Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6: (89 commits)
bonding: documentation and code cleanup for resend_igmp
bonding: prevent deadlock on slave store with alb mode (v3)
net: hold rtnl again in dump callbacks
Add Fujitsu 1000base-SX PCI ID to tg3
bnx2x: protect sequence increment with mutex
sch_sfq: fix peek() implementation
isdn: netjet - blacklist Digium TDM400P
via-velocity: don't annotate MAC registers as packed
xen: netfront: hold RTNL when updating features.
sctp: fix memory leak of the ASCONF queue when free asoc
net: make dev_disable_lro use physical device if passed a vlan dev (v2)
net: move is_vlan_dev into public header file (v2)
bug.h: Fix build with CONFIG_PRINTK disabled.
wireless: fix fatal kernel-doc error + warning in mac80211.h
wireless: fix cfg80211.h new kernel-doc warnings
iwlagn: dbg_fixed_rate only used when CONFIG_MAC80211_DEBUGFS enabled
dst: catch uninitialized metrics
be2net: hash key for rss-config cmd not set
bridge: initialize fake_rtable metrics
net: fix __dst_destroy_metrics_generic()
...
Fix up trivial conflicts in drivers/staging/brcm80211/brcmfmac/wl_cfg80211.c
diff --git a/.gitignore b/.gitignore
index 5d56a3f..9dacde0 100644
--- a/.gitignore
+++ b/.gitignore
@@ -57,6 +57,7 @@
include/config
include/linux/version.h
include/generated
+arch/*/include/generated
# stgit generated dirs
patches-*
diff --git a/.mailmap b/.mailmap
index 5a6dd59..353ad56 100644
--- a/.mailmap
+++ b/.mailmap
@@ -32,6 +32,7 @@
Brian King <brking@us.ibm.com>
Christoph Hellwig <hch@lst.de>
Corey Minyard <minyard@acm.org>
+Damian Hobson-Garcia <dhobsong@igel.co.jp>
David Brownell <david-b@pacbell.net>
David Woodhouse <dwmw2@shinybook.infradead.org>
Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
diff --git a/CREDITS b/CREDITS
index 95c469c..a7ea8e3 100644
--- a/CREDITS
+++ b/CREDITS
@@ -2943,6 +2943,10 @@
S: 70110 Kuopio
S: Finland
+N: Tobias Ringström
+E: tori@unhappy.mine.nu
+D: Davicom DM9102(A)/DM9132/DM9801 fast ethernet driver
+
N: Luca Risolia
E: luca.risolia@studio.unibo.it
P: 1024D/FCE635A4 88E8 F32F 7244 68BA 3958 5D40 99DA 5D2A FCE6 35A4
@@ -3913,6 +3917,10 @@
S: D-73732 Esslingen
S: Germany
+N: Roman Zippel
+E: zippel@linux-m68k.org
+D: AFFS and HFS filesystems, m68k maintainer, new kernel configuration in 2.5
+
N: Leonard N. Zubkoff
W: http://www.dandelion.com/Linux/
D: BusLogic SCSI driver
diff --git a/Documentation/ABI/testing/sysfs-block b/Documentation/ABI/testing/sysfs-block
index 4873c75..c1eb41c 100644
--- a/Documentation/ABI/testing/sysfs-block
+++ b/Documentation/ABI/testing/sysfs-block
@@ -142,3 +142,67 @@
with the previous I/O request are enabled. When set to 2,
all merge tries are disabled. The default value is 0 -
which enables all types of merge tries.
+
+What: /sys/block/<disk>/discard_alignment
+Date: May 2011
+Contact: Martin K. Petersen <martin.petersen@oracle.com>
+Description:
+ Devices that support discard functionality may
+ internally allocate space in units that are bigger than
+ the exported logical block size. The discard_alignment
+ parameter indicates how many bytes the beginning of the
+ device is offset from the internal allocation unit's
+ natural alignment.
+
+What: /sys/block/<disk>/<partition>/discard_alignment
+Date: May 2011
+Contact: Martin K. Petersen <martin.petersen@oracle.com>
+Description:
+ Devices that support discard functionality may
+ internally allocate space in units that are bigger than
+ the exported logical block size. The discard_alignment
+ parameter indicates how many bytes the beginning of the
+ partition is offset from the internal allocation unit's
+ natural alignment.
+
+What: /sys/block/<disk>/queue/discard_granularity
+Date: May 2011
+Contact: Martin K. Petersen <martin.petersen@oracle.com>
+Description:
+ Devices that support discard functionality may
+ internally allocate space using units that are bigger
+ than the logical block size. The discard_granularity
+ parameter indicates the size of the internal allocation
+ unit in bytes if reported by the device. Otherwise the
+ discard_granularity will be set to match the device's
+ physical block size. A discard_granularity of 0 means
+ that the device does not support discard functionality.
+
+What: /sys/block/<disk>/queue/discard_max_bytes
+Date: May 2011
+Contact: Martin K. Petersen <martin.petersen@oracle.com>
+Description:
+ Devices that support discard functionality may have
+ internal limits on the number of bytes that can be
+ trimmed or unmapped in a single operation. Some storage
+ protocols also have inherent limits on the number of
+ blocks that can be described in a single command. The
+ discard_max_bytes parameter is set by the device driver
+ to the maximum number of bytes that can be discarded in
+ a single operation. Discard requests issued to the
+ device must not exceed this limit. A discard_max_bytes
+ value of 0 means that the device does not support
+ discard functionality.
+
+What: /sys/block/<disk>/queue/discard_zeroes_data
+Date: May 2011
+Contact: Martin K. Petersen <martin.petersen@oracle.com>
+Description:
+ Devices that support discard functionality may return
+ stale or random data when a previously discarded block
+ is read back. This can cause problems if the filesystem
+ expects discarded blocks to be explicitly cleared. If a
+ device reports that it deterministically returns zeroes
+ when a discarded area is read the discard_zeroes_data
+ parameter will be set to one. Otherwise it will be 0 and
+ the result of reading a discarded area is undefined.
diff --git a/Documentation/ABI/testing/sysfs-bus-pci b/Documentation/ABI/testing/sysfs-bus-pci
index 36bf454..349ecf2 100644
--- a/Documentation/ABI/testing/sysfs-bus-pci
+++ b/Documentation/ABI/testing/sysfs-bus-pci
@@ -74,6 +74,15 @@
hot-remove the PCI device and any of its children.
Depends on CONFIG_HOTPLUG.
+What: /sys/bus/pci/devices/.../pci_bus/.../rescan
+Date: May 2011
+Contact: Linux PCI developers <linux-pci@vger.kernel.org>
+Description:
+ Writing a non-zero value to this attribute will
+ force a rescan of the bus and all child buses,
+ and re-discover devices removed earlier from this
+ part of the device tree. Depends on CONFIG_HOTPLUG.
+
What: /sys/bus/pci/devices/.../rescan
Date: January 2009
Contact: Linux PCI developers <linux-pci@vger.kernel.org>
diff --git a/Documentation/ABI/testing/sysfs-ptp b/Documentation/ABI/testing/sysfs-ptp
new file mode 100644
index 0000000..d40d2b5
--- /dev/null
+++ b/Documentation/ABI/testing/sysfs-ptp
@@ -0,0 +1,98 @@
+What: /sys/class/ptp/
+Date: September 2010
+Contact: Richard Cochran <richardcochran@gmail.com>
+Description:
+ This directory contains files and directories
+ providing a standardized interface to the ancillary
+ features of PTP hardware clocks.
+
+What: /sys/class/ptp/ptpN/
+Date: September 2010
+Contact: Richard Cochran <richardcochran@gmail.com>
+Description:
+ This directory contains the attributes of the Nth PTP
+ hardware clock registered into the PTP class driver
+ subsystem.
+
+What: /sys/class/ptp/ptpN/clock_name
+Date: September 2010
+Contact: Richard Cochran <richardcochran@gmail.com>
+Description:
+ This file contains the name of the PTP hardware clock
+ as a human readable string.
+
+What: /sys/class/ptp/ptpN/max_adjustment
+Date: September 2010
+Contact: Richard Cochran <richardcochran@gmail.com>
+Description:
+ This file contains the PTP hardware clock's maximum
+ frequency adjustment value (a positive integer) in
+ parts per billion.
+
+What: /sys/class/ptp/ptpN/n_alarms
+Date: September 2010
+Contact: Richard Cochran <richardcochran@gmail.com>
+Description:
+ This file contains the number of periodic or one shot
+ alarms offer by the PTP hardware clock.
+
+What: /sys/class/ptp/ptpN/n_external_timestamps
+Date: September 2010
+Contact: Richard Cochran <richardcochran@gmail.com>
+Description:
+ This file contains the number of external timestamp
+ channels offered by the PTP hardware clock.
+
+What: /sys/class/ptp/ptpN/n_periodic_outputs
+Date: September 2010
+Contact: Richard Cochran <richardcochran@gmail.com>
+Description:
+ This file contains the number of programmable periodic
+ output channels offered by the PTP hardware clock.
+
+What: /sys/class/ptp/ptpN/pps_avaiable
+Date: September 2010
+Contact: Richard Cochran <richardcochran@gmail.com>
+Description:
+ This file indicates whether the PTP hardware clock
+ supports a Pulse Per Second to the host CPU. Reading
+ "1" means that the PPS is supported, while "0" means
+ not supported.
+
+What: /sys/class/ptp/ptpN/extts_enable
+Date: September 2010
+Contact: Richard Cochran <richardcochran@gmail.com>
+Description:
+ This write-only file enables or disables external
+ timestamps. To enable external timestamps, write the
+ channel index followed by a "1" into the file.
+ To disable external timestamps, write the channel
+ index followed by a "0" into the file.
+
+What: /sys/class/ptp/ptpN/fifo
+Date: September 2010
+Contact: Richard Cochran <richardcochran@gmail.com>
+Description:
+ This file provides timestamps on external events, in
+ the form of three integers: channel index, seconds,
+ and nanoseconds.
+
+What: /sys/class/ptp/ptpN/period
+Date: September 2010
+Contact: Richard Cochran <richardcochran@gmail.com>
+Description:
+ This write-only file enables or disables periodic
+ outputs. To enable a periodic output, write five
+ integers into the file: channel index, start time
+ seconds, start time nanoseconds, period seconds, and
+ period nanoseconds. To disable a periodic output, set
+ all the seconds and nanoseconds values to zero.
+
+What: /sys/class/ptp/ptpN/pps_enable
+Date: September 2010
+Contact: Richard Cochran <richardcochran@gmail.com>
+Description:
+ This write-only file enables or disables delivery of
+ PPS events to the Linux PPS subsystem. To enable PPS
+ events, write a "1" into the file. To disable events,
+ write a "0" into the file.
diff --git a/Documentation/DocBook/.gitignore b/Documentation/DocBook/.gitignore
index c6def35..679034c 100644
--- a/Documentation/DocBook/.gitignore
+++ b/Documentation/DocBook/.gitignore
@@ -8,3 +8,4 @@
*.dvi
*.log
*.out
+media/
diff --git a/Documentation/DocBook/Makefile b/Documentation/DocBook/Makefile
index 8436b01..3cebfa0 100644
--- a/Documentation/DocBook/Makefile
+++ b/Documentation/DocBook/Makefile
@@ -73,7 +73,7 @@
###
#External programs used
KERNELDOC = $(srctree)/scripts/kernel-doc
-DOCPROC = $(objtree)/scripts/basic/docproc
+DOCPROC = $(objtree)/scripts/docproc
XMLTOFLAGS = -m $(srctree)/Documentation/DocBook/stylesheet.xsl
XMLTOFLAGS += --skip-validation
diff --git a/Documentation/DocBook/dvb/dvbapi.xml b/Documentation/DocBook/dvb/dvbapi.xml
index ad8678d..9fad86c 100644
--- a/Documentation/DocBook/dvb/dvbapi.xml
+++ b/Documentation/DocBook/dvb/dvbapi.xml
@@ -35,6 +35,14 @@
<revhistory>
<!-- Put document revisions here, newest first. -->
<revision>
+ <revnumber>2.0.4</revnumber>
+ <date>2011-05-06</date>
+ <authorinitials>mcc</authorinitials>
+ <revremark>
+ Add more information about DVB APIv5, better describing the frontend GET/SET props ioctl's.
+ </revremark>
+</revision>
+<revision>
<revnumber>2.0.3</revnumber>
<date>2010-07-03</date>
<authorinitials>mcc</authorinitials>
diff --git a/Documentation/DocBook/dvb/dvbproperty.xml b/Documentation/DocBook/dvb/dvbproperty.xml
index 97f397e..52d5e3c 100644
--- a/Documentation/DocBook/dvb/dvbproperty.xml
+++ b/Documentation/DocBook/dvb/dvbproperty.xml
@@ -1,6 +1,327 @@
-<section id="FE_GET_PROPERTY">
+<section id="FE_GET_SET_PROPERTY">
<title>FE_GET_PROPERTY/FE_SET_PROPERTY</title>
+<programlisting>
+/* Reserved fields should be set to 0 */
+struct dtv_property {
+ __u32 cmd;
+ union {
+ __u32 data;
+ struct {
+ __u8 data[32];
+ __u32 len;
+ __u32 reserved1[3];
+ void *reserved2;
+ } buffer;
+ } u;
+ int result;
+} __attribute__ ((packed));
+
+/* num of properties cannot exceed DTV_IOCTL_MAX_MSGS per ioctl */
+#define DTV_IOCTL_MAX_MSGS 64
+
+struct dtv_properties {
+ __u32 num;
+ struct dtv_property *props;
+};
+</programlisting>
+
+<section id="FE_GET_PROPERTY">
+<title>FE_GET_PROPERTY</title>
+<para>DESCRIPTION
+</para>
+<informaltable><tgroup cols="1"><tbody><row><entry
+ align="char">
+<para>This ioctl call returns one or more frontend properties. This call only
+ requires read-only access to the device.</para>
+</entry>
+ </row></tbody></tgroup></informaltable>
+<para>SYNOPSIS
+</para>
+<informaltable><tgroup cols="1"><tbody><row><entry
+ align="char">
+<para>int ioctl(int fd, int request = <link linkend="FE_GET_PROPERTY">FE_GET_PROPERTY</link>,
+ dtv_properties ⋆props);</para>
+</entry>
+ </row></tbody></tgroup></informaltable>
+<para>PARAMETERS
+</para>
+<informaltable><tgroup cols="2"><tbody><row><entry align="char">
+<para>int fd</para>
+</entry><entry
+ align="char">
+<para>File descriptor returned by a previous call to open().</para>
+</entry>
+ </row><row><entry
+ align="char">
+<para>int num</para>
+</entry><entry
+ align="char">
+<para>Equals <link linkend="FE_GET_PROPERTY">FE_GET_PROPERTY</link> for this command.</para>
+</entry>
+ </row><row><entry
+ align="char">
+<para>struct dtv_property *props</para>
+</entry><entry
+ align="char">
+<para>Points to the location where the front-end property commands are stored.</para>
+</entry>
+ </row></tbody></tgroup></informaltable>
+<para>ERRORS</para>
+<informaltable><tgroup cols="2"><tbody><row>
+ <entry align="char"><para>EINVAL</para></entry>
+ <entry align="char"><para>Invalid parameter(s) received or number of parameters out of the range.</para></entry>
+ </row><row>
+ <entry align="char"><para>ENOMEM</para></entry>
+ <entry align="char"><para>Out of memory.</para></entry>
+ </row><row>
+ <entry align="char"><para>EFAULT</para></entry>
+ <entry align="char"><para>Failure while copying data from/to userspace.</para></entry>
+ </row><row>
+ <entry align="char"><para>EOPNOTSUPP</para></entry>
+ <entry align="char"><para>Property type not supported.</para></entry>
+ </row></tbody></tgroup></informaltable>
+</section>
+
+<section id="FE_SET_PROPERTY">
+<title>FE_SET_PROPERTY</title>
+<para>DESCRIPTION
+</para>
+<informaltable><tgroup cols="1"><tbody><row><entry
+ align="char">
+<para>This ioctl call sets one or more frontend properties. This call only
+ requires read-only access to the device.</para>
+</entry>
+ </row></tbody></tgroup></informaltable>
+<para>SYNOPSIS
+</para>
+<informaltable><tgroup cols="1"><tbody><row><entry
+ align="char">
+<para>int ioctl(int fd, int request = <link linkend="FE_SET_PROPERTY">FE_SET_PROPERTY</link>,
+ dtv_properties ⋆props);</para>
+</entry>
+ </row></tbody></tgroup></informaltable>
+<para>PARAMETERS
+</para>
+<informaltable><tgroup cols="2"><tbody><row><entry align="char">
+<para>int fd</para>
+</entry><entry
+ align="char">
+<para>File descriptor returned by a previous call to open().</para>
+</entry>
+ </row><row><entry
+ align="char">
+<para>int num</para>
+</entry><entry
+ align="char">
+<para>Equals <link linkend="FE_SET_PROPERTY">FE_SET_PROPERTY</link> for this command.</para>
+</entry>
+ </row><row><entry
+ align="char">
+<para>struct dtv_property *props</para>
+</entry><entry
+ align="char">
+<para>Points to the location where the front-end property commands are stored.</para>
+</entry>
+ </row></tbody></tgroup></informaltable>
+<para>ERRORS
+</para>
+<informaltable><tgroup cols="2"><tbody><row>
+ <entry align="char"><para>EINVAL</para></entry>
+ <entry align="char"><para>Invalid parameter(s) received or number of parameters out of the range.</para></entry>
+ </row><row>
+ <entry align="char"><para>ENOMEM</para></entry>
+ <entry align="char"><para>Out of memory.</para></entry>
+ </row><row>
+ <entry align="char"><para>EFAULT</para></entry>
+ <entry align="char"><para>Failure while copying data from/to userspace.</para></entry>
+ </row><row>
+ <entry align="char"><para>EOPNOTSUPP</para></entry>
+ <entry align="char"><para>Property type not supported.</para></entry>
+ </row></tbody></tgroup></informaltable>
+</section>
+
+<para>
+On <link linkend="FE_GET_PROPERTY">FE_GET_PROPERTY</link>/<link linkend="FE_SET_PROPERTY">FE_SET_PROPERTY</link>,
+the actual action is determined by the dtv_property cmd/data pairs. With one single ioctl, is possible to
+get/set up to 64 properties. The actual meaning of each property is described on the next sections.
+</para>
+
+<para>The Available frontend property types are:</para>
+<programlisting>
+#define DTV_UNDEFINED 0
+#define DTV_TUNE 1
+#define DTV_CLEAR 2
+#define DTV_FREQUENCY 3
+#define DTV_MODULATION 4
+#define DTV_BANDWIDTH_HZ 5
+#define DTV_INVERSION 6
+#define DTV_DISEQC_MASTER 7
+#define DTV_SYMBOL_RATE 8
+#define DTV_INNER_FEC 9
+#define DTV_VOLTAGE 10
+#define DTV_TONE 11
+#define DTV_PILOT 12
+#define DTV_ROLLOFF 13
+#define DTV_DISEQC_SLAVE_REPLY 14
+#define DTV_FE_CAPABILITY_COUNT 15
+#define DTV_FE_CAPABILITY 16
+#define DTV_DELIVERY_SYSTEM 17
+#define DTV_ISDBT_PARTIAL_RECEPTION 18
+#define DTV_ISDBT_SOUND_BROADCASTING 19
+#define DTV_ISDBT_SB_SUBCHANNEL_ID 20
+#define DTV_ISDBT_SB_SEGMENT_IDX 21
+#define DTV_ISDBT_SB_SEGMENT_COUNT 22
+#define DTV_ISDBT_LAYERA_FEC 23
+#define DTV_ISDBT_LAYERA_MODULATION 24
+#define DTV_ISDBT_LAYERA_SEGMENT_COUNT 25
+#define DTV_ISDBT_LAYERA_TIME_INTERLEAVING 26
+#define DTV_ISDBT_LAYERB_FEC 27
+#define DTV_ISDBT_LAYERB_MODULATION 28
+#define DTV_ISDBT_LAYERB_SEGMENT_COUNT 29
+#define DTV_ISDBT_LAYERB_TIME_INTERLEAVING 30
+#define DTV_ISDBT_LAYERC_FEC 31
+#define DTV_ISDBT_LAYERC_MODULATION 32
+#define DTV_ISDBT_LAYERC_SEGMENT_COUNT 33
+#define DTV_ISDBT_LAYERC_TIME_INTERLEAVING 34
+#define DTV_API_VERSION 35
+#define DTV_CODE_RATE_HP 36
+#define DTV_CODE_RATE_LP 37
+#define DTV_GUARD_INTERVAL 38
+#define DTV_TRANSMISSION_MODE 39
+#define DTV_HIERARCHY 40
+#define DTV_ISDBT_LAYER_ENABLED 41
+#define DTV_ISDBS_TS_ID 42
+</programlisting>
+
+<section id="fe_property_common">
+ <title>Parameters that are common to all Digital TV standards</title>
+ <section id="DTV_FREQUENCY">
+ <title><constant>DTV_FREQUENCY</constant></title>
+
+ <para>Central frequency of the channel, in HZ.</para>
+
+ <para>Notes:</para>
+ <para>1)For ISDB-T, the channels are usually transmitted with an offset of 143kHz.
+ E.g. a valid frequncy could be 474143 kHz. The stepping is bound to the bandwidth of
+ the channel which is 6MHz.</para>
+
+ <para>2)As in ISDB-Tsb the channel consists of only one or three segments the
+ frequency step is 429kHz, 3*429 respectively. As for ISDB-T the
+ central frequency of the channel is expected.</para>
+ </section>
+
+ <section id="DTV_BANDWIDTH_HZ">
+ <title><constant>DTV_BANDWIDTH_HZ</constant></title>
+
+ <para>Bandwidth for the channel, in HZ.</para>
+
+ <para>Possible values:
+ <constant>1712000</constant>,
+ <constant>5000000</constant>,
+ <constant>6000000</constant>,
+ <constant>7000000</constant>,
+ <constant>8000000</constant>,
+ <constant>10000000</constant>.
+ </para>
+
+ <para>Notes:</para>
+
+ <para>1) For ISDB-T it should be always 6000000Hz (6MHz)</para>
+ <para>2) For ISDB-Tsb it can vary depending on the number of connected segments</para>
+ <para>3) Bandwidth doesn't apply for DVB-C transmissions, as the bandwidth
+ for DVB-C depends on the symbol rate</para>
+ <para>4) Bandwidth in ISDB-T is fixed (6MHz) or can be easily derived from
+ other parameters (DTV_ISDBT_SB_SEGMENT_IDX,
+ DTV_ISDBT_SB_SEGMENT_COUNT).</para>
+ <para>5) DVB-T supports 6, 7 and 8MHz.</para>
+ <para>6) In addition, DVB-T2 supports 1.172, 5 and 10MHz.</para>
+ </section>
+
+ <section id="DTV_DELIVERY_SYSTEM">
+ <title><constant>DTV_DELIVERY_SYSTEM</constant></title>
+
+ <para>Specifies the type of Delivery system</para>
+
+ <para>Possible values: </para>
+<programlisting>
+typedef enum fe_delivery_system {
+ SYS_UNDEFINED,
+ SYS_DVBC_ANNEX_AC,
+ SYS_DVBC_ANNEX_B,
+ SYS_DVBT,
+ SYS_DSS,
+ SYS_DVBS,
+ SYS_DVBS2,
+ SYS_DVBH,
+ SYS_ISDBT,
+ SYS_ISDBS,
+ SYS_ISDBC,
+ SYS_ATSC,
+ SYS_ATSCMH,
+ SYS_DMBTH,
+ SYS_CMMB,
+ SYS_DAB,
+ SYS_DVBT2,
+} fe_delivery_system_t;
+</programlisting>
+
+ </section>
+
+ <section id="DTV_TRANSMISSION_MODE">
+ <title><constant>DTV_TRANSMISSION_MODE</constant></title>
+
+ <para>Specifies the number of carriers used by the standard</para>
+
+ <para>Possible values are:</para>
+<programlisting>
+typedef enum fe_transmit_mode {
+ TRANSMISSION_MODE_2K,
+ TRANSMISSION_MODE_8K,
+ TRANSMISSION_MODE_AUTO,
+ TRANSMISSION_MODE_4K,
+ TRANSMISSION_MODE_1K,
+ TRANSMISSION_MODE_16K,
+ TRANSMISSION_MODE_32K,
+} fe_transmit_mode_t;
+</programlisting>
+
+ <para>Notes:</para>
+ <para>1) ISDB-T supports three carrier/symbol-size: 8K, 4K, 2K. It is called
+ 'mode' in the standard: Mode 1 is 2K, mode 2 is 4K, mode 3 is 8K</para>
+
+ <para>2) If <constant>DTV_TRANSMISSION_MODE</constant> is set the <constant>TRANSMISSION_MODE_AUTO</constant> the
+ hardware will try to find the correct FFT-size (if capable) and will
+ use TMCC to fill in the missing parameters.</para>
+ <para>3) DVB-T specifies 2K and 8K as valid sizes.</para>
+ <para>4) DVB-T2 specifies 1K, 2K, 4K, 8K, 16K and 32K.</para>
+ </section>
+
+ <section id="DTV_GUARD_INTERVAL">
+ <title><constant>DTV_GUARD_INTERVAL</constant></title>
+
+ <para>Possible values are:</para>
+<programlisting>
+typedef enum fe_guard_interval {
+ GUARD_INTERVAL_1_32,
+ GUARD_INTERVAL_1_16,
+ GUARD_INTERVAL_1_8,
+ GUARD_INTERVAL_1_4,
+ GUARD_INTERVAL_AUTO,
+ GUARD_INTERVAL_1_128,
+ GUARD_INTERVAL_19_128,
+ GUARD_INTERVAL_19_256,
+} fe_guard_interval_t;
+</programlisting>
+
+ <para>Notes:</para>
+ <para>1) If <constant>DTV_GUARD_INTERVAL</constant> is set the <constant>GUARD_INTERVAL_AUTO</constant> the hardware will
+ try to find the correct guard interval (if capable) and will use TMCC to fill
+ in the missing parameters.</para>
+ <para>2) Intervals 1/128, 19/128 and 19/256 are used only for DVB-T2 at present</para>
+ </section>
+</section>
+
<section id="isdbt">
<title>ISDB-T frontend</title>
<para>This section describes shortly what are the possible parameters in the Linux
@@ -32,73 +353,6 @@
<para>Parameters used by ISDB-T and ISDB-Tsb.</para>
- <section id="isdbt-parms">
- <title>Parameters that are common with DVB-T and ATSC</title>
-
- <section id="isdbt-freq">
- <title><constant>DTV_FREQUENCY</constant></title>
-
- <para>Central frequency of the channel.</para>
-
- <para>For ISDB-T the channels are usually transmitted with an offset of 143kHz. E.g. a
- valid frequncy could be 474143 kHz. The stepping is bound to the bandwidth of
- the channel which is 6MHz.</para>
-
- <para>As in ISDB-Tsb the channel consists of only one or three segments the
- frequency step is 429kHz, 3*429 respectively. As for ISDB-T the
- central frequency of the channel is expected.</para>
- </section>
-
- <section id="isdbt-bw">
- <title><constant>DTV_BANDWIDTH_HZ</constant> (optional)</title>
-
- <para>Possible values:</para>
-
- <para>For ISDB-T it should be always 6000000Hz (6MHz)</para>
- <para>For ISDB-Tsb it can vary depending on the number of connected segments</para>
-
- <para>Note: Hardware specific values might be given here, but standard
- applications should not bother to set a value to this field as
- standard demods are ignoring it anyway.</para>
-
- <para>Bandwidth in ISDB-T is fixed (6MHz) or can be easily derived from
- other parameters (DTV_ISDBT_SB_SEGMENT_IDX,
- DTV_ISDBT_SB_SEGMENT_COUNT).</para>
- </section>
-
- <section id="isdbt-delivery-sys">
- <title><constant>DTV_DELIVERY_SYSTEM</constant></title>
-
- <para>Possible values: <constant>SYS_ISDBT</constant></para>
- </section>
-
- <section id="isdbt-tx-mode">
- <title><constant>DTV_TRANSMISSION_MODE</constant></title>
-
- <para>ISDB-T supports three carrier/symbol-size: 8K, 4K, 2K. It is called
- 'mode' in the standard: Mode 1 is 2K, mode 2 is 4K, mode 3 is 8K</para>
-
- <para>Possible values: <constant>TRANSMISSION_MODE_2K</constant>, <constant>TRANSMISSION_MODE_8K</constant>,
- <constant>TRANSMISSION_MODE_AUTO</constant>, <constant>TRANSMISSION_MODE_4K</constant></para>
-
- <para>If <constant>DTV_TRANSMISSION_MODE</constant> is set the <constant>TRANSMISSION_MODE_AUTO</constant> the
- hardware will try to find the correct FFT-size (if capable) and will
- use TMCC to fill in the missing parameters.</para>
-
- <para><constant>TRANSMISSION_MODE_4K</constant> is added at the same time as the other new parameters.</para>
- </section>
-
- <section id="isdbt-guard-interval">
- <title><constant>DTV_GUARD_INTERVAL</constant></title>
-
- <para>Possible values: <constant>GUARD_INTERVAL_1_32</constant>, <constant>GUARD_INTERVAL_1_16</constant>, <constant>GUARD_INTERVAL_1_8</constant>,
- <constant>GUARD_INTERVAL_1_4</constant>, <constant>GUARD_INTERVAL_AUTO</constant></para>
-
- <para>If <constant>DTV_GUARD_INTERVAL</constant> is set the <constant>GUARD_INTERVAL_AUTO</constant> the hardware will
- try to find the correct guard interval (if capable) and will use TMCC to fill
- in the missing parameters.</para>
- </section>
- </section>
<section id="isdbt-new-parms">
<title>ISDB-T only parameters</title>
@@ -314,5 +568,20 @@
</section>
</section>
</section>
+ <section id="dvbt2-params">
+ <title>DVB-T2 parameters</title>
+
+ <para>This section covers parameters that apply only to the DVB-T2 delivery method. DVB-T2
+ support is currently in the early stages development so expect this section to grow
+ and become more detailed with time.</para>
+
+ <section id="dvbt2-plp-id">
+ <title><constant>DTV_DVBT2_PLP_ID</constant></title>
+
+ <para>DVB-T2 supports Physical Layer Pipes (PLP) to allow transmission of
+ many data types via a single multiplex. The API will soon support this
+ at which point this section will be expanded.</para>
+ </section>
+ </section>
</section>
</section>
diff --git a/Documentation/DocBook/dvb/frontend.h.xml b/Documentation/DocBook/dvb/frontend.h.xml
index d08e0d4..d792f78 100644
--- a/Documentation/DocBook/dvb/frontend.h.xml
+++ b/Documentation/DocBook/dvb/frontend.h.xml
@@ -176,14 +176,20 @@
TRANSMISSION_MODE_2K,
TRANSMISSION_MODE_8K,
TRANSMISSION_MODE_AUTO,
- TRANSMISSION_MODE_4K
+ TRANSMISSION_MODE_4K,
+ TRANSMISSION_MODE_1K,
+ TRANSMISSION_MODE_16K,
+ TRANSMISSION_MODE_32K,
} fe_transmit_mode_t;
typedef enum fe_bandwidth {
BANDWIDTH_8_MHZ,
BANDWIDTH_7_MHZ,
BANDWIDTH_6_MHZ,
- BANDWIDTH_AUTO
+ BANDWIDTH_AUTO,
+ BANDWIDTH_5_MHZ,
+ BANDWIDTH_10_MHZ,
+ BANDWIDTH_1_712_MHZ,
} fe_bandwidth_t;
@@ -192,7 +198,10 @@
GUARD_INTERVAL_1_16,
GUARD_INTERVAL_1_8,
GUARD_INTERVAL_1_4,
- GUARD_INTERVAL_AUTO
+ GUARD_INTERVAL_AUTO,
+ GUARD_INTERVAL_1_128,
+ GUARD_INTERVAL_19_128,
+ GUARD_INTERVAL_19_256,
} fe_guard_interval_t;
@@ -306,7 +315,9 @@
#define DTV_ISDBS_TS_ID 42
-#define DTV_MAX_COMMAND DTV_ISDBS_TS_ID
+#define DTV_DVBT2_PLP_ID 43
+
+#define DTV_MAX_COMMAND DTV_DVBT2_PLP_ID
typedef enum fe_pilot {
PILOT_ON,
@@ -338,6 +349,7 @@
SYS_DMBTH,
SYS_CMMB,
SYS_DAB,
+ SYS_DVBT2,
} fe_delivery_system_t;
struct dtv_cmds_h {
diff --git a/Documentation/DocBook/media-entities.tmpl b/Documentation/DocBook/media-entities.tmpl
index fea63b4..c8abb23 100644
--- a/Documentation/DocBook/media-entities.tmpl
+++ b/Documentation/DocBook/media-entities.tmpl
@@ -270,6 +270,7 @@
<!ENTITY sub-write SYSTEM "v4l/func-write.xml">
<!ENTITY sub-io SYSTEM "v4l/io.xml">
<!ENTITY sub-grey SYSTEM "v4l/pixfmt-grey.xml">
+<!ENTITY sub-m420 SYSTEM "v4l/pixfmt-m420.xml">
<!ENTITY sub-nv12 SYSTEM "v4l/pixfmt-nv12.xml">
<!ENTITY sub-nv12m SYSTEM "v4l/pixfmt-nv12m.xml">
<!ENTITY sub-nv12mt SYSTEM "v4l/pixfmt-nv12mt.xml">
@@ -295,6 +296,7 @@
<!ENTITY sub-srggb8 SYSTEM "v4l/pixfmt-srggb8.xml">
<!ENTITY sub-y10 SYSTEM "v4l/pixfmt-y10.xml">
<!ENTITY sub-y12 SYSTEM "v4l/pixfmt-y12.xml">
+<!ENTITY sub-y10b SYSTEM "v4l/pixfmt-y10b.xml">
<!ENTITY sub-pixfmt SYSTEM "v4l/pixfmt.xml">
<!ENTITY sub-cropcap SYSTEM "v4l/vidioc-cropcap.xml">
<!ENTITY sub-dbg-g-register SYSTEM "v4l/vidioc-dbg-g-register.xml">
diff --git a/Documentation/DocBook/v4l/pixfmt-m420.xml b/Documentation/DocBook/v4l/pixfmt-m420.xml
new file mode 100644
index 0000000..ce4bc019
--- /dev/null
+++ b/Documentation/DocBook/v4l/pixfmt-m420.xml
@@ -0,0 +1,147 @@
+ <refentry id="V4L2-PIX-FMT-M420">
+ <refmeta>
+ <refentrytitle>V4L2_PIX_FMT_M420 ('M420')</refentrytitle>
+ &manvol;
+ </refmeta>
+ <refnamediv>
+ <refname><constant>V4L2_PIX_FMT_M420</constant></refname>
+ <refpurpose>Format with ½ horizontal and vertical chroma
+ resolution, also known as YUV 4:2:0. Hybrid plane line-interleaved
+ layout.</refpurpose>
+ </refnamediv>
+ <refsect1>
+ <title>Description</title>
+
+ <para>M420 is a YUV format with ½ horizontal and vertical chroma
+ subsampling (YUV 4:2:0). Pixels are organized as interleaved luma and
+ chroma planes. Two lines of luma data are followed by one line of chroma
+ data.</para>
+ <para>The luma plane has one byte per pixel. The chroma plane contains
+ interleaved CbCr pixels subsampled by ½ in the horizontal and
+ vertical directions. Each CbCr pair belongs to four pixels. For example,
+Cb<subscript>0</subscript>/Cr<subscript>0</subscript> belongs to
+Y'<subscript>00</subscript>, Y'<subscript>01</subscript>,
+Y'<subscript>10</subscript>, Y'<subscript>11</subscript>.</para>
+
+ <para>All line lengths are identical: if the Y lines include pad bytes
+ so do the CbCr lines.</para>
+
+ <example>
+ <title><constant>V4L2_PIX_FMT_M420</constant> 4 × 4
+pixel image</title>
+
+ <formalpara>
+ <title>Byte Order.</title>
+ <para>Each cell is one byte.
+ <informaltable frame="none">
+ <tgroup cols="5" align="center">
+ <colspec align="left" colwidth="2*" />
+ <tbody valign="top">
+ <row>
+ <entry>start + 0:</entry>
+ <entry>Y'<subscript>00</subscript></entry>
+ <entry>Y'<subscript>01</subscript></entry>
+ <entry>Y'<subscript>02</subscript></entry>
+ <entry>Y'<subscript>03</subscript></entry>
+ </row>
+ <row>
+ <entry>start + 4:</entry>
+ <entry>Y'<subscript>10</subscript></entry>
+ <entry>Y'<subscript>11</subscript></entry>
+ <entry>Y'<subscript>12</subscript></entry>
+ <entry>Y'<subscript>13</subscript></entry>
+ </row>
+ <row>
+ <entry>start + 8:</entry>
+ <entry>Cb<subscript>00</subscript></entry>
+ <entry>Cr<subscript>00</subscript></entry>
+ <entry>Cb<subscript>01</subscript></entry>
+ <entry>Cr<subscript>01</subscript></entry>
+ </row>
+ <row>
+ <entry>start + 16:</entry>
+ <entry>Y'<subscript>20</subscript></entry>
+ <entry>Y'<subscript>21</subscript></entry>
+ <entry>Y'<subscript>22</subscript></entry>
+ <entry>Y'<subscript>23</subscript></entry>
+ </row>
+ <row>
+ <entry>start + 20:</entry>
+ <entry>Y'<subscript>30</subscript></entry>
+ <entry>Y'<subscript>31</subscript></entry>
+ <entry>Y'<subscript>32</subscript></entry>
+ <entry>Y'<subscript>33</subscript></entry>
+ </row>
+ <row>
+ <entry>start + 24:</entry>
+ <entry>Cb<subscript>10</subscript></entry>
+ <entry>Cr<subscript>10</subscript></entry>
+ <entry>Cb<subscript>11</subscript></entry>
+ <entry>Cr<subscript>11</subscript></entry>
+ </row>
+ </tbody>
+ </tgroup>
+ </informaltable>
+ </para>
+ </formalpara>
+
+ <formalpara>
+ <title>Color Sample Location.</title>
+ <para>
+ <informaltable frame="none">
+ <tgroup cols="7" align="center">
+ <tbody valign="top">
+ <row>
+ <entry></entry>
+ <entry>0</entry><entry></entry><entry>1</entry><entry></entry>
+ <entry>2</entry><entry></entry><entry>3</entry>
+ </row>
+ <row>
+ <entry>0</entry>
+ <entry>Y</entry><entry></entry><entry>Y</entry><entry></entry>
+ <entry>Y</entry><entry></entry><entry>Y</entry>
+ </row>
+ <row>
+ <entry></entry>
+ <entry></entry><entry>C</entry><entry></entry><entry></entry>
+ <entry></entry><entry>C</entry><entry></entry>
+ </row>
+ <row>
+ <entry>1</entry>
+ <entry>Y</entry><entry></entry><entry>Y</entry><entry></entry>
+ <entry>Y</entry><entry></entry><entry>Y</entry>
+ </row>
+ <row>
+ <entry></entry>
+ </row>
+ <row>
+ <entry>2</entry>
+ <entry>Y</entry><entry></entry><entry>Y</entry><entry></entry>
+ <entry>Y</entry><entry></entry><entry>Y</entry>
+ </row>
+ <row>
+ <entry></entry>
+ <entry></entry><entry>C</entry><entry></entry><entry></entry>
+ <entry></entry><entry>C</entry><entry></entry>
+ </row>
+ <row>
+ <entry>3</entry>
+ <entry>Y</entry><entry></entry><entry>Y</entry><entry></entry>
+ <entry>Y</entry><entry></entry><entry>Y</entry>
+ </row>
+ </tbody>
+ </tgroup>
+ </informaltable>
+ </para>
+ </formalpara>
+ </example>
+ </refsect1>
+ </refentry>
+
+ <!--
+Local Variables:
+mode: sgml
+sgml-parent-document: "pixfmt.sgml"
+indent-tabs-mode: nil
+End:
+ -->
diff --git a/Documentation/DocBook/v4l/pixfmt-y10b.xml b/Documentation/DocBook/v4l/pixfmt-y10b.xml
new file mode 100644
index 0000000..adb0ad8
--- /dev/null
+++ b/Documentation/DocBook/v4l/pixfmt-y10b.xml
@@ -0,0 +1,43 @@
+<refentry id="V4L2-PIX-FMT-Y10BPACK">
+ <refmeta>
+ <refentrytitle>V4L2_PIX_FMT_Y10BPACK ('Y10B')</refentrytitle>
+ &manvol;
+ </refmeta>
+ <refnamediv>
+ <refname><constant>V4L2_PIX_FMT_Y10BPACK</constant></refname>
+ <refpurpose>Grey-scale image as a bit-packed array</refpurpose>
+ </refnamediv>
+ <refsect1>
+ <title>Description</title>
+
+ <para>This is a packed grey-scale image format with a depth of 10 bits per
+ pixel. Pixels are stored in a bit-packed array of 10bit bits per pixel,
+ with no padding between them and with the most significant bits coming
+ first from the left.</para>
+
+ <example>
+ <title><constant>V4L2_PIX_FMT_Y10BPACK</constant> 4 pixel data stream taking 5 bytes</title>
+
+ <formalpara>
+ <title>Bit-packed representation</title>
+ <para>pixels cross the byte boundary and have a ratio of 5 bytes for each 4
+ pixels.
+ <informaltable frame="all">
+ <tgroup cols="5" align="center">
+ <colspec align="left" colwidth="2*" />
+ <tbody valign="top">
+ <row>
+ <entry>Y'<subscript>00[9:2]</subscript></entry>
+ <entry>Y'<subscript>00[1:0]</subscript>Y'<subscript>01[9:4]</subscript></entry>
+ <entry>Y'<subscript>01[3:0]</subscript>Y'<subscript>02[9:6]</subscript></entry>
+ <entry>Y'<subscript>02[5:0]</subscript>Y'<subscript>03[9:8]</subscript></entry>
+ <entry>Y'<subscript>03[7:0]</subscript></entry>
+ </row>
+ </tbody>
+ </tgroup>
+ </informaltable>
+ </para>
+ </formalpara>
+ </example>
+ </refsect1>
+</refentry>
diff --git a/Documentation/DocBook/v4l/pixfmt.xml b/Documentation/DocBook/v4l/pixfmt.xml
index 40af4be..dbfe3b0 100644
--- a/Documentation/DocBook/v4l/pixfmt.xml
+++ b/Documentation/DocBook/v4l/pixfmt.xml
@@ -697,6 +697,7 @@
&sub-grey;
&sub-y10;
&sub-y12;
+ &sub-y10b;
&sub-y16;
&sub-yuyv;
&sub-uyvy;
@@ -712,6 +713,7 @@
&sub-nv12m;
&sub-nv12mt;
&sub-nv16;
+ &sub-m420;
</section>
<section>
diff --git a/Documentation/DocBook/v4l/subdev-formats.xml b/Documentation/DocBook/v4l/subdev-formats.xml
index d7ccd25..a26b10c 100644
--- a/Documentation/DocBook/v4l/subdev-formats.xml
+++ b/Documentation/DocBook/v4l/subdev-formats.xml
@@ -2522,5 +2522,51 @@
</tgroup>
</table>
</section>
+
+ <section>
+ <title>JPEG Compressed Formats</title>
+
+ <para>Those data formats consist of an ordered sequence of 8-bit bytes
+ obtained from JPEG compression process. Additionally to the
+ <constant>_JPEG</constant> prefix the format code is made of
+ the following information.
+ <itemizedlist>
+ <listitem>The number of bus samples per entropy encoded byte.</listitem>
+ <listitem>The bus width.</listitem>
+ </itemizedlist>
+
+ <para>For instance, for a JPEG baseline process and an 8-bit bus width
+ the format will be named <constant>V4L2_MBUS_FMT_JPEG_1X8</constant>.
+ </para>
+ </para>
+
+ <para>The following table lists existing JPEG compressed formats.</para>
+
+ <table pgwide="0" frame="none" id="v4l2-mbus-pixelcode-jpeg">
+ <title>JPEG Formats</title>
+ <tgroup cols="3">
+ <colspec colname="id" align="left" />
+ <colspec colname="code" align="left"/>
+ <colspec colname="remarks" align="left"/>
+ <thead>
+ <row>
+ <entry>Identifier</entry>
+ <entry>Code</entry>
+ <entry>Remarks</entry>
+ </row>
+ </thead>
+ <tbody valign="top">
+ <row id="V4L2-MBUS-FMT-JPEG-1X8">
+ <entry>V4L2_MBUS_FMT_JPEG_1X8</entry>
+ <entry>0x4001</entry>
+ <entry>Besides of its usage for the parallel bus this format is
+ recommended for transmission of JPEG data over MIPI CSI bus
+ using the User Defined 8-bit Data types.
+ </entry>
+ </row>
+ </tbody>
+ </tgroup>
+ </table>
+ </section>
</section>
</section>
diff --git a/Documentation/DocBook/v4l/videodev2.h.xml b/Documentation/DocBook/v4l/videodev2.h.xml
index 2b796a2..c50536a 100644
--- a/Documentation/DocBook/v4l/videodev2.h.xml
+++ b/Documentation/DocBook/v4l/videodev2.h.xml
@@ -311,6 +311,9 @@
#define <link linkend="V4L2-PIX-FMT-Y10">V4L2_PIX_FMT_Y10</link> v4l2_fourcc('Y', '1', '0', ' ') /* 10 Greyscale */
#define <link linkend="V4L2-PIX-FMT-Y16">V4L2_PIX_FMT_Y16</link> v4l2_fourcc('Y', '1', '6', ' ') /* 16 Greyscale */
+/* Grey bit-packed formats */
+#define <link linkend="V4L2-PIX-FMT-Y10BPACK">V4L2_PIX_FMT_Y10BPACK</link> v4l2_fourcc('Y', '1', '0', 'B') /* 10 Greyscale bit-packed */
+
/* Palette formats */
#define <link linkend="V4L2-PIX-FMT-PAL8">V4L2_PIX_FMT_PAL8</link> v4l2_fourcc('P', 'A', 'L', '8') /* 8 8-bit palette */
@@ -333,6 +336,7 @@
#define <link linkend="V4L2-PIX-FMT-YUV420">V4L2_PIX_FMT_YUV420</link> v4l2_fourcc('Y', 'U', '1', '2') /* 12 YUV 4:2:0 */
#define <link linkend="V4L2-PIX-FMT-HI240">V4L2_PIX_FMT_HI240</link> v4l2_fourcc('H', 'I', '2', '4') /* 8 8-bit color */
#define <link linkend="V4L2-PIX-FMT-HM12">V4L2_PIX_FMT_HM12</link> v4l2_fourcc('H', 'M', '1', '2') /* 8 YUV 4:2:0 16x16 macroblocks */
+#define <link linkend="V4L2-PIX-FMT-M420">V4L2_PIX_FMT_M420</link> v4l2_fourcc('M', '4', '2', '0') /* 12 YUV 4:2:0 2 lines y, 1 line uv interleaved */
/* two planes -- one Y, one Cr + Cb interleaved */
#define <link linkend="V4L2-PIX-FMT-NV12">V4L2_PIX_FMT_NV12</link> v4l2_fourcc('N', 'V', '1', '2') /* 12 Y/CbCr 4:2:0 */
diff --git a/Documentation/HOWTO b/Documentation/HOWTO
index 365bda9..81bc1a9 100644
--- a/Documentation/HOWTO
+++ b/Documentation/HOWTO
@@ -209,7 +209,7 @@
Cross-Reference project, which is able to present source code in a
self-referential, indexed webpage format. An excellent up-to-date
repository of the kernel code may be found at:
- http://users.sosdg.org/~qiyong/lxr/
+ http://lxr.linux.no/+trees
The development process
diff --git a/Documentation/IRQ-affinity.txt b/Documentation/IRQ-affinity.txt
index b4a615b..7890fae 100644
--- a/Documentation/IRQ-affinity.txt
+++ b/Documentation/IRQ-affinity.txt
@@ -4,10 +4,11 @@
SMP IRQ affinity
-/proc/irq/IRQ#/smp_affinity specifies which target CPUs are permitted
-for a given IRQ source. It's a bitmask of allowed CPUs. It's not allowed
-to turn off all CPUs, and if an IRQ controller does not support IRQ
-affinity then the value will not change from the default 0xffffffff.
+/proc/irq/IRQ#/smp_affinity and /proc/irq/IRQ#/smp_affinity_list specify
+which target CPUs are permitted for a given IRQ source. It's a bitmask
+(smp_affinity) or cpu list (smp_affinity_list) of allowed CPUs. It's not
+allowed to turn off all CPUs, and if an IRQ controller does not support
+IRQ affinity then the value will not change from the default of all cpus.
/proc/irq/default_smp_affinity specifies default affinity mask that applies
to all non-active IRQs. Once IRQ is allocated/activated its affinity bitmask
@@ -54,3 +55,11 @@
This time around IRQ44 was delivered only to the last four processors.
i.e counters for the CPU0-3 did not change.
+Here is an example of limiting that same irq (44) to cpus 1024 to 1031:
+
+[root@moon 44]# echo 1024-1031 > smp_affinity
+[root@moon 44]# cat smp_affinity
+1024-1031
+
+Note that to do this with a bitmask would require 32 bitmasks of zero
+to follow the pertinent one.
diff --git a/Documentation/SubmittingPatches b/Documentation/SubmittingPatches
index e439cd0..569f353 100644
--- a/Documentation/SubmittingPatches
+++ b/Documentation/SubmittingPatches
@@ -714,10 +714,11 @@
<http://linux.yyz.us/patch-format.html>
Greg Kroah-Hartman, "How to piss off a kernel subsystem maintainer".
- <http://www.kroah.com/log/2005/03/31/>
- <http://www.kroah.com/log/2005/07/08/>
- <http://www.kroah.com/log/2005/10/19/>
- <http://www.kroah.com/log/2006/01/11/>
+ <http://www.kroah.com/log/linux/maintainer.html>
+ <http://www.kroah.com/log/linux/maintainer-02.html>
+ <http://www.kroah.com/log/linux/maintainer-03.html>
+ <http://www.kroah.com/log/linux/maintainer-04.html>
+ <http://www.kroah.com/log/linux/maintainer-05.html>
NO!!!! No more huge patch bombs to linux-kernel@vger.kernel.org people!
<http://marc.theaimsgroup.com/?l=linux-kernel&m=112112749912944&w=2>
diff --git a/Documentation/blockdev/cciss.txt b/Documentation/blockdev/cciss.txt
index 89698e8..c00c6a5 100644
--- a/Documentation/blockdev/cciss.txt
+++ b/Documentation/blockdev/cciss.txt
@@ -169,3 +169,18 @@
must rewind the tape (by issuing "mt -f /dev/st0 rewind" for example)
before i/o can proceed again to a tape drive which was reset.
+There is a cciss_tape_cmds module parameter which can be used to make cciss
+allocate more commands for use by tape drives. Ordinarily only a few commands
+(6) are allocated for tape drives because tape drives are slow and
+infrequently used and the primary purpose of Smart Array controllers is to
+act as a RAID controller for disk drives, so the vast majority of commands
+are allocated for disk devices. However, if you have more than a few tape
+drives attached to a smart array, the default number of commands may not be
+enought (for example, if you have 8 tape drives, you could only rewind 6
+at one time with the default number of commands.) The cciss_tape_cmds module
+parameter allows more commands (up to 16 more) to be allocated for use by
+tape drives. For example:
+
+ insmod cciss.ko cciss_tape_cmds=16
+
+Or, as a kernel boot parameter passed in via grub: cciss.cciss_tape_cmds=8
diff --git a/Documentation/cachetlb.txt b/Documentation/cachetlb.txt
index 9164ae3..9b728dc 100644
--- a/Documentation/cachetlb.txt
+++ b/Documentation/cachetlb.txt
@@ -16,7 +16,7 @@
thinking SMP cache/tlb flushing must be so inefficient, this is in
fact an area where many optimizations are possible. For example,
if it can be proven that a user address space has never executed
-on a cpu (see vma->cpu_vm_mask), one need not perform a flush
+on a cpu (see mm_cpumask()), one need not perform a flush
for this address space on that cpu.
First, the TLB flushing interfaces, since they are the simplest. The
diff --git a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
index edb7ae1..2c6be03 100644
--- a/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
+++ b/Documentation/devicetree/bindings/net/fsl-tsec-phy.txt
@@ -74,3 +74,57 @@
interrupt-parent = <&mpic>;
phy-handle = <&phy0>
};
+
+* Gianfar PTP clock nodes
+
+General Properties:
+
+ - compatible Should be "fsl,etsec-ptp"
+ - reg Offset and length of the register set for the device
+ - interrupts There should be at least two interrupts. Some devices
+ have as many as four PTP related interrupts.
+
+Clock Properties:
+
+ - fsl,tclk-period Timer reference clock period in nanoseconds.
+ - fsl,tmr-prsc Prescaler, divides the output clock.
+ - fsl,tmr-add Frequency compensation value.
+ - fsl,tmr-fiper1 Fixed interval period pulse generator.
+ - fsl,tmr-fiper2 Fixed interval period pulse generator.
+ - fsl,max-adj Maximum frequency adjustment in parts per billion.
+
+ These properties set the operational parameters for the PTP
+ clock. You must choose these carefully for the clock to work right.
+ Here is how to figure good values:
+
+ TimerOsc = system clock MHz
+ tclk_period = desired clock period nanoseconds
+ NominalFreq = 1000 / tclk_period MHz
+ FreqDivRatio = TimerOsc / NominalFreq (must be greater that 1.0)
+ tmr_add = ceil(2^32 / FreqDivRatio)
+ OutputClock = NominalFreq / tmr_prsc MHz
+ PulseWidth = 1 / OutputClock microseconds
+ FiperFreq1 = desired frequency in Hz
+ FiperDiv1 = 1000000 * OutputClock / FiperFreq1
+ tmr_fiper1 = tmr_prsc * tclk_period * FiperDiv1 - tclk_period
+ max_adj = 1000000000 * (FreqDivRatio - 1.0) - 1
+
+ The calculation for tmr_fiper2 is the same as for tmr_fiper1. The
+ driver expects that tmr_fiper1 will be correctly set to produce a 1
+ Pulse Per Second (PPS) signal, since this will be offered to the PPS
+ subsystem to synchronize the Linux clock.
+
+Example:
+
+ ptp_clock@24E00 {
+ compatible = "fsl,etsec-ptp";
+ reg = <0x24E00 0xB0>;
+ interrupts = <12 0x8 13 0x8>;
+ interrupt-parent = < &ipic >;
+ fsl,tclk-period = <10>;
+ fsl,tmr-prsc = <100>;
+ fsl,tmr-add = <0x999999A4>;
+ fsl,tmr-fiper1 = <0x3B9AC9F6>;
+ fsl,tmr-fiper2 = <0x00018696>;
+ fsl,max-adj = <659999998>;
+ };
diff --git a/Documentation/dontdiff b/Documentation/dontdiff
index 470d3db..dfa6fc6 100644
--- a/Documentation/dontdiff
+++ b/Documentation/dontdiff
@@ -1,6 +1,8 @@
*.a
*.aux
*.bin
+*.bz2
+*.cis
*.cpio
*.csp
*.dsp
@@ -8,6 +10,8 @@
*.elf
*.eps
*.fw
+*.gcno
+*.gcov
*.gen.S
*.gif
*.grep
@@ -19,14 +23,20 @@
*.ko
*.log
*.lst
+*.lzma
+*.lzo
+*.mo
*.moc
*.mod.c
*.o
*.o.*
+*.order
*.orig
*.out
+*.patch
*.pdf
*.png
+*.pot
*.ps
*.rej
*.s
@@ -39,16 +49,22 @@
*.tex
*.ver
*.xml
+*.xz
*_MODULES
*_vga16.c
*~
+\#*#
*.9
-*.9.gz
.*
+.*.d
.mm
53c700_d.h
CVS
ChangeSet
+GPATH
+GRTAGS
+GSYMS
+GTAGS
Image
Kerntypes
Module.markers
@@ -57,15 +73,14 @@
SCCS
System.map*
TAGS
+aconf
+af_names.h
aic7*reg.h*
aic7*reg_print.c*
aic7*seq.h*
aicasm
aicdb.h*
-altivec1.c
-altivec2.c
-altivec4.c
-altivec8.c
+altivec*.c
asm-offsets.h
asm_offsets.h
autoconf.h*
@@ -80,6 +95,7 @@
build
bvmlinux
bzImage*
+capability_names.h
capflags.c
classlist.h*
comp*.log
@@ -88,7 +104,8 @@
config
config-*
config_data.h*
-config_data.gz*
+config.mak
+config.mak.autogen
conmakehash
consolemap_deftbl.c*
cpustr.h
@@ -96,7 +113,9 @@
cscope.*
defkeymap.c
devlist.h*
+dnotify_test
docproc
+dslm
elf2ecoff
elfconfig.h*
evergreen_reg_safe.h
@@ -105,6 +124,7 @@
fore200e_mkfirm
fore200e_pca_fw.c*
gconf
+gconf.glade.h
gen-devlist
gen_crc32table
gen_init_cpio
@@ -112,11 +132,12 @@
genheaders
genksyms
*_gray256.c
+hpet_example
+hugepage-mmap
+hugepage-shm
ihex2fw
ikconfig.h*
inat-tables.c
-initramfs_data.cpio
-initramfs_data.cpio.gz
initramfs_list
int16.c
int1.c
@@ -133,15 +154,19 @@
lkc_defs.h
lex.c
lex.*.c
+linux
logo_*.c
logo_*_clut224.c
logo_*_mono.c
lxdialog
+mach
mach-types
mach-types.h
machtypes.h
map
+map_hugetlb
maui_boot.h
+media
mconf
miboot*
mk_elfconfig
@@ -150,23 +175,29 @@
mkcpustr
mkdep
mkprep
+mkregtable
mktables
mktree
modpost
modules.builtin
modules.order
modversions.h*
+nconf
ncscope.*
offset.h
offsets.h
oui.c*
+page-types
parse.c
parse.h
patches*
pca200e.bin
pca200e_ecd.bin2
-piggy.gz
+perf.data
+perf.data.old
+perf-archive
piggyback
+piggy.gzip
piggy.S
pnmtologo
ppc_defs.h*
@@ -177,10 +208,9 @@
r300_reg_safe.h
r420_reg_safe.h
r600_reg_safe.h
-raid6altivec*.c
-raid6int*.c
-raid6tables.c
+recordmcount
relocs
+rlim_names.h
rn50_reg_safe.h
rs600_reg_safe.h
rv515_reg_safe.h
@@ -194,6 +224,7 @@
syscalltab.h
tables.c
tags
+test_get_len
tftpboot.img
timeconst.h
times.h*
@@ -210,10 +241,13 @@
vdso64.lds
vdso64.so.dbg
version.h*
+vmImage
vmlinux
vmlinux-*
vmlinux.aout
+vmlinux.bin.all
vmlinux.lds
+vmlinuz
voffset.h
vsyscall.lds
vsyscall_32.lds
diff --git a/Documentation/feature-removal-schedule.txt b/Documentation/feature-removal-schedule.txt
index 19132ca..95788ad 100644
--- a/Documentation/feature-removal-schedule.txt
+++ b/Documentation/feature-removal-schedule.txt
@@ -551,3 +551,26 @@
Who: Jean Delvare <khali@linux-fr.org>
----------------------------
+
+What: Support for UVCIOC_CTRL_ADD in the uvcvideo driver
+When: 2.6.42
+Why: The information passed to the driver by this ioctl is now queried
+ dynamically from the device.
+Who: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+
+----------------------------
+
+What: Support for UVCIOC_CTRL_MAP_OLD in the uvcvideo driver
+When: 2.6.42
+Why: Used only by applications compiled against older driver versions.
+ Superseded by UVCIOC_CTRL_MAP which supports V4L2 menu controls.
+Who: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+
+----------------------------
+
+What: Support for UVCIOC_CTRL_GET and UVCIOC_CTRL_SET in the uvcvideo driver
+When: 2.6.42
+Why: Superseded by the UVCIOC_CTRL_QUERY ioctl.
+Who: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+
+----------------------------
diff --git a/Documentation/filesystems/9p.txt b/Documentation/filesystems/9p.txt
index b22abba..13de64c 100644
--- a/Documentation/filesystems/9p.txt
+++ b/Documentation/filesystems/9p.txt
@@ -25,6 +25,8 @@
http://xcpu.org/papers/cellfs-talk.pdf
* PROSE I/O: Using 9p to enable Application Partitions
http://plan9.escet.urjc.es/iwp9/cready/PROSE_iwp9_2006.pdf
+ * VirtFS: A Virtualization Aware File System pass-through
+ http://goo.gl/3WPDg
USAGE
=====
@@ -130,31 +132,20 @@
RESOURCES
=========
-Our current recommendation is to use Inferno (http://www.vitanuova.com/nferno/index.html)
-as the 9p server. You can start a 9p server under Inferno by issuing the
-following command:
- ; styxlisten -A tcp!*!564 export '#U*'
+Protocol specifications are maintained on github:
+http://ericvh.github.com/9p-rfc/
-The -A specifies an unauthenticated export. The 564 is the port # (you may
-have to choose a higher port number if running as a normal user). The '#U*'
-specifies exporting the root of the Linux name space. You may specify a
-subset of the namespace by extending the path: '#U*'/tmp would just export
-/tmp. For more information, see the Inferno manual pages covering styxlisten
-and export.
+9p client and server implementations are listed on
+http://9p.cat-v.org/implementations
-A Linux version of the 9p server is now maintained under the npfs project
-on sourceforge (http://sourceforge.net/projects/npfs). The currently
-maintained version is the single-threaded version of the server (named spfs)
-available from the same SVN repository.
+A 9p2000.L server is being developed by LLNL and can be found
+at http://code.google.com/p/diod/
There are user and developer mailing lists available through the v9fs project
on sourceforge (http://sourceforge.net/projects/v9fs).
-A stand-alone version of the module (which should build for any 2.6 kernel)
-is available via (http://github.com/ericvh/9p-sac/tree/master)
-
-News and other information is maintained on SWiK (http://swik.net/v9fs)
-and the Wiki (http://sf.net/apps/mediawiki/v9fs/index.php).
+News and other information is maintained on a Wiki.
+(http://sf.net/apps/mediawiki/v9fs/index.php).
Bug reports may be issued through the kernel.org bugzilla
(http://bugzilla.kernel.org)
diff --git a/Documentation/filesystems/proc.txt b/Documentation/filesystems/proc.txt
index 60740e8..f481780 100644
--- a/Documentation/filesystems/proc.txt
+++ b/Documentation/filesystems/proc.txt
@@ -574,6 +574,12 @@
> cat /proc/irq/0/smp_affinity
ffffffff
+There is an alternate interface, smp_affinity_list which allows specifying
+a cpu range instead of a bitmask:
+
+ > cat /proc/irq/0/smp_affinity_list
+ 1024-1031
+
The default_smp_affinity mask applies to all non-active IRQs, which are the
IRQs which have not yet been allocated/activated, and hence which lack a
/proc/irq/[0-9]* directory.
@@ -583,12 +589,13 @@
include information about any possible driver locality preference.
prof_cpu_mask specifies which CPUs are to be profiled by the system wide
-profiler. Default value is ffffffff (all cpus).
+profiler. Default value is ffffffff (all cpus if there are only 32 of them).
The way IRQs are routed is handled by the IO-APIC, and it's Round Robin
between all the CPUs which are allowed to handle it. As usual the kernel has
more info than you and does a better job than you, so the defaults are the
-best choice for almost everyone.
+best choice for almost everyone. [Note this applies only to those IO-APIC's
+that support "Round Robin" interrupt distribution.]
There are three more important subdirectories in /proc: net, scsi, and sys.
The general rule is that the contents, or even the existence of these
diff --git a/Documentation/filesystems/ubifs.txt b/Documentation/filesystems/ubifs.txt
index d7b13b0..8e4fab6 100644
--- a/Documentation/filesystems/ubifs.txt
+++ b/Documentation/filesystems/ubifs.txt
@@ -115,28 +115,8 @@
Module Parameters for Debugging
===============================
-When UBIFS has been compiled with debugging enabled, there are 3 module
+When UBIFS has been compiled with debugging enabled, there are 2 module
parameters that are available to control aspects of testing and debugging.
-The parameters are unsigned integers where each bit controls an option.
-The parameters are:
-
-debug_msgs Selects which debug messages to display, as follows:
-
- Message Type Flag value
-
- General messages 1
- Journal messages 2
- Mount messages 4
- Commit messages 8
- LEB search messages 16
- Budgeting messages 32
- Garbage collection messages 64
- Tree Node Cache (TNC) messages 128
- LEB properties (lprops) messages 256
- Input/output messages 512
- Log messages 1024
- Scan messages 2048
- Recovery messages 4096
debug_chks Selects extra checks that UBIFS can do while running:
@@ -154,11 +134,9 @@
Test mode Flag value
- Force in-the-gaps method 2
Failure mode for recovery testing 4
-For example, set debug_msgs to 5 to display General messages and Mount
-messages.
+For example, set debug_chks to 3 to enable general and TNC checks.
References
diff --git a/Documentation/hwmon/emc6w201 b/Documentation/hwmon/emc6w201
new file mode 100644
index 0000000..32f355a
--- /dev/null
+++ b/Documentation/hwmon/emc6w201
@@ -0,0 +1,42 @@
+Kernel driver emc6w201
+======================
+
+Supported chips:
+ * SMSC EMC6W201
+ Prefix: 'emc6w201'
+ Addresses scanned: I2C 0x2c, 0x2d, 0x2e
+ Datasheet: Not public
+
+Author: Jean Delvare <khali@linux-fr.org>
+
+
+Description
+-----------
+
+From the datasheet:
+
+"The EMC6W201 is an environmental monitoring device with automatic fan
+control capability and enhanced system acoustics for noise suppression.
+This ACPI compliant device provides hardware monitoring for up to six
+voltages (including its own VCC) and five external thermal sensors,
+measures the speed of up to five fans, and controls the speed of
+multiple DC fans using three Pulse Width Modulator (PWM) outputs. Note
+that it is possible to control more than three fans by connecting two
+fans to one PWM output. The EMC6W201 will be available in a 36-pin
+QFN package."
+
+The device is functionally close to the EMC6D100 series, but is
+register-incompatible.
+
+The driver currently only supports the monitoring of the voltages,
+temperatures and fan speeds. Limits can be changed. Alarms are not
+supported, and neither is fan speed control.
+
+
+Known Systems With EMC6W201
+---------------------------
+
+The EMC6W201 is a rare device, only found on a few systems, made in
+2005 and 2006. Known systems with this device:
+* Dell Precision 670 workstation
+* Gigabyte 2CEWH mainboard
diff --git a/Documentation/hwmon/f71882fg b/Documentation/hwmon/f71882fg
index df02245..84d2623 100644
--- a/Documentation/hwmon/f71882fg
+++ b/Documentation/hwmon/f71882fg
@@ -6,6 +6,10 @@
Prefix: 'f71808e'
Addresses scanned: none, address read from Super I/O config space
Datasheet: Not public
+ * Fintek F71808A
+ Prefix: 'f71808a'
+ Addresses scanned: none, address read from Super I/O config space
+ Datasheet: Not public
* Fintek F71858FG
Prefix: 'f71858fg'
Addresses scanned: none, address read from Super I/O config space
diff --git a/Documentation/hwmon/fam15h_power b/Documentation/hwmon/fam15h_power
new file mode 100644
index 0000000..a92918e
--- /dev/null
+++ b/Documentation/hwmon/fam15h_power
@@ -0,0 +1,37 @@
+Kernel driver fam15h_power
+==========================
+
+Supported chips:
+* AMD Family 15h Processors
+
+ Prefix: 'fam15h_power'
+ Addresses scanned: PCI space
+ Datasheets:
+ BIOS and Kernel Developer's Guide (BKDG) For AMD Family 15h Processors
+ (not yet published)
+
+Author: Andreas Herrmann <andreas.herrmann3@amd.com>
+
+Description
+-----------
+
+This driver permits reading of registers providing power information
+of AMD Family 15h processors.
+
+For AMD Family 15h processors the following power values can be
+calculated using different processor northbridge function registers:
+
+* BasePwrWatts: Specifies in watts the maximum amount of power
+ consumed by the processor for NB and logic external to the core.
+* ProcessorPwrWatts: Specifies in watts the maximum amount of power
+ the processor can support.
+* CurrPwrWatts: Specifies in watts the current amount of power being
+ consumed by the processor.
+
+This driver provides ProcessorPwrWatts and CurrPwrWatts:
+* power1_crit (ProcessorPwrWatts)
+* power1_input (CurrPwrWatts)
+
+On multi-node processors the calculated value is for the entire
+package and not for a single node. Thus the driver creates sysfs
+attributes only for internal node0 of a multi-node processor.
diff --git a/Documentation/hwmon/k10temp b/Documentation/hwmon/k10temp
index d2b56a4..0393c89 100644
--- a/Documentation/hwmon/k10temp
+++ b/Documentation/hwmon/k10temp
@@ -11,6 +11,7 @@
Socket S1G2: Athlon (X2), Sempron (X2), Turion X2 (Ultra)
* AMD Family 12h processors: "Llano"
* AMD Family 14h processors: "Brazos" (C/E/G-Series)
+* AMD Family 15h processors: "Bulldozer"
Prefix: 'k10temp'
Addresses scanned: PCI space
@@ -40,7 +41,7 @@
-----------
This driver permits reading of the internal temperature sensor of AMD
-Family 10h/11h/12h/14h processors.
+Family 10h/11h/12h/14h/15h processors.
All these processors have a sensor, but on those for Socket F or AM2+,
the sensor may return inconsistent values (erratum 319). The driver
diff --git a/Documentation/hwmon/max6650 b/Documentation/hwmon/max6650
index c565650..58d9644 100644
--- a/Documentation/hwmon/max6650
+++ b/Documentation/hwmon/max6650
@@ -2,9 +2,13 @@
=====================
Supported chips:
- * Maxim 6650 / 6651
+ * Maxim MAX6650
Prefix: 'max6650'
- Addresses scanned: I2C 0x1b, 0x1f, 0x48, 0x4b
+ Addresses scanned: none
+ Datasheet: http://pdfserv.maxim-ic.com/en/ds/MAX6650-MAX6651.pdf
+ * Maxim MAX6651
+ Prefix: 'max6651'
+ Addresses scanned: none
Datasheet: http://pdfserv.maxim-ic.com/en/ds/MAX6650-MAX6651.pdf
Authors:
@@ -15,10 +19,10 @@
Description
-----------
-This driver implements support for the Maxim 6650/6651
+This driver implements support for the Maxim MAX6650 and MAX6651.
-The 2 devices are very similar, but the Maxim 6550 has a reduced feature
-set, e.g. only one fan-input, instead of 4 for the 6651.
+The 2 devices are very similar, but the MAX6550 has a reduced feature
+set, e.g. only one fan-input, instead of 4 for the MAX6651.
The driver is not able to distinguish between the 2 devices.
@@ -36,6 +40,13 @@
values are 1, 2, 4, and 8. Use lower values for
faster fans.
+Usage notes
+-----------
+
+This driver does not auto-detect devices. You will have to instantiate the
+devices explicitly. Please see Documentation/i2c/instantiating-devices for
+details.
+
Module parameters
-----------------
diff --git a/Documentation/i2c/busses/i2c-i801 b/Documentation/i2c/busses/i2c-i801
index 6df6976..2871fd5 100644
--- a/Documentation/i2c/busses/i2c-i801
+++ b/Documentation/i2c/busses/i2c-i801
@@ -19,6 +19,7 @@
* Intel 6 Series (PCH)
* Intel Patsburg (PCH)
* Intel DH89xxCC (PCH)
+ * Intel Panther Point (PCH)
Datasheets: Publicly available at the Intel website
On Intel Patsburg and later chipsets, both the normal host SMBus controller
diff --git a/Documentation/i2c/writing-clients b/Documentation/i2c/writing-clients
index 5ebf5af..5aa5337 100644
--- a/Documentation/i2c/writing-clients
+++ b/Documentation/i2c/writing-clients
@@ -38,7 +38,7 @@
.name = "foo",
},
- .id_table = foo_ids,
+ .id_table = foo_idtable,
.probe = foo_probe,
.remove = foo_remove,
/* if device autodetection is needed: */
diff --git a/Documentation/input/elantech.txt b/Documentation/input/elantech.txt
index 56941ae..db798af 100644
--- a/Documentation/input/elantech.txt
+++ b/Documentation/input/elantech.txt
@@ -34,7 +34,8 @@
Currently the Linux Elantech touchpad driver is aware of two different
hardware versions unimaginatively called version 1 and version 2. Version 1
is found in "older" laptops and uses 4 bytes per packet. Version 2 seems to
-be introduced with the EeePC and uses 6 bytes per packet.
+be introduced with the EeePC and uses 6 bytes per packet, and provides
+additional features such as position of two fingers, and width of the touch.
The driver tries to support both hardware versions and should be compatible
with the Xorg Synaptics touchpad driver and its graphical configuration
@@ -94,18 +95,44 @@
can check these bits and reject any packet that appears corrupted. Using
this knob you can bypass that check.
- It is not known yet whether hardware version 2 provides the same parity
- bits. Hence checking is disabled by default. Currently even turning it on
- will do nothing.
-
+ Hardware version 2 does not provide the same parity bits. Only some basic
+ data consistency checking can be done. For now checking is disabled by
+ default. Currently even turning it on will do nothing.
/////////////////////////////////////////////////////////////////////////////
+3. Differentiating hardware versions
+ =================================
-3. Hardware version 1
+To detect the hardware version, read the version number as param[0].param[1].param[2]
+
+ 4 bytes version: (after the arrow is the name given in the Dell-provided driver)
+ 02.00.22 => EF013
+ 02.06.00 => EF019
+In the wild, there appear to be more versions, such as 00.01.64, 01.00.21,
+02.00.00, 02.00.04, 02.00.06.
+
+ 6 bytes:
+ 02.00.30 => EF113
+ 02.08.00 => EF023
+ 02.08.XX => EF123
+ 02.0B.00 => EF215
+ 04.01.XX => Scroll_EF051
+ 04.02.XX => EF051
+In the wild, there appear to be more versions, such as 04.03.01, 04.04.11. There
+appears to be almost no difference, except for EF113, which does not report
+pressure/width and has different data consistency checks.
+
+Probably all the versions with param[0] <= 01 can be considered as
+4 bytes/firmware 1. The versions < 02.08.00, with the exception of 02.00.30, as
+4 bytes/firmware 2. Everything >= 02.08.00 can be considered as 6 bytes.
+
+/////////////////////////////////////////////////////////////////////////////
+
+4. Hardware version 1
==================
-3.1 Registers
+4.1 Registers
~~~~~~~~~
By echoing a hexadecimal value to a register it contents can be altered.
@@ -168,7 +195,7 @@
smart edge activation area width?
-3.2 Native relative mode 4 byte packet format
+4.2 Native relative mode 4 byte packet format
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
byte 0:
@@ -226,9 +253,13 @@
positive = down
-3.3 Native absolute mode 4 byte packet format
+4.3 Native absolute mode 4 byte packet format
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+EF013 and EF019 have a special behaviour (due to a bug in the firmware?), and
+when 1 finger is touching, the first 2 position reports must be discarded.
+This counting is reset whenever a different number of fingers is reported.
+
byte 0:
firmware version 1.x:
@@ -279,11 +310,11 @@
/////////////////////////////////////////////////////////////////////////////
-4. Hardware version 2
+5. Hardware version 2
==================
-4.1 Registers
+5.1 Registers
~~~~~~~~~
By echoing a hexadecimal value to a register it contents can be altered.
@@ -316,16 +347,41 @@
0x7f = never i.e. tap again to release)
-4.2 Native absolute mode 6 byte packet format
+5.2 Native absolute mode 6 byte packet format
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+5.2.1 Parity checking and packet re-synchronization
+There is no parity checking, however some consistency checks can be performed.
-4.2.1 One finger touch
+For instance for EF113:
+ SA1= packet[0];
+ A1 = packet[1];
+ B1 = packet[2];
+ SB1= packet[3];
+ C1 = packet[4];
+ D1 = packet[5];
+ if( (((SA1 & 0x3C) != 0x3C) && ((SA1 & 0xC0) != 0x80)) || // check Byte 1
+ (((SA1 & 0x0C) != 0x0C) && ((SA1 & 0xC0) == 0x80)) || // check Byte 1 (one finger pressed)
+ (((SA1 & 0xC0) != 0x80) && (( A1 & 0xF0) != 0x00)) || // check Byte 2
+ (((SB1 & 0x3E) != 0x38) && ((SA1 & 0xC0) != 0x80)) || // check Byte 4
+ (((SB1 & 0x0E) != 0x08) && ((SA1 & 0xC0) == 0x80)) || // check Byte 4 (one finger pressed)
+ (((SA1 & 0xC0) != 0x80) && (( C1 & 0xF0) != 0x00)) ) // check Byte 5
+ // error detected
+
+For all the other ones, there are just a few constant bits:
+ if( ((packet[0] & 0x0C) != 0x04) ||
+ ((packet[3] & 0x0f) != 0x02) )
+ // error detected
+
+
+In case an error is detected, all the packets are shifted by one (and packet[0] is discarded).
+
+5.2.1 One/Three finger touch
~~~~~~~~~~~~~~~~
byte 0:
bit 7 6 5 4 3 2 1 0
- n1 n0 . . . . R L
+ n1 n0 w3 w2 . . R L
L, R = 1 when Left, Right mouse button pressed
n1..n0 = numbers of fingers on touchpad
@@ -333,24 +389,40 @@
byte 1:
bit 7 6 5 4 3 2 1 0
- . . . . . x10 x9 x8
+ p7 p6 p5 p4 . x10 x9 x8
byte 2:
bit 7 6 5 4 3 2 1 0
- x7 x6 x5 x4 x4 x2 x1 x0
+ x7 x6 x5 x4 x3 x2 x1 x0
x10..x0 = absolute x value (horizontal)
byte 3:
bit 7 6 5 4 3 2 1 0
- . . . . . . . .
+ n4 vf w1 w0 . . . b2
+
+ n4 = set if more than 3 fingers (only in 3 fingers mode)
+ vf = a kind of flag ? (only on EF123, 0 when finger is over one
+ of the buttons, 1 otherwise)
+ w3..w0 = width of the finger touch (not EF113)
+ b2 (on EF113 only, 0 otherwise), b2.R.L indicates one button pressed:
+ 0 = none
+ 1 = Left
+ 2 = Right
+ 3 = Middle (Left and Right)
+ 4 = Forward
+ 5 = Back
+ 6 = Another one
+ 7 = Another one
byte 4:
bit 7 6 5 4 3 2 1 0
- . . . . . . y9 y8
+ p3 p1 p2 p0 . . y9 y8
+
+ p7..p0 = pressure (not EF113)
byte 5:
@@ -363,6 +435,11 @@
4.2.2 Two finger touch
~~~~~~~~~~~~~~~~
+Note that the two pairs of coordinates are not exactly the coordinates of the
+two fingers, but only the pair of the lower-left and upper-right coordinates.
+So the actual fingers might be situated on the other diagonal of the square
+defined by these two points.
+
byte 0:
bit 7 6 5 4 3 2 1 0
@@ -376,14 +453,14 @@
bit 7 6 5 4 3 2 1 0
ax7 ax6 ax5 ax4 ax3 ax2 ax1 ax0
- ax8..ax0 = first finger absolute x value
+ ax8..ax0 = lower-left finger absolute x value
byte 2:
bit 7 6 5 4 3 2 1 0
ay7 ay6 ay5 ay4 ay3 ay2 ay1 ay0
- ay8..ay0 = first finger absolute y value
+ ay8..ay0 = lower-left finger absolute y value
byte 3:
@@ -395,11 +472,11 @@
bit 7 6 5 4 3 2 1 0
bx7 bx6 bx5 bx4 bx3 bx2 bx1 bx0
- bx8..bx0 = second finger absolute x value
+ bx8..bx0 = upper-right finger absolute x value
byte 5:
bit 7 6 5 4 3 2 1 0
by7 by8 by5 by4 by3 by2 by1 by0
- by8..by0 = second finger absolute y value
+ by8..by0 = upper-right finger absolute y value
diff --git a/Documentation/input/rotary-encoder.txt b/Documentation/input/rotary-encoder.txt
index 943e8f6..92e68bc 100644
--- a/Documentation/input/rotary-encoder.txt
+++ b/Documentation/input/rotary-encoder.txt
@@ -9,6 +9,9 @@
and by triggering on falling and rising edges, the turn direction can
be determined.
+Some encoders have both outputs low in stable states, whereas others also have
+a stable state with both outputs high (half-period mode).
+
The phase diagram of these two outputs look like this:
_____ _____ _____
@@ -26,6 +29,8 @@
|<-------->|
one step
+ |<-->|
+ one step (half-period mode)
For more information, please see
http://en.wikipedia.org/wiki/Rotary_encoder
@@ -34,6 +39,13 @@
1. Events / state machine
-------------------------
+In half-period mode, state a) and c) above are used to determine the
+rotational direction based on the last stable state. Events are reported in
+states b) and d) given that the new stable state is different from the last
+(i.e. the rotation was not reversed half-way).
+
+Otherwise, the following apply:
+
a) Rising edge on channel A, channel B in low state
This state is used to recognize a clockwise turn
@@ -96,6 +108,7 @@
.gpio_b = GPIO_ROTARY_B,
.inverted_a = 0,
.inverted_b = 0,
+ .half_period = false,
};
static struct platform_device rotary_encoder_device = {
diff --git a/Documentation/ioctl/ioctl-number.txt b/Documentation/ioctl/ioctl-number.txt
index a0a5d82..3a46e36 100644
--- a/Documentation/ioctl/ioctl-number.txt
+++ b/Documentation/ioctl/ioctl-number.txt
@@ -166,7 +166,6 @@
'T' all arch/x86/include/asm/ioctls.h conflict!
'T' C0-DF linux/if_tun.h conflict!
'U' all sound/asound.h conflict!
-'U' 00-0F drivers/media/video/uvc/uvcvideo.h conflict!
'U' 00-CF linux/uinput.h conflict!
'U' 00-EF linux/usbdevice_fs.h
'U' C0-CF drivers/bluetooth/hci_uart.h
@@ -259,6 +258,7 @@
't' 80-8F linux/isdn_ppp.h
't' 90 linux/toshiba.h
'u' 00-1F linux/smb_fs.h gone
+'u' 20-3F linux/uvcvideo.h USB video class host driver
'v' 00-1F linux/ext2_fs.h conflict!
'v' 00-1F linux/fs.h conflict!
'v' 00-0F linux/sonypi.h conflict!
@@ -304,6 +304,7 @@
0xB0 all RATIO devices in development:
<mailto:vgo@ratio.de>
0xB1 00-1F PPPoX <mailto:mostrows@styx.uwaterloo.ca>
+0xB3 00 linux/mmc/ioctl.h
0xC0 00-0F linux/usb/iowarrior.h
0xCB 00-1F CBM serial IEC bus in development:
<mailto:michael.klein@puffin.lb.shuttle.de>
diff --git a/Documentation/kbuild/kbuild.txt b/Documentation/kbuild/kbuild.txt
index 7c2a89b..68e32bb 100644
--- a/Documentation/kbuild/kbuild.txt
+++ b/Documentation/kbuild/kbuild.txt
@@ -201,3 +201,16 @@
--------------------------------------------------
If enabled over the make command line with "W=1", it turns on additional
gcc -W... options for more extensive build-time checking.
+
+KBUILD_BUILD_TIMESTAMP
+--------------------------------------------------
+Setting this to a date string overrides the timestamp used in the
+UTS_VERSION definition (uname -v in the running kernel). The value has to
+be a string that can be passed to date -d. The default value
+is the output of the date command at one point during build.
+
+KBUILD_BUILD_USER, KBUILD_BUILD_HOST
+--------------------------------------------------
+These two variables allow to override the user@host string displayed during
+boot and in /proc/version. The default value is the output of the commands
+whoami and host, respectively.
diff --git a/Documentation/kbuild/kconfig-language.txt b/Documentation/kbuild/kconfig-language.txt
index b507d61..44e2649 100644
--- a/Documentation/kbuild/kconfig-language.txt
+++ b/Documentation/kbuild/kconfig-language.txt
@@ -113,6 +113,13 @@
That will limit the usefulness but on the other hand avoid
the illegal configurations all over.
+- limiting menu display: "visible if" <expr>
+ This attribute is only applicable to menu blocks, if the condition is
+ false, the menu block is not displayed to the user (the symbols
+ contained there can still be selected by other symbols, though). It is
+ similar to a conditional "prompt" attribude for individual menu
+ entries. Default value of "visible" is true.
+
- numerical ranges: "range" <symbol> <symbol> ["if" <expr>]
This allows to limit the range of possible input values for int
and hex symbols. The user can only input a value which is larger than
@@ -303,7 +310,8 @@
"endmenu"
This defines a menu block, see "Menu structure" above for more
-information. The only possible options are dependencies.
+information. The only possible options are dependencies and "visible"
+attributes.
if:
@@ -381,3 +389,25 @@
limits FOO to module (=m) or disabled (=n).
+Kconfig symbol existence
+~~~~~~~~~~~~~~~~~~~~~~~~
+The following two methods produce the same kconfig symbol dependencies
+but differ greatly in kconfig symbol existence (production) in the
+generated config file.
+
+case 1:
+
+config FOO
+ tristate "about foo"
+ depends on BAR
+
+vs. case 2:
+
+if BAR
+config FOO
+ tristate "about foo"
+endif
+
+In case 1, the symbol FOO will always exist in the config file (given
+no other dependencies). In case 2, the symbol FOO will only exist in
+the config file if BAR is enabled.
diff --git a/Documentation/kbuild/kconfig.txt b/Documentation/kbuild/kconfig.txt
index cca46b1..c313d71 100644
--- a/Documentation/kbuild/kconfig.txt
+++ b/Documentation/kbuild/kconfig.txt
@@ -48,11 +48,6 @@
If you set KCONFIG_OVERWRITECONFIG in the environment, Kconfig will not
break symlinks when .config is a symlink to somewhere else.
-KCONFIG_NOTIMESTAMP
---------------------------------------------------
-If this environment variable exists and is non-null, the timestamp line
-in generated .config files is omitted.
-
______________________________________________________________________
Environment variables for '{allyes/allmod/allno/rand}config'
diff --git a/Documentation/kbuild/makefiles.txt b/Documentation/kbuild/makefiles.txt
index 5d145bb..47435e5 100644
--- a/Documentation/kbuild/makefiles.txt
+++ b/Documentation/kbuild/makefiles.txt
@@ -40,11 +40,13 @@
--- 6.6 Commands useful for building a boot image
--- 6.7 Custom kbuild commands
--- 6.8 Preprocessing linker scripts
+ --- 6.9 Generic header files
=== 7 Kbuild syntax for exported headers
--- 7.1 header-y
--- 7.2 objhdr-y
--- 7.3 destination-y
+ --- 7.4 generic-y
=== 8 Kbuild Variables
=== 9 Makefile language
@@ -499,6 +501,18 @@
gcc >= 3.00. For gcc < 3.00, -malign-functions=4 is used.
Note: cc-option-align uses KBUILD_CFLAGS for $(CC) options
+ cc-disable-warning
+ cc-disable-warning checks if gcc supports a given warning and returns
+ the commandline switch to disable it. This special function is needed,
+ because gcc 4.4 and later accept any unknown -Wno-* option and only
+ warn about it if there is another warning in the source file.
+
+ Example:
+ KBUILD_CFLAGS += $(call cc-disable-warning, unused-but-set-variable)
+
+ In the above example, -Wno-unused-but-set-variable will be added to
+ KBUILD_CFLAGS only if gcc really accepts it.
+
cc-version
cc-version returns a numerical version of the $(CC) compiler version.
The format is <major><minor> where both are two digits. So for example
@@ -955,6 +969,11 @@
used when linking modules. This is often a linker script.
From commandline LDFLAGS_MODULE shall be used (see kbuild.txt).
+ KBUILD_ARFLAGS Options for $(AR) when creating archives
+
+ $(KBUILD_ARFLAGS) set by the top level Makefile to "D" (deterministic
+ mode) if this option is supported by $(AR).
+
--- 6.2 Add prerequisites to archprepare:
The archprepare: rule is used to list prerequisites that need to be
@@ -1209,6 +1228,14 @@
The kbuild infrastructure for *lds file are used in several
architecture-specific files.
+--- 6.9 Generic header files
+
+ The directory include/asm-generic contains the header files
+ that may be shared between individual architectures.
+ The recommended approach how to use a generic header file is
+ to list the file in the Kbuild file.
+ See "7.4 generic-y" for further info on syntax etc.
+
=== 7 Kbuild syntax for exported headers
The kernel include a set of headers that is exported to userspace.
@@ -1265,6 +1292,32 @@
In the example above all exported headers in the Kbuild file
will be located in the directory "include/linux" when exported.
+ --- 7.4 generic-y
+
+ If an architecture uses a verbatim copy of a header from
+ include/asm-generic then this is listed in the file
+ arch/$(ARCH)/include/asm/Kbuild like this:
+
+ Example:
+ #arch/x86/include/asm/Kbuild
+ generic-y += termios.h
+ generic-y += rtc.h
+
+ During the prepare phase of the build a wrapper include
+ file is generated in the directory:
+
+ arch/$(ARCH)/include/generated/asm
+
+ When a header is exported where the architecture uses
+ the generic header a similar wrapper is generated as part
+ of the set of exported headers in the directory:
+
+ usr/include/asm
+
+ The generated wrapper will in both cases look like the following:
+
+ Example: termios.h
+ #include <asm-generic/termios.h>
=== 8 Kbuild Variables
diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
index c603ef7..5438a2d 100644
--- a/Documentation/kernel-parameters.txt
+++ b/Documentation/kernel-parameters.txt
@@ -1777,9 +1777,6 @@
nosoftlockup [KNL] Disable the soft-lockup detector.
- noswapaccount [KNL] Disable accounting of swap in memory resource
- controller. (See Documentation/cgroups/memory.txt)
-
nosync [HW,M68K] Disables sync negotiation for all devices.
notsc [BUGS=X86-32] Disable Time Stamp Counter
@@ -2585,6 +2582,10 @@
bytes of sense data);
c = FIX_CAPACITY (decrease the reported
device capacity by one sector);
+ d = NO_READ_DISC_INFO (don't use
+ READ_DISC_INFO command);
+ e = NO_READ_CAPACITY_16 (don't use
+ READ_CAPACITY_16 command);
h = CAPACITY_HEURISTICS (decrease the
reported device capacity by one
sector if the number is odd);
diff --git a/Documentation/lockstat.txt b/Documentation/lockstat.txt
index 65f4c79..9c0a80d 100644
--- a/Documentation/lockstat.txt
+++ b/Documentation/lockstat.txt
@@ -136,7 +136,7 @@
dcache_lock: 1037 1161 0.38 45.32 774.51 6611 243371 0.15 306.48 77387.24
&inode->i_mutex: 161 286 18446744073709 62882.54 1244614.55 3653 20598 18446744073709 62318.60 1693822.74
&zone->lru_lock: 94 94 0.53 7.33 92.10 4366 32690 0.29 59.81 16350.06
- &inode->i_data.i_mmap_lock: 79 79 0.40 3.77 53.03 11779 87755 0.28 116.93 29898.44
+ &inode->i_data.i_mmap_mutex: 79 79 0.40 3.77 53.03 11779 87755 0.28 116.93 29898.44
&q->__queue_lock: 48 50 0.52 31.62 86.31 774 13131 0.17 113.08 12277.52
&rq->rq_lock_key: 43 47 0.74 68.50 170.63 3706 33929 0.22 107.99 17460.62
&rq->rq_lock_key#2: 39 46 0.75 6.68 49.03 2979 32292 0.17 125.17 17137.63
diff --git a/Documentation/mmc/00-INDEX b/Documentation/mmc/00-INDEX
index fca586f..93dd7a7 100644
--- a/Documentation/mmc/00-INDEX
+++ b/Documentation/mmc/00-INDEX
@@ -2,3 +2,5 @@
- this file
mmc-dev-attrs.txt
- info on SD and MMC device attributes
+mmc-dev-parts.txt
+ - info on SD and MMC device partitions
diff --git a/Documentation/mmc/mmc-dev-attrs.txt b/Documentation/mmc/mmc-dev-attrs.txt
index ff2bd68..8898a95 100644
--- a/Documentation/mmc/mmc-dev-attrs.txt
+++ b/Documentation/mmc/mmc-dev-attrs.txt
@@ -1,3 +1,13 @@
+SD and MMC Block Device Attributes
+==================================
+
+These attributes are defined for the block devices associated with the
+SD or MMC device.
+
+The following attributes are read/write.
+
+ force_ro Enforce read-only access even if write protect switch is off.
+
SD and MMC Device Attributes
============================
diff --git a/Documentation/mmc/mmc-dev-parts.txt b/Documentation/mmc/mmc-dev-parts.txt
new file mode 100644
index 0000000..2db28b8
--- /dev/null
+++ b/Documentation/mmc/mmc-dev-parts.txt
@@ -0,0 +1,27 @@
+SD and MMC Device Partitions
+============================
+
+Device partitions are additional logical block devices present on the
+SD/MMC device.
+
+As of this writing, MMC boot partitions as supported and exposed as
+/dev/mmcblkXboot0 and /dev/mmcblkXboot1, where X is the index of the
+parent /dev/mmcblkX.
+
+MMC Boot Partitions
+===================
+
+Read and write access is provided to the two MMC boot partitions. Due to
+the sensitive nature of the boot partition contents, which often store
+a bootloader or bootloader configuration tables crucial to booting the
+platform, write access is disabled by default to reduce the chance of
+accidental bricking.
+
+To enable write access to /dev/mmcblkXbootY, disable the forced read-only
+access with:
+
+echo 0 > /sys/block/mmcblkXbootY/force_ro
+
+To re-enable read-only access:
+
+echo 1 > /sys/block/mmcblkXbootY/force_ro
diff --git a/Documentation/pti/pti_intel_mid.txt b/Documentation/pti/pti_intel_mid.txt
new file mode 100644
index 0000000..e7a5b6d
--- /dev/null
+++ b/Documentation/pti/pti_intel_mid.txt
@@ -0,0 +1,99 @@
+The Intel MID PTI project is HW implemented in Intel Atom
+system-on-a-chip designs based on the Parallel Trace
+Interface for MIPI P1149.7 cJTAG standard. The kernel solution
+for this platform involves the following files:
+
+./include/linux/pti.h
+./drivers/.../n_tracesink.h
+./drivers/.../n_tracerouter.c
+./drivers/.../n_tracesink.c
+./drivers/.../pti.c
+
+pti.c is the driver that enables various debugging features
+popular on platforms from certain mobile manufacturers.
+n_tracerouter.c and n_tracesink.c allow extra system information to
+be collected and routed to the pti driver, such as trace
+debugging data from a modem. Although n_tracerouter
+and n_tracesink are a part of the complete PTI solution,
+these two line disciplines can work separately from
+pti.c and route any data stream from one /dev/tty node
+to another /dev/tty node via kernel-space. This provides
+a stable, reliable connection that will not break unless
+the user-space application shuts down (plus avoids
+kernel->user->kernel context switch overheads of routing
+data).
+
+An example debugging usage for this driver system:
+ *Hook /dev/ttyPTI0 to syslogd. Opening this port will also start
+ a console device to further capture debugging messages to PTI.
+ *Hook /dev/ttyPTI1 to modem debugging data to write to PTI HW.
+ This is where n_tracerouter and n_tracesink are used.
+ *Hook /dev/pti to a user-level debugging application for writing
+ to PTI HW.
+ *Use mipi_* Kernel Driver API in other device drivers for
+ debugging to PTI by first requesting a PTI write address via
+ mipi_request_masterchannel(1).
+
+Below is example pseudo-code on how a 'privileged' application
+can hook up n_tracerouter and n_tracesink to any tty on
+a system. 'Privileged' means the application has enough
+privileges to successfully manipulate the ldisc drivers
+but is not just blindly executing as 'root'. Keep in mind
+the use of ioctl(,TIOCSETD,) is not specific to the n_tracerouter
+and n_tracesink line discpline drivers but is a generic
+operation for a program to use a line discpline driver
+on a tty port other than the default n_tty.
+
+/////////// To hook up n_tracerouter and n_tracesink /////////
+
+// Note that n_tracerouter depends on n_tracesink.
+#include <errno.h>
+#define ONE_TTY "/dev/ttyOne"
+#define TWO_TTY "/dev/ttyTwo"
+
+// needed global to hand onto ldisc connection
+static int g_fd_source = -1;
+static int g_fd_sink = -1;
+
+// these two vars used to grab LDISC values from loaded ldisc drivers
+// in OS. Look at /proc/tty/ldiscs to get the right numbers from
+// the ldiscs loaded in the system.
+int source_ldisc_num, sink_ldisc_num = -1;
+int retval;
+
+g_fd_source = open(ONE_TTY, O_RDWR); // must be R/W
+g_fd_sink = open(TWO_TTY, O_RDWR); // must be R/W
+
+if (g_fd_source <= 0) || (g_fd_sink <= 0) {
+ // doubt you'll want to use these exact error lines of code
+ printf("Error on open(). errno: %d\n",errno);
+ return errno;
+}
+
+retval = ioctl(g_fd_sink, TIOCSETD, &sink_ldisc_num);
+if (retval < 0) {
+ printf("Error on ioctl(). errno: %d\n", errno);
+ return errno;
+}
+
+retval = ioctl(g_fd_source, TIOCSETD, &source_ldisc_num);
+if (retval < 0) {
+ printf("Error on ioctl(). errno: %d\n", errno);
+ return errno;
+}
+
+/////////// To disconnect n_tracerouter and n_tracesink ////////
+
+// First make sure data through the ldiscs has stopped.
+
+// Second, disconnect ldiscs. This provides a
+// little cleaner shutdown on tty stack.
+sink_ldisc_num = 0;
+source_ldisc_num = 0;
+ioctl(g_fd_uart, TIOCSETD, &sink_ldisc_num);
+ioctl(g_fd_gadget, TIOCSETD, &source_ldisc_num);
+
+// Three, program closes connection, and cleanup:
+close(g_fd_uart);
+close(g_fd_gadget);
+g_fd_uart = g_fd_gadget = NULL;
diff --git a/Documentation/ptp/ptp.txt b/Documentation/ptp/ptp.txt
new file mode 100644
index 0000000..ae8fef8
--- /dev/null
+++ b/Documentation/ptp/ptp.txt
@@ -0,0 +1,89 @@
+
+* PTP hardware clock infrastructure for Linux
+
+ This patch set introduces support for IEEE 1588 PTP clocks in
+ Linux. Together with the SO_TIMESTAMPING socket options, this
+ presents a standardized method for developing PTP user space
+ programs, synchronizing Linux with external clocks, and using the
+ ancillary features of PTP hardware clocks.
+
+ A new class driver exports a kernel interface for specific clock
+ drivers and a user space interface. The infrastructure supports a
+ complete set of PTP hardware clock functionality.
+
+ + Basic clock operations
+ - Set time
+ - Get time
+ - Shift the clock by a given offset atomically
+ - Adjust clock frequency
+
+ + Ancillary clock features
+ - One short or periodic alarms, with signal delivery to user program
+ - Time stamp external events
+ - Period output signals configurable from user space
+ - Synchronization of the Linux system time via the PPS subsystem
+
+** PTP hardware clock kernel API
+
+ A PTP clock driver registers itself with the class driver. The
+ class driver handles all of the dealings with user space. The
+ author of a clock driver need only implement the details of
+ programming the clock hardware. The clock driver notifies the class
+ driver of asynchronous events (alarms and external time stamps) via
+ a simple message passing interface.
+
+ The class driver supports multiple PTP clock drivers. In normal use
+ cases, only one PTP clock is needed. However, for testing and
+ development, it can be useful to have more than one clock in a
+ single system, in order to allow performance comparisons.
+
+** PTP hardware clock user space API
+
+ The class driver also creates a character device for each
+ registered clock. User space can use an open file descriptor from
+ the character device as a POSIX clock id and may call
+ clock_gettime, clock_settime, and clock_adjtime. These calls
+ implement the basic clock operations.
+
+ User space programs may control the clock using standardized
+ ioctls. A program may query, enable, configure, and disable the
+ ancillary clock features. User space can receive time stamped
+ events via blocking read() and poll(). One shot and periodic
+ signals may be configured via the POSIX timer_settime() system
+ call.
+
+** Writing clock drivers
+
+ Clock drivers include include/linux/ptp_clock_kernel.h and register
+ themselves by presenting a 'struct ptp_clock_info' to the
+ registration method. Clock drivers must implement all of the
+ functions in the interface. If a clock does not offer a particular
+ ancillary feature, then the driver should just return -EOPNOTSUPP
+ from those functions.
+
+ Drivers must ensure that all of the methods in interface are
+ reentrant. Since most hardware implementations treat the time value
+ as a 64 bit integer accessed as two 32 bit registers, drivers
+ should use spin_lock_irqsave/spin_unlock_irqrestore to protect
+ against concurrent access. This locking cannot be accomplished in
+ class driver, since the lock may also be needed by the clock
+ driver's interrupt service routine.
+
+** Supported hardware
+
+ + Freescale eTSEC gianfar
+ - 2 Time stamp external triggers, programmable polarity (opt. interrupt)
+ - 2 Alarm registers (optional interrupt)
+ - 3 Periodic signals (optional interrupt)
+
+ + National DP83640
+ - 6 GPIOs programmable as inputs or outputs
+ - 6 GPIOs with dedicated functions (LED/JTAG/clock) can also be
+ used as general inputs or outputs
+ - GPIO inputs can time stamp external triggers
+ - GPIO outputs can produce periodic signals
+ - 1 interrupt pin
+
+ + Intel IXP465
+ - Auxiliary Slave/Master Mode Snapshot (optional interrupt)
+ - Target Time (optional interrupt)
diff --git a/Documentation/ptp/testptp.c b/Documentation/ptp/testptp.c
new file mode 100644
index 0000000..f59ded0
--- /dev/null
+++ b/Documentation/ptp/testptp.c
@@ -0,0 +1,381 @@
+/*
+ * PTP 1588 clock support - User space test program
+ *
+ * Copyright (C) 2010 OMICRON electronics GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <errno.h>
+#include <fcntl.h>
+#include <math.h>
+#include <signal.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/ioctl.h>
+#include <sys/mman.h>
+#include <sys/stat.h>
+#include <sys/time.h>
+#include <sys/timex.h>
+#include <sys/types.h>
+#include <time.h>
+#include <unistd.h>
+
+#include <linux/ptp_clock.h>
+
+#define DEVICE "/dev/ptp0"
+
+#ifndef ADJ_SETOFFSET
+#define ADJ_SETOFFSET 0x0100
+#endif
+
+#ifndef CLOCK_INVALID
+#define CLOCK_INVALID -1
+#endif
+
+/* When glibc offers the syscall, this will go away. */
+#include <sys/syscall.h>
+static int clock_adjtime(clockid_t id, struct timex *tx)
+{
+ return syscall(__NR_clock_adjtime, id, tx);
+}
+
+static clockid_t get_clockid(int fd)
+{
+#define CLOCKFD 3
+#define FD_TO_CLOCKID(fd) ((~(clockid_t) (fd) << 3) | CLOCKFD)
+
+ return FD_TO_CLOCKID(fd);
+}
+
+static void handle_alarm(int s)
+{
+ printf("received signal %d\n", s);
+}
+
+static int install_handler(int signum, void (*handler)(int))
+{
+ struct sigaction action;
+ sigset_t mask;
+
+ /* Unblock the signal. */
+ sigemptyset(&mask);
+ sigaddset(&mask, signum);
+ sigprocmask(SIG_UNBLOCK, &mask, NULL);
+
+ /* Install the signal handler. */
+ action.sa_handler = handler;
+ action.sa_flags = 0;
+ sigemptyset(&action.sa_mask);
+ sigaction(signum, &action, NULL);
+
+ return 0;
+}
+
+static long ppb_to_scaled_ppm(int ppb)
+{
+ /*
+ * The 'freq' field in the 'struct timex' is in parts per
+ * million, but with a 16 bit binary fractional field.
+ * Instead of calculating either one of
+ *
+ * scaled_ppm = (ppb / 1000) << 16 [1]
+ * scaled_ppm = (ppb << 16) / 1000 [2]
+ *
+ * we simply use double precision math, in order to avoid the
+ * truncation in [1] and the possible overflow in [2].
+ */
+ return (long) (ppb * 65.536);
+}
+
+static void usage(char *progname)
+{
+ fprintf(stderr,
+ "usage: %s [options]\n"
+ " -a val request a one-shot alarm after 'val' seconds\n"
+ " -A val request a periodic alarm every 'val' seconds\n"
+ " -c query the ptp clock's capabilities\n"
+ " -d name device to open\n"
+ " -e val read 'val' external time stamp events\n"
+ " -f val adjust the ptp clock frequency by 'val' ppb\n"
+ " -g get the ptp clock time\n"
+ " -h prints this message\n"
+ " -p val enable output with a period of 'val' nanoseconds\n"
+ " -P val enable or disable (val=1|0) the system clock PPS\n"
+ " -s set the ptp clock time from the system time\n"
+ " -S set the system time from the ptp clock time\n"
+ " -t val shift the ptp clock time by 'val' seconds\n",
+ progname);
+}
+
+int main(int argc, char *argv[])
+{
+ struct ptp_clock_caps caps;
+ struct ptp_extts_event event;
+ struct ptp_extts_request extts_request;
+ struct ptp_perout_request perout_request;
+ struct timespec ts;
+ struct timex tx;
+
+ static timer_t timerid;
+ struct itimerspec timeout;
+ struct sigevent sigevent;
+
+ char *progname;
+ int c, cnt, fd;
+
+ char *device = DEVICE;
+ clockid_t clkid;
+ int adjfreq = 0x7fffffff;
+ int adjtime = 0;
+ int capabilities = 0;
+ int extts = 0;
+ int gettime = 0;
+ int oneshot = 0;
+ int periodic = 0;
+ int perout = -1;
+ int pps = -1;
+ int settime = 0;
+
+ progname = strrchr(argv[0], '/');
+ progname = progname ? 1+progname : argv[0];
+ while (EOF != (c = getopt(argc, argv, "a:A:cd:e:f:ghp:P:sSt:v"))) {
+ switch (c) {
+ case 'a':
+ oneshot = atoi(optarg);
+ break;
+ case 'A':
+ periodic = atoi(optarg);
+ break;
+ case 'c':
+ capabilities = 1;
+ break;
+ case 'd':
+ device = optarg;
+ break;
+ case 'e':
+ extts = atoi(optarg);
+ break;
+ case 'f':
+ adjfreq = atoi(optarg);
+ break;
+ case 'g':
+ gettime = 1;
+ break;
+ case 'p':
+ perout = atoi(optarg);
+ break;
+ case 'P':
+ pps = atoi(optarg);
+ break;
+ case 's':
+ settime = 1;
+ break;
+ case 'S':
+ settime = 2;
+ break;
+ case 't':
+ adjtime = atoi(optarg);
+ break;
+ case 'h':
+ usage(progname);
+ return 0;
+ case '?':
+ default:
+ usage(progname);
+ return -1;
+ }
+ }
+
+ fd = open(device, O_RDWR);
+ if (fd < 0) {
+ fprintf(stderr, "opening %s: %s\n", device, strerror(errno));
+ return -1;
+ }
+
+ clkid = get_clockid(fd);
+ if (CLOCK_INVALID == clkid) {
+ fprintf(stderr, "failed to read clock id\n");
+ return -1;
+ }
+
+ if (capabilities) {
+ if (ioctl(fd, PTP_CLOCK_GETCAPS, &caps)) {
+ perror("PTP_CLOCK_GETCAPS");
+ } else {
+ printf("capabilities:\n"
+ " %d maximum frequency adjustment (ppb)\n"
+ " %d programmable alarms\n"
+ " %d external time stamp channels\n"
+ " %d programmable periodic signals\n"
+ " %d pulse per second\n",
+ caps.max_adj,
+ caps.n_alarm,
+ caps.n_ext_ts,
+ caps.n_per_out,
+ caps.pps);
+ }
+ }
+
+ if (0x7fffffff != adjfreq) {
+ memset(&tx, 0, sizeof(tx));
+ tx.modes = ADJ_FREQUENCY;
+ tx.freq = ppb_to_scaled_ppm(adjfreq);
+ if (clock_adjtime(clkid, &tx)) {
+ perror("clock_adjtime");
+ } else {
+ puts("frequency adjustment okay");
+ }
+ }
+
+ if (adjtime) {
+ memset(&tx, 0, sizeof(tx));
+ tx.modes = ADJ_SETOFFSET;
+ tx.time.tv_sec = adjtime;
+ tx.time.tv_usec = 0;
+ if (clock_adjtime(clkid, &tx) < 0) {
+ perror("clock_adjtime");
+ } else {
+ puts("time shift okay");
+ }
+ }
+
+ if (gettime) {
+ if (clock_gettime(clkid, &ts)) {
+ perror("clock_gettime");
+ } else {
+ printf("clock time: %ld.%09ld or %s",
+ ts.tv_sec, ts.tv_nsec, ctime(&ts.tv_sec));
+ }
+ }
+
+ if (settime == 1) {
+ clock_gettime(CLOCK_REALTIME, &ts);
+ if (clock_settime(clkid, &ts)) {
+ perror("clock_settime");
+ } else {
+ puts("set time okay");
+ }
+ }
+
+ if (settime == 2) {
+ clock_gettime(clkid, &ts);
+ if (clock_settime(CLOCK_REALTIME, &ts)) {
+ perror("clock_settime");
+ } else {
+ puts("set time okay");
+ }
+ }
+
+ if (extts) {
+ memset(&extts_request, 0, sizeof(extts_request));
+ extts_request.index = 0;
+ extts_request.flags = PTP_ENABLE_FEATURE;
+ if (ioctl(fd, PTP_EXTTS_REQUEST, &extts_request)) {
+ perror("PTP_EXTTS_REQUEST");
+ extts = 0;
+ } else {
+ puts("external time stamp request okay");
+ }
+ for (; extts; extts--) {
+ cnt = read(fd, &event, sizeof(event));
+ if (cnt != sizeof(event)) {
+ perror("read");
+ break;
+ }
+ printf("event index %u at %lld.%09u\n", event.index,
+ event.t.sec, event.t.nsec);
+ fflush(stdout);
+ }
+ /* Disable the feature again. */
+ extts_request.flags = 0;
+ if (ioctl(fd, PTP_EXTTS_REQUEST, &extts_request)) {
+ perror("PTP_EXTTS_REQUEST");
+ }
+ }
+
+ if (oneshot) {
+ install_handler(SIGALRM, handle_alarm);
+ /* Create a timer. */
+ sigevent.sigev_notify = SIGEV_SIGNAL;
+ sigevent.sigev_signo = SIGALRM;
+ if (timer_create(clkid, &sigevent, &timerid)) {
+ perror("timer_create");
+ return -1;
+ }
+ /* Start the timer. */
+ memset(&timeout, 0, sizeof(timeout));
+ timeout.it_value.tv_sec = oneshot;
+ if (timer_settime(timerid, 0, &timeout, NULL)) {
+ perror("timer_settime");
+ return -1;
+ }
+ pause();
+ timer_delete(timerid);
+ }
+
+ if (periodic) {
+ install_handler(SIGALRM, handle_alarm);
+ /* Create a timer. */
+ sigevent.sigev_notify = SIGEV_SIGNAL;
+ sigevent.sigev_signo = SIGALRM;
+ if (timer_create(clkid, &sigevent, &timerid)) {
+ perror("timer_create");
+ return -1;
+ }
+ /* Start the timer. */
+ memset(&timeout, 0, sizeof(timeout));
+ timeout.it_interval.tv_sec = periodic;
+ timeout.it_value.tv_sec = periodic;
+ if (timer_settime(timerid, 0, &timeout, NULL)) {
+ perror("timer_settime");
+ return -1;
+ }
+ while (1) {
+ pause();
+ }
+ timer_delete(timerid);
+ }
+
+ if (perout >= 0) {
+ if (clock_gettime(clkid, &ts)) {
+ perror("clock_gettime");
+ return -1;
+ }
+ memset(&perout_request, 0, sizeof(perout_request));
+ perout_request.index = 0;
+ perout_request.start.sec = ts.tv_sec + 2;
+ perout_request.start.nsec = 0;
+ perout_request.period.sec = 0;
+ perout_request.period.nsec = perout;
+ if (ioctl(fd, PTP_PEROUT_REQUEST, &perout_request)) {
+ perror("PTP_PEROUT_REQUEST");
+ } else {
+ puts("periodic output request okay");
+ }
+ }
+
+ if (pps != -1) {
+ int enable = pps ? 1 : 0;
+ if (ioctl(fd, PTP_ENABLE_PPS, enable)) {
+ perror("PTP_ENABLE_PPS");
+ } else {
+ puts("pps for system time request okay");
+ }
+ }
+
+ close(fd);
+ return 0;
+}
diff --git a/Documentation/ptp/testptp.mk b/Documentation/ptp/testptp.mk
new file mode 100644
index 0000000..4ef2d97
--- /dev/null
+++ b/Documentation/ptp/testptp.mk
@@ -0,0 +1,33 @@
+# PTP 1588 clock support - User space test program
+#
+# Copyright (C) 2010 OMICRON electronics GmbH
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; either version 2 of the License, or
+# (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+
+CC = $(CROSS_COMPILE)gcc
+INC = -I$(KBUILD_OUTPUT)/usr/include
+CFLAGS = -Wall $(INC)
+LDLIBS = -lrt
+PROGS = testptp
+
+all: $(PROGS)
+
+testptp: testptp.o
+
+clean:
+ rm -f testptp.o
+
+distclean: clean
+ rm -f $(PROGS)
diff --git a/Documentation/sysctl/fs.txt b/Documentation/sysctl/fs.txt
index 4af0614..88fd7f5 100644
--- a/Documentation/sysctl/fs.txt
+++ b/Documentation/sysctl/fs.txt
@@ -231,13 +231,6 @@
This directory contains configuration options for the epoll(7) interface.
-max_user_instances
-------------------
-
-This is the maximum number of epoll file descriptors that a single user can
-have open at a given time. The default value is 128, and should be enough
-for normal users.
-
max_user_watches
----------------
diff --git a/Documentation/usb/callbacks.txt b/Documentation/usb/callbacks.txt
index bfb36b3..9e85846 100644
--- a/Documentation/usb/callbacks.txt
+++ b/Documentation/usb/callbacks.txt
@@ -95,9 +95,11 @@
int (*pre_reset)(struct usb_interface *intf);
-Another driver or user space is triggering a reset on the device which
-contains the interface passed as an argument. Cease IO and save any
-device state you need to restore.
+A driver or user space is triggering a reset on the device which
+contains the interface passed as an argument. Cease IO, wait for all
+outstanding URBs to complete, and save any device state you need to
+restore. No more URBs may be submitted until the post_reset method
+is called.
If you need to allocate memory here, use GFP_NOIO or GFP_ATOMIC, if you
are in atomic context.
diff --git a/Documentation/usb/linux-cdc-acm.inf b/Documentation/usb/linux-cdc-acm.inf
index 612e722..37a02ce 100644
--- a/Documentation/usb/linux-cdc-acm.inf
+++ b/Documentation/usb/linux-cdc-acm.inf
@@ -90,10 +90,10 @@
[SourceDisksFiles]
[SourceDisksNames]
[DeviceList]
-%DESCRIPTION%=DriverInstall, USB\VID_0525&PID_A4A7, USB\VID_0525&PID_A4AB&MI_02
+%DESCRIPTION%=DriverInstall, USB\VID_0525&PID_A4A7, USB\VID_1D6B&PID_0104&MI_02
[DeviceList.NTamd64]
-%DESCRIPTION%=DriverInstall, USB\VID_0525&PID_A4A7, USB\VID_0525&PID_A4AB&MI_02
+%DESCRIPTION%=DriverInstall, USB\VID_0525&PID_A4A7, USB\VID_1D6B&PID_0104&MI_02
;------------------------------------------------------------------------------
diff --git a/Documentation/usb/linux.inf b/Documentation/usb/linux.inf
index 4dee958..4ffa715b0 100644
--- a/Documentation/usb/linux.inf
+++ b/Documentation/usb/linux.inf
@@ -18,15 +18,15 @@
; Decoration for x86 architecture
[LinuxDevices.NTx86]
-%LinuxDevice% = RNDIS.NT.5.1, USB\VID_0525&PID_a4a2, USB\VID_0525&PID_a4ab&MI_00
+%LinuxDevice% = RNDIS.NT.5.1, USB\VID_0525&PID_a4a2, USB\VID_1d6b&PID_0104&MI_00
; Decoration for x64 architecture
[LinuxDevices.NTamd64]
-%LinuxDevice% = RNDIS.NT.5.1, USB\VID_0525&PID_a4a2, USB\VID_0525&PID_a4ab&MI_00
+%LinuxDevice% = RNDIS.NT.5.1, USB\VID_0525&PID_a4a2, USB\VID_1d6b&PID_0104&MI_00
; Decoration for ia64 architecture
[LinuxDevices.NTia64]
-%LinuxDevice% = RNDIS.NT.5.1, USB\VID_0525&PID_a4a2, USB\VID_0525&PID_a4ab&MI_00
+%LinuxDevice% = RNDIS.NT.5.1, USB\VID_0525&PID_a4a2, USB\VID_1d6b&PID_0104&MI_00
;@@@ This is the common setting for setup
[ControlFlags]
diff --git a/Documentation/vgaarbiter.txt b/Documentation/vgaarbiter.txt
index 43a9b06..b7d401e 100644
--- a/Documentation/vgaarbiter.txt
+++ b/Documentation/vgaarbiter.txt
@@ -14,11 +14,10 @@
than one legacy device co-exists on the same machine. But the problem happens
when these devices are trying to be accessed by different userspace clients
(e.g. two server in parallel). Their address assignments conflict. Moreover,
-ideally, being an userspace application, it is not the role of the the X
-server to control bus resources. Therefore an arbitration scheme outside of
-the X server is needed to control the sharing of these resources. This
-document introduces the operation of the VGA arbiter implemented for Linux
-kernel.
+ideally, being a userspace application, it is not the role of the X server to
+control bus resources. Therefore an arbitration scheme outside of the X server
+is needed to control the sharing of these resources. This document introduces
+the operation of the VGA arbiter implemented for the Linux kernel.
----------------------------------------------------------------------------
@@ -39,7 +38,7 @@
The vgaarb is a module of the Linux Kernel. When it is initially loaded, it
scans all PCI devices and adds the VGA ones inside the arbitration. The
arbiter then enables/disables the decoding on different devices of the VGA
-legacy instructions. Device which do not want/need to use the arbiter may
+legacy instructions. Devices which do not want/need to use the arbiter may
explicitly tell it by calling vga_set_legacy_decoding().
The kernel exports a char device interface (/dev/vga_arbiter) to the clients,
@@ -95,8 +94,8 @@
notify them being added/removed in the system and automatically added/removed
in the arbiter.
-There's also a in-kernel API of the arbiter in the case of DRM, vgacon and
-others which may use the arbiter.
+There is also an in-kernel API of the arbiter in case DRM, vgacon, or other
+drivers want to use it.
I.2 libpciaccess
@@ -117,9 +116,8 @@
struct pci_device *vga_default_dev;
-The vga_count is usually need to keep informed how many cards are being
-arbitrated, so for instance if there's only one then it can totally escape the
-scheme.
+The vga_count is used to track how many cards are being arbitrated, so for
+instance, if there is only one card, then it can completely escape arbitration.
These functions below acquire VGA resources for the given card and mark those
diff --git a/Documentation/video4linux/CARDLIST.em28xx b/Documentation/video4linux/CARDLIST.em28xx
index 31b4857..9aae449 100644
--- a/Documentation/video4linux/CARDLIST.em28xx
+++ b/Documentation/video4linux/CARDLIST.em28xx
@@ -54,7 +54,7 @@
53 -> Pinnacle Hybrid Pro (em2881)
54 -> Kworld VS-DVB-T 323UR (em2882) [eb1a:e323]
55 -> Terratec Cinnergy Hybrid T USB XS (em2882) (em2882) [0ccd:005e,0ccd:0042]
- 56 -> Pinnacle Hybrid Pro (2) (em2882) [2304:0226]
+ 56 -> Pinnacle Hybrid Pro (330e) (em2882) [2304:0226]
57 -> Kworld PlusTV HD Hybrid 330 (em2883) [eb1a:a316]
58 -> Compro VideoMate ForYou/Stereo (em2820/em2840) [185b:2041]
60 -> Hauppauge WinTV HVR 850 (em2883) [2040:651f]
diff --git a/Documentation/video4linux/Zoran b/Documentation/video4linux/Zoran
index c40e3ba..9ed629d 100644
--- a/Documentation/video4linux/Zoran
+++ b/Documentation/video4linux/Zoran
@@ -130,7 +130,6 @@
Note: No module for the mse3000 is available yet
Note: No module for the vpx3224 is available yet
-Note: use encoder=X or decoder=X for non-default i2c chips
===========================
diff --git a/Documentation/video4linux/gspca.txt b/Documentation/video4linux/gspca.txt
index 5c542e6..5bfa9a7 100644
--- a/Documentation/video4linux/gspca.txt
+++ b/Documentation/video4linux/gspca.txt
@@ -275,6 +275,7 @@
pac7302 093a:262a Webcam 300k
pac7302 093a:262c Philips SPC 230 NC
jeilinj 0979:0280 Sakar 57379
+jeilinj 0979:0280 Sportscam DV15
zc3xx 0ac8:0302 Z-star Vimicro zc0302
vc032x 0ac8:0321 Vimicro generic vc0321
vc032x 0ac8:0323 Vimicro Vc0323
diff --git a/Documentation/video4linux/uvcvideo.txt b/Documentation/video4linux/uvcvideo.txt
new file mode 100644
index 0000000..848d620
--- /dev/null
+++ b/Documentation/video4linux/uvcvideo.txt
@@ -0,0 +1,239 @@
+Linux USB Video Class (UVC) driver
+==================================
+
+This file documents some driver-specific aspects of the UVC driver, such as
+driver-specific ioctls and implementation notes.
+
+Questions and remarks can be sent to the Linux UVC development mailing list at
+linux-uvc-devel@lists.berlios.de.
+
+
+Extension Unit (XU) support
+---------------------------
+
+1. Introduction
+
+The UVC specification allows for vendor-specific extensions through extension
+units (XUs). The Linux UVC driver supports extension unit controls (XU controls)
+through two separate mechanisms:
+
+ - through mappings of XU controls to V4L2 controls
+ - through a driver-specific ioctl interface
+
+The first one allows generic V4L2 applications to use XU controls by mapping
+certain XU controls onto V4L2 controls, which then show up during ordinary
+control enumeration.
+
+The second mechanism requires uvcvideo-specific knowledge for the application to
+access XU controls but exposes the entire UVC XU concept to user space for
+maximum flexibility.
+
+Both mechanisms complement each other and are described in more detail below.
+
+
+2. Control mappings
+
+The UVC driver provides an API for user space applications to define so-called
+control mappings at runtime. These allow for individual XU controls or byte
+ranges thereof to be mapped to new V4L2 controls. Such controls appear and
+function exactly like normal V4L2 controls (i.e. the stock controls, such as
+brightness, contrast, etc.). However, reading or writing of such a V4L2 controls
+triggers a read or write of the associated XU control.
+
+The ioctl used to create these control mappings is called UVCIOC_CTRL_MAP.
+Previous driver versions (before 0.2.0) required another ioctl to be used
+beforehand (UVCIOC_CTRL_ADD) to pass XU control information to the UVC driver.
+This is no longer necessary as newer uvcvideo versions query the information
+directly from the device.
+
+For details on the UVCIOC_CTRL_MAP ioctl please refer to the section titled
+"IOCTL reference" below.
+
+
+3. Driver specific XU control interface
+
+For applications that need to access XU controls directly, e.g. for testing
+purposes, firmware upload, or accessing binary controls, a second mechanism to
+access XU controls is provided in the form of a driver-specific ioctl, namely
+UVCIOC_CTRL_QUERY.
+
+A call to this ioctl allows applications to send queries to the UVC driver that
+directly map to the low-level UVC control requests.
+
+In order to make such a request the UVC unit ID of the control's extension unit
+and the control selector need to be known. This information either needs to be
+hardcoded in the application or queried using other ways such as by parsing the
+UVC descriptor or, if available, using the media controller API to enumerate a
+device's entities.
+
+Unless the control size is already known it is necessary to first make a
+UVC_GET_LEN requests in order to be able to allocate a sufficiently large buffer
+and set the buffer size to the correct value. Similarly, to find out whether
+UVC_GET_CUR or UVC_SET_CUR are valid requests for a given control, a
+UVC_GET_INFO request should be made. The bits 0 (GET supported) and 1 (SET
+supported) of the resulting byte indicate which requests are valid.
+
+With the addition of the UVCIOC_CTRL_QUERY ioctl the UVCIOC_CTRL_GET and
+UVCIOC_CTRL_SET ioctls have become obsolete since their functionality is a
+subset of the former ioctl. For the time being they are still supported but
+application developers are encouraged to use UVCIOC_CTRL_QUERY instead.
+
+For details on the UVCIOC_CTRL_QUERY ioctl please refer to the section titled
+"IOCTL reference" below.
+
+
+4. Security
+
+The API doesn't currently provide a fine-grained access control facility. The
+UVCIOC_CTRL_ADD and UVCIOC_CTRL_MAP ioctls require super user permissions.
+
+Suggestions on how to improve this are welcome.
+
+
+5. Debugging
+
+In order to debug problems related to XU controls or controls in general it is
+recommended to enable the UVC_TRACE_CONTROL bit in the module parameter 'trace'.
+This causes extra output to be written into the system log.
+
+
+6. IOCTL reference
+
+---- UVCIOC_CTRL_MAP - Map a UVC control to a V4L2 control ----
+
+Argument: struct uvc_xu_control_mapping
+
+Description:
+ This ioctl creates a mapping between a UVC control or part of a UVC
+ control and a V4L2 control. Once mappings are defined, userspace
+ applications can access vendor-defined UVC control through the V4L2
+ control API.
+
+ To create a mapping, applications fill the uvc_xu_control_mapping
+ structure with information about an existing UVC control defined with
+ UVCIOC_CTRL_ADD and a new V4L2 control.
+
+ A UVC control can be mapped to several V4L2 controls. For instance,
+ a UVC pan/tilt control could be mapped to separate pan and tilt V4L2
+ controls. The UVC control is divided into non overlapping fields using
+ the 'size' and 'offset' fields and are then independantly mapped to
+ V4L2 control.
+
+ For signed integer V4L2 controls the data_type field should be set to
+ UVC_CTRL_DATA_TYPE_SIGNED. Other values are currently ignored.
+
+Return value:
+ On success 0 is returned. On error -1 is returned and errno is set
+ appropriately.
+
+ ENOMEM
+ Not enough memory to perform the operation.
+ EPERM
+ Insufficient privileges (super user privileges are required).
+ EINVAL
+ No such UVC control.
+ EOVERFLOW
+ The requested offset and size would overflow the UVC control.
+ EEXIST
+ Mapping already exists.
+
+Data types:
+ * struct uvc_xu_control_mapping
+
+ __u32 id V4L2 control identifier
+ __u8 name[32] V4L2 control name
+ __u8 entity[16] UVC extension unit GUID
+ __u8 selector UVC control selector
+ __u8 size V4L2 control size (in bits)
+ __u8 offset V4L2 control offset (in bits)
+ enum v4l2_ctrl_type
+ v4l2_type V4L2 control type
+ enum uvc_control_data_type
+ data_type UVC control data type
+ struct uvc_menu_info
+ *menu_info Array of menu entries (for menu controls only)
+ __u32 menu_count Number of menu entries (for menu controls only)
+
+ * struct uvc_menu_info
+
+ __u32 value Menu entry value used by the device
+ __u8 name[32] Menu entry name
+
+
+ * enum uvc_control_data_type
+
+ UVC_CTRL_DATA_TYPE_RAW Raw control (byte array)
+ UVC_CTRL_DATA_TYPE_SIGNED Signed integer
+ UVC_CTRL_DATA_TYPE_UNSIGNED Unsigned integer
+ UVC_CTRL_DATA_TYPE_BOOLEAN Boolean
+ UVC_CTRL_DATA_TYPE_ENUM Enumeration
+ UVC_CTRL_DATA_TYPE_BITMASK Bitmask
+
+
+---- UVCIOC_CTRL_QUERY - Query a UVC XU control ----
+
+Argument: struct uvc_xu_control_query
+
+Description:
+ This ioctl queries a UVC XU control identified by its extension unit ID
+ and control selector.
+
+ There are a number of different queries available that closely
+ correspond to the low-level control requests described in the UVC
+ specification. These requests are:
+
+ UVC_GET_CUR
+ Obtain the current value of the control.
+ UVC_GET_MIN
+ Obtain the minimum value of the control.
+ UVC_GET_MAX
+ Obtain the maximum value of the control.
+ UVC_GET_DEF
+ Obtain the default value of the control.
+ UVC_GET_RES
+ Query the resolution of the control, i.e. the step size of the
+ allowed control values.
+ UVC_GET_LEN
+ Query the size of the control in bytes.
+ UVC_GET_INFO
+ Query the control information bitmap, which indicates whether
+ get/set requests are supported.
+ UVC_SET_CUR
+ Update the value of the control.
+
+ Applications must set the 'size' field to the correct length for the
+ control. Exceptions are the UVC_GET_LEN and UVC_GET_INFO queries, for
+ which the size must be set to 2 and 1, respectively. The 'data' field
+ must point to a valid writable buffer big enough to hold the indicated
+ number of data bytes.
+
+ Data is copied directly from the device without any driver-side
+ processing. Applications are responsible for data buffer formatting,
+ including little-endian/big-endian conversion. This is particularly
+ important for the result of the UVC_GET_LEN requests, which is always
+ returned as a little-endian 16-bit integer by the device.
+
+Return value:
+ On success 0 is returned. On error -1 is returned and errno is set
+ appropriately.
+
+ ENOENT
+ The device does not support the given control or the specified
+ extension unit could not be found.
+ ENOBUFS
+ The specified buffer size is incorrect (too big or too small).
+ EINVAL
+ An invalid request code was passed.
+ EBADRQC
+ The given request is not supported by the given control.
+ EFAULT
+ The data pointer references an inaccessible memory area.
+
+Data types:
+ * struct uvc_xu_control_query
+
+ __u8 unit Extension unit ID
+ __u8 selector Control selector
+ __u8 query Request code to send to the device
+ __u16 size Control data size (in bytes)
+ __u8 *data Control value
diff --git a/Documentation/virtual/uml/UserModeLinux-HOWTO.txt b/Documentation/virtual/uml/UserModeLinux-HOWTO.txt
index 9b7e190..5d0fc8b 100644
--- a/Documentation/virtual/uml/UserModeLinux-HOWTO.txt
+++ b/Documentation/virtual/uml/UserModeLinux-HOWTO.txt
@@ -1182,6 +1182,16 @@
forge.net/> and explains these in detail, as well as
some other issues.
+ There is also a related point-to-point only "ucast" transport.
+ This is useful when your network does not support multicast, and
+ all network connections are simple point to point links.
+
+ The full set of command line options for this transport are
+
+
+ ethn=ucast,ethernet address,remote address,listen port,remote port
+
+
66..66.. TTUUNN//TTAAPP wwiitthh tthhee uummll__nneett hheellppeerr
diff --git a/Documentation/vm/locking b/Documentation/vm/locking
index 25fadb4..f61228b 100644
--- a/Documentation/vm/locking
+++ b/Documentation/vm/locking
@@ -66,7 +66,7 @@
expand_stack(), it is hard to come up with a destructive scenario without
having the vmlist protection in this case.
-The page_table_lock nests with the inode i_mmap_lock and the kmem cache
+The page_table_lock nests with the inode i_mmap_mutex and the kmem cache
c_spinlock spinlocks. This is okay, since the kmem code asks for pages after
dropping c_spinlock. The page_table_lock also nests with pagecache_lock and
pagemap_lru_lock spinlocks, and no code asks for memory with these locks
diff --git a/MAINTAINERS b/MAINTAINERS
index a301ffa..1ab17de 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -287,35 +287,35 @@
AD525X ANALOG DEVICES DIGITAL POTENTIOMETERS DRIVER
M: Michael Hennerich <michael.hennerich@analog.com>
-L: device-driver-devel@blackfin.uclinux.org
+L: device-drivers-devel@blackfin.uclinux.org
W: http://wiki.analog.com/AD5254
S: Supported
F: drivers/misc/ad525x_dpot.c
AD5398 CURRENT REGULATOR DRIVER (AD5398/AD5821)
M: Michael Hennerich <michael.hennerich@analog.com>
-L: device-driver-devel@blackfin.uclinux.org
+L: device-drivers-devel@blackfin.uclinux.org
W: http://wiki.analog.com/AD5398
S: Supported
F: drivers/regulator/ad5398.c
AD714X CAPACITANCE TOUCH SENSOR DRIVER (AD7142/3/7/8/7A)
M: Michael Hennerich <michael.hennerich@analog.com>
-L: device-driver-devel@blackfin.uclinux.org
+L: device-drivers-devel@blackfin.uclinux.org
W: http://wiki.analog.com/AD7142
S: Supported
F: drivers/input/misc/ad714x.c
AD7877 TOUCHSCREEN DRIVER
M: Michael Hennerich <michael.hennerich@analog.com>
-L: device-driver-devel@blackfin.uclinux.org
+L: device-drivers-devel@blackfin.uclinux.org
W: http://wiki.analog.com/AD7877
S: Supported
F: drivers/input/touchscreen/ad7877.c
AD7879 TOUCHSCREEN DRIVER (AD7879/AD7889)
M: Michael Hennerich <michael.hennerich@analog.com>
-L: device-driver-devel@blackfin.uclinux.org
+L: device-drivers-devel@blackfin.uclinux.org
W: http://wiki.analog.com/AD7879
S: Supported
F: drivers/input/touchscreen/ad7879.c
@@ -341,7 +341,7 @@
ADP5520 BACKLIGHT DRIVER WITH IO EXPANDER (ADP5520/ADP5501)
M: Michael Hennerich <michael.hennerich@analog.com>
-L: device-driver-devel@blackfin.uclinux.org
+L: device-drivers-devel@blackfin.uclinux.org
W: http://wiki.analog.com/ADP5520
S: Supported
F: drivers/mfd/adp5520.c
@@ -352,7 +352,7 @@
ADP5588 QWERTY KEYPAD AND IO EXPANDER DRIVER (ADP5588/ADP5587)
M: Michael Hennerich <michael.hennerich@analog.com>
-L: device-driver-devel@blackfin.uclinux.org
+L: device-drivers-devel@blackfin.uclinux.org
W: http://wiki.analog.com/ADP5588
S: Supported
F: drivers/input/keyboard/adp5588-keys.c
@@ -360,7 +360,7 @@
ADP8860 BACKLIGHT DRIVER (ADP8860/ADP8861/ADP8863)
M: Michael Hennerich <michael.hennerich@analog.com>
-L: device-driver-devel@blackfin.uclinux.org
+L: device-drivers-devel@blackfin.uclinux.org
W: http://wiki.analog.com/ADP8860
S: Supported
F: drivers/video/backlight/adp8860_bl.c
@@ -387,7 +387,7 @@
ADXL34X THREE-AXIS DIGITAL ACCELEROMETER DRIVER (ADXL345/ADXL346)
M: Michael Hennerich <michael.hennerich@analog.com>
-L: device-driver-devel@blackfin.uclinux.org
+L: device-drivers-devel@blackfin.uclinux.org
W: http://wiki.analog.com/ADXL345
S: Supported
F: drivers/input/misc/adxl34x.c
@@ -483,6 +483,13 @@
F: include/linux/altera_uart.h
F: include/linux/altera_jtaguart.h
+AMD FAM15H PROCESSOR POWER MONITORING DRIVER
+M: Andreas Herrmann <andreas.herrmann3@amd.com>
+L: lm-sensors@lm-sensors.org
+S: Maintained
+F: Documentation/hwmon/fam15h_power
+F: drivers/hwmon/fam15h_power.c
+
AMD GEODE CS5536 USB DEVICE CONTROLLER DRIVER
M: Thomas Dahlmann <dahlmann.thomas@arcor.de>
L: linux-geode@lists.infradead.org (moderated for non-subscribers)
@@ -526,7 +533,7 @@
F: drivers/infiniband/hw/amso1100/
ANALOG DEVICES INC ASOC CODEC DRIVERS
-L: device-driver-devel@blackfin.uclinux.org
+L: device-drivers-devel@blackfin.uclinux.org
L: alsa-devel@alsa-project.org (moderated for non-subscribers)
W: http://wiki.analog.com/
S: Supported
@@ -2034,9 +2041,8 @@
F: net/ax25/sysctl_net_ax25.c
DAVICOM FAST ETHERNET (DMFE) NETWORK DRIVER
-M: Tobias Ringstrom <tori@unhappy.mine.nu>
L: netdev@vger.kernel.org
-S: Maintained
+S: Orphan
F: Documentation/networking/dmfe.txt
F: drivers/net/tulip/dmfe.c
@@ -2245,10 +2251,10 @@
F: include/drm/
INTEL DRM DRIVERS (excluding Poulsbo, Moorestown and derivative chipsets)
-M: Chris Wilson <chris@chris-wilson.co.uk>
+M: Keith Packard <keithp@keithp.com>
L: intel-gfx@lists.freedesktop.org (subscribers-only)
L: dri-devel@lists.freedesktop.org
-T: git git://git.kernel.org/pub/scm/linux/kernel/git/ickle/drm-intel.git
+T: git git://git.kernel.org/pub/scm/linux/kernel/git/keithp/linux-2.6.git
S: Supported
F: drivers/gpu/drm/i915
F: include/drm/i915*
@@ -3591,10 +3597,9 @@
F: drivers/hwmon/k8temp.c
KCONFIG
-M: Roman Zippel <zippel@linux-m68k.org>
+M: Michal Marek <mmarek@suse.cz>
L: linux-kbuild@vger.kernel.org
-Q: http://patchwork.kernel.org/project/linux-kbuild/list/
-S: Maintained
+S: Odd Fixes
F: Documentation/kbuild/kconfig-language.txt
F: scripts/kconfig/
@@ -3898,7 +3903,6 @@
LINUX SECURITY MODULE (LSM) FRAMEWORK
M: Chris Wright <chrisw@sous-sol.org>
L: linux-security-module@vger.kernel.org
-T: git git://git.kernel.org/pub/scm/linux/kernel/git/chrisw/lsm-2.6.git
S: Supported
LIS3LV02D ACCELEROMETER DRIVER
@@ -4253,7 +4257,7 @@
MUSB MULTIPOINT HIGH SPEED DUAL-ROLE CONTROLLER
M: Felipe Balbi <balbi@ti.com>
L: linux-usb@vger.kernel.org
-T: git git://gitorious.org/usb/usb.git
+T: git git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb.git
S: Maintained
F: drivers/usb/musb/
@@ -4588,6 +4592,7 @@
M: David Brownell <dbrownell@users.sourceforge.net>
L: linux-usb@vger.kernel.org
L: linux-omap@vger.kernel.org
+T: git git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usb.git
S: Maintained
F: drivers/usb/*/*omap*
F: arch/arm/*omap*/usb*
@@ -5591,10 +5596,11 @@
M: Eric Paris <eparis@parisplace.org>
L: selinux@tycho.nsa.gov (subscribers-only, general discussion)
W: http://selinuxproject.org
-T: git git://git.kernel.org/pub/scm/linux/kernel/git/jmorris/security-testing-2.6.git
+T: git git://git.infradead.org/users/eparis/selinux.git
S: Supported
F: include/linux/selinux*
F: security/selinux/
+F: scripts/selinux/
APPARMOR SECURITY MODULE
M: John Johansen <john.johansen@canonical.com>
@@ -6794,6 +6800,13 @@
S: Maintained
F: drivers/hwmon/vt8231.c
+VUB300 USB to SDIO/SD/MMC bridge chip
+M: Tony Olech <tony.olech@elandigitalsystems.com>
+L: linux-mmc@vger.kernel.org
+L: linux-usb@vger.kernel.org
+S: Supported
+F: drivers/mmc/host/vub300.c
+
W1 DALLAS'S 1-WIRE BUS
M: Evgeniy Polyakov <johnpol@2ka.mipt.ru>
S: Maintained
diff --git a/Makefile b/Makefile
index a0344a8..529d93f 100644
--- a/Makefile
+++ b/Makefile
@@ -103,7 +103,7 @@
endif
ifeq ("$(origin W)", "command line")
- export KBUILD_ENABLE_EXTRA_GCC_CHECKS := 1
+ export KBUILD_ENABLE_EXTRA_GCC_CHECKS := $(W)
endif
# That's our default target when none is given on the command line
@@ -220,6 +220,14 @@
SRCARCH := sh
endif
+# Additional ARCH settings for tile
+ifeq ($(ARCH),tilepro)
+ SRCARCH := tile
+endif
+ifeq ($(ARCH),tilegx)
+ SRCARCH := tile
+endif
+
# Where to locate arch specific headers
hdr-arch := $(SRCARCH)
@@ -349,7 +357,8 @@
# Use LINUXINCLUDE when you must reference the include/ directory.
# Needed to be compatible with the O= option
-LINUXINCLUDE := -I$(srctree)/arch/$(hdr-arch)/include -Iinclude \
+LINUXINCLUDE := -I$(srctree)/arch/$(hdr-arch)/include \
+ -Iarch/$(hdr-arch)/include/generated -Iinclude \
$(if $(KBUILD_SRC), -I$(srctree)/include) \
-include include/generated/autoconf.h
@@ -382,6 +391,7 @@
export KBUILD_AFLAGS AFLAGS_KERNEL AFLAGS_MODULE
export KBUILD_AFLAGS_MODULE KBUILD_CFLAGS_MODULE KBUILD_LDFLAGS_MODULE
export KBUILD_AFLAGS_KERNEL KBUILD_CFLAGS_KERNEL
+export KBUILD_ARFLAGS
# When compiling out-of-tree modules, put MODVERDIR in the module
# tree rather than in the kernel tree. The kernel tree might
@@ -416,6 +426,12 @@
$(srctree) $(objtree) $(VERSION) $(PATCHLEVEL)
endif
+# Support for using generic headers in asm-generic
+PHONY += asm-generic
+asm-generic:
+ $(Q)$(MAKE) -f $(srctree)/scripts/Makefile.asm-generic \
+ obj=arch/$(SRCARCH)/include/generated/asm
+
# To make sure we do not include .config for any of the *config targets
# catch them early, and hand them over to scripts/kconfig/Makefile
# It is allowed to specify more targets when calling make, including
@@ -559,6 +575,10 @@
KBUILD_CFLAGS += $(call cc-option, -fno-stack-protector)
endif
+# This warning generated too much noise in a regular build.
+# Use make W=1 to enable this warning (see scripts/Makefile.build)
+KBUILD_CFLAGS += $(call cc-disable-warning, unused-but-set-variable)
+
ifdef CONFIG_FRAME_POINTER
KBUILD_CFLAGS += -fno-omit-frame-pointer -fno-optimize-sibling-calls
else
@@ -604,7 +624,7 @@
KBUILD_CFLAGS += $(call cc-option,-Wdeclaration-after-statement,)
# disable pointer signed / unsigned warnings in gcc 4.0
-KBUILD_CFLAGS += $(call cc-option,-Wno-pointer-sign,)
+KBUILD_CFLAGS += $(call cc-disable-warning, pointer-sign)
# disable invalid "can't wrap" optimizations for signed / pointers
KBUILD_CFLAGS += $(call cc-option,-fno-strict-overflow)
@@ -612,6 +632,9 @@
# conserve stack if available
KBUILD_CFLAGS += $(call cc-option,-fconserve-stack)
+# use the deterministic mode of AR if available
+KBUILD_ARFLAGS := $(call ar-option,D)
+
# check for 'asm goto'
ifeq ($(shell $(CONFIG_SHELL) $(srctree)/scripts/gcc-goto.sh $(CC)), y)
KBUILD_CFLAGS += -DCC_HAVE_ASM_GOTO
@@ -797,15 +820,17 @@
# o The correct .tmp_kallsyms2.o is linked into the final vmlinux.
# o Verify that the System.map from vmlinux matches the map from
# .tmp_vmlinux2, just in case we did not generate kallsyms correctly.
-# o If CONFIG_KALLSYMS_EXTRA_PASS is set, do an extra pass using
+# o If 'make KALLSYMS_EXTRA_PASS=1" was used, do an extra pass using
# .tmp_vmlinux3 and .tmp_kallsyms3.o. This is only meant as a
# temporary bypass to allow the kernel to be built while the
# maintainers work out what went wrong with kallsyms.
-ifdef CONFIG_KALLSYMS_EXTRA_PASS
-last_kallsyms := 3
-else
last_kallsyms := 2
+
+ifdef KALLSYMS_EXTRA_PASS
+ifneq ($(KALLSYMS_EXTRA_PASS),0)
+last_kallsyms := 3
+endif
endif
kallsyms.o := .tmp_kallsyms$(last_kallsyms).o
@@ -816,7 +841,8 @@
$(cmd_sysmap) .tmp_vmlinux$(last_kallsyms) .tmp_System.map
$(Q)cmp -s System.map .tmp_System.map || \
(echo Inconsistent kallsyms data; \
- echo Try setting CONFIG_KALLSYMS_EXTRA_PASS; \
+ echo This is a bug - please report about it; \
+ echo Try "make KALLSYMS_EXTRA_PASS=1" as a workaround; \
rm .tmp_kallsyms* ; /bin/false )
endef
@@ -947,7 +973,7 @@
endif
# prepare2 creates a makefile if using a separate output directory
-prepare2: prepare3 outputmakefile
+prepare2: prepare3 outputmakefile asm-generic
prepare1: prepare2 include/linux/version.h include/generated/utsrelease.h \
include/config/auto.conf
@@ -991,7 +1017,8 @@
PHONY += headerdep
headerdep:
- $(Q)find include/ -name '*.h' | xargs --max-args 1 scripts/headerdep.pl
+ $(Q)find $(srctree)/include/ -name '*.h' | xargs --max-args 1 \
+ $(srctree)/scripts/headerdep.pl -I$(srctree)/include
# ---------------------------------------------------------------------------
@@ -1021,7 +1048,7 @@
hdr-dst = $(if $(KBUILD_HEADERS), dst=include/asm-$(hdr-arch), dst=include/asm)
PHONY += __headers
-__headers: include/linux/version.h scripts_basic FORCE
+__headers: include/linux/version.h scripts_basic asm-generic FORCE
$(Q)$(MAKE) $(build)=scripts build_unifdef
PHONY += headers_install_all
@@ -1136,7 +1163,8 @@
.tmp_kallsyms* .tmp_version .tmp_vmlinux* .tmp_System.map
# Directories & files removed with 'make mrproper'
-MRPROPER_DIRS += include/config usr/include include/generated
+MRPROPER_DIRS += include/config usr/include include/generated \
+ arch/*/include/generated
MRPROPER_FILES += .config .config.old .version .old_version \
include/linux/version.h \
Module.symvers tags TAGS cscope* GPATH GTAGS GRTAGS GSYMS
@@ -1267,7 +1295,11 @@
@echo ' make O=dir [targets] Locate all output files in "dir", including .config'
@echo ' make C=1 [targets] Check all c source with $$CHECK (sparse by default)'
@echo ' make C=2 [targets] Force check of all c source with $$CHECK'
- @echo ' make W=1 [targets] Enable extra gcc checks'
+ @echo ' make W=n [targets] Enable extra gcc checks, n=1,2,3 where'
+ @echo ' 1: warnings which may be relevant and do not occur too often'
+ @echo ' 2: warnings which occur quite often but may still be relevant'
+ @echo ' 3: more obscure warnings, can most likely be ignored'
+ @echo ' Multiple levels can be combined with W=12 or W=123'
@echo ' make RECORDMCOUNT_WARN=1 [targets] Warn about ignored mcount sections'
@echo ''
@echo 'Execute "make" or "make all" to build all targets marked with [*] '
@@ -1291,6 +1323,7 @@
# Documentation targets
# ---------------------------------------------------------------------------
%docs: scripts_basic FORCE
+ $(Q)$(MAKE) $(build)=scripts build_docproc
$(Q)$(MAKE) $(build)=Documentation/DocBook $@
else # KBUILD_EXTMOD
@@ -1375,7 +1408,7 @@
clean: $(clean-dirs)
$(call cmd,rmdirs)
$(call cmd,rmfiles)
- @find $(or $(KBUILD_EXTMOD), .) $(RCS_FIND_IGNORE) \
+ @find $(if $(KBUILD_EXTMOD), $(KBUILD_EXTMOD), .) $(RCS_FIND_IGNORE) \
\( -name '*.[oas]' -o -name '*.ko' -o -name '.*.cmd' \
-o -name '.*.d' -o -name '.*.tmp' -o -name '*.mod.c' \
-o -name '*.symtypes' -o -name 'modules.order' \
@@ -1393,13 +1426,15 @@
# Scripts to check various things for consistency
# ---------------------------------------------------------------------------
+PHONY += includecheck versioncheck coccicheck namespacecheck export_report
+
includecheck:
- find * $(RCS_FIND_IGNORE) \
+ find $(srctree)/* $(RCS_FIND_IGNORE) \
-name '*.[hcS]' -type f -print | sort \
| xargs $(PERL) -w $(srctree)/scripts/checkincludes.pl
versioncheck:
- find * $(RCS_FIND_IGNORE) \
+ find $(srctree)/* $(RCS_FIND_IGNORE) \
-name '*.[hcS]' -type f -print | sort \
| xargs $(PERL) -w $(srctree)/scripts/checkversion.pl
diff --git a/arch/Kconfig b/arch/Kconfig
index 8d24bac..26b0e23 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -175,4 +175,7 @@
config HAVE_ARCH_MUTEX_CPU_RELAX
bool
+config HAVE_RCU_TABLE_FREE
+ bool
+
source "kernel/gcov/Kconfig"
diff --git a/arch/alpha/Kconfig b/arch/alpha/Kconfig
index 9808998..e3a8277 100644
--- a/arch/alpha/Kconfig
+++ b/arch/alpha/Kconfig
@@ -12,6 +12,7 @@
select GENERIC_IRQ_PROBE
select AUTO_IRQ_AFFINITY if SMP
select GENERIC_IRQ_SHOW
+ select ARCH_WANT_OPTIONAL_GPIOLIB
help
The Alpha is a 64-bit general-purpose processor designed and
marketed by the Digital Equipment Corporation of blessed memory,
@@ -51,6 +52,9 @@
config GENERIC_CMOS_UPDATE
def_bool y
+config GENERIC_GPIO
+ def_bool y
+
config ZONE_DMA
bool
default y
diff --git a/arch/alpha/include/asm/gpio.h b/arch/alpha/include/asm/gpio.h
new file mode 100644
index 0000000..7dc6a63
--- /dev/null
+++ b/arch/alpha/include/asm/gpio.h
@@ -0,0 +1,55 @@
+/*
+ * Generic GPIO API implementation for Alpha.
+ *
+ * A stright copy of that for PowerPC which was:
+ *
+ * Copyright (c) 2007-2008 MontaVista Software, Inc.
+ *
+ * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef _ASM_ALPHA_GPIO_H
+#define _ASM_ALPHA_GPIO_H
+
+#include <linux/errno.h>
+#include <asm-generic/gpio.h>
+
+#ifdef CONFIG_GPIOLIB
+
+/*
+ * We don't (yet) implement inlined/rapid versions for on-chip gpios.
+ * Just call gpiolib.
+ */
+static inline int gpio_get_value(unsigned int gpio)
+{
+ return __gpio_get_value(gpio);
+}
+
+static inline void gpio_set_value(unsigned int gpio, int value)
+{
+ __gpio_set_value(gpio, value);
+}
+
+static inline int gpio_cansleep(unsigned int gpio)
+{
+ return __gpio_cansleep(gpio);
+}
+
+static inline int gpio_to_irq(unsigned int gpio)
+{
+ return __gpio_to_irq(gpio);
+}
+
+static inline int irq_to_gpio(unsigned int irq)
+{
+ return -EINVAL;
+}
+
+#endif /* CONFIG_GPIOLIB */
+
+#endif /* _ASM_ALPHA_GPIO_H */
diff --git a/arch/alpha/include/asm/smp.h b/arch/alpha/include/asm/smp.h
index 3f390e8..c46e714 100644
--- a/arch/alpha/include/asm/smp.h
+++ b/arch/alpha/include/asm/smp.h
@@ -39,8 +39,6 @@
extern struct cpuinfo_alpha cpu_data[NR_CPUS];
-#define PROC_CHANGE_PENALTY 20
-
#define hard_smp_processor_id() __hard_smp_processor_id()
#define raw_smp_processor_id() (current_thread_info()->cpu)
diff --git a/arch/alpha/kernel/process.c b/arch/alpha/kernel/process.c
index 3ec3506..838eac1 100644
--- a/arch/alpha/kernel/process.c
+++ b/arch/alpha/kernel/process.c
@@ -121,7 +121,7 @@
/* Wait for the secondaries to halt. */
set_cpu_present(boot_cpuid, false);
set_cpu_possible(boot_cpuid, false);
- while (cpus_weight(cpu_present_map))
+ while (cpumask_weight(cpu_present_mask))
barrier();
#endif
diff --git a/arch/alpha/kernel/setup.c b/arch/alpha/kernel/setup.c
index edbddcb..cc0fd86 100644
--- a/arch/alpha/kernel/setup.c
+++ b/arch/alpha/kernel/setup.c
@@ -1257,7 +1257,7 @@
#ifdef CONFIG_SMP
seq_printf(f, "cpus active\t\t: %u\n"
"cpu active mask\t\t: %016lx\n",
- num_online_cpus(), cpus_addr(cpu_possible_map)[0]);
+ num_online_cpus(), cpumask_bits(cpu_possible_mask)[0]);
#endif
show_cache_size (f, "L1 Icache", alpha_l1i_cacheshape);
diff --git a/arch/alpha/kernel/smp.c b/arch/alpha/kernel/smp.c
index 5a621c6..d739703 100644
--- a/arch/alpha/kernel/smp.c
+++ b/arch/alpha/kernel/smp.c
@@ -451,7 +451,7 @@
}
printk(KERN_INFO "SMP: %d CPUs probed -- cpu_present_map = %lx\n",
- smp_num_probed, cpu_present_map.bits[0]);
+ smp_num_probed, cpumask_bits(cpu_present_mask)[0]);
}
/*
@@ -629,8 +629,9 @@
void
smp_send_stop(void)
{
- cpumask_t to_whom = cpu_possible_map;
- cpu_clear(smp_processor_id(), to_whom);
+ cpumask_t to_whom;
+ cpumask_copy(&to_whom, cpu_possible_mask);
+ cpumask_clear_cpu(smp_processor_id(), &to_whom);
#ifdef DEBUG_IPI_MSG
if (hard_smp_processor_id() != boot_cpu_id)
printk(KERN_WARNING "smp_send_stop: Not on boot cpu.\n");
diff --git a/arch/alpha/kernel/sys_dp264.c b/arch/alpha/kernel/sys_dp264.c
index 5ac00fd..f885682 100644
--- a/arch/alpha/kernel/sys_dp264.c
+++ b/arch/alpha/kernel/sys_dp264.c
@@ -140,7 +140,7 @@
for (cpu = 0; cpu < 4; cpu++) {
unsigned long aff = cpu_irq_affinity[cpu];
- if (cpu_isset(cpu, affinity))
+ if (cpumask_test_cpu(cpu, &affinity))
aff |= 1UL << irq;
else
aff &= ~(1UL << irq);
diff --git a/arch/alpha/kernel/sys_titan.c b/arch/alpha/kernel/sys_titan.c
index fea0e46..6994407 100644
--- a/arch/alpha/kernel/sys_titan.c
+++ b/arch/alpha/kernel/sys_titan.c
@@ -65,10 +65,11 @@
register int bcpu = boot_cpuid;
#ifdef CONFIG_SMP
- cpumask_t cpm = cpu_present_map;
+ cpumask_t cpm;
volatile unsigned long *dim0, *dim1, *dim2, *dim3;
unsigned long mask0, mask1, mask2, mask3, dummy;
+ cpumask_copy(&cpm, cpu_present_mask);
mask &= ~isa_enable;
mask0 = mask & titan_cpu_irq_affinity[0];
mask1 = mask & titan_cpu_irq_affinity[1];
@@ -84,10 +85,10 @@
dim1 = &cchip->dim1.csr;
dim2 = &cchip->dim2.csr;
dim3 = &cchip->dim3.csr;
- if (!cpu_isset(0, cpm)) dim0 = &dummy;
- if (!cpu_isset(1, cpm)) dim1 = &dummy;
- if (!cpu_isset(2, cpm)) dim2 = &dummy;
- if (!cpu_isset(3, cpm)) dim3 = &dummy;
+ if (!cpumask_test_cpu(0, &cpm)) dim0 = &dummy;
+ if (!cpumask_test_cpu(1, &cpm)) dim1 = &dummy;
+ if (!cpumask_test_cpu(2, &cpm)) dim2 = &dummy;
+ if (!cpumask_test_cpu(3, &cpm)) dim3 = &dummy;
*dim0 = mask0;
*dim1 = mask1;
@@ -137,7 +138,7 @@
int cpu;
for (cpu = 0; cpu < 4; cpu++) {
- if (cpu_isset(cpu, affinity))
+ if (cpumask_test_cpu(cpu, &affinity))
titan_cpu_irq_affinity[cpu] |= 1UL << irq;
else
titan_cpu_irq_affinity[cpu] &= ~(1UL << irq);
diff --git a/arch/alpha/kernel/vmlinux.lds.S b/arch/alpha/kernel/vmlinux.lds.S
index 3d890a9..f937ad1 100644
--- a/arch/alpha/kernel/vmlinux.lds.S
+++ b/arch/alpha/kernel/vmlinux.lds.S
@@ -39,7 +39,7 @@
__init_begin = ALIGN(PAGE_SIZE);
INIT_TEXT_SECTION(PAGE_SIZE)
INIT_DATA_SECTION(16)
- PERCPU(L1_CACHE_BYTES, PAGE_SIZE)
+ PERCPU_SECTION(L1_CACHE_BYTES)
/* Align to THREAD_SIZE rather than PAGE_SIZE here so any padding page
needed for the THREAD_SIZE aligned init_task gets freed after init */
. = ALIGN(THREAD_SIZE);
diff --git a/arch/alpha/mm/init.c b/arch/alpha/mm/init.c
index 86425ab..69d0c57 100644
--- a/arch/alpha/mm/init.c
+++ b/arch/alpha/mm/init.c
@@ -32,8 +32,6 @@
#include <asm/console.h>
#include <asm/tlb.h>
-DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
-
extern void die_if_kernel(char *,struct pt_regs *,long);
static struct pcb_struct original_pcb;
diff --git a/arch/alpha/mm/numa.c b/arch/alpha/mm/numa.c
index 7b2c56d..3973ae3 100644
--- a/arch/alpha/mm/numa.c
+++ b/arch/alpha/mm/numa.c
@@ -313,6 +313,7 @@
zones_size[ZONE_DMA] = dma_local_pfn;
zones_size[ZONE_NORMAL] = (end_pfn - start_pfn) - dma_local_pfn;
}
+ node_set_state(nid, N_NORMAL_MEMORY);
free_area_init_node(nid, zones_size, start_pfn, NULL);
}
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 377a7a5..7275009 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -197,15 +197,21 @@
depends on !XIP_KERNEL && MMU
depends on !ARCH_REALVIEW || !SPARSEMEM
help
- Patch phys-to-virt translation functions at runtime according to
- the position of the kernel in system memory.
+ Patch phys-to-virt and virt-to-phys translation functions at
+ boot and module load time according to the position of the
+ kernel in system memory.
- This can only be used with non-XIP with MMU kernels where
- the base of physical memory is at a 16MB boundary.
+ This can only be used with non-XIP MMU kernels where the base
+ of physical memory is at a 16MB boundary, or theoretically 64K
+ for the MSM machine class.
config ARM_PATCH_PHYS_VIRT_16BIT
def_bool y
depends on ARM_PATCH_PHYS_VIRT && ARCH_MSM
+ help
+ This option extends the physical to virtual translation patching
+ to allow physical memory down to a theoretical minimum of 64K
+ boundaries.
source "init/Kconfig"
@@ -297,6 +303,7 @@
depends on MMU
select CPU_V6
select ARM_AMBA
+ select ARM_TIMER_SP804
select CLKDEV_LOOKUP
select GENERIC_CLOCKEVENTS
select ARCH_WANT_OPTIONAL_GPIOLIB
@@ -366,6 +373,7 @@
select GENERIC_CLOCKEVENTS
select ARCH_REQUIRE_GPIOLIB
select CLKDEV_LOOKUP
+ select CLKSRC_MMIO
select HAVE_SCHED_CLOCK
help
Support for Freescale MXC/iMX-based family of processors
@@ -375,21 +383,13 @@
select GENERIC_CLOCKEVENTS
select ARCH_REQUIRE_GPIOLIB
select CLKDEV_LOOKUP
+ select CLKSRC_MMIO
help
Support for Freescale MXS-based family of processors
-config ARCH_STMP3XXX
- bool "Freescale STMP3xxx"
- select CPU_ARM926T
- select CLKDEV_LOOKUP
- select ARCH_REQUIRE_GPIOLIB
- select GENERIC_CLOCKEVENTS
- select USB_ARCH_HAS_EHCI
- help
- Support for systems based on the Freescale 3xxx CPUs.
-
config ARCH_NETX
bool "Hilscher NetX based"
+ select CLKSRC_MMIO
select CPU_ARM926T
select ARM_VIC
select GENERIC_CLOCKEVENTS
@@ -457,6 +457,7 @@
config ARCH_IXP4XX
bool "IXP4xx-based"
depends on MMU
+ select CLKSRC_MMIO
select CPU_XSCALE
select GENERIC_GPIO
select GENERIC_CLOCKEVENTS
@@ -468,7 +469,7 @@
config ARCH_DOVE
bool "Marvell Dove"
- select CPU_V6K
+ select CPU_V7
select PCI
select ARCH_REQUIRE_GPIOLIB
select GENERIC_CLOCKEVENTS
@@ -497,6 +498,7 @@
config ARCH_LPC32XX
bool "NXP LPC32XX"
+ select CLKSRC_MMIO
select CPU_ARM926T
select ARCH_REQUIRE_GPIOLIB
select HAVE_IDE
@@ -554,23 +556,12 @@
Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
System-on-Chip devices.
-config ARCH_NS9XXX
- bool "NetSilicon NS9xxx"
- select CPU_ARM926T
- select GENERIC_GPIO
- select GENERIC_CLOCKEVENTS
- select HAVE_CLK
- help
- Say Y here if you intend to run this kernel on a NetSilicon NS9xxx
- System.
-
- <http://www.digi.com/products/microprocessors/index.jsp>
-
config ARCH_W90X900
bool "Nuvoton W90X900 CPU"
select CPU_ARM926T
select ARCH_REQUIRE_GPIOLIB
select CLKDEV_LOOKUP
+ select CLKSRC_MMIO
select GENERIC_CLOCKEVENTS
help
Support for Nuvoton (Winbond logic dept.) ARM9 processor,
@@ -592,6 +583,7 @@
config ARCH_TEGRA
bool "NVIDIA Tegra"
select CLKDEV_LOOKUP
+ select CLKSRC_MMIO
select GENERIC_TIME
select GENERIC_CLOCKEVENTS
select GENERIC_GPIO
@@ -617,6 +609,7 @@
select ARCH_MTD_XIP
select ARCH_HAS_CPUFREQ
select CLKDEV_LOOKUP
+ select CLKSRC_MMIO
select ARCH_REQUIRE_GPIOLIB
select GENERIC_CLOCKEVENTS
select HAVE_SCHED_CLOCK
@@ -667,6 +660,7 @@
config ARCH_SA1100
bool "SA1100-based"
+ select CLKSRC_MMIO
select CPU_SA1100
select ISA
select ARCH_SPARSEMEM_ENABLE
@@ -803,6 +797,7 @@
config ARCH_TCC_926
bool "Telechips TCC ARM926-based systems"
+ select CLKSRC_MMIO
select CPU_ARM926T
select HAVE_CLK
select CLKDEV_LOOKUP
@@ -813,6 +808,7 @@
config ARCH_U300
bool "ST-Ericsson U300 Series"
depends on MMU
+ select CLKSRC_MMIO
select CPU_ARM926T
select HAVE_SCHED_CLOCK
select HAVE_TCM
@@ -854,6 +850,7 @@
select HAVE_IDE
select CLKDEV_LOOKUP
select GENERIC_ALLOCATOR
+ select GENERIC_IRQ_CHIP
select ARCH_HAS_HOLES_MEMORYMODEL
help
Support for TI's DaVinci platform.
@@ -874,6 +871,7 @@
select ARM_AMBA
select ARCH_REQUIRE_GPIOLIB
select CLKDEV_LOOKUP
+ select CLKSRC_MMIO
select GENERIC_CLOCKEVENTS
select HAVE_CLK
help
@@ -951,8 +949,6 @@
source "arch/arm/mach-nomadik/Kconfig"
source "arch/arm/plat-nomadik/Kconfig"
-source "arch/arm/mach-ns9xxx/Kconfig"
-
source "arch/arm/mach-nuc93x/Kconfig"
source "arch/arm/plat-omap/Kconfig"
@@ -1005,8 +1001,6 @@
source "arch/arm/mach-shmobile/Kconfig"
-source "arch/arm/plat-stmp3xxx/Kconfig"
-
source "arch/arm/mach-tegra/Kconfig"
source "arch/arm/mach-u300/Kconfig"
@@ -1033,6 +1027,8 @@
config PLAT_ORION
bool
+ select CLKSRC_MMIO
+ select GENERIC_IRQ_CHIP
select HAVE_SCHED_CLOCK
config PLAT_PXA
@@ -1043,6 +1039,7 @@
config ARM_TIMER_SP804
bool
+ select CLKSRC_MMIO
source arch/arm/mm/Kconfig
@@ -1318,8 +1315,7 @@
source "kernel/time/Kconfig"
config SMP
- bool "Symmetric Multi-Processing (EXPERIMENTAL)"
- depends on EXPERIMENTAL
+ bool "Symmetric Multi-Processing"
depends on CPU_V6K || CPU_V7
depends on GENERIC_CLOCKEVENTS
depends on REALVIEW_EB_ARM11MP || REALVIEW_EB_A9MP || \
@@ -1521,8 +1517,8 @@
def_bool ARCH_SPARSEMEM_ENABLE
config HIGHMEM
- bool "High Memory Support (EXPERIMENTAL)"
- depends on MMU && EXPERIMENTAL
+ bool "High Memory Support"
+ depends on MMU
help
The address space of ARM processors is only 4 Gigabytes large
and it has to accommodate user address space, kernel address
@@ -1742,16 +1738,31 @@
time by entering them here. As a minimum, you should specify the
memory size and the root device (e.g., mem=64M root=/dev/nfs).
+choice
+ prompt "Kernel command line type" if CMDLINE != ""
+ default CMDLINE_FROM_BOOTLOADER
+
+config CMDLINE_FROM_BOOTLOADER
+ bool "Use bootloader kernel arguments if available"
+ help
+ Uses the command-line options passed by the boot loader. If
+ the boot loader doesn't provide any, the default kernel command
+ string provided in CMDLINE will be used.
+
+config CMDLINE_EXTEND
+ bool "Extend bootloader kernel arguments"
+ help
+ The command-line arguments provided by the boot loader will be
+ appended to the default kernel command string.
+
config CMDLINE_FORCE
bool "Always use the default kernel command string"
- depends on CMDLINE != ""
help
Always use the default kernel command string, even if the boot
loader passes other arguments to the kernel.
This is useful if you cannot or don't want to change the
command-line options your boot loader passes to the kernel.
-
- If unsure, say N.
+endchoice
config XIP_KERNEL
bool "Kernel Execute-In-Place from ROM"
@@ -2010,7 +2021,7 @@
source "kernel/power/Kconfig"
config ARCH_SUSPEND_POSSIBLE
- depends on !ARCH_S5P64X0 && !ARCH_S5P6442
+ depends on !ARCH_S5P64X0 && !ARCH_S5P6442 && !ARCH_S5PC100
depends on CPU_ARM920T || CPU_ARM926T || CPU_SA1100 || \
CPU_V6 || CPU_V6K || CPU_V7 || CPU_XSC3 || CPU_XSCALE
def_bool y
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 03d01d7..81cbe40 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -63,13 +63,6 @@
8 - SIGSEGV faults
16 - SIGBUS faults
-config DEBUG_STACK_USAGE
- bool "Enable stack utilization instrumentation"
- depends on DEBUG_KERNEL
- help
- Enables the display of the minimum amount of free stack which each
- task has ever had available in the sysrq-T output.
-
# These options are only for real kernel hackers who want to get their hands dirty.
config DEBUG_LL
bool "Kernel low-level debugging functions"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index c7d321a..25750bc 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -158,13 +158,11 @@
machine-$(CONFIG_ARCH_MX1) := imx
machine-$(CONFIG_ARCH_MX2) := imx
machine-$(CONFIG_ARCH_MX25) := imx
-machine-$(CONFIG_ARCH_MX3) := mx3
+machine-$(CONFIG_ARCH_MX3) := imx
machine-$(CONFIG_ARCH_MX5) := mx5
-machine-$(CONFIG_ARCH_MXC91231) := mxc91231
machine-$(CONFIG_ARCH_MXS) := mxs
machine-$(CONFIG_ARCH_NETX) := netx
machine-$(CONFIG_ARCH_NOMADIK) := nomadik
-machine-$(CONFIG_ARCH_NS9XXX) := ns9xxx
machine-$(CONFIG_ARCH_OMAP1) := omap1
machine-$(CONFIG_ARCH_OMAP2) := omap2
machine-$(CONFIG_ARCH_OMAP3) := omap2
@@ -185,8 +183,6 @@
machine-$(CONFIG_ARCH_SA1100) := sa1100
machine-$(CONFIG_ARCH_SHARK) := shark
machine-$(CONFIG_ARCH_SHMOBILE) := shmobile
-machine-$(CONFIG_ARCH_STMP378X) := stmp378x
-machine-$(CONFIG_ARCH_STMP37XX) := stmp37xx
machine-$(CONFIG_ARCH_TCC8K) := tcc8k
machine-$(CONFIG_ARCH_TEGRA) := tegra
machine-$(CONFIG_ARCH_U300) := u300
@@ -207,7 +203,6 @@
plat-$(CONFIG_ARCH_MXC) := mxc
plat-$(CONFIG_ARCH_OMAP) := omap
plat-$(CONFIG_ARCH_S3C64XX) := samsung
-plat-$(CONFIG_ARCH_STMP3XXX) := stmp3xxx
plat-$(CONFIG_ARCH_TCC_926) := tcc
plat-$(CONFIG_PLAT_IOP) := iop
plat-$(CONFIG_PLAT_NOMADIK) := nomadik
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index 0c6852d..23aad07 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -98,8 +98,6 @@
ccflags-y := -fpic -fno-builtin
asflags-y := -Wa,-march=all
-# Provide size of uncompressed kernel to the decompressor via a linker symbol.
-LDFLAGS_vmlinux = --defsym _image_size=$(shell stat -c "%s" $(obj)/../Image)
# Supply ZRELADDR to the decompressor via a linker symbol.
ifneq ($(CONFIG_AUTO_ZRELADDR),y)
LDFLAGS_vmlinux += --defsym zreladdr=$(ZRELADDR)
@@ -122,10 +120,23 @@
$(obj)/lib1funcs.S: $(srctree)/arch/$(SRCARCH)/lib/lib1funcs.S FORCE
$(call cmd,shipped)
+# We need to prevent any GOTOFF relocs being used with references
+# to symbols in the .bss section since we cannot relocate them
+# independently from the rest at run time. This can be achieved by
+# ensuring that no private .bss symbols exist, as global symbols
+# always have a GOT entry which is what we need.
+# The .data section is already discarded by the linker script so no need
+# to bother about it here.
+check_for_bad_syms = \
+bad_syms=$$($(CROSS_COMPILE)nm $@ | sed -n 's/^.\{8\} [bc] \(.*\)/\1/p') && \
+[ -z "$$bad_syms" ] || \
+ ( echo "following symbols must have non local/private scope:" >&2; \
+ echo "$$bad_syms" >&2; rm -f $@; false )
+
$(obj)/vmlinux: $(obj)/vmlinux.lds $(obj)/$(HEAD) $(obj)/piggy.$(suffix_y).o \
$(addprefix $(obj)/, $(OBJS)) $(lib1funcs) FORCE
$(call if_changed,ld)
- @:
+ @$(check_for_bad_syms)
$(obj)/piggy.$(suffix_y): $(obj)/../Image FORCE
$(call if_changed,$(suffix_y))
diff --git a/arch/arm/boot/compressed/decompress.c b/arch/arm/boot/compressed/decompress.c
index 4c72a97..07be5a2 100644
--- a/arch/arm/boot/compressed/decompress.c
+++ b/arch/arm/boot/compressed/decompress.c
@@ -44,7 +44,7 @@
#include "../../../../lib/decompress_unlzma.c"
#endif
-void do_decompress(u8 *input, int len, u8 *output, void (*error)(char *x))
+int do_decompress(u8 *input, int len, u8 *output, void (*error)(char *x))
{
- decompress(input, len, NULL, NULL, output, NULL, error);
+ return decompress(input, len, NULL, NULL, output, NULL, error);
}
diff --git a/arch/arm/boot/compressed/head.S b/arch/arm/boot/compressed/head.S
index 49f5b2e..f9da419 100644
--- a/arch/arm/boot/compressed/head.S
+++ b/arch/arm/boot/compressed/head.S
@@ -179,7 +179,7 @@
bl cache_on
restart: adr r0, LC0
- ldmia r0, {r1, r2, r3, r6, r9, r11, r12}
+ ldmia r0, {r1, r2, r3, r6, r10, r11, r12}
ldr sp, [r0, #28]
/*
@@ -188,6 +188,20 @@
*/
sub r0, r0, r1 @ calculate the delta offset
add r6, r6, r0 @ _edata
+ add r10, r10, r0 @ inflated kernel size location
+
+ /*
+ * The kernel build system appends the size of the
+ * decompressed kernel at the end of the compressed data
+ * in little-endian form.
+ */
+ ldrb r9, [r10, #0]
+ ldrb lr, [r10, #1]
+ orr r9, r9, lr, lsl #8
+ ldrb lr, [r10, #2]
+ ldrb r10, [r10, #3]
+ orr r9, r9, lr, lsl #16
+ orr r9, r9, r10, lsl #24
#ifndef CONFIG_ZBOOT_ROM
/* malloc space is above the relocated stack (64k max) */
@@ -347,10 +361,10 @@
.word __bss_start @ r2
.word _end @ r3
.word _edata @ r6
- .word _image_size @ r9
+ .word input_data_end - 4 @ r10 (inflated size location)
.word _got_start @ r11
.word _got_end @ ip
- .word user_stack_end @ sp
+ .word .L_user_stack_end @ sp
.size LC0, . - LC0
#ifdef CONFIG_ARCH_RPC
@@ -459,7 +473,11 @@
orr r1, r1, #3 << 10
add r2, r3, #16384
1: cmp r1, r9 @ if virt > start of RAM
+#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
+ orrhs r1, r1, #0x08 @ set cacheable
+#else
orrhs r1, r1, #0x0c @ set cacheable, bufferable
+#endif
cmp r1, r10 @ if virt > end of RAM
bichs r1, r1, #0x0c @ clear cacheable, bufferable
str r1, [r0], #4 @ 1:1 mapping
@@ -484,6 +502,12 @@
mov pc, lr
ENDPROC(__setup_mmu)
+__arm926ejs_mmu_cache_on:
+#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
+ mov r0, #4 @ put dcache in WT mode
+ mcr p15, 7, r0, c15, c0, 0
+#endif
+
__armv4_mmu_cache_on:
mov r12, lr
#ifdef CONFIG_MMU
@@ -665,6 +689,12 @@
W(b) __armv4_mpu_cache_off
W(b) __armv4_mpu_cache_flush
+ .word 0x41069260 @ ARM926EJ-S (v5TEJ)
+ .word 0xff0ffff0
+ b __arm926ejs_mmu_cache_on
+ b __armv4_mmu_cache_off
+ b __armv5tej_mmu_cache_flush
+
.word 0x00007000 @ ARM7 IDs
.word 0x0000f000
mov pc, lr
@@ -747,12 +777,6 @@
W(b) __armv4_mmu_cache_off
W(b) __armv6_mmu_cache_flush
- .word 0x560f5810 @ Marvell PJ4 ARMv6
- .word 0xff0ffff0
- W(b) __armv4_mmu_cache_on
- W(b) __armv4_mmu_cache_off
- W(b) __armv6_mmu_cache_flush
-
.word 0x000f0000 @ new CPU Id
.word 0x000f0000
W(b) __armv7_mmu_cache_on
@@ -1078,5 +1102,5 @@
.align
.section ".stack", "aw", %nobits
-user_stack: .space 4096
-user_stack_end:
+.L_user_stack: .space 4096
+.L_user_stack_end:
diff --git a/arch/arm/boot/compressed/misc.c b/arch/arm/boot/compressed/misc.c
index 2df3826..832d372 100644
--- a/arch/arm/boot/compressed/misc.c
+++ b/arch/arm/boot/compressed/misc.c
@@ -26,8 +26,6 @@
#include <linux/linkage.h>
#include <asm/string.h>
-#include <asm/unaligned.h>
-
static void putstr(const char *ptr);
extern void error(char *x);
@@ -139,13 +137,12 @@
}
/*
- * gzip delarations
+ * gzip declarations
*/
extern char input_data[];
extern char input_data_end[];
unsigned char *output_data;
-unsigned long output_ptr;
unsigned long free_mem_ptr;
unsigned long free_mem_end_ptr;
@@ -170,15 +167,15 @@
error("Attempting division by 0!");
}
-extern void do_decompress(u8 *input, int len, u8 *output, void (*error)(char *x));
+extern int do_decompress(u8 *input, int len, u8 *output, void (*error)(char *x));
-unsigned long
+void
decompress_kernel(unsigned long output_start, unsigned long free_mem_ptr_p,
unsigned long free_mem_ptr_end_p,
int arch_id)
{
- unsigned char *tmp;
+ int ret;
output_data = (unsigned char *)output_start;
free_mem_ptr = free_mem_ptr_p;
@@ -187,12 +184,11 @@
arch_decomp_setup();
- tmp = (unsigned char *) (((unsigned long)input_data_end) - 4);
- output_ptr = get_unaligned_le32(tmp);
-
putstr("Uncompressing Linux...");
- do_decompress(input_data, input_data_end - input_data,
- output_data, error);
- putstr(" done, booting the kernel.\n");
- return output_ptr;
+ ret = do_decompress(input_data, input_data_end - input_data,
+ output_data, error);
+ if (ret)
+ error("decompressor returned an error");
+ else
+ putstr(" done, booting the kernel.\n");
}
diff --git a/arch/arm/common/gic.c b/arch/arm/common/gic.c
index f70ec7d..4ddd0a6 100644
--- a/arch/arm/common/gic.c
+++ b/arch/arm/common/gic.c
@@ -49,7 +49,7 @@
* Default make them NULL.
*/
struct irq_chip gic_arch_extn = {
- .irq_ack = NULL,
+ .irq_eoi = NULL,
.irq_mask = NULL,
.irq_unmask = NULL,
.irq_retrigger = NULL,
@@ -84,21 +84,12 @@
/*
* Routines to acknowledge, disable and enable interrupts
*/
-static void gic_ack_irq(struct irq_data *d)
-{
- spin_lock(&irq_controller_lock);
- if (gic_arch_extn.irq_ack)
- gic_arch_extn.irq_ack(d);
- writel(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
- spin_unlock(&irq_controller_lock);
-}
-
static void gic_mask_irq(struct irq_data *d)
{
u32 mask = 1 << (d->irq % 32);
spin_lock(&irq_controller_lock);
- writel(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4);
+ writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4);
if (gic_arch_extn.irq_mask)
gic_arch_extn.irq_mask(d);
spin_unlock(&irq_controller_lock);
@@ -111,10 +102,21 @@
spin_lock(&irq_controller_lock);
if (gic_arch_extn.irq_unmask)
gic_arch_extn.irq_unmask(d);
- writel(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4);
+ writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4);
spin_unlock(&irq_controller_lock);
}
+static void gic_eoi_irq(struct irq_data *d)
+{
+ if (gic_arch_extn.irq_eoi) {
+ spin_lock(&irq_controller_lock);
+ gic_arch_extn.irq_eoi(d);
+ spin_unlock(&irq_controller_lock);
+ }
+
+ writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
+}
+
static int gic_set_type(struct irq_data *d, unsigned int type)
{
void __iomem *base = gic_dist_base(d);
@@ -138,7 +140,7 @@
if (gic_arch_extn.irq_set_type)
gic_arch_extn.irq_set_type(d, type);
- val = readl(base + GIC_DIST_CONFIG + confoff);
+ val = readl_relaxed(base + GIC_DIST_CONFIG + confoff);
if (type == IRQ_TYPE_LEVEL_HIGH)
val &= ~confmask;
else if (type == IRQ_TYPE_EDGE_RISING)
@@ -148,15 +150,15 @@
* As recommended by the spec, disable the interrupt before changing
* the configuration
*/
- if (readl(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) {
- writel(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff);
+ if (readl_relaxed(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) {
+ writel_relaxed(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff);
enabled = true;
}
- writel(val, base + GIC_DIST_CONFIG + confoff);
+ writel_relaxed(val, base + GIC_DIST_CONFIG + confoff);
if (enabled)
- writel(enablemask, base + GIC_DIST_ENABLE_SET + enableoff);
+ writel_relaxed(enablemask, base + GIC_DIST_ENABLE_SET + enableoff);
spin_unlock(&irq_controller_lock);
@@ -188,8 +190,8 @@
spin_lock(&irq_controller_lock);
d->node = cpu;
- val = readl(reg) & ~mask;
- writel(val | bit, reg);
+ val = readl_relaxed(reg) & ~mask;
+ writel_relaxed(val | bit, reg);
spin_unlock(&irq_controller_lock);
return 0;
@@ -218,11 +220,10 @@
unsigned int cascade_irq, gic_irq;
unsigned long status;
- /* primary controller ack'ing */
- chip->irq_ack(&desc->irq_data);
+ chained_irq_enter(chip, desc);
spin_lock(&irq_controller_lock);
- status = readl(chip_data->cpu_base + GIC_CPU_INTACK);
+ status = readl_relaxed(chip_data->cpu_base + GIC_CPU_INTACK);
spin_unlock(&irq_controller_lock);
gic_irq = (status & 0x3ff);
@@ -236,15 +237,14 @@
generic_handle_irq(cascade_irq);
out:
- /* primary controller unmasking */
- chip->irq_unmask(&desc->irq_data);
+ chained_irq_exit(chip, desc);
}
static struct irq_chip gic_chip = {
.name = "GIC",
- .irq_ack = gic_ack_irq,
.irq_mask = gic_mask_irq,
.irq_unmask = gic_unmask_irq,
+ .irq_eoi = gic_eoi_irq,
.irq_set_type = gic_set_type,
.irq_retrigger = gic_retrigger,
#ifdef CONFIG_SMP
@@ -272,13 +272,13 @@
cpumask |= cpumask << 8;
cpumask |= cpumask << 16;
- writel(0, base + GIC_DIST_CTRL);
+ writel_relaxed(0, base + GIC_DIST_CTRL);
/*
* Find out how many interrupts are supported.
* The GIC only supports up to 1020 interrupt sources.
*/
- gic_irqs = readl(base + GIC_DIST_CTR) & 0x1f;
+ gic_irqs = readl_relaxed(base + GIC_DIST_CTR) & 0x1f;
gic_irqs = (gic_irqs + 1) * 32;
if (gic_irqs > 1020)
gic_irqs = 1020;
@@ -287,26 +287,26 @@
* Set all global interrupts to be level triggered, active low.
*/
for (i = 32; i < gic_irqs; i += 16)
- writel(0, base + GIC_DIST_CONFIG + i * 4 / 16);
+ writel_relaxed(0, base + GIC_DIST_CONFIG + i * 4 / 16);
/*
* Set all global interrupts to this CPU only.
*/
for (i = 32; i < gic_irqs; i += 4)
- writel(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
+ writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
/*
* Set priority on all global interrupts.
*/
for (i = 32; i < gic_irqs; i += 4)
- writel(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);
+ writel_relaxed(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);
/*
* Disable all interrupts. Leave the PPI and SGIs alone
* as these enables are banked registers.
*/
for (i = 32; i < gic_irqs; i += 32)
- writel(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
+ writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
/*
* Limit number of interrupts registered to the platform maximum
@@ -319,12 +319,12 @@
* Setup the Linux IRQ subsystem.
*/
for (i = irq_start; i < irq_limit; i++) {
- irq_set_chip_and_handler(i, &gic_chip, handle_level_irq);
+ irq_set_chip_and_handler(i, &gic_chip, handle_fasteoi_irq);
irq_set_chip_data(i, gic);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
}
- writel(1, base + GIC_DIST_CTRL);
+ writel_relaxed(1, base + GIC_DIST_CTRL);
}
static void __cpuinit gic_cpu_init(struct gic_chip_data *gic)
@@ -337,17 +337,17 @@
* Deal with the banked PPI and SGI interrupts - disable all
* PPI interrupts, ensure all SGI interrupts are enabled.
*/
- writel(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);
- writel(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);
+ writel_relaxed(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);
+ writel_relaxed(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);
/*
* Set priority on PPI and SGI interrupts
*/
for (i = 0; i < 32; i += 4)
- writel(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);
+ writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);
- writel(0xf0, base + GIC_CPU_PRIMASK);
- writel(1, base + GIC_CPU_CTRL);
+ writel_relaxed(0xf0, base + GIC_CPU_PRIMASK);
+ writel_relaxed(1, base + GIC_CPU_CTRL);
}
void __init gic_init(unsigned int gic_nr, unsigned int irq_start,
@@ -391,7 +391,13 @@
{
unsigned long map = *cpus_addr(*mask);
+ /*
+ * Ensure that stores to Normal memory are visible to the
+ * other CPUs before issuing the IPI.
+ */
+ dsb();
+
/* this always happens on GIC0 */
- writel(map << 16 | irq, gic_data[0].dist_base + GIC_DIST_SOFTINT);
+ writel_relaxed(map << 16 | irq, gic_data[0].dist_base + GIC_DIST_SOFTINT);
}
#endif
diff --git a/arch/arm/common/sa1111.c b/arch/arm/common/sa1111.c
index a12b33c..9c49a46 100644
--- a/arch/arm/common/sa1111.c
+++ b/arch/arm/common/sa1111.c
@@ -185,14 +185,6 @@
},
};
-void __init sa1111_adjust_zones(unsigned long *size, unsigned long *holes)
-{
- unsigned int sz = SZ_1M >> PAGE_SHIFT;
-
- size[1] = size[0] - sz;
- size[0] = sz;
-}
-
/*
* SA1111 interrupt support. Since clearing an IRQ while there are
* active IRQs causes the interrupt output to pulse, the upper levels
diff --git a/arch/arm/common/timer-sp.c b/arch/arm/common/timer-sp.c
index 6ef3342..41df478 100644
--- a/arch/arm/common/timer-sp.c
+++ b/arch/arm/common/timer-sp.c
@@ -18,53 +18,67 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*/
+#include <linux/clk.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
+#include <linux/err.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <asm/hardware/arm_timer.h>
-/*
- * These timers are currently always setup to be clocked at 1MHz.
- */
-#define TIMER_FREQ_KHZ (1000)
-#define TIMER_RELOAD (TIMER_FREQ_KHZ * 1000 / HZ)
-
-static void __iomem *clksrc_base;
-
-static cycle_t sp804_read(struct clocksource *cs)
+static long __init sp804_get_clock_rate(const char *name)
{
- return ~readl(clksrc_base + TIMER_VALUE);
+ struct clk *clk;
+ long rate;
+ int err;
+
+ clk = clk_get_sys("sp804", name);
+ if (IS_ERR(clk)) {
+ pr_err("sp804: %s clock not found: %d\n", name,
+ (int)PTR_ERR(clk));
+ return PTR_ERR(clk);
+ }
+
+ err = clk_enable(clk);
+ if (err) {
+ pr_err("sp804: %s clock failed to enable: %d\n", name, err);
+ clk_put(clk);
+ return err;
+ }
+
+ rate = clk_get_rate(clk);
+ if (rate < 0) {
+ pr_err("sp804: %s clock failed to get rate: %ld\n", name, rate);
+ clk_disable(clk);
+ clk_put(clk);
+ }
+
+ return rate;
}
-static struct clocksource clocksource_sp804 = {
- .name = "timer3",
- .rating = 200,
- .read = sp804_read,
- .mask = CLOCKSOURCE_MASK(32),
- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
-void __init sp804_clocksource_init(void __iomem *base)
+void __init sp804_clocksource_init(void __iomem *base, const char *name)
{
- struct clocksource *cs = &clocksource_sp804;
+ long rate = sp804_get_clock_rate(name);
- clksrc_base = base;
+ if (rate < 0)
+ return;
/* setup timer 0 as free-running clocksource */
- writel(0, clksrc_base + TIMER_CTRL);
- writel(0xffffffff, clksrc_base + TIMER_LOAD);
- writel(0xffffffff, clksrc_base + TIMER_VALUE);
+ writel(0, base + TIMER_CTRL);
+ writel(0xffffffff, base + TIMER_LOAD);
+ writel(0xffffffff, base + TIMER_VALUE);
writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
- clksrc_base + TIMER_CTRL);
+ base + TIMER_CTRL);
- clocksource_register_khz(cs, TIMER_FREQ_KHZ);
+ clocksource_mmio_init(base + TIMER_VALUE, name,
+ rate, 200, 32, clocksource_mmio_readl_down);
}
static void __iomem *clkevt_base;
+static unsigned long clkevt_reload;
/*
* IRQ handler for the timer
@@ -90,7 +104,7 @@
switch (mode) {
case CLOCK_EVT_MODE_PERIODIC:
- writel(TIMER_RELOAD, clkevt_base + TIMER_LOAD);
+ writel(clkevt_reload, clkevt_base + TIMER_LOAD);
ctrl |= TIMER_CTRL_PERIODIC | TIMER_CTRL_ENABLE;
break;
@@ -120,7 +134,6 @@
}
static struct clock_event_device sp804_clockevent = {
- .name = "timer0",
.shift = 32,
.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
.set_mode = sp804_set_mode,
@@ -136,17 +149,24 @@
.dev_id = &sp804_clockevent,
};
-void __init sp804_clockevents_init(void __iomem *base, unsigned int timer_irq)
+void __init sp804_clockevents_init(void __iomem *base, unsigned int irq,
+ const char *name)
{
struct clock_event_device *evt = &sp804_clockevent;
+ long rate = sp804_get_clock_rate(name);
+
+ if (rate < 0)
+ return;
clkevt_base = base;
+ clkevt_reload = DIV_ROUND_CLOSEST(rate, HZ);
- evt->irq = timer_irq;
- evt->mult = div_sc(TIMER_FREQ_KHZ, NSEC_PER_MSEC, evt->shift);
+ evt->name = name;
+ evt->irq = irq;
+ evt->mult = div_sc(rate, NSEC_PER_SEC, evt->shift);
evt->max_delta_ns = clockevent_delta2ns(0xffffffff, evt);
evt->min_delta_ns = clockevent_delta2ns(0xf, evt);
- setup_irq(timer_irq, &sp804_timer_irq);
+ setup_irq(irq, &sp804_timer_irq);
clockevents_register_device(evt);
}
diff --git a/arch/arm/configs/dove_defconfig b/arch/arm/configs/dove_defconfig
index 54bf5ee..40db34c 100644
--- a/arch/arm/configs/dove_defconfig
+++ b/arch/arm/configs/dove_defconfig
@@ -8,8 +8,6 @@
# CONFIG_BLK_DEV_BSG is not set
CONFIG_ARCH_DOVE=y
CONFIG_MACH_DOVE_DB=y
-CONFIG_CPU_V6=y
-CONFIG_CPU_32v6K=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
CONFIG_AEABI=y
@@ -44,7 +42,6 @@
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_BLK_DEV_RAM_COUNT=1
-# CONFIG_MISC_DEVICES is not set
# CONFIG_SCSI_PROC_FS is not set
CONFIG_BLK_DEV_SD=y
# CONFIG_SCSI_LOWLEVEL is not set
@@ -59,12 +56,12 @@
# CONFIG_KEYBOARD_ATKBD is not set
# CONFIG_MOUSE_PS2 is not set
# CONFIG_SERIO is not set
+CONFIG_LEGACY_PTY_COUNT=16
# CONFIG_DEVKMEM is not set
CONFIG_SERIAL_8250=y
CONFIG_SERIAL_8250_CONSOLE=y
# CONFIG_SERIAL_8250_PCI is not set
CONFIG_SERIAL_8250_RUNTIME_UARTS=2
-CONFIG_LEGACY_PTY_COUNT=16
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
@@ -72,12 +69,10 @@
CONFIG_SPI=y
CONFIG_SPI_ORION=y
# CONFIG_HWMON is not set
-# CONFIG_VGA_CONSOLE is not set
CONFIG_USB=y
CONFIG_USB_DEVICEFS=y
CONFIG_USB_EHCI_HCD=y
CONFIG_USB_EHCI_ROOT_HUB_TT=y
-CONFIG_USB_EHCI_TT_NEWSCHED=y
CONFIG_USB_STORAGE=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_MV=y
@@ -86,7 +81,6 @@
CONFIG_EXT2_FS=y
CONFIG_EXT3_FS=y
# CONFIG_EXT3_FS_XATTR is not set
-CONFIG_INOTIFY=y
CONFIG_ISO9660_FS=y
CONFIG_JOLIET=y
CONFIG_UDF_FS=m
@@ -110,23 +104,19 @@
CONFIG_TIMER_STATS=y
# CONFIG_DEBUG_BUGVERBOSE is not set
CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
CONFIG_SYSCTL_SYSCALL_CHECK=y
CONFIG_DEBUG_USER=y
CONFIG_DEBUG_ERRORS=y
CONFIG_CRYPTO_NULL=y
-CONFIG_CRYPTO_CBC=y
CONFIG_CRYPTO_ECB=m
CONFIG_CRYPTO_PCBC=m
CONFIG_CRYPTO_HMAC=y
CONFIG_CRYPTO_MD4=y
-CONFIG_CRYPTO_MD5=y
CONFIG_CRYPTO_SHA1=y
CONFIG_CRYPTO_SHA256=y
CONFIG_CRYPTO_SHA512=y
CONFIG_CRYPTO_AES=y
CONFIG_CRYPTO_BLOWFISH=y
-CONFIG_CRYPTO_DES=y
CONFIG_CRYPTO_TEA=y
CONFIG_CRYPTO_TWOFISH=y
CONFIG_CRYPTO_DEFLATE=y
diff --git a/arch/arm/configs/mx1_defconfig b/arch/arm/configs/mx1_defconfig
index b39b5ce..c9436d0 100644
--- a/arch/arm/configs/mx1_defconfig
+++ b/arch/arm/configs/mx1_defconfig
@@ -15,6 +15,7 @@
CONFIG_ARCH_MX1=y
CONFIG_ARCH_MX1ADS=y
CONFIG_MACH_SCB9328=y
+CONFIG_MACH_APF9328=y
CONFIG_MXC_IRQ_PRIOR=y
CONFIG_NO_HZ=y
CONFIG_HIGH_RES_TIMERS=y
diff --git a/arch/arm/configs/mx51_defconfig b/arch/arm/configs/mx51_defconfig
index e3c9032..0ace16c 100644
--- a/arch/arm/configs/mx51_defconfig
+++ b/arch/arm/configs/mx51_defconfig
@@ -13,7 +13,7 @@
# CONFIG_LBDAF is not set
# CONFIG_BLK_DEV_BSG is not set
CONFIG_ARCH_MXC=y
-CONFIG_ARCH_MX5=y
+CONFIG_ARCH_MX51=y
CONFIG_MACH_MX51_BABBAGE=y
CONFIG_MACH_MX51_3DS=y
CONFIG_MACH_EUKREA_CPUIMX51=y
diff --git a/arch/arm/configs/mxs_defconfig b/arch/arm/configs/mxs_defconfig
new file mode 100644
index 0000000..2bf2243
--- /dev/null
+++ b/arch/arm/configs/mxs_defconfig
@@ -0,0 +1,129 @@
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+# CONFIG_UTS_NS is not set
+# CONFIG_IPC_NS is not set
+# CONFIG_USER_NS is not set
+# CONFIG_PID_NS is not set
+# CONFIG_NET_NS is not set
+CONFIG_PERF_EVENTS=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODULE_FORCE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_BLK_DEV_INTEGRITY=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_ARCH_MXS=y
+CONFIG_MACH_STMP378X_DEVB=y
+CONFIG_MACH_TX28=y
+# CONFIG_ARM_THUMB is not set
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT_VOLUNTARY=y
+CONFIG_AEABI=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=65536
+CONFIG_AUTO_ZRELADDR=y
+CONFIG_FPE_NWFPE=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_IPV6 is not set
+CONFIG_CAN=m
+CONFIG_CAN_RAW=m
+CONFIG_CAN_BCM=m
+CONFIG_CAN_DEV=m
+CONFIG_CAN_FLEXCAN=m
+# CONFIG_WIRELESS is not set
+CONFIG_DEVTMPFS=y
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+# CONFIG_BLK_DEV is not set
+CONFIG_NETDEVICES=y
+CONFIG_NET_ETHERNET=y
+CONFIG_ENC28J60=y
+# CONFIG_NETDEV_1000 is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_WLAN is not set
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_EVDEV=m
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_INPUT_TOUCHSCREEN=y
+CONFIG_TOUCHSCREEN_TSC2007=m
+# CONFIG_SERIO is not set
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_DEVKMEM is not set
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+# CONFIG_HW_RANDOM is not set
+CONFIG_I2C=m
+# CONFIG_I2C_COMPAT is not set
+CONFIG_I2C_CHARDEV=m
+CONFIG_I2C_MXS=m
+CONFIG_SPI=y
+CONFIG_SPI_GPIO=m
+CONFIG_DEBUG_GPIO=y
+CONFIG_GPIO_SYSFS=y
+# CONFIG_HWMON is not set
+# CONFIG_MFD_SUPPORT is not set
+CONFIG_DISPLAY_SUPPORT=m
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+CONFIG_MMC=y
+CONFIG_MMC_MXS=y
+CONFIG_RTC_CLASS=m
+CONFIG_RTC_DRV_DS1307=m
+CONFIG_DMADEVICES=y
+CONFIG_MXS_DMA=y
+CONFIG_EXT3_FS=y
+# CONFIG_DNOTIFY is not set
+CONFIG_FSCACHE=m
+CONFIG_FSCACHE_STATS=y
+CONFIG_CACHEFILES=m
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+# CONFIG_MISC_FILESYSTEMS is not set
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_ROOT_NFS=y
+CONFIG_PRINTK_TIME=y
+CONFIG_FRAME_WARN=2048
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_UNUSED_SYMBOLS=y
+CONFIG_DEBUG_KERNEL=y
+CONFIG_LOCKUP_DETECTOR=y
+CONFIG_DETECT_HUNG_TASK=y
+CONFIG_TIMER_STATS=y
+CONFIG_PROVE_LOCKING=y
+CONFIG_DEBUG_SPINLOCK_SLEEP=y
+CONFIG_DEBUG_INFO=y
+CONFIG_SYSCTL_SYSCALL_CHECK=y
+CONFIG_BLK_DEV_IO_TRACE=y
+CONFIG_STRICT_DEVMEM=y
+CONFIG_DEBUG_USER=y
+CONFIG_CRYPTO=y
+CONFIG_CRYPTO_CRC32C=m
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_HW is not set
+CONFIG_CRC_ITU_T=m
+CONFIG_CRC7=m
diff --git a/arch/arm/configs/ns9xxx_defconfig b/arch/arm/configs/ns9xxx_defconfig
deleted file mode 100644
index 1f528a0..0000000
--- a/arch/arm/configs/ns9xxx_defconfig
+++ /dev/null
@@ -1,56 +0,0 @@
-CONFIG_IKCONFIG=y
-CONFIG_IKCONFIG_PROC=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_ARCH_NS9XXX=y
-CONFIG_MACH_CC9P9360DEV=y
-CONFIG_MACH_CC9P9360JS=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_FPE_NWFPE=y
-CONFIG_NET=y
-CONFIG_PACKET=m
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_SYN_COOKIES=y
-CONFIG_MTD=m
-CONFIG_MTD_CONCAT=m
-CONFIG_MTD_CHAR=m
-CONFIG_MTD_BLOCK=m
-CONFIG_MTD_CFI=m
-CONFIG_MTD_JEDECPROBE=m
-CONFIG_MTD_CFI_AMDSTD=m
-CONFIG_MTD_PHYSMAP=m
-CONFIG_BLK_DEV_LOOP=m
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-# CONFIG_SERIO_SERPORT is not set
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_I2C=m
-CONFIG_I2C_GPIO=m
-# CONFIG_HWMON is not set
-# CONFIG_VGA_CONSOLE is not set
-# CONFIG_USB_SUPPORT is not set
-CONFIG_NEW_LEDS=y
-CONFIG_LEDS_CLASS=m
-CONFIG_LEDS_GPIO=m
-CONFIG_LEDS_TRIGGERS=y
-CONFIG_LEDS_TRIGGER_TIMER=m
-CONFIG_LEDS_TRIGGER_HEARTBEAT=m
-CONFIG_RTC_CLASS=m
-CONFIG_EXT2_FS=m
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=m
-CONFIG_NFS_FS=y
-CONFIG_ROOT_NFS=y
-# CONFIG_ENABLE_MUST_CHECK is not set
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_ERRORS=y
diff --git a/arch/arm/configs/realview-smp_defconfig b/arch/arm/configs/realview-smp_defconfig
index 5ca7a61..abe61bf 100644
--- a/arch/arm/configs/realview-smp_defconfig
+++ b/arch/arm/configs/realview-smp_defconfig
@@ -38,7 +38,7 @@
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_ARM_INTEGRATOR=y
+CONFIG_MTD_PHYSMAP=y
CONFIG_ARM_CHARLCD=y
CONFIG_NETDEVICES=y
CONFIG_SMSC_PHY=y
diff --git a/arch/arm/configs/realview_defconfig b/arch/arm/configs/realview_defconfig
index fcaa603..7079cbe 100644
--- a/arch/arm/configs/realview_defconfig
+++ b/arch/arm/configs/realview_defconfig
@@ -37,7 +37,7 @@
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_INTELEXT=y
CONFIG_MTD_CFI_AMDSTD=y
-CONFIG_MTD_ARM_INTEGRATOR=y
+CONFIG_MTD_PHYSMAP=y
CONFIG_ARM_CHARLCD=y
CONFIG_NETDEVICES=y
CONFIG_SMSC_PHY=y
diff --git a/arch/arm/configs/spear300_defconfig b/arch/arm/configs/spear300_defconfig
deleted file mode 100644
index cf29f3e..0000000
--- a/arch/arm/configs/spear300_defconfig
+++ /dev/null
@@ -1,51 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_KALLSYMS_EXTRA_PASS=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_PLAT_SPEAR=y
-CONFIG_BINFMT_MISC=y
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=16384
-CONFIG_INPUT_FF_MEMLESS=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_SERIAL_AMBA_PL011=y
-CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_RAW_DRIVER=y
-CONFIG_MAX_RAW_DEVS=8192
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_PL061=y
-# CONFIG_HWMON is not set
-# CONFIG_VGA_CONSOLE is not set
-# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT2_FS_SECURITY=y
-CONFIG_EXT3_FS=y
-CONFIG_EXT3_FS_SECURITY=y
-CONFIG_AUTOFS4_FS=m
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
-CONFIG_TMPFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="utf8"
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=m
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_SPINLOCK=y
-CONFIG_DEBUG_SPINLOCK_SLEEP=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_CRC32 is not set
diff --git a/arch/arm/configs/spear310_defconfig b/arch/arm/configs/spear310_defconfig
deleted file mode 100644
index 824e444..0000000
--- a/arch/arm/configs/spear310_defconfig
+++ /dev/null
@@ -1,52 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_KALLSYMS_EXTRA_PASS=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_PLAT_SPEAR=y
-CONFIG_MACH_SPEAR310=y
-CONFIG_BINFMT_MISC=y
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=16384
-CONFIG_INPUT_FF_MEMLESS=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_SERIAL_AMBA_PL011=y
-CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_RAW_DRIVER=y
-CONFIG_MAX_RAW_DEVS=8192
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_PL061=y
-# CONFIG_HWMON is not set
-# CONFIG_VGA_CONSOLE is not set
-# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT2_FS_SECURITY=y
-CONFIG_EXT3_FS=y
-CONFIG_EXT3_FS_SECURITY=y
-CONFIG_AUTOFS4_FS=m
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
-CONFIG_TMPFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="utf8"
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=m
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_SPINLOCK=y
-CONFIG_DEBUG_SPINLOCK_SLEEP=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_CRC32 is not set
diff --git a/arch/arm/configs/spear320_defconfig b/arch/arm/configs/spear320_defconfig
deleted file mode 100644
index 842f7f3..0000000
--- a/arch/arm/configs/spear320_defconfig
+++ /dev/null
@@ -1,52 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_KALLSYMS_EXTRA_PASS=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_PLAT_SPEAR=y
-CONFIG_MACH_SPEAR320=y
-CONFIG_BINFMT_MISC=y
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=16384
-CONFIG_INPUT_FF_MEMLESS=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_SERIAL_AMBA_PL011=y
-CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_RAW_DRIVER=y
-CONFIG_MAX_RAW_DEVS=8192
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_PL061=y
-# CONFIG_HWMON is not set
-# CONFIG_VGA_CONSOLE is not set
-# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT2_FS_SECURITY=y
-CONFIG_EXT3_FS=y
-CONFIG_EXT3_FS_SECURITY=y
-CONFIG_AUTOFS4_FS=m
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
-CONFIG_TMPFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="utf8"
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=m
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_SPINLOCK=y
-CONFIG_DEBUG_SPINLOCK_SLEEP=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_CRC32 is not set
diff --git a/arch/arm/configs/spear3xx_defconfig b/arch/arm/configs/spear3xx_defconfig
new file mode 100644
index 0000000..fea7e1f
--- /dev/null
+++ b/arch/arm/configs/spear3xx_defconfig
@@ -0,0 +1,53 @@
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_KALLSYMS_EXTRA_PASS=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_PLAT_SPEAR=y
+CONFIG_BOARD_SPEAR300_EVB=y
+CONFIG_BOARD_SPEAR310_EVB=y
+CONFIG_BOARD_SPEAR320_EVB=y
+CONFIG_BINFMT_MISC=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_INPUT_FF_MEMLESS=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_HW_RANDOM is not set
+CONFIG_RAW_DRIVER=y
+CONFIG_MAX_RAW_DEVS=8192
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_PL061=y
+# CONFIG_HWMON is not set
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_SECURITY=y
+CONFIG_AUTOFS4_FS=m
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=m
+CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
+CONFIG_TMPFS=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="utf8"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ASCII=m
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_FS=y
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_SPINLOCK=y
+CONFIG_DEBUG_SPINLOCK_SLEEP=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_CRC32 is not set
diff --git a/arch/arm/configs/spear600_defconfig b/arch/arm/configs/spear600_defconfig
deleted file mode 100644
index 6777c11..0000000
--- a/arch/arm/configs/spear600_defconfig
+++ /dev/null
@@ -1,49 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_KALLSYMS_EXTRA_PASS=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_PLAT_SPEAR=y
-CONFIG_ARCH_SPEAR6XX=y
-CONFIG_BINFMT_MISC=y
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=16384
-CONFIG_INPUT_FF_MEMLESS=y
-# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
-CONFIG_SERIAL_AMBA_PL011=y
-CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_RAW_DRIVER=y
-CONFIG_MAX_RAW_DEVS=8192
-CONFIG_GPIO_SYSFS=y
-CONFIG_GPIO_PL061=y
-# CONFIG_HWMON is not set
-# CONFIG_VGA_CONSOLE is not set
-# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
-CONFIG_EXT2_FS=y
-CONFIG_EXT2_FS_XATTR=y
-CONFIG_EXT2_FS_SECURITY=y
-CONFIG_EXT3_FS=y
-CONFIG_EXT3_FS_SECURITY=y
-CONFIG_AUTOFS4_FS=m
-CONFIG_MSDOS_FS=m
-CONFIG_VFAT_FS=m
-CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
-CONFIG_TMPFS=y
-CONFIG_PARTITION_ADVANCED=y
-CONFIG_NLS=y
-CONFIG_NLS_DEFAULT="utf8"
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ASCII=m
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_FS=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_SPINLOCK=y
-CONFIG_DEBUG_SPINLOCK_SLEEP=y
-CONFIG_DEBUG_INFO=y
-# CONFIG_CRC32 is not set
diff --git a/arch/arm/configs/spear6xx_defconfig b/arch/arm/configs/spear6xx_defconfig
new file mode 100644
index 0000000..cef2e83
--- /dev/null
+++ b/arch/arm/configs/spear6xx_defconfig
@@ -0,0 +1,49 @@
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_KALLSYMS_EXTRA_PASS=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_PLAT_SPEAR=y
+CONFIG_ARCH_SPEAR6XX=y
+CONFIG_BOARD_SPEAR600_EVB=y
+CONFIG_BINFMT_MISC=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_INPUT_FF_MEMLESS=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_SERIAL_AMBA_PL011=y
+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_RAW_DRIVER=y
+CONFIG_MAX_RAW_DEVS=8192
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_PL061=y
+# CONFIG_HWMON is not set
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_SECURITY=y
+CONFIG_AUTOFS4_FS=m
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=m
+CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
+CONFIG_TMPFS=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="utf8"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ASCII=m
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_DEBUG_FS=y
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_SPINLOCK=y
+CONFIG_DEBUG_SPINLOCK_SLEEP=y
+CONFIG_DEBUG_INFO=y
+# CONFIG_CRC32 is not set
diff --git a/arch/arm/configs/stmp378x_defconfig b/arch/arm/configs/stmp378x_defconfig
deleted file mode 100644
index 1079c2b..0000000
--- a/arch/arm/configs/stmp378x_defconfig
+++ /dev/null
@@ -1,128 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_LOCALVERSION="-default"
-CONFIG_SYSVIPC=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_SYSFS_DEPRECATED_V2=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_STMP3XXX=y
-CONFIG_ARCH_STMP378X=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-CONFIG_HIGHMEM=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttySDBG0,115200 mem=32M"
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_IP_ROUTE_MULTIPATH=y
-CONFIG_IP_ROUTE_VERBOSE=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_MROUTE=y
-CONFIG_IP_PIMSM_V1=y
-CONFIG_IP_PIMSM_V2=y
-CONFIG_SYN_COOKIES=y
-# CONFIG_INET_LRO is not set
-# CONFIG_IPV6 is not set
-CONFIG_NET_SCHED=y
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_STANDALONE is not set
-CONFIG_MTD=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_NAND=y
-CONFIG_MTD_UBI=y
-CONFIG_MTD_UBI_GLUEBI=y
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_CRYPTOLOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=4
-CONFIG_BLK_DEV_RAM_SIZE=6144
-# CONFIG_MISC_DEVICES is not set
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_CHR_DEV_SG=y
-# CONFIG_SCSI_LOWLEVEL is not set
-CONFIG_INPUT_POLLDEV=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=320
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240
-CONFIG_INPUT_EVDEV=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_INPUT_MISC=y
-# CONFIG_SERIO_SERPORT is not set
-CONFIG_VT_HW_CONSOLE_BINDING=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_HW_RANDOM=y
-CONFIG_DEBUG_GPIO=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_FB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-CONFIG_LCD_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_LOGO=y
-# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_TMPFS=y
-CONFIG_CONFIGFS_FS=m
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-# CONFIG_ENABLE_MUST_CHECK is not set
-CONFIG_STRIP_ASM_SYMS=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_SHIRQ=y
-# CONFIG_SCHED_DEBUG is not set
-CONFIG_DEBUG_OBJECTS=y
-CONFIG_DEBUG_OBJECTS_SELFTEST=y
-CONFIG_DEBUG_OBJECTS_FREE=y
-CONFIG_DEBUG_OBJECTS_TIMERS=y
-CONFIG_DEBUG_SLAB=y
-CONFIG_DEBUG_SLAB_LEAK=y
-CONFIG_DEBUG_RT_MUTEXES=y
-CONFIG_PROVE_LOCKING=y
-CONFIG_DEBUG_SPINLOCK_SLEEP=y
-CONFIG_DEBUG_KOBJECT=y
-# CONFIG_DEBUG_BUGVERBOSE is not set
-CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_SYSCTL_SYSCALL_CHECK=y
-CONFIG_BOOT_TRACER=y
-CONFIG_STACK_TRACER=y
-CONFIG_BLK_DEV_IO_TRACE=y
-CONFIG_KEYS=y
-CONFIG_KEYS_DEBUG_PROC_KEYS=y
-CONFIG_SECURITY=y
-CONFIG_CRYPTO_TEST=m
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_MD5=y
-CONFIG_CRYPTO_SHA1=m
-CONFIG_CRYPTO_AES=m
-CONFIG_CRYPTO_DES=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_LZO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRC_CCITT=m
-CONFIG_CRC16=y
diff --git a/arch/arm/configs/stmp37xx_defconfig b/arch/arm/configs/stmp37xx_defconfig
deleted file mode 100644
index 564a5cc..0000000
--- a/arch/arm/configs/stmp37xx_defconfig
+++ /dev/null
@@ -1,108 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_LOCALVERSION="-default"
-CONFIG_SYSVIPC=y
-CONFIG_POSIX_MQUEUE=y
-CONFIG_BSD_PROCESS_ACCT=y
-CONFIG_SYSFS_DEPRECATED_V2=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_EXPERT=y
-CONFIG_SLAB=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-CONFIG_MODULE_FORCE_UNLOAD=y
-CONFIG_MODVERSIONS=y
-CONFIG_MODULE_SRCVERSION_ALL=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_ARCH_STMP3XXX=y
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_PREEMPT=y
-CONFIG_AEABI=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttySDBG0,115200 mem=32M lcd_panel=lms350 rdinit=/bin/sh ignore_loglevel"
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-CONFIG_IP_ADVANCED_ROUTER=y
-CONFIG_IP_MULTIPLE_TABLES=y
-CONFIG_IP_ROUTE_MULTIPATH=y
-CONFIG_IP_ROUTE_VERBOSE=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_DHCP=y
-CONFIG_IP_PNP_BOOTP=y
-CONFIG_IP_MROUTE=y
-CONFIG_IP_PIMSM_V1=y
-CONFIG_IP_PIMSM_V2=y
-CONFIG_SYN_COOKIES=y
-# CONFIG_INET_LRO is not set
-# CONFIG_IPV6 is not set
-CONFIG_NET_SCHED=y
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-# CONFIG_STANDALONE is not set
-CONFIG_BLK_DEV_LOOP=y
-CONFIG_BLK_DEV_CRYPTOLOOP=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_COUNT=4
-CONFIG_BLK_DEV_RAM_SIZE=6144
-# CONFIG_MISC_DEVICES is not set
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_CHR_DEV_SG=y
-# CONFIG_SCSI_LOWLEVEL is not set
-CONFIG_INPUT_POLLDEV=y
-CONFIG_INPUT_MOUSEDEV_SCREEN_X=320
-CONFIG_INPUT_MOUSEDEV_SCREEN_Y=240
-CONFIG_INPUT_EVDEV=y
-# CONFIG_KEYBOARD_ATKBD is not set
-# CONFIG_INPUT_MOUSE is not set
-CONFIG_INPUT_TOUCHSCREEN=y
-CONFIG_INPUT_MISC=y
-# CONFIG_SERIO_SERPORT is not set
-CONFIG_VT_HW_CONSOLE_BINDING=y
-# CONFIG_LEGACY_PTYS is not set
-CONFIG_HW_RANDOM=y
-CONFIG_DEBUG_GPIO=y
-CONFIG_GPIO_SYSFS=y
-# CONFIG_HWMON is not set
-CONFIG_FB=y
-CONFIG_BACKLIGHT_LCD_SUPPORT=y
-CONFIG_LCD_CLASS_DEVICE=y
-CONFIG_BACKLIGHT_CLASS_DEVICE=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_FRAMEBUFFER_CONSOLE=y
-CONFIG_LOGO=y
-# CONFIG_HID_SUPPORT is not set
-# CONFIG_USB_SUPPORT is not set
-# CONFIG_DNOTIFY is not set
-CONFIG_TMPFS=y
-CONFIG_CONFIGFS_FS=m
-# CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_NETWORK_FILESYSTEMS is not set
-# CONFIG_ENABLE_MUST_CHECK is not set
-CONFIG_DEBUG_KERNEL=y
-# CONFIG_DEBUG_BUGVERBOSE is not set
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_SYSCTL_SYSCALL_CHECK=y
-CONFIG_BOOT_TRACER=y
-CONFIG_STACK_TRACER=y
-CONFIG_BLK_DEV_IO_TRACE=y
-CONFIG_DEBUG_LL=y
-CONFIG_KEYS=y
-CONFIG_KEYS_DEBUG_PROC_KEYS=y
-CONFIG_SECURITY=y
-CONFIG_CRYPTO_TEST=m
-CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_HMAC=y
-CONFIG_CRYPTO_MD5=y
-CONFIG_CRYPTO_SHA1=m
-CONFIG_CRYPTO_AES=m
-CONFIG_CRYPTO_DES=y
-CONFIG_CRYPTO_DEFLATE=y
-CONFIG_CRYPTO_LZO=y
-# CONFIG_CRYPTO_ANSI_CPRNG is not set
-CONFIG_CRC_CCITT=m
-CONFIG_CRC16=y
diff --git a/arch/arm/configs/versatile_defconfig b/arch/arm/configs/versatile_defconfig
index 0ce710f..cdd4d2b 100644
--- a/arch/arm/configs/versatile_defconfig
+++ b/arch/arm/configs/versatile_defconfig
@@ -32,7 +32,7 @@
CONFIG_MTD_CFI=y
CONFIG_MTD_CFI_ADV_OPTIONS=y
CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_ARM_INTEGRATOR=y
+CONFIG_MTD_PHYSMAP=y
CONFIG_BLK_DEV_RAM=y
CONFIG_EEPROM_LEGACY=m
CONFIG_NETDEVICES=y
diff --git a/arch/arm/include/asm/dma.h b/arch/arm/include/asm/dma.h
index ca51143..4200554 100644
--- a/arch/arm/include/asm/dma.h
+++ b/arch/arm/include/asm/dma.h
@@ -6,8 +6,10 @@
/*
* This is the maximum virtual address which can be DMA'd from.
*/
-#ifndef MAX_DMA_ADDRESS
+#ifndef ARM_DMA_ZONE_SIZE
#define MAX_DMA_ADDRESS 0xffffffff
+#else
+#define MAX_DMA_ADDRESS (PAGE_OFFSET + ARM_DMA_ZONE_SIZE)
#endif
#ifdef CONFIG_ISA_DMA_API
diff --git a/arch/arm/include/asm/elf.h b/arch/arm/include/asm/elf.h
index c3cd875..0e9ce8d 100644
--- a/arch/arm/include/asm/elf.h
+++ b/arch/arm/include/asm/elf.h
@@ -108,6 +108,7 @@
int dump_task_regs(struct task_struct *t, elf_gregset_t *elfregs);
#define ELF_CORE_COPY_TASK_REGS dump_task_regs
+#define CORE_DUMP_USE_REGSET
#define ELF_EXEC_PAGESIZE 4096
/* This is the location that an ET_DYN program is loaded if exec'ed. Typical
diff --git a/arch/arm/include/asm/futex.h b/arch/arm/include/asm/futex.h
index 199a6b6..8c73900 100644
--- a/arch/arm/include/asm/futex.h
+++ b/arch/arm/include/asm/futex.h
@@ -3,16 +3,74 @@
#ifdef __KERNEL__
+#if defined(CONFIG_CPU_USE_DOMAINS) && defined(CONFIG_SMP)
+/* ARM doesn't provide unprivileged exclusive memory accessors */
+#include <asm-generic/futex.h>
+#else
+
+#include <linux/futex.h>
+#include <linux/uaccess.h>
+#include <asm/errno.h>
+
+#define __futex_atomic_ex_table(err_reg) \
+ "3:\n" \
+ " .pushsection __ex_table,\"a\"\n" \
+ " .align 3\n" \
+ " .long 1b, 4f, 2b, 4f\n" \
+ " .popsection\n" \
+ " .pushsection .fixup,\"ax\"\n" \
+ "4: mov %0, " err_reg "\n" \
+ " b 3b\n" \
+ " .popsection"
+
#ifdef CONFIG_SMP
-#include <asm-generic/futex.h>
+#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
+ smp_mb(); \
+ __asm__ __volatile__( \
+ "1: ldrex %1, [%2]\n" \
+ " " insn "\n" \
+ "2: strex %1, %0, [%2]\n" \
+ " teq %1, #0\n" \
+ " bne 1b\n" \
+ " mov %0, #0\n" \
+ __futex_atomic_ex_table("%4") \
+ : "=&r" (ret), "=&r" (oldval) \
+ : "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \
+ : "cc", "memory")
+
+static inline int
+futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
+ u32 oldval, u32 newval)
+{
+ int ret;
+ u32 val;
+
+ if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
+ return -EFAULT;
+
+ smp_mb();
+ __asm__ __volatile__("@futex_atomic_cmpxchg_inatomic\n"
+ "1: ldrex %1, [%4]\n"
+ " teq %1, %2\n"
+ " ite eq @ explicit IT needed for the 2b label\n"
+ "2: strexeq %0, %3, [%4]\n"
+ " movne %0, #0\n"
+ " teq %0, #0\n"
+ " bne 1b\n"
+ __futex_atomic_ex_table("%5")
+ : "=&r" (ret), "=&r" (val)
+ : "r" (oldval), "r" (newval), "r" (uaddr), "Ir" (-EFAULT)
+ : "cc", "memory");
+ smp_mb();
+
+ *uval = val;
+ return ret;
+}
#else /* !SMP, we can work around lack of atomic ops by disabling preemption */
-#include <linux/futex.h>
#include <linux/preempt.h>
-#include <linux/uaccess.h>
-#include <asm/errno.h>
#include <asm/domain.h>
#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
@@ -21,20 +79,38 @@
" " insn "\n" \
"2: " T(str) " %0, [%2]\n" \
" mov %0, #0\n" \
- "3:\n" \
- " .pushsection __ex_table,\"a\"\n" \
- " .align 3\n" \
- " .long 1b, 4f, 2b, 4f\n" \
- " .popsection\n" \
- " .pushsection .fixup,\"ax\"\n" \
- "4: mov %0, %4\n" \
- " b 3b\n" \
- " .popsection" \
+ __futex_atomic_ex_table("%4") \
: "=&r" (ret), "=&r" (oldval) \
: "r" (uaddr), "r" (oparg), "Ir" (-EFAULT) \
: "cc", "memory")
static inline int
+futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
+ u32 oldval, u32 newval)
+{
+ int ret = 0;
+ u32 val;
+
+ if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
+ return -EFAULT;
+
+ __asm__ __volatile__("@futex_atomic_cmpxchg_inatomic\n"
+ "1: " T(ldr) " %1, [%4]\n"
+ " teq %1, %2\n"
+ " it eq @ explicit IT needed for the 2b label\n"
+ "2: " T(streq) " %3, [%4]\n"
+ __futex_atomic_ex_table("%5")
+ : "+r" (ret), "=&r" (val)
+ : "r" (oldval), "r" (newval), "r" (uaddr), "Ir" (-EFAULT)
+ : "cc", "memory");
+
+ *uval = val;
+ return ret;
+}
+
+#endif /* !SMP */
+
+static inline int
futex_atomic_op_inuser (int encoded_op, u32 __user *uaddr)
{
int op = (encoded_op >> 28) & 7;
@@ -87,39 +163,6 @@
return ret;
}
-static inline int
-futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
- u32 oldval, u32 newval)
-{
- int ret = 0;
- u32 val;
-
- if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32)))
- return -EFAULT;
-
- __asm__ __volatile__("@futex_atomic_cmpxchg_inatomic\n"
- "1: " T(ldr) " %1, [%4]\n"
- " teq %1, %2\n"
- " it eq @ explicit IT needed for the 2b label\n"
- "2: " T(streq) " %3, [%4]\n"
- "3:\n"
- " .pushsection __ex_table,\"a\"\n"
- " .align 3\n"
- " .long 1b, 4f, 2b, 4f\n"
- " .popsection\n"
- " .pushsection .fixup,\"ax\"\n"
- "4: mov %0, %5\n"
- " b 3b\n"
- " .popsection"
- : "+r" (ret), "=&r" (val)
- : "r" (oldval), "r" (newval), "r" (uaddr), "Ir" (-EFAULT)
- : "cc", "memory");
-
- *uval = val;
- return ret;
-}
-
-#endif /* !SMP */
-
+#endif /* !(CPU_USE_DOMAINS && SMP) */
#endif /* __KERNEL__ */
#endif /* _ASM_ARM_FUTEX_H */
diff --git a/arch/arm/include/asm/hardware/timer-sp.h b/arch/arm/include/asm/hardware/timer-sp.h
index 21e75e3..4384d81 100644
--- a/arch/arm/include/asm/hardware/timer-sp.h
+++ b/arch/arm/include/asm/hardware/timer-sp.h
@@ -1,2 +1,2 @@
-void sp804_clocksource_init(void __iomem *);
-void sp804_clockevents_init(void __iomem *, unsigned int);
+void sp804_clocksource_init(void __iomem *, const char *);
+void sp804_clockevents_init(void __iomem *, unsigned int, const char *);
diff --git a/arch/arm/include/asm/memory.h b/arch/arm/include/asm/memory.h
index 431077c..af44a8f 100644
--- a/arch/arm/include/asm/memory.h
+++ b/arch/arm/include/asm/memory.h
@@ -209,14 +209,10 @@
* allocations. This must be the smallest DMA mask in the system,
* so a successful GFP_DMA allocation will always satisfy this.
*/
-#ifndef ISA_DMA_THRESHOLD
+#ifndef ARM_DMA_ZONE_SIZE
#define ISA_DMA_THRESHOLD (0xffffffffULL)
-#endif
-
-#ifndef arch_adjust_zones
-#define arch_adjust_zones(size,holes) do { } while (0)
-#elif !defined(CONFIG_ZONE_DMA)
-#error "custom arch_adjust_zones() requires CONFIG_ZONE_DMA"
+#else
+#define ISA_DMA_THRESHOLD (PHYS_OFFSET + ARM_DMA_ZONE_SIZE - 1)
#endif
/*
diff --git a/arch/arm/include/asm/ptrace.h b/arch/arm/include/asm/ptrace.h
index a8ff22b..312d108 100644
--- a/arch/arm/include/asm/ptrace.h
+++ b/arch/arm/include/asm/ptrace.h
@@ -128,6 +128,12 @@
#define ARM_r0 uregs[0]
#define ARM_ORIG_r0 uregs[17]
+/*
+ * The size of the user-visible VFP state as seen by PTRACE_GET/SETVFPREGS
+ * and core dumps.
+ */
+#define ARM_VFPREGS_SIZE ( 32 * 8 /*fpregs*/ + 4 /*fpscr*/ )
+
#ifdef __KERNEL__
#define user_mode(regs) \
diff --git a/arch/arm/include/asm/sizes.h b/arch/arm/include/asm/sizes.h
index 316bb2b..154b89b 100644
--- a/arch/arm/include/asm/sizes.h
+++ b/arch/arm/include/asm/sizes.h
@@ -16,44 +16,6 @@
/* Size definitions
* Copyright (C) ARM Limited 1998. All rights reserved.
*/
+#include <asm-generic/sizes.h>
-#ifndef __sizes_h
-#define __sizes_h 1
-
-/* handy sizes */
-#define SZ_16 0x00000010
-#define SZ_32 0x00000020
-#define SZ_64 0x00000040
-#define SZ_128 0x00000080
-#define SZ_256 0x00000100
-#define SZ_512 0x00000200
-
-#define SZ_1K 0x00000400
-#define SZ_2K 0x00000800
-#define SZ_4K 0x00001000
-#define SZ_8K 0x00002000
-#define SZ_16K 0x00004000
-#define SZ_32K 0x00008000
-#define SZ_64K 0x00010000
-#define SZ_128K 0x00020000
-#define SZ_256K 0x00040000
-#define SZ_512K 0x00080000
-
-#define SZ_1M 0x00100000
-#define SZ_2M 0x00200000
-#define SZ_4M 0x00400000
-#define SZ_8M 0x00800000
-#define SZ_16M 0x01000000
-#define SZ_32M 0x02000000
-#define SZ_48M 0x03000000
-#define SZ_64M 0x04000000
-#define SZ_128M 0x08000000
-#define SZ_256M 0x10000000
-#define SZ_512M 0x20000000
-
-#define SZ_1G 0x40000000
-#define SZ_2G 0x80000000
-
-#endif
-
-/* END */
+#define SZ_48M (SZ_32M + SZ_16M)
diff --git a/arch/arm/include/asm/smp.h b/arch/arm/include/asm/smp.h
index 96ed521..d2b514f 100644
--- a/arch/arm/include/asm/smp.h
+++ b/arch/arm/include/asm/smp.h
@@ -14,20 +14,12 @@
#include <linux/cpumask.h>
#include <linux/thread_info.h>
-#include <mach/smp.h>
-
#ifndef CONFIG_SMP
# error "<asm/smp.h> included in non-SMP build"
#endif
#define raw_smp_processor_id() (current_thread_info()->cpu)
-/*
- * at the moment, there's not a big penalty for changing CPUs
- * (the >big< penalty is running SMP in the first place)
- */
-#define PROC_CHANGE_PENALTY 15
-
struct seq_file;
/*
@@ -47,9 +39,9 @@
/*
- * Raise an IPI cross call on CPUs in callmap.
+ * Provide a function to raise an IPI cross call on CPUs in callmap.
*/
-extern void smp_cross_call(const struct cpumask *mask, int ipi);
+extern void set_smp_cross_call(void (*)(const struct cpumask *, unsigned int));
/*
* Boot a secondary CPU, and assign it the specified idle task.
diff --git a/arch/arm/include/asm/spinlock.h b/arch/arm/include/asm/spinlock.h
index fdd3820..65fa3c8 100644
--- a/arch/arm/include/asm/spinlock.h
+++ b/arch/arm/include/asm/spinlock.h
@@ -5,6 +5,8 @@
#error SMP not supported on pre-ARMv6 CPUs
#endif
+#include <asm/processor.h>
+
/*
* sev and wfe are ARMv6K extensions. Uniprocessor ARMv6 may not have the K
* extensions, so when running on UP, we have to patch these instructions away.
diff --git a/arch/arm/include/asm/tlb.h b/arch/arm/include/asm/tlb.h
index 82dfe5d..265f908 100644
--- a/arch/arm/include/asm/tlb.h
+++ b/arch/arm/include/asm/tlb.h
@@ -41,12 +41,12 @@
*/
#if defined(CONFIG_SMP) || defined(CONFIG_CPU_32v7)
#define tlb_fast_mode(tlb) 0
-#define FREE_PTE_NR 500
#else
#define tlb_fast_mode(tlb) 1
-#define FREE_PTE_NR 0
#endif
+#define MMU_GATHER_BUNDLE 8
+
/*
* TLB handling. This allows us to remove pages from the page
* tables, and efficiently handle the TLB issues.
@@ -58,7 +58,9 @@
unsigned long range_start;
unsigned long range_end;
unsigned int nr;
- struct page *pages[FREE_PTE_NR];
+ unsigned int max;
+ struct page **pages;
+ struct page *local[MMU_GATHER_BUNDLE];
};
DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
@@ -97,26 +99,37 @@
}
}
+static inline void __tlb_alloc_page(struct mmu_gather *tlb)
+{
+ unsigned long addr = __get_free_pages(GFP_NOWAIT | __GFP_NOWARN, 0);
+
+ if (addr) {
+ tlb->pages = (void *)addr;
+ tlb->max = PAGE_SIZE / sizeof(struct page *);
+ }
+}
+
static inline void tlb_flush_mmu(struct mmu_gather *tlb)
{
tlb_flush(tlb);
if (!tlb_fast_mode(tlb)) {
free_pages_and_swap_cache(tlb->pages, tlb->nr);
tlb->nr = 0;
+ if (tlb->pages == tlb->local)
+ __tlb_alloc_page(tlb);
}
}
-static inline struct mmu_gather *
-tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
+static inline void
+tlb_gather_mmu(struct mmu_gather *tlb, struct mm_struct *mm, unsigned int fullmm)
{
- struct mmu_gather *tlb = &get_cpu_var(mmu_gathers);
-
tlb->mm = mm;
- tlb->fullmm = full_mm_flush;
+ tlb->fullmm = fullmm;
tlb->vma = NULL;
+ tlb->max = ARRAY_SIZE(tlb->local);
+ tlb->pages = tlb->local;
tlb->nr = 0;
-
- return tlb;
+ __tlb_alloc_page(tlb);
}
static inline void
@@ -127,7 +140,8 @@
/* keep the page table cache within bounds */
check_pgt_cache();
- put_cpu_var(mmu_gathers);
+ if (tlb->pages != tlb->local)
+ free_pages((unsigned long)tlb->pages, 0);
}
/*
@@ -162,15 +176,22 @@
tlb_flush(tlb);
}
-static inline void tlb_remove_page(struct mmu_gather *tlb, struct page *page)
+static inline int __tlb_remove_page(struct mmu_gather *tlb, struct page *page)
{
if (tlb_fast_mode(tlb)) {
free_page_and_swap_cache(page);
- } else {
- tlb->pages[tlb->nr++] = page;
- if (tlb->nr >= FREE_PTE_NR)
- tlb_flush_mmu(tlb);
+ return 1; /* avoid calling tlb_flush_mmu */
}
+
+ tlb->pages[tlb->nr++] = page;
+ VM_BUG_ON(tlb->nr > tlb->max);
+ return tlb->max - tlb->nr;
+}
+
+static inline void tlb_remove_page(struct mmu_gather *tlb, struct page *page)
+{
+ if (!__tlb_remove_page(tlb, page))
+ tlb_flush_mmu(tlb);
}
static inline void __pte_free_tlb(struct mmu_gather *tlb, pgtable_t pte,
diff --git a/arch/arm/kernel/perf_event.c b/arch/arm/kernel/perf_event.c
index 139e3c8..d53c0ab 100644
--- a/arch/arm/kernel/perf_event.c
+++ b/arch/arm/kernel/perf_event.c
@@ -560,11 +560,6 @@
event->destroy = hw_perf_event_destroy;
if (!atomic_inc_not_zero(&active_events)) {
- if (atomic_read(&active_events) > armpmu->num_events) {
- atomic_dec(&active_events);
- return -ENOSPC;
- }
-
mutex_lock(&pmu_reserve_mutex);
if (atomic_read(&active_events) == 0) {
err = armpmu_reserve_hardware();
diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
index 8182f45..9726006 100644
--- a/arch/arm/kernel/ptrace.c
+++ b/arch/arm/kernel/ptrace.c
@@ -21,6 +21,7 @@
#include <linux/uaccess.h>
#include <linux/perf_event.h>
#include <linux/hw_breakpoint.h>
+#include <linux/regset.h>
#include <asm/pgtable.h>
#include <asm/system.h>
@@ -308,58 +309,6 @@
return put_user_reg(tsk, off >> 2, val);
}
-/*
- * Get all user integer registers.
- */
-static int ptrace_getregs(struct task_struct *tsk, void __user *uregs)
-{
- struct pt_regs *regs = task_pt_regs(tsk);
-
- return copy_to_user(uregs, regs, sizeof(struct pt_regs)) ? -EFAULT : 0;
-}
-
-/*
- * Set all user integer registers.
- */
-static int ptrace_setregs(struct task_struct *tsk, void __user *uregs)
-{
- struct pt_regs newregs;
- int ret;
-
- ret = -EFAULT;
- if (copy_from_user(&newregs, uregs, sizeof(struct pt_regs)) == 0) {
- struct pt_regs *regs = task_pt_regs(tsk);
-
- ret = -EINVAL;
- if (valid_user_regs(&newregs)) {
- *regs = newregs;
- ret = 0;
- }
- }
-
- return ret;
-}
-
-/*
- * Get the child FPU state.
- */
-static int ptrace_getfpregs(struct task_struct *tsk, void __user *ufp)
-{
- return copy_to_user(ufp, &task_thread_info(tsk)->fpstate,
- sizeof(struct user_fp)) ? -EFAULT : 0;
-}
-
-/*
- * Set the child FPU state.
- */
-static int ptrace_setfpregs(struct task_struct *tsk, void __user *ufp)
-{
- struct thread_info *thread = task_thread_info(tsk);
- thread->used_cp[1] = thread->used_cp[2] = 1;
- return copy_from_user(&thread->fpstate, ufp,
- sizeof(struct user_fp)) ? -EFAULT : 0;
-}
-
#ifdef CONFIG_IWMMXT
/*
@@ -418,56 +367,6 @@
}
#endif
-#ifdef CONFIG_VFP
-/*
- * Get the child VFP state.
- */
-static int ptrace_getvfpregs(struct task_struct *tsk, void __user *data)
-{
- struct thread_info *thread = task_thread_info(tsk);
- union vfp_state *vfp = &thread->vfpstate;
- struct user_vfp __user *ufp = data;
-
- vfp_sync_hwstate(thread);
-
- /* copy the floating point registers */
- if (copy_to_user(&ufp->fpregs, &vfp->hard.fpregs,
- sizeof(vfp->hard.fpregs)))
- return -EFAULT;
-
- /* copy the status and control register */
- if (put_user(vfp->hard.fpscr, &ufp->fpscr))
- return -EFAULT;
-
- return 0;
-}
-
-/*
- * Set the child VFP state.
- */
-static int ptrace_setvfpregs(struct task_struct *tsk, void __user *data)
-{
- struct thread_info *thread = task_thread_info(tsk);
- union vfp_state *vfp = &thread->vfpstate;
- struct user_vfp __user *ufp = data;
-
- vfp_sync_hwstate(thread);
-
- /* copy the floating point registers */
- if (copy_from_user(&vfp->hard.fpregs, &ufp->fpregs,
- sizeof(vfp->hard.fpregs)))
- return -EFAULT;
-
- /* copy the status and control register */
- if (get_user(vfp->hard.fpscr, &ufp->fpscr))
- return -EFAULT;
-
- vfp_flush_hwstate(thread);
-
- return 0;
-}
-#endif
-
#ifdef CONFIG_HAVE_HW_BREAKPOINT
/*
* Convert a virtual register number into an index for a thread_info
@@ -694,6 +593,219 @@
}
#endif
+/* regset get/set implementations */
+
+static int gpr_get(struct task_struct *target,
+ const struct user_regset *regset,
+ unsigned int pos, unsigned int count,
+ void *kbuf, void __user *ubuf)
+{
+ struct pt_regs *regs = task_pt_regs(target);
+
+ return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
+ regs,
+ 0, sizeof(*regs));
+}
+
+static int gpr_set(struct task_struct *target,
+ const struct user_regset *regset,
+ unsigned int pos, unsigned int count,
+ const void *kbuf, const void __user *ubuf)
+{
+ int ret;
+ struct pt_regs newregs;
+
+ ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
+ &newregs,
+ 0, sizeof(newregs));
+ if (ret)
+ return ret;
+
+ if (!valid_user_regs(&newregs))
+ return -EINVAL;
+
+ *task_pt_regs(target) = newregs;
+ return 0;
+}
+
+static int fpa_get(struct task_struct *target,
+ const struct user_regset *regset,
+ unsigned int pos, unsigned int count,
+ void *kbuf, void __user *ubuf)
+{
+ return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
+ &task_thread_info(target)->fpstate,
+ 0, sizeof(struct user_fp));
+}
+
+static int fpa_set(struct task_struct *target,
+ const struct user_regset *regset,
+ unsigned int pos, unsigned int count,
+ const void *kbuf, const void __user *ubuf)
+{
+ struct thread_info *thread = task_thread_info(target);
+
+ thread->used_cp[1] = thread->used_cp[2] = 1;
+
+ return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
+ &thread->fpstate,
+ 0, sizeof(struct user_fp));
+}
+
+#ifdef CONFIG_VFP
+/*
+ * VFP register get/set implementations.
+ *
+ * With respect to the kernel, struct user_fp is divided into three chunks:
+ * 16 or 32 real VFP registers (d0-d15 or d0-31)
+ * These are transferred to/from the real registers in the task's
+ * vfp_hard_struct. The number of registers depends on the kernel
+ * configuration.
+ *
+ * 16 or 0 fake VFP registers (d16-d31 or empty)
+ * i.e., the user_vfp structure has space for 32 registers even if
+ * the kernel doesn't have them all.
+ *
+ * vfp_get() reads this chunk as zero where applicable
+ * vfp_set() ignores this chunk
+ *
+ * 1 word for the FPSCR
+ *
+ * The bounds-checking logic built into user_regset_copyout and friends
+ * means that we can make a simple sequence of calls to map the relevant data
+ * to/from the specified slice of the user regset structure.
+ */
+static int vfp_get(struct task_struct *target,
+ const struct user_regset *regset,
+ unsigned int pos, unsigned int count,
+ void *kbuf, void __user *ubuf)
+{
+ int ret;
+ struct thread_info *thread = task_thread_info(target);
+ struct vfp_hard_struct const *vfp = &thread->vfpstate.hard;
+ const size_t user_fpregs_offset = offsetof(struct user_vfp, fpregs);
+ const size_t user_fpscr_offset = offsetof(struct user_vfp, fpscr);
+
+ vfp_sync_hwstate(thread);
+
+ ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
+ &vfp->fpregs,
+ user_fpregs_offset,
+ user_fpregs_offset + sizeof(vfp->fpregs));
+ if (ret)
+ return ret;
+
+ ret = user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,
+ user_fpregs_offset + sizeof(vfp->fpregs),
+ user_fpscr_offset);
+ if (ret)
+ return ret;
+
+ return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
+ &vfp->fpscr,
+ user_fpscr_offset,
+ user_fpscr_offset + sizeof(vfp->fpscr));
+}
+
+/*
+ * For vfp_set() a read-modify-write is done on the VFP registers,
+ * in order to avoid writing back a half-modified set of registers on
+ * failure.
+ */
+static int vfp_set(struct task_struct *target,
+ const struct user_regset *regset,
+ unsigned int pos, unsigned int count,
+ const void *kbuf, const void __user *ubuf)
+{
+ int ret;
+ struct thread_info *thread = task_thread_info(target);
+ struct vfp_hard_struct new_vfp = thread->vfpstate.hard;
+ const size_t user_fpregs_offset = offsetof(struct user_vfp, fpregs);
+ const size_t user_fpscr_offset = offsetof(struct user_vfp, fpscr);
+
+ ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
+ &new_vfp.fpregs,
+ user_fpregs_offset,
+ user_fpregs_offset + sizeof(new_vfp.fpregs));
+ if (ret)
+ return ret;
+
+ ret = user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf,
+ user_fpregs_offset + sizeof(new_vfp.fpregs),
+ user_fpscr_offset);
+ if (ret)
+ return ret;
+
+ ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
+ &new_vfp.fpscr,
+ user_fpscr_offset,
+ user_fpscr_offset + sizeof(new_vfp.fpscr));
+ if (ret)
+ return ret;
+
+ vfp_sync_hwstate(thread);
+ thread->vfpstate.hard = new_vfp;
+ vfp_flush_hwstate(thread);
+
+ return 0;
+}
+#endif /* CONFIG_VFP */
+
+enum arm_regset {
+ REGSET_GPR,
+ REGSET_FPR,
+#ifdef CONFIG_VFP
+ REGSET_VFP,
+#endif
+};
+
+static const struct user_regset arm_regsets[] = {
+ [REGSET_GPR] = {
+ .core_note_type = NT_PRSTATUS,
+ .n = ELF_NGREG,
+ .size = sizeof(u32),
+ .align = sizeof(u32),
+ .get = gpr_get,
+ .set = gpr_set
+ },
+ [REGSET_FPR] = {
+ /*
+ * For the FPA regs in fpstate, the real fields are a mixture
+ * of sizes, so pretend that the registers are word-sized:
+ */
+ .core_note_type = NT_PRFPREG,
+ .n = sizeof(struct user_fp) / sizeof(u32),
+ .size = sizeof(u32),
+ .align = sizeof(u32),
+ .get = fpa_get,
+ .set = fpa_set
+ },
+#ifdef CONFIG_VFP
+ [REGSET_VFP] = {
+ /*
+ * Pretend that the VFP regs are word-sized, since the FPSCR is
+ * a single word dangling at the end of struct user_vfp:
+ */
+ .core_note_type = NT_ARM_VFP,
+ .n = ARM_VFPREGS_SIZE / sizeof(u32),
+ .size = sizeof(u32),
+ .align = sizeof(u32),
+ .get = vfp_get,
+ .set = vfp_set
+ },
+#endif /* CONFIG_VFP */
+};
+
+static const struct user_regset_view user_arm_view = {
+ .name = "arm", .e_machine = ELF_ARCH, .ei_osabi = ELF_OSABI,
+ .regsets = arm_regsets, .n = ARRAY_SIZE(arm_regsets)
+};
+
+const struct user_regset_view *task_user_regset_view(struct task_struct *task)
+{
+ return &user_arm_view;
+}
+
long arch_ptrace(struct task_struct *child, long request,
unsigned long addr, unsigned long data)
{
@@ -710,19 +822,31 @@
break;
case PTRACE_GETREGS:
- ret = ptrace_getregs(child, datap);
+ ret = copy_regset_to_user(child,
+ &user_arm_view, REGSET_GPR,
+ 0, sizeof(struct pt_regs),
+ datap);
break;
case PTRACE_SETREGS:
- ret = ptrace_setregs(child, datap);
+ ret = copy_regset_from_user(child,
+ &user_arm_view, REGSET_GPR,
+ 0, sizeof(struct pt_regs),
+ datap);
break;
case PTRACE_GETFPREGS:
- ret = ptrace_getfpregs(child, datap);
+ ret = copy_regset_to_user(child,
+ &user_arm_view, REGSET_FPR,
+ 0, sizeof(union fp_state),
+ datap);
break;
-
+
case PTRACE_SETFPREGS:
- ret = ptrace_setfpregs(child, datap);
+ ret = copy_regset_from_user(child,
+ &user_arm_view, REGSET_FPR,
+ 0, sizeof(union fp_state),
+ datap);
break;
#ifdef CONFIG_IWMMXT
@@ -757,11 +881,17 @@
#ifdef CONFIG_VFP
case PTRACE_GETVFPREGS:
- ret = ptrace_getvfpregs(child, datap);
+ ret = copy_regset_to_user(child,
+ &user_arm_view, REGSET_VFP,
+ 0, ARM_VFPREGS_SIZE,
+ datap);
break;
case PTRACE_SETVFPREGS:
- ret = ptrace_setvfpregs(child, datap);
+ ret = copy_regset_from_user(child,
+ &user_arm_view, REGSET_VFP,
+ 0, ARM_VFPREGS_SIZE,
+ datap);
break;
#endif
diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 006c1e8..6dce209 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -672,11 +672,16 @@
static int __init parse_tag_cmdline(const struct tag *tag)
{
-#ifndef CONFIG_CMDLINE_FORCE
- strlcpy(default_command_line, tag->u.cmdline.cmdline, COMMAND_LINE_SIZE);
-#else
+#if defined(CONFIG_CMDLINE_EXTEND)
+ strlcat(default_command_line, " ", COMMAND_LINE_SIZE);
+ strlcat(default_command_line, tag->u.cmdline.cmdline,
+ COMMAND_LINE_SIZE);
+#elif defined(CONFIG_CMDLINE_FORCE)
pr_warning("Ignoring tag cmdline (using the default kernel command line)\n");
-#endif /* CONFIG_CMDLINE_FORCE */
+#else
+ strlcpy(default_command_line, tag->u.cmdline.cmdline,
+ COMMAND_LINE_SIZE);
+#endif
return 0;
}
diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c
index 007a0a9..d439a8f 100644
--- a/arch/arm/kernel/smp.c
+++ b/arch/arm/kernel/smp.c
@@ -376,6 +376,13 @@
}
}
+static void (*smp_cross_call)(const struct cpumask *, unsigned int);
+
+void __init set_smp_cross_call(void (*fn)(const struct cpumask *, unsigned int))
+{
+ smp_cross_call = fn;
+}
+
void arch_send_call_function_ipi_mask(const struct cpumask *mask)
{
smp_cross_call(mask, IPI_CALL_FUNC);
diff --git a/arch/arm/kernel/vmlinux.lds.S b/arch/arm/kernel/vmlinux.lds.S
index b4348e6..e5287f2 100644
--- a/arch/arm/kernel/vmlinux.lds.S
+++ b/arch/arm/kernel/vmlinux.lds.S
@@ -82,7 +82,7 @@
#endif
}
- PERCPU(32, PAGE_SIZE)
+ PERCPU_SECTION(32)
#ifndef CONFIG_XIP_KERNEL
. = ALIGN(PAGE_SIZE);
diff --git a/arch/arm/mach-bcmring/arch.c b/arch/arm/mach-bcmring/arch.c
index 73eb066..a604b9e 100644
--- a/arch/arm/mach-bcmring/arch.c
+++ b/arch/arm/mach-bcmring/arch.c
@@ -169,6 +169,7 @@
/* Maintainer: Broadcom Corporation */
.fixup = bcmring_fixup,
.map_io = bcmring_map_io,
+ .init_early = bcmring_init_early,
.init_irq = bcmring_init_irq,
.timer = &bcmring_timer,
.init_machine = bcmring_init_machine
diff --git a/arch/arm/mach-bcmring/core.c b/arch/arm/mach-bcmring/core.c
index 8fc2035..43eadbc 100644
--- a/arch/arm/mach-bcmring/core.c
+++ b/arch/arm/mach-bcmring/core.c
@@ -28,8 +28,6 @@
#include <linux/sysdev.h>
#include <linux/interrupt.h>
#include <linux/amba/bus.h>
-#include <linux/clocksource.h>
-#include <linux/clockchips.h>
#include <linux/clkdev.h>
#include <mach/csp/mm_addr.h>
@@ -37,6 +35,7 @@
#include <linux/io.h>
#include <asm/irq.h>
#include <asm/hardware/arm_timer.h>
+#include <asm/hardware/timer-sp.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@@ -97,6 +96,35 @@
.mode = CLK_MODE_XTAL,
};
+/* Timer 0 - 25 MHz, Timer3 at bus clock rate, typically 150-166 MHz */
+#if defined(CONFIG_ARCH_FPGA11107)
+/* fpga cpu/bus are currently 30 times slower so scale frequency as well to */
+/* slow down Linux's sense of time */
+#define TIMER0_FREQUENCY_MHZ (tmrHw_LOW_FREQUENCY_MHZ * 30)
+#define TIMER1_FREQUENCY_MHZ (tmrHw_LOW_FREQUENCY_MHZ * 30)
+#define TIMER3_FREQUENCY_MHZ (tmrHw_HIGH_FREQUENCY_MHZ * 30)
+#define TIMER3_FREQUENCY_KHZ (tmrHw_HIGH_FREQUENCY_HZ / 1000 * 30)
+#else
+#define TIMER0_FREQUENCY_MHZ tmrHw_LOW_FREQUENCY_MHZ
+#define TIMER1_FREQUENCY_MHZ tmrHw_LOW_FREQUENCY_MHZ
+#define TIMER3_FREQUENCY_MHZ tmrHw_HIGH_FREQUENCY_MHZ
+#define TIMER3_FREQUENCY_KHZ (tmrHw_HIGH_FREQUENCY_HZ / 1000)
+#endif
+
+static struct clk sp804_timer012_clk = {
+ .name = "sp804-timer-0,1,2",
+ .type = CLK_TYPE_PRIMARY,
+ .mode = CLK_MODE_XTAL,
+ .rate_hz = TIMER1_FREQUENCY_MHZ * 1000000,
+};
+
+static struct clk sp804_timer3_clk = {
+ .name = "sp804-timer-3",
+ .type = CLK_TYPE_PRIMARY,
+ .mode = CLK_MODE_XTAL,
+ .rate_hz = TIMER3_FREQUENCY_KHZ * 1000,
+};
+
static struct clk_lookup lookups[] = {
{ /* Bus clock */
.con_id = "apb_pclk",
@@ -107,6 +135,18 @@
}, { /* UART1 */
.dev_id = "uartb",
.clk = &uart_clk,
+ }, { /* SP804 timer 0 */
+ .dev_id = "sp804",
+ .con_id = "timer0",
+ .clk = &sp804_timer012_clk,
+ }, { /* SP804 timer 1 */
+ .dev_id = "sp804",
+ .con_id = "timer1",
+ .clk = &sp804_timer012_clk,
+ }, { /* SP804 timer 3 */
+ .dev_id = "sp804",
+ .con_id = "timer3",
+ .clk = &sp804_timer3_clk,
}
};
@@ -151,8 +191,6 @@
chipcHw_busInterfaceClockEnable(bus_clock);
- clkdev_add_table(lookups, ARRAY_SIZE(lookups));
-
for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
struct amba_device *d = amba_devs[i];
amba_device_register(d, &iomem_resource);
@@ -162,170 +200,18 @@
/*
* Where is the timer (VA)?
*/
-#define TIMER0_VA_BASE MM_IO_BASE_TMR
-#define TIMER1_VA_BASE (MM_IO_BASE_TMR + 0x20)
-#define TIMER2_VA_BASE (MM_IO_BASE_TMR + 0x40)
-#define TIMER3_VA_BASE (MM_IO_BASE_TMR + 0x60)
-
-/* Timer 0 - 25 MHz, Timer3 at bus clock rate, typically 150-166 MHz */
-#if defined(CONFIG_ARCH_FPGA11107)
-/* fpga cpu/bus are currently 30 times slower so scale frequency as well to */
-/* slow down Linux's sense of time */
-#define TIMER0_FREQUENCY_MHZ (tmrHw_LOW_FREQUENCY_MHZ * 30)
-#define TIMER1_FREQUENCY_MHZ (tmrHw_LOW_FREQUENCY_MHZ * 30)
-#define TIMER3_FREQUENCY_MHZ (tmrHw_HIGH_FREQUENCY_MHZ * 30)
-#define TIMER3_FREQUENCY_KHZ (tmrHw_HIGH_FREQUENCY_HZ / 1000 * 30)
-#else
-#define TIMER0_FREQUENCY_MHZ tmrHw_LOW_FREQUENCY_MHZ
-#define TIMER1_FREQUENCY_MHZ tmrHw_LOW_FREQUENCY_MHZ
-#define TIMER3_FREQUENCY_MHZ tmrHw_HIGH_FREQUENCY_MHZ
-#define TIMER3_FREQUENCY_KHZ (tmrHw_HIGH_FREQUENCY_HZ / 1000)
-#endif
-
-#define TICKS_PER_uSEC TIMER0_FREQUENCY_MHZ
-
-/*
- * These are useconds NOT ticks.
- *
- */
-#define mSEC_1 1000
-#define mSEC_5 (mSEC_1 * 5)
-#define mSEC_10 (mSEC_1 * 10)
-#define mSEC_25 (mSEC_1 * 25)
-#define SEC_1 (mSEC_1 * 1000)
-
-/*
- * How long is the timer interval?
- */
-#define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10)
-#if TIMER_INTERVAL >= 0x100000
-#define TIMER_RELOAD (TIMER_INTERVAL >> 8)
-#define TIMER_DIVISOR (TIMER_CTRL_DIV256)
-#define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC)
-#elif TIMER_INTERVAL >= 0x10000
-#define TIMER_RELOAD (TIMER_INTERVAL >> 4) /* Divide by 16 */
-#define TIMER_DIVISOR (TIMER_CTRL_DIV16)
-#define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC)
-#else
-#define TIMER_RELOAD (TIMER_INTERVAL)
-#define TIMER_DIVISOR (TIMER_CTRL_DIV1)
-#define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
-#endif
-
-static void timer_set_mode(enum clock_event_mode mode,
- struct clock_event_device *clk)
-{
- unsigned long ctrl;
-
- switch (mode) {
- case CLOCK_EVT_MODE_PERIODIC:
- writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD);
-
- ctrl = TIMER_CTRL_PERIODIC;
- ctrl |=
- TIMER_DIVISOR | TIMER_CTRL_32BIT | TIMER_CTRL_IE |
- TIMER_CTRL_ENABLE;
- break;
- case CLOCK_EVT_MODE_ONESHOT:
- /* period set, and timer enabled in 'next_event' hook */
- ctrl = TIMER_CTRL_ONESHOT;
- ctrl |= TIMER_DIVISOR | TIMER_CTRL_32BIT | TIMER_CTRL_IE;
- break;
- case CLOCK_EVT_MODE_UNUSED:
- case CLOCK_EVT_MODE_SHUTDOWN:
- default:
- ctrl = 0;
- }
-
- writel(ctrl, TIMER0_VA_BASE + TIMER_CTRL);
-}
-
-static int timer_set_next_event(unsigned long evt,
- struct clock_event_device *unused)
-{
- unsigned long ctrl = readl(TIMER0_VA_BASE + TIMER_CTRL);
-
- writel(evt, TIMER0_VA_BASE + TIMER_LOAD);
- writel(ctrl | TIMER_CTRL_ENABLE, TIMER0_VA_BASE + TIMER_CTRL);
-
- return 0;
-}
-
-static struct clock_event_device timer0_clockevent = {
- .name = "timer0",
- .shift = 32,
- .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
- .set_mode = timer_set_mode,
- .set_next_event = timer_set_next_event,
-};
-
-/*
- * IRQ handler for the timer
- */
-static irqreturn_t bcmring_timer_interrupt(int irq, void *dev_id)
-{
- struct clock_event_device *evt = &timer0_clockevent;
-
- writel(1, TIMER0_VA_BASE + TIMER_INTCLR);
-
- evt->event_handler(evt);
-
- return IRQ_HANDLED;
-}
-
-static struct irqaction bcmring_timer_irq = {
- .name = "bcmring Timer Tick",
- .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
- .handler = bcmring_timer_interrupt,
-};
-
-static cycle_t bcmring_get_cycles_timer1(struct clocksource *cs)
-{
- return ~readl(TIMER1_VA_BASE + TIMER_VALUE);
-}
-
-static cycle_t bcmring_get_cycles_timer3(struct clocksource *cs)
-{
- return ~readl(TIMER3_VA_BASE + TIMER_VALUE);
-}
-
-static struct clocksource clocksource_bcmring_timer1 = {
- .name = "timer1",
- .rating = 200,
- .read = bcmring_get_cycles_timer1,
- .mask = CLOCKSOURCE_MASK(32),
- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
-static struct clocksource clocksource_bcmring_timer3 = {
- .name = "timer3",
- .rating = 100,
- .read = bcmring_get_cycles_timer3,
- .mask = CLOCKSOURCE_MASK(32),
- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-};
+#define TIMER0_VA_BASE ((void __iomem *)MM_IO_BASE_TMR)
+#define TIMER1_VA_BASE ((void __iomem *)(MM_IO_BASE_TMR + 0x20))
+#define TIMER2_VA_BASE ((void __iomem *)(MM_IO_BASE_TMR + 0x40))
+#define TIMER3_VA_BASE ((void __iomem *)(MM_IO_BASE_TMR + 0x60))
static int __init bcmring_clocksource_init(void)
{
/* setup timer1 as free-running clocksource */
- writel(0, TIMER1_VA_BASE + TIMER_CTRL);
- writel(0xffffffff, TIMER1_VA_BASE + TIMER_LOAD);
- writel(0xffffffff, TIMER1_VA_BASE + TIMER_VALUE);
- writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
- TIMER1_VA_BASE + TIMER_CTRL);
-
- clocksource_register_khz(&clocksource_bcmring_timer1,
- TIMER1_FREQUENCY_MHZ * 1000);
+ sp804_clocksource_init(TIMER1_VA_BASE, "timer1");
/* setup timer3 as free-running clocksource */
- writel(0, TIMER3_VA_BASE + TIMER_CTRL);
- writel(0xffffffff, TIMER3_VA_BASE + TIMER_LOAD);
- writel(0xffffffff, TIMER3_VA_BASE + TIMER_VALUE);
- writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
- TIMER3_VA_BASE + TIMER_CTRL);
-
- clocksource_register_khz(&clocksource_bcmring_timer3,
- TIMER3_FREQUENCY_KHZ);
+ sp804_clocksource_init(TIMER3_VA_BASE, "timer3");
return 0;
}
@@ -347,21 +233,16 @@
/*
* Make irqs happen for the system timer
*/
- setup_irq(IRQ_TIMER0, &bcmring_timer_irq);
-
bcmring_clocksource_init();
- timer0_clockevent.mult =
- div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift);
- timer0_clockevent.max_delta_ns =
- clockevent_delta2ns(0xffffffff, &timer0_clockevent);
- timer0_clockevent.min_delta_ns =
- clockevent_delta2ns(0xf, &timer0_clockevent);
-
- timer0_clockevent.cpumask = cpumask_of(0);
- clockevents_register_device(&timer0_clockevent);
+ sp804_clockevents_register(TIMER0_VA_BASE, IRQ_TIMER0, "timer0");
}
struct sys_timer bcmring_timer = {
.init = bcmring_init_timer,
};
+
+void __init bcmring_init_early(void)
+{
+ clkdev_add_table(lookups, ARRAY_SIZE(lookups));
+}
diff --git a/arch/arm/mach-bcmring/core.h b/arch/arm/mach-bcmring/core.h
index b197ba4..e0e02c4 100644
--- a/arch/arm/mach-bcmring/core.h
+++ b/arch/arm/mach-bcmring/core.h
@@ -25,6 +25,7 @@
void __init bcmring_amba_init(void);
void __init bcmring_map_io(void);
void __init bcmring_init_irq(void);
+void __init bcmring_init_early(void);
extern struct sys_timer bcmring_timer;
#endif
diff --git a/arch/arm/mach-davinci/include/mach/memory.h b/arch/arm/mach-davinci/include/mach/memory.h
index 7882272..491249e 100644
--- a/arch/arm/mach-davinci/include/mach/memory.h
+++ b/arch/arm/mach-davinci/include/mach/memory.h
@@ -41,27 +41,11 @@
*/
#define CONSISTENT_DMA_SIZE (14<<20)
-#ifndef __ASSEMBLY__
/*
* Restrict DMA-able region to workaround silicon bug. The bug
* restricts buffers available for DMA to video hardware to be
* below 128M
*/
-static inline void
-__arch_adjust_zones(unsigned long *size, unsigned long *holes)
-{
- unsigned int sz = (128<<20) >> PAGE_SHIFT;
-
- size[1] = size[0] - sz;
- size[0] = sz;
-}
-
-#define arch_adjust_zones(zone_size, holes) \
- if ((meminfo.bank[0].size >> 20) > 128) __arch_adjust_zones(zone_size, holes)
-
-#define ISA_DMA_THRESHOLD (PHYS_OFFSET + (128<<20) - 1)
-#define MAX_DMA_ADDRESS (PAGE_OFFSET + (128<<20))
-
-#endif
+#define ARM_DMA_ZONE_SIZE SZ_128M
#endif /* __ASM_ARCH_MEMORY_H */
diff --git a/arch/arm/mach-davinci/include/mach/uncompress.h b/arch/arm/mach-davinci/include/mach/uncompress.h
index 47723e8..78d8068 100644
--- a/arch/arm/mach-davinci/include/mach/uncompress.h
+++ b/arch/arm/mach-davinci/include/mach/uncompress.h
@@ -25,8 +25,7 @@
#include <mach/serial.h>
-static u32 *uart;
-static u32 *uart_info = (u32 *)(DAVINCI_UART_INFO);
+u32 *uart;
/* PORT_16C550A, in polled non-fifo mode */
static void putc(char c)
@@ -44,6 +43,8 @@
static inline void set_uart_info(u32 phys, void * __iomem virt)
{
+ u32 *uart_info = (u32 *)(DAVINCI_UART_INFO);
+
uart = (u32 *)phys;
uart_info[0] = phys;
uart_info[1] = (u32)virt;
diff --git a/arch/arm/mach-davinci/irq.c b/arch/arm/mach-davinci/irq.c
index e6269a6..bfe68ec 100644
--- a/arch/arm/mach-davinci/irq.c
+++ b/arch/arm/mach-davinci/irq.c
@@ -29,8 +29,6 @@
#include <mach/common.h>
#include <asm/mach/irq.h>
-#define IRQ_BIT(irq) ((irq) & 0x1f)
-
#define FIQ_REG0_OFFSET 0x0000
#define FIQ_REG1_OFFSET 0x0004
#define IRQ_REG0_OFFSET 0x0008
@@ -42,78 +40,33 @@
#define IRQ_INTPRI0_REG_OFFSET 0x0030
#define IRQ_INTPRI7_REG_OFFSET 0x004C
-static inline unsigned int davinci_irq_readl(int offset)
-{
- return __raw_readl(davinci_intc_base + offset);
-}
-
static inline void davinci_irq_writel(unsigned long value, int offset)
{
__raw_writel(value, davinci_intc_base + offset);
}
-/* Disable interrupt */
-static void davinci_mask_irq(struct irq_data *d)
+static __init void
+davinci_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
{
- unsigned int mask;
- u32 l;
+ struct irq_chip_generic *gc;
+ struct irq_chip_type *ct;
- mask = 1 << IRQ_BIT(d->irq);
+ gc = irq_alloc_generic_chip("AINTC", 1, irq_start, base, handle_edge_irq);
+ ct = gc->chip_types;
+ ct->chip.irq_ack = irq_gc_ack;
+ ct->chip.irq_mask = irq_gc_mask_clr_bit;
+ ct->chip.irq_unmask = irq_gc_mask_set_bit;
- if (d->irq > 31) {
- l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET);
- l &= ~mask;
- davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET);
- } else {
- l = davinci_irq_readl(IRQ_ENT_REG0_OFFSET);
- l &= ~mask;
- davinci_irq_writel(l, IRQ_ENT_REG0_OFFSET);
- }
+ ct->regs.ack = IRQ_REG0_OFFSET;
+ ct->regs.mask = IRQ_ENT_REG0_OFFSET;
+ irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
+ IRQ_NOREQUEST | IRQ_NOPROBE, 0);
}
-/* Enable interrupt */
-static void davinci_unmask_irq(struct irq_data *d)
-{
- unsigned int mask;
- u32 l;
-
- mask = 1 << IRQ_BIT(d->irq);
-
- if (d->irq > 31) {
- l = davinci_irq_readl(IRQ_ENT_REG1_OFFSET);
- l |= mask;
- davinci_irq_writel(l, IRQ_ENT_REG1_OFFSET);
- } else {
- l = davinci_irq_readl(IRQ_ENT_REG0_OFFSET);
- l |= mask;
- davinci_irq_writel(l, IRQ_ENT_REG0_OFFSET);
- }
-}
-
-/* EOI interrupt */
-static void davinci_ack_irq(struct irq_data *d)
-{
- unsigned int mask;
-
- mask = 1 << IRQ_BIT(d->irq);
-
- if (d->irq > 31)
- davinci_irq_writel(mask, IRQ_REG1_OFFSET);
- else
- davinci_irq_writel(mask, IRQ_REG0_OFFSET);
-}
-
-static struct irq_chip davinci_irq_chip_0 = {
- .name = "AINTC",
- .irq_ack = davinci_ack_irq,
- .irq_mask = davinci_mask_irq,
- .irq_unmask = davinci_unmask_irq,
-};
-
/* ARM Interrupt Controller Initialization */
void __init davinci_irq_init(void)
{
- unsigned i;
+ unsigned i, j;
const u8 *davinci_def_priorities = davinci_soc_info.intc_irq_prios;
davinci_intc_type = DAVINCI_INTC_TYPE_AINTC;
@@ -144,7 +97,6 @@
davinci_irq_writel(~0x0, IRQ_REG1_OFFSET);
for (i = IRQ_INTPRI0_REG_OFFSET; i <= IRQ_INTPRI7_REG_OFFSET; i += 4) {
- unsigned j;
u32 pri;
for (j = 0, pri = 0; j < 32; j += 4, davinci_def_priorities++)
@@ -152,13 +104,8 @@
davinci_irq_writel(pri, i);
}
- /* set up genirq dispatch for ARM INTC */
- for (i = 0; i < davinci_soc_info.intc_irq_num; i++) {
- irq_set_chip(i, &davinci_irq_chip_0);
- set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
- if (i != IRQ_TINT1_TINT34)
- irq_set_handler(i, handle_edge_irq);
- else
- irq_set_handler(i, handle_level_irq);
- }
+ for (i = 0, j = 0; i < davinci_soc_info.intc_irq_num; i += 32, j += 0x04)
+ davinci_alloc_gc(davinci_intc_base + j, i, 32);
+
+ irq_set_handler(IRQ_TINT1_TINT34, handle_level_irq);
}
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index e06a88f..5ed51b8 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -16,10 +16,8 @@
#include <linux/serial_8250.h>
#include <linux/clk.h>
#include <linux/mbus.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/mv643xx_i2c.h>
#include <linux/ata_platform.h>
-#include <linux/spi/orion_spi.h>
+#include <linux/serial_8250.h>
#include <linux/gpio.h>
#include <asm/page.h>
#include <asm/setup.h>
@@ -32,11 +30,12 @@
#include <mach/bridge-regs.h>
#include <asm/mach/arch.h>
#include <linux/irq.h>
-#include <plat/mv_xor.h>
-#include <plat/ehci-orion.h>
#include <plat/time.h>
+#include <plat/common.h>
#include "common.h"
+static int get_tclk(void);
+
/*****************************************************************************
* I/O Address Mapping
****************************************************************************/
@@ -70,463 +69,106 @@
}
/*****************************************************************************
- * EHCI
- ****************************************************************************/
-static struct orion_ehci_data dove_ehci_data = {
- .dram = &dove_mbus_dram_info,
- .phy_version = EHCI_PHY_NA,
-};
-
-static u64 ehci_dmamask = DMA_BIT_MASK(32);
-
-/*****************************************************************************
* EHCI0
****************************************************************************/
-static struct resource dove_ehci0_resources[] = {
- {
- .start = DOVE_USB0_PHYS_BASE,
- .end = DOVE_USB0_PHYS_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_DOVE_USB0,
- .end = IRQ_DOVE_USB0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device dove_ehci0 = {
- .name = "orion-ehci",
- .id = 0,
- .dev = {
- .dma_mask = &ehci_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- .platform_data = &dove_ehci_data,
- },
- .resource = dove_ehci0_resources,
- .num_resources = ARRAY_SIZE(dove_ehci0_resources),
-};
-
void __init dove_ehci0_init(void)
{
- platform_device_register(&dove_ehci0);
+ orion_ehci_init(&dove_mbus_dram_info,
+ DOVE_USB0_PHYS_BASE, IRQ_DOVE_USB0);
}
/*****************************************************************************
* EHCI1
****************************************************************************/
-static struct resource dove_ehci1_resources[] = {
- {
- .start = DOVE_USB1_PHYS_BASE,
- .end = DOVE_USB1_PHYS_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_DOVE_USB1,
- .end = IRQ_DOVE_USB1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device dove_ehci1 = {
- .name = "orion-ehci",
- .id = 1,
- .dev = {
- .dma_mask = &ehci_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- .platform_data = &dove_ehci_data,
- },
- .resource = dove_ehci1_resources,
- .num_resources = ARRAY_SIZE(dove_ehci1_resources),
-};
-
void __init dove_ehci1_init(void)
{
- platform_device_register(&dove_ehci1);
+ orion_ehci_1_init(&dove_mbus_dram_info,
+ DOVE_USB1_PHYS_BASE, IRQ_DOVE_USB1);
}
/*****************************************************************************
* GE00
****************************************************************************/
-struct mv643xx_eth_shared_platform_data dove_ge00_shared_data = {
- .t_clk = 0,
- .dram = &dove_mbus_dram_info,
-};
-
-static struct resource dove_ge00_shared_resources[] = {
- {
- .name = "ge00 base",
- .start = DOVE_GE00_PHYS_BASE + 0x2000,
- .end = DOVE_GE00_PHYS_BASE + SZ_16K - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device dove_ge00_shared = {
- .name = MV643XX_ETH_SHARED_NAME,
- .id = 0,
- .dev = {
- .platform_data = &dove_ge00_shared_data,
- },
- .num_resources = 1,
- .resource = dove_ge00_shared_resources,
-};
-
-static struct resource dove_ge00_resources[] = {
- {
- .name = "ge00 irq",
- .start = IRQ_DOVE_GE00_SUM,
- .end = IRQ_DOVE_GE00_SUM,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device dove_ge00 = {
- .name = MV643XX_ETH_NAME,
- .id = 0,
- .num_resources = 1,
- .resource = dove_ge00_resources,
- .dev = {
- .coherent_dma_mask = 0xffffffff,
- },
-};
-
void __init dove_ge00_init(struct mv643xx_eth_platform_data *eth_data)
{
- eth_data->shared = &dove_ge00_shared;
- dove_ge00.dev.platform_data = eth_data;
-
- platform_device_register(&dove_ge00_shared);
- platform_device_register(&dove_ge00);
+ orion_ge00_init(eth_data, &dove_mbus_dram_info,
+ DOVE_GE00_PHYS_BASE, IRQ_DOVE_GE00_SUM,
+ 0, get_tclk());
}
/*****************************************************************************
* SoC RTC
****************************************************************************/
-static struct resource dove_rtc_resource[] = {
- {
- .start = DOVE_RTC_PHYS_BASE,
- .end = DOVE_RTC_PHYS_BASE + 32 - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_DOVE_RTC,
- .flags = IORESOURCE_IRQ,
- }
-};
-
void __init dove_rtc_init(void)
{
- platform_device_register_simple("rtc-mv", -1, dove_rtc_resource, 2);
+ orion_rtc_init(DOVE_RTC_PHYS_BASE, IRQ_DOVE_RTC);
}
/*****************************************************************************
* SATA
****************************************************************************/
-static struct resource dove_sata_resources[] = {
- {
- .name = "sata base",
- .start = DOVE_SATA_PHYS_BASE,
- .end = DOVE_SATA_PHYS_BASE + 0x5000 - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .name = "sata irq",
- .start = IRQ_DOVE_SATA,
- .end = IRQ_DOVE_SATA,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device dove_sata = {
- .name = "sata_mv",
- .id = 0,
- .dev = {
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- .num_resources = ARRAY_SIZE(dove_sata_resources),
- .resource = dove_sata_resources,
-};
-
void __init dove_sata_init(struct mv_sata_platform_data *sata_data)
{
- sata_data->dram = &dove_mbus_dram_info;
- dove_sata.dev.platform_data = sata_data;
- platform_device_register(&dove_sata);
+ orion_sata_init(sata_data, &dove_mbus_dram_info,
+ DOVE_SATA_PHYS_BASE, IRQ_DOVE_SATA);
+
}
/*****************************************************************************
* UART0
****************************************************************************/
-static struct plat_serial8250_port dove_uart0_data[] = {
- {
- .mapbase = DOVE_UART0_PHYS_BASE,
- .membase = (char *)DOVE_UART0_VIRT_BASE,
- .irq = IRQ_DOVE_UART_0,
- .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
- .iotype = UPIO_MEM,
- .regshift = 2,
- .uartclk = 0,
- }, {
- },
-};
-
-static struct resource dove_uart0_resources[] = {
- {
- .start = DOVE_UART0_PHYS_BASE,
- .end = DOVE_UART0_PHYS_BASE + SZ_256 - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_DOVE_UART_0,
- .end = IRQ_DOVE_UART_0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device dove_uart0 = {
- .name = "serial8250",
- .id = 0,
- .dev = {
- .platform_data = dove_uart0_data,
- },
- .resource = dove_uart0_resources,
- .num_resources = ARRAY_SIZE(dove_uart0_resources),
-};
-
void __init dove_uart0_init(void)
{
- platform_device_register(&dove_uart0);
+ orion_uart0_init(DOVE_UART0_VIRT_BASE, DOVE_UART0_PHYS_BASE,
+ IRQ_DOVE_UART_0, get_tclk());
}
/*****************************************************************************
* UART1
****************************************************************************/
-static struct plat_serial8250_port dove_uart1_data[] = {
- {
- .mapbase = DOVE_UART1_PHYS_BASE,
- .membase = (char *)DOVE_UART1_VIRT_BASE,
- .irq = IRQ_DOVE_UART_1,
- .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
- .iotype = UPIO_MEM,
- .regshift = 2,
- .uartclk = 0,
- }, {
- },
-};
-
-static struct resource dove_uart1_resources[] = {
- {
- .start = DOVE_UART1_PHYS_BASE,
- .end = DOVE_UART1_PHYS_BASE + SZ_256 - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_DOVE_UART_1,
- .end = IRQ_DOVE_UART_1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device dove_uart1 = {
- .name = "serial8250",
- .id = 1,
- .dev = {
- .platform_data = dove_uart1_data,
- },
- .resource = dove_uart1_resources,
- .num_resources = ARRAY_SIZE(dove_uart1_resources),
-};
-
void __init dove_uart1_init(void)
{
- platform_device_register(&dove_uart1);
+ orion_uart1_init(DOVE_UART1_VIRT_BASE, DOVE_UART1_PHYS_BASE,
+ IRQ_DOVE_UART_1, get_tclk());
}
/*****************************************************************************
* UART2
****************************************************************************/
-static struct plat_serial8250_port dove_uart2_data[] = {
- {
- .mapbase = DOVE_UART2_PHYS_BASE,
- .membase = (char *)DOVE_UART2_VIRT_BASE,
- .irq = IRQ_DOVE_UART_2,
- .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
- .iotype = UPIO_MEM,
- .regshift = 2,
- .uartclk = 0,
- }, {
- },
-};
-
-static struct resource dove_uart2_resources[] = {
- {
- .start = DOVE_UART2_PHYS_BASE,
- .end = DOVE_UART2_PHYS_BASE + SZ_256 - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_DOVE_UART_2,
- .end = IRQ_DOVE_UART_2,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device dove_uart2 = {
- .name = "serial8250",
- .id = 2,
- .dev = {
- .platform_data = dove_uart2_data,
- },
- .resource = dove_uart2_resources,
- .num_resources = ARRAY_SIZE(dove_uart2_resources),
-};
-
void __init dove_uart2_init(void)
{
- platform_device_register(&dove_uart2);
+ orion_uart2_init(DOVE_UART2_VIRT_BASE, DOVE_UART2_PHYS_BASE,
+ IRQ_DOVE_UART_2, get_tclk());
}
/*****************************************************************************
* UART3
****************************************************************************/
-static struct plat_serial8250_port dove_uart3_data[] = {
- {
- .mapbase = DOVE_UART3_PHYS_BASE,
- .membase = (char *)DOVE_UART3_VIRT_BASE,
- .irq = IRQ_DOVE_UART_3,
- .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
- .iotype = UPIO_MEM,
- .regshift = 2,
- .uartclk = 0,
- }, {
- },
-};
-
-static struct resource dove_uart3_resources[] = {
- {
- .start = DOVE_UART3_PHYS_BASE,
- .end = DOVE_UART3_PHYS_BASE + SZ_256 - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_DOVE_UART_3,
- .end = IRQ_DOVE_UART_3,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device dove_uart3 = {
- .name = "serial8250",
- .id = 3,
- .dev = {
- .platform_data = dove_uart3_data,
- },
- .resource = dove_uart3_resources,
- .num_resources = ARRAY_SIZE(dove_uart3_resources),
-};
-
void __init dove_uart3_init(void)
{
- platform_device_register(&dove_uart3);
+ orion_uart3_init(DOVE_UART3_VIRT_BASE, DOVE_UART3_PHYS_BASE,
+ IRQ_DOVE_UART_3, get_tclk());
}
/*****************************************************************************
- * SPI0
+ * SPI
****************************************************************************/
-static struct orion_spi_info dove_spi0_data = {
- .tclk = 0,
-};
-
-static struct resource dove_spi0_resources[] = {
- {
- .start = DOVE_SPI0_PHYS_BASE,
- .end = DOVE_SPI0_PHYS_BASE + SZ_512 - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_DOVE_SPI0,
- .end = IRQ_DOVE_SPI0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device dove_spi0 = {
- .name = "orion_spi",
- .id = 0,
- .resource = dove_spi0_resources,
- .dev = {
- .platform_data = &dove_spi0_data,
- },
- .num_resources = ARRAY_SIZE(dove_spi0_resources),
-};
-
void __init dove_spi0_init(void)
{
- platform_device_register(&dove_spi0);
+ orion_spi_init(DOVE_SPI0_PHYS_BASE, get_tclk());
}
-/*****************************************************************************
- * SPI1
- ****************************************************************************/
-static struct orion_spi_info dove_spi1_data = {
- .tclk = 0,
-};
-
-static struct resource dove_spi1_resources[] = {
- {
- .start = DOVE_SPI1_PHYS_BASE,
- .end = DOVE_SPI1_PHYS_BASE + SZ_512 - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_DOVE_SPI1,
- .end = IRQ_DOVE_SPI1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device dove_spi1 = {
- .name = "orion_spi",
- .id = 1,
- .resource = dove_spi1_resources,
- .dev = {
- .platform_data = &dove_spi1_data,
- },
- .num_resources = ARRAY_SIZE(dove_spi1_resources),
-};
-
void __init dove_spi1_init(void)
{
- platform_device_register(&dove_spi1);
+ orion_spi_init(DOVE_SPI1_PHYS_BASE, get_tclk());
}
/*****************************************************************************
* I2C
****************************************************************************/
-static struct mv64xxx_i2c_pdata dove_i2c_data = {
- .freq_m = 10, /* assumes 166 MHz TCLK gets 94.3kHz */
- .freq_n = 3,
- .timeout = 1000, /* Default timeout of 1 second */
-};
-
-static struct resource dove_i2c_resources[] = {
- {
- .name = "i2c base",
- .start = DOVE_I2C_PHYS_BASE,
- .end = DOVE_I2C_PHYS_BASE + 0x20 - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .name = "i2c irq",
- .start = IRQ_DOVE_I2C,
- .end = IRQ_DOVE_I2C,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device dove_i2c = {
- .name = MV64XXX_I2C_CTLR_NAME,
- .id = 0,
- .num_resources = ARRAY_SIZE(dove_i2c_resources),
- .resource = dove_i2c_resources,
- .dev = {
- .platform_data = &dove_i2c_data,
- },
-};
-
void __init dove_i2c_init(void)
{
- platform_device_register(&dove_i2c);
+ orion_i2c_init(DOVE_I2C_PHYS_BASE, IRQ_DOVE_I2C, 10);
}
/*****************************************************************************
@@ -554,208 +196,22 @@
};
/*****************************************************************************
- * XOR
- ****************************************************************************/
-static struct mv_xor_platform_shared_data dove_xor_shared_data = {
- .dram = &dove_mbus_dram_info,
-};
-
-/*****************************************************************************
* XOR 0
****************************************************************************/
-static u64 dove_xor0_dmamask = DMA_BIT_MASK(32);
-
-static struct resource dove_xor0_shared_resources[] = {
- {
- .name = "xor 0 low",
- .start = DOVE_XOR0_PHYS_BASE,
- .end = DOVE_XOR0_PHYS_BASE + 0xff,
- .flags = IORESOURCE_MEM,
- }, {
- .name = "xor 0 high",
- .start = DOVE_XOR0_HIGH_PHYS_BASE,
- .end = DOVE_XOR0_HIGH_PHYS_BASE + 0xff,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device dove_xor0_shared = {
- .name = MV_XOR_SHARED_NAME,
- .id = 0,
- .dev = {
- .platform_data = &dove_xor_shared_data,
- },
- .num_resources = ARRAY_SIZE(dove_xor0_shared_resources),
- .resource = dove_xor0_shared_resources,
-};
-
-static struct resource dove_xor00_resources[] = {
- [0] = {
- .start = IRQ_DOVE_XOR_00,
- .end = IRQ_DOVE_XOR_00,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct mv_xor_platform_data dove_xor00_data = {
- .shared = &dove_xor0_shared,
- .hw_id = 0,
- .pool_size = PAGE_SIZE,
-};
-
-static struct platform_device dove_xor00_channel = {
- .name = MV_XOR_NAME,
- .id = 0,
- .num_resources = ARRAY_SIZE(dove_xor00_resources),
- .resource = dove_xor00_resources,
- .dev = {
- .dma_mask = &dove_xor0_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(64),
- .platform_data = &dove_xor00_data,
- },
-};
-
-static struct resource dove_xor01_resources[] = {
- [0] = {
- .start = IRQ_DOVE_XOR_01,
- .end = IRQ_DOVE_XOR_01,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct mv_xor_platform_data dove_xor01_data = {
- .shared = &dove_xor0_shared,
- .hw_id = 1,
- .pool_size = PAGE_SIZE,
-};
-
-static struct platform_device dove_xor01_channel = {
- .name = MV_XOR_NAME,
- .id = 1,
- .num_resources = ARRAY_SIZE(dove_xor01_resources),
- .resource = dove_xor01_resources,
- .dev = {
- .dma_mask = &dove_xor0_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(64),
- .platform_data = &dove_xor01_data,
- },
-};
-
void __init dove_xor0_init(void)
{
- platform_device_register(&dove_xor0_shared);
-
- /*
- * two engines can't do memset simultaneously, this limitation
- * satisfied by removing memset support from one of the engines.
- */
- dma_cap_set(DMA_MEMCPY, dove_xor00_data.cap_mask);
- dma_cap_set(DMA_XOR, dove_xor00_data.cap_mask);
- platform_device_register(&dove_xor00_channel);
-
- dma_cap_set(DMA_MEMCPY, dove_xor01_data.cap_mask);
- dma_cap_set(DMA_MEMSET, dove_xor01_data.cap_mask);
- dma_cap_set(DMA_XOR, dove_xor01_data.cap_mask);
- platform_device_register(&dove_xor01_channel);
+ orion_xor0_init(&dove_mbus_dram_info,
+ DOVE_XOR0_PHYS_BASE, DOVE_XOR0_HIGH_PHYS_BASE,
+ IRQ_DOVE_XOR_00, IRQ_DOVE_XOR_01);
}
/*****************************************************************************
* XOR 1
****************************************************************************/
-static u64 dove_xor1_dmamask = DMA_BIT_MASK(32);
-
-static struct resource dove_xor1_shared_resources[] = {
- {
- .name = "xor 0 low",
- .start = DOVE_XOR1_PHYS_BASE,
- .end = DOVE_XOR1_PHYS_BASE + 0xff,
- .flags = IORESOURCE_MEM,
- }, {
- .name = "xor 0 high",
- .start = DOVE_XOR1_HIGH_PHYS_BASE,
- .end = DOVE_XOR1_HIGH_PHYS_BASE + 0xff,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device dove_xor1_shared = {
- .name = MV_XOR_SHARED_NAME,
- .id = 1,
- .dev = {
- .platform_data = &dove_xor_shared_data,
- },
- .num_resources = ARRAY_SIZE(dove_xor1_shared_resources),
- .resource = dove_xor1_shared_resources,
-};
-
-static struct resource dove_xor10_resources[] = {
- [0] = {
- .start = IRQ_DOVE_XOR_10,
- .end = IRQ_DOVE_XOR_10,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct mv_xor_platform_data dove_xor10_data = {
- .shared = &dove_xor1_shared,
- .hw_id = 0,
- .pool_size = PAGE_SIZE,
-};
-
-static struct platform_device dove_xor10_channel = {
- .name = MV_XOR_NAME,
- .id = 2,
- .num_resources = ARRAY_SIZE(dove_xor10_resources),
- .resource = dove_xor10_resources,
- .dev = {
- .dma_mask = &dove_xor1_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(64),
- .platform_data = &dove_xor10_data,
- },
-};
-
-static struct resource dove_xor11_resources[] = {
- [0] = {
- .start = IRQ_DOVE_XOR_11,
- .end = IRQ_DOVE_XOR_11,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct mv_xor_platform_data dove_xor11_data = {
- .shared = &dove_xor1_shared,
- .hw_id = 1,
- .pool_size = PAGE_SIZE,
-};
-
-static struct platform_device dove_xor11_channel = {
- .name = MV_XOR_NAME,
- .id = 3,
- .num_resources = ARRAY_SIZE(dove_xor11_resources),
- .resource = dove_xor11_resources,
- .dev = {
- .dma_mask = &dove_xor1_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(64),
- .platform_data = &dove_xor11_data,
- },
-};
-
void __init dove_xor1_init(void)
{
- platform_device_register(&dove_xor1_shared);
-
- /*
- * two engines can't do memset simultaneously, this limitation
- * satisfied by removing memset support from one of the engines.
- */
- dma_cap_set(DMA_MEMCPY, dove_xor10_data.cap_mask);
- dma_cap_set(DMA_XOR, dove_xor10_data.cap_mask);
- platform_device_register(&dove_xor10_channel);
-
- dma_cap_set(DMA_MEMCPY, dove_xor11_data.cap_mask);
- dma_cap_set(DMA_MEMSET, dove_xor11_data.cap_mask);
- dma_cap_set(DMA_XOR, dove_xor11_data.cap_mask);
- platform_device_register(&dove_xor11_channel);
+ orion_xor1_init(DOVE_XOR1_PHYS_BASE, DOVE_XOR1_HIGH_PHYS_BASE,
+ IRQ_DOVE_XOR_10, IRQ_DOVE_XOR_11);
}
/*****************************************************************************
@@ -833,14 +289,6 @@
#endif
dove_setup_cpu_mbus();
- dove_ge00_shared_data.t_clk = tclk;
- dove_uart0_data[0].uartclk = tclk;
- dove_uart1_data[0].uartclk = tclk;
- dove_uart2_data[0].uartclk = tclk;
- dove_uart3_data[0].uartclk = tclk;
- dove_spi0_data.tclk = tclk;
- dove_spi1_data.tclk = tclk;
-
/* internal devices that every board has */
dove_rtc_init();
dove_xor0_init();
diff --git a/arch/arm/mach-dove/mpp.c b/arch/arm/mach-dove/mpp.c
index c66c763..51e0e41 100644
--- a/arch/arm/mach-dove/mpp.c
+++ b/arch/arm/mach-dove/mpp.c
@@ -11,24 +11,17 @@
#include <linux/kernel.h>
#include <linux/gpio.h>
#include <linux/io.h>
-
+#include <plat/mpp.h>
#include <mach/dove.h>
-
#include "mpp.h"
-#define MPP_NR_REGS 4
-#define MPP_CTRL(i) ((i) == 3 ? \
- DOVE_MPP_CTRL4_VIRT_BASE : \
- DOVE_MPP_VIRT_BASE + (i) * 4)
-#define PMU_SIG_REGS 2
-#define PMU_SIG_CTRL(i) (DOVE_PMU_SIG_CTRL + (i) * 4)
-
struct dove_mpp_grp {
int start;
int end;
};
-static struct dove_mpp_grp dove_mpp_grp[] = {
+/* Map a group to a range of GPIO pins in that group */
+static const struct dove_mpp_grp dove_mpp_grp[] = {
[MPP_24_39] = {
.start = 24,
.end = 39,
@@ -38,8 +31,8 @@
.end = 45,
},
[MPP_46_51] = {
- .start = 40,
- .end = 45,
+ .start = 46,
+ .end = 51,
},
[MPP_58_61] = {
.start = 58,
@@ -51,6 +44,8 @@
},
};
+/* Enable gpio for a range of pins. mode should be a combination of
+ GPIO_OUTPUT_OK | GPIO_INPUT_OK */
static void dove_mpp_gpio_mode(int start, int end, int gpio_mode)
{
int i;
@@ -59,24 +54,17 @@
orion_gpio_set_valid(i, gpio_mode);
}
+/* Dump all the extra MPP registers. The platform code will dump the
+ registers for pins 0-23. */
static void dove_mpp_dump_regs(void)
{
-#ifdef DEBUG
- int i;
+ pr_debug("PMU_CTRL4_CTRL: %08x\n",
+ readl(DOVE_MPP_CTRL4_VIRT_BASE));
- pr_debug("MPP_CTRL regs:");
- for (i = 0; i < MPP_NR_REGS; i++)
- printk(" %08x", readl(MPP_CTRL(i)));
- printk("\n");
+ pr_debug("PMU_MPP_GENERAL_CTRL: %08x\n",
+ readl(DOVE_PMU_MPP_GENERAL_CTRL));
- pr_debug("PMU_SIG_CTRL regs:");
- for (i = 0; i < PMU_SIG_REGS; i++)
- printk(" %08x", readl(PMU_SIG_CTRL(i)));
- printk("\n");
-
- pr_debug("PMU_MPP_GENERAL_CTRL: %08x\n", readl(DOVE_PMU_MPP_GENERAL_CTRL));
pr_debug("MPP_GENERAL: %08x\n", readl(DOVE_MPP_GENERAL_VIRT_BASE));
-#endif
}
static void dove_mpp_cfg_nfc(int sel)
@@ -92,7 +80,7 @@
static void dove_mpp_cfg_au1(int sel)
{
- u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
+ u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
u32 ssp_ctrl1 = readl(DOVE_SSP_CTRL_STATUS_1);
u32 mpp_gen_ctrl = readl(DOVE_MPP_GENERAL_VIRT_BASE);
u32 global_cfg_2 = readl(DOVE_GLOBAL_CONFIG_2);
@@ -128,82 +116,46 @@
writel(global_cfg_2, DOVE_GLOBAL_CONFIG_2);
}
-static void dove_mpp_conf_grp(int num, int sel, u32 *mpp_ctrl)
+/* Configure the group registers, enabling GPIO if sel indicates the
+ pin is to be used for GPIO */
+static void dove_mpp_conf_grp(unsigned int *mpp_grp_list)
{
- int start = dove_mpp_grp[num].start;
- int end = dove_mpp_grp[num].end;
- int gpio_mode = sel ? GPIO_OUTPUT_OK | GPIO_INPUT_OK : 0;
+ u32 mpp_ctrl4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
+ int gpio_mode;
- *mpp_ctrl &= ~(0x1 << num);
- *mpp_ctrl |= sel << num;
+ for ( ; *mpp_grp_list; mpp_grp_list++) {
+ unsigned int num = MPP_NUM(*mpp_grp_list);
+ unsigned int sel = MPP_SEL(*mpp_grp_list);
- dove_mpp_gpio_mode(start, end, gpio_mode);
+ if (num > MPP_GRP_MAX) {
+ pr_err("dove: invalid MPP GRP number (%u)\n", num);
+ continue;
+ }
+
+ mpp_ctrl4 &= ~(0x1 << num);
+ mpp_ctrl4 |= sel << num;
+
+ gpio_mode = sel ? GPIO_OUTPUT_OK | GPIO_INPUT_OK : 0;
+ dove_mpp_gpio_mode(dove_mpp_grp[num].start,
+ dove_mpp_grp[num].end, gpio_mode);
+ }
+ writel(mpp_ctrl4, DOVE_MPP_CTRL4_VIRT_BASE);
}
-void __init dove_mpp_conf(unsigned int *mpp_list)
+/* Configure the various MPP pins on Dove */
+void __init dove_mpp_conf(unsigned int *mpp_list,
+ unsigned int *mpp_grp_list,
+ unsigned int grp_au1_52_57,
+ unsigned int grp_nfc_64_71)
{
- u32 mpp_ctrl[MPP_NR_REGS];
- u32 pmu_mpp_ctrl = 0;
- u32 pmu_sig_ctrl[PMU_SIG_REGS];
- int i;
-
- for (i = 0; i < MPP_NR_REGS; i++)
- mpp_ctrl[i] = readl(MPP_CTRL(i));
-
- for (i = 0; i < PMU_SIG_REGS; i++)
- pmu_sig_ctrl[i] = readl(PMU_SIG_CTRL(i));
-
- pmu_mpp_ctrl = readl(DOVE_PMU_MPP_GENERAL_CTRL);
-
dove_mpp_dump_regs();
- for ( ; *mpp_list != MPP_END; mpp_list++) {
- unsigned int num = MPP_NUM(*mpp_list);
- unsigned int sel = MPP_SEL(*mpp_list);
- int shift, gpio_mode;
+ /* Use platform code for pins 0-23 */
+ orion_mpp_conf(mpp_list, 0, MPP_MAX, DOVE_MPP_VIRT_BASE);
- if (num > MPP_MAX) {
- pr_err("dove: invalid MPP number (%u)\n", num);
- continue;
- }
-
- if (*mpp_list & MPP_NFC_MASK) {
- dove_mpp_cfg_nfc(sel);
- continue;
- }
-
- if (*mpp_list & MPP_AU1_MASK) {
- dove_mpp_cfg_au1(sel);
- continue;
- }
-
- if (*mpp_list & MPP_GRP_MASK) {
- dove_mpp_conf_grp(num, sel, &mpp_ctrl[3]);
- continue;
- }
-
- shift = (num & 7) << 2;
- if (*mpp_list & MPP_PMU_MASK) {
- pmu_mpp_ctrl |= (0x1 << num);
- pmu_sig_ctrl[num / 8] &= ~(0xf << shift);
- pmu_sig_ctrl[num / 8] |= 0xf << shift;
- gpio_mode = 0;
- } else {
- mpp_ctrl[num / 8] &= ~(0xf << shift);
- mpp_ctrl[num / 8] |= sel << shift;
- gpio_mode = GPIO_OUTPUT_OK | GPIO_INPUT_OK;
- }
-
- orion_gpio_set_valid(num, gpio_mode);
- }
-
- for (i = 0; i < MPP_NR_REGS; i++)
- writel(mpp_ctrl[i], MPP_CTRL(i));
-
- for (i = 0; i < PMU_SIG_REGS; i++)
- writel(pmu_sig_ctrl[i], PMU_SIG_CTRL(i));
-
- writel(pmu_mpp_ctrl, DOVE_PMU_MPP_GENERAL_CTRL);
+ dove_mpp_conf_grp(mpp_grp_list);
+ dove_mpp_cfg_au1(grp_au1_52_57);
+ dove_mpp_cfg_nfc(grp_nfc_64_71);
dove_mpp_dump_regs();
}
diff --git a/arch/arm/mach-dove/mpp.h b/arch/arm/mach-dove/mpp.h
index 2a43ce4..fbec7c5 100644
--- a/arch/arm/mach-dove/mpp.h
+++ b/arch/arm/mach-dove/mpp.h
@@ -1,178 +1,150 @@
#ifndef __ARCH_DOVE_MPP_CODED_H
#define __ARCH_DOVE_MPP_CODED_H
-#define MPP(_num, _mode, _pmu, _grp, _au1, _nfc) ( \
-/* MPP/group number */ ((_num) & 0xff) | \
-/* MPP select value */ (((_mode) & 0xf) << 8) | \
-/* MPP PMU */ ((!!(_pmu)) << 12) | \
-/* group flag */ ((!!(_grp)) << 13) | \
-/* AU1 flag */ ((!!(_au1)) << 14) | \
-/* NFCE flag */ ((!!(_nfc)) << 15))
+#define MPP(_num, _sel, _in, _out) ( \
+ /* MPP number */ ((_num) & 0xff) | \
+ /* MPP select value */ (((_sel) & 0xf) << 8) | \
+ /* may be input signal */ ((!!(_in)) << 12) | \
+ /* may be output signal */ ((!!(_out)) << 13))
-#define MPP_MAX 71
+#define MPP0_GPIO0 MPP(0, 0x0, 1, 1)
+#define MPP0_UA2_RTSn MPP(0, 0x2, 0, 0)
+#define MPP0_SDIO0_CD MPP(0, 0x3, 0, 0)
+#define MPP0_LCD0_PWM MPP(0, 0xf, 0, 0)
-#define MPP_NUM(x) ((x) & 0xff)
-#define MPP_SEL(x) (((x) >> 8) & 0xf)
+#define MPP1_GPIO1 MPP(1, 0x0, 1, 1)
+#define MPP1_UA2_CTSn MPP(1, 0x2, 0, 0)
+#define MPP1_SDIO0_WP MPP(1, 0x3, 0, 0)
+#define MPP1_LCD1_PWM MPP(1, 0xf, 0, 0)
-#define MPP_PMU_MASK MPP(0, 0x0, 1, 0, 0, 0)
-#define MPP_GRP_MASK MPP(0, 0x0, 0, 1, 0, 0)
-#define MPP_AU1_MASK MPP(0, 0x0, 0, 0, 1, 0)
-#define MPP_NFC_MASK MPP(0, 0x0, 0, 0, 0, 1)
+#define MPP2_GPIO2 MPP(2, 0x0, 1, 1)
+#define MPP2_SATA_PRESENT MPP(2, 0x1, 0, 0)
+#define MPP2_UA2_TXD MPP(2, 0x2, 0, 0)
+#define MPP2_SDIO0_BUS_POWER MPP(2, 0x3, 0, 0)
+#define MPP2_UA_RTSn1 MPP(2, 0x4, 0, 0)
-#define MPP_END MPP(0xff, 0xf, 1, 1, 1, 1)
+#define MPP3_GPIO3 MPP(3, 0x0, 1, 1)
+#define MPP3_SATA_ACT MPP(3, 0x1, 0, 0)
+#define MPP3_UA2_RXD MPP(3, 0x2, 0, 0)
+#define MPP3_SDIO0_LED_CTRL MPP(3, 0x3, 0, 0)
+#define MPP3_UA_CTSn1 MPP(3, 0x4, 0, 0)
+#define MPP3_SPI_LCD_CS1 MPP(3, 0xf, 0, 0)
-#define MPP_PMU_DRIVE_0 0x1
-#define MPP_PMU_DRIVE_1 0x2
-#define MPP_PMU_SDI 0x3
-#define MPP_PMU_CPU_PWRDWN 0x4
-#define MPP_PMU_STBY_PWRDWN 0x5
-#define MPP_PMU_CORE_PWR_GOOD 0x8
-#define MPP_PMU_BAT_FAULT 0xa
-#define MPP_PMU_EXT0_WU 0xb
-#define MPP_PMU_EXT1_WU 0xc
-#define MPP_PMU_EXT2_WU 0xd
-#define MPP_PMU_BLINK 0xe
-#define MPP_PMU(_num, _mode) MPP((_num), MPP_PMU_##_mode, 1, 0, 0, 0)
+#define MPP4_GPIO4 MPP(4, 0x0, 1, 1)
+#define MPP4_UA3_RTSn MPP(4, 0x2, 0, 0)
+#define MPP4_SDIO1_CD MPP(4, 0x3, 0, 0)
+#define MPP4_SPI_1_MISO MPP(4, 0x4, 0, 0)
-#define MPP_PIN(_num, _mode) MPP((_num), (_mode), 0, 0, 0, 0)
-#define MPP_GRP(_grp, _mode) MPP((_grp), (_mode), 0, 1, 0, 0)
-#define MPP_GRP_AU1(_mode) MPP(0, (_mode), 0, 0, 1, 0)
-#define MPP_GRP_NFC(_mode) MPP(0, (_mode), 0, 0, 0, 1)
+#define MPP5_GPIO5 MPP(5, 0x0, 1, 1)
+#define MPP5_UA3_CTSn MPP(5, 0x2, 0, 0)
+#define MPP5_SDIO1_WP MPP(5, 0x3, 0, 0)
+#define MPP5_SPI_1_CS MPP(5, 0x4, 0, 0)
-#define MPP0_GPIO0 MPP_PIN(0, 0x0)
-#define MPP0_UA2_RTSn MPP_PIN(0, 0x2)
-#define MPP0_SDIO0_CD MPP_PIN(0, 0x3)
-#define MPP0_LCD0_PWM MPP_PIN(0, 0xf)
+#define MPP6_GPIO6 MPP(6, 0x0, 1, 1)
+#define MPP6_UA3_TXD MPP(6, 0x2, 0, 0)
+#define MPP6_SDIO1_BUS_POWER MPP(6, 0x3, 0, 0)
+#define MPP6_SPI_1_MOSI MPP(6, 0x4, 0, 0)
-#define MPP1_GPIO1 MPP_PIN(1, 0x0)
-#define MPP1_UA2_CTSn MPP_PIN(1, 0x2)
-#define MPP1_SDIO0_WP MPP_PIN(1, 0x3)
-#define MPP1_LCD1_PWM MPP_PIN(1, 0xf)
+#define MPP7_GPIO7 MPP(7, 0x0, 1, 1)
+#define MPP7_UA3_RXD MPP(7, 0x2, 0, 0)
+#define MPP7_SDIO1_LED_CTRL MPP(7, 0x3, 0, 0)
+#define MPP7_SPI_1_SCK MPP(7, 0x4, 0, 0)
-#define MPP2_GPIO2 MPP_PIN(2, 0x0)
-#define MPP2_SATA_PRESENT MPP_PIN(2, 0x1)
-#define MPP2_UA2_TXD MPP_PIN(2, 0x2)
-#define MPP2_SDIO0_BUS_POWER MPP_PIN(2, 0x3)
-#define MPP2_UA_RTSn1 MPP_PIN(2, 0x4)
+#define MPP8_GPIO8 MPP(8, 0x0, 1, 1)
+#define MPP8_WD_RST_OUT MPP(8, 0x1, 0, 0)
-#define MPP3_GPIO3 MPP_PIN(3, 0x0)
-#define MPP3_SATA_ACT MPP_PIN(3, 0x1)
-#define MPP3_UA2_RXD MPP_PIN(3, 0x2)
-#define MPP3_SDIO0_LED_CTRL MPP_PIN(3, 0x3)
-#define MPP3_UA_CTSn1 MPP_PIN(3, 0x4)
-#define MPP3_SPI_LCD_CS1 MPP_PIN(3, 0xf)
+#define MPP9_GPIO9 MPP(9, 0x0, 1, 1)
+#define MPP9_PEX1_CLKREQn MPP(9, 0x5, 0, 0)
-#define MPP4_GPIO4 MPP_PIN(4, 0x0)
-#define MPP4_UA3_RTSn MPP_PIN(4, 0x2)
-#define MPP4_SDIO1_CD MPP_PIN(4, 0x3)
-#define MPP4_SPI_1_MISO MPP_PIN(4, 0x4)
+#define MPP10_GPIO10 MPP(10, 0x0, 1, 1)
+#define MPP10_SSP_SCLK MPP(10, 0x5, 0, 0)
-#define MPP5_GPIO5 MPP_PIN(5, 0x0)
-#define MPP5_UA3_CTSn MPP_PIN(5, 0x2)
-#define MPP5_SDIO1_WP MPP_PIN(5, 0x3)
-#define MPP5_SPI_1_CS MPP_PIN(5, 0x4)
+#define MPP11_GPIO11 MPP(11, 0x0, 1, 1)
+#define MPP11_SATA_PRESENT MPP(11, 0x1, 0, 0)
+#define MPP11_SATA_ACT MPP(11, 0x2, 0, 0)
+#define MPP11_SDIO0_LED_CTRL MPP(11, 0x3, 0, 0)
+#define MPP11_SDIO1_LED_CTRL MPP(11, 0x4, 0, 0)
+#define MPP11_PEX0_CLKREQn MPP(11, 0x5, 0, 0)
-#define MPP6_GPIO6 MPP_PIN(6, 0x0)
-#define MPP6_UA3_TXD MPP_PIN(6, 0x2)
-#define MPP6_SDIO1_BUS_POWER MPP_PIN(6, 0x3)
-#define MPP6_SPI_1_MOSI MPP_PIN(6, 0x4)
+#define MPP12_GPIO12 MPP(12, 0x0, 1, 1)
+#define MPP12_SATA_ACT MPP(12, 0x1, 0, 0)
+#define MPP12_UA2_RTSn MPP(12, 0x2, 0, 0)
+#define MPP12_AD0_I2S_EXT_MCLK MPP(12, 0x3, 0, 0)
+#define MPP12_SDIO1_CD MPP(12, 0x4, 0, 0)
-#define MPP7_GPIO7 MPP_PIN(7, 0x0)
-#define MPP7_UA3_RXD MPP_PIN(7, 0x2)
-#define MPP7_SDIO1_LED_CTRL MPP_PIN(7, 0x3)
-#define MPP7_SPI_1_SCK MPP_PIN(7, 0x4)
+#define MPP13_GPIO13 MPP(13, 0x0, 1, 1)
+#define MPP13_UA2_CTSn MPP(13, 0x2, 0, 0)
+#define MPP13_AD1_I2S_EXT_MCLK MPP(13, 0x3, 0, 0)
+#define MPP13_SDIO1WP MPP(13, 0x4, 0, 0)
+#define MPP13_SSP_EXTCLK MPP(13, 0x5, 0, 0)
-#define MPP8_GPIO8 MPP_PIN(8, 0x0)
-#define MPP8_WD_RST_OUT MPP_PIN(8, 0x1)
+#define MPP14_GPIO14 MPP(14, 0x0, 1, 1)
+#define MPP14_UA2_TXD MPP(14, 0x2, 0, 0)
+#define MPP14_SDIO1_BUS_POWER MPP(14, 0x4, 0, 0)
+#define MPP14_SSP_RXD MPP(14, 0x5, 0, 0)
-#define MPP9_GPIO9 MPP_PIN(9, 0x0)
-#define MPP9_PEX1_CLKREQn MPP_PIN(9, 0x5)
+#define MPP15_GPIO15 MPP(15, 0x0, 1, 1)
+#define MPP15_UA2_RXD MPP(15, 0x2, 0, 0)
+#define MPP15_SDIO1_LED_CTRL MPP(15, 0x4, 0, 0)
+#define MPP15_SSP_SFRM MPP(15, 0x5, 0, 0)
-#define MPP10_GPIO10 MPP_PIN(10, 0x0)
-#define MPP10_SSP_SCLK MPP_PIN(10, 0x5)
+#define MPP16_GPIO16 MPP(16, 0x0, 1, 1)
+#define MPP16_UA3_RTSn MPP(16, 0x2, 0, 0)
+#define MPP16_SDIO0_CD MPP(16, 0x3, 0, 0)
+#define MPP16_SPI_LCD_CS1 MPP(16, 0x4, 0, 0)
+#define MPP16_AC97_SDATA_IN1 MPP(16, 0x5, 0, 0)
-#define MPP11_GPIO11 MPP_PIN(11, 0x0)
-#define MPP11_SATA_PRESENT MPP_PIN(11, 0x1)
-#define MPP11_SATA_ACT MPP_PIN(11, 0x2)
-#define MPP11_SDIO0_LED_CTRL MPP_PIN(11, 0x3)
-#define MPP11_SDIO1_LED_CTRL MPP_PIN(11, 0x4)
-#define MPP11_PEX0_CLKREQn MPP_PIN(11, 0x5)
+#define MPP17_GPIO17 MPP(17, 0x0, 1, 1)
+#define MPP17_AC97_SYSCLK_OUT MPP(17, 0x1, 0, 0)
+#define MPP17_UA3_CTSn MPP(17, 0x2, 0, 0)
+#define MPP17_SDIO0_WP MPP(17, 0x3, 0, 0)
+#define MPP17_TW_SDA2 MPP(17, 0x4, 0, 0)
+#define MPP17_AC97_SDATA_IN2 MPP(17, 0x5, 0, 0)
-#define MPP12_GPIO12 MPP_PIN(12, 0x0)
-#define MPP12_SATA_ACT MPP_PIN(12, 0x1)
-#define MPP12_UA2_RTSn MPP_PIN(12, 0x2)
-#define MPP12_AD0_I2S_EXT_MCLK MPP_PIN(12, 0x3)
-#define MPP12_SDIO1_CD MPP_PIN(12, 0x4)
+#define MPP18_GPIO18 MPP(18, 0x0, 1, 1)
+#define MPP18_UA3_TXD MPP(18, 0x2, 0, 0)
+#define MPP18_SDIO0_BUS_POWER MPP(18, 0x3, 0, 0)
+#define MPP18_LCD0_PWM MPP(18, 0x4, 0, 0)
+#define MPP18_AC_SDATA_IN3 MPP(18, 0x5, 0, 0)
-#define MPP13_GPIO13 MPP_PIN(13, 0x0)
-#define MPP13_UA2_CTSn MPP_PIN(13, 0x2)
-#define MPP13_AD1_I2S_EXT_MCLK MPP_PIN(13, 0x3)
-#define MPP13_SDIO1WP MPP_PIN(13, 0x4)
-#define MPP13_SSP_EXTCLK MPP_PIN(13, 0x5)
+#define MPP19_GPIO19 MPP(19, 0x0, 1, 1)
+#define MPP19_UA3_RXD MPP(19, 0x2, 0, 0)
+#define MPP19_SDIO0_LED_CTRL MPP(19, 0x3, 0, 0)
+#define MPP19_TW_SCK2 MPP(19, 0x4, 0, 0)
-#define MPP14_GPIO14 MPP_PIN(14, 0x0)
-#define MPP14_UA2_TXD MPP_PIN(14, 0x2)
-#define MPP14_SDIO1_BUS_POWER MPP_PIN(14, 0x4)
-#define MPP14_SSP_RXD MPP_PIN(14, 0x5)
+#define MPP20_GPIO20 MPP(20, 0x0, 1, 1)
+#define MPP20_AC97_SYSCLK_OUT MPP(20, 0x1, 0, 0)
+#define MPP20_SPI_LCD_MISO MPP(20, 0x2, 0, 0)
+#define MPP20_SDIO1_CD MPP(20, 0x3, 0, 0)
+#define MPP20_SDIO0_CD MPP(20, 0x5, 0, 0)
+#define MPP20_SPI_1_MISO MPP(20, 0x6, 0, 0)
-#define MPP15_GPIO15 MPP_PIN(15, 0x0)
-#define MPP15_UA2_RXD MPP_PIN(15, 0x2)
-#define MPP15_SDIO1_LED_CTRL MPP_PIN(15, 0x4)
-#define MPP15_SSP_SFRM MPP_PIN(15, 0x5)
+#define MPP21_GPIO21 MPP(21, 0x0, 1, 1)
+#define MPP21_UA1_RTSn MPP(21, 0x1, 0, 0)
+#define MPP21_SPI_LCD_CS0 MPP(21, 0x2, 0, 0)
+#define MPP21_SDIO1_WP MPP(21, 0x3, 0, 0)
+#define MPP21_SSP_SFRM MPP(21, 0x4, 0, 0)
+#define MPP21_SDIO0_WP MPP(21, 0x5, 0, 0)
+#define MPP21_SPI_1_CS MPP(21, 0x6, 0, 0)
-#define MPP16_GPIO16 MPP_PIN(16, 0x0)
-#define MPP16_UA3_RTSn MPP_PIN(16, 0x2)
-#define MPP16_SDIO0_CD MPP_PIN(16, 0x3)
-#define MPP16_SPI_LCD_CS1 MPP_PIN(16, 0x4)
-#define MPP16_AC97_SDATA_IN1 MPP_PIN(16, 0x5)
+#define MPP22_GPIO22 MPP(22, 0x0, 1, 1)
+#define MPP22_UA1_CTSn MPP(22, 0x1, 0, 0)
+#define MPP22_SPI_LCD_MOSI MPP(22, 0x2, 0, 0)
+#define MPP22_SDIO1_BUS_POWER MPP(22, 0x3, 0, 0)
+#define MPP22_SSP_TXD MPP(22, 0x4, 0, 0)
+#define MPP22_SDIO0_BUS_POWER MPP(22, 0x5, 0, 0)
+#define MPP22_SPI_1_MOSI MPP(22, 0x6, 0, 0)
-#define MPP17_GPIO17 MPP_PIN(17, 0x0)
-#define MPP17_AC97_SYSCLK_OUT MPP_PIN(17, 0x1)
-#define MPP17_UA3_CTSn MPP_PIN(17, 0x2)
-#define MPP17_SDIO0_WP MPP_PIN(17, 0x3)
-#define MPP17_TW_SDA2 MPP_PIN(17, 0x4)
-#define MPP17_AC97_SDATA_IN2 MPP_PIN(17, 0x5)
+#define MPP23_GPIO23 MPP(23, 0x0, 1, 1)
+#define MPP23_SPI_LCD_SCK MPP(23, 0x2, 0, 0)
+#define MPP23_SDIO1_LED_CTRL MPP(23, 0x3, 0, 0)
+#define MPP23_SSP_SCLK MPP(23, 0x4, 0, 0)
+#define MPP23_SDIO0_LED_CTRL MPP(23, 0x5, 0, 0)
+#define MPP23_SPI_1_SCK MPP(23, 0x6, 0, 0)
-#define MPP18_GPIO18 MPP_PIN(18, 0x0)
-#define MPP18_UA3_TXD MPP_PIN(18, 0x2)
-#define MPP18_SDIO0_BUS_POWER MPP_PIN(18, 0x3)
-#define MPP18_LCD0_PWM MPP_PIN(18, 0x4)
-#define MPP18_AC_SDATA_IN3 MPP_PIN(18, 0x5)
+#define MPP_MAX 23
-#define MPP19_GPIO19 MPP_PIN(19, 0x0)
-#define MPP19_UA3_RXD MPP_PIN(19, 0x2)
-#define MPP19_SDIO0_LED_CTRL MPP_PIN(19, 0x3)
-#define MPP19_TW_SCK2 MPP_PIN(19, 0x4)
-
-#define MPP20_GPIO20 MPP_PIN(20, 0x0)
-#define MPP20_AC97_SYSCLK_OUT MPP_PIN(20, 0x1)
-#define MPP20_SPI_LCD_MISO MPP_PIN(20, 0x2)
-#define MPP20_SDIO1_CD MPP_PIN(20, 0x3)
-#define MPP20_SDIO0_CD MPP_PIN(20, 0x5)
-#define MPP20_SPI_1_MISO MPP_PIN(20, 0x6)
-
-#define MPP21_GPIO21 MPP_PIN(21, 0x0)
-#define MPP21_UA1_RTSn MPP_PIN(21, 0x1)
-#define MPP21_SPI_LCD_CS0 MPP_PIN(21, 0x2)
-#define MPP21_SDIO1_WP MPP_PIN(21, 0x3)
-#define MPP21_SSP_SFRM MPP_PIN(21, 0x4)
-#define MPP21_SDIO0_WP MPP_PIN(21, 0x5)
-#define MPP21_SPI_1_CS MPP_PIN(21, 0x6)
-
-#define MPP22_GPIO22 MPP_PIN(22, 0x0)
-#define MPP22_UA1_CTSn MPP_PIN(22, 0x1)
-#define MPP22_SPI_LCD_MOSI MPP_PIN(22, 0x2)
-#define MPP22_SDIO1_BUS_POWER MPP_PIN(22, 0x3)
-#define MPP22_SSP_TXD MPP_PIN(22, 0x4)
-#define MPP22_SDIO0_BUS_POWER MPP_PIN(22, 0x5)
-#define MPP22_SPI_1_MOSI MPP_PIN(22, 0x6)
-
-#define MPP23_GPIO23 MPP_PIN(23, 0x0)
-#define MPP23_SPI_LCD_SCK MPP_PIN(23, 0x2)
-#define MPP23_SDIO1_LED_CTRL MPP_PIN(23, 0x3)
-#define MPP23_SSP_SCLK MPP_PIN(23, 0x4)
-#define MPP23_SDIO0_LED_CTRL MPP_PIN(23, 0x5)
-#define MPP23_SPI_1_SCK MPP_PIN(23, 0x6)
+#define MPP_GRP(_grp, _mode) MPP((_grp), (_mode), 0, 0)
/* for MPP groups _num is a group index */
enum dove_mpp_grp_idx {
@@ -181,40 +153,44 @@
MPP_46_51 = 1,
MPP_58_61 = 5,
MPP_62_63 = 4,
+ MPP_GRP_MAX = 5,
};
-#define MPP24_39_GPIO MPP_GRP(MPP_24_39, 0x1)
-#define MPP24_39_CAM MPP_GRP(MPP_24_39, 0x0)
+#define MPP_GRP_24_39_GPIO MPP_GRP(MPP_24_39, 0x1)
+#define MPP_GRP_24_39_CAM MPP_GRP(MPP_24_39, 0x0)
-#define MPP40_45_GPIO MPP_GRP(MPP_40_45, 0x1)
-#define MPP40_45_SD0 MPP_GRP(MPP_40_45, 0x0)
+#define MPP_GRP_40_45_GPIO MPP_GRP(MPP_40_45, 0x1)
+#define MPP_GRP_40_45_SD0 MPP_GRP(MPP_40_45, 0x0)
-#define MPP46_51_GPIO MPP_GRP(MPP_46_51, 0x1)
-#define MPP46_51_SD1 MPP_GRP(MPP_46_51, 0x0)
+#define MPP_GRP_46_51_GPIO MPP_GRP(MPP_46_51, 0x1)
+#define MPP_GRP_46_51_SD1 MPP_GRP(MPP_46_51, 0x0)
-#define MPP58_61_GPIO MPP_GRP(MPP_58_61, 0x1)
-#define MPP58_61_SPI MPP_GRP(MPP_58_61, 0x0)
+#define MPP_GRP_58_61_GPIO MPP_GRP(MPP_58_61, 0x1)
+#define MPP_GRP_58_61_SPI MPP_GRP(MPP_58_61, 0x0)
-#define MPP62_63_GPIO MPP_GRP(MPP_62_63, 0x1)
-#define MPP62_63_UA1 MPP_GRP(MPP_62_63, 0x0)
+#define MPP_GRP_62_63_GPIO MPP_GRP(MPP_62_63, 0x1)
+#define MPP_GRP_62_63_UA1 MPP_GRP(MPP_62_63, 0x0)
/* The MPP[64:71] control differs from other groups */
-#define MPP64_71_GPO MPP_GRP_NFC(0x1)
-#define MPP64_71_NFC MPP_GRP_NFC(0x0)
+#define MPP_GRP_NFC_64_71_GPO 0x1
+#define MPP_GRP_NFC_64_71_NFC 0x0
/*
* The MPP[52:57] functionality is encoded by 4 bits in different
* registers. The _num field in this case encodes those bits in
* correspodence with Table 135 of 88AP510 Functional specification
*/
-#define MPP52_57_AU1 MPP_GRP_AU1(0x0)
-#define MPP52_57_AU1_GPIO57 MPP_GRP_AU1(0x2)
-#define MPP52_57_GPIO MPP_GRP_AU1(0xa)
-#define MPP52_57_TW_GPIO MPP_GRP_AU1(0xb)
-#define MPP52_57_AU1_SSP MPP_GRP_AU1(0xc)
-#define MPP52_57_SSP_GPIO MPP_GRP_AU1(0xe)
-#define MPP52_57_SSP_TW MPP_GRP_AU1(0xf)
+#define MPP_GRP_AU1_52_57_AU1 0x0
+#define MPP_GRP_AU1_52_57_AU1_GPIO57 0x2
+#define MPP_GRP_AU1_52_57_GPIO 0xa
+#define MPP_GRP_AU1_52_57_TW_GPIO 0xb
+#define MPP_GRP_AU1_52_57_AU1_SSP 0xc
+#define MPP_GRP_AU1_52_57_SSP_GPIO 0xe
+#define MPP_GRP_AU1_52_57_SSP_TW 0xf
-void dove_mpp_conf(unsigned int *mpp_list);
+void dove_mpp_conf(unsigned int *mpp_list,
+ unsigned int *mpp_grp_list,
+ unsigned int grp_au1_52_57,
+ unsigned int grp_nfc_64_71);
#endif /* __ARCH_DOVE_MPP_CODED_H */
diff --git a/arch/arm/mach-ep93xx/gpio.c b/arch/arm/mach-ep93xx/gpio.c
index a5a9ff7..415dce3 100644
--- a/arch/arm/mach-ep93xx/gpio.c
+++ b/arch/arm/mach-ep93xx/gpio.c
@@ -356,29 +356,6 @@
return 0;
}
-static void ep93xx_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
-{
- struct ep93xx_gpio_chip *ep93xx_chip = to_ep93xx_gpio_chip(chip);
- u8 data_reg, data_dir_reg;
- int gpio, i;
-
- data_reg = __raw_readb(ep93xx_chip->data_reg);
- data_dir_reg = __raw_readb(ep93xx_chip->data_dir_reg);
-
- gpio = ep93xx_chip->chip.base;
- for (i = 0; i < chip->ngpio; i++, gpio++) {
- int is_out = data_dir_reg & (1 << i);
- int irq = gpio_to_irq(gpio);
-
- seq_printf(s, " %s%d gpio-%-3d (%-12s) %s %s %s\n",
- chip->label, i, gpio,
- gpiochip_is_requested(chip, i) ? : "",
- is_out ? "out" : "in ",
- (data_reg & (1<< i)) ? "hi" : "lo",
- (!is_out && irq>= 0) ? "(interrupt)" : "");
- }
-}
-
#define EP93XX_GPIO_BANK(name, dr, ddr, base_gpio) \
{ \
.chip = { \
@@ -387,7 +364,6 @@
.direction_output = ep93xx_gpio_direction_output, \
.get = ep93xx_gpio_get, \
.set = ep93xx_gpio_set, \
- .dbg_show = ep93xx_gpio_dbg_show, \
.base = base_gpio, \
.ngpio = 8, \
}, \
diff --git a/arch/arm/mach-exynos4/Kconfig b/arch/arm/mach-exynos4/Kconfig
index e849f67..8051962 100644
--- a/arch/arm/mach-exynos4/Kconfig
+++ b/arch/arm/mach-exynos4/Kconfig
@@ -170,6 +170,7 @@
select S3C_DEV_HSMMC3
select S3C_DEV_I2C1
select S3C_DEV_I2C5
+ select S5P_DEV_USB_EHCI
select EXYNOS4_SETUP_I2C1
select EXYNOS4_SETUP_I2C5
select EXYNOS4_SETUP_SDHCI
diff --git a/arch/arm/mach-exynos4/Makefile b/arch/arm/mach-exynos4/Makefile
index 9be104f..7778975 100644
--- a/arch/arm/mach-exynos4/Makefile
+++ b/arch/arm/mach-exynos4/Makefile
@@ -54,3 +54,5 @@
obj-$(CONFIG_EXYNOS4_SETUP_KEYPAD) += setup-keypad.o
obj-$(CONFIG_EXYNOS4_SETUP_SDHCI) += setup-sdhci.o
obj-$(CONFIG_EXYNOS4_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
+
+obj-$(CONFIG_USB_SUPPORT) += usb-phy.o
diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c
index 7930113..08813a6 100644
--- a/arch/arm/mach-exynos4/cpu.c
+++ b/arch/arm/mach-exynos4/cpu.c
@@ -97,7 +97,12 @@
.pfn = __phys_to_pfn(EXYNOS4_PA_SROMC),
.length = SZ_4K,
.type = MT_DEVICE,
- },
+ }, {
+ .virtual = (unsigned long)S5P_VA_USB_HSPHY,
+ .pfn = __phys_to_pfn(EXYNOS4_PA_HSPHY),
+ .length = SZ_4K,
+ .type = MT_DEVICE,
+ }
};
static void exynos4_idle(void)
diff --git a/arch/arm/mach-exynos4/include/mach/map.h b/arch/arm/mach-exynos4/include/mach/map.h
index 6330b73..0009e77 100644
--- a/arch/arm/mach-exynos4/include/mach/map.h
+++ b/arch/arm/mach-exynos4/include/mach/map.h
@@ -101,6 +101,9 @@
#define EXYNOS4_PA_SROMC 0x12570000
+#define EXYNOS4_PA_EHCI 0x12580000
+#define EXYNOS4_PA_HSPHY 0x125B0000
+
#define EXYNOS4_PA_UART 0x13800000
#define EXYNOS4_PA_IIC(x) (0x13860000 + ((x) * 0x10000))
@@ -143,6 +146,7 @@
#define S5P_PA_SROMC EXYNOS4_PA_SROMC
#define S5P_PA_SYSCON EXYNOS4_PA_SYSCON
#define S5P_PA_TIMER EXYNOS4_PA_TIMER
+#define S5P_PA_EHCI EXYNOS4_PA_EHCI
#define SAMSUNG_PA_KEYPAD EXYNOS4_PA_KEYPAD
diff --git a/arch/arm/mach-exynos4/include/mach/regs-pmu.h b/arch/arm/mach-exynos4/include/mach/regs-pmu.h
index 62b0014..a964337 100644
--- a/arch/arm/mach-exynos4/include/mach/regs-pmu.h
+++ b/arch/arm/mach-exynos4/include/mach/regs-pmu.h
@@ -33,6 +33,9 @@
#define S5P_EINT_WAKEUP_MASK S5P_PMUREG(0x0604)
#define S5P_WAKEUP_MASK S5P_PMUREG(0x0608)
+#define S5P_USBHOST_PHY_CONTROL S5P_PMUREG(0x0708)
+#define S5P_USBHOST_PHY_ENABLE (1 << 0)
+
#define S5P_MIPI_DPHY_CONTROL(n) S5P_PMUREG(0x0710 + (n) * 4)
#define S5P_MIPI_DPHY_ENABLE (1 << 0)
#define S5P_MIPI_DPHY_SRESETN (1 << 1)
diff --git a/arch/arm/mach-exynos4/include/mach/regs-usb-phy.h b/arch/arm/mach-exynos4/include/mach/regs-usb-phy.h
new file mode 100644
index 0000000..703118d
--- /dev/null
+++ b/arch/arm/mach-exynos4/include/mach/regs-usb-phy.h
@@ -0,0 +1,64 @@
+/*
+ * Copyright (C) 2011 Samsung Electronics Co.Ltd
+ * Author: Joonyoung Shim <jy0922.shim@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __PLAT_S5P_REGS_USB_PHY_H
+#define __PLAT_S5P_REGS_USB_PHY_H
+
+#define EXYNOS4_HSOTG_PHYREG(x) ((x) + S5P_VA_USB_HSPHY)
+
+#define EXYNOS4_PHYPWR EXYNOS4_HSOTG_PHYREG(0x00)
+#define PHY1_HSIC_NORMAL_MASK (0xf << 9)
+#define PHY1_HSIC1_SLEEP (1 << 12)
+#define PHY1_HSIC1_FORCE_SUSPEND (1 << 11)
+#define PHY1_HSIC0_SLEEP (1 << 10)
+#define PHY1_HSIC0_FORCE_SUSPEND (1 << 9)
+
+#define PHY1_STD_NORMAL_MASK (0x7 << 6)
+#define PHY1_STD_SLEEP (1 << 8)
+#define PHY1_STD_ANALOG_POWERDOWN (1 << 7)
+#define PHY1_STD_FORCE_SUSPEND (1 << 6)
+
+#define PHY0_NORMAL_MASK (0x39 << 0)
+#define PHY0_SLEEP (1 << 5)
+#define PHY0_OTG_DISABLE (1 << 4)
+#define PHY0_ANALOG_POWERDOWN (1 << 3)
+#define PHY0_FORCE_SUSPEND (1 << 0)
+
+#define EXYNOS4_PHYCLK EXYNOS4_HSOTG_PHYREG(0x04)
+#define PHY1_COMMON_ON_N (1 << 7)
+#define PHY0_COMMON_ON_N (1 << 4)
+#define PHY0_ID_PULLUP (1 << 2)
+#define CLKSEL_MASK (0x3 << 0)
+#define CLKSEL_SHIFT (0)
+#define CLKSEL_48M (0x0 << 0)
+#define CLKSEL_12M (0x2 << 0)
+#define CLKSEL_24M (0x3 << 0)
+
+#define EXYNOS4_RSTCON EXYNOS4_HSOTG_PHYREG(0x08)
+#define HOST_LINK_PORT_SWRST_MASK (0xf << 6)
+#define HOST_LINK_PORT2_SWRST (1 << 9)
+#define HOST_LINK_PORT1_SWRST (1 << 8)
+#define HOST_LINK_PORT0_SWRST (1 << 7)
+#define HOST_LINK_ALL_SWRST (1 << 6)
+
+#define PHY1_SWRST_MASK (0x7 << 3)
+#define PHY1_HSIC_SWRST (1 << 5)
+#define PHY1_STD_SWRST (1 << 4)
+#define PHY1_ALL_SWRST (1 << 3)
+
+#define PHY0_SWRST_MASK (0x7 << 0)
+#define PHY0_PHYLINK_SWRST (1 << 2)
+#define PHY0_HLINK_SWRST (1 << 1)
+#define PHY0_SWRST (1 << 0)
+
+#define EXYNOS4_PHY1CON EXYNOS4_HSOTG_PHYREG(0x34)
+#define FPENABLEN (1 << 0)
+
+#endif /* __PLAT_S5P_REGS_USB_PHY_H */
diff --git a/arch/arm/mach-exynos4/include/mach/smp.h b/arch/arm/mach-exynos4/include/mach/smp.h
deleted file mode 100644
index a463dce..0000000
--- a/arch/arm/mach-exynos4/include/mach/smp.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* linux/arch/arm/mach-exynos4/include/mach/smp.h
- *
- * Cloned from arch/arm/mach-realview/include/mach/smp.h
-*/
-
-#ifndef ASM_ARCH_SMP_H
-#define ASM_ARCH_SMP_H __FILE__
-
-#include <asm/hardware/gic.h>
-
-/*
- * We use IRQ1 as the IPI
- */
-static inline void smp_cross_call(const struct cpumask *mask, int ipi)
-{
- gic_raise_softirq(mask, ipi);
-}
-
-#endif
diff --git a/arch/arm/mach-exynos4/irq-combiner.c b/arch/arm/mach-exynos4/irq-combiner.c
index f488b66..5a2758a 100644
--- a/arch/arm/mach-exynos4/irq-combiner.c
+++ b/arch/arm/mach-exynos4/irq-combiner.c
@@ -59,8 +59,7 @@
unsigned int cascade_irq, combiner_irq;
unsigned long status;
- /* primary controller ack'ing */
- chip->irq_ack(&desc->irq_data);
+ chained_irq_enter(chip, desc);
spin_lock(&irq_controller_lock);
status = __raw_readl(chip_data->base + COMBINER_INT_STATUS);
@@ -79,8 +78,7 @@
generic_handle_irq(cascade_irq);
out:
- /* primary controller unmasking */
- chip->irq_unmask(&desc->irq_data);
+ chained_irq_exit(chip, desc);
}
static struct irq_chip combiner_chip = {
diff --git a/arch/arm/mach-exynos4/mach-nuri.c b/arch/arm/mach-exynos4/mach-nuri.c
index b79ad01..bb5d12f 100644
--- a/arch/arm/mach-exynos4/mach-nuri.c
+++ b/arch/arm/mach-exynos4/mach-nuri.c
@@ -30,6 +30,8 @@
#include <plat/cpu.h>
#include <plat/devs.h>
#include <plat/sdhci.h>
+#include <plat/ehci.h>
+#include <plat/clock.h>
#include <mach/map.h>
@@ -262,6 +264,16 @@
/* max8997, To be updated */
};
+/* USB EHCI */
+static struct s5p_ehci_platdata nuri_ehci_pdata;
+
+static void __init nuri_ehci_init(void)
+{
+ struct s5p_ehci_platdata *pdata = &nuri_ehci_pdata;
+
+ s5p_ehci_set_platdata(pdata);
+}
+
static struct platform_device *nuri_devices[] __initdata = {
/* Samsung Platform Devices */
&emmc_fixed_voltage,
@@ -270,6 +282,7 @@
&s3c_device_hsmmc3,
&s3c_device_wdt,
&s3c_device_timer[0],
+ &s5p_device_ehci,
/* NURI Devices */
&nuri_gpio_keys,
@@ -291,6 +304,9 @@
i2c_register_board_info(1, i2c1_devs, ARRAY_SIZE(i2c1_devs));
i2c_register_board_info(5, i2c5_devs, ARRAY_SIZE(i2c5_devs));
+ nuri_ehci_init();
+ clk_xusbxti.rate = 24000000;
+
/* Last */
platform_add_devices(nuri_devices, ARRAY_SIZE(nuri_devices));
}
diff --git a/arch/arm/mach-exynos4/platsmp.c b/arch/arm/mach-exynos4/platsmp.c
index 6d35878..c5e65a0 100644
--- a/arch/arm/mach-exynos4/platsmp.c
+++ b/arch/arm/mach-exynos4/platsmp.c
@@ -22,6 +22,7 @@
#include <linux/io.h>
#include <asm/cacheflush.h>
+#include <asm/hardware/gic.h>
#include <asm/smp_scu.h>
#include <asm/unified.h>
@@ -104,7 +105,7 @@
* the boot monitor to read the system wide flags register,
* and branch to the address found there.
*/
- smp_cross_call(cpumask_of(cpu), 1);
+ gic_raise_softirq(cpumask_of(cpu), 1);
timeout = jiffies + (1 * HZ);
while (time_before(jiffies, timeout)) {
@@ -147,6 +148,8 @@
for (i = 0; i < ncores; i++)
set_cpu_possible(i, true);
+
+ set_smp_cross_call(gic_raise_softirq);
}
void __init platform_smp_prepare_cpus(unsigned int max_cpus)
diff --git a/arch/arm/mach-exynos4/usb-phy.c b/arch/arm/mach-exynos4/usb-phy.c
new file mode 100644
index 0000000..0883c1b
--- /dev/null
+++ b/arch/arm/mach-exynos4/usb-phy.c
@@ -0,0 +1,136 @@
+/*
+ * Copyright (C) 2011 Samsung Electronics Co.Ltd
+ * Author: Joonyoung Shim <jy0922.shim@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/platform_device.h>
+#include <mach/regs-pmu.h>
+#include <mach/regs-usb-phy.h>
+#include <plat/cpu.h>
+#include <plat/usb-phy.h>
+
+static int exynos4_usb_phy1_init(struct platform_device *pdev)
+{
+ struct clk *otg_clk;
+ struct clk *xusbxti_clk;
+ u32 phyclk;
+ u32 rstcon;
+ int err;
+
+ otg_clk = clk_get(&pdev->dev, "otg");
+ if (IS_ERR(otg_clk)) {
+ dev_err(&pdev->dev, "Failed to get otg clock\n");
+ return PTR_ERR(otg_clk);
+ }
+
+ err = clk_enable(otg_clk);
+ if (err) {
+ clk_put(otg_clk);
+ return err;
+ }
+
+ writel(readl(S5P_USBHOST_PHY_CONTROL) | S5P_USBHOST_PHY_ENABLE,
+ S5P_USBHOST_PHY_CONTROL);
+
+ /* set clock frequency for PLL */
+ phyclk = readl(EXYNOS4_PHYCLK) & ~CLKSEL_MASK;
+
+ xusbxti_clk = clk_get(&pdev->dev, "xusbxti");
+ if (xusbxti_clk && !IS_ERR(xusbxti_clk)) {
+ switch (clk_get_rate(xusbxti_clk)) {
+ case 12 * MHZ:
+ phyclk |= CLKSEL_12M;
+ break;
+ case 24 * MHZ:
+ phyclk |= CLKSEL_24M;
+ break;
+ default:
+ case 48 * MHZ:
+ /* default reference clock */
+ break;
+ }
+ clk_put(xusbxti_clk);
+ }
+
+ writel(phyclk, EXYNOS4_PHYCLK);
+
+ /* floating prevention logic: disable */
+ writel((readl(EXYNOS4_PHY1CON) | FPENABLEN), EXYNOS4_PHY1CON);
+
+ /* set to normal HSIC 0 and 1 of PHY1 */
+ writel((readl(EXYNOS4_PHYPWR) & ~PHY1_HSIC_NORMAL_MASK),
+ EXYNOS4_PHYPWR);
+
+ /* set to normal standard USB of PHY1 */
+ writel((readl(EXYNOS4_PHYPWR) & ~PHY1_STD_NORMAL_MASK), EXYNOS4_PHYPWR);
+
+ /* reset all ports of both PHY and Link */
+ rstcon = readl(EXYNOS4_RSTCON) | HOST_LINK_PORT_SWRST_MASK |
+ PHY1_SWRST_MASK;
+ writel(rstcon, EXYNOS4_RSTCON);
+ udelay(10);
+
+ rstcon &= ~(HOST_LINK_PORT_SWRST_MASK | PHY1_SWRST_MASK);
+ writel(rstcon, EXYNOS4_RSTCON);
+ udelay(50);
+
+ clk_disable(otg_clk);
+ clk_put(otg_clk);
+
+ return 0;
+}
+
+static int exynos4_usb_phy1_exit(struct platform_device *pdev)
+{
+ struct clk *otg_clk;
+ int err;
+
+ otg_clk = clk_get(&pdev->dev, "otg");
+ if (IS_ERR(otg_clk)) {
+ dev_err(&pdev->dev, "Failed to get otg clock\n");
+ return PTR_ERR(otg_clk);
+ }
+
+ err = clk_enable(otg_clk);
+ if (err) {
+ clk_put(otg_clk);
+ return err;
+ }
+
+ writel((readl(EXYNOS4_PHYPWR) | PHY1_STD_ANALOG_POWERDOWN),
+ EXYNOS4_PHYPWR);
+
+ writel(readl(S5P_USBHOST_PHY_CONTROL) & ~S5P_USBHOST_PHY_ENABLE,
+ S5P_USBHOST_PHY_CONTROL);
+
+ clk_disable(otg_clk);
+ clk_put(otg_clk);
+
+ return 0;
+}
+
+int s5p_usb_phy_init(struct platform_device *pdev, int type)
+{
+ if (type == S5P_USB_PHY_HOST)
+ return exynos4_usb_phy1_init(pdev);
+
+ return -EINVAL;
+}
+
+int s5p_usb_phy_exit(struct platform_device *pdev, int type)
+{
+ if (type == S5P_USB_PHY_HOST)
+ return exynos4_usb_phy1_exit(pdev);
+
+ return -EINVAL;
+}
diff --git a/arch/arm/mach-gemini/include/mach/uncompress.h b/arch/arm/mach-gemini/include/mach/uncompress.h
index 5483f61..0efa262 100644
--- a/arch/arm/mach-gemini/include/mach/uncompress.h
+++ b/arch/arm/mach-gemini/include/mach/uncompress.h
@@ -16,7 +16,7 @@
#include <linux/serial_reg.h>
#include <mach/hardware.h>
-static volatile unsigned long *UART = (unsigned long *)GEMINI_UART_BASE;
+static volatile unsigned long * const UART = (unsigned long *)GEMINI_UART_BASE;
/*
* The following code assumes the serial port has already been
diff --git a/arch/arm/mach-h720x/include/mach/memory.h b/arch/arm/mach-h720x/include/mach/memory.h
index 9d36876..b0b3bae 100644
--- a/arch/arm/mach-h720x/include/mach/memory.h
+++ b/arch/arm/mach-h720x/include/mach/memory.h
@@ -13,7 +13,6 @@
* There should not be more than (0xd0000000 - 0xc0000000)
* bytes of RAM.
*/
-#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_256M - 1)
-#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_256M)
+#define ARM_DMA_ZONE_SIZE SZ_256M
#endif
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 56b930a..59c97a3 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -1,5 +1,15 @@
config IMX_HAVE_DMA_V1
bool
+#
+# ARCH_MX31 and ARCH_MX35 are left for compatibility
+# Some usages assume that having one of them implies not having (e.g.) ARCH_MX2.
+# To easily distinguish good and reviewed from unreviewed usages new (and IMHO
+# more sensible) names are used: SOC_IMX31 and SOC_IMX35
+config ARCH_MX31
+ bool
+
+config ARCH_MX35
+ bool
config SOC_IMX1
bool
@@ -31,6 +41,24 @@
select IMX_HAVE_IOMUX_V1
select MXC_AVIC
+config SOC_IMX31
+ bool
+ select CPU_V6
+ select IMX_HAVE_PLATFORM_MXC_RNGA
+ select ARCH_MXC_AUDMUX_V2
+ select ARCH_MX31
+ select MXC_AVIC
+
+config SOC_IMX35
+ bool
+ select CPU_V6
+ select ARCH_MXC_IOMUX_V3
+ select ARCH_MXC_AUDMUX_V2
+ select HAVE_EPIT
+ select ARCH_MX35
+ select MXC_AVIC
+
+
if ARCH_MX1
comment "MX1 platforms:"
@@ -40,6 +68,7 @@
config ARCH_MX1ADS
bool "MX1ADS platform"
select MACH_MXLADS
+ select SOC_IMX1
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
help
@@ -51,6 +80,13 @@
help
Say Y here if you are using a Synertronixx scb9328 board
+config MACH_APF9328
+ bool "APF9328"
+ select SOC_IMX1
+ select IMX_HAVE_PLATFORM_IMX_UART
+ help
+ Say Yes here if you are using the Armadeus APF9328 development board
+
endif
if ARCH_MX2
@@ -129,6 +165,7 @@
config MACH_EUKREA_MBIMXSD25_BASEBOARD
bool "Eukrea MBIMXSD development board"
+ select IMX_HAVE_PLATFORM_GPIO_KEYS
select IMX_HAVE_PLATFORM_IMX_SSI
help
This adds board specific devices that can be found on Eukrea's
@@ -254,6 +291,7 @@
config MACH_IMX27_VISSTRIM_M10
bool "Vista Silicon i.MX27 Visstrim_m10"
select SOC_IMX27
+ select IMX_HAVE_PLATFORM_GPIO_KEYS
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_SSI
select IMX_HAVE_PLATFORM_IMX_UART
@@ -314,3 +352,251 @@
configurations for the board and its peripherals.
endif
+
+if ARCH_MX3
+
+comment "MX31 platforms:"
+
+config MACH_MX31ADS
+ bool "Support MX31ADS platforms"
+ select SOC_IMX31
+ select IMX_HAVE_PLATFORM_IMX_I2C
+ select IMX_HAVE_PLATFORM_IMX_SSI
+ select IMX_HAVE_PLATFORM_IMX_UART
+ default y
+ help
+ Include support for MX31ADS platform. This includes specific
+ configurations for the board and its peripherals.
+
+config MACH_MX31ADS_WM1133_EV1
+ bool "Support Wolfson Microelectronics 1133-EV1 module"
+ depends on MACH_MX31ADS
+ depends on MFD_WM8350_I2C
+ depends on REGULATOR_WM8350
+ select MFD_WM8350_CONFIG_MODE_0
+ select MFD_WM8352_CONFIG_MODE_0
+ help
+ Include support for the Wolfson Microelectronics 1133-EV1 PMU
+ and audio module for the MX31ADS platform.
+
+config MACH_MX31LILLY
+ bool "Support MX31 LILLY-1131 platforms (INCO startec)"
+ select SOC_IMX31
+ select IMX_HAVE_PLATFORM_IMX_UART
+ select IMX_HAVE_PLATFORM_IPU_CORE
+ select IMX_HAVE_PLATFORM_MXC_EHCI
+ select IMX_HAVE_PLATFORM_MXC_MMC
+ select IMX_HAVE_PLATFORM_SPI_IMX
+ select MXC_ULPI if USB_ULPI
+ help
+ Include support for mx31 based LILLY1131 modules. This includes
+ specific configurations for the board and its peripherals.
+
+config MACH_MX31LITE
+ bool "Support MX31 LITEKIT (LogicPD)"
+ select SOC_IMX31
+ select MXC_ULPI if USB_ULPI
+ select IMX_HAVE_PLATFORM_IMX2_WDT
+ select IMX_HAVE_PLATFORM_IMX_UART
+ select IMX_HAVE_PLATFORM_MXC_EHCI
+ select IMX_HAVE_PLATFORM_MXC_MMC
+ select IMX_HAVE_PLATFORM_MXC_NAND
+ select IMX_HAVE_PLATFORM_MXC_RTC
+ select IMX_HAVE_PLATFORM_SPI_IMX
+ help
+ Include support for MX31 LITEKIT platform. This includes specific
+ configurations for the board and its peripherals.
+
+config MACH_PCM037
+ bool "Support Phytec pcm037 (i.MX31) platforms"
+ select SOC_IMX31
+ select IMX_HAVE_PLATFORM_FSL_USB2_UDC
+ select IMX_HAVE_PLATFORM_IMX2_WDT
+ select IMX_HAVE_PLATFORM_IMX_I2C
+ select IMX_HAVE_PLATFORM_IMX_UART
+ select IMX_HAVE_PLATFORM_IPU_CORE
+ select IMX_HAVE_PLATFORM_MXC_EHCI
+ select IMX_HAVE_PLATFORM_MXC_MMC
+ select IMX_HAVE_PLATFORM_MXC_NAND
+ select IMX_HAVE_PLATFORM_MXC_W1
+ select MXC_ULPI if USB_ULPI
+ help
+ Include support for Phytec pcm037 platform. This includes
+ specific configurations for the board and its peripherals.
+
+config MACH_PCM037_EET
+ bool "Support pcm037 EET board extensions"
+ depends on MACH_PCM037
+ select IMX_HAVE_PLATFORM_GPIO_KEYS
+ select IMX_HAVE_PLATFORM_SPI_IMX
+ help
+ Add support for PCM037 EET baseboard extensions. If you are using the
+ OLED display with EET, use "video=mx3fb:CMEL-OLED" kernel
+ command-line parameter.
+
+config MACH_MX31_3DS
+ bool "Support MX31PDK (3DS)"
+ select SOC_IMX31
+ select MXC_DEBUG_BOARD
+ select IMX_HAVE_PLATFORM_FSL_USB2_UDC
+ select IMX_HAVE_PLATFORM_IMX2_WDT
+ select IMX_HAVE_PLATFORM_IMX_I2C
+ select IMX_HAVE_PLATFORM_IMX_KEYPAD
+ select IMX_HAVE_PLATFORM_IMX_UART
+ select IMX_HAVE_PLATFORM_IPU_CORE
+ select IMX_HAVE_PLATFORM_MXC_EHCI
+ select IMX_HAVE_PLATFORM_MXC_NAND
+ select IMX_HAVE_PLATFORM_SPI_IMX
+ select MXC_ULPI if USB_ULPI
+ help
+ Include support for MX31PDK (3DS) platform. This includes specific
+ configurations for the board and its peripherals.
+
+config MACH_MX31_3DS_MXC_NAND_USE_BBT
+ bool "Make the MXC NAND driver use the in flash Bad Block Table"
+ depends on MACH_MX31_3DS
+ depends on MTD_NAND_MXC
+ help
+ Enable this if you want that the MXC NAND driver uses the in flash
+ Bad Block Table to know what blocks are bad instead of scanning the
+ entire flash looking for bad block markers.
+
+config MACH_MX31MOBOARD
+ bool "Support mx31moboard platforms (EPFL Mobots group)"
+ select SOC_IMX31
+ select IMX_HAVE_PLATFORM_FSL_USB2_UDC
+ select IMX_HAVE_PLATFORM_IMX_I2C
+ select IMX_HAVE_PLATFORM_IMX_UART
+ select IMX_HAVE_PLATFORM_IPU_CORE
+ select IMX_HAVE_PLATFORM_MXC_EHCI
+ select IMX_HAVE_PLATFORM_MXC_MMC
+ select IMX_HAVE_PLATFORM_SPI_IMX
+ select MXC_ULPI if USB_ULPI
+ help
+ Include support for mx31moboard platform. This includes specific
+ configurations for the board and its peripherals.
+
+config MACH_QONG
+ bool "Support Dave/DENX QongEVB-LITE platform"
+ select SOC_IMX31
+ select IMX_HAVE_PLATFORM_IMX_UART
+ help
+ Include support for Dave/DENX QongEVB-LITE platform. This includes
+ specific configurations for the board and its peripherals.
+
+config MACH_ARMADILLO5X0
+ bool "Support Atmark Armadillo-500 Development Base Board"
+ select SOC_IMX31
+ select IMX_HAVE_PLATFORM_GPIO_KEYS
+ select IMX_HAVE_PLATFORM_IMX_I2C
+ select IMX_HAVE_PLATFORM_IMX_UART
+ select IMX_HAVE_PLATFORM_IPU_CORE
+ select IMX_HAVE_PLATFORM_MXC_EHCI
+ select IMX_HAVE_PLATFORM_MXC_MMC
+ select IMX_HAVE_PLATFORM_MXC_NAND
+ select MXC_ULPI if USB_ULPI
+ help
+ Include support for Atmark Armadillo-500 platform. This includes
+ specific configurations for the board and its peripherals.
+
+config MACH_KZM_ARM11_01
+ bool "Support KZM-ARM11-01(Kyoto Microcomputer)"
+ select SOC_IMX31
+ select IMX_HAVE_PLATFORM_IMX_UART
+ help
+ Include support for KZM-ARM11-01. This includes specific
+ configurations for the board and its peripherals.
+
+config MACH_BUG
+ bool "Support Buglabs BUGBase platform"
+ select SOC_IMX31
+ select IMX_HAVE_PLATFORM_IMX_UART
+ default y
+ help
+ Include support for BUGBase 1.3 platform. This includes specific
+ configurations for the board and its peripherals.
+
+comment "MX35 platforms:"
+
+config MACH_PCM043
+ bool "Support Phytec pcm043 (i.MX35) platforms"
+ select SOC_IMX35
+ select IMX_HAVE_PLATFORM_FLEXCAN
+ select IMX_HAVE_PLATFORM_FSL_USB2_UDC
+ select IMX_HAVE_PLATFORM_IMX2_WDT
+ select IMX_HAVE_PLATFORM_IMX_I2C
+ select IMX_HAVE_PLATFORM_IMX_SSI
+ select IMX_HAVE_PLATFORM_IMX_UART
+ select IMX_HAVE_PLATFORM_IPU_CORE
+ select IMX_HAVE_PLATFORM_MXC_EHCI
+ select IMX_HAVE_PLATFORM_MXC_NAND
+ select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
+ select MXC_ULPI if USB_ULPI
+ help
+ Include support for Phytec pcm043 platform. This includes
+ specific configurations for the board and its peripherals.
+
+config MACH_MX35_3DS
+ bool "Support MX35PDK platform"
+ select SOC_IMX35
+ select MXC_DEBUG_BOARD
+ select IMX_HAVE_PLATFORM_FSL_USB2_UDC
+ select IMX_HAVE_PLATFORM_IMX2_WDT
+ select IMX_HAVE_PLATFORM_IMX_I2C
+ select IMX_HAVE_PLATFORM_IMX_UART
+ select IMX_HAVE_PLATFORM_MXC_EHCI
+ select IMX_HAVE_PLATFORM_MXC_NAND
+ select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
+ help
+ Include support for MX35PDK platform. This includes specific
+ configurations for the board and its peripherals.
+
+config MACH_EUKREA_CPUIMX35
+ bool "Support Eukrea CPUIMX35 Platform"
+ select SOC_IMX35
+ select IMX_HAVE_PLATFORM_FLEXCAN
+ select IMX_HAVE_PLATFORM_FSL_USB2_UDC
+ select IMX_HAVE_PLATFORM_IMX2_WDT
+ select IMX_HAVE_PLATFORM_IMX_I2C
+ select IMX_HAVE_PLATFORM_IMX_UART
+ select IMX_HAVE_PLATFORM_MXC_EHCI
+ select IMX_HAVE_PLATFORM_MXC_NAND
+ select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
+ select MXC_ULPI if USB_ULPI
+ help
+ Include support for Eukrea CPUIMX35 platform. This includes
+ specific configurations for the board and its peripherals.
+
+choice
+ prompt "Baseboard"
+ depends on MACH_EUKREA_CPUIMX35
+ default MACH_EUKREA_MBIMXSD35_BASEBOARD
+
+config MACH_EUKREA_MBIMXSD35_BASEBOARD
+ bool "Eukrea MBIMXSD development board"
+ select IMX_HAVE_PLATFORM_GPIO_KEYS
+ select IMX_HAVE_PLATFORM_IMX_SSI
+ select IMX_HAVE_PLATFORM_IPU_CORE
+ help
+ This adds board specific devices that can be found on Eukrea's
+ MBIMXSD evaluation board.
+
+endchoice
+
+config MACH_VPR200
+ bool "Support VPR200 platform"
+ select SOC_IMX35
+ select IMX_HAVE_PLATFORM_FSL_USB2_UDC
+ select IMX_HAVE_PLATFORM_GPIO_KEYS
+ select IMX_HAVE_PLATFORM_IMX2_WDT
+ select IMX_HAVE_PLATFORM_IMX_UART
+ select IMX_HAVE_PLATFORM_IMX_I2C
+ select IMX_HAVE_PLATFORM_IPU_CORE
+ select IMX_HAVE_PLATFORM_MXC_EHCI
+ select IMX_HAVE_PLATFORM_MXC_NAND
+ select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
+ help
+ Include support for VPR200 platform. This includes specific
+ configurations for the board and its peripherals.
+
+endif
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index b85794d..e9eb36d 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -1,9 +1,3 @@
-#
-# Makefile for the linux kernel.
-#
-
-# Object file lists.
-
obj-$(CONFIG_IMX_HAVE_DMA_V1) += dma-v1.o
obj-$(CONFIG_ARCH_MX1) += clock-imx1.o mm-imx1.o
@@ -14,18 +8,27 @@
obj-$(CONFIG_MACH_MX27) += cpu-imx27.o pm-imx27.o
obj-$(CONFIG_MACH_MX27) += clock-imx27.o mm-imx27.o ehci-imx27.o
-# Support for CMOS sensor interface
-obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o
+obj-$(CONFIG_SOC_IMX31) += mm-imx31.o cpu-imx31.o clock-imx31.o iomux-imx31.o ehci-imx31.o
+obj-$(CONFIG_SOC_IMX35) += mm-imx35.o cpu-imx35.o clock-imx35.o ehci-imx35.o
+obj-$(CONFIG_CACHE_L2X0) += cache-l2x0.o
+# Support for CMOS sensor interface
+obj-$(CONFIG_MX1_VIDEO) += mx1-camera-fiq.o mx1-camera-fiq-ksym.o
+
+# i.MX1 based machines
obj-$(CONFIG_ARCH_MX1ADS) += mach-mx1ads.o
obj-$(CONFIG_MACH_SCB9328) += mach-scb9328.o
+obj-$(CONFIG_MACH_APF9328) += mach-apf9328.o
+# i.MX21 based machines
obj-$(CONFIG_MACH_MX21ADS) += mach-mx21ads.o
+# i.MX25 based machines
obj-$(CONFIG_MACH_MX25_3DS) += mach-mx25_3ds.o
obj-$(CONFIG_MACH_EUKREA_CPUIMX25) += mach-eukrea_cpuimx25.o
obj-$(CONFIG_MACH_EUKREA_MBIMXSD25_BASEBOARD) += eukrea_mbimxsd25-baseboard.o
+# i.MX27 based machines
obj-$(CONFIG_MACH_MX27ADS) += mach-mx27ads.o
obj-$(CONFIG_MACH_PCM038) += mach-pcm038.o
obj-$(CONFIG_MACH_PCM970_BASEBOARD) += pcm970-baseboard.o
@@ -37,3 +40,24 @@
obj-$(CONFIG_MACH_PCA100) += mach-pca100.o
obj-$(CONFIG_MACH_MXT_TD60) += mach-mxt_td60.o
obj-$(CONFIG_MACH_IMX27IPCAM) += mach-imx27ipcam.o
+
+# i.MX31 based machines
+obj-$(CONFIG_MACH_MX31ADS) += mach-mx31ads.o
+obj-$(CONFIG_MACH_MX31LILLY) += mach-mx31lilly.o mx31lilly-db.o
+obj-$(CONFIG_MACH_MX31LITE) += mach-mx31lite.o mx31lite-db.o
+obj-$(CONFIG_MACH_PCM037) += mach-pcm037.o
+obj-$(CONFIG_MACH_PCM037_EET) += mach-pcm037_eet.o
+obj-$(CONFIG_MACH_MX31_3DS) += mach-mx31_3ds.o
+obj-$(CONFIG_MACH_MX31MOBOARD) += mach-mx31moboard.o mx31moboard-devboard.o \
+ mx31moboard-marxbot.o mx31moboard-smartbot.o
+obj-$(CONFIG_MACH_QONG) += mach-qong.o
+obj-$(CONFIG_MACH_ARMADILLO5X0) += mach-armadillo5x0.o
+obj-$(CONFIG_MACH_KZM_ARM11_01) += mach-kzm_arm11_01.o
+obj-$(CONFIG_MACH_BUG) += mach-bug.o
+
+# i.MX35 based machines
+obj-$(CONFIG_MACH_PCM043) += mach-pcm043.o
+obj-$(CONFIG_MACH_MX35_3DS) += mach-mx35_3ds.o
+obj-$(CONFIG_MACH_EUKREA_CPUIMX35) += mach-cpuimx35.o
+obj-$(CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD) += eukrea_mbimxsd35-baseboard.o
+obj-$(CONFIG_MACH_VPR200) += mach-vpr200.o
diff --git a/arch/arm/mach-imx/Makefile.boot b/arch/arm/mach-imx/Makefile.boot
index 3953d60..ebee18b 100644
--- a/arch/arm/mach-imx/Makefile.boot
+++ b/arch/arm/mach-imx/Makefile.boot
@@ -13,3 +13,7 @@
zreladdr-$(CONFIG_MACH_MX27) := 0xA0008000
params_phys-$(CONFIG_MACH_MX27) := 0xA0000100
initrd_phys-$(CONFIG_MACH_MX27) := 0xA0800000
+
+zreladdr-$(CONFIG_ARCH_MX3) := 0x80008000
+params_phys-$(CONFIG_ARCH_MX3) := 0x80000100
+initrd_phys-$(CONFIG_ARCH_MX3) := 0x80800000
diff --git a/arch/arm/mach-imx/cache-l2x0.c b/arch/arm/mach-imx/cache-l2x0.c
new file mode 100644
index 0000000..69d1322
--- /dev/null
+++ b/arch/arm/mach-imx/cache-l2x0.c
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2009-2010 Pengutronix
+ * Sascha Hauer <s.hauer@pengutronix.de>
+ * Juergen Beisert <j.beisert@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/kernel.h>
+
+#include <asm/hardware/cache-l2x0.h>
+
+#include <mach/hardware.h>
+
+static int mxc_init_l2x0(void)
+{
+ void __iomem *l2x0_base;
+ void __iomem *clkctl_base;
+
+ if (!cpu_is_mx31() && !cpu_is_mx35())
+ return 0;
+
+/*
+ * First of all, we must repair broken chip settings. There are some
+ * i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These
+ * misconfigured CPUs will run amok immediately when the L2 cache gets enabled.
+ * Workaraound is to setup the correct register setting prior enabling the
+ * L2 cache. This should not hurt already working CPUs, as they are using the
+ * same value.
+ */
+#define L2_MEM_VAL 0x10
+
+ clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096);
+ if (clkctl_base != NULL) {
+ writel(0x00000515, clkctl_base + L2_MEM_VAL);
+ iounmap(clkctl_base);
+ } else {
+ pr_err("L2 cache: Cannot fix timing. Trying to continue without\n");
+ }
+
+ l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096);
+ if (IS_ERR(l2x0_base)) {
+ printk(KERN_ERR "remapping L2 cache area failed with %ld\n",
+ PTR_ERR(l2x0_base));
+ return 0;
+ }
+
+ l2x0_init(l2x0_base, 0x00030024, 0x00000000);
+
+ return 0;
+}
+arch_initcall(mxc_init_l2x0);
diff --git a/arch/arm/mach-imx/clock-imx31.c b/arch/arm/mach-imx/clock-imx31.c
new file mode 100644
index 0000000..25f343f
--- /dev/null
+++ b/arch/arm/mach-imx/clock-imx31.c
@@ -0,0 +1,629 @@
+/*
+ * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/spinlock.h>
+#include <linux/delay.h>
+#include <linux/clk.h>
+#include <linux/err.h>
+#include <linux/io.h>
+#include <linux/clkdev.h>
+
+#include <asm/div64.h>
+
+#include <mach/clock.h>
+#include <mach/hardware.h>
+#include <mach/mx31.h>
+#include <mach/common.h>
+
+#include "crmregs-imx31.h"
+
+#define PRE_DIV_MIN_FREQ 10000000 /* Minimum Frequency after Predivider */
+
+static void __calc_pre_post_dividers(u32 div, u32 *pre, u32 *post)
+{
+ u32 min_pre, temp_pre, old_err, err;
+
+ if (div >= 512) {
+ *pre = 8;
+ *post = 64;
+ } else if (div >= 64) {
+ min_pre = (div - 1) / 64 + 1;
+ old_err = 8;
+ for (temp_pre = 8; temp_pre >= min_pre; temp_pre--) {
+ err = div % temp_pre;
+ if (err == 0) {
+ *pre = temp_pre;
+ break;
+ }
+ err = temp_pre - err;
+ if (err < old_err) {
+ old_err = err;
+ *pre = temp_pre;
+ }
+ }
+ *post = (div + *pre - 1) / *pre;
+ } else if (div <= 8) {
+ *pre = div;
+ *post = 1;
+ } else {
+ *pre = 1;
+ *post = div;
+ }
+}
+
+static struct clk mcu_pll_clk;
+static struct clk serial_pll_clk;
+static struct clk ipg_clk;
+static struct clk ckih_clk;
+
+static int cgr_enable(struct clk *clk)
+{
+ u32 reg;
+
+ if (!clk->enable_reg)
+ return 0;
+
+ reg = __raw_readl(clk->enable_reg);
+ reg |= 3 << clk->enable_shift;
+ __raw_writel(reg, clk->enable_reg);
+
+ return 0;
+}
+
+static void cgr_disable(struct clk *clk)
+{
+ u32 reg;
+
+ if (!clk->enable_reg)
+ return;
+
+ reg = __raw_readl(clk->enable_reg);
+ reg &= ~(3 << clk->enable_shift);
+
+ /* special case for EMI clock */
+ if (clk->enable_reg == MXC_CCM_CGR2 && clk->enable_shift == 8)
+ reg |= (1 << clk->enable_shift);
+
+ __raw_writel(reg, clk->enable_reg);
+}
+
+static unsigned long pll_ref_get_rate(void)
+{
+ unsigned long ccmr;
+ unsigned int prcs;
+
+ ccmr = __raw_readl(MXC_CCM_CCMR);
+ prcs = (ccmr & MXC_CCM_CCMR_PRCS_MASK) >> MXC_CCM_CCMR_PRCS_OFFSET;
+ if (prcs == 0x1)
+ return CKIL_CLK_FREQ * 1024;
+ else
+ return clk_get_rate(&ckih_clk);
+}
+
+static unsigned long usb_pll_get_rate(struct clk *clk)
+{
+ unsigned long reg;
+
+ reg = __raw_readl(MXC_CCM_UPCTL);
+
+ return mxc_decode_pll(reg, pll_ref_get_rate());
+}
+
+static unsigned long serial_pll_get_rate(struct clk *clk)
+{
+ unsigned long reg;
+
+ reg = __raw_readl(MXC_CCM_SRPCTL);
+
+ return mxc_decode_pll(reg, pll_ref_get_rate());
+}
+
+static unsigned long mcu_pll_get_rate(struct clk *clk)
+{
+ unsigned long reg, ccmr;
+
+ ccmr = __raw_readl(MXC_CCM_CCMR);
+
+ if (!(ccmr & MXC_CCM_CCMR_MPE) || (ccmr & MXC_CCM_CCMR_MDS))
+ return clk_get_rate(&ckih_clk);
+
+ reg = __raw_readl(MXC_CCM_MPCTL);
+
+ return mxc_decode_pll(reg, pll_ref_get_rate());
+}
+
+static int usb_pll_enable(struct clk *clk)
+{
+ u32 reg;
+
+ reg = __raw_readl(MXC_CCM_CCMR);
+ reg |= MXC_CCM_CCMR_UPE;
+ __raw_writel(reg, MXC_CCM_CCMR);
+
+ /* No lock bit on MX31, so using max time from spec */
+ udelay(80);
+
+ return 0;
+}
+
+static void usb_pll_disable(struct clk *clk)
+{
+ u32 reg;
+
+ reg = __raw_readl(MXC_CCM_CCMR);
+ reg &= ~MXC_CCM_CCMR_UPE;
+ __raw_writel(reg, MXC_CCM_CCMR);
+}
+
+static int serial_pll_enable(struct clk *clk)
+{
+ u32 reg;
+
+ reg = __raw_readl(MXC_CCM_CCMR);
+ reg |= MXC_CCM_CCMR_SPE;
+ __raw_writel(reg, MXC_CCM_CCMR);
+
+ /* No lock bit on MX31, so using max time from spec */
+ udelay(80);
+
+ return 0;
+}
+
+static void serial_pll_disable(struct clk *clk)
+{
+ u32 reg;
+
+ reg = __raw_readl(MXC_CCM_CCMR);
+ reg &= ~MXC_CCM_CCMR_SPE;
+ __raw_writel(reg, MXC_CCM_CCMR);
+}
+
+#define PDR0(mask, off) ((__raw_readl(MXC_CCM_PDR0) & mask) >> off)
+#define PDR1(mask, off) ((__raw_readl(MXC_CCM_PDR1) & mask) >> off)
+#define PDR2(mask, off) ((__raw_readl(MXC_CCM_PDR2) & mask) >> off)
+
+static unsigned long mcu_main_get_rate(struct clk *clk)
+{
+ u32 pmcr0 = __raw_readl(MXC_CCM_PMCR0);
+
+ if ((pmcr0 & MXC_CCM_PMCR0_DFSUP1) == MXC_CCM_PMCR0_DFSUP1_SPLL)
+ return clk_get_rate(&serial_pll_clk);
+ else
+ return clk_get_rate(&mcu_pll_clk);
+}
+
+static unsigned long ahb_get_rate(struct clk *clk)
+{
+ unsigned long max_pdf;
+
+ max_pdf = PDR0(MXC_CCM_PDR0_MAX_PODF_MASK,
+ MXC_CCM_PDR0_MAX_PODF_OFFSET);
+ return clk_get_rate(clk->parent) / (max_pdf + 1);
+}
+
+static unsigned long ipg_get_rate(struct clk *clk)
+{
+ unsigned long ipg_pdf;
+
+ ipg_pdf = PDR0(MXC_CCM_PDR0_IPG_PODF_MASK,
+ MXC_CCM_PDR0_IPG_PODF_OFFSET);
+ return clk_get_rate(clk->parent) / (ipg_pdf + 1);
+}
+
+static unsigned long nfc_get_rate(struct clk *clk)
+{
+ unsigned long nfc_pdf;
+
+ nfc_pdf = PDR0(MXC_CCM_PDR0_NFC_PODF_MASK,
+ MXC_CCM_PDR0_NFC_PODF_OFFSET);
+ return clk_get_rate(clk->parent) / (nfc_pdf + 1);
+}
+
+static unsigned long hsp_get_rate(struct clk *clk)
+{
+ unsigned long hsp_pdf;
+
+ hsp_pdf = PDR0(MXC_CCM_PDR0_HSP_PODF_MASK,
+ MXC_CCM_PDR0_HSP_PODF_OFFSET);
+ return clk_get_rate(clk->parent) / (hsp_pdf + 1);
+}
+
+static unsigned long usb_get_rate(struct clk *clk)
+{
+ unsigned long usb_pdf, usb_prepdf;
+
+ usb_pdf = PDR1(MXC_CCM_PDR1_USB_PODF_MASK,
+ MXC_CCM_PDR1_USB_PODF_OFFSET);
+ usb_prepdf = PDR1(MXC_CCM_PDR1_USB_PRDF_MASK,
+ MXC_CCM_PDR1_USB_PRDF_OFFSET);
+ return clk_get_rate(clk->parent) / (usb_prepdf + 1) / (usb_pdf + 1);
+}
+
+static unsigned long csi_get_rate(struct clk *clk)
+{
+ u32 reg, pre, post;
+
+ reg = __raw_readl(MXC_CCM_PDR0);
+ pre = (reg & MXC_CCM_PDR0_CSI_PRDF_MASK) >>
+ MXC_CCM_PDR0_CSI_PRDF_OFFSET;
+ pre++;
+ post = (reg & MXC_CCM_PDR0_CSI_PODF_MASK) >>
+ MXC_CCM_PDR0_CSI_PODF_OFFSET;
+ post++;
+ return clk_get_rate(clk->parent) / (pre * post);
+}
+
+static unsigned long csi_round_rate(struct clk *clk, unsigned long rate)
+{
+ u32 pre, post, parent = clk_get_rate(clk->parent);
+ u32 div = parent / rate;
+
+ if (parent % rate)
+ div++;
+
+ __calc_pre_post_dividers(div, &pre, &post);
+
+ return parent / (pre * post);
+}
+
+static int csi_set_rate(struct clk *clk, unsigned long rate)
+{
+ u32 reg, div, pre, post, parent = clk_get_rate(clk->parent);
+
+ div = parent / rate;
+
+ if ((parent / div) != rate)
+ return -EINVAL;
+
+ __calc_pre_post_dividers(div, &pre, &post);
+
+ /* Set CSI clock divider */
+ reg = __raw_readl(MXC_CCM_PDR0) &
+ ~(MXC_CCM_PDR0_CSI_PODF_MASK | MXC_CCM_PDR0_CSI_PRDF_MASK);
+ reg |= (post - 1) << MXC_CCM_PDR0_CSI_PODF_OFFSET;
+ reg |= (pre - 1) << MXC_CCM_PDR0_CSI_PRDF_OFFSET;
+ __raw_writel(reg, MXC_CCM_PDR0);
+
+ return 0;
+}
+
+static unsigned long ssi1_get_rate(struct clk *clk)
+{
+ unsigned long ssi1_pdf, ssi1_prepdf;
+
+ ssi1_pdf = PDR1(MXC_CCM_PDR1_SSI1_PODF_MASK,
+ MXC_CCM_PDR1_SSI1_PODF_OFFSET);
+ ssi1_prepdf = PDR1(MXC_CCM_PDR1_SSI1_PRE_PODF_MASK,
+ MXC_CCM_PDR1_SSI1_PRE_PODF_OFFSET);
+ return clk_get_rate(clk->parent) / (ssi1_prepdf + 1) / (ssi1_pdf + 1);
+}
+
+static unsigned long ssi2_get_rate(struct clk *clk)
+{
+ unsigned long ssi2_pdf, ssi2_prepdf;
+
+ ssi2_pdf = PDR1(MXC_CCM_PDR1_SSI2_PODF_MASK,
+ MXC_CCM_PDR1_SSI2_PODF_OFFSET);
+ ssi2_prepdf = PDR1(MXC_CCM_PDR1_SSI2_PRE_PODF_MASK,
+ MXC_CCM_PDR1_SSI2_PRE_PODF_OFFSET);
+ return clk_get_rate(clk->parent) / (ssi2_prepdf + 1) / (ssi2_pdf + 1);
+}
+
+static unsigned long firi_get_rate(struct clk *clk)
+{
+ unsigned long firi_pdf, firi_prepdf;
+
+ firi_pdf = PDR1(MXC_CCM_PDR1_FIRI_PODF_MASK,
+ MXC_CCM_PDR1_FIRI_PODF_OFFSET);
+ firi_prepdf = PDR1(MXC_CCM_PDR1_FIRI_PRE_PODF_MASK,
+ MXC_CCM_PDR1_FIRI_PRE_PODF_OFFSET);
+ return clk_get_rate(clk->parent) / (firi_prepdf + 1) / (firi_pdf + 1);
+}
+
+static unsigned long firi_round_rate(struct clk *clk, unsigned long rate)
+{
+ u32 pre, post;
+ u32 parent = clk_get_rate(clk->parent);
+ u32 div = parent / rate;
+
+ if (parent % rate)
+ div++;
+
+ __calc_pre_post_dividers(div, &pre, &post);
+
+ return parent / (pre * post);
+
+}
+
+static int firi_set_rate(struct clk *clk, unsigned long rate)
+{
+ u32 reg, div, pre, post, parent = clk_get_rate(clk->parent);
+
+ div = parent / rate;
+
+ if ((parent / div) != rate)
+ return -EINVAL;
+
+ __calc_pre_post_dividers(div, &pre, &post);
+
+ /* Set FIRI clock divider */
+ reg = __raw_readl(MXC_CCM_PDR1) &
+ ~(MXC_CCM_PDR1_FIRI_PODF_MASK | MXC_CCM_PDR1_FIRI_PRE_PODF_MASK);
+ reg |= (pre - 1) << MXC_CCM_PDR1_FIRI_PRE_PODF_OFFSET;
+ reg |= (post - 1) << MXC_CCM_PDR1_FIRI_PODF_OFFSET;
+ __raw_writel(reg, MXC_CCM_PDR1);
+
+ return 0;
+}
+
+static unsigned long mbx_get_rate(struct clk *clk)
+{
+ return clk_get_rate(clk->parent) / 2;
+}
+
+static unsigned long mstick1_get_rate(struct clk *clk)
+{
+ unsigned long msti_pdf;
+
+ msti_pdf = PDR2(MXC_CCM_PDR2_MST1_PDF_MASK,
+ MXC_CCM_PDR2_MST1_PDF_OFFSET);
+ return clk_get_rate(clk->parent) / (msti_pdf + 1);
+}
+
+static unsigned long mstick2_get_rate(struct clk *clk)
+{
+ unsigned long msti_pdf;
+
+ msti_pdf = PDR2(MXC_CCM_PDR2_MST2_PDF_MASK,
+ MXC_CCM_PDR2_MST2_PDF_OFFSET);
+ return clk_get_rate(clk->parent) / (msti_pdf + 1);
+}
+
+static unsigned long ckih_rate;
+
+static unsigned long clk_ckih_get_rate(struct clk *clk)
+{
+ return ckih_rate;
+}
+
+static unsigned long clk_ckil_get_rate(struct clk *clk)
+{
+ return CKIL_CLK_FREQ;
+}
+
+static struct clk ckih_clk = {
+ .get_rate = clk_ckih_get_rate,
+};
+
+static struct clk mcu_pll_clk = {
+ .parent = &ckih_clk,
+ .get_rate = mcu_pll_get_rate,
+};
+
+static struct clk mcu_main_clk = {
+ .parent = &mcu_pll_clk,
+ .get_rate = mcu_main_get_rate,
+};
+
+static struct clk serial_pll_clk = {
+ .parent = &ckih_clk,
+ .get_rate = serial_pll_get_rate,
+ .enable = serial_pll_enable,
+ .disable = serial_pll_disable,
+};
+
+static struct clk usb_pll_clk = {
+ .parent = &ckih_clk,
+ .get_rate = usb_pll_get_rate,
+ .enable = usb_pll_enable,
+ .disable = usb_pll_disable,
+};
+
+static struct clk ahb_clk = {
+ .parent = &mcu_main_clk,
+ .get_rate = ahb_get_rate,
+};
+
+#define DEFINE_CLOCK(name, i, er, es, gr, s, p) \
+ static struct clk name = { \
+ .id = i, \
+ .enable_reg = er, \
+ .enable_shift = es, \
+ .get_rate = gr, \
+ .enable = cgr_enable, \
+ .disable = cgr_disable, \
+ .secondary = s, \
+ .parent = p, \
+ }
+
+#define DEFINE_CLOCK1(name, i, er, es, getsetround, s, p) \
+ static struct clk name = { \
+ .id = i, \
+ .enable_reg = er, \
+ .enable_shift = es, \
+ .get_rate = getsetround##_get_rate, \
+ .set_rate = getsetround##_set_rate, \
+ .round_rate = getsetround##_round_rate, \
+ .enable = cgr_enable, \
+ .disable = cgr_disable, \
+ .secondary = s, \
+ .parent = p, \
+ }
+
+DEFINE_CLOCK(perclk_clk, 0, NULL, 0, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(ckil_clk, 0, NULL, 0, clk_ckil_get_rate, NULL, NULL);
+
+DEFINE_CLOCK(sdhc1_clk, 0, MXC_CCM_CGR0, 0, NULL, NULL, &perclk_clk);
+DEFINE_CLOCK(sdhc2_clk, 1, MXC_CCM_CGR0, 2, NULL, NULL, &perclk_clk);
+DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CGR0, 4, NULL, NULL, &perclk_clk);
+DEFINE_CLOCK(epit1_clk, 0, MXC_CCM_CGR0, 6, NULL, NULL, &perclk_clk);
+DEFINE_CLOCK(epit2_clk, 1, MXC_CCM_CGR0, 8, NULL, NULL, &perclk_clk);
+DEFINE_CLOCK(iim_clk, 0, MXC_CCM_CGR0, 10, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(ata_clk, 0, MXC_CCM_CGR0, 12, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(sdma_clk1, 0, MXC_CCM_CGR0, 14, NULL, NULL, &ahb_clk);
+DEFINE_CLOCK(cspi3_clk, 2, MXC_CCM_CGR0, 16, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(rng_clk, 0, MXC_CCM_CGR0, 18, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CGR0, 20, NULL, NULL, &perclk_clk);
+DEFINE_CLOCK(uart2_clk, 1, MXC_CCM_CGR0, 22, NULL, NULL, &perclk_clk);
+DEFINE_CLOCK(ssi1_clk, 0, MXC_CCM_CGR0, 24, ssi1_get_rate, NULL, &serial_pll_clk);
+DEFINE_CLOCK(i2c1_clk, 0, MXC_CCM_CGR0, 26, NULL, NULL, &perclk_clk);
+DEFINE_CLOCK(i2c2_clk, 1, MXC_CCM_CGR0, 28, NULL, NULL, &perclk_clk);
+DEFINE_CLOCK(i2c3_clk, 2, MXC_CCM_CGR0, 30, NULL, NULL, &perclk_clk);
+
+DEFINE_CLOCK(mpeg4_clk, 0, MXC_CCM_CGR1, 0, NULL, NULL, &ahb_clk);
+DEFINE_CLOCK(mstick1_clk, 0, MXC_CCM_CGR1, 2, mstick1_get_rate, NULL, &usb_pll_clk);
+DEFINE_CLOCK(mstick2_clk, 1, MXC_CCM_CGR1, 4, mstick2_get_rate, NULL, &usb_pll_clk);
+DEFINE_CLOCK1(csi_clk, 0, MXC_CCM_CGR1, 6, csi, NULL, &serial_pll_clk);
+DEFINE_CLOCK(rtc_clk, 0, MXC_CCM_CGR1, 8, NULL, NULL, &ckil_clk);
+DEFINE_CLOCK(wdog_clk, 0, MXC_CCM_CGR1, 10, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(pwm_clk, 0, MXC_CCM_CGR1, 12, NULL, NULL, &perclk_clk);
+DEFINE_CLOCK(usb_clk2, 0, MXC_CCM_CGR1, 18, usb_get_rate, NULL, &ahb_clk);
+DEFINE_CLOCK(kpp_clk, 0, MXC_CCM_CGR1, 20, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(ipu_clk, 0, MXC_CCM_CGR1, 22, hsp_get_rate, NULL, &mcu_main_clk);
+DEFINE_CLOCK(uart3_clk, 2, MXC_CCM_CGR1, 24, NULL, NULL, &perclk_clk);
+DEFINE_CLOCK(uart4_clk, 3, MXC_CCM_CGR1, 26, NULL, NULL, &perclk_clk);
+DEFINE_CLOCK(uart5_clk, 4, MXC_CCM_CGR1, 28, NULL, NULL, &perclk_clk);
+DEFINE_CLOCK(owire_clk, 0, MXC_CCM_CGR1, 30, NULL, NULL, &perclk_clk);
+
+DEFINE_CLOCK(ssi2_clk, 1, MXC_CCM_CGR2, 0, ssi2_get_rate, NULL, &serial_pll_clk);
+DEFINE_CLOCK(cspi1_clk, 0, MXC_CCM_CGR2, 2, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(cspi2_clk, 1, MXC_CCM_CGR2, 4, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(mbx_clk, 0, MXC_CCM_CGR2, 6, mbx_get_rate, NULL, &ahb_clk);
+DEFINE_CLOCK(emi_clk, 0, MXC_CCM_CGR2, 8, NULL, NULL, &ahb_clk);
+DEFINE_CLOCK(rtic_clk, 0, MXC_CCM_CGR2, 10, NULL, NULL, &ahb_clk);
+DEFINE_CLOCK1(firi_clk, 0, MXC_CCM_CGR2, 12, firi, NULL, &usb_pll_clk);
+
+DEFINE_CLOCK(sdma_clk2, 0, NULL, 0, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(usb_clk1, 0, NULL, 0, usb_get_rate, NULL, &usb_pll_clk);
+DEFINE_CLOCK(nfc_clk, 0, NULL, 0, nfc_get_rate, NULL, &ahb_clk);
+DEFINE_CLOCK(scc_clk, 0, NULL, 0, NULL, NULL, &ipg_clk);
+DEFINE_CLOCK(ipg_clk, 0, NULL, 0, ipg_get_rate, NULL, &ahb_clk);
+
+#define _REGISTER_CLOCK(d, n, c) \
+ { \
+ .dev_id = d, \
+ .con_id = n, \
+ .clk = &c, \
+ },
+
+static struct clk_lookup lookups[] = {
+ _REGISTER_CLOCK(NULL, "emi", emi_clk)
+ _REGISTER_CLOCK("imx31-cspi.0", NULL, cspi1_clk)
+ _REGISTER_CLOCK("imx31-cspi.1", NULL, cspi2_clk)
+ _REGISTER_CLOCK("imx31-cspi.2", NULL, cspi3_clk)
+ _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
+ _REGISTER_CLOCK(NULL, "pwm", pwm_clk)
+ _REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk)
+ _REGISTER_CLOCK(NULL, "rtc", rtc_clk)
+ _REGISTER_CLOCK(NULL, "epit", epit1_clk)
+ _REGISTER_CLOCK(NULL, "epit", epit2_clk)
+ _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
+ _REGISTER_CLOCK("ipu-core", NULL, ipu_clk)
+ _REGISTER_CLOCK("mx3_sdc_fb", NULL, ipu_clk)
+ _REGISTER_CLOCK(NULL, "kpp", kpp_clk)
+ _REGISTER_CLOCK("mxc-ehci.0", "usb", usb_clk1)
+ _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", usb_clk2)
+ _REGISTER_CLOCK("mxc-ehci.1", "usb", usb_clk1)
+ _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", usb_clk2)
+ _REGISTER_CLOCK("mxc-ehci.2", "usb", usb_clk1)
+ _REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_clk2)
+ _REGISTER_CLOCK("fsl-usb2-udc", "usb", usb_clk1)
+ _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usb_clk2)
+ _REGISTER_CLOCK("mx3-camera.0", NULL, csi_clk)
+ _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
+ _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
+ _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
+ _REGISTER_CLOCK("imx-uart.3", NULL, uart4_clk)
+ _REGISTER_CLOCK("imx-uart.4", NULL, uart5_clk)
+ _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
+ _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
+ _REGISTER_CLOCK("imx-i2c.2", NULL, i2c3_clk)
+ _REGISTER_CLOCK("mxc_w1.0", NULL, owire_clk)
+ _REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc1_clk)
+ _REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc2_clk)
+ _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
+ _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
+ _REGISTER_CLOCK(NULL, "firi", firi_clk)
+ _REGISTER_CLOCK(NULL, "ata", ata_clk)
+ _REGISTER_CLOCK(NULL, "rtic", rtic_clk)
+ _REGISTER_CLOCK(NULL, "rng", rng_clk)
+ _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk1)
+ _REGISTER_CLOCK(NULL, "sdma_ipg", sdma_clk2)
+ _REGISTER_CLOCK(NULL, "mstick", mstick1_clk)
+ _REGISTER_CLOCK(NULL, "mstick", mstick2_clk)
+ _REGISTER_CLOCK(NULL, "scc", scc_clk)
+ _REGISTER_CLOCK(NULL, "iim", iim_clk)
+ _REGISTER_CLOCK(NULL, "mpeg4", mpeg4_clk)
+ _REGISTER_CLOCK(NULL, "mbx", mbx_clk)
+};
+
+int __init mx31_clocks_init(unsigned long fref)
+{
+ u32 reg;
+
+ ckih_rate = fref;
+
+ clkdev_add_table(lookups, ARRAY_SIZE(lookups));
+
+ /* change the csi_clk parent if necessary */
+ reg = __raw_readl(MXC_CCM_CCMR);
+ if (!(reg & MXC_CCM_CCMR_CSCS))
+ if (clk_set_parent(&csi_clk, &usb_pll_clk))
+ pr_err("%s: error changing csi_clk parent\n", __func__);
+
+
+ /* Turn off all possible clocks */
+ __raw_writel((3 << 4), MXC_CCM_CGR0);
+ __raw_writel(0, MXC_CCM_CGR1);
+ __raw_writel((3 << 8) | (3 << 14) | (3 << 16)|
+ 1 << 27 | 1 << 28, /* Bit 27 and 28 are not defined for
+ MX32, but still required to be set */
+ MXC_CCM_CGR2);
+
+ /*
+ * Before turning off usb_pll make sure ipg_per_clk is generated
+ * by ipg_clk and not usb_pll.
+ */
+ __raw_writel(__raw_readl(MXC_CCM_CCMR) | (1 << 24), MXC_CCM_CCMR);
+
+ usb_pll_disable(&usb_pll_clk);
+
+ pr_info("Clock input source is %ld\n", clk_get_rate(&ckih_clk));
+
+ clk_enable(&gpt_clk);
+ clk_enable(&emi_clk);
+ clk_enable(&iim_clk);
+
+ clk_enable(&serial_pll_clk);
+
+ mx31_read_cpu_rev();
+
+ if (mx31_revision() >= IMX_CHIP_REVISION_2_0) {
+ reg = __raw_readl(MXC_CCM_PMCR1);
+ /* No PLL restart on DVFS switch; enable auto EMI handshake */
+ reg |= MXC_CCM_PMCR1_PLLRDIS | MXC_CCM_PMCR1_EMIRQ_EN;
+ __raw_writel(reg, MXC_CCM_PMCR1);
+ }
+
+ mxc_timer_init(&ipg_clk, MX31_IO_ADDRESS(MX31_GPT1_BASE_ADDR),
+ MX31_INT_GPT);
+
+ return 0;
+}
diff --git a/arch/arm/mach-imx/clock-imx35.c b/arch/arm/mach-imx/clock-imx35.c
new file mode 100644
index 0000000..5a4cc1e
--- /dev/null
+++ b/arch/arm/mach-imx/clock-imx35.c
@@ -0,0 +1,549 @@
+/*
+ * Copyright (C) 2009 by Sascha Hauer, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/list.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/clkdev.h>
+
+#include <mach/clock.h>
+#include <mach/hardware.h>
+#include <mach/common.h>
+
+#define CCM_BASE MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR)
+
+#define CCM_CCMR 0x00
+#define CCM_PDR0 0x04
+#define CCM_PDR1 0x08
+#define CCM_PDR2 0x0C
+#define CCM_PDR3 0x10
+#define CCM_PDR4 0x14
+#define CCM_RCSR 0x18
+#define CCM_MPCTL 0x1C
+#define CCM_PPCTL 0x20
+#define CCM_ACMR 0x24
+#define CCM_COSR 0x28
+#define CCM_CGR0 0x2C
+#define CCM_CGR1 0x30
+#define CCM_CGR2 0x34
+#define CCM_CGR3 0x38
+
+#ifdef HAVE_SET_RATE_SUPPORT
+static void calc_dividers(u32 div, u32 *pre, u32 *post, u32 maxpost)
+{
+ u32 min_pre, temp_pre, old_err, err;
+
+ min_pre = (div - 1) / maxpost + 1;
+ old_err = 8;
+
+ for (temp_pre = 8; temp_pre >= min_pre; temp_pre--) {
+ if (div > (temp_pre * maxpost))
+ break;
+
+ if (div < (temp_pre * temp_pre))
+ continue;
+
+ err = div % temp_pre;
+
+ if (err == 0) {
+ *pre = temp_pre;
+ break;
+ }
+
+ err = temp_pre - err;
+
+ if (err < old_err) {
+ old_err = err;
+ *pre = temp_pre;
+ }
+ }
+
+ *post = (div + *pre - 1) / *pre;
+}
+
+/* get the best values for a 3-bit divider combined with a 6-bit divider */
+static void calc_dividers_3_6(u32 div, u32 *pre, u32 *post)
+{
+ if (div >= 512) {
+ *pre = 8;
+ *post = 64;
+ } else if (div >= 64) {
+ calc_dividers(div, pre, post, 64);
+ } else if (div <= 8) {
+ *pre = div;
+ *post = 1;
+ } else {
+ *pre = 1;
+ *post = div;
+ }
+}
+
+/* get the best values for two cascaded 3-bit dividers */
+static void calc_dividers_3_3(u32 div, u32 *pre, u32 *post)
+{
+ if (div >= 64) {
+ *pre = *post = 8;
+ } else if (div > 8) {
+ calc_dividers(div, pre, post, 8);
+ } else {
+ *pre = 1;
+ *post = div;
+ }
+}
+#endif
+
+static unsigned long get_rate_mpll(void)
+{
+ ulong mpctl = __raw_readl(CCM_BASE + CCM_MPCTL);
+
+ return mxc_decode_pll(mpctl, 24000000);
+}
+
+static unsigned long get_rate_ppll(void)
+{
+ ulong ppctl = __raw_readl(CCM_BASE + CCM_PPCTL);
+
+ return mxc_decode_pll(ppctl, 24000000);
+}
+
+struct arm_ahb_div {
+ unsigned char arm, ahb, sel;
+};
+
+static struct arm_ahb_div clk_consumer[] = {
+ { .arm = 1, .ahb = 4, .sel = 0},
+ { .arm = 1, .ahb = 3, .sel = 1},
+ { .arm = 2, .ahb = 2, .sel = 0},
+ { .arm = 0, .ahb = 0, .sel = 0},
+ { .arm = 0, .ahb = 0, .sel = 0},
+ { .arm = 0, .ahb = 0, .sel = 0},
+ { .arm = 4, .ahb = 1, .sel = 0},
+ { .arm = 1, .ahb = 5, .sel = 0},
+ { .arm = 1, .ahb = 8, .sel = 0},
+ { .arm = 1, .ahb = 6, .sel = 1},
+ { .arm = 2, .ahb = 4, .sel = 0},
+ { .arm = 0, .ahb = 0, .sel = 0},
+ { .arm = 0, .ahb = 0, .sel = 0},
+ { .arm = 0, .ahb = 0, .sel = 0},
+ { .arm = 4, .ahb = 2, .sel = 0},
+ { .arm = 0, .ahb = 0, .sel = 0},
+};
+
+static unsigned long get_rate_arm(void)
+{
+ unsigned long pdr0 = __raw_readl(CCM_BASE + CCM_PDR0);
+ struct arm_ahb_div *aad;
+ unsigned long fref = get_rate_mpll();
+
+ aad = &clk_consumer[(pdr0 >> 16) & 0xf];
+ if (aad->sel)
+ fref = fref * 3 / 4;
+
+ return fref / aad->arm;
+}
+
+static unsigned long get_rate_ahb(struct clk *clk)
+{
+ unsigned long pdr0 = __raw_readl(CCM_BASE + CCM_PDR0);
+ struct arm_ahb_div *aad;
+ unsigned long fref = get_rate_arm();
+
+ aad = &clk_consumer[(pdr0 >> 16) & 0xf];
+
+ return fref / aad->ahb;
+}
+
+static unsigned long get_rate_ipg(struct clk *clk)
+{
+ return get_rate_ahb(NULL) >> 1;
+}
+
+static unsigned long get_rate_uart(struct clk *clk)
+{
+ unsigned long pdr3 = __raw_readl(CCM_BASE + CCM_PDR3);
+ unsigned long pdr4 = __raw_readl(CCM_BASE + CCM_PDR4);
+ unsigned long div = ((pdr4 >> 10) & 0x3f) + 1;
+
+ if (pdr3 & (1 << 14))
+ return get_rate_arm() / div;
+ else
+ return get_rate_ppll() / div;
+}
+
+static unsigned long get_rate_sdhc(struct clk *clk)
+{
+ unsigned long pdr3 = __raw_readl(CCM_BASE + CCM_PDR3);
+ unsigned long div, rate;
+
+ if (pdr3 & (1 << 6))
+ rate = get_rate_arm();
+ else
+ rate = get_rate_ppll();
+
+ switch (clk->id) {
+ default:
+ case 0:
+ div = pdr3 & 0x3f;
+ break;
+ case 1:
+ div = (pdr3 >> 8) & 0x3f;
+ break;
+ case 2:
+ div = (pdr3 >> 16) & 0x3f;
+ break;
+ }
+
+ return rate / (div + 1);
+}
+
+static unsigned long get_rate_mshc(struct clk *clk)
+{
+ unsigned long pdr1 = __raw_readl(CCM_BASE + CCM_PDR1);
+ unsigned long div1, div2, rate;
+
+ if (pdr1 & (1 << 7))
+ rate = get_rate_arm();
+ else
+ rate = get_rate_ppll();
+
+ div1 = (pdr1 >> 29) & 0x7;
+ div2 = (pdr1 >> 22) & 0x3f;
+
+ return rate / ((div1 + 1) * (div2 + 1));
+}
+
+static unsigned long get_rate_ssi(struct clk *clk)
+{
+ unsigned long pdr2 = __raw_readl(CCM_BASE + CCM_PDR2);
+ unsigned long div1, div2, rate;
+
+ if (pdr2 & (1 << 6))
+ rate = get_rate_arm();
+ else
+ rate = get_rate_ppll();
+
+ switch (clk->id) {
+ default:
+ case 0:
+ div1 = pdr2 & 0x3f;
+ div2 = (pdr2 >> 24) & 0x7;
+ break;
+ case 1:
+ div1 = (pdr2 >> 8) & 0x3f;
+ div2 = (pdr2 >> 27) & 0x7;
+ break;
+ }
+
+ return rate / ((div1 + 1) * (div2 + 1));
+}
+
+static unsigned long get_rate_csi(struct clk *clk)
+{
+ unsigned long pdr2 = __raw_readl(CCM_BASE + CCM_PDR2);
+ unsigned long rate;
+
+ if (pdr2 & (1 << 7))
+ rate = get_rate_arm();
+ else
+ rate = get_rate_ppll();
+
+ return rate / (((pdr2 >> 16) & 0x3f) + 1);
+}
+
+static unsigned long get_rate_otg(struct clk *clk)
+{
+ unsigned long pdr4 = __raw_readl(CCM_BASE + CCM_PDR4);
+ unsigned long rate;
+
+ if (pdr4 & (1 << 9))
+ rate = get_rate_arm();
+ else
+ rate = get_rate_ppll();
+
+ return rate / (((pdr4 >> 22) & 0x3f) + 1);
+}
+
+static unsigned long get_rate_ipg_per(struct clk *clk)
+{
+ unsigned long pdr0 = __raw_readl(CCM_BASE + CCM_PDR0);
+ unsigned long pdr4 = __raw_readl(CCM_BASE + CCM_PDR4);
+ unsigned long div;
+
+ if (pdr0 & (1 << 26)) {
+ div = (pdr4 >> 16) & 0x3f;
+ return get_rate_arm() / (div + 1);
+ } else {
+ div = (pdr0 >> 12) & 0x7;
+ return get_rate_ahb(NULL) / (div + 1);
+ }
+}
+
+static unsigned long get_rate_hsp(struct clk *clk)
+{
+ unsigned long hsp_podf = (__raw_readl(CCM_BASE + CCM_PDR0) >> 20) & 0x03;
+ unsigned long fref = get_rate_mpll();
+
+ if (fref > 400 * 1000 * 1000) {
+ switch (hsp_podf) {
+ case 0:
+ return fref >> 2;
+ case 1:
+ return fref >> 3;
+ case 2:
+ return fref / 3;
+ }
+ } else {
+ switch (hsp_podf) {
+ case 0:
+ case 2:
+ return fref / 3;
+ case 1:
+ return fref / 6;
+ }
+ }
+
+ return 0;
+}
+
+static int clk_cgr_enable(struct clk *clk)
+{
+ u32 reg;
+
+ reg = __raw_readl(clk->enable_reg);
+ reg |= 3 << clk->enable_shift;
+ __raw_writel(reg, clk->enable_reg);
+
+ return 0;
+}
+
+static void clk_cgr_disable(struct clk *clk)
+{
+ u32 reg;
+
+ reg = __raw_readl(clk->enable_reg);
+ reg &= ~(3 << clk->enable_shift);
+ __raw_writel(reg, clk->enable_reg);
+}
+
+#define DEFINE_CLOCK(name, i, er, es, gr, sr) \
+ static struct clk name = { \
+ .id = i, \
+ .enable_reg = CCM_BASE + er, \
+ .enable_shift = es, \
+ .get_rate = gr, \
+ .set_rate = sr, \
+ .enable = clk_cgr_enable, \
+ .disable = clk_cgr_disable, \
+ }
+
+DEFINE_CLOCK(asrc_clk, 0, CCM_CGR0, 0, NULL, NULL);
+DEFINE_CLOCK(ata_clk, 0, CCM_CGR0, 2, get_rate_ipg, NULL);
+/* DEFINE_CLOCK(audmux_clk, 0, CCM_CGR0, 4, NULL, NULL); */
+DEFINE_CLOCK(can1_clk, 0, CCM_CGR0, 6, get_rate_ipg, NULL);
+DEFINE_CLOCK(can2_clk, 1, CCM_CGR0, 8, get_rate_ipg, NULL);
+DEFINE_CLOCK(cspi1_clk, 0, CCM_CGR0, 10, get_rate_ipg, NULL);
+DEFINE_CLOCK(cspi2_clk, 1, CCM_CGR0, 12, get_rate_ipg, NULL);
+DEFINE_CLOCK(ect_clk, 0, CCM_CGR0, 14, get_rate_ipg, NULL);
+DEFINE_CLOCK(edio_clk, 0, CCM_CGR0, 16, NULL, NULL);
+DEFINE_CLOCK(emi_clk, 0, CCM_CGR0, 18, get_rate_ipg, NULL);
+DEFINE_CLOCK(epit1_clk, 0, CCM_CGR0, 20, get_rate_ipg, NULL);
+DEFINE_CLOCK(epit2_clk, 1, CCM_CGR0, 22, get_rate_ipg, NULL);
+DEFINE_CLOCK(esai_clk, 0, CCM_CGR0, 24, NULL, NULL);
+DEFINE_CLOCK(esdhc1_clk, 0, CCM_CGR0, 26, get_rate_sdhc, NULL);
+DEFINE_CLOCK(esdhc2_clk, 1, CCM_CGR0, 28, get_rate_sdhc, NULL);
+DEFINE_CLOCK(esdhc3_clk, 2, CCM_CGR0, 30, get_rate_sdhc, NULL);
+
+DEFINE_CLOCK(fec_clk, 0, CCM_CGR1, 0, get_rate_ipg, NULL);
+DEFINE_CLOCK(gpio1_clk, 0, CCM_CGR1, 2, NULL, NULL);
+DEFINE_CLOCK(gpio2_clk, 1, CCM_CGR1, 4, NULL, NULL);
+DEFINE_CLOCK(gpio3_clk, 2, CCM_CGR1, 6, NULL, NULL);
+DEFINE_CLOCK(gpt_clk, 0, CCM_CGR1, 8, get_rate_ipg, NULL);
+DEFINE_CLOCK(i2c1_clk, 0, CCM_CGR1, 10, get_rate_ipg_per, NULL);
+DEFINE_CLOCK(i2c2_clk, 1, CCM_CGR1, 12, get_rate_ipg_per, NULL);
+DEFINE_CLOCK(i2c3_clk, 2, CCM_CGR1, 14, get_rate_ipg_per, NULL);
+DEFINE_CLOCK(iomuxc_clk, 0, CCM_CGR1, 16, NULL, NULL);
+DEFINE_CLOCK(ipu_clk, 0, CCM_CGR1, 18, get_rate_hsp, NULL);
+DEFINE_CLOCK(kpp_clk, 0, CCM_CGR1, 20, get_rate_ipg, NULL);
+DEFINE_CLOCK(mlb_clk, 0, CCM_CGR1, 22, get_rate_ahb, NULL);
+DEFINE_CLOCK(mshc_clk, 0, CCM_CGR1, 24, get_rate_mshc, NULL);
+DEFINE_CLOCK(owire_clk, 0, CCM_CGR1, 26, get_rate_ipg_per, NULL);
+DEFINE_CLOCK(pwm_clk, 0, CCM_CGR1, 28, get_rate_ipg_per, NULL);
+DEFINE_CLOCK(rngc_clk, 0, CCM_CGR1, 30, get_rate_ipg, NULL);
+
+DEFINE_CLOCK(rtc_clk, 0, CCM_CGR2, 0, get_rate_ipg, NULL);
+DEFINE_CLOCK(rtic_clk, 0, CCM_CGR2, 2, get_rate_ahb, NULL);
+DEFINE_CLOCK(scc_clk, 0, CCM_CGR2, 4, get_rate_ipg, NULL);
+DEFINE_CLOCK(sdma_clk, 0, CCM_CGR2, 6, NULL, NULL);
+DEFINE_CLOCK(spba_clk, 0, CCM_CGR2, 8, get_rate_ipg, NULL);
+DEFINE_CLOCK(spdif_clk, 0, CCM_CGR2, 10, NULL, NULL);
+DEFINE_CLOCK(ssi1_clk, 0, CCM_CGR2, 12, get_rate_ssi, NULL);
+DEFINE_CLOCK(ssi2_clk, 1, CCM_CGR2, 14, get_rate_ssi, NULL);
+DEFINE_CLOCK(uart1_clk, 0, CCM_CGR2, 16, get_rate_uart, NULL);
+DEFINE_CLOCK(uart2_clk, 1, CCM_CGR2, 18, get_rate_uart, NULL);
+DEFINE_CLOCK(uart3_clk, 2, CCM_CGR2, 20, get_rate_uart, NULL);
+DEFINE_CLOCK(usbotg_clk, 0, CCM_CGR2, 22, get_rate_otg, NULL);
+DEFINE_CLOCK(wdog_clk, 0, CCM_CGR2, 24, NULL, NULL);
+DEFINE_CLOCK(max_clk, 0, CCM_CGR2, 26, NULL, NULL);
+DEFINE_CLOCK(audmux_clk, 0, CCM_CGR2, 30, NULL, NULL);
+
+DEFINE_CLOCK(csi_clk, 0, CCM_CGR3, 0, get_rate_csi, NULL);
+DEFINE_CLOCK(iim_clk, 0, CCM_CGR3, 2, NULL, NULL);
+DEFINE_CLOCK(gpu2d_clk, 0, CCM_CGR3, 4, NULL, NULL);
+
+DEFINE_CLOCK(usbahb_clk, 0, 0, 0, get_rate_ahb, NULL);
+
+static int clk_dummy_enable(struct clk *clk)
+{
+ return 0;
+}
+
+static void clk_dummy_disable(struct clk *clk)
+{
+}
+
+static unsigned long get_rate_nfc(struct clk *clk)
+{
+ unsigned long div1;
+
+ div1 = (__raw_readl(CCM_BASE + CCM_PDR4) >> 28) + 1;
+
+ return get_rate_ahb(NULL) / div1;
+}
+
+/* NAND Controller: It seems it can't be disabled */
+static struct clk nfc_clk = {
+ .id = 0,
+ .enable_reg = 0,
+ .enable_shift = 0,
+ .get_rate = get_rate_nfc,
+ .set_rate = NULL, /* set_rate_nfc, */
+ .enable = clk_dummy_enable,
+ .disable = clk_dummy_disable
+};
+
+#define _REGISTER_CLOCK(d, n, c) \
+ { \
+ .dev_id = d, \
+ .con_id = n, \
+ .clk = &c, \
+ },
+
+static struct clk_lookup lookups[] = {
+ _REGISTER_CLOCK(NULL, "asrc", asrc_clk)
+ _REGISTER_CLOCK(NULL, "ata", ata_clk)
+ _REGISTER_CLOCK("flexcan.0", NULL, can1_clk)
+ _REGISTER_CLOCK("flexcan.1", NULL, can2_clk)
+ _REGISTER_CLOCK("imx35-cspi.0", NULL, cspi1_clk)
+ _REGISTER_CLOCK("imx35-cspi.1", NULL, cspi2_clk)
+ _REGISTER_CLOCK(NULL, "ect", ect_clk)
+ _REGISTER_CLOCK(NULL, "edio", edio_clk)
+ _REGISTER_CLOCK(NULL, "emi", emi_clk)
+ _REGISTER_CLOCK("imx-epit.0", NULL, epit1_clk)
+ _REGISTER_CLOCK("imx-epit.1", NULL, epit2_clk)
+ _REGISTER_CLOCK(NULL, "esai", esai_clk)
+ _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk)
+ _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk)
+ _REGISTER_CLOCK("sdhci-esdhc-imx.2", NULL, esdhc3_clk)
+ _REGISTER_CLOCK("fec.0", NULL, fec_clk)
+ _REGISTER_CLOCK(NULL, "gpio", gpio1_clk)
+ _REGISTER_CLOCK(NULL, "gpio", gpio2_clk)
+ _REGISTER_CLOCK(NULL, "gpio", gpio3_clk)
+ _REGISTER_CLOCK("gpt.0", NULL, gpt_clk)
+ _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
+ _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
+ _REGISTER_CLOCK("imx-i2c.2", NULL, i2c3_clk)
+ _REGISTER_CLOCK(NULL, "iomuxc", iomuxc_clk)
+ _REGISTER_CLOCK("ipu-core", NULL, ipu_clk)
+ _REGISTER_CLOCK("mx3_sdc_fb", NULL, ipu_clk)
+ _REGISTER_CLOCK(NULL, "kpp", kpp_clk)
+ _REGISTER_CLOCK(NULL, "mlb", mlb_clk)
+ _REGISTER_CLOCK(NULL, "mshc", mshc_clk)
+ _REGISTER_CLOCK("mxc_w1", NULL, owire_clk)
+ _REGISTER_CLOCK(NULL, "pwm", pwm_clk)
+ _REGISTER_CLOCK(NULL, "rngc", rngc_clk)
+ _REGISTER_CLOCK(NULL, "rtc", rtc_clk)
+ _REGISTER_CLOCK(NULL, "rtic", rtic_clk)
+ _REGISTER_CLOCK(NULL, "scc", scc_clk)
+ _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk)
+ _REGISTER_CLOCK(NULL, "spba", spba_clk)
+ _REGISTER_CLOCK(NULL, "spdif", spdif_clk)
+ _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
+ _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
+ _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
+ _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
+ _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
+ _REGISTER_CLOCK("mxc-ehci.0", "usb", usbotg_clk)
+ _REGISTER_CLOCK("mxc-ehci.1", "usb", usbotg_clk)
+ _REGISTER_CLOCK("mxc-ehci.2", "usb", usbotg_clk)
+ _REGISTER_CLOCK("fsl-usb2-udc", "usb", usbotg_clk)
+ _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usbahb_clk)
+ _REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk)
+ _REGISTER_CLOCK(NULL, "max", max_clk)
+ _REGISTER_CLOCK(NULL, "audmux", audmux_clk)
+ _REGISTER_CLOCK(NULL, "csi", csi_clk)
+ _REGISTER_CLOCK(NULL, "iim", iim_clk)
+ _REGISTER_CLOCK(NULL, "gpu2d", gpu2d_clk)
+ _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
+};
+
+int __init mx35_clocks_init()
+{
+ unsigned int cgr2 = 3 << 26, cgr3 = 0;
+
+#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC)
+ cgr2 |= 3 << 16;
+#endif
+
+ clkdev_add_table(lookups, ARRAY_SIZE(lookups));
+
+ /* Turn off all clocks except the ones we need to survive, namely:
+ * EMI, GPIO1/2/3, GPT, IOMUX, MAX and eventually uart
+ */
+ __raw_writel((3 << 18), CCM_BASE + CCM_CGR0);
+ __raw_writel((3 << 2) | (3 << 4) | (3 << 6) | (3 << 8) | (3 << 16),
+ CCM_BASE + CCM_CGR1);
+
+ /*
+ * Check if we came up in internal boot mode. If yes, we need some
+ * extra clocks turned on, otherwise the MX35 boot ROM code will
+ * hang after a watchdog reset.
+ */
+ if (!(__raw_readl(CCM_BASE + CCM_RCSR) & (3 << 10))) {
+ /* Additionally turn on UART1, SCC, and IIM clocks */
+ cgr2 |= 3 << 16 | 3 << 4;
+ cgr3 |= 3 << 2;
+ }
+
+ __raw_writel(cgr2, CCM_BASE + CCM_CGR2);
+ __raw_writel(cgr3, CCM_BASE + CCM_CGR3);
+
+ clk_enable(&iim_clk);
+ mx35_read_cpu_rev();
+
+#ifdef CONFIG_MXC_USE_EPIT
+ epit_timer_init(&epit1_clk,
+ MX35_IO_ADDRESS(MX35_EPIT1_BASE_ADDR), MX35_INT_EPIT1);
+#else
+ mxc_timer_init(&gpt_clk,
+ MX35_IO_ADDRESS(MX35_GPT1_BASE_ADDR), MX35_INT_GPT);
+#endif
+
+ return 0;
+}
diff --git a/arch/arm/mach-imx/cpu-imx31.c b/arch/arm/mach-imx/cpu-imx31.c
new file mode 100644
index 0000000..a378070
--- /dev/null
+++ b/arch/arm/mach-imx/cpu-imx31.c
@@ -0,0 +1,57 @@
+/*
+ * MX31 CPU type detection
+ *
+ * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/module.h>
+#include <linux/io.h>
+#include <mach/hardware.h>
+#include <mach/iim.h>
+
+unsigned int mx31_cpu_rev;
+EXPORT_SYMBOL(mx31_cpu_rev);
+
+static struct {
+ u8 srev;
+ const char *name;
+ const char *v;
+ unsigned int rev;
+} mx31_cpu_type[] __initdata = {
+ { .srev = 0x00, .name = "i.MX31(L)", .v = "1.0", .rev = IMX_CHIP_REVISION_1_0 },
+ { .srev = 0x10, .name = "i.MX31", .v = "1.1", .rev = IMX_CHIP_REVISION_1_1 },
+ { .srev = 0x11, .name = "i.MX31L", .v = "1.1", .rev = IMX_CHIP_REVISION_1_1 },
+ { .srev = 0x12, .name = "i.MX31", .v = "1.15", .rev = IMX_CHIP_REVISION_1_1 },
+ { .srev = 0x13, .name = "i.MX31L", .v = "1.15", .rev = IMX_CHIP_REVISION_1_1 },
+ { .srev = 0x14, .name = "i.MX31", .v = "1.2", .rev = IMX_CHIP_REVISION_1_2 },
+ { .srev = 0x15, .name = "i.MX31L", .v = "1.2", .rev = IMX_CHIP_REVISION_1_2 },
+ { .srev = 0x28, .name = "i.MX31", .v = "2.0", .rev = IMX_CHIP_REVISION_2_0 },
+ { .srev = 0x29, .name = "i.MX31L", .v = "2.0", .rev = IMX_CHIP_REVISION_2_0 },
+};
+
+void __init mx31_read_cpu_rev(void)
+{
+ u32 i, srev;
+
+ /* read SREV register from IIM module */
+ srev = __raw_readl(MX31_IO_ADDRESS(MX31_IIM_BASE_ADDR + MXC_IIMSREV));
+
+ for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++)
+ if (srev == mx31_cpu_type[i].srev) {
+ printk(KERN_INFO
+ "CPU identified as %s, silicon rev %s\n",
+ mx31_cpu_type[i].name, mx31_cpu_type[i].v);
+
+ mx31_cpu_rev = mx31_cpu_type[i].rev;
+ return;
+ }
+
+ mx31_cpu_rev = IMX_CHIP_REVISION_UNKNOWN;
+
+ printk(KERN_WARNING "Unknown CPU identifier. srev = %02x\n", srev);
+}
diff --git a/arch/arm/mach-imx/cpu-imx35.c b/arch/arm/mach-imx/cpu-imx35.c
new file mode 100644
index 0000000..6637cd8
--- /dev/null
+++ b/arch/arm/mach-imx/cpu-imx35.c
@@ -0,0 +1,44 @@
+/*
+ * MX35 CPU type detection
+ *
+ * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include <linux/module.h>
+#include <linux/io.h>
+#include <mach/hardware.h>
+#include <mach/iim.h>
+
+unsigned int mx35_cpu_rev;
+EXPORT_SYMBOL(mx35_cpu_rev);
+
+void __init mx35_read_cpu_rev(void)
+{
+ u32 rev;
+ char *srev;
+
+ rev = __raw_readl(MX35_IO_ADDRESS(MX35_IIM_BASE_ADDR + MXC_IIMSREV));
+ switch (rev) {
+ case 0x00:
+ mx35_cpu_rev = IMX_CHIP_REVISION_1_0;
+ srev = "1.0";
+ break;
+ case 0x10:
+ mx35_cpu_rev = IMX_CHIP_REVISION_2_0;
+ srev = "2.0";
+ break;
+ case 0x11:
+ mx35_cpu_rev = IMX_CHIP_REVISION_2_1;
+ srev = "2.1";
+ break;
+ default:
+ mx35_cpu_rev = IMX_CHIP_REVISION_UNKNOWN;
+ srev = "unknown";
+ }
+
+ printk(KERN_INFO "CPU identified as i.MX35, silicon rev %s\n", srev);
+}
diff --git a/arch/arm/mach-mx3/crm_regs.h b/arch/arm/mach-imx/crmregs-imx31.h
similarity index 100%
rename from arch/arm/mach-mx3/crm_regs.h
rename to arch/arm/mach-imx/crmregs-imx31.h
diff --git a/arch/arm/mach-imx/devices-imx1.h b/arch/arm/mach-imx/devices-imx1.h
index da59365..3aad1e7 100644
--- a/arch/arm/mach-imx/devices-imx1.h
+++ b/arch/arm/mach-imx/devices-imx1.h
@@ -9,21 +9,21 @@
#include <mach/mx1.h>
#include <mach/devices-common.h>
-extern const struct imx_imx_fb_data imx1_imx_fb_data __initconst;
+extern const struct imx_imx_fb_data imx1_imx_fb_data;
#define imx1_add_imx_fb(pdata) \
imx_add_imx_fb(&imx1_imx_fb_data, pdata)
-extern const struct imx_imx_i2c_data imx1_imx_i2c_data __initconst;
+extern const struct imx_imx_i2c_data imx1_imx_i2c_data;
#define imx1_add_imx_i2c(pdata) \
imx_add_imx_i2c(&imx1_imx_i2c_data, pdata)
-extern const struct imx_imx_uart_3irq_data imx1_imx_uart_data[] __initconst;
+extern const struct imx_imx_uart_3irq_data imx1_imx_uart_data[];
#define imx1_add_imx_uart(id, pdata) \
imx_add_imx_uart_3irq(&imx1_imx_uart_data[id], pdata)
#define imx1_add_imx_uart0(pdata) imx1_add_imx_uart(0, pdata)
#define imx1_add_imx_uart1(pdata) imx1_add_imx_uart(1, pdata)
-extern const struct imx_spi_imx_data imx1_cspi_data[] __initconst;
+extern const struct imx_spi_imx_data imx1_cspi_data[];
#define imx1_add_cspi(id, pdata) \
imx_add_spi_imx(&imx1_cspi_data[id], pdata)
diff --git a/arch/arm/mach-imx/devices-imx21.h b/arch/arm/mach-imx/devices-imx21.h
index 16744d2..2628e0c 100644
--- a/arch/arm/mach-imx/devices-imx21.h
+++ b/arch/arm/mach-imx/devices-imx21.h
@@ -9,31 +9,31 @@
#include <mach/mx21.h>
#include <mach/devices-common.h>
-extern const struct imx_imx21_hcd_data imx21_imx21_hcd_data __initconst;
+extern const struct imx_imx21_hcd_data imx21_imx21_hcd_data;
#define imx21_add_imx21_hcd(pdata) \
imx_add_imx21_hcd(&imx21_imx21_hcd_data, pdata)
-extern const struct imx_imx2_wdt_data imx21_imx2_wdt_data __initconst;
+extern const struct imx_imx2_wdt_data imx21_imx2_wdt_data;
#define imx21_add_imx2_wdt(pdata) \
imx_add_imx2_wdt(&imx21_imx2_wdt_data)
-extern const struct imx_imx_fb_data imx21_imx_fb_data __initconst;
+extern const struct imx_imx_fb_data imx21_imx_fb_data;
#define imx21_add_imx_fb(pdata) \
imx_add_imx_fb(&imx21_imx_fb_data, pdata)
-extern const struct imx_imx_i2c_data imx21_imx_i2c_data __initconst;
+extern const struct imx_imx_i2c_data imx21_imx_i2c_data;
#define imx21_add_imx_i2c(pdata) \
imx_add_imx_i2c(&imx21_imx_i2c_data, pdata)
-extern const struct imx_imx_keypad_data imx21_imx_keypad_data __initconst;
+extern const struct imx_imx_keypad_data imx21_imx_keypad_data;
#define imx21_add_imx_keypad(pdata) \
imx_add_imx_keypad(&imx21_imx_keypad_data, pdata)
-extern const struct imx_imx_ssi_data imx21_imx_ssi_data[] __initconst;
+extern const struct imx_imx_ssi_data imx21_imx_ssi_data[];
#define imx21_add_imx_ssi(id, pdata) \
imx_add_imx_ssi(&imx21_imx_ssi_data[id], pdata)
-extern const struct imx_imx_uart_1irq_data imx21_imx_uart_data[] __initconst;
+extern const struct imx_imx_uart_1irq_data imx21_imx_uart_data[];
#define imx21_add_imx_uart(id, pdata) \
imx_add_imx_uart_1irq(&imx21_imx_uart_data[id], pdata)
#define imx21_add_imx_uart0(pdata) imx21_add_imx_uart(0, pdata)
@@ -41,19 +41,19 @@
#define imx21_add_imx_uart2(pdata) imx21_add_imx_uart(2, pdata)
#define imx21_add_imx_uart3(pdata) imx21_add_imx_uart(3, pdata)
-extern const struct imx_mxc_mmc_data imx21_mxc_mmc_data[] __initconst;
+extern const struct imx_mxc_mmc_data imx21_mxc_mmc_data[];
#define imx21_add_mxc_mmc(id, pdata) \
imx_add_mxc_mmc(&imx21_mxc_mmc_data[id], pdata)
-extern const struct imx_mxc_nand_data imx21_mxc_nand_data __initconst;
+extern const struct imx_mxc_nand_data imx21_mxc_nand_data;
#define imx21_add_mxc_nand(pdata) \
imx_add_mxc_nand(&imx21_mxc_nand_data, pdata)
-extern const struct imx_mxc_w1_data imx21_mxc_w1_data __initconst;
+extern const struct imx_mxc_w1_data imx21_mxc_w1_data;
#define imx21_add_mxc_w1(pdata) \
imx_add_mxc_w1(&imx21_mxc_w1_data)
-extern const struct imx_spi_imx_data imx21_cspi_data[] __initconst;
+extern const struct imx_spi_imx_data imx21_cspi_data[];
#define imx21_add_cspi(id, pdata) \
imx_add_spi_imx(&imx21_cspi_data[id], pdata)
#define imx21_add_spi_imx0(pdata) imx21_add_cspi(0, pdata)
diff --git a/arch/arm/mach-imx/devices-imx25.h b/arch/arm/mach-imx/devices-imx25.h
index b591d72..efa0761 100644
--- a/arch/arm/mach-imx/devices-imx25.h
+++ b/arch/arm/mach-imx/devices-imx25.h
@@ -9,48 +9,48 @@
#include <mach/mx25.h>
#include <mach/devices-common.h>
-extern const struct imx_fec_data imx25_fec_data __initconst;
+extern const struct imx_fec_data imx25_fec_data;
#define imx25_add_fec(pdata) \
imx_add_fec(&imx25_fec_data, pdata)
-extern const struct imx_flexcan_data imx25_flexcan_data[] __initconst;
+extern const struct imx_flexcan_data imx25_flexcan_data[];
#define imx25_add_flexcan(id, pdata) \
imx_add_flexcan(&imx25_flexcan_data[id], pdata)
#define imx25_add_flexcan0(pdata) imx25_add_flexcan(0, pdata)
#define imx25_add_flexcan1(pdata) imx25_add_flexcan(1, pdata)
-extern const struct imx_fsl_usb2_udc_data imx25_fsl_usb2_udc_data __initconst;
+extern const struct imx_fsl_usb2_udc_data imx25_fsl_usb2_udc_data;
#define imx25_add_fsl_usb2_udc(pdata) \
imx_add_fsl_usb2_udc(&imx25_fsl_usb2_udc_data, pdata)
-extern struct imx_imxdi_rtc_data imx25_imxdi_rtc_data __initconst;
+extern struct imx_imxdi_rtc_data imx25_imxdi_rtc_data;
#define imx25_add_imxdi_rtc(pdata) \
imx_add_imxdi_rtc(&imx25_imxdi_rtc_data)
-extern const struct imx_imx2_wdt_data imx25_imx2_wdt_data __initconst;
+extern const struct imx_imx2_wdt_data imx25_imx2_wdt_data;
#define imx25_add_imx2_wdt(pdata) \
imx_add_imx2_wdt(&imx25_imx2_wdt_data)
-extern const struct imx_imx_fb_data imx25_imx_fb_data __initconst;
+extern const struct imx_imx_fb_data imx25_imx_fb_data;
#define imx25_add_imx_fb(pdata) \
imx_add_imx_fb(&imx25_imx_fb_data, pdata)
-extern const struct imx_imx_i2c_data imx25_imx_i2c_data[] __initconst;
+extern const struct imx_imx_i2c_data imx25_imx_i2c_data[];
#define imx25_add_imx_i2c(id, pdata) \
imx_add_imx_i2c(&imx25_imx_i2c_data[id], pdata)
#define imx25_add_imx_i2c0(pdata) imx25_add_imx_i2c(0, pdata)
#define imx25_add_imx_i2c1(pdata) imx25_add_imx_i2c(1, pdata)
#define imx25_add_imx_i2c2(pdata) imx25_add_imx_i2c(2, pdata)
-extern const struct imx_imx_keypad_data imx25_imx_keypad_data __initconst;
+extern const struct imx_imx_keypad_data imx25_imx_keypad_data;
#define imx25_add_imx_keypad(pdata) \
imx_add_imx_keypad(&imx25_imx_keypad_data, pdata)
-extern const struct imx_imx_ssi_data imx25_imx_ssi_data[] __initconst;
+extern const struct imx_imx_ssi_data imx25_imx_ssi_data[];
#define imx25_add_imx_ssi(id, pdata) \
imx_add_imx_ssi(&imx25_imx_ssi_data[id], pdata)
-extern const struct imx_imx_uart_1irq_data imx25_imx_uart_data[] __initconst;
+extern const struct imx_imx_uart_1irq_data imx25_imx_uart_data[];
#define imx25_add_imx_uart(id, pdata) \
imx_add_imx_uart_1irq(&imx25_imx_uart_data[id], pdata)
#define imx25_add_imx_uart0(pdata) imx25_add_imx_uart(0, pdata)
@@ -59,33 +59,32 @@
#define imx25_add_imx_uart3(pdata) imx25_add_imx_uart(3, pdata)
#define imx25_add_imx_uart4(pdata) imx25_add_imx_uart(4, pdata)
-extern const struct imx_mx2_camera_data imx25_mx2_camera_data __initconst;
+extern const struct imx_mx2_camera_data imx25_mx2_camera_data;
#define imx25_add_mx2_camera(pdata) \
imx_add_mx2_camera(&imx25_mx2_camera_data, pdata)
-extern const struct imx_mxc_ehci_data imx25_mxc_ehci_otg_data __initconst;
+extern const struct imx_mxc_ehci_data imx25_mxc_ehci_otg_data;
#define imx25_add_mxc_ehci_otg(pdata) \
imx_add_mxc_ehci(&imx25_mxc_ehci_otg_data, pdata)
-extern const struct imx_mxc_ehci_data imx25_mxc_ehci_hs_data __initconst;
+extern const struct imx_mxc_ehci_data imx25_mxc_ehci_hs_data;
#define imx25_add_mxc_ehci_hs(pdata) \
imx_add_mxc_ehci(&imx25_mxc_ehci_hs_data, pdata)
-extern const struct imx_mxc_nand_data imx25_mxc_nand_data __initconst;
+extern const struct imx_mxc_nand_data imx25_mxc_nand_data;
#define imx25_add_mxc_nand(pdata) \
imx_add_mxc_nand(&imx25_mxc_nand_data, pdata)
-extern const struct imx_sdhci_esdhc_imx_data
-imx25_sdhci_esdhc_imx_data[] __initconst;
+extern const struct imx_sdhci_esdhc_imx_data imx25_sdhci_esdhc_imx_data[];
#define imx25_add_sdhci_esdhc_imx(id, pdata) \
imx_add_sdhci_esdhc_imx(&imx25_sdhci_esdhc_imx_data[id], pdata)
-extern const struct imx_spi_imx_data imx25_cspi_data[] __initconst;
+extern const struct imx_spi_imx_data imx25_cspi_data[];
#define imx25_add_spi_imx(id, pdata) \
imx_add_spi_imx(&imx25_cspi_data[id], pdata)
#define imx25_add_spi_imx0(pdata) imx25_add_spi_imx(0, pdata)
#define imx25_add_spi_imx1(pdata) imx25_add_spi_imx(1, pdata)
#define imx25_add_spi_imx2(pdata) imx25_add_spi_imx(2, pdata)
-extern struct imx_mxc_pwm_data imx25_mxc_pwm_data[] __initconst;
+extern struct imx_mxc_pwm_data imx25_mxc_pwm_data[];
#define imx25_add_mxc_pwm(id) \
imx_add_mxc_pwm(&imx25_mxc_pwm_data[id])
diff --git a/arch/arm/mach-imx/devices-imx27.h b/arch/arm/mach-imx/devices-imx27.h
index f1272d4..7f97a3c 100644
--- a/arch/arm/mach-imx/devices-imx27.h
+++ b/arch/arm/mach-imx/devices-imx27.h
@@ -9,35 +9,35 @@
#include <mach/mx27.h>
#include <mach/devices-common.h>
-extern const struct imx_fec_data imx27_fec_data __initconst;
+extern const struct imx_fec_data imx27_fec_data;
#define imx27_add_fec(pdata) \
imx_add_fec(&imx27_fec_data, pdata)
-extern const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data __initconst;
+extern const struct imx_fsl_usb2_udc_data imx27_fsl_usb2_udc_data;
#define imx27_add_fsl_usb2_udc(pdata) \
imx_add_fsl_usb2_udc(&imx27_fsl_usb2_udc_data, pdata)
-extern const struct imx_imx2_wdt_data imx27_imx2_wdt_data __initconst;
+extern const struct imx_imx2_wdt_data imx27_imx2_wdt_data;
#define imx27_add_imx2_wdt(pdata) \
imx_add_imx2_wdt(&imx27_imx2_wdt_data)
-extern const struct imx_imx_fb_data imx27_imx_fb_data __initconst;
+extern const struct imx_imx_fb_data imx27_imx_fb_data;
#define imx27_add_imx_fb(pdata) \
imx_add_imx_fb(&imx27_imx_fb_data, pdata)
-extern const struct imx_imx_i2c_data imx27_imx_i2c_data[] __initconst;
+extern const struct imx_imx_i2c_data imx27_imx_i2c_data[];
#define imx27_add_imx_i2c(id, pdata) \
imx_add_imx_i2c(&imx27_imx_i2c_data[id], pdata)
-extern const struct imx_imx_keypad_data imx27_imx_keypad_data __initconst;
+extern const struct imx_imx_keypad_data imx27_imx_keypad_data;
#define imx27_add_imx_keypad(pdata) \
imx_add_imx_keypad(&imx27_imx_keypad_data, pdata)
-extern const struct imx_imx_ssi_data imx27_imx_ssi_data[] __initconst;
+extern const struct imx_imx_ssi_data imx27_imx_ssi_data[];
#define imx27_add_imx_ssi(id, pdata) \
imx_add_imx_ssi(&imx27_imx_ssi_data[id], pdata)
-extern const struct imx_imx_uart_1irq_data imx27_imx_uart_data[] __initconst;
+extern const struct imx_imx_uart_1irq_data imx27_imx_uart_data[];
#define imx27_add_imx_uart(id, pdata) \
imx_add_imx_uart_1irq(&imx27_imx_uart_data[id], pdata)
#define imx27_add_imx_uart0(pdata) imx27_add_imx_uart(0, pdata)
@@ -47,30 +47,30 @@
#define imx27_add_imx_uart4(pdata) imx27_add_imx_uart(4, pdata)
#define imx27_add_imx_uart5(pdata) imx27_add_imx_uart(5, pdata)
-extern const struct imx_mx2_camera_data imx27_mx2_camera_data __initconst;
+extern const struct imx_mx2_camera_data imx27_mx2_camera_data;
#define imx27_add_mx2_camera(pdata) \
imx_add_mx2_camera(&imx27_mx2_camera_data, pdata)
-extern const struct imx_mxc_ehci_data imx27_mxc_ehci_otg_data __initconst;
+extern const struct imx_mxc_ehci_data imx27_mxc_ehci_otg_data;
#define imx27_add_mxc_ehci_otg(pdata) \
imx_add_mxc_ehci(&imx27_mxc_ehci_otg_data, pdata)
-extern const struct imx_mxc_ehci_data imx27_mxc_ehci_hs_data[] __initconst;
+extern const struct imx_mxc_ehci_data imx27_mxc_ehci_hs_data[];
#define imx27_add_mxc_ehci_hs(id, pdata) \
imx_add_mxc_ehci(&imx27_mxc_ehci_hs_data[id - 1], pdata)
-extern const struct imx_mxc_mmc_data imx27_mxc_mmc_data[] __initconst;
+extern const struct imx_mxc_mmc_data imx27_mxc_mmc_data[];
#define imx27_add_mxc_mmc(id, pdata) \
imx_add_mxc_mmc(&imx27_mxc_mmc_data[id], pdata)
-extern const struct imx_mxc_nand_data imx27_mxc_nand_data __initconst;
+extern const struct imx_mxc_nand_data imx27_mxc_nand_data;
#define imx27_add_mxc_nand(pdata) \
imx_add_mxc_nand(&imx27_mxc_nand_data, pdata)
-extern const struct imx_mxc_w1_data imx27_mxc_w1_data __initconst;
+extern const struct imx_mxc_w1_data imx27_mxc_w1_data;
#define imx27_add_mxc_w1(pdata) \
imx_add_mxc_w1(&imx27_mxc_w1_data)
-extern const struct imx_spi_imx_data imx27_cspi_data[] __initconst;
+extern const struct imx_spi_imx_data imx27_cspi_data[];
#define imx27_add_cspi(id, pdata) \
imx_add_spi_imx(&imx27_cspi_data[id], pdata)
#define imx27_add_spi_imx0(pdata) imx27_add_cspi(0, pdata)
diff --git a/arch/arm/mach-imx/devices-imx31.h b/arch/arm/mach-imx/devices-imx31.h
new file mode 100644
index 0000000..dbe940d
--- /dev/null
+++ b/arch/arm/mach-imx/devices-imx31.h
@@ -0,0 +1,80 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/mx31.h>
+#include <mach/devices-common.h>
+
+extern const struct imx_fsl_usb2_udc_data imx31_fsl_usb2_udc_data;
+#define imx31_add_fsl_usb2_udc(pdata) \
+ imx_add_fsl_usb2_udc(&imx31_fsl_usb2_udc_data, pdata)
+
+extern const struct imx_imx2_wdt_data imx31_imx2_wdt_data;
+#define imx31_add_imx2_wdt(pdata) \
+ imx_add_imx2_wdt(&imx31_imx2_wdt_data)
+
+extern const struct imx_imx_i2c_data imx31_imx_i2c_data[];
+#define imx31_add_imx_i2c(id, pdata) \
+ imx_add_imx_i2c(&imx31_imx_i2c_data[id], pdata)
+#define imx31_add_imx_i2c0(pdata) imx31_add_imx_i2c(0, pdata)
+#define imx31_add_imx_i2c1(pdata) imx31_add_imx_i2c(1, pdata)
+#define imx31_add_imx_i2c2(pdata) imx31_add_imx_i2c(2, pdata)
+
+extern const struct imx_imx_keypad_data imx31_imx_keypad_data;
+#define imx31_add_imx_keypad(pdata) \
+ imx_add_imx_keypad(&imx31_imx_keypad_data, pdata)
+
+extern const struct imx_imx_ssi_data imx31_imx_ssi_data[];
+#define imx31_add_imx_ssi(id, pdata) \
+ imx_add_imx_ssi(&imx31_imx_ssi_data[id], pdata)
+
+extern const struct imx_imx_uart_1irq_data imx31_imx_uart_data[];
+#define imx31_add_imx_uart(id, pdata) \
+ imx_add_imx_uart_1irq(&imx31_imx_uart_data[id], pdata)
+#define imx31_add_imx_uart0(pdata) imx31_add_imx_uart(0, pdata)
+#define imx31_add_imx_uart1(pdata) imx31_add_imx_uart(1, pdata)
+#define imx31_add_imx_uart2(pdata) imx31_add_imx_uart(2, pdata)
+#define imx31_add_imx_uart3(pdata) imx31_add_imx_uart(3, pdata)
+#define imx31_add_imx_uart4(pdata) imx31_add_imx_uart(4, pdata)
+
+extern const struct imx_ipu_core_data imx31_ipu_core_data;
+#define imx31_add_ipu_core(pdata) \
+ imx_add_ipu_core(&imx31_ipu_core_data, pdata)
+#define imx31_alloc_mx3_camera(pdata) \
+ imx_alloc_mx3_camera(&imx31_ipu_core_data, pdata)
+#define imx31_add_mx3_sdc_fb(pdata) \
+ imx_add_mx3_sdc_fb(&imx31_ipu_core_data, pdata)
+
+extern const struct imx_mxc_ehci_data imx31_mxc_ehci_otg_data;
+#define imx31_add_mxc_ehci_otg(pdata) \
+ imx_add_mxc_ehci(&imx31_mxc_ehci_otg_data, pdata)
+extern const struct imx_mxc_ehci_data imx31_mxc_ehci_hs_data[];
+#define imx31_add_mxc_ehci_hs(id, pdata) \
+ imx_add_mxc_ehci(&imx31_mxc_ehci_hs_data[id - 1], pdata)
+
+extern const struct imx_mxc_mmc_data imx31_mxc_mmc_data[];
+#define imx31_add_mxc_mmc(id, pdata) \
+ imx_add_mxc_mmc(&imx31_mxc_mmc_data[id], pdata)
+
+extern const struct imx_mxc_nand_data imx31_mxc_nand_data;
+#define imx31_add_mxc_nand(pdata) \
+ imx_add_mxc_nand(&imx31_mxc_nand_data, pdata)
+
+extern const struct imx_mxc_rtc_data imx31_mxc_rtc_data;
+#define imx31_add_mxc_rtc(pdata) \
+ imx_add_mxc_rtc(&imx31_mxc_rtc_data)
+
+extern const struct imx_mxc_w1_data imx31_mxc_w1_data;
+#define imx31_add_mxc_w1(pdata) \
+ imx_add_mxc_w1(&imx31_mxc_w1_data)
+
+extern const struct imx_spi_imx_data imx31_cspi_data[];
+#define imx31_add_cspi(id, pdata) \
+ imx_add_spi_imx(&imx31_cspi_data[id], pdata)
+#define imx31_add_spi_imx0(pdata) imx31_add_cspi(0, pdata)
+#define imx31_add_spi_imx1(pdata) imx31_add_cspi(1, pdata)
+#define imx31_add_spi_imx2(pdata) imx31_add_cspi(2, pdata)
diff --git a/arch/arm/mach-imx/devices-imx35.h b/arch/arm/mach-imx/devices-imx35.h
new file mode 100644
index 0000000..234cbd3
--- /dev/null
+++ b/arch/arm/mach-imx/devices-imx35.h
@@ -0,0 +1,83 @@
+/*
+ * Copyright (C) 2010 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/mx35.h>
+#include <mach/devices-common.h>
+
+extern const struct imx_fec_data imx35_fec_data;
+#define imx35_add_fec(pdata) \
+ imx_add_fec(&imx35_fec_data, pdata)
+
+extern const struct imx_fsl_usb2_udc_data imx35_fsl_usb2_udc_data;
+#define imx35_add_fsl_usb2_udc(pdata) \
+ imx_add_fsl_usb2_udc(&imx35_fsl_usb2_udc_data, pdata)
+
+extern const struct imx_flexcan_data imx35_flexcan_data[];
+#define imx35_add_flexcan(id, pdata) \
+ imx_add_flexcan(&imx35_flexcan_data[id], pdata)
+#define imx35_add_flexcan0(pdata) imx35_add_flexcan(0, pdata)
+#define imx35_add_flexcan1(pdata) imx35_add_flexcan(1, pdata)
+
+extern const struct imx_imx2_wdt_data imx35_imx2_wdt_data;
+#define imx35_add_imx2_wdt(pdata) \
+ imx_add_imx2_wdt(&imx35_imx2_wdt_data)
+
+extern const struct imx_imx_i2c_data imx35_imx_i2c_data[];
+#define imx35_add_imx_i2c(id, pdata) \
+ imx_add_imx_i2c(&imx35_imx_i2c_data[id], pdata)
+#define imx35_add_imx_i2c0(pdata) imx35_add_imx_i2c(0, pdata)
+#define imx35_add_imx_i2c1(pdata) imx35_add_imx_i2c(1, pdata)
+#define imx35_add_imx_i2c2(pdata) imx35_add_imx_i2c(2, pdata)
+
+extern const struct imx_imx_keypad_data imx35_imx_keypad_data;
+#define imx35_add_imx_keypad(pdata) \
+ imx_add_imx_keypad(&imx35_imx_keypad_data, pdata)
+
+extern const struct imx_imx_ssi_data imx35_imx_ssi_data[];
+#define imx35_add_imx_ssi(id, pdata) \
+ imx_add_imx_ssi(&imx35_imx_ssi_data[id], pdata)
+
+extern const struct imx_imx_uart_1irq_data imx35_imx_uart_data[];
+#define imx35_add_imx_uart(id, pdata) \
+ imx_add_imx_uart_1irq(&imx35_imx_uart_data[id], pdata)
+#define imx35_add_imx_uart0(pdata) imx35_add_imx_uart(0, pdata)
+#define imx35_add_imx_uart1(pdata) imx35_add_imx_uart(1, pdata)
+#define imx35_add_imx_uart2(pdata) imx35_add_imx_uart(2, pdata)
+
+extern const struct imx_ipu_core_data imx35_ipu_core_data;
+#define imx35_add_ipu_core(pdata) \
+ imx_add_ipu_core(&imx35_ipu_core_data, pdata)
+#define imx35_alloc_mx3_camera(pdata) \
+ imx_alloc_mx3_camera(&imx35_ipu_core_data, pdata)
+#define imx35_add_mx3_sdc_fb(pdata) \
+ imx_add_mx3_sdc_fb(&imx35_ipu_core_data, pdata)
+
+extern const struct imx_mxc_ehci_data imx35_mxc_ehci_otg_data;
+#define imx35_add_mxc_ehci_otg(pdata) \
+ imx_add_mxc_ehci(&imx35_mxc_ehci_otg_data, pdata)
+extern const struct imx_mxc_ehci_data imx35_mxc_ehci_hs_data;
+#define imx35_add_mxc_ehci_hs(pdata) \
+ imx_add_mxc_ehci(&imx35_mxc_ehci_hs_data, pdata)
+
+extern const struct imx_mxc_nand_data imx35_mxc_nand_data;
+#define imx35_add_mxc_nand(pdata) \
+ imx_add_mxc_nand(&imx35_mxc_nand_data, pdata)
+
+extern const struct imx_mxc_w1_data imx35_mxc_w1_data;
+#define imx35_add_mxc_w1(pdata) \
+ imx_add_mxc_w1(&imx35_mxc_w1_data)
+
+extern const struct imx_sdhci_esdhc_imx_data imx35_sdhci_esdhc_imx_data[];
+#define imx35_add_sdhci_esdhc_imx(id, pdata) \
+ imx_add_sdhci_esdhc_imx(&imx35_sdhci_esdhc_imx_data[id], pdata)
+
+extern const struct imx_spi_imx_data imx35_cspi_data[];
+#define imx35_add_cspi(id, pdata) \
+ imx_add_spi_imx(&imx35_cspi_data[id], pdata)
+#define imx35_add_spi_imx0(pdata) imx35_add_cspi(0, pdata)
+#define imx35_add_spi_imx1(pdata) imx35_add_cspi(1, pdata)
diff --git a/arch/arm/mach-imx/ehci-imx31.c b/arch/arm/mach-imx/ehci-imx31.c
new file mode 100644
index 0000000..faad0f1
--- /dev/null
+++ b/arch/arm/mach-imx/ehci-imx31.c
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+#include <mach/mxc_ehci.h>
+
+#define USBCTRL_OTGBASE_OFFSET 0x600
+
+#define MX31_OTG_SIC_SHIFT 29
+#define MX31_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT)
+#define MX31_OTG_PM_BIT (1 << 24)
+
+#define MX31_H2_SIC_SHIFT 21
+#define MX31_H2_SIC_MASK (0x3 << MX31_H2_SIC_SHIFT)
+#define MX31_H2_PM_BIT (1 << 16)
+#define MX31_H2_DT_BIT (1 << 5)
+
+#define MX31_H1_SIC_SHIFT 13
+#define MX31_H1_SIC_MASK (0x3 << MX31_H1_SIC_SHIFT)
+#define MX31_H1_PM_BIT (1 << 8)
+#define MX31_H1_DT_BIT (1 << 4)
+
+int mx31_initialize_usb_hw(int port, unsigned int flags)
+{
+ unsigned int v;
+
+ v = readl(MX31_IO_ADDRESS(MX31_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
+
+ switch (port) {
+ case 0: /* OTG port */
+ v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
+ v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_OTG_SIC_SHIFT;
+
+ if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+ v |= MX31_OTG_PM_BIT;
+
+ break;
+ case 1: /* H1 port */
+ v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT);
+ v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H1_SIC_SHIFT;
+
+ if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+ v |= MX31_H1_PM_BIT;
+
+ if (!(flags & MXC_EHCI_TTL_ENABLED))
+ v |= MX31_H1_DT_BIT;
+
+ break;
+ case 2: /* H2 port */
+ v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT);
+ v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H2_SIC_SHIFT;
+
+ if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+ v |= MX31_H2_PM_BIT;
+
+ if (!(flags & MXC_EHCI_TTL_ENABLED))
+ v |= MX31_H2_DT_BIT;
+
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ writel(v, MX31_IO_ADDRESS(MX31_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
+
+ return 0;
+}
diff --git a/arch/arm/mach-imx/ehci-imx35.c b/arch/arm/mach-imx/ehci-imx35.c
new file mode 100644
index 0000000..001ec39
--- /dev/null
+++ b/arch/arm/mach-imx/ehci-imx35.c
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
+ * Copyright (C) 2010 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/io.h>
+
+#include <mach/hardware.h>
+#include <mach/mxc_ehci.h>
+
+#define USBCTRL_OTGBASE_OFFSET 0x600
+
+#define MX35_OTG_SIC_SHIFT 29
+#define MX35_OTG_SIC_MASK (0x3 << MX35_OTG_SIC_SHIFT)
+#define MX35_OTG_PM_BIT (1 << 24)
+
+#define MX35_H1_SIC_SHIFT 21
+#define MX35_H1_SIC_MASK (0x3 << MX35_H1_SIC_SHIFT)
+#define MX35_H1_PM_BIT (1 << 8)
+#define MX35_H1_IPPUE_UP_BIT (1 << 7)
+#define MX35_H1_IPPUE_DOWN_BIT (1 << 6)
+#define MX35_H1_TLL_BIT (1 << 5)
+#define MX35_H1_USBTE_BIT (1 << 4)
+
+int mx35_initialize_usb_hw(int port, unsigned int flags)
+{
+ unsigned int v;
+
+ v = readl(MX35_IO_ADDRESS(MX35_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
+
+ switch (port) {
+ case 0: /* OTG port */
+ v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT);
+ v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_OTG_SIC_SHIFT;
+
+ if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+ v |= MX35_OTG_PM_BIT;
+
+ break;
+ case 1: /* H1 port */
+ v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT |
+ MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT);
+ v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_H1_SIC_SHIFT;
+
+ if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
+ v |= MX35_H1_PM_BIT;
+
+ if (!(flags & MXC_EHCI_TTL_ENABLED))
+ v |= MX35_H1_TLL_BIT;
+
+ if (flags & MXC_EHCI_INTERNAL_PHY)
+ v |= MX35_H1_USBTE_BIT;
+
+ if (flags & MXC_EHCI_IPPUE_DOWN)
+ v |= MX35_H1_IPPUE_DOWN_BIT;
+
+ if (flags & MXC_EHCI_IPPUE_UP)
+ v |= MX35_H1_IPPUE_UP_BIT;
+
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ writel(v, MX35_IO_ADDRESS(MX35_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
+
+ return 0;
+}
diff --git a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
index fa5288018..5911281 100644
--- a/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimx27-baseboard.c
@@ -32,7 +32,6 @@
#include <mach/common.h>
#include <mach/iomux-mx27.h>
#include <mach/hardware.h>
-#include <mach/spi.h>
#include <mach/audmux.h>
#include "devices-imx27.h"
diff --git a/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
index 6269053..f9ef04a 100644
--- a/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
+++ b/arch/arm/mach-imx/eukrea_mbimxsd25-baseboard.c
@@ -22,7 +22,6 @@
#include <linux/gpio.h>
#include <linux/leds.h>
#include <linux/platform_device.h>
-#include <linux/gpio_keys.h>
#include <linux/input.h>
#include <video/platform_lcd.h>
@@ -32,9 +31,7 @@
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <mach/mx25.h>
-#include <mach/imx-uart.h>
#include <mach/audmux.h>
-#include <mach/esdhc.h>
#include "devices-imx25.h"
@@ -208,23 +205,14 @@
},
};
-static struct gpio_keys_platform_data eukrea_mbimxsd_button_data = {
+static const struct gpio_keys_platform_data
+ eukrea_mbimxsd_button_data __initconst = {
.buttons = eukrea_mbimxsd_gpio_buttons,
.nbuttons = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons),
};
-static struct platform_device eukrea_mbimxsd_button_device = {
- .name = "gpio-keys",
- .id = -1,
- .num_resources = 0,
- .dev = {
- .platform_data = &eukrea_mbimxsd_button_data,
- }
-};
-
static struct platform_device *platform_devices[] __initdata = {
&eukrea_mbimxsd_leds_gpio,
- &eukrea_mbimxsd_button_device,
&eukrea_mbimxsd_lcd_powerdev,
};
@@ -299,4 +287,5 @@
ARRAY_SIZE(eukrea_mbimxsd_i2c_devices));
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+ imx_add_gpio_keys(&eukrea_mbimxsd_button_data);
}
diff --git a/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c b/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
new file mode 100644
index 0000000..4909ea0
--- /dev/null
+++ b/arch/arm/mach-imx/eukrea_mbimxsd35-baseboard.c
@@ -0,0 +1,303 @@
+/*
+ * Copyright (C) 2010 Eric Benard - eric@eukrea.com
+ *
+ * Based on pcm970-baseboard.c which is :
+ * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+
+#include <linux/gpio.h>
+#include <linux/interrupt.h>
+#include <linux/leds.h>
+#include <linux/platform_device.h>
+#include <linux/input.h>
+#include <video/platform_lcd.h>
+#include <linux/i2c.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/iomux-mx35.h>
+#include <mach/audmux.h>
+
+#include "devices-imx35.h"
+
+static const struct fb_videomode fb_modedb[] = {
+ {
+ .name = "CMO-QVGA",
+ .refresh = 60,
+ .xres = 320,
+ .yres = 240,
+ .pixclock = KHZ2PICOS(6500),
+ .left_margin = 68,
+ .right_margin = 20,
+ .upper_margin = 15,
+ .lower_margin = 4,
+ .hsync_len = 30,
+ .vsync_len = 3,
+ .sync = 0,
+ .vmode = FB_VMODE_NONINTERLACED,
+ .flag = 0,
+ },
+ {
+ .name = "DVI-VGA",
+ .refresh = 60,
+ .xres = 640,
+ .yres = 480,
+ .pixclock = 32000,
+ .left_margin = 100,
+ .right_margin = 100,
+ .upper_margin = 7,
+ .lower_margin = 100,
+ .hsync_len = 7,
+ .vsync_len = 7,
+ .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT |
+ FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT,
+ .vmode = FB_VMODE_NONINTERLACED,
+ .flag = 0,
+ },
+ {
+ .name = "DVI-SVGA",
+ .refresh = 60,
+ .xres = 800,
+ .yres = 600,
+ .pixclock = 25000,
+ .left_margin = 75,
+ .right_margin = 75,
+ .upper_margin = 7,
+ .lower_margin = 75,
+ .hsync_len = 7,
+ .vsync_len = 7,
+ .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT |
+ FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT,
+ .vmode = FB_VMODE_NONINTERLACED,
+ .flag = 0,
+ },
+};
+
+static const struct ipu_platform_data mx3_ipu_data __initconst = {
+ .irq_base = MXC_IPU_IRQ_START,
+};
+
+static struct mx3fb_platform_data mx3fb_pdata __initdata = {
+ .name = "CMO-QVGA",
+ .mode = fb_modedb,
+ .num_modes = ARRAY_SIZE(fb_modedb),
+};
+
+static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = {
+ /* LCD */
+ MX35_PAD_LD0__IPU_DISPB_DAT_0,
+ MX35_PAD_LD1__IPU_DISPB_DAT_1,
+ MX35_PAD_LD2__IPU_DISPB_DAT_2,
+ MX35_PAD_LD3__IPU_DISPB_DAT_3,
+ MX35_PAD_LD4__IPU_DISPB_DAT_4,
+ MX35_PAD_LD5__IPU_DISPB_DAT_5,
+ MX35_PAD_LD6__IPU_DISPB_DAT_6,
+ MX35_PAD_LD7__IPU_DISPB_DAT_7,
+ MX35_PAD_LD8__IPU_DISPB_DAT_8,
+ MX35_PAD_LD9__IPU_DISPB_DAT_9,
+ MX35_PAD_LD10__IPU_DISPB_DAT_10,
+ MX35_PAD_LD11__IPU_DISPB_DAT_11,
+ MX35_PAD_LD12__IPU_DISPB_DAT_12,
+ MX35_PAD_LD13__IPU_DISPB_DAT_13,
+ MX35_PAD_LD14__IPU_DISPB_DAT_14,
+ MX35_PAD_LD15__IPU_DISPB_DAT_15,
+ MX35_PAD_LD16__IPU_DISPB_DAT_16,
+ MX35_PAD_LD17__IPU_DISPB_DAT_17,
+ MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC,
+ MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK,
+ MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY,
+ MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC,
+ /* Backlight */
+ MX35_PAD_CONTRAST__IPU_DISPB_CONTR,
+ /* LCD_PWR */
+ MX35_PAD_D3_CLS__GPIO1_4,
+ /* LED */
+ MX35_PAD_LD23__GPIO3_29,
+ /* SWITCH */
+ MX35_PAD_LD19__GPIO3_25,
+ /* UART2 */
+ MX35_PAD_CTS2__UART2_CTS,
+ MX35_PAD_RTS2__UART2_RTS,
+ MX35_PAD_TXD2__UART2_TXD_MUX,
+ MX35_PAD_RXD2__UART2_RXD_MUX,
+ /* I2S */
+ MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS,
+ MX35_PAD_STXD4__AUDMUX_AUD4_TXD,
+ MX35_PAD_SRXD4__AUDMUX_AUD4_RXD,
+ MX35_PAD_SCK4__AUDMUX_AUD4_TXC,
+ /* CAN2 */
+ MX35_PAD_TX5_RX0__CAN2_TXCAN,
+ MX35_PAD_TX4_RX1__CAN2_RXCAN,
+ /* SDCARD */
+ MX35_PAD_SD1_CMD__ESDHC1_CMD,
+ MX35_PAD_SD1_CLK__ESDHC1_CLK,
+ MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
+ MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
+ MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
+ MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
+ /* SD1 CD */
+ MX35_PAD_LD18__GPIO3_24,
+};
+
+#define GPIO_LED1 IMX_GPIO_NR(3, 29)
+#define GPIO_SWITCH1 IMX_GPIO_NR(3, 25)
+#define GPIO_LCDPWR IMX_GPIO_NR(1, 4)
+#define GPIO_SD1CD IMX_GPIO_NR(3, 24)
+
+static void eukrea_mbimxsd_lcd_power_set(struct plat_lcd_data *pd,
+ unsigned int power)
+{
+ if (power)
+ gpio_direction_output(GPIO_LCDPWR, 1);
+ else
+ gpio_direction_output(GPIO_LCDPWR, 0);
+}
+
+static struct plat_lcd_data eukrea_mbimxsd_lcd_power_data = {
+ .set_power = eukrea_mbimxsd_lcd_power_set,
+};
+
+static struct platform_device eukrea_mbimxsd_lcd_powerdev = {
+ .name = "platform-lcd",
+ .dev.platform_data = &eukrea_mbimxsd_lcd_power_data,
+};
+
+static struct gpio_led eukrea_mbimxsd_leds[] = {
+ {
+ .name = "led1",
+ .default_trigger = "heartbeat",
+ .active_low = 1,
+ .gpio = GPIO_LED1,
+ },
+};
+
+static struct gpio_led_platform_data eukrea_mbimxsd_led_info = {
+ .leds = eukrea_mbimxsd_leds,
+ .num_leds = ARRAY_SIZE(eukrea_mbimxsd_leds),
+};
+
+static struct platform_device eukrea_mbimxsd_leds_gpio = {
+ .name = "leds-gpio",
+ .id = -1,
+ .dev = {
+ .platform_data = &eukrea_mbimxsd_led_info,
+ },
+};
+
+static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = {
+ {
+ .gpio = GPIO_SWITCH1,
+ .code = BTN_0,
+ .desc = "BP1",
+ .active_low = 1,
+ .wakeup = 1,
+ },
+};
+
+static const struct gpio_keys_platform_data
+ eukrea_mbimxsd_button_data __initconst = {
+ .buttons = eukrea_mbimxsd_gpio_buttons,
+ .nbuttons = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons),
+};
+
+static struct platform_device *platform_devices[] __initdata = {
+ &eukrea_mbimxsd_leds_gpio,
+ &eukrea_mbimxsd_lcd_powerdev,
+};
+
+static const struct imxuart_platform_data uart_pdata __initconst = {
+ .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static struct i2c_board_info eukrea_mbimxsd_i2c_devices[] = {
+ {
+ I2C_BOARD_INFO("tlv320aic23", 0x1a),
+ },
+};
+
+static const
+struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata __initconst = {
+ .flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE,
+};
+
+static struct esdhc_platform_data sd1_pdata = {
+ .cd_gpio = GPIO_SD1CD,
+ .wp_gpio = -EINVAL,
+};
+
+/*
+ * system init for baseboard usage. Will be called by cpuimx35 init.
+ *
+ * Add platform devices present on this baseboard and init
+ * them from CPU side as far as required to use them later on
+ */
+void __init eukrea_mbimxsd35_baseboard_init(void)
+{
+ if (mxc_iomux_v3_setup_multiple_pads(eukrea_mbimxsd_pads,
+ ARRAY_SIZE(eukrea_mbimxsd_pads)))
+ printk(KERN_ERR "error setting mbimxsd pads !\n");
+
+#if defined(CONFIG_SND_SOC_EUKREA_TLV320)
+ /* SSI unit master I2S codec connected to SSI_AUD4 */
+ mxc_audmux_v2_configure_port(0,
+ MXC_AUDMUX_V2_PTCR_SYN |
+ MXC_AUDMUX_V2_PTCR_TFSDIR |
+ MXC_AUDMUX_V2_PTCR_TFSEL(3) |
+ MXC_AUDMUX_V2_PTCR_TCLKDIR |
+ MXC_AUDMUX_V2_PTCR_TCSEL(3),
+ MXC_AUDMUX_V2_PDCR_RXDSEL(3)
+ );
+ mxc_audmux_v2_configure_port(3,
+ MXC_AUDMUX_V2_PTCR_SYN,
+ MXC_AUDMUX_V2_PDCR_RXDSEL(0)
+ );
+#endif
+
+ imx35_add_imx_uart1(&uart_pdata);
+ imx35_add_ipu_core(&mx3_ipu_data);
+ imx35_add_mx3_sdc_fb(&mx3fb_pdata);
+
+ imx35_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata);
+
+ imx35_add_flexcan1(NULL);
+ imx35_add_sdhci_esdhc_imx(0, &sd1_pdata);
+
+ gpio_request(GPIO_LED1, "LED1");
+ gpio_direction_output(GPIO_LED1, 1);
+ gpio_free(GPIO_LED1);
+
+ gpio_request(GPIO_SWITCH1, "SWITCH1");
+ gpio_direction_input(GPIO_SWITCH1);
+ gpio_free(GPIO_SWITCH1);
+
+ gpio_request(GPIO_LCDPWR, "LCDPWR");
+ gpio_direction_output(GPIO_LCDPWR, 1);
+
+ i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices,
+ ARRAY_SIZE(eukrea_mbimxsd_i2c_devices));
+
+ platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+ imx_add_gpio_keys(&eukrea_mbimxsd_button_data);
+}
diff --git a/arch/arm/mach-mx3/iomux-imx31.c b/arch/arm/mach-imx/iomux-imx31.c
similarity index 100%
rename from arch/arm/mach-mx3/iomux-imx31.c
rename to arch/arm/mach-imx/iomux-imx31.c
diff --git a/arch/arm/mach-imx/mach-apf9328.c b/arch/arm/mach-imx/mach-apf9328.c
new file mode 100644
index 0000000..15e45c8
--- /dev/null
+++ b/arch/arm/mach-imx/mach-apf9328.c
@@ -0,0 +1,144 @@
+/*
+ * linux/arch/arm/mach-imx/mach-apf9328.c
+ *
+ * Copyright (c) 2005-2011 ARMadeus systems <support@armadeus.com>
+ *
+ * This work is based on mach-scb9328.c which is:
+ * Copyright (c) 2004 Sascha Hauer <saschahauer@web.de>
+ * Copyright (c) 2006-2008 Juergen Beisert <jbeisert@netscape.net>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+#include <linux/dm9000.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/irqs.h>
+#include <mach/iomux-mx1.h>
+
+#include "devices-imx1.h"
+
+static const int apf9328_pins[] __initconst = {
+ /* UART1 */
+ PC9_PF_UART1_CTS,
+ PC10_PF_UART1_RTS,
+ PC11_PF_UART1_TXD,
+ PC12_PF_UART1_RXD,
+ /* UART2 */
+ PB28_PF_UART2_CTS,
+ PB29_PF_UART2_RTS,
+ PB30_PF_UART2_TXD,
+ PB31_PF_UART2_RXD,
+};
+
+/*
+ * The APF9328 can have up to 32MB NOR Flash
+ */
+static struct resource flash_resource = {
+ .start = MX1_CS0_PHYS,
+ .end = MX1_CS0_PHYS + SZ_32M - 1,
+ .flags = IORESOURCE_MEM,
+};
+
+static struct physmap_flash_data apf9328_flash_data = {
+ .width = 2,
+};
+
+static struct platform_device apf9328_flash_device = {
+ .name = "physmap-flash",
+ .id = 0,
+ .dev = {
+ .platform_data = &apf9328_flash_data,
+ },
+ .resource = &flash_resource,
+ .num_resources = 1,
+};
+
+/*
+ * APF9328 has a DM9000 Ethernet controller
+ */
+static struct dm9000_plat_data dm9000_setup = {
+ .flags = DM9000_PLATF_16BITONLY
+};
+
+static struct resource dm9000_resources[] = {
+ {
+ .start = MX1_CS4_PHYS + 0x00C00000,
+ .end = MX1_CS4_PHYS + 0x00C00001,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = MX1_CS4_PHYS + 0x00C00002,
+ .end = MX1_CS4_PHYS + 0x00C00003,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = IRQ_GPIOB(14),
+ .end = IRQ_GPIOB(14),
+ .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
+ },
+};
+
+static struct platform_device dm9000x_device = {
+ .name = "dm9000",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(dm9000_resources),
+ .resource = dm9000_resources,
+ .dev = {
+ .platform_data = &dm9000_setup,
+ }
+};
+
+/* --- SERIAL RESSOURCE --- */
+static const struct imxuart_platform_data uart0_pdata __initconst = {
+ .flags = 0,
+};
+
+static const struct imxuart_platform_data uart1_pdata __initconst = {
+ .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static struct platform_device *devices[] __initdata = {
+ &apf9328_flash_device,
+ &dm9000x_device,
+};
+
+static void __init apf9328_init(void)
+{
+ mxc_gpio_setup_multiple_pins(apf9328_pins,
+ ARRAY_SIZE(apf9328_pins),
+ "APF9328");
+
+ imx1_add_imx_uart0(&uart0_pdata);
+ imx1_add_imx_uart1(&uart1_pdata);
+
+ platform_add_devices(devices, ARRAY_SIZE(devices));
+}
+
+static void __init apf9328_timer_init(void)
+{
+ mx1_clocks_init(32768);
+}
+
+static struct sys_timer apf9328_timer = {
+ .init = apf9328_timer_init,
+};
+
+MACHINE_START(APF9328, "Armadeus APF9328")
+ /* Maintainer: Gwenhael Goavec-Merou, ARMadeus Systems */
+ .map_io = mx1_map_io,
+ .init_early = imx1_init_early,
+ .init_irq = mx1_init_irq,
+ .timer = &apf9328_timer,
+ .init_machine = apf9328_init,
+MACHINE_END
diff --git a/arch/arm/mach-imx/mach-armadillo5x0.c b/arch/arm/mach-imx/mach-armadillo5x0.c
new file mode 100644
index 0000000..ffb40ff
--- /dev/null
+++ b/arch/arm/mach-imx/mach-armadillo5x0.c
@@ -0,0 +1,565 @@
+/*
+ * armadillo5x0.c
+ *
+ * Copyright 2009 Alberto Panizzo <maramaopercheseimorto@gmail.com>
+ * updates in http://alberdroid.blogspot.com/
+ *
+ * Based on Atmark Techno, Inc. armadillo 500 BSP 2008
+ * Based on mx31ads.c and pcm037.c Great Work!
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
+ * MA 02110-1301, USA.
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/smsc911x.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/mtd/physmap.h>
+#include <linux/io.h>
+#include <linux/input.h>
+#include <linux/i2c.h>
+#include <linux/usb/otg.h>
+#include <linux/usb/ulpi.h>
+#include <linux/delay.h>
+
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/memory.h>
+#include <asm/mach/map.h>
+
+#include <mach/common.h>
+#include <mach/iomux-mx3.h>
+#include <mach/ulpi.h>
+
+#include "devices-imx31.h"
+#include "crmregs-imx31.h"
+
+static int armadillo5x0_pins[] = {
+ /* UART1 */
+ MX31_PIN_CTS1__CTS1,
+ MX31_PIN_RTS1__RTS1,
+ MX31_PIN_TXD1__TXD1,
+ MX31_PIN_RXD1__RXD1,
+ /* UART2 */
+ MX31_PIN_CTS2__CTS2,
+ MX31_PIN_RTS2__RTS2,
+ MX31_PIN_TXD2__TXD2,
+ MX31_PIN_RXD2__RXD2,
+ /* LAN9118_IRQ */
+ IOMUX_MODE(MX31_PIN_GPIO1_0, IOMUX_CONFIG_GPIO),
+ /* SDHC1 */
+ MX31_PIN_SD1_DATA3__SD1_DATA3,
+ MX31_PIN_SD1_DATA2__SD1_DATA2,
+ MX31_PIN_SD1_DATA1__SD1_DATA1,
+ MX31_PIN_SD1_DATA0__SD1_DATA0,
+ MX31_PIN_SD1_CLK__SD1_CLK,
+ MX31_PIN_SD1_CMD__SD1_CMD,
+ /* Framebuffer */
+ MX31_PIN_LD0__LD0,
+ MX31_PIN_LD1__LD1,
+ MX31_PIN_LD2__LD2,
+ MX31_PIN_LD3__LD3,
+ MX31_PIN_LD4__LD4,
+ MX31_PIN_LD5__LD5,
+ MX31_PIN_LD6__LD6,
+ MX31_PIN_LD7__LD7,
+ MX31_PIN_LD8__LD8,
+ MX31_PIN_LD9__LD9,
+ MX31_PIN_LD10__LD10,
+ MX31_PIN_LD11__LD11,
+ MX31_PIN_LD12__LD12,
+ MX31_PIN_LD13__LD13,
+ MX31_PIN_LD14__LD14,
+ MX31_PIN_LD15__LD15,
+ MX31_PIN_LD16__LD16,
+ MX31_PIN_LD17__LD17,
+ MX31_PIN_VSYNC3__VSYNC3,
+ MX31_PIN_HSYNC__HSYNC,
+ MX31_PIN_FPSHIFT__FPSHIFT,
+ MX31_PIN_DRDY0__DRDY0,
+ IOMUX_MODE(MX31_PIN_LCS1, IOMUX_CONFIG_GPIO), /*ADV7125_PSAVE*/
+ /* I2C2 */
+ MX31_PIN_CSPI2_MOSI__SCL,
+ MX31_PIN_CSPI2_MISO__SDA,
+ /* OTG */
+ MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
+ MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
+ MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
+ MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
+ MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
+ MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
+ MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
+ MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
+ MX31_PIN_USBOTG_CLK__USBOTG_CLK,
+ MX31_PIN_USBOTG_DIR__USBOTG_DIR,
+ MX31_PIN_USBOTG_NXT__USBOTG_NXT,
+ MX31_PIN_USBOTG_STP__USBOTG_STP,
+ /* USB host 2 */
+ IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC),
+ IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC),
+ IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC),
+ IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC),
+ IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC),
+ IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC),
+ IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC),
+ IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC),
+ IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC),
+ IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC),
+ IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC),
+ IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC),
+};
+
+/* USB */
+
+#define OTG_RESET IOMUX_TO_GPIO(MX31_PIN_STXD4)
+#define USBH2_RESET IOMUX_TO_GPIO(MX31_PIN_SCK6)
+#define USBH2_CS IOMUX_TO_GPIO(MX31_PIN_GPIO1_3)
+
+#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
+ PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
+
+static int usbotg_init(struct platform_device *pdev)
+{
+ int err;
+
+ mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG);
+
+ /* Chip already enabled by hardware */
+ /* OTG phy reset*/
+ err = gpio_request(OTG_RESET, "USB-OTG-RESET");
+ if (err) {
+ pr_err("Failed to request the usb otg reset gpio\n");
+ return err;
+ }
+
+ err = gpio_direction_output(OTG_RESET, 1/*HIGH*/);
+ if (err) {
+ pr_err("Failed to reset the usb otg phy\n");
+ goto otg_free_reset;
+ }
+
+ gpio_set_value(OTG_RESET, 0/*LOW*/);
+ mdelay(5);
+ gpio_set_value(OTG_RESET, 1/*HIGH*/);
+ mdelay(10);
+
+ return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED |
+ MXC_EHCI_INTERFACE_DIFF_UNI);
+
+otg_free_reset:
+ gpio_free(OTG_RESET);
+ return err;
+}
+
+static int usbh2_init(struct platform_device *pdev)
+{
+ int err;
+
+ mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG);
+
+ mxc_iomux_set_gpr(MUX_PGP_UH2, true);
+
+
+ /* Enable the chip */
+ err = gpio_request(USBH2_CS, "USB-H2-CS");
+ if (err) {
+ pr_err("Failed to request the usb host 2 CS gpio\n");
+ return err;
+ }
+
+ err = gpio_direction_output(USBH2_CS, 0/*Enabled*/);
+ if (err) {
+ pr_err("Failed to drive the usb host 2 CS gpio\n");
+ goto h2_free_cs;
+ }
+
+ /* H2 phy reset*/
+ err = gpio_request(USBH2_RESET, "USB-H2-RESET");
+ if (err) {
+ pr_err("Failed to request the usb host 2 reset gpio\n");
+ goto h2_free_cs;
+ }
+
+ err = gpio_direction_output(USBH2_RESET, 1/*HIGH*/);
+ if (err) {
+ pr_err("Failed to reset the usb host 2 phy\n");
+ goto h2_free_reset;
+ }
+
+ gpio_set_value(USBH2_RESET, 0/*LOW*/);
+ mdelay(5);
+ gpio_set_value(USBH2_RESET, 1/*HIGH*/);
+ mdelay(10);
+
+ return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED |
+ MXC_EHCI_INTERFACE_DIFF_UNI);
+
+h2_free_reset:
+ gpio_free(USBH2_RESET);
+h2_free_cs:
+ gpio_free(USBH2_CS);
+ return err;
+}
+
+static struct mxc_usbh_platform_data usbotg_pdata __initdata = {
+ .init = usbotg_init,
+ .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
+};
+
+static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
+ .init = usbh2_init,
+ .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
+};
+
+/* RTC over I2C*/
+#define ARMADILLO5X0_RTC_GPIO IOMUX_TO_GPIO(MX31_PIN_SRXD4)
+
+static struct i2c_board_info armadillo5x0_i2c_rtc = {
+ I2C_BOARD_INFO("s35390a", 0x30),
+};
+
+/* GPIO BUTTONS */
+static struct gpio_keys_button armadillo5x0_buttons[] = {
+ {
+ .code = KEY_ENTER, /*28*/
+ .gpio = IOMUX_TO_GPIO(MX31_PIN_SCLK0),
+ .active_low = 1,
+ .desc = "menu",
+ .wakeup = 1,
+ }, {
+ .code = KEY_BACK, /*158*/
+ .gpio = IOMUX_TO_GPIO(MX31_PIN_SRST0),
+ .active_low = 1,
+ .desc = "back",
+ .wakeup = 1,
+ }
+};
+
+static const struct gpio_keys_platform_data
+ armadillo5x0_button_data __initconst = {
+ .buttons = armadillo5x0_buttons,
+ .nbuttons = ARRAY_SIZE(armadillo5x0_buttons),
+};
+
+/*
+ * NAND Flash
+ */
+static const struct mxc_nand_platform_data
+armadillo5x0_nand_board_info __initconst = {
+ .width = 1,
+ .hw_ecc = 1,
+};
+
+/*
+ * MTD NOR Flash
+ */
+static struct mtd_partition armadillo5x0_nor_flash_partitions[] = {
+ {
+ .name = "nor.bootloader",
+ .offset = 0x00000000,
+ .size = 4*32*1024,
+ }, {
+ .name = "nor.kernel",
+ .offset = MTDPART_OFS_APPEND,
+ .size = 16*128*1024,
+ }, {
+ .name = "nor.userland",
+ .offset = MTDPART_OFS_APPEND,
+ .size = 110*128*1024,
+ }, {
+ .name = "nor.config",
+ .offset = MTDPART_OFS_APPEND,
+ .size = 1*128*1024,
+ },
+};
+
+static struct physmap_flash_data armadillo5x0_nor_flash_pdata = {
+ .width = 2,
+ .parts = armadillo5x0_nor_flash_partitions,
+ .nr_parts = ARRAY_SIZE(armadillo5x0_nor_flash_partitions),
+};
+
+static struct resource armadillo5x0_nor_flash_resource = {
+ .flags = IORESOURCE_MEM,
+ .start = MX31_CS0_BASE_ADDR,
+ .end = MX31_CS0_BASE_ADDR + SZ_64M - 1,
+};
+
+static struct platform_device armadillo5x0_nor_flash = {
+ .name = "physmap-flash",
+ .id = -1,
+ .num_resources = 1,
+ .resource = &armadillo5x0_nor_flash_resource,
+};
+
+/*
+ * FB support
+ */
+static const struct fb_videomode fb_modedb[] = {
+ { /* 640x480 @ 60 Hz */
+ .name = "CRT-VGA",
+ .refresh = 60,
+ .xres = 640,
+ .yres = 480,
+ .pixclock = 39721,
+ .left_margin = 35,
+ .right_margin = 115,
+ .upper_margin = 43,
+ .lower_margin = 1,
+ .hsync_len = 10,
+ .vsync_len = 1,
+ .sync = FB_SYNC_OE_ACT_HIGH,
+ .vmode = FB_VMODE_NONINTERLACED,
+ .flag = 0,
+ }, {/* 800x600 @ 56 Hz */
+ .name = "CRT-SVGA",
+ .refresh = 56,
+ .xres = 800,
+ .yres = 600,
+ .pixclock = 30000,
+ .left_margin = 30,
+ .right_margin = 108,
+ .upper_margin = 13,
+ .lower_margin = 10,
+ .hsync_len = 10,
+ .vsync_len = 1,
+ .sync = FB_SYNC_OE_ACT_HIGH | FB_SYNC_HOR_HIGH_ACT |
+ FB_SYNC_VERT_HIGH_ACT,
+ .vmode = FB_VMODE_NONINTERLACED,
+ .flag = 0,
+ },
+};
+
+static const struct ipu_platform_data mx3_ipu_data __initconst = {
+ .irq_base = MXC_IPU_IRQ_START,
+};
+
+static struct mx3fb_platform_data mx3fb_pdata __initdata = {
+ .name = "CRT-VGA",
+ .mode = fb_modedb,
+ .num_modes = ARRAY_SIZE(fb_modedb),
+};
+
+/*
+ * SDHC 1
+ * MMC support
+ */
+static int armadillo5x0_sdhc1_get_ro(struct device *dev)
+{
+ return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_ATA_RESET_B));
+}
+
+static int armadillo5x0_sdhc1_init(struct device *dev,
+ irq_handler_t detect_irq, void *data)
+{
+ int ret;
+ int gpio_det, gpio_wp;
+
+ gpio_det = IOMUX_TO_GPIO(MX31_PIN_ATA_DMACK);
+ gpio_wp = IOMUX_TO_GPIO(MX31_PIN_ATA_RESET_B);
+
+ ret = gpio_request(gpio_det, "sdhc-card-detect");
+ if (ret)
+ return ret;
+
+ gpio_direction_input(gpio_det);
+
+ ret = gpio_request(gpio_wp, "sdhc-write-protect");
+ if (ret)
+ goto err_gpio_free;
+
+ gpio_direction_input(gpio_wp);
+
+ /* When supported the trigger type have to be BOTH */
+ ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_ATA_DMACK), detect_irq,
+ IRQF_DISABLED | IRQF_TRIGGER_FALLING,
+ "sdhc-detect", data);
+
+ if (ret)
+ goto err_gpio_free_2;
+
+ return 0;
+
+err_gpio_free_2:
+ gpio_free(gpio_wp);
+
+err_gpio_free:
+ gpio_free(gpio_det);
+
+ return ret;
+
+}
+
+static void armadillo5x0_sdhc1_exit(struct device *dev, void *data)
+{
+ free_irq(IOMUX_TO_IRQ(MX31_PIN_ATA_DMACK), data);
+ gpio_free(IOMUX_TO_GPIO(MX31_PIN_ATA_DMACK));
+ gpio_free(IOMUX_TO_GPIO(MX31_PIN_ATA_RESET_B));
+}
+
+static const struct imxmmc_platform_data sdhc_pdata __initconst = {
+ .get_ro = armadillo5x0_sdhc1_get_ro,
+ .init = armadillo5x0_sdhc1_init,
+ .exit = armadillo5x0_sdhc1_exit,
+};
+
+/*
+ * SMSC 9118
+ * Network support
+ */
+static struct resource armadillo5x0_smc911x_resources[] = {
+ {
+ .start = MX31_CS3_BASE_ADDR,
+ .end = MX31_CS3_BASE_ADDR + SZ_32M - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = IOMUX_TO_IRQ(MX31_PIN_GPIO1_0),
+ .end = IOMUX_TO_IRQ(MX31_PIN_GPIO1_0),
+ .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
+ },
+};
+
+static struct smsc911x_platform_config smsc911x_info = {
+ .flags = SMSC911X_USE_16BIT,
+ .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
+ .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
+};
+
+static struct platform_device armadillo5x0_smc911x_device = {
+ .name = "smsc911x",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(armadillo5x0_smc911x_resources),
+ .resource = armadillo5x0_smc911x_resources,
+ .dev = {
+ .platform_data = &smsc911x_info,
+ },
+};
+
+/* UART device data */
+static const struct imxuart_platform_data uart_pdata __initconst = {
+ .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static struct platform_device *devices[] __initdata = {
+ &armadillo5x0_smc911x_device,
+};
+
+/*
+ * Perform board specific initializations
+ */
+static void __init armadillo5x0_init(void)
+{
+ mxc_iomux_setup_multiple_pins(armadillo5x0_pins,
+ ARRAY_SIZE(armadillo5x0_pins), "armadillo5x0");
+
+ platform_add_devices(devices, ARRAY_SIZE(devices));
+ imx_add_gpio_keys(&armadillo5x0_button_data);
+ imx31_add_imx_i2c1(NULL);
+
+ /* Register UART */
+ imx31_add_imx_uart0(&uart_pdata);
+ imx31_add_imx_uart1(&uart_pdata);
+
+ /* SMSC9118 IRQ pin */
+ gpio_direction_input(MX31_PIN_GPIO1_0);
+
+ /* Register SDHC */
+ imx31_add_mxc_mmc(0, &sdhc_pdata);
+
+ /* Register FB */
+ imx31_add_ipu_core(&mx3_ipu_data);
+ imx31_add_mx3_sdc_fb(&mx3fb_pdata);
+
+ /* Register NOR Flash */
+ mxc_register_device(&armadillo5x0_nor_flash,
+ &armadillo5x0_nor_flash_pdata);
+
+ /* Register NAND Flash */
+ imx31_add_mxc_nand(&armadillo5x0_nand_board_info);
+
+ /* set NAND page size to 2k if not configured via boot mode pins */
+ __raw_writel(__raw_readl(MXC_CCM_RCSR) | (1 << 30), MXC_CCM_RCSR);
+
+ /* RTC */
+ /* Get RTC IRQ and register the chip */
+ if (gpio_request(ARMADILLO5X0_RTC_GPIO, "rtc") == 0) {
+ if (gpio_direction_input(ARMADILLO5X0_RTC_GPIO) == 0)
+ armadillo5x0_i2c_rtc.irq = gpio_to_irq(ARMADILLO5X0_RTC_GPIO);
+ else
+ gpio_free(ARMADILLO5X0_RTC_GPIO);
+ }
+ if (armadillo5x0_i2c_rtc.irq == 0)
+ pr_warning("armadillo5x0_init: failed to get RTC IRQ\n");
+ i2c_register_board_info(1, &armadillo5x0_i2c_rtc, 1);
+
+ /* USB */
+
+ usbotg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
+ ULPI_OTG_DRVVBUS_EXT);
+ if (usbotg_pdata.otg)
+ imx31_add_mxc_ehci_otg(&usbotg_pdata);
+ usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
+ ULPI_OTG_DRVVBUS_EXT);
+ if (usbh2_pdata.otg)
+ imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
+}
+
+static void __init armadillo5x0_timer_init(void)
+{
+ mx31_clocks_init(26000000);
+}
+
+static struct sys_timer armadillo5x0_timer = {
+ .init = armadillo5x0_timer_init,
+};
+
+MACHINE_START(ARMADILLO5X0, "Armadillo-500")
+ /* Maintainer: Alberto Panizzo */
+ .boot_params = MX3x_PHYS_OFFSET + 0x100,
+ .map_io = mx31_map_io,
+ .init_early = imx31_init_early,
+ .init_irq = mx31_init_irq,
+ .timer = &armadillo5x0_timer,
+ .init_machine = armadillo5x0_init,
+MACHINE_END
diff --git a/arch/arm/mach-imx/mach-bug.c b/arch/arm/mach-imx/mach-bug.c
new file mode 100644
index 0000000..42e4f07
--- /dev/null
+++ b/arch/arm/mach-imx/mach-bug.c
@@ -0,0 +1,65 @@
+/*
+ * Copyright (C) 2000 Deep Blue Solutions Ltd
+ * Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2011 Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+
+#include <mach/iomux-mx3.h>
+#include <mach/hardware.h>
+#include <mach/common.h>
+
+#include <asm/mach/time.h>
+#include <asm/mach/arch.h>
+#include <asm/mach-types.h>
+
+#include "devices-imx31.h"
+
+static const struct imxuart_platform_data uart_pdata __initconst = {
+ .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static const unsigned int bug_pins[] __initconst = {
+ MX31_PIN_PC_RST__CTS5,
+ MX31_PIN_PC_VS2__RTS5,
+ MX31_PIN_PC_BVD2__TXD5,
+ MX31_PIN_PC_BVD1__RXD5,
+};
+
+static void __init bug_board_init(void)
+{
+ mxc_iomux_setup_multiple_pins(bug_pins,
+ ARRAY_SIZE(bug_pins), "uart-4");
+ imx31_add_imx_uart4(&uart_pdata);
+}
+
+static void __init bug_timer_init(void)
+{
+ mx31_clocks_init(26000000);
+}
+
+static struct sys_timer bug_timer = {
+ .init = bug_timer_init,
+};
+
+MACHINE_START(BUG, "BugLabs BUGBase")
+ .map_io = mx31_map_io,
+ .init_early = imx31_init_early,
+ .init_irq = mx31_init_irq,
+ .timer = &bug_timer,
+ .init_machine = bug_board_init,
+MACHINE_END
diff --git a/arch/arm/mach-imx/mach-cpuimx27.c b/arch/arm/mach-imx/mach-cpuimx27.c
index 759299b..46a2e41 100644
--- a/arch/arm/mach-imx/mach-cpuimx27.c
+++ b/arch/arm/mach-imx/mach-cpuimx27.c
@@ -38,7 +38,6 @@
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-mx27.h>
-#include <mach/mxc_nand.h>
#include <mach/ulpi.h>
#include "devices-imx27.h"
diff --git a/arch/arm/mach-imx/mach-cpuimx35.c b/arch/arm/mach-imx/mach-cpuimx35.c
new file mode 100644
index 0000000..3f8ef82
--- /dev/null
+++ b/arch/arm/mach-imx/mach-cpuimx35.c
@@ -0,0 +1,201 @@
+/*
+ * Copyright (C) 2010 Eric Benard - eric@eukrea.com
+ * Copyright (C) 2009 Sascha Hauer, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+#include <linux/memory.h>
+#include <linux/gpio.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <linux/i2c.h>
+#include <linux/i2c/tsc2007.h>
+#include <linux/usb/otg.h>
+#include <linux/usb/ulpi.h>
+#include <linux/i2c-gpio.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+
+#include <mach/eukrea-baseboards.h>
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/iomux-mx35.h>
+
+#include "devices-imx35.h"
+
+static const struct imxuart_platform_data uart_pdata __initconst = {
+ .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static const struct imxi2c_platform_data
+ eukrea_cpuimx35_i2c0_data __initconst = {
+ .bitrate = 100000,
+};
+
+static struct tsc2007_platform_data tsc2007_info = {
+ .model = 2007,
+ .x_plate_ohms = 180,
+};
+
+#define TSC2007_IRQGPIO IMX_GPIO_NR(3, 2)
+static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = {
+ {
+ I2C_BOARD_INFO("pcf8563", 0x51),
+ }, {
+ I2C_BOARD_INFO("tsc2007", 0x48),
+ .type = "tsc2007",
+ .platform_data = &tsc2007_info,
+ .irq = gpio_to_irq(TSC2007_IRQGPIO),
+ },
+};
+
+static iomux_v3_cfg_t eukrea_cpuimx35_pads[] = {
+ /* UART1 */
+ MX35_PAD_CTS1__UART1_CTS,
+ MX35_PAD_RTS1__UART1_RTS,
+ MX35_PAD_TXD1__UART1_TXD_MUX,
+ MX35_PAD_RXD1__UART1_RXD_MUX,
+ /* FEC */
+ MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
+ MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
+ MX35_PAD_FEC_RX_DV__FEC_RX_DV,
+ MX35_PAD_FEC_COL__FEC_COL,
+ MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
+ MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
+ MX35_PAD_FEC_TX_EN__FEC_TX_EN,
+ MX35_PAD_FEC_MDC__FEC_MDC,
+ MX35_PAD_FEC_MDIO__FEC_MDIO,
+ MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
+ MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
+ MX35_PAD_FEC_CRS__FEC_CRS,
+ MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
+ MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
+ MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
+ MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
+ MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
+ MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
+ /* I2C1 */
+ MX35_PAD_I2C1_CLK__I2C1_SCL,
+ MX35_PAD_I2C1_DAT__I2C1_SDA,
+ /* TSC2007 IRQ */
+ MX35_PAD_ATA_DA2__GPIO3_2,
+};
+
+static const struct mxc_nand_platform_data
+ eukrea_cpuimx35_nand_board_info __initconst = {
+ .width = 1,
+ .hw_ecc = 1,
+ .flash_bbt = 1,
+};
+
+static int eukrea_cpuimx35_otg_init(struct platform_device *pdev)
+{
+ return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
+}
+
+static const struct mxc_usbh_platform_data otg_pdata __initconst = {
+ .init = eukrea_cpuimx35_otg_init,
+ .portsc = MXC_EHCI_MODE_UTMI,
+};
+
+static int eukrea_cpuimx35_usbh1_init(struct platform_device *pdev)
+{
+ return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_SINGLE_UNI |
+ MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN);
+}
+
+static const struct mxc_usbh_platform_data usbh1_pdata __initconst = {
+ .init = eukrea_cpuimx35_usbh1_init,
+ .portsc = MXC_EHCI_MODE_SERIAL,
+};
+
+static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
+ .operating_mode = FSL_USB2_DR_DEVICE,
+ .phy_mode = FSL_USB2_PHY_UTMI,
+ .workaround = FLS_USB2_WORKAROUND_ENGCM09152,
+};
+
+static int otg_mode_host;
+
+static int __init eukrea_cpuimx35_otg_mode(char *options)
+{
+ if (!strcmp(options, "host"))
+ otg_mode_host = 1;
+ else if (!strcmp(options, "device"))
+ otg_mode_host = 0;
+ else
+ pr_info("otg_mode neither \"host\" nor \"device\". "
+ "Defaulting to device\n");
+ return 0;
+}
+__setup("otg_mode=", eukrea_cpuimx35_otg_mode);
+
+/*
+ * Board specific initialization.
+ */
+static void __init eukrea_cpuimx35_init(void)
+{
+ mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx35_pads,
+ ARRAY_SIZE(eukrea_cpuimx35_pads));
+
+ imx35_add_fec(NULL);
+ imx35_add_imx2_wdt(NULL);
+
+ imx35_add_imx_uart0(&uart_pdata);
+ imx35_add_mxc_nand(&eukrea_cpuimx35_nand_board_info);
+
+ i2c_register_board_info(0, eukrea_cpuimx35_i2c_devices,
+ ARRAY_SIZE(eukrea_cpuimx35_i2c_devices));
+ imx35_add_imx_i2c0(&eukrea_cpuimx35_i2c0_data);
+
+ if (otg_mode_host)
+ imx35_add_mxc_ehci_otg(&otg_pdata);
+ else
+ imx35_add_fsl_usb2_udc(&otg_device_pdata);
+
+ imx35_add_mxc_ehci_hs(&usbh1_pdata);
+
+#ifdef CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD
+ eukrea_mbimxsd35_baseboard_init();
+#endif
+}
+
+static void __init eukrea_cpuimx35_timer_init(void)
+{
+ mx35_clocks_init();
+}
+
+struct sys_timer eukrea_cpuimx35_timer = {
+ .init = eukrea_cpuimx35_timer_init,
+};
+
+MACHINE_START(EUKREA_CPUIMX35, "Eukrea CPUIMX35")
+ /* Maintainer: Eukrea Electromatique */
+ .boot_params = MX3x_PHYS_OFFSET + 0x100,
+ .map_io = mx35_map_io,
+ .init_early = imx35_init_early,
+ .init_irq = mx35_init_irq,
+ .timer = &eukrea_cpuimx35_timer,
+ .init_machine = eukrea_cpuimx35_init,
+MACHINE_END
diff --git a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
index 9da8d18..148cff2 100644
--- a/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
+++ b/arch/arm/mach-imx/mach-eukrea_cpuimx25.c
@@ -36,8 +36,6 @@
#include <asm/mach/map.h>
#include <mach/common.h>
#include <mach/mx25.h>
-#include <mach/mxc_nand.h>
-#include <mach/imxfb.h>
#include <mach/iomux-mx25.h>
#include "devices-imx25.h"
diff --git a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
index d7e0d21..7ae43b1 100644
--- a/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
+++ b/arch/arm/mach-imx/mach-imx27_visstrim_m10.c
@@ -27,7 +27,6 @@
#include <linux/mtd/physmap.h>
#include <linux/i2c.h>
#include <linux/i2c/pca953x.h>
-#include <linux/gpio_keys.h>
#include <linux/input.h>
#include <linux/gpio.h>
#include <linux/delay.h>
@@ -130,19 +129,12 @@
}
};
-static struct gpio_keys_platform_data visstrim_gpio_keys_platform_data = {
+static const struct gpio_keys_platform_data
+ visstrim_gpio_keys_platform_data __initconst = {
.buttons = visstrim_gpio_keys,
.nbuttons = ARRAY_SIZE(visstrim_gpio_keys),
};
-static struct platform_device visstrim_gpio_keys_device = {
- .name = "gpio-keys",
- .id = -1,
- .dev = {
- .platform_data = &visstrim_gpio_keys_platform_data,
- },
-};
-
/* Visstrim_SM10 has a microSD slot connected to sdhc1 */
static int visstrim_m10_sdhc1_init(struct device *dev,
irq_handler_t detect_irq, void *data)
@@ -186,7 +178,6 @@
};
static struct platform_device *platform_devices[] __initdata = {
- &visstrim_gpio_keys_device,
&visstrim_m10_nor_mtd_device,
};
@@ -255,6 +246,7 @@
imx27_add_mxc_mmc(0, &visstrim_m10_sdhc_pdata);
imx27_add_mxc_ehci_otg(&visstrim_m10_usbotg_pdata);
imx27_add_fec(NULL);
+ imx_add_gpio_keys(&visstrim_gpio_keys_platform_data);
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
}
diff --git a/arch/arm/mach-imx/mach-kzm_arm11_01.c b/arch/arm/mach-imx/mach-kzm_arm11_01.c
new file mode 100644
index 0000000..1ecae20
--- /dev/null
+++ b/arch/arm/mach-imx/mach-kzm_arm11_01.c
@@ -0,0 +1,278 @@
+/*
+ * KZM-ARM11-01 support
+ * Copyright (C) 2009 Yoichi Yuasa <yuasa@linux-mips.org>
+ *
+ * based on code for MX31ADS,
+ * Copyright (C) 2000 Deep Blue Solutions Ltd
+ * Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/gpio.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/serial_8250.h>
+#include <linux/smsc911x.h>
+#include <linux/types.h>
+
+#include <asm/irq.h>
+#include <asm/mach-types.h>
+#include <asm/memory.h>
+#include <asm/setup.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/irq.h>
+#include <asm/mach/map.h>
+#include <asm/mach/time.h>
+
+#include <mach/clock.h>
+#include <mach/common.h>
+#include <mach/iomux-mx3.h>
+
+#include "devices-imx31.h"
+
+#define KZM_ARM11_IO_ADDRESS(x) (IOMEM( \
+ IMX_IO_P2V_MODULE(x, MX31_CS4) ?: \
+ IMX_IO_P2V_MODULE(x, MX31_CS5)) ?: \
+ MX31_IO_ADDRESS(x))
+
+/*
+ * KZM-ARM11-01 Board Control Registers on FPGA
+ */
+#define KZM_ARM11_CTL1 (MX31_CS4_BASE_ADDR + 0x1000)
+#define KZM_ARM11_CTL2 (MX31_CS4_BASE_ADDR + 0x1001)
+#define KZM_ARM11_RSW1 (MX31_CS4_BASE_ADDR + 0x1002)
+#define KZM_ARM11_BACK_LIGHT (MX31_CS4_BASE_ADDR + 0x1004)
+#define KZM_ARM11_FPGA_REV (MX31_CS4_BASE_ADDR + 0x1008)
+#define KZM_ARM11_7SEG_LED (MX31_CS4_BASE_ADDR + 0x1010)
+#define KZM_ARM11_LEDS (MX31_CS4_BASE_ADDR + 0x1020)
+#define KZM_ARM11_DIPSW2 (MX31_CS4_BASE_ADDR + 0x1003)
+
+/*
+ * External UART for touch panel on FPGA
+ */
+#define KZM_ARM11_16550 (MX31_CS4_BASE_ADDR + 0x1050)
+
+#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
+/*
+ * KZM-ARM11-01 has an external UART on FPGA
+ */
+static struct plat_serial8250_port serial_platform_data[] = {
+ {
+ .membase = KZM_ARM11_IO_ADDRESS(KZM_ARM11_16550),
+ .mapbase = KZM_ARM11_16550,
+ .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_1),
+ .irqflags = IRQ_TYPE_EDGE_RISING,
+ .uartclk = 14745600,
+ .regshift = 0,
+ .iotype = UPIO_MEM,
+ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
+ UPF_BUGGY_UART,
+ },
+ {},
+};
+
+static struct resource serial8250_resources[] = {
+ {
+ .start = KZM_ARM11_16550,
+ .end = KZM_ARM11_16550 + 0x10,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = IOMUX_TO_IRQ(MX31_PIN_GPIO1_1),
+ .end = IOMUX_TO_IRQ(MX31_PIN_GPIO1_1),
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device serial_device = {
+ .name = "serial8250",
+ .id = PLAT8250_DEV_PLATFORM,
+ .dev = {
+ .platform_data = serial_platform_data,
+ },
+ .num_resources = ARRAY_SIZE(serial8250_resources),
+ .resource = serial8250_resources,
+};
+
+static int __init kzm_init_ext_uart(void)
+{
+ u8 tmp;
+
+ /*
+ * GPIO 1-1: external UART interrupt line
+ */
+ mxc_iomux_mode(IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO));
+ gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1), "ext-uart-int");
+ gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
+
+ /*
+ * Unmask UART interrupt
+ */
+ tmp = __raw_readb(KZM_ARM11_IO_ADDRESS(KZM_ARM11_CTL1));
+ tmp |= 0x2;
+ __raw_writeb(tmp, KZM_ARM11_IO_ADDRESS(KZM_ARM11_CTL1));
+
+ return platform_device_register(&serial_device);
+}
+#else
+static inline int kzm_init_ext_uart(void)
+{
+ return 0;
+}
+#endif
+
+/*
+ * SMSC LAN9118
+ */
+#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
+static struct smsc911x_platform_config kzm_smsc9118_config = {
+ .phy_interface = PHY_INTERFACE_MODE_MII,
+ .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
+ .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
+ .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
+};
+
+static struct resource kzm_smsc9118_resources[] = {
+ {
+ .start = MX31_CS5_BASE_ADDR,
+ .end = MX31_CS5_BASE_ADDR + SZ_128K - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = IOMUX_TO_IRQ(MX31_PIN_GPIO1_2),
+ .end = IOMUX_TO_IRQ(MX31_PIN_GPIO1_2),
+ .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
+ },
+};
+
+static struct platform_device kzm_smsc9118_device = {
+ .name = "smsc911x",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(kzm_smsc9118_resources),
+ .resource = kzm_smsc9118_resources,
+ .dev = {
+ .platform_data = &kzm_smsc9118_config,
+ },
+};
+
+static int __init kzm_init_smsc9118(void)
+{
+ /*
+ * GPIO 1-2: SMSC9118 interrupt line
+ */
+ mxc_iomux_mode(IOMUX_MODE(MX31_PIN_GPIO1_2, IOMUX_CONFIG_GPIO));
+ gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2), "smsc9118-int");
+ gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2));
+
+ return platform_device_register(&kzm_smsc9118_device);
+}
+#else
+static inline int kzm_init_smsc9118(void)
+{
+ return 0;
+}
+#endif
+
+#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
+static const struct imxuart_platform_data uart_pdata __initconst = {
+ .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static void __init kzm_init_imx_uart(void)
+{
+ imx31_add_imx_uart0(&uart_pdata);
+ imx31_add_imx_uart1(&uart_pdata);
+}
+#else
+static inline void kzm_init_imx_uart(void)
+{
+}
+#endif
+
+static int kzm_pins[] __initdata = {
+ MX31_PIN_CTS1__CTS1,
+ MX31_PIN_RTS1__RTS1,
+ MX31_PIN_TXD1__TXD1,
+ MX31_PIN_RXD1__RXD1,
+ MX31_PIN_DCD_DCE1__DCD_DCE1,
+ MX31_PIN_RI_DCE1__RI_DCE1,
+ MX31_PIN_DSR_DCE1__DSR_DCE1,
+ MX31_PIN_DTR_DCE1__DTR_DCE1,
+ MX31_PIN_CTS2__CTS2,
+ MX31_PIN_RTS2__RTS2,
+ MX31_PIN_TXD2__TXD2,
+ MX31_PIN_RXD2__RXD2,
+ MX31_PIN_DCD_DTE1__DCD_DTE2,
+ MX31_PIN_RI_DTE1__RI_DTE2,
+ MX31_PIN_DSR_DTE1__DSR_DTE2,
+ MX31_PIN_DTR_DTE1__DTR_DTE2,
+};
+
+/*
+ * Board specific initialization.
+ */
+static void __init kzm_board_init(void)
+{
+ mxc_iomux_setup_multiple_pins(kzm_pins,
+ ARRAY_SIZE(kzm_pins), "kzm");
+ kzm_init_ext_uart();
+ kzm_init_smsc9118();
+ kzm_init_imx_uart();
+
+ pr_info("Clock input source is 26MHz\n");
+}
+
+/*
+ * This structure defines static mappings for the kzm-arm11-01 board.
+ */
+static struct map_desc kzm_io_desc[] __initdata = {
+ {
+ .virtual = MX31_CS4_BASE_ADDR_VIRT,
+ .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
+ .length = MX31_CS4_SIZE,
+ .type = MT_DEVICE
+ },
+ {
+ .virtual = MX31_CS5_BASE_ADDR_VIRT,
+ .pfn = __phys_to_pfn(MX31_CS5_BASE_ADDR),
+ .length = MX31_CS5_SIZE,
+ .type = MT_DEVICE
+ },
+};
+
+/*
+ * Set up static virtual mappings.
+ */
+static void __init kzm_map_io(void)
+{
+ mx31_map_io();
+ iotable_init(kzm_io_desc, ARRAY_SIZE(kzm_io_desc));
+}
+
+static void __init kzm_timer_init(void)
+{
+ mx31_clocks_init(26000000);
+}
+
+static struct sys_timer kzm_timer = {
+ .init = kzm_timer_init,
+};
+
+MACHINE_START(KZM_ARM11_01, "Kyoto Microcomputer Co., Ltd. KZM-ARM11-01")
+ .boot_params = MX3x_PHYS_OFFSET + 0x100,
+ .map_io = kzm_map_io,
+ .init_early = imx31_init_early,
+ .init_irq = mx31_init_irq,
+ .timer = &kzm_timer,
+ .init_machine = kzm_board_init,
+MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx1ads.c b/arch/arm/mach-imx/mach-mx1ads.c
index 47cf56a..38ec5cb 100644
--- a/arch/arm/mach-imx/mach-mx1ads.c
+++ b/arch/arm/mach-imx/mach-mx1ads.c
@@ -25,7 +25,6 @@
#include <mach/common.h>
#include <mach/hardware.h>
-#include <mach/i2c.h>
#include <mach/iomux-mx1.h>
#include <mach/irqs.h>
diff --git a/arch/arm/mach-imx/mach-mx21ads.c b/arch/arm/mach-imx/mach-mx21ads.c
index fa52a10..74ac889 100644
--- a/arch/arm/mach-imx/mach-mx21ads.c
+++ b/arch/arm/mach-imx/mach-mx21ads.c
@@ -25,7 +25,6 @@
#include <asm/mach/time.h>
#include <asm/mach/map.h>
#include <mach/iomux-mx21.h>
-#include <mach/mxc_nand.h>
#include "devices-imx21.h"
diff --git a/arch/arm/mach-imx/mach-mx25_3ds.c b/arch/arm/mach-imx/mach-mx25_3ds.c
index 06da438..58ea3fd 100644
--- a/arch/arm/mach-imx/mach-mx25_3ds.c
+++ b/arch/arm/mach-imx/mach-mx25_3ds.c
@@ -29,7 +29,6 @@
#include <linux/irq.h>
#include <linux/gpio.h>
#include <linux/platform_device.h>
-#include <linux/input/matrix_keypad.h>
#include <linux/usb/otg.h>
#include <mach/hardware.h>
@@ -103,6 +102,8 @@
MX25_PAD_SD1_DATA1__SD1_DATA1,
MX25_PAD_SD1_DATA2__SD1_DATA2,
MX25_PAD_SD1_DATA3__SD1_DATA3,
+ MX25_PAD_A14__GPIO_2_0, /* WriteProtect */
+ MX25_PAD_A15__GPIO_2_1, /* CardDetect */
/* I2C1 */
MX25_PAD_I2C1_CLK__I2C1_CLK,
@@ -208,6 +209,14 @@
.bitrate = 100000,
};
+#define SD1_GPIO_WP IMX_GPIO_NR(2, 0)
+#define SD1_GPIO_CD IMX_GPIO_NR(2, 1)
+
+static const struct esdhc_platform_data mx25pdk_esdhc_pdata __initconst = {
+ .wp_gpio = SD1_GPIO_WP,
+ .cd_gpio = SD1_GPIO_CD,
+};
+
static void __init mx25pdk_init(void)
{
mxc_iomux_v3_setup_multiple_pads(mx25pdk_pads,
@@ -225,7 +234,7 @@
imx25_add_fec(&mx25_fec_pdata);
imx25_add_imx_keypad(&mx25pdk_keymap_data);
- imx25_add_sdhci_esdhc_imx(0, NULL);
+ imx25_add_sdhci_esdhc_imx(0, &mx25pdk_esdhc_pdata);
imx25_add_imx_i2c0(&mx25_3ds_i2c0_data);
}
diff --git a/arch/arm/mach-imx/mach-mx27ads.c b/arch/arm/mach-imx/mach-mx27ads.c
index 367d1e4..1db7950 100644
--- a/arch/arm/mach-imx/mach-mx27ads.c
+++ b/arch/arm/mach-imx/mach-mx27ads.c
@@ -29,7 +29,6 @@
#include <asm/mach/map.h>
#include <mach/gpio.h>
#include <mach/iomux-mx27.h>
-#include <mach/mxc_nand.h>
#include "devices-imx27.h"
diff --git a/arch/arm/mach-imx/mach-mx31_3ds.c b/arch/arm/mach-imx/mach-mx31_3ds.c
new file mode 100644
index 0000000..9b98244
--- /dev/null
+++ b/arch/arm/mach-imx/mach-mx31_3ds.c
@@ -0,0 +1,771 @@
+/*
+ * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/delay.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/irq.h>
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+#include <linux/mfd/mc13783.h>
+#include <linux/spi/spi.h>
+#include <linux/spi/l4f00242t03.h>
+#include <linux/regulator/machine.h>
+#include <linux/usb/otg.h>
+#include <linux/usb/ulpi.h>
+#include <linux/memblock.h>
+
+#include <media/soc_camera.h>
+
+#include <mach/hardware.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/memory.h>
+#include <asm/mach/map.h>
+#include <mach/common.h>
+#include <mach/iomux-mx3.h>
+#include <mach/3ds_debugboard.h>
+#include <mach/ulpi.h>
+
+#include "devices-imx31.h"
+
+/* CPLD IRQ line for external uart, external ethernet etc */
+#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_1)
+
+static int mx31_3ds_pins[] = {
+ /* UART1 */
+ MX31_PIN_CTS1__CTS1,
+ MX31_PIN_RTS1__RTS1,
+ MX31_PIN_TXD1__TXD1,
+ MX31_PIN_RXD1__RXD1,
+ IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO),
+ /*SPI0*/
+ MX31_PIN_CSPI1_SCLK__SCLK,
+ MX31_PIN_CSPI1_MOSI__MOSI,
+ MX31_PIN_CSPI1_MISO__MISO,
+ MX31_PIN_CSPI1_SPI_RDY__SPI_RDY,
+ MX31_PIN_CSPI1_SS2__SS2, /* CS for LCD */
+ /* SPI 1 */
+ MX31_PIN_CSPI2_SCLK__SCLK,
+ MX31_PIN_CSPI2_MOSI__MOSI,
+ MX31_PIN_CSPI2_MISO__MISO,
+ MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
+ MX31_PIN_CSPI2_SS0__SS0,
+ MX31_PIN_CSPI2_SS2__SS2, /*CS for MC13783 */
+ /* MC13783 IRQ */
+ IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO),
+ /* USB OTG reset */
+ IOMUX_MODE(MX31_PIN_USB_PWR, IOMUX_CONFIG_GPIO),
+ /* USB OTG */
+ MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
+ MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
+ MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
+ MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
+ MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
+ MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
+ MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
+ MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
+ MX31_PIN_USBOTG_CLK__USBOTG_CLK,
+ MX31_PIN_USBOTG_DIR__USBOTG_DIR,
+ MX31_PIN_USBOTG_NXT__USBOTG_NXT,
+ MX31_PIN_USBOTG_STP__USBOTG_STP,
+ /*Keyboard*/
+ MX31_PIN_KEY_ROW0_KEY_ROW0,
+ MX31_PIN_KEY_ROW1_KEY_ROW1,
+ MX31_PIN_KEY_ROW2_KEY_ROW2,
+ MX31_PIN_KEY_COL0_KEY_COL0,
+ MX31_PIN_KEY_COL1_KEY_COL1,
+ MX31_PIN_KEY_COL2_KEY_COL2,
+ MX31_PIN_KEY_COL3_KEY_COL3,
+ /* USB Host 2 */
+ IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC),
+ IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC),
+ IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC),
+ IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC),
+ IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC),
+ IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC),
+ IOMUX_MODE(MX31_PIN_PC_VS2, IOMUX_CONFIG_ALT1),
+ IOMUX_MODE(MX31_PIN_PC_BVD1, IOMUX_CONFIG_ALT1),
+ IOMUX_MODE(MX31_PIN_PC_BVD2, IOMUX_CONFIG_ALT1),
+ IOMUX_MODE(MX31_PIN_PC_RST, IOMUX_CONFIG_ALT1),
+ IOMUX_MODE(MX31_PIN_IOIS16, IOMUX_CONFIG_ALT1),
+ IOMUX_MODE(MX31_PIN_PC_RW_B, IOMUX_CONFIG_ALT1),
+ /* USB Host2 reset */
+ IOMUX_MODE(MX31_PIN_USB_BYP, IOMUX_CONFIG_GPIO),
+ /* I2C1 */
+ MX31_PIN_I2C_CLK__I2C1_SCL,
+ MX31_PIN_I2C_DAT__I2C1_SDA,
+ /* SDHC1 */
+ MX31_PIN_SD1_DATA3__SD1_DATA3,
+ MX31_PIN_SD1_DATA2__SD1_DATA2,
+ MX31_PIN_SD1_DATA1__SD1_DATA1,
+ MX31_PIN_SD1_DATA0__SD1_DATA0,
+ MX31_PIN_SD1_CLK__SD1_CLK,
+ MX31_PIN_SD1_CMD__SD1_CMD,
+ MX31_PIN_GPIO3_1__GPIO3_1, /* Card detect */
+ MX31_PIN_GPIO3_0__GPIO3_0, /* OE */
+ /* Framebuffer */
+ MX31_PIN_LD0__LD0,
+ MX31_PIN_LD1__LD1,
+ MX31_PIN_LD2__LD2,
+ MX31_PIN_LD3__LD3,
+ MX31_PIN_LD4__LD4,
+ MX31_PIN_LD5__LD5,
+ MX31_PIN_LD6__LD6,
+ MX31_PIN_LD7__LD7,
+ MX31_PIN_LD8__LD8,
+ MX31_PIN_LD9__LD9,
+ MX31_PIN_LD10__LD10,
+ MX31_PIN_LD11__LD11,
+ MX31_PIN_LD12__LD12,
+ MX31_PIN_LD13__LD13,
+ MX31_PIN_LD14__LD14,
+ MX31_PIN_LD15__LD15,
+ MX31_PIN_LD16__LD16,
+ MX31_PIN_LD17__LD17,
+ MX31_PIN_VSYNC3__VSYNC3,
+ MX31_PIN_HSYNC__HSYNC,
+ MX31_PIN_FPSHIFT__FPSHIFT,
+ MX31_PIN_CONTRAST__CONTRAST,
+ /* CSI */
+ MX31_PIN_CSI_D6__CSI_D6,
+ MX31_PIN_CSI_D7__CSI_D7,
+ MX31_PIN_CSI_D8__CSI_D8,
+ MX31_PIN_CSI_D9__CSI_D9,
+ MX31_PIN_CSI_D10__CSI_D10,
+ MX31_PIN_CSI_D11__CSI_D11,
+ MX31_PIN_CSI_D12__CSI_D12,
+ MX31_PIN_CSI_D13__CSI_D13,
+ MX31_PIN_CSI_D14__CSI_D14,
+ MX31_PIN_CSI_D15__CSI_D15,
+ MX31_PIN_CSI_HSYNC__CSI_HSYNC,
+ MX31_PIN_CSI_MCLK__CSI_MCLK,
+ MX31_PIN_CSI_PIXCLK__CSI_PIXCLK,
+ MX31_PIN_CSI_VSYNC__CSI_VSYNC,
+ MX31_PIN_CSI_D5__GPIO3_5, /* CMOS PWDN */
+ IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_GPIO), /* CMOS reset */
+};
+
+/*
+ * Camera support
+ */
+static phys_addr_t mx3_camera_base __initdata;
+#define MX31_3DS_CAMERA_BUF_SIZE SZ_8M
+
+#define MX31_3DS_GPIO_CAMERA_PW IOMUX_TO_GPIO(MX31_PIN_CSI_D5)
+#define MX31_3DS_GPIO_CAMERA_RST IOMUX_TO_GPIO(MX31_PIN_RI_DTE1)
+
+static struct gpio mx31_3ds_camera_gpios[] = {
+ { MX31_3DS_GPIO_CAMERA_PW, GPIOF_OUT_INIT_HIGH, "camera-power" },
+ { MX31_3DS_GPIO_CAMERA_RST, GPIOF_OUT_INIT_HIGH, "camera-reset" },
+};
+
+static const struct mx3_camera_pdata mx31_3ds_camera_pdata __initconst = {
+ .flags = MX3_CAMERA_DATAWIDTH_10,
+ .mclk_10khz = 2600,
+};
+
+static int __init mx31_3ds_init_camera(void)
+{
+ int dma, ret = -ENOMEM;
+ struct platform_device *pdev =
+ imx31_alloc_mx3_camera(&mx31_3ds_camera_pdata);
+
+ if (IS_ERR(pdev))
+ return PTR_ERR(pdev);
+
+ if (!mx3_camera_base)
+ goto err;
+
+ dma = dma_declare_coherent_memory(&pdev->dev,
+ mx3_camera_base, mx3_camera_base,
+ MX31_3DS_CAMERA_BUF_SIZE,
+ DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
+
+ if (!(dma & DMA_MEMORY_MAP))
+ goto err;
+
+ ret = platform_device_add(pdev);
+ if (ret)
+err:
+ platform_device_put(pdev);
+
+ return ret;
+}
+
+static int mx31_3ds_camera_power(struct device *dev, int on)
+{
+ /* enable or disable the camera */
+ pr_debug("%s: %s the camera\n", __func__, on ? "ENABLE" : "DISABLE");
+ gpio_set_value(MX31_3DS_GPIO_CAMERA_PW, on ? 0 : 1);
+
+ if (!on)
+ goto out;
+
+ /* If enabled, give a reset impulse */
+ gpio_set_value(MX31_3DS_GPIO_CAMERA_RST, 0);
+ msleep(20);
+ gpio_set_value(MX31_3DS_GPIO_CAMERA_RST, 1);
+ msleep(100);
+
+out:
+ return 0;
+}
+
+static struct i2c_board_info mx31_3ds_i2c_camera = {
+ I2C_BOARD_INFO("ov2640", 0x30),
+};
+
+static struct regulator_bulk_data mx31_3ds_camera_regs[] = {
+ { .supply = "cmos_vcore" },
+ { .supply = "cmos_2v8" },
+};
+
+static struct soc_camera_link iclink_ov2640 = {
+ .bus_id = 0,
+ .board_info = &mx31_3ds_i2c_camera,
+ .i2c_adapter_id = 0,
+ .power = mx31_3ds_camera_power,
+ .regulators = mx31_3ds_camera_regs,
+ .num_regulators = ARRAY_SIZE(mx31_3ds_camera_regs),
+};
+
+static struct platform_device mx31_3ds_ov2640 = {
+ .name = "soc-camera-pdrv",
+ .id = 0,
+ .dev = {
+ .platform_data = &iclink_ov2640,
+ },
+};
+
+/*
+ * FB support
+ */
+static const struct fb_videomode fb_modedb[] = {
+ { /* 480x640 @ 60 Hz */
+ .name = "Epson-VGA",
+ .refresh = 60,
+ .xres = 480,
+ .yres = 640,
+ .pixclock = 41701,
+ .left_margin = 20,
+ .right_margin = 41,
+ .upper_margin = 10,
+ .lower_margin = 5,
+ .hsync_len = 20,
+ .vsync_len = 10,
+ .sync = FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT,
+ .vmode = FB_VMODE_NONINTERLACED,
+ .flag = 0,
+ },
+};
+
+static struct ipu_platform_data mx3_ipu_data = {
+ .irq_base = MXC_IPU_IRQ_START,
+};
+
+static struct mx3fb_platform_data mx3fb_pdata __initdata = {
+ .name = "Epson-VGA",
+ .mode = fb_modedb,
+ .num_modes = ARRAY_SIZE(fb_modedb),
+};
+
+/* LCD */
+static struct l4f00242t03_pdata mx31_3ds_l4f00242t03_pdata = {
+ .reset_gpio = IOMUX_TO_GPIO(MX31_PIN_LCS1),
+ .data_enable_gpio = IOMUX_TO_GPIO(MX31_PIN_SER_RS),
+ .core_supply = "lcd_2v8",
+ .io_supply = "vdd_lcdio",
+};
+
+/*
+ * Support for SD card slot in personality board
+ */
+#define MX31_3DS_GPIO_SDHC1_CD IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)
+#define MX31_3DS_GPIO_SDHC1_BE IOMUX_TO_GPIO(MX31_PIN_GPIO3_0)
+
+static struct gpio mx31_3ds_sdhc1_gpios[] = {
+ { MX31_3DS_GPIO_SDHC1_CD, GPIOF_IN, "sdhc1-card-detect" },
+ { MX31_3DS_GPIO_SDHC1_BE, GPIOF_OUT_INIT_LOW, "sdhc1-bus-en" },
+};
+
+static int mx31_3ds_sdhc1_init(struct device *dev,
+ irq_handler_t detect_irq,
+ void *data)
+{
+ int ret;
+
+ ret = gpio_request_array(mx31_3ds_sdhc1_gpios,
+ ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
+ if (ret) {
+ pr_warning("Unable to request the SD/MMC GPIOs.\n");
+ return ret;
+ }
+
+ ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
+ detect_irq, IRQF_DISABLED |
+ IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
+ "sdhc1-detect", data);
+ if (ret) {
+ pr_warning("Unable to request the SD/MMC card-detect IRQ.\n");
+ goto gpio_free;
+ }
+
+ return 0;
+
+gpio_free:
+ gpio_free_array(mx31_3ds_sdhc1_gpios,
+ ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
+ return ret;
+}
+
+static void mx31_3ds_sdhc1_exit(struct device *dev, void *data)
+{
+ free_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO3_1), data);
+ gpio_free_array(mx31_3ds_sdhc1_gpios,
+ ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
+}
+
+static void mx31_3ds_sdhc1_setpower(struct device *dev, unsigned int vdd)
+{
+ /*
+ * While the voltage stuff is done by the driver, activate the
+ * Buffer Enable Pin only if there is a card in slot to fix the card
+ * voltage issue caused by bi-directional chip TXB0108 on 3Stack.
+ * Done here because at this stage we have for sure a debounced value
+ * of the presence of the card, showed by the value of vdd.
+ * 7 == ilog2(MMC_VDD_165_195)
+ */
+ if (vdd > 7)
+ gpio_set_value(MX31_3DS_GPIO_SDHC1_BE, 1);
+ else
+ gpio_set_value(MX31_3DS_GPIO_SDHC1_BE, 0);
+}
+
+static struct imxmmc_platform_data sdhc1_pdata = {
+ .init = mx31_3ds_sdhc1_init,
+ .exit = mx31_3ds_sdhc1_exit,
+ .setpower = mx31_3ds_sdhc1_setpower,
+};
+
+/*
+ * Matrix keyboard
+ */
+
+static const uint32_t mx31_3ds_keymap[] = {
+ KEY(0, 0, KEY_UP),
+ KEY(0, 1, KEY_DOWN),
+ KEY(1, 0, KEY_RIGHT),
+ KEY(1, 1, KEY_LEFT),
+ KEY(1, 2, KEY_ENTER),
+ KEY(2, 0, KEY_F6),
+ KEY(2, 1, KEY_F8),
+ KEY(2, 2, KEY_F9),
+ KEY(2, 3, KEY_F10),
+};
+
+static const struct matrix_keymap_data mx31_3ds_keymap_data __initconst = {
+ .keymap = mx31_3ds_keymap,
+ .keymap_size = ARRAY_SIZE(mx31_3ds_keymap),
+};
+
+/* Regulators */
+static struct regulator_init_data pwgtx_init = {
+ .constraints = {
+ .boot_on = 1,
+ .always_on = 1,
+ },
+};
+
+static struct regulator_init_data gpo_init = {
+ .constraints = {
+ .boot_on = 1,
+ .always_on = 1,
+ }
+};
+
+static struct regulator_consumer_supply vmmc2_consumers[] = {
+ REGULATOR_SUPPLY("vmmc", "mxc-mmc.0"),
+};
+
+static struct regulator_init_data vmmc2_init = {
+ .constraints = {
+ .min_uV = 3000000,
+ .max_uV = 3000000,
+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+ REGULATOR_CHANGE_STATUS,
+ },
+ .num_consumer_supplies = ARRAY_SIZE(vmmc2_consumers),
+ .consumer_supplies = vmmc2_consumers,
+};
+
+static struct regulator_consumer_supply vmmc1_consumers[] = {
+ REGULATOR_SUPPLY("lcd_2v8", NULL),
+ REGULATOR_SUPPLY("cmos_2v8", "soc-camera-pdrv.0"),
+};
+
+static struct regulator_init_data vmmc1_init = {
+ .constraints = {
+ .min_uV = 2800000,
+ .max_uV = 2800000,
+ .apply_uV = 1,
+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+ REGULATOR_CHANGE_STATUS,
+ },
+ .num_consumer_supplies = ARRAY_SIZE(vmmc1_consumers),
+ .consumer_supplies = vmmc1_consumers,
+};
+
+static struct regulator_consumer_supply vgen_consumers[] = {
+ REGULATOR_SUPPLY("vdd_lcdio", NULL),
+};
+
+static struct regulator_init_data vgen_init = {
+ .constraints = {
+ .min_uV = 1800000,
+ .max_uV = 1800000,
+ .apply_uV = 1,
+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+ REGULATOR_CHANGE_STATUS,
+ },
+ .num_consumer_supplies = ARRAY_SIZE(vgen_consumers),
+ .consumer_supplies = vgen_consumers,
+};
+
+static struct regulator_consumer_supply vvib_consumers[] = {
+ REGULATOR_SUPPLY("cmos_vcore", "soc-camera-pdrv.0"),
+};
+
+static struct regulator_init_data vvib_init = {
+ .constraints = {
+ .min_uV = 1300000,
+ .max_uV = 1300000,
+ .apply_uV = 1,
+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+ REGULATOR_CHANGE_STATUS,
+ },
+ .num_consumer_supplies = ARRAY_SIZE(vvib_consumers),
+ .consumer_supplies = vvib_consumers,
+};
+
+static struct mc13xxx_regulator_init_data mx31_3ds_regulators[] = {
+ {
+ .id = MC13783_REG_PWGT1SPI, /* Power Gate for ARM core. */
+ .init_data = &pwgtx_init,
+ }, {
+ .id = MC13783_REG_PWGT2SPI, /* Power Gate for L2 Cache. */
+ .init_data = &pwgtx_init,
+ }, {
+
+ .id = MC13783_REG_GPO1, /* Turn on 1.8V */
+ .init_data = &gpo_init,
+ }, {
+ .id = MC13783_REG_GPO3, /* Turn on 3.3V */
+ .init_data = &gpo_init,
+ }, {
+ .id = MC13783_REG_VMMC2, /* Power MMC/SD, WiFi/Bluetooth. */
+ .init_data = &vmmc2_init,
+ }, {
+ .id = MC13783_REG_VMMC1, /* Power LCD, CMOS, FM, GPS, Accel. */
+ .init_data = &vmmc1_init,
+ }, {
+ .id = MC13783_REG_VGEN, /* Power LCD */
+ .init_data = &vgen_init,
+ }, {
+ .id = MC13783_REG_VVIB, /* Power CMOS */
+ .init_data = &vvib_init,
+ },
+};
+
+/* MC13783 */
+static struct mc13xxx_platform_data mc13783_pdata = {
+ .regulators = {
+ .regulators = mx31_3ds_regulators,
+ .num_regulators = ARRAY_SIZE(mx31_3ds_regulators),
+ },
+ .flags = MC13783_USE_REGULATOR | MC13783_USE_TOUCHSCREEN,
+};
+
+/* SPI */
+static int spi0_internal_chipselect[] = {
+ MXC_SPI_CS(2),
+};
+
+static const struct spi_imx_master spi0_pdata __initconst = {
+ .chipselect = spi0_internal_chipselect,
+ .num_chipselect = ARRAY_SIZE(spi0_internal_chipselect),
+};
+
+static int spi1_internal_chipselect[] = {
+ MXC_SPI_CS(0),
+ MXC_SPI_CS(2),
+};
+
+static const struct spi_imx_master spi1_pdata __initconst = {
+ .chipselect = spi1_internal_chipselect,
+ .num_chipselect = ARRAY_SIZE(spi1_internal_chipselect),
+};
+
+static struct spi_board_info mx31_3ds_spi_devs[] __initdata = {
+ {
+ .modalias = "mc13783",
+ .max_speed_hz = 1000000,
+ .bus_num = 1,
+ .chip_select = 1, /* SS2 */
+ .platform_data = &mc13783_pdata,
+ .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
+ .mode = SPI_CS_HIGH,
+ }, {
+ .modalias = "l4f00242t03",
+ .max_speed_hz = 5000000,
+ .bus_num = 0,
+ .chip_select = 0, /* SS2 */
+ .platform_data = &mx31_3ds_l4f00242t03_pdata,
+ },
+};
+
+/*
+ * NAND Flash
+ */
+static const struct mxc_nand_platform_data
+mx31_3ds_nand_board_info __initconst = {
+ .width = 1,
+ .hw_ecc = 1,
+#ifdef MACH_MX31_3DS_MXC_NAND_USE_BBT
+ .flash_bbt = 1,
+#endif
+};
+
+/*
+ * USB OTG
+ */
+
+#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
+ PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
+
+#define USBOTG_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_PWR)
+#define USBH2_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_BYP)
+
+static int mx31_3ds_usbotg_init(void)
+{
+ int err;
+
+ mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG);
+
+ err = gpio_request(USBOTG_RST_B, "otgusb-reset");
+ if (err) {
+ pr_err("Failed to request the USB OTG reset gpio\n");
+ return err;
+ }
+
+ err = gpio_direction_output(USBOTG_RST_B, 0);
+ if (err) {
+ pr_err("Failed to drive the USB OTG reset gpio\n");
+ goto usbotg_free_reset;
+ }
+
+ mdelay(1);
+ gpio_set_value(USBOTG_RST_B, 1);
+ return 0;
+
+usbotg_free_reset:
+ gpio_free(USBOTG_RST_B);
+ return err;
+}
+
+static int mx31_3ds_otg_init(struct platform_device *pdev)
+{
+ return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
+}
+
+static int mx31_3ds_host2_init(struct platform_device *pdev)
+{
+ int err;
+
+ mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_PC_VS2, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_PC_BVD1, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_PC_BVD2, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_PC_RST, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_IOIS16, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_PC_RW_B, USB_PAD_CFG);
+
+ err = gpio_request(USBH2_RST_B, "usbh2-reset");
+ if (err) {
+ pr_err("Failed to request the USB Host 2 reset gpio\n");
+ return err;
+ }
+
+ err = gpio_direction_output(USBH2_RST_B, 0);
+ if (err) {
+ pr_err("Failed to drive the USB Host 2 reset gpio\n");
+ goto usbotg_free_reset;
+ }
+
+ mdelay(1);
+ gpio_set_value(USBH2_RST_B, 1);
+
+ mdelay(10);
+
+ return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
+
+usbotg_free_reset:
+ gpio_free(USBH2_RST_B);
+ return err;
+}
+
+static struct mxc_usbh_platform_data otg_pdata __initdata = {
+ .init = mx31_3ds_otg_init,
+ .portsc = MXC_EHCI_MODE_ULPI,
+};
+
+static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
+ .init = mx31_3ds_host2_init,
+ .portsc = MXC_EHCI_MODE_ULPI,
+};
+
+static const struct fsl_usb2_platform_data usbotg_pdata __initconst = {
+ .operating_mode = FSL_USB2_DR_DEVICE,
+ .phy_mode = FSL_USB2_PHY_ULPI,
+};
+
+static int otg_mode_host;
+
+static int __init mx31_3ds_otg_mode(char *options)
+{
+ if (!strcmp(options, "host"))
+ otg_mode_host = 1;
+ else if (!strcmp(options, "device"))
+ otg_mode_host = 0;
+ else
+ pr_info("otg_mode neither \"host\" nor \"device\". "
+ "Defaulting to device\n");
+ return 0;
+}
+__setup("otg_mode=", mx31_3ds_otg_mode);
+
+static const struct imxuart_platform_data uart_pdata __initconst = {
+ .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static const struct imxi2c_platform_data mx31_3ds_i2c0_data __initconst = {
+ .bitrate = 100000,
+};
+
+static struct platform_device *devices[] __initdata = {
+ &mx31_3ds_ov2640,
+};
+
+static void __init mx31_3ds_init(void)
+{
+ int ret;
+
+ mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins),
+ "mx31_3ds");
+
+ imx31_add_imx_uart0(&uart_pdata);
+ imx31_add_mxc_nand(&mx31_3ds_nand_board_info);
+
+ imx31_add_spi_imx1(&spi1_pdata);
+ spi_register_board_info(mx31_3ds_spi_devs,
+ ARRAY_SIZE(mx31_3ds_spi_devs));
+
+ platform_add_devices(devices, ARRAY_SIZE(devices));
+
+ imx31_add_imx_keypad(&mx31_3ds_keymap_data);
+
+ mx31_3ds_usbotg_init();
+ if (otg_mode_host) {
+ otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
+ ULPI_OTG_DRVVBUS_EXT);
+ if (otg_pdata.otg)
+ imx31_add_mxc_ehci_otg(&otg_pdata);
+ }
+ usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
+ ULPI_OTG_DRVVBUS_EXT);
+ if (usbh2_pdata.otg)
+ imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
+
+ if (!otg_mode_host)
+ imx31_add_fsl_usb2_udc(&usbotg_pdata);
+
+ if (mxc_expio_init(MX31_CS5_BASE_ADDR, EXPIO_PARENT_INT))
+ printk(KERN_WARNING "Init of the debug board failed, all "
+ "devices on the debug board are unusable.\n");
+ imx31_add_imx2_wdt(NULL);
+ imx31_add_imx_i2c0(&mx31_3ds_i2c0_data);
+ imx31_add_mxc_mmc(0, &sdhc1_pdata);
+
+ imx31_add_spi_imx0(&spi0_pdata);
+ imx31_add_ipu_core(&mx3_ipu_data);
+ imx31_add_mx3_sdc_fb(&mx3fb_pdata);
+
+ /* CSI */
+ /* Camera power: default - off */
+ ret = gpio_request_array(mx31_3ds_camera_gpios,
+ ARRAY_SIZE(mx31_3ds_camera_gpios));
+ if (ret) {
+ pr_err("Failed to request camera gpios");
+ iclink_ov2640.power = NULL;
+ }
+
+ mx31_3ds_init_camera();
+}
+
+static void __init mx31_3ds_timer_init(void)
+{
+ mx31_clocks_init(26000000);
+}
+
+static struct sys_timer mx31_3ds_timer = {
+ .init = mx31_3ds_timer_init,
+};
+
+static void __init mx31_3ds_reserve(void)
+{
+ /* reserve MX31_3DS_CAMERA_BUF_SIZE bytes for mx3-camera */
+ mx3_camera_base = memblock_alloc(MX31_3DS_CAMERA_BUF_SIZE,
+ MX31_3DS_CAMERA_BUF_SIZE);
+ memblock_free(mx3_camera_base, MX31_3DS_CAMERA_BUF_SIZE);
+ memblock_remove(mx3_camera_base, MX31_3DS_CAMERA_BUF_SIZE);
+}
+
+MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
+ /* Maintainer: Freescale Semiconductor, Inc. */
+ .boot_params = MX3x_PHYS_OFFSET + 0x100,
+ .map_io = mx31_map_io,
+ .init_early = imx31_init_early,
+ .init_irq = mx31_init_irq,
+ .timer = &mx31_3ds_timer,
+ .init_machine = mx31_3ds_init,
+ .reserve = mx31_3ds_reserve,
+MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx31ads.c b/arch/arm/mach-imx/mach-mx31ads.c
new file mode 100644
index 0000000..f4dee02
--- /dev/null
+++ b/arch/arm/mach-imx/mach-mx31ads.c
@@ -0,0 +1,542 @@
+/*
+ * Copyright (C) 2000 Deep Blue Solutions Ltd
+ * Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/serial_8250.h>
+#include <linux/gpio.h>
+#include <linux/i2c.h>
+#include <linux/irq.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/memory.h>
+#include <asm/mach/map.h>
+#include <mach/common.h>
+#include <mach/board-mx31ads.h>
+#include <mach/iomux-mx3.h>
+
+#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
+#include <linux/mfd/wm8350/audio.h>
+#include <linux/mfd/wm8350/core.h>
+#include <linux/mfd/wm8350/pmic.h>
+#endif
+
+#include "devices-imx31.h"
+
+/* PBC Board interrupt status register */
+#define PBC_INTSTATUS 0x000016
+
+/* PBC Board interrupt current status register */
+#define PBC_INTCURR_STATUS 0x000018
+
+/* PBC Interrupt mask register set address */
+#define PBC_INTMASK_SET 0x00001A
+
+/* PBC Interrupt mask register clear address */
+#define PBC_INTMASK_CLEAR 0x00001C
+
+/* External UART A */
+#define PBC_SC16C652_UARTA 0x010000
+
+/* External UART B */
+#define PBC_SC16C652_UARTB 0x010010
+
+#define PBC_INTSTATUS_REG (PBC_INTSTATUS + PBC_BASE_ADDRESS)
+#define PBC_INTMASK_SET_REG (PBC_INTMASK_SET + PBC_BASE_ADDRESS)
+#define PBC_INTMASK_CLEAR_REG (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
+#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)
+
+#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE)
+
+#define EXPIO_INT_XUART_INTA (MXC_EXP_IO_BASE + 10)
+#define EXPIO_INT_XUART_INTB (MXC_EXP_IO_BASE + 11)
+
+#define MXC_MAX_EXP_IO_LINES 16
+
+/*
+ * The serial port definition structure.
+ */
+static struct plat_serial8250_port serial_platform_data[] = {
+ {
+ .membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTA),
+ .mapbase = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTA),
+ .irq = EXPIO_INT_XUART_INTA,
+ .uartclk = 14745600,
+ .regshift = 0,
+ .iotype = UPIO_MEM,
+ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
+ }, {
+ .membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTB),
+ .mapbase = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTB),
+ .irq = EXPIO_INT_XUART_INTB,
+ .uartclk = 14745600,
+ .regshift = 0,
+ .iotype = UPIO_MEM,
+ .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
+ },
+ {},
+};
+
+static struct platform_device serial_device = {
+ .name = "serial8250",
+ .id = 0,
+ .dev = {
+ .platform_data = serial_platform_data,
+ },
+};
+
+static int __init mxc_init_extuart(void)
+{
+ return platform_device_register(&serial_device);
+}
+
+static const struct imxuart_platform_data uart_pdata __initconst = {
+ .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static unsigned int uart_pins[] = {
+ MX31_PIN_CTS1__CTS1,
+ MX31_PIN_RTS1__RTS1,
+ MX31_PIN_TXD1__TXD1,
+ MX31_PIN_RXD1__RXD1
+};
+
+static inline void mxc_init_imx_uart(void)
+{
+ mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0");
+ imx31_add_imx_uart0(&uart_pdata);
+}
+
+static void mx31ads_expio_irq_handler(u32 irq, struct irq_desc *desc)
+{
+ u32 imr_val;
+ u32 int_valid;
+ u32 expio_irq;
+
+ imr_val = __raw_readw(PBC_INTMASK_SET_REG);
+ int_valid = __raw_readw(PBC_INTSTATUS_REG) & imr_val;
+
+ expio_irq = MXC_EXP_IO_BASE;
+ for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
+ if ((int_valid & 1) == 0)
+ continue;
+
+ generic_handle_irq(expio_irq);
+ }
+}
+
+/*
+ * Disable an expio pin's interrupt by setting the bit in the imr.
+ * @param d an expio virtual irq description
+ */
+static void expio_mask_irq(struct irq_data *d)
+{
+ u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
+ /* mask the interrupt */
+ __raw_writew(1 << expio, PBC_INTMASK_CLEAR_REG);
+ __raw_readw(PBC_INTMASK_CLEAR_REG);
+}
+
+/*
+ * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
+ * @param d an expio virtual irq description
+ */
+static void expio_ack_irq(struct irq_data *d)
+{
+ u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
+ /* clear the interrupt status */
+ __raw_writew(1 << expio, PBC_INTSTATUS_REG);
+}
+
+/*
+ * Enable a expio pin's interrupt by clearing the bit in the imr.
+ * @param d an expio virtual irq description
+ */
+static void expio_unmask_irq(struct irq_data *d)
+{
+ u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
+ /* unmask the interrupt */
+ __raw_writew(1 << expio, PBC_INTMASK_SET_REG);
+}
+
+static struct irq_chip expio_irq_chip = {
+ .name = "EXPIO(CPLD)",
+ .irq_ack = expio_ack_irq,
+ .irq_mask = expio_mask_irq,
+ .irq_unmask = expio_unmask_irq,
+};
+
+static void __init mx31ads_init_expio(void)
+{
+ int i;
+
+ printk(KERN_INFO "MX31ADS EXPIO(CPLD) hardware\n");
+
+ /*
+ * Configure INT line as GPIO input
+ */
+ mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_GPIO1_4, IOMUX_CONFIG_GPIO), "expio");
+
+ /* disable the interrupt and clear the status */
+ __raw_writew(0xFFFF, PBC_INTMASK_CLEAR_REG);
+ __raw_writew(0xFFFF, PBC_INTSTATUS_REG);
+ for (i = MXC_EXP_IO_BASE; i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
+ i++) {
+ irq_set_chip_and_handler(i, &expio_irq_chip, handle_level_irq);
+ set_irq_flags(i, IRQF_VALID);
+ }
+ irq_set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_HIGH);
+ irq_set_chained_handler(EXPIO_PARENT_INT, mx31ads_expio_irq_handler);
+}
+
+#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
+/* This section defines setup for the Wolfson Microelectronics
+ * 1133-EV1 PMU/audio board. When other PMU boards are supported the
+ * regulator definitions may be shared with them, but for now they can
+ * only be used with this board so would generate warnings about
+ * unused statics and some of the configuration is specific to this
+ * module.
+ */
+
+/* CPU */
+static struct regulator_consumer_supply sw1a_consumers[] = {
+ {
+ .supply = "cpu_vcc",
+ }
+};
+
+static struct regulator_init_data sw1a_data = {
+ .constraints = {
+ .name = "SW1A",
+ .min_uV = 1275000,
+ .max_uV = 1600000,
+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+ REGULATOR_CHANGE_MODE,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL |
+ REGULATOR_MODE_FAST,
+ .state_mem = {
+ .uV = 1400000,
+ .mode = REGULATOR_MODE_NORMAL,
+ .enabled = 1,
+ },
+ .initial_state = PM_SUSPEND_MEM,
+ .always_on = 1,
+ .boot_on = 1,
+ },
+ .num_consumer_supplies = ARRAY_SIZE(sw1a_consumers),
+ .consumer_supplies = sw1a_consumers,
+};
+
+/* System IO - High */
+static struct regulator_init_data viohi_data = {
+ .constraints = {
+ .name = "VIOHO",
+ .min_uV = 2800000,
+ .max_uV = 2800000,
+ .state_mem = {
+ .uV = 2800000,
+ .mode = REGULATOR_MODE_NORMAL,
+ .enabled = 1,
+ },
+ .initial_state = PM_SUSPEND_MEM,
+ .always_on = 1,
+ .boot_on = 1,
+ },
+};
+
+/* System IO - Low */
+static struct regulator_init_data violo_data = {
+ .constraints = {
+ .name = "VIOLO",
+ .min_uV = 1800000,
+ .max_uV = 1800000,
+ .state_mem = {
+ .uV = 1800000,
+ .mode = REGULATOR_MODE_NORMAL,
+ .enabled = 1,
+ },
+ .initial_state = PM_SUSPEND_MEM,
+ .always_on = 1,
+ .boot_on = 1,
+ },
+};
+
+/* DDR RAM */
+static struct regulator_init_data sw2a_data = {
+ .constraints = {
+ .name = "SW2A",
+ .min_uV = 1800000,
+ .max_uV = 1800000,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL,
+ .state_mem = {
+ .uV = 1800000,
+ .mode = REGULATOR_MODE_NORMAL,
+ .enabled = 1,
+ },
+ .state_disk = {
+ .mode = REGULATOR_MODE_NORMAL,
+ .enabled = 0,
+ },
+ .always_on = 1,
+ .boot_on = 1,
+ .initial_state = PM_SUSPEND_MEM,
+ },
+};
+
+static struct regulator_init_data ldo1_data = {
+ .constraints = {
+ .name = "VCAM/VMMC1/VMMC2",
+ .min_uV = 2800000,
+ .max_uV = 2800000,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL,
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ .apply_uV = 1,
+ },
+};
+
+static struct regulator_consumer_supply ldo2_consumers[] = {
+ { .supply = "AVDD", .dev_name = "1-001a" },
+ { .supply = "HPVDD", .dev_name = "1-001a" },
+};
+
+/* CODEC and SIM */
+static struct regulator_init_data ldo2_data = {
+ .constraints = {
+ .name = "VESIM/VSIM/AVDD",
+ .min_uV = 3300000,
+ .max_uV = 3300000,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL,
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ .apply_uV = 1,
+ },
+ .num_consumer_supplies = ARRAY_SIZE(ldo2_consumers),
+ .consumer_supplies = ldo2_consumers,
+};
+
+/* General */
+static struct regulator_init_data vdig_data = {
+ .constraints = {
+ .name = "VDIG",
+ .min_uV = 1500000,
+ .max_uV = 1500000,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL,
+ .apply_uV = 1,
+ .always_on = 1,
+ .boot_on = 1,
+ },
+};
+
+/* Tranceivers */
+static struct regulator_init_data ldo4_data = {
+ .constraints = {
+ .name = "VRF1/CVDD_2.775",
+ .min_uV = 2500000,
+ .max_uV = 2500000,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL,
+ .apply_uV = 1,
+ .always_on = 1,
+ .boot_on = 1,
+ },
+};
+
+static struct wm8350_led_platform_data wm8350_led_data = {
+ .name = "wm8350:white",
+ .default_trigger = "heartbeat",
+ .max_uA = 27899,
+};
+
+static struct wm8350_audio_platform_data imx32ads_wm8350_setup = {
+ .vmid_discharge_msecs = 1000,
+ .drain_msecs = 30,
+ .cap_discharge_msecs = 700,
+ .vmid_charge_msecs = 700,
+ .vmid_s_curve = WM8350_S_CURVE_SLOW,
+ .dis_out4 = WM8350_DISCHARGE_SLOW,
+ .dis_out3 = WM8350_DISCHARGE_SLOW,
+ .dis_out2 = WM8350_DISCHARGE_SLOW,
+ .dis_out1 = WM8350_DISCHARGE_SLOW,
+ .vroi_out4 = WM8350_TIE_OFF_500R,
+ .vroi_out3 = WM8350_TIE_OFF_500R,
+ .vroi_out2 = WM8350_TIE_OFF_500R,
+ .vroi_out1 = WM8350_TIE_OFF_500R,
+ .vroi_enable = 0,
+ .codec_current_on = WM8350_CODEC_ISEL_1_0,
+ .codec_current_standby = WM8350_CODEC_ISEL_0_5,
+ .codec_current_charge = WM8350_CODEC_ISEL_1_5,
+};
+
+static int mx31_wm8350_init(struct wm8350 *wm8350)
+{
+ wm8350_gpio_config(wm8350, 0, WM8350_GPIO_DIR_IN,
+ WM8350_GPIO0_PWR_ON_IN, WM8350_GPIO_ACTIVE_LOW,
+ WM8350_GPIO_PULL_UP, WM8350_GPIO_INVERT_OFF,
+ WM8350_GPIO_DEBOUNCE_ON);
+
+ wm8350_gpio_config(wm8350, 3, WM8350_GPIO_DIR_IN,
+ WM8350_GPIO3_PWR_OFF_IN, WM8350_GPIO_ACTIVE_HIGH,
+ WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
+ WM8350_GPIO_DEBOUNCE_ON);
+
+ wm8350_gpio_config(wm8350, 4, WM8350_GPIO_DIR_IN,
+ WM8350_GPIO4_MR_IN, WM8350_GPIO_ACTIVE_HIGH,
+ WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
+ WM8350_GPIO_DEBOUNCE_OFF);
+
+ wm8350_gpio_config(wm8350, 7, WM8350_GPIO_DIR_IN,
+ WM8350_GPIO7_HIBERNATE_IN, WM8350_GPIO_ACTIVE_HIGH,
+ WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
+ WM8350_GPIO_DEBOUNCE_OFF);
+
+ wm8350_gpio_config(wm8350, 6, WM8350_GPIO_DIR_OUT,
+ WM8350_GPIO6_SDOUT_OUT, WM8350_GPIO_ACTIVE_HIGH,
+ WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
+ WM8350_GPIO_DEBOUNCE_OFF);
+
+ wm8350_gpio_config(wm8350, 8, WM8350_GPIO_DIR_OUT,
+ WM8350_GPIO8_VCC_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW,
+ WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
+ WM8350_GPIO_DEBOUNCE_OFF);
+
+ wm8350_gpio_config(wm8350, 9, WM8350_GPIO_DIR_OUT,
+ WM8350_GPIO9_BATT_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW,
+ WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
+ WM8350_GPIO_DEBOUNCE_OFF);
+
+ wm8350_register_regulator(wm8350, WM8350_DCDC_1, &sw1a_data);
+ wm8350_register_regulator(wm8350, WM8350_DCDC_3, &viohi_data);
+ wm8350_register_regulator(wm8350, WM8350_DCDC_4, &violo_data);
+ wm8350_register_regulator(wm8350, WM8350_DCDC_6, &sw2a_data);
+ wm8350_register_regulator(wm8350, WM8350_LDO_1, &ldo1_data);
+ wm8350_register_regulator(wm8350, WM8350_LDO_2, &ldo2_data);
+ wm8350_register_regulator(wm8350, WM8350_LDO_3, &vdig_data);
+ wm8350_register_regulator(wm8350, WM8350_LDO_4, &ldo4_data);
+
+ /* LEDs */
+ wm8350_dcdc_set_slot(wm8350, WM8350_DCDC_5, 1, 1,
+ WM8350_DC5_ERRACT_SHUTDOWN_CONV);
+ wm8350_isink_set_flash(wm8350, WM8350_ISINK_A,
+ WM8350_ISINK_FLASH_DISABLE,
+ WM8350_ISINK_FLASH_TRIG_BIT,
+ WM8350_ISINK_FLASH_DUR_32MS,
+ WM8350_ISINK_FLASH_ON_INSTANT,
+ WM8350_ISINK_FLASH_OFF_INSTANT,
+ WM8350_ISINK_FLASH_MODE_EN);
+ wm8350_dcdc25_set_mode(wm8350, WM8350_DCDC_5,
+ WM8350_ISINK_MODE_BOOST,
+ WM8350_ISINK_ILIM_NORMAL,
+ WM8350_DC5_RMP_20V,
+ WM8350_DC5_FBSRC_ISINKA);
+ wm8350_register_led(wm8350, 0, WM8350_DCDC_5, WM8350_ISINK_A,
+ &wm8350_led_data);
+
+ wm8350->codec.platform_data = &imx32ads_wm8350_setup;
+
+ regulator_has_full_constraints();
+
+ return 0;
+}
+
+static struct wm8350_platform_data __initdata mx31_wm8350_pdata = {
+ .init = mx31_wm8350_init,
+ .irq_base = MXC_BOARD_IRQ_START + MXC_MAX_EXP_IO_LINES,
+};
+#endif
+
+static struct i2c_board_info __initdata mx31ads_i2c1_devices[] = {
+#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
+ {
+ I2C_BOARD_INFO("wm8350", 0x1a),
+ .platform_data = &mx31_wm8350_pdata,
+ .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
+ },
+#endif
+};
+
+static void mxc_init_i2c(void)
+{
+ i2c_register_board_info(1, mx31ads_i2c1_devices,
+ ARRAY_SIZE(mx31ads_i2c1_devices));
+
+ mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1));
+ mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1));
+
+ imx31_add_imx_i2c1(NULL);
+}
+
+static unsigned int ssi_pins[] = {
+ MX31_PIN_SFS5__SFS5,
+ MX31_PIN_SCK5__SCK5,
+ MX31_PIN_SRXD5__SRXD5,
+ MX31_PIN_STXD5__STXD5,
+};
+
+static void mxc_init_audio(void)
+{
+ imx31_add_imx_ssi(0, NULL);
+ mxc_iomux_setup_multiple_pins(ssi_pins, ARRAY_SIZE(ssi_pins), "ssi");
+}
+
+/* static mappings */
+static struct map_desc mx31ads_io_desc[] __initdata = {
+ {
+ .virtual = MX31_CS4_BASE_ADDR_VIRT,
+ .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
+ .length = MX31_CS4_SIZE / 2,
+ .type = MT_DEVICE
+ },
+};
+
+static void __init mx31ads_map_io(void)
+{
+ mx31_map_io();
+ iotable_init(mx31ads_io_desc, ARRAY_SIZE(mx31ads_io_desc));
+}
+
+static void __init mx31ads_init_irq(void)
+{
+ mx31_init_irq();
+ mx31ads_init_expio();
+}
+
+static void __init mx31ads_init(void)
+{
+ mxc_init_extuart();
+ mxc_init_imx_uart();
+ mxc_init_i2c();
+ mxc_init_audio();
+}
+
+static void __init mx31ads_timer_init(void)
+{
+ mx31_clocks_init(26000000);
+}
+
+static struct sys_timer mx31ads_timer = {
+ .init = mx31ads_timer_init,
+};
+
+MACHINE_START(MX31ADS, "Freescale MX31ADS")
+ /* Maintainer: Freescale Semiconductor, Inc. */
+ .boot_params = MX3x_PHYS_OFFSET + 0x100,
+ .map_io = mx31ads_map_io,
+ .init_early = imx31_init_early,
+ .init_irq = mx31ads_init_irq,
+ .timer = &mx31ads_timer,
+ .init_machine = mx31ads_init,
+MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx31lilly.c b/arch/arm/mach-imx/mach-mx31lilly.c
new file mode 100644
index 0000000..410e676
--- /dev/null
+++ b/arch/arm/mach-imx/mach-mx31lilly.c
@@ -0,0 +1,302 @@
+/*
+ * LILLY-1131 module support
+ *
+ * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
+ *
+ * based on code for other MX31 boards,
+ *
+ * Copyright 2005-2007 Freescale Semiconductor
+ * Copyright (c) 2009 Alberto Panizzo <maramaopercheseimorto@gmail.com>
+ * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/clk.h>
+#include <linux/gpio.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/interrupt.h>
+#include <linux/smsc911x.h>
+#include <linux/mtd/physmap.h>
+#include <linux/spi/spi.h>
+#include <linux/mfd/mc13783.h>
+#include <linux/usb/otg.h>
+#include <linux/usb/ulpi.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/iomux-mx3.h>
+#include <mach/board-mx31lilly.h>
+#include <mach/ulpi.h>
+
+#include "devices-imx31.h"
+
+/*
+ * This file contains module-specific initialization routines for LILLY-1131.
+ * Initialization of peripherals found on the baseboard is implemented in the
+ * appropriate baseboard support code.
+ */
+
+/* SMSC ethernet support */
+
+static struct resource smsc91x_resources[] = {
+ {
+ .start = MX31_CS4_BASE_ADDR,
+ .end = MX31_CS4_BASE_ADDR + 0xffff,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ .start = IOMUX_TO_IRQ(MX31_PIN_GPIO1_0),
+ .end = IOMUX_TO_IRQ(MX31_PIN_GPIO1_0),
+ .flags = IORESOURCE_IRQ | IRQF_TRIGGER_FALLING,
+ }
+};
+
+static struct smsc911x_platform_config smsc911x_config = {
+ .phy_interface = PHY_INTERFACE_MODE_MII,
+ .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
+ .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
+ .flags = SMSC911X_USE_32BIT |
+ SMSC911X_SAVE_MAC_ADDRESS |
+ SMSC911X_FORCE_INTERNAL_PHY,
+};
+
+static struct platform_device smsc91x_device = {
+ .name = "smsc911x",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(smsc91x_resources),
+ .resource = smsc91x_resources,
+ .dev = {
+ .platform_data = &smsc911x_config,
+ }
+};
+
+/* NOR flash */
+static struct physmap_flash_data nor_flash_data = {
+ .width = 2,
+};
+
+static struct resource nor_flash_resource = {
+ .start = 0xa0000000,
+ .end = 0xa1ffffff,
+ .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device physmap_flash_device = {
+ .name = "physmap-flash",
+ .id = 0,
+ .dev = {
+ .platform_data = &nor_flash_data,
+ },
+ .resource = &nor_flash_resource,
+ .num_resources = 1,
+};
+
+/* USB */
+
+#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
+ PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
+
+static int usbh1_init(struct platform_device *pdev)
+{
+ int pins[] = {
+ MX31_PIN_CSPI1_MOSI__USBH1_RXDM,
+ MX31_PIN_CSPI1_MISO__USBH1_RXDP,
+ MX31_PIN_CSPI1_SS0__USBH1_TXDM,
+ MX31_PIN_CSPI1_SS1__USBH1_TXDP,
+ MX31_PIN_CSPI1_SS2__USBH1_RCV,
+ MX31_PIN_CSPI1_SCLK__USBH1_OEB,
+ MX31_PIN_CSPI1_SPI_RDY__USBH1_FS,
+ };
+
+ mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB H1");
+
+ mxc_iomux_set_pad(MX31_PIN_CSPI1_MOSI, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_CSPI1_MISO, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_CSPI1_SS0, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_CSPI1_SS1, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_CSPI1_SS2, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_CSPI1_SCLK, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, USB_PAD_CFG);
+
+ mxc_iomux_set_gpr(MUX_PGP_USB_SUSPEND, true);
+
+ mdelay(10);
+
+ return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED |
+ MXC_EHCI_INTERFACE_SINGLE_UNI);
+}
+
+static int usbh2_init(struct platform_device *pdev)
+{
+ int pins[] = {
+ MX31_PIN_USBH2_DATA0__USBH2_DATA0,
+ MX31_PIN_USBH2_DATA1__USBH2_DATA1,
+ MX31_PIN_USBH2_CLK__USBH2_CLK,
+ MX31_PIN_USBH2_DIR__USBH2_DIR,
+ MX31_PIN_USBH2_NXT__USBH2_NXT,
+ MX31_PIN_USBH2_STP__USBH2_STP,
+ };
+
+ mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB H2");
+
+ mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG);
+
+ mxc_iomux_set_gpr(MUX_PGP_UH2, true);
+
+ /* chip select */
+ mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_GPIO),
+ "USBH2_CS");
+ gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), "USBH2 CS");
+ gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), 0);
+
+ mdelay(10);
+
+ return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
+}
+
+static const struct mxc_usbh_platform_data usbh1_pdata __initconst = {
+ .init = usbh1_init,
+ .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL,
+};
+
+static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
+ .init = usbh2_init,
+ .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
+};
+
+static void lilly1131_usb_init(void)
+{
+ imx31_add_mxc_ehci_hs(1, &usbh1_pdata);
+
+ usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
+ ULPI_OTG_DRVVBUS_EXT);
+ if (usbh2_pdata.otg)
+ imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
+}
+
+/* SPI */
+
+static int spi_internal_chipselect[] = {
+ MXC_SPI_CS(0),
+ MXC_SPI_CS(1),
+ MXC_SPI_CS(2),
+};
+
+static const struct spi_imx_master spi0_pdata __initconst = {
+ .chipselect = spi_internal_chipselect,
+ .num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
+};
+
+static const struct spi_imx_master spi1_pdata __initconst = {
+ .chipselect = spi_internal_chipselect,
+ .num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
+};
+
+static struct mc13xxx_platform_data mc13783_pdata __initdata = {
+ .flags = MC13XXX_USE_RTC | MC13XXX_USE_TOUCHSCREEN,
+};
+
+static struct spi_board_info mc13783_dev __initdata = {
+ .modalias = "mc13783",
+ .max_speed_hz = 1000000,
+ .bus_num = 1,
+ .chip_select = 0,
+ .platform_data = &mc13783_pdata,
+ .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
+};
+
+static struct platform_device *devices[] __initdata = {
+ &smsc91x_device,
+ &physmap_flash_device,
+};
+
+static int mx31lilly_baseboard;
+core_param(mx31lilly_baseboard, mx31lilly_baseboard, int, 0444);
+
+static void __init mx31lilly_board_init(void)
+{
+ switch (mx31lilly_baseboard) {
+ case MX31LILLY_NOBOARD:
+ break;
+ case MX31LILLY_DB:
+ mx31lilly_db_init();
+ break;
+ default:
+ printk(KERN_ERR "Illegal mx31lilly_baseboard type %d\n",
+ mx31lilly_baseboard);
+ }
+
+ mxc_iomux_alloc_pin(MX31_PIN_CS4__CS4, "Ethernet CS");
+
+ /* SPI */
+ mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SCLK__SCLK, "SPI1_CLK");
+ mxc_iomux_alloc_pin(MX31_PIN_CSPI1_MOSI__MOSI, "SPI1_TX");
+ mxc_iomux_alloc_pin(MX31_PIN_CSPI1_MISO__MISO, "SPI1_RX");
+ mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SPI_RDY__SPI_RDY, "SPI1_RDY");
+ mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SS0__SS0, "SPI1_SS0");
+ mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SS1__SS1, "SPI1_SS1");
+ mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SS2__SS2, "SPI1_SS2");
+
+ mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SCLK__SCLK, "SPI2_CLK");
+ mxc_iomux_alloc_pin(MX31_PIN_CSPI2_MOSI__MOSI, "SPI2_TX");
+ mxc_iomux_alloc_pin(MX31_PIN_CSPI2_MISO__MISO, "SPI2_RX");
+ mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SPI_RDY__SPI_RDY, "SPI2_RDY");
+ mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS0__SS0, "SPI2_SS0");
+ mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS1__SS1, "SPI2_SS1");
+ mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS2__SS2, "SPI2_SS2");
+
+ imx31_add_spi_imx0(&spi0_pdata);
+ imx31_add_spi_imx1(&spi1_pdata);
+ spi_register_board_info(&mc13783_dev, 1);
+
+ platform_add_devices(devices, ARRAY_SIZE(devices));
+
+ /* USB */
+ lilly1131_usb_init();
+}
+
+static void __init mx31lilly_timer_init(void)
+{
+ mx31_clocks_init(26000000);
+}
+
+static struct sys_timer mx31lilly_timer = {
+ .init = mx31lilly_timer_init,
+};
+
+MACHINE_START(LILLY1131, "INCO startec LILLY-1131")
+ .boot_params = MX3x_PHYS_OFFSET + 0x100,
+ .map_io = mx31_map_io,
+ .init_early = imx31_init_early,
+ .init_irq = mx31_init_irq,
+ .timer = &mx31lilly_timer,
+ .init_machine = mx31lilly_board_init,
+MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx31lite.c b/arch/arm/mach-imx/mach-mx31lite.c
new file mode 100644
index 0000000..ac9b4ca
--- /dev/null
+++ b/arch/arm/mach-imx/mach-mx31lite.c
@@ -0,0 +1,287 @@
+/*
+ * Copyright (C) 2000 Deep Blue Solutions Ltd
+ * Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2009 Daniel Mack <daniel@caiaq.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/memory.h>
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/smsc911x.h>
+#include <linux/mfd/mc13783.h>
+#include <linux/spi/spi.h>
+#include <linux/usb/otg.h>
+#include <linux/usb/ulpi.h>
+#include <linux/mtd/physmap.h>
+#include <linux/delay.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+#include <asm/page.h>
+#include <asm/setup.h>
+
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/board-mx31lite.h>
+#include <mach/iomux-mx3.h>
+#include <mach/irqs.h>
+#include <mach/ulpi.h>
+
+#include "devices-imx31.h"
+
+/*
+ * This file contains the module-specific initialization routines.
+ */
+
+static unsigned int mx31lite_pins[] = {
+ /* LAN9117 IRQ pin */
+ IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO),
+ /* SPI 1 */
+ MX31_PIN_CSPI2_SCLK__SCLK,
+ MX31_PIN_CSPI2_MOSI__MOSI,
+ MX31_PIN_CSPI2_MISO__MISO,
+ MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
+ MX31_PIN_CSPI2_SS0__SS0,
+ MX31_PIN_CSPI2_SS1__SS1,
+ MX31_PIN_CSPI2_SS2__SS2,
+};
+
+static const struct mxc_nand_platform_data
+mx31lite_nand_board_info __initconst = {
+ .width = 1,
+ .hw_ecc = 1,
+};
+
+static struct smsc911x_platform_config smsc911x_config = {
+ .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
+ .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
+ .flags = SMSC911X_USE_16BIT,
+};
+
+static struct resource smsc911x_resources[] = {
+ {
+ .start = MX31_CS4_BASE_ADDR,
+ .end = MX31_CS4_BASE_ADDR + 0x100,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = IOMUX_TO_IRQ(MX31_PIN_SFS6),
+ .end = IOMUX_TO_IRQ(MX31_PIN_SFS6),
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device smsc911x_device = {
+ .name = "smsc911x",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(smsc911x_resources),
+ .resource = smsc911x_resources,
+ .dev = {
+ .platform_data = &smsc911x_config,
+ },
+};
+
+/*
+ * SPI
+ *
+ * The MC13783 is the only hard-wired SPI device on the module.
+ */
+
+static int spi_internal_chipselect[] = {
+ MXC_SPI_CS(0),
+};
+
+static const struct spi_imx_master spi1_pdata __initconst = {
+ .chipselect = spi_internal_chipselect,
+ .num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
+};
+
+static struct mc13xxx_platform_data mc13783_pdata __initdata = {
+ .flags = MC13XXX_USE_RTC |
+ MC13XXX_USE_REGULATOR,
+};
+
+static struct spi_board_info mc13783_spi_dev __initdata = {
+ .modalias = "mc13783",
+ .max_speed_hz = 1000000,
+ .bus_num = 1,
+ .chip_select = 0,
+ .platform_data = &mc13783_pdata,
+ .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
+};
+
+/*
+ * USB
+ */
+
+#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
+ PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
+
+static int usbh2_init(struct platform_device *pdev)
+{
+ int pins[] = {
+ MX31_PIN_USBH2_DATA0__USBH2_DATA0,
+ MX31_PIN_USBH2_DATA1__USBH2_DATA1,
+ MX31_PIN_USBH2_CLK__USBH2_CLK,
+ MX31_PIN_USBH2_DIR__USBH2_DIR,
+ MX31_PIN_USBH2_NXT__USBH2_NXT,
+ MX31_PIN_USBH2_STP__USBH2_STP,
+ };
+
+ mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB H2");
+
+ mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG);
+
+ mxc_iomux_set_gpr(MUX_PGP_UH2, true);
+
+ /* chip select */
+ mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_GPIO),
+ "USBH2_CS");
+ gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), "USBH2 CS");
+ gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), 0);
+
+ mdelay(10);
+
+ return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
+}
+
+static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
+ .init = usbh2_init,
+ .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
+};
+
+/*
+ * NOR flash
+ */
+
+static struct physmap_flash_data nor_flash_data = {
+ .width = 2,
+};
+
+static struct resource nor_flash_resource = {
+ .start = 0xa0000000,
+ .end = 0xa1ffffff,
+ .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device physmap_flash_device = {
+ .name = "physmap-flash",
+ .id = 0,
+ .dev = {
+ .platform_data = &nor_flash_data,
+ },
+ .resource = &nor_flash_resource,
+ .num_resources = 1,
+};
+
+
+
+/*
+ * This structure defines the MX31 memory map.
+ */
+static struct map_desc mx31lite_io_desc[] __initdata = {
+ {
+ .virtual = MX31_CS4_BASE_ADDR_VIRT,
+ .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
+ .length = MX31_CS4_SIZE,
+ .type = MT_DEVICE
+ }
+};
+
+/*
+ * Set up static virtual mappings.
+ */
+void __init mx31lite_map_io(void)
+{
+ mx31_map_io();
+ iotable_init(mx31lite_io_desc, ARRAY_SIZE(mx31lite_io_desc));
+}
+
+static int mx31lite_baseboard;
+core_param(mx31lite_baseboard, mx31lite_baseboard, int, 0444);
+
+static void __init mx31lite_init(void)
+{
+ int ret;
+
+ switch (mx31lite_baseboard) {
+ case MX31LITE_NOBOARD:
+ break;
+ case MX31LITE_DB:
+ mx31lite_db_init();
+ break;
+ default:
+ printk(KERN_ERR "Illegal mx31lite_baseboard type %d\n",
+ mx31lite_baseboard);
+ }
+
+ mxc_iomux_setup_multiple_pins(mx31lite_pins, ARRAY_SIZE(mx31lite_pins),
+ "mx31lite");
+
+ /* NOR and NAND flash */
+ platform_device_register(&physmap_flash_device);
+ imx31_add_mxc_nand(&mx31lite_nand_board_info);
+
+ imx31_add_spi_imx1(&spi1_pdata);
+ spi_register_board_info(&mc13783_spi_dev, 1);
+
+ /* USB */
+ usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
+ ULPI_OTG_DRVVBUS_EXT);
+ if (usbh2_pdata.otg)
+ imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
+
+ /* SMSC9117 IRQ pin */
+ ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_SFS6), "sms9117-irq");
+ if (ret)
+ pr_warning("could not get LAN irq gpio\n");
+ else {
+ gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_SFS6));
+ platform_device_register(&smsc911x_device);
+ }
+}
+
+static void __init mx31lite_timer_init(void)
+{
+ mx31_clocks_init(26000000);
+}
+
+struct sys_timer mx31lite_timer = {
+ .init = mx31lite_timer_init,
+};
+
+MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM")
+ /* Maintainer: Freescale Semiconductor, Inc. */
+ .boot_params = MX3x_PHYS_OFFSET + 0x100,
+ .map_io = mx31lite_map_io,
+ .init_early = imx31_init_early,
+ .init_irq = mx31_init_irq,
+ .timer = &mx31lite_timer,
+ .init_machine = mx31lite_init,
+MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx31moboard.c b/arch/arm/mach-imx/mach-mx31moboard.c
new file mode 100644
index 0000000..eaa51e4
--- /dev/null
+++ b/arch/arm/mach-imx/mach-mx31moboard.c
@@ -0,0 +1,583 @@
+/*
+ * Copyright (C) 2008 Valentin Longchamp, EPFL Mobots group
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/delay.h>
+#include <linux/dma-mapping.h>
+#include <linux/gfp.h>
+#include <linux/gpio.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/leds.h>
+#include <linux/memory.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mtd/partitions.h>
+#include <linux/platform_device.h>
+#include <linux/regulator/machine.h>
+#include <linux/mfd/mc13783.h>
+#include <linux/spi/spi.h>
+#include <linux/types.h>
+#include <linux/memblock.h>
+
+#include <linux/usb/otg.h>
+#include <linux/usb/ulpi.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+#include <mach/board-mx31moboard.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/iomux-mx3.h>
+#include <mach/ulpi.h>
+
+#include "devices-imx31.h"
+
+static unsigned int moboard_pins[] = {
+ /* UART0 */
+ MX31_PIN_TXD1__TXD1, MX31_PIN_RXD1__RXD1,
+ MX31_PIN_CTS1__GPIO2_7,
+ /* UART4 */
+ MX31_PIN_PC_RST__CTS5, MX31_PIN_PC_VS2__RTS5,
+ MX31_PIN_PC_BVD2__TXD5, MX31_PIN_PC_BVD1__RXD5,
+ /* I2C0 */
+ MX31_PIN_I2C_DAT__I2C1_SDA, MX31_PIN_I2C_CLK__I2C1_SCL,
+ /* I2C1 */
+ MX31_PIN_DCD_DTE1__I2C2_SDA, MX31_PIN_RI_DTE1__I2C2_SCL,
+ /* SDHC1 */
+ MX31_PIN_SD1_DATA3__SD1_DATA3, MX31_PIN_SD1_DATA2__SD1_DATA2,
+ MX31_PIN_SD1_DATA1__SD1_DATA1, MX31_PIN_SD1_DATA0__SD1_DATA0,
+ MX31_PIN_SD1_CLK__SD1_CLK, MX31_PIN_SD1_CMD__SD1_CMD,
+ MX31_PIN_ATA_CS0__GPIO3_26, MX31_PIN_ATA_CS1__GPIO3_27,
+ /* USB reset */
+ MX31_PIN_GPIO1_0__GPIO1_0,
+ /* USB OTG */
+ MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
+ MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
+ MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
+ MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
+ MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
+ MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
+ MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
+ MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
+ MX31_PIN_USBOTG_CLK__USBOTG_CLK, MX31_PIN_USBOTG_DIR__USBOTG_DIR,
+ MX31_PIN_USBOTG_NXT__USBOTG_NXT, MX31_PIN_USBOTG_STP__USBOTG_STP,
+ MX31_PIN_USB_OC__GPIO1_30,
+ /* USB H2 */
+ MX31_PIN_USBH2_DATA0__USBH2_DATA0,
+ MX31_PIN_USBH2_DATA1__USBH2_DATA1,
+ MX31_PIN_STXD3__USBH2_DATA2, MX31_PIN_SRXD3__USBH2_DATA3,
+ MX31_PIN_SCK3__USBH2_DATA4, MX31_PIN_SFS3__USBH2_DATA5,
+ MX31_PIN_STXD6__USBH2_DATA6, MX31_PIN_SRXD6__USBH2_DATA7,
+ MX31_PIN_USBH2_CLK__USBH2_CLK, MX31_PIN_USBH2_DIR__USBH2_DIR,
+ MX31_PIN_USBH2_NXT__USBH2_NXT, MX31_PIN_USBH2_STP__USBH2_STP,
+ MX31_PIN_SCK6__GPIO1_25,
+ /* LEDs */
+ MX31_PIN_SVEN0__GPIO2_0, MX31_PIN_STX0__GPIO2_1,
+ MX31_PIN_SRX0__GPIO2_2, MX31_PIN_SIMPD0__GPIO2_3,
+ /* SPI1 */
+ MX31_PIN_CSPI2_MOSI__MOSI, MX31_PIN_CSPI2_MISO__MISO,
+ MX31_PIN_CSPI2_SCLK__SCLK, MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
+ MX31_PIN_CSPI2_SS0__SS0, MX31_PIN_CSPI2_SS2__SS2,
+ /* Atlas IRQ */
+ MX31_PIN_GPIO1_3__GPIO1_3,
+ /* SPI2 */
+ MX31_PIN_CSPI3_MOSI__MOSI, MX31_PIN_CSPI3_MISO__MISO,
+ MX31_PIN_CSPI3_SCLK__SCLK, MX31_PIN_CSPI3_SPI_RDY__SPI_RDY,
+ MX31_PIN_CSPI2_SS1__CSPI3_SS1,
+};
+
+static struct physmap_flash_data mx31moboard_flash_data = {
+ .width = 2,
+};
+
+static struct resource mx31moboard_flash_resource = {
+ .start = 0xa0000000,
+ .end = 0xa1ffffff,
+ .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device mx31moboard_flash = {
+ .name = "physmap-flash",
+ .id = 0,
+ .dev = {
+ .platform_data = &mx31moboard_flash_data,
+ },
+ .resource = &mx31moboard_flash_resource,
+ .num_resources = 1,
+};
+
+static int moboard_uart0_init(struct platform_device *pdev)
+{
+ int ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_CTS1), "uart0-cts-hack");
+ if (ret)
+ return ret;
+
+ ret = gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CTS1), 0);
+ if (ret)
+ gpio_free(IOMUX_TO_GPIO(MX31_PIN_CTS1));
+
+ return ret;
+}
+
+static void moboard_uart0_exit(struct platform_device *pdev)
+{
+ gpio_free(IOMUX_TO_GPIO(MX31_PIN_CTS1));
+}
+
+static const struct imxuart_platform_data uart0_pdata __initconst = {
+ .init = moboard_uart0_init,
+ .exit = moboard_uart0_exit,
+};
+
+static const struct imxuart_platform_data uart4_pdata __initconst = {
+ .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static const struct imxi2c_platform_data moboard_i2c0_data __initconst = {
+ .bitrate = 400000,
+};
+
+static const struct imxi2c_platform_data moboard_i2c1_data __initconst = {
+ .bitrate = 100000,
+};
+
+static int moboard_spi1_cs[] = {
+ MXC_SPI_CS(0),
+ MXC_SPI_CS(2),
+};
+
+static const struct spi_imx_master moboard_spi1_pdata __initconst = {
+ .chipselect = moboard_spi1_cs,
+ .num_chipselect = ARRAY_SIZE(moboard_spi1_cs),
+};
+
+static struct regulator_consumer_supply sdhc_consumers[] = {
+ {
+ .dev_name = "mxc-mmc.0",
+ .supply = "sdhc0_vcc",
+ },
+ {
+ .dev_name = "mxc-mmc.1",
+ .supply = "sdhc1_vcc",
+ },
+};
+
+static struct regulator_init_data sdhc_vreg_data = {
+ .constraints = {
+ .min_uV = 2700000,
+ .max_uV = 3000000,
+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+ REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL |
+ REGULATOR_MODE_FAST,
+ .always_on = 0,
+ .boot_on = 1,
+ },
+ .num_consumer_supplies = ARRAY_SIZE(sdhc_consumers),
+ .consumer_supplies = sdhc_consumers,
+};
+
+static struct regulator_consumer_supply cam_consumers[] = {
+ {
+ .dev_name = "mx3_camera.0",
+ .supply = "cam_vcc",
+ },
+};
+
+static struct regulator_init_data cam_vreg_data = {
+ .constraints = {
+ .min_uV = 2700000,
+ .max_uV = 3000000,
+ .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
+ REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
+ .valid_modes_mask = REGULATOR_MODE_NORMAL |
+ REGULATOR_MODE_FAST,
+ .always_on = 0,
+ .boot_on = 1,
+ },
+ .num_consumer_supplies = ARRAY_SIZE(cam_consumers),
+ .consumer_supplies = cam_consumers,
+};
+
+static struct mc13xxx_regulator_init_data moboard_regulators[] = {
+ {
+ .id = MC13783_REG_VMMC1,
+ .init_data = &sdhc_vreg_data,
+ },
+ {
+ .id = MC13783_REG_VCAM,
+ .init_data = &cam_vreg_data,
+ },
+};
+
+static struct mc13783_led_platform_data moboard_led[] = {
+ {
+ .id = MC13783_LED_R1,
+ .name = "coreboard-led-4:red",
+ .max_current = 2,
+ },
+ {
+ .id = MC13783_LED_G1,
+ .name = "coreboard-led-4:green",
+ .max_current = 2,
+ },
+ {
+ .id = MC13783_LED_B1,
+ .name = "coreboard-led-4:blue",
+ .max_current = 2,
+ },
+ {
+ .id = MC13783_LED_R2,
+ .name = "coreboard-led-5:red",
+ .max_current = 3,
+ },
+ {
+ .id = MC13783_LED_G2,
+ .name = "coreboard-led-5:green",
+ .max_current = 3,
+ },
+ {
+ .id = MC13783_LED_B2,
+ .name = "coreboard-led-5:blue",
+ .max_current = 3,
+ },
+};
+
+static struct mc13783_leds_platform_data moboard_leds = {
+ .num_leds = ARRAY_SIZE(moboard_led),
+ .led = moboard_led,
+ .flags = MC13783_LED_SLEWLIMTC,
+ .abmode = MC13783_LED_AB_DISABLED,
+ .tc1_period = MC13783_LED_PERIOD_10MS,
+ .tc2_period = MC13783_LED_PERIOD_10MS,
+};
+
+static struct mc13xxx_platform_data moboard_pmic = {
+ .regulators = {
+ .regulators = moboard_regulators,
+ .num_regulators = ARRAY_SIZE(moboard_regulators),
+ },
+ .leds = &moboard_leds,
+ .flags = MC13XXX_USE_REGULATOR | MC13XXX_USE_RTC |
+ MC13XXX_USE_ADC | MC13XXX_USE_LED,
+};
+
+static struct spi_board_info moboard_spi_board_info[] __initdata = {
+ {
+ .modalias = "mc13783",
+ .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
+ .max_speed_hz = 300000,
+ .bus_num = 1,
+ .chip_select = 0,
+ .platform_data = &moboard_pmic,
+ .mode = SPI_CS_HIGH,
+ },
+};
+
+static int moboard_spi2_cs[] = {
+ MXC_SPI_CS(1),
+};
+
+static const struct spi_imx_master moboard_spi2_pdata __initconst = {
+ .chipselect = moboard_spi2_cs,
+ .num_chipselect = ARRAY_SIZE(moboard_spi2_cs),
+};
+
+#define SDHC1_CD IOMUX_TO_GPIO(MX31_PIN_ATA_CS0)
+#define SDHC1_WP IOMUX_TO_GPIO(MX31_PIN_ATA_CS1)
+
+static int moboard_sdhc1_get_ro(struct device *dev)
+{
+ return !gpio_get_value(SDHC1_WP);
+}
+
+static int moboard_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
+ void *data)
+{
+ int ret;
+
+ ret = gpio_request(SDHC1_CD, "sdhc-detect");
+ if (ret)
+ return ret;
+
+ gpio_direction_input(SDHC1_CD);
+
+ ret = gpio_request(SDHC1_WP, "sdhc-wp");
+ if (ret)
+ goto err_gpio_free;
+ gpio_direction_input(SDHC1_WP);
+
+ ret = request_irq(gpio_to_irq(SDHC1_CD), detect_irq,
+ IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
+ "sdhc1-card-detect", data);
+ if (ret)
+ goto err_gpio_free_2;
+
+ return 0;
+
+err_gpio_free_2:
+ gpio_free(SDHC1_WP);
+err_gpio_free:
+ gpio_free(SDHC1_CD);
+
+ return ret;
+}
+
+static void moboard_sdhc1_exit(struct device *dev, void *data)
+{
+ free_irq(gpio_to_irq(SDHC1_CD), data);
+ gpio_free(SDHC1_WP);
+ gpio_free(SDHC1_CD);
+}
+
+static const struct imxmmc_platform_data sdhc1_pdata __initconst = {
+ .get_ro = moboard_sdhc1_get_ro,
+ .init = moboard_sdhc1_init,
+ .exit = moboard_sdhc1_exit,
+};
+
+/*
+ * this pin is dedicated for all mx31moboard systems, so we do it here
+ */
+#define USB_RESET_B IOMUX_TO_GPIO(MX31_PIN_GPIO1_0)
+#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
+ PAD_CTL_ODE_CMOS)
+
+#define OTG_EN_B IOMUX_TO_GPIO(MX31_PIN_USB_OC)
+#define USBH2_EN_B IOMUX_TO_GPIO(MX31_PIN_SCK6)
+
+static void usb_xcvr_reset(void)
+{
+ mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG | PAD_CTL_100K_PD);
+ mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG | PAD_CTL_100K_PD);
+ mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG | PAD_CTL_100K_PD);
+ mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG | PAD_CTL_100K_PD);
+ mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG | PAD_CTL_100K_PD);
+ mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG | PAD_CTL_100K_PD);
+ mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG | PAD_CTL_100K_PD);
+ mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG | PAD_CTL_100K_PD);
+ mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG | PAD_CTL_100K_PU);
+ mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG | PAD_CTL_100K_PU);
+ mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG | PAD_CTL_100K_PU);
+ mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG | PAD_CTL_100K_PU);
+
+ mxc_iomux_set_gpr(MUX_PGP_UH2, true);
+ mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG | PAD_CTL_100K_PU);
+ mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG | PAD_CTL_100K_PU);
+ mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG | PAD_CTL_100K_PU);
+ mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG | PAD_CTL_100K_PU);
+ mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG | PAD_CTL_100K_PD);
+ mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG | PAD_CTL_100K_PD);
+ mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG | PAD_CTL_100K_PD);
+ mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG | PAD_CTL_100K_PD);
+ mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG | PAD_CTL_100K_PD);
+ mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG | PAD_CTL_100K_PD);
+ mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG | PAD_CTL_100K_PD);
+ mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG | PAD_CTL_100K_PD);
+
+ gpio_request(OTG_EN_B, "usb-udc-en");
+ gpio_direction_output(OTG_EN_B, 0);
+ gpio_request(USBH2_EN_B, "usbh2-en");
+ gpio_direction_output(USBH2_EN_B, 0);
+
+ gpio_request(USB_RESET_B, "usb-reset");
+ gpio_direction_output(USB_RESET_B, 0);
+ mdelay(1);
+ gpio_set_value(USB_RESET_B, 1);
+ mdelay(1);
+}
+
+static int moboard_usbh2_init_hw(struct platform_device *pdev)
+{
+ return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
+}
+
+static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
+ .init = moboard_usbh2_init_hw,
+ .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
+};
+
+static int __init moboard_usbh2_init(void)
+{
+ struct platform_device *pdev;
+
+ usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
+ ULPI_OTG_DRVVBUS_EXT);
+ if (!usbh2_pdata.otg)
+ return -ENODEV;
+
+ pdev = imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
+ if (IS_ERR(pdev))
+ return PTR_ERR(pdev);
+
+ return 0;
+}
+
+static struct gpio_led mx31moboard_leds[] = {
+ {
+ .name = "coreboard-led-0:red:running",
+ .default_trigger = "heartbeat",
+ .gpio = IOMUX_TO_GPIO(MX31_PIN_SVEN0),
+ }, {
+ .name = "coreboard-led-1:red",
+ .gpio = IOMUX_TO_GPIO(MX31_PIN_STX0),
+ }, {
+ .name = "coreboard-led-2:red",
+ .gpio = IOMUX_TO_GPIO(MX31_PIN_SRX0),
+ }, {
+ .name = "coreboard-led-3:red",
+ .gpio = IOMUX_TO_GPIO(MX31_PIN_SIMPD0),
+ },
+};
+
+static struct gpio_led_platform_data mx31moboard_led_pdata = {
+ .num_leds = ARRAY_SIZE(mx31moboard_leds),
+ .leds = mx31moboard_leds,
+};
+
+static struct platform_device mx31moboard_leds_device = {
+ .name = "leds-gpio",
+ .id = -1,
+ .dev = {
+ .platform_data = &mx31moboard_led_pdata,
+ },
+};
+
+static const struct ipu_platform_data mx3_ipu_data __initconst = {
+ .irq_base = MXC_IPU_IRQ_START,
+};
+
+static struct platform_device *devices[] __initdata = {
+ &mx31moboard_flash,
+ &mx31moboard_leds_device,
+};
+
+static struct mx3_camera_pdata camera_pdata __initdata = {
+ .flags = MX3_CAMERA_DATAWIDTH_8 | MX3_CAMERA_DATAWIDTH_10,
+ .mclk_10khz = 4800,
+};
+
+static phys_addr_t mx3_camera_base __initdata;
+#define MX3_CAMERA_BUF_SIZE SZ_4M
+
+static int __init mx31moboard_init_cam(void)
+{
+ int dma, ret = -ENOMEM;
+ struct platform_device *pdev;
+
+ imx31_add_ipu_core(&mx3_ipu_data);
+
+ pdev = imx31_alloc_mx3_camera(&camera_pdata);
+ if (IS_ERR(pdev))
+ return PTR_ERR(pdev);
+
+ dma = dma_declare_coherent_memory(&pdev->dev,
+ mx3_camera_base, mx3_camera_base,
+ MX3_CAMERA_BUF_SIZE,
+ DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
+ if (!(dma & DMA_MEMORY_MAP))
+ goto err;
+
+ ret = platform_device_add(pdev);
+ if (ret)
+err:
+ platform_device_put(pdev);
+
+ return ret;
+
+}
+
+static int mx31moboard_baseboard;
+core_param(mx31moboard_baseboard, mx31moboard_baseboard, int, 0444);
+
+/*
+ * Board specific initialization.
+ */
+static void __init mx31moboard_init(void)
+{
+ mxc_iomux_setup_multiple_pins(moboard_pins, ARRAY_SIZE(moboard_pins),
+ "moboard");
+
+ platform_add_devices(devices, ARRAY_SIZE(devices));
+
+ imx31_add_imx_uart0(&uart0_pdata);
+ imx31_add_imx_uart4(&uart4_pdata);
+
+ imx31_add_imx_i2c0(&moboard_i2c0_data);
+ imx31_add_imx_i2c1(&moboard_i2c1_data);
+
+ imx31_add_spi_imx1(&moboard_spi1_pdata);
+ imx31_add_spi_imx2(&moboard_spi2_pdata);
+
+ gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3), "pmic-irq");
+ gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
+ spi_register_board_info(moboard_spi_board_info,
+ ARRAY_SIZE(moboard_spi_board_info));
+
+ imx31_add_mxc_mmc(0, &sdhc1_pdata);
+
+ mx31moboard_init_cam();
+
+ usb_xcvr_reset();
+
+ moboard_usbh2_init();
+
+ switch (mx31moboard_baseboard) {
+ case MX31NOBOARD:
+ break;
+ case MX31DEVBOARD:
+ mx31moboard_devboard_init();
+ break;
+ case MX31MARXBOT:
+ mx31moboard_marxbot_init();
+ break;
+ case MX31SMARTBOT:
+ case MX31EYEBOT:
+ mx31moboard_smartbot_init(mx31moboard_baseboard);
+ break;
+ default:
+ printk(KERN_ERR "Illegal mx31moboard_baseboard type %d\n",
+ mx31moboard_baseboard);
+ }
+}
+
+static void __init mx31moboard_timer_init(void)
+{
+ mx31_clocks_init(26000000);
+}
+
+struct sys_timer mx31moboard_timer = {
+ .init = mx31moboard_timer_init,
+};
+
+static void __init mx31moboard_reserve(void)
+{
+ /* reserve 4 MiB for mx3-camera */
+ mx3_camera_base = memblock_alloc(MX3_CAMERA_BUF_SIZE,
+ MX3_CAMERA_BUF_SIZE);
+ memblock_free(mx3_camera_base, MX3_CAMERA_BUF_SIZE);
+ memblock_remove(mx3_camera_base, MX3_CAMERA_BUF_SIZE);
+}
+
+MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard")
+ /* Maintainer: Valentin Longchamp, EPFL Mobots group */
+ .boot_params = MX3x_PHYS_OFFSET + 0x100,
+ .reserve = mx31moboard_reserve,
+ .map_io = mx31_map_io,
+ .init_early = imx31_init_early,
+ .init_irq = mx31_init_irq,
+ .timer = &mx31moboard_timer,
+ .init_machine = mx31moboard_init,
+MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mx35_3ds.c b/arch/arm/mach-imx/mach-mx35_3ds.c
new file mode 100644
index 0000000..882880a
--- /dev/null
+++ b/arch/arm/mach-imx/mach-mx35_3ds.c
@@ -0,0 +1,224 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2009 Marc Kleine-Budde, Pengutronix
+ *
+ * Author: Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * This machine is known as:
+ * - i.MX35 3-Stack Development System
+ * - i.MX35 Platform Development Kit (i.MX35 PDK)
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/memory.h>
+#include <linux/gpio.h>
+#include <linux/usb/otg.h>
+
+#include <linux/mtd/physmap.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/iomux-mx35.h>
+#include <mach/irqs.h>
+#include <mach/3ds_debugboard.h>
+
+#include "devices-imx35.h"
+
+#define EXPIO_PARENT_INT (MXC_INTERNAL_IRQS + GPIO_PORTA + 1)
+
+static const struct imxuart_platform_data uart_pdata __initconst = {
+ .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static struct physmap_flash_data mx35pdk_flash_data = {
+ .width = 2,
+};
+
+static struct resource mx35pdk_flash_resource = {
+ .start = MX35_CS0_BASE_ADDR,
+ .end = MX35_CS0_BASE_ADDR + SZ_64M - 1,
+ .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device mx35pdk_flash = {
+ .name = "physmap-flash",
+ .id = 0,
+ .dev = {
+ .platform_data = &mx35pdk_flash_data,
+ },
+ .resource = &mx35pdk_flash_resource,
+ .num_resources = 1,
+};
+
+static const struct mxc_nand_platform_data mx35pdk_nand_board_info __initconst = {
+ .width = 1,
+ .hw_ecc = 1,
+ .flash_bbt = 1,
+};
+
+static struct platform_device *devices[] __initdata = {
+ &mx35pdk_flash,
+};
+
+static iomux_v3_cfg_t mx35pdk_pads[] = {
+ /* UART1 */
+ MX35_PAD_CTS1__UART1_CTS,
+ MX35_PAD_RTS1__UART1_RTS,
+ MX35_PAD_TXD1__UART1_TXD_MUX,
+ MX35_PAD_RXD1__UART1_RXD_MUX,
+ /* FEC */
+ MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
+ MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
+ MX35_PAD_FEC_RX_DV__FEC_RX_DV,
+ MX35_PAD_FEC_COL__FEC_COL,
+ MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
+ MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
+ MX35_PAD_FEC_TX_EN__FEC_TX_EN,
+ MX35_PAD_FEC_MDC__FEC_MDC,
+ MX35_PAD_FEC_MDIO__FEC_MDIO,
+ MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
+ MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
+ MX35_PAD_FEC_CRS__FEC_CRS,
+ MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
+ MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
+ MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
+ MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
+ MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
+ MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
+ /* USBOTG */
+ MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR,
+ MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC,
+ /* USBH1 */
+ MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR,
+ MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC,
+ /* SDCARD */
+ MX35_PAD_SD1_CMD__ESDHC1_CMD,
+ MX35_PAD_SD1_CLK__ESDHC1_CLK,
+ MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
+ MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
+ MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
+ MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
+ /* I2C1 */
+ MX35_PAD_I2C1_CLK__I2C1_SCL,
+ MX35_PAD_I2C1_DAT__I2C1_SDA,
+};
+
+static int mx35_3ds_otg_init(struct platform_device *pdev)
+{
+ return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY);
+}
+
+/* OTG config */
+static const struct fsl_usb2_platform_data usb_otg_pdata __initconst = {
+ .operating_mode = FSL_USB2_DR_DEVICE,
+ .phy_mode = FSL_USB2_PHY_UTMI_WIDE,
+ .workaround = FLS_USB2_WORKAROUND_ENGCM09152,
+/*
+ * ENGCM09152 also requires a hardware change.
+ * Please check the MX35 Chip Errata document for details.
+ */
+};
+
+static struct mxc_usbh_platform_data otg_pdata __initdata = {
+ .init = mx35_3ds_otg_init,
+ .portsc = MXC_EHCI_MODE_UTMI,
+};
+
+static int mx35_3ds_usbh_init(struct platform_device *pdev)
+{
+ return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_SINGLE_UNI |
+ MXC_EHCI_INTERNAL_PHY);
+}
+
+/* USB HOST config */
+static const struct mxc_usbh_platform_data usb_host_pdata __initconst = {
+ .init = mx35_3ds_usbh_init,
+ .portsc = MXC_EHCI_MODE_SERIAL,
+};
+
+static int otg_mode_host;
+
+static int __init mx35_3ds_otg_mode(char *options)
+{
+ if (!strcmp(options, "host"))
+ otg_mode_host = 1;
+ else if (!strcmp(options, "device"))
+ otg_mode_host = 0;
+ else
+ pr_info("otg_mode neither \"host\" nor \"device\". "
+ "Defaulting to device\n");
+ return 0;
+}
+__setup("otg_mode=", mx35_3ds_otg_mode);
+
+static const struct imxi2c_platform_data mx35_3ds_i2c0_data __initconst = {
+ .bitrate = 100000,
+};
+
+/*
+ * Board specific initialization.
+ */
+static void __init mx35_3ds_init(void)
+{
+ mxc_iomux_v3_setup_multiple_pads(mx35pdk_pads, ARRAY_SIZE(mx35pdk_pads));
+
+ imx35_add_fec(NULL);
+ imx35_add_imx2_wdt(NULL);
+ platform_add_devices(devices, ARRAY_SIZE(devices));
+
+ imx35_add_imx_uart0(&uart_pdata);
+
+ if (otg_mode_host)
+ imx35_add_mxc_ehci_otg(&otg_pdata);
+
+ imx35_add_mxc_ehci_hs(&usb_host_pdata);
+
+ if (!otg_mode_host)
+ imx35_add_fsl_usb2_udc(&usb_otg_pdata);
+
+ imx35_add_mxc_nand(&mx35pdk_nand_board_info);
+ imx35_add_sdhci_esdhc_imx(0, NULL);
+
+ if (mxc_expio_init(MX35_CS5_BASE_ADDR, EXPIO_PARENT_INT))
+ pr_warn("Init of the debugboard failed, all "
+ "devices on the debugboard are unusable.\n");
+ imx35_add_imx_i2c0(&mx35_3ds_i2c0_data);
+}
+
+static void __init mx35pdk_timer_init(void)
+{
+ mx35_clocks_init();
+}
+
+struct sys_timer mx35pdk_timer = {
+ .init = mx35pdk_timer_init,
+};
+
+MACHINE_START(MX35_3DS, "Freescale MX35PDK")
+ /* Maintainer: Freescale Semiconductor, Inc */
+ .boot_params = MX3x_PHYS_OFFSET + 0x100,
+ .map_io = mx35_map_io,
+ .init_early = imx35_init_early,
+ .init_irq = mx35_init_irq,
+ .timer = &mx35pdk_timer,
+ .init_machine = mx35_3ds_init,
+MACHINE_END
diff --git a/arch/arm/mach-imx/mach-mxt_td60.c b/arch/arm/mach-imx/mach-mxt_td60.c
index 69787c3..2774541 100644
--- a/arch/arm/mach-imx/mach-mxt_td60.c
+++ b/arch/arm/mach-imx/mach-mxt_td60.c
@@ -29,7 +29,6 @@
#include <asm/mach/map.h>
#include <linux/gpio.h>
#include <mach/iomux-mx27.h>
-#include <mach/mxc_nand.h>
#include <linux/i2c/pca953x.h>
#include "devices-imx27.h"
diff --git a/arch/arm/mach-imx/mach-pca100.c b/arch/arm/mach-imx/mach-pca100.c
index 63e1825..bbddc5a 100644
--- a/arch/arm/mach-imx/mach-pca100.c
+++ b/arch/arm/mach-imx/mach-pca100.c
@@ -37,7 +37,6 @@
#include <mach/iomux-mx27.h>
#include <asm/mach/time.h>
#include <mach/audmux.h>
-#include <mach/mxc_nand.h>
#include <mach/irqs.h>
#include <mach/ulpi.h>
diff --git a/arch/arm/mach-imx/mach-pcm037.c b/arch/arm/mach-imx/mach-pcm037.c
new file mode 100644
index 0000000..89c213b
--- /dev/null
+++ b/arch/arm/mach-imx/mach-pcm037.c
@@ -0,0 +1,696 @@
+/*
+ * Copyright (C) 2008 Sascha Hauer, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/dma-mapping.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mtd/plat-ram.h>
+#include <linux/memory.h>
+#include <linux/gpio.h>
+#include <linux/smsc911x.h>
+#include <linux/interrupt.h>
+#include <linux/i2c.h>
+#include <linux/i2c/at24.h>
+#include <linux/delay.h>
+#include <linux/spi/spi.h>
+#include <linux/irq.h>
+#include <linux/can/platform/sja1000.h>
+#include <linux/usb/otg.h>
+#include <linux/usb/ulpi.h>
+#include <linux/gfp.h>
+#include <linux/memblock.h>
+
+#include <media/soc_camera.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/iomux-mx3.h>
+#include <mach/ulpi.h>
+
+#include "devices-imx31.h"
+#include "pcm037.h"
+
+static enum pcm037_board_variant pcm037_instance = PCM037_PCM970;
+
+static int __init pcm037_variant_setup(char *str)
+{
+ if (!strcmp("eet", str))
+ pcm037_instance = PCM037_EET;
+ else if (strcmp("pcm970", str))
+ pr_warning("Unknown pcm037 baseboard variant %s\n", str);
+
+ return 1;
+}
+
+/* Supported values: "pcm970" (default) and "eet" */
+__setup("pcm037_variant=", pcm037_variant_setup);
+
+enum pcm037_board_variant pcm037_variant(void)
+{
+ return pcm037_instance;
+}
+
+/* UART1 with RTS/CTS handshake signals */
+static unsigned int pcm037_uart1_handshake_pins[] = {
+ MX31_PIN_CTS1__CTS1,
+ MX31_PIN_RTS1__RTS1,
+ MX31_PIN_TXD1__TXD1,
+ MX31_PIN_RXD1__RXD1,
+};
+
+/* UART1 without RTS/CTS handshake signals */
+static unsigned int pcm037_uart1_pins[] = {
+ MX31_PIN_TXD1__TXD1,
+ MX31_PIN_RXD1__RXD1,
+};
+
+static unsigned int pcm037_pins[] = {
+ /* I2C */
+ MX31_PIN_CSPI2_MOSI__SCL,
+ MX31_PIN_CSPI2_MISO__SDA,
+ MX31_PIN_CSPI2_SS2__I2C3_SDA,
+ MX31_PIN_CSPI2_SCLK__I2C3_SCL,
+ /* SDHC1 */
+ MX31_PIN_SD1_DATA3__SD1_DATA3,
+ MX31_PIN_SD1_DATA2__SD1_DATA2,
+ MX31_PIN_SD1_DATA1__SD1_DATA1,
+ MX31_PIN_SD1_DATA0__SD1_DATA0,
+ MX31_PIN_SD1_CLK__SD1_CLK,
+ MX31_PIN_SD1_CMD__SD1_CMD,
+ IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO), /* card detect */
+ IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO), /* write protect */
+ /* SPI1 */
+ MX31_PIN_CSPI1_MOSI__MOSI,
+ MX31_PIN_CSPI1_MISO__MISO,
+ MX31_PIN_CSPI1_SCLK__SCLK,
+ MX31_PIN_CSPI1_SPI_RDY__SPI_RDY,
+ MX31_PIN_CSPI1_SS0__SS0,
+ MX31_PIN_CSPI1_SS1__SS1,
+ MX31_PIN_CSPI1_SS2__SS2,
+ /* UART2 */
+ MX31_PIN_TXD2__TXD2,
+ MX31_PIN_RXD2__RXD2,
+ MX31_PIN_CTS2__CTS2,
+ MX31_PIN_RTS2__RTS2,
+ /* UART3 */
+ MX31_PIN_CSPI3_MOSI__RXD3,
+ MX31_PIN_CSPI3_MISO__TXD3,
+ MX31_PIN_CSPI3_SCLK__RTS3,
+ MX31_PIN_CSPI3_SPI_RDY__CTS3,
+ /* LAN9217 irq pin */
+ IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO),
+ /* Onewire */
+ MX31_PIN_BATT_LINE__OWIRE,
+ /* Framebuffer */
+ MX31_PIN_LD0__LD0,
+ MX31_PIN_LD1__LD1,
+ MX31_PIN_LD2__LD2,
+ MX31_PIN_LD3__LD3,
+ MX31_PIN_LD4__LD4,
+ MX31_PIN_LD5__LD5,
+ MX31_PIN_LD6__LD6,
+ MX31_PIN_LD7__LD7,
+ MX31_PIN_LD8__LD8,
+ MX31_PIN_LD9__LD9,
+ MX31_PIN_LD10__LD10,
+ MX31_PIN_LD11__LD11,
+ MX31_PIN_LD12__LD12,
+ MX31_PIN_LD13__LD13,
+ MX31_PIN_LD14__LD14,
+ MX31_PIN_LD15__LD15,
+ MX31_PIN_LD16__LD16,
+ MX31_PIN_LD17__LD17,
+ MX31_PIN_VSYNC3__VSYNC3,
+ MX31_PIN_HSYNC__HSYNC,
+ MX31_PIN_FPSHIFT__FPSHIFT,
+ MX31_PIN_DRDY0__DRDY0,
+ MX31_PIN_D3_REV__D3_REV,
+ MX31_PIN_CONTRAST__CONTRAST,
+ MX31_PIN_D3_SPL__D3_SPL,
+ MX31_PIN_D3_CLS__D3_CLS,
+ MX31_PIN_LCS0__GPI03_23,
+ /* CSI */
+ IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_GPIO),
+ MX31_PIN_CSI_D6__CSI_D6,
+ MX31_PIN_CSI_D7__CSI_D7,
+ MX31_PIN_CSI_D8__CSI_D8,
+ MX31_PIN_CSI_D9__CSI_D9,
+ MX31_PIN_CSI_D10__CSI_D10,
+ MX31_PIN_CSI_D11__CSI_D11,
+ MX31_PIN_CSI_D12__CSI_D12,
+ MX31_PIN_CSI_D13__CSI_D13,
+ MX31_PIN_CSI_D14__CSI_D14,
+ MX31_PIN_CSI_D15__CSI_D15,
+ MX31_PIN_CSI_HSYNC__CSI_HSYNC,
+ MX31_PIN_CSI_MCLK__CSI_MCLK,
+ MX31_PIN_CSI_PIXCLK__CSI_PIXCLK,
+ MX31_PIN_CSI_VSYNC__CSI_VSYNC,
+ /* GPIO */
+ IOMUX_MODE(MX31_PIN_ATA_DMACK, IOMUX_CONFIG_GPIO),
+ /* OTG */
+ MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
+ MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
+ MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
+ MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
+ MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
+ MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
+ MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
+ MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
+ MX31_PIN_USBOTG_CLK__USBOTG_CLK,
+ MX31_PIN_USBOTG_DIR__USBOTG_DIR,
+ MX31_PIN_USBOTG_NXT__USBOTG_NXT,
+ MX31_PIN_USBOTG_STP__USBOTG_STP,
+ /* USB host 2 */
+ IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC),
+ IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC),
+ IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC),
+ IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC),
+ IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC),
+ IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC),
+ IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC),
+ IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC),
+ IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC),
+ IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC),
+ IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC),
+ IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC),
+};
+
+static struct physmap_flash_data pcm037_flash_data = {
+ .width = 2,
+};
+
+static struct resource pcm037_flash_resource = {
+ .start = 0xa0000000,
+ .end = 0xa1ffffff,
+ .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device pcm037_flash = {
+ .name = "physmap-flash",
+ .id = 0,
+ .dev = {
+ .platform_data = &pcm037_flash_data,
+ },
+ .resource = &pcm037_flash_resource,
+ .num_resources = 1,
+};
+
+static const struct imxuart_platform_data uart_pdata __initconst = {
+ .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static struct resource smsc911x_resources[] = {
+ {
+ .start = MX31_CS1_BASE_ADDR + 0x300,
+ .end = MX31_CS1_BASE_ADDR + 0x300 + SZ_64K - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
+ .end = IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
+ .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
+ },
+};
+
+static struct smsc911x_platform_config smsc911x_info = {
+ .flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY |
+ SMSC911X_SAVE_MAC_ADDRESS,
+ .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
+ .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
+ .phy_interface = PHY_INTERFACE_MODE_MII,
+};
+
+static struct platform_device pcm037_eth = {
+ .name = "smsc911x",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(smsc911x_resources),
+ .resource = smsc911x_resources,
+ .dev = {
+ .platform_data = &smsc911x_info,
+ },
+};
+
+static struct platdata_mtd_ram pcm038_sram_data = {
+ .bankwidth = 2,
+};
+
+static struct resource pcm038_sram_resource = {
+ .start = MX31_CS4_BASE_ADDR,
+ .end = MX31_CS4_BASE_ADDR + 512 * 1024 - 1,
+ .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device pcm037_sram_device = {
+ .name = "mtd-ram",
+ .id = 0,
+ .dev = {
+ .platform_data = &pcm038_sram_data,
+ },
+ .num_resources = 1,
+ .resource = &pcm038_sram_resource,
+};
+
+static const struct mxc_nand_platform_data
+pcm037_nand_board_info __initconst = {
+ .width = 1,
+ .hw_ecc = 1,
+};
+
+static const struct imxi2c_platform_data pcm037_i2c1_data __initconst = {
+ .bitrate = 100000,
+};
+
+static const struct imxi2c_platform_data pcm037_i2c2_data __initconst = {
+ .bitrate = 20000,
+};
+
+static struct at24_platform_data board_eeprom = {
+ .byte_len = 4096,
+ .page_size = 32,
+ .flags = AT24_FLAG_ADDR16,
+};
+
+static int pcm037_camera_power(struct device *dev, int on)
+{
+ /* disable or enable the camera in X7 or X8 PCM970 connector */
+ gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), !on);
+ return 0;
+}
+
+static struct i2c_board_info pcm037_i2c_camera[] = {
+ {
+ I2C_BOARD_INFO("mt9t031", 0x5d),
+ }, {
+ I2C_BOARD_INFO("mt9v022", 0x48),
+ },
+};
+
+static struct soc_camera_link iclink_mt9v022 = {
+ .bus_id = 0, /* Must match with the camera ID */
+ .board_info = &pcm037_i2c_camera[1],
+ .i2c_adapter_id = 2,
+};
+
+static struct soc_camera_link iclink_mt9t031 = {
+ .bus_id = 0, /* Must match with the camera ID */
+ .power = pcm037_camera_power,
+ .board_info = &pcm037_i2c_camera[0],
+ .i2c_adapter_id = 2,
+};
+
+static struct i2c_board_info pcm037_i2c_devices[] = {
+ {
+ I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
+ .platform_data = &board_eeprom,
+ }, {
+ I2C_BOARD_INFO("pcf8563", 0x51),
+ }
+};
+
+static struct platform_device pcm037_mt9t031 = {
+ .name = "soc-camera-pdrv",
+ .id = 0,
+ .dev = {
+ .platform_data = &iclink_mt9t031,
+ },
+};
+
+static struct platform_device pcm037_mt9v022 = {
+ .name = "soc-camera-pdrv",
+ .id = 1,
+ .dev = {
+ .platform_data = &iclink_mt9v022,
+ },
+};
+
+/* Not connected by default */
+#ifdef PCM970_SDHC_RW_SWITCH
+static int pcm970_sdhc1_get_ro(struct device *dev)
+{
+ return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_SFS6));
+}
+#endif
+
+#define SDHC1_GPIO_WP IOMUX_TO_GPIO(MX31_PIN_SFS6)
+#define SDHC1_GPIO_DET IOMUX_TO_GPIO(MX31_PIN_SCK6)
+
+static int pcm970_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
+ void *data)
+{
+ int ret;
+
+ ret = gpio_request(SDHC1_GPIO_DET, "sdhc-detect");
+ if (ret)
+ return ret;
+
+ gpio_direction_input(SDHC1_GPIO_DET);
+
+#ifdef PCM970_SDHC_RW_SWITCH
+ ret = gpio_request(SDHC1_GPIO_WP, "sdhc-wp");
+ if (ret)
+ goto err_gpio_free;
+ gpio_direction_input(SDHC1_GPIO_WP);
+#endif
+
+ ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_SCK6), detect_irq,
+ IRQF_DISABLED | IRQF_TRIGGER_FALLING,
+ "sdhc-detect", data);
+ if (ret)
+ goto err_gpio_free_2;
+
+ return 0;
+
+err_gpio_free_2:
+#ifdef PCM970_SDHC_RW_SWITCH
+ gpio_free(SDHC1_GPIO_WP);
+err_gpio_free:
+#endif
+ gpio_free(SDHC1_GPIO_DET);
+
+ return ret;
+}
+
+static void pcm970_sdhc1_exit(struct device *dev, void *data)
+{
+ free_irq(IOMUX_TO_IRQ(MX31_PIN_SCK6), data);
+ gpio_free(SDHC1_GPIO_DET);
+ gpio_free(SDHC1_GPIO_WP);
+}
+
+static const struct imxmmc_platform_data sdhc_pdata __initconst = {
+#ifdef PCM970_SDHC_RW_SWITCH
+ .get_ro = pcm970_sdhc1_get_ro,
+#endif
+ .init = pcm970_sdhc1_init,
+ .exit = pcm970_sdhc1_exit,
+};
+
+struct mx3_camera_pdata camera_pdata __initdata = {
+ .flags = MX3_CAMERA_DATAWIDTH_8 | MX3_CAMERA_DATAWIDTH_10,
+ .mclk_10khz = 2000,
+};
+
+static phys_addr_t mx3_camera_base __initdata;
+#define MX3_CAMERA_BUF_SIZE SZ_4M
+
+static int __init pcm037_init_camera(void)
+{
+ int dma, ret = -ENOMEM;
+ struct platform_device *pdev = imx31_alloc_mx3_camera(&camera_pdata);
+
+ if (IS_ERR(pdev))
+ return PTR_ERR(pdev);
+
+ dma = dma_declare_coherent_memory(&pdev->dev,
+ mx3_camera_base, mx3_camera_base,
+ MX3_CAMERA_BUF_SIZE,
+ DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
+ if (!(dma & DMA_MEMORY_MAP))
+ goto err;
+
+ ret = platform_device_add(pdev);
+ if (ret)
+err:
+ platform_device_put(pdev);
+
+ return ret;
+}
+
+static struct platform_device *devices[] __initdata = {
+ &pcm037_flash,
+ &pcm037_sram_device,
+ &pcm037_mt9t031,
+ &pcm037_mt9v022,
+};
+
+static const struct ipu_platform_data mx3_ipu_data __initconst = {
+ .irq_base = MXC_IPU_IRQ_START,
+};
+
+static const struct fb_videomode fb_modedb[] = {
+ {
+ /* 240x320 @ 60 Hz Sharp */
+ .name = "Sharp-LQ035Q7DH06-QVGA",
+ .refresh = 60,
+ .xres = 240,
+ .yres = 320,
+ .pixclock = 185925,
+ .left_margin = 9,
+ .right_margin = 16,
+ .upper_margin = 7,
+ .lower_margin = 9,
+ .hsync_len = 1,
+ .vsync_len = 1,
+ .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE |
+ FB_SYNC_CLK_INVERT | FB_SYNC_CLK_IDLE_EN,
+ .vmode = FB_VMODE_NONINTERLACED,
+ .flag = 0,
+ }, {
+ /* 240x320 @ 60 Hz */
+ .name = "TX090",
+ .refresh = 60,
+ .xres = 240,
+ .yres = 320,
+ .pixclock = 38255,
+ .left_margin = 144,
+ .right_margin = 0,
+ .upper_margin = 7,
+ .lower_margin = 40,
+ .hsync_len = 96,
+ .vsync_len = 1,
+ .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH,
+ .vmode = FB_VMODE_NONINTERLACED,
+ .flag = 0,
+ }, {
+ /* 240x320 @ 60 Hz */
+ .name = "CMEL-OLED",
+ .refresh = 60,
+ .xres = 240,
+ .yres = 320,
+ .pixclock = 185925,
+ .left_margin = 9,
+ .right_margin = 16,
+ .upper_margin = 7,
+ .lower_margin = 9,
+ .hsync_len = 1,
+ .vsync_len = 1,
+ .sync = FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT,
+ .vmode = FB_VMODE_NONINTERLACED,
+ .flag = 0,
+ },
+};
+
+static struct mx3fb_platform_data mx3fb_pdata = {
+ .name = "Sharp-LQ035Q7DH06-QVGA",
+ .mode = fb_modedb,
+ .num_modes = ARRAY_SIZE(fb_modedb),
+};
+
+static struct resource pcm970_sja1000_resources[] = {
+ {
+ .start = MX31_CS5_BASE_ADDR,
+ .end = MX31_CS5_BASE_ADDR + 0x100 - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = IOMUX_TO_IRQ(IOMUX_PIN(48, 105)),
+ .end = IOMUX_TO_IRQ(IOMUX_PIN(48, 105)),
+ .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
+ },
+};
+
+struct sja1000_platform_data pcm970_sja1000_platform_data = {
+ .osc_freq = 16000000,
+ .ocr = OCR_TX1_PULLDOWN | OCR_TX0_PUSHPULL,
+ .cdr = CDR_CBP,
+};
+
+static struct platform_device pcm970_sja1000 = {
+ .name = "sja1000_platform",
+ .dev = {
+ .platform_data = &pcm970_sja1000_platform_data,
+ },
+ .resource = pcm970_sja1000_resources,
+ .num_resources = ARRAY_SIZE(pcm970_sja1000_resources),
+};
+
+static int pcm037_otg_init(struct platform_device *pdev)
+{
+ return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
+}
+
+static struct mxc_usbh_platform_data otg_pdata __initdata = {
+ .init = pcm037_otg_init,
+ .portsc = MXC_EHCI_MODE_ULPI,
+};
+
+static int pcm037_usbh2_init(struct platform_device *pdev)
+{
+ return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
+}
+
+static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
+ .init = pcm037_usbh2_init,
+ .portsc = MXC_EHCI_MODE_ULPI,
+};
+
+static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
+ .operating_mode = FSL_USB2_DR_DEVICE,
+ .phy_mode = FSL_USB2_PHY_ULPI,
+};
+
+static int otg_mode_host;
+
+static int __init pcm037_otg_mode(char *options)
+{
+ if (!strcmp(options, "host"))
+ otg_mode_host = 1;
+ else if (!strcmp(options, "device"))
+ otg_mode_host = 0;
+ else
+ pr_info("otg_mode neither \"host\" nor \"device\". "
+ "Defaulting to device\n");
+ return 0;
+}
+__setup("otg_mode=", pcm037_otg_mode);
+
+/*
+ * Board specific initialization.
+ */
+static void __init pcm037_init(void)
+{
+ int ret;
+
+ mxc_iomux_set_gpr(MUX_PGP_UH2, 1);
+
+ mxc_iomux_setup_multiple_pins(pcm037_pins, ARRAY_SIZE(pcm037_pins),
+ "pcm037");
+
+#define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS \
+ | PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
+
+ mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */
+ mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */
+ mxc_iomux_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG); /* USBH2_DATA2 */
+ mxc_iomux_set_pad(MX31_PIN_STXD6, H2_PAD_CFG); /* USBH2_DATA3 */
+ mxc_iomux_set_pad(MX31_PIN_SFS3, H2_PAD_CFG); /* USBH2_DATA4 */
+ mxc_iomux_set_pad(MX31_PIN_SCK3, H2_PAD_CFG); /* USBH2_DATA5 */
+ mxc_iomux_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG); /* USBH2_DATA6 */
+ mxc_iomux_set_pad(MX31_PIN_STXD3, H2_PAD_CFG); /* USBH2_DATA7 */
+
+ if (pcm037_variant() == PCM037_EET)
+ mxc_iomux_setup_multiple_pins(pcm037_uart1_pins,
+ ARRAY_SIZE(pcm037_uart1_pins), "pcm037_uart1");
+ else
+ mxc_iomux_setup_multiple_pins(pcm037_uart1_handshake_pins,
+ ARRAY_SIZE(pcm037_uart1_handshake_pins),
+ "pcm037_uart1");
+
+ platform_add_devices(devices, ARRAY_SIZE(devices));
+
+ imx31_add_imx2_wdt(NULL);
+ imx31_add_imx_uart0(&uart_pdata);
+ /* XXX: should't this have .flags = 0 (i.e. no RTSCTS) on PCM037_EET? */
+ imx31_add_imx_uart1(&uart_pdata);
+ imx31_add_imx_uart2(&uart_pdata);
+
+ imx31_add_mxc_w1(NULL);
+
+ /* LAN9217 IRQ pin */
+ ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1), "lan9217-irq");
+ if (ret)
+ pr_warning("could not get LAN irq gpio\n");
+ else {
+ gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1));
+ platform_device_register(&pcm037_eth);
+ }
+
+
+ /* I2C adapters and devices */
+ i2c_register_board_info(1, pcm037_i2c_devices,
+ ARRAY_SIZE(pcm037_i2c_devices));
+
+ imx31_add_imx_i2c1(&pcm037_i2c1_data);
+ imx31_add_imx_i2c2(&pcm037_i2c2_data);
+
+ imx31_add_mxc_nand(&pcm037_nand_board_info);
+ imx31_add_mxc_mmc(0, &sdhc_pdata);
+ imx31_add_ipu_core(&mx3_ipu_data);
+ imx31_add_mx3_sdc_fb(&mx3fb_pdata);
+
+ /* CSI */
+ /* Camera power: default - off */
+ ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), "mt9t031-power");
+ if (!ret)
+ gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), 1);
+ else
+ iclink_mt9t031.power = NULL;
+
+ pcm037_init_camera();
+
+ platform_device_register(&pcm970_sja1000);
+
+ if (otg_mode_host) {
+ otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
+ ULPI_OTG_DRVVBUS_EXT);
+ if (otg_pdata.otg)
+ imx31_add_mxc_ehci_otg(&otg_pdata);
+ }
+
+ usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
+ ULPI_OTG_DRVVBUS_EXT);
+ if (usbh2_pdata.otg)
+ imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
+
+ if (!otg_mode_host)
+ imx31_add_fsl_usb2_udc(&otg_device_pdata);
+
+}
+
+static void __init pcm037_timer_init(void)
+{
+ mx31_clocks_init(26000000);
+}
+
+struct sys_timer pcm037_timer = {
+ .init = pcm037_timer_init,
+};
+
+static void __init pcm037_reserve(void)
+{
+ /* reserve 4 MiB for mx3-camera */
+ mx3_camera_base = memblock_alloc(MX3_CAMERA_BUF_SIZE,
+ MX3_CAMERA_BUF_SIZE);
+ memblock_free(mx3_camera_base, MX3_CAMERA_BUF_SIZE);
+ memblock_remove(mx3_camera_base, MX3_CAMERA_BUF_SIZE);
+}
+
+MACHINE_START(PCM037, "Phytec Phycore pcm037")
+ /* Maintainer: Pengutronix */
+ .boot_params = MX3x_PHYS_OFFSET + 0x100,
+ .reserve = pcm037_reserve,
+ .map_io = mx31_map_io,
+ .init_early = imx31_init_early,
+ .init_irq = mx31_init_irq,
+ .timer = &pcm037_timer,
+ .init_machine = pcm037_init,
+MACHINE_END
diff --git a/arch/arm/mach-imx/mach-pcm037_eet.c b/arch/arm/mach-imx/mach-pcm037_eet.c
new file mode 100644
index 0000000..1b7606b
--- /dev/null
+++ b/arch/arm/mach-imx/mach-pcm037_eet.c
@@ -0,0 +1,179 @@
+/*
+ * Copyright (C) 2009
+ * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/gpio.h>
+#include <linux/input.h>
+#include <linux/platform_device.h>
+#include <linux/spi/spi.h>
+
+#include <mach/common.h>
+#include <mach/iomux-mx3.h>
+
+#include <asm/mach-types.h>
+
+#include "pcm037.h"
+#include "devices-imx31.h"
+
+static unsigned int pcm037_eet_pins[] = {
+ /* Reserve and hardwire GPIO 57 high - S6E63D6 chipselect */
+ IOMUX_MODE(MX31_PIN_KEY_COL7, IOMUX_CONFIG_GPIO),
+ /* GPIO keys */
+ IOMUX_MODE(MX31_PIN_GPIO1_0, IOMUX_CONFIG_GPIO), /* 0 */
+ IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO), /* 1 */
+ IOMUX_MODE(MX31_PIN_GPIO1_2, IOMUX_CONFIG_GPIO), /* 2 */
+ IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO), /* 3 */
+ IOMUX_MODE(MX31_PIN_SVEN0, IOMUX_CONFIG_GPIO), /* 32 */
+ IOMUX_MODE(MX31_PIN_STX0, IOMUX_CONFIG_GPIO), /* 33 */
+ IOMUX_MODE(MX31_PIN_SRX0, IOMUX_CONFIG_GPIO), /* 34 */
+ IOMUX_MODE(MX31_PIN_SIMPD0, IOMUX_CONFIG_GPIO), /* 35 */
+ IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_GPIO), /* 38 */
+ IOMUX_MODE(MX31_PIN_CTS1, IOMUX_CONFIG_GPIO), /* 39 */
+ IOMUX_MODE(MX31_PIN_KEY_ROW4, IOMUX_CONFIG_GPIO), /* 50 */
+ IOMUX_MODE(MX31_PIN_KEY_ROW5, IOMUX_CONFIG_GPIO), /* 51 */
+ IOMUX_MODE(MX31_PIN_KEY_ROW6, IOMUX_CONFIG_GPIO), /* 52 */
+ IOMUX_MODE(MX31_PIN_KEY_ROW7, IOMUX_CONFIG_GPIO), /* 53 */
+
+ /* LEDs */
+ IOMUX_MODE(MX31_PIN_DTR_DTE1, IOMUX_CONFIG_GPIO), /* 44 */
+ IOMUX_MODE(MX31_PIN_DSR_DTE1, IOMUX_CONFIG_GPIO), /* 45 */
+ IOMUX_MODE(MX31_PIN_KEY_COL5, IOMUX_CONFIG_GPIO), /* 55 */
+ IOMUX_MODE(MX31_PIN_KEY_COL6, IOMUX_CONFIG_GPIO), /* 56 */
+};
+
+/* SPI */
+static struct spi_board_info pcm037_spi_dev[] = {
+ {
+ .modalias = "dac124s085",
+ .max_speed_hz = 400000,
+ .bus_num = 0,
+ .chip_select = 0, /* Index in pcm037_spi1_cs[] */
+ .mode = SPI_CPHA,
+ },
+};
+
+/* Platform Data for MXC CSPI */
+static int pcm037_spi1_cs[] = {MXC_SPI_CS(1), IOMUX_TO_GPIO(MX31_PIN_KEY_COL7)};
+
+static const struct spi_imx_master pcm037_spi1_pdata __initconst = {
+ .chipselect = pcm037_spi1_cs,
+ .num_chipselect = ARRAY_SIZE(pcm037_spi1_cs),
+};
+
+/* GPIO-keys input device */
+static struct gpio_keys_button pcm037_gpio_keys[] = {
+ {
+ .type = EV_KEY,
+ .code = KEY_L,
+ .gpio = 0,
+ .desc = "Wheel Manual",
+ .wakeup = 0,
+ }, {
+ .type = EV_KEY,
+ .code = KEY_A,
+ .gpio = 1,
+ .desc = "Wheel AF",
+ .wakeup = 0,
+ }, {
+ .type = EV_KEY,
+ .code = KEY_V,
+ .gpio = 2,
+ .desc = "Wheel View",
+ .wakeup = 0,
+ }, {
+ .type = EV_KEY,
+ .code = KEY_M,
+ .gpio = 3,
+ .desc = "Wheel Menu",
+ .wakeup = 0,
+ }, {
+ .type = EV_KEY,
+ .code = KEY_UP,
+ .gpio = 32,
+ .desc = "Nav Pad Up",
+ .wakeup = 0,
+ }, {
+ .type = EV_KEY,
+ .code = KEY_RIGHT,
+ .gpio = 33,
+ .desc = "Nav Pad Right",
+ .wakeup = 0,
+ }, {
+ .type = EV_KEY,
+ .code = KEY_DOWN,
+ .gpio = 34,
+ .desc = "Nav Pad Down",
+ .wakeup = 0,
+ }, {
+ .type = EV_KEY,
+ .code = KEY_LEFT,
+ .gpio = 35,
+ .desc = "Nav Pad Left",
+ .wakeup = 0,
+ }, {
+ .type = EV_KEY,
+ .code = KEY_ENTER,
+ .gpio = 38,
+ .desc = "Nav Pad Ok",
+ .wakeup = 0,
+ }, {
+ .type = EV_KEY,
+ .code = KEY_O,
+ .gpio = 39,
+ .desc = "Wheel Off",
+ .wakeup = 0,
+ }, {
+ .type = EV_KEY,
+ .code = BTN_FORWARD,
+ .gpio = 50,
+ .desc = "Focus Forward",
+ .wakeup = 0,
+ }, {
+ .type = EV_KEY,
+ .code = BTN_BACK,
+ .gpio = 51,
+ .desc = "Focus Backward",
+ .wakeup = 0,
+ }, {
+ .type = EV_KEY,
+ .code = BTN_MIDDLE,
+ .gpio = 52,
+ .desc = "Release Half",
+ .wakeup = 0,
+ }, {
+ .type = EV_KEY,
+ .code = BTN_EXTRA,
+ .gpio = 53,
+ .desc = "Release Full",
+ .wakeup = 0,
+ },
+};
+
+static const struct gpio_keys_platform_data
+ pcm037_gpio_keys_platform_data __initconst = {
+ .buttons = pcm037_gpio_keys,
+ .nbuttons = ARRAY_SIZE(pcm037_gpio_keys),
+ .rep = 0, /* No auto-repeat */
+};
+
+static int __init eet_init_devices(void)
+{
+ if (!machine_is_pcm037() || pcm037_variant() != PCM037_EET)
+ return 0;
+
+ mxc_iomux_setup_multiple_pins(pcm037_eet_pins,
+ ARRAY_SIZE(pcm037_eet_pins), "pcm037_eet");
+
+ /* SPI */
+ spi_register_board_info(pcm037_spi_dev, ARRAY_SIZE(pcm037_spi_dev));
+ imx31_add_spi_imx0(&pcm037_spi1_pdata);
+
+ imx_add_gpio_keys(&pcm037_gpio_keys_platform_data);
+
+ return 0;
+}
+late_initcall(eet_init_devices);
diff --git a/arch/arm/mach-imx/mach-pcm038.c b/arch/arm/mach-imx/mach-pcm038.c
index 4cbce6d..853bb87 100644
--- a/arch/arm/mach-imx/mach-pcm038.c
+++ b/arch/arm/mach-imx/mach-pcm038.c
@@ -36,7 +36,6 @@
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-mx27.h>
-#include <mach/mxc_nand.h>
#include <mach/ulpi.h>
#include "devices-imx27.h"
diff --git a/arch/arm/mach-imx/mach-pcm043.c b/arch/arm/mach-imx/mach-pcm043.c
new file mode 100644
index 0000000..0264416
--- /dev/null
+++ b/arch/arm/mach-imx/mach-pcm043.c
@@ -0,0 +1,423 @@
+/*
+ * Copyright (C) 2009 Sascha Hauer, Pengutronix
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mtd/plat-ram.h>
+#include <linux/memory.h>
+#include <linux/gpio.h>
+#include <linux/smc911x.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <linux/i2c.h>
+#include <linux/i2c/at24.h>
+#include <linux/usb/otg.h>
+#include <linux/usb/ulpi.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/iomux-mx35.h>
+#include <mach/ulpi.h>
+#include <mach/audmux.h>
+
+#include "devices-imx35.h"
+
+static const struct fb_videomode fb_modedb[] = {
+ {
+ /* 240x320 @ 60 Hz */
+ .name = "Sharp-LQ035Q7",
+ .refresh = 60,
+ .xres = 240,
+ .yres = 320,
+ .pixclock = 185925,
+ .left_margin = 9,
+ .right_margin = 16,
+ .upper_margin = 7,
+ .lower_margin = 9,
+ .hsync_len = 1,
+ .vsync_len = 1,
+ .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE | FB_SYNC_CLK_INVERT | FB_SYNC_CLK_IDLE_EN,
+ .vmode = FB_VMODE_NONINTERLACED,
+ .flag = 0,
+ }, {
+ /* 240x320 @ 60 Hz */
+ .name = "TX090",
+ .refresh = 60,
+ .xres = 240,
+ .yres = 320,
+ .pixclock = 38255,
+ .left_margin = 144,
+ .right_margin = 0,
+ .upper_margin = 7,
+ .lower_margin = 40,
+ .hsync_len = 96,
+ .vsync_len = 1,
+ .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH,
+ .vmode = FB_VMODE_NONINTERLACED,
+ .flag = 0,
+ },
+};
+
+static const struct ipu_platform_data mx3_ipu_data __initconst = {
+ .irq_base = MXC_IPU_IRQ_START,
+};
+
+static struct mx3fb_platform_data mx3fb_pdata __initdata = {
+ .name = "Sharp-LQ035Q7",
+ .mode = fb_modedb,
+ .num_modes = ARRAY_SIZE(fb_modedb),
+};
+
+static struct physmap_flash_data pcm043_flash_data = {
+ .width = 2,
+};
+
+static struct resource pcm043_flash_resource = {
+ .start = 0xa0000000,
+ .end = 0xa1ffffff,
+ .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device pcm043_flash = {
+ .name = "physmap-flash",
+ .id = 0,
+ .dev = {
+ .platform_data = &pcm043_flash_data,
+ },
+ .resource = &pcm043_flash_resource,
+ .num_resources = 1,
+};
+
+static const struct imxuart_platform_data uart_pdata __initconst = {
+ .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static const struct imxi2c_platform_data pcm043_i2c0_data __initconst = {
+ .bitrate = 50000,
+};
+
+static struct at24_platform_data board_eeprom = {
+ .byte_len = 4096,
+ .page_size = 32,
+ .flags = AT24_FLAG_ADDR16,
+};
+
+static struct i2c_board_info pcm043_i2c_devices[] = {
+ {
+ I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
+ .platform_data = &board_eeprom,
+ }, {
+ I2C_BOARD_INFO("pcf8563", 0x51),
+ },
+};
+
+static struct platform_device *devices[] __initdata = {
+ &pcm043_flash,
+};
+
+static iomux_v3_cfg_t pcm043_pads[] = {
+ /* UART1 */
+ MX35_PAD_CTS1__UART1_CTS,
+ MX35_PAD_RTS1__UART1_RTS,
+ MX35_PAD_TXD1__UART1_TXD_MUX,
+ MX35_PAD_RXD1__UART1_RXD_MUX,
+ /* UART2 */
+ MX35_PAD_CTS2__UART2_CTS,
+ MX35_PAD_RTS2__UART2_RTS,
+ MX35_PAD_TXD2__UART2_TXD_MUX,
+ MX35_PAD_RXD2__UART2_RXD_MUX,
+ /* FEC */
+ MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
+ MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
+ MX35_PAD_FEC_RX_DV__FEC_RX_DV,
+ MX35_PAD_FEC_COL__FEC_COL,
+ MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
+ MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
+ MX35_PAD_FEC_TX_EN__FEC_TX_EN,
+ MX35_PAD_FEC_MDC__FEC_MDC,
+ MX35_PAD_FEC_MDIO__FEC_MDIO,
+ MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
+ MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
+ MX35_PAD_FEC_CRS__FEC_CRS,
+ MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
+ MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
+ MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
+ MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
+ MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
+ MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
+ /* I2C1 */
+ MX35_PAD_I2C1_CLK__I2C1_SCL,
+ MX35_PAD_I2C1_DAT__I2C1_SDA,
+ /* Display */
+ MX35_PAD_LD0__IPU_DISPB_DAT_0,
+ MX35_PAD_LD1__IPU_DISPB_DAT_1,
+ MX35_PAD_LD2__IPU_DISPB_DAT_2,
+ MX35_PAD_LD3__IPU_DISPB_DAT_3,
+ MX35_PAD_LD4__IPU_DISPB_DAT_4,
+ MX35_PAD_LD5__IPU_DISPB_DAT_5,
+ MX35_PAD_LD6__IPU_DISPB_DAT_6,
+ MX35_PAD_LD7__IPU_DISPB_DAT_7,
+ MX35_PAD_LD8__IPU_DISPB_DAT_8,
+ MX35_PAD_LD9__IPU_DISPB_DAT_9,
+ MX35_PAD_LD10__IPU_DISPB_DAT_10,
+ MX35_PAD_LD11__IPU_DISPB_DAT_11,
+ MX35_PAD_LD12__IPU_DISPB_DAT_12,
+ MX35_PAD_LD13__IPU_DISPB_DAT_13,
+ MX35_PAD_LD14__IPU_DISPB_DAT_14,
+ MX35_PAD_LD15__IPU_DISPB_DAT_15,
+ MX35_PAD_LD16__IPU_DISPB_DAT_16,
+ MX35_PAD_LD17__IPU_DISPB_DAT_17,
+ MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC,
+ MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK,
+ MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY,
+ MX35_PAD_CONTRAST__IPU_DISPB_CONTR,
+ MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC,
+ MX35_PAD_D3_REV__IPU_DISPB_D3_REV,
+ MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS,
+ /* gpio */
+ MX35_PAD_ATA_CS0__GPIO2_6,
+ /* USB host */
+ MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR,
+ MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC,
+ /* SSI */
+ MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS,
+ MX35_PAD_STXD4__AUDMUX_AUD4_TXD,
+ MX35_PAD_SRXD4__AUDMUX_AUD4_RXD,
+ MX35_PAD_SCK4__AUDMUX_AUD4_TXC,
+ /* CAN2 */
+ MX35_PAD_TX5_RX0__CAN2_TXCAN,
+ MX35_PAD_TX4_RX1__CAN2_RXCAN,
+ /* esdhc */
+ MX35_PAD_SD1_CMD__ESDHC1_CMD,
+ MX35_PAD_SD1_CLK__ESDHC1_CLK,
+ MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
+ MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
+ MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
+ MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
+ MX35_PAD_ATA_DATA10__GPIO2_23, /* WriteProtect */
+ MX35_PAD_ATA_DATA11__GPIO2_24, /* CardDetect */
+};
+
+#define AC97_GPIO_TXFS IMX_GPIO_NR(2, 31)
+#define AC97_GPIO_TXD IMX_GPIO_NR(2, 28)
+#define AC97_GPIO_RESET IMX_GPIO_NR(2, 0)
+#define SD1_GPIO_WP IMX_GPIO_NR(2, 23)
+#define SD1_GPIO_CD IMX_GPIO_NR(2, 24)
+
+static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97)
+{
+ iomux_v3_cfg_t txfs_gpio = MX35_PAD_STXFS4__GPIO2_31;
+ iomux_v3_cfg_t txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS;
+ int ret;
+
+ ret = gpio_request(AC97_GPIO_TXFS, "SSI");
+ if (ret) {
+ printk("failed to get GPIO_TXFS: %d\n", ret);
+ return;
+ }
+
+ mxc_iomux_v3_setup_pad(txfs_gpio);
+
+ /* warm reset */
+ gpio_direction_output(AC97_GPIO_TXFS, 1);
+ udelay(2);
+ gpio_set_value(AC97_GPIO_TXFS, 0);
+
+ gpio_free(AC97_GPIO_TXFS);
+ mxc_iomux_v3_setup_pad(txfs);
+}
+
+static void pcm043_ac97_cold_reset(struct snd_ac97 *ac97)
+{
+ iomux_v3_cfg_t txfs_gpio = MX35_PAD_STXFS4__GPIO2_31;
+ iomux_v3_cfg_t txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS;
+ iomux_v3_cfg_t txd_gpio = MX35_PAD_STXD4__GPIO2_28;
+ iomux_v3_cfg_t txd = MX35_PAD_STXD4__AUDMUX_AUD4_TXD;
+ iomux_v3_cfg_t reset_gpio = MX35_PAD_SD2_CMD__GPIO2_0;
+ int ret;
+
+ ret = gpio_request(AC97_GPIO_TXFS, "SSI");
+ if (ret)
+ goto err1;
+
+ ret = gpio_request(AC97_GPIO_TXD, "SSI");
+ if (ret)
+ goto err2;
+
+ ret = gpio_request(AC97_GPIO_RESET, "SSI");
+ if (ret)
+ goto err3;
+
+ mxc_iomux_v3_setup_pad(txfs_gpio);
+ mxc_iomux_v3_setup_pad(txd_gpio);
+ mxc_iomux_v3_setup_pad(reset_gpio);
+
+ gpio_direction_output(AC97_GPIO_TXFS, 0);
+ gpio_direction_output(AC97_GPIO_TXD, 0);
+
+ /* cold reset */
+ gpio_direction_output(AC97_GPIO_RESET, 0);
+ udelay(10);
+ gpio_direction_output(AC97_GPIO_RESET, 1);
+
+ mxc_iomux_v3_setup_pad(txd);
+ mxc_iomux_v3_setup_pad(txfs);
+
+ gpio_free(AC97_GPIO_RESET);
+err3:
+ gpio_free(AC97_GPIO_TXD);
+err2:
+ gpio_free(AC97_GPIO_TXFS);
+err1:
+ if (ret)
+ printk("%s failed with %d\n", __func__, ret);
+ mdelay(1);
+}
+
+static const struct imx_ssi_platform_data pcm043_ssi_pdata __initconst = {
+ .ac97_reset = pcm043_ac97_cold_reset,
+ .ac97_warm_reset = pcm043_ac97_warm_reset,
+ .flags = IMX_SSI_USE_AC97,
+};
+
+static const struct mxc_nand_platform_data
+pcm037_nand_board_info __initconst = {
+ .width = 1,
+ .hw_ecc = 1,
+};
+
+static int pcm043_otg_init(struct platform_device *pdev)
+{
+ return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
+}
+
+static struct mxc_usbh_platform_data otg_pdata __initdata = {
+ .init = pcm043_otg_init,
+ .portsc = MXC_EHCI_MODE_UTMI,
+};
+
+static int pcm043_usbh1_init(struct platform_device *pdev)
+{
+ return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_SINGLE_UNI |
+ MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN);
+}
+
+static const struct mxc_usbh_platform_data usbh1_pdata __initconst = {
+ .init = pcm043_usbh1_init,
+ .portsc = MXC_EHCI_MODE_SERIAL,
+};
+
+static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
+ .operating_mode = FSL_USB2_DR_DEVICE,
+ .phy_mode = FSL_USB2_PHY_UTMI,
+};
+
+static int otg_mode_host;
+
+static int __init pcm043_otg_mode(char *options)
+{
+ if (!strcmp(options, "host"))
+ otg_mode_host = 1;
+ else if (!strcmp(options, "device"))
+ otg_mode_host = 0;
+ else
+ pr_info("otg_mode neither \"host\" nor \"device\". "
+ "Defaulting to device\n");
+ return 0;
+}
+__setup("otg_mode=", pcm043_otg_mode);
+
+static struct esdhc_platform_data sd1_pdata = {
+ .wp_gpio = SD1_GPIO_WP,
+ .cd_gpio = SD1_GPIO_CD,
+};
+
+/*
+ * Board specific initialization.
+ */
+static void __init pcm043_init(void)
+{
+ mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads));
+
+ mxc_audmux_v2_configure_port(3,
+ MXC_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
+ MXC_AUDMUX_V2_PTCR_TFSEL(0) |
+ MXC_AUDMUX_V2_PTCR_TFSDIR,
+ MXC_AUDMUX_V2_PDCR_RXDSEL(0));
+
+ mxc_audmux_v2_configure_port(0,
+ MXC_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
+ MXC_AUDMUX_V2_PTCR_TCSEL(3) |
+ MXC_AUDMUX_V2_PTCR_TCLKDIR, /* clock is output */
+ MXC_AUDMUX_V2_PDCR_RXDSEL(3));
+
+ imx35_add_fec(NULL);
+ platform_add_devices(devices, ARRAY_SIZE(devices));
+ imx35_add_imx2_wdt(NULL);
+
+ imx35_add_imx_uart0(&uart_pdata);
+ imx35_add_mxc_nand(&pcm037_nand_board_info);
+ imx35_add_imx_ssi(0, &pcm043_ssi_pdata);
+
+ imx35_add_imx_uart1(&uart_pdata);
+
+ i2c_register_board_info(0, pcm043_i2c_devices,
+ ARRAY_SIZE(pcm043_i2c_devices));
+
+ imx35_add_imx_i2c0(&pcm043_i2c0_data);
+
+ imx35_add_ipu_core(&mx3_ipu_data);
+ imx35_add_mx3_sdc_fb(&mx3fb_pdata);
+
+ if (otg_mode_host) {
+ otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
+ ULPI_OTG_DRVVBUS_EXT);
+ if (otg_pdata.otg)
+ imx35_add_mxc_ehci_otg(&otg_pdata);
+ }
+ imx35_add_mxc_ehci_hs(&usbh1_pdata);
+
+ if (!otg_mode_host)
+ imx35_add_fsl_usb2_udc(&otg_device_pdata);
+
+ imx35_add_flexcan1(NULL);
+ imx35_add_sdhci_esdhc_imx(0, &sd1_pdata);
+}
+
+static void __init pcm043_timer_init(void)
+{
+ mx35_clocks_init();
+}
+
+struct sys_timer pcm043_timer = {
+ .init = pcm043_timer_init,
+};
+
+MACHINE_START(PCM043, "Phytec Phycore pcm043")
+ /* Maintainer: Pengutronix */
+ .boot_params = MX3x_PHYS_OFFSET + 0x100,
+ .map_io = mx35_map_io,
+ .init_early = imx35_init_early,
+ .init_irq = mx35_init_irq,
+ .timer = &pcm043_timer,
+ .init_machine = pcm043_init,
+MACHINE_END
diff --git a/arch/arm/mach-imx/mach-qong.c b/arch/arm/mach-imx/mach-qong.c
new file mode 100644
index 0000000..c1632871
--- /dev/null
+++ b/arch/arm/mach-imx/mach-qong.c
@@ -0,0 +1,269 @@
+/*
+ * Copyright (C) 2009 Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/memory.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+#include <linux/mtd/nand.h>
+#include <linux/gpio.h>
+
+#include <mach/hardware.h>
+#include <mach/irqs.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+#include <asm/mach/map.h>
+#include <mach/common.h>
+#include <asm/page.h>
+#include <asm/setup.h>
+#include <mach/iomux-mx3.h>
+
+#include "devices-imx31.h"
+
+/* FPGA defines */
+#define QONG_FPGA_VERSION(major, minor, rev) \
+ (((major & 0xF) << 12) | ((minor & 0xF) << 8) | (rev & 0xFF))
+
+#define QONG_FPGA_BASEADDR MX31_CS1_BASE_ADDR
+#define QONG_FPGA_PERIPH_SIZE (1 << 24)
+
+#define QONG_FPGA_CTRL_BASEADDR QONG_FPGA_BASEADDR
+#define QONG_FPGA_CTRL_SIZE 0x10
+/* FPGA control registers */
+#define QONG_FPGA_CTRL_VERSION 0x00
+
+#define QONG_DNET_ID 1
+#define QONG_DNET_BASEADDR \
+ (QONG_FPGA_BASEADDR + QONG_DNET_ID * QONG_FPGA_PERIPH_SIZE)
+#define QONG_DNET_SIZE 0x00001000
+
+#define QONG_FPGA_IRQ IOMUX_TO_IRQ(MX31_PIN_DTR_DCE1)
+
+static const struct imxuart_platform_data uart_pdata __initconst = {
+ .flags = IMXUART_HAVE_RTSCTS,
+};
+
+static int uart_pins[] = {
+ MX31_PIN_CTS1__CTS1,
+ MX31_PIN_RTS1__RTS1,
+ MX31_PIN_TXD1__TXD1,
+ MX31_PIN_RXD1__RXD1
+};
+
+static inline void __init mxc_init_imx_uart(void)
+{
+ mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins),
+ "uart-0");
+ imx31_add_imx_uart0(&uart_pdata);
+}
+
+static struct resource dnet_resources[] = {
+ {
+ .name = "dnet-memory",
+ .start = QONG_DNET_BASEADDR,
+ .end = QONG_DNET_BASEADDR + QONG_DNET_SIZE - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = QONG_FPGA_IRQ,
+ .end = QONG_FPGA_IRQ,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device dnet_device = {
+ .name = "dnet",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(dnet_resources),
+ .resource = dnet_resources,
+};
+
+static int __init qong_init_dnet(void)
+{
+ int ret;
+
+ ret = platform_device_register(&dnet_device);
+ return ret;
+}
+
+/* MTD NOR flash */
+
+static struct physmap_flash_data qong_flash_data = {
+ .width = 2,
+};
+
+static struct resource qong_flash_resource = {
+ .start = MX31_CS0_BASE_ADDR,
+ .end = MX31_CS0_BASE_ADDR + SZ_128M - 1,
+ .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device qong_nor_mtd_device = {
+ .name = "physmap-flash",
+ .id = 0,
+ .dev = {
+ .platform_data = &qong_flash_data,
+ },
+ .resource = &qong_flash_resource,
+ .num_resources = 1,
+};
+
+static void qong_init_nor_mtd(void)
+{
+ (void)platform_device_register(&qong_nor_mtd_device);
+}
+
+/*
+ * Hardware specific access to control-lines
+ */
+static void qong_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+{
+ struct nand_chip *nand_chip = mtd->priv;
+
+ if (cmd == NAND_CMD_NONE)
+ return;
+
+ if (ctrl & NAND_CLE)
+ writeb(cmd, nand_chip->IO_ADDR_W + (1 << 24));
+ else
+ writeb(cmd, nand_chip->IO_ADDR_W + (1 << 23));
+}
+
+/*
+ * Read the Device Ready pin.
+ */
+static int qong_nand_device_ready(struct mtd_info *mtd)
+{
+ return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_NFRB));
+}
+
+static void qong_nand_select_chip(struct mtd_info *mtd, int chip)
+{
+ if (chip >= 0)
+ gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 0);
+ else
+ gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 1);
+}
+
+static struct platform_nand_data qong_nand_data = {
+ .chip = {
+ .nr_chips = 1,
+ .chip_delay = 20,
+ .options = 0,
+ },
+ .ctrl = {
+ .cmd_ctrl = qong_nand_cmd_ctrl,
+ .dev_ready = qong_nand_device_ready,
+ .select_chip = qong_nand_select_chip,
+ }
+};
+
+static struct resource qong_nand_resource = {
+ .start = MX31_CS3_BASE_ADDR,
+ .end = MX31_CS3_BASE_ADDR + SZ_32M - 1,
+ .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device qong_nand_device = {
+ .name = "gen_nand",
+ .id = -1,
+ .dev = {
+ .platform_data = &qong_nand_data,
+ },
+ .num_resources = 1,
+ .resource = &qong_nand_resource,
+};
+
+static void __init qong_init_nand_mtd(void)
+{
+ /* init CS */
+ mx31_setup_weimcs(3, 0x00004f00, 0x20013b31, 0x00020800);
+ mxc_iomux_set_gpr(MUX_SDCTL_CSD1_SEL, true);
+
+ /* enable pin */
+ mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFCE_B, IOMUX_CONFIG_GPIO));
+ if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), "nand_enable"))
+ gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 0);
+
+ /* ready/busy pin */
+ mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFRB, IOMUX_CONFIG_GPIO));
+ if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFRB), "nand_rdy"))
+ gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_NFRB));
+
+ /* write protect pin */
+ mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFWP_B, IOMUX_CONFIG_GPIO));
+ if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFWP_B), "nand_wp"))
+ gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_NFWP_B));
+
+ platform_device_register(&qong_nand_device);
+}
+
+static void __init qong_init_fpga(void)
+{
+ void __iomem *regs;
+ u32 fpga_ver;
+
+ regs = ioremap(QONG_FPGA_CTRL_BASEADDR, QONG_FPGA_CTRL_SIZE);
+ if (!regs) {
+ printk(KERN_ERR "%s: failed to map registers, aborting.\n",
+ __func__);
+ return;
+ }
+
+ fpga_ver = readl(regs + QONG_FPGA_CTRL_VERSION);
+ iounmap(regs);
+ printk(KERN_INFO "Qong FPGA version %d.%d.%d\n",
+ (fpga_ver & 0xF000) >> 12,
+ (fpga_ver & 0x0F00) >> 8, fpga_ver & 0x00FF);
+ if (fpga_ver < QONG_FPGA_VERSION(0, 8, 7)) {
+ printk(KERN_ERR "qong: Unexpected FPGA version, FPGA-based "
+ "devices won't be registered!\n");
+ return;
+ }
+
+ /* register FPGA-based devices */
+ qong_init_nand_mtd();
+ qong_init_dnet();
+}
+
+/*
+ * Board specific initialization.
+ */
+static void __init qong_init(void)
+{
+ mxc_init_imx_uart();
+ qong_init_nor_mtd();
+ qong_init_fpga();
+}
+
+static void __init qong_timer_init(void)
+{
+ mx31_clocks_init(26000000);
+}
+
+static struct sys_timer qong_timer = {
+ .init = qong_timer_init,
+};
+
+MACHINE_START(QONG, "Dave/DENX QongEVB-LITE")
+ /* Maintainer: DENX Software Engineering GmbH */
+ .boot_params = MX3x_PHYS_OFFSET + 0x100,
+ .map_io = mx31_map_io,
+ .init_early = imx31_init_early,
+ .init_irq = mx31_init_irq,
+ .timer = &qong_timer,
+ .init_machine = qong_init,
+MACHINE_END
diff --git a/arch/arm/mach-imx/mach-vpr200.c b/arch/arm/mach-imx/mach-vpr200.c
new file mode 100644
index 0000000..d74e347
--- /dev/null
+++ b/arch/arm/mach-imx/mach-vpr200.c
@@ -0,0 +1,322 @@
+/*
+ * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2009 Marc Kleine-Budde, Pengutronix
+ * Copyright 2010 Creative Product Design
+ *
+ * Derived from mx35 3stack.
+ * Original author: Fabio Estevam <fabio.estevam@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mtd/physmap.h>
+#include <linux/memory.h>
+#include <linux/gpio.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/iomux-mx35.h>
+#include <mach/irqs.h>
+
+#include <linux/i2c.h>
+#include <linux/i2c/at24.h>
+#include <linux/mfd/mc13xxx.h>
+
+#include "devices-imx35.h"
+
+#define GPIO_LCDPWR IMX_GPIO_NR(1, 2)
+#define GPIO_PMIC_INT IMX_GPIO_NR(2, 0)
+
+#define GPIO_BUTTON1 IMX_GPIO_NR(1, 4)
+#define GPIO_BUTTON2 IMX_GPIO_NR(1, 5)
+#define GPIO_BUTTON3 IMX_GPIO_NR(1, 7)
+#define GPIO_BUTTON4 IMX_GPIO_NR(1, 8)
+#define GPIO_BUTTON5 IMX_GPIO_NR(1, 9)
+#define GPIO_BUTTON6 IMX_GPIO_NR(1, 10)
+#define GPIO_BUTTON7 IMX_GPIO_NR(1, 11)
+#define GPIO_BUTTON8 IMX_GPIO_NR(1, 12)
+
+static const struct fb_videomode fb_modedb[] = {
+ {
+ /* 800x480 @ 60 Hz */
+ .name = "PT0708048",
+ .refresh = 60,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = KHZ2PICOS(33260),
+ .left_margin = 50,
+ .right_margin = 156,
+ .upper_margin = 10,
+ .lower_margin = 10,
+ .hsync_len = 1, /* note: DE only display */
+ .vsync_len = 1, /* note: DE only display */
+ .sync = FB_SYNC_CLK_IDLE_EN | FB_SYNC_OE_ACT_HIGH,
+ .vmode = FB_VMODE_NONINTERLACED,
+ .flag = 0,
+ }, {
+ /* 800x480 @ 60 Hz */
+ .name = "CTP-CLAA070LC0ACW",
+ .refresh = 60,
+ .xres = 800,
+ .yres = 480,
+ .pixclock = KHZ2PICOS(27000),
+ .left_margin = 50,
+ .right_margin = 50, /* whole line should have 900 clocks */
+ .upper_margin = 10,
+ .lower_margin = 10, /* whole frame should have 500 lines */
+ .hsync_len = 1, /* note: DE only display */
+ .vsync_len = 1, /* note: DE only display */
+ .sync = FB_SYNC_CLK_IDLE_EN | FB_SYNC_OE_ACT_HIGH,
+ .vmode = FB_VMODE_NONINTERLACED,
+ .flag = 0,
+ }
+};
+
+static const struct ipu_platform_data mx3_ipu_data __initconst = {
+ .irq_base = MXC_IPU_IRQ_START,
+};
+
+static struct mx3fb_platform_data mx3fb_pdata __initdata = {
+ .name = "PT0708048",
+ .mode = fb_modedb,
+ .num_modes = ARRAY_SIZE(fb_modedb),
+};
+
+static struct physmap_flash_data vpr200_flash_data = {
+ .width = 2,
+};
+
+static struct resource vpr200_flash_resource = {
+ .start = MX35_CS0_BASE_ADDR,
+ .end = MX35_CS0_BASE_ADDR + SZ_64M - 1,
+ .flags = IORESOURCE_MEM,
+};
+
+static struct platform_device vpr200_flash = {
+ .name = "physmap-flash",
+ .id = 0,
+ .dev = {
+ .platform_data = &vpr200_flash_data,
+ },
+ .resource = &vpr200_flash_resource,
+ .num_resources = 1,
+};
+
+static const struct mxc_nand_platform_data
+ vpr200_nand_board_info __initconst = {
+ .width = 1,
+ .hw_ecc = 1,
+ .flash_bbt = 1,
+};
+
+#define VPR_KEY_DEBOUNCE 500
+static struct gpio_keys_button vpr200_gpio_keys_table[] = {
+ {KEY_F2, GPIO_BUTTON1, 1, "vpr-keys: F2", 0, VPR_KEY_DEBOUNCE},
+ {KEY_F3, GPIO_BUTTON2, 1, "vpr-keys: F3", 0, VPR_KEY_DEBOUNCE},
+ {KEY_F4, GPIO_BUTTON3, 1, "vpr-keys: F4", 0, VPR_KEY_DEBOUNCE},
+ {KEY_F5, GPIO_BUTTON4, 1, "vpr-keys: F5", 0, VPR_KEY_DEBOUNCE},
+ {KEY_F6, GPIO_BUTTON5, 1, "vpr-keys: F6", 0, VPR_KEY_DEBOUNCE},
+ {KEY_F7, GPIO_BUTTON6, 1, "vpr-keys: F7", 0, VPR_KEY_DEBOUNCE},
+ {KEY_F8, GPIO_BUTTON7, 1, "vpr-keys: F8", 1, VPR_KEY_DEBOUNCE},
+ {KEY_F9, GPIO_BUTTON8, 1, "vpr-keys: F9", 1, VPR_KEY_DEBOUNCE},
+};
+
+static const struct gpio_keys_platform_data
+ vpr200_gpio_keys_data __initconst = {
+ .buttons = vpr200_gpio_keys_table,
+ .nbuttons = ARRAY_SIZE(vpr200_gpio_keys_table),
+};
+
+static struct mc13xxx_platform_data vpr200_pmic = {
+ .flags = MC13XXX_USE_ADC | MC13XXX_USE_TOUCHSCREEN,
+};
+
+static const struct imxi2c_platform_data vpr200_i2c0_data __initconst = {
+ .bitrate = 50000,
+};
+
+static struct at24_platform_data vpr200_eeprom = {
+ .byte_len = 2048 / 8,
+ .page_size = 1,
+};
+
+static struct i2c_board_info vpr200_i2c_devices[] = {
+ {
+ I2C_BOARD_INFO("at24", 0x50), /* E0=0, E1=0, E2=0 */
+ .platform_data = &vpr200_eeprom,
+ }, {
+ I2C_BOARD_INFO("mc13892", 0x08),
+ .platform_data = &vpr200_pmic,
+ .irq = gpio_to_irq(GPIO_PMIC_INT),
+ }
+};
+
+static iomux_v3_cfg_t vpr200_pads[] = {
+ /* UART1 */
+ MX35_PAD_TXD1__UART1_TXD_MUX,
+ MX35_PAD_RXD1__UART1_RXD_MUX,
+ /* UART3 */
+ MX35_PAD_ATA_DATA10__UART3_RXD_MUX,
+ MX35_PAD_ATA_DATA11__UART3_TXD_MUX,
+ /* FEC */
+ MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
+ MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
+ MX35_PAD_FEC_RX_DV__FEC_RX_DV,
+ MX35_PAD_FEC_COL__FEC_COL,
+ MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
+ MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
+ MX35_PAD_FEC_TX_EN__FEC_TX_EN,
+ MX35_PAD_FEC_MDC__FEC_MDC,
+ MX35_PAD_FEC_MDIO__FEC_MDIO,
+ MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
+ MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
+ MX35_PAD_FEC_CRS__FEC_CRS,
+ MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
+ MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
+ MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
+ MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
+ MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
+ MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
+ /* Display */
+ MX35_PAD_LD0__IPU_DISPB_DAT_0,
+ MX35_PAD_LD1__IPU_DISPB_DAT_1,
+ MX35_PAD_LD2__IPU_DISPB_DAT_2,
+ MX35_PAD_LD3__IPU_DISPB_DAT_3,
+ MX35_PAD_LD4__IPU_DISPB_DAT_4,
+ MX35_PAD_LD5__IPU_DISPB_DAT_5,
+ MX35_PAD_LD6__IPU_DISPB_DAT_6,
+ MX35_PAD_LD7__IPU_DISPB_DAT_7,
+ MX35_PAD_LD8__IPU_DISPB_DAT_8,
+ MX35_PAD_LD9__IPU_DISPB_DAT_9,
+ MX35_PAD_LD10__IPU_DISPB_DAT_10,
+ MX35_PAD_LD11__IPU_DISPB_DAT_11,
+ MX35_PAD_LD12__IPU_DISPB_DAT_12,
+ MX35_PAD_LD13__IPU_DISPB_DAT_13,
+ MX35_PAD_LD14__IPU_DISPB_DAT_14,
+ MX35_PAD_LD15__IPU_DISPB_DAT_15,
+ MX35_PAD_LD16__IPU_DISPB_DAT_16,
+ MX35_PAD_LD17__IPU_DISPB_DAT_17,
+ MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK,
+ MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY,
+ MX35_PAD_CONTRAST__IPU_DISPB_CONTR,
+ /* LCD Enable */
+ MX35_PAD_D3_VSYNC__GPIO1_2,
+ /* USBOTG */
+ MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR,
+ MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC,
+ /* SDCARD */
+ MX35_PAD_SD1_CMD__ESDHC1_CMD,
+ MX35_PAD_SD1_CLK__ESDHC1_CLK,
+ MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
+ MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
+ MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
+ MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
+ /* PMIC */
+ MX35_PAD_GPIO2_0__GPIO2_0,
+ /* GPIO keys */
+ MX35_PAD_SCKR__GPIO1_4,
+ MX35_PAD_COMPARE__GPIO1_5,
+ MX35_PAD_SCKT__GPIO1_7,
+ MX35_PAD_FST__GPIO1_8,
+ MX35_PAD_HCKT__GPIO1_9,
+ MX35_PAD_TX5_RX0__GPIO1_10,
+ MX35_PAD_TX4_RX1__GPIO1_11,
+ MX35_PAD_TX3_RX2__GPIO1_12,
+};
+
+/* USB Device config */
+static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
+ .operating_mode = FSL_USB2_DR_DEVICE,
+ .phy_mode = FSL_USB2_PHY_UTMI,
+ .workaround = FLS_USB2_WORKAROUND_ENGCM09152,
+};
+
+static int vpr200_usbh_init(struct platform_device *pdev)
+{
+ return mx35_initialize_usb_hw(pdev->id,
+ MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY);
+}
+
+/* USB HOST config */
+static const struct mxc_usbh_platform_data usb_host_pdata __initconst = {
+ .init = vpr200_usbh_init,
+ .portsc = MXC_EHCI_MODE_SERIAL,
+};
+
+static struct platform_device *devices[] __initdata = {
+ &vpr200_flash,
+};
+
+/*
+ * Board specific initialization.
+ */
+static void __init vpr200_board_init(void)
+{
+ mxc_iomux_v3_setup_multiple_pads(vpr200_pads, ARRAY_SIZE(vpr200_pads));
+
+ imx35_add_fec(NULL);
+ imx35_add_imx2_wdt(NULL);
+ imx_add_gpio_keys(&vpr200_gpio_keys_data);
+
+ platform_add_devices(devices, ARRAY_SIZE(devices));
+
+ if (0 != gpio_request(GPIO_LCDPWR, "LCDPWR"))
+ printk(KERN_WARNING "vpr200: Couldn't get LCDPWR gpio\n");
+ else
+ gpio_direction_output(GPIO_LCDPWR, 0);
+
+ if (0 != gpio_request(GPIO_PMIC_INT, "PMIC_INT"))
+ printk(KERN_WARNING "vpr200: Couldn't get PMIC_INT gpio\n");
+ else
+ gpio_direction_input(GPIO_PMIC_INT);
+
+ imx35_add_imx_uart0(NULL);
+ imx35_add_imx_uart2(NULL);
+
+ imx35_add_ipu_core(&mx3_ipu_data);
+ imx35_add_mx3_sdc_fb(&mx3fb_pdata);
+
+ imx35_add_fsl_usb2_udc(&otg_device_pdata);
+ imx35_add_mxc_ehci_hs(&usb_host_pdata);
+
+ imx35_add_mxc_nand(&vpr200_nand_board_info);
+ imx35_add_sdhci_esdhc_imx(0, NULL);
+
+ i2c_register_board_info(0, vpr200_i2c_devices,
+ ARRAY_SIZE(vpr200_i2c_devices));
+
+ imx35_add_imx_i2c0(&vpr200_i2c0_data);
+}
+
+static void __init vpr200_timer_init(void)
+{
+ mx35_clocks_init();
+}
+
+struct sys_timer vpr200_timer = {
+ .init = vpr200_timer_init,
+};
+
+MACHINE_START(VPR200, "VPR200")
+ /* Maintainer: Creative Product Design */
+ .map_io = mx35_map_io,
+ .init_early = imx35_init_early,
+ .init_irq = mx35_init_irq,
+ .timer = &vpr200_timer,
+ .init_machine = vpr200_board_init,
+MACHINE_END
diff --git a/arch/arm/mach-imx/mm-imx31.c b/arch/arm/mach-imx/mm-imx31.c
new file mode 100644
index 0000000..86b9b45
--- /dev/null
+++ b/arch/arm/mach-imx/mm-imx31.c
@@ -0,0 +1,66 @@
+/*
+ * Copyright (C) 1999,2000 Arm Limited
+ * Copyright (C) 2000 Deep Blue Solutions Ltd
+ * Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * - add MX31 specific definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/mm.h>
+#include <linux/init.h>
+#include <linux/err.h>
+
+#include <asm/pgtable.h>
+#include <asm/mach/map.h>
+
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/iomux-v3.h>
+#include <mach/gpio.h>
+#include <mach/irqs.h>
+
+static struct map_desc mx31_io_desc[] __initdata = {
+ imx_map_entry(MX31, X_MEMC, MT_DEVICE),
+ imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED),
+ imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED),
+ imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED),
+ imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED),
+};
+
+/*
+ * This function initializes the memory map. It is called during the
+ * system startup to create static physical to virtual memory mappings
+ * for the IO modules.
+ */
+void __init mx31_map_io(void)
+{
+ iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
+}
+
+void __init imx31_init_early(void)
+{
+ mxc_set_cpu_type(MXC_CPU_MX31);
+ mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
+}
+
+static struct mxc_gpio_port imx31_gpio_ports[] = {
+ DEFINE_IMX_GPIO_PORT_IRQ(MX31, 0, 1, MX31_INT_GPIO1),
+ DEFINE_IMX_GPIO_PORT_IRQ(MX31, 1, 2, MX31_INT_GPIO2),
+ DEFINE_IMX_GPIO_PORT_IRQ(MX31, 2, 3, MX31_INT_GPIO3),
+};
+
+void __init mx31_init_irq(void)
+{
+ mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
+ mxc_gpio_init(imx31_gpio_ports, ARRAY_SIZE(imx31_gpio_ports));
+}
diff --git a/arch/arm/mach-imx/mm-imx35.c b/arch/arm/mach-imx/mm-imx35.c
new file mode 100644
index 0000000..c880e6d
--- /dev/null
+++ b/arch/arm/mach-imx/mm-imx35.c
@@ -0,0 +1,63 @@
+/*
+ * Copyright (C) 1999,2000 Arm Limited
+ * Copyright (C) 2000 Deep Blue Solutions Ltd
+ * Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * - add MX31 specific definitions
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/mm.h>
+#include <linux/init.h>
+#include <linux/err.h>
+
+#include <asm/pgtable.h>
+#include <asm/mach/map.h>
+#include <asm/hardware/cache-l2x0.h>
+
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/iomux-v3.h>
+#include <mach/gpio.h>
+#include <mach/irqs.h>
+
+static struct map_desc mx35_io_desc[] __initdata = {
+ imx_map_entry(MX35, X_MEMC, MT_DEVICE),
+ imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED),
+ imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED),
+ imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED),
+ imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED),
+};
+
+void __init mx35_map_io(void)
+{
+ iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
+}
+
+void __init imx35_init_early(void)
+{
+ mxc_set_cpu_type(MXC_CPU_MX35);
+ mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
+ mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
+}
+
+static struct mxc_gpio_port imx35_gpio_ports[] = {
+ DEFINE_IMX_GPIO_PORT_IRQ(MX35, 0, 1, MX35_INT_GPIO1),
+ DEFINE_IMX_GPIO_PORT_IRQ(MX35, 1, 2, MX35_INT_GPIO2),
+ DEFINE_IMX_GPIO_PORT_IRQ(MX35, 2, 3, MX35_INT_GPIO3),
+};
+
+void __init mx35_init_irq(void)
+{
+ mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
+ mxc_gpio_init(imx35_gpio_ports, ARRAY_SIZE(imx35_gpio_ports));
+}
diff --git a/arch/arm/mach-imx/mx31lilly-db.c b/arch/arm/mach-imx/mx31lilly-db.c
new file mode 100644
index 0000000..7d26f76
--- /dev/null
+++ b/arch/arm/mach-imx/mx31lilly-db.c
@@ -0,0 +1,216 @@
+/*
+ * LILLY-1131 development board support
+ *
+ * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
+ *
+ * based on code for other MX31 boards,
+ *
+ * Copyright 2005-2007 Freescale Semiconductor
+ * Copyright (c) 2009 Alberto Panizzo <maramaopercheseimorto@gmail.com>
+ * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/gpio.h>
+#include <linux/platform_device.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/iomux-mx3.h>
+#include <mach/board-mx31lilly.h>
+
+#include "devices-imx31.h"
+
+/*
+ * This file contains board-specific initialization routines for the
+ * LILLY-1131 development board. If you design an own baseboard for the
+ * module, use this file as base for support code.
+ */
+
+static unsigned int lilly_db_board_pins[] __initdata = {
+ MX31_PIN_CTS1__CTS1,
+ MX31_PIN_RTS1__RTS1,
+ MX31_PIN_TXD1__TXD1,
+ MX31_PIN_RXD1__RXD1,
+ MX31_PIN_CTS2__CTS2,
+ MX31_PIN_RTS2__RTS2,
+ MX31_PIN_TXD2__TXD2,
+ MX31_PIN_RXD2__RXD2,
+ MX31_PIN_CSPI3_MOSI__RXD3,
+ MX31_PIN_CSPI3_MISO__TXD3,
+ MX31_PIN_CSPI3_SCLK__RTS3,
+ MX31_PIN_CSPI3_SPI_RDY__CTS3,
+ MX31_PIN_SD1_DATA3__SD1_DATA3,
+ MX31_PIN_SD1_DATA2__SD1_DATA2,
+ MX31_PIN_SD1_DATA1__SD1_DATA1,
+ MX31_PIN_SD1_DATA0__SD1_DATA0,
+ MX31_PIN_SD1_CLK__SD1_CLK,
+ MX31_PIN_SD1_CMD__SD1_CMD,
+ MX31_PIN_LD0__LD0,
+ MX31_PIN_LD1__LD1,
+ MX31_PIN_LD2__LD2,
+ MX31_PIN_LD3__LD3,
+ MX31_PIN_LD4__LD4,
+ MX31_PIN_LD5__LD5,
+ MX31_PIN_LD6__LD6,
+ MX31_PIN_LD7__LD7,
+ MX31_PIN_LD8__LD8,
+ MX31_PIN_LD9__LD9,
+ MX31_PIN_LD10__LD10,
+ MX31_PIN_LD11__LD11,
+ MX31_PIN_LD12__LD12,
+ MX31_PIN_LD13__LD13,
+ MX31_PIN_LD14__LD14,
+ MX31_PIN_LD15__LD15,
+ MX31_PIN_LD16__LD16,
+ MX31_PIN_LD17__LD17,
+ MX31_PIN_VSYNC3__VSYNC3,
+ MX31_PIN_HSYNC__HSYNC,
+ MX31_PIN_FPSHIFT__FPSHIFT,
+ MX31_PIN_DRDY0__DRDY0,
+ MX31_PIN_CONTRAST__CONTRAST,
+};
+
+/* UART */
+static const struct imxuart_platform_data uart_pdata __initconst = {
+ .flags = IMXUART_HAVE_RTSCTS,
+};
+
+/* MMC support */
+
+static int mxc_mmc1_get_ro(struct device *dev)
+{
+ return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_LCS0));
+}
+
+static int gpio_det, gpio_wp;
+
+#define MMC_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
+ PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
+
+static int mxc_mmc1_init(struct device *dev,
+ irq_handler_t detect_irq, void *data)
+{
+ int ret;
+
+ gpio_det = IOMUX_TO_GPIO(MX31_PIN_GPIO1_1);
+ gpio_wp = IOMUX_TO_GPIO(MX31_PIN_LCS0);
+
+ mxc_iomux_set_pad(MX31_PIN_SD1_DATA0, MMC_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_SD1_DATA1, MMC_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_SD1_DATA2, MMC_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_SD1_DATA3, MMC_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_SD1_CLK, MMC_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_SD1_CMD, MMC_PAD_CFG);
+
+ ret = gpio_request(gpio_det, "MMC detect");
+ if (ret)
+ return ret;
+
+ ret = gpio_request(gpio_wp, "MMC w/p");
+ if (ret)
+ goto exit_free_det;
+
+ gpio_direction_input(gpio_det);
+ gpio_direction_input(gpio_wp);
+
+ ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO1_1), detect_irq,
+ IRQF_DISABLED | IRQF_TRIGGER_FALLING,
+ "MMC detect", data);
+ if (ret)
+ goto exit_free_wp;
+
+ return 0;
+
+exit_free_wp:
+ gpio_free(gpio_wp);
+
+exit_free_det:
+ gpio_free(gpio_det);
+
+ return ret;
+}
+
+static void mxc_mmc1_exit(struct device *dev, void *data)
+{
+ gpio_free(gpio_det);
+ gpio_free(gpio_wp);
+ free_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO1_1), data);
+}
+
+static const struct imxmmc_platform_data mmc_pdata __initconst = {
+ .get_ro = mxc_mmc1_get_ro,
+ .init = mxc_mmc1_init,
+ .exit = mxc_mmc1_exit,
+};
+
+/* Framebuffer support */
+static const struct ipu_platform_data ipu_data __initconst = {
+ .irq_base = MXC_IPU_IRQ_START,
+};
+
+static const struct fb_videomode fb_modedb = {
+ /* 640x480 TFT panel (IPS-056T) */
+ .name = "CRT-VGA",
+ .refresh = 64,
+ .xres = 640,
+ .yres = 480,
+ .pixclock = 30000,
+ .left_margin = 200,
+ .right_margin = 2,
+ .upper_margin = 2,
+ .lower_margin = 2,
+ .hsync_len = 3,
+ .vsync_len = 1,
+ .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH,
+ .vmode = FB_VMODE_NONINTERLACED,
+ .flag = 0,
+};
+
+static struct mx3fb_platform_data fb_pdata __initdata = {
+ .name = "CRT-VGA",
+ .mode = &fb_modedb,
+ .num_modes = 1,
+};
+
+#define LCD_VCC_EN_GPIO (7)
+
+static void __init mx31lilly_init_fb(void)
+{
+ if (gpio_request(LCD_VCC_EN_GPIO, "LCD enable") != 0) {
+ printk(KERN_WARNING "unable to request LCD_VCC_EN pin.\n");
+ return;
+ }
+
+ imx31_add_ipu_core(&ipu_data);
+ imx31_add_mx3_sdc_fb(&fb_pdata);
+ gpio_direction_output(LCD_VCC_EN_GPIO, 1);
+}
+
+void __init mx31lilly_db_init(void)
+{
+ mxc_iomux_setup_multiple_pins(lilly_db_board_pins,
+ ARRAY_SIZE(lilly_db_board_pins),
+ "development board pins");
+ imx31_add_imx_uart0(&uart_pdata);
+ imx31_add_imx_uart1(&uart_pdata);
+ imx31_add_imx_uart2(&uart_pdata);
+ imx31_add_mxc_mmc(0, &mmc_pdata);
+ mx31lilly_init_fb();
+}
diff --git a/arch/arm/mach-imx/mx31lite-db.c b/arch/arm/mach-imx/mx31lite-db.c
new file mode 100644
index 0000000..5aa053e
--- /dev/null
+++ b/arch/arm/mach-imx/mx31lite-db.c
@@ -0,0 +1,203 @@
+/*
+ * LogicPD i.MX31 SOM-LV development board support
+ *
+ * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
+ *
+ * based on code for other MX31 boards,
+ *
+ * Copyright 2005-2007 Freescale Semiconductor
+ * Copyright (c) 2009 Alberto Panizzo <maramaopercheseimorto@gmail.com>
+ * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/init.h>
+#include <linux/gpio.h>
+#include <linux/leds.h>
+#include <linux/platform_device.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+
+#include <mach/hardware.h>
+#include <mach/common.h>
+#include <mach/iomux-mx3.h>
+#include <mach/board-mx31lite.h>
+
+#include "devices-imx31.h"
+
+/*
+ * This file contains board-specific initialization routines for the
+ * LogicPD i.MX31 SOM-LV development board, aka 'LiteKit'.
+ * If you design an own baseboard for the module, use this file as base
+ * for support code.
+ */
+
+static unsigned int litekit_db_board_pins[] __initdata = {
+ /* UART1 */
+ MX31_PIN_CTS1__CTS1,
+ MX31_PIN_RTS1__RTS1,
+ MX31_PIN_TXD1__TXD1,
+ MX31_PIN_RXD1__RXD1,
+ /* SPI 0 */
+ MX31_PIN_CSPI1_SCLK__SCLK,
+ MX31_PIN_CSPI1_MOSI__MOSI,
+ MX31_PIN_CSPI1_MISO__MISO,
+ MX31_PIN_CSPI1_SPI_RDY__SPI_RDY,
+ MX31_PIN_CSPI1_SS0__SS0,
+ MX31_PIN_CSPI1_SS1__SS1,
+ MX31_PIN_CSPI1_SS2__SS2,
+ /* SDHC1 */
+ MX31_PIN_SD1_DATA0__SD1_DATA0,
+ MX31_PIN_SD1_DATA1__SD1_DATA1,
+ MX31_PIN_SD1_DATA2__SD1_DATA2,
+ MX31_PIN_SD1_DATA3__SD1_DATA3,
+ MX31_PIN_SD1_CLK__SD1_CLK,
+ MX31_PIN_SD1_CMD__SD1_CMD,
+};
+
+/* UART */
+static const struct imxuart_platform_data uart_pdata __initconst = {
+ .flags = IMXUART_HAVE_RTSCTS,
+};
+
+/* MMC */
+
+static int gpio_det, gpio_wp;
+
+#define MMC_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
+ PAD_CTL_ODE_CMOS)
+
+static int mxc_mmc1_get_ro(struct device *dev)
+{
+ return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_GPIO1_6));
+}
+
+static int mxc_mmc1_init(struct device *dev,
+ irq_handler_t detect_irq, void *data)
+{
+ int ret;
+
+ gpio_det = IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1);
+ gpio_wp = IOMUX_TO_GPIO(MX31_PIN_GPIO1_6);
+
+ mxc_iomux_set_pad(MX31_PIN_SD1_DATA0,
+ MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
+ mxc_iomux_set_pad(MX31_PIN_SD1_DATA1,
+ MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
+ mxc_iomux_set_pad(MX31_PIN_SD1_DATA2,
+ MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
+ mxc_iomux_set_pad(MX31_PIN_SD1_DATA3,
+ MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
+ mxc_iomux_set_pad(MX31_PIN_SD1_CMD,
+ MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
+ mxc_iomux_set_pad(MX31_PIN_SD1_CLK, MMC_PAD_CFG);
+
+ ret = gpio_request(gpio_det, "MMC detect");
+ if (ret)
+ return ret;
+
+ ret = gpio_request(gpio_wp, "MMC w/p");
+ if (ret)
+ goto exit_free_det;
+
+ gpio_direction_input(gpio_det);
+ gpio_direction_input(gpio_wp);
+
+ ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_DCD_DCE1), detect_irq,
+ IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
+ "MMC detect", data);
+ if (ret)
+ goto exit_free_wp;
+
+ return 0;
+
+exit_free_wp:
+ gpio_free(gpio_wp);
+
+exit_free_det:
+ gpio_free(gpio_det);
+
+ return ret;
+}
+
+static void mxc_mmc1_exit(struct device *dev, void *data)
+{
+ gpio_free(gpio_det);
+ gpio_free(gpio_wp);
+ free_irq(IOMUX_TO_IRQ(MX31_PIN_DCD_DCE1), data);
+}
+
+static const struct imxmmc_platform_data mmc_pdata __initconst = {
+ .get_ro = mxc_mmc1_get_ro,
+ .init = mxc_mmc1_init,
+ .exit = mxc_mmc1_exit,
+};
+
+/* SPI */
+
+static int spi_internal_chipselect[] = {
+ MXC_SPI_CS(0),
+ MXC_SPI_CS(1),
+ MXC_SPI_CS(2),
+};
+
+static const struct spi_imx_master spi0_pdata __initconst = {
+ .chipselect = spi_internal_chipselect,
+ .num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
+};
+
+/* GPIO LEDs */
+
+static struct gpio_led litekit_leds[] = {
+ {
+ .name = "GPIO0",
+ .gpio = IOMUX_TO_GPIO(MX31_PIN_COMPARE),
+ .active_low = 1,
+ .default_state = LEDS_GPIO_DEFSTATE_OFF,
+ },
+ {
+ .name = "GPIO1",
+ .gpio = IOMUX_TO_GPIO(MX31_PIN_CAPTURE),
+ .active_low = 1,
+ .default_state = LEDS_GPIO_DEFSTATE_OFF,
+ }
+};
+
+static struct gpio_led_platform_data litekit_led_platform_data = {
+ .leds = litekit_leds,
+ .num_leds = ARRAY_SIZE(litekit_leds),
+};
+
+static struct platform_device litekit_led_device = {
+ .name = "leds-gpio",
+ .id = -1,
+ .dev = {
+ .platform_data = &litekit_led_platform_data,
+ },
+};
+
+void __init mx31lite_db_init(void)
+{
+ mxc_iomux_setup_multiple_pins(litekit_db_board_pins,
+ ARRAY_SIZE(litekit_db_board_pins),
+ "development board pins");
+ imx31_add_imx_uart0(&uart_pdata);
+ imx31_add_mxc_mmc(0, &mmc_pdata);
+ imx31_add_spi_imx0(&spi0_pdata);
+ platform_device_register(&litekit_led_device);
+ imx31_add_imx2_wdt(NULL);
+ imx31_add_mxc_rtc(NULL);
+}
diff --git a/arch/arm/mach-imx/mx31moboard-devboard.c b/arch/arm/mach-imx/mx31moboard-devboard.c
new file mode 100644
index 0000000..0aa2536
--- /dev/null
+++ b/arch/arm/mach-imx/mx31moboard-devboard.c
@@ -0,0 +1,242 @@
+/*
+ * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/gpio.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+
+#include <linux/usb/otg.h>
+
+#include <mach/common.h>
+#include <mach/iomux-mx3.h>
+#include <mach/hardware.h>
+#include <mach/ulpi.h>
+
+#include "devices-imx31.h"
+
+static unsigned int devboard_pins[] = {
+ /* UART1 */
+ MX31_PIN_CTS2__CTS2, MX31_PIN_RTS2__RTS2,
+ MX31_PIN_TXD2__TXD2, MX31_PIN_RXD2__RXD2,
+ /* SDHC2 */
+ MX31_PIN_PC_PWRON__SD2_DATA3, MX31_PIN_PC_VS1__SD2_DATA2,
+ MX31_PIN_PC_READY__SD2_DATA1, MX31_PIN_PC_WAIT_B__SD2_DATA0,
+ MX31_PIN_PC_CD2_B__SD2_CLK, MX31_PIN_PC_CD1_B__SD2_CMD,
+ MX31_PIN_ATA_DIOR__GPIO3_28, MX31_PIN_ATA_DIOW__GPIO3_29,
+ /* USB H1 */
+ MX31_PIN_CSPI1_MISO__USBH1_RXDP, MX31_PIN_CSPI1_MOSI__USBH1_RXDM,
+ MX31_PIN_CSPI1_SS0__USBH1_TXDM, MX31_PIN_CSPI1_SS1__USBH1_TXDP,
+ MX31_PIN_CSPI1_SS2__USBH1_RCV, MX31_PIN_CSPI1_SCLK__USBH1_OEB,
+ MX31_PIN_CSPI1_SPI_RDY__USBH1_FS, MX31_PIN_SFS6__USBH1_SUSPEND,
+ MX31_PIN_NFRE_B__GPIO1_11, MX31_PIN_NFALE__GPIO1_12,
+ /* SEL */
+ MX31_PIN_DTR_DCE1__GPIO2_8, MX31_PIN_DSR_DCE1__GPIO2_9,
+ MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11,
+};
+
+static const struct imxuart_platform_data uart_pdata __initconst = {
+ .flags = IMXUART_HAVE_RTSCTS,
+};
+
+#define SDHC2_CD IOMUX_TO_GPIO(MX31_PIN_ATA_DIOR)
+#define SDHC2_WP IOMUX_TO_GPIO(MX31_PIN_ATA_DIOW)
+
+static int devboard_sdhc2_get_ro(struct device *dev)
+{
+ return !gpio_get_value(SDHC2_WP);
+}
+
+static int devboard_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
+ void *data)
+{
+ int ret;
+
+ ret = gpio_request(SDHC2_CD, "sdhc-detect");
+ if (ret)
+ return ret;
+
+ gpio_direction_input(SDHC2_CD);
+
+ ret = gpio_request(SDHC2_WP, "sdhc-wp");
+ if (ret)
+ goto err_gpio_free;
+ gpio_direction_input(SDHC2_WP);
+
+ ret = request_irq(gpio_to_irq(SDHC2_CD), detect_irq,
+ IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
+ "sdhc2-card-detect", data);
+ if (ret)
+ goto err_gpio_free_2;
+
+ return 0;
+
+err_gpio_free_2:
+ gpio_free(SDHC2_WP);
+err_gpio_free:
+ gpio_free(SDHC2_CD);
+
+ return ret;
+}
+
+static void devboard_sdhc2_exit(struct device *dev, void *data)
+{
+ free_irq(gpio_to_irq(SDHC2_CD), data);
+ gpio_free(SDHC2_WP);
+ gpio_free(SDHC2_CD);
+}
+
+static const struct imxmmc_platform_data sdhc2_pdata __initconst = {
+ .get_ro = devboard_sdhc2_get_ro,
+ .init = devboard_sdhc2_init,
+ .exit = devboard_sdhc2_exit,
+};
+
+#define SEL0 IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1)
+#define SEL1 IOMUX_TO_GPIO(MX31_PIN_DSR_DCE1)
+#define SEL2 IOMUX_TO_GPIO(MX31_PIN_RI_DCE1)
+#define SEL3 IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1)
+
+static void devboard_init_sel_gpios(void)
+{
+ if (!gpio_request(SEL0, "sel0")) {
+ gpio_direction_input(SEL0);
+ gpio_export(SEL0, true);
+ }
+
+ if (!gpio_request(SEL1, "sel1")) {
+ gpio_direction_input(SEL1);
+ gpio_export(SEL1, true);
+ }
+
+ if (!gpio_request(SEL2, "sel2")) {
+ gpio_direction_input(SEL2);
+ gpio_export(SEL2, true);
+ }
+
+ if (!gpio_request(SEL3, "sel3")) {
+ gpio_direction_input(SEL3);
+ gpio_export(SEL3, true);
+ }
+}
+#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
+ PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
+
+static int devboard_usbh1_hw_init(struct platform_device *pdev)
+{
+ mxc_iomux_set_gpr(MUX_PGP_USB_SUSPEND, true);
+
+ mxc_iomux_set_pad(MX31_PIN_CSPI1_MISO, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_CSPI1_MOSI, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_CSPI1_SS0, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_CSPI1_SS1, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_CSPI1_SS2, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_CSPI1_SCLK, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_SFS6, USB_PAD_CFG);
+
+ mdelay(10);
+
+ return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED |
+ MXC_EHCI_INTERFACE_SINGLE_UNI);
+}
+
+#define USBH1_VBUSEN_B IOMUX_TO_GPIO(MX31_PIN_NFRE_B)
+#define USBH1_MODE IOMUX_TO_GPIO(MX31_PIN_NFALE)
+
+static int devboard_isp1105_init(struct otg_transceiver *otg)
+{
+ int ret = gpio_request(USBH1_MODE, "usbh1-mode");
+ if (ret)
+ return ret;
+ /* single ended */
+ gpio_direction_output(USBH1_MODE, 0);
+
+ ret = gpio_request(USBH1_VBUSEN_B, "usbh1-vbusen");
+ if (ret) {
+ gpio_free(USBH1_MODE);
+ return ret;
+ }
+ gpio_direction_output(USBH1_VBUSEN_B, 1);
+
+ return 0;
+}
+
+
+static int devboard_isp1105_set_vbus(struct otg_transceiver *otg, bool on)
+{
+ if (on)
+ gpio_set_value(USBH1_VBUSEN_B, 0);
+ else
+ gpio_set_value(USBH1_VBUSEN_B, 1);
+
+ return 0;
+}
+
+static struct mxc_usbh_platform_data usbh1_pdata __initdata = {
+ .init = devboard_usbh1_hw_init,
+ .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL,
+};
+
+static int __init devboard_usbh1_init(void)
+{
+ struct otg_transceiver *otg;
+ struct platform_device *pdev;
+
+ otg = kzalloc(sizeof(*otg), GFP_KERNEL);
+ if (!otg)
+ return -ENOMEM;
+
+ otg->label = "ISP1105";
+ otg->init = devboard_isp1105_init;
+ otg->set_vbus = devboard_isp1105_set_vbus;
+
+ usbh1_pdata.otg = otg;
+
+ pdev = imx31_add_mxc_ehci_hs(1, &usbh1_pdata);
+ if (IS_ERR(pdev))
+ return PTR_ERR(pdev);
+
+ return 0;
+}
+
+
+static const struct fsl_usb2_platform_data usb_pdata __initconst = {
+ .operating_mode = FSL_USB2_DR_DEVICE,
+ .phy_mode = FSL_USB2_PHY_ULPI,
+};
+
+/*
+ * system init for baseboard usage. Will be called by mx31moboard init.
+ */
+void __init mx31moboard_devboard_init(void)
+{
+ printk(KERN_INFO "Initializing mx31devboard peripherals\n");
+
+ mxc_iomux_setup_multiple_pins(devboard_pins, ARRAY_SIZE(devboard_pins),
+ "devboard");
+
+ imx31_add_imx_uart1(&uart_pdata);
+
+ imx31_add_mxc_mmc(1, &sdhc2_pdata);
+
+ devboard_init_sel_gpios();
+
+ imx31_add_fsl_usb2_udc(&usb_pdata);
+
+ devboard_usbh1_init();
+}
diff --git a/arch/arm/mach-imx/mx31moboard-marxbot.c b/arch/arm/mach-imx/mx31moboard-marxbot.c
new file mode 100644
index 0000000..bb639cb
--- /dev/null
+++ b/arch/arm/mach-imx/mx31moboard-marxbot.c
@@ -0,0 +1,366 @@
+/*
+ * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/i2c.h>
+#include <linux/spi/spi.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/types.h>
+
+#include <linux/usb/otg.h>
+
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/iomux-mx3.h>
+#include <mach/ulpi.h>
+
+#include <media/soc_camera.h>
+
+#include "devices-imx31.h"
+
+static unsigned int marxbot_pins[] = {
+ /* SDHC2 */
+ MX31_PIN_PC_PWRON__SD2_DATA3, MX31_PIN_PC_VS1__SD2_DATA2,
+ MX31_PIN_PC_READY__SD2_DATA1, MX31_PIN_PC_WAIT_B__SD2_DATA0,
+ MX31_PIN_PC_CD2_B__SD2_CLK, MX31_PIN_PC_CD1_B__SD2_CMD,
+ MX31_PIN_ATA_DIOR__GPIO3_28, MX31_PIN_ATA_DIOW__GPIO3_29,
+ /* CSI */
+ MX31_PIN_CSI_D6__CSI_D6, MX31_PIN_CSI_D7__CSI_D7,
+ MX31_PIN_CSI_D8__CSI_D8, MX31_PIN_CSI_D9__CSI_D9,
+ MX31_PIN_CSI_D10__CSI_D10, MX31_PIN_CSI_D11__CSI_D11,
+ MX31_PIN_CSI_D12__CSI_D12, MX31_PIN_CSI_D13__CSI_D13,
+ MX31_PIN_CSI_D14__CSI_D14, MX31_PIN_CSI_D15__CSI_D15,
+ MX31_PIN_CSI_HSYNC__CSI_HSYNC, MX31_PIN_CSI_MCLK__CSI_MCLK,
+ MX31_PIN_CSI_PIXCLK__CSI_PIXCLK, MX31_PIN_CSI_VSYNC__CSI_VSYNC,
+ MX31_PIN_CSI_D4__GPIO3_4, MX31_PIN_CSI_D5__GPIO3_5,
+ MX31_PIN_GPIO3_0__GPIO3_0, MX31_PIN_GPIO3_1__GPIO3_1,
+ MX31_PIN_TXD2__GPIO1_28,
+ /* dsPIC resets */
+ MX31_PIN_STXD5__GPIO1_21, MX31_PIN_SRXD5__GPIO1_22,
+ /*battery detection */
+ MX31_PIN_LCS0__GPIO3_23,
+ /* USB H1 */
+ MX31_PIN_CSPI1_MISO__USBH1_RXDP, MX31_PIN_CSPI1_MOSI__USBH1_RXDM,
+ MX31_PIN_CSPI1_SS0__USBH1_TXDM, MX31_PIN_CSPI1_SS1__USBH1_TXDP,
+ MX31_PIN_CSPI1_SS2__USBH1_RCV, MX31_PIN_CSPI1_SCLK__USBH1_OEB,
+ MX31_PIN_CSPI1_SPI_RDY__USBH1_FS, MX31_PIN_SFS6__USBH1_SUSPEND,
+ MX31_PIN_NFRE_B__GPIO1_11, MX31_PIN_NFALE__GPIO1_12,
+ /* SEL */
+ MX31_PIN_DTR_DCE1__GPIO2_8, MX31_PIN_DSR_DCE1__GPIO2_9,
+ MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11,
+};
+
+#define SDHC2_CD IOMUX_TO_GPIO(MX31_PIN_ATA_DIOR)
+#define SDHC2_WP IOMUX_TO_GPIO(MX31_PIN_ATA_DIOW)
+
+static int marxbot_sdhc2_get_ro(struct device *dev)
+{
+ return !gpio_get_value(SDHC2_WP);
+}
+
+static int marxbot_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
+ void *data)
+{
+ int ret;
+
+ ret = gpio_request(SDHC2_CD, "sdhc-detect");
+ if (ret)
+ return ret;
+
+ gpio_direction_input(SDHC2_CD);
+
+ ret = gpio_request(SDHC2_WP, "sdhc-wp");
+ if (ret)
+ goto err_gpio_free;
+ gpio_direction_input(SDHC2_WP);
+
+ ret = request_irq(gpio_to_irq(SDHC2_CD), detect_irq,
+ IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
+ "sdhc2-card-detect", data);
+ if (ret)
+ goto err_gpio_free_2;
+
+ return 0;
+
+err_gpio_free_2:
+ gpio_free(SDHC2_WP);
+err_gpio_free:
+ gpio_free(SDHC2_CD);
+
+ return ret;
+}
+
+static void marxbot_sdhc2_exit(struct device *dev, void *data)
+{
+ free_irq(gpio_to_irq(SDHC2_CD), data);
+ gpio_free(SDHC2_WP);
+ gpio_free(SDHC2_CD);
+}
+
+static const struct imxmmc_platform_data sdhc2_pdata __initconst = {
+ .get_ro = marxbot_sdhc2_get_ro,
+ .init = marxbot_sdhc2_init,
+ .exit = marxbot_sdhc2_exit,
+};
+
+#define TRSLAT_RST_B IOMUX_TO_GPIO(MX31_PIN_STXD5)
+#define DSPICS_RST_B IOMUX_TO_GPIO(MX31_PIN_SRXD5)
+
+static void dspics_resets_init(void)
+{
+ if (!gpio_request(TRSLAT_RST_B, "translator-rst")) {
+ gpio_direction_output(TRSLAT_RST_B, 0);
+ gpio_export(TRSLAT_RST_B, false);
+ }
+
+ if (!gpio_request(DSPICS_RST_B, "dspics-rst")) {
+ gpio_direction_output(DSPICS_RST_B, 0);
+ gpio_export(DSPICS_RST_B, false);
+ }
+}
+
+static struct spi_board_info marxbot_spi_board_info[] __initdata = {
+ {
+ .modalias = "spidev",
+ .max_speed_hz = 300000,
+ .bus_num = 1,
+ .chip_select = 1, /* according spi1_cs[] ! */
+ },
+};
+
+#define TURRETCAM_POWER IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)
+#define BASECAM_POWER IOMUX_TO_GPIO(MX31_PIN_CSI_D5)
+#define TURRETCAM_RST_B IOMUX_TO_GPIO(MX31_PIN_GPIO3_0)
+#define BASECAM_RST_B IOMUX_TO_GPIO(MX31_PIN_CSI_D4)
+#define CAM_CHOICE IOMUX_TO_GPIO(MX31_PIN_TXD2)
+
+static int marxbot_basecam_power(struct device *dev, int on)
+{
+ gpio_set_value(BASECAM_POWER, !on);
+ return 0;
+}
+
+static int marxbot_basecam_reset(struct device *dev)
+{
+ gpio_set_value(BASECAM_RST_B, 0);
+ udelay(100);
+ gpio_set_value(BASECAM_RST_B, 1);
+ return 0;
+}
+
+static struct i2c_board_info marxbot_i2c_devices[] = {
+ {
+ I2C_BOARD_INFO("mt9t031", 0x5d),
+ },
+};
+
+static struct soc_camera_link base_iclink = {
+ .bus_id = 0, /* Must match with the camera ID */
+ .power = marxbot_basecam_power,
+ .reset = marxbot_basecam_reset,
+ .board_info = &marxbot_i2c_devices[0],
+ .i2c_adapter_id = 0,
+};
+
+static struct platform_device marxbot_camera[] = {
+ {
+ .name = "soc-camera-pdrv",
+ .id = 0,
+ .dev = {
+ .platform_data = &base_iclink,
+ },
+ },
+};
+
+static struct platform_device *marxbot_cameras[] __initdata = {
+ &marxbot_camera[0],
+};
+
+static int __init marxbot_cam_init(void)
+{
+ int ret = gpio_request(CAM_CHOICE, "cam-choice");
+ if (ret)
+ return ret;
+ gpio_direction_output(CAM_CHOICE, 0);
+
+ ret = gpio_request(BASECAM_RST_B, "basecam-reset");
+ if (ret)
+ return ret;
+ gpio_direction_output(BASECAM_RST_B, 1);
+ ret = gpio_request(BASECAM_POWER, "basecam-standby");
+ if (ret)
+ return ret;
+ gpio_direction_output(BASECAM_POWER, 0);
+
+ ret = gpio_request(TURRETCAM_RST_B, "turretcam-reset");
+ if (ret)
+ return ret;
+ gpio_direction_output(TURRETCAM_RST_B, 1);
+ ret = gpio_request(TURRETCAM_POWER, "turretcam-standby");
+ if (ret)
+ return ret;
+ gpio_direction_output(TURRETCAM_POWER, 0);
+
+ return 0;
+}
+
+#define SEL0 IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1)
+#define SEL1 IOMUX_TO_GPIO(MX31_PIN_DSR_DCE1)
+#define SEL2 IOMUX_TO_GPIO(MX31_PIN_RI_DCE1)
+#define SEL3 IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1)
+
+static void marxbot_init_sel_gpios(void)
+{
+ if (!gpio_request(SEL0, "sel0")) {
+ gpio_direction_input(SEL0);
+ gpio_export(SEL0, true);
+ }
+
+ if (!gpio_request(SEL1, "sel1")) {
+ gpio_direction_input(SEL1);
+ gpio_export(SEL1, true);
+ }
+
+ if (!gpio_request(SEL2, "sel2")) {
+ gpio_direction_input(SEL2);
+ gpio_export(SEL2, true);
+ }
+
+ if (!gpio_request(SEL3, "sel3")) {
+ gpio_direction_input(SEL3);
+ gpio_export(SEL3, true);
+ }
+}
+
+#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
+ PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
+
+static int marxbot_usbh1_hw_init(struct platform_device *pdev)
+{
+ mxc_iomux_set_gpr(MUX_PGP_USB_SUSPEND, true);
+
+ mxc_iomux_set_pad(MX31_PIN_CSPI1_MISO, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_CSPI1_MOSI, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_CSPI1_SS0, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_CSPI1_SS1, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_CSPI1_SS2, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_CSPI1_SCLK, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, USB_PAD_CFG);
+ mxc_iomux_set_pad(MX31_PIN_SFS6, USB_PAD_CFG);
+
+ mdelay(10);
+
+ return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED |
+ MXC_EHCI_INTERFACE_SINGLE_UNI);
+}
+
+#define USBH1_VBUSEN_B IOMUX_TO_GPIO(MX31_PIN_NFRE_B)
+#define USBH1_MODE IOMUX_TO_GPIO(MX31_PIN_NFALE)
+
+static int marxbot_isp1105_init(struct otg_transceiver *otg)
+{
+ int ret = gpio_request(USBH1_MODE, "usbh1-mode");
+ if (ret)
+ return ret;
+ /* single ended */
+ gpio_direction_output(USBH1_MODE, 0);
+
+ ret = gpio_request(USBH1_VBUSEN_B, "usbh1-vbusen");
+ if (ret) {
+ gpio_free(USBH1_MODE);
+ return ret;
+ }
+ gpio_direction_output(USBH1_VBUSEN_B, 1);
+
+ return 0;
+}
+
+
+static int marxbot_isp1105_set_vbus(struct otg_transceiver *otg, bool on)
+{
+ if (on)
+ gpio_set_value(USBH1_VBUSEN_B, 0);
+ else
+ gpio_set_value(USBH1_VBUSEN_B, 1);
+
+ return 0;
+}
+
+static struct mxc_usbh_platform_data usbh1_pdata __initdata = {
+ .init = marxbot_usbh1_hw_init,
+ .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL,
+};
+
+static int __init marxbot_usbh1_init(void)
+{
+ struct otg_transceiver *otg;
+ struct platform_device *pdev;
+
+ otg = kzalloc(sizeof(*otg), GFP_KERNEL);
+ if (!otg)
+ return -ENOMEM;
+
+ otg->label = "ISP1105";
+ otg->init = marxbot_isp1105_init;
+ otg->set_vbus = marxbot_isp1105_set_vbus;
+
+ usbh1_pdata.otg = otg;
+
+ pdev = imx31_add_mxc_ehci_hs(1, &usbh1_pdata);
+ if (IS_ERR(pdev))
+ return PTR_ERR(pdev);
+
+ return 0;
+}
+
+static const struct fsl_usb2_platform_data usb_pdata __initconst = {
+ .operating_mode = FSL_USB2_DR_DEVICE,
+ .phy_mode = FSL_USB2_PHY_ULPI,
+};
+
+/*
+ * system init for baseboard usage. Will be called by mx31moboard init.
+ */
+void __init mx31moboard_marxbot_init(void)
+{
+ printk(KERN_INFO "Initializing mx31marxbot peripherals\n");
+
+ mxc_iomux_setup_multiple_pins(marxbot_pins, ARRAY_SIZE(marxbot_pins),
+ "marxbot");
+
+ marxbot_init_sel_gpios();
+
+ dspics_resets_init();
+
+ imx31_add_mxc_mmc(1, &sdhc2_pdata);
+
+ spi_register_board_info(marxbot_spi_board_info,
+ ARRAY_SIZE(marxbot_spi_board_info));
+
+ marxbot_cam_init();
+ platform_add_devices(marxbot_cameras, ARRAY_SIZE(marxbot_cameras));
+
+ /* battery present pin */
+ gpio_request(IOMUX_TO_GPIO(MX31_PIN_LCS0), "bat-present");
+ gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_LCS0));
+ gpio_export(IOMUX_TO_GPIO(MX31_PIN_LCS0), false);
+
+ imx31_add_fsl_usb2_udc(&usb_pdata);
+
+ marxbot_usbh1_init();
+}
diff --git a/arch/arm/mach-imx/mx31moboard-smartbot.c b/arch/arm/mach-imx/mx31moboard-smartbot.c
new file mode 100644
index 0000000..fabb801
--- /dev/null
+++ b/arch/arm/mach-imx/mx31moboard-smartbot.c
@@ -0,0 +1,209 @@
+/*
+ * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/delay.h>
+#include <linux/gpio.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/i2c.h>
+#include <linux/platform_device.h>
+#include <linux/types.h>
+
+#include <linux/usb/otg.h>
+#include <linux/usb/ulpi.h>
+
+#include <mach/common.h>
+#include <mach/hardware.h>
+#include <mach/iomux-mx3.h>
+#include <mach/board-mx31moboard.h>
+#include <mach/ulpi.h>
+
+#include <media/soc_camera.h>
+
+#include "devices-imx31.h"
+
+static unsigned int smartbot_pins[] = {
+ /* UART1 */
+ MX31_PIN_CTS2__CTS2, MX31_PIN_RTS2__RTS2,
+ MX31_PIN_TXD2__TXD2, MX31_PIN_RXD2__RXD2,
+ /* CSI */
+ MX31_PIN_CSI_D4__CSI_D4, MX31_PIN_CSI_D5__CSI_D5,
+ MX31_PIN_CSI_D6__CSI_D6, MX31_PIN_CSI_D7__CSI_D7,
+ MX31_PIN_CSI_D8__CSI_D8, MX31_PIN_CSI_D9__CSI_D9,
+ MX31_PIN_CSI_D10__CSI_D10, MX31_PIN_CSI_D11__CSI_D11,
+ MX31_PIN_CSI_D12__CSI_D12, MX31_PIN_CSI_D13__CSI_D13,
+ MX31_PIN_CSI_D14__CSI_D14, MX31_PIN_CSI_D15__CSI_D15,
+ MX31_PIN_CSI_HSYNC__CSI_HSYNC, MX31_PIN_CSI_MCLK__CSI_MCLK,
+ MX31_PIN_CSI_PIXCLK__CSI_PIXCLK, MX31_PIN_CSI_VSYNC__CSI_VSYNC,
+ MX31_PIN_GPIO3_0__GPIO3_0, MX31_PIN_GPIO3_1__GPIO3_1,
+ /* ENABLES */
+ MX31_PIN_DTR_DCE1__GPIO2_8, MX31_PIN_DSR_DCE1__GPIO2_9,
+ MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11,
+};
+
+static const struct imxuart_platform_data uart_pdata __initconst = {
+ .flags = IMXUART_HAVE_RTSCTS,
+};
+
+#define CAM_POWER IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)
+#define CAM_RST_B IOMUX_TO_GPIO(MX31_PIN_GPIO3_0)
+
+static int smartbot_cam_power(struct device *dev, int on)
+{
+ gpio_set_value(CAM_POWER, !on);
+ return 0;
+}
+
+static int smartbot_cam_reset(struct device *dev)
+{
+ gpio_set_value(CAM_RST_B, 0);
+ udelay(100);
+ gpio_set_value(CAM_RST_B, 1);
+ return 0;
+}
+
+static struct i2c_board_info smartbot_i2c_devices[] = {
+ {
+ I2C_BOARD_INFO("mt9t031", 0x5d),
+ },
+};
+
+static struct soc_camera_link base_iclink = {
+ .bus_id = 0, /* Must match with the camera ID */
+ .power = smartbot_cam_power,
+ .reset = smartbot_cam_reset,
+ .board_info = &smartbot_i2c_devices[0],
+ .i2c_adapter_id = 0,
+};
+
+static struct platform_device smartbot_camera[] = {
+ {
+ .name = "soc-camera-pdrv",
+ .id = 0,
+ .dev = {
+ .platform_data = &base_iclink,
+ },
+ },
+};
+
+static struct platform_device *smartbot_cameras[] __initdata = {
+ &smartbot_camera[0],
+};
+
+static int __init smartbot_cam_init(void)
+{
+ int ret = gpio_request(CAM_RST_B, "cam-reset");
+ if (ret)
+ return ret;
+ gpio_direction_output(CAM_RST_B, 1);
+ ret = gpio_request(CAM_POWER, "cam-standby");
+ if (ret)
+ return ret;
+ gpio_direction_output(CAM_POWER, 0);
+
+ return 0;
+}
+
+static const struct fsl_usb2_platform_data usb_pdata __initconst = {
+ .operating_mode = FSL_USB2_DR_DEVICE,
+ .phy_mode = FSL_USB2_PHY_ULPI,
+};
+
+#if defined(CONFIG_USB_ULPI)
+
+static int smartbot_otg_init(struct platform_device *pdev)
+{
+ return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
+}
+
+static struct mxc_usbh_platform_data otg_host_pdata __initdata = {
+ .init = smartbot_otg_init,
+ .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
+};
+
+static int __init smartbot_otg_host_init(void)
+{
+ struct platform_device *pdev;
+
+ otg_host_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
+ ULPI_OTG_DRVVBUS_EXT);
+ if (!otg_host_pdata.otg)
+ return -ENODEV;
+
+ pdev = imx31_add_mxc_ehci_otg(&otg_host_pdata);
+ if (IS_ERR(pdev))
+ return PTR_ERR(pdev);
+
+ return 0;
+}
+#else
+static inline int smartbot_otg_host_init(void) { return 0; }
+#endif
+
+#define POWER_EN IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1)
+#define DSPIC_RST_B IOMUX_TO_GPIO(MX31_PIN_DSR_DCE1)
+#define TRSLAT_RST_B IOMUX_TO_GPIO(MX31_PIN_RI_DCE1)
+#define TRSLAT_SRC_CHOICE IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1)
+
+static void smartbot_resets_init(void)
+{
+ if (!gpio_request(POWER_EN, "power-enable")) {
+ gpio_direction_output(POWER_EN, 0);
+ gpio_export(POWER_EN, false);
+ }
+
+ if (!gpio_request(DSPIC_RST_B, "dspic-rst")) {
+ gpio_direction_output(DSPIC_RST_B, 0);
+ gpio_export(DSPIC_RST_B, false);
+ }
+
+ if (!gpio_request(TRSLAT_RST_B, "translator-rst")) {
+ gpio_direction_output(TRSLAT_RST_B, 0);
+ gpio_export(TRSLAT_RST_B, false);
+ }
+
+ if (!gpio_request(TRSLAT_SRC_CHOICE, "translator-src-choice")) {
+ gpio_direction_output(TRSLAT_SRC_CHOICE, 0);
+ gpio_export(TRSLAT_SRC_CHOICE, false);
+ }
+}
+/*
+ * system init for baseboard usage. Will be called by mx31moboard init.
+ */
+void __init mx31moboard_smartbot_init(int board)
+{
+ printk(KERN_INFO "Initializing mx31smartbot peripherals\n");
+
+ mxc_iomux_setup_multiple_pins(smartbot_pins, ARRAY_SIZE(smartbot_pins),
+ "smartbot");
+
+ imx31_add_imx_uart1(&uart_pdata);
+
+ switch (board) {
+ case MX31SMARTBOT:
+ imx31_add_fsl_usb2_udc(&usb_pdata);
+ break;
+ case MX31EYEBOT:
+ smartbot_otg_host_init();
+ break;
+ default:
+ printk(KERN_WARNING "Unknown board %d, USB OTG not initialized",
+ board);
+ }
+
+ smartbot_resets_init();
+
+ smartbot_cam_init();
+ platform_add_devices(smartbot_cameras, ARRAY_SIZE(smartbot_cameras));
+}
diff --git a/arch/arm/mach-mx3/pcm037.h b/arch/arm/mach-imx/pcm037.h
similarity index 100%
rename from arch/arm/mach-mx3/pcm037.h
rename to arch/arm/mach-imx/pcm037.h
diff --git a/arch/arm/mach-integrator/Kconfig b/arch/arm/mach-integrator/Kconfig
index d701d32..dfd18f3 100644
--- a/arch/arm/mach-integrator/Kconfig
+++ b/arch/arm/mach-integrator/Kconfig
@@ -4,6 +4,7 @@
config ARCH_INTEGRATOR_AP
bool "Support Integrator/AP and Integrator/PP2 platforms"
+ select CLKSRC_MMIO
select MIGHT_HAVE_PCI
help
Include support for the ARM(R) Integrator/AP and
diff --git a/arch/arm/mach-integrator/integrator_ap.c b/arch/arm/mach-integrator/integrator_ap.c
index d3e9645..2fbbdd5 100644
--- a/arch/arm/mach-integrator/integrator_ap.c
+++ b/arch/arm/mach-integrator/integrator_ap.c
@@ -31,6 +31,7 @@
#include <linux/clockchips.h>
#include <linux/interrupt.h>
#include <linux/io.h>
+#include <linux/mtd/physmap.h>
#include <mach/hardware.h>
#include <mach/platform.h>
@@ -43,7 +44,6 @@
#include <mach/lm.h>
#include <asm/mach/arch.h>
-#include <asm/mach/flash.h>
#include <asm/mach/irq.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
@@ -222,7 +222,7 @@
#define EBI_CSR1 (VA_EBI_BASE + INTEGRATOR_EBI_CSR1_OFFSET)
#define EBI_LOCK (VA_EBI_BASE + INTEGRATOR_EBI_LOCK_OFFSET)
-static int ap_flash_init(void)
+static int ap_flash_init(struct platform_device *dev)
{
u32 tmp;
@@ -239,7 +239,7 @@
return 0;
}
-static void ap_flash_exit(void)
+static void ap_flash_exit(struct platform_device *dev)
{
u32 tmp;
@@ -255,15 +255,14 @@
}
}
-static void ap_flash_set_vpp(int on)
+static void ap_flash_set_vpp(struct platform_device *pdev, int on)
{
void __iomem *reg = on ? SC_CTRLS : SC_CTRLC;
writel(INTEGRATOR_SC_CTRL_nFLVPPEN, reg);
}
-static struct flash_platform_data ap_flash_data = {
- .map_name = "cfi_probe",
+static struct physmap_flash_data ap_flash_data = {
.width = 4,
.init = ap_flash_init,
.exit = ap_flash_exit,
@@ -277,7 +276,7 @@
};
static struct platform_device cfi_flash_device = {
- .name = "armflash",
+ .name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &ap_flash_data,
@@ -335,25 +334,9 @@
static unsigned long timer_reload;
-static void __iomem * const clksrc_base = (void __iomem *)TIMER2_VA_BASE;
-
-static cycle_t timersp_read(struct clocksource *cs)
-{
- return ~(readl(clksrc_base + TIMER_VALUE) & 0xffff);
-}
-
-static struct clocksource clocksource_timersp = {
- .name = "timer2",
- .rating = 200,
- .read = timersp_read,
- .mask = CLOCKSOURCE_MASK(16),
- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
static void integrator_clocksource_init(u32 khz)
{
- struct clocksource *cs = &clocksource_timersp;
- void __iomem *base = clksrc_base;
+ void __iomem *base = (void __iomem *)TIMER2_VA_BASE;
u32 ctrl = TIMER_CTRL_ENABLE;
if (khz >= 1500) {
@@ -364,7 +347,8 @@
writel(ctrl, base + TIMER_CTRL);
writel(0xffff, base + TIMER_LOAD);
- clocksource_register_khz(cs, khz);
+ clocksource_mmio_init(base + TIMER_VALUE, "timer2",
+ khz * 1000, 200, 16, clocksource_mmio_readl_down);
}
static void __iomem * const clkevt_base = (void __iomem *)TIMER1_VA_BASE;
diff --git a/arch/arm/mach-integrator/integrator_cp.c b/arch/arm/mach-integrator/integrator_cp.c
index 9e3ce26..4eb03ab 100644
--- a/arch/arm/mach-integrator/integrator_cp.c
+++ b/arch/arm/mach-integrator/integrator_cp.c
@@ -22,6 +22,7 @@
#include <linux/io.h>
#include <linux/gfp.h>
#include <linux/clkdev.h>
+#include <linux/mtd/physmap.h>
#include <mach/hardware.h>
#include <mach/platform.h>
@@ -35,7 +36,6 @@
#include <mach/lm.h>
#include <asm/mach/arch.h>
-#include <asm/mach/flash.h>
#include <asm/mach/irq.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
@@ -229,17 +229,24 @@
.vcoreg = CM_AUXOSC,
};
+static struct clk sp804_clk = {
+ .rate = 1000000,
+};
+
static struct clk_lookup cp_lookups[] = {
{ /* CLCD */
.dev_id = "mb:c0",
.clk = &cp_auxclk,
+ }, { /* SP804 timers */
+ .dev_id = "sp804",
+ .clk = &sp804_clk,
},
};
/*
* Flash handling.
*/
-static int intcp_flash_init(void)
+static int intcp_flash_init(struct platform_device *dev)
{
u32 val;
@@ -250,7 +257,7 @@
return 0;
}
-static void intcp_flash_exit(void)
+static void intcp_flash_exit(struct platform_device *dev)
{
u32 val;
@@ -259,7 +266,7 @@
writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
}
-static void intcp_flash_set_vpp(int on)
+static void intcp_flash_set_vpp(struct platform_device *pdev, int on)
{
u32 val;
@@ -271,8 +278,7 @@
writel(val, INTCP_VA_CTRL_BASE + INTCP_FLASHPROG);
}
-static struct flash_platform_data intcp_flash_data = {
- .map_name = "cfi_probe",
+static struct physmap_flash_data intcp_flash_data = {
.width = 4,
.init = intcp_flash_init,
.exit = intcp_flash_exit,
@@ -286,7 +292,7 @@
};
static struct platform_device intcp_flash_device = {
- .name = "armflash",
+ .name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &intcp_flash_data,
@@ -476,8 +482,8 @@
writel(0, TIMER1_VA_BASE + TIMER_CTRL);
writel(0, TIMER2_VA_BASE + TIMER_CTRL);
- sp804_clocksource_init(TIMER2_VA_BASE);
- sp804_clockevents_init(TIMER1_VA_BASE, IRQ_TIMERINT1);
+ sp804_clocksource_init(TIMER2_VA_BASE, "timer2");
+ sp804_clockevents_init(TIMER1_VA_BASE, IRQ_TIMERINT1, "timer1");
}
static struct sys_timer cp_timer = {
diff --git a/arch/arm/mach-iop32x/include/mach/uncompress.h b/arch/arm/mach-iop32x/include/mach/uncompress.h
index b247551..4fd7154 100644
--- a/arch/arm/mach-iop32x/include/mach/uncompress.h
+++ b/arch/arm/mach-iop32x/include/mach/uncompress.h
@@ -7,7 +7,7 @@
#include <linux/serial_reg.h>
#include <mach/hardware.h>
-static volatile u8 *uart_base;
+volatile u8 *uart_base;
#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE)
diff --git a/arch/arm/mach-iop33x/include/mach/uncompress.h b/arch/arm/mach-iop33x/include/mach/uncompress.h
index b42423f..f99bb84 100644
--- a/arch/arm/mach-iop33x/include/mach/uncompress.h
+++ b/arch/arm/mach-iop33x/include/mach/uncompress.h
@@ -7,7 +7,7 @@
#include <linux/serial_reg.h>
#include <mach/hardware.h>
-static volatile u32 *uart_base;
+volatile u32 *uart_base;
#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE)
diff --git a/arch/arm/mach-ixp4xx/common-pci.c b/arch/arm/mach-ixp4xx/common-pci.c
index a54b3db..e9a5893 100644
--- a/arch/arm/mach-ixp4xx/common-pci.c
+++ b/arch/arm/mach-ixp4xx/common-pci.c
@@ -342,29 +342,6 @@
return (dev->bus == &pci_bus_type ) && ((dma_addr + size) >= SZ_64M);
}
-/*
- * Only first 64MB of memory can be accessed via PCI.
- * We use GFP_DMA to allocate safe buffers to do map/unmap.
- * This is really ugly and we need a better way of specifying
- * DMA-capable regions of memory.
- */
-void __init ixp4xx_adjust_zones(unsigned long *zone_size,
- unsigned long *zhole_size)
-{
- unsigned int sz = SZ_64M >> PAGE_SHIFT;
-
- /*
- * Only adjust if > 64M on current system
- */
- if (zone_size[0] <= sz)
- return;
-
- zone_size[1] = zone_size[0] - sz;
- zone_size[0] = sz;
- zhole_size[1] = zhole_size[0];
- zhole_size[0] = 0;
-}
-
void __init ixp4xx_pci_preinit(void)
{
unsigned long cpuid = read_cpuid_id();
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index ed19bc3..74ed81a 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -419,26 +419,14 @@
/*
* clocksource
*/
-static cycle_t ixp4xx_get_cycles(struct clocksource *cs)
-{
- return *IXP4XX_OSTS;
-}
-
-static struct clocksource clocksource_ixp4xx = {
- .name = "OSTS",
- .rating = 200,
- .read = ixp4xx_get_cycles,
- .mask = CLOCKSOURCE_MASK(32),
- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
unsigned long ixp4xx_timer_freq = IXP4XX_TIMER_FREQ;
EXPORT_SYMBOL(ixp4xx_timer_freq);
static void __init ixp4xx_clocksource_init(void)
{
init_sched_clock(&cd, ixp4xx_update_sched_clock, 32, ixp4xx_timer_freq);
- clocksource_register_hz(&clocksource_ixp4xx, ixp4xx_timer_freq);
+ clocksource_mmio_init(&IXP4XX_OSTS, "OSTS", ixp4xx_timer_freq, 200, 32,
+ clocksource_mmio_readl_up);
}
/*
diff --git a/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h b/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h
new file mode 100644
index 0000000..292d55e
--- /dev/null
+++ b/arch/arm/mach-ixp4xx/include/mach/ixp46x_ts.h
@@ -0,0 +1,78 @@
+/*
+ * PTP 1588 clock using the IXP46X
+ *
+ * Copyright (C) 2010 OMICRON electronics GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef _IXP46X_TS_H_
+#define _IXP46X_TS_H_
+
+#define DEFAULT_ADDEND 0xF0000029
+#define TICKS_NS_SHIFT 4
+
+struct ixp46x_channel_ctl {
+ u32 ch_control; /* 0x40 Time Synchronization Channel Control */
+ u32 ch_event; /* 0x44 Time Synchronization Channel Event */
+ u32 tx_snap_lo; /* 0x48 Transmit Snapshot Low Register */
+ u32 tx_snap_hi; /* 0x4C Transmit Snapshot High Register */
+ u32 rx_snap_lo; /* 0x50 Receive Snapshot Low Register */
+ u32 rx_snap_hi; /* 0x54 Receive Snapshot High Register */
+ u32 src_uuid_lo; /* 0x58 Source UUID0 Low Register */
+ u32 src_uuid_hi; /* 0x5C Sequence Identifier/Source UUID0 High */
+};
+
+struct ixp46x_ts_regs {
+ u32 control; /* 0x00 Time Sync Control Register */
+ u32 event; /* 0x04 Time Sync Event Register */
+ u32 addend; /* 0x08 Time Sync Addend Register */
+ u32 accum; /* 0x0C Time Sync Accumulator Register */
+ u32 test; /* 0x10 Time Sync Test Register */
+ u32 unused; /* 0x14 */
+ u32 rsystime_lo; /* 0x18 RawSystemTime_Low Register */
+ u32 rsystime_hi; /* 0x1C RawSystemTime_High Register */
+ u32 systime_lo; /* 0x20 SystemTime_Low Register */
+ u32 systime_hi; /* 0x24 SystemTime_High Register */
+ u32 trgt_lo; /* 0x28 TargetTime_Low Register */
+ u32 trgt_hi; /* 0x2C TargetTime_High Register */
+ u32 asms_lo; /* 0x30 Auxiliary Slave Mode Snapshot Low */
+ u32 asms_hi; /* 0x34 Auxiliary Slave Mode Snapshot High */
+ u32 amms_lo; /* 0x38 Auxiliary Master Mode Snapshot Low */
+ u32 amms_hi; /* 0x3C Auxiliary Master Mode Snapshot High */
+
+ struct ixp46x_channel_ctl channel[3];
+};
+
+/* 0x00 Time Sync Control Register Bits */
+#define TSCR_AMM (1<<3)
+#define TSCR_ASM (1<<2)
+#define TSCR_TTM (1<<1)
+#define TSCR_RST (1<<0)
+
+/* 0x04 Time Sync Event Register Bits */
+#define TSER_SNM (1<<3)
+#define TSER_SNS (1<<2)
+#define TTIPEND (1<<1)
+
+/* 0x40 Time Synchronization Channel Control Register Bits */
+#define MASTER_MODE (1<<0)
+#define TIMESTAMP_ALL (1<<1)
+
+/* 0x44 Time Synchronization Channel Event Register Bits */
+#define TX_SNAPSHOT_LOCKED (1<<0)
+#define RX_SNAPSHOT_LOCKED (1<<1)
+
+#endif
diff --git a/arch/arm/mach-ixp4xx/include/mach/memory.h b/arch/arm/mach-ixp4xx/include/mach/memory.h
index 6d388c9..34e7940 100644
--- a/arch/arm/mach-ixp4xx/include/mach/memory.h
+++ b/arch/arm/mach-ixp4xx/include/mach/memory.h
@@ -14,16 +14,8 @@
*/
#define PLAT_PHYS_OFFSET UL(0x00000000)
-#if !defined(__ASSEMBLY__) && defined(CONFIG_PCI)
-
-void ixp4xx_adjust_zones(unsigned long *size, unsigned long *holes);
-
-#define arch_adjust_zones(size, holes) \
- ixp4xx_adjust_zones(size, holes)
-
-#define ISA_DMA_THRESHOLD (SZ_64M - 1)
-#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_64M)
-
+#ifdef CONFIG_PCI
+#define ARM_DMA_ZONE_SIZE SZ_64M
#endif
#endif
diff --git a/arch/arm/mach-ixp4xx/include/mach/uncompress.h b/arch/arm/mach-ixp4xx/include/mach/uncompress.h
index 2db0078..219d7c1 100644
--- a/arch/arm/mach-ixp4xx/include/mach/uncompress.h
+++ b/arch/arm/mach-ixp4xx/include/mach/uncompress.h
@@ -19,7 +19,7 @@
#define TX_DONE (UART_LSR_TEMT|UART_LSR_THRE)
-static volatile u32* uart_base;
+volatile u32* uart_base;
static inline void putc(int c)
{
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 20e71df..f3248cf 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -13,11 +13,9 @@
#include <linux/platform_device.h>
#include <linux/serial_8250.h>
#include <linux/mbus.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/mv643xx_i2c.h>
#include <linux/ata_platform.h>
#include <linux/mtd/nand.h>
-#include <linux/spi/orion_spi.h>
+#include <linux/dma-mapping.h>
#include <net/dsa.h>
#include <asm/page.h>
#include <asm/timex.h>
@@ -28,11 +26,9 @@
#include <mach/bridge-regs.h>
#include <plat/audio.h>
#include <plat/cache-feroceon-l2.h>
-#include <plat/ehci-orion.h>
#include <plat/mvsdio.h>
-#include <plat/mv_xor.h>
#include <plat/orion_nand.h>
-#include <plat/orion_wdt.h>
+#include <plat/common.h>
#include <plat/time.h>
#include "common.h"
@@ -69,210 +65,52 @@
* registered. Some reserved bits must be set to 1.
*/
unsigned int kirkwood_clk_ctrl = CGC_DUNIT | CGC_RESERVED;
-
-
-/*****************************************************************************
- * EHCI
- ****************************************************************************/
-static struct orion_ehci_data kirkwood_ehci_data = {
- .dram = &kirkwood_mbus_dram_info,
- .phy_version = EHCI_PHY_NA,
-};
-
-static u64 ehci_dmamask = 0xffffffffUL;
/*****************************************************************************
* EHCI0
****************************************************************************/
-static struct resource kirkwood_ehci_resources[] = {
- {
- .start = USB_PHYS_BASE,
- .end = USB_PHYS_BASE + 0x0fff,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_KIRKWOOD_USB,
- .end = IRQ_KIRKWOOD_USB,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device kirkwood_ehci = {
- .name = "orion-ehci",
- .id = 0,
- .dev = {
- .dma_mask = &ehci_dmamask,
- .coherent_dma_mask = 0xffffffff,
- .platform_data = &kirkwood_ehci_data,
- },
- .resource = kirkwood_ehci_resources,
- .num_resources = ARRAY_SIZE(kirkwood_ehci_resources),
-};
-
void __init kirkwood_ehci_init(void)
{
kirkwood_clk_ctrl |= CGC_USB0;
- platform_device_register(&kirkwood_ehci);
+ orion_ehci_init(&kirkwood_mbus_dram_info,
+ USB_PHYS_BASE, IRQ_KIRKWOOD_USB);
}
/*****************************************************************************
* GE00
****************************************************************************/
-struct mv643xx_eth_shared_platform_data kirkwood_ge00_shared_data = {
- .dram = &kirkwood_mbus_dram_info,
-};
-
-static struct resource kirkwood_ge00_shared_resources[] = {
- {
- .name = "ge00 base",
- .start = GE00_PHYS_BASE + 0x2000,
- .end = GE00_PHYS_BASE + 0x3fff,
- .flags = IORESOURCE_MEM,
- }, {
- .name = "ge00 err irq",
- .start = IRQ_KIRKWOOD_GE00_ERR,
- .end = IRQ_KIRKWOOD_GE00_ERR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device kirkwood_ge00_shared = {
- .name = MV643XX_ETH_SHARED_NAME,
- .id = 0,
- .dev = {
- .platform_data = &kirkwood_ge00_shared_data,
- },
- .num_resources = ARRAY_SIZE(kirkwood_ge00_shared_resources),
- .resource = kirkwood_ge00_shared_resources,
-};
-
-static struct resource kirkwood_ge00_resources[] = {
- {
- .name = "ge00 irq",
- .start = IRQ_KIRKWOOD_GE00_SUM,
- .end = IRQ_KIRKWOOD_GE00_SUM,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device kirkwood_ge00 = {
- .name = MV643XX_ETH_NAME,
- .id = 0,
- .num_resources = 1,
- .resource = kirkwood_ge00_resources,
- .dev = {
- .coherent_dma_mask = 0xffffffff,
- },
-};
-
void __init kirkwood_ge00_init(struct mv643xx_eth_platform_data *eth_data)
{
kirkwood_clk_ctrl |= CGC_GE0;
- eth_data->shared = &kirkwood_ge00_shared;
- kirkwood_ge00.dev.platform_data = eth_data;
- platform_device_register(&kirkwood_ge00_shared);
- platform_device_register(&kirkwood_ge00);
+ orion_ge00_init(eth_data, &kirkwood_mbus_dram_info,
+ GE00_PHYS_BASE, IRQ_KIRKWOOD_GE00_SUM,
+ IRQ_KIRKWOOD_GE00_ERR, kirkwood_tclk);
}
/*****************************************************************************
* GE01
****************************************************************************/
-struct mv643xx_eth_shared_platform_data kirkwood_ge01_shared_data = {
- .dram = &kirkwood_mbus_dram_info,
- .shared_smi = &kirkwood_ge00_shared,
-};
-
-static struct resource kirkwood_ge01_shared_resources[] = {
- {
- .name = "ge01 base",
- .start = GE01_PHYS_BASE + 0x2000,
- .end = GE01_PHYS_BASE + 0x3fff,
- .flags = IORESOURCE_MEM,
- }, {
- .name = "ge01 err irq",
- .start = IRQ_KIRKWOOD_GE01_ERR,
- .end = IRQ_KIRKWOOD_GE01_ERR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device kirkwood_ge01_shared = {
- .name = MV643XX_ETH_SHARED_NAME,
- .id = 1,
- .dev = {
- .platform_data = &kirkwood_ge01_shared_data,
- },
- .num_resources = ARRAY_SIZE(kirkwood_ge01_shared_resources),
- .resource = kirkwood_ge01_shared_resources,
-};
-
-static struct resource kirkwood_ge01_resources[] = {
- {
- .name = "ge01 irq",
- .start = IRQ_KIRKWOOD_GE01_SUM,
- .end = IRQ_KIRKWOOD_GE01_SUM,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device kirkwood_ge01 = {
- .name = MV643XX_ETH_NAME,
- .id = 1,
- .num_resources = 1,
- .resource = kirkwood_ge01_resources,
- .dev = {
- .coherent_dma_mask = 0xffffffff,
- },
-};
-
void __init kirkwood_ge01_init(struct mv643xx_eth_platform_data *eth_data)
{
- kirkwood_clk_ctrl |= CGC_GE1;
- eth_data->shared = &kirkwood_ge01_shared;
- kirkwood_ge01.dev.platform_data = eth_data;
- platform_device_register(&kirkwood_ge01_shared);
- platform_device_register(&kirkwood_ge01);
+ kirkwood_clk_ctrl |= CGC_GE1;
+
+ orion_ge01_init(eth_data, &kirkwood_mbus_dram_info,
+ GE01_PHYS_BASE, IRQ_KIRKWOOD_GE01_SUM,
+ IRQ_KIRKWOOD_GE01_ERR, kirkwood_tclk);
}
/*****************************************************************************
* Ethernet switch
****************************************************************************/
-static struct resource kirkwood_switch_resources[] = {
- {
- .start = 0,
- .end = 0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device kirkwood_switch_device = {
- .name = "dsa",
- .id = 0,
- .num_resources = 0,
- .resource = kirkwood_switch_resources,
-};
-
void __init kirkwood_ge00_switch_init(struct dsa_platform_data *d, int irq)
{
- int i;
-
- if (irq != NO_IRQ) {
- kirkwood_switch_resources[0].start = irq;
- kirkwood_switch_resources[0].end = irq;
- kirkwood_switch_device.num_resources = 1;
- }
-
- d->netdev = &kirkwood_ge00.dev;
- for (i = 0; i < d->nr_chips; i++)
- d->chip[i].mii_bus = &kirkwood_ge00_shared.dev;
- kirkwood_switch_device.dev.platform_data = d;
-
- platform_device_register(&kirkwood_switch_device);
+ orion_ge00_switch_init(d, irq);
}
@@ -325,53 +163,23 @@
/*****************************************************************************
* SoC RTC
****************************************************************************/
-static struct resource kirkwood_rtc_resource = {
- .start = RTC_PHYS_BASE,
- .end = RTC_PHYS_BASE + SZ_16 - 1,
- .flags = IORESOURCE_MEM,
-};
-
static void __init kirkwood_rtc_init(void)
{
- platform_device_register_simple("rtc-mv", -1, &kirkwood_rtc_resource, 1);
+ orion_rtc_init(RTC_PHYS_BASE, IRQ_KIRKWOOD_RTC);
}
/*****************************************************************************
* SATA
****************************************************************************/
-static struct resource kirkwood_sata_resources[] = {
- {
- .name = "sata base",
- .start = SATA_PHYS_BASE,
- .end = SATA_PHYS_BASE + 0x5000 - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .name = "sata irq",
- .start = IRQ_KIRKWOOD_SATA,
- .end = IRQ_KIRKWOOD_SATA,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device kirkwood_sata = {
- .name = "sata_mv",
- .id = 0,
- .dev = {
- .coherent_dma_mask = 0xffffffff,
- },
- .num_resources = ARRAY_SIZE(kirkwood_sata_resources),
- .resource = kirkwood_sata_resources,
-};
-
void __init kirkwood_sata_init(struct mv_sata_platform_data *sata_data)
{
kirkwood_clk_ctrl |= CGC_SATA0;
if (sata_data->n_ports > 1)
kirkwood_clk_ctrl |= CGC_SATA1;
- sata_data->dram = &kirkwood_mbus_dram_info;
- kirkwood_sata.dev.platform_data = sata_data;
- platform_device_register(&kirkwood_sata);
+
+ orion_sata_init(sata_data, &kirkwood_mbus_dram_info,
+ SATA_PHYS_BASE, IRQ_KIRKWOOD_SATA);
}
@@ -391,14 +199,14 @@
},
};
-static u64 mvsdio_dmamask = 0xffffffffUL;
+static u64 mvsdio_dmamask = DMA_BIT_MASK(32);
static struct platform_device kirkwood_sdio = {
.name = "mvsdio",
.id = -1,
.dev = {
.dma_mask = &mvsdio_dmamask,
- .coherent_dma_mask = 0xffffffff,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
},
.num_resources = ARRAY_SIZE(mvsdio_resources),
.resource = mvsdio_resources,
@@ -423,424 +231,84 @@
/*****************************************************************************
* SPI
****************************************************************************/
-static struct orion_spi_info kirkwood_spi_plat_data = {
-};
-
-static struct resource kirkwood_spi_resources[] = {
- {
- .start = SPI_PHYS_BASE,
- .end = SPI_PHYS_BASE + SZ_512 - 1,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device kirkwood_spi = {
- .name = "orion_spi",
- .id = 0,
- .resource = kirkwood_spi_resources,
- .dev = {
- .platform_data = &kirkwood_spi_plat_data,
- },
- .num_resources = ARRAY_SIZE(kirkwood_spi_resources),
-};
-
void __init kirkwood_spi_init()
{
kirkwood_clk_ctrl |= CGC_RUNIT;
- platform_device_register(&kirkwood_spi);
+ orion_spi_init(SPI_PHYS_BASE, kirkwood_tclk);
}
/*****************************************************************************
* I2C
****************************************************************************/
-static struct mv64xxx_i2c_pdata kirkwood_i2c_pdata = {
- .freq_m = 8, /* assumes 166 MHz TCLK */
- .freq_n = 3,
- .timeout = 1000, /* Default timeout of 1 second */
-};
-
-static struct resource kirkwood_i2c_resources[] = {
- {
- .start = I2C_PHYS_BASE,
- .end = I2C_PHYS_BASE + 0x1f,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_KIRKWOOD_TWSI,
- .end = IRQ_KIRKWOOD_TWSI,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device kirkwood_i2c = {
- .name = MV64XXX_I2C_CTLR_NAME,
- .id = 0,
- .num_resources = ARRAY_SIZE(kirkwood_i2c_resources),
- .resource = kirkwood_i2c_resources,
- .dev = {
- .platform_data = &kirkwood_i2c_pdata,
- },
-};
-
void __init kirkwood_i2c_init(void)
{
- platform_device_register(&kirkwood_i2c);
+ orion_i2c_init(I2C_PHYS_BASE, IRQ_KIRKWOOD_TWSI, 8);
}
/*****************************************************************************
* UART0
****************************************************************************/
-static struct plat_serial8250_port kirkwood_uart0_data[] = {
- {
- .mapbase = UART0_PHYS_BASE,
- .membase = (char *)UART0_VIRT_BASE,
- .irq = IRQ_KIRKWOOD_UART_0,
- .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
- .iotype = UPIO_MEM,
- .regshift = 2,
- .uartclk = 0,
- }, {
- },
-};
-
-static struct resource kirkwood_uart0_resources[] = {
- {
- .start = UART0_PHYS_BASE,
- .end = UART0_PHYS_BASE + 0xff,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_KIRKWOOD_UART_0,
- .end = IRQ_KIRKWOOD_UART_0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device kirkwood_uart0 = {
- .name = "serial8250",
- .id = 0,
- .dev = {
- .platform_data = kirkwood_uart0_data,
- },
- .resource = kirkwood_uart0_resources,
- .num_resources = ARRAY_SIZE(kirkwood_uart0_resources),
-};
void __init kirkwood_uart0_init(void)
{
- platform_device_register(&kirkwood_uart0);
+ orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
+ IRQ_KIRKWOOD_UART_0, kirkwood_tclk);
}
/*****************************************************************************
* UART1
****************************************************************************/
-static struct plat_serial8250_port kirkwood_uart1_data[] = {
- {
- .mapbase = UART1_PHYS_BASE,
- .membase = (char *)UART1_VIRT_BASE,
- .irq = IRQ_KIRKWOOD_UART_1,
- .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
- .iotype = UPIO_MEM,
- .regshift = 2,
- .uartclk = 0,
- }, {
- },
-};
-
-static struct resource kirkwood_uart1_resources[] = {
- {
- .start = UART1_PHYS_BASE,
- .end = UART1_PHYS_BASE + 0xff,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_KIRKWOOD_UART_1,
- .end = IRQ_KIRKWOOD_UART_1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device kirkwood_uart1 = {
- .name = "serial8250",
- .id = 1,
- .dev = {
- .platform_data = kirkwood_uart1_data,
- },
- .resource = kirkwood_uart1_resources,
- .num_resources = ARRAY_SIZE(kirkwood_uart1_resources),
-};
-
void __init kirkwood_uart1_init(void)
{
- platform_device_register(&kirkwood_uart1);
+ orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
+ IRQ_KIRKWOOD_UART_1, kirkwood_tclk);
}
-
/*****************************************************************************
* Cryptographic Engines and Security Accelerator (CESA)
****************************************************************************/
-
-static struct resource kirkwood_crypto_res[] = {
- {
- .name = "regs",
- .start = CRYPTO_PHYS_BASE,
- .end = CRYPTO_PHYS_BASE + 0xffff,
- .flags = IORESOURCE_MEM,
- }, {
- .name = "sram",
- .start = KIRKWOOD_SRAM_PHYS_BASE,
- .end = KIRKWOOD_SRAM_PHYS_BASE + KIRKWOOD_SRAM_SIZE - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .name = "crypto interrupt",
- .start = IRQ_KIRKWOOD_CRYPTO,
- .end = IRQ_KIRKWOOD_CRYPTO,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device kirkwood_crypto_device = {
- .name = "mv_crypto",
- .id = -1,
- .num_resources = ARRAY_SIZE(kirkwood_crypto_res),
- .resource = kirkwood_crypto_res,
-};
-
void __init kirkwood_crypto_init(void)
{
kirkwood_clk_ctrl |= CGC_CRYPTO;
- platform_device_register(&kirkwood_crypto_device);
+ orion_crypto_init(CRYPTO_PHYS_BASE, KIRKWOOD_SRAM_PHYS_BASE,
+ KIRKWOOD_SRAM_SIZE, IRQ_KIRKWOOD_CRYPTO);
}
/*****************************************************************************
- * XOR
- ****************************************************************************/
-static struct mv_xor_platform_shared_data kirkwood_xor_shared_data = {
- .dram = &kirkwood_mbus_dram_info,
-};
-
-static u64 kirkwood_xor_dmamask = DMA_BIT_MASK(32);
-
-
-/*****************************************************************************
* XOR0
****************************************************************************/
-static struct resource kirkwood_xor0_shared_resources[] = {
- {
- .name = "xor 0 low",
- .start = XOR0_PHYS_BASE,
- .end = XOR0_PHYS_BASE + 0xff,
- .flags = IORESOURCE_MEM,
- }, {
- .name = "xor 0 high",
- .start = XOR0_HIGH_PHYS_BASE,
- .end = XOR0_HIGH_PHYS_BASE + 0xff,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device kirkwood_xor0_shared = {
- .name = MV_XOR_SHARED_NAME,
- .id = 0,
- .dev = {
- .platform_data = &kirkwood_xor_shared_data,
- },
- .num_resources = ARRAY_SIZE(kirkwood_xor0_shared_resources),
- .resource = kirkwood_xor0_shared_resources,
-};
-
-static struct resource kirkwood_xor00_resources[] = {
- [0] = {
- .start = IRQ_KIRKWOOD_XOR_00,
- .end = IRQ_KIRKWOOD_XOR_00,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct mv_xor_platform_data kirkwood_xor00_data = {
- .shared = &kirkwood_xor0_shared,
- .hw_id = 0,
- .pool_size = PAGE_SIZE,
-};
-
-static struct platform_device kirkwood_xor00_channel = {
- .name = MV_XOR_NAME,
- .id = 0,
- .num_resources = ARRAY_SIZE(kirkwood_xor00_resources),
- .resource = kirkwood_xor00_resources,
- .dev = {
- .dma_mask = &kirkwood_xor_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(64),
- .platform_data = &kirkwood_xor00_data,
- },
-};
-
-static struct resource kirkwood_xor01_resources[] = {
- [0] = {
- .start = IRQ_KIRKWOOD_XOR_01,
- .end = IRQ_KIRKWOOD_XOR_01,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct mv_xor_platform_data kirkwood_xor01_data = {
- .shared = &kirkwood_xor0_shared,
- .hw_id = 1,
- .pool_size = PAGE_SIZE,
-};
-
-static struct platform_device kirkwood_xor01_channel = {
- .name = MV_XOR_NAME,
- .id = 1,
- .num_resources = ARRAY_SIZE(kirkwood_xor01_resources),
- .resource = kirkwood_xor01_resources,
- .dev = {
- .dma_mask = &kirkwood_xor_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(64),
- .platform_data = &kirkwood_xor01_data,
- },
-};
-
static void __init kirkwood_xor0_init(void)
{
kirkwood_clk_ctrl |= CGC_XOR0;
- platform_device_register(&kirkwood_xor0_shared);
- /*
- * two engines can't do memset simultaneously, this limitation
- * satisfied by removing memset support from one of the engines.
- */
- dma_cap_set(DMA_MEMCPY, kirkwood_xor00_data.cap_mask);
- dma_cap_set(DMA_XOR, kirkwood_xor00_data.cap_mask);
- platform_device_register(&kirkwood_xor00_channel);
-
- dma_cap_set(DMA_MEMCPY, kirkwood_xor01_data.cap_mask);
- dma_cap_set(DMA_MEMSET, kirkwood_xor01_data.cap_mask);
- dma_cap_set(DMA_XOR, kirkwood_xor01_data.cap_mask);
- platform_device_register(&kirkwood_xor01_channel);
+ orion_xor0_init(&kirkwood_mbus_dram_info,
+ XOR0_PHYS_BASE, XOR0_HIGH_PHYS_BASE,
+ IRQ_KIRKWOOD_XOR_00, IRQ_KIRKWOOD_XOR_01);
}
/*****************************************************************************
* XOR1
****************************************************************************/
-static struct resource kirkwood_xor1_shared_resources[] = {
- {
- .name = "xor 1 low",
- .start = XOR1_PHYS_BASE,
- .end = XOR1_PHYS_BASE + 0xff,
- .flags = IORESOURCE_MEM,
- }, {
- .name = "xor 1 high",
- .start = XOR1_HIGH_PHYS_BASE,
- .end = XOR1_HIGH_PHYS_BASE + 0xff,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device kirkwood_xor1_shared = {
- .name = MV_XOR_SHARED_NAME,
- .id = 1,
- .dev = {
- .platform_data = &kirkwood_xor_shared_data,
- },
- .num_resources = ARRAY_SIZE(kirkwood_xor1_shared_resources),
- .resource = kirkwood_xor1_shared_resources,
-};
-
-static struct resource kirkwood_xor10_resources[] = {
- [0] = {
- .start = IRQ_KIRKWOOD_XOR_10,
- .end = IRQ_KIRKWOOD_XOR_10,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct mv_xor_platform_data kirkwood_xor10_data = {
- .shared = &kirkwood_xor1_shared,
- .hw_id = 0,
- .pool_size = PAGE_SIZE,
-};
-
-static struct platform_device kirkwood_xor10_channel = {
- .name = MV_XOR_NAME,
- .id = 2,
- .num_resources = ARRAY_SIZE(kirkwood_xor10_resources),
- .resource = kirkwood_xor10_resources,
- .dev = {
- .dma_mask = &kirkwood_xor_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(64),
- .platform_data = &kirkwood_xor10_data,
- },
-};
-
-static struct resource kirkwood_xor11_resources[] = {
- [0] = {
- .start = IRQ_KIRKWOOD_XOR_11,
- .end = IRQ_KIRKWOOD_XOR_11,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct mv_xor_platform_data kirkwood_xor11_data = {
- .shared = &kirkwood_xor1_shared,
- .hw_id = 1,
- .pool_size = PAGE_SIZE,
-};
-
-static struct platform_device kirkwood_xor11_channel = {
- .name = MV_XOR_NAME,
- .id = 3,
- .num_resources = ARRAY_SIZE(kirkwood_xor11_resources),
- .resource = kirkwood_xor11_resources,
- .dev = {
- .dma_mask = &kirkwood_xor_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(64),
- .platform_data = &kirkwood_xor11_data,
- },
-};
-
static void __init kirkwood_xor1_init(void)
{
kirkwood_clk_ctrl |= CGC_XOR1;
- platform_device_register(&kirkwood_xor1_shared);
- /*
- * two engines can't do memset simultaneously, this limitation
- * satisfied by removing memset support from one of the engines.
- */
- dma_cap_set(DMA_MEMCPY, kirkwood_xor10_data.cap_mask);
- dma_cap_set(DMA_XOR, kirkwood_xor10_data.cap_mask);
- platform_device_register(&kirkwood_xor10_channel);
-
- dma_cap_set(DMA_MEMCPY, kirkwood_xor11_data.cap_mask);
- dma_cap_set(DMA_MEMSET, kirkwood_xor11_data.cap_mask);
- dma_cap_set(DMA_XOR, kirkwood_xor11_data.cap_mask);
- platform_device_register(&kirkwood_xor11_channel);
+ orion_xor1_init(XOR1_PHYS_BASE, XOR1_HIGH_PHYS_BASE,
+ IRQ_KIRKWOOD_XOR_10, IRQ_KIRKWOOD_XOR_11);
}
/*****************************************************************************
* Watchdog
****************************************************************************/
-static struct orion_wdt_platform_data kirkwood_wdt_data = {
- .tclk = 0,
-};
-
-static struct platform_device kirkwood_wdt_device = {
- .name = "orion_wdt",
- .id = -1,
- .dev = {
- .platform_data = &kirkwood_wdt_data,
- },
- .num_resources = 0,
-};
-
static void __init kirkwood_wdt_init(void)
{
- kirkwood_wdt_data.tclk = kirkwood_tclk;
- platform_device_register(&kirkwood_wdt_device);
+ orion_wdt_init(kirkwood_tclk);
}
@@ -984,11 +452,6 @@
{
printk(KERN_INFO "Kirkwood: %s, TCLK=%d.\n",
kirkwood_id(), kirkwood_tclk);
- kirkwood_ge00_shared_data.t_clk = kirkwood_tclk;
- kirkwood_ge01_shared_data.t_clk = kirkwood_tclk;
- kirkwood_spi_plat_data.tclk = kirkwood_tclk;
- kirkwood_uart0_data[0].uartclk = kirkwood_tclk;
- kirkwood_uart1_data[0].uartclk = kirkwood_tclk;
kirkwood_i2s_data.tclk = kirkwood_tclk;
/*
diff --git a/arch/arm/mach-kirkwood/include/mach/irqs.h b/arch/arm/mach-kirkwood/include/mach/irqs.h
index 9da2eb5..2bf8161 100644
--- a/arch/arm/mach-kirkwood/include/mach/irqs.h
+++ b/arch/arm/mach-kirkwood/include/mach/irqs.h
@@ -51,6 +51,7 @@
#define IRQ_KIRKWOOD_GPIO_HIGH_16_23 41
#define IRQ_KIRKWOOD_GE00_ERR 46
#define IRQ_KIRKWOOD_GE01_ERR 47
+#define IRQ_KIRKWOOD_RTC 53
/*
* KIRKWOOD General Purpose Pins
diff --git a/arch/arm/mach-kirkwood/mpp.c b/arch/arm/mach-kirkwood/mpp.c
index 7ce2018..b0a7d97 100644
--- a/arch/arm/mach-kirkwood/mpp.c
+++ b/arch/arm/mach-kirkwood/mpp.c
@@ -14,6 +14,7 @@
#include <linux/io.h>
#include <asm/gpio.h>
#include <mach/hardware.h>
+#include <plat/mpp.h>
#include "common.h"
#include "mpp.h"
@@ -36,61 +37,8 @@
return 0;
}
-#define MPP_CTRL(i) (DEV_BUS_VIRT_BASE + (i) * 4)
-#define MPP_NR_REGS (1 + MPP_MAX/8)
-
void __init kirkwood_mpp_conf(unsigned int *mpp_list)
{
- u32 mpp_ctrl[MPP_NR_REGS];
- unsigned int variant_mask;
- int i;
-
- variant_mask = kirkwood_variant();
- if (!variant_mask)
- return;
-
- printk(KERN_DEBUG "initial MPP regs:");
- for (i = 0; i < MPP_NR_REGS; i++) {
- mpp_ctrl[i] = readl(MPP_CTRL(i));
- printk(" %08x", mpp_ctrl[i]);
- }
- printk("\n");
-
- for ( ; *mpp_list; mpp_list++) {
- unsigned int num = MPP_NUM(*mpp_list);
- unsigned int sel = MPP_SEL(*mpp_list);
- int shift, gpio_mode;
-
- if (num > MPP_MAX) {
- printk(KERN_ERR "kirkwood_mpp_conf: invalid MPP "
- "number (%u)\n", num);
- continue;
- }
- if (!(*mpp_list & variant_mask)) {
- printk(KERN_WARNING
- "kirkwood_mpp_conf: requested MPP%u config "
- "unavailable on this hardware\n", num);
- continue;
- }
-
- shift = (num & 7) << 2;
- mpp_ctrl[num / 8] &= ~(0xf << shift);
- mpp_ctrl[num / 8] |= sel << shift;
-
- gpio_mode = 0;
- if (*mpp_list & MPP_INPUT_MASK)
- gpio_mode |= GPIO_INPUT_OK;
- if (*mpp_list & MPP_OUTPUT_MASK)
- gpio_mode |= GPIO_OUTPUT_OK;
- if (sel != 0)
- gpio_mode = 0;
- orion_gpio_set_valid(num, gpio_mode);
- }
-
- printk(KERN_DEBUG " final MPP regs:");
- for (i = 0; i < MPP_NR_REGS; i++) {
- writel(mpp_ctrl[i], MPP_CTRL(i));
- printk(" %08x", mpp_ctrl[i]);
- }
- printk("\n");
+ orion_mpp_conf(mpp_list, kirkwood_variant(),
+ MPP_MAX, DEV_BUS_VIRT_BASE);
}
diff --git a/arch/arm/mach-kirkwood/mpp.h b/arch/arm/mach-kirkwood/mpp.h
index 9b0a94d..ac78795 100644
--- a/arch/arm/mach-kirkwood/mpp.h
+++ b/arch/arm/mach-kirkwood/mpp.h
@@ -22,14 +22,8 @@
/* available on F6281 */ ((!!(_F6281)) << 17) | \
/* available on F6282 */ ((!!(_F6282)) << 18))
-#define MPP_NUM(x) ((x) & 0xff)
-#define MPP_SEL(x) (((x) >> 8) & 0xf)
-
/* num sel i o 6180 6190 6192 6281 6282 */
-#define MPP_INPUT_MASK MPP( 0, 0x0, 1, 0, 0, 0, 0, 0, 0 )
-#define MPP_OUTPUT_MASK MPP( 0, 0x0, 0, 1, 0, 0, 0, 0, 0 )
-
#define MPP_F6180_MASK MPP( 0, 0x0, 0, 0, 1, 0, 0, 0, 0 )
#define MPP_F6190_MASK MPP( 0, 0x0, 0, 0, 0, 1, 0, 0, 0 )
#define MPP_F6192_MASK MPP( 0, 0x0, 0, 0, 0, 0, 1, 0, 0 )
diff --git a/arch/arm/mach-loki/common.c b/arch/arm/mach-loki/common.c
index e41e909..5f02664 100644
--- a/arch/arm/mach-loki/common.c
+++ b/arch/arm/mach-loki/common.c
@@ -13,7 +13,7 @@
#include <linux/platform_device.h>
#include <linux/serial_8250.h>
#include <linux/mbus.h>
-#include <linux/mv643xx_eth.h>
+#include <linux/dma-mapping.h>
#include <asm/page.h>
#include <asm/timex.h>
#include <asm/mach/map.h>
@@ -22,6 +22,7 @@
#include <mach/loki.h>
#include <plat/orion_nand.h>
#include <plat/time.h>
+#include <plat/common.h>
#include "common.h"
/*****************************************************************************
@@ -43,116 +44,28 @@
/*****************************************************************************
- * GE0
+ * GE00
****************************************************************************/
-struct mv643xx_eth_shared_platform_data loki_ge0_shared_data = {
- .t_clk = LOKI_TCLK,
- .dram = &loki_mbus_dram_info,
-};
-
-static struct resource loki_ge0_shared_resources[] = {
- {
- .name = "ge0 base",
- .start = GE0_PHYS_BASE + 0x2000,
- .end = GE0_PHYS_BASE + 0x3fff,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device loki_ge0_shared = {
- .name = MV643XX_ETH_SHARED_NAME,
- .id = 0,
- .dev = {
- .platform_data = &loki_ge0_shared_data,
- },
- .num_resources = 1,
- .resource = loki_ge0_shared_resources,
-};
-
-static struct resource loki_ge0_resources[] = {
- {
- .name = "ge0 irq",
- .start = IRQ_LOKI_GBE_A_INT,
- .end = IRQ_LOKI_GBE_A_INT,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device loki_ge0 = {
- .name = MV643XX_ETH_NAME,
- .id = 0,
- .num_resources = 1,
- .resource = loki_ge0_resources,
- .dev = {
- .coherent_dma_mask = 0xffffffff,
- },
-};
-
void __init loki_ge0_init(struct mv643xx_eth_platform_data *eth_data)
{
- eth_data->shared = &loki_ge0_shared;
- loki_ge0.dev.platform_data = eth_data;
-
writel(0x00079220, GE0_VIRT_BASE + 0x20b0);
- platform_device_register(&loki_ge0_shared);
- platform_device_register(&loki_ge0);
+
+ orion_ge00_init(eth_data, &loki_mbus_dram_info,
+ GE0_PHYS_BASE, IRQ_LOKI_GBE_A_INT,
+ 0, LOKI_TCLK);
}
/*****************************************************************************
- * GE1
+ * GE01
****************************************************************************/
-struct mv643xx_eth_shared_platform_data loki_ge1_shared_data = {
- .t_clk = LOKI_TCLK,
- .dram = &loki_mbus_dram_info,
-};
-
-static struct resource loki_ge1_shared_resources[] = {
- {
- .name = "ge1 base",
- .start = GE1_PHYS_BASE + 0x2000,
- .end = GE1_PHYS_BASE + 0x3fff,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device loki_ge1_shared = {
- .name = MV643XX_ETH_SHARED_NAME,
- .id = 1,
- .dev = {
- .platform_data = &loki_ge1_shared_data,
- },
- .num_resources = 1,
- .resource = loki_ge1_shared_resources,
-};
-
-static struct resource loki_ge1_resources[] = {
- {
- .name = "ge1 irq",
- .start = IRQ_LOKI_GBE_B_INT,
- .end = IRQ_LOKI_GBE_B_INT,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device loki_ge1 = {
- .name = MV643XX_ETH_NAME,
- .id = 1,
- .num_resources = 1,
- .resource = loki_ge1_resources,
- .dev = {
- .coherent_dma_mask = 0xffffffff,
- },
-};
-
void __init loki_ge1_init(struct mv643xx_eth_platform_data *eth_data)
{
- eth_data->shared = &loki_ge1_shared;
- loki_ge1.dev.platform_data = eth_data;
-
writel(0x00079220, GE1_VIRT_BASE + 0x20b0);
- platform_device_register(&loki_ge1_shared);
- platform_device_register(&loki_ge1);
+
+ orion_ge01_init(eth_data, &loki_mbus_dram_info,
+ GE1_PHYS_BASE, IRQ_LOKI_GBE_B_INT,
+ 0, LOKI_TCLK);
}
@@ -187,7 +100,7 @@
.name = "mvsas",
.id = 0,
.dev = {
- .coherent_dma_mask = 0xffffffff,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
},
.num_resources = ARRAY_SIZE(loki_sas_resources),
.resource = loki_sas_resources,
@@ -203,88 +116,19 @@
/*****************************************************************************
* UART0
****************************************************************************/
-static struct plat_serial8250_port loki_uart0_data[] = {
- {
- .mapbase = UART0_PHYS_BASE,
- .membase = (char *)UART0_VIRT_BASE,
- .irq = IRQ_LOKI_UART0,
- .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
- .iotype = UPIO_MEM,
- .regshift = 2,
- .uartclk = LOKI_TCLK,
- }, {
- },
-};
-
-static struct resource loki_uart0_resources[] = {
- {
- .start = UART0_PHYS_BASE,
- .end = UART0_PHYS_BASE + 0xff,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_LOKI_UART0,
- .end = IRQ_LOKI_UART0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device loki_uart0 = {
- .name = "serial8250",
- .id = 0,
- .dev = {
- .platform_data = loki_uart0_data,
- },
- .resource = loki_uart0_resources,
- .num_resources = ARRAY_SIZE(loki_uart0_resources),
-};
-
void __init loki_uart0_init(void)
{
- platform_device_register(&loki_uart0);
+ orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
+ IRQ_LOKI_UART0, LOKI_TCLK);
}
-
/*****************************************************************************
* UART1
****************************************************************************/
-static struct plat_serial8250_port loki_uart1_data[] = {
- {
- .mapbase = UART1_PHYS_BASE,
- .membase = (char *)UART1_VIRT_BASE,
- .irq = IRQ_LOKI_UART1,
- .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
- .iotype = UPIO_MEM,
- .regshift = 2,
- .uartclk = LOKI_TCLK,
- }, {
- },
-};
-
-static struct resource loki_uart1_resources[] = {
- {
- .start = UART1_PHYS_BASE,
- .end = UART1_PHYS_BASE + 0xff,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_LOKI_UART1,
- .end = IRQ_LOKI_UART1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device loki_uart1 = {
- .name = "serial8250",
- .id = 1,
- .dev = {
- .platform_data = loki_uart1_data,
- },
- .resource = loki_uart1_resources,
- .num_resources = ARRAY_SIZE(loki_uart1_resources),
-};
-
void __init loki_uart1_init(void)
{
- platform_device_register(&loki_uart1);
+ orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
+ IRQ_LOKI_UART1, LOKI_TCLK);
}
diff --git a/arch/arm/mach-lpc32xx/timer.c b/arch/arm/mach-lpc32xx/timer.c
index 6162ac3..b42c909b 100644
--- a/arch/arm/mach-lpc32xx/timer.c
+++ b/arch/arm/mach-lpc32xx/timer.c
@@ -31,19 +31,6 @@
#include <mach/platform.h>
#include "common.h"
-static cycle_t lpc32xx_clksrc_read(struct clocksource *cs)
-{
- return (cycle_t)__raw_readl(LCP32XX_TIMER_TC(LPC32XX_TIMER1_BASE));
-}
-
-static struct clocksource lpc32xx_clksrc = {
- .name = "lpc32xx_clksrc",
- .rating = 300,
- .read = lpc32xx_clksrc_read,
- .mask = CLOCKSOURCE_MASK(32),
- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
static int lpc32xx_clkevt_next_event(unsigned long delta,
struct clock_event_device *dev)
{
@@ -170,7 +157,9 @@
__raw_writel(0, LCP32XX_TIMER_MCR(LPC32XX_TIMER1_BASE));
__raw_writel(LCP32XX_TIMER_CNTR_TCR_EN,
LCP32XX_TIMER_TCR(LPC32XX_TIMER1_BASE));
- clocksource_register_hz(&lpc32xx_clksrc, clkrate);
+
+ clocksource_mmio_init(LCP32XX_TIMER_TC(LPC32XX_TIMER1_BASE),
+ "lpc32xx_clksrc", clkrate, 300, 32, clocksource_mmio_readl_up);
}
struct sys_timer lpc32xx_timer = {
diff --git a/arch/arm/mach-mmp/include/mach/uncompress.h b/arch/arm/mach-mmp/include/mach/uncompress.h
index 85bd8a2..d6daeb7 100644
--- a/arch/arm/mach-mmp/include/mach/uncompress.h
+++ b/arch/arm/mach-mmp/include/mach/uncompress.h
@@ -14,7 +14,7 @@
#define UART2_BASE (APB_PHYS_BASE + 0x17000)
#define UART3_BASE (APB_PHYS_BASE + 0x18000)
-static volatile unsigned long *UART;
+volatile unsigned long *UART;
static inline void putc(char c)
{
diff --git a/arch/arm/mach-msm/gpio-v2.c b/arch/arm/mach-msm/gpio-v2.c
index 56a964e..cc9c4fd 100644
--- a/arch/arm/mach-msm/gpio-v2.c
+++ b/arch/arm/mach-msm/gpio-v2.c
@@ -27,6 +27,9 @@
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
+
+#include <asm/mach/irq.h>
+
#include <mach/msm_iomap.h>
#include "gpiomux.h"
@@ -309,8 +312,10 @@
*/
static void msm_summary_irq_handler(unsigned int irq, struct irq_desc *desc)
{
- struct irq_data *data = irq_desc_get_irq_data(desc);
unsigned long i;
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+
+ chained_irq_enter(chip, desc);
for (i = find_first_bit(msm_gpio.enabled_irqs, NR_GPIO_IRQS);
i < NR_GPIO_IRQS;
@@ -319,7 +324,8 @@
generic_handle_irq(msm_gpio_to_irq(&msm_gpio.gpio_chip,
i));
}
- data->chip->irq_ack(data);
+
+ chained_irq_exit(chip, desc);
}
static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
diff --git a/arch/arm/mach-msm/include/mach/smp.h b/arch/arm/mach-msm/include/mach/smp.h
deleted file mode 100644
index 3c01000e..0000000
--- a/arch/arm/mach-msm/include/mach/smp.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __ASM_ARCH_MSM_SMP_H
-#define __ASM_ARCH_MSM_SMP_H
-
-#include <asm/hardware/gic.h>
-
-static inline void smp_cross_call(const struct cpumask *mask, int ipi)
-{
- gic_raise_softirq(mask, ipi);
-}
-
-#endif
diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c
index 0f427bc..2034098 100644
--- a/arch/arm/mach-msm/platsmp.c
+++ b/arch/arm/mach-msm/platsmp.c
@@ -119,7 +119,7 @@
* the boot monitor to read the system wide flags register,
* and branch to the address found there.
*/
- smp_cross_call(cpumask_of(cpu), 1);
+ gic_raise_softirq(cpumask_of(cpu), 1);
timeout = jiffies + (1 * HZ);
while (time_before(jiffies, timeout)) {
@@ -151,6 +151,8 @@
for (i = 0; i < NR_CPUS; i++)
set_cpu_possible(i, true);
+
+ set_smp_cross_call(gic_raise_softirq);
}
void __init platform_smp_prepare_cpus(unsigned int max_cpus)
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c
index 44fb4e5..23d3980 100644
--- a/arch/arm/mach-mv78xx0/common.c
+++ b/arch/arm/mach-mv78xx0/common.c
@@ -13,8 +13,6 @@
#include <linux/platform_device.h>
#include <linux/serial_8250.h>
#include <linux/mbus.h>
-#include <linux/mv643xx_eth.h>
-#include <linux/mv643xx_i2c.h>
#include <linux/ata_platform.h>
#include <linux/ethtool.h>
#include <asm/mach/map.h>
@@ -22,11 +20,12 @@
#include <mach/mv78xx0.h>
#include <mach/bridge-regs.h>
#include <plat/cache-feroceon-l2.h>
-#include <plat/ehci-orion.h>
#include <plat/orion_nand.h>
#include <plat/time.h>
+#include <plat/common.h>
#include "common.h"
+static int get_tclk(void);
/*****************************************************************************
* Common bits
@@ -168,285 +167,62 @@
/*****************************************************************************
* EHCI
****************************************************************************/
-static struct orion_ehci_data mv78xx0_ehci_data = {
- .dram = &mv78xx0_mbus_dram_info,
- .phy_version = EHCI_PHY_NA,
-};
-
-static u64 ehci_dmamask = 0xffffffffUL;
-
-
-/*****************************************************************************
- * EHCI0
- ****************************************************************************/
-static struct resource mv78xx0_ehci0_resources[] = {
- {
- .start = USB0_PHYS_BASE,
- .end = USB0_PHYS_BASE + 0x0fff,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_MV78XX0_USB_0,
- .end = IRQ_MV78XX0_USB_0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device mv78xx0_ehci0 = {
- .name = "orion-ehci",
- .id = 0,
- .dev = {
- .dma_mask = &ehci_dmamask,
- .coherent_dma_mask = 0xffffffff,
- .platform_data = &mv78xx0_ehci_data,
- },
- .resource = mv78xx0_ehci0_resources,
- .num_resources = ARRAY_SIZE(mv78xx0_ehci0_resources),
-};
-
void __init mv78xx0_ehci0_init(void)
{
- platform_device_register(&mv78xx0_ehci0);
+ orion_ehci_init(&mv78xx0_mbus_dram_info,
+ USB0_PHYS_BASE, IRQ_MV78XX0_USB_0);
}
/*****************************************************************************
* EHCI1
****************************************************************************/
-static struct resource mv78xx0_ehci1_resources[] = {
- {
- .start = USB1_PHYS_BASE,
- .end = USB1_PHYS_BASE + 0x0fff,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_MV78XX0_USB_1,
- .end = IRQ_MV78XX0_USB_1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device mv78xx0_ehci1 = {
- .name = "orion-ehci",
- .id = 1,
- .dev = {
- .dma_mask = &ehci_dmamask,
- .coherent_dma_mask = 0xffffffff,
- .platform_data = &mv78xx0_ehci_data,
- },
- .resource = mv78xx0_ehci1_resources,
- .num_resources = ARRAY_SIZE(mv78xx0_ehci1_resources),
-};
-
void __init mv78xx0_ehci1_init(void)
{
- platform_device_register(&mv78xx0_ehci1);
+ orion_ehci_1_init(&mv78xx0_mbus_dram_info,
+ USB1_PHYS_BASE, IRQ_MV78XX0_USB_1);
}
/*****************************************************************************
* EHCI2
****************************************************************************/
-static struct resource mv78xx0_ehci2_resources[] = {
- {
- .start = USB2_PHYS_BASE,
- .end = USB2_PHYS_BASE + 0x0fff,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_MV78XX0_USB_2,
- .end = IRQ_MV78XX0_USB_2,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device mv78xx0_ehci2 = {
- .name = "orion-ehci",
- .id = 2,
- .dev = {
- .dma_mask = &ehci_dmamask,
- .coherent_dma_mask = 0xffffffff,
- .platform_data = &mv78xx0_ehci_data,
- },
- .resource = mv78xx0_ehci2_resources,
- .num_resources = ARRAY_SIZE(mv78xx0_ehci2_resources),
-};
-
void __init mv78xx0_ehci2_init(void)
{
- platform_device_register(&mv78xx0_ehci2);
+ orion_ehci_2_init(&mv78xx0_mbus_dram_info,
+ USB2_PHYS_BASE, IRQ_MV78XX0_USB_2);
}
/*****************************************************************************
* GE00
****************************************************************************/
-struct mv643xx_eth_shared_platform_data mv78xx0_ge00_shared_data = {
- .t_clk = 0,
- .dram = &mv78xx0_mbus_dram_info,
-};
-
-static struct resource mv78xx0_ge00_shared_resources[] = {
- {
- .name = "ge00 base",
- .start = GE00_PHYS_BASE + 0x2000,
- .end = GE00_PHYS_BASE + 0x3fff,
- .flags = IORESOURCE_MEM,
- }, {
- .name = "ge err irq",
- .start = IRQ_MV78XX0_GE_ERR,
- .end = IRQ_MV78XX0_GE_ERR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device mv78xx0_ge00_shared = {
- .name = MV643XX_ETH_SHARED_NAME,
- .id = 0,
- .dev = {
- .platform_data = &mv78xx0_ge00_shared_data,
- },
- .num_resources = ARRAY_SIZE(mv78xx0_ge00_shared_resources),
- .resource = mv78xx0_ge00_shared_resources,
-};
-
-static struct resource mv78xx0_ge00_resources[] = {
- {
- .name = "ge00 irq",
- .start = IRQ_MV78XX0_GE00_SUM,
- .end = IRQ_MV78XX0_GE00_SUM,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device mv78xx0_ge00 = {
- .name = MV643XX_ETH_NAME,
- .id = 0,
- .num_resources = 1,
- .resource = mv78xx0_ge00_resources,
- .dev = {
- .coherent_dma_mask = 0xffffffff,
- },
-};
-
void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data)
{
- eth_data->shared = &mv78xx0_ge00_shared;
- mv78xx0_ge00.dev.platform_data = eth_data;
-
- platform_device_register(&mv78xx0_ge00_shared);
- platform_device_register(&mv78xx0_ge00);
+ orion_ge00_init(eth_data, &mv78xx0_mbus_dram_info,
+ GE00_PHYS_BASE, IRQ_MV78XX0_GE00_SUM,
+ IRQ_MV78XX0_GE_ERR, get_tclk());
}
/*****************************************************************************
* GE01
****************************************************************************/
-struct mv643xx_eth_shared_platform_data mv78xx0_ge01_shared_data = {
- .t_clk = 0,
- .dram = &mv78xx0_mbus_dram_info,
- .shared_smi = &mv78xx0_ge00_shared,
-};
-
-static struct resource mv78xx0_ge01_shared_resources[] = {
- {
- .name = "ge01 base",
- .start = GE01_PHYS_BASE + 0x2000,
- .end = GE01_PHYS_BASE + 0x3fff,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device mv78xx0_ge01_shared = {
- .name = MV643XX_ETH_SHARED_NAME,
- .id = 1,
- .dev = {
- .platform_data = &mv78xx0_ge01_shared_data,
- },
- .num_resources = 1,
- .resource = mv78xx0_ge01_shared_resources,
-};
-
-static struct resource mv78xx0_ge01_resources[] = {
- {
- .name = "ge01 irq",
- .start = IRQ_MV78XX0_GE01_SUM,
- .end = IRQ_MV78XX0_GE01_SUM,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device mv78xx0_ge01 = {
- .name = MV643XX_ETH_NAME,
- .id = 1,
- .num_resources = 1,
- .resource = mv78xx0_ge01_resources,
- .dev = {
- .coherent_dma_mask = 0xffffffff,
- },
-};
-
void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data)
{
- eth_data->shared = &mv78xx0_ge01_shared;
- mv78xx0_ge01.dev.platform_data = eth_data;
-
- platform_device_register(&mv78xx0_ge01_shared);
- platform_device_register(&mv78xx0_ge01);
+ orion_ge01_init(eth_data, &mv78xx0_mbus_dram_info,
+ GE01_PHYS_BASE, IRQ_MV78XX0_GE01_SUM,
+ NO_IRQ, get_tclk());
}
/*****************************************************************************
* GE10
****************************************************************************/
-struct mv643xx_eth_shared_platform_data mv78xx0_ge10_shared_data = {
- .t_clk = 0,
- .dram = &mv78xx0_mbus_dram_info,
- .shared_smi = &mv78xx0_ge00_shared,
-};
-
-static struct resource mv78xx0_ge10_shared_resources[] = {
- {
- .name = "ge10 base",
- .start = GE10_PHYS_BASE + 0x2000,
- .end = GE10_PHYS_BASE + 0x3fff,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device mv78xx0_ge10_shared = {
- .name = MV643XX_ETH_SHARED_NAME,
- .id = 2,
- .dev = {
- .platform_data = &mv78xx0_ge10_shared_data,
- },
- .num_resources = 1,
- .resource = mv78xx0_ge10_shared_resources,
-};
-
-static struct resource mv78xx0_ge10_resources[] = {
- {
- .name = "ge10 irq",
- .start = IRQ_MV78XX0_GE10_SUM,
- .end = IRQ_MV78XX0_GE10_SUM,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device mv78xx0_ge10 = {
- .name = MV643XX_ETH_NAME,
- .id = 2,
- .num_resources = 1,
- .resource = mv78xx0_ge10_resources,
- .dev = {
- .coherent_dma_mask = 0xffffffff,
- },
-};
-
void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data)
{
u32 dev, rev;
- eth_data->shared = &mv78xx0_ge10_shared;
- mv78xx0_ge10.dev.platform_data = eth_data;
-
/*
* On the Z0, ge10 and ge11 are internally connected back
* to back, and not brought out.
@@ -458,65 +234,19 @@
eth_data->duplex = DUPLEX_FULL;
}
- platform_device_register(&mv78xx0_ge10_shared);
- platform_device_register(&mv78xx0_ge10);
+ orion_ge10_init(eth_data, &mv78xx0_mbus_dram_info,
+ GE10_PHYS_BASE, IRQ_MV78XX0_GE10_SUM,
+ NO_IRQ, get_tclk());
}
/*****************************************************************************
* GE11
****************************************************************************/
-struct mv643xx_eth_shared_platform_data mv78xx0_ge11_shared_data = {
- .t_clk = 0,
- .dram = &mv78xx0_mbus_dram_info,
- .shared_smi = &mv78xx0_ge00_shared,
-};
-
-static struct resource mv78xx0_ge11_shared_resources[] = {
- {
- .name = "ge11 base",
- .start = GE11_PHYS_BASE + 0x2000,
- .end = GE11_PHYS_BASE + 0x3fff,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device mv78xx0_ge11_shared = {
- .name = MV643XX_ETH_SHARED_NAME,
- .id = 3,
- .dev = {
- .platform_data = &mv78xx0_ge11_shared_data,
- },
- .num_resources = 1,
- .resource = mv78xx0_ge11_shared_resources,
-};
-
-static struct resource mv78xx0_ge11_resources[] = {
- {
- .name = "ge11 irq",
- .start = IRQ_MV78XX0_GE11_SUM,
- .end = IRQ_MV78XX0_GE11_SUM,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device mv78xx0_ge11 = {
- .name = MV643XX_ETH_NAME,
- .id = 3,
- .num_resources = 1,
- .resource = mv78xx0_ge11_resources,
- .dev = {
- .coherent_dma_mask = 0xffffffff,
- },
-};
-
void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data)
{
u32 dev, rev;
- eth_data->shared = &mv78xx0_ge11_shared;
- mv78xx0_ge11.dev.platform_data = eth_data;
-
/*
* On the Z0, ge10 and ge11 are internally connected back
* to back, and not brought out.
@@ -528,293 +258,68 @@
eth_data->duplex = DUPLEX_FULL;
}
- platform_device_register(&mv78xx0_ge11_shared);
- platform_device_register(&mv78xx0_ge11);
+ orion_ge11_init(eth_data, &mv78xx0_mbus_dram_info,
+ GE11_PHYS_BASE, IRQ_MV78XX0_GE11_SUM,
+ NO_IRQ, get_tclk());
}
/*****************************************************************************
- * I2C bus 0
+ * I2C
****************************************************************************/
-
-static struct mv64xxx_i2c_pdata mv78xx0_i2c_0_pdata = {
- .freq_m = 8, /* assumes 166 MHz TCLK */
- .freq_n = 3,
- .timeout = 1000, /* Default timeout of 1 second */
-};
-
-static struct resource mv78xx0_i2c_0_resources[] = {
- {
- .start = I2C_0_PHYS_BASE,
- .end = I2C_0_PHYS_BASE + 0x1f,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_MV78XX0_I2C_0,
- .end = IRQ_MV78XX0_I2C_0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-
-static struct platform_device mv78xx0_i2c_0 = {
- .name = MV64XXX_I2C_CTLR_NAME,
- .id = 0,
- .num_resources = ARRAY_SIZE(mv78xx0_i2c_0_resources),
- .resource = mv78xx0_i2c_0_resources,
- .dev = {
- .platform_data = &mv78xx0_i2c_0_pdata,
- },
-};
-
-/*****************************************************************************
- * I2C bus 1
- ****************************************************************************/
-
-static struct mv64xxx_i2c_pdata mv78xx0_i2c_1_pdata = {
- .freq_m = 8, /* assumes 166 MHz TCLK */
- .freq_n = 3,
- .timeout = 1000, /* Default timeout of 1 second */
-};
-
-static struct resource mv78xx0_i2c_1_resources[] = {
- {
- .start = I2C_1_PHYS_BASE,
- .end = I2C_1_PHYS_BASE + 0x1f,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_MV78XX0_I2C_1,
- .end = IRQ_MV78XX0_I2C_1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-
-static struct platform_device mv78xx0_i2c_1 = {
- .name = MV64XXX_I2C_CTLR_NAME,
- .id = 1,
- .num_resources = ARRAY_SIZE(mv78xx0_i2c_1_resources),
- .resource = mv78xx0_i2c_1_resources,
- .dev = {
- .platform_data = &mv78xx0_i2c_1_pdata,
- },
-};
-
void __init mv78xx0_i2c_init(void)
{
- platform_device_register(&mv78xx0_i2c_0);
- platform_device_register(&mv78xx0_i2c_1);
+ orion_i2c_init(I2C_0_PHYS_BASE, IRQ_MV78XX0_I2C_0, 8);
+ orion_i2c_1_init(I2C_1_PHYS_BASE, IRQ_MV78XX0_I2C_1, 8);
}
/*****************************************************************************
* SATA
****************************************************************************/
-static struct resource mv78xx0_sata_resources[] = {
- {
- .name = "sata base",
- .start = SATA_PHYS_BASE,
- .end = SATA_PHYS_BASE + 0x5000 - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .name = "sata irq",
- .start = IRQ_MV78XX0_SATA,
- .end = IRQ_MV78XX0_SATA,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device mv78xx0_sata = {
- .name = "sata_mv",
- .id = 0,
- .dev = {
- .coherent_dma_mask = 0xffffffff,
- },
- .num_resources = ARRAY_SIZE(mv78xx0_sata_resources),
- .resource = mv78xx0_sata_resources,
-};
-
void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data)
{
- sata_data->dram = &mv78xx0_mbus_dram_info;
- mv78xx0_sata.dev.platform_data = sata_data;
- platform_device_register(&mv78xx0_sata);
+ orion_sata_init(sata_data, &mv78xx0_mbus_dram_info,
+ SATA_PHYS_BASE, IRQ_MV78XX0_SATA);
}
/*****************************************************************************
* UART0
****************************************************************************/
-static struct plat_serial8250_port mv78xx0_uart0_data[] = {
- {
- .mapbase = UART0_PHYS_BASE,
- .membase = (char *)UART0_VIRT_BASE,
- .irq = IRQ_MV78XX0_UART_0,
- .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
- .iotype = UPIO_MEM,
- .regshift = 2,
- .uartclk = 0,
- }, {
- },
-};
-
-static struct resource mv78xx0_uart0_resources[] = {
- {
- .start = UART0_PHYS_BASE,
- .end = UART0_PHYS_BASE + 0xff,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_MV78XX0_UART_0,
- .end = IRQ_MV78XX0_UART_0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device mv78xx0_uart0 = {
- .name = "serial8250",
- .id = 0,
- .dev = {
- .platform_data = mv78xx0_uart0_data,
- },
- .resource = mv78xx0_uart0_resources,
- .num_resources = ARRAY_SIZE(mv78xx0_uart0_resources),
-};
-
void __init mv78xx0_uart0_init(void)
{
- platform_device_register(&mv78xx0_uart0);
+ orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
+ IRQ_MV78XX0_UART_0, get_tclk());
}
/*****************************************************************************
* UART1
****************************************************************************/
-static struct plat_serial8250_port mv78xx0_uart1_data[] = {
- {
- .mapbase = UART1_PHYS_BASE,
- .membase = (char *)UART1_VIRT_BASE,
- .irq = IRQ_MV78XX0_UART_1,
- .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
- .iotype = UPIO_MEM,
- .regshift = 2,
- .uartclk = 0,
- }, {
- },
-};
-
-static struct resource mv78xx0_uart1_resources[] = {
- {
- .start = UART1_PHYS_BASE,
- .end = UART1_PHYS_BASE + 0xff,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_MV78XX0_UART_1,
- .end = IRQ_MV78XX0_UART_1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device mv78xx0_uart1 = {
- .name = "serial8250",
- .id = 1,
- .dev = {
- .platform_data = mv78xx0_uart1_data,
- },
- .resource = mv78xx0_uart1_resources,
- .num_resources = ARRAY_SIZE(mv78xx0_uart1_resources),
-};
-
void __init mv78xx0_uart1_init(void)
{
- platform_device_register(&mv78xx0_uart1);
+ orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
+ IRQ_MV78XX0_UART_1, get_tclk());
}
/*****************************************************************************
* UART2
****************************************************************************/
-static struct plat_serial8250_port mv78xx0_uart2_data[] = {
- {
- .mapbase = UART2_PHYS_BASE,
- .membase = (char *)UART2_VIRT_BASE,
- .irq = IRQ_MV78XX0_UART_2,
- .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
- .iotype = UPIO_MEM,
- .regshift = 2,
- .uartclk = 0,
- }, {
- },
-};
-
-static struct resource mv78xx0_uart2_resources[] = {
- {
- .start = UART2_PHYS_BASE,
- .end = UART2_PHYS_BASE + 0xff,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_MV78XX0_UART_2,
- .end = IRQ_MV78XX0_UART_2,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device mv78xx0_uart2 = {
- .name = "serial8250",
- .id = 2,
- .dev = {
- .platform_data = mv78xx0_uart2_data,
- },
- .resource = mv78xx0_uart2_resources,
- .num_resources = ARRAY_SIZE(mv78xx0_uart2_resources),
-};
-
void __init mv78xx0_uart2_init(void)
{
- platform_device_register(&mv78xx0_uart2);
+ orion_uart2_init(UART2_VIRT_BASE, UART2_PHYS_BASE,
+ IRQ_MV78XX0_UART_2, get_tclk());
}
-
/*****************************************************************************
* UART3
****************************************************************************/
-static struct plat_serial8250_port mv78xx0_uart3_data[] = {
- {
- .mapbase = UART3_PHYS_BASE,
- .membase = (char *)UART3_VIRT_BASE,
- .irq = IRQ_MV78XX0_UART_3,
- .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
- .iotype = UPIO_MEM,
- .regshift = 2,
- .uartclk = 0,
- }, {
- },
-};
-
-static struct resource mv78xx0_uart3_resources[] = {
- {
- .start = UART3_PHYS_BASE,
- .end = UART3_PHYS_BASE + 0xff,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_MV78XX0_UART_3,
- .end = IRQ_MV78XX0_UART_3,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device mv78xx0_uart3 = {
- .name = "serial8250",
- .id = 3,
- .dev = {
- .platform_data = mv78xx0_uart3_data,
- },
- .resource = mv78xx0_uart3_resources,
- .num_resources = ARRAY_SIZE(mv78xx0_uart3_resources),
-};
-
void __init mv78xx0_uart3_init(void)
{
- platform_device_register(&mv78xx0_uart3);
+ orion_uart3_init(UART3_VIRT_BASE, UART3_PHYS_BASE,
+ IRQ_MV78XX0_UART_3, get_tclk());
}
-
/*****************************************************************************
* Time handling
****************************************************************************/
@@ -895,13 +400,4 @@
#ifdef CONFIG_CACHE_FEROCEON_L2
feroceon_l2_init(is_l2_writethrough());
#endif
-
- mv78xx0_ge00_shared_data.t_clk = tclk;
- mv78xx0_ge01_shared_data.t_clk = tclk;
- mv78xx0_ge10_shared_data.t_clk = tclk;
- mv78xx0_ge11_shared_data.t_clk = tclk;
- mv78xx0_uart0_data[0].uartclk = tclk;
- mv78xx0_uart1_data[0].uartclk = tclk;
- mv78xx0_uart2_data[0].uartclk = tclk;
- mv78xx0_uart3_data[0].uartclk = tclk;
}
diff --git a/arch/arm/mach-mv78xx0/mpp.c b/arch/arm/mach-mv78xx0/mpp.c
index 65b72c4..59b7686 100644
--- a/arch/arm/mach-mv78xx0/mpp.c
+++ b/arch/arm/mach-mv78xx0/mpp.c
@@ -12,6 +12,7 @@
#include <linux/init.h>
#include <linux/mbus.h>
#include <linux/io.h>
+#include <plat/mpp.h>
#include <asm/gpio.h>
#include <mach/hardware.h>
#include "common.h"
@@ -31,61 +32,8 @@
return 0;
}
-#define MPP_CTRL(i) (DEV_BUS_VIRT_BASE + (i) * 4)
-#define MPP_NR_REGS (1 + MPP_MAX/8)
-
void __init mv78xx0_mpp_conf(unsigned int *mpp_list)
{
- u32 mpp_ctrl[MPP_NR_REGS];
- unsigned int variant_mask;
- int i;
-
- variant_mask = mv78xx0_variant();
- if (!variant_mask)
- return;
-
- printk(KERN_DEBUG "initial MPP regs:");
- for (i = 0; i < MPP_NR_REGS; i++) {
- mpp_ctrl[i] = readl(MPP_CTRL(i));
- printk(" %08x", mpp_ctrl[i]);
- }
- printk("\n");
-
- for ( ; *mpp_list; mpp_list++) {
- unsigned int num = MPP_NUM(*mpp_list);
- unsigned int sel = MPP_SEL(*mpp_list);
- int shift, gpio_mode;
-
- if (num > MPP_MAX) {
- printk(KERN_ERR "mv78xx0_mpp_conf: invalid MPP "
- "number (%u)\n", num);
- continue;
- }
- if (!(*mpp_list & variant_mask)) {
- printk(KERN_WARNING
- "mv78xx0_mpp_conf: requested MPP%u config "
- "unavailable on this hardware\n", num);
- continue;
- }
-
- shift = (num & 7) << 2;
- mpp_ctrl[num / 8] &= ~(0xf << shift);
- mpp_ctrl[num / 8] |= sel << shift;
-
- gpio_mode = 0;
- if (*mpp_list & MPP_INPUT_MASK)
- gpio_mode |= GPIO_INPUT_OK;
- if (*mpp_list & MPP_OUTPUT_MASK)
- gpio_mode |= GPIO_OUTPUT_OK;
- if (sel != 0)
- gpio_mode = 0;
- orion_gpio_set_valid(num, gpio_mode);
- }
-
- printk(KERN_DEBUG " final MPP regs:");
- for (i = 0; i < MPP_NR_REGS; i++) {
- writel(mpp_ctrl[i], MPP_CTRL(i));
- printk(" %08x", mpp_ctrl[i]);
- }
- printk("\n");
+ orion_mpp_conf(mpp_list, mv78xx0_variant(),
+ MPP_MAX, DEV_BUS_VIRT_BASE);
}
diff --git a/arch/arm/mach-mv78xx0/mpp.h b/arch/arm/mach-mv78xx0/mpp.h
index 80840b7..b61b509 100644
--- a/arch/arm/mach-mv78xx0/mpp.h
+++ b/arch/arm/mach-mv78xx0/mpp.h
@@ -19,14 +19,8 @@
/* may be output signal */ ((!!(_out)) << 13) | \
/* available on A0 */ ((!!(_78100_A0)) << 14))
-#define MPP_NUM(x) ((x) & 0xff)
-#define MPP_SEL(x) (((x) >> 8) & 0xf)
-
/* num sel i o 78100_A0 */
-#define MPP_INPUT_MASK MPP(0, 0x0, 1, 0, 0)
-#define MPP_OUTPUT_MASK MPP(0, 0x0, 0, 1, 0)
-
#define MPP_78100_A0_MASK MPP(0, 0x0, 0, 0, 1)
#define MPP0_GPIO MPP(0, 0x0, 1, 1, 1)
diff --git a/arch/arm/mach-mx3/Kconfig b/arch/arm/mach-mx3/Kconfig
deleted file mode 100644
index 340809a..0000000
--- a/arch/arm/mach-mx3/Kconfig
+++ /dev/null
@@ -1,257 +0,0 @@
-if ARCH_MX3
-
-# ARCH_MX31 and ARCH_MX35 are left for compatibility
-# Some usages assume that having one of them implies not having (e.g.) ARCH_MX2.
-# To easily distinguish good and reviewed from unreviewed usages new (and IMHO
-# more sensible) names are used: SOC_IMX31 and SOC_IMX35
-config ARCH_MX31
- bool
-
-config ARCH_MX35
- bool
-
-config SOC_IMX31
- bool
- select IMX_HAVE_PLATFORM_MXC_RNGA
- select ARCH_MXC_AUDMUX_V2
- select ARCH_MX31
- select MXC_AVIC
-
-config SOC_IMX35
- bool
- select ARCH_MXC_IOMUX_V3
- select ARCH_MXC_AUDMUX_V2
- select HAVE_EPIT
- select ARCH_MX35
- select MXC_AVIC
-
-comment "MX3 platforms:"
-
-config MACH_MX31ADS
- bool "Support MX31ADS platforms"
- select SOC_IMX31
- select IMX_HAVE_PLATFORM_IMX_I2C
- select IMX_HAVE_PLATFORM_IMX_SSI
- select IMX_HAVE_PLATFORM_IMX_UART
- default y
- help
- Include support for MX31ADS platform. This includes specific
- configurations for the board and its peripherals.
-
-config MACH_MX31ADS_WM1133_EV1
- bool "Support Wolfson Microelectronics 1133-EV1 module"
- depends on MACH_MX31ADS
- depends on MFD_WM8350_I2C
- depends on REGULATOR_WM8350
- select MFD_WM8350_CONFIG_MODE_0
- select MFD_WM8352_CONFIG_MODE_0
- help
- Include support for the Wolfson Microelectronics 1133-EV1 PMU
- and audio module for the MX31ADS platform.
-
-config MACH_PCM037
- bool "Support Phytec pcm037 (i.MX31) platforms"
- select SOC_IMX31
- select IMX_HAVE_PLATFORM_FSL_USB2_UDC
- select IMX_HAVE_PLATFORM_IMX2_WDT
- select IMX_HAVE_PLATFORM_IMX_I2C
- select IMX_HAVE_PLATFORM_IMX_UART
- select IMX_HAVE_PLATFORM_MXC_EHCI
- select IMX_HAVE_PLATFORM_MXC_MMC
- select IMX_HAVE_PLATFORM_MXC_NAND
- select IMX_HAVE_PLATFORM_MXC_W1
- select MXC_ULPI if USB_ULPI
- help
- Include support for Phytec pcm037 platform. This includes
- specific configurations for the board and its peripherals.
-
-config MACH_PCM037_EET
- bool "Support pcm037 EET board extensions"
- depends on MACH_PCM037
- select IMX_HAVE_PLATFORM_SPI_IMX
- help
- Add support for PCM037 EET baseboard extensions. If you are using the
- OLED display with EET, use "video=mx3fb:CMEL-OLED" kernel
- command-line parameter.
-
-config MACH_MX31LITE
- bool "Support MX31 LITEKIT (LogicPD)"
- select SOC_IMX31
- select MXC_ULPI if USB_ULPI
- select IMX_HAVE_PLATFORM_IMX2_WDT
- select IMX_HAVE_PLATFORM_IMX_UART
- select IMX_HAVE_PLATFORM_MXC_EHCI
- select IMX_HAVE_PLATFORM_MXC_MMC
- select IMX_HAVE_PLATFORM_MXC_NAND
- select IMX_HAVE_PLATFORM_SPI_IMX
- help
- Include support for MX31 LITEKIT platform. This includes specific
- configurations for the board and its peripherals.
-
-config MACH_MX31_3DS
- bool "Support MX31PDK (3DS)"
- select SOC_IMX31
- select MXC_DEBUG_BOARD
- select IMX_HAVE_PLATFORM_FSL_USB2_UDC
- select IMX_HAVE_PLATFORM_IMX2_WDT
- select IMX_HAVE_PLATFORM_IMX_I2C
- select IMX_HAVE_PLATFORM_IMX_KEYPAD
- select IMX_HAVE_PLATFORM_IMX_UART
- select IMX_HAVE_PLATFORM_MXC_EHCI
- select IMX_HAVE_PLATFORM_MXC_NAND
- select IMX_HAVE_PLATFORM_SPI_IMX
- select MXC_ULPI if USB_ULPI
- help
- Include support for MX31PDK (3DS) platform. This includes specific
- configurations for the board and its peripherals.
-
-config MACH_MX31_3DS_MXC_NAND_USE_BBT
- bool "Make the MXC NAND driver use the in flash Bad Block Table"
- depends on MACH_MX31_3DS
- depends on MTD_NAND_MXC
- help
- Enable this if you want that the MXC NAND driver uses the in flash
- Bad Block Table to know what blocks are bad instead of scanning the
- entire flash looking for bad block markers.
-
-config MACH_MX31MOBOARD
- bool "Support mx31moboard platforms (EPFL Mobots group)"
- select SOC_IMX31
- select IMX_HAVE_PLATFORM_FSL_USB2_UDC
- select IMX_HAVE_PLATFORM_IMX_I2C
- select IMX_HAVE_PLATFORM_IMX_UART
- select IMX_HAVE_PLATFORM_MXC_EHCI
- select IMX_HAVE_PLATFORM_MXC_MMC
- select IMX_HAVE_PLATFORM_SPI_IMX
- select MXC_ULPI if USB_ULPI
- help
- Include support for mx31moboard platform. This includes specific
- configurations for the board and its peripherals.
-
-config MACH_MX31LILLY
- bool "Support MX31 LILLY-1131 platforms (INCO startec)"
- select SOC_IMX31
- select IMX_HAVE_PLATFORM_IMX_UART
- select IMX_HAVE_PLATFORM_MXC_EHCI
- select IMX_HAVE_PLATFORM_MXC_MMC
- select IMX_HAVE_PLATFORM_SPI_IMX
- select MXC_ULPI if USB_ULPI
- help
- Include support for mx31 based LILLY1131 modules. This includes
- specific configurations for the board and its peripherals.
-
-config MACH_QONG
- bool "Support Dave/DENX QongEVB-LITE platform"
- select SOC_IMX31
- select IMX_HAVE_PLATFORM_IMX_UART
- help
- Include support for Dave/DENX QongEVB-LITE platform. This includes
- specific configurations for the board and its peripherals.
-
-config MACH_PCM043
- bool "Support Phytec pcm043 (i.MX35) platforms"
- select SOC_IMX35
- select IMX_HAVE_PLATFORM_FLEXCAN
- select IMX_HAVE_PLATFORM_FSL_USB2_UDC
- select IMX_HAVE_PLATFORM_IMX2_WDT
- select IMX_HAVE_PLATFORM_IMX_I2C
- select IMX_HAVE_PLATFORM_IMX_SSI
- select IMX_HAVE_PLATFORM_IMX_UART
- select IMX_HAVE_PLATFORM_MXC_EHCI
- select IMX_HAVE_PLATFORM_MXC_NAND
- select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
- select MXC_ULPI if USB_ULPI
- help
- Include support for Phytec pcm043 platform. This includes
- specific configurations for the board and its peripherals.
-
-config MACH_ARMADILLO5X0
- bool "Support Atmark Armadillo-500 Development Base Board"
- select SOC_IMX31
- select IMX_HAVE_PLATFORM_IMX_I2C
- select IMX_HAVE_PLATFORM_IMX_UART
- select IMX_HAVE_PLATFORM_MXC_EHCI
- select IMX_HAVE_PLATFORM_MXC_MMC
- select IMX_HAVE_PLATFORM_MXC_NAND
- select MXC_ULPI if USB_ULPI
- help
- Include support for Atmark Armadillo-500 platform. This includes
- specific configurations for the board and its peripherals.
-
-config MACH_MX35_3DS
- bool "Support MX35PDK platform"
- select SOC_IMX35
- select MXC_DEBUG_BOARD
- select IMX_HAVE_PLATFORM_FSL_USB2_UDC
- select IMX_HAVE_PLATFORM_IMX2_WDT
- select IMX_HAVE_PLATFORM_IMX_I2C
- select IMX_HAVE_PLATFORM_IMX_UART
- select IMX_HAVE_PLATFORM_MXC_EHCI
- select IMX_HAVE_PLATFORM_MXC_NAND
- select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
- help
- Include support for MX35PDK platform. This includes specific
- configurations for the board and its peripherals.
-
-config MACH_KZM_ARM11_01
- bool "Support KZM-ARM11-01(Kyoto Microcomputer)"
- select SOC_IMX31
- select IMX_HAVE_PLATFORM_IMX_UART
- help
- Include support for KZM-ARM11-01. This includes specific
- configurations for the board and its peripherals.
-
-config MACH_BUG
- bool "Support Buglabs BUGBase platform"
- select SOC_IMX31
- select IMX_HAVE_PLATFORM_IMX_UART
- default y
- help
- Include support for BUGBase 1.3 platform. This includes specific
- configurations for the board and its peripherals.
-
-config MACH_EUKREA_CPUIMX35
- bool "Support Eukrea CPUIMX35 Platform"
- select SOC_IMX35
- select IMX_HAVE_PLATFORM_FLEXCAN
- select IMX_HAVE_PLATFORM_FSL_USB2_UDC
- select IMX_HAVE_PLATFORM_IMX2_WDT
- select IMX_HAVE_PLATFORM_IMX_I2C
- select IMX_HAVE_PLATFORM_IMX_UART
- select IMX_HAVE_PLATFORM_MXC_EHCI
- select IMX_HAVE_PLATFORM_MXC_NAND
- select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
- select MXC_ULPI if USB_ULPI
- help
- Include support for Eukrea CPUIMX35 platform. This includes
- specific configurations for the board and its peripherals.
-
-choice
- prompt "Baseboard"
- depends on MACH_EUKREA_CPUIMX35
- default MACH_EUKREA_MBIMXSD35_BASEBOARD
-
-config MACH_EUKREA_MBIMXSD35_BASEBOARD
- bool "Eukrea MBIMXSD development board"
- select IMX_HAVE_PLATFORM_IMX_SSI
- help
- This adds board specific devices that can be found on Eukrea's
- MBIMXSD evaluation board.
-
-endchoice
-
-config MACH_VPR200
- bool "Support VPR200 platform"
- select SOC_IMX35
- select IMX_HAVE_PLATFORM_FSL_USB2_UDC
- select IMX_HAVE_PLATFORM_IMX2_WDT
- select IMX_HAVE_PLATFORM_IMX_UART
- select IMX_HAVE_PLATFORM_IMX_I2C
- select IMX_HAVE_PLATFORM_MXC_EHCI
- select IMX_HAVE_PLATFORM_MXC_NAND
- select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
- help
- Include support for VPR200 platform. This includes specific
- configurations for the board and its peripherals.
-
-endif
diff --git a/arch/arm/mach-mx3/Makefile b/arch/arm/mach-mx3/Makefile
deleted file mode 100644
index a54faf2..0000000
--- a/arch/arm/mach-mx3/Makefile
+++ /dev/null
@@ -1,26 +0,0 @@
-#
-# Makefile for the linux kernel.
-#
-
-# Object file lists.
-
-obj-y := mm.o devices.o cpu.o
-obj-$(CONFIG_SOC_IMX31) += clock-imx31.o iomux-imx31.o ehci-imx31.o
-obj-$(CONFIG_SOC_IMX35) += clock-imx35.o ehci-imx35.o
-obj-$(CONFIG_MACH_MX31ADS) += mach-mx31ads.o
-obj-$(CONFIG_MACH_MX31LILLY) += mach-mx31lilly.o mx31lilly-db.o
-obj-$(CONFIG_MACH_MX31LITE) += mach-mx31lite.o mx31lite-db.o
-obj-$(CONFIG_MACH_PCM037) += mach-pcm037.o
-obj-$(CONFIG_MACH_PCM037_EET) += mach-pcm037_eet.o
-obj-$(CONFIG_MACH_MX31_3DS) += mach-mx31_3ds.o
-obj-$(CONFIG_MACH_MX31MOBOARD) += mach-mx31moboard.o mx31moboard-devboard.o \
- mx31moboard-marxbot.o mx31moboard-smartbot.o
-obj-$(CONFIG_MACH_QONG) += mach-qong.o
-obj-$(CONFIG_MACH_PCM043) += mach-pcm043.o
-obj-$(CONFIG_MACH_ARMADILLO5X0) += mach-armadillo5x0.o
-obj-$(CONFIG_MACH_MX35_3DS) += mach-mx35_3ds.o
-obj-$(CONFIG_MACH_KZM_ARM11_01) += mach-kzm_arm11_01.o
-obj-$(CONFIG_MACH_BUG) += mach-bug.o
-obj-$(CONFIG_MACH_EUKREA_CPUIMX35) += mach-cpuimx35.o
-obj-$(CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD) += eukrea_mbimxsd-baseboard.o
-obj-$(CONFIG_MACH_VPR200) += mach-vpr200.o
diff --git a/arch/arm/mach-mx3/Makefile.boot b/arch/arm/mach-mx3/Makefile.boot
deleted file mode 100644
index e1dd366..0000000
--- a/arch/arm/mach-mx3/Makefile.boot
+++ /dev/null
@@ -1,3 +0,0 @@
- zreladdr-y := 0x80008000
-params_phys-y := 0x80000100
-initrd_phys-y := 0x80800000
diff --git a/arch/arm/mach-mx3/clock-imx31.c b/arch/arm/mach-mx3/clock-imx31.c
deleted file mode 100644
index d423cac..0000000
--- a/arch/arm/mach-mx3/clock-imx31.c
+++ /dev/null
@@ -1,630 +0,0 @@
-/*
- * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#include <linux/module.h>
-#include <linux/spinlock.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/clkdev.h>
-
-#include <asm/div64.h>
-
-#include <mach/clock.h>
-#include <mach/hardware.h>
-#include <mach/mx31.h>
-#include <mach/common.h>
-
-#include "crm_regs.h"
-
-#define PRE_DIV_MIN_FREQ 10000000 /* Minimum Frequency after Predivider */
-
-static void __calc_pre_post_dividers(u32 div, u32 *pre, u32 *post)
-{
- u32 min_pre, temp_pre, old_err, err;
-
- if (div >= 512) {
- *pre = 8;
- *post = 64;
- } else if (div >= 64) {
- min_pre = (div - 1) / 64 + 1;
- old_err = 8;
- for (temp_pre = 8; temp_pre >= min_pre; temp_pre--) {
- err = div % temp_pre;
- if (err == 0) {
- *pre = temp_pre;
- break;
- }
- err = temp_pre - err;
- if (err < old_err) {
- old_err = err;
- *pre = temp_pre;
- }
- }
- *post = (div + *pre - 1) / *pre;
- } else if (div <= 8) {
- *pre = div;
- *post = 1;
- } else {
- *pre = 1;
- *post = div;
- }
-}
-
-static struct clk mcu_pll_clk;
-static struct clk serial_pll_clk;
-static struct clk ipg_clk;
-static struct clk ckih_clk;
-
-static int cgr_enable(struct clk *clk)
-{
- u32 reg;
-
- if (!clk->enable_reg)
- return 0;
-
- reg = __raw_readl(clk->enable_reg);
- reg |= 3 << clk->enable_shift;
- __raw_writel(reg, clk->enable_reg);
-
- return 0;
-}
-
-static void cgr_disable(struct clk *clk)
-{
- u32 reg;
-
- if (!clk->enable_reg)
- return;
-
- reg = __raw_readl(clk->enable_reg);
- reg &= ~(3 << clk->enable_shift);
-
- /* special case for EMI clock */
- if (clk->enable_reg == MXC_CCM_CGR2 && clk->enable_shift == 8)
- reg |= (1 << clk->enable_shift);
-
- __raw_writel(reg, clk->enable_reg);
-}
-
-static unsigned long pll_ref_get_rate(void)
-{
- unsigned long ccmr;
- unsigned int prcs;
-
- ccmr = __raw_readl(MXC_CCM_CCMR);
- prcs = (ccmr & MXC_CCM_CCMR_PRCS_MASK) >> MXC_CCM_CCMR_PRCS_OFFSET;
- if (prcs == 0x1)
- return CKIL_CLK_FREQ * 1024;
- else
- return clk_get_rate(&ckih_clk);
-}
-
-static unsigned long usb_pll_get_rate(struct clk *clk)
-{
- unsigned long reg;
-
- reg = __raw_readl(MXC_CCM_UPCTL);
-
- return mxc_decode_pll(reg, pll_ref_get_rate());
-}
-
-static unsigned long serial_pll_get_rate(struct clk *clk)
-{
- unsigned long reg;
-
- reg = __raw_readl(MXC_CCM_SRPCTL);
-
- return mxc_decode_pll(reg, pll_ref_get_rate());
-}
-
-static unsigned long mcu_pll_get_rate(struct clk *clk)
-{
- unsigned long reg, ccmr;
-
- ccmr = __raw_readl(MXC_CCM_CCMR);
-
- if (!(ccmr & MXC_CCM_CCMR_MPE) || (ccmr & MXC_CCM_CCMR_MDS))
- return clk_get_rate(&ckih_clk);
-
- reg = __raw_readl(MXC_CCM_MPCTL);
-
- return mxc_decode_pll(reg, pll_ref_get_rate());
-}
-
-static int usb_pll_enable(struct clk *clk)
-{
- u32 reg;
-
- reg = __raw_readl(MXC_CCM_CCMR);
- reg |= MXC_CCM_CCMR_UPE;
- __raw_writel(reg, MXC_CCM_CCMR);
-
- /* No lock bit on MX31, so using max time from spec */
- udelay(80);
-
- return 0;
-}
-
-static void usb_pll_disable(struct clk *clk)
-{
- u32 reg;
-
- reg = __raw_readl(MXC_CCM_CCMR);
- reg &= ~MXC_CCM_CCMR_UPE;
- __raw_writel(reg, MXC_CCM_CCMR);
-}
-
-static int serial_pll_enable(struct clk *clk)
-{
- u32 reg;
-
- reg = __raw_readl(MXC_CCM_CCMR);
- reg |= MXC_CCM_CCMR_SPE;
- __raw_writel(reg, MXC_CCM_CCMR);
-
- /* No lock bit on MX31, so using max time from spec */
- udelay(80);
-
- return 0;
-}
-
-static void serial_pll_disable(struct clk *clk)
-{
- u32 reg;
-
- reg = __raw_readl(MXC_CCM_CCMR);
- reg &= ~MXC_CCM_CCMR_SPE;
- __raw_writel(reg, MXC_CCM_CCMR);
-}
-
-#define PDR0(mask, off) ((__raw_readl(MXC_CCM_PDR0) & mask) >> off)
-#define PDR1(mask, off) ((__raw_readl(MXC_CCM_PDR1) & mask) >> off)
-#define PDR2(mask, off) ((__raw_readl(MXC_CCM_PDR2) & mask) >> off)
-
-static unsigned long mcu_main_get_rate(struct clk *clk)
-{
- u32 pmcr0 = __raw_readl(MXC_CCM_PMCR0);
-
- if ((pmcr0 & MXC_CCM_PMCR0_DFSUP1) == MXC_CCM_PMCR0_DFSUP1_SPLL)
- return clk_get_rate(&serial_pll_clk);
- else
- return clk_get_rate(&mcu_pll_clk);
-}
-
-static unsigned long ahb_get_rate(struct clk *clk)
-{
- unsigned long max_pdf;
-
- max_pdf = PDR0(MXC_CCM_PDR0_MAX_PODF_MASK,
- MXC_CCM_PDR0_MAX_PODF_OFFSET);
- return clk_get_rate(clk->parent) / (max_pdf + 1);
-}
-
-static unsigned long ipg_get_rate(struct clk *clk)
-{
- unsigned long ipg_pdf;
-
- ipg_pdf = PDR0(MXC_CCM_PDR0_IPG_PODF_MASK,
- MXC_CCM_PDR0_IPG_PODF_OFFSET);
- return clk_get_rate(clk->parent) / (ipg_pdf + 1);
-}
-
-static unsigned long nfc_get_rate(struct clk *clk)
-{
- unsigned long nfc_pdf;
-
- nfc_pdf = PDR0(MXC_CCM_PDR0_NFC_PODF_MASK,
- MXC_CCM_PDR0_NFC_PODF_OFFSET);
- return clk_get_rate(clk->parent) / (nfc_pdf + 1);
-}
-
-static unsigned long hsp_get_rate(struct clk *clk)
-{
- unsigned long hsp_pdf;
-
- hsp_pdf = PDR0(MXC_CCM_PDR0_HSP_PODF_MASK,
- MXC_CCM_PDR0_HSP_PODF_OFFSET);
- return clk_get_rate(clk->parent) / (hsp_pdf + 1);
-}
-
-static unsigned long usb_get_rate(struct clk *clk)
-{
- unsigned long usb_pdf, usb_prepdf;
-
- usb_pdf = PDR1(MXC_CCM_PDR1_USB_PODF_MASK,
- MXC_CCM_PDR1_USB_PODF_OFFSET);
- usb_prepdf = PDR1(MXC_CCM_PDR1_USB_PRDF_MASK,
- MXC_CCM_PDR1_USB_PRDF_OFFSET);
- return clk_get_rate(clk->parent) / (usb_prepdf + 1) / (usb_pdf + 1);
-}
-
-static unsigned long csi_get_rate(struct clk *clk)
-{
- u32 reg, pre, post;
-
- reg = __raw_readl(MXC_CCM_PDR0);
- pre = (reg & MXC_CCM_PDR0_CSI_PRDF_MASK) >>
- MXC_CCM_PDR0_CSI_PRDF_OFFSET;
- pre++;
- post = (reg & MXC_CCM_PDR0_CSI_PODF_MASK) >>
- MXC_CCM_PDR0_CSI_PODF_OFFSET;
- post++;
- return clk_get_rate(clk->parent) / (pre * post);
-}
-
-static unsigned long csi_round_rate(struct clk *clk, unsigned long rate)
-{
- u32 pre, post, parent = clk_get_rate(clk->parent);
- u32 div = parent / rate;
-
- if (parent % rate)
- div++;
-
- __calc_pre_post_dividers(div, &pre, &post);
-
- return parent / (pre * post);
-}
-
-static int csi_set_rate(struct clk *clk, unsigned long rate)
-{
- u32 reg, div, pre, post, parent = clk_get_rate(clk->parent);
-
- div = parent / rate;
-
- if ((parent / div) != rate)
- return -EINVAL;
-
- __calc_pre_post_dividers(div, &pre, &post);
-
- /* Set CSI clock divider */
- reg = __raw_readl(MXC_CCM_PDR0) &
- ~(MXC_CCM_PDR0_CSI_PODF_MASK | MXC_CCM_PDR0_CSI_PRDF_MASK);
- reg |= (post - 1) << MXC_CCM_PDR0_CSI_PODF_OFFSET;
- reg |= (pre - 1) << MXC_CCM_PDR0_CSI_PRDF_OFFSET;
- __raw_writel(reg, MXC_CCM_PDR0);
-
- return 0;
-}
-
-static unsigned long ssi1_get_rate(struct clk *clk)
-{
- unsigned long ssi1_pdf, ssi1_prepdf;
-
- ssi1_pdf = PDR1(MXC_CCM_PDR1_SSI1_PODF_MASK,
- MXC_CCM_PDR1_SSI1_PODF_OFFSET);
- ssi1_prepdf = PDR1(MXC_CCM_PDR1_SSI1_PRE_PODF_MASK,
- MXC_CCM_PDR1_SSI1_PRE_PODF_OFFSET);
- return clk_get_rate(clk->parent) / (ssi1_prepdf + 1) / (ssi1_pdf + 1);
-}
-
-static unsigned long ssi2_get_rate(struct clk *clk)
-{
- unsigned long ssi2_pdf, ssi2_prepdf;
-
- ssi2_pdf = PDR1(MXC_CCM_PDR1_SSI2_PODF_MASK,
- MXC_CCM_PDR1_SSI2_PODF_OFFSET);
- ssi2_prepdf = PDR1(MXC_CCM_PDR1_SSI2_PRE_PODF_MASK,
- MXC_CCM_PDR1_SSI2_PRE_PODF_OFFSET);
- return clk_get_rate(clk->parent) / (ssi2_prepdf + 1) / (ssi2_pdf + 1);
-}
-
-static unsigned long firi_get_rate(struct clk *clk)
-{
- unsigned long firi_pdf, firi_prepdf;
-
- firi_pdf = PDR1(MXC_CCM_PDR1_FIRI_PODF_MASK,
- MXC_CCM_PDR1_FIRI_PODF_OFFSET);
- firi_prepdf = PDR1(MXC_CCM_PDR1_FIRI_PRE_PODF_MASK,
- MXC_CCM_PDR1_FIRI_PRE_PODF_OFFSET);
- return clk_get_rate(clk->parent) / (firi_prepdf + 1) / (firi_pdf + 1);
-}
-
-static unsigned long firi_round_rate(struct clk *clk, unsigned long rate)
-{
- u32 pre, post;
- u32 parent = clk_get_rate(clk->parent);
- u32 div = parent / rate;
-
- if (parent % rate)
- div++;
-
- __calc_pre_post_dividers(div, &pre, &post);
-
- return parent / (pre * post);
-
-}
-
-static int firi_set_rate(struct clk *clk, unsigned long rate)
-{
- u32 reg, div, pre, post, parent = clk_get_rate(clk->parent);
-
- div = parent / rate;
-
- if ((parent / div) != rate)
- return -EINVAL;
-
- __calc_pre_post_dividers(div, &pre, &post);
-
- /* Set FIRI clock divider */
- reg = __raw_readl(MXC_CCM_PDR1) &
- ~(MXC_CCM_PDR1_FIRI_PODF_MASK | MXC_CCM_PDR1_FIRI_PRE_PODF_MASK);
- reg |= (pre - 1) << MXC_CCM_PDR1_FIRI_PRE_PODF_OFFSET;
- reg |= (post - 1) << MXC_CCM_PDR1_FIRI_PODF_OFFSET;
- __raw_writel(reg, MXC_CCM_PDR1);
-
- return 0;
-}
-
-static unsigned long mbx_get_rate(struct clk *clk)
-{
- return clk_get_rate(clk->parent) / 2;
-}
-
-static unsigned long mstick1_get_rate(struct clk *clk)
-{
- unsigned long msti_pdf;
-
- msti_pdf = PDR2(MXC_CCM_PDR2_MST1_PDF_MASK,
- MXC_CCM_PDR2_MST1_PDF_OFFSET);
- return clk_get_rate(clk->parent) / (msti_pdf + 1);
-}
-
-static unsigned long mstick2_get_rate(struct clk *clk)
-{
- unsigned long msti_pdf;
-
- msti_pdf = PDR2(MXC_CCM_PDR2_MST2_PDF_MASK,
- MXC_CCM_PDR2_MST2_PDF_OFFSET);
- return clk_get_rate(clk->parent) / (msti_pdf + 1);
-}
-
-static unsigned long ckih_rate;
-
-static unsigned long clk_ckih_get_rate(struct clk *clk)
-{
- return ckih_rate;
-}
-
-static unsigned long clk_ckil_get_rate(struct clk *clk)
-{
- return CKIL_CLK_FREQ;
-}
-
-static struct clk ckih_clk = {
- .get_rate = clk_ckih_get_rate,
-};
-
-static struct clk mcu_pll_clk = {
- .parent = &ckih_clk,
- .get_rate = mcu_pll_get_rate,
-};
-
-static struct clk mcu_main_clk = {
- .parent = &mcu_pll_clk,
- .get_rate = mcu_main_get_rate,
-};
-
-static struct clk serial_pll_clk = {
- .parent = &ckih_clk,
- .get_rate = serial_pll_get_rate,
- .enable = serial_pll_enable,
- .disable = serial_pll_disable,
-};
-
-static struct clk usb_pll_clk = {
- .parent = &ckih_clk,
- .get_rate = usb_pll_get_rate,
- .enable = usb_pll_enable,
- .disable = usb_pll_disable,
-};
-
-static struct clk ahb_clk = {
- .parent = &mcu_main_clk,
- .get_rate = ahb_get_rate,
-};
-
-#define DEFINE_CLOCK(name, i, er, es, gr, s, p) \
- static struct clk name = { \
- .id = i, \
- .enable_reg = er, \
- .enable_shift = es, \
- .get_rate = gr, \
- .enable = cgr_enable, \
- .disable = cgr_disable, \
- .secondary = s, \
- .parent = p, \
- }
-
-#define DEFINE_CLOCK1(name, i, er, es, getsetround, s, p) \
- static struct clk name = { \
- .id = i, \
- .enable_reg = er, \
- .enable_shift = es, \
- .get_rate = getsetround##_get_rate, \
- .set_rate = getsetround##_set_rate, \
- .round_rate = getsetround##_round_rate, \
- .enable = cgr_enable, \
- .disable = cgr_disable, \
- .secondary = s, \
- .parent = p, \
- }
-
-DEFINE_CLOCK(perclk_clk, 0, NULL, 0, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(ckil_clk, 0, NULL, 0, clk_ckil_get_rate, NULL, NULL);
-
-DEFINE_CLOCK(sdhc1_clk, 0, MXC_CCM_CGR0, 0, NULL, NULL, &perclk_clk);
-DEFINE_CLOCK(sdhc2_clk, 1, MXC_CCM_CGR0, 2, NULL, NULL, &perclk_clk);
-DEFINE_CLOCK(gpt_clk, 0, MXC_CCM_CGR0, 4, NULL, NULL, &perclk_clk);
-DEFINE_CLOCK(epit1_clk, 0, MXC_CCM_CGR0, 6, NULL, NULL, &perclk_clk);
-DEFINE_CLOCK(epit2_clk, 1, MXC_CCM_CGR0, 8, NULL, NULL, &perclk_clk);
-DEFINE_CLOCK(iim_clk, 0, MXC_CCM_CGR0, 10, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(ata_clk, 0, MXC_CCM_CGR0, 12, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(sdma_clk1, 0, MXC_CCM_CGR0, 14, NULL, NULL, &ahb_clk);
-DEFINE_CLOCK(cspi3_clk, 2, MXC_CCM_CGR0, 16, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(rng_clk, 0, MXC_CCM_CGR0, 18, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(uart1_clk, 0, MXC_CCM_CGR0, 20, NULL, NULL, &perclk_clk);
-DEFINE_CLOCK(uart2_clk, 1, MXC_CCM_CGR0, 22, NULL, NULL, &perclk_clk);
-DEFINE_CLOCK(ssi1_clk, 0, MXC_CCM_CGR0, 24, ssi1_get_rate, NULL, &serial_pll_clk);
-DEFINE_CLOCK(i2c1_clk, 0, MXC_CCM_CGR0, 26, NULL, NULL, &perclk_clk);
-DEFINE_CLOCK(i2c2_clk, 1, MXC_CCM_CGR0, 28, NULL, NULL, &perclk_clk);
-DEFINE_CLOCK(i2c3_clk, 2, MXC_CCM_CGR0, 30, NULL, NULL, &perclk_clk);
-
-DEFINE_CLOCK(mpeg4_clk, 0, MXC_CCM_CGR1, 0, NULL, NULL, &ahb_clk);
-DEFINE_CLOCK(mstick1_clk, 0, MXC_CCM_CGR1, 2, mstick1_get_rate, NULL, &usb_pll_clk);
-DEFINE_CLOCK(mstick2_clk, 1, MXC_CCM_CGR1, 4, mstick2_get_rate, NULL, &usb_pll_clk);
-DEFINE_CLOCK1(csi_clk, 0, MXC_CCM_CGR1, 6, csi, NULL, &serial_pll_clk);
-DEFINE_CLOCK(rtc_clk, 0, MXC_CCM_CGR1, 8, NULL, NULL, &ckil_clk);
-DEFINE_CLOCK(wdog_clk, 0, MXC_CCM_CGR1, 10, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(pwm_clk, 0, MXC_CCM_CGR1, 12, NULL, NULL, &perclk_clk);
-DEFINE_CLOCK(usb_clk2, 0, MXC_CCM_CGR1, 18, usb_get_rate, NULL, &ahb_clk);
-DEFINE_CLOCK(kpp_clk, 0, MXC_CCM_CGR1, 20, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(ipu_clk, 0, MXC_CCM_CGR1, 22, hsp_get_rate, NULL, &mcu_main_clk);
-DEFINE_CLOCK(uart3_clk, 2, MXC_CCM_CGR1, 24, NULL, NULL, &perclk_clk);
-DEFINE_CLOCK(uart4_clk, 3, MXC_CCM_CGR1, 26, NULL, NULL, &perclk_clk);
-DEFINE_CLOCK(uart5_clk, 4, MXC_CCM_CGR1, 28, NULL, NULL, &perclk_clk);
-DEFINE_CLOCK(owire_clk, 0, MXC_CCM_CGR1, 30, NULL, NULL, &perclk_clk);
-
-DEFINE_CLOCK(ssi2_clk, 1, MXC_CCM_CGR2, 0, ssi2_get_rate, NULL, &serial_pll_clk);
-DEFINE_CLOCK(cspi1_clk, 0, MXC_CCM_CGR2, 2, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(cspi2_clk, 1, MXC_CCM_CGR2, 4, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(mbx_clk, 0, MXC_CCM_CGR2, 6, mbx_get_rate, NULL, &ahb_clk);
-DEFINE_CLOCK(emi_clk, 0, MXC_CCM_CGR2, 8, NULL, NULL, &ahb_clk);
-DEFINE_CLOCK(rtic_clk, 0, MXC_CCM_CGR2, 10, NULL, NULL, &ahb_clk);
-DEFINE_CLOCK1(firi_clk, 0, MXC_CCM_CGR2, 12, firi, NULL, &usb_pll_clk);
-
-DEFINE_CLOCK(sdma_clk2, 0, NULL, 0, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(usb_clk1, 0, NULL, 0, usb_get_rate, NULL, &usb_pll_clk);
-DEFINE_CLOCK(nfc_clk, 0, NULL, 0, nfc_get_rate, NULL, &ahb_clk);
-DEFINE_CLOCK(scc_clk, 0, NULL, 0, NULL, NULL, &ipg_clk);
-DEFINE_CLOCK(ipg_clk, 0, NULL, 0, ipg_get_rate, NULL, &ahb_clk);
-
-#define _REGISTER_CLOCK(d, n, c) \
- { \
- .dev_id = d, \
- .con_id = n, \
- .clk = &c, \
- },
-
-static struct clk_lookup lookups[] = {
- _REGISTER_CLOCK(NULL, "emi", emi_clk)
- _REGISTER_CLOCK("imx31-cspi.0", NULL, cspi1_clk)
- _REGISTER_CLOCK("imx31-cspi.1", NULL, cspi2_clk)
- _REGISTER_CLOCK("imx31-cspi.2", NULL, cspi3_clk)
- _REGISTER_CLOCK(NULL, "gpt", gpt_clk)
- _REGISTER_CLOCK(NULL, "pwm", pwm_clk)
- _REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk)
- _REGISTER_CLOCK(NULL, "rtc", rtc_clk)
- _REGISTER_CLOCK(NULL, "epit", epit1_clk)
- _REGISTER_CLOCK(NULL, "epit", epit2_clk)
- _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
- _REGISTER_CLOCK("ipu-core", NULL, ipu_clk)
- _REGISTER_CLOCK("mx3_sdc_fb", NULL, ipu_clk)
- _REGISTER_CLOCK(NULL, "kpp", kpp_clk)
- _REGISTER_CLOCK("mxc-ehci.0", "usb", usb_clk1)
- _REGISTER_CLOCK("mxc-ehci.0", "usb_ahb", usb_clk2)
- _REGISTER_CLOCK("mxc-ehci.1", "usb", usb_clk1)
- _REGISTER_CLOCK("mxc-ehci.1", "usb_ahb", usb_clk2)
- _REGISTER_CLOCK("mxc-ehci.2", "usb", usb_clk1)
- _REGISTER_CLOCK("mxc-ehci.2", "usb_ahb", usb_clk2)
- _REGISTER_CLOCK("fsl-usb2-udc", "usb", usb_clk1)
- _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usb_clk2)
- _REGISTER_CLOCK("mx3-camera.0", NULL, csi_clk)
- _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
- _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
- _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
- _REGISTER_CLOCK("imx-uart.3", NULL, uart4_clk)
- _REGISTER_CLOCK("imx-uart.4", NULL, uart5_clk)
- _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
- _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
- _REGISTER_CLOCK("imx-i2c.2", NULL, i2c3_clk)
- _REGISTER_CLOCK("mxc_w1.0", NULL, owire_clk)
- _REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc1_clk)
- _REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc2_clk)
- _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
- _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
- _REGISTER_CLOCK(NULL, "firi", firi_clk)
- _REGISTER_CLOCK(NULL, "ata", ata_clk)
- _REGISTER_CLOCK(NULL, "rtic", rtic_clk)
- _REGISTER_CLOCK(NULL, "rng", rng_clk)
- _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk1)
- _REGISTER_CLOCK(NULL, "sdma_ipg", sdma_clk2)
- _REGISTER_CLOCK(NULL, "mstick", mstick1_clk)
- _REGISTER_CLOCK(NULL, "mstick", mstick2_clk)
- _REGISTER_CLOCK(NULL, "scc", scc_clk)
- _REGISTER_CLOCK(NULL, "iim", iim_clk)
- _REGISTER_CLOCK(NULL, "mpeg4", mpeg4_clk)
- _REGISTER_CLOCK(NULL, "mbx", mbx_clk)
-};
-
-int __init mx31_clocks_init(unsigned long fref)
-{
- u32 reg;
-
- ckih_rate = fref;
-
- clkdev_add_table(lookups, ARRAY_SIZE(lookups));
-
- /* change the csi_clk parent if necessary */
- reg = __raw_readl(MXC_CCM_CCMR);
- if (!(reg & MXC_CCM_CCMR_CSCS))
- if (clk_set_parent(&csi_clk, &usb_pll_clk))
- pr_err("%s: error changing csi_clk parent\n", __func__);
-
-
- /* Turn off all possible clocks */
- __raw_writel((3 << 4), MXC_CCM_CGR0);
- __raw_writel(0, MXC_CCM_CGR1);
- __raw_writel((3 << 8) | (3 << 14) | (3 << 16)|
- 1 << 27 | 1 << 28, /* Bit 27 and 28 are not defined for
- MX32, but still required to be set */
- MXC_CCM_CGR2);
-
- /*
- * Before turning off usb_pll make sure ipg_per_clk is generated
- * by ipg_clk and not usb_pll.
- */
- __raw_writel(__raw_readl(MXC_CCM_CCMR) | (1 << 24), MXC_CCM_CCMR);
-
- usb_pll_disable(&usb_pll_clk);
-
- pr_info("Clock input source is %ld\n", clk_get_rate(&ckih_clk));
-
- clk_enable(&gpt_clk);
- clk_enable(&emi_clk);
- clk_enable(&iim_clk);
-
- clk_enable(&serial_pll_clk);
-
- mx31_read_cpu_rev();
-
- if (mx31_revision() >= IMX_CHIP_REVISION_2_0) {
- reg = __raw_readl(MXC_CCM_PMCR1);
- /* No PLL restart on DVFS switch; enable auto EMI handshake */
- reg |= MXC_CCM_PMCR1_PLLRDIS | MXC_CCM_PMCR1_EMIRQ_EN;
- __raw_writel(reg, MXC_CCM_PMCR1);
- }
-
- mxc_timer_init(&ipg_clk, MX31_IO_ADDRESS(MX31_GPT1_BASE_ADDR),
- MX31_INT_GPT);
-
- return 0;
-}
-
diff --git a/arch/arm/mach-mx3/clock-imx35.c b/arch/arm/mach-mx3/clock-imx35.c
deleted file mode 100644
index 448a038..0000000
--- a/arch/arm/mach-mx3/clock-imx35.c
+++ /dev/null
@@ -1,550 +0,0 @@
-/*
- * Copyright (C) 2009 by Sascha Hauer, Pengutronix
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/list.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/clkdev.h>
-
-#include <mach/clock.h>
-#include <mach/hardware.h>
-#include <mach/common.h>
-
-#define CCM_BASE MX35_IO_ADDRESS(MX35_CCM_BASE_ADDR)
-
-#define CCM_CCMR 0x00
-#define CCM_PDR0 0x04
-#define CCM_PDR1 0x08
-#define CCM_PDR2 0x0C
-#define CCM_PDR3 0x10
-#define CCM_PDR4 0x14
-#define CCM_RCSR 0x18
-#define CCM_MPCTL 0x1C
-#define CCM_PPCTL 0x20
-#define CCM_ACMR 0x24
-#define CCM_COSR 0x28
-#define CCM_CGR0 0x2C
-#define CCM_CGR1 0x30
-#define CCM_CGR2 0x34
-#define CCM_CGR3 0x38
-
-#ifdef HAVE_SET_RATE_SUPPORT
-static void calc_dividers(u32 div, u32 *pre, u32 *post, u32 maxpost)
-{
- u32 min_pre, temp_pre, old_err, err;
-
- min_pre = (div - 1) / maxpost + 1;
- old_err = 8;
-
- for (temp_pre = 8; temp_pre >= min_pre; temp_pre--) {
- if (div > (temp_pre * maxpost))
- break;
-
- if (div < (temp_pre * temp_pre))
- continue;
-
- err = div % temp_pre;
-
- if (err == 0) {
- *pre = temp_pre;
- break;
- }
-
- err = temp_pre - err;
-
- if (err < old_err) {
- old_err = err;
- *pre = temp_pre;
- }
- }
-
- *post = (div + *pre - 1) / *pre;
-}
-
-/* get the best values for a 3-bit divider combined with a 6-bit divider */
-static void calc_dividers_3_6(u32 div, u32 *pre, u32 *post)
-{
- if (div >= 512) {
- *pre = 8;
- *post = 64;
- } else if (div >= 64) {
- calc_dividers(div, pre, post, 64);
- } else if (div <= 8) {
- *pre = div;
- *post = 1;
- } else {
- *pre = 1;
- *post = div;
- }
-}
-
-/* get the best values for two cascaded 3-bit dividers */
-static void calc_dividers_3_3(u32 div, u32 *pre, u32 *post)
-{
- if (div >= 64) {
- *pre = *post = 8;
- } else if (div > 8) {
- calc_dividers(div, pre, post, 8);
- } else {
- *pre = 1;
- *post = div;
- }
-}
-#endif
-
-static unsigned long get_rate_mpll(void)
-{
- ulong mpctl = __raw_readl(CCM_BASE + CCM_MPCTL);
-
- return mxc_decode_pll(mpctl, 24000000);
-}
-
-static unsigned long get_rate_ppll(void)
-{
- ulong ppctl = __raw_readl(CCM_BASE + CCM_PPCTL);
-
- return mxc_decode_pll(ppctl, 24000000);
-}
-
-struct arm_ahb_div {
- unsigned char arm, ahb, sel;
-};
-
-static struct arm_ahb_div clk_consumer[] = {
- { .arm = 1, .ahb = 4, .sel = 0},
- { .arm = 1, .ahb = 3, .sel = 1},
- { .arm = 2, .ahb = 2, .sel = 0},
- { .arm = 0, .ahb = 0, .sel = 0},
- { .arm = 0, .ahb = 0, .sel = 0},
- { .arm = 0, .ahb = 0, .sel = 0},
- { .arm = 4, .ahb = 1, .sel = 0},
- { .arm = 1, .ahb = 5, .sel = 0},
- { .arm = 1, .ahb = 8, .sel = 0},
- { .arm = 1, .ahb = 6, .sel = 1},
- { .arm = 2, .ahb = 4, .sel = 0},
- { .arm = 0, .ahb = 0, .sel = 0},
- { .arm = 0, .ahb = 0, .sel = 0},
- { .arm = 0, .ahb = 0, .sel = 0},
- { .arm = 4, .ahb = 2, .sel = 0},
- { .arm = 0, .ahb = 0, .sel = 0},
-};
-
-static unsigned long get_rate_arm(void)
-{
- unsigned long pdr0 = __raw_readl(CCM_BASE + CCM_PDR0);
- struct arm_ahb_div *aad;
- unsigned long fref = get_rate_mpll();
-
- aad = &clk_consumer[(pdr0 >> 16) & 0xf];
- if (aad->sel)
- fref = fref * 3 / 4;
-
- return fref / aad->arm;
-}
-
-static unsigned long get_rate_ahb(struct clk *clk)
-{
- unsigned long pdr0 = __raw_readl(CCM_BASE + CCM_PDR0);
- struct arm_ahb_div *aad;
- unsigned long fref = get_rate_arm();
-
- aad = &clk_consumer[(pdr0 >> 16) & 0xf];
-
- return fref / aad->ahb;
-}
-
-static unsigned long get_rate_ipg(struct clk *clk)
-{
- return get_rate_ahb(NULL) >> 1;
-}
-
-static unsigned long get_rate_uart(struct clk *clk)
-{
- unsigned long pdr3 = __raw_readl(CCM_BASE + CCM_PDR3);
- unsigned long pdr4 = __raw_readl(CCM_BASE + CCM_PDR4);
- unsigned long div = ((pdr4 >> 10) & 0x3f) + 1;
-
- if (pdr3 & (1 << 14))
- return get_rate_arm() / div;
- else
- return get_rate_ppll() / div;
-}
-
-static unsigned long get_rate_sdhc(struct clk *clk)
-{
- unsigned long pdr3 = __raw_readl(CCM_BASE + CCM_PDR3);
- unsigned long div, rate;
-
- if (pdr3 & (1 << 6))
- rate = get_rate_arm();
- else
- rate = get_rate_ppll();
-
- switch (clk->id) {
- default:
- case 0:
- div = pdr3 & 0x3f;
- break;
- case 1:
- div = (pdr3 >> 8) & 0x3f;
- break;
- case 2:
- div = (pdr3 >> 16) & 0x3f;
- break;
- }
-
- return rate / (div + 1);
-}
-
-static unsigned long get_rate_mshc(struct clk *clk)
-{
- unsigned long pdr1 = __raw_readl(CCM_BASE + CCM_PDR1);
- unsigned long div1, div2, rate;
-
- if (pdr1 & (1 << 7))
- rate = get_rate_arm();
- else
- rate = get_rate_ppll();
-
- div1 = (pdr1 >> 29) & 0x7;
- div2 = (pdr1 >> 22) & 0x3f;
-
- return rate / ((div1 + 1) * (div2 + 1));
-}
-
-static unsigned long get_rate_ssi(struct clk *clk)
-{
- unsigned long pdr2 = __raw_readl(CCM_BASE + CCM_PDR2);
- unsigned long div1, div2, rate;
-
- if (pdr2 & (1 << 6))
- rate = get_rate_arm();
- else
- rate = get_rate_ppll();
-
- switch (clk->id) {
- default:
- case 0:
- div1 = pdr2 & 0x3f;
- div2 = (pdr2 >> 24) & 0x7;
- break;
- case 1:
- div1 = (pdr2 >> 8) & 0x3f;
- div2 = (pdr2 >> 27) & 0x7;
- break;
- }
-
- return rate / ((div1 + 1) * (div2 + 1));
-}
-
-static unsigned long get_rate_csi(struct clk *clk)
-{
- unsigned long pdr2 = __raw_readl(CCM_BASE + CCM_PDR2);
- unsigned long rate;
-
- if (pdr2 & (1 << 7))
- rate = get_rate_arm();
- else
- rate = get_rate_ppll();
-
- return rate / (((pdr2 >> 16) & 0x3f) + 1);
-}
-
-static unsigned long get_rate_otg(struct clk *clk)
-{
- unsigned long pdr4 = __raw_readl(CCM_BASE + CCM_PDR4);
- unsigned long rate;
-
- if (pdr4 & (1 << 9))
- rate = get_rate_arm();
- else
- rate = get_rate_ppll();
-
- return rate / (((pdr4 >> 22) & 0x3f) + 1);
-}
-
-static unsigned long get_rate_ipg_per(struct clk *clk)
-{
- unsigned long pdr0 = __raw_readl(CCM_BASE + CCM_PDR0);
- unsigned long pdr4 = __raw_readl(CCM_BASE + CCM_PDR4);
- unsigned long div;
-
- if (pdr0 & (1 << 26)) {
- div = (pdr4 >> 16) & 0x3f;
- return get_rate_arm() / (div + 1);
- } else {
- div = (pdr0 >> 12) & 0x7;
- return get_rate_ahb(NULL) / (div + 1);
- }
-}
-
-static unsigned long get_rate_hsp(struct clk *clk)
-{
- unsigned long hsp_podf = (__raw_readl(CCM_BASE + CCM_PDR0) >> 20) & 0x03;
- unsigned long fref = get_rate_mpll();
-
- if (fref > 400 * 1000 * 1000) {
- switch (hsp_podf) {
- case 0:
- return fref >> 2;
- case 1:
- return fref >> 3;
- case 2:
- return fref / 3;
- }
- } else {
- switch (hsp_podf) {
- case 0:
- case 2:
- return fref / 3;
- case 1:
- return fref / 6;
- }
- }
-
- return 0;
-}
-
-static int clk_cgr_enable(struct clk *clk)
-{
- u32 reg;
-
- reg = __raw_readl(clk->enable_reg);
- reg |= 3 << clk->enable_shift;
- __raw_writel(reg, clk->enable_reg);
-
- return 0;
-}
-
-static void clk_cgr_disable(struct clk *clk)
-{
- u32 reg;
-
- reg = __raw_readl(clk->enable_reg);
- reg &= ~(3 << clk->enable_shift);
- __raw_writel(reg, clk->enable_reg);
-}
-
-#define DEFINE_CLOCK(name, i, er, es, gr, sr) \
- static struct clk name = { \
- .id = i, \
- .enable_reg = CCM_BASE + er, \
- .enable_shift = es, \
- .get_rate = gr, \
- .set_rate = sr, \
- .enable = clk_cgr_enable, \
- .disable = clk_cgr_disable, \
- }
-
-DEFINE_CLOCK(asrc_clk, 0, CCM_CGR0, 0, NULL, NULL);
-DEFINE_CLOCK(ata_clk, 0, CCM_CGR0, 2, get_rate_ipg, NULL);
-/* DEFINE_CLOCK(audmux_clk, 0, CCM_CGR0, 4, NULL, NULL); */
-DEFINE_CLOCK(can1_clk, 0, CCM_CGR0, 6, get_rate_ipg, NULL);
-DEFINE_CLOCK(can2_clk, 1, CCM_CGR0, 8, get_rate_ipg, NULL);
-DEFINE_CLOCK(cspi1_clk, 0, CCM_CGR0, 10, get_rate_ipg, NULL);
-DEFINE_CLOCK(cspi2_clk, 1, CCM_CGR0, 12, get_rate_ipg, NULL);
-DEFINE_CLOCK(ect_clk, 0, CCM_CGR0, 14, get_rate_ipg, NULL);
-DEFINE_CLOCK(edio_clk, 0, CCM_CGR0, 16, NULL, NULL);
-DEFINE_CLOCK(emi_clk, 0, CCM_CGR0, 18, get_rate_ipg, NULL);
-DEFINE_CLOCK(epit1_clk, 0, CCM_CGR0, 20, get_rate_ipg, NULL);
-DEFINE_CLOCK(epit2_clk, 1, CCM_CGR0, 22, get_rate_ipg, NULL);
-DEFINE_CLOCK(esai_clk, 0, CCM_CGR0, 24, NULL, NULL);
-DEFINE_CLOCK(esdhc1_clk, 0, CCM_CGR0, 26, get_rate_sdhc, NULL);
-DEFINE_CLOCK(esdhc2_clk, 1, CCM_CGR0, 28, get_rate_sdhc, NULL);
-DEFINE_CLOCK(esdhc3_clk, 2, CCM_CGR0, 30, get_rate_sdhc, NULL);
-
-DEFINE_CLOCK(fec_clk, 0, CCM_CGR1, 0, get_rate_ipg, NULL);
-DEFINE_CLOCK(gpio1_clk, 0, CCM_CGR1, 2, NULL, NULL);
-DEFINE_CLOCK(gpio2_clk, 1, CCM_CGR1, 4, NULL, NULL);
-DEFINE_CLOCK(gpio3_clk, 2, CCM_CGR1, 6, NULL, NULL);
-DEFINE_CLOCK(gpt_clk, 0, CCM_CGR1, 8, get_rate_ipg, NULL);
-DEFINE_CLOCK(i2c1_clk, 0, CCM_CGR1, 10, get_rate_ipg_per, NULL);
-DEFINE_CLOCK(i2c2_clk, 1, CCM_CGR1, 12, get_rate_ipg_per, NULL);
-DEFINE_CLOCK(i2c3_clk, 2, CCM_CGR1, 14, get_rate_ipg_per, NULL);
-DEFINE_CLOCK(iomuxc_clk, 0, CCM_CGR1, 16, NULL, NULL);
-DEFINE_CLOCK(ipu_clk, 0, CCM_CGR1, 18, get_rate_hsp, NULL);
-DEFINE_CLOCK(kpp_clk, 0, CCM_CGR1, 20, get_rate_ipg, NULL);
-DEFINE_CLOCK(mlb_clk, 0, CCM_CGR1, 22, get_rate_ahb, NULL);
-DEFINE_CLOCK(mshc_clk, 0, CCM_CGR1, 24, get_rate_mshc, NULL);
-DEFINE_CLOCK(owire_clk, 0, CCM_CGR1, 26, get_rate_ipg_per, NULL);
-DEFINE_CLOCK(pwm_clk, 0, CCM_CGR1, 28, get_rate_ipg_per, NULL);
-DEFINE_CLOCK(rngc_clk, 0, CCM_CGR1, 30, get_rate_ipg, NULL);
-
-DEFINE_CLOCK(rtc_clk, 0, CCM_CGR2, 0, get_rate_ipg, NULL);
-DEFINE_CLOCK(rtic_clk, 0, CCM_CGR2, 2, get_rate_ahb, NULL);
-DEFINE_CLOCK(scc_clk, 0, CCM_CGR2, 4, get_rate_ipg, NULL);
-DEFINE_CLOCK(sdma_clk, 0, CCM_CGR2, 6, NULL, NULL);
-DEFINE_CLOCK(spba_clk, 0, CCM_CGR2, 8, get_rate_ipg, NULL);
-DEFINE_CLOCK(spdif_clk, 0, CCM_CGR2, 10, NULL, NULL);
-DEFINE_CLOCK(ssi1_clk, 0, CCM_CGR2, 12, get_rate_ssi, NULL);
-DEFINE_CLOCK(ssi2_clk, 1, CCM_CGR2, 14, get_rate_ssi, NULL);
-DEFINE_CLOCK(uart1_clk, 0, CCM_CGR2, 16, get_rate_uart, NULL);
-DEFINE_CLOCK(uart2_clk, 1, CCM_CGR2, 18, get_rate_uart, NULL);
-DEFINE_CLOCK(uart3_clk, 2, CCM_CGR2, 20, get_rate_uart, NULL);
-DEFINE_CLOCK(usbotg_clk, 0, CCM_CGR2, 22, get_rate_otg, NULL);
-DEFINE_CLOCK(wdog_clk, 0, CCM_CGR2, 24, NULL, NULL);
-DEFINE_CLOCK(max_clk, 0, CCM_CGR2, 26, NULL, NULL);
-DEFINE_CLOCK(audmux_clk, 0, CCM_CGR2, 30, NULL, NULL);
-
-DEFINE_CLOCK(csi_clk, 0, CCM_CGR3, 0, get_rate_csi, NULL);
-DEFINE_CLOCK(iim_clk, 0, CCM_CGR3, 2, NULL, NULL);
-DEFINE_CLOCK(gpu2d_clk, 0, CCM_CGR3, 4, NULL, NULL);
-
-DEFINE_CLOCK(usbahb_clk, 0, 0, 0, get_rate_ahb, NULL);
-
-static int clk_dummy_enable(struct clk *clk)
-{
- return 0;
-}
-
-static void clk_dummy_disable(struct clk *clk)
-{
-}
-
-static unsigned long get_rate_nfc(struct clk *clk)
-{
- unsigned long div1;
-
- div1 = (__raw_readl(CCM_BASE + CCM_PDR4) >> 28) + 1;
-
- return get_rate_ahb(NULL) / div1;
-}
-
-/* NAND Controller: It seems it can't be disabled */
-static struct clk nfc_clk = {
- .id = 0,
- .enable_reg = 0,
- .enable_shift = 0,
- .get_rate = get_rate_nfc,
- .set_rate = NULL, /* set_rate_nfc, */
- .enable = clk_dummy_enable,
- .disable = clk_dummy_disable
-};
-
-#define _REGISTER_CLOCK(d, n, c) \
- { \
- .dev_id = d, \
- .con_id = n, \
- .clk = &c, \
- },
-
-static struct clk_lookup lookups[] = {
- _REGISTER_CLOCK(NULL, "asrc", asrc_clk)
- _REGISTER_CLOCK(NULL, "ata", ata_clk)
- _REGISTER_CLOCK("flexcan.0", NULL, can1_clk)
- _REGISTER_CLOCK("flexcan.1", NULL, can2_clk)
- _REGISTER_CLOCK("imx35-cspi.0", NULL, cspi1_clk)
- _REGISTER_CLOCK("imx35-cspi.1", NULL, cspi2_clk)
- _REGISTER_CLOCK(NULL, "ect", ect_clk)
- _REGISTER_CLOCK(NULL, "edio", edio_clk)
- _REGISTER_CLOCK(NULL, "emi", emi_clk)
- _REGISTER_CLOCK("imx-epit.0", NULL, epit1_clk)
- _REGISTER_CLOCK("imx-epit.1", NULL, epit2_clk)
- _REGISTER_CLOCK(NULL, "esai", esai_clk)
- _REGISTER_CLOCK("sdhci-esdhc-imx.0", NULL, esdhc1_clk)
- _REGISTER_CLOCK("sdhci-esdhc-imx.1", NULL, esdhc2_clk)
- _REGISTER_CLOCK("sdhci-esdhc-imx.2", NULL, esdhc3_clk)
- _REGISTER_CLOCK("fec.0", NULL, fec_clk)
- _REGISTER_CLOCK(NULL, "gpio", gpio1_clk)
- _REGISTER_CLOCK(NULL, "gpio", gpio2_clk)
- _REGISTER_CLOCK(NULL, "gpio", gpio3_clk)
- _REGISTER_CLOCK("gpt.0", NULL, gpt_clk)
- _REGISTER_CLOCK("imx-i2c.0", NULL, i2c1_clk)
- _REGISTER_CLOCK("imx-i2c.1", NULL, i2c2_clk)
- _REGISTER_CLOCK("imx-i2c.2", NULL, i2c3_clk)
- _REGISTER_CLOCK(NULL, "iomuxc", iomuxc_clk)
- _REGISTER_CLOCK("ipu-core", NULL, ipu_clk)
- _REGISTER_CLOCK("mx3_sdc_fb", NULL, ipu_clk)
- _REGISTER_CLOCK(NULL, "kpp", kpp_clk)
- _REGISTER_CLOCK(NULL, "mlb", mlb_clk)
- _REGISTER_CLOCK(NULL, "mshc", mshc_clk)
- _REGISTER_CLOCK("mxc_w1", NULL, owire_clk)
- _REGISTER_CLOCK(NULL, "pwm", pwm_clk)
- _REGISTER_CLOCK(NULL, "rngc", rngc_clk)
- _REGISTER_CLOCK(NULL, "rtc", rtc_clk)
- _REGISTER_CLOCK(NULL, "rtic", rtic_clk)
- _REGISTER_CLOCK(NULL, "scc", scc_clk)
- _REGISTER_CLOCK("imx-sdma", NULL, sdma_clk)
- _REGISTER_CLOCK(NULL, "spba", spba_clk)
- _REGISTER_CLOCK(NULL, "spdif", spdif_clk)
- _REGISTER_CLOCK("imx-ssi.0", NULL, ssi1_clk)
- _REGISTER_CLOCK("imx-ssi.1", NULL, ssi2_clk)
- _REGISTER_CLOCK("imx-uart.0", NULL, uart1_clk)
- _REGISTER_CLOCK("imx-uart.1", NULL, uart2_clk)
- _REGISTER_CLOCK("imx-uart.2", NULL, uart3_clk)
- _REGISTER_CLOCK("mxc-ehci.0", "usb", usbotg_clk)
- _REGISTER_CLOCK("mxc-ehci.1", "usb", usbotg_clk)
- _REGISTER_CLOCK("mxc-ehci.2", "usb", usbotg_clk)
- _REGISTER_CLOCK("fsl-usb2-udc", "usb", usbotg_clk)
- _REGISTER_CLOCK("fsl-usb2-udc", "usb_ahb", usbahb_clk)
- _REGISTER_CLOCK("imx2-wdt.0", NULL, wdog_clk)
- _REGISTER_CLOCK(NULL, "max", max_clk)
- _REGISTER_CLOCK(NULL, "audmux", audmux_clk)
- _REGISTER_CLOCK(NULL, "csi", csi_clk)
- _REGISTER_CLOCK(NULL, "iim", iim_clk)
- _REGISTER_CLOCK(NULL, "gpu2d", gpu2d_clk)
- _REGISTER_CLOCK("mxc_nand.0", NULL, nfc_clk)
-};
-
-int __init mx35_clocks_init()
-{
- unsigned int cgr2 = 3 << 26, cgr3 = 0;
-
-#if defined(CONFIG_DEBUG_LL) && !defined(CONFIG_DEBUG_ICEDCC)
- cgr2 |= 3 << 16;
-#endif
-
- clkdev_add_table(lookups, ARRAY_SIZE(lookups));
-
- /* Turn off all clocks except the ones we need to survive, namely:
- * EMI, GPIO1/2/3, GPT, IOMUX, MAX and eventually uart
- */
- __raw_writel((3 << 18), CCM_BASE + CCM_CGR0);
- __raw_writel((3 << 2) | (3 << 4) | (3 << 6) | (3 << 8) | (3 << 16),
- CCM_BASE + CCM_CGR1);
-
- /*
- * Check if we came up in internal boot mode. If yes, we need some
- * extra clocks turned on, otherwise the MX35 boot ROM code will
- * hang after a watchdog reset.
- */
- if (!(__raw_readl(CCM_BASE + CCM_RCSR) & (3 << 10))) {
- /* Additionally turn on UART1, SCC, and IIM clocks */
- cgr2 |= 3 << 16 | 3 << 4;
- cgr3 |= 3 << 2;
- }
-
- __raw_writel(cgr2, CCM_BASE + CCM_CGR2);
- __raw_writel(cgr3, CCM_BASE + CCM_CGR3);
-
- clk_enable(&iim_clk);
- mx35_read_cpu_rev();
-
-#ifdef CONFIG_MXC_USE_EPIT
- epit_timer_init(&epit1_clk,
- MX35_IO_ADDRESS(MX35_EPIT1_BASE_ADDR), MX35_INT_EPIT1);
-#else
- mxc_timer_init(&gpt_clk,
- MX35_IO_ADDRESS(MX35_GPT1_BASE_ADDR), MX35_INT_GPT);
-#endif
-
- return 0;
-}
-
diff --git a/arch/arm/mach-mx3/cpu.c b/arch/arm/mach-mx3/cpu.c
deleted file mode 100644
index d1d3395..0000000
--- a/arch/arm/mach-mx3/cpu.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * MX3 CPU type detection
- *
- * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- */
-
-#include <linux/module.h>
-#include <linux/io.h>
-#include <mach/hardware.h>
-#include <mach/iim.h>
-
-unsigned int mx31_cpu_rev;
-EXPORT_SYMBOL(mx31_cpu_rev);
-
-struct mx3_cpu_type {
- u8 srev;
- const char *name;
- const char *v;
- unsigned int rev;
-};
-
-static struct mx3_cpu_type mx31_cpu_type[] __initdata = {
- { .srev = 0x00, .name = "i.MX31(L)", .v = "1.0", .rev = IMX_CHIP_REVISION_1_0 },
- { .srev = 0x10, .name = "i.MX31", .v = "1.1", .rev = IMX_CHIP_REVISION_1_1 },
- { .srev = 0x11, .name = "i.MX31L", .v = "1.1", .rev = IMX_CHIP_REVISION_1_1 },
- { .srev = 0x12, .name = "i.MX31", .v = "1.15", .rev = IMX_CHIP_REVISION_1_1 },
- { .srev = 0x13, .name = "i.MX31L", .v = "1.15", .rev = IMX_CHIP_REVISION_1_1 },
- { .srev = 0x14, .name = "i.MX31", .v = "1.2", .rev = IMX_CHIP_REVISION_1_2 },
- { .srev = 0x15, .name = "i.MX31L", .v = "1.2", .rev = IMX_CHIP_REVISION_1_2 },
- { .srev = 0x28, .name = "i.MX31", .v = "2.0", .rev = IMX_CHIP_REVISION_2_0 },
- { .srev = 0x29, .name = "i.MX31L", .v = "2.0", .rev = IMX_CHIP_REVISION_2_0 },
-};
-
-void __init mx31_read_cpu_rev(void)
-{
- u32 i, srev;
-
- /* read SREV register from IIM module */
- srev = __raw_readl(MX31_IO_ADDRESS(MX31_IIM_BASE_ADDR + MXC_IIMSREV));
-
- for (i = 0; i < ARRAY_SIZE(mx31_cpu_type); i++)
- if (srev == mx31_cpu_type[i].srev) {
- printk(KERN_INFO
- "CPU identified as %s, silicon rev %s\n",
- mx31_cpu_type[i].name, mx31_cpu_type[i].v);
-
- mx31_cpu_rev = mx31_cpu_type[i].rev;
- return;
- }
-
- mx31_cpu_rev = IMX_CHIP_REVISION_UNKNOWN;
-
- printk(KERN_WARNING "Unknown CPU identifier. srev = %02x\n", srev);
-}
-
-unsigned int mx35_cpu_rev;
-EXPORT_SYMBOL(mx35_cpu_rev);
-
-void __init mx35_read_cpu_rev(void)
-{
- u32 rev;
- char *srev;
-
- rev = __raw_readl(MX35_IO_ADDRESS(MX35_IIM_BASE_ADDR + MXC_IIMSREV));
- switch (rev) {
- case 0x00:
- mx35_cpu_rev = IMX_CHIP_REVISION_1_0;
- srev = "1.0";
- break;
- case 0x10:
- mx35_cpu_rev = IMX_CHIP_REVISION_2_0;
- srev = "2.0";
- break;
- case 0x11:
- mx35_cpu_rev = IMX_CHIP_REVISION_2_1;
- srev = "2.1";
- break;
- default:
- mx35_cpu_rev = IMX_CHIP_REVISION_UNKNOWN;
- srev = "unknown";
- }
-
- printk(KERN_INFO "CPU identified as i.MX35, silicon rev %s\n", srev);
-}
diff --git a/arch/arm/mach-mx3/devices-imx31.h b/arch/arm/mach-mx3/devices-imx31.h
deleted file mode 100644
index 40f4e84..0000000
--- a/arch/arm/mach-mx3/devices-imx31.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <mach/mx31.h>
-#include <mach/devices-common.h>
-
-extern const struct imx_fsl_usb2_udc_data imx31_fsl_usb2_udc_data __initconst;
-#define imx31_add_fsl_usb2_udc(pdata) \
- imx_add_fsl_usb2_udc(&imx31_fsl_usb2_udc_data, pdata)
-
-extern const struct imx_imx2_wdt_data imx31_imx2_wdt_data __initconst;
-#define imx31_add_imx2_wdt(pdata) \
- imx_add_imx2_wdt(&imx31_imx2_wdt_data)
-
-extern const struct imx_imx_i2c_data imx31_imx_i2c_data[] __initconst;
-#define imx31_add_imx_i2c(id, pdata) \
- imx_add_imx_i2c(&imx31_imx_i2c_data[id], pdata)
-#define imx31_add_imx_i2c0(pdata) imx31_add_imx_i2c(0, pdata)
-#define imx31_add_imx_i2c1(pdata) imx31_add_imx_i2c(1, pdata)
-#define imx31_add_imx_i2c2(pdata) imx31_add_imx_i2c(2, pdata)
-
-extern const struct imx_imx_keypad_data imx31_imx_keypad_data __initconst;
-#define imx31_add_imx_keypad(pdata) \
- imx_add_imx_keypad(&imx31_imx_keypad_data, pdata)
-
-extern const struct imx_imx_ssi_data imx31_imx_ssi_data[] __initconst;
-#define imx31_add_imx_ssi(id, pdata) \
- imx_add_imx_ssi(&imx31_imx_ssi_data[id], pdata)
-
-extern const struct imx_imx_uart_1irq_data imx31_imx_uart_data[] __initconst;
-#define imx31_add_imx_uart(id, pdata) \
- imx_add_imx_uart_1irq(&imx31_imx_uart_data[id], pdata)
-#define imx31_add_imx_uart0(pdata) imx31_add_imx_uart(0, pdata)
-#define imx31_add_imx_uart1(pdata) imx31_add_imx_uart(1, pdata)
-#define imx31_add_imx_uart2(pdata) imx31_add_imx_uart(2, pdata)
-#define imx31_add_imx_uart3(pdata) imx31_add_imx_uart(3, pdata)
-#define imx31_add_imx_uart4(pdata) imx31_add_imx_uart(4, pdata)
-
-extern const struct imx_mxc_ehci_data imx31_mxc_ehci_otg_data __initconst;
-#define imx31_add_mxc_ehci_otg(pdata) \
- imx_add_mxc_ehci(&imx31_mxc_ehci_otg_data, pdata)
-extern const struct imx_mxc_ehci_data imx31_mxc_ehci_hs_data[] __initconst;
-#define imx31_add_mxc_ehci_hs(id, pdata) \
- imx_add_mxc_ehci(&imx31_mxc_ehci_hs_data[id - 1], pdata)
-
-extern const struct imx_mxc_mmc_data imx31_mxc_mmc_data[] __initconst;
-#define imx31_add_mxc_mmc(id, pdata) \
- imx_add_mxc_mmc(&imx31_mxc_mmc_data[id], pdata)
-
-extern const struct imx_mxc_nand_data imx31_mxc_nand_data __initconst;
-#define imx31_add_mxc_nand(pdata) \
- imx_add_mxc_nand(&imx31_mxc_nand_data, pdata)
-
-extern const struct imx_mxc_w1_data imx31_mxc_w1_data __initconst;
-#define imx31_add_mxc_w1(pdata) \
- imx_add_mxc_w1(&imx31_mxc_w1_data)
-
-extern const struct imx_spi_imx_data imx31_cspi_data[] __initconst;
-#define imx31_add_cspi(id, pdata) \
- imx_add_spi_imx(&imx31_cspi_data[id], pdata)
-#define imx31_add_spi_imx0(pdata) imx31_add_cspi(0, pdata)
-#define imx31_add_spi_imx1(pdata) imx31_add_cspi(1, pdata)
-#define imx31_add_spi_imx2(pdata) imx31_add_cspi(2, pdata)
diff --git a/arch/arm/mach-mx3/devices-imx35.h b/arch/arm/mach-mx3/devices-imx35.h
deleted file mode 100644
index d545d86..0000000
--- a/arch/arm/mach-mx3/devices-imx35.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * Copyright (C) 2010 Pengutronix
- * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License version 2 as published by the
- * Free Software Foundation.
- */
-#include <mach/mx35.h>
-#include <mach/devices-common.h>
-
-extern const struct imx_fec_data imx35_fec_data __initconst;
-#define imx35_add_fec(pdata) \
- imx_add_fec(&imx35_fec_data, pdata)
-
-extern const struct imx_fsl_usb2_udc_data imx35_fsl_usb2_udc_data __initconst;
-#define imx35_add_fsl_usb2_udc(pdata) \
- imx_add_fsl_usb2_udc(&imx35_fsl_usb2_udc_data, pdata)
-
-extern const struct imx_flexcan_data imx35_flexcan_data[] __initconst;
-#define imx35_add_flexcan(id, pdata) \
- imx_add_flexcan(&imx35_flexcan_data[id], pdata)
-#define imx35_add_flexcan0(pdata) imx35_add_flexcan(0, pdata)
-#define imx35_add_flexcan1(pdata) imx35_add_flexcan(1, pdata)
-
-extern const struct imx_imx2_wdt_data imx35_imx2_wdt_data __initconst;
-#define imx35_add_imx2_wdt(pdata) \
- imx_add_imx2_wdt(&imx35_imx2_wdt_data)
-
-extern const struct imx_imx_i2c_data imx35_imx_i2c_data[] __initconst;
-#define imx35_add_imx_i2c(id, pdata) \
- imx_add_imx_i2c(&imx35_imx_i2c_data[id], pdata)
-#define imx35_add_imx_i2c0(pdata) imx35_add_imx_i2c(0, pdata)
-#define imx35_add_imx_i2c1(pdata) imx35_add_imx_i2c(1, pdata)
-#define imx35_add_imx_i2c2(pdata) imx35_add_imx_i2c(2, pdata)
-
-extern const struct imx_imx_keypad_data imx35_imx_keypad_data __initconst;
-#define imx35_add_imx_keypad(pdata) \
- imx_add_imx_keypad(&imx35_imx_keypad_data, pdata)
-
-extern const struct imx_imx_ssi_data imx35_imx_ssi_data[] __initconst;
-#define imx35_add_imx_ssi(id, pdata) \
- imx_add_imx_ssi(&imx35_imx_ssi_data[id], pdata)
-
-extern const struct imx_imx_uart_1irq_data imx35_imx_uart_data[] __initconst;
-#define imx35_add_imx_uart(id, pdata) \
- imx_add_imx_uart_1irq(&imx35_imx_uart_data[id], pdata)
-#define imx35_add_imx_uart0(pdata) imx35_add_imx_uart(0, pdata)
-#define imx35_add_imx_uart1(pdata) imx35_add_imx_uart(1, pdata)
-#define imx35_add_imx_uart2(pdata) imx35_add_imx_uart(2, pdata)
-
-extern const struct imx_mxc_ehci_data imx35_mxc_ehci_otg_data __initconst;
-#define imx35_add_mxc_ehci_otg(pdata) \
- imx_add_mxc_ehci(&imx35_mxc_ehci_otg_data, pdata)
-extern const struct imx_mxc_ehci_data imx35_mxc_ehci_hs_data __initconst;
-#define imx35_add_mxc_ehci_hs(pdata) \
- imx_add_mxc_ehci(&imx35_mxc_ehci_hs_data, pdata)
-
-extern const struct imx_mxc_nand_data imx35_mxc_nand_data __initconst;
-#define imx35_add_mxc_nand(pdata) \
- imx_add_mxc_nand(&imx35_mxc_nand_data, pdata)
-
-extern const struct imx_mxc_w1_data imx35_mxc_w1_data __initconst;
-#define imx35_add_mxc_w1(pdata) \
- imx_add_mxc_w1(&imx35_mxc_w1_data)
-
-extern const struct imx_sdhci_esdhc_imx_data
-imx35_sdhci_esdhc_imx_data[] __initconst;
-#define imx35_add_sdhci_esdhc_imx(id, pdata) \
- imx_add_sdhci_esdhc_imx(&imx35_sdhci_esdhc_imx_data[id], pdata)
-
-extern const struct imx_spi_imx_data imx35_cspi_data[] __initconst;
-#define imx35_add_cspi(id, pdata) \
- imx_add_spi_imx(&imx35_cspi_data[id], pdata)
-#define imx35_add_spi_imx0(pdata) imx35_add_cspi(0, pdata)
-#define imx35_add_spi_imx1(pdata) imx35_add_cspi(1, pdata)
diff --git a/arch/arm/mach-mx3/devices.c b/arch/arm/mach-mx3/devices.c
deleted file mode 100644
index b6672db..0000000
--- a/arch/arm/mach-mx3/devices.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor,
- * Boston, MA 02110-1301, USA.
- */
-
-#include <linux/dma-mapping.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/serial.h>
-#include <linux/gpio.h>
-#include <mach/hardware.h>
-#include <mach/irqs.h>
-#include <mach/common.h>
-#include <mach/mx3_camera.h>
-
-#include "devices.h"
-
-/* i.MX31 Image Processing Unit */
-
-/* The resource order is important! */
-static struct resource mx3_ipu_rsrc[] = {
- {
- .start = MX3x_IPU_CTRL_BASE_ADDR,
- .end = MX3x_IPU_CTRL_BASE_ADDR + 0x5F,
- .flags = IORESOURCE_MEM,
- }, {
- .start = MX3x_IPU_CTRL_BASE_ADDR + 0x88,
- .end = MX3x_IPU_CTRL_BASE_ADDR + 0xB3,
- .flags = IORESOURCE_MEM,
- }, {
- .start = MX3x_INT_IPU_SYN,
- .end = MX3x_INT_IPU_SYN,
- .flags = IORESOURCE_IRQ,
- }, {
- .start = MX3x_INT_IPU_ERR,
- .end = MX3x_INT_IPU_ERR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-struct platform_device mx3_ipu = {
- .name = "ipu-core",
- .id = -1,
- .num_resources = ARRAY_SIZE(mx3_ipu_rsrc),
- .resource = mx3_ipu_rsrc,
-};
-
-static struct resource fb_resources[] = {
- {
- .start = MX3x_IPU_CTRL_BASE_ADDR + 0xB4,
- .end = MX3x_IPU_CTRL_BASE_ADDR + 0x1BF,
- .flags = IORESOURCE_MEM,
- },
-};
-
-struct platform_device mx3_fb = {
- .name = "mx3_sdc_fb",
- .id = -1,
- .num_resources = ARRAY_SIZE(fb_resources),
- .resource = fb_resources,
- .dev = {
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
-};
-
-static struct resource camera_resources[] = {
- {
- .start = MX3x_IPU_CTRL_BASE_ADDR + 0x60,
- .end = MX3x_IPU_CTRL_BASE_ADDR + 0x87,
- .flags = IORESOURCE_MEM,
- },
-};
-
-struct platform_device mx3_camera = {
- .name = "mx3-camera",
- .id = 0,
- .num_resources = ARRAY_SIZE(camera_resources),
- .resource = camera_resources,
- .dev = {
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
-};
-
-static struct resource imx_rtc_resources[] = {
- {
- .start = MX31_RTC_BASE_ADDR,
- .end = MX31_RTC_BASE_ADDR + 0x3fff,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = MX31_INT_RTC,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-struct platform_device imx_rtc_device0 = {
- .name = "mxc_rtc",
- .id = -1,
- .num_resources = ARRAY_SIZE(imx_rtc_resources),
- .resource = imx_rtc_resources,
-};
diff --git a/arch/arm/mach-mx3/devices.h b/arch/arm/mach-mx3/devices.h
deleted file mode 100644
index 121962c..0000000
--- a/arch/arm/mach-mx3/devices.h
+++ /dev/null
@@ -1,4 +0,0 @@
-extern struct platform_device mx3_ipu;
-extern struct platform_device mx3_fb;
-extern struct platform_device mx3_camera;
-extern struct platform_device imx_rtc_device0;
diff --git a/arch/arm/mach-mx3/ehci-imx31.c b/arch/arm/mach-mx3/ehci-imx31.c
deleted file mode 100644
index 314a983..0000000
--- a/arch/arm/mach-mx3/ehci-imx31.c
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * for more details.
- */
-
-#include <linux/platform_device.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <mach/mxc_ehci.h>
-
-#define USBCTRL_OTGBASE_OFFSET 0x600
-
-#define MX31_OTG_SIC_SHIFT 29
-#define MX31_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT)
-#define MX31_OTG_PM_BIT (1 << 24)
-
-#define MX31_H2_SIC_SHIFT 21
-#define MX31_H2_SIC_MASK (0x3 << MX31_H2_SIC_SHIFT)
-#define MX31_H2_PM_BIT (1 << 16)
-#define MX31_H2_DT_BIT (1 << 5)
-
-#define MX31_H1_SIC_SHIFT 13
-#define MX31_H1_SIC_MASK (0x3 << MX31_H1_SIC_SHIFT)
-#define MX31_H1_PM_BIT (1 << 8)
-#define MX31_H1_DT_BIT (1 << 4)
-
-int mx31_initialize_usb_hw(int port, unsigned int flags)
-{
- unsigned int v;
-
- v = readl(MX31_IO_ADDRESS(MX31_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
-
- switch (port) {
- case 0: /* OTG port */
- v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
- v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_OTG_SIC_SHIFT;
-
- if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
- v |= MX31_OTG_PM_BIT;
-
- break;
- case 1: /* H1 port */
- v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT);
- v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H1_SIC_SHIFT;
-
- if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
- v |= MX31_H1_PM_BIT;
-
- if (!(flags & MXC_EHCI_TTL_ENABLED))
- v |= MX31_H1_DT_BIT;
-
- break;
- case 2: /* H2 port */
- v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT);
- v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H2_SIC_SHIFT;
-
- if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
- v |= MX31_H2_PM_BIT;
-
- if (!(flags & MXC_EHCI_TTL_ENABLED))
- v |= MX31_H2_DT_BIT;
-
- break;
- default:
- return -EINVAL;
- }
-
- writel(v, MX31_IO_ADDRESS(MX31_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
-
- return 0;
-}
-
diff --git a/arch/arm/mach-mx3/ehci-imx35.c b/arch/arm/mach-mx3/ehci-imx35.c
deleted file mode 100644
index 33983a4..0000000
--- a/arch/arm/mach-mx3/ehci-imx35.c
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
- * Copyright (C) 2010 Freescale Semiconductor, Inc.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
- * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
- * for more details.
- */
-
-#include <linux/platform_device.h>
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <mach/mxc_ehci.h>
-
-#define USBCTRL_OTGBASE_OFFSET 0x600
-
-#define MX35_OTG_SIC_SHIFT 29
-#define MX35_OTG_SIC_MASK (0x3 << MX35_OTG_SIC_SHIFT)
-#define MX35_OTG_PM_BIT (1 << 24)
-
-#define MX35_H1_SIC_SHIFT 21
-#define MX35_H1_SIC_MASK (0x3 << MX35_H1_SIC_SHIFT)
-#define MX35_H1_PM_BIT (1 << 8)
-#define MX35_H1_IPPUE_UP_BIT (1 << 7)
-#define MX35_H1_IPPUE_DOWN_BIT (1 << 6)
-#define MX35_H1_TLL_BIT (1 << 5)
-#define MX35_H1_USBTE_BIT (1 << 4)
-
-int mx35_initialize_usb_hw(int port, unsigned int flags)
-{
- unsigned int v;
-
- v = readl(MX35_IO_ADDRESS(MX35_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
-
- switch (port) {
- case 0: /* OTG port */
- v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT);
- v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_OTG_SIC_SHIFT;
-
- if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
- v |= MX35_OTG_PM_BIT;
-
- break;
- case 1: /* H1 port */
- v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_TLL_BIT |
- MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT | MX35_H1_IPPUE_UP_BIT);
- v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_H1_SIC_SHIFT;
-
- if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
- v |= MX35_H1_PM_BIT;
-
- if (!(flags & MXC_EHCI_TTL_ENABLED))
- v |= MX35_H1_TLL_BIT;
-
- if (flags & MXC_EHCI_INTERNAL_PHY)
- v |= MX35_H1_USBTE_BIT;
-
- if (flags & MXC_EHCI_IPPUE_DOWN)
- v |= MX35_H1_IPPUE_DOWN_BIT;
-
- if (flags & MXC_EHCI_IPPUE_UP)
- v |= MX35_H1_IPPUE_UP_BIT;
-
- break;
- default:
- return -EINVAL;
- }
-
- writel(v, MX35_IO_ADDRESS(MX35_USB_BASE_ADDR + USBCTRL_OTGBASE_OFFSET));
-
- return 0;
-}
-
diff --git a/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
deleted file mode 100644
index 2e288b3..0000000
--- a/arch/arm/mach-mx3/eukrea_mbimxsd-baseboard.c
+++ /dev/null
@@ -1,318 +0,0 @@
-/*
- * Copyright (C) 2010 Eric Benard - eric@eukrea.com
- *
- * Based on pcm970-baseboard.c which is :
- * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#include <linux/types.h>
-#include <linux/init.h>
-
-#include <linux/gpio.h>
-#include <linux/interrupt.h>
-#include <linux/leds.h>
-#include <linux/platform_device.h>
-#include <linux/gpio_keys.h>
-#include <linux/input.h>
-#include <video/platform_lcd.h>
-#include <linux/i2c.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <asm/mach/map.h>
-
-#include <mach/hardware.h>
-#include <mach/common.h>
-#include <mach/imx-uart.h>
-#include <mach/iomux-mx35.h>
-#include <mach/ipu.h>
-#include <mach/mx3fb.h>
-#include <mach/audmux.h>
-#include <mach/esdhc.h>
-
-#include "devices-imx35.h"
-#include "devices.h"
-
-static const struct fb_videomode fb_modedb[] = {
- {
- .name = "CMO-QVGA",
- .refresh = 60,
- .xres = 320,
- .yres = 240,
- .pixclock = KHZ2PICOS(6500),
- .left_margin = 68,
- .right_margin = 20,
- .upper_margin = 15,
- .lower_margin = 4,
- .hsync_len = 30,
- .vsync_len = 3,
- .sync = 0,
- .vmode = FB_VMODE_NONINTERLACED,
- .flag = 0,
- },
- {
- .name = "DVI-VGA",
- .refresh = 60,
- .xres = 640,
- .yres = 480,
- .pixclock = 32000,
- .left_margin = 100,
- .right_margin = 100,
- .upper_margin = 7,
- .lower_margin = 100,
- .hsync_len = 7,
- .vsync_len = 7,
- .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT |
- FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT,
- .vmode = FB_VMODE_NONINTERLACED,
- .flag = 0,
- },
- {
- .name = "DVI-SVGA",
- .refresh = 60,
- .xres = 800,
- .yres = 600,
- .pixclock = 25000,
- .left_margin = 75,
- .right_margin = 75,
- .upper_margin = 7,
- .lower_margin = 75,
- .hsync_len = 7,
- .vsync_len = 7,
- .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_HOR_HIGH_ACT |
- FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT,
- .vmode = FB_VMODE_NONINTERLACED,
- .flag = 0,
- },
-};
-
-static struct ipu_platform_data mx3_ipu_data = {
- .irq_base = MXC_IPU_IRQ_START,
-};
-
-static struct mx3fb_platform_data mx3fb_pdata = {
- .dma_dev = &mx3_ipu.dev,
- .name = "CMO-QVGA",
- .mode = fb_modedb,
- .num_modes = ARRAY_SIZE(fb_modedb),
-};
-
-static iomux_v3_cfg_t eukrea_mbimxsd_pads[] = {
- /* LCD */
- MX35_PAD_LD0__IPU_DISPB_DAT_0,
- MX35_PAD_LD1__IPU_DISPB_DAT_1,
- MX35_PAD_LD2__IPU_DISPB_DAT_2,
- MX35_PAD_LD3__IPU_DISPB_DAT_3,
- MX35_PAD_LD4__IPU_DISPB_DAT_4,
- MX35_PAD_LD5__IPU_DISPB_DAT_5,
- MX35_PAD_LD6__IPU_DISPB_DAT_6,
- MX35_PAD_LD7__IPU_DISPB_DAT_7,
- MX35_PAD_LD8__IPU_DISPB_DAT_8,
- MX35_PAD_LD9__IPU_DISPB_DAT_9,
- MX35_PAD_LD10__IPU_DISPB_DAT_10,
- MX35_PAD_LD11__IPU_DISPB_DAT_11,
- MX35_PAD_LD12__IPU_DISPB_DAT_12,
- MX35_PAD_LD13__IPU_DISPB_DAT_13,
- MX35_PAD_LD14__IPU_DISPB_DAT_14,
- MX35_PAD_LD15__IPU_DISPB_DAT_15,
- MX35_PAD_LD16__IPU_DISPB_DAT_16,
- MX35_PAD_LD17__IPU_DISPB_DAT_17,
- MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC,
- MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK,
- MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY,
- MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC,
- /* Backlight */
- MX35_PAD_CONTRAST__IPU_DISPB_CONTR,
- /* LCD_PWR */
- MX35_PAD_D3_CLS__GPIO1_4,
- /* LED */
- MX35_PAD_LD23__GPIO3_29,
- /* SWITCH */
- MX35_PAD_LD19__GPIO3_25,
- /* UART2 */
- MX35_PAD_CTS2__UART2_CTS,
- MX35_PAD_RTS2__UART2_RTS,
- MX35_PAD_TXD2__UART2_TXD_MUX,
- MX35_PAD_RXD2__UART2_RXD_MUX,
- /* I2S */
- MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS,
- MX35_PAD_STXD4__AUDMUX_AUD4_TXD,
- MX35_PAD_SRXD4__AUDMUX_AUD4_RXD,
- MX35_PAD_SCK4__AUDMUX_AUD4_TXC,
- /* CAN2 */
- MX35_PAD_TX5_RX0__CAN2_TXCAN,
- MX35_PAD_TX4_RX1__CAN2_RXCAN,
- /* SDCARD */
- MX35_PAD_SD1_CMD__ESDHC1_CMD,
- MX35_PAD_SD1_CLK__ESDHC1_CLK,
- MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
- MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
- MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
- MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
- /* SD1 CD */
- MX35_PAD_LD18__GPIO3_24,
-};
-
-#define GPIO_LED1 IMX_GPIO_NR(3, 29)
-#define GPIO_SWITCH1 IMX_GPIO_NR(3, 25)
-#define GPIO_LCDPWR IMX_GPIO_NR(1, 4)
-#define GPIO_SD1CD IMX_GPIO_NR(3, 24)
-
-static void eukrea_mbimxsd_lcd_power_set(struct plat_lcd_data *pd,
- unsigned int power)
-{
- if (power)
- gpio_direction_output(GPIO_LCDPWR, 1);
- else
- gpio_direction_output(GPIO_LCDPWR, 0);
-}
-
-static struct plat_lcd_data eukrea_mbimxsd_lcd_power_data = {
- .set_power = eukrea_mbimxsd_lcd_power_set,
-};
-
-static struct platform_device eukrea_mbimxsd_lcd_powerdev = {
- .name = "platform-lcd",
- .dev.platform_data = &eukrea_mbimxsd_lcd_power_data,
-};
-
-static struct gpio_led eukrea_mbimxsd_leds[] = {
- {
- .name = "led1",
- .default_trigger = "heartbeat",
- .active_low = 1,
- .gpio = GPIO_LED1,
- },
-};
-
-static struct gpio_led_platform_data eukrea_mbimxsd_led_info = {
- .leds = eukrea_mbimxsd_leds,
- .num_leds = ARRAY_SIZE(eukrea_mbimxsd_leds),
-};
-
-static struct platform_device eukrea_mbimxsd_leds_gpio = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &eukrea_mbimxsd_led_info,
- },
-};
-
-static struct gpio_keys_button eukrea_mbimxsd_gpio_buttons[] = {
- {
- .gpio = GPIO_SWITCH1,
- .code = BTN_0,
- .desc = "BP1",
- .active_low = 1,
- .wakeup = 1,
- },
-};
-
-static struct gpio_keys_platform_data eukrea_mbimxsd_button_data = {
- .buttons = eukrea_mbimxsd_gpio_buttons,
- .nbuttons = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons),
-};
-
-static struct platform_device eukrea_mbimxsd_button_device = {
- .name = "gpio-keys",
- .id = -1,
- .num_resources = 0,
- .dev = {
- .platform_data = &eukrea_mbimxsd_button_data,
- }
-};
-
-static struct platform_device *platform_devices[] __initdata = {
- &eukrea_mbimxsd_leds_gpio,
- &eukrea_mbimxsd_button_device,
- &eukrea_mbimxsd_lcd_powerdev,
-};
-
-static const struct imxuart_platform_data uart_pdata __initconst = {
- .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static struct i2c_board_info eukrea_mbimxsd_i2c_devices[] = {
- {
- I2C_BOARD_INFO("tlv320aic23", 0x1a),
- },
-};
-
-static const
-struct imx_ssi_platform_data eukrea_mbimxsd_ssi_pdata __initconst = {
- .flags = IMX_SSI_SYN | IMX_SSI_NET | IMX_SSI_USE_I2S_SLAVE,
-};
-
-static struct esdhc_platform_data sd1_pdata = {
- .cd_gpio = GPIO_SD1CD,
- .wp_gpio = -EINVAL,
-};
-
-/*
- * system init for baseboard usage. Will be called by cpuimx35 init.
- *
- * Add platform devices present on this baseboard and init
- * them from CPU side as far as required to use them later on
- */
-void __init eukrea_mbimxsd35_baseboard_init(void)
-{
- if (mxc_iomux_v3_setup_multiple_pads(eukrea_mbimxsd_pads,
- ARRAY_SIZE(eukrea_mbimxsd_pads)))
- printk(KERN_ERR "error setting mbimxsd pads !\n");
-
-#if defined(CONFIG_SND_SOC_EUKREA_TLV320)
- /* SSI unit master I2S codec connected to SSI_AUD4 */
- mxc_audmux_v2_configure_port(0,
- MXC_AUDMUX_V2_PTCR_SYN |
- MXC_AUDMUX_V2_PTCR_TFSDIR |
- MXC_AUDMUX_V2_PTCR_TFSEL(3) |
- MXC_AUDMUX_V2_PTCR_TCLKDIR |
- MXC_AUDMUX_V2_PTCR_TCSEL(3),
- MXC_AUDMUX_V2_PDCR_RXDSEL(3)
- );
- mxc_audmux_v2_configure_port(3,
- MXC_AUDMUX_V2_PTCR_SYN,
- MXC_AUDMUX_V2_PDCR_RXDSEL(0)
- );
-#endif
-
- imx35_add_imx_uart1(&uart_pdata);
- mxc_register_device(&mx3_ipu, &mx3_ipu_data);
- mxc_register_device(&mx3_fb, &mx3fb_pdata);
-
- imx35_add_imx_ssi(0, &eukrea_mbimxsd_ssi_pdata);
-
- imx35_add_flexcan1(NULL);
- imx35_add_sdhci_esdhc_imx(0, &sd1_pdata);
-
- gpio_request(GPIO_LED1, "LED1");
- gpio_direction_output(GPIO_LED1, 1);
- gpio_free(GPIO_LED1);
-
- gpio_request(GPIO_SWITCH1, "SWITCH1");
- gpio_direction_input(GPIO_SWITCH1);
- gpio_free(GPIO_SWITCH1);
-
- gpio_request(GPIO_LCDPWR, "LCDPWR");
- gpio_direction_output(GPIO_LCDPWR, 1);
-
- i2c_register_board_info(0, eukrea_mbimxsd_i2c_devices,
- ARRAY_SIZE(eukrea_mbimxsd_i2c_devices));
-
- platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
-}
diff --git a/arch/arm/mach-mx3/mach-armadillo5x0.c b/arch/arm/mach-mx3/mach-armadillo5x0.c
deleted file mode 100644
index 226829b..0000000
--- a/arch/arm/mach-mx3/mach-armadillo5x0.c
+++ /dev/null
@@ -1,578 +0,0 @@
-/*
- * armadillo5x0.c
- *
- * Copyright 2009 Alberto Panizzo <maramaopercheseimorto@gmail.com>
- * updates in http://alberdroid.blogspot.com/
- *
- * Based on Atmark Techno, Inc. armadillo 500 BSP 2008
- * Based on mx31ads.c and pcm037.c Great Work!
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/clk.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <linux/smsc911x.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/mtd/physmap.h>
-#include <linux/io.h>
-#include <linux/input.h>
-#include <linux/gpio_keys.h>
-#include <linux/i2c.h>
-#include <linux/usb/otg.h>
-#include <linux/usb/ulpi.h>
-#include <linux/delay.h>
-
-#include <mach/hardware.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <asm/memory.h>
-#include <asm/mach/map.h>
-
-#include <mach/common.h>
-#include <mach/iomux-mx3.h>
-#include <mach/ipu.h>
-#include <mach/mx3fb.h>
-#include <mach/ulpi.h>
-
-#include "devices-imx31.h"
-#include "devices.h"
-#include "crm_regs.h"
-
-static int armadillo5x0_pins[] = {
- /* UART1 */
- MX31_PIN_CTS1__CTS1,
- MX31_PIN_RTS1__RTS1,
- MX31_PIN_TXD1__TXD1,
- MX31_PIN_RXD1__RXD1,
- /* UART2 */
- MX31_PIN_CTS2__CTS2,
- MX31_PIN_RTS2__RTS2,
- MX31_PIN_TXD2__TXD2,
- MX31_PIN_RXD2__RXD2,
- /* LAN9118_IRQ */
- IOMUX_MODE(MX31_PIN_GPIO1_0, IOMUX_CONFIG_GPIO),
- /* SDHC1 */
- MX31_PIN_SD1_DATA3__SD1_DATA3,
- MX31_PIN_SD1_DATA2__SD1_DATA2,
- MX31_PIN_SD1_DATA1__SD1_DATA1,
- MX31_PIN_SD1_DATA0__SD1_DATA0,
- MX31_PIN_SD1_CLK__SD1_CLK,
- MX31_PIN_SD1_CMD__SD1_CMD,
- /* Framebuffer */
- MX31_PIN_LD0__LD0,
- MX31_PIN_LD1__LD1,
- MX31_PIN_LD2__LD2,
- MX31_PIN_LD3__LD3,
- MX31_PIN_LD4__LD4,
- MX31_PIN_LD5__LD5,
- MX31_PIN_LD6__LD6,
- MX31_PIN_LD7__LD7,
- MX31_PIN_LD8__LD8,
- MX31_PIN_LD9__LD9,
- MX31_PIN_LD10__LD10,
- MX31_PIN_LD11__LD11,
- MX31_PIN_LD12__LD12,
- MX31_PIN_LD13__LD13,
- MX31_PIN_LD14__LD14,
- MX31_PIN_LD15__LD15,
- MX31_PIN_LD16__LD16,
- MX31_PIN_LD17__LD17,
- MX31_PIN_VSYNC3__VSYNC3,
- MX31_PIN_HSYNC__HSYNC,
- MX31_PIN_FPSHIFT__FPSHIFT,
- MX31_PIN_DRDY0__DRDY0,
- IOMUX_MODE(MX31_PIN_LCS1, IOMUX_CONFIG_GPIO), /*ADV7125_PSAVE*/
- /* I2C2 */
- MX31_PIN_CSPI2_MOSI__SCL,
- MX31_PIN_CSPI2_MISO__SDA,
- /* OTG */
- MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
- MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
- MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
- MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
- MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
- MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
- MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
- MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
- MX31_PIN_USBOTG_CLK__USBOTG_CLK,
- MX31_PIN_USBOTG_DIR__USBOTG_DIR,
- MX31_PIN_USBOTG_NXT__USBOTG_NXT,
- MX31_PIN_USBOTG_STP__USBOTG_STP,
- /* USB host 2 */
- IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC),
- IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC),
- IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC),
- IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC),
- IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC),
- IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC),
- IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC),
- IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC),
- IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC),
- IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC),
- IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC),
- IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC),
-};
-
-/* USB */
-
-#define OTG_RESET IOMUX_TO_GPIO(MX31_PIN_STXD4)
-#define USBH2_RESET IOMUX_TO_GPIO(MX31_PIN_SCK6)
-#define USBH2_CS IOMUX_TO_GPIO(MX31_PIN_GPIO1_3)
-
-#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
- PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
-
-static int usbotg_init(struct platform_device *pdev)
-{
- int err;
-
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG);
-
- /* Chip already enabled by hardware */
- /* OTG phy reset*/
- err = gpio_request(OTG_RESET, "USB-OTG-RESET");
- if (err) {
- pr_err("Failed to request the usb otg reset gpio\n");
- return err;
- }
-
- err = gpio_direction_output(OTG_RESET, 1/*HIGH*/);
- if (err) {
- pr_err("Failed to reset the usb otg phy\n");
- goto otg_free_reset;
- }
-
- gpio_set_value(OTG_RESET, 0/*LOW*/);
- mdelay(5);
- gpio_set_value(OTG_RESET, 1/*HIGH*/);
- mdelay(10);
-
- return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED |
- MXC_EHCI_INTERFACE_DIFF_UNI);
-
-otg_free_reset:
- gpio_free(OTG_RESET);
- return err;
-}
-
-static int usbh2_init(struct platform_device *pdev)
-{
- int err;
-
- mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG);
-
- mxc_iomux_set_gpr(MUX_PGP_UH2, true);
-
-
- /* Enable the chip */
- err = gpio_request(USBH2_CS, "USB-H2-CS");
- if (err) {
- pr_err("Failed to request the usb host 2 CS gpio\n");
- return err;
- }
-
- err = gpio_direction_output(USBH2_CS, 0/*Enabled*/);
- if (err) {
- pr_err("Failed to drive the usb host 2 CS gpio\n");
- goto h2_free_cs;
- }
-
- /* H2 phy reset*/
- err = gpio_request(USBH2_RESET, "USB-H2-RESET");
- if (err) {
- pr_err("Failed to request the usb host 2 reset gpio\n");
- goto h2_free_cs;
- }
-
- err = gpio_direction_output(USBH2_RESET, 1/*HIGH*/);
- if (err) {
- pr_err("Failed to reset the usb host 2 phy\n");
- goto h2_free_reset;
- }
-
- gpio_set_value(USBH2_RESET, 0/*LOW*/);
- mdelay(5);
- gpio_set_value(USBH2_RESET, 1/*HIGH*/);
- mdelay(10);
-
- return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED |
- MXC_EHCI_INTERFACE_DIFF_UNI);
-
-h2_free_reset:
- gpio_free(USBH2_RESET);
-h2_free_cs:
- gpio_free(USBH2_CS);
- return err;
-}
-
-static struct mxc_usbh_platform_data usbotg_pdata __initdata = {
- .init = usbotg_init,
- .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
-};
-
-static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
- .init = usbh2_init,
- .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
-};
-
-/* RTC over I2C*/
-#define ARMADILLO5X0_RTC_GPIO IOMUX_TO_GPIO(MX31_PIN_SRXD4)
-
-static struct i2c_board_info armadillo5x0_i2c_rtc = {
- I2C_BOARD_INFO("s35390a", 0x30),
-};
-
-/* GPIO BUTTONS */
-static struct gpio_keys_button armadillo5x0_buttons[] = {
- {
- .code = KEY_ENTER, /*28*/
- .gpio = IOMUX_TO_GPIO(MX31_PIN_SCLK0),
- .active_low = 1,
- .desc = "menu",
- .wakeup = 1,
- }, {
- .code = KEY_BACK, /*158*/
- .gpio = IOMUX_TO_GPIO(MX31_PIN_SRST0),
- .active_low = 1,
- .desc = "back",
- .wakeup = 1,
- }
-};
-
-static struct gpio_keys_platform_data armadillo5x0_button_data = {
- .buttons = armadillo5x0_buttons,
- .nbuttons = ARRAY_SIZE(armadillo5x0_buttons),
-};
-
-static struct platform_device armadillo5x0_button_device = {
- .name = "gpio-keys",
- .id = -1,
- .num_resources = 0,
- .dev = {
- .platform_data = &armadillo5x0_button_data,
- }
-};
-
-/*
- * NAND Flash
- */
-static const struct mxc_nand_platform_data
-armadillo5x0_nand_board_info __initconst = {
- .width = 1,
- .hw_ecc = 1,
-};
-
-/*
- * MTD NOR Flash
- */
-static struct mtd_partition armadillo5x0_nor_flash_partitions[] = {
- {
- .name = "nor.bootloader",
- .offset = 0x00000000,
- .size = 4*32*1024,
- }, {
- .name = "nor.kernel",
- .offset = MTDPART_OFS_APPEND,
- .size = 16*128*1024,
- }, {
- .name = "nor.userland",
- .offset = MTDPART_OFS_APPEND,
- .size = 110*128*1024,
- }, {
- .name = "nor.config",
- .offset = MTDPART_OFS_APPEND,
- .size = 1*128*1024,
- },
-};
-
-static struct physmap_flash_data armadillo5x0_nor_flash_pdata = {
- .width = 2,
- .parts = armadillo5x0_nor_flash_partitions,
- .nr_parts = ARRAY_SIZE(armadillo5x0_nor_flash_partitions),
-};
-
-static struct resource armadillo5x0_nor_flash_resource = {
- .flags = IORESOURCE_MEM,
- .start = MX31_CS0_BASE_ADDR,
- .end = MX31_CS0_BASE_ADDR + SZ_64M - 1,
-};
-
-static struct platform_device armadillo5x0_nor_flash = {
- .name = "physmap-flash",
- .id = -1,
- .num_resources = 1,
- .resource = &armadillo5x0_nor_flash_resource,
-};
-
-/*
- * FB support
- */
-static const struct fb_videomode fb_modedb[] = {
- { /* 640x480 @ 60 Hz */
- .name = "CRT-VGA",
- .refresh = 60,
- .xres = 640,
- .yres = 480,
- .pixclock = 39721,
- .left_margin = 35,
- .right_margin = 115,
- .upper_margin = 43,
- .lower_margin = 1,
- .hsync_len = 10,
- .vsync_len = 1,
- .sync = FB_SYNC_OE_ACT_HIGH,
- .vmode = FB_VMODE_NONINTERLACED,
- .flag = 0,
- }, {/* 800x600 @ 56 Hz */
- .name = "CRT-SVGA",
- .refresh = 56,
- .xres = 800,
- .yres = 600,
- .pixclock = 30000,
- .left_margin = 30,
- .right_margin = 108,
- .upper_margin = 13,
- .lower_margin = 10,
- .hsync_len = 10,
- .vsync_len = 1,
- .sync = FB_SYNC_OE_ACT_HIGH | FB_SYNC_HOR_HIGH_ACT |
- FB_SYNC_VERT_HIGH_ACT,
- .vmode = FB_VMODE_NONINTERLACED,
- .flag = 0,
- },
-};
-
-static struct ipu_platform_data mx3_ipu_data = {
- .irq_base = MXC_IPU_IRQ_START,
-};
-
-static struct mx3fb_platform_data mx3fb_pdata = {
- .dma_dev = &mx3_ipu.dev,
- .name = "CRT-VGA",
- .mode = fb_modedb,
- .num_modes = ARRAY_SIZE(fb_modedb),
-};
-
-/*
- * SDHC 1
- * MMC support
- */
-static int armadillo5x0_sdhc1_get_ro(struct device *dev)
-{
- return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_ATA_RESET_B));
-}
-
-static int armadillo5x0_sdhc1_init(struct device *dev,
- irq_handler_t detect_irq, void *data)
-{
- int ret;
- int gpio_det, gpio_wp;
-
- gpio_det = IOMUX_TO_GPIO(MX31_PIN_ATA_DMACK);
- gpio_wp = IOMUX_TO_GPIO(MX31_PIN_ATA_RESET_B);
-
- ret = gpio_request(gpio_det, "sdhc-card-detect");
- if (ret)
- return ret;
-
- gpio_direction_input(gpio_det);
-
- ret = gpio_request(gpio_wp, "sdhc-write-protect");
- if (ret)
- goto err_gpio_free;
-
- gpio_direction_input(gpio_wp);
-
- /* When supported the trigger type have to be BOTH */
- ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_ATA_DMACK), detect_irq,
- IRQF_DISABLED | IRQF_TRIGGER_FALLING,
- "sdhc-detect", data);
-
- if (ret)
- goto err_gpio_free_2;
-
- return 0;
-
-err_gpio_free_2:
- gpio_free(gpio_wp);
-
-err_gpio_free:
- gpio_free(gpio_det);
-
- return ret;
-
-}
-
-static void armadillo5x0_sdhc1_exit(struct device *dev, void *data)
-{
- free_irq(IOMUX_TO_IRQ(MX31_PIN_ATA_DMACK), data);
- gpio_free(IOMUX_TO_GPIO(MX31_PIN_ATA_DMACK));
- gpio_free(IOMUX_TO_GPIO(MX31_PIN_ATA_RESET_B));
-}
-
-static const struct imxmmc_platform_data sdhc_pdata __initconst = {
- .get_ro = armadillo5x0_sdhc1_get_ro,
- .init = armadillo5x0_sdhc1_init,
- .exit = armadillo5x0_sdhc1_exit,
-};
-
-/*
- * SMSC 9118
- * Network support
- */
-static struct resource armadillo5x0_smc911x_resources[] = {
- {
- .start = MX31_CS3_BASE_ADDR,
- .end = MX31_CS3_BASE_ADDR + SZ_32M - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IOMUX_TO_IRQ(MX31_PIN_GPIO1_0),
- .end = IOMUX_TO_IRQ(MX31_PIN_GPIO1_0),
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- },
-};
-
-static struct smsc911x_platform_config smsc911x_info = {
- .flags = SMSC911X_USE_16BIT,
- .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
- .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
-};
-
-static struct platform_device armadillo5x0_smc911x_device = {
- .name = "smsc911x",
- .id = -1,
- .num_resources = ARRAY_SIZE(armadillo5x0_smc911x_resources),
- .resource = armadillo5x0_smc911x_resources,
- .dev = {
- .platform_data = &smsc911x_info,
- },
-};
-
-/* UART device data */
-static const struct imxuart_platform_data uart_pdata __initconst = {
- .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static struct platform_device *devices[] __initdata = {
- &armadillo5x0_smc911x_device,
- &armadillo5x0_button_device,
-};
-
-/*
- * Perform board specific initializations
- */
-static void __init armadillo5x0_init(void)
-{
- mxc_iomux_setup_multiple_pins(armadillo5x0_pins,
- ARRAY_SIZE(armadillo5x0_pins), "armadillo5x0");
-
- platform_add_devices(devices, ARRAY_SIZE(devices));
- imx31_add_imx_i2c1(NULL);
-
- /* Register UART */
- imx31_add_imx_uart0(&uart_pdata);
- imx31_add_imx_uart1(&uart_pdata);
-
- /* SMSC9118 IRQ pin */
- gpio_direction_input(MX31_PIN_GPIO1_0);
-
- /* Register SDHC */
- imx31_add_mxc_mmc(0, &sdhc_pdata);
-
- /* Register FB */
- mxc_register_device(&mx3_ipu, &mx3_ipu_data);
- mxc_register_device(&mx3_fb, &mx3fb_pdata);
-
- /* Register NOR Flash */
- mxc_register_device(&armadillo5x0_nor_flash,
- &armadillo5x0_nor_flash_pdata);
-
- /* Register NAND Flash */
- imx31_add_mxc_nand(&armadillo5x0_nand_board_info);
-
- /* set NAND page size to 2k if not configured via boot mode pins */
- __raw_writel(__raw_readl(MXC_CCM_RCSR) | (1 << 30), MXC_CCM_RCSR);
-
- /* RTC */
- /* Get RTC IRQ and register the chip */
- if (gpio_request(ARMADILLO5X0_RTC_GPIO, "rtc") == 0) {
- if (gpio_direction_input(ARMADILLO5X0_RTC_GPIO) == 0)
- armadillo5x0_i2c_rtc.irq = gpio_to_irq(ARMADILLO5X0_RTC_GPIO);
- else
- gpio_free(ARMADILLO5X0_RTC_GPIO);
- }
- if (armadillo5x0_i2c_rtc.irq == 0)
- pr_warning("armadillo5x0_init: failed to get RTC IRQ\n");
- i2c_register_board_info(1, &armadillo5x0_i2c_rtc, 1);
-
- /* USB */
-
- usbotg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
- ULPI_OTG_DRVVBUS_EXT);
- if (usbotg_pdata.otg)
- imx31_add_mxc_ehci_otg(&usbotg_pdata);
- usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
- ULPI_OTG_DRVVBUS_EXT);
- if (usbh2_pdata.otg)
- imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
-}
-
-static void __init armadillo5x0_timer_init(void)
-{
- mx31_clocks_init(26000000);
-}
-
-static struct sys_timer armadillo5x0_timer = {
- .init = armadillo5x0_timer_init,
-};
-
-MACHINE_START(ARMADILLO5X0, "Armadillo-500")
- /* Maintainer: Alberto Panizzo */
- .boot_params = MX3x_PHYS_OFFSET + 0x100,
- .map_io = mx31_map_io,
- .init_early = imx31_init_early,
- .init_irq = mx31_init_irq,
- .timer = &armadillo5x0_timer,
- .init_machine = armadillo5x0_init,
-MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-bug.c b/arch/arm/mach-mx3/mach-bug.c
deleted file mode 100644
index d137d70..0000000
--- a/arch/arm/mach-mx3/mach-bug.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * Copyright (C) 2000 Deep Blue Solutions Ltd
- * Copyright (C) 2002 Shane Nay (shane@minirl.com)
- * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2011 Denis 'GNUtoo' Carikli <GNUtoo@no-log.org>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-
-#include <mach/iomux-mx3.h>
-#include <mach/imx-uart.h>
-#include <mach/hardware.h>
-#include <mach/common.h>
-
-#include <asm/mach/time.h>
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-
-#include "devices-imx31.h"
-
-static const struct imxuart_platform_data uart_pdata __initconst = {
- .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static const unsigned int bug_pins[] __initconst = {
- MX31_PIN_PC_RST__CTS5,
- MX31_PIN_PC_VS2__RTS5,
- MX31_PIN_PC_BVD2__TXD5,
- MX31_PIN_PC_BVD1__RXD5,
-};
-
-static void __init bug_board_init(void)
-{
- mxc_iomux_setup_multiple_pins(bug_pins,
- ARRAY_SIZE(bug_pins), "uart-4");
- imx31_add_imx_uart4(&uart_pdata);
-}
-
-static void __init bug_timer_init(void)
-{
- mx31_clocks_init(26000000);
-}
-
-static struct sys_timer bug_timer = {
- .init = bug_timer_init,
-};
-
-MACHINE_START(BUG, "BugLabs BUGBase")
- .map_io = mx31_map_io,
- .init_early = imx31_init_early,
- .init_irq = mx31_init_irq,
- .timer = &bug_timer,
- .init_machine = bug_board_init,
-MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-cpuimx35.c b/arch/arm/mach-mx3/mach-cpuimx35.c
deleted file mode 100644
index ec63d99..0000000
--- a/arch/arm/mach-mx3/mach-cpuimx35.c
+++ /dev/null
@@ -1,203 +0,0 @@
-/*
- * Copyright (C) 2010 Eric Benard - eric@eukrea.com
- * Copyright (C) 2009 Sascha Hauer, Pengutronix
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-
-#include <linux/types.h>
-#include <linux/init.h>
-
-#include <linux/platform_device.h>
-#include <linux/mtd/physmap.h>
-#include <linux/memory.h>
-#include <linux/gpio.h>
-#include <linux/interrupt.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/i2c/tsc2007.h>
-#include <linux/usb/otg.h>
-#include <linux/usb/ulpi.h>
-#include <linux/i2c-gpio.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <asm/mach/map.h>
-
-#include <mach/eukrea-baseboards.h>
-#include <mach/hardware.h>
-#include <mach/common.h>
-#include <mach/iomux-mx35.h>
-#include <mach/mxc_nand.h>
-
-#include "devices-imx35.h"
-#include "devices.h"
-
-static const struct imxuart_platform_data uart_pdata __initconst = {
- .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static const struct imxi2c_platform_data
- eukrea_cpuimx35_i2c0_data __initconst = {
- .bitrate = 100000,
-};
-
-static struct tsc2007_platform_data tsc2007_info = {
- .model = 2007,
- .x_plate_ohms = 180,
-};
-
-#define TSC2007_IRQGPIO IMX_GPIO_NR(3, 2)
-static struct i2c_board_info eukrea_cpuimx35_i2c_devices[] = {
- {
- I2C_BOARD_INFO("pcf8563", 0x51),
- }, {
- I2C_BOARD_INFO("tsc2007", 0x48),
- .type = "tsc2007",
- .platform_data = &tsc2007_info,
- .irq = gpio_to_irq(TSC2007_IRQGPIO),
- },
-};
-
-static iomux_v3_cfg_t eukrea_cpuimx35_pads[] = {
- /* UART1 */
- MX35_PAD_CTS1__UART1_CTS,
- MX35_PAD_RTS1__UART1_RTS,
- MX35_PAD_TXD1__UART1_TXD_MUX,
- MX35_PAD_RXD1__UART1_RXD_MUX,
- /* FEC */
- MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
- MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
- MX35_PAD_FEC_RX_DV__FEC_RX_DV,
- MX35_PAD_FEC_COL__FEC_COL,
- MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
- MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
- MX35_PAD_FEC_TX_EN__FEC_TX_EN,
- MX35_PAD_FEC_MDC__FEC_MDC,
- MX35_PAD_FEC_MDIO__FEC_MDIO,
- MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
- MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
- MX35_PAD_FEC_CRS__FEC_CRS,
- MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
- MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
- MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
- MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
- MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
- MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
- /* I2C1 */
- MX35_PAD_I2C1_CLK__I2C1_SCL,
- MX35_PAD_I2C1_DAT__I2C1_SDA,
- /* TSC2007 IRQ */
- MX35_PAD_ATA_DA2__GPIO3_2,
-};
-
-static const struct mxc_nand_platform_data
- eukrea_cpuimx35_nand_board_info __initconst = {
- .width = 1,
- .hw_ecc = 1,
- .flash_bbt = 1,
-};
-
-static int eukrea_cpuimx35_otg_init(struct platform_device *pdev)
-{
- return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
-}
-
-static const struct mxc_usbh_platform_data otg_pdata __initconst = {
- .init = eukrea_cpuimx35_otg_init,
- .portsc = MXC_EHCI_MODE_UTMI,
-};
-
-static int eukrea_cpuimx35_usbh1_init(struct platform_device *pdev)
-{
- return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_SINGLE_UNI |
- MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN);
-}
-
-static const struct mxc_usbh_platform_data usbh1_pdata __initconst = {
- .init = eukrea_cpuimx35_usbh1_init,
- .portsc = MXC_EHCI_MODE_SERIAL,
-};
-
-static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
- .operating_mode = FSL_USB2_DR_DEVICE,
- .phy_mode = FSL_USB2_PHY_UTMI,
- .workaround = FLS_USB2_WORKAROUND_ENGCM09152,
-};
-
-static int otg_mode_host;
-
-static int __init eukrea_cpuimx35_otg_mode(char *options)
-{
- if (!strcmp(options, "host"))
- otg_mode_host = 1;
- else if (!strcmp(options, "device"))
- otg_mode_host = 0;
- else
- pr_info("otg_mode neither \"host\" nor \"device\". "
- "Defaulting to device\n");
- return 0;
-}
-__setup("otg_mode=", eukrea_cpuimx35_otg_mode);
-
-/*
- * Board specific initialization.
- */
-static void __init eukrea_cpuimx35_init(void)
-{
- mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx35_pads,
- ARRAY_SIZE(eukrea_cpuimx35_pads));
-
- imx35_add_fec(NULL);
- imx35_add_imx2_wdt(NULL);
-
- imx35_add_imx_uart0(&uart_pdata);
- imx35_add_mxc_nand(&eukrea_cpuimx35_nand_board_info);
-
- i2c_register_board_info(0, eukrea_cpuimx35_i2c_devices,
- ARRAY_SIZE(eukrea_cpuimx35_i2c_devices));
- imx35_add_imx_i2c0(&eukrea_cpuimx35_i2c0_data);
-
- if (otg_mode_host)
- imx35_add_mxc_ehci_otg(&otg_pdata);
- else
- imx35_add_fsl_usb2_udc(&otg_device_pdata);
-
- imx35_add_mxc_ehci_hs(&usbh1_pdata);
-
-#ifdef CONFIG_MACH_EUKREA_MBIMXSD35_BASEBOARD
- eukrea_mbimxsd35_baseboard_init();
-#endif
-}
-
-static void __init eukrea_cpuimx35_timer_init(void)
-{
- mx35_clocks_init();
-}
-
-struct sys_timer eukrea_cpuimx35_timer = {
- .init = eukrea_cpuimx35_timer_init,
-};
-
-MACHINE_START(EUKREA_CPUIMX35, "Eukrea CPUIMX35")
- /* Maintainer: Eukrea Electromatique */
- .boot_params = MX3x_PHYS_OFFSET + 0x100,
- .map_io = mx35_map_io,
- .init_early = imx35_init_early,
- .init_irq = mx35_init_irq,
- .timer = &eukrea_cpuimx35_timer,
- .init_machine = eukrea_cpuimx35_init,
-MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-kzm_arm11_01.c b/arch/arm/mach-mx3/mach-kzm_arm11_01.c
deleted file mode 100644
index d35621d..0000000
--- a/arch/arm/mach-mx3/mach-kzm_arm11_01.c
+++ /dev/null
@@ -1,279 +0,0 @@
-/*
- * KZM-ARM11-01 support
- * Copyright (C) 2009 Yoichi Yuasa <yuasa@linux-mips.org>
- *
- * based on code for MX31ADS,
- * Copyright (C) 2000 Deep Blue Solutions Ltd
- * Copyright (C) 2002 Shane Nay (shane@minirl.com)
- * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/serial_8250.h>
-#include <linux/smsc911x.h>
-#include <linux/types.h>
-
-#include <asm/irq.h>
-#include <asm/mach-types.h>
-#include <asm/memory.h>
-#include <asm/setup.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/irq.h>
-#include <asm/mach/map.h>
-#include <asm/mach/time.h>
-
-#include <mach/clock.h>
-#include <mach/common.h>
-#include <mach/iomux-mx3.h>
-
-#include "devices-imx31.h"
-#include "devices.h"
-
-#define KZM_ARM11_IO_ADDRESS(x) (IOMEM( \
- IMX_IO_P2V_MODULE(x, MX31_CS4) ?: \
- IMX_IO_P2V_MODULE(x, MX31_CS5)) ?: \
- MX31_IO_ADDRESS(x))
-
-/*
- * KZM-ARM11-01 Board Control Registers on FPGA
- */
-#define KZM_ARM11_CTL1 (MX31_CS4_BASE_ADDR + 0x1000)
-#define KZM_ARM11_CTL2 (MX31_CS4_BASE_ADDR + 0x1001)
-#define KZM_ARM11_RSW1 (MX31_CS4_BASE_ADDR + 0x1002)
-#define KZM_ARM11_BACK_LIGHT (MX31_CS4_BASE_ADDR + 0x1004)
-#define KZM_ARM11_FPGA_REV (MX31_CS4_BASE_ADDR + 0x1008)
-#define KZM_ARM11_7SEG_LED (MX31_CS4_BASE_ADDR + 0x1010)
-#define KZM_ARM11_LEDS (MX31_CS4_BASE_ADDR + 0x1020)
-#define KZM_ARM11_DIPSW2 (MX31_CS4_BASE_ADDR + 0x1003)
-
-/*
- * External UART for touch panel on FPGA
- */
-#define KZM_ARM11_16550 (MX31_CS4_BASE_ADDR + 0x1050)
-
-#if defined(CONFIG_SERIAL_8250) || defined(CONFIG_SERIAL_8250_MODULE)
-/*
- * KZM-ARM11-01 has an external UART on FPGA
- */
-static struct plat_serial8250_port serial_platform_data[] = {
- {
- .membase = KZM_ARM11_IO_ADDRESS(KZM_ARM11_16550),
- .mapbase = KZM_ARM11_16550,
- .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_1),
- .irqflags = IRQ_TYPE_EDGE_RISING,
- .uartclk = 14745600,
- .regshift = 0,
- .iotype = UPIO_MEM,
- .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
- UPF_BUGGY_UART,
- },
- {},
-};
-
-static struct resource serial8250_resources[] = {
- {
- .start = KZM_ARM11_16550,
- .end = KZM_ARM11_16550 + 0x10,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IOMUX_TO_IRQ(MX31_PIN_GPIO1_1),
- .end = IOMUX_TO_IRQ(MX31_PIN_GPIO1_1),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device serial_device = {
- .name = "serial8250",
- .id = PLAT8250_DEV_PLATFORM,
- .dev = {
- .platform_data = serial_platform_data,
- },
- .num_resources = ARRAY_SIZE(serial8250_resources),
- .resource = serial8250_resources,
-};
-
-static int __init kzm_init_ext_uart(void)
-{
- u8 tmp;
-
- /*
- * GPIO 1-1: external UART interrupt line
- */
- mxc_iomux_mode(IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO));
- gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1), "ext-uart-int");
- gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_1));
-
- /*
- * Unmask UART interrupt
- */
- tmp = __raw_readb(KZM_ARM11_IO_ADDRESS(KZM_ARM11_CTL1));
- tmp |= 0x2;
- __raw_writeb(tmp, KZM_ARM11_IO_ADDRESS(KZM_ARM11_CTL1));
-
- return platform_device_register(&serial_device);
-}
-#else
-static inline int kzm_init_ext_uart(void)
-{
- return 0;
-}
-#endif
-
-/*
- * SMSC LAN9118
- */
-#if defined(CONFIG_SMSC911X) || defined(CONFIG_SMSC911X_MODULE)
-static struct smsc911x_platform_config kzm_smsc9118_config = {
- .phy_interface = PHY_INTERFACE_MODE_MII,
- .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_HIGH,
- .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
- .flags = SMSC911X_USE_32BIT | SMSC911X_SAVE_MAC_ADDRESS,
-};
-
-static struct resource kzm_smsc9118_resources[] = {
- {
- .start = MX31_CS5_BASE_ADDR,
- .end = MX31_CS5_BASE_ADDR + SZ_128K - 1,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IOMUX_TO_IRQ(MX31_PIN_GPIO1_2),
- .end = IOMUX_TO_IRQ(MX31_PIN_GPIO1_2),
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
- },
-};
-
-static struct platform_device kzm_smsc9118_device = {
- .name = "smsc911x",
- .id = -1,
- .num_resources = ARRAY_SIZE(kzm_smsc9118_resources),
- .resource = kzm_smsc9118_resources,
- .dev = {
- .platform_data = &kzm_smsc9118_config,
- },
-};
-
-static int __init kzm_init_smsc9118(void)
-{
- /*
- * GPIO 1-2: SMSC9118 interrupt line
- */
- mxc_iomux_mode(IOMUX_MODE(MX31_PIN_GPIO1_2, IOMUX_CONFIG_GPIO));
- gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2), "smsc9118-int");
- gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_2));
-
- return platform_device_register(&kzm_smsc9118_device);
-}
-#else
-static inline int kzm_init_smsc9118(void)
-{
- return 0;
-}
-#endif
-
-#if defined(CONFIG_SERIAL_IMX) || defined(CONFIG_SERIAL_IMX_MODULE)
-static const struct imxuart_platform_data uart_pdata __initconst = {
- .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static void __init kzm_init_imx_uart(void)
-{
- imx31_add_imx_uart0(&uart_pdata);
- imx31_add_imx_uart1(&uart_pdata);
-}
-#else
-static inline void kzm_init_imx_uart(void)
-{
-}
-#endif
-
-static int kzm_pins[] __initdata = {
- MX31_PIN_CTS1__CTS1,
- MX31_PIN_RTS1__RTS1,
- MX31_PIN_TXD1__TXD1,
- MX31_PIN_RXD1__RXD1,
- MX31_PIN_DCD_DCE1__DCD_DCE1,
- MX31_PIN_RI_DCE1__RI_DCE1,
- MX31_PIN_DSR_DCE1__DSR_DCE1,
- MX31_PIN_DTR_DCE1__DTR_DCE1,
- MX31_PIN_CTS2__CTS2,
- MX31_PIN_RTS2__RTS2,
- MX31_PIN_TXD2__TXD2,
- MX31_PIN_RXD2__RXD2,
- MX31_PIN_DCD_DTE1__DCD_DTE2,
- MX31_PIN_RI_DTE1__RI_DTE2,
- MX31_PIN_DSR_DTE1__DSR_DTE2,
- MX31_PIN_DTR_DTE1__DTR_DTE2,
-};
-
-/*
- * Board specific initialization.
- */
-static void __init kzm_board_init(void)
-{
- mxc_iomux_setup_multiple_pins(kzm_pins,
- ARRAY_SIZE(kzm_pins), "kzm");
- kzm_init_ext_uart();
- kzm_init_smsc9118();
- kzm_init_imx_uart();
-
- pr_info("Clock input source is 26MHz\n");
-}
-
-/*
- * This structure defines static mappings for the kzm-arm11-01 board.
- */
-static struct map_desc kzm_io_desc[] __initdata = {
- {
- .virtual = MX31_CS4_BASE_ADDR_VIRT,
- .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
- .length = MX31_CS4_SIZE,
- .type = MT_DEVICE
- },
- {
- .virtual = MX31_CS5_BASE_ADDR_VIRT,
- .pfn = __phys_to_pfn(MX31_CS5_BASE_ADDR),
- .length = MX31_CS5_SIZE,
- .type = MT_DEVICE
- },
-};
-
-/*
- * Set up static virtual mappings.
- */
-static void __init kzm_map_io(void)
-{
- mx31_map_io();
- iotable_init(kzm_io_desc, ARRAY_SIZE(kzm_io_desc));
-}
-
-static void __init kzm_timer_init(void)
-{
- mx31_clocks_init(26000000);
-}
-
-static struct sys_timer kzm_timer = {
- .init = kzm_timer_init,
-};
-
-MACHINE_START(KZM_ARM11_01, "Kyoto Microcomputer Co., Ltd. KZM-ARM11-01")
- .boot_params = MX3x_PHYS_OFFSET + 0x100,
- .map_io = kzm_map_io,
- .init_early = imx31_init_early,
- .init_irq = mx31_init_irq,
- .timer = &kzm_timer,
- .init_machine = kzm_board_init,
-MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-mx31_3ds.c b/arch/arm/mach-mx3/mach-mx31_3ds.c
deleted file mode 100644
index 034be62..0000000
--- a/arch/arm/mach-mx3/mach-mx31_3ds.c
+++ /dev/null
@@ -1,771 +0,0 @@
-/*
- * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/delay.h>
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/clk.h>
-#include <linux/irq.h>
-#include <linux/gpio.h>
-#include <linux/platform_device.h>
-#include <linux/mfd/mc13783.h>
-#include <linux/spi/spi.h>
-#include <linux/spi/l4f00242t03.h>
-#include <linux/regulator/machine.h>
-#include <linux/usb/otg.h>
-#include <linux/usb/ulpi.h>
-#include <linux/memblock.h>
-
-#include <media/soc_camera.h>
-
-#include <mach/hardware.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <asm/memory.h>
-#include <asm/mach/map.h>
-#include <mach/common.h>
-#include <mach/iomux-mx3.h>
-#include <mach/3ds_debugboard.h>
-#include <mach/ulpi.h>
-#include <mach/mmc.h>
-#include <mach/ipu.h>
-#include <mach/mx3fb.h>
-#include <mach/mx3_camera.h>
-
-#include "devices-imx31.h"
-#include "devices.h"
-
-/* CPLD IRQ line for external uart, external ethernet etc */
-#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_1)
-
-static int mx31_3ds_pins[] = {
- /* UART1 */
- MX31_PIN_CTS1__CTS1,
- MX31_PIN_RTS1__RTS1,
- MX31_PIN_TXD1__TXD1,
- MX31_PIN_RXD1__RXD1,
- IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO),
- /*SPI0*/
- MX31_PIN_CSPI1_SCLK__SCLK,
- MX31_PIN_CSPI1_MOSI__MOSI,
- MX31_PIN_CSPI1_MISO__MISO,
- MX31_PIN_CSPI1_SPI_RDY__SPI_RDY,
- MX31_PIN_CSPI1_SS2__SS2, /* CS for LCD */
- /* SPI 1 */
- MX31_PIN_CSPI2_SCLK__SCLK,
- MX31_PIN_CSPI2_MOSI__MOSI,
- MX31_PIN_CSPI2_MISO__MISO,
- MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
- MX31_PIN_CSPI2_SS0__SS0,
- MX31_PIN_CSPI2_SS2__SS2, /*CS for MC13783 */
- /* MC13783 IRQ */
- IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO),
- /* USB OTG reset */
- IOMUX_MODE(MX31_PIN_USB_PWR, IOMUX_CONFIG_GPIO),
- /* USB OTG */
- MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
- MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
- MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
- MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
- MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
- MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
- MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
- MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
- MX31_PIN_USBOTG_CLK__USBOTG_CLK,
- MX31_PIN_USBOTG_DIR__USBOTG_DIR,
- MX31_PIN_USBOTG_NXT__USBOTG_NXT,
- MX31_PIN_USBOTG_STP__USBOTG_STP,
- /*Keyboard*/
- MX31_PIN_KEY_ROW0_KEY_ROW0,
- MX31_PIN_KEY_ROW1_KEY_ROW1,
- MX31_PIN_KEY_ROW2_KEY_ROW2,
- MX31_PIN_KEY_COL0_KEY_COL0,
- MX31_PIN_KEY_COL1_KEY_COL1,
- MX31_PIN_KEY_COL2_KEY_COL2,
- MX31_PIN_KEY_COL3_KEY_COL3,
- /* USB Host 2 */
- IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC),
- IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC),
- IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC),
- IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC),
- IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC),
- IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC),
- IOMUX_MODE(MX31_PIN_PC_VS2, IOMUX_CONFIG_ALT1),
- IOMUX_MODE(MX31_PIN_PC_BVD1, IOMUX_CONFIG_ALT1),
- IOMUX_MODE(MX31_PIN_PC_BVD2, IOMUX_CONFIG_ALT1),
- IOMUX_MODE(MX31_PIN_PC_RST, IOMUX_CONFIG_ALT1),
- IOMUX_MODE(MX31_PIN_IOIS16, IOMUX_CONFIG_ALT1),
- IOMUX_MODE(MX31_PIN_PC_RW_B, IOMUX_CONFIG_ALT1),
- /* USB Host2 reset */
- IOMUX_MODE(MX31_PIN_USB_BYP, IOMUX_CONFIG_GPIO),
- /* I2C1 */
- MX31_PIN_I2C_CLK__I2C1_SCL,
- MX31_PIN_I2C_DAT__I2C1_SDA,
- /* SDHC1 */
- MX31_PIN_SD1_DATA3__SD1_DATA3,
- MX31_PIN_SD1_DATA2__SD1_DATA2,
- MX31_PIN_SD1_DATA1__SD1_DATA1,
- MX31_PIN_SD1_DATA0__SD1_DATA0,
- MX31_PIN_SD1_CLK__SD1_CLK,
- MX31_PIN_SD1_CMD__SD1_CMD,
- MX31_PIN_GPIO3_1__GPIO3_1, /* Card detect */
- MX31_PIN_GPIO3_0__GPIO3_0, /* OE */
- /* Framebuffer */
- MX31_PIN_LD0__LD0,
- MX31_PIN_LD1__LD1,
- MX31_PIN_LD2__LD2,
- MX31_PIN_LD3__LD3,
- MX31_PIN_LD4__LD4,
- MX31_PIN_LD5__LD5,
- MX31_PIN_LD6__LD6,
- MX31_PIN_LD7__LD7,
- MX31_PIN_LD8__LD8,
- MX31_PIN_LD9__LD9,
- MX31_PIN_LD10__LD10,
- MX31_PIN_LD11__LD11,
- MX31_PIN_LD12__LD12,
- MX31_PIN_LD13__LD13,
- MX31_PIN_LD14__LD14,
- MX31_PIN_LD15__LD15,
- MX31_PIN_LD16__LD16,
- MX31_PIN_LD17__LD17,
- MX31_PIN_VSYNC3__VSYNC3,
- MX31_PIN_HSYNC__HSYNC,
- MX31_PIN_FPSHIFT__FPSHIFT,
- MX31_PIN_CONTRAST__CONTRAST,
- /* CSI */
- MX31_PIN_CSI_D6__CSI_D6,
- MX31_PIN_CSI_D7__CSI_D7,
- MX31_PIN_CSI_D8__CSI_D8,
- MX31_PIN_CSI_D9__CSI_D9,
- MX31_PIN_CSI_D10__CSI_D10,
- MX31_PIN_CSI_D11__CSI_D11,
- MX31_PIN_CSI_D12__CSI_D12,
- MX31_PIN_CSI_D13__CSI_D13,
- MX31_PIN_CSI_D14__CSI_D14,
- MX31_PIN_CSI_D15__CSI_D15,
- MX31_PIN_CSI_HSYNC__CSI_HSYNC,
- MX31_PIN_CSI_MCLK__CSI_MCLK,
- MX31_PIN_CSI_PIXCLK__CSI_PIXCLK,
- MX31_PIN_CSI_VSYNC__CSI_VSYNC,
- MX31_PIN_CSI_D5__GPIO3_5, /* CMOS PWDN */
- IOMUX_MODE(MX31_PIN_RI_DTE1, IOMUX_CONFIG_GPIO), /* CMOS reset */
-};
-
-/*
- * Camera support
- */
-static phys_addr_t mx3_camera_base __initdata;
-#define MX31_3DS_CAMERA_BUF_SIZE SZ_8M
-
-#define MX31_3DS_GPIO_CAMERA_PW IOMUX_TO_GPIO(MX31_PIN_CSI_D5)
-#define MX31_3DS_GPIO_CAMERA_RST IOMUX_TO_GPIO(MX31_PIN_RI_DTE1)
-
-static struct gpio mx31_3ds_camera_gpios[] = {
- { MX31_3DS_GPIO_CAMERA_PW, GPIOF_OUT_INIT_HIGH, "camera-power" },
- { MX31_3DS_GPIO_CAMERA_RST, GPIOF_OUT_INIT_HIGH, "camera-reset" },
-};
-
-static int __init mx31_3ds_camera_alloc_dma(void)
-{
- int dma;
-
- if (!mx3_camera_base)
- return -ENOMEM;
-
- dma = dma_declare_coherent_memory(&mx3_camera.dev,
- mx3_camera_base, mx3_camera_base,
- MX31_3DS_CAMERA_BUF_SIZE,
- DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
-
- if (!(dma & DMA_MEMORY_MAP))
- return -ENOMEM;
-
- return 0;
-}
-
-static int mx31_3ds_camera_power(struct device *dev, int on)
-{
- /* enable or disable the camera */
- pr_debug("%s: %s the camera\n", __func__, on ? "ENABLE" : "DISABLE");
- gpio_set_value(MX31_3DS_GPIO_CAMERA_PW, on ? 0 : 1);
-
- if (!on)
- goto out;
-
- /* If enabled, give a reset impulse */
- gpio_set_value(MX31_3DS_GPIO_CAMERA_RST, 0);
- msleep(20);
- gpio_set_value(MX31_3DS_GPIO_CAMERA_RST, 1);
- msleep(100);
-
-out:
- return 0;
-}
-
-static struct i2c_board_info mx31_3ds_i2c_camera = {
- I2C_BOARD_INFO("ov2640", 0x30),
-};
-
-static struct regulator_bulk_data mx31_3ds_camera_regs[] = {
- { .supply = "cmos_vcore" },
- { .supply = "cmos_2v8" },
-};
-
-static struct soc_camera_link iclink_ov2640 = {
- .bus_id = 0,
- .board_info = &mx31_3ds_i2c_camera,
- .i2c_adapter_id = 0,
- .power = mx31_3ds_camera_power,
- .regulators = mx31_3ds_camera_regs,
- .num_regulators = ARRAY_SIZE(mx31_3ds_camera_regs),
-};
-
-static struct platform_device mx31_3ds_ov2640 = {
- .name = "soc-camera-pdrv",
- .id = 0,
- .dev = {
- .platform_data = &iclink_ov2640,
- },
-};
-
-struct mx3_camera_pdata mx31_3ds_camera_pdata = {
- .dma_dev = &mx3_ipu.dev,
- .flags = MX3_CAMERA_DATAWIDTH_10,
- .mclk_10khz = 2600,
-};
-
-/*
- * FB support
- */
-static const struct fb_videomode fb_modedb[] = {
- { /* 480x640 @ 60 Hz */
- .name = "Epson-VGA",
- .refresh = 60,
- .xres = 480,
- .yres = 640,
- .pixclock = 41701,
- .left_margin = 20,
- .right_margin = 41,
- .upper_margin = 10,
- .lower_margin = 5,
- .hsync_len = 20,
- .vsync_len = 10,
- .sync = FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT,
- .vmode = FB_VMODE_NONINTERLACED,
- .flag = 0,
- },
-};
-
-static struct ipu_platform_data mx3_ipu_data = {
- .irq_base = MXC_IPU_IRQ_START,
-};
-
-static struct mx3fb_platform_data mx3fb_pdata = {
- .dma_dev = &mx3_ipu.dev,
- .name = "Epson-VGA",
- .mode = fb_modedb,
- .num_modes = ARRAY_SIZE(fb_modedb),
-};
-
-/* LCD */
-static struct l4f00242t03_pdata mx31_3ds_l4f00242t03_pdata = {
- .reset_gpio = IOMUX_TO_GPIO(MX31_PIN_LCS1),
- .data_enable_gpio = IOMUX_TO_GPIO(MX31_PIN_SER_RS),
- .core_supply = "lcd_2v8",
- .io_supply = "vdd_lcdio",
-};
-
-/*
- * Support for SD card slot in personality board
- */
-#define MX31_3DS_GPIO_SDHC1_CD IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)
-#define MX31_3DS_GPIO_SDHC1_BE IOMUX_TO_GPIO(MX31_PIN_GPIO3_0)
-
-static struct gpio mx31_3ds_sdhc1_gpios[] = {
- { MX31_3DS_GPIO_SDHC1_CD, GPIOF_IN, "sdhc1-card-detect" },
- { MX31_3DS_GPIO_SDHC1_BE, GPIOF_OUT_INIT_LOW, "sdhc1-bus-en" },
-};
-
-static int mx31_3ds_sdhc1_init(struct device *dev,
- irq_handler_t detect_irq,
- void *data)
-{
- int ret;
-
- ret = gpio_request_array(mx31_3ds_sdhc1_gpios,
- ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
- if (ret) {
- pr_warning("Unable to request the SD/MMC GPIOs.\n");
- return ret;
- }
-
- ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
- detect_irq, IRQF_DISABLED |
- IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
- "sdhc1-detect", data);
- if (ret) {
- pr_warning("Unable to request the SD/MMC card-detect IRQ.\n");
- goto gpio_free;
- }
-
- return 0;
-
-gpio_free:
- gpio_free_array(mx31_3ds_sdhc1_gpios,
- ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
- return ret;
-}
-
-static void mx31_3ds_sdhc1_exit(struct device *dev, void *data)
-{
- free_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO3_1), data);
- gpio_free_array(mx31_3ds_sdhc1_gpios,
- ARRAY_SIZE(mx31_3ds_sdhc1_gpios));
-}
-
-static void mx31_3ds_sdhc1_setpower(struct device *dev, unsigned int vdd)
-{
- /*
- * While the voltage stuff is done by the driver, activate the
- * Buffer Enable Pin only if there is a card in slot to fix the card
- * voltage issue caused by bi-directional chip TXB0108 on 3Stack.
- * Done here because at this stage we have for sure a debounced value
- * of the presence of the card, showed by the value of vdd.
- * 7 == ilog2(MMC_VDD_165_195)
- */
- if (vdd > 7)
- gpio_set_value(MX31_3DS_GPIO_SDHC1_BE, 1);
- else
- gpio_set_value(MX31_3DS_GPIO_SDHC1_BE, 0);
-}
-
-static struct imxmmc_platform_data sdhc1_pdata = {
- .init = mx31_3ds_sdhc1_init,
- .exit = mx31_3ds_sdhc1_exit,
- .setpower = mx31_3ds_sdhc1_setpower,
-};
-
-/*
- * Matrix keyboard
- */
-
-static const uint32_t mx31_3ds_keymap[] = {
- KEY(0, 0, KEY_UP),
- KEY(0, 1, KEY_DOWN),
- KEY(1, 0, KEY_RIGHT),
- KEY(1, 1, KEY_LEFT),
- KEY(1, 2, KEY_ENTER),
- KEY(2, 0, KEY_F6),
- KEY(2, 1, KEY_F8),
- KEY(2, 2, KEY_F9),
- KEY(2, 3, KEY_F10),
-};
-
-static const struct matrix_keymap_data mx31_3ds_keymap_data __initconst = {
- .keymap = mx31_3ds_keymap,
- .keymap_size = ARRAY_SIZE(mx31_3ds_keymap),
-};
-
-/* Regulators */
-static struct regulator_init_data pwgtx_init = {
- .constraints = {
- .boot_on = 1,
- .always_on = 1,
- },
-};
-
-static struct regulator_init_data gpo_init = {
- .constraints = {
- .boot_on = 1,
- .always_on = 1,
- }
-};
-
-static struct regulator_consumer_supply vmmc2_consumers[] = {
- REGULATOR_SUPPLY("vmmc", "mxc-mmc.0"),
-};
-
-static struct regulator_init_data vmmc2_init = {
- .constraints = {
- .min_uV = 3000000,
- .max_uV = 3000000,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
- REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = ARRAY_SIZE(vmmc2_consumers),
- .consumer_supplies = vmmc2_consumers,
-};
-
-static struct regulator_consumer_supply vmmc1_consumers[] = {
- REGULATOR_SUPPLY("lcd_2v8", NULL),
- REGULATOR_SUPPLY("cmos_2v8", "soc-camera-pdrv.0"),
-};
-
-static struct regulator_init_data vmmc1_init = {
- .constraints = {
- .min_uV = 2800000,
- .max_uV = 2800000,
- .apply_uV = 1,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
- REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = ARRAY_SIZE(vmmc1_consumers),
- .consumer_supplies = vmmc1_consumers,
-};
-
-static struct regulator_consumer_supply vgen_consumers[] = {
- REGULATOR_SUPPLY("vdd_lcdio", NULL),
-};
-
-static struct regulator_init_data vgen_init = {
- .constraints = {
- .min_uV = 1800000,
- .max_uV = 1800000,
- .apply_uV = 1,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
- REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = ARRAY_SIZE(vgen_consumers),
- .consumer_supplies = vgen_consumers,
-};
-
-static struct regulator_consumer_supply vvib_consumers[] = {
- REGULATOR_SUPPLY("cmos_vcore", "soc-camera-pdrv.0"),
-};
-
-static struct regulator_init_data vvib_init = {
- .constraints = {
- .min_uV = 1300000,
- .max_uV = 1300000,
- .apply_uV = 1,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
- REGULATOR_CHANGE_STATUS,
- },
- .num_consumer_supplies = ARRAY_SIZE(vvib_consumers),
- .consumer_supplies = vvib_consumers,
-};
-
-static struct mc13xxx_regulator_init_data mx31_3ds_regulators[] = {
- {
- .id = MC13783_REG_PWGT1SPI, /* Power Gate for ARM core. */
- .init_data = &pwgtx_init,
- }, {
- .id = MC13783_REG_PWGT2SPI, /* Power Gate for L2 Cache. */
- .init_data = &pwgtx_init,
- }, {
-
- .id = MC13783_REG_GPO1, /* Turn on 1.8V */
- .init_data = &gpo_init,
- }, {
- .id = MC13783_REG_GPO3, /* Turn on 3.3V */
- .init_data = &gpo_init,
- }, {
- .id = MC13783_REG_VMMC2, /* Power MMC/SD, WiFi/Bluetooth. */
- .init_data = &vmmc2_init,
- }, {
- .id = MC13783_REG_VMMC1, /* Power LCD, CMOS, FM, GPS, Accel. */
- .init_data = &vmmc1_init,
- }, {
- .id = MC13783_REG_VGEN, /* Power LCD */
- .init_data = &vgen_init,
- }, {
- .id = MC13783_REG_VVIB, /* Power CMOS */
- .init_data = &vvib_init,
- },
-};
-
-/* MC13783 */
-static struct mc13xxx_platform_data mc13783_pdata = {
- .regulators = {
- .regulators = mx31_3ds_regulators,
- .num_regulators = ARRAY_SIZE(mx31_3ds_regulators),
- },
- .flags = MC13783_USE_REGULATOR | MC13783_USE_TOUCHSCREEN,
-};
-
-/* SPI */
-static int spi0_internal_chipselect[] = {
- MXC_SPI_CS(2),
-};
-
-static const struct spi_imx_master spi0_pdata __initconst = {
- .chipselect = spi0_internal_chipselect,
- .num_chipselect = ARRAY_SIZE(spi0_internal_chipselect),
-};
-
-static int spi1_internal_chipselect[] = {
- MXC_SPI_CS(0),
- MXC_SPI_CS(2),
-};
-
-static const struct spi_imx_master spi1_pdata __initconst = {
- .chipselect = spi1_internal_chipselect,
- .num_chipselect = ARRAY_SIZE(spi1_internal_chipselect),
-};
-
-static struct spi_board_info mx31_3ds_spi_devs[] __initdata = {
- {
- .modalias = "mc13783",
- .max_speed_hz = 1000000,
- .bus_num = 1,
- .chip_select = 1, /* SS2 */
- .platform_data = &mc13783_pdata,
- .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
- .mode = SPI_CS_HIGH,
- }, {
- .modalias = "l4f00242t03",
- .max_speed_hz = 5000000,
- .bus_num = 0,
- .chip_select = 0, /* SS2 */
- .platform_data = &mx31_3ds_l4f00242t03_pdata,
- },
-};
-
-/*
- * NAND Flash
- */
-static const struct mxc_nand_platform_data
-mx31_3ds_nand_board_info __initconst = {
- .width = 1,
- .hw_ecc = 1,
-#ifdef MACH_MX31_3DS_MXC_NAND_USE_BBT
- .flash_bbt = 1,
-#endif
-};
-
-/*
- * USB OTG
- */
-
-#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
- PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
-
-#define USBOTG_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_PWR)
-#define USBH2_RST_B IOMUX_TO_GPIO(MX31_PIN_USB_BYP)
-
-static int mx31_3ds_usbotg_init(void)
-{
- int err;
-
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG);
-
- err = gpio_request(USBOTG_RST_B, "otgusb-reset");
- if (err) {
- pr_err("Failed to request the USB OTG reset gpio\n");
- return err;
- }
-
- err = gpio_direction_output(USBOTG_RST_B, 0);
- if (err) {
- pr_err("Failed to drive the USB OTG reset gpio\n");
- goto usbotg_free_reset;
- }
-
- mdelay(1);
- gpio_set_value(USBOTG_RST_B, 1);
- return 0;
-
-usbotg_free_reset:
- gpio_free(USBOTG_RST_B);
- return err;
-}
-
-static int mx31_3ds_otg_init(struct platform_device *pdev)
-{
- return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
-}
-
-static int mx31_3ds_host2_init(struct platform_device *pdev)
-{
- int err;
-
- mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_PC_VS2, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_PC_BVD1, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_PC_BVD2, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_PC_RST, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_IOIS16, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_PC_RW_B, USB_PAD_CFG);
-
- err = gpio_request(USBH2_RST_B, "usbh2-reset");
- if (err) {
- pr_err("Failed to request the USB Host 2 reset gpio\n");
- return err;
- }
-
- err = gpio_direction_output(USBH2_RST_B, 0);
- if (err) {
- pr_err("Failed to drive the USB Host 2 reset gpio\n");
- goto usbotg_free_reset;
- }
-
- mdelay(1);
- gpio_set_value(USBH2_RST_B, 1);
-
- mdelay(10);
-
- return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
-
-usbotg_free_reset:
- gpio_free(USBH2_RST_B);
- return err;
-}
-
-static struct mxc_usbh_platform_data otg_pdata __initdata = {
- .init = mx31_3ds_otg_init,
- .portsc = MXC_EHCI_MODE_ULPI,
-};
-
-static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
- .init = mx31_3ds_host2_init,
- .portsc = MXC_EHCI_MODE_ULPI,
-};
-
-static const struct fsl_usb2_platform_data usbotg_pdata __initconst = {
- .operating_mode = FSL_USB2_DR_DEVICE,
- .phy_mode = FSL_USB2_PHY_ULPI,
-};
-
-static int otg_mode_host;
-
-static int __init mx31_3ds_otg_mode(char *options)
-{
- if (!strcmp(options, "host"))
- otg_mode_host = 1;
- else if (!strcmp(options, "device"))
- otg_mode_host = 0;
- else
- pr_info("otg_mode neither \"host\" nor \"device\". "
- "Defaulting to device\n");
- return 0;
-}
-__setup("otg_mode=", mx31_3ds_otg_mode);
-
-static const struct imxuart_platform_data uart_pdata __initconst = {
- .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static const struct imxi2c_platform_data mx31_3ds_i2c0_data __initconst = {
- .bitrate = 100000,
-};
-
-static struct platform_device *devices[] __initdata = {
- &mx31_3ds_ov2640,
-};
-
-static void __init mx31_3ds_init(void)
-{
- int ret;
-
- mxc_iomux_setup_multiple_pins(mx31_3ds_pins, ARRAY_SIZE(mx31_3ds_pins),
- "mx31_3ds");
-
- imx31_add_imx_uart0(&uart_pdata);
- imx31_add_mxc_nand(&mx31_3ds_nand_board_info);
-
- imx31_add_spi_imx1(&spi1_pdata);
- spi_register_board_info(mx31_3ds_spi_devs,
- ARRAY_SIZE(mx31_3ds_spi_devs));
-
- platform_add_devices(devices, ARRAY_SIZE(devices));
-
- imx31_add_imx_keypad(&mx31_3ds_keymap_data);
-
- mx31_3ds_usbotg_init();
- if (otg_mode_host) {
- otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
- ULPI_OTG_DRVVBUS_EXT);
- if (otg_pdata.otg)
- imx31_add_mxc_ehci_otg(&otg_pdata);
- }
- usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
- ULPI_OTG_DRVVBUS_EXT);
- if (usbh2_pdata.otg)
- imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
-
- if (!otg_mode_host)
- imx31_add_fsl_usb2_udc(&usbotg_pdata);
-
- if (mxc_expio_init(MX31_CS5_BASE_ADDR, EXPIO_PARENT_INT))
- printk(KERN_WARNING "Init of the debug board failed, all "
- "devices on the debug board are unusable.\n");
- imx31_add_imx2_wdt(NULL);
- imx31_add_imx_i2c0(&mx31_3ds_i2c0_data);
- imx31_add_mxc_mmc(0, &sdhc1_pdata);
-
- imx31_add_spi_imx0(&spi0_pdata);
- mxc_register_device(&mx3_ipu, &mx3_ipu_data);
- mxc_register_device(&mx3_fb, &mx3fb_pdata);
-
- /* CSI */
- /* Camera power: default - off */
- ret = gpio_request_array(mx31_3ds_camera_gpios,
- ARRAY_SIZE(mx31_3ds_camera_gpios));
- if (ret) {
- pr_err("Failed to request camera gpios");
- iclink_ov2640.power = NULL;
- }
-
- if (!mx31_3ds_camera_alloc_dma())
- mxc_register_device(&mx3_camera, &mx31_3ds_camera_pdata);
- else
- pr_err("Failed to allocate dma memory for camera");
-}
-
-static void __init mx31_3ds_timer_init(void)
-{
- mx31_clocks_init(26000000);
-}
-
-static struct sys_timer mx31_3ds_timer = {
- .init = mx31_3ds_timer_init,
-};
-
-static void __init mx31_3ds_reserve(void)
-{
- /* reserve MX31_3DS_CAMERA_BUF_SIZE bytes for mx3-camera */
- mx3_camera_base = memblock_alloc(MX31_3DS_CAMERA_BUF_SIZE,
- MX31_3DS_CAMERA_BUF_SIZE);
- memblock_free(mx3_camera_base, MX31_3DS_CAMERA_BUF_SIZE);
- memblock_remove(mx3_camera_base, MX31_3DS_CAMERA_BUF_SIZE);
-}
-
-MACHINE_START(MX31_3DS, "Freescale MX31PDK (3DS)")
- /* Maintainer: Freescale Semiconductor, Inc. */
- .boot_params = MX3x_PHYS_OFFSET + 0x100,
- .map_io = mx31_map_io,
- .init_early = imx31_init_early,
- .init_irq = mx31_init_irq,
- .timer = &mx31_3ds_timer,
- .init_machine = mx31_3ds_init,
- .reserve = mx31_3ds_reserve,
-MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-mx31ads.c b/arch/arm/mach-mx3/mach-mx31ads.c
deleted file mode 100644
index 3d095d6..0000000
--- a/arch/arm/mach-mx3/mach-mx31ads.c
+++ /dev/null
@@ -1,543 +0,0 @@
-/*
- * Copyright (C) 2000 Deep Blue Solutions Ltd
- * Copyright (C) 2002 Shane Nay (shane@minirl.com)
- * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/clk.h>
-#include <linux/serial_8250.h>
-#include <linux/gpio.h>
-#include <linux/i2c.h>
-#include <linux/irq.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <asm/memory.h>
-#include <asm/mach/map.h>
-#include <mach/common.h>
-#include <mach/board-mx31ads.h>
-#include <mach/iomux-mx3.h>
-
-#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
-#include <linux/mfd/wm8350/audio.h>
-#include <linux/mfd/wm8350/core.h>
-#include <linux/mfd/wm8350/pmic.h>
-#endif
-
-#include "devices-imx31.h"
-#include "devices.h"
-
-/* PBC Board interrupt status register */
-#define PBC_INTSTATUS 0x000016
-
-/* PBC Board interrupt current status register */
-#define PBC_INTCURR_STATUS 0x000018
-
-/* PBC Interrupt mask register set address */
-#define PBC_INTMASK_SET 0x00001A
-
-/* PBC Interrupt mask register clear address */
-#define PBC_INTMASK_CLEAR 0x00001C
-
-/* External UART A */
-#define PBC_SC16C652_UARTA 0x010000
-
-/* External UART B */
-#define PBC_SC16C652_UARTB 0x010010
-
-#define PBC_INTSTATUS_REG (PBC_INTSTATUS + PBC_BASE_ADDRESS)
-#define PBC_INTMASK_SET_REG (PBC_INTMASK_SET + PBC_BASE_ADDRESS)
-#define PBC_INTMASK_CLEAR_REG (PBC_INTMASK_CLEAR + PBC_BASE_ADDRESS)
-#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX31_PIN_GPIO1_4)
-
-#define MXC_IRQ_TO_EXPIO(irq) ((irq) - MXC_EXP_IO_BASE)
-
-#define EXPIO_INT_XUART_INTA (MXC_EXP_IO_BASE + 10)
-#define EXPIO_INT_XUART_INTB (MXC_EXP_IO_BASE + 11)
-
-#define MXC_MAX_EXP_IO_LINES 16
-
-/*
- * The serial port definition structure.
- */
-static struct plat_serial8250_port serial_platform_data[] = {
- {
- .membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTA),
- .mapbase = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTA),
- .irq = EXPIO_INT_XUART_INTA,
- .uartclk = 14745600,
- .regshift = 0,
- .iotype = UPIO_MEM,
- .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
- }, {
- .membase = (void *)(PBC_BASE_ADDRESS + PBC_SC16C652_UARTB),
- .mapbase = (unsigned long)(MX31_CS4_BASE_ADDR + PBC_SC16C652_UARTB),
- .irq = EXPIO_INT_XUART_INTB,
- .uartclk = 14745600,
- .regshift = 0,
- .iotype = UPIO_MEM,
- .flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_AUTO_IRQ,
- },
- {},
-};
-
-static struct platform_device serial_device = {
- .name = "serial8250",
- .id = 0,
- .dev = {
- .platform_data = serial_platform_data,
- },
-};
-
-static int __init mxc_init_extuart(void)
-{
- return platform_device_register(&serial_device);
-}
-
-static const struct imxuart_platform_data uart_pdata __initconst = {
- .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static unsigned int uart_pins[] = {
- MX31_PIN_CTS1__CTS1,
- MX31_PIN_RTS1__RTS1,
- MX31_PIN_TXD1__TXD1,
- MX31_PIN_RXD1__RXD1
-};
-
-static inline void mxc_init_imx_uart(void)
-{
- mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins), "uart-0");
- imx31_add_imx_uart0(&uart_pdata);
-}
-
-static void mx31ads_expio_irq_handler(u32 irq, struct irq_desc *desc)
-{
- u32 imr_val;
- u32 int_valid;
- u32 expio_irq;
-
- imr_val = __raw_readw(PBC_INTMASK_SET_REG);
- int_valid = __raw_readw(PBC_INTSTATUS_REG) & imr_val;
-
- expio_irq = MXC_EXP_IO_BASE;
- for (; int_valid != 0; int_valid >>= 1, expio_irq++) {
- if ((int_valid & 1) == 0)
- continue;
-
- generic_handle_irq(expio_irq);
- }
-}
-
-/*
- * Disable an expio pin's interrupt by setting the bit in the imr.
- * @param d an expio virtual irq description
- */
-static void expio_mask_irq(struct irq_data *d)
-{
- u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
- /* mask the interrupt */
- __raw_writew(1 << expio, PBC_INTMASK_CLEAR_REG);
- __raw_readw(PBC_INTMASK_CLEAR_REG);
-}
-
-/*
- * Acknowledge an expanded io pin's interrupt by clearing the bit in the isr.
- * @param d an expio virtual irq description
- */
-static void expio_ack_irq(struct irq_data *d)
-{
- u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
- /* clear the interrupt status */
- __raw_writew(1 << expio, PBC_INTSTATUS_REG);
-}
-
-/*
- * Enable a expio pin's interrupt by clearing the bit in the imr.
- * @param d an expio virtual irq description
- */
-static void expio_unmask_irq(struct irq_data *d)
-{
- u32 expio = MXC_IRQ_TO_EXPIO(d->irq);
- /* unmask the interrupt */
- __raw_writew(1 << expio, PBC_INTMASK_SET_REG);
-}
-
-static struct irq_chip expio_irq_chip = {
- .name = "EXPIO(CPLD)",
- .irq_ack = expio_ack_irq,
- .irq_mask = expio_mask_irq,
- .irq_unmask = expio_unmask_irq,
-};
-
-static void __init mx31ads_init_expio(void)
-{
- int i;
-
- printk(KERN_INFO "MX31ADS EXPIO(CPLD) hardware\n");
-
- /*
- * Configure INT line as GPIO input
- */
- mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_GPIO1_4, IOMUX_CONFIG_GPIO), "expio");
-
- /* disable the interrupt and clear the status */
- __raw_writew(0xFFFF, PBC_INTMASK_CLEAR_REG);
- __raw_writew(0xFFFF, PBC_INTSTATUS_REG);
- for (i = MXC_EXP_IO_BASE; i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
- i++) {
- irq_set_chip_and_handler(i, &expio_irq_chip, handle_level_irq);
- set_irq_flags(i, IRQF_VALID);
- }
- irq_set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_HIGH);
- irq_set_chained_handler(EXPIO_PARENT_INT, mx31ads_expio_irq_handler);
-}
-
-#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
-/* This section defines setup for the Wolfson Microelectronics
- * 1133-EV1 PMU/audio board. When other PMU boards are supported the
- * regulator definitions may be shared with them, but for now they can
- * only be used with this board so would generate warnings about
- * unused statics and some of the configuration is specific to this
- * module.
- */
-
-/* CPU */
-static struct regulator_consumer_supply sw1a_consumers[] = {
- {
- .supply = "cpu_vcc",
- }
-};
-
-static struct regulator_init_data sw1a_data = {
- .constraints = {
- .name = "SW1A",
- .min_uV = 1275000,
- .max_uV = 1600000,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
- REGULATOR_CHANGE_MODE,
- .valid_modes_mask = REGULATOR_MODE_NORMAL |
- REGULATOR_MODE_FAST,
- .state_mem = {
- .uV = 1400000,
- .mode = REGULATOR_MODE_NORMAL,
- .enabled = 1,
- },
- .initial_state = PM_SUSPEND_MEM,
- .always_on = 1,
- .boot_on = 1,
- },
- .num_consumer_supplies = ARRAY_SIZE(sw1a_consumers),
- .consumer_supplies = sw1a_consumers,
-};
-
-/* System IO - High */
-static struct regulator_init_data viohi_data = {
- .constraints = {
- .name = "VIOHO",
- .min_uV = 2800000,
- .max_uV = 2800000,
- .state_mem = {
- .uV = 2800000,
- .mode = REGULATOR_MODE_NORMAL,
- .enabled = 1,
- },
- .initial_state = PM_SUSPEND_MEM,
- .always_on = 1,
- .boot_on = 1,
- },
-};
-
-/* System IO - Low */
-static struct regulator_init_data violo_data = {
- .constraints = {
- .name = "VIOLO",
- .min_uV = 1800000,
- .max_uV = 1800000,
- .state_mem = {
- .uV = 1800000,
- .mode = REGULATOR_MODE_NORMAL,
- .enabled = 1,
- },
- .initial_state = PM_SUSPEND_MEM,
- .always_on = 1,
- .boot_on = 1,
- },
-};
-
-/* DDR RAM */
-static struct regulator_init_data sw2a_data = {
- .constraints = {
- .name = "SW2A",
- .min_uV = 1800000,
- .max_uV = 1800000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL,
- .state_mem = {
- .uV = 1800000,
- .mode = REGULATOR_MODE_NORMAL,
- .enabled = 1,
- },
- .state_disk = {
- .mode = REGULATOR_MODE_NORMAL,
- .enabled = 0,
- },
- .always_on = 1,
- .boot_on = 1,
- .initial_state = PM_SUSPEND_MEM,
- },
-};
-
-static struct regulator_init_data ldo1_data = {
- .constraints = {
- .name = "VCAM/VMMC1/VMMC2",
- .min_uV = 2800000,
- .max_uV = 2800000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS,
- .apply_uV = 1,
- },
-};
-
-static struct regulator_consumer_supply ldo2_consumers[] = {
- { .supply = "AVDD", .dev_name = "1-001a" },
- { .supply = "HPVDD", .dev_name = "1-001a" },
-};
-
-/* CODEC and SIM */
-static struct regulator_init_data ldo2_data = {
- .constraints = {
- .name = "VESIM/VSIM/AVDD",
- .min_uV = 3300000,
- .max_uV = 3300000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL,
- .valid_ops_mask = REGULATOR_CHANGE_STATUS,
- .apply_uV = 1,
- },
- .num_consumer_supplies = ARRAY_SIZE(ldo2_consumers),
- .consumer_supplies = ldo2_consumers,
-};
-
-/* General */
-static struct regulator_init_data vdig_data = {
- .constraints = {
- .name = "VDIG",
- .min_uV = 1500000,
- .max_uV = 1500000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL,
- .apply_uV = 1,
- .always_on = 1,
- .boot_on = 1,
- },
-};
-
-/* Tranceivers */
-static struct regulator_init_data ldo4_data = {
- .constraints = {
- .name = "VRF1/CVDD_2.775",
- .min_uV = 2500000,
- .max_uV = 2500000,
- .valid_modes_mask = REGULATOR_MODE_NORMAL,
- .apply_uV = 1,
- .always_on = 1,
- .boot_on = 1,
- },
-};
-
-static struct wm8350_led_platform_data wm8350_led_data = {
- .name = "wm8350:white",
- .default_trigger = "heartbeat",
- .max_uA = 27899,
-};
-
-static struct wm8350_audio_platform_data imx32ads_wm8350_setup = {
- .vmid_discharge_msecs = 1000,
- .drain_msecs = 30,
- .cap_discharge_msecs = 700,
- .vmid_charge_msecs = 700,
- .vmid_s_curve = WM8350_S_CURVE_SLOW,
- .dis_out4 = WM8350_DISCHARGE_SLOW,
- .dis_out3 = WM8350_DISCHARGE_SLOW,
- .dis_out2 = WM8350_DISCHARGE_SLOW,
- .dis_out1 = WM8350_DISCHARGE_SLOW,
- .vroi_out4 = WM8350_TIE_OFF_500R,
- .vroi_out3 = WM8350_TIE_OFF_500R,
- .vroi_out2 = WM8350_TIE_OFF_500R,
- .vroi_out1 = WM8350_TIE_OFF_500R,
- .vroi_enable = 0,
- .codec_current_on = WM8350_CODEC_ISEL_1_0,
- .codec_current_standby = WM8350_CODEC_ISEL_0_5,
- .codec_current_charge = WM8350_CODEC_ISEL_1_5,
-};
-
-static int mx31_wm8350_init(struct wm8350 *wm8350)
-{
- wm8350_gpio_config(wm8350, 0, WM8350_GPIO_DIR_IN,
- WM8350_GPIO0_PWR_ON_IN, WM8350_GPIO_ACTIVE_LOW,
- WM8350_GPIO_PULL_UP, WM8350_GPIO_INVERT_OFF,
- WM8350_GPIO_DEBOUNCE_ON);
-
- wm8350_gpio_config(wm8350, 3, WM8350_GPIO_DIR_IN,
- WM8350_GPIO3_PWR_OFF_IN, WM8350_GPIO_ACTIVE_HIGH,
- WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
- WM8350_GPIO_DEBOUNCE_ON);
-
- wm8350_gpio_config(wm8350, 4, WM8350_GPIO_DIR_IN,
- WM8350_GPIO4_MR_IN, WM8350_GPIO_ACTIVE_HIGH,
- WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
- WM8350_GPIO_DEBOUNCE_OFF);
-
- wm8350_gpio_config(wm8350, 7, WM8350_GPIO_DIR_IN,
- WM8350_GPIO7_HIBERNATE_IN, WM8350_GPIO_ACTIVE_HIGH,
- WM8350_GPIO_PULL_DOWN, WM8350_GPIO_INVERT_OFF,
- WM8350_GPIO_DEBOUNCE_OFF);
-
- wm8350_gpio_config(wm8350, 6, WM8350_GPIO_DIR_OUT,
- WM8350_GPIO6_SDOUT_OUT, WM8350_GPIO_ACTIVE_HIGH,
- WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
- WM8350_GPIO_DEBOUNCE_OFF);
-
- wm8350_gpio_config(wm8350, 8, WM8350_GPIO_DIR_OUT,
- WM8350_GPIO8_VCC_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW,
- WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
- WM8350_GPIO_DEBOUNCE_OFF);
-
- wm8350_gpio_config(wm8350, 9, WM8350_GPIO_DIR_OUT,
- WM8350_GPIO9_BATT_FAULT_OUT, WM8350_GPIO_ACTIVE_LOW,
- WM8350_GPIO_PULL_NONE, WM8350_GPIO_INVERT_OFF,
- WM8350_GPIO_DEBOUNCE_OFF);
-
- wm8350_register_regulator(wm8350, WM8350_DCDC_1, &sw1a_data);
- wm8350_register_regulator(wm8350, WM8350_DCDC_3, &viohi_data);
- wm8350_register_regulator(wm8350, WM8350_DCDC_4, &violo_data);
- wm8350_register_regulator(wm8350, WM8350_DCDC_6, &sw2a_data);
- wm8350_register_regulator(wm8350, WM8350_LDO_1, &ldo1_data);
- wm8350_register_regulator(wm8350, WM8350_LDO_2, &ldo2_data);
- wm8350_register_regulator(wm8350, WM8350_LDO_3, &vdig_data);
- wm8350_register_regulator(wm8350, WM8350_LDO_4, &ldo4_data);
-
- /* LEDs */
- wm8350_dcdc_set_slot(wm8350, WM8350_DCDC_5, 1, 1,
- WM8350_DC5_ERRACT_SHUTDOWN_CONV);
- wm8350_isink_set_flash(wm8350, WM8350_ISINK_A,
- WM8350_ISINK_FLASH_DISABLE,
- WM8350_ISINK_FLASH_TRIG_BIT,
- WM8350_ISINK_FLASH_DUR_32MS,
- WM8350_ISINK_FLASH_ON_INSTANT,
- WM8350_ISINK_FLASH_OFF_INSTANT,
- WM8350_ISINK_FLASH_MODE_EN);
- wm8350_dcdc25_set_mode(wm8350, WM8350_DCDC_5,
- WM8350_ISINK_MODE_BOOST,
- WM8350_ISINK_ILIM_NORMAL,
- WM8350_DC5_RMP_20V,
- WM8350_DC5_FBSRC_ISINKA);
- wm8350_register_led(wm8350, 0, WM8350_DCDC_5, WM8350_ISINK_A,
- &wm8350_led_data);
-
- wm8350->codec.platform_data = &imx32ads_wm8350_setup;
-
- regulator_has_full_constraints();
-
- return 0;
-}
-
-static struct wm8350_platform_data __initdata mx31_wm8350_pdata = {
- .init = mx31_wm8350_init,
- .irq_base = MXC_BOARD_IRQ_START + MXC_MAX_EXP_IO_LINES,
-};
-#endif
-
-static struct i2c_board_info __initdata mx31ads_i2c1_devices[] = {
-#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
- {
- I2C_BOARD_INFO("wm8350", 0x1a),
- .platform_data = &mx31_wm8350_pdata,
- .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
- },
-#endif
-};
-
-static void mxc_init_i2c(void)
-{
- i2c_register_board_info(1, mx31ads_i2c1_devices,
- ARRAY_SIZE(mx31ads_i2c1_devices));
-
- mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MOSI, IOMUX_CONFIG_ALT1));
- mxc_iomux_mode(IOMUX_MODE(MX31_PIN_CSPI2_MISO, IOMUX_CONFIG_ALT1));
-
- imx31_add_imx_i2c1(NULL);
-}
-
-static unsigned int ssi_pins[] = {
- MX31_PIN_SFS5__SFS5,
- MX31_PIN_SCK5__SCK5,
- MX31_PIN_SRXD5__SRXD5,
- MX31_PIN_STXD5__STXD5,
-};
-
-static void mxc_init_audio(void)
-{
- imx31_add_imx_ssi(0, NULL);
- mxc_iomux_setup_multiple_pins(ssi_pins, ARRAY_SIZE(ssi_pins), "ssi");
-}
-
-/* static mappings */
-static struct map_desc mx31ads_io_desc[] __initdata = {
- {
- .virtual = MX31_CS4_BASE_ADDR_VIRT,
- .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
- .length = MX31_CS4_SIZE / 2,
- .type = MT_DEVICE
- },
-};
-
-static void __init mx31ads_map_io(void)
-{
- mx31_map_io();
- iotable_init(mx31ads_io_desc, ARRAY_SIZE(mx31ads_io_desc));
-}
-
-static void __init mx31ads_init_irq(void)
-{
- mx31_init_irq();
- mx31ads_init_expio();
-}
-
-static void __init mx31ads_init(void)
-{
- mxc_init_extuart();
- mxc_init_imx_uart();
- mxc_init_i2c();
- mxc_init_audio();
-}
-
-static void __init mx31ads_timer_init(void)
-{
- mx31_clocks_init(26000000);
-}
-
-static struct sys_timer mx31ads_timer = {
- .init = mx31ads_timer_init,
-};
-
-MACHINE_START(MX31ADS, "Freescale MX31ADS")
- /* Maintainer: Freescale Semiconductor, Inc. */
- .boot_params = MX3x_PHYS_OFFSET + 0x100,
- .map_io = mx31ads_map_io,
- .init_early = imx31_init_early,
- .init_irq = mx31ads_init_irq,
- .timer = &mx31ads_timer,
- .init_machine = mx31ads_init,
-MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-mx31lilly.c b/arch/arm/mach-mx3/mach-mx31lilly.c
deleted file mode 100644
index ed95745..0000000
--- a/arch/arm/mach-mx3/mach-mx31lilly.c
+++ /dev/null
@@ -1,303 +0,0 @@
-/*
- * LILLY-1131 module support
- *
- * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
- *
- * based on code for other MX31 boards,
- *
- * Copyright 2005-2007 Freescale Semiconductor
- * Copyright (c) 2009 Alberto Panizzo <maramaopercheseimorto@gmail.com>
- * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/clk.h>
-#include <linux/gpio.h>
-#include <linux/delay.h>
-#include <linux/platform_device.h>
-#include <linux/interrupt.h>
-#include <linux/smsc911x.h>
-#include <linux/mtd/physmap.h>
-#include <linux/spi/spi.h>
-#include <linux/mfd/mc13783.h>
-#include <linux/usb/otg.h>
-#include <linux/usb/ulpi.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <asm/mach/map.h>
-
-#include <mach/hardware.h>
-#include <mach/common.h>
-#include <mach/iomux-mx3.h>
-#include <mach/board-mx31lilly.h>
-#include <mach/ulpi.h>
-
-#include "devices-imx31.h"
-#include "devices.h"
-
-/*
- * This file contains module-specific initialization routines for LILLY-1131.
- * Initialization of peripherals found on the baseboard is implemented in the
- * appropriate baseboard support code.
- */
-
-/* SMSC ethernet support */
-
-static struct resource smsc91x_resources[] = {
- {
- .start = MX31_CS4_BASE_ADDR,
- .end = MX31_CS4_BASE_ADDR + 0xffff,
- .flags = IORESOURCE_MEM,
- },
- {
- .start = IOMUX_TO_IRQ(MX31_PIN_GPIO1_0),
- .end = IOMUX_TO_IRQ(MX31_PIN_GPIO1_0),
- .flags = IORESOURCE_IRQ | IRQF_TRIGGER_FALLING,
- }
-};
-
-static struct smsc911x_platform_config smsc911x_config = {
- .phy_interface = PHY_INTERFACE_MODE_MII,
- .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
- .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
- .flags = SMSC911X_USE_32BIT |
- SMSC911X_SAVE_MAC_ADDRESS |
- SMSC911X_FORCE_INTERNAL_PHY,
-};
-
-static struct platform_device smsc91x_device = {
- .name = "smsc911x",
- .id = -1,
- .num_resources = ARRAY_SIZE(smsc91x_resources),
- .resource = smsc91x_resources,
- .dev = {
- .platform_data = &smsc911x_config,
- }
-};
-
-/* NOR flash */
-static struct physmap_flash_data nor_flash_data = {
- .width = 2,
-};
-
-static struct resource nor_flash_resource = {
- .start = 0xa0000000,
- .end = 0xa1ffffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device physmap_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &nor_flash_data,
- },
- .resource = &nor_flash_resource,
- .num_resources = 1,
-};
-
-/* USB */
-
-#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
- PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
-
-static int usbh1_init(struct platform_device *pdev)
-{
- int pins[] = {
- MX31_PIN_CSPI1_MOSI__USBH1_RXDM,
- MX31_PIN_CSPI1_MISO__USBH1_RXDP,
- MX31_PIN_CSPI1_SS0__USBH1_TXDM,
- MX31_PIN_CSPI1_SS1__USBH1_TXDP,
- MX31_PIN_CSPI1_SS2__USBH1_RCV,
- MX31_PIN_CSPI1_SCLK__USBH1_OEB,
- MX31_PIN_CSPI1_SPI_RDY__USBH1_FS,
- };
-
- mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB H1");
-
- mxc_iomux_set_pad(MX31_PIN_CSPI1_MOSI, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_CSPI1_MISO, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_CSPI1_SS0, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_CSPI1_SS1, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_CSPI1_SS2, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_CSPI1_SCLK, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, USB_PAD_CFG);
-
- mxc_iomux_set_gpr(MUX_PGP_USB_SUSPEND, true);
-
- mdelay(10);
-
- return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED |
- MXC_EHCI_INTERFACE_SINGLE_UNI);
-}
-
-static int usbh2_init(struct platform_device *pdev)
-{
- int pins[] = {
- MX31_PIN_USBH2_DATA0__USBH2_DATA0,
- MX31_PIN_USBH2_DATA1__USBH2_DATA1,
- MX31_PIN_USBH2_CLK__USBH2_CLK,
- MX31_PIN_USBH2_DIR__USBH2_DIR,
- MX31_PIN_USBH2_NXT__USBH2_NXT,
- MX31_PIN_USBH2_STP__USBH2_STP,
- };
-
- mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB H2");
-
- mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG);
-
- mxc_iomux_set_gpr(MUX_PGP_UH2, true);
-
- /* chip select */
- mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_GPIO),
- "USBH2_CS");
- gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), "USBH2 CS");
- gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), 0);
-
- mdelay(10);
-
- return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
-}
-
-static const struct mxc_usbh_platform_data usbh1_pdata __initconst = {
- .init = usbh1_init,
- .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL,
-};
-
-static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
- .init = usbh2_init,
- .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
-};
-
-static void lilly1131_usb_init(void)
-{
- imx31_add_mxc_ehci_hs(1, &usbh1_pdata);
-
- usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
- ULPI_OTG_DRVVBUS_EXT);
- if (usbh2_pdata.otg)
- imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
-}
-
-/* SPI */
-
-static int spi_internal_chipselect[] = {
- MXC_SPI_CS(0),
- MXC_SPI_CS(1),
- MXC_SPI_CS(2),
-};
-
-static const struct spi_imx_master spi0_pdata __initconst = {
- .chipselect = spi_internal_chipselect,
- .num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
-};
-
-static const struct spi_imx_master spi1_pdata __initconst = {
- .chipselect = spi_internal_chipselect,
- .num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
-};
-
-static struct mc13xxx_platform_data mc13783_pdata __initdata = {
- .flags = MC13XXX_USE_RTC | MC13XXX_USE_TOUCHSCREEN,
-};
-
-static struct spi_board_info mc13783_dev __initdata = {
- .modalias = "mc13783",
- .max_speed_hz = 1000000,
- .bus_num = 1,
- .chip_select = 0,
- .platform_data = &mc13783_pdata,
- .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
-};
-
-static struct platform_device *devices[] __initdata = {
- &smsc91x_device,
- &physmap_flash_device,
-};
-
-static int mx31lilly_baseboard;
-core_param(mx31lilly_baseboard, mx31lilly_baseboard, int, 0444);
-
-static void __init mx31lilly_board_init(void)
-{
- switch (mx31lilly_baseboard) {
- case MX31LILLY_NOBOARD:
- break;
- case MX31LILLY_DB:
- mx31lilly_db_init();
- break;
- default:
- printk(KERN_ERR "Illegal mx31lilly_baseboard type %d\n",
- mx31lilly_baseboard);
- }
-
- mxc_iomux_alloc_pin(MX31_PIN_CS4__CS4, "Ethernet CS");
-
- /* SPI */
- mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SCLK__SCLK, "SPI1_CLK");
- mxc_iomux_alloc_pin(MX31_PIN_CSPI1_MOSI__MOSI, "SPI1_TX");
- mxc_iomux_alloc_pin(MX31_PIN_CSPI1_MISO__MISO, "SPI1_RX");
- mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SPI_RDY__SPI_RDY, "SPI1_RDY");
- mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SS0__SS0, "SPI1_SS0");
- mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SS1__SS1, "SPI1_SS1");
- mxc_iomux_alloc_pin(MX31_PIN_CSPI1_SS2__SS2, "SPI1_SS2");
-
- mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SCLK__SCLK, "SPI2_CLK");
- mxc_iomux_alloc_pin(MX31_PIN_CSPI2_MOSI__MOSI, "SPI2_TX");
- mxc_iomux_alloc_pin(MX31_PIN_CSPI2_MISO__MISO, "SPI2_RX");
- mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SPI_RDY__SPI_RDY, "SPI2_RDY");
- mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS0__SS0, "SPI2_SS0");
- mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS1__SS1, "SPI2_SS1");
- mxc_iomux_alloc_pin(MX31_PIN_CSPI2_SS2__SS2, "SPI2_SS2");
-
- imx31_add_spi_imx0(&spi0_pdata);
- imx31_add_spi_imx1(&spi1_pdata);
- spi_register_board_info(&mc13783_dev, 1);
-
- platform_add_devices(devices, ARRAY_SIZE(devices));
-
- /* USB */
- lilly1131_usb_init();
-}
-
-static void __init mx31lilly_timer_init(void)
-{
- mx31_clocks_init(26000000);
-}
-
-static struct sys_timer mx31lilly_timer = {
- .init = mx31lilly_timer_init,
-};
-
-MACHINE_START(LILLY1131, "INCO startec LILLY-1131")
- .boot_params = MX3x_PHYS_OFFSET + 0x100,
- .map_io = mx31_map_io,
- .init_early = imx31_init_early,
- .init_irq = mx31_init_irq,
- .timer = &mx31lilly_timer,
- .init_machine = mx31lilly_board_init,
-MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-mx31lite.c b/arch/arm/mach-mx3/mach-mx31lite.c
deleted file mode 100644
index 24a21a3..0000000
--- a/arch/arm/mach-mx3/mach-mx31lite.c
+++ /dev/null
@@ -1,288 +0,0 @@
-/*
- * Copyright (C) 2000 Deep Blue Solutions Ltd
- * Copyright (C) 2002 Shane Nay (shane@minirl.com)
- * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (C) 2009 Daniel Mack <daniel@caiaq.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/memory.h>
-#include <linux/platform_device.h>
-#include <linux/gpio.h>
-#include <linux/smsc911x.h>
-#include <linux/mfd/mc13783.h>
-#include <linux/spi/spi.h>
-#include <linux/usb/otg.h>
-#include <linux/usb/ulpi.h>
-#include <linux/mtd/physmap.h>
-#include <linux/delay.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <asm/mach/map.h>
-#include <asm/page.h>
-#include <asm/setup.h>
-
-#include <mach/hardware.h>
-#include <mach/common.h>
-#include <mach/board-mx31lite.h>
-#include <mach/iomux-mx3.h>
-#include <mach/irqs.h>
-#include <mach/ulpi.h>
-
-#include "devices-imx31.h"
-#include "devices.h"
-
-/*
- * This file contains the module-specific initialization routines.
- */
-
-static unsigned int mx31lite_pins[] = {
- /* LAN9117 IRQ pin */
- IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO),
- /* SPI 1 */
- MX31_PIN_CSPI2_SCLK__SCLK,
- MX31_PIN_CSPI2_MOSI__MOSI,
- MX31_PIN_CSPI2_MISO__MISO,
- MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
- MX31_PIN_CSPI2_SS0__SS0,
- MX31_PIN_CSPI2_SS1__SS1,
- MX31_PIN_CSPI2_SS2__SS2,
-};
-
-static const struct mxc_nand_platform_data
-mx31lite_nand_board_info __initconst = {
- .width = 1,
- .hw_ecc = 1,
-};
-
-static struct smsc911x_platform_config smsc911x_config = {
- .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
- .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
- .flags = SMSC911X_USE_16BIT,
-};
-
-static struct resource smsc911x_resources[] = {
- {
- .start = MX31_CS4_BASE_ADDR,
- .end = MX31_CS4_BASE_ADDR + 0x100,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IOMUX_TO_IRQ(MX31_PIN_SFS6),
- .end = IOMUX_TO_IRQ(MX31_PIN_SFS6),
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device smsc911x_device = {
- .name = "smsc911x",
- .id = -1,
- .num_resources = ARRAY_SIZE(smsc911x_resources),
- .resource = smsc911x_resources,
- .dev = {
- .platform_data = &smsc911x_config,
- },
-};
-
-/*
- * SPI
- *
- * The MC13783 is the only hard-wired SPI device on the module.
- */
-
-static int spi_internal_chipselect[] = {
- MXC_SPI_CS(0),
-};
-
-static const struct spi_imx_master spi1_pdata __initconst = {
- .chipselect = spi_internal_chipselect,
- .num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
-};
-
-static struct mc13xxx_platform_data mc13783_pdata __initdata = {
- .flags = MC13XXX_USE_RTC |
- MC13XXX_USE_REGULATOR,
-};
-
-static struct spi_board_info mc13783_spi_dev __initdata = {
- .modalias = "mc13783",
- .max_speed_hz = 1000000,
- .bus_num = 1,
- .chip_select = 0,
- .platform_data = &mc13783_pdata,
- .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
-};
-
-/*
- * USB
- */
-
-#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
- PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
-
-static int usbh2_init(struct platform_device *pdev)
-{
- int pins[] = {
- MX31_PIN_USBH2_DATA0__USBH2_DATA0,
- MX31_PIN_USBH2_DATA1__USBH2_DATA1,
- MX31_PIN_USBH2_CLK__USBH2_CLK,
- MX31_PIN_USBH2_DIR__USBH2_DIR,
- MX31_PIN_USBH2_NXT__USBH2_NXT,
- MX31_PIN_USBH2_STP__USBH2_STP,
- };
-
- mxc_iomux_setup_multiple_pins(pins, ARRAY_SIZE(pins), "USB H2");
-
- mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG);
-
- mxc_iomux_set_gpr(MUX_PGP_UH2, true);
-
- /* chip select */
- mxc_iomux_alloc_pin(IOMUX_MODE(MX31_PIN_DTR_DCE1, IOMUX_CONFIG_GPIO),
- "USBH2_CS");
- gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), "USBH2 CS");
- gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), 0);
-
- mdelay(10);
-
- return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
-}
-
-static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
- .init = usbh2_init,
- .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
-};
-
-/*
- * NOR flash
- */
-
-static struct physmap_flash_data nor_flash_data = {
- .width = 2,
-};
-
-static struct resource nor_flash_resource = {
- .start = 0xa0000000,
- .end = 0xa1ffffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device physmap_flash_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &nor_flash_data,
- },
- .resource = &nor_flash_resource,
- .num_resources = 1,
-};
-
-
-
-/*
- * This structure defines the MX31 memory map.
- */
-static struct map_desc mx31lite_io_desc[] __initdata = {
- {
- .virtual = MX31_CS4_BASE_ADDR_VIRT,
- .pfn = __phys_to_pfn(MX31_CS4_BASE_ADDR),
- .length = MX31_CS4_SIZE,
- .type = MT_DEVICE
- }
-};
-
-/*
- * Set up static virtual mappings.
- */
-void __init mx31lite_map_io(void)
-{
- mx31_map_io();
- iotable_init(mx31lite_io_desc, ARRAY_SIZE(mx31lite_io_desc));
-}
-
-static int mx31lite_baseboard;
-core_param(mx31lite_baseboard, mx31lite_baseboard, int, 0444);
-
-static void __init mx31lite_init(void)
-{
- int ret;
-
- switch (mx31lite_baseboard) {
- case MX31LITE_NOBOARD:
- break;
- case MX31LITE_DB:
- mx31lite_db_init();
- break;
- default:
- printk(KERN_ERR "Illegal mx31lite_baseboard type %d\n",
- mx31lite_baseboard);
- }
-
- mxc_iomux_setup_multiple_pins(mx31lite_pins, ARRAY_SIZE(mx31lite_pins),
- "mx31lite");
-
- /* NOR and NAND flash */
- platform_device_register(&physmap_flash_device);
- imx31_add_mxc_nand(&mx31lite_nand_board_info);
-
- imx31_add_spi_imx1(&spi1_pdata);
- spi_register_board_info(&mc13783_spi_dev, 1);
-
- /* USB */
- usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
- ULPI_OTG_DRVVBUS_EXT);
- if (usbh2_pdata.otg)
- imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
-
- /* SMSC9117 IRQ pin */
- ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_SFS6), "sms9117-irq");
- if (ret)
- pr_warning("could not get LAN irq gpio\n");
- else {
- gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_SFS6));
- platform_device_register(&smsc911x_device);
- }
-}
-
-static void __init mx31lite_timer_init(void)
-{
- mx31_clocks_init(26000000);
-}
-
-struct sys_timer mx31lite_timer = {
- .init = mx31lite_timer_init,
-};
-
-MACHINE_START(MX31LITE, "LogicPD i.MX31 SOM")
- /* Maintainer: Freescale Semiconductor, Inc. */
- .boot_params = MX3x_PHYS_OFFSET + 0x100,
- .map_io = mx31lite_map_io,
- .init_early = imx31_init_early,
- .init_irq = mx31_init_irq,
- .timer = &mx31lite_timer,
- .init_machine = mx31lite_init,
-MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-mx31moboard.c b/arch/arm/mach-mx3/mach-mx31moboard.c
deleted file mode 100644
index 3a021b0..0000000
--- a/arch/arm/mach-mx3/mach-mx31moboard.c
+++ /dev/null
@@ -1,576 +0,0 @@
-/*
- * Copyright (C) 2008 Valentin Longchamp, EPFL Mobots group
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/delay.h>
-#include <linux/dma-mapping.h>
-#include <linux/gfp.h>
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/leds.h>
-#include <linux/memory.h>
-#include <linux/mtd/physmap.h>
-#include <linux/mtd/partitions.h>
-#include <linux/platform_device.h>
-#include <linux/regulator/machine.h>
-#include <linux/mfd/mc13783.h>
-#include <linux/spi/spi.h>
-#include <linux/types.h>
-
-#include <linux/usb/otg.h>
-#include <linux/usb/ulpi.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <asm/mach/map.h>
-#include <mach/board-mx31moboard.h>
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <mach/iomux-mx3.h>
-#include <mach/ipu.h>
-#include <mach/mx3_camera.h>
-#include <mach/spi.h>
-#include <mach/ulpi.h>
-
-#include "devices-imx31.h"
-#include "devices.h"
-
-static unsigned int moboard_pins[] = {
- /* UART0 */
- MX31_PIN_TXD1__TXD1, MX31_PIN_RXD1__RXD1,
- MX31_PIN_CTS1__GPIO2_7,
- /* UART4 */
- MX31_PIN_PC_RST__CTS5, MX31_PIN_PC_VS2__RTS5,
- MX31_PIN_PC_BVD2__TXD5, MX31_PIN_PC_BVD1__RXD5,
- /* I2C0 */
- MX31_PIN_I2C_DAT__I2C1_SDA, MX31_PIN_I2C_CLK__I2C1_SCL,
- /* I2C1 */
- MX31_PIN_DCD_DTE1__I2C2_SDA, MX31_PIN_RI_DTE1__I2C2_SCL,
- /* SDHC1 */
- MX31_PIN_SD1_DATA3__SD1_DATA3, MX31_PIN_SD1_DATA2__SD1_DATA2,
- MX31_PIN_SD1_DATA1__SD1_DATA1, MX31_PIN_SD1_DATA0__SD1_DATA0,
- MX31_PIN_SD1_CLK__SD1_CLK, MX31_PIN_SD1_CMD__SD1_CMD,
- MX31_PIN_ATA_CS0__GPIO3_26, MX31_PIN_ATA_CS1__GPIO3_27,
- /* USB reset */
- MX31_PIN_GPIO1_0__GPIO1_0,
- /* USB OTG */
- MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
- MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
- MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
- MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
- MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
- MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
- MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
- MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
- MX31_PIN_USBOTG_CLK__USBOTG_CLK, MX31_PIN_USBOTG_DIR__USBOTG_DIR,
- MX31_PIN_USBOTG_NXT__USBOTG_NXT, MX31_PIN_USBOTG_STP__USBOTG_STP,
- MX31_PIN_USB_OC__GPIO1_30,
- /* USB H2 */
- MX31_PIN_USBH2_DATA0__USBH2_DATA0,
- MX31_PIN_USBH2_DATA1__USBH2_DATA1,
- MX31_PIN_STXD3__USBH2_DATA2, MX31_PIN_SRXD3__USBH2_DATA3,
- MX31_PIN_SCK3__USBH2_DATA4, MX31_PIN_SFS3__USBH2_DATA5,
- MX31_PIN_STXD6__USBH2_DATA6, MX31_PIN_SRXD6__USBH2_DATA7,
- MX31_PIN_USBH2_CLK__USBH2_CLK, MX31_PIN_USBH2_DIR__USBH2_DIR,
- MX31_PIN_USBH2_NXT__USBH2_NXT, MX31_PIN_USBH2_STP__USBH2_STP,
- MX31_PIN_SCK6__GPIO1_25,
- /* LEDs */
- MX31_PIN_SVEN0__GPIO2_0, MX31_PIN_STX0__GPIO2_1,
- MX31_PIN_SRX0__GPIO2_2, MX31_PIN_SIMPD0__GPIO2_3,
- /* SPI1 */
- MX31_PIN_CSPI2_MOSI__MOSI, MX31_PIN_CSPI2_MISO__MISO,
- MX31_PIN_CSPI2_SCLK__SCLK, MX31_PIN_CSPI2_SPI_RDY__SPI_RDY,
- MX31_PIN_CSPI2_SS0__SS0, MX31_PIN_CSPI2_SS2__SS2,
- /* Atlas IRQ */
- MX31_PIN_GPIO1_3__GPIO1_3,
- /* SPI2 */
- MX31_PIN_CSPI3_MOSI__MOSI, MX31_PIN_CSPI3_MISO__MISO,
- MX31_PIN_CSPI3_SCLK__SCLK, MX31_PIN_CSPI3_SPI_RDY__SPI_RDY,
- MX31_PIN_CSPI2_SS1__CSPI3_SS1,
-};
-
-static struct physmap_flash_data mx31moboard_flash_data = {
- .width = 2,
-};
-
-static struct resource mx31moboard_flash_resource = {
- .start = 0xa0000000,
- .end = 0xa1ffffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device mx31moboard_flash = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &mx31moboard_flash_data,
- },
- .resource = &mx31moboard_flash_resource,
- .num_resources = 1,
-};
-
-static int moboard_uart0_init(struct platform_device *pdev)
-{
- int ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_CTS1), "uart0-cts-hack");
- if (ret)
- return ret;
-
- ret = gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CTS1), 0);
- if (ret)
- gpio_free(IOMUX_TO_GPIO(MX31_PIN_CTS1));
-
- return ret;
-}
-
-static void moboard_uart0_exit(struct platform_device *pdev)
-{
- gpio_free(IOMUX_TO_GPIO(MX31_PIN_CTS1));
-}
-
-static const struct imxuart_platform_data uart0_pdata __initconst = {
- .init = moboard_uart0_init,
- .exit = moboard_uart0_exit,
-};
-
-static const struct imxuart_platform_data uart4_pdata __initconst = {
- .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static const struct imxi2c_platform_data moboard_i2c0_data __initconst = {
- .bitrate = 400000,
-};
-
-static const struct imxi2c_platform_data moboard_i2c1_data __initconst = {
- .bitrate = 100000,
-};
-
-static int moboard_spi1_cs[] = {
- MXC_SPI_CS(0),
- MXC_SPI_CS(2),
-};
-
-static const struct spi_imx_master moboard_spi1_pdata __initconst = {
- .chipselect = moboard_spi1_cs,
- .num_chipselect = ARRAY_SIZE(moboard_spi1_cs),
-};
-
-static struct regulator_consumer_supply sdhc_consumers[] = {
- {
- .dev_name = "mxc-mmc.0",
- .supply = "sdhc0_vcc",
- },
- {
- .dev_name = "mxc-mmc.1",
- .supply = "sdhc1_vcc",
- },
-};
-
-static struct regulator_init_data sdhc_vreg_data = {
- .constraints = {
- .min_uV = 2700000,
- .max_uV = 3000000,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
- REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
- .valid_modes_mask = REGULATOR_MODE_NORMAL |
- REGULATOR_MODE_FAST,
- .always_on = 0,
- .boot_on = 1,
- },
- .num_consumer_supplies = ARRAY_SIZE(sdhc_consumers),
- .consumer_supplies = sdhc_consumers,
-};
-
-static struct regulator_consumer_supply cam_consumers[] = {
- {
- .dev = &mx3_camera.dev,
- .supply = "cam_vcc",
- },
-};
-
-static struct regulator_init_data cam_vreg_data = {
- .constraints = {
- .min_uV = 2700000,
- .max_uV = 3000000,
- .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
- REGULATOR_CHANGE_MODE | REGULATOR_CHANGE_STATUS,
- .valid_modes_mask = REGULATOR_MODE_NORMAL |
- REGULATOR_MODE_FAST,
- .always_on = 0,
- .boot_on = 1,
- },
- .num_consumer_supplies = ARRAY_SIZE(cam_consumers),
- .consumer_supplies = cam_consumers,
-};
-
-static struct mc13xxx_regulator_init_data moboard_regulators[] = {
- {
- .id = MC13783_REG_VMMC1,
- .init_data = &sdhc_vreg_data,
- },
- {
- .id = MC13783_REG_VCAM,
- .init_data = &cam_vreg_data,
- },
-};
-
-static struct mc13783_led_platform_data moboard_led[] = {
- {
- .id = MC13783_LED_R1,
- .name = "coreboard-led-4:red",
- .max_current = 2,
- },
- {
- .id = MC13783_LED_G1,
- .name = "coreboard-led-4:green",
- .max_current = 2,
- },
- {
- .id = MC13783_LED_B1,
- .name = "coreboard-led-4:blue",
- .max_current = 2,
- },
- {
- .id = MC13783_LED_R2,
- .name = "coreboard-led-5:red",
- .max_current = 3,
- },
- {
- .id = MC13783_LED_G2,
- .name = "coreboard-led-5:green",
- .max_current = 3,
- },
- {
- .id = MC13783_LED_B2,
- .name = "coreboard-led-5:blue",
- .max_current = 3,
- },
-};
-
-static struct mc13783_leds_platform_data moboard_leds = {
- .num_leds = ARRAY_SIZE(moboard_led),
- .led = moboard_led,
- .flags = MC13783_LED_SLEWLIMTC,
- .abmode = MC13783_LED_AB_DISABLED,
- .tc1_period = MC13783_LED_PERIOD_10MS,
- .tc2_period = MC13783_LED_PERIOD_10MS,
-};
-
-static struct mc13xxx_platform_data moboard_pmic = {
- .regulators = {
- .regulators = moboard_regulators,
- .num_regulators = ARRAY_SIZE(moboard_regulators),
- },
- .leds = &moboard_leds,
- .flags = MC13XXX_USE_REGULATOR | MC13XXX_USE_RTC |
- MC13XXX_USE_ADC | MC13XXX_USE_LED,
-};
-
-static struct spi_board_info moboard_spi_board_info[] __initdata = {
- {
- .modalias = "mc13783",
- .irq = IOMUX_TO_IRQ(MX31_PIN_GPIO1_3),
- .max_speed_hz = 300000,
- .bus_num = 1,
- .chip_select = 0,
- .platform_data = &moboard_pmic,
- .mode = SPI_CS_HIGH,
- },
-};
-
-static int moboard_spi2_cs[] = {
- MXC_SPI_CS(1),
-};
-
-static const struct spi_imx_master moboard_spi2_pdata __initconst = {
- .chipselect = moboard_spi2_cs,
- .num_chipselect = ARRAY_SIZE(moboard_spi2_cs),
-};
-
-#define SDHC1_CD IOMUX_TO_GPIO(MX31_PIN_ATA_CS0)
-#define SDHC1_WP IOMUX_TO_GPIO(MX31_PIN_ATA_CS1)
-
-static int moboard_sdhc1_get_ro(struct device *dev)
-{
- return !gpio_get_value(SDHC1_WP);
-}
-
-static int moboard_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
- void *data)
-{
- int ret;
-
- ret = gpio_request(SDHC1_CD, "sdhc-detect");
- if (ret)
- return ret;
-
- gpio_direction_input(SDHC1_CD);
-
- ret = gpio_request(SDHC1_WP, "sdhc-wp");
- if (ret)
- goto err_gpio_free;
- gpio_direction_input(SDHC1_WP);
-
- ret = request_irq(gpio_to_irq(SDHC1_CD), detect_irq,
- IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
- "sdhc1-card-detect", data);
- if (ret)
- goto err_gpio_free_2;
-
- return 0;
-
-err_gpio_free_2:
- gpio_free(SDHC1_WP);
-err_gpio_free:
- gpio_free(SDHC1_CD);
-
- return ret;
-}
-
-static void moboard_sdhc1_exit(struct device *dev, void *data)
-{
- free_irq(gpio_to_irq(SDHC1_CD), data);
- gpio_free(SDHC1_WP);
- gpio_free(SDHC1_CD);
-}
-
-static const struct imxmmc_platform_data sdhc1_pdata __initconst = {
- .get_ro = moboard_sdhc1_get_ro,
- .init = moboard_sdhc1_init,
- .exit = moboard_sdhc1_exit,
-};
-
-/*
- * this pin is dedicated for all mx31moboard systems, so we do it here
- */
-#define USB_RESET_B IOMUX_TO_GPIO(MX31_PIN_GPIO1_0)
-#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
- PAD_CTL_ODE_CMOS)
-
-#define OTG_EN_B IOMUX_TO_GPIO(MX31_PIN_USB_OC)
-#define USBH2_EN_B IOMUX_TO_GPIO(MX31_PIN_SCK6)
-
-static void usb_xcvr_reset(void)
-{
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA0, USB_PAD_CFG | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA1, USB_PAD_CFG | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA2, USB_PAD_CFG | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA3, USB_PAD_CFG | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA4, USB_PAD_CFG | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA5, USB_PAD_CFG | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA6, USB_PAD_CFG | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DATA7, USB_PAD_CFG | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_CLK, USB_PAD_CFG | PAD_CTL_100K_PU);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_DIR, USB_PAD_CFG | PAD_CTL_100K_PU);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_NXT, USB_PAD_CFG | PAD_CTL_100K_PU);
- mxc_iomux_set_pad(MX31_PIN_USBOTG_STP, USB_PAD_CFG | PAD_CTL_100K_PU);
-
- mxc_iomux_set_gpr(MUX_PGP_UH2, true);
- mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, USB_PAD_CFG | PAD_CTL_100K_PU);
- mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, USB_PAD_CFG | PAD_CTL_100K_PU);
- mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, USB_PAD_CFG | PAD_CTL_100K_PU);
- mxc_iomux_set_pad(MX31_PIN_USBH2_STP, USB_PAD_CFG | PAD_CTL_100K_PU);
- mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, USB_PAD_CFG | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, USB_PAD_CFG | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX31_PIN_SRXD6, USB_PAD_CFG | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX31_PIN_STXD6, USB_PAD_CFG | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX31_PIN_SFS3, USB_PAD_CFG | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX31_PIN_SCK3, USB_PAD_CFG | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX31_PIN_SRXD3, USB_PAD_CFG | PAD_CTL_100K_PD);
- mxc_iomux_set_pad(MX31_PIN_STXD3, USB_PAD_CFG | PAD_CTL_100K_PD);
-
- gpio_request(OTG_EN_B, "usb-udc-en");
- gpio_direction_output(OTG_EN_B, 0);
- gpio_request(USBH2_EN_B, "usbh2-en");
- gpio_direction_output(USBH2_EN_B, 0);
-
- gpio_request(USB_RESET_B, "usb-reset");
- gpio_direction_output(USB_RESET_B, 0);
- mdelay(1);
- gpio_set_value(USB_RESET_B, 1);
- mdelay(1);
-}
-
-static int moboard_usbh2_init_hw(struct platform_device *pdev)
-{
- return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
-}
-
-static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
- .init = moboard_usbh2_init_hw,
- .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
-};
-
-static int __init moboard_usbh2_init(void)
-{
- struct platform_device *pdev;
-
- usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
- ULPI_OTG_DRVVBUS_EXT);
- if (!usbh2_pdata.otg)
- return -ENODEV;
-
- pdev = imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
- if (IS_ERR(pdev))
- return PTR_ERR(pdev);
-
- return 0;
-}
-
-static struct gpio_led mx31moboard_leds[] = {
- {
- .name = "coreboard-led-0:red:running",
- .default_trigger = "heartbeat",
- .gpio = IOMUX_TO_GPIO(MX31_PIN_SVEN0),
- }, {
- .name = "coreboard-led-1:red",
- .gpio = IOMUX_TO_GPIO(MX31_PIN_STX0),
- }, {
- .name = "coreboard-led-2:red",
- .gpio = IOMUX_TO_GPIO(MX31_PIN_SRX0),
- }, {
- .name = "coreboard-led-3:red",
- .gpio = IOMUX_TO_GPIO(MX31_PIN_SIMPD0),
- },
-};
-
-static struct gpio_led_platform_data mx31moboard_led_pdata = {
- .num_leds = ARRAY_SIZE(mx31moboard_leds),
- .leds = mx31moboard_leds,
-};
-
-static struct platform_device mx31moboard_leds_device = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &mx31moboard_led_pdata,
- },
-};
-
-static struct ipu_platform_data mx3_ipu_data = {
- .irq_base = MXC_IPU_IRQ_START,
-};
-
-static struct platform_device *devices[] __initdata = {
- &mx31moboard_flash,
- &mx31moboard_leds_device,
-};
-
-static struct mx3_camera_pdata camera_pdata = {
- .dma_dev = &mx3_ipu.dev,
- .flags = MX3_CAMERA_DATAWIDTH_8 | MX3_CAMERA_DATAWIDTH_10,
- .mclk_10khz = 4800,
-};
-
-#define CAMERA_BUF_SIZE (4*1024*1024)
-
-static int __init mx31moboard_cam_alloc_dma(const size_t buf_size)
-{
- dma_addr_t dma_handle;
- void *buf;
- int dma;
-
- if (buf_size < 2 * 1024 * 1024)
- return -EINVAL;
-
- buf = dma_alloc_coherent(NULL, buf_size, &dma_handle, GFP_KERNEL);
- if (!buf) {
- pr_err("%s: cannot allocate camera buffer-memory\n", __func__);
- return -ENOMEM;
- }
-
- memset(buf, 0, buf_size);
-
- dma = dma_declare_coherent_memory(&mx3_camera.dev,
- dma_handle, dma_handle, buf_size,
- DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
-
- /* The way we call dma_declare_coherent_memory only a malloc can fail */
- return dma & DMA_MEMORY_MAP ? 0 : -ENOMEM;
-}
-
-static int mx31moboard_baseboard;
-core_param(mx31moboard_baseboard, mx31moboard_baseboard, int, 0444);
-
-/*
- * Board specific initialization.
- */
-static void __init mx31moboard_init(void)
-{
- mxc_iomux_setup_multiple_pins(moboard_pins, ARRAY_SIZE(moboard_pins),
- "moboard");
-
- platform_add_devices(devices, ARRAY_SIZE(devices));
-
- imx31_add_imx_uart0(&uart0_pdata);
- imx31_add_imx_uart4(&uart4_pdata);
-
- imx31_add_imx_i2c0(&moboard_i2c0_data);
- imx31_add_imx_i2c1(&moboard_i2c1_data);
-
- imx31_add_spi_imx1(&moboard_spi1_pdata);
- imx31_add_spi_imx2(&moboard_spi2_pdata);
-
- gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3), "pmic-irq");
- gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO1_3));
- spi_register_board_info(moboard_spi_board_info,
- ARRAY_SIZE(moboard_spi_board_info));
-
- imx31_add_mxc_mmc(0, &sdhc1_pdata);
-
- mxc_register_device(&mx3_ipu, &mx3_ipu_data);
- if (!mx31moboard_cam_alloc_dma(CAMERA_BUF_SIZE))
- mxc_register_device(&mx3_camera, &camera_pdata);
-
- usb_xcvr_reset();
-
- moboard_usbh2_init();
-
- switch (mx31moboard_baseboard) {
- case MX31NOBOARD:
- break;
- case MX31DEVBOARD:
- mx31moboard_devboard_init();
- break;
- case MX31MARXBOT:
- mx31moboard_marxbot_init();
- break;
- case MX31SMARTBOT:
- case MX31EYEBOT:
- mx31moboard_smartbot_init(mx31moboard_baseboard);
- break;
- default:
- printk(KERN_ERR "Illegal mx31moboard_baseboard type %d\n",
- mx31moboard_baseboard);
- }
-}
-
-static void __init mx31moboard_timer_init(void)
-{
- mx31_clocks_init(26000000);
-}
-
-struct sys_timer mx31moboard_timer = {
- .init = mx31moboard_timer_init,
-};
-
-MACHINE_START(MX31MOBOARD, "EPFL Mobots mx31moboard")
- /* Maintainer: Valentin Longchamp, EPFL Mobots group */
- .boot_params = MX3x_PHYS_OFFSET + 0x100,
- .map_io = mx31_map_io,
- .init_early = imx31_init_early,
- .init_irq = mx31_init_irq,
- .timer = &mx31moboard_timer,
- .init_machine = mx31moboard_init,
-MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-mx35_3ds.c b/arch/arm/mach-mx3/mach-mx35_3ds.c
deleted file mode 100644
index ff5fe23..0000000
--- a/arch/arm/mach-mx3/mach-mx35_3ds.c
+++ /dev/null
@@ -1,225 +0,0 @@
-/*
- * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (C) 2009 Marc Kleine-Budde, Pengutronix
- *
- * Author: Fabio Estevam <fabio.estevam@freescale.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-/*
- * This machine is known as:
- * - i.MX35 3-Stack Development System
- * - i.MX35 Platform Development Kit (i.MX35 PDK)
- */
-
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/memory.h>
-#include <linux/gpio.h>
-#include <linux/usb/otg.h>
-
-#include <linux/mtd/physmap.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <asm/mach/map.h>
-
-#include <mach/hardware.h>
-#include <mach/common.h>
-#include <mach/iomux-mx35.h>
-#include <mach/irqs.h>
-#include <mach/3ds_debugboard.h>
-
-#include "devices-imx35.h"
-#include "devices.h"
-
-#define EXPIO_PARENT_INT (MXC_INTERNAL_IRQS + GPIO_PORTA + 1)
-
-static const struct imxuart_platform_data uart_pdata __initconst = {
- .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static struct physmap_flash_data mx35pdk_flash_data = {
- .width = 2,
-};
-
-static struct resource mx35pdk_flash_resource = {
- .start = MX35_CS0_BASE_ADDR,
- .end = MX35_CS0_BASE_ADDR + SZ_64M - 1,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device mx35pdk_flash = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &mx35pdk_flash_data,
- },
- .resource = &mx35pdk_flash_resource,
- .num_resources = 1,
-};
-
-static const struct mxc_nand_platform_data mx35pdk_nand_board_info __initconst = {
- .width = 1,
- .hw_ecc = 1,
- .flash_bbt = 1,
-};
-
-static struct platform_device *devices[] __initdata = {
- &mx35pdk_flash,
-};
-
-static iomux_v3_cfg_t mx35pdk_pads[] = {
- /* UART1 */
- MX35_PAD_CTS1__UART1_CTS,
- MX35_PAD_RTS1__UART1_RTS,
- MX35_PAD_TXD1__UART1_TXD_MUX,
- MX35_PAD_RXD1__UART1_RXD_MUX,
- /* FEC */
- MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
- MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
- MX35_PAD_FEC_RX_DV__FEC_RX_DV,
- MX35_PAD_FEC_COL__FEC_COL,
- MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
- MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
- MX35_PAD_FEC_TX_EN__FEC_TX_EN,
- MX35_PAD_FEC_MDC__FEC_MDC,
- MX35_PAD_FEC_MDIO__FEC_MDIO,
- MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
- MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
- MX35_PAD_FEC_CRS__FEC_CRS,
- MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
- MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
- MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
- MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
- MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
- MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
- /* USBOTG */
- MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR,
- MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC,
- /* USBH1 */
- MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR,
- MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC,
- /* SDCARD */
- MX35_PAD_SD1_CMD__ESDHC1_CMD,
- MX35_PAD_SD1_CLK__ESDHC1_CLK,
- MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
- MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
- MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
- MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
- /* I2C1 */
- MX35_PAD_I2C1_CLK__I2C1_SCL,
- MX35_PAD_I2C1_DAT__I2C1_SDA,
-};
-
-static int mx35_3ds_otg_init(struct platform_device *pdev)
-{
- return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY);
-}
-
-/* OTG config */
-static const struct fsl_usb2_platform_data usb_otg_pdata __initconst = {
- .operating_mode = FSL_USB2_DR_DEVICE,
- .phy_mode = FSL_USB2_PHY_UTMI_WIDE,
- .workaround = FLS_USB2_WORKAROUND_ENGCM09152,
-/*
- * ENGCM09152 also requires a hardware change.
- * Please check the MX35 Chip Errata document for details.
- */
-};
-
-static struct mxc_usbh_platform_data otg_pdata __initdata = {
- .init = mx35_3ds_otg_init,
- .portsc = MXC_EHCI_MODE_UTMI,
-};
-
-static int mx35_3ds_usbh_init(struct platform_device *pdev)
-{
- return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_SINGLE_UNI |
- MXC_EHCI_INTERNAL_PHY);
-}
-
-/* USB HOST config */
-static const struct mxc_usbh_platform_data usb_host_pdata __initconst = {
- .init = mx35_3ds_usbh_init,
- .portsc = MXC_EHCI_MODE_SERIAL,
-};
-
-static int otg_mode_host;
-
-static int __init mx35_3ds_otg_mode(char *options)
-{
- if (!strcmp(options, "host"))
- otg_mode_host = 1;
- else if (!strcmp(options, "device"))
- otg_mode_host = 0;
- else
- pr_info("otg_mode neither \"host\" nor \"device\". "
- "Defaulting to device\n");
- return 0;
-}
-__setup("otg_mode=", mx35_3ds_otg_mode);
-
-static const struct imxi2c_platform_data mx35_3ds_i2c0_data __initconst = {
- .bitrate = 100000,
-};
-
-/*
- * Board specific initialization.
- */
-static void __init mx35_3ds_init(void)
-{
- mxc_iomux_v3_setup_multiple_pads(mx35pdk_pads, ARRAY_SIZE(mx35pdk_pads));
-
- imx35_add_fec(NULL);
- imx35_add_imx2_wdt(NULL);
- platform_add_devices(devices, ARRAY_SIZE(devices));
-
- imx35_add_imx_uart0(&uart_pdata);
-
- if (otg_mode_host)
- imx35_add_mxc_ehci_otg(&otg_pdata);
-
- imx35_add_mxc_ehci_hs(&usb_host_pdata);
-
- if (!otg_mode_host)
- imx35_add_fsl_usb2_udc(&usb_otg_pdata);
-
- imx35_add_mxc_nand(&mx35pdk_nand_board_info);
- imx35_add_sdhci_esdhc_imx(0, NULL);
-
- if (mxc_expio_init(MX35_CS5_BASE_ADDR, EXPIO_PARENT_INT))
- pr_warn("Init of the debugboard failed, all "
- "devices on the debugboard are unusable.\n");
- imx35_add_imx_i2c0(&mx35_3ds_i2c0_data);
-}
-
-static void __init mx35pdk_timer_init(void)
-{
- mx35_clocks_init();
-}
-
-struct sys_timer mx35pdk_timer = {
- .init = mx35pdk_timer_init,
-};
-
-MACHINE_START(MX35_3DS, "Freescale MX35PDK")
- /* Maintainer: Freescale Semiconductor, Inc */
- .boot_params = MX3x_PHYS_OFFSET + 0x100,
- .map_io = mx35_map_io,
- .init_early = imx35_init_early,
- .init_irq = mx35_init_irq,
- .timer = &mx35pdk_timer,
- .init_machine = mx35_3ds_init,
-MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-pcm037.c b/arch/arm/mach-mx3/mach-pcm037.c
deleted file mode 100644
index f07d3bd..0000000
--- a/arch/arm/mach-mx3/mach-pcm037.c
+++ /dev/null
@@ -1,691 +0,0 @@
-/*
- * Copyright (C) 2008 Sascha Hauer, Pengutronix
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/dma-mapping.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/physmap.h>
-#include <linux/mtd/plat-ram.h>
-#include <linux/memory.h>
-#include <linux/gpio.h>
-#include <linux/smsc911x.h>
-#include <linux/interrupt.h>
-#include <linux/i2c.h>
-#include <linux/i2c/at24.h>
-#include <linux/delay.h>
-#include <linux/spi/spi.h>
-#include <linux/irq.h>
-#include <linux/can/platform/sja1000.h>
-#include <linux/usb/otg.h>
-#include <linux/usb/ulpi.h>
-#include <linux/gfp.h>
-
-#include <media/soc_camera.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <asm/mach/map.h>
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <mach/iomux-mx3.h>
-#include <mach/ipu.h>
-#include <mach/mx3_camera.h>
-#include <mach/mx3fb.h>
-#include <mach/ulpi.h>
-
-#include "devices-imx31.h"
-#include "devices.h"
-#include "pcm037.h"
-
-static enum pcm037_board_variant pcm037_instance = PCM037_PCM970;
-
-static int __init pcm037_variant_setup(char *str)
-{
- if (!strcmp("eet", str))
- pcm037_instance = PCM037_EET;
- else if (strcmp("pcm970", str))
- pr_warning("Unknown pcm037 baseboard variant %s\n", str);
-
- return 1;
-}
-
-/* Supported values: "pcm970" (default) and "eet" */
-__setup("pcm037_variant=", pcm037_variant_setup);
-
-enum pcm037_board_variant pcm037_variant(void)
-{
- return pcm037_instance;
-}
-
-/* UART1 with RTS/CTS handshake signals */
-static unsigned int pcm037_uart1_handshake_pins[] = {
- MX31_PIN_CTS1__CTS1,
- MX31_PIN_RTS1__RTS1,
- MX31_PIN_TXD1__TXD1,
- MX31_PIN_RXD1__RXD1,
-};
-
-/* UART1 without RTS/CTS handshake signals */
-static unsigned int pcm037_uart1_pins[] = {
- MX31_PIN_TXD1__TXD1,
- MX31_PIN_RXD1__RXD1,
-};
-
-static unsigned int pcm037_pins[] = {
- /* I2C */
- MX31_PIN_CSPI2_MOSI__SCL,
- MX31_PIN_CSPI2_MISO__SDA,
- MX31_PIN_CSPI2_SS2__I2C3_SDA,
- MX31_PIN_CSPI2_SCLK__I2C3_SCL,
- /* SDHC1 */
- MX31_PIN_SD1_DATA3__SD1_DATA3,
- MX31_PIN_SD1_DATA2__SD1_DATA2,
- MX31_PIN_SD1_DATA1__SD1_DATA1,
- MX31_PIN_SD1_DATA0__SD1_DATA0,
- MX31_PIN_SD1_CLK__SD1_CLK,
- MX31_PIN_SD1_CMD__SD1_CMD,
- IOMUX_MODE(MX31_PIN_SCK6, IOMUX_CONFIG_GPIO), /* card detect */
- IOMUX_MODE(MX31_PIN_SFS6, IOMUX_CONFIG_GPIO), /* write protect */
- /* SPI1 */
- MX31_PIN_CSPI1_MOSI__MOSI,
- MX31_PIN_CSPI1_MISO__MISO,
- MX31_PIN_CSPI1_SCLK__SCLK,
- MX31_PIN_CSPI1_SPI_RDY__SPI_RDY,
- MX31_PIN_CSPI1_SS0__SS0,
- MX31_PIN_CSPI1_SS1__SS1,
- MX31_PIN_CSPI1_SS2__SS2,
- /* UART2 */
- MX31_PIN_TXD2__TXD2,
- MX31_PIN_RXD2__RXD2,
- MX31_PIN_CTS2__CTS2,
- MX31_PIN_RTS2__RTS2,
- /* UART3 */
- MX31_PIN_CSPI3_MOSI__RXD3,
- MX31_PIN_CSPI3_MISO__TXD3,
- MX31_PIN_CSPI3_SCLK__RTS3,
- MX31_PIN_CSPI3_SPI_RDY__CTS3,
- /* LAN9217 irq pin */
- IOMUX_MODE(MX31_PIN_GPIO3_1, IOMUX_CONFIG_GPIO),
- /* Onewire */
- MX31_PIN_BATT_LINE__OWIRE,
- /* Framebuffer */
- MX31_PIN_LD0__LD0,
- MX31_PIN_LD1__LD1,
- MX31_PIN_LD2__LD2,
- MX31_PIN_LD3__LD3,
- MX31_PIN_LD4__LD4,
- MX31_PIN_LD5__LD5,
- MX31_PIN_LD6__LD6,
- MX31_PIN_LD7__LD7,
- MX31_PIN_LD8__LD8,
- MX31_PIN_LD9__LD9,
- MX31_PIN_LD10__LD10,
- MX31_PIN_LD11__LD11,
- MX31_PIN_LD12__LD12,
- MX31_PIN_LD13__LD13,
- MX31_PIN_LD14__LD14,
- MX31_PIN_LD15__LD15,
- MX31_PIN_LD16__LD16,
- MX31_PIN_LD17__LD17,
- MX31_PIN_VSYNC3__VSYNC3,
- MX31_PIN_HSYNC__HSYNC,
- MX31_PIN_FPSHIFT__FPSHIFT,
- MX31_PIN_DRDY0__DRDY0,
- MX31_PIN_D3_REV__D3_REV,
- MX31_PIN_CONTRAST__CONTRAST,
- MX31_PIN_D3_SPL__D3_SPL,
- MX31_PIN_D3_CLS__D3_CLS,
- MX31_PIN_LCS0__GPI03_23,
- /* CSI */
- IOMUX_MODE(MX31_PIN_CSI_D5, IOMUX_CONFIG_GPIO),
- MX31_PIN_CSI_D6__CSI_D6,
- MX31_PIN_CSI_D7__CSI_D7,
- MX31_PIN_CSI_D8__CSI_D8,
- MX31_PIN_CSI_D9__CSI_D9,
- MX31_PIN_CSI_D10__CSI_D10,
- MX31_PIN_CSI_D11__CSI_D11,
- MX31_PIN_CSI_D12__CSI_D12,
- MX31_PIN_CSI_D13__CSI_D13,
- MX31_PIN_CSI_D14__CSI_D14,
- MX31_PIN_CSI_D15__CSI_D15,
- MX31_PIN_CSI_HSYNC__CSI_HSYNC,
- MX31_PIN_CSI_MCLK__CSI_MCLK,
- MX31_PIN_CSI_PIXCLK__CSI_PIXCLK,
- MX31_PIN_CSI_VSYNC__CSI_VSYNC,
- /* GPIO */
- IOMUX_MODE(MX31_PIN_ATA_DMACK, IOMUX_CONFIG_GPIO),
- /* OTG */
- MX31_PIN_USBOTG_DATA0__USBOTG_DATA0,
- MX31_PIN_USBOTG_DATA1__USBOTG_DATA1,
- MX31_PIN_USBOTG_DATA2__USBOTG_DATA2,
- MX31_PIN_USBOTG_DATA3__USBOTG_DATA3,
- MX31_PIN_USBOTG_DATA4__USBOTG_DATA4,
- MX31_PIN_USBOTG_DATA5__USBOTG_DATA5,
- MX31_PIN_USBOTG_DATA6__USBOTG_DATA6,
- MX31_PIN_USBOTG_DATA7__USBOTG_DATA7,
- MX31_PIN_USBOTG_CLK__USBOTG_CLK,
- MX31_PIN_USBOTG_DIR__USBOTG_DIR,
- MX31_PIN_USBOTG_NXT__USBOTG_NXT,
- MX31_PIN_USBOTG_STP__USBOTG_STP,
- /* USB host 2 */
- IOMUX_MODE(MX31_PIN_USBH2_CLK, IOMUX_CONFIG_FUNC),
- IOMUX_MODE(MX31_PIN_USBH2_DIR, IOMUX_CONFIG_FUNC),
- IOMUX_MODE(MX31_PIN_USBH2_NXT, IOMUX_CONFIG_FUNC),
- IOMUX_MODE(MX31_PIN_USBH2_STP, IOMUX_CONFIG_FUNC),
- IOMUX_MODE(MX31_PIN_USBH2_DATA0, IOMUX_CONFIG_FUNC),
- IOMUX_MODE(MX31_PIN_USBH2_DATA1, IOMUX_CONFIG_FUNC),
- IOMUX_MODE(MX31_PIN_STXD3, IOMUX_CONFIG_FUNC),
- IOMUX_MODE(MX31_PIN_SRXD3, IOMUX_CONFIG_FUNC),
- IOMUX_MODE(MX31_PIN_SCK3, IOMUX_CONFIG_FUNC),
- IOMUX_MODE(MX31_PIN_SFS3, IOMUX_CONFIG_FUNC),
- IOMUX_MODE(MX31_PIN_STXD6, IOMUX_CONFIG_FUNC),
- IOMUX_MODE(MX31_PIN_SRXD6, IOMUX_CONFIG_FUNC),
-};
-
-static struct physmap_flash_data pcm037_flash_data = {
- .width = 2,
-};
-
-static struct resource pcm037_flash_resource = {
- .start = 0xa0000000,
- .end = 0xa1ffffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device pcm037_flash = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &pcm037_flash_data,
- },
- .resource = &pcm037_flash_resource,
- .num_resources = 1,
-};
-
-static const struct imxuart_platform_data uart_pdata __initconst = {
- .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static struct resource smsc911x_resources[] = {
- {
- .start = MX31_CS1_BASE_ADDR + 0x300,
- .end = MX31_CS1_BASE_ADDR + 0x300 + SZ_64K - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
- .end = IOMUX_TO_IRQ(MX31_PIN_GPIO3_1),
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
- },
-};
-
-static struct smsc911x_platform_config smsc911x_info = {
- .flags = SMSC911X_USE_32BIT | SMSC911X_FORCE_INTERNAL_PHY |
- SMSC911X_SAVE_MAC_ADDRESS,
- .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
- .irq_type = SMSC911X_IRQ_TYPE_OPEN_DRAIN,
- .phy_interface = PHY_INTERFACE_MODE_MII,
-};
-
-static struct platform_device pcm037_eth = {
- .name = "smsc911x",
- .id = -1,
- .num_resources = ARRAY_SIZE(smsc911x_resources),
- .resource = smsc911x_resources,
- .dev = {
- .platform_data = &smsc911x_info,
- },
-};
-
-static struct platdata_mtd_ram pcm038_sram_data = {
- .bankwidth = 2,
-};
-
-static struct resource pcm038_sram_resource = {
- .start = MX31_CS4_BASE_ADDR,
- .end = MX31_CS4_BASE_ADDR + 512 * 1024 - 1,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device pcm037_sram_device = {
- .name = "mtd-ram",
- .id = 0,
- .dev = {
- .platform_data = &pcm038_sram_data,
- },
- .num_resources = 1,
- .resource = &pcm038_sram_resource,
-};
-
-static const struct mxc_nand_platform_data
-pcm037_nand_board_info __initconst = {
- .width = 1,
- .hw_ecc = 1,
-};
-
-static const struct imxi2c_platform_data pcm037_i2c1_data __initconst = {
- .bitrate = 100000,
-};
-
-static const struct imxi2c_platform_data pcm037_i2c2_data __initconst = {
- .bitrate = 20000,
-};
-
-static struct at24_platform_data board_eeprom = {
- .byte_len = 4096,
- .page_size = 32,
- .flags = AT24_FLAG_ADDR16,
-};
-
-static int pcm037_camera_power(struct device *dev, int on)
-{
- /* disable or enable the camera in X7 or X8 PCM970 connector */
- gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), !on);
- return 0;
-}
-
-static struct i2c_board_info pcm037_i2c_camera[] = {
- {
- I2C_BOARD_INFO("mt9t031", 0x5d),
- }, {
- I2C_BOARD_INFO("mt9v022", 0x48),
- },
-};
-
-static struct soc_camera_link iclink_mt9v022 = {
- .bus_id = 0, /* Must match with the camera ID */
- .board_info = &pcm037_i2c_camera[1],
- .i2c_adapter_id = 2,
-};
-
-static struct soc_camera_link iclink_mt9t031 = {
- .bus_id = 0, /* Must match with the camera ID */
- .power = pcm037_camera_power,
- .board_info = &pcm037_i2c_camera[0],
- .i2c_adapter_id = 2,
-};
-
-static struct i2c_board_info pcm037_i2c_devices[] = {
- {
- I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
- .platform_data = &board_eeprom,
- }, {
- I2C_BOARD_INFO("pcf8563", 0x51),
- }
-};
-
-static struct platform_device pcm037_mt9t031 = {
- .name = "soc-camera-pdrv",
- .id = 0,
- .dev = {
- .platform_data = &iclink_mt9t031,
- },
-};
-
-static struct platform_device pcm037_mt9v022 = {
- .name = "soc-camera-pdrv",
- .id = 1,
- .dev = {
- .platform_data = &iclink_mt9v022,
- },
-};
-
-/* Not connected by default */
-#ifdef PCM970_SDHC_RW_SWITCH
-static int pcm970_sdhc1_get_ro(struct device *dev)
-{
- return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_SFS6));
-}
-#endif
-
-#define SDHC1_GPIO_WP IOMUX_TO_GPIO(MX31_PIN_SFS6)
-#define SDHC1_GPIO_DET IOMUX_TO_GPIO(MX31_PIN_SCK6)
-
-static int pcm970_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
- void *data)
-{
- int ret;
-
- ret = gpio_request(SDHC1_GPIO_DET, "sdhc-detect");
- if (ret)
- return ret;
-
- gpio_direction_input(SDHC1_GPIO_DET);
-
-#ifdef PCM970_SDHC_RW_SWITCH
- ret = gpio_request(SDHC1_GPIO_WP, "sdhc-wp");
- if (ret)
- goto err_gpio_free;
- gpio_direction_input(SDHC1_GPIO_WP);
-#endif
-
- ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_SCK6), detect_irq,
- IRQF_DISABLED | IRQF_TRIGGER_FALLING,
- "sdhc-detect", data);
- if (ret)
- goto err_gpio_free_2;
-
- return 0;
-
-err_gpio_free_2:
-#ifdef PCM970_SDHC_RW_SWITCH
- gpio_free(SDHC1_GPIO_WP);
-err_gpio_free:
-#endif
- gpio_free(SDHC1_GPIO_DET);
-
- return ret;
-}
-
-static void pcm970_sdhc1_exit(struct device *dev, void *data)
-{
- free_irq(IOMUX_TO_IRQ(MX31_PIN_SCK6), data);
- gpio_free(SDHC1_GPIO_DET);
- gpio_free(SDHC1_GPIO_WP);
-}
-
-static const struct imxmmc_platform_data sdhc_pdata __initconst = {
-#ifdef PCM970_SDHC_RW_SWITCH
- .get_ro = pcm970_sdhc1_get_ro,
-#endif
- .init = pcm970_sdhc1_init,
- .exit = pcm970_sdhc1_exit,
-};
-
-struct mx3_camera_pdata camera_pdata = {
- .dma_dev = &mx3_ipu.dev,
- .flags = MX3_CAMERA_DATAWIDTH_8 | MX3_CAMERA_DATAWIDTH_10,
- .mclk_10khz = 2000,
-};
-
-static int __init pcm037_camera_alloc_dma(const size_t buf_size)
-{
- dma_addr_t dma_handle;
- void *buf;
- int dma;
-
- if (buf_size < 2 * 1024 * 1024)
- return -EINVAL;
-
- buf = dma_alloc_coherent(NULL, buf_size, &dma_handle, GFP_KERNEL);
- if (!buf) {
- pr_err("%s: cannot allocate camera buffer-memory\n", __func__);
- return -ENOMEM;
- }
-
- memset(buf, 0, buf_size);
-
- dma = dma_declare_coherent_memory(&mx3_camera.dev,
- dma_handle, dma_handle, buf_size,
- DMA_MEMORY_MAP | DMA_MEMORY_EXCLUSIVE);
-
- /* The way we call dma_declare_coherent_memory only a malloc can fail */
- return dma & DMA_MEMORY_MAP ? 0 : -ENOMEM;
-}
-
-static struct platform_device *devices[] __initdata = {
- &pcm037_flash,
- &pcm037_sram_device,
- &pcm037_mt9t031,
- &pcm037_mt9v022,
-};
-
-static struct ipu_platform_data mx3_ipu_data = {
- .irq_base = MXC_IPU_IRQ_START,
-};
-
-static const struct fb_videomode fb_modedb[] = {
- {
- /* 240x320 @ 60 Hz Sharp */
- .name = "Sharp-LQ035Q7DH06-QVGA",
- .refresh = 60,
- .xres = 240,
- .yres = 320,
- .pixclock = 185925,
- .left_margin = 9,
- .right_margin = 16,
- .upper_margin = 7,
- .lower_margin = 9,
- .hsync_len = 1,
- .vsync_len = 1,
- .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE |
- FB_SYNC_CLK_INVERT | FB_SYNC_CLK_IDLE_EN,
- .vmode = FB_VMODE_NONINTERLACED,
- .flag = 0,
- }, {
- /* 240x320 @ 60 Hz */
- .name = "TX090",
- .refresh = 60,
- .xres = 240,
- .yres = 320,
- .pixclock = 38255,
- .left_margin = 144,
- .right_margin = 0,
- .upper_margin = 7,
- .lower_margin = 40,
- .hsync_len = 96,
- .vsync_len = 1,
- .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH,
- .vmode = FB_VMODE_NONINTERLACED,
- .flag = 0,
- }, {
- /* 240x320 @ 60 Hz */
- .name = "CMEL-OLED",
- .refresh = 60,
- .xres = 240,
- .yres = 320,
- .pixclock = 185925,
- .left_margin = 9,
- .right_margin = 16,
- .upper_margin = 7,
- .lower_margin = 9,
- .hsync_len = 1,
- .vsync_len = 1,
- .sync = FB_SYNC_OE_ACT_HIGH | FB_SYNC_CLK_INVERT,
- .vmode = FB_VMODE_NONINTERLACED,
- .flag = 0,
- },
-};
-
-static struct mx3fb_platform_data mx3fb_pdata = {
- .dma_dev = &mx3_ipu.dev,
- .name = "Sharp-LQ035Q7DH06-QVGA",
- .mode = fb_modedb,
- .num_modes = ARRAY_SIZE(fb_modedb),
-};
-
-static struct resource pcm970_sja1000_resources[] = {
- {
- .start = MX31_CS5_BASE_ADDR,
- .end = MX31_CS5_BASE_ADDR + 0x100 - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IOMUX_TO_IRQ(IOMUX_PIN(48, 105)),
- .end = IOMUX_TO_IRQ(IOMUX_PIN(48, 105)),
- .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWEDGE,
- },
-};
-
-struct sja1000_platform_data pcm970_sja1000_platform_data = {
- .osc_freq = 16000000,
- .ocr = OCR_TX1_PULLDOWN | OCR_TX0_PUSHPULL,
- .cdr = CDR_CBP,
-};
-
-static struct platform_device pcm970_sja1000 = {
- .name = "sja1000_platform",
- .dev = {
- .platform_data = &pcm970_sja1000_platform_data,
- },
- .resource = pcm970_sja1000_resources,
- .num_resources = ARRAY_SIZE(pcm970_sja1000_resources),
-};
-
-static int pcm037_otg_init(struct platform_device *pdev)
-{
- return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
-}
-
-static struct mxc_usbh_platform_data otg_pdata __initdata = {
- .init = pcm037_otg_init,
- .portsc = MXC_EHCI_MODE_ULPI,
-};
-
-static int pcm037_usbh2_init(struct platform_device *pdev)
-{
- return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
-}
-
-static struct mxc_usbh_platform_data usbh2_pdata __initdata = {
- .init = pcm037_usbh2_init,
- .portsc = MXC_EHCI_MODE_ULPI,
-};
-
-static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
- .operating_mode = FSL_USB2_DR_DEVICE,
- .phy_mode = FSL_USB2_PHY_ULPI,
-};
-
-static int otg_mode_host;
-
-static int __init pcm037_otg_mode(char *options)
-{
- if (!strcmp(options, "host"))
- otg_mode_host = 1;
- else if (!strcmp(options, "device"))
- otg_mode_host = 0;
- else
- pr_info("otg_mode neither \"host\" nor \"device\". "
- "Defaulting to device\n");
- return 0;
-}
-__setup("otg_mode=", pcm037_otg_mode);
-
-/*
- * Board specific initialization.
- */
-static void __init pcm037_init(void)
-{
- int ret;
-
- mxc_iomux_set_gpr(MUX_PGP_UH2, 1);
-
- mxc_iomux_setup_multiple_pins(pcm037_pins, ARRAY_SIZE(pcm037_pins),
- "pcm037");
-
-#define H2_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS \
- | PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
-
- mxc_iomux_set_pad(MX31_PIN_USBH2_CLK, H2_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBH2_DIR, H2_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBH2_NXT, H2_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBH2_STP, H2_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_USBH2_DATA0, H2_PAD_CFG); /* USBH2_DATA0 */
- mxc_iomux_set_pad(MX31_PIN_USBH2_DATA1, H2_PAD_CFG); /* USBH2_DATA1 */
- mxc_iomux_set_pad(MX31_PIN_SRXD6, H2_PAD_CFG); /* USBH2_DATA2 */
- mxc_iomux_set_pad(MX31_PIN_STXD6, H2_PAD_CFG); /* USBH2_DATA3 */
- mxc_iomux_set_pad(MX31_PIN_SFS3, H2_PAD_CFG); /* USBH2_DATA4 */
- mxc_iomux_set_pad(MX31_PIN_SCK3, H2_PAD_CFG); /* USBH2_DATA5 */
- mxc_iomux_set_pad(MX31_PIN_SRXD3, H2_PAD_CFG); /* USBH2_DATA6 */
- mxc_iomux_set_pad(MX31_PIN_STXD3, H2_PAD_CFG); /* USBH2_DATA7 */
-
- if (pcm037_variant() == PCM037_EET)
- mxc_iomux_setup_multiple_pins(pcm037_uart1_pins,
- ARRAY_SIZE(pcm037_uart1_pins), "pcm037_uart1");
- else
- mxc_iomux_setup_multiple_pins(pcm037_uart1_handshake_pins,
- ARRAY_SIZE(pcm037_uart1_handshake_pins),
- "pcm037_uart1");
-
- platform_add_devices(devices, ARRAY_SIZE(devices));
-
- imx31_add_imx2_wdt(NULL);
- imx31_add_imx_uart0(&uart_pdata);
- /* XXX: should't this have .flags = 0 (i.e. no RTSCTS) on PCM037_EET? */
- imx31_add_imx_uart1(&uart_pdata);
- imx31_add_imx_uart2(&uart_pdata);
-
- imx31_add_mxc_w1(NULL);
-
- /* LAN9217 IRQ pin */
- ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1), "lan9217-irq");
- if (ret)
- pr_warning("could not get LAN irq gpio\n");
- else {
- gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_GPIO3_1));
- platform_device_register(&pcm037_eth);
- }
-
-
- /* I2C adapters and devices */
- i2c_register_board_info(1, pcm037_i2c_devices,
- ARRAY_SIZE(pcm037_i2c_devices));
-
- imx31_add_imx_i2c1(&pcm037_i2c1_data);
- imx31_add_imx_i2c2(&pcm037_i2c2_data);
-
- imx31_add_mxc_nand(&pcm037_nand_board_info);
- imx31_add_mxc_mmc(0, &sdhc_pdata);
- mxc_register_device(&mx3_ipu, &mx3_ipu_data);
- mxc_register_device(&mx3_fb, &mx3fb_pdata);
-
- /* CSI */
- /* Camera power: default - off */
- ret = gpio_request(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), "mt9t031-power");
- if (!ret)
- gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_CSI_D5), 1);
- else
- iclink_mt9t031.power = NULL;
-
- if (!pcm037_camera_alloc_dma(4 * 1024 * 1024))
- mxc_register_device(&mx3_camera, &camera_pdata);
-
- platform_device_register(&pcm970_sja1000);
-
- if (otg_mode_host) {
- otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
- ULPI_OTG_DRVVBUS_EXT);
- if (otg_pdata.otg)
- imx31_add_mxc_ehci_otg(&otg_pdata);
- }
-
- usbh2_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
- ULPI_OTG_DRVVBUS_EXT);
- if (usbh2_pdata.otg)
- imx31_add_mxc_ehci_hs(2, &usbh2_pdata);
-
- if (!otg_mode_host)
- imx31_add_fsl_usb2_udc(&otg_device_pdata);
-
-}
-
-static void __init pcm037_timer_init(void)
-{
- mx31_clocks_init(26000000);
-}
-
-struct sys_timer pcm037_timer = {
- .init = pcm037_timer_init,
-};
-
-MACHINE_START(PCM037, "Phytec Phycore pcm037")
- /* Maintainer: Pengutronix */
- .boot_params = MX3x_PHYS_OFFSET + 0x100,
- .map_io = mx31_map_io,
- .init_early = imx31_init_early,
- .init_irq = mx31_init_irq,
- .timer = &pcm037_timer,
- .init_machine = pcm037_init,
-MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-pcm037_eet.c b/arch/arm/mach-mx3/mach-pcm037_eet.c
deleted file mode 100644
index df6fb07..0000000
--- a/arch/arm/mach-mx3/mach-pcm037_eet.c
+++ /dev/null
@@ -1,190 +0,0 @@
-/*
- * Copyright (C) 2009
- * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#include <linux/gpio.h>
-#include <linux/gpio_keys.h>
-#include <linux/input.h>
-#include <linux/platform_device.h>
-#include <linux/spi/spi.h>
-
-#include <mach/common.h>
-#include <mach/iomux-mx3.h>
-#include <mach/spi.h>
-
-#include <asm/mach-types.h>
-
-#include "pcm037.h"
-#include "devices.h"
-#include "devices-imx31.h"
-
-static unsigned int pcm037_eet_pins[] = {
- /* Reserve and hardwire GPIO 57 high - S6E63D6 chipselect */
- IOMUX_MODE(MX31_PIN_KEY_COL7, IOMUX_CONFIG_GPIO),
- /* GPIO keys */
- IOMUX_MODE(MX31_PIN_GPIO1_0, IOMUX_CONFIG_GPIO), /* 0 */
- IOMUX_MODE(MX31_PIN_GPIO1_1, IOMUX_CONFIG_GPIO), /* 1 */
- IOMUX_MODE(MX31_PIN_GPIO1_2, IOMUX_CONFIG_GPIO), /* 2 */
- IOMUX_MODE(MX31_PIN_GPIO1_3, IOMUX_CONFIG_GPIO), /* 3 */
- IOMUX_MODE(MX31_PIN_SVEN0, IOMUX_CONFIG_GPIO), /* 32 */
- IOMUX_MODE(MX31_PIN_STX0, IOMUX_CONFIG_GPIO), /* 33 */
- IOMUX_MODE(MX31_PIN_SRX0, IOMUX_CONFIG_GPIO), /* 34 */
- IOMUX_MODE(MX31_PIN_SIMPD0, IOMUX_CONFIG_GPIO), /* 35 */
- IOMUX_MODE(MX31_PIN_RTS1, IOMUX_CONFIG_GPIO), /* 38 */
- IOMUX_MODE(MX31_PIN_CTS1, IOMUX_CONFIG_GPIO), /* 39 */
- IOMUX_MODE(MX31_PIN_KEY_ROW4, IOMUX_CONFIG_GPIO), /* 50 */
- IOMUX_MODE(MX31_PIN_KEY_ROW5, IOMUX_CONFIG_GPIO), /* 51 */
- IOMUX_MODE(MX31_PIN_KEY_ROW6, IOMUX_CONFIG_GPIO), /* 52 */
- IOMUX_MODE(MX31_PIN_KEY_ROW7, IOMUX_CONFIG_GPIO), /* 53 */
-
- /* LEDs */
- IOMUX_MODE(MX31_PIN_DTR_DTE1, IOMUX_CONFIG_GPIO), /* 44 */
- IOMUX_MODE(MX31_PIN_DSR_DTE1, IOMUX_CONFIG_GPIO), /* 45 */
- IOMUX_MODE(MX31_PIN_KEY_COL5, IOMUX_CONFIG_GPIO), /* 55 */
- IOMUX_MODE(MX31_PIN_KEY_COL6, IOMUX_CONFIG_GPIO), /* 56 */
-};
-
-/* SPI */
-static struct spi_board_info pcm037_spi_dev[] = {
- {
- .modalias = "dac124s085",
- .max_speed_hz = 400000,
- .bus_num = 0,
- .chip_select = 0, /* Index in pcm037_spi1_cs[] */
- .mode = SPI_CPHA,
- },
-};
-
-/* Platform Data for MXC CSPI */
-static int pcm037_spi1_cs[] = {MXC_SPI_CS(1), IOMUX_TO_GPIO(MX31_PIN_KEY_COL7)};
-
-static const struct spi_imx_master pcm037_spi1_pdata __initconst = {
- .chipselect = pcm037_spi1_cs,
- .num_chipselect = ARRAY_SIZE(pcm037_spi1_cs),
-};
-
-/* GPIO-keys input device */
-static struct gpio_keys_button pcm037_gpio_keys[] = {
- {
- .type = EV_KEY,
- .code = KEY_L,
- .gpio = 0,
- .desc = "Wheel Manual",
- .wakeup = 0,
- }, {
- .type = EV_KEY,
- .code = KEY_A,
- .gpio = 1,
- .desc = "Wheel AF",
- .wakeup = 0,
- }, {
- .type = EV_KEY,
- .code = KEY_V,
- .gpio = 2,
- .desc = "Wheel View",
- .wakeup = 0,
- }, {
- .type = EV_KEY,
- .code = KEY_M,
- .gpio = 3,
- .desc = "Wheel Menu",
- .wakeup = 0,
- }, {
- .type = EV_KEY,
- .code = KEY_UP,
- .gpio = 32,
- .desc = "Nav Pad Up",
- .wakeup = 0,
- }, {
- .type = EV_KEY,
- .code = KEY_RIGHT,
- .gpio = 33,
- .desc = "Nav Pad Right",
- .wakeup = 0,
- }, {
- .type = EV_KEY,
- .code = KEY_DOWN,
- .gpio = 34,
- .desc = "Nav Pad Down",
- .wakeup = 0,
- }, {
- .type = EV_KEY,
- .code = KEY_LEFT,
- .gpio = 35,
- .desc = "Nav Pad Left",
- .wakeup = 0,
- }, {
- .type = EV_KEY,
- .code = KEY_ENTER,
- .gpio = 38,
- .desc = "Nav Pad Ok",
- .wakeup = 0,
- }, {
- .type = EV_KEY,
- .code = KEY_O,
- .gpio = 39,
- .desc = "Wheel Off",
- .wakeup = 0,
- }, {
- .type = EV_KEY,
- .code = BTN_FORWARD,
- .gpio = 50,
- .desc = "Focus Forward",
- .wakeup = 0,
- }, {
- .type = EV_KEY,
- .code = BTN_BACK,
- .gpio = 51,
- .desc = "Focus Backward",
- .wakeup = 0,
- }, {
- .type = EV_KEY,
- .code = BTN_MIDDLE,
- .gpio = 52,
- .desc = "Release Half",
- .wakeup = 0,
- }, {
- .type = EV_KEY,
- .code = BTN_EXTRA,
- .gpio = 53,
- .desc = "Release Full",
- .wakeup = 0,
- },
-};
-
-static struct gpio_keys_platform_data pcm037_gpio_keys_platform_data = {
- .buttons = pcm037_gpio_keys,
- .nbuttons = ARRAY_SIZE(pcm037_gpio_keys),
- .rep = 0, /* No auto-repeat */
-};
-
-static struct platform_device pcm037_gpio_keys_device = {
- .name = "gpio-keys",
- .id = -1,
- .dev = {
- .platform_data = &pcm037_gpio_keys_platform_data,
- },
-};
-
-static int __init eet_init_devices(void)
-{
- if (!machine_is_pcm037() || pcm037_variant() != PCM037_EET)
- return 0;
-
- mxc_iomux_setup_multiple_pins(pcm037_eet_pins,
- ARRAY_SIZE(pcm037_eet_pins), "pcm037_eet");
-
- /* SPI */
- spi_register_board_info(pcm037_spi_dev, ARRAY_SIZE(pcm037_spi_dev));
- imx31_add_spi_imx0(&pcm037_spi1_pdata);
-
- platform_device_register(&pcm037_gpio_keys_device);
-
- return 0;
-}
-
-late_initcall(eet_init_devices);
diff --git a/arch/arm/mach-mx3/mach-pcm043.c b/arch/arm/mach-mx3/mach-pcm043.c
deleted file mode 100644
index 036ba1a..0000000
--- a/arch/arm/mach-mx3/mach-pcm043.c
+++ /dev/null
@@ -1,428 +0,0 @@
-/*
- * Copyright (C) 2009 Sascha Hauer, Pengutronix
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/types.h>
-#include <linux/init.h>
-
-#include <linux/platform_device.h>
-#include <linux/mtd/physmap.h>
-#include <linux/mtd/plat-ram.h>
-#include <linux/memory.h>
-#include <linux/gpio.h>
-#include <linux/smc911x.h>
-#include <linux/interrupt.h>
-#include <linux/delay.h>
-#include <linux/i2c.h>
-#include <linux/i2c/at24.h>
-#include <linux/usb/otg.h>
-#include <linux/usb/ulpi.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <asm/mach/map.h>
-
-#include <mach/hardware.h>
-#include <mach/common.h>
-#include <mach/iomux-mx35.h>
-#include <mach/ipu.h>
-#include <mach/mx3fb.h>
-#include <mach/ulpi.h>
-#include <mach/audmux.h>
-#include <mach/esdhc.h>
-
-#include "devices-imx35.h"
-#include "devices.h"
-
-static const struct fb_videomode fb_modedb[] = {
- {
- /* 240x320 @ 60 Hz */
- .name = "Sharp-LQ035Q7",
- .refresh = 60,
- .xres = 240,
- .yres = 320,
- .pixclock = 185925,
- .left_margin = 9,
- .right_margin = 16,
- .upper_margin = 7,
- .lower_margin = 9,
- .hsync_len = 1,
- .vsync_len = 1,
- .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_SHARP_MODE | FB_SYNC_CLK_INVERT | FB_SYNC_CLK_IDLE_EN,
- .vmode = FB_VMODE_NONINTERLACED,
- .flag = 0,
- }, {
- /* 240x320 @ 60 Hz */
- .name = "TX090",
- .refresh = 60,
- .xres = 240,
- .yres = 320,
- .pixclock = 38255,
- .left_margin = 144,
- .right_margin = 0,
- .upper_margin = 7,
- .lower_margin = 40,
- .hsync_len = 96,
- .vsync_len = 1,
- .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH,
- .vmode = FB_VMODE_NONINTERLACED,
- .flag = 0,
- },
-};
-
-static struct ipu_platform_data mx3_ipu_data = {
- .irq_base = MXC_IPU_IRQ_START,
-};
-
-static struct mx3fb_platform_data mx3fb_pdata = {
- .dma_dev = &mx3_ipu.dev,
- .name = "Sharp-LQ035Q7",
- .mode = fb_modedb,
- .num_modes = ARRAY_SIZE(fb_modedb),
-};
-
-static struct physmap_flash_data pcm043_flash_data = {
- .width = 2,
-};
-
-static struct resource pcm043_flash_resource = {
- .start = 0xa0000000,
- .end = 0xa1ffffff,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device pcm043_flash = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &pcm043_flash_data,
- },
- .resource = &pcm043_flash_resource,
- .num_resources = 1,
-};
-
-static const struct imxuart_platform_data uart_pdata __initconst = {
- .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static const struct imxi2c_platform_data pcm043_i2c0_data __initconst = {
- .bitrate = 50000,
-};
-
-static struct at24_platform_data board_eeprom = {
- .byte_len = 4096,
- .page_size = 32,
- .flags = AT24_FLAG_ADDR16,
-};
-
-static struct i2c_board_info pcm043_i2c_devices[] = {
- {
- I2C_BOARD_INFO("at24", 0x52), /* E0=0, E1=1, E2=0 */
- .platform_data = &board_eeprom,
- }, {
- I2C_BOARD_INFO("pcf8563", 0x51),
- }
-};
-
-static struct platform_device *devices[] __initdata = {
- &pcm043_flash,
-};
-
-static iomux_v3_cfg_t pcm043_pads[] = {
- /* UART1 */
- MX35_PAD_CTS1__UART1_CTS,
- MX35_PAD_RTS1__UART1_RTS,
- MX35_PAD_TXD1__UART1_TXD_MUX,
- MX35_PAD_RXD1__UART1_RXD_MUX,
- /* UART2 */
- MX35_PAD_CTS2__UART2_CTS,
- MX35_PAD_RTS2__UART2_RTS,
- MX35_PAD_TXD2__UART2_TXD_MUX,
- MX35_PAD_RXD2__UART2_RXD_MUX,
- /* FEC */
- MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
- MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
- MX35_PAD_FEC_RX_DV__FEC_RX_DV,
- MX35_PAD_FEC_COL__FEC_COL,
- MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
- MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
- MX35_PAD_FEC_TX_EN__FEC_TX_EN,
- MX35_PAD_FEC_MDC__FEC_MDC,
- MX35_PAD_FEC_MDIO__FEC_MDIO,
- MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
- MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
- MX35_PAD_FEC_CRS__FEC_CRS,
- MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
- MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
- MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
- MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
- MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
- MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
- /* I2C1 */
- MX35_PAD_I2C1_CLK__I2C1_SCL,
- MX35_PAD_I2C1_DAT__I2C1_SDA,
- /* Display */
- MX35_PAD_LD0__IPU_DISPB_DAT_0,
- MX35_PAD_LD1__IPU_DISPB_DAT_1,
- MX35_PAD_LD2__IPU_DISPB_DAT_2,
- MX35_PAD_LD3__IPU_DISPB_DAT_3,
- MX35_PAD_LD4__IPU_DISPB_DAT_4,
- MX35_PAD_LD5__IPU_DISPB_DAT_5,
- MX35_PAD_LD6__IPU_DISPB_DAT_6,
- MX35_PAD_LD7__IPU_DISPB_DAT_7,
- MX35_PAD_LD8__IPU_DISPB_DAT_8,
- MX35_PAD_LD9__IPU_DISPB_DAT_9,
- MX35_PAD_LD10__IPU_DISPB_DAT_10,
- MX35_PAD_LD11__IPU_DISPB_DAT_11,
- MX35_PAD_LD12__IPU_DISPB_DAT_12,
- MX35_PAD_LD13__IPU_DISPB_DAT_13,
- MX35_PAD_LD14__IPU_DISPB_DAT_14,
- MX35_PAD_LD15__IPU_DISPB_DAT_15,
- MX35_PAD_LD16__IPU_DISPB_DAT_16,
- MX35_PAD_LD17__IPU_DISPB_DAT_17,
- MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC,
- MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK,
- MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY,
- MX35_PAD_CONTRAST__IPU_DISPB_CONTR,
- MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC,
- MX35_PAD_D3_REV__IPU_DISPB_D3_REV,
- MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS,
- /* gpio */
- MX35_PAD_ATA_CS0__GPIO2_6,
- /* USB host */
- MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR,
- MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC,
- /* SSI */
- MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS,
- MX35_PAD_STXD4__AUDMUX_AUD4_TXD,
- MX35_PAD_SRXD4__AUDMUX_AUD4_RXD,
- MX35_PAD_SCK4__AUDMUX_AUD4_TXC,
- /* CAN2 */
- MX35_PAD_TX5_RX0__CAN2_TXCAN,
- MX35_PAD_TX4_RX1__CAN2_RXCAN,
- /* esdhc */
- MX35_PAD_SD1_CMD__ESDHC1_CMD,
- MX35_PAD_SD1_CLK__ESDHC1_CLK,
- MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
- MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
- MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
- MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
- MX35_PAD_ATA_DATA10__GPIO2_23, /* WriteProtect */
- MX35_PAD_ATA_DATA11__GPIO2_24, /* CardDetect */
-};
-
-#define AC97_GPIO_TXFS IMX_GPIO_NR(2, 31)
-#define AC97_GPIO_TXD IMX_GPIO_NR(2, 28)
-#define AC97_GPIO_RESET IMX_GPIO_NR(2, 0)
-#define SD1_GPIO_WP IMX_GPIO_NR(2, 23)
-#define SD1_GPIO_CD IMX_GPIO_NR(2, 24)
-
-static void pcm043_ac97_warm_reset(struct snd_ac97 *ac97)
-{
- iomux_v3_cfg_t txfs_gpio = MX35_PAD_STXFS4__GPIO2_31;
- iomux_v3_cfg_t txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS;
- int ret;
-
- ret = gpio_request(AC97_GPIO_TXFS, "SSI");
- if (ret) {
- printk("failed to get GPIO_TXFS: %d\n", ret);
- return;
- }
-
- mxc_iomux_v3_setup_pad(txfs_gpio);
-
- /* warm reset */
- gpio_direction_output(AC97_GPIO_TXFS, 1);
- udelay(2);
- gpio_set_value(AC97_GPIO_TXFS, 0);
-
- gpio_free(AC97_GPIO_TXFS);
- mxc_iomux_v3_setup_pad(txfs);
-}
-
-static void pcm043_ac97_cold_reset(struct snd_ac97 *ac97)
-{
- iomux_v3_cfg_t txfs_gpio = MX35_PAD_STXFS4__GPIO2_31;
- iomux_v3_cfg_t txfs = MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS;
- iomux_v3_cfg_t txd_gpio = MX35_PAD_STXD4__GPIO2_28;
- iomux_v3_cfg_t txd = MX35_PAD_STXD4__AUDMUX_AUD4_TXD;
- iomux_v3_cfg_t reset_gpio = MX35_PAD_SD2_CMD__GPIO2_0;
- int ret;
-
- ret = gpio_request(AC97_GPIO_TXFS, "SSI");
- if (ret)
- goto err1;
-
- ret = gpio_request(AC97_GPIO_TXD, "SSI");
- if (ret)
- goto err2;
-
- ret = gpio_request(AC97_GPIO_RESET, "SSI");
- if (ret)
- goto err3;
-
- mxc_iomux_v3_setup_pad(txfs_gpio);
- mxc_iomux_v3_setup_pad(txd_gpio);
- mxc_iomux_v3_setup_pad(reset_gpio);
-
- gpio_direction_output(AC97_GPIO_TXFS, 0);
- gpio_direction_output(AC97_GPIO_TXD, 0);
-
- /* cold reset */
- gpio_direction_output(AC97_GPIO_RESET, 0);
- udelay(10);
- gpio_direction_output(AC97_GPIO_RESET, 1);
-
- mxc_iomux_v3_setup_pad(txd);
- mxc_iomux_v3_setup_pad(txfs);
-
- gpio_free(AC97_GPIO_RESET);
-err3:
- gpio_free(AC97_GPIO_TXD);
-err2:
- gpio_free(AC97_GPIO_TXFS);
-err1:
- if (ret)
- printk("%s failed with %d\n", __func__, ret);
- mdelay(1);
-}
-
-static const struct imx_ssi_platform_data pcm043_ssi_pdata __initconst = {
- .ac97_reset = pcm043_ac97_cold_reset,
- .ac97_warm_reset = pcm043_ac97_warm_reset,
- .flags = IMX_SSI_USE_AC97,
-};
-
-static const struct mxc_nand_platform_data
-pcm037_nand_board_info __initconst = {
- .width = 1,
- .hw_ecc = 1,
-};
-
-static int pcm043_otg_init(struct platform_device *pdev)
-{
- return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
-}
-
-static struct mxc_usbh_platform_data otg_pdata __initdata = {
- .init = pcm043_otg_init,
- .portsc = MXC_EHCI_MODE_UTMI,
-};
-
-static int pcm043_usbh1_init(struct platform_device *pdev)
-{
- return mx35_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_SINGLE_UNI |
- MXC_EHCI_INTERNAL_PHY | MXC_EHCI_IPPUE_DOWN);
-}
-
-static const struct mxc_usbh_platform_data usbh1_pdata __initconst = {
- .init = pcm043_usbh1_init,
- .portsc = MXC_EHCI_MODE_SERIAL,
-};
-
-static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
- .operating_mode = FSL_USB2_DR_DEVICE,
- .phy_mode = FSL_USB2_PHY_UTMI,
-};
-
-static int otg_mode_host;
-
-static int __init pcm043_otg_mode(char *options)
-{
- if (!strcmp(options, "host"))
- otg_mode_host = 1;
- else if (!strcmp(options, "device"))
- otg_mode_host = 0;
- else
- pr_info("otg_mode neither \"host\" nor \"device\". "
- "Defaulting to device\n");
- return 0;
-}
-__setup("otg_mode=", pcm043_otg_mode);
-
-static struct esdhc_platform_data sd1_pdata = {
- .wp_gpio = SD1_GPIO_WP,
- .cd_gpio = SD1_GPIO_CD,
-};
-
-/*
- * Board specific initialization.
- */
-static void __init pcm043_init(void)
-{
- mxc_iomux_v3_setup_multiple_pads(pcm043_pads, ARRAY_SIZE(pcm043_pads));
-
- mxc_audmux_v2_configure_port(3,
- MXC_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
- MXC_AUDMUX_V2_PTCR_TFSEL(0) |
- MXC_AUDMUX_V2_PTCR_TFSDIR,
- MXC_AUDMUX_V2_PDCR_RXDSEL(0));
-
- mxc_audmux_v2_configure_port(0,
- MXC_AUDMUX_V2_PTCR_SYN | /* 4wire mode */
- MXC_AUDMUX_V2_PTCR_TCSEL(3) |
- MXC_AUDMUX_V2_PTCR_TCLKDIR, /* clock is output */
- MXC_AUDMUX_V2_PDCR_RXDSEL(3));
-
- imx35_add_fec(NULL);
- platform_add_devices(devices, ARRAY_SIZE(devices));
- imx35_add_imx2_wdt(NULL);
-
- imx35_add_imx_uart0(&uart_pdata);
- imx35_add_mxc_nand(&pcm037_nand_board_info);
- imx35_add_imx_ssi(0, &pcm043_ssi_pdata);
-
- imx35_add_imx_uart1(&uart_pdata);
-
- i2c_register_board_info(0, pcm043_i2c_devices,
- ARRAY_SIZE(pcm043_i2c_devices));
-
- imx35_add_imx_i2c0(&pcm043_i2c0_data);
-
- mxc_register_device(&mx3_ipu, &mx3_ipu_data);
- mxc_register_device(&mx3_fb, &mx3fb_pdata);
-
- if (otg_mode_host) {
- otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
- ULPI_OTG_DRVVBUS_EXT);
- if (otg_pdata.otg)
- imx35_add_mxc_ehci_otg(&otg_pdata);
- }
- imx35_add_mxc_ehci_hs(&usbh1_pdata);
-
- if (!otg_mode_host)
- imx35_add_fsl_usb2_udc(&otg_device_pdata);
-
- imx35_add_flexcan1(NULL);
- imx35_add_sdhci_esdhc_imx(0, &sd1_pdata);
-}
-
-static void __init pcm043_timer_init(void)
-{
- mx35_clocks_init();
-}
-
-struct sys_timer pcm043_timer = {
- .init = pcm043_timer_init,
-};
-
-MACHINE_START(PCM043, "Phytec Phycore pcm043")
- /* Maintainer: Pengutronix */
- .boot_params = MX3x_PHYS_OFFSET + 0x100,
- .map_io = mx35_map_io,
- .init_early = imx35_init_early,
- .init_irq = mx35_init_irq,
- .timer = &pcm043_timer,
- .init_machine = pcm043_init,
-MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-qong.c b/arch/arm/mach-mx3/mach-qong.c
deleted file mode 100644
index 17f758b..0000000
--- a/arch/arm/mach-mx3/mach-qong.c
+++ /dev/null
@@ -1,270 +0,0 @@
-/*
- * Copyright (C) 2009 Ilya Yanok, Emcraft Systems Ltd, <yanok@emcraft.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/memory.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/physmap.h>
-#include <linux/mtd/nand.h>
-#include <linux/gpio.h>
-
-#include <mach/hardware.h>
-#include <mach/irqs.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-#include <asm/mach/map.h>
-#include <mach/common.h>
-#include <asm/page.h>
-#include <asm/setup.h>
-#include <mach/iomux-mx3.h>
-
-#include "devices-imx31.h"
-#include "devices.h"
-
-/* FPGA defines */
-#define QONG_FPGA_VERSION(major, minor, rev) \
- (((major & 0xF) << 12) | ((minor & 0xF) << 8) | (rev & 0xFF))
-
-#define QONG_FPGA_BASEADDR MX31_CS1_BASE_ADDR
-#define QONG_FPGA_PERIPH_SIZE (1 << 24)
-
-#define QONG_FPGA_CTRL_BASEADDR QONG_FPGA_BASEADDR
-#define QONG_FPGA_CTRL_SIZE 0x10
-/* FPGA control registers */
-#define QONG_FPGA_CTRL_VERSION 0x00
-
-#define QONG_DNET_ID 1
-#define QONG_DNET_BASEADDR \
- (QONG_FPGA_BASEADDR + QONG_DNET_ID * QONG_FPGA_PERIPH_SIZE)
-#define QONG_DNET_SIZE 0x00001000
-
-#define QONG_FPGA_IRQ IOMUX_TO_IRQ(MX31_PIN_DTR_DCE1)
-
-static const struct imxuart_platform_data uart_pdata __initconst = {
- .flags = IMXUART_HAVE_RTSCTS,
-};
-
-static int uart_pins[] = {
- MX31_PIN_CTS1__CTS1,
- MX31_PIN_RTS1__RTS1,
- MX31_PIN_TXD1__TXD1,
- MX31_PIN_RXD1__RXD1
-};
-
-static inline void __init mxc_init_imx_uart(void)
-{
- mxc_iomux_setup_multiple_pins(uart_pins, ARRAY_SIZE(uart_pins),
- "uart-0");
- imx31_add_imx_uart0(&uart_pdata);
-}
-
-static struct resource dnet_resources[] = {
- {
- .name = "dnet-memory",
- .start = QONG_DNET_BASEADDR,
- .end = QONG_DNET_BASEADDR + QONG_DNET_SIZE - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = QONG_FPGA_IRQ,
- .end = QONG_FPGA_IRQ,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device dnet_device = {
- .name = "dnet",
- .id = -1,
- .num_resources = ARRAY_SIZE(dnet_resources),
- .resource = dnet_resources,
-};
-
-static int __init qong_init_dnet(void)
-{
- int ret;
-
- ret = platform_device_register(&dnet_device);
- return ret;
-}
-
-/* MTD NOR flash */
-
-static struct physmap_flash_data qong_flash_data = {
- .width = 2,
-};
-
-static struct resource qong_flash_resource = {
- .start = MX31_CS0_BASE_ADDR,
- .end = MX31_CS0_BASE_ADDR + SZ_128M - 1,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device qong_nor_mtd_device = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &qong_flash_data,
- },
- .resource = &qong_flash_resource,
- .num_resources = 1,
-};
-
-static void qong_init_nor_mtd(void)
-{
- (void)platform_device_register(&qong_nor_mtd_device);
-}
-
-/*
- * Hardware specific access to control-lines
- */
-static void qong_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
-{
- struct nand_chip *nand_chip = mtd->priv;
-
- if (cmd == NAND_CMD_NONE)
- return;
-
- if (ctrl & NAND_CLE)
- writeb(cmd, nand_chip->IO_ADDR_W + (1 << 24));
- else
- writeb(cmd, nand_chip->IO_ADDR_W + (1 << 23));
-}
-
-/*
- * Read the Device Ready pin.
- */
-static int qong_nand_device_ready(struct mtd_info *mtd)
-{
- return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_NFRB));
-}
-
-static void qong_nand_select_chip(struct mtd_info *mtd, int chip)
-{
- if (chip >= 0)
- gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 0);
- else
- gpio_set_value(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 1);
-}
-
-static struct platform_nand_data qong_nand_data = {
- .chip = {
- .nr_chips = 1,
- .chip_delay = 20,
- .options = 0,
- },
- .ctrl = {
- .cmd_ctrl = qong_nand_cmd_ctrl,
- .dev_ready = qong_nand_device_ready,
- .select_chip = qong_nand_select_chip,
- }
-};
-
-static struct resource qong_nand_resource = {
- .start = MX31_CS3_BASE_ADDR,
- .end = MX31_CS3_BASE_ADDR + SZ_32M - 1,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device qong_nand_device = {
- .name = "gen_nand",
- .id = -1,
- .dev = {
- .platform_data = &qong_nand_data,
- },
- .num_resources = 1,
- .resource = &qong_nand_resource,
-};
-
-static void __init qong_init_nand_mtd(void)
-{
- /* init CS */
- mx31_setup_weimcs(3, 0x00004f00, 0x20013b31, 0x00020800);
- mxc_iomux_set_gpr(MUX_SDCTL_CSD1_SEL, true);
-
- /* enable pin */
- mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFCE_B, IOMUX_CONFIG_GPIO));
- if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), "nand_enable"))
- gpio_direction_output(IOMUX_TO_GPIO(MX31_PIN_NFCE_B), 0);
-
- /* ready/busy pin */
- mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFRB, IOMUX_CONFIG_GPIO));
- if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFRB), "nand_rdy"))
- gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_NFRB));
-
- /* write protect pin */
- mxc_iomux_mode(IOMUX_MODE(MX31_PIN_NFWP_B, IOMUX_CONFIG_GPIO));
- if (!gpio_request(IOMUX_TO_GPIO(MX31_PIN_NFWP_B), "nand_wp"))
- gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_NFWP_B));
-
- platform_device_register(&qong_nand_device);
-}
-
-static void __init qong_init_fpga(void)
-{
- void __iomem *regs;
- u32 fpga_ver;
-
- regs = ioremap(QONG_FPGA_CTRL_BASEADDR, QONG_FPGA_CTRL_SIZE);
- if (!regs) {
- printk(KERN_ERR "%s: failed to map registers, aborting.\n",
- __func__);
- return;
- }
-
- fpga_ver = readl(regs + QONG_FPGA_CTRL_VERSION);
- iounmap(regs);
- printk(KERN_INFO "Qong FPGA version %d.%d.%d\n",
- (fpga_ver & 0xF000) >> 12,
- (fpga_ver & 0x0F00) >> 8, fpga_ver & 0x00FF);
- if (fpga_ver < QONG_FPGA_VERSION(0, 8, 7)) {
- printk(KERN_ERR "qong: Unexpected FPGA version, FPGA-based "
- "devices won't be registered!\n");
- return;
- }
-
- /* register FPGA-based devices */
- qong_init_nand_mtd();
- qong_init_dnet();
-}
-
-/*
- * Board specific initialization.
- */
-static void __init qong_init(void)
-{
- mxc_init_imx_uart();
- qong_init_nor_mtd();
- qong_init_fpga();
-}
-
-static void __init qong_timer_init(void)
-{
- mx31_clocks_init(26000000);
-}
-
-static struct sys_timer qong_timer = {
- .init = qong_timer_init,
-};
-
-MACHINE_START(QONG, "Dave/DENX QongEVB-LITE")
- /* Maintainer: DENX Software Engineering GmbH */
- .boot_params = MX3x_PHYS_OFFSET + 0x100,
- .map_io = mx31_map_io,
- .init_early = imx31_init_early,
- .init_irq = mx31_init_irq,
- .timer = &qong_timer,
- .init_machine = qong_init,
-MACHINE_END
diff --git a/arch/arm/mach-mx3/mach-vpr200.c b/arch/arm/mach-mx3/mach-vpr200.c
deleted file mode 100644
index 47a69cb..0000000
--- a/arch/arm/mach-mx3/mach-vpr200.c
+++ /dev/null
@@ -1,333 +0,0 @@
-/*
- * Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (C) 2009 Marc Kleine-Budde, Pengutronix
- * Copyright 2010 Creative Product Design
- *
- * Derived from mx35 3stack.
- * Original author: Fabio Estevam <fabio.estevam@freescale.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/mtd/physmap.h>
-#include <linux/memory.h>
-#include <linux/gpio.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/time.h>
-
-#include <mach/hardware.h>
-#include <mach/common.h>
-#include <mach/iomux-mx35.h>
-#include <mach/irqs.h>
-#include <mach/ipu.h>
-#include <mach/mx3fb.h>
-
-#include <linux/i2c.h>
-#include <linux/i2c/at24.h>
-#include <linux/mfd/mc13xxx.h>
-#include <linux/gpio_keys.h>
-
-#include "devices-imx35.h"
-#include "devices.h"
-
-#define GPIO_LCDPWR IMX_GPIO_NR(1, 2)
-#define GPIO_PMIC_INT IMX_GPIO_NR(2, 0)
-
-#define GPIO_BUTTON1 IMX_GPIO_NR(1, 4)
-#define GPIO_BUTTON2 IMX_GPIO_NR(1, 5)
-#define GPIO_BUTTON3 IMX_GPIO_NR(1, 7)
-#define GPIO_BUTTON4 IMX_GPIO_NR(1, 8)
-#define GPIO_BUTTON5 IMX_GPIO_NR(1, 9)
-#define GPIO_BUTTON6 IMX_GPIO_NR(1, 10)
-#define GPIO_BUTTON7 IMX_GPIO_NR(1, 11)
-#define GPIO_BUTTON8 IMX_GPIO_NR(1, 12)
-
-static const struct fb_videomode fb_modedb[] = {
- {
- /* 800x480 @ 60 Hz */
- .name = "PT0708048",
- .refresh = 60,
- .xres = 800,
- .yres = 480,
- .pixclock = KHZ2PICOS(33260),
- .left_margin = 50,
- .right_margin = 156,
- .upper_margin = 10,
- .lower_margin = 10,
- .hsync_len = 1, /* note: DE only display */
- .vsync_len = 1, /* note: DE only display */
- .sync = FB_SYNC_CLK_IDLE_EN | FB_SYNC_OE_ACT_HIGH,
- .vmode = FB_VMODE_NONINTERLACED,
- .flag = 0,
- }, {
- /* 800x480 @ 60 Hz */
- .name = "CTP-CLAA070LC0ACW",
- .refresh = 60,
- .xres = 800,
- .yres = 480,
- .pixclock = KHZ2PICOS(27000),
- .left_margin = 50,
- .right_margin = 50, /* whole line should have 900 clocks */
- .upper_margin = 10,
- .lower_margin = 10, /* whole frame should have 500 lines */
- .hsync_len = 1, /* note: DE only display */
- .vsync_len = 1, /* note: DE only display */
- .sync = FB_SYNC_CLK_IDLE_EN | FB_SYNC_OE_ACT_HIGH,
- .vmode = FB_VMODE_NONINTERLACED,
- .flag = 0,
- }
-};
-
-static struct ipu_platform_data mx3_ipu_data = {
- .irq_base = MXC_IPU_IRQ_START,
-};
-
-static struct mx3fb_platform_data mx3fb_pdata = {
- .dma_dev = &mx3_ipu.dev,
- .name = "PT0708048",
- .mode = fb_modedb,
- .num_modes = ARRAY_SIZE(fb_modedb),
-};
-
-static struct physmap_flash_data vpr200_flash_data = {
- .width = 2,
-};
-
-static struct resource vpr200_flash_resource = {
- .start = MX35_CS0_BASE_ADDR,
- .end = MX35_CS0_BASE_ADDR + SZ_64M - 1,
- .flags = IORESOURCE_MEM,
-};
-
-static struct platform_device vpr200_flash = {
- .name = "physmap-flash",
- .id = 0,
- .dev = {
- .platform_data = &vpr200_flash_data,
- },
- .resource = &vpr200_flash_resource,
- .num_resources = 1,
-};
-
-static const struct mxc_nand_platform_data
- vpr200_nand_board_info __initconst = {
- .width = 1,
- .hw_ecc = 1,
- .flash_bbt = 1,
-};
-
-#define VPR_KEY_DEBOUNCE 500
-static struct gpio_keys_button vpr200_gpio_keys_table[] = {
- {KEY_F2, GPIO_BUTTON1, 1, "vpr-keys: F2", 0, VPR_KEY_DEBOUNCE},
- {KEY_F3, GPIO_BUTTON2, 1, "vpr-keys: F3", 0, VPR_KEY_DEBOUNCE},
- {KEY_F4, GPIO_BUTTON3, 1, "vpr-keys: F4", 0, VPR_KEY_DEBOUNCE},
- {KEY_F5, GPIO_BUTTON4, 1, "vpr-keys: F5", 0, VPR_KEY_DEBOUNCE},
- {KEY_F6, GPIO_BUTTON5, 1, "vpr-keys: F6", 0, VPR_KEY_DEBOUNCE},
- {KEY_F7, GPIO_BUTTON6, 1, "vpr-keys: F7", 0, VPR_KEY_DEBOUNCE},
- {KEY_F8, GPIO_BUTTON7, 1, "vpr-keys: F8", 1, VPR_KEY_DEBOUNCE},
- {KEY_F9, GPIO_BUTTON8, 1, "vpr-keys: F9", 1, VPR_KEY_DEBOUNCE},
-};
-
-static struct gpio_keys_platform_data vpr200_gpio_keys_data = {
- .buttons = vpr200_gpio_keys_table,
- .nbuttons = ARRAY_SIZE(vpr200_gpio_keys_table),
-};
-
-static struct platform_device vpr200_device_gpiokeys = {
- .name = "gpio-keys",
- .dev = {
- .platform_data = &vpr200_gpio_keys_data,
- }
-};
-
-static struct mc13xxx_platform_data vpr200_pmic = {
- .flags = MC13XXX_USE_ADC | MC13XXX_USE_TOUCHSCREEN,
-};
-
-static const struct imxi2c_platform_data vpr200_i2c0_data __initconst = {
- .bitrate = 50000,
-};
-
-static struct at24_platform_data vpr200_eeprom = {
- .byte_len = 2048 / 8,
- .page_size = 1,
-};
-
-static struct i2c_board_info vpr200_i2c_devices[] = {
- {
- I2C_BOARD_INFO("at24", 0x50), /* E0=0, E1=0, E2=0 */
- .platform_data = &vpr200_eeprom,
- }, {
- I2C_BOARD_INFO("mc13892", 0x08),
- .platform_data = &vpr200_pmic,
- .irq = gpio_to_irq(GPIO_PMIC_INT),
- }
-};
-
-static iomux_v3_cfg_t vpr200_pads[] = {
- /* UART1 */
- MX35_PAD_TXD1__UART1_TXD_MUX,
- MX35_PAD_RXD1__UART1_RXD_MUX,
- /* UART3 */
- MX35_PAD_ATA_DATA10__UART3_RXD_MUX,
- MX35_PAD_ATA_DATA11__UART3_TXD_MUX,
- /* FEC */
- MX35_PAD_FEC_TX_CLK__FEC_TX_CLK,
- MX35_PAD_FEC_RX_CLK__FEC_RX_CLK,
- MX35_PAD_FEC_RX_DV__FEC_RX_DV,
- MX35_PAD_FEC_COL__FEC_COL,
- MX35_PAD_FEC_RDATA0__FEC_RDATA_0,
- MX35_PAD_FEC_TDATA0__FEC_TDATA_0,
- MX35_PAD_FEC_TX_EN__FEC_TX_EN,
- MX35_PAD_FEC_MDC__FEC_MDC,
- MX35_PAD_FEC_MDIO__FEC_MDIO,
- MX35_PAD_FEC_TX_ERR__FEC_TX_ERR,
- MX35_PAD_FEC_RX_ERR__FEC_RX_ERR,
- MX35_PAD_FEC_CRS__FEC_CRS,
- MX35_PAD_FEC_RDATA1__FEC_RDATA_1,
- MX35_PAD_FEC_TDATA1__FEC_TDATA_1,
- MX35_PAD_FEC_RDATA2__FEC_RDATA_2,
- MX35_PAD_FEC_TDATA2__FEC_TDATA_2,
- MX35_PAD_FEC_RDATA3__FEC_RDATA_3,
- MX35_PAD_FEC_TDATA3__FEC_TDATA_3,
- /* Display */
- MX35_PAD_LD0__IPU_DISPB_DAT_0,
- MX35_PAD_LD1__IPU_DISPB_DAT_1,
- MX35_PAD_LD2__IPU_DISPB_DAT_2,
- MX35_PAD_LD3__IPU_DISPB_DAT_3,
- MX35_PAD_LD4__IPU_DISPB_DAT_4,
- MX35_PAD_LD5__IPU_DISPB_DAT_5,
- MX35_PAD_LD6__IPU_DISPB_DAT_6,
- MX35_PAD_LD7__IPU_DISPB_DAT_7,
- MX35_PAD_LD8__IPU_DISPB_DAT_8,
- MX35_PAD_LD9__IPU_DISPB_DAT_9,
- MX35_PAD_LD10__IPU_DISPB_DAT_10,
- MX35_PAD_LD11__IPU_DISPB_DAT_11,
- MX35_PAD_LD12__IPU_DISPB_DAT_12,
- MX35_PAD_LD13__IPU_DISPB_DAT_13,
- MX35_PAD_LD14__IPU_DISPB_DAT_14,
- MX35_PAD_LD15__IPU_DISPB_DAT_15,
- MX35_PAD_LD16__IPU_DISPB_DAT_16,
- MX35_PAD_LD17__IPU_DISPB_DAT_17,
- MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK,
- MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY,
- MX35_PAD_CONTRAST__IPU_DISPB_CONTR,
- /* LCD Enable */
- MX35_PAD_D3_VSYNC__GPIO1_2,
- /* USBOTG */
- MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR,
- MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC,
- /* SDCARD */
- MX35_PAD_SD1_CMD__ESDHC1_CMD,
- MX35_PAD_SD1_CLK__ESDHC1_CLK,
- MX35_PAD_SD1_DATA0__ESDHC1_DAT0,
- MX35_PAD_SD1_DATA1__ESDHC1_DAT1,
- MX35_PAD_SD1_DATA2__ESDHC1_DAT2,
- MX35_PAD_SD1_DATA3__ESDHC1_DAT3,
- /* PMIC */
- MX35_PAD_GPIO2_0__GPIO2_0,
- /* GPIO keys */
- MX35_PAD_SCKR__GPIO1_4,
- MX35_PAD_COMPARE__GPIO1_5,
- MX35_PAD_SCKT__GPIO1_7,
- MX35_PAD_FST__GPIO1_8,
- MX35_PAD_HCKT__GPIO1_9,
- MX35_PAD_TX5_RX0__GPIO1_10,
- MX35_PAD_TX4_RX1__GPIO1_11,
- MX35_PAD_TX3_RX2__GPIO1_12,
-};
-
-/* USB Device config */
-static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
- .operating_mode = FSL_USB2_DR_DEVICE,
- .phy_mode = FSL_USB2_PHY_UTMI,
- .workaround = FLS_USB2_WORKAROUND_ENGCM09152,
-};
-
-static int vpr200_usbh_init(struct platform_device *pdev)
-{
- return mx35_initialize_usb_hw(pdev->id,
- MXC_EHCI_INTERFACE_SINGLE_UNI | MXC_EHCI_INTERNAL_PHY);
-}
-
-/* USB HOST config */
-static const struct mxc_usbh_platform_data usb_host_pdata __initconst = {
- .init = vpr200_usbh_init,
- .portsc = MXC_EHCI_MODE_SERIAL,
-};
-
-static struct platform_device *devices[] __initdata = {
- &vpr200_flash,
- &vpr200_device_gpiokeys,
-};
-
-/*
- * Board specific initialization.
- */
-static void __init vpr200_board_init(void)
-{
- mxc_iomux_v3_setup_multiple_pads(vpr200_pads, ARRAY_SIZE(vpr200_pads));
-
- imx35_add_fec(NULL);
- imx35_add_imx2_wdt(NULL);
-
- platform_add_devices(devices, ARRAY_SIZE(devices));
-
- if (0 != gpio_request(GPIO_LCDPWR, "LCDPWR"))
- printk(KERN_WARNING "vpr200: Couldn't get LCDPWR gpio\n");
- else
- gpio_direction_output(GPIO_LCDPWR, 0);
-
- if (0 != gpio_request(GPIO_PMIC_INT, "PMIC_INT"))
- printk(KERN_WARNING "vpr200: Couldn't get PMIC_INT gpio\n");
- else
- gpio_direction_input(GPIO_PMIC_INT);
-
- imx35_add_imx_uart0(NULL);
- imx35_add_imx_uart2(NULL);
-
- mxc_register_device(&mx3_ipu, &mx3_ipu_data);
- mxc_register_device(&mx3_fb, &mx3fb_pdata);
-
- imx35_add_fsl_usb2_udc(&otg_device_pdata);
- imx35_add_mxc_ehci_hs(&usb_host_pdata);
-
- imx35_add_mxc_nand(&vpr200_nand_board_info);
- imx35_add_sdhci_esdhc_imx(0, NULL);
-
- i2c_register_board_info(0, vpr200_i2c_devices,
- ARRAY_SIZE(vpr200_i2c_devices));
-
- imx35_add_imx_i2c0(&vpr200_i2c0_data);
-}
-
-static void __init vpr200_timer_init(void)
-{
- mx35_clocks_init();
-}
-
-struct sys_timer vpr200_timer = {
- .init = vpr200_timer_init,
-};
-
-MACHINE_START(VPR200, "VPR200")
- /* Maintainer: Creative Product Design */
- .map_io = mx35_map_io,
- .init_early = imx35_init_early,
- .init_irq = mx35_init_irq,
- .timer = &vpr200_timer,
- .init_machine = vpr200_board_init,
-MACHINE_END
diff --git a/arch/arm/mach-mx3/mm.c b/arch/arm/mach-mx3/mm.c
deleted file mode 100644
index 54d7174..0000000
--- a/arch/arm/mach-mx3/mm.c
+++ /dev/null
@@ -1,141 +0,0 @@
-/*
- * Copyright (C) 1999,2000 Arm Limited
- * Copyright (C) 2000 Deep Blue Solutions Ltd
- * Copyright (C) 2002 Shane Nay (shane@minirl.com)
- * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * - add MX31 specific definitions
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/mm.h>
-#include <linux/init.h>
-#include <linux/err.h>
-
-#include <asm/pgtable.h>
-#include <asm/mach/map.h>
-#include <asm/hardware/cache-l2x0.h>
-
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <mach/iomux-v3.h>
-#include <mach/gpio.h>
-#include <mach/irqs.h>
-
-#ifdef CONFIG_SOC_IMX31
-static struct map_desc mx31_io_desc[] __initdata = {
- imx_map_entry(MX31, X_MEMC, MT_DEVICE),
- imx_map_entry(MX31, AVIC, MT_DEVICE_NONSHARED),
- imx_map_entry(MX31, AIPS1, MT_DEVICE_NONSHARED),
- imx_map_entry(MX31, AIPS2, MT_DEVICE_NONSHARED),
- imx_map_entry(MX31, SPBA0, MT_DEVICE_NONSHARED),
-};
-
-/*
- * This function initializes the memory map. It is called during the
- * system startup to create static physical to virtual memory mappings
- * for the IO modules.
- */
-void __init mx31_map_io(void)
-{
- iotable_init(mx31_io_desc, ARRAY_SIZE(mx31_io_desc));
-}
-
-void __init imx31_init_early(void)
-{
- mxc_set_cpu_type(MXC_CPU_MX31);
- mxc_arch_reset_init(MX31_IO_ADDRESS(MX31_WDOG_BASE_ADDR));
-}
-
-static struct mxc_gpio_port imx31_gpio_ports[] = {
- DEFINE_IMX_GPIO_PORT_IRQ(MX31, 0, 1, MX31_INT_GPIO1),
- DEFINE_IMX_GPIO_PORT_IRQ(MX31, 1, 2, MX31_INT_GPIO2),
- DEFINE_IMX_GPIO_PORT_IRQ(MX31, 2, 3, MX31_INT_GPIO3),
-};
-
-void __init mx31_init_irq(void)
-{
- mxc_init_irq(MX31_IO_ADDRESS(MX31_AVIC_BASE_ADDR));
- mxc_gpio_init(imx31_gpio_ports, ARRAY_SIZE(imx31_gpio_ports));
-}
-#endif /* ifdef CONFIG_SOC_IMX31 */
-
-#ifdef CONFIG_SOC_IMX35
-static struct map_desc mx35_io_desc[] __initdata = {
- imx_map_entry(MX35, X_MEMC, MT_DEVICE),
- imx_map_entry(MX35, AVIC, MT_DEVICE_NONSHARED),
- imx_map_entry(MX35, AIPS1, MT_DEVICE_NONSHARED),
- imx_map_entry(MX35, AIPS2, MT_DEVICE_NONSHARED),
- imx_map_entry(MX35, SPBA0, MT_DEVICE_NONSHARED),
-};
-
-void __init mx35_map_io(void)
-{
- iotable_init(mx35_io_desc, ARRAY_SIZE(mx35_io_desc));
-}
-
-void __init imx35_init_early(void)
-{
- mxc_set_cpu_type(MXC_CPU_MX35);
- mxc_iomux_v3_init(MX35_IO_ADDRESS(MX35_IOMUXC_BASE_ADDR));
- mxc_arch_reset_init(MX35_IO_ADDRESS(MX35_WDOG_BASE_ADDR));
-}
-
-static struct mxc_gpio_port imx35_gpio_ports[] = {
- DEFINE_IMX_GPIO_PORT_IRQ(MX35, 0, 1, MX35_INT_GPIO1),
- DEFINE_IMX_GPIO_PORT_IRQ(MX35, 1, 2, MX35_INT_GPIO2),
- DEFINE_IMX_GPIO_PORT_IRQ(MX35, 2, 3, MX35_INT_GPIO3),
-};
-
-void __init mx35_init_irq(void)
-{
- mxc_init_irq(MX35_IO_ADDRESS(MX35_AVIC_BASE_ADDR));
- mxc_gpio_init(imx35_gpio_ports, ARRAY_SIZE(imx35_gpio_ports));
-}
-#endif /* ifdef CONFIG_SOC_IMX35 */
-
-#ifdef CONFIG_CACHE_L2X0
-static int mxc_init_l2x0(void)
-{
- void __iomem *l2x0_base;
- void __iomem *clkctl_base;
-/*
- * First of all, we must repair broken chip settings. There are some
- * i.MX35 CPUs in the wild, comming with bogus L2 cache settings. These
- * misconfigured CPUs will run amok immediately when the L2 cache gets enabled.
- * Workaraound is to setup the correct register setting prior enabling the
- * L2 cache. This should not hurt already working CPUs, as they are using the
- * same value
- */
-#define L2_MEM_VAL 0x10
-
- clkctl_base = ioremap(MX35_CLKCTL_BASE_ADDR, 4096);
- if (clkctl_base != NULL) {
- writel(0x00000515, clkctl_base + L2_MEM_VAL);
- iounmap(clkctl_base);
- } else {
- pr_err("L2 cache: Cannot fix timing. Trying to continue without\n");
- }
-
- l2x0_base = ioremap(MX3x_L2CC_BASE_ADDR, 4096);
- if (IS_ERR(l2x0_base)) {
- printk(KERN_ERR "remapping L2 cache area failed with %ld\n",
- PTR_ERR(l2x0_base));
- return 0;
- }
-
- l2x0_init(l2x0_base, 0x00030024, 0x00000000);
-
- return 0;
-}
-
-arch_initcall(mxc_init_l2x0);
-#endif
diff --git a/arch/arm/mach-mx3/mx31lilly-db.c b/arch/arm/mach-mx3/mx31lilly-db.c
deleted file mode 100644
index 8f1a38e..0000000
--- a/arch/arm/mach-mx3/mx31lilly-db.c
+++ /dev/null
@@ -1,221 +0,0 @@
-/*
- * LILLY-1131 development board support
- *
- * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
- *
- * based on code for other MX31 boards,
- *
- * Copyright 2005-2007 Freescale Semiconductor
- * Copyright (c) 2009 Alberto Panizzo <maramaopercheseimorto@gmail.com>
- * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/gpio.h>
-#include <linux/platform_device.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-
-#include <mach/hardware.h>
-#include <mach/common.h>
-#include <mach/iomux-mx3.h>
-#include <mach/board-mx31lilly.h>
-#include <mach/mx3fb.h>
-#include <mach/ipu.h>
-
-#include "devices-imx31.h"
-#include "devices.h"
-
-/*
- * This file contains board-specific initialization routines for the
- * LILLY-1131 development board. If you design an own baseboard for the
- * module, use this file as base for support code.
- */
-
-static unsigned int lilly_db_board_pins[] __initdata = {
- MX31_PIN_CTS1__CTS1,
- MX31_PIN_RTS1__RTS1,
- MX31_PIN_TXD1__TXD1,
- MX31_PIN_RXD1__RXD1,
- MX31_PIN_CTS2__CTS2,
- MX31_PIN_RTS2__RTS2,
- MX31_PIN_TXD2__TXD2,
- MX31_PIN_RXD2__RXD2,
- MX31_PIN_CSPI3_MOSI__RXD3,
- MX31_PIN_CSPI3_MISO__TXD3,
- MX31_PIN_CSPI3_SCLK__RTS3,
- MX31_PIN_CSPI3_SPI_RDY__CTS3,
- MX31_PIN_SD1_DATA3__SD1_DATA3,
- MX31_PIN_SD1_DATA2__SD1_DATA2,
- MX31_PIN_SD1_DATA1__SD1_DATA1,
- MX31_PIN_SD1_DATA0__SD1_DATA0,
- MX31_PIN_SD1_CLK__SD1_CLK,
- MX31_PIN_SD1_CMD__SD1_CMD,
- MX31_PIN_LD0__LD0,
- MX31_PIN_LD1__LD1,
- MX31_PIN_LD2__LD2,
- MX31_PIN_LD3__LD3,
- MX31_PIN_LD4__LD4,
- MX31_PIN_LD5__LD5,
- MX31_PIN_LD6__LD6,
- MX31_PIN_LD7__LD7,
- MX31_PIN_LD8__LD8,
- MX31_PIN_LD9__LD9,
- MX31_PIN_LD10__LD10,
- MX31_PIN_LD11__LD11,
- MX31_PIN_LD12__LD12,
- MX31_PIN_LD13__LD13,
- MX31_PIN_LD14__LD14,
- MX31_PIN_LD15__LD15,
- MX31_PIN_LD16__LD16,
- MX31_PIN_LD17__LD17,
- MX31_PIN_VSYNC3__VSYNC3,
- MX31_PIN_HSYNC__HSYNC,
- MX31_PIN_FPSHIFT__FPSHIFT,
- MX31_PIN_DRDY0__DRDY0,
- MX31_PIN_CONTRAST__CONTRAST,
-};
-
-/* UART */
-static const struct imxuart_platform_data uart_pdata __initconst = {
- .flags = IMXUART_HAVE_RTSCTS,
-};
-
-/* MMC support */
-
-static int mxc_mmc1_get_ro(struct device *dev)
-{
- return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_LCS0));
-}
-
-static int gpio_det, gpio_wp;
-
-#define MMC_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
- PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
-
-static int mxc_mmc1_init(struct device *dev,
- irq_handler_t detect_irq, void *data)
-{
- int ret;
-
- gpio_det = IOMUX_TO_GPIO(MX31_PIN_GPIO1_1);
- gpio_wp = IOMUX_TO_GPIO(MX31_PIN_LCS0);
-
- mxc_iomux_set_pad(MX31_PIN_SD1_DATA0, MMC_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_SD1_DATA1, MMC_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_SD1_DATA2, MMC_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_SD1_DATA3, MMC_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_SD1_CLK, MMC_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_SD1_CMD, MMC_PAD_CFG);
-
- ret = gpio_request(gpio_det, "MMC detect");
- if (ret)
- return ret;
-
- ret = gpio_request(gpio_wp, "MMC w/p");
- if (ret)
- goto exit_free_det;
-
- gpio_direction_input(gpio_det);
- gpio_direction_input(gpio_wp);
-
- ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO1_1), detect_irq,
- IRQF_DISABLED | IRQF_TRIGGER_FALLING,
- "MMC detect", data);
- if (ret)
- goto exit_free_wp;
-
- return 0;
-
-exit_free_wp:
- gpio_free(gpio_wp);
-
-exit_free_det:
- gpio_free(gpio_det);
-
- return ret;
-}
-
-static void mxc_mmc1_exit(struct device *dev, void *data)
-{
- gpio_free(gpio_det);
- gpio_free(gpio_wp);
- free_irq(IOMUX_TO_IRQ(MX31_PIN_GPIO1_1), data);
-}
-
-static const struct imxmmc_platform_data mmc_pdata __initconst = {
- .get_ro = mxc_mmc1_get_ro,
- .init = mxc_mmc1_init,
- .exit = mxc_mmc1_exit,
-};
-
-/* Framebuffer support */
-static struct ipu_platform_data ipu_data __initdata = {
- .irq_base = MXC_IPU_IRQ_START,
-};
-
-static const struct fb_videomode fb_modedb = {
- /* 640x480 TFT panel (IPS-056T) */
- .name = "CRT-VGA",
- .refresh = 64,
- .xres = 640,
- .yres = 480,
- .pixclock = 30000,
- .left_margin = 200,
- .right_margin = 2,
- .upper_margin = 2,
- .lower_margin = 2,
- .hsync_len = 3,
- .vsync_len = 1,
- .sync = FB_SYNC_VERT_HIGH_ACT | FB_SYNC_OE_ACT_HIGH,
- .vmode = FB_VMODE_NONINTERLACED,
- .flag = 0,
-};
-
-static struct mx3fb_platform_data fb_pdata __initdata = {
- .dma_dev = &mx3_ipu.dev,
- .name = "CRT-VGA",
- .mode = &fb_modedb,
- .num_modes = 1,
-};
-
-#define LCD_VCC_EN_GPIO (7)
-
-static void __init mx31lilly_init_fb(void)
-{
- if (gpio_request(LCD_VCC_EN_GPIO, "LCD enable") != 0) {
- printk(KERN_WARNING "unable to request LCD_VCC_EN pin.\n");
- return;
- }
-
- mxc_register_device(&mx3_ipu, &ipu_data);
- mxc_register_device(&mx3_fb, &fb_pdata);
- gpio_direction_output(LCD_VCC_EN_GPIO, 1);
-}
-
-void __init mx31lilly_db_init(void)
-{
- mxc_iomux_setup_multiple_pins(lilly_db_board_pins,
- ARRAY_SIZE(lilly_db_board_pins),
- "development board pins");
- imx31_add_imx_uart0(&uart_pdata);
- imx31_add_imx_uart1(&uart_pdata);
- imx31_add_imx_uart2(&uart_pdata);
- imx31_add_mxc_mmc(0, &mmc_pdata);
- mx31lilly_init_fb();
-}
-
diff --git a/arch/arm/mach-mx3/mx31lite-db.c b/arch/arm/mach-mx3/mx31lite-db.c
deleted file mode 100644
index 3124ea8..0000000
--- a/arch/arm/mach-mx3/mx31lite-db.c
+++ /dev/null
@@ -1,204 +0,0 @@
-/*
- * LogicPD i.MX31 SOM-LV development board support
- *
- * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
- *
- * based on code for other MX31 boards,
- *
- * Copyright 2005-2007 Freescale Semiconductor
- * Copyright (c) 2009 Alberto Panizzo <maramaopercheseimorto@gmail.com>
- * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/init.h>
-#include <linux/gpio.h>
-#include <linux/leds.h>
-#include <linux/platform_device.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-
-#include <mach/hardware.h>
-#include <mach/common.h>
-#include <mach/iomux-mx3.h>
-#include <mach/board-mx31lite.h>
-
-#include "devices-imx31.h"
-#include "devices.h"
-
-/*
- * This file contains board-specific initialization routines for the
- * LogicPD i.MX31 SOM-LV development board, aka 'LiteKit'.
- * If you design an own baseboard for the module, use this file as base
- * for support code.
- */
-
-static unsigned int litekit_db_board_pins[] __initdata = {
- /* UART1 */
- MX31_PIN_CTS1__CTS1,
- MX31_PIN_RTS1__RTS1,
- MX31_PIN_TXD1__TXD1,
- MX31_PIN_RXD1__RXD1,
- /* SPI 0 */
- MX31_PIN_CSPI1_SCLK__SCLK,
- MX31_PIN_CSPI1_MOSI__MOSI,
- MX31_PIN_CSPI1_MISO__MISO,
- MX31_PIN_CSPI1_SPI_RDY__SPI_RDY,
- MX31_PIN_CSPI1_SS0__SS0,
- MX31_PIN_CSPI1_SS1__SS1,
- MX31_PIN_CSPI1_SS2__SS2,
- /* SDHC1 */
- MX31_PIN_SD1_DATA0__SD1_DATA0,
- MX31_PIN_SD1_DATA1__SD1_DATA1,
- MX31_PIN_SD1_DATA2__SD1_DATA2,
- MX31_PIN_SD1_DATA3__SD1_DATA3,
- MX31_PIN_SD1_CLK__SD1_CLK,
- MX31_PIN_SD1_CMD__SD1_CMD,
-};
-
-/* UART */
-static const struct imxuart_platform_data uart_pdata __initconst = {
- .flags = IMXUART_HAVE_RTSCTS,
-};
-
-/* MMC */
-
-static int gpio_det, gpio_wp;
-
-#define MMC_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
- PAD_CTL_ODE_CMOS)
-
-static int mxc_mmc1_get_ro(struct device *dev)
-{
- return gpio_get_value(IOMUX_TO_GPIO(MX31_PIN_GPIO1_6));
-}
-
-static int mxc_mmc1_init(struct device *dev,
- irq_handler_t detect_irq, void *data)
-{
- int ret;
-
- gpio_det = IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1);
- gpio_wp = IOMUX_TO_GPIO(MX31_PIN_GPIO1_6);
-
- mxc_iomux_set_pad(MX31_PIN_SD1_DATA0,
- MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
- mxc_iomux_set_pad(MX31_PIN_SD1_DATA1,
- MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
- mxc_iomux_set_pad(MX31_PIN_SD1_DATA2,
- MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
- mxc_iomux_set_pad(MX31_PIN_SD1_DATA3,
- MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
- mxc_iomux_set_pad(MX31_PIN_SD1_CMD,
- MMC_PAD_CFG | PAD_CTL_PUE_PUD | PAD_CTL_100K_PU);
- mxc_iomux_set_pad(MX31_PIN_SD1_CLK, MMC_PAD_CFG);
-
- ret = gpio_request(gpio_det, "MMC detect");
- if (ret)
- return ret;
-
- ret = gpio_request(gpio_wp, "MMC w/p");
- if (ret)
- goto exit_free_det;
-
- gpio_direction_input(gpio_det);
- gpio_direction_input(gpio_wp);
-
- ret = request_irq(IOMUX_TO_IRQ(MX31_PIN_DCD_DCE1), detect_irq,
- IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
- "MMC detect", data);
- if (ret)
- goto exit_free_wp;
-
- return 0;
-
-exit_free_wp:
- gpio_free(gpio_wp);
-
-exit_free_det:
- gpio_free(gpio_det);
-
- return ret;
-}
-
-static void mxc_mmc1_exit(struct device *dev, void *data)
-{
- gpio_free(gpio_det);
- gpio_free(gpio_wp);
- free_irq(IOMUX_TO_IRQ(MX31_PIN_DCD_DCE1), data);
-}
-
-static const struct imxmmc_platform_data mmc_pdata __initconst = {
- .get_ro = mxc_mmc1_get_ro,
- .init = mxc_mmc1_init,
- .exit = mxc_mmc1_exit,
-};
-
-/* SPI */
-
-static int spi_internal_chipselect[] = {
- MXC_SPI_CS(0),
- MXC_SPI_CS(1),
- MXC_SPI_CS(2),
-};
-
-static const struct spi_imx_master spi0_pdata __initconst = {
- .chipselect = spi_internal_chipselect,
- .num_chipselect = ARRAY_SIZE(spi_internal_chipselect),
-};
-
-/* GPIO LEDs */
-
-static struct gpio_led litekit_leds[] = {
- {
- .name = "GPIO0",
- .gpio = IOMUX_TO_GPIO(MX31_PIN_COMPARE),
- .active_low = 1,
- .default_state = LEDS_GPIO_DEFSTATE_OFF,
- },
- {
- .name = "GPIO1",
- .gpio = IOMUX_TO_GPIO(MX31_PIN_CAPTURE),
- .active_low = 1,
- .default_state = LEDS_GPIO_DEFSTATE_OFF,
- }
-};
-
-static struct gpio_led_platform_data litekit_led_platform_data = {
- .leds = litekit_leds,
- .num_leds = ARRAY_SIZE(litekit_leds),
-};
-
-static struct platform_device litekit_led_device = {
- .name = "leds-gpio",
- .id = -1,
- .dev = {
- .platform_data = &litekit_led_platform_data,
- },
-};
-
-void __init mx31lite_db_init(void)
-{
- mxc_iomux_setup_multiple_pins(litekit_db_board_pins,
- ARRAY_SIZE(litekit_db_board_pins),
- "development board pins");
- imx31_add_imx_uart0(&uart_pdata);
- imx31_add_mxc_mmc(0, &mmc_pdata);
- imx31_add_spi_imx0(&spi0_pdata);
- platform_device_register(&litekit_led_device);
- imx31_add_imx2_wdt(NULL);
- mxc_register_device(&imx_rtc_device0, NULL);
-}
diff --git a/arch/arm/mach-mx3/mx31moboard-devboard.c b/arch/arm/mach-mx3/mx31moboard-devboard.c
deleted file mode 100644
index 6410b9c..0000000
--- a/arch/arm/mach-mx3/mx31moboard-devboard.c
+++ /dev/null
@@ -1,243 +0,0 @@
-/*
- * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/delay.h>
-#include <linux/platform_device.h>
-#include <linux/slab.h>
-#include <linux/types.h>
-
-#include <linux/usb/otg.h>
-
-#include <mach/common.h>
-#include <mach/iomux-mx3.h>
-#include <mach/hardware.h>
-#include <mach/ulpi.h>
-
-#include "devices-imx31.h"
-#include "devices.h"
-
-static unsigned int devboard_pins[] = {
- /* UART1 */
- MX31_PIN_CTS2__CTS2, MX31_PIN_RTS2__RTS2,
- MX31_PIN_TXD2__TXD2, MX31_PIN_RXD2__RXD2,
- /* SDHC2 */
- MX31_PIN_PC_PWRON__SD2_DATA3, MX31_PIN_PC_VS1__SD2_DATA2,
- MX31_PIN_PC_READY__SD2_DATA1, MX31_PIN_PC_WAIT_B__SD2_DATA0,
- MX31_PIN_PC_CD2_B__SD2_CLK, MX31_PIN_PC_CD1_B__SD2_CMD,
- MX31_PIN_ATA_DIOR__GPIO3_28, MX31_PIN_ATA_DIOW__GPIO3_29,
- /* USB H1 */
- MX31_PIN_CSPI1_MISO__USBH1_RXDP, MX31_PIN_CSPI1_MOSI__USBH1_RXDM,
- MX31_PIN_CSPI1_SS0__USBH1_TXDM, MX31_PIN_CSPI1_SS1__USBH1_TXDP,
- MX31_PIN_CSPI1_SS2__USBH1_RCV, MX31_PIN_CSPI1_SCLK__USBH1_OEB,
- MX31_PIN_CSPI1_SPI_RDY__USBH1_FS, MX31_PIN_SFS6__USBH1_SUSPEND,
- MX31_PIN_NFRE_B__GPIO1_11, MX31_PIN_NFALE__GPIO1_12,
- /* SEL */
- MX31_PIN_DTR_DCE1__GPIO2_8, MX31_PIN_DSR_DCE1__GPIO2_9,
- MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11,
-};
-
-static const struct imxuart_platform_data uart_pdata __initconst = {
- .flags = IMXUART_HAVE_RTSCTS,
-};
-
-#define SDHC2_CD IOMUX_TO_GPIO(MX31_PIN_ATA_DIOR)
-#define SDHC2_WP IOMUX_TO_GPIO(MX31_PIN_ATA_DIOW)
-
-static int devboard_sdhc2_get_ro(struct device *dev)
-{
- return !gpio_get_value(SDHC2_WP);
-}
-
-static int devboard_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
- void *data)
-{
- int ret;
-
- ret = gpio_request(SDHC2_CD, "sdhc-detect");
- if (ret)
- return ret;
-
- gpio_direction_input(SDHC2_CD);
-
- ret = gpio_request(SDHC2_WP, "sdhc-wp");
- if (ret)
- goto err_gpio_free;
- gpio_direction_input(SDHC2_WP);
-
- ret = request_irq(gpio_to_irq(SDHC2_CD), detect_irq,
- IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
- "sdhc2-card-detect", data);
- if (ret)
- goto err_gpio_free_2;
-
- return 0;
-
-err_gpio_free_2:
- gpio_free(SDHC2_WP);
-err_gpio_free:
- gpio_free(SDHC2_CD);
-
- return ret;
-}
-
-static void devboard_sdhc2_exit(struct device *dev, void *data)
-{
- free_irq(gpio_to_irq(SDHC2_CD), data);
- gpio_free(SDHC2_WP);
- gpio_free(SDHC2_CD);
-}
-
-static const struct imxmmc_platform_data sdhc2_pdata __initconst = {
- .get_ro = devboard_sdhc2_get_ro,
- .init = devboard_sdhc2_init,
- .exit = devboard_sdhc2_exit,
-};
-
-#define SEL0 IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1)
-#define SEL1 IOMUX_TO_GPIO(MX31_PIN_DSR_DCE1)
-#define SEL2 IOMUX_TO_GPIO(MX31_PIN_RI_DCE1)
-#define SEL3 IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1)
-
-static void devboard_init_sel_gpios(void)
-{
- if (!gpio_request(SEL0, "sel0")) {
- gpio_direction_input(SEL0);
- gpio_export(SEL0, true);
- }
-
- if (!gpio_request(SEL1, "sel1")) {
- gpio_direction_input(SEL1);
- gpio_export(SEL1, true);
- }
-
- if (!gpio_request(SEL2, "sel2")) {
- gpio_direction_input(SEL2);
- gpio_export(SEL2, true);
- }
-
- if (!gpio_request(SEL3, "sel3")) {
- gpio_direction_input(SEL3);
- gpio_export(SEL3, true);
- }
-}
-#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
- PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
-
-static int devboard_usbh1_hw_init(struct platform_device *pdev)
-{
- mxc_iomux_set_gpr(MUX_PGP_USB_SUSPEND, true);
-
- mxc_iomux_set_pad(MX31_PIN_CSPI1_MISO, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_CSPI1_MOSI, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_CSPI1_SS0, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_CSPI1_SS1, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_CSPI1_SS2, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_CSPI1_SCLK, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_SFS6, USB_PAD_CFG);
-
- mdelay(10);
-
- return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED |
- MXC_EHCI_INTERFACE_SINGLE_UNI);
-}
-
-#define USBH1_VBUSEN_B IOMUX_TO_GPIO(MX31_PIN_NFRE_B)
-#define USBH1_MODE IOMUX_TO_GPIO(MX31_PIN_NFALE)
-
-static int devboard_isp1105_init(struct otg_transceiver *otg)
-{
- int ret = gpio_request(USBH1_MODE, "usbh1-mode");
- if (ret)
- return ret;
- /* single ended */
- gpio_direction_output(USBH1_MODE, 0);
-
- ret = gpio_request(USBH1_VBUSEN_B, "usbh1-vbusen");
- if (ret) {
- gpio_free(USBH1_MODE);
- return ret;
- }
- gpio_direction_output(USBH1_VBUSEN_B, 1);
-
- return 0;
-}
-
-
-static int devboard_isp1105_set_vbus(struct otg_transceiver *otg, bool on)
-{
- if (on)
- gpio_set_value(USBH1_VBUSEN_B, 0);
- else
- gpio_set_value(USBH1_VBUSEN_B, 1);
-
- return 0;
-}
-
-static struct mxc_usbh_platform_data usbh1_pdata __initdata = {
- .init = devboard_usbh1_hw_init,
- .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL,
-};
-
-static int __init devboard_usbh1_init(void)
-{
- struct otg_transceiver *otg;
- struct platform_device *pdev;
-
- otg = kzalloc(sizeof(*otg), GFP_KERNEL);
- if (!otg)
- return -ENOMEM;
-
- otg->label = "ISP1105";
- otg->init = devboard_isp1105_init;
- otg->set_vbus = devboard_isp1105_set_vbus;
-
- usbh1_pdata.otg = otg;
-
- pdev = imx31_add_mxc_ehci_hs(1, &usbh1_pdata);
- if (IS_ERR(pdev))
- return PTR_ERR(pdev);
-
- return 0;
-}
-
-
-static const struct fsl_usb2_platform_data usb_pdata __initconst = {
- .operating_mode = FSL_USB2_DR_DEVICE,
- .phy_mode = FSL_USB2_PHY_ULPI,
-};
-
-/*
- * system init for baseboard usage. Will be called by mx31moboard init.
- */
-void __init mx31moboard_devboard_init(void)
-{
- printk(KERN_INFO "Initializing mx31devboard peripherals\n");
-
- mxc_iomux_setup_multiple_pins(devboard_pins, ARRAY_SIZE(devboard_pins),
- "devboard");
-
- imx31_add_imx_uart1(&uart_pdata);
-
- imx31_add_mxc_mmc(1, &sdhc2_pdata);
-
- devboard_init_sel_gpios();
-
- imx31_add_fsl_usb2_udc(&usb_pdata);
-
- devboard_usbh1_init();
-}
diff --git a/arch/arm/mach-mx3/mx31moboard-marxbot.c b/arch/arm/mach-mx3/mx31moboard-marxbot.c
deleted file mode 100644
index 57f7b00..0000000
--- a/arch/arm/mach-mx3/mx31moboard-marxbot.c
+++ /dev/null
@@ -1,368 +0,0 @@
-/*
- * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/delay.h>
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/i2c.h>
-#include <linux/spi/spi.h>
-#include <linux/slab.h>
-#include <linux/platform_device.h>
-#include <linux/types.h>
-
-#include <linux/usb/otg.h>
-
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <mach/imx-uart.h>
-#include <mach/iomux-mx3.h>
-#include <mach/ulpi.h>
-
-#include <media/soc_camera.h>
-
-#include "devices-imx31.h"
-#include "devices.h"
-
-static unsigned int marxbot_pins[] = {
- /* SDHC2 */
- MX31_PIN_PC_PWRON__SD2_DATA3, MX31_PIN_PC_VS1__SD2_DATA2,
- MX31_PIN_PC_READY__SD2_DATA1, MX31_PIN_PC_WAIT_B__SD2_DATA0,
- MX31_PIN_PC_CD2_B__SD2_CLK, MX31_PIN_PC_CD1_B__SD2_CMD,
- MX31_PIN_ATA_DIOR__GPIO3_28, MX31_PIN_ATA_DIOW__GPIO3_29,
- /* CSI */
- MX31_PIN_CSI_D6__CSI_D6, MX31_PIN_CSI_D7__CSI_D7,
- MX31_PIN_CSI_D8__CSI_D8, MX31_PIN_CSI_D9__CSI_D9,
- MX31_PIN_CSI_D10__CSI_D10, MX31_PIN_CSI_D11__CSI_D11,
- MX31_PIN_CSI_D12__CSI_D12, MX31_PIN_CSI_D13__CSI_D13,
- MX31_PIN_CSI_D14__CSI_D14, MX31_PIN_CSI_D15__CSI_D15,
- MX31_PIN_CSI_HSYNC__CSI_HSYNC, MX31_PIN_CSI_MCLK__CSI_MCLK,
- MX31_PIN_CSI_PIXCLK__CSI_PIXCLK, MX31_PIN_CSI_VSYNC__CSI_VSYNC,
- MX31_PIN_CSI_D4__GPIO3_4, MX31_PIN_CSI_D5__GPIO3_5,
- MX31_PIN_GPIO3_0__GPIO3_0, MX31_PIN_GPIO3_1__GPIO3_1,
- MX31_PIN_TXD2__GPIO1_28,
- /* dsPIC resets */
- MX31_PIN_STXD5__GPIO1_21, MX31_PIN_SRXD5__GPIO1_22,
- /*battery detection */
- MX31_PIN_LCS0__GPIO3_23,
- /* USB H1 */
- MX31_PIN_CSPI1_MISO__USBH1_RXDP, MX31_PIN_CSPI1_MOSI__USBH1_RXDM,
- MX31_PIN_CSPI1_SS0__USBH1_TXDM, MX31_PIN_CSPI1_SS1__USBH1_TXDP,
- MX31_PIN_CSPI1_SS2__USBH1_RCV, MX31_PIN_CSPI1_SCLK__USBH1_OEB,
- MX31_PIN_CSPI1_SPI_RDY__USBH1_FS, MX31_PIN_SFS6__USBH1_SUSPEND,
- MX31_PIN_NFRE_B__GPIO1_11, MX31_PIN_NFALE__GPIO1_12,
- /* SEL */
- MX31_PIN_DTR_DCE1__GPIO2_8, MX31_PIN_DSR_DCE1__GPIO2_9,
- MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11,
-};
-
-#define SDHC2_CD IOMUX_TO_GPIO(MX31_PIN_ATA_DIOR)
-#define SDHC2_WP IOMUX_TO_GPIO(MX31_PIN_ATA_DIOW)
-
-static int marxbot_sdhc2_get_ro(struct device *dev)
-{
- return !gpio_get_value(SDHC2_WP);
-}
-
-static int marxbot_sdhc2_init(struct device *dev, irq_handler_t detect_irq,
- void *data)
-{
- int ret;
-
- ret = gpio_request(SDHC2_CD, "sdhc-detect");
- if (ret)
- return ret;
-
- gpio_direction_input(SDHC2_CD);
-
- ret = gpio_request(SDHC2_WP, "sdhc-wp");
- if (ret)
- goto err_gpio_free;
- gpio_direction_input(SDHC2_WP);
-
- ret = request_irq(gpio_to_irq(SDHC2_CD), detect_irq,
- IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
- "sdhc2-card-detect", data);
- if (ret)
- goto err_gpio_free_2;
-
- return 0;
-
-err_gpio_free_2:
- gpio_free(SDHC2_WP);
-err_gpio_free:
- gpio_free(SDHC2_CD);
-
- return ret;
-}
-
-static void marxbot_sdhc2_exit(struct device *dev, void *data)
-{
- free_irq(gpio_to_irq(SDHC2_CD), data);
- gpio_free(SDHC2_WP);
- gpio_free(SDHC2_CD);
-}
-
-static const struct imxmmc_platform_data sdhc2_pdata __initconst = {
- .get_ro = marxbot_sdhc2_get_ro,
- .init = marxbot_sdhc2_init,
- .exit = marxbot_sdhc2_exit,
-};
-
-#define TRSLAT_RST_B IOMUX_TO_GPIO(MX31_PIN_STXD5)
-#define DSPICS_RST_B IOMUX_TO_GPIO(MX31_PIN_SRXD5)
-
-static void dspics_resets_init(void)
-{
- if (!gpio_request(TRSLAT_RST_B, "translator-rst")) {
- gpio_direction_output(TRSLAT_RST_B, 0);
- gpio_export(TRSLAT_RST_B, false);
- }
-
- if (!gpio_request(DSPICS_RST_B, "dspics-rst")) {
- gpio_direction_output(DSPICS_RST_B, 0);
- gpio_export(DSPICS_RST_B, false);
- }
-}
-
-static struct spi_board_info marxbot_spi_board_info[] __initdata = {
- {
- .modalias = "spidev",
- .max_speed_hz = 300000,
- .bus_num = 1,
- .chip_select = 1, /* according spi1_cs[] ! */
- },
-};
-
-#define TURRETCAM_POWER IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)
-#define BASECAM_POWER IOMUX_TO_GPIO(MX31_PIN_CSI_D5)
-#define TURRETCAM_RST_B IOMUX_TO_GPIO(MX31_PIN_GPIO3_0)
-#define BASECAM_RST_B IOMUX_TO_GPIO(MX31_PIN_CSI_D4)
-#define CAM_CHOICE IOMUX_TO_GPIO(MX31_PIN_TXD2)
-
-static int marxbot_basecam_power(struct device *dev, int on)
-{
- gpio_set_value(BASECAM_POWER, !on);
- return 0;
-}
-
-static int marxbot_basecam_reset(struct device *dev)
-{
- gpio_set_value(BASECAM_RST_B, 0);
- udelay(100);
- gpio_set_value(BASECAM_RST_B, 1);
- return 0;
-}
-
-static struct i2c_board_info marxbot_i2c_devices[] = {
- {
- I2C_BOARD_INFO("mt9t031", 0x5d),
- },
-};
-
-static struct soc_camera_link base_iclink = {
- .bus_id = 0, /* Must match with the camera ID */
- .power = marxbot_basecam_power,
- .reset = marxbot_basecam_reset,
- .board_info = &marxbot_i2c_devices[0],
- .i2c_adapter_id = 0,
-};
-
-static struct platform_device marxbot_camera[] = {
- {
- .name = "soc-camera-pdrv",
- .id = 0,
- .dev = {
- .platform_data = &base_iclink,
- },
- },
-};
-
-static struct platform_device *marxbot_cameras[] __initdata = {
- &marxbot_camera[0],
-};
-
-static int __init marxbot_cam_init(void)
-{
- int ret = gpio_request(CAM_CHOICE, "cam-choice");
- if (ret)
- return ret;
- gpio_direction_output(CAM_CHOICE, 0);
-
- ret = gpio_request(BASECAM_RST_B, "basecam-reset");
- if (ret)
- return ret;
- gpio_direction_output(BASECAM_RST_B, 1);
- ret = gpio_request(BASECAM_POWER, "basecam-standby");
- if (ret)
- return ret;
- gpio_direction_output(BASECAM_POWER, 0);
-
- ret = gpio_request(TURRETCAM_RST_B, "turretcam-reset");
- if (ret)
- return ret;
- gpio_direction_output(TURRETCAM_RST_B, 1);
- ret = gpio_request(TURRETCAM_POWER, "turretcam-standby");
- if (ret)
- return ret;
- gpio_direction_output(TURRETCAM_POWER, 0);
-
- return 0;
-}
-
-#define SEL0 IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1)
-#define SEL1 IOMUX_TO_GPIO(MX31_PIN_DSR_DCE1)
-#define SEL2 IOMUX_TO_GPIO(MX31_PIN_RI_DCE1)
-#define SEL3 IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1)
-
-static void marxbot_init_sel_gpios(void)
-{
- if (!gpio_request(SEL0, "sel0")) {
- gpio_direction_input(SEL0);
- gpio_export(SEL0, true);
- }
-
- if (!gpio_request(SEL1, "sel1")) {
- gpio_direction_input(SEL1);
- gpio_export(SEL1, true);
- }
-
- if (!gpio_request(SEL2, "sel2")) {
- gpio_direction_input(SEL2);
- gpio_export(SEL2, true);
- }
-
- if (!gpio_request(SEL3, "sel3")) {
- gpio_direction_input(SEL3);
- gpio_export(SEL3, true);
- }
-}
-
-#define USB_PAD_CFG (PAD_CTL_DRV_MAX | PAD_CTL_SRE_FAST | PAD_CTL_HYS_CMOS | \
- PAD_CTL_ODE_CMOS | PAD_CTL_100K_PU)
-
-static int marxbot_usbh1_hw_init(struct platform_device *pdev)
-{
- mxc_iomux_set_gpr(MUX_PGP_USB_SUSPEND, true);
-
- mxc_iomux_set_pad(MX31_PIN_CSPI1_MISO, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_CSPI1_MOSI, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_CSPI1_SS0, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_CSPI1_SS1, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_CSPI1_SS2, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_CSPI1_SCLK, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_CSPI1_SPI_RDY, USB_PAD_CFG);
- mxc_iomux_set_pad(MX31_PIN_SFS6, USB_PAD_CFG);
-
- mdelay(10);
-
- return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED |
- MXC_EHCI_INTERFACE_SINGLE_UNI);
-}
-
-#define USBH1_VBUSEN_B IOMUX_TO_GPIO(MX31_PIN_NFRE_B)
-#define USBH1_MODE IOMUX_TO_GPIO(MX31_PIN_NFALE)
-
-static int marxbot_isp1105_init(struct otg_transceiver *otg)
-{
- int ret = gpio_request(USBH1_MODE, "usbh1-mode");
- if (ret)
- return ret;
- /* single ended */
- gpio_direction_output(USBH1_MODE, 0);
-
- ret = gpio_request(USBH1_VBUSEN_B, "usbh1-vbusen");
- if (ret) {
- gpio_free(USBH1_MODE);
- return ret;
- }
- gpio_direction_output(USBH1_VBUSEN_B, 1);
-
- return 0;
-}
-
-
-static int marxbot_isp1105_set_vbus(struct otg_transceiver *otg, bool on)
-{
- if (on)
- gpio_set_value(USBH1_VBUSEN_B, 0);
- else
- gpio_set_value(USBH1_VBUSEN_B, 1);
-
- return 0;
-}
-
-static struct mxc_usbh_platform_data usbh1_pdata __initdata = {
- .init = marxbot_usbh1_hw_init,
- .portsc = MXC_EHCI_MODE_UTMI | MXC_EHCI_SERIAL,
-};
-
-static int __init marxbot_usbh1_init(void)
-{
- struct otg_transceiver *otg;
- struct platform_device *pdev;
-
- otg = kzalloc(sizeof(*otg), GFP_KERNEL);
- if (!otg)
- return -ENOMEM;
-
- otg->label = "ISP1105";
- otg->init = marxbot_isp1105_init;
- otg->set_vbus = marxbot_isp1105_set_vbus;
-
- usbh1_pdata.otg = otg;
-
- pdev = imx31_add_mxc_ehci_hs(1, &usbh1_pdata);
- if (IS_ERR(pdev))
- return PTR_ERR(pdev);
-
- return 0;
-}
-
-static const struct fsl_usb2_platform_data usb_pdata __initconst = {
- .operating_mode = FSL_USB2_DR_DEVICE,
- .phy_mode = FSL_USB2_PHY_ULPI,
-};
-
-/*
- * system init for baseboard usage. Will be called by mx31moboard init.
- */
-void __init mx31moboard_marxbot_init(void)
-{
- printk(KERN_INFO "Initializing mx31marxbot peripherals\n");
-
- mxc_iomux_setup_multiple_pins(marxbot_pins, ARRAY_SIZE(marxbot_pins),
- "marxbot");
-
- marxbot_init_sel_gpios();
-
- dspics_resets_init();
-
- imx31_add_mxc_mmc(1, &sdhc2_pdata);
-
- spi_register_board_info(marxbot_spi_board_info,
- ARRAY_SIZE(marxbot_spi_board_info));
-
- marxbot_cam_init();
- platform_add_devices(marxbot_cameras, ARRAY_SIZE(marxbot_cameras));
-
- /* battery present pin */
- gpio_request(IOMUX_TO_GPIO(MX31_PIN_LCS0), "bat-present");
- gpio_direction_input(IOMUX_TO_GPIO(MX31_PIN_LCS0));
- gpio_export(IOMUX_TO_GPIO(MX31_PIN_LCS0), false);
-
- imx31_add_fsl_usb2_udc(&usb_pdata);
-
- marxbot_usbh1_init();
-}
diff --git a/arch/arm/mach-mx3/mx31moboard-smartbot.c b/arch/arm/mach-mx3/mx31moboard-smartbot.c
deleted file mode 100644
index 35f806e..0000000
--- a/arch/arm/mach-mx3/mx31moboard-smartbot.c
+++ /dev/null
@@ -1,210 +0,0 @@
-/*
- * Copyright (C) 2009 Valentin Longchamp, EPFL Mobots group
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/delay.h>
-#include <linux/gpio.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/i2c.h>
-#include <linux/platform_device.h>
-#include <linux/types.h>
-
-#include <linux/usb/otg.h>
-#include <linux/usb/ulpi.h>
-
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <mach/iomux-mx3.h>
-#include <mach/board-mx31moboard.h>
-#include <mach/ulpi.h>
-
-#include <media/soc_camera.h>
-
-#include "devices-imx31.h"
-#include "devices.h"
-
-static unsigned int smartbot_pins[] = {
- /* UART1 */
- MX31_PIN_CTS2__CTS2, MX31_PIN_RTS2__RTS2,
- MX31_PIN_TXD2__TXD2, MX31_PIN_RXD2__RXD2,
- /* CSI */
- MX31_PIN_CSI_D4__CSI_D4, MX31_PIN_CSI_D5__CSI_D5,
- MX31_PIN_CSI_D6__CSI_D6, MX31_PIN_CSI_D7__CSI_D7,
- MX31_PIN_CSI_D8__CSI_D8, MX31_PIN_CSI_D9__CSI_D9,
- MX31_PIN_CSI_D10__CSI_D10, MX31_PIN_CSI_D11__CSI_D11,
- MX31_PIN_CSI_D12__CSI_D12, MX31_PIN_CSI_D13__CSI_D13,
- MX31_PIN_CSI_D14__CSI_D14, MX31_PIN_CSI_D15__CSI_D15,
- MX31_PIN_CSI_HSYNC__CSI_HSYNC, MX31_PIN_CSI_MCLK__CSI_MCLK,
- MX31_PIN_CSI_PIXCLK__CSI_PIXCLK, MX31_PIN_CSI_VSYNC__CSI_VSYNC,
- MX31_PIN_GPIO3_0__GPIO3_0, MX31_PIN_GPIO3_1__GPIO3_1,
- /* ENABLES */
- MX31_PIN_DTR_DCE1__GPIO2_8, MX31_PIN_DSR_DCE1__GPIO2_9,
- MX31_PIN_RI_DCE1__GPIO2_10, MX31_PIN_DCD_DCE1__GPIO2_11,
-};
-
-static const struct imxuart_platform_data uart_pdata __initconst = {
- .flags = IMXUART_HAVE_RTSCTS,
-};
-
-#define CAM_POWER IOMUX_TO_GPIO(MX31_PIN_GPIO3_1)
-#define CAM_RST_B IOMUX_TO_GPIO(MX31_PIN_GPIO3_0)
-
-static int smartbot_cam_power(struct device *dev, int on)
-{
- gpio_set_value(CAM_POWER, !on);
- return 0;
-}
-
-static int smartbot_cam_reset(struct device *dev)
-{
- gpio_set_value(CAM_RST_B, 0);
- udelay(100);
- gpio_set_value(CAM_RST_B, 1);
- return 0;
-}
-
-static struct i2c_board_info smartbot_i2c_devices[] = {
- {
- I2C_BOARD_INFO("mt9t031", 0x5d),
- },
-};
-
-static struct soc_camera_link base_iclink = {
- .bus_id = 0, /* Must match with the camera ID */
- .power = smartbot_cam_power,
- .reset = smartbot_cam_reset,
- .board_info = &smartbot_i2c_devices[0],
- .i2c_adapter_id = 0,
-};
-
-static struct platform_device smartbot_camera[] = {
- {
- .name = "soc-camera-pdrv",
- .id = 0,
- .dev = {
- .platform_data = &base_iclink,
- },
- },
-};
-
-static struct platform_device *smartbot_cameras[] __initdata = {
- &smartbot_camera[0],
-};
-
-static int __init smartbot_cam_init(void)
-{
- int ret = gpio_request(CAM_RST_B, "cam-reset");
- if (ret)
- return ret;
- gpio_direction_output(CAM_RST_B, 1);
- ret = gpio_request(CAM_POWER, "cam-standby");
- if (ret)
- return ret;
- gpio_direction_output(CAM_POWER, 0);
-
- return 0;
-}
-
-static const struct fsl_usb2_platform_data usb_pdata __initconst = {
- .operating_mode = FSL_USB2_DR_DEVICE,
- .phy_mode = FSL_USB2_PHY_ULPI,
-};
-
-#if defined(CONFIG_USB_ULPI)
-
-static int smartbot_otg_init(struct platform_device *pdev)
-{
- return mx31_initialize_usb_hw(pdev->id, MXC_EHCI_POWER_PINS_ENABLED);
-}
-
-static struct mxc_usbh_platform_data otg_host_pdata __initdata = {
- .init = smartbot_otg_init,
- .portsc = MXC_EHCI_MODE_ULPI | MXC_EHCI_UTMI_8BIT,
-};
-
-static int __init smartbot_otg_host_init(void)
-{
- struct platform_device *pdev;
-
- otg_host_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
- ULPI_OTG_DRVVBUS_EXT);
- if (!otg_host_pdata.otg)
- return -ENODEV;
-
- pdev = imx31_add_mxc_ehci_otg(&otg_host_pdata);
- if (IS_ERR(pdev))
- return PTR_ERR(pdev);
-
- return 0;
-}
-#else
-static inline int smartbot_otg_host_init(void) { return 0; }
-#endif
-
-#define POWER_EN IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1)
-#define DSPIC_RST_B IOMUX_TO_GPIO(MX31_PIN_DSR_DCE1)
-#define TRSLAT_RST_B IOMUX_TO_GPIO(MX31_PIN_RI_DCE1)
-#define TRSLAT_SRC_CHOICE IOMUX_TO_GPIO(MX31_PIN_DCD_DCE1)
-
-static void smartbot_resets_init(void)
-{
- if (!gpio_request(POWER_EN, "power-enable")) {
- gpio_direction_output(POWER_EN, 0);
- gpio_export(POWER_EN, false);
- }
-
- if (!gpio_request(DSPIC_RST_B, "dspic-rst")) {
- gpio_direction_output(DSPIC_RST_B, 0);
- gpio_export(DSPIC_RST_B, false);
- }
-
- if (!gpio_request(TRSLAT_RST_B, "translator-rst")) {
- gpio_direction_output(TRSLAT_RST_B, 0);
- gpio_export(TRSLAT_RST_B, false);
- }
-
- if (!gpio_request(TRSLAT_SRC_CHOICE, "translator-src-choice")) {
- gpio_direction_output(TRSLAT_SRC_CHOICE, 0);
- gpio_export(TRSLAT_SRC_CHOICE, false);
- }
-}
-/*
- * system init for baseboard usage. Will be called by mx31moboard init.
- */
-void __init mx31moboard_smartbot_init(int board)
-{
- printk(KERN_INFO "Initializing mx31smartbot peripherals\n");
-
- mxc_iomux_setup_multiple_pins(smartbot_pins, ARRAY_SIZE(smartbot_pins),
- "smartbot");
-
- imx31_add_imx_uart1(&uart_pdata);
-
- switch (board) {
- case MX31SMARTBOT:
- imx31_add_fsl_usb2_udc(&usb_pdata);
- break;
- case MX31EYEBOT:
- smartbot_otg_host_init();
- break;
- default:
- printk(KERN_WARNING "Unknown board %d, USB OTG not initialized",
- board);
- }
-
- smartbot_resets_init();
-
- smartbot_cam_init();
- platform_add_devices(smartbot_cameras, ARRAY_SIZE(smartbot_cameras));
-}
diff --git a/arch/arm/mach-mx5/Kconfig b/arch/arm/mach-mx5/Kconfig
index 159340d..799fbc4 100644
--- a/arch/arm/mach-mx5/Kconfig
+++ b/arch/arm/mach-mx5/Kconfig
@@ -1,11 +1,11 @@
-if ARCH_MX5
-# ARCH_MX50/51/53 are left to mark places where prevent multi-soc in single
+if ARCH_MX503 || ARCH_MX51
+# ARCH_MX5/50/53 are left to mark places where prevent multi-soc in single
# image. So for most time, SOC_IMX50/51/53 should be used.
-config ARCH_MX50
+config ARCH_MX5
bool
-config ARCH_MX51
+config ARCH_MX50
bool
config ARCH_MX53
@@ -13,27 +13,54 @@
config SOC_IMX50
bool
+ select CPU_V7
+ select ARM_L1_CACHE_SHIFT_6
select MXC_TZIC
select ARCH_MXC_IOMUX_V3
select ARCH_MXC_AUDMUX_V2
select ARCH_HAS_CPUFREQ
+ select ARCH_MX5
select ARCH_MX50
config SOC_IMX51
bool
+ select CPU_V7
+ select ARM_L1_CACHE_SHIFT_6
select MXC_TZIC
select ARCH_MXC_IOMUX_V3
select ARCH_MXC_AUDMUX_V2
select ARCH_HAS_CPUFREQ
- select ARCH_MX51
+ select ARCH_MX5
config SOC_IMX53
bool
+ select CPU_V7
+ select ARM_L1_CACHE_SHIFT_6
select MXC_TZIC
select ARCH_MXC_IOMUX_V3
+ select ARCH_MX5
select ARCH_MX53
-comment "MX5 platforms:"
+if ARCH_MX50_SUPPORTED
+#comment "i.MX50 machines:"
+
+config MACH_MX50_RDP
+ bool "Support MX50 reference design platform"
+ depends on BROKEN
+ select SOC_IMX50
+ select IMX_HAVE_PLATFORM_IMX_I2C
+ select IMX_HAVE_PLATFORM_IMX_UART
+ select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
+ select IMX_HAVE_PLATFORM_SPI_IMX
+ select IMX_HAVE_PLATFORM_FEC
+ help
+ Include support for MX50 reference design platform (RDP) board. This
+ includes specific configurations for the board and its peripherals.
+
+endif # ARCH_MX50_SUPPORTED
+
+if ARCH_MX51
+comment "i.MX51 machines:"
config MACH_MX51_BABBAGE
bool "Support MX51 BABBAGE platforms"
@@ -136,6 +163,11 @@
Include support for Genesi Efika Smartbook. This includes specific
configurations for the board and its peripherals.
+endif # ARCH_MX51
+
+if ARCH_MX53_SUPPORTED
+comment "i.MX53 machines:"
+
config MACH_MX53_EVK
bool "Support MX53 EVK platforms"
select SOC_IMX53
@@ -154,6 +186,7 @@
select IMX_HAVE_PLATFORM_IMX2_WDT
select IMX_HAVE_PLATFORM_IMX_I2C
select IMX_HAVE_PLATFORM_IMX_UART
+ select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
help
Include support for MX53 SMD platform. This includes specific
configurations for the board and its peripherals.
@@ -170,17 +203,6 @@
Include support for MX53 LOCO platform. This includes specific
configurations for the board and its peripherals.
-config MACH_MX50_RDP
- bool "Support MX50 reference design platform"
- depends on BROKEN
- select SOC_IMX50
- select IMX_HAVE_PLATFORM_IMX_I2C
- select IMX_HAVE_PLATFORM_IMX_UART
- select IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
- select IMX_HAVE_PLATFORM_SPI_IMX
- select IMX_HAVE_PLATFORM_FEC
- help
- Include support for MX50 reference design platform (RDP) board. This
- includes specific configurations for the board and its peripherals.
+endif # ARCH_MX53_SUPPORTED
endif
diff --git a/arch/arm/mach-mx5/board-cpuimx51.c b/arch/arm/mach-mx5/board-cpuimx51.c
index d0296a9..4efa02e 100644
--- a/arch/arm/mach-mx5/board-cpuimx51.c
+++ b/arch/arm/mach-mx5/board-cpuimx51.c
@@ -23,13 +23,11 @@
#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
-#include <linux/fsl_devices.h>
#include <mach/eukrea-baseboards.h>
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-mx51.h>
-#include <mach/mxc_ehci.h>
#include <asm/irq.h>
#include <asm/setup.h>
diff --git a/arch/arm/mach-mx5/board-cpuimx51sd.c b/arch/arm/mach-mx5/board-cpuimx51sd.c
index 29b1808..5ef25a5 100644
--- a/arch/arm/mach-mx5/board-cpuimx51sd.c
+++ b/arch/arm/mach-mx5/board-cpuimx51sd.c
@@ -23,7 +23,6 @@
#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
-#include <linux/fsl_devices.h>
#include <linux/i2c-gpio.h>
#include <linux/spi/spi.h>
#include <linux/can/platform/mcp251x.h>
@@ -32,7 +31,6 @@
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-mx51.h>
-#include <mach/mxc_ehci.h>
#include <asm/irq.h>
#include <asm/setup.h>
diff --git a/arch/arm/mach-mx5/board-mx50_rdp.c b/arch/arm/mach-mx5/board-mx50_rdp.c
index dedf7f2..11210e1 100644
--- a/arch/arm/mach-mx5/board-mx50_rdp.c
+++ b/arch/arm/mach-mx5/board-mx50_rdp.c
@@ -23,7 +23,6 @@
#include <linux/gpio.h>
#include <linux/delay.h>
#include <linux/io.h>
-#include <linux/fsl_devices.h>
#include <mach/common.h>
#include <mach/hardware.h>
diff --git a/arch/arm/mach-mx5/board-mx51_babbage.c b/arch/arm/mach-mx5/board-mx51_babbage.c
index bea4e41..c7b3fab 100644
--- a/arch/arm/mach-mx5/board-mx51_babbage.c
+++ b/arch/arm/mach-mx5/board-mx51_babbage.c
@@ -16,9 +16,6 @@
#include <linux/gpio.h>
#include <linux/delay.h>
#include <linux/io.h>
-#include <linux/fsl_devices.h>
-#include <linux/fec.h>
-#include <linux/gpio_keys.h>
#include <linux/input.h>
#include <linux/spi/flash.h>
#include <linux/spi/spi.h>
@@ -26,7 +23,6 @@
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-mx51.h>
-#include <mach/mxc_ehci.h>
#include <asm/irq.h>
#include <asm/setup.h>
@@ -208,18 +204,16 @@
{
int ret;
- /* Bring USB hub out of reset */
- ret = gpio_request(BABBAGE_USB_HUB_RESET, "GPIO1_7");
+ /* Reset USB hub */
+ ret = gpio_request_one(BABBAGE_USB_HUB_RESET,
+ GPIOF_OUT_INIT_LOW, "GPIO1_7");
if (ret) {
printk(KERN_ERR"failed to get GPIO_USB_HUB_RESET: %d\n", ret);
return;
}
- gpio_direction_output(BABBAGE_USB_HUB_RESET, 0);
- /* USB HUB RESET - De-assert USB HUB RESET_N */
- msleep(1);
- gpio_set_value(BABBAGE_USB_HUB_RESET, 0);
- msleep(1);
+ msleep(2);
+ /* Deassert reset */
gpio_set_value(BABBAGE_USB_HUB_RESET, 1);
}
@@ -361,7 +355,7 @@
/* Set the PAD settings for the pwr key. */
mxc_iomux_v3_setup_pad(power_key);
- imx51_add_gpio_keys(&imx_button_data);
+ imx_add_gpio_keys(&imx_button_data);
imx51_add_imx_i2c(0, &babbage_i2c_data);
imx51_add_imx_i2c(1, &babbage_i2c_data);
diff --git a/arch/arm/mach-mx5/board-mx51_efikamx.c b/arch/arm/mach-mx5/board-mx51_efikamx.c
index acab191..6e36231 100644
--- a/arch/arm/mach-mx5/board-mx51_efikamx.c
+++ b/arch/arm/mach-mx5/board-mx51_efikamx.c
@@ -22,7 +22,6 @@
#include <linux/input.h>
#include <linux/delay.h>
#include <linux/io.h>
-#include <linux/fsl_devices.h>
#include <linux/spi/flash.h>
#include <linux/spi/spi.h>
#include <linux/mfd/mc13892.h>
@@ -32,8 +31,6 @@
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-mx51.h>
-#include <mach/i2c.h>
-#include <mach/mxc_ehci.h>
#include <asm/irq.h>
#include <asm/setup.h>
@@ -252,7 +249,7 @@
}
platform_device_register(&mx51_efikamx_leds_device);
- imx51_add_gpio_keys(&mx51_efikamx_powerkey_data);
+ imx_add_gpio_keys(&mx51_efikamx_powerkey_data);
if (system_rev == 0x11) {
gpio_request(EFIKAMX_RESET1_1, "reset");
diff --git a/arch/arm/mach-mx5/board-mx51_efikasb.c b/arch/arm/mach-mx5/board-mx51_efikasb.c
index db04ce84..474fc6e 100644
--- a/arch/arm/mach-mx5/board-mx51_efikasb.c
+++ b/arch/arm/mach-mx5/board-mx51_efikasb.c
@@ -22,7 +22,6 @@
#include <linux/input.h>
#include <linux/delay.h>
#include <linux/io.h>
-#include <linux/fsl_devices.h>
#include <linux/spi/flash.h>
#include <linux/spi/spi.h>
#include <linux/mfd/mc13892.h>
@@ -35,8 +34,6 @@
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-mx51.h>
-#include <mach/i2c.h>
-#include <mach/mxc_ehci.h>
#include <asm/irq.h>
#include <asm/setup.h>
@@ -260,7 +257,7 @@
imx51_add_sdhci_esdhc_imx(1, NULL);
platform_device_register(&mx51_efikasb_leds_device);
- imx51_add_gpio_keys(&mx51_efikasb_keys_data);
+ imx_add_gpio_keys(&mx51_efikasb_keys_data);
}
diff --git a/arch/arm/mach-mx5/board-mx53_evk.c b/arch/arm/mach-mx5/board-mx53_evk.c
index 2af3f43..f87d571 100644
--- a/arch/arm/mach-mx5/board-mx53_evk.c
+++ b/arch/arm/mach-mx5/board-mx53_evk.c
@@ -21,7 +21,6 @@
#include <linux/init.h>
#include <linux/clk.h>
-#include <linux/fec.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/spi/flash.h>
@@ -31,7 +30,6 @@
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
-#include <mach/imx-uart.h>
#include <mach/iomux-mx53.h>
#define MX53_EVK_FEC_PHY_RST IMX_GPIO_NR(7, 6)
diff --git a/arch/arm/mach-mx5/board-mx53_loco.c b/arch/arm/mach-mx5/board-mx53_loco.c
index 6206b11..1b947e8 100644
--- a/arch/arm/mach-mx5/board-mx53_loco.c
+++ b/arch/arm/mach-mx5/board-mx53_loco.c
@@ -20,13 +20,11 @@
#include <linux/init.h>
#include <linux/clk.h>
-#include <linux/fec.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <mach/common.h>
#include <mach/hardware.h>
-#include <mach/imx-uart.h>
#include <mach/iomux-mx53.h>
#include <asm/mach-types.h>
diff --git a/arch/arm/mach-mx5/board-mx53_smd.c b/arch/arm/mach-mx5/board-mx53_smd.c
index 31e1732..817c089 100644
--- a/arch/arm/mach-mx5/board-mx53_smd.c
+++ b/arch/arm/mach-mx5/board-mx53_smd.c
@@ -20,13 +20,11 @@
#include <linux/init.h>
#include <linux/clk.h>
-#include <linux/fec.h>
#include <linux/delay.h>
#include <linux/gpio.h>
#include <mach/common.h>
#include <mach/hardware.h>
-#include <mach/imx-uart.h>
#include <mach/iomux-mx53.h>
#include <asm/mach-types.h>
@@ -52,6 +50,31 @@
/* I2C1 */
MX53_PAD_CSI0_DAT8__I2C1_SDA,
MX53_PAD_CSI0_DAT9__I2C1_SCL,
+ /* SD1 */
+ MX53_PAD_SD1_CMD__ESDHC1_CMD,
+ MX53_PAD_SD1_CLK__ESDHC1_CLK,
+ MX53_PAD_SD1_DATA0__ESDHC1_DAT0,
+ MX53_PAD_SD1_DATA1__ESDHC1_DAT1,
+ MX53_PAD_SD1_DATA2__ESDHC1_DAT2,
+ MX53_PAD_SD1_DATA3__ESDHC1_DAT3,
+ /* SD2 */
+ MX53_PAD_SD2_CMD__ESDHC2_CMD,
+ MX53_PAD_SD2_CLK__ESDHC2_CLK,
+ MX53_PAD_SD2_DATA0__ESDHC2_DAT0,
+ MX53_PAD_SD2_DATA1__ESDHC2_DAT1,
+ MX53_PAD_SD2_DATA2__ESDHC2_DAT2,
+ MX53_PAD_SD2_DATA3__ESDHC2_DAT3,
+ /* SD3 */
+ MX53_PAD_PATA_DATA8__ESDHC3_DAT0,
+ MX53_PAD_PATA_DATA9__ESDHC3_DAT1,
+ MX53_PAD_PATA_DATA10__ESDHC3_DAT2,
+ MX53_PAD_PATA_DATA11__ESDHC3_DAT3,
+ MX53_PAD_PATA_DATA0__ESDHC3_DAT4,
+ MX53_PAD_PATA_DATA1__ESDHC3_DAT5,
+ MX53_PAD_PATA_DATA2__ESDHC3_DAT6,
+ MX53_PAD_PATA_DATA3__ESDHC3_DAT7,
+ MX53_PAD_PATA_IORDY__ESDHC3_CLK,
+ MX53_PAD_PATA_RESET_B__ESDHC3_CMD,
};
static const struct imxuart_platform_data mx53_smd_uart_data __initconst = {
@@ -97,6 +120,9 @@
imx53_add_fec(&mx53_smd_fec_data);
imx53_add_imx2_wdt(0, NULL);
imx53_add_imx_i2c(0, &mx53_smd_i2c_data);
+ imx53_add_sdhci_esdhc_imx(0, NULL);
+ imx53_add_sdhci_esdhc_imx(1, NULL);
+ imx53_add_sdhci_esdhc_imx(2, NULL);
}
static void __init mx53_smd_timer_init(void)
diff --git a/arch/arm/mach-mx5/clock-mx51-mx53.c b/arch/arm/mach-mx5/clock-mx51-mx53.c
index fdbc05e..6b89c1b 100644
--- a/arch/arm/mach-mx5/clock-mx51-mx53.c
+++ b/arch/arm/mach-mx5/clock-mx51-mx53.c
@@ -1563,6 +1563,7 @@
clk_enable(&iim_clk);
mx53_revision();
clk_disable(&iim_clk);
+ mx53_display_revision();
/* Set SDHC parents to be PLL2 */
clk_set_parent(&esdhc1_clk, &pll2_sw_clk);
diff --git a/arch/arm/mach-mx5/cpu.c b/arch/arm/mach-mx5/cpu.c
index 472bdfa..86f87da 100644
--- a/arch/arm/mach-mx5/cpu.c
+++ b/arch/arm/mach-mx5/cpu.c
@@ -166,6 +166,29 @@
}
EXPORT_SYMBOL(mx50_revision);
+void mx53_display_revision(void)
+{
+ int rev;
+ char *srev;
+ rev = mx53_revision();
+
+ switch (rev) {
+ case IMX_CHIP_REVISION_1_0:
+ srev = IMX_CHIP_REVISION_1_0_STRING;
+ break;
+ case IMX_CHIP_REVISION_2_0:
+ srev = IMX_CHIP_REVISION_2_0_STRING;
+ break;
+ case IMX_CHIP_REVISION_2_1:
+ srev = IMX_CHIP_REVISION_2_1_STRING;
+ break;
+ default:
+ srev = IMX_CHIP_REVISION_UNKNOWN_STRING;
+ }
+ printk(KERN_INFO "CPU identified as i.MX53, silicon rev %s\n", srev);
+}
+EXPORT_SYMBOL(mx53_display_revision);
+
static int __init post_cpu_init(void)
{
unsigned int reg;
diff --git a/arch/arm/mach-mx5/devices-imx50.h b/arch/arm/mach-mx5/devices-imx50.h
index c9e4282..7216667 100644
--- a/arch/arm/mach-mx5/devices-imx50.h
+++ b/arch/arm/mach-mx5/devices-imx50.h
@@ -21,14 +21,14 @@
#include <mach/mx50.h>
#include <mach/devices-common.h>
-extern const struct imx_imx_uart_1irq_data imx50_imx_uart_data[] __initconst;
+extern const struct imx_imx_uart_1irq_data imx50_imx_uart_data[];
#define imx50_add_imx_uart(id, pdata) \
imx_add_imx_uart_1irq(&imx50_imx_uart_data[id], pdata)
-extern const struct imx_fec_data imx50_fec_data __initconst;
+extern const struct imx_fec_data imx50_fec_data;
#define imx50_add_fec(pdata) \
imx_add_fec(&imx50_fec_data, pdata)
-extern const struct imx_imx_i2c_data imx50_imx_i2c_data[] __initconst;
+extern const struct imx_imx_i2c_data imx50_imx_i2c_data[];
#define imx50_add_imx_i2c(id, pdata) \
imx_add_imx_i2c(&imx50_imx_i2c_data[id], pdata)
diff --git a/arch/arm/mach-mx5/devices-imx51.h b/arch/arm/mach-mx5/devices-imx51.h
index 7fff485..e11bc0e 100644
--- a/arch/arm/mach-mx5/devices-imx51.h
+++ b/arch/arm/mach-mx5/devices-imx51.h
@@ -9,49 +9,46 @@
#include <mach/mx51.h>
#include <mach/devices-common.h>
-extern const struct imx_fec_data imx51_fec_data __initconst;
+extern const struct imx_fec_data imx51_fec_data;
#define imx51_add_fec(pdata) \
imx_add_fec(&imx51_fec_data, pdata)
-#define imx51_add_gpio_keys(pdata) imx_add_gpio_keys(pdata)
-
-extern const struct imx_imx_i2c_data imx51_imx_i2c_data[] __initconst;
+extern const struct imx_imx_i2c_data imx51_imx_i2c_data[];
#define imx51_add_imx_i2c(id, pdata) \
imx_add_imx_i2c(&imx51_imx_i2c_data[id], pdata)
-extern const struct imx_imx_ssi_data imx51_imx_ssi_data[] __initconst;
+extern const struct imx_imx_ssi_data imx51_imx_ssi_data[];
#define imx51_add_imx_ssi(id, pdata) \
imx_add_imx_ssi(&imx51_imx_ssi_data[id], pdata)
-extern const struct imx_imx_uart_1irq_data imx51_imx_uart_data[] __initconst;
+extern const struct imx_imx_uart_1irq_data imx51_imx_uart_data[];
#define imx51_add_imx_uart(id, pdata) \
imx_add_imx_uart_1irq(&imx51_imx_uart_data[id], pdata)
-extern const struct imx_mxc_nand_data imx51_mxc_nand_data __initconst;
+extern const struct imx_mxc_nand_data imx51_mxc_nand_data;
#define imx51_add_mxc_nand(pdata) \
imx_add_mxc_nand(&imx51_mxc_nand_data, pdata)
-extern const struct imx_sdhci_esdhc_imx_data
-imx51_sdhci_esdhc_imx_data[] __initconst;
+extern const struct imx_sdhci_esdhc_imx_data imx51_sdhci_esdhc_imx_data[];
#define imx51_add_sdhci_esdhc_imx(id, pdata) \
imx_add_sdhci_esdhc_imx(&imx51_sdhci_esdhc_imx_data[id], pdata)
-extern const struct imx_spi_imx_data imx51_cspi_data __initconst;
+extern const struct imx_spi_imx_data imx51_cspi_data;
#define imx51_add_cspi(pdata) \
imx_add_spi_imx(&imx51_cspi_data, pdata)
-extern const struct imx_spi_imx_data imx51_ecspi_data[] __initconst;
+extern const struct imx_spi_imx_data imx51_ecspi_data[];
#define imx51_add_ecspi(id, pdata) \
imx_add_spi_imx(&imx51_ecspi_data[id], pdata)
-extern const struct imx_imx2_wdt_data imx51_imx2_wdt_data[] __initconst;
+extern const struct imx_imx2_wdt_data imx51_imx2_wdt_data[];
#define imx51_add_imx2_wdt(id, pdata) \
imx_add_imx2_wdt(&imx51_imx2_wdt_data[id])
-extern const struct imx_mxc_pwm_data imx51_mxc_pwm_data[] __initconst;
+extern const struct imx_mxc_pwm_data imx51_mxc_pwm_data[];
#define imx51_add_mxc_pwm(id) \
imx_add_mxc_pwm(&imx51_mxc_pwm_data[id])
-extern const struct imx_imx_keypad_data imx51_imx_keypad_data __initconst;
+extern const struct imx_imx_keypad_data imx51_imx_keypad_data;
#define imx51_add_imx_keypad(pdata) \
imx_add_imx_keypad(&imx51_imx_keypad_data, pdata)
diff --git a/arch/arm/mach-mx5/devices-imx53.h b/arch/arm/mach-mx5/devices-imx53.h
index 9251008..48f4c8c 100644
--- a/arch/arm/mach-mx5/devices-imx53.h
+++ b/arch/arm/mach-mx5/devices-imx53.h
@@ -8,28 +8,27 @@
#include <mach/mx53.h>
#include <mach/devices-common.h>
-extern const struct imx_fec_data imx53_fec_data __initconst;
+extern const struct imx_fec_data imx53_fec_data;
#define imx53_add_fec(pdata) \
imx_add_fec(&imx53_fec_data, pdata)
-extern const struct imx_imx_uart_1irq_data imx53_imx_uart_data[] __initconst;
+extern const struct imx_imx_uart_1irq_data imx53_imx_uart_data[];
#define imx53_add_imx_uart(id, pdata) \
imx_add_imx_uart_1irq(&imx53_imx_uart_data[id], pdata)
-extern const struct imx_imx_i2c_data imx53_imx_i2c_data[] __initconst;
+extern const struct imx_imx_i2c_data imx53_imx_i2c_data[];
#define imx53_add_imx_i2c(id, pdata) \
imx_add_imx_i2c(&imx53_imx_i2c_data[id], pdata)
-extern const struct imx_sdhci_esdhc_imx_data
-imx53_sdhci_esdhc_imx_data[] __initconst;
+extern const struct imx_sdhci_esdhc_imx_data imx53_sdhci_esdhc_imx_data[];
#define imx53_add_sdhci_esdhc_imx(id, pdata) \
imx_add_sdhci_esdhc_imx(&imx53_sdhci_esdhc_imx_data[id], pdata)
-extern const struct imx_spi_imx_data imx53_ecspi_data[] __initconst;
+extern const struct imx_spi_imx_data imx53_ecspi_data[];
#define imx53_add_ecspi(id, pdata) \
imx_add_spi_imx(&imx53_ecspi_data[id], pdata)
-extern const struct imx_imx2_wdt_data imx53_imx2_wdt_data[] __initconst;
+extern const struct imx_imx2_wdt_data imx53_imx2_wdt_data[];
#define imx53_add_imx2_wdt(id, pdata) \
imx_add_imx2_wdt(&imx53_imx2_wdt_data[id])
diff --git a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
index 4a85505..97292d2 100644
--- a/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
+++ b/arch/arm/mach-mx5/eukrea_mbimx51-baseboard.c
@@ -18,13 +18,11 @@
#include <linux/io.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
-#include <linux/fsl_devices.h>
#include <linux/i2c/tsc2007.h>
#include <linux/leds.h>
#include <mach/common.h>
#include <mach/hardware.h>
-#include <mach/imx-uart.h>
#include <mach/iomux-mx51.h>
#include <asm/mach/arch.h>
diff --git a/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c b/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c
index e6c1119..31c871e 100644
--- a/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c
+++ b/arch/arm/mach-mx5/eukrea_mbimxsd-baseboard.c
@@ -27,7 +27,6 @@
#include <linux/irq.h>
#include <linux/leds.h>
#include <linux/platform_device.h>
-#include <linux/gpio_keys.h>
#include <linux/input.h>
#include <linux/i2c.h>
@@ -38,7 +37,6 @@
#include <mach/hardware.h>
#include <mach/common.h>
-#include <mach/imx-uart.h>
#include <mach/iomux-mx51.h>
#include <mach/audmux.h>
@@ -108,23 +106,14 @@
},
};
-static struct gpio_keys_platform_data eukrea_mbimxsd_button_data = {
+static const struct gpio_keys_platform_data
+ eukrea_mbimxsd_button_data __initconst = {
.buttons = eukrea_mbimxsd_gpio_buttons,
.nbuttons = ARRAY_SIZE(eukrea_mbimxsd_gpio_buttons),
};
-static struct platform_device eukrea_mbimxsd_button_device = {
- .name = "gpio-keys",
- .id = -1,
- .num_resources = 0,
- .dev = {
- .platform_data = &eukrea_mbimxsd_button_data,
- }
-};
-
static struct platform_device *platform_devices[] __initdata = {
&eukrea_mbimxsd_leds_gpio,
- &eukrea_mbimxsd_button_device,
};
static const struct imxuart_platform_data uart_pdata __initconst = {
@@ -166,4 +155,5 @@
ARRAY_SIZE(eukrea_mbimxsd_i2c_devices));
platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
+ imx_add_gpio_keys(&eukrea_mbimxsd_button_data);
}
diff --git a/arch/arm/mach-mx5/mx51_efika.c b/arch/arm/mach-mx5/mx51_efika.c
index d0c7075..56739c2 100644
--- a/arch/arm/mach-mx5/mx51_efika.c
+++ b/arch/arm/mach-mx5/mx51_efika.c
@@ -20,7 +20,6 @@
#include <linux/input.h>
#include <linux/delay.h>
#include <linux/io.h>
-#include <linux/fsl_devices.h>
#include <linux/spi/flash.h>
#include <linux/spi/spi.h>
#include <linux/mfd/mc13892.h>
@@ -30,8 +29,6 @@
#include <mach/common.h>
#include <mach/hardware.h>
#include <mach/iomux-mx51.h>
-#include <mach/i2c.h>
-#include <mach/mxc_ehci.h>
#include <linux/usb/otg.h>
#include <linux/usb/ulpi.h>
diff --git a/arch/arm/mach-mxc91231/Kconfig b/arch/arm/mach-mxc91231/Kconfig
deleted file mode 100644
index 8e5fa38..0000000
--- a/arch/arm/mach-mxc91231/Kconfig
+++ /dev/null
@@ -1,11 +0,0 @@
-if ARCH_MXC91231
-
-comment "MXC91231 platforms:"
-
-config MACH_MAGX_ZN5
- bool "Support Motorola Zn5 GSM phone"
- default n
- help
- Include support for Motorola Zn5 GSM phone.
-
-endif
diff --git a/arch/arm/mach-mxc91231/Makefile b/arch/arm/mach-mxc91231/Makefile
deleted file mode 100644
index 011d5e1..0000000
--- a/arch/arm/mach-mxc91231/Makefile
+++ /dev/null
@@ -1,2 +0,0 @@
-obj-y := mm.o clock.o devices.o system.o iomux.o
-obj-$(CONFIG_MACH_MAGX_ZN5) += magx-zn5.o
diff --git a/arch/arm/mach-mxc91231/Makefile.boot b/arch/arm/mach-mxc91231/Makefile.boot
deleted file mode 100644
index 9939a19..0000000
--- a/arch/arm/mach-mxc91231/Makefile.boot
+++ /dev/null
@@ -1,3 +0,0 @@
- zreladdr-y := 0x90008000
-params_phys-y := 0x90000100
-initrd_phys-y := 0x90800000
diff --git a/arch/arm/mach-mxc91231/clock.c b/arch/arm/mach-mxc91231/clock.c
deleted file mode 100644
index 9fab505..0000000
--- a/arch/arm/mach-mxc91231/clock.c
+++ /dev/null
@@ -1,640 +0,0 @@
-#include <linux/clk.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/clkdev.h>
-
-#include <mach/clock.h>
-#include <mach/hardware.h>
-#include <mach/common.h>
-
-#include <asm/bug.h>
-#include <asm/div64.h>
-
-#include "crm_regs.h"
-
-#define CRM_SMALL_DIVIDER(base, name) \
- crm_small_divider(base, \
- base ## _ ## name ## _OFFSET, \
- base ## _ ## name ## _MASK)
-#define CRM_1DIVIDER(base, name) \
- crm_divider(base, \
- base ## _ ## name ## _OFFSET, \
- base ## _ ## name ## _MASK, 1)
-#define CRM_16DIVIDER(base, name) \
- crm_divider(base, \
- base ## _ ## name ## _OFFSET, \
- base ## _ ## name ## _MASK, 16)
-
-static u32 crm_small_divider(void __iomem *reg, u8 offset, u32 mask)
-{
- static const u32 crm_small_dividers[] = {
- 2, 3, 4, 5, 6, 8, 10, 12
- };
- u8 idx;
-
- idx = (__raw_readl(reg) & mask) >> offset;
- if (idx > 7)
- return 1;
-
- return crm_small_dividers[idx];
-}
-
-static u32 crm_divider(void __iomem *reg, u8 offset, u32 mask, u32 z)
-{
- u32 div;
- div = (__raw_readl(reg) & mask) >> offset;
- return div ? div : z;
-}
-
-static int _clk_1bit_enable(struct clk *clk)
-{
- u32 reg;
-
- reg = __raw_readl(clk->enable_reg);
- reg |= 1 << clk->enable_shift;
- __raw_writel(reg, clk->enable_reg);
-
- return 0;
-}
-
-static void _clk_1bit_disable(struct clk *clk)
-{
- u32 reg;
-
- reg = __raw_readl(clk->enable_reg);
- reg &= ~(1 << clk->enable_shift);
- __raw_writel(reg, clk->enable_reg);
-}
-
-static int _clk_3bit_enable(struct clk *clk)
-{
- u32 reg;
-
- reg = __raw_readl(clk->enable_reg);
- reg |= 0x7 << clk->enable_shift;
- __raw_writel(reg, clk->enable_reg);
-
- return 0;
-}
-
-static void _clk_3bit_disable(struct clk *clk)
-{
- u32 reg;
-
- reg = __raw_readl(clk->enable_reg);
- reg &= ~(0x7 << clk->enable_shift);
- __raw_writel(reg, clk->enable_reg);
-}
-
-static unsigned long ckih_rate;
-
-static unsigned long clk_ckih_get_rate(struct clk *clk)
-{
- return ckih_rate;
-}
-
-static struct clk ckih_clk = {
- .get_rate = clk_ckih_get_rate,
-};
-
-static unsigned long clk_ckih_x2_get_rate(struct clk *clk)
-{
- return 2 * clk_get_rate(clk->parent);
-}
-
-static struct clk ckih_x2_clk = {
- .parent = &ckih_clk,
- .get_rate = clk_ckih_x2_get_rate,
-};
-
-static unsigned long clk_ckil_get_rate(struct clk *clk)
-{
- return CKIL_CLK_FREQ;
-}
-
-static struct clk ckil_clk = {
- .get_rate = clk_ckil_get_rate,
-};
-
-/* plls stuff */
-static struct clk mcu_pll_clk;
-static struct clk dsp_pll_clk;
-static struct clk usb_pll_clk;
-
-static struct clk *pll_clk(u8 sel)
-{
- switch (sel) {
- case 0:
- return &mcu_pll_clk;
- case 1:
- return &dsp_pll_clk;
- case 2:
- return &usb_pll_clk;
- }
- BUG();
-}
-
-static void __iomem *pll_base(struct clk *clk)
-{
- if (clk == &mcu_pll_clk)
- return MXC_PLL0_BASE;
- else if (clk == &dsp_pll_clk)
- return MXC_PLL1_BASE;
- else if (clk == &usb_pll_clk)
- return MXC_PLL2_BASE;
- BUG();
-}
-
-static unsigned long clk_pll_get_rate(struct clk *clk)
-{
- const void __iomem *pllbase;
- unsigned long dp_op, dp_mfd, dp_mfn, pll_hfsm, ref_clk, mfi;
- long mfn, mfn_abs, mfd, pdf;
- s64 temp;
- pllbase = pll_base(clk);
-
- pll_hfsm = __raw_readl(pllbase + MXC_PLL_DP_CTL) & MXC_PLL_DP_CTL_HFSM;
- if (pll_hfsm == 0) {
- dp_op = __raw_readl(pllbase + MXC_PLL_DP_OP);
- dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_MFD);
- dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_MFN);
- } else {
- dp_op = __raw_readl(pllbase + MXC_PLL_DP_HFS_OP);
- dp_mfd = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFD);
- dp_mfn = __raw_readl(pllbase + MXC_PLL_DP_HFS_MFN);
- }
-
- pdf = dp_op & MXC_PLL_DP_OP_PDF_MASK;
- mfi = (dp_op >> MXC_PLL_DP_OP_MFI_OFFSET) & MXC_PLL_DP_OP_PDF_MASK;
- mfi = (mfi <= 5) ? 5 : mfi;
- mfd = dp_mfd & MXC_PLL_DP_MFD_MASK;
- mfn = dp_mfn & MXC_PLL_DP_MFN_MASK;
- mfn = (mfn <= 0x4000000) ? mfn : (mfn - 0x10000000);
-
- if (mfn < 0)
- mfn_abs = -mfn;
- else
- mfn_abs = mfn;
-
-/* XXX: actually this asumes that ckih is fed to pll, but spec says
- * that ckih_x2 is also possible. need to check this out.
- */
- ref_clk = clk_get_rate(&ckih_clk);
-
- ref_clk *= 2;
- ref_clk /= pdf + 1;
-
- temp = (u64) ref_clk * mfn_abs;
- do_div(temp, mfd);
- if (mfn < 0)
- temp = -temp;
- temp += ref_clk * mfi;
-
- return temp;
-}
-
-static int clk_pll_enable(struct clk *clk)
-{
- void __iomem *ctl;
- u32 reg;
-
- ctl = pll_base(clk);
- reg = __raw_readl(ctl);
- reg |= (MXC_PLL_DP_CTL_RST | MXC_PLL_DP_CTL_UPEN);
- __raw_writel(reg, ctl);
- do {
- reg = __raw_readl(ctl);
- } while ((reg & MXC_PLL_DP_CTL_LRF) != MXC_PLL_DP_CTL_LRF);
- return 0;
-}
-
-static void clk_pll_disable(struct clk *clk)
-{
- void __iomem *ctl;
- u32 reg;
-
- ctl = pll_base(clk);
- reg = __raw_readl(ctl);
- reg &= ~(MXC_PLL_DP_CTL_RST | MXC_PLL_DP_CTL_UPEN);
- __raw_writel(reg, ctl);
-}
-
-static struct clk mcu_pll_clk = {
- .parent = &ckih_clk,
- .get_rate = clk_pll_get_rate,
- .enable = clk_pll_enable,
- .disable = clk_pll_disable,
-};
-
-static struct clk dsp_pll_clk = {
- .parent = &ckih_clk,
- .get_rate = clk_pll_get_rate,
- .enable = clk_pll_enable,
- .disable = clk_pll_disable,
-};
-
-static struct clk usb_pll_clk = {
- .parent = &ckih_clk,
- .get_rate = clk_pll_get_rate,
- .enable = clk_pll_enable,
- .disable = clk_pll_disable,
-};
-/* plls stuff end */
-
-/* ap_ref_clk stuff */
-static struct clk ap_ref_clk;
-
-static unsigned long clk_ap_ref_get_rate(struct clk *clk)
-{
- u32 ascsr, acsr;
- u8 ap_pat_ref_div_2, ap_isel, acs, ads;
-
- ascsr = __raw_readl(MXC_CRMAP_ASCSR);
- acsr = __raw_readl(MXC_CRMAP_ACSR);
-
- /* 0 for ckih, 1 for ckih*2 */
- ap_isel = ascsr & MXC_CRMAP_ASCSR_APISEL;
- /* reg divider */
- ap_pat_ref_div_2 = (ascsr >> MXC_CRMAP_ASCSR_AP_PATDIV2_OFFSET) & 0x1;
- /* undocumented, 1 for disabling divider */
- ads = (acsr >> MXC_CRMAP_ACSR_ADS_OFFSET) & 0x1;
- /* 0 for pat_ref, 1 for divider out */
- acs = acsr & MXC_CRMAP_ACSR_ACS;
-
- if (acs & !ads)
- /* use divided clock */
- return clk_get_rate(clk->parent) / (ap_pat_ref_div_2 ? 2 : 1);
-
- return clk_get_rate(clk->parent) * (ap_isel ? 2 : 1);
-}
-
-static struct clk ap_ref_clk = {
- .parent = &ckih_clk,
- .get_rate = clk_ap_ref_get_rate,
-};
-/* ap_ref_clk stuff end */
-
-/* ap_pre_dfs_clk stuff */
-static struct clk ap_pre_dfs_clk;
-
-static unsigned long clk_ap_pre_dfs_get_rate(struct clk *clk)
-{
- u32 acsr, ascsr;
-
- acsr = __raw_readl(MXC_CRMAP_ACSR);
- ascsr = __raw_readl(MXC_CRMAP_ASCSR);
-
- if (acsr & MXC_CRMAP_ACSR_ACS) {
- u8 sel;
- sel = (ascsr & MXC_CRMAP_ASCSR_APSEL_MASK) >>
- MXC_CRMAP_ASCSR_APSEL_OFFSET;
- return clk_get_rate(pll_clk(sel)) /
- CRM_SMALL_DIVIDER(MXC_CRMAP_ACDR, ARMDIV);
- }
- return clk_get_rate(&ap_ref_clk);
-}
-
-static struct clk ap_pre_dfs_clk = {
- .get_rate = clk_ap_pre_dfs_get_rate,
-};
-/* ap_pre_dfs_clk stuff end */
-
-/* usb_clk stuff */
-static struct clk usb_clk;
-
-static struct clk *clk_usb_parent(struct clk *clk)
-{
- u32 acsr, ascsr;
-
- acsr = __raw_readl(MXC_CRMAP_ACSR);
- ascsr = __raw_readl(MXC_CRMAP_ASCSR);
-
- if (acsr & MXC_CRMAP_ACSR_ACS) {
- u8 sel;
- sel = (ascsr & MXC_CRMAP_ASCSR_USBSEL_MASK) >>
- MXC_CRMAP_ASCSR_USBSEL_OFFSET;
- return pll_clk(sel);
- }
- return &ap_ref_clk;
-}
-
-static unsigned long clk_usb_get_rate(struct clk *clk)
-{
- return clk_get_rate(clk->parent) /
- CRM_SMALL_DIVIDER(MXC_CRMAP_ACDER2, USBDIV);
-}
-
-static struct clk usb_clk = {
- .enable_reg = MXC_CRMAP_ACDER2,
- .enable_shift = MXC_CRMAP_ACDER2_USBEN_OFFSET,
- .get_rate = clk_usb_get_rate,
- .enable = _clk_1bit_enable,
- .disable = _clk_1bit_disable,
-};
-/* usb_clk stuff end */
-
-static unsigned long clk_ipg_get_rate(struct clk *clk)
-{
- return clk_get_rate(clk->parent) / CRM_16DIVIDER(MXC_CRMAP_ACDR, IPDIV);
-}
-
-static unsigned long clk_ahb_get_rate(struct clk *clk)
-{
- return clk_get_rate(clk->parent) /
- CRM_16DIVIDER(MXC_CRMAP_ACDR, AHBDIV);
-}
-
-static struct clk ipg_clk = {
- .parent = &ap_pre_dfs_clk,
- .get_rate = clk_ipg_get_rate,
-};
-
-static struct clk ahb_clk = {
- .parent = &ap_pre_dfs_clk,
- .get_rate = clk_ahb_get_rate,
-};
-
-/* perclk_clk stuff */
-static struct clk perclk_clk;
-
-static unsigned long clk_perclk_get_rate(struct clk *clk)
-{
- u32 acder2;
-
- acder2 = __raw_readl(MXC_CRMAP_ACDER2);
- if (acder2 & MXC_CRMAP_ACDER2_BAUD_ISEL_MASK)
- return 2 * clk_get_rate(clk->parent);
-
- return clk_get_rate(clk->parent);
-}
-
-static struct clk perclk_clk = {
- .parent = &ckih_clk,
- .get_rate = clk_perclk_get_rate,
-};
-/* perclk_clk stuff end */
-
-/* uart_clk stuff */
-static struct clk uart_clk[];
-
-static unsigned long clk_uart_get_rate(struct clk *clk)
-{
- u32 div;
-
- switch (clk->id) {
- case 0:
- case 1:
- div = CRM_SMALL_DIVIDER(MXC_CRMAP_ACDER2, BAUDDIV);
- break;
- case 2:
- div = CRM_SMALL_DIVIDER(MXC_CRMAP_APRA, UART3DIV);
- break;
- default:
- BUG();
- }
- return clk_get_rate(clk->parent) / div;
-}
-
-static struct clk uart_clk[] = {
- {
- .id = 0,
- .parent = &perclk_clk,
- .enable_reg = MXC_CRMAP_APRA,
- .enable_shift = MXC_CRMAP_APRA_UART1EN_OFFSET,
- .get_rate = clk_uart_get_rate,
- .enable = _clk_1bit_enable,
- .disable = _clk_1bit_disable,
- }, {
- .id = 1,
- .parent = &perclk_clk,
- .enable_reg = MXC_CRMAP_APRA,
- .enable_shift = MXC_CRMAP_APRA_UART2EN_OFFSET,
- .get_rate = clk_uart_get_rate,
- .enable = _clk_1bit_enable,
- .disable = _clk_1bit_disable,
- }, {
- .id = 2,
- .parent = &perclk_clk,
- .enable_reg = MXC_CRMAP_APRA,
- .enable_shift = MXC_CRMAP_APRA_UART3EN_OFFSET,
- .get_rate = clk_uart_get_rate,
- .enable = _clk_1bit_enable,
- .disable = _clk_1bit_disable,
- },
-};
-/* uart_clk stuff end */
-
-/* sdhc_clk stuff */
-static struct clk nfc_clk;
-
-static unsigned long clk_nfc_get_rate(struct clk *clk)
-{
- return clk_get_rate(clk->parent) /
- CRM_1DIVIDER(MXC_CRMAP_ACDER2, NFCDIV);
-}
-
-static struct clk nfc_clk = {
- .parent = &ahb_clk,
- .enable_reg = MXC_CRMAP_ACDER2,
- .enable_shift = MXC_CRMAP_ACDER2_NFCEN_OFFSET,
- .get_rate = clk_nfc_get_rate,
- .enable = _clk_1bit_enable,
- .disable = _clk_1bit_disable,
-};
-/* sdhc_clk stuff end */
-
-/* sdhc_clk stuff */
-static struct clk sdhc_clk[];
-
-static struct clk *clk_sdhc_parent(struct clk *clk)
-{
- u32 aprb;
- u8 sel;
- u32 mask;
- int offset;
-
- aprb = __raw_readl(MXC_CRMAP_APRB);
-
- switch (clk->id) {
- case 0:
- mask = MXC_CRMAP_APRB_SDHC1_ISEL_MASK;
- offset = MXC_CRMAP_APRB_SDHC1_ISEL_OFFSET;
- break;
- case 1:
- mask = MXC_CRMAP_APRB_SDHC2_ISEL_MASK;
- offset = MXC_CRMAP_APRB_SDHC2_ISEL_OFFSET;
- break;
- default:
- BUG();
- }
- sel = (aprb & mask) >> offset;
-
- switch (sel) {
- case 0:
- return &ckih_clk;
- case 1:
- return &ckih_x2_clk;
- }
- return &usb_clk;
-}
-
-static unsigned long clk_sdhc_get_rate(struct clk *clk)
-{
- u32 div;
-
- switch (clk->id) {
- case 0:
- div = CRM_SMALL_DIVIDER(MXC_CRMAP_APRB, SDHC1_DIV);
- break;
- case 1:
- div = CRM_SMALL_DIVIDER(MXC_CRMAP_APRB, SDHC2_DIV);
- break;
- default:
- BUG();
- }
-
- return clk_get_rate(clk->parent) / div;
-}
-
-static int clk_sdhc_enable(struct clk *clk)
-{
- u32 amlpmre1, aprb;
-
- amlpmre1 = __raw_readl(MXC_CRMAP_AMLPMRE1);
- aprb = __raw_readl(MXC_CRMAP_APRB);
- switch (clk->id) {
- case 0:
- amlpmre1 |= (0x7 << MXC_CRMAP_AMLPMRE1_MLPME4_OFFSET);
- aprb |= (0x1 << MXC_CRMAP_APRB_SDHC1EN_OFFSET);
- break;
- case 1:
- amlpmre1 |= (0x7 << MXC_CRMAP_AMLPMRE1_MLPME5_OFFSET);
- aprb |= (0x1 << MXC_CRMAP_APRB_SDHC2EN_OFFSET);
- break;
- }
- __raw_writel(amlpmre1, MXC_CRMAP_AMLPMRE1);
- __raw_writel(aprb, MXC_CRMAP_APRB);
- return 0;
-}
-
-static void clk_sdhc_disable(struct clk *clk)
-{
- u32 amlpmre1, aprb;
-
- amlpmre1 = __raw_readl(MXC_CRMAP_AMLPMRE1);
- aprb = __raw_readl(MXC_CRMAP_APRB);
- switch (clk->id) {
- case 0:
- amlpmre1 &= ~(0x7 << MXC_CRMAP_AMLPMRE1_MLPME4_OFFSET);
- aprb &= ~(0x1 << MXC_CRMAP_APRB_SDHC1EN_OFFSET);
- break;
- case 1:
- amlpmre1 &= ~(0x7 << MXC_CRMAP_AMLPMRE1_MLPME5_OFFSET);
- aprb &= ~(0x1 << MXC_CRMAP_APRB_SDHC2EN_OFFSET);
- break;
- }
- __raw_writel(amlpmre1, MXC_CRMAP_AMLPMRE1);
- __raw_writel(aprb, MXC_CRMAP_APRB);
-}
-
-static struct clk sdhc_clk[] = {
- {
- .id = 0,
- .get_rate = clk_sdhc_get_rate,
- .enable = clk_sdhc_enable,
- .disable = clk_sdhc_disable,
- }, {
- .id = 1,
- .get_rate = clk_sdhc_get_rate,
- .enable = clk_sdhc_enable,
- .disable = clk_sdhc_disable,
- },
-};
-/* sdhc_clk stuff end */
-
-/* wdog_clk stuff */
-static struct clk wdog_clk[] = {
- {
- .id = 0,
- .parent = &ipg_clk,
- .enable_reg = MXC_CRMAP_AMLPMRD,
- .enable_shift = MXC_CRMAP_AMLPMRD_MLPMD7_OFFSET,
- .enable = _clk_3bit_enable,
- .disable = _clk_3bit_disable,
- }, {
- .id = 1,
- .parent = &ipg_clk,
- .enable_reg = MXC_CRMAP_AMLPMRD,
- .enable_shift = MXC_CRMAP_AMLPMRD_MLPMD3_OFFSET,
- .enable = _clk_3bit_enable,
- .disable = _clk_3bit_disable,
- },
-};
-/* wdog_clk stuff end */
-
-/* gpt_clk stuff */
-static struct clk gpt_clk = {
- .parent = &ipg_clk,
- .enable_reg = MXC_CRMAP_AMLPMRC,
- .enable_shift = MXC_CRMAP_AMLPMRC_MLPMC4_OFFSET,
- .enable = _clk_3bit_enable,
- .disable = _clk_3bit_disable,
-};
-/* gpt_clk stuff end */
-
-/* cspi_clk stuff */
-static struct clk cspi_clk[] = {
- {
- .id = 0,
- .parent = &ipg_clk,
- .enable_reg = MXC_CRMAP_AMLPMRE2,
- .enable_shift = MXC_CRMAP_AMLPMRE2_MLPME0_OFFSET,
- .enable = _clk_3bit_enable,
- .disable = _clk_3bit_disable,
- }, {
- .id = 1,
- .parent = &ipg_clk,
- .enable_reg = MXC_CRMAP_AMLPMRE1,
- .enable_shift = MXC_CRMAP_AMLPMRE1_MLPME6_OFFSET,
- .enable = _clk_3bit_enable,
- .disable = _clk_3bit_disable,
- },
-};
-/* cspi_clk stuff end */
-
-#define _REGISTER_CLOCK(d, n, c) \
- { \
- .dev_id = d, \
- .con_id = n, \
- .clk = &c, \
- },
-
-static struct clk_lookup lookups[] = {
- _REGISTER_CLOCK("imx-uart.0", NULL, uart_clk[0])
- _REGISTER_CLOCK("imx-uart.1", NULL, uart_clk[1])
- _REGISTER_CLOCK("imx-uart.2", NULL, uart_clk[2])
- _REGISTER_CLOCK("mxc-mmc.0", NULL, sdhc_clk[0])
- _REGISTER_CLOCK("mxc-mmc.1", NULL, sdhc_clk[1])
- _REGISTER_CLOCK("mxc-wdt.0", NULL, wdog_clk[0])
- _REGISTER_CLOCK("spi_imx.0", NULL, cspi_clk[0])
- _REGISTER_CLOCK("spi_imx.1", NULL, cspi_clk[1])
-};
-
-int __init mxc91231_clocks_init(unsigned long fref)
-{
- void __iomem *gpt_base;
-
- ckih_rate = fref;
-
- usb_clk.parent = clk_usb_parent(&usb_clk);
- sdhc_clk[0].parent = clk_sdhc_parent(&sdhc_clk[0]);
- sdhc_clk[1].parent = clk_sdhc_parent(&sdhc_clk[1]);
-
- clkdev_add_table(lookups, ARRAY_SIZE(lookups));
-
- gpt_base = MXC91231_IO_ADDRESS(MXC91231_GPT1_BASE_ADDR);
- mxc_timer_init(&gpt_clk, gpt_base, MXC91231_INT_GPT);
-
- return 0;
-}
diff --git a/arch/arm/mach-mxc91231/crm_regs.h b/arch/arm/mach-mxc91231/crm_regs.h
deleted file mode 100644
index b989bac..0000000
--- a/arch/arm/mach-mxc91231/crm_regs.h
+++ /dev/null
@@ -1,394 +0,0 @@
-/*
- * Copyright 2006 Freescale Semiconductor, Inc.
- * Copyright 2006-2007 Motorola, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _ARCH_ARM_MACH_MXC91231_CRM_REGS_H_
-#define _ARCH_ARM_MACH_MXC91231_CRM_REGS_H_
-
-#define CKIL_CLK_FREQ 32768
-
-#define MXC_CRM_AP_BASE MXC91231_IO_ADDRESS(MXC91231_CRM_AP_BASE_ADDR)
-#define MXC_CRM_COM_BASE MXC91231_IO_ADDRESS(MXC91231_CRM_COM_BASE_ADDR)
-#define MXC_DSM_BASE MXC91231_IO_ADDRESS(MXC91231_DSM_BASE_ADDR)
-#define MXC_PLL0_BASE MXC91231_IO_ADDRESS(MXC91231_PLL0_BASE_ADDR)
-#define MXC_PLL1_BASE MXC91231_IO_ADDRESS(MXC91231_PLL1_BASE_ADDR)
-#define MXC_PLL2_BASE MXC91231_IO_ADDRESS(MXC91231_PLL2_BASE_ADDR)
-#define MXC_CLKCTL_BASE MXC91231_IO_ADDRESS(MXC91231_CLKCTL_BASE_ADDR)
-
-/* PLL Register Offsets */
-#define MXC_PLL_DP_CTL 0x00
-#define MXC_PLL_DP_CONFIG 0x04
-#define MXC_PLL_DP_OP 0x08
-#define MXC_PLL_DP_MFD 0x0C
-#define MXC_PLL_DP_MFN 0x10
-#define MXC_PLL_DP_HFS_OP 0x1C
-#define MXC_PLL_DP_HFS_MFD 0x20
-#define MXC_PLL_DP_HFS_MFN 0x24
-
-/* PLL Register Bit definitions */
-#define MXC_PLL_DP_CTL_DPDCK0_2_EN 0x1000
-#define MXC_PLL_DP_CTL_ADE 0x800
-#define MXC_PLL_DP_CTL_REF_CLK_DIV 0x400
-#define MXC_PLL_DP_CTL_HFSM 0x80
-#define MXC_PLL_DP_CTL_PRE 0x40
-#define MXC_PLL_DP_CTL_UPEN 0x20
-#define MXC_PLL_DP_CTL_RST 0x10
-#define MXC_PLL_DP_CTL_RCP 0x8
-#define MXC_PLL_DP_CTL_PLM 0x4
-#define MXC_PLL_DP_CTL_BRM0 0x2
-#define MXC_PLL_DP_CTL_LRF 0x1
-
-#define MXC_PLL_DP_OP_MFI_OFFSET 4
-#define MXC_PLL_DP_OP_MFI_MASK 0xF
-#define MXC_PLL_DP_OP_PDF_OFFSET 0
-#define MXC_PLL_DP_OP_PDF_MASK 0xF
-
-#define MXC_PLL_DP_MFD_OFFSET 0
-#define MXC_PLL_DP_MFD_MASK 0x7FFFFFF
-
-#define MXC_PLL_DP_MFN_OFFSET 0
-#define MXC_PLL_DP_MFN_MASK 0x7FFFFFF
-
-/* CRM AP Register Offsets */
-#define MXC_CRMAP_ASCSR (MXC_CRM_AP_BASE + 0x00)
-#define MXC_CRMAP_ACDR (MXC_CRM_AP_BASE + 0x04)
-#define MXC_CRMAP_ACDER1 (MXC_CRM_AP_BASE + 0x08)
-#define MXC_CRMAP_ACDER2 (MXC_CRM_AP_BASE + 0x0C)
-#define MXC_CRMAP_ACGCR (MXC_CRM_AP_BASE + 0x10)
-#define MXC_CRMAP_ACCGCR (MXC_CRM_AP_BASE + 0x14)
-#define MXC_CRMAP_AMLPMRA (MXC_CRM_AP_BASE + 0x18)
-#define MXC_CRMAP_AMLPMRB (MXC_CRM_AP_BASE + 0x1C)
-#define MXC_CRMAP_AMLPMRC (MXC_CRM_AP_BASE + 0x20)
-#define MXC_CRMAP_AMLPMRD (MXC_CRM_AP_BASE + 0x24)
-#define MXC_CRMAP_AMLPMRE1 (MXC_CRM_AP_BASE + 0x28)
-#define MXC_CRMAP_AMLPMRE2 (MXC_CRM_AP_BASE + 0x2C)
-#define MXC_CRMAP_AMLPMRF (MXC_CRM_AP_BASE + 0x30)
-#define MXC_CRMAP_AMLPMRG (MXC_CRM_AP_BASE + 0x34)
-#define MXC_CRMAP_APGCR (MXC_CRM_AP_BASE + 0x38)
-#define MXC_CRMAP_ACSR (MXC_CRM_AP_BASE + 0x3C)
-#define MXC_CRMAP_ADCR (MXC_CRM_AP_BASE + 0x40)
-#define MXC_CRMAP_ACR (MXC_CRM_AP_BASE + 0x44)
-#define MXC_CRMAP_AMCR (MXC_CRM_AP_BASE + 0x48)
-#define MXC_CRMAP_APCR (MXC_CRM_AP_BASE + 0x4C)
-#define MXC_CRMAP_AMORA (MXC_CRM_AP_BASE + 0x50)
-#define MXC_CRMAP_AMORB (MXC_CRM_AP_BASE + 0x54)
-#define MXC_CRMAP_AGPR (MXC_CRM_AP_BASE + 0x58)
-#define MXC_CRMAP_APRA (MXC_CRM_AP_BASE + 0x5C)
-#define MXC_CRMAP_APRB (MXC_CRM_AP_BASE + 0x60)
-#define MXC_CRMAP_APOR (MXC_CRM_AP_BASE + 0x64)
-#define MXC_CRMAP_ADFMR (MXC_CRM_AP_BASE + 0x68)
-
-/* CRM AP Register Bit definitions */
-#define MXC_CRMAP_ASCSR_CRS 0x10000
-#define MXC_CRMAP_ASCSR_AP_PATDIV2_OFFSET 15
-#define MXC_CRMAP_ASCSR_AP_PATREF_DIV2 0x8000
-#define MXC_CRMAP_ASCSR_USBSEL_OFFSET 13
-#define MXC_CRMAP_ASCSR_USBSEL_MASK (0x3 << 13)
-#define MXC_CRMAP_ASCSR_CSISEL_OFFSET 11
-#define MXC_CRMAP_ASCSR_CSISEL_MASK (0x3 << 11)
-#define MXC_CRMAP_ASCSR_SSI2SEL_OFFSET 7
-#define MXC_CRMAP_ASCSR_SSI2SEL_MASK (0x3 << 7)
-#define MXC_CRMAP_ASCSR_SSI1SEL_OFFSET 5
-#define MXC_CRMAP_ASCSR_SSI1SEL_MASK (0x3 << 5)
-#define MXC_CRMAP_ASCSR_APSEL_OFFSET 3
-#define MXC_CRMAP_ASCSR_APSEL_MASK (0x3 << 3)
-#define MXC_CRMAP_ASCSR_AP_PATDIV1_OFFSET 2
-#define MXC_CRMAP_ASCSR_AP_PATREF_DIV1 0x4
-#define MXC_CRMAP_ASCSR_APISEL 0x1
-
-#define MXC_CRMAP_ACDR_ARMDIV_OFFSET 8
-#define MXC_CRMAP_ACDR_ARMDIV_MASK (0xF << 8)
-#define MXC_CRMAP_ACDR_AHBDIV_OFFSET 4
-#define MXC_CRMAP_ACDR_AHBDIV_MASK (0xF << 4)
-#define MXC_CRMAP_ACDR_IPDIV_OFFSET 0
-#define MXC_CRMAP_ACDR_IPDIV_MASK 0xF
-
-#define MXC_CRMAP_ACDER1_CSIEN_OFFSET 30
-#define MXC_CRMAP_ACDER1_CSIDIV_OFFSET 24
-#define MXC_CRMAP_ACDER1_CSIDIV_MASK (0x3F << 24)
-#define MXC_CRMAP_ACDER1_SSI2EN_OFFSET 14
-#define MXC_CRMAP_ACDER1_SSI2DIV_OFFSET 8
-#define MXC_CRMAP_ACDER1_SSI2DIV_MASK (0x3F << 8)
-#define MXC_CRMAP_ACDER1_SSI1EN_OFFSET 6
-#define MXC_CRMAP_ACDER1_SSI1DIV_OFFSET 0
-#define MXC_CRMAP_ACDER1_SSI1DIV_MASK 0x3F
-
-#define MXC_CRMAP_ACDER2_CRCT_CLK_DIV_OFFSET 24
-#define MXC_CRMAP_ACDER2_CRCT_CLK_DIV_MASK (0x7 << 24)
-#define MXC_CRMAP_ACDER2_NFCEN_OFFSET 20
-#define MXC_CRMAP_ACDER2_NFCDIV_OFFSET 16
-#define MXC_CRMAP_ACDER2_NFCDIV_MASK (0xF << 16)
-#define MXC_CRMAP_ACDER2_USBEN_OFFSET 12
-#define MXC_CRMAP_ACDER2_USBDIV_OFFSET 8
-#define MXC_CRMAP_ACDER2_USBDIV_MASK (0xF << 8)
-#define MXC_CRMAP_ACDER2_BAUD_ISEL_OFFSET 5
-#define MXC_CRMAP_ACDER2_BAUD_ISEL_MASK (0x3 << 5)
-#define MXC_CRMAP_ACDER2_BAUDDIV_OFFSET 0
-#define MXC_CRMAP_ACDER2_BAUDDIV_MASK 0xF
-
-#define MXC_CRMAP_AMLPMRA_MLPMA7_OFFSET 22
-#define MXC_CRMAP_AMLPMRA_MLPMA7_MASK (0x7 << 22)
-#define MXC_CRMAP_AMLPMRA_MLPMA6_OFFSET 19
-#define MXC_CRMAP_AMLPMRA_MLPMA6_MASK (0x7 << 19)
-#define MXC_CRMAP_AMLPMRA_MLPMA4_OFFSET 12
-#define MXC_CRMAP_AMLPMRA_MLPMA4_MASK (0x7 << 12)
-#define MXC_CRMAP_AMLPMRA_MLPMA3_OFFSET 9
-#define MXC_CRMAP_AMLPMRA_MLPMA3_MASK (0x7 << 9)
-#define MXC_CRMAP_AMLPMRA_MLPMA2_OFFSET 6
-#define MXC_CRMAP_AMLPMRA_MLPMA2_MASK (0x7 << 6)
-#define MXC_CRMAP_AMLPMRA_MLPMA1_OFFSET 3
-#define MXC_CRMAP_AMLPMRA_MLPMA1_MASK (0x7 << 3)
-
-#define MXC_CRMAP_AMLPMRB_MLPMB0_OFFSET 0
-#define MXC_CRMAP_AMLPMRB_MLPMB0_MASK 0x7
-
-#define MXC_CRMAP_AMLPMRC_MLPMC9_OFFSET 28
-#define MXC_CRMAP_AMLPMRC_MLPMC9_MASK (0x7 << 28)
-#define MXC_CRMAP_AMLPMRC_MLPMC7_OFFSET 22
-#define MXC_CRMAP_AMLPMRC_MLPMC7_MASK (0x7 << 22)
-#define MXC_CRMAP_AMLPMRC_MLPMC5_OFFSET 16
-#define MXC_CRMAP_AMLPMRC_MLPMC5_MASK (0x7 << 16)
-#define MXC_CRMAP_AMLPMRC_MLPMC4_OFFSET 12
-#define MXC_CRMAP_AMLPMRC_MLPMC4_MASK (0x7 << 12)
-#define MXC_CRMAP_AMLPMRC_MLPMC3_OFFSET 9
-#define MXC_CRMAP_AMLPMRC_MLPMC3_MASK (0x7 << 9)
-#define MXC_CRMAP_AMLPMRC_MLPMC2_OFFSET 6
-#define MXC_CRMAP_AMLPMRC_MLPMC2_MASK (0x7 << 6)
-#define MXC_CRMAP_AMLPMRC_MLPMC1_OFFSET 3
-#define MXC_CRMAP_AMLPMRC_MLPMC1_MASK (0x7 << 3)
-#define MXC_CRMAP_AMLPMRC_MLPMC0_OFFSET 0
-#define MXC_CRMAP_AMLPMRC_MLPMC0_MASK 0x7
-
-#define MXC_CRMAP_AMLPMRD_MLPMD7_OFFSET 22
-#define MXC_CRMAP_AMLPMRD_MLPMD7_MASK (0x7 << 22)
-#define MXC_CRMAP_AMLPMRD_MLPMD4_OFFSET 12
-#define MXC_CRMAP_AMLPMRD_MLPMD4_MASK (0x7 << 12)
-#define MXC_CRMAP_AMLPMRD_MLPMD3_OFFSET 9
-#define MXC_CRMAP_AMLPMRD_MLPMD3_MASK (0x7 << 9)
-#define MXC_CRMAP_AMLPMRD_MLPMD2_OFFSET 6
-#define MXC_CRMAP_AMLPMRD_MLPMD2_MASK (0x7 << 6)
-#define MXC_CRMAP_AMLPMRD_MLPMD0_OFFSET 0
-#define MXC_CRMAP_AMLPMRD_MLPMD0_MASK 0x7
-
-#define MXC_CRMAP_AMLPMRE1_MLPME9_OFFSET 28
-#define MXC_CRMAP_AMLPMRE1_MLPME9_MASK (0x7 << 28)
-#define MXC_CRMAP_AMLPMRE1_MLPME8_OFFSET 25
-#define MXC_CRMAP_AMLPMRE1_MLPME8_MASK (0x7 << 25)
-#define MXC_CRMAP_AMLPMRE1_MLPME7_OFFSET 22
-#define MXC_CRMAP_AMLPMRE1_MLPME7_MASK (0x7 << 22)
-#define MXC_CRMAP_AMLPMRE1_MLPME6_OFFSET 19
-#define MXC_CRMAP_AMLPMRE1_MLPME6_MASK (0x7 << 19)
-#define MXC_CRMAP_AMLPMRE1_MLPME5_OFFSET 16
-#define MXC_CRMAP_AMLPMRE1_MLPME5_MASK (0x7 << 16)
-#define MXC_CRMAP_AMLPMRE1_MLPME4_OFFSET 12
-#define MXC_CRMAP_AMLPMRE1_MLPME4_MASK (0x7 << 12)
-#define MXC_CRMAP_AMLPMRE1_MLPME3_OFFSET 9
-#define MXC_CRMAP_AMLPMRE1_MLPME3_MASK (0x7 << 9)
-#define MXC_CRMAP_AMLPMRE1_MLPME2_OFFSET 6
-#define MXC_CRMAP_AMLPMRE1_MLPME2_MASK (0x7 << 6)
-#define MXC_CRMAP_AMLPMRE1_MLPME1_OFFSET 3
-#define MXC_CRMAP_AMLPMRE1_MLPME1_MASK (0x7 << 3)
-#define MXC_CRMAP_AMLPMRE1_MLPME0_OFFSET 0
-#define MXC_CRMAP_AMLPMRE1_MLPME0_MASK 0x7
-
-#define MXC_CRMAP_AMLPMRE2_MLPME0_OFFSET 0
-#define MXC_CRMAP_AMLPMRE2_MLPME0_MASK 0x7
-
-#define MXC_CRMAP_AMLPMRF_MLPMF6_OFFSET 19
-#define MXC_CRMAP_AMLPMRF_MLPMF6_MASK (0x7 << 19)
-#define MXC_CRMAP_AMLPMRF_MLPMF5_OFFSET 16
-#define MXC_CRMAP_AMLPMRF_MLPMF5_MASK (0x7 << 16)
-#define MXC_CRMAP_AMLPMRF_MLPMF3_OFFSET 9
-#define MXC_CRMAP_AMLPMRF_MLPMF3_MASK (0x7 << 9)
-#define MXC_CRMAP_AMLPMRF_MLPMF2_OFFSET 6
-#define MXC_CRMAP_AMLPMRF_MLPMF2_MASK (0x7 << 6)
-#define MXC_CRMAP_AMLPMRF_MLPMF1_OFFSET 3
-#define MXC_CRMAP_AMLPMRF_MLPMF1_MASK (0x7 << 3)
-#define MXC_CRMAP_AMLPMRF_MLPMF0_OFFSET 0
-#define MXC_CRMAP_AMLPMRF_MLPMF0_MASK (0x7 << 0)
-
-#define MXC_CRMAP_AMLPMRG_MLPMG9_OFFSET 28
-#define MXC_CRMAP_AMLPMRG_MLPMG9_MASK (0x7 << 28)
-#define MXC_CRMAP_AMLPMRG_MLPMG7_OFFSET 22
-#define MXC_CRMAP_AMLPMRG_MLPMG7_MASK (0x7 << 22)
-#define MXC_CRMAP_AMLPMRG_MLPMG6_OFFSET 19
-#define MXC_CRMAP_AMLPMRG_MLPMG6_MASK (0x7 << 19)
-#define MXC_CRMAP_AMLPMRG_MLPMG5_OFFSET 16
-#define MXC_CRMAP_AMLPMRG_MLPMG5_MASK (0x7 << 16)
-#define MXC_CRMAP_AMLPMRG_MLPMG4_OFFSET 12
-#define MXC_CRMAP_AMLPMRG_MLPMG4_MASK (0x7 << 12)
-#define MXC_CRMAP_AMLPMRG_MLPMG3_OFFSET 9
-#define MXC_CRMAP_AMLPMRG_MLPMG3_MASK (0x7 << 9)
-#define MXC_CRMAP_AMLPMRG_MLPMG2_OFFSET 6
-#define MXC_CRMAP_AMLPMRG_MLPMG2_MASK (0x7 << 6)
-#define MXC_CRMAP_AMLPMRG_MLPMG1_OFFSET 3
-#define MXC_CRMAP_AMLPMRG_MLPMG1_MASK (0x7 << 3)
-#define MXC_CRMAP_AMLPMRG_MLPMG0_OFFSET 0
-#define MXC_CRMAP_AMLPMRG_MLPMG0_MASK 0x7
-
-#define MXC_CRMAP_AGPR_IPUPAD_OFFSET 20
-#define MXC_CRMAP_AGPR_IPUPAD_MASK (0x7 << 20)
-
-#define MXC_CRMAP_APRA_EL1TEN_OFFSET 29
-#define MXC_CRMAP_APRA_SIMEN_OFFSET 24
-#define MXC_CRMAP_APRA_UART3DIV_OFFSET 17
-#define MXC_CRMAP_APRA_UART3DIV_MASK (0xF << 17)
-#define MXC_CRMAP_APRA_UART3EN_OFFSET 16
-#define MXC_CRMAP_APRA_SAHARA_DIV2_CLKEN_OFFSET 14
-#define MXC_CRMAP_APRA_MQSPIEN_OFFSET 13
-#define MXC_CRMAP_APRA_UART2EN_OFFSET 8
-#define MXC_CRMAP_APRA_UART1EN_OFFSET 0
-
-#define MXC_CRMAP_APRB_SDHC2_ISEL_OFFSET 13
-#define MXC_CRMAP_APRB_SDHC2_ISEL_MASK (0x7 << 13)
-#define MXC_CRMAP_APRB_SDHC2_DIV_OFFSET 9
-#define MXC_CRMAP_APRB_SDHC2_DIV_MASK (0xF << 9)
-#define MXC_CRMAP_APRB_SDHC2EN_OFFSET 8
-#define MXC_CRMAP_APRB_SDHC1_ISEL_OFFSET 5
-#define MXC_CRMAP_APRB_SDHC1_ISEL_MASK (0x7 << 5)
-#define MXC_CRMAP_APRB_SDHC1_DIV_OFFSET 1
-#define MXC_CRMAP_APRB_SDHC1_DIV_MASK (0xF << 1)
-#define MXC_CRMAP_APRB_SDHC1EN_OFFSET 0
-
-#define MXC_CRMAP_ACSR_ADS_OFFSET 8
-#define MXC_CRMAP_ACSR_ADS (0x1 << 8)
-#define MXC_CRMAP_ACSR_ACS 0x1
-
-#define MXC_CRMAP_ADCR_LFDF_0 (0x0 << 8)
-#define MXC_CRMAP_ADCR_LFDF_2 (0x1 << 8)
-#define MXC_CRMAP_ADCR_LFDF_4 (0x2 << 8)
-#define MXC_CRMAP_ADCR_LFDF_8 (0x3 << 8)
-#define MXC_CRMAP_ADCR_LFDF_OFFSET 8
-#define MXC_CRMAP_ADCR_LFDF_MASK (0x3 << 8)
-#define MXC_CRMAP_ADCR_ALT_PLL 0x80
-#define MXC_CRMAP_ADCR_DFS_DIVEN 0x20
-#define MXC_CRMAP_ADCR_DIV_BYP 0x2
-#define MXC_CRMAP_ADCR_VSTAT 0x8
-#define MXC_CRMAP_ADCR_TSTAT 0x10
-#define MXC_CRMAP_ADCR_DVFS_VCTRL 0x10
-#define MXC_CRMAP_ADCR_CLK_ON 0x40
-
-#define MXC_CRMAP_ADFMR_FC_OFFSET 16
-#define MXC_CRMAP_ADFMR_FC_MASK (0x1F << 16)
-#define MXC_CRMAP_ADFMR_MF_OFFSET 1
-#define MXC_CRMAP_ADFMR_MF_MASK (0x3FF << 1)
-#define MXC_CRMAP_ADFMR_DFM_CLK_READY 0x1
-#define MXC_CRMAP_ADFMR_DFM_PWR_DOWN 0x8000
-
-#define MXC_CRMAP_ACR_CKOHS_HIGH (1 << 18)
-#define MXC_CRMAP_ACR_CKOS_HIGH (1 << 16)
-#define MXC_CRMAP_ACR_CKOHS_MASK (0x7 << 12)
-#define MXC_CRMAP_ACR_CKOHD (1 << 11)
-#define MXC_CRMAP_ACR_CKOHDIV_MASK (0xF << 8)
-#define MXC_CRMAP_ACR_CKOHDIV_OFFSET 8
-#define MXC_CRMAP_ACR_CKOD (1 << 7)
-#define MXC_CRMAP_ACR_CKOS_MASK (0x7 << 4)
-
-/* AP Warm reset */
-#define MXC_CRMAP_AMCR_SW_AP (1 << 14)
-
-/* Bit definitions of ACGCR in CRM_AP for tree level clock gating */
-#define MXC_CRMAP_ACGCR_ACG0_STOP_WAIT 0x00000001
-#define MXC_CRMAP_ACGCR_ACG0_STOP 0x00000003
-#define MXC_CRMAP_ACGCR_ACG0_RUN 0x00000007
-#define MXC_CRMAP_ACGCR_ACG0_DISABLED 0x00000000
-
-#define MXC_CRMAP_ACGCR_ACG1_STOP_WAIT 0x00000008
-#define MXC_CRMAP_ACGCR_ACG1_STOP 0x00000018
-#define MXC_CRMAP_ACGCR_ACG1_RUN 0x00000038
-#define MXC_CRMAP_ACGCR_ACG1_DISABLED 0x00000000
-
-#define MXC_CRMAP_ACGCR_ACG2_STOP_WAIT 0x00000040
-#define MXC_CRMAP_ACGCR_ACG2_STOP 0x000000C0
-#define MXC_CRMAP_ACGCR_ACG2_RUN 0x000001C0
-#define MXC_CRMAP_ACGCR_ACG2_DISABLED 0x00000000
-
-#define MXC_CRMAP_ACGCR_ACG3_STOP_WAIT 0x00000200
-#define MXC_CRMAP_ACGCR_ACG3_STOP 0x00000600
-#define MXC_CRMAP_ACGCR_ACG3_RUN 0x00000E00
-#define MXC_CRMAP_ACGCR_ACG3_DISABLED 0x00000000
-
-#define MXC_CRMAP_ACGCR_ACG4_STOP_WAIT 0x00001000
-#define MXC_CRMAP_ACGCR_ACG4_STOP 0x00003000
-#define MXC_CRMAP_ACGCR_ACG4_RUN 0x00007000
-#define MXC_CRMAP_ACGCR_ACG4_DISABLED 0x00000000
-
-#define MXC_CRMAP_ACGCR_ACG5_STOP_WAIT 0x00010000
-#define MXC_CRMAP_ACGCR_ACG5_STOP 0x00030000
-#define MXC_CRMAP_ACGCR_ACG5_RUN 0x00070000
-#define MXC_CRMAP_ACGCR_ACG5_DISABLED 0x00000000
-
-#define MXC_CRMAP_ACGCR_ACG6_STOP_WAIT 0x00080000
-#define MXC_CRMAP_ACGCR_ACG6_STOP 0x00180000
-#define MXC_CRMAP_ACGCR_ACG6_RUN 0x00380000
-#define MXC_CRMAP_ACGCR_ACG6_DISABLED 0x00000000
-
-#define NUM_GATE_CTRL 6
-
-/* CRM COM Register Offsets */
-#define MXC_CRMCOM_CSCR (MXC_CRM_COM_BASE + 0x0C)
-#define MXC_CRMCOM_CCCR (MXC_CRM_COM_BASE + 0x10)
-
-/* CRM COM Bit Definitions */
-#define MXC_CRMCOM_CSCR_PPD1 0x08000000
-#define MXC_CRMCOM_CSCR_CKOHSEL (1 << 18)
-#define MXC_CRMCOM_CSCR_CKOSEL (1 << 17)
-#define MXC_CRMCOM_CCCR_CC_DIV_OFFSET 8
-#define MXC_CRMCOM_CCCR_CC_DIV_MASK (0x1F << 8)
-#define MXC_CRMCOM_CCCR_CC_SEL_OFFSET 0
-#define MXC_CRMCOM_CCCR_CC_SEL_MASK 0x3
-
-/* DSM Register Offsets */
-#define MXC_DSM_SLEEP_TIME (MXC_DSM_BASE + 0x0c)
-#define MXC_DSM_CONTROL0 (MXC_DSM_BASE + 0x20)
-#define MXC_DSM_CONTROL1 (MXC_DSM_BASE + 0x24)
-#define MXC_DSM_CTREN (MXC_DSM_BASE + 0x28)
-#define MXC_DSM_WARM_PER (MXC_DSM_BASE + 0x40)
-#define MXC_DSM_LOCK_PER (MXC_DSM_BASE + 0x44)
-#define MXC_DSM_MGPER (MXC_DSM_BASE + 0x4c)
-#define MXC_DSM_CRM_CONTROL (MXC_DSM_BASE + 0x50)
-
-/* Bit definitions of various registers in DSM */
-#define MXC_DSM_CRM_CTRL_DVFS_BYP 0x00000008
-#define MXC_DSM_CRM_CTRL_DVFS_VCTRL 0x00000004
-#define MXC_DSM_CRM_CTRL_LPMD1 0x00000002
-#define MXC_DSM_CRM_CTRL_LPMD0 0x00000001
-#define MXC_DSM_CRM_CTRL_LPMD_STOP_MODE 0x00000000
-#define MXC_DSM_CRM_CTRL_LPMD_WAIT_MODE 0x00000001
-#define MXC_DSM_CRM_CTRL_LPMD_RUN_MODE 0x00000003
-#define MXC_DSM_CONTROL0_STBY_COMMIT_EN 0x00000200
-#define MXC_DSM_CONTROL0_MSTR_EN 0x00000001
-#define MXC_DSM_CONTROL0_RESTART 0x00000010
-/* Counter Block reset */
-#define MXC_DSM_CONTROL1_CB_RST 0x00000002
-/* State Machine reset */
-#define MXC_DSM_CONTROL1_SM_RST 0x00000004
-/* Bit needed to reset counter block */
-#define MXC_CONTROL1_RST_CNT32 0x00000008
-#define MXC_DSM_CONTROL1_RST_CNT32_EN 0x00000800
-#define MXC_DSM_CONTROL1_SLEEP 0x00000100
-#define MXC_DSM_CONTROL1_WAKEUP_DISABLE 0x00004000
-#define MXC_DSM_CTREN_CNT32 0x00000001
-
-/* Magic Fix enable bit */
-#define MXC_DSM_MGPER_EN_MGFX 0x80000000
-#define MXC_DSM_MGPER_PER_MASK 0x000003FF
-#define MXC_DSM_MGPER_PER(n) (MXC_DSM_MGPER_PER_MASK & n)
-
-/* Address offsets of the CLKCTL registers */
-#define MXC_CLKCTL_GP_CTRL (MXC_CLKCTL_BASE + 0x00)
-#define MXC_CLKCTL_GP_SER (MXC_CLKCTL_BASE + 0x04)
-#define MXC_CLKCTL_GP_CER (MXC_CLKCTL_BASE + 0x08)
-
-#endif /* _ARCH_ARM_MACH_MXC91231_CRM_REGS_H_ */
diff --git a/arch/arm/mach-mxc91231/devices.c b/arch/arm/mach-mxc91231/devices.c
deleted file mode 100644
index 027af4f..0000000
--- a/arch/arm/mach-mxc91231/devices.c
+++ /dev/null
@@ -1,251 +0,0 @@
-/*
- * Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor,
- * Boston, MA 02110-1301, USA.
- */
-
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/serial.h>
-#include <linux/gpio.h>
-#include <mach/hardware.h>
-#include <mach/irqs.h>
-#include <mach/imx-uart.h>
-
-static struct resource uart0[] = {
- {
- .start = MXC91231_UART1_BASE_ADDR,
- .end = MXC91231_UART1_BASE_ADDR + 0x0B5,
- .flags = IORESOURCE_MEM,
- }, {
- .start = MXC91231_INT_UART1_RX,
- .end = MXC91231_INT_UART1_RX,
- .flags = IORESOURCE_IRQ,
- }, {
- .start = MXC91231_INT_UART1_TX,
- .end = MXC91231_INT_UART1_TX,
- .flags = IORESOURCE_IRQ,
- }, {
- .start = MXC91231_INT_UART1_MINT,
- .end = MXC91231_INT_UART1_MINT,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-struct platform_device mxc_uart_device0 = {
- .name = "imx-uart",
- .id = 0,
- .resource = uart0,
- .num_resources = ARRAY_SIZE(uart0),
-};
-
-static struct resource uart1[] = {
- {
- .start = MXC91231_UART2_BASE_ADDR,
- .end = MXC91231_UART2_BASE_ADDR + 0x0B5,
- .flags = IORESOURCE_MEM,
- }, {
- .start = MXC91231_INT_UART2_RX,
- .end = MXC91231_INT_UART2_RX,
- .flags = IORESOURCE_IRQ,
- }, {
- .start = MXC91231_INT_UART2_TX,
- .end = MXC91231_INT_UART2_TX,
- .flags = IORESOURCE_IRQ,
- }, {
- .start = MXC91231_INT_UART2_MINT,
- .end = MXC91231_INT_UART2_MINT,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-struct platform_device mxc_uart_device1 = {
- .name = "imx-uart",
- .id = 1,
- .resource = uart1,
- .num_resources = ARRAY_SIZE(uart1),
-};
-
-static struct resource uart2[] = {
- {
- .start = MXC91231_UART3_BASE_ADDR,
- .end = MXC91231_UART3_BASE_ADDR + 0x0B5,
- .flags = IORESOURCE_MEM,
- }, {
- .start = MXC91231_INT_UART3_RX,
- .end = MXC91231_INT_UART3_RX,
- .flags = IORESOURCE_IRQ,
- }, {
- .start = MXC91231_INT_UART3_TX,
- .end = MXC91231_INT_UART3_TX,
- .flags = IORESOURCE_IRQ,
- }, {
- .start = MXC91231_INT_UART3_MINT,
- .end = MXC91231_INT_UART3_MINT,
- .flags = IORESOURCE_IRQ,
-
- },
-};
-
-struct platform_device mxc_uart_device2 = {
- .name = "imx-uart",
- .id = 2,
- .resource = uart2,
- .num_resources = ARRAY_SIZE(uart2),
-};
-
-/* GPIO port description */
-static struct mxc_gpio_port mxc_gpio_ports[] = {
- [0] = {
- .chip.label = "gpio-0",
- .base = MXC91231_IO_ADDRESS(MXC91231_GPIO1_AP_BASE_ADDR),
- .irq = MXC91231_INT_GPIO1,
- .virtual_irq_start = MXC_GPIO_IRQ_START,
- },
- [1] = {
- .chip.label = "gpio-1",
- .base = MXC91231_IO_ADDRESS(MXC91231_GPIO2_AP_BASE_ADDR),
- .irq = MXC91231_INT_GPIO2,
- .virtual_irq_start = MXC_GPIO_IRQ_START + 32,
- },
- [2] = {
- .chip.label = "gpio-2",
- .base = MXC91231_IO_ADDRESS(MXC91231_GPIO3_AP_BASE_ADDR),
- .irq = MXC91231_INT_GPIO3,
- .virtual_irq_start = MXC_GPIO_IRQ_START + 64,
- },
- [3] = {
- .chip.label = "gpio-3",
- .base = MXC91231_IO_ADDRESS(MXC91231_GPIO4_SH_BASE_ADDR),
- .irq = MXC91231_INT_GPIO4,
- .virtual_irq_start = MXC_GPIO_IRQ_START + 96,
- },
-};
-
-int __init mxc91231_register_gpios(void)
-{
- return mxc_gpio_init(mxc_gpio_ports, ARRAY_SIZE(mxc_gpio_ports));
-}
-
-static struct resource mxc_nand_resources[] = {
- {
- .start = MXC91231_NFC_BASE_ADDR,
- .end = MXC91231_NFC_BASE_ADDR + 0xfff,
- .flags = IORESOURCE_MEM
- }, {
- .start = MXC91231_INT_NANDFC,
- .end = MXC91231_INT_NANDFC,
- .flags = IORESOURCE_IRQ
- },
-};
-
-struct platform_device mxc_nand_device = {
- .name = "mxc_nand",
- .id = 0,
- .num_resources = ARRAY_SIZE(mxc_nand_resources),
- .resource = mxc_nand_resources,
-};
-
-static struct resource mxc_sdhc0_resources[] = {
- {
- .start = MXC91231_MMC_SDHC1_BASE_ADDR,
- .end = MXC91231_MMC_SDHC1_BASE_ADDR + SZ_16K - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = MXC91231_INT_MMC_SDHC1,
- .end = MXC91231_INT_MMC_SDHC1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct resource mxc_sdhc1_resources[] = {
- {
- .start = MXC91231_MMC_SDHC2_BASE_ADDR,
- .end = MXC91231_MMC_SDHC2_BASE_ADDR + SZ_16K - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = MXC91231_INT_MMC_SDHC2,
- .end = MXC91231_INT_MMC_SDHC2,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-struct platform_device mxc_sdhc_device0 = {
- .name = "mxc-mmc",
- .id = 0,
- .num_resources = ARRAY_SIZE(mxc_sdhc0_resources),
- .resource = mxc_sdhc0_resources,
-};
-
-struct platform_device mxc_sdhc_device1 = {
- .name = "mxc-mmc",
- .id = 1,
- .num_resources = ARRAY_SIZE(mxc_sdhc1_resources),
- .resource = mxc_sdhc1_resources,
-};
-
-static struct resource mxc_cspi0_resources[] = {
- {
- .start = MXC91231_CSPI1_BASE_ADDR,
- .end = MXC91231_CSPI1_BASE_ADDR + 0x20,
- .flags = IORESOURCE_MEM,
- }, {
- .start = MXC91231_INT_CSPI1,
- .end = MXC91231_INT_CSPI1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-struct platform_device mxc_cspi_device0 = {
- .name = "spi_imx",
- .id = 0,
- .num_resources = ARRAY_SIZE(mxc_cspi0_resources),
- .resource = mxc_cspi0_resources,
-};
-
-static struct resource mxc_cspi1_resources[] = {
- {
- .start = MXC91231_CSPI2_BASE_ADDR,
- .end = MXC91231_CSPI2_BASE_ADDR + 0x20,
- .flags = IORESOURCE_MEM,
- }, {
- .start = MXC91231_INT_CSPI2,
- .end = MXC91231_INT_CSPI2,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-struct platform_device mxc_cspi_device1 = {
- .name = "spi_imx",
- .id = 1,
- .num_resources = ARRAY_SIZE(mxc_cspi1_resources),
- .resource = mxc_cspi1_resources,
-};
-
-static struct resource mxc_wdog0_resources[] = {
- {
- .start = MXC91231_WDOG1_BASE_ADDR,
- .end = MXC91231_WDOG1_BASE_ADDR + 0x10,
- .flags = IORESOURCE_MEM,
- },
-};
-
-struct platform_device mxc_wdog_device0 = {
- .name = "mxc-wdt",
- .id = 0,
- .num_resources = ARRAY_SIZE(mxc_wdog0_resources),
- .resource = mxc_wdog0_resources,
-};
diff --git a/arch/arm/mach-mxc91231/devices.h b/arch/arm/mach-mxc91231/devices.h
deleted file mode 100644
index 72a2136..0000000
--- a/arch/arm/mach-mxc91231/devices.h
+++ /dev/null
@@ -1,13 +0,0 @@
-extern struct platform_device mxc_uart_device0;
-extern struct platform_device mxc_uart_device1;
-extern struct platform_device mxc_uart_device2;
-
-extern struct platform_device mxc_nand_device;
-
-extern struct platform_device mxc_sdhc_device0;
-extern struct platform_device mxc_sdhc_device1;
-
-extern struct platform_device mxc_cspi_device0;
-extern struct platform_device mxc_cspi_device1;
-
-extern struct platform_device mxc_wdog_device0;
diff --git a/arch/arm/mach-mxc91231/iomux.c b/arch/arm/mach-mxc91231/iomux.c
deleted file mode 100644
index 66fc41c..0000000
--- a/arch/arm/mach-mxc91231/iomux.c
+++ /dev/null
@@ -1,177 +0,0 @@
-/*
- * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
- * Copyright (C) 2009 by Valentin Longchamp <valentin.longchamp@epfl.ch>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA 02110-1301, USA.
- */
-
-#include <linux/module.h>
-#include <linux/spinlock.h>
-#include <linux/io.h>
-#include <linux/kernel.h>
-#include <mach/hardware.h>
-#include <mach/gpio.h>
-#include <mach/iomux-mxc91231.h>
-
-/*
- * IOMUX register (base) addresses
- */
-#define IOMUX_AP_BASE MXC91231_IO_ADDRESS(MXC91231_IOMUX_AP_BASE_ADDR)
-#define IOMUX_COM_BASE MXC91231_IO_ADDRESS(MXC91231_IOMUX_COM_BASE_ADDR)
-#define IOMUXSW_AP_MUX_CTL (IOMUX_AP_BASE + 0x000)
-#define IOMUXSW_SP_MUX_CTL (IOMUX_COM_BASE + 0x000)
-#define IOMUXSW_PAD_CTL (IOMUX_COM_BASE + 0x200)
-
-#define IOMUXINT_OBS1 (IOMUX_AP_BASE + 0x600)
-#define IOMUXINT_OBS2 (IOMUX_AP_BASE + 0x004)
-
-static DEFINE_SPINLOCK(gpio_mux_lock);
-
-#define NB_PORTS ((PIN_MAX + 32) / 32)
-#define PIN_GLOBAL_NUM(pin) \
- (((pin & MUX_SIDE_MASK) >> MUX_SIDE_SHIFT)*PIN_AP_MAX + \
- ((pin & MUX_REG_MASK) >> MUX_REG_SHIFT)*4 + \
- ((pin & MUX_FIELD_MASK) >> MUX_FIELD_SHIFT))
-
-unsigned long mxc_pin_alloc_map[NB_PORTS * 32 / BITS_PER_LONG];
-/*
- * set the mode for a IOMUX pin.
- */
-int mxc_iomux_mode(unsigned int pin_mode)
-{
- u32 side, field, l, mode, ret = 0;
- void __iomem *reg;
-
- side = (pin_mode & MUX_SIDE_MASK) >> MUX_SIDE_SHIFT;
- switch (side) {
- case MUX_SIDE_AP:
- reg = IOMUXSW_AP_MUX_CTL;
- break;
- case MUX_SIDE_SP:
- reg = IOMUXSW_SP_MUX_CTL;
- break;
- default:
- return -EINVAL;
- }
- reg += ((pin_mode & MUX_REG_MASK) >> MUX_REG_SHIFT) * 4;
- field = (pin_mode & MUX_FIELD_MASK) >> MUX_FIELD_SHIFT;
- mode = (pin_mode & MUX_MODE_MASK) >> MUX_MODE_SHIFT;
-
- spin_lock(&gpio_mux_lock);
-
- l = __raw_readl(reg);
- l &= ~(0xff << (field * 8));
- l |= mode << (field * 8);
- __raw_writel(l, reg);
-
- spin_unlock(&gpio_mux_lock);
-
- return ret;
-}
-EXPORT_SYMBOL(mxc_iomux_mode);
-
-/*
- * This function configures the pad value for a IOMUX pin.
- */
-void mxc_iomux_set_pad(enum iomux_pins pin, u32 config)
-{
- u32 padgrp, field, l;
- void __iomem *reg;
-
- padgrp = (pin & MUX_PADGRP_MASK) >> MUX_PADGRP_SHIFT;
- reg = IOMUXSW_PAD_CTL + (pin + 2) / 3 * 4;
- field = (pin + 2) % 3;
-
- pr_debug("%s: reg offset = 0x%x, field = %d\n",
- __func__, (pin + 2) / 3, field);
-
- spin_lock(&gpio_mux_lock);
-
- l = __raw_readl(reg);
- l &= ~(0x1ff << (field * 10));
- l |= config << (field * 10);
- __raw_writel(l, reg);
-
- spin_unlock(&gpio_mux_lock);
-}
-EXPORT_SYMBOL(mxc_iomux_set_pad);
-
-/*
- * allocs a single pin:
- * - reserves the pin so that it is not claimed by another driver
- * - setups the iomux according to the configuration
- */
-int mxc_iomux_alloc_pin(unsigned int pin_mode, const char *label)
-{
- unsigned pad = PIN_GLOBAL_NUM(pin_mode);
- if (pad >= (PIN_MAX + 1)) {
- printk(KERN_ERR "mxc_iomux: Attempt to request nonexistant pin %u for \"%s\"\n",
- pad, label ? label : "?");
- return -EINVAL;
- }
-
- if (test_and_set_bit(pad, mxc_pin_alloc_map)) {
- printk(KERN_ERR "mxc_iomux: pin %u already used. Allocation for \"%s\" failed\n",
- pad, label ? label : "?");
- return -EBUSY;
- }
- mxc_iomux_mode(pin_mode);
-
- return 0;
-}
-EXPORT_SYMBOL(mxc_iomux_alloc_pin);
-
-int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count,
- const char *label)
-{
- const unsigned int *p = pin_list;
- int i;
- int ret = -EINVAL;
-
- for (i = 0; i < count; i++) {
- ret = mxc_iomux_alloc_pin(*p, label);
- if (ret)
- goto setup_error;
- p++;
- }
- return 0;
-
-setup_error:
- mxc_iomux_release_multiple_pins(pin_list, i);
- return ret;
-}
-EXPORT_SYMBOL(mxc_iomux_setup_multiple_pins);
-
-void mxc_iomux_release_pin(unsigned int pin_mode)
-{
- unsigned pad = PIN_GLOBAL_NUM(pin_mode);
-
- if (pad < (PIN_MAX + 1))
- clear_bit(pad, mxc_pin_alloc_map);
-}
-EXPORT_SYMBOL(mxc_iomux_release_pin);
-
-void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count)
-{
- const unsigned int *p = pin_list;
- int i;
-
- for (i = 0; i < count; i++) {
- mxc_iomux_release_pin(*p);
- p++;
- }
-}
-EXPORT_SYMBOL(mxc_iomux_release_multiple_pins);
diff --git a/arch/arm/mach-mxc91231/magx-zn5.c b/arch/arm/mach-mxc91231/magx-zn5.c
deleted file mode 100644
index f31a45e..0000000
--- a/arch/arm/mach-mxc91231/magx-zn5.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * Copyright 2009 Dmitriy Taychenachev <dimichxp@gmail.com>
- *
- * This file is released under the GPLv2 or later.
- */
-
-#include <linux/irq.h>
-#include <linux/init.h>
-#include <linux/device.h>
-
-#include <asm/mach-types.h>
-#include <asm/mach/time.h>
-#include <asm/mach/arch.h>
-
-#include <mach/common.h>
-#include <mach/hardware.h>
-#include <mach/iomux-mxc91231.h>
-#include <mach/mmc.h>
-#include <mach/imx-uart.h>
-
-#include "devices.h"
-
-static struct imxuart_platform_data uart_pdata = {
-};
-
-static struct imxmmc_platform_data sdhc_pdata = {
-};
-
-static void __init zn5_init(void)
-{
- pm_power_off = mxc91231_power_off;
-
- mxc_iomux_alloc_pin(MXC91231_PIN_SP_USB_DAT_VP__RXD2, "uart2-rx");
- mxc_iomux_alloc_pin(MXC91231_PIN_SP_USB_SE0_VM__TXD2, "uart2-tx");
-
- mxc_register_device(&mxc_uart_device1, &uart_pdata);
- mxc_register_device(&mxc_uart_device0, &uart_pdata);
-
- mxc_register_device(&mxc_sdhc_device0, &sdhc_pdata);
-
- mxc_register_device(&mxc_wdog_device0, NULL);
-
- return;
-}
-
-static void __init zn5_timer_init(void)
-{
- mxc91231_clocks_init(26000000); /* 26mhz ckih */
-}
-
-struct sys_timer zn5_timer = {
- .init = zn5_timer_init,
-};
-
-MACHINE_START(MAGX_ZN5, "Motorola Zn5")
- .boot_params = MXC91231_PHYS_OFFSET + 0x100,
- .map_io = mxc91231_map_io,
- .init_early = mxc91231_init_early,
- .init_irq = mxc91231_init_irq,
- .timer = &zn5_timer,
- .init_machine = zn5_init,
-MACHINE_END
diff --git a/arch/arm/mach-mxc91231/mm.c b/arch/arm/mach-mxc91231/mm.c
deleted file mode 100644
index a77f6da..0000000
--- a/arch/arm/mach-mxc91231/mm.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * Copyright (C) 1999,2000 Arm Limited
- * Copyright (C) 2000 Deep Blue Solutions Ltd
- * Copyright (C) 2002 Shane Nay (shane@minirl.com)
- * Copyright 2004-2005 Freescale Semiconductor, Inc. All Rights Reserved.
- * - add MXC specific definitions
- * Copyright 2006 Motorola, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include <linux/mm.h>
-#include <linux/init.h>
-#include <mach/hardware.h>
-#include <mach/common.h>
-#include <asm/pgtable.h>
-#include <asm/mach/map.h>
-
-/*
- * This structure defines the MXC memory map.
- */
-static struct map_desc mxc91231_io_desc[] __initdata = {
- imx_map_entry(MXC91231, L2CC, MT_DEVICE),
- imx_map_entry(MXC91231, X_MEMC, MT_DEVICE),
- imx_map_entry(MXC91231, ROMP, MT_DEVICE),
- imx_map_entry(MXC91231, AVIC, MT_DEVICE),
- imx_map_entry(MXC91231, AIPS1, MT_DEVICE),
- imx_map_entry(MXC91231, SPBA0, MT_DEVICE),
- imx_map_entry(MXC91231, SPBA1, MT_DEVICE),
- imx_map_entry(MXC91231, AIPS2, MT_DEVICE),
-};
-
-/*
- * This function initializes the memory map. It is called during the
- * system startup to create static physical to virtual memory map for
- * the IO modules.
- */
-void __init mxc91231_map_io(void)
-{
- iotable_init(mxc91231_io_desc, ARRAY_SIZE(mxc91231_io_desc));
-}
-
-void __init mxc91231_init_early(void)
-{
- mxc_set_cpu_type(MXC_CPU_MXC91231);
-}
-
-int mxc91231_register_gpios(void);
-
-void __init mxc91231_init_irq(void)
-{
- mxc91231_register_gpios();
- mxc_init_irq(MXC91231_IO_ADDRESS(MXC91231_AVIC_BASE_ADDR));
-}
diff --git a/arch/arm/mach-mxc91231/system.c b/arch/arm/mach-mxc91231/system.c
deleted file mode 100644
index 736f7ef..0000000
--- a/arch/arm/mach-mxc91231/system.c
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright 2009 Dmitriy Taychenachev <dimichxp@gmail.com>
- *
- * This file is released under the GPLv2 or later.
- */
-
-#include <linux/delay.h>
-#include <linux/io.h>
-
-#include <asm/proc-fns.h>
-#include <mach/hardware.h>
-
-#include "crm_regs.h"
-
-#define WDOG_WCR MXC91231_IO_ADDRESS(MXC91231_WDOG1_BASE_ADDR)
-#define WDOG_WCR_OUT_ENABLE (1 << 6)
-#define WDOG_WCR_ASSERT (1 << 5)
-
-void mxc91231_power_off(void)
-{
- u16 wcr;
-
- wcr = __raw_readw(WDOG_WCR);
- wcr |= WDOG_WCR_OUT_ENABLE;
- wcr &= ~WDOG_WCR_ASSERT;
- __raw_writew(wcr, WDOG_WCR);
-}
-
-void mxc91231_arch_reset(char mode, const char *cmd)
-{
- u32 amcr;
-
- /* Reset the AP using CRM */
- amcr = __raw_readl(MXC_CRMAP_AMCR);
- amcr &= ~MXC_CRMAP_AMCR_SW_AP;
- __raw_writel(amcr, MXC_CRMAP_AMCR);
-
- mdelay(10);
- cpu_reset(0);
-}
-
-void mxc91231_prepare_idle(void)
-{
- u32 crm_ctl;
-
- /* Go to WAIT mode after WFI */
- crm_ctl = __raw_readl(MXC_DSM_CRM_CONTROL);
- crm_ctl &= ~(MXC_DSM_CRM_CTRL_LPMD0 | MXC_DSM_CRM_CTRL_LPMD1);
- crm_ctl |= MXC_DSM_CRM_CTRL_LPMD_WAIT_MODE;
- __raw_writel(crm_ctl, MXC_DSM_CRM_CONTROL);
-}
diff --git a/arch/arm/mach-mxs/Kconfig b/arch/arm/mach-mxs/Kconfig
index 4522fbb..f114960 100644
--- a/arch/arm/mach-mxs/Kconfig
+++ b/arch/arm/mach-mxs/Kconfig
@@ -17,6 +17,16 @@
comment "MXS platforms:"
+config MACH_STMP378X_DEVB
+ bool "Support STMP378x_devb Platform"
+ select SOC_IMX23
+ select MXS_HAVE_AMBA_DUART
+ select MXS_HAVE_PLATFORM_AUART
+ select MXS_HAVE_PLATFORM_MXS_MMC
+ help
+ Include support for STMP378x-devb platform. This includes specific
+ configurations for the board and its peripherals.
+
config MACH_MX23EVK
bool "Support MX23EVK Platform"
select SOC_IMX23
@@ -24,7 +34,6 @@
select MXS_HAVE_PLATFORM_AUART
select MXS_HAVE_PLATFORM_MXS_MMC
select MXS_HAVE_PLATFORM_MXSFB
- default y
help
Include support for MX23EVK platform. This includes specific
configurations for the board and its peripherals.
@@ -39,7 +48,6 @@
select MXS_HAVE_PLATFORM_MXS_MMC
select MXS_HAVE_PLATFORM_MXSFB
select MXS_OCOTP
- default y
help
Include support for MX28EVK platform. This includes specific
configurations for the board and its peripherals.
diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile
index 2f1f614..58e8923 100644
--- a/arch/arm/mach-mxs/Makefile
+++ b/arch/arm/mach-mxs/Makefile
@@ -7,6 +7,7 @@
obj-$(CONFIG_SOC_IMX23) += clock-mx23.o mm-mx23.o
obj-$(CONFIG_SOC_IMX28) += clock-mx28.o mm-mx28.o
+obj-$(CONFIG_MACH_STMP378X_DEVB) += mach-stmp378x_devb.o
obj-$(CONFIG_MACH_MX23EVK) += mach-mx23evk.o
obj-$(CONFIG_MACH_MX28EVK) += mach-mx28evk.o
obj-$(CONFIG_MODULE_TX28) += module-tx28.o
diff --git a/arch/arm/mach-mxs/clock-mx23.c b/arch/arm/mach-mxs/clock-mx23.c
index c3577ea..0163b6d 100644
--- a/arch/arm/mach-mxs/clock-mx23.c
+++ b/arch/arm/mach-mxs/clock-mx23.c
@@ -446,6 +446,8 @@
_REGISTER_CLOCK("rtc", NULL, rtc_clk)
_REGISTER_CLOCK("mxs-dma-apbh", NULL, hbus_clk)
_REGISTER_CLOCK("mxs-dma-apbx", NULL, xbus_clk)
+ _REGISTER_CLOCK("mxs-mmc.0", NULL, ssp_clk)
+ _REGISTER_CLOCK("mxs-mmc.1", NULL, ssp_clk)
_REGISTER_CLOCK(NULL, "usb", usb_clk)
_REGISTER_CLOCK(NULL, "audio", audio_clk)
_REGISTER_CLOCK("mxs-pwm.0", NULL, pwm_clk)
diff --git a/arch/arm/mach-mxs/devices-mx28.h b/arch/arm/mach-mxs/devices-mx28.h
index c473edd..79b9452 100644
--- a/arch/arm/mach-mxs/devices-mx28.h
+++ b/arch/arm/mach-mxs/devices-mx28.h
@@ -34,7 +34,7 @@
#define mx28_add_flexcan0(pdata) mx28_add_flexcan(0, pdata)
#define mx28_add_flexcan1(pdata) mx28_add_flexcan(1, pdata)
-extern const struct mxs_i2c_data mx28_mxs_i2c_data[] __initconst;
+extern const struct mxs_mxs_i2c_data mx28_mxs_i2c_data[] __initconst;
#define mx28_add_mxs_i2c(id) mxs_add_mxs_i2c(&mx28_mxs_i2c_data[id])
extern const struct mxs_mxs_mmc_data mx28_mxs_mmc_data[] __initconst;
diff --git a/arch/arm/mach-mxs/devices/platform-mxs-i2c.c b/arch/arm/mach-mxs/devices/platform-mxs-i2c.c
index eab3a06..79222ec 100644
--- a/arch/arm/mach-mxs/devices/platform-mxs-i2c.c
+++ b/arch/arm/mach-mxs/devices/platform-mxs-i2c.c
@@ -22,13 +22,14 @@
[_id] = mxs_i2c_data_entry_single(soc, _id)
#ifdef CONFIG_SOC_IMX28
-const struct mxs_i2c_data mx28_mxs_i2c_data[] __initconst = {
+const struct mxs_mxs_i2c_data mx28_mxs_i2c_data[] __initconst = {
mxs_i2c_data_entry(MX28, 0),
mxs_i2c_data_entry(MX28, 1),
};
#endif
-struct platform_device *__init mxs_add_mxs_i2c(const struct mxs_i2c_data *data)
+struct platform_device *__init mxs_add_mxs_i2c(
+ const struct mxs_mxs_i2c_data *data)
{
struct resource res[] = {
{
diff --git a/arch/arm/mach-mxs/include/mach/devices-common.h b/arch/arm/mach-mxs/include/mach/devices-common.h
index c5137f1..7a37469 100644
--- a/arch/arm/mach-mxs/include/mach/devices-common.h
+++ b/arch/arm/mach-mxs/include/mach/devices-common.h
@@ -65,13 +65,14 @@
const struct flexcan_platform_data *pdata);
/* i2c */
-struct mxs_i2c_data {
+struct mxs_mxs_i2c_data {
int id;
resource_size_t iobase;
resource_size_t errirq;
resource_size_t dmairq;
};
-struct platform_device * __init mxs_add_mxs_i2c(const struct mxs_i2c_data *data);
+struct platform_device * __init mxs_add_mxs_i2c(
+ const struct mxs_mxs_i2c_data *data);
/* mmc */
#include <mach/mmc.h>
diff --git a/arch/arm/mach-mxs/include/mach/mx23.h b/arch/arm/mach-mxs/include/mach/mx23.h
index c0a18c2..599094b 100644
--- a/arch/arm/mach-mxs/include/mach/mx23.h
+++ b/arch/arm/mach-mxs/include/mach/mx23.h
@@ -57,7 +57,7 @@
#define MX23_AUDIOIN_BASE_ADDR (MX23_IO_BASE_ADDR + 0x04c000)
#define MX23_LRADC_BASE_ADDR (MX23_IO_BASE_ADDR + 0x050000)
#define MX23_SPDIF_BASE_ADDR (MX23_IO_BASE_ADDR + 0x054000)
-#define MX23_I2C0_BASE_ADDR (MX23_IO_BASE_ADDR + 0x058000)
+#define MX23_I2C_BASE_ADDR (MX23_IO_BASE_ADDR + 0x058000)
#define MX23_RTC_BASE_ADDR (MX23_IO_BASE_ADDR + 0x05c000)
#define MX23_PWM_BASE_ADDR (MX23_IO_BASE_ADDR + 0x064000)
#define MX23_TIMROT_BASE_ADDR (MX23_IO_BASE_ADDR + 0x068000)
diff --git a/arch/arm/mach-mxs/include/mach/uncompress.h b/arch/arm/mach-mxs/include/mach/uncompress.h
index f12a173..7f8bf65 100644
--- a/arch/arm/mach-mxs/include/mach/uncompress.h
+++ b/arch/arm/mach-mxs/include/mach/uncompress.h
@@ -20,7 +20,7 @@
#include <asm/mach-types.h>
-static unsigned long mxs_duart_base;
+unsigned long mxs_duart_base;
#define MXS_DUART(x) (*(volatile unsigned long *)(mxs_duart_base + (x)))
diff --git a/arch/arm/mach-mxs/mach-mx23evk.c b/arch/arm/mach-mxs/mach-mx23evk.c
index 214e5b6..3c2de33 100644
--- a/arch/arm/mach-mxs/mach-mx23evk.c
+++ b/arch/arm/mach-mxs/mach-mx23evk.c
@@ -148,7 +148,7 @@
mx23_add_auart0();
/* power on mmc slot by writing 0 to the gpio */
- ret = gpio_request_one(MX23EVK_MMC0_SLOT_POWER, GPIOF_DIR_OUT,
+ ret = gpio_request_one(MX23EVK_MMC0_SLOT_POWER, GPIOF_OUT_INIT_LOW,
"mmc0-slot-power");
if (ret)
pr_warn("failed to request gpio mmc0-slot-power: %d\n", ret);
diff --git a/arch/arm/mach-mxs/mach-mx28evk.c b/arch/arm/mach-mxs/mach-mx28evk.c
index bb329b9..eacdc6b 100644
--- a/arch/arm/mach-mxs/mach-mx28evk.c
+++ b/arch/arm/mach-mxs/mach-mx28evk.c
@@ -375,13 +375,13 @@
mx28_add_mxsfb(&mx28evk_mxsfb_pdata);
/* power on mmc slot by writing 0 to the gpio */
- ret = gpio_request_one(MX28EVK_MMC0_SLOT_POWER, GPIOF_DIR_OUT,
+ ret = gpio_request_one(MX28EVK_MMC0_SLOT_POWER, GPIOF_OUT_INIT_LOW,
"mmc0-slot-power");
if (ret)
pr_warn("failed to request gpio mmc0-slot-power: %d\n", ret);
mx28_add_mxs_mmc(0, &mx28evk_mmc_pdata[0]);
- ret = gpio_request_one(MX28EVK_MMC1_SLOT_POWER, GPIOF_DIR_OUT,
+ ret = gpio_request_one(MX28EVK_MMC1_SLOT_POWER, GPIOF_OUT_INIT_LOW,
"mmc1-slot-power");
if (ret)
pr_warn("failed to request gpio mmc1-slot-power: %d\n", ret);
diff --git a/arch/arm/mach-mxs/mach-stmp378x_devb.c b/arch/arm/mach-mxs/mach-stmp378x_devb.c
new file mode 100644
index 0000000..7f38d82
--- /dev/null
+++ b/arch/arm/mach-mxs/mach-stmp378x_devb.c
@@ -0,0 +1,120 @@
+/*
+ * board setup for STMP378x-Development-Board
+ *
+ * based on mx23evk board setup and information gained form the original
+ * plat-stmp based board setup, now converted to mach-mxs.
+ *
+ * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright (C) 2011 Wolfram Sang, Pengutronix e.K.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/gpio.h>
+#include <linux/irq.h>
+#include <linux/spi/spi.h>
+
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/time.h>
+
+#include <mach/common.h>
+#include <mach/iomux-mx23.h>
+
+#include "devices-mx23.h"
+
+#define STMP378X_DEVB_MMC0_WRITE_PROTECT MXS_GPIO_NR(1, 30)
+#define STMP378X_DEVB_MMC0_SLOT_POWER MXS_GPIO_NR(1, 29)
+
+#define STMP378X_DEVB_PAD_AUART (MXS_PAD_4MA | MXS_PAD_1V8 | MXS_PAD_NOPULL)
+
+static const iomux_cfg_t stmp378x_dvb_pads[] __initconst = {
+ /* duart (extended setup missing in old boardcode, too */
+ MX23_PAD_PWM0__DUART_RX,
+ MX23_PAD_PWM1__DUART_TX,
+
+ /* auart */
+ MX23_PAD_AUART1_RX__AUART1_RX | STMP378X_DEVB_PAD_AUART,
+ MX23_PAD_AUART1_TX__AUART1_TX | STMP378X_DEVB_PAD_AUART,
+ MX23_PAD_AUART1_CTS__AUART1_CTS | STMP378X_DEVB_PAD_AUART,
+ MX23_PAD_AUART1_RTS__AUART1_RTS | STMP378X_DEVB_PAD_AUART,
+
+ /* mmc */
+ MX23_PAD_SSP1_DATA0__SSP1_DATA0 |
+ (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+ MX23_PAD_SSP1_DATA1__SSP1_DATA1 |
+ (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+ MX23_PAD_SSP1_DATA2__SSP1_DATA2 |
+ (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+ MX23_PAD_SSP1_DATA3__SSP1_DATA3 |
+ (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+ MX23_PAD_SSP1_CMD__SSP1_CMD |
+ (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_PULLUP),
+ MX23_PAD_SSP1_DETECT__SSP1_DETECT |
+ (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX23_PAD_SSP1_SCK__SSP1_SCK |
+ (MXS_PAD_8MA | MXS_PAD_3V3 | MXS_PAD_NOPULL),
+ MX23_PAD_PWM4__GPIO_1_30 | MXS_PAD_CTRL, /* write protect */
+ MX23_PAD_PWM3__GPIO_1_29 | MXS_PAD_CTRL, /* power enable */
+};
+
+static struct mxs_mmc_platform_data stmp378x_dvb_mmc_pdata __initdata = {
+ .wp_gpio = STMP378X_DEVB_MMC0_WRITE_PROTECT,
+};
+
+static struct spi_board_info spi_board_info[] __initdata = {
+#if defined(CONFIG_ENC28J60) || defined(CONFIG_ENC28J60_MODULE)
+ {
+ .modalias = "enc28j60",
+ .max_speed_hz = 6 * 1000 * 1000,
+ .bus_num = 1,
+ .chip_select = 0,
+ .platform_data = NULL,
+ },
+#endif
+};
+
+static void __init stmp378x_dvb_init(void)
+{
+ int ret;
+
+ mxs_iomux_setup_multiple_pads(stmp378x_dvb_pads,
+ ARRAY_SIZE(stmp378x_dvb_pads));
+
+ mx23_add_duart();
+ mx23_add_auart0();
+
+ /* power on mmc slot */
+ ret = gpio_request_one(STMP378X_DEVB_MMC0_SLOT_POWER,
+ GPIOF_OUT_INIT_LOW, "mmc0-slot-power");
+ if (ret)
+ pr_warn("could not power mmc (%d)\n", ret);
+
+ mx23_add_mxs_mmc(0, &stmp378x_dvb_mmc_pdata);
+
+ spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
+}
+
+static void __init stmp378x_dvb_timer_init(void)
+{
+ mx23_clocks_init();
+}
+
+static struct sys_timer stmp378x_dvb_timer = {
+ .init = stmp378x_dvb_timer_init,
+};
+
+MACHINE_START(STMP378X, "STMP378X")
+ .map_io = mx23_map_io,
+ .init_irq = mx23_init_irq,
+ .init_machine = stmp378x_dvb_init,
+ .timer = &stmp378x_dvb_timer,
+MACHINE_END
diff --git a/arch/arm/mach-mxs/timer.c b/arch/arm/mach-mxs/timer.c
index 13647f3..cace0d2 100644
--- a/arch/arm/mach-mxs/timer.c
+++ b/arch/arm/mach-mxs/timer.c
@@ -101,11 +101,6 @@
& 0xffff0000) >> 16);
}
-static cycle_t timrotv2_get_cycles(struct clocksource *cs)
-{
- return ~__raw_readl(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1));
-}
-
static int timrotv1_set_next_event(unsigned long evt,
struct clock_event_device *dev)
{
@@ -230,8 +225,8 @@
static struct clocksource clocksource_mxs = {
.name = "mxs_timer",
.rating = 200,
- .read = timrotv2_get_cycles,
- .mask = CLOCKSOURCE_MASK(32),
+ .read = timrotv1_get_cycles,
+ .mask = CLOCKSOURCE_MASK(16),
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
};
@@ -239,12 +234,11 @@
{
unsigned int c = clk_get_rate(timer_clk);
- if (timrot_is_v1()) {
- clocksource_mxs.read = timrotv1_get_cycles;
- clocksource_mxs.mask = CLOCKSOURCE_MASK(16);
- }
-
- clocksource_register_hz(&clocksource_mxs, c);
+ if (timrot_is_v1())
+ clocksource_register_hz(&clocksource_mxs, c);
+ else
+ clocksource_mmio_init(mxs_timrot_base + HW_TIMROT_RUNNING_COUNTn(1),
+ "mxs_timer", c, 200, 32, clocksource_mmio_readl_down);
return 0;
}
diff --git a/arch/arm/mach-netx/time.c b/arch/arm/mach-netx/time.c
index f12f22d..e24c141 100644
--- a/arch/arm/mach-netx/time.c
+++ b/arch/arm/mach-netx/time.c
@@ -104,19 +104,6 @@
.handler = netx_timer_interrupt,
};
-cycle_t netx_get_cycles(struct clocksource *cs)
-{
- return readl(NETX_GPIO_COUNTER_CURRENT(TIMER_CLOCKSOURCE));
-}
-
-static struct clocksource clocksource_netx = {
- .name = "netx_timer",
- .rating = 200,
- .read = netx_get_cycles,
- .mask = CLOCKSOURCE_MASK(32),
- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
/*
* Set up timer interrupt
*/
@@ -150,7 +137,8 @@
writel(NETX_GPIO_COUNTER_CTRL_RUN,
NETX_GPIO_COUNTER_CTRL(TIMER_CLOCKSOURCE));
- clocksource_register_hz(&clocksource_netx, CLOCK_TICK_RATE);
+ clocksource_mmio_init(NETX_GPIO_COUNTER_CURRENT(TIMER_CLOCKSOURCE),
+ "netx_timer", CLOCK_TICK_RATE, 200, 32, clocksource_mmio_readl_up);
netx_clockevent.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC,
netx_clockevent.shift);
diff --git a/arch/arm/mach-ns9xxx/Kconfig b/arch/arm/mach-ns9xxx/Kconfig
deleted file mode 100644
index dd0cd5a..0000000
--- a/arch/arm/mach-ns9xxx/Kconfig
+++ /dev/null
@@ -1,40 +0,0 @@
-if ARCH_NS9XXX
-
-menu "NS9xxx Implementations"
-
-config NS9XXX_HAVE_SERIAL8250
- bool
-
-config PROCESSOR_NS9360
- bool
-
-config MODULE_CC9P9360
- bool
- select PROCESSOR_NS9360
-
-config BOARD_A9M9750DEV
- select NS9XXX_HAVE_SERIAL8250
- bool
-
-config BOARD_JSCC9P9360
- bool
-
-config MACH_CC9P9360DEV
- bool "ConnectCore 9P 9360 on an A9M9750 Devboard"
- select MODULE_CC9P9360
- select BOARD_A9M9750DEV
- help
- Say Y here if you are using the Digi ConnectCore 9P 9360
- on an A9M9750 Development Board.
-
-config MACH_CC9P9360JS
- bool "ConnectCore 9P 9360 on a JSCC9P9360 Devboard"
- select MODULE_CC9P9360
- select BOARD_JSCC9P9360
- help
- Say Y here if you are using the Digi ConnectCore 9P 9360
- on an JSCC9P9360 Development Board.
-
-endmenu
-
-endif
diff --git a/arch/arm/mach-ns9xxx/Makefile b/arch/arm/mach-ns9xxx/Makefile
deleted file mode 100644
index 41efaf9..0000000
--- a/arch/arm/mach-ns9xxx/Makefile
+++ /dev/null
@@ -1,12 +0,0 @@
-obj-y := clock.o generic.o gpio.o irq.o
-
-obj-$(CONFIG_MACH_CC9P9360DEV) += mach-cc9p9360dev.o
-obj-$(CONFIG_MACH_CC9P9360JS) += mach-cc9p9360js.o
-
-obj-$(CONFIG_PROCESSOR_NS9360) += gpio-ns9360.o processor-ns9360.o time-ns9360.o
-
-obj-$(CONFIG_BOARD_A9M9750DEV) += board-a9m9750dev.o
-obj-$(CONFIG_BOARD_JSCC9P9360) += board-jscc9p9360.o
-
-# platform devices
-obj-$(CONFIG_NS9XXX_HAVE_SERIAL8250) += plat-serial8250.o
diff --git a/arch/arm/mach-ns9xxx/Makefile.boot b/arch/arm/mach-ns9xxx/Makefile.boot
deleted file mode 100644
index 5465491..0000000
--- a/arch/arm/mach-ns9xxx/Makefile.boot
+++ /dev/null
@@ -1,2 +0,0 @@
-zreladdr-y := 0x8000
-params_phys-y := 0x100
diff --git a/arch/arm/mach-ns9xxx/board-a9m9750dev.c b/arch/arm/mach-ns9xxx/board-a9m9750dev.c
deleted file mode 100644
index e27687d..0000000
--- a/arch/arm/mach-ns9xxx/board-a9m9750dev.c
+++ /dev/null
@@ -1,156 +0,0 @@
-/*
- * arch/arm/mach-ns9xxx/board-a9m9750dev.c
- *
- * Copyright (C) 2006,2007 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-#include <linux/irq.h>
-
-#include <asm/mach/map.h>
-#include <asm/gpio.h>
-
-#include <mach/board.h>
-#include <mach/processor-ns9360.h>
-#include <mach/regs-sys-ns9360.h>
-#include <mach/regs-mem.h>
-#include <mach/regs-bbu.h>
-#include <mach/regs-board-a9m9750dev.h>
-
-#include "board-a9m9750dev.h"
-
-static struct map_desc board_a9m9750dev_io_desc[] __initdata = {
- { /* FPGA on CS0 */
- .virtual = io_p2v(NS9XXX_CSxSTAT_PHYS(0)),
- .pfn = __phys_to_pfn(NS9XXX_CSxSTAT_PHYS(0)),
- .length = NS9XXX_CS0STAT_LENGTH,
- .type = MT_DEVICE,
- },
-};
-
-void __init board_a9m9750dev_map_io(void)
-{
- iotable_init(board_a9m9750dev_io_desc,
- ARRAY_SIZE(board_a9m9750dev_io_desc));
-}
-
-static void a9m9750dev_fpga_ack_irq(struct irq_data *d)
-{
- /* nothing */
-}
-
-static void a9m9750dev_fpga_mask_irq(struct irq_data *d)
-{
- u8 ier;
-
- ier = __raw_readb(FPGA_IER);
-
- ier &= ~(1 << (d->irq - FPGA_IRQ(0)));
-
- __raw_writeb(ier, FPGA_IER);
-}
-
-static void a9m9750dev_fpga_maskack_irq(struct irq_data *d)
-{
- a9m9750dev_fpga_mask_irq(d);
- a9m9750dev_fpga_ack_irq(d);
-}
-
-static void a9m9750dev_fpga_unmask_irq(struct irq_data *d)
-{
- u8 ier;
-
- ier = __raw_readb(FPGA_IER);
-
- ier |= 1 << (d->irq - FPGA_IRQ(0));
-
- __raw_writeb(ier, FPGA_IER);
-}
-
-static struct irq_chip a9m9750dev_fpga_chip = {
- .irq_ack = a9m9750dev_fpga_ack_irq,
- .irq_mask = a9m9750dev_fpga_mask_irq,
- .irq_mask_ack = a9m9750dev_fpga_maskack_irq,
- .irq_unmask = a9m9750dev_fpga_unmask_irq,
-};
-
-static void a9m9750dev_fpga_demux_handler(unsigned int irq,
- struct irq_desc *desc)
-{
- u8 stat = __raw_readb(FPGA_ISR);
-
- desc->irq_data.chip->irq_mask_ack(&desc->irq_data);
-
- while (stat != 0) {
- int irqno = fls(stat) - 1;
-
- stat &= ~(1 << irqno);
-
- generic_handle_irq(FPGA_IRQ(irqno));
- }
-
- desc->irq_data.chip->irq_unmask(&desc->irq_data);
-}
-
-void __init board_a9m9750dev_init_irq(void)
-{
- u32 eic;
- int i;
-
- if (gpio_request(11, "board a9m9750dev extirq2") == 0)
- ns9360_gpio_configure(11, 0, 1);
- else
- printk(KERN_ERR "%s: cannot get gpio 11 for IRQ_NS9XXX_EXT2\n",
- __func__);
-
- for (i = FPGA_IRQ(0); i <= FPGA_IRQ(7); ++i) {
- irq_set_chip_and_handler(i, &a9m9750dev_fpga_chip,
- handle_level_irq);
- set_irq_flags(i, IRQF_VALID);
- }
-
- /* IRQ_NS9XXX_EXT2: level sensitive + active low */
- eic = __raw_readl(SYS_EIC(2));
- REGSET(eic, SYS_EIC, PLTY, AL);
- REGSET(eic, SYS_EIC, LVEDG, LEVEL);
- __raw_writel(eic, SYS_EIC(2));
-
- irq_set_chained_handler(IRQ_NS9XXX_EXT2,
- a9m9750dev_fpga_demux_handler);
-}
-
-void __init board_a9m9750dev_init_machine(void)
-{
- u32 reg;
-
- /* setup static CS0: memory base ... */
- reg = __raw_readl(SYS_SMCSSMB(0));
- REGSETIM(reg, SYS_SMCSSMB, CSxB, NS9XXX_CSxSTAT_PHYS(0) >> 12);
- __raw_writel(reg, SYS_SMCSSMB(0));
-
- /* ... and mask */
- reg = __raw_readl(SYS_SMCSSMM(0));
- REGSETIM(reg, SYS_SMCSSMM, CSxM, 0xfffff);
- REGSET(reg, SYS_SMCSSMM, CSEx, EN);
- __raw_writel(reg, SYS_SMCSSMM(0));
-
- /* setup static CS0: memory configuration */
- reg = __raw_readl(MEM_SMC(0));
- REGSET(reg, MEM_SMC, PSMC, OFF);
- REGSET(reg, MEM_SMC, BSMC, OFF);
- REGSET(reg, MEM_SMC, EW, OFF);
- REGSET(reg, MEM_SMC, PB, 1);
- REGSET(reg, MEM_SMC, PC, AL);
- REGSET(reg, MEM_SMC, PM, DIS);
- REGSET(reg, MEM_SMC, MW, 8);
- __raw_writel(reg, MEM_SMC(0));
-
- /* setup static CS0: timing */
- __raw_writel(0x2, MEM_SMWED(0));
- __raw_writel(0x2, MEM_SMOED(0));
- __raw_writel(0x6, MEM_SMRD(0));
- __raw_writel(0x6, MEM_SMWD(0));
-}
diff --git a/arch/arm/mach-ns9xxx/board-a9m9750dev.h b/arch/arm/mach-ns9xxx/board-a9m9750dev.h
deleted file mode 100644
index edc75ab..0000000
--- a/arch/arm/mach-ns9xxx/board-a9m9750dev.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * arch/arm/mach-ns9xxx/board-a9m9750dev.h
- *
- * Copyright (C) 2006 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-#include <linux/init.h>
-
-void __init board_a9m9750dev_map_io(void);
-void __init board_a9m9750dev_init_machine(void);
-void __init board_a9m9750dev_init_irq(void);
diff --git a/arch/arm/mach-ns9xxx/board-jscc9p9360.c b/arch/arm/mach-ns9xxx/board-jscc9p9360.c
deleted file mode 100644
index 4bd3eec..0000000
--- a/arch/arm/mach-ns9xxx/board-jscc9p9360.c
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * arch/arm/mach-ns9xxx/board-jscc9p9360.c
- *
- * Copyright (C) 2006,2007 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-#include "board-jscc9p9360.h"
-
-void __init board_jscc9p9360_init_machine(void)
-{
- /* TODO: reserve GPIOs for push buttons, etc pp */
-}
-
diff --git a/arch/arm/mach-ns9xxx/board-jscc9p9360.h b/arch/arm/mach-ns9xxx/board-jscc9p9360.h
deleted file mode 100644
index 1a81a07..0000000
--- a/arch/arm/mach-ns9xxx/board-jscc9p9360.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * arch/arm/mach-ns9xxx/board-jscc9p9360.h
- *
- * Copyright (C) 2006 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-#include <linux/init.h>
-
-void __init board_jscc9p9360_init_machine(void);
diff --git a/arch/arm/mach-ns9xxx/clock.c b/arch/arm/mach-ns9xxx/clock.c
deleted file mode 100644
index cf81cbc..0000000
--- a/arch/arm/mach-ns9xxx/clock.c
+++ /dev/null
@@ -1,215 +0,0 @@
-/*
- * arch/arm/mach-ns9xxx/clock.c
- *
- * Copyright (C) 2007 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-#include <linux/err.h>
-#include <linux/module.h>
-#include <linux/list.h>
-#include <linux/clk.h>
-#include <linux/string.h>
-#include <linux/platform_device.h>
-#include <linux/semaphore.h>
-
-#include "clock.h"
-
-static LIST_HEAD(clocks);
-static DEFINE_SPINLOCK(clk_lock);
-
-struct clk *clk_get(struct device *dev, const char *id)
-{
- struct clk *p, *ret = NULL, *retgen = NULL;
- unsigned long flags;
- int idno;
-
- if (dev == NULL || dev->bus != &platform_bus_type)
- idno = -1;
- else
- idno = to_platform_device(dev)->id;
-
- spin_lock_irqsave(&clk_lock, flags);
- list_for_each_entry(p, &clocks, node) {
- if (strcmp(id, p->name) == 0) {
- if (p->id == idno) {
- if (!try_module_get(p->owner))
- continue;
- ret = p;
- break;
- } else if (p->id == -1)
- /* remember match with id == -1 in case there is
- * no clock for idno */
- retgen = p;
- }
- }
-
- if (!ret && retgen && try_module_get(retgen->owner))
- ret = retgen;
-
- if (ret)
- ++ret->refcount;
-
- spin_unlock_irqrestore(&clk_lock, flags);
-
- return ret ? ret : ERR_PTR(-ENOENT);
-}
-EXPORT_SYMBOL(clk_get);
-
-void clk_put(struct clk *clk)
-{
- module_put(clk->owner);
- --clk->refcount;
-}
-EXPORT_SYMBOL(clk_put);
-
-static int clk_enable_unlocked(struct clk *clk)
-{
- int ret = 0;
- if (clk->parent) {
- ret = clk_enable_unlocked(clk->parent);
- if (ret)
- return ret;
- }
-
- if (clk->usage++ == 0 && clk->endisable)
- ret = clk->endisable(clk, 1);
-
- return ret;
-}
-
-int clk_enable(struct clk *clk)
-{
- int ret;
- unsigned long flags;
-
- spin_lock_irqsave(&clk_lock, flags);
-
- ret = clk_enable_unlocked(clk);
-
- spin_unlock_irqrestore(&clk_lock, flags);
-
- return ret;
-}
-EXPORT_SYMBOL(clk_enable);
-
-static void clk_disable_unlocked(struct clk *clk)
-{
- if (--clk->usage == 0 && clk->endisable)
- clk->endisable(clk, 0);
-
- if (clk->parent)
- clk_disable_unlocked(clk->parent);
-}
-
-void clk_disable(struct clk *clk)
-{
- unsigned long flags;
-
- spin_lock_irqsave(&clk_lock, flags);
-
- clk_disable_unlocked(clk);
-
- spin_unlock_irqrestore(&clk_lock, flags);
-}
-EXPORT_SYMBOL(clk_disable);
-
-unsigned long clk_get_rate(struct clk *clk)
-{
- if (clk->get_rate)
- return clk->get_rate(clk);
-
- if (clk->rate)
- return clk->rate;
-
- if (clk->parent)
- return clk_get_rate(clk->parent);
-
- return 0;
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-int clk_register(struct clk *clk)
-{
- unsigned long flags;
-
- spin_lock_irqsave(&clk_lock, flags);
-
- list_add(&clk->node, &clocks);
-
- if (clk->parent)
- ++clk->parent->refcount;
-
- spin_unlock_irqrestore(&clk_lock, flags);
-
- return 0;
-}
-
-int clk_unregister(struct clk *clk)
-{
- int ret = 0;
- unsigned long flags;
-
- spin_lock_irqsave(&clk_lock, flags);
-
- if (clk->usage || clk->refcount)
- ret = -EBUSY;
- else
- list_del(&clk->node);
-
- if (clk->parent)
- --clk->parent->refcount;
-
- spin_unlock_irqrestore(&clk_lock, flags);
-
- return ret;
-}
-
-#if defined CONFIG_DEBUG_FS
-
-#include <linux/debugfs.h>
-#include <linux/seq_file.h>
-
-static int clk_debugfs_show(struct seq_file *s, void *null)
-{
- unsigned long flags;
- struct clk *p;
-
- spin_lock_irqsave(&clk_lock, flags);
-
- list_for_each_entry(p, &clocks, node)
- seq_printf(s, "%s.%d: usage=%lu refcount=%lu rate=%lu\n",
- p->name, p->id, p->usage, p->refcount,
- p->usage ? clk_get_rate(p) : 0);
-
- spin_unlock_irqrestore(&clk_lock, flags);
-
- return 0;
-}
-
-static int clk_debugfs_open(struct inode *inode, struct file *file)
-{
- return single_open(file, clk_debugfs_show, NULL);
-}
-
-static const struct file_operations clk_debugfs_operations = {
- .open = clk_debugfs_open,
- .read = seq_read,
- .llseek = seq_lseek,
- .release = single_release,
-};
-
-static int __init clk_debugfs_init(void)
-{
- struct dentry *dentry;
-
- dentry = debugfs_create_file("clk", S_IFREG | S_IRUGO, NULL, NULL,
- &clk_debugfs_operations);
- return IS_ERR(dentry) ? PTR_ERR(dentry) : 0;
-}
-subsys_initcall(clk_debugfs_init);
-
-#endif /* if defined CONFIG_DEBUG_FS */
diff --git a/arch/arm/mach-ns9xxx/clock.h b/arch/arm/mach-ns9xxx/clock.h
deleted file mode 100644
index b86c30d..0000000
--- a/arch/arm/mach-ns9xxx/clock.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * arch/arm/mach-ns9xxx/clock.h
- *
- * Copyright (C) 2007 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-#ifndef __NS9XXX_CLOCK_H
-#define __NS9XXX_CLOCK_H
-
-#include <linux/list.h>
-
-struct clk {
- struct module *owner;
- const char *name;
- int id;
-
- struct clk *parent;
-
- unsigned long rate;
- int (*endisable)(struct clk *, int enable);
- unsigned long (*get_rate)(struct clk *);
-
- struct list_head node;
- unsigned long refcount;
- unsigned long usage;
-};
-
-int clk_register(struct clk *clk);
-int clk_unregister(struct clk *clk);
-
-#endif /* ifndef __NS9XXX_CLOCK_H */
diff --git a/arch/arm/mach-ns9xxx/generic.c b/arch/arm/mach-ns9xxx/generic.c
deleted file mode 100644
index 1e0f467..0000000
--- a/arch/arm/mach-ns9xxx/generic.c
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-ns9xxx/generic.c
- *
- * Copyright (C) 2006,2007 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <asm/memory.h>
-
-#include "generic.h"
-
-void __init ns9xxx_init_machine(void)
-{
-}
diff --git a/arch/arm/mach-ns9xxx/generic.h b/arch/arm/mach-ns9xxx/generic.h
deleted file mode 100644
index 8249319..0000000
--- a/arch/arm/mach-ns9xxx/generic.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * arch/arm/mach-ns9xxx/generic.h
- *
- * Copyright (C) 2006,2007 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-#include <linux/time.h>
-#include <asm/mach/time.h>
-#include <linux/init.h>
-
-void __init ns9xxx_init_irq(void);
-void __init ns9xxx_init_machine(void);
diff --git a/arch/arm/mach-ns9xxx/gpio-ns9360.c b/arch/arm/mach-ns9xxx/gpio-ns9360.c
deleted file mode 100644
index 377330c..0000000
--- a/arch/arm/mach-ns9xxx/gpio-ns9360.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * arch/arm/mach-ns9xxx/gpio-ns9360.c
- *
- * Copyright (C) 2006,2007 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-#include <linux/bug.h>
-#include <linux/errno.h>
-#include <linux/io.h>
-#include <linux/kernel.h>
-#include <linux/module.h>
-
-#include <mach/regs-bbu.h>
-#include <mach/processor-ns9360.h>
-
-#include "gpio-ns9360.h"
-
-static inline int ns9360_valid_gpio(unsigned gpio)
-{
- return gpio <= 72;
-}
-
-static inline void __iomem *ns9360_gpio_get_gconfaddr(unsigned gpio)
-{
- if (gpio < 56)
- return BBU_GCONFb1(gpio / 8);
- else
- /*
- * this could be optimised away on
- * ns9750 only builds, but it isn't ...
- */
- return BBU_GCONFb2((gpio - 56) / 8);
-}
-
-static inline void __iomem *ns9360_gpio_get_gctrladdr(unsigned gpio)
-{
- if (gpio < 32)
- return BBU_GCTRL1;
- else if (gpio < 64)
- return BBU_GCTRL2;
- else
- /* this could be optimised away on ns9750 only builds */
- return BBU_GCTRL3;
-}
-
-static inline void __iomem *ns9360_gpio_get_gstataddr(unsigned gpio)
-{
- if (gpio < 32)
- return BBU_GSTAT1;
- else if (gpio < 64)
- return BBU_GSTAT2;
- else
- /* this could be optimised away on ns9750 only builds */
- return BBU_GSTAT3;
-}
-
-/*
- * each gpio can serve for 4 different purposes [0..3]. These are called
- * "functions" and passed in the parameter func. Functions 0-2 are always some
- * special things, function 3 is GPIO. If func == 3 dir specifies input or
- * output, and with inv you can enable an inverter (independent of func).
- */
-int __ns9360_gpio_configure(unsigned gpio, int dir, int inv, int func)
-{
- void __iomem *conf = ns9360_gpio_get_gconfaddr(gpio);
- u32 confval;
-
- confval = __raw_readl(conf);
- REGSETIM_IDX(confval, BBU_GCONFx, DIR, gpio & 7, dir);
- REGSETIM_IDX(confval, BBU_GCONFx, INV, gpio & 7, inv);
- REGSETIM_IDX(confval, BBU_GCONFx, FUNC, gpio & 7, func);
- __raw_writel(confval, conf);
-
- return 0;
-}
-
-int ns9360_gpio_configure(unsigned gpio, int inv, int func)
-{
- if (likely(ns9360_valid_gpio(gpio))) {
- if (func == 3) {
- printk(KERN_WARNING "use gpio_direction_input "
- "or gpio_direction_output\n");
- return -EINVAL;
- } else
- return __ns9360_gpio_configure(gpio, 0, inv, func);
- } else
- return -EINVAL;
-}
-EXPORT_SYMBOL(ns9360_gpio_configure);
-
-int ns9360_gpio_get_value(unsigned gpio)
-{
- void __iomem *stat = ns9360_gpio_get_gstataddr(gpio);
- int ret;
-
- ret = 1 & (__raw_readl(stat) >> (gpio & 31));
-
- return ret;
-}
-
-void ns9360_gpio_set_value(unsigned gpio, int value)
-{
- void __iomem *ctrl = ns9360_gpio_get_gctrladdr(gpio);
- u32 ctrlval;
-
- ctrlval = __raw_readl(ctrl);
-
- if (value)
- ctrlval |= 1 << (gpio & 31);
- else
- ctrlval &= ~(1 << (gpio & 31));
-
- __raw_writel(ctrlval, ctrl);
-}
diff --git a/arch/arm/mach-ns9xxx/gpio-ns9360.h b/arch/arm/mach-ns9xxx/gpio-ns9360.h
deleted file mode 100644
index 131cd17..0000000
--- a/arch/arm/mach-ns9xxx/gpio-ns9360.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * arch/arm/mach-ns9xxx/gpio-ns9360.h
- *
- * Copyright (C) 2006,2007 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-int __ns9360_gpio_configure(unsigned gpio, int dir, int inv, int func);
-int ns9360_gpio_get_value(unsigned gpio);
-void ns9360_gpio_set_value(unsigned gpio, int value);
diff --git a/arch/arm/mach-ns9xxx/gpio.c b/arch/arm/mach-ns9xxx/gpio.c
deleted file mode 100644
index 5503ca0..0000000
--- a/arch/arm/mach-ns9xxx/gpio.c
+++ /dev/null
@@ -1,147 +0,0 @@
-/*
- * arch/arm/mach-ns9xxx/gpio.c
- *
- * Copyright (C) 2006,2007 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-#include <linux/kernel.h>
-#include <linux/compiler.h>
-#include <linux/init.h>
-#include <linux/spinlock.h>
-#include <linux/module.h>
-#include <linux/bitops.h>
-
-#include <mach/gpio.h>
-#include <mach/processor.h>
-#include <mach/processor-ns9360.h>
-#include <asm/bug.h>
-#include <asm/types.h>
-
-#include "gpio-ns9360.h"
-
-#if defined(CONFIG_PROCESSOR_NS9360)
-#define GPIO_MAX 72
-#elif defined(CONFIG_PROCESSOR_NS9750)
-#define GPIO_MAX 49
-#endif
-
-/* protects BBU_GCONFx and BBU_GCTRLx */
-static spinlock_t gpio_lock = __SPIN_LOCK_UNLOCKED(gpio_lock);
-
-/* only access gpiores with atomic ops */
-static DECLARE_BITMAP(gpiores, GPIO_MAX + 1);
-
-static inline int ns9xxx_valid_gpio(unsigned gpio)
-{
-#if defined(CONFIG_PROCESSOR_NS9360)
- if (processor_is_ns9360())
- return gpio <= 72;
- else
-#endif
-#if defined(CONFIG_PROCESSOR_NS9750)
- if (processor_is_ns9750())
- return gpio <= 49;
- else
-#endif
- {
- BUG();
- return 0;
- }
-}
-
-int gpio_request(unsigned gpio, const char *label)
-{
- if (likely(ns9xxx_valid_gpio(gpio)))
- return test_and_set_bit(gpio, gpiores) ? -EBUSY : 0;
- else
- return -EINVAL;
-}
-EXPORT_SYMBOL(gpio_request);
-
-void gpio_free(unsigned gpio)
-{
- might_sleep();
- clear_bit(gpio, gpiores);
- return;
-}
-EXPORT_SYMBOL(gpio_free);
-
-int gpio_direction_input(unsigned gpio)
-{
- if (likely(ns9xxx_valid_gpio(gpio))) {
- int ret = -EINVAL;
- unsigned long flags;
-
- spin_lock_irqsave(&gpio_lock, flags);
-#if defined(CONFIG_PROCESSOR_NS9360)
- if (processor_is_ns9360())
- ret = __ns9360_gpio_configure(gpio, 0, 0, 3);
- else
-#endif
- BUG();
-
- spin_unlock_irqrestore(&gpio_lock, flags);
-
- return ret;
-
- } else
- return -EINVAL;
-}
-EXPORT_SYMBOL(gpio_direction_input);
-
-int gpio_direction_output(unsigned gpio, int value)
-{
- if (likely(ns9xxx_valid_gpio(gpio))) {
- int ret = -EINVAL;
- unsigned long flags;
-
- gpio_set_value(gpio, value);
-
- spin_lock_irqsave(&gpio_lock, flags);
-#if defined(CONFIG_PROCESSOR_NS9360)
- if (processor_is_ns9360())
- ret = __ns9360_gpio_configure(gpio, 1, 0, 3);
- else
-#endif
- BUG();
-
- spin_unlock_irqrestore(&gpio_lock, flags);
-
- return ret;
- } else
- return -EINVAL;
-}
-EXPORT_SYMBOL(gpio_direction_output);
-
-int gpio_get_value(unsigned gpio)
-{
-#if defined(CONFIG_PROCESSOR_NS9360)
- if (processor_is_ns9360())
- return ns9360_gpio_get_value(gpio);
- else
-#endif
- {
- BUG();
- return -EINVAL;
- }
-}
-EXPORT_SYMBOL(gpio_get_value);
-
-void gpio_set_value(unsigned gpio, int value)
-{
- unsigned long flags;
- spin_lock_irqsave(&gpio_lock, flags);
-#if defined(CONFIG_PROCESSOR_NS9360)
- if (processor_is_ns9360())
- ns9360_gpio_set_value(gpio, value);
- else
-#endif
- BUG();
-
- spin_unlock_irqrestore(&gpio_lock, flags);
-}
-EXPORT_SYMBOL(gpio_set_value);
diff --git a/arch/arm/mach-ns9xxx/include/mach/board.h b/arch/arm/mach-ns9xxx/include/mach/board.h
deleted file mode 100644
index 19ca6de..0000000
--- a/arch/arm/mach-ns9xxx/include/mach/board.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * arch/arm/mach-ns9xxx/include/mach/board.h
- *
- * Copyright (C) 2006,2007 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-#ifndef __ASM_ARCH_BOARD_H
-#define __ASM_ARCH_BOARD_H
-
-#include <asm/mach-types.h>
-
-#define board_is_a9m9750dev() (0 \
- || machine_is_cc9p9750dev() \
- )
-
-#define board_is_a9mvali() (0 \
- || machine_is_cc9p9750val() \
- )
-
-#define board_is_jscc9p9210() (0 \
- || machine_is_cc9p9210js() \
- )
-
-#define board_is_jscc9p9215() (0 \
- || machine_is_cc9p9215js() \
- )
-
-#define board_is_jscc9p9360() (0 \
- || machine_is_cc9p9360js() \
- )
-
-#define board_is_uncbas() (0 \
- || machine_is_cc7ucamry() \
- )
-
-#endif /* ifndef __ASM_ARCH_BOARD_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/debug-macro.S b/arch/arm/mach-ns9xxx/include/mach/debug-macro.S
deleted file mode 100644
index 5a2acbd..0000000
--- a/arch/arm/mach-ns9xxx/include/mach/debug-macro.S
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * arch/arm/mach-ns9xxx/include/mach/debug-macro.S
- * Copyright (C) 2006 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-#include <mach/hardware.h>
-#include <asm/memory.h>
-
-#include <mach/regs-board-a9m9750dev.h>
-
- .macro addruart, rp, rv
- ldr \rp, =NS9XXX_CSxSTAT_PHYS(0)
- ldr \rv, =io_p2v(NS9XXX_CSxSTAT_PHYS(0))
- .endm
-
-#define UART_SHIFT 2
-#include <asm/hardware/debug-8250.S>
diff --git a/arch/arm/mach-ns9xxx/include/mach/entry-macro.S b/arch/arm/mach-ns9xxx/include/mach/entry-macro.S
deleted file mode 100644
index 71ca031..0000000
--- a/arch/arm/mach-ns9xxx/include/mach/entry-macro.S
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * arch/arm/mach-ns9xxx/include/mach/entry-macro.S
- *
- * Copyright (C) 2006,2007 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-#include <mach/hardware.h>
-#include <mach/regs-sys-common.h>
-
- .macro get_irqnr_preamble, base, tmp
- ldr \base, =SYS_ISRADDR
- .endm
-
- .macro arch_ret_to_user, tmp1, tmp2
- .endm
-
- .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
- ldr \irqstat, [\base, #(SYS_ISA - SYS_ISRADDR)]
- cmp \irqstat, #0
- ldrne \irqnr, [\base]
- .endm
-
- .macro disable_fiq
- .endm
diff --git a/arch/arm/mach-ns9xxx/include/mach/gpio.h b/arch/arm/mach-ns9xxx/include/mach/gpio.h
deleted file mode 100644
index 5eb3490..0000000
--- a/arch/arm/mach-ns9xxx/include/mach/gpio.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * arch/arm/mach-ns9xxx/include/mach/gpio.h
- *
- * Copyright (C) 2007 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
-*/
-#ifndef __ASM_ARCH_GPIO_H
-#define __ASM_ARCH_GPIO_H
-
-#include <asm/errno.h>
-
-int gpio_request(unsigned gpio, const char *label);
-
-void gpio_free(unsigned gpio);
-
-int ns9xxx_gpio_configure(unsigned gpio, int inv, int func);
-
-int gpio_direction_input(unsigned gpio);
-
-int gpio_direction_output(unsigned gpio, int value);
-
-int gpio_get_value(unsigned gpio);
-
-void gpio_set_value(unsigned gpio, int value);
-
-/*
- * ns9xxx can use gpio pins to trigger an irq, but it's not generic
- * enough to be supported by the gpio_to_irq/irq_to_gpio interface
- */
-static inline int gpio_to_irq(unsigned gpio)
-{
- return -EINVAL;
-}
-
-static inline int irq_to_gpio(unsigned irq)
-{
- return -EINVAL;
-}
-
-/* get the cansleep() stubs */
-#include <asm-generic/gpio.h>
-
-#endif /* ifndef __ASM_ARCH_GPIO_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/hardware.h b/arch/arm/mach-ns9xxx/include/mach/hardware.h
deleted file mode 100644
index 7663112..0000000
--- a/arch/arm/mach-ns9xxx/include/mach/hardware.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * arch/arm/mach-ns9xxx/include/mach/hardware.h
- *
- * Copyright (C) 2006 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-/*
- * NetSilicon NS9xxx internal mapping:
- *
- * physical <--> virtual
- * 0x90000000 - 0x906fffff <--> 0xf9000000 - 0xf96fffff
- * 0xa0100000 - 0xa0afffff <--> 0xfa100000 - 0xfaafffff
- */
-#define io_p2v(x) (0xf0000000 \
- + (((x) & 0xf0000000) >> 4) \
- + ((x) & 0x00ffffff))
-
-#define io_v2p(x) ((((x) & 0x0f000000) << 4) \
- + ((x) & 0x00ffffff))
-
-#define __REGSHIFT(mask) ((mask) & (-(mask)))
-
-#define __REGBIT(bit) ((u32)1 << (bit))
-#define __REGBITS(hbit, lbit) ((((u32)1 << ((hbit) - (lbit) + 1)) - 1) << (lbit))
-#define __REGVAL(mask, value) (((value) * __REGSHIFT(mask)) & (mask))
-
-#ifndef __ASSEMBLY__
-
-# define __REG(x) ((void __iomem __force *)io_p2v((x)))
-# define __REG2(x, y) ((void __iomem __force *)(io_p2v((x)) + 4 * (y)))
-
-# define __REGSET(var, field, value) \
- ((var) = (((var) & ~((field) & ~(value))) | (value)))
-
-# define REGSET(var, reg, field, value) \
- __REGSET(var, reg ## _ ## field, reg ## _ ## field ## _ ## value)
-
-# define REGSET_IDX(var, reg, field, idx, value) \
- __REGSET(var, reg ## _ ## field((idx)), reg ## _ ## field ## _ ## value((idx)))
-
-# define REGSETIM(var, reg, field, value) \
- __REGSET(var, reg ## _ ## field, __REGVAL(reg ## _ ## field, (value)))
-
-# define REGSETIM_IDX(var, reg, field, idx, value) \
- __REGSET(var, reg ## _ ## field((idx)), __REGVAL(reg ## _ ## field((idx)), (value)))
-
-# define __REGGET(var, field) \
- (((var) & (field)))
-
-# define REGGET(var, reg, field) \
- __REGGET(var, reg ## _ ## field)
-
-# define REGGET_IDX(var, reg, field, idx) \
- __REGGET(var, reg ## _ ## field((idx)))
-
-# define REGGETIM(var, reg, field) \
- __REGGET(var, reg ## _ ## field) / __REGSHIFT(reg ## _ ## field)
-
-# define REGGETIM_IDX(var, reg, field, idx) \
- __REGGET(var, reg ## _ ## field((idx))) / \
- __REGSHIFT(reg ## _ ## field((idx)))
-
-#else
-
-# define __REG(x) io_p2v(x)
-# define __REG2(x, y) io_p2v((x) + 4 * (y))
-
-#endif
-
-#endif /* ifndef __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/io.h b/arch/arm/mach-ns9xxx/include/mach/io.h
deleted file mode 100644
index f08451d..0000000
--- a/arch/arm/mach-ns9xxx/include/mach/io.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * arch/arm/mach-ns9xxx/include/mach/io.h
- *
- * Copyright (C) 2006 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-#ifndef __ASM_ARCH_IO_H
-#define __ASM_ARCH_IO_H
-
-#define IO_SPACE_LIMIT 0xffffffff /* XXX */
-
-#define __io(a) __typesafe_io(a)
-#define __mem_pci(a) (a)
-#define __mem_isa(a) (IO_BASE + (a))
-
-#endif /* ifndef __ASM_ARCH_IO_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/irqs.h b/arch/arm/mach-ns9xxx/include/mach/irqs.h
deleted file mode 100644
index 1348394..0000000
--- a/arch/arm/mach-ns9xxx/include/mach/irqs.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * arch/arm/mach-ns9xxx/include/mach/irqs.h
- *
- * Copyright (C) 2006,2007 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-#ifndef __ASM_ARCH_IRQS_H
-#define __ASM_ARCH_IRQS_H
-
-/* NetSilicon 9360 */
-#define IRQ_NS9XXX_WATCHDOG 0
-#define IRQ_NS9XXX_AHBBUSERR 1
-#define IRQ_NS9360_BBUSAGG 2
-/* irq 3 is reserved for NS9360 */
-#define IRQ_NS9XXX_ETHRX 4
-#define IRQ_NS9XXX_ETHTX 5
-#define IRQ_NS9XXX_ETHPHY 6
-#define IRQ_NS9360_LCD 7
-#define IRQ_NS9360_SERBRX 8
-#define IRQ_NS9360_SERBTX 9
-#define IRQ_NS9360_SERARX 10
-#define IRQ_NS9360_SERATX 11
-#define IRQ_NS9360_SERCRX 12
-#define IRQ_NS9360_SERCTX 13
-#define IRQ_NS9360_I2C 14
-#define IRQ_NS9360_BBUSDMA 15
-#define IRQ_NS9360_TIMER0 16
-#define IRQ_NS9360_TIMER1 17
-#define IRQ_NS9360_TIMER2 18
-#define IRQ_NS9360_TIMER3 19
-#define IRQ_NS9360_TIMER4 20
-#define IRQ_NS9360_TIMER5 21
-#define IRQ_NS9360_TIMER6 22
-#define IRQ_NS9360_TIMER7 23
-#define IRQ_NS9360_RTC 24
-#define IRQ_NS9360_USBHOST 25
-#define IRQ_NS9360_USBDEVICE 26
-#define IRQ_NS9360_IEEE1284 27
-#define IRQ_NS9XXX_EXT0 28
-#define IRQ_NS9XXX_EXT1 29
-#define IRQ_NS9XXX_EXT2 30
-#define IRQ_NS9XXX_EXT3 31
-
-#define BBUS_IRQ(irq) (32 + irq)
-
-#define IRQ_BBUS_DMA BBUS_IRQ(0)
-#define IRQ_BBUS_SERBRX BBUS_IRQ(2)
-#define IRQ_BBUS_SERBTX BBUS_IRQ(3)
-#define IRQ_BBUS_SERARX BBUS_IRQ(4)
-#define IRQ_BBUS_SERATX BBUS_IRQ(5)
-#define IRQ_BBUS_SERCRX BBUS_IRQ(6)
-#define IRQ_BBUS_SERCTX BBUS_IRQ(7)
-#define IRQ_BBUS_SERDRX BBUS_IRQ(8)
-#define IRQ_BBUS_SERDTX BBUS_IRQ(9)
-#define IRQ_BBUS_I2C BBUS_IRQ(10)
-#define IRQ_BBUS_1284 BBUS_IRQ(11)
-#define IRQ_BBUS_UTIL BBUS_IRQ(12)
-#define IRQ_BBUS_RTC BBUS_IRQ(13)
-#define IRQ_BBUS_USBHST BBUS_IRQ(14)
-#define IRQ_BBUS_USBDEV BBUS_IRQ(15)
-#define IRQ_BBUS_AHBDMA1 BBUS_IRQ(24)
-#define IRQ_BBUS_AHBDMA2 BBUS_IRQ(25)
-
-/*
- * these Interrupts are specific for the a9m9750dev board.
- * They are generated by an FPGA that interrupts the CPU on
- * IRQ_NS9360_EXT2
- */
-#define FPGA_IRQ(irq) (64 + irq)
-
-#define IRQ_FPGA_UARTA FPGA_IRQ(0)
-#define IRQ_FPGA_UARTB FPGA_IRQ(1)
-#define IRQ_FPGA_UARTC FPGA_IRQ(2)
-#define IRQ_FPGA_UARTD FPGA_IRQ(3)
-#define IRQ_FPGA_TOUCH FPGA_IRQ(4)
-#define IRQ_FPGA_CF FPGA_IRQ(5)
-#define IRQ_FPGA_CAN0 FPGA_IRQ(6)
-#define IRQ_FPGA_CAN1 FPGA_IRQ(7)
-
-#define NR_IRQS 72
-
-#endif /* __ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/memory.h b/arch/arm/mach-ns9xxx/include/mach/memory.h
deleted file mode 100644
index 5c65aee..0000000
--- a/arch/arm/mach-ns9xxx/include/mach/memory.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * arch/arm/mach-ns9xxx/include/mach/memory.h
- *
- * Copyright (C) 2006 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
-*/
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
-
-/* x in [0..3] */
-#define NS9XXX_CSxSTAT_PHYS(x) UL(((x) + 4) << 28)
-
-#define NS9XXX_CS0STAT_LENGTH UL(0x1000)
-#define NS9XXX_CS1STAT_LENGTH UL(0x1000)
-#define NS9XXX_CS2STAT_LENGTH UL(0x1000)
-#define NS9XXX_CS3STAT_LENGTH UL(0x1000)
-
-#define PLAT_PHYS_OFFSET UL(0x00000000)
-
-#endif
diff --git a/arch/arm/mach-ns9xxx/include/mach/module.h b/arch/arm/mach-ns9xxx/include/mach/module.h
deleted file mode 100644
index 628e975..0000000
--- a/arch/arm/mach-ns9xxx/include/mach/module.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * arch/arm/mach-ns9xxx/include/mach/module.h
- *
- * Copyright (C) 2007 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-#ifndef __ASM_ARCH_MODULE_H
-#define __ASM_ARCH_MODULE_H
-
-#include <asm/mach-types.h>
-
-#define module_is_cc7ucamry() (0 \
- || machine_is_cc7ucamry() \
- )
-
-#define module_is_cc9c() (0 \
- )
-
-#define module_is_cc9p9210() (0 \
- || machine_is_cc9p9210() \
- || machine_is_cc9p9210js() \
- )
-
-#define module_is_cc9p9215() (0 \
- || machine_is_cc9p9215() \
- || machine_is_cc9p9215js() \
- )
-
-#define module_is_cc9p9360() (0 \
- || machine_is_cc9p9360dev() \
- || machine_is_cc9p9360js() \
- )
-
-#define module_is_cc9p9750() (0 \
- || machine_is_a9m9750() \
- || machine_is_cc9p9750js() \
- || machine_is_cc9p9750val() \
- )
-
-#define module_is_ccw9c() (0 \
- )
-
-#define module_is_inc20otter() (0 \
- || machine_is_inc20otter() \
- )
-
-#define module_is_otter() (0 \
- || machine_is_otter() \
- )
-
-#endif /* ifndef __ASM_ARCH_MODULE_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/processor-ns9360.h b/arch/arm/mach-ns9xxx/include/mach/processor-ns9360.h
deleted file mode 100644
index f41deda..0000000
--- a/arch/arm/mach-ns9xxx/include/mach/processor-ns9360.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * arch/arm/mach-ns9xxx/include/mach/processor-ns9360.h
- *
- * Copyright (C) 2007 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-#ifndef __ASM_ARCH_PROCESSORNS9360_H
-#define __ASM_ARCH_PROCESSORNS9360_H
-
-#include <linux/init.h>
-
-void ns9360_reset(char mode);
-
-unsigned long ns9360_systemclock(void) __attribute__((const));
-
-static inline unsigned long ns9360_cpuclock(void) __attribute__((const));
-static inline unsigned long ns9360_cpuclock(void)
-{
- return ns9360_systemclock() / 2;
-}
-
-void __init ns9360_map_io(void);
-
-extern struct sys_timer ns9360_timer;
-
-int ns9360_gpio_configure(unsigned gpio, int inv, int func);
-
-#endif /* ifndef __ASM_ARCH_PROCESSORNS9360_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/processor.h b/arch/arm/mach-ns9xxx/include/mach/processor.h
deleted file mode 100644
index 9f77f74..0000000
--- a/arch/arm/mach-ns9xxx/include/mach/processor.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * arch/arm/mach-ns9xxx/include/mach/processor.h
- *
- * Copyright (C) 2006,2007 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-#ifndef __ASM_ARCH_PROCESSOR_H
-#define __ASM_ARCH_PROCESSOR_H
-
-#include <mach/module.h>
-
-#define processor_is_ns9210() (0 \
- || module_is_cc7ucamry() \
- || module_is_cc9p9210() \
- || module_is_inc20otter() \
- || module_is_otter() \
- )
-
-#define processor_is_ns9215() (0 \
- || module_is_cc9p9215() \
- )
-
-#define processor_is_ns9360() (0 \
- || module_is_cc9p9360() \
- || module_is_cc9c() \
- || module_is_ccw9c() \
- )
-
-#define processor_is_ns9750() (0 \
- || module_is_cc9p9750() \
- )
-
-#define processor_is_ns921x() (0 \
- || processor_is_ns9210() \
- || processor_is_ns9215() \
- )
-
-#endif /* ifndef __ASM_ARCH_PROCESSOR_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/regs-bbu.h b/arch/arm/mach-ns9xxx/include/mach/regs-bbu.h
deleted file mode 100644
index af227c0..0000000
--- a/arch/arm/mach-ns9xxx/include/mach/regs-bbu.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * arch/arm/mach-ns9xxx/include/mach/regs-bbu.h
- *
- * Copyright (C) 2006 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-#ifndef __ASM_ARCH_REGSBBU_H
-#define __ASM_ARCH_REGSBBU_H
-
-#include <mach/hardware.h>
-
-/* BBus Utility */
-
-/* GPIO Configuration Registers block 1 */
-/* NOTE: the HRM starts counting at 1 for the GPIO registers, here the start is
- * at 0 for each block. That is, BBU_GCONFb1(0) is GPIO Configuration Register
- * #1, BBU_GCONFb2(0) is GPIO Configuration Register #8. */
-#define BBU_GCONFb1(x) __REG2(0x90600010, (x))
-#define BBU_GCONFb2(x) __REG2(0x90600100, (x))
-
-#define BBU_GCONFx_DIR(m) __REGBIT(3 + (((m) & 7) << 2))
-#define BBU_GCONFx_DIR_INPUT(m) __REGVAL(BBU_GCONFx_DIR(m), 0)
-#define BBU_GCONFx_DIR_OUTPUT(m) __REGVAL(BBU_GCONFx_DIR(m), 1)
-#define BBU_GCONFx_INV(m) __REGBIT(2 + (((m) & 7) << 2))
-#define BBU_GCONFx_INV_NO(m) __REGVAL(BBU_GCONFx_INV(m), 0)
-#define BBU_GCONFx_INV_YES(m) __REGVAL(BBU_GCONFx_INV(m), 1)
-#define BBU_GCONFx_FUNC(m) __REGBITS(1 + (((m) & 7) << 2), ((m) & 7) << 2)
-#define BBU_GCONFx_FUNC_0(m) __REGVAL(BBU_GCONFx_FUNC(m), 0)
-#define BBU_GCONFx_FUNC_1(m) __REGVAL(BBU_GCONFx_FUNC(m), 1)
-#define BBU_GCONFx_FUNC_2(m) __REGVAL(BBU_GCONFx_FUNC(m), 2)
-#define BBU_GCONFx_FUNC_3(m) __REGVAL(BBU_GCONFx_FUNC(m), 3)
-
-#define BBU_GCTRL1 __REG(0x90600030)
-#define BBU_GCTRL2 __REG(0x90600034)
-#define BBU_GCTRL3 __REG(0x90600120)
-
-#define BBU_GSTAT1 __REG(0x90600040)
-#define BBU_GSTAT2 __REG(0x90600044)
-#define BBU_GSTAT3 __REG(0x90600130)
-
-#endif /* ifndef __ASM_ARCH_REGSBBU_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/regs-board-a9m9750dev.h b/arch/arm/mach-ns9xxx/include/mach/regs-board-a9m9750dev.h
deleted file mode 100644
index cd15936..0000000
--- a/arch/arm/mach-ns9xxx/include/mach/regs-board-a9m9750dev.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * arch/arm/mach-ns9xxx/include/mach/regs-board-a9m9750dev.h
- *
- * Copyright (C) 2006 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-#ifndef __ASM_ARCH_REGSBOARDA9M9750_H
-#define __ASM_ARCH_REGSBOARDA9M9750_H
-
-#include <mach/hardware.h>
-
-#define FPGA_UARTA_BASE io_p2v(NS9XXX_CSxSTAT_PHYS(0))
-#define FPGA_UARTB_BASE io_p2v(NS9XXX_CSxSTAT_PHYS(0) + 0x08)
-#define FPGA_UARTC_BASE io_p2v(NS9XXX_CSxSTAT_PHYS(0) + 0x10)
-#define FPGA_UARTD_BASE io_p2v(NS9XXX_CSxSTAT_PHYS(0) + 0x18)
-
-#define FPGA_IER __REG(NS9XXX_CSxSTAT_PHYS(0) + 0x50)
-#define FPGA_ISR __REG(NS9XXX_CSxSTAT_PHYS(0) + 0x60)
-
-#endif /* ifndef __ASM_ARCH_REGSBOARDA9M9750_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/regs-mem.h b/arch/arm/mach-ns9xxx/include/mach/regs-mem.h
deleted file mode 100644
index f1625bf..0000000
--- a/arch/arm/mach-ns9xxx/include/mach/regs-mem.h
+++ /dev/null
@@ -1,135 +0,0 @@
-/*
- * arch/arm/mach-ns9xxx/include/mach/regs-mem.h
- *
- * Copyright (C) 2006 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-#ifndef __ASM_ARCH_REGSMEM_H
-#define __ASM_ARCH_REGSMEM_H
-
-#include <mach/hardware.h>
-
-/* Memory Module */
-
-/* Control register */
-#define MEM_CTRL __REG(0xa0700000)
-
-/* Status register */
-#define MEM_STAT __REG(0xa0700004)
-
-/* Configuration register */
-#define MEM_CONF __REG(0xa0700008)
-
-/* Dynamic Memory Control register */
-#define MEM_DMCTRL __REG(0xa0700020)
-
-/* Dynamic Memory Refresh Timer */
-#define MEM_DMRT __REG(0xa0700024)
-
-/* Dynamic Memory Read Configuration register */
-#define MEM_DMRC __REG(0xa0700028)
-
-/* Dynamic Memory Precharge Command Period (tRP) */
-#define MEM_DMPCP __REG(0xa0700030)
-
-/* Dynamic Memory Active to Precharge Command Period (tRAS) */
-#define MEM_DMAPCP __REG(0xa0700034)
-
-/* Dynamic Memory Self-Refresh Exit Time (tSREX) */
-#define MEM_DMSRET __REG(0xa0700038)
-
-/* Dynamic Memory Last Data Out to Active Time (tAPR) */
-#define MEM_DMLDOAT __REG(0xa070003c)
-
-/* Dynamic Memory Data-in to Active Command Time (tDAL or TAPW) */
-#define MEM_DMDIACT __REG(0xa0700040)
-
-/* Dynamic Memory Write Recovery Time (tWR, tDPL, tRWL, tRDL) */
-#define MEM_DMWRT __REG(0xa0700044)
-
-/* Dynamic Memory Active to Active Command Period (tRC) */
-#define MEM_DMAACP __REG(0xa0700048)
-
-/* Dynamic Memory Auto Refresh Period, and Auto Refresh to Active Command Period (tRFC) */
-#define MEM_DMARP __REG(0xa070004c)
-
-/* Dynamic Memory Exit Self-Refresh to Active Command (tXSR) */
-#define MEM_DMESRAC __REG(0xa0700050)
-
-/* Dynamic Memory Active Bank A to Active B Time (tRRD) */
-#define MEM_DMABAABT __REG(0xa0700054)
-
-/* Dynamic Memory Load Mode register to Active Command Time (tMRD) */
-#define MEM_DMLMACT __REG(0xa0700058)
-
-/* Static Memory Extended Wait */
-#define MEM_SMEW __REG(0xa0700080)
-
-/* Dynamic Memory Configuration Register x */
-#define MEM_DMCONF(x) __REG2(0xa0700100, (x) << 3)
-
-/* Dynamic Memory RAS and CAS Delay x */
-#define MEM_DMRCD(x) __REG2(0xa0700104, (x) << 3)
-
-/* Static Memory Configuration Register x */
-#define MEM_SMC(x) __REG2(0xa0700200, (x) << 3)
-
-/* Static Memory Configuration Register x: Write protect */
-#define MEM_SMC_PSMC __REGBIT(20)
-#define MEM_SMC_PSMC_OFF __REGVAL(MEM_SMC_PSMC, 0)
-#define MEM_SMC_PSMC_ON __REGVAL(MEM_SMC_PSMC, 1)
-
-/* Static Memory Configuration Register x: Buffer enable */
-#define MEM_SMC_BSMC __REGBIT(19)
-#define MEM_SMC_BSMC_OFF __REGVAL(MEM_SMC_BSMC, 0)
-#define MEM_SMC_BSMC_ON __REGVAL(MEM_SMC_BSMC, 1)
-
-/* Static Memory Configuration Register x: Extended Wait */
-#define MEM_SMC_EW __REGBIT(8)
-#define MEM_SMC_EW_OFF __REGVAL(MEM_SMC_EW, 0)
-#define MEM_SMC_EW_ON __REGVAL(MEM_SMC_EW, 1)
-
-/* Static Memory Configuration Register x: Byte lane state */
-#define MEM_SMC_PB __REGBIT(7)
-#define MEM_SMC_PB_0 __REGVAL(MEM_SMC_PB, 0)
-#define MEM_SMC_PB_1 __REGVAL(MEM_SMC_PB, 1)
-
-/* Static Memory Configuration Register x: Chip select polarity */
-#define MEM_SMC_PC __REGBIT(6)
-#define MEM_SMC_PC_AL __REGVAL(MEM_SMC_PC, 0)
-#define MEM_SMC_PC_AH __REGVAL(MEM_SMC_PC, 1)
-
-/* static memory configuration register x: page mode*/
-#define MEM_SMC_PM __REGBIT(3)
-#define MEM_SMC_PM_DIS __REGVAL(MEM_SMC_PM, 0)
-#define MEM_SMC_PM_ASYNC __REGVAL(MEM_SMC_PM, 1)
-
-/* static memory configuration register x: Memory width */
-#define MEM_SMC_MW __REGBITS(1, 0)
-#define MEM_SMC_MW_8 __REGVAL(MEM_SMC_MW, 0)
-#define MEM_SMC_MW_16 __REGVAL(MEM_SMC_MW, 1)
-#define MEM_SMC_MW_32 __REGVAL(MEM_SMC_MW, 2)
-
-/* Static Memory Write Enable Delay x */
-#define MEM_SMWED(x) __REG2(0xa0700204, (x) << 3)
-
-/* Static Memory Output Enable Delay x */
-#define MEM_SMOED(x) __REG2(0xa0700208, (x) << 3)
-
-/* Static Memory Read Delay x */
-#define MEM_SMRD(x) __REG2(0xa070020c, (x) << 3)
-
-/* Static Memory Page Mode Read Delay 0 */
-#define MEM_SMPMRD(x) __REG2(0xa0700210, (x) << 3)
-
-/* Static Memory Write Delay */
-#define MEM_SMWD(x) __REG2(0xa0700214, (x) << 3)
-
-/* Static Memory Turn Round Delay x */
-#define MEM_SWT(x) __REG2(0xa0700218, (x) << 3)
-
-#endif /* ifndef __ASM_ARCH_REGSMEM_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/regs-sys-common.h b/arch/arm/mach-ns9xxx/include/mach/regs-sys-common.h
deleted file mode 100644
index 14f91df..0000000
--- a/arch/arm/mach-ns9xxx/include/mach/regs-sys-common.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * arch/arm/mach-ns9xxx/include/mach/regs-sys-common.h
- *
- * Copyright (C) 2007 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_REGSSYSCOMMON_H
-#define __ASM_ARCH_REGSSYSCOMMON_H
-#include <mach/hardware.h>
-
-/* Interrupt Vector Address Register Level x */
-#define SYS_IVA(x) __REG2(0xa09000c4, (x))
-
-/* Interrupt Configuration registers */
-#define SYS_IC(x) __REG2(0xa0900144, (x))
-
-/* ISRADDR */
-#define SYS_ISRADDR __REG(0xa0900164)
-
-/* Interrupt Status Active */
-#define SYS_ISA __REG(0xa0900168)
-
-/* Interrupt Status Raw */
-#define SYS_ISR __REG(0xa090016c)
-
-#endif /* ifndef __ASM_ARCH_REGSSYSCOMMON_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/regs-sys-ns9360.h b/arch/arm/mach-ns9xxx/include/mach/regs-sys-ns9360.h
deleted file mode 100644
index 8ff254d..0000000
--- a/arch/arm/mach-ns9xxx/include/mach/regs-sys-ns9360.h
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * arch/arm/mach-ns9xxx/include/mach/regs-sys-ns9360.h
- *
- * Copyright (C) 2006,2007 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-#ifndef __ASM_ARCH_REGSSYSNS9360_H
-#define __ASM_ARCH_REGSSYSNS9360_H
-
-#include <mach/hardware.h>
-
-/* System Control Module */
-
-/* AHB Arbiter Gen Configuration */
-#define SYS_AHBAGENCONF __REG(0xa0900000)
-
-/* BRC */
-#define SYS_BRC(x) __REG2(0xa0900004, (x))
-
-/* Timer x Reload Count register */
-#define SYS_TRC(x) __REG2(0xa0900044, (x))
-
-/* Timer x Read register */
-#define SYS_TR(x) __REG2(0xa0900084, (x))
-
-/* Timer Interrupt Status register */
-#define SYS_TIS __REG(0xa0900170)
-
-/* PLL Configuration register */
-#define SYS_PLL __REG(0xa0900188)
-
-/* PLL FS status */
-#define SYS_PLL_FS __REGBITS(24, 23)
-
-/* PLL ND status */
-#define SYS_PLL_ND __REGBITS(20, 16)
-
-/* PLL Configuration register: PLL SW change */
-#define SYS_PLL_SWC __REGBIT(15)
-#define SYS_PLL_SWC_NO __REGVAL(SYS_PLL_SWC, 0)
-#define SYS_PLL_SWC_YES __REGVAL(SYS_PLL_SWC, 1)
-
-/* Timer x Control register */
-#define SYS_TC(x) __REG2(0xa0900190, (x))
-
-/* Timer x Control register: Timer enable */
-#define SYS_TCx_TEN __REGBIT(15)
-#define SYS_TCx_TEN_DIS __REGVAL(SYS_TCx_TEN, 0)
-#define SYS_TCx_TEN_EN __REGVAL(SYS_TCx_TEN, 1)
-
-/* Timer x Control register: CPU debug mode */
-#define SYS_TCx_TDBG __REGBIT(10)
-#define SYS_TCx_TDBG_CONT __REGVAL(SYS_TCx_TDBG, 0)
-#define SYS_TCx_TDBG_STOP __REGVAL(SYS_TCx_TDBG, 1)
-
-/* Timer x Control register: Interrupt clear */
-#define SYS_TCx_INTC __REGBIT(9)
-#define SYS_TCx_INTC_UNSET __REGVAL(SYS_TCx_INTC, 0)
-#define SYS_TCx_INTC_SET __REGVAL(SYS_TCx_INTC, 1)
-
-/* Timer x Control register: Timer clock select */
-#define SYS_TCx_TLCS __REGBITS(8, 6)
-#define SYS_TCx_TLCS_CPU __REGVAL(SYS_TCx_TLCS, 0) /* CPU clock */
-#define SYS_TCx_TLCS_DIV2 __REGVAL(SYS_TCx_TLCS, 1) /* CPU clock / 2 */
-#define SYS_TCx_TLCS_DIV4 __REGVAL(SYS_TCx_TLCS, 2) /* CPU clock / 4 */
-#define SYS_TCx_TLCS_DIV8 __REGVAL(SYS_TCx_TLCS, 3) /* CPU clock / 8 */
-#define SYS_TCx_TLCS_DIV16 __REGVAL(SYS_TCx_TLCS, 4) /* CPU clock / 16 */
-#define SYS_TCx_TLCS_DIV32 __REGVAL(SYS_TCx_TLCS, 5) /* CPU clock / 32 */
-#define SYS_TCx_TLCS_DIV64 __REGVAL(SYS_TCx_TLCS, 6) /* CPU clock / 64 */
-#define SYS_TCx_TLCS_EXT __REGVAL(SYS_TCx_TLCS, 7)
-
-/* Timer x Control register: Timer mode */
-#define SYS_TCx_TM __REGBITS(5, 4)
-#define SYS_TCx_TM_IEE __REGVAL(SYS_TCx_TM, 0) /* Internal timer or external event */
-#define SYS_TCx_TM_ELL __REGVAL(SYS_TCx_TM, 1) /* External low-level, gated timer */
-#define SYS_TCx_TM_EHL __REGVAL(SYS_TCx_TM, 2) /* External high-level, gated timer */
-#define SYS_TCx_TM_CONCAT __REGVAL(SYS_TCx_TM, 3) /* Concatenate the lower timer. */
-
-/* Timer x Control register: Interrupt select */
-#define SYS_TCx_INTS __REGBIT(3)
-#define SYS_TCx_INTS_DIS __REGVAL(SYS_TCx_INTS, 0)
-#define SYS_TCx_INTS_EN __REGVAL(SYS_TCx_INTS, 1)
-
-/* Timer x Control register: Up/down select */
-#define SYS_TCx_UDS __REGBIT(2)
-#define SYS_TCx_UDS_UP __REGVAL(SYS_TCx_UDS, 0)
-#define SYS_TCx_UDS_DOWN __REGVAL(SYS_TCx_UDS, 1)
-
-/* Timer x Control register: 32- or 16-bit timer */
-#define SYS_TCx_TSZ __REGBIT(1)
-#define SYS_TCx_TSZ_16 __REGVAL(SYS_TCx_TSZ, 0)
-#define SYS_TCx_TSZ_32 __REGVAL(SYS_TCx_TSZ, 1)
-
-/* Timer x Control register: Reload enable */
-#define SYS_TCx_REN __REGBIT(0)
-#define SYS_TCx_REN_DIS __REGVAL(SYS_TCx_REN, 0)
-#define SYS_TCx_REN_EN __REGVAL(SYS_TCx_REN, 1)
-
-/* System Memory Chip Select x Dynamic Memory Base */
-#define SYS_SMCSDMB(x) __REG2(0xa09001d0, (x) << 1)
-
-/* System Memory Chip Select x Dynamic Memory Mask */
-#define SYS_SMCSDMM(x) __REG2(0xa09001d4, (x) << 1)
-
-/* System Memory Chip Select x Static Memory Base */
-#define SYS_SMCSSMB(x) __REG2(0xa09001f0, (x) << 1)
-
-/* System Memory Chip Select x Static Memory Base: Chip select x base */
-#define SYS_SMCSSMB_CSxB __REGBITS(31, 12)
-
-/* System Memory Chip Select x Static Memory Mask */
-#define SYS_SMCSSMM(x) __REG2(0xa09001f4, (x) << 1)
-
-/* System Memory Chip Select x Static Memory Mask: Chip select x mask */
-#define SYS_SMCSSMM_CSxM __REGBITS(31, 12)
-
-/* System Memory Chip Select x Static Memory Mask: Chip select x enable */
-#define SYS_SMCSSMM_CSEx __REGBIT(0)
-#define SYS_SMCSSMM_CSEx_DIS __REGVAL(SYS_SMCSSMM_CSEx, 0)
-#define SYS_SMCSSMM_CSEx_EN __REGVAL(SYS_SMCSSMM_CSEx, 1)
-
-/* General purpose, user-defined ID register */
-#define SYS_GENID __REG(0xa0900210)
-
-/* External Interrupt x Control register */
-#define SYS_EIC(x) __REG2(0xa0900214, (x))
-
-/* External Interrupt x Control register: Status */
-#define SYS_EIC_STS __REGBIT(3)
-
-/* External Interrupt x Control register: Clear */
-#define SYS_EIC_CLR __REGBIT(2)
-
-/* External Interrupt x Control register: Polarity */
-#define SYS_EIC_PLTY __REGBIT(1)
-#define SYS_EIC_PLTY_AH __REGVAL(SYS_EIC_PLTY, 0)
-#define SYS_EIC_PLTY_AL __REGVAL(SYS_EIC_PLTY, 1)
-
-/* External Interrupt x Control register: Level edge */
-#define SYS_EIC_LVEDG __REGBIT(0)
-#define SYS_EIC_LVEDG_LEVEL __REGVAL(SYS_EIC_LVEDG, 0)
-#define SYS_EIC_LVEDG_EDGE __REGVAL(SYS_EIC_LVEDG, 1)
-
-#endif /* ifndef __ASM_ARCH_REGSSYSNS9360_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/system.h b/arch/arm/mach-ns9xxx/include/mach/system.h
deleted file mode 100644
index 1561588..0000000
--- a/arch/arm/mach-ns9xxx/include/mach/system.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * arch/arm/mach-ns9xxx/include/mach/system.h
- *
- * Copyright (C) 2006,2007 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-#include <asm/proc-fns.h>
-#include <mach/processor.h>
-#include <mach/processor-ns9360.h>
-
-static inline void arch_idle(void)
-{
- cpu_do_idle();
-}
-
-static inline void arch_reset(char mode, const char *cmd)
-{
-#ifdef CONFIG_PROCESSOR_NS9360
- if (processor_is_ns9360())
- ns9360_reset(mode);
- else
-#endif
- BUG();
-
- BUG();
-}
-
-#endif /* ifndef __ASM_ARCH_SYSTEM_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/timex.h b/arch/arm/mach-ns9xxx/include/mach/timex.h
deleted file mode 100644
index 734a8d8..0000000
--- a/arch/arm/mach-ns9xxx/include/mach/timex.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * arch/arm/mach-ns9xxx/include/mach/timex.h
- *
- * Copyright (C) 2005-2006 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-#ifndef __ASM_ARCH_TIMEX_H
-#define __ASM_ARCH_TIMEX_H
-
-/*
- * value for CLOCK_TICK_RATE stolen from arch/arm/mach-s3c2410/include/mach/timex.h.
- * See there for an explanation.
- */
-#define CLOCK_TICK_RATE 12000000
-
-#endif /* ifndef __ASM_ARCH_TIMEX_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/uncompress.h b/arch/arm/mach-ns9xxx/include/mach/uncompress.h
deleted file mode 100644
index 770a68c..0000000
--- a/arch/arm/mach-ns9xxx/include/mach/uncompress.h
+++ /dev/null
@@ -1,164 +0,0 @@
-/*
- * arch/arm/mach-ns9xxx/include/mach/uncompress.h
- *
- * Copyright (C) 2006 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-#ifndef __ASM_ARCH_UNCOMPRESS_H
-#define __ASM_ARCH_UNCOMPRESS_H
-
-#include <linux/io.h>
-
-#define __REG(x) ((void __iomem __force *)(x))
-
-static void putc_dummy(char c, void __iomem *base)
-{
- /* nothing */
-}
-
-static int timeout;
-
-static void putc_ns9360(char c, void __iomem *base)
-{
- do {
- if (timeout)
- --timeout;
-
- if (__raw_readl(base + 8) & (1 << 3)) {
- __raw_writeb(c, base + 16);
- timeout = 0x10000;
- break;
- }
- } while (timeout);
-}
-
-static void putc_a9m9750dev(char c, void __iomem *base)
-{
- do {
- if (timeout)
- --timeout;
-
- if (__raw_readb(base + 5) & (1 << 5)) {
- __raw_writeb(c, base);
- timeout = 0x10000;
- break;
- }
- } while (timeout);
-
-}
-
-static void putc_ns921x(char c, void __iomem *base)
-{
- do {
- if (timeout)
- --timeout;
-
- if (!(__raw_readl(base) & (1 << 11))) {
- __raw_writeb(c, base + 0x0028);
- timeout = 0x10000;
- break;
- }
- } while (timeout);
-}
-
-#define MSCS __REG(0xA0900184)
-
-#define NS9360_UARTA __REG(0x90200040)
-#define NS9360_UARTB __REG(0x90200000)
-#define NS9360_UARTC __REG(0x90300000)
-#define NS9360_UARTD __REG(0x90300040)
-
-#define NS9360_UART_ENABLED(base) \
- (__raw_readl(NS9360_UARTA) & (1 << 31))
-
-#define A9M9750DEV_UARTA __REG(0x40000000)
-
-#define NS921XSYS_CLOCK __REG(0xa090017c)
-#define NS921X_UARTA __REG(0x90010000)
-#define NS921X_UARTB __REG(0x90018000)
-#define NS921X_UARTC __REG(0x90020000)
-#define NS921X_UARTD __REG(0x90028000)
-
-#define NS921X_UART_ENABLED(base) \
- (__raw_readl((base) + 0x1000) & (1 << 29))
-
-static void autodetect(void (**putc)(char, void __iomem *), void __iomem **base)
-{
- timeout = 0x10000;
- if (((__raw_readl(MSCS) >> 16) & 0xfe) == 0x00) {
- /* ns9360 or ns9750 */
- if (NS9360_UART_ENABLED(NS9360_UARTA)) {
- *putc = putc_ns9360;
- *base = NS9360_UARTA;
- return;
- } else if (NS9360_UART_ENABLED(NS9360_UARTB)) {
- *putc = putc_ns9360;
- *base = NS9360_UARTB;
- return;
- } else if (NS9360_UART_ENABLED(NS9360_UARTC)) {
- *putc = putc_ns9360;
- *base = NS9360_UARTC;
- return;
- } else if (NS9360_UART_ENABLED(NS9360_UARTD)) {
- *putc = putc_ns9360;
- *base = NS9360_UARTD;
- return;
- } else if (__raw_readl(__REG(0xa09001f4)) == 0xfffff001) {
- *putc = putc_a9m9750dev;
- *base = A9M9750DEV_UARTA;
- return;
- }
- } else if (((__raw_readl(MSCS) >> 16) & 0xfe) == 0x02) {
- /* ns921x */
- u32 clock = __raw_readl(NS921XSYS_CLOCK);
-
- if ((clock & (1 << 1)) &&
- NS921X_UART_ENABLED(NS921X_UARTA)) {
- *putc = putc_ns921x;
- *base = NS921X_UARTA;
- return;
- } else if ((clock & (1 << 2)) &&
- NS921X_UART_ENABLED(NS921X_UARTB)) {
- *putc = putc_ns921x;
- *base = NS921X_UARTB;
- return;
- } else if ((clock & (1 << 3)) &&
- NS921X_UART_ENABLED(NS921X_UARTC)) {
- *putc = putc_ns921x;
- *base = NS921X_UARTC;
- return;
- } else if ((clock & (1 << 4)) &&
- NS921X_UART_ENABLED(NS921X_UARTD)) {
- *putc = putc_ns921x;
- *base = NS921X_UARTD;
- return;
- }
- }
-
- *putc = putc_dummy;
-}
-
-void (*myputc)(char, void __iomem *);
-void __iomem *base;
-
-static void putc(char c)
-{
- myputc(c, base);
-}
-
-static void arch_decomp_setup(void)
-{
- autodetect(&myputc, &base);
-}
-#define arch_decomp_wdog()
-
-static void flush(void)
-{
- /* nothing */
-}
-
-#endif /* ifndef __ASM_ARCH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-ns9xxx/include/mach/vmalloc.h b/arch/arm/mach-ns9xxx/include/mach/vmalloc.h
deleted file mode 100644
index c865197..0000000
--- a/arch/arm/mach-ns9xxx/include/mach/vmalloc.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * arch/arm/mach-ns9xxx/include/mach/vmalloc.h
- *
- * Copyright (C) 2006 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-#ifndef __ASM_ARCH_VMALLOC_H
-#define __ASM_ARCH_VMALLOC_H
-
-#define VMALLOC_END (0xf0000000UL)
-
-#endif /* ifndef __ASM_ARCH_VMALLOC_H */
diff --git a/arch/arm/mach-ns9xxx/irq.c b/arch/arm/mach-ns9xxx/irq.c
deleted file mode 100644
index 37ab0a2..0000000
--- a/arch/arm/mach-ns9xxx/irq.c
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * arch/arm/mach-ns9xxx/irq.c
- *
- * Copyright (C) 2006,2007 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-#include <linux/interrupt.h>
-#include <linux/kernel_stat.h>
-#include <linux/io.h>
-#include <asm/mach/irq.h>
-#include <mach/regs-sys-common.h>
-#include <mach/irqs.h>
-#include <mach/board.h>
-
-#include "generic.h"
-
-/* simple interrupt prio table: prio(x) < prio(y) <=> x < y */
-#define irq2prio(i) (i)
-#define prio2irq(p) (p)
-
-static void ns9xxx_mask_irq(struct irq_data *d)
-{
- /* XXX: better use cpp symbols */
- int prio = irq2prio(d->irq);
- u32 ic = __raw_readl(SYS_IC(prio / 4));
- ic &= ~(1 << (7 + 8 * (3 - (prio & 3))));
- __raw_writel(ic, SYS_IC(prio / 4));
-}
-
-static void ns9xxx_eoi_irq(struct irq_data *d)
-{
- __raw_writel(0, SYS_ISRADDR);
-}
-
-static void ns9xxx_unmask_irq(struct irq_data *d)
-{
- /* XXX: better use cpp symbols */
- int prio = irq2prio(d->irq);
- u32 ic = __raw_readl(SYS_IC(prio / 4));
- ic |= 1 << (7 + 8 * (3 - (prio & 3)));
- __raw_writel(ic, SYS_IC(prio / 4));
-}
-
-static struct irq_chip ns9xxx_chip = {
- .irq_eoi = ns9xxx_eoi_irq,
- .irq_mask = ns9xxx_mask_irq,
- .irq_unmask = ns9xxx_unmask_irq,
-};
-
-void __init ns9xxx_init_irq(void)
-{
- int i;
-
- /* disable all IRQs */
- for (i = 0; i < 8; ++i)
- __raw_writel(prio2irq(4 * i) << 24 |
- prio2irq(4 * i + 1) << 16 |
- prio2irq(4 * i + 2) << 8 |
- prio2irq(4 * i + 3),
- SYS_IC(i));
-
- for (i = 0; i < 32; ++i)
- __raw_writel(prio2irq(i), SYS_IVA(i));
-
- for (i = 0; i <= 31; ++i) {
- irq_set_chip_and_handler(i, &ns9xxx_chip, handle_fasteoi_irq);
- set_irq_flags(i, IRQF_VALID);
- irq_set_status_flags(i, IRQ_LEVEL);
- }
-}
diff --git a/arch/arm/mach-ns9xxx/mach-cc9p9360dev.c b/arch/arm/mach-ns9xxx/mach-cc9p9360dev.c
deleted file mode 100644
index 2858417..0000000
--- a/arch/arm/mach-ns9xxx/mach-cc9p9360dev.c
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * arch/arm/mach-ns9xxx/mach-cc9p9360dev.c
- *
- * Copyright (C) 2006,2007 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-
-#include <mach/processor-ns9360.h>
-
-#include "board-a9m9750dev.h"
-#include "generic.h"
-
-static void __init mach_cc9p9360dev_map_io(void)
-{
- ns9360_map_io();
- board_a9m9750dev_map_io();
-}
-
-static void __init mach_cc9p9360dev_init_irq(void)
-{
- ns9xxx_init_irq();
- board_a9m9750dev_init_irq();
-}
-
-static void __init mach_cc9p9360dev_init_machine(void)
-{
- ns9xxx_init_machine();
- board_a9m9750dev_init_machine();
-}
-
-MACHINE_START(CC9P9360DEV, "Digi ConnectCore 9P 9360 on an A9M9750 Devboard")
- .map_io = mach_cc9p9360dev_map_io,
- .init_irq = mach_cc9p9360dev_init_irq,
- .init_machine = mach_cc9p9360dev_init_machine,
- .timer = &ns9360_timer,
- .boot_params = 0x100,
-MACHINE_END
diff --git a/arch/arm/mach-ns9xxx/mach-cc9p9360js.c b/arch/arm/mach-ns9xxx/mach-cc9p9360js.c
deleted file mode 100644
index 729f68d..0000000
--- a/arch/arm/mach-ns9xxx/mach-cc9p9360js.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * arch/arm/mach-ns9xxx/mach-cc9p9360js.c
- *
- * Copyright (C) 2006,2007 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-#include <asm/mach/arch.h>
-#include <asm/mach-types.h>
-
-#include <mach/processor-ns9360.h>
-
-#include "board-jscc9p9360.h"
-#include "generic.h"
-
-static void __init mach_cc9p9360js_init_machine(void)
-{
- ns9xxx_init_machine();
- board_jscc9p9360_init_machine();
-}
-
-MACHINE_START(CC9P9360JS, "Digi ConnectCore 9P 9360 on an JSCC9P9360 Devboard")
- .map_io = ns9360_map_io,
- .init_irq = ns9xxx_init_irq,
- .init_machine = mach_cc9p9360js_init_machine,
- .timer = &ns9360_timer,
- .boot_params = 0x100,
-MACHINE_END
diff --git a/arch/arm/mach-ns9xxx/plat-serial8250.c b/arch/arm/mach-ns9xxx/plat-serial8250.c
deleted file mode 100644
index 463e924..0000000
--- a/arch/arm/mach-ns9xxx/plat-serial8250.c
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * arch/arm/mach-ns9xxx/plat-serial8250.c
- *
- * Copyright (C) 2008 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-#include <linux/platform_device.h>
-#include <linux/serial_8250.h>
-#include <linux/slab.h>
-
-#include <mach/regs-board-a9m9750dev.h>
-#include <mach/board.h>
-
-#define DRIVER_NAME "serial8250"
-
-static int __init ns9xxx_plat_serial8250_init(void)
-{
- struct plat_serial8250_port *pdata;
- struct platform_device *pdev;
- int ret = -ENOMEM;
- int i;
-
- if (!board_is_a9m9750dev())
- return -ENODEV;
-
- pdev = platform_device_alloc(DRIVER_NAME, 0);
- if (!pdev)
- goto err;
-
- pdata = kzalloc(5 * sizeof(*pdata), GFP_KERNEL);
- if (!pdata)
- goto err;
-
- pdev->dev.platform_data = pdata;
-
- pdata[0].iobase = FPGA_UARTA_BASE;
- pdata[1].iobase = FPGA_UARTB_BASE;
- pdata[2].iobase = FPGA_UARTC_BASE;
- pdata[3].iobase = FPGA_UARTD_BASE;
-
- for (i = 0; i < 4; ++i) {
- pdata[i].membase = (void __iomem *)pdata[i].iobase;
- pdata[i].mapbase = pdata[i].iobase;
- pdata[i].iotype = UPIO_MEM;
- pdata[i].uartclk = 18432000;
- pdata[i].flags = UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
- }
-
- pdata[0].irq = IRQ_FPGA_UARTA;
- pdata[1].irq = IRQ_FPGA_UARTB;
- pdata[2].irq = IRQ_FPGA_UARTC;
- pdata[3].irq = IRQ_FPGA_UARTD;
-
- ret = platform_device_add(pdev);
- if (ret) {
-err:
- platform_device_put(pdev);
-
- printk(KERN_WARNING "Could not add %s (errno=%d)\n",
- DRIVER_NAME, ret);
- }
-
- return 0;
-}
-
-arch_initcall(ns9xxx_plat_serial8250_init);
diff --git a/arch/arm/mach-ns9xxx/processor-ns9360.c b/arch/arm/mach-ns9xxx/processor-ns9360.c
deleted file mode 100644
index aed1999..0000000
--- a/arch/arm/mach-ns9xxx/processor-ns9360.c
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * arch/arm/mach-ns9xxx/processor-ns9360.c
- *
- * Copyright (C) 2007 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-#include <linux/io.h>
-#include <linux/kernel.h>
-
-#include <asm/page.h>
-#include <asm/mach/map.h>
-#include <mach/processor-ns9360.h>
-#include <mach/regs-sys-ns9360.h>
-
-void ns9360_reset(char mode)
-{
- u32 reg;
-
- reg = __raw_readl(SYS_PLL) >> 16;
- REGSET(reg, SYS_PLL, SWC, YES);
- __raw_writel(reg, SYS_PLL);
-}
-
-#define CRYSTAL 29491200 /* Hz */
-unsigned long ns9360_systemclock(void)
-{
- u32 pll = __raw_readl(SYS_PLL);
- return CRYSTAL * (REGGETIM(pll, SYS_PLL, ND) + 1)
- >> REGGETIM(pll, SYS_PLL, FS);
-}
-
-static struct map_desc ns9360_io_desc[] __initdata = {
- { /* BBus */
- .virtual = io_p2v(0x90000000),
- .pfn = __phys_to_pfn(0x90000000),
- .length = 0x00700000,
- .type = MT_DEVICE,
- }, { /* AHB */
- .virtual = io_p2v(0xa0100000),
- .pfn = __phys_to_pfn(0xa0100000),
- .length = 0x00900000,
- .type = MT_DEVICE,
- },
-};
-
-void __init ns9360_map_io(void)
-{
- iotable_init(ns9360_io_desc, ARRAY_SIZE(ns9360_io_desc));
-}
diff --git a/arch/arm/mach-ns9xxx/time-ns9360.c b/arch/arm/mach-ns9xxx/time-ns9360.c
deleted file mode 100644
index 9ca32f5..0000000
--- a/arch/arm/mach-ns9xxx/time-ns9360.c
+++ /dev/null
@@ -1,181 +0,0 @@
-/*
- * arch/arm/mach-ns9xxx/time-ns9360.c
- *
- * Copyright (C) 2006,2007 by Digi International Inc.
- * All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- */
-#include <linux/jiffies.h>
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/stringify.h>
-#include <linux/clocksource.h>
-#include <linux/clockchips.h>
-
-#include <mach/processor-ns9360.h>
-#include <mach/regs-sys-ns9360.h>
-#include <mach/irqs.h>
-#include <mach/system.h>
-#include "generic.h"
-
-#define TIMER_CLOCKSOURCE 0
-#define TIMER_CLOCKEVENT 1
-static u32 latch;
-
-static cycle_t ns9360_clocksource_read(struct clocksource *cs)
-{
- return __raw_readl(SYS_TR(TIMER_CLOCKSOURCE));
-}
-
-static struct clocksource ns9360_clocksource = {
- .name = "ns9360-timer" __stringify(TIMER_CLOCKSOURCE),
- .rating = 300,
- .read = ns9360_clocksource_read,
- .mask = CLOCKSOURCE_MASK(32),
- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
-static void ns9360_clockevent_setmode(enum clock_event_mode mode,
- struct clock_event_device *clk)
-{
- u32 tc = __raw_readl(SYS_TC(TIMER_CLOCKEVENT));
-
- switch (mode) {
- case CLOCK_EVT_MODE_PERIODIC:
- __raw_writel(latch, SYS_TRC(TIMER_CLOCKEVENT));
- REGSET(tc, SYS_TCx, REN, EN);
- REGSET(tc, SYS_TCx, INTS, EN);
- REGSET(tc, SYS_TCx, TEN, EN);
- break;
-
- case CLOCK_EVT_MODE_ONESHOT:
- REGSET(tc, SYS_TCx, REN, DIS);
- REGSET(tc, SYS_TCx, INTS, EN);
-
- /* fall through */
-
- case CLOCK_EVT_MODE_UNUSED:
- case CLOCK_EVT_MODE_SHUTDOWN:
- case CLOCK_EVT_MODE_RESUME:
- default:
- REGSET(tc, SYS_TCx, TEN, DIS);
- break;
- }
-
- __raw_writel(tc, SYS_TC(TIMER_CLOCKEVENT));
-}
-
-static int ns9360_clockevent_setnextevent(unsigned long evt,
- struct clock_event_device *clk)
-{
- u32 tc = __raw_readl(SYS_TC(TIMER_CLOCKEVENT));
-
- if (REGGET(tc, SYS_TCx, TEN)) {
- REGSET(tc, SYS_TCx, TEN, DIS);
- __raw_writel(tc, SYS_TC(TIMER_CLOCKEVENT));
- }
-
- REGSET(tc, SYS_TCx, TEN, EN);
-
- __raw_writel(evt, SYS_TRC(TIMER_CLOCKEVENT));
-
- __raw_writel(tc, SYS_TC(TIMER_CLOCKEVENT));
-
- return 0;
-}
-
-static struct clock_event_device ns9360_clockevent_device = {
- .name = "ns9360-timer" __stringify(TIMER_CLOCKEVENT),
- .shift = 20,
- .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
- .set_mode = ns9360_clockevent_setmode,
- .set_next_event = ns9360_clockevent_setnextevent,
-};
-
-static irqreturn_t ns9360_clockevent_handler(int irq, void *dev_id)
-{
- int timerno = irq - IRQ_NS9360_TIMER0;
- u32 tc;
-
- struct clock_event_device *evt = &ns9360_clockevent_device;
-
- /* clear irq */
- tc = __raw_readl(SYS_TC(timerno));
- if (REGGET(tc, SYS_TCx, REN) == SYS_TCx_REN_DIS) {
- REGSET(tc, SYS_TCx, TEN, DIS);
- __raw_writel(tc, SYS_TC(timerno));
- }
- REGSET(tc, SYS_TCx, INTC, SET);
- __raw_writel(tc, SYS_TC(timerno));
- REGSET(tc, SYS_TCx, INTC, UNSET);
- __raw_writel(tc, SYS_TC(timerno));
-
- evt->event_handler(evt);
-
- return IRQ_HANDLED;
-}
-
-static struct irqaction ns9360_clockevent_action = {
- .name = "ns9360-timer" __stringify(TIMER_CLOCKEVENT),
- .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
- .handler = ns9360_clockevent_handler,
-};
-
-static void __init ns9360_timer_init(void)
-{
- int tc;
-
- tc = __raw_readl(SYS_TC(TIMER_CLOCKSOURCE));
- if (REGGET(tc, SYS_TCx, TEN)) {
- REGSET(tc, SYS_TCx, TEN, DIS);
- __raw_writel(tc, SYS_TC(TIMER_CLOCKSOURCE));
- }
-
- __raw_writel(0, SYS_TRC(TIMER_CLOCKSOURCE));
-
- REGSET(tc, SYS_TCx, TEN, EN);
- REGSET(tc, SYS_TCx, TDBG, STOP);
- REGSET(tc, SYS_TCx, TLCS, CPU);
- REGSET(tc, SYS_TCx, TM, IEE);
- REGSET(tc, SYS_TCx, INTS, DIS);
- REGSET(tc, SYS_TCx, UDS, UP);
- REGSET(tc, SYS_TCx, TSZ, 32);
- REGSET(tc, SYS_TCx, REN, EN);
-
- __raw_writel(tc, SYS_TC(TIMER_CLOCKSOURCE));
-
- clocksource_register_hz(&ns9360_clocksource, ns9360_cpuclock());
-
- latch = SH_DIV(ns9360_cpuclock(), HZ, 0);
-
- tc = __raw_readl(SYS_TC(TIMER_CLOCKEVENT));
- REGSET(tc, SYS_TCx, TEN, DIS);
- REGSET(tc, SYS_TCx, TDBG, STOP);
- REGSET(tc, SYS_TCx, TLCS, CPU);
- REGSET(tc, SYS_TCx, TM, IEE);
- REGSET(tc, SYS_TCx, INTS, DIS);
- REGSET(tc, SYS_TCx, UDS, DOWN);
- REGSET(tc, SYS_TCx, TSZ, 32);
- REGSET(tc, SYS_TCx, REN, EN);
- __raw_writel(tc, SYS_TC(TIMER_CLOCKEVENT));
-
- ns9360_clockevent_device.mult = div_sc(ns9360_cpuclock(),
- NSEC_PER_SEC, ns9360_clockevent_device.shift);
- ns9360_clockevent_device.max_delta_ns =
- clockevent_delta2ns(-1, &ns9360_clockevent_device);
- ns9360_clockevent_device.min_delta_ns =
- clockevent_delta2ns(1, &ns9360_clockevent_device);
-
- ns9360_clockevent_device.cpumask = cpumask_of(0);
- clockevents_register_device(&ns9360_clockevent_device);
-
- setup_irq(IRQ_NS9360_TIMER0 + TIMER_CLOCKEVENT,
- &ns9360_clockevent_action);
-}
-
-struct sys_timer ns9360_timer = {
- .init = ns9360_timer_init,
-};
diff --git a/arch/arm/mach-nuc93x/include/mach/uncompress.h b/arch/arm/mach-nuc93x/include/mach/uncompress.h
index 73082cd..381cb9b 100644
--- a/arch/arm/mach-nuc93x/include/mach/uncompress.h
+++ b/arch/arm/mach-nuc93x/include/mach/uncompress.h
@@ -27,7 +27,7 @@
#define arch_decomp_wdog()
#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE)
-static u32 * uart_base = (u32 *)UART0_PA;
+static u32 * const uart_base = (u32 *)UART0_PA;
static void putc(int ch)
{
diff --git a/arch/arm/mach-omap1/flash.c b/arch/arm/mach-omap1/flash.c
index acd1616..1749cb3 100644
--- a/arch/arm/mach-omap1/flash.c
+++ b/arch/arm/mach-omap1/flash.c
@@ -13,7 +13,7 @@
#include <plat/tc.h>
#include <plat/flash.h>
-void omap1_set_vpp(struct map_info *map, int enable)
+void omap1_set_vpp(struct platform_device *pdev, int enable)
{
static int count;
u32 l;
diff --git a/arch/arm/mach-omap1/time.c b/arch/arm/mach-omap1/time.c
index 6885d2f..03e1e10 100644
--- a/arch/arm/mach-omap1/time.c
+++ b/arch/arm/mach-omap1/time.c
@@ -68,49 +68,50 @@
} omap_mpu_timer_regs_t;
#define omap_mpu_timer_base(n) \
-((volatile omap_mpu_timer_regs_t*)OMAP1_IO_ADDRESS(OMAP_MPU_TIMER_BASE + \
+((omap_mpu_timer_regs_t __iomem *)OMAP1_IO_ADDRESS(OMAP_MPU_TIMER_BASE + \
(n)*OMAP_MPU_TIMER_OFFSET))
static inline unsigned long notrace omap_mpu_timer_read(int nr)
{
- volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);
- return timer->read_tim;
+ omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr);
+ return readl(&timer->read_tim);
}
static inline void omap_mpu_set_autoreset(int nr)
{
- volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);
+ omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr);
- timer->cntl = timer->cntl | MPU_TIMER_AR;
+ writel(readl(&timer->cntl) | MPU_TIMER_AR, &timer->cntl);
}
static inline void omap_mpu_remove_autoreset(int nr)
{
- volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);
+ omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr);
- timer->cntl = timer->cntl & ~MPU_TIMER_AR;
+ writel(readl(&timer->cntl) & ~MPU_TIMER_AR, &timer->cntl);
}
static inline void omap_mpu_timer_start(int nr, unsigned long load_val,
int autoreset)
{
- volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);
- unsigned int timerflags = (MPU_TIMER_CLOCK_ENABLE | MPU_TIMER_ST);
+ omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr);
+ unsigned int timerflags = MPU_TIMER_CLOCK_ENABLE | MPU_TIMER_ST;
- if (autoreset) timerflags |= MPU_TIMER_AR;
+ if (autoreset)
+ timerflags |= MPU_TIMER_AR;
- timer->cntl = MPU_TIMER_CLOCK_ENABLE;
+ writel(MPU_TIMER_CLOCK_ENABLE, &timer->cntl);
udelay(1);
- timer->load_tim = load_val;
+ writel(load_val, &timer->load_tim);
udelay(1);
- timer->cntl = timerflags;
+ writel(timerflags, &timer->cntl);
}
static inline void omap_mpu_timer_stop(int nr)
{
- volatile omap_mpu_timer_regs_t* timer = omap_mpu_timer_base(nr);
+ omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(nr);
- timer->cntl &= ~MPU_TIMER_ST;
+ writel(readl(&timer->cntl) & ~MPU_TIMER_ST, &timer->cntl);
}
/*
@@ -189,38 +190,11 @@
* ---------------------------------------------------------------------------
*/
-static unsigned long omap_mpu_timer2_overflows;
-
-static irqreturn_t omap_mpu_timer2_interrupt(int irq, void *dev_id)
-{
- omap_mpu_timer2_overflows++;
- return IRQ_HANDLED;
-}
-
-static struct irqaction omap_mpu_timer2_irq = {
- .name = "mpu_timer2",
- .flags = IRQF_DISABLED,
- .handler = omap_mpu_timer2_interrupt,
-};
-
-static cycle_t mpu_read(struct clocksource *cs)
-{
- return ~omap_mpu_timer_read(1);
-}
-
-static struct clocksource clocksource_mpu = {
- .name = "mpu_timer2",
- .rating = 300,
- .read = mpu_read,
- .mask = CLOCKSOURCE_MASK(32),
- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
static DEFINE_CLOCK_DATA(cd);
static inline unsigned long long notrace _omap_mpu_sched_clock(void)
{
- u32 cyc = mpu_read(&clocksource_mpu);
+ u32 cyc = ~omap_mpu_timer_read(1);
return cyc_to_sched_clock(&cd, cyc, (u32)~0);
}
@@ -238,21 +212,22 @@
static void notrace mpu_update_sched_clock(void)
{
- u32 cyc = mpu_read(&clocksource_mpu);
+ u32 cyc = ~omap_mpu_timer_read(1);
update_sched_clock(&cd, cyc, (u32)~0);
}
static void __init omap_init_clocksource(unsigned long rate)
{
+ omap_mpu_timer_regs_t __iomem *timer = omap_mpu_timer_base(1);
static char err[] __initdata = KERN_ERR
"%s: can't register clocksource!\n";
- setup_irq(INT_TIMER2, &omap_mpu_timer2_irq);
omap_mpu_timer_start(1, ~0, 1);
init_sched_clock(&cd, mpu_update_sched_clock, 32, rate);
- if (clocksource_register_hz(&clocksource_mpu, rate))
- printk(err, clocksource_mpu.name);
+ if (clocksource_mmio_init(&timer->read_tim, "mpu_timer2", rate,
+ 300, 32, clocksource_mmio_readl_down))
+ printk(err, "mpu_timer2");
}
static void __init omap_mpu_timer_init(void)
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
index 9afd087..23244cd 100644
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ b/arch/arm/mach-omap2/board-3430sdp.c
@@ -37,8 +37,8 @@
#include <plat/common.h>
#include <plat/dma.h>
#include <plat/gpmc.h>
-#include <plat/display.h>
-#include <plat/panel-generic-dpi.h>
+#include <video/omapdss.h>
+#include <video/omap-panel-generic-dpi.h>
#include <plat/gpmc-smc91x.h>
diff --git a/arch/arm/mach-omap2/board-4430sdp.c b/arch/arm/mach-omap2/board-4430sdp.c
index 56702c5..93edd7f 100644
--- a/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@ -36,7 +36,7 @@
#include <plat/usb.h>
#include <plat/mmc.h>
#include <plat/omap4-keypad.h>
-#include <plat/display.h>
+#include <video/omapdss.h>
#include "mux.h"
#include "hsmmc.h"
@@ -680,6 +680,15 @@
.name = "hdmi",
.driver_name = "hdmi_panel",
.type = OMAP_DISPLAY_TYPE_HDMI,
+ .clocks = {
+ .dispc = {
+ .dispc_fclk_src = OMAP_DSS_CLK_SRC_FCK,
+ },
+ .hdmi = {
+ .regn = 15,
+ .regm2 = 1,
+ },
+ },
.platform_enable = sdp4430_panel_enable_hdmi,
.platform_disable = sdp4430_panel_disable_hdmi,
.channel = OMAP_DSS_CHANNEL_DIGIT,
diff --git a/arch/arm/mach-omap2/board-am3517evm.c b/arch/arm/mach-omap2/board-am3517evm.c
index ce7d5e6..ff8c59b 100644
--- a/arch/arm/mach-omap2/board-am3517evm.c
+++ b/arch/arm/mach-omap2/board-am3517evm.c
@@ -34,8 +34,8 @@
#include <plat/board.h>
#include <plat/common.h>
#include <plat/usb.h>
-#include <plat/display.h>
-#include <plat/panel-generic-dpi.h>
+#include <video/omapdss.h>
+#include <video/omap-panel-generic-dpi.h>
#include "mux.h"
#include "control.h"
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index 02a12b4..9340f6a 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -45,8 +45,8 @@
#include <plat/nand.h>
#include <plat/gpmc.h>
#include <plat/usb.h>
-#include <plat/display.h>
-#include <plat/panel-generic-dpi.h>
+#include <video/omapdss.h>
+#include <video/omap-panel-generic-dpi.h>
#include <plat/mcspi.h>
#include <mach/hardware.h>
diff --git a/arch/arm/mach-omap2/board-devkit8000.c b/arch/arm/mach-omap2/board-devkit8000.c
index 65f9fde..1d1b56a 100644
--- a/arch/arm/mach-omap2/board-devkit8000.c
+++ b/arch/arm/mach-omap2/board-devkit8000.c
@@ -45,8 +45,8 @@
#include <plat/gpmc.h>
#include <plat/nand.h>
#include <plat/usb.h>
-#include <plat/display.h>
-#include <plat/panel-generic-dpi.h>
+#include <video/omapdss.h>
+#include <video/omap-panel-generic-dpi.h>
#include <plat/mcspi.h>
#include <linux/input/matrix_keypad.h>
diff --git a/arch/arm/mach-omap2/board-igep0020.c b/arch/arm/mach-omap2/board-igep0020.c
index 34cf982..3da64d3 100644
--- a/arch/arm/mach-omap2/board-igep0020.c
+++ b/arch/arm/mach-omap2/board-igep0020.c
@@ -31,8 +31,8 @@
#include <plat/common.h>
#include <plat/gpmc.h>
#include <plat/usb.h>
-#include <plat/display.h>
-#include <plat/panel-generic-dpi.h>
+#include <video/omapdss.h>
+#include <video/omap-panel-generic-dpi.h>
#include <plat/onenand.h>
#include "mux.h"
diff --git a/arch/arm/mach-omap2/board-omap3beagle.c b/arch/arm/mach-omap2/board-omap3beagle.c
index 33007fd..97750d4 100644
--- a/arch/arm/mach-omap2/board-omap3beagle.c
+++ b/arch/arm/mach-omap2/board-omap3beagle.c
@@ -41,8 +41,8 @@
#include <plat/board.h>
#include <plat/common.h>
-#include <plat/display.h>
-#include <plat/panel-generic-dpi.h>
+#include <video/omapdss.h>
+#include <video/omap-panel-generic-dpi.h>
#include <plat/gpmc.h>
#include <plat/nand.h>
#include <plat/usb.h>
diff --git a/arch/arm/mach-omap2/board-omap3evm.c b/arch/arm/mach-omap2/board-omap3evm.c
index 5a1a916..7f94ccc 100644
--- a/arch/arm/mach-omap2/board-omap3evm.c
+++ b/arch/arm/mach-omap2/board-omap3evm.c
@@ -44,8 +44,8 @@
#include <plat/usb.h>
#include <plat/common.h>
#include <plat/mcspi.h>
-#include <plat/display.h>
-#include <plat/panel-generic-dpi.h>
+#include <video/omapdss.h>
+#include <video/omap-panel-generic-dpi.h>
#include "mux.h"
#include "sdram-micron-mt46h32m32lf-6.h"
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index 07dba88..1db1549 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -46,7 +46,7 @@
#include <mach/hardware.h>
#include <plat/mcspi.h>
#include <plat/usb.h>
-#include <plat/display.h>
+#include <video/omapdss.h>
#include <plat/nand.h>
#include "mux.h"
diff --git a/arch/arm/mach-omap2/board-omap3stalker.c b/arch/arm/mach-omap2/board-omap3stalker.c
index a6e0b91..a72c90a 100644
--- a/arch/arm/mach-omap2/board-omap3stalker.c
+++ b/arch/arm/mach-omap2/board-omap3stalker.c
@@ -39,8 +39,8 @@
#include <plat/gpmc.h>
#include <plat/nand.h>
#include <plat/usb.h>
-#include <plat/display.h>
-#include <plat/panel-generic-dpi.h>
+#include <video/omapdss.h>
+#include <video/omap-panel-generic-dpi.h>
#include <plat/mcspi.h>
#include <linux/input/matrix_keypad.h>
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index f3a7b10..e4973ac 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -34,13 +34,13 @@
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
-#include <plat/display.h>
+#include <video/omapdss.h>
#include <plat/board.h>
#include <plat/common.h>
#include <plat/usb.h>
#include <plat/mmc.h>
-#include <plat/panel-generic-dpi.h>
+#include <video/omap-panel-generic-dpi.h>
#include "timer-gp.h"
#include "hsmmc.h"
diff --git a/arch/arm/mach-omap2/board-overo.c b/arch/arm/mach-omap2/board-overo.c
index 59ca333..9d192ff 100644
--- a/arch/arm/mach-omap2/board-overo.c
+++ b/arch/arm/mach-omap2/board-overo.c
@@ -43,8 +43,8 @@
#include <plat/board.h>
#include <plat/common.h>
-#include <plat/display.h>
-#include <plat/panel-generic-dpi.h>
+#include <video/omapdss.h>
+#include <video/omap-panel-generic-dpi.h>
#include <mach/gpio.h>
#include <plat/gpmc.h>
#include <mach/hardware.h>
diff --git a/arch/arm/mach-omap2/board-rx51-video.c b/arch/arm/mach-omap2/board-rx51-video.c
index 89a66db..2df10b6 100644
--- a/arch/arm/mach-omap2/board-rx51-video.c
+++ b/arch/arm/mach-omap2/board-rx51-video.c
@@ -15,7 +15,7 @@
#include <linux/spi/spi.h>
#include <linux/mm.h>
#include <asm/mach-types.h>
-#include <plat/display.h>
+#include <video/omapdss.h>
#include <plat/vram.h>
#include <plat/mcspi.h>
diff --git a/arch/arm/mach-omap2/board-zoom-display.c b/arch/arm/mach-omap2/board-zoom-display.c
index 37b84c2..60e8645 100644
--- a/arch/arm/mach-omap2/board-zoom-display.c
+++ b/arch/arm/mach-omap2/board-zoom-display.c
@@ -15,7 +15,7 @@
#include <linux/i2c/twl.h>
#include <linux/spi/spi.h>
#include <plat/mcspi.h>
-#include <plat/display.h>
+#include <video/omapdss.h>
#define LCD_PANEL_RESET_GPIO_PROD 96
#define LCD_PANEL_RESET_GPIO_PILOT 55
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index 256d23f..543fcb8 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -22,7 +22,7 @@
#include <linux/clk.h>
#include <linux/err.h>
-#include <plat/display.h>
+#include <video/omapdss.h>
#include <plat/omap_hwmod.h>
#include <plat/omap_device.h>
@@ -56,37 +56,58 @@
return false;
}
+struct omap_dss_hwmod_data {
+ const char *oh_name;
+ const char *dev_name;
+ const int id;
+};
+
+static const struct omap_dss_hwmod_data omap2_dss_hwmod_data[] __initdata = {
+ { "dss_core", "omapdss_dss", -1 },
+ { "dss_dispc", "omapdss_dispc", -1 },
+ { "dss_rfbi", "omapdss_rfbi", -1 },
+ { "dss_venc", "omapdss_venc", -1 },
+};
+
+static const struct omap_dss_hwmod_data omap3_dss_hwmod_data[] __initdata = {
+ { "dss_core", "omapdss_dss", -1 },
+ { "dss_dispc", "omapdss_dispc", -1 },
+ { "dss_rfbi", "omapdss_rfbi", -1 },
+ { "dss_venc", "omapdss_venc", -1 },
+ { "dss_dsi1", "omapdss_dsi1", -1 },
+};
+
+static const struct omap_dss_hwmod_data omap4_dss_hwmod_data[] __initdata = {
+ { "dss_core", "omapdss_dss", -1 },
+ { "dss_dispc", "omapdss_dispc", -1 },
+ { "dss_rfbi", "omapdss_rfbi", -1 },
+ { "dss_venc", "omapdss_venc", -1 },
+ { "dss_dsi1", "omapdss_dsi1", -1 },
+ { "dss_dsi2", "omapdss_dsi2", -1 },
+ { "dss_hdmi", "omapdss_hdmi", -1 },
+};
+
int __init omap_display_init(struct omap_dss_board_info *board_data)
{
int r = 0;
struct omap_hwmod *oh;
struct omap_device *od;
- int i;
+ int i, oh_count;
struct omap_display_platform_data pdata;
-
- /*
- * omap: valid DSS hwmod names
- * omap2,3,4: dss_core, dss_dispc, dss_rfbi, dss_venc
- * omap3,4: dss_dsi1
- * omap4: dss_dsi2, dss_hdmi
- */
- char *oh_name[] = { "dss_core", "dss_dispc", "dss_rfbi", "dss_venc",
- "dss_dsi1", "dss_dsi2", "dss_hdmi" };
- char *dev_name[] = { "omapdss_dss", "omapdss_dispc", "omapdss_rfbi",
- "omapdss_venc", "omapdss_dsi1", "omapdss_dsi2",
- "omapdss_hdmi" };
- int oh_count;
+ const struct omap_dss_hwmod_data *curr_dss_hwmod;
memset(&pdata, 0, sizeof(pdata));
- if (cpu_is_omap24xx())
- oh_count = ARRAY_SIZE(oh_name) - 3;
- /* last 3 hwmod dev in oh_name are not available for omap2 */
- else if (cpu_is_omap44xx())
- oh_count = ARRAY_SIZE(oh_name);
- else
- oh_count = ARRAY_SIZE(oh_name) - 2;
- /* last 2 hwmod dev in oh_name are not available for omap3 */
+ if (cpu_is_omap24xx()) {
+ curr_dss_hwmod = omap2_dss_hwmod_data;
+ oh_count = ARRAY_SIZE(omap2_dss_hwmod_data);
+ } else if (cpu_is_omap34xx()) {
+ curr_dss_hwmod = omap3_dss_hwmod_data;
+ oh_count = ARRAY_SIZE(omap3_dss_hwmod_data);
+ } else {
+ curr_dss_hwmod = omap4_dss_hwmod_data;
+ oh_count = ARRAY_SIZE(omap4_dss_hwmod_data);
+ }
/* opt_clks are always associated with dss hwmod */
oh_core = omap_hwmod_lookup("dss_core");
@@ -100,19 +121,21 @@
pdata.opt_clock_available = opt_clock_available;
for (i = 0; i < oh_count; i++) {
- oh = omap_hwmod_lookup(oh_name[i]);
+ oh = omap_hwmod_lookup(curr_dss_hwmod[i].oh_name);
if (!oh) {
- pr_err("Could not look up %s\n", oh_name[i]);
+ pr_err("Could not look up %s\n",
+ curr_dss_hwmod[i].oh_name);
return -ENODEV;
}
- od = omap_device_build(dev_name[i], -1, oh, &pdata,
+ od = omap_device_build(curr_dss_hwmod[i].dev_name,
+ curr_dss_hwmod[i].id, oh, &pdata,
sizeof(struct omap_display_platform_data),
omap_dss_latency,
ARRAY_SIZE(omap_dss_latency), 0);
if (WARN((IS_ERR(od)), "Could not build omap_device for %s\n",
- oh_name[i]))
+ curr_dss_hwmod[i].oh_name))
return -ENODEV;
}
omap_display_device.dev.platform_data = board_data;
diff --git a/arch/arm/mach-omap2/include/mach/board-zoom.h b/arch/arm/mach-omap2/include/mach/board-zoom.h
index d20bd9c..775fdc3 100644
--- a/arch/arm/mach-omap2/include/mach/board-zoom.h
+++ b/arch/arm/mach-omap2/include/mach/board-zoom.h
@@ -1,7 +1,7 @@
/*
* Defines for zoom boards
*/
-#include <plat/display.h>
+#include <video/omapdss.h>
#define ZOOM_NAND_CS 0
diff --git a/arch/arm/mach-omap2/include/mach/omap4-common.h b/arch/arm/mach-omap2/include/mach/omap4-common.h
index de441c0..e4bd87619 100644
--- a/arch/arm/mach-omap2/include/mach/omap4-common.h
+++ b/arch/arm/mach-omap2/include/mach/omap4-common.h
@@ -33,4 +33,11 @@
extern void __init gic_init_irq(void);
extern void omap_smc1(u32 fn, u32 arg);
+#ifdef CONFIG_SMP
+/* Needed for secondary core boot */
+extern void omap_secondary_startup(void);
+extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
+extern void omap_auxcoreboot_addr(u32 cpu_addr);
+extern u32 omap_read_auxcoreboot0(void);
+#endif
#endif
diff --git a/arch/arm/mach-omap2/irq.c b/arch/arm/mach-omap2/irq.c
index 237e453..3af2b7a 100644
--- a/arch/arm/mach-omap2/irq.c
+++ b/arch/arm/mach-omap2/irq.c
@@ -73,83 +73,18 @@
return __raw_readl(bank->base_reg + reg);
}
-static int previous_irq;
-
-/*
- * On 34xx we can get occasional spurious interrupts if the ack from
- * an interrupt handler does not get posted before we unmask. Warn about
- * the interrupt handlers that need to flush posted writes.
- */
-static int omap_check_spurious(unsigned int irq)
-{
- u32 sir, spurious;
-
- sir = intc_bank_read_reg(&irq_banks[0], INTC_SIR);
- spurious = sir >> 7;
-
- if (spurious) {
- printk(KERN_WARNING "Spurious irq %i: 0x%08x, please flush "
- "posted write for irq %i\n",
- irq, sir, previous_irq);
- return spurious;
- }
-
- return 0;
-}
-
/* XXX: FIQ and additional INTC support (only MPU at the moment) */
static void omap_ack_irq(struct irq_data *d)
{
intc_bank_write_reg(0x1, &irq_banks[0], INTC_CONTROL);
}
-static void omap_mask_irq(struct irq_data *d)
-{
- unsigned int irq = d->irq;
- int offset = irq & (~(IRQ_BITS_PER_REG - 1));
-
- if (cpu_is_omap34xx() && !cpu_is_ti816x()) {
- int spurious = 0;
-
- /*
- * INT_34XX_GPT12_IRQ is also the spurious irq. Maybe because
- * it is the highest irq number?
- */
- if (irq == INT_34XX_GPT12_IRQ)
- spurious = omap_check_spurious(irq);
-
- if (!spurious)
- previous_irq = irq;
- }
-
- irq &= (IRQ_BITS_PER_REG - 1);
-
- intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_SET0 + offset);
-}
-
-static void omap_unmask_irq(struct irq_data *d)
-{
- unsigned int irq = d->irq;
- int offset = irq & (~(IRQ_BITS_PER_REG - 1));
-
- irq &= (IRQ_BITS_PER_REG - 1);
-
- intc_bank_write_reg(1 << irq, &irq_banks[0], INTC_MIR_CLEAR0 + offset);
-}
-
static void omap_mask_ack_irq(struct irq_data *d)
{
- omap_mask_irq(d);
+ irq_gc_mask_disable_reg(d);
omap_ack_irq(d);
}
-static struct irq_chip omap_irq_chip = {
- .name = "INTC",
- .irq_ack = omap_mask_ack_irq,
- .irq_mask = omap_mask_irq,
- .irq_unmask = omap_unmask_irq,
-};
-
static void __init omap_irq_bank_init_one(struct omap_irq_bank *bank)
{
unsigned long tmp;
@@ -186,11 +121,31 @@
return 0;
}
+static __init void
+omap_alloc_gc(void __iomem *base, unsigned int irq_start, unsigned int num)
+{
+ struct irq_chip_generic *gc;
+ struct irq_chip_type *ct;
+
+ gc = irq_alloc_generic_chip("INTC", 1, irq_start, base,
+ handle_level_irq);
+ ct = gc->chip_types;
+ ct->chip.irq_ack = omap_mask_ack_irq;
+ ct->chip.irq_mask = irq_gc_mask_disable_reg;
+ ct->chip.irq_unmask = irq_gc_unmask_enable_reg;
+
+ ct->regs.ack = INTC_CONTROL;
+ ct->regs.enable = INTC_MIR_CLEAR0;
+ ct->regs.disable = INTC_MIR_SET0;
+ irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
+ IRQ_NOREQUEST | IRQ_NOPROBE, 0);
+}
+
void __init omap_init_irq(void)
{
unsigned long nr_of_irqs = 0;
unsigned int nr_banks = 0;
- int i;
+ int i, j;
for (i = 0; i < ARRAY_SIZE(irq_banks); i++) {
unsigned long base = 0;
@@ -215,17 +170,15 @@
omap_irq_bank_init_one(bank);
+ for (i = 0, j = 0; i < bank->nr_irqs; i += 32, j += 0x20)
+ omap_alloc_gc(bank->base_reg + j, i, 32);
+
nr_of_irqs += bank->nr_irqs;
nr_banks++;
}
printk(KERN_INFO "Total of %ld interrupts on %d active controller%s\n",
nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
-
- for (i = 0; i < nr_of_irqs; i++) {
- irq_set_chip_and_handler(i, &omap_irq_chip, handle_level_irq);
- set_irq_flags(i, IRQF_VALID);
- }
}
#ifdef CONFIG_ARCH_OMAP3
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index b66cfe8..ecfe93c 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -21,6 +21,7 @@
#include <linux/io.h>
#include <asm/cacheflush.h>
+#include <asm/hardware/gic.h>
#include <asm/smp_scu.h>
#include <mach/hardware.h>
#include <mach/omap4-common.h>
@@ -63,7 +64,7 @@
omap_modify_auxcoreboot0(0x200, 0xfffffdff);
flush_cache_all();
smp_wmb();
- smp_cross_call(cpumask_of(cpu), 1);
+ gic_raise_softirq(cpumask_of(cpu), 1);
/*
* Now the secondary core is starting up let it run its
@@ -118,6 +119,8 @@
for (i = 0; i < ncores; i++)
set_cpu_possible(i, true);
+
+ set_smp_cross_call(gic_raise_softirq);
}
void __init platform_smp_prepare_cpus(unsigned int max_cpus)
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index 986c3bf..0ab531d 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -13,12 +13,11 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
#include <linux/serial_8250.h>
#include <linux/mbus.h>
-#include <linux/mv643xx_eth.h>
#include <linux/mv643xx_i2c.h>
#include <linux/ata_platform.h>
-#include <linux/spi/orion_spi.h>
#include <net/dsa.h>
#include <asm/page.h>
#include <asm/setup.h>
@@ -29,11 +28,9 @@
#include <mach/bridge-regs.h>
#include <mach/hardware.h>
#include <mach/orion5x.h>
-#include <plat/ehci-orion.h>
-#include <plat/mv_xor.h>
#include <plat/orion_nand.h>
-#include <plat/orion_wdt.h>
#include <plat/time.h>
+#include <plat/common.h>
#include "common.h"
/*****************************************************************************
@@ -70,530 +67,124 @@
/*****************************************************************************
- * EHCI
- ****************************************************************************/
-static struct orion_ehci_data orion5x_ehci_data = {
- .dram = &orion5x_mbus_dram_info,
- .phy_version = EHCI_PHY_ORION,
-};
-
-static u64 ehci_dmamask = 0xffffffffUL;
-
-
-/*****************************************************************************
* EHCI0
****************************************************************************/
-static struct resource orion5x_ehci0_resources[] = {
- {
- .start = ORION5X_USB0_PHYS_BASE,
- .end = ORION5X_USB0_PHYS_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_ORION5X_USB0_CTRL,
- .end = IRQ_ORION5X_USB0_CTRL,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device orion5x_ehci0 = {
- .name = "orion-ehci",
- .id = 0,
- .dev = {
- .dma_mask = &ehci_dmamask,
- .coherent_dma_mask = 0xffffffff,
- .platform_data = &orion5x_ehci_data,
- },
- .resource = orion5x_ehci0_resources,
- .num_resources = ARRAY_SIZE(orion5x_ehci0_resources),
-};
-
void __init orion5x_ehci0_init(void)
{
- platform_device_register(&orion5x_ehci0);
+ orion_ehci_init(&orion5x_mbus_dram_info,
+ ORION5X_USB0_PHYS_BASE, IRQ_ORION5X_USB0_CTRL);
}
/*****************************************************************************
* EHCI1
****************************************************************************/
-static struct resource orion5x_ehci1_resources[] = {
- {
- .start = ORION5X_USB1_PHYS_BASE,
- .end = ORION5X_USB1_PHYS_BASE + SZ_4K - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_ORION5X_USB1_CTRL,
- .end = IRQ_ORION5X_USB1_CTRL,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device orion5x_ehci1 = {
- .name = "orion-ehci",
- .id = 1,
- .dev = {
- .dma_mask = &ehci_dmamask,
- .coherent_dma_mask = 0xffffffff,
- .platform_data = &orion5x_ehci_data,
- },
- .resource = orion5x_ehci1_resources,
- .num_resources = ARRAY_SIZE(orion5x_ehci1_resources),
-};
-
void __init orion5x_ehci1_init(void)
{
- platform_device_register(&orion5x_ehci1);
+ orion_ehci_1_init(&orion5x_mbus_dram_info,
+ ORION5X_USB1_PHYS_BASE, IRQ_ORION5X_USB1_CTRL);
}
/*****************************************************************************
- * GigE
+ * GE00
****************************************************************************/
-struct mv643xx_eth_shared_platform_data orion5x_eth_shared_data = {
- .dram = &orion5x_mbus_dram_info,
-};
-
-static struct resource orion5x_eth_shared_resources[] = {
- {
- .start = ORION5X_ETH_PHYS_BASE + 0x2000,
- .end = ORION5X_ETH_PHYS_BASE + 0x3fff,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_ORION5X_ETH_ERR,
- .end = IRQ_ORION5X_ETH_ERR,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device orion5x_eth_shared = {
- .name = MV643XX_ETH_SHARED_NAME,
- .id = 0,
- .dev = {
- .platform_data = &orion5x_eth_shared_data,
- },
- .num_resources = ARRAY_SIZE(orion5x_eth_shared_resources),
- .resource = orion5x_eth_shared_resources,
-};
-
-static struct resource orion5x_eth_resources[] = {
- {
- .name = "eth irq",
- .start = IRQ_ORION5X_ETH_SUM,
- .end = IRQ_ORION5X_ETH_SUM,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device orion5x_eth = {
- .name = MV643XX_ETH_NAME,
- .id = 0,
- .num_resources = 1,
- .resource = orion5x_eth_resources,
- .dev = {
- .coherent_dma_mask = 0xffffffff,
- },
-};
-
void __init orion5x_eth_init(struct mv643xx_eth_platform_data *eth_data)
{
- eth_data->shared = &orion5x_eth_shared;
- orion5x_eth.dev.platform_data = eth_data;
-
- platform_device_register(&orion5x_eth_shared);
- platform_device_register(&orion5x_eth);
+ orion_ge00_init(eth_data, &orion5x_mbus_dram_info,
+ ORION5X_ETH_PHYS_BASE, IRQ_ORION5X_ETH_SUM,
+ IRQ_ORION5X_ETH_ERR, orion5x_tclk);
}
/*****************************************************************************
* Ethernet switch
****************************************************************************/
-static struct resource orion5x_switch_resources[] = {
- {
- .start = 0,
- .end = 0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device orion5x_switch_device = {
- .name = "dsa",
- .id = 0,
- .num_resources = 0,
- .resource = orion5x_switch_resources,
-};
-
void __init orion5x_eth_switch_init(struct dsa_platform_data *d, int irq)
{
- int i;
-
- if (irq != NO_IRQ) {
- orion5x_switch_resources[0].start = irq;
- orion5x_switch_resources[0].end = irq;
- orion5x_switch_device.num_resources = 1;
- }
-
- d->netdev = &orion5x_eth.dev;
- for (i = 0; i < d->nr_chips; i++)
- d->chip[i].mii_bus = &orion5x_eth_shared.dev;
- orion5x_switch_device.dev.platform_data = d;
-
- platform_device_register(&orion5x_switch_device);
+ orion_ge00_switch_init(d, irq);
}
/*****************************************************************************
* I2C
****************************************************************************/
-static struct mv64xxx_i2c_pdata orion5x_i2c_pdata = {
- .freq_m = 8, /* assumes 166 MHz TCLK */
- .freq_n = 3,
- .timeout = 1000, /* Default timeout of 1 second */
-};
-
-static struct resource orion5x_i2c_resources[] = {
- {
- .start = I2C_PHYS_BASE,
- .end = I2C_PHYS_BASE + 0x1f,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_ORION5X_I2C,
- .end = IRQ_ORION5X_I2C,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device orion5x_i2c = {
- .name = MV64XXX_I2C_CTLR_NAME,
- .id = 0,
- .num_resources = ARRAY_SIZE(orion5x_i2c_resources),
- .resource = orion5x_i2c_resources,
- .dev = {
- .platform_data = &orion5x_i2c_pdata,
- },
-};
-
void __init orion5x_i2c_init(void)
{
- platform_device_register(&orion5x_i2c);
+ orion_i2c_init(I2C_PHYS_BASE, IRQ_ORION5X_I2C, 8);
+
}
/*****************************************************************************
* SATA
****************************************************************************/
-static struct resource orion5x_sata_resources[] = {
- {
- .name = "sata base",
- .start = ORION5X_SATA_PHYS_BASE,
- .end = ORION5X_SATA_PHYS_BASE + 0x5000 - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .name = "sata irq",
- .start = IRQ_ORION5X_SATA,
- .end = IRQ_ORION5X_SATA,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device orion5x_sata = {
- .name = "sata_mv",
- .id = 0,
- .dev = {
- .coherent_dma_mask = 0xffffffff,
- },
- .num_resources = ARRAY_SIZE(orion5x_sata_resources),
- .resource = orion5x_sata_resources,
-};
-
void __init orion5x_sata_init(struct mv_sata_platform_data *sata_data)
{
- sata_data->dram = &orion5x_mbus_dram_info;
- orion5x_sata.dev.platform_data = sata_data;
- platform_device_register(&orion5x_sata);
+ orion_sata_init(sata_data, &orion5x_mbus_dram_info,
+ ORION5X_SATA_PHYS_BASE, IRQ_ORION5X_SATA);
}
/*****************************************************************************
* SPI
****************************************************************************/
-static struct orion_spi_info orion5x_spi_plat_data = {
- .tclk = 0,
- .enable_clock_fix = 1,
-};
-
-static struct resource orion5x_spi_resources[] = {
- {
- .name = "spi base",
- .start = SPI_PHYS_BASE,
- .end = SPI_PHYS_BASE + 0x1f,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device orion5x_spi = {
- .name = "orion_spi",
- .id = 0,
- .dev = {
- .platform_data = &orion5x_spi_plat_data,
- },
- .num_resources = ARRAY_SIZE(orion5x_spi_resources),
- .resource = orion5x_spi_resources,
-};
-
void __init orion5x_spi_init()
{
- platform_device_register(&orion5x_spi);
+ orion_spi_init(SPI_PHYS_BASE, orion5x_tclk);
}
/*****************************************************************************
* UART0
****************************************************************************/
-static struct plat_serial8250_port orion5x_uart0_data[] = {
- {
- .mapbase = UART0_PHYS_BASE,
- .membase = (char *)UART0_VIRT_BASE,
- .irq = IRQ_ORION5X_UART0,
- .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
- .iotype = UPIO_MEM,
- .regshift = 2,
- .uartclk = 0,
- }, {
- },
-};
-
-static struct resource orion5x_uart0_resources[] = {
- {
- .start = UART0_PHYS_BASE,
- .end = UART0_PHYS_BASE + 0xff,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_ORION5X_UART0,
- .end = IRQ_ORION5X_UART0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device orion5x_uart0 = {
- .name = "serial8250",
- .id = PLAT8250_DEV_PLATFORM,
- .dev = {
- .platform_data = orion5x_uart0_data,
- },
- .resource = orion5x_uart0_resources,
- .num_resources = ARRAY_SIZE(orion5x_uart0_resources),
-};
-
void __init orion5x_uart0_init(void)
{
- platform_device_register(&orion5x_uart0);
+ orion_uart0_init(UART0_VIRT_BASE, UART0_PHYS_BASE,
+ IRQ_ORION5X_UART0, orion5x_tclk);
}
-
/*****************************************************************************
* UART1
****************************************************************************/
-static struct plat_serial8250_port orion5x_uart1_data[] = {
- {
- .mapbase = UART1_PHYS_BASE,
- .membase = (char *)UART1_VIRT_BASE,
- .irq = IRQ_ORION5X_UART1,
- .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
- .iotype = UPIO_MEM,
- .regshift = 2,
- .uartclk = 0,
- }, {
- },
-};
-
-static struct resource orion5x_uart1_resources[] = {
- {
- .start = UART1_PHYS_BASE,
- .end = UART1_PHYS_BASE + 0xff,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_ORION5X_UART1,
- .end = IRQ_ORION5X_UART1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device orion5x_uart1 = {
- .name = "serial8250",
- .id = PLAT8250_DEV_PLATFORM1,
- .dev = {
- .platform_data = orion5x_uart1_data,
- },
- .resource = orion5x_uart1_resources,
- .num_resources = ARRAY_SIZE(orion5x_uart1_resources),
-};
-
void __init orion5x_uart1_init(void)
{
- platform_device_register(&orion5x_uart1);
+ orion_uart1_init(UART1_VIRT_BASE, UART1_PHYS_BASE,
+ IRQ_ORION5X_UART1, orion5x_tclk);
}
-
/*****************************************************************************
* XOR engine
****************************************************************************/
-struct mv_xor_platform_shared_data orion5x_xor_shared_data = {
- .dram = &orion5x_mbus_dram_info,
-};
-
-static struct resource orion5x_xor_shared_resources[] = {
- {
- .name = "xor low",
- .start = ORION5X_XOR_PHYS_BASE,
- .end = ORION5X_XOR_PHYS_BASE + 0xff,
- .flags = IORESOURCE_MEM,
- }, {
- .name = "xor high",
- .start = ORION5X_XOR_PHYS_BASE + 0x200,
- .end = ORION5X_XOR_PHYS_BASE + 0x2ff,
- .flags = IORESOURCE_MEM,
- },
-};
-
-static struct platform_device orion5x_xor_shared = {
- .name = MV_XOR_SHARED_NAME,
- .id = 0,
- .dev = {
- .platform_data = &orion5x_xor_shared_data,
- },
- .num_resources = ARRAY_SIZE(orion5x_xor_shared_resources),
- .resource = orion5x_xor_shared_resources,
-};
-
-static u64 orion5x_xor_dmamask = DMA_BIT_MASK(32);
-
-static struct resource orion5x_xor0_resources[] = {
- [0] = {
- .start = IRQ_ORION5X_XOR0,
- .end = IRQ_ORION5X_XOR0,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct mv_xor_platform_data orion5x_xor0_data = {
- .shared = &orion5x_xor_shared,
- .hw_id = 0,
- .pool_size = PAGE_SIZE,
-};
-
-static struct platform_device orion5x_xor0_channel = {
- .name = MV_XOR_NAME,
- .id = 0,
- .num_resources = ARRAY_SIZE(orion5x_xor0_resources),
- .resource = orion5x_xor0_resources,
- .dev = {
- .dma_mask = &orion5x_xor_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(64),
- .platform_data = &orion5x_xor0_data,
- },
-};
-
-static struct resource orion5x_xor1_resources[] = {
- [0] = {
- .start = IRQ_ORION5X_XOR1,
- .end = IRQ_ORION5X_XOR1,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct mv_xor_platform_data orion5x_xor1_data = {
- .shared = &orion5x_xor_shared,
- .hw_id = 1,
- .pool_size = PAGE_SIZE,
-};
-
-static struct platform_device orion5x_xor1_channel = {
- .name = MV_XOR_NAME,
- .id = 1,
- .num_resources = ARRAY_SIZE(orion5x_xor1_resources),
- .resource = orion5x_xor1_resources,
- .dev = {
- .dma_mask = &orion5x_xor_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(64),
- .platform_data = &orion5x_xor1_data,
- },
-};
-
void __init orion5x_xor_init(void)
{
- platform_device_register(&orion5x_xor_shared);
-
- /*
- * two engines can't do memset simultaneously, this limitation
- * satisfied by removing memset support from one of the engines.
- */
- dma_cap_set(DMA_MEMCPY, orion5x_xor0_data.cap_mask);
- dma_cap_set(DMA_XOR, orion5x_xor0_data.cap_mask);
- platform_device_register(&orion5x_xor0_channel);
-
- dma_cap_set(DMA_MEMCPY, orion5x_xor1_data.cap_mask);
- dma_cap_set(DMA_MEMSET, orion5x_xor1_data.cap_mask);
- dma_cap_set(DMA_XOR, orion5x_xor1_data.cap_mask);
- platform_device_register(&orion5x_xor1_channel);
+ orion_xor0_init(&orion5x_mbus_dram_info,
+ ORION5X_XOR_PHYS_BASE,
+ ORION5X_XOR_PHYS_BASE + 0x200,
+ IRQ_ORION5X_XOR0, IRQ_ORION5X_XOR1);
}
-static struct resource orion5x_crypto_res[] = {
- {
- .name = "regs",
- .start = ORION5X_CRYPTO_PHYS_BASE,
- .end = ORION5X_CRYPTO_PHYS_BASE + 0xffff,
- .flags = IORESOURCE_MEM,
- }, {
- .name = "sram",
- .start = ORION5X_SRAM_PHYS_BASE,
- .end = ORION5X_SRAM_PHYS_BASE + SZ_8K - 1,
- .flags = IORESOURCE_MEM,
- }, {
- .name = "crypto interrupt",
- .start = IRQ_ORION5X_CESA,
- .end = IRQ_ORION5X_CESA,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-static struct platform_device orion5x_crypto_device = {
- .name = "mv_crypto",
- .id = -1,
- .num_resources = ARRAY_SIZE(orion5x_crypto_res),
- .resource = orion5x_crypto_res,
-};
-
-static int __init orion5x_crypto_init(void)
+/*****************************************************************************
+ * Cryptographic Engines and Security Accelerator (CESA)
+ ****************************************************************************/
+static void __init orion5x_crypto_init(void)
{
int ret;
ret = orion5x_setup_sram_win();
if (ret)
- return ret;
+ return;
- return platform_device_register(&orion5x_crypto_device);
+ orion_crypto_init(ORION5X_CRYPTO_PHYS_BASE, ORION5X_SRAM_PHYS_BASE,
+ SZ_8K, IRQ_ORION5X_CESA);
}
/*****************************************************************************
* Watchdog
****************************************************************************/
-static struct orion_wdt_platform_data orion5x_wdt_data = {
- .tclk = 0,
-};
-
-static struct platform_device orion5x_wdt_device = {
- .name = "orion_wdt",
- .id = -1,
- .dev = {
- .platform_data = &orion5x_wdt_data,
- },
- .num_resources = 0,
-};
-
void __init orion5x_wdt_init(void)
{
- orion5x_wdt_data.tclk = orion5x_tclk;
- platform_device_register(&orion5x_wdt_device);
+ orion_wdt_init(orion5x_tclk);
}
@@ -685,11 +276,6 @@
orion5x_id(&dev, &rev, &dev_name);
printk(KERN_INFO "Orion ID: %s. TCLK=%d.\n", dev_name, orion5x_tclk);
- orion5x_eth_shared_data.t_clk = orion5x_tclk;
- orion5x_spi_plat_data.tclk = orion5x_tclk;
- orion5x_uart0_data[0].uartclk = orion5x_tclk;
- orion5x_uart1_data[0].uartclk = orion5x_tclk;
-
/*
* Setup Orion address map
*/
diff --git a/arch/arm/mach-orion5x/d2net-setup.c b/arch/arm/mach-orion5x/d2net-setup.c
index 4258075..19cf5bf 100644
--- a/arch/arm/mach-orion5x/d2net-setup.c
+++ b/arch/arm/mach-orion5x/d2net-setup.c
@@ -267,28 +267,28 @@
* General Setup
****************************************************************************/
-static struct orion5x_mpp_mode d2net_mpp_modes[] __initdata = {
- { 0, MPP_GPIO }, /* Board ID (bit 0) */
- { 1, MPP_GPIO }, /* Board ID (bit 1) */
- { 2, MPP_GPIO }, /* Board ID (bit 2) */
- { 3, MPP_GPIO }, /* SATA 0 power */
- { 4, MPP_UNUSED },
- { 5, MPP_GPIO }, /* Fan fail detection */
- { 6, MPP_GPIO }, /* Red front LED */
- { 7, MPP_UNUSED },
- { 8, MPP_GPIO }, /* Rear power switch (on|auto) */
- { 9, MPP_GPIO }, /* Rear power switch (auto|off) */
- { 10, MPP_UNUSED },
- { 11, MPP_UNUSED },
- { 12, MPP_GPIO }, /* SATA 1 power */
- { 13, MPP_UNUSED },
- { 14, MPP_SATA_LED }, /* SATA 0 active */
- { 15, MPP_SATA_LED }, /* SATA 1 active */
- { 16, MPP_GPIO }, /* Blue front LED blink control */
- { 17, MPP_UNUSED },
- { 18, MPP_GPIO }, /* Front button (0 = Released, 1 = Pushed ) */
- { 19, MPP_UNUSED },
- { -1 }
+static unsigned int d2net_mpp_modes[] __initdata = {
+ MPP0_GPIO, /* Board ID (bit 0) */
+ MPP1_GPIO, /* Board ID (bit 1) */
+ MPP2_GPIO, /* Board ID (bit 2) */
+ MPP3_GPIO, /* SATA 0 power */
+ MPP4_UNUSED,
+ MPP5_GPIO, /* Fan fail detection */
+ MPP6_GPIO, /* Red front LED */
+ MPP7_UNUSED,
+ MPP8_GPIO, /* Rear power switch (on|auto) */
+ MPP9_GPIO, /* Rear power switch (auto|off) */
+ MPP10_UNUSED,
+ MPP11_UNUSED,
+ MPP12_GPIO, /* SATA 1 power */
+ MPP13_UNUSED,
+ MPP14_SATA_LED, /* SATA 0 active */
+ MPP15_SATA_LED, /* SATA 1 active */
+ MPP16_GPIO, /* Blue front LED blink control */
+ MPP17_UNUSED,
+ MPP18_GPIO, /* Front button (0 = Released, 1 = Pushed ) */
+ MPP19_UNUSED,
+ 0,
/* 22: USB port 1 fuse (0 = Fail, 1 = Ok) */
/* 23: Blue front LED off */
/* 24: Inhibit board power off (0 = Disabled, 1 = Enabled) */
diff --git a/arch/arm/mach-orion5x/db88f5281-setup.c b/arch/arm/mach-orion5x/db88f5281-setup.c
index b7d4591..f95d3cb 100644
--- a/arch/arm/mach-orion5x/db88f5281-setup.c
+++ b/arch/arm/mach-orion5x/db88f5281-setup.c
@@ -298,28 +298,28 @@
/*****************************************************************************
* General Setup
****************************************************************************/
-static struct orion5x_mpp_mode db88f5281_mpp_modes[] __initdata = {
- { 0, MPP_GPIO }, /* USB Over Current */
- { 1, MPP_GPIO }, /* USB Vbat input */
- { 2, MPP_PCI_ARB }, /* PCI_REQn[2] */
- { 3, MPP_PCI_ARB }, /* PCI_GNTn[2] */
- { 4, MPP_PCI_ARB }, /* PCI_REQn[3] */
- { 5, MPP_PCI_ARB }, /* PCI_GNTn[3] */
- { 6, MPP_GPIO }, /* JP0, CON17.2 */
- { 7, MPP_GPIO }, /* JP1, CON17.1 */
- { 8, MPP_GPIO }, /* JP2, CON11.2 */
- { 9, MPP_GPIO }, /* JP3, CON11.3 */
- { 10, MPP_GPIO }, /* RTC int */
- { 11, MPP_GPIO }, /* Baud Rate Generator */
- { 12, MPP_GPIO }, /* PCI int 1 */
- { 13, MPP_GPIO }, /* PCI int 2 */
- { 14, MPP_NAND }, /* NAND_REn[2] */
- { 15, MPP_NAND }, /* NAND_WEn[2] */
- { 16, MPP_UART }, /* UART1_RX */
- { 17, MPP_UART }, /* UART1_TX */
- { 18, MPP_UART }, /* UART1_CTSn */
- { 19, MPP_UART }, /* UART1_RTSn */
- { -1 },
+static unsigned int db88f5281_mpp_modes[] __initdata = {
+ MPP0_GPIO, /* USB Over Current */
+ MPP1_GPIO, /* USB Vbat input */
+ MPP2_PCI_ARB, /* PCI_REQn[2] */
+ MPP3_PCI_ARB, /* PCI_GNTn[2] */
+ MPP4_PCI_ARB, /* PCI_REQn[3] */
+ MPP5_PCI_ARB, /* PCI_GNTn[3] */
+ MPP6_GPIO, /* JP0, CON17.2 */
+ MPP7_GPIO, /* JP1, CON17.1 */
+ MPP8_GPIO, /* JP2, CON11.2 */
+ MPP9_GPIO, /* JP3, CON11.3 */
+ MPP10_GPIO, /* RTC int */
+ MPP11_GPIO, /* Baud Rate Generator */
+ MPP12_GPIO, /* PCI int 1 */
+ MPP13_GPIO, /* PCI int 2 */
+ MPP14_NAND, /* NAND_REn[2] */
+ MPP15_NAND, /* NAND_WEn[2] */
+ MPP16_UART, /* UART1_RX */
+ MPP17_UART, /* UART1_TX */
+ MPP18_UART, /* UART1_CTSn */
+ MPP19_UART, /* UART1_RTSn */
+ 0,
};
static void __init db88f5281_init(void)
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
index 90ab022..855e0e7 100644
--- a/arch/arm/mach-orion5x/dns323-setup.c
+++ b/arch/arm/mach-orion5x/dns323-setup.c
@@ -385,76 +385,76 @@
/****************************************************************************
* General Setup
*/
-static struct orion5x_mpp_mode dns323a_mpp_modes[] __initdata = {
- { 0, MPP_PCIE_RST_OUTn },
- { 1, MPP_GPIO }, /* right amber LED (sata ch0) */
- { 2, MPP_GPIO }, /* left amber LED (sata ch1) */
- { 3, MPP_UNUSED },
- { 4, MPP_GPIO }, /* power button LED */
- { 5, MPP_GPIO }, /* power button LED */
- { 6, MPP_GPIO }, /* GMT G751-2f overtemp */
- { 7, MPP_GPIO }, /* M41T80 nIRQ/OUT/SQW */
- { 8, MPP_GPIO }, /* triggers power off */
- { 9, MPP_GPIO }, /* power button switch */
- { 10, MPP_GPIO }, /* reset button switch */
- { 11, MPP_UNUSED },
- { 12, MPP_UNUSED },
- { 13, MPP_UNUSED },
- { 14, MPP_UNUSED },
- { 15, MPP_UNUSED },
- { 16, MPP_UNUSED },
- { 17, MPP_UNUSED },
- { 18, MPP_UNUSED },
- { 19, MPP_UNUSED },
- { -1 },
+static unsigned int dns323a_mpp_modes[] __initdata = {
+ MPP0_PCIE_RST_OUTn,
+ MPP1_GPIO, /* right amber LED (sata ch0) */
+ MPP2_GPIO, /* left amber LED (sata ch1) */
+ MPP3_UNUSED,
+ MPP4_GPIO, /* power button LED */
+ MPP5_GPIO, /* power button LED */
+ MPP6_GPIO, /* GMT G751-2f overtemp */
+ MPP7_GPIO, /* M41T80 nIRQ/OUT/SQW */
+ MPP8_GPIO, /* triggers power off */
+ MPP9_GPIO, /* power button switch */
+ MPP10_GPIO, /* reset button switch */
+ MPP11_UNUSED,
+ MPP12_UNUSED,
+ MPP13_UNUSED,
+ MPP14_UNUSED,
+ MPP15_UNUSED,
+ MPP16_UNUSED,
+ MPP17_UNUSED,
+ MPP18_UNUSED,
+ MPP19_UNUSED,
+ 0,
};
-static struct orion5x_mpp_mode dns323b_mpp_modes[] __initdata = {
- { 0, MPP_UNUSED },
- { 1, MPP_GPIO }, /* right amber LED (sata ch0) */
- { 2, MPP_GPIO }, /* left amber LED (sata ch1) */
- { 3, MPP_GPIO }, /* system up flag */
- { 4, MPP_GPIO }, /* power button LED */
- { 5, MPP_GPIO }, /* power button LED */
- { 6, MPP_GPIO }, /* GMT G751-2f overtemp */
- { 7, MPP_GPIO }, /* M41T80 nIRQ/OUT/SQW */
- { 8, MPP_GPIO }, /* triggers power off */
- { 9, MPP_GPIO }, /* power button switch */
- { 10, MPP_GPIO }, /* reset button switch */
- { 11, MPP_UNUSED },
- { 12, MPP_SATA_LED },
- { 13, MPP_SATA_LED },
- { 14, MPP_SATA_LED },
- { 15, MPP_SATA_LED },
- { 16, MPP_UNUSED },
- { 17, MPP_UNUSED },
- { 18, MPP_UNUSED },
- { 19, MPP_UNUSED },
- { -1 },
+static unsigned int dns323b_mpp_modes[] __initdata = {
+ MPP0_UNUSED,
+ MPP1_GPIO, /* right amber LED (sata ch0) */
+ MPP2_GPIO, /* left amber LED (sata ch1) */
+ MPP3_GPIO, /* system up flag */
+ MPP4_GPIO, /* power button LED */
+ MPP5_GPIO, /* power button LED */
+ MPP6_GPIO, /* GMT G751-2f overtemp */
+ MPP7_GPIO, /* M41T80 nIRQ/OUT/SQW */
+ MPP8_GPIO, /* triggers power off */
+ MPP9_GPIO, /* power button switch */
+ MPP10_GPIO, /* reset button switch */
+ MPP11_UNUSED,
+ MPP12_SATA_LED,
+ MPP13_SATA_LED,
+ MPP14_SATA_LED,
+ MPP15_SATA_LED,
+ MPP16_UNUSED,
+ MPP17_UNUSED,
+ MPP18_UNUSED,
+ MPP19_UNUSED,
+ 0,
};
-static struct orion5x_mpp_mode dns323c_mpp_modes[] __initdata = {
- { 0, MPP_GPIO }, /* ? input */
- { 1, MPP_GPIO }, /* input power switch (0 = pressed) */
- { 2, MPP_GPIO }, /* output power off */
- { 3, MPP_UNUSED }, /* ? output */
- { 4, MPP_UNUSED }, /* ? output */
- { 5, MPP_UNUSED }, /* ? output */
- { 6, MPP_UNUSED }, /* ? output */
- { 7, MPP_UNUSED }, /* ? output */
- { 8, MPP_GPIO }, /* i/o right amber LED */
- { 9, MPP_GPIO }, /* i/o left amber LED */
- { 10, MPP_GPIO }, /* input */
- { 11, MPP_UNUSED },
- { 12, MPP_SATA_LED },
- { 13, MPP_SATA_LED },
- { 14, MPP_SATA_LED },
- { 15, MPP_SATA_LED },
- { 16, MPP_UNUSED },
- { 17, MPP_GPIO }, /* power button LED */
- { 18, MPP_GPIO }, /* fan speed bit 0 */
- { 19, MPP_GPIO }, /* fan speed bit 1 */
- { -1 },
+static unsigned int dns323c_mpp_modes[] __initdata = {
+ MPP0_GPIO, /* ? input */
+ MPP1_GPIO, /* input power switch (0 = pressed) */
+ MPP2_GPIO, /* output power off */
+ MPP3_UNUSED, /* ? output */
+ MPP4_UNUSED, /* ? output */
+ MPP5_UNUSED, /* ? output */
+ MPP6_UNUSED, /* ? output */
+ MPP7_UNUSED, /* ? output */
+ MPP8_GPIO, /* i/o right amber LED */
+ MPP9_GPIO, /* i/o left amber LED */
+ MPP10_GPIO, /* input */
+ MPP11_UNUSED,
+ MPP12_SATA_LED,
+ MPP13_SATA_LED,
+ MPP14_SATA_LED,
+ MPP15_SATA_LED,
+ MPP16_UNUSED,
+ MPP17_GPIO, /* power button LED */
+ MPP18_GPIO, /* fan speed bit 0 */
+ MPP19_GPIO, /* fan speed bit 1 */
+ 0,
};
/* Rev C1 Fan speed notes:
diff --git a/arch/arm/mach-orion5x/edmini_v2-setup.c b/arch/arm/mach-orion5x/edmini_v2-setup.c
index d037a90..b67cff0 100644
--- a/arch/arm/mach-orion5x/edmini_v2-setup.c
+++ b/arch/arm/mach-orion5x/edmini_v2-setup.c
@@ -180,31 +180,31 @@
/*****************************************************************************
* General Setup
****************************************************************************/
-static struct orion5x_mpp_mode edminiv2_mpp_modes[] __initdata = {
- { 0, MPP_UNUSED },
- { 1, MPP_UNUSED },
- { 2, MPP_UNUSED },
- { 3, MPP_GPIO }, /* RTC interrupt */
- { 4, MPP_UNUSED },
- { 5, MPP_UNUSED },
- { 6, MPP_UNUSED },
- { 7, MPP_UNUSED },
- { 8, MPP_UNUSED },
- { 9, MPP_UNUSED },
- { 10, MPP_UNUSED },
- { 11, MPP_UNUSED },
- { 12, MPP_SATA_LED }, /* SATA 0 presence */
- { 13, MPP_SATA_LED }, /* SATA 1 presence */
- { 14, MPP_SATA_LED }, /* SATA 0 active */
- { 15, MPP_SATA_LED }, /* SATA 1 active */
+static unsigned int edminiv2_mpp_modes[] __initdata = {
+ MPP0_UNUSED,
+ MPP1_UNUSED,
+ MPP2_UNUSED,
+ MPP3_GPIO, /* RTC interrupt */
+ MPP4_UNUSED,
+ MPP5_UNUSED,
+ MPP6_UNUSED,
+ MPP7_UNUSED,
+ MPP8_UNUSED,
+ MPP9_UNUSED,
+ MPP10_UNUSED,
+ MPP11_UNUSED,
+ MPP12_SATA_LED, /* SATA 0 presence */
+ MPP13_SATA_LED, /* SATA 1 presence */
+ MPP14_SATA_LED, /* SATA 0 active */
+ MPP15_SATA_LED, /* SATA 1 active */
/* 16: Power LED control (0 = On, 1 = Off) */
- { 16, MPP_GPIO },
+ MPP16_GPIO,
/* 17: Power LED control select (0 = CPLD, 1 = GPIO16) */
- { 17, MPP_GPIO },
+ MPP17_GPIO,
/* 18: Power button status (0 = Released, 1 = Pressed) */
- { 18, MPP_GPIO },
- { 19, MPP_UNUSED },
- { -1 }
+ MPP18_GPIO,
+ MPP19_UNUSED,
+ 0,
};
static void __init edmini_v2_init(void)
diff --git a/arch/arm/mach-orion5x/kurobox_pro-setup.c b/arch/arm/mach-orion5x/kurobox_pro-setup.c
index 47497c7..c0eb646 100644
--- a/arch/arm/mach-orion5x/kurobox_pro-setup.c
+++ b/arch/arm/mach-orion5x/kurobox_pro-setup.c
@@ -315,28 +315,28 @@
/*****************************************************************************
* General Setup
****************************************************************************/
-static struct orion5x_mpp_mode kurobox_pro_mpp_modes[] __initdata = {
- { 0, MPP_UNUSED },
- { 1, MPP_UNUSED },
- { 2, MPP_GPIO }, /* GPIO Micon */
- { 3, MPP_GPIO }, /* GPIO Rtc */
- { 4, MPP_UNUSED },
- { 5, MPP_UNUSED },
- { 6, MPP_NAND }, /* NAND Flash REn */
- { 7, MPP_NAND }, /* NAND Flash WEn */
- { 8, MPP_UNUSED },
- { 9, MPP_UNUSED },
- { 10, MPP_UNUSED },
- { 11, MPP_UNUSED },
- { 12, MPP_SATA_LED }, /* SATA 0 presence */
- { 13, MPP_SATA_LED }, /* SATA 1 presence */
- { 14, MPP_SATA_LED }, /* SATA 0 active */
- { 15, MPP_SATA_LED }, /* SATA 1 active */
- { 16, MPP_UART }, /* UART1 RXD */
- { 17, MPP_UART }, /* UART1 TXD */
- { 18, MPP_UART }, /* UART1 CTSn */
- { 19, MPP_UART }, /* UART1 RTSn */
- { -1 },
+static unsigned int kurobox_pro_mpp_modes[] __initdata = {
+ MPP0_UNUSED,
+ MPP1_UNUSED,
+ MPP2_GPIO, /* GPIO Micon */
+ MPP3_GPIO, /* GPIO Rtc */
+ MPP4_UNUSED,
+ MPP5_UNUSED,
+ MPP6_NAND, /* NAND Flash REn */
+ MPP7_NAND, /* NAND Flash WEn */
+ MPP8_UNUSED,
+ MPP9_UNUSED,
+ MPP10_UNUSED,
+ MPP11_UNUSED,
+ MPP12_SATA_LED, /* SATA 0 presence */
+ MPP13_SATA_LED, /* SATA 1 presence */
+ MPP14_SATA_LED, /* SATA 0 active */
+ MPP15_SATA_LED, /* SATA 1 active */
+ MPP16_UART, /* UART1 RXD */
+ MPP17_UART, /* UART1 TXD */
+ MPP18_UART, /* UART1 CTSn */
+ MPP19_UART, /* UART1 RTSn */
+ 0,
};
static void __init kurobox_pro_init(void)
diff --git a/arch/arm/mach-orion5x/ls-chl-setup.c b/arch/arm/mach-orion5x/ls-chl-setup.c
index 6ae12aa..5065803 100644
--- a/arch/arm/mach-orion5x/ls-chl-setup.c
+++ b/arch/arm/mach-orion5x/ls-chl-setup.c
@@ -251,28 +251,28 @@
* GPIO Data
****************************************************************************/
-static struct orion5x_mpp_mode lschl_mpp_modes[] __initdata = {
- { 0, MPP_GPIO }, /* LED POWER */
- { 1, MPP_GPIO }, /* HDD POWER */
- { 2, MPP_GPIO }, /* LED ALARM */
- { 3, MPP_GPIO }, /* LED INFO */
- { 4, MPP_UNUSED },
- { 5, MPP_UNUSED },
- { 6, MPP_GPIO }, /* FAN LOCK */
- { 7, MPP_GPIO }, /* SW INIT */
- { 8, MPP_GPIO }, /* SW POWER */
- { 9, MPP_GPIO }, /* USB POWER */
- { 10, MPP_GPIO }, /* SW AUTO POWER */
- { 11, MPP_UNUSED },
- { 12, MPP_UNUSED },
- { 13, MPP_UNUSED },
- { 14, MPP_GPIO }, /* FAN HIGH */
- { 15, MPP_GPIO }, /* SW FUNC */
- { 16, MPP_GPIO }, /* FAN LOW */
- { 17, MPP_GPIO }, /* LED FUNC */
- { 18, MPP_UNUSED },
- { 19, MPP_UNUSED },
- { -1 },
+static unsigned int lschl_mpp_modes[] __initdata = {
+ MPP0_GPIO, /* LED POWER */
+ MPP1_GPIO, /* HDD POWER */
+ MPP2_GPIO, /* LED ALARM */
+ MPP3_GPIO, /* LED INFO */
+ MPP4_UNUSED,
+ MPP5_UNUSED,
+ MPP6_GPIO, /* FAN LOCK */
+ MPP7_GPIO, /* SW INIT */
+ MPP8_GPIO, /* SW POWER */
+ MPP9_GPIO, /* USB POWER */
+ MPP10_GPIO, /* SW AUTO POWER */
+ MPP11_UNUSED,
+ MPP12_UNUSED,
+ MPP13_UNUSED,
+ MPP14_GPIO, /* FAN HIGH */
+ MPP15_GPIO, /* SW FUNC */
+ MPP16_GPIO, /* FAN LOW */
+ MPP17_GPIO, /* LED FUNC */
+ MPP18_UNUSED,
+ MPP19_UNUSED,
+ 0,
};
static void __init lschl_init(void)
diff --git a/arch/arm/mach-orion5x/ls_hgl-setup.c b/arch/arm/mach-orion5x/ls_hgl-setup.c
index 7adafd7..8503d0a 100644
--- a/arch/arm/mach-orion5x/ls_hgl-setup.c
+++ b/arch/arm/mach-orion5x/ls_hgl-setup.c
@@ -200,28 +200,28 @@
#define LS_HGL_GPIO_HDD_POWER 1
-static struct orion5x_mpp_mode ls_hgl_mpp_modes[] __initdata = {
- { 0, MPP_GPIO }, /* LED_PWR */
- { 1, MPP_GPIO }, /* HDD_PWR */
- { 2, MPP_GPIO }, /* LED_ALARM */
- { 3, MPP_GPIO }, /* LED_INFO */
- { 4, MPP_UNUSED },
- { 5, MPP_UNUSED },
- { 6, MPP_GPIO }, /* FAN_LCK */
- { 7, MPP_GPIO }, /* INIT */
- { 8, MPP_GPIO }, /* POWER */
- { 9, MPP_GPIO }, /* USB_PWR */
- { 10, MPP_GPIO }, /* AUTO_POWER */
- { 11, MPP_UNUSED }, /* LED_ETH (dummy) */
- { 12, MPP_UNUSED },
- { 13, MPP_UNUSED },
- { 14, MPP_UNUSED },
- { 15, MPP_GPIO }, /* FUNC */
- { 16, MPP_UNUSED },
- { 17, MPP_GPIO }, /* LED_FUNC */
- { 18, MPP_UNUSED },
- { 19, MPP_UNUSED },
- { -1 },
+static unsigned int ls_hgl_mpp_modes[] __initdata = {
+ MPP0_GPIO, /* LED_PWR */
+ MPP1_GPIO, /* HDD_PWR */
+ MPP2_GPIO, /* LED_ALARM */
+ MPP3_GPIO, /* LED_INFO */
+ MPP4_UNUSED,
+ MPP5_UNUSED,
+ MPP6_GPIO, /* FAN_LCK */
+ MPP7_GPIO, /* INIT */
+ MPP8_GPIO, /* POWER */
+ MPP9_GPIO, /* USB_PWR */
+ MPP10_GPIO, /* AUTO_POWER */
+ MPP11_UNUSED, /* LED_ETH (dummy) */
+ MPP12_UNUSED,
+ MPP13_UNUSED,
+ MPP14_UNUSED,
+ MPP15_GPIO, /* FUNC */
+ MPP16_UNUSED,
+ MPP17_GPIO, /* LED_FUNC */
+ MPP18_UNUSED,
+ MPP19_UNUSED,
+ 0,
};
static void __init ls_hgl_init(void)
diff --git a/arch/arm/mach-orion5x/lsmini-setup.c b/arch/arm/mach-orion5x/lsmini-setup.c
index 869958f..9c82723 100644
--- a/arch/arm/mach-orion5x/lsmini-setup.c
+++ b/arch/arm/mach-orion5x/lsmini-setup.c
@@ -201,28 +201,28 @@
#define LSMINI_GPIO_HDD_POWER0 1
#define LSMINI_GPIO_HDD_POWER1 19
-static struct orion5x_mpp_mode lsmini_mpp_modes[] __initdata = {
- { 0, MPP_UNUSED }, /* LED_RESERVE1 (unused) */
- { 1, MPP_GPIO }, /* HDD_PWR */
- { 2, MPP_GPIO }, /* LED_ALARM */
- { 3, MPP_GPIO }, /* LED_INFO */
- { 4, MPP_UNUSED },
- { 5, MPP_UNUSED },
- { 6, MPP_UNUSED },
- { 7, MPP_UNUSED },
- { 8, MPP_UNUSED },
- { 9, MPP_GPIO }, /* LED_FUNC */
- { 10, MPP_UNUSED },
- { 11, MPP_UNUSED }, /* LED_ETH (dummy) */
- { 12, MPP_UNUSED },
- { 13, MPP_UNUSED },
- { 14, MPP_GPIO }, /* LED_PWR */
- { 15, MPP_GPIO }, /* FUNC */
- { 16, MPP_GPIO }, /* USB_PWR */
- { 17, MPP_GPIO }, /* AUTO_POWER */
- { 18, MPP_GPIO }, /* POWER */
- { 19, MPP_GPIO }, /* HDD_PWR1 */
- { -1 },
+static unsigned int lsmini_mpp_modes[] __initdata = {
+ MPP0_UNUSED, /* LED_RESERVE1 (unused) */
+ MPP1_GPIO, /* HDD_PWR */
+ MPP2_GPIO, /* LED_ALARM */
+ MPP3_GPIO, /* LED_INFO */
+ MPP4_UNUSED,
+ MPP5_UNUSED,
+ MPP6_UNUSED,
+ MPP7_UNUSED,
+ MPP8_UNUSED,
+ MPP9_GPIO, /* LED_FUNC */
+ MPP10_UNUSED,
+ MPP11_UNUSED, /* LED_ETH (dummy) */
+ MPP12_UNUSED,
+ MPP13_UNUSED,
+ MPP14_GPIO, /* LED_PWR */
+ MPP15_GPIO, /* FUNC */
+ MPP16_GPIO, /* USB_PWR */
+ MPP17_GPIO, /* AUTO_POWER */
+ MPP18_GPIO, /* POWER */
+ MPP19_GPIO, /* HDD_PWR1 */
+ 0,
};
static void __init lsmini_init(void)
diff --git a/arch/arm/mach-orion5x/mpp.c b/arch/arm/mach-orion5x/mpp.c
index 2288207..f12c41b 100644
--- a/arch/arm/mach-orion5x/mpp.c
+++ b/arch/arm/mach-orion5x/mpp.c
@@ -12,154 +12,34 @@
#include <linux/init.h>
#include <linux/mbus.h>
#include <linux/io.h>
-#include <asm/gpio.h>
#include <mach/hardware.h>
-#include "common.h"
+#include <plat/mpp.h>
#include "mpp.h"
+#include "common.h"
-static int is_5181l(void)
+static unsigned int __init orion5x_variant(void)
{
u32 dev;
u32 rev;
orion5x_pcie_id(&dev, &rev);
- return !!(dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0);
+ if (dev == MV88F5181_DEV_ID && rev >= MV88F5181L_REV_A0)
+ return MPP_F5181_MASK;
+
+ if (dev == MV88F5182_DEV_ID)
+ return MPP_F5182_MASK;
+
+ if (dev == MV88F5281_DEV_ID)
+ return MPP_F5281_MASK;
+
+ printk(KERN_ERR "MPP setup: unknown orion5x variant "
+ "(dev %#x rev %#x)\n", dev, rev);
+ return 0;
}
-static int is_5182(void)
+void __init orion5x_mpp_conf(unsigned int *mpp_list)
{
- u32 dev;
- u32 rev;
-
- orion5x_pcie_id(&dev, &rev);
-
- return !!(dev == MV88F5182_DEV_ID);
-}
-
-static int is_5281(void)
-{
- u32 dev;
- u32 rev;
-
- orion5x_pcie_id(&dev, &rev);
-
- return !!(dev == MV88F5281_DEV_ID);
-}
-
-static int __init determine_type_encoding(int mpp, enum orion5x_mpp_type type)
-{
- switch (type) {
- case MPP_UNUSED:
- case MPP_GPIO:
- if (mpp == 0)
- return 3;
- if (mpp >= 1 && mpp <= 15)
- return 0;
- if (mpp >= 16 && mpp <= 19) {
- if (is_5182())
- return 5;
- if (type == MPP_UNUSED)
- return 0;
- }
- return -1;
-
- case MPP_PCIE_RST_OUTn:
- if (mpp == 0)
- return 0;
- return -1;
-
- case MPP_PCI_ARB:
- if (mpp >= 0 && mpp <= 7)
- return 2;
- return -1;
-
- case MPP_PCI_PMEn:
- if (mpp == 2)
- return 3;
- return -1;
-
- case MPP_GIGE:
- if (mpp >= 8 && mpp <= 19)
- return 1;
- return -1;
-
- case MPP_NAND:
- if (is_5182() || is_5281()) {
- if (mpp >= 4 && mpp <= 7)
- return 4;
- if (mpp >= 12 && mpp <= 17)
- return 4;
- }
- return -1;
-
- case MPP_PCI_CLK:
- if (is_5181l() && mpp >= 6 && mpp <= 7)
- return 5;
- return -1;
-
- case MPP_SATA_LED:
- if (is_5182()) {
- if (mpp >= 4 && mpp <= 7)
- return 5;
- if (mpp >= 12 && mpp <= 15)
- return 5;
- }
- return -1;
-
- case MPP_UART:
- if (mpp >= 16 && mpp <= 19)
- return 0;
- return -1;
- }
-
- printk(KERN_INFO "unknown MPP type %d\n", type);
-
- return -1;
-}
-
-void __init orion5x_mpp_conf(struct orion5x_mpp_mode *mode)
-{
- u32 mpp_0_7_ctrl = readl(MPP_0_7_CTRL);
- u32 mpp_8_15_ctrl = readl(MPP_8_15_CTRL);
- u32 mpp_16_19_ctrl = readl(MPP_16_19_CTRL);
-
- for ( ; mode->mpp >= 0; mode++) {
- u32 *reg;
- int num_type;
- int shift;
-
- if (mode->mpp >= 0 && mode->mpp <= 7)
- reg = &mpp_0_7_ctrl;
- else if (mode->mpp >= 8 && mode->mpp <= 15)
- reg = &mpp_8_15_ctrl;
- else if (mode->mpp >= 16 && mode->mpp <= 19)
- reg = &mpp_16_19_ctrl;
- else {
- printk(KERN_ERR "orion5x_mpp_conf: invalid MPP "
- "(%d)\n", mode->mpp);
- continue;
- }
-
- num_type = determine_type_encoding(mode->mpp, mode->type);
- if (num_type < 0) {
- printk(KERN_ERR "orion5x_mpp_conf: invalid MPP "
- "combination (%d, %d)\n", mode->mpp,
- mode->type);
- continue;
- }
-
- shift = (mode->mpp & 7) << 2;
- *reg &= ~(0xf << shift);
- *reg |= (num_type & 0xf) << shift;
-
- if (mode->type == MPP_UNUSED && (mode->mpp < 16 || is_5182()))
- orion_gpio_set_unused(mode->mpp);
-
- orion_gpio_set_valid(mode->mpp, !!(mode->type == MPP_GPIO));
- }
-
- writel(mpp_0_7_ctrl, MPP_0_7_CTRL);
- writel(mpp_8_15_ctrl, MPP_8_15_CTRL);
- writel(mpp_16_19_ctrl, MPP_16_19_CTRL);
+ orion_mpp_conf(mpp_list, orion5x_variant(),
+ MPP_MAX, ORION5X_DEV_BUS_VIRT_BASE);
}
diff --git a/arch/arm/mach-orion5x/mpp.h b/arch/arm/mach-orion5x/mpp.h
index 290e610..eac6897 100644
--- a/arch/arm/mach-orion5x/mpp.h
+++ b/arch/arm/mach-orion5x/mpp.h
@@ -1,74 +1,129 @@
#ifndef __ARCH_ORION5X_MPP_H
#define __ARCH_ORION5X_MPP_H
-enum orion5x_mpp_type {
- /*
- * This MPP is unused.
- */
- MPP_UNUSED,
+#define MPP(_num, _sel, _in, _out, _F5181l, _F5182, _F5281) ( \
+ /* MPP number */ ((_num) & 0xff) | \
+ /* MPP select value */ (((_sel) & 0xf) << 8) | \
+ /* may be input signal */ ((!!(_in)) << 12) | \
+ /* may be output signal */ ((!!(_out)) << 13) | \
+ /* available on F5181l */ ((!!(_F5181l)) << 14) | \
+ /* available on F5182 */ ((!!(_F5182)) << 15) | \
+ /* available on F5281 */ ((!!(_F5281)) << 16))
- /*
- * This MPP pin is used as a generic GPIO pin. Valid for
- * MPPs 0-15 and device bus data pins 16-31. On 5182, also
- * valid for MPPs 16-19.
- */
- MPP_GPIO,
+ /* num sel i o 5181 5182 5281 */
- /*
- * This MPP is used as PCIe_RST_OUTn pin. Valid for
- * MPP 0 only.
- */
- MPP_PCIE_RST_OUTn,
+#define MPP_F5181_MASK MPP(0, 0x0, 0, 0, 1, 0, 0)
+#define MPP_F5182_MASK MPP(0, 0x0, 0, 0, 0, 1, 0)
+#define MPP_F5281_MASK MPP(0, 0x0, 0, 0, 0, 0, 1)
- /*
- * This MPP is used as PCI arbiter pin (REQn/GNTn).
- * Valid for MPPs 0-7 only.
- */
- MPP_PCI_ARB,
+#define MPP0_UNUSED MPP(0, 0x3, 0, 0, 1, 1, 1)
+#define MPP0_GPIO MPP(0, 0x3, 1, 1, 1, 1, 1)
+#define MPP0_PCIE_RST_OUTn MPP(0, 0x0, 0, 0, 1, 1, 1)
+#define MPP0_PCI_ARB MPP(0, 0x2, 0, 0, 1, 1, 1)
- /*
- * This MPP is used as PCI_PMEn pin. Valid for MPP 2 only.
- */
- MPP_PCI_PMEn,
+#define MPP1_UNUSED MPP(1, 0x0, 0, 0, 1, 1, 1)
+#define MPP1_GPIO MPP(1, 0x0, 1, 1, 1, 1, 1)
+#define MPP1_PCI_ARB MPP(1, 0x2, 0, 0, 1, 1, 1)
- /*
- * This MPP is used as GigE half-duplex (COL, CRS) or GMII
- * (RXERR, CRS, TXERR, TXD[7:4], RXD[7:4]) pin. Valid for
- * MPPs 8-19 only.
- */
- MPP_GIGE,
+#define MPP2_UNUSED MPP(2, 0x0, 0, 0, 1, 1, 1)
+#define MPP2_GPIO MPP(2, 0x0, 1, 1, 1, 1, 1)
+#define MPP2_PCI_ARB MPP(2, 0x2, 0, 0, 1, 1, 1)
+#define MPP2_PCI_PMEn MPP(2, 0x3, 0, 0, 1, 1, 1)
- /*
- * This MPP is used as NAND REn/WEn pin. Valid for MPPs
- * 4-7 and 12-17 only, and only on the 5181l/5182/5281.
- */
- MPP_NAND,
+#define MPP3_UNUSED MPP(3, 0x0, 0, 0, 1, 1, 1)
+#define MPP3_GPIO MPP(3, 0x0, 1, 1, 1, 1, 1)
+#define MPP3_PCI_ARB MPP(3, 0x2, 0, 0, 1, 1, 1)
- /*
- * This MPP is used as a PCI clock output pin. Valid for
- * MPPs 6-7 only, and only on the 5181l.
- */
- MPP_PCI_CLK,
+#define MPP4_UNUSED MPP(4, 0x0, 0, 0, 1, 1, 1)
+#define MPP4_GPIO MPP(4, 0x0, 1, 1, 1, 1, 1)
+#define MPP4_PCI_ARB MPP(4, 0x2, 0, 0, 1, 1, 1)
+#define MPP4_NAND MPP(4, 0x4, 0, 0, 0, 1, 1)
+#define MPP4_SATA_LED MPP(4, 0x5, 0, 0, 0, 1, 0)
- /*
- * This MPP is used as a SATA presence/activity LED.
- * Valid for MPPs 4-7 and 12-15 only, and only on the 5182.
- */
- MPP_SATA_LED,
+#define MPP5_UNUSED MPP(5, 0x0, 0, 0, 1, 1, 1)
+#define MPP5_GPIO MPP(5, 0x0, 1, 1, 1, 1, 1)
+#define MPP5_PCI_ARB MPP(5, 0x2, 0, 0, 1, 1, 1)
+#define MPP5_NAND MPP(5, 0x4, 0, 0, 0, 1, 1)
+#define MPP5_SATA_LED MPP(5, 0x5, 0, 0, 0, 1, 0)
- /*
- * This MPP is used as UART1 RXD/TXD/CTSn/RTSn pin.
- * Valid for MPPs 16-19 only.
- */
- MPP_UART,
-};
+#define MPP6_UNUSED MPP(6, 0x0, 0, 0, 1, 1, 1)
+#define MPP6_GPIO MPP(6, 0x0, 1, 1, 1, 1, 1)
+#define MPP6_PCI_ARB MPP(6, 0x2, 0, 0, 1, 1, 1)
+#define MPP6_NAND MPP(6, 0x4, 0, 0, 0, 1, 1)
+#define MPP6_PCI_CLK MPP(6, 0x5, 0, 0, 1, 0, 0)
+#define MPP6_SATA_LED MPP(6, 0x5, 0, 0, 0, 1, 0)
-struct orion5x_mpp_mode {
- int mpp;
- enum orion5x_mpp_type type;
-};
+#define MPP7_UNUSED MPP(7, 0x0, 0, 0, 1, 1, 1)
+#define MPP7_GPIO MPP(7, 0x0, 1, 1, 1, 1, 1)
+#define MPP7_PCI_ARB MPP(7, 0x2, 0, 0, 1, 1, 1)
+#define MPP7_NAND MPP(7, 0x4, 0, 0, 0, 1, 1)
+#define MPP7_PCI_CLK MPP(7, 0x5, 0, 0, 1, 0, 0)
+#define MPP7_SATA_LED MPP(7, 0x5, 0, 0, 0, 1, 0)
-void orion5x_mpp_conf(struct orion5x_mpp_mode *mode);
+#define MPP8_UNUSED MPP(8, 0x0, 0, 0, 1, 1, 1)
+#define MPP8_GPIO MPP(8, 0x0, 1, 1, 1, 1, 1)
+#define MPP8_GIGE MPP(8, 0x1, 0, 0, 1, 1, 1)
+#define MPP9_UNUSED MPP(9, 0x0, 0, 0, 1, 1, 1)
+#define MPP9_GPIO MPP(9, 0x0, 0, 0, 1, 1, 1)
+#define MPP9_GIGE MPP(9, 0x1, 1, 1, 1, 1, 1)
+
+#define MPP10_UNUSED MPP(10, 0x0, 0, 0, 1, 1, 1)
+#define MPP10_GPIO MPP(10, 0x0, 1, 1, 1, 1, 1)
+#define MPP10_GIGE MPP(10, 0x1, 0, 0, 1, 1, 1)
+
+#define MPP11_UNUSED MPP(11, 0x0, 0, 0, 1, 1, 1)
+#define MPP11_GPIO MPP(11, 0x0, 1, 1, 1, 1, 1)
+#define MPP11_GIGE MPP(11, 0x1, 0, 0, 1, 1, 1)
+
+#define MPP12_UNUSED MPP(12, 0x0, 0, 0, 1, 1, 1)
+#define MPP12_GPIO MPP(12, 0x0, 1, 1, 1, 1, 1)
+#define MPP12_GIGE MPP(12, 0x1, 0, 0, 1, 1, 1)
+#define MPP12_NAND MPP(12, 0x4, 0, 0, 0, 1, 1)
+#define MPP12_SATA_LED MPP(12, 0x5, 0, 0, 0, 1, 0)
+
+#define MPP13_UNUSED MPP(13, 0x0, 0, 0, 1, 1, 1)
+#define MPP13_GPIO MPP(13, 0x0, 1, 1, 1, 1, 1)
+#define MPP13_GIGE MPP(13, 0x1, 0, 0, 1, 1, 1)
+#define MPP13_NAND MPP(13, 0x4, 0, 0, 0, 1, 1)
+#define MPP13_SATA_LED MPP(13, 0x5, 0, 0, 0, 1, 0)
+
+#define MPP14_UNUSED MPP(14, 0x0, 0, 0, 1, 1, 1)
+#define MPP14_GPIO MPP(14, 0x0, 1, 1, 1, 1, 1)
+#define MPP14_GIGE MPP(14, 0x1, 0, 0, 1, 1, 1)
+#define MPP14_NAND MPP(14, 0x4, 0, 0, 0, 1, 1)
+#define MPP14_SATA_LED MPP(14, 0x5, 0, 0, 0, 1, 0)
+
+#define MPP15_UNUSED MPP(15, 0x0, 0, 0, 1, 1, 1)
+#define MPP15_GPIO MPP(15, 0x0, 1, 1, 1, 1, 1)
+#define MPP15_GIGE MPP(15, 0x1, 0, 0, 1, 1, 1)
+#define MPP15_NAND MPP(15, 0x4, 0, 0, 0, 1, 1)
+#define MPP15_SATA_LED MPP(15, 0x5, 0, 0, 0, 1, 0)
+
+#define MPP16_UNUSED MPP(16, 0x0, 0, 0, 1, 1, 1)
+#define MPP16_GPIO MPP(16, 0x5, 1, 1, 0, 1, 0)
+#define MPP16_GIGE MPP(16, 0x1, 0, 0, 1, 1, 1)
+#define MPP16_NAND MPP(16, 0x4, 0, 0, 0, 1, 1)
+#define MPP16_UART MPP(16, 0x0, 0, 0, 0, 1, 1)
+
+#define MPP17_UNUSED MPP(17, 0x0, 0, 0, 1, 1, 1)
+#define MPP17_GPIO MPP(17, 0x5, 1, 1, 0, 1, 0)
+#define MPP17_GIGE MPP(17, 0x1, 0, 0, 1, 1, 1)
+#define MPP17_NAND MPP(17, 0x4, 0, 0, 0, 1, 1)
+#define MPP17_UART MPP(17, 0x0, 0, 0, 0, 1, 1)
+
+#define MPP18_UNUSED MPP(18, 0x0, 0, 0, 1, 1, 1)
+#define MPP18_GPIO MPP(18, 0x5, 1, 1, 0, 1, 0)
+#define MPP18_GIGE MPP(18, 0x1, 0, 0, 1, 1, 1)
+#define MPP18_UART MPP(18, 0x0, 0, 0, 0, 1, 1)
+
+#define MPP19_UNUSED MPP(19, 0x0, 0, 0, 1, 1, 1)
+#define MPP19_GPIO MPP(19, 0x5, 1, 1, 0, 1, 0)
+#define MPP19_GIGE MPP(19, 0x1, 0, 0, 1, 1, 1)
+#define MPP19_UART MPP(19, 0x0, 0, 0, 0, 1, 1)
+
+#define MPP_MAX 19
+
+void orion5x_mpp_conf(unsigned int *mpp_list);
#endif
diff --git a/arch/arm/mach-orion5x/mss2-setup.c b/arch/arm/mach-orion5x/mss2-setup.c
index b43b208..59263b7 100644
--- a/arch/arm/mach-orion5x/mss2-setup.c
+++ b/arch/arm/mach-orion5x/mss2-setup.c
@@ -193,28 +193,28 @@
/****************************************************************************
* General Setup
****************************************************************************/
-static struct orion5x_mpp_mode mss2_mpp_modes[] __initdata = {
- { 0, MPP_GPIO }, /* Power LED */
- { 1, MPP_GPIO }, /* Error LED */
- { 2, MPP_UNUSED },
- { 3, MPP_GPIO }, /* RTC interrupt */
- { 4, MPP_GPIO }, /* HDD ind. (Single/Dual)*/
- { 5, MPP_GPIO }, /* HD0 5V control */
- { 6, MPP_GPIO }, /* HD0 12V control */
- { 7, MPP_GPIO }, /* HD1 5V control */
- { 8, MPP_GPIO }, /* HD1 12V control */
- { 9, MPP_UNUSED },
- { 10, MPP_GPIO }, /* Fan control */
- { 11, MPP_GPIO }, /* Power button */
- { 12, MPP_GPIO }, /* Reset button */
- { 13, MPP_UNUSED },
- { 14, MPP_SATA_LED }, /* SATA 0 active */
- { 15, MPP_SATA_LED }, /* SATA 1 active */
- { 16, MPP_UNUSED },
- { 17, MPP_UNUSED },
- { 18, MPP_UNUSED },
- { 19, MPP_UNUSED },
- { -1 },
+static unsigned int mss2_mpp_modes[] __initdata = {
+ MPP0_GPIO, /* Power LED */
+ MPP1_GPIO, /* Error LED */
+ MPP2_UNUSED,
+ MPP3_GPIO, /* RTC interrupt */
+ MPP4_GPIO, /* HDD ind. (Single/Dual)*/
+ MPP5_GPIO, /* HD0 5V control */
+ MPP6_GPIO, /* HD0 12V control */
+ MPP7_GPIO, /* HD1 5V control */
+ MPP8_GPIO, /* HD1 12V control */
+ MPP9_UNUSED,
+ MPP10_GPIO, /* Fan control */
+ MPP11_GPIO, /* Power button */
+ MPP12_GPIO, /* Reset button */
+ MPP13_UNUSED,
+ MPP14_SATA_LED, /* SATA 0 active */
+ MPP15_SATA_LED, /* SATA 1 active */
+ MPP16_UNUSED,
+ MPP17_UNUSED,
+ MPP18_UNUSED,
+ MPP19_UNUSED,
+ 0,
};
static void __init mss2_init(void)
diff --git a/arch/arm/mach-orion5x/mv2120-setup.c b/arch/arm/mach-orion5x/mv2120-setup.c
index c55d071..63ff10c 100644
--- a/arch/arm/mach-orion5x/mv2120-setup.c
+++ b/arch/arm/mach-orion5x/mv2120-setup.c
@@ -108,28 +108,28 @@
/****************************************************************************
* General Setup
****************************************************************************/
-static struct orion5x_mpp_mode mv2120_mpp_modes[] __initdata = {
- { 0, MPP_GPIO }, /* Sys status LED */
- { 1, MPP_GPIO }, /* Sys error LED */
- { 2, MPP_GPIO }, /* OverTemp interrupt */
- { 3, MPP_GPIO }, /* RTC interrupt */
- { 4, MPP_GPIO }, /* V_LED 5V */
- { 5, MPP_GPIO }, /* V_LED 3.3V */
- { 6, MPP_UNUSED },
- { 7, MPP_UNUSED },
- { 8, MPP_GPIO }, /* SATA 0 fail LED */
- { 9, MPP_GPIO }, /* SATA 1 fail LED */
- { 10, MPP_UNUSED },
- { 11, MPP_UNUSED },
- { 12, MPP_SATA_LED }, /* SATA 0 presence */
- { 13, MPP_SATA_LED }, /* SATA 1 presence */
- { 14, MPP_SATA_LED }, /* SATA 0 active */
- { 15, MPP_SATA_LED }, /* SATA 1 active */
- { 16, MPP_UNUSED },
- { 17, MPP_GPIO }, /* Reset button */
- { 18, MPP_GPIO }, /* Power button */
- { 19, MPP_GPIO }, /* Power off */
- { -1 },
+static unsigned int mv2120_mpp_modes[] __initdata = {
+ MPP0_GPIO, /* Sys status LED */
+ MPP1_GPIO, /* Sys error LED */
+ MPP2_GPIO, /* OverTemp interrupt */
+ MPP3_GPIO, /* RTC interrupt */
+ MPP4_GPIO, /* V_LED 5V */
+ MPP5_GPIO, /* V_LED 3.3V */
+ MPP6_UNUSED,
+ MPP7_UNUSED,
+ MPP8_GPIO, /* SATA 0 fail LED */
+ MPP9_GPIO, /* SATA 1 fail LED */
+ MPP10_UNUSED,
+ MPP11_UNUSED,
+ MPP12_SATA_LED, /* SATA 0 presence */
+ MPP13_SATA_LED, /* SATA 1 presence */
+ MPP14_SATA_LED, /* SATA 0 active */
+ MPP15_SATA_LED, /* SATA 1 active */
+ MPP16_UNUSED,
+ MPP17_GPIO, /* Reset button */
+ MPP18_GPIO, /* Power button */
+ MPP19_GPIO, /* Power off */
+ 0,
};
static struct i2c_board_info __initdata mv2120_i2c_rtc = {
diff --git a/arch/arm/mach-orion5x/net2big-setup.c b/arch/arm/mach-orion5x/net2big-setup.c
index a5930f8..e43b39c 100644
--- a/arch/arm/mach-orion5x/net2big-setup.c
+++ b/arch/arm/mach-orion5x/net2big-setup.c
@@ -339,28 +339,28 @@
* General Setup
****************************************************************************/
-static struct orion5x_mpp_mode net2big_mpp_modes[] __initdata = {
- { 0, MPP_GPIO }, /* Raid mode (bit 0) */
- { 1, MPP_GPIO }, /* USB port 2 fuse (0 = Fail, 1 = Ok) */
- { 2, MPP_GPIO }, /* Raid mode (bit 1) */
- { 3, MPP_GPIO }, /* Board ID (bit 0) */
- { 4, MPP_GPIO }, /* Fan activity (0 = Off, 1 = On) */
- { 5, MPP_GPIO }, /* Fan fail detection */
- { 6, MPP_GPIO }, /* Red front LED (0 = Off, 1 = On) */
- { 7, MPP_GPIO }, /* Disable initial blinking on front LED */
- { 8, MPP_GPIO }, /* Rear power switch (on|auto) */
- { 9, MPP_GPIO }, /* Rear power switch (auto|off) */
- { 10, MPP_GPIO }, /* SATA 1 red LED (0 = Off, 1 = On) */
- { 11, MPP_GPIO }, /* SATA 0 red LED (0 = Off, 1 = On) */
- { 12, MPP_GPIO }, /* Board ID (bit 1) */
- { 13, MPP_GPIO }, /* SATA 1 blue LED blink control */
- { 14, MPP_SATA_LED },
- { 15, MPP_SATA_LED },
- { 16, MPP_GPIO }, /* Blue front LED control */
- { 17, MPP_GPIO }, /* SATA 0 blue LED blink control */
- { 18, MPP_GPIO }, /* Front button (0 = Released, 1 = Pushed ) */
- { 19, MPP_GPIO }, /* SATA{0,1} power On/Off request */
- { -1 }
+static unsigned int net2big_mpp_modes[] __initdata = {
+ MPP0_GPIO, /* Raid mode (bit 0) */
+ MPP1_GPIO, /* USB port 2 fuse (0 = Fail, 1 = Ok) */
+ MPP2_GPIO, /* Raid mode (bit 1) */
+ MPP3_GPIO, /* Board ID (bit 0) */
+ MPP4_GPIO, /* Fan activity (0 = Off, 1 = On) */
+ MPP5_GPIO, /* Fan fail detection */
+ MPP6_GPIO, /* Red front LED (0 = Off, 1 = On) */
+ MPP7_GPIO, /* Disable initial blinking on front LED */
+ MPP8_GPIO, /* Rear power switch (on|auto) */
+ MPP9_GPIO, /* Rear power switch (auto|off) */
+ MPP10_GPIO, /* SATA 1 red LED (0 = Off, 1 = On) */
+ MPP11_GPIO, /* SATA 0 red LED (0 = Off, 1 = On) */
+ MPP12_GPIO, /* Board ID (bit 1) */
+ MPP13_GPIO, /* SATA 1 blue LED blink control */
+ MPP14_SATA_LED,
+ MPP15_SATA_LED,
+ MPP16_GPIO, /* Blue front LED control */
+ MPP17_GPIO, /* SATA 0 blue LED blink control */
+ MPP18_GPIO, /* Front button (0 = Released, 1 = Pushed ) */
+ MPP19_GPIO, /* SATA{0,1} power On/Off request */
+ 0,
/* 22: USB port 1 fuse (0 = Fail, 1 = Ok) */
/* 23: SATA 0 power status */
/* 24: Board power off */
diff --git a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
index 34310ab..9eec7c2 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-fxo-setup.c
@@ -64,28 +64,28 @@
/*****************************************************************************
* General Setup
****************************************************************************/
-static struct orion5x_mpp_mode rd88f5181l_fxo_mpp_modes[] __initdata = {
- { 0, MPP_GPIO }, /* LED1 CardBus LED (front panel) */
- { 1, MPP_GPIO }, /* PCI_intA */
- { 2, MPP_GPIO }, /* Hard Reset / Factory Init*/
- { 3, MPP_GPIO }, /* FXS or DAA select */
- { 4, MPP_GPIO }, /* LED6 - phone LED (front panel) */
- { 5, MPP_GPIO }, /* LED5 - phone LED (front panel) */
- { 6, MPP_PCI_CLK }, /* CPU PCI refclk */
- { 7, MPP_PCI_CLK }, /* PCI/PCIe refclk */
- { 8, MPP_GPIO }, /* CardBus reset */
- { 9, MPP_GPIO }, /* GE_RXERR */
- { 10, MPP_GPIO }, /* LED2 MiniPCI LED (front panel) */
- { 11, MPP_GPIO }, /* Lifeline control */
- { 12, MPP_GIGE }, /* GE_TXD[4] */
- { 13, MPP_GIGE }, /* GE_TXD[5] */
- { 14, MPP_GIGE }, /* GE_TXD[6] */
- { 15, MPP_GIGE }, /* GE_TXD[7] */
- { 16, MPP_GIGE }, /* GE_RXD[4] */
- { 17, MPP_GIGE }, /* GE_RXD[5] */
- { 18, MPP_GIGE }, /* GE_RXD[6] */
- { 19, MPP_GIGE }, /* GE_RXD[7] */
- { -1 },
+static unsigned int rd88f5181l_fxo_mpp_modes[] __initdata = {
+ MPP0_GPIO, /* LED1 CardBus LED (front panel) */
+ MPP1_GPIO, /* PCI_intA */
+ MPP2_GPIO, /* Hard Reset / Factory Init*/
+ MPP3_GPIO, /* FXS or DAA select */
+ MPP4_GPIO, /* LED6 - phone LED (front panel) */
+ MPP5_GPIO, /* LED5 - phone LED (front panel) */
+ MPP6_PCI_CLK, /* CPU PCI refclk */
+ MPP7_PCI_CLK, /* PCI/PCIe refclk */
+ MPP8_GPIO, /* CardBus reset */
+ MPP9_GPIO, /* GE_RXERR */
+ MPP10_GPIO, /* LED2 MiniPCI LED (front panel) */
+ MPP11_GPIO, /* Lifeline control */
+ MPP12_GIGE, /* GE_TXD[4] */
+ MPP13_GIGE, /* GE_TXD[5] */
+ MPP14_GIGE, /* GE_TXD[6] */
+ MPP15_GIGE, /* GE_TXD[7] */
+ MPP16_GIGE, /* GE_RXD[4] */
+ MPP17_GIGE, /* GE_RXD[5] */
+ MPP18_GIGE, /* GE_RXD[6] */
+ MPP19_GIGE, /* GE_RXD[7] */
+ 0,
};
static struct mv643xx_eth_platform_data rd88f5181l_fxo_eth_data = {
diff --git a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
index c1f79fa..0cc90bbf 100644
--- a/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5181l-ge-setup.c
@@ -65,28 +65,28 @@
/*****************************************************************************
* General Setup
****************************************************************************/
-static struct orion5x_mpp_mode rd88f5181l_ge_mpp_modes[] __initdata = {
- { 0, MPP_GPIO }, /* LED1 */
- { 1, MPP_GPIO }, /* LED5 */
- { 2, MPP_GPIO }, /* LED4 */
- { 3, MPP_GPIO }, /* LED3 */
- { 4, MPP_GPIO }, /* PCI_intA */
- { 5, MPP_GPIO }, /* RTC interrupt */
- { 6, MPP_PCI_CLK }, /* CPU PCI refclk */
- { 7, MPP_PCI_CLK }, /* PCI/PCIe refclk */
- { 8, MPP_GPIO }, /* 88e6131 interrupt */
- { 9, MPP_GPIO }, /* GE_RXERR */
- { 10, MPP_GPIO }, /* PCI_intB */
- { 11, MPP_GPIO }, /* LED2 */
- { 12, MPP_GIGE }, /* GE_TXD[4] */
- { 13, MPP_GIGE }, /* GE_TXD[5] */
- { 14, MPP_GIGE }, /* GE_TXD[6] */
- { 15, MPP_GIGE }, /* GE_TXD[7] */
- { 16, MPP_GIGE }, /* GE_RXD[4] */
- { 17, MPP_GIGE }, /* GE_RXD[5] */
- { 18, MPP_GIGE }, /* GE_RXD[6] */
- { 19, MPP_GIGE }, /* GE_RXD[7] */
- { -1 },
+static unsigned int rd88f5181l_ge_mpp_modes[] __initdata = {
+ MPP0_GPIO, /* LED1 */
+ MPP1_GPIO, /* LED5 */
+ MPP2_GPIO, /* LED4 */
+ MPP3_GPIO, /* LED3 */
+ MPP4_GPIO, /* PCI_intA */
+ MPP5_GPIO, /* RTC interrupt */
+ MPP6_PCI_CLK, /* CPU PCI refclk */
+ MPP7_PCI_CLK, /* PCI/PCIe refclk */
+ MPP8_GPIO, /* 88e6131 interrupt */
+ MPP9_GPIO, /* GE_RXERR */
+ MPP10_GPIO, /* PCI_intB */
+ MPP11_GPIO, /* LED2 */
+ MPP12_GIGE, /* GE_TXD[4] */
+ MPP13_GIGE, /* GE_TXD[5] */
+ MPP14_GIGE, /* GE_TXD[6] */
+ MPP15_GIGE, /* GE_TXD[7] */
+ MPP16_GIGE, /* GE_RXD[4] */
+ MPP17_GIGE, /* GE_RXD[5] */
+ MPP18_GIGE, /* GE_RXD[6] */
+ MPP19_GIGE, /* GE_RXD[7] */
+ 0,
};
static struct mv643xx_eth_platform_data rd88f5181l_ge_eth_data = {
diff --git a/arch/arm/mach-orion5x/rd88f5182-setup.c b/arch/arm/mach-orion5x/rd88f5182-setup.c
index 4fc4677..48da39b 100644
--- a/arch/arm/mach-orion5x/rd88f5182-setup.c
+++ b/arch/arm/mach-orion5x/rd88f5182-setup.c
@@ -241,28 +241,28 @@
/*****************************************************************************
* General Setup
****************************************************************************/
-static struct orion5x_mpp_mode rd88f5182_mpp_modes[] __initdata = {
- { 0, MPP_GPIO }, /* Debug Led */
- { 1, MPP_GPIO }, /* Reset Switch */
- { 2, MPP_UNUSED },
- { 3, MPP_GPIO }, /* RTC Int */
- { 4, MPP_GPIO },
- { 5, MPP_GPIO },
- { 6, MPP_GPIO }, /* PCI_intA */
- { 7, MPP_GPIO }, /* PCI_intB */
- { 8, MPP_UNUSED },
- { 9, MPP_UNUSED },
- { 10, MPP_UNUSED },
- { 11, MPP_UNUSED },
- { 12, MPP_SATA_LED }, /* SATA 0 presence */
- { 13, MPP_SATA_LED }, /* SATA 1 presence */
- { 14, MPP_SATA_LED }, /* SATA 0 active */
- { 15, MPP_SATA_LED }, /* SATA 1 active */
- { 16, MPP_UNUSED },
- { 17, MPP_UNUSED },
- { 18, MPP_UNUSED },
- { 19, MPP_UNUSED },
- { -1 },
+static unsigned int rd88f5182_mpp_modes[] __initdata = {
+ MPP0_GPIO, /* Debug Led */
+ MPP1_GPIO, /* Reset Switch */
+ MPP2_UNUSED,
+ MPP3_GPIO, /* RTC Int */
+ MPP4_GPIO,
+ MPP5_GPIO,
+ MPP6_GPIO, /* PCI_intA */
+ MPP7_GPIO, /* PCI_intB */
+ MPP8_UNUSED,
+ MPP9_UNUSED,
+ MPP10_UNUSED,
+ MPP11_UNUSED,
+ MPP12_SATA_LED, /* SATA 0 presence */
+ MPP13_SATA_LED, /* SATA 1 presence */
+ MPP14_SATA_LED, /* SATA 0 active */
+ MPP15_SATA_LED, /* SATA 1 active */
+ MPP16_UNUSED,
+ MPP17_UNUSED,
+ MPP18_UNUSED,
+ MPP19_UNUSED,
+ 0,
};
static void __init rd88f5182_init(void)
diff --git a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
index b080c69..ad2eba9 100644
--- a/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
+++ b/arch/arm/mach-orion5x/rd88f6183ap-ge-setup.c
@@ -27,7 +27,6 @@
#include <asm/mach/pci.h>
#include <mach/orion5x.h>
#include "common.h"
-#include "mpp.h"
static struct mv643xx_eth_platform_data rd88f6183ap_ge_eth_data = {
.phy_addr = -1,
diff --git a/arch/arm/mach-orion5x/terastation_pro2-setup.c b/arch/arm/mach-orion5x/terastation_pro2-setup.c
index 6160041..29ce826 100644
--- a/arch/arm/mach-orion5x/terastation_pro2-setup.c
+++ b/arch/arm/mach-orion5x/terastation_pro2-setup.c
@@ -295,28 +295,28 @@
/*****************************************************************************
* General Setup
****************************************************************************/
-static struct orion5x_mpp_mode tsp2_mpp_modes[] __initdata = {
- { 0, MPP_PCIE_RST_OUTn },
- { 1, MPP_UNUSED },
- { 2, MPP_UNUSED },
- { 3, MPP_UNUSED },
- { 4, MPP_NAND }, /* BOOT NAND Flash REn */
- { 5, MPP_NAND }, /* BOOT NAND Flash WEn */
- { 6, MPP_NAND }, /* BOOT NAND Flash HREn[0] */
- { 7, MPP_NAND }, /* BOOT NAND Flash WEn[0] */
- { 8, MPP_GPIO }, /* MICON int */
- { 9, MPP_GPIO }, /* RTC int */
- { 10, MPP_UNUSED },
- { 11, MPP_GPIO }, /* PCI Int A */
- { 12, MPP_UNUSED },
- { 13, MPP_GPIO }, /* UPS on UART0 enable */
- { 14, MPP_GPIO }, /* UPS low battery detection */
- { 15, MPP_UNUSED },
- { 16, MPP_UART }, /* UART1 RXD */
- { 17, MPP_UART }, /* UART1 TXD */
- { 18, MPP_UART }, /* UART1 CTSn */
- { 19, MPP_UART }, /* UART1 RTSn */
- { -1 },
+static unsigned int tsp2_mpp_modes[] __initdata = {
+ MPP0_PCIE_RST_OUTn,
+ MPP1_UNUSED,
+ MPP2_UNUSED,
+ MPP3_UNUSED,
+ MPP4_NAND, /* BOOT NAND Flash REn */
+ MPP5_NAND, /* BOOT NAND Flash WEn */
+ MPP6_NAND, /* BOOT NAND Flash HREn[0] */
+ MPP7_NAND, /* BOOT NAND Flash WEn[0] */
+ MPP8_GPIO, /* MICON int */
+ MPP9_GPIO, /* RTC int */
+ MPP10_UNUSED,
+ MPP11_GPIO, /* PCI Int A */
+ MPP12_UNUSED,
+ MPP13_GPIO, /* UPS on UART0 enable */
+ MPP14_GPIO, /* UPS low battery detection */
+ MPP15_UNUSED,
+ MPP16_UART, /* UART1 RXD */
+ MPP17_UART, /* UART1 TXD */
+ MPP18_UART, /* UART1 CTSn */
+ MPP19_UART, /* UART1 RTSn */
+ 0,
};
static void __init tsp2_init(void)
diff --git a/arch/arm/mach-orion5x/ts209-setup.c b/arch/arm/mach-orion5x/ts209-setup.c
index e6d6449..47162fd 100644
--- a/arch/arm/mach-orion5x/ts209-setup.c
+++ b/arch/arm/mach-orion5x/ts209-setup.c
@@ -244,28 +244,28 @@
* General Setup
****************************************************************************/
-static struct orion5x_mpp_mode ts209_mpp_modes[] __initdata = {
- { 0, MPP_UNUSED },
- { 1, MPP_GPIO }, /* USB copy button */
- { 2, MPP_GPIO }, /* Load defaults button */
- { 3, MPP_GPIO }, /* GPIO RTC */
- { 4, MPP_UNUSED },
- { 5, MPP_UNUSED },
- { 6, MPP_GPIO }, /* PCI Int A */
- { 7, MPP_GPIO }, /* PCI Int B */
- { 8, MPP_UNUSED },
- { 9, MPP_UNUSED },
- { 10, MPP_UNUSED },
- { 11, MPP_UNUSED },
- { 12, MPP_SATA_LED }, /* SATA 0 presence */
- { 13, MPP_SATA_LED }, /* SATA 1 presence */
- { 14, MPP_SATA_LED }, /* SATA 0 active */
- { 15, MPP_SATA_LED }, /* SATA 1 active */
- { 16, MPP_UART }, /* UART1 RXD */
- { 17, MPP_UART }, /* UART1 TXD */
- { 18, MPP_GPIO }, /* SW_RST */
- { 19, MPP_UNUSED },
- { -1 },
+static unsigned int ts209_mpp_modes[] __initdata = {
+ MPP0_UNUSED,
+ MPP1_GPIO, /* USB copy button */
+ MPP2_GPIO, /* Load defaults button */
+ MPP3_GPIO, /* GPIO RTC */
+ MPP4_UNUSED,
+ MPP5_UNUSED,
+ MPP6_GPIO, /* PCI Int A */
+ MPP7_GPIO, /* PCI Int B */
+ MPP8_UNUSED,
+ MPP9_UNUSED,
+ MPP10_UNUSED,
+ MPP11_UNUSED,
+ MPP12_SATA_LED, /* SATA 0 presence */
+ MPP13_SATA_LED, /* SATA 1 presence */
+ MPP14_SATA_LED, /* SATA 0 active */
+ MPP15_SATA_LED, /* SATA 1 active */
+ MPP16_UART, /* UART1 RXD */
+ MPP17_UART, /* UART1 TXD */
+ MPP18_GPIO, /* SW_RST */
+ MPP19_UNUSED,
+ 0,
};
static void __init qnap_ts209_init(void)
diff --git a/arch/arm/mach-orion5x/ts409-setup.c b/arch/arm/mach-orion5x/ts409-setup.c
index 9eac819..5aacc7a 100644
--- a/arch/arm/mach-orion5x/ts409-setup.c
+++ b/arch/arm/mach-orion5x/ts409-setup.c
@@ -242,28 +242,28 @@
/*****************************************************************************
* General Setup
****************************************************************************/
-static struct orion5x_mpp_mode ts409_mpp_modes[] __initdata = {
- { 0, MPP_UNUSED },
- { 1, MPP_UNUSED },
- { 2, MPP_UNUSED },
- { 3, MPP_UNUSED },
- { 4, MPP_GPIO }, /* HDD 1 status */
- { 5, MPP_GPIO }, /* HDD 2 status */
- { 6, MPP_GPIO }, /* HDD 3 status */
- { 7, MPP_GPIO }, /* HDD 4 status */
- { 8, MPP_UNUSED },
- { 9, MPP_UNUSED },
- { 10, MPP_GPIO }, /* RTC int */
- { 11, MPP_UNUSED },
- { 12, MPP_UNUSED },
- { 13, MPP_UNUSED },
- { 14, MPP_GPIO }, /* SW_RST */
- { 15, MPP_GPIO }, /* USB copy button */
- { 16, MPP_UART }, /* UART1 RXD */
- { 17, MPP_UART }, /* UART1 TXD */
- { 18, MPP_UNUSED },
- { 19, MPP_UNUSED },
- { -1 },
+static unsigned int ts409_mpp_modes[] __initdata = {
+ MPP0_UNUSED,
+ MPP1_UNUSED,
+ MPP2_UNUSED,
+ MPP3_UNUSED,
+ MPP4_GPIO, /* HDD 1 status */
+ MPP5_GPIO, /* HDD 2 status */
+ MPP6_GPIO, /* HDD 3 status */
+ MPP7_GPIO, /* HDD 4 status */
+ MPP8_UNUSED,
+ MPP9_UNUSED,
+ MPP10_GPIO, /* RTC int */
+ MPP11_UNUSED,
+ MPP12_UNUSED,
+ MPP13_UNUSED,
+ MPP14_GPIO, /* SW_RST */
+ MPP15_GPIO, /* USB copy button */
+ MPP16_UART, /* UART1 RXD */
+ MPP17_UART, /* UART1 TXD */
+ MPP18_UNUSED,
+ MPP19_UNUSED,
+ 0,
};
static void __init qnap_ts409_init(void)
diff --git a/arch/arm/mach-orion5x/ts78xx-setup.c b/arch/arm/mach-orion5x/ts78xx-setup.c
index edb1dd2..6b7b541 100644
--- a/arch/arm/mach-orion5x/ts78xx-setup.c
+++ b/arch/arm/mach-orion5x/ts78xx-setup.c
@@ -557,27 +557,27 @@
/*****************************************************************************
* General Setup
****************************************************************************/
-static struct orion5x_mpp_mode ts78xx_mpp_modes[] __initdata = {
- { 0, MPP_UNUSED },
- { 1, MPP_GPIO }, /* JTAG Clock */
- { 2, MPP_GPIO }, /* JTAG Data In */
- { 3, MPP_GPIO }, /* Lat ECP2 256 FPGA - PB2B */
- { 4, MPP_GPIO }, /* JTAG Data Out */
- { 5, MPP_GPIO }, /* JTAG TMS */
- { 6, MPP_GPIO }, /* Lat ECP2 256 FPGA - PB31A_CLK4+ */
- { 7, MPP_GPIO }, /* Lat ECP2 256 FPGA - PB22B */
- { 8, MPP_UNUSED },
- { 9, MPP_UNUSED },
- { 10, MPP_UNUSED },
- { 11, MPP_UNUSED },
- { 12, MPP_UNUSED },
- { 13, MPP_UNUSED },
- { 14, MPP_UNUSED },
- { 15, MPP_UNUSED },
- { 16, MPP_UART },
- { 17, MPP_UART },
- { 18, MPP_UART },
- { 19, MPP_UART },
+static unsigned int ts78xx_mpp_modes[] __initdata = {
+ MPP0_UNUSED,
+ MPP1_GPIO, /* JTAG Clock */
+ MPP2_GPIO, /* JTAG Data In */
+ MPP3_GPIO, /* Lat ECP2 256 FPGA - PB2B */
+ MPP4_GPIO, /* JTAG Data Out */
+ MPP5_GPIO, /* JTAG TMS */
+ MPP6_GPIO, /* Lat ECP2 256 FPGA - PB31A_CLK4+ */
+ MPP7_GPIO, /* Lat ECP2 256 FPGA - PB22B */
+ MPP8_UNUSED,
+ MPP9_UNUSED,
+ MPP10_UNUSED,
+ MPP11_UNUSED,
+ MPP12_UNUSED,
+ MPP13_UNUSED,
+ MPP14_UNUSED,
+ MPP15_UNUSED,
+ MPP16_UART,
+ MPP17_UART,
+ MPP18_UART,
+ MPP19_UART,
/*
* MPP[20] PCI Clock Out 1
* MPP[21] PCI Clock Out 0
@@ -586,7 +586,7 @@
* MPP[24] Unused
* MPP[25] Unused
*/
- { -1 },
+ 0,
};
static void __init ts78xx_init(void)
diff --git a/arch/arm/mach-orion5x/wnr854t-setup.c b/arch/arm/mach-orion5x/wnr854t-setup.c
index 4e5216b..444a1c7 100644
--- a/arch/arm/mach-orion5x/wnr854t-setup.c
+++ b/arch/arm/mach-orion5x/wnr854t-setup.c
@@ -24,28 +24,28 @@
#include "common.h"
#include "mpp.h"
-static struct orion5x_mpp_mode wnr854t_mpp_modes[] __initdata = {
- { 0, MPP_GPIO }, /* Power LED green (0=on) */
- { 1, MPP_GPIO }, /* Reset Button (0=off) */
- { 2, MPP_GPIO }, /* Power LED blink (0=off) */
- { 3, MPP_GPIO }, /* WAN Status LED amber (0=off) */
- { 4, MPP_GPIO }, /* PCI int */
- { 5, MPP_GPIO }, /* ??? */
- { 6, MPP_GPIO }, /* ??? */
- { 7, MPP_GPIO }, /* ??? */
- { 8, MPP_UNUSED }, /* ??? */
- { 9, MPP_GIGE }, /* GE_RXERR */
- { 10, MPP_UNUSED }, /* ??? */
- { 11, MPP_UNUSED }, /* ??? */
- { 12, MPP_GIGE }, /* GE_TXD[4] */
- { 13, MPP_GIGE }, /* GE_TXD[5] */
- { 14, MPP_GIGE }, /* GE_TXD[6] */
- { 15, MPP_GIGE }, /* GE_TXD[7] */
- { 16, MPP_GIGE }, /* GE_RXD[4] */
- { 17, MPP_GIGE }, /* GE_RXD[5] */
- { 18, MPP_GIGE }, /* GE_RXD[6] */
- { 19, MPP_GIGE }, /* GE_RXD[7] */
- { -1 },
+static unsigned int wnr854t_mpp_modes[] __initdata = {
+ MPP0_GPIO, /* Power LED green (0=on) */
+ MPP1_GPIO, /* Reset Button (0=off) */
+ MPP2_GPIO, /* Power LED blink (0=off) */
+ MPP3_GPIO, /* WAN Status LED amber (0=off) */
+ MPP4_GPIO, /* PCI int */
+ MPP5_GPIO, /* ??? */
+ MPP6_GPIO, /* ??? */
+ MPP7_GPIO, /* ??? */
+ MPP8_UNUSED, /* ??? */
+ MPP9_GIGE, /* GE_RXERR */
+ MPP10_UNUSED, /* ??? */
+ MPP11_UNUSED, /* ??? */
+ MPP12_GIGE, /* GE_TXD[4] */
+ MPP13_GIGE, /* GE_TXD[5] */
+ MPP14_GIGE, /* GE_TXD[6] */
+ MPP15_GIGE, /* GE_TXD[7] */
+ MPP16_GIGE, /* GE_RXD[4] */
+ MPP17_GIGE, /* GE_RXD[5] */
+ MPP18_GIGE, /* GE_RXD[6] */
+ MPP19_GIGE, /* GE_RXD[7] */
+ 0,
};
/*
diff --git a/arch/arm/mach-orion5x/wrt350n-v2-setup.c b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
index fab79d0..d1952be 100644
--- a/arch/arm/mach-orion5x/wrt350n-v2-setup.c
+++ b/arch/arm/mach-orion5x/wrt350n-v2-setup.c
@@ -101,28 +101,28 @@
/*
* General setup
*/
-static struct orion5x_mpp_mode wrt350n_v2_mpp_modes[] __initdata = {
- { 0, MPP_GPIO }, /* Power LED green (0=on) */
- { 1, MPP_GPIO }, /* Security LED (0=on) */
- { 2, MPP_GPIO }, /* Internal Button (0=on) */
- { 3, MPP_GPIO }, /* Reset Button (0=on) */
- { 4, MPP_GPIO }, /* PCI int */
- { 5, MPP_GPIO }, /* Power LED orange (0=on) */
- { 6, MPP_GPIO }, /* USB LED (0=on) */
- { 7, MPP_GPIO }, /* Wireless LED (0=on) */
- { 8, MPP_UNUSED }, /* ??? */
- { 9, MPP_GIGE }, /* GE_RXERR */
- { 10, MPP_UNUSED }, /* ??? */
- { 11, MPP_UNUSED }, /* ??? */
- { 12, MPP_GIGE }, /* GE_TXD[4] */
- { 13, MPP_GIGE }, /* GE_TXD[5] */
- { 14, MPP_GIGE }, /* GE_TXD[6] */
- { 15, MPP_GIGE }, /* GE_TXD[7] */
- { 16, MPP_GIGE }, /* GE_RXD[4] */
- { 17, MPP_GIGE }, /* GE_RXD[5] */
- { 18, MPP_GIGE }, /* GE_RXD[6] */
- { 19, MPP_GIGE }, /* GE_RXD[7] */
- { -1 },
+static unsigned int wrt350n_v2_mpp_modes[] __initdata = {
+ MPP0_GPIO, /* Power LED green (0=on) */
+ MPP1_GPIO, /* Security LED (0=on) */
+ MPP2_GPIO, /* Internal Button (0=on) */
+ MPP3_GPIO, /* Reset Button (0=on) */
+ MPP4_GPIO, /* PCI int */
+ MPP5_GPIO, /* Power LED orange (0=on) */
+ MPP6_GPIO, /* USB LED (0=on) */
+ MPP7_GPIO, /* Wireless LED (0=on) */
+ MPP8_UNUSED, /* ??? */
+ MPP9_GIGE, /* GE_RXERR */
+ MPP10_UNUSED, /* ??? */
+ MPP11_UNUSED, /* ??? */
+ MPP12_GIGE, /* GE_TXD[4] */
+ MPP13_GIGE, /* GE_TXD[5] */
+ MPP14_GIGE, /* GE_TXD[6] */
+ MPP15_GIGE, /* GE_TXD[7] */
+ MPP16_GIGE, /* GE_RXD[4] */
+ MPP17_GIGE, /* GE_RXD[5] */
+ MPP18_GIGE, /* GE_RXD[6] */
+ MPP19_GIGE, /* GE_RXD[7] */
+ 0,
};
/*
diff --git a/arch/arm/mach-pxa/cm-x2xx-pci.c b/arch/arm/mach-pxa/cm-x2xx-pci.c
index 8b1a309..1afc0fb 100644
--- a/arch/arm/mach-pxa/cm-x2xx-pci.c
+++ b/arch/arm/mach-pxa/cm-x2xx-pci.c
@@ -29,33 +29,6 @@
unsigned long it8152_base_address;
static int cmx2xx_it8152_irq_gpio;
-/*
- * Only first 64MB of memory can be accessed via PCI.
- * We use GFP_DMA to allocate safe buffers to do map/unmap.
- * This is really ugly and we need a better way of specifying
- * DMA-capable regions of memory.
- */
-void __init cmx2xx_pci_adjust_zones(unsigned long *zone_size,
- unsigned long *zhole_size)
-{
- unsigned int sz = SZ_64M >> PAGE_SHIFT;
-
- if (machine_is_armcore()) {
- pr_info("Adjusting zones for CM-X2XX\n");
-
- /*
- * Only adjust if > 64M on current system
- */
- if (zone_size[0] <= sz)
- return;
-
- zone_size[1] = zone_size[0] - sz;
- zone_size[0] = sz;
- zhole_size[1] = zhole_size[0];
- zhole_size[0] = 0;
- }
-}
-
static void cmx2xx_it8152_irq_demux(unsigned int irq, struct irq_desc *desc)
{
/* clear our parent irq */
diff --git a/arch/arm/mach-pxa/hx4700.c b/arch/arm/mach-pxa/hx4700.c
index 9cdcca5..f941a49 100644
--- a/arch/arm/mach-pxa/hx4700.c
+++ b/arch/arm/mach-pxa/hx4700.c
@@ -735,7 +735,7 @@
* StrataFlash
*/
-static void hx4700_set_vpp(struct map_info *map, int vpp)
+static void hx4700_set_vpp(struct platform_device *pdev, int vpp)
{
gpio_set_value(GPIO91_HX4700_FLASH_VPEN, vpp);
}
diff --git a/arch/arm/mach-pxa/include/mach/memory.h b/arch/arm/mach-pxa/include/mach/memory.h
index 7f68724..07734f3 100644
--- a/arch/arm/mach-pxa/include/mach/memory.h
+++ b/arch/arm/mach-pxa/include/mach/memory.h
@@ -17,14 +17,8 @@
*/
#define PLAT_PHYS_OFFSET UL(0xa0000000)
-#if !defined(__ASSEMBLY__) && defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI)
-void cmx2xx_pci_adjust_zones(unsigned long *size, unsigned long *holes);
-
-#define arch_adjust_zones(size, holes) \
- cmx2xx_pci_adjust_zones(size, holes)
-
-#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_64M - 1)
-#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_64M)
+#if defined(CONFIG_MACH_ARMCORE) && defined(CONFIG_PCI)
+#define ARM_DMA_ZONE_SIZE SZ_64M
#endif
#endif
diff --git a/arch/arm/mach-pxa/include/mach/uncompress.h b/arch/arm/mach-pxa/include/mach/uncompress.h
index 759b851..5519a34 100644
--- a/arch/arm/mach-pxa/include/mach/uncompress.h
+++ b/arch/arm/mach-pxa/include/mach/uncompress.h
@@ -16,9 +16,9 @@
#define BTUART_BASE (0x40200000)
#define STUART_BASE (0x40700000)
-static unsigned long uart_base;
-static unsigned int uart_shift;
-static unsigned int uart_is_pxa;
+unsigned long uart_base;
+unsigned int uart_shift;
+unsigned int uart_is_pxa;
static inline unsigned char uart_read(int offset)
{
diff --git a/arch/arm/mach-pxa/magician.c b/arch/arm/mach-pxa/magician.c
index 9984ef7..e192057 100644
--- a/arch/arm/mach-pxa/magician.c
+++ b/arch/arm/mach-pxa/magician.c
@@ -662,7 +662,7 @@
* StrataFlash
*/
-static void magician_set_vpp(struct map_info *map, int vpp)
+static void magician_set_vpp(struct platform_device *pdev, int vpp)
{
gpio_set_value(EGPIO_MAGICIAN_FLASH_VPP, vpp);
}
diff --git a/arch/arm/mach-pxa/time.c b/arch/arm/mach-pxa/time.c
index 428da3f..de68470 100644
--- a/arch/arm/mach-pxa/time.c
+++ b/arch/arm/mach-pxa/time.c
@@ -105,19 +105,6 @@
.set_mode = pxa_osmr0_set_mode,
};
-static cycle_t pxa_read_oscr(struct clocksource *cs)
-{
- return OSCR;
-}
-
-static struct clocksource cksrc_pxa_oscr0 = {
- .name = "oscr0",
- .rating = 200,
- .read = pxa_read_oscr,
- .mask = CLOCKSOURCE_MASK(32),
- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
static struct irqaction pxa_ost0_irq = {
.name = "ost0",
.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
@@ -134,7 +121,6 @@
init_sched_clock(&cd, pxa_update_sched_clock, 32, clock_tick_rate);
- clocksource_calc_mult_shift(&cksrc_pxa_oscr0, clock_tick_rate, 4);
clockevents_calc_mult_shift(&ckevt_pxa_osmr0, clock_tick_rate, 4);
ckevt_pxa_osmr0.max_delta_ns =
clockevent_delta2ns(0x7fffffff, &ckevt_pxa_osmr0);
@@ -144,7 +130,8 @@
setup_irq(IRQ_OST0, &pxa_ost0_irq);
- clocksource_register_hz(&cksrc_pxa_oscr0, clock_tick_rate);
+ clocksource_mmio_init(&OSCR, "oscr0", clock_tick_rate, 200, 32,
+ clocksource_mmio_readl_up);
clockevents_register_device(&ckevt_pxa_osmr0);
}
diff --git a/arch/arm/mach-realview/core.c b/arch/arm/mach-realview/core.c
index 75dbc87..5c23450 100644
--- a/arch/arm/mach-realview/core.c
+++ b/arch/arm/mach-realview/core.c
@@ -31,6 +31,7 @@
#include <linux/amba/mmci.h>
#include <linux/gfp.h>
#include <linux/clkdev.h>
+#include <linux/mtd/physmap.h>
#include <asm/system.h>
#include <mach/hardware.h>
@@ -41,7 +42,6 @@
#include <asm/hardware/icst.h>
#include <asm/mach/arch.h>
-#include <asm/mach/flash.h>
#include <asm/mach/irq.h>
#include <asm/mach/map.h>
@@ -56,48 +56,9 @@
#include "core.h"
-#ifdef CONFIG_ZONE_DMA
-/*
- * Adjust the zones if there are restrictions for DMA access.
- */
-void __init realview_adjust_zones(unsigned long *size, unsigned long *hole)
-{
- unsigned long dma_size = SZ_256M >> PAGE_SHIFT;
-
- if (!machine_is_realview_pbx() || size[0] <= dma_size)
- return;
-
- size[ZONE_NORMAL] = size[0] - dma_size;
- size[ZONE_DMA] = dma_size;
- hole[ZONE_NORMAL] = hole[0];
- hole[ZONE_DMA] = 0;
-}
-#endif
-
-
#define REALVIEW_FLASHCTRL (__io_address(REALVIEW_SYS_BASE) + REALVIEW_SYS_FLASH_OFFSET)
-static int realview_flash_init(void)
-{
- u32 val;
-
- val = __raw_readl(REALVIEW_FLASHCTRL);
- val &= ~REALVIEW_FLASHPROG_FLVPPEN;
- __raw_writel(val, REALVIEW_FLASHCTRL);
-
- return 0;
-}
-
-static void realview_flash_exit(void)
-{
- u32 val;
-
- val = __raw_readl(REALVIEW_FLASHCTRL);
- val &= ~REALVIEW_FLASHPROG_FLVPPEN;
- __raw_writel(val, REALVIEW_FLASHCTRL);
-}
-
-static void realview_flash_set_vpp(int on)
+static void realview_flash_set_vpp(struct platform_device *pdev, int on)
{
u32 val;
@@ -109,16 +70,13 @@
__raw_writel(val, REALVIEW_FLASHCTRL);
}
-static struct flash_platform_data realview_flash_data = {
- .map_name = "cfi_probe",
+static struct physmap_flash_data realview_flash_data = {
.width = 4,
- .init = realview_flash_init,
- .exit = realview_flash_exit,
.set_vpp = realview_flash_set_vpp,
};
struct platform_device realview_flash_device = {
- .name = "armflash",
+ .name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &realview_flash_data,
@@ -315,6 +273,10 @@
.rate = 24000000,
};
+static struct clk sp804_clk = {
+ .rate = 1000000,
+};
+
static struct clk dummy_apb_pclk;
static struct clk_lookup lookups[] = {
@@ -357,7 +319,10 @@
}, { /* SSP */
.dev_id = "dev:ssp0",
.clk = &ref24_clk,
- }
+ }, { /* SP804 timers */
+ .dev_id = "sp804",
+ .clk = &sp804_clk,
+ },
};
void __init realview_init_early(void)
@@ -545,8 +510,8 @@
writel(0, timer2_va_base + TIMER_CTRL);
writel(0, timer3_va_base + TIMER_CTRL);
- sp804_clocksource_init(timer3_va_base);
- sp804_clockevents_init(timer0_va_base, timer_irq);
+ sp804_clocksource_init(timer3_va_base, "timer3");
+ sp804_clockevents_init(timer0_va_base, timer_irq, "timer0");
}
/*
diff --git a/arch/arm/mach-realview/include/mach/memory.h b/arch/arm/mach-realview/include/mach/memory.h
index e05fc2c..1759fa6 100644
--- a/arch/arm/mach-realview/include/mach/memory.h
+++ b/arch/arm/mach-realview/include/mach/memory.h
@@ -29,13 +29,8 @@
#define PLAT_PHYS_OFFSET UL(0x00000000)
#endif
-#if !defined(__ASSEMBLY__) && defined(CONFIG_ZONE_DMA)
-extern void realview_adjust_zones(unsigned long *size, unsigned long *hole);
-#define arch_adjust_zones(size, hole) \
- realview_adjust_zones(size, hole)
-
-#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_256M - 1)
-#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_256M)
+#ifdef CONFIG_ZONE_DMA
+#define ARM_DMA_ZONE_SIZE SZ_256M
#endif
#ifdef CONFIG_SPARSEMEM
diff --git a/arch/arm/mach-realview/include/mach/smp.h b/arch/arm/mach-realview/include/mach/smp.h
deleted file mode 100644
index c8221b3..0000000
--- a/arch/arm/mach-realview/include/mach/smp.h
+++ /dev/null
@@ -1,14 +0,0 @@
-#ifndef ASMARM_ARCH_SMP_H
-#define ASMARM_ARCH_SMP_H
-
-#include <asm/hardware/gic.h>
-
-/*
- * We use IRQ1 as the IPI
- */
-static inline void smp_cross_call(const struct cpumask *mask, int ipi)
-{
- gic_raise_softirq(mask, ipi);
-}
-
-#endif
diff --git a/arch/arm/mach-realview/platsmp.c b/arch/arm/mach-realview/platsmp.c
index 2391922..963bf0d 100644
--- a/arch/arm/mach-realview/platsmp.c
+++ b/arch/arm/mach-realview/platsmp.c
@@ -14,6 +14,7 @@
#include <linux/io.h>
#include <mach/hardware.h>
+#include <asm/hardware/gic.h>
#include <asm/mach-types.h>
#include <asm/smp_scu.h>
#include <asm/unified.h>
@@ -61,6 +62,8 @@
for (i = 0; i < ncores; i++)
set_cpu_possible(i, true);
+
+ set_smp_cross_call(gic_raise_softirq);
}
void __init platform_smp_prepare_cpus(unsigned int max_cpus)
diff --git a/arch/arm/mach-rpc/include/mach/uncompress.h b/arch/arm/mach-rpc/include/mach/uncompress.h
index 8c9e2c7..9cd9bcd 100644
--- a/arch/arm/mach-rpc/include/mach/uncompress.h
+++ b/arch/arm/mach-rpc/include/mach/uncompress.h
@@ -66,12 +66,12 @@
#define params (params())
#ifndef STANDALONE_DEBUG
-static unsigned long video_num_cols;
-static unsigned long video_num_rows;
-static unsigned long video_x;
-static unsigned long video_y;
-static unsigned char bytes_per_char_v;
-static int white;
+unsigned long video_num_cols;
+unsigned long video_num_rows;
+unsigned long video_x;
+unsigned long video_y;
+unsigned char bytes_per_char_v;
+int white;
/*
* This does not append a newline
diff --git a/arch/arm/mach-s3c2410/include/mach/map.h b/arch/arm/mach-s3c2410/include/mach/map.h
index 25bbf5a..425552d 100644
--- a/arch/arm/mach-s3c2410/include/mach/map.h
+++ b/arch/arm/mach-s3c2410/include/mach/map.h
@@ -21,6 +21,10 @@
/* USB host controller */
#define S3C2410_PA_USBHOST (0x49000000)
+/* S3C2416/S3C2443/S3C2450 High-Speed USB Gadget */
+#define S3C2416_PA_HSUDC (0x49800000)
+#define S3C2416_SZ_HSUDC (SZ_4K)
+
/* DMA controller */
#define S3C2410_PA_DMA (0x4B000000)
#define S3C24XX_SZ_DMA SZ_1M
diff --git a/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h b/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h
index 44494a5..5e06c72 100644
--- a/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h
+++ b/arch/arm/mach-s3c2410/include/mach/regs-s3c2443-clock.h
@@ -37,6 +37,10 @@
#define S3C2443_SYSID S3C2443_CLKREG(0x5C)
#define S3C2443_PWRCFG S3C2443_CLKREG(0x60)
#define S3C2443_RSTCON S3C2443_CLKREG(0x64)
+#define S3C2443_PHYCTRL S3C2443_CLKREG(0x80)
+#define S3C2443_PHYPWR S3C2443_CLKREG(0x84)
+#define S3C2443_URSTCON S3C2443_CLKREG(0x88)
+#define S3C2443_UCLKCON S3C2443_CLKREG(0x8C)
#define S3C2443_SWRST_RESET (0x533c2443)
@@ -121,6 +125,27 @@
#define S3C2443_PWRCFG_SLEEP (1<<15)
+#define S3C2443_PWRCFG_USBPHY (1 << 4)
+
+#define S3C2443_URSTCON_FUNCRST (1 << 2)
+#define S3C2443_URSTCON_PHYRST (1 << 0)
+
+#define S3C2443_PHYCTRL_CLKSEL (1 << 3)
+#define S3C2443_PHYCTRL_EXTCLK (1 << 2)
+#define S3C2443_PHYCTRL_PLLSEL (1 << 1)
+#define S3C2443_PHYCTRL_DSPORT (1 << 0)
+
+#define S3C2443_PHYPWR_COMMON_ON (1 << 31)
+#define S3C2443_PHYPWR_ANALOG_PD (1 << 4)
+#define S3C2443_PHYPWR_PLL_REFCLK (1 << 3)
+#define S3C2443_PHYPWR_XO_ON (1 << 2)
+#define S3C2443_PHYPWR_PLL_PWRDN (1 << 1)
+#define S3C2443_PHYPWR_FSUSPEND (1 << 0)
+
+#define S3C2443_UCLKCON_DETECT_VBUS (1 << 31)
+#define S3C2443_UCLKCON_FUNC_CLKEN (1 << 2)
+#define S3C2443_UCLKCON_TCLKEN (1 << 0)
+
#include <asm/div64.h>
static inline unsigned int
diff --git a/arch/arm/mach-s3c2410/nor-simtec.c b/arch/arm/mach-s3c2410/nor-simtec.c
index 598d130..ad9f750 100644
--- a/arch/arm/mach-s3c2410/nor-simtec.c
+++ b/arch/arm/mach-s3c2410/nor-simtec.c
@@ -32,7 +32,7 @@
#include "nor-simtec.h"
-static void simtec_nor_vpp(struct map_info *map, int vpp)
+static void simtec_nor_vpp(struct platform_device *pdev, int vpp)
{
unsigned int val;
unsigned long flags;
diff --git a/arch/arm/mach-s3c2416/mach-smdk2416.c b/arch/arm/mach-s3c2416/mach-smdk2416.c
index 3f83177..ac27ebb 100644
--- a/arch/arm/mach-s3c2416/mach-smdk2416.c
+++ b/arch/arm/mach-s3c2416/mach-smdk2416.c
@@ -23,6 +23,7 @@
#include <linux/mtd/partitions.h>
#include <linux/gpio.h>
#include <linux/fb.h>
+#include <linux/delay.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
@@ -35,6 +36,7 @@
#include <plat/regs-serial.h>
#include <mach/regs-gpio.h>
#include <mach/regs-lcd.h>
+#include <mach/regs-s3c2443-clock.h>
#include <mach/idle.h>
#include <mach/leds-gpio.h>
@@ -47,6 +49,7 @@
#include <plat/cpu.h>
#include <plat/nand.h>
#include <plat/sdhci.h>
+#include <plat/udc.h>
#include <plat/regs-fb-v4.h>
#include <plat/fb.h>
@@ -121,6 +124,27 @@
}
};
+void smdk2416_hsudc_gpio_init(void)
+{
+ s3c_gpio_setpull(S3C2410_GPH(14), S3C_GPIO_PULL_UP);
+ s3c_gpio_setpull(S3C2410_GPF(2), S3C_GPIO_PULL_NONE);
+ s3c_gpio_cfgpin(S3C2410_GPH(14), S3C_GPIO_SFN(1));
+ s3c2410_modify_misccr(S3C2416_MISCCR_SEL_SUSPND, 0);
+}
+
+void smdk2416_hsudc_gpio_uninit(void)
+{
+ s3c2410_modify_misccr(S3C2416_MISCCR_SEL_SUSPND, 1);
+ s3c_gpio_setpull(S3C2410_GPH(14), S3C_GPIO_PULL_NONE);
+ s3c_gpio_cfgpin(S3C2410_GPH(14), S3C_GPIO_SFN(0));
+}
+
+struct s3c24xx_hsudc_platdata smdk2416_hsudc_platdata = {
+ .epnum = 9,
+ .gpio_init = smdk2416_hsudc_gpio_init,
+ .gpio_uninit = smdk2416_hsudc_gpio_uninit,
+};
+
struct s3c_fb_pd_win smdk2416_fb_win[] = {
[0] = {
/* think this is the same as the smdk6410 */
@@ -186,6 +210,7 @@
&s3c_device_i2c0,
&s3c_device_hsmmc0,
&s3c_device_hsmmc1,
+ &s3c_device_usb_hsudc,
};
static void __init smdk2416_map_io(void)
@@ -203,6 +228,8 @@
s3c_sdhci0_set_platdata(&smdk2416_hsmmc0_pdata);
s3c_sdhci1_set_platdata(&smdk2416_hsmmc1_pdata);
+ s3c24xx_hsudc_set_platdata(&smdk2416_hsudc_platdata);
+
gpio_request(S3C2410_GPB(4), "USBHost Power");
gpio_direction_output(S3C2410_GPB(4), 1);
diff --git a/arch/arm/mach-s3c64xx/irq.c b/arch/arm/mach-s3c64xx/irq.c
index 67a145d..97660c8 100644
--- a/arch/arm/mach-s3c64xx/irq.c
+++ b/arch/arm/mach-s3c64xx/irq.c
@@ -58,12 +58,7 @@
vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, 0);
/* add the timer sub-irqs */
-
- s3c_init_vic_timer_irq(IRQ_TIMER0_VIC, IRQ_TIMER0);
- s3c_init_vic_timer_irq(IRQ_TIMER1_VIC, IRQ_TIMER1);
- s3c_init_vic_timer_irq(IRQ_TIMER2_VIC, IRQ_TIMER2);
- s3c_init_vic_timer_irq(IRQ_TIMER3_VIC, IRQ_TIMER3);
- s3c_init_vic_timer_irq(IRQ_TIMER4_VIC, IRQ_TIMER4);
+ s3c_init_vic_timer_irq(5, IRQ_TIMER0);
s3c_init_uart_irqs(uart_irqs, ARRAY_SIZE(uart_irqs));
}
diff --git a/arch/arm/mach-s5p64x0/include/mach/uncompress.h b/arch/arm/mach-s5p64x0/include/mach/uncompress.h
index c65b229..1608faf 100644
--- a/arch/arm/mach-s5p64x0/include/mach/uncompress.h
+++ b/arch/arm/mach-s5p64x0/include/mach/uncompress.h
@@ -24,8 +24,8 @@
/* uart setup */
-static unsigned int fifo_mask;
-static unsigned int fifo_max;
+unsigned int fifo_mask;
+unsigned int fifo_max;
/* forward declerations */
@@ -43,7 +43,7 @@
/* how many bytes we allow into the FIFO at a time in FIFO mode */
#define FIFO_MAX (14)
-static unsigned long uart_base;
+unsigned long uart_base;
static __inline__ void get_uart_base(void)
{
diff --git a/arch/arm/mach-sa1100/include/mach/memory.h b/arch/arm/mach-sa1100/include/mach/memory.h
index a44da6a..cff31ee 100644
--- a/arch/arm/mach-sa1100/include/mach/memory.h
+++ b/arch/arm/mach-sa1100/include/mach/memory.h
@@ -14,18 +14,8 @@
*/
#define PLAT_PHYS_OFFSET UL(0xc0000000)
-#ifndef __ASSEMBLY__
-
#ifdef CONFIG_SA1111
-void sa1111_adjust_zones(unsigned long *size, unsigned long *holes);
-
-#define arch_adjust_zones(size, holes) \
- sa1111_adjust_zones(size, holes)
-
-#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_1M - 1)
-#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_1M)
-
-#endif
+#define ARM_DMA_ZONE_SIZE SZ_1M
#endif
/*
diff --git a/arch/arm/mach-sa1100/time.c b/arch/arm/mach-sa1100/time.c
index ae4f3d8..fa66024 100644
--- a/arch/arm/mach-sa1100/time.c
+++ b/arch/arm/mach-sa1100/time.c
@@ -92,25 +92,11 @@
static struct clock_event_device ckevt_sa1100_osmr0 = {
.name = "osmr0",
.features = CLOCK_EVT_FEAT_ONESHOT,
- .shift = 32,
.rating = 200,
.set_next_event = sa1100_osmr0_set_next_event,
.set_mode = sa1100_osmr0_set_mode,
};
-static cycle_t sa1100_read_oscr(struct clocksource *s)
-{
- return OSCR;
-}
-
-static struct clocksource cksrc_sa1100_oscr = {
- .name = "oscr",
- .rating = 200,
- .read = sa1100_read_oscr,
- .mask = CLOCKSOURCE_MASK(32),
- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
static struct irqaction sa1100_timer_irq = {
.name = "ost0",
.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
@@ -120,14 +106,13 @@
static void __init sa1100_timer_init(void)
{
- OIER = 0; /* disable any timer interrupts */
- OSSR = 0xf; /* clear status on all timers */
+ OIER = 0;
+ OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3;
init_fixed_sched_clock(&cd, sa1100_update_sched_clock, 32,
3686400, SC_MULT, SC_SHIFT);
- ckevt_sa1100_osmr0.mult =
- div_sc(3686400, NSEC_PER_SEC, ckevt_sa1100_osmr0.shift);
+ clockevents_calc_mult_shift(&ckevt_sa1100_osmr0, 3686400, 4);
ckevt_sa1100_osmr0.max_delta_ns =
clockevent_delta2ns(0x7fffffff, &ckevt_sa1100_osmr0);
ckevt_sa1100_osmr0.min_delta_ns =
@@ -136,7 +121,8 @@
setup_irq(IRQ_OST0, &sa1100_timer_irq);
- clocksource_register_hz(&cksrc_sa1100_oscr, CLOCK_TICK_RATE);
+ clocksource_mmio_init(&OSCR, "oscr", CLOCK_TICK_RATE, 200, 32,
+ clocksource_mmio_readl_up);
clockevents_register_device(&ckevt_sa1100_osmr0);
}
diff --git a/arch/arm/mach-shark/include/mach/memory.h b/arch/arm/mach-shark/include/mach/memory.h
index 9afb170..4c0831f8 100644
--- a/arch/arm/mach-shark/include/mach/memory.h
+++ b/arch/arm/mach-shark/include/mach/memory.h
@@ -17,25 +17,7 @@
*/
#define PLAT_PHYS_OFFSET UL(0x08000000)
-#ifndef __ASSEMBLY__
-
-static inline void __arch_adjust_zones(unsigned long *zone_size, unsigned long *zhole_size)
-{
- /* Only the first 4 MB (=1024 Pages) are usable for DMA */
- /* See dev / -> .properties in OpenFirmware. */
- zone_size[1] = zone_size[0] - 1024;
- zone_size[0] = 1024;
- zhole_size[1] = zhole_size[0];
- zhole_size[0] = 0;
-}
-
-#define arch_adjust_zones(size, holes) \
- __arch_adjust_zones(size, holes)
-
-#define ISA_DMA_THRESHOLD (PHYS_OFFSET + SZ_4M - 1)
-#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_4M)
-
-#endif
+#define ARM_DMA_ZONE_SIZE SZ_4M
/*
* Cache flushing area
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index e2507f6..612b270 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -30,6 +30,11 @@
obj-$(CONFIG_ARCH_SH7372) += entry-intc.o
obj-$(CONFIG_ARCH_SH73A0) += entry-gic.o
+# PM objects
+obj-$(CONFIG_SUSPEND) += suspend.o
+obj-$(CONFIG_CPU_IDLE) += cpuidle.o
+obj-$(CONFIG_ARCH_SH7372) += pm-sh7372.o sleep-sh7372.o
+
# Board objects
obj-$(CONFIG_MACH_G3EVM) += board-g3evm.o
obj-$(CONFIG_MACH_G4EVM) += board-g4evm.o
diff --git a/arch/arm/mach-shmobile/board-ag5evm.c b/arch/arm/mach-shmobile/board-ag5evm.c
index 3e6f0aa..c95258c 100644
--- a/arch/arm/mach-shmobile/board-ag5evm.c
+++ b/arch/arm/mach-shmobile/board-ag5evm.c
@@ -34,6 +34,8 @@
#include <linux/input/sh_keysc.h>
#include <linux/mmc/host.h>
#include <linux/mmc/sh_mmcif.h>
+#include <linux/mmc/sh_mobile_sdhi.h>
+#include <linux/mfd/tmio.h>
#include <linux/sh_clk.h>
#include <video/sh_mobile_lcdc.h>
#include <video/sh_mipi_dsi.h>
@@ -156,10 +158,19 @@
},
};
+static struct sh_mmcif_dma sh_mmcif_dma = {
+ .chan_priv_rx = {
+ .slave_id = SHDMA_SLAVE_MMCIF_RX,
+ },
+ .chan_priv_tx = {
+ .slave_id = SHDMA_SLAVE_MMCIF_TX,
+ },
+};
static struct sh_mmcif_plat_data sh_mmcif_platdata = {
.sup_pclk = 0,
.ocr = MMC_VDD_165_195,
.caps = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE,
+ .dma = &sh_mmcif_dma,
};
static struct platform_device mmc_device = {
@@ -296,11 +307,13 @@
/* MIPI-DSI */
static struct resource mipidsi0_resources[] = {
[0] = {
+ .name = "DSI0",
.start = 0xfeab0000,
.end = 0xfeab3fff,
.flags = IORESOURCE_MEM,
},
[1] = {
+ .name = "DSI0",
.start = 0xfeab4000,
.end = 0xfeab7fff,
.flags = IORESOURCE_MEM,
@@ -325,6 +338,89 @@
},
};
+static struct sh_mobile_sdhi_info sdhi0_info = {
+ .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
+ .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
+ .tmio_caps = MMC_CAP_SD_HIGHSPEED,
+ .tmio_ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
+};
+
+static struct resource sdhi0_resources[] = {
+ [0] = {
+ .name = "SDHI0",
+ .start = 0xee100000,
+ .end = 0xee1000ff,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = gic_spi(83),
+ .flags = IORESOURCE_IRQ,
+ },
+ [2] = {
+ .start = gic_spi(84),
+ .flags = IORESOURCE_IRQ,
+ },
+ [3] = {
+ .start = gic_spi(85),
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device sdhi0_device = {
+ .name = "sh_mobile_sdhi",
+ .id = 0,
+ .num_resources = ARRAY_SIZE(sdhi0_resources),
+ .resource = sdhi0_resources,
+ .dev = {
+ .platform_data = &sdhi0_info,
+ },
+};
+
+void ag5evm_sdhi1_set_pwr(struct platform_device *pdev, int state)
+{
+ gpio_set_value(GPIO_PORT114, state);
+}
+
+static struct sh_mobile_sdhi_info sh_sdhi1_platdata = {
+ .dma_slave_tx = SHDMA_SLAVE_SDHI1_TX,
+ .dma_slave_rx = SHDMA_SLAVE_SDHI1_RX,
+ .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE,
+ .tmio_caps = MMC_CAP_NONREMOVABLE,
+ .tmio_ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
+ .set_pwr = ag5evm_sdhi1_set_pwr,
+};
+
+static struct resource sdhi1_resources[] = {
+ [0] = {
+ .name = "SDHI1",
+ .start = 0xee120000,
+ .end = 0xee1200ff,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = gic_spi(87),
+ .flags = IORESOURCE_IRQ,
+ },
+ [2] = {
+ .start = gic_spi(88),
+ .flags = IORESOURCE_IRQ,
+ },
+ [3] = {
+ .start = gic_spi(89),
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device sdhi1_device = {
+ .name = "sh_mobile_sdhi",
+ .id = 1,
+ .dev = {
+ .platform_data = &sh_sdhi1_platdata,
+ },
+ .num_resources = ARRAY_SIZE(sdhi1_resources),
+ .resource = sdhi1_resources,
+};
+
static struct platform_device *ag5evm_devices[] __initdata = {
ð_device,
&keysc_device,
@@ -333,6 +429,8 @@
&irda_device,
&lcdc0_device,
&mipidsi0_device,
+ &sdhi0_device,
+ &sdhi1_device,
};
static struct map_desc ag5evm_io_desc[] __initdata = {
@@ -454,6 +552,26 @@
/* MIPI-DSI clock setup */
__raw_writel(0x2a809010, DSI0PHYCR);
+ /* enable SDHI0 on CN15 [SD I/F] */
+ gpio_request(GPIO_FN_SDHICD0, NULL);
+ gpio_request(GPIO_FN_SDHIWP0, NULL);
+ gpio_request(GPIO_FN_SDHICMD0, NULL);
+ gpio_request(GPIO_FN_SDHICLK0, NULL);
+ gpio_request(GPIO_FN_SDHID0_3, NULL);
+ gpio_request(GPIO_FN_SDHID0_2, NULL);
+ gpio_request(GPIO_FN_SDHID0_1, NULL);
+ gpio_request(GPIO_FN_SDHID0_0, NULL);
+
+ /* enable SDHI1 on CN4 [WLAN I/F] */
+ gpio_request(GPIO_FN_SDHICLK1, NULL);
+ gpio_request(GPIO_FN_SDHICMD1_PU, NULL);
+ gpio_request(GPIO_FN_SDHID1_3_PU, NULL);
+ gpio_request(GPIO_FN_SDHID1_2_PU, NULL);
+ gpio_request(GPIO_FN_SDHID1_1_PU, NULL);
+ gpio_request(GPIO_FN_SDHID1_0_PU, NULL);
+ gpio_request(GPIO_PORT114, "sdhi1_power");
+ gpio_direction_output(GPIO_PORT114, 0);
+
#ifdef CONFIG_CACHE_L2X0
/* Shared attribute override enable, 64K*8way */
l2x0_init(__io(0xf0100000), 0x00460000, 0xc2000fff);
diff --git a/arch/arm/mach-shmobile/board-ap4evb.c b/arch/arm/mach-shmobile/board-ap4evb.c
index 1e35fa9..08acb6e 100644
--- a/arch/arm/mach-shmobile/board-ap4evb.c
+++ b/arch/arm/mach-shmobile/board-ap4evb.c
@@ -316,8 +316,16 @@
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = evt2irq(0x0e00) /* SDHI0 */,
- .flags = IORESOURCE_IRQ,
+ .start = evt2irq(0x0e00) /* SDHI0_SDHI0I0 */,
+ .flags = IORESOURCE_IRQ,
+ },
+ [2] = {
+ .start = evt2irq(0x0e20) /* SDHI0_SDHI0I1 */,
+ .flags = IORESOURCE_IRQ,
+ },
+ [3] = {
+ .start = evt2irq(0x0e40) /* SDHI0_SDHI0I2 */,
+ .flags = IORESOURCE_IRQ,
},
};
@@ -349,8 +357,16 @@
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = evt2irq(0x0e80),
- .flags = IORESOURCE_IRQ,
+ .start = evt2irq(0x0e80), /* SDHI1_SDHI1I0 */
+ .flags = IORESOURCE_IRQ,
+ },
+ [2] = {
+ .start = evt2irq(0x0ea0), /* SDHI1_SDHI1I1 */
+ .flags = IORESOURCE_IRQ,
+ },
+ [3] = {
+ .start = evt2irq(0x0ec0), /* SDHI1_SDHI1I2 */
+ .flags = IORESOURCE_IRQ,
},
};
@@ -980,11 +996,6 @@
goto out;
}
- ret = clk_enable(&sh7372_pllc2_clk);
- if (ret < 0) {
- pr_err("Cannot enable pllc2 clock\n");
- goto out;
- }
pr_debug("PLLC2 set frequency %lu\n", rate);
ret = clk_set_parent(hdmi_ick, &sh7372_pllc2_clk);
@@ -1343,6 +1354,7 @@
hdmi_init_pm_clock();
fsi_init_pm_clock();
+ sh7372_pm_init();
}
static void __init ap4evb_timer_init(void)
diff --git a/arch/arm/mach-shmobile/board-g4evm.c b/arch/arm/mach-shmobile/board-g4evm.c
index c87a7b7..8e3c555 100644
--- a/arch/arm/mach-shmobile/board-g4evm.c
+++ b/arch/arm/mach-shmobile/board-g4evm.c
@@ -205,7 +205,7 @@
[0] = {
.name = "SDHI0",
.start = 0xe6d50000,
- .end = 0xe6d50nff,
+ .end = 0xe6d500ff,
.flags = IORESOURCE_MEM,
},
[1] = {
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
index 7da2ca2..448ddbe 100644
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ b/arch/arm/mach-shmobile/board-mackerel.c
@@ -43,6 +43,7 @@
#include <linux/sh_intc.h>
#include <linux/tca6416_keypad.h>
#include <linux/usb/r8a66597.h>
+#include <linux/usb/renesas_usbhs.h>
#include <video/sh_mobile_hdmi.h>
#include <video/sh_mobile_lcdc.h>
@@ -143,7 +144,30 @@
* open | external VBUS | Function
*
* *1
- * CN31 is used as Host in Linux.
+ * CN31 is used as
+ * CONFIG_USB_R8A66597_HCD Host
+ * CONFIG_USB_RENESAS_USBHS Function
+ *
+ * CAUTION
+ *
+ * renesas_usbhs driver can use external interrupt mode
+ * (which come from USB-PHY) or autonomy mode (it use own interrupt)
+ * for detecting connection/disconnection when Function.
+ * USB will be power OFF while it has been disconnecting
+ * if external interrupt mode, and it is always power ON if autonomy mode,
+ *
+ * mackerel can not use external interrupt (IRQ7-PORT167) mode on "USB0",
+ * because Touchscreen is using IRQ7-PORT40.
+ * It is impossible to use IRQ7 demux on this board.
+ *
+ * We can use external interrupt mode USB-Function on "USB1".
+ * USB1 can become Host by r8a66597, and become Function by renesas_usbhs.
+ * But don't select both drivers in same time.
+ * These uses same IRQ number for request_irq(), and aren't supporting
+ * IRQF_SHARD / IORESOURCE_IRQ_SHAREABLE.
+ *
+ * Actually these are old/new version of USB driver.
+ * This mean its register will be broken if it supports SHARD IRQ,
*/
/*
@@ -185,6 +209,7 @@
* FIXME !!
*
* gpio_no_direction
+ * gpio_pull_down
* are quick_hack.
*
* current gpio frame work doesn't have
@@ -196,6 +221,16 @@
__raw_writeb(0x00, addr);
}
+static void __init gpio_pull_down(u32 addr)
+{
+ u8 data = __raw_readb(addr);
+
+ data &= 0x0F;
+ data |= 0xA0;
+
+ __raw_writeb(data, addr);
+}
+
/* MTD */
static struct mtd_partition nor_flash_partitions[] = {
{
@@ -458,12 +493,6 @@
goto out;
}
- ret = clk_enable(&sh7372_pllc2_clk);
- if (ret < 0) {
- pr_err("Cannot enable pllc2 clock\n");
- goto out;
- }
-
pr_debug("PLLC2 set frequency %lu\n", rate);
ret = clk_set_parent(hdmi_ick, &sh7372_pllc2_clk);
@@ -515,6 +544,157 @@
.resource = usb1_host_resources,
};
+/* USB1 (Function) */
+#define USB_PHY_MODE (1 << 4)
+#define USB_PHY_INT_EN ((1 << 3) | (1 << 2))
+#define USB_PHY_ON (1 << 1)
+#define USB_PHY_OFF (1 << 0)
+#define USB_PHY_INT_CLR (USB_PHY_ON | USB_PHY_OFF)
+
+struct usbhs_private {
+ unsigned int irq;
+ unsigned int usbphyaddr;
+ unsigned int usbcrcaddr;
+ struct renesas_usbhs_platform_info info;
+};
+
+#define usbhs_get_priv(pdev) \
+ container_of(renesas_usbhs_get_info(pdev), \
+ struct usbhs_private, info)
+
+#define usbhs_is_connected(priv) \
+ (!((1 << 7) & __raw_readw(priv->usbcrcaddr)))
+
+static int usbhs1_get_id(struct platform_device *pdev)
+{
+ return USBHS_GADGET;
+}
+
+static int usbhs1_get_vbus(struct platform_device *pdev)
+{
+ return usbhs_is_connected(usbhs_get_priv(pdev));
+}
+
+static irqreturn_t usbhs1_interrupt(int irq, void *data)
+{
+ struct platform_device *pdev = data;
+ struct usbhs_private *priv = usbhs_get_priv(pdev);
+
+ dev_dbg(&pdev->dev, "%s\n", __func__);
+
+ renesas_usbhs_call_notify_hotplug(pdev);
+
+ /* clear status */
+ __raw_writew(__raw_readw(priv->usbphyaddr) | USB_PHY_INT_CLR,
+ priv->usbphyaddr);
+
+ return IRQ_HANDLED;
+}
+
+static int usbhs1_hardware_init(struct platform_device *pdev)
+{
+ struct usbhs_private *priv = usbhs_get_priv(pdev);
+ int ret;
+
+ irq_set_irq_type(priv->irq, IRQ_TYPE_LEVEL_HIGH);
+
+ /* clear interrupt status */
+ __raw_writew(USB_PHY_MODE | USB_PHY_INT_CLR, priv->usbphyaddr);
+
+ ret = request_irq(priv->irq, usbhs1_interrupt, 0,
+ dev_name(&pdev->dev), pdev);
+ if (ret) {
+ dev_err(&pdev->dev, "request_irq err\n");
+ return ret;
+ }
+
+ /* enable USB phy interrupt */
+ __raw_writew(USB_PHY_MODE | USB_PHY_INT_EN, priv->usbphyaddr);
+
+ return 0;
+}
+
+static void usbhs1_hardware_exit(struct platform_device *pdev)
+{
+ struct usbhs_private *priv = usbhs_get_priv(pdev);
+
+ /* clear interrupt status */
+ __raw_writew(USB_PHY_MODE | USB_PHY_INT_CLR, priv->usbphyaddr);
+
+ free_irq(priv->irq, pdev);
+}
+
+static void usbhs1_phy_reset(struct platform_device *pdev)
+{
+ struct usbhs_private *priv = usbhs_get_priv(pdev);
+
+ /* init phy */
+ __raw_writew(0x8a0a, priv->usbcrcaddr);
+}
+
+static u32 usbhs1_pipe_cfg[] = {
+ USB_ENDPOINT_XFER_CONTROL,
+ USB_ENDPOINT_XFER_ISOC,
+ USB_ENDPOINT_XFER_ISOC,
+ USB_ENDPOINT_XFER_BULK,
+ USB_ENDPOINT_XFER_BULK,
+ USB_ENDPOINT_XFER_BULK,
+ USB_ENDPOINT_XFER_INT,
+ USB_ENDPOINT_XFER_INT,
+ USB_ENDPOINT_XFER_INT,
+ USB_ENDPOINT_XFER_BULK,
+ USB_ENDPOINT_XFER_BULK,
+ USB_ENDPOINT_XFER_BULK,
+ USB_ENDPOINT_XFER_BULK,
+ USB_ENDPOINT_XFER_BULK,
+ USB_ENDPOINT_XFER_BULK,
+ USB_ENDPOINT_XFER_BULK,
+};
+
+static struct usbhs_private usbhs1_private = {
+ .irq = evt2irq(0x0300), /* IRQ8 */
+ .usbphyaddr = 0xE60581E2, /* USBPHY1INTAP */
+ .usbcrcaddr = 0xE6058130, /* USBCR4 */
+ .info = {
+ .platform_callback = {
+ .hardware_init = usbhs1_hardware_init,
+ .hardware_exit = usbhs1_hardware_exit,
+ .phy_reset = usbhs1_phy_reset,
+ .get_id = usbhs1_get_id,
+ .get_vbus = usbhs1_get_vbus,
+ },
+ .driver_param = {
+ .buswait_bwait = 4,
+ .pipe_type = usbhs1_pipe_cfg,
+ .pipe_size = ARRAY_SIZE(usbhs1_pipe_cfg),
+ },
+ },
+};
+
+static struct resource usbhs1_resources[] = {
+ [0] = {
+ .name = "USBHS",
+ .start = 0xE68B0000,
+ .end = 0xE68B00E6 - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = evt2irq(0x1ce0) /* USB1_USB1I0 */,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device usbhs1_device = {
+ .name = "renesas_usbhs",
+ .id = 1,
+ .dev = {
+ .platform_data = &usbhs1_private.info,
+ },
+ .num_resources = ARRAY_SIZE(usbhs1_resources),
+ .resource = usbhs1_resources,
+};
+
+
/* LED */
static struct gpio_led mackerel_leds[] = {
{
@@ -690,7 +870,15 @@
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = evt2irq(0x0e00) /* SDHI0 */,
+ .start = evt2irq(0x0e00) /* SDHI0_SDHI0I0 */,
+ .flags = IORESOURCE_IRQ,
+ },
+ [2] = {
+ .start = evt2irq(0x0e20) /* SDHI0_SDHI0I1 */,
+ .flags = IORESOURCE_IRQ,
+ },
+ [3] = {
+ .start = evt2irq(0x0e40) /* SDHI0_SDHI0I2 */,
.flags = IORESOURCE_IRQ,
},
};
@@ -705,7 +893,7 @@
},
};
-#if !defined(CONFIG_MMC_SH_MMCIF)
+#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
/* SDHI1 */
static struct sh_mobile_sdhi_info sdhi1_info = {
.dma_slave_tx = SHDMA_SLAVE_SDHI1_TX,
@@ -725,7 +913,15 @@
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = evt2irq(0x0e80),
+ .start = evt2irq(0x0e80), /* SDHI1_SDHI1I0 */
+ .flags = IORESOURCE_IRQ,
+ },
+ [2] = {
+ .start = evt2irq(0x0ea0), /* SDHI1_SDHI1I1 */
+ .flags = IORESOURCE_IRQ,
+ },
+ [3] = {
+ .start = evt2irq(0x0ec0), /* SDHI1_SDHI1I2 */
.flags = IORESOURCE_IRQ,
},
};
@@ -768,7 +964,15 @@
.flags = IORESOURCE_MEM,
},
[1] = {
- .start = evt2irq(0x1200),
+ .start = evt2irq(0x1200), /* SDHI2_SDHI2I0 */
+ .flags = IORESOURCE_IRQ,
+ },
+ [2] = {
+ .start = evt2irq(0x1220), /* SDHI2_SDHI2I1 */
+ .flags = IORESOURCE_IRQ,
+ },
+ [3] = {
+ .start = evt2irq(0x1240), /* SDHI2_SDHI2I2 */
.flags = IORESOURCE_IRQ,
},
};
@@ -803,6 +1007,15 @@
},
};
+static struct sh_mmcif_dma sh_mmcif_dma = {
+ .chan_priv_rx = {
+ .slave_id = SHDMA_SLAVE_MMCIF_RX,
+ },
+ .chan_priv_tx = {
+ .slave_id = SHDMA_SLAVE_MMCIF_TX,
+ },
+};
+
static struct sh_mmcif_plat_data sh_mmcif_plat = {
.sup_pclk = 0,
.ocr = MMC_VDD_165_195 | MMC_VDD_32_33 | MMC_VDD_33_34,
@@ -810,6 +1023,7 @@
MMC_CAP_8_BIT_DATA |
MMC_CAP_NEEDS_POLL,
.get_cd = slot_cn7_get_cd,
+ .dma = &sh_mmcif_dma,
};
static struct platform_device sh_mmcif_device = {
@@ -858,37 +1072,23 @@
.priv = &camera_info,
};
-static void dummy_release(struct device *dev)
-{
-}
+static struct platform_device *camera_device;
-static struct platform_device camera_device = {
- .name = "soc_camera_platform",
- .dev = {
- .platform_data = &camera_info,
- .release = dummy_release,
- },
-};
+static void mackerel_camera_release(struct device *dev)
+{
+ soc_camera_platform_release(&camera_device);
+}
static int mackerel_camera_add(struct soc_camera_link *icl,
struct device *dev)
{
- if (icl != &camera_link)
- return -ENODEV;
-
- camera_info.dev = dev;
-
- return platform_device_register(&camera_device);
+ return soc_camera_platform_add(icl, dev, &camera_device, &camera_link,
+ mackerel_camera_release, 0);
}
static void mackerel_camera_del(struct soc_camera_link *icl)
{
- if (icl != &camera_link)
- return;
-
- platform_device_unregister(&camera_device);
- memset(&camera_device.dev.kobj, 0,
- sizeof(camera_device.dev.kobj));
+ soc_camera_platform_del(icl, camera_device, &camera_link);
}
static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
@@ -935,12 +1135,13 @@
&smc911x_device,
&lcdc_device,
&usb1_host_device,
+ &usbhs1_device,
&leds_device,
&fsi_device,
&fsi_ak4643_device,
&fsi_hdmi_device,
&sdhi0_device,
-#if !defined(CONFIG_MMC_SH_MMCIF)
+#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
&sdhi1_device,
#endif
&sdhi2_device,
@@ -1030,6 +1231,7 @@
#define GPIO_PORT9CR 0xE6051009
#define GPIO_PORT10CR 0xE605100A
+#define GPIO_PORT168CR 0xE60520A8
#define SRCR4 0xe61580bc
#define USCCR1 0xE6058144
static void __init mackerel_init(void)
@@ -1088,6 +1290,7 @@
gpio_request(GPIO_FN_OVCN_1_114, NULL);
gpio_request(GPIO_FN_EXTLP_1, NULL);
gpio_request(GPIO_FN_OVCN2_1, NULL);
+ gpio_pull_down(GPIO_PORT168CR);
/* setup USB phy */
__raw_writew(0x8a0a, 0xE6058130); /* USBCR4 */
@@ -1140,7 +1343,7 @@
gpio_request(GPIO_FN_SDHID0_1, NULL);
gpio_request(GPIO_FN_SDHID0_0, NULL);
-#if !defined(CONFIG_MMC_SH_MMCIF)
+#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
/* enable SDHI1 */
gpio_request(GPIO_FN_SDHICMD1, NULL);
gpio_request(GPIO_FN_SDHICLK1, NULL);
@@ -1216,6 +1419,7 @@
platform_add_devices(mackerel_devices, ARRAY_SIZE(mackerel_devices));
hdmi_init_pm_clock();
+ sh7372_pm_init();
}
static void __init mackerel_timer_init(void)
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c
index e9731b5..d17eb66 100644
--- a/arch/arm/mach-shmobile/clock-sh7372.c
+++ b/arch/arm/mach-shmobile/clock-sh7372.c
@@ -44,6 +44,11 @@
#define DSI1PCKCR 0xe6150098
#define PLLC01CR 0xe6150028
#define PLLC2CR 0xe615002c
+#define RMSTPCR0 0xe6150110
+#define RMSTPCR1 0xe6150114
+#define RMSTPCR2 0xe6150118
+#define RMSTPCR3 0xe615011c
+#define RMSTPCR4 0xe6150120
#define SMSTPCR0 0xe6150130
#define SMSTPCR1 0xe6150134
#define SMSTPCR2 0xe6150138
@@ -421,9 +426,6 @@
value = __raw_readl(clk->mapping->base);
- if ((value & 0x3) != 0x3)
- return 0;
-
value >>= 16;
if (value < 2)
return 0;
@@ -504,7 +506,7 @@
enum { MSTP001,
MSTP131, MSTP130,
MSTP129, MSTP128, MSTP127, MSTP126, MSTP125,
- MSTP118, MSTP117, MSTP116,
+ MSTP118, MSTP117, MSTP116, MSTP113,
MSTP106, MSTP101, MSTP100,
MSTP223,
MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
@@ -527,6 +529,7 @@
[MSTP118] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 18, 0), /* DSITX */
[MSTP117] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 17, 0), /* LCDC1 */
[MSTP116] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */
+ [MSTP113] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 13, 0), /* MERAM */
[MSTP106] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 6, 0), /* JPU */
[MSTP101] = MSTP(&div4_clks[DIV4_M1], SMSTPCR1, 1, 0), /* VPU */
[MSTP100] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */
@@ -617,6 +620,7 @@
CLKDEV_DEV_ID("sh-mipi-dsi.0", &mstp_clks[MSTP118]), /* DSITX0 */
CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1", &mstp_clks[MSTP117]), /* LCDC1 */
CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* IIC0 */
+ CLKDEV_DEV_ID("sh_mobile_meram.0", &mstp_clks[MSTP113]), /* MERAM */
CLKDEV_DEV_ID("uio_pdrv_genirq.5", &mstp_clks[MSTP106]), /* JPU */
CLKDEV_DEV_ID("uio_pdrv_genirq.0", &mstp_clks[MSTP101]), /* VPU */
CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]), /* LCDC0 */
@@ -634,6 +638,7 @@
CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* IIC1 */
CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[MSTP322]), /* USB0 */
CLKDEV_DEV_ID("r8a66597_udc.0", &mstp_clks[MSTP322]), /* USB0 */
+ CLKDEV_DEV_ID("renesas_usbhs.0", &mstp_clks[MSTP322]), /* USB0 */
CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */
CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMC */
@@ -644,6 +649,7 @@
CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* IIC4 */
CLKDEV_DEV_ID("r8a66597_hcd.1", &mstp_clks[MSTP406]), /* USB1 */
CLKDEV_DEV_ID("r8a66597_udc.1", &mstp_clks[MSTP406]), /* USB1 */
+ CLKDEV_DEV_ID("renesas_usbhs.1", &mstp_clks[MSTP406]), /* USB1 */
CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
CLKDEV_ICK_ID("ick", "sh-mobile-hdmi", &div6_reparent_clks[DIV6_HDMI]),
@@ -655,6 +661,13 @@
{
int k, ret = 0;
+ /* make sure MSTP bits on the RT/SH4AL-DSP side are off */
+ __raw_writel(0xe4ef8087, RMSTPCR0);
+ __raw_writel(0xffffffff, RMSTPCR1);
+ __raw_writel(0x37c7f7ff, RMSTPCR2);
+ __raw_writel(0xffffffff, RMSTPCR3);
+ __raw_writel(0xffe0fffd, RMSTPCR4);
+
for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
ret = clk_register(main_clks[k]);
diff --git a/arch/arm/mach-shmobile/clock-sh73a0.c b/arch/arm/mach-shmobile/clock-sh73a0.c
index 7e58904..bcacb1e 100644
--- a/arch/arm/mach-shmobile/clock-sh73a0.c
+++ b/arch/arm/mach-shmobile/clock-sh73a0.c
@@ -266,7 +266,8 @@
MSTP129, MSTP128, MSTP127, MSTP126, MSTP125, MSTP118, MSTP116, MSTP100,
MSTP219,
MSTP207, MSTP206, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
- MSTP331, MSTP329, MSTP325, MSTP323, MSTP312,
+ MSTP331, MSTP329, MSTP325, MSTP323, MSTP318,
+ MSTP314, MSTP313, MSTP312, MSTP311,
MSTP411, MSTP410, MSTP403,
MSTP_NR };
@@ -295,7 +296,11 @@
[MSTP329] = MSTP(&r_clk, SMSTPCR3, 29, 0), /* CMT10 */
[MSTP325] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 25, 0), /* IrDA */
[MSTP323] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 23, 0), /* IIC1 */
+ [MSTP318] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 18, 0), /* SY-DMAC */
+ [MSTP314] = MSTP(&div6_clks[DIV6_SDHI0], SMSTPCR3, 14, 0), /* SDHI0 */
+ [MSTP313] = MSTP(&div6_clks[DIV6_SDHI1], SMSTPCR3, 13, 0), /* SDHI1 */
[MSTP312] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMCIF0 */
+ [MSTP311] = MSTP(&div6_clks[DIV6_SDHI2], SMSTPCR3, 11, 0), /* SDHI2 */
[MSTP411] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 11, 0), /* IIC3 */
[MSTP410] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 10, 0), /* IIC4 */
[MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */
@@ -313,6 +318,9 @@
CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]),
CLKDEV_CON_ID("vck3_clk", &div6_clks[DIV6_VCK3]),
+ CLKDEV_CON_ID("sdhi0_clk", &div6_clks[DIV6_SDHI0]),
+ CLKDEV_CON_ID("sdhi1_clk", &div6_clks[DIV6_SDHI1]),
+ CLKDEV_CON_ID("sdhi2_clk", &div6_clks[DIV6_SDHI2]),
CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSIT]),
CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSIT]),
CLKDEV_ICK_ID("dsi0p_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSI0P]),
@@ -341,7 +349,11 @@
CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]), /* CMT10 */
CLKDEV_DEV_ID("sh_irda.0", &mstp_clks[MSTP325]), /* IrDA */
CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* I2C1 */
+ CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP318]), /* SY-DMAC */
+ CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */
+ CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMCIF0 */
+ CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP311]), /* SDHI2 */
CLKDEV_DEV_ID("i2c-sh_mobile.3", &mstp_clks[MSTP411]), /* I2C3 */
CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* I2C4 */
CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
@@ -351,6 +363,11 @@
{
int k, ret = 0;
+ /* Set SDHI clocks to a known state */
+ __raw_writel(0x108, SD0CKCR);
+ __raw_writel(0x108, SD1CKCR);
+ __raw_writel(0x108, SD2CKCR);
+
/* detect main clock parent */
switch ((__raw_readl(CKSCR) >> 24) & 0x03) {
case 0:
diff --git a/arch/arm/mach-shmobile/cpuidle.c b/arch/arm/mach-shmobile/cpuidle.c
new file mode 100644
index 0000000..2e44f11
--- /dev/null
+++ b/arch/arm/mach-shmobile/cpuidle.c
@@ -0,0 +1,92 @@
+/*
+ * CPUIdle support code for SH-Mobile ARM
+ *
+ * Copyright (C) 2011 Magnus Damm
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/pm.h>
+#include <linux/cpuidle.h>
+#include <linux/suspend.h>
+#include <linux/module.h>
+#include <linux/err.h>
+#include <asm/system.h>
+#include <asm/io.h>
+
+static void shmobile_enter_wfi(void)
+{
+ cpu_do_idle();
+}
+
+void (*shmobile_cpuidle_modes[CPUIDLE_STATE_MAX])(void) = {
+ shmobile_enter_wfi, /* regular sleep mode */
+};
+
+static int shmobile_cpuidle_enter(struct cpuidle_device *dev,
+ struct cpuidle_state *state)
+{
+ ktime_t before, after;
+ int requested_state = state - &dev->states[0];
+
+ dev->last_state = &dev->states[requested_state];
+ before = ktime_get();
+
+ local_irq_disable();
+ local_fiq_disable();
+
+ shmobile_cpuidle_modes[requested_state]();
+
+ local_irq_enable();
+ local_fiq_enable();
+
+ after = ktime_get();
+ return ktime_to_ns(ktime_sub(after, before)) >> 10;
+}
+
+static struct cpuidle_device shmobile_cpuidle_dev;
+static struct cpuidle_driver shmobile_cpuidle_driver = {
+ .name = "shmobile_cpuidle",
+ .owner = THIS_MODULE,
+};
+
+void (*shmobile_cpuidle_setup)(struct cpuidle_device *dev);
+
+static int shmobile_cpuidle_init(void)
+{
+ struct cpuidle_device *dev = &shmobile_cpuidle_dev;
+ struct cpuidle_state *state;
+ int i;
+
+ cpuidle_register_driver(&shmobile_cpuidle_driver);
+
+ for (i = 0; i < CPUIDLE_STATE_MAX; i++) {
+ dev->states[i].name[0] = '\0';
+ dev->states[i].desc[0] = '\0';
+ dev->states[i].enter = shmobile_cpuidle_enter;
+ }
+
+ i = CPUIDLE_DRIVER_STATE_START;
+
+ state = &dev->states[i++];
+ snprintf(state->name, CPUIDLE_NAME_LEN, "C1");
+ strncpy(state->desc, "WFI", CPUIDLE_DESC_LEN);
+ state->exit_latency = 1;
+ state->target_residency = 1 * 2;
+ state->power_usage = 3;
+ state->flags = 0;
+ state->flags |= CPUIDLE_FLAG_TIME_VALID;
+
+ dev->safe_state = state;
+ dev->state_count = i;
+
+ if (shmobile_cpuidle_setup)
+ shmobile_cpuidle_setup(dev);
+
+ cpuidle_register_device(dev);
+
+ return 0;
+}
+late_initcall(shmobile_cpuidle_init);
diff --git a/arch/arm/mach-shmobile/headsmp.S b/arch/arm/mach-shmobile/headsmp.S
index d4cec6b..26079d9 100644
--- a/arch/arm/mach-shmobile/headsmp.S
+++ b/arch/arm/mach-shmobile/headsmp.S
@@ -24,4 +24,4 @@
.align 12
ENTRY(shmobile_secondary_vector)
ldr pc, 1f
-1: .long secondary_startup - PAGE_OFFSET + PHYS_OFFSET
+1: .long secondary_startup - PAGE_OFFSET + PLAT_PHYS_OFFSET
diff --git a/arch/arm/mach-shmobile/include/mach/common.h b/arch/arm/mach-shmobile/include/mach/common.h
index 013ac0e..06aecb3 100644
--- a/arch/arm/mach-shmobile/include/mach/common.h
+++ b/arch/arm/mach-shmobile/include/mach/common.h
@@ -8,6 +8,10 @@
extern int clk_init(void);
extern void shmobile_handle_irq_intc(struct pt_regs *);
extern void shmobile_handle_irq_gic(struct pt_regs *);
+extern struct platform_suspend_ops shmobile_suspend_ops;
+struct cpuidle_device;
+extern void (*shmobile_cpuidle_modes[])(void);
+extern void (*shmobile_cpuidle_setup)(struct cpuidle_device *dev);
extern void sh7367_init_irq(void);
extern void sh7367_add_early_devices(void);
@@ -30,6 +34,9 @@
extern void sh7372_add_standard_devices(void);
extern void sh7372_clock_init(void);
extern void sh7372_pinmux_init(void);
+extern void sh7372_pm_init(void);
+extern void sh7372_cpu_suspend(void);
+extern void sh7372_cpu_resume(void);
extern struct clk sh7372_extal1_clk;
extern struct clk sh7372_extal2_clk;
diff --git a/arch/arm/mach-shmobile/include/mach/head-ap4evb.txt b/arch/arm/mach-shmobile/include/mach/head-ap4evb.txt
index 3029aba..9f134df 100644
--- a/arch/arm/mach-shmobile/include/mach/head-ap4evb.txt
+++ b/arch/arm/mach-shmobile/include/mach/head-ap4evb.txt
@@ -87,8 +87,7 @@
ED 0xFE400354, 0x01AD8002
LIST "SCIF0 - Serial port for earlyprintk"
-EB 0xE6053098, 0x11
EB 0xE6053098, 0xe1
EW 0xE6C40000, 0x0000
EB 0xE6C40004, 0x19
-EW 0xE6C40008, 0x3000
+EW 0xE6C40008, 0x0030
diff --git a/arch/arm/mach-shmobile/include/mach/head-mackerel.txt b/arch/arm/mach-shmobile/include/mach/head-mackerel.txt
index 3029aba..9f134df 100644
--- a/arch/arm/mach-shmobile/include/mach/head-mackerel.txt
+++ b/arch/arm/mach-shmobile/include/mach/head-mackerel.txt
@@ -87,8 +87,7 @@
ED 0xFE400354, 0x01AD8002
LIST "SCIF0 - Serial port for earlyprintk"
-EB 0xE6053098, 0x11
EB 0xE6053098, 0xe1
EW 0xE6C40000, 0x0000
EB 0xE6C40004, 0x19
-EW 0xE6C40008, 0x3000
+EW 0xE6C40008, 0x0030
diff --git a/arch/arm/mach-shmobile/include/mach/sh7372.h b/arch/arm/mach-shmobile/include/mach/sh7372.h
index 5736efc..df20d76 100644
--- a/arch/arm/mach-shmobile/include/mach/sh7372.h
+++ b/arch/arm/mach-shmobile/include/mach/sh7372.h
@@ -435,6 +435,7 @@
/* DMA slave IDs */
enum {
+ SHDMA_SLAVE_INVALID,
SHDMA_SLAVE_SCIF0_TX,
SHDMA_SLAVE_SCIF0_RX,
SHDMA_SLAVE_SCIF1_TX,
diff --git a/arch/arm/mach-shmobile/include/mach/sh73a0.h b/arch/arm/mach-shmobile/include/mach/sh73a0.h
index ceb2cdc..216c3d6 100644
--- a/arch/arm/mach-shmobile/include/mach/sh73a0.h
+++ b/arch/arm/mach-shmobile/include/mach/sh73a0.h
@@ -463,5 +463,35 @@
GPIO_FN_FSIAIBT_PU,
GPIO_FN_FSIAISLD_PU,
};
+/* DMA slave IDs */
+enum {
+ SHDMA_SLAVE_INVALID,
+ SHDMA_SLAVE_SCIF0_TX,
+ SHDMA_SLAVE_SCIF0_RX,
+ SHDMA_SLAVE_SCIF1_TX,
+ SHDMA_SLAVE_SCIF1_RX,
+ SHDMA_SLAVE_SCIF2_TX,
+ SHDMA_SLAVE_SCIF2_RX,
+ SHDMA_SLAVE_SCIF3_TX,
+ SHDMA_SLAVE_SCIF3_RX,
+ SHDMA_SLAVE_SCIF4_TX,
+ SHDMA_SLAVE_SCIF4_RX,
+ SHDMA_SLAVE_SCIF5_TX,
+ SHDMA_SLAVE_SCIF5_RX,
+ SHDMA_SLAVE_SCIF6_TX,
+ SHDMA_SLAVE_SCIF6_RX,
+ SHDMA_SLAVE_SCIF7_TX,
+ SHDMA_SLAVE_SCIF7_RX,
+ SHDMA_SLAVE_SCIF8_TX,
+ SHDMA_SLAVE_SCIF8_RX,
+ SHDMA_SLAVE_SDHI0_TX,
+ SHDMA_SLAVE_SDHI0_RX,
+ SHDMA_SLAVE_SDHI1_TX,
+ SHDMA_SLAVE_SDHI1_RX,
+ SHDMA_SLAVE_SDHI2_TX,
+ SHDMA_SLAVE_SDHI2_RX,
+ SHDMA_SLAVE_MMCIF_TX,
+ SHDMA_SLAVE_MMCIF_RX,
+};
#endif /* __ASM_SH73A0_H__ */
diff --git a/arch/arm/mach-shmobile/include/mach/smp.h b/arch/arm/mach-shmobile/include/mach/smp.h
deleted file mode 100644
index 50db94e..0000000
--- a/arch/arm/mach-shmobile/include/mach/smp.h
+++ /dev/null
@@ -1,16 +0,0 @@
-#ifndef __MACH_SMP_H
-#define __MACH_SMP_H
-
-#include <asm/hardware/gic.h>
-
-/*
- * We use IRQ1 as the IPI
- */
-static inline void smp_cross_call(const struct cpumask *mask, int ipi)
-{
-#if defined(CONFIG_ARM_GIC)
- gic_raise_softirq(mask, ipi);
-#endif
-}
-
-#endif
diff --git a/arch/arm/mach-shmobile/intc-sh7372.c b/arch/arm/mach-shmobile/intc-sh7372.c
index 7a4960f..3b28743 100644
--- a/arch/arm/mach-shmobile/intc-sh7372.c
+++ b/arch/arm/mach-shmobile/intc-sh7372.c
@@ -27,8 +27,6 @@
enum {
UNUSED_INTCA = 0,
- ENABLED,
- DISABLED,
/* interrupt sources INTCA */
IRQ0A, IRQ1A, IRQ2A, IRQ3A, IRQ4A, IRQ5A, IRQ6A, IRQ7A,
@@ -49,14 +47,14 @@
MSIOF2, MSIOF1,
SCIFA4, SCIFA5, SCIFB,
FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
- SDHI0,
- SDHI1,
+ SDHI0_SDHI0I0, SDHI0_SDHI0I1, SDHI0_SDHI0I2, SDHI0_SDHI0I3,
+ SDHI1_SDHI1I0, SDHI1_SDHI1I1, SDHI1_SDHI1I2,
IRREM,
IRDA,
TPU0,
TTI20,
DDM,
- SDHI2,
+ SDHI2_SDHI2I0, SDHI2_SDHI2I1, SDHI2_SDHI2I2, SDHI2_SDHI2I3,
RWDT0,
DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3,
DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR,
@@ -84,7 +82,7 @@
/* interrupt groups INTCA */
DMAC1_1, DMAC1_2, DMAC2_1, DMAC2_2, DMAC3_1, DMAC3_2, SHWYSTAT,
- AP_ARM1, AP_ARM2, SPU2, FLCTL, IIC1
+ AP_ARM1, AP_ARM2, SPU2, FLCTL, IIC1, SDHI0, SDHI1, SDHI2
};
static struct intc_vect intca_vectors[] __initdata = {
@@ -125,17 +123,17 @@
INTC_VECT(SCIFB, 0x0d60),
INTC_VECT(FLCTL_FLSTEI, 0x0d80), INTC_VECT(FLCTL_FLTENDI, 0x0da0),
INTC_VECT(FLCTL_FLTREQ0I, 0x0dc0), INTC_VECT(FLCTL_FLTREQ1I, 0x0de0),
- INTC_VECT(SDHI0, 0x0e00), INTC_VECT(SDHI0, 0x0e20),
- INTC_VECT(SDHI0, 0x0e40), INTC_VECT(SDHI0, 0x0e60),
- INTC_VECT(SDHI1, 0x0e80), INTC_VECT(SDHI1, 0x0ea0),
- INTC_VECT(SDHI1, 0x0ec0),
+ INTC_VECT(SDHI0_SDHI0I0, 0x0e00), INTC_VECT(SDHI0_SDHI0I1, 0x0e20),
+ INTC_VECT(SDHI0_SDHI0I2, 0x0e40), INTC_VECT(SDHI0_SDHI0I3, 0x0e60),
+ INTC_VECT(SDHI1_SDHI1I0, 0x0e80), INTC_VECT(SDHI1_SDHI1I1, 0x0ea0),
+ INTC_VECT(SDHI1_SDHI1I2, 0x0ec0),
INTC_VECT(IRREM, 0x0f60),
INTC_VECT(IRDA, 0x0480),
INTC_VECT(TPU0, 0x04a0),
INTC_VECT(TTI20, 0x1100),
INTC_VECT(DDM, 0x1140),
- INTC_VECT(SDHI2, 0x1200), INTC_VECT(SDHI2, 0x1220),
- INTC_VECT(SDHI2, 0x1240), INTC_VECT(SDHI2, 0x1260),
+ INTC_VECT(SDHI2_SDHI2I0, 0x1200), INTC_VECT(SDHI2_SDHI2I1, 0x1220),
+ INTC_VECT(SDHI2_SDHI2I2, 0x1240), INTC_VECT(SDHI2_SDHI2I3, 0x1260),
INTC_VECT(RWDT0, 0x1280),
INTC_VECT(DMAC1_1_DEI0, 0x2000), INTC_VECT(DMAC1_1_DEI1, 0x2020),
INTC_VECT(DMAC1_1_DEI2, 0x2040), INTC_VECT(DMAC1_1_DEI3, 0x2060),
@@ -195,6 +193,12 @@
INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI,
FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1),
+ INTC_GROUP(SDHI0, SDHI0_SDHI0I0, SDHI0_SDHI0I1,
+ SDHI0_SDHI0I2, SDHI0_SDHI0I3),
+ INTC_GROUP(SDHI1, SDHI1_SDHI1I0, SDHI1_SDHI1I1,
+ SDHI1_SDHI1I2),
+ INTC_GROUP(SDHI2, SDHI2_SDHI2I0, SDHI2_SDHI2I1,
+ SDHI2_SDHI2I2, SDHI2_SDHI2I3),
INTC_GROUP(SHWYSTAT, SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM),
};
@@ -230,10 +234,10 @@
{ SCIFB, SCIFA5, SCIFA4, MSIOF1,
0, 0, MSIOF2, 0 } },
{ 0xe694009c, 0xe69400dc, 8, /* IMR7A / IMCR7A */
- { DISABLED, ENABLED, ENABLED, ENABLED,
+ { SDHI0_SDHI0I3, SDHI0_SDHI0I2, SDHI0_SDHI0I1, SDHI0_SDHI0I0,
FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
{ 0xe69400a0, 0xe69400e0, 8, /* IMR8A / IMCR8A */
- { 0, ENABLED, ENABLED, ENABLED,
+ { 0, SDHI1_SDHI1I2, SDHI1_SDHI1I1, SDHI1_SDHI1I0,
TTI20, USBHSDMAC0_USHDMI, 0, 0 } },
{ 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */
{ CMT1_CMT13, CMT1_CMT12, CMT1_CMT11, CMT1_CMT10,
@@ -248,7 +252,7 @@
{ 0, 0, TPU0, 0,
0, 0, 0, 0 } },
{ 0xe69400b4, 0xe69400f4, 8, /* IMR13A / IMCR13A */
- { DISABLED, DISABLED, ENABLED, ENABLED,
+ { SDHI2_SDHI2I3, SDHI2_SDHI2I2, SDHI2_SDHI2I1, SDHI2_SDHI2I0,
0, CMT3, 0, RWDT0 } },
{ 0xe6950080, 0xe69500c0, 8, /* IMR0A3 / IMCR0A3 */
{ SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, 0,
@@ -354,14 +358,10 @@
{ IRQ24A, IRQ25A, IRQ26A, IRQ27A, IRQ28A, IRQ29A, IRQ30A, IRQ31A } },
};
-static struct intc_desc intca_desc __initdata = {
- .name = "sh7372-intca",
- .force_enable = ENABLED,
- .force_disable = DISABLED,
- .hw = INTC_HW_DESC(intca_vectors, intca_groups,
- intca_mask_registers, intca_prio_registers,
- intca_sense_registers, intca_ack_registers),
-};
+static DECLARE_INTC_DESC_ACK(intca_desc, "sh7372-intca",
+ intca_vectors, intca_groups,
+ intca_mask_registers, intca_prio_registers,
+ intca_sense_registers, intca_ack_registers);
enum {
UNUSED_INTCS = 0,
diff --git a/arch/arm/mach-shmobile/platsmp.c b/arch/arm/mach-shmobile/platsmp.c
index 65e879b..f3888fe 100644
--- a/arch/arm/mach-shmobile/platsmp.c
+++ b/arch/arm/mach-shmobile/platsmp.c
@@ -16,6 +16,7 @@
#include <linux/device.h>
#include <linux/smp.h>
#include <linux/io.h>
+#include <asm/hardware/gic.h>
#include <asm/localtimer.h>
#include <asm/mach-types.h>
#include <mach/common.h>
@@ -57,6 +58,8 @@
for (i = 0; i < ncores; i++)
set_cpu_possible(i, true);
+
+ set_smp_cross_call(gic_raise_softirq);
}
void __init platform_smp_prepare_cpus(unsigned int max_cpus)
diff --git a/arch/arm/mach-shmobile/pm-sh7372.c b/arch/arm/mach-shmobile/pm-sh7372.c
new file mode 100644
index 0000000..8e4aadf
--- /dev/null
+++ b/arch/arm/mach-shmobile/pm-sh7372.c
@@ -0,0 +1,108 @@
+/*
+ * sh7372 Power management support
+ *
+ * Copyright (C) 2011 Magnus Damm
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/pm.h>
+#include <linux/suspend.h>
+#include <linux/cpuidle.h>
+#include <linux/module.h>
+#include <linux/list.h>
+#include <linux/err.h>
+#include <linux/slab.h>
+#include <asm/system.h>
+#include <asm/io.h>
+#include <asm/tlbflush.h>
+#include <mach/common.h>
+
+#define SMFRAM 0xe6a70000
+#define SYSTBCR 0xe6150024
+#define SBAR 0xe6180020
+#define APARMBAREA 0xe6f10020
+
+static void sh7372_enter_core_standby(void)
+{
+ void __iomem *smfram = (void __iomem *)SMFRAM;
+
+ __raw_writel(0, APARMBAREA); /* translate 4k */
+ __raw_writel(__pa(sh7372_cpu_resume), SBAR); /* set reset vector */
+ __raw_writel(0x10, SYSTBCR); /* enable core standby */
+
+ __raw_writel(0, smfram + 0x3c); /* clear page table address */
+
+ sh7372_cpu_suspend();
+ cpu_init();
+
+ /* if page table address is non-NULL then we have been powered down */
+ if (__raw_readl(smfram + 0x3c)) {
+ __raw_writel(__raw_readl(smfram + 0x40),
+ __va(__raw_readl(smfram + 0x3c)));
+
+ flush_tlb_all();
+ set_cr(__raw_readl(smfram + 0x38));
+ }
+
+ __raw_writel(0, SYSTBCR); /* disable core standby */
+ __raw_writel(0, SBAR); /* disable reset vector translation */
+}
+
+#ifdef CONFIG_CPU_IDLE
+static void sh7372_cpuidle_setup(struct cpuidle_device *dev)
+{
+ struct cpuidle_state *state;
+ int i = dev->state_count;
+
+ state = &dev->states[i];
+ snprintf(state->name, CPUIDLE_NAME_LEN, "C2");
+ strncpy(state->desc, "Core Standby Mode", CPUIDLE_DESC_LEN);
+ state->exit_latency = 10;
+ state->target_residency = 20 + 10;
+ state->power_usage = 1; /* perhaps not */
+ state->flags = 0;
+ state->flags |= CPUIDLE_FLAG_TIME_VALID;
+ shmobile_cpuidle_modes[i] = sh7372_enter_core_standby;
+
+ dev->state_count = i + 1;
+}
+
+static void sh7372_cpuidle_init(void)
+{
+ shmobile_cpuidle_setup = sh7372_cpuidle_setup;
+}
+#else
+static void sh7372_cpuidle_init(void) {}
+#endif
+
+#ifdef CONFIG_SUSPEND
+static int sh7372_enter_suspend(suspend_state_t suspend_state)
+{
+ sh7372_enter_core_standby();
+ return 0;
+}
+
+static void sh7372_suspend_init(void)
+{
+ shmobile_suspend_ops.enter = sh7372_enter_suspend;
+}
+#else
+static void sh7372_suspend_init(void) {}
+#endif
+
+#define DBGREG1 0xe6100020
+#define DBGREG9 0xe6100040
+
+void __init sh7372_pm_init(void)
+{
+ /* enable DBG hardware block to kick SYSC */
+ __raw_writel(0x0000a500, DBGREG9);
+ __raw_writel(0x0000a501, DBGREG9);
+ __raw_writel(0x00000000, DBGREG1);
+
+ sh7372_suspend_init();
+ sh7372_cpuidle_init();
+}
diff --git a/arch/arm/mach-shmobile/setup-sh7367.c b/arch/arm/mach-shmobile/setup-sh7367.c
index ce28141..2c10190 100644
--- a/arch/arm/mach-shmobile/setup-sh7367.c
+++ b/arch/arm/mach-shmobile/setup-sh7367.c
@@ -22,6 +22,7 @@
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/platform_device.h>
+#include <linux/uio_driver.h>
#include <linux/delay.h>
#include <linux/input.h>
#include <linux/io.h>
@@ -195,6 +196,214 @@
.num_resources = ARRAY_SIZE(cmt10_resources),
};
+/* VPU */
+static struct uio_info vpu_platform_data = {
+ .name = "VPU5",
+ .version = "0",
+ .irq = intcs_evt2irq(0x980),
+};
+
+static struct resource vpu_resources[] = {
+ [0] = {
+ .name = "VPU",
+ .start = 0xfe900000,
+ .end = 0xfe902807,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device vpu_device = {
+ .name = "uio_pdrv_genirq",
+ .id = 0,
+ .dev = {
+ .platform_data = &vpu_platform_data,
+ },
+ .resource = vpu_resources,
+ .num_resources = ARRAY_SIZE(vpu_resources),
+};
+
+/* VEU0 */
+static struct uio_info veu0_platform_data = {
+ .name = "VEU0",
+ .version = "0",
+ .irq = intcs_evt2irq(0x700),
+};
+
+static struct resource veu0_resources[] = {
+ [0] = {
+ .name = "VEU0",
+ .start = 0xfe920000,
+ .end = 0xfe9200b7,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device veu0_device = {
+ .name = "uio_pdrv_genirq",
+ .id = 1,
+ .dev = {
+ .platform_data = &veu0_platform_data,
+ },
+ .resource = veu0_resources,
+ .num_resources = ARRAY_SIZE(veu0_resources),
+};
+
+/* VEU1 */
+static struct uio_info veu1_platform_data = {
+ .name = "VEU1",
+ .version = "0",
+ .irq = intcs_evt2irq(0x720),
+};
+
+static struct resource veu1_resources[] = {
+ [0] = {
+ .name = "VEU1",
+ .start = 0xfe924000,
+ .end = 0xfe9240b7,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device veu1_device = {
+ .name = "uio_pdrv_genirq",
+ .id = 2,
+ .dev = {
+ .platform_data = &veu1_platform_data,
+ },
+ .resource = veu1_resources,
+ .num_resources = ARRAY_SIZE(veu1_resources),
+};
+
+/* VEU2 */
+static struct uio_info veu2_platform_data = {
+ .name = "VEU2",
+ .version = "0",
+ .irq = intcs_evt2irq(0x740),
+};
+
+static struct resource veu2_resources[] = {
+ [0] = {
+ .name = "VEU2",
+ .start = 0xfe928000,
+ .end = 0xfe9280b7,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device veu2_device = {
+ .name = "uio_pdrv_genirq",
+ .id = 3,
+ .dev = {
+ .platform_data = &veu2_platform_data,
+ },
+ .resource = veu2_resources,
+ .num_resources = ARRAY_SIZE(veu2_resources),
+};
+
+/* VEU3 */
+static struct uio_info veu3_platform_data = {
+ .name = "VEU3",
+ .version = "0",
+ .irq = intcs_evt2irq(0x760),
+};
+
+static struct resource veu3_resources[] = {
+ [0] = {
+ .name = "VEU3",
+ .start = 0xfe92c000,
+ .end = 0xfe92c0b7,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device veu3_device = {
+ .name = "uio_pdrv_genirq",
+ .id = 4,
+ .dev = {
+ .platform_data = &veu3_platform_data,
+ },
+ .resource = veu3_resources,
+ .num_resources = ARRAY_SIZE(veu3_resources),
+};
+
+/* VEU2H */
+static struct uio_info veu2h_platform_data = {
+ .name = "VEU2H",
+ .version = "0",
+ .irq = intcs_evt2irq(0x520),
+};
+
+static struct resource veu2h_resources[] = {
+ [0] = {
+ .name = "VEU2H",
+ .start = 0xfe93c000,
+ .end = 0xfe93c27b,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device veu2h_device = {
+ .name = "uio_pdrv_genirq",
+ .id = 5,
+ .dev = {
+ .platform_data = &veu2h_platform_data,
+ },
+ .resource = veu2h_resources,
+ .num_resources = ARRAY_SIZE(veu2h_resources),
+};
+
+/* JPU */
+static struct uio_info jpu_platform_data = {
+ .name = "JPU",
+ .version = "0",
+ .irq = intcs_evt2irq(0x560),
+};
+
+static struct resource jpu_resources[] = {
+ [0] = {
+ .name = "JPU",
+ .start = 0xfe980000,
+ .end = 0xfe9902d3,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device jpu_device = {
+ .name = "uio_pdrv_genirq",
+ .id = 6,
+ .dev = {
+ .platform_data = &jpu_platform_data,
+ },
+ .resource = jpu_resources,
+ .num_resources = ARRAY_SIZE(jpu_resources),
+};
+
+/* SPU1 */
+static struct uio_info spu1_platform_data = {
+ .name = "SPU1",
+ .version = "0",
+ .irq = evt2irq(0xfc0),
+};
+
+static struct resource spu1_resources[] = {
+ [0] = {
+ .name = "SPU1",
+ .start = 0xfe300000,
+ .end = 0xfe3fffff,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device spu1_device = {
+ .name = "uio_pdrv_genirq",
+ .id = 7,
+ .dev = {
+ .platform_data = &spu1_platform_data,
+ },
+ .resource = spu1_resources,
+ .num_resources = ARRAY_SIZE(spu1_resources),
+};
+
static struct platform_device *sh7367_early_devices[] __initdata = {
&scif0_device,
&scif1_device,
@@ -206,10 +415,24 @@
&cmt10_device,
};
+static struct platform_device *sh7367_devices[] __initdata = {
+ &vpu_device,
+ &veu0_device,
+ &veu1_device,
+ &veu2_device,
+ &veu3_device,
+ &veu2h_device,
+ &jpu_device,
+ &spu1_device,
+};
+
void __init sh7367_add_standard_devices(void)
{
platform_add_devices(sh7367_early_devices,
ARRAY_SIZE(sh7367_early_devices));
+
+ platform_add_devices(sh7367_devices,
+ ARRAY_SIZE(sh7367_devices));
}
#define SYMSTPCR2 0xe6158048
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
index ff0494f..cd807ee 100644
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ b/arch/arm/mach-shmobile/setup-sh7372.c
@@ -22,6 +22,7 @@
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/platform_device.h>
+#include <linux/uio_driver.h>
#include <linux/delay.h>
#include <linux/input.h>
#include <linux/io.h>
@@ -601,6 +602,214 @@
},
};
+/* VPU */
+static struct uio_info vpu_platform_data = {
+ .name = "VPU5HG",
+ .version = "0",
+ .irq = intcs_evt2irq(0x980),
+};
+
+static struct resource vpu_resources[] = {
+ [0] = {
+ .name = "VPU",
+ .start = 0xfe900000,
+ .end = 0xfe900157,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device vpu_device = {
+ .name = "uio_pdrv_genirq",
+ .id = 0,
+ .dev = {
+ .platform_data = &vpu_platform_data,
+ },
+ .resource = vpu_resources,
+ .num_resources = ARRAY_SIZE(vpu_resources),
+};
+
+/* VEU0 */
+static struct uio_info veu0_platform_data = {
+ .name = "VEU0",
+ .version = "0",
+ .irq = intcs_evt2irq(0x700),
+};
+
+static struct resource veu0_resources[] = {
+ [0] = {
+ .name = "VEU0",
+ .start = 0xfe920000,
+ .end = 0xfe9200cb,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device veu0_device = {
+ .name = "uio_pdrv_genirq",
+ .id = 1,
+ .dev = {
+ .platform_data = &veu0_platform_data,
+ },
+ .resource = veu0_resources,
+ .num_resources = ARRAY_SIZE(veu0_resources),
+};
+
+/* VEU1 */
+static struct uio_info veu1_platform_data = {
+ .name = "VEU1",
+ .version = "0",
+ .irq = intcs_evt2irq(0x720),
+};
+
+static struct resource veu1_resources[] = {
+ [0] = {
+ .name = "VEU1",
+ .start = 0xfe924000,
+ .end = 0xfe9240cb,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device veu1_device = {
+ .name = "uio_pdrv_genirq",
+ .id = 2,
+ .dev = {
+ .platform_data = &veu1_platform_data,
+ },
+ .resource = veu1_resources,
+ .num_resources = ARRAY_SIZE(veu1_resources),
+};
+
+/* VEU2 */
+static struct uio_info veu2_platform_data = {
+ .name = "VEU2",
+ .version = "0",
+ .irq = intcs_evt2irq(0x740),
+};
+
+static struct resource veu2_resources[] = {
+ [0] = {
+ .name = "VEU2",
+ .start = 0xfe928000,
+ .end = 0xfe928307,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device veu2_device = {
+ .name = "uio_pdrv_genirq",
+ .id = 3,
+ .dev = {
+ .platform_data = &veu2_platform_data,
+ },
+ .resource = veu2_resources,
+ .num_resources = ARRAY_SIZE(veu2_resources),
+};
+
+/* VEU3 */
+static struct uio_info veu3_platform_data = {
+ .name = "VEU3",
+ .version = "0",
+ .irq = intcs_evt2irq(0x760),
+};
+
+static struct resource veu3_resources[] = {
+ [0] = {
+ .name = "VEU3",
+ .start = 0xfe92c000,
+ .end = 0xfe92c307,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device veu3_device = {
+ .name = "uio_pdrv_genirq",
+ .id = 4,
+ .dev = {
+ .platform_data = &veu3_platform_data,
+ },
+ .resource = veu3_resources,
+ .num_resources = ARRAY_SIZE(veu3_resources),
+};
+
+/* JPU */
+static struct uio_info jpu_platform_data = {
+ .name = "JPU",
+ .version = "0",
+ .irq = intcs_evt2irq(0x560),
+};
+
+static struct resource jpu_resources[] = {
+ [0] = {
+ .name = "JPU",
+ .start = 0xfe980000,
+ .end = 0xfe9902d3,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device jpu_device = {
+ .name = "uio_pdrv_genirq",
+ .id = 5,
+ .dev = {
+ .platform_data = &jpu_platform_data,
+ },
+ .resource = jpu_resources,
+ .num_resources = ARRAY_SIZE(jpu_resources),
+};
+
+/* SPU2DSP0 */
+static struct uio_info spu0_platform_data = {
+ .name = "SPU2DSP0",
+ .version = "0",
+ .irq = evt2irq(0x1800),
+};
+
+static struct resource spu0_resources[] = {
+ [0] = {
+ .name = "SPU2DSP0",
+ .start = 0xfe200000,
+ .end = 0xfe2fffff,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device spu0_device = {
+ .name = "uio_pdrv_genirq",
+ .id = 6,
+ .dev = {
+ .platform_data = &spu0_platform_data,
+ },
+ .resource = spu0_resources,
+ .num_resources = ARRAY_SIZE(spu0_resources),
+};
+
+/* SPU2DSP1 */
+static struct uio_info spu1_platform_data = {
+ .name = "SPU2DSP1",
+ .version = "0",
+ .irq = evt2irq(0x1820),
+};
+
+static struct resource spu1_resources[] = {
+ [0] = {
+ .name = "SPU2DSP1",
+ .start = 0xfe300000,
+ .end = 0xfe3fffff,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device spu1_device = {
+ .name = "uio_pdrv_genirq",
+ .id = 7,
+ .dev = {
+ .platform_data = &spu1_platform_data,
+ },
+ .resource = spu1_resources,
+ .num_resources = ARRAY_SIZE(spu1_resources),
+};
+
static struct platform_device *sh7372_early_devices[] __initdata = {
&scif0_device,
&scif1_device,
@@ -620,6 +829,14 @@
&dma0_device,
&dma1_device,
&dma2_device,
+ &vpu_device,
+ &veu0_device,
+ &veu1_device,
+ &veu2_device,
+ &veu3_device,
+ &jpu_device,
+ &spu0_device,
+ &spu1_device,
};
void __init sh7372_add_standard_devices(void)
diff --git a/arch/arm/mach-shmobile/setup-sh7377.c b/arch/arm/mach-shmobile/setup-sh7377.c
index 8099b0b..bb405b8 100644
--- a/arch/arm/mach-shmobile/setup-sh7377.c
+++ b/arch/arm/mach-shmobile/setup-sh7377.c
@@ -22,6 +22,7 @@
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/platform_device.h>
+#include <linux/uio_driver.h>
#include <linux/delay.h>
#include <linux/input.h>
#include <linux/io.h>
@@ -38,7 +39,7 @@
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
- .type = PORT_SCIF,
+ .type = PORT_SCIFA,
.irqs = { evt2irq(0xc00), evt2irq(0xc00),
evt2irq(0xc00), evt2irq(0xc00) },
};
@@ -57,7 +58,7 @@
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
- .type = PORT_SCIF,
+ .type = PORT_SCIFA,
.irqs = { evt2irq(0xc20), evt2irq(0xc20),
evt2irq(0xc20), evt2irq(0xc20) },
};
@@ -76,7 +77,7 @@
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
- .type = PORT_SCIF,
+ .type = PORT_SCIFA,
.irqs = { evt2irq(0xc40), evt2irq(0xc40),
evt2irq(0xc40), evt2irq(0xc40) },
};
@@ -95,7 +96,7 @@
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
- .type = PORT_SCIF,
+ .type = PORT_SCIFA,
.irqs = { evt2irq(0xc60), evt2irq(0xc60),
evt2irq(0xc60), evt2irq(0xc60) },
};
@@ -114,7 +115,7 @@
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
- .type = PORT_SCIF,
+ .type = PORT_SCIFA,
.irqs = { evt2irq(0xd20), evt2irq(0xd20),
evt2irq(0xd20), evt2irq(0xd20) },
};
@@ -133,7 +134,7 @@
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
- .type = PORT_SCIF,
+ .type = PORT_SCIFA,
.irqs = { evt2irq(0xd40), evt2irq(0xd40),
evt2irq(0xd40), evt2irq(0xd40) },
};
@@ -152,7 +153,7 @@
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
- .type = PORT_SCIF,
+ .type = PORT_SCIFA,
.irqs = { intcs_evt2irq(0x1a80), intcs_evt2irq(0x1a80),
intcs_evt2irq(0x1a80), intcs_evt2irq(0x1a80) },
};
@@ -171,7 +172,7 @@
.flags = UPF_BOOT_AUTOCONF,
.scscr = SCSCR_RE | SCSCR_TE,
.scbrr_algo_id = SCBRR_ALGO_4,
- .type = PORT_SCIF,
+ .type = PORT_SCIFB,
.irqs = { evt2irq(0xd60), evt2irq(0xd60),
evt2irq(0xd60), evt2irq(0xd60) },
};
@@ -215,6 +216,214 @@
.num_resources = ARRAY_SIZE(cmt10_resources),
};
+/* VPU */
+static struct uio_info vpu_platform_data = {
+ .name = "VPU5HG",
+ .version = "0",
+ .irq = intcs_evt2irq(0x980),
+};
+
+static struct resource vpu_resources[] = {
+ [0] = {
+ .name = "VPU",
+ .start = 0xfe900000,
+ .end = 0xfe900157,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device vpu_device = {
+ .name = "uio_pdrv_genirq",
+ .id = 0,
+ .dev = {
+ .platform_data = &vpu_platform_data,
+ },
+ .resource = vpu_resources,
+ .num_resources = ARRAY_SIZE(vpu_resources),
+};
+
+/* VEU0 */
+static struct uio_info veu0_platform_data = {
+ .name = "VEU0",
+ .version = "0",
+ .irq = intcs_evt2irq(0x700),
+};
+
+static struct resource veu0_resources[] = {
+ [0] = {
+ .name = "VEU0",
+ .start = 0xfe920000,
+ .end = 0xfe9200cb,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device veu0_device = {
+ .name = "uio_pdrv_genirq",
+ .id = 1,
+ .dev = {
+ .platform_data = &veu0_platform_data,
+ },
+ .resource = veu0_resources,
+ .num_resources = ARRAY_SIZE(veu0_resources),
+};
+
+/* VEU1 */
+static struct uio_info veu1_platform_data = {
+ .name = "VEU1",
+ .version = "0",
+ .irq = intcs_evt2irq(0x720),
+};
+
+static struct resource veu1_resources[] = {
+ [0] = {
+ .name = "VEU1",
+ .start = 0xfe924000,
+ .end = 0xfe9240cb,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device veu1_device = {
+ .name = "uio_pdrv_genirq",
+ .id = 2,
+ .dev = {
+ .platform_data = &veu1_platform_data,
+ },
+ .resource = veu1_resources,
+ .num_resources = ARRAY_SIZE(veu1_resources),
+};
+
+/* VEU2 */
+static struct uio_info veu2_platform_data = {
+ .name = "VEU2",
+ .version = "0",
+ .irq = intcs_evt2irq(0x740),
+};
+
+static struct resource veu2_resources[] = {
+ [0] = {
+ .name = "VEU2",
+ .start = 0xfe928000,
+ .end = 0xfe928307,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device veu2_device = {
+ .name = "uio_pdrv_genirq",
+ .id = 3,
+ .dev = {
+ .platform_data = &veu2_platform_data,
+ },
+ .resource = veu2_resources,
+ .num_resources = ARRAY_SIZE(veu2_resources),
+};
+
+/* VEU3 */
+static struct uio_info veu3_platform_data = {
+ .name = "VEU3",
+ .version = "0",
+ .irq = intcs_evt2irq(0x760),
+};
+
+static struct resource veu3_resources[] = {
+ [0] = {
+ .name = "VEU3",
+ .start = 0xfe92c000,
+ .end = 0xfe92c307,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device veu3_device = {
+ .name = "uio_pdrv_genirq",
+ .id = 4,
+ .dev = {
+ .platform_data = &veu3_platform_data,
+ },
+ .resource = veu3_resources,
+ .num_resources = ARRAY_SIZE(veu3_resources),
+};
+
+/* JPU */
+static struct uio_info jpu_platform_data = {
+ .name = "JPU",
+ .version = "0",
+ .irq = intcs_evt2irq(0x560),
+};
+
+static struct resource jpu_resources[] = {
+ [0] = {
+ .name = "JPU",
+ .start = 0xfe980000,
+ .end = 0xfe9902d3,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device jpu_device = {
+ .name = "uio_pdrv_genirq",
+ .id = 5,
+ .dev = {
+ .platform_data = &jpu_platform_data,
+ },
+ .resource = jpu_resources,
+ .num_resources = ARRAY_SIZE(jpu_resources),
+};
+
+/* SPU2DSP0 */
+static struct uio_info spu0_platform_data = {
+ .name = "SPU2DSP0",
+ .version = "0",
+ .irq = evt2irq(0x1800),
+};
+
+static struct resource spu0_resources[] = {
+ [0] = {
+ .name = "SPU2DSP0",
+ .start = 0xfe200000,
+ .end = 0xfe2fffff,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device spu0_device = {
+ .name = "uio_pdrv_genirq",
+ .id = 6,
+ .dev = {
+ .platform_data = &spu0_platform_data,
+ },
+ .resource = spu0_resources,
+ .num_resources = ARRAY_SIZE(spu0_resources),
+};
+
+/* SPU2DSP1 */
+static struct uio_info spu1_platform_data = {
+ .name = "SPU2DSP1",
+ .version = "0",
+ .irq = evt2irq(0x1820),
+};
+
+static struct resource spu1_resources[] = {
+ [0] = {
+ .name = "SPU2DSP1",
+ .start = 0xfe300000,
+ .end = 0xfe3fffff,
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device spu1_device = {
+ .name = "uio_pdrv_genirq",
+ .id = 7,
+ .dev = {
+ .platform_data = &spu1_platform_data,
+ },
+ .resource = spu1_resources,
+ .num_resources = ARRAY_SIZE(spu1_resources),
+};
+
static struct platform_device *sh7377_early_devices[] __initdata = {
&scif0_device,
&scif1_device,
@@ -227,10 +436,24 @@
&cmt10_device,
};
+static struct platform_device *sh7377_devices[] __initdata = {
+ &vpu_device,
+ &veu0_device,
+ &veu1_device,
+ &veu2_device,
+ &veu3_device,
+ &jpu_device,
+ &spu0_device,
+ &spu1_device,
+};
+
void __init sh7377_add_standard_devices(void)
{
platform_add_devices(sh7377_early_devices,
ARRAY_SIZE(sh7377_early_devices));
+
+ platform_add_devices(sh7377_devices,
+ ARRAY_SIZE(sh7377_devices));
}
#define SMSTPCR3 0xe615013c
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index 685c40a..e46821c 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -27,9 +27,11 @@
#include <linux/input.h>
#include <linux/io.h>
#include <linux/serial_sci.h>
+#include <linux/sh_dma.h>
#include <linux/sh_intc.h>
#include <linux/sh_timer.h>
#include <mach/hardware.h>
+#include <mach/sh73a0.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
@@ -392,6 +394,242 @@
.num_resources = ARRAY_SIZE(i2c4_resources),
};
+/* Transmit sizes and respective CHCR register values */
+enum {
+ XMIT_SZ_8BIT = 0,
+ XMIT_SZ_16BIT = 1,
+ XMIT_SZ_32BIT = 2,
+ XMIT_SZ_64BIT = 7,
+ XMIT_SZ_128BIT = 3,
+ XMIT_SZ_256BIT = 4,
+ XMIT_SZ_512BIT = 5,
+};
+
+/* log2(size / 8) - used to calculate number of transfers */
+#define TS_SHIFT { \
+ [XMIT_SZ_8BIT] = 0, \
+ [XMIT_SZ_16BIT] = 1, \
+ [XMIT_SZ_32BIT] = 2, \
+ [XMIT_SZ_64BIT] = 3, \
+ [XMIT_SZ_128BIT] = 4, \
+ [XMIT_SZ_256BIT] = 5, \
+ [XMIT_SZ_512BIT] = 6, \
+}
+
+#define TS_INDEX2VAL(i) ((((i) & 3) << 3) | (((i) & 0xc) << (20 - 2)))
+#define CHCR_TX(xmit_sz) (DM_FIX | SM_INC | 0x800 | TS_INDEX2VAL((xmit_sz)))
+#define CHCR_RX(xmit_sz) (DM_INC | SM_FIX | 0x800 | TS_INDEX2VAL((xmit_sz)))
+
+static const struct sh_dmae_slave_config sh73a0_dmae_slaves[] = {
+ {
+ .slave_id = SHDMA_SLAVE_SCIF0_TX,
+ .addr = 0xe6c40020,
+ .chcr = CHCR_TX(XMIT_SZ_8BIT),
+ .mid_rid = 0x21,
+ }, {
+ .slave_id = SHDMA_SLAVE_SCIF0_RX,
+ .addr = 0xe6c40024,
+ .chcr = CHCR_RX(XMIT_SZ_8BIT),
+ .mid_rid = 0x22,
+ }, {
+ .slave_id = SHDMA_SLAVE_SCIF1_TX,
+ .addr = 0xe6c50020,
+ .chcr = CHCR_TX(XMIT_SZ_8BIT),
+ .mid_rid = 0x25,
+ }, {
+ .slave_id = SHDMA_SLAVE_SCIF1_RX,
+ .addr = 0xe6c50024,
+ .chcr = CHCR_RX(XMIT_SZ_8BIT),
+ .mid_rid = 0x26,
+ }, {
+ .slave_id = SHDMA_SLAVE_SCIF2_TX,
+ .addr = 0xe6c60020,
+ .chcr = CHCR_TX(XMIT_SZ_8BIT),
+ .mid_rid = 0x29,
+ }, {
+ .slave_id = SHDMA_SLAVE_SCIF2_RX,
+ .addr = 0xe6c60024,
+ .chcr = CHCR_RX(XMIT_SZ_8BIT),
+ .mid_rid = 0x2a,
+ }, {
+ .slave_id = SHDMA_SLAVE_SCIF3_TX,
+ .addr = 0xe6c70020,
+ .chcr = CHCR_TX(XMIT_SZ_8BIT),
+ .mid_rid = 0x2d,
+ }, {
+ .slave_id = SHDMA_SLAVE_SCIF3_RX,
+ .addr = 0xe6c70024,
+ .chcr = CHCR_RX(XMIT_SZ_8BIT),
+ .mid_rid = 0x2e,
+ }, {
+ .slave_id = SHDMA_SLAVE_SCIF4_TX,
+ .addr = 0xe6c80020,
+ .chcr = CHCR_TX(XMIT_SZ_8BIT),
+ .mid_rid = 0x39,
+ }, {
+ .slave_id = SHDMA_SLAVE_SCIF4_RX,
+ .addr = 0xe6c80024,
+ .chcr = CHCR_RX(XMIT_SZ_8BIT),
+ .mid_rid = 0x3a,
+ }, {
+ .slave_id = SHDMA_SLAVE_SCIF5_TX,
+ .addr = 0xe6cb0020,
+ .chcr = CHCR_TX(XMIT_SZ_8BIT),
+ .mid_rid = 0x35,
+ }, {
+ .slave_id = SHDMA_SLAVE_SCIF5_RX,
+ .addr = 0xe6cb0024,
+ .chcr = CHCR_RX(XMIT_SZ_8BIT),
+ .mid_rid = 0x36,
+ }, {
+ .slave_id = SHDMA_SLAVE_SCIF6_TX,
+ .addr = 0xe6cc0020,
+ .chcr = CHCR_TX(XMIT_SZ_8BIT),
+ .mid_rid = 0x1d,
+ }, {
+ .slave_id = SHDMA_SLAVE_SCIF6_RX,
+ .addr = 0xe6cc0024,
+ .chcr = CHCR_RX(XMIT_SZ_8BIT),
+ .mid_rid = 0x1e,
+ }, {
+ .slave_id = SHDMA_SLAVE_SCIF7_TX,
+ .addr = 0xe6cd0020,
+ .chcr = CHCR_TX(XMIT_SZ_8BIT),
+ .mid_rid = 0x19,
+ }, {
+ .slave_id = SHDMA_SLAVE_SCIF7_RX,
+ .addr = 0xe6cd0024,
+ .chcr = CHCR_RX(XMIT_SZ_8BIT),
+ .mid_rid = 0x1a,
+ }, {
+ .slave_id = SHDMA_SLAVE_SCIF8_TX,
+ .addr = 0xe6c30040,
+ .chcr = CHCR_TX(XMIT_SZ_8BIT),
+ .mid_rid = 0x3d,
+ }, {
+ .slave_id = SHDMA_SLAVE_SCIF8_RX,
+ .addr = 0xe6c30060,
+ .chcr = CHCR_RX(XMIT_SZ_8BIT),
+ .mid_rid = 0x3e,
+ }, {
+ .slave_id = SHDMA_SLAVE_SDHI0_TX,
+ .addr = 0xee100030,
+ .chcr = CHCR_TX(XMIT_SZ_16BIT),
+ .mid_rid = 0xc1,
+ }, {
+ .slave_id = SHDMA_SLAVE_SDHI0_RX,
+ .addr = 0xee100030,
+ .chcr = CHCR_RX(XMIT_SZ_16BIT),
+ .mid_rid = 0xc2,
+ }, {
+ .slave_id = SHDMA_SLAVE_SDHI1_TX,
+ .addr = 0xee120030,
+ .chcr = CHCR_TX(XMIT_SZ_16BIT),
+ .mid_rid = 0xc9,
+ }, {
+ .slave_id = SHDMA_SLAVE_SDHI1_RX,
+ .addr = 0xee120030,
+ .chcr = CHCR_RX(XMIT_SZ_16BIT),
+ .mid_rid = 0xca,
+ }, {
+ .slave_id = SHDMA_SLAVE_SDHI2_TX,
+ .addr = 0xee140030,
+ .chcr = CHCR_TX(XMIT_SZ_16BIT),
+ .mid_rid = 0xcd,
+ }, {
+ .slave_id = SHDMA_SLAVE_SDHI2_RX,
+ .addr = 0xee140030,
+ .chcr = CHCR_RX(XMIT_SZ_16BIT),
+ .mid_rid = 0xce,
+ }, {
+ .slave_id = SHDMA_SLAVE_MMCIF_TX,
+ .addr = 0xe6bd0034,
+ .chcr = CHCR_TX(XMIT_SZ_32BIT),
+ .mid_rid = 0xd1,
+ }, {
+ .slave_id = SHDMA_SLAVE_MMCIF_RX,
+ .addr = 0xe6bd0034,
+ .chcr = CHCR_RX(XMIT_SZ_32BIT),
+ .mid_rid = 0xd2,
+ },
+};
+
+#define DMAE_CHANNEL(_offset) \
+ { \
+ .offset = _offset - 0x20, \
+ .dmars = _offset - 0x20 + 0x40, \
+ }
+
+static const struct sh_dmae_channel sh73a0_dmae_channels[] = {
+ DMAE_CHANNEL(0x8000),
+ DMAE_CHANNEL(0x8080),
+ DMAE_CHANNEL(0x8100),
+ DMAE_CHANNEL(0x8180),
+ DMAE_CHANNEL(0x8200),
+ DMAE_CHANNEL(0x8280),
+ DMAE_CHANNEL(0x8300),
+ DMAE_CHANNEL(0x8380),
+ DMAE_CHANNEL(0x8400),
+ DMAE_CHANNEL(0x8480),
+ DMAE_CHANNEL(0x8500),
+ DMAE_CHANNEL(0x8580),
+ DMAE_CHANNEL(0x8600),
+ DMAE_CHANNEL(0x8680),
+ DMAE_CHANNEL(0x8700),
+ DMAE_CHANNEL(0x8780),
+ DMAE_CHANNEL(0x8800),
+ DMAE_CHANNEL(0x8880),
+ DMAE_CHANNEL(0x8900),
+ DMAE_CHANNEL(0x8980),
+};
+
+static const unsigned int ts_shift[] = TS_SHIFT;
+
+static struct sh_dmae_pdata sh73a0_dmae_platform_data = {
+ .slave = sh73a0_dmae_slaves,
+ .slave_num = ARRAY_SIZE(sh73a0_dmae_slaves),
+ .channel = sh73a0_dmae_channels,
+ .channel_num = ARRAY_SIZE(sh73a0_dmae_channels),
+ .ts_low_shift = 3,
+ .ts_low_mask = 0x18,
+ .ts_high_shift = (20 - 2), /* 2 bits for shifted low TS */
+ .ts_high_mask = 0x00300000,
+ .ts_shift = ts_shift,
+ .ts_shift_num = ARRAY_SIZE(ts_shift),
+ .dmaor_init = DMAOR_DME,
+};
+
+static struct resource sh73a0_dmae_resources[] = {
+ {
+ /* Registers including DMAOR and channels including DMARSx */
+ .start = 0xfe000020,
+ .end = 0xfe008a00 - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ {
+ /* DMA error IRQ */
+ .start = gic_spi(129),
+ .end = gic_spi(129),
+ .flags = IORESOURCE_IRQ,
+ },
+ {
+ /* IRQ for channels 0-19 */
+ .start = gic_spi(109),
+ .end = gic_spi(128),
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device dma0_device = {
+ .name = "sh-dma-engine",
+ .id = 0,
+ .resource = sh73a0_dmae_resources,
+ .num_resources = ARRAY_SIZE(sh73a0_dmae_resources),
+ .dev = {
+ .platform_data = &sh73a0_dmae_platform_data,
+ },
+};
+
static struct platform_device *sh73a0_early_devices[] __initdata = {
&scif0_device,
&scif1_device,
@@ -413,10 +651,16 @@
&i2c2_device,
&i2c3_device,
&i2c4_device,
+ &dma0_device,
};
+#define SRCR2 0xe61580b0
+
void __init sh73a0_add_standard_devices(void)
{
+ /* Clear software reset bit on SY-DMAC module */
+ __raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2);
+
platform_add_devices(sh73a0_early_devices,
ARRAY_SIZE(sh73a0_early_devices));
platform_add_devices(sh73a0_late_devices,
diff --git a/arch/arm/mach-shmobile/sleep-sh7372.S b/arch/arm/mach-shmobile/sleep-sh7372.S
new file mode 100644
index 0000000..d37d3ca
--- /dev/null
+++ b/arch/arm/mach-shmobile/sleep-sh7372.S
@@ -0,0 +1,260 @@
+/*
+ * sh7372 lowlevel sleep code for "Core Standby Mode"
+ *
+ * Copyright (C) 2011 Magnus Damm
+ *
+ * In "Core Standby Mode" the ARM core is off, but L2 cache is still on
+ *
+ * Based on mach-omap2/sleep34xx.S
+ *
+ * (C) Copyright 2007 Texas Instruments
+ * Karthik Dasu <karthik-dp@ti.com>
+ *
+ * (C) Copyright 2004 Texas Instruments, <www.ti.com>
+ * Richard Woodruff <r-woodruff2@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <linux/linkage.h>
+#include <asm/assembler.h>
+
+#define SMFRAM 0xe6a70000
+
+ .align
+kernel_flush:
+ .word v7_flush_dcache_all
+
+ .align 3
+ENTRY(sh7372_cpu_suspend)
+ stmfd sp!, {r0-r12, lr} @ save registers on stack
+
+ ldr r8, =SMFRAM
+
+ mov r4, sp @ Store sp
+ mrs r5, spsr @ Store spsr
+ mov r6, lr @ Store lr
+ stmia r8!, {r4-r6}
+
+ mrc p15, 0, r4, c1, c0, 2 @ Coprocessor access control register
+ mrc p15, 0, r5, c2, c0, 0 @ TTBR0
+ mrc p15, 0, r6, c2, c0, 1 @ TTBR1
+ mrc p15, 0, r7, c2, c0, 2 @ TTBCR
+ stmia r8!, {r4-r7}
+
+ mrc p15, 0, r4, c3, c0, 0 @ Domain access Control Register
+ mrc p15, 0, r5, c10, c2, 0 @ PRRR
+ mrc p15, 0, r6, c10, c2, 1 @ NMRR
+ stmia r8!,{r4-r6}
+
+ mrc p15, 0, r4, c13, c0, 1 @ Context ID
+ mrc p15, 0, r5, c13, c0, 2 @ User r/w thread and process ID
+ mrc p15, 0, r6, c12, c0, 0 @ Secure or NS vector base address
+ mrs r7, cpsr @ Store current cpsr
+ stmia r8!, {r4-r7}
+
+ mrc p15, 0, r4, c1, c0, 0 @ save control register
+ stmia r8!, {r4}
+
+ /*
+ * jump out to kernel flush routine
+ * - reuse that code is better
+ * - it executes in a cached space so is faster than refetch per-block
+ * - should be faster and will change with kernel
+ * - 'might' have to copy address, load and jump to it
+ * Flush all data from the L1 data cache before disabling
+ * SCTLR.C bit.
+ */
+ ldr r1, kernel_flush
+ mov lr, pc
+ bx r1
+
+ /*
+ * Clear the SCTLR.C bit to prevent further data cache
+ * allocation. Clearing SCTLR.C would make all the data accesses
+ * strongly ordered and would not hit the cache.
+ */
+ mrc p15, 0, r0, c1, c0, 0
+ bic r0, r0, #(1 << 2) @ Disable the C bit
+ mcr p15, 0, r0, c1, c0, 0
+ isb
+
+ /*
+ * Invalidate L1 data cache. Even though only invalidate is
+ * necessary exported flush API is used here. Doing clean
+ * on already clean cache would be almost NOP.
+ */
+ ldr r1, kernel_flush
+ blx r1
+ /*
+ * The kernel doesn't interwork: v7_flush_dcache_all in particluar will
+ * always return in Thumb state when CONFIG_THUMB2_KERNEL is enabled.
+ * This sequence switches back to ARM. Note that .align may insert a
+ * nop: bx pc needs to be word-aligned in order to work.
+ */
+ THUMB( .thumb )
+ THUMB( .align )
+ THUMB( bx pc )
+ THUMB( nop )
+ .arm
+
+ /* Data memory barrier and Data sync barrier */
+ dsb
+ dmb
+
+/*
+ * ===================================
+ * == WFI instruction => Enter idle ==
+ * ===================================
+ */
+ wfi @ wait for interrupt
+
+/*
+ * ===================================
+ * == Resume path for non-OFF modes ==
+ * ===================================
+ */
+ mrc p15, 0, r0, c1, c0, 0
+ tst r0, #(1 << 2) @ Check C bit enabled?
+ orreq r0, r0, #(1 << 2) @ Enable the C bit if cleared
+ mcreq p15, 0, r0, c1, c0, 0
+ isb
+
+/*
+ * ===================================
+ * == Exit point from non-OFF modes ==
+ * ===================================
+ */
+ ldmfd sp!, {r0-r12, pc} @ restore regs and return
+
+ .pool
+
+ .align 12
+ .text
+ .global sh7372_cpu_resume
+sh7372_cpu_resume:
+
+ mov r1, #0
+ /*
+ * Invalidate all instruction caches to PoU
+ * and flush branch target cache
+ */
+ mcr p15, 0, r1, c7, c5, 0
+
+ ldr r3, =SMFRAM
+
+ ldmia r3!, {r4-r6}
+ mov sp, r4 @ Restore sp
+ msr spsr_cxsf, r5 @ Restore spsr
+ mov lr, r6 @ Restore lr
+
+ ldmia r3!, {r4-r7}
+ mcr p15, 0, r4, c1, c0, 2 @ Coprocessor access Control Register
+ mcr p15, 0, r5, c2, c0, 0 @ TTBR0
+ mcr p15, 0, r6, c2, c0, 1 @ TTBR1
+ mcr p15, 0, r7, c2, c0, 2 @ TTBCR
+
+ ldmia r3!,{r4-r6}
+ mcr p15, 0, r4, c3, c0, 0 @ Domain access Control Register
+ mcr p15, 0, r5, c10, c2, 0 @ PRRR
+ mcr p15, 0, r6, c10, c2, 1 @ NMRR
+
+ ldmia r3!,{r4-r7}
+ mcr p15, 0, r4, c13, c0, 1 @ Context ID
+ mcr p15, 0, r5, c13, c0, 2 @ User r/w thread and process ID
+ mrc p15, 0, r6, c12, c0, 0 @ Secure or NS vector base address
+ msr cpsr, r7 @ store cpsr
+
+ /* Starting to enable MMU here */
+ mrc p15, 0, r7, c2, c0, 2 @ Read TTBRControl
+ /* Extract N (0:2) bits and decide whether to use TTBR0 or TTBR1 */
+ and r7, #0x7
+ cmp r7, #0x0
+ beq usettbr0
+ttbr_error:
+ /*
+ * More work needs to be done to support N[0:2] value other than 0
+ * So looping here so that the error can be detected
+ */
+ b ttbr_error
+
+ .align
+cache_pred_disable_mask:
+ .word 0xFFFFE7FB
+ttbrbit_mask:
+ .word 0xFFFFC000
+table_index_mask:
+ .word 0xFFF00000
+table_entry:
+ .word 0x00000C02
+usettbr0:
+
+ mrc p15, 0, r2, c2, c0, 0
+ ldr r5, ttbrbit_mask
+ and r2, r5
+ mov r4, pc
+ ldr r5, table_index_mask
+ and r4, r5 @ r4 = 31 to 20 bits of pc
+ /* Extract the value to be written to table entry */
+ ldr r6, table_entry
+ /* r6 has the value to be written to table entry */
+ add r6, r6, r4
+ /* Getting the address of table entry to modify */
+ lsr r4, #18
+ /* r2 has the location which needs to be modified */
+ add r2, r4
+ ldr r4, [r2]
+ str r6, [r2] /* modify the table entry */
+
+ mov r7, r6
+ mov r5, r2
+ mov r6, r4
+ /* r5 = original page table address */
+ /* r6 = original page table data */
+
+ mov r0, #0
+ mcr p15, 0, r0, c7, c5, 4 @ Flush prefetch buffer
+ mcr p15, 0, r0, c7, c5, 6 @ Invalidate branch predictor array
+ mcr p15, 0, r0, c8, c5, 0 @ Invalidate instruction TLB
+ mcr p15, 0, r0, c8, c6, 0 @ Invalidate data TLB
+
+ /*
+ * Restore control register. This enables the MMU.
+ * The caches and prediction are not enabled here, they
+ * will be enabled after restoring the MMU table entry.
+ */
+ ldmia r3!, {r4}
+ stmia r3!, {r5} /* save original page table address */
+ stmia r3!, {r6} /* save original page table data */
+ stmia r3!, {r7} /* save modified page table data */
+
+ ldr r2, cache_pred_disable_mask
+ and r4, r2
+ mcr p15, 0, r4, c1, c0, 0
+ dsb
+ isb
+
+ ldr r0, =restoremmu_on
+ bx r0
+
+/*
+ * ==============================
+ * == Exit point from OFF mode ==
+ * ==============================
+ */
+restoremmu_on:
+
+ ldmfd sp!, {r0-r12, pc} @ restore regs and return
diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c
index a156d21..3ffdbc9 100644
--- a/arch/arm/mach-shmobile/smp-sh73a0.c
+++ b/arch/arm/mach-shmobile/smp-sh73a0.c
@@ -59,6 +59,11 @@
{
void __iomem *scu_base = scu_base_addr();
+#ifdef CONFIG_HAVE_ARM_TWD
+ /* twd_base needs to be initialized before percpu_timer_setup() */
+ twd_base = (void __iomem *)0xf0000600;
+#endif
+
return scu_get_core_count(scu_base);
}
@@ -82,10 +87,6 @@
void __init sh73a0_smp_prepare_cpus(void)
{
-#ifdef CONFIG_HAVE_ARM_TWD
- twd_base = (void __iomem *)0xf0000600;
-#endif
-
scu_enable(scu_base_addr());
/* Map the reset vector (in headsmp.S) */
diff --git a/arch/arm/mach-shmobile/suspend.c b/arch/arm/mach-shmobile/suspend.c
new file mode 100644
index 0000000..c1febe1
--- /dev/null
+++ b/arch/arm/mach-shmobile/suspend.c
@@ -0,0 +1,47 @@
+/*
+ * Suspend-to-RAM support code for SH-Mobile ARM
+ *
+ * Copyright (C) 2011 Magnus Damm
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/pm.h>
+#include <linux/suspend.h>
+#include <linux/module.h>
+#include <linux/err.h>
+#include <asm/system.h>
+#include <asm/io.h>
+
+static int shmobile_suspend_default_enter(suspend_state_t suspend_state)
+{
+ cpu_do_idle();
+ return 0;
+}
+
+static int shmobile_suspend_begin(suspend_state_t state)
+{
+ disable_hlt();
+ return 0;
+}
+
+static void shmobile_suspend_end(void)
+{
+ enable_hlt();
+}
+
+struct platform_suspend_ops shmobile_suspend_ops = {
+ .begin = shmobile_suspend_begin,
+ .end = shmobile_suspend_end,
+ .enter = shmobile_suspend_default_enter,
+ .valid = suspend_valid_only_mem,
+};
+
+static int __init shmobile_suspend_init(void)
+{
+ suspend_set_ops(&shmobile_suspend_ops);
+ return 0;
+}
+late_initcall(shmobile_suspend_init);
diff --git a/arch/arm/mach-spear3xx/Kconfig b/arch/arm/mach-spear3xx/Kconfig
index 20d1317..2cee6b0 100644
--- a/arch/arm/mach-spear3xx/Kconfig
+++ b/arch/arm/mach-spear3xx/Kconfig
@@ -4,9 +4,26 @@
if ARCH_SPEAR3XX
-choice
- prompt "SPEAr3XX Family"
- default MACH_SPEAR300
+menu "SPEAr3xx Implementations"
+config BOARD_SPEAR300_EVB
+ bool "SPEAr300 Evaluation Board"
+ select MACH_SPEAR300
+ help
+ Supports ST SPEAr300 Evaluation Board
+
+config BOARD_SPEAR310_EVB
+ bool "SPEAr310 Evaluation Board"
+ select MACH_SPEAR310
+ help
+ Supports ST SPEAr310 Evaluation Board
+
+config BOARD_SPEAR320_EVB
+ bool "SPEAr320 Evaluation Board"
+ select MACH_SPEAR320
+ help
+ Supports ST SPEAr320 Evaluation Board
+
+endmenu
config MACH_SPEAR300
bool "SPEAr300"
@@ -23,11 +40,4 @@
help
Supports ST SPEAr320 Machine
-endchoice
-
-# Adding SPEAr3XX machine specific configuration files
-source "arch/arm/mach-spear3xx/Kconfig300"
-source "arch/arm/mach-spear3xx/Kconfig310"
-source "arch/arm/mach-spear3xx/Kconfig320"
-
endif #ARCH_SPEAR3XX
diff --git a/arch/arm/mach-spear3xx/Kconfig300 b/arch/arm/mach-spear3xx/Kconfig300
deleted file mode 100644
index c519a05..0000000
--- a/arch/arm/mach-spear3xx/Kconfig300
+++ /dev/null
@@ -1,17 +0,0 @@
-#
-# SPEAr300 machine configuration file
-#
-
-if MACH_SPEAR300
-
-choice
- prompt "SPEAr300 Boards"
- default BOARD_SPEAR300_EVB
-
-config BOARD_SPEAR300_EVB
- bool "SPEAr300 Evaluation Board"
- help
- Supports ST SPEAr300 Evaluation Board
-endchoice
-
-endif #MACH_SPEAR300
diff --git a/arch/arm/mach-spear3xx/Kconfig310 b/arch/arm/mach-spear3xx/Kconfig310
deleted file mode 100644
index 60e7442..0000000
--- a/arch/arm/mach-spear3xx/Kconfig310
+++ /dev/null
@@ -1,17 +0,0 @@
-#
-# SPEAr310 machine configuration file
-#
-
-if MACH_SPEAR310
-
-choice
- prompt "SPEAr310 Boards"
- default BOARD_SPEAR310_EVB
-
-config BOARD_SPEAR310_EVB
- bool "SPEAr310 Evaluation Board"
- help
- Supports ST SPEAr310 Evaluation Board
-endchoice
-
-endif #MACH_SPEAR310
diff --git a/arch/arm/mach-spear3xx/Kconfig320 b/arch/arm/mach-spear3xx/Kconfig320
deleted file mode 100644
index 1c1d438..0000000
--- a/arch/arm/mach-spear3xx/Kconfig320
+++ /dev/null
@@ -1,17 +0,0 @@
-#
-# SPEAr320 machine configuration file
-#
-
-if MACH_SPEAR320
-
-choice
- prompt "SPEAr320 Boards"
- default BOARD_SPEAR320_EVB
-
-config BOARD_SPEAR320_EVB
- bool "SPEAr320 Evaluation Board"
- help
- Supports ST SPEAr320 Evaluation Board
-endchoice
-
-endif #MACH_SPEAR320
diff --git a/arch/arm/mach-spear3xx/clock.c b/arch/arm/mach-spear3xx/clock.c
index 98bc7ed..f67860c 100644
--- a/arch/arm/mach-spear3xx/clock.c
+++ b/arch/arm/mach-spear3xx/clock.c
@@ -13,6 +13,7 @@
#include <linux/init.h>
#include <linux/kernel.h>
+#include <asm/mach-types.h>
#include <plat/clock.h>
#include <mach/misc_regs.h>
@@ -688,56 +689,71 @@
{ .dev_id = "adc", .clk = &adc_clk},
{ .dev_id = "ssp-pl022.0", .clk = &ssp0_clk},
{ .dev_id = "gpio", .clk = &gpio_clk},
-#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
- { .dev_id = "physmap-flash", .clk = &emi_clk},
-#endif
-#if defined(CONFIG_MACH_SPEAR300) || defined(CONFIG_MACH_SPEAR310) || \
- defined(CONFIG_MACH_SPEAR320)
- { .con_id = "fsmc", .clk = &fsmc_clk},
-#endif
+};
-/* common clocks to spear310 and spear320 */
-#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
- { .dev_id = "uart1", .clk = &uart1_clk},
- { .dev_id = "uart2", .clk = &uart2_clk},
-#endif
-
- /* common clock to spear300 and spear320 */
-#if defined(CONFIG_MACH_SPEAR300) || defined(CONFIG_MACH_SPEAR320)
- { .dev_id = "clcd", .clk = &clcd_clk},
- { .dev_id = "sdhci", .clk = &sdhci_clk},
-#endif /* CONFIG_MACH_SPEAR300 || CONFIG_MACH_SPEAR320 */
-
- /* spear300 machine specific clock structures */
+/* array of all spear 300 clock lookups */
#ifdef CONFIG_MACH_SPEAR300
+static struct clk_lookup spear300_clk_lookups[] = {
+ { .dev_id = "clcd", .clk = &clcd_clk},
+ { .con_id = "fsmc", .clk = &fsmc_clk},
{ .dev_id = "gpio1", .clk = &gpio1_clk},
{ .dev_id = "keyboard", .clk = &kbd_clk},
+ { .dev_id = "sdhci", .clk = &sdhci_clk},
+};
#endif
- /* spear310 machine specific clock structures */
+/* array of all spear 310 clock lookups */
#ifdef CONFIG_MACH_SPEAR310
+static struct clk_lookup spear310_clk_lookups[] = {
+ { .con_id = "fsmc", .clk = &fsmc_clk},
+ { .con_id = "emi", .clk = &emi_clk},
+ { .dev_id = "uart1", .clk = &uart1_clk},
+ { .dev_id = "uart2", .clk = &uart2_clk},
{ .dev_id = "uart3", .clk = &uart3_clk},
{ .dev_id = "uart4", .clk = &uart4_clk},
{ .dev_id = "uart5", .clk = &uart5_clk},
-
+};
#endif
- /* spear320 machine specific clock structures */
+
+/* array of all spear 320 clock lookups */
#ifdef CONFIG_MACH_SPEAR320
+static struct clk_lookup spear320_clk_lookups[] = {
+ { .dev_id = "clcd", .clk = &clcd_clk},
+ { .con_id = "fsmc", .clk = &fsmc_clk},
+ { .dev_id = "i2c_designware.1", .clk = &i2c1_clk},
+ { .con_id = "emi", .clk = &emi_clk},
+ { .dev_id = "pwm", .clk = &pwm_clk},
+ { .dev_id = "sdhci", .clk = &sdhci_clk},
{ .dev_id = "c_can_platform.0", .clk = &can0_clk},
{ .dev_id = "c_can_platform.1", .clk = &can1_clk},
- { .dev_id = "i2c_designware.1", .clk = &i2c1_clk},
{ .dev_id = "ssp-pl022.1", .clk = &ssp1_clk},
{ .dev_id = "ssp-pl022.2", .clk = &ssp2_clk},
- { .dev_id = "pwm", .clk = &pwm_clk},
-#endif
+ { .dev_id = "uart1", .clk = &uart1_clk},
+ { .dev_id = "uart2", .clk = &uart2_clk},
};
+#endif
-void __init clk_init(void)
+void __init spear3xx_clk_init(void)
{
- int i;
+ int i, cnt;
+ struct clk_lookup *lookups;
+
+ if (machine_is_spear300()) {
+ cnt = ARRAY_SIZE(spear300_clk_lookups);
+ lookups = spear300_clk_lookups;
+ } else if (machine_is_spear310()) {
+ cnt = ARRAY_SIZE(spear310_clk_lookups);
+ lookups = spear310_clk_lookups;
+ } else {
+ cnt = ARRAY_SIZE(spear320_clk_lookups);
+ lookups = spear320_clk_lookups;
+ }
for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
clk_register(&spear_clk_lookups[i]);
- recalc_root_clocks();
+ for (i = 0; i < cnt; i++)
+ clk_register(&lookups[i]);
+
+ clk_init();
}
diff --git a/arch/arm/mach-spear3xx/include/mach/generic.h b/arch/arm/mach-spear3xx/include/mach/generic.h
index 8e30636..b8f31c3 100644
--- a/arch/arm/mach-spear3xx/include/mach/generic.h
+++ b/arch/arm/mach-spear3xx/include/mach/generic.h
@@ -27,16 +27,16 @@
* Following GPT channels will be used as clock source and clockevent
*/
#define SPEAR_GPT0_BASE SPEAR3XX_ML1_TMR_BASE
-#define SPEAR_GPT0_CHAN0_IRQ IRQ_CPU_GPT1_1
-#define SPEAR_GPT0_CHAN1_IRQ IRQ_CPU_GPT1_2
+#define SPEAR_GPT0_CHAN0_IRQ SPEAR3XX_IRQ_CPU_GPT1_1
+#define SPEAR_GPT0_CHAN1_IRQ SPEAR3XX_IRQ_CPU_GPT1_2
/* Add spear3xx family device structure declarations here */
-extern struct amba_device gpio_device;
-extern struct amba_device uart_device;
+extern struct amba_device spear3xx_gpio_device;
+extern struct amba_device spear3xx_uart_device;
extern struct sys_timer spear3xx_timer;
/* Add spear3xx family function declarations here */
-void __init clk_init(void);
+void __init spear3xx_clk_init(void);
void __init spear_setup_timer(void);
void __init spear3xx_map_io(void);
void __init spear3xx_init_irq(void);
@@ -60,81 +60,80 @@
#define PMX_TIMER_1_2_MASK (1 << 0)
/* pad mux devices */
-extern struct pmx_dev pmx_firda;
-extern struct pmx_dev pmx_i2c;
-extern struct pmx_dev pmx_ssp_cs;
-extern struct pmx_dev pmx_ssp;
-extern struct pmx_dev pmx_mii;
-extern struct pmx_dev pmx_gpio_pin0;
-extern struct pmx_dev pmx_gpio_pin1;
-extern struct pmx_dev pmx_gpio_pin2;
-extern struct pmx_dev pmx_gpio_pin3;
-extern struct pmx_dev pmx_gpio_pin4;
-extern struct pmx_dev pmx_gpio_pin5;
-extern struct pmx_dev pmx_uart0_modem;
-extern struct pmx_dev pmx_uart0;
-extern struct pmx_dev pmx_timer_3_4;
-extern struct pmx_dev pmx_timer_1_2;
+extern struct pmx_dev spear3xx_pmx_firda;
+extern struct pmx_dev spear3xx_pmx_i2c;
+extern struct pmx_dev spear3xx_pmx_ssp_cs;
+extern struct pmx_dev spear3xx_pmx_ssp;
+extern struct pmx_dev spear3xx_pmx_mii;
+extern struct pmx_dev spear3xx_pmx_gpio_pin0;
+extern struct pmx_dev spear3xx_pmx_gpio_pin1;
+extern struct pmx_dev spear3xx_pmx_gpio_pin2;
+extern struct pmx_dev spear3xx_pmx_gpio_pin3;
+extern struct pmx_dev spear3xx_pmx_gpio_pin4;
+extern struct pmx_dev spear3xx_pmx_gpio_pin5;
+extern struct pmx_dev spear3xx_pmx_uart0_modem;
+extern struct pmx_dev spear3xx_pmx_uart0;
+extern struct pmx_dev spear3xx_pmx_timer_3_4;
+extern struct pmx_dev spear3xx_pmx_timer_1_2;
#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
/* padmux plgpio devices */
-extern struct pmx_dev pmx_plgpio_0_1;
-extern struct pmx_dev pmx_plgpio_2_3;
-extern struct pmx_dev pmx_plgpio_4_5;
-extern struct pmx_dev pmx_plgpio_6_9;
-extern struct pmx_dev pmx_plgpio_10_27;
-extern struct pmx_dev pmx_plgpio_28;
-extern struct pmx_dev pmx_plgpio_29;
-extern struct pmx_dev pmx_plgpio_30;
-extern struct pmx_dev pmx_plgpio_31;
-extern struct pmx_dev pmx_plgpio_32;
-extern struct pmx_dev pmx_plgpio_33;
-extern struct pmx_dev pmx_plgpio_34_36;
-extern struct pmx_dev pmx_plgpio_37_42;
-extern struct pmx_dev pmx_plgpio_43_44_47_48;
-extern struct pmx_dev pmx_plgpio_45_46_49_50;
+extern struct pmx_dev spear3xx_pmx_plgpio_0_1;
+extern struct pmx_dev spear3xx_pmx_plgpio_2_3;
+extern struct pmx_dev spear3xx_pmx_plgpio_4_5;
+extern struct pmx_dev spear3xx_pmx_plgpio_6_9;
+extern struct pmx_dev spear3xx_pmx_plgpio_10_27;
+extern struct pmx_dev spear3xx_pmx_plgpio_28;
+extern struct pmx_dev spear3xx_pmx_plgpio_29;
+extern struct pmx_dev spear3xx_pmx_plgpio_30;
+extern struct pmx_dev spear3xx_pmx_plgpio_31;
+extern struct pmx_dev spear3xx_pmx_plgpio_32;
+extern struct pmx_dev spear3xx_pmx_plgpio_33;
+extern struct pmx_dev spear3xx_pmx_plgpio_34_36;
+extern struct pmx_dev spear3xx_pmx_plgpio_37_42;
+extern struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48;
+extern struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50;
#endif
-extern struct pmx_driver pmx_driver;
-
/* spear300 declarations */
#ifdef CONFIG_MACH_SPEAR300
/* Add spear300 machine device structure declarations here */
-extern struct amba_device gpio1_device;
+extern struct amba_device spear300_gpio1_device;
/* pad mux modes */
-extern struct pmx_mode nand_mode;
-extern struct pmx_mode nor_mode;
-extern struct pmx_mode photo_frame_mode;
-extern struct pmx_mode lend_ip_phone_mode;
-extern struct pmx_mode hend_ip_phone_mode;
-extern struct pmx_mode lend_wifi_phone_mode;
-extern struct pmx_mode hend_wifi_phone_mode;
-extern struct pmx_mode ata_pabx_wi2s_mode;
-extern struct pmx_mode ata_pabx_i2s_mode;
-extern struct pmx_mode caml_lcdw_mode;
-extern struct pmx_mode camu_lcd_mode;
-extern struct pmx_mode camu_wlcd_mode;
-extern struct pmx_mode caml_lcd_mode;
+extern struct pmx_mode spear300_nand_mode;
+extern struct pmx_mode spear300_nor_mode;
+extern struct pmx_mode spear300_photo_frame_mode;
+extern struct pmx_mode spear300_lend_ip_phone_mode;
+extern struct pmx_mode spear300_hend_ip_phone_mode;
+extern struct pmx_mode spear300_lend_wifi_phone_mode;
+extern struct pmx_mode spear300_hend_wifi_phone_mode;
+extern struct pmx_mode spear300_ata_pabx_wi2s_mode;
+extern struct pmx_mode spear300_ata_pabx_i2s_mode;
+extern struct pmx_mode spear300_caml_lcdw_mode;
+extern struct pmx_mode spear300_camu_lcd_mode;
+extern struct pmx_mode spear300_camu_wlcd_mode;
+extern struct pmx_mode spear300_caml_lcd_mode;
/* pad mux devices */
-extern struct pmx_dev pmx_fsmc_2_chips;
-extern struct pmx_dev pmx_fsmc_4_chips;
-extern struct pmx_dev pmx_keyboard;
-extern struct pmx_dev pmx_clcd;
-extern struct pmx_dev pmx_telecom_gpio;
-extern struct pmx_dev pmx_telecom_tdm;
-extern struct pmx_dev pmx_telecom_spi_cs_i2c_clk;
-extern struct pmx_dev pmx_telecom_camera;
-extern struct pmx_dev pmx_telecom_dac;
-extern struct pmx_dev pmx_telecom_i2s;
-extern struct pmx_dev pmx_telecom_boot_pins;
-extern struct pmx_dev pmx_telecom_sdhci_4bit;
-extern struct pmx_dev pmx_telecom_sdhci_8bit;
-extern struct pmx_dev pmx_gpio1;
+extern struct pmx_dev spear300_pmx_fsmc_2_chips;
+extern struct pmx_dev spear300_pmx_fsmc_4_chips;
+extern struct pmx_dev spear300_pmx_keyboard;
+extern struct pmx_dev spear300_pmx_clcd;
+extern struct pmx_dev spear300_pmx_telecom_gpio;
+extern struct pmx_dev spear300_pmx_telecom_tdm;
+extern struct pmx_dev spear300_pmx_telecom_spi_cs_i2c_clk;
+extern struct pmx_dev spear300_pmx_telecom_camera;
+extern struct pmx_dev spear300_pmx_telecom_dac;
+extern struct pmx_dev spear300_pmx_telecom_i2s;
+extern struct pmx_dev spear300_pmx_telecom_boot_pins;
+extern struct pmx_dev spear300_pmx_telecom_sdhci_4bit;
+extern struct pmx_dev spear300_pmx_telecom_sdhci_8bit;
+extern struct pmx_dev spear300_pmx_gpio1;
/* Add spear300 machine function declarations here */
-void __init spear300_init(void);
+void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
+ u8 pmx_dev_count);
#endif /* CONFIG_MACH_SPEAR300 */
@@ -143,17 +142,18 @@
/* Add spear310 machine device structure declarations here */
/* pad mux devices */
-extern struct pmx_dev pmx_emi_cs_0_1_4_5;
-extern struct pmx_dev pmx_emi_cs_2_3;
-extern struct pmx_dev pmx_uart1;
-extern struct pmx_dev pmx_uart2;
-extern struct pmx_dev pmx_uart3_4_5;
-extern struct pmx_dev pmx_fsmc;
-extern struct pmx_dev pmx_rs485_0_1;
-extern struct pmx_dev pmx_tdm0;
+extern struct pmx_dev spear310_pmx_emi_cs_0_1_4_5;
+extern struct pmx_dev spear310_pmx_emi_cs_2_3;
+extern struct pmx_dev spear310_pmx_uart1;
+extern struct pmx_dev spear310_pmx_uart2;
+extern struct pmx_dev spear310_pmx_uart3_4_5;
+extern struct pmx_dev spear310_pmx_fsmc;
+extern struct pmx_dev spear310_pmx_rs485_0_1;
+extern struct pmx_dev spear310_pmx_tdm0;
/* Add spear310 machine function declarations here */
-void __init spear310_init(void);
+void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
+ u8 pmx_dev_count);
#endif /* CONFIG_MACH_SPEAR310 */
@@ -162,37 +162,38 @@
/* Add spear320 machine device structure declarations here */
/* pad mux modes */
-extern struct pmx_mode auto_net_smii_mode;
-extern struct pmx_mode auto_net_mii_mode;
-extern struct pmx_mode auto_exp_mode;
-extern struct pmx_mode small_printers_mode;
+extern struct pmx_mode spear320_auto_net_smii_mode;
+extern struct pmx_mode spear320_auto_net_mii_mode;
+extern struct pmx_mode spear320_auto_exp_mode;
+extern struct pmx_mode spear320_small_printers_mode;
/* pad mux devices */
-extern struct pmx_dev pmx_clcd;
-extern struct pmx_dev pmx_emi;
-extern struct pmx_dev pmx_fsmc;
-extern struct pmx_dev pmx_spp;
-extern struct pmx_dev pmx_sdhci;
-extern struct pmx_dev pmx_i2s;
-extern struct pmx_dev pmx_uart1;
-extern struct pmx_dev pmx_uart1_modem;
-extern struct pmx_dev pmx_uart2;
-extern struct pmx_dev pmx_touchscreen;
-extern struct pmx_dev pmx_can;
-extern struct pmx_dev pmx_sdhci_led;
-extern struct pmx_dev pmx_pwm0;
-extern struct pmx_dev pmx_pwm1;
-extern struct pmx_dev pmx_pwm2;
-extern struct pmx_dev pmx_pwm3;
-extern struct pmx_dev pmx_ssp1;
-extern struct pmx_dev pmx_ssp2;
-extern struct pmx_dev pmx_mii1;
-extern struct pmx_dev pmx_smii0;
-extern struct pmx_dev pmx_smii1;
-extern struct pmx_dev pmx_i2c1;
+extern struct pmx_dev spear320_pmx_clcd;
+extern struct pmx_dev spear320_pmx_emi;
+extern struct pmx_dev spear320_pmx_fsmc;
+extern struct pmx_dev spear320_pmx_spp;
+extern struct pmx_dev spear320_pmx_sdhci;
+extern struct pmx_dev spear320_pmx_i2s;
+extern struct pmx_dev spear320_pmx_uart1;
+extern struct pmx_dev spear320_pmx_uart1_modem;
+extern struct pmx_dev spear320_pmx_uart2;
+extern struct pmx_dev spear320_pmx_touchscreen;
+extern struct pmx_dev spear320_pmx_can;
+extern struct pmx_dev spear320_pmx_sdhci_led;
+extern struct pmx_dev spear320_pmx_pwm0;
+extern struct pmx_dev spear320_pmx_pwm1;
+extern struct pmx_dev spear320_pmx_pwm2;
+extern struct pmx_dev spear320_pmx_pwm3;
+extern struct pmx_dev spear320_pmx_ssp1;
+extern struct pmx_dev spear320_pmx_ssp2;
+extern struct pmx_dev spear320_pmx_mii1;
+extern struct pmx_dev spear320_pmx_smii0;
+extern struct pmx_dev spear320_pmx_smii1;
+extern struct pmx_dev spear320_pmx_i2c1;
/* Add spear320 machine function declarations here */
-void __init spear320_init(void);
+void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
+ u8 pmx_dev_count);
#endif /* CONFIG_MACH_SPEAR320 */
diff --git a/arch/arm/mach-spear3xx/include/mach/irqs.h b/arch/arm/mach-spear3xx/include/mach/irqs.h
index a1a7f48..6e26544 100644
--- a/arch/arm/mach-spear3xx/include/mach/irqs.h
+++ b/arch/arm/mach-spear3xx/include/mach/irqs.h
@@ -15,138 +15,140 @@
#define __MACH_IRQS_H
/* SPEAr3xx IRQ definitions */
-#define IRQ_HW_ACCEL_MOD_0 0
-#define IRQ_INTRCOMM_RAS_ARM 1
-#define IRQ_CPU_GPT1_1 2
-#define IRQ_CPU_GPT1_2 3
-#define IRQ_BASIC_GPT1_1 4
-#define IRQ_BASIC_GPT1_2 5
-#define IRQ_BASIC_GPT2_1 6
-#define IRQ_BASIC_GPT2_2 7
-#define IRQ_BASIC_DMA 8
-#define IRQ_BASIC_SMI 9
-#define IRQ_BASIC_RTC 10
-#define IRQ_BASIC_GPIO 11
-#define IRQ_BASIC_WDT 12
-#define IRQ_DDR_CONTROLLER 13
-#define IRQ_SYS_ERROR 14
-#define IRQ_WAKEUP_RCV 15
-#define IRQ_JPEG 16
-#define IRQ_IRDA 17
-#define IRQ_ADC 18
-#define IRQ_UART 19
-#define IRQ_SSP 20
-#define IRQ_I2C 21
-#define IRQ_MAC_1 22
-#define IRQ_MAC_2 23
-#define IRQ_USB_DEV 24
-#define IRQ_USB_H_OHCI_0 25
-#define IRQ_USB_H_EHCI_0 26
-#define IRQ_USB_H_EHCI_1 IRQ_USB_H_EHCI_0
-#define IRQ_USB_H_OHCI_1 27
-#define IRQ_GEN_RAS_1 28
-#define IRQ_GEN_RAS_2 29
-#define IRQ_GEN_RAS_3 30
-#define IRQ_HW_ACCEL_MOD_1 31
-#define IRQ_VIC_END 32
+#define SPEAR3XX_IRQ_HW_ACCEL_MOD_0 0
+#define SPEAR3XX_IRQ_INTRCOMM_RAS_ARM 1
+#define SPEAR3XX_IRQ_CPU_GPT1_1 2
+#define SPEAR3XX_IRQ_CPU_GPT1_2 3
+#define SPEAR3XX_IRQ_BASIC_GPT1_1 4
+#define SPEAR3XX_IRQ_BASIC_GPT1_2 5
+#define SPEAR3XX_IRQ_BASIC_GPT2_1 6
+#define SPEAR3XX_IRQ_BASIC_GPT2_2 7
+#define SPEAR3XX_IRQ_BASIC_DMA 8
+#define SPEAR3XX_IRQ_BASIC_SMI 9
+#define SPEAR3XX_IRQ_BASIC_RTC 10
+#define SPEAR3XX_IRQ_BASIC_GPIO 11
+#define SPEAR3XX_IRQ_BASIC_WDT 12
+#define SPEAR3XX_IRQ_DDR_CONTROLLER 13
+#define SPEAR3XX_IRQ_SYS_ERROR 14
+#define SPEAR3XX_IRQ_WAKEUP_RCV 15
+#define SPEAR3XX_IRQ_JPEG 16
+#define SPEAR3XX_IRQ_IRDA 17
+#define SPEAR3XX_IRQ_ADC 18
+#define SPEAR3XX_IRQ_UART 19
+#define SPEAR3XX_IRQ_SSP 20
+#define SPEAR3XX_IRQ_I2C 21
+#define SPEAR3XX_IRQ_MAC_1 22
+#define SPEAR3XX_IRQ_MAC_2 23
+#define SPEAR3XX_IRQ_USB_DEV 24
+#define SPEAR3XX_IRQ_USB_H_OHCI_0 25
+#define SPEAR3XX_IRQ_USB_H_EHCI_0 26
+#define SPEAR3XX_IRQ_USB_H_EHCI_1 SPEAR3XX_IRQ_USB_H_EHCI_0
+#define SPEAR3XX_IRQ_USB_H_OHCI_1 27
+#define SPEAR3XX_IRQ_GEN_RAS_1 28
+#define SPEAR3XX_IRQ_GEN_RAS_2 29
+#define SPEAR3XX_IRQ_GEN_RAS_3 30
+#define SPEAR3XX_IRQ_HW_ACCEL_MOD_1 31
+#define SPEAR3XX_IRQ_VIC_END 32
-#define VIRQ_START IRQ_VIC_END
+#define SPEAR3XX_VIRQ_START SPEAR3XX_IRQ_VIC_END
/* SPEAr300 Virtual irq definitions */
-#ifdef CONFIG_MACH_SPEAR300
/* IRQs sharing IRQ_GEN_RAS_1 */
-#define VIRQ_IT_PERS_S (VIRQ_START + 0)
-#define VIRQ_IT_CHANGE_S (VIRQ_START + 1)
-#define VIRQ_I2S (VIRQ_START + 2)
-#define VIRQ_TDM (VIRQ_START + 3)
-#define VIRQ_CAMERA_L (VIRQ_START + 4)
-#define VIRQ_CAMERA_F (VIRQ_START + 5)
-#define VIRQ_CAMERA_V (VIRQ_START + 6)
-#define VIRQ_KEYBOARD (VIRQ_START + 7)
-#define VIRQ_GPIO1 (VIRQ_START + 8)
+#define SPEAR300_VIRQ_IT_PERS_S (SPEAR3XX_VIRQ_START + 0)
+#define SPEAR300_VIRQ_IT_CHANGE_S (SPEAR3XX_VIRQ_START + 1)
+#define SPEAR300_VIRQ_I2S (SPEAR3XX_VIRQ_START + 2)
+#define SPEAR300_VIRQ_TDM (SPEAR3XX_VIRQ_START + 3)
+#define SPEAR300_VIRQ_CAMERA_L (SPEAR3XX_VIRQ_START + 4)
+#define SPEAR300_VIRQ_CAMERA_F (SPEAR3XX_VIRQ_START + 5)
+#define SPEAR300_VIRQ_CAMERA_V (SPEAR3XX_VIRQ_START + 6)
+#define SPEAR300_VIRQ_KEYBOARD (SPEAR3XX_VIRQ_START + 7)
+#define SPEAR300_VIRQ_GPIO1 (SPEAR3XX_VIRQ_START + 8)
/* IRQs sharing IRQ_GEN_RAS_3 */
-#define IRQ_CLCD IRQ_GEN_RAS_3
+#define SPEAR300_IRQ_CLCD SPEAR3XX_IRQ_GEN_RAS_3
/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
-#define IRQ_SDHCI IRQ_INTRCOMM_RAS_ARM
-
-/* GPIO pins virtual irqs */
-#define SPEAR_GPIO_INT_BASE (VIRQ_START + 9)
-#define SPEAR_GPIO1_INT_BASE (SPEAR_GPIO_INT_BASE + 8)
-#define SPEAR_GPIO_INT_END (SPEAR_GPIO1_INT_BASE + 8)
+#define SPEAR300_IRQ_SDHCI SPEAR3XX_IRQ_INTRCOMM_RAS_ARM
/* SPEAr310 Virtual irq definitions */
-#elif defined(CONFIG_MACH_SPEAR310)
/* IRQs sharing IRQ_GEN_RAS_1 */
-#define VIRQ_SMII0 (VIRQ_START + 0)
-#define VIRQ_SMII1 (VIRQ_START + 1)
-#define VIRQ_SMII2 (VIRQ_START + 2)
-#define VIRQ_SMII3 (VIRQ_START + 3)
-#define VIRQ_WAKEUP_SMII0 (VIRQ_START + 4)
-#define VIRQ_WAKEUP_SMII1 (VIRQ_START + 5)
-#define VIRQ_WAKEUP_SMII2 (VIRQ_START + 6)
-#define VIRQ_WAKEUP_SMII3 (VIRQ_START + 7)
+#define SPEAR310_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 0)
+#define SPEAR310_VIRQ_SMII1 (SPEAR3XX_VIRQ_START + 1)
+#define SPEAR310_VIRQ_SMII2 (SPEAR3XX_VIRQ_START + 2)
+#define SPEAR310_VIRQ_SMII3 (SPEAR3XX_VIRQ_START + 3)
+#define SPEAR310_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 4)
+#define SPEAR310_VIRQ_WAKEUP_SMII1 (SPEAR3XX_VIRQ_START + 5)
+#define SPEAR310_VIRQ_WAKEUP_SMII2 (SPEAR3XX_VIRQ_START + 6)
+#define SPEAR310_VIRQ_WAKEUP_SMII3 (SPEAR3XX_VIRQ_START + 7)
/* IRQs sharing IRQ_GEN_RAS_2 */
-#define VIRQ_UART1 (VIRQ_START + 8)
-#define VIRQ_UART2 (VIRQ_START + 9)
-#define VIRQ_UART3 (VIRQ_START + 10)
-#define VIRQ_UART4 (VIRQ_START + 11)
-#define VIRQ_UART5 (VIRQ_START + 12)
+#define SPEAR310_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8)
+#define SPEAR310_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9)
+#define SPEAR310_VIRQ_UART3 (SPEAR3XX_VIRQ_START + 10)
+#define SPEAR310_VIRQ_UART4 (SPEAR3XX_VIRQ_START + 11)
+#define SPEAR310_VIRQ_UART5 (SPEAR3XX_VIRQ_START + 12)
/* IRQs sharing IRQ_GEN_RAS_3 */
-#define VIRQ_EMI (VIRQ_START + 13)
-#define VIRQ_PLGPIO (VIRQ_START + 14)
+#define SPEAR310_VIRQ_EMI (SPEAR3XX_VIRQ_START + 13)
+#define SPEAR310_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 14)
/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
-#define VIRQ_TDM_HDLC (VIRQ_START + 15)
-#define VIRQ_RS485_0 (VIRQ_START + 16)
-#define VIRQ_RS485_1 (VIRQ_START + 17)
-
-/* GPIO pins virtual irqs */
-#define SPEAR_GPIO_INT_BASE (VIRQ_START + 18)
+#define SPEAR310_VIRQ_TDM_HDLC (SPEAR3XX_VIRQ_START + 15)
+#define SPEAR310_VIRQ_RS485_0 (SPEAR3XX_VIRQ_START + 16)
+#define SPEAR310_VIRQ_RS485_1 (SPEAR3XX_VIRQ_START + 17)
/* SPEAr320 Virtual irq definitions */
-#else
/* IRQs sharing IRQ_GEN_RAS_1 */
-#define VIRQ_EMI (VIRQ_START + 0)
-#define VIRQ_CLCD (VIRQ_START + 1)
-#define VIRQ_SPP (VIRQ_START + 2)
+#define SPEAR320_VIRQ_EMI (SPEAR3XX_VIRQ_START + 0)
+#define SPEAR320_VIRQ_CLCD (SPEAR3XX_VIRQ_START + 1)
+#define SPEAR320_VIRQ_SPP (SPEAR3XX_VIRQ_START + 2)
/* IRQs sharing IRQ_GEN_RAS_2 */
-#define IRQ_SDHCI IRQ_GEN_RAS_2
+#define SPEAR320_IRQ_SDHCI SPEAR3XX_IRQ_GEN_RAS_2
/* IRQs sharing IRQ_GEN_RAS_3 */
-#define VIRQ_PLGPIO (VIRQ_START + 3)
-#define VIRQ_I2S_PLAY (VIRQ_START + 4)
-#define VIRQ_I2S_REC (VIRQ_START + 5)
+#define SPEAR320_VIRQ_PLGPIO (SPEAR3XX_VIRQ_START + 3)
+#define SPEAR320_VIRQ_I2S_PLAY (SPEAR3XX_VIRQ_START + 4)
+#define SPEAR320_VIRQ_I2S_REC (SPEAR3XX_VIRQ_START + 5)
/* IRQs sharing IRQ_INTRCOMM_RAS_ARM */
-#define VIRQ_CANU (VIRQ_START + 6)
-#define VIRQ_CANL (VIRQ_START + 7)
-#define VIRQ_UART1 (VIRQ_START + 8)
-#define VIRQ_UART2 (VIRQ_START + 9)
-#define VIRQ_SSP1 (VIRQ_START + 10)
-#define VIRQ_SSP2 (VIRQ_START + 11)
-#define VIRQ_SMII0 (VIRQ_START + 12)
-#define VIRQ_MII1_SMII1 (VIRQ_START + 13)
-#define VIRQ_WAKEUP_SMII0 (VIRQ_START + 14)
-#define VIRQ_WAKEUP_MII1_SMII1 (VIRQ_START + 15)
-#define VIRQ_I2C (VIRQ_START + 16)
+#define SPEAR320_VIRQ_CANU (SPEAR3XX_VIRQ_START + 6)
+#define SPEAR320_VIRQ_CANL (SPEAR3XX_VIRQ_START + 7)
+#define SPEAR320_VIRQ_UART1 (SPEAR3XX_VIRQ_START + 8)
+#define SPEAR320_VIRQ_UART2 (SPEAR3XX_VIRQ_START + 9)
+#define SPEAR320_VIRQ_SSP1 (SPEAR3XX_VIRQ_START + 10)
+#define SPEAR320_VIRQ_SSP2 (SPEAR3XX_VIRQ_START + 11)
+#define SPEAR320_VIRQ_SMII0 (SPEAR3XX_VIRQ_START + 12)
+#define SPEAR320_VIRQ_MII1_SMII1 (SPEAR3XX_VIRQ_START + 13)
+#define SPEAR320_VIRQ_WAKEUP_SMII0 (SPEAR3XX_VIRQ_START + 14)
+#define SPEAR320_VIRQ_WAKEUP_MII1_SMII1 (SPEAR3XX_VIRQ_START + 15)
+#define SPEAR320_VIRQ_I2C1 (SPEAR3XX_VIRQ_START + 16)
-/* GPIO pins virtual irqs */
-#define SPEAR_GPIO_INT_BASE (VIRQ_START + 17)
-
+/*
+ * GPIO pins virtual irqs
+ * Use the lowest number for the GPIO virtual IRQs base on which subarchs
+ * we have compiled in
+ */
+#if defined(CONFIG_MACH_SPEAR310)
+#define SPEAR3XX_GPIO_INT_BASE (SPEAR3XX_VIRQ_START + 18)
+#elif defined(CONFIG_MACH_SPEAR320)
+#define SPEAR3XX_GPIO_INT_BASE (SPEAR3XX_VIRQ_START + 17)
+#else
+#define SPEAR3XX_GPIO_INT_BASE (SPEAR3XX_VIRQ_START + 9)
#endif
-/* PLGPIO Virtual IRQs */
+#define SPEAR300_GPIO1_INT_BASE (SPEAR3XX_GPIO_INT_BASE + 8)
+#define SPEAR3XX_PLGPIO_COUNT 102
+
#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
-#define SPEAR_PLGPIO_INT_BASE (SPEAR_GPIO_INT_BASE + 8)
-#define SPEAR_GPIO_INT_END (SPEAR_PLGPIO_INT_BASE + 102)
+#define SPEAR3XX_PLGPIO_INT_BASE (SPEAR3XX_GPIO_INT_BASE + 8)
+#define SPEAR3XX_GPIO_INT_END (SPEAR3XX_PLGPIO_INT_BASE + \
+ SPEAR3XX_PLGPIO_COUNT)
+#else
+#define SPEAR3XX_GPIO_INT_END (SPEAR300_GPIO1_INT_BASE + 8)
#endif
-#define VIRQ_END SPEAR_GPIO_INT_END
-#define NR_IRQS VIRQ_END
+#define SPEAR3XX_VIRQ_END SPEAR3XX_GPIO_INT_END
+#define NR_IRQS SPEAR3XX_VIRQ_END
#endif /* __MACH_IRQS_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear300.h b/arch/arm/mach-spear3xx/include/mach/spear300.h
index c723515..3b6ea07 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear300.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear300.h
@@ -20,19 +20,19 @@
#define SPEAR300_TELECOM_BASE UL(0x50000000)
/* Interrupt registers offsets and masks */
-#define INT_ENB_MASK_REG 0x54
-#define INT_STS_MASK_REG 0x58
-#define IT_PERS_S_IRQ_MASK (1 << 0)
-#define IT_CHANGE_S_IRQ_MASK (1 << 1)
-#define I2S_IRQ_MASK (1 << 2)
-#define TDM_IRQ_MASK (1 << 3)
-#define CAMERA_L_IRQ_MASK (1 << 4)
-#define CAMERA_F_IRQ_MASK (1 << 5)
-#define CAMERA_V_IRQ_MASK (1 << 6)
-#define KEYBOARD_IRQ_MASK (1 << 7)
-#define GPIO1_IRQ_MASK (1 << 8)
+#define SPEAR300_INT_ENB_MASK_REG 0x54
+#define SPEAR300_INT_STS_MASK_REG 0x58
+#define SPEAR300_IT_PERS_S_IRQ_MASK (1 << 0)
+#define SPEAR300_IT_CHANGE_S_IRQ_MASK (1 << 1)
+#define SPEAR300_I2S_IRQ_MASK (1 << 2)
+#define SPEAR300_TDM_IRQ_MASK (1 << 3)
+#define SPEAR300_CAMERA_L_IRQ_MASK (1 << 4)
+#define SPEAR300_CAMERA_F_IRQ_MASK (1 << 5)
+#define SPEAR300_CAMERA_V_IRQ_MASK (1 << 6)
+#define SPEAR300_KEYBOARD_IRQ_MASK (1 << 7)
+#define SPEAR300_GPIO1_IRQ_MASK (1 << 8)
-#define SHIRQ_RAS1_MASK 0x1FF
+#define SPEAR300_SHIRQ_RAS1_MASK 0x1FF
#define SPEAR300_CLCD_BASE UL(0x60000000)
#define SPEAR300_SDHCI_BASE UL(0x70000000)
diff --git a/arch/arm/mach-spear3xx/include/mach/spear310.h b/arch/arm/mach-spear3xx/include/mach/spear310.h
index 1e85347..1567d0da 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear310.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear310.h
@@ -29,29 +29,29 @@
#define SPEAR310_SOC_CONFIG_BASE UL(0xB4000000)
/* Interrupt registers offsets and masks */
-#define INT_STS_MASK_REG 0x04
-#define SMII0_IRQ_MASK (1 << 0)
-#define SMII1_IRQ_MASK (1 << 1)
-#define SMII2_IRQ_MASK (1 << 2)
-#define SMII3_IRQ_MASK (1 << 3)
-#define WAKEUP_SMII0_IRQ_MASK (1 << 4)
-#define WAKEUP_SMII1_IRQ_MASK (1 << 5)
-#define WAKEUP_SMII2_IRQ_MASK (1 << 6)
-#define WAKEUP_SMII3_IRQ_MASK (1 << 7)
-#define UART1_IRQ_MASK (1 << 8)
-#define UART2_IRQ_MASK (1 << 9)
-#define UART3_IRQ_MASK (1 << 10)
-#define UART4_IRQ_MASK (1 << 11)
-#define UART5_IRQ_MASK (1 << 12)
-#define EMI_IRQ_MASK (1 << 13)
-#define TDM_HDLC_IRQ_MASK (1 << 14)
-#define RS485_0_IRQ_MASK (1 << 15)
-#define RS485_1_IRQ_MASK (1 << 16)
+#define SPEAR310_INT_STS_MASK_REG 0x04
+#define SPEAR310_SMII0_IRQ_MASK (1 << 0)
+#define SPEAR310_SMII1_IRQ_MASK (1 << 1)
+#define SPEAR310_SMII2_IRQ_MASK (1 << 2)
+#define SPEAR310_SMII3_IRQ_MASK (1 << 3)
+#define SPEAR310_WAKEUP_SMII0_IRQ_MASK (1 << 4)
+#define SPEAR310_WAKEUP_SMII1_IRQ_MASK (1 << 5)
+#define SPEAR310_WAKEUP_SMII2_IRQ_MASK (1 << 6)
+#define SPEAR310_WAKEUP_SMII3_IRQ_MASK (1 << 7)
+#define SPEAR310_UART1_IRQ_MASK (1 << 8)
+#define SPEAR310_UART2_IRQ_MASK (1 << 9)
+#define SPEAR310_UART3_IRQ_MASK (1 << 10)
+#define SPEAR310_UART4_IRQ_MASK (1 << 11)
+#define SPEAR310_UART5_IRQ_MASK (1 << 12)
+#define SPEAR310_EMI_IRQ_MASK (1 << 13)
+#define SPEAR310_TDM_HDLC_IRQ_MASK (1 << 14)
+#define SPEAR310_RS485_0_IRQ_MASK (1 << 15)
+#define SPEAR310_RS485_1_IRQ_MASK (1 << 16)
-#define SHIRQ_RAS1_MASK 0x000FF
-#define SHIRQ_RAS2_MASK 0x01F00
-#define SHIRQ_RAS3_MASK 0x02000
-#define SHIRQ_INTRCOMM_RAS_MASK 0x1C000
+#define SPEAR310_SHIRQ_RAS1_MASK 0x000FF
+#define SPEAR310_SHIRQ_RAS2_MASK 0x01F00
+#define SPEAR310_SHIRQ_RAS3_MASK 0x02000
+#define SPEAR310_SHIRQ_INTRCOMM_RAS_MASK 0x1C000
#endif /* __MACH_SPEAR310_H */
diff --git a/arch/arm/mach-spear3xx/include/mach/spear320.h b/arch/arm/mach-spear3xx/include/mach/spear320.h
index 940f0d8..8cfa83f 100644
--- a/arch/arm/mach-spear3xx/include/mach/spear320.h
+++ b/arch/arm/mach-spear3xx/include/mach/spear320.h
@@ -36,31 +36,31 @@
#define SPEAR320_SOC_CONFIG_BASE UL(0xB3000000)
/* Interrupt registers offsets and masks */
-#define INT_STS_MASK_REG 0x04
-#define INT_CLR_MASK_REG 0x04
-#define INT_ENB_MASK_REG 0x08
-#define GPIO_IRQ_MASK (1 << 0)
-#define I2S_PLAY_IRQ_MASK (1 << 1)
-#define I2S_REC_IRQ_MASK (1 << 2)
-#define EMI_IRQ_MASK (1 << 7)
-#define CLCD_IRQ_MASK (1 << 8)
-#define SPP_IRQ_MASK (1 << 9)
-#define SDHCI_IRQ_MASK (1 << 10)
-#define CAN_U_IRQ_MASK (1 << 11)
-#define CAN_L_IRQ_MASK (1 << 12)
-#define UART1_IRQ_MASK (1 << 13)
-#define UART2_IRQ_MASK (1 << 14)
-#define SSP1_IRQ_MASK (1 << 15)
-#define SSP2_IRQ_MASK (1 << 16)
-#define SMII0_IRQ_MASK (1 << 17)
-#define MII1_SMII1_IRQ_MASK (1 << 18)
-#define WAKEUP_SMII0_IRQ_MASK (1 << 19)
-#define WAKEUP_MII1_SMII1_IRQ_MASK (1 << 20)
-#define I2C1_IRQ_MASK (1 << 21)
+#define SPEAR320_INT_STS_MASK_REG 0x04
+#define SPEAR320_INT_CLR_MASK_REG 0x04
+#define SPEAR320_INT_ENB_MASK_REG 0x08
+#define SPEAR320_GPIO_IRQ_MASK (1 << 0)
+#define SPEAR320_I2S_PLAY_IRQ_MASK (1 << 1)
+#define SPEAR320_I2S_REC_IRQ_MASK (1 << 2)
+#define SPEAR320_EMI_IRQ_MASK (1 << 7)
+#define SPEAR320_CLCD_IRQ_MASK (1 << 8)
+#define SPEAR320_SPP_IRQ_MASK (1 << 9)
+#define SPEAR320_SDHCI_IRQ_MASK (1 << 10)
+#define SPEAR320_CAN_U_IRQ_MASK (1 << 11)
+#define SPEAR320_CAN_L_IRQ_MASK (1 << 12)
+#define SPEAR320_UART1_IRQ_MASK (1 << 13)
+#define SPEAR320_UART2_IRQ_MASK (1 << 14)
+#define SPEAR320_SSP1_IRQ_MASK (1 << 15)
+#define SPEAR320_SSP2_IRQ_MASK (1 << 16)
+#define SPEAR320_SMII0_IRQ_MASK (1 << 17)
+#define SPEAR320_MII1_SMII1_IRQ_MASK (1 << 18)
+#define SPEAR320_WAKEUP_SMII0_IRQ_MASK (1 << 19)
+#define SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK (1 << 20)
+#define SPEAR320_I2C1_IRQ_MASK (1 << 21)
-#define SHIRQ_RAS1_MASK 0x000380
-#define SHIRQ_RAS3_MASK 0x000007
-#define SHIRQ_INTRCOMM_RAS_MASK 0x3FF800
+#define SPEAR320_SHIRQ_RAS1_MASK 0x000380
+#define SPEAR320_SHIRQ_RAS3_MASK 0x000007
+#define SPEAR320_SHIRQ_INTRCOMM_RAS_MASK 0x3FF800
#endif /* __MACH_SPEAR320_H */
diff --git a/arch/arm/mach-spear3xx/spear300.c b/arch/arm/mach-spear3xx/spear300.c
index 2697e65..a5e46b4 100644
--- a/arch/arm/mach-spear3xx/spear300.c
+++ b/arch/arm/mach-spear3xx/spear300.c
@@ -40,86 +40,86 @@
#define CAML_LCD_MODE (1 << 12)
#define ALL_MODES 0x1FFF
-struct pmx_mode nand_mode = {
+struct pmx_mode spear300_nand_mode = {
.id = NAND_MODE,
.name = "nand mode",
.mask = 0x00,
};
-struct pmx_mode nor_mode = {
+struct pmx_mode spear300_nor_mode = {
.id = NOR_MODE,
.name = "nor mode",
.mask = 0x01,
};
-struct pmx_mode photo_frame_mode = {
+struct pmx_mode spear300_photo_frame_mode = {
.id = PHOTO_FRAME_MODE,
.name = "photo frame mode",
.mask = 0x02,
};
-struct pmx_mode lend_ip_phone_mode = {
+struct pmx_mode spear300_lend_ip_phone_mode = {
.id = LEND_IP_PHONE_MODE,
.name = "lend ip phone mode",
.mask = 0x03,
};
-struct pmx_mode hend_ip_phone_mode = {
+struct pmx_mode spear300_hend_ip_phone_mode = {
.id = HEND_IP_PHONE_MODE,
.name = "hend ip phone mode",
.mask = 0x04,
};
-struct pmx_mode lend_wifi_phone_mode = {
+struct pmx_mode spear300_lend_wifi_phone_mode = {
.id = LEND_WIFI_PHONE_MODE,
.name = "lend wifi phone mode",
.mask = 0x05,
};
-struct pmx_mode hend_wifi_phone_mode = {
+struct pmx_mode spear300_hend_wifi_phone_mode = {
.id = HEND_WIFI_PHONE_MODE,
.name = "hend wifi phone mode",
.mask = 0x06,
};
-struct pmx_mode ata_pabx_wi2s_mode = {
+struct pmx_mode spear300_ata_pabx_wi2s_mode = {
.id = ATA_PABX_WI2S_MODE,
.name = "ata pabx wi2s mode",
.mask = 0x07,
};
-struct pmx_mode ata_pabx_i2s_mode = {
+struct pmx_mode spear300_ata_pabx_i2s_mode = {
.id = ATA_PABX_I2S_MODE,
.name = "ata pabx i2s mode",
.mask = 0x08,
};
-struct pmx_mode caml_lcdw_mode = {
+struct pmx_mode spear300_caml_lcdw_mode = {
.id = CAML_LCDW_MODE,
.name = "caml lcdw mode",
.mask = 0x0C,
};
-struct pmx_mode camu_lcd_mode = {
+struct pmx_mode spear300_camu_lcd_mode = {
.id = CAMU_LCD_MODE,
.name = "camu lcd mode",
.mask = 0x0D,
};
-struct pmx_mode camu_wlcd_mode = {
+struct pmx_mode spear300_camu_wlcd_mode = {
.id = CAMU_WLCD_MODE,
.name = "camu wlcd mode",
.mask = 0x0E,
};
-struct pmx_mode caml_lcd_mode = {
+struct pmx_mode spear300_caml_lcd_mode = {
.id = CAML_LCD_MODE,
.name = "caml lcd mode",
.mask = 0x0F,
};
/* devices */
-struct pmx_dev_mode pmx_fsmc_2_chips_modes[] = {
+static struct pmx_dev_mode pmx_fsmc_2_chips_modes[] = {
{
.ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
@@ -127,14 +127,14 @@
},
};
-struct pmx_dev pmx_fsmc_2_chips = {
+struct pmx_dev spear300_pmx_fsmc_2_chips = {
.name = "fsmc_2_chips",
.modes = pmx_fsmc_2_chips_modes,
.mode_count = ARRAY_SIZE(pmx_fsmc_2_chips_modes),
.enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_fsmc_4_chips_modes[] = {
+static struct pmx_dev_mode pmx_fsmc_4_chips_modes[] = {
{
.ids = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE |
ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE,
@@ -142,14 +142,14 @@
},
};
-struct pmx_dev pmx_fsmc_4_chips = {
+struct pmx_dev spear300_pmx_fsmc_4_chips = {
.name = "fsmc_4_chips",
.modes = pmx_fsmc_4_chips_modes,
.mode_count = ARRAY_SIZE(pmx_fsmc_4_chips_modes),
.enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_keyboard_modes[] = {
+static struct pmx_dev_mode pmx_keyboard_modes[] = {
{
.ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
@@ -159,14 +159,14 @@
},
};
-struct pmx_dev pmx_keyboard = {
+struct pmx_dev spear300_pmx_keyboard = {
.name = "keyboard",
.modes = pmx_keyboard_modes,
.mode_count = ARRAY_SIZE(pmx_keyboard_modes),
.enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_clcd_modes[] = {
+static struct pmx_dev_mode pmx_clcd_modes[] = {
{
.ids = PHOTO_FRAME_MODE,
.mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK ,
@@ -177,14 +177,14 @@
},
};
-struct pmx_dev pmx_clcd = {
+struct pmx_dev spear300_pmx_clcd = {
.name = "clcd",
.modes = pmx_clcd_modes,
.mode_count = ARRAY_SIZE(pmx_clcd_modes),
.enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_telecom_gpio_modes[] = {
+static struct pmx_dev_mode pmx_telecom_gpio_modes[] = {
{
.ids = PHOTO_FRAME_MODE | CAMU_LCD_MODE | CAML_LCD_MODE,
.mask = PMX_MII_MASK,
@@ -204,14 +204,14 @@
},
};
-struct pmx_dev pmx_telecom_gpio = {
+struct pmx_dev spear300_pmx_telecom_gpio = {
.name = "telecom_gpio",
.modes = pmx_telecom_gpio_modes,
.mode_count = ARRAY_SIZE(pmx_telecom_gpio_modes),
.enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_telecom_tdm_modes[] = {
+static struct pmx_dev_mode pmx_telecom_tdm_modes[] = {
{
.ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE
@@ -222,14 +222,14 @@
},
};
-struct pmx_dev pmx_telecom_tdm = {
+struct pmx_dev spear300_pmx_telecom_tdm = {
.name = "telecom_tdm",
.modes = pmx_telecom_tdm_modes,
.mode_count = ARRAY_SIZE(pmx_telecom_tdm_modes),
.enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_telecom_spi_cs_i2c_clk_modes[] = {
+static struct pmx_dev_mode pmx_telecom_spi_cs_i2c_clk_modes[] = {
{
.ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE |
LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE
@@ -239,14 +239,14 @@
},
};
-struct pmx_dev pmx_telecom_spi_cs_i2c_clk = {
+struct pmx_dev spear300_pmx_telecom_spi_cs_i2c_clk = {
.name = "telecom_spi_cs_i2c_clk",
.modes = pmx_telecom_spi_cs_i2c_clk_modes,
.mode_count = ARRAY_SIZE(pmx_telecom_spi_cs_i2c_clk_modes),
.enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_telecom_camera_modes[] = {
+static struct pmx_dev_mode pmx_telecom_camera_modes[] = {
{
.ids = CAML_LCDW_MODE | CAML_LCD_MODE,
.mask = PMX_MII_MASK,
@@ -256,14 +256,14 @@
},
};
-struct pmx_dev pmx_telecom_camera = {
+struct pmx_dev spear300_pmx_telecom_camera = {
.name = "telecom_camera",
.modes = pmx_telecom_camera_modes,
.mode_count = ARRAY_SIZE(pmx_telecom_camera_modes),
.enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_telecom_dac_modes[] = {
+static struct pmx_dev_mode pmx_telecom_dac_modes[] = {
{
.ids = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE
| CAMU_WLCD_MODE | CAML_LCD_MODE,
@@ -271,14 +271,14 @@
},
};
-struct pmx_dev pmx_telecom_dac = {
+struct pmx_dev spear300_pmx_telecom_dac = {
.name = "telecom_dac",
.modes = pmx_telecom_dac_modes,
.mode_count = ARRAY_SIZE(pmx_telecom_dac_modes),
.enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_telecom_i2s_modes[] = {
+static struct pmx_dev_mode pmx_telecom_i2s_modes[] = {
{
.ids = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE
| LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE |
@@ -288,14 +288,14 @@
},
};
-struct pmx_dev pmx_telecom_i2s = {
+struct pmx_dev spear300_pmx_telecom_i2s = {
.name = "telecom_i2s",
.modes = pmx_telecom_i2s_modes,
.mode_count = ARRAY_SIZE(pmx_telecom_i2s_modes),
.enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_telecom_boot_pins_modes[] = {
+static struct pmx_dev_mode pmx_telecom_boot_pins_modes[] = {
{
.ids = NAND_MODE | NOR_MODE,
.mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK |
@@ -303,14 +303,14 @@
},
};
-struct pmx_dev pmx_telecom_boot_pins = {
+struct pmx_dev spear300_pmx_telecom_boot_pins = {
.name = "telecom_boot_pins",
.modes = pmx_telecom_boot_pins_modes,
.mode_count = ARRAY_SIZE(pmx_telecom_boot_pins_modes),
.enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_telecom_sdhci_4bit_modes[] = {
+static struct pmx_dev_mode pmx_telecom_sdhci_4bit_modes[] = {
{
.ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
@@ -323,14 +323,14 @@
},
};
-struct pmx_dev pmx_telecom_sdhci_4bit = {
+struct pmx_dev spear300_pmx_telecom_sdhci_4bit = {
.name = "telecom_sdhci_4bit",
.modes = pmx_telecom_sdhci_4bit_modes,
.mode_count = ARRAY_SIZE(pmx_telecom_sdhci_4bit_modes),
.enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_telecom_sdhci_8bit_modes[] = {
+static struct pmx_dev_mode pmx_telecom_sdhci_8bit_modes[] = {
{
.ids = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE |
HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE |
@@ -342,14 +342,14 @@
},
};
-struct pmx_dev pmx_telecom_sdhci_8bit = {
+struct pmx_dev spear300_pmx_telecom_sdhci_8bit = {
.name = "telecom_sdhci_8bit",
.modes = pmx_telecom_sdhci_8bit_modes,
.mode_count = ARRAY_SIZE(pmx_telecom_sdhci_8bit_modes),
.enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_gpio1_modes[] = {
+static struct pmx_dev_mode pmx_gpio1_modes[] = {
{
.ids = PHOTO_FRAME_MODE,
.mask = PMX_UART0_MODEM_MASK | PMX_TIMER_1_2_MASK |
@@ -357,7 +357,7 @@
},
};
-struct pmx_dev pmx_gpio1 = {
+struct pmx_dev spear300_pmx_gpio1 = {
.name = "arm gpio1",
.modes = pmx_gpio1_modes,
.mode_count = ARRAY_SIZE(pmx_gpio1_modes),
@@ -365,60 +365,60 @@
};
/* pmx driver structure */
-struct pmx_driver pmx_driver = {
+static struct pmx_driver pmx_driver = {
.mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x0000000f},
.mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
};
/* spear3xx shared irq */
-struct shirq_dev_config shirq_ras1_config[] = {
+static struct shirq_dev_config shirq_ras1_config[] = {
{
- .virq = VIRQ_IT_PERS_S,
- .enb_mask = IT_PERS_S_IRQ_MASK,
- .status_mask = IT_PERS_S_IRQ_MASK,
+ .virq = SPEAR300_VIRQ_IT_PERS_S,
+ .enb_mask = SPEAR300_IT_PERS_S_IRQ_MASK,
+ .status_mask = SPEAR300_IT_PERS_S_IRQ_MASK,
}, {
- .virq = VIRQ_IT_CHANGE_S,
- .enb_mask = IT_CHANGE_S_IRQ_MASK,
- .status_mask = IT_CHANGE_S_IRQ_MASK,
+ .virq = SPEAR300_VIRQ_IT_CHANGE_S,
+ .enb_mask = SPEAR300_IT_CHANGE_S_IRQ_MASK,
+ .status_mask = SPEAR300_IT_CHANGE_S_IRQ_MASK,
}, {
- .virq = VIRQ_I2S,
- .enb_mask = I2S_IRQ_MASK,
- .status_mask = I2S_IRQ_MASK,
+ .virq = SPEAR300_VIRQ_I2S,
+ .enb_mask = SPEAR300_I2S_IRQ_MASK,
+ .status_mask = SPEAR300_I2S_IRQ_MASK,
}, {
- .virq = VIRQ_TDM,
- .enb_mask = TDM_IRQ_MASK,
- .status_mask = TDM_IRQ_MASK,
+ .virq = SPEAR300_VIRQ_TDM,
+ .enb_mask = SPEAR300_TDM_IRQ_MASK,
+ .status_mask = SPEAR300_TDM_IRQ_MASK,
}, {
- .virq = VIRQ_CAMERA_L,
- .enb_mask = CAMERA_L_IRQ_MASK,
- .status_mask = CAMERA_L_IRQ_MASK,
+ .virq = SPEAR300_VIRQ_CAMERA_L,
+ .enb_mask = SPEAR300_CAMERA_L_IRQ_MASK,
+ .status_mask = SPEAR300_CAMERA_L_IRQ_MASK,
}, {
- .virq = VIRQ_CAMERA_F,
- .enb_mask = CAMERA_F_IRQ_MASK,
- .status_mask = CAMERA_F_IRQ_MASK,
+ .virq = SPEAR300_VIRQ_CAMERA_F,
+ .enb_mask = SPEAR300_CAMERA_F_IRQ_MASK,
+ .status_mask = SPEAR300_CAMERA_F_IRQ_MASK,
}, {
- .virq = VIRQ_CAMERA_V,
- .enb_mask = CAMERA_V_IRQ_MASK,
- .status_mask = CAMERA_V_IRQ_MASK,
+ .virq = SPEAR300_VIRQ_CAMERA_V,
+ .enb_mask = SPEAR300_CAMERA_V_IRQ_MASK,
+ .status_mask = SPEAR300_CAMERA_V_IRQ_MASK,
}, {
- .virq = VIRQ_KEYBOARD,
- .enb_mask = KEYBOARD_IRQ_MASK,
- .status_mask = KEYBOARD_IRQ_MASK,
+ .virq = SPEAR300_VIRQ_KEYBOARD,
+ .enb_mask = SPEAR300_KEYBOARD_IRQ_MASK,
+ .status_mask = SPEAR300_KEYBOARD_IRQ_MASK,
}, {
- .virq = VIRQ_GPIO1,
- .enb_mask = GPIO1_IRQ_MASK,
- .status_mask = GPIO1_IRQ_MASK,
+ .virq = SPEAR300_VIRQ_GPIO1,
+ .enb_mask = SPEAR300_GPIO1_IRQ_MASK,
+ .status_mask = SPEAR300_GPIO1_IRQ_MASK,
},
};
-struct spear_shirq shirq_ras1 = {
- .irq = IRQ_GEN_RAS_1,
+static struct spear_shirq shirq_ras1 = {
+ .irq = SPEAR3XX_IRQ_GEN_RAS_1,
.dev_config = shirq_ras1_config,
.dev_count = ARRAY_SIZE(shirq_ras1_config),
.regs = {
- .enb_reg = INT_ENB_MASK_REG,
- .status_reg = INT_STS_MASK_REG,
- .status_reg_mask = SHIRQ_RAS1_MASK,
+ .enb_reg = SPEAR300_INT_ENB_MASK_REG,
+ .status_reg = SPEAR300_INT_STS_MASK_REG,
+ .status_reg_mask = SPEAR300_SHIRQ_RAS1_MASK,
.clear_reg = -1,
},
};
@@ -427,10 +427,10 @@
/* arm gpio1 device registration */
static struct pl061_platform_data gpio1_plat_data = {
.gpio_base = 8,
- .irq_base = SPEAR_GPIO1_INT_BASE,
+ .irq_base = SPEAR300_GPIO1_INT_BASE,
};
-struct amba_device gpio1_device = {
+struct amba_device spear300_gpio1_device = {
.dev = {
.init_name = "gpio1",
.platform_data = &gpio1_plat_data,
@@ -440,11 +440,12 @@
.end = SPEAR300_GPIO_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
- .irq = {VIRQ_GPIO1, NO_IRQ},
+ .irq = {SPEAR300_VIRQ_GPIO1, NO_IRQ},
};
/* spear300 routines */
-void __init spear300_init(void)
+void __init spear300_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
+ u8 pmx_dev_count)
{
int ret = 0;
@@ -460,6 +461,10 @@
}
/* pmx initialization */
+ pmx_driver.mode = pmx_mode;
+ pmx_driver.devs = pmx_devs;
+ pmx_driver.devs_count = pmx_dev_count;
+
pmx_driver.base = ioremap(SPEAR300_SOC_CONFIG_BASE, SZ_4K);
if (pmx_driver.base) {
ret = pmx_register(&pmx_driver);
diff --git a/arch/arm/mach-spear3xx/spear300_evb.c b/arch/arm/mach-spear3xx/spear300_evb.c
index 42d2253..69006f6 100644
--- a/arch/arm/mach-spear3xx/spear300_evb.c
+++ b/arch/arm/mach-spear3xx/spear300_evb.c
@@ -19,26 +19,26 @@
/* padmux devices to enable */
static struct pmx_dev *pmx_devs[] = {
/* spear3xx specific devices */
- &pmx_i2c,
- &pmx_ssp_cs,
- &pmx_ssp,
- &pmx_mii,
- &pmx_uart0,
+ &spear3xx_pmx_i2c,
+ &spear3xx_pmx_ssp_cs,
+ &spear3xx_pmx_ssp,
+ &spear3xx_pmx_mii,
+ &spear3xx_pmx_uart0,
/* spear300 specific devices */
- &pmx_fsmc_2_chips,
- &pmx_clcd,
- &pmx_telecom_sdhci_4bit,
- &pmx_gpio1,
+ &spear300_pmx_fsmc_2_chips,
+ &spear300_pmx_clcd,
+ &spear300_pmx_telecom_sdhci_4bit,
+ &spear300_pmx_gpio1,
};
static struct amba_device *amba_devs[] __initdata = {
/* spear3xx specific devices */
- &gpio_device,
- &uart_device,
+ &spear3xx_gpio_device,
+ &spear3xx_uart_device,
/* spear300 specific devices */
- &gpio1_device,
+ &spear300_gpio1_device,
};
static struct platform_device *plat_devs[] __initdata = {
@@ -51,13 +51,9 @@
{
unsigned int i;
- /* padmux initialization, must be done before spear300_init */
- pmx_driver.mode = &photo_frame_mode;
- pmx_driver.devs = pmx_devs;
- pmx_driver.devs_count = ARRAY_SIZE(pmx_devs);
-
/* call spear300 machine init function */
- spear300_init();
+ spear300_init(&spear300_photo_frame_mode, pmx_devs,
+ ARRAY_SIZE(pmx_devs));
/* Add Platform Devices */
platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
diff --git a/arch/arm/mach-spear3xx/spear310.c b/arch/arm/mach-spear3xx/spear310.c
index 5c0a67b..9004cf9 100644
--- a/arch/arm/mach-spear3xx/spear310.c
+++ b/arch/arm/mach-spear3xx/spear310.c
@@ -22,112 +22,112 @@
#define PAD_MUX_CONFIG_REG 0x08
/* devices */
-struct pmx_dev_mode pmx_emi_cs_0_1_4_5_modes[] = {
+static struct pmx_dev_mode pmx_emi_cs_0_1_4_5_modes[] = {
{
.ids = 0x00,
.mask = PMX_TIMER_3_4_MASK,
},
};
-struct pmx_dev pmx_emi_cs_0_1_4_5 = {
+struct pmx_dev spear310_pmx_emi_cs_0_1_4_5 = {
.name = "emi_cs_0_1_4_5",
.modes = pmx_emi_cs_0_1_4_5_modes,
.mode_count = ARRAY_SIZE(pmx_emi_cs_0_1_4_5_modes),
.enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_emi_cs_2_3_modes[] = {
+static struct pmx_dev_mode pmx_emi_cs_2_3_modes[] = {
{
.ids = 0x00,
.mask = PMX_TIMER_1_2_MASK,
},
};
-struct pmx_dev pmx_emi_cs_2_3 = {
+struct pmx_dev spear310_pmx_emi_cs_2_3 = {
.name = "emi_cs_2_3",
.modes = pmx_emi_cs_2_3_modes,
.mode_count = ARRAY_SIZE(pmx_emi_cs_2_3_modes),
.enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_uart1_modes[] = {
+static struct pmx_dev_mode pmx_uart1_modes[] = {
{
.ids = 0x00,
.mask = PMX_FIRDA_MASK,
},
};
-struct pmx_dev pmx_uart1 = {
+struct pmx_dev spear310_pmx_uart1 = {
.name = "uart1",
.modes = pmx_uart1_modes,
.mode_count = ARRAY_SIZE(pmx_uart1_modes),
.enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_uart2_modes[] = {
+static struct pmx_dev_mode pmx_uart2_modes[] = {
{
.ids = 0x00,
.mask = PMX_TIMER_1_2_MASK,
},
};
-struct pmx_dev pmx_uart2 = {
+struct pmx_dev spear310_pmx_uart2 = {
.name = "uart2",
.modes = pmx_uart2_modes,
.mode_count = ARRAY_SIZE(pmx_uart2_modes),
.enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_uart3_4_5_modes[] = {
+static struct pmx_dev_mode pmx_uart3_4_5_modes[] = {
{
.ids = 0x00,
.mask = PMX_UART0_MODEM_MASK,
},
};
-struct pmx_dev pmx_uart3_4_5 = {
+struct pmx_dev spear310_pmx_uart3_4_5 = {
.name = "uart3_4_5",
.modes = pmx_uart3_4_5_modes,
.mode_count = ARRAY_SIZE(pmx_uart3_4_5_modes),
.enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_fsmc_modes[] = {
+static struct pmx_dev_mode pmx_fsmc_modes[] = {
{
.ids = 0x00,
.mask = PMX_SSP_CS_MASK,
},
};
-struct pmx_dev pmx_fsmc = {
+struct pmx_dev spear310_pmx_fsmc = {
.name = "fsmc",
.modes = pmx_fsmc_modes,
.mode_count = ARRAY_SIZE(pmx_fsmc_modes),
.enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_rs485_0_1_modes[] = {
+static struct pmx_dev_mode pmx_rs485_0_1_modes[] = {
{
.ids = 0x00,
.mask = PMX_MII_MASK,
},
};
-struct pmx_dev pmx_rs485_0_1 = {
+struct pmx_dev spear310_pmx_rs485_0_1 = {
.name = "rs485_0_1",
.modes = pmx_rs485_0_1_modes,
.mode_count = ARRAY_SIZE(pmx_rs485_0_1_modes),
.enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_tdm0_modes[] = {
+static struct pmx_dev_mode pmx_tdm0_modes[] = {
{
.ids = 0x00,
.mask = PMX_MII_MASK,
},
};
-struct pmx_dev pmx_tdm0 = {
+struct pmx_dev spear310_pmx_tdm0 = {
.name = "tdm0",
.modes = pmx_tdm0_modes,
.mode_count = ARRAY_SIZE(pmx_tdm0_modes),
@@ -135,122 +135,122 @@
};
/* pmx driver structure */
-struct pmx_driver pmx_driver = {
+static struct pmx_driver pmx_driver = {
.mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
};
/* spear3xx shared irq */
-struct shirq_dev_config shirq_ras1_config[] = {
+static struct shirq_dev_config shirq_ras1_config[] = {
{
- .virq = VIRQ_SMII0,
- .status_mask = SMII0_IRQ_MASK,
+ .virq = SPEAR310_VIRQ_SMII0,
+ .status_mask = SPEAR310_SMII0_IRQ_MASK,
}, {
- .virq = VIRQ_SMII1,
- .status_mask = SMII1_IRQ_MASK,
+ .virq = SPEAR310_VIRQ_SMII1,
+ .status_mask = SPEAR310_SMII1_IRQ_MASK,
}, {
- .virq = VIRQ_SMII2,
- .status_mask = SMII2_IRQ_MASK,
+ .virq = SPEAR310_VIRQ_SMII2,
+ .status_mask = SPEAR310_SMII2_IRQ_MASK,
}, {
- .virq = VIRQ_SMII3,
- .status_mask = SMII3_IRQ_MASK,
+ .virq = SPEAR310_VIRQ_SMII3,
+ .status_mask = SPEAR310_SMII3_IRQ_MASK,
}, {
- .virq = VIRQ_WAKEUP_SMII0,
- .status_mask = WAKEUP_SMII0_IRQ_MASK,
+ .virq = SPEAR310_VIRQ_WAKEUP_SMII0,
+ .status_mask = SPEAR310_WAKEUP_SMII0_IRQ_MASK,
}, {
- .virq = VIRQ_WAKEUP_SMII1,
- .status_mask = WAKEUP_SMII1_IRQ_MASK,
+ .virq = SPEAR310_VIRQ_WAKEUP_SMII1,
+ .status_mask = SPEAR310_WAKEUP_SMII1_IRQ_MASK,
}, {
- .virq = VIRQ_WAKEUP_SMII2,
- .status_mask = WAKEUP_SMII2_IRQ_MASK,
+ .virq = SPEAR310_VIRQ_WAKEUP_SMII2,
+ .status_mask = SPEAR310_WAKEUP_SMII2_IRQ_MASK,
}, {
- .virq = VIRQ_WAKEUP_SMII3,
- .status_mask = WAKEUP_SMII3_IRQ_MASK,
+ .virq = SPEAR310_VIRQ_WAKEUP_SMII3,
+ .status_mask = SPEAR310_WAKEUP_SMII3_IRQ_MASK,
},
};
-struct spear_shirq shirq_ras1 = {
- .irq = IRQ_GEN_RAS_1,
+static struct spear_shirq shirq_ras1 = {
+ .irq = SPEAR3XX_IRQ_GEN_RAS_1,
.dev_config = shirq_ras1_config,
.dev_count = ARRAY_SIZE(shirq_ras1_config),
.regs = {
.enb_reg = -1,
- .status_reg = INT_STS_MASK_REG,
- .status_reg_mask = SHIRQ_RAS1_MASK,
+ .status_reg = SPEAR310_INT_STS_MASK_REG,
+ .status_reg_mask = SPEAR310_SHIRQ_RAS1_MASK,
.clear_reg = -1,
},
};
-struct shirq_dev_config shirq_ras2_config[] = {
+static struct shirq_dev_config shirq_ras2_config[] = {
{
- .virq = VIRQ_UART1,
- .status_mask = UART1_IRQ_MASK,
+ .virq = SPEAR310_VIRQ_UART1,
+ .status_mask = SPEAR310_UART1_IRQ_MASK,
}, {
- .virq = VIRQ_UART2,
- .status_mask = UART2_IRQ_MASK,
+ .virq = SPEAR310_VIRQ_UART2,
+ .status_mask = SPEAR310_UART2_IRQ_MASK,
}, {
- .virq = VIRQ_UART3,
- .status_mask = UART3_IRQ_MASK,
+ .virq = SPEAR310_VIRQ_UART3,
+ .status_mask = SPEAR310_UART3_IRQ_MASK,
}, {
- .virq = VIRQ_UART4,
- .status_mask = UART4_IRQ_MASK,
+ .virq = SPEAR310_VIRQ_UART4,
+ .status_mask = SPEAR310_UART4_IRQ_MASK,
}, {
- .virq = VIRQ_UART5,
- .status_mask = UART5_IRQ_MASK,
+ .virq = SPEAR310_VIRQ_UART5,
+ .status_mask = SPEAR310_UART5_IRQ_MASK,
},
};
-struct spear_shirq shirq_ras2 = {
- .irq = IRQ_GEN_RAS_2,
+static struct spear_shirq shirq_ras2 = {
+ .irq = SPEAR3XX_IRQ_GEN_RAS_2,
.dev_config = shirq_ras2_config,
.dev_count = ARRAY_SIZE(shirq_ras2_config),
.regs = {
.enb_reg = -1,
- .status_reg = INT_STS_MASK_REG,
- .status_reg_mask = SHIRQ_RAS2_MASK,
+ .status_reg = SPEAR310_INT_STS_MASK_REG,
+ .status_reg_mask = SPEAR310_SHIRQ_RAS2_MASK,
.clear_reg = -1,
},
};
-struct shirq_dev_config shirq_ras3_config[] = {
+static struct shirq_dev_config shirq_ras3_config[] = {
{
- .virq = VIRQ_EMI,
- .status_mask = EMI_IRQ_MASK,
+ .virq = SPEAR310_VIRQ_EMI,
+ .status_mask = SPEAR310_EMI_IRQ_MASK,
},
};
-struct spear_shirq shirq_ras3 = {
- .irq = IRQ_GEN_RAS_3,
+static struct spear_shirq shirq_ras3 = {
+ .irq = SPEAR3XX_IRQ_GEN_RAS_3,
.dev_config = shirq_ras3_config,
.dev_count = ARRAY_SIZE(shirq_ras3_config),
.regs = {
.enb_reg = -1,
- .status_reg = INT_STS_MASK_REG,
- .status_reg_mask = SHIRQ_RAS3_MASK,
+ .status_reg = SPEAR310_INT_STS_MASK_REG,
+ .status_reg_mask = SPEAR310_SHIRQ_RAS3_MASK,
.clear_reg = -1,
},
};
-struct shirq_dev_config shirq_intrcomm_ras_config[] = {
+static struct shirq_dev_config shirq_intrcomm_ras_config[] = {
{
- .virq = VIRQ_TDM_HDLC,
- .status_mask = TDM_HDLC_IRQ_MASK,
+ .virq = SPEAR310_VIRQ_TDM_HDLC,
+ .status_mask = SPEAR310_TDM_HDLC_IRQ_MASK,
}, {
- .virq = VIRQ_RS485_0,
- .status_mask = RS485_0_IRQ_MASK,
+ .virq = SPEAR310_VIRQ_RS485_0,
+ .status_mask = SPEAR310_RS485_0_IRQ_MASK,
}, {
- .virq = VIRQ_RS485_1,
- .status_mask = RS485_1_IRQ_MASK,
+ .virq = SPEAR310_VIRQ_RS485_1,
+ .status_mask = SPEAR310_RS485_1_IRQ_MASK,
},
};
-struct spear_shirq shirq_intrcomm_ras = {
- .irq = IRQ_INTRCOMM_RAS_ARM,
+static struct spear_shirq shirq_intrcomm_ras = {
+ .irq = SPEAR3XX_IRQ_INTRCOMM_RAS_ARM,
.dev_config = shirq_intrcomm_ras_config,
.dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config),
.regs = {
.enb_reg = -1,
- .status_reg = INT_STS_MASK_REG,
- .status_reg_mask = SHIRQ_INTRCOMM_RAS_MASK,
+ .status_reg = SPEAR310_INT_STS_MASK_REG,
+ .status_reg_mask = SPEAR310_SHIRQ_INTRCOMM_RAS_MASK,
.clear_reg = -1,
},
};
@@ -258,7 +258,8 @@
/* Add spear310 specific devices here */
/* spear310 routines */
-void __init spear310_init(void)
+void __init spear310_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
+ u8 pmx_dev_count)
{
void __iomem *base;
int ret = 0;
@@ -296,6 +297,10 @@
/* pmx initialization */
pmx_driver.base = base;
+ pmx_driver.mode = pmx_mode;
+ pmx_driver.devs = pmx_devs;
+ pmx_driver.devs_count = pmx_dev_count;
+
ret = pmx_register(&pmx_driver);
if (ret)
printk(KERN_ERR "padmux: registeration failed. err no: %d\n",
diff --git a/arch/arm/mach-spear3xx/spear310_evb.c b/arch/arm/mach-spear3xx/spear310_evb.c
index 2d7f333..c8684ce 100644
--- a/arch/arm/mach-spear3xx/spear310_evb.c
+++ b/arch/arm/mach-spear3xx/spear310_evb.c
@@ -19,31 +19,31 @@
/* padmux devices to enable */
static struct pmx_dev *pmx_devs[] = {
/* spear3xx specific devices */
- &pmx_i2c,
- &pmx_ssp,
- &pmx_gpio_pin0,
- &pmx_gpio_pin1,
- &pmx_gpio_pin2,
- &pmx_gpio_pin3,
- &pmx_gpio_pin4,
- &pmx_gpio_pin5,
- &pmx_uart0,
+ &spear3xx_pmx_i2c,
+ &spear3xx_pmx_ssp,
+ &spear3xx_pmx_gpio_pin0,
+ &spear3xx_pmx_gpio_pin1,
+ &spear3xx_pmx_gpio_pin2,
+ &spear3xx_pmx_gpio_pin3,
+ &spear3xx_pmx_gpio_pin4,
+ &spear3xx_pmx_gpio_pin5,
+ &spear3xx_pmx_uart0,
/* spear310 specific devices */
- &pmx_emi_cs_0_1_4_5,
- &pmx_emi_cs_2_3,
- &pmx_uart1,
- &pmx_uart2,
- &pmx_uart3_4_5,
- &pmx_fsmc,
- &pmx_rs485_0_1,
- &pmx_tdm0,
+ &spear310_pmx_emi_cs_0_1_4_5,
+ &spear310_pmx_emi_cs_2_3,
+ &spear310_pmx_uart1,
+ &spear310_pmx_uart2,
+ &spear310_pmx_uart3_4_5,
+ &spear310_pmx_fsmc,
+ &spear310_pmx_rs485_0_1,
+ &spear310_pmx_tdm0,
};
static struct amba_device *amba_devs[] __initdata = {
/* spear3xx specific devices */
- &gpio_device,
- &uart_device,
+ &spear3xx_gpio_device,
+ &spear3xx_uart_device,
/* spear310 specific devices */
};
@@ -58,13 +58,8 @@
{
unsigned int i;
- /* padmux initialization, must be done before spear310_init */
- pmx_driver.mode = NULL;
- pmx_driver.devs = pmx_devs;
- pmx_driver.devs_count = ARRAY_SIZE(pmx_devs);
-
/* call spear310 machine init function */
- spear310_init();
+ spear310_init(NULL, pmx_devs, ARRAY_SIZE(pmx_devs));
/* Add Platform Devices */
platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
diff --git a/arch/arm/mach-spear3xx/spear320.c b/arch/arm/mach-spear3xx/spear320.c
index 741c1f4..ee29bef 100644
--- a/arch/arm/mach-spear3xx/spear320.c
+++ b/arch/arm/mach-spear3xx/spear320.c
@@ -29,88 +29,88 @@
#define SMALL_PRINTERS_MODE (1 << 3)
#define ALL_MODES 0xF
-struct pmx_mode auto_net_smii_mode = {
+struct pmx_mode spear320_auto_net_smii_mode = {
.id = AUTO_NET_SMII_MODE,
.name = "Automation Networking SMII Mode",
.mask = 0x00,
};
-struct pmx_mode auto_net_mii_mode = {
+struct pmx_mode spear320_auto_net_mii_mode = {
.id = AUTO_NET_MII_MODE,
.name = "Automation Networking MII Mode",
.mask = 0x01,
};
-struct pmx_mode auto_exp_mode = {
+struct pmx_mode spear320_auto_exp_mode = {
.id = AUTO_EXP_MODE,
.name = "Automation Expanded Mode",
.mask = 0x02,
};
-struct pmx_mode small_printers_mode = {
+struct pmx_mode spear320_small_printers_mode = {
.id = SMALL_PRINTERS_MODE,
.name = "Small Printers Mode",
.mask = 0x03,
};
/* devices */
-struct pmx_dev_mode pmx_clcd_modes[] = {
+static struct pmx_dev_mode pmx_clcd_modes[] = {
{
.ids = AUTO_NET_SMII_MODE,
.mask = 0x0,
},
};
-struct pmx_dev pmx_clcd = {
+struct pmx_dev spear320_pmx_clcd = {
.name = "clcd",
.modes = pmx_clcd_modes,
.mode_count = ARRAY_SIZE(pmx_clcd_modes),
.enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_emi_modes[] = {
+static struct pmx_dev_mode pmx_emi_modes[] = {
{
.ids = AUTO_EXP_MODE,
.mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK,
},
};
-struct pmx_dev pmx_emi = {
+struct pmx_dev spear320_pmx_emi = {
.name = "emi",
.modes = pmx_emi_modes,
.mode_count = ARRAY_SIZE(pmx_emi_modes),
.enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_fsmc_modes[] = {
+static struct pmx_dev_mode pmx_fsmc_modes[] = {
{
.ids = ALL_MODES,
.mask = 0x0,
},
};
-struct pmx_dev pmx_fsmc = {
+struct pmx_dev spear320_pmx_fsmc = {
.name = "fsmc",
.modes = pmx_fsmc_modes,
.mode_count = ARRAY_SIZE(pmx_fsmc_modes),
.enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_spp_modes[] = {
+static struct pmx_dev_mode pmx_spp_modes[] = {
{
.ids = SMALL_PRINTERS_MODE,
.mask = 0x0,
},
};
-struct pmx_dev pmx_spp = {
+struct pmx_dev spear320_pmx_spp = {
.name = "spp",
.modes = pmx_spp_modes,
.mode_count = ARRAY_SIZE(pmx_spp_modes),
.enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_sdhci_modes[] = {
+static struct pmx_dev_mode pmx_sdhci_modes[] = {
{
.ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE |
SMALL_PRINTERS_MODE,
@@ -118,42 +118,42 @@
},
};
-struct pmx_dev pmx_sdhci = {
+struct pmx_dev spear320_pmx_sdhci = {
.name = "sdhci",
.modes = pmx_sdhci_modes,
.mode_count = ARRAY_SIZE(pmx_sdhci_modes),
.enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_i2s_modes[] = {
+static struct pmx_dev_mode pmx_i2s_modes[] = {
{
.ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
.mask = PMX_UART0_MODEM_MASK,
},
};
-struct pmx_dev pmx_i2s = {
+struct pmx_dev spear320_pmx_i2s = {
.name = "i2s",
.modes = pmx_i2s_modes,
.mode_count = ARRAY_SIZE(pmx_i2s_modes),
.enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_uart1_modes[] = {
+static struct pmx_dev_mode pmx_uart1_modes[] = {
{
.ids = ALL_MODES,
.mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK,
},
};
-struct pmx_dev pmx_uart1 = {
+struct pmx_dev spear320_pmx_uart1 = {
.name = "uart1",
.modes = pmx_uart1_modes,
.mode_count = ARRAY_SIZE(pmx_uart1_modes),
.enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_uart1_modem_modes[] = {
+static struct pmx_dev_mode pmx_uart1_modem_modes[] = {
{
.ids = AUTO_EXP_MODE,
.mask = PMX_TIMER_1_2_MASK | PMX_TIMER_3_4_MASK |
@@ -165,42 +165,42 @@
},
};
-struct pmx_dev pmx_uart1_modem = {
+struct pmx_dev spear320_pmx_uart1_modem = {
.name = "uart1_modem",
.modes = pmx_uart1_modem_modes,
.mode_count = ARRAY_SIZE(pmx_uart1_modem_modes),
.enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_uart2_modes[] = {
+static struct pmx_dev_mode pmx_uart2_modes[] = {
{
.ids = ALL_MODES,
.mask = PMX_FIRDA_MASK,
},
};
-struct pmx_dev pmx_uart2 = {
+struct pmx_dev spear320_pmx_uart2 = {
.name = "uart2",
.modes = pmx_uart2_modes,
.mode_count = ARRAY_SIZE(pmx_uart2_modes),
.enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_touchscreen_modes[] = {
+static struct pmx_dev_mode pmx_touchscreen_modes[] = {
{
.ids = AUTO_NET_SMII_MODE,
.mask = PMX_SSP_CS_MASK,
},
};
-struct pmx_dev pmx_touchscreen = {
+struct pmx_dev spear320_pmx_touchscreen = {
.name = "touchscreen",
.modes = pmx_touchscreen_modes,
.mode_count = ARRAY_SIZE(pmx_touchscreen_modes),
.enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_can_modes[] = {
+static struct pmx_dev_mode pmx_can_modes[] = {
{
.ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE,
.mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK |
@@ -208,28 +208,28 @@
},
};
-struct pmx_dev pmx_can = {
+struct pmx_dev spear320_pmx_can = {
.name = "can",
.modes = pmx_can_modes,
.mode_count = ARRAY_SIZE(pmx_can_modes),
.enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_sdhci_led_modes[] = {
+static struct pmx_dev_mode pmx_sdhci_led_modes[] = {
{
.ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
.mask = PMX_SSP_CS_MASK,
},
};
-struct pmx_dev pmx_sdhci_led = {
+struct pmx_dev spear320_pmx_sdhci_led = {
.name = "sdhci_led",
.modes = pmx_sdhci_led_modes,
.mode_count = ARRAY_SIZE(pmx_sdhci_led_modes),
.enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_pwm0_modes[] = {
+static struct pmx_dev_mode pmx_pwm0_modes[] = {
{
.ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
.mask = PMX_UART0_MODEM_MASK,
@@ -239,14 +239,14 @@
},
};
-struct pmx_dev pmx_pwm0 = {
+struct pmx_dev spear320_pmx_pwm0 = {
.name = "pwm0",
.modes = pmx_pwm0_modes,
.mode_count = ARRAY_SIZE(pmx_pwm0_modes),
.enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_pwm1_modes[] = {
+static struct pmx_dev_mode pmx_pwm1_modes[] = {
{
.ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
.mask = PMX_UART0_MODEM_MASK,
@@ -256,14 +256,14 @@
},
};
-struct pmx_dev pmx_pwm1 = {
+struct pmx_dev spear320_pmx_pwm1 = {
.name = "pwm1",
.modes = pmx_pwm1_modes,
.mode_count = ARRAY_SIZE(pmx_pwm1_modes),
.enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_pwm2_modes[] = {
+static struct pmx_dev_mode pmx_pwm2_modes[] = {
{
.ids = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE,
.mask = PMX_SSP_CS_MASK,
@@ -273,105 +273,105 @@
},
};
-struct pmx_dev pmx_pwm2 = {
+struct pmx_dev spear320_pmx_pwm2 = {
.name = "pwm2",
.modes = pmx_pwm2_modes,
.mode_count = ARRAY_SIZE(pmx_pwm2_modes),
.enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_pwm3_modes[] = {
+static struct pmx_dev_mode pmx_pwm3_modes[] = {
{
.ids = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
.mask = PMX_MII_MASK,
},
};
-struct pmx_dev pmx_pwm3 = {
+struct pmx_dev spear320_pmx_pwm3 = {
.name = "pwm3",
.modes = pmx_pwm3_modes,
.mode_count = ARRAY_SIZE(pmx_pwm3_modes),
.enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_ssp1_modes[] = {
+static struct pmx_dev_mode pmx_ssp1_modes[] = {
{
.ids = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE,
.mask = PMX_MII_MASK,
},
};
-struct pmx_dev pmx_ssp1 = {
+struct pmx_dev spear320_pmx_ssp1 = {
.name = "ssp1",
.modes = pmx_ssp1_modes,
.mode_count = ARRAY_SIZE(pmx_ssp1_modes),
.enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_ssp2_modes[] = {
+static struct pmx_dev_mode pmx_ssp2_modes[] = {
{
.ids = AUTO_NET_SMII_MODE,
.mask = PMX_MII_MASK,
},
};
-struct pmx_dev pmx_ssp2 = {
+struct pmx_dev spear320_pmx_ssp2 = {
.name = "ssp2",
.modes = pmx_ssp2_modes,
.mode_count = ARRAY_SIZE(pmx_ssp2_modes),
.enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_mii1_modes[] = {
+static struct pmx_dev_mode pmx_mii1_modes[] = {
{
.ids = AUTO_NET_MII_MODE,
.mask = 0x0,
},
};
-struct pmx_dev pmx_mii1 = {
+struct pmx_dev spear320_pmx_mii1 = {
.name = "mii1",
.modes = pmx_mii1_modes,
.mode_count = ARRAY_SIZE(pmx_mii1_modes),
.enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_smii0_modes[] = {
+static struct pmx_dev_mode pmx_smii0_modes[] = {
{
.ids = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | SMALL_PRINTERS_MODE,
.mask = PMX_MII_MASK,
},
};
-struct pmx_dev pmx_smii0 = {
+struct pmx_dev spear320_pmx_smii0 = {
.name = "smii0",
.modes = pmx_smii0_modes,
.mode_count = ARRAY_SIZE(pmx_smii0_modes),
.enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_smii1_modes[] = {
+static struct pmx_dev_mode pmx_smii1_modes[] = {
{
.ids = AUTO_NET_SMII_MODE | SMALL_PRINTERS_MODE,
.mask = PMX_MII_MASK,
},
};
-struct pmx_dev pmx_smii1 = {
+struct pmx_dev spear320_pmx_smii1 = {
.name = "smii1",
.modes = pmx_smii1_modes,
.mode_count = ARRAY_SIZE(pmx_smii1_modes),
.enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_i2c1_modes[] = {
+static struct pmx_dev_mode pmx_i2c1_modes[] = {
{
.ids = AUTO_EXP_MODE,
.mask = 0x0,
},
};
-struct pmx_dev pmx_i2c1 = {
+struct pmx_dev spear320_pmx_i2c1 = {
.name = "i2c1",
.modes = pmx_i2c1_modes,
.mode_count = ARRAY_SIZE(pmx_i2c1_modes),
@@ -379,131 +379,131 @@
};
/* pmx driver structure */
-struct pmx_driver pmx_driver = {
+static struct pmx_driver pmx_driver = {
.mode_reg = {.offset = MODE_CONFIG_REG, .mask = 0x00000007},
.mux_reg = {.offset = PAD_MUX_CONFIG_REG, .mask = 0x00007fff},
};
/* spear3xx shared irq */
-struct shirq_dev_config shirq_ras1_config[] = {
+static struct shirq_dev_config shirq_ras1_config[] = {
{
- .virq = VIRQ_EMI,
- .status_mask = EMI_IRQ_MASK,
- .clear_mask = EMI_IRQ_MASK,
+ .virq = SPEAR320_VIRQ_EMI,
+ .status_mask = SPEAR320_EMI_IRQ_MASK,
+ .clear_mask = SPEAR320_EMI_IRQ_MASK,
}, {
- .virq = VIRQ_CLCD,
- .status_mask = CLCD_IRQ_MASK,
- .clear_mask = CLCD_IRQ_MASK,
+ .virq = SPEAR320_VIRQ_CLCD,
+ .status_mask = SPEAR320_CLCD_IRQ_MASK,
+ .clear_mask = SPEAR320_CLCD_IRQ_MASK,
}, {
- .virq = VIRQ_SPP,
- .status_mask = SPP_IRQ_MASK,
- .clear_mask = SPP_IRQ_MASK,
+ .virq = SPEAR320_VIRQ_SPP,
+ .status_mask = SPEAR320_SPP_IRQ_MASK,
+ .clear_mask = SPEAR320_SPP_IRQ_MASK,
},
};
-struct spear_shirq shirq_ras1 = {
- .irq = IRQ_GEN_RAS_1,
+static struct spear_shirq shirq_ras1 = {
+ .irq = SPEAR3XX_IRQ_GEN_RAS_1,
.dev_config = shirq_ras1_config,
.dev_count = ARRAY_SIZE(shirq_ras1_config),
.regs = {
.enb_reg = -1,
- .status_reg = INT_STS_MASK_REG,
- .status_reg_mask = SHIRQ_RAS1_MASK,
- .clear_reg = INT_CLR_MASK_REG,
+ .status_reg = SPEAR320_INT_STS_MASK_REG,
+ .status_reg_mask = SPEAR320_SHIRQ_RAS1_MASK,
+ .clear_reg = SPEAR320_INT_CLR_MASK_REG,
.reset_to_clear = 1,
},
};
-struct shirq_dev_config shirq_ras3_config[] = {
+static struct shirq_dev_config shirq_ras3_config[] = {
{
- .virq = VIRQ_PLGPIO,
- .enb_mask = GPIO_IRQ_MASK,
- .status_mask = GPIO_IRQ_MASK,
- .clear_mask = GPIO_IRQ_MASK,
+ .virq = SPEAR320_VIRQ_PLGPIO,
+ .enb_mask = SPEAR320_GPIO_IRQ_MASK,
+ .status_mask = SPEAR320_GPIO_IRQ_MASK,
+ .clear_mask = SPEAR320_GPIO_IRQ_MASK,
}, {
- .virq = VIRQ_I2S_PLAY,
- .enb_mask = I2S_PLAY_IRQ_MASK,
- .status_mask = I2S_PLAY_IRQ_MASK,
- .clear_mask = I2S_PLAY_IRQ_MASK,
+ .virq = SPEAR320_VIRQ_I2S_PLAY,
+ .enb_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
+ .status_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
+ .clear_mask = SPEAR320_I2S_PLAY_IRQ_MASK,
}, {
- .virq = VIRQ_I2S_REC,
- .enb_mask = I2S_REC_IRQ_MASK,
- .status_mask = I2S_REC_IRQ_MASK,
- .clear_mask = I2S_REC_IRQ_MASK,
+ .virq = SPEAR320_VIRQ_I2S_REC,
+ .enb_mask = SPEAR320_I2S_REC_IRQ_MASK,
+ .status_mask = SPEAR320_I2S_REC_IRQ_MASK,
+ .clear_mask = SPEAR320_I2S_REC_IRQ_MASK,
},
};
-struct spear_shirq shirq_ras3 = {
- .irq = IRQ_GEN_RAS_3,
+static struct spear_shirq shirq_ras3 = {
+ .irq = SPEAR3XX_IRQ_GEN_RAS_3,
.dev_config = shirq_ras3_config,
.dev_count = ARRAY_SIZE(shirq_ras3_config),
.regs = {
- .enb_reg = INT_ENB_MASK_REG,
+ .enb_reg = SPEAR320_INT_ENB_MASK_REG,
.reset_to_enb = 1,
- .status_reg = INT_STS_MASK_REG,
- .status_reg_mask = SHIRQ_RAS3_MASK,
- .clear_reg = INT_CLR_MASK_REG,
+ .status_reg = SPEAR320_INT_STS_MASK_REG,
+ .status_reg_mask = SPEAR320_SHIRQ_RAS3_MASK,
+ .clear_reg = SPEAR320_INT_CLR_MASK_REG,
.reset_to_clear = 1,
},
};
-struct shirq_dev_config shirq_intrcomm_ras_config[] = {
+static struct shirq_dev_config shirq_intrcomm_ras_config[] = {
{
- .virq = VIRQ_CANU,
- .status_mask = CAN_U_IRQ_MASK,
- .clear_mask = CAN_U_IRQ_MASK,
+ .virq = SPEAR320_VIRQ_CANU,
+ .status_mask = SPEAR320_CAN_U_IRQ_MASK,
+ .clear_mask = SPEAR320_CAN_U_IRQ_MASK,
}, {
- .virq = VIRQ_CANL,
- .status_mask = CAN_L_IRQ_MASK,
- .clear_mask = CAN_L_IRQ_MASK,
+ .virq = SPEAR320_VIRQ_CANL,
+ .status_mask = SPEAR320_CAN_L_IRQ_MASK,
+ .clear_mask = SPEAR320_CAN_L_IRQ_MASK,
}, {
- .virq = VIRQ_UART1,
- .status_mask = UART1_IRQ_MASK,
- .clear_mask = UART1_IRQ_MASK,
+ .virq = SPEAR320_VIRQ_UART1,
+ .status_mask = SPEAR320_UART1_IRQ_MASK,
+ .clear_mask = SPEAR320_UART1_IRQ_MASK,
}, {
- .virq = VIRQ_UART2,
- .status_mask = UART2_IRQ_MASK,
- .clear_mask = UART2_IRQ_MASK,
+ .virq = SPEAR320_VIRQ_UART2,
+ .status_mask = SPEAR320_UART2_IRQ_MASK,
+ .clear_mask = SPEAR320_UART2_IRQ_MASK,
}, {
- .virq = VIRQ_SSP1,
- .status_mask = SSP1_IRQ_MASK,
- .clear_mask = SSP1_IRQ_MASK,
+ .virq = SPEAR320_VIRQ_SSP1,
+ .status_mask = SPEAR320_SSP1_IRQ_MASK,
+ .clear_mask = SPEAR320_SSP1_IRQ_MASK,
}, {
- .virq = VIRQ_SSP2,
- .status_mask = SSP2_IRQ_MASK,
- .clear_mask = SSP2_IRQ_MASK,
+ .virq = SPEAR320_VIRQ_SSP2,
+ .status_mask = SPEAR320_SSP2_IRQ_MASK,
+ .clear_mask = SPEAR320_SSP2_IRQ_MASK,
}, {
- .virq = VIRQ_SMII0,
- .status_mask = SMII0_IRQ_MASK,
- .clear_mask = SMII0_IRQ_MASK,
+ .virq = SPEAR320_VIRQ_SMII0,
+ .status_mask = SPEAR320_SMII0_IRQ_MASK,
+ .clear_mask = SPEAR320_SMII0_IRQ_MASK,
}, {
- .virq = VIRQ_MII1_SMII1,
- .status_mask = MII1_SMII1_IRQ_MASK,
- .clear_mask = MII1_SMII1_IRQ_MASK,
+ .virq = SPEAR320_VIRQ_MII1_SMII1,
+ .status_mask = SPEAR320_MII1_SMII1_IRQ_MASK,
+ .clear_mask = SPEAR320_MII1_SMII1_IRQ_MASK,
}, {
- .virq = VIRQ_WAKEUP_SMII0,
- .status_mask = WAKEUP_SMII0_IRQ_MASK,
- .clear_mask = WAKEUP_SMII0_IRQ_MASK,
+ .virq = SPEAR320_VIRQ_WAKEUP_SMII0,
+ .status_mask = SPEAR320_WAKEUP_SMII0_IRQ_MASK,
+ .clear_mask = SPEAR320_WAKEUP_SMII0_IRQ_MASK,
}, {
- .virq = VIRQ_WAKEUP_MII1_SMII1,
- .status_mask = WAKEUP_MII1_SMII1_IRQ_MASK,
- .clear_mask = WAKEUP_MII1_SMII1_IRQ_MASK,
+ .virq = SPEAR320_VIRQ_WAKEUP_MII1_SMII1,
+ .status_mask = SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK,
+ .clear_mask = SPEAR320_WAKEUP_MII1_SMII1_IRQ_MASK,
}, {
- .virq = VIRQ_I2C,
- .status_mask = I2C1_IRQ_MASK,
- .clear_mask = I2C1_IRQ_MASK,
+ .virq = SPEAR320_VIRQ_I2C1,
+ .status_mask = SPEAR320_I2C1_IRQ_MASK,
+ .clear_mask = SPEAR320_I2C1_IRQ_MASK,
},
};
-struct spear_shirq shirq_intrcomm_ras = {
- .irq = IRQ_INTRCOMM_RAS_ARM,
+static struct spear_shirq shirq_intrcomm_ras = {
+ .irq = SPEAR3XX_IRQ_INTRCOMM_RAS_ARM,
.dev_config = shirq_intrcomm_ras_config,
.dev_count = ARRAY_SIZE(shirq_intrcomm_ras_config),
.regs = {
.enb_reg = -1,
- .status_reg = INT_STS_MASK_REG,
- .status_reg_mask = SHIRQ_INTRCOMM_RAS_MASK,
- .clear_reg = INT_CLR_MASK_REG,
+ .status_reg = SPEAR320_INT_STS_MASK_REG,
+ .status_reg_mask = SPEAR320_SHIRQ_INTRCOMM_RAS_MASK,
+ .clear_reg = SPEAR320_INT_CLR_MASK_REG,
.reset_to_clear = 1,
},
};
@@ -511,7 +511,8 @@
/* Add spear320 specific devices here */
/* spear320 routines */
-void __init spear320_init(void)
+void __init spear320_init(struct pmx_mode *pmx_mode, struct pmx_dev **pmx_devs,
+ u8 pmx_dev_count)
{
void __iomem *base;
int ret = 0;
@@ -543,6 +544,10 @@
/* pmx initialization */
pmx_driver.base = base;
+ pmx_driver.mode = pmx_mode;
+ pmx_driver.devs = pmx_devs;
+ pmx_driver.devs_count = pmx_dev_count;
+
ret = pmx_register(&pmx_driver);
if (ret)
printk(KERN_ERR "padmux: registeration failed. err no: %d\n",
diff --git a/arch/arm/mach-spear3xx/spear320_evb.c b/arch/arm/mach-spear3xx/spear320_evb.c
index 8213e4b..a12b353 100644
--- a/arch/arm/mach-spear3xx/spear320_evb.c
+++ b/arch/arm/mach-spear3xx/spear320_evb.c
@@ -19,28 +19,28 @@
/* padmux devices to enable */
static struct pmx_dev *pmx_devs[] = {
/* spear3xx specific devices */
- &pmx_i2c,
- &pmx_ssp,
- &pmx_mii,
- &pmx_uart0,
+ &spear3xx_pmx_i2c,
+ &spear3xx_pmx_ssp,
+ &spear3xx_pmx_mii,
+ &spear3xx_pmx_uart0,
/* spear320 specific devices */
- &pmx_fsmc,
- &pmx_sdhci,
- &pmx_i2s,
- &pmx_uart1,
- &pmx_uart2,
- &pmx_can,
- &pmx_pwm0,
- &pmx_pwm1,
- &pmx_pwm2,
- &pmx_mii1,
+ &spear320_pmx_fsmc,
+ &spear320_pmx_sdhci,
+ &spear320_pmx_i2s,
+ &spear320_pmx_uart1,
+ &spear320_pmx_uart2,
+ &spear320_pmx_can,
+ &spear320_pmx_pwm0,
+ &spear320_pmx_pwm1,
+ &spear320_pmx_pwm2,
+ &spear320_pmx_mii1,
};
static struct amba_device *amba_devs[] __initdata = {
/* spear3xx specific devices */
- &gpio_device,
- &uart_device,
+ &spear3xx_gpio_device,
+ &spear3xx_uart_device,
/* spear320 specific devices */
};
@@ -55,13 +55,9 @@
{
unsigned int i;
- /* padmux initialization, must be done before spear320_init */
- pmx_driver.mode = &auto_net_mii_mode;
- pmx_driver.devs = pmx_devs;
- pmx_driver.devs_count = ARRAY_SIZE(pmx_devs);
-
/* call spear320 machine init function */
- spear320_init();
+ spear320_init(&spear320_auto_net_mii_mode, pmx_devs,
+ ARRAY_SIZE(pmx_devs));
/* Add Platform Devices */
platform_add_devices(plat_devs, ARRAY_SIZE(plat_devs));
diff --git a/arch/arm/mach-spear3xx/spear3xx.c b/arch/arm/mach-spear3xx/spear3xx.c
index d3ba8ca..10af45d 100644
--- a/arch/arm/mach-spear3xx/spear3xx.c
+++ b/arch/arm/mach-spear3xx/spear3xx.c
@@ -25,10 +25,10 @@
/* gpio device registration */
static struct pl061_platform_data gpio_plat_data = {
.gpio_base = 0,
- .irq_base = SPEAR_GPIO_INT_BASE,
+ .irq_base = SPEAR3XX_GPIO_INT_BASE,
};
-struct amba_device gpio_device = {
+struct amba_device spear3xx_gpio_device = {
.dev = {
.init_name = "gpio",
.platform_data = &gpio_plat_data,
@@ -38,11 +38,11 @@
.end = SPEAR3XX_ICM3_GPIO_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
- .irq = {IRQ_BASIC_GPIO, NO_IRQ},
+ .irq = {SPEAR3XX_IRQ_BASIC_GPIO, NO_IRQ},
};
/* uart device registration */
-struct amba_device uart_device = {
+struct amba_device spear3xx_uart_device = {
.dev = {
.init_name = "uart",
},
@@ -51,7 +51,7 @@
.end = SPEAR3XX_ICM1_UART_BASE + SZ_4K - 1,
.flags = IORESOURCE_MEM,
},
- .irq = {IRQ_UART, NO_IRQ},
+ .irq = {SPEAR3XX_IRQ_UART, NO_IRQ},
};
/* Do spear3xx familiy common initialization part here */
@@ -97,215 +97,215 @@
iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc));
/* This will initialize clock framework */
- clk_init();
+ spear3xx_clk_init();
}
/* pad multiplexing support */
/* devices */
-struct pmx_dev_mode pmx_firda_modes[] = {
+static struct pmx_dev_mode pmx_firda_modes[] = {
{
.ids = 0xffffffff,
.mask = PMX_FIRDA_MASK,
},
};
-struct pmx_dev pmx_firda = {
+struct pmx_dev spear3xx_pmx_firda = {
.name = "firda",
.modes = pmx_firda_modes,
.mode_count = ARRAY_SIZE(pmx_firda_modes),
.enb_on_reset = 0,
};
-struct pmx_dev_mode pmx_i2c_modes[] = {
+static struct pmx_dev_mode pmx_i2c_modes[] = {
{
.ids = 0xffffffff,
.mask = PMX_I2C_MASK,
},
};
-struct pmx_dev pmx_i2c = {
+struct pmx_dev spear3xx_pmx_i2c = {
.name = "i2c",
.modes = pmx_i2c_modes,
.mode_count = ARRAY_SIZE(pmx_i2c_modes),
.enb_on_reset = 0,
};
-struct pmx_dev_mode pmx_ssp_cs_modes[] = {
+static struct pmx_dev_mode pmx_ssp_cs_modes[] = {
{
.ids = 0xffffffff,
.mask = PMX_SSP_CS_MASK,
},
};
-struct pmx_dev pmx_ssp_cs = {
+struct pmx_dev spear3xx_pmx_ssp_cs = {
.name = "ssp_chip_selects",
.modes = pmx_ssp_cs_modes,
.mode_count = ARRAY_SIZE(pmx_ssp_cs_modes),
.enb_on_reset = 0,
};
-struct pmx_dev_mode pmx_ssp_modes[] = {
+static struct pmx_dev_mode pmx_ssp_modes[] = {
{
.ids = 0xffffffff,
.mask = PMX_SSP_MASK,
},
};
-struct pmx_dev pmx_ssp = {
+struct pmx_dev spear3xx_pmx_ssp = {
.name = "ssp",
.modes = pmx_ssp_modes,
.mode_count = ARRAY_SIZE(pmx_ssp_modes),
.enb_on_reset = 0,
};
-struct pmx_dev_mode pmx_mii_modes[] = {
+static struct pmx_dev_mode pmx_mii_modes[] = {
{
.ids = 0xffffffff,
.mask = PMX_MII_MASK,
},
};
-struct pmx_dev pmx_mii = {
+struct pmx_dev spear3xx_pmx_mii = {
.name = "mii",
.modes = pmx_mii_modes,
.mode_count = ARRAY_SIZE(pmx_mii_modes),
.enb_on_reset = 0,
};
-struct pmx_dev_mode pmx_gpio_pin0_modes[] = {
+static struct pmx_dev_mode pmx_gpio_pin0_modes[] = {
{
.ids = 0xffffffff,
.mask = PMX_GPIO_PIN0_MASK,
},
};
-struct pmx_dev pmx_gpio_pin0 = {
+struct pmx_dev spear3xx_pmx_gpio_pin0 = {
.name = "gpio_pin0",
.modes = pmx_gpio_pin0_modes,
.mode_count = ARRAY_SIZE(pmx_gpio_pin0_modes),
.enb_on_reset = 0,
};
-struct pmx_dev_mode pmx_gpio_pin1_modes[] = {
+static struct pmx_dev_mode pmx_gpio_pin1_modes[] = {
{
.ids = 0xffffffff,
.mask = PMX_GPIO_PIN1_MASK,
},
};
-struct pmx_dev pmx_gpio_pin1 = {
+struct pmx_dev spear3xx_pmx_gpio_pin1 = {
.name = "gpio_pin1",
.modes = pmx_gpio_pin1_modes,
.mode_count = ARRAY_SIZE(pmx_gpio_pin1_modes),
.enb_on_reset = 0,
};
-struct pmx_dev_mode pmx_gpio_pin2_modes[] = {
+static struct pmx_dev_mode pmx_gpio_pin2_modes[] = {
{
.ids = 0xffffffff,
.mask = PMX_GPIO_PIN2_MASK,
},
};
-struct pmx_dev pmx_gpio_pin2 = {
+struct pmx_dev spear3xx_pmx_gpio_pin2 = {
.name = "gpio_pin2",
.modes = pmx_gpio_pin2_modes,
.mode_count = ARRAY_SIZE(pmx_gpio_pin2_modes),
.enb_on_reset = 0,
};
-struct pmx_dev_mode pmx_gpio_pin3_modes[] = {
+static struct pmx_dev_mode pmx_gpio_pin3_modes[] = {
{
.ids = 0xffffffff,
.mask = PMX_GPIO_PIN3_MASK,
},
};
-struct pmx_dev pmx_gpio_pin3 = {
+struct pmx_dev spear3xx_pmx_gpio_pin3 = {
.name = "gpio_pin3",
.modes = pmx_gpio_pin3_modes,
.mode_count = ARRAY_SIZE(pmx_gpio_pin3_modes),
.enb_on_reset = 0,
};
-struct pmx_dev_mode pmx_gpio_pin4_modes[] = {
+static struct pmx_dev_mode pmx_gpio_pin4_modes[] = {
{
.ids = 0xffffffff,
.mask = PMX_GPIO_PIN4_MASK,
},
};
-struct pmx_dev pmx_gpio_pin4 = {
+struct pmx_dev spear3xx_pmx_gpio_pin4 = {
.name = "gpio_pin4",
.modes = pmx_gpio_pin4_modes,
.mode_count = ARRAY_SIZE(pmx_gpio_pin4_modes),
.enb_on_reset = 0,
};
-struct pmx_dev_mode pmx_gpio_pin5_modes[] = {
+static struct pmx_dev_mode pmx_gpio_pin5_modes[] = {
{
.ids = 0xffffffff,
.mask = PMX_GPIO_PIN5_MASK,
},
};
-struct pmx_dev pmx_gpio_pin5 = {
+struct pmx_dev spear3xx_pmx_gpio_pin5 = {
.name = "gpio_pin5",
.modes = pmx_gpio_pin5_modes,
.mode_count = ARRAY_SIZE(pmx_gpio_pin5_modes),
.enb_on_reset = 0,
};
-struct pmx_dev_mode pmx_uart0_modem_modes[] = {
+static struct pmx_dev_mode pmx_uart0_modem_modes[] = {
{
.ids = 0xffffffff,
.mask = PMX_UART0_MODEM_MASK,
},
};
-struct pmx_dev pmx_uart0_modem = {
+struct pmx_dev spear3xx_pmx_uart0_modem = {
.name = "uart0_modem",
.modes = pmx_uart0_modem_modes,
.mode_count = ARRAY_SIZE(pmx_uart0_modem_modes),
.enb_on_reset = 0,
};
-struct pmx_dev_mode pmx_uart0_modes[] = {
+static struct pmx_dev_mode pmx_uart0_modes[] = {
{
.ids = 0xffffffff,
.mask = PMX_UART0_MASK,
},
};
-struct pmx_dev pmx_uart0 = {
+struct pmx_dev spear3xx_pmx_uart0 = {
.name = "uart0",
.modes = pmx_uart0_modes,
.mode_count = ARRAY_SIZE(pmx_uart0_modes),
.enb_on_reset = 0,
};
-struct pmx_dev_mode pmx_timer_3_4_modes[] = {
+static struct pmx_dev_mode pmx_timer_3_4_modes[] = {
{
.ids = 0xffffffff,
.mask = PMX_TIMER_3_4_MASK,
},
};
-struct pmx_dev pmx_timer_3_4 = {
+struct pmx_dev spear3xx_pmx_timer_3_4 = {
.name = "timer_3_4",
.modes = pmx_timer_3_4_modes,
.mode_count = ARRAY_SIZE(pmx_timer_3_4_modes),
.enb_on_reset = 0,
};
-struct pmx_dev_mode pmx_timer_1_2_modes[] = {
+static struct pmx_dev_mode pmx_timer_1_2_modes[] = {
{
.ids = 0xffffffff,
.mask = PMX_TIMER_1_2_MASK,
},
};
-struct pmx_dev pmx_timer_1_2 = {
+struct pmx_dev spear3xx_pmx_timer_1_2 = {
.name = "timer_1_2",
.modes = pmx_timer_1_2_modes,
.mode_count = ARRAY_SIZE(pmx_timer_1_2_modes),
@@ -314,210 +314,210 @@
#if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320)
/* plgpios devices */
-struct pmx_dev_mode pmx_plgpio_0_1_modes[] = {
+static struct pmx_dev_mode pmx_plgpio_0_1_modes[] = {
{
.ids = 0x00,
.mask = PMX_FIRDA_MASK,
},
};
-struct pmx_dev pmx_plgpio_0_1 = {
+struct pmx_dev spear3xx_pmx_plgpio_0_1 = {
.name = "plgpio 0 and 1",
.modes = pmx_plgpio_0_1_modes,
.mode_count = ARRAY_SIZE(pmx_plgpio_0_1_modes),
.enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_plgpio_2_3_modes[] = {
+static struct pmx_dev_mode pmx_plgpio_2_3_modes[] = {
{
.ids = 0x00,
.mask = PMX_UART0_MASK,
},
};
-struct pmx_dev pmx_plgpio_2_3 = {
+struct pmx_dev spear3xx_pmx_plgpio_2_3 = {
.name = "plgpio 2 and 3",
.modes = pmx_plgpio_2_3_modes,
.mode_count = ARRAY_SIZE(pmx_plgpio_2_3_modes),
.enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_plgpio_4_5_modes[] = {
+static struct pmx_dev_mode pmx_plgpio_4_5_modes[] = {
{
.ids = 0x00,
.mask = PMX_I2C_MASK,
},
};
-struct pmx_dev pmx_plgpio_4_5 = {
+struct pmx_dev spear3xx_pmx_plgpio_4_5 = {
.name = "plgpio 4 and 5",
.modes = pmx_plgpio_4_5_modes,
.mode_count = ARRAY_SIZE(pmx_plgpio_4_5_modes),
.enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_plgpio_6_9_modes[] = {
+static struct pmx_dev_mode pmx_plgpio_6_9_modes[] = {
{
.ids = 0x00,
.mask = PMX_SSP_MASK,
},
};
-struct pmx_dev pmx_plgpio_6_9 = {
+struct pmx_dev spear3xx_pmx_plgpio_6_9 = {
.name = "plgpio 6 to 9",
.modes = pmx_plgpio_6_9_modes,
.mode_count = ARRAY_SIZE(pmx_plgpio_6_9_modes),
.enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_plgpio_10_27_modes[] = {
+static struct pmx_dev_mode pmx_plgpio_10_27_modes[] = {
{
.ids = 0x00,
.mask = PMX_MII_MASK,
},
};
-struct pmx_dev pmx_plgpio_10_27 = {
+struct pmx_dev spear3xx_pmx_plgpio_10_27 = {
.name = "plgpio 10 to 27",
.modes = pmx_plgpio_10_27_modes,
.mode_count = ARRAY_SIZE(pmx_plgpio_10_27_modes),
.enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_plgpio_28_modes[] = {
+static struct pmx_dev_mode pmx_plgpio_28_modes[] = {
{
.ids = 0x00,
.mask = PMX_GPIO_PIN0_MASK,
},
};
-struct pmx_dev pmx_plgpio_28 = {
+struct pmx_dev spear3xx_pmx_plgpio_28 = {
.name = "plgpio 28",
.modes = pmx_plgpio_28_modes,
.mode_count = ARRAY_SIZE(pmx_plgpio_28_modes),
.enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_plgpio_29_modes[] = {
+static struct pmx_dev_mode pmx_plgpio_29_modes[] = {
{
.ids = 0x00,
.mask = PMX_GPIO_PIN1_MASK,
},
};
-struct pmx_dev pmx_plgpio_29 = {
+struct pmx_dev spear3xx_pmx_plgpio_29 = {
.name = "plgpio 29",
.modes = pmx_plgpio_29_modes,
.mode_count = ARRAY_SIZE(pmx_plgpio_29_modes),
.enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_plgpio_30_modes[] = {
+static struct pmx_dev_mode pmx_plgpio_30_modes[] = {
{
.ids = 0x00,
.mask = PMX_GPIO_PIN2_MASK,
},
};
-struct pmx_dev pmx_plgpio_30 = {
+struct pmx_dev spear3xx_pmx_plgpio_30 = {
.name = "plgpio 30",
.modes = pmx_plgpio_30_modes,
.mode_count = ARRAY_SIZE(pmx_plgpio_30_modes),
.enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_plgpio_31_modes[] = {
+static struct pmx_dev_mode pmx_plgpio_31_modes[] = {
{
.ids = 0x00,
.mask = PMX_GPIO_PIN3_MASK,
},
};
-struct pmx_dev pmx_plgpio_31 = {
+struct pmx_dev spear3xx_pmx_plgpio_31 = {
.name = "plgpio 31",
.modes = pmx_plgpio_31_modes,
.mode_count = ARRAY_SIZE(pmx_plgpio_31_modes),
.enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_plgpio_32_modes[] = {
+static struct pmx_dev_mode pmx_plgpio_32_modes[] = {
{
.ids = 0x00,
.mask = PMX_GPIO_PIN4_MASK,
},
};
-struct pmx_dev pmx_plgpio_32 = {
+struct pmx_dev spear3xx_pmx_plgpio_32 = {
.name = "plgpio 32",
.modes = pmx_plgpio_32_modes,
.mode_count = ARRAY_SIZE(pmx_plgpio_32_modes),
.enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_plgpio_33_modes[] = {
+static struct pmx_dev_mode pmx_plgpio_33_modes[] = {
{
.ids = 0x00,
.mask = PMX_GPIO_PIN5_MASK,
},
};
-struct pmx_dev pmx_plgpio_33 = {
+struct pmx_dev spear3xx_pmx_plgpio_33 = {
.name = "plgpio 33",
.modes = pmx_plgpio_33_modes,
.mode_count = ARRAY_SIZE(pmx_plgpio_33_modes),
.enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_plgpio_34_36_modes[] = {
+static struct pmx_dev_mode pmx_plgpio_34_36_modes[] = {
{
.ids = 0x00,
.mask = PMX_SSP_CS_MASK,
},
};
-struct pmx_dev pmx_plgpio_34_36 = {
+struct pmx_dev spear3xx_pmx_plgpio_34_36 = {
.name = "plgpio 34 to 36",
.modes = pmx_plgpio_34_36_modes,
.mode_count = ARRAY_SIZE(pmx_plgpio_34_36_modes),
.enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_plgpio_37_42_modes[] = {
+static struct pmx_dev_mode pmx_plgpio_37_42_modes[] = {
{
.ids = 0x00,
.mask = PMX_UART0_MODEM_MASK,
},
};
-struct pmx_dev pmx_plgpio_37_42 = {
+struct pmx_dev spear3xx_pmx_plgpio_37_42 = {
.name = "plgpio 37 to 42",
.modes = pmx_plgpio_37_42_modes,
.mode_count = ARRAY_SIZE(pmx_plgpio_37_42_modes),
.enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_plgpio_43_44_47_48_modes[] = {
+static struct pmx_dev_mode pmx_plgpio_43_44_47_48_modes[] = {
{
.ids = 0x00,
.mask = PMX_TIMER_1_2_MASK,
},
};
-struct pmx_dev pmx_plgpio_43_44_47_48 = {
+struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48 = {
.name = "plgpio 43, 44, 47 and 48",
.modes = pmx_plgpio_43_44_47_48_modes,
.mode_count = ARRAY_SIZE(pmx_plgpio_43_44_47_48_modes),
.enb_on_reset = 1,
};
-struct pmx_dev_mode pmx_plgpio_45_46_49_50_modes[] = {
+static struct pmx_dev_mode pmx_plgpio_45_46_49_50_modes[] = {
{
.ids = 0x00,
.mask = PMX_TIMER_3_4_MASK,
},
};
-struct pmx_dev pmx_plgpio_45_46_49_50 = {
+struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50 = {
.name = "plgpio 45, 46, 49 and 50",
.modes = pmx_plgpio_45_46_49_50_modes,
.mode_count = ARRAY_SIZE(pmx_plgpio_45_46_49_50_modes),
diff --git a/arch/arm/mach-spear6xx/Kconfig b/arch/arm/mach-spear6xx/Kconfig
index bddba03..ff4ae5b 100644
--- a/arch/arm/mach-spear6xx/Kconfig
+++ b/arch/arm/mach-spear6xx/Kconfig
@@ -4,17 +4,18 @@
if ARCH_SPEAR6XX
-choice
- prompt "SPEAr6XX Family"
- default MACH_SPEAR600
+menu "SPEAr6xx Implementations"
+config BOARD_SPEAR600_EVB
+ bool "SPEAr600 Evaluation Board"
+ select MACH_SPEAR600
+ help
+ Supports ST SPEAr600 Evaluation Board
+
+endmenu
config MACH_SPEAR600
bool "SPEAr600"
help
Supports ST SPEAr600 Machine
-endchoice
-
-# Adding SPEAr6XX machine specific configuration files
-source "arch/arm/mach-spear6xx/Kconfig600"
endif #ARCH_SPEAR6XX
diff --git a/arch/arm/mach-spear6xx/Kconfig600 b/arch/arm/mach-spear6xx/Kconfig600
deleted file mode 100644
index 9e19f65..0000000
--- a/arch/arm/mach-spear6xx/Kconfig600
+++ /dev/null
@@ -1,17 +0,0 @@
-#
-# SPEAr600 machine configuration file
-#
-
-if MACH_SPEAR600
-
-choice
- prompt "SPEAr600 Boards"
- default BOARD_SPEAR600_EVB
-
-config BOARD_SPEAR600_EVB
- bool "SPEAr600 Evaluation Board"
- help
- Supports ST SPEAr600 Evaluation Board
-endchoice
-
-endif #MACH_SPEAR600
diff --git a/arch/arm/mach-spear6xx/clock.c b/arch/arm/mach-spear6xx/clock.c
index 88b748b..ac70e0d 100644
--- a/arch/arm/mach-spear6xx/clock.c
+++ b/arch/arm/mach-spear6xx/clock.c
@@ -671,12 +671,12 @@
{ .dev_id = "gpio2", .clk = &gpio2_clk},
};
-void __init clk_init(void)
+void __init spear6xx_clk_init(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(spear_clk_lookups); i++)
clk_register(&spear_clk_lookups[i]);
- recalc_root_clocks();
+ clk_init();
}
diff --git a/arch/arm/mach-spear6xx/include/mach/generic.h b/arch/arm/mach-spear6xx/include/mach/generic.h
index 94cf4a6..183f023 100644
--- a/arch/arm/mach-spear6xx/include/mach/generic.h
+++ b/arch/arm/mach-spear6xx/include/mach/generic.h
@@ -39,7 +39,7 @@
void __init spear6xx_init_irq(void);
void __init spear6xx_init(void);
void __init spear600_init(void);
-void __init clk_init(void);
+void __init spear6xx_clk_init(void);
/* Add spear600 machine device structure declarations here */
diff --git a/arch/arm/mach-spear6xx/spear6xx.c b/arch/arm/mach-spear6xx/spear6xx.c
index 9818129..e0f6628 100644
--- a/arch/arm/mach-spear6xx/spear6xx.c
+++ b/arch/arm/mach-spear6xx/spear6xx.c
@@ -148,7 +148,7 @@
iotable_init(spear6xx_io_desc, ARRAY_SIZE(spear6xx_io_desc));
/* This will initialize clock framework */
- clk_init();
+ spear6xx_clk_init();
}
static void __init spear6xx_timer_init(void)
diff --git a/arch/arm/mach-stmp378x/Makefile b/arch/arm/mach-stmp378x/Makefile
deleted file mode 100644
index d156f76..0000000
--- a/arch/arm/mach-stmp378x/Makefile
+++ /dev/null
@@ -1,2 +0,0 @@
-obj-$(CONFIG_ARCH_STMP378X) += stmp378x.o
-obj-$(CONFIG_MACH_STMP378X) += stmp378x_devb.o
diff --git a/arch/arm/mach-stmp378x/Makefile.boot b/arch/arm/mach-stmp378x/Makefile.boot
deleted file mode 100644
index 1568ad4..0000000
--- a/arch/arm/mach-stmp378x/Makefile.boot
+++ /dev/null
@@ -1,3 +0,0 @@
- zreladdr-y := 0x40008000
-params_phys-y := 0x40000100
-initrd_phys-y := 0x40800000
diff --git a/arch/arm/mach-stmp378x/include/mach/entry-macro.S b/arch/arm/mach-stmp378x/include/mach/entry-macro.S
deleted file mode 100644
index 731a922..0000000
--- a/arch/arm/mach-stmp378x/include/mach/entry-macro.S
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * Low-level IRQ helper macros for Freescale STMP378X
- *
- * Embedded Alley Solutions, Inc <source@embeddedalley.com>
- *
- * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
- .macro disable_fiq
- .endm
-
- .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
-
- mov \base, #0xf0000000 @ vm address of IRQ controller
- ldr \irqnr, [\base, #0x70] @ HW_ICOLL_STAT
- cmp \irqnr, #0x7f
- moveqs \irqnr, #0 @ Zero flag set for no IRQ
-
- .endm
-
- .macro get_irqnr_preamble, base, tmp
- .endm
-
- .macro arch_ret_to_user, tmp1, tmp2
- .endm
diff --git a/arch/arm/mach-stmp378x/include/mach/irqs.h b/arch/arm/mach-stmp378x/include/mach/irqs.h
deleted file mode 100644
index cc59673..0000000
--- a/arch/arm/mach-stmp378x/include/mach/irqs.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
- * Freescale STMP378X interrupts
- *
- * Copyright (C) 2005 Sigmatel Inc
- *
- * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#define IRQ_DEBUG_UART 0
-#define IRQ_COMMS_RX 1
-#define IRQ_COMMS_TX 1
-#define IRQ_SSP2_ERROR 2
-#define IRQ_VDD5V 3
-#define IRQ_HEADPHONE_SHORT 4
-#define IRQ_DAC_DMA 5
-#define IRQ_DAC_ERROR 6
-#define IRQ_ADC_DMA 7
-#define IRQ_ADC_ERROR 8
-#define IRQ_SPDIF_DMA 9
-#define IRQ_SAIF2_DMA 9
-#define IRQ_SPDIF_ERROR 10
-#define IRQ_SAIF1_IRQ 10
-#define IRQ_SAIF2_IRQ 10
-#define IRQ_USB_CTRL 11
-#define IRQ_USB_WAKEUP 12
-#define IRQ_GPMI_DMA 13
-#define IRQ_SSP1_DMA 14
-#define IRQ_SSP_ERROR 15
-#define IRQ_GPIO0 16
-#define IRQ_GPIO1 17
-#define IRQ_GPIO2 18
-#define IRQ_SAIF1_DMA 19
-#define IRQ_SSP2_DMA 20
-#define IRQ_ECC8_IRQ 21
-#define IRQ_RTC_ALARM 22
-#define IRQ_UARTAPP_TX_DMA 23
-#define IRQ_UARTAPP_INTERNAL 24
-#define IRQ_UARTAPP_RX_DMA 25
-#define IRQ_I2C_DMA 26
-#define IRQ_I2C_ERROR 27
-#define IRQ_TIMER0 28
-#define IRQ_TIMER1 29
-#define IRQ_TIMER2 30
-#define IRQ_TIMER3 31
-#define IRQ_BATT_BRNOUT 32
-#define IRQ_VDDD_BRNOUT 33
-#define IRQ_VDDIO_BRNOUT 34
-#define IRQ_VDD18_BRNOUT 35
-#define IRQ_TOUCH_DETECT 36
-#define IRQ_LRADC_CH0 37
-#define IRQ_LRADC_CH1 38
-#define IRQ_LRADC_CH2 39
-#define IRQ_LRADC_CH3 40
-#define IRQ_LRADC_CH4 41
-#define IRQ_LRADC_CH5 42
-#define IRQ_LRADC_CH6 43
-#define IRQ_LRADC_CH7 44
-#define IRQ_LCDIF_DMA 45
-#define IRQ_LCDIF_ERROR 46
-#define IRQ_DIGCTL_DEBUG_TRAP 47
-#define IRQ_RTC_1MSEC 48
-#define IRQ_DRI_DMA 49
-#define IRQ_DRI_ATTENTION 50
-#define IRQ_GPMI_ATTENTION 51
-#define IRQ_IR 52
-#define IRQ_DCP_VMI 53
-#define IRQ_DCP 54
-#define IRQ_BCH 56
-#define IRQ_PXP 57
-#define IRQ_UARTAPP2_TX_DMA 58
-#define IRQ_UARTAPP2_INTERNAL 59
-#define IRQ_UARTAPP2_RX_DMA 60
-#define IRQ_VDAC_DETECT 61
-#define IRQ_VDD5V_DROOP 64
-#define IRQ_DCDC4P2_BO 65
-
-
-#define NR_REAL_IRQS 128
-#define NR_IRQS (NR_REAL_IRQS + 32 * 3)
-
-/* All interrupts are FIQ capable */
-#define FIQ_START IRQ_DEBUG_UART
-
-/* Hard disk IRQ is a GPMI attention IRQ */
-#define IRQ_HARDDISK IRQ_GPMI_ATTENTION
diff --git a/arch/arm/mach-stmp378x/include/mach/pins.h b/arch/arm/mach-stmp378x/include/mach/pins.h
deleted file mode 100644
index 93f952d..0000000
--- a/arch/arm/mach-stmp378x/include/mach/pins.h
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- * Freescale STMP378X SoC pin multiplexing
- *
- * Author: Vladislav Buzov <vbuzov@embeddedalley.com>
- *
- * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#ifndef __ASM_ARCH_PINS_H
-#define __ASM_ARCH_PINS_H
-
-/*
- * Define all STMP378x pins, a pin name corresponds to a STMP378x hardware
- * interface this pin belongs to.
- */
-
-/* Bank 0 */
-#define PINID_GPMI_D00 STMP3XXX_PINID(0, 0)
-#define PINID_GPMI_D01 STMP3XXX_PINID(0, 1)
-#define PINID_GPMI_D02 STMP3XXX_PINID(0, 2)
-#define PINID_GPMI_D03 STMP3XXX_PINID(0, 3)
-#define PINID_GPMI_D04 STMP3XXX_PINID(0, 4)
-#define PINID_GPMI_D05 STMP3XXX_PINID(0, 5)
-#define PINID_GPMI_D06 STMP3XXX_PINID(0, 6)
-#define PINID_GPMI_D07 STMP3XXX_PINID(0, 7)
-#define PINID_GPMI_D08 STMP3XXX_PINID(0, 8)
-#define PINID_GPMI_D09 STMP3XXX_PINID(0, 9)
-#define PINID_GPMI_D10 STMP3XXX_PINID(0, 10)
-#define PINID_GPMI_D11 STMP3XXX_PINID(0, 11)
-#define PINID_GPMI_D12 STMP3XXX_PINID(0, 12)
-#define PINID_GPMI_D13 STMP3XXX_PINID(0, 13)
-#define PINID_GPMI_D14 STMP3XXX_PINID(0, 14)
-#define PINID_GPMI_D15 STMP3XXX_PINID(0, 15)
-#define PINID_GPMI_CLE STMP3XXX_PINID(0, 16)
-#define PINID_GPMI_ALE STMP3XXX_PINID(0, 17)
-#define PINID_GMPI_CE2N STMP3XXX_PINID(0, 18)
-#define PINID_GPMI_RDY0 STMP3XXX_PINID(0, 19)
-#define PINID_GPMI_RDY1 STMP3XXX_PINID(0, 20)
-#define PINID_GPMI_RDY2 STMP3XXX_PINID(0, 21)
-#define PINID_GPMI_RDY3 STMP3XXX_PINID(0, 22)
-#define PINID_GPMI_WPN STMP3XXX_PINID(0, 23)
-#define PINID_GPMI_WRN STMP3XXX_PINID(0, 24)
-#define PINID_GPMI_RDN STMP3XXX_PINID(0, 25)
-#define PINID_AUART1_CTS STMP3XXX_PINID(0, 26)
-#define PINID_AUART1_RTS STMP3XXX_PINID(0, 27)
-#define PINID_AUART1_RX STMP3XXX_PINID(0, 28)
-#define PINID_AUART1_TX STMP3XXX_PINID(0, 29)
-#define PINID_I2C_SCL STMP3XXX_PINID(0, 30)
-#define PINID_I2C_SDA STMP3XXX_PINID(0, 31)
-
-/* Bank 1 */
-#define PINID_LCD_D00 STMP3XXX_PINID(1, 0)
-#define PINID_LCD_D01 STMP3XXX_PINID(1, 1)
-#define PINID_LCD_D02 STMP3XXX_PINID(1, 2)
-#define PINID_LCD_D03 STMP3XXX_PINID(1, 3)
-#define PINID_LCD_D04 STMP3XXX_PINID(1, 4)
-#define PINID_LCD_D05 STMP3XXX_PINID(1, 5)
-#define PINID_LCD_D06 STMP3XXX_PINID(1, 6)
-#define PINID_LCD_D07 STMP3XXX_PINID(1, 7)
-#define PINID_LCD_D08 STMP3XXX_PINID(1, 8)
-#define PINID_LCD_D09 STMP3XXX_PINID(1, 9)
-#define PINID_LCD_D10 STMP3XXX_PINID(1, 10)
-#define PINID_LCD_D11 STMP3XXX_PINID(1, 11)
-#define PINID_LCD_D12 STMP3XXX_PINID(1, 12)
-#define PINID_LCD_D13 STMP3XXX_PINID(1, 13)
-#define PINID_LCD_D14 STMP3XXX_PINID(1, 14)
-#define PINID_LCD_D15 STMP3XXX_PINID(1, 15)
-#define PINID_LCD_D16 STMP3XXX_PINID(1, 16)
-#define PINID_LCD_D17 STMP3XXX_PINID(1, 17)
-#define PINID_LCD_RESET STMP3XXX_PINID(1, 18)
-#define PINID_LCD_RS STMP3XXX_PINID(1, 19)
-#define PINID_LCD_WR STMP3XXX_PINID(1, 20)
-#define PINID_LCD_CS STMP3XXX_PINID(1, 21)
-#define PINID_LCD_DOTCK STMP3XXX_PINID(1, 22)
-#define PINID_LCD_ENABLE STMP3XXX_PINID(1, 23)
-#define PINID_LCD_HSYNC STMP3XXX_PINID(1, 24)
-#define PINID_LCD_VSYNC STMP3XXX_PINID(1, 25)
-#define PINID_PWM0 STMP3XXX_PINID(1, 26)
-#define PINID_PWM1 STMP3XXX_PINID(1, 27)
-#define PINID_PWM2 STMP3XXX_PINID(1, 28)
-#define PINID_PWM3 STMP3XXX_PINID(1, 29)
-#define PINID_PWM4 STMP3XXX_PINID(1, 30)
-
-/* Bank 2 */
-#define PINID_SSP1_CMD STMP3XXX_PINID(2, 0)
-#define PINID_SSP1_DETECT STMP3XXX_PINID(2, 1)
-#define PINID_SSP1_DATA0 STMP3XXX_PINID(2, 2)
-#define PINID_SSP1_DATA1 STMP3XXX_PINID(2, 3)
-#define PINID_SSP1_DATA2 STMP3XXX_PINID(2, 4)
-#define PINID_SSP1_DATA3 STMP3XXX_PINID(2, 5)
-#define PINID_SSP1_SCK STMP3XXX_PINID(2, 6)
-#define PINID_ROTARYA STMP3XXX_PINID(2, 7)
-#define PINID_ROTARYB STMP3XXX_PINID(2, 8)
-#define PINID_EMI_A00 STMP3XXX_PINID(2, 9)
-#define PINID_EMI_A01 STMP3XXX_PINID(2, 10)
-#define PINID_EMI_A02 STMP3XXX_PINID(2, 11)
-#define PINID_EMI_A03 STMP3XXX_PINID(2, 12)
-#define PINID_EMI_A04 STMP3XXX_PINID(2, 13)
-#define PINID_EMI_A05 STMP3XXX_PINID(2, 14)
-#define PINID_EMI_A06 STMP3XXX_PINID(2, 15)
-#define PINID_EMI_A07 STMP3XXX_PINID(2, 16)
-#define PINID_EMI_A08 STMP3XXX_PINID(2, 17)
-#define PINID_EMI_A09 STMP3XXX_PINID(2, 18)
-#define PINID_EMI_A10 STMP3XXX_PINID(2, 19)
-#define PINID_EMI_A11 STMP3XXX_PINID(2, 20)
-#define PINID_EMI_A12 STMP3XXX_PINID(2, 21)
-#define PINID_EMI_BA0 STMP3XXX_PINID(2, 22)
-#define PINID_EMI_BA1 STMP3XXX_PINID(2, 23)
-#define PINID_EMI_CASN STMP3XXX_PINID(2, 24)
-#define PINID_EMI_CE0N STMP3XXX_PINID(2, 25)
-#define PINID_EMI_CE1N STMP3XXX_PINID(2, 26)
-#define PINID_GPMI_CE1N STMP3XXX_PINID(2, 27)
-#define PINID_GPMI_CE0N STMP3XXX_PINID(2, 28)
-#define PINID_EMI_CKE STMP3XXX_PINID(2, 29)
-#define PINID_EMI_RASN STMP3XXX_PINID(2, 30)
-#define PINID_EMI_WEN STMP3XXX_PINID(2, 31)
-
-/* Bank 3 */
-#define PINID_EMI_D00 STMP3XXX_PINID(3, 0)
-#define PINID_EMI_D01 STMP3XXX_PINID(3, 1)
-#define PINID_EMI_D02 STMP3XXX_PINID(3, 2)
-#define PINID_EMI_D03 STMP3XXX_PINID(3, 3)
-#define PINID_EMI_D04 STMP3XXX_PINID(3, 4)
-#define PINID_EMI_D05 STMP3XXX_PINID(3, 5)
-#define PINID_EMI_D06 STMP3XXX_PINID(3, 6)
-#define PINID_EMI_D07 STMP3XXX_PINID(3, 7)
-#define PINID_EMI_D08 STMP3XXX_PINID(3, 8)
-#define PINID_EMI_D09 STMP3XXX_PINID(3, 9)
-#define PINID_EMI_D10 STMP3XXX_PINID(3, 10)
-#define PINID_EMI_D11 STMP3XXX_PINID(3, 11)
-#define PINID_EMI_D12 STMP3XXX_PINID(3, 12)
-#define PINID_EMI_D13 STMP3XXX_PINID(3, 13)
-#define PINID_EMI_D14 STMP3XXX_PINID(3, 14)
-#define PINID_EMI_D15 STMP3XXX_PINID(3, 15)
-#define PINID_EMI_DQM0 STMP3XXX_PINID(3, 16)
-#define PINID_EMI_DQM1 STMP3XXX_PINID(3, 17)
-#define PINID_EMI_DQS0 STMP3XXX_PINID(3, 18)
-#define PINID_EMI_DQS1 STMP3XXX_PINID(3, 19)
-#define PINID_EMI_CLK STMP3XXX_PINID(3, 20)
-#define PINID_EMI_CLKN STMP3XXX_PINID(3, 21)
-
-#endif /* __ASM_ARCH_PINS_H */
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-apbh.h b/arch/arm/mach-stmp378x/include/mach/regs-apbh.h
deleted file mode 100644
index dbcf85b..0000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-apbh.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * stmp378x: APBH register definitions
- *
- * Copyright (c) 2008 Freescale Semiconductor
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#ifndef _MACH_REGS_APBH
-#define _MACH_REGS_APBH
-
-#define REGS_APBH_BASE (STMP3XXX_REGS_BASE + 0x4000)
-#define REGS_APBH_PHYS 0x80004000
-#define REGS_APBH_SIZE 0x2000
-
-#define HW_APBH_CTRL0 0x0
-#define BM_APBH_CTRL0_RESET_CHANNEL 0x00FF0000
-#define BP_APBH_CTRL0_RESET_CHANNEL 16
-#define BM_APBH_CTRL0_CLKGATE 0x40000000
-#define BM_APBH_CTRL0_SFTRST 0x80000000
-
-#define HW_APBH_CTRL1 0x10
-#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0x00000001
-#define BP_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0
-
-#define HW_APBH_CTRL2 0x20
-
-#define HW_APBH_DEVSEL 0x30
-
-#define HW_APBH_CH0_NXTCMDAR (0x50 + 0 * 0x70)
-#define HW_APBH_CH1_NXTCMDAR (0x50 + 1 * 0x70)
-#define HW_APBH_CH2_NXTCMDAR (0x50 + 2 * 0x70)
-#define HW_APBH_CH3_NXTCMDAR (0x50 + 3 * 0x70)
-#define HW_APBH_CH4_NXTCMDAR (0x50 + 4 * 0x70)
-#define HW_APBH_CH5_NXTCMDAR (0x50 + 5 * 0x70)
-#define HW_APBH_CH6_NXTCMDAR (0x50 + 6 * 0x70)
-#define HW_APBH_CH7_NXTCMDAR (0x50 + 7 * 0x70)
-#define HW_APBH_CH8_NXTCMDAR (0x50 + 8 * 0x70)
-#define HW_APBH_CH9_NXTCMDAR (0x50 + 9 * 0x70)
-#define HW_APBH_CH10_NXTCMDAR (0x50 + 10 * 0x70)
-#define HW_APBH_CH11_NXTCMDAR (0x50 + 11 * 0x70)
-#define HW_APBH_CH12_NXTCMDAR (0x50 + 12 * 0x70)
-#define HW_APBH_CH13_NXTCMDAR (0x50 + 13 * 0x70)
-#define HW_APBH_CH14_NXTCMDAR (0x50 + 14 * 0x70)
-#define HW_APBH_CH15_NXTCMDAR (0x50 + 15 * 0x70)
-
-#define HW_APBH_CHn_NXTCMDAR 0x50
-
-#define BV_APBH_CHn_CMD_COMMAND__NO_DMA_XFER 0
-#define BV_APBH_CHn_CMD_COMMAND__DMA_WRITE 1
-#define BV_APBH_CHn_CMD_COMMAND__DMA_READ 2
-#define BV_APBH_CHn_CMD_COMMAND__DMA_SENSE 3
-#define BM_APBH_CHn_CMD_COMMAND 0x00000003
-#define BP_APBH_CHn_CMD_COMMAND 0
-#define BM_APBH_CHn_CMD_CHAIN 0x00000004
-#define BM_APBH_CHn_CMD_IRQONCMPLT 0x00000008
-#define BM_APBH_CHn_CMD_NANDLOCK 0x00000010
-#define BM_APBH_CHn_CMD_NANDWAIT4READY 0x00000020
-#define BM_APBH_CHn_CMD_SEMAPHORE 0x00000040
-#define BM_APBH_CHn_CMD_WAIT4ENDCMD 0x00000080
-#define BM_APBH_CHn_CMD_CMDWORDS 0x0000F000
-#define BP_APBH_CHn_CMD_CMDWORDS 12
-#define BM_APBH_CHn_CMD_XFER_COUNT 0xFFFF0000
-#define BP_APBH_CHn_CMD_XFER_COUNT 16
-
-#define HW_APBH_CH0_SEMA (0x80 + 0 * 0x70)
-#define HW_APBH_CH1_SEMA (0x80 + 1 * 0x70)
-#define HW_APBH_CH2_SEMA (0x80 + 2 * 0x70)
-#define HW_APBH_CH3_SEMA (0x80 + 3 * 0x70)
-#define HW_APBH_CH4_SEMA (0x80 + 4 * 0x70)
-#define HW_APBH_CH5_SEMA (0x80 + 5 * 0x70)
-#define HW_APBH_CH6_SEMA (0x80 + 6 * 0x70)
-#define HW_APBH_CH7_SEMA (0x80 + 7 * 0x70)
-#define HW_APBH_CH8_SEMA (0x80 + 8 * 0x70)
-#define HW_APBH_CH9_SEMA (0x80 + 9 * 0x70)
-#define HW_APBH_CH10_SEMA (0x80 + 10 * 0x70)
-#define HW_APBH_CH11_SEMA (0x80 + 11 * 0x70)
-#define HW_APBH_CH12_SEMA (0x80 + 12 * 0x70)
-#define HW_APBH_CH13_SEMA (0x80 + 13 * 0x70)
-#define HW_APBH_CH14_SEMA (0x80 + 14 * 0x70)
-#define HW_APBH_CH15_SEMA (0x80 + 15 * 0x70)
-
-#define HW_APBH_CHn_SEMA 0x80
-#define BM_APBH_CHn_SEMA_INCREMENT_SEMA 0x000000FF
-#define BP_APBH_CHn_SEMA_INCREMENT_SEMA 0
-#define BM_APBH_CHn_SEMA_PHORE 0x00FF0000
-#define BP_APBH_CHn_SEMA_PHORE 16
-
-#endif
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-apbx.h b/arch/arm/mach-stmp378x/include/mach/regs-apbx.h
deleted file mode 100644
index 3b934a4..0000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-apbx.h
+++ /dev/null
@@ -1,119 +0,0 @@
-/*
- * stmp378x: APBX register definitions
- *
- * Copyright (c) 2008 Freescale Semiconductor
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#ifndef _MACH_REGS_APBX
-#define _MACH_REGS_APBX
-
-#define REGS_APBX_BASE (STMP3XXX_REGS_BASE + 0x24000)
-#define REGS_APBX_PHYS 0x80024000
-#define REGS_APBX_SIZE 0x2000
-
-#define HW_APBX_CTRL0 0x0
-#define BM_APBX_CTRL0_CLKGATE 0x40000000
-#define BM_APBX_CTRL0_SFTRST 0x80000000
-
-#define HW_APBX_CTRL1 0x10
-
-#define HW_APBX_CTRL2 0x20
-
-#define HW_APBX_CHANNEL_CTRL 0x30
-#define BM_APBX_CHANNEL_CTRL_RESET_CHANNEL 0xFFFF0000
-#define BP_APBX_CHANNEL_CTRL_RESET_CHANNEL 16
-
-#define HW_APBX_DEVSEL 0x40
-
-#define HW_APBX_CH0_NXTCMDAR (0x110 + 0 * 0x70)
-#define HW_APBX_CH1_NXTCMDAR (0x110 + 1 * 0x70)
-#define HW_APBX_CH2_NXTCMDAR (0x110 + 2 * 0x70)
-#define HW_APBX_CH3_NXTCMDAR (0x110 + 3 * 0x70)
-#define HW_APBX_CH4_NXTCMDAR (0x110 + 4 * 0x70)
-#define HW_APBX_CH5_NXTCMDAR (0x110 + 5 * 0x70)
-#define HW_APBX_CH6_NXTCMDAR (0x110 + 6 * 0x70)
-#define HW_APBX_CH7_NXTCMDAR (0x110 + 7 * 0x70)
-#define HW_APBX_CH8_NXTCMDAR (0x110 + 8 * 0x70)
-#define HW_APBX_CH9_NXTCMDAR (0x110 + 9 * 0x70)
-#define HW_APBX_CH10_NXTCMDAR (0x110 + 10 * 0x70)
-#define HW_APBX_CH11_NXTCMDAR (0x110 + 11 * 0x70)
-#define HW_APBX_CH12_NXTCMDAR (0x110 + 12 * 0x70)
-#define HW_APBX_CH13_NXTCMDAR (0x110 + 13 * 0x70)
-#define HW_APBX_CH14_NXTCMDAR (0x110 + 14 * 0x70)
-#define HW_APBX_CH15_NXTCMDAR (0x110 + 15 * 0x70)
-
-#define HW_APBX_CHn_NXTCMDAR 0x110
-#define BM_APBX_CHn_CMD_COMMAND 0x00000003
-#define BP_APBX_CHn_CMD_COMMAND 0
-#define BV_APBX_CHn_CMD_COMMAND__NO_DMA_XFER 0
-#define BV_APBX_CHn_CMD_COMMAND__DMA_WRITE 1
-#define BV_APBX_CHn_CMD_COMMAND__DMA_READ 2
-#define BV_APBX_CHn_CMD_COMMAND__DMA_SENSE 3
-#define BM_APBX_CHn_CMD_CHAIN 0x00000004
-#define BM_APBX_CHn_CMD_IRQONCMPLT 0x00000008
-#define BM_APBX_CHn_CMD_SEMAPHORE 0x00000040
-#define BM_APBX_CHn_CMD_WAIT4ENDCMD 0x00000080
-#define BM_APBX_CHn_CMD_HALTONTERMINATE 0x00000100
-#define BM_APBX_CHn_CMD_CMDWORDS 0x0000F000
-#define BP_APBX_CHn_CMD_CMDWORDS 12
-#define BM_APBX_CHn_CMD_XFER_COUNT 0xFFFF0000
-#define BP_APBX_CHn_CMD_XFER_COUNT 16
-
-#define HW_APBX_CH0_BAR (0x130 + 0 * 0x70)
-#define HW_APBX_CH1_BAR (0x130 + 1 * 0x70)
-#define HW_APBX_CH2_BAR (0x130 + 2 * 0x70)
-#define HW_APBX_CH3_BAR (0x130 + 3 * 0x70)
-#define HW_APBX_CH4_BAR (0x130 + 4 * 0x70)
-#define HW_APBX_CH5_BAR (0x130 + 5 * 0x70)
-#define HW_APBX_CH6_BAR (0x130 + 6 * 0x70)
-#define HW_APBX_CH7_BAR (0x130 + 7 * 0x70)
-#define HW_APBX_CH8_BAR (0x130 + 8 * 0x70)
-#define HW_APBX_CH9_BAR (0x130 + 9 * 0x70)
-#define HW_APBX_CH10_BAR (0x130 + 10 * 0x70)
-#define HW_APBX_CH11_BAR (0x130 + 11 * 0x70)
-#define HW_APBX_CH12_BAR (0x130 + 12 * 0x70)
-#define HW_APBX_CH13_BAR (0x130 + 13 * 0x70)
-#define HW_APBX_CH14_BAR (0x130 + 14 * 0x70)
-#define HW_APBX_CH15_BAR (0x130 + 15 * 0x70)
-
-#define HW_APBX_CHn_BAR 0x130
-
-#define HW_APBX_CH0_SEMA (0x140 + 0 * 0x70)
-#define HW_APBX_CH1_SEMA (0x140 + 1 * 0x70)
-#define HW_APBX_CH2_SEMA (0x140 + 2 * 0x70)
-#define HW_APBX_CH3_SEMA (0x140 + 3 * 0x70)
-#define HW_APBX_CH4_SEMA (0x140 + 4 * 0x70)
-#define HW_APBX_CH5_SEMA (0x140 + 5 * 0x70)
-#define HW_APBX_CH6_SEMA (0x140 + 6 * 0x70)
-#define HW_APBX_CH7_SEMA (0x140 + 7 * 0x70)
-#define HW_APBX_CH8_SEMA (0x140 + 8 * 0x70)
-#define HW_APBX_CH9_SEMA (0x140 + 9 * 0x70)
-#define HW_APBX_CH10_SEMA (0x140 + 10 * 0x70)
-#define HW_APBX_CH11_SEMA (0x140 + 11 * 0x70)
-#define HW_APBX_CH12_SEMA (0x140 + 12 * 0x70)
-#define HW_APBX_CH13_SEMA (0x140 + 13 * 0x70)
-#define HW_APBX_CH14_SEMA (0x140 + 14 * 0x70)
-#define HW_APBX_CH15_SEMA (0x140 + 15 * 0x70)
-
-#define HW_APBX_CHn_SEMA 0x140
-#define BM_APBX_CHn_SEMA_INCREMENT_SEMA 0x000000FF
-#define BP_APBX_CHn_SEMA_INCREMENT_SEMA 0
-#define BM_APBX_CHn_SEMA_PHORE 0x00FF0000
-#define BP_APBX_CHn_SEMA_PHORE 16
-
-#endif
-
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-audioin.h b/arch/arm/mach-stmp378x/include/mach/regs-audioin.h
deleted file mode 100644
index 641ac61..0000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-audioin.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * stmp378x: AUDIOIN register definitions
- *
- * Copyright (c) 2008 Freescale Semiconductor
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#define REGS_AUDIOIN_BASE (STMP3XXX_REGS_BASE + 0x4C000)
-#define REGS_AUDIOIN_PHYS 0x8004C000
-#define REGS_AUDIOIN_SIZE 0x2000
-
-#define HW_AUDIOIN_CTRL 0x0
-#define BM_AUDIOIN_CTRL_RUN 0x00000001
-#define BP_AUDIOIN_CTRL_RUN 0
-#define BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN 0x00000002
-#define BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ 0x00000004
-#define BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008
-#define BM_AUDIOIN_CTRL_WORD_LENGTH 0x00000020
-#define BM_AUDIOIN_CTRL_CLKGATE 0x40000000
-#define BM_AUDIOIN_CTRL_SFTRST 0x80000000
-
-#define HW_AUDIOIN_STAT 0x10
-
-#define HW_AUDIOIN_ADCSRR 0x20
-
-#define HW_AUDIOIN_ADCVOLUME 0x30
-#define BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0x000000FF
-#define BP_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0
-#define BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT 0x00FF0000
-#define BP_AUDIOIN_ADCVOLUME_VOLUME_LEFT 16
-
-#define HW_AUDIOIN_ADCDEBUG 0x40
-
-#define HW_AUDIOIN_ADCVOL 0x50
-#define BM_AUDIOIN_ADCVOL_GAIN_RIGHT 0x0000000F
-#define BP_AUDIOIN_ADCVOL_GAIN_RIGHT 0
-#define BM_AUDIOIN_ADCVOL_SELECT_RIGHT 0x00000030
-#define BP_AUDIOIN_ADCVOL_SELECT_RIGHT 4
-#define BM_AUDIOIN_ADCVOL_GAIN_LEFT 0x00000F00
-#define BP_AUDIOIN_ADCVOL_GAIN_LEFT 8
-#define BM_AUDIOIN_ADCVOL_SELECT_LEFT 0x00003000
-#define BP_AUDIOIN_ADCVOL_SELECT_LEFT 12
-#define BM_AUDIOIN_ADCVOL_MUTE 0x01000000
-
-#define HW_AUDIOIN_MICLINE 0x60
-
-#define HW_AUDIOIN_ANACLKCTRL 0x70
-#define BM_AUDIOIN_ANACLKCTRL_CLKGATE 0x80000000
-
-#define HW_AUDIOIN_DATA 0x80
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-audioout.h b/arch/arm/mach-stmp378x/include/mach/regs-audioout.h
deleted file mode 100644
index f533e23..0000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-audioout.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * stmp378x: AUDIOOUT register definitions
- *
- * Copyright (c) 2008 Freescale Semiconductor
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#define REGS_AUDIOOUT_BASE (STMP3XXX_REGS_BASE + 0x48000)
-#define REGS_AUDIOOUT_PHYS 0x80048000
-#define REGS_AUDIOOUT_SIZE 0x2000
-
-#define HW_AUDIOOUT_CTRL 0x0
-#define BM_AUDIOOUT_CTRL_RUN 0x00000001
-#define BP_AUDIOOUT_CTRL_RUN 0
-#define BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN 0x00000002
-#define BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ 0x00000004
-#define BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008
-#define BM_AUDIOOUT_CTRL_WORD_LENGTH 0x00000040
-#define BM_AUDIOOUT_CTRL_CLKGATE 0x40000000
-#define BM_AUDIOOUT_CTRL_SFTRST 0x80000000
-
-#define HW_AUDIOOUT_STAT 0x10
-
-#define HW_AUDIOOUT_DACSRR 0x20
-#define BM_AUDIOOUT_DACSRR_SRC_FRAC 0x00001FFF
-#define BP_AUDIOOUT_DACSRR_SRC_FRAC 0
-#define BM_AUDIOOUT_DACSRR_SRC_INT 0x001F0000
-#define BP_AUDIOOUT_DACSRR_SRC_INT 16
-#define BM_AUDIOOUT_DACSRR_SRC_HOLD 0x07000000
-#define BP_AUDIOOUT_DACSRR_SRC_HOLD 24
-#define BM_AUDIOOUT_DACSRR_BASEMULT 0x70000000
-#define BP_AUDIOOUT_DACSRR_BASEMULT 28
-
-#define HW_AUDIOOUT_DACVOLUME 0x30
-#define BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT 0x00000100
-#define BM_AUDIOOUT_DACVOLUME_MUTE_LEFT 0x01000000
-#define BM_AUDIOOUT_DACVOLUME_EN_ZCD 0x02000000
-
-#define HW_AUDIOOUT_DACDEBUG 0x40
-
-#define HW_AUDIOOUT_HPVOL 0x50
-#define BM_AUDIOOUT_HPVOL_MUTE 0x01000000
-#define BM_AUDIOOUT_HPVOL_EN_MSTR_ZCD 0x02000000
-
-#define HW_AUDIOOUT_PWRDN 0x70
-#define BM_AUDIOOUT_PWRDN_HEADPHONE 0x00000001
-#define BP_AUDIOOUT_PWRDN_HEADPHONE 0
-#define BM_AUDIOOUT_PWRDN_CAPLESS 0x00000010
-#define BM_AUDIOOUT_PWRDN_ADC 0x00000100
-#define BM_AUDIOOUT_PWRDN_DAC 0x00001000
-#define BM_AUDIOOUT_PWRDN_RIGHT_ADC 0x00010000
-#define BM_AUDIOOUT_PWRDN_SPEAKER 0x01000000
-
-#define HW_AUDIOOUT_REFCTRL 0x80
-#define BM_AUDIOOUT_REFCTRL_VAG_VAL 0x000000F0
-#define BP_AUDIOOUT_REFCTRL_VAG_VAL 4
-#define BM_AUDIOOUT_REFCTRL_ADC_REFVAL 0x00000F00
-#define BP_AUDIOOUT_REFCTRL_ADC_REFVAL 8
-#define BM_AUDIOOUT_REFCTRL_ADJ_VAG 0x00001000
-#define BM_AUDIOOUT_REFCTRL_ADJ_ADC 0x00002000
-#define BM_AUDIOOUT_REFCTRL_BIAS_CTRL 0x00030000
-#define BP_AUDIOOUT_REFCTRL_BIAS_CTRL 16
-#define BM_AUDIOOUT_REFCTRL_LOW_PWR 0x00080000
-#define BM_AUDIOOUT_REFCTRL_VBG_ADJ 0x00700000
-#define BP_AUDIOOUT_REFCTRL_VBG_ADJ 20
-#define BM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS 0x01000000
-#define BM_AUDIOOUT_REFCTRL_RAISE_REF 0x02000000
-
-#define HW_AUDIOOUT_ANACTRL 0x90
-#define BM_AUDIOOUT_ANACTRL_HP_CLASSAB 0x00000010
-#define BM_AUDIOOUT_ANACTRL_HP_HOLD_GND 0x00000020
-
-#define HW_AUDIOOUT_TEST 0xA0
-#define BM_AUDIOOUT_TEST_HP_I1_ADJ 0x00C00000
-#define BP_AUDIOOUT_TEST_HP_I1_ADJ 22
-
-#define HW_AUDIOOUT_BISTCTRL 0xB0
-
-#define HW_AUDIOOUT_BISTSTAT0 0xC0
-
-#define HW_AUDIOOUT_BISTSTAT1 0xD0
-
-#define HW_AUDIOOUT_ANACLKCTRL 0xE0
-#define BM_AUDIOOUT_ANACLKCTRL_CLKGATE 0x80000000
-
-#define HW_AUDIOOUT_DATA 0xF0
-
-#define HW_AUDIOOUT_SPEAKERCTRL 0x100
-#define BM_AUDIOOUT_SPEAKERCTRL_MUTE 0x01000000
-
-#define HW_AUDIOOUT_VERSION 0x200
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-bch.h b/arch/arm/mach-stmp378x/include/mach/regs-bch.h
deleted file mode 100644
index 532d246..0000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-bch.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * stmp378x: BCH register definitions
- *
- * Copyright (c) 2008 Freescale Semiconductor
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#define REGS_BCH_BASE (STMP3XXX_REGS_BASE + 0xA000)
-#define REGS_BCH_PHYS 0x8000A000
-#define REGS_BCH_SIZE 0x2000
-
-#define HW_BCH_CTRL 0x0
-#define BM_BCH_CTRL_COMPLETE_IRQ 0x00000001
-#define BP_BCH_CTRL_COMPLETE_IRQ 0
-#define BM_BCH_CTRL_COMPLETE_IRQ_EN 0x00000100
-
-#define HW_BCH_STATUS0 0x10
-#define BM_BCH_STATUS0_UNCORRECTABLE 0x00000004
-#define BM_BCH_STATUS0_CORRECTED 0x00000008
-#define BM_BCH_STATUS0_STATUS_BLK0 0x0000FF00
-#define BP_BCH_STATUS0_STATUS_BLK0 8
-#define BM_BCH_STATUS0_COMPLETED_CE 0x000F0000
-#define BP_BCH_STATUS0_COMPLETED_CE 16
-
-#define HW_BCH_LAYOUTSELECT 0x70
-
-#define HW_BCH_FLASH0LAYOUT0 0x80
-#define BM_BCH_FLASH0LAYOUT0_DATA0_SIZE 0x00000FFF
-#define BP_BCH_FLASH0LAYOUT0_DATA0_SIZE 0
-#define BM_BCH_FLASH0LAYOUT0_ECC0 0x0000F000
-#define BP_BCH_FLASH0LAYOUT0_ECC0 12
-#define BM_BCH_FLASH0LAYOUT0_META_SIZE 0x00FF0000
-#define BP_BCH_FLASH0LAYOUT0_META_SIZE 16
-#define BM_BCH_FLASH0LAYOUT0_NBLOCKS 0xFF000000
-#define BP_BCH_FLASH0LAYOUT0_NBLOCKS 24
-#define BM_BCH_FLASH0LAYOUT1_DATAN_SIZE 0x00000FFF
-#define BP_BCH_FLASH0LAYOUT1_DATAN_SIZE 0
-#define BM_BCH_FLASH0LAYOUT1_ECCN 0x0000F000
-#define BP_BCH_FLASH0LAYOUT1_ECCN 12
-#define BM_BCH_FLASH0LAYOUT1_PAGE_SIZE 0xFFFF0000
-#define BP_BCH_FLASH0LAYOUT1_PAGE_SIZE 16
-
-#define HW_BCH_BLOCKNAME 0x150
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-clkctrl.h b/arch/arm/mach-stmp378x/include/mach/regs-clkctrl.h
deleted file mode 100644
index 7c546af..0000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-clkctrl.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * stmp378x: CLKCTRL register definitions
- *
- * Copyright (c) 2008 Freescale Semiconductor
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#ifndef _MACH_REGS_CLKCTRL
-#define _MACH_REGS_CLKCTRL
-
-#define REGS_CLKCTRL_BASE (STMP3XXX_REGS_BASE + 0x40000)
-#define REGS_CLKCTRL_PHYS 0x80040000
-#define REGS_CLKCTRL_SIZE 0x2000
-
-#define HW_CLKCTRL_PLLCTRL0 0x0
-#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x00040000
-
-#define HW_CLKCTRL_CPU 0x20
-#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F
-#define BP_CLKCTRL_CPU_DIV_CPU 0
-
-#define HW_CLKCTRL_HBUS 0x30
-#define BM_CLKCTRL_HBUS_DIV 0x0000001F
-#define BP_CLKCTRL_HBUS_DIV 0
-#define BM_CLKCTRL_HBUS_DIV_FRAC_EN 0x00000020
-
-#define HW_CLKCTRL_XBUS 0x40
-
-#define HW_CLKCTRL_XTAL 0x50
-#define BM_CLKCTRL_XTAL_DRI_CLK24M_GATE 0x10000000
-
-#define HW_CLKCTRL_PIX 0x60
-#define BM_CLKCTRL_PIX_DIV 0x00000FFF
-#define BP_CLKCTRL_PIX_DIV 0
-#define BM_CLKCTRL_PIX_CLKGATE 0x80000000
-
-#define HW_CLKCTRL_SSP 0x70
-
-#define HW_CLKCTRL_GPMI 0x80
-
-#define HW_CLKCTRL_SPDIF 0x90
-
-#define HW_CLKCTRL_EMI 0xA0
-#define BM_CLKCTRL_EMI_DIV_EMI 0x0000003F
-#define BP_CLKCTRL_EMI_DIV_EMI 0
-#define BM_CLKCTRL_EMI_DCC_RESYNC_ENABLE 0x00010000
-#define BM_CLKCTRL_EMI_BUSY_DCC_RESYNC 0x00020000
-#define BM_CLKCTRL_EMI_BUSY_REF_EMI 0x10000000
-#define BM_CLKCTRL_EMI_BUSY_REF_XTAL 0x20000000
-
-#define HW_CLKCTRL_IR 0xB0
-
-#define HW_CLKCTRL_SAIF 0xC0
-
-#define HW_CLKCTRL_TV 0xD0
-
-#define HW_CLKCTRL_ETM 0xE0
-
-#define HW_CLKCTRL_FRAC 0xF0
-#define BM_CLKCTRL_FRAC_EMIFRAC 0x00003F00
-#define BP_CLKCTRL_FRAC_EMIFRAC 8
-#define BM_CLKCTRL_FRAC_PIXFRAC 0x003F0000
-#define BP_CLKCTRL_FRAC_PIXFRAC 16
-#define BM_CLKCTRL_FRAC_CLKGATEPIX 0x00800000
-
-#define HW_CLKCTRL_FRAC1 0x100
-
-#define HW_CLKCTRL_CLKSEQ 0x110
-#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX 0x00000002
-
-#define HW_CLKCTRL_RESET 0x120
-#define BM_CLKCTRL_RESET_DIG 0x00000001
-#define BP_CLKCTRL_RESET_DIG 0
-
-#endif
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-dcp.h b/arch/arm/mach-stmp378x/include/mach/regs-dcp.h
deleted file mode 100644
index fdedd00..0000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-dcp.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * stmp378x: DCP register definitions
- *
- * Copyright (c) 2008 Freescale Semiconductor
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#define REGS_DCP_BASE (STMP3XXX_REGS_BASE + 0x28000)
-#define REGS_DCP_PHYS 0x80028000
-#define REGS_DCP_SIZE 0x2000
-
-#define HW_DCP_CTRL 0x0
-#define BM_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE 0x000000FF
-#define BP_DCP_CTRL_CHANNEL_INTERRUPT_ENABLE 0
-#define BM_DCP_CTRL_ENABLE_CONTEXT_CACHING 0x00400000
-#define BM_DCP_CTRL_GATHER_RESIDUAL_WRITES 0x00800000
-#define BM_DCP_CTRL_CLKGATE 0x40000000
-#define BM_DCP_CTRL_SFTRST 0x80000000
-
-#define HW_DCP_STAT 0x10
-#define BM_DCP_STAT_IRQ 0x0000000F
-#define BP_DCP_STAT_IRQ 0
-
-#define HW_DCP_CHANNELCTRL 0x20
-#define BM_DCP_CHANNELCTRL_ENABLE_CHANNEL 0x000000FF
-#define BP_DCP_CHANNELCTRL_ENABLE_CHANNEL 0
-
-#define HW_DCP_CONTEXT 0x50
-#define BM_DCP_PACKET1_INTERRUPT 0x00000001
-#define BP_DCP_PACKET1_INTERRUPT 0
-#define BM_DCP_PACKET1_DECR_SEMAPHORE 0x00000002
-#define BM_DCP_PACKET1_CHAIN 0x00000004
-#define BM_DCP_PACKET1_CHAIN_CONTIGUOUS 0x00000008
-#define BM_DCP_PACKET1_ENABLE_CIPHER 0x00000020
-#define BM_DCP_PACKET1_ENABLE_HASH 0x00000040
-#define BM_DCP_PACKET1_CIPHER_ENCRYPT 0x00000100
-#define BM_DCP_PACKET1_CIPHER_INIT 0x00000200
-#define BM_DCP_PACKET1_OTP_KEY 0x00000400
-#define BM_DCP_PACKET1_PAYLOAD_KEY 0x00000800
-#define BM_DCP_PACKET1_HASH_INIT 0x00001000
-#define BM_DCP_PACKET1_HASH_TERM 0x00002000
-#define BM_DCP_PACKET2_CIPHER_SELECT 0x0000000F
-#define BP_DCP_PACKET2_CIPHER_SELECT 0
-#define BM_DCP_PACKET2_CIPHER_MODE 0x000000F0
-#define BP_DCP_PACKET2_CIPHER_MODE 4
-#define BM_DCP_PACKET2_KEY_SELECT 0x0000FF00
-#define BP_DCP_PACKET2_KEY_SELECT 8
-#define BM_DCP_PACKET2_HASH_SELECT 0x000F0000
-#define BP_DCP_PACKET2_HASH_SELECT 16
-#define BM_DCP_PACKET2_CIPHER_CFG 0xFF000000
-#define BP_DCP_PACKET2_CIPHER_CFG 24
-
-#define HW_DCP_CH0CMDPTR (0x100 + 0 * 0x40)
-#define HW_DCP_CH1CMDPTR (0x100 + 1 * 0x40)
-#define HW_DCP_CH2CMDPTR (0x100 + 2 * 0x40)
-#define HW_DCP_CH3CMDPTR (0x100 + 3 * 0x40)
-
-#define HW_DCP_CHnCMDPTR 0x100
-
-#define HW_DCP_CH0SEMA (0x110 + 0 * 0x40)
-#define HW_DCP_CH1SEMA (0x110 + 1 * 0x40)
-#define HW_DCP_CH2SEMA (0x110 + 2 * 0x40)
-#define HW_DCP_CH3SEMA (0x110 + 3 * 0x40)
-
-#define HW_DCP_CHnSEMA 0x110
-#define BM_DCP_CHnSEMA_INCREMENT 0x000000FF
-#define BP_DCP_CHnSEMA_INCREMENT 0
-
-#define HW_DCP_CH0STAT (0x120 + 0 * 0x40)
-#define HW_DCP_CH1STAT (0x120 + 1 * 0x40)
-#define HW_DCP_CH2STAT (0x120 + 2 * 0x40)
-#define HW_DCP_CH3STAT (0x120 + 3 * 0x40)
-
-#define HW_DCP_CHnSTAT 0x120
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-digctl.h b/arch/arm/mach-stmp378x/include/mach/regs-digctl.h
deleted file mode 100644
index 5293005..0000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-digctl.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * stmp378x: DIGCTL register definitions
- *
- * Copyright (c) 2008 Freescale Semiconductor
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#define REGS_DIGCTL_BASE (STMP3XXX_REGS_BASE + 0x1C000)
-#define REGS_DIGCTL_PHYS 0x8001C000
-#define REGS_DIGCTL_SIZE 0x2000
-
-#define HW_DIGCTL_CTRL 0x0
-#define BM_DIGCTL_CTRL_USB_CLKGATE 0x00000004
-
-#define HW_DIGCTL_ARMCACHE 0x2B0
-#define BM_DIGCTL_ARMCACHE_ITAG_SS 0x00000003
-#define BP_DIGCTL_ARMCACHE_ITAG_SS 0
-#define BM_DIGCTL_ARMCACHE_DTAG_SS 0x00000030
-#define BP_DIGCTL_ARMCACHE_DTAG_SS 4
-#define BM_DIGCTL_ARMCACHE_CACHE_SS 0x00000300
-#define BP_DIGCTL_ARMCACHE_CACHE_SS 8
-#define BM_DIGCTL_ARMCACHE_DRTY_SS 0x00003000
-#define BP_DIGCTL_ARMCACHE_DRTY_SS 12
-#define BM_DIGCTL_ARMCACHE_VALID_SS 0x00030000
-#define BP_DIGCTL_ARMCACHE_VALID_SS 16
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-dram.h b/arch/arm/mach-stmp378x/include/mach/regs-dram.h
deleted file mode 100644
index 0285143..0000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-dram.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * stmp378x: DRAM register definitions
- *
- * Copyright (c) 2008 Freescale Semiconductor
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#define REGS_DRAM_BASE (STMP3XXX_REGS_BASE + 0xE0000)
-#define REGS_DRAM_PHYS 0x800E0000
-#define REGS_DRAM_SIZE 0x2000
-
-#define HW_DRAM_CTL06 0x18
-
-#define HW_DRAM_CTL08 0x20
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-dri.h b/arch/arm/mach-stmp378x/include/mach/regs-dri.h
deleted file mode 100644
index da25f7e..0000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-dri.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * stmp378x: DRI register definitions
- *
- * Copyright (c) 2008 Freescale Semiconductor
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#define REGS_DRI_BASE (STMP3XXX_REGS_BASE + 0x74000)
-#define REGS_DRI_PHYS 0x80074000
-#define REGS_DRI_SIZE 0x2000
-
-#define HW_DRI_CTRL 0x0
-#define BM_DRI_CTRL_RUN 0x00000001
-#define BP_DRI_CTRL_RUN 0
-#define BM_DRI_CTRL_ATTENTION_IRQ 0x00000002
-#define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ 0x00000004
-#define BM_DRI_CTRL_OVERFLOW_IRQ 0x00000008
-#define BM_DRI_CTRL_ATTENTION_IRQ_EN 0x00000200
-#define BM_DRI_CTRL_PILOT_SYNC_LOSS_IRQ_EN 0x00000400
-#define BM_DRI_CTRL_OVERFLOW_IRQ_EN 0x00000800
-#define BM_DRI_CTRL_REACQUIRE_PHASE 0x00008000
-#define BM_DRI_CTRL_STOP_ON_PILOT_ERROR 0x02000000
-#define BM_DRI_CTRL_STOP_ON_OFLOW_ERROR 0x04000000
-#define BM_DRI_CTRL_ENABLE_INPUTS 0x20000000
-#define BM_DRI_CTRL_CLKGATE 0x40000000
-#define BM_DRI_CTRL_SFTRST 0x80000000
-
-#define HW_DRI_TIMING 0x10
-#define BM_DRI_TIMING_GAP_DETECTION_INTERVAL 0x000000FF
-#define BP_DRI_TIMING_GAP_DETECTION_INTERVAL 0
-#define BM_DRI_TIMING_PILOT_REP_RATE 0x000F0000
-#define BP_DRI_TIMING_PILOT_REP_RATE 16
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-ecc8.h b/arch/arm/mach-stmp378x/include/mach/regs-ecc8.h
deleted file mode 100644
index cc353be..0000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-ecc8.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * stmp378x: ECC8 register definitions
- *
- * Copyright (c) 2008 Freescale Semiconductor
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#define REGS_ECC8_BASE (STMP3XXX_REGS_BASE + 0x8000)
-#define REGS_ECC8_PHYS 0x80008000
-#define REGS_ECC8_SIZE 0x2000
-
-#define HW_ECC8_CTRL 0x0
-#define BM_ECC8_CTRL_COMPLETE_IRQ 0x00000001
-#define BP_ECC8_CTRL_COMPLETE_IRQ 0
-#define BM_ECC8_CTRL_COMPLETE_IRQ_EN 0x00000100
-#define BM_ECC8_CTRL_AHBM_SFTRST 0x20000000
-
-#define HW_ECC8_STATUS0 0x10
-#define BM_ECC8_STATUS0_UNCORRECTABLE 0x00000004
-#define BM_ECC8_STATUS0_CORRECTED 0x00000008
-#define BM_ECC8_STATUS0_STATUS_AUX 0x00000F00
-#define BP_ECC8_STATUS0_STATUS_AUX 8
-#define BM_ECC8_STATUS0_COMPLETED_CE 0x000F0000
-#define BP_ECC8_STATUS0_COMPLETED_CE 16
-
-#define HW_ECC8_STATUS1 0x20
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-emi.h b/arch/arm/mach-stmp378x/include/mach/regs-emi.h
deleted file mode 100644
index 98773fc..0000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-emi.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * stmp378x: EMI register definitions
- *
- * Copyright (c) 2008 Freescale Semiconductor
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#define REGS_EMI_BASE (STMP3XXX_REGS_BASE + 0x20000)
-#define REGS_EMI_PHYS 0x80020000
-#define REGS_EMI_SIZE 0x2000
-
-#define HW_EMI_STAT 0x10
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-gpmi.h b/arch/arm/mach-stmp378x/include/mach/regs-gpmi.h
deleted file mode 100644
index 2cc8bbe..0000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-gpmi.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * stmp378x: GPMI register definitions
- *
- * Copyright (c) 2008 Freescale Semiconductor
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#define REGS_GPMI_BASE (STMP3XXX_REGS_BASE + 0xC000)
-#define REGS_GPMI_PHYS 0x8000C000
-#define REGS_GPMI_SIZE 0x2000
-
-#define HW_GPMI_CTRL0 0x0
-#define BM_GPMI_CTRL0_XFER_COUNT 0x0000FFFF
-#define BP_GPMI_CTRL0_XFER_COUNT 0
-#define BM_GPMI_CTRL0_CS 0x00300000
-#define BP_GPMI_CTRL0_CS 20
-#define BM_GPMI_CTRL0_LOCK_CS 0x00400000
-#define BM_GPMI_CTRL0_WORD_LENGTH 0x00800000
-#define BM_GPMI_CTRL0_ADDRESS 0x000E0000
-#define BP_GPMI_CTRL0_ADDRESS 17
-#define BV_GPMI_CTRL0_ADDRESS__NAND_DATA 0x0
-#define BV_GPMI_CTRL0_ADDRESS__NAND_CLE 0x1
-#define BV_GPMI_CTRL0_ADDRESS__NAND_ALE 0x2
-#define BM_GPMI_CTRL0_ADDRESS_INCREMENT 0x00010000
-#define BM_GPMI_CTRL0_COMMAND_MODE 0x03000000
-#define BP_GPMI_CTRL0_COMMAND_MODE 24
-#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE 0x0
-#define BV_GPMI_CTRL0_COMMAND_MODE__READ 0x1
-#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2
-#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY 0x3
-#define BM_GPMI_CTRL0_RUN 0x20000000
-#define BM_GPMI_CTRL0_CLKGATE 0x40000000
-#define BM_GPMI_CTRL0_SFTRST 0x80000000
-#define BM_GPMI_ECCCTRL_BUFFER_MASK 0x000001FF
-#define BP_GPMI_ECCCTRL_BUFFER_MASK 0
-#define BM_GPMI_ECCCTRL_ENABLE_ECC 0x00001000
-#define BM_GPMI_ECCCTRL_ECC_CMD 0x00006000
-#define BP_GPMI_ECCCTRL_ECC_CMD 13
-#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_4_BIT 0
-#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_4_BIT 1
-#define BV_GPMI_ECCCTRL_ECC_CMD__DECODE_8_BIT 2
-#define BV_GPMI_ECCCTRL_ECC_CMD__ENCODE_8_BIT 3
-
-#define HW_GPMI_CTRL1 0x60
-#define BM_GPMI_CTRL1_GPMI_MODE 0x00000001
-#define BP_GPMI_CTRL1_GPMI_MODE 0
-#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY 0x00000004
-#define BM_GPMI_CTRL1_DEV_RESET 0x00000008
-#define BM_GPMI_CTRL1_TIMEOUT_IRQ 0x00000200
-#define BM_GPMI_CTRL1_DEV_IRQ 0x00000400
-#define BM_GPMI_CTRL1_RDN_DELAY 0x0000F000
-#define BP_GPMI_CTRL1_RDN_DELAY 12
-#define BM_GPMI_CTRL1_BCH_MODE 0x00040000
-
-#define HW_GPMI_TIMING0 0x70
-#define BM_GPMI_TIMING0_DATA_SETUP 0x000000FF
-#define BP_GPMI_TIMING0_DATA_SETUP 0
-#define BM_GPMI_TIMING0_DATA_HOLD 0x0000FF00
-#define BP_GPMI_TIMING0_DATA_HOLD 8
-#define BM_GPMI_TIMING0_ADDRESS_SETUP 0x00FF0000
-#define BP_GPMI_TIMING0_ADDRESS_SETUP 16
-
-#define HW_GPMI_TIMING1 0x80
-#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 0xFFFF0000
-#define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 16
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-i2c.h b/arch/arm/mach-stmp378x/include/mach/regs-i2c.h
deleted file mode 100644
index 13a234c..0000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-i2c.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * stmp378x: I2C register definitions
- *
- * Copyright (c) 2008 Freescale Semiconductor
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#define REGS_I2C_BASE (STMP3XXX_REGS_BASE + 0x58000)
-#define REGS_I2C_PHYS 0x80058000
-#define REGS_I2C_SIZE 0x2000
-
-#define HW_I2C_CTRL0 0x0
-#define BM_I2C_CTRL0_XFER_COUNT 0x0000FFFF
-#define BP_I2C_CTRL0_XFER_COUNT 0
-#define BM_I2C_CTRL0_DIRECTION 0x00010000
-#define BM_I2C_CTRL0_MASTER_MODE 0x00020000
-#define BM_I2C_CTRL0_PRE_SEND_START 0x00080000
-#define BM_I2C_CTRL0_POST_SEND_STOP 0x00100000
-#define BM_I2C_CTRL0_RETAIN_CLOCK 0x00200000
-#define BM_I2C_CTRL0_SEND_NAK_ON_LAST 0x02000000
-#define BM_I2C_CTRL0_CLKGATE 0x40000000
-#define BM_I2C_CTRL0_SFTRST 0x80000000
-
-#define HW_I2C_TIMING0 0x10
-
-#define HW_I2C_TIMING1 0x20
-
-#define HW_I2C_TIMING2 0x30
-
-#define HW_I2C_CTRL1 0x40
-#define BM_I2C_CTRL1_SLAVE_IRQ 0x00000001
-#define BP_I2C_CTRL1_SLAVE_IRQ 0
-#define BM_I2C_CTRL1_SLAVE_STOP_IRQ 0x00000002
-#define BM_I2C_CTRL1_MASTER_LOSS_IRQ 0x00000004
-#define BM_I2C_CTRL1_EARLY_TERM_IRQ 0x00000008
-#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 0x00000010
-#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ 0x00000020
-#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 0x00000040
-#define BM_I2C_CTRL1_BUS_FREE_IRQ 0x00000080
-#define BM_I2C_CTRL1_CLR_GOT_A_NAK 0x10000000
-
-#define HW_I2C_VERSION 0x90
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-icoll.h b/arch/arm/mach-stmp378x/include/mach/regs-icoll.h
deleted file mode 100644
index f996e80..0000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-icoll.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * stmp378x: ICOLL register definitions
- *
- * Copyright (c) 2008 Freescale Semiconductor
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#ifndef _MACH_REGS_ICOLL
-#define _MACH_REGS_ICOLL
-
-#define REGS_ICOLL_BASE (STMP3XXX_REGS_BASE + 0x0)
-#define REGS_ICOLL_PHYS 0x80000000
-#define REGS_ICOLL_SIZE 0x2000
-
-#define HW_ICOLL_VECTOR 0x0
-
-#define HW_ICOLL_LEVELACK 0x10
-#define BM_ICOLL_LEVELACK_IRQLEVELACK 0x0000000F
-#define BP_ICOLL_LEVELACK_IRQLEVELACK 0
-
-#define HW_ICOLL_CTRL 0x20
-#define BM_ICOLL_CTRL_CLKGATE 0x40000000
-#define BM_ICOLL_CTRL_SFTRST 0x80000000
-
-#define HW_ICOLL_STAT 0x70
-
-#define HW_ICOLL_INTERRUPTn 0x120
-
-#define HW_ICOLL_INTERRUPTn 0x120
-#define BM_ICOLL_INTERRUPTn_ENABLE 0x00000004
-
-#endif
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-ir.h b/arch/arm/mach-stmp378x/include/mach/regs-ir.h
deleted file mode 100644
index a5b4ef1..0000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-ir.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * stmp378x: IR register definitions
- *
- * Copyright (c) 2008 Freescale Semiconductor
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#define REGS_IR_BASE (STMP3XXX_REGS_BASE + 0x78000)
-#define REGS_IR_PHYS 0x80078000
-#define REGS_IR_SIZE 0x2000
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-lcdif.h b/arch/arm/mach-stmp378x/include/mach/regs-lcdif.h
deleted file mode 100644
index 9cdbef4..0000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-lcdif.h
+++ /dev/null
@@ -1,195 +0,0 @@
-/*
- * stmp378x: LCDIF register definitions
- *
- * Copyright (c) 2008 Freescale Semiconductor
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#define REGS_LCDIF_BASE (STMP3XXX_REGS_BASE + 0x30000)
-#define REGS_LCDIF_PHYS 0x80030000
-#define REGS_LCDIF_SIZE 0x2000
-
-#define HW_LCDIF_CTRL 0x0
-#define BM_LCDIF_CTRL_RUN 0x00000001
-#define BP_LCDIF_CTRL_RUN 0
-#define BM_LCDIF_CTRL_LCDIF_MASTER 0x00000020
-#define BM_LCDIF_CTRL_RGB_TO_YCBCR422_CSC 0x00000080
-#define BM_LCDIF_CTRL_WORD_LENGTH 0x00000300
-#define BP_LCDIF_CTRL_WORD_LENGTH 8
-#define BM_LCDIF_CTRL_LCD_DATABUS_WIDTH 0x00000C00
-#define BP_LCDIF_CTRL_LCD_DATABUS_WIDTH 10
-#define BM_LCDIF_CTRL_INPUT_DATA_SWIZZLE 0x0000C000
-#define BP_LCDIF_CTRL_INPUT_DATA_SWIZZLE 14
-#define BM_LCDIF_CTRL_DATA_SELECT 0x00010000
-#define BM_LCDIF_CTRL_DOTCLK_MODE 0x00020000
-#define BM_LCDIF_CTRL_VSYNC_MODE 0x00040000
-#define BM_LCDIF_CTRL_BYPASS_COUNT 0x00080000
-#define BM_LCDIF_CTRL_DVI_MODE 0x00100000
-#define BM_LCDIF_CTRL_SHIFT_NUM_BITS 0x03E00000
-#define BP_LCDIF_CTRL_SHIFT_NUM_BITS 21
-#define BM_LCDIF_CTRL_DATA_SHIFT_DIR 0x04000000
-#define BM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE 0x08000000
-#define BM_LCDIF_CTRL_CLKGATE 0x40000000
-#define BM_LCDIF_CTRL_SFTRST 0x80000000
-
-#define HW_LCDIF_CTRL1 0x10
-#define BM_LCDIF_CTRL1_RESET 0x00000001
-#define BP_LCDIF_CTRL1_RESET 0
-#define BM_LCDIF_CTRL1_MODE86 0x00000002
-#define BM_LCDIF_CTRL1_BUSY_ENABLE 0x00000004
-#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ 0x00000100
-#define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ 0x00000200
-#define BM_LCDIF_CTRL1_UNDERFLOW_IRQ 0x00000400
-#define BM_LCDIF_CTRL1_OVERFLOW_IRQ 0x00000800
-#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN 0x00001000
-#define BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT 0x000F0000
-#define BP_LCDIF_CTRL1_BYTE_PACKING_FORMAT 16
-#define BM_LCDIF_CTRL1_INTERLACE_FIELDS 0x00800000
-#define BM_LCDIF_CTRL1_RECOVER_ON_UNDERFLOW 0x01000000
-
-#define HW_LCDIF_TRANSFER_COUNT 0x20
-#define BM_LCDIF_TRANSFER_COUNT_H_COUNT 0x0000FFFF
-#define BP_LCDIF_TRANSFER_COUNT_H_COUNT 0
-#define BM_LCDIF_TRANSFER_COUNT_V_COUNT 0xFFFF0000
-#define BP_LCDIF_TRANSFER_COUNT_V_COUNT 16
-
-#define HW_LCDIF_CUR_BUF 0x30
-
-#define HW_LCDIF_NEXT_BUF 0x40
-
-#define HW_LCDIF_TIMING 0x60
-
-#define HW_LCDIF_VDCTRL0 0x70
-#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH 0x0003FFFF
-#define BP_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH 0
-#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT 0x00100000
-#define BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT 0x00200000
-#define BM_LCDIF_VDCTRL0_ENABLE_POL 0x01000000
-#define BM_LCDIF_VDCTRL0_DOTCLK_POL 0x02000000
-#define BM_LCDIF_VDCTRL0_HSYNC_POL 0x04000000
-#define BM_LCDIF_VDCTRL0_VSYNC_POL 0x08000000
-#define BM_LCDIF_VDCTRL0_ENABLE_PRESENT 0x10000000
-#define BM_LCDIF_VDCTRL0_VSYNC_OEB 0x20000000
-
-#define HW_LCDIF_VDCTRL1 0x80
-#define BM_LCDIF_VDCTRL1_VSYNC_PERIOD 0xFFFFFFFF
-#define BP_LCDIF_VDCTRL1_VSYNC_PERIOD 0
-
-#define HW_LCDIF_VDCTRL2 0x90
-#define BM_LCDIF_VDCTRL2_HSYNC_PERIOD 0x0003FFFF
-#define BP_LCDIF_VDCTRL2_HSYNC_PERIOD 0
-#define BM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 0xFF000000
-#define BP_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 24
-
-#define HW_LCDIF_VDCTRL3 0xA0
-#define BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0x0000FFFF
-#define BP_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0
-#define BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 0x0FFF0000
-#define BP_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 16
-
-#define HW_LCDIF_VDCTRL4 0xB0
-#define BM_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT 0x0003FFFF
-#define BP_LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT 0
-#define BM_LCDIF_VDCTRL4_SYNC_SIGNALS_ON 0x00040000
-
-#define HW_LCDIF_DVICTRL0 0xC0
-#define BM_LCDIF_DVICTRL0_V_LINES_CNT 0x000003FF
-#define BP_LCDIF_DVICTRL0_V_LINES_CNT 0
-#define BM_LCDIF_DVICTRL0_H_BLANKING_CNT 0x000FFC00
-#define BP_LCDIF_DVICTRL0_H_BLANKING_CNT 10
-#define BM_LCDIF_DVICTRL0_H_ACTIVE_CNT 0x7FF00000
-#define BP_LCDIF_DVICTRL0_H_ACTIVE_CNT 20
-
-#define HW_LCDIF_DVICTRL1 0xD0
-#define BM_LCDIF_DVICTRL1_F2_START_LINE 0x000003FF
-#define BP_LCDIF_DVICTRL1_F2_START_LINE 0
-#define BM_LCDIF_DVICTRL1_F1_END_LINE 0x000FFC00
-#define BP_LCDIF_DVICTRL1_F1_END_LINE 10
-#define BM_LCDIF_DVICTRL1_F1_START_LINE 0x3FF00000
-#define BP_LCDIF_DVICTRL1_F1_START_LINE 20
-
-#define HW_LCDIF_DVICTRL2 0xE0
-#define BM_LCDIF_DVICTRL2_V1_BLANK_END_LINE 0x000003FF
-#define BP_LCDIF_DVICTRL2_V1_BLANK_END_LINE 0
-#define BM_LCDIF_DVICTRL2_V1_BLANK_START_LINE 0x000FFC00
-#define BP_LCDIF_DVICTRL2_V1_BLANK_START_LINE 10
-#define BM_LCDIF_DVICTRL2_F2_END_LINE 0x3FF00000
-#define BP_LCDIF_DVICTRL2_F2_END_LINE 20
-
-#define HW_LCDIF_DVICTRL3 0xF0
-#define BM_LCDIF_DVICTRL3_V2_BLANK_END_LINE 0x000003FF
-#define BP_LCDIF_DVICTRL3_V2_BLANK_END_LINE 0
-#define BM_LCDIF_DVICTRL3_V2_BLANK_START_LINE 0x03FF0000
-#define BP_LCDIF_DVICTRL3_V2_BLANK_START_LINE 16
-
-#define HW_LCDIF_DVICTRL4 0x100
-#define BM_LCDIF_DVICTRL4_H_FILL_CNT 0x000000FF
-#define BP_LCDIF_DVICTRL4_H_FILL_CNT 0
-#define BM_LCDIF_DVICTRL4_CR_FILL_VALUE 0x0000FF00
-#define BP_LCDIF_DVICTRL4_CR_FILL_VALUE 8
-#define BM_LCDIF_DVICTRL4_CB_FILL_VALUE 0x00FF0000
-#define BP_LCDIF_DVICTRL4_CB_FILL_VALUE 16
-#define BM_LCDIF_DVICTRL4_Y_FILL_VALUE 0xFF000000
-#define BP_LCDIF_DVICTRL4_Y_FILL_VALUE 24
-
-#define HW_LCDIF_CSC_COEFF0 0x110
-#define BM_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER 0x00000003
-#define BP_LCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER 0
-#define BM_LCDIF_CSC_COEFF0_C0 0x03FF0000
-#define BP_LCDIF_CSC_COEFF0_C0 16
-
-#define HW_LCDIF_CSC_COEFF1 0x120
-#define BM_LCDIF_CSC_COEFF1_C1 0x000003FF
-#define BP_LCDIF_CSC_COEFF1_C1 0
-#define BM_LCDIF_CSC_COEFF1_C2 0x03FF0000
-#define BP_LCDIF_CSC_COEFF1_C2 16
-
-#define HW_LCDIF_CSC_COEFF2 0x130
-#define BM_LCDIF_CSC_COEFF2_C3 0x000003FF
-#define BP_LCDIF_CSC_COEFF2_C3 0
-#define BM_LCDIF_CSC_COEFF2_C4 0x03FF0000
-#define BP_LCDIF_CSC_COEFF2_C4 16
-
-#define HW_LCDIF_CSC_COEFF3 0x140
-#define BM_LCDIF_CSC_COEFF3_C5 0x000003FF
-#define BP_LCDIF_CSC_COEFF3_C5 0
-#define BM_LCDIF_CSC_COEFF3_C6 0x03FF0000
-#define BP_LCDIF_CSC_COEFF3_C6 16
-
-#define HW_LCDIF_CSC_COEFF4 0x150
-#define BM_LCDIF_CSC_COEFF4_C7 0x000003FF
-#define BP_LCDIF_CSC_COEFF4_C7 0
-#define BM_LCDIF_CSC_COEFF4_C8 0x03FF0000
-#define BP_LCDIF_CSC_COEFF4_C8 16
-
-#define HW_LCDIF_CSC_OFFSET 0x160
-#define BM_LCDIF_CSC_OFFSET_Y_OFFSET 0x000001FF
-#define BP_LCDIF_CSC_OFFSET_Y_OFFSET 0
-#define BM_LCDIF_CSC_OFFSET_CBCR_OFFSET 0x01FF0000
-#define BP_LCDIF_CSC_OFFSET_CBCR_OFFSET 16
-
-#define HW_LCDIF_CSC_LIMIT 0x170
-#define BM_LCDIF_CSC_LIMIT_Y_MAX 0x000000FF
-#define BP_LCDIF_CSC_LIMIT_Y_MAX 0
-#define BM_LCDIF_CSC_LIMIT_Y_MIN 0x0000FF00
-#define BP_LCDIF_CSC_LIMIT_Y_MIN 8
-#define BM_LCDIF_CSC_LIMIT_CBCR_MAX 0x00FF0000
-#define BP_LCDIF_CSC_LIMIT_CBCR_MAX 16
-#define BM_LCDIF_CSC_LIMIT_CBCR_MIN 0xFF000000
-#define BP_LCDIF_CSC_LIMIT_CBCR_MIN 24
-
-#define HW_LCDIF_STAT 0x1D0
-#define BM_LCDIF_STAT_TXFIFO_EMPTY 0x04000000
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-lradc.h b/arch/arm/mach-stmp378x/include/mach/regs-lradc.h
deleted file mode 100644
index cb8cb06..0000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-lradc.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * stmp378x: LRADC register definitions
- *
- * Copyright (c) 2008 Freescale Semiconductor
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#define REGS_LRADC_BASE (STMP3XXX_REGS_BASE + 0x50000)
-#define REGS_LRADC_PHYS 0x80050000
-#define REGS_LRADC_SIZE 0x2000
-
-#define HW_LRADC_CTRL0 0x0
-#define BM_LRADC_CTRL0_SCHEDULE 0x000000FF
-#define BP_LRADC_CTRL0_SCHEDULE 0
-#define BM_LRADC_CTRL0_XPLUS_ENABLE 0x00010000
-#define BM_LRADC_CTRL0_YPLUS_ENABLE 0x00020000
-#define BM_LRADC_CTRL0_XMINUS_ENABLE 0x00040000
-#define BM_LRADC_CTRL0_YMINUS_ENABLE 0x00080000
-#define BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE 0x00100000
-#define BM_LRADC_CTRL0_ONCHIP_GROUNDREF 0x00200000
-#define BM_LRADC_CTRL0_CLKGATE 0x40000000
-#define BM_LRADC_CTRL0_SFTRST 0x80000000
-
-#define HW_LRADC_CTRL1 0x10
-#define BM_LRADC_CTRL1_LRADC0_IRQ 0x00000001
-#define BP_LRADC_CTRL1_LRADC0_IRQ 0
-#define BM_LRADC_CTRL1_LRADC5_IRQ 0x00000020
-#define BM_LRADC_CTRL1_LRADC6_IRQ 0x00000040
-#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ 0x00000100
-#define BM_LRADC_CTRL1_LRADC0_IRQ_EN 0x00010000
-#define BM_LRADC_CTRL1_LRADC5_IRQ_EN 0x00200000
-#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN 0x01000000
-
-#define HW_LRADC_CTRL2 0x20
-#define BM_LRADC_CTRL2_BL_BRIGHTNESS 0x001F0000
-#define BP_LRADC_CTRL2_BL_BRIGHTNESS 16
-#define BM_LRADC_CTRL2_BL_MUX_SELECT 0x00200000
-#define BM_LRADC_CTRL2_BL_ENABLE 0x00400000
-#define BM_LRADC_CTRL2_DIVIDE_BY_TWO 0xFF000000
-#define BP_LRADC_CTRL2_DIVIDE_BY_TWO 24
-
-#define HW_LRADC_CTRL3 0x30
-#define BM_LRADC_CTRL3_CYCLE_TIME 0x00000300
-#define BP_LRADC_CTRL3_CYCLE_TIME 8
-
-#define HW_LRADC_STATUS 0x40
-#define BM_LRADC_STATUS_TOUCH_DETECT_RAW 0x00000001
-#define BP_LRADC_STATUS_TOUCH_DETECT_RAW 0
-
-#define HW_LRADC_CH0 (0x50 + 0 * 0x10)
-#define HW_LRADC_CH1 (0x50 + 1 * 0x10)
-#define HW_LRADC_CH2 (0x50 + 2 * 0x10)
-#define HW_LRADC_CH3 (0x50 + 3 * 0x10)
-#define HW_LRADC_CH4 (0x50 + 4 * 0x10)
-#define HW_LRADC_CH5 (0x50 + 5 * 0x10)
-#define HW_LRADC_CH6 (0x50 + 6 * 0x10)
-#define HW_LRADC_CH7 (0x50 + 7 * 0x10)
-
-#define HW_LRADC_CHn 0x50
-#define BM_LRADC_CHn_VALUE 0x0003FFFF
-#define BP_LRADC_CHn_VALUE 0
-#define BM_LRADC_CHn_NUM_SAMPLES 0x1F000000
-#define BP_LRADC_CHn_NUM_SAMPLES 24
-#define BM_LRADC_CHn_ACCUMULATE 0x20000000
-
-#define HW_LRADC_DELAY0 (0xD0 + 0 * 0x10)
-#define HW_LRADC_DELAY1 (0xD0 + 1 * 0x10)
-#define HW_LRADC_DELAY2 (0xD0 + 2 * 0x10)
-#define HW_LRADC_DELAY3 (0xD0 + 3 * 0x10)
-
-#define HW_LRADC_DELAYn 0xD0
-#define BM_LRADC_DELAYn_DELAY 0x000007FF
-#define BP_LRADC_DELAYn_DELAY 0
-#define BM_LRADC_DELAYn_LOOP_COUNT 0x0000F800
-#define BP_LRADC_DELAYn_LOOP_COUNT 11
-#define BM_LRADC_DELAYn_TRIGGER_DELAYS 0x000F0000
-#define BP_LRADC_DELAYn_TRIGGER_DELAYS 16
-#define BM_LRADC_DELAYn_KICK 0x00100000
-#define BM_LRADC_DELAYn_TRIGGER_LRADCS 0xFF000000
-#define BP_LRADC_DELAYn_TRIGGER_LRADCS 24
-
-#define HW_LRADC_CTRL4 0x140
-#define BM_LRADC_CTRL4_LRADC6SELECT 0x0F000000
-#define BP_LRADC_CTRL4_LRADC6SELECT 24
-#define BM_LRADC_CTRL4_LRADC7SELECT 0xF0000000
-#define BP_LRADC_CTRL4_LRADC7SELECT 28
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-ocotp.h b/arch/arm/mach-stmp378x/include/mach/regs-ocotp.h
deleted file mode 100644
index f0af64d..0000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-ocotp.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * stmp378x: OCOTP register definitions
- *
- * Copyright (c) 2008 Freescale Semiconductor
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#define REGS_OCOTP_BASE (STMP3XXX_REGS_BASE + 0x2C000)
-#define REGS_OCOTP_PHYS 0x8002C000
-#define REGS_OCOTP_SIZE 0x2000
-
-#define HW_OCOTP_CTRL 0x0
-#define BM_OCOTP_CTRL_BUSY 0x00000100
-#define BM_OCOTP_CTRL_ERROR 0x00000200
-#define BM_OCOTP_CTRL_RD_BANK_OPEN 0x00001000
-#define BM_OCOTP_CTRL_RELOAD_SHADOWS 0x00002000
-#define BM_OCOTP_CTRL_WR_UNLOCK 0xFFFF0000
-#define BP_OCOTP_CTRL_WR_UNLOCK 16
-
-#define HW_OCOTP_DATA 0x10
-
-#define HW_OCOTP_CUST0 (0x20 + 0 * 0x10)
-#define HW_OCOTP_CUST1 (0x20 + 1 * 0x10)
-#define HW_OCOTP_CUST2 (0x20 + 2 * 0x10)
-#define HW_OCOTP_CUST3 (0x20 + 3 * 0x10)
-
-#define HW_OCOTP_CUSTn 0x20
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-pinctrl.h b/arch/arm/mach-stmp378x/include/mach/regs-pinctrl.h
deleted file mode 100644
index 50d90ea..0000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-pinctrl.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * stmp378x: PINCTRL register definitions
- *
- * Copyright (c) 2008 Freescale Semiconductor
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#ifndef _MACH_REGS_PINCTRL
-#define _MACH_REGS_PINCTRL
-
-#define REGS_PINCTRL_BASE (STMP3XXX_REGS_BASE + 0x18000)
-#define REGS_PINCTRL_PHYS 0x80018000
-#define REGS_PINCTRL_SIZE 0x2000
-
-#define HW_PINCTRL_MUXSEL0 0x100
-#define HW_PINCTRL_MUXSEL1 0x110
-#define HW_PINCTRL_MUXSEL2 0x120
-#define HW_PINCTRL_MUXSEL3 0x130
-#define HW_PINCTRL_MUXSEL4 0x140
-#define HW_PINCTRL_MUXSEL5 0x150
-#define HW_PINCTRL_MUXSEL6 0x160
-#define HW_PINCTRL_MUXSEL7 0x170
-
-#define HW_PINCTRL_DRIVE0 0x200
-#define HW_PINCTRL_DRIVE1 0x210
-#define HW_PINCTRL_DRIVE2 0x220
-#define HW_PINCTRL_DRIVE3 0x230
-#define HW_PINCTRL_DRIVE4 0x240
-#define HW_PINCTRL_DRIVE5 0x250
-#define HW_PINCTRL_DRIVE6 0x260
-#define HW_PINCTRL_DRIVE7 0x270
-#define HW_PINCTRL_DRIVE8 0x280
-#define HW_PINCTRL_DRIVE9 0x290
-#define HW_PINCTRL_DRIVE10 0x2A0
-#define HW_PINCTRL_DRIVE11 0x2B0
-#define HW_PINCTRL_DRIVE12 0x2C0
-#define HW_PINCTRL_DRIVE13 0x2D0
-#define HW_PINCTRL_DRIVE14 0x2E0
-
-#define HW_PINCTRL_PULL0 0x400
-#define HW_PINCTRL_PULL1 0x410
-#define HW_PINCTRL_PULL2 0x420
-#define HW_PINCTRL_PULL3 0x430
-
-#define HW_PINCTRL_DOUT0 0x500
-#define HW_PINCTRL_DOUT1 0x510
-#define HW_PINCTRL_DOUT2 0x520
-
-#define HW_PINCTRL_DIN0 0x600
-#define HW_PINCTRL_DIN1 0x610
-#define HW_PINCTRL_DIN2 0x620
-
-#define HW_PINCTRL_DOE0 0x700
-#define HW_PINCTRL_DOE1 0x710
-#define HW_PINCTRL_DOE2 0x720
-
-#define HW_PINCTRL_PIN2IRQ0 0x800
-#define HW_PINCTRL_PIN2IRQ1 0x810
-#define HW_PINCTRL_PIN2IRQ2 0x820
-
-#define HW_PINCTRL_IRQEN0 0x900
-#define HW_PINCTRL_IRQEN1 0x910
-#define HW_PINCTRL_IRQEN2 0x920
-
-#define HW_PINCTRL_IRQLEVEL0 0xA00
-#define HW_PINCTRL_IRQLEVEL1 0xA10
-#define HW_PINCTRL_IRQLEVEL2 0xA20
-
-#define HW_PINCTRL_IRQPOL0 0xB00
-#define HW_PINCTRL_IRQPOL1 0xB10
-#define HW_PINCTRL_IRQPOL2 0xB20
-
-#define HW_PINCTRL_IRQSTAT0 0xC00
-#define HW_PINCTRL_IRQSTAT1 0xC10
-#define HW_PINCTRL_IRQSTAT2 0xC20
-
-#endif
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-power.h b/arch/arm/mach-stmp378x/include/mach/regs-power.h
deleted file mode 100644
index e454c83..0000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-power.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * stmp378x: POWER register definitions
- *
- * Copyright (c) 2008 Freescale Semiconductor
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#ifndef _MACH_REGS_POWER
-#define _MACH_REGS_POWER
-
-#define REGS_POWER_BASE (STMP3XXX_REGS_BASE + 0x44000)
-#define REGS_POWER_PHYS 0x80044000
-#define REGS_POWER_SIZE 0x2000
-
-#define HW_POWER_CTRL 0x0
-#define BM_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO 0x00000001
-#define BP_POWER_CTRL_ENIRQ_VDD5V_GT_VDDIO 0
-#define BM_POWER_CTRL_ENIRQ_PSWITCH 0x00020000
-#define BM_POWER_CTRL_PSWITCH_IRQ 0x00100000
-#define BM_POWER_CTRL_CLKGATE 0x40000000
-
-#define HW_POWER_5VCTRL 0x10
-#define BM_POWER_5VCTRL_ENABLE_LINREG_ILIMIT 0x00000040
-
-#define HW_POWER_MINPWR 0x20
-
-#define HW_POWER_CHARGE 0x30
-
-#define HW_POWER_VDDDCTRL 0x40
-
-#define HW_POWER_VDDACTRL 0x50
-
-#define HW_POWER_VDDIOCTRL 0x60
-#define BM_POWER_VDDIOCTRL_TRG 0x0000001F
-#define BP_POWER_VDDIOCTRL_TRG 0
-
-#define HW_POWER_STS 0xC0
-#define BM_POWER_STS_VBUSVALID 0x00000002
-#define BM_POWER_STS_BVALID 0x00000004
-#define BM_POWER_STS_AVALID 0x00000008
-#define BM_POWER_STS_DC_OK 0x00000200
-
-#define HW_POWER_RESET 0x100
-
-#define HW_POWER_DEBUG 0x110
-#define BM_POWER_DEBUG_BVALIDPIOLOCK 0x00000002
-#define BM_POWER_DEBUG_AVALIDPIOLOCK 0x00000004
-#define BM_POWER_DEBUG_VBUSVALIDPIOLOCK 0x00000008
-
-#endif
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-pwm.h b/arch/arm/mach-stmp378x/include/mach/regs-pwm.h
deleted file mode 100644
index 0d0f9e5..0000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-pwm.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * stmp378x: PWM register definitions
- *
- * Copyright (c) 2008 Freescale Semiconductor
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#define REGS_PWM_BASE (STMP3XXX_REGS_BASE + 0x64000)
-#define REGS_PWM_PHYS 0x80064000
-#define REGS_PWM_SIZE 0x2000
-
-#define HW_PWM_CTRL 0x0
-#define BM_PWM_CTRL_PWM2_ENABLE 0x00000004
-#define BM_PWM_CTRL_PWM2_ANA_CTRL_ENABLE 0x00000020
-
-#define HW_PWM_ACTIVE0 (0x10 + 0 * 0x20)
-#define HW_PWM_ACTIVE1 (0x10 + 1 * 0x20)
-#define HW_PWM_ACTIVE2 (0x10 + 2 * 0x20)
-#define HW_PWM_ACTIVE3 (0x10 + 3 * 0x20)
-
-#define HW_PWM_ACTIVEn 0x10
-#define BM_PWM_ACTIVEn_ACTIVE 0x0000FFFF
-#define BP_PWM_ACTIVEn_ACTIVE 0
-#define BM_PWM_ACTIVEn_INACTIVE 0xFFFF0000
-#define BP_PWM_ACTIVEn_INACTIVE 16
-
-#define HW_PWM_PERIOD0 (0x20 + 0 * 0x20)
-#define HW_PWM_PERIOD1 (0x20 + 1 * 0x20)
-#define HW_PWM_PERIOD2 (0x20 + 2 * 0x20)
-#define HW_PWM_PERIOD3 (0x20 + 3 * 0x20)
-
-#define HW_PWM_PERIODn 0x20
-#define BM_PWM_PERIODn_PERIOD 0x0000FFFF
-#define BP_PWM_PERIODn_PERIOD 0
-#define BM_PWM_PERIODn_ACTIVE_STATE 0x00030000
-#define BP_PWM_PERIODn_ACTIVE_STATE 16
-#define BM_PWM_PERIODn_INACTIVE_STATE 0x000C0000
-#define BP_PWM_PERIODn_INACTIVE_STATE 18
-#define BM_PWM_PERIODn_CDIV 0x00700000
-#define BP_PWM_PERIODn_CDIV 20
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-pxp.h b/arch/arm/mach-stmp378x/include/mach/regs-pxp.h
deleted file mode 100644
index 54d2978..0000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-pxp.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
- * stmp378x: PXP register definitions
- *
- * Copyright (c) 2008 Freescale Semiconductor
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#define REGS_PXP_BASE (STMP3XXX_REGS_BASE + 0x2A000)
-#define REGS_PXP_PHYS 0x8002A000
-#define REGS_PXP_SIZE 0x2000
-
-#define HW_PXP_CTRL 0x0
-#define BM_PXP_CTRL_ENABLE 0x00000001
-#define BP_PXP_CTRL_ENABLE 0
-#define BM_PXP_CTRL_IRQ_ENABLE 0x00000002
-#define BM_PXP_CTRL_OUTPUT_RGB_FORMAT 0x000000F0
-#define BP_PXP_CTRL_OUTPUT_RGB_FORMAT 4
-#define BM_PXP_CTRL_ROTATE 0x00000300
-#define BP_PXP_CTRL_ROTATE 8
-#define BM_PXP_CTRL_HFLIP 0x00000400
-#define BM_PXP_CTRL_VFLIP 0x00000800
-#define BM_PXP_CTRL_S0_FORMAT 0x0000F000
-#define BP_PXP_CTRL_S0_FORMAT 12
-#define BM_PXP_CTRL_SCALE 0x00040000
-#define BM_PXP_CTRL_CROP 0x00080000
-
-#define HW_PXP_STAT 0x10
-#define BM_PXP_STAT_IRQ 0x00000001
-#define BP_PXP_STAT_IRQ 0
-
-#define HW_PXP_RGBBUF 0x20
-
-#define HW_PXP_RGBSIZE 0x40
-#define BM_PXP_RGBSIZE_HEIGHT 0x00000FFF
-#define BP_PXP_RGBSIZE_HEIGHT 0
-#define BM_PXP_RGBSIZE_WIDTH 0x00FFF000
-#define BP_PXP_RGBSIZE_WIDTH 12
-
-#define HW_PXP_S0BUF 0x50
-
-#define HW_PXP_S0UBUF 0x60
-
-#define HW_PXP_S0VBUF 0x70
-
-#define HW_PXP_S0PARAM 0x80
-#define BM_PXP_S0PARAM_HEIGHT 0x000000FF
-#define BP_PXP_S0PARAM_HEIGHT 0
-#define BM_PXP_S0PARAM_WIDTH 0x0000FF00
-#define BP_PXP_S0PARAM_WIDTH 8
-#define BM_PXP_S0PARAM_YBASE 0x00FF0000
-#define BP_PXP_S0PARAM_YBASE 16
-#define BM_PXP_S0PARAM_XBASE 0xFF000000
-#define BP_PXP_S0PARAM_XBASE 24
-
-#define HW_PXP_S0BACKGROUND 0x90
-
-#define HW_PXP_S0CROP 0xA0
-#define BM_PXP_S0CROP_HEIGHT 0x000000FF
-#define BP_PXP_S0CROP_HEIGHT 0
-#define BM_PXP_S0CROP_WIDTH 0x0000FF00
-#define BP_PXP_S0CROP_WIDTH 8
-#define BM_PXP_S0CROP_YBASE 0x00FF0000
-#define BP_PXP_S0CROP_YBASE 16
-#define BM_PXP_S0CROP_XBASE 0xFF000000
-#define BP_PXP_S0CROP_XBASE 24
-
-#define HW_PXP_S0SCALE 0xB0
-#define BM_PXP_S0SCALE_XSCALE 0x00003FFF
-#define BP_PXP_S0SCALE_XSCALE 0
-#define BM_PXP_S0SCALE_YSCALE 0x3FFF0000
-#define BP_PXP_S0SCALE_YSCALE 16
-
-#define HW_PXP_CSCCOEFF0 0xD0
-
-#define HW_PXP_CSCCOEFF1 0xE0
-
-#define HW_PXP_CSCCOEFF2 0xF0
-
-#define HW_PXP_S0COLORKEYLOW 0x180
-
-#define HW_PXP_S0COLORKEYHIGH 0x190
-
-#define HW_PXP_OL0 (0x200 + 0 * 0x40)
-#define HW_PXP_OL1 (0x200 + 1 * 0x40)
-#define HW_PXP_OL2 (0x200 + 2 * 0x40)
-#define HW_PXP_OL3 (0x200 + 3 * 0x40)
-#define HW_PXP_OL4 (0x200 + 4 * 0x40)
-#define HW_PXP_OL5 (0x200 + 5 * 0x40)
-#define HW_PXP_OL6 (0x200 + 6 * 0x40)
-#define HW_PXP_OL7 (0x200 + 7 * 0x40)
-
-#define HW_PXP_OLn 0x200
-
-#define HW_PXP_OL0SIZE (0x210 + 0 * 0x40)
-#define HW_PXP_OL1SIZE (0x210 + 1 * 0x40)
-#define HW_PXP_OL2SIZE (0x210 + 2 * 0x40)
-#define HW_PXP_OL3SIZE (0x210 + 3 * 0x40)
-#define HW_PXP_OL4SIZE (0x210 + 4 * 0x40)
-#define HW_PXP_OL5SIZE (0x210 + 5 * 0x40)
-#define HW_PXP_OL6SIZE (0x210 + 6 * 0x40)
-#define HW_PXP_OL7SIZE (0x210 + 7 * 0x40)
-
-#define HW_PXP_OLnSIZE 0x210
-#define BM_PXP_OLnSIZE_HEIGHT 0x000000FF
-#define BP_PXP_OLnSIZE_HEIGHT 0
-#define BM_PXP_OLnSIZE_WIDTH 0x0000FF00
-#define BP_PXP_OLnSIZE_WIDTH 8
-
-#define HW_PXP_OL0PARAM (0x220 + 0 * 0x40)
-#define HW_PXP_OL1PARAM (0x220 + 1 * 0x40)
-#define HW_PXP_OL2PARAM (0x220 + 2 * 0x40)
-#define HW_PXP_OL3PARAM (0x220 + 3 * 0x40)
-#define HW_PXP_OL4PARAM (0x220 + 4 * 0x40)
-#define HW_PXP_OL5PARAM (0x220 + 5 * 0x40)
-#define HW_PXP_OL6PARAM (0x220 + 6 * 0x40)
-#define HW_PXP_OL7PARAM (0x220 + 7 * 0x40)
-
-#define HW_PXP_OLnPARAM 0x220
-#define BM_PXP_OLnPARAM_ENABLE 0x00000001
-#define BP_PXP_OLnPARAM_ENABLE 0
-#define BM_PXP_OLnPARAM_ALPHA_CNTL 0x00000006
-#define BP_PXP_OLnPARAM_ALPHA_CNTL 1
-#define BM_PXP_OLnPARAM_ENABLE_COLORKEY 0x00000008
-#define BM_PXP_OLnPARAM_FORMAT 0x000000F0
-#define BP_PXP_OLnPARAM_FORMAT 4
-#define BM_PXP_OLnPARAM_ALPHA 0x0000FF00
-#define BP_PXP_OLnPARAM_ALPHA 8
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-rtc.h b/arch/arm/mach-stmp378x/include/mach/regs-rtc.h
deleted file mode 100644
index b8dbd67..0000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-rtc.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * stmp378x: RTC register definitions
- *
- * Copyright (c) 2008 Freescale Semiconductor
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#define REGS_RTC_BASE (STMP3XXX_REGS_BASE + 0x5C000)
-#define REGS_RTC_PHYS 0x8005C000
-#define REGS_RTC_SIZE 0x2000
-
-#define HW_RTC_CTRL 0x0
-#define BM_RTC_CTRL_ALARM_IRQ_EN 0x00000001
-#define BP_RTC_CTRL_ALARM_IRQ_EN 0
-#define BM_RTC_CTRL_ONEMSEC_IRQ_EN 0x00000002
-#define BM_RTC_CTRL_ALARM_IRQ 0x00000004
-#define BM_RTC_CTRL_ONEMSEC_IRQ 0x00000008
-#define BM_RTC_CTRL_WATCHDOGEN 0x00000010
-
-#define HW_RTC_STAT 0x10
-#define BM_RTC_STAT_NEW_REGS 0x0000FF00
-#define BP_RTC_STAT_NEW_REGS 8
-#define BM_RTC_STAT_STALE_REGS 0x00FF0000
-#define BP_RTC_STAT_STALE_REGS 16
-#define BM_RTC_STAT_RTC_PRESENT 0x80000000
-
-#define HW_RTC_SECONDS 0x30
-
-#define HW_RTC_ALARM 0x40
-
-#define HW_RTC_WATCHDOG 0x50
-
-#define HW_RTC_PERSISTENT0 0x60
-#define BM_RTC_PERSISTENT0_ALARM_WAKE_EN 0x00000002
-#define BM_RTC_PERSISTENT0_ALARM_EN 0x00000004
-#define BM_RTC_PERSISTENT0_XTAL24MHZ_PWRUP 0x00000010
-#define BM_RTC_PERSISTENT0_XTAL32KHZ_PWRUP 0x00000020
-#define BM_RTC_PERSISTENT0_ALARM_WAKE 0x00000080
-#define BM_RTC_PERSISTENT0_SPARE_ANALOG 0xFFFC0000
-#define BP_RTC_PERSISTENT0_SPARE_ANALOG 18
-
-#define HW_RTC_PERSISTENT1 0x70
-#define BM_RTC_PERSISTENT1_GENERAL 0xFFFFFFFF
-#define BP_RTC_PERSISTENT1_GENERAL 0
-
-#define HW_RTC_VERSION 0xD0
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-saif.h b/arch/arm/mach-stmp378x/include/mach/regs-saif.h
deleted file mode 100644
index 6df4176..0000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-saif.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * stmp378x: SAIF register definitions
- *
- * Copyright (c) 2008 Freescale Semiconductor
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#define REGS_SAIF_SIZE 0x2000
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-spdif.h b/arch/arm/mach-stmp378x/include/mach/regs-spdif.h
deleted file mode 100644
index 8015398..0000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-spdif.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * stmp378x: SPDIF register definitions
- *
- * Copyright (c) 2008 Freescale Semiconductor
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#define REGS_SPDIF_BASE (STMP3XXX_REGS_BASE + 0x54000)
-#define REGS_SPDIF_PHYS 0x80054000
-#define REGS_SPDIF_SIZE 0x2000
-
-#define HW_SPDIF_CTRL 0x0
-#define BM_SPDIF_CTRL_RUN 0x00000001
-#define BP_SPDIF_CTRL_RUN 0
-#define BM_SPDIF_CTRL_FIFO_ERROR_IRQ_EN 0x00000002
-#define BM_SPDIF_CTRL_FIFO_OVERFLOW_IRQ 0x00000004
-#define BM_SPDIF_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008
-#define BM_SPDIF_CTRL_WORD_LENGTH 0x00000010
-#define BM_SPDIF_CTRL_CLKGATE 0x40000000
-#define BM_SPDIF_CTRL_SFTRST 0x80000000
-
-#define HW_SPDIF_STAT 0x10
-
-#define HW_SPDIF_FRAMECTRL 0x20
-
-#define HW_SPDIF_SRR 0x30
-#define BM_SPDIF_SRR_RATE 0x000FFFFF
-#define BP_SPDIF_SRR_RATE 0
-#define BM_SPDIF_SRR_BASEMULT 0x70000000
-#define BP_SPDIF_SRR_BASEMULT 28
-
-#define HW_SPDIF_DEBUG 0x40
-
-#define HW_SPDIF_DATA 0x50
-
-#define HW_SPDIF_VERSION 0x60
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-ssp.h b/arch/arm/mach-stmp378x/include/mach/regs-ssp.h
deleted file mode 100644
index 28aacf0..0000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-ssp.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * stmp378x: SSP register definitions
- *
- * Copyright (c) 2008 Freescale Semiconductor
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#define REGS_SSP1_BASE (STMP3XXX_REGS_BASE + 0x10000)
-#define REGS_SSP1_PHYS 0x80010000
-#define REGS_SSP2_BASE (STMP3XXX_REGS_BASE + 0x34000)
-#define REGS_SSP2_PHYS 0x80034000
-#define REGS_SSP_SIZE 0x2000
-
-#define HW_SSP_CTRL0 0x0
-#define BM_SSP_CTRL0_XFER_COUNT 0x0000FFFF
-#define BP_SSP_CTRL0_XFER_COUNT 0
-#define BM_SSP_CTRL0_ENABLE 0x00010000
-#define BM_SSP_CTRL0_GET_RESP 0x00020000
-#define BM_SSP_CTRL0_LONG_RESP 0x00080000
-#define BM_SSP_CTRL0_WAIT_FOR_CMD 0x00100000
-#define BM_SSP_CTRL0_WAIT_FOR_IRQ 0x00200000
-#define BM_SSP_CTRL0_BUS_WIDTH 0x00C00000
-#define BP_SSP_CTRL0_BUS_WIDTH 22
-#define BM_SSP_CTRL0_DATA_XFER 0x01000000
-#define BM_SSP_CTRL0_READ 0x02000000
-#define BM_SSP_CTRL0_IGNORE_CRC 0x04000000
-#define BM_SSP_CTRL0_LOCK_CS 0x08000000
-#define BM_SSP_CTRL0_RUN 0x20000000
-#define BM_SSP_CTRL0_CLKGATE 0x40000000
-#define BM_SSP_CTRL0_SFTRST 0x80000000
-
-#define HW_SSP_CMD0 0x10
-#define BM_SSP_CMD0_CMD 0x000000FF
-#define BP_SSP_CMD0_CMD 0
-#define BM_SSP_CMD0_BLOCK_COUNT 0x0000FF00
-#define BP_SSP_CMD0_BLOCK_COUNT 8
-#define BM_SSP_CMD0_BLOCK_SIZE 0x000F0000
-#define BP_SSP_CMD0_BLOCK_SIZE 16
-#define BM_SSP_CMD0_APPEND_8CYC 0x00100000
-#define BM_SSP_CMD1_CMD_ARG 0xFFFFFFFF
-#define BP_SSP_CMD1_CMD_ARG 0
-
-#define HW_SSP_TIMING 0x50
-#define BM_SSP_TIMING_CLOCK_RATE 0x000000FF
-#define BP_SSP_TIMING_CLOCK_RATE 0
-#define BM_SSP_TIMING_CLOCK_DIVIDE 0x0000FF00
-#define BP_SSP_TIMING_CLOCK_DIVIDE 8
-#define BM_SSP_TIMING_TIMEOUT 0xFFFF0000
-#define BP_SSP_TIMING_TIMEOUT 16
-
-#define HW_SSP_CTRL1 0x60
-#define BM_SSP_CTRL1_SSP_MODE 0x0000000F
-#define BP_SSP_CTRL1_SSP_MODE 0
-#define BM_SSP_CTRL1_WORD_LENGTH 0x000000F0
-#define BP_SSP_CTRL1_WORD_LENGTH 4
-#define BM_SSP_CTRL1_POLARITY 0x00000200
-#define BM_SSP_CTRL1_PHASE 0x00000400
-#define BM_SSP_CTRL1_DMA_ENABLE 0x00002000
-#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ 0x00008000
-#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN 0x00010000
-#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ 0x00020000
-#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ 0x00200000
-#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN 0x00400000
-#define BM_SSP_CTRL1_DATA_CRC_IRQ 0x00800000
-#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN 0x01000000
-#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ 0x02000000
-#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN 0x04000000
-#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ 0x08000000
-#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN 0x10000000
-#define BM_SSP_CTRL1_RESP_ERR_IRQ 0x20000000
-#define BM_SSP_CTRL1_SDIO_IRQ 0x80000000
-
-#define HW_SSP_DATA 0x70
-
-#define HW_SSP_SDRESP0 0x80
-
-#define HW_SSP_SDRESP1 0x90
-
-#define HW_SSP_SDRESP2 0xA0
-
-#define HW_SSP_SDRESP3 0xB0
-
-#define HW_SSP_STATUS 0xC0
-#define BM_SSP_STATUS_FIFO_EMPTY 0x00000020
-#define BM_SSP_STATUS_TIMEOUT 0x00001000
-#define BM_SSP_STATUS_RESP_TIMEOUT 0x00004000
-#define BM_SSP_STATUS_RESP_ERR 0x00008000
-#define BM_SSP_STATUS_RESP_CRC_ERR 0x00010000
-#define BM_SSP_STATUS_CARD_DETECT 0x10000000
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-sydma.h b/arch/arm/mach-stmp378x/include/mach/regs-sydma.h
deleted file mode 100644
index 08343a8..0000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-sydma.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * stmp378x: SYDMA register definitions
- *
- * Copyright (c) 2008 Freescale Semiconductor
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#define REGS_SYDMA_BASE (STMP3XXX_REGS_BASE + 0x26000)
-#define REGS_SYDMA_PHYS 0x80026000
-#define REGS_SYDMA_SIZE 0x2000
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-timrot.h b/arch/arm/mach-stmp378x/include/mach/regs-timrot.h
deleted file mode 100644
index b552795..0000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-timrot.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * stmp378x: TIMROT register definitions
- *
- * Copyright (c) 2008 Freescale Semiconductor
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#ifndef _MACH_REGS_TIMROT
-#define _MACH_REGS_TIMROT
-
-#define REGS_TIMROT_BASE (STMP3XXX_REGS_BASE + 0x68000)
-#define REGS_TIMROT_PHYS 0x80068000
-#define REGS_TIMROT_SIZE 0x2000
-
-#define HW_TIMROT_ROTCTRL 0x0
-#define BM_TIMROT_ROTCTRL_SELECT_A 0x00000007
-#define BP_TIMROT_ROTCTRL_SELECT_A 0
-#define BM_TIMROT_ROTCTRL_SELECT_B 0x00000070
-#define BP_TIMROT_ROTCTRL_SELECT_B 4
-#define BM_TIMROT_ROTCTRL_POLARITY_A 0x00000100
-#define BM_TIMROT_ROTCTRL_POLARITY_B 0x00000200
-#define BM_TIMROT_ROTCTRL_OVERSAMPLE 0x00000C00
-#define BP_TIMROT_ROTCTRL_OVERSAMPLE 10
-#define BM_TIMROT_ROTCTRL_RELATIVE 0x00001000
-#define BM_TIMROT_ROTCTRL_DIVIDER 0x003F0000
-#define BP_TIMROT_ROTCTRL_DIVIDER 16
-#define BM_TIMROT_ROTCTRL_ROTARY_PRESENT 0x20000000
-#define BM_TIMROT_ROTCTRL_CLKGATE 0x40000000
-#define BM_TIMROT_ROTCTRL_SFTRST 0x80000000
-
-#define HW_TIMROT_ROTCOUNT 0x10
-#define BM_TIMROT_ROTCOUNT_UPDOWN 0x0000FFFF
-#define BP_TIMROT_ROTCOUNT_UPDOWN 0
-
-#define HW_TIMROT_TIMCTRL0 (0x20 + 0 * 0x20)
-#define HW_TIMROT_TIMCTRL1 (0x20 + 1 * 0x20)
-#define HW_TIMROT_TIMCTRL2 (0x20 + 2 * 0x20)
-
-#define HW_TIMROT_TIMCTRLn 0x20
-#define BM_TIMROT_TIMCTRLn_SELECT 0x0000000F
-#define BP_TIMROT_TIMCTRLn_SELECT 0
-#define BM_TIMROT_TIMCTRLn_PRESCALE 0x00000030
-#define BP_TIMROT_TIMCTRLn_PRESCALE 4
-#define BM_TIMROT_TIMCTRLn_RELOAD 0x00000040
-#define BM_TIMROT_TIMCTRLn_UPDATE 0x00000080
-#define BM_TIMROT_TIMCTRLn_IRQ_EN 0x00004000
-#define BM_TIMROT_TIMCTRLn_IRQ 0x00008000
-
-#define HW_TIMROT_TIMCOUNT0 (0x30 + 0 * 0x20)
-#define HW_TIMROT_TIMCOUNT1 (0x30 + 1 * 0x20)
-#define HW_TIMROT_TIMCOUNT2 (0x30 + 2 * 0x20)
-
-#define HW_TIMROT_TIMCOUNTn 0x30
-
-#endif
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-tvenc.h b/arch/arm/mach-stmp378x/include/mach/regs-tvenc.h
deleted file mode 100644
index 7f895cb..0000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-tvenc.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * stmp378x: TVENC register definitions
- *
- * Copyright (c) 2008 Freescale Semiconductor
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#define REGS_TVENC_BASE (STMP3XXX_REGS_BASE + 0x38000)
-#define REGS_TVENC_PHYS 0x80038000
-#define REGS_TVENC_SIZE 0x2000
-
-#define HW_TVENC_CTRL 0x0
-#define BM_TVENC_CTRL_CLKGATE 0x40000000
-#define BM_TVENC_CTRL_SFTRST 0x80000000
-
-#define HW_TVENC_CONFIG 0x10
-#define BM_TVENC_CONFIG_ENCD_MODE 0x00000007
-#define BP_TVENC_CONFIG_ENCD_MODE 0
-#define BM_TVENC_CONFIG_SYNC_MODE 0x00000070
-#define BP_TVENC_CONFIG_SYNC_MODE 4
-#define BM_TVENC_CONFIG_FSYNC_PHS 0x00000200
-#define BM_TVENC_CONFIG_CGAIN 0x0000C000
-#define BP_TVENC_CONFIG_CGAIN 14
-#define BM_TVENC_CONFIG_YGAIN_SEL 0x00030000
-#define BP_TVENC_CONFIG_YGAIN_SEL 16
-#define BM_TVENC_CONFIG_PAL_SHAPE 0x00100000
-
-#define HW_TVENC_SYNCOFFSET 0x30
-
-#define HW_TVENC_COLORSUB0 0xC0
-
-#define HW_TVENC_COLORBURST 0x140
-#define BM_TVENC_COLORBURST_PBA 0x00FF0000
-#define BP_TVENC_COLORBURST_PBA 16
-#define BM_TVENC_COLORBURST_NBA 0xFF000000
-#define BP_TVENC_COLORBURST_NBA 24
-
-#define HW_TVENC_MACROVISION0 0x150
-
-#define HW_TVENC_MACROVISION1 0x160
-
-#define HW_TVENC_MACROVISION2 0x170
-
-#define HW_TVENC_MACROVISION3 0x180
-
-#define HW_TVENC_MACROVISION4 0x190
-
-#define HW_TVENC_DACCTRL 0x1A0
-#define BM_TVENC_DACCTRL_RVAL 0x00000070
-#define BP_TVENC_DACCTRL_RVAL 4
-#define BM_TVENC_DACCTRL_DUMP_TOVDD1 0x00000100
-#define BM_TVENC_DACCTRL_PWRUP1 0x00001000
-#define BM_TVENC_DACCTRL_GAINUP 0x00040000
-#define BM_TVENC_DACCTRL_GAINDN 0x00080000
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-uartapp.h b/arch/arm/mach-stmp378x/include/mach/regs-uartapp.h
deleted file mode 100644
index a251e68..0000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-uartapp.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * stmp378x: UARTAPP register definitions
- *
- * Copyright (c) 2008 Freescale Semiconductor
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#define REGS_UARTAPP1_BASE (STMP3XXX_REGS_BASE + 0x6C000)
-#define REGS_UARTAPP1_PHYS 0x8006C000
-#define REGS_UARTAPP2_BASE (STMP3XXX_REGS_BASE + 0x6E000)
-#define REGS_UARTAPP2_PHYS 0x8006E000
-#define REGS_UARTAPP_SIZE 0x2000
-
-#define HW_UARTAPP_CTRL0 0x0
-#define BM_UARTAPP_CTRL0_XFER_COUNT 0x0000FFFF
-#define BP_UARTAPP_CTRL0_XFER_COUNT 0
-#define BM_UARTAPP_CTRL0_RXTIMEOUT 0x07FF0000
-#define BP_UARTAPP_CTRL0_RXTIMEOUT 16
-#define BM_UARTAPP_CTRL0_RXTO_ENABLE 0x08000000
-#define BM_UARTAPP_CTRL0_RUN 0x20000000
-#define BM_UARTAPP_CTRL0_SFTRST 0x80000000
-#define BM_UARTAPP_CTRL1_XFER_COUNT 0x0000FFFF
-#define BP_UARTAPP_CTRL1_XFER_COUNT 0
-#define BM_UARTAPP_CTRL1_RUN 0x10000000
-
-#define HW_UARTAPP_CTRL2 0x20
-#define BM_UARTAPP_CTRL2_UARTEN 0x00000001
-#define BP_UARTAPP_CTRL2_UARTEN 0
-#define BM_UARTAPP_CTRL2_TXE 0x00000100
-#define BM_UARTAPP_CTRL2_RXE 0x00000200
-#define BM_UARTAPP_CTRL2_RTS 0x00000800
-#define BM_UARTAPP_CTRL2_RTSEN 0x00004000
-#define BM_UARTAPP_CTRL2_CTSEN 0x00008000
-#define BM_UARTAPP_CTRL2_RXDMAE 0x01000000
-#define BM_UARTAPP_CTRL2_TXDMAE 0x02000000
-#define BM_UARTAPP_CTRL2_DMAONERR 0x04000000
-
-#define HW_UARTAPP_LINECTRL 0x30
-#define BM_UARTAPP_LINECTRL_BRK 0x00000001
-#define BP_UARTAPP_LINECTRL_BRK 0
-#define BM_UARTAPP_LINECTRL_PEN 0x00000002
-#define BM_UARTAPP_LINECTRL_EPS 0x00000004
-#define BM_UARTAPP_LINECTRL_STP2 0x00000008
-#define BM_UARTAPP_LINECTRL_FEN 0x00000010
-#define BM_UARTAPP_LINECTRL_WLEN 0x00000060
-#define BP_UARTAPP_LINECTRL_WLEN 5
-#define BM_UARTAPP_LINECTRL_SPS 0x00000080
-#define BM_UARTAPP_LINECTRL_BAUD_DIVFRAC 0x00003F00
-#define BP_UARTAPP_LINECTRL_BAUD_DIVFRAC 8
-#define BM_UARTAPP_LINECTRL_BAUD_DIVINT 0xFFFF0000
-#define BP_UARTAPP_LINECTRL_BAUD_DIVINT 16
-
-#define HW_UARTAPP_INTR 0x50
-#define BM_UARTAPP_INTR_CTSMIS 0x00000002
-#define BM_UARTAPP_INTR_RTIS 0x00000040
-#define BM_UARTAPP_INTR_CTSMIEN 0x00020000
-#define BM_UARTAPP_INTR_RXIEN 0x00100000
-#define BM_UARTAPP_INTR_RTIEN 0x00400000
-
-#define HW_UARTAPP_DATA 0x60
-
-#define HW_UARTAPP_STAT 0x70
-#define BM_UARTAPP_STAT_RXCOUNT 0x0000FFFF
-#define BP_UARTAPP_STAT_RXCOUNT 0
-#define BM_UARTAPP_STAT_FERR 0x00010000
-#define BM_UARTAPP_STAT_PERR 0x00020000
-#define BM_UARTAPP_STAT_BERR 0x00040000
-#define BM_UARTAPP_STAT_OERR 0x00080000
-#define BM_UARTAPP_STAT_RXFE 0x01000000
-#define BM_UARTAPP_STAT_TXFF 0x02000000
-#define BM_UARTAPP_STAT_TXFE 0x08000000
-#define BM_UARTAPP_STAT_CTS 0x10000000
-
-#define HW_UARTAPP_VERSION 0x90
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-uartdbg.h b/arch/arm/mach-stmp378x/include/mach/regs-uartdbg.h
deleted file mode 100644
index b810deb..0000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-uartdbg.h
+++ /dev/null
@@ -1,268 +0,0 @@
-/*
- * stmp378x: UARTDBG register definitions
- *
- * Copyright (c) 2008 Freescale Semiconductor
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#define REGS_UARTDBG_BASE (STMP3XXX_REGS_BASE + 0x70000)
-#define REGS_UARTDBG_PHYS 0x80070000
-#define REGS_UARTDBG_SIZE 0x2000
-
-#define HW_UARTDBGDR 0x00000000
-#define BP_UARTDBGDR_UNAVAILABLE 16
-#define BM_UARTDBGDR_UNAVAILABLE 0xFFFF0000
-#define BF_UARTDBGDR_UNAVAILABLE(v) \
- (((v) << 16) & BM_UARTDBGDR_UNAVAILABLE)
-#define BP_UARTDBGDR_RESERVED 12
-#define BM_UARTDBGDR_RESERVED 0x0000F000
-#define BF_UARTDBGDR_RESERVED(v) \
- (((v) << 12) & BM_UARTDBGDR_RESERVED)
-#define BM_UARTDBGDR_OE 0x00000800
-#define BM_UARTDBGDR_BE 0x00000400
-#define BM_UARTDBGDR_PE 0x00000200
-#define BM_UARTDBGDR_FE 0x00000100
-#define BP_UARTDBGDR_DATA 0
-#define BM_UARTDBGDR_DATA 0x000000FF
-#define BF_UARTDBGDR_DATA(v) \
- (((v) << 0) & BM_UARTDBGDR_DATA)
-#define HW_UARTDBGRSR_ECR 0x00000004
-#define BP_UARTDBGRSR_ECR_UNAVAILABLE 8
-#define BM_UARTDBGRSR_ECR_UNAVAILABLE 0xFFFFFF00
-#define BF_UARTDBGRSR_ECR_UNAVAILABLE(v) \
- (((v) << 8) & BM_UARTDBGRSR_ECR_UNAVAILABLE)
-#define BP_UARTDBGRSR_ECR_EC 4
-#define BM_UARTDBGRSR_ECR_EC 0x000000F0
-#define BF_UARTDBGRSR_ECR_EC(v) \
- (((v) << 4) & BM_UARTDBGRSR_ECR_EC)
-#define BM_UARTDBGRSR_ECR_OE 0x00000008
-#define BM_UARTDBGRSR_ECR_BE 0x00000004
-#define BM_UARTDBGRSR_ECR_PE 0x00000002
-#define BM_UARTDBGRSR_ECR_FE 0x00000001
-#define HW_UARTDBGFR 0x00000018
-#define BP_UARTDBGFR_UNAVAILABLE 16
-#define BM_UARTDBGFR_UNAVAILABLE 0xFFFF0000
-#define BF_UARTDBGFR_UNAVAILABLE(v) \
- (((v) << 16) & BM_UARTDBGFR_UNAVAILABLE)
-#define BP_UARTDBGFR_RESERVED 9
-#define BM_UARTDBGFR_RESERVED 0x0000FE00
-#define BF_UARTDBGFR_RESERVED(v) \
- (((v) << 9) & BM_UARTDBGFR_RESERVED)
-#define BM_UARTDBGFR_RI 0x00000100
-#define BM_UARTDBGFR_TXFE 0x00000080
-#define BM_UARTDBGFR_RXFF 0x00000040
-#define BM_UARTDBGFR_TXFF 0x00000020
-#define BM_UARTDBGFR_RXFE 0x00000010
-#define BM_UARTDBGFR_BUSY 0x00000008
-#define BM_UARTDBGFR_DCD 0x00000004
-#define BM_UARTDBGFR_DSR 0x00000002
-#define BM_UARTDBGFR_CTS 0x00000001
-#define HW_UARTDBGILPR 0x00000020
-#define BP_UARTDBGILPR_UNAVAILABLE 8
-#define BM_UARTDBGILPR_UNAVAILABLE 0xFFFFFF00
-#define BF_UARTDBGILPR_UNAVAILABLE(v) \
- (((v) << 8) & BM_UARTDBGILPR_UNAVAILABLE)
-#define BP_UARTDBGILPR_ILPDVSR 0
-#define BM_UARTDBGILPR_ILPDVSR 0x000000FF
-#define BF_UARTDBGILPR_ILPDVSR(v) \
- (((v) << 0) & BM_UARTDBGILPR_ILPDVSR)
-#define HW_UARTDBGIBRD 0x00000024
-#define BP_UARTDBGIBRD_UNAVAILABLE 16
-#define BM_UARTDBGIBRD_UNAVAILABLE 0xFFFF0000
-#define BF_UARTDBGIBRD_UNAVAILABLE(v) \
- (((v) << 16) & BM_UARTDBGIBRD_UNAVAILABLE)
-#define BP_UARTDBGIBRD_BAUD_DIVINT 0
-#define BM_UARTDBGIBRD_BAUD_DIVINT 0x0000FFFF
-#define BF_UARTDBGIBRD_BAUD_DIVINT(v) \
- (((v) << 0) & BM_UARTDBGIBRD_BAUD_DIVINT)
-#define HW_UARTDBGFBRD 0x00000028
-#define BP_UARTDBGFBRD_UNAVAILABLE 8
-#define BM_UARTDBGFBRD_UNAVAILABLE 0xFFFFFF00
-#define BF_UARTDBGFBRD_UNAVAILABLE(v) \
- (((v) << 8) & BM_UARTDBGFBRD_UNAVAILABLE)
-#define BP_UARTDBGFBRD_RESERVED 6
-#define BM_UARTDBGFBRD_RESERVED 0x000000C0
-#define BF_UARTDBGFBRD_RESERVED(v) \
- (((v) << 6) & BM_UARTDBGFBRD_RESERVED)
-#define BP_UARTDBGFBRD_BAUD_DIVFRAC 0
-#define BM_UARTDBGFBRD_BAUD_DIVFRAC 0x0000003F
-#define BF_UARTDBGFBRD_BAUD_DIVFRAC(v) \
- (((v) << 0) & BM_UARTDBGFBRD_BAUD_DIVFRAC)
-#define HW_UARTDBGLCR_H 0x0000002c
-#define BP_UARTDBGLCR_H_UNAVAILABLE 16
-#define BM_UARTDBGLCR_H_UNAVAILABLE 0xFFFF0000
-#define BF_UARTDBGLCR_H_UNAVAILABLE(v) \
- (((v) << 16) & BM_UARTDBGLCR_H_UNAVAILABLE)
-#define BP_UARTDBGLCR_H_RESERVED 8
-#define BM_UARTDBGLCR_H_RESERVED 0x0000FF00
-#define BF_UARTDBGLCR_H_RESERVED(v) \
- (((v) << 8) & BM_UARTDBGLCR_H_RESERVED)
-#define BM_UARTDBGLCR_H_SPS 0x00000080
-#define BP_UARTDBGLCR_H_WLEN 5
-#define BM_UARTDBGLCR_H_WLEN 0x00000060
-#define BF_UARTDBGLCR_H_WLEN(v) \
- (((v) << 5) & BM_UARTDBGLCR_H_WLEN)
-#define BM_UARTDBGLCR_H_FEN 0x00000010
-#define BM_UARTDBGLCR_H_STP2 0x00000008
-#define BM_UARTDBGLCR_H_EPS 0x00000004
-#define BM_UARTDBGLCR_H_PEN 0x00000002
-#define BM_UARTDBGLCR_H_BRK 0x00000001
-#define HW_UARTDBGCR 0x00000030
-#define BP_UARTDBGCR_UNAVAILABLE 16
-#define BM_UARTDBGCR_UNAVAILABLE 0xFFFF0000
-#define BF_UARTDBGCR_UNAVAILABLE(v) \
- (((v) << 16) & BM_UARTDBGCR_UNAVAILABLE)
-#define BM_UARTDBGCR_CTSEN 0x00008000
-#define BM_UARTDBGCR_RTSEN 0x00004000
-#define BM_UARTDBGCR_OUT2 0x00002000
-#define BM_UARTDBGCR_OUT1 0x00001000
-#define BM_UARTDBGCR_RTS 0x00000800
-#define BM_UARTDBGCR_DTR 0x00000400
-#define BM_UARTDBGCR_RXE 0x00000200
-#define BM_UARTDBGCR_TXE 0x00000100
-#define BM_UARTDBGCR_LBE 0x00000080
-#define BP_UARTDBGCR_RESERVED 3
-#define BM_UARTDBGCR_RESERVED 0x00000078
-#define BF_UARTDBGCR_RESERVED(v) \
- (((v) << 3) & BM_UARTDBGCR_RESERVED)
-#define BM_UARTDBGCR_SIRLP 0x00000004
-#define BM_UARTDBGCR_SIREN 0x00000002
-#define BM_UARTDBGCR_UARTEN 0x00000001
-#define HW_UARTDBGIFLS 0x00000034
-#define BP_UARTDBGIFLS_UNAVAILABLE 16
-#define BM_UARTDBGIFLS_UNAVAILABLE 0xFFFF0000
-#define BF_UARTDBGIFLS_UNAVAILABLE(v) \
- (((v) << 16) & BM_UARTDBGIFLS_UNAVAILABLE)
-#define BP_UARTDBGIFLS_RESERVED 6
-#define BM_UARTDBGIFLS_RESERVED 0x0000FFC0
-#define BF_UARTDBGIFLS_RESERVED(v) \
- (((v) << 6) & BM_UARTDBGIFLS_RESERVED)
-#define BP_UARTDBGIFLS_RXIFLSEL 3
-#define BM_UARTDBGIFLS_RXIFLSEL 0x00000038
-#define BF_UARTDBGIFLS_RXIFLSEL(v) \
- (((v) << 3) & BM_UARTDBGIFLS_RXIFLSEL)
-#define BV_UARTDBGIFLS_RXIFLSEL__NOT_EMPTY 0x0
-#define BV_UARTDBGIFLS_RXIFLSEL__ONE_QUARTER 0x1
-#define BV_UARTDBGIFLS_RXIFLSEL__ONE_HALF 0x2
-#define BV_UARTDBGIFLS_RXIFLSEL__THREE_QUARTERS 0x3
-#define BV_UARTDBGIFLS_RXIFLSEL__SEVEN_EIGHTHS 0x4
-#define BV_UARTDBGIFLS_RXIFLSEL__INVALID5 0x5
-#define BV_UARTDBGIFLS_RXIFLSEL__INVALID6 0x6
-#define BV_UARTDBGIFLS_RXIFLSEL__INVALID7 0x7
-#define BP_UARTDBGIFLS_TXIFLSEL 0
-#define BM_UARTDBGIFLS_TXIFLSEL 0x00000007
-#define BF_UARTDBGIFLS_TXIFLSEL(v) \
- (((v) << 0) & BM_UARTDBGIFLS_TXIFLSEL)
-#define BV_UARTDBGIFLS_TXIFLSEL__EMPTY 0x0
-#define BV_UARTDBGIFLS_TXIFLSEL__ONE_QUARTER 0x1
-#define BV_UARTDBGIFLS_TXIFLSEL__ONE_HALF 0x2
-#define BV_UARTDBGIFLS_TXIFLSEL__THREE_QUARTERS 0x3
-#define BV_UARTDBGIFLS_TXIFLSEL__SEVEN_EIGHTHS 0x4
-#define BV_UARTDBGIFLS_TXIFLSEL__INVALID5 0x5
-#define BV_UARTDBGIFLS_TXIFLSEL__INVALID6 0x6
-#define BV_UARTDBGIFLS_TXIFLSEL__INVALID7 0x7
-#define HW_UARTDBGIMSC 0x00000038
-#define BP_UARTDBGIMSC_UNAVAILABLE 16
-#define BM_UARTDBGIMSC_UNAVAILABLE 0xFFFF0000
-#define BF_UARTDBGIMSC_UNAVAILABLE(v) \
- (((v) << 16) & BM_UARTDBGIMSC_UNAVAILABLE)
-#define BP_UARTDBGIMSC_RESERVED 11
-#define BM_UARTDBGIMSC_RESERVED 0x0000F800
-#define BF_UARTDBGIMSC_RESERVED(v) \
- (((v) << 11) & BM_UARTDBGIMSC_RESERVED)
-#define BM_UARTDBGIMSC_OEIM 0x00000400
-#define BM_UARTDBGIMSC_BEIM 0x00000200
-#define BM_UARTDBGIMSC_PEIM 0x00000100
-#define BM_UARTDBGIMSC_FEIM 0x00000080
-#define BM_UARTDBGIMSC_RTIM 0x00000040
-#define BM_UARTDBGIMSC_TXIM 0x00000020
-#define BM_UARTDBGIMSC_RXIM 0x00000010
-#define BM_UARTDBGIMSC_DSRMIM 0x00000008
-#define BM_UARTDBGIMSC_DCDMIM 0x00000004
-#define BM_UARTDBGIMSC_CTSMIM 0x00000002
-#define BM_UARTDBGIMSC_RIMIM 0x00000001
-#define HW_UARTDBGRIS 0x0000003c
-#define BP_UARTDBGRIS_UNAVAILABLE 16
-#define BM_UARTDBGRIS_UNAVAILABLE 0xFFFF0000
-#define BF_UARTDBGRIS_UNAVAILABLE(v) \
- (((v) << 16) & BM_UARTDBGRIS_UNAVAILABLE)
-#define BP_UARTDBGRIS_RESERVED 11
-#define BM_UARTDBGRIS_RESERVED 0x0000F800
-#define BF_UARTDBGRIS_RESERVED(v) \
- (((v) << 11) & BM_UARTDBGRIS_RESERVED)
-#define BM_UARTDBGRIS_OERIS 0x00000400
-#define BM_UARTDBGRIS_BERIS 0x00000200
-#define BM_UARTDBGRIS_PERIS 0x00000100
-#define BM_UARTDBGRIS_FERIS 0x00000080
-#define BM_UARTDBGRIS_RTRIS 0x00000040
-#define BM_UARTDBGRIS_TXRIS 0x00000020
-#define BM_UARTDBGRIS_RXRIS 0x00000010
-#define BM_UARTDBGRIS_DSRRMIS 0x00000008
-#define BM_UARTDBGRIS_DCDRMIS 0x00000004
-#define BM_UARTDBGRIS_CTSRMIS 0x00000002
-#define BM_UARTDBGRIS_RIRMIS 0x00000001
-#define HW_UARTDBGMIS 0x00000040
-#define BP_UARTDBGMIS_UNAVAILABLE 16
-#define BM_UARTDBGMIS_UNAVAILABLE 0xFFFF0000
-#define BF_UARTDBGMIS_UNAVAILABLE(v) \
- (((v) << 16) & BM_UARTDBGMIS_UNAVAILABLE)
-#define BP_UARTDBGMIS_RESERVED 11
-#define BM_UARTDBGMIS_RESERVED 0x0000F800
-#define BF_UARTDBGMIS_RESERVED(v) \
- (((v) << 11) & BM_UARTDBGMIS_RESERVED)
-#define BM_UARTDBGMIS_OEMIS 0x00000400
-#define BM_UARTDBGMIS_BEMIS 0x00000200
-#define BM_UARTDBGMIS_PEMIS 0x00000100
-#define BM_UARTDBGMIS_FEMIS 0x00000080
-#define BM_UARTDBGMIS_RTMIS 0x00000040
-#define BM_UARTDBGMIS_TXMIS 0x00000020
-#define BM_UARTDBGMIS_RXMIS 0x00000010
-#define BM_UARTDBGMIS_DSRMMIS 0x00000008
-#define BM_UARTDBGMIS_DCDMMIS 0x00000004
-#define BM_UARTDBGMIS_CTSMMIS 0x00000002
-#define BM_UARTDBGMIS_RIMMIS 0x00000001
-#define HW_UARTDBGICR 0x00000044
-#define BP_UARTDBGICR_UNAVAILABLE 16
-#define BM_UARTDBGICR_UNAVAILABLE 0xFFFF0000
-#define BF_UARTDBGICR_UNAVAILABLE(v) \
- (((v) << 16) & BM_UARTDBGICR_UNAVAILABLE)
-#define BP_UARTDBGICR_RESERVED 11
-#define BM_UARTDBGICR_RESERVED 0x0000F800
-#define BF_UARTDBGICR_RESERVED(v) \
- (((v) << 11) & BM_UARTDBGICR_RESERVED)
-#define BM_UARTDBGICR_OEIC 0x00000400
-#define BM_UARTDBGICR_BEIC 0x00000200
-#define BM_UARTDBGICR_PEIC 0x00000100
-#define BM_UARTDBGICR_FEIC 0x00000080
-#define BM_UARTDBGICR_RTIC 0x00000040
-#define BM_UARTDBGICR_TXIC 0x00000020
-#define BM_UARTDBGICR_RXIC 0x00000010
-#define BM_UARTDBGICR_DSRMIC 0x00000008
-#define BM_UARTDBGICR_DCDMIC 0x00000004
-#define BM_UARTDBGICR_CTSMIC 0x00000002
-#define BM_UARTDBGICR_RIMIC 0x00000001
-#define HW_UARTDBGDMACR 0x00000048
-#define BP_UARTDBGDMACR_UNAVAILABLE 16
-#define BM_UARTDBGDMACR_UNAVAILABLE 0xFFFF0000
-#define BF_UARTDBGDMACR_UNAVAILABLE(v) \
- (((v) << 16) & BM_UARTDBGDMACR_UNAVAILABLE)
-#define BP_UARTDBGDMACR_RESERVED 3
-#define BM_UARTDBGDMACR_RESERVED 0x0000FFF8
-#define BF_UARTDBGDMACR_RESERVED(v) \
- (((v) << 3) & BM_UARTDBGDMACR_RESERVED)
-#define BM_UARTDBGDMACR_DMAONERR 0x00000004
-#define BM_UARTDBGDMACR_TXDMAE 0x00000002
-#define BM_UARTDBGDMACR_RXDMAE 0x00000001
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-usbctrl.h b/arch/arm/mach-stmp378x/include/mach/regs-usbctrl.h
deleted file mode 100644
index 25112c1..0000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-usbctrl.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * stmp378x: USBCTRL register definitions
- *
- * Copyright (c) 2008 Freescale Semiconductor
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#define REGS_USBCTRL_BASE (STMP3XXX_REGS_BASE + 0x80000)
-#define REGS_USBCTRL_PHYS 0x80080000
-#define REGS_USBCTRL_SIZE 0x2000
-
-#define HW_USBCTRL_USBCMD 0x140
-#define BM_USBCTRL_USBCMD_RS 0x00000001
-#define BP_USBCTRL_USBCMD_RS 0
-#define BM_USBCTRL_USBCMD_RST 0x00000002
-
-#define HW_USBCTRL_USBINTR 0x148
-#define BM_USBCTRL_USBINTR_UE 0x00000001
-#define BP_USBCTRL_USBINTR_UE 0
-
-#define HW_USBCTRL_PORTSC1 0x184
-#define BM_USBCTRL_PORTSC1_PHCD 0x00800000
-
-#define HW_USBCTRL_OTGSC 0x1A4
-#define BM_USBCTRL_OTGSC_ID 0x00000100
-#define BM_USBCTRL_OTGSC_IDIS 0x00010000
-#define BM_USBCTRL_OTGSC_IDIE 0x01000000
diff --git a/arch/arm/mach-stmp378x/include/mach/regs-usbphy.h b/arch/arm/mach-stmp378x/include/mach/regs-usbphy.h
deleted file mode 100644
index 11f3b73..0000000
--- a/arch/arm/mach-stmp378x/include/mach/regs-usbphy.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * stmp378x: USBPHY register definitions
- *
- * Copyright (c) 2008 Freescale Semiconductor
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#define REGS_USBPHY_BASE (STMP3XXX_REGS_BASE + 0x7C000)
-#define REGS_USBPHY_PHYS 0x8007C000
-#define REGS_USBPHY_SIZE 0x2000
-
-#define HW_USBPHY_PWD 0x0
-
-#define HW_USBPHY_CTRL 0x30
-#define BM_USBPHY_CTRL_ENHOSTDISCONDETECT 0x00000002
-#define BM_USBPHY_CTRL_ENDEVPLUGINDETECT 0x00000010
-#define BM_USBPHY_CTRL_ENOTGIDDETECT 0x00000080
-#define BM_USBPHY_CTRL_ENIRQDEVPLUGIN 0x00000800
-#define BM_USBPHY_CTRL_CLKGATE 0x40000000
-#define BM_USBPHY_CTRL_SFTRST 0x80000000
-
-#define HW_USBPHY_STATUS 0x40
-#define BM_USBPHY_STATUS_DEVPLUGIN_STATUS 0x00000040
-#define BM_USBPHY_STATUS_OTGID_STATUS 0x00000100
diff --git a/arch/arm/mach-stmp378x/stmp378x.c b/arch/arm/mach-stmp378x/stmp378x.c
deleted file mode 100644
index c2f9fe0..0000000
--- a/arch/arm/mach-stmp378x/stmp378x.c
+++ /dev/null
@@ -1,299 +0,0 @@
-/*
- * Freescale STMP378X platform support
- *
- * Embedded Alley Solutions, Inc <source@embeddedalley.com>
- *
- * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/platform_device.h>
-#include <linux/irq.h>
-#include <linux/dma-mapping.h>
-
-#include <asm/dma.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/irq.h>
-#include <asm/mach/map.h>
-#include <asm/mach/time.h>
-
-#include <mach/pins.h>
-#include <mach/pinmux.h>
-#include <mach/dma.h>
-#include <mach/hardware.h>
-#include <mach/system.h>
-#include <mach/platform.h>
-#include <mach/stmp3xxx.h>
-#include <mach/regs-icoll.h>
-#include <mach/regs-apbh.h>
-#include <mach/regs-apbx.h>
-#include <mach/regs-pxp.h>
-#include <mach/regs-i2c.h>
-
-#include "stmp378x.h"
-/*
- * IRQ handling
- */
-static void stmp378x_ack_irq(struct irq_data *d)
-{
- /* Tell ICOLL to release IRQ line */
- __raw_writel(0, REGS_ICOLL_BASE + HW_ICOLL_VECTOR);
-
- /* ACK current interrupt */
- __raw_writel(0x01 /* BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 */,
- REGS_ICOLL_BASE + HW_ICOLL_LEVELACK);
-
- /* Barrier */
- (void)__raw_readl(REGS_ICOLL_BASE + HW_ICOLL_STAT);
-}
-
-static void stmp378x_mask_irq(struct irq_data *d)
-{
- /* IRQ disable */
- stmp3xxx_clearl(BM_ICOLL_INTERRUPTn_ENABLE,
- REGS_ICOLL_BASE + HW_ICOLL_INTERRUPTn + d->irq * 0x10);
-}
-
-static void stmp378x_unmask_irq(struct irq_data *d)
-{
- /* IRQ enable */
- stmp3xxx_setl(BM_ICOLL_INTERRUPTn_ENABLE,
- REGS_ICOLL_BASE + HW_ICOLL_INTERRUPTn + d->irq * 0x10);
-}
-
-static struct irq_chip stmp378x_chip = {
- .irq_ack = stmp378x_ack_irq,
- .irq_mask = stmp378x_mask_irq,
- .irq_unmask = stmp378x_unmask_irq,
-};
-
-void __init stmp378x_init_irq(void)
-{
- stmp3xxx_init_irq(&stmp378x_chip);
-}
-
-/*
- * DMA interrupt handling
- */
-void stmp3xxx_arch_dma_enable_interrupt(int channel)
-{
- void __iomem *c1, *c2;
-
- switch (STMP3XXX_DMA_BUS(channel)) {
- case STMP3XXX_BUS_APBH:
- c1 = REGS_APBH_BASE + HW_APBH_CTRL1;
- c2 = REGS_APBH_BASE + HW_APBH_CTRL2;
- break;
-
- case STMP3XXX_BUS_APBX:
- c1 = REGS_APBX_BASE + HW_APBX_CTRL1;
- c2 = REGS_APBX_BASE + HW_APBX_CTRL2;
- break;
-
- default:
- return;
- }
- stmp3xxx_setl(1 << (16 + STMP3XXX_DMA_CHANNEL(channel)), c1);
- stmp3xxx_setl(1 << (16 + STMP3XXX_DMA_CHANNEL(channel)), c2);
-}
-EXPORT_SYMBOL(stmp3xxx_arch_dma_enable_interrupt);
-
-void stmp3xxx_arch_dma_clear_interrupt(int channel)
-{
- void __iomem *c1, *c2;
-
- switch (STMP3XXX_DMA_BUS(channel)) {
- case STMP3XXX_BUS_APBH:
- c1 = REGS_APBH_BASE + HW_APBH_CTRL1;
- c2 = REGS_APBH_BASE + HW_APBH_CTRL2;
- break;
-
- case STMP3XXX_BUS_APBX:
- c1 = REGS_APBX_BASE + HW_APBX_CTRL1;
- c2 = REGS_APBX_BASE + HW_APBX_CTRL2;
- break;
-
- default:
- return;
- }
- stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel), c1);
- stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel), c2);
-}
-EXPORT_SYMBOL(stmp3xxx_arch_dma_clear_interrupt);
-
-int stmp3xxx_arch_dma_is_interrupt(int channel)
-{
- int r = 0;
-
- switch (STMP3XXX_DMA_BUS(channel)) {
- case STMP3XXX_BUS_APBH:
- r = __raw_readl(REGS_APBH_BASE + HW_APBH_CTRL1) &
- (1 << STMP3XXX_DMA_CHANNEL(channel));
- break;
-
- case STMP3XXX_BUS_APBX:
- r = __raw_readl(REGS_APBX_BASE + HW_APBX_CTRL1) &
- (1 << STMP3XXX_DMA_CHANNEL(channel));
- break;
- }
- return r;
-}
-EXPORT_SYMBOL(stmp3xxx_arch_dma_is_interrupt);
-
-void stmp3xxx_arch_dma_reset_channel(int channel)
-{
- unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
- void __iomem *c0;
- u32 mask;
-
- switch (STMP3XXX_DMA_BUS(channel)) {
- case STMP3XXX_BUS_APBH:
- c0 = REGS_APBH_BASE + HW_APBH_CTRL0;
- mask = chbit << BP_APBH_CTRL0_RESET_CHANNEL;
- break;
- case STMP3XXX_BUS_APBX:
- c0 = REGS_APBX_BASE + HW_APBX_CHANNEL_CTRL;
- mask = chbit << BP_APBX_CHANNEL_CTRL_RESET_CHANNEL;
- break;
- default:
- return;
- }
-
- /* Reset channel and wait for it to complete */
- stmp3xxx_setl(mask, c0);
- while (__raw_readl(c0) & mask)
- cpu_relax();
-}
-EXPORT_SYMBOL(stmp3xxx_arch_dma_reset_channel);
-
-void stmp3xxx_arch_dma_freeze(int channel)
-{
- unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
- u32 mask = 1 << chbit;
-
- switch (STMP3XXX_DMA_BUS(channel)) {
- case STMP3XXX_BUS_APBH:
- stmp3xxx_setl(mask, REGS_APBH_BASE + HW_APBH_CTRL0);
- break;
- case STMP3XXX_BUS_APBX:
- stmp3xxx_setl(mask, REGS_APBX_BASE + HW_APBX_CHANNEL_CTRL);
- break;
- }
-}
-EXPORT_SYMBOL(stmp3xxx_arch_dma_freeze);
-
-void stmp3xxx_arch_dma_unfreeze(int channel)
-{
- unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
- u32 mask = 1 << chbit;
-
- switch (STMP3XXX_DMA_BUS(channel)) {
- case STMP3XXX_BUS_APBH:
- stmp3xxx_clearl(mask, REGS_APBH_BASE + HW_APBH_CTRL0);
- break;
- case STMP3XXX_BUS_APBX:
- stmp3xxx_clearl(mask, REGS_APBX_BASE + HW_APBX_CHANNEL_CTRL);
- break;
- }
-}
-EXPORT_SYMBOL(stmp3xxx_arch_dma_unfreeze);
-
-/*
- * The registers are all very closely mapped, so we might as well map them all
- * with a single mapping
- *
- * Logical Physical
- * f0000000 80000000 On-chip registers
- * f1000000 00000000 32k on-chip SRAM
- */
-
-static struct map_desc stmp378x_io_desc[] __initdata = {
- {
- .virtual = (u32)STMP3XXX_REGS_BASE,
- .pfn = __phys_to_pfn(STMP3XXX_REGS_PHBASE),
- .length = STMP3XXX_REGS_SIZE,
- .type = MT_DEVICE,
- },
- {
- .virtual = (u32)STMP3XXX_OCRAM_BASE,
- .pfn = __phys_to_pfn(STMP3XXX_OCRAM_PHBASE),
- .length = STMP3XXX_OCRAM_SIZE,
- .type = MT_DEVICE,
- },
-};
-
-
-static u64 common_dmamask = DMA_BIT_MASK(32);
-
-/*
- * devices that are present only on stmp378x, not on all 3xxx boards:
- * PxP
- * I2C
- */
-static struct resource pxp_resource[] = {
- {
- .flags = IORESOURCE_MEM,
- .start = REGS_PXP_PHYS,
- .end = REGS_PXP_PHYS + REGS_PXP_SIZE,
- }, {
- .flags = IORESOURCE_IRQ,
- .start = IRQ_PXP,
- .end = IRQ_PXP,
- },
-};
-
-struct platform_device stmp378x_pxp = {
- .name = "stmp3xxx-pxp",
- .id = -1,
- .dev = {
- .dma_mask = &common_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- .num_resources = ARRAY_SIZE(pxp_resource),
- .resource = pxp_resource,
-};
-
-static struct resource i2c_resources[] = {
- {
- .flags = IORESOURCE_IRQ,
- .start = IRQ_I2C_ERROR,
- .end = IRQ_I2C_ERROR,
- }, {
- .flags = IORESOURCE_MEM,
- .start = REGS_I2C_PHYS,
- .end = REGS_I2C_PHYS + REGS_I2C_SIZE,
- }, {
- .flags = IORESOURCE_DMA,
- .start = STMP3XXX_DMA(3, STMP3XXX_BUS_APBX),
- .end = STMP3XXX_DMA(3, STMP3XXX_BUS_APBX),
- },
-};
-
-struct platform_device stmp378x_i2c = {
- .name = "i2c_stmp3xxx",
- .id = 0,
- .dev = {
- .dma_mask = &common_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- .resource = i2c_resources,
- .num_resources = ARRAY_SIZE(i2c_resources),
-};
-
-void __init stmp378x_map_io(void)
-{
- iotable_init(stmp378x_io_desc, ARRAY_SIZE(stmp378x_io_desc));
-}
diff --git a/arch/arm/mach-stmp378x/stmp378x.h b/arch/arm/mach-stmp378x/stmp378x.h
deleted file mode 100644
index 0dc15b3..0000000
--- a/arch/arm/mach-stmp378x/stmp378x.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Freescale STMP37XX/STMP378X internal functions and data declarations
- *
- * Embedded Alley Solutions, Inc <source@embeddedalley.com>
- *
- * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#ifndef __MACH_STMP378X_H
-#define __MACH_STMP378X_H
-
-void stmp378x_map_io(void);
-void stmp378x_init_irq(void);
-
-extern struct platform_device stmp378x_pxp, stmp378x_i2c;
-#endif /* __MACH_STMP378X_COMMON_H */
diff --git a/arch/arm/mach-stmp378x/stmp378x_devb.c b/arch/arm/mach-stmp378x/stmp378x_devb.c
deleted file mode 100644
index 0615884..0000000
--- a/arch/arm/mach-stmp378x/stmp378x_devb.c
+++ /dev/null
@@ -1,332 +0,0 @@
-/*
- * Freescale STMP378X development board support
- *
- * Embedded Alley Solutions, Inc <source@embeddedalley.com>
- *
- * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/io.h>
-#include <linux/platform_device.h>
-#include <linux/delay.h>
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/spi/spi.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-
-#include <mach/pins.h>
-#include <mach/pinmux.h>
-#include <mach/platform.h>
-#include <mach/stmp3xxx.h>
-#include <mach/mmc.h>
-#include <mach/gpmi.h>
-
-#include "stmp378x.h"
-
-static struct platform_device *devices[] = {
- &stmp3xxx_dbguart,
- &stmp3xxx_appuart,
- &stmp3xxx_watchdog,
- &stmp3xxx_touchscreen,
- &stmp3xxx_rtc,
- &stmp3xxx_keyboard,
- &stmp3xxx_framebuffer,
- &stmp3xxx_backlight,
- &stmp3xxx_rotdec,
- &stmp3xxx_persistent,
- &stmp3xxx_dcp_bootstream,
- &stmp3xxx_dcp,
- &stmp3xxx_battery,
- &stmp378x_pxp,
- &stmp378x_i2c,
-};
-
-static struct pin_desc i2c_pins_desc[] = {
- { PINID_I2C_SCL, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
- { PINID_I2C_SDA, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
-};
-
-static struct pin_group i2c_pins = {
- .pins = i2c_pins_desc,
- .nr_pins = ARRAY_SIZE(i2c_pins_desc),
-};
-
-static struct pin_desc dbguart_pins_0[] = {
- { PINID_PWM0, PIN_FUN3, },
- { PINID_PWM1, PIN_FUN3, },
-};
-
-static struct pin_group dbguart_pins[] = {
- [0] = {
- .pins = dbguart_pins_0,
- .nr_pins = ARRAY_SIZE(dbguart_pins_0),
- },
-};
-
-static int dbguart_pins_control(int id, int request)
-{
- int r = 0;
-
- if (request)
- r = stmp3xxx_request_pin_group(&dbguart_pins[id], "debug uart");
- else
- stmp3xxx_release_pin_group(&dbguart_pins[id], "debug uart");
- return r;
-}
-
-static struct pin_desc appuart_pins_0[] = {
- { PINID_AUART1_CTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
- { PINID_AUART1_RTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
- { PINID_AUART1_RX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
- { PINID_AUART1_TX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
-};
-
-static struct pin_desc appuart_pins_1[] = {
-#if 0 /* enable these when second appuart will be connected */
- { PINID_AUART2_CTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
- { PINID_AUART2_RTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
- { PINID_AUART2_RX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
- { PINID_AUART2_TX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
-#endif
-};
-
-static struct pin_desc mmc_pins_desc[] = {
- { PINID_SSP1_DATA0, PIN_FUN1, PIN_8MA, PIN_3_3V, 1 },
- { PINID_SSP1_DATA1, PIN_FUN1, PIN_8MA, PIN_3_3V, 1 },
- { PINID_SSP1_DATA2, PIN_FUN1, PIN_8MA, PIN_3_3V, 1 },
- { PINID_SSP1_DATA3, PIN_FUN1, PIN_8MA, PIN_3_3V, 1 },
- { PINID_SSP1_CMD, PIN_FUN1, PIN_8MA, PIN_3_3V, 1 },
- { PINID_SSP1_SCK, PIN_FUN1, PIN_8MA, PIN_3_3V, 0 },
- { PINID_SSP1_DETECT, PIN_FUN1, PIN_8MA, PIN_3_3V, 0 },
-};
-
-static struct pin_group mmc_pins = {
- .pins = mmc_pins_desc,
- .nr_pins = ARRAY_SIZE(mmc_pins_desc),
-};
-
-static int stmp3xxxmmc_get_wp(void)
-{
- return gpio_get_value(PINID_PWM4);
-}
-
-static int stmp3xxxmmc_hw_init_ssp1(void)
-{
- int ret;
-
- ret = stmp3xxx_request_pin_group(&mmc_pins, "mmc");
- if (ret)
- goto out;
-
- /* Configure write protect GPIO pin */
- ret = gpio_request(PINID_PWM4, "mmc wp");
- if (ret)
- goto out_wp;
-
- gpio_direction_input(PINID_PWM4);
-
- /* Configure POWER pin as gpio to drive power to MMC slot */
- ret = gpio_request(PINID_PWM3, "mmc power");
- if (ret)
- goto out_power;
-
- gpio_direction_output(PINID_PWM3, 0);
- mdelay(100);
-
- return 0;
-
-out_power:
- gpio_free(PINID_PWM4);
-out_wp:
- stmp3xxx_release_pin_group(&mmc_pins, "mmc");
-out:
- return ret;
-}
-
-static void stmp3xxxmmc_hw_release_ssp1(void)
-{
- gpio_free(PINID_PWM3);
- gpio_free(PINID_PWM4);
- stmp3xxx_release_pin_group(&mmc_pins, "mmc");
-}
-
-static void stmp3xxxmmc_cmd_pullup_ssp1(int enable)
-{
- stmp3xxx_pin_pullup(PINID_SSP1_CMD, enable, "mmc");
-}
-
-static unsigned long
-stmp3xxxmmc_setclock_ssp1(void __iomem *base, unsigned long hz)
-{
- struct clk *ssp, *parent;
- char *p;
- long r;
-
- ssp = clk_get(NULL, "ssp");
-
- /* using SSP1, no timeout, clock rate 1 */
- writel(BF(2, SSP_TIMING_CLOCK_DIVIDE) |
- BF(0xFFFF, SSP_TIMING_TIMEOUT),
- base + HW_SSP_TIMING);
-
- p = (hz > 1000000) ? "io" : "osc_24M";
- parent = clk_get(NULL, p);
- clk_set_parent(ssp, parent);
- r = clk_set_rate(ssp, 2 * hz / 1000);
- clk_put(parent);
- clk_put(ssp);
-
- return hz;
-}
-
-static struct stmp3xxxmmc_platform_data mmc_data = {
- .hw_init = stmp3xxxmmc_hw_init_ssp1,
- .hw_release = stmp3xxxmmc_hw_release_ssp1,
- .get_wp = stmp3xxxmmc_get_wp,
- .cmd_pullup = stmp3xxxmmc_cmd_pullup_ssp1,
- .setclock = stmp3xxxmmc_setclock_ssp1,
-};
-
-
-static struct pin_group appuart_pins[] = {
- [0] = {
- .pins = appuart_pins_0,
- .nr_pins = ARRAY_SIZE(appuart_pins_0),
- },
- [1] = {
- .pins = appuart_pins_1,
- .nr_pins = ARRAY_SIZE(appuart_pins_1),
- },
-};
-
-static struct pin_desc ssp1_pins_desc[] = {
- { PINID_SSP1_SCK, PIN_FUN1, PIN_8MA, PIN_3_3V, 0, },
- { PINID_SSP1_CMD, PIN_FUN1, PIN_4MA, PIN_3_3V, 0, },
- { PINID_SSP1_DATA0, PIN_FUN1, PIN_4MA, PIN_3_3V, 0, },
- { PINID_SSP1_DATA3, PIN_FUN1, PIN_4MA, PIN_3_3V, 0, },
-};
-
-static struct pin_desc ssp2_pins_desc[] = {
- { PINID_GPMI_WRN, PIN_FUN3, PIN_8MA, PIN_3_3V, 0, },
- { PINID_GPMI_RDY1, PIN_FUN3, PIN_4MA, PIN_3_3V, 0, },
- { PINID_GPMI_D00, PIN_FUN3, PIN_4MA, PIN_3_3V, 0, },
- { PINID_GPMI_D03, PIN_FUN3, PIN_4MA, PIN_3_3V, 0, },
-};
-
-static struct pin_group ssp1_pins = {
- .pins = ssp1_pins_desc,
- .nr_pins = ARRAY_SIZE(ssp1_pins_desc),
-};
-
-static struct pin_group ssp2_pins = {
- .pins = ssp1_pins_desc,
- .nr_pins = ARRAY_SIZE(ssp2_pins_desc),
-};
-
-static struct pin_desc gpmi_pins_desc[] = {
- { PINID_GPMI_CE0N, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
- { PINID_GPMI_CE1N, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
- { PINID_GMPI_CE2N, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
- { PINID_GPMI_CLE, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
- { PINID_GPMI_ALE, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
- { PINID_GPMI_WPN, PIN_FUN1, PIN_12MA, PIN_3_3V, 0 },
- { PINID_GPMI_RDY1, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
- { PINID_GPMI_D00, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
- { PINID_GPMI_D01, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
- { PINID_GPMI_D02, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
- { PINID_GPMI_D03, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
- { PINID_GPMI_D04, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
- { PINID_GPMI_D05, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
- { PINID_GPMI_D06, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
- { PINID_GPMI_D07, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
- { PINID_GPMI_RDY0, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
- { PINID_GPMI_RDY2, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
- { PINID_GPMI_RDY3, PIN_FUN1, PIN_4MA, PIN_3_3V, 0 },
- { PINID_GPMI_WRN, PIN_FUN1, PIN_12MA, PIN_3_3V, 0 },
- { PINID_GPMI_RDN, PIN_FUN1, PIN_12MA, PIN_3_3V, 0 },
-};
-
-static struct pin_group gpmi_pins = {
- .pins = gpmi_pins_desc,
- .nr_pins = ARRAY_SIZE(gpmi_pins_desc),
-};
-
-static struct mtd_partition gpmi_partitions[] = {
- [0] = {
- .name = "boot",
- .size = 10 * SZ_1M,
- .offset = 0,
- },
- [1] = {
- .name = "data",
- .size = MTDPART_SIZ_FULL,
- .offset = MTDPART_OFS_APPEND,
- },
-};
-
-static struct gpmi_platform_data gpmi_data = {
- .pins = &gpmi_pins,
- .nr_parts = ARRAY_SIZE(gpmi_partitions),
- .parts = gpmi_partitions,
- .part_types = { "cmdline", NULL },
-};
-
-static struct spi_board_info spi_board_info[] __initdata = {
-#if defined(CONFIG_ENC28J60) || defined(CONFIG_ENC28J60_MODULE)
- {
- .modalias = "enc28j60",
- .max_speed_hz = 6 * 1000 * 1000,
- .bus_num = 1,
- .chip_select = 0,
- .platform_data = NULL,
- },
-#endif
-};
-
-static void __init stmp378x_devb_init(void)
-{
- stmp3xxx_pinmux_init(NR_REAL_IRQS);
-
- /* init stmp3xxx platform */
- stmp3xxx_init();
-
- stmp3xxx_dbguart.dev.platform_data = dbguart_pins_control;
- stmp3xxx_appuart.dev.platform_data = appuart_pins;
- stmp3xxx_mmc.dev.platform_data = &mmc_data;
- stmp3xxx_gpmi.dev.platform_data = &gpmi_data;
- stmp3xxx_spi1.dev.platform_data = &ssp1_pins;
- stmp3xxx_spi2.dev.platform_data = &ssp2_pins;
- stmp378x_i2c.dev.platform_data = &i2c_pins;
-
- /* register spi devices */
- spi_register_board_info(spi_board_info, ARRAY_SIZE(spi_board_info));
-
- /* add board's devices */
- platform_add_devices(devices, ARRAY_SIZE(devices));
-
- /* add devices selected by command line ssp1= and ssp2= options */
- stmp3xxx_ssp1_device_register();
- stmp3xxx_ssp2_device_register();
-}
-
-MACHINE_START(STMP378X, "STMP378X")
- .boot_params = 0x40000100,
- .map_io = stmp378x_map_io,
- .init_irq = stmp378x_init_irq,
- .timer = &stmp3xxx_timer,
- .init_machine = stmp378x_devb_init,
-MACHINE_END
diff --git a/arch/arm/mach-stmp37xx/Makefile b/arch/arm/mach-stmp37xx/Makefile
deleted file mode 100644
index 57deffd..0000000
--- a/arch/arm/mach-stmp37xx/Makefile
+++ /dev/null
@@ -1,2 +0,0 @@
-obj-$(CONFIG_ARCH_STMP37XX) += stmp37xx.o
-obj-$(CONFIG_MACH_STMP37XX) += stmp37xx_devb.o
diff --git a/arch/arm/mach-stmp37xx/Makefile.boot b/arch/arm/mach-stmp37xx/Makefile.boot
deleted file mode 100644
index 1568ad4..0000000
--- a/arch/arm/mach-stmp37xx/Makefile.boot
+++ /dev/null
@@ -1,3 +0,0 @@
- zreladdr-y := 0x40008000
-params_phys-y := 0x40000100
-initrd_phys-y := 0x40800000
diff --git a/arch/arm/mach-stmp37xx/include/mach/entry-macro.S b/arch/arm/mach-stmp37xx/include/mach/entry-macro.S
deleted file mode 100644
index fed2787..0000000
--- a/arch/arm/mach-stmp37xx/include/mach/entry-macro.S
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * Low-level IRQ helper macros for Freescale STMP37XX
- *
- * Embedded Alley Solutions, Inc <source@embeddedalley.com>
- *
- * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
- .macro disable_fiq
- .endm
-
- .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
-
- mov \base, #0xf0000000 @ vm address of IRQ controller
- ldr \irqnr, [\base, #0x30] @ HW_ICOLL_STAT
- cmp \irqnr, #0x3f
- movne \irqstat, #0 @ Ack this IRQ
- strne \irqstat, [\base, #0x00]@ HW_ICOLL_VECTOR
- moveqs \irqnr, #0 @ Zero flag set for no IRQ
-
- .endm
-
- .macro get_irqnr_preamble, base, tmp
- .endm
-
- .macro arch_ret_to_user, tmp1, tmp2
- .endm
diff --git a/arch/arm/mach-stmp37xx/include/mach/irqs.h b/arch/arm/mach-stmp37xx/include/mach/irqs.h
deleted file mode 100644
index 98f1293..0000000
--- a/arch/arm/mach-stmp37xx/include/mach/irqs.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * Freescale STMP37XX interrupts
- *
- * Copyright (C) 2005 Sigmatel Inc
- *
- * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#ifndef _ASM_ARCH_IRQS_H
-#define _ASM_ARCH_IRQS_H
-
-#define IRQ_DEBUG_UART 0
-#define IRQ_COMMS_RX 1
-#define IRQ_COMMS_TX 1
-#define IRQ_SSP2_ERROR 2
-#define IRQ_VDD5V 3
-#define IRQ_HEADPHONE_SHORT 4
-#define IRQ_DAC_DMA 5
-#define IRQ_DAC_ERROR 6
-#define IRQ_ADC_DMA 7
-#define IRQ_ADC_ERROR 8
-#define IRQ_SPDIF_DMA 9
-#define IRQ_SAIF2_DMA 9
-#define IRQ_SPDIF_ERROR 10
-#define IRQ_SAIF1_IRQ 10
-#define IRQ_SAIF2_IRQ 10
-#define IRQ_USB_CTRL 11
-#define IRQ_USB_WAKEUP 12
-#define IRQ_GPMI_DMA 13
-#define IRQ_SSP1_DMA 14
-#define IRQ_SSP_ERROR 15
-#define IRQ_GPIO0 16
-#define IRQ_GPIO1 17
-#define IRQ_GPIO2 18
-#define IRQ_SAIF1_DMA 19
-#define IRQ_SSP2_DMA 20
-#define IRQ_ECC8_IRQ 21
-#define IRQ_RTC_ALARM 22
-#define IRQ_UARTAPP_TX_DMA 23
-#define IRQ_UARTAPP_INTERNAL 24
-#define IRQ_UARTAPP_RX_DMA 25
-#define IRQ_I2C_DMA 26
-#define IRQ_I2C_ERROR 27
-#define IRQ_TIMER0 28
-#define IRQ_TIMER1 29
-#define IRQ_TIMER2 30
-#define IRQ_TIMER3 31
-#define IRQ_BATT_BRNOUT 32
-#define IRQ_VDDD_BRNOUT 33
-#define IRQ_VDDIO_BRNOUT 34
-#define IRQ_VDD18_BRNOUT 35
-#define IRQ_TOUCH_DETECT 36
-#define IRQ_LRADC_CH0 37
-#define IRQ_LRADC_CH1 38
-#define IRQ_LRADC_CH2 39
-#define IRQ_LRADC_CH3 40
-#define IRQ_LRADC_CH4 41
-#define IRQ_LRADC_CH5 42
-#define IRQ_LRADC_CH6 43
-#define IRQ_LRADC_CH7 44
-#define IRQ_LCDIF_DMA 45
-#define IRQ_LCDIF_ERROR 46
-#define IRQ_DIGCTL_DEBUG_TRAP 47
-#define IRQ_RTC_1MSEC 48
-#define IRQ_DRI_DMA 49
-#define IRQ_DRI_ATTENTION 50
-#define IRQ_GPMI_ATTENTION 51
-#define IRQ_IR 52
-#define IRQ_DCP_VMI 53
-#define IRQ_DCP 54
-#define IRQ_RESERVED_55 55
-#define IRQ_RESERVED_56 56
-#define IRQ_RESERVED_57 57
-#define IRQ_RESERVED_58 58
-#define IRQ_RESERVED_59 59
-#define SW_IRQ_60 60
-#define SW_IRQ_61 61
-#define SW_IRQ_62 62
-#define SW_IRQ_63 63
-
-#define NR_REAL_IRQS 64
-#define NR_IRQS (NR_REAL_IRQS + 32 * 3)
-
-/* TIMER and BRNOUT are FIQ capable */
-#define FIQ_START IRQ_TIMER0
-
-/* Hard disk IRQ is a GPMI attention IRQ */
-#define IRQ_HARDDISK IRQ_GPMI_ATTENTION
-
-#endif /* _ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-stmp37xx/include/mach/pins.h b/arch/arm/mach-stmp37xx/include/mach/pins.h
deleted file mode 100644
index d56de0c..0000000
--- a/arch/arm/mach-stmp37xx/include/mach/pins.h
+++ /dev/null
@@ -1,147 +0,0 @@
-/*
- * Freescale STMP37XX SoC pin multiplexing
- *
- * Author: Vladislav Buzov <vbuzov@embeddedalley.com>
- *
- * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#ifndef __ASM_ARCH_PINS_H
-#define __ASM_ARCH_PINS_H
-
-/*
- * Define all STMP37XX pins, a pin name corresponds to a STMP37xx hardware
- * interface this pin belongs to.
- */
-
-/* Bank 0 */
-#define PINID_GPMI_D00 STMP3XXX_PINID(0, 0)
-#define PINID_GPMI_D01 STMP3XXX_PINID(0, 1)
-#define PINID_GPMI_D02 STMP3XXX_PINID(0, 2)
-#define PINID_GPMI_D03 STMP3XXX_PINID(0, 3)
-#define PINID_GPMI_D04 STMP3XXX_PINID(0, 4)
-#define PINID_GPMI_D05 STMP3XXX_PINID(0, 5)
-#define PINID_GPMI_D06 STMP3XXX_PINID(0, 6)
-#define PINID_GPMI_D07 STMP3XXX_PINID(0, 7)
-#define PINID_GPMI_D08 STMP3XXX_PINID(0, 8)
-#define PINID_GPMI_D09 STMP3XXX_PINID(0, 9)
-#define PINID_GPMI_D10 STMP3XXX_PINID(0, 10)
-#define PINID_GPMI_D11 STMP3XXX_PINID(0, 11)
-#define PINID_GPMI_D12 STMP3XXX_PINID(0, 12)
-#define PINID_GPMI_D13 STMP3XXX_PINID(0, 13)
-#define PINID_GPMI_D14 STMP3XXX_PINID(0, 14)
-#define PINID_GPMI_D15 STMP3XXX_PINID(0, 15)
-#define PINID_GPMI_A0 STMP3XXX_PINID(0, 16)
-#define PINID_GPMI_A1 STMP3XXX_PINID(0, 17)
-#define PINID_GPMI_A2 STMP3XXX_PINID(0, 18)
-#define PINID_GPMI_RDY0 STMP3XXX_PINID(0, 19)
-#define PINID_GPMI_RDY2 STMP3XXX_PINID(0, 20)
-#define PINID_GPMI_RDY3 STMP3XXX_PINID(0, 21)
-#define PINID_GPMI_RESETN STMP3XXX_PINID(0, 22)
-#define PINID_GPMI_IRQ STMP3XXX_PINID(0, 23)
-#define PINID_GPMI_WRN STMP3XXX_PINID(0, 24)
-#define PINID_GPMI_RDN STMP3XXX_PINID(0, 25)
-#define PINID_UART2_CTS STMP3XXX_PINID(0, 26)
-#define PINID_UART2_RTS STMP3XXX_PINID(0, 27)
-#define PINID_UART2_RX STMP3XXX_PINID(0, 28)
-#define PINID_UART2_TX STMP3XXX_PINID(0, 29)
-
-/* Bank 1 */
-#define PINID_LCD_D00 STMP3XXX_PINID(1, 0)
-#define PINID_LCD_D01 STMP3XXX_PINID(1, 1)
-#define PINID_LCD_D02 STMP3XXX_PINID(1, 2)
-#define PINID_LCD_D03 STMP3XXX_PINID(1, 3)
-#define PINID_LCD_D04 STMP3XXX_PINID(1, 4)
-#define PINID_LCD_D05 STMP3XXX_PINID(1, 5)
-#define PINID_LCD_D06 STMP3XXX_PINID(1, 6)
-#define PINID_LCD_D07 STMP3XXX_PINID(1, 7)
-#define PINID_LCD_D08 STMP3XXX_PINID(1, 8)
-#define PINID_LCD_D09 STMP3XXX_PINID(1, 9)
-#define PINID_LCD_D10 STMP3XXX_PINID(1, 10)
-#define PINID_LCD_D11 STMP3XXX_PINID(1, 11)
-#define PINID_LCD_D12 STMP3XXX_PINID(1, 12)
-#define PINID_LCD_D13 STMP3XXX_PINID(1, 13)
-#define PINID_LCD_D14 STMP3XXX_PINID(1, 14)
-#define PINID_LCD_D15 STMP3XXX_PINID(1, 15)
-#define PINID_LCD_RESET STMP3XXX_PINID(1, 16)
-#define PINID_LCD_RS STMP3XXX_PINID(1, 17)
-#define PINID_LCD_WR_RWN STMP3XXX_PINID(1, 18)
-#define PINID_LCD_RD_E STMP3XXX_PINID(1, 19)
-#define PINID_LCD_CS STMP3XXX_PINID(1, 20)
-#define PINID_LCD_BUSY STMP3XXX_PINID(1, 21)
-#define PINID_SSP1_CMD STMP3XXX_PINID(1, 22)
-#define PINID_SSP1_SCK STMP3XXX_PINID(1, 23)
-#define PINID_SSP1_DATA0 STMP3XXX_PINID(1, 24)
-#define PINID_SSP1_DATA1 STMP3XXX_PINID(1, 25)
-#define PINID_SSP1_DATA2 STMP3XXX_PINID(1, 26)
-#define PINID_SSP1_DATA3 STMP3XXX_PINID(1, 27)
-#define PINID_SSP1_DETECT STMP3XXX_PINID(1, 28)
-
-/* Bank 2 */
-#define PINID_PWM0 STMP3XXX_PINID(2, 0)
-#define PINID_PWM1 STMP3XXX_PINID(2, 1)
-#define PINID_PWM2 STMP3XXX_PINID(2, 2)
-#define PINID_PWM3 STMP3XXX_PINID(2, 3)
-#define PINID_PWM4 STMP3XXX_PINID(2, 4)
-#define PINID_I2C_SCL STMP3XXX_PINID(2, 5)
-#define PINID_I2C_SDA STMP3XXX_PINID(2, 6)
-#define PINID_ROTTARYA STMP3XXX_PINID(2, 7)
-#define PINID_ROTTARYB STMP3XXX_PINID(2, 8)
-#define PINID_EMI_CKE STMP3XXX_PINID(2, 9)
-#define PINID_EMI_RASN STMP3XXX_PINID(2, 10)
-#define PINID_EMI_CASN STMP3XXX_PINID(2, 11)
-#define PINID_EMI_CE0N STMP3XXX_PINID(2, 12)
-#define PINID_EMI_CE1N STMP3XXX_PINID(2, 13)
-#define PINID_EMI_CE2N STMP3XXX_PINID(2, 14)
-#define PINID_EMI_CE3N STMP3XXX_PINID(2, 15)
-#define PINID_EMI_A00 STMP3XXX_PINID(2, 16)
-#define PINID_EMI_A01 STMP3XXX_PINID(2, 17)
-#define PINID_EMI_A02 STMP3XXX_PINID(2, 18)
-#define PINID_EMI_A03 STMP3XXX_PINID(2, 19)
-#define PINID_EMI_A04 STMP3XXX_PINID(2, 20)
-#define PINID_EMI_A05 STMP3XXX_PINID(2, 21)
-#define PINID_EMI_A06 STMP3XXX_PINID(2, 22)
-#define PINID_EMI_A07 STMP3XXX_PINID(2, 23)
-#define PINID_EMI_A08 STMP3XXX_PINID(2, 24)
-#define PINID_EMI_A09 STMP3XXX_PINID(2, 25)
-#define PINID_EMI_A10 STMP3XXX_PINID(2, 26)
-#define PINID_EMI_A11 STMP3XXX_PINID(2, 27)
-#define PINID_EMI_A12 STMP3XXX_PINID(2, 28)
-#define PINID_EMI_A13 STMP3XXX_PINID(2, 29)
-#define PINID_EMI_A14 STMP3XXX_PINID(2, 30)
-#define PINID_EMI_WEN STMP3XXX_PINID(2, 31)
-
-/* Bank 3 */
-#define PINID_EMI_D00 STMP3XXX_PINID(3, 0)
-#define PINID_EMI_D01 STMP3XXX_PINID(3, 1)
-#define PINID_EMI_D02 STMP3XXX_PINID(3, 2)
-#define PINID_EMI_D03 STMP3XXX_PINID(3, 3)
-#define PINID_EMI_D04 STMP3XXX_PINID(3, 4)
-#define PINID_EMI_D05 STMP3XXX_PINID(3, 5)
-#define PINID_EMI_D06 STMP3XXX_PINID(3, 6)
-#define PINID_EMI_D07 STMP3XXX_PINID(3, 7)
-#define PINID_EMI_D08 STMP3XXX_PINID(3, 8)
-#define PINID_EMI_D09 STMP3XXX_PINID(3, 9)
-#define PINID_EMI_D10 STMP3XXX_PINID(3, 10)
-#define PINID_EMI_D11 STMP3XXX_PINID(3, 11)
-#define PINID_EMI_D12 STMP3XXX_PINID(3, 12)
-#define PINID_EMI_D13 STMP3XXX_PINID(3, 13)
-#define PINID_EMI_D14 STMP3XXX_PINID(3, 14)
-#define PINID_EMI_D15 STMP3XXX_PINID(3, 15)
-#define PINID_EMI_DQS0 STMP3XXX_PINID(3, 16)
-#define PINID_EMI_DQS1 STMP3XXX_PINID(3, 17)
-#define PINID_EMI_DQM0 STMP3XXX_PINID(3, 18)
-#define PINID_EMI_DQM1 STMP3XXX_PINID(3, 19)
-#define PINID_EMI_CLK STMP3XXX_PINID(3, 20)
-#define PINID_EMI_CLKN STMP3XXX_PINID(3, 21)
-
-#endif /* __ASM_ARCH_PINS_H */
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-apbh.h b/arch/arm/mach-stmp37xx/include/mach/regs-apbh.h
deleted file mode 100644
index a323aa9..0000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-apbh.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * stmp37xx: APBH register definitions
- *
- * Copyright (c) 2008 Freescale Semiconductor
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#ifndef _MACH_REGS_APBH
-#define _MACH_REGS_APBH
-
-#define REGS_APBH_BASE (STMP3XXX_REGS_BASE + 0x4000)
-
-#define HW_APBH_CTRL0 0x0
-#define BM_APBH_CTRL0_RESET_CHANNEL 0x00FF0000
-#define BP_APBH_CTRL0_RESET_CHANNEL 16
-#define BM_APBH_CTRL0_CLKGATE 0x40000000
-#define BM_APBH_CTRL0_SFTRST 0x80000000
-
-#define HW_APBH_CTRL1 0x10
-#define BM_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0x00000001
-#define BP_APBH_CTRL1_CH0_CMDCMPLT_IRQ 0
-
-#define HW_APBH_DEVSEL 0x20
-
-#define HW_APBH_CH0_NXTCMDAR (0x50 + 0 * 0x70)
-#define HW_APBH_CH1_NXTCMDAR (0x50 + 1 * 0x70)
-#define HW_APBH_CH2_NXTCMDAR (0x50 + 2 * 0x70)
-#define HW_APBH_CH3_NXTCMDAR (0x50 + 3 * 0x70)
-#define HW_APBH_CH4_NXTCMDAR (0x50 + 4 * 0x70)
-#define HW_APBH_CH5_NXTCMDAR (0x50 + 5 * 0x70)
-#define HW_APBH_CH6_NXTCMDAR (0x50 + 6 * 0x70)
-#define HW_APBH_CH7_NXTCMDAR (0x50 + 7 * 0x70)
-#define HW_APBH_CH8_NXTCMDAR (0x50 + 8 * 0x70)
-#define HW_APBH_CH9_NXTCMDAR (0x50 + 9 * 0x70)
-#define HW_APBH_CH10_NXTCMDAR (0x50 + 10 * 0x70)
-#define HW_APBH_CH11_NXTCMDAR (0x50 + 11 * 0x70)
-#define HW_APBH_CH12_NXTCMDAR (0x50 + 12 * 0x70)
-#define HW_APBH_CH13_NXTCMDAR (0x50 + 13 * 0x70)
-#define HW_APBH_CH14_NXTCMDAR (0x50 + 14 * 0x70)
-#define HW_APBH_CH15_NXTCMDAR (0x50 + 15 * 0x70)
-
-#define HW_APBH_CHn_NXTCMDAR 0x50
-
-#define BM_APBH_CHn_CMD_MODE 0x00000003
-#define BP_APBH_CHn_CMD_MODE 0x00000001
-#define BV_APBH_CHn_CMD_MODE_NOOP 0
-#define BV_APBH_CHn_CMD_MODE_WRITE 1
-#define BV_APBH_CHn_CMD_MODE_READ 2
-#define BV_APBH_CHn_CMD_MODE_SENSE 3
-#define BM_APBH_CHn_CMD_CHAIN 0x00000004
-#define BM_APBH_CHn_CMD_IRQONCMPLT 0x00000008
-#define BM_APBH_CHn_CMD_NANDLOCK 0x00000010
-#define BM_APBH_CHn_CMD_NANDWAIT4READY 0x00000020
-#define BM_APBH_CHn_CMD_SEMAPHORE 0x00000040
-#define BM_APBH_CHn_CMD_WAIT4ENDCMD 0x00000080
-#define BM_APBH_CHn_CMD_CMDWORDS 0x0000F000
-#define BP_APBH_CHn_CMD_CMDWORDS 12
-#define BM_APBH_CHn_CMD_XFER_COUNT 0xFFFF0000
-#define BP_APBH_CHn_CMD_XFER_COUNT 16
-
-#define HW_APBH_CH0_SEMA (0x80 + 0 * 0x70)
-#define HW_APBH_CH1_SEMA (0x80 + 1 * 0x70)
-#define HW_APBH_CH2_SEMA (0x80 + 2 * 0x70)
-#define HW_APBH_CH3_SEMA (0x80 + 3 * 0x70)
-#define HW_APBH_CH4_SEMA (0x80 + 4 * 0x70)
-#define HW_APBH_CH5_SEMA (0x80 + 5 * 0x70)
-#define HW_APBH_CH6_SEMA (0x80 + 6 * 0x70)
-#define HW_APBH_CH7_SEMA (0x80 + 7 * 0x70)
-#define HW_APBH_CH8_SEMA (0x80 + 8 * 0x70)
-#define HW_APBH_CH9_SEMA (0x80 + 9 * 0x70)
-#define HW_APBH_CH10_SEMA (0x80 + 10 * 0x70)
-#define HW_APBH_CH11_SEMA (0x80 + 11 * 0x70)
-#define HW_APBH_CH12_SEMA (0x80 + 12 * 0x70)
-#define HW_APBH_CH13_SEMA (0x80 + 13 * 0x70)
-#define HW_APBH_CH14_SEMA (0x80 + 14 * 0x70)
-#define HW_APBH_CH15_SEMA (0x80 + 15 * 0x70)
-
-#define HW_APBH_CHn_SEMA 0x80
-#define BM_APBH_CHn_SEMA_INCREMENT_SEMA 0x000000FF
-#define BP_APBH_CHn_SEMA_INCREMENT_SEMA 0
-#define BM_APBH_CHn_SEMA_PHORE 0x00FF0000
-#define BP_APBH_CHn_SEMA_PHORE 16
-
-#endif
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-apbx.h b/arch/arm/mach-stmp37xx/include/mach/regs-apbx.h
deleted file mode 100644
index 6d080cd..0000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-apbx.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * stmp37xx: APBX register definitions
- *
- * Copyright (c) 2008 Freescale Semiconductor
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#ifndef _MACH_REGS_APBX
-#define _MACH_REGS_APBX
-
-#define REGS_APBX_BASE (STMP3XXX_REGS_BASE + 0x24000)
-
-#define HW_APBX_CTRL0 0x0
-#define BM_APBX_CTRL0_RESET_CHANNEL 0x00FF0000
-#define BP_APBX_CTRL0_RESET_CHANNEL 16
-#define BM_APBX_CTRL0_CLKGATE 0x40000000
-#define BM_APBX_CTRL0_SFTRST 0x80000000
-
-#define HW_APBX_CTRL1 0x10
-
-#define HW_APBX_DEVSEL 0x20
-
-#define HW_APBX_CH0_NXTCMDAR (0x50 + 0 * 0x70)
-#define HW_APBX_CH1_NXTCMDAR (0x50 + 1 * 0x70)
-#define HW_APBX_CH2_NXTCMDAR (0x50 + 2 * 0x70)
-#define HW_APBX_CH3_NXTCMDAR (0x50 + 3 * 0x70)
-#define HW_APBX_CH4_NXTCMDAR (0x50 + 4 * 0x70)
-#define HW_APBX_CH5_NXTCMDAR (0x50 + 5 * 0x70)
-#define HW_APBX_CH6_NXTCMDAR (0x50 + 6 * 0x70)
-#define HW_APBX_CH7_NXTCMDAR (0x50 + 7 * 0x70)
-#define HW_APBX_CH8_NXTCMDAR (0x50 + 8 * 0x70)
-#define HW_APBX_CH9_NXTCMDAR (0x50 + 9 * 0x70)
-#define HW_APBX_CH10_NXTCMDAR (0x50 + 10 * 0x70)
-#define HW_APBX_CH11_NXTCMDAR (0x50 + 11 * 0x70)
-#define HW_APBX_CH12_NXTCMDAR (0x50 + 12 * 0x70)
-#define HW_APBX_CH13_NXTCMDAR (0x50 + 13 * 0x70)
-#define HW_APBX_CH14_NXTCMDAR (0x50 + 14 * 0x70)
-#define HW_APBX_CH15_NXTCMDAR (0x50 + 15 * 0x70)
-
-#define HW_APBX_CHn_NXTCMDAR 0x50
-#define BM_APBX_CHn_CMD_MODE 0x00000003
-#define BP_APBX_CHn_CMD_MODE 0x00000001
-#define BV_APBX_CHn_CMD_MODE_NOOP 0
-#define BV_APBX_CHn_CMD_MODE_WRITE 1
-#define BV_APBX_CHn_CMD_MODE_READ 2
-#define BV_APBX_CHn_CMD_MODE_SENSE 3
-#define BM_APBX_CHn_CMD_COMMAND 0x00000003
-#define BP_APBX_CHn_CMD_COMMAND 0
-#define BM_APBX_CHn_CMD_CHAIN 0x00000004
-#define BM_APBX_CHn_CMD_IRQONCMPLT 0x00000008
-#define BM_APBX_CHn_CMD_SEMAPHORE 0x00000040
-#define BM_APBX_CHn_CMD_WAIT4ENDCMD 0x00000080
-#define BM_APBX_CHn_CMD_CMDWORDS 0x0000F000
-#define BP_APBX_CHn_CMD_CMDWORDS 12
-#define BM_APBX_CHn_CMD_XFER_COUNT 0xFFFF0000
-#define BP_APBX_CHn_CMD_XFER_COUNT 16
-
-#define HW_APBX_CH0_BAR (0x70 + 0 * 0x70)
-#define HW_APBX_CH1_BAR (0x70 + 1 * 0x70)
-#define HW_APBX_CH2_BAR (0x70 + 2 * 0x70)
-#define HW_APBX_CH3_BAR (0x70 + 3 * 0x70)
-#define HW_APBX_CH4_BAR (0x70 + 4 * 0x70)
-#define HW_APBX_CH5_BAR (0x70 + 5 * 0x70)
-#define HW_APBX_CH6_BAR (0x70 + 6 * 0x70)
-#define HW_APBX_CH7_BAR (0x70 + 7 * 0x70)
-#define HW_APBX_CH8_BAR (0x70 + 8 * 0x70)
-#define HW_APBX_CH9_BAR (0x70 + 9 * 0x70)
-#define HW_APBX_CH10_BAR (0x70 + 10 * 0x70)
-#define HW_APBX_CH11_BAR (0x70 + 11 * 0x70)
-#define HW_APBX_CH12_BAR (0x70 + 12 * 0x70)
-#define HW_APBX_CH13_BAR (0x70 + 13 * 0x70)
-#define HW_APBX_CH14_BAR (0x70 + 14 * 0x70)
-#define HW_APBX_CH15_BAR (0x70 + 15 * 0x70)
-
-#define HW_APBX_CHn_BAR 0x70
-
-#define HW_APBX_CH0_SEMA (0x80 + 0 * 0x70)
-#define HW_APBX_CH1_SEMA (0x80 + 1 * 0x70)
-#define HW_APBX_CH2_SEMA (0x80 + 2 * 0x70)
-#define HW_APBX_CH3_SEMA (0x80 + 3 * 0x70)
-#define HW_APBX_CH4_SEMA (0x80 + 4 * 0x70)
-#define HW_APBX_CH5_SEMA (0x80 + 5 * 0x70)
-#define HW_APBX_CH6_SEMA (0x80 + 6 * 0x70)
-#define HW_APBX_CH7_SEMA (0x80 + 7 * 0x70)
-#define HW_APBX_CH8_SEMA (0x80 + 8 * 0x70)
-#define HW_APBX_CH9_SEMA (0x80 + 9 * 0x70)
-#define HW_APBX_CH10_SEMA (0x80 + 10 * 0x70)
-#define HW_APBX_CH11_SEMA (0x80 + 11 * 0x70)
-#define HW_APBX_CH12_SEMA (0x80 + 12 * 0x70)
-#define HW_APBX_CH13_SEMA (0x80 + 13 * 0x70)
-#define HW_APBX_CH14_SEMA (0x80 + 14 * 0x70)
-#define HW_APBX_CH15_SEMA (0x80 + 15 * 0x70)
-
-#define HW_APBX_CHn_SEMA 0x80
-#define BM_APBX_CHn_SEMA_INCREMENT_SEMA 0x000000FF
-#define BP_APBX_CHn_SEMA_INCREMENT_SEMA 0
-#define BM_APBX_CHn_SEMA_PHORE 0x00FF0000
-#define BP_APBX_CHn_SEMA_PHORE 16
-
-#endif
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-audioin.h b/arch/arm/mach-stmp37xx/include/mach/regs-audioin.h
deleted file mode 100644
index 3b511f9..0000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-audioin.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * stmp37xx: AUDIOIN register definitions
- *
- * Copyright (c) 2008 Freescale Semiconductor
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#define REGS_AUDIOIN_BASE (STMP3XXX_REGS_BASE + 0x4C000)
-
-#define HW_AUDIOIN_CTRL 0x0
-#define BM_AUDIOIN_CTRL_RUN 0x00000001
-#define BP_AUDIOIN_CTRL_RUN 0
-#define BM_AUDIOIN_CTRL_FIFO_ERROR_IRQ_EN 0x00000002
-#define BM_AUDIOIN_CTRL_FIFO_OVERFLOW_IRQ 0x00000004
-#define BM_AUDIOIN_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008
-#define BM_AUDIOIN_CTRL_WORD_LENGTH 0x00000020
-#define BM_AUDIOIN_CTRL_CLKGATE 0x40000000
-#define BM_AUDIOIN_CTRL_SFTRST 0x80000000
-
-#define HW_AUDIOIN_STAT 0x10
-
-#define HW_AUDIOIN_ADCSRR 0x20
-
-#define HW_AUDIOIN_ADCVOLUME 0x30
-#define BM_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0x000000FF
-#define BP_AUDIOIN_ADCVOLUME_VOLUME_RIGHT 0
-#define BM_AUDIOIN_ADCVOLUME_VOLUME_LEFT 0x00FF0000
-#define BP_AUDIOIN_ADCVOLUME_VOLUME_LEFT 16
-
-#define HW_AUDIOIN_ADCDEBUG 0x40
-
-#define HW_AUDIOIN_ADCVOL 0x50
-#define BM_AUDIOIN_ADCVOL_GAIN_RIGHT 0x0000000F
-#define BP_AUDIOIN_ADCVOL_GAIN_RIGHT 0
-#define BM_AUDIOIN_ADCVOL_SELECT_RIGHT 0x00000030
-#define BP_AUDIOIN_ADCVOL_SELECT_RIGHT 4
-#define BM_AUDIOIN_ADCVOL_GAIN_LEFT 0x00000F00
-#define BP_AUDIOIN_ADCVOL_GAIN_LEFT 8
-#define BM_AUDIOIN_ADCVOL_SELECT_LEFT 0x00003000
-#define BP_AUDIOIN_ADCVOL_SELECT_LEFT 12
-#define BM_AUDIOIN_ADCVOL_MUTE 0x01000000
-
-#define HW_AUDIOIN_MICLINE 0x60
-
-#define HW_AUDIOIN_ANACLKCTRL 0x70
-#define BM_AUDIOIN_ANACLKCTRL_CLKGATE 0x80000000
-
-#define HW_AUDIOIN_DATA 0x80
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-audioout.h b/arch/arm/mach-stmp37xx/include/mach/regs-audioout.h
deleted file mode 100644
index ca1942b..0000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-audioout.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * stmp37xx: AUDIOOUT register definitions
- *
- * Copyright (c) 2008 Freescale Semiconductor
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#define REGS_AUDIOOUT_BASE (STMP3XXX_REGS_BASE + 0x48000)
-
-#define HW_AUDIOOUT_CTRL 0x0
-#define BM_AUDIOOUT_CTRL_RUN 0x00000001
-#define BP_AUDIOOUT_CTRL_RUN 0
-#define BM_AUDIOOUT_CTRL_FIFO_ERROR_IRQ_EN 0x00000002
-#define BM_AUDIOOUT_CTRL_FIFO_OVERFLOW_IRQ 0x00000004
-#define BM_AUDIOOUT_CTRL_FIFO_UNDERFLOW_IRQ 0x00000008
-#define BM_AUDIOOUT_CTRL_WORD_LENGTH 0x00000040
-#define BM_AUDIOOUT_CTRL_CLKGATE 0x40000000
-#define BM_AUDIOOUT_CTRL_SFTRST 0x80000000
-
-#define HW_AUDIOOUT_STAT 0x10
-
-#define HW_AUDIOOUT_DACSRR 0x20
-#define BM_AUDIOOUT_DACSRR_SRC_FRAC 0x00001FFF
-#define BP_AUDIOOUT_DACSRR_SRC_FRAC 0
-#define BM_AUDIOOUT_DACSRR_SRC_INT 0x001F0000
-#define BP_AUDIOOUT_DACSRR_SRC_INT 16
-#define BM_AUDIOOUT_DACSRR_SRC_HOLD 0x07000000
-#define BP_AUDIOOUT_DACSRR_SRC_HOLD 24
-#define BM_AUDIOOUT_DACSRR_BASEMULT 0x70000000
-#define BP_AUDIOOUT_DACSRR_BASEMULT 28
-
-#define HW_AUDIOOUT_DACVOLUME 0x30
-#define BM_AUDIOOUT_DACVOLUME_MUTE_RIGHT 0x00000100
-#define BM_AUDIOOUT_DACVOLUME_MUTE_LEFT 0x01000000
-#define BM_AUDIOOUT_DACVOLUME_EN_ZCD 0x02000000
-
-#define HW_AUDIOOUT_DACDEBUG 0x40
-
-#define HW_AUDIOOUT_HPVOL 0x50
-#define BM_AUDIOOUT_HPVOL_MUTE 0x01000000
-#define BM_AUDIOOUT_HPVOL_EN_MSTR_ZCD 0x02000000
-
-#define HW_AUDIOOUT_PWRDN 0x70
-#define BM_AUDIOOUT_PWRDN_HEADPHONE 0x00000001
-#define BP_AUDIOOUT_PWRDN_HEADPHONE 0
-#define BM_AUDIOOUT_PWRDN_CAPLESS 0x00000010
-#define BM_AUDIOOUT_PWRDN_ADC 0x00000100
-#define BM_AUDIOOUT_PWRDN_DAC 0x00001000
-#define BM_AUDIOOUT_PWRDN_RIGHT_ADC 0x00010000
-#define BM_AUDIOOUT_PWRDN_LINEOUT 0x01000000
-
-#define HW_AUDIOOUT_REFCTRL 0x80
-#define BM_AUDIOOUT_REFCTRL_VAG_VAL 0x000000F0
-#define BP_AUDIOOUT_REFCTRL_VAG_VAL 4
-#define BM_AUDIOOUT_REFCTRL_ADC_REFVAL 0x00000F00
-#define BP_AUDIOOUT_REFCTRL_ADC_REFVAL 8
-#define BM_AUDIOOUT_REFCTRL_ADJ_VAG 0x00001000
-#define BM_AUDIOOUT_REFCTRL_ADJ_ADC 0x00002000
-#define BM_AUDIOOUT_REFCTRL_BIAS_CTRL 0x00030000
-#define BP_AUDIOOUT_REFCTRL_BIAS_CTRL 16
-#define BM_AUDIOOUT_REFCTRL_LOW_PWR 0x00080000
-#define BM_AUDIOOUT_REFCTRL_VBG_ADJ 0x00700000
-#define BP_AUDIOOUT_REFCTRL_VBG_ADJ 20
-#define BM_AUDIOOUT_REFCTRL_XTAL_BGR_BIAS 0x01000000
-#define BM_AUDIOOUT_REFCTRL_RAISE_REF 0x02000000
-
-#define HW_AUDIOOUT_ANACTRL 0x90
-#define BM_AUDIOOUT_ANACTRL_HP_CLASSAB 0x00000010
-#define BM_AUDIOOUT_ANACTRL_HP_HOLD_GND 0x00000020
-
-#define HW_AUDIOOUT_TEST 0xA0
-#define BM_AUDIOOUT_TEST_HP_I1_ADJ 0x00C00000
-#define BP_AUDIOOUT_TEST_HP_I1_ADJ 22
-
-#define HW_AUDIOOUT_BISTCTRL 0xB0
-
-#define HW_AUDIOOUT_BISTSTAT0 0xC0
-
-#define HW_AUDIOOUT_BISTSTAT1 0xD0
-
-#define HW_AUDIOOUT_ANACLKCTRL 0xE0
-#define BM_AUDIOOUT_ANACLKCTRL_CLKGATE 0x80000000
-
-#define HW_AUDIOOUT_DATA 0xF0
-
-#define HW_AUDIOOUT_LINEOUTCTRL 0x100
-#define BM_AUDIOOUT_LINEOUTCTRL_VOL_RIGHT 0x0000001F
-#define BP_AUDIOOUT_LINEOUTCTRL_VOL_RIGHT 0
-#define BM_AUDIOOUT_LINEOUTCTRL_VOL_LEFT 0x00001F00
-#define BP_AUDIOOUT_LINEOUTCTRL_VOL_LEFT 8
-#define BM_AUDIOOUT_LINEOUTCTRL_CHARGE_CAP 0x00007000
-#define BP_AUDIOOUT_LINEOUTCTRL_CHARGE_CAP 12
-#define BM_AUDIOOUT_LINEOUTCTRL_VAG_CTRL 0x00F00000
-#define BP_AUDIOOUT_LINEOUTCTRL_VAG_CTRL 20
-#define BM_AUDIOOUT_LINEOUTCTRL_MUTE 0x01000000
-#define BM_AUDIOOUT_LINEOUTCTRL_EN_ZCD 0x02000000
-
-#define HW_AUDIOOUT_VERSION 0x200
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-clkctrl.h b/arch/arm/mach-stmp37xx/include/mach/regs-clkctrl.h
deleted file mode 100644
index 47f5c92..0000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-clkctrl.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * stmp37xx: CLKCTRL register definitions
- *
- * Copyright (c) 2008 Freescale Semiconductor
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#ifndef _MACH_REGS_CLKCTRL
-#define _MACH_REGS_CLKCTRL
-
-#define REGS_CLKCTRL_BASE (STMP3XXX_REGS_BASE + 0x40000)
-
-#define HW_CLKCTRL_PLLCTRL0 0x0
-#define BM_CLKCTRL_PLLCTRL0_EN_USB_CLKS 0x00040000
-
-#define HW_CLKCTRL_CPU 0x20
-#define BM_CLKCTRL_CPU_DIV_CPU 0x0000003F
-#define BP_CLKCTRL_CPU_DIV_CPU 0
-
-#define HW_CLKCTRL_HBUS 0x30
-#define BM_CLKCTRL_HBUS_DIV 0x0000001F
-#define BP_CLKCTRL_HBUS_DIV 0
-
-#define HW_CLKCTRL_XBUS 0x40
-
-#define HW_CLKCTRL_XTAL 0x50
-
-#define HW_CLKCTRL_PIX 0x60
-#define BM_CLKCTRL_PIX_DIV 0x00007FFF
-#define BP_CLKCTRL_PIX_DIV 0
-#define BM_CLKCTRL_PIX_CLKGATE 0x80000000
-
-#define HW_CLKCTRL_SSP 0x70
-
-#define HW_CLKCTRL_GPMI 0x80
-
-#define HW_CLKCTRL_SPDIF 0x90
-
-#define HW_CLKCTRL_EMI 0xA0
-
-#define HW_CLKCTRL_IR 0xB0
-
-#define HW_CLKCTRL_SAIF 0xC0
-
-#define HW_CLKCTRL_FRAC 0xD0
-#define BM_CLKCTRL_FRAC_EMIFRAC 0x00003F00
-#define BP_CLKCTRL_FRAC_EMIFRAC 8
-#define BM_CLKCTRL_FRAC_PIXFRAC 0x003F0000
-#define BP_CLKCTRL_FRAC_PIXFRAC 16
-#define BM_CLKCTRL_FRAC_CLKGATEPIX 0x00800000
-
-#define HW_CLKCTRL_CLKSEQ 0xE0
-#define BM_CLKCTRL_CLKSEQ_BYPASS_PIX 0x00000002
-
-#define HW_CLKCTRL_RESET 0xF0
-#define BM_CLKCTRL_RESET_DIG 0x00000001
-#define BP_CLKCTRL_RESET_DIG 0
-
-#endif
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-digctl.h b/arch/arm/mach-stmp37xx/include/mach/regs-digctl.h
deleted file mode 100644
index ba1bbe2..0000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-digctl.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * stmp37xx: DIGCTL register definitions
- *
- * Copyright (c) 2008 Freescale Semiconductor
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#define REGS_DIGCTL_BASE (STMP3XXX_REGS_BASE + 0x1C000)
-
-#define HW_DIGCTL_CTRL 0x0
-#define BM_DIGCTL_CTRL_USB_CLKGATE 0x00000004
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-ecc8.h b/arch/arm/mach-stmp37xx/include/mach/regs-ecc8.h
deleted file mode 100644
index 3b6d990..0000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-ecc8.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * stmp37xx: ECC8 register definitions
- *
- * Copyright (c) 2008 Freescale Semiconductor
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#define REGS_ECC8_BASE (STMP3XXX_REGS_BASE + 0x8000)
-
-#define HW_ECC8_CTRL 0x0
-#define BM_ECC8_CTRL_COMPLETE_IRQ 0x00000001
-#define BP_ECC8_CTRL_COMPLETE_IRQ 0
-#define BM_ECC8_CTRL_COMPLETE_IRQ_EN 0x00000100
-#define BM_ECC8_CTRL_AHBM_SFTRST 0x20000000
-
-#define HW_ECC8_STATUS0 0x10
-#define BM_ECC8_STATUS0_UNCORRECTABLE 0x00000004
-#define BM_ECC8_STATUS0_CORRECTED 0x00000008
-#define BM_ECC8_STATUS0_STATUS_AUX 0x00000F00
-#define BP_ECC8_STATUS0_STATUS_AUX 8
-#define BM_ECC8_STATUS0_COMPLETED_CE 0x000F0000
-#define BP_ECC8_STATUS0_COMPLETED_CE 16
-
-#define HW_ECC8_STATUS1 0x20
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-gpmi.h b/arch/arm/mach-stmp37xx/include/mach/regs-gpmi.h
deleted file mode 100644
index f2b304f..0000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-gpmi.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * stmp37xx: GPMI register definitions
- *
- * Copyright (c) 2008 Freescale Semiconductor
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#define REGS_GPMI_BASE (STMP3XXX_REGS_BASE + 0xC000)
-#define REGS_GPMI_PHYS 0x8000C000
-#define REGS_GPMI_SIZE 0x2000
-
-#define HW_GPMI_CTRL0 0x0
-#define BM_GPMI_CTRL0_XFER_COUNT 0x0000FFFF
-#define BP_GPMI_CTRL0_XFER_COUNT 0
-#define BM_GPMI_CTRL0_CS 0x00300000
-#define BP_GPMI_CTRL0_CS 20
-#define BM_GPMI_CTRL0_LOCK_CS 0x00400000
-#define BM_GPMI_CTRL0_WORD_LENGTH 0x00800000
-#define BM_GPMI_CTRL0_COMMAND_MODE 0x03000000
-#define BP_GPMI_CTRL0_COMMAND_MODE 24
-#define BV_GPMI_CTRL0_COMMAND_MODE__WRITE 0x0
-#define BV_GPMI_CTRL0_COMMAND_MODE__READ 0x1
-#define BV_GPMI_CTRL0_COMMAND_MODE__READ_AND_COMPARE 0x2
-#define BV_GPMI_CTRL0_COMMAND_MODE__WAIT_FOR_READY 0x3
-#define BM_GPMI_CTRL0_RUN 0x20000000
-#define BM_GPMI_CTRL0_CLKGATE 0x40000000
-#define BM_GPMI_CTRL0_SFTRST 0x80000000
-#define BM_GPMI_ECCCTRL_ENABLE_ECC 0x00001000
-#define BM_GPMI_ECCCTRL_ECC_CMD 0x00006000
-#define BP_GPMI_ECCCTRL_ECC_CMD 13
-
-#define HW_GPMI_CTRL1 0x60
-#define BM_GPMI_CTRL1_GPMI_MODE 0x00000003
-#define BP_GPMI_CTRL1_GPMI_MODE 0
-#define BM_GPMI_CTRL1_ATA_IRQRDY_POLARITY 0x00000004
-#define BM_GPMI_CTRL1_DEV_RESET 0x00000008
-#define BM_GPMI_CTRL1_TIMEOUT_IRQ 0x00000200
-#define BM_GPMI_CTRL1_DEV_IRQ 0x00000400
-#define BM_GPMI_CTRL1_DSAMPLE_TIME 0x00007000
-#define BP_GPMI_CTRL1_DSAMPLE_TIME 12
-
-#define HW_GPMI_TIMING0 0x70
-#define BM_GPMI_TIMING0_DATA_SETUP 0x000000FF
-#define BP_GPMI_TIMING0_DATA_SETUP 0
-#define BM_GPMI_TIMING0_DATA_HOLD 0x0000FF00
-#define BP_GPMI_TIMING0_DATA_HOLD 8
-
-#define HW_GPMI_TIMING1 0x80
-#define BM_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 0xFFFF0000
-#define BP_GPMI_TIMING1_DEVICE_BUSY_TIMEOUT 16
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-i2c.h b/arch/arm/mach-stmp37xx/include/mach/regs-i2c.h
deleted file mode 100644
index 35882a9..0000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-i2c.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * stmp37xx: I2C register definitions
- *
- * Copyright (c) 2008 Freescale Semiconductor
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#define REGS_I2C_BASE (STMP3XXX_REGS_BASE + 0x58000)
-#define REGS_I2C_PHYS 0x80058000
-#define REGS_I2C_SIZE 0x2000
-
-#define HW_I2C_CTRL0 0x0
-#define BM_I2C_CTRL0_XFER_COUNT 0x0000FFFF
-#define BP_I2C_CTRL0_XFER_COUNT 0
-#define BM_I2C_CTRL0_DIRECTION 0x00010000
-#define BM_I2C_CTRL0_MASTER_MODE 0x00020000
-#define BM_I2C_CTRL0_PRE_SEND_START 0x00080000
-#define BM_I2C_CTRL0_POST_SEND_STOP 0x00100000
-#define BM_I2C_CTRL0_RETAIN_CLOCK 0x00200000
-#define BM_I2C_CTRL0_SEND_NAK_ON_LAST 0x02000000
-#define BM_I2C_CTRL0_CLKGATE 0x40000000
-#define BM_I2C_CTRL0_SFTRST 0x80000000
-
-#define HW_I2C_TIMING0 0x10
-
-#define HW_I2C_TIMING1 0x20
-
-#define HW_I2C_TIMING2 0x30
-
-#define HW_I2C_CTRL1 0x40
-#define BM_I2C_CTRL1_SLAVE_IRQ 0x00000001
-#define BP_I2C_CTRL1_SLAVE_IRQ 0
-#define BM_I2C_CTRL1_SLAVE_STOP_IRQ 0x00000002
-#define BM_I2C_CTRL1_MASTER_LOSS_IRQ 0x00000004
-#define BM_I2C_CTRL1_EARLY_TERM_IRQ 0x00000008
-#define BM_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 0x00000010
-#define BM_I2C_CTRL1_NO_SLAVE_ACK_IRQ 0x00000020
-#define BM_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 0x00000040
-#define BM_I2C_CTRL1_BUS_FREE_IRQ 0x00000080
-#define BM_I2C_CTRL1_CLR_GOT_A_NAK 0x10000000
-
-#define HW_I2C_VERSION 0x90
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-icoll.h b/arch/arm/mach-stmp37xx/include/mach/regs-icoll.h
deleted file mode 100644
index 3b7c922..0000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-icoll.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * stmp37xx: ICOLL register definitions
- *
- * Copyright (c) 2008 Freescale Semiconductor
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#ifndef _MACH_REGS_ICOLL
-#define _MACH_REGS_ICOLL
-
-#define REGS_ICOLL_BASE (STMP3XXX_REGS_BASE + 0x0)
-
-#define HW_ICOLL_VECTOR 0x0
-
-#define HW_ICOLL_LEVELACK 0x10
-
-#define HW_ICOLL_CTRL 0x20
-#define BM_ICOLL_CTRL_CLKGATE 0x40000000
-#define BM_ICOLL_CTRL_SFTRST 0x80000000
-
-#define HW_ICOLL_STAT 0x30
-
-#define HW_ICOLL_PRIORITY0 (0x60 + 0 * 0x10)
-#define HW_ICOLL_PRIORITY1 (0x60 + 1 * 0x10)
-#define HW_ICOLL_PRIORITY2 (0x60 + 2 * 0x10)
-#define HW_ICOLL_PRIORITY3 (0x60 + 3 * 0x10)
-
-#define HW_ICOLL_PRIORITYn 0x60
-
-#endif
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-lcdif.h b/arch/arm/mach-stmp37xx/include/mach/regs-lcdif.h
deleted file mode 100644
index 72514e8..0000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-lcdif.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * stmp37xx: LCDIF register definitions
- *
- * Copyright (c) 2008 Freescale Semiconductor
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#define REGS_LCDIF_BASE (STMP3XXX_REGS_BASE + 0x30000)
-#define REGS_LCDIF_PHYS 0x80030000
-#define REGS_LCDIF_SIZE 0x2000
-
-#define HW_LCDIF_CTRL 0x0
-#define BM_LCDIF_CTRL_COUNT 0x0000FFFF
-#define BP_LCDIF_CTRL_COUNT 0
-#define BM_LCDIF_CTRL_RUN 0x00010000
-#define BM_LCDIF_CTRL_WORD_LENGTH 0x00020000
-#define BM_LCDIF_CTRL_DATA_SELECT 0x00040000
-#define BM_LCDIF_CTRL_DOTCLK_MODE 0x00080000
-#define BM_LCDIF_CTRL_VSYNC_MODE 0x00100000
-#define BM_LCDIF_CTRL_DATA_SWIZZLE 0x00600000
-#define BP_LCDIF_CTRL_DATA_SWIZZLE 21
-#define BM_LCDIF_CTRL_BYPASS_COUNT 0x00800000
-#define BM_LCDIF_CTRL_SHIFT_NUM_BITS 0x06000000
-#define BP_LCDIF_CTRL_SHIFT_NUM_BITS 25
-#define BM_LCDIF_CTRL_DATA_SHIFT_DIR 0x08000000
-#define BM_LCDIF_CTRL_WAIT_FOR_VSYNC_EDGE 0x10000000
-#define BM_LCDIF_CTRL_CLKGATE 0x40000000
-#define BM_LCDIF_CTRL_SFTRST 0x80000000
-
-#define HW_LCDIF_CTRL1 0x10
-#define BM_LCDIF_CTRL1_RESET 0x00000001
-#define BP_LCDIF_CTRL1_RESET 0
-#define BM_LCDIF_CTRL1_MODE86 0x00000002
-#define BM_LCDIF_CTRL1_BUSY_ENABLE 0x00000004
-#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ 0x00000100
-#define BM_LCDIF_CTRL1_CUR_FRAME_DONE_IRQ 0x00000200
-#define BM_LCDIF_CTRL1_UNDERFLOW_IRQ 0x00000400
-#define BM_LCDIF_CTRL1_OVERFLOW_IRQ 0x00000800
-#define BM_LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN 0x00001000
-#define BM_LCDIF_CTRL1_BYTE_PACKING_FORMAT 0x000F0000
-#define BP_LCDIF_CTRL1_BYTE_PACKING_FORMAT 16
-
-#define HW_LCDIF_TIMING 0x20
-
-#define HW_LCDIF_VDCTRL0 0x30
-#define BM_LCDIF_VDCTRL0_VALID_DATA_CNT 0x000003FF
-#define BP_LCDIF_VDCTRL0_VALID_DATA_CNT 0
-#define BM_LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT 0x00100000
-#define BM_LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT 0x00200000
-#define BM_LCDIF_VDCTRL0_ENABLE_POL 0x01000000
-#define BM_LCDIF_VDCTRL0_DOTCLK_POL 0x02000000
-#define BM_LCDIF_VDCTRL0_HSYNC_POL 0x04000000
-#define BM_LCDIF_VDCTRL0_VSYNC_POL 0x08000000
-#define BM_LCDIF_VDCTRL0_ENABLE_PRESENT 0x10000000
-#define BM_LCDIF_VDCTRL0_VSYNC_OEB 0x20000000
-
-#define HW_LCDIF_VDCTRL1 0x40
-#define BM_LCDIF_VDCTRL1_VSYNC_PERIOD 0x000FFFFF
-#define BP_LCDIF_VDCTRL1_VSYNC_PERIOD 0
-#define BM_LCDIF_VDCTRL1_VSYNC_PULSE_WIDTH 0xFFF00000
-#define BP_LCDIF_VDCTRL1_VSYNC_PULSE_WIDTH 20
-
-#define HW_LCDIF_VDCTRL2 0x50
-#define BM_LCDIF_VDCTRL2_VALID_DATA_CNT 0x000007FF
-#define BP_LCDIF_VDCTRL2_VALID_DATA_CNT 0
-#define BM_LCDIF_VDCTRL2_HSYNC_PERIOD 0x007FF800
-#define BP_LCDIF_VDCTRL2_HSYNC_PERIOD 11
-#define BM_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 0xFF800000
-#define BP_LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH 23
-
-#define HW_LCDIF_VDCTRL3 0x60
-#define BM_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0x000001FF
-#define BP_LCDIF_VDCTRL3_VERTICAL_WAIT_CNT 0
-#define BM_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 0x00FFF000
-#define BP_LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT 12
-#define BM_LCDIF_VDCTRL3_SYNC_SIGNALS_ON 0x01000000
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-lradc.h b/arch/arm/mach-stmp37xx/include/mach/regs-lradc.h
deleted file mode 100644
index cc7b470..0000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-lradc.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * stmp37xx: LRADC register definitions
- *
- * Copyright (c) 2008 Freescale Semiconductor
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#define REGS_LRADC_BASE (STMP3XXX_REGS_BASE + 0x50000)
-
-#define HW_LRADC_CTRL0 0x0
-#define BM_LRADC_CTRL0_SCHEDULE 0x000000FF
-#define BP_LRADC_CTRL0_SCHEDULE 0
-#define BM_LRADC_CTRL0_XPLUS_ENABLE 0x00010000
-#define BM_LRADC_CTRL0_YPLUS_ENABLE 0x00020000
-#define BM_LRADC_CTRL0_XMINUS_ENABLE 0x00040000
-#define BM_LRADC_CTRL0_YMINUS_ENABLE 0x00080000
-#define BM_LRADC_CTRL0_TOUCH_DETECT_ENABLE 0x00100000
-#define BM_LRADC_CTRL0_ONCHIP_GROUNDREF 0x00200000
-#define BM_LRADC_CTRL0_CLKGATE 0x40000000
-#define BM_LRADC_CTRL0_SFTRST 0x80000000
-
-#define HW_LRADC_CTRL1 0x10
-#define BM_LRADC_CTRL1_LRADC0_IRQ 0x00000001
-#define BP_LRADC_CTRL1_LRADC0_IRQ 0
-#define BM_LRADC_CTRL1_LRADC5_IRQ 0x00000020
-#define BM_LRADC_CTRL1_LRADC6_IRQ 0x00000040
-#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ 0x00000100
-#define BM_LRADC_CTRL1_LRADC0_IRQ_EN 0x00010000
-#define BM_LRADC_CTRL1_LRADC5_IRQ_EN 0x00200000
-#define BM_LRADC_CTRL1_TOUCH_DETECT_IRQ_EN 0x01000000
-
-#define HW_LRADC_CTRL2 0x20
-#define BM_LRADC_CTRL2_BL_BRIGHTNESS 0x001F0000
-#define BP_LRADC_CTRL2_BL_BRIGHTNESS 16
-#define BM_LRADC_CTRL2_BL_MUX_SELECT 0x00200000
-#define BM_LRADC_CTRL2_BL_ENABLE 0x00400000
-#define BM_LRADC_CTRL2_DIVIDE_BY_TWO 0xFF000000
-#define BP_LRADC_CTRL2_DIVIDE_BY_TWO 24
-
-#define HW_LRADC_CTRL3 0x30
-#define BM_LRADC_CTRL3_CYCLE_TIME 0x00000300
-#define BP_LRADC_CTRL3_CYCLE_TIME 8
-
-#define HW_LRADC_STATUS 0x40
-#define BM_LRADC_STATUS_TOUCH_DETECT_RAW 0x00000001
-#define BP_LRADC_STATUS_TOUCH_DETECT_RAW 0
-
-#define HW_LRADC_CH0 (0x50 + 0 * 0x10)
-#define HW_LRADC_CH1 (0x50 + 1 * 0x10)
-#define HW_LRADC_CH2 (0x50 + 2 * 0x10)
-#define HW_LRADC_CH3 (0x50 + 3 * 0x10)
-#define HW_LRADC_CH4 (0x50 + 4 * 0x10)
-#define HW_LRADC_CH5 (0x50 + 5 * 0x10)
-#define HW_LRADC_CH6 (0x50 + 6 * 0x10)
-#define HW_LRADC_CH7 (0x50 + 7 * 0x10)
-
-#define HW_LRADC_CHn 0x50
-#define BM_LRADC_CHn_VALUE 0x0003FFFF
-#define BP_LRADC_CHn_VALUE 0
-#define BM_LRADC_CHn_NUM_SAMPLES 0x1F000000
-#define BP_LRADC_CHn_NUM_SAMPLES 24
-#define BM_LRADC_CHn_ACCUMULATE 0x20000000
-
-#define HW_LRADC_DELAY0 (0xD0 + 0 * 0x10)
-#define HW_LRADC_DELAY1 (0xD0 + 1 * 0x10)
-#define HW_LRADC_DELAY2 (0xD0 + 2 * 0x10)
-#define HW_LRADC_DELAY3 (0xD0 + 3 * 0x10)
-
-#define HW_LRADC_DELAYn 0xD0
-#define BM_LRADC_DELAYn_DELAY 0x000007FF
-#define BP_LRADC_DELAYn_DELAY 0
-#define BM_LRADC_DELAYn_LOOP_COUNT 0x0000F800
-#define BP_LRADC_DELAYn_LOOP_COUNT 11
-#define BM_LRADC_DELAYn_TRIGGER_DELAYS 0x000F0000
-#define BP_LRADC_DELAYn_TRIGGER_DELAYS 16
-#define BM_LRADC_DELAYn_KICK 0x00100000
-#define BM_LRADC_DELAYn_TRIGGER_LRADCS 0xFF000000
-#define BP_LRADC_DELAYn_TRIGGER_LRADCS 24
-
-#define HW_LRADC_CTRL4 0x140
-#define BM_LRADC_CTRL4_LRADC6SELECT 0x0F000000
-#define BP_LRADC_CTRL4_LRADC6SELECT 24
-#define BM_LRADC_CTRL4_LRADC7SELECT 0xF0000000
-#define BP_LRADC_CTRL4_LRADC7SELECT 28
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-pinctrl.h b/arch/arm/mach-stmp37xx/include/mach/regs-pinctrl.h
deleted file mode 100644
index d5efce2..0000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-pinctrl.h
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * stmp37xx: PINCTRL register definitions
- *
- * Copyright (c) 2008 Freescale Semiconductor
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#ifndef _MACH_REGS_PINCTRL
-#define _MACH_REGS_PINCTRL
-
-#define REGS_PINCTRL_BASE (STMP3XXX_REGS_BASE + 0x18000)
-
-#define HW_PINCTRL_MUXSEL0 0x100
-#define HW_PINCTRL_MUXSEL1 0x110
-#define HW_PINCTRL_MUXSEL2 0x120
-#define HW_PINCTRL_MUXSEL3 0x130
-#define HW_PINCTRL_MUXSEL4 0x140
-#define HW_PINCTRL_MUXSEL5 0x150
-#define HW_PINCTRL_MUXSEL6 0x160
-#define HW_PINCTRL_MUXSEL7 0x170
-
-#define HW_PINCTRL_DRIVE0 0x200
-#define HW_PINCTRL_DRIVE1 0x210
-#define HW_PINCTRL_DRIVE2 0x220
-#define HW_PINCTRL_DRIVE3 0x230
-#define HW_PINCTRL_DRIVE4 0x240
-#define HW_PINCTRL_DRIVE5 0x250
-#define HW_PINCTRL_DRIVE6 0x260
-#define HW_PINCTRL_DRIVE7 0x270
-#define HW_PINCTRL_DRIVE8 0x280
-#define HW_PINCTRL_DRIVE9 0x290
-#define HW_PINCTRL_DRIVE10 0x2A0
-#define HW_PINCTRL_DRIVE11 0x2B0
-#define HW_PINCTRL_DRIVE12 0x2C0
-#define HW_PINCTRL_DRIVE13 0x2D0
-#define HW_PINCTRL_DRIVE14 0x2E0
-
-#define HW_PINCTRL_PULL0 0x300
-#define HW_PINCTRL_PULL1 0x310
-#define HW_PINCTRL_PULL2 0x320
-#define HW_PINCTRL_PULL3 0x330
-
-#define HW_PINCTRL_DOUT0 0x400
-#define HW_PINCTRL_DOUT1 0x410
-#define HW_PINCTRL_DOUT2 0x420
-
-#define HW_PINCTRL_DIN0 0x500
-#define HW_PINCTRL_DIN1 0x510
-#define HW_PINCTRL_DIN2 0x520
-
-#define HW_PINCTRL_DOE0 0x600
-#define HW_PINCTRL_DOE1 0x610
-#define HW_PINCTRL_DOE2 0x620
-
-#define HW_PINCTRL_PIN2IRQ0 0x700
-#define HW_PINCTRL_PIN2IRQ1 0x710
-#define HW_PINCTRL_PIN2IRQ2 0x720
-
-#define HW_PINCTRL_IRQEN0 0x800
-#define HW_PINCTRL_IRQEN1 0x810
-#define HW_PINCTRL_IRQEN2 0x820
-
-#define HW_PINCTRL_IRQLEVEL0 0x900
-#define HW_PINCTRL_IRQLEVEL1 0x910
-#define HW_PINCTRL_IRQLEVEL2 0x920
-
-#define HW_PINCTRL_IRQPOL0 0xA00
-#define HW_PINCTRL_IRQPOL1 0xA10
-#define HW_PINCTRL_IRQPOL2 0xA20
-
-#define HW_PINCTRL_IRQSTAT0 0xB00
-#define HW_PINCTRL_IRQSTAT1 0xB10
-#define HW_PINCTRL_IRQSTAT2 0xB20
-
-#endif
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-power.h b/arch/arm/mach-stmp37xx/include/mach/regs-power.h
deleted file mode 100644
index 0e733d7..0000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-power.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * stmp37xx: POWER register definitions
- *
- * Copyright (c) 2008 Freescale Semiconductor
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#ifndef _MACH_REGS_POWER
-#define _MACH_REGS_POWER
-
-#define REGS_POWER_BASE (STMP3XXX_REGS_BASE + 0x44000)
-
-#define HW_POWER_CTRL 0x0
-#define BM_POWER_CTRL_CLKGATE 0x40000000
-
-#define HW_POWER_5VCTRL 0x10
-
-#define HW_POWER_MINPWR 0x20
-
-#define HW_POWER_CHARGE 0x30
-
-#define HW_POWER_VDDDCTRL 0x40
-
-#define HW_POWER_VDDACTRL 0x50
-
-#define HW_POWER_VDDIOCTRL 0x60
-#define BM_POWER_VDDIOCTRL_TRG 0x0000001F
-#define BP_POWER_VDDIOCTRL_TRG 0
-
-#define HW_POWER_STS 0xB0
-#define BM_POWER_STS_VBUSVALID 0x00000002
-#define BM_POWER_STS_BVALID 0x00000004
-#define BM_POWER_STS_AVALID 0x00000008
-#define BM_POWER_STS_DC_OK 0x00000100
-
-#define HW_POWER_RESET 0xE0
-
-#define HW_POWER_DEBUG 0xF0
-#define BM_POWER_DEBUG_BVALIDPIOLOCK 0x00000002
-#define BM_POWER_DEBUG_AVALIDPIOLOCK 0x00000004
-#define BM_POWER_DEBUG_VBUSVALIDPIOLOCK 0x00000008
-
-#endif
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-pwm.h b/arch/arm/mach-stmp37xx/include/mach/regs-pwm.h
deleted file mode 100644
index 15966a1..0000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-pwm.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * stmp37xx: PWM register definitions
- *
- * Copyright (c) 2008 Freescale Semiconductor
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#define REGS_PWM_BASE (STMP3XXX_REGS_BASE + 0x64000)
-
-#define HW_PWM_CTRL 0x0
-#define BM_PWM_CTRL_PWM2_ENABLE 0x00000004
-#define BM_PWM_CTRL_PWM2_ANA_CTRL_ENABLE 0x00000020
-
-#define HW_PWM_ACTIVE0 (0x10 + 0 * 0x20)
-#define HW_PWM_ACTIVE1 (0x10 + 1 * 0x20)
-#define HW_PWM_ACTIVE2 (0x10 + 2 * 0x20)
-#define HW_PWM_ACTIVE3 (0x10 + 3 * 0x20)
-
-#define HW_PWM_ACTIVEn 0x10
-#define BM_PWM_ACTIVEn_ACTIVE 0x0000FFFF
-#define BP_PWM_ACTIVEn_ACTIVE 0
-#define BM_PWM_ACTIVEn_INACTIVE 0xFFFF0000
-#define BP_PWM_ACTIVEn_INACTIVE 16
-
-#define HW_PWM_PERIOD0 (0x20 + 0 * 0x20)
-#define HW_PWM_PERIOD1 (0x20 + 1 * 0x20)
-#define HW_PWM_PERIOD2 (0x20 + 2 * 0x20)
-#define HW_PWM_PERIOD3 (0x20 + 3 * 0x20)
-
-#define HW_PWM_PERIODn 0x20
-#define BM_PWM_PERIODn_PERIOD 0x0000FFFF
-#define BP_PWM_PERIODn_PERIOD 0
-#define BM_PWM_PERIODn_ACTIVE_STATE 0x00030000
-#define BP_PWM_PERIODn_ACTIVE_STATE 16
-#define BM_PWM_PERIODn_INACTIVE_STATE 0x000C0000
-#define BP_PWM_PERIODn_INACTIVE_STATE 18
-#define BM_PWM_PERIODn_CDIV 0x00700000
-#define BP_PWM_PERIODn_CDIV 20
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-rtc.h b/arch/arm/mach-stmp37xx/include/mach/regs-rtc.h
deleted file mode 100644
index fac40ed..0000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-rtc.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * stmp37xx: RTC register definitions
- *
- * Copyright (c) 2008 Freescale Semiconductor
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#define REGS_RTC_BASE (STMP3XXX_REGS_BASE + 0x5C000)
-#define REGS_RTC_PHYS 0x8005C000
-#define REGS_RTC_SIZE 0x2000
-
-#define HW_RTC_CTRL 0x0
-#define BM_RTC_CTRL_ALARM_IRQ_EN 0x00000001
-#define BP_RTC_CTRL_ALARM_IRQ_EN 0
-#define BM_RTC_CTRL_ONEMSEC_IRQ_EN 0x00000002
-#define BM_RTC_CTRL_ALARM_IRQ 0x00000004
-#define BM_RTC_CTRL_ONEMSEC_IRQ 0x00000008
-#define BM_RTC_CTRL_WATCHDOGEN 0x00000010
-
-#define HW_RTC_STAT 0x10
-#define BM_RTC_STAT_NEW_REGS 0x0000FF00
-#define BP_RTC_STAT_NEW_REGS 8
-#define BM_RTC_STAT_STALE_REGS 0x00FF0000
-#define BP_RTC_STAT_STALE_REGS 16
-#define BM_RTC_STAT_RTC_PRESENT 0x80000000
-
-#define HW_RTC_SECONDS 0x30
-
-#define HW_RTC_ALARM 0x40
-
-#define HW_RTC_WATCHDOG 0x50
-
-#define HW_RTC_PERSISTENT0 0x60
-#define BM_RTC_PERSISTENT0_ALARM_WAKE_EN 0x00000002
-#define BM_RTC_PERSISTENT0_ALARM_EN 0x00000004
-#define BM_RTC_PERSISTENT0_XTAL24MHZ_PWRUP 0x00000010
-#define BM_RTC_PERSISTENT0_XTAL32KHZ_PWRUP 0x00000020
-#define BM_RTC_PERSISTENT0_ALARM_WAKE 0x00000080
-#define BM_RTC_PERSISTENT0_SPARE_ANALOG 0xFFFC0000
-#define BP_RTC_PERSISTENT0_SPARE_ANALOG 18
-
-#define HW_RTC_PERSISTENT1 0x70
-
-#define HW_RTC_VERSION 0xD0
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-ssp.h b/arch/arm/mach-stmp37xx/include/mach/regs-ssp.h
deleted file mode 100644
index cbde891..0000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-ssp.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * stmp37xx: SSP register definitions
- *
- * Copyright (c) 2008 Freescale Semiconductor
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#define REGS_SSP_BASE (STMP3XXX_REGS_BASE + 0x10000)
-#define REGS_SSP1_PHYS 0x80010000
-#define REGS_SSP2_PHYS 0x80034000
-#define REGS_SSP_SIZE 0x2000
-
-#define HW_SSP_CTRL0 0x0
-#define BM_SSP_CTRL0_XFER_COUNT 0x0000FFFF
-#define BP_SSP_CTRL0_XFER_COUNT 0
-#define BM_SSP_CTRL0_ENABLE 0x00010000
-#define BM_SSP_CTRL0_GET_RESP 0x00020000
-#define BM_SSP_CTRL0_LONG_RESP 0x00080000
-#define BM_SSP_CTRL0_WAIT_FOR_CMD 0x00100000
-#define BM_SSP_CTRL0_WAIT_FOR_IRQ 0x00200000
-#define BM_SSP_CTRL0_BUS_WIDTH 0x00C00000
-#define BP_SSP_CTRL0_BUS_WIDTH 22
-#define BM_SSP_CTRL0_DATA_XFER 0x01000000
-#define BM_SSP_CTRL0_READ 0x02000000
-#define BM_SSP_CTRL0_IGNORE_CRC 0x04000000
-#define BM_SSP_CTRL0_LOCK_CS 0x08000000
-#define BM_SSP_CTRL0_RUN 0x20000000
-#define BM_SSP_CTRL0_CLKGATE 0x40000000
-#define BM_SSP_CTRL0_SFTRST 0x80000000
-
-#define HW_SSP_CMD0 0x10
-#define BM_SSP_CMD0_CMD 0x000000FF
-#define BP_SSP_CMD0_CMD 0
-#define BM_SSP_CMD0_BLOCK_COUNT 0x0000FF00
-#define BP_SSP_CMD0_BLOCK_COUNT 8
-#define BM_SSP_CMD0_BLOCK_SIZE 0x000F0000
-#define BP_SSP_CMD0_BLOCK_SIZE 16
-#define BM_SSP_CMD0_APPEND_8CYC 0x00100000
-#define BM_SSP_CMD1_CMD_ARG 0xFFFFFFFF
-#define BP_SSP_CMD1_CMD_ARG 0
-
-#define HW_SSP_TIMING 0x50
-#define BM_SSP_TIMING_CLOCK_RATE 0x000000FF
-#define BP_SSP_TIMING_CLOCK_RATE 0
-#define BM_SSP_TIMING_CLOCK_DIVIDE 0x0000FF00
-#define BP_SSP_TIMING_CLOCK_DIVIDE 8
-#define BM_SSP_TIMING_TIMEOUT 0xFFFF0000
-#define BP_SSP_TIMING_TIMEOUT 16
-
-#define HW_SSP_CTRL1 0x60
-#define BM_SSP_CTRL1_SSP_MODE 0x0000000F
-#define BP_SSP_CTRL1_SSP_MODE 0
-#define BM_SSP_CTRL1_WORD_LENGTH 0x000000F0
-#define BP_SSP_CTRL1_WORD_LENGTH 4
-#define BM_SSP_CTRL1_POLARITY 0x00000200
-#define BM_SSP_CTRL1_PHASE 0x00000400
-#define BM_SSP_CTRL1_DMA_ENABLE 0x00002000
-#define BM_SSP_CTRL1_FIFO_OVERRUN_IRQ 0x00008000
-#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ_EN 0x00010000
-#define BM_SSP_CTRL1_RECV_TIMEOUT_IRQ 0x00020000
-#define BM_SSP_CTRL1_FIFO_UNDERRUN_IRQ 0x00200000
-#define BM_SSP_CTRL1_DATA_CRC_IRQ_EN 0x00400000
-#define BM_SSP_CTRL1_DATA_CRC_IRQ 0x00800000
-#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ_EN 0x01000000
-#define BM_SSP_CTRL1_DATA_TIMEOUT_IRQ 0x02000000
-#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ_EN 0x04000000
-#define BM_SSP_CTRL1_RESP_TIMEOUT_IRQ 0x08000000
-#define BM_SSP_CTRL1_RESP_ERR_IRQ_EN 0x10000000
-#define BM_SSP_CTRL1_RESP_ERR_IRQ 0x20000000
-#define BM_SSP_CTRL1_SDIO_IRQ 0x80000000
-
-#define HW_SSP_DATA 0x70
-
-#define HW_SSP_SDRESP0 0x80
-
-#define HW_SSP_SDRESP1 0x90
-
-#define HW_SSP_SDRESP2 0xA0
-
-#define HW_SSP_SDRESP3 0xB0
-
-#define HW_SSP_STATUS 0xC0
-#define BM_SSP_STATUS_FIFO_EMPTY 0x00000020
-#define BM_SSP_STATUS_TIMEOUT 0x00001000
-#define BM_SSP_STATUS_RESP_TIMEOUT 0x00004000
-#define BM_SSP_STATUS_RESP_ERR 0x00008000
-#define BM_SSP_STATUS_RESP_CRC_ERR 0x00010000
-#define BM_SSP_STATUS_CARD_DETECT 0x10000000
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-timrot.h b/arch/arm/mach-stmp37xx/include/mach/regs-timrot.h
deleted file mode 100644
index 4af0f6e..0000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-timrot.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * stmp37xx: TIMROT register definitions
- *
- * Copyright (c) 2008 Freescale Semiconductor
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#ifndef _MACH_REGS_TIMROT
-#define _MACH_REGS_TIMROT
-
-#define REGS_TIMROT_BASE (STMP3XXX_REGS_BASE + 0x68000)
-
-#define HW_TIMROT_ROTCTRL 0x0
-#define BM_TIMROT_ROTCTRL_CLKGATE 0x40000000
-#define BM_TIMROT_ROTCTRL_SFTRST 0x80000000
-
-#define HW_TIMROT_TIMCTRL0 (0x20 + 0 * 0x20)
-#define HW_TIMROT_TIMCTRL1 (0x20 + 1 * 0x20)
-#define HW_TIMROT_TIMCTRL2 (0x20 + 2 * 0x20)
-
-#define HW_TIMROT_TIMCTRLn 0x20
-#define BM_TIMROT_TIMCTRLn_SELECT 0x0000000F
-#define BP_TIMROT_TIMCTRLn_SELECT 0
-#define BM_TIMROT_TIMCTRLn_PRESCALE 0x00000030
-#define BP_TIMROT_TIMCTRLn_PRESCALE 4
-#define BM_TIMROT_TIMCTRLn_RELOAD 0x00000040
-#define BM_TIMROT_TIMCTRLn_UPDATE 0x00000080
-#define BM_TIMROT_TIMCTRLn_IRQ_EN 0x00004000
-#define BM_TIMROT_TIMCTRLn_IRQ 0x00008000
-
-#define HW_TIMROT_TIMCOUNT0 (0x30 + 0 * 0x20)
-#define HW_TIMROT_TIMCOUNT1 (0x30 + 1 * 0x20)
-#define HW_TIMROT_TIMCOUNT2 (0x30 + 2 * 0x20)
-
-#define HW_TIMROT_TIMCOUNTn 0x30
-#endif
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-uartapp.h b/arch/arm/mach-stmp37xx/include/mach/regs-uartapp.h
deleted file mode 100644
index 0594275..0000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-uartapp.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * stmp37xx: UARTAPP register definitions
- *
- * Copyright (c) 2008 Freescale Semiconductor
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#define REGS_UARTAPP_BASE (STMP3XXX_REGS_BASE + 0x6C000)
-#define REGS_UARTAPP1_PHYS 0x8006C000
-#define REGS_UARTAPP_SIZE 0x2000
-
-#define HW_UARTAPP_CTRL0 0x0
-#define BM_UARTAPP_CTRL0_XFER_COUNT 0x0000FFFF
-#define BP_UARTAPP_CTRL0_XFER_COUNT 0
-#define BM_UARTAPP_CTRL0_RXTIMEOUT 0x07FF0000
-#define BP_UARTAPP_CTRL0_RXTIMEOUT 16
-#define BM_UARTAPP_CTRL0_RXTO_ENABLE 0x08000000
-#define BM_UARTAPP_CTRL0_RUN 0x20000000
-#define BM_UARTAPP_CTRL0_SFTRST 0x80000000
-#define BM_UARTAPP_CTRL1_XFER_COUNT 0x0000FFFF
-#define BP_UARTAPP_CTRL1_XFER_COUNT 0
-#define BM_UARTAPP_CTRL1_RUN 0x10000000
-
-#define HW_UARTAPP_CTRL2 0x20
-#define BM_UARTAPP_CTRL2_UARTEN 0x00000001
-#define BP_UARTAPP_CTRL2_UARTEN 0
-#define BM_UARTAPP_CTRL2_TXE 0x00000100
-#define BM_UARTAPP_CTRL2_RXE 0x00000200
-#define BM_UARTAPP_CTRL2_RTS 0x00000800
-#define BM_UARTAPP_CTRL2_RTSEN 0x00004000
-#define BM_UARTAPP_CTRL2_CTSEN 0x00008000
-#define BM_UARTAPP_CTRL2_RXDMAE 0x01000000
-#define BM_UARTAPP_CTRL2_TXDMAE 0x02000000
-#define BM_UARTAPP_CTRL2_DMAONERR 0x04000000
-
-#define HW_UARTAPP_LINECTRL 0x30
-#define BM_UARTAPP_LINECTRL_BRK 0x00000001
-#define BP_UARTAPP_LINECTRL_BRK 0
-#define BM_UARTAPP_LINECTRL_PEN 0x00000002
-#define BM_UARTAPP_LINECTRL_EPS 0x00000004
-#define BM_UARTAPP_LINECTRL_STP2 0x00000008
-#define BM_UARTAPP_LINECTRL_FEN 0x00000010
-#define BM_UARTAPP_LINECTRL_WLEN 0x00000060
-#define BP_UARTAPP_LINECTRL_WLEN 5
-#define BM_UARTAPP_LINECTRL_SPS 0x00000080
-#define BM_UARTAPP_LINECTRL_BAUD_DIVFRAC 0x00003F00
-#define BP_UARTAPP_LINECTRL_BAUD_DIVFRAC 8
-#define BM_UARTAPP_LINECTRL_BAUD_DIVINT 0xFFFF0000
-#define BP_UARTAPP_LINECTRL_BAUD_DIVINT 16
-
-#define HW_UARTAPP_INTR 0x50
-#define BM_UARTAPP_INTR_CTSMIS 0x00000002
-#define BM_UARTAPP_INTR_RTIS 0x00000040
-#define BM_UARTAPP_INTR_CTSMIEN 0x00020000
-#define BM_UARTAPP_INTR_RXIEN 0x00100000
-#define BM_UARTAPP_INTR_RTIEN 0x00400000
-
-#define HW_UARTAPP_DATA 0x60
-
-#define HW_UARTAPP_STAT 0x70
-#define BM_UARTAPP_STAT_RXCOUNT 0x0000FFFF
-#define BP_UARTAPP_STAT_RXCOUNT 0
-#define BM_UARTAPP_STAT_FERR 0x00010000
-#define BM_UARTAPP_STAT_PERR 0x00020000
-#define BM_UARTAPP_STAT_BERR 0x00040000
-#define BM_UARTAPP_STAT_OERR 0x00080000
-#define BM_UARTAPP_STAT_RXFE 0x01000000
-#define BM_UARTAPP_STAT_TXFF 0x02000000
-#define BM_UARTAPP_STAT_TXFE 0x08000000
-#define BM_UARTAPP_STAT_CTS 0x10000000
-
-#define HW_UARTAPP_VERSION 0x90
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-uartdbg.h b/arch/arm/mach-stmp37xx/include/mach/regs-uartdbg.h
deleted file mode 100644
index b810deb..0000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-uartdbg.h
+++ /dev/null
@@ -1,268 +0,0 @@
-/*
- * stmp378x: UARTDBG register definitions
- *
- * Copyright (c) 2008 Freescale Semiconductor
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#define REGS_UARTDBG_BASE (STMP3XXX_REGS_BASE + 0x70000)
-#define REGS_UARTDBG_PHYS 0x80070000
-#define REGS_UARTDBG_SIZE 0x2000
-
-#define HW_UARTDBGDR 0x00000000
-#define BP_UARTDBGDR_UNAVAILABLE 16
-#define BM_UARTDBGDR_UNAVAILABLE 0xFFFF0000
-#define BF_UARTDBGDR_UNAVAILABLE(v) \
- (((v) << 16) & BM_UARTDBGDR_UNAVAILABLE)
-#define BP_UARTDBGDR_RESERVED 12
-#define BM_UARTDBGDR_RESERVED 0x0000F000
-#define BF_UARTDBGDR_RESERVED(v) \
- (((v) << 12) & BM_UARTDBGDR_RESERVED)
-#define BM_UARTDBGDR_OE 0x00000800
-#define BM_UARTDBGDR_BE 0x00000400
-#define BM_UARTDBGDR_PE 0x00000200
-#define BM_UARTDBGDR_FE 0x00000100
-#define BP_UARTDBGDR_DATA 0
-#define BM_UARTDBGDR_DATA 0x000000FF
-#define BF_UARTDBGDR_DATA(v) \
- (((v) << 0) & BM_UARTDBGDR_DATA)
-#define HW_UARTDBGRSR_ECR 0x00000004
-#define BP_UARTDBGRSR_ECR_UNAVAILABLE 8
-#define BM_UARTDBGRSR_ECR_UNAVAILABLE 0xFFFFFF00
-#define BF_UARTDBGRSR_ECR_UNAVAILABLE(v) \
- (((v) << 8) & BM_UARTDBGRSR_ECR_UNAVAILABLE)
-#define BP_UARTDBGRSR_ECR_EC 4
-#define BM_UARTDBGRSR_ECR_EC 0x000000F0
-#define BF_UARTDBGRSR_ECR_EC(v) \
- (((v) << 4) & BM_UARTDBGRSR_ECR_EC)
-#define BM_UARTDBGRSR_ECR_OE 0x00000008
-#define BM_UARTDBGRSR_ECR_BE 0x00000004
-#define BM_UARTDBGRSR_ECR_PE 0x00000002
-#define BM_UARTDBGRSR_ECR_FE 0x00000001
-#define HW_UARTDBGFR 0x00000018
-#define BP_UARTDBGFR_UNAVAILABLE 16
-#define BM_UARTDBGFR_UNAVAILABLE 0xFFFF0000
-#define BF_UARTDBGFR_UNAVAILABLE(v) \
- (((v) << 16) & BM_UARTDBGFR_UNAVAILABLE)
-#define BP_UARTDBGFR_RESERVED 9
-#define BM_UARTDBGFR_RESERVED 0x0000FE00
-#define BF_UARTDBGFR_RESERVED(v) \
- (((v) << 9) & BM_UARTDBGFR_RESERVED)
-#define BM_UARTDBGFR_RI 0x00000100
-#define BM_UARTDBGFR_TXFE 0x00000080
-#define BM_UARTDBGFR_RXFF 0x00000040
-#define BM_UARTDBGFR_TXFF 0x00000020
-#define BM_UARTDBGFR_RXFE 0x00000010
-#define BM_UARTDBGFR_BUSY 0x00000008
-#define BM_UARTDBGFR_DCD 0x00000004
-#define BM_UARTDBGFR_DSR 0x00000002
-#define BM_UARTDBGFR_CTS 0x00000001
-#define HW_UARTDBGILPR 0x00000020
-#define BP_UARTDBGILPR_UNAVAILABLE 8
-#define BM_UARTDBGILPR_UNAVAILABLE 0xFFFFFF00
-#define BF_UARTDBGILPR_UNAVAILABLE(v) \
- (((v) << 8) & BM_UARTDBGILPR_UNAVAILABLE)
-#define BP_UARTDBGILPR_ILPDVSR 0
-#define BM_UARTDBGILPR_ILPDVSR 0x000000FF
-#define BF_UARTDBGILPR_ILPDVSR(v) \
- (((v) << 0) & BM_UARTDBGILPR_ILPDVSR)
-#define HW_UARTDBGIBRD 0x00000024
-#define BP_UARTDBGIBRD_UNAVAILABLE 16
-#define BM_UARTDBGIBRD_UNAVAILABLE 0xFFFF0000
-#define BF_UARTDBGIBRD_UNAVAILABLE(v) \
- (((v) << 16) & BM_UARTDBGIBRD_UNAVAILABLE)
-#define BP_UARTDBGIBRD_BAUD_DIVINT 0
-#define BM_UARTDBGIBRD_BAUD_DIVINT 0x0000FFFF
-#define BF_UARTDBGIBRD_BAUD_DIVINT(v) \
- (((v) << 0) & BM_UARTDBGIBRD_BAUD_DIVINT)
-#define HW_UARTDBGFBRD 0x00000028
-#define BP_UARTDBGFBRD_UNAVAILABLE 8
-#define BM_UARTDBGFBRD_UNAVAILABLE 0xFFFFFF00
-#define BF_UARTDBGFBRD_UNAVAILABLE(v) \
- (((v) << 8) & BM_UARTDBGFBRD_UNAVAILABLE)
-#define BP_UARTDBGFBRD_RESERVED 6
-#define BM_UARTDBGFBRD_RESERVED 0x000000C0
-#define BF_UARTDBGFBRD_RESERVED(v) \
- (((v) << 6) & BM_UARTDBGFBRD_RESERVED)
-#define BP_UARTDBGFBRD_BAUD_DIVFRAC 0
-#define BM_UARTDBGFBRD_BAUD_DIVFRAC 0x0000003F
-#define BF_UARTDBGFBRD_BAUD_DIVFRAC(v) \
- (((v) << 0) & BM_UARTDBGFBRD_BAUD_DIVFRAC)
-#define HW_UARTDBGLCR_H 0x0000002c
-#define BP_UARTDBGLCR_H_UNAVAILABLE 16
-#define BM_UARTDBGLCR_H_UNAVAILABLE 0xFFFF0000
-#define BF_UARTDBGLCR_H_UNAVAILABLE(v) \
- (((v) << 16) & BM_UARTDBGLCR_H_UNAVAILABLE)
-#define BP_UARTDBGLCR_H_RESERVED 8
-#define BM_UARTDBGLCR_H_RESERVED 0x0000FF00
-#define BF_UARTDBGLCR_H_RESERVED(v) \
- (((v) << 8) & BM_UARTDBGLCR_H_RESERVED)
-#define BM_UARTDBGLCR_H_SPS 0x00000080
-#define BP_UARTDBGLCR_H_WLEN 5
-#define BM_UARTDBGLCR_H_WLEN 0x00000060
-#define BF_UARTDBGLCR_H_WLEN(v) \
- (((v) << 5) & BM_UARTDBGLCR_H_WLEN)
-#define BM_UARTDBGLCR_H_FEN 0x00000010
-#define BM_UARTDBGLCR_H_STP2 0x00000008
-#define BM_UARTDBGLCR_H_EPS 0x00000004
-#define BM_UARTDBGLCR_H_PEN 0x00000002
-#define BM_UARTDBGLCR_H_BRK 0x00000001
-#define HW_UARTDBGCR 0x00000030
-#define BP_UARTDBGCR_UNAVAILABLE 16
-#define BM_UARTDBGCR_UNAVAILABLE 0xFFFF0000
-#define BF_UARTDBGCR_UNAVAILABLE(v) \
- (((v) << 16) & BM_UARTDBGCR_UNAVAILABLE)
-#define BM_UARTDBGCR_CTSEN 0x00008000
-#define BM_UARTDBGCR_RTSEN 0x00004000
-#define BM_UARTDBGCR_OUT2 0x00002000
-#define BM_UARTDBGCR_OUT1 0x00001000
-#define BM_UARTDBGCR_RTS 0x00000800
-#define BM_UARTDBGCR_DTR 0x00000400
-#define BM_UARTDBGCR_RXE 0x00000200
-#define BM_UARTDBGCR_TXE 0x00000100
-#define BM_UARTDBGCR_LBE 0x00000080
-#define BP_UARTDBGCR_RESERVED 3
-#define BM_UARTDBGCR_RESERVED 0x00000078
-#define BF_UARTDBGCR_RESERVED(v) \
- (((v) << 3) & BM_UARTDBGCR_RESERVED)
-#define BM_UARTDBGCR_SIRLP 0x00000004
-#define BM_UARTDBGCR_SIREN 0x00000002
-#define BM_UARTDBGCR_UARTEN 0x00000001
-#define HW_UARTDBGIFLS 0x00000034
-#define BP_UARTDBGIFLS_UNAVAILABLE 16
-#define BM_UARTDBGIFLS_UNAVAILABLE 0xFFFF0000
-#define BF_UARTDBGIFLS_UNAVAILABLE(v) \
- (((v) << 16) & BM_UARTDBGIFLS_UNAVAILABLE)
-#define BP_UARTDBGIFLS_RESERVED 6
-#define BM_UARTDBGIFLS_RESERVED 0x0000FFC0
-#define BF_UARTDBGIFLS_RESERVED(v) \
- (((v) << 6) & BM_UARTDBGIFLS_RESERVED)
-#define BP_UARTDBGIFLS_RXIFLSEL 3
-#define BM_UARTDBGIFLS_RXIFLSEL 0x00000038
-#define BF_UARTDBGIFLS_RXIFLSEL(v) \
- (((v) << 3) & BM_UARTDBGIFLS_RXIFLSEL)
-#define BV_UARTDBGIFLS_RXIFLSEL__NOT_EMPTY 0x0
-#define BV_UARTDBGIFLS_RXIFLSEL__ONE_QUARTER 0x1
-#define BV_UARTDBGIFLS_RXIFLSEL__ONE_HALF 0x2
-#define BV_UARTDBGIFLS_RXIFLSEL__THREE_QUARTERS 0x3
-#define BV_UARTDBGIFLS_RXIFLSEL__SEVEN_EIGHTHS 0x4
-#define BV_UARTDBGIFLS_RXIFLSEL__INVALID5 0x5
-#define BV_UARTDBGIFLS_RXIFLSEL__INVALID6 0x6
-#define BV_UARTDBGIFLS_RXIFLSEL__INVALID7 0x7
-#define BP_UARTDBGIFLS_TXIFLSEL 0
-#define BM_UARTDBGIFLS_TXIFLSEL 0x00000007
-#define BF_UARTDBGIFLS_TXIFLSEL(v) \
- (((v) << 0) & BM_UARTDBGIFLS_TXIFLSEL)
-#define BV_UARTDBGIFLS_TXIFLSEL__EMPTY 0x0
-#define BV_UARTDBGIFLS_TXIFLSEL__ONE_QUARTER 0x1
-#define BV_UARTDBGIFLS_TXIFLSEL__ONE_HALF 0x2
-#define BV_UARTDBGIFLS_TXIFLSEL__THREE_QUARTERS 0x3
-#define BV_UARTDBGIFLS_TXIFLSEL__SEVEN_EIGHTHS 0x4
-#define BV_UARTDBGIFLS_TXIFLSEL__INVALID5 0x5
-#define BV_UARTDBGIFLS_TXIFLSEL__INVALID6 0x6
-#define BV_UARTDBGIFLS_TXIFLSEL__INVALID7 0x7
-#define HW_UARTDBGIMSC 0x00000038
-#define BP_UARTDBGIMSC_UNAVAILABLE 16
-#define BM_UARTDBGIMSC_UNAVAILABLE 0xFFFF0000
-#define BF_UARTDBGIMSC_UNAVAILABLE(v) \
- (((v) << 16) & BM_UARTDBGIMSC_UNAVAILABLE)
-#define BP_UARTDBGIMSC_RESERVED 11
-#define BM_UARTDBGIMSC_RESERVED 0x0000F800
-#define BF_UARTDBGIMSC_RESERVED(v) \
- (((v) << 11) & BM_UARTDBGIMSC_RESERVED)
-#define BM_UARTDBGIMSC_OEIM 0x00000400
-#define BM_UARTDBGIMSC_BEIM 0x00000200
-#define BM_UARTDBGIMSC_PEIM 0x00000100
-#define BM_UARTDBGIMSC_FEIM 0x00000080
-#define BM_UARTDBGIMSC_RTIM 0x00000040
-#define BM_UARTDBGIMSC_TXIM 0x00000020
-#define BM_UARTDBGIMSC_RXIM 0x00000010
-#define BM_UARTDBGIMSC_DSRMIM 0x00000008
-#define BM_UARTDBGIMSC_DCDMIM 0x00000004
-#define BM_UARTDBGIMSC_CTSMIM 0x00000002
-#define BM_UARTDBGIMSC_RIMIM 0x00000001
-#define HW_UARTDBGRIS 0x0000003c
-#define BP_UARTDBGRIS_UNAVAILABLE 16
-#define BM_UARTDBGRIS_UNAVAILABLE 0xFFFF0000
-#define BF_UARTDBGRIS_UNAVAILABLE(v) \
- (((v) << 16) & BM_UARTDBGRIS_UNAVAILABLE)
-#define BP_UARTDBGRIS_RESERVED 11
-#define BM_UARTDBGRIS_RESERVED 0x0000F800
-#define BF_UARTDBGRIS_RESERVED(v) \
- (((v) << 11) & BM_UARTDBGRIS_RESERVED)
-#define BM_UARTDBGRIS_OERIS 0x00000400
-#define BM_UARTDBGRIS_BERIS 0x00000200
-#define BM_UARTDBGRIS_PERIS 0x00000100
-#define BM_UARTDBGRIS_FERIS 0x00000080
-#define BM_UARTDBGRIS_RTRIS 0x00000040
-#define BM_UARTDBGRIS_TXRIS 0x00000020
-#define BM_UARTDBGRIS_RXRIS 0x00000010
-#define BM_UARTDBGRIS_DSRRMIS 0x00000008
-#define BM_UARTDBGRIS_DCDRMIS 0x00000004
-#define BM_UARTDBGRIS_CTSRMIS 0x00000002
-#define BM_UARTDBGRIS_RIRMIS 0x00000001
-#define HW_UARTDBGMIS 0x00000040
-#define BP_UARTDBGMIS_UNAVAILABLE 16
-#define BM_UARTDBGMIS_UNAVAILABLE 0xFFFF0000
-#define BF_UARTDBGMIS_UNAVAILABLE(v) \
- (((v) << 16) & BM_UARTDBGMIS_UNAVAILABLE)
-#define BP_UARTDBGMIS_RESERVED 11
-#define BM_UARTDBGMIS_RESERVED 0x0000F800
-#define BF_UARTDBGMIS_RESERVED(v) \
- (((v) << 11) & BM_UARTDBGMIS_RESERVED)
-#define BM_UARTDBGMIS_OEMIS 0x00000400
-#define BM_UARTDBGMIS_BEMIS 0x00000200
-#define BM_UARTDBGMIS_PEMIS 0x00000100
-#define BM_UARTDBGMIS_FEMIS 0x00000080
-#define BM_UARTDBGMIS_RTMIS 0x00000040
-#define BM_UARTDBGMIS_TXMIS 0x00000020
-#define BM_UARTDBGMIS_RXMIS 0x00000010
-#define BM_UARTDBGMIS_DSRMMIS 0x00000008
-#define BM_UARTDBGMIS_DCDMMIS 0x00000004
-#define BM_UARTDBGMIS_CTSMMIS 0x00000002
-#define BM_UARTDBGMIS_RIMMIS 0x00000001
-#define HW_UARTDBGICR 0x00000044
-#define BP_UARTDBGICR_UNAVAILABLE 16
-#define BM_UARTDBGICR_UNAVAILABLE 0xFFFF0000
-#define BF_UARTDBGICR_UNAVAILABLE(v) \
- (((v) << 16) & BM_UARTDBGICR_UNAVAILABLE)
-#define BP_UARTDBGICR_RESERVED 11
-#define BM_UARTDBGICR_RESERVED 0x0000F800
-#define BF_UARTDBGICR_RESERVED(v) \
- (((v) << 11) & BM_UARTDBGICR_RESERVED)
-#define BM_UARTDBGICR_OEIC 0x00000400
-#define BM_UARTDBGICR_BEIC 0x00000200
-#define BM_UARTDBGICR_PEIC 0x00000100
-#define BM_UARTDBGICR_FEIC 0x00000080
-#define BM_UARTDBGICR_RTIC 0x00000040
-#define BM_UARTDBGICR_TXIC 0x00000020
-#define BM_UARTDBGICR_RXIC 0x00000010
-#define BM_UARTDBGICR_DSRMIC 0x00000008
-#define BM_UARTDBGICR_DCDMIC 0x00000004
-#define BM_UARTDBGICR_CTSMIC 0x00000002
-#define BM_UARTDBGICR_RIMIC 0x00000001
-#define HW_UARTDBGDMACR 0x00000048
-#define BP_UARTDBGDMACR_UNAVAILABLE 16
-#define BM_UARTDBGDMACR_UNAVAILABLE 0xFFFF0000
-#define BF_UARTDBGDMACR_UNAVAILABLE(v) \
- (((v) << 16) & BM_UARTDBGDMACR_UNAVAILABLE)
-#define BP_UARTDBGDMACR_RESERVED 3
-#define BM_UARTDBGDMACR_RESERVED 0x0000FFF8
-#define BF_UARTDBGDMACR_RESERVED(v) \
- (((v) << 3) & BM_UARTDBGDMACR_RESERVED)
-#define BM_UARTDBGDMACR_DMAONERR 0x00000004
-#define BM_UARTDBGDMACR_TXDMAE 0x00000002
-#define BM_UARTDBGDMACR_RXDMAE 0x00000001
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-usbctl.h b/arch/arm/mach-stmp37xx/include/mach/regs-usbctl.h
deleted file mode 100644
index 9145e22..0000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-usbctl.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * stmp37xx: USBCTL register definitions
- *
- * Copyright (c) 2008 Freescale Semiconductor
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#define REGS_USBCTL_BASE (STMP3XXX_REGS_BASE + 0x80000)
-#define REGS_USBCTL_PHYS 0x80000
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-usbctrl.h b/arch/arm/mach-stmp37xx/include/mach/regs-usbctrl.h
deleted file mode 100644
index 1a2ae9c..0000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-usbctrl.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * stmp37xx: USBCTRL register definitions
- *
- * Copyright (c) 2008 Freescale Semiconductor
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#define REGS_USBCTRL_BASE (STMP3XXX_REGS_BASE + 0x80000)
-#define REGS_USBCTRL_PHYS 0x80080000
diff --git a/arch/arm/mach-stmp37xx/include/mach/regs-usbphy.h b/arch/arm/mach-stmp37xx/include/mach/regs-usbphy.h
deleted file mode 100644
index b7fce0f..0000000
--- a/arch/arm/mach-stmp37xx/include/mach/regs-usbphy.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * stmp37xx: USBPHY register definitions
- *
- * Copyright (c) 2008 Freescale Semiconductor
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
- */
-#define REGS_USBPHY_BASE (STMP3XXX_REGS_BASE + 0x7C000)
-
-#define HW_USBPHY_PWD 0x0
-
-#define HW_USBPHY_CTRL 0x30
-#define BM_USBPHY_CTRL_ENHSPRECHARGEXMIT 0x00000001
-#define BP_USBPHY_CTRL_ENHSPRECHARGEXMIT 0
-#define BM_USBPHY_CTRL_ENHOSTDISCONDETECT 0x00000002
-#define BM_USBPHY_CTRL_ENDEVPLUGINDETECT 0x00000010
-#define BM_USBPHY_CTRL_ENOTGIDDETECT 0x00000080
-#define BM_USBPHY_CTRL_ENIRQDEVPLUGIN 0x00000800
-#define BM_USBPHY_CTRL_CLKGATE 0x40000000
-#define BM_USBPHY_CTRL_SFTRST 0x80000000
-
-#define HW_USBPHY_STATUS 0x40
-#define BM_USBPHY_STATUS_DEVPLUGIN_STATUS 0x00000040
-#define BM_USBPHY_STATUS_OTGID_STATUS 0x00000100
diff --git a/arch/arm/mach-stmp37xx/stmp37xx.c b/arch/arm/mach-stmp37xx/stmp37xx.c
deleted file mode 100644
index a9aed06..0000000
--- a/arch/arm/mach-stmp37xx/stmp37xx.c
+++ /dev/null
@@ -1,219 +0,0 @@
-/*
- * Freescale STMP37XX platform support
- *
- * Embedded Alley Solutions, Inc <source@embeddedalley.com>
- *
- * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/irq.h>
-#include <linux/io.h>
-
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-
-#include <asm/mach/arch.h>
-#include <asm/mach/irq.h>
-#include <asm/mach/map.h>
-#include <asm/mach/time.h>
-
-#include <mach/stmp3xxx.h>
-#include <mach/dma.h>
-
-#include <mach/platform.h>
-#include <mach/regs-icoll.h>
-#include <mach/regs-apbh.h>
-#include <mach/regs-apbx.h>
-#include "stmp37xx.h"
-
-/*
- * IRQ handling
- */
-static void stmp37xx_ack_irq(struct irq_data *d)
-{
- /* Disable IRQ */
- stmp3xxx_clearl(0x04 << ((d->irq % 4) * 8),
- REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn + d->irq / 4 * 0x10);
-
- /* ACK current interrupt */
- __raw_writel(1, REGS_ICOLL_BASE + HW_ICOLL_LEVELACK);
-
- /* Barrier */
- (void)__raw_readl(REGS_ICOLL_BASE + HW_ICOLL_STAT);
-}
-
-static void stmp37xx_mask_irq(struct irq_data *d)
-{
- /* IRQ disable */
- stmp3xxx_clearl(0x04 << ((d->irq % 4) * 8),
- REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn + d->irq / 4 * 0x10);
-}
-
-static void stmp37xx_unmask_irq(struct irq_data *d)
-{
- /* IRQ enable */
- stmp3xxx_setl(0x04 << ((d->irq % 4) * 8),
- REGS_ICOLL_BASE + HW_ICOLL_PRIORITYn + d->irq / 4 * 0x10);
-}
-
-static struct irq_chip stmp37xx_chip = {
- .irq_ack = stmp37xx_ack_irq,
- .irq_mask = stmp37xx_mask_irq,
- .irq_unmask = stmp37xx_unmask_irq,
-};
-
-void __init stmp37xx_init_irq(void)
-{
- stmp3xxx_init_irq(&stmp37xx_chip);
-}
-
-/*
- * DMA interrupt handling
- */
-void stmp3xxx_arch_dma_enable_interrupt(int channel)
-{
- switch (STMP3XXX_DMA_BUS(channel)) {
- case STMP3XXX_BUS_APBH:
- stmp3xxx_setl(1 << (8 + STMP3XXX_DMA_CHANNEL(channel)),
- REGS_APBH_BASE + HW_APBH_CTRL1);
- break;
-
- case STMP3XXX_BUS_APBX:
- stmp3xxx_setl(1 << (8 + STMP3XXX_DMA_CHANNEL(channel)),
- REGS_APBX_BASE + HW_APBX_CTRL1);
- break;
- }
-}
-EXPORT_SYMBOL(stmp3xxx_arch_dma_enable_interrupt);
-
-void stmp3xxx_arch_dma_clear_interrupt(int channel)
-{
- switch (STMP3XXX_DMA_BUS(channel)) {
- case STMP3XXX_BUS_APBH:
- stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel),
- REGS_APBH_BASE + HW_APBH_CTRL1);
- break;
-
- case STMP3XXX_BUS_APBX:
- stmp3xxx_clearl(1 << STMP3XXX_DMA_CHANNEL(channel),
- REGS_APBX_BASE + HW_APBX_CTRL1);
- break;
- }
-}
-EXPORT_SYMBOL(stmp3xxx_arch_dma_clear_interrupt);
-
-int stmp3xxx_arch_dma_is_interrupt(int channel)
-{
- int r = 0;
-
- switch (STMP3XXX_DMA_BUS(channel)) {
- case STMP3XXX_BUS_APBH:
- r = __raw_readl(REGS_APBH_BASE + HW_APBH_CTRL1) &
- (1 << STMP3XXX_DMA_CHANNEL(channel));
- break;
-
- case STMP3XXX_BUS_APBX:
- r = __raw_readl(REGS_APBH_BASE + HW_APBH_CTRL1) &
- (1 << STMP3XXX_DMA_CHANNEL(channel));
- break;
- }
- return r;
-}
-EXPORT_SYMBOL(stmp3xxx_arch_dma_is_interrupt);
-
-void stmp3xxx_arch_dma_reset_channel(int channel)
-{
- unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
-
- switch (STMP3XXX_DMA_BUS(channel)) {
- case STMP3XXX_BUS_APBH:
- /* Reset channel and wait for it to complete */
- stmp3xxx_setl(chbit << BP_APBH_CTRL0_RESET_CHANNEL,
- REGS_APBH_BASE + HW_APBH_CTRL0);
- while (__raw_readl(REGS_APBH_BASE + HW_APBH_CTRL0) &
- (chbit << BP_APBH_CTRL0_RESET_CHANNEL))
- cpu_relax();
- break;
-
- case STMP3XXX_BUS_APBX:
- stmp3xxx_setl(chbit << BP_APBX_CTRL0_RESET_CHANNEL,
- REGS_APBX_BASE + HW_APBX_CTRL0);
- while (__raw_readl(REGS_APBX_BASE + HW_APBX_CTRL0) &
- (chbit << BP_APBX_CTRL0_RESET_CHANNEL))
- cpu_relax();
- break;
- }
-}
-EXPORT_SYMBOL(stmp3xxx_arch_dma_reset_channel);
-
-void stmp3xxx_arch_dma_freeze(int channel)
-{
- unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
-
- switch (STMP3XXX_DMA_BUS(channel)) {
- case STMP3XXX_BUS_APBH:
- stmp3xxx_setl(1 << chbit, REGS_APBH_BASE + HW_APBH_CTRL0);
- break;
- case STMP3XXX_BUS_APBX:
- stmp3xxx_setl(1 << chbit, REGS_APBH_BASE + HW_APBH_CTRL0);
- break;
- }
-}
-EXPORT_SYMBOL(stmp3xxx_arch_dma_freeze);
-
-void stmp3xxx_arch_dma_unfreeze(int channel)
-{
- unsigned chbit = 1 << STMP3XXX_DMA_CHANNEL(channel);
-
- switch (STMP3XXX_DMA_BUS(channel)) {
- case STMP3XXX_BUS_APBH:
- stmp3xxx_clearl(1 << chbit, REGS_APBH_BASE + HW_APBH_CTRL0);
- break;
- case STMP3XXX_BUS_APBX:
- stmp3xxx_clearl(1 << chbit, REGS_APBH_BASE + HW_APBH_CTRL0);
- break;
- }
-}
-EXPORT_SYMBOL(stmp3xxx_arch_dma_unfreeze);
-
-/*
- * The registers are all very closely mapped, so we might as well map them all
- * with a single mapping
- *
- * Logical Physical
- * f0000000 80000000 On-chip registers
- * f1000000 00000000 32k on-chip SRAM
- */
-static struct map_desc stmp37xx_io_desc[] __initdata = {
- {
- .virtual = (u32)STMP3XXX_REGS_BASE,
- .pfn = __phys_to_pfn(STMP3XXX_REGS_PHBASE),
- .length = SZ_1M,
- .type = MT_DEVICE
- },
- {
- .virtual = (u32)STMP3XXX_OCRAM_BASE,
- .pfn = __phys_to_pfn(STMP3XXX_OCRAM_PHBASE),
- .length = STMP3XXX_OCRAM_SIZE,
- .type = MT_DEVICE,
- },
-};
-
-void __init stmp37xx_map_io(void)
-{
- iotable_init(stmp37xx_io_desc, ARRAY_SIZE(stmp37xx_io_desc));
-}
diff --git a/arch/arm/mach-stmp37xx/stmp37xx.h b/arch/arm/mach-stmp37xx/stmp37xx.h
deleted file mode 100644
index 0b75fb7..0000000
--- a/arch/arm/mach-stmp37xx/stmp37xx.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Freescale STMP37XX/STMP378X internal functions and data declarations
- *
- * Embedded Alley Solutions, Inc <source@embeddedalley.com>
- *
- * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#ifndef __MACH_STMP37XX_H
-#define __MACH_STMP37XX_H
-
-void stmp37xx_map_io(void);
-void stmp37xx_init_irq(void);
-
-#endif /* __MACH_STMP37XX_H */
diff --git a/arch/arm/mach-stmp37xx/stmp37xx_devb.c b/arch/arm/mach-stmp37xx/stmp37xx_devb.c
deleted file mode 100644
index 311d855..0000000
--- a/arch/arm/mach-stmp37xx/stmp37xx_devb.c
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * Freescale STMP37XX development board support
- *
- * Embedded Alley Solutions, Inc <source@embeddedalley.com>
- *
- * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <asm/setup.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-
-#include <mach/stmp3xxx.h>
-#include <mach/pins.h>
-#include <mach/pinmux.h>
-#include "stmp37xx.h"
-
-/*
- * List of STMP37xx development board specific devices
- */
-static struct platform_device *stmp37xx_devb_devices[] = {
- &stmp3xxx_dbguart,
- &stmp3xxx_appuart,
-};
-
-static struct pin_desc dbguart_pins_0[] = {
- { PINID_PWM0, PIN_FUN3, },
- { PINID_PWM1, PIN_FUN3, },
-};
-
-struct pin_desc appuart_pins_0[] = {
- { PINID_UART2_CTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
- { PINID_UART2_RTS, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
- { PINID_UART2_RX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
- { PINID_UART2_TX, PIN_FUN1, PIN_4MA, PIN_1_8V, 0, },
-};
-
-static struct pin_group appuart_pins[] = {
- [0] = {
- .pins = appuart_pins_0,
- .nr_pins = ARRAY_SIZE(appuart_pins_0),
- },
- /* 37xx has the only app uart */
-};
-
-static struct pin_group dbguart_pins[] = {
- [0] = {
- .pins = dbguart_pins_0,
- .nr_pins = ARRAY_SIZE(dbguart_pins_0),
- },
-};
-
-static int dbguart_pins_control(int id, int request)
-{
- int r = 0;
-
- if (request)
- r = stmp3xxx_request_pin_group(&dbguart_pins[id], "debug uart");
- else
- stmp3xxx_release_pin_group(&dbguart_pins[id], "debug uart");
- return r;
-}
-
-
-static void __init stmp37xx_devb_init(void)
-{
- stmp3xxx_pinmux_init(NR_REAL_IRQS);
-
- /* Init STMP3xxx platform */
- stmp3xxx_init();
-
- stmp3xxx_dbguart.dev.platform_data = dbguart_pins_control;
- stmp3xxx_appuart.dev.platform_data = appuart_pins;
-
- /* Add STMP37xx development board devices */
- platform_add_devices(stmp37xx_devb_devices,
- ARRAY_SIZE(stmp37xx_devb_devices));
-}
-
-MACHINE_START(STMP37XX, "STMP37XX")
- .boot_params = 0x40000100,
- .map_io = stmp37xx_map_io,
- .init_irq = stmp37xx_init_irq,
- .timer = &stmp3xxx_timer,
- .init_machine = stmp37xx_devb_init,
-MACHINE_END
diff --git a/arch/arm/mach-tcc8k/time.c b/arch/arm/mach-tcc8k/time.c
index e0a8d60..a96babe 100644
--- a/arch/arm/mach-tcc8k/time.c
+++ b/arch/arm/mach-tcc8k/time.c
@@ -25,19 +25,6 @@
static void __iomem *timer_base;
-static cycle_t tcc_get_cycles(struct clocksource *cs)
-{
- return __raw_readl(timer_base + TC32MCNT_OFFS);
-}
-
-static struct clocksource clocksource_tcc = {
- .name = "tcc_tc32",
- .rating = 200,
- .read = tcc_get_cycles,
- .mask = CLOCKSOURCE_MASK(32),
- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
static int tcc_set_next_event(unsigned long evt,
struct clock_event_device *unused)
{
@@ -102,7 +89,8 @@
{
unsigned int c = clk_get_rate(clock);
- clocksource_register_hz(&clocksource_tcc, c);
+ clocksource_mmio_init(timer_base + TC32MCNT_OFFS, "tcc_tc32", c,
+ 200, 32, clocksource_mmio_readl_up);
clockevent_tcc.mult = div_sc(c, NSEC_PER_SEC,
clockevent_tcc.shift);
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 1afe050..823c703 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -1,7 +1,7 @@
obj-y += common.o
obj-y += devices.o
obj-y += io.o
-obj-y += irq.o legacy_irq.o
+obj-y += irq.o
obj-y += clock.o
obj-y += timer.o
obj-y += gpio.o
diff --git a/arch/arm/mach-tegra/gpio.c b/arch/arm/mach-tegra/gpio.c
index 65a1aba..919d638 100644
--- a/arch/arm/mach-tegra/gpio.c
+++ b/arch/arm/mach-tegra/gpio.c
@@ -24,6 +24,8 @@
#include <linux/io.h>
#include <linux/gpio.h>
+#include <asm/mach/irq.h>
+
#include <mach/iomap.h>
#include <mach/suspend.h>
@@ -221,8 +223,9 @@
int port;
int pin;
int unmasked = 0;
+ struct irq_chip *chip = irq_desc_get_chip(desc);
- desc->irq_data.chip->irq_ack(&desc->irq_data);
+ chained_irq_enter(chip, desc);
bank = irq_get_handler_data(irq);
@@ -241,7 +244,7 @@
*/
if (lvl & (0x100 << pin)) {
unmasked = 1;
- desc->irq_data.chip->irq_unmask(&desc->irq_data);
+ chained_irq_exit(chip, desc);
}
generic_handle_irq(gpio_to_irq(gpio + pin));
@@ -249,7 +252,7 @@
}
if (!unmasked)
- desc->irq_data.chip->irq_unmask(&desc->irq_data);
+ chained_irq_exit(chip, desc);
}
diff --git a/arch/arm/mach-tegra/include/mach/kbc.h b/arch/arm/mach-tegra/include/mach/kbc.h
index 04c7798..4f3572a 100644
--- a/arch/arm/mach-tegra/include/mach/kbc.h
+++ b/arch/arm/mach-tegra/include/mach/kbc.h
@@ -50,13 +50,11 @@
unsigned int debounce_cnt;
unsigned int repeat_cnt;
- unsigned int wake_cnt; /* 0:wake on any key >1:wake on wake_cfg */
- const struct tegra_kbc_wake_key *wake_cfg;
-
struct tegra_kbc_pin_cfg pin_cfg[KBC_MAX_GPIO];
const struct matrix_keymap_data *keymap_data;
bool wakeup;
bool use_fn_map;
+ bool use_ghost_filter;
};
#endif
diff --git a/arch/arm/mach-tegra/include/mach/legacy_irq.h b/arch/arm/mach-tegra/include/mach/legacy_irq.h
deleted file mode 100644
index d898c0e..0000000
--- a/arch/arm/mach-tegra/include/mach/legacy_irq.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * arch/arm/mach-tegra/include/mach/legacy_irq.h
- *
- * Copyright (C) 2010 Google, Inc.
- * Author: Colin Cross <ccross@android.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef _ARCH_ARM_MACH_TEGRA_LEGARY_IRQ_H
-#define _ARCH_ARM_MACH_TEGRA_LEGARY_IRQ_H
-
-void tegra_legacy_mask_irq(unsigned int irq);
-void tegra_legacy_unmask_irq(unsigned int irq);
-void tegra_legacy_select_fiq(unsigned int irq, bool fiq);
-void tegra_legacy_force_irq_set(unsigned int irq);
-void tegra_legacy_force_irq_clr(unsigned int irq);
-int tegra_legacy_force_irq_status(unsigned int irq);
-void tegra_legacy_select_fiq(unsigned int irq, bool fiq);
-unsigned long tegra_legacy_vfiq(int nr);
-unsigned long tegra_legacy_class(int nr);
-int tegra_legacy_irq_set_wake(int irq, int enable);
-void tegra_legacy_irq_set_lp1_wake_mask(void);
-void tegra_legacy_irq_restore_mask(void);
-void tegra_init_legacy_irq(void);
-
-#endif
diff --git a/arch/arm/mach-tegra/include/mach/sdhci.h b/arch/arm/mach-tegra/include/mach/sdhci.h
index 3ad086e..4231bc7 100644
--- a/arch/arm/mach-tegra/include/mach/sdhci.h
+++ b/arch/arm/mach-tegra/include/mach/sdhci.h
@@ -24,6 +24,7 @@
int wp_gpio;
int power_gpio;
int is_8bit;
+ int pm_flags;
};
#endif
diff --git a/arch/arm/mach-tegra/include/mach/smp.h b/arch/arm/mach-tegra/include/mach/smp.h
deleted file mode 100644
index c8221b3..0000000
--- a/arch/arm/mach-tegra/include/mach/smp.h
+++ /dev/null
@@ -1,14 +0,0 @@
-#ifndef ASMARM_ARCH_SMP_H
-#define ASMARM_ARCH_SMP_H
-
-#include <asm/hardware/gic.h>
-
-/*
- * We use IRQ1 as the IPI
- */
-static inline void smp_cross_call(const struct cpumask *mask, int ipi)
-{
- gic_raise_softirq(mask, ipi);
-}
-
-#endif
diff --git a/arch/arm/mach-tegra/irq.c b/arch/arm/mach-tegra/irq.c
index 4330d89..4956c3c 100644
--- a/arch/arm/mach-tegra/irq.c
+++ b/arch/arm/mach-tegra/irq.c
@@ -1,8 +1,8 @@
/*
- * Copyright (C) 2010 Google, Inc.
+ * Copyright (C) 2011 Google, Inc.
*
* Author:
- * Colin Cross <ccross@google.com>
+ * Colin Cross <ccross@android.com>
*
* Copyright (C) 2010, NVIDIA Corporation
*
@@ -18,8 +18,6 @@
*/
#include <linux/kernel.h>
-#include <linux/delay.h>
-#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
@@ -27,134 +25,110 @@
#include <asm/hardware/gic.h>
#include <mach/iomap.h>
-#include <mach/legacy_irq.h>
-#include <mach/suspend.h>
#include "board.h"
-#define PMC_CTRL 0x0
-#define PMC_CTRL_LATCH_WAKEUPS (1 << 5)
-#define PMC_WAKE_MASK 0xc
-#define PMC_WAKE_LEVEL 0x10
-#define PMC_WAKE_STATUS 0x14
-#define PMC_SW_WAKE_STATUS 0x18
-#define PMC_DPD_SAMPLE 0x20
+#define INT_SYS_NR (INT_GPIO_BASE - INT_PRI_BASE)
+#define INT_SYS_SZ (INT_SEC_BASE - INT_PRI_BASE)
+#define PPI_NR ((INT_SYS_NR+INT_SYS_SZ-1)/INT_SYS_SZ)
-static void __iomem *pmc = IO_ADDRESS(TEGRA_PMC_BASE);
+#define ICTLR_CPU_IEP_VFIQ 0x08
+#define ICTLR_CPU_IEP_FIR 0x14
+#define ICTLR_CPU_IEP_FIR_SET 0x18
+#define ICTLR_CPU_IEP_FIR_CLR 0x1c
-static u32 tegra_lp0_wake_enb;
-static u32 tegra_lp0_wake_level;
-static u32 tegra_lp0_wake_level_any;
+#define ICTLR_CPU_IER 0x20
+#define ICTLR_CPU_IER_SET 0x24
+#define ICTLR_CPU_IER_CLR 0x28
+#define ICTLR_CPU_IEP_CLASS 0x2C
-static void (*tegra_gic_mask_irq)(struct irq_data *d);
-static void (*tegra_gic_unmask_irq)(struct irq_data *d);
-static void (*tegra_gic_ack_irq)(struct irq_data *d);
+#define ICTLR_COP_IER 0x30
+#define ICTLR_COP_IER_SET 0x34
+#define ICTLR_COP_IER_CLR 0x38
+#define ICTLR_COP_IEP_CLASS 0x3c
-/* ensures that sufficient time is passed for a register write to
- * serialize into the 32KHz domain */
-static void pmc_32kwritel(u32 val, unsigned long offs)
+#define NUM_ICTLRS 4
+#define FIRST_LEGACY_IRQ 32
+
+static void __iomem *ictlr_reg_base[] = {
+ IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE),
+ IO_ADDRESS(TEGRA_SECONDARY_ICTLR_BASE),
+ IO_ADDRESS(TEGRA_TERTIARY_ICTLR_BASE),
+ IO_ADDRESS(TEGRA_QUATERNARY_ICTLR_BASE),
+};
+
+static inline void tegra_irq_write_mask(unsigned int irq, unsigned long reg)
{
- writel(val, pmc + offs);
- udelay(130);
-}
+ void __iomem *base;
+ u32 mask;
-int tegra_set_lp1_wake(int irq, int enable)
-{
- return tegra_legacy_irq_set_wake(irq, enable);
-}
+ BUG_ON(irq < FIRST_LEGACY_IRQ ||
+ irq >= FIRST_LEGACY_IRQ + NUM_ICTLRS * 32);
-void tegra_set_lp0_wake_pads(u32 wake_enb, u32 wake_level, u32 wake_any)
-{
- u32 temp;
- u32 status;
- u32 lvl;
+ base = ictlr_reg_base[(irq - FIRST_LEGACY_IRQ) / 32];
+ mask = BIT((irq - FIRST_LEGACY_IRQ) % 32);
- wake_level &= wake_enb;
- wake_any &= wake_enb;
-
- wake_level |= (tegra_lp0_wake_level & tegra_lp0_wake_enb);
- wake_any |= (tegra_lp0_wake_level_any & tegra_lp0_wake_enb);
-
- wake_enb |= tegra_lp0_wake_enb;
-
- pmc_32kwritel(0, PMC_SW_WAKE_STATUS);
- temp = readl(pmc + PMC_CTRL);
- temp |= PMC_CTRL_LATCH_WAKEUPS;
- pmc_32kwritel(temp, PMC_CTRL);
- temp &= ~PMC_CTRL_LATCH_WAKEUPS;
- pmc_32kwritel(temp, PMC_CTRL);
- status = readl(pmc + PMC_SW_WAKE_STATUS);
- lvl = readl(pmc + PMC_WAKE_LEVEL);
-
- /* flip the wakeup trigger for any-edge triggered pads
- * which are currently asserting as wakeups */
- lvl ^= status;
- lvl &= wake_any;
-
- wake_level |= lvl;
-
- writel(wake_level, pmc + PMC_WAKE_LEVEL);
- /* Enable DPD sample to trigger sampling pads data and direction
- * in which pad will be driven during lp0 mode*/
- writel(0x1, pmc + PMC_DPD_SAMPLE);
-
- writel(wake_enb, pmc + PMC_WAKE_MASK);
+ __raw_writel(mask, base + reg);
}
static void tegra_mask(struct irq_data *d)
{
- tegra_gic_mask_irq(d);
- tegra_legacy_mask_irq(d->irq);
+ if (d->irq < FIRST_LEGACY_IRQ)
+ return;
+
+ tegra_irq_write_mask(d->irq, ICTLR_CPU_IER_CLR);
}
static void tegra_unmask(struct irq_data *d)
{
- tegra_gic_unmask_irq(d);
- tegra_legacy_unmask_irq(d->irq);
+ if (d->irq < FIRST_LEGACY_IRQ)
+ return;
+
+ tegra_irq_write_mask(d->irq, ICTLR_CPU_IER_SET);
}
static void tegra_ack(struct irq_data *d)
{
- tegra_legacy_force_irq_clr(d->irq);
- tegra_gic_ack_irq(d);
+ if (d->irq < FIRST_LEGACY_IRQ)
+ return;
+
+ tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_CLR);
+}
+
+static void tegra_eoi(struct irq_data *d)
+{
+ if (d->irq < FIRST_LEGACY_IRQ)
+ return;
+
+ tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_CLR);
}
static int tegra_retrigger(struct irq_data *d)
{
- tegra_legacy_force_irq_set(d->irq);
+ if (d->irq < FIRST_LEGACY_IRQ)
+ return 0;
+
+ tegra_irq_write_mask(d->irq, ICTLR_CPU_IEP_FIR_SET);
+
return 1;
}
-static struct irq_chip tegra_irq = {
- .name = "PPI",
- .irq_ack = tegra_ack,
- .irq_mask = tegra_mask,
- .irq_unmask = tegra_unmask,
- .irq_retrigger = tegra_retrigger,
-};
-
void __init tegra_init_irq(void)
{
- struct irq_chip *gic;
- unsigned int i;
- int irq;
+ int i;
- tegra_init_legacy_irq();
+ for (i = 0; i < NUM_ICTLRS; i++) {
+ void __iomem *ictlr = ictlr_reg_base[i];
+ writel(~0, ictlr + ICTLR_CPU_IER_CLR);
+ writel(0, ictlr + ICTLR_CPU_IEP_CLASS);
+ }
+
+ gic_arch_extn.irq_ack = tegra_ack;
+ gic_arch_extn.irq_eoi = tegra_eoi;
+ gic_arch_extn.irq_mask = tegra_mask;
+ gic_arch_extn.irq_unmask = tegra_unmask;
+ gic_arch_extn.irq_retrigger = tegra_retrigger;
gic_init(0, 29, IO_ADDRESS(TEGRA_ARM_INT_DIST_BASE),
IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x100));
-
- gic = irq_get_chip(29);
- tegra_gic_unmask_irq = gic->irq_unmask;
- tegra_gic_mask_irq = gic->irq_mask;
- tegra_gic_ack_irq = gic->irq_ack;
-#ifdef CONFIG_SMP
- tegra_irq.irq_set_affinity = gic->irq_set_affinity;
-#endif
-
- for (i = 0; i < INT_MAIN_NR; i++) {
- irq = INT_PRI_BASE + i;
- irq_set_chip_and_handler(irq, &tegra_irq, handle_level_irq);
- set_irq_flags(irq, IRQF_VALID);
- }
}
diff --git a/arch/arm/mach-tegra/legacy_irq.c b/arch/arm/mach-tegra/legacy_irq.c
deleted file mode 100644
index 38eb719..0000000
--- a/arch/arm/mach-tegra/legacy_irq.c
+++ /dev/null
@@ -1,215 +0,0 @@
-/*
- * arch/arm/mach-tegra/legacy_irq.c
- *
- * Copyright (C) 2010 Google, Inc.
- * Author: Colin Cross <ccross@android.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/io.h>
-#include <linux/kernel.h>
-#include <mach/iomap.h>
-#include <mach/irqs.h>
-#include <mach/legacy_irq.h>
-
-#define INT_SYS_NR (INT_GPIO_BASE - INT_PRI_BASE)
-#define INT_SYS_SZ (INT_SEC_BASE - INT_PRI_BASE)
-#define PPI_NR ((INT_SYS_NR+INT_SYS_SZ-1)/INT_SYS_SZ)
-
-#define ICTLR_CPU_IEP_VFIQ 0x08
-#define ICTLR_CPU_IEP_FIR 0x14
-#define ICTLR_CPU_IEP_FIR_SET 0x18
-#define ICTLR_CPU_IEP_FIR_CLR 0x1c
-
-#define ICTLR_CPU_IER 0x20
-#define ICTLR_CPU_IER_SET 0x24
-#define ICTLR_CPU_IER_CLR 0x28
-#define ICTLR_CPU_IEP_CLASS 0x2C
-
-#define ICTLR_COP_IER 0x30
-#define ICTLR_COP_IER_SET 0x34
-#define ICTLR_COP_IER_CLR 0x38
-#define ICTLR_COP_IEP_CLASS 0x3c
-
-#define NUM_ICTLRS 4
-
-static void __iomem *ictlr_reg_base[] = {
- IO_ADDRESS(TEGRA_PRIMARY_ICTLR_BASE),
- IO_ADDRESS(TEGRA_SECONDARY_ICTLR_BASE),
- IO_ADDRESS(TEGRA_TERTIARY_ICTLR_BASE),
- IO_ADDRESS(TEGRA_QUATERNARY_ICTLR_BASE),
-};
-
-static u32 tegra_legacy_wake_mask[4];
-static u32 tegra_legacy_saved_mask[4];
-
-/* When going into deep sleep, the CPU is powered down, taking the GIC with it
- In order to wake, the wake interrupts need to be enabled in the legacy
- interrupt controller. */
-void tegra_legacy_unmask_irq(unsigned int irq)
-{
- void __iomem *base;
- pr_debug("%s: %d\n", __func__, irq);
-
- irq -= 32;
- base = ictlr_reg_base[irq>>5];
- writel(1 << (irq & 31), base + ICTLR_CPU_IER_SET);
-}
-
-void tegra_legacy_mask_irq(unsigned int irq)
-{
- void __iomem *base;
- pr_debug("%s: %d\n", __func__, irq);
-
- irq -= 32;
- base = ictlr_reg_base[irq>>5];
- writel(1 << (irq & 31), base + ICTLR_CPU_IER_CLR);
-}
-
-void tegra_legacy_force_irq_set(unsigned int irq)
-{
- void __iomem *base;
- pr_debug("%s: %d\n", __func__, irq);
-
- irq -= 32;
- base = ictlr_reg_base[irq>>5];
- writel(1 << (irq & 31), base + ICTLR_CPU_IEP_FIR_SET);
-}
-
-void tegra_legacy_force_irq_clr(unsigned int irq)
-{
- void __iomem *base;
- pr_debug("%s: %d\n", __func__, irq);
-
- irq -= 32;
- base = ictlr_reg_base[irq>>5];
- writel(1 << (irq & 31), base + ICTLR_CPU_IEP_FIR_CLR);
-}
-
-int tegra_legacy_force_irq_status(unsigned int irq)
-{
- void __iomem *base;
- pr_debug("%s: %d\n", __func__, irq);
-
- irq -= 32;
- base = ictlr_reg_base[irq>>5];
- return !!(readl(base + ICTLR_CPU_IEP_FIR) & (1 << (irq & 31)));
-}
-
-void tegra_legacy_select_fiq(unsigned int irq, bool fiq)
-{
- void __iomem *base;
- pr_debug("%s: %d\n", __func__, irq);
-
- irq -= 32;
- base = ictlr_reg_base[irq>>5];
- writel(fiq << (irq & 31), base + ICTLR_CPU_IEP_CLASS);
-}
-
-unsigned long tegra_legacy_vfiq(int nr)
-{
- void __iomem *base;
- base = ictlr_reg_base[nr];
- return readl(base + ICTLR_CPU_IEP_VFIQ);
-}
-
-unsigned long tegra_legacy_class(int nr)
-{
- void __iomem *base;
- base = ictlr_reg_base[nr];
- return readl(base + ICTLR_CPU_IEP_CLASS);
-}
-
-int tegra_legacy_irq_set_wake(int irq, int enable)
-{
- irq -= 32;
- if (enable)
- tegra_legacy_wake_mask[irq >> 5] |= 1 << (irq & 31);
- else
- tegra_legacy_wake_mask[irq >> 5] &= ~(1 << (irq & 31));
-
- return 0;
-}
-
-void tegra_legacy_irq_set_lp1_wake_mask(void)
-{
- void __iomem *base;
- int i;
-
- for (i = 0; i < NUM_ICTLRS; i++) {
- base = ictlr_reg_base[i];
- tegra_legacy_saved_mask[i] = readl(base + ICTLR_CPU_IER);
- writel(tegra_legacy_wake_mask[i], base + ICTLR_CPU_IER);
- }
-}
-
-void tegra_legacy_irq_restore_mask(void)
-{
- void __iomem *base;
- int i;
-
- for (i = 0; i < NUM_ICTLRS; i++) {
- base = ictlr_reg_base[i];
- writel(tegra_legacy_saved_mask[i], base + ICTLR_CPU_IER);
- }
-}
-
-void tegra_init_legacy_irq(void)
-{
- int i;
-
- for (i = 0; i < NUM_ICTLRS; i++) {
- void __iomem *ictlr = ictlr_reg_base[i];
- writel(~0, ictlr + ICTLR_CPU_IER_CLR);
- writel(0, ictlr + ICTLR_CPU_IEP_CLASS);
- }
-}
-
-#ifdef CONFIG_PM
-static u32 cop_ier[NUM_ICTLRS];
-static u32 cpu_ier[NUM_ICTLRS];
-static u32 cpu_iep[NUM_ICTLRS];
-
-void tegra_irq_suspend(void)
-{
- unsigned long flags;
- int i;
-
- local_irq_save(flags);
- for (i = 0; i < NUM_ICTLRS; i++) {
- void __iomem *ictlr = ictlr_reg_base[i];
- cpu_ier[i] = readl(ictlr + ICTLR_CPU_IER);
- cpu_iep[i] = readl(ictlr + ICTLR_CPU_IEP_CLASS);
- cop_ier[i] = readl(ictlr + ICTLR_COP_IER);
- writel(~0, ictlr + ICTLR_COP_IER_CLR);
- }
- local_irq_restore(flags);
-}
-
-void tegra_irq_resume(void)
-{
- unsigned long flags;
- int i;
-
- local_irq_save(flags);
- for (i = 0; i < NUM_ICTLRS; i++) {
- void __iomem *ictlr = ictlr_reg_base[i];
- writel(cpu_iep[i], ictlr + ICTLR_CPU_IEP_CLASS);
- writel(~0ul, ictlr + ICTLR_CPU_IER_CLR);
- writel(cpu_ier[i], ictlr + ICTLR_CPU_IER_SET);
- writel(0, ictlr + ICTLR_COP_IEP_CLASS);
- writel(~0ul, ictlr + ICTLR_COP_IER_CLR);
- writel(cop_ier[i], ictlr + ICTLR_COP_IER_SET);
- }
- local_irq_restore(flags);
-}
-#endif
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index ec1f689..b8ae3c9 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -20,6 +20,7 @@
#include <linux/io.h>
#include <asm/cacheflush.h>
+#include <asm/hardware/gic.h>
#include <mach/hardware.h>
#include <asm/mach-types.h>
#include <asm/smp_scu.h>
@@ -122,6 +123,8 @@
for (i = 0; i < ncores; i++)
cpu_set(i, cpu_possible_map);
+
+ set_smp_cross_call(gic_raise_softirq);
}
void __init platform_smp_prepare_cpus(unsigned int max_cpus)
diff --git a/arch/arm/mach-tegra/timer.c b/arch/arm/mach-tegra/timer.c
index 0fcb1eb..9035042 100644
--- a/arch/arm/mach-tegra/timer.c
+++ b/arch/arm/mach-tegra/timer.c
@@ -98,11 +98,6 @@
}
}
-static cycle_t tegra_clocksource_read(struct clocksource *cs)
-{
- return timer_readl(TIMERUS_CNTR_1US);
-}
-
static struct clock_event_device tegra_clockevent = {
.name = "timer0",
.rating = 300,
@@ -111,14 +106,6 @@
.set_mode = tegra_timer_set_mode,
};
-static struct clocksource tegra_clocksource = {
- .name = "timer_us",
- .rating = 300,
- .read = tegra_clocksource_read,
- .mask = CLOCKSOURCE_MASK(32),
- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
static DEFINE_CLOCK_DATA(cd);
/*
@@ -234,7 +221,8 @@
init_fixed_sched_clock(&cd, tegra_update_sched_clock, 32,
1000000, SC_MULT, SC_SHIFT);
- if (clocksource_register_hz(&tegra_clocksource, 1000000)) {
+ if (clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
+ "timer_us", 1000000, 300, 32, clocksource_mmio_readl_up)) {
printk(KERN_ERR "Failed to register clocksource\n");
BUG();
}
diff --git a/arch/arm/mach-u300/timer.c b/arch/arm/mach-u300/timer.c
index 3ec58bd..891cf44 100644
--- a/arch/arm/mach-u300/timer.c
+++ b/arch/arm/mach-u300/timer.c
@@ -333,20 +333,6 @@
.handler = u300_timer_interrupt,
};
-/* Use general purpose timer 2 as clock source */
-static cycle_t u300_get_cycles(struct clocksource *cs)
-{
- return (cycles_t) readl(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC);
-}
-
-static struct clocksource clocksource_u300_1mhz = {
- .name = "GPT2",
- .rating = 300, /* Reasonably fast and accurate clock source */
- .read = u300_get_cycles,
- .mask = CLOCKSOURCE_MASK(32), /* 32 bits */
- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
/*
* Override the global weak sched_clock symbol with this
* local implementation which uses the clocksource to get some
@@ -422,7 +408,9 @@
writel(U300_TIMER_APP_EGPT2_TIMER_ENABLE,
U300_TIMER_APP_VBASE + U300_TIMER_APP_EGPT2);
- if (clocksource_register_hz(&clocksource_u300_1mhz, rate))
+ /* Use general purpose timer 2 as clock source */
+ if (clocksource_mmio_init(U300_TIMER_APP_VBASE + U300_TIMER_APP_GPT2CC,
+ "GPT2", rate, 300, 32, clocksource_mmio_readl_up))
printk(KERN_ERR "timer: failed to initialize clock "
"source %s\n", clocksource_u300_1mhz.name);
diff --git a/arch/arm/mach-ux500/Kconfig b/arch/arm/mach-ux500/Kconfig
index 5862601..54429d0 100644
--- a/arch/arm/mach-ux500/Kconfig
+++ b/arch/arm/mach-ux500/Kconfig
@@ -12,9 +12,12 @@
config UX500_SOC_DB5500
bool "DB5500"
+ select MFD_DB5500_PRCMU
config UX500_SOC_DB8500
bool "DB8500"
+ select MFD_DB8500_PRCMU
+ select REGULATOR_DB8500_PRCMU
endmenu
diff --git a/arch/arm/mach-ux500/Makefile b/arch/arm/mach-ux500/Makefile
index b549a8f..1694916 100644
--- a/arch/arm/mach-ux500/Makefile
+++ b/arch/arm/mach-ux500/Makefile
@@ -5,7 +5,7 @@
obj-y := clock.o cpu.o devices.o devices-common.o \
id.o usb.o
obj-$(CONFIG_UX500_SOC_DB5500) += cpu-db5500.o dma-db5500.o
-obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o devices-db8500.o prcmu.o
+obj-$(CONFIG_UX500_SOC_DB8500) += cpu-db8500.o devices-db8500.o
obj-$(CONFIG_MACH_U8500) += board-mop500.o board-mop500-sdi.o \
board-mop500-regulators.o \
board-mop500-uib.o board-mop500-stuib.o \
@@ -17,4 +17,4 @@
obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
obj-$(CONFIG_U5500_MODEM_IRQ) += modem-irq-db5500.o
obj-$(CONFIG_U5500_MBOX) += mbox-db5500.o
-obj-$(CONFIG_CPU_FREQ) += cpufreq.o
+
diff --git a/arch/arm/mach-ux500/board-mop500.c b/arch/arm/mach-ux500/board-mop500.c
index 6e1907fa..bb26f40 100644
--- a/arch/arm/mach-ux500/board-mop500.c
+++ b/arch/arm/mach-ux500/board-mop500.c
@@ -204,7 +204,7 @@
},
};
-#define U8500_I2C_CONTROLLER(id, _slsu, _tft, _rft, clk, _sm) \
+#define U8500_I2C_CONTROLLER(id, _slsu, _tft, _rft, clk, t_out, _sm) \
static struct nmk_i2c_controller u8500_i2c##id##_data = { \
/* \
* slave data setup time, which is \
@@ -219,19 +219,21 @@
.rft = _rft, \
/* std. mode operation */ \
.clk_freq = clk, \
+ /* Slave response timeout(ms) */\
+ .timeout = t_out, \
.sm = _sm, \
}
/*
* The board uses 4 i2c controllers, initialize all of
* them with slave data setup time of 250 ns,
- * Tx & Rx FIFO threshold values as 1 and standard
+ * Tx & Rx FIFO threshold values as 8 and standard
* mode of operation
*/
-U8500_I2C_CONTROLLER(0, 0xe, 1, 1, 100000, I2C_FREQ_MODE_STANDARD);
-U8500_I2C_CONTROLLER(1, 0xe, 1, 1, 100000, I2C_FREQ_MODE_STANDARD);
-U8500_I2C_CONTROLLER(2, 0xe, 1, 1, 100000, I2C_FREQ_MODE_STANDARD);
-U8500_I2C_CONTROLLER(3, 0xe, 1, 1, 100000, I2C_FREQ_MODE_STANDARD);
+U8500_I2C_CONTROLLER(0, 0xe, 1, 8, 100000, 200, I2C_FREQ_MODE_FAST);
+U8500_I2C_CONTROLLER(1, 0xe, 1, 8, 100000, 200, I2C_FREQ_MODE_FAST);
+U8500_I2C_CONTROLLER(2, 0xe, 1, 8, 100000, 200, I2C_FREQ_MODE_FAST);
+U8500_I2C_CONTROLLER(3, 0xe, 1, 8, 100000, 200, I2C_FREQ_MODE_FAST);
static void __init mop500_i2c_init(void)
{
diff --git a/arch/arm/mach-ux500/cpu-db5500.c b/arch/arm/mach-ux500/cpu-db5500.c
index c9dc2ef..c01bc19 100644
--- a/arch/arm/mach-ux500/cpu-db5500.c
+++ b/arch/arm/mach-ux500/cpu-db5500.c
@@ -188,6 +188,8 @@
ux500_map_io();
iotable_init(u5500_io_desc, ARRAY_SIZE(u5500_io_desc));
+
+ _PRCMU_BASE = __io_address(U5500_PRCMU_BASE);
}
static int usb_db5500_rx_dma_cfg[] = {
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 516126c..c3c4176 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -87,6 +87,8 @@
iotable_init(u8500_v1_io_desc, ARRAY_SIZE(u8500_v1_io_desc));
else if (cpu_is_u8500v2())
iotable_init(u8500_v2_io_desc, ARRAY_SIZE(u8500_v2_io_desc));
+
+ _PRCMU_BASE = __io_address(U8500_PRCMU_BASE);
}
static struct resource db8500_pmu_resources[] = {
@@ -129,9 +131,14 @@
.dev.platform_data = &db8500_pmu_platdata,
};
+static struct platform_device db8500_prcmu_device = {
+ .name = "db8500-prcmu",
+};
+
static struct platform_device *platform_devs[] __initdata = {
&u8500_dma40_device,
&db8500_pmu_device,
+ &db8500_prcmu_device,
};
static resource_size_t __initdata db8500_gpio_base[] = {
diff --git a/arch/arm/mach-ux500/cpu.c b/arch/arm/mach-ux500/cpu.c
index 5a43107..1da23bb 100644
--- a/arch/arm/mach-ux500/cpu.c
+++ b/arch/arm/mach-ux500/cpu.c
@@ -8,6 +8,8 @@
#include <linux/platform_device.h>
#include <linux/io.h>
#include <linux/clk.h>
+#include <linux/mfd/db8500-prcmu.h>
+#include <linux/mfd/db5500-prcmu.h>
#include <asm/cacheflush.h>
#include <asm/hardware/cache-l2x0.h>
@@ -19,10 +21,11 @@
#include <mach/hardware.h>
#include <mach/setup.h>
#include <mach/devices.h>
-#include <mach/prcmu.h>
#include "clock.h"
+void __iomem *_PRCMU_BASE;
+
#ifdef CONFIG_CACHE_L2X0
static void __iomem *l2x0_base;
#endif
@@ -47,6 +50,8 @@
* Init clocks here so that they are available for system timer
* initialization.
*/
+ if (cpu_is_u5500())
+ db5500_prcmu_early_init();
if (cpu_is_u8500())
prcmu_early_init();
clk_init();
diff --git a/arch/arm/mach-ux500/cpufreq.c b/arch/arm/mach-ux500/cpufreq.c
deleted file mode 100644
index 5c5b747..0000000
--- a/arch/arm/mach-ux500/cpufreq.c
+++ /dev/null
@@ -1,211 +0,0 @@
-/*
- * CPU frequency scaling for u8500
- * Inspired by linux/arch/arm/mach-davinci/cpufreq.c
- *
- * Copyright (C) STMicroelectronics 2009
- * Copyright (C) ST-Ericsson SA 2010
- *
- * License Terms: GNU General Public License v2
- *
- * Author: Sundar Iyer <sundar.iyer@stericsson.com>
- * Author: Martin Persson <martin.persson@stericsson.com>
- * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
- *
- */
-
-#include <linux/platform_device.h>
-#include <linux/kernel.h>
-#include <linux/cpufreq.h>
-#include <linux/delay.h>
-
-#include <mach/hardware.h>
-#include <mach/prcmu.h>
-#include <mach/prcmu-defs.h>
-
-#define DRIVER_NAME "cpufreq-u8500"
-#define CPUFREQ_NAME "u8500"
-
-static struct device *dev;
-
-static struct cpufreq_frequency_table freq_table[] = {
- [0] = {
- .index = 0,
- .frequency = 200000,
- },
- [1] = {
- .index = 1,
- .frequency = 300000,
- },
- [2] = {
- .index = 2,
- .frequency = 600000,
- },
- [3] = {
- /* Used for CPU_OPP_MAX, if available */
- .index = 3,
- .frequency = CPUFREQ_TABLE_END,
- },
- [4] = {
- .index = 4,
- .frequency = CPUFREQ_TABLE_END,
- },
-};
-
-static enum prcmu_cpu_opp index2opp[] = {
- CPU_OPP_EXT_CLK,
- CPU_OPP_50,
- CPU_OPP_100,
- CPU_OPP_MAX
-};
-
-static int u8500_cpufreq_verify_speed(struct cpufreq_policy *policy)
-{
- return cpufreq_frequency_table_verify(policy, freq_table);
-}
-
-static int u8500_cpufreq_target(struct cpufreq_policy *policy,
- unsigned int target_freq,
- unsigned int relation)
-{
- struct cpufreq_freqs freqs;
- unsigned int index;
- int ret = 0;
-
- /*
- * Ensure desired rate is within allowed range. Some govenors
- * (ondemand) will just pass target_freq=0 to get the minimum.
- */
- if (target_freq < policy->cpuinfo.min_freq)
- target_freq = policy->cpuinfo.min_freq;
- if (target_freq > policy->cpuinfo.max_freq)
- target_freq = policy->cpuinfo.max_freq;
-
- ret = cpufreq_frequency_table_target(policy, freq_table,
- target_freq, relation, &index);
- if (ret < 0) {
- dev_err(dev, "Could not look up next frequency\n");
- return ret;
- }
-
- freqs.old = policy->cur;
- freqs.new = freq_table[index].frequency;
- freqs.cpu = policy->cpu;
-
- if (freqs.old == freqs.new) {
- dev_dbg(dev, "Current and target frequencies are equal\n");
- return 0;
- }
-
- dev_dbg(dev, "transition: %u --> %u\n", freqs.old, freqs.new);
- cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
-
- ret = prcmu_set_cpu_opp(index2opp[index]);
- if (ret < 0) {
- dev_err(dev, "Failed to set OPP level\n");
- return ret;
- }
-
- cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
-
- return ret;
-}
-
-static unsigned int u8500_cpufreq_getspeed(unsigned int cpu)
-{
- int i;
-
- for (i = 0; prcmu_get_cpu_opp() != index2opp[i]; i++)
- ;
- return freq_table[i].frequency;
-}
-
-static int __cpuinit u8500_cpu_init(struct cpufreq_policy *policy)
-{
- int res;
-
- BUILD_BUG_ON(ARRAY_SIZE(index2opp) + 1 != ARRAY_SIZE(freq_table));
-
- if (cpu_is_u8500v2()) {
- freq_table[1].frequency = 400000;
- freq_table[2].frequency = 800000;
- if (prcmu_has_arm_maxopp())
- freq_table[3].frequency = 1000000;
- }
-
- /* get policy fields based on the table */
- res = cpufreq_frequency_table_cpuinfo(policy, freq_table);
- if (!res)
- cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
- else {
- dev_err(dev, "u8500-cpufreq : Failed to read policy table\n");
- return res;
- }
-
- policy->min = policy->cpuinfo.min_freq;
- policy->max = policy->cpuinfo.max_freq;
- policy->cur = u8500_cpufreq_getspeed(policy->cpu);
- policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
-
- /*
- * FIXME : Need to take time measurement across the target()
- * function with no/some/all drivers in the notification
- * list.
- */
- policy->cpuinfo.transition_latency = 200 * 1000; /* in ns */
-
- /* policy sharing between dual CPUs */
- cpumask_copy(policy->cpus, &cpu_present_map);
-
- policy->shared_type = CPUFREQ_SHARED_TYPE_ALL;
-
- return res;
-}
-
-static struct freq_attr *u8500_cpufreq_attr[] = {
- &cpufreq_freq_attr_scaling_available_freqs,
- NULL,
-};
-static int u8500_cpu_exit(struct cpufreq_policy *policy)
-{
- cpufreq_frequency_table_put_attr(policy->cpu);
- return 0;
-}
-
-static struct cpufreq_driver u8500_driver = {
- .owner = THIS_MODULE,
- .flags = CPUFREQ_STICKY,
- .verify = u8500_cpufreq_verify_speed,
- .target = u8500_cpufreq_target,
- .get = u8500_cpufreq_getspeed,
- .init = u8500_cpu_init,
- .exit = u8500_cpu_exit,
- .name = CPUFREQ_NAME,
- .attr = u8500_cpufreq_attr,
-};
-
-static int __init u8500_cpufreq_probe(struct platform_device *pdev)
-{
- dev = &pdev->dev;
- return cpufreq_register_driver(&u8500_driver);
-}
-
-static int __exit u8500_cpufreq_remove(struct platform_device *pdev)
-{
- return cpufreq_unregister_driver(&u8500_driver);
-}
-
-static struct platform_driver u8500_cpufreq_driver = {
- .driver = {
- .name = DRIVER_NAME,
- .owner = THIS_MODULE,
- },
- .remove = __exit_p(u8500_cpufreq_remove),
-};
-
-static int __init u8500_cpufreq_init(void)
-{
- return platform_driver_probe(&u8500_cpufreq_driver,
- &u8500_cpufreq_probe);
-}
-
-device_initcall(u8500_cpufreq_init);
diff --git a/arch/arm/mach-ux500/include/mach/db5500-regs.h b/arch/arm/mach-ux500/include/mach/db5500-regs.h
index bd88c1e..6ad9832 100644
--- a/arch/arm/mach-ux500/include/mach/db5500-regs.h
+++ b/arch/arm/mach-ux500/include/mach/db5500-regs.h
@@ -17,6 +17,8 @@
#define U5500_GIC_DIST_BASE 0xA0411000
#define U5500_GIC_CPU_BASE 0xA0410100
#define U5500_DMA_BASE 0x90030000
+#define U5500_STM_BASE 0x90020000
+#define U5500_STM_REG_BASE (U5500_STM_BASE + 0xF000)
#define U5500_MCDE_BASE 0xA0400000
#define U5500_MODEM_BASE 0xB0000000
#define U5500_L2CC_BASE 0xA0412000
@@ -29,7 +31,9 @@
#define U5500_NAND0_BASE 0x60000000
#define U5500_NAND1_BASE 0x70000000
#define U5500_TWD_BASE 0xa0410600
+#define U5500_ICN_BASE 0xA0040000
#define U5500_B2R2_BASE 0xa0200000
+#define U5500_BOOT_ROM_BASE 0x90000000
#define U5500_FSMC_BASE (U5500_PER1_BASE + 0x0000)
#define U5500_SDI0_BASE (U5500_PER1_BASE + 0x1000)
@@ -60,6 +64,7 @@
#define U5500_MSP1_BASE (U5500_PER4_BASE + 0x9000)
#define U5500_GPIO2_BASE (U5500_PER4_BASE + 0xA000)
#define U5500_CDETECT_BASE (U5500_PER4_BASE + 0xF000)
+#define U5500_PRCMU_TCDM_BASE (U5500_PER4_BASE + 0x18000)
#define U5500_SPI0_BASE (U5500_PER5_BASE + 0x0000)
#define U5500_SPI1_BASE (U5500_PER5_BASE + 0x1000)
@@ -83,7 +88,7 @@
#define U5500_HASH0_BASE (U5500_PER6_BASE + 0x1000)
#define U5500_HASH1_BASE (U5500_PER6_BASE + 0x2000)
#define U5500_PKA_BASE (U5500_PER6_BASE + 0x4000)
-#define U5500_PKAM_BASE (U5500_PER6_BASE + 0x5000)
+#define U5500_PKAM_BASE (U5500_PER6_BASE + 0x5100)
#define U5500_MTU0_BASE (U5500_PER6_BASE + 0x6000)
#define U5500_MTU1_BASE (U5500_PER6_BASE + 0x7000)
#define U5500_CR_BASE (U5500_PER6_BASE + 0x8000)
@@ -114,8 +119,19 @@
#define U5500_MBOX2_LOCAL_START (U5500_MBOX_BASE + 0x20)
#define U5500_MBOX2_LOCAL_END (U5500_MBOX_BASE + 0x3F)
-#define U5500_ESRAM_BASE 0x40000000
+#define U5500_ACCCON_BASE_SEC (0xBFFF0000)
+#define U5500_ACCCON_BASE (0xBFFF1000)
+#define U5500_ACCCON_CPUVEC_RESET_ADDR_OFFSET (0x00000020)
+#define U5500_ACCCON_ACC_CPU_CTRL_OFFSET (0x000000BC)
+
+#define U5500_ESRAM_BASE 0x40000000
#define U5500_ESRAM_DMA_LCPA_OFFSET 0x10000
#define U5500_DMA_LCPA_BASE (U5500_ESRAM_BASE + U5500_ESRAM_DMA_LCPA_OFFSET)
+#define U5500_MCDE_SIZE 0x1000
+#define U5500_DSI_LINK_SIZE 0x1000
+#define U5500_DSI_LINK_COUNT 0x2
+#define U5500_DSI_LINK1_BASE (U5500_MCDE_BASE + U5500_MCDE_SIZE)
+#define U5500_DSI_LINK2_BASE (U5500_DSI_LINK1_BASE + U5500_DSI_LINK_SIZE)
+
#endif
diff --git a/arch/arm/mach-ux500/include/mach/db8500-regs.h b/arch/arm/mach-ux500/include/mach/db8500-regs.h
index 16647b2..0499971 100644
--- a/arch/arm/mach-ux500/include/mach/db8500-regs.h
+++ b/arch/arm/mach-ux500/include/mach/db8500-regs.h
@@ -15,8 +15,13 @@
#define U8500_ESRAM_BANK2 (U8500_ESRAM_BANK1 + U8500_ESRAM_BANK_SIZE)
#define U8500_ESRAM_BANK3 (U8500_ESRAM_BANK2 + U8500_ESRAM_BANK_SIZE)
#define U8500_ESRAM_BANK4 (U8500_ESRAM_BANK3 + U8500_ESRAM_BANK_SIZE)
-/* Use bank 4 for DMA LCPA */
-#define U8500_DMA_LCPA_BASE U8500_ESRAM_BANK4
+/*
+ * on V1 DMA uses 4KB for logical parameters position is right after the 64KB
+ * reserved for security
+ */
+#define U8500_ESRAM_DMA_LCPA_OFFSET 0x10000
+
+#define U8500_DMA_LCPA_BASE (U8500_ESRAM_BANK0 + U8500_ESRAM_DMA_LCPA_OFFSET)
#define U8500_DMA_LCPA_BASE_ED (U8500_ESRAM_BANK4 + 0x4000)
#define U8500_PER3_BASE 0x80000000
@@ -27,9 +32,12 @@
#define U8500_B2R2_BASE 0x80130000
#define U8500_HSEM_BASE 0x80140000
#define U8500_PER4_BASE 0x80150000
+#define U8500_TPIU_BASE 0x80190000
#define U8500_ICN_BASE 0x81000000
#define U8500_BOOT_ROM_BASE 0x90000000
+/* ASIC ID is at 0xbf4 offset within this region */
+#define U8500_ASIC_ID_BASE 0x9001D000
#define U8500_PER6_BASE 0xa03c0000
#define U8500_PER5_BASE 0xa03e0000
@@ -70,13 +78,15 @@
/* per6 base addresses */
#define U8500_RNG_BASE (U8500_PER6_BASE + 0x0000)
-#define U8500_PKA_BASE (U8500_PER6_BASE + 0x1000)
-#define U8500_PKAM_BASE (U8500_PER6_BASE + 0x2000)
+#define U8500_HASH0_BASE (U8500_PER6_BASE + 0x1000)
+#define U8500_HASH1_BASE (U8500_PER6_BASE + 0x2000)
+#define U8500_PKA_BASE (U8500_PER6_BASE + 0x4000)
+#define U8500_PKAM_BASE (U8500_PER6_BASE + 0x5100)
#define U8500_MTU0_BASE (U8500_PER6_BASE + 0x6000) /* v1 */
#define U8500_MTU1_BASE (U8500_PER6_BASE + 0x7000) /* v1 */
#define U8500_CR_BASE (U8500_PER6_BASE + 0x8000) /* v1 */
-#define U8500_CRYPTO0_BASE (U8500_PER6_BASE + 0xa000)
-#define U8500_CRYPTO1_BASE (U8500_PER6_BASE + 0xb000)
+#define U8500_CRYP0_BASE (U8500_PER6_BASE + 0xa000)
+#define U8500_CRYP1_BASE (U8500_PER6_BASE + 0xb000)
#define U8500_CLKRST6_BASE (U8500_PER6_BASE + 0xf000)
/* per5 base addresses */
@@ -93,7 +103,8 @@
#define U8500_DMC_BASE (U8500_PER4_BASE + 0x06000)
#define U8500_PRCMU_BASE (U8500_PER4_BASE + 0x07000)
#define U8500_PRCMU_TCDM_BASE_V1 (U8500_PER4_BASE + 0x0f000)
-#define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x68000)
+#define U8500_PRCMU_TCDM_BASE (U8500_PER4_BASE + 0x68000)
+#define U8500_PRCMU_TCPM_BASE (U8500_PER4_BASE + 0x60000)
/* per3 base addresses */
#define U8500_FSMC_BASE (U8500_PER3_BASE + 0x0000)
@@ -124,6 +135,7 @@
#define U8500_I2C1_BASE (U8500_PER1_BASE + 0x2000)
#define U8500_MSP0_BASE (U8500_PER1_BASE + 0x3000)
#define U8500_MSP1_BASE (U8500_PER1_BASE + 0x4000)
+#define U8500_MSP3_BASE (U8500_PER1_BASE + 0x5000)
#define U8500_SDI0_BASE (U8500_PER1_BASE + 0x6000)
#define U8500_I2C2_BASE (U8500_PER1_BASE + 0x8000)
#define U8500_SPI3_BASE (U8500_PER1_BASE + 0x9000)
@@ -143,4 +155,15 @@
#define U8500_GPIOBANK7_BASE (U8500_GPIO2_BASE + 0x80)
#define U8500_GPIOBANK8_BASE U8500_GPIO3_BASE
+#define U8500_MCDE_SIZE 0x1000
+#define U8500_DSI_LINK_SIZE 0x1000
+#define U8500_DSI_LINK1_BASE (U8500_MCDE_BASE + U8500_MCDE_SIZE)
+#define U8500_DSI_LINK2_BASE (U8500_DSI_LINK1_BASE + U8500_DSI_LINK_SIZE)
+#define U8500_DSI_LINK3_BASE (U8500_DSI_LINK2_BASE + U8500_DSI_LINK_SIZE)
+#define U8500_DSI_LINK_COUNT 0x3
+
+/* Modem and APE physical addresses */
+#define U8500_MODEM_BASE 0xe000000
+#define U8500_APE_BASE 0x6000000
+
#endif
diff --git a/arch/arm/mach-ux500/include/mach/hardware.h b/arch/arm/mach-ux500/include/mach/hardware.h
index bf63f26..2c6f710 100644
--- a/arch/arm/mach-ux500/include/mach/hardware.h
+++ b/arch/arm/mach-ux500/include/mach/hardware.h
@@ -35,6 +35,7 @@
#ifndef __ASSEMBLY__
#include <mach/id.h>
+extern void __iomem *_PRCMU_BASE;
#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
diff --git a/arch/arm/mach-ux500/include/mach/id.h b/arch/arm/mach-ux500/include/mach/id.h
index f1288d1..02b541a3 100644
--- a/arch/arm/mach-ux500/include/mach/id.h
+++ b/arch/arm/mach-ux500/include/mach/id.h
@@ -75,6 +75,26 @@
return cpu_is_u8500() && ((dbx500_revision() & 0xf0) == 0xB0);
}
+static inline bool cpu_is_u8500v20(void)
+{
+ return cpu_is_u8500() && (dbx500_revision() == 0xB0);
+}
+
+static inline bool cpu_is_u8500v21(void)
+{
+ return cpu_is_u8500() && (dbx500_revision() == 0xB1);
+}
+
+static inline bool cpu_is_u8500v20_or_later(void)
+{
+ return cpu_is_u8500() && !cpu_is_u8500v10() && !cpu_is_u8500v11();
+}
+
+static inline bool ux500_is_svp(void)
+{
+ return false;
+}
+
#define ux500_unknown_soc() BUG()
#endif
diff --git a/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h b/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h
index 97ef55f..4796990 100644
--- a/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h
+++ b/arch/arm/mach-ux500/include/mach/irqs-board-mop500.h
@@ -50,6 +50,11 @@
#define MOP500_IRQ_END MOP500_NR_IRQS
+/*
+ * We may have several boards, but only one will run at a
+ * time, so the one with most IRQs will bump this ahead,
+ * but the IRQ_BOARD_START remains the same for either board.
+ */
#if MOP500_IRQ_END > IRQ_BOARD_END
#undef IRQ_BOARD_END
#define IRQ_BOARD_END MOP500_IRQ_END
diff --git a/arch/arm/mach-ux500/include/mach/irqs-board-u5500.h b/arch/arm/mach-ux500/include/mach/irqs-board-u5500.h
new file mode 100644
index 0000000..29d972c
--- /dev/null
+++ b/arch/arm/mach-ux500/include/mach/irqs-board-u5500.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * License terms: GNU General Public License (GPL) version 2
+ */
+
+#ifndef __MACH_IRQS_BOARD_U5500_H
+#define __MACH_IRQS_BOARD_U5500_H
+
+#define AB5500_NR_IRQS 5
+#define IRQ_AB5500_BASE IRQ_BOARD_START
+#define IRQ_AB5500_END (IRQ_AB5500_BASE + AB5500_NR_IRQS)
+
+#define U5500_IRQ_END IRQ_AB5500_END
+
+#if IRQ_BOARD_END < U5500_IRQ_END
+#undef IRQ_BOARD_END
+#define IRQ_BOARD_END U5500_IRQ_END
+#endif
+
+#endif
diff --git a/arch/arm/mach-ux500/include/mach/irqs-db5500.h b/arch/arm/mach-ux500/include/mach/irqs-db5500.h
index bfa123d..7723977 100644
--- a/arch/arm/mach-ux500/include/mach/irqs-db5500.h
+++ b/arch/arm/mach-ux500/include/mach/irqs-db5500.h
@@ -83,4 +83,31 @@
#define IRQ_DB5500_GPIO6 (IRQ_SHPI_START + 125)
#define IRQ_DB5500_GPIO7 (IRQ_SHPI_START + 126)
+#ifdef CONFIG_UX500_SOC_DB5500
+
+/*
+ * After the GPIO ones we reserve a range of IRQ:s in which virtual
+ * IRQ:s representing modem IRQ:s can be allocated
+ */
+#define IRQ_MODEM_EVENTS_BASE IRQ_SOC_START
+#define IRQ_MODEM_EVENTS_NBR 72
+#define IRQ_MODEM_EVENTS_END (IRQ_MODEM_EVENTS_BASE + IRQ_MODEM_EVENTS_NBR)
+
+/* List of virtual IRQ:s that are allocated from the range above */
+#define MBOX_PAIR0_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 43)
+#define MBOX_PAIR1_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 45)
+#define MBOX_PAIR2_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 41)
+
+/*
+ * We may have several SoCs, but only one will run at a
+ * time, so the one with most IRQs will bump this ahead,
+ * but the IRQ_SOC_START remains the same for either SoC.
+ */
+#if IRQ_SOC_END < IRQ_MODEM_EVENTS_END
+#undef IRQ_SOC_END
+#define IRQ_SOC_END IRQ_MODEM_EVENTS_END
+#endif
+
+#endif /* CONFIG_UX500_SOC_DB5500 */
+
#endif
diff --git a/arch/arm/mach-ux500/include/mach/irqs-db8500.h b/arch/arm/mach-ux500/include/mach/irqs-db8500.h
index 8b5d9f0..68bc149 100644
--- a/arch/arm/mach-ux500/include/mach/irqs-db8500.h
+++ b/arch/arm/mach-ux500/include/mach/irqs-db8500.h
@@ -93,4 +93,58 @@
#define IRQ_DB8500_GPIO7 (IRQ_SHPI_START + 126)
#define IRQ_DB8500_GPIO8 (IRQ_SHPI_START + 127)
+#define IRQ_CA_WAKE_REQ_ED (IRQ_SHPI_START + 71)
+#define IRQ_AC_READ_NOTIFICATION_0_ED (IRQ_SHPI_START + 66)
+#define IRQ_AC_READ_NOTIFICATION_1_ED (IRQ_SHPI_START + 64)
+#define IRQ_CA_MSG_PEND_NOTIFICATION_0_ED (IRQ_SHPI_START + 67)
+#define IRQ_CA_MSG_PEND_NOTIFICATION_1_ED (IRQ_SHPI_START + 65)
+
+#define IRQ_CA_WAKE_REQ_V1 (IRQ_SHPI_START + 83)
+#define IRQ_AC_READ_NOTIFICATION_0_V1 (IRQ_SHPI_START + 78)
+#define IRQ_AC_READ_NOTIFICATION_1_V1 (IRQ_SHPI_START + 76)
+#define IRQ_CA_MSG_PEND_NOTIFICATION_0_V1 (IRQ_SHPI_START + 79)
+#define IRQ_CA_MSG_PEND_NOTIFICATION_1_V1 (IRQ_SHPI_START + 77)
+
+#ifdef CONFIG_UX500_SOC_DB8500
+
+/* Virtual interrupts corresponding to the PRCMU wakeups. */
+#define IRQ_PRCMU_BASE IRQ_SOC_START
+#define NUM_PRCMU_WAKEUPS (IRQ_PRCMU_END - IRQ_PRCMU_BASE)
+
+#define IRQ_PRCMU_RTC (IRQ_PRCMU_BASE)
+#define IRQ_PRCMU_RTT0 (IRQ_PRCMU_BASE + 1)
+#define IRQ_PRCMU_RTT1 (IRQ_PRCMU_BASE + 2)
+#define IRQ_PRCMU_HSI0 (IRQ_PRCMU_BASE + 3)
+#define IRQ_PRCMU_HSI1 (IRQ_PRCMU_BASE + 4)
+#define IRQ_PRCMU_CA_WAKE (IRQ_PRCMU_BASE + 5)
+#define IRQ_PRCMU_USB (IRQ_PRCMU_BASE + 6)
+#define IRQ_PRCMU_ABB (IRQ_PRCMU_BASE + 7)
+#define IRQ_PRCMU_ABB_FIFO (IRQ_PRCMU_BASE + 8)
+#define IRQ_PRCMU_ARM (IRQ_PRCMU_BASE + 9)
+#define IRQ_PRCMU_MODEM_SW_RESET_REQ (IRQ_PRCMU_BASE + 10)
+#define IRQ_PRCMU_GPIO0 (IRQ_PRCMU_BASE + 11)
+#define IRQ_PRCMU_GPIO1 (IRQ_PRCMU_BASE + 12)
+#define IRQ_PRCMU_GPIO2 (IRQ_PRCMU_BASE + 13)
+#define IRQ_PRCMU_GPIO3 (IRQ_PRCMU_BASE + 14)
+#define IRQ_PRCMU_GPIO4 (IRQ_PRCMU_BASE + 15)
+#define IRQ_PRCMU_GPIO5 (IRQ_PRCMU_BASE + 16)
+#define IRQ_PRCMU_GPIO6 (IRQ_PRCMU_BASE + 17)
+#define IRQ_PRCMU_GPIO7 (IRQ_PRCMU_BASE + 18)
+#define IRQ_PRCMU_GPIO8 (IRQ_PRCMU_BASE + 19)
+#define IRQ_PRCMU_CA_SLEEP (IRQ_PRCMU_BASE + 20)
+#define IRQ_PRCMU_HOTMON_LOW (IRQ_PRCMU_BASE + 21)
+#define IRQ_PRCMU_HOTMON_HIGH (IRQ_PRCMU_BASE + 22)
+#define IRQ_PRCMU_END (IRQ_PRCMU_BASE + 23)
+
+/*
+ * We may have several SoCs, but only one will run at a
+ * time, so the one with most IRQs will bump this ahead,
+ * but the IRQ_SOC_START remains the same for either SoC.
+ */
+#if IRQ_SOC_END < IRQ_PRCMU_END
+#undef IRQ_SOC_END
+#define IRQ_SOC_END IRQ_PRCMU_END
+#endif
+
+#endif /* CONFIG_UX500_SOC_DB8500 */
#endif
diff --git a/arch/arm/mach-ux500/include/mach/irqs.h b/arch/arm/mach-ux500/include/mach/irqs.h
index ba1294c..9db68d2 100644
--- a/arch/arm/mach-ux500/include/mach/irqs.h
+++ b/arch/arm/mach-ux500/include/mach/irqs.h
@@ -10,49 +10,47 @@
#ifndef ASM_ARCH_IRQS_H
#define ASM_ARCH_IRQS_H
-#include <mach/irqs-db5500.h>
-#include <mach/irqs-db8500.h>
+#include <mach/hardware.h>
-#define IRQ_LOCALTIMER 29
-#define IRQ_LOCALWDOG 30
+#define IRQ_LOCALTIMER 29
+#define IRQ_LOCALWDOG 30
/* Shared Peripheral Interrupt (SHPI) */
#define IRQ_SHPI_START 32
-/* Interrupt numbers generic for shared peripheral */
+/*
+ * MTU0 preserved for now until plat-nomadik is taught not to use it. Don't
+ * add any other IRQs here, use the irqs-dbx500.h files.
+ */
#define IRQ_MTU0 (IRQ_SHPI_START + 4)
-/* There are 128 shared peripheral interrupts assigned to
- * INTID[160:32]. The first 32 interrupts are reserved.
- */
-#define DBX500_NR_INTERNAL_IRQS 161
+#define DBX500_NR_INTERNAL_IRQS 160
/* After chip-specific IRQ numbers we have the GPIO ones */
#define NOMADIK_NR_GPIO 288
#define NOMADIK_GPIO_TO_IRQ(gpio) ((gpio) + DBX500_NR_INTERNAL_IRQS)
#define NOMADIK_IRQ_TO_GPIO(irq) ((irq) - DBX500_NR_INTERNAL_IRQS)
-#define IRQ_BOARD_START NOMADIK_GPIO_TO_IRQ(NOMADIK_NR_GPIO)
+#define IRQ_GPIO_END NOMADIK_GPIO_TO_IRQ(NOMADIK_NR_GPIO)
+#define IRQ_SOC_START IRQ_GPIO_END
+/* This will be overridden by SoC-specific irq headers */
+#define IRQ_SOC_END IRQ_SOC_START
+
+#include <mach/irqs-db5500.h>
+#include <mach/irqs-db8500.h>
+
+#define IRQ_BOARD_START IRQ_SOC_END
/* This will be overridden by board-specific irq headers */
-#define IRQ_BOARD_END IRQ_BOARD_START
+#define IRQ_BOARD_END IRQ_BOARD_START
#ifdef CONFIG_MACH_U8500
#include <mach/irqs-board-mop500.h>
#endif
-/*
- * After the board specific IRQ:s we reserve a range of IRQ:s in which virtual
- * IRQ:s representing modem IRQ:s can be allocated
- */
-#define IRQ_MODEM_EVENTS_BASE (IRQ_BOARD_END + 1)
-#define IRQ_MODEM_EVENTS_NBR 72
-#define IRQ_MODEM_EVENTS_END (IRQ_MODEM_EVENTS_BASE + IRQ_MODEM_EVENTS_NBR)
+#ifdef CONFIG_MACH_U5500
+#include <mach/irqs-board-u5500.h>
+#endif
-/* List of virtual IRQ:s that are allocated from the range above */
-#define MBOX_PAIR0_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 43)
-#define MBOX_PAIR1_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 45)
-#define MBOX_PAIR2_VIRT_IRQ (IRQ_MODEM_EVENTS_BASE + 41)
-
-#define NR_IRQS IRQ_MODEM_EVENTS_END
+#define NR_IRQS IRQ_BOARD_END
#endif /* ASM_ARCH_IRQS_H */
diff --git a/arch/arm/mach-ux500/include/mach/prcmu-defs.h b/arch/arm/mach-ux500/include/mach/prcmu-defs.h
deleted file mode 100644
index 848ba64..0000000
--- a/arch/arm/mach-ux500/include/mach/prcmu-defs.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * Copyright (C) STMicroelectronics 2009
- * Copyright (C) ST-Ericsson SA 2010
- *
- * Author: Sundar Iyer <sundar.iyer@stericsson.com>
- * Author: Martin Persson <martin.persson@stericsson.com>
- *
- * License Terms: GNU General Public License v2
- *
- * PRCM Unit definitions
- */
-
-#ifndef __MACH_PRCMU_DEFS_H
-#define __MACH_PRCMU_DEFS_H
-
-enum prcmu_cpu_opp {
- CPU_OPP_INIT = 0x00,
- CPU_OPP_NO_CHANGE = 0x01,
- CPU_OPP_100 = 0x02,
- CPU_OPP_50 = 0x03,
- CPU_OPP_MAX = 0x04,
- CPU_OPP_EXT_CLK = 0x07
-};
-enum prcmu_ape_opp {
- APE_OPP_NO_CHANGE = 0x00,
- APE_OPP_100 = 0x02,
- APE_OPP_50 = 0x03,
-};
-
-#endif /* __MACH_PRCMU_DEFS_H */
diff --git a/arch/arm/mach-ux500/include/mach/prcmu-regs.h b/arch/arm/mach-ux500/include/mach/prcmu-regs.h
deleted file mode 100644
index 455467e..0000000
--- a/arch/arm/mach-ux500/include/mach/prcmu-regs.h
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- * Copyright (C) STMicroelectronics 2009
- * Copyright (C) ST-Ericsson SA 2010
- *
- * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
- * Author: Sundar Iyer <sundar.iyer@stericsson.com>
- *
- * License Terms: GNU General Public License v2
- *
- * PRCM Unit registers
- */
-
-#ifndef __MACH_PRCMU_REGS_H
-#define __MACH_PRCMU_REGS_H
-
-#include <mach/hardware.h>
-
-#define _PRCMU_BASE IO_ADDRESS(U8500_PRCMU_BASE)
-
-#define PRCM_ARM_PLLDIVPS (_PRCMU_BASE + 0x118)
-#define PRCM_ARM_CHGCLKREQ (_PRCMU_BASE + 0x114)
-#define PRCM_PLLARM_ENABLE (_PRCMU_BASE + 0x98)
-#define PRCM_ARMCLKFIX_MGT (_PRCMU_BASE + 0x0)
-#define PRCM_A9_RESETN_CLR (_PRCMU_BASE + 0x1f4)
-#define PRCM_A9_RESETN_SET (_PRCMU_BASE + 0x1f0)
-#define PRCM_ARM_LS_CLAMP (_PRCMU_BASE + 0x30c)
-#define PRCM_SRAM_A9 (_PRCMU_BASE + 0x308)
-
-/* ARM WFI Standby signal register */
-#define PRCM_ARM_WFI_STANDBY (_PRCMU_BASE + 0x130)
-#define PRCMU_IOCR (_PRCMU_BASE + 0x310)
-
-/* CPU mailbox registers */
-#define PRCM_MBOX_CPU_VAL (_PRCMU_BASE + 0x0fc)
-#define PRCM_MBOX_CPU_SET (_PRCMU_BASE + 0x100)
-#define PRCM_MBOX_CPU_CLR (_PRCMU_BASE + 0x104)
-
-/* Dual A9 core interrupt management unit registers */
-#define PRCM_A9_MASK_REQ (_PRCMU_BASE + 0x328)
-#define PRCM_A9_MASK_ACK (_PRCMU_BASE + 0x32c)
-#define PRCM_ARMITMSK31TO0 (_PRCMU_BASE + 0x11c)
-#define PRCM_ARMITMSK63TO32 (_PRCMU_BASE + 0x120)
-#define PRCM_ARMITMSK95TO64 (_PRCMU_BASE + 0x124)
-#define PRCM_ARMITMSK127TO96 (_PRCMU_BASE + 0x128)
-#define PRCM_POWER_STATE_VAL (_PRCMU_BASE + 0x25C)
-#define PRCM_ARMITVAL31TO0 (_PRCMU_BASE + 0x260)
-#define PRCM_ARMITVAL63TO32 (_PRCMU_BASE + 0x264)
-#define PRCM_ARMITVAL95TO64 (_PRCMU_BASE + 0x268)
-#define PRCM_ARMITVAL127TO96 (_PRCMU_BASE + 0x26C)
-
-#define PRCM_HOSTACCESS_REQ (_PRCMU_BASE + 0x334)
-#define ARM_WAKEUP_MODEM 0x1
-
-#define PRCM_ARM_IT1_CLEAR (_PRCMU_BASE + 0x48C)
-#define PRCM_ARM_IT1_VAL (_PRCMU_BASE + 0x494)
-#define PRCM_HOLD_EVT (_PRCMU_BASE + 0x174)
-
-#define PRCM_ITSTATUS0 (_PRCMU_BASE + 0x148)
-#define PRCM_ITSTATUS1 (_PRCMU_BASE + 0x150)
-#define PRCM_ITSTATUS2 (_PRCMU_BASE + 0x158)
-#define PRCM_ITSTATUS3 (_PRCMU_BASE + 0x160)
-#define PRCM_ITSTATUS4 (_PRCMU_BASE + 0x168)
-#define PRCM_ITSTATUS5 (_PRCMU_BASE + 0x484)
-#define PRCM_ITCLEAR5 (_PRCMU_BASE + 0x488)
-#define PRCM_ARMIT_MASKXP70_IT (_PRCMU_BASE + 0x1018)
-
-/* System reset register */
-#define PRCM_APE_SOFTRST (_PRCMU_BASE + 0x228)
-
-/* Level shifter and clamp control registers */
-#define PRCM_MMIP_LS_CLAMP_SET (_PRCMU_BASE + 0x420)
-#define PRCM_MMIP_LS_CLAMP_CLR (_PRCMU_BASE + 0x424)
-
-/* PRCMU clock/PLL/reset registers */
-#define PRCM_PLLDSI_FREQ (_PRCMU_BASE + 0x500)
-#define PRCM_PLLDSI_ENABLE (_PRCMU_BASE + 0x504)
-#define PRCM_LCDCLK_MGT (_PRCMU_BASE + 0x044)
-#define PRCM_MCDECLK_MGT (_PRCMU_BASE + 0x064)
-#define PRCM_HDMICLK_MGT (_PRCMU_BASE + 0x058)
-#define PRCM_TVCLK_MGT (_PRCMU_BASE + 0x07c)
-#define PRCM_DSI_PLLOUT_SEL (_PRCMU_BASE + 0x530)
-#define PRCM_DSITVCLK_DIV (_PRCMU_BASE + 0x52C)
-#define PRCM_APE_RESETN_SET (_PRCMU_BASE + 0x1E4)
-#define PRCM_APE_RESETN_CLR (_PRCMU_BASE + 0x1E8)
-
-/* ePOD and memory power signal control registers */
-#define PRCM_EPOD_C_SET (_PRCMU_BASE + 0x410)
-#define PRCM_SRAM_LS_SLEEP (_PRCMU_BASE + 0x304)
-
-/* Debug power control unit registers */
-#define PRCM_POWER_STATE_SET (_PRCMU_BASE + 0x254)
-
-/* Miscellaneous unit registers */
-#define PRCM_DSI_SW_RESET (_PRCMU_BASE + 0x324)
-
-#endif /* __MACH_PRCMU_REGS_H */
diff --git a/arch/arm/mach-ux500/include/mach/prcmu.h b/arch/arm/mach-ux500/include/mach/prcmu.h
deleted file mode 100644
index c49e456..0000000
--- a/arch/arm/mach-ux500/include/mach/prcmu.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * Copyright (C) STMicroelectronics 2009
- * Copyright (C) ST-Ericsson SA 2010
- *
- * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
- * Author: Sundar Iyer <sundar.iyer@stericsson.com>
- * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
- *
- * License Terms: GNU General Public License v2
- *
- * PRCM Unit f/w API
- */
-#ifndef __MACH_PRCMU_H
-#define __MACH_PRCMU_H
-#include <mach/prcmu-defs.h>
-
-void __init prcmu_early_init(void);
-int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
-int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
-int prcmu_set_ape_opp(enum prcmu_ape_opp opp);
-int prcmu_set_cpu_opp(enum prcmu_cpu_opp opp);
-int prcmu_set_ape_cpu_opps(enum prcmu_ape_opp ape_opp,
- enum prcmu_cpu_opp cpu_opp);
-int prcmu_get_ape_opp(void);
-int prcmu_get_cpu_opp(void);
-bool prcmu_has_arm_maxopp(void);
-
-#endif /* __MACH_PRCMU_H */
diff --git a/arch/arm/mach-ux500/include/mach/smp.h b/arch/arm/mach-ux500/include/mach/smp.h
deleted file mode 100644
index ca2b15b..0000000
--- a/arch/arm/mach-ux500/include/mach/smp.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is based ARM realview platform.
- * Copyright (C) ARM Limited.
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#ifndef ASMARM_ARCH_SMP_H
-#define ASMARM_ARCH_SMP_H
-
-#include <asm/hardware/gic.h>
-
-/* This is required to wakeup the secondary core */
-extern void u8500_secondary_startup(void);
-
-/*
- * We use IRQ1 as the IPI
- */
-static inline void smp_cross_call(const struct cpumask *mask, int ipi)
-{
- gic_raise_softirq(mask, ipi);
-}
-#endif
diff --git a/arch/arm/mach-ux500/include/mach/uncompress.h b/arch/arm/mach-ux500/include/mach/uncompress.h
index ab0fe14..088b550 100644
--- a/arch/arm/mach-ux500/include/mach/uncompress.h
+++ b/arch/arm/mach-ux500/include/mach/uncompress.h
@@ -24,7 +24,7 @@
#include <linux/amba/serial.h>
#include <mach/hardware.h>
-static u32 ux500_uart_base;
+u32 ux500_uart_base;
static void putc(const char c)
{
diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c
index 4fff4d4..0c527fe 100644
--- a/arch/arm/mach-ux500/platsmp.c
+++ b/arch/arm/mach-ux500/platsmp.c
@@ -18,10 +18,14 @@
#include <linux/io.h>
#include <asm/cacheflush.h>
+#include <asm/hardware/gic.h>
#include <asm/smp_scu.h>
#include <mach/hardware.h>
#include <mach/setup.h>
+/* This is called from headsmp.S to wakeup the secondary core */
+extern void u8500_secondary_startup(void);
+
/*
* control for which core is the next to come out of the secondary
* boot "holding pen"
@@ -94,7 +98,7 @@
*/
write_pen_release(cpu);
- smp_cross_call(cpumask_of(cpu), 1);
+ gic_raise_softirq(cpumask_of(cpu), 1);
timeout = jiffies + (1 * HZ);
while (time_before(jiffies, timeout)) {
@@ -162,6 +166,8 @@
for (i = 0; i < ncores; i++)
set_cpu_possible(i, true);
+
+ set_smp_cross_call(gic_raise_softirq);
}
void __init platform_smp_prepare_cpus(unsigned int max_cpus)
diff --git a/arch/arm/mach-ux500/prcmu.c b/arch/arm/mach-ux500/prcmu.c
deleted file mode 100644
index c522d26..0000000
--- a/arch/arm/mach-ux500/prcmu.c
+++ /dev/null
@@ -1,394 +0,0 @@
-/*
- * Copyright (C) STMicroelectronics 2009
- * Copyright (C) ST-Ericsson SA 2010
- *
- * License Terms: GNU General Public License v2
- * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
- * Author: Sundar Iyer <sundar.iyer@stericsson.com>
- * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
- *
- * U8500 PRCM Unit interface driver
- *
- */
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/io.h>
-#include <linux/mutex.h>
-#include <linux/completion.h>
-#include <linux/jiffies.h>
-#include <linux/bitops.h>
-#include <linux/interrupt.h>
-
-#include <mach/hardware.h>
-#include <mach/prcmu-regs.h>
-#include <mach/prcmu-defs.h>
-
-/* Global var to runtime determine TCDM base for v2 or v1 */
-static __iomem void *tcdm_base;
-
-#define _MBOX_HEADER (tcdm_base + 0xFE8)
-#define MBOX_HEADER_REQ_MB0 (_MBOX_HEADER + 0x0)
-
-#define REQ_MB1 (tcdm_base + 0xFD0)
-#define REQ_MB5 (tcdm_base + 0xE44)
-
-#define REQ_MB1_ARMOPP (REQ_MB1 + 0x0)
-#define REQ_MB1_APEOPP (REQ_MB1 + 0x1)
-#define REQ_MB1_BOOSTOPP (REQ_MB1 + 0x2)
-
-#define ACK_MB1 (tcdm_base + 0xE04)
-#define ACK_MB5 (tcdm_base + 0xDF4)
-
-#define ACK_MB1_CURR_ARMOPP (ACK_MB1 + 0x0)
-#define ACK_MB1_CURR_APEOPP (ACK_MB1 + 0x1)
-
-#define REQ_MB5_I2C_SLAVE_OP (REQ_MB5)
-#define REQ_MB5_I2C_HW_BITS (REQ_MB5 + 1)
-#define REQ_MB5_I2C_REG (REQ_MB5 + 2)
-#define REQ_MB5_I2C_VAL (REQ_MB5 + 3)
-
-#define ACK_MB5_I2C_STATUS (ACK_MB5 + 1)
-#define ACK_MB5_I2C_VAL (ACK_MB5 + 3)
-
-#define PRCM_AVS_VARM_MAX_OPP (tcdm_base + 0x2E4)
-#define PRCM_AVS_ISMODEENABLE 7
-#define PRCM_AVS_ISMODEENABLE_MASK (1 << PRCM_AVS_ISMODEENABLE)
-
-#define I2C_WRITE(slave) \
- (((slave) << 1) | (cpu_is_u8500v2() ? BIT(6) : 0))
-#define I2C_READ(slave) \
- (((slave) << 1) | (cpu_is_u8500v2() ? BIT(6) : 0) | BIT(0))
-#define I2C_STOP_EN BIT(3)
-
-enum mb1_h {
- MB1H_ARM_OPP = 1,
- MB1H_APE_OPP,
- MB1H_ARM_APE_OPP,
-};
-
-static struct {
- struct mutex lock;
- struct completion work;
- struct {
- u8 arm_opp;
- u8 ape_opp;
- u8 arm_status;
- u8 ape_status;
- } ack;
-} mb1_transfer;
-
-enum ack_mb5_status {
- I2C_WR_OK = 0x01,
- I2C_RD_OK = 0x02,
-};
-
-#define MBOX_BIT BIT
-#define NUM_MBOX 8
-
-static struct {
- struct mutex lock;
- struct completion work;
- bool failed;
- struct {
- u8 status;
- u8 value;
- } ack;
-} mb5_transfer;
-
-/**
- * prcmu_abb_read() - Read register value(s) from the ABB.
- * @slave: The I2C slave address.
- * @reg: The (start) register address.
- * @value: The read out value(s).
- * @size: The number of registers to read.
- *
- * Reads register value(s) from the ABB.
- * @size has to be 1 for the current firmware version.
- */
-int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
-{
- int r;
-
- if (size != 1)
- return -EINVAL;
-
- r = mutex_lock_interruptible(&mb5_transfer.lock);
- if (r)
- return r;
-
- while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
- cpu_relax();
-
- writeb(I2C_READ(slave), REQ_MB5_I2C_SLAVE_OP);
- writeb(I2C_STOP_EN, REQ_MB5_I2C_HW_BITS);
- writeb(reg, REQ_MB5_I2C_REG);
-
- writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
- if (!wait_for_completion_timeout(&mb5_transfer.work,
- msecs_to_jiffies(500))) {
- pr_err("prcmu: prcmu_abb_read timed out.\n");
- r = -EIO;
- goto unlock_and_return;
- }
- r = ((mb5_transfer.ack.status == I2C_RD_OK) ? 0 : -EIO);
- if (!r)
- *value = mb5_transfer.ack.value;
-
-unlock_and_return:
- mutex_unlock(&mb5_transfer.lock);
- return r;
-}
-EXPORT_SYMBOL(prcmu_abb_read);
-
-/**
- * prcmu_abb_write() - Write register value(s) to the ABB.
- * @slave: The I2C slave address.
- * @reg: The (start) register address.
- * @value: The value(s) to write.
- * @size: The number of registers to write.
- *
- * Reads register value(s) from the ABB.
- * @size has to be 1 for the current firmware version.
- */
-int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
-{
- int r;
-
- if (size != 1)
- return -EINVAL;
-
- r = mutex_lock_interruptible(&mb5_transfer.lock);
- if (r)
- return r;
-
-
- while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
- cpu_relax();
-
- writeb(I2C_WRITE(slave), REQ_MB5_I2C_SLAVE_OP);
- writeb(I2C_STOP_EN, REQ_MB5_I2C_HW_BITS);
- writeb(reg, REQ_MB5_I2C_REG);
- writeb(*value, REQ_MB5_I2C_VAL);
-
- writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
- if (!wait_for_completion_timeout(&mb5_transfer.work,
- msecs_to_jiffies(500))) {
- pr_err("prcmu: prcmu_abb_write timed out.\n");
- r = -EIO;
- goto unlock_and_return;
- }
- r = ((mb5_transfer.ack.status == I2C_WR_OK) ? 0 : -EIO);
-
-unlock_and_return:
- mutex_unlock(&mb5_transfer.lock);
- return r;
-}
-EXPORT_SYMBOL(prcmu_abb_write);
-
-static int set_ape_cpu_opps(u8 header, enum prcmu_ape_opp ape_opp,
- enum prcmu_cpu_opp cpu_opp)
-{
- bool do_ape;
- bool do_arm;
- int err = 0;
-
- do_ape = ((header == MB1H_APE_OPP) || (header == MB1H_ARM_APE_OPP));
- do_arm = ((header == MB1H_ARM_OPP) || (header == MB1H_ARM_APE_OPP));
-
- mutex_lock(&mb1_transfer.lock);
-
- while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
- cpu_relax();
-
- writeb(0, MBOX_HEADER_REQ_MB0);
- writeb(cpu_opp, REQ_MB1_ARMOPP);
- writeb(ape_opp, REQ_MB1_APEOPP);
- writeb(0, REQ_MB1_BOOSTOPP);
- writel(MBOX_BIT(1), PRCM_MBOX_CPU_SET);
- wait_for_completion(&mb1_transfer.work);
- if ((do_ape) && (mb1_transfer.ack.ape_status != 0))
- err = -EIO;
- if ((do_arm) && (mb1_transfer.ack.arm_status != 0))
- err = -EIO;
-
- mutex_unlock(&mb1_transfer.lock);
-
- return err;
-}
-
-/**
- * prcmu_set_ape_opp() - Set the OPP of the APE.
- * @opp: The OPP to set.
- *
- * This function sets the OPP of the APE.
- */
-int prcmu_set_ape_opp(enum prcmu_ape_opp opp)
-{
- return set_ape_cpu_opps(MB1H_APE_OPP, opp, APE_OPP_NO_CHANGE);
-}
-EXPORT_SYMBOL(prcmu_set_ape_opp);
-
-/**
- * prcmu_set_cpu_opp() - Set the OPP of the CPU.
- * @opp: The OPP to set.
- *
- * This function sets the OPP of the CPU.
- */
-int prcmu_set_cpu_opp(enum prcmu_cpu_opp opp)
-{
- return set_ape_cpu_opps(MB1H_ARM_OPP, CPU_OPP_NO_CHANGE, opp);
-}
-EXPORT_SYMBOL(prcmu_set_cpu_opp);
-
-/**
- * prcmu_set_ape_cpu_opps() - Set the OPPs of the APE and the CPU.
- * @ape_opp: The APE OPP to set.
- * @cpu_opp: The CPU OPP to set.
- *
- * This function sets the OPPs of the APE and the CPU.
- */
-int prcmu_set_ape_cpu_opps(enum prcmu_ape_opp ape_opp,
- enum prcmu_cpu_opp cpu_opp)
-{
- return set_ape_cpu_opps(MB1H_ARM_APE_OPP, ape_opp, cpu_opp);
-}
-EXPORT_SYMBOL(prcmu_set_ape_cpu_opps);
-
-/**
- * prcmu_get_ape_opp() - Get the OPP of the APE.
- *
- * This function gets the OPP of the APE.
- */
-enum prcmu_ape_opp prcmu_get_ape_opp(void)
-{
- return readb(ACK_MB1_CURR_APEOPP);
-}
-EXPORT_SYMBOL(prcmu_get_ape_opp);
-
-/**
- * prcmu_get_cpu_opp() - Get the OPP of the CPU.
- *
- * This function gets the OPP of the CPU. The OPP is specified in %%.
- * PRCMU_OPP_EXT is a special OPP value, not specified in %%.
- */
-int prcmu_get_cpu_opp(void)
-{
- return readb(ACK_MB1_CURR_ARMOPP);
-}
-EXPORT_SYMBOL(prcmu_get_cpu_opp);
-
-bool prcmu_has_arm_maxopp(void)
-{
- return (readb(PRCM_AVS_VARM_MAX_OPP) & PRCM_AVS_ISMODEENABLE_MASK)
- == PRCM_AVS_ISMODEENABLE_MASK;
-}
-
-static void read_mailbox_0(void)
-{
- writel(MBOX_BIT(0), PRCM_ARM_IT1_CLEAR);
-}
-
-static void read_mailbox_1(void)
-{
- mb1_transfer.ack.arm_opp = readb(ACK_MB1_CURR_ARMOPP);
- mb1_transfer.ack.ape_opp = readb(ACK_MB1_CURR_APEOPP);
- complete(&mb1_transfer.work);
- writel(MBOX_BIT(1), PRCM_ARM_IT1_CLEAR);
-}
-
-static void read_mailbox_2(void)
-{
- writel(MBOX_BIT(2), PRCM_ARM_IT1_CLEAR);
-}
-
-static void read_mailbox_3(void)
-{
- writel(MBOX_BIT(3), PRCM_ARM_IT1_CLEAR);
-}
-
-static void read_mailbox_4(void)
-{
- writel(MBOX_BIT(4), PRCM_ARM_IT1_CLEAR);
-}
-
-static void read_mailbox_5(void)
-{
- mb5_transfer.ack.status = readb(ACK_MB5_I2C_STATUS);
- mb5_transfer.ack.value = readb(ACK_MB5_I2C_VAL);
- complete(&mb5_transfer.work);
- writel(MBOX_BIT(5), PRCM_ARM_IT1_CLEAR);
-}
-
-static void read_mailbox_6(void)
-{
- writel(MBOX_BIT(6), PRCM_ARM_IT1_CLEAR);
-}
-
-static void read_mailbox_7(void)
-{
- writel(MBOX_BIT(7), PRCM_ARM_IT1_CLEAR);
-}
-
-static void (* const read_mailbox[NUM_MBOX])(void) = {
- read_mailbox_0,
- read_mailbox_1,
- read_mailbox_2,
- read_mailbox_3,
- read_mailbox_4,
- read_mailbox_5,
- read_mailbox_6,
- read_mailbox_7
-};
-
-static irqreturn_t prcmu_irq_handler(int irq, void *data)
-{
- u32 bits;
- u8 n;
-
- bits = (readl(PRCM_ARM_IT1_VAL) & (MBOX_BIT(NUM_MBOX) - 1));
- if (unlikely(!bits))
- return IRQ_NONE;
-
- for (n = 0; bits; n++) {
- if (bits & MBOX_BIT(n)) {
- bits -= MBOX_BIT(n);
- read_mailbox[n]();
- }
- }
- return IRQ_HANDLED;
-}
-
-void __init prcmu_early_init(void)
-{
- if (cpu_is_u8500v11() || cpu_is_u8500ed()) {
- tcdm_base = __io_address(U8500_PRCMU_TCDM_BASE_V1);
- } else if (cpu_is_u8500v2()) {
- tcdm_base = __io_address(U8500_PRCMU_TCDM_BASE);
- } else {
- pr_err("prcmu: Unsupported chip version\n");
- BUG();
- }
-}
-
-static int __init prcmu_init(void)
-{
- if (cpu_is_u8500ed()) {
- pr_err("prcmu: Unsupported chip version\n");
- return 0;
- }
-
- mutex_init(&mb1_transfer.lock);
- init_completion(&mb1_transfer.work);
- mutex_init(&mb5_transfer.lock);
- init_completion(&mb5_transfer.work);
-
- /* Clean up the mailbox interrupts after pre-kernel code. */
- writel((MBOX_BIT(NUM_MBOX) - 1), PRCM_ARM_IT1_CLEAR);
-
- return request_irq(IRQ_DB8500_PRCMU1, prcmu_irq_handler, 0,
- "prcmu", NULL);
-}
-
-arch_initcall(prcmu_init);
diff --git a/arch/arm/mach-versatile/core.c b/arch/arm/mach-versatile/core.c
index eb7ffa0..0c99cf0 100644
--- a/arch/arm/mach-versatile/core.c
+++ b/arch/arm/mach-versatile/core.c
@@ -32,6 +32,7 @@
#include <linux/io.h>
#include <linux/gfp.h>
#include <linux/clkdev.h>
+#include <linux/mtd/physmap.h>
#include <asm/system.h>
#include <asm/irq.h>
@@ -42,7 +43,6 @@
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
-#include <asm/mach/flash.h>
#include <asm/mach/irq.h>
#include <asm/mach/time.h>
#include <asm/mach/map.h>
@@ -190,27 +190,7 @@
#define VERSATILE_FLASHCTRL (__io_address(VERSATILE_SYS_BASE) + VERSATILE_SYS_FLASH_OFFSET)
-static int versatile_flash_init(void)
-{
- u32 val;
-
- val = __raw_readl(VERSATILE_FLASHCTRL);
- val &= ~VERSATILE_FLASHPROG_FLVPPEN;
- __raw_writel(val, VERSATILE_FLASHCTRL);
-
- return 0;
-}
-
-static void versatile_flash_exit(void)
-{
- u32 val;
-
- val = __raw_readl(VERSATILE_FLASHCTRL);
- val &= ~VERSATILE_FLASHPROG_FLVPPEN;
- __raw_writel(val, VERSATILE_FLASHCTRL);
-}
-
-static void versatile_flash_set_vpp(int on)
+static void versatile_flash_set_vpp(struct platform_device *pdev, int on)
{
u32 val;
@@ -222,11 +202,8 @@
__raw_writel(val, VERSATILE_FLASHCTRL);
}
-static struct flash_platform_data versatile_flash_data = {
- .map_name = "cfi_probe",
+static struct physmap_flash_data versatile_flash_data = {
.width = 4,
- .init = versatile_flash_init,
- .exit = versatile_flash_exit,
.set_vpp = versatile_flash_set_vpp,
};
@@ -237,7 +214,7 @@
};
static struct platform_device versatile_flash_device = {
- .name = "armflash",
+ .name = "physmap-flash",
.id = 0,
.dev = {
.platform_data = &versatile_flash_data,
@@ -375,6 +352,10 @@
.rate = 24000000,
};
+static struct clk sp804_clk = {
+ .rate = 1000000,
+};
+
static struct clk dummy_apb_pclk;
static struct clk_lookup lookups[] = {
@@ -411,7 +392,10 @@
}, { /* CLCD */
.dev_id = "dev:20",
.clk = &osc4_clk,
- }
+ }, { /* SP804 timers */
+ .dev_id = "sp804",
+ .clk = &sp804_clk,
+ },
};
/*
@@ -764,8 +748,8 @@
writel(0, TIMER2_VA_BASE + TIMER_CTRL);
writel(0, TIMER3_VA_BASE + TIMER_CTRL);
- sp804_clocksource_init(TIMER3_VA_BASE);
- sp804_clockevents_init(TIMER0_VA_BASE, IRQ_TIMERINT0_1);
+ sp804_clocksource_init(TIMER3_VA_BASE, "timer3");
+ sp804_clockevents_init(TIMER0_VA_BASE, IRQ_TIMERINT0_1, "timer0");
}
struct sys_timer versatile_timer = {
diff --git a/arch/arm/mach-vexpress/ct-ca9x4.c b/arch/arm/mach-vexpress/ct-ca9x4.c
index ebc22e7..765a71f 100644
--- a/arch/arm/mach-vexpress/ct-ca9x4.c
+++ b/arch/arm/mach-vexpress/ct-ca9x4.c
@@ -71,8 +71,9 @@
writel(0, MMIO_P2V(CT_CA9X4_TIMER0) + TIMER_CTRL);
writel(0, MMIO_P2V(CT_CA9X4_TIMER1) + TIMER_CTRL);
- sp804_clocksource_init(MMIO_P2V(CT_CA9X4_TIMER1));
- sp804_clockevents_init(MMIO_P2V(CT_CA9X4_TIMER0), IRQ_CT_CA9X4_TIMER0);
+ sp804_clocksource_init(MMIO_P2V(CT_CA9X4_TIMER1), "ct-timer1");
+ sp804_clockevents_init(MMIO_P2V(CT_CA9X4_TIMER0), IRQ_CT_CA9X4_TIMER0,
+ "ct-timer0");
}
static struct sys_timer ct_ca9x4_timer = {
@@ -141,10 +142,22 @@
.rate = 24000000,
};
+static struct clk ct_sp804_clk = {
+ .rate = 1000000,
+};
+
static struct clk_lookup lookups[] = {
{ /* CLCD */
.dev_id = "ct:clcd",
.clk = &osc1_clk,
+ }, { /* SP804 timers */
+ .dev_id = "sp804",
+ .con_id = "ct-timer0",
+ .clk = &ct_sp804_clk,
+ }, { /* SP804 timers */
+ .dev_id = "sp804",
+ .con_id = "ct-timer1",
+ .clk = &ct_sp804_clk,
},
};
@@ -210,6 +223,8 @@
for (i = 0; i < ncores; ++i)
set_cpu_possible(i, true);
+
+ set_smp_cross_call(gic_raise_softirq);
}
static void ct_ca9x4_smp_enable(unsigned int max_cpus)
diff --git a/arch/arm/mach-vexpress/include/mach/smp.h b/arch/arm/mach-vexpress/include/mach/smp.h
deleted file mode 100644
index 4c05e4a..0000000
--- a/arch/arm/mach-vexpress/include/mach/smp.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef __MACH_SMP_H
-#define __MACH_SMP_H
-
-#include <asm/hardware/gic.h>
-
-/*
- * We use IRQ1 as the IPI
- */
-static inline void smp_cross_call(const struct cpumask *mask, int ipi)
-{
- gic_raise_softirq(mask, ipi);
-}
-#endif
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index ba46e8e..285edcd 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -13,11 +13,11 @@
#include <linux/sysdev.h>
#include <linux/usb/isp1760.h>
#include <linux/clkdev.h>
+#include <linux/mtd/physmap.h>
#include <asm/mach-types.h>
#include <asm/sizes.h>
#include <asm/mach/arch.h>
-#include <asm/mach/flash.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include <asm/hardware/arm_timer.h>
@@ -65,8 +65,9 @@
writel(0, MMIO_P2V(V2M_TIMER0) + TIMER_CTRL);
writel(0, MMIO_P2V(V2M_TIMER1) + TIMER_CTRL);
- sp804_clocksource_init(MMIO_P2V(V2M_TIMER1));
- sp804_clockevents_init(MMIO_P2V(V2M_TIMER0), IRQ_V2M_TIMER0);
+ sp804_clocksource_init(MMIO_P2V(V2M_TIMER1), "v2m-timer1");
+ sp804_clockevents_init(MMIO_P2V(V2M_TIMER0), IRQ_V2M_TIMER0,
+ "v2m-timer0");
}
static struct sys_timer v2m_timer = {
@@ -206,27 +207,13 @@
.dev.platform_data = &v2m_usb_config,
};
-static int v2m_flash_init(void)
-{
- writel(0, MMIO_P2V(V2M_SYS_FLASH));
- return 0;
-}
-
-static void v2m_flash_exit(void)
-{
- writel(0, MMIO_P2V(V2M_SYS_FLASH));
-}
-
-static void v2m_flash_set_vpp(int on)
+static void v2m_flash_set_vpp(struct platform_device *pdev, int on)
{
writel(on != 0, MMIO_P2V(V2M_SYS_FLASH));
}
-static struct flash_platform_data v2m_flash_data = {
- .map_name = "cfi_probe",
+static struct physmap_flash_data v2m_flash_data = {
.width = 4,
- .init = v2m_flash_init,
- .exit = v2m_flash_exit,
.set_vpp = v2m_flash_set_vpp,
};
@@ -243,7 +230,7 @@
};
static struct platform_device v2m_flash_device = {
- .name = "armflash",
+ .name = "physmap-flash",
.id = -1,
.resource = v2m_flash_resources,
.num_resources = ARRAY_SIZE(v2m_flash_resources),
@@ -333,6 +320,10 @@
.rate = 24000000,
};
+static struct clk v2m_sp804_clk = {
+ .rate = 1000000,
+};
+
static struct clk dummy_apb_pclk;
static struct clk_lookup v2m_lookups[] = {
@@ -363,6 +354,14 @@
}, { /* CLCD */
.dev_id = "mb:clcd",
.clk = &osc1_clk,
+ }, { /* SP804 timers */
+ .dev_id = "sp804",
+ .con_id = "v2m-timer0",
+ .clk = &v2m_sp804_clk,
+ }, { /* SP804 timers */
+ .dev_id = "sp804",
+ .con_id = "v2m-timer1",
+ .clk = &v2m_sp804_clk,
},
};
diff --git a/arch/arm/mach-w90x900/include/mach/uncompress.h b/arch/arm/mach-w90x900/include/mach/uncompress.h
index 56f1a74..0313021 100644
--- a/arch/arm/mach-w90x900/include/mach/uncompress.h
+++ b/arch/arm/mach-w90x900/include/mach/uncompress.h
@@ -27,7 +27,7 @@
#define arch_decomp_wdog()
#define TX_DONE (UART_LSR_TEMT | UART_LSR_THRE)
-static volatile u32 * uart_base = (u32 *)UART0_PA;
+static volatile u32 * const uart_base = (u32 *)UART0_PA;
static void putc(int ch)
{
diff --git a/arch/arm/mach-w90x900/time.c b/arch/arm/mach-w90x900/time.c
index 4b089cb..a2c4e2d 100644
--- a/arch/arm/mach-w90x900/time.c
+++ b/arch/arm/mach-w90x900/time.c
@@ -43,7 +43,6 @@
#define PRESCALE 0x63 /* Divider = prescale + 1 */
#define TDR_SHIFT 24
-#define TDR_MASK ((1 << TDR_SHIFT) - 1)
static unsigned int timer0_load;
@@ -143,19 +142,6 @@
clockevents_register_device(&nuc900_clockevent_device);
}
-static cycle_t nuc900_get_cycles(struct clocksource *cs)
-{
- return (~__raw_readl(REG_TDR1)) & TDR_MASK;
-}
-
-static struct clocksource clocksource_nuc900 = {
- .name = "nuc900-timer1",
- .rating = 200,
- .read = nuc900_get_cycles,
- .mask = CLOCKSOURCE_MASK(TDR_SHIFT),
- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
static void __init nuc900_clocksource_init(void)
{
unsigned int val;
@@ -175,7 +161,8 @@
val |= (COUNTEN | PERIOD | PRESCALE);
__raw_writel(val, REG_TCSR1);
- clocksource_register_hz(&clocksource_nuc900, rate);
+ clocksource_mmio_init(REG_TDR1, "nuc900-timer1", rate, 200,
+ TDR_SHIFT, clocksource_mmio_readl_down);
}
static void __init nuc900_timer_init(void)
diff --git a/arch/arm/mm/flush.c b/arch/arm/mm/flush.c
index 2b269c9..1a8d4aa 100644
--- a/arch/arm/mm/flush.c
+++ b/arch/arm/mm/flush.c
@@ -253,8 +253,8 @@
if (!test_and_set_bit(PG_dcache_clean, &page->flags))
__flush_dcache_page(mapping, page);
- /* pte_exec() already checked above for non-aliasing VIPT cache */
- if (cache_is_vipt_nonaliasing() || pte_exec(pteval))
+
+ if (pte_exec(pteval))
__flush_icache_all();
}
#endif
@@ -275,7 +275,8 @@
* kernel cache lines for later. Otherwise, we assume we have
* aliasing mappings.
*
- * Note that we disable the lazy flush for SMP.
+ * Note that we disable the lazy flush for SMP configurations where
+ * the cache maintenance operations are not automatically broadcasted.
*/
void flush_dcache_page(struct page *page)
{
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index e591513..3f17ea1 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -85,7 +85,7 @@
struct meminfo * mi = &meminfo;
printk("Mem-info:\n");
- show_free_areas();
+ show_free_areas(filter);
for_each_bank (i, mi) {
struct membank *bank = &mi->bank[i];
@@ -201,6 +201,20 @@
}
}
+#ifdef CONFIG_ZONE_DMA
+static void __init arm_adjust_dma_zone(unsigned long *size, unsigned long *hole,
+ unsigned long dma_size)
+{
+ if (size[0] <= dma_size)
+ return;
+
+ size[ZONE_NORMAL] = size[0] - dma_size;
+ size[ZONE_DMA] = dma_size;
+ hole[ZONE_NORMAL] = hole[0];
+ hole[ZONE_DMA] = 0;
+}
+#endif
+
static void __init arm_bootmem_free(unsigned long min, unsigned long max_low,
unsigned long max_high)
{
@@ -243,11 +257,18 @@
#endif
}
+#ifdef ARM_DMA_ZONE_SIZE
+#ifndef CONFIG_ZONE_DMA
+#error ARM_DMA_ZONE_SIZE set but no DMA zone to limit allocations
+#endif
+
/*
* Adjust the sizes according to any special requirements for
* this machine type.
*/
- arch_adjust_zones(zone_size, zhole_size);
+ arm_adjust_dma_zone(zone_size, zhole_size,
+ ARM_DMA_ZONE_SIZE >> PAGE_SHIFT);
+#endif
free_area_init_node(0, zone_size, min, zhole_size);
}
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 6cf76b3..08a9236 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -31,8 +31,6 @@
#include "mm.h"
-DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
-
/*
* empty_zero_page is a special page that is used for
* zero-initialized data and COW.
diff --git a/arch/arm/mm/proc-v6.S b/arch/arm/mm/proc-v6.S
index 7c99cb4..ab17cc0 100644
--- a/arch/arm/mm/proc-v6.S
+++ b/arch/arm/mm/proc-v6.S
@@ -175,11 +175,6 @@
.asciz "ARMv6-compatible processor"
.size cpu_v6_name, . - cpu_v6_name
- .type cpu_pj4_name, #object
-cpu_pj4_name:
- .asciz "Marvell PJ4 processor"
- .size cpu_pj4_name, . - cpu_pj4_name
-
.align
__CPUINIT
@@ -305,32 +300,3 @@
.long v6_user_fns
.long v6_cache_fns
.size __v6_proc_info, . - __v6_proc_info
-
- .type __pj4_v6_proc_info, #object
-__pj4_v6_proc_info:
- .long 0x560f5810
- .long 0xff0ffff0
- ALT_SMP(.long \
- PMD_TYPE_SECT | \
- PMD_SECT_AP_WRITE | \
- PMD_SECT_AP_READ | \
- PMD_FLAGS_SMP)
- ALT_UP(.long \
- PMD_TYPE_SECT | \
- PMD_SECT_AP_WRITE | \
- PMD_SECT_AP_READ | \
- PMD_FLAGS_UP)
- .long PMD_TYPE_SECT | \
- PMD_SECT_XN | \
- PMD_SECT_AP_WRITE | \
- PMD_SECT_AP_READ
- b __v6_setup
- .long cpu_arch_name
- .long cpu_elf_name
- .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_TLS
- .long cpu_pj4_name
- .long v6_processor_functions
- .long v6wbi_tlb_fns
- .long v6_user_fns
- .long v6_cache_fns
- .size __pj4_v6_proc_info, . - __pj4_v6_proc_info
diff --git a/arch/arm/plat-mxc/Kconfig b/arch/arm/plat-mxc/Kconfig
index b0cb425..a5353fc 100644
--- a/arch/arm/plat-mxc/Kconfig
+++ b/arch/arm/plat-mxc/Kconfig
@@ -4,13 +4,18 @@
menu "Freescale MXC Implementations"
+config ARCH_MX50_SUPPORTED
+ bool
+
+config ARCH_MX53_SUPPORTED
+ bool
+
choice
prompt "Freescale CPU family:"
default ARCH_MX3
config ARCH_MX1
bool "MX1-based"
- select SOC_IMX1
help
This enables support for systems based on the Freescale i.MX1 family
@@ -26,29 +31,26 @@
config ARCH_MX3
bool "MX3-based"
- select CPU_V6
help
This enables support for systems based on the Freescale i.MX3 family
-config ARCH_MXC91231
- bool "MXC91231-based"
- select CPU_V6
- select MXC_AVIC
+config ARCH_MX503
+ bool "i.MX50 + i.MX53"
+ select ARCH_MX50_SUPPORTED
+ select ARCH_MX53_SUPPORTED
help
- This enables support for systems based on the Freescale MXC91231 family
+ This enables support for machines using Freescale's i.MX50 and i.MX51
+ processors.
-config ARCH_MX5
- bool "MX5-based"
- select CPU_V7
- select ARM_L1_CACHE_SHIFT_6
+config ARCH_MX51
+ bool "i.MX51"
+ select ARCH_MX51_SUPPORTED
help
This enables support for systems based on the Freescale i.MX51 family
endchoice
source "arch/arm/mach-imx/Kconfig"
-source "arch/arm/mach-mx3/Kconfig"
-source "arch/arm/mach-mxc91231/Kconfig"
source "arch/arm/mach-mx5/Kconfig"
endmenu
diff --git a/arch/arm/plat-mxc/devices/Kconfig b/arch/arm/plat-mxc/devices/Kconfig
index b9ab1d5..bd294ad 100644
--- a/arch/arm/plat-mxc/devices/Kconfig
+++ b/arch/arm/plat-mxc/devices/Kconfig
@@ -24,7 +24,6 @@
config IMX_HAVE_PLATFORM_IMX_FB
bool
- select HAVE_FB_IMX
config IMX_HAVE_PLATFORM_IMX_I2C
bool
@@ -41,6 +40,9 @@
config IMX_HAVE_PLATFORM_IMX_UDC
bool
+config IMX_HAVE_PLATFORM_IPU_CORE
+ bool
+
config IMX_HAVE_PLATFORM_MX1_CAMERA
bool
@@ -63,6 +65,9 @@
bool
select ARCH_HAS_RNGA
+config IMX_HAVE_PLATFORM_MXC_RTC
+ bool
+
config IMX_HAVE_PLATFORM_MXC_W1
bool
diff --git a/arch/arm/plat-mxc/devices/Makefile b/arch/arm/plat-mxc/devices/Makefile
index 75cd2ec..ad2922a 100644
--- a/arch/arm/plat-mxc/devices/Makefile
+++ b/arch/arm/plat-mxc/devices/Makefile
@@ -12,6 +12,7 @@
obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_SSI) += platform-imx-ssi.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UART) += platform-imx-uart.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_IMX_UDC) += platform-imx_udc.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_IPU_CORE) += platform-ipu-core.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_MX1_CAMERA) += platform-mx1-camera.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_MX2_CAMERA) += platform-mx2-camera.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_EHCI) += platform-mxc-ehci.o
@@ -19,6 +20,7 @@
obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_NAND) += platform-mxc_nand.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_PWM) += platform-mxc_pwm.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RNGA) += platform-mxc_rnga.o
+obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RTC) += platform-mxc_rtc.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_W1) += platform-mxc_w1.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX) += platform-sdhci-esdhc-imx.o
obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) += platform-spi_imx.o
diff --git a/arch/arm/plat-mxc/devices/platform-ipu-core.c b/arch/arm/plat-mxc/devices/platform-ipu-core.c
new file mode 100644
index 0000000..edf6503
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-ipu-core.c
@@ -0,0 +1,129 @@
+/*
+ * Copyright (C) 2011 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/hardware.h>
+#include <mach/devices-common.h>
+
+#define imx_ipu_core_entry_single(soc) \
+{ \
+ .iobase = soc ## _IPU_CTRL_BASE_ADDR, \
+ .synirq = soc ## _INT_IPU_SYN, \
+ .errirq = soc ## _INT_IPU_ERR, \
+}
+
+#ifdef CONFIG_SOC_IMX31
+const struct imx_ipu_core_data imx31_ipu_core_data __initconst =
+ imx_ipu_core_entry_single(MX31);
+#endif
+
+#ifdef CONFIG_SOC_IMX35
+const struct imx_ipu_core_data imx35_ipu_core_data __initconst =
+ imx_ipu_core_entry_single(MX35);
+#endif
+
+static struct platform_device *imx_ipu_coredev __initdata;
+
+struct platform_device *__init imx_add_ipu_core(
+ const struct imx_ipu_core_data *data,
+ const struct ipu_platform_data *pdata)
+{
+ /* The resource order is important! */
+ struct resource res[] = {
+ {
+ .start = data->iobase,
+ .end = data->iobase + 0x5f,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = data->iobase + 0x88,
+ .end = data->iobase + 0xb3,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = data->synirq,
+ .end = data->synirq,
+ .flags = IORESOURCE_IRQ,
+ }, {
+ .start = data->errirq,
+ .end = data->errirq,
+ .flags = IORESOURCE_IRQ,
+ },
+ };
+
+ return imx_ipu_coredev = imx_add_platform_device("ipu-core", -1,
+ res, ARRAY_SIZE(res), pdata, sizeof(*pdata));
+}
+
+struct platform_device *__init imx_alloc_mx3_camera(
+ const struct imx_ipu_core_data *data,
+ const struct mx3_camera_pdata *pdata)
+{
+ struct resource res[] = {
+ {
+ .start = data->iobase + 0x60,
+ .end = data->iobase + 0x87,
+ .flags = IORESOURCE_MEM,
+ },
+ };
+ int ret = -ENOMEM;
+ struct platform_device *pdev;
+
+ if (IS_ERR_OR_NULL(imx_ipu_coredev))
+ return ERR_PTR(-ENODEV);
+
+ pdev = platform_device_alloc("mx3-camera", 0);
+ if (!pdev)
+ goto err;
+
+ pdev->dev.dma_mask = kmalloc(sizeof(*pdev->dev.dma_mask), GFP_KERNEL);
+ if (!pdev->dev.dma_mask)
+ goto err;
+
+ *pdev->dev.dma_mask = DMA_BIT_MASK(32);
+ pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
+
+ ret = platform_device_add_resources(pdev, res, ARRAY_SIZE(res));
+ if (ret)
+ goto err;
+
+ if (pdata) {
+ struct mx3_camera_pdata *copied_pdata;
+
+ ret = platform_device_add_data(pdev, pdata, sizeof(*pdata));
+ if (ret) {
+err:
+ kfree(pdev->dev.dma_mask);
+ platform_device_put(pdev);
+ return ERR_PTR(-ENODEV);
+ }
+ copied_pdata = dev_get_platdata(&pdev->dev);
+ copied_pdata->dma_dev = &imx_ipu_coredev->dev;
+ }
+
+ return pdev;
+}
+
+struct platform_device *__init imx_add_mx3_sdc_fb(
+ const struct imx_ipu_core_data *data,
+ struct mx3fb_platform_data *pdata)
+{
+ struct resource res[] = {
+ {
+ .start = data->iobase + 0xb4,
+ .end = data->iobase + 0x1bf,
+ .flags = IORESOURCE_MEM,
+ },
+ };
+
+ if (IS_ERR_OR_NULL(imx_ipu_coredev))
+ return ERR_PTR(-ENODEV);
+
+ pdata->dma_dev = &imx_ipu_coredev->dev;
+
+ return imx_add_platform_device_dmamask("mx3_sdc_fb", -1,
+ res, ARRAY_SIZE(res), pdata, sizeof(*pdata),
+ DMA_BIT_MASK(32));
+}
diff --git a/arch/arm/plat-mxc/devices/platform-mxc_rtc.c b/arch/arm/plat-mxc/devices/platform-mxc_rtc.c
new file mode 100644
index 0000000..16d0ec4
--- /dev/null
+++ b/arch/arm/plat-mxc/devices/platform-mxc_rtc.c
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2010-2011 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <mach/hardware.h>
+#include <mach/devices-common.h>
+
+#define imx_mxc_rtc_data_entry_single(soc) \
+ { \
+ .iobase = soc ## _RTC_BASE_ADDR, \
+ .irq = soc ## _INT_RTC, \
+ }
+
+#ifdef CONFIG_SOC_IMX31
+const struct imx_mxc_rtc_data imx31_mxc_rtc_data __initconst =
+ imx_mxc_rtc_data_entry_single(MX31);
+#endif /* ifdef CONFIG_SOC_IMX31 */
+
+struct platform_device *__init imx_add_mxc_rtc(
+ const struct imx_mxc_rtc_data *data)
+{
+ struct resource res[] = {
+ {
+ .start = data->iobase,
+ .end = data->iobase + SZ_16K - 1,
+ .flags = IORESOURCE_MEM,
+ }, {
+ .start = data->irq,
+ .end = data->irq,
+ .flags = IORESOURCE_IRQ,
+ },
+ };
+
+ return imx_add_platform_device("mxc_rtc", -1,
+ res, ARRAY_SIZE(res), NULL, 0);
+}
diff --git a/arch/arm/plat-mxc/devices/platform-spi_imx.c b/arch/arm/plat-mxc/devices/platform-spi_imx.c
index f4a60ab..f97eb36 100644
--- a/arch/arm/plat-mxc/devices/platform-spi_imx.c
+++ b/arch/arm/plat-mxc/devices/platform-spi_imx.c
@@ -80,7 +80,7 @@
#ifdef CONFIG_SOC_IMX51
const struct imx_spi_imx_data imx51_cspi_data __initconst =
- imx_spi_imx_data_entry_single(MX51, CSPI, "imx51-cspi", 0, , SZ_4K);
+ imx_spi_imx_data_entry_single(MX51, CSPI, "imx51-cspi", 2, , SZ_4K);
const struct imx_spi_imx_data imx51_ecspi_data[] __initconst = {
#define imx51_ecspi_data_entry(_id, _hwid) \
diff --git a/arch/arm/plat-mxc/epit.c b/arch/arm/plat-mxc/epit.c
index d69d343..d3467f8 100644
--- a/arch/arm/plat-mxc/epit.c
+++ b/arch/arm/plat-mxc/epit.c
@@ -83,26 +83,12 @@
__raw_writel(EPITSR_OCIF, timer_base + EPITSR);
}
-static cycle_t epit_read(struct clocksource *cs)
-{
- return 0 - __raw_readl(timer_base + EPITCNR);
-}
-
-static struct clocksource clocksource_epit = {
- .name = "epit",
- .rating = 200,
- .read = epit_read,
- .mask = CLOCKSOURCE_MASK(32),
- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
static int __init epit_clocksource_init(struct clk *timer_clk)
{
unsigned int c = clk_get_rate(timer_clk);
- clocksource_register_hz(&clocksource_epit, c);
-
- return 0;
+ return clocksource_mmio_init(timer_base + EPITCNR, "epit", c, 200, 32,
+ clocksource_mmio_readl_down);
}
/* clock event */
diff --git a/arch/arm/plat-mxc/include/mach/common.h b/arch/arm/plat-mxc/include/mach/common.h
index a22ebe1..da79918 100644
--- a/arch/arm/plat-mxc/include/mach/common.h
+++ b/arch/arm/plat-mxc/include/mach/common.h
@@ -23,7 +23,6 @@
extern void mx50_map_io(void);
extern void mx51_map_io(void);
extern void mx53_map_io(void);
-extern void mxc91231_map_io(void);
extern void imx1_init_early(void);
extern void imx21_init_early(void);
extern void imx25_init_early(void);
@@ -33,7 +32,6 @@
extern void imx50_init_early(void);
extern void imx51_init_early(void);
extern void imx53_init_early(void);
-extern void mxc91231_init_early(void);
extern void mxc_init_irq(void __iomem *);
extern void tzic_init_irq(void __iomem *);
extern void mx1_init_irq(void);
@@ -45,7 +43,6 @@
extern void mx50_init_irq(void);
extern void mx51_init_irq(void);
extern void mx53_init_irq(void);
-extern void mxc91231_init_irq(void);
extern void epit_timer_init(struct clk *timer_clk, void __iomem *base, int irq);
extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int);
extern int mx1_clocks_init(unsigned long fref);
@@ -58,14 +55,11 @@
unsigned long ckih1, unsigned long ckih2);
extern int mx53_clocks_init(unsigned long ckil, unsigned long osc,
unsigned long ckih1, unsigned long ckih2);
-extern int mxc91231_clocks_init(unsigned long fref);
extern int mxc_register_gpios(void);
extern int mxc_register_device(struct platform_device *pdev, void *data);
extern void mxc_set_cpu_type(unsigned int type);
extern void mxc_arch_reset_init(void __iomem *);
-extern void mxc91231_power_off(void);
-extern void mxc91231_arch_reset(int, const char *);
-extern void mxc91231_prepare_idle(void);
extern void mx51_efikamx_reset(void);
extern int mx53_revision(void);
+extern int mx53_display_revision(void);
#endif
diff --git a/arch/arm/plat-mxc/include/mach/debug-macro.S b/arch/arm/plat-mxc/include/mach/debug-macro.S
index 3b3a37c..8e8d175 100644
--- a/arch/arm/plat-mxc/include/mach/debug-macro.S
+++ b/arch/arm/plat-mxc/include/mach/debug-macro.S
@@ -44,13 +44,6 @@
#define UART_PADDR MX51_UART1_BASE_ADDR
#endif
-#ifdef CONFIG_ARCH_MXC91231
-#ifdef UART_PADDR
-#error "CONFIG_DEBUG_LL is incompatible with multiple archs"
-#endif
-#define UART_PADDR MXC91231_UART2_BASE_ADDR
-#endif
-
#define UART_VADDR IMX_IO_ADDRESS(UART_PADDR)
.macro addruart, rp, rv
diff --git a/arch/arm/plat-mxc/include/mach/devices-common.h b/arch/arm/plat-mxc/include/mach/devices-common.h
index 8658c9c..fa84773 100644
--- a/arch/arm/plat-mxc/include/mach/devices-common.h
+++ b/arch/arm/plat-mxc/include/mach/devices-common.h
@@ -166,6 +166,24 @@
const struct imx_imx_udc_data *data,
const struct imxusb_platform_data *pdata);
+#include <mach/ipu.h>
+#include <mach/mx3fb.h>
+#include <mach/mx3_camera.h>
+struct imx_ipu_core_data {
+ resource_size_t iobase;
+ resource_size_t synirq;
+ resource_size_t errirq;
+};
+struct platform_device *__init imx_add_ipu_core(
+ const struct imx_ipu_core_data *data,
+ const struct ipu_platform_data *pdata);
+struct platform_device *__init imx_alloc_mx3_camera(
+ const struct imx_ipu_core_data *data,
+ const struct mx3_camera_pdata *pdata);
+struct platform_device *__init imx_add_mx3_sdc_fb(
+ const struct imx_ipu_core_data *data,
+ struct mx3fb_platform_data *pdata);
+
#include <mach/mx1_camera.h>
struct imx_mx1_camera_data {
resource_size_t iobase;
@@ -237,6 +255,15 @@
struct platform_device *__init imx_add_mxc_pwm(
const struct imx_mxc_pwm_data *data);
+/* mxc_rtc */
+struct imx_mxc_rtc_data {
+ resource_size_t iobase;
+ resource_size_t irq;
+};
+struct platform_device *__init imx_add_mxc_rtc(
+ const struct imx_mxc_rtc_data *data);
+
+/* mxc_w1 */
struct imx_mxc_w1_data {
resource_size_t iobase;
};
diff --git a/arch/arm/plat-mxc/include/mach/hardware.h b/arch/arm/plat-mxc/include/mach/hardware.h
index 26bb1ba..67d3e2b 100644
--- a/arch/arm/plat-mxc/include/mach/hardware.h
+++ b/arch/arm/plat-mxc/include/mach/hardware.h
@@ -86,15 +86,6 @@
* SPBA0 0x70000000+0x100000 -> 0xf5400000+0x100000
* AIPS1 0x73f00000+0x100000 -> 0xf5700000+0x100000
* AIPS2 0x83f00000+0x100000 -> 0xf4300000+0x100000
- * mxc91231:
- * L2CC 0x30000000+0x010000 -> 0xf4400000+0x010000
- * X_MEMC 0xb8000000+0x010000 -> 0xf4c00000+0x010000
- * ROMP 0x60000000+0x010000 -> 0xf5000000+0x010000
- * AVIC 0x68000000+0x010000 -> 0xf5800000+0x010000
- * AIPS1 0x43f00000+0x100000 -> 0xf5300000+0x100000
- * SPBA0 0x50000000+0x100000 -> 0xf5400000+0x100000
- * SPBA1 0x52000000+0x100000 -> 0xf5600000+0x100000
- * AIPS2 0x53f00000+0x100000 -> 0xf5700000+0x100000
*/
#define IMX_IO_P2V(x) ( \
0xf4000000 + \
@@ -104,6 +95,8 @@
#define IMX_IO_ADDRESS(x) IOMEM(IMX_IO_P2V(x))
+#include <mach/mxc.h>
+
#ifdef CONFIG_ARCH_MX5
#include <mach/mx50.h>
#include <mach/mx51.h>
@@ -134,12 +127,6 @@
# include <mach/mx25.h>
#endif
-#ifdef CONFIG_ARCH_MXC91231
-# include <mach/mxc91231.h>
-#endif
-
-#include <mach/mxc.h>
-
#define imx_map_entry(soc, name, _type) { \
.virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR), \
.pfn = __phys_to_pfn(soc ## _ ## name ## _BASE_ADDR), \
diff --git a/arch/arm/plat-mxc/include/mach/io.h b/arch/arm/plat-mxc/include/mach/io.h
index b4f2de7..4347a87 100644
--- a/arch/arm/plat-mxc/include/mach/io.h
+++ b/arch/arm/plat-mxc/include/mach/io.h
@@ -14,19 +14,26 @@
/* Allow IO space to be anywhere in the memory */
#define IO_SPACE_LIMIT 0xffffffff
-#ifdef CONFIG_ARCH_MX3
-#define __arch_ioremap __mx3_ioremap
+#if defined(CONFIG_SOC_IMX31) || defined(CONFIG_SOC_IMX35)
+#include <mach/hardware.h>
+
+#define __arch_ioremap __imx_ioremap
#define __arch_iounmap __iounmap
+#define addr_in_module(addr, mod) \
+ ((unsigned long)(addr) - mod ## _BASE_ADDR < mod ## _SIZE)
+
static inline void __iomem *
-__mx3_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
+__imx_ioremap(unsigned long phys_addr, size_t size, unsigned int mtype)
{
- if (mtype == MT_DEVICE) {
- /* Access all peripherals below 0x80000000 as nonshared device
- * but leave l2cc alone.
+ if (mtype == MT_DEVICE && (cpu_is_mx31() || cpu_is_mx35())) {
+ /*
+ * Access all peripherals below 0x80000000 as nonshared device
+ * on mx3, but leave l2cc alone. Otherwise cache corruptions
+ * can occur.
*/
- if ((phys_addr < 0x80000000) && ((phys_addr < 0x30000000) ||
- (phys_addr >= 0x30000000 + SZ_1M)))
+ if (phys_addr < 0x80000000 &&
+ !addr_in_module(phys_addr, MX3x_L2CC))
mtype = MT_DEVICE_NONSHARED;
}
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mx25.h b/arch/arm/plat-mxc/include/mach/iomux-mx25.h
index d7f52c9..2e5244d 100644
--- a/arch/arm/plat-mxc/include/mach/iomux-mx25.h
+++ b/arch/arm/plat-mxc/include/mach/iomux-mx25.h
@@ -89,13 +89,16 @@
#define MX25_PAD_CS0__GPIO_4_2 IOMUX_PAD(0x000, 0x04c, 0x05, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CS1__CS1 IOMUX_PAD(0x000, 0x050, 0x00, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CS1__NF_CE3 IOMUX_PAD(0x000, 0x050, 0x01, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CS1__GPIO_4_3 IOMUX_PAD(0x000, 0x050, 0x05, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CS4__CS4 IOMUX_PAD(0x264, 0x054, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CS4__NF_CE1 IOMUX_PAD(0x264, 0x054, 0x01, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CS4__UART5_CTS IOMUX_PAD(0x264, 0x054, 0x13, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CS4__GPIO_3_20 IOMUX_PAD(0x264, 0x054, 0x15, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CS5__CS5 IOMUX_PAD(0x268, 0x058, 0x10, 0, 0, NO_PAD_CTRL)
+#define MX25_PAD_CS5__NF_CE2 IOMUX_PAD(0x268, 0x058, 0x01, 0, 0, NO_PAD_CTRL)
#define MX25_PAD_CS5__UART5_RTS IOMUX_PAD(0x268, 0x058, 0x13, 0x574, 0, NO_PAD_CTRL)
#define MX25_PAD_CS5__GPIO_3_21 IOMUX_PAD(0x268, 0x058, 0x15, 0, 0, NO_PAD_CTRL)
diff --git a/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h b/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h
deleted file mode 100644
index bf28df0..0000000
--- a/arch/arm/plat-mxc/include/mach/iomux-mxc91231.h
+++ /dev/null
@@ -1,283 +0,0 @@
-/*
- * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright (C) 2008 by Sascha Hauer <kernel@pengutronix.de>
- * Copyright (C) 2009 by Dmitriy Taychenachev <dimichxp@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __MACH_IOMUX_MXC91231_H__
-#define __MACH_IOMUX_MXC91231_H__
-
-/*
- * various IOMUX output functions
- */
-
-#define IOMUX_OCONFIG_GPIO (0 << 4) /* used as GPIO */
-#define IOMUX_OCONFIG_FUNC (1 << 4) /* used as function */
-#define IOMUX_OCONFIG_ALT1 (2 << 4) /* used as alternate function 1 */
-#define IOMUX_OCONFIG_ALT2 (3 << 4) /* used as alternate function 2 */
-#define IOMUX_OCONFIG_ALT3 (4 << 4) /* used as alternate function 3 */
-#define IOMUX_OCONFIG_ALT4 (5 << 4) /* used as alternate function 4 */
-#define IOMUX_OCONFIG_ALT5 (6 << 4) /* used as alternate function 5 */
-#define IOMUX_OCONFIG_ALT6 (7 << 4) /* used as alternate function 6 */
-#define IOMUX_ICONFIG_NONE 0 /* not configured for input */
-#define IOMUX_ICONFIG_GPIO 1 /* used as GPIO */
-#define IOMUX_ICONFIG_FUNC 2 /* used as function */
-#define IOMUX_ICONFIG_ALT1 4 /* used as alternate function 1 */
-#define IOMUX_ICONFIG_ALT2 8 /* used as alternate function 2 */
-
-#define IOMUX_CONFIG_GPIO (IOMUX_OCONFIG_GPIO | IOMUX_ICONFIG_GPIO)
-#define IOMUX_CONFIG_FUNC (IOMUX_OCONFIG_FUNC | IOMUX_ICONFIG_FUNC)
-#define IOMUX_CONFIG_ALT1 (IOMUX_OCONFIG_ALT1 | IOMUX_ICONFIG_ALT1)
-#define IOMUX_CONFIG_ALT2 (IOMUX_OCONFIG_ALT2 | IOMUX_ICONFIG_ALT2)
-
-/*
- * setups a single pin:
- * - reserves the pin so that it is not claimed by another driver
- * - setups the iomux according to the configuration
- * - if the pin is configured as a GPIO, we claim it through kernel gpiolib
- */
-int mxc_iomux_alloc_pin(unsigned int pin_mode, const char *label);
-/*
- * setups mutliple pins
- * convenient way to call the above function with tables
- */
-int mxc_iomux_setup_multiple_pins(const unsigned int *pin_list, unsigned count,
- const char *label);
-
-/*
- * releases a single pin:
- * - make it available for a future use by another driver
- * - frees the GPIO if the pin was configured as GPIO
- * - DOES NOT reconfigure the IOMUX in its reset state
- */
-void mxc_iomux_release_pin(unsigned int pin_mode);
-/*
- * releases multiple pins
- * convenvient way to call the above function with tables
- */
-void mxc_iomux_release_multiple_pins(const unsigned int *pin_list, int count);
-
-#define MUX_SIDE_AP (0)
-#define MUX_SIDE_SP (1)
-
-#define MUX_SIDE_SHIFT (26)
-#define MUX_SIDE_MASK (0x1 << MUX_SIDE_SHIFT)
-
-#define MUX_GPIO_PORT_SHIFT (23)
-#define MUX_GPIO_PORT_MASK (0x7 << MUX_GPIO_PORT_SHIFT)
-
-#define MUX_GPIO_PIN_SHIFT (20)
-#define MUX_GPIO_PIN_MASK (0x1f << MUX_GPIO_PIN_SHIFT)
-
-#define MUX_REG_SHIFT (15)
-#define MUX_REG_MASK (0x1f << MUX_REG_SHIFT)
-
-#define MUX_FIELD_SHIFT (13)
-#define MUX_FIELD_MASK (0x3 << MUX_FIELD_SHIFT)
-
-#define MUX_PADGRP_SHIFT (8)
-#define MUX_PADGRP_MASK (0x1f << MUX_PADGRP_SHIFT)
-
-#define MUX_PIN_MASK (0xffffff << 8)
-
-#define GPIO_PORT_MAX (3)
-
-#define IOMUX_PIN(side, gport, gpin, ctlreg, ctlfield, padgrp) \
- (((side) << MUX_SIDE_SHIFT) | \
- (gport << MUX_GPIO_PORT_SHIFT) | \
- ((gpin) << MUX_GPIO_PIN_SHIFT) | \
- ((ctlreg) << MUX_REG_SHIFT) | \
- ((ctlfield) << MUX_FIELD_SHIFT) | \
- ((padgrp) << MUX_PADGRP_SHIFT))
-
-#define MUX_MODE_OUT_SHIFT (4)
-#define MUX_MODE_IN_SHIFT (0)
-#define MUX_MODE_SHIFT (0)
-#define MUX_MODE_MASK (0xff << MUX_MODE_SHIFT)
-
-#define IOMUX_MODE(pin, mode) \
- (pin | (mode << MUX_MODE_SHIFT))
-
-enum iomux_pins {
- /* AP Side pins */
- MXC91231_PIN_AP_CLE = IOMUX_PIN(0, 0, 0, 0, 0, 24),
- MXC91231_PIN_AP_ALE = IOMUX_PIN(0, 0, 1, 0, 1, 24),
- MXC91231_PIN_AP_CE_B = IOMUX_PIN(0, 0, 2, 0, 2, 24),
- MXC91231_PIN_AP_RE_B = IOMUX_PIN(0, 0, 3, 0, 3, 24),
- MXC91231_PIN_AP_WE_B = IOMUX_PIN(0, 0, 4, 1, 0, 24),
- MXC91231_PIN_AP_WP_B = IOMUX_PIN(0, 0, 5, 1, 1, 24),
- MXC91231_PIN_AP_BSY_B = IOMUX_PIN(0, 0, 6, 1, 2, 24),
- MXC91231_PIN_AP_U1_TXD = IOMUX_PIN(0, 0, 7, 1, 3, 28),
- MXC91231_PIN_AP_U1_RXD = IOMUX_PIN(0, 0, 8, 2, 0, 28),
- MXC91231_PIN_AP_U1_RTS_B = IOMUX_PIN(0, 0, 9, 2, 1, 28),
- MXC91231_PIN_AP_U1_CTS_B = IOMUX_PIN(0, 0, 10, 2, 2, 28),
- MXC91231_PIN_AP_AD1_TXD = IOMUX_PIN(0, 0, 11, 2, 3, 9),
- MXC91231_PIN_AP_AD1_RXD = IOMUX_PIN(0, 0, 12, 3, 0, 9),
- MXC91231_PIN_AP_AD1_TXC = IOMUX_PIN(0, 0, 13, 3, 1, 9),
- MXC91231_PIN_AP_AD1_TXFS = IOMUX_PIN(0, 0, 14, 3, 2, 9),
- MXC91231_PIN_AP_AD2_TXD = IOMUX_PIN(0, 0, 15, 3, 3, 9),
- MXC91231_PIN_AP_AD2_RXD = IOMUX_PIN(0, 0, 16, 4, 0, 9),
- MXC91231_PIN_AP_AD2_TXC = IOMUX_PIN(0, 0, 17, 4, 1, 9),
- MXC91231_PIN_AP_AD2_TXFS = IOMUX_PIN(0, 0, 18, 4, 2, 9),
- MXC91231_PIN_AP_OWDAT = IOMUX_PIN(0, 0, 19, 4, 3, 28),
- MXC91231_PIN_AP_IPU_LD17 = IOMUX_PIN(0, 0, 20, 5, 0, 28),
- MXC91231_PIN_AP_IPU_D3_VSYNC = IOMUX_PIN(0, 0, 21, 5, 1, 28),
- MXC91231_PIN_AP_IPU_D3_HSYNC = IOMUX_PIN(0, 0, 22, 5, 2, 28),
- MXC91231_PIN_AP_IPU_D3_CLK = IOMUX_PIN(0, 0, 23, 5, 3, 28),
- MXC91231_PIN_AP_IPU_D3_DRDY = IOMUX_PIN(0, 0, 24, 6, 0, 28),
- MXC91231_PIN_AP_IPU_D3_CONTR = IOMUX_PIN(0, 0, 25, 6, 1, 28),
- MXC91231_PIN_AP_IPU_D0_CS = IOMUX_PIN(0, 0, 26, 6, 2, 28),
- MXC91231_PIN_AP_IPU_LD16 = IOMUX_PIN(0, 0, 27, 6, 3, 28),
- MXC91231_PIN_AP_IPU_D2_CS = IOMUX_PIN(0, 0, 28, 7, 0, 28),
- MXC91231_PIN_AP_IPU_PAR_RS = IOMUX_PIN(0, 0, 29, 7, 1, 28),
- MXC91231_PIN_AP_IPU_D3_PS = IOMUX_PIN(0, 0, 30, 7, 2, 28),
- MXC91231_PIN_AP_IPU_D3_CLS = IOMUX_PIN(0, 0, 31, 7, 3, 28),
- MXC91231_PIN_AP_IPU_RD = IOMUX_PIN(0, 1, 0, 8, 0, 28),
- MXC91231_PIN_AP_IPU_WR = IOMUX_PIN(0, 1, 1, 8, 1, 28),
- MXC91231_PIN_AP_IPU_LD0 = IOMUX_PIN(0, 7, 0, 8, 2, 28),
- MXC91231_PIN_AP_IPU_LD1 = IOMUX_PIN(0, 7, 0, 8, 3, 28),
- MXC91231_PIN_AP_IPU_LD2 = IOMUX_PIN(0, 7, 0, 9, 0, 28),
- MXC91231_PIN_AP_IPU_LD3 = IOMUX_PIN(0, 1, 2, 9, 1, 28),
- MXC91231_PIN_AP_IPU_LD4 = IOMUX_PIN(0, 1, 3, 9, 2, 28),
- MXC91231_PIN_AP_IPU_LD5 = IOMUX_PIN(0, 1, 4, 9, 3, 28),
- MXC91231_PIN_AP_IPU_LD6 = IOMUX_PIN(0, 1, 5, 10, 0, 28),
- MXC91231_PIN_AP_IPU_LD7 = IOMUX_PIN(0, 1, 6, 10, 1, 28),
- MXC91231_PIN_AP_IPU_LD8 = IOMUX_PIN(0, 1, 7, 10, 2, 28),
- MXC91231_PIN_AP_IPU_LD9 = IOMUX_PIN(0, 1, 8, 10, 3, 28),
- MXC91231_PIN_AP_IPU_LD10 = IOMUX_PIN(0, 1, 9, 11, 0, 28),
- MXC91231_PIN_AP_IPU_LD11 = IOMUX_PIN(0, 1, 10, 11, 1, 28),
- MXC91231_PIN_AP_IPU_LD12 = IOMUX_PIN(0, 1, 11, 11, 2, 28),
- MXC91231_PIN_AP_IPU_LD13 = IOMUX_PIN(0, 1, 12, 11, 3, 28),
- MXC91231_PIN_AP_IPU_LD14 = IOMUX_PIN(0, 1, 13, 12, 0, 28),
- MXC91231_PIN_AP_IPU_LD15 = IOMUX_PIN(0, 1, 14, 12, 1, 28),
- MXC91231_PIN_AP_KPROW4 = IOMUX_PIN(0, 7, 0, 12, 2, 10),
- MXC91231_PIN_AP_KPROW5 = IOMUX_PIN(0, 1, 16, 12, 3, 10),
- MXC91231_PIN_AP_GPIO_AP_B17 = IOMUX_PIN(0, 1, 17, 13, 0, 10),
- MXC91231_PIN_AP_GPIO_AP_B18 = IOMUX_PIN(0, 1, 18, 13, 1, 10),
- MXC91231_PIN_AP_KPCOL3 = IOMUX_PIN(0, 1, 19, 13, 2, 11),
- MXC91231_PIN_AP_KPCOL4 = IOMUX_PIN(0, 1, 20, 13, 3, 11),
- MXC91231_PIN_AP_KPCOL5 = IOMUX_PIN(0, 1, 21, 14, 0, 11),
- MXC91231_PIN_AP_GPIO_AP_B22 = IOMUX_PIN(0, 1, 22, 14, 1, 11),
- MXC91231_PIN_AP_GPIO_AP_B23 = IOMUX_PIN(0, 1, 23, 14, 2, 11),
- MXC91231_PIN_AP_CSI_D0 = IOMUX_PIN(0, 1, 24, 14, 3, 21),
- MXC91231_PIN_AP_CSI_D1 = IOMUX_PIN(0, 1, 25, 15, 0, 21),
- MXC91231_PIN_AP_CSI_D2 = IOMUX_PIN(0, 1, 26, 15, 1, 21),
- MXC91231_PIN_AP_CSI_D3 = IOMUX_PIN(0, 1, 27, 15, 2, 21),
- MXC91231_PIN_AP_CSI_D4 = IOMUX_PIN(0, 1, 28, 15, 3, 21),
- MXC91231_PIN_AP_CSI_D5 = IOMUX_PIN(0, 1, 29, 16, 0, 21),
- MXC91231_PIN_AP_CSI_D6 = IOMUX_PIN(0, 1, 30, 16, 1, 21),
- MXC91231_PIN_AP_CSI_D7 = IOMUX_PIN(0, 1, 31, 16, 2, 21),
- MXC91231_PIN_AP_CSI_D8 = IOMUX_PIN(0, 2, 0, 16, 3, 21),
- MXC91231_PIN_AP_CSI_D9 = IOMUX_PIN(0, 2, 1, 17, 0, 21),
- MXC91231_PIN_AP_CSI_MCLK = IOMUX_PIN(0, 2, 2, 17, 1, 21),
- MXC91231_PIN_AP_CSI_VSYNC = IOMUX_PIN(0, 2, 3, 17, 2, 21),
- MXC91231_PIN_AP_CSI_HSYNC = IOMUX_PIN(0, 2, 4, 17, 3, 21),
- MXC91231_PIN_AP_CSI_PIXCLK = IOMUX_PIN(0, 2, 5, 18, 0, 21),
- MXC91231_PIN_AP_I2CLK = IOMUX_PIN(0, 2, 6, 18, 1, 12),
- MXC91231_PIN_AP_I2DAT = IOMUX_PIN(0, 2, 7, 18, 2, 12),
- MXC91231_PIN_AP_GPIO_AP_C8 = IOMUX_PIN(0, 2, 8, 18, 3, 9),
- MXC91231_PIN_AP_GPIO_AP_C9 = IOMUX_PIN(0, 2, 9, 19, 0, 9),
- MXC91231_PIN_AP_GPIO_AP_C10 = IOMUX_PIN(0, 2, 10, 19, 1, 9),
- MXC91231_PIN_AP_GPIO_AP_C11 = IOMUX_PIN(0, 2, 11, 19, 2, 9),
- MXC91231_PIN_AP_GPIO_AP_C12 = IOMUX_PIN(0, 2, 12, 19, 3, 9),
- MXC91231_PIN_AP_GPIO_AP_C13 = IOMUX_PIN(0, 2, 13, 20, 0, 28),
- MXC91231_PIN_AP_GPIO_AP_C14 = IOMUX_PIN(0, 2, 14, 20, 1, 28),
- MXC91231_PIN_AP_GPIO_AP_C15 = IOMUX_PIN(0, 2, 15, 20, 2, 9),
- MXC91231_PIN_AP_GPIO_AP_C16 = IOMUX_PIN(0, 2, 16, 20, 3, 9),
- MXC91231_PIN_AP_GPIO_AP_C17 = IOMUX_PIN(0, 2, 17, 21, 0, 9),
- MXC91231_PIN_AP_ED_INT0 = IOMUX_PIN(0, 2, 18, 21, 1, 22),
- MXC91231_PIN_AP_ED_INT1 = IOMUX_PIN(0, 2, 19, 21, 2, 22),
- MXC91231_PIN_AP_ED_INT2 = IOMUX_PIN(0, 2, 20, 21, 3, 22),
- MXC91231_PIN_AP_ED_INT3 = IOMUX_PIN(0, 2, 21, 22, 0, 22),
- MXC91231_PIN_AP_ED_INT4 = IOMUX_PIN(0, 2, 22, 22, 1, 23),
- MXC91231_PIN_AP_ED_INT5 = IOMUX_PIN(0, 2, 23, 22, 2, 23),
- MXC91231_PIN_AP_ED_INT6 = IOMUX_PIN(0, 2, 24, 22, 3, 23),
- MXC91231_PIN_AP_ED_INT7 = IOMUX_PIN(0, 2, 25, 23, 0, 23),
- MXC91231_PIN_AP_U2_DSR_B = IOMUX_PIN(0, 2, 26, 23, 1, 28),
- MXC91231_PIN_AP_U2_RI_B = IOMUX_PIN(0, 2, 27, 23, 2, 28),
- MXC91231_PIN_AP_U2_CTS_B = IOMUX_PIN(0, 2, 28, 23, 3, 28),
- MXC91231_PIN_AP_U2_DTR_B = IOMUX_PIN(0, 2, 29, 24, 0, 28),
- MXC91231_PIN_AP_KPROW0 = IOMUX_PIN(0, 7, 0, 24, 1, 10),
- MXC91231_PIN_AP_KPROW1 = IOMUX_PIN(0, 1, 15, 24, 2, 10),
- MXC91231_PIN_AP_KPROW2 = IOMUX_PIN(0, 7, 0, 24, 3, 10),
- MXC91231_PIN_AP_KPROW3 = IOMUX_PIN(0, 7, 0, 25, 0, 10),
- MXC91231_PIN_AP_KPCOL0 = IOMUX_PIN(0, 7, 0, 25, 1, 11),
- MXC91231_PIN_AP_KPCOL1 = IOMUX_PIN(0, 7, 0, 25, 2, 11),
- MXC91231_PIN_AP_KPCOL2 = IOMUX_PIN(0, 7, 0, 25, 3, 11),
-
- /* Shared pins */
- MXC91231_PIN_SP_U3_TXD = IOMUX_PIN(1, 3, 0, 0, 0, 28),
- MXC91231_PIN_SP_U3_RXD = IOMUX_PIN(1, 3, 1, 0, 1, 28),
- MXC91231_PIN_SP_U3_RTS_B = IOMUX_PIN(1, 3, 2, 0, 2, 28),
- MXC91231_PIN_SP_U3_CTS_B = IOMUX_PIN(1, 3, 3, 0, 3, 28),
- MXC91231_PIN_SP_USB_TXOE_B = IOMUX_PIN(1, 3, 4, 1, 0, 28),
- MXC91231_PIN_SP_USB_DAT_VP = IOMUX_PIN(1, 3, 5, 1, 1, 28),
- MXC91231_PIN_SP_USB_SE0_VM = IOMUX_PIN(1, 3, 6, 1, 2, 28),
- MXC91231_PIN_SP_USB_RXD = IOMUX_PIN(1, 3, 7, 1, 3, 28),
- MXC91231_PIN_SP_UH2_TXOE_B = IOMUX_PIN(1, 3, 8, 2, 0, 28),
- MXC91231_PIN_SP_UH2_SPEED = IOMUX_PIN(1, 3, 9, 2, 1, 28),
- MXC91231_PIN_SP_UH2_SUSPEN = IOMUX_PIN(1, 3, 10, 2, 2, 28),
- MXC91231_PIN_SP_UH2_TXDP = IOMUX_PIN(1, 3, 11, 2, 3, 28),
- MXC91231_PIN_SP_UH2_RXDP = IOMUX_PIN(1, 3, 12, 3, 0, 28),
- MXC91231_PIN_SP_UH2_RXDM = IOMUX_PIN(1, 3, 13, 3, 1, 28),
- MXC91231_PIN_SP_UH2_OVR = IOMUX_PIN(1, 3, 14, 3, 2, 28),
- MXC91231_PIN_SP_UH2_PWR = IOMUX_PIN(1, 3, 15, 3, 3, 28),
- MXC91231_PIN_SP_SD1_DAT0 = IOMUX_PIN(1, 3, 16, 4, 0, 25),
- MXC91231_PIN_SP_SD1_DAT1 = IOMUX_PIN(1, 3, 17, 4, 1, 25),
- MXC91231_PIN_SP_SD1_DAT2 = IOMUX_PIN(1, 3, 18, 4, 2, 25),
- MXC91231_PIN_SP_SD1_DAT3 = IOMUX_PIN(1, 3, 19, 4, 3, 25),
- MXC91231_PIN_SP_SD1_CMD = IOMUX_PIN(1, 3, 20, 5, 0, 25),
- MXC91231_PIN_SP_SD1_CLK = IOMUX_PIN(1, 3, 21, 5, 1, 25),
- MXC91231_PIN_SP_SD2_DAT0 = IOMUX_PIN(1, 3, 22, 5, 2, 26),
- MXC91231_PIN_SP_SD2_DAT1 = IOMUX_PIN(1, 3, 23, 5, 3, 26),
- MXC91231_PIN_SP_SD2_DAT2 = IOMUX_PIN(1, 3, 24, 6, 0, 26),
- MXC91231_PIN_SP_SD2_DAT3 = IOMUX_PIN(1, 3, 25, 6, 1, 26),
- MXC91231_PIN_SP_GPIO_SP_A26 = IOMUX_PIN(1, 3, 26, 6, 2, 28),
- MXC91231_PIN_SP_SPI1_CLK = IOMUX_PIN(1, 3, 27, 6, 3, 13),
- MXC91231_PIN_SP_SPI1_MOSI = IOMUX_PIN(1, 3, 28, 7, 0, 13),
- MXC91231_PIN_SP_SPI1_MISO = IOMUX_PIN(1, 3, 29, 7, 1, 13),
- MXC91231_PIN_SP_SPI1_SS0 = IOMUX_PIN(1, 3, 30, 7, 2, 13),
- MXC91231_PIN_SP_SPI1_SS1 = IOMUX_PIN(1, 3, 31, 7, 3, 13),
- MXC91231_PIN_SP_SD2_CMD = IOMUX_PIN(1, 7, 0, 8, 0, 26),
- MXC91231_PIN_SP_SD2_CLK = IOMUX_PIN(1, 7, 0, 8, 1, 26),
- MXC91231_PIN_SP_SIM1_RST_B = IOMUX_PIN(1, 2, 30, 8, 2, 28),
- MXC91231_PIN_SP_SIM1_SVEN = IOMUX_PIN(1, 7, 0, 8, 3, 28),
- MXC91231_PIN_SP_SIM1_CLK = IOMUX_PIN(1, 7, 0, 9, 0, 28),
- MXC91231_PIN_SP_SIM1_TRXD = IOMUX_PIN(1, 7, 0, 9, 1, 28),
- MXC91231_PIN_SP_SIM1_PD = IOMUX_PIN(1, 2, 31, 9, 2, 28),
- MXC91231_PIN_SP_UH2_TXDM = IOMUX_PIN(1, 7, 0, 9, 3, 28),
- MXC91231_PIN_SP_UH2_RXD = IOMUX_PIN(1, 7, 0, 10, 0, 28),
-};
-
-#define PIN_AP_MAX (104)
-#define PIN_SP_MAX (41)
-
-#define PIN_MAX (PIN_AP_MAX + PIN_SP_MAX)
-
-/*
- * Convenience values for use with mxc_iomux_mode()
- *
- * Format here is MXC91231_PIN_(pin name)__(function)
- */
-
-#define MXC91231_PIN_SP_USB_DAT_VP__USB_DAT_VP \
- IOMUX_MODE(MXC91231_PIN_SP_USB_DAT_VP, IOMUX_CONFIG_FUNC)
-#define MXC91231_PIN_SP_USB_SE0_VM__USB_SE0_VM \
- IOMUX_MODE(MXC91231_PIN_SP_USB_SE0_VM, IOMUX_CONFIG_FUNC)
-#define MXC91231_PIN_SP_USB_DAT_VP__RXD2 \
- IOMUX_MODE(MXC91231_PIN_SP_USB_DAT_VP, IOMUX_CONFIG_ALT1)
-#define MXC91231_PIN_SP_USB_SE0_VM__TXD2 \
- IOMUX_MODE(MXC91231_PIN_SP_USB_SE0_VM, IOMUX_CONFIG_ALT1)
-
-
-#endif /* __MACH_IOMUX_MXC91231_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/irqs.h b/arch/arm/plat-mxc/include/mach/irqs.h
index a3d930d3..35c89bc 100644
--- a/arch/arm/plat-mxc/include/mach/irqs.h
+++ b/arch/arm/plat-mxc/include/mach/irqs.h
@@ -35,8 +35,6 @@
#define MXC_GPIO_IRQS (32 * 4)
#elif defined CONFIG_SOC_IMX51
#define MXC_GPIO_IRQS (32 * 4)
-#elif defined CONFIG_ARCH_MXC91231
-#define MXC_GPIO_IRQS (32 * 4)
#elif defined CONFIG_ARCH_MX3
#define MXC_GPIO_IRQS (32 * 3)
#endif
diff --git a/arch/arm/plat-mxc/include/mach/memory.h b/arch/arm/plat-mxc/include/mach/memory.h
index 5d51cbb..11be5cd 100644
--- a/arch/arm/plat-mxc/include/mach/memory.h
+++ b/arch/arm/plat-mxc/include/mach/memory.h
@@ -19,7 +19,6 @@
#define MX50_PHYS_OFFSET UL(0x70000000)
#define MX51_PHYS_OFFSET UL(0x90000000)
#define MX53_PHYS_OFFSET UL(0x70000000)
-#define MXC91231_PHYS_OFFSET UL(0x90000000)
#if !defined(CONFIG_RUNTIME_PHYS_OFFSET)
# if defined CONFIG_ARCH_MX1
@@ -32,8 +31,6 @@
# define PLAT_PHYS_OFFSET MX27_PHYS_OFFSET
# elif defined CONFIG_ARCH_MX3
# define PLAT_PHYS_OFFSET MX3x_PHYS_OFFSET
-# elif defined CONFIG_ARCH_MXC91231
-# define PLAT_PHYS_OFFSET MXC91231_PHYS_OFFSET
# elif defined CONFIG_ARCH_MX50
# define PLAT_PHYS_OFFSET MX50_PHYS_OFFSET
# elif defined CONFIG_ARCH_MX51
diff --git a/arch/arm/plat-mxc/include/mach/mx27.h b/arch/arm/plat-mxc/include/mach/mx27.h
index cbc43ad..1dc1c52 100644
--- a/arch/arm/plat-mxc/include/mach/mx27.h
+++ b/arch/arm/plat-mxc/include/mach/mx27.h
@@ -60,8 +60,8 @@
#define MX27_AUDMUX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x16000)
#define MX27_CSPI3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x17000)
#define MX27_MSHC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x18000)
-#define MX27_GPT5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x19000)
-#define MX27_GPT4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1a000)
+#define MX27_GPT4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x19000)
+#define MX27_GPT5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1a000)
#define MX27_UART5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1b000)
#define MX27_UART6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1c000)
#define MX27_I2C2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1d000)
diff --git a/arch/arm/plat-mxc/include/mach/mx53.h b/arch/arm/plat-mxc/include/mach/mx53.h
index ace1786..9d2a1ef 100644
--- a/arch/arm/plat-mxc/include/mach/mx53.h
+++ b/arch/arm/plat-mxc/include/mach/mx53.h
@@ -337,17 +337,4 @@
#define MX53_INT_GPIO7_LOW 107
#define MX53_INT_GPIO7_HIGH 108
-/* silicon revisions specific to i.MX53 */
-#define MX53_CHIP_REV_1_0 0x10
-#define MX53_CHIP_REV_1_1 0x11
-#define MX53_CHIP_REV_1_2 0x12
-#define MX53_CHIP_REV_1_3 0x13
-#define MX53_CHIP_REV_2_0 0x20
-#define MX53_CHIP_REV_2_1 0x21
-#define MX53_CHIP_REV_2_2 0x22
-#define MX53_CHIP_REV_2_3 0x23
-#define MX53_CHIP_REV_3_0 0x30
-#define MX53_CHIP_REV_3_1 0x31
-#define MX53_CHIP_REV_3_2 0x32
-
#endif /* ifndef __MACH_MX53_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
index 1aea818..4ac53ce 100644
--- a/arch/arm/plat-mxc/include/mach/mxc.h
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
@@ -35,7 +35,6 @@
#define MXC_CPU_MX50 50
#define MXC_CPU_MX51 51
#define MXC_CPU_MX53 53
-#define MXC_CPU_MXC91231 91231
#define IMX_CHIP_REVISION_1_0 0x10
#define IMX_CHIP_REVISION_1_1 0x11
@@ -177,18 +176,6 @@
# define cpu_is_mx53() (0)
#endif
-#ifdef CONFIG_ARCH_MXC91231
-# ifdef mxc_cpu_type
-# undef mxc_cpu_type
-# define mxc_cpu_type __mxc_cpu_type
-# else
-# define mxc_cpu_type MXC_CPU_MXC91231
-# endif
-# define cpu_is_mxc91231() (mxc_cpu_type == MXC_CPU_MXC91231)
-#else
-# define cpu_is_mxc91231() (0)
-#endif
-
#ifndef __ASSEMBLY__
struct cpu_op {
@@ -207,14 +194,7 @@
extern struct cpu_op *(*get_cpu_op)(int *op);
#endif
-#if defined(CONFIG_ARCH_MX3) || defined(CONFIG_ARCH_MX2)
-/* These are deprecated, use mx[23][157]_setup_weimcs instead. */
-#define CSCR_U(n) (IO_ADDRESS(WEIM_BASE_ADDR + n * 0x10))
-#define CSCR_L(n) (IO_ADDRESS(WEIM_BASE_ADDR + n * 0x10 + 0x4))
-#define CSCR_A(n) (IO_ADDRESS(WEIM_BASE_ADDR + n * 0x10 + 0x8))
-#endif
-
-#define cpu_is_mx3() (cpu_is_mx31() || cpu_is_mx35() || cpu_is_mxc91231())
+#define cpu_is_mx3() (cpu_is_mx31() || cpu_is_mx35())
#define cpu_is_mx2() (cpu_is_mx21() || cpu_is_mx27())
#endif /* __ASM_ARCH_MXC_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/mxc91231.h b/arch/arm/plat-mxc/include/mach/mxc91231.h
deleted file mode 100644
index 765190f..0000000
--- a/arch/arm/plat-mxc/include/mach/mxc91231.h
+++ /dev/null
@@ -1,256 +0,0 @@
-/*
- * Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
- * - Platform specific register memory map
- *
- * Copyright 2005-2007 Motorola, Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-#ifndef __MACH_MXC91231_H__
-#define __MACH_MXC91231_H__
-
-/*
- * L2CC
- */
-#define MXC91231_L2CC_BASE_ADDR 0x30000000
-#define MXC91231_L2CC_SIZE SZ_64K
-
-/*
- * AIPS 1
- */
-#define MXC91231_AIPS1_BASE_ADDR 0x43F00000
-#define MXC91231_AIPS1_SIZE SZ_1M
-
-#define MXC91231_AIPS1_CTRL_BASE_ADDR MXC91231_AIPS1_BASE_ADDR
-#define MXC91231_MAX_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x04000)
-#define MXC91231_EVTMON_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x08000)
-#define MXC91231_CLKCTL_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x0C000)
-#define MXC91231_ETB_SLOT4_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x10000)
-#define MXC91231_ETB_SLOT5_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x14000)
-#define MXC91231_ECT_CTIO_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x18000)
-#define MXC91231_I2C_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x80000)
-#define MXC91231_MU_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x88000)
-#define MXC91231_UART1_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x90000)
-#define MXC91231_UART2_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x94000)
-#define MXC91231_DSM_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x98000)
-#define MXC91231_OWIRE_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0x9C000)
-#define MXC91231_SSI1_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0xA0000)
-#define MXC91231_KPP_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0xA8000)
-#define MXC91231_IOMUX_AP_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0xAC000)
-#define MXC91231_CTI_AP_BASE_ADDR (MXC91231_AIPS1_BASE_ADDR + 0xB8000)
-
-/*
- * AIPS 2
- */
-#define MXC91231_AIPS2_BASE_ADDR 0x53F00000
-#define MXC91231_AIPS2_SIZE SZ_1M
-
-#define MXC91231_GEMK_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0x8C000)
-#define MXC91231_GPT1_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0x90000)
-#define MXC91231_EPIT1_AP_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0x94000)
-#define MXC91231_SCC_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xAC000)
-#define MXC91231_RNGA_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xB0000)
-#define MXC91231_IPU_CTRL_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xC0000)
-#define MXC91231_AUDMUX_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xC4000)
-#define MXC91231_EDIO_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xC8000)
-#define MXC91231_GPIO1_AP_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xCC000)
-#define MXC91231_GPIO2_AP_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xD0000)
-#define MXC91231_SDMA_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xD4000)
-#define MXC91231_RTC_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xD8000)
-#define MXC91231_WDOG1_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xDC000)
-#define MXC91231_PWM_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xE0000)
-#define MXC91231_GPIO3_AP_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xE4000)
-#define MXC91231_WDOG2_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xE8000)
-#define MXC91231_RTIC_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xEC000)
-#define MXC91231_LPMC_BASE_ADDR (MXC91231_AIPS2_BASE_ADDR + 0xF0000)
-
-/*
- * SPBA global module 0
- */
-#define MXC91231_SPBA0_BASE_ADDR 0x50000000
-#define MXC91231_SPBA0_SIZE SZ_1M
-
-#define MXC91231_MMC_SDHC1_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x04000)
-#define MXC91231_MMC_SDHC2_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x08000)
-#define MXC91231_UART3_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x0C000)
-#define MXC91231_CSPI2_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x10000)
-#define MXC91231_SSI2_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x14000)
-#define MXC91231_SIM_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x18000)
-#define MXC91231_IIM_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x1C000)
-#define MXC91231_CTI_SDMA_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x20000)
-#define MXC91231_USBOTG_CTRL_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x24000)
-#define MXC91231_USBOTG_DATA_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x28000)
-#define MXC91231_CSPI1_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x30000)
-#define MXC91231_SPBA_CTRL_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x3C000)
-#define MXC91231_IOMUX_COM_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x40000)
-#define MXC91231_CRM_COM_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x44000)
-#define MXC91231_CRM_AP_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x48000)
-#define MXC91231_PLL0_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x4C000)
-#define MXC91231_PLL1_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x50000)
-#define MXC91231_PLL2_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x54000)
-#define MXC91231_GPIO4_SH_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x58000)
-#define MXC91231_HAC_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x5C000)
-#define MXC91231_SAHARA_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x5C000)
-#define MXC91231_PLL3_BASE_ADDR (MXC91231_SPBA0_BASE_ADDR + 0x60000)
-
-/*
- * SPBA global module 1
- */
-#define MXC91231_SPBA1_BASE_ADDR 0x52000000
-#define MXC91231_SPBA1_SIZE SZ_1M
-
-#define MXC91231_MQSPI_BASE_ADDR (MXC91231_SPBA1_BASE_ADDR + 0x34000)
-#define MXC91231_EL1T_BASE_ADDR (MXC91231_SPBA1_BASE_ADDR + 0x38000)
-
-/*!
- * Defines for SPBA modules
- */
-#define MXC91231_SPBA_SDHC1 0x04
-#define MXC91231_SPBA_SDHC2 0x08
-#define MXC91231_SPBA_UART3 0x0C
-#define MXC91231_SPBA_CSPI2 0x10
-#define MXC91231_SPBA_SSI2 0x14
-#define MXC91231_SPBA_SIM 0x18
-#define MXC91231_SPBA_IIM 0x1C
-#define MXC91231_SPBA_CTI_SDMA 0x20
-#define MXC91231_SPBA_USBOTG_CTRL_REGS 0x24
-#define MXC91231_SPBA_USBOTG_DATA_REGS 0x28
-#define MXC91231_SPBA_CSPI1 0x30
-#define MXC91231_SPBA_MQSPI 0x34
-#define MXC91231_SPBA_EL1T 0x38
-#define MXC91231_SPBA_IOMUX 0x40
-#define MXC91231_SPBA_CRM_COM 0x44
-#define MXC91231_SPBA_CRM_AP 0x48
-#define MXC91231_SPBA_PLL0 0x4C
-#define MXC91231_SPBA_PLL1 0x50
-#define MXC91231_SPBA_PLL2 0x54
-#define MXC91231_SPBA_GPIO4 0x58
-#define MXC91231_SPBA_SAHARA 0x5C
-
-/*
- * ROMP and AVIC
- */
-#define MXC91231_ROMP_BASE_ADDR 0x60000000
-#define MXC91231_ROMP_SIZE SZ_64K
-
-#define MXC91231_AVIC_BASE_ADDR 0x68000000
-#define MXC91231_AVIC_SIZE SZ_64K
-
-/*
- * NAND, SDRAM, WEIM, M3IF, EMI controllers
- */
-#define MXC91231_X_MEMC_BASE_ADDR 0xB8000000
-#define MXC91231_X_MEMC_SIZE SZ_64K
-
-#define MXC91231_NFC_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x0000)
-#define MXC91231_ESDCTL_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x1000)
-#define MXC91231_WEIM_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x2000)
-#define MXC91231_M3IF_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x3000)
-#define MXC91231_EMI_CTL_BASE_ADDR (MXC91231_X_MEMC_BASE_ADDR + 0x4000)
-
-/*
- * Memory regions and CS
- * CPLD is connected on CS4
- * CS5 is TP1021 or it is not connected
- * */
-#define MXC91231_FB_RAM_BASE_ADDR 0x78000000
-#define MXC91231_FB_RAM_SIZE SZ_256K
-#define MXC91231_CSD0_BASE_ADDR 0x80000000
-#define MXC91231_CSD1_BASE_ADDR 0x90000000
-#define MXC91231_CS0_BASE_ADDR 0xA0000000
-#define MXC91231_CS1_BASE_ADDR 0xA8000000
-#define MXC91231_CS2_BASE_ADDR 0xB0000000
-#define MXC91231_CS3_BASE_ADDR 0xB2000000
-#define MXC91231_CS4_BASE_ADDR 0xB4000000
-#define MXC91231_CS5_BASE_ADDR 0xB6000000
-
-/*
- * This macro defines the physical to virtual address mapping for all the
- * peripheral modules. It is used by passing in the physical address as x
- * and returning the virtual address.
- */
-#define MXC91231_IO_P2V(x) IMX_IO_P2V(x)
-#define MXC91231_IO_ADDRESS(x) IOMEM(MXC91231_IO_P2V(x))
-
-/*
- * Interrupt numbers
- */
-#define MXC91231_INT_GPIO3 0
-#define MXC91231_INT_EL1T_CI 1
-#define MXC91231_INT_EL1T_RFCI 2
-#define MXC91231_INT_EL1T_RFI 3
-#define MXC91231_INT_EL1T_MCU 4
-#define MXC91231_INT_EL1T_IPI 5
-#define MXC91231_INT_MU_GEN 6
-#define MXC91231_INT_GPIO4 7
-#define MXC91231_INT_MMC_SDHC2 8
-#define MXC91231_INT_MMC_SDHC1 9
-#define MXC91231_INT_I2C 10
-#define MXC91231_INT_SSI2 11
-#define MXC91231_INT_SSI1 12
-#define MXC91231_INT_CSPI2 13
-#define MXC91231_INT_CSPI1 14
-#define MXC91231_INT_RTIC 15
-#define MXC91231_INT_SAHARA 15
-#define MXC91231_INT_HAC 15
-#define MXC91231_INT_UART3_RX 16
-#define MXC91231_INT_UART3_TX 17
-#define MXC91231_INT_UART3_MINT 18
-#define MXC91231_INT_ECT 19
-#define MXC91231_INT_SIM_IPB 20
-#define MXC91231_INT_SIM_DATA 21
-#define MXC91231_INT_RNGA 22
-#define MXC91231_INT_DSM_AP 23
-#define MXC91231_INT_KPP 24
-#define MXC91231_INT_RTC 25
-#define MXC91231_INT_PWM 26
-#define MXC91231_INT_GEMK_AP 27
-#define MXC91231_INT_EPIT 28
-#define MXC91231_INT_GPT 29
-#define MXC91231_INT_UART2_RX 30
-#define MXC91231_INT_UART2_TX 31
-#define MXC91231_INT_UART2_MINT 32
-#define MXC91231_INT_NANDFC 33
-#define MXC91231_INT_SDMA 34
-#define MXC91231_INT_USB_WAKEUP 35
-#define MXC91231_INT_USB_SOF 36
-#define MXC91231_INT_PMU_EVTMON 37
-#define MXC91231_INT_USB_FUNC 38
-#define MXC91231_INT_USB_DMA 39
-#define MXC91231_INT_USB_CTRL 40
-#define MXC91231_INT_IPU_ERR 41
-#define MXC91231_INT_IPU_SYN 42
-#define MXC91231_INT_UART1_RX 43
-#define MXC91231_INT_UART1_TX 44
-#define MXC91231_INT_UART1_MINT 45
-#define MXC91231_INT_IIM 46
-#define MXC91231_INT_MU_RX_OR 47
-#define MXC91231_INT_MU_TX_OR 48
-#define MXC91231_INT_SCC_SCM 49
-#define MXC91231_INT_SCC_SMN 50
-#define MXC91231_INT_GPIO2 51
-#define MXC91231_INT_GPIO1 52
-#define MXC91231_INT_MQSPI1 53
-#define MXC91231_INT_MQSPI2 54
-#define MXC91231_INT_WDOG2 55
-#define MXC91231_INT_EXT_INT7 56
-#define MXC91231_INT_EXT_INT6 57
-#define MXC91231_INT_EXT_INT5 58
-#define MXC91231_INT_EXT_INT4 59
-#define MXC91231_INT_EXT_INT3 60
-#define MXC91231_INT_EXT_INT2 61
-#define MXC91231_INT_EXT_INT1 62
-#define MXC91231_INT_EXT_INT0 63
-
-#define MXC91231_MAX_INT_LINES 63
-#define MXC91231_MAX_EXT_LINES 8
-
-#endif /* __MACH_MXC91231_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/system.h b/arch/arm/plat-mxc/include/mach/system.h
index 0417da9..51f02a9 100644
--- a/arch/arm/plat-mxc/include/mach/system.h
+++ b/arch/arm/plat-mxc/include/mach/system.h
@@ -24,12 +24,6 @@
static inline void arch_idle(void)
{
-#ifdef CONFIG_ARCH_MXC91231
- if (cpu_is_mxc91231()) {
- /* Need this to set DSM low-power mode */
- mxc91231_prepare_idle();
- }
-#endif
/* fix i.MX31 errata TLSbo65953 and i.MX35 errata ENGcm09472 */
if (cpu_is_mx31() || cpu_is_mx35()) {
unsigned long reg = 0;
diff --git a/arch/arm/plat-mxc/include/mach/timex.h b/arch/arm/plat-mxc/include/mach/timex.h
index 2d96246..d61d5c7 100644
--- a/arch/arm/plat-mxc/include/mach/timex.h
+++ b/arch/arm/plat-mxc/include/mach/timex.h
@@ -26,8 +26,6 @@
#define CLOCK_TICK_RATE 16000000
#elif defined CONFIG_ARCH_MX5
#define CLOCK_TICK_RATE 8000000
-#elif defined CONFIG_ARCH_MXC91231
-#define CLOCK_TICK_RATE 13000000
#endif
#endif /* __ASM_ARCH_MXC_TIMEX_H__ */
diff --git a/arch/arm/plat-mxc/include/mach/uncompress.h b/arch/arm/plat-mxc/include/mach/uncompress.h
index 4864b0a..d85e2d1 100644
--- a/arch/arm/plat-mxc/include/mach/uncompress.h
+++ b/arch/arm/plat-mxc/include/mach/uncompress.h
@@ -21,7 +21,7 @@
#include <asm/mach-types.h>
-static unsigned long uart_base;
+unsigned long uart_base;
#define UART(x) (*(volatile unsigned long *)(uart_base + (x)))
diff --git a/arch/arm/plat-mxc/system.c b/arch/arm/plat-mxc/system.c
index 3455fc0..8024f2a 100644
--- a/arch/arm/plat-mxc/system.c
+++ b/arch/arm/plat-mxc/system.c
@@ -37,12 +37,6 @@
{
unsigned int wcr_enable;
-#ifdef CONFIG_ARCH_MXC91231
- if (cpu_is_mxc91231()) {
- mxc91231_arch_reset(mode, cmd);
- return;
- }
-#endif
#ifdef CONFIG_MACH_MX51_EFIKAMX
if (machine_is_mx51_efikamx()) {
mx51_efikamx_reset();
diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c
index 2237ff8..4b0fe28 100644
--- a/arch/arm/plat-mxc/time.c
+++ b/arch/arm/plat-mxc/time.c
@@ -54,7 +54,7 @@
#define MX2_TSTAT_CAPT (1 << 1)
#define MX2_TSTAT_COMP (1 << 0)
-/* MX31, MX35, MX25, MXC91231, MX5 */
+/* MX31, MX35, MX25, MX5 */
#define V2_TCTL_WAITEN (1 << 3) /* Wait enable mode */
#define V2_TCTL_CLK_IPG (1 << 6)
#define V2_TCTL_FRR (1 << 9)
@@ -106,56 +106,32 @@
__raw_writel(V2_TSTAT_OF1, timer_base + V2_TSTAT);
}
-static cycle_t dummy_get_cycles(struct clocksource *cs)
-{
- return 0;
-}
-
-static cycle_t mx1_2_get_cycles(struct clocksource *cs)
-{
- return __raw_readl(timer_base + MX1_2_TCN);
-}
-
-static cycle_t v2_get_cycles(struct clocksource *cs)
-{
- return __raw_readl(timer_base + V2_TCN);
-}
-
-static struct clocksource clocksource_mxc = {
- .name = "mxc_timer1",
- .rating = 200,
- .read = dummy_get_cycles,
- .mask = CLOCKSOURCE_MASK(32),
- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-};
+static void __iomem *sched_clock_reg;
static DEFINE_CLOCK_DATA(cd);
unsigned long long notrace sched_clock(void)
{
- cycle_t cyc = clocksource_mxc.read(&clocksource_mxc);
+ cycle_t cyc = sched_clock_reg ? __raw_readl(sched_clock_reg) : 0;
return cyc_to_sched_clock(&cd, cyc, (u32)~0);
}
static void notrace mxc_update_sched_clock(void)
{
- cycle_t cyc = clocksource_mxc.read(&clocksource_mxc);
+ cycle_t cyc = sched_clock_reg ? __raw_readl(sched_clock_reg) : 0;
update_sched_clock(&cd, cyc, (u32)~0);
}
static int __init mxc_clocksource_init(struct clk *timer_clk)
{
unsigned int c = clk_get_rate(timer_clk);
+ void __iomem *reg = timer_base + (timer_is_v2() ? V2_TCN : MX1_2_TCN);
- if (timer_is_v2())
- clocksource_mxc.read = v2_get_cycles;
- else
- clocksource_mxc.read = mx1_2_get_cycles;
+ sched_clock_reg = reg;
init_sched_clock(&cd, mxc_update_sched_clock, 32, c);
- clocksource_register_hz(&clocksource_mxc, c);
-
- return 0;
+ return clocksource_mmio_init(reg, "mxc_timer1", c, 200, 32,
+ clocksource_mmio_readl_up);
}
/* clock event */
diff --git a/arch/arm/plat-nomadik/Kconfig b/arch/arm/plat-nomadik/Kconfig
index 187f4e8..18296ee 100644
--- a/arch/arm/plat-nomadik/Kconfig
+++ b/arch/arm/plat-nomadik/Kconfig
@@ -5,6 +5,7 @@
config PLAT_NOMADIK
bool
depends on ARCH_NOMADIK || ARCH_U8500
+ select CLKSRC_MMIO
default y
help
Common platform code for Nomadik and other ST-Ericsson
diff --git a/arch/arm/plat-nomadik/gpio.c b/arch/arm/plat-nomadik/gpio.c
index f49748e..307b813 100644
--- a/arch/arm/plat-nomadik/gpio.c
+++ b/arch/arm/plat-nomadik/gpio.c
@@ -23,6 +23,8 @@
#include <linux/irq.h>
#include <linux/slab.h>
+#include <asm/mach/irq.h>
+
#include <plat/pincfg.h>
#include <mach/hardware.h>
#include <mach/gpio.h>
@@ -681,13 +683,7 @@
struct irq_chip *host_chip = irq_get_chip(irq);
unsigned int first_irq;
- if (host_chip->irq_mask_ack)
- host_chip->irq_mask_ack(&desc->irq_data);
- else {
- host_chip->irq_mask(&desc->irq_data);
- if (host_chip->irq_ack)
- host_chip->irq_ack(&desc->irq_data);
- }
+ chained_irq_enter(host_chip, desc);
nmk_chip = irq_get_handler_data(irq);
first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base);
@@ -698,7 +694,7 @@
status &= ~BIT(bit);
}
- host_chip->irq_unmask(&desc->irq_data);
+ chained_irq_exit(host_chip, desc);
}
static void nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
diff --git a/arch/arm/plat-nomadik/include/plat/i2c.h b/arch/arm/plat-nomadik/include/plat/i2c.h
index 1621db6..8ba70ff 100644
--- a/arch/arm/plat-nomadik/include/plat/i2c.h
+++ b/arch/arm/plat-nomadik/include/plat/i2c.h
@@ -11,8 +11,8 @@
enum i2c_freq_mode {
I2C_FREQ_MODE_STANDARD, /* up to 100 Kb/s */
I2C_FREQ_MODE_FAST, /* up to 400 Kb/s */
+ I2C_FREQ_MODE_HIGH_SPEED, /* up to 3.4 Mb/s */
I2C_FREQ_MODE_FAST_PLUS, /* up to 1 Mb/s */
- I2C_FREQ_MODE_HIGH_SPEED /* up to 3.4 Mb/s */
};
/**
@@ -24,13 +24,15 @@
* to the values of 14, 6, 2 for a 48 MHz i2c clk
* @tft: Tx FIFO Threshold in bytes
* @rft: Rx FIFO Threshold in bytes
+ * @timeout Slave response timeout(ms)
* @sm: speed mode
*/
struct nmk_i2c_controller {
unsigned long clk_freq;
unsigned short slsu;
- unsigned char tft;
- unsigned char rft;
+ unsigned char tft;
+ unsigned char rft;
+ int timeout;
enum i2c_freq_mode sm;
};
diff --git a/arch/arm/plat-nomadik/timer.c b/arch/arm/plat-nomadik/timer.c
index 4172340..ef74e157 100644
--- a/arch/arm/plat-nomadik/timer.c
+++ b/arch/arm/plat-nomadik/timer.c
@@ -26,29 +26,6 @@
void __iomem *mtu_base; /* Assigned by machine code */
/*
- * Kernel assumes that sched_clock can be called early
- * but the MTU may not yet be initialized.
- */
-static cycle_t nmdk_read_timer_dummy(struct clocksource *cs)
-{
- return 0;
-}
-
-/* clocksource: MTU decrements, so we negate the value being read. */
-static cycle_t nmdk_read_timer(struct clocksource *cs)
-{
- return -readl(mtu_base + MTU_VAL(0));
-}
-
-static struct clocksource nmdk_clksrc = {
- .name = "mtu_0",
- .rating = 200,
- .read = nmdk_read_timer_dummy,
- .mask = CLOCKSOURCE_MASK(32),
- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
-/*
* Override the global weak sched_clock symbol with this
* local implementation which uses the clocksource to get some
* better resolution when scheduling the kernel.
@@ -172,12 +149,10 @@
writel(0, mtu_base + MTU_BGLR(0));
writel(cr | MTU_CRn_ENA, mtu_base + MTU_CR(0));
- /* Now the clock source is ready */
- nmdk_clksrc.read = nmdk_read_timer;
-
- if (clocksource_register_hz(&nmdk_clksrc, rate))
+ if (clocksource_mmio_init(mtu_base + MTU_VAL(0), "mtu_0",
+ rate, 200, 32, clocksource_mmio_readl_down))
pr_err("timer: failed to initialize clock source %s\n",
- nmdk_clksrc.name);
+ "mtu_0");
init_sched_clock(&cd, nomadik_update_sched_clock, 32, rate);
diff --git a/arch/arm/plat-omap/Kconfig b/arch/arm/plat-omap/Kconfig
index cd5f993..49a4c75 100644
--- a/arch/arm/plat-omap/Kconfig
+++ b/arch/arm/plat-omap/Kconfig
@@ -12,12 +12,14 @@
config ARCH_OMAP1
bool "TI OMAP1"
select CLKDEV_LOOKUP
+ select CLKSRC_MMIO
help
"Systems based on omap7xx, omap15xx or omap16xx"
config ARCH_OMAP2PLUS
bool "TI OMAP2/3/4"
select CLKDEV_LOOKUP
+ select GENERIC_IRQ_CHIP
select OMAP_DM_TIMER
help
"Systems based on OMAP2, OMAP3 or OMAP4"
diff --git a/arch/arm/plat-omap/gpio.c b/arch/arm/plat-omap/gpio.c
index bd9e321..efb8693 100644
--- a/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@ -1137,8 +1137,9 @@
struct gpio_bank *bank;
u32 retrigger = 0;
int unmasked = 0;
+ struct irq_chip *chip = irq_desc_get_chip(desc);
- desc->irq_data.chip->irq_ack(&desc->irq_data);
+ chained_irq_enter(chip, desc);
bank = irq_get_handler_data(irq);
#ifdef CONFIG_ARCH_OMAP1
@@ -1195,7 +1196,7 @@
configured, we could unmask GPIO bank interrupt immediately */
if (!level_mask && !unmasked) {
unmasked = 1;
- desc->irq_data.chip->irq_unmask(&desc->irq_data);
+ chained_irq_exit(chip, desc);
}
isr |= retrigger;
@@ -1231,7 +1232,7 @@
interrupt */
exit:
if (!unmasked)
- desc->irq_data.chip->irq_unmask(&desc->irq_data);
+ chained_irq_exit(chip, desc);
}
static void gpio_irq_shutdown(struct irq_data *d)
diff --git a/arch/arm/plat-omap/include/plat/display.h b/arch/arm/plat-omap/include/plat/display.h
deleted file mode 100644
index 5e04ddc..0000000
--- a/arch/arm/plat-omap/include/plat/display.h
+++ /dev/null
@@ -1,591 +0,0 @@
-/*
- * linux/include/asm-arm/arch-omap/display.h
- *
- * Copyright (C) 2008 Nokia Corporation
- * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef __ASM_ARCH_OMAP_DISPLAY_H
-#define __ASM_ARCH_OMAP_DISPLAY_H
-
-#include <linux/list.h>
-#include <linux/kobject.h>
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <asm/atomic.h>
-
-#define DISPC_IRQ_FRAMEDONE (1 << 0)
-#define DISPC_IRQ_VSYNC (1 << 1)
-#define DISPC_IRQ_EVSYNC_EVEN (1 << 2)
-#define DISPC_IRQ_EVSYNC_ODD (1 << 3)
-#define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4)
-#define DISPC_IRQ_PROG_LINE_NUM (1 << 5)
-#define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6)
-#define DISPC_IRQ_GFX_END_WIN (1 << 7)
-#define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8)
-#define DISPC_IRQ_OCP_ERR (1 << 9)
-#define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10)
-#define DISPC_IRQ_VID1_END_WIN (1 << 11)
-#define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12)
-#define DISPC_IRQ_VID2_END_WIN (1 << 13)
-#define DISPC_IRQ_SYNC_LOST (1 << 14)
-#define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15)
-#define DISPC_IRQ_WAKEUP (1 << 16)
-#define DISPC_IRQ_SYNC_LOST2 (1 << 17)
-#define DISPC_IRQ_VSYNC2 (1 << 18)
-#define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21)
-#define DISPC_IRQ_FRAMEDONE2 (1 << 22)
-
-struct omap_dss_device;
-struct omap_overlay_manager;
-
-enum omap_display_type {
- OMAP_DISPLAY_TYPE_NONE = 0,
- OMAP_DISPLAY_TYPE_DPI = 1 << 0,
- OMAP_DISPLAY_TYPE_DBI = 1 << 1,
- OMAP_DISPLAY_TYPE_SDI = 1 << 2,
- OMAP_DISPLAY_TYPE_DSI = 1 << 3,
- OMAP_DISPLAY_TYPE_VENC = 1 << 4,
- OMAP_DISPLAY_TYPE_HDMI = 1 << 5,
-};
-
-enum omap_plane {
- OMAP_DSS_GFX = 0,
- OMAP_DSS_VIDEO1 = 1,
- OMAP_DSS_VIDEO2 = 2
-};
-
-enum omap_channel {
- OMAP_DSS_CHANNEL_LCD = 0,
- OMAP_DSS_CHANNEL_DIGIT = 1,
- OMAP_DSS_CHANNEL_LCD2 = 2,
-};
-
-enum omap_color_mode {
- OMAP_DSS_COLOR_CLUT1 = 1 << 0, /* BITMAP 1 */
- OMAP_DSS_COLOR_CLUT2 = 1 << 1, /* BITMAP 2 */
- OMAP_DSS_COLOR_CLUT4 = 1 << 2, /* BITMAP 4 */
- OMAP_DSS_COLOR_CLUT8 = 1 << 3, /* BITMAP 8 */
- OMAP_DSS_COLOR_RGB12U = 1 << 4, /* RGB12, 16-bit container */
- OMAP_DSS_COLOR_ARGB16 = 1 << 5, /* ARGB16 */
- OMAP_DSS_COLOR_RGB16 = 1 << 6, /* RGB16 */
- OMAP_DSS_COLOR_RGB24U = 1 << 7, /* RGB24, 32-bit container */
- OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24, 24-bit container */
- OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */
- OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */
- OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32 */
- OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32 */
- OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32 */
-};
-
-enum omap_lcd_display_type {
- OMAP_DSS_LCD_DISPLAY_STN,
- OMAP_DSS_LCD_DISPLAY_TFT,
-};
-
-enum omap_dss_load_mode {
- OMAP_DSS_LOAD_CLUT_AND_FRAME = 0,
- OMAP_DSS_LOAD_CLUT_ONLY = 1,
- OMAP_DSS_LOAD_FRAME_ONLY = 2,
- OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3,
-};
-
-enum omap_dss_trans_key_type {
- OMAP_DSS_COLOR_KEY_GFX_DST = 0,
- OMAP_DSS_COLOR_KEY_VID_SRC = 1,
-};
-
-enum omap_rfbi_te_mode {
- OMAP_DSS_RFBI_TE_MODE_1 = 1,
- OMAP_DSS_RFBI_TE_MODE_2 = 2,
-};
-
-enum omap_panel_config {
- OMAP_DSS_LCD_IVS = 1<<0,
- OMAP_DSS_LCD_IHS = 1<<1,
- OMAP_DSS_LCD_IPC = 1<<2,
- OMAP_DSS_LCD_IEO = 1<<3,
- OMAP_DSS_LCD_RF = 1<<4,
- OMAP_DSS_LCD_ONOFF = 1<<5,
-
- OMAP_DSS_LCD_TFT = 1<<20,
-};
-
-enum omap_dss_venc_type {
- OMAP_DSS_VENC_TYPE_COMPOSITE,
- OMAP_DSS_VENC_TYPE_SVIDEO,
-};
-
-enum omap_display_caps {
- OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0,
- OMAP_DSS_DISPLAY_CAP_TEAR_ELIM = 1 << 1,
-};
-
-enum omap_dss_update_mode {
- OMAP_DSS_UPDATE_DISABLED = 0,
- OMAP_DSS_UPDATE_AUTO,
- OMAP_DSS_UPDATE_MANUAL,
-};
-
-enum omap_dss_display_state {
- OMAP_DSS_DISPLAY_DISABLED = 0,
- OMAP_DSS_DISPLAY_ACTIVE,
- OMAP_DSS_DISPLAY_SUSPENDED,
-};
-
-/* XXX perhaps this should be removed */
-enum omap_dss_overlay_managers {
- OMAP_DSS_OVL_MGR_LCD,
- OMAP_DSS_OVL_MGR_TV,
- OMAP_DSS_OVL_MGR_LCD2,
-};
-
-enum omap_dss_rotation_type {
- OMAP_DSS_ROT_DMA = 0,
- OMAP_DSS_ROT_VRFB = 1,
-};
-
-/* clockwise rotation angle */
-enum omap_dss_rotation_angle {
- OMAP_DSS_ROT_0 = 0,
- OMAP_DSS_ROT_90 = 1,
- OMAP_DSS_ROT_180 = 2,
- OMAP_DSS_ROT_270 = 3,
-};
-
-enum omap_overlay_caps {
- OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
- OMAP_DSS_OVL_CAP_DISPC = 1 << 1,
-};
-
-enum omap_overlay_manager_caps {
- OMAP_DSS_OVL_MGR_CAP_DISPC = 1 << 0,
-};
-
-/* RFBI */
-
-struct rfbi_timings {
- int cs_on_time;
- int cs_off_time;
- int we_on_time;
- int we_off_time;
- int re_on_time;
- int re_off_time;
- int we_cycle_time;
- int re_cycle_time;
- int cs_pulse_width;
- int access_time;
-
- int clk_div;
-
- u32 tim[5]; /* set by rfbi_convert_timings() */
-
- int converted;
-};
-
-void omap_rfbi_write_command(const void *buf, u32 len);
-void omap_rfbi_read_data(void *buf, u32 len);
-void omap_rfbi_write_data(const void *buf, u32 len);
-void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
- u16 x, u16 y,
- u16 w, u16 h);
-int omap_rfbi_enable_te(bool enable, unsigned line);
-int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
- unsigned hs_pulse_time, unsigned vs_pulse_time,
- int hs_pol_inv, int vs_pol_inv, int extif_div);
-
-/* DSI */
-void dsi_bus_lock(void);
-void dsi_bus_unlock(void);
-int dsi_vc_dcs_write(int channel, u8 *data, int len);
-int dsi_vc_dcs_write_0(int channel, u8 dcs_cmd);
-int dsi_vc_dcs_write_1(int channel, u8 dcs_cmd, u8 param);
-int dsi_vc_dcs_write_nosync(int channel, u8 *data, int len);
-int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen);
-int dsi_vc_dcs_read_1(int channel, u8 dcs_cmd, u8 *data);
-int dsi_vc_dcs_read_2(int channel, u8 dcs_cmd, u8 *data1, u8 *data2);
-int dsi_vc_set_max_rx_packet_size(int channel, u16 len);
-int dsi_vc_send_null(int channel);
-int dsi_vc_send_bta_sync(int channel);
-
-/* Board specific data */
-struct omap_dss_board_info {
- int (*get_last_off_on_transaction_id)(struct device *dev);
- int num_devices;
- struct omap_dss_device **devices;
- struct omap_dss_device *default_device;
-};
-
-#if defined(CONFIG_OMAP2_DSS_MODULE) || defined(CONFIG_OMAP2_DSS)
-/* Init with the board info */
-extern int omap_display_init(struct omap_dss_board_info *board_data);
-#else
-static inline int omap_display_init(struct omap_dss_board_info *board_data)
-{
- return 0;
-}
-#endif
-
-struct omap_display_platform_data {
- struct omap_dss_board_info *board_data;
- /* TODO: Additional members to be added when PM is considered */
-
- bool (*opt_clock_available)(const char *clk_role);
-};
-
-struct omap_video_timings {
- /* Unit: pixels */
- u16 x_res;
- /* Unit: pixels */
- u16 y_res;
- /* Unit: KHz */
- u32 pixel_clock;
- /* Unit: pixel clocks */
- u16 hsw; /* Horizontal synchronization pulse width */
- /* Unit: pixel clocks */
- u16 hfp; /* Horizontal front porch */
- /* Unit: pixel clocks */
- u16 hbp; /* Horizontal back porch */
- /* Unit: line clocks */
- u16 vsw; /* Vertical synchronization pulse width */
- /* Unit: line clocks */
- u16 vfp; /* Vertical front porch */
- /* Unit: line clocks */
- u16 vbp; /* Vertical back porch */
-};
-
-#ifdef CONFIG_OMAP2_DSS_VENC
-/* Hardcoded timings for tv modes. Venc only uses these to
- * identify the mode, and does not actually use the configs
- * itself. However, the configs should be something that
- * a normal monitor can also show */
-extern const struct omap_video_timings omap_dss_pal_timings;
-extern const struct omap_video_timings omap_dss_ntsc_timings;
-#endif
-
-struct omap_overlay_info {
- bool enabled;
-
- u32 paddr;
- void __iomem *vaddr;
- u16 screen_width;
- u16 width;
- u16 height;
- enum omap_color_mode color_mode;
- u8 rotation;
- enum omap_dss_rotation_type rotation_type;
- bool mirror;
-
- u16 pos_x;
- u16 pos_y;
- u16 out_width; /* if 0, out_width == width */
- u16 out_height; /* if 0, out_height == height */
- u8 global_alpha;
- u8 pre_mult_alpha;
-};
-
-struct omap_overlay {
- struct kobject kobj;
- struct list_head list;
-
- /* static fields */
- const char *name;
- int id;
- enum omap_color_mode supported_modes;
- enum omap_overlay_caps caps;
-
- /* dynamic fields */
- struct omap_overlay_manager *manager;
- struct omap_overlay_info info;
-
- /* if true, info has been changed, but not applied() yet */
- bool info_dirty;
-
- int (*set_manager)(struct omap_overlay *ovl,
- struct omap_overlay_manager *mgr);
- int (*unset_manager)(struct omap_overlay *ovl);
-
- int (*set_overlay_info)(struct omap_overlay *ovl,
- struct omap_overlay_info *info);
- void (*get_overlay_info)(struct omap_overlay *ovl,
- struct omap_overlay_info *info);
-
- int (*wait_for_go)(struct omap_overlay *ovl);
-};
-
-struct omap_overlay_manager_info {
- u32 default_color;
-
- enum omap_dss_trans_key_type trans_key_type;
- u32 trans_key;
- bool trans_enabled;
-
- bool alpha_enabled;
-};
-
-struct omap_overlay_manager {
- struct kobject kobj;
- struct list_head list;
-
- /* static fields */
- const char *name;
- int id;
- enum omap_overlay_manager_caps caps;
- int num_overlays;
- struct omap_overlay **overlays;
- enum omap_display_type supported_displays;
-
- /* dynamic fields */
- struct omap_dss_device *device;
- struct omap_overlay_manager_info info;
-
- bool device_changed;
- /* if true, info has been changed but not applied() yet */
- bool info_dirty;
-
- int (*set_device)(struct omap_overlay_manager *mgr,
- struct omap_dss_device *dssdev);
- int (*unset_device)(struct omap_overlay_manager *mgr);
-
- int (*set_manager_info)(struct omap_overlay_manager *mgr,
- struct omap_overlay_manager_info *info);
- void (*get_manager_info)(struct omap_overlay_manager *mgr,
- struct omap_overlay_manager_info *info);
-
- int (*apply)(struct omap_overlay_manager *mgr);
- int (*wait_for_go)(struct omap_overlay_manager *mgr);
- int (*wait_for_vsync)(struct omap_overlay_manager *mgr);
-
- int (*enable)(struct omap_overlay_manager *mgr);
- int (*disable)(struct omap_overlay_manager *mgr);
-};
-
-struct omap_dss_device {
- struct device dev;
-
- enum omap_display_type type;
-
- enum omap_channel channel;
-
- union {
- struct {
- u8 data_lines;
- } dpi;
-
- struct {
- u8 channel;
- u8 data_lines;
- } rfbi;
-
- struct {
- u8 datapairs;
- } sdi;
-
- struct {
- u8 clk_lane;
- u8 clk_pol;
- u8 data1_lane;
- u8 data1_pol;
- u8 data2_lane;
- u8 data2_pol;
-
- struct {
- u16 regn;
- u16 regm;
- u16 regm_dispc;
- u16 regm_dsi;
-
- u16 lp_clk_div;
-
- u16 lck_div;
- u16 pck_div;
- } div;
-
- bool ext_te;
- u8 ext_te_gpio;
- } dsi;
-
- struct {
- enum omap_dss_venc_type type;
- bool invert_polarity;
- } venc;
- } phy;
-
- struct {
- struct omap_video_timings timings;
-
- int acbi; /* ac-bias pin transitions per interrupt */
- /* Unit: line clocks */
- int acb; /* ac-bias pin frequency */
-
- enum omap_panel_config config;
- } panel;
-
- struct {
- u8 pixel_size;
- struct rfbi_timings rfbi_timings;
- } ctrl;
-
- int reset_gpio;
-
- int max_backlight_level;
-
- const char *name;
-
- /* used to match device to driver */
- const char *driver_name;
-
- void *data;
-
- struct omap_dss_driver *driver;
-
- /* helper variable for driver suspend/resume */
- bool activate_after_resume;
-
- enum omap_display_caps caps;
-
- struct omap_overlay_manager *manager;
-
- enum omap_dss_display_state state;
-
- /* platform specific */
- int (*platform_enable)(struct omap_dss_device *dssdev);
- void (*platform_disable)(struct omap_dss_device *dssdev);
- int (*set_backlight)(struct omap_dss_device *dssdev, int level);
- int (*get_backlight)(struct omap_dss_device *dssdev);
-};
-
-struct omap_dss_driver {
- struct device_driver driver;
-
- int (*probe)(struct omap_dss_device *);
- void (*remove)(struct omap_dss_device *);
-
- int (*enable)(struct omap_dss_device *display);
- void (*disable)(struct omap_dss_device *display);
- int (*suspend)(struct omap_dss_device *display);
- int (*resume)(struct omap_dss_device *display);
- int (*run_test)(struct omap_dss_device *display, int test);
-
- int (*set_update_mode)(struct omap_dss_device *dssdev,
- enum omap_dss_update_mode);
- enum omap_dss_update_mode (*get_update_mode)(
- struct omap_dss_device *dssdev);
-
- int (*update)(struct omap_dss_device *dssdev,
- u16 x, u16 y, u16 w, u16 h);
- int (*sync)(struct omap_dss_device *dssdev);
-
- int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
- int (*get_te)(struct omap_dss_device *dssdev);
-
- u8 (*get_rotate)(struct omap_dss_device *dssdev);
- int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
-
- bool (*get_mirror)(struct omap_dss_device *dssdev);
- int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);
-
- int (*memory_read)(struct omap_dss_device *dssdev,
- void *buf, size_t size,
- u16 x, u16 y, u16 w, u16 h);
-
- void (*get_resolution)(struct omap_dss_device *dssdev,
- u16 *xres, u16 *yres);
- int (*get_recommended_bpp)(struct omap_dss_device *dssdev);
-
- int (*check_timings)(struct omap_dss_device *dssdev,
- struct omap_video_timings *timings);
- void (*set_timings)(struct omap_dss_device *dssdev,
- struct omap_video_timings *timings);
- void (*get_timings)(struct omap_dss_device *dssdev,
- struct omap_video_timings *timings);
-
- int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
- u32 (*get_wss)(struct omap_dss_device *dssdev);
-};
-
-int omap_dss_register_driver(struct omap_dss_driver *);
-void omap_dss_unregister_driver(struct omap_dss_driver *);
-
-int omap_dss_register_device(struct omap_dss_device *);
-void omap_dss_unregister_device(struct omap_dss_device *);
-
-void omap_dss_get_device(struct omap_dss_device *dssdev);
-void omap_dss_put_device(struct omap_dss_device *dssdev);
-#define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
-struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from);
-struct omap_dss_device *omap_dss_find_device(void *data,
- int (*match)(struct omap_dss_device *dssdev, void *data));
-
-int omap_dss_start_device(struct omap_dss_device *dssdev);
-void omap_dss_stop_device(struct omap_dss_device *dssdev);
-
-int omap_dss_get_num_overlay_managers(void);
-struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
-
-int omap_dss_get_num_overlays(void);
-struct omap_overlay *omap_dss_get_overlay(int num);
-
-void omapdss_default_get_resolution(struct omap_dss_device *dssdev,
- u16 *xres, u16 *yres);
-int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev);
-
-typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
-int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
-int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
-
-int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout);
-int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
- unsigned long timeout);
-
-#define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver)
-#define to_dss_device(x) container_of((x), struct omap_dss_device, dev)
-
-void omapdss_dsi_vc_enable_hs(int channel, bool enable);
-int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable);
-
-int omap_dsi_prepare_update(struct omap_dss_device *dssdev,
- u16 *x, u16 *y, u16 *w, u16 *h,
- bool enlarge_update_area);
-int omap_dsi_update(struct omap_dss_device *dssdev,
- int channel,
- u16 x, u16 y, u16 w, u16 h,
- void (*callback)(int, void *), void *data);
-int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel);
-int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id);
-void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel);
-
-int omapdss_dsi_display_enable(struct omap_dss_device *dssdev);
-void omapdss_dsi_display_disable(struct omap_dss_device *dssdev);
-
-int omapdss_dpi_display_enable(struct omap_dss_device *dssdev);
-void omapdss_dpi_display_disable(struct omap_dss_device *dssdev);
-void dpi_set_timings(struct omap_dss_device *dssdev,
- struct omap_video_timings *timings);
-int dpi_check_timings(struct omap_dss_device *dssdev,
- struct omap_video_timings *timings);
-
-int omapdss_sdi_display_enable(struct omap_dss_device *dssdev);
-void omapdss_sdi_display_disable(struct omap_dss_device *dssdev);
-
-int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev);
-void omapdss_rfbi_display_disable(struct omap_dss_device *dssdev);
-int omap_rfbi_prepare_update(struct omap_dss_device *dssdev,
- u16 *x, u16 *y, u16 *w, u16 *h);
-int omap_rfbi_update(struct omap_dss_device *dssdev,
- u16 x, u16 y, u16 w, u16 h,
- void (*callback)(void *), void *data);
-
-#endif
diff --git a/arch/arm/plat-omap/include/plat/flash.h b/arch/arm/plat-omap/include/plat/flash.h
index 3e63270..3083195 100644
--- a/arch/arm/plat-omap/include/plat/flash.h
+++ b/arch/arm/plat-omap/include/plat/flash.h
@@ -11,6 +11,6 @@
#include <linux/mtd/map.h>
-extern void omap1_set_vpp(struct map_info *map, int enable);
+extern void omap1_set_vpp(struct platform_device *pdev, int enable);
#endif
diff --git a/arch/arm/plat-omap/include/plat/nokia-dsi-panel.h b/arch/arm/plat-omap/include/plat/nokia-dsi-panel.h
deleted file mode 100644
index 01ab657..0000000
--- a/arch/arm/plat-omap/include/plat/nokia-dsi-panel.h
+++ /dev/null
@@ -1,31 +0,0 @@
-#ifndef __ARCH_ARM_PLAT_OMAP_NOKIA_DSI_PANEL_H
-#define __ARCH_ARM_PLAT_OMAP_NOKIA_DSI_PANEL_H
-
-#include "display.h"
-
-/**
- * struct nokia_dsi_panel_data - Nokia DSI panel driver configuration
- * @name: panel name
- * @use_ext_te: use external TE
- * @ext_te_gpio: external TE GPIO
- * @use_esd_check: perform ESD checks
- * @max_backlight_level: maximum backlight level
- * @set_backlight: pointer to backlight set function
- * @get_backlight: pointer to backlight get function
- */
-struct nokia_dsi_panel_data {
- const char *name;
-
- int reset_gpio;
-
- bool use_ext_te;
- int ext_te_gpio;
-
- bool use_esd_check;
-
- int max_backlight_level;
- int (*set_backlight)(struct omap_dss_device *dssdev, int level);
- int (*get_backlight)(struct omap_dss_device *dssdev);
-};
-
-#endif /* __ARCH_ARM_PLAT_OMAP_NOKIA_DSI_PANEL_H */
diff --git a/arch/arm/plat-omap/include/plat/panel-generic-dpi.h b/arch/arm/plat-omap/include/plat/panel-generic-dpi.h
deleted file mode 100644
index 7906197..0000000
--- a/arch/arm/plat-omap/include/plat/panel-generic-dpi.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * Header for generic DPI panel driver
- *
- * Copyright (C) 2010 Canonical Ltd.
- * Author: Bryan Wu <bryan.wu@canonical.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License version 2 as published by
- * the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program. If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef __ARCH_ARM_PLAT_OMAP_PANEL_GENERIC_DPI_H
-#define __ARCH_ARM_PLAT_OMAP_PANEL_GENERIC_DPI_H
-
-#include "display.h"
-
-/**
- * struct panel_generic_dpi_data - panel driver configuration data
- * @name: panel name
- * @platform_enable: platform specific panel enable function
- * @platform_disable: platform specific panel disable function
- */
-struct panel_generic_dpi_data {
- const char *name;
- int (*platform_enable)(struct omap_dss_device *dssdev);
- void (*platform_disable)(struct omap_dss_device *dssdev);
-};
-
-#endif /* __ARCH_ARM_PLAT_OMAP_PANEL_GENERIC_DPI_H */
diff --git a/arch/arm/plat-omap/include/plat/smp.h b/arch/arm/plat-omap/include/plat/smp.h
deleted file mode 100644
index 7a10257..0000000
--- a/arch/arm/plat-omap/include/plat/smp.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * OMAP4 machine specific smp.h
- *
- * Copyright (C) 2009 Texas Instruments, Inc.
- *
- * Author:
- * Santosh Shilimkar <santosh.shilimkar@ti.com>
- *
- * Interface functions needed for the SMP. This file is based on arm
- * realview smp platform.
- * Copyright (c) 2003 ARM Limited.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-#ifndef OMAP_ARCH_SMP_H
-#define OMAP_ARCH_SMP_H
-
-#include <asm/hardware/gic.h>
-
-/* Needed for secondary core boot */
-extern void omap_secondary_startup(void);
-extern u32 omap_modify_auxcoreboot0(u32 set_mask, u32 clear_mask);
-extern void omap_auxcoreboot_addr(u32 cpu_addr);
-extern u32 omap_read_auxcoreboot0(void);
-
-/*
- * We use Soft IRQ1 as the IPI
- */
-static inline void smp_cross_call(const struct cpumask *mask, int ipi)
-{
- gic_raise_softirq(mask, ipi);
-}
-
-#endif
diff --git a/arch/arm/plat-omap/include/plat/uncompress.h b/arch/arm/plat-omap/include/plat/uncompress.h
index 30b891c..565d266 100644
--- a/arch/arm/plat-omap/include/plat/uncompress.h
+++ b/arch/arm/plat-omap/include/plat/uncompress.h
@@ -27,8 +27,8 @@
#define MDR1_MODE_MASK 0x07
-static volatile u8 *uart_base;
-static int uart_shift;
+volatile u8 *uart_base;
+int uart_shift;
/*
* Store the DEBUG_LL uart number into memory.
diff --git a/arch/arm/plat-orion/Makefile b/arch/arm/plat-orion/Makefile
index 56021a7..95a5fc5 100644
--- a/arch/arm/plat-orion/Makefile
+++ b/arch/arm/plat-orion/Makefile
@@ -2,7 +2,7 @@
# Makefile for the linux kernel.
#
-obj-y := irq.o pcie.o time.o
+obj-y := irq.o pcie.o time.o common.o mpp.o
obj-m :=
obj-n :=
obj- :=
diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c
new file mode 100644
index 0000000..9e5451b
--- /dev/null
+++ b/arch/arm/plat-orion/common.c
@@ -0,0 +1,957 @@
+/*
+ * arch/arm/plat-orion/common.c
+ *
+ * Marvell Orion SoC common setup code used by multiple mach-/common.c
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/serial_8250.h>
+#include <linux/mbus.h>
+#include <linux/ata_platform.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/mv643xx_i2c.h>
+#include <net/dsa.h>
+#include <linux/spi/orion_spi.h>
+#include <plat/orion_wdt.h>
+#include <plat/mv_xor.h>
+#include <plat/ehci-orion.h>
+
+/* Fill in the resources structure and link it into the platform
+ device structure. There is always a memory region, and nearly
+ always an interrupt.*/
+static void fill_resources(struct platform_device *device,
+ struct resource *resources,
+ resource_size_t mapbase,
+ resource_size_t size,
+ unsigned int irq)
+{
+ device->resource = resources;
+ device->num_resources = 1;
+ resources[0].flags = IORESOURCE_MEM;
+ resources[0].start = mapbase;
+ resources[0].end = mapbase + size;
+
+ if (irq != NO_IRQ) {
+ device->num_resources++;
+ resources[1].flags = IORESOURCE_IRQ;
+ resources[1].start = irq;
+ resources[1].end = irq;
+ }
+}
+
+/*****************************************************************************
+ * UART
+ ****************************************************************************/
+static void __init uart_complete(
+ struct platform_device *orion_uart,
+ struct plat_serial8250_port *data,
+ struct resource *resources,
+ unsigned int membase,
+ resource_size_t mapbase,
+ unsigned int irq,
+ unsigned int uartclk)
+{
+ data->mapbase = mapbase;
+ data->membase = (void __iomem *)membase;
+ data->irq = irq;
+ data->uartclk = uartclk;
+ orion_uart->dev.platform_data = data;
+
+ fill_resources(orion_uart, resources, mapbase, 0xff, irq);
+ platform_device_register(orion_uart);
+}
+
+/*****************************************************************************
+ * UART0
+ ****************************************************************************/
+static struct plat_serial8250_port orion_uart0_data[] = {
+ {
+ .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
+ .iotype = UPIO_MEM,
+ .regshift = 2,
+ }, {
+ },
+};
+
+static struct resource orion_uart0_resources[2];
+
+static struct platform_device orion_uart0 = {
+ .name = "serial8250",
+ .id = PLAT8250_DEV_PLATFORM,
+};
+
+void __init orion_uart0_init(unsigned int membase,
+ resource_size_t mapbase,
+ unsigned int irq,
+ unsigned int uartclk)
+{
+ uart_complete(&orion_uart0, orion_uart0_data, orion_uart0_resources,
+ membase, mapbase, irq, uartclk);
+}
+
+/*****************************************************************************
+ * UART1
+ ****************************************************************************/
+static struct plat_serial8250_port orion_uart1_data[] = {
+ {
+ .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
+ .iotype = UPIO_MEM,
+ .regshift = 2,
+ }, {
+ },
+};
+
+static struct resource orion_uart1_resources[2];
+
+static struct platform_device orion_uart1 = {
+ .name = "serial8250",
+ .id = PLAT8250_DEV_PLATFORM1,
+};
+
+void __init orion_uart1_init(unsigned int membase,
+ resource_size_t mapbase,
+ unsigned int irq,
+ unsigned int uartclk)
+{
+ uart_complete(&orion_uart1, orion_uart1_data, orion_uart1_resources,
+ membase, mapbase, irq, uartclk);
+}
+
+/*****************************************************************************
+ * UART2
+ ****************************************************************************/
+static struct plat_serial8250_port orion_uart2_data[] = {
+ {
+ .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
+ .iotype = UPIO_MEM,
+ .regshift = 2,
+ }, {
+ },
+};
+
+static struct resource orion_uart2_resources[2];
+
+static struct platform_device orion_uart2 = {
+ .name = "serial8250",
+ .id = PLAT8250_DEV_PLATFORM2,
+};
+
+void __init orion_uart2_init(unsigned int membase,
+ resource_size_t mapbase,
+ unsigned int irq,
+ unsigned int uartclk)
+{
+ uart_complete(&orion_uart2, orion_uart2_data, orion_uart2_resources,
+ membase, mapbase, irq, uartclk);
+}
+
+/*****************************************************************************
+ * UART3
+ ****************************************************************************/
+static struct plat_serial8250_port orion_uart3_data[] = {
+ {
+ .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
+ .iotype = UPIO_MEM,
+ .regshift = 2,
+ }, {
+ },
+};
+
+static struct resource orion_uart3_resources[2];
+
+static struct platform_device orion_uart3 = {
+ .name = "serial8250",
+ .id = 3,
+};
+
+void __init orion_uart3_init(unsigned int membase,
+ resource_size_t mapbase,
+ unsigned int irq,
+ unsigned int uartclk)
+{
+ uart_complete(&orion_uart3, orion_uart3_data, orion_uart3_resources,
+ membase, mapbase, irq, uartclk);
+}
+
+/*****************************************************************************
+ * SoC RTC
+ ****************************************************************************/
+static struct resource orion_rtc_resource[2];
+
+void __init orion_rtc_init(unsigned long mapbase,
+ unsigned long irq)
+{
+ orion_rtc_resource[0].start = mapbase;
+ orion_rtc_resource[0].end = mapbase + SZ_32 - 1;
+ orion_rtc_resource[0].flags = IORESOURCE_MEM;
+ orion_rtc_resource[1].start = irq;
+ orion_rtc_resource[1].end = irq;
+ orion_rtc_resource[1].flags = IORESOURCE_IRQ;
+
+ platform_device_register_simple("rtc-mv", -1, orion_rtc_resource, 2);
+}
+
+/*****************************************************************************
+ * GE
+ ****************************************************************************/
+static __init void ge_complete(
+ struct mv643xx_eth_shared_platform_data *orion_ge_shared_data,
+ struct mbus_dram_target_info *mbus_dram_info, int tclk,
+ struct resource *orion_ge_resource, unsigned long irq,
+ struct platform_device *orion_ge_shared,
+ struct mv643xx_eth_platform_data *eth_data,
+ struct platform_device *orion_ge)
+{
+ orion_ge_shared_data->dram = mbus_dram_info;
+ orion_ge_shared_data->t_clk = tclk;
+ orion_ge_resource->start = irq;
+ orion_ge_resource->end = irq;
+ eth_data->shared = orion_ge_shared;
+ orion_ge->dev.platform_data = eth_data;
+
+ platform_device_register(orion_ge_shared);
+ platform_device_register(orion_ge);
+}
+
+/*****************************************************************************
+ * GE00
+ ****************************************************************************/
+struct mv643xx_eth_shared_platform_data orion_ge00_shared_data;
+
+static struct resource orion_ge00_shared_resources[] = {
+ {
+ .name = "ge00 base",
+ }, {
+ .name = "ge00 err irq",
+ },
+};
+
+static struct platform_device orion_ge00_shared = {
+ .name = MV643XX_ETH_SHARED_NAME,
+ .id = 0,
+ .dev = {
+ .platform_data = &orion_ge00_shared_data,
+ },
+};
+
+static struct resource orion_ge00_resources[] = {
+ {
+ .name = "ge00 irq",
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device orion_ge00 = {
+ .name = MV643XX_ETH_NAME,
+ .id = 0,
+ .num_resources = 1,
+ .resource = orion_ge00_resources,
+ .dev = {
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+};
+
+void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data,
+ struct mbus_dram_target_info *mbus_dram_info,
+ unsigned long mapbase,
+ unsigned long irq,
+ unsigned long irq_err,
+ int tclk)
+{
+ fill_resources(&orion_ge00_shared, orion_ge00_shared_resources,
+ mapbase + 0x2000, SZ_16K - 1, irq_err);
+ ge_complete(&orion_ge00_shared_data, mbus_dram_info, tclk,
+ orion_ge00_resources, irq, &orion_ge00_shared,
+ eth_data, &orion_ge00);
+}
+
+/*****************************************************************************
+ * GE01
+ ****************************************************************************/
+struct mv643xx_eth_shared_platform_data orion_ge01_shared_data = {
+ .shared_smi = &orion_ge00_shared,
+};
+
+static struct resource orion_ge01_shared_resources[] = {
+ {
+ .name = "ge01 base",
+ }, {
+ .name = "ge01 err irq",
+ },
+};
+
+static struct platform_device orion_ge01_shared = {
+ .name = MV643XX_ETH_SHARED_NAME,
+ .id = 1,
+ .dev = {
+ .platform_data = &orion_ge01_shared_data,
+ },
+};
+
+static struct resource orion_ge01_resources[] = {
+ {
+ .name = "ge01 irq",
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device orion_ge01 = {
+ .name = MV643XX_ETH_NAME,
+ .id = 1,
+ .num_resources = 1,
+ .resource = orion_ge01_resources,
+ .dev = {
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+};
+
+void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data,
+ struct mbus_dram_target_info *mbus_dram_info,
+ unsigned long mapbase,
+ unsigned long irq,
+ unsigned long irq_err,
+ int tclk)
+{
+ fill_resources(&orion_ge01_shared, orion_ge01_shared_resources,
+ mapbase + 0x2000, SZ_16K - 1, irq_err);
+ ge_complete(&orion_ge01_shared_data, mbus_dram_info, tclk,
+ orion_ge01_resources, irq, &orion_ge01_shared,
+ eth_data, &orion_ge01);
+}
+
+/*****************************************************************************
+ * GE10
+ ****************************************************************************/
+struct mv643xx_eth_shared_platform_data orion_ge10_shared_data = {
+ .shared_smi = &orion_ge00_shared,
+};
+
+static struct resource orion_ge10_shared_resources[] = {
+ {
+ .name = "ge10 base",
+ }, {
+ .name = "ge10 err irq",
+ },
+};
+
+static struct platform_device orion_ge10_shared = {
+ .name = MV643XX_ETH_SHARED_NAME,
+ .id = 1,
+ .dev = {
+ .platform_data = &orion_ge10_shared_data,
+ },
+};
+
+static struct resource orion_ge10_resources[] = {
+ {
+ .name = "ge10 irq",
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device orion_ge10 = {
+ .name = MV643XX_ETH_NAME,
+ .id = 1,
+ .num_resources = 2,
+ .resource = orion_ge10_resources,
+ .dev = {
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+};
+
+void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data,
+ struct mbus_dram_target_info *mbus_dram_info,
+ unsigned long mapbase,
+ unsigned long irq,
+ unsigned long irq_err,
+ int tclk)
+{
+ fill_resources(&orion_ge10_shared, orion_ge10_shared_resources,
+ mapbase + 0x2000, SZ_16K - 1, irq_err);
+ ge_complete(&orion_ge10_shared_data, mbus_dram_info, tclk,
+ orion_ge10_resources, irq, &orion_ge10_shared,
+ eth_data, &orion_ge10);
+}
+
+/*****************************************************************************
+ * GE11
+ ****************************************************************************/
+struct mv643xx_eth_shared_platform_data orion_ge11_shared_data = {
+ .shared_smi = &orion_ge00_shared,
+};
+
+static struct resource orion_ge11_shared_resources[] = {
+ {
+ .name = "ge11 base",
+ }, {
+ .name = "ge11 err irq",
+ },
+};
+
+static struct platform_device orion_ge11_shared = {
+ .name = MV643XX_ETH_SHARED_NAME,
+ .id = 1,
+ .dev = {
+ .platform_data = &orion_ge11_shared_data,
+ },
+};
+
+static struct resource orion_ge11_resources[] = {
+ {
+ .name = "ge11 irq",
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device orion_ge11 = {
+ .name = MV643XX_ETH_NAME,
+ .id = 1,
+ .num_resources = 2,
+ .resource = orion_ge11_resources,
+ .dev = {
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+};
+
+void __init orion_ge11_init(struct mv643xx_eth_platform_data *eth_data,
+ struct mbus_dram_target_info *mbus_dram_info,
+ unsigned long mapbase,
+ unsigned long irq,
+ unsigned long irq_err,
+ int tclk)
+{
+ fill_resources(&orion_ge11_shared, orion_ge11_shared_resources,
+ mapbase + 0x2000, SZ_16K - 1, irq_err);
+ ge_complete(&orion_ge11_shared_data, mbus_dram_info, tclk,
+ orion_ge11_resources, irq, &orion_ge11_shared,
+ eth_data, &orion_ge11);
+}
+
+/*****************************************************************************
+ * Ethernet switch
+ ****************************************************************************/
+static struct resource orion_switch_resources[] = {
+ {
+ .start = 0,
+ .end = 0,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct platform_device orion_switch_device = {
+ .name = "dsa",
+ .id = 0,
+ .num_resources = 0,
+ .resource = orion_switch_resources,
+};
+
+void __init orion_ge00_switch_init(struct dsa_platform_data *d, int irq)
+{
+ int i;
+
+ if (irq != NO_IRQ) {
+ orion_switch_resources[0].start = irq;
+ orion_switch_resources[0].end = irq;
+ orion_switch_device.num_resources = 1;
+ }
+
+ d->netdev = &orion_ge00.dev;
+ for (i = 0; i < d->nr_chips; i++)
+ d->chip[i].mii_bus = &orion_ge00_shared.dev;
+ orion_switch_device.dev.platform_data = d;
+
+ platform_device_register(&orion_switch_device);
+}
+
+/*****************************************************************************
+ * I2C
+ ****************************************************************************/
+static struct mv64xxx_i2c_pdata orion_i2c_pdata = {
+ .freq_n = 3,
+ .timeout = 1000, /* Default timeout of 1 second */
+};
+
+static struct resource orion_i2c_resources[2];
+
+static struct platform_device orion_i2c = {
+ .name = MV64XXX_I2C_CTLR_NAME,
+ .id = 0,
+ .dev = {
+ .platform_data = &orion_i2c_pdata,
+ },
+};
+
+static struct mv64xxx_i2c_pdata orion_i2c_1_pdata = {
+ .freq_n = 3,
+ .timeout = 1000, /* Default timeout of 1 second */
+};
+
+static struct resource orion_i2c_1_resources[2];
+
+static struct platform_device orion_i2c_1 = {
+ .name = MV64XXX_I2C_CTLR_NAME,
+ .id = 1,
+ .dev = {
+ .platform_data = &orion_i2c_1_pdata,
+ },
+};
+
+void __init orion_i2c_init(unsigned long mapbase,
+ unsigned long irq,
+ unsigned long freq_m)
+{
+ orion_i2c_pdata.freq_m = freq_m;
+ fill_resources(&orion_i2c, orion_i2c_resources, mapbase,
+ SZ_32 - 1, irq);
+ platform_device_register(&orion_i2c);
+}
+
+void __init orion_i2c_1_init(unsigned long mapbase,
+ unsigned long irq,
+ unsigned long freq_m)
+{
+ orion_i2c_1_pdata.freq_m = freq_m;
+ fill_resources(&orion_i2c_1, orion_i2c_1_resources, mapbase,
+ SZ_32 - 1, irq);
+ platform_device_register(&orion_i2c_1);
+}
+
+/*****************************************************************************
+ * SPI
+ ****************************************************************************/
+static struct orion_spi_info orion_spi_plat_data;
+static struct resource orion_spi_resources;
+
+static struct platform_device orion_spi = {
+ .name = "orion_spi",
+ .id = 0,
+ .dev = {
+ .platform_data = &orion_spi_plat_data,
+ },
+};
+
+static struct orion_spi_info orion_spi_1_plat_data;
+static struct resource orion_spi_1_resources;
+
+static struct platform_device orion_spi_1 = {
+ .name = "orion_spi",
+ .id = 1,
+ .dev = {
+ .platform_data = &orion_spi_1_plat_data,
+ },
+};
+
+/* Note: The SPI silicon core does have interrupts. However the
+ * current Linux software driver does not use interrupts. */
+
+void __init orion_spi_init(unsigned long mapbase,
+ unsigned long tclk)
+{
+ orion_spi_plat_data.tclk = tclk;
+ fill_resources(&orion_spi, &orion_spi_resources,
+ mapbase, SZ_512 - 1, NO_IRQ);
+ platform_device_register(&orion_spi);
+}
+
+void __init orion_spi_1_init(unsigned long mapbase,
+ unsigned long tclk)
+{
+ orion_spi_1_plat_data.tclk = tclk;
+ fill_resources(&orion_spi_1, &orion_spi_1_resources,
+ mapbase, SZ_512 - 1, NO_IRQ);
+ platform_device_register(&orion_spi_1);
+}
+
+/*****************************************************************************
+ * Watchdog
+ ****************************************************************************/
+static struct orion_wdt_platform_data orion_wdt_data;
+
+static struct platform_device orion_wdt_device = {
+ .name = "orion_wdt",
+ .id = -1,
+ .dev = {
+ .platform_data = &orion_wdt_data,
+ },
+ .num_resources = 0,
+};
+
+void __init orion_wdt_init(unsigned long tclk)
+{
+ orion_wdt_data.tclk = tclk;
+ platform_device_register(&orion_wdt_device);
+}
+
+/*****************************************************************************
+ * XOR
+ ****************************************************************************/
+static struct mv_xor_platform_shared_data orion_xor_shared_data;
+
+static u64 orion_xor_dmamask = DMA_BIT_MASK(32);
+
+void __init orion_xor_init_channels(
+ struct mv_xor_platform_data *orion_xor0_data,
+ struct platform_device *orion_xor0_channel,
+ struct mv_xor_platform_data *orion_xor1_data,
+ struct platform_device *orion_xor1_channel)
+{
+ /*
+ * two engines can't do memset simultaneously, this limitation
+ * satisfied by removing memset support from one of the engines.
+ */
+ dma_cap_set(DMA_MEMCPY, orion_xor0_data->cap_mask);
+ dma_cap_set(DMA_XOR, orion_xor0_data->cap_mask);
+ platform_device_register(orion_xor0_channel);
+
+ dma_cap_set(DMA_MEMCPY, orion_xor1_data->cap_mask);
+ dma_cap_set(DMA_MEMSET, orion_xor1_data->cap_mask);
+ dma_cap_set(DMA_XOR, orion_xor1_data->cap_mask);
+ platform_device_register(orion_xor1_channel);
+}
+
+/*****************************************************************************
+ * XOR0
+ ****************************************************************************/
+static struct resource orion_xor0_shared_resources[] = {
+ {
+ .name = "xor 0 low",
+ .flags = IORESOURCE_MEM,
+ }, {
+ .name = "xor 0 high",
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device orion_xor0_shared = {
+ .name = MV_XOR_SHARED_NAME,
+ .id = 0,
+ .dev = {
+ .platform_data = &orion_xor_shared_data,
+ },
+ .num_resources = ARRAY_SIZE(orion_xor0_shared_resources),
+ .resource = orion_xor0_shared_resources,
+};
+
+static struct resource orion_xor00_resources[] = {
+ [0] = {
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct mv_xor_platform_data orion_xor00_data = {
+ .shared = &orion_xor0_shared,
+ .hw_id = 0,
+ .pool_size = PAGE_SIZE,
+};
+
+static struct platform_device orion_xor00_channel = {
+ .name = MV_XOR_NAME,
+ .id = 0,
+ .num_resources = ARRAY_SIZE(orion_xor00_resources),
+ .resource = orion_xor00_resources,
+ .dev = {
+ .dma_mask = &orion_xor_dmamask,
+ .coherent_dma_mask = DMA_BIT_MASK(64),
+ .platform_data = &orion_xor00_data,
+ },
+};
+
+static struct resource orion_xor01_resources[] = {
+ [0] = {
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct mv_xor_platform_data orion_xor01_data = {
+ .shared = &orion_xor0_shared,
+ .hw_id = 1,
+ .pool_size = PAGE_SIZE,
+};
+
+static struct platform_device orion_xor01_channel = {
+ .name = MV_XOR_NAME,
+ .id = 1,
+ .num_resources = ARRAY_SIZE(orion_xor01_resources),
+ .resource = orion_xor01_resources,
+ .dev = {
+ .dma_mask = &orion_xor_dmamask,
+ .coherent_dma_mask = DMA_BIT_MASK(64),
+ .platform_data = &orion_xor01_data,
+ },
+};
+
+void __init orion_xor0_init(struct mbus_dram_target_info *mbus_dram_info,
+ unsigned long mapbase_low,
+ unsigned long mapbase_high,
+ unsigned long irq_0,
+ unsigned long irq_1)
+{
+ orion_xor_shared_data.dram = mbus_dram_info;
+
+ orion_xor0_shared_resources[0].start = mapbase_low;
+ orion_xor0_shared_resources[0].end = mapbase_low + 0xff;
+ orion_xor0_shared_resources[1].start = mapbase_high;
+ orion_xor0_shared_resources[1].end = mapbase_high + 0xff;
+
+ orion_xor00_resources[0].start = irq_0;
+ orion_xor00_resources[0].end = irq_0;
+ orion_xor01_resources[0].start = irq_1;
+ orion_xor01_resources[0].end = irq_1;
+
+ platform_device_register(&orion_xor0_shared);
+
+ orion_xor_init_channels(&orion_xor00_data, &orion_xor00_channel,
+ &orion_xor01_data, &orion_xor01_channel);
+}
+
+/*****************************************************************************
+ * XOR1
+ ****************************************************************************/
+static struct resource orion_xor1_shared_resources[] = {
+ {
+ .name = "xor 1 low",
+ .flags = IORESOURCE_MEM,
+ }, {
+ .name = "xor 1 high",
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device orion_xor1_shared = {
+ .name = MV_XOR_SHARED_NAME,
+ .id = 1,
+ .dev = {
+ .platform_data = &orion_xor_shared_data,
+ },
+ .num_resources = ARRAY_SIZE(orion_xor1_shared_resources),
+ .resource = orion_xor1_shared_resources,
+};
+
+static struct resource orion_xor10_resources[] = {
+ [0] = {
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct mv_xor_platform_data orion_xor10_data = {
+ .shared = &orion_xor1_shared,
+ .hw_id = 0,
+ .pool_size = PAGE_SIZE,
+};
+
+static struct platform_device orion_xor10_channel = {
+ .name = MV_XOR_NAME,
+ .id = 2,
+ .num_resources = ARRAY_SIZE(orion_xor10_resources),
+ .resource = orion_xor10_resources,
+ .dev = {
+ .dma_mask = &orion_xor_dmamask,
+ .coherent_dma_mask = DMA_BIT_MASK(64),
+ .platform_data = &orion_xor10_data,
+ },
+};
+
+static struct resource orion_xor11_resources[] = {
+ [0] = {
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+static struct mv_xor_platform_data orion_xor11_data = {
+ .shared = &orion_xor1_shared,
+ .hw_id = 1,
+ .pool_size = PAGE_SIZE,
+};
+
+static struct platform_device orion_xor11_channel = {
+ .name = MV_XOR_NAME,
+ .id = 3,
+ .num_resources = ARRAY_SIZE(orion_xor11_resources),
+ .resource = orion_xor11_resources,
+ .dev = {
+ .dma_mask = &orion_xor_dmamask,
+ .coherent_dma_mask = DMA_BIT_MASK(64),
+ .platform_data = &orion_xor11_data,
+ },
+};
+
+void __init orion_xor1_init(unsigned long mapbase_low,
+ unsigned long mapbase_high,
+ unsigned long irq_0,
+ unsigned long irq_1)
+{
+ orion_xor1_shared_resources[0].start = mapbase_low;
+ orion_xor1_shared_resources[0].end = mapbase_low + 0xff;
+ orion_xor1_shared_resources[1].start = mapbase_high;
+ orion_xor1_shared_resources[1].end = mapbase_high + 0xff;
+
+ orion_xor10_resources[0].start = irq_0;
+ orion_xor10_resources[0].end = irq_0;
+ orion_xor11_resources[0].start = irq_1;
+ orion_xor11_resources[0].end = irq_1;
+
+ platform_device_register(&orion_xor1_shared);
+
+ orion_xor_init_channels(&orion_xor10_data, &orion_xor10_channel,
+ &orion_xor11_data, &orion_xor11_channel);
+}
+
+/*****************************************************************************
+ * EHCI
+ ****************************************************************************/
+static struct orion_ehci_data orion_ehci_data = {
+ .phy_version = EHCI_PHY_NA,
+};
+
+static u64 ehci_dmamask = DMA_BIT_MASK(32);
+
+
+/*****************************************************************************
+ * EHCI0
+ ****************************************************************************/
+static struct resource orion_ehci_resources[2];
+
+static struct platform_device orion_ehci = {
+ .name = "orion-ehci",
+ .id = 0,
+ .dev = {
+ .dma_mask = &ehci_dmamask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ .platform_data = &orion_ehci_data,
+ },
+};
+
+void __init orion_ehci_init(struct mbus_dram_target_info *mbus_dram_info,
+ unsigned long mapbase,
+ unsigned long irq)
+{
+ orion_ehci_data.dram = mbus_dram_info;
+ fill_resources(&orion_ehci, orion_ehci_resources, mapbase, SZ_4K - 1,
+ irq);
+
+ platform_device_register(&orion_ehci);
+}
+
+/*****************************************************************************
+ * EHCI1
+ ****************************************************************************/
+static struct resource orion_ehci_1_resources[2];
+
+static struct platform_device orion_ehci_1 = {
+ .name = "orion-ehci",
+ .id = 1,
+ .dev = {
+ .dma_mask = &ehci_dmamask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ .platform_data = &orion_ehci_data,
+ },
+};
+
+void __init orion_ehci_1_init(struct mbus_dram_target_info *mbus_dram_info,
+ unsigned long mapbase,
+ unsigned long irq)
+{
+ orion_ehci_data.dram = mbus_dram_info;
+ fill_resources(&orion_ehci_1, orion_ehci_1_resources,
+ mapbase, SZ_4K - 1, irq);
+
+ platform_device_register(&orion_ehci_1);
+}
+
+/*****************************************************************************
+ * EHCI2
+ ****************************************************************************/
+static struct resource orion_ehci_2_resources[2];
+
+static struct platform_device orion_ehci_2 = {
+ .name = "orion-ehci",
+ .id = 2,
+ .dev = {
+ .dma_mask = &ehci_dmamask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ .platform_data = &orion_ehci_data,
+ },
+};
+
+void __init orion_ehci_2_init(struct mbus_dram_target_info *mbus_dram_info,
+ unsigned long mapbase,
+ unsigned long irq)
+{
+ orion_ehci_data.dram = mbus_dram_info;
+ fill_resources(&orion_ehci_2, orion_ehci_2_resources,
+ mapbase, SZ_4K - 1, irq);
+
+ platform_device_register(&orion_ehci_2);
+}
+
+/*****************************************************************************
+ * SATA
+ ****************************************************************************/
+static struct resource orion_sata_resources[2] = {
+ {
+ .name = "sata base",
+ }, {
+ .name = "sata irq",
+ },
+};
+
+static struct platform_device orion_sata = {
+ .name = "sata_mv",
+ .id = 0,
+ .dev = {
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+};
+
+void __init orion_sata_init(struct mv_sata_platform_data *sata_data,
+ struct mbus_dram_target_info *mbus_dram_info,
+ unsigned long mapbase,
+ unsigned long irq)
+{
+ sata_data->dram = mbus_dram_info;
+ orion_sata.dev.platform_data = sata_data;
+ fill_resources(&orion_sata, orion_sata_resources,
+ mapbase, 0x5000 - 1, irq);
+
+ platform_device_register(&orion_sata);
+}
+
+/*****************************************************************************
+ * Cryptographic Engines and Security Accelerator (CESA)
+ ****************************************************************************/
+static struct resource orion_crypto_resources[] = {
+ {
+ .name = "regs",
+ }, {
+ .name = "crypto interrupt",
+ }, {
+ .name = "sram",
+ .flags = IORESOURCE_MEM,
+ },
+};
+
+static struct platform_device orion_crypto = {
+ .name = "mv_crypto",
+ .id = -1,
+};
+
+void __init orion_crypto_init(unsigned long mapbase,
+ unsigned long srambase,
+ unsigned long sram_size,
+ unsigned long irq)
+{
+ fill_resources(&orion_crypto, orion_crypto_resources,
+ mapbase, 0xffff, irq);
+ orion_crypto.num_resources = 3;
+ orion_crypto_resources[2].start = srambase;
+ orion_crypto_resources[2].end = srambase + sram_size - 1;
+
+ platform_device_register(&orion_crypto);
+}
diff --git a/arch/arm/plat-orion/gpio.c b/arch/arm/plat-orion/gpio.c
index a431a13..5b4fffa 100644
--- a/arch/arm/plat-orion/gpio.c
+++ b/arch/arm/plat-orion/gpio.c
@@ -321,59 +321,16 @@
* polarity LEVEL mask
*
****************************************************************************/
-static void gpio_irq_ack(struct irq_data *d)
-{
- struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
- int type = irqd_get_trigger_type(d);
-
- if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
- int pin = d->irq - ochip->secondary_irq_base;
-
- writel(~(1 << pin), GPIO_EDGE_CAUSE(ochip));
- }
-}
-
-static void gpio_irq_mask(struct irq_data *d)
-{
- struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
- int type = irqd_get_trigger_type(d);
- void __iomem *reg;
- int pin;
-
- if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
- reg = GPIO_EDGE_MASK(ochip);
- else
- reg = GPIO_LEVEL_MASK(ochip);
-
- pin = d->irq - ochip->secondary_irq_base;
-
- writel(readl(reg) & ~(1 << pin), reg);
-}
-
-static void gpio_irq_unmask(struct irq_data *d)
-{
- struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
- int type = irqd_get_trigger_type(d);
- void __iomem *reg;
- int pin;
-
- if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
- reg = GPIO_EDGE_MASK(ochip);
- else
- reg = GPIO_LEVEL_MASK(ochip);
-
- pin = d->irq - ochip->secondary_irq_base;
-
- writel(readl(reg) | (1 << pin), reg);
-}
static int gpio_irq_set_type(struct irq_data *d, u32 type)
{
- struct orion_gpio_chip *ochip = irq_data_get_irq_chip_data(d);
+ struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+ struct irq_chip_type *ct = irq_data_get_chip_type(d);
+ struct orion_gpio_chip *ochip = gc->private;
int pin;
u32 u;
- pin = d->irq - ochip->secondary_irq_base;
+ pin = d->irq - gc->irq_base;
u = readl(GPIO_IO_CONF(ochip)) & (1 << pin);
if (!u) {
@@ -382,18 +339,14 @@
return -EINVAL;
}
- /*
- * Set edge/level type.
- */
- if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
- __irq_set_handler_locked(d->irq, handle_edge_irq);
- } else if (type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
- __irq_set_handler_locked(d->irq, handle_level_irq);
- } else {
- printk(KERN_ERR "failed to set irq=%d (type=%d)\n",
- d->irq, type);
+ type &= IRQ_TYPE_SENSE_MASK;
+ if (type == IRQ_TYPE_NONE)
return -EINVAL;
- }
+
+ /* Check if we need to change chip and handler */
+ if (!(ct->type & type))
+ if (irq_setup_alt_chip(d, type))
+ return -EINVAL;
/*
* Configure interrupt polarity.
@@ -425,19 +378,12 @@
return 0;
}
-struct irq_chip orion_gpio_irq_chip = {
- .name = "orion_gpio_irq",
- .irq_ack = gpio_irq_ack,
- .irq_mask = gpio_irq_mask,
- .irq_unmask = gpio_irq_unmask,
- .irq_set_type = gpio_irq_set_type,
-};
-
void __init orion_gpio_init(int gpio_base, int ngpio,
u32 base, int mask_offset, int secondary_irq_base)
{
struct orion_gpio_chip *ochip;
- int i;
+ struct irq_chip_generic *gc;
+ struct irq_chip_type *ct;
if (orion_gpio_chip_count == ARRAY_SIZE(orion_gpio_chips))
return;
@@ -471,15 +417,29 @@
writel(0, GPIO_EDGE_MASK(ochip));
writel(0, GPIO_LEVEL_MASK(ochip));
- for (i = 0; i < ngpio; i++) {
- unsigned int irq = secondary_irq_base + i;
+ gc = irq_alloc_generic_chip("orion_gpio_irq", 2, secondary_irq_base,
+ ochip->base, handle_level_irq);
+ gc->private = ochip;
- irq_set_chip_and_handler(irq, &orion_gpio_irq_chip,
- handle_level_irq);
- irq_set_chip_data(irq, ochip);
- irq_set_status_flags(irq, IRQ_LEVEL);
- set_irq_flags(irq, IRQF_VALID);
- }
+ ct = gc->chip_types;
+ ct->regs.mask = ochip->mask_offset + GPIO_LEVEL_MASK_OFF;
+ ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
+ ct->chip.irq_mask = irq_gc_mask_clr_bit;
+ ct->chip.irq_unmask = irq_gc_mask_set_bit;
+ ct->chip.irq_set_type = gpio_irq_set_type;
+
+ ct++;
+ ct->regs.mask = ochip->mask_offset + GPIO_EDGE_MASK_OFF;
+ ct->regs.ack = GPIO_EDGE_CAUSE_OFF;
+ ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
+ ct->chip.irq_ack = irq_gc_ack;
+ ct->chip.irq_mask = irq_gc_mask_clr_bit;
+ ct->chip.irq_unmask = irq_gc_mask_set_bit;
+ ct->chip.irq_set_type = gpio_irq_set_type;
+ ct->handler = handle_edge_irq;
+
+ irq_setup_generic_chip(gc, IRQ_MSK(ngpio), IRQ_GC_INIT_MASK_CACHE,
+ IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
}
void orion_gpio_irq_handler(int pinoff)
diff --git a/arch/arm/plat-orion/include/plat/common.h b/arch/arm/plat-orion/include/plat/common.h
new file mode 100644
index 0000000..a63c357
--- /dev/null
+++ b/arch/arm/plat-orion/include/plat/common.h
@@ -0,0 +1,117 @@
+/*
+ * arch/arm/plat-orion/include/plat/common.h
+ *
+ * Marvell Orion SoC common setup code used by different mach-/common.c
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __PLAT_COMMON_H
+#include <linux/mv643xx_eth.h>
+
+struct dsa_platform_data;
+
+void __init orion_uart0_init(unsigned int membase,
+ resource_size_t mapbase,
+ unsigned int irq,
+ unsigned int uartclk);
+
+void __init orion_uart1_init(unsigned int membase,
+ resource_size_t mapbase,
+ unsigned int irq,
+ unsigned int uartclk);
+
+void __init orion_uart2_init(unsigned int membase,
+ resource_size_t mapbase,
+ unsigned int irq,
+ unsigned int uartclk);
+
+void __init orion_uart3_init(unsigned int membase,
+ resource_size_t mapbase,
+ unsigned int irq,
+ unsigned int uartclk);
+
+void __init orion_rtc_init(unsigned long mapbase,
+ unsigned long irq);
+
+void __init orion_ge00_init(struct mv643xx_eth_platform_data *eth_data,
+ struct mbus_dram_target_info *mbus_dram_info,
+ unsigned long mapbase,
+ unsigned long irq,
+ unsigned long irq_err,
+ int tclk);
+
+void __init orion_ge01_init(struct mv643xx_eth_platform_data *eth_data,
+ struct mbus_dram_target_info *mbus_dram_info,
+ unsigned long mapbase,
+ unsigned long irq,
+ unsigned long irq_err,
+ int tclk);
+
+void __init orion_ge10_init(struct mv643xx_eth_platform_data *eth_data,
+ struct mbus_dram_target_info *mbus_dram_info,
+ unsigned long mapbase,
+ unsigned long irq,
+ unsigned long irq_err,
+ int tclk);
+
+void __init orion_ge11_init(struct mv643xx_eth_platform_data *eth_data,
+ struct mbus_dram_target_info *mbus_dram_info,
+ unsigned long mapbase,
+ unsigned long irq,
+ unsigned long irq_err,
+ int tclk);
+
+void __init orion_ge00_switch_init(struct dsa_platform_data *d,
+ int irq);
+void __init orion_i2c_init(unsigned long mapbase,
+ unsigned long irq,
+ unsigned long freq_m);
+
+void __init orion_i2c_1_init(unsigned long mapbase,
+ unsigned long irq,
+ unsigned long freq_m);
+
+void __init orion_spi_init(unsigned long mapbase,
+ unsigned long tclk);
+
+void __init orion_spi_1_init(unsigned long mapbase,
+ unsigned long tclk);
+
+void __init orion_wdt_init(unsigned long tclk);
+
+void __init orion_xor0_init(struct mbus_dram_target_info *mbus_dram_info,
+ unsigned long mapbase_low,
+ unsigned long mapbase_high,
+ unsigned long irq_0,
+ unsigned long irq_1);
+
+void __init orion_xor1_init(unsigned long mapbase_low,
+ unsigned long mapbase_high,
+ unsigned long irq_0,
+ unsigned long irq_1);
+
+void __init orion_ehci_init(struct mbus_dram_target_info *mbus_dram_info,
+ unsigned long mapbase,
+ unsigned long irq);
+
+void __init orion_ehci_1_init(struct mbus_dram_target_info *mbus_dram_info,
+ unsigned long mapbase,
+ unsigned long irq);
+
+void __init orion_ehci_2_init(struct mbus_dram_target_info *mbus_dram_info,
+ unsigned long mapbase,
+ unsigned long irq);
+
+void __init orion_sata_init(struct mv_sata_platform_data *sata_data,
+ struct mbus_dram_target_info *mbus_dram_info,
+ unsigned long mapbase,
+ unsigned long irq);
+
+void __init orion_crypto_init(unsigned long mapbase,
+ unsigned long srambase,
+ unsigned long sram_size,
+ unsigned long irq);
+#endif
diff --git a/arch/arm/plat-orion/include/plat/gpio.h b/arch/arm/plat-orion/include/plat/gpio.h
index 5578b98..3075b9f 100644
--- a/arch/arm/plat-orion/include/plat/gpio.h
+++ b/arch/arm/plat-orion/include/plat/gpio.h
@@ -39,7 +39,6 @@
/*
* GPIO interrupt handling.
*/
-extern struct irq_chip orion_gpio_irq_chip;
void orion_gpio_irq_handler(int irqoff);
diff --git a/arch/arm/plat-orion/include/plat/mpp.h b/arch/arm/plat-orion/include/plat/mpp.h
new file mode 100644
index 0000000..723adce
--- /dev/null
+++ b/arch/arm/plat-orion/include/plat/mpp.h
@@ -0,0 +1,34 @@
+/*
+ * arch/arm/plat-orion/include/plat/mpp.h
+ *
+ * Marvell Orion SoC MPP handling.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __PLAT_MPP_H
+#define __PLAT_MPP_H
+
+#define MPP_NUM(x) ((x) & 0xff)
+#define MPP_SEL(x) (((x) >> 8) & 0xf)
+
+/* This is the generic MPP macro, without any variant information.
+ Each machine architecture is expected to extend this with further
+ bit fields indicating which MPP configurations are valid for a
+ specific variant. */
+
+#define GENERIC_MPP(_num, _sel, _in, _out) ( \
+ /* MPP number */ ((_num) & 0xff) | \
+ /* MPP select value */ (((_sel) & 0xf) << 8) | \
+ /* may be input signal */ ((!!(_in)) << 12) | \
+ /* may be output signal */ ((!!(_out)) << 13))
+
+#define MPP_INPUT_MASK GENERIC_MPP(0, 0x0, 1, 0)
+#define MPP_OUTPUT_MASK GENERIC_MPP(0, 0x0, 0, 1)
+
+void __init orion_mpp_conf(unsigned int *mpp_list, unsigned int variant_mask,
+ unsigned int mpp_max, unsigned int dev_bus);
+
+#endif
diff --git a/arch/arm/plat-orion/irq.c b/arch/arm/plat-orion/irq.c
index d8d638e..2d5b9c1 100644
--- a/arch/arm/plat-orion/irq.c
+++ b/arch/arm/plat-orion/irq.c
@@ -14,52 +14,21 @@
#include <linux/io.h>
#include <plat/irq.h>
-static void orion_irq_mask(struct irq_data *d)
-{
- void __iomem *maskaddr = irq_data_get_irq_chip_data(d);
- u32 mask;
-
- mask = readl(maskaddr);
- mask &= ~(1 << (d->irq & 31));
- writel(mask, maskaddr);
-}
-
-static void orion_irq_unmask(struct irq_data *d)
-{
- void __iomem *maskaddr = irq_data_get_irq_chip_data(d);
- u32 mask;
-
- mask = readl(maskaddr);
- mask |= 1 << (d->irq & 31);
- writel(mask, maskaddr);
-}
-
-static struct irq_chip orion_irq_chip = {
- .name = "orion_irq",
- .irq_mask = orion_irq_mask,
- .irq_mask_ack = orion_irq_mask,
- .irq_unmask = orion_irq_unmask,
-};
-
void __init orion_irq_init(unsigned int irq_start, void __iomem *maskaddr)
{
- unsigned int i;
+ struct irq_chip_generic *gc;
+ struct irq_chip_type *ct;
/*
* Mask all interrupts initially.
*/
writel(0, maskaddr);
- /*
- * Register IRQ sources.
- */
- for (i = 0; i < 32; i++) {
- unsigned int irq = irq_start + i;
-
- irq_set_chip_and_handler(irq, &orion_irq_chip,
- handle_level_irq);
- irq_set_chip_data(irq, maskaddr);
- irq_set_status_flags(irq, IRQ_LEVEL);
- set_irq_flags(irq, IRQF_VALID);
- }
+ gc = irq_alloc_generic_chip("orion_irq", 1, irq_start, maskaddr,
+ handle_level_irq);
+ ct = gc->chip_types;
+ ct->chip.irq_mask = irq_gc_mask_clr_bit;
+ ct->chip.irq_unmask = irq_gc_mask_set_bit;
+ irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_MASK_CACHE,
+ IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
}
diff --git a/arch/arm/plat-orion/mpp.c b/arch/arm/plat-orion/mpp.c
new file mode 100644
index 0000000..9155343
--- /dev/null
+++ b/arch/arm/plat-orion/mpp.c
@@ -0,0 +1,78 @@
+/*
+ * arch/arm/plat-orion/mpp.c
+ *
+ * MPP functions for Marvell orion SoCs
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mbus.h>
+#include <linux/io.h>
+#include <linux/gpio.h>
+#include <mach/hardware.h>
+#include <plat/mpp.h>
+
+/* Address of the ith MPP control register */
+static __init unsigned long mpp_ctrl_addr(unsigned int i,
+ unsigned long dev_bus)
+{
+ return dev_bus + (i) * 4;
+}
+
+
+void __init orion_mpp_conf(unsigned int *mpp_list, unsigned int variant_mask,
+ unsigned int mpp_max, unsigned int dev_bus)
+{
+ unsigned int mpp_nr_regs = (1 + mpp_max/8);
+ u32 mpp_ctrl[mpp_nr_regs];
+ int i;
+
+ printk(KERN_DEBUG "initial MPP regs:");
+ for (i = 0; i < mpp_nr_regs; i++) {
+ mpp_ctrl[i] = readl(mpp_ctrl_addr(i, dev_bus));
+ printk(" %08x", mpp_ctrl[i]);
+ }
+ printk("\n");
+
+ for ( ; *mpp_list; mpp_list++) {
+ unsigned int num = MPP_NUM(*mpp_list);
+ unsigned int sel = MPP_SEL(*mpp_list);
+ int shift, gpio_mode;
+
+ if (num > mpp_max) {
+ printk(KERN_ERR "orion_mpp_conf: invalid MPP "
+ "number (%u)\n", num);
+ continue;
+ }
+ if (variant_mask & !(*mpp_list & variant_mask)) {
+ printk(KERN_WARNING
+ "orion_mpp_conf: requested MPP%u config "
+ "unavailable on this hardware\n", num);
+ continue;
+ }
+
+ shift = (num & 7) << 2;
+ mpp_ctrl[num / 8] &= ~(0xf << shift);
+ mpp_ctrl[num / 8] |= sel << shift;
+
+ gpio_mode = 0;
+ if (*mpp_list & MPP_INPUT_MASK)
+ gpio_mode |= GPIO_INPUT_OK;
+ if (*mpp_list & MPP_OUTPUT_MASK)
+ gpio_mode |= GPIO_OUTPUT_OK;
+ if (sel != 0)
+ gpio_mode = 0;
+ orion_gpio_set_valid(num, gpio_mode);
+ }
+
+ printk(KERN_DEBUG " final MPP regs:");
+ for (i = 0; i < mpp_nr_regs; i++) {
+ writel(mpp_ctrl[i], mpp_ctrl_addr(i, dev_bus));
+ printk(" %08x", mpp_ctrl[i]);
+ }
+ printk("\n");
+}
diff --git a/arch/arm/plat-orion/time.c b/arch/arm/plat-orion/time.c
index 742b032..69a6136 100644
--- a/arch/arm/plat-orion/time.c
+++ b/arch/arm/plat-orion/time.c
@@ -81,24 +81,6 @@
}
/*
- * Clocksource handling.
- */
-static cycle_t orion_clksrc_read(struct clocksource *cs)
-{
- return 0xffffffff - readl(timer_base + TIMER0_VAL_OFF);
-}
-
-static struct clocksource orion_clksrc = {
- .name = "orion_clocksource",
- .rating = 300,
- .read = orion_clksrc_read,
- .mask = CLOCKSOURCE_MASK(32),
- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
-
-
-/*
* Clockevent handling.
*/
static int
@@ -247,7 +229,8 @@
writel(u & ~BRIDGE_INT_TIMER0, bridge_base + BRIDGE_MASK_OFF);
u = readl(timer_base + TIMER_CTRL_OFF);
writel(u | TIMER0_EN | TIMER0_RELOAD_EN, timer_base + TIMER_CTRL_OFF);
- clocksource_register_hz(&orion_clksrc, tclk);
+ clocksource_mmio_init(timer_base + TIMER0_VAL_OFF, "orion_clocksource",
+ tclk, 300, 32, clocksource_mmio_readl_down);
/*
* Setup clockevent timer (interrupt-driven).
diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c
index 268f3ed..7366799 100644
--- a/arch/arm/plat-s3c24xx/devs.c
+++ b/arch/arm/plat-s3c24xx/devs.c
@@ -22,6 +22,7 @@
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/string.h>
+#include <linux/dma-mapping.h>
#include <asm/mach/arch.h>
#include <asm/mach/map.h>
@@ -233,6 +234,46 @@
}
}
+/* USB High Speed 2.0 Device (Gadget) */
+static struct resource s3c_hsudc_resource[] = {
+ [0] = {
+ .start = S3C2416_PA_HSUDC,
+ .end = S3C2416_PA_HSUDC + S3C2416_SZ_HSUDC - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_USBD,
+ .end = IRQ_USBD,
+ .flags = IORESOURCE_IRQ,
+ }
+};
+
+static u64 s3c_hsudc_dmamask = DMA_BIT_MASK(32);
+
+struct platform_device s3c_device_usb_hsudc = {
+ .name = "s3c-hsudc",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(s3c_hsudc_resource),
+ .resource = s3c_hsudc_resource,
+ .dev = {
+ .dma_mask = &s3c_hsudc_dmamask,
+ .coherent_dma_mask = DMA_BIT_MASK(32),
+ },
+};
+
+void __init s3c24xx_hsudc_set_platdata(struct s3c24xx_hsudc_platdata *pd)
+{
+ struct s3c24xx_hsudc_platdata *npd;
+
+ npd = kmalloc(sizeof(*npd), GFP_KERNEL);
+ if (npd) {
+ memcpy(npd, pd, sizeof(*npd));
+ s3c_device_usb_hsudc.dev.platform_data = npd;
+ } else {
+ printk(KERN_ERR "no memory for udc platform data\n");
+ }
+}
+
/* IIS */
static struct resource s3c_iis_resource[] = {
diff --git a/arch/arm/plat-s3c24xx/include/plat/udc.h b/arch/arm/plat-s3c24xx/include/plat/udc.h
index 80457c6..f6388424 100644
--- a/arch/arm/plat-s3c24xx/include/plat/udc.h
+++ b/arch/arm/plat-s3c24xx/include/plat/udc.h
@@ -37,4 +37,21 @@
extern void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *);
+/**
+ * s3c24xx_hsudc_platdata - Platform data for USB High-Speed gadget controller.
+ * @epnum: Number of endpoints to be instantiated by the controller driver.
+ * @gpio_init: Platform specific USB related GPIO initialization.
+ * @gpio_uninit: Platform specific USB releted GPIO uninitialzation.
+ *
+ * Representation of platform data for the S3C24XX USB 2.0 High Speed gadget
+ * controllers.
+ */
+struct s3c24xx_hsudc_platdata {
+ unsigned int epnum;
+ void (*gpio_init)(void);
+ void (*gpio_uninit)(void);
+};
+
+extern void __init s3c24xx_hsudc_set_platdata(struct s3c24xx_hsudc_platdata *pd);
+
#endif /* __ASM_ARM_ARCH_UDC_H */
diff --git a/arch/arm/plat-s5p/Kconfig b/arch/arm/plat-s5p/Kconfig
index 8492297..6751bcf 100644
--- a/arch/arm/plat-s5p/Kconfig
+++ b/arch/arm/plat-s5p/Kconfig
@@ -85,6 +85,11 @@
help
Compile in platform device definitions for MIPI-CSIS channel 1
+config S5P_DEV_USB_EHCI
+ bool
+ help
+ Compile in platform device definition for USB EHCI
+
config S5P_SETUP_MIPIPHY
bool
help
diff --git a/arch/arm/plat-s5p/Makefile b/arch/arm/plat-s5p/Makefile
index 42afff7..e234cc4 100644
--- a/arch/arm/plat-s5p/Makefile
+++ b/arch/arm/plat-s5p/Makefile
@@ -33,4 +33,5 @@
obj-$(CONFIG_S5P_DEV_ONENAND) += dev-onenand.o
obj-$(CONFIG_S5P_DEV_CSIS0) += dev-csis0.o
obj-$(CONFIG_S5P_DEV_CSIS1) += dev-csis1.o
+obj-$(CONFIG_S5P_DEV_USB_EHCI) += dev-ehci.o
obj-$(CONFIG_S5P_SETUP_MIPIPHY) += setup-mipiphy.o
diff --git a/arch/arm/plat-s5p/dev-ehci.c b/arch/arm/plat-s5p/dev-ehci.c
new file mode 100644
index 0000000..94080ff
--- /dev/null
+++ b/arch/arm/plat-s5p/dev-ehci.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2011 Samsung Electronics Co.Ltd
+ * Author: Joonyoung Shim <jy0922.shim@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#include <linux/platform_device.h>
+#include <mach/irqs.h>
+#include <mach/map.h>
+#include <plat/devs.h>
+#include <plat/ehci.h>
+#include <plat/usb-phy.h>
+
+/* USB EHCI Host Controller registration */
+static struct resource s5p_ehci_resource[] = {
+ [0] = {
+ .start = S5P_PA_EHCI,
+ .end = S5P_PA_EHCI + SZ_256 - 1,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = IRQ_USB_HOST,
+ .end = IRQ_USB_HOST,
+ .flags = IORESOURCE_IRQ,
+ }
+};
+
+static u64 s5p_device_ehci_dmamask = 0xffffffffUL;
+
+struct platform_device s5p_device_ehci = {
+ .name = "s5p-ehci",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(s5p_ehci_resource),
+ .resource = s5p_ehci_resource,
+ .dev = {
+ .dma_mask = &s5p_device_ehci_dmamask,
+ .coherent_dma_mask = 0xffffffffUL
+ }
+};
+
+void __init s5p_ehci_set_platdata(struct s5p_ehci_platdata *pd)
+{
+ struct s5p_ehci_platdata *npd;
+
+ npd = s3c_set_platdata(pd, sizeof(struct s5p_ehci_platdata),
+ &s5p_device_ehci);
+
+ if (!npd->phy_init)
+ npd->phy_init = s5p_usb_phy_init;
+ if (!npd->phy_exit)
+ npd->phy_exit = s5p_usb_phy_exit;
+}
diff --git a/arch/arm/plat-s5p/include/plat/ehci.h b/arch/arm/plat-s5p/include/plat/ehci.h
new file mode 100644
index 0000000..6ae6810
--- /dev/null
+++ b/arch/arm/plat-s5p/include/plat/ehci.h
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2011 Samsung Electronics Co.Ltd
+ * Author: Joonyoung Shim <jy0922.shim@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __PLAT_S5P_EHCI_H
+#define __PLAT_S5P_EHCI_H
+
+struct s5p_ehci_platdata {
+ int (*phy_init)(struct platform_device *pdev, int type);
+ int (*phy_exit)(struct platform_device *pdev, int type);
+};
+
+extern void s5p_ehci_set_platdata(struct s5p_ehci_platdata *pd);
+
+#endif /* __PLAT_S5P_EHCI_H */
diff --git a/arch/arm/plat-s5p/include/plat/map-s5p.h b/arch/arm/plat-s5p/include/plat/map-s5p.h
index d973d39..a6c3d32 100644
--- a/arch/arm/plat-s5p/include/plat/map-s5p.h
+++ b/arch/arm/plat-s5p/include/plat/map-s5p.h
@@ -39,7 +39,7 @@
#define S5P_VA_TWD S5P_VA_COREPERI(0x600)
#define S5P_VA_GIC_DIST S5P_VA_COREPERI(0x1000)
-#define S3C_VA_USB_HSPHY S3C_ADDR(0x02900000)
+#define S5P_VA_USB_HSPHY S3C_ADDR(0x02900000)
#define VA_VIC(x) (S3C_VA_IRQ + ((x) * 0x10000))
#define VA_VIC0 VA_VIC(0)
diff --git a/arch/arm/plat-s5p/include/plat/usb-phy.h b/arch/arm/plat-s5p/include/plat/usb-phy.h
new file mode 100644
index 0000000..6dd6bcf
--- /dev/null
+++ b/arch/arm/plat-s5p/include/plat/usb-phy.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (C) 2011 Samsung Electronics Co.Ltd
+ * Author: Joonyoung Shim <jy0922.shim@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+#ifndef __PLAT_S5P_USB_PHY_H
+#define __PLAT_S5P_USB_PHY_H
+
+enum s5p_usb_phy_type {
+ S5P_USB_PHY_DEVICE,
+ S5P_USB_PHY_HOST,
+};
+
+extern int s5p_usb_phy_init(struct platform_device *pdev, int type);
+extern int s5p_usb_phy_exit(struct platform_device *pdev, int type);
+
+#endif /* __PLAT_S5P_REGS_USB_PHY_H */
diff --git a/arch/arm/plat-s5p/irq-gpioint.c b/arch/arm/plat-s5p/irq-gpioint.c
index cd6d67c..135abda 100644
--- a/arch/arm/plat-s5p/irq-gpioint.c
+++ b/arch/arm/plat-s5p/irq-gpioint.c
@@ -41,72 +41,11 @@
LIST_HEAD(banks);
-static int s5p_gpioint_get_offset(struct irq_data *data)
+static int s5p_gpioint_set_type(struct irq_data *d, unsigned int type)
{
- struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data);
- return data->irq - chip->irq_base;
-}
-
-static void s5p_gpioint_ack(struct irq_data *data)
-{
- struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data);
- int group, offset, pend_offset;
- unsigned int value;
-
- group = chip->group;
- offset = s5p_gpioint_get_offset(data);
- pend_offset = REG_OFFSET(group);
-
- value = __raw_readl(GPIO_BASE(chip) + PEND_OFFSET + pend_offset);
- value |= BIT(offset);
- __raw_writel(value, GPIO_BASE(chip) + PEND_OFFSET + pend_offset);
-}
-
-static void s5p_gpioint_mask(struct irq_data *data)
-{
- struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data);
- int group, offset, mask_offset;
- unsigned int value;
-
- group = chip->group;
- offset = s5p_gpioint_get_offset(data);
- mask_offset = REG_OFFSET(group);
-
- value = __raw_readl(GPIO_BASE(chip) + MASK_OFFSET + mask_offset);
- value |= BIT(offset);
- __raw_writel(value, GPIO_BASE(chip) + MASK_OFFSET + mask_offset);
-}
-
-static void s5p_gpioint_unmask(struct irq_data *data)
-{
- struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data);
- int group, offset, mask_offset;
- unsigned int value;
-
- group = chip->group;
- offset = s5p_gpioint_get_offset(data);
- mask_offset = REG_OFFSET(group);
-
- value = __raw_readl(GPIO_BASE(chip) + MASK_OFFSET + mask_offset);
- value &= ~BIT(offset);
- __raw_writel(value, GPIO_BASE(chip) + MASK_OFFSET + mask_offset);
-}
-
-static void s5p_gpioint_mask_ack(struct irq_data *data)
-{
- s5p_gpioint_mask(data);
- s5p_gpioint_ack(data);
-}
-
-static int s5p_gpioint_set_type(struct irq_data *data, unsigned int type)
-{
- struct s3c_gpio_chip *chip = irq_data_get_irq_handler_data(data);
- int group, offset, con_offset;
- unsigned int value;
-
- group = chip->group;
- offset = s5p_gpioint_get_offset(data);
- con_offset = REG_OFFSET(group);
+ struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+ struct irq_chip_type *ct = gc->chip_types;
+ unsigned int shift = (d->irq - gc->irq_base) << 2;
switch (type) {
case IRQ_TYPE_EDGE_RISING:
@@ -130,23 +69,12 @@
return -EINVAL;
}
- value = __raw_readl(GPIO_BASE(chip) + CON_OFFSET + con_offset);
- value &= ~(0x7 << (offset * 0x4));
- value |= (type << (offset * 0x4));
- __raw_writel(value, GPIO_BASE(chip) + CON_OFFSET + con_offset);
-
+ gc->type_cache &= ~(0x7 << shift);
+ gc->type_cache |= type << shift;
+ writel(gc->type_cache, gc->reg_base + ct->regs.type);
return 0;
}
-static struct irq_chip s5p_gpioint = {
- .name = "s5p_gpioint",
- .irq_ack = s5p_gpioint_ack,
- .irq_mask = s5p_gpioint_mask,
- .irq_mask_ack = s5p_gpioint_mask_ack,
- .irq_unmask = s5p_gpioint_unmask,
- .irq_set_type = s5p_gpioint_set_type,
-};
-
static void s5p_gpioint_handler(unsigned int irq, struct irq_desc *desc)
{
struct s5p_gpioint_bank *bank = irq_get_handler_data(irq);
@@ -179,9 +107,10 @@
static __init int s5p_gpioint_add(struct s3c_gpio_chip *chip)
{
static int used_gpioint_groups = 0;
- int irq, group = chip->group;
- int i;
+ int group = chip->group;
struct s5p_gpioint_bank *bank = NULL;
+ struct irq_chip_generic *gc;
+ struct irq_chip_type *ct;
if (used_gpioint_groups >= S5P_GPIOINT_GROUP_COUNT)
return -ENOMEM;
@@ -211,19 +140,28 @@
* chained GPIO irq has been successfully registered, allocate new gpio
* int group and assign irq nubmers
*/
-
chip->irq_base = S5P_GPIOINT_BASE +
used_gpioint_groups * S5P_GPIOINT_GROUP_SIZE;
used_gpioint_groups++;
bank->chips[group - bank->start] = chip;
- for (i = 0; i < chip->chip.ngpio; i++) {
- irq = chip->irq_base + i;
- irq_set_chip(irq, &s5p_gpioint);
- irq_set_handler_data(irq, chip);
- irq_set_handler(irq, handle_level_irq);
- set_irq_flags(irq, IRQF_VALID);
- }
+
+ gc = irq_alloc_generic_chip("s5p_gpioint", 1, chip->irq_base,
+ (void __iomem *)GPIO_BASE(chip),
+ handle_level_irq);
+ if (!gc)
+ return -ENOMEM;
+ ct = gc->chip_types;
+ ct->chip.irq_ack = irq_gc_ack;
+ ct->chip.irq_mask = irq_gc_mask_set_bit;
+ ct->chip.irq_unmask = irq_gc_mask_clr_bit;
+ ct->chip.irq_set_type = s5p_gpioint_set_type,
+ ct->regs.ack = PEND_OFFSET + REG_OFFSET(chip->group);
+ ct->regs.mask = MASK_OFFSET + REG_OFFSET(chip->group);
+ ct->regs.type = CON_OFFSET + REG_OFFSET(chip->group);
+ irq_setup_generic_chip(gc, IRQ_MSK(chip->chip.ngpio),
+ IRQ_GC_INIT_MASK_CACHE,
+ IRQ_NOREQUEST | IRQ_NOPROBE, 0);
return 0;
}
diff --git a/arch/arm/plat-s5p/irq.c b/arch/arm/plat-s5p/irq.c
index 5560b12..a97c089 100644
--- a/arch/arm/plat-s5p/irq.c
+++ b/arch/arm/plat-s5p/irq.c
@@ -64,11 +64,7 @@
vic_init(VA_VIC(irq), VIC_BASE(irq), vic[irq], 0);
#endif
- s3c_init_vic_timer_irq(IRQ_TIMER0_VIC, IRQ_TIMER0);
- s3c_init_vic_timer_irq(IRQ_TIMER1_VIC, IRQ_TIMER1);
- s3c_init_vic_timer_irq(IRQ_TIMER2_VIC, IRQ_TIMER2);
- s3c_init_vic_timer_irq(IRQ_TIMER3_VIC, IRQ_TIMER3);
- s3c_init_vic_timer_irq(IRQ_TIMER4_VIC, IRQ_TIMER4);
+ s3c_init_vic_timer_irq(5, IRQ_TIMER0);
s3c_init_uart_irqs(uart_irqs, ARRAY_SIZE(uart_irqs));
}
diff --git a/arch/arm/plat-s5p/s5p-time.c b/arch/arm/plat-s5p/s5p-time.c
index 8090403..899a8cc 100644
--- a/arch/arm/plat-s5p/s5p-time.c
+++ b/arch/arm/plat-s5p/s5p-time.c
@@ -290,7 +290,7 @@
setup_irq(irq_number, &s5p_clock_event_irq);
}
-static cycle_t s5p_timer_read(struct clocksource *cs)
+static void __iomem *s5p_timer_reg(void)
{
unsigned long offset = 0;
@@ -308,10 +308,17 @@
default:
printk(KERN_ERR "Invalid Timer %d\n", timer_source.source_id);
- return 0;
+ return NULL;
}
- return (cycle_t) ~__raw_readl(S3C_TIMERREG(offset));
+ return S3C_TIMERREG(offset);
+}
+
+static cycle_t s5p_timer_read(struct clocksource *cs)
+{
+ void __iomem *reg = s5p_timer_reg();
+
+ return (cycle_t) (reg ? ~__raw_readl(reg) : 0);
}
/*
@@ -325,53 +332,22 @@
unsigned long long notrace sched_clock(void)
{
- u32 cyc;
- unsigned long offset = 0;
+ void __iomem *reg = s5p_timer_reg();
- switch (timer_source.source_id) {
- case S5P_PWM0:
- case S5P_PWM1:
- case S5P_PWM2:
- case S5P_PWM3:
- offset = (timer_source.source_id * 0x0c) + 0x14;
- break;
-
- case S5P_PWM4:
- offset = 0x40;
- break;
-
- default:
- printk(KERN_ERR "Invalid Timer %d\n", timer_source.source_id);
+ if (!reg)
return 0;
- }
- cyc = ~__raw_readl(S3C_TIMERREG(offset));
- return cyc_to_sched_clock(&cd, cyc, (u32)~0);
+ return cyc_to_sched_clock(&cd, ~__raw_readl(reg), (u32)~0);
}
static void notrace s5p_update_sched_clock(void)
{
- u32 cyc;
- unsigned long offset = 0;
+ void __iomem *reg = s5p_timer_reg();
- switch (timer_source.source_id) {
- case S5P_PWM0:
- case S5P_PWM1:
- case S5P_PWM2:
- case S5P_PWM3:
- offset = (timer_source.source_id * 0x0c) + 0x14;
- break;
+ if (!reg)
+ return;
- case S5P_PWM4:
- offset = 0x40;
- break;
-
- default:
- printk(KERN_ERR "Invalid Timer %d\n", timer_source.source_id);
- }
-
- cyc = ~__raw_readl(S3C_TIMERREG(offset));
- update_sched_clock(&cd, cyc, (u32)~0);
+ update_sched_clock(&cd, ~__raw_readl(reg), (u32)~0);
}
struct clocksource time_clocksource = {
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index be72100..4d79519 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -8,6 +8,7 @@
bool
depends on PLAT_S3C24XX || ARCH_S3C64XX || PLAT_S5P
select NO_IOPORT
+ select GENERIC_IRQ_CHIP
default y
help
Base platform code for all Samsung SoC based systems
diff --git a/arch/arm/plat-samsung/include/plat/devs.h b/arch/arm/plat-samsung/include/plat/devs.h
index f0da6b7..39818d8 100644
--- a/arch/arm/plat-samsung/include/plat/devs.h
+++ b/arch/arm/plat-samsung/include/plat/devs.h
@@ -88,6 +88,7 @@
extern struct platform_device s5p_device_onenand;
extern struct platform_device s3c_device_usbgadget;
+extern struct platform_device s3c_device_usb_hsudc;
extern struct platform_device s3c_device_usb_hsotg;
extern struct platform_device s5pv210_device_ac97;
@@ -142,6 +143,8 @@
extern struct platform_device s5p_device_mipi_csis0;
extern struct platform_device s5p_device_mipi_csis1;
+extern struct platform_device s5p_device_ehci;
+
extern struct platform_device exynos4_device_sysmmu;
/* s3c2440 specific devices */
diff --git a/arch/arm/plat-samsung/include/plat/irq-vic-timer.h b/arch/arm/plat-samsung/include/plat/irq-vic-timer.h
index a90b534..5b9c42f 100644
--- a/arch/arm/plat-samsung/include/plat/irq-vic-timer.h
+++ b/arch/arm/plat-samsung/include/plat/irq-vic-timer.h
@@ -10,4 +10,4 @@
* published by the Free Software Foundation.
*/
-extern void s3c_init_vic_timer_irq(unsigned int vic, unsigned int timer);
+extern void s3c_init_vic_timer_irq(unsigned int num, unsigned int timer_irq);
diff --git a/arch/arm/plat-samsung/include/plat/uncompress.h b/arch/arm/plat-samsung/include/plat/uncompress.h
index 7d6ed72..ee48e12 100644
--- a/arch/arm/plat-samsung/include/plat/uncompress.h
+++ b/arch/arm/plat-samsung/include/plat/uncompress.h
@@ -18,8 +18,8 @@
/* uart setup */
-static unsigned int fifo_mask;
-static unsigned int fifo_max;
+unsigned int fifo_mask;
+unsigned int fifo_max;
/* forward declerations */
diff --git a/arch/arm/plat-samsung/irq-uart.c b/arch/arm/plat-samsung/irq-uart.c
index 4d4e571..32582c0 100644
--- a/arch/arm/plat-samsung/irq-uart.c
+++ b/arch/arm/plat-samsung/irq-uart.c
@@ -27,60 +27,6 @@
/* Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3]
* are consecutive when looking up the interrupt in the demux routines.
*/
-
-static inline void __iomem *s3c_irq_uart_base(struct irq_data *data)
-{
- struct s3c_uart_irq *uirq = irq_data_get_irq_chip_data(data);
- return uirq->regs;
-}
-
-static inline unsigned int s3c_irq_uart_bit(unsigned int irq)
-{
- return irq & 3;
-}
-
-static void s3c_irq_uart_mask(struct irq_data *data)
-{
- void __iomem *regs = s3c_irq_uart_base(data);
- unsigned int bit = s3c_irq_uart_bit(data->irq);
- u32 reg;
-
- reg = __raw_readl(regs + S3C64XX_UINTM);
- reg |= (1 << bit);
- __raw_writel(reg, regs + S3C64XX_UINTM);
-}
-
-static void s3c_irq_uart_maskack(struct irq_data *data)
-{
- void __iomem *regs = s3c_irq_uart_base(data);
- unsigned int bit = s3c_irq_uart_bit(data->irq);
- u32 reg;
-
- reg = __raw_readl(regs + S3C64XX_UINTM);
- reg |= (1 << bit);
- __raw_writel(reg, regs + S3C64XX_UINTM);
- __raw_writel(1 << bit, regs + S3C64XX_UINTP);
-}
-
-static void s3c_irq_uart_unmask(struct irq_data *data)
-{
- void __iomem *regs = s3c_irq_uart_base(data);
- unsigned int bit = s3c_irq_uart_bit(data->irq);
- u32 reg;
-
- reg = __raw_readl(regs + S3C64XX_UINTM);
- reg &= ~(1 << bit);
- __raw_writel(reg, regs + S3C64XX_UINTM);
-}
-
-static void s3c_irq_uart_ack(struct irq_data *data)
-{
- void __iomem *regs = s3c_irq_uart_base(data);
- unsigned int bit = s3c_irq_uart_bit(data->irq);
-
- __raw_writel(1 << bit, regs + S3C64XX_UINTP);
-}
-
static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc)
{
struct s3c_uart_irq *uirq = desc->irq_data.handler_data;
@@ -97,30 +43,25 @@
generic_handle_irq(base + 3);
}
-static struct irq_chip s3c_irq_uart = {
- .name = "s3c-uart",
- .irq_mask = s3c_irq_uart_mask,
- .irq_unmask = s3c_irq_uart_unmask,
- .irq_mask_ack = s3c_irq_uart_maskack,
- .irq_ack = s3c_irq_uart_ack,
-};
-
static void __init s3c_init_uart_irq(struct s3c_uart_irq *uirq)
{
void __iomem *reg_base = uirq->regs;
- unsigned int irq;
- int offs;
+ struct irq_chip_generic *gc;
+ struct irq_chip_type *ct;
/* mask all interrupts at the start. */
__raw_writel(0xf, reg_base + S3C64XX_UINTM);
- for (offs = 0; offs < 3; offs++) {
- irq = uirq->base_irq + offs;
-
- irq_set_chip_and_handler(irq, &s3c_irq_uart, handle_level_irq);
- irq_set_chip_data(irq, uirq);
- set_irq_flags(irq, IRQF_VALID);
- }
+ gc = irq_alloc_generic_chip("s3c-uart", 1, uirq->base_irq, reg_base,
+ handle_level_irq);
+ ct = gc->chip_types;
+ ct->chip.irq_ack = irq_gc_ack;
+ ct->chip.irq_mask = irq_gc_mask_set_bit;
+ ct->chip.irq_unmask = irq_gc_mask_clr_bit;
+ ct->regs.ack = S3C64XX_UINTP;
+ ct->regs.mask = S3C64XX_UINTM;
+ irq_setup_generic_chip(gc, IRQ_MSK(4), IRQ_GC_INIT_MASK_CACHE,
+ IRQ_NOREQUEST | IRQ_NOPROBE, 0);
irq_set_handler_data(uirq->parent_irq, uirq);
irq_set_chained_handler(uirq->parent_irq, s3c_irq_demux_uart);
diff --git a/arch/arm/plat-samsung/irq-vic-timer.c b/arch/arm/plat-samsung/irq-vic-timer.c
index d6ad66a..a607546 100644
--- a/arch/arm/plat-samsung/irq-vic-timer.c
+++ b/arch/arm/plat-samsung/irq-vic-timer.c
@@ -28,60 +28,43 @@
}
/* We assume the IRQ_TIMER0..IRQ_TIMER4 range is continuous. */
-
-static void s3c_irq_timer_mask(struct irq_data *data)
+static void s3c_irq_timer_ack(struct irq_data *d)
{
- u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
- u32 mask = (u32)data->chip_data;
+ struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+ u32 mask = (1 << 5) << (d->irq - gc->irq_base);
- reg &= 0x1f; /* mask out pending interrupts */
- reg &= ~mask;
- __raw_writel(reg, S3C64XX_TINT_CSTAT);
+ irq_reg_writel(mask | gc->mask_cache, gc->reg_base);
}
-static void s3c_irq_timer_unmask(struct irq_data *data)
-{
- u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
- u32 mask = (u32)data->chip_data;
-
- reg &= 0x1f; /* mask out pending interrupts */
- reg |= mask;
- __raw_writel(reg, S3C64XX_TINT_CSTAT);
-}
-
-static void s3c_irq_timer_ack(struct irq_data *data)
-{
- u32 reg = __raw_readl(S3C64XX_TINT_CSTAT);
- u32 mask = (u32)data->chip_data;
-
- reg &= 0x1f;
- reg |= mask << 5;
- __raw_writel(reg, S3C64XX_TINT_CSTAT);
-}
-
-static struct irq_chip s3c_irq_timer = {
- .name = "s3c-timer",
- .irq_mask = s3c_irq_timer_mask,
- .irq_unmask = s3c_irq_timer_unmask,
- .irq_ack = s3c_irq_timer_ack,
-};
-
/**
* s3c_init_vic_timer_irq() - initialise timer irq chanined off VIC.\
- * @parent_irq: The parent IRQ on the VIC for the timer.
- * @timer_irq: The IRQ to be used for the timer.
+ * @num: Number of timers to initialize
+ * @timer_irq: Base IRQ number to be used for the timers.
*
* Register the necessary IRQ chaining and support for the timer IRQs
* chained of the VIC.
*/
-void __init s3c_init_vic_timer_irq(unsigned int parent_irq,
- unsigned int timer_irq)
+void __init s3c_init_vic_timer_irq(unsigned int num, unsigned int timer_irq)
{
+ unsigned int pirq[5] = { IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC,
+ IRQ_TIMER3_VIC, IRQ_TIMER4_VIC };
+ struct irq_chip_generic *s3c_tgc;
+ struct irq_chip_type *ct;
+ unsigned int i;
- irq_set_chained_handler(parent_irq, s3c_irq_demux_vic_timer);
- irq_set_handler_data(parent_irq, (void *)timer_irq);
+ s3c_tgc = irq_alloc_generic_chip("s3c-timer", 1, timer_irq,
+ S3C64XX_TINT_CSTAT, handle_level_irq);
+ ct = s3c_tgc->chip_types;
+ ct->chip.irq_mask = irq_gc_mask_clr_bit;
+ ct->chip.irq_unmask = irq_gc_mask_set_bit;
+ ct->chip.irq_ack = s3c_irq_timer_ack;
+ irq_setup_generic_chip(s3c_tgc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE,
+ IRQ_NOREQUEST | IRQ_NOPROBE, 0);
+ /* Clear the upper bits of the mask_cache*/
+ s3c_tgc->mask_cache &= 0x1f;
- irq_set_chip_and_handler(timer_irq, &s3c_irq_timer, handle_level_irq);
- irq_set_chip_data(timer_irq, (void *)(1 << (timer_irq - IRQ_TIMER0)));
- set_irq_flags(timer_irq, IRQF_VALID);
+ for (i = 0; i < num; i++, timer_irq++) {
+ irq_set_chained_handler(pirq[i], s3c_irq_demux_vic_timer);
+ irq_set_handler_data(pirq[i], (void *)timer_irq);
+ }
}
diff --git a/arch/arm/plat-spear/clock.c b/arch/arm/plat-spear/clock.c
index bdbd7ec..6fa474c 100644
--- a/arch/arm/plat-spear/clock.c
+++ b/arch/arm/plat-spear/clock.c
@@ -903,6 +903,11 @@
spin_unlock_irqrestore(&clocks_lock, flags);
}
+void __init clk_init(void)
+{
+ recalc_root_clocks();
+}
+
#ifdef CONFIG_DEBUG_FS
/*
* debugfs support to trace clock tree hierarchy and attributes
diff --git a/arch/arm/plat-spear/include/plat/clock.h b/arch/arm/plat-spear/include/plat/clock.h
index fcc0d0a..0062baf 100644
--- a/arch/arm/plat-spear/include/plat/clock.h
+++ b/arch/arm/plat-spear/include/plat/clock.h
@@ -224,6 +224,7 @@
};
/* platform specific clock functions */
+void __init clk_init(void);
void clk_register(struct clk_lookup *cl);
void recalc_root_clocks(void);
diff --git a/arch/arm/plat-spear/time.c b/arch/arm/plat-spear/time.c
index dbb6e4f..0c77e42 100644
--- a/arch/arm/plat-spear/time.c
+++ b/arch/arm/plat-spear/time.c
@@ -70,19 +70,6 @@
static int clockevent_next_event(unsigned long evt,
struct clock_event_device *clk_event_dev);
-static cycle_t clocksource_read_cycles(struct clocksource *cs)
-{
- return (cycle_t) readw(gpt_base + COUNT(CLKSRC));
-}
-
-static struct clocksource clksrc = {
- .name = "tmr1",
- .rating = 200, /* its a pretty decent clock */
- .read = clocksource_read_cycles,
- .mask = 0xFFFF, /* 16 bits */
- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
static void spear_clocksource_init(void)
{
u32 tick_rate;
@@ -103,7 +90,8 @@
writew(val, gpt_base + CR(CLKSRC));
/* register the clocksource */
- clocksource_register_hz(&clksrc, tick_rate);
+ clocksource_mmio_init(gpt_base + COUNT(CLKSRC), "tmr1", tick_rate,
+ 200, 16, clocksource_mmio_readw_up);
}
static struct clock_event_device clkevt = {
diff --git a/arch/arm/plat-stmp3xxx/Kconfig b/arch/arm/plat-stmp3xxx/Kconfig
deleted file mode 100644
index 2cf37c3..0000000
--- a/arch/arm/plat-stmp3xxx/Kconfig
+++ /dev/null
@@ -1,37 +0,0 @@
-if ARCH_STMP3XXX
-
-menu "Freescale STMP3xxx implementations"
-
-choice
- prompt "Select STMP3xxx chip family"
-
-config ARCH_STMP37XX
- bool "Freescale SMTP37xx"
- select CPU_ARM926T
- ---help---
- STMP37xx refers to 3700 through 3769 chips
-
-config ARCH_STMP378X
- bool "Freescale STMP378x"
- select CPU_ARM926T
- ---help---
- STMP378x refers to 3780 through 3789 chips
-
-endchoice
-
-choice
- prompt "Select STMP3xxx board type"
-
-config MACH_STMP37XX
- depends on ARCH_STMP37XX
- bool "Freescale STMP37xx development board"
-
-config MACH_STMP378X
- depends on ARCH_STMP378X
- bool "Freescale STMP378x development board"
-
-endchoice
-
-endmenu
-
-endif
diff --git a/arch/arm/plat-stmp3xxx/Makefile b/arch/arm/plat-stmp3xxx/Makefile
deleted file mode 100644
index 31dd518..0000000
--- a/arch/arm/plat-stmp3xxx/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# Makefile for the linux kernel.
-#
-# Object file lists.
-obj-y += core.o timer.o irq.o dma.o clock.o pinmux.o devices.o
diff --git a/arch/arm/plat-stmp3xxx/clock.c b/arch/arm/plat-stmp3xxx/clock.c
deleted file mode 100644
index 2e712e1..0000000
--- a/arch/arm/plat-stmp3xxx/clock.c
+++ /dev/null
@@ -1,1134 +0,0 @@
-/*
- * Clock manipulation routines for Freescale STMP37XX/STMP378X
- *
- * Author: Vitaly Wool <vital@embeddedalley.com>
- *
- * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#define DEBUG
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/init.h>
-#include <linux/clk.h>
-#include <linux/spinlock.h>
-#include <linux/errno.h>
-#include <linux/err.h>
-#include <linux/delay.h>
-#include <linux/io.h>
-#include <linux/clkdev.h>
-
-#include <asm/mach-types.h>
-#include <mach/platform.h>
-#include <mach/regs-clkctrl.h>
-
-#include "clock.h"
-
-static DEFINE_SPINLOCK(clocks_lock);
-
-static struct clk osc_24M;
-static struct clk pll_clk;
-static struct clk cpu_clk;
-static struct clk hclk;
-
-static int propagate_rate(struct clk *);
-
-static inline int clk_is_busy(struct clk *clk)
-{
- return __raw_readl(clk->busy_reg) & (1 << clk->busy_bit);
-}
-
-static inline int clk_good(struct clk *clk)
-{
- return clk && !IS_ERR(clk) && clk->ops;
-}
-
-static int std_clk_enable(struct clk *clk)
-{
- if (clk->enable_reg) {
- u32 clk_reg = __raw_readl(clk->enable_reg);
- if (clk->enable_negate)
- clk_reg &= ~(1 << clk->enable_shift);
- else
- clk_reg |= (1 << clk->enable_shift);
- __raw_writel(clk_reg, clk->enable_reg);
- if (clk->enable_wait)
- udelay(clk->enable_wait);
- return 0;
- } else
- return -EINVAL;
-}
-
-static int std_clk_disable(struct clk *clk)
-{
- if (clk->enable_reg) {
- u32 clk_reg = __raw_readl(clk->enable_reg);
- if (clk->enable_negate)
- clk_reg |= (1 << clk->enable_shift);
- else
- clk_reg &= ~(1 << clk->enable_shift);
- __raw_writel(clk_reg, clk->enable_reg);
- return 0;
- } else
- return -EINVAL;
-}
-
-static int io_set_rate(struct clk *clk, u32 rate)
-{
- u32 reg_frac, clkctrl_frac;
- int i, ret = 0, mask = 0x1f;
-
- clkctrl_frac = (clk->parent->rate * 18 + rate - 1) / rate;
-
- if (clkctrl_frac < 18 || clkctrl_frac > 35) {
- ret = -EINVAL;
- goto out;
- }
-
- reg_frac = __raw_readl(clk->scale_reg);
- reg_frac &= ~(mask << clk->scale_shift);
- __raw_writel(reg_frac | (clkctrl_frac << clk->scale_shift),
- clk->scale_reg);
- if (clk->busy_reg) {
- for (i = 10000; i; i--)
- if (!clk_is_busy(clk))
- break;
- if (!i)
- ret = -ETIMEDOUT;
- else
- ret = 0;
- }
-out:
- return ret;
-}
-
-static long io_get_rate(struct clk *clk)
-{
- long rate = clk->parent->rate * 18;
- int mask = 0x1f;
-
- rate /= (__raw_readl(clk->scale_reg) >> clk->scale_shift) & mask;
- clk->rate = rate;
-
- return rate;
-}
-
-static long per_get_rate(struct clk *clk)
-{
- long rate = clk->parent->rate;
- long div;
- const int mask = 0xff;
-
- if (clk->enable_reg &&
- !(__raw_readl(clk->enable_reg) & clk->enable_shift))
- clk->rate = 0;
- else {
- div = (__raw_readl(clk->scale_reg) >> clk->scale_shift) & mask;
- if (div)
- rate /= div;
- clk->rate = rate;
- }
-
- return clk->rate;
-}
-
-static int per_set_rate(struct clk *clk, u32 rate)
-{
- int ret = -EINVAL;
- int div = (clk->parent->rate + rate - 1) / rate;
- u32 reg_frac;
- const int mask = 0xff;
- int try = 10;
- int i = -1;
-
- if (div == 0 || div > mask)
- goto out;
-
- reg_frac = __raw_readl(clk->scale_reg);
- reg_frac &= ~(mask << clk->scale_shift);
-
- while (try--) {
- __raw_writel(reg_frac | (div << clk->scale_shift),
- clk->scale_reg);
-
- if (clk->busy_reg) {
- for (i = 10000; i; i--)
- if (!clk_is_busy(clk))
- break;
- }
- if (i)
- break;
- }
-
- if (!i)
- ret = -ETIMEDOUT;
- else
- ret = 0;
-
-out:
- if (ret != 0)
- printk(KERN_ERR "%s: error %d\n", __func__, ret);
- return ret;
-}
-
-static long lcdif_get_rate(struct clk *clk)
-{
- long rate = clk->parent->rate;
- long div;
- const int mask = 0xff;
-
- div = (__raw_readl(clk->scale_reg) >> clk->scale_shift) & mask;
- if (div) {
- rate /= div;
- div = (__raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC) &
- BM_CLKCTRL_FRAC_PIXFRAC) >> BP_CLKCTRL_FRAC_PIXFRAC;
- rate /= div;
- }
- clk->rate = rate;
-
- return rate;
-}
-
-static int lcdif_set_rate(struct clk *clk, u32 rate)
-{
- int ret = 0;
- /*
- * On 3700, we can get most timings exact by modifying ref_pix
- * and the divider, but keeping the phase timings at 1 (2
- * phases per cycle).
- *
- * ref_pix can be between 480e6*18/35=246.9MHz and 480e6*18/18=480MHz,
- * which is between 18/(18*480e6)=2.084ns and 35/(18*480e6)=4.050ns.
- *
- * ns_cycle >= 2*18e3/(18*480) = 25/6
- * ns_cycle <= 2*35e3/(18*480) = 875/108
- *
- * Multiply the ns_cycle by 'div' to lengthen it until it fits the
- * bounds. This is the divider we'll use after ref_pix.
- *
- * 6 * ns_cycle >= 25 * div
- * 108 * ns_cycle <= 875 * div
- */
- u32 ns_cycle = 1000000 / rate;
- u32 div, reg_val;
- u32 lowest_result = (u32) -1;
- u32 lowest_div = 0, lowest_fracdiv = 0;
-
- for (div = 1; div < 256; ++div) {
- u32 fracdiv;
- u32 ps_result;
- int lower_bound = 6 * ns_cycle >= 25 * div;
- int upper_bound = 108 * ns_cycle <= 875 * div;
- if (!lower_bound)
- break;
- if (!upper_bound)
- continue;
- /*
- * Found a matching div. Calculate fractional divider needed,
- * rounded up.
- */
- fracdiv = ((clk->parent->rate / 1000 * 18 / 2) *
- ns_cycle + 1000 * div - 1) /
- (1000 * div);
- if (fracdiv < 18 || fracdiv > 35) {
- ret = -EINVAL;
- goto out;
- }
- /* Calculate the actual cycle time this results in */
- ps_result = 6250 * div * fracdiv / 27;
-
- /* Use the fastest result that doesn't break ns_cycle */
- if (ps_result <= lowest_result) {
- lowest_result = ps_result;
- lowest_div = div;
- lowest_fracdiv = fracdiv;
- }
- }
-
- if (div >= 256 || lowest_result == (u32) -1) {
- ret = -EINVAL;
- goto out;
- }
- pr_debug("Programming PFD=%u,DIV=%u ref_pix=%uMHz "
- "PIXCLK=%uMHz cycle=%u.%03uns\n",
- lowest_fracdiv, lowest_div,
- 480*18/lowest_fracdiv, 480*18/lowest_fracdiv/lowest_div,
- lowest_result / 1000, lowest_result % 1000);
-
- /* Program ref_pix phase fractional divider */
- reg_val = __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC);
- reg_val &= ~BM_CLKCTRL_FRAC_PIXFRAC;
- reg_val |= BF(lowest_fracdiv, CLKCTRL_FRAC_PIXFRAC);
- __raw_writel(reg_val, REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC);
-
- /* Ungate PFD */
- stmp3xxx_clearl(BM_CLKCTRL_FRAC_CLKGATEPIX,
- REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC);
-
- /* Program pix divider */
- reg_val = __raw_readl(clk->scale_reg);
- reg_val &= ~(BM_CLKCTRL_PIX_DIV | BM_CLKCTRL_PIX_CLKGATE);
- reg_val |= BF(lowest_div, CLKCTRL_PIX_DIV);
- __raw_writel(reg_val, clk->scale_reg);
-
- /* Wait for divider update */
- if (clk->busy_reg) {
- int i;
- for (i = 10000; i; i--)
- if (!clk_is_busy(clk))
- break;
- if (!i) {
- ret = -ETIMEDOUT;
- goto out;
- }
- }
-
- /* Switch to ref_pix source */
- reg_val = __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ);
- reg_val &= ~BM_CLKCTRL_CLKSEQ_BYPASS_PIX;
- __raw_writel(reg_val, REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ);
-
-out:
- return ret;
-}
-
-
-static int cpu_set_rate(struct clk *clk, u32 rate)
-{
- u32 reg_val;
-
- if (rate < 24000)
- return -EINVAL;
- else if (rate == 24000) {
- /* switch to the 24M source */
- clk_set_parent(clk, &osc_24M);
- } else {
- int i;
- u32 clkctrl_cpu = 1;
- u32 c = clkctrl_cpu;
- u32 clkctrl_frac = 1;
- u32 val;
- for ( ; c < 0x40; c++) {
- u32 f = (pll_clk.rate*18/c + rate/2) / rate;
- int s1, s2;
-
- if (f < 18 || f > 35)
- continue;
- s1 = pll_clk.rate*18/clkctrl_frac/clkctrl_cpu - rate;
- s2 = pll_clk.rate*18/c/f - rate;
- pr_debug("%s: s1 %d, s2 %d\n", __func__, s1, s2);
- if (abs(s1) > abs(s2)) {
- clkctrl_cpu = c;
- clkctrl_frac = f;
- }
- if (s2 == 0)
- break;
- };
- pr_debug("%s: clkctrl_cpu %d, clkctrl_frac %d\n", __func__,
- clkctrl_cpu, clkctrl_frac);
- if (c == 0x40) {
- int d = pll_clk.rate*18/clkctrl_frac/clkctrl_cpu -
- rate;
- if (abs(d) > 100 ||
- clkctrl_frac < 18 || clkctrl_frac > 35)
- return -EINVAL;
- }
-
- /* 4.6.2 */
- val = __raw_readl(clk->scale_reg);
- val &= ~(0x3f << clk->scale_shift);
- val |= clkctrl_frac;
- clk_set_parent(clk, &osc_24M);
- udelay(10);
- __raw_writel(val, clk->scale_reg);
- /* ungate */
- __raw_writel(1<<7, clk->scale_reg + 8);
- /* write clkctrl_cpu */
- clk->saved_div = clkctrl_cpu;
-
- reg_val = __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU);
- reg_val &= ~0x3F;
- reg_val |= clkctrl_cpu;
- __raw_writel(reg_val, REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU);
-
- for (i = 10000; i; i--)
- if (!clk_is_busy(clk))
- break;
- if (!i) {
- printk(KERN_ERR "couldn't set up CPU divisor\n");
- return -ETIMEDOUT;
- }
- clk_set_parent(clk, &pll_clk);
- clk->saved_div = 0;
- udelay(10);
- }
- return 0;
-}
-
-static long cpu_get_rate(struct clk *clk)
-{
- long rate = clk->parent->rate * 18;
-
- rate /= (__raw_readl(clk->scale_reg) >> clk->scale_shift) & 0x3f;
- rate /= __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU) & 0x3f;
- rate = ((rate + 9) / 10) * 10;
- clk->rate = rate;
-
- return rate;
-}
-
-static long cpu_round_rate(struct clk *clk, u32 rate)
-{
- unsigned long r = 0;
-
- if (rate <= 24000)
- r = 24000;
- else {
- u32 clkctrl_cpu = 1;
- u32 clkctrl_frac;
- do {
- clkctrl_frac =
- (pll_clk.rate*18 / clkctrl_cpu + rate/2) / rate;
- if (clkctrl_frac > 35)
- continue;
- if (pll_clk.rate*18 / clkctrl_frac / clkctrl_cpu/10 ==
- rate / 10)
- break;
- } while (pll_clk.rate / 2 >= clkctrl_cpu++ * rate);
- if (pll_clk.rate / 2 < (clkctrl_cpu - 1) * rate)
- clkctrl_cpu--;
- pr_debug("%s: clkctrl_cpu %d, clkctrl_frac %d\n", __func__,
- clkctrl_cpu, clkctrl_frac);
- if (clkctrl_frac < 18)
- clkctrl_frac = 18;
- if (clkctrl_frac > 35)
- clkctrl_frac = 35;
-
- r = pll_clk.rate * 18;
- r /= clkctrl_frac;
- r /= clkctrl_cpu;
- r = 10 * ((r + 9) / 10);
- }
- return r;
-}
-
-static long emi_get_rate(struct clk *clk)
-{
- long rate = clk->parent->rate * 18;
-
- rate /= (__raw_readl(clk->scale_reg) >> clk->scale_shift) & 0x3f;
- rate /= __raw_readl(REGS_CLKCTRL_BASE + HW_CLKCTRL_EMI) & 0x3f;
- clk->rate = rate;
-
- return rate;
-}
-
-static int clkseq_set_parent(struct clk *clk, struct clk *parent)
-{
- int ret = -EINVAL;
- int shift = 8;
-
- /* bypass? */
- if (parent == &osc_24M)
- shift = 4;
-
- if (clk->bypass_reg) {
-#ifdef CONFIG_ARCH_STMP378X
- u32 hbus_val, cpu_val;
-
- if (clk == &cpu_clk && shift == 4) {
- hbus_val = __raw_readl(REGS_CLKCTRL_BASE +
- HW_CLKCTRL_HBUS);
- cpu_val = __raw_readl(REGS_CLKCTRL_BASE +
- HW_CLKCTRL_CPU);
-
- hbus_val &= ~(BM_CLKCTRL_HBUS_DIV_FRAC_EN |
- BM_CLKCTRL_HBUS_DIV);
- clk->saved_div = cpu_val & BM_CLKCTRL_CPU_DIV_CPU;
- cpu_val &= ~BM_CLKCTRL_CPU_DIV_CPU;
- cpu_val |= 1;
-
- if (machine_is_stmp378x()) {
- __raw_writel(hbus_val,
- REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS);
- __raw_writel(cpu_val,
- REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU);
- hclk.rate = 0;
- }
- } else if (clk == &cpu_clk && shift == 8) {
- hbus_val = __raw_readl(REGS_CLKCTRL_BASE +
- HW_CLKCTRL_HBUS);
- cpu_val = __raw_readl(REGS_CLKCTRL_BASE +
- HW_CLKCTRL_CPU);
- hbus_val &= ~(BM_CLKCTRL_HBUS_DIV_FRAC_EN |
- BM_CLKCTRL_HBUS_DIV);
- hbus_val |= 2;
- cpu_val &= ~BM_CLKCTRL_CPU_DIV_CPU;
- if (clk->saved_div)
- cpu_val |= clk->saved_div;
- else
- cpu_val |= 2;
-
- if (machine_is_stmp378x()) {
- __raw_writel(hbus_val,
- REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS);
- __raw_writel(cpu_val,
- REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU);
- hclk.rate = 0;
- }
- }
-#endif
- __raw_writel(1 << clk->bypass_shift, clk->bypass_reg + shift);
-
- ret = 0;
- }
-
- return ret;
-}
-
-static int hbus_set_rate(struct clk *clk, u32 rate)
-{
- u8 div = 0;
- int is_frac = 0;
- u32 clkctrl_hbus;
- struct clk *parent = clk->parent;
-
- pr_debug("%s: rate %d, parent rate %d\n", __func__, rate,
- parent->rate);
-
- if (rate > parent->rate)
- return -EINVAL;
-
- if (((parent->rate + rate/2) / rate) * rate != parent->rate &&
- parent->rate / rate < 32) {
- pr_debug("%s: switching to fractional mode\n", __func__);
- is_frac = 1;
- }
-
- if (is_frac)
- div = (32 * rate + parent->rate / 2) / parent->rate;
- else
- div = (parent->rate + rate - 1) / rate;
- pr_debug("%s: div calculated is %d\n", __func__, div);
- if (!div || div > 0x1f)
- return -EINVAL;
-
- clk_set_parent(&cpu_clk, &osc_24M);
- udelay(10);
- clkctrl_hbus = __raw_readl(clk->scale_reg);
- clkctrl_hbus &= ~0x3f;
- clkctrl_hbus |= div;
- clkctrl_hbus |= (is_frac << 5);
-
- __raw_writel(clkctrl_hbus, clk->scale_reg);
- if (clk->busy_reg) {
- int i;
- for (i = 10000; i; i--)
- if (!clk_is_busy(clk))
- break;
- if (!i) {
- printk(KERN_ERR "couldn't set up CPU divisor\n");
- return -ETIMEDOUT;
- }
- }
- clk_set_parent(&cpu_clk, &pll_clk);
- __raw_writel(clkctrl_hbus, clk->scale_reg);
- udelay(10);
- return 0;
-}
-
-static long hbus_get_rate(struct clk *clk)
-{
- long rate = clk->parent->rate;
-
- if (__raw_readl(clk->scale_reg) & 0x20) {
- rate *= __raw_readl(clk->scale_reg) & 0x1f;
- rate /= 32;
- } else
- rate /= __raw_readl(clk->scale_reg) & 0x1f;
- clk->rate = rate;
-
- return rate;
-}
-
-static int xbus_set_rate(struct clk *clk, u32 rate)
-{
- u16 div = 0;
- u32 clkctrl_xbus;
-
- pr_debug("%s: rate %d, parent rate %d\n", __func__, rate,
- clk->parent->rate);
-
- div = (clk->parent->rate + rate - 1) / rate;
- pr_debug("%s: div calculated is %d\n", __func__, div);
- if (!div || div > 0x3ff)
- return -EINVAL;
-
- clkctrl_xbus = __raw_readl(clk->scale_reg);
- clkctrl_xbus &= ~0x3ff;
- clkctrl_xbus |= div;
- __raw_writel(clkctrl_xbus, clk->scale_reg);
- if (clk->busy_reg) {
- int i;
- for (i = 10000; i; i--)
- if (!clk_is_busy(clk))
- break;
- if (!i) {
- printk(KERN_ERR "couldn't set up xbus divisor\n");
- return -ETIMEDOUT;
- }
- }
- return 0;
-}
-
-static long xbus_get_rate(struct clk *clk)
-{
- long rate = clk->parent->rate;
-
- rate /= __raw_readl(clk->scale_reg) & 0x3ff;
- clk->rate = rate;
-
- return rate;
-}
-
-
-/* Clock ops */
-
-static struct clk_ops std_ops = {
- .enable = std_clk_enable,
- .disable = std_clk_disable,
- .get_rate = per_get_rate,
- .set_rate = per_set_rate,
- .set_parent = clkseq_set_parent,
-};
-
-static struct clk_ops min_ops = {
- .enable = std_clk_enable,
- .disable = std_clk_disable,
-};
-
-static struct clk_ops cpu_ops = {
- .enable = std_clk_enable,
- .disable = std_clk_disable,
- .get_rate = cpu_get_rate,
- .set_rate = cpu_set_rate,
- .round_rate = cpu_round_rate,
- .set_parent = clkseq_set_parent,
-};
-
-static struct clk_ops io_ops = {
- .enable = std_clk_enable,
- .disable = std_clk_disable,
- .get_rate = io_get_rate,
- .set_rate = io_set_rate,
-};
-
-static struct clk_ops hbus_ops = {
- .get_rate = hbus_get_rate,
- .set_rate = hbus_set_rate,
-};
-
-static struct clk_ops xbus_ops = {
- .get_rate = xbus_get_rate,
- .set_rate = xbus_set_rate,
-};
-
-static struct clk_ops lcdif_ops = {
- .enable = std_clk_enable,
- .disable = std_clk_disable,
- .get_rate = lcdif_get_rate,
- .set_rate = lcdif_set_rate,
- .set_parent = clkseq_set_parent,
-};
-
-static struct clk_ops emi_ops = {
- .get_rate = emi_get_rate,
-};
-
-/* List of on-chip clocks */
-
-static struct clk osc_24M = {
- .flags = FIXED_RATE | ENABLED,
- .rate = 24000,
-};
-
-static struct clk pll_clk = {
- .parent = &osc_24M,
- .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PLLCTRL0,
- .enable_shift = 16,
- .enable_wait = 10,
- .flags = FIXED_RATE | ENABLED,
- .rate = 480000,
- .ops = &min_ops,
-};
-
-static struct clk cpu_clk = {
- .parent = &pll_clk,
- .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC,
- .scale_shift = 0,
- .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
- .bypass_shift = 7,
- .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CPU,
- .busy_bit = 28,
- .flags = RATE_PROPAGATES | ENABLED,
- .ops = &cpu_ops,
-};
-
-static struct clk io_clk = {
- .parent = &pll_clk,
- .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC,
- .enable_shift = 31,
- .enable_negate = 1,
- .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC,
- .scale_shift = 24,
- .flags = RATE_PROPAGATES | ENABLED,
- .ops = &io_ops,
-};
-
-static struct clk hclk = {
- .parent = &cpu_clk,
- .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS,
- .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
- .bypass_shift = 7,
- .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS,
- .busy_bit = 29,
- .flags = RATE_PROPAGATES | ENABLED,
- .ops = &hbus_ops,
-};
-
-static struct clk xclk = {
- .parent = &osc_24M,
- .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XBUS,
- .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XBUS,
- .busy_bit = 31,
- .flags = RATE_PROPAGATES | ENABLED,
- .ops = &xbus_ops,
-};
-
-static struct clk uart_clk = {
- .parent = &xclk,
- .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
- .enable_shift = 31,
- .enable_negate = 1,
- .flags = ENABLED,
- .ops = &min_ops,
-};
-
-static struct clk audio_clk = {
- .parent = &xclk,
- .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
- .enable_shift = 30,
- .enable_negate = 1,
- .ops = &min_ops,
-};
-
-static struct clk pwm_clk = {
- .parent = &xclk,
- .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
- .enable_shift = 29,
- .enable_negate = 1,
- .ops = &min_ops,
-};
-
-static struct clk dri_clk = {
- .parent = &xclk,
- .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
- .enable_shift = 28,
- .enable_negate = 1,
- .ops = &min_ops,
-};
-
-static struct clk digctl_clk = {
- .parent = &xclk,
- .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
- .enable_shift = 27,
- .enable_negate = 1,
- .ops = &min_ops,
-};
-
-static struct clk timer_clk = {
- .parent = &xclk,
- .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_XTAL,
- .enable_shift = 26,
- .enable_negate = 1,
- .flags = ENABLED,
- .ops = &min_ops,
-};
-
-static struct clk lcdif_clk = {
- .parent = &pll_clk,
- .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PIX,
- .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PIX,
- .busy_bit = 29,
- .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PIX,
- .enable_shift = 31,
- .enable_negate = 1,
- .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
- .bypass_shift = 1,
- .flags = NEEDS_SET_PARENT,
- .ops = &lcdif_ops,
-};
-
-static struct clk ssp_clk = {
- .parent = &io_clk,
- .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SSP,
- .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SSP,
- .busy_bit = 29,
- .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SSP,
- .enable_shift = 31,
- .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
- .bypass_shift = 5,
- .enable_negate = 1,
- .flags = NEEDS_SET_PARENT,
- .ops = &std_ops,
-};
-
-static struct clk gpmi_clk = {
- .parent = &io_clk,
- .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_GPMI,
- .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_GPMI,
- .busy_bit = 29,
- .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_GPMI,
- .enable_shift = 31,
- .enable_negate = 1,
- .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
- .bypass_shift = 4,
- .flags = NEEDS_SET_PARENT,
- .ops = &std_ops,
-};
-
-static struct clk spdif_clk = {
- .parent = &pll_clk,
- .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SPDIF,
- .enable_shift = 31,
- .enable_negate = 1,
- .ops = &min_ops,
-};
-
-static struct clk emi_clk = {
- .parent = &pll_clk,
- .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_EMI,
- .enable_shift = 31,
- .enable_negate = 1,
- .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_FRAC,
- .scale_shift = 8,
- .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_EMI,
- .busy_bit = 28,
- .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
- .bypass_shift = 6,
- .flags = ENABLED,
- .ops = &emi_ops,
-};
-
-static struct clk ir_clk = {
- .parent = &io_clk,
- .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_IR,
- .enable_shift = 31,
- .enable_negate = 1,
- .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
- .bypass_shift = 3,
- .ops = &min_ops,
-};
-
-static struct clk saif_clk = {
- .parent = &pll_clk,
- .scale_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SAIF,
- .busy_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SAIF,
- .busy_bit = 29,
- .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_SAIF,
- .enable_shift = 31,
- .enable_negate = 1,
- .bypass_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_CLKSEQ,
- .bypass_shift = 0,
- .ops = &std_ops,
-};
-
-static struct clk usb_clk = {
- .parent = &pll_clk,
- .enable_reg = REGS_CLKCTRL_BASE + HW_CLKCTRL_PLLCTRL0,
- .enable_shift = 18,
- .enable_negate = 1,
- .ops = &min_ops,
-};
-
-/* list of all the clocks */
-static struct clk_lookup onchip_clks[] = {
- {
- .con_id = "osc_24M",
- .clk = &osc_24M,
- }, {
- .con_id = "pll",
- .clk = &pll_clk,
- }, {
- .con_id = "cpu",
- .clk = &cpu_clk,
- }, {
- .con_id = "hclk",
- .clk = &hclk,
- }, {
- .con_id = "xclk",
- .clk = &xclk,
- }, {
- .con_id = "io",
- .clk = &io_clk,
- }, {
- .con_id = "uart",
- .clk = &uart_clk,
- }, {
- .con_id = "audio",
- .clk = &audio_clk,
- }, {
- .con_id = "pwm",
- .clk = &pwm_clk,
- }, {
- .con_id = "dri",
- .clk = &dri_clk,
- }, {
- .con_id = "digctl",
- .clk = &digctl_clk,
- }, {
- .con_id = "timer",
- .clk = &timer_clk,
- }, {
- .con_id = "lcdif",
- .clk = &lcdif_clk,
- }, {
- .con_id = "ssp",
- .clk = &ssp_clk,
- }, {
- .con_id = "gpmi",
- .clk = &gpmi_clk,
- }, {
- .con_id = "spdif",
- .clk = &spdif_clk,
- }, {
- .con_id = "emi",
- .clk = &emi_clk,
- }, {
- .con_id = "ir",
- .clk = &ir_clk,
- }, {
- .con_id = "saif",
- .clk = &saif_clk,
- }, {
- .con_id = "usb",
- .clk = &usb_clk,
- },
-};
-
-static int __init propagate_rate(struct clk *clk)
-{
- struct clk_lookup *cl;
-
- for (cl = onchip_clks; cl < onchip_clks + ARRAY_SIZE(onchip_clks);
- cl++) {
- if (unlikely(!clk_good(cl->clk)))
- continue;
- if (cl->clk->parent == clk && cl->clk->ops->get_rate) {
- cl->clk->ops->get_rate(cl->clk);
- if (cl->clk->flags & RATE_PROPAGATES)
- propagate_rate(cl->clk);
- }
- }
-
- return 0;
-}
-
-/* Exported API */
-unsigned long clk_get_rate(struct clk *clk)
-{
- if (unlikely(!clk_good(clk)))
- return 0;
-
- if (clk->rate != 0)
- return clk->rate;
-
- if (clk->ops->get_rate != NULL)
- return clk->ops->get_rate(clk);
-
- return clk_get_rate(clk->parent);
-}
-EXPORT_SYMBOL(clk_get_rate);
-
-long clk_round_rate(struct clk *clk, unsigned long rate)
-{
- if (unlikely(!clk_good(clk)))
- return 0;
-
- if (clk->ops->round_rate)
- return clk->ops->round_rate(clk, rate);
-
- return 0;
-}
-EXPORT_SYMBOL(clk_round_rate);
-
-static inline int close_enough(long rate1, long rate2)
-{
- return rate1 && !((rate2 - rate1) * 1000 / rate1);
-}
-
-int clk_set_rate(struct clk *clk, unsigned long rate)
-{
- int ret = -EINVAL;
-
- if (unlikely(!clk_good(clk)))
- goto out;
-
- if (clk->flags & FIXED_RATE || !clk->ops->set_rate)
- goto out;
-
- else if (!close_enough(clk->rate, rate)) {
- ret = clk->ops->set_rate(clk, rate);
- if (ret < 0)
- goto out;
- clk->rate = rate;
- if (clk->flags & RATE_PROPAGATES)
- propagate_rate(clk);
- } else
- ret = 0;
-
-out:
- return ret;
-}
-EXPORT_SYMBOL(clk_set_rate);
-
-int clk_enable(struct clk *clk)
-{
- unsigned long clocks_flags;
-
- if (unlikely(!clk_good(clk)))
- return -EINVAL;
-
- if (clk->parent)
- clk_enable(clk->parent);
-
- spin_lock_irqsave(&clocks_lock, clocks_flags);
-
- clk->usage++;
- if (clk->ops && clk->ops->enable)
- clk->ops->enable(clk);
-
- spin_unlock_irqrestore(&clocks_lock, clocks_flags);
- return 0;
-}
-EXPORT_SYMBOL(clk_enable);
-
-static void local_clk_disable(struct clk *clk)
-{
- if (unlikely(!clk_good(clk)))
- return;
-
- if (clk->usage == 0 && clk->ops->disable)
- clk->ops->disable(clk);
-
- if (clk->parent)
- local_clk_disable(clk->parent);
-}
-
-void clk_disable(struct clk *clk)
-{
- unsigned long clocks_flags;
-
- if (unlikely(!clk_good(clk)))
- return;
-
- spin_lock_irqsave(&clocks_lock, clocks_flags);
-
- if ((--clk->usage) == 0 && clk->ops->disable)
- clk->ops->disable(clk);
-
- spin_unlock_irqrestore(&clocks_lock, clocks_flags);
- if (clk->parent)
- clk_disable(clk->parent);
-}
-EXPORT_SYMBOL(clk_disable);
-
-/* Some additional API */
-int clk_set_parent(struct clk *clk, struct clk *parent)
-{
- int ret = -ENODEV;
- unsigned long clocks_flags;
-
- if (unlikely(!clk_good(clk)))
- goto out;
-
- if (!clk->ops->set_parent)
- goto out;
-
- spin_lock_irqsave(&clocks_lock, clocks_flags);
-
- ret = clk->ops->set_parent(clk, parent);
- if (!ret) {
- /* disable if usage count is 0 */
- local_clk_disable(parent);
-
- parent->usage += clk->usage;
- clk->parent->usage -= clk->usage;
-
- /* disable if new usage count is 0 */
- local_clk_disable(clk->parent);
-
- clk->parent = parent;
- }
- spin_unlock_irqrestore(&clocks_lock, clocks_flags);
-
-out:
- return ret;
-}
-EXPORT_SYMBOL(clk_set_parent);
-
-struct clk *clk_get_parent(struct clk *clk)
-{
- if (unlikely(!clk_good(clk)))
- return NULL;
- return clk->parent;
-}
-EXPORT_SYMBOL(clk_get_parent);
-
-static int __init clk_init(void)
-{
- struct clk_lookup *cl;
- struct clk_ops *ops;
-
- spin_lock_init(&clocks_lock);
-
- for (cl = onchip_clks; cl < onchip_clks + ARRAY_SIZE(onchip_clks);
- cl++) {
- if (cl->clk->flags & ENABLED)
- clk_enable(cl->clk);
- else
- local_clk_disable(cl->clk);
-
- ops = cl->clk->ops;
-
- if ((cl->clk->flags & NEEDS_INITIALIZATION) &&
- ops && ops->set_rate)
- ops->set_rate(cl->clk, cl->clk->rate);
-
- if (cl->clk->flags & FIXED_RATE) {
- if (cl->clk->flags & RATE_PROPAGATES)
- propagate_rate(cl->clk);
- } else {
- if (ops && ops->get_rate)
- ops->get_rate(cl->clk);
- }
-
- if (cl->clk->flags & NEEDS_SET_PARENT) {
- if (ops && ops->set_parent)
- ops->set_parent(cl->clk, cl->clk->parent);
- }
- }
- clkdev_add_table(onchip_clks, ARRAY_SIZE(onchip_clks));
- return 0;
-}
-
-arch_initcall(clk_init);
diff --git a/arch/arm/plat-stmp3xxx/clock.h b/arch/arm/plat-stmp3xxx/clock.h
deleted file mode 100644
index a6611e1..0000000
--- a/arch/arm/plat-stmp3xxx/clock.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * Clock control driver for Freescale STMP37XX/STMP378X - internal header file
- *
- * Author: Vitaly Wool <vital@embeddedalley.com>
- *
- * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#ifndef __ARCH_ARM_STMX3XXX_CLOCK_H__
-#define __ARCH_ARM_STMX3XXX_CLOCK_H__
-
-#ifndef __ASSEMBLER__
-
-struct clk_ops {
- int (*enable) (struct clk *);
- int (*disable) (struct clk *);
- long (*get_rate) (struct clk *);
- long (*round_rate) (struct clk *, u32);
- int (*set_rate) (struct clk *, u32);
- int (*set_parent) (struct clk *, struct clk *);
-};
-
-struct clk {
- struct clk *parent;
- u32 rate;
- u32 flags;
- u8 scale_shift;
- u8 enable_shift;
- u8 bypass_shift;
- u8 busy_bit;
- s8 usage;
- int enable_wait;
- int enable_negate;
- u32 saved_div;
- void __iomem *enable_reg;
- void __iomem *scale_reg;
- void __iomem *bypass_reg;
- void __iomem *busy_reg;
- struct clk_ops *ops;
-};
-
-#endif /* __ASSEMBLER__ */
-
-/* Flags */
-#define RATE_PROPAGATES (1<<0)
-#define NEEDS_INITIALIZATION (1<<1)
-#define PARENT_SET_RATE (1<<2)
-#define FIXED_RATE (1<<3)
-#define ENABLED (1<<4)
-#define NEEDS_SET_PARENT (1<<5)
-
-#endif
diff --git a/arch/arm/plat-stmp3xxx/core.c b/arch/arm/plat-stmp3xxx/core.c
deleted file mode 100644
index 37b8a09..0000000
--- a/arch/arm/plat-stmp3xxx/core.c
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * Freescale STMP37XX/STMP378X core routines
- *
- * Embedded Alley Solutions, Inc <source@embeddedalley.com>
- *
- * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/io.h>
-
-#include <mach/stmp3xxx.h>
-#include <mach/platform.h>
-#include <mach/dma.h>
-#include <mach/regs-clkctrl.h>
-
-static int __stmp3xxx_reset_block(void __iomem *hwreg, int just_enable)
-{
- u32 c;
- int timeout;
-
- /* the process of software reset of IP block is done
- in several steps:
-
- - clear SFTRST and wait for block is enabled;
- - clear clock gating (CLKGATE bit);
- - set the SFTRST again and wait for block is in reset;
- - clear SFTRST and wait for reset completion.
- */
- c = __raw_readl(hwreg);
- c &= ~(1<<31); /* clear SFTRST */
- __raw_writel(c, hwreg);
- for (timeout = 1000000; timeout > 0; timeout--)
- /* still in SFTRST state ? */
- if ((__raw_readl(hwreg) & (1<<31)) == 0)
- break;
- if (timeout <= 0) {
- printk(KERN_ERR"%s(%p): timeout when enabling\n",
- __func__, hwreg);
- return -ETIME;
- }
-
- c = __raw_readl(hwreg);
- c &= ~(1<<30); /* clear CLKGATE */
- __raw_writel(c, hwreg);
-
- if (!just_enable) {
- c = __raw_readl(hwreg);
- c |= (1<<31); /* now again set SFTRST */
- __raw_writel(c, hwreg);
- for (timeout = 1000000; timeout > 0; timeout--)
- /* poll until CLKGATE set */
- if (__raw_readl(hwreg) & (1<<30))
- break;
- if (timeout <= 0) {
- printk(KERN_ERR"%s(%p): timeout when resetting\n",
- __func__, hwreg);
- return -ETIME;
- }
-
- c = __raw_readl(hwreg);
- c &= ~(1<<31); /* clear SFTRST */
- __raw_writel(c, hwreg);
- for (timeout = 1000000; timeout > 0; timeout--)
- /* still in SFTRST state ? */
- if ((__raw_readl(hwreg) & (1<<31)) == 0)
- break;
- if (timeout <= 0) {
- printk(KERN_ERR"%s(%p): timeout when enabling "
- "after reset\n", __func__, hwreg);
- return -ETIME;
- }
-
- c = __raw_readl(hwreg);
- c &= ~(1<<30); /* clear CLKGATE */
- __raw_writel(c, hwreg);
- }
- for (timeout = 1000000; timeout > 0; timeout--)
- /* still in SFTRST state ? */
- if ((__raw_readl(hwreg) & (1<<30)) == 0)
- break;
-
- if (timeout <= 0) {
- printk(KERN_ERR"%s(%p): timeout when unclockgating\n",
- __func__, hwreg);
- return -ETIME;
- }
-
- return 0;
-}
-
-int stmp3xxx_reset_block(void __iomem *hwreg, int just_enable)
-{
- int try = 10;
- int r;
-
- while (try--) {
- r = __stmp3xxx_reset_block(hwreg, just_enable);
- if (!r)
- break;
- pr_debug("%s: try %d failed\n", __func__, 10 - try);
- }
- return r;
-}
-EXPORT_SYMBOL(stmp3xxx_reset_block);
-
-struct platform_device stmp3xxx_dbguart = {
- .name = "stmp3xxx-dbguart",
- .id = -1,
-};
-
-void __init stmp3xxx_init(void)
-{
- /* Turn off auto-slow and other tricks */
- stmp3xxx_clearl(0x7f00000, REGS_CLKCTRL_BASE + HW_CLKCTRL_HBUS);
-
- stmp3xxx_dma_init();
-}
diff --git a/arch/arm/plat-stmp3xxx/devices.c b/arch/arm/plat-stmp3xxx/devices.c
deleted file mode 100644
index 68fed4b..0000000
--- a/arch/arm/plat-stmp3xxx/devices.c
+++ /dev/null
@@ -1,389 +0,0 @@
-/*
-* Freescale STMP37XX/STMP378X platform devices
-*
-* Embedded Alley Solutions, Inc <source@embeddedalley.com>
-*
-* Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
-* Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
-*/
-
-/*
-* The code contained herein is licensed under the GNU General Public
-* License. You may obtain a copy of the GNU General Public License
-* Version 2 or later at the following locations:
-*
-* http://www.opensource.org/licenses/gpl-license.html
-* http://www.gnu.org/copyleft/gpl.html
-*/
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/device.h>
-#include <linux/platform_device.h>
-#include <linux/dma-mapping.h>
-
-#include <mach/dma.h>
-#include <mach/platform.h>
-#include <mach/stmp3xxx.h>
-#include <mach/regs-lcdif.h>
-#include <mach/regs-uartapp.h>
-#include <mach/regs-gpmi.h>
-#include <mach/regs-usbctrl.h>
-#include <mach/regs-ssp.h>
-#include <mach/regs-rtc.h>
-
-static u64 common_dmamask = DMA_BIT_MASK(32);
-
-static struct resource appuart_resources[] = {
- {
- .start = IRQ_UARTAPP_INTERNAL,
- .end = IRQ_UARTAPP_INTERNAL,
- .flags = IORESOURCE_IRQ,
- }, {
- .start = IRQ_UARTAPP_RX_DMA,
- .end = IRQ_UARTAPP_RX_DMA,
- .flags = IORESOURCE_IRQ,
- }, {
- .start = IRQ_UARTAPP_TX_DMA,
- .end = IRQ_UARTAPP_TX_DMA,
- .flags = IORESOURCE_IRQ,
- }, {
- .start = REGS_UARTAPP1_PHYS,
- .end = REGS_UARTAPP1_PHYS + REGS_UARTAPP_SIZE,
- .flags = IORESOURCE_MEM,
- }, {
- /* Rx DMA channel */
- .start = STMP3XXX_DMA(6, STMP3XXX_BUS_APBX),
- .end = STMP3XXX_DMA(6, STMP3XXX_BUS_APBX),
- .flags = IORESOURCE_DMA,
- }, {
- /* Tx DMA channel */
- .start = STMP3XXX_DMA(7, STMP3XXX_BUS_APBX),
- .end = STMP3XXX_DMA(7, STMP3XXX_BUS_APBX),
- .flags = IORESOURCE_DMA,
- },
-};
-
-struct platform_device stmp3xxx_appuart = {
- .name = "stmp3xxx-appuart",
- .id = 0,
- .resource = appuart_resources,
- .num_resources = ARRAY_SIZE(appuart_resources),
- .dev = {
- .dma_mask = &common_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
-};
-
-struct platform_device stmp3xxx_watchdog = {
- .name = "stmp3xxx_wdt",
- .id = -1,
-};
-
-static struct resource ts_resource[] = {
- {
- .flags = IORESOURCE_IRQ,
- .start = IRQ_TOUCH_DETECT,
- .end = IRQ_TOUCH_DETECT,
- }, {
- .flags = IORESOURCE_IRQ,
- .start = IRQ_LRADC_CH5,
- .end = IRQ_LRADC_CH5,
- },
-};
-
-struct platform_device stmp3xxx_touchscreen = {
- .name = "stmp3xxx_ts",
- .id = -1,
- .resource = ts_resource,
- .num_resources = ARRAY_SIZE(ts_resource),
-};
-
-/*
-* Keypad device
-*/
-struct platform_device stmp3xxx_keyboard = {
- .name = "stmp3xxx-keyboard",
- .id = -1,
-};
-
-static struct resource gpmi_resources[] = {
- {
- .flags = IORESOURCE_MEM,
- .start = REGS_GPMI_PHYS,
- .end = REGS_GPMI_PHYS + REGS_GPMI_SIZE,
- }, {
- .flags = IORESOURCE_IRQ,
- .start = IRQ_GPMI_DMA,
- .end = IRQ_GPMI_DMA,
- }, {
- .flags = IORESOURCE_DMA,
- .start = STMP3XXX_DMA(4, STMP3XXX_BUS_APBH),
- .end = STMP3XXX_DMA(8, STMP3XXX_BUS_APBH),
- },
-};
-
-struct platform_device stmp3xxx_gpmi = {
- .name = "gpmi",
- .id = -1,
- .dev = {
- .dma_mask = &common_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- .resource = gpmi_resources,
- .num_resources = ARRAY_SIZE(gpmi_resources),
-};
-
-static struct resource mmc1_resource[] = {
- {
- .flags = IORESOURCE_MEM,
- .start = REGS_SSP1_PHYS,
- .end = REGS_SSP1_PHYS + REGS_SSP_SIZE,
- }, {
- .flags = IORESOURCE_DMA,
- .start = STMP3XXX_DMA(1, STMP3XXX_BUS_APBH),
- .end = STMP3XXX_DMA(1, STMP3XXX_BUS_APBH),
- }, {
- .flags = IORESOURCE_IRQ,
- .start = IRQ_SSP1_DMA,
- .end = IRQ_SSP1_DMA,
- }, {
- .flags = IORESOURCE_IRQ,
- .start = IRQ_SSP_ERROR,
- .end = IRQ_SSP_ERROR,
- },
-};
-
-struct platform_device stmp3xxx_mmc = {
- .name = "stmp3xxx-mmc",
- .id = 1,
- .dev = {
- .dma_mask = &common_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- .resource = mmc1_resource,
- .num_resources = ARRAY_SIZE(mmc1_resource),
-};
-
-static struct resource usb_resources[] = {
- {
- .start = REGS_USBCTRL_PHYS,
- .end = REGS_USBCTRL_PHYS + SZ_4K,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_USB_CTRL,
- .end = IRQ_USB_CTRL,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-struct platform_device stmp3xxx_udc = {
- .name = "fsl-usb2-udc",
- .id = -1,
- .dev = {
- .dma_mask = &common_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- .resource = usb_resources,
- .num_resources = ARRAY_SIZE(usb_resources),
-};
-
-struct platform_device stmp3xxx_ehci = {
- .name = "fsl-ehci",
- .id = -1,
- .dev = {
- .dma_mask = &common_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- .resource = usb_resources,
- .num_resources = ARRAY_SIZE(usb_resources),
-};
-
-static struct resource rtc_resources[] = {
- {
- .start = REGS_RTC_PHYS,
- .end = REGS_RTC_PHYS + REGS_RTC_SIZE,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_RTC_ALARM,
- .end = IRQ_RTC_ALARM,
- .flags = IORESOURCE_IRQ,
- }, {
- .start = IRQ_RTC_1MSEC,
- .end = IRQ_RTC_1MSEC,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-struct platform_device stmp3xxx_rtc = {
- .name = "stmp3xxx-rtc",
- .id = -1,
- .resource = rtc_resources,
- .num_resources = ARRAY_SIZE(rtc_resources),
-};
-
-static struct resource ssp1_resources[] = {
- {
- .start = REGS_SSP1_PHYS,
- .end = REGS_SSP1_PHYS + REGS_SSP_SIZE,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_SSP1_DMA,
- .end = IRQ_SSP1_DMA,
- .flags = IORESOURCE_IRQ,
- }, {
- .start = STMP3XXX_DMA(1, STMP3XXX_BUS_APBH),
- .end = STMP3XXX_DMA(1, STMP3XXX_BUS_APBH),
- .flags = IORESOURCE_DMA,
- },
-};
-
-static struct resource ssp2_resources[] = {
- {
- .start = REGS_SSP2_PHYS,
- .end = REGS_SSP2_PHYS + REGS_SSP_SIZE,
- .flags = IORESOURCE_MEM,
- }, {
- .start = IRQ_SSP2_DMA,
- .end = IRQ_SSP2_DMA,
- .flags = IORESOURCE_IRQ,
- }, {
- .start = STMP3XXX_DMA(2, STMP3XXX_BUS_APBH),
- .end = STMP3XXX_DMA(2, STMP3XXX_BUS_APBH),
- .flags = IORESOURCE_DMA,
- },
-};
-
-struct platform_device stmp3xxx_spi1 = {
- .name = "stmp3xxx_ssp",
- .id = 1,
- .dev = {
- .dma_mask = &common_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- .resource = ssp1_resources,
- .num_resources = ARRAY_SIZE(ssp1_resources),
-};
-
-struct platform_device stmp3xxx_spi2 = {
- .name = "stmp3xxx_ssp",
- .id = 2,
- .dev = {
- .dma_mask = &common_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- .resource = ssp2_resources,
- .num_resources = ARRAY_SIZE(ssp2_resources),
-};
-
-static struct resource fb_resource[] = {
- {
- .flags = IORESOURCE_IRQ,
- .start = IRQ_LCDIF_DMA,
- .end = IRQ_LCDIF_DMA,
- }, {
- .flags = IORESOURCE_IRQ,
- .start = IRQ_LCDIF_ERROR,
- .end = IRQ_LCDIF_ERROR,
- }, {
- .flags = IORESOURCE_MEM,
- .start = REGS_LCDIF_PHYS,
- .end = REGS_LCDIF_PHYS + REGS_LCDIF_SIZE,
- },
-};
-
-struct platform_device stmp3xxx_framebuffer = {
- .name = "stmp3xxx-fb",
- .id = -1,
- .dev = {
- .dma_mask = &common_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
- .num_resources = ARRAY_SIZE(fb_resource),
- .resource = fb_resource,
-};
-
-#define CMDLINE_DEVICE_CHOOSE(name, dev1, dev2) \
- static char *cmdline_device_##name; \
- static int cmdline_device_##name##_setup(char *dev) \
- { \
- cmdline_device_##name = dev + 1; \
- return 0; \
- } \
- __setup(#name, cmdline_device_##name##_setup); \
- int stmp3xxx_##name##_device_register(void) \
- { \
- struct platform_device *d = NULL; \
- if (!cmdline_device_##name || \
- !strcmp(cmdline_device_##name, #dev1)) \
- d = &stmp3xxx_##dev1; \
- else if (!strcmp(cmdline_device_##name, #dev2)) \
- d = &stmp3xxx_##dev2; \
- else \
- printk(KERN_ERR"Unknown %s assignment '%s'.\n", \
- #name, cmdline_device_##name); \
- return d ? platform_device_register(d) : -ENOENT; \
- }
-
-CMDLINE_DEVICE_CHOOSE(ssp1, mmc, spi1)
-CMDLINE_DEVICE_CHOOSE(ssp2, gpmi, spi2)
-
-struct platform_device stmp3xxx_backlight = {
- .name = "stmp3xxx-bl",
- .id = -1,
-};
-
-struct platform_device stmp3xxx_rotdec = {
- .name = "stmp3xxx-rotdec",
- .id = -1,
-};
-
-struct platform_device stmp3xxx_persistent = {
- .name = "stmp3xxx-persistent",
- .id = -1,
-};
-
-struct platform_device stmp3xxx_dcp_bootstream = {
- .name = "stmp3xxx-dcpboot",
- .id = -1,
- .dev = {
- .dma_mask = &common_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
-};
-
-static struct resource dcp_resources[] = {
- {
- .start = IRQ_DCP_VMI,
- .end = IRQ_DCP_VMI,
- .flags = IORESOURCE_IRQ,
- }, {
- .start = IRQ_DCP,
- .end = IRQ_DCP,
- .flags = IORESOURCE_IRQ,
- },
-};
-
-struct platform_device stmp3xxx_dcp = {
- .name = "stmp3xxx-dcp",
- .id = -1,
- .resource = dcp_resources,
- .num_resources = ARRAY_SIZE(dcp_resources),
- .dev = {
- .dma_mask = &common_dmamask,
- .coherent_dma_mask = DMA_BIT_MASK(32),
- },
-};
-
-static struct resource battery_resource[] = {
- {
- .flags = IORESOURCE_IRQ,
- .start = IRQ_VDD5V,
- .end = IRQ_VDD5V,
- },
-};
-
-struct platform_device stmp3xxx_battery = {
- .name = "stmp3xxx-battery",
- .resource = battery_resource,
- .num_resources = ARRAY_SIZE(battery_resource),
-};
diff --git a/arch/arm/plat-stmp3xxx/dma.c b/arch/arm/plat-stmp3xxx/dma.c
deleted file mode 100644
index b4dcf8c..0000000
--- a/arch/arm/plat-stmp3xxx/dma.c
+++ /dev/null
@@ -1,464 +0,0 @@
-/*
- * DMA helper routines for Freescale STMP37XX/STMP378X
- *
- * Author: dmitry pervushin <dpervushin@embeddedalley.com>
- *
- * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#include <linux/gfp.h>
-#include <linux/kernel.h>
-#include <linux/device.h>
-#include <linux/dmapool.h>
-#include <linux/sysdev.h>
-#include <linux/cpufreq.h>
-
-#include <asm/page.h>
-
-#include <mach/platform.h>
-#include <mach/dma.h>
-#include <mach/regs-apbx.h>
-#include <mach/regs-apbh.h>
-
-static const size_t pool_item_size = sizeof(struct stmp3xxx_dma_command);
-static const size_t pool_alignment = 8;
-static struct stmp3xxx_dma_user {
- void *pool;
- int inuse;
- const char *name;
-} channels[MAX_DMA_CHANNELS];
-
-#define IS_VALID_CHANNEL(ch) ((ch) >= 0 && (ch) < MAX_DMA_CHANNELS)
-#define IS_USED(ch) (channels[ch].inuse)
-
-int stmp3xxx_dma_request(int ch, struct device *dev, const char *name)
-{
- struct stmp3xxx_dma_user *user;
- int err = 0;
-
- user = channels + ch;
- if (!IS_VALID_CHANNEL(ch)) {
- err = -ENODEV;
- goto out;
- }
- if (IS_USED(ch)) {
- err = -EBUSY;
- goto out;
- }
- /* Create a pool to allocate dma commands from */
- user->pool = dma_pool_create(name, dev, pool_item_size,
- pool_alignment, PAGE_SIZE);
- if (user->pool == NULL) {
- err = -ENOMEM;
- goto out;
- }
- user->name = name;
- user->inuse++;
-out:
- return err;
-}
-EXPORT_SYMBOL(stmp3xxx_dma_request);
-
-int stmp3xxx_dma_release(int ch)
-{
- struct stmp3xxx_dma_user *user = channels + ch;
- int err = 0;
-
- if (!IS_VALID_CHANNEL(ch)) {
- err = -ENODEV;
- goto out;
- }
- if (!IS_USED(ch)) {
- err = -EBUSY;
- goto out;
- }
- BUG_ON(user->pool == NULL);
- dma_pool_destroy(user->pool);
- user->inuse--;
-out:
- return err;
-}
-EXPORT_SYMBOL(stmp3xxx_dma_release);
-
-int stmp3xxx_dma_read_semaphore(int channel)
-{
- int sem = -1;
-
- switch (STMP3XXX_DMA_BUS(channel)) {
- case STMP3XXX_BUS_APBH:
- sem = __raw_readl(REGS_APBH_BASE + HW_APBH_CHn_SEMA +
- STMP3XXX_DMA_CHANNEL(channel) * 0x70);
- sem &= BM_APBH_CHn_SEMA_PHORE;
- sem >>= BP_APBH_CHn_SEMA_PHORE;
- break;
-
- case STMP3XXX_BUS_APBX:
- sem = __raw_readl(REGS_APBX_BASE + HW_APBX_CHn_SEMA +
- STMP3XXX_DMA_CHANNEL(channel) * 0x70);
- sem &= BM_APBX_CHn_SEMA_PHORE;
- sem >>= BP_APBX_CHn_SEMA_PHORE;
- break;
- default:
- BUG();
- }
- return sem;
-}
-EXPORT_SYMBOL(stmp3xxx_dma_read_semaphore);
-
-int stmp3xxx_dma_allocate_command(int channel,
- struct stmp3xxx_dma_descriptor *descriptor)
-{
- struct stmp3xxx_dma_user *user = channels + channel;
- int err = 0;
-
- if (!IS_VALID_CHANNEL(channel)) {
- err = -ENODEV;
- goto out;
- }
- if (!IS_USED(channel)) {
- err = -EBUSY;
- goto out;
- }
- if (descriptor == NULL) {
- err = -EINVAL;
- goto out;
- }
-
- /* Allocate memory for a command from the buffer */
- descriptor->command =
- dma_pool_alloc(user->pool, GFP_KERNEL, &descriptor->handle);
-
- /* Check it worked */
- if (!descriptor->command) {
- err = -ENOMEM;
- goto out;
- }
-
- memset(descriptor->command, 0, pool_item_size);
-out:
- WARN_ON(err);
- return err;
-}
-EXPORT_SYMBOL(stmp3xxx_dma_allocate_command);
-
-int stmp3xxx_dma_free_command(int channel,
- struct stmp3xxx_dma_descriptor *descriptor)
-{
- int err = 0;
-
- if (!IS_VALID_CHANNEL(channel)) {
- err = -ENODEV;
- goto out;
- }
- if (!IS_USED(channel)) {
- err = -EBUSY;
- goto out;
- }
-
- /* Return the command memory to the pool */
- dma_pool_free(channels[channel].pool, descriptor->command,
- descriptor->handle);
-
- /* Initialise descriptor so we're not tempted to use it */
- descriptor->command = NULL;
- descriptor->handle = 0;
- descriptor->virtual_buf_ptr = NULL;
- descriptor->next_descr = NULL;
-
- WARN_ON(err);
-out:
- return err;
-}
-EXPORT_SYMBOL(stmp3xxx_dma_free_command);
-
-void stmp3xxx_dma_go(int channel,
- struct stmp3xxx_dma_descriptor *head, u32 semaphore)
-{
- int ch = STMP3XXX_DMA_CHANNEL(channel);
- void __iomem *c, *s;
-
- switch (STMP3XXX_DMA_BUS(channel)) {
- case STMP3XXX_BUS_APBH:
- c = REGS_APBH_BASE + HW_APBH_CHn_NXTCMDAR + 0x70 * ch;
- s = REGS_APBH_BASE + HW_APBH_CHn_SEMA + 0x70 * ch;
- break;
-
- case STMP3XXX_BUS_APBX:
- c = REGS_APBX_BASE + HW_APBX_CHn_NXTCMDAR + 0x70 * ch;
- s = REGS_APBX_BASE + HW_APBX_CHn_SEMA + 0x70 * ch;
- break;
-
- default:
- return;
- }
-
- /* Set next command */
- __raw_writel(head->handle, c);
- /* Set counting semaphore (kicks off transfer). Assumes
- peripheral has been set up correctly */
- __raw_writel(semaphore, s);
-}
-EXPORT_SYMBOL(stmp3xxx_dma_go);
-
-int stmp3xxx_dma_running(int channel)
-{
- switch (STMP3XXX_DMA_BUS(channel)) {
- case STMP3XXX_BUS_APBH:
- return (__raw_readl(REGS_APBH_BASE + HW_APBH_CHn_SEMA +
- 0x70 * STMP3XXX_DMA_CHANNEL(channel))) &
- BM_APBH_CHn_SEMA_PHORE;
-
- case STMP3XXX_BUS_APBX:
- return (__raw_readl(REGS_APBX_BASE + HW_APBX_CHn_SEMA +
- 0x70 * STMP3XXX_DMA_CHANNEL(channel))) &
- BM_APBX_CHn_SEMA_PHORE;
- default:
- BUG();
- return 0;
- }
-}
-EXPORT_SYMBOL(stmp3xxx_dma_running);
-
-/*
- * Circular dma chain management
- */
-void stmp3xxx_dma_free_chain(struct stmp37xx_circ_dma_chain *chain)
-{
- int i;
-
- for (i = 0; i < chain->total_count; i++)
- stmp3xxx_dma_free_command(
- STMP3XXX_DMA(chain->channel, chain->bus),
- &chain->chain[i]);
-}
-EXPORT_SYMBOL(stmp3xxx_dma_free_chain);
-
-int stmp3xxx_dma_make_chain(int ch, struct stmp37xx_circ_dma_chain *chain,
- struct stmp3xxx_dma_descriptor descriptors[],
- unsigned items)
-{
- int i;
- int err = 0;
-
- if (items == 0)
- return err;
-
- for (i = 0; i < items; i++) {
- err = stmp3xxx_dma_allocate_command(ch, &descriptors[i]);
- if (err) {
- WARN_ON(err);
- /*
- * Couldn't allocate the whole chain.
- * deallocate what has been allocated
- */
- if (i) {
- do {
- stmp3xxx_dma_free_command(ch,
- &descriptors
- [i]);
- } while (i-- > 0);
- }
- return err;
- }
-
- /* link them! */
- if (i > 0) {
- descriptors[i - 1].next_descr = &descriptors[i];
- descriptors[i - 1].command->next =
- descriptors[i].handle;
- }
- }
-
- /* make list circular */
- descriptors[items - 1].next_descr = &descriptors[0];
- descriptors[items - 1].command->next = descriptors[0].handle;
-
- chain->total_count = items;
- chain->chain = descriptors;
- chain->free_index = 0;
- chain->active_index = 0;
- chain->cooked_index = 0;
- chain->free_count = items;
- chain->active_count = 0;
- chain->cooked_count = 0;
- chain->bus = STMP3XXX_DMA_BUS(ch);
- chain->channel = STMP3XXX_DMA_CHANNEL(ch);
- return err;
-}
-EXPORT_SYMBOL(stmp3xxx_dma_make_chain);
-
-void stmp37xx_circ_clear_chain(struct stmp37xx_circ_dma_chain *chain)
-{
- BUG_ON(stmp3xxx_dma_running(STMP3XXX_DMA(chain->channel, chain->bus)));
- chain->free_index = 0;
- chain->active_index = 0;
- chain->cooked_index = 0;
- chain->free_count = chain->total_count;
- chain->active_count = 0;
- chain->cooked_count = 0;
-}
-EXPORT_SYMBOL(stmp37xx_circ_clear_chain);
-
-void stmp37xx_circ_advance_free(struct stmp37xx_circ_dma_chain *chain,
- unsigned count)
-{
- BUG_ON(chain->cooked_count < count);
-
- chain->cooked_count -= count;
- chain->cooked_index += count;
- chain->cooked_index %= chain->total_count;
- chain->free_count += count;
-}
-EXPORT_SYMBOL(stmp37xx_circ_advance_free);
-
-void stmp37xx_circ_advance_active(struct stmp37xx_circ_dma_chain *chain,
- unsigned count)
-{
- void __iomem *c;
- u32 mask_clr, mask;
- BUG_ON(chain->free_count < count);
-
- chain->free_count -= count;
- chain->free_index += count;
- chain->free_index %= chain->total_count;
- chain->active_count += count;
-
- switch (chain->bus) {
- case STMP3XXX_BUS_APBH:
- c = REGS_APBH_BASE + HW_APBH_CHn_SEMA + 0x70 * chain->channel;
- mask_clr = BM_APBH_CHn_SEMA_INCREMENT_SEMA;
- mask = BF(count, APBH_CHn_SEMA_INCREMENT_SEMA);
- break;
- case STMP3XXX_BUS_APBX:
- c = REGS_APBX_BASE + HW_APBX_CHn_SEMA + 0x70 * chain->channel;
- mask_clr = BM_APBX_CHn_SEMA_INCREMENT_SEMA;
- mask = BF(count, APBX_CHn_SEMA_INCREMENT_SEMA);
- break;
- default:
- BUG();
- return;
- }
-
- /* Set counting semaphore (kicks off transfer). Assumes
- peripheral has been set up correctly */
- stmp3xxx_clearl(mask_clr, c);
- stmp3xxx_setl(mask, c);
-}
-EXPORT_SYMBOL(stmp37xx_circ_advance_active);
-
-unsigned stmp37xx_circ_advance_cooked(struct stmp37xx_circ_dma_chain *chain)
-{
- unsigned cooked;
-
- cooked = chain->active_count -
- stmp3xxx_dma_read_semaphore(STMP3XXX_DMA(chain->channel, chain->bus));
-
- chain->active_count -= cooked;
- chain->active_index += cooked;
- chain->active_index %= chain->total_count;
-
- chain->cooked_count += cooked;
-
- return cooked;
-}
-EXPORT_SYMBOL(stmp37xx_circ_advance_cooked);
-
-void stmp3xxx_dma_set_alt_target(int channel, int function)
-{
-#if defined(CONFIG_ARCH_STMP37XX)
- unsigned bits = 4;
-#elif defined(CONFIG_ARCH_STMP378X)
- unsigned bits = 2;
-#else
-#error wrong arch
-#endif
- int shift = STMP3XXX_DMA_CHANNEL(channel) * bits;
- unsigned mask = (1<<bits) - 1;
- void __iomem *c;
-
- BUG_ON(function < 0 || function >= (1<<bits));
- pr_debug("%s: channel = %d, using mask %x, "
- "shift = %d\n", __func__, channel, mask, shift);
-
- switch (STMP3XXX_DMA_BUS(channel)) {
- case STMP3XXX_BUS_APBH:
- c = REGS_APBH_BASE + HW_APBH_DEVSEL;
- break;
- case STMP3XXX_BUS_APBX:
- c = REGS_APBX_BASE + HW_APBX_DEVSEL;
- break;
- default:
- BUG();
- }
- stmp3xxx_clearl(mask << shift, c);
- stmp3xxx_setl(mask << shift, c);
-}
-EXPORT_SYMBOL(stmp3xxx_dma_set_alt_target);
-
-void stmp3xxx_dma_suspend(void)
-{
- stmp3xxx_setl(BM_APBH_CTRL0_CLKGATE, REGS_APBH_BASE + HW_APBH_CTRL0);
- stmp3xxx_setl(BM_APBX_CTRL0_CLKGATE, REGS_APBX_BASE + HW_APBX_CTRL0);
-}
-
-void stmp3xxx_dma_resume(void)
-{
- stmp3xxx_clearl(BM_APBH_CTRL0_CLKGATE | BM_APBH_CTRL0_SFTRST,
- REGS_APBH_BASE + HW_APBH_CTRL0);
- stmp3xxx_clearl(BM_APBX_CTRL0_CLKGATE | BM_APBX_CTRL0_SFTRST,
- REGS_APBX_BASE + HW_APBX_CTRL0);
-}
-
-#ifdef CONFIG_CPU_FREQ
-
-struct dma_notifier_block {
- struct notifier_block nb;
- void *data;
-};
-
-static int dma_cpufreq_notifier(struct notifier_block *self,
- unsigned long phase, void *p)
-{
- switch (phase) {
- case CPUFREQ_POSTCHANGE:
- stmp3xxx_dma_resume();
- break;
-
- case CPUFREQ_PRECHANGE:
- stmp3xxx_dma_suspend();
- break;
-
- default:
- break;
- }
-
- return NOTIFY_DONE;
-}
-
-static struct dma_notifier_block dma_cpufreq_nb = {
- .nb = {
- .notifier_call = dma_cpufreq_notifier,
- },
-};
-#endif /* CONFIG_CPU_FREQ */
-
-void __init stmp3xxx_dma_init(void)
-{
- stmp3xxx_clearl(BM_APBH_CTRL0_CLKGATE | BM_APBH_CTRL0_SFTRST,
- REGS_APBH_BASE + HW_APBH_CTRL0);
- stmp3xxx_clearl(BM_APBX_CTRL0_CLKGATE | BM_APBX_CTRL0_SFTRST,
- REGS_APBX_BASE + HW_APBX_CTRL0);
-#ifdef CONFIG_CPU_FREQ
- cpufreq_register_notifier(&dma_cpufreq_nb.nb,
- CPUFREQ_TRANSITION_NOTIFIER);
-#endif /* CONFIG_CPU_FREQ */
-}
diff --git a/arch/arm/plat-stmp3xxx/include/mach/clkdev.h b/arch/arm/plat-stmp3xxx/include/mach/clkdev.h
deleted file mode 100644
index f9c3977..0000000
--- a/arch/arm/plat-stmp3xxx/include/mach/clkdev.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#ifndef __ASM_MACH_CLKDEV_H
-#define __ASM_MACH_CLKDEV_H
-
-#define __clk_get(clk) ({ 1; })
-#define __clk_put(clk) do { } while (0)
-
-#endif
diff --git a/arch/arm/plat-stmp3xxx/include/mach/cputype.h b/arch/arm/plat-stmp3xxx/include/mach/cputype.h
deleted file mode 100644
index b4e205b..0000000
--- a/arch/arm/plat-stmp3xxx/include/mach/cputype.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Freescale STMP37XX/STMP378X CPU type detection
- *
- * Embedded Alley Solutions, Inc <source@embeddedalley.com>
- *
- * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#ifndef __ASM_PLAT_CPU_H
-#define __ASM_PLAT_CPU_H
-
-#ifdef CONFIG_ARCH_STMP37XX
-#define cpu_is_stmp37xx() (1)
-#else
-#define cpu_is_stmp37xx() (0)
-#endif
-
-#ifdef CONFIG_ARCH_STMP378X
-#define cpu_is_stmp378x() (1)
-#else
-#define cpu_is_stmp378x() (0)
-#endif
-
-#endif /* __ASM_PLAT_CPU_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/debug-macro.S b/arch/arm/plat-stmp3xxx/include/mach/debug-macro.S
deleted file mode 100644
index d3a0985..0000000
--- a/arch/arm/plat-stmp3xxx/include/mach/debug-macro.S
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * Debugging macro include header
- *
- * Embedded Alley Solutions, Inc <source@embeddedalley.com>
- *
- * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
- .macro addruart, rp, rv
- mov \rp, #0x00070000
- add \rv, \rp, #0xf0000000 @ virtual base
- add \rp, \rp, #0x80000000 @ physical base
- .endm
-
- .macro senduart,rd,rx
- strb \rd, [\rx, #0] @ data register at 0
- .endm
-
- .macro waituart,rd,rx
-1001: ldr \rd, [\rx, #0x18] @ UARTFLG
- tst \rd, #1 << 5 @ UARTFLGUTXFF - 1 when full
- bne 1001b
- .endm
-
- .macro busyuart,rd,rx
-1001: ldr \rd, [\rx, #0x18] @ UARTFLG
- tst \rd, #1 << 3 @ UARTFLGUBUSY - 1 when busy
- bne 1001b
- .endm
diff --git a/arch/arm/plat-stmp3xxx/include/mach/dma.h b/arch/arm/plat-stmp3xxx/include/mach/dma.h
deleted file mode 100644
index 7c58557..0000000
--- a/arch/arm/plat-stmp3xxx/include/mach/dma.h
+++ /dev/null
@@ -1,153 +0,0 @@
-/*
- * Freescale STMP37XX/STMP378X DMA helper interface
- *
- * Embedded Alley Solutions, Inc <source@embeddedalley.com>
- *
- * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#ifndef __ASM_PLAT_STMP3XXX_DMA_H
-#define __ASM_PLAT_STMP3XXX_DMA_H
-
-#include <linux/platform_device.h>
-#include <linux/dmapool.h>
-
-#if !defined(MAX_PIO_WORDS)
-#define MAX_PIO_WORDS (15)
-#endif
-
-#define STMP3XXX_BUS_APBH 0
-#define STMP3XXX_BUS_APBX 1
-#define STMP3XXX_DMA_MAX_CHANNEL 16
-#define STMP3XXX_DMA_BUS(dma) ((dma) / 16)
-#define STMP3XXX_DMA_CHANNEL(dma) ((dma) % 16)
-#define STMP3XXX_DMA(channel, bus) ((bus) * 16 + (channel))
-#define MAX_DMA_ADDRESS 0xffffffff
-#define MAX_DMA_CHANNELS 32
-
-struct stmp3xxx_dma_command {
- u32 next;
- u32 cmd;
- union {
- u32 buf_ptr;
- u32 alternate;
- };
- u32 pio_words[MAX_PIO_WORDS];
-};
-
-struct stmp3xxx_dma_descriptor {
- struct stmp3xxx_dma_command *command;
- dma_addr_t handle;
-
- /* The virtual address of the buffer pointer */
- void *virtual_buf_ptr;
- /* The next descriptor in a the DMA chain (optional) */
- struct stmp3xxx_dma_descriptor *next_descr;
-};
-
-struct stmp37xx_circ_dma_chain {
- unsigned total_count;
- struct stmp3xxx_dma_descriptor *chain;
-
- unsigned free_index;
- unsigned free_count;
- unsigned active_index;
- unsigned active_count;
- unsigned cooked_index;
- unsigned cooked_count;
-
- int bus;
- unsigned channel;
-};
-
-static inline struct stmp3xxx_dma_descriptor
- *stmp3xxx_dma_circ_get_free_head(struct stmp37xx_circ_dma_chain *chain)
-{
- return &(chain->chain[chain->free_index]);
-}
-
-static inline struct stmp3xxx_dma_descriptor
- *stmp3xxx_dma_circ_get_cooked_head(struct stmp37xx_circ_dma_chain *chain)
-{
- return &(chain->chain[chain->cooked_index]);
-}
-
-int stmp3xxx_dma_request(int ch, struct device *dev, const char *name);
-int stmp3xxx_dma_release(int ch);
-int stmp3xxx_dma_allocate_command(int ch,
- struct stmp3xxx_dma_descriptor *descriptor);
-int stmp3xxx_dma_free_command(int ch,
- struct stmp3xxx_dma_descriptor *descriptor);
-void stmp3xxx_dma_continue(int channel, u32 semaphore);
-void stmp3xxx_dma_go(int ch, struct stmp3xxx_dma_descriptor *head,
- u32 semaphore);
-int stmp3xxx_dma_running(int ch);
-int stmp3xxx_dma_make_chain(int ch, struct stmp37xx_circ_dma_chain *chain,
- struct stmp3xxx_dma_descriptor descriptors[],
- unsigned items);
-void stmp3xxx_dma_free_chain(struct stmp37xx_circ_dma_chain *chain);
-void stmp37xx_circ_clear_chain(struct stmp37xx_circ_dma_chain *chain);
-void stmp37xx_circ_advance_free(struct stmp37xx_circ_dma_chain *chain,
- unsigned count);
-void stmp37xx_circ_advance_active(struct stmp37xx_circ_dma_chain *chain,
- unsigned count);
-unsigned stmp37xx_circ_advance_cooked(struct stmp37xx_circ_dma_chain *chain);
-int stmp3xxx_dma_read_semaphore(int ch);
-void stmp3xxx_dma_init(void);
-void stmp3xxx_dma_set_alt_target(int ch, int target);
-void stmp3xxx_dma_suspend(void);
-void stmp3xxx_dma_resume(void);
-
-/*
- * STMP37xx and STMP378x have different DMA control
- * registers layout
- */
-
-void stmp3xxx_arch_dma_freeze(int ch);
-void stmp3xxx_arch_dma_unfreeze(int ch);
-void stmp3xxx_arch_dma_reset_channel(int ch);
-void stmp3xxx_arch_dma_enable_interrupt(int ch);
-void stmp3xxx_arch_dma_clear_interrupt(int ch);
-int stmp3xxx_arch_dma_is_interrupt(int ch);
-
-static inline void stmp3xxx_dma_reset_channel(int ch)
-{
- stmp3xxx_arch_dma_reset_channel(ch);
-}
-
-
-static inline void stmp3xxx_dma_freeze(int ch)
-{
- stmp3xxx_arch_dma_freeze(ch);
-}
-
-static inline void stmp3xxx_dma_unfreeze(int ch)
-{
- stmp3xxx_arch_dma_unfreeze(ch);
-}
-
-static inline void stmp3xxx_dma_enable_interrupt(int ch)
-{
- stmp3xxx_arch_dma_enable_interrupt(ch);
-}
-
-static inline void stmp3xxx_dma_clear_interrupt(int ch)
-{
- stmp3xxx_arch_dma_clear_interrupt(ch);
-}
-
-static inline int stmp3xxx_dma_is_interrupt(int ch)
-{
- return stmp3xxx_arch_dma_is_interrupt(ch);
-}
-
-#endif /* __ASM_PLAT_STMP3XXX_DMA_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/gpio.h b/arch/arm/plat-stmp3xxx/include/mach/gpio.h
deleted file mode 100644
index a8b5792..0000000
--- a/arch/arm/plat-stmp3xxx/include/mach/gpio.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * Freescale STMP37XX/STMP378X GPIO interface
- *
- * Embedded Alley Solutions, Inc <source@embeddedalley.com>
- *
- * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#ifndef __ASM_PLAT_GPIO_H
-#define __ASM_PLAT_GPIO_H
-
-#define ARCH_NR_GPIOS (32 * 3)
-#define gpio_to_irq(gpio) __gpio_to_irq(gpio)
-#define gpio_get_value(gpio) __gpio_get_value(gpio)
-#define gpio_set_value(gpio, value) __gpio_set_value(gpio, value)
-
-#include <asm-generic/gpio.h>
-
-#endif /* __ASM_PLAT_GPIO_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/gpmi.h b/arch/arm/plat-stmp3xxx/include/mach/gpmi.h
deleted file mode 100644
index e166432..0000000
--- a/arch/arm/plat-stmp3xxx/include/mach/gpmi.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#ifndef __MACH_GPMI_H
-
-#include <linux/mtd/partitions.h>
-#include <mach/regs-gpmi.h>
-
-struct gpmi_platform_data {
- void *pins;
- int nr_parts;
- struct mtd_partition *parts;
- const char *part_types[];
-};
-#endif
diff --git a/arch/arm/plat-stmp3xxx/include/mach/hardware.h b/arch/arm/plat-stmp3xxx/include/mach/hardware.h
deleted file mode 100644
index 47b8978..0000000
--- a/arch/arm/plat-stmp3xxx/include/mach/hardware.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * This file contains the hardware definitions of the Freescale STMP3XXX
- *
- * Copyright (C) 2005 Sigmatel Inc
- *
- * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-/*
- * Where in virtual memory the IO devices (timers, system controllers
- * and so on)
- */
-#define IO_BASE 0xF0000000 /* VA of IO */
-#define IO_SIZE 0x00100000 /* How much? */
-#define IO_START 0x80000000 /* PA of IO */
-
-/* macro to get at IO space when running virtually */
-#define IO_ADDRESS(x) (((x) & 0x000fffff) | IO_BASE)
-
-#endif
diff --git a/arch/arm/plat-stmp3xxx/include/mach/io.h b/arch/arm/plat-stmp3xxx/include/mach/io.h
deleted file mode 100644
index d08b1b7..0000000
--- a/arch/arm/plat-stmp3xxx/include/mach/io.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Copyright (C) 2005 Sigmatel Inc
- *
- * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#ifndef __ASM_ARM_ARCH_IO_H
-#define __ASM_ARM_ARCH_IO_H
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-#define __io(a) __typesafe_io(a)
-#define __mem_pci(a) (a)
-#define __mem_isa(a) (a)
-
-#endif
diff --git a/arch/arm/plat-stmp3xxx/include/mach/memory.h b/arch/arm/plat-stmp3xxx/include/mach/memory.h
deleted file mode 100644
index 61fa548..0000000
--- a/arch/arm/plat-stmp3xxx/include/mach/memory.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#ifndef __ASM_ARCH_MEMORY_H
-#define __ASM_ARCH_MEMORY_H
-
-/*
- * Physical DRAM offset.
- */
-#define PLAT_PHYS_OFFSET UL(0x40000000)
-
-#endif
diff --git a/arch/arm/plat-stmp3xxx/include/mach/mmc.h b/arch/arm/plat-stmp3xxx/include/mach/mmc.h
deleted file mode 100644
index ba81e15..0000000
--- a/arch/arm/plat-stmp3xxx/include/mach/mmc.h
+++ /dev/null
@@ -1,14 +0,0 @@
-#ifndef _MACH_MMC_H
-#define _MACH_MMC_H
-
-#include <mach/regs-ssp.h>
-
-struct stmp3xxxmmc_platform_data {
- int (*get_wp)(void);
- unsigned long (*setclock)(void __iomem *base, unsigned long);
- void (*cmd_pullup)(int);
- int (*hw_init)(void);
- void (*hw_release)(void);
-};
-
-#endif
diff --git a/arch/arm/plat-stmp3xxx/include/mach/pinmux.h b/arch/arm/plat-stmp3xxx/include/mach/pinmux.h
deleted file mode 100644
index cc5af82..0000000
--- a/arch/arm/plat-stmp3xxx/include/mach/pinmux.h
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * Freescale STMP37XX/STMP378X Pin Multiplexing
- *
- * Author: Vladislav Buzov <vbuzov@embeddedalley.com>
- *
- * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#ifndef __PINMUX_H
-#define __PINMUX_H
-
-#include <linux/spinlock.h>
-#include <linux/types.h>
-#include <linux/gpio.h>
-#include <asm-generic/gpio.h>
-
-/* Pin definitions */
-#include "pins.h"
-#include <mach/pins.h>
-
-/*
- * Each pin may be routed up to four different HW interfaces
- * including GPIO
- */
-enum pin_fun {
- PIN_FUN1 = 0,
- PIN_FUN2,
- PIN_FUN3,
- PIN_GPIO,
-};
-
-/*
- * Each pin may have different output drive strength in range from
- * 4mA to 20mA. The most common case is 4, 8 and 12 mA strengths.
- */
-enum pin_strength {
- PIN_4MA = 0,
- PIN_8MA,
- PIN_12MA,
- PIN_16MA,
- PIN_20MA,
-};
-
-/*
- * Each pin can be programmed for 1.8V or 3.3V
- */
-enum pin_voltage {
- PIN_1_8V = 0,
- PIN_3_3V,
-};
-
-/*
- * Structure to define a group of pins and their parameters
- */
-struct pin_desc {
- unsigned id;
- enum pin_fun fun;
- enum pin_strength strength;
- enum pin_voltage voltage;
- unsigned pullup:1;
-};
-
-struct pin_group {
- struct pin_desc *pins;
- int nr_pins;
-};
-
-/* Set pin drive strength */
-void stmp3xxx_pin_strength(unsigned id, enum pin_strength strength,
- const char *label);
-
-/* Set pin voltage */
-void stmp3xxx_pin_voltage(unsigned id, enum pin_voltage voltage,
- const char *label);
-
-/* Enable pull-up resistor for a pin */
-void stmp3xxx_pin_pullup(unsigned id, int enable, const char *label);
-
-/*
- * Request a pin ownership, only one module (identified by @label)
- * may own a pin.
- */
-int stmp3xxx_request_pin(unsigned id, enum pin_fun fun, const char *label);
-
-/* Release pin */
-void stmp3xxx_release_pin(unsigned id, const char *label);
-
-void stmp3xxx_set_pin_type(unsigned id, enum pin_fun fun);
-
-/*
- * Each bank is associated with a number of registers to control
- * pin function, drive strength, voltage and pull-up reigster. The
- * number of registers of a given type depends on the number of bits
- * describin particular pin.
- */
-#define HW_MUXSEL_NUM 2 /* registers per bank */
-#define HW_MUXSEL_PIN_LEN 2 /* bits per pin */
-#define HW_MUXSEL_PIN_NUM 16 /* pins per register */
-#define HW_MUXSEL_PINFUN_MASK 0x3 /* pin function mask */
-#define HW_MUXSEL_PINFUN_NUM 4 /* four options for a pin */
-
-#define HW_DRIVE_NUM 4 /* registers per bank */
-#define HW_DRIVE_PIN_LEN 4 /* bits per pin */
-#define HW_DRIVE_PIN_NUM 8 /* pins per register */
-#define HW_DRIVE_PINDRV_MASK 0x3 /* pin strength mask - 2 bits */
-#define HW_DRIVE_PINDRV_NUM 5 /* five possible strength values */
-#define HW_DRIVE_PINV_MASK 0x4 /* pin voltage mask - 1 bit */
-
-
-struct stmp3xxx_pinmux_bank {
- struct gpio_chip chip;
-
- /* Pins allocation map */
- unsigned long pin_map;
-
- /* Pin owner names */
- const char *pin_labels[32];
-
- /* Bank registers */
- void __iomem *hw_muxsel[HW_MUXSEL_NUM];
- void __iomem *hw_drive[HW_DRIVE_NUM];
- void __iomem *hw_pull;
-
- void __iomem *pin2irq,
- *irqlevel,
- *irqpolarity,
- *irqen,
- *irqstat;
-
- /* HW MUXSEL register function bit values */
- u8 functions[HW_MUXSEL_PINFUN_NUM];
-
- /*
- * HW DRIVE register strength bit values:
- * 0xff - requested strength is not supported for this bank
- */
- u8 strengths[HW_DRIVE_PINDRV_NUM];
-
- /* GPIO things */
- void __iomem *hw_gpio_in,
- *hw_gpio_out,
- *hw_gpio_doe;
- int irq, virq;
-};
-
-int __init stmp3xxx_pinmux_init(int virtual_irq_start);
-
-#endif /* __PINMUX_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/pins.h b/arch/arm/plat-stmp3xxx/include/mach/pins.h
deleted file mode 100644
index c573318..0000000
--- a/arch/arm/plat-stmp3xxx/include/mach/pins.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * Freescale STMP37XX/STMP378X Pin multiplexing interface definitions
- *
- * Author: Vladislav Buzov <vbuzov@embeddedalley.com>
- *
- * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#ifndef __ASM_PLAT_PINS_H
-#define __ASM_PLAT_PINS_H
-
-#define STMP3XXX_PINID(bank, pin) (bank * 32 + pin)
-#define STMP3XXX_PINID_TO_BANK(pinid) (pinid / 32)
-#define STMP3XXX_PINID_TO_PINNUM(pinid) (pinid % 32)
-
-/*
- * Special invalid pin identificator to show a pin doesn't exist
- */
-#define PINID_NO_PIN STMP3XXX_PINID(0xFF, 0xFF)
-
-#endif /* __ASM_PLAT_PINS_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/platform.h b/arch/arm/plat-stmp3xxx/include/mach/platform.h
deleted file mode 100644
index 7007dda..0000000
--- a/arch/arm/plat-stmp3xxx/include/mach/platform.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#ifndef __ASM_PLAT_PLATFORM_H
-#define __ASM_PLAT_PLATFORM_H
-
-#ifndef __ASSEMBLER__
-#include <linux/io.h>
-#endif
-#include <asm/sizes.h>
-
-/* Virtual address where registers are mapped */
-#define STMP3XXX_REGS_PHBASE 0x80000000
-#ifdef __ASSEMBLER__
-#define STMP3XXX_REGS_BASE 0xF0000000
-#else
-#define STMP3XXX_REGS_BASE (void __iomem *)0xF0000000
-#endif
-#define STMP3XXX_REGS_SIZE SZ_1M
-
-/* Virtual address where OCRAM is mapped */
-#define STMP3XXX_OCRAM_PHBASE 0x00000000
-#ifdef __ASSEMBLER__
-#define STMP3XXX_OCRAM_BASE 0xf1000000
-#else
-#define STMP3XXX_OCRAM_BASE (void __iomem *)0xf1000000
-#endif
-#define STMP3XXX_OCRAM_SIZE (32 * SZ_1K)
-
-#ifdef CONFIG_ARCH_STMP37XX
-#define IRQ_PRIORITY_REG_RD HW_ICOLL_PRIORITYn_RD
-#define IRQ_PRIORITY_REG_WR HW_ICOLL_PRIORITYn_WR
-#endif
-
-#ifdef CONFIG_ARCH_STMP378X
-#define IRQ_PRIORITY_REG_RD HW_ICOLL_INTERRUPTn_RD
-#define IRQ_PRIORITY_REG_WR HW_ICOLL_INTERRUPTn_WR
-#endif
-
-#define HW_STMP3XXX_SET 0x04
-#define HW_STMP3XXX_CLR 0x08
-#define HW_STMP3XXX_TOG 0x0c
-
-#ifndef __ASSEMBLER__
-static inline void stmp3xxx_clearl(u32 v, void __iomem *r)
-{
- __raw_writel(v, r + HW_STMP3XXX_CLR);
-}
-
-static inline void stmp3xxx_setl(u32 v, void __iomem *r)
-{
- __raw_writel(v, r + HW_STMP3XXX_SET);
-}
-#endif
-
-#define BF(value, field) (((value) << BP_##field) & BM_##field)
-
-#endif /* __ASM_ARCH_PLATFORM_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/stmp3xxx.h b/arch/arm/plat-stmp3xxx/include/mach/stmp3xxx.h
deleted file mode 100644
index 2e300fe..0000000
--- a/arch/arm/plat-stmp3xxx/include/mach/stmp3xxx.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * Freescale STMP37XX/STMP378X core structure and function declarations
- *
- * Embedded Alley Solutions, Inc <source@embeddedalley.com>
- *
- * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#ifndef __ASM_PLAT_STMP3XXX_H
-#define __ASM_PLAT_STMP3XXX_H
-
-#include <linux/irq.h>
-
-extern struct sys_timer stmp3xxx_timer;
-
-void stmp3xxx_init_irq(struct irq_chip *chip);
-void stmp3xxx_init(void);
-int stmp3xxx_reset_block(void __iomem *hwreg, int just_enable);
-extern struct platform_device stmp3xxx_dbguart,
- stmp3xxx_appuart,
- stmp3xxx_watchdog,
- stmp3xxx_touchscreen,
- stmp3xxx_keyboard,
- stmp3xxx_gpmi,
- stmp3xxx_mmc,
- stmp3xxx_udc,
- stmp3xxx_ehci,
- stmp3xxx_rtc,
- stmp3xxx_spi1,
- stmp3xxx_spi2,
- stmp3xxx_backlight,
- stmp3xxx_rotdec,
- stmp3xxx_dcp,
- stmp3xxx_dcp_bootstream,
- stmp3xxx_persistent,
- stmp3xxx_framebuffer,
- stmp3xxx_battery;
-int stmp3xxx_ssp1_device_register(void);
-int stmp3xxx_ssp2_device_register(void);
-
-struct pin_group;
-void stmp3xxx_release_pin_group(struct pin_group *pin_group, const char *label);
-int stmp3xxx_request_pin_group(struct pin_group *pin_group, const char *label);
-
-#endif /* __ASM_PLAT_STMP3XXX_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/system.h b/arch/arm/plat-stmp3xxx/include/mach/system.h
deleted file mode 100644
index 28a9888..0000000
--- a/arch/arm/plat-stmp3xxx/include/mach/system.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * Copyright (C) 2005 Sigmatel Inc
- *
- * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#ifndef __ASM_ARCH_SYSTEM_H
-#define __ASM_ARCH_SYSTEM_H
-
-#include <asm/proc-fns.h>
-#include <mach/platform.h>
-#include <mach/regs-clkctrl.h>
-#include <mach/regs-power.h>
-
-static inline void arch_idle(void)
-{
- /*
- * This should do all the clock switching
- * and wait for interrupt tricks
- */
-
- cpu_do_idle();
-}
-
-static inline void arch_reset(char mode, const char *cmd)
-{
- /* Set BATTCHRG to default value */
- __raw_writel(0x00010000, REGS_POWER_BASE + HW_POWER_CHARGE);
-
- /* Set MINPWR to default value */
- __raw_writel(0, REGS_POWER_BASE + HW_POWER_MINPWR);
-
- /* Reset digital side of chip (but not power or RTC) */
- __raw_writel(BM_CLKCTRL_RESET_DIG,
- REGS_CLKCTRL_BASE + HW_CLKCTRL_RESET);
-
- /* Should not return */
-}
-
-#endif
diff --git a/arch/arm/plat-stmp3xxx/include/mach/timex.h b/arch/arm/plat-stmp3xxx/include/mach/timex.h
deleted file mode 100644
index 3373985..0000000
--- a/arch/arm/plat-stmp3xxx/include/mach/timex.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * Copyright (C) 1999 ARM Limited
- *
- * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-/*
- * System time clock is sourced from the 32k clock
- */
-#define CLOCK_TICK_RATE (32768)
diff --git a/arch/arm/plat-stmp3xxx/include/mach/uncompress.h b/arch/arm/plat-stmp3xxx/include/mach/uncompress.h
deleted file mode 100644
index f79f5ee..0000000
--- a/arch/arm/plat-stmp3xxx/include/mach/uncompress.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- *
- * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#ifndef __ASM_PLAT_UNCOMPRESS_H
-#define __ASM_PLAT_UNCOMPRESS_H
-
-/*
- * Register includes are for when the MMU enabled; we need to define our
- * own stuff here for pre-MMU use
- */
-#define UARTDBG_BASE 0x80070000
-#define UART(c) (((volatile unsigned *)UARTDBG_BASE)[c])
-
-/*
- * This does not append a newline
- */
-static void putc(char c)
-{
- /* Wait for TX fifo empty */
- while ((UART(6) & (1<<7)) == 0)
- continue;
-
- /* Write byte */
- UART(0) = c;
-
- /* Wait for last bit to exit the UART */
- while (UART(6) & (1<<3))
- continue;
-}
-
-static void flush(void)
-{
-}
-
-/*
- * nothing to do
- */
-#define arch_decomp_setup()
-
-#define arch_decomp_wdog()
-
-#endif /* __ASM_PLAT_UNCOMPRESS_H */
diff --git a/arch/arm/plat-stmp3xxx/include/mach/vmalloc.h b/arch/arm/plat-stmp3xxx/include/mach/vmalloc.h
deleted file mode 100644
index 943c1a2..0000000
--- a/arch/arm/plat-stmp3xxx/include/mach/vmalloc.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#define VMALLOC_END 0xf0000000UL
diff --git a/arch/arm/plat-stmp3xxx/irq.c b/arch/arm/plat-stmp3xxx/irq.c
deleted file mode 100644
index 6fdf9ac..0000000
--- a/arch/arm/plat-stmp3xxx/irq.c
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * Freescale STMP37XX/STMP378X common interrupt handling code
- *
- * Author: Vladislav Buzov <vbuzov@embeddedalley.com>
- *
- * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/delay.h>
-#include <linux/irq.h>
-#include <linux/sysdev.h>
-
-#include <mach/stmp3xxx.h>
-#include <mach/platform.h>
-#include <mach/regs-icoll.h>
-
-void __init stmp3xxx_init_irq(struct irq_chip *chip)
-{
- unsigned int i, lv;
-
- /* Reset the interrupt controller */
- stmp3xxx_reset_block(REGS_ICOLL_BASE + HW_ICOLL_CTRL, true);
-
- /* Disable all interrupts initially */
- for (i = 0; i < NR_REAL_IRQS; i++) {
- chip->irq_mask(irq_get_irq_data(i));
- irq_set_chip_and_handler(i, chip, handle_level_irq);
- set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
- }
-
- /* Ensure vector is cleared */
- for (lv = 0; lv < 4; lv++)
- __raw_writel(1 << lv, REGS_ICOLL_BASE + HW_ICOLL_LEVELACK);
- __raw_writel(0, REGS_ICOLL_BASE + HW_ICOLL_VECTOR);
-
- /* Barrier */
- (void)__raw_readl(REGS_ICOLL_BASE + HW_ICOLL_STAT);
-}
-
diff --git a/arch/arm/plat-stmp3xxx/pinmux.c b/arch/arm/plat-stmp3xxx/pinmux.c
deleted file mode 100644
index 3def03b..0000000
--- a/arch/arm/plat-stmp3xxx/pinmux.c
+++ /dev/null
@@ -1,550 +0,0 @@
-/*
- * Freescale STMP378X/STMP378X Pin Multiplexing
- *
- * Author: Vladislav Buzov <vbuzov@embeddedalley.com>
- *
- * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#define DEBUG
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/sysdev.h>
-#include <linux/string.h>
-#include <linux/bitops.h>
-#include <linux/irq.h>
-
-#include <mach/hardware.h>
-#include <mach/platform.h>
-#include <mach/regs-pinctrl.h>
-#include <mach/pins.h>
-#include <mach/pinmux.h>
-
-#define NR_BANKS ARRAY_SIZE(pinmux_banks)
-static struct stmp3xxx_pinmux_bank pinmux_banks[] = {
- [0] = {
- .hw_muxsel = {
- REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL0,
- REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL1,
- },
- .hw_drive = {
- REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE0,
- REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE1,
- REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE2,
- REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE3,
- },
- .hw_pull = REGS_PINCTRL_BASE + HW_PINCTRL_PULL0,
- .functions = { 0x0, 0x1, 0x2, 0x3 },
- .strengths = { 0x0, 0x1, 0x2, 0x3, 0xff },
-
- .hw_gpio_in = REGS_PINCTRL_BASE + HW_PINCTRL_DIN0,
- .hw_gpio_out = REGS_PINCTRL_BASE + HW_PINCTRL_DOUT0,
- .hw_gpio_doe = REGS_PINCTRL_BASE + HW_PINCTRL_DOE0,
- .irq = IRQ_GPIO0,
-
- .pin2irq = REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ0,
- .irqstat = REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT0,
- .irqlevel = REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL0,
- .irqpolarity = REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL0,
- .irqen = REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN0,
- },
- [1] = {
- .hw_muxsel = {
- REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL2,
- REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL3,
- },
- .hw_drive = {
- REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE4,
- REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE5,
- REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE6,
- REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE7,
- },
- .hw_pull = REGS_PINCTRL_BASE + HW_PINCTRL_PULL1,
- .functions = { 0x0, 0x1, 0x2, 0x3 },
- .strengths = { 0x0, 0x1, 0x2, 0x3, 0xff },
-
- .hw_gpio_in = REGS_PINCTRL_BASE + HW_PINCTRL_DIN1,
- .hw_gpio_out = REGS_PINCTRL_BASE + HW_PINCTRL_DOUT1,
- .hw_gpio_doe = REGS_PINCTRL_BASE + HW_PINCTRL_DOE1,
- .irq = IRQ_GPIO1,
-
- .pin2irq = REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ1,
- .irqstat = REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT1,
- .irqlevel = REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL1,
- .irqpolarity = REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL1,
- .irqen = REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN1,
- },
- [2] = {
- .hw_muxsel = {
- REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL4,
- REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL5,
- },
- .hw_drive = {
- REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE8,
- REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE9,
- REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE10,
- REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE11,
- },
- .hw_pull = REGS_PINCTRL_BASE + HW_PINCTRL_PULL2,
- .functions = { 0x0, 0x1, 0x2, 0x3 },
- .strengths = { 0x0, 0x1, 0x2, 0x1, 0x2 },
-
- .hw_gpio_in = REGS_PINCTRL_BASE + HW_PINCTRL_DIN2,
- .hw_gpio_out = REGS_PINCTRL_BASE + HW_PINCTRL_DOUT2,
- .hw_gpio_doe = REGS_PINCTRL_BASE + HW_PINCTRL_DOE2,
- .irq = IRQ_GPIO2,
-
- .pin2irq = REGS_PINCTRL_BASE + HW_PINCTRL_PIN2IRQ2,
- .irqstat = REGS_PINCTRL_BASE + HW_PINCTRL_IRQSTAT2,
- .irqlevel = REGS_PINCTRL_BASE + HW_PINCTRL_IRQLEVEL2,
- .irqpolarity = REGS_PINCTRL_BASE + HW_PINCTRL_IRQPOL2,
- .irqen = REGS_PINCTRL_BASE + HW_PINCTRL_IRQEN2,
- },
- [3] = {
- .hw_muxsel = {
- REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL6,
- REGS_PINCTRL_BASE + HW_PINCTRL_MUXSEL7,
- },
- .hw_drive = {
- REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE12,
- REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE13,
- REGS_PINCTRL_BASE + HW_PINCTRL_DRIVE14,
- NULL,
- },
- .hw_pull = REGS_PINCTRL_BASE + HW_PINCTRL_PULL3,
- .functions = {0x0, 0x1, 0x2, 0x3},
- .strengths = {0x0, 0x1, 0x2, 0x3, 0xff},
- },
-};
-
-static inline struct stmp3xxx_pinmux_bank *
-stmp3xxx_pinmux_bank(unsigned id, unsigned *bank, unsigned *pin)
-{
- unsigned b, p;
-
- b = STMP3XXX_PINID_TO_BANK(id);
- p = STMP3XXX_PINID_TO_PINNUM(id);
- BUG_ON(b >= NR_BANKS);
- if (bank)
- *bank = b;
- if (pin)
- *pin = p;
- return &pinmux_banks[b];
-}
-
-/* Check if requested pin is owned by caller */
-static int stmp3xxx_check_pin(unsigned id, const char *label)
-{
- unsigned pin;
- struct stmp3xxx_pinmux_bank *pm = stmp3xxx_pinmux_bank(id, NULL, &pin);
-
- if (!test_bit(pin, &pm->pin_map)) {
- printk(KERN_WARNING
- "%s: Accessing free pin %x, caller %s\n",
- __func__, id, label);
-
- return -EINVAL;
- }
-
- if (label && pm->pin_labels[pin] &&
- strcmp(label, pm->pin_labels[pin])) {
- printk(KERN_WARNING
- "%s: Wrong pin owner %x, caller %s owner %s\n",
- __func__, id, label, pm->pin_labels[pin]);
-
- return -EINVAL;
- }
- return 0;
-}
-
-void stmp3xxx_pin_strength(unsigned id, enum pin_strength strength,
- const char *label)
-{
- struct stmp3xxx_pinmux_bank *pbank;
- void __iomem *hwdrive;
- u32 shift, val;
- u32 bank, pin;
-
- pbank = stmp3xxx_pinmux_bank(id, &bank, &pin);
- pr_debug("%s: label %s bank %d pin %d strength %d\n", __func__, label,
- bank, pin, strength);
-
- hwdrive = pbank->hw_drive[pin / HW_DRIVE_PIN_NUM];
- shift = (pin % HW_DRIVE_PIN_NUM) * HW_DRIVE_PIN_LEN;
- val = pbank->strengths[strength];
- if (val == 0xff) {
- printk(KERN_WARNING
- "%s: strength is not supported for bank %d, caller %s",
- __func__, bank, label);
- return;
- }
-
- if (stmp3xxx_check_pin(id, label))
- return;
-
- pr_debug("%s: writing 0x%x to 0x%p register\n", __func__,
- val << shift, hwdrive);
- stmp3xxx_clearl(HW_DRIVE_PINDRV_MASK << shift, hwdrive);
- stmp3xxx_setl(val << shift, hwdrive);
-}
-
-void stmp3xxx_pin_voltage(unsigned id, enum pin_voltage voltage,
- const char *label)
-{
- struct stmp3xxx_pinmux_bank *pbank;
- void __iomem *hwdrive;
- u32 shift;
- u32 bank, pin;
-
- pbank = stmp3xxx_pinmux_bank(id, &bank, &pin);
- pr_debug("%s: label %s bank %d pin %d voltage %d\n", __func__, label,
- bank, pin, voltage);
-
- hwdrive = pbank->hw_drive[pin / HW_DRIVE_PIN_NUM];
- shift = (pin % HW_DRIVE_PIN_NUM) * HW_DRIVE_PIN_LEN;
-
- if (stmp3xxx_check_pin(id, label))
- return;
-
- pr_debug("%s: changing 0x%x bit in 0x%p register\n",
- __func__, HW_DRIVE_PINV_MASK << shift, hwdrive);
- if (voltage == PIN_1_8V)
- stmp3xxx_clearl(HW_DRIVE_PINV_MASK << shift, hwdrive);
- else
- stmp3xxx_setl(HW_DRIVE_PINV_MASK << shift, hwdrive);
-}
-
-void stmp3xxx_pin_pullup(unsigned id, int enable, const char *label)
-{
- struct stmp3xxx_pinmux_bank *pbank;
- void __iomem *hwpull;
- u32 bank, pin;
-
- pbank = stmp3xxx_pinmux_bank(id, &bank, &pin);
- pr_debug("%s: label %s bank %d pin %d enable %d\n", __func__, label,
- bank, pin, enable);
-
- hwpull = pbank->hw_pull;
-
- if (stmp3xxx_check_pin(id, label))
- return;
-
- pr_debug("%s: changing 0x%x bit in 0x%p register\n",
- __func__, 1 << pin, hwpull);
- if (enable)
- stmp3xxx_setl(1 << pin, hwpull);
- else
- stmp3xxx_clearl(1 << pin, hwpull);
-}
-
-int stmp3xxx_request_pin(unsigned id, enum pin_fun fun, const char *label)
-{
- struct stmp3xxx_pinmux_bank *pbank;
- u32 bank, pin;
- int ret = 0;
-
- pbank = stmp3xxx_pinmux_bank(id, &bank, &pin);
- pr_debug("%s: label %s bank %d pin %d fun %d\n", __func__, label,
- bank, pin, fun);
-
- if (test_bit(pin, &pbank->pin_map)) {
- printk(KERN_WARNING
- "%s: CONFLICT DETECTED pin %d:%d caller %s owner %s\n",
- __func__, bank, pin, label, pbank->pin_labels[pin]);
- return -EBUSY;
- }
-
- set_bit(pin, &pbank->pin_map);
- pbank->pin_labels[pin] = label;
-
- stmp3xxx_set_pin_type(id, fun);
-
- return ret;
-}
-
-void stmp3xxx_set_pin_type(unsigned id, enum pin_fun fun)
-{
- struct stmp3xxx_pinmux_bank *pbank;
- void __iomem *hwmux;
- u32 shift, val;
- u32 bank, pin;
-
- pbank = stmp3xxx_pinmux_bank(id, &bank, &pin);
-
- hwmux = pbank->hw_muxsel[pin / HW_MUXSEL_PIN_NUM];
- shift = (pin % HW_MUXSEL_PIN_NUM) * HW_MUXSEL_PIN_LEN;
-
- val = pbank->functions[fun];
- shift = (pin % HW_MUXSEL_PIN_NUM) * HW_MUXSEL_PIN_LEN;
- pr_debug("%s: writing 0x%x to 0x%p register\n",
- __func__, val << shift, hwmux);
- stmp3xxx_clearl(HW_MUXSEL_PINFUN_MASK << shift, hwmux);
- stmp3xxx_setl(val << shift, hwmux);
-}
-
-void stmp3xxx_release_pin(unsigned id, const char *label)
-{
- struct stmp3xxx_pinmux_bank *pbank;
- u32 bank, pin;
-
- pbank = stmp3xxx_pinmux_bank(id, &bank, &pin);
- pr_debug("%s: label %s bank %d pin %d\n", __func__, label, bank, pin);
-
- if (stmp3xxx_check_pin(id, label))
- return;
-
- clear_bit(pin, &pbank->pin_map);
- pbank->pin_labels[pin] = NULL;
-}
-
-int stmp3xxx_request_pin_group(struct pin_group *pin_group, const char *label)
-{
- struct pin_desc *pin;
- int p;
- int err = 0;
-
- /* Allocate and configure pins */
- for (p = 0; p < pin_group->nr_pins; p++) {
- pr_debug("%s: #%d\n", __func__, p);
- pin = &pin_group->pins[p];
-
- err = stmp3xxx_request_pin(pin->id, pin->fun, label);
- if (err)
- goto out_err;
-
- stmp3xxx_pin_strength(pin->id, pin->strength, label);
- stmp3xxx_pin_voltage(pin->id, pin->voltage, label);
- stmp3xxx_pin_pullup(pin->id, pin->pullup, label);
- }
-
- return 0;
-
-out_err:
- /* Release allocated pins in case of error */
- while (--p >= 0) {
- pr_debug("%s: releasing #%d\n", __func__, p);
- stmp3xxx_release_pin(pin_group->pins[p].id, label);
- }
- return err;
-}
-EXPORT_SYMBOL(stmp3xxx_request_pin_group);
-
-void stmp3xxx_release_pin_group(struct pin_group *pin_group, const char *label)
-{
- struct pin_desc *pin;
- int p;
-
- for (p = 0; p < pin_group->nr_pins; p++) {
- pin = &pin_group->pins[p];
- stmp3xxx_release_pin(pin->id, label);
- }
-}
-EXPORT_SYMBOL(stmp3xxx_release_pin_group);
-
-static int stmp3xxx_irq_data_to_gpio(struct irq_data *d,
- struct stmp3xxx_pinmux_bank **bank, unsigned *gpio)
-{
- struct stmp3xxx_pinmux_bank *pm;
-
- for (pm = pinmux_banks; pm < pinmux_banks + NR_BANKS; pm++)
- if (pm->virq <= d->irq && d->irq < pm->virq + 32) {
- *bank = pm;
- *gpio = d->irq - pm->virq;
- return 0;
- }
- return -ENOENT;
-}
-
-static int stmp3xxx_set_irqtype(struct irq_data *d, unsigned type)
-{
- struct stmp3xxx_pinmux_bank *pm;
- unsigned gpio;
- int l, p;
-
- stmp3xxx_irq_data_to_gpio(d, &pm, &gpio);
- switch (type) {
- case IRQ_TYPE_EDGE_RISING:
- l = 0; p = 1; break;
- case IRQ_TYPE_EDGE_FALLING:
- l = 0; p = 0; break;
- case IRQ_TYPE_LEVEL_HIGH:
- l = 1; p = 1; break;
- case IRQ_TYPE_LEVEL_LOW:
- l = 1; p = 0; break;
- default:
- pr_debug("%s: Incorrect GPIO interrupt type 0x%x\n",
- __func__, type);
- return -ENXIO;
- }
-
- if (l)
- stmp3xxx_setl(1 << gpio, pm->irqlevel);
- else
- stmp3xxx_clearl(1 << gpio, pm->irqlevel);
- if (p)
- stmp3xxx_setl(1 << gpio, pm->irqpolarity);
- else
- stmp3xxx_clearl(1 << gpio, pm->irqpolarity);
- return 0;
-}
-
-static void stmp3xxx_pin_ack_irq(struct irq_data *d)
-{
- u32 stat;
- struct stmp3xxx_pinmux_bank *pm;
- unsigned gpio;
-
- stmp3xxx_irq_data_to_gpio(d, &pm, &gpio);
- stat = __raw_readl(pm->irqstat) & (1 << gpio);
- stmp3xxx_clearl(stat, pm->irqstat);
-}
-
-static void stmp3xxx_pin_mask_irq(struct irq_data *d)
-{
- struct stmp3xxx_pinmux_bank *pm;
- unsigned gpio;
-
- stmp3xxx_irq_data_to_gpio(d, &pm, &gpio);
- stmp3xxx_clearl(1 << gpio, pm->irqen);
- stmp3xxx_clearl(1 << gpio, pm->pin2irq);
-}
-
-static void stmp3xxx_pin_unmask_irq(struct irq_data *d)
-{
- struct stmp3xxx_pinmux_bank *pm;
- unsigned gpio;
-
- stmp3xxx_irq_data_to_gpio(d, &pm, &gpio);
- stmp3xxx_setl(1 << gpio, pm->irqen);
- stmp3xxx_setl(1 << gpio, pm->pin2irq);
-}
-
-static inline
-struct stmp3xxx_pinmux_bank *to_pinmux_bank(struct gpio_chip *chip)
-{
- return container_of(chip, struct stmp3xxx_pinmux_bank, chip);
-}
-
-static int stmp3xxx_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
-{
- struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip);
- return pm->virq + offset;
-}
-
-static int stmp3xxx_gpio_get(struct gpio_chip *chip, unsigned offset)
-{
- struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip);
- unsigned v;
-
- v = __raw_readl(pm->hw_gpio_in) & (1 << offset);
- return v ? 1 : 0;
-}
-
-static void stmp3xxx_gpio_set(struct gpio_chip *chip, unsigned offset, int v)
-{
- struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip);
-
- if (v)
- stmp3xxx_setl(1 << offset, pm->hw_gpio_out);
- else
- stmp3xxx_clearl(1 << offset, pm->hw_gpio_out);
-}
-
-static int stmp3xxx_gpio_output(struct gpio_chip *chip, unsigned offset, int v)
-{
- struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip);
-
- stmp3xxx_setl(1 << offset, pm->hw_gpio_doe);
- stmp3xxx_gpio_set(chip, offset, v);
- return 0;
-}
-
-static int stmp3xxx_gpio_input(struct gpio_chip *chip, unsigned offset)
-{
- struct stmp3xxx_pinmux_bank *pm = to_pinmux_bank(chip);
-
- stmp3xxx_clearl(1 << offset, pm->hw_gpio_doe);
- return 0;
-}
-
-static int stmp3xxx_gpio_request(struct gpio_chip *chip, unsigned offset)
-{
- return stmp3xxx_request_pin(chip->base + offset, PIN_GPIO, "gpio");
-}
-
-static void stmp3xxx_gpio_free(struct gpio_chip *chip, unsigned offset)
-{
- stmp3xxx_release_pin(chip->base + offset, "gpio");
-}
-
-static void stmp3xxx_gpio_irq(u32 irq, struct irq_desc *desc)
-{
- struct stmp3xxx_pinmux_bank *pm = irq_get_handler_data(irq);
- int gpio_irq = pm->virq;
- u32 stat = __raw_readl(pm->irqstat);
-
- while (stat) {
- if (stat & 1)
- generic_handle_irq(gpio_irq);
- gpio_irq++;
- stat >>= 1;
- }
-}
-
-static struct irq_chip gpio_irq_chip = {
- .irq_ack = stmp3xxx_pin_ack_irq,
- .irq_mask = stmp3xxx_pin_mask_irq,
- .irq_unmask = stmp3xxx_pin_unmask_irq,
- .irq_set_type = stmp3xxx_set_irqtype,
-};
-
-int __init stmp3xxx_pinmux_init(int virtual_irq_start)
-{
- int b, r = 0;
- struct stmp3xxx_pinmux_bank *pm;
- int virq;
-
- for (b = 0; b < 3; b++) {
- /* only banks 0,1,2 are allowed to GPIO */
- pm = pinmux_banks + b;
- pm->chip.base = 32 * b;
- pm->chip.ngpio = 32;
- pm->chip.owner = THIS_MODULE;
- pm->chip.can_sleep = 1;
- pm->chip.exported = 1;
- pm->chip.to_irq = stmp3xxx_gpio_to_irq;
- pm->chip.direction_input = stmp3xxx_gpio_input;
- pm->chip.direction_output = stmp3xxx_gpio_output;
- pm->chip.get = stmp3xxx_gpio_get;
- pm->chip.set = stmp3xxx_gpio_set;
- pm->chip.request = stmp3xxx_gpio_request;
- pm->chip.free = stmp3xxx_gpio_free;
- pm->virq = virtual_irq_start + b * 32;
-
- for (virq = pm->virq; virq < pm->virq; virq++) {
- gpio_irq_chip.irq_mask(irq_get_irq_data(virq));
- irq_set_chip_and_handler(virq, &gpio_irq_chip,
- handle_level_irq);
- set_irq_flags(virq, IRQF_VALID);
- }
- r = gpiochip_add(&pm->chip);
- if (r < 0)
- break;
- irq_set_chained_handler(pm->irq, stmp3xxx_gpio_irq);
- irq_set_handler_data(pm->irq, pm);
- }
- return r;
-}
-
-MODULE_AUTHOR("Vladislav Buzov");
-MODULE_LICENSE("GPL");
diff --git a/arch/arm/plat-stmp3xxx/timer.c b/arch/arm/plat-stmp3xxx/timer.c
deleted file mode 100644
index c395630..0000000
--- a/arch/arm/plat-stmp3xxx/timer.c
+++ /dev/null
@@ -1,186 +0,0 @@
-/*
- * System timer for Freescale STMP37XX/STMP378X
- *
- * Embedded Alley Solutions, Inc <source@embeddedalley.com>
- *
- * Copyright 2008 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Embedded Alley Solutions, Inc All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/spinlock.h>
-#include <linux/clocksource.h>
-#include <linux/clockchips.h>
-#include <linux/io.h>
-#include <linux/irq.h>
-#include <linux/interrupt.h>
-
-#include <asm/mach/time.h>
-#include <mach/stmp3xxx.h>
-#include <mach/platform.h>
-#include <mach/regs-timrot.h>
-
-static irqreturn_t
-stmp3xxx_timer_interrupt(int irq, void *dev_id)
-{
- struct clock_event_device *c = dev_id;
-
- /* timer 0 */
- if (__raw_readl(REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0) &
- BM_TIMROT_TIMCTRLn_IRQ) {
- stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ,
- REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0);
- c->event_handler(c);
- }
-
- /* timer 1 */
- else if (__raw_readl(REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1)
- & BM_TIMROT_TIMCTRLn_IRQ) {
- stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ,
- REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1);
- stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ_EN,
- REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1);
- __raw_writel(0xFFFF, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1);
- }
-
- return IRQ_HANDLED;
-}
-
-static cycle_t stmp3xxx_clock_read(struct clocksource *cs)
-{
- return ~((__raw_readl(REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1)
- & 0xFFFF0000) >> 16);
-}
-
-static int
-stmp3xxx_timrot_set_next_event(unsigned long delta,
- struct clock_event_device *dev)
-{
- /* reload the timer */
- __raw_writel(delta, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0);
- return 0;
-}
-
-static void
-stmp3xxx_timrot_set_mode(enum clock_event_mode mode,
- struct clock_event_device *dev)
-{
-}
-
-static struct clock_event_device ckevt_timrot = {
- .name = "timrot",
- .features = CLOCK_EVT_FEAT_ONESHOT,
- .shift = 32,
- .set_next_event = stmp3xxx_timrot_set_next_event,
- .set_mode = stmp3xxx_timrot_set_mode,
-};
-
-static struct clocksource cksrc_stmp3xxx = {
- .name = "cksrc_stmp3xxx",
- .rating = 250,
- .read = stmp3xxx_clock_read,
- .mask = CLOCKSOURCE_MASK(16),
- .flags = CLOCK_SOURCE_IS_CONTINUOUS,
-};
-
-static struct irqaction stmp3xxx_timer_irq = {
- .name = "stmp3xxx_timer",
- .flags = IRQF_DISABLED | IRQF_TIMER,
- .handler = stmp3xxx_timer_interrupt,
- .dev_id = &ckevt_timrot,
-};
-
-
-/*
- * Set up timer interrupt, and return the current time in seconds.
- */
-static void __init stmp3xxx_init_timer(void)
-{
- ckevt_timrot.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC,
- ckevt_timrot.shift);
- ckevt_timrot.min_delta_ns = clockevent_delta2ns(2, &ckevt_timrot);
- ckevt_timrot.max_delta_ns = clockevent_delta2ns(0xFFF, &ckevt_timrot);
- ckevt_timrot.cpumask = cpumask_of(0);
-
- stmp3xxx_reset_block(REGS_TIMROT_BASE, false);
-
- /* clear two timers */
- __raw_writel(0, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0);
- __raw_writel(0, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1);
-
- /* configure them */
- __raw_writel(
- (8 << BP_TIMROT_TIMCTRLn_SELECT) | /* 32 kHz */
- BM_TIMROT_TIMCTRLn_RELOAD |
- BM_TIMROT_TIMCTRLn_UPDATE |
- BM_TIMROT_TIMCTRLn_IRQ_EN,
- REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0);
- __raw_writel(
- (8 << BP_TIMROT_TIMCTRLn_SELECT) | /* 32 kHz */
- BM_TIMROT_TIMCTRLn_RELOAD |
- BM_TIMROT_TIMCTRLn_UPDATE |
- BM_TIMROT_TIMCTRLn_IRQ_EN,
- REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1);
-
- __raw_writel(CLOCK_TICK_RATE / HZ - 1,
- REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0);
- __raw_writel(0xFFFF, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1);
-
- setup_irq(IRQ_TIMER0, &stmp3xxx_timer_irq);
-
- clocksource_register_hz(&cksrc_stmp3xxx, CLOCK_TICK_RATE);
- clockevents_register_device(&ckevt_timrot);
-}
-
-#ifdef CONFIG_PM
-
-void stmp3xxx_suspend_timer(void)
-{
- stmp3xxx_clearl(BM_TIMROT_TIMCTRLn_IRQ_EN | BM_TIMROT_TIMCTRLn_IRQ,
- REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0);
- stmp3xxx_setl(BM_TIMROT_ROTCTRL_CLKGATE,
- REGS_TIMROT_BASE + HW_TIMROT_ROTCTRL);
-}
-
-void stmp3xxx_resume_timer(void)
-{
- stmp3xxx_clearl(BM_TIMROT_ROTCTRL_SFTRST | BM_TIMROT_ROTCTRL_CLKGATE,
- REGS_TIMROT_BASE + HW_TIMROT_ROTCTRL);
- __raw_writel(
- 8 << BP_TIMROT_TIMCTRLn_SELECT | /* 32 kHz */
- BM_TIMROT_TIMCTRLn_RELOAD |
- BM_TIMROT_TIMCTRLn_UPDATE |
- BM_TIMROT_TIMCTRLn_IRQ_EN,
- REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL0);
- __raw_writel(
- 8 << BP_TIMROT_TIMCTRLn_SELECT | /* 32 kHz */
- BM_TIMROT_TIMCTRLn_RELOAD |
- BM_TIMROT_TIMCTRLn_UPDATE |
- BM_TIMROT_TIMCTRLn_IRQ_EN,
- REGS_TIMROT_BASE + HW_TIMROT_TIMCTRL1);
- __raw_writel(CLOCK_TICK_RATE / HZ - 1,
- REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT0);
- __raw_writel(0xFFFF, REGS_TIMROT_BASE + HW_TIMROT_TIMCOUNT1);
-}
-
-#else
-
-#define stmp3xxx_suspend_timer NULL
-#define stmp3xxx_resume_timer NULL
-
-#endif /* CONFIG_PM */
-
-struct sys_timer stmp3xxx_timer = {
- .init = stmp3xxx_init_timer,
- .suspend = stmp3xxx_suspend_timer,
- .resume = stmp3xxx_resume_timer,
-};
diff --git a/arch/arm/plat-versatile/platsmp.c b/arch/arm/plat-versatile/platsmp.c
index ba3d471..51ecfea 100644
--- a/arch/arm/plat-versatile/platsmp.c
+++ b/arch/arm/plat-versatile/platsmp.c
@@ -16,6 +16,7 @@
#include <linux/smp.h>
#include <asm/cacheflush.h>
+#include <asm/hardware/gic.h>
/*
* control for which core is the next to come out of the secondary
@@ -83,7 +84,7 @@
* the boot monitor to read the system wide flags register,
* and branch to the address found there.
*/
- smp_cross_call(cpumask_of(cpu), 1);
+ gic_raise_softirq(cpumask_of(cpu), 1);
timeout = jiffies + (1 * HZ);
while (time_before(jiffies, timeout)) {
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index 7ca41f0..3b3776d 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -17,7 +17,7 @@
# XXX: the last 12 months. If your entry is missing please email rmk at
# XXX: <linux@arm.linux.org.uk>
#
-# Last update: Sun Mar 20 18:06:11 2011
+# Last update: Sat May 7 08:48:24 2011
#
# machine_is_xxx CONFIG_xxxx MACH_TYPE_xxx number
#
@@ -377,6 +377,8 @@
at91sam9g10ek MACH_AT91SAM9G10EK AT91SAM9G10EK 2159
omap_4430sdp MACH_OMAP_4430SDP OMAP_4430SDP 2160
magx_zn5 MACH_MAGX_ZN5 MAGX_ZN5 2162
+btmavb101 MACH_BTMAVB101 BTMAVB101 2172
+btmawb101 MACH_BTMAWB101 BTMAWB101 2173
omap3_torpedo MACH_OMAP3_TORPEDO OMAP3_TORPEDO 2178
anw6410 MACH_ANW6410 ANW6410 2183
imx27_visstrim_m10 MACH_IMX27_VISSTRIM_M10 IMX27_VISSTRIM_M10 2187
@@ -400,6 +402,7 @@
bigdisk MACH_BIGDISK BIGDISK 2283
at91sam9g20ek_2mmc MACH_AT91SAM9G20EK_2MMC AT91SAM9G20EK_2MMC 2288
bcmring MACH_BCMRING BCMRING 2289
+dp6xx MACH_DP6XX DP6XX 2302
mahimahi MACH_MAHIMAHI MAHIMAHI 2304
smdk6442 MACH_SMDK6442 SMDK6442 2324
openrd_base MACH_OPENRD_BASE OPENRD_BASE 2325
@@ -424,6 +427,7 @@
omap_zoom3 MACH_OMAP_ZOOM3 OMAP_ZOOM3 2464
omap_3630sdp MACH_OMAP_3630SDP OMAP_3630SDP 2465
smartq7 MACH_SMARTQ7 SMARTQ7 2479
+watson_efm_plugin MACH_WATSON_EFM_PLUGIN WATSON_EFM_PLUGIN 2491
g4evm MACH_G4EVM G4EVM 2493
omapl138_hawkboard MACH_OMAPL138_HAWKBOARD OMAPL138_HAWKBOARD 2495
ts41x MACH_TS41X TS41X 2502
@@ -433,6 +437,8 @@
smartq5 MACH_SMARTQ5 SMARTQ5 2534
davinci_dm6467tevm MACH_DAVINCI_DM6467TEVM DAVINCI_DM6467TEVM 2548
mxt_td60 MACH_MXT_TD60 MXT_TD60 2550
+riot_bei2 MACH_RIOT_BEI2 RIOT_BEI2 2576
+riot_x37 MACH_RIOT_X37 RIOT_X37 2578
capc7117 MACH_CAPC7117 CAPC7117 2612
icontrol MACH_ICONTROL ICONTROL 2624
qsd8x50a_st1_5 MACH_QSD8X50A_ST1_5 QSD8X50A_ST1_5 2627
@@ -445,6 +451,7 @@
aquila MACH_AQUILA AQUILA 2676
sheeva_esata MACH_ESATA_SHEEVAPLUG ESATA_SHEEVAPLUG 2678
msm7x30_surf MACH_MSM7X30_SURF MSM7X30_SURF 2679
+ea2478devkit MACH_EA2478DEVKIT EA2478DEVKIT 2683
terastation_wxl MACH_TERASTATION_WXL TERASTATION_WXL 2697
msm7x25_surf MACH_MSM7X25_SURF MSM7X25_SURF 2703
msm7x25_ffa MACH_MSM7X25_FFA MSM7X25_FFA 2704
@@ -463,75 +470,16 @@
msm8x60_surf MACH_MSM8X60_SURF MSM8X60_SURF 2755
msm8x60_sim MACH_MSM8X60_SIM MSM8X60_SIM 2756
tcc8000_sdk MACH_TCC8000_SDK TCC8000_SDK 2758
-ap420 MACH_AP420 AP420 2765
-davinci_dm365_fc MACH_DAVINCI_DM365_FC DAVINCI_DM365_FC 2767
-msm8x55_surf MACH_MSM8X55_SURF MSM8X55_SURF 2768
-msm8x55_ffa MACH_MSM8X55_FFA MSM8X55_FFA 2769
-esl_vamana MACH_ESL_VAMANA ESL_VAMANA 2770
-sbc35 MACH_SBC35 SBC35 2771
-mpx6446 MACH_MPX6446 MPX6446 2772
-oreo_controller MACH_OREO_CONTROLLER OREO_CONTROLLER 2773
-kopin_models MACH_KOPIN_MODELS KOPIN_MODELS 2774
-ttc_vision2 MACH_TTC_VISION2 TTC_VISION2 2775
+nanos MACH_NANOS NANOS 2759
+stamp9g45 MACH_STAMP9G45 STAMP9G45 2761
cns3420vb MACH_CNS3420VB CNS3420VB 2776
-olympus MACH_OLYMPUS OLYMPUS 2778
-vortex MACH_VORTEX VORTEX 2779
-s5pc200 MACH_S5PC200 S5PC200 2780
-ecucore_9263 MACH_ECUCORE_9263 ECUCORE_9263 2781
-smdkc200 MACH_SMDKC200 SMDKC200 2782
-emsiso_sx27 MACH_EMSISO_SX27 EMSISO_SX27 2783
-apx_som9g45_ek MACH_APX_SOM9G45_EK APX_SOM9G45_EK 2784
-songshan MACH_SONGSHAN SONGSHAN 2785
-tianshan MACH_TIANSHAN TIANSHAN 2786
-vpx500 MACH_VPX500 VPX500 2787
-am3517sam MACH_AM3517SAM AM3517SAM 2788
-skat91_sim508 MACH_SKAT91_SIM508 SKAT91_SIM508 2789
-skat91_s3e MACH_SKAT91_S3E SKAT91_S3E 2790
omap4_panda MACH_OMAP4_PANDA OMAP4_PANDA 2791
-df7220 MACH_DF7220 DF7220 2792
-nemini MACH_NEMINI NEMINI 2793
-t8200 MACH_T8200 T8200 2794
-apf51 MACH_APF51 APF51 2795
-dr_rc_unit MACH_DR_RC_UNIT DR_RC_UNIT 2796
-bordeaux MACH_BORDEAUX BORDEAUX 2797
-catania_b MACH_CATANIA_B CATANIA_B 2798
-mx51_ocean MACH_MX51_OCEAN MX51_OCEAN 2799
ti8168evm MACH_TI8168EVM TI8168EVM 2800
-neocoreomap MACH_NEOCOREOMAP NEOCOREOMAP 2801
-withings_wbp MACH_WITHINGS_WBP WITHINGS_WBP 2802
-dbps MACH_DBPS DBPS 2803
-pcbfp0001 MACH_PCBFP0001 PCBFP0001 2805
-speedy MACH_SPEEDY SPEEDY 2806
-chrysaor MACH_CHRYSAOR CHRYSAOR 2807
-tango MACH_TANGO TANGO 2808
-synology_dsx11 MACH_SYNOLOGY_DSX11 SYNOLOGY_DSX11 2809
-hanlin_v3ext MACH_HANLIN_V3EXT HANLIN_V3EXT 2810
-hanlin_v5 MACH_HANLIN_V5 HANLIN_V5 2811
-hanlin_v3plus MACH_HANLIN_V3PLUS HANLIN_V3PLUS 2812
-iriver_story MACH_IRIVER_STORY IRIVER_STORY 2813
-irex_iliad MACH_IREX_ILIAD IREX_ILIAD 2814
-irex_dr1000 MACH_IREX_DR1000 IREX_DR1000 2815
teton_bga MACH_TETON_BGA TETON_BGA 2816
-snapper9g45 MACH_SNAPPER9G45 SNAPPER9G45 2817
-tam3517 MACH_TAM3517 TAM3517 2818
-pdc100 MACH_PDC100 PDC100 2819
eukrea_cpuimx25sd MACH_EUKREA_CPUIMX25 EUKREA_CPUIMX25 2820
eukrea_cpuimx35sd MACH_EUKREA_CPUIMX35 EUKREA_CPUIMX35 2821
eukrea_cpuimx51sd MACH_EUKREA_CPUIMX51SD EUKREA_CPUIMX51SD 2822
eukrea_cpuimx51 MACH_EUKREA_CPUIMX51 EUKREA_CPUIMX51 2823
-p565 MACH_P565 P565 2824
-acer_a4 MACH_ACER_A4 ACER_A4 2825
-davinci_dm368_bip MACH_DAVINCI_DM368_BIP DAVINCI_DM368_BIP 2826
-eshare MACH_ESHARE ESHARE 2827
-wlbargn MACH_WLBARGN WLBARGN 2829
-bm170 MACH_BM170 BM170 2830
-netspace_mini_v2 MACH_NETSPACE_MINI_V2 NETSPACE_MINI_V2 2831
-netspace_plug_v2 MACH_NETSPACE_PLUG_V2 NETSPACE_PLUG_V2 2832
-siemens_l1 MACH_SIEMENS_L1 SIEMENS_L1 2833
-elv_lcu1 MACH_ELV_LCU1 ELV_LCU1 2834
-mcu1 MACH_MCU1 MCU1 2835
-omap3_tao3530 MACH_OMAP3_TAO3530 OMAP3_TAO3530 2836
-omap3_pcutouch MACH_OMAP3_PCUTOUCH OMAP3_PCUTOUCH 2837
smdkc210 MACH_SMDKC210 SMDKC210 2838
omap3_braillo MACH_OMAP3_BRAILLO OMAP3_BRAILLO 2839
spyplug MACH_SPYPLUG SPYPLUG 2840
@@ -973,9 +921,7 @@
rascal MACH_RASCAL RASCAL 3292
hrefv60 MACH_HREFV60 HREFV60 3293
tpt_2_0 MACH_TPT_2_0 TPT_2_0 3294
-pyramid_td MACH_PYRAMID_TD PYRAMID_TD 3295
splendor MACH_SPLENDOR SPLENDOR 3296
-guf_planet MACH_GUF_PLANET GUF_PLANET 3297
msm8x60_qt MACH_MSM8X60_QT MSM8X60_QT 3298
htc_hd_mini MACH_HTC_HD_MINI HTC_HD_MINI 3299
athene MACH_ATHENE ATHENE 3300
@@ -1099,3 +1045,71 @@
hsgx6d MACH_HSGX6D HSGX6D 3422
dawad7 MACH_DAWAD7 DAWAD7 3423
sam9repeater MACH_SAM9REPEATER SAM9REPEATER 3424
+gt_i5700 MACH_GT_I5700 GT_I5700 3425
+ctera_plug_c2 MACH_CTERA_PLUG_C2 CTERA_PLUG_C2 3426
+marvelct MACH_MARVELCT MARVELCT 3427
+ag11005 MACH_AG11005 AG11005 3428
+vangogh MACH_VANGOGH VANGOGH 3430
+matrix505 MACH_MATRIX505 MATRIX505 3431
+oce_nigma MACH_OCE_NIGMA OCE_NIGMA 3432
+t55 MACH_T55 T55 3433
+bio3k MACH_BIO3K BIO3K 3434
+expressct MACH_EXPRESSCT EXPRESSCT 3435
+cardhu MACH_CARDHU CARDHU 3436
+aruba MACH_ARUBA ARUBA 3437
+bonaire MACH_BONAIRE BONAIRE 3438
+nuc700evb MACH_NUC700EVB NUC700EVB 3439
+nuc710evb MACH_NUC710EVB NUC710EVB 3440
+nuc740evb MACH_NUC740EVB NUC740EVB 3441
+nuc745evb MACH_NUC745EVB NUC745EVB 3442
+transcede MACH_TRANSCEDE TRANSCEDE 3443
+mora MACH_MORA MORA 3444
+nda_evm MACH_NDA_EVM NDA_EVM 3445
+timu MACH_TIMU TIMU 3446
+expressh MACH_EXPRESSH EXPRESSH 3447
+veridis_a300 MACH_VERIDIS_A300 VERIDIS_A300 3448
+dm368_leopard MACH_DM368_LEOPARD DM368_LEOPARD 3449
+omap_mcop MACH_OMAP_MCOP OMAP_MCOP 3450
+tritip MACH_TRITIP TRITIP 3451
+sm1k MACH_SM1K SM1K 3452
+monch MACH_MONCH MONCH 3453
+curacao MACH_CURACAO CURACAO 3454
+origen MACH_ORIGEN ORIGEN 3455
+epc10 MACH_EPC10 EPC10 3456
+sgh_i740 MACH_SGH_I740 SGH_I740 3457
+tuna MACH_TUNA TUNA 3458
+mx51_tulip MACH_MX51_TULIP MX51_TULIP 3459
+mx51_aster7 MACH_MX51_ASTER7 MX51_ASTER7 3460
+acro37xbrd MACH_ACRO37XBRD ACRO37XBRD 3461
+elke MACH_ELKE ELKE 3462
+sbc6000x MACH_SBC6000X SBC6000X 3463
+r1801e MACH_R1801E R1801E 3464
+h1600 MACH_H1600 H1600 3465
+mini210 MACH_MINI210 MINI210 3466
+mini8168 MACH_MINI8168 MINI8168 3467
+pc7308 MACH_PC7308 PC7308 3468
+kmm2m01 MACH_KMM2M01 KMM2M01 3470
+mx51erebus MACH_MX51EREBUS MX51EREBUS 3471
+wm8650refboard MACH_WM8650REFBOARD WM8650REFBOARD 3472
+tuxrail MACH_TUXRAIL TUXRAIL 3473
+arthur MACH_ARTHUR ARTHUR 3474
+doorboy MACH_DOORBOY DOORBOY 3475
+xarina MACH_XARINA XARINA 3476
+roverx7 MACH_ROVERX7 ROVERX7 3477
+sdvr MACH_SDVR SDVR 3478
+acer_maya MACH_ACER_MAYA ACER_MAYA 3479
+pico MACH_PICO PICO 3480
+cwmx233 MACH_CWMX233 CWMX233 3481
+cwam1808 MACH_CWAM1808 CWAM1808 3482
+cwdm365 MACH_CWDM365 CWDM365 3483
+mx51_moray MACH_MX51_MORAY MX51_MORAY 3484
+thales_cbc MACH_THALES_CBC THALES_CBC 3485
+bluepoint MACH_BLUEPOINT BLUEPOINT 3486
+dir665 MACH_DIR665 DIR665 3487
+acmerover1 MACH_ACMEROVER1 ACMEROVER1 3488
+shooter_ct MACH_SHOOTER_CT SHOOTER_CT 3489
+bliss MACH_BLISS BLISS 3490
+blissc MACH_BLISSC BLISSC 3491
+thales_adc MACH_THALES_ADC THALES_ADC 3492
+ubisys_p9d_evp MACH_UBISYS_P9D_EVP UBISYS_P9D_EVP 3493
+atdgp318 MACH_ATDGP318 ATDGP318 3494
diff --git a/arch/avr32/mm/init.c b/arch/avr32/mm/init.c
index a7314d4..2798c2d 100644
--- a/arch/avr32/mm/init.c
+++ b/arch/avr32/mm/init.c
@@ -25,8 +25,6 @@
#include <asm/setup.h>
#include <asm/sections.h>
-DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
-
pgd_t swapper_pg_dir[PTRS_PER_PGD] __page_aligned_data;
struct page *empty_zero_page;
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index 8addb12..a18180f 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -24,11 +24,13 @@
select HAVE_FUNCTION_TRACER
select HAVE_FUNCTION_TRACE_MCOUNT_TEST
select HAVE_IDE
+ select HAVE_IRQ_WORK
select HAVE_KERNEL_GZIP if RAMKERNEL
select HAVE_KERNEL_BZIP2 if RAMKERNEL
select HAVE_KERNEL_LZMA if RAMKERNEL
select HAVE_KERNEL_LZO if RAMKERNEL
select HAVE_OPROFILE
+ select HAVE_PERF_EVENTS
select ARCH_WANT_OPTIONAL_GPIOLIB
select HAVE_GENERIC_HARDIRQS
select GENERIC_ATOMIC64
diff --git a/arch/blackfin/Kconfig.debug b/arch/blackfin/Kconfig.debug
index 2641731..e2a3d4c 100644
--- a/arch/blackfin/Kconfig.debug
+++ b/arch/blackfin/Kconfig.debug
@@ -9,15 +9,6 @@
This option will cause messages to be printed if free stack space
drops below a certain limit.
-config DEBUG_STACK_USAGE
- bool "Enable stack utilization instrumentation"
- depends on DEBUG_KERNEL
- help
- Enables the display of the minimum amount of free stack which each
- task has ever had available in the sysrq-T output.
-
- This option will slow down process creation somewhat.
-
config DEBUG_VERBOSE
bool "Verbose fault messages"
default y
@@ -32,7 +23,7 @@
Most people should say N here.
config DEBUG_MMRS
- bool "Generate Blackfin MMR tree"
+ tristate "Generate Blackfin MMR tree"
select DEBUG_FS
help
Create a tree of Blackfin MMRs via the debugfs tree. If
diff --git a/arch/blackfin/configs/BF527-EZKIT-V2_defconfig b/arch/blackfin/configs/BF527-EZKIT-V2_defconfig
index 95cf2ba..8465b3e 100644
--- a/arch/blackfin/configs/BF527-EZKIT-V2_defconfig
+++ b/arch/blackfin/configs/BF527-EZKIT-V2_defconfig
@@ -121,13 +121,11 @@
# CONFIG_LOGO_LINUX_VGA16 is not set
# CONFIG_LOGO_LINUX_CLUT224 is not set
# CONFIG_LOGO_BLACKFIN_VGA16 is not set
-CONFIG_SOUND=m
-CONFIG_SND=m
-CONFIG_SND_SOC=m
-CONFIG_SND_BF5XX_I2S=m
-CONFIG_SND_BF5XX_SOC_SSM2602=m
-CONFIG_SND_BF5XX_AC97=m
-CONFIG_SND_BF5XX_SOC_AD1980=m
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_SOC=y
+CONFIG_SND_BF5XX_I2S=y
+CONFIG_SND_BF5XX_SOC_SSM2602=y
CONFIG_HID_A4TECH=y
CONFIG_HID_APPLE=y
CONFIG_HID_BELKIN=y
diff --git a/arch/blackfin/configs/BF527-EZKIT_defconfig b/arch/blackfin/configs/BF527-EZKIT_defconfig
index 8be8e33..5e7321b 100644
--- a/arch/blackfin/configs/BF527-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF527-EZKIT_defconfig
@@ -96,7 +96,7 @@
# CONFIG_HW_RANDOM is not set
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=m
-CONFIG_I2C_BLACKFIN_TWI=m
+CONFIG_I2C_BLACKFIN_TWI=y
CONFIG_I2C_BLACKFIN_TWI_CLK_KHZ=100
CONFIG_SPI=y
CONFIG_SPI_BFIN=y
@@ -115,13 +115,11 @@
# CONFIG_LOGO_LINUX_VGA16 is not set
# CONFIG_LOGO_LINUX_CLUT224 is not set
# CONFIG_LOGO_BLACKFIN_VGA16 is not set
-CONFIG_SOUND=m
-CONFIG_SND=m
-CONFIG_SND_SOC=m
-CONFIG_SND_BF5XX_I2S=m
-CONFIG_SND_BF5XX_SOC_SSM2602=m
-CONFIG_SND_BF5XX_AC97=m
-CONFIG_SND_BF5XX_SOC_AD1980=m
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_SOC=y
+CONFIG_SND_BF5XX_I2S=y
+CONFIG_SND_BF5XX_SOC_SSM2602=y
CONFIG_HID_A4TECH=y
CONFIG_HID_APPLE=y
CONFIG_HID_BELKIN=y
diff --git a/arch/blackfin/configs/BF533-STAMP_defconfig b/arch/blackfin/configs/BF533-STAMP_defconfig
index 0aafde6..b90d379 100644
--- a/arch/blackfin/configs/BF533-STAMP_defconfig
+++ b/arch/blackfin/configs/BF533-STAMP_defconfig
@@ -99,8 +99,6 @@
CONFIG_SND_SOC=m
CONFIG_SND_BF5XX_I2S=m
CONFIG_SND_BF5XX_SOC_AD73311=m
-CONFIG_SND_BF5XX_AC97=m
-CONFIG_SND_BF5XX_SOC_AD1980=m
# CONFIG_USB_SUPPORT is not set
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_BFIN=y
diff --git a/arch/blackfin/configs/BF537-STAMP_defconfig b/arch/blackfin/configs/BF537-STAMP_defconfig
index c9077fb..0053625 100644
--- a/arch/blackfin/configs/BF537-STAMP_defconfig
+++ b/arch/blackfin/configs/BF537-STAMP_defconfig
@@ -110,8 +110,6 @@
CONFIG_SND_SOC=m
CONFIG_SND_BF5XX_I2S=m
CONFIG_SND_BF5XX_SOC_AD73311=m
-CONFIG_SND_BF5XX_AC97=m
-CONFIG_SND_BF5XX_SOC_AD1980=m
# CONFIG_USB_SUPPORT is not set
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_BFIN=y
diff --git a/arch/blackfin/include/asm/bfin-global.h b/arch/blackfin/include/asm/bfin-global.h
index 121cc04..17bcbf6 100644
--- a/arch/blackfin/include/asm/bfin-global.h
+++ b/arch/blackfin/include/asm/bfin-global.h
@@ -49,16 +49,6 @@
#define dump_bfin_trace_buffer()
#endif
-/* init functions only */
-extern int init_arch_irq(void);
-extern void init_exception_vectors(void);
-extern void program_IAR(void);
-
-extern asmlinkage void lower_to_irq14(void);
-extern asmlinkage void bfin_return_from_exception(void);
-extern asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs);
-extern int bfin_internal_set_wake(unsigned int irq, unsigned int state);
-
extern void *l1_data_A_sram_alloc(size_t);
extern void *l1_data_B_sram_alloc(size_t);
extern void *l1_inst_sram_alloc(size_t);
diff --git a/arch/blackfin/include/asm/bfin_pfmon.h b/arch/blackfin/include/asm/bfin_pfmon.h
new file mode 100644
index 0000000..accd47e
--- /dev/null
+++ b/arch/blackfin/include/asm/bfin_pfmon.h
@@ -0,0 +1,44 @@
+/*
+ * Blackfin Performance Monitor definitions
+ *
+ * Copyright 2005-2011 Analog Devices Inc.
+ *
+ * Licensed under the ADI BSD license or GPL-2 (or later).
+ */
+
+#ifndef __ASM_BFIN_PFMON_H__
+#define __ASM_BFIN_PFMON_H__
+
+/* PFCTL Masks */
+#define PFMON_MASK 0xff
+#define PFCEN_MASK 0x3
+#define PFCEN_DISABLE 0x0
+#define PFCEN_ENABLE_USER 0x1
+#define PFCEN_ENABLE_SUPV 0x2
+#define PFCEN_ENABLE_ALL (PFCEN_ENABLE_USER | PFCEN_ENABLE_SUPV)
+
+#define PFPWR_P 0
+#define PEMUSW0_P 2
+#define PFCEN0_P 3
+#define PFMON0_P 5
+#define PEMUSW1_P 13
+#define PFCEN1_P 14
+#define PFMON1_P 16
+#define PFCNT0_P 24
+#define PFCNT1_P 25
+
+#define PFPWR (1 << PFPWR_P)
+#define PEMUSW(n, x) ((x) << ((n) ? PEMUSW1_P : PEMUSW0_P))
+#define PEMUSW0 PEMUSW(0, 1)
+#define PEMUSW1 PEMUSW(1, 1)
+#define PFCEN(n, x) ((x) << ((n) ? PFCEN1_P : PFCEN0_P))
+#define PFCEN0 PFCEN(0, PFCEN_MASK)
+#define PFCEN1 PFCEN(1, PFCEN_MASK)
+#define PFCNT(n, x) ((x) << ((n) ? PFCNT1_P : PFCNT0_P))
+#define PFCNT0 PFCNT(0, 1)
+#define PFCNT1 PFCNT(1, 1)
+#define PFMON(n, x) ((x) << ((n) ? PFMON1_P : PFMON0_P))
+#define PFMON0 PFMON(0, PFMON_MASK)
+#define PFMON1 PFMON(1, PFMON_MASK)
+
+#endif
diff --git a/arch/blackfin/include/asm/bfin_sport.h b/arch/blackfin/include/asm/bfin_sport.h
index d27600c2..f8568a3 100644
--- a/arch/blackfin/include/asm/bfin_sport.h
+++ b/arch/blackfin/include/asm/bfin_sport.h
@@ -100,6 +100,10 @@
};
#undef __BFP
+struct bfin_snd_platform_data {
+ const unsigned short *pin_req;
+};
+
#define bfin_read_sport_rx32(base) \
({ \
struct sport_register *__mmrs = (void *)base; \
diff --git a/arch/blackfin/include/asm/cacheflush.h b/arch/blackfin/include/asm/cacheflush.h
index 77135b6..9a5b2c5 100644
--- a/arch/blackfin/include/asm/cacheflush.h
+++ b/arch/blackfin/include/asm/cacheflush.h
@@ -39,8 +39,13 @@
static inline void flush_icache_range(unsigned start, unsigned end)
{
-#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
- blackfin_dcache_flush_range(start, end);
+#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK)
+ if (end <= physical_mem_end)
+ blackfin_dcache_flush_range(start, end);
+#endif
+#if defined(CONFIG_BFIN_L2_WRITEBACK)
+ if (start >= L2_START && end <= L2_START + L2_LENGTH)
+ blackfin_dcache_flush_range(start, end);
#endif
/* Make sure all write buffers in the data side of the core
@@ -52,9 +57,17 @@
* the pipeline.
*/
SSYNC();
-#if defined(CONFIG_BFIN_ICACHE)
- blackfin_icache_flush_range(start, end);
- flush_icache_range_others(start, end);
+#if defined(CONFIG_BFIN_EXTMEM_ICACHEABLE)
+ if (end <= physical_mem_end) {
+ blackfin_icache_flush_range(start, end);
+ flush_icache_range_others(start, end);
+ }
+#endif
+#if defined(CONFIG_BFIN_L2_ICACHEABLE)
+ if (start >= L2_START && end <= L2_START + L2_LENGTH) {
+ blackfin_icache_flush_range(start, end);
+ flush_icache_range_others(start, end);
+ }
#endif
}
diff --git a/arch/blackfin/include/asm/cpu.h b/arch/blackfin/include/asm/cpu.h
index 16883e5..0504378 100644
--- a/arch/blackfin/include/asm/cpu.h
+++ b/arch/blackfin/include/asm/cpu.h
@@ -10,11 +10,8 @@
#include <linux/percpu.h>
-struct task_struct;
-
struct blackfin_cpudata {
struct cpu cpu;
- struct task_struct *idle;
unsigned int imemctl;
unsigned int dmemctl;
};
diff --git a/arch/blackfin/include/asm/def_LPBlackfin.h b/arch/blackfin/include/asm/def_LPBlackfin.h
index 7600fe0..8236790 100644
--- a/arch/blackfin/include/asm/def_LPBlackfin.h
+++ b/arch/blackfin/include/asm/def_LPBlackfin.h
@@ -52,10 +52,10 @@
#define bfin_read(addr) \
({ \
- sizeof(*(addr)) == 1 ? bfin_read8(addr) : \
- sizeof(*(addr)) == 2 ? bfin_read16(addr) : \
- sizeof(*(addr)) == 4 ? bfin_read32(addr) : \
- ({ BUG(); 0; }); \
+ sizeof(*(addr)) == 1 ? bfin_read8(addr) : \
+ sizeof(*(addr)) == 2 ? bfin_read16(addr) : \
+ sizeof(*(addr)) == 4 ? bfin_read32(addr) : \
+ ({ BUG(); 0; }); \
})
#define bfin_write(addr, val) \
do { \
@@ -69,13 +69,13 @@
#define bfin_write_or(addr, bits) \
do { \
- void *__addr = (void *)(addr); \
+ typeof(addr) __addr = (addr); \
bfin_write(__addr, bfin_read(__addr) | (bits)); \
} while (0)
#define bfin_write_and(addr, bits) \
do { \
- void *__addr = (void *)(addr); \
+ typeof(addr) __addr = (addr); \
bfin_write(__addr, bfin_read(__addr) & (bits)); \
} while (0)
diff --git a/arch/blackfin/include/asm/irq_handler.h b/arch/blackfin/include/asm/irq_handler.h
index 7fbe423..ee73f79 100644
--- a/arch/blackfin/include/asm/irq_handler.h
+++ b/arch/blackfin/include/asm/irq_handler.h
@@ -10,6 +10,16 @@
#include <linux/types.h>
#include <linux/linkage.h>
+/* init functions only */
+extern int __init init_arch_irq(void);
+extern void init_exception_vectors(void);
+extern void __init program_IAR(void);
+#ifdef init_mach_irq
+extern void __init init_mach_irq(void);
+#else
+# define init_mach_irq()
+#endif
+
/* BASE LEVEL interrupt handler routines */
asmlinkage void evt_exception(void);
asmlinkage void trap(void);
@@ -37,4 +47,19 @@
extern int bfin_request_exception(unsigned int exception, void (*handler)(void));
extern int bfin_free_exception(unsigned int exception, void (*handler)(void));
+extern asmlinkage void lower_to_irq14(void);
+extern asmlinkage void bfin_return_from_exception(void);
+extern asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs);
+extern int bfin_internal_set_wake(unsigned int irq, unsigned int state);
+
+struct irq_data;
+extern void bfin_handle_irq(unsigned irq);
+extern void bfin_ack_noop(struct irq_data *);
+extern void bfin_internal_mask_irq(unsigned int irq);
+extern void bfin_internal_unmask_irq(unsigned int irq);
+
+struct irq_desc;
+extern void bfin_demux_mac_status_irq(unsigned int, struct irq_desc *);
+extern void bfin_demux_gpio_irq(unsigned int, struct irq_desc *);
+
#endif
diff --git a/arch/blackfin/include/asm/kgdb.h b/arch/blackfin/include/asm/kgdb.h
index 8651afe..3ac0c72 100644
--- a/arch/blackfin/include/asm/kgdb.h
+++ b/arch/blackfin/include/asm/kgdb.h
@@ -103,7 +103,11 @@
asm("EXCPT 2;");
}
#define BREAK_INSTR_SIZE 2
-#define CACHE_FLUSH_IS_SAFE 1
+#ifdef CONFIG_SMP
+# define CACHE_FLUSH_IS_SAFE 0
+#else
+# define CACHE_FLUSH_IS_SAFE 1
+#endif
#define HW_INST_WATCHPOINT_NUM 6
#define HW_WATCHPOINT_NUM 8
#define TYPE_INST_WATCHPOINT 0
diff --git a/arch/blackfin/include/asm/perf_event.h b/arch/blackfin/include/asm/perf_event.h
new file mode 100644
index 0000000..3d2b171
--- /dev/null
+++ b/arch/blackfin/include/asm/perf_event.h
@@ -0,0 +1 @@
+#define MAX_HWEVENTS 2
diff --git a/arch/blackfin/include/asm/ptrace.h b/arch/blackfin/include/asm/ptrace.h
index 832d7c0..1066d63 100644
--- a/arch/blackfin/include/asm/ptrace.h
+++ b/arch/blackfin/include/asm/ptrace.h
@@ -108,8 +108,6 @@
extern void show_regs(struct pt_regs *);
#define arch_has_single_step() (1)
-extern void user_enable_single_step(struct task_struct *child);
-extern void user_disable_single_step(struct task_struct *child);
/* common code demands this function */
#define ptrace_disable(child) user_disable_single_step(child)
diff --git a/arch/blackfin/include/mach-common/irq.h b/arch/blackfin/include/mach-common/irq.h
new file mode 100644
index 0000000..cab14e9
--- /dev/null
+++ b/arch/blackfin/include/mach-common/irq.h
@@ -0,0 +1,57 @@
+/*
+ * Common Blackfin IRQ definitions (i.e. the CEC)
+ *
+ * Copyright 2005-2011 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later
+ */
+
+#ifndef _MACH_COMMON_IRQ_H_
+#define _MACH_COMMON_IRQ_H_
+
+/*
+ * Core events interrupt source definitions
+ *
+ * Event Source Event Name
+ * Emulation EMU 0 (highest priority)
+ * Reset RST 1
+ * NMI NMI 2
+ * Exception EVX 3
+ * Reserved -- 4
+ * Hardware Error IVHW 5
+ * Core Timer IVTMR 6
+ * Peripherals IVG7 7
+ * Peripherals IVG8 8
+ * Peripherals IVG9 9
+ * Peripherals IVG10 10
+ * Peripherals IVG11 11
+ * Peripherals IVG12 12
+ * Peripherals IVG13 13
+ * Softirq IVG14 14
+ * System Call IVG15 15 (lowest priority)
+ */
+
+/* The ABSTRACT IRQ definitions */
+#define IRQ_EMU 0 /* Emulation */
+#define IRQ_RST 1 /* reset */
+#define IRQ_NMI 2 /* Non Maskable */
+#define IRQ_EVX 3 /* Exception */
+#define IRQ_UNUSED 4 /* - unused interrupt */
+#define IRQ_HWERR 5 /* Hardware Error */
+#define IRQ_CORETMR 6 /* Core timer */
+
+#define BFIN_IRQ(x) ((x) + 7)
+
+#define IVG7 7
+#define IVG8 8
+#define IVG9 9
+#define IVG10 10
+#define IVG11 11
+#define IVG12 12
+#define IVG13 13
+#define IVG14 14
+#define IVG15 15
+
+#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
+
+#endif
diff --git a/arch/blackfin/kernel/Makefile b/arch/blackfin/kernel/Makefile
index ca5ccc7..d550b24 100644
--- a/arch/blackfin/kernel/Makefile
+++ b/arch/blackfin/kernel/Makefile
@@ -33,7 +33,10 @@
obj-$(CONFIG_STACKTRACE) += stacktrace.o
obj-$(CONFIG_DEBUG_VERBOSE) += trace.o
obj-$(CONFIG_BFIN_PSEUDODBG_INSNS) += pseudodbg.o
+obj-$(CONFIG_PERF_EVENTS) += perf_event.o
# the kgdb test puts code into L2 and without linker
# relaxation, we need to force long calls to/from it
CFLAGS_kgdb_test.o := -mlong-calls -O0
+
+obj-$(CONFIG_DEBUG_MMRS) += debug-mmrs.o
diff --git a/arch/blackfin/kernel/bfin_dma_5xx.c b/arch/blackfin/kernel/bfin_dma_5xx.c
index 6ce8dce..71dbaa4 100644
--- a/arch/blackfin/kernel/bfin_dma_5xx.c
+++ b/arch/blackfin/kernel/bfin_dma_5xx.c
@@ -36,6 +36,11 @@
printk(KERN_INFO "Blackfin DMA Controller\n");
+
+#if ANOMALY_05000480
+ bfin_write_DMAC_TC_PER(0x0111);
+#endif
+
for (i = 0; i < MAX_DMA_CHANNELS; i++) {
atomic_set(&dma_ch[i].chan_status, 0);
dma_ch[i].regs = dma_io_base_addr[i];
diff --git a/arch/blackfin/kernel/bfin_gpio.c b/arch/blackfin/kernel/bfin_gpio.c
index 170cf90..bcf8cf6 100644
--- a/arch/blackfin/kernel/bfin_gpio.c
+++ b/arch/blackfin/kernel/bfin_gpio.c
@@ -10,10 +10,12 @@
#include <linux/module.h>
#include <linux/err.h>
#include <linux/proc_fs.h>
+#include <linux/seq_file.h>
#include <asm/blackfin.h>
#include <asm/gpio.h>
#include <asm/portmux.h>
#include <linux/irq.h>
+#include <asm/irq_handler.h>
#if ANOMALY_05000311 || ANOMALY_05000323
enum {
@@ -534,7 +536,7 @@
#if defined(BF533_FAMILY)
IRQ_PROG_INTB
#elif defined(BF537_FAMILY)
- IRQ_PROG_INTB, IRQ_PORTG_INTB, IRQ_MAC_TX
+ IRQ_PF_INTB_WATCH, IRQ_PORTG_INTB, IRQ_PH_INTB_MAC_TX
#elif defined(BF538_FAMILY)
IRQ_PORTF_INTB
#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
@@ -1203,35 +1205,43 @@
}
#if defined(CONFIG_PROC_FS)
-static int gpio_proc_read(char *buf, char **start, off_t offset,
- int len, int *unused_i, void *unused_v)
+static int gpio_proc_show(struct seq_file *m, void *v)
{
- int c, irq, gpio, outlen = 0;
+ int c, irq, gpio;
for (c = 0; c < MAX_RESOURCES; c++) {
irq = is_reserved(gpio_irq, c, 1);
gpio = is_reserved(gpio, c, 1);
if (!check_gpio(c) && (gpio || irq))
- len = sprintf(buf, "GPIO_%d: \t%s%s \t\tGPIO %s\n", c,
+ seq_printf(m, "GPIO_%d: \t%s%s \t\tGPIO %s\n", c,
get_label(c), (gpio && irq) ? " *" : "",
get_gpio_dir(c) ? "OUTPUT" : "INPUT");
else if (is_reserved(peri, c, 1))
- len = sprintf(buf, "GPIO_%d: \t%s \t\tPeripheral\n", c, get_label(c));
+ seq_printf(m, "GPIO_%d: \t%s \t\tPeripheral\n", c, get_label(c));
else
continue;
- buf += len;
- outlen += len;
}
- return outlen;
+
+ return 0;
}
+static int gpio_proc_open(struct inode *inode, struct file *file)
+{
+ return single_open(file, gpio_proc_show, NULL);
+}
+
+static const struct file_operations gpio_proc_ops = {
+ .open = gpio_proc_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = single_release,
+};
+
static __init int gpio_register_proc(void)
{
struct proc_dir_entry *proc_gpio;
- proc_gpio = create_proc_entry("gpio", S_IRUGO, NULL);
- if (proc_gpio)
- proc_gpio->read_proc = gpio_proc_read;
+ proc_gpio = proc_create("gpio", S_IRUGO, NULL, &gpio_proc_ops);
return proc_gpio != NULL;
}
__initcall(gpio_register_proc);
diff --git a/arch/blackfin/kernel/bfin_ksyms.c b/arch/blackfin/kernel/bfin_ksyms.c
index 2c264b5..c446591 100644
--- a/arch/blackfin/kernel/bfin_ksyms.c
+++ b/arch/blackfin/kernel/bfin_ksyms.c
@@ -11,6 +11,7 @@
#include <asm/cacheflush.h>
#include <asm/io.h>
+#include <asm/irq_handler.h>
/* Allow people to have their own Blackfin exception handler in a module */
EXPORT_SYMBOL(bfin_return_from_exception);
diff --git a/arch/blackfin/kernel/debug-mmrs.c b/arch/blackfin/kernel/debug-mmrs.c
new file mode 100644
index 0000000..94b1d8a
--- /dev/null
+++ b/arch/blackfin/kernel/debug-mmrs.c
@@ -0,0 +1,1860 @@
+/*
+ * debugfs interface to core/system MMRs
+ *
+ * Copyright 2007-2011 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later
+ */
+
+#include <linux/debugfs.h>
+#include <linux/fs.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+
+#include <asm/blackfin.h>
+#include <asm/gpio.h>
+#include <asm/bfin_can.h>
+#include <asm/bfin_dma.h>
+#include <asm/bfin_ppi.h>
+#include <asm/bfin_serial.h>
+#include <asm/bfin5xx_spi.h>
+#include <asm/bfin_twi.h>
+
+/* Common code defines PORT_MUX on us, so redirect the MMR back locally */
+#ifdef BFIN_PORT_MUX
+#undef PORT_MUX
+#define PORT_MUX BFIN_PORT_MUX
+#endif
+
+#define _d(name, bits, addr, perms) debugfs_create_x##bits(name, perms, parent, (u##bits *)addr)
+#define d(name, bits, addr) _d(name, bits, addr, S_IRUSR|S_IWUSR)
+#define d_RO(name, bits, addr) _d(name, bits, addr, S_IRUSR)
+#define d_WO(name, bits, addr) _d(name, bits, addr, S_IWUSR)
+
+#define D_RO(name, bits) d_RO(#name, bits, name)
+#define D_WO(name, bits) d_WO(#name, bits, name)
+#define D32(name) d(#name, 32, name)
+#define D16(name) d(#name, 16, name)
+
+#define REGS_OFF(peri, mmr) offsetof(struct bfin_##peri##_regs, mmr)
+#define __REGS(peri, sname, rname) \
+ do { \
+ struct bfin_##peri##_regs r; \
+ void *addr = (void *)(base + REGS_OFF(peri, rname)); \
+ strcpy(_buf, sname); \
+ if (sizeof(r.rname) == 2) \
+ debugfs_create_x16(buf, S_IRUSR|S_IWUSR, parent, addr); \
+ else \
+ debugfs_create_x32(buf, S_IRUSR|S_IWUSR, parent, addr); \
+ } while (0)
+#define REGS_STR_PFX(buf, pfx, num) \
+ ({ \
+ buf + (num >= 0 ? \
+ sprintf(buf, #pfx "%i_", num) : \
+ sprintf(buf, #pfx "_")); \
+ })
+#define REGS_STR_PFX_C(buf, pfx, num) \
+ ({ \
+ buf + (num >= 0 ? \
+ sprintf(buf, #pfx "%c_", 'A' + num) : \
+ sprintf(buf, #pfx "_")); \
+ })
+
+/*
+ * Core registers (not memory mapped)
+ */
+extern u32 last_seqstat;
+
+static int debug_cclk_get(void *data, u64 *val)
+{
+ *val = get_cclk();
+ return 0;
+}
+DEFINE_SIMPLE_ATTRIBUTE(fops_debug_cclk, debug_cclk_get, NULL, "0x%08llx\n");
+
+static int debug_sclk_get(void *data, u64 *val)
+{
+ *val = get_sclk();
+ return 0;
+}
+DEFINE_SIMPLE_ATTRIBUTE(fops_debug_sclk, debug_sclk_get, NULL, "0x%08llx\n");
+
+#define DEFINE_SYSREG(sr, pre, post) \
+static int sysreg_##sr##_get(void *data, u64 *val) \
+{ \
+ unsigned long tmp; \
+ pre; \
+ __asm__ __volatile__("%0 = " #sr ";" : "=d"(tmp)); \
+ *val = tmp; \
+ return 0; \
+} \
+static int sysreg_##sr##_set(void *data, u64 val) \
+{ \
+ unsigned long tmp = val; \
+ __asm__ __volatile__(#sr " = %0;" : : "d"(tmp)); \
+ post; \
+ return 0; \
+} \
+DEFINE_SIMPLE_ATTRIBUTE(fops_sysreg_##sr, sysreg_##sr##_get, sysreg_##sr##_set, "0x%08llx\n")
+
+DEFINE_SYSREG(cycles, , );
+DEFINE_SYSREG(cycles2, __asm__ __volatile__("%0 = cycles;" : "=d"(tmp)), );
+DEFINE_SYSREG(emudat, , );
+DEFINE_SYSREG(seqstat, , );
+DEFINE_SYSREG(syscfg, , CSYNC());
+#define D_SYSREG(sr) debugfs_create_file(#sr, S_IRUSR|S_IWUSR, parent, NULL, &fops_sysreg_##sr)
+
+/*
+ * CAN
+ */
+#define CAN_OFF(mmr) REGS_OFF(can, mmr)
+#define __CAN(uname, lname) __REGS(can, #uname, lname)
+static void __init __maybe_unused
+bfin_debug_mmrs_can(struct dentry *parent, unsigned long base, int num)
+{
+ static struct dentry *am, *mb;
+ int i, j;
+ char buf[32], *_buf = REGS_STR_PFX(buf, CAN, num);
+
+ if (!am) {
+ am = debugfs_create_dir("am", parent);
+ mb = debugfs_create_dir("mb", parent);
+ }
+
+ __CAN(MC1, mc1);
+ __CAN(MD1, md1);
+ __CAN(TRS1, trs1);
+ __CAN(TRR1, trr1);
+ __CAN(TA1, ta1);
+ __CAN(AA1, aa1);
+ __CAN(RMP1, rmp1);
+ __CAN(RML1, rml1);
+ __CAN(MBTIF1, mbtif1);
+ __CAN(MBRIF1, mbrif1);
+ __CAN(MBIM1, mbim1);
+ __CAN(RFH1, rfh1);
+ __CAN(OPSS1, opss1);
+
+ __CAN(MC2, mc2);
+ __CAN(MD2, md2);
+ __CAN(TRS2, trs2);
+ __CAN(TRR2, trr2);
+ __CAN(TA2, ta2);
+ __CAN(AA2, aa2);
+ __CAN(RMP2, rmp2);
+ __CAN(RML2, rml2);
+ __CAN(MBTIF2, mbtif2);
+ __CAN(MBRIF2, mbrif2);
+ __CAN(MBIM2, mbim2);
+ __CAN(RFH2, rfh2);
+ __CAN(OPSS2, opss2);
+
+ __CAN(CLOCK, clock);
+ __CAN(TIMING, timing);
+ __CAN(DEBUG, debug);
+ __CAN(STATUS, status);
+ __CAN(CEC, cec);
+ __CAN(GIS, gis);
+ __CAN(GIM, gim);
+ __CAN(GIF, gif);
+ __CAN(CONTROL, control);
+ __CAN(INTR, intr);
+ __CAN(VERSION, version);
+ __CAN(MBTD, mbtd);
+ __CAN(EWR, ewr);
+ __CAN(ESR, esr);
+ /*__CAN(UCREG, ucreg); no longer exists */
+ __CAN(UCCNT, uccnt);
+ __CAN(UCRC, ucrc);
+ __CAN(UCCNF, uccnf);
+ __CAN(VERSION2, version2);
+
+ for (i = 0; i < 32; ++i) {
+ sprintf(_buf, "AM%02iL", i);
+ debugfs_create_x16(buf, S_IRUSR|S_IWUSR, am,
+ (u16 *)(base + CAN_OFF(msk[i].aml)));
+ sprintf(_buf, "AM%02iH", i);
+ debugfs_create_x16(buf, S_IRUSR|S_IWUSR, am,
+ (u16 *)(base + CAN_OFF(msk[i].amh)));
+
+ for (j = 0; j < 3; ++j) {
+ sprintf(_buf, "MB%02i_DATA%i", i, j);
+ debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
+ (u16 *)(base + CAN_OFF(chl[i].data[j*2])));
+ }
+ sprintf(_buf, "MB%02i_LENGTH", i);
+ debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
+ (u16 *)(base + CAN_OFF(chl[i].dlc)));
+ sprintf(_buf, "MB%02i_TIMESTAMP", i);
+ debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
+ (u16 *)(base + CAN_OFF(chl[i].tsv)));
+ sprintf(_buf, "MB%02i_ID0", i);
+ debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
+ (u16 *)(base + CAN_OFF(chl[i].id0)));
+ sprintf(_buf, "MB%02i_ID1", i);
+ debugfs_create_x16(buf, S_IRUSR|S_IWUSR, mb,
+ (u16 *)(base + CAN_OFF(chl[i].id1)));
+ }
+}
+#define CAN(num) bfin_debug_mmrs_can(parent, CAN##num##_MC1, num)
+
+/*
+ * DMA
+ */
+#define __DMA(uname, lname) __REGS(dma, #uname, lname)
+static void __init __maybe_unused
+bfin_debug_mmrs_dma(struct dentry *parent, unsigned long base, int num, char mdma, const char *pfx)
+{
+ char buf[32], *_buf;
+
+ if (mdma)
+ _buf = buf + sprintf(buf, "%s_%c%i_", pfx, mdma, num);
+ else
+ _buf = buf + sprintf(buf, "%s%i_", pfx, num);
+
+ __DMA(NEXT_DESC_PTR, next_desc_ptr);
+ __DMA(START_ADDR, start_addr);
+ __DMA(CONFIG, config);
+ __DMA(X_COUNT, x_count);
+ __DMA(X_MODIFY, x_modify);
+ __DMA(Y_COUNT, y_count);
+ __DMA(Y_MODIFY, y_modify);
+ __DMA(CURR_DESC_PTR, curr_desc_ptr);
+ __DMA(CURR_ADDR, curr_addr);
+ __DMA(IRQ_STATUS, irq_status);
+ __DMA(PERIPHERAL_MAP, peripheral_map);
+ __DMA(CURR_X_COUNT, curr_x_count);
+ __DMA(CURR_Y_COUNT, curr_y_count);
+}
+#define _DMA(num, base, mdma, pfx) bfin_debug_mmrs_dma(parent, base, num, mdma, pfx "DMA")
+#define DMA(num) _DMA(num, DMA##num##_NEXT_DESC_PTR, 0, "")
+#define _MDMA(num, x) \
+ do { \
+ _DMA(num, x##DMA_D##num##_CONFIG, 'D', #x); \
+ _DMA(num, x##DMA_S##num##_CONFIG, 'S', #x); \
+ } while (0)
+#define MDMA(num) _MDMA(num, M)
+#define IMDMA(num) _MDMA(num, IM)
+
+/*
+ * EPPI
+ */
+#define __EPPI(uname, lname) __REGS(eppi, #uname, lname)
+static void __init __maybe_unused
+bfin_debug_mmrs_eppi(struct dentry *parent, unsigned long base, int num)
+{
+ char buf[32], *_buf = REGS_STR_PFX(buf, EPPI, num);
+ __EPPI(STATUS, status);
+ __EPPI(HCOUNT, hcount);
+ __EPPI(HDELAY, hdelay);
+ __EPPI(VCOUNT, vcount);
+ __EPPI(VDELAY, vdelay);
+ __EPPI(FRAME, frame);
+ __EPPI(LINE, line);
+ __EPPI(CLKDIV, clkdiv);
+ __EPPI(CONTROL, control);
+ __EPPI(FS1W_HBL, fs1w_hbl);
+ __EPPI(FS1P_AVPL, fs1p_avpl);
+ __EPPI(FS2W_LVB, fs2w_lvb);
+ __EPPI(FS2P_LAVF, fs2p_lavf);
+ __EPPI(CLIP, clip);
+}
+#define EPPI(num) bfin_debug_mmrs_eppi(parent, EPPI##num##_STATUS, num)
+
+/*
+ * General Purpose Timers
+ */
+#define GPTIMER_OFF(mmr) (TIMER0_##mmr - TIMER0_CONFIG)
+#define __GPTIMER(name) \
+ do { \
+ strcpy(_buf, #name); \
+ debugfs_create_x16(buf, S_IRUSR|S_IWUSR, parent, (u16 *)(base + GPTIMER_OFF(name))); \
+ } while (0)
+static void __init __maybe_unused
+bfin_debug_mmrs_gptimer(struct dentry *parent, unsigned long base, int num)
+{
+ char buf[32], *_buf = REGS_STR_PFX(buf, TIMER, num);
+ __GPTIMER(CONFIG);
+ __GPTIMER(COUNTER);
+ __GPTIMER(PERIOD);
+ __GPTIMER(WIDTH);
+}
+#define GPTIMER(num) bfin_debug_mmrs_gptimer(parent, TIMER##num##_CONFIG, num)
+
+/*
+ * Handshake MDMA
+ */
+#define __HMDMA(uname, lname) __REGS(hmdma, #uname, lname)
+static void __init __maybe_unused
+bfin_debug_mmrs_hmdma(struct dentry *parent, unsigned long base, int num)
+{
+ char buf[32], *_buf = REGS_STR_PFX(buf, HMDMA, num);
+ __HMDMA(CONTROL, control);
+ __HMDMA(ECINIT, ecinit);
+ __HMDMA(BCINIT, bcinit);
+ __HMDMA(ECURGENT, ecurgent);
+ __HMDMA(ECOVERFLOW, ecoverflow);
+ __HMDMA(ECOUNT, ecount);
+ __HMDMA(BCOUNT, bcount);
+}
+#define HMDMA(num) bfin_debug_mmrs_hmdma(parent, HMDMA##num##_CONTROL, num)
+
+/*
+ * Port/GPIO
+ */
+#define bfin_gpio_regs gpio_port_t
+#define __PORT(uname, lname) __REGS(gpio, #uname, lname)
+static void __init __maybe_unused
+bfin_debug_mmrs_port(struct dentry *parent, unsigned long base, int num)
+{
+ char buf[32], *_buf;
+#ifdef __ADSPBF54x__
+ _buf = REGS_STR_PFX_C(buf, PORT, num);
+ __PORT(FER, port_fer);
+ __PORT(SET, data_set);
+ __PORT(CLEAR, data_clear);
+ __PORT(DIR_SET, dir_set);
+ __PORT(DIR_CLEAR, dir_clear);
+ __PORT(INEN, inen);
+ __PORT(MUX, port_mux);
+#else
+ _buf = buf + sprintf(buf, "PORT%cIO_", num);
+ __PORT(CLEAR, data_clear);
+ __PORT(SET, data_set);
+ __PORT(TOGGLE, toggle);
+ __PORT(MASKA, maska);
+ __PORT(MASKA_CLEAR, maska_clear);
+ __PORT(MASKA_SET, maska_set);
+ __PORT(MASKA_TOGGLE, maska_toggle);
+ __PORT(MASKB, maskb);
+ __PORT(MASKB_CLEAR, maskb_clear);
+ __PORT(MASKB_SET, maskb_set);
+ __PORT(MASKB_TOGGLE, maskb_toggle);
+ __PORT(DIR, dir);
+ __PORT(POLAR, polar);
+ __PORT(EDGE, edge);
+ __PORT(BOTH, both);
+ __PORT(INEN, inen);
+#endif
+ _buf[-1] = '\0';
+ d(buf, 16, base + REGS_OFF(gpio, data));
+}
+#define PORT(base, num) bfin_debug_mmrs_port(parent, base, num)
+
+/*
+ * PPI
+ */
+#define __PPI(uname, lname) __REGS(ppi, #uname, lname)
+static void __init __maybe_unused
+bfin_debug_mmrs_ppi(struct dentry *parent, unsigned long base, int num)
+{
+ char buf[32], *_buf = REGS_STR_PFX(buf, PPI, num);
+ __PPI(CONTROL, control);
+ __PPI(STATUS, status);
+ __PPI(COUNT, count);
+ __PPI(DELAY, delay);
+ __PPI(FRAME, frame);
+}
+#define PPI(num) bfin_debug_mmrs_ppi(parent, PPI##num##_STATUS, num)
+
+/*
+ * SPI
+ */
+#define __SPI(uname, lname) __REGS(spi, #uname, lname)
+static void __init __maybe_unused
+bfin_debug_mmrs_spi(struct dentry *parent, unsigned long base, int num)
+{
+ char buf[32], *_buf = REGS_STR_PFX(buf, SPI, num);
+ __SPI(CTL, ctl);
+ __SPI(FLG, flg);
+ __SPI(STAT, stat);
+ __SPI(TDBR, tdbr);
+ __SPI(RDBR, rdbr);
+ __SPI(BAUD, baud);
+ __SPI(SHADOW, shadow);
+}
+#define SPI(num) bfin_debug_mmrs_spi(parent, SPI##num##_REGBASE, num)
+
+/*
+ * SPORT
+ */
+static inline int sport_width(void *mmr)
+{
+ unsigned long lmmr = (unsigned long)mmr;
+ if ((lmmr & 0xff) == 0x10)
+ /* SPORT#_TX has 0x10 offset -> SPORT#_TCR2 has 0x04 offset */
+ lmmr -= 0xc;
+ else
+ /* SPORT#_RX has 0x18 offset -> SPORT#_RCR2 has 0x24 offset */
+ lmmr += 0xc;
+ /* extract SLEN field from control register 2 and add 1 */
+ return (bfin_read16(lmmr) & 0x1f) + 1;
+}
+static int sport_set(void *mmr, u64 val)
+{
+ unsigned long flags;
+ local_irq_save(flags);
+ if (sport_width(mmr) <= 16)
+ bfin_write16(mmr, val);
+ else
+ bfin_write32(mmr, val);
+ local_irq_restore(flags);
+ return 0;
+}
+static int sport_get(void *mmr, u64 *val)
+{
+ unsigned long flags;
+ local_irq_save(flags);
+ if (sport_width(mmr) <= 16)
+ *val = bfin_read16(mmr);
+ else
+ *val = bfin_read32(mmr);
+ local_irq_restore(flags);
+ return 0;
+}
+DEFINE_SIMPLE_ATTRIBUTE(fops_sport, sport_get, sport_set, "0x%08llx\n");
+/*DEFINE_SIMPLE_ATTRIBUTE(fops_sport_ro, sport_get, NULL, "0x%08llx\n");*/
+DEFINE_SIMPLE_ATTRIBUTE(fops_sport_wo, NULL, sport_set, "0x%08llx\n");
+#define SPORT_OFF(mmr) (SPORT0_##mmr - SPORT0_TCR1)
+#define _D_SPORT(name, perms, fops) \
+ do { \
+ strcpy(_buf, #name); \
+ debugfs_create_file(buf, perms, parent, (void *)(base + SPORT_OFF(name)), fops); \
+ } while (0)
+#define __SPORT_RW(name) _D_SPORT(name, S_IRUSR|S_IWUSR, &fops_sport)
+#define __SPORT_RO(name) _D_SPORT(name, S_IRUSR, &fops_sport_ro)
+#define __SPORT_WO(name) _D_SPORT(name, S_IWUSR, &fops_sport_wo)
+#define __SPORT(name, bits) \
+ do { \
+ strcpy(_buf, #name); \
+ debugfs_create_x##bits(buf, S_IRUSR|S_IWUSR, parent, (u##bits *)(base + SPORT_OFF(name))); \
+ } while (0)
+static void __init __maybe_unused
+bfin_debug_mmrs_sport(struct dentry *parent, unsigned long base, int num)
+{
+ char buf[32], *_buf = REGS_STR_PFX(buf, SPORT, num);
+ __SPORT(CHNL, 16);
+ __SPORT(MCMC1, 16);
+ __SPORT(MCMC2, 16);
+ __SPORT(MRCS0, 32);
+ __SPORT(MRCS1, 32);
+ __SPORT(MRCS2, 32);
+ __SPORT(MRCS3, 32);
+ __SPORT(MTCS0, 32);
+ __SPORT(MTCS1, 32);
+ __SPORT(MTCS2, 32);
+ __SPORT(MTCS3, 32);
+ __SPORT(RCLKDIV, 16);
+ __SPORT(RCR1, 16);
+ __SPORT(RCR2, 16);
+ __SPORT(RFSDIV, 16);
+ __SPORT_RW(RX);
+ __SPORT(STAT, 16);
+ __SPORT(TCLKDIV, 16);
+ __SPORT(TCR1, 16);
+ __SPORT(TCR2, 16);
+ __SPORT(TFSDIV, 16);
+ __SPORT_WO(TX);
+}
+#define SPORT(num) bfin_debug_mmrs_sport(parent, SPORT##num##_TCR1, num)
+
+/*
+ * TWI
+ */
+#define __TWI(uname, lname) __REGS(twi, #uname, lname)
+static void __init __maybe_unused
+bfin_debug_mmrs_twi(struct dentry *parent, unsigned long base, int num)
+{
+ char buf[32], *_buf = REGS_STR_PFX(buf, TWI, num);
+ __TWI(CLKDIV, clkdiv);
+ __TWI(CONTROL, control);
+ __TWI(SLAVE_CTL, slave_ctl);
+ __TWI(SLAVE_STAT, slave_stat);
+ __TWI(SLAVE_ADDR, slave_addr);
+ __TWI(MASTER_CTL, master_ctl);
+ __TWI(MASTER_STAT, master_stat);
+ __TWI(MASTER_ADDR, master_addr);
+ __TWI(INT_STAT, int_stat);
+ __TWI(INT_MASK, int_mask);
+ __TWI(FIFO_CTL, fifo_ctl);
+ __TWI(FIFO_STAT, fifo_stat);
+ __TWI(XMT_DATA8, xmt_data8);
+ __TWI(XMT_DATA16, xmt_data16);
+ __TWI(RCV_DATA8, rcv_data8);
+ __TWI(RCV_DATA16, rcv_data16);
+}
+#define TWI(num) bfin_debug_mmrs_twi(parent, TWI##num##_CLKDIV, num)
+
+/*
+ * UART
+ */
+#define __UART(uname, lname) __REGS(uart, #uname, lname)
+static void __init __maybe_unused
+bfin_debug_mmrs_uart(struct dentry *parent, unsigned long base, int num)
+{
+ char buf[32], *_buf = REGS_STR_PFX(buf, UART, num);
+#ifdef BFIN_UART_BF54X_STYLE
+ __UART(DLL, dll);
+ __UART(DLH, dlh);
+ __UART(GCTL, gctl);
+ __UART(LCR, lcr);
+ __UART(MCR, mcr);
+ __UART(LSR, lsr);
+ __UART(MSR, msr);
+ __UART(SCR, scr);
+ __UART(IER_SET, ier_set);
+ __UART(IER_CLEAR, ier_clear);
+ __UART(THR, thr);
+ __UART(RBR, rbr);
+#else
+ __UART(DLL, dll);
+ __UART(THR, thr);
+ __UART(RBR, rbr);
+ __UART(DLH, dlh);
+ __UART(IER, ier);
+ __UART(IIR, iir);
+ __UART(LCR, lcr);
+ __UART(MCR, mcr);
+ __UART(LSR, lsr);
+ __UART(MSR, msr);
+ __UART(SCR, scr);
+ __UART(GCTL, gctl);
+#endif
+}
+#define UART(num) bfin_debug_mmrs_uart(parent, UART##num##_DLL, num)
+
+/*
+ * The actual debugfs generation
+ */
+static struct dentry *debug_mmrs_dentry;
+
+static int __init bfin_debug_mmrs_init(void)
+{
+ struct dentry *top, *parent;
+
+ pr_info("debug-mmrs: setting up Blackfin MMR debugfs\n");
+
+ top = debugfs_create_dir("blackfin", NULL);
+ if (top == NULL)
+ return -1;
+
+ parent = debugfs_create_dir("core_regs", top);
+ debugfs_create_file("cclk", S_IRUSR, parent, NULL, &fops_debug_cclk);
+ debugfs_create_file("sclk", S_IRUSR, parent, NULL, &fops_debug_sclk);
+ debugfs_create_x32("last_seqstat", S_IRUSR, parent, &last_seqstat);
+ D_SYSREG(cycles);
+ D_SYSREG(cycles2);
+ D_SYSREG(emudat);
+ D_SYSREG(seqstat);
+ D_SYSREG(syscfg);
+
+ /* Core MMRs */
+ parent = debugfs_create_dir("ctimer", top);
+ D32(TCNTL);
+ D32(TCOUNT);
+ D32(TPERIOD);
+ D32(TSCALE);
+
+ parent = debugfs_create_dir("cec", top);
+ D32(EVT0);
+ D32(EVT1);
+ D32(EVT2);
+ D32(EVT3);
+ D32(EVT4);
+ D32(EVT5);
+ D32(EVT6);
+ D32(EVT7);
+ D32(EVT8);
+ D32(EVT9);
+ D32(EVT10);
+ D32(EVT11);
+ D32(EVT12);
+ D32(EVT13);
+ D32(EVT14);
+ D32(EVT15);
+ D32(EVT_OVERRIDE);
+ D32(IMASK);
+ D32(IPEND);
+ D32(ILAT);
+ D32(IPRIO);
+
+ parent = debugfs_create_dir("debug", top);
+ D32(DBGSTAT);
+ D32(DSPID);
+
+ parent = debugfs_create_dir("mmu", top);
+ D32(SRAM_BASE_ADDRESS);
+ D32(DCPLB_ADDR0);
+ D32(DCPLB_ADDR10);
+ D32(DCPLB_ADDR11);
+ D32(DCPLB_ADDR12);
+ D32(DCPLB_ADDR13);
+ D32(DCPLB_ADDR14);
+ D32(DCPLB_ADDR15);
+ D32(DCPLB_ADDR1);
+ D32(DCPLB_ADDR2);
+ D32(DCPLB_ADDR3);
+ D32(DCPLB_ADDR4);
+ D32(DCPLB_ADDR5);
+ D32(DCPLB_ADDR6);
+ D32(DCPLB_ADDR7);
+ D32(DCPLB_ADDR8);
+ D32(DCPLB_ADDR9);
+ D32(DCPLB_DATA0);
+ D32(DCPLB_DATA10);
+ D32(DCPLB_DATA11);
+ D32(DCPLB_DATA12);
+ D32(DCPLB_DATA13);
+ D32(DCPLB_DATA14);
+ D32(DCPLB_DATA15);
+ D32(DCPLB_DATA1);
+ D32(DCPLB_DATA2);
+ D32(DCPLB_DATA3);
+ D32(DCPLB_DATA4);
+ D32(DCPLB_DATA5);
+ D32(DCPLB_DATA6);
+ D32(DCPLB_DATA7);
+ D32(DCPLB_DATA8);
+ D32(DCPLB_DATA9);
+ D32(DCPLB_FAULT_ADDR);
+ D32(DCPLB_STATUS);
+ D32(DMEM_CONTROL);
+ D32(DTEST_COMMAND);
+ D32(DTEST_DATA0);
+ D32(DTEST_DATA1);
+
+ D32(ICPLB_ADDR0);
+ D32(ICPLB_ADDR1);
+ D32(ICPLB_ADDR2);
+ D32(ICPLB_ADDR3);
+ D32(ICPLB_ADDR4);
+ D32(ICPLB_ADDR5);
+ D32(ICPLB_ADDR6);
+ D32(ICPLB_ADDR7);
+ D32(ICPLB_ADDR8);
+ D32(ICPLB_ADDR9);
+ D32(ICPLB_ADDR10);
+ D32(ICPLB_ADDR11);
+ D32(ICPLB_ADDR12);
+ D32(ICPLB_ADDR13);
+ D32(ICPLB_ADDR14);
+ D32(ICPLB_ADDR15);
+ D32(ICPLB_DATA0);
+ D32(ICPLB_DATA1);
+ D32(ICPLB_DATA2);
+ D32(ICPLB_DATA3);
+ D32(ICPLB_DATA4);
+ D32(ICPLB_DATA5);
+ D32(ICPLB_DATA6);
+ D32(ICPLB_DATA7);
+ D32(ICPLB_DATA8);
+ D32(ICPLB_DATA9);
+ D32(ICPLB_DATA10);
+ D32(ICPLB_DATA11);
+ D32(ICPLB_DATA12);
+ D32(ICPLB_DATA13);
+ D32(ICPLB_DATA14);
+ D32(ICPLB_DATA15);
+ D32(ICPLB_FAULT_ADDR);
+ D32(ICPLB_STATUS);
+ D32(IMEM_CONTROL);
+ if (!ANOMALY_05000481) {
+ D32(ITEST_COMMAND);
+ D32(ITEST_DATA0);
+ D32(ITEST_DATA1);
+ }
+
+ parent = debugfs_create_dir("perf", top);
+ D32(PFCNTR0);
+ D32(PFCNTR1);
+ D32(PFCTL);
+
+ parent = debugfs_create_dir("trace", top);
+ D32(TBUF);
+ D32(TBUFCTL);
+ D32(TBUFSTAT);
+
+ parent = debugfs_create_dir("watchpoint", top);
+ D32(WPIACTL);
+ D32(WPIA0);
+ D32(WPIA1);
+ D32(WPIA2);
+ D32(WPIA3);
+ D32(WPIA4);
+ D32(WPIA5);
+ D32(WPIACNT0);
+ D32(WPIACNT1);
+ D32(WPIACNT2);
+ D32(WPIACNT3);
+ D32(WPIACNT4);
+ D32(WPIACNT5);
+ D32(WPDACTL);
+ D32(WPDA0);
+ D32(WPDA1);
+ D32(WPDACNT0);
+ D32(WPDACNT1);
+ D32(WPSTAT);
+
+ /* System MMRs */
+#ifdef ATAPI_CONTROL
+ parent = debugfs_create_dir("atapi", top);
+ D16(ATAPI_CONTROL);
+ D16(ATAPI_DEV_ADDR);
+ D16(ATAPI_DEV_RXBUF);
+ D16(ATAPI_DEV_TXBUF);
+ D16(ATAPI_DMA_TFRCNT);
+ D16(ATAPI_INT_MASK);
+ D16(ATAPI_INT_STATUS);
+ D16(ATAPI_LINE_STATUS);
+ D16(ATAPI_MULTI_TIM_0);
+ D16(ATAPI_MULTI_TIM_1);
+ D16(ATAPI_MULTI_TIM_2);
+ D16(ATAPI_PIO_TFRCNT);
+ D16(ATAPI_PIO_TIM_0);
+ D16(ATAPI_PIO_TIM_1);
+ D16(ATAPI_REG_TIM_0);
+ D16(ATAPI_SM_STATE);
+ D16(ATAPI_STATUS);
+ D16(ATAPI_TERMINATE);
+ D16(ATAPI_UDMAOUT_TFRCNT);
+ D16(ATAPI_ULTRA_TIM_0);
+ D16(ATAPI_ULTRA_TIM_1);
+ D16(ATAPI_ULTRA_TIM_2);
+ D16(ATAPI_ULTRA_TIM_3);
+ D16(ATAPI_UMAIN_TFRCNT);
+ D16(ATAPI_XFER_LEN);
+#endif
+
+#if defined(CAN_MC1) || defined(CAN0_MC1) || defined(CAN1_MC1)
+ parent = debugfs_create_dir("can", top);
+# ifdef CAN_MC1
+ bfin_debug_mmrs_can(parent, CAN_MC1, -1);
+# endif
+# ifdef CAN0_MC1
+ CAN(0);
+# endif
+# ifdef CAN1_MC1
+ CAN(1);
+# endif
+#endif
+
+#ifdef CNT_COMMAND
+ parent = debugfs_create_dir("counter", top);
+ D16(CNT_COMMAND);
+ D16(CNT_CONFIG);
+ D32(CNT_COUNTER);
+ D16(CNT_DEBOUNCE);
+ D16(CNT_IMASK);
+ D32(CNT_MAX);
+ D32(CNT_MIN);
+ D16(CNT_STATUS);
+#endif
+
+ parent = debugfs_create_dir("dmac", top);
+#ifdef DMA_TC_CNT
+ D16(DMAC_TC_CNT);
+ D16(DMAC_TC_PER);
+#endif
+#ifdef DMAC0_TC_CNT
+ D16(DMAC0_TC_CNT);
+ D16(DMAC0_TC_PER);
+#endif
+#ifdef DMAC1_TC_CNT
+ D16(DMAC1_TC_CNT);
+ D16(DMAC1_TC_PER);
+#endif
+#ifdef DMAC1_PERIMUX
+ D16(DMAC1_PERIMUX);
+#endif
+
+#ifdef __ADSPBF561__
+ /* XXX: should rewrite the MMR map */
+# define DMA0_NEXT_DESC_PTR DMA2_0_NEXT_DESC_PTR
+# define DMA1_NEXT_DESC_PTR DMA2_1_NEXT_DESC_PTR
+# define DMA2_NEXT_DESC_PTR DMA2_2_NEXT_DESC_PTR
+# define DMA3_NEXT_DESC_PTR DMA2_3_NEXT_DESC_PTR
+# define DMA4_NEXT_DESC_PTR DMA2_4_NEXT_DESC_PTR
+# define DMA5_NEXT_DESC_PTR DMA2_5_NEXT_DESC_PTR
+# define DMA6_NEXT_DESC_PTR DMA2_6_NEXT_DESC_PTR
+# define DMA7_NEXT_DESC_PTR DMA2_7_NEXT_DESC_PTR
+# define DMA8_NEXT_DESC_PTR DMA2_8_NEXT_DESC_PTR
+# define DMA9_NEXT_DESC_PTR DMA2_9_NEXT_DESC_PTR
+# define DMA10_NEXT_DESC_PTR DMA2_10_NEXT_DESC_PTR
+# define DMA11_NEXT_DESC_PTR DMA2_11_NEXT_DESC_PTR
+# define DMA12_NEXT_DESC_PTR DMA1_0_NEXT_DESC_PTR
+# define DMA13_NEXT_DESC_PTR DMA1_1_NEXT_DESC_PTR
+# define DMA14_NEXT_DESC_PTR DMA1_2_NEXT_DESC_PTR
+# define DMA15_NEXT_DESC_PTR DMA1_3_NEXT_DESC_PTR
+# define DMA16_NEXT_DESC_PTR DMA1_4_NEXT_DESC_PTR
+# define DMA17_NEXT_DESC_PTR DMA1_5_NEXT_DESC_PTR
+# define DMA18_NEXT_DESC_PTR DMA1_6_NEXT_DESC_PTR
+# define DMA19_NEXT_DESC_PTR DMA1_7_NEXT_DESC_PTR
+# define DMA20_NEXT_DESC_PTR DMA1_8_NEXT_DESC_PTR
+# define DMA21_NEXT_DESC_PTR DMA1_9_NEXT_DESC_PTR
+# define DMA22_NEXT_DESC_PTR DMA1_10_NEXT_DESC_PTR
+# define DMA23_NEXT_DESC_PTR DMA1_11_NEXT_DESC_PTR
+#endif
+ parent = debugfs_create_dir("dma", top);
+ DMA(0);
+ DMA(1);
+ DMA(1);
+ DMA(2);
+ DMA(3);
+ DMA(4);
+ DMA(5);
+ DMA(6);
+ DMA(7);
+#ifdef DMA8_NEXT_DESC_PTR
+ DMA(8);
+ DMA(9);
+ DMA(10);
+ DMA(11);
+#endif
+#ifdef DMA12_NEXT_DESC_PTR
+ DMA(12);
+ DMA(13);
+ DMA(14);
+ DMA(15);
+ DMA(16);
+ DMA(17);
+ DMA(18);
+ DMA(19);
+#endif
+#ifdef DMA20_NEXT_DESC_PTR
+ DMA(20);
+ DMA(21);
+ DMA(22);
+ DMA(23);
+#endif
+
+ parent = debugfs_create_dir("ebiu_amc", top);
+ D32(EBIU_AMBCTL0);
+ D32(EBIU_AMBCTL1);
+ D16(EBIU_AMGCTL);
+#ifdef EBIU_MBSCTL
+ D16(EBIU_MBSCTL);
+ D32(EBIU_ARBSTAT);
+ D32(EBIU_MODE);
+ D16(EBIU_FCTL);
+#endif
+
+#ifdef EBIU_SDGCTL
+ parent = debugfs_create_dir("ebiu_sdram", top);
+# ifdef __ADSPBF561__
+ D32(EBIU_SDBCTL);
+# else
+ D16(EBIU_SDBCTL);
+# endif
+ D32(EBIU_SDGCTL);
+ D16(EBIU_SDRRC);
+ D16(EBIU_SDSTAT);
+#endif
+
+#ifdef EBIU_DDRACCT
+ parent = debugfs_create_dir("ebiu_ddr", top);
+ D32(EBIU_DDRACCT);
+ D32(EBIU_DDRARCT);
+ D32(EBIU_DDRBRC0);
+ D32(EBIU_DDRBRC1);
+ D32(EBIU_DDRBRC2);
+ D32(EBIU_DDRBRC3);
+ D32(EBIU_DDRBRC4);
+ D32(EBIU_DDRBRC5);
+ D32(EBIU_DDRBRC6);
+ D32(EBIU_DDRBRC7);
+ D32(EBIU_DDRBWC0);
+ D32(EBIU_DDRBWC1);
+ D32(EBIU_DDRBWC2);
+ D32(EBIU_DDRBWC3);
+ D32(EBIU_DDRBWC4);
+ D32(EBIU_DDRBWC5);
+ D32(EBIU_DDRBWC6);
+ D32(EBIU_DDRBWC7);
+ D32(EBIU_DDRCTL0);
+ D32(EBIU_DDRCTL1);
+ D32(EBIU_DDRCTL2);
+ D32(EBIU_DDRCTL3);
+ D32(EBIU_DDRGC0);
+ D32(EBIU_DDRGC1);
+ D32(EBIU_DDRGC2);
+ D32(EBIU_DDRGC3);
+ D32(EBIU_DDRMCCL);
+ D32(EBIU_DDRMCEN);
+ D32(EBIU_DDRQUE);
+ D32(EBIU_DDRTACT);
+ D32(EBIU_ERRADD);
+ D16(EBIU_ERRMST);
+ D16(EBIU_RSTCTL);
+#endif
+
+#ifdef EMAC_ADDRHI
+ parent = debugfs_create_dir("emac", top);
+ D32(EMAC_ADDRHI);
+ D32(EMAC_ADDRLO);
+ D32(EMAC_FLC);
+ D32(EMAC_HASHHI);
+ D32(EMAC_HASHLO);
+ D32(EMAC_MMC_CTL);
+ D32(EMAC_MMC_RIRQE);
+ D32(EMAC_MMC_RIRQS);
+ D32(EMAC_MMC_TIRQE);
+ D32(EMAC_MMC_TIRQS);
+ D32(EMAC_OPMODE);
+ D32(EMAC_RXC_ALIGN);
+ D32(EMAC_RXC_ALLFRM);
+ D32(EMAC_RXC_ALLOCT);
+ D32(EMAC_RXC_BROAD);
+ D32(EMAC_RXC_DMAOVF);
+ D32(EMAC_RXC_EQ64);
+ D32(EMAC_RXC_FCS);
+ D32(EMAC_RXC_GE1024);
+ D32(EMAC_RXC_LNERRI);
+ D32(EMAC_RXC_LNERRO);
+ D32(EMAC_RXC_LONG);
+ D32(EMAC_RXC_LT1024);
+ D32(EMAC_RXC_LT128);
+ D32(EMAC_RXC_LT256);
+ D32(EMAC_RXC_LT512);
+ D32(EMAC_RXC_MACCTL);
+ D32(EMAC_RXC_MULTI);
+ D32(EMAC_RXC_OCTET);
+ D32(EMAC_RXC_OK);
+ D32(EMAC_RXC_OPCODE);
+ D32(EMAC_RXC_PAUSE);
+ D32(EMAC_RXC_SHORT);
+ D32(EMAC_RXC_TYPED);
+ D32(EMAC_RXC_UNICST);
+ D32(EMAC_RX_IRQE);
+ D32(EMAC_RX_STAT);
+ D32(EMAC_RX_STKY);
+ D32(EMAC_STAADD);
+ D32(EMAC_STADAT);
+ D32(EMAC_SYSCTL);
+ D32(EMAC_SYSTAT);
+ D32(EMAC_TXC_1COL);
+ D32(EMAC_TXC_ABORT);
+ D32(EMAC_TXC_ALLFRM);
+ D32(EMAC_TXC_ALLOCT);
+ D32(EMAC_TXC_BROAD);
+ D32(EMAC_TXC_CRSERR);
+ D32(EMAC_TXC_DEFER);
+ D32(EMAC_TXC_DMAUND);
+ D32(EMAC_TXC_EQ64);
+ D32(EMAC_TXC_GE1024);
+ D32(EMAC_TXC_GT1COL);
+ D32(EMAC_TXC_LATECL);
+ D32(EMAC_TXC_LT1024);
+ D32(EMAC_TXC_LT128);
+ D32(EMAC_TXC_LT256);
+ D32(EMAC_TXC_LT512);
+ D32(EMAC_TXC_MACCTL);
+ D32(EMAC_TXC_MULTI);
+ D32(EMAC_TXC_OCTET);
+ D32(EMAC_TXC_OK);
+ D32(EMAC_TXC_UNICST);
+ D32(EMAC_TXC_XS_COL);
+ D32(EMAC_TXC_XS_DFR);
+ D32(EMAC_TX_IRQE);
+ D32(EMAC_TX_STAT);
+ D32(EMAC_TX_STKY);
+ D32(EMAC_VLAN1);
+ D32(EMAC_VLAN2);
+ D32(EMAC_WKUP_CTL);
+ D32(EMAC_WKUP_FFCMD);
+ D32(EMAC_WKUP_FFCRC0);
+ D32(EMAC_WKUP_FFCRC1);
+ D32(EMAC_WKUP_FFMSK0);
+ D32(EMAC_WKUP_FFMSK1);
+ D32(EMAC_WKUP_FFMSK2);
+ D32(EMAC_WKUP_FFMSK3);
+ D32(EMAC_WKUP_FFOFF);
+# ifdef EMAC_PTP_ACCR
+ D32(EMAC_PTP_ACCR);
+ D32(EMAC_PTP_ADDEND);
+ D32(EMAC_PTP_ALARMHI);
+ D32(EMAC_PTP_ALARMLO);
+ D16(EMAC_PTP_CTL);
+ D32(EMAC_PTP_FOFF);
+ D32(EMAC_PTP_FV1);
+ D32(EMAC_PTP_FV2);
+ D32(EMAC_PTP_FV3);
+ D16(EMAC_PTP_ID_OFF);
+ D32(EMAC_PTP_ID_SNAP);
+ D16(EMAC_PTP_IE);
+ D16(EMAC_PTP_ISTAT);
+ D32(EMAC_PTP_OFFSET);
+ D32(EMAC_PTP_PPS_PERIOD);
+ D32(EMAC_PTP_PPS_STARTHI);
+ D32(EMAC_PTP_PPS_STARTLO);
+ D32(EMAC_PTP_RXSNAPHI);
+ D32(EMAC_PTP_RXSNAPLO);
+ D32(EMAC_PTP_TIMEHI);
+ D32(EMAC_PTP_TIMELO);
+ D32(EMAC_PTP_TXSNAPHI);
+ D32(EMAC_PTP_TXSNAPLO);
+# endif
+#endif
+
+#if defined(EPPI0_STATUS) || defined(EPPI1_STATUS) || defined(EPPI2_STATUS)
+ parent = debugfs_create_dir("eppi", top);
+# ifdef EPPI0_STATUS
+ EPPI(0);
+# endif
+# ifdef EPPI1_STATUS
+ EPPI(1);
+# endif
+# ifdef EPPI2_STATUS
+ EPPI(2);
+# endif
+#endif
+
+ parent = debugfs_create_dir("gptimer", top);
+#ifdef TIMER_DISABLE
+ D16(TIMER_DISABLE);
+ D16(TIMER_ENABLE);
+ D32(TIMER_STATUS);
+#endif
+#ifdef TIMER_DISABLE0
+ D16(TIMER_DISABLE0);
+ D16(TIMER_ENABLE0);
+ D32(TIMER_STATUS0);
+#endif
+#ifdef TIMER_DISABLE1
+ D16(TIMER_DISABLE1);
+ D16(TIMER_ENABLE1);
+ D32(TIMER_STATUS1);
+#endif
+ /* XXX: Should convert BF561 MMR names */
+#ifdef TMRS4_DISABLE
+ D16(TMRS4_DISABLE);
+ D16(TMRS4_ENABLE);
+ D32(TMRS4_STATUS);
+ D16(TMRS8_DISABLE);
+ D16(TMRS8_ENABLE);
+ D32(TMRS8_STATUS);
+#endif
+ GPTIMER(0);
+ GPTIMER(1);
+ GPTIMER(2);
+#ifdef TIMER3_CONFIG
+ GPTIMER(3);
+ GPTIMER(4);
+ GPTIMER(5);
+ GPTIMER(6);
+ GPTIMER(7);
+#endif
+#ifdef TIMER8_CONFIG
+ GPTIMER(8);
+ GPTIMER(9);
+ GPTIMER(10);
+#endif
+#ifdef TIMER11_CONFIG
+ GPTIMER(11);
+#endif
+
+#ifdef HMDMA0_CONTROL
+ parent = debugfs_create_dir("hmdma", top);
+ HMDMA(0);
+ HMDMA(1);
+#endif
+
+#ifdef HOST_CONTROL
+ parent = debugfs_create_dir("hostdp", top);
+ D16(HOST_CONTROL);
+ D16(HOST_STATUS);
+ D16(HOST_TIMEOUT);
+#endif
+
+#ifdef IMDMA_S0_CONFIG
+ parent = debugfs_create_dir("imdma", top);
+ IMDMA(0);
+ IMDMA(1);
+#endif
+
+#ifdef KPAD_CTL
+ parent = debugfs_create_dir("keypad", top);
+ D16(KPAD_CTL);
+ D16(KPAD_PRESCALE);
+ D16(KPAD_MSEL);
+ D16(KPAD_ROWCOL);
+ D16(KPAD_STAT);
+ D16(KPAD_SOFTEVAL);
+#endif
+
+ parent = debugfs_create_dir("mdma", top);
+ MDMA(0);
+ MDMA(1);
+#ifdef MDMA_D2_CONFIG
+ MDMA(2);
+ MDMA(3);
+#endif
+
+#ifdef MXVR_CONFIG
+ parent = debugfs_create_dir("mxvr", top);
+ D16(MXVR_CONFIG);
+# ifdef MXVR_PLL_CTL_0
+ D32(MXVR_PLL_CTL_0);
+# endif
+ D32(MXVR_STATE_0);
+ D32(MXVR_STATE_1);
+ D32(MXVR_INT_STAT_0);
+ D32(MXVR_INT_STAT_1);
+ D32(MXVR_INT_EN_0);
+ D32(MXVR_INT_EN_1);
+ D16(MXVR_POSITION);
+ D16(MXVR_MAX_POSITION);
+ D16(MXVR_DELAY);
+ D16(MXVR_MAX_DELAY);
+ D32(MXVR_LADDR);
+ D16(MXVR_GADDR);
+ D32(MXVR_AADDR);
+ D32(MXVR_ALLOC_0);
+ D32(MXVR_ALLOC_1);
+ D32(MXVR_ALLOC_2);
+ D32(MXVR_ALLOC_3);
+ D32(MXVR_ALLOC_4);
+ D32(MXVR_ALLOC_5);
+ D32(MXVR_ALLOC_6);
+ D32(MXVR_ALLOC_7);
+ D32(MXVR_ALLOC_8);
+ D32(MXVR_ALLOC_9);
+ D32(MXVR_ALLOC_10);
+ D32(MXVR_ALLOC_11);
+ D32(MXVR_ALLOC_12);
+ D32(MXVR_ALLOC_13);
+ D32(MXVR_ALLOC_14);
+ D32(MXVR_SYNC_LCHAN_0);
+ D32(MXVR_SYNC_LCHAN_1);
+ D32(MXVR_SYNC_LCHAN_2);
+ D32(MXVR_SYNC_LCHAN_3);
+ D32(MXVR_SYNC_LCHAN_4);
+ D32(MXVR_SYNC_LCHAN_5);
+ D32(MXVR_SYNC_LCHAN_6);
+ D32(MXVR_SYNC_LCHAN_7);
+ D32(MXVR_DMA0_CONFIG);
+ D32(MXVR_DMA0_START_ADDR);
+ D16(MXVR_DMA0_COUNT);
+ D32(MXVR_DMA0_CURR_ADDR);
+ D16(MXVR_DMA0_CURR_COUNT);
+ D32(MXVR_DMA1_CONFIG);
+ D32(MXVR_DMA1_START_ADDR);
+ D16(MXVR_DMA1_COUNT);
+ D32(MXVR_DMA1_CURR_ADDR);
+ D16(MXVR_DMA1_CURR_COUNT);
+ D32(MXVR_DMA2_CONFIG);
+ D32(MXVR_DMA2_START_ADDR);
+ D16(MXVR_DMA2_COUNT);
+ D32(MXVR_DMA2_CURR_ADDR);
+ D16(MXVR_DMA2_CURR_COUNT);
+ D32(MXVR_DMA3_CONFIG);
+ D32(MXVR_DMA3_START_ADDR);
+ D16(MXVR_DMA3_COUNT);
+ D32(MXVR_DMA3_CURR_ADDR);
+ D16(MXVR_DMA3_CURR_COUNT);
+ D32(MXVR_DMA4_CONFIG);
+ D32(MXVR_DMA4_START_ADDR);
+ D16(MXVR_DMA4_COUNT);
+ D32(MXVR_DMA4_CURR_ADDR);
+ D16(MXVR_DMA4_CURR_COUNT);
+ D32(MXVR_DMA5_CONFIG);
+ D32(MXVR_DMA5_START_ADDR);
+ D16(MXVR_DMA5_COUNT);
+ D32(MXVR_DMA5_CURR_ADDR);
+ D16(MXVR_DMA5_CURR_COUNT);
+ D32(MXVR_DMA6_CONFIG);
+ D32(MXVR_DMA6_START_ADDR);
+ D16(MXVR_DMA6_COUNT);
+ D32(MXVR_DMA6_CURR_ADDR);
+ D16(MXVR_DMA6_CURR_COUNT);
+ D32(MXVR_DMA7_CONFIG);
+ D32(MXVR_DMA7_START_ADDR);
+ D16(MXVR_DMA7_COUNT);
+ D32(MXVR_DMA7_CURR_ADDR);
+ D16(MXVR_DMA7_CURR_COUNT);
+ D16(MXVR_AP_CTL);
+ D32(MXVR_APRB_START_ADDR);
+ D32(MXVR_APRB_CURR_ADDR);
+ D32(MXVR_APTB_START_ADDR);
+ D32(MXVR_APTB_CURR_ADDR);
+ D32(MXVR_CM_CTL);
+ D32(MXVR_CMRB_START_ADDR);
+ D32(MXVR_CMRB_CURR_ADDR);
+ D32(MXVR_CMTB_START_ADDR);
+ D32(MXVR_CMTB_CURR_ADDR);
+ D32(MXVR_RRDB_START_ADDR);
+ D32(MXVR_RRDB_CURR_ADDR);
+ D32(MXVR_PAT_DATA_0);
+ D32(MXVR_PAT_EN_0);
+ D32(MXVR_PAT_DATA_1);
+ D32(MXVR_PAT_EN_1);
+ D16(MXVR_FRAME_CNT_0);
+ D16(MXVR_FRAME_CNT_1);
+ D32(MXVR_ROUTING_0);
+ D32(MXVR_ROUTING_1);
+ D32(MXVR_ROUTING_2);
+ D32(MXVR_ROUTING_3);
+ D32(MXVR_ROUTING_4);
+ D32(MXVR_ROUTING_5);
+ D32(MXVR_ROUTING_6);
+ D32(MXVR_ROUTING_7);
+ D32(MXVR_ROUTING_8);
+ D32(MXVR_ROUTING_9);
+ D32(MXVR_ROUTING_10);
+ D32(MXVR_ROUTING_11);
+ D32(MXVR_ROUTING_12);
+ D32(MXVR_ROUTING_13);
+ D32(MXVR_ROUTING_14);
+# ifdef MXVR_PLL_CTL_1
+ D32(MXVR_PLL_CTL_1);
+# endif
+ D16(MXVR_BLOCK_CNT);
+# ifdef MXVR_CLK_CTL
+ D32(MXVR_CLK_CTL);
+# endif
+# ifdef MXVR_CDRPLL_CTL
+ D32(MXVR_CDRPLL_CTL);
+# endif
+# ifdef MXVR_FMPLL_CTL
+ D32(MXVR_FMPLL_CTL);
+# endif
+# ifdef MXVR_PIN_CTL
+ D16(MXVR_PIN_CTL);
+# endif
+# ifdef MXVR_SCLK_CNT
+ D16(MXVR_SCLK_CNT);
+# endif
+#endif
+
+#ifdef NFC_ADDR
+ parent = debugfs_create_dir("nfc", top);
+ D_WO(NFC_ADDR, 16);
+ D_WO(NFC_CMD, 16);
+ D_RO(NFC_COUNT, 16);
+ D16(NFC_CTL);
+ D_WO(NFC_DATA_RD, 16);
+ D_WO(NFC_DATA_WR, 16);
+ D_RO(NFC_ECC0, 16);
+ D_RO(NFC_ECC1, 16);
+ D_RO(NFC_ECC2, 16);
+ D_RO(NFC_ECC3, 16);
+ D16(NFC_IRQMASK);
+ D16(NFC_IRQSTAT);
+ D_WO(NFC_PGCTL, 16);
+ D_RO(NFC_READ, 16);
+ D16(NFC_RST);
+ D_RO(NFC_STAT, 16);
+#endif
+
+#ifdef OTP_CONTROL
+ parent = debugfs_create_dir("otp", top);
+ D16(OTP_CONTROL);
+ D16(OTP_BEN);
+ D16(OTP_STATUS);
+ D32(OTP_TIMING);
+ D32(OTP_DATA0);
+ D32(OTP_DATA1);
+ D32(OTP_DATA2);
+ D32(OTP_DATA3);
+#endif
+
+#ifdef PIXC_CTL
+ parent = debugfs_create_dir("pixc", top);
+ D16(PIXC_CTL);
+ D16(PIXC_PPL);
+ D16(PIXC_LPF);
+ D16(PIXC_AHSTART);
+ D16(PIXC_AHEND);
+ D16(PIXC_AVSTART);
+ D16(PIXC_AVEND);
+ D16(PIXC_ATRANSP);
+ D16(PIXC_BHSTART);
+ D16(PIXC_BHEND);
+ D16(PIXC_BVSTART);
+ D16(PIXC_BVEND);
+ D16(PIXC_BTRANSP);
+ D16(PIXC_INTRSTAT);
+ D32(PIXC_RYCON);
+ D32(PIXC_GUCON);
+ D32(PIXC_BVCON);
+ D32(PIXC_CCBIAS);
+ D32(PIXC_TC);
+#endif
+
+ parent = debugfs_create_dir("pll", top);
+ D16(PLL_CTL);
+ D16(PLL_DIV);
+ D16(PLL_LOCKCNT);
+ D16(PLL_STAT);
+ D16(VR_CTL);
+ D32(CHIPID); /* it's part of this hardware block */
+
+#if defined(PPI_STATUS) || defined(PPI0_STATUS) || defined(PPI1_STATUS)
+ parent = debugfs_create_dir("ppi", top);
+# ifdef PPI_STATUS
+ bfin_debug_mmrs_ppi(parent, PPI_STATUS, -1);
+# endif
+# ifdef PPI0_STATUS
+ PPI(0);
+# endif
+# ifdef PPI1_STATUS
+ PPI(1);
+# endif
+#endif
+
+#ifdef PWM_CTRL
+ parent = debugfs_create_dir("pwm", top);
+ D16(PWM_CTRL);
+ D16(PWM_STAT);
+ D16(PWM_TM);
+ D16(PWM_DT);
+ D16(PWM_GATE);
+ D16(PWM_CHA);
+ D16(PWM_CHB);
+ D16(PWM_CHC);
+ D16(PWM_SEG);
+ D16(PWM_SYNCWT);
+ D16(PWM_CHAL);
+ D16(PWM_CHBL);
+ D16(PWM_CHCL);
+ D16(PWM_LSI);
+ D16(PWM_STAT2);
+#endif
+
+#ifdef RSI_CONFIG
+ parent = debugfs_create_dir("rsi", top);
+ D32(RSI_ARGUMENT);
+ D16(RSI_CEATA_CONTROL);
+ D16(RSI_CLK_CONTROL);
+ D16(RSI_COMMAND);
+ D16(RSI_CONFIG);
+ D16(RSI_DATA_CNT);
+ D16(RSI_DATA_CONTROL);
+ D16(RSI_DATA_LGTH);
+ D32(RSI_DATA_TIMER);
+ D16(RSI_EMASK);
+ D16(RSI_ESTAT);
+ D32(RSI_FIFO);
+ D16(RSI_FIFO_CNT);
+ D32(RSI_MASK0);
+ D32(RSI_MASK1);
+ D16(RSI_PID0);
+ D16(RSI_PID1);
+ D16(RSI_PID2);
+ D16(RSI_PID3);
+ D16(RSI_PWR_CONTROL);
+ D16(RSI_RD_WAIT_EN);
+ D32(RSI_RESPONSE0);
+ D32(RSI_RESPONSE1);
+ D32(RSI_RESPONSE2);
+ D32(RSI_RESPONSE3);
+ D16(RSI_RESP_CMD);
+ D32(RSI_STATUS);
+ D_WO(RSI_STATUSCL, 16);
+#endif
+
+#ifdef RTC_ALARM
+ parent = debugfs_create_dir("rtc", top);
+ D32(RTC_ALARM);
+ D16(RTC_ICTL);
+ D16(RTC_ISTAT);
+ D16(RTC_PREN);
+ D32(RTC_STAT);
+ D16(RTC_SWCNT);
+#endif
+
+#ifdef SDH_CFG
+ parent = debugfs_create_dir("sdh", top);
+ D32(SDH_ARGUMENT);
+ D16(SDH_CFG);
+ D16(SDH_CLK_CTL);
+ D16(SDH_COMMAND);
+ D_RO(SDH_DATA_CNT, 16);
+ D16(SDH_DATA_CTL);
+ D16(SDH_DATA_LGTH);
+ D32(SDH_DATA_TIMER);
+ D16(SDH_E_MASK);
+ D16(SDH_E_STATUS);
+ D32(SDH_FIFO);
+ D_RO(SDH_FIFO_CNT, 16);
+ D32(SDH_MASK0);
+ D32(SDH_MASK1);
+ D_RO(SDH_PID0, 16);
+ D_RO(SDH_PID1, 16);
+ D_RO(SDH_PID2, 16);
+ D_RO(SDH_PID3, 16);
+ D_RO(SDH_PID4, 16);
+ D_RO(SDH_PID5, 16);
+ D_RO(SDH_PID6, 16);
+ D_RO(SDH_PID7, 16);
+ D16(SDH_PWR_CTL);
+ D16(SDH_RD_WAIT_EN);
+ D_RO(SDH_RESPONSE0, 32);
+ D_RO(SDH_RESPONSE1, 32);
+ D_RO(SDH_RESPONSE2, 32);
+ D_RO(SDH_RESPONSE3, 32);
+ D_RO(SDH_RESP_CMD, 16);
+ D_RO(SDH_STATUS, 32);
+ D_WO(SDH_STATUS_CLR, 16);
+#endif
+
+#ifdef SECURE_CONTROL
+ parent = debugfs_create_dir("security", top);
+ D16(SECURE_CONTROL);
+ D16(SECURE_STATUS);
+ D32(SECURE_SYSSWT);
+#endif
+
+ parent = debugfs_create_dir("sic", top);
+ D16(SWRST);
+ D16(SYSCR);
+ D16(SIC_RVECT);
+ D32(SIC_IAR0);
+ D32(SIC_IAR1);
+ D32(SIC_IAR2);
+#ifdef SIC_IAR3
+ D32(SIC_IAR3);
+#endif
+#ifdef SIC_IAR4
+ D32(SIC_IAR4);
+ D32(SIC_IAR5);
+ D32(SIC_IAR6);
+#endif
+#ifdef SIC_IAR7
+ D32(SIC_IAR7);
+#endif
+#ifdef SIC_IAR8
+ D32(SIC_IAR8);
+ D32(SIC_IAR9);
+ D32(SIC_IAR10);
+ D32(SIC_IAR11);
+#endif
+#ifdef SIC_IMASK
+ D32(SIC_IMASK);
+ D32(SIC_ISR);
+ D32(SIC_IWR);
+#endif
+#ifdef SIC_IMASK0
+ D32(SIC_IMASK0);
+ D32(SIC_IMASK1);
+ D32(SIC_ISR0);
+ D32(SIC_ISR1);
+ D32(SIC_IWR0);
+ D32(SIC_IWR1);
+#endif
+#ifdef SIC_IMASK2
+ D32(SIC_IMASK2);
+ D32(SIC_ISR2);
+ D32(SIC_IWR2);
+#endif
+#ifdef SICB_RVECT
+ D16(SICB_SWRST);
+ D16(SICB_SYSCR);
+ D16(SICB_RVECT);
+ D32(SICB_IAR0);
+ D32(SICB_IAR1);
+ D32(SICB_IAR2);
+ D32(SICB_IAR3);
+ D32(SICB_IAR4);
+ D32(SICB_IAR5);
+ D32(SICB_IAR6);
+ D32(SICB_IAR7);
+ D32(SICB_IMASK0);
+ D32(SICB_IMASK1);
+ D32(SICB_ISR0);
+ D32(SICB_ISR1);
+ D32(SICB_IWR0);
+ D32(SICB_IWR1);
+#endif
+
+ parent = debugfs_create_dir("spi", top);
+#ifdef SPI0_REGBASE
+ SPI(0);
+#endif
+#ifdef SPI1_REGBASE
+ SPI(1);
+#endif
+#ifdef SPI2_REGBASE
+ SPI(2);
+#endif
+
+ parent = debugfs_create_dir("sport", top);
+#ifdef SPORT0_STAT
+ SPORT(0);
+#endif
+#ifdef SPORT1_STAT
+ SPORT(1);
+#endif
+#ifdef SPORT2_STAT
+ SPORT(2);
+#endif
+#ifdef SPORT3_STAT
+ SPORT(3);
+#endif
+
+#if defined(TWI_CLKDIV) || defined(TWI0_CLKDIV) || defined(TWI1_CLKDIV)
+ parent = debugfs_create_dir("twi", top);
+# ifdef TWI_CLKDIV
+ bfin_debug_mmrs_twi(parent, TWI_CLKDIV, -1);
+# endif
+# ifdef TWI0_CLKDIV
+ TWI(0);
+# endif
+# ifdef TWI1_CLKDIV
+ TWI(1);
+# endif
+#endif
+
+ parent = debugfs_create_dir("uart", top);
+#ifdef BFIN_UART_DLL
+ bfin_debug_mmrs_uart(parent, BFIN_UART_DLL, -1);
+#endif
+#ifdef UART0_DLL
+ UART(0);
+#endif
+#ifdef UART1_DLL
+ UART(1);
+#endif
+#ifdef UART2_DLL
+ UART(2);
+#endif
+#ifdef UART3_DLL
+ UART(3);
+#endif
+
+#ifdef USB_FADDR
+ parent = debugfs_create_dir("usb", top);
+ D16(USB_FADDR);
+ D16(USB_POWER);
+ D16(USB_INTRTX);
+ D16(USB_INTRRX);
+ D16(USB_INTRTXE);
+ D16(USB_INTRRXE);
+ D16(USB_INTRUSB);
+ D16(USB_INTRUSBE);
+ D16(USB_FRAME);
+ D16(USB_INDEX);
+ D16(USB_TESTMODE);
+ D16(USB_GLOBINTR);
+ D16(USB_GLOBAL_CTL);
+ D16(USB_TX_MAX_PACKET);
+ D16(USB_CSR0);
+ D16(USB_TXCSR);
+ D16(USB_RX_MAX_PACKET);
+ D16(USB_RXCSR);
+ D16(USB_COUNT0);
+ D16(USB_RXCOUNT);
+ D16(USB_TXTYPE);
+ D16(USB_NAKLIMIT0);
+ D16(USB_TXINTERVAL);
+ D16(USB_RXTYPE);
+ D16(USB_RXINTERVAL);
+ D16(USB_TXCOUNT);
+ D16(USB_EP0_FIFO);
+ D16(USB_EP1_FIFO);
+ D16(USB_EP2_FIFO);
+ D16(USB_EP3_FIFO);
+ D16(USB_EP4_FIFO);
+ D16(USB_EP5_FIFO);
+ D16(USB_EP6_FIFO);
+ D16(USB_EP7_FIFO);
+ D16(USB_OTG_DEV_CTL);
+ D16(USB_OTG_VBUS_IRQ);
+ D16(USB_OTG_VBUS_MASK);
+ D16(USB_LINKINFO);
+ D16(USB_VPLEN);
+ D16(USB_HS_EOF1);
+ D16(USB_FS_EOF1);
+ D16(USB_LS_EOF1);
+ D16(USB_APHY_CNTRL);
+ D16(USB_APHY_CALIB);
+ D16(USB_APHY_CNTRL2);
+ D16(USB_PHY_TEST);
+ D16(USB_PLLOSC_CTRL);
+ D16(USB_SRP_CLKDIV);
+ D16(USB_EP_NI0_TXMAXP);
+ D16(USB_EP_NI0_TXCSR);
+ D16(USB_EP_NI0_RXMAXP);
+ D16(USB_EP_NI0_RXCSR);
+ D16(USB_EP_NI0_RXCOUNT);
+ D16(USB_EP_NI0_TXTYPE);
+ D16(USB_EP_NI0_TXINTERVAL);
+ D16(USB_EP_NI0_RXTYPE);
+ D16(USB_EP_NI0_RXINTERVAL);
+ D16(USB_EP_NI0_TXCOUNT);
+ D16(USB_EP_NI1_TXMAXP);
+ D16(USB_EP_NI1_TXCSR);
+ D16(USB_EP_NI1_RXMAXP);
+ D16(USB_EP_NI1_RXCSR);
+ D16(USB_EP_NI1_RXCOUNT);
+ D16(USB_EP_NI1_TXTYPE);
+ D16(USB_EP_NI1_TXINTERVAL);
+ D16(USB_EP_NI1_RXTYPE);
+ D16(USB_EP_NI1_RXINTERVAL);
+ D16(USB_EP_NI1_TXCOUNT);
+ D16(USB_EP_NI2_TXMAXP);
+ D16(USB_EP_NI2_TXCSR);
+ D16(USB_EP_NI2_RXMAXP);
+ D16(USB_EP_NI2_RXCSR);
+ D16(USB_EP_NI2_RXCOUNT);
+ D16(USB_EP_NI2_TXTYPE);
+ D16(USB_EP_NI2_TXINTERVAL);
+ D16(USB_EP_NI2_RXTYPE);
+ D16(USB_EP_NI2_RXINTERVAL);
+ D16(USB_EP_NI2_TXCOUNT);
+ D16(USB_EP_NI3_TXMAXP);
+ D16(USB_EP_NI3_TXCSR);
+ D16(USB_EP_NI3_RXMAXP);
+ D16(USB_EP_NI3_RXCSR);
+ D16(USB_EP_NI3_RXCOUNT);
+ D16(USB_EP_NI3_TXTYPE);
+ D16(USB_EP_NI3_TXINTERVAL);
+ D16(USB_EP_NI3_RXTYPE);
+ D16(USB_EP_NI3_RXINTERVAL);
+ D16(USB_EP_NI3_TXCOUNT);
+ D16(USB_EP_NI4_TXMAXP);
+ D16(USB_EP_NI4_TXCSR);
+ D16(USB_EP_NI4_RXMAXP);
+ D16(USB_EP_NI4_RXCSR);
+ D16(USB_EP_NI4_RXCOUNT);
+ D16(USB_EP_NI4_TXTYPE);
+ D16(USB_EP_NI4_TXINTERVAL);
+ D16(USB_EP_NI4_RXTYPE);
+ D16(USB_EP_NI4_RXINTERVAL);
+ D16(USB_EP_NI4_TXCOUNT);
+ D16(USB_EP_NI5_TXMAXP);
+ D16(USB_EP_NI5_TXCSR);
+ D16(USB_EP_NI5_RXMAXP);
+ D16(USB_EP_NI5_RXCSR);
+ D16(USB_EP_NI5_RXCOUNT);
+ D16(USB_EP_NI5_TXTYPE);
+ D16(USB_EP_NI5_TXINTERVAL);
+ D16(USB_EP_NI5_RXTYPE);
+ D16(USB_EP_NI5_RXINTERVAL);
+ D16(USB_EP_NI5_TXCOUNT);
+ D16(USB_EP_NI6_TXMAXP);
+ D16(USB_EP_NI6_TXCSR);
+ D16(USB_EP_NI6_RXMAXP);
+ D16(USB_EP_NI6_RXCSR);
+ D16(USB_EP_NI6_RXCOUNT);
+ D16(USB_EP_NI6_TXTYPE);
+ D16(USB_EP_NI6_TXINTERVAL);
+ D16(USB_EP_NI6_RXTYPE);
+ D16(USB_EP_NI6_RXINTERVAL);
+ D16(USB_EP_NI6_TXCOUNT);
+ D16(USB_EP_NI7_TXMAXP);
+ D16(USB_EP_NI7_TXCSR);
+ D16(USB_EP_NI7_RXMAXP);
+ D16(USB_EP_NI7_RXCSR);
+ D16(USB_EP_NI7_RXCOUNT);
+ D16(USB_EP_NI7_TXTYPE);
+ D16(USB_EP_NI7_TXINTERVAL);
+ D16(USB_EP_NI7_RXTYPE);
+ D16(USB_EP_NI7_RXINTERVAL);
+ D16(USB_EP_NI7_TXCOUNT);
+ D16(USB_DMA_INTERRUPT);
+ D16(USB_DMA0CONTROL);
+ D16(USB_DMA0ADDRLOW);
+ D16(USB_DMA0ADDRHIGH);
+ D16(USB_DMA0COUNTLOW);
+ D16(USB_DMA0COUNTHIGH);
+ D16(USB_DMA1CONTROL);
+ D16(USB_DMA1ADDRLOW);
+ D16(USB_DMA1ADDRHIGH);
+ D16(USB_DMA1COUNTLOW);
+ D16(USB_DMA1COUNTHIGH);
+ D16(USB_DMA2CONTROL);
+ D16(USB_DMA2ADDRLOW);
+ D16(USB_DMA2ADDRHIGH);
+ D16(USB_DMA2COUNTLOW);
+ D16(USB_DMA2COUNTHIGH);
+ D16(USB_DMA3CONTROL);
+ D16(USB_DMA3ADDRLOW);
+ D16(USB_DMA3ADDRHIGH);
+ D16(USB_DMA3COUNTLOW);
+ D16(USB_DMA3COUNTHIGH);
+ D16(USB_DMA4CONTROL);
+ D16(USB_DMA4ADDRLOW);
+ D16(USB_DMA4ADDRHIGH);
+ D16(USB_DMA4COUNTLOW);
+ D16(USB_DMA4COUNTHIGH);
+ D16(USB_DMA5CONTROL);
+ D16(USB_DMA5ADDRLOW);
+ D16(USB_DMA5ADDRHIGH);
+ D16(USB_DMA5COUNTLOW);
+ D16(USB_DMA5COUNTHIGH);
+ D16(USB_DMA6CONTROL);
+ D16(USB_DMA6ADDRLOW);
+ D16(USB_DMA6ADDRHIGH);
+ D16(USB_DMA6COUNTLOW);
+ D16(USB_DMA6COUNTHIGH);
+ D16(USB_DMA7CONTROL);
+ D16(USB_DMA7ADDRLOW);
+ D16(USB_DMA7ADDRHIGH);
+ D16(USB_DMA7COUNTLOW);
+ D16(USB_DMA7COUNTHIGH);
+#endif
+
+#ifdef WDOG_CNT
+ parent = debugfs_create_dir("watchdog", top);
+ D32(WDOG_CNT);
+ D16(WDOG_CTL);
+ D32(WDOG_STAT);
+#endif
+#ifdef WDOGA_CNT
+ parent = debugfs_create_dir("watchdog", top);
+ D32(WDOGA_CNT);
+ D16(WDOGA_CTL);
+ D32(WDOGA_STAT);
+ D32(WDOGB_CNT);
+ D16(WDOGB_CTL);
+ D32(WDOGB_STAT);
+#endif
+
+ /* BF533 glue */
+#ifdef FIO_FLAG_D
+#define PORTFIO FIO_FLAG_D
+#endif
+ /* BF561 glue */
+#ifdef FIO0_FLAG_D
+#define PORTFIO FIO0_FLAG_D
+#endif
+#ifdef FIO1_FLAG_D
+#define PORTGIO FIO1_FLAG_D
+#endif
+#ifdef FIO2_FLAG_D
+#define PORTHIO FIO2_FLAG_D
+#endif
+ parent = debugfs_create_dir("port", top);
+#ifdef PORTFIO
+ PORT(PORTFIO, 'F');
+#endif
+#ifdef PORTGIO
+ PORT(PORTGIO, 'G');
+#endif
+#ifdef PORTHIO
+ PORT(PORTHIO, 'H');
+#endif
+
+#ifdef __ADSPBF51x__
+ D16(PORTF_FER);
+ D16(PORTF_DRIVE);
+ D16(PORTF_HYSTERESIS);
+ D16(PORTF_MUX);
+
+ D16(PORTG_FER);
+ D16(PORTG_DRIVE);
+ D16(PORTG_HYSTERESIS);
+ D16(PORTG_MUX);
+
+ D16(PORTH_FER);
+ D16(PORTH_DRIVE);
+ D16(PORTH_HYSTERESIS);
+ D16(PORTH_MUX);
+
+ D16(MISCPORT_DRIVE);
+ D16(MISCPORT_HYSTERESIS);
+#endif /* BF51x */
+
+#ifdef __ADSPBF52x__
+ D16(PORTF_FER);
+ D16(PORTF_DRIVE);
+ D16(PORTF_HYSTERESIS);
+ D16(PORTF_MUX);
+ D16(PORTF_SLEW);
+
+ D16(PORTG_FER);
+ D16(PORTG_DRIVE);
+ D16(PORTG_HYSTERESIS);
+ D16(PORTG_MUX);
+ D16(PORTG_SLEW);
+
+ D16(PORTH_FER);
+ D16(PORTH_DRIVE);
+ D16(PORTH_HYSTERESIS);
+ D16(PORTH_MUX);
+ D16(PORTH_SLEW);
+
+ D16(MISCPORT_DRIVE);
+ D16(MISCPORT_HYSTERESIS);
+ D16(MISCPORT_SLEW);
+#endif /* BF52x */
+
+#ifdef BF537_FAMILY
+ D16(PORTF_FER);
+ D16(PORTG_FER);
+ D16(PORTH_FER);
+ D16(PORT_MUX);
+#endif /* BF534 BF536 BF537 */
+
+#ifdef BF538_FAMILY
+ D16(PORTCIO_FER);
+ D16(PORTCIO);
+ D16(PORTCIO_CLEAR);
+ D16(PORTCIO_SET);
+ D16(PORTCIO_TOGGLE);
+ D16(PORTCIO_DIR);
+ D16(PORTCIO_INEN);
+
+ D16(PORTDIO);
+ D16(PORTDIO_CLEAR);
+ D16(PORTDIO_DIR);
+ D16(PORTDIO_FER);
+ D16(PORTDIO_INEN);
+ D16(PORTDIO_SET);
+ D16(PORTDIO_TOGGLE);
+
+ D16(PORTEIO);
+ D16(PORTEIO_CLEAR);
+ D16(PORTEIO_DIR);
+ D16(PORTEIO_FER);
+ D16(PORTEIO_INEN);
+ D16(PORTEIO_SET);
+ D16(PORTEIO_TOGGLE);
+#endif /* BF538 BF539 */
+
+#ifdef __ADSPBF54x__
+ {
+ int num;
+ unsigned long base;
+ char *_buf, buf[32];
+
+ base = PORTA_FER;
+ for (num = 0; num < 10; ++num) {
+ PORT(base, num);
+ base += sizeof(struct bfin_gpio_regs);
+ }
+
+#define __PINT(uname, lname) __REGS(pint, #uname, lname)
+ parent = debugfs_create_dir("pint", top);
+ base = PINT0_MASK_SET;
+ for (num = 0; num < 4; ++num) {
+ _buf = REGS_STR_PFX(buf, PINT, num);
+ __PINT(MASK_SET, mask_set);
+ __PINT(MASK_CLEAR, mask_clear);
+ __PINT(IRQ, irq);
+ __PINT(ASSIGN, assign);
+ __PINT(EDGE_SET, edge_set);
+ __PINT(EDGE_CLEAR, edge_clear);
+ __PINT(INVERT_SET, invert_set);
+ __PINT(INVERT_CLEAR, invert_clear);
+ __PINT(PINSTATE, pinstate);
+ __PINT(LATCH, latch);
+ base += sizeof(struct bfin_pint_regs);
+ }
+
+ }
+#endif /* BF54x */
+
+ debug_mmrs_dentry = top;
+
+ return 0;
+}
+module_init(bfin_debug_mmrs_init);
+
+static void __exit bfin_debug_mmrs_exit(void)
+{
+ debugfs_remove_recursive(debug_mmrs_dentry);
+}
+module_exit(bfin_debug_mmrs_exit);
+
+MODULE_LICENSE("GPL");
diff --git a/arch/blackfin/kernel/ipipe.c b/arch/blackfin/kernel/ipipe.c
index f37019c..486426f 100644
--- a/arch/blackfin/kernel/ipipe.c
+++ b/arch/blackfin/kernel/ipipe.c
@@ -33,6 +33,7 @@
#include <linux/io.h>
#include <asm/system.h>
#include <asm/atomic.h>
+#include <asm/irq_handler.h>
DEFINE_PER_CPU(struct pt_regs, __ipipe_tick_regs);
diff --git a/arch/blackfin/kernel/irqchip.c b/arch/blackfin/kernel/irqchip.c
index 1696d34..ff3d747 100644
--- a/arch/blackfin/kernel/irqchip.c
+++ b/arch/blackfin/kernel/irqchip.c
@@ -11,6 +11,7 @@
#include <linux/kallsyms.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
+#include <asm/irq_handler.h>
#include <asm/trace.h>
#include <asm/pda.h>
diff --git a/arch/blackfin/kernel/nmi.c b/arch/blackfin/kernel/nmi.c
index 401eb1d..679d0db 100644
--- a/arch/blackfin/kernel/nmi.c
+++ b/arch/blackfin/kernel/nmi.c
@@ -145,16 +145,16 @@
{
unsigned int this_cpu = smp_processor_id();
unsigned int cpu;
+ cpumask_t mask;
- cpumask_t mask = cpu_online_map;
-
+ cpumask_copy(&mask, cpu_online_mask);
if (!atomic_read(&nmi_touched[this_cpu]))
return 0;
atomic_set(&nmi_touched[this_cpu], 0);
- cpu_clear(this_cpu, mask);
- for_each_cpu_mask(cpu, mask) {
+ cpumask_clear_cpu(this_cpu, &mask);
+ for_each_cpu(cpu, &mask) {
invalidate_dcache_range((unsigned long)(&nmi_touched[cpu]),
(unsigned long)(&nmi_touched[cpu]));
if (!atomic_read(&nmi_touched[cpu]))
diff --git a/arch/blackfin/kernel/perf_event.c b/arch/blackfin/kernel/perf_event.c
new file mode 100644
index 0000000..04300f2
--- /dev/null
+++ b/arch/blackfin/kernel/perf_event.c
@@ -0,0 +1,498 @@
+/*
+ * Blackfin performance counters
+ *
+ * Copyright 2011 Analog Devices Inc.
+ *
+ * Ripped from SuperH version:
+ *
+ * Copyright (C) 2009 Paul Mundt
+ *
+ * Heavily based on the x86 and PowerPC implementations.
+ *
+ * x86:
+ * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
+ * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
+ * Copyright (C) 2009 Jaswinder Singh Rajput
+ * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
+ * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
+ * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
+ *
+ * ppc:
+ * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/perf_event.h>
+#include <asm/bfin_pfmon.h>
+
+/*
+ * We have two counters, and each counter can support an event type.
+ * The 'o' is PFCNTx=1 and 's' is PFCNTx=0
+ *
+ * 0x04 o pc invariant branches
+ * 0x06 o mispredicted branches
+ * 0x09 o predicted branches taken
+ * 0x0B o EXCPT insn
+ * 0x0C o CSYNC/SSYNC insn
+ * 0x0D o Insns committed
+ * 0x0E o Interrupts taken
+ * 0x0F o Misaligned address exceptions
+ * 0x80 o Code memory fetches stalled due to DMA
+ * 0x83 o 64bit insn fetches delivered
+ * 0x9A o data cache fills (bank a)
+ * 0x9B o data cache fills (bank b)
+ * 0x9C o data cache lines evicted (bank a)
+ * 0x9D o data cache lines evicted (bank b)
+ * 0x9E o data cache high priority fills
+ * 0x9F o data cache low priority fills
+ * 0x00 s loop 0 iterations
+ * 0x01 s loop 1 iterations
+ * 0x0A s CSYNC/SSYNC stalls
+ * 0x10 s DAG read/after write hazards
+ * 0x13 s RAW data hazards
+ * 0x81 s code TAG stalls
+ * 0x82 s code fill stalls
+ * 0x90 s processor to memory stalls
+ * 0x91 s data memory stalls not hidden by 0x90
+ * 0x92 s data store buffer full stalls
+ * 0x93 s data memory write buffer full stalls due to high->low priority
+ * 0x95 s data memory fill buffer stalls
+ * 0x96 s data TAG collision stalls
+ * 0x97 s data collision stalls
+ * 0x98 s data stalls
+ * 0x99 s data stalls sent to processor
+ */
+
+static const int event_map[] = {
+ /* use CYCLES cpu register */
+ [PERF_COUNT_HW_CPU_CYCLES] = -1,
+ [PERF_COUNT_HW_INSTRUCTIONS] = 0x0D,
+ [PERF_COUNT_HW_CACHE_REFERENCES] = -1,
+ [PERF_COUNT_HW_CACHE_MISSES] = 0x83,
+ [PERF_COUNT_HW_BRANCH_INSTRUCTIONS] = 0x09,
+ [PERF_COUNT_HW_BRANCH_MISSES] = 0x06,
+ [PERF_COUNT_HW_BUS_CYCLES] = -1,
+};
+
+#define C(x) PERF_COUNT_HW_CACHE_##x
+
+static const int cache_events[PERF_COUNT_HW_CACHE_MAX]
+ [PERF_COUNT_HW_CACHE_OP_MAX]
+ [PERF_COUNT_HW_CACHE_RESULT_MAX] =
+{
+ [C(L1D)] = { /* Data bank A */
+ [C(OP_READ)] = {
+ [C(RESULT_ACCESS)] = 0,
+ [C(RESULT_MISS) ] = 0x9A,
+ },
+ [C(OP_WRITE)] = {
+ [C(RESULT_ACCESS)] = 0,
+ [C(RESULT_MISS) ] = 0,
+ },
+ [C(OP_PREFETCH)] = {
+ [C(RESULT_ACCESS)] = 0,
+ [C(RESULT_MISS) ] = 0,
+ },
+ },
+
+ [C(L1I)] = {
+ [C(OP_READ)] = {
+ [C(RESULT_ACCESS)] = 0,
+ [C(RESULT_MISS) ] = 0x83,
+ },
+ [C(OP_WRITE)] = {
+ [C(RESULT_ACCESS)] = -1,
+ [C(RESULT_MISS) ] = -1,
+ },
+ [C(OP_PREFETCH)] = {
+ [C(RESULT_ACCESS)] = 0,
+ [C(RESULT_MISS) ] = 0,
+ },
+ },
+
+ [C(LL)] = {
+ [C(OP_READ)] = {
+ [C(RESULT_ACCESS)] = -1,
+ [C(RESULT_MISS) ] = -1,
+ },
+ [C(OP_WRITE)] = {
+ [C(RESULT_ACCESS)] = -1,
+ [C(RESULT_MISS) ] = -1,
+ },
+ [C(OP_PREFETCH)] = {
+ [C(RESULT_ACCESS)] = -1,
+ [C(RESULT_MISS) ] = -1,
+ },
+ },
+
+ [C(DTLB)] = {
+ [C(OP_READ)] = {
+ [C(RESULT_ACCESS)] = -1,
+ [C(RESULT_MISS) ] = -1,
+ },
+ [C(OP_WRITE)] = {
+ [C(RESULT_ACCESS)] = -1,
+ [C(RESULT_MISS) ] = -1,
+ },
+ [C(OP_PREFETCH)] = {
+ [C(RESULT_ACCESS)] = -1,
+ [C(RESULT_MISS) ] = -1,
+ },
+ },
+
+ [C(ITLB)] = {
+ [C(OP_READ)] = {
+ [C(RESULT_ACCESS)] = -1,
+ [C(RESULT_MISS) ] = -1,
+ },
+ [C(OP_WRITE)] = {
+ [C(RESULT_ACCESS)] = -1,
+ [C(RESULT_MISS) ] = -1,
+ },
+ [C(OP_PREFETCH)] = {
+ [C(RESULT_ACCESS)] = -1,
+ [C(RESULT_MISS) ] = -1,
+ },
+ },
+
+ [C(BPU)] = {
+ [C(OP_READ)] = {
+ [C(RESULT_ACCESS)] = -1,
+ [C(RESULT_MISS) ] = -1,
+ },
+ [C(OP_WRITE)] = {
+ [C(RESULT_ACCESS)] = -1,
+ [C(RESULT_MISS) ] = -1,
+ },
+ [C(OP_PREFETCH)] = {
+ [C(RESULT_ACCESS)] = -1,
+ [C(RESULT_MISS) ] = -1,
+ },
+ },
+};
+
+const char *perf_pmu_name(void)
+{
+ return "bfin";
+}
+EXPORT_SYMBOL(perf_pmu_name);
+
+int perf_num_counters(void)
+{
+ return ARRAY_SIZE(event_map);
+}
+EXPORT_SYMBOL(perf_num_counters);
+
+static u64 bfin_pfmon_read(int idx)
+{
+ return bfin_read32(PFCNTR0 + (idx * 4));
+}
+
+static void bfin_pfmon_disable(struct hw_perf_event *hwc, int idx)
+{
+ bfin_write_PFCTL(bfin_read_PFCTL() & ~PFCEN(idx, PFCEN_MASK));
+}
+
+static void bfin_pfmon_enable(struct hw_perf_event *hwc, int idx)
+{
+ u32 val, mask;
+
+ val = PFPWR;
+ if (idx) {
+ mask = ~(PFCNT1 | PFMON1 | PFCEN1 | PEMUSW1);
+ /* The packed config is for event0, so shift it to event1 slots */
+ val |= (hwc->config << (PFMON1_P - PFMON0_P));
+ val |= (hwc->config & PFCNT0) << (PFCNT1_P - PFCNT0_P);
+ bfin_write_PFCNTR1(0);
+ } else {
+ mask = ~(PFCNT0 | PFMON0 | PFCEN0 | PEMUSW0);
+ val |= hwc->config;
+ bfin_write_PFCNTR0(0);
+ }
+
+ bfin_write_PFCTL((bfin_read_PFCTL() & mask) | val);
+}
+
+static void bfin_pfmon_disable_all(void)
+{
+ bfin_write_PFCTL(bfin_read_PFCTL() & ~PFPWR);
+}
+
+static void bfin_pfmon_enable_all(void)
+{
+ bfin_write_PFCTL(bfin_read_PFCTL() | PFPWR);
+}
+
+struct cpu_hw_events {
+ struct perf_event *events[MAX_HWEVENTS];
+ unsigned long used_mask[BITS_TO_LONGS(MAX_HWEVENTS)];
+};
+DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
+
+static int hw_perf_cache_event(int config, int *evp)
+{
+ unsigned long type, op, result;
+ int ev;
+
+ /* unpack config */
+ type = config & 0xff;
+ op = (config >> 8) & 0xff;
+ result = (config >> 16) & 0xff;
+
+ if (type >= PERF_COUNT_HW_CACHE_MAX ||
+ op >= PERF_COUNT_HW_CACHE_OP_MAX ||
+ result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
+ return -EINVAL;
+
+ ev = cache_events[type][op][result];
+ if (ev == 0)
+ return -EOPNOTSUPP;
+ if (ev == -1)
+ return -EINVAL;
+ *evp = ev;
+ return 0;
+}
+
+static void bfin_perf_event_update(struct perf_event *event,
+ struct hw_perf_event *hwc, int idx)
+{
+ u64 prev_raw_count, new_raw_count;
+ s64 delta;
+ int shift = 0;
+
+ /*
+ * Depending on the counter configuration, they may or may not
+ * be chained, in which case the previous counter value can be
+ * updated underneath us if the lower-half overflows.
+ *
+ * Our tactic to handle this is to first atomically read and
+ * exchange a new raw count - then add that new-prev delta
+ * count to the generic counter atomically.
+ *
+ * As there is no interrupt associated with the overflow events,
+ * this is the simplest approach for maintaining consistency.
+ */
+again:
+ prev_raw_count = local64_read(&hwc->prev_count);
+ new_raw_count = bfin_pfmon_read(idx);
+
+ if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
+ new_raw_count) != prev_raw_count)
+ goto again;
+
+ /*
+ * Now we have the new raw value and have updated the prev
+ * timestamp already. We can now calculate the elapsed delta
+ * (counter-)time and add that to the generic counter.
+ *
+ * Careful, not all hw sign-extends above the physical width
+ * of the count.
+ */
+ delta = (new_raw_count << shift) - (prev_raw_count << shift);
+ delta >>= shift;
+
+ local64_add(delta, &event->count);
+}
+
+static void bfin_pmu_stop(struct perf_event *event, int flags)
+{
+ struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+ struct hw_perf_event *hwc = &event->hw;
+ int idx = hwc->idx;
+
+ if (!(event->hw.state & PERF_HES_STOPPED)) {
+ bfin_pfmon_disable(hwc, idx);
+ cpuc->events[idx] = NULL;
+ event->hw.state |= PERF_HES_STOPPED;
+ }
+
+ if ((flags & PERF_EF_UPDATE) && !(event->hw.state & PERF_HES_UPTODATE)) {
+ bfin_perf_event_update(event, &event->hw, idx);
+ event->hw.state |= PERF_HES_UPTODATE;
+ }
+}
+
+static void bfin_pmu_start(struct perf_event *event, int flags)
+{
+ struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+ struct hw_perf_event *hwc = &event->hw;
+ int idx = hwc->idx;
+
+ if (WARN_ON_ONCE(idx == -1))
+ return;
+
+ if (flags & PERF_EF_RELOAD)
+ WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
+
+ cpuc->events[idx] = event;
+ event->hw.state = 0;
+ bfin_pfmon_enable(hwc, idx);
+}
+
+static void bfin_pmu_del(struct perf_event *event, int flags)
+{
+ struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+
+ bfin_pmu_stop(event, PERF_EF_UPDATE);
+ __clear_bit(event->hw.idx, cpuc->used_mask);
+
+ perf_event_update_userpage(event);
+}
+
+static int bfin_pmu_add(struct perf_event *event, int flags)
+{
+ struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+ struct hw_perf_event *hwc = &event->hw;
+ int idx = hwc->idx;
+ int ret = -EAGAIN;
+
+ perf_pmu_disable(event->pmu);
+
+ if (__test_and_set_bit(idx, cpuc->used_mask)) {
+ idx = find_first_zero_bit(cpuc->used_mask, MAX_HWEVENTS);
+ if (idx == MAX_HWEVENTS)
+ goto out;
+
+ __set_bit(idx, cpuc->used_mask);
+ hwc->idx = idx;
+ }
+
+ bfin_pfmon_disable(hwc, idx);
+
+ event->hw.state = PERF_HES_UPTODATE | PERF_HES_STOPPED;
+ if (flags & PERF_EF_START)
+ bfin_pmu_start(event, PERF_EF_RELOAD);
+
+ perf_event_update_userpage(event);
+ ret = 0;
+out:
+ perf_pmu_enable(event->pmu);
+ return ret;
+}
+
+static void bfin_pmu_read(struct perf_event *event)
+{
+ bfin_perf_event_update(event, &event->hw, event->hw.idx);
+}
+
+static int bfin_pmu_event_init(struct perf_event *event)
+{
+ struct perf_event_attr *attr = &event->attr;
+ struct hw_perf_event *hwc = &event->hw;
+ int config = -1;
+ int ret;
+
+ if (attr->exclude_hv || attr->exclude_idle)
+ return -EPERM;
+
+ /*
+ * All of the on-chip counters are "limited", in that they have
+ * no interrupts, and are therefore unable to do sampling without
+ * further work and timer assistance.
+ */
+ if (hwc->sample_period)
+ return -EINVAL;
+
+ ret = 0;
+ switch (attr->type) {
+ case PERF_TYPE_RAW:
+ config = PFMON(0, attr->config & PFMON_MASK) |
+ PFCNT(0, !(attr->config & 0x100));
+ break;
+ case PERF_TYPE_HW_CACHE:
+ ret = hw_perf_cache_event(attr->config, &config);
+ break;
+ case PERF_TYPE_HARDWARE:
+ if (attr->config >= ARRAY_SIZE(event_map))
+ return -EINVAL;
+
+ config = event_map[attr->config];
+ break;
+ }
+
+ if (config == -1)
+ return -EINVAL;
+
+ if (!attr->exclude_kernel)
+ config |= PFCEN(0, PFCEN_ENABLE_SUPV);
+ if (!attr->exclude_user)
+ config |= PFCEN(0, PFCEN_ENABLE_USER);
+
+ hwc->config |= config;
+
+ return ret;
+}
+
+static void bfin_pmu_enable(struct pmu *pmu)
+{
+ struct cpu_hw_events *cpuc = &__get_cpu_var(cpu_hw_events);
+ struct perf_event *event;
+ struct hw_perf_event *hwc;
+ int i;
+
+ for (i = 0; i < MAX_HWEVENTS; ++i) {
+ event = cpuc->events[i];
+ if (!event)
+ continue;
+ hwc = &event->hw;
+ bfin_pfmon_enable(hwc, hwc->idx);
+ }
+
+ bfin_pfmon_enable_all();
+}
+
+static void bfin_pmu_disable(struct pmu *pmu)
+{
+ bfin_pfmon_disable_all();
+}
+
+static struct pmu pmu = {
+ .pmu_enable = bfin_pmu_enable,
+ .pmu_disable = bfin_pmu_disable,
+ .event_init = bfin_pmu_event_init,
+ .add = bfin_pmu_add,
+ .del = bfin_pmu_del,
+ .start = bfin_pmu_start,
+ .stop = bfin_pmu_stop,
+ .read = bfin_pmu_read,
+};
+
+static void bfin_pmu_setup(int cpu)
+{
+ struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu);
+
+ memset(cpuhw, 0, sizeof(struct cpu_hw_events));
+}
+
+static int __cpuinit
+bfin_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
+{
+ unsigned int cpu = (long)hcpu;
+
+ switch (action & ~CPU_TASKS_FROZEN) {
+ case CPU_UP_PREPARE:
+ bfin_write_PFCTL(0);
+ bfin_pmu_setup(cpu);
+ break;
+
+ default:
+ break;
+ }
+
+ return NOTIFY_OK;
+}
+
+static int __init bfin_pmu_init(void)
+{
+ int ret;
+
+ ret = perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW);
+ if (!ret)
+ perf_cpu_notifier(bfin_pmu_notifier);
+
+ return ret;
+}
+early_initcall(bfin_pmu_init);
diff --git a/arch/blackfin/kernel/process.c b/arch/blackfin/kernel/process.c
index b407bc8..6a660fa 100644
--- a/arch/blackfin/kernel/process.c
+++ b/arch/blackfin/kernel/process.c
@@ -171,10 +171,8 @@
unsigned long newsp;
#ifdef __ARCH_SYNC_CORE_DCACHE
- if (current->rt.nr_cpus_allowed == num_possible_cpus()) {
- current->cpus_allowed = cpumask_of_cpu(smp_processor_id());
- current->rt.nr_cpus_allowed = 1;
- }
+ if (current->rt.nr_cpus_allowed == num_possible_cpus())
+ set_cpus_allowed_ptr(current, cpumask_of(smp_processor_id()));
#endif
/* syscall2 puts clone_flags in r0 and usp in r1 */
diff --git a/arch/blackfin/kernel/reboot.c b/arch/blackfin/kernel/reboot.c
index 53d08de..488bdc5 100644
--- a/arch/blackfin/kernel/reboot.c
+++ b/arch/blackfin/kernel/reboot.c
@@ -23,6 +23,9 @@
__attribute__ ((__l1_text__, __noreturn__))
static void bfin_reset(void)
{
+ if (!ANOMALY_05000353 && !ANOMALY_05000386)
+ bfrom_SoftReset((void *)(L1_SCRATCH_START + L1_SCRATCH_LENGTH - 20));
+
/* Wait for completion of "system" events such as cache line
* line fills so that we avoid infinite stalls later on as
* much as possible. This code is in L1, so it won't trigger
@@ -30,46 +33,40 @@
*/
__builtin_bfin_ssync();
- /* The bootrom checks to see how it was reset and will
- * automatically perform a software reset for us when
- * it starts executing after the core reset.
+ /* Initiate System software reset. */
+ bfin_write_SWRST(0x7);
+
+ /* Due to the way reset is handled in the hardware, we need
+ * to delay for 10 SCLKS. The only reliable way to do this is
+ * to calculate the CCLK/SCLK ratio and multiply 10. For now,
+ * we'll assume worse case which is a 1:15 ratio.
*/
- if (ANOMALY_05000353 || ANOMALY_05000386) {
- /* Initiate System software reset. */
- bfin_write_SWRST(0x7);
+ asm(
+ "LSETUP (1f, 1f) LC0 = %0\n"
+ "1: nop;"
+ :
+ : "a" (15 * 10)
+ : "LC0", "LB0", "LT0"
+ );
- /* Due to the way reset is handled in the hardware, we need
- * to delay for 10 SCLKS. The only reliable way to do this is
- * to calculate the CCLK/SCLK ratio and multiply 10. For now,
- * we'll assume worse case which is a 1:15 ratio.
- */
- asm(
- "LSETUP (1f, 1f) LC0 = %0\n"
- "1: nop;"
- :
- : "a" (15 * 10)
- : "LC0", "LB0", "LT0"
- );
+ /* Clear System software reset */
+ bfin_write_SWRST(0);
- /* Clear System software reset */
- bfin_write_SWRST(0);
-
- /* The BF526 ROM will crash during reset */
+ /* The BF526 ROM will crash during reset */
#if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)
- bfin_read_SWRST();
+ bfin_read_SWRST();
#endif
- /* Wait for the SWRST write to complete. Cannot rely on SSYNC
- * though as the System state is all reset now.
- */
- asm(
- "LSETUP (1f, 1f) LC1 = %0\n"
- "1: nop;"
- :
- : "a" (15 * 1)
- : "LC1", "LB1", "LT1"
- );
- }
+ /* Wait for the SWRST write to complete. Cannot rely on SSYNC
+ * though as the System state is all reset now.
+ */
+ asm(
+ "LSETUP (1f, 1f) LC1 = %0\n"
+ "1: nop;"
+ :
+ : "a" (15 * 1)
+ : "LC1", "LB1", "LT1"
+ );
while (1)
/* Issue core reset */
diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c
index 805c613..536bd9d 100644
--- a/arch/blackfin/kernel/setup.c
+++ b/arch/blackfin/kernel/setup.c
@@ -29,6 +29,7 @@
#include <asm/cpu.h>
#include <asm/fixed_code.h>
#include <asm/early_printk.h>
+#include <asm/irq_handler.h>
u16 _bfin_swrst;
EXPORT_SYMBOL(_bfin_swrst);
@@ -105,6 +106,8 @@
bfin_dcache_init(dcplb_tbl[cpu]);
#endif
+ bfin_setup_cpudata(cpu);
+
/*
* In cache coherence emulation mode, we need to have the
* D-cache enabled before running any atomic operation which
@@ -163,7 +166,6 @@
{
struct blackfin_cpudata *cpudata = &per_cpu(cpu_data, cpu);
- cpudata->idle = current;
cpudata->imemctl = bfin_read_IMEM_CONTROL();
cpudata->dmemctl = bfin_read_DMEM_CONTROL();
}
@@ -851,6 +853,7 @@
void __init setup_arch(char **cmdline_p)
{
+ u32 mmr;
unsigned long sclk, cclk;
native_machine_early_platform_add_devices();
@@ -902,10 +905,10 @@
bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTLVAL);
#endif
#ifdef CONFIG_BFIN_HYSTERESIS_CONTROL
- bfin_write_PORTF_HYSTERISIS(HYST_PORTF_0_15);
- bfin_write_PORTG_HYSTERISIS(HYST_PORTG_0_15);
- bfin_write_PORTH_HYSTERISIS(HYST_PORTH_0_15);
- bfin_write_MISCPORT_HYSTERISIS((bfin_read_MISCPORT_HYSTERISIS() &
+ bfin_write_PORTF_HYSTERESIS(HYST_PORTF_0_15);
+ bfin_write_PORTG_HYSTERESIS(HYST_PORTG_0_15);
+ bfin_write_PORTH_HYSTERESIS(HYST_PORTH_0_15);
+ bfin_write_MISCPORT_HYSTERESIS((bfin_read_MISCPORT_HYSTERESIS() &
~HYST_NONEGPIO_MASK) | HYST_NONEGPIO);
#endif
@@ -921,17 +924,14 @@
bfin_read_IMDMA_D1_IRQ_STATUS();
}
#endif
- printk(KERN_INFO "Hardware Trace ");
- if (bfin_read_TBUFCTL() & 0x1)
- printk(KERN_CONT "Active ");
- else
- printk(KERN_CONT "Off ");
- if (bfin_read_TBUFCTL() & 0x2)
- printk(KERN_CONT "and Enabled\n");
- else
- printk(KERN_CONT "and Disabled\n");
- printk(KERN_INFO "Boot Mode: %i\n", bfin_read_SYSCR() & 0xF);
+ mmr = bfin_read_TBUFCTL();
+ printk(KERN_INFO "Hardware Trace %s and %sabled\n",
+ (mmr & 0x1) ? "active" : "off",
+ (mmr & 0x2) ? "en" : "dis");
+
+ mmr = bfin_read_SYSCR();
+ printk(KERN_INFO "Boot Mode: %i\n", mmr & 0xF);
/* Newer parts mirror SWRST bits in SYSCR */
#if defined(CONFIG_BF53x) || defined(CONFIG_BF561) || \
@@ -939,7 +939,7 @@
_bfin_swrst = bfin_read_SWRST();
#else
/* Clear boot mode field */
- _bfin_swrst = bfin_read_SYSCR() & ~0xf;
+ _bfin_swrst = mmr & ~0xf;
#endif
#ifdef CONFIG_DEBUG_DOUBLEFAULT_PRINT
@@ -1036,8 +1036,6 @@
static int __init topology_init(void)
{
unsigned int cpu;
- /* Record CPU-private information for the boot processor. */
- bfin_setup_cpudata(0);
for_each_possible_cpu(cpu) {
register_cpu(&per_cpu(cpu_data, cpu).cpu, cpu);
@@ -1283,12 +1281,14 @@
dsup_banks, BFIN_DSUBBANKS, BFIN_DWAYS,
BFIN_DLINES);
#ifdef __ARCH_SYNC_CORE_DCACHE
- seq_printf(m, "SMP Dcache Flushes\t: %lu\n\n", dcache_invld_count[cpu_num]);
+ seq_printf(m, "dcache flushes\t: %lu\n", dcache_invld_count[cpu_num]);
#endif
#ifdef __ARCH_SYNC_CORE_ICACHE
- seq_printf(m, "SMP Icache Flushes\t: %lu\n\n", icache_invld_count[cpu_num]);
+ seq_printf(m, "icache flushes\t: %lu\n", icache_invld_count[cpu_num]);
#endif
+ seq_printf(m, "\n");
+
if (cpu_num != num_possible_cpus() - 1)
return 0;
@@ -1312,13 +1312,11 @@
" in data cache\n");
}
seq_printf(m, "board name\t: %s\n", bfin_board_name);
- seq_printf(m, "board memory\t: %ld kB (0x%p -> 0x%p)\n",
- physical_mem_end >> 10, (void *)0, (void *)physical_mem_end);
- seq_printf(m, "kernel memory\t: %d kB (0x%p -> 0x%p)\n",
+ seq_printf(m, "board memory\t: %ld kB (0x%08lx -> 0x%08lx)\n",
+ physical_mem_end >> 10, 0ul, physical_mem_end);
+ seq_printf(m, "kernel memory\t: %d kB (0x%08lx -> 0x%08lx)\n",
((int)memory_end - (int)_rambase) >> 10,
- (void *)_rambase,
- (void *)memory_end);
- seq_printf(m, "\n");
+ _rambase, memory_end);
return 0;
}
@@ -1326,7 +1324,7 @@
static void *c_start(struct seq_file *m, loff_t *pos)
{
if (*pos == 0)
- *pos = first_cpu(cpu_online_map);
+ *pos = cpumask_first(cpu_online_mask);
if (*pos >= num_online_cpus())
return NULL;
@@ -1335,7 +1333,7 @@
static void *c_next(struct seq_file *m, void *v, loff_t *pos)
{
- *pos = next_cpu(*pos, cpu_online_map);
+ *pos = cpumask_next(*pos, cpu_online_mask);
return c_start(m, pos);
}
diff --git a/arch/blackfin/kernel/vmlinux.lds.S b/arch/blackfin/kernel/vmlinux.lds.S
index 854fa49..3ac5b66 100644
--- a/arch/blackfin/kernel/vmlinux.lds.S
+++ b/arch/blackfin/kernel/vmlinux.lds.S
@@ -136,7 +136,7 @@
. = ALIGN(16);
INIT_DATA_SECTION(16)
- PERCPU(32, PAGE_SIZE)
+ PERCPU_SECTION(32)
.exit.data :
{
@@ -155,14 +155,8 @@
SECURITY_INITCALL
INIT_RAM_FS
- . = ALIGN(4);
___per_cpu_load = .;
- ___per_cpu_start = .;
- *(.data.percpu.first)
- *(.data.percpu.page_aligned)
- *(.data.percpu)
- *(.data.percpu.shared_aligned)
- ___per_cpu_end = .;
+ PERCPU_INPUT(32)
EXIT_DATA
__einitdata = .;
diff --git a/arch/blackfin/mach-bf518/include/mach/anomaly.h b/arch/blackfin/mach-bf518/include/mach/anomaly.h
index 24918c5..d2f076f 100644
--- a/arch/blackfin/mach-bf518/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf518/include/mach/anomaly.h
@@ -5,7 +5,7 @@
* and can be replaced with that version at any time
* DO NOT EDIT THIS FILE
*
- * Copyright 2004-2010 Analog Devices Inc.
+ * Copyright 2004-2011 Analog Devices Inc.
* Licensed under the ADI BSD license.
* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
*/
@@ -141,6 +141,7 @@
#define ANOMALY_05000364 (0)
#define ANOMALY_05000371 (0)
#define ANOMALY_05000380 (0)
+#define ANOMALY_05000383 (0)
#define ANOMALY_05000386 (0)
#define ANOMALY_05000389 (0)
#define ANOMALY_05000400 (0)
@@ -155,6 +156,7 @@
#define ANOMALY_05000467 (0)
#define ANOMALY_05000474 (0)
#define ANOMALY_05000475 (0)
+#define ANOMALY_05000480 (0)
#define ANOMALY_05000485 (0)
#endif
diff --git a/arch/blackfin/mach-bf518/include/mach/cdefBF512.h b/arch/blackfin/mach-bf518/include/mach/cdefBF512.h
index b657d37..bb79627 100644
--- a/arch/blackfin/mach-bf518/include/mach/cdefBF512.h
+++ b/arch/blackfin/mach-bf518/include/mach/cdefBF512.h
@@ -990,18 +990,18 @@
#define bfin_write_PORTG_SLEW(val) bfin_write16(PORTG_SLEW, val)
#define bfin_read_PORTH_SLEW() bfin_read16(PORTH_SLEW)
#define bfin_write_PORTH_SLEW(val) bfin_write16(PORTH_SLEW, val)
-#define bfin_read_PORTF_HYSTERISIS() bfin_read16(PORTF_HYSTERISIS)
-#define bfin_write_PORTF_HYSTERISIS(val) bfin_write16(PORTF_HYSTERISIS, val)
-#define bfin_read_PORTG_HYSTERISIS() bfin_read16(PORTG_HYSTERISIS)
-#define bfin_write_PORTG_HYSTERISIS(val) bfin_write16(PORTG_HYSTERISIS, val)
-#define bfin_read_PORTH_HYSTERISIS() bfin_read16(PORTH_HYSTERISIS)
-#define bfin_write_PORTH_HYSTERISIS(val) bfin_write16(PORTH_HYSTERISIS, val)
+#define bfin_read_PORTF_HYSTERESIS() bfin_read16(PORTF_HYSTERESIS)
+#define bfin_write_PORTF_HYSTERESIS(val) bfin_write16(PORTF_HYSTERESIS, val)
+#define bfin_read_PORTG_HYSTERESIS() bfin_read16(PORTG_HYSTERESIS)
+#define bfin_write_PORTG_HYSTERESIS(val) bfin_write16(PORTG_HYSTERESIS, val)
+#define bfin_read_PORTH_HYSTERESIS() bfin_read16(PORTH_HYSTERESIS)
+#define bfin_write_PORTH_HYSTERESIS(val) bfin_write16(PORTH_HYSTERESIS, val)
#define bfin_read_MISCPORT_DRIVE() bfin_read16(MISCPORT_DRIVE)
#define bfin_write_MISCPORT_DRIVE(val) bfin_write16(MISCPORT_DRIVE, val)
#define bfin_read_MISCPORT_SLEW() bfin_read16(MISCPORT_SLEW)
#define bfin_write_MISCPORT_SLEW(val) bfin_write16(MISCPORT_SLEW, val)
-#define bfin_read_MISCPORT_HYSTERISIS() bfin_read16(MISCPORT_HYSTERISIS)
-#define bfin_write_MISCPORT_HYSTERISIS(val) bfin_write16(MISCPORT_HYSTERISIS, val)
+#define bfin_read_MISCPORT_HYSTERESIS() bfin_read16(MISCPORT_HYSTERESIS)
+#define bfin_write_MISCPORT_HYSTERESIS(val) bfin_write16(MISCPORT_HYSTERESIS, val)
/* HOST Port Registers */
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF512.h b/arch/blackfin/mach-bf518/include/mach/defBF512.h
index cb1172f..7297040 100644
--- a/arch/blackfin/mach-bf518/include/mach/defBF512.h
+++ b/arch/blackfin/mach-bf518/include/mach/defBF512.h
@@ -561,12 +561,12 @@
#define PORTF_SLEW 0xFFC03230 /* Port F slew control */
#define PORTG_SLEW 0xFFC03234 /* Port G slew control */
#define PORTH_SLEW 0xFFC03238 /* Port H slew control */
-#define PORTF_HYSTERISIS 0xFFC03240 /* Port F Schmitt trigger control */
-#define PORTG_HYSTERISIS 0xFFC03244 /* Port G Schmitt trigger control */
-#define PORTH_HYSTERISIS 0xFFC03248 /* Port H Schmitt trigger control */
+#define PORTF_HYSTERESIS 0xFFC03240 /* Port F Schmitt trigger control */
+#define PORTG_HYSTERESIS 0xFFC03244 /* Port G Schmitt trigger control */
+#define PORTH_HYSTERESIS 0xFFC03248 /* Port H Schmitt trigger control */
#define MISCPORT_DRIVE 0xFFC03280 /* Misc Port drive strength control */
#define MISCPORT_SLEW 0xFFC03284 /* Misc Port slew control */
-#define MISCPORT_HYSTERISIS 0xFFC03288 /* Misc Port Schmitt trigger control */
+#define MISCPORT_HYSTERESIS 0xFFC03288 /* Misc Port Schmitt trigger control */
/***********************************************************************************
diff --git a/arch/blackfin/mach-bf518/include/mach/irq.h b/arch/blackfin/mach-bf518/include/mach/irq.h
index 435e76e..edf8efd 100644
--- a/arch/blackfin/mach-bf518/include/mach/irq.h
+++ b/arch/blackfin/mach-bf518/include/mach/irq.h
@@ -7,38 +7,9 @@
#ifndef _BF518_IRQ_H_
#define _BF518_IRQ_H_
-/*
- * Interrupt source definitions
- Event Source Core Event Name
- Core Emulation **
- Events (highest priority) EMU 0
- Reset RST 1
- NMI NMI 2
- Exception EVX 3
- Reserved -- 4
- Hardware Error IVHW 5
- Core Timer IVTMR 6 *
+#include <mach-common/irq.h>
- .....
-
- Software Interrupt 1 IVG14 31
- Software Interrupt 2 --
- (lowest priority) IVG15 32 *
-*/
-
-#define NR_PERI_INTS (2 * 32)
-
-/* The ABSTRACT IRQ definitions */
-/** the first seven of the following are fixed, the rest you change if you need to **/
-#define IRQ_EMU 0 /* Emulation */
-#define IRQ_RST 1 /* reset */
-#define IRQ_NMI 2 /* Non Maskable */
-#define IRQ_EVX 3 /* Exception */
-#define IRQ_UNUSED 4 /* - unused interrupt */
-#define IRQ_HWERR 5 /* Hardware Error */
-#define IRQ_CORETMR 6 /* Core timer */
-
-#define BFIN_IRQ(x) ((x) + 7)
+#define NR_PERI_INTS (2 * 32)
#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */
@@ -54,23 +25,23 @@
#define IRQ_UART0_ERROR BFIN_IRQ(12) /* UART0 Status */
#define IRQ_UART1_ERROR BFIN_IRQ(13) /* UART1 Status */
#define IRQ_RTC BFIN_IRQ(14) /* RTC */
-#define IRQ_PPI BFIN_IRQ(15) /* DMA Channel 0 (PPI) */
+#define IRQ_PPI BFIN_IRQ(15) /* DMA Channel 0 (PPI) */
#define IRQ_SPORT0_RX BFIN_IRQ(16) /* DMA 3 Channel (SPORT0 RX) */
#define IRQ_SPORT0_TX BFIN_IRQ(17) /* DMA 4 Channel (SPORT0 TX) */
#define IRQ_RSI BFIN_IRQ(17) /* DMA 4 Channel (RSI) */
#define IRQ_SPORT1_RX BFIN_IRQ(18) /* DMA 5 Channel (SPORT1 RX/SPI) */
#define IRQ_SPI1 BFIN_IRQ(18) /* DMA 5 Channel (SPI1) */
#define IRQ_SPORT1_TX BFIN_IRQ(19) /* DMA 6 Channel (SPORT1 TX) */
-#define IRQ_TWI BFIN_IRQ(20) /* TWI */
-#define IRQ_SPI0 BFIN_IRQ(21) /* DMA 7 Channel (SPI0) */
-#define IRQ_UART0_RX BFIN_IRQ(22) /* DMA8 Channel (UART0 RX) */
-#define IRQ_UART0_TX BFIN_IRQ(23) /* DMA9 Channel (UART0 TX) */
-#define IRQ_UART1_RX BFIN_IRQ(24) /* DMA10 Channel (UART1 RX) */
-#define IRQ_UART1_TX BFIN_IRQ(25) /* DMA11 Channel (UART1 TX) */
-#define IRQ_OPTSEC BFIN_IRQ(26) /* OTPSEC Interrupt */
-#define IRQ_CNT BFIN_IRQ(27) /* GP Counter */
-#define IRQ_MAC_RX BFIN_IRQ(28) /* DMA1 Channel (MAC RX) */
-#define IRQ_PORTH_INTA BFIN_IRQ(29) /* Port H Interrupt A */
+#define IRQ_TWI BFIN_IRQ(20) /* TWI */
+#define IRQ_SPI0 BFIN_IRQ(21) /* DMA 7 Channel (SPI0) */
+#define IRQ_UART0_RX BFIN_IRQ(22) /* DMA8 Channel (UART0 RX) */
+#define IRQ_UART0_TX BFIN_IRQ(23) /* DMA9 Channel (UART0 TX) */
+#define IRQ_UART1_RX BFIN_IRQ(24) /* DMA10 Channel (UART1 RX) */
+#define IRQ_UART1_TX BFIN_IRQ(25) /* DMA11 Channel (UART1 TX) */
+#define IRQ_OPTSEC BFIN_IRQ(26) /* OTPSEC Interrupt */
+#define IRQ_CNT BFIN_IRQ(27) /* GP Counter */
+#define IRQ_MAC_RX BFIN_IRQ(28) /* DMA1 Channel (MAC RX) */
+#define IRQ_PORTH_INTA BFIN_IRQ(29) /* Port H Interrupt A */
#define IRQ_MAC_TX BFIN_IRQ(30) /* DMA2 Channel (MAC TX) */
#define IRQ_PORTH_INTB BFIN_IRQ(31) /* Port H Interrupt B */
#define IRQ_TIMER0 BFIN_IRQ(32) /* Timer 0 */
@@ -96,101 +67,90 @@
#define IRQ_PWM_SYNC BFIN_IRQ(54) /* PWM Sync Interrupt */
#define IRQ_PTP_STAT BFIN_IRQ(55) /* PTP Stat Interrupt */
-#define SYS_IRQS BFIN_IRQ(63) /* 70 */
+#define SYS_IRQS BFIN_IRQ(63) /* 70 */
-#define IRQ_PF0 71
-#define IRQ_PF1 72
-#define IRQ_PF2 73
-#define IRQ_PF3 74
-#define IRQ_PF4 75
-#define IRQ_PF5 76
-#define IRQ_PF6 77
-#define IRQ_PF7 78
-#define IRQ_PF8 79
-#define IRQ_PF9 80
-#define IRQ_PF10 81
-#define IRQ_PF11 82
-#define IRQ_PF12 83
-#define IRQ_PF13 84
-#define IRQ_PF14 85
-#define IRQ_PF15 86
+#define IRQ_PF0 71
+#define IRQ_PF1 72
+#define IRQ_PF2 73
+#define IRQ_PF3 74
+#define IRQ_PF4 75
+#define IRQ_PF5 76
+#define IRQ_PF6 77
+#define IRQ_PF7 78
+#define IRQ_PF8 79
+#define IRQ_PF9 80
+#define IRQ_PF10 81
+#define IRQ_PF11 82
+#define IRQ_PF12 83
+#define IRQ_PF13 84
+#define IRQ_PF14 85
+#define IRQ_PF15 86
-#define IRQ_PG0 87
-#define IRQ_PG1 88
-#define IRQ_PG2 89
-#define IRQ_PG3 90
-#define IRQ_PG4 91
-#define IRQ_PG5 92
-#define IRQ_PG6 93
-#define IRQ_PG7 94
-#define IRQ_PG8 95
-#define IRQ_PG9 96
-#define IRQ_PG10 97
-#define IRQ_PG11 98
-#define IRQ_PG12 99
-#define IRQ_PG13 100
-#define IRQ_PG14 101
-#define IRQ_PG15 102
+#define IRQ_PG0 87
+#define IRQ_PG1 88
+#define IRQ_PG2 89
+#define IRQ_PG3 90
+#define IRQ_PG4 91
+#define IRQ_PG5 92
+#define IRQ_PG6 93
+#define IRQ_PG7 94
+#define IRQ_PG8 95
+#define IRQ_PG9 96
+#define IRQ_PG10 97
+#define IRQ_PG11 98
+#define IRQ_PG12 99
+#define IRQ_PG13 100
+#define IRQ_PG14 101
+#define IRQ_PG15 102
-#define IRQ_PH0 103
-#define IRQ_PH1 104
-#define IRQ_PH2 105
-#define IRQ_PH3 106
-#define IRQ_PH4 107
-#define IRQ_PH5 108
-#define IRQ_PH6 109
-#define IRQ_PH7 110
-#define IRQ_PH8 111
-#define IRQ_PH9 112
-#define IRQ_PH10 113
-#define IRQ_PH11 114
-#define IRQ_PH12 115
-#define IRQ_PH13 116
-#define IRQ_PH14 117
-#define IRQ_PH15 118
+#define IRQ_PH0 103
+#define IRQ_PH1 104
+#define IRQ_PH2 105
+#define IRQ_PH3 106
+#define IRQ_PH4 107
+#define IRQ_PH5 108
+#define IRQ_PH6 109
+#define IRQ_PH7 110
+#define IRQ_PH8 111
+#define IRQ_PH9 112
+#define IRQ_PH10 113
+#define IRQ_PH11 114
+#define IRQ_PH12 115
+#define IRQ_PH13 116
+#define IRQ_PH14 117
+#define IRQ_PH15 118
-#define GPIO_IRQ_BASE IRQ_PF0
+#define GPIO_IRQ_BASE IRQ_PF0
-#define IRQ_MAC_PHYINT 119 /* PHY_INT Interrupt */
-#define IRQ_MAC_MMCINT 120 /* MMC Counter Interrupt */
-#define IRQ_MAC_RXFSINT 121 /* RX Frame-Status Interrupt */
-#define IRQ_MAC_TXFSINT 122 /* TX Frame-Status Interrupt */
-#define IRQ_MAC_WAKEDET 123 /* Wake-Up Interrupt */
-#define IRQ_MAC_RXDMAERR 124 /* RX DMA Direction Error Interrupt */
-#define IRQ_MAC_TXDMAERR 125 /* TX DMA Direction Error Interrupt */
-#define IRQ_MAC_STMDONE 126 /* Station Mgt. Transfer Done Interrupt */
+#define IRQ_MAC_PHYINT 119 /* PHY_INT Interrupt */
+#define IRQ_MAC_MMCINT 120 /* MMC Counter Interrupt */
+#define IRQ_MAC_RXFSINT 121 /* RX Frame-Status Interrupt */
+#define IRQ_MAC_TXFSINT 122 /* TX Frame-Status Interrupt */
+#define IRQ_MAC_WAKEDET 123 /* Wake-Up Interrupt */
+#define IRQ_MAC_RXDMAERR 124 /* RX DMA Direction Error Interrupt */
+#define IRQ_MAC_TXDMAERR 125 /* TX DMA Direction Error Interrupt */
+#define IRQ_MAC_STMDONE 126 /* Station Mgt. Transfer Done Interrupt */
-#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1)
-#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
-
-#define IVG7 7
-#define IVG8 8
-#define IVG9 9
-#define IVG10 10
-#define IVG11 11
-#define IVG12 12
-#define IVG13 13
-#define IVG14 14
-#define IVG15 15
+#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1)
/* IAR0 BIT FIELDS */
#define IRQ_PLL_WAKEUP_POS 0
#define IRQ_DMA0_ERROR_POS 4
-#define IRQ_DMAR0_BLK_POS 8
-#define IRQ_DMAR1_BLK_POS 12
-#define IRQ_DMAR0_OVR_POS 16
-#define IRQ_DMAR1_OVR_POS 20
-#define IRQ_PPI_ERROR_POS 24
-#define IRQ_MAC_ERROR_POS 28
+#define IRQ_DMAR0_BLK_POS 8
+#define IRQ_DMAR1_BLK_POS 12
+#define IRQ_DMAR0_OVR_POS 16
+#define IRQ_DMAR1_OVR_POS 20
+#define IRQ_PPI_ERROR_POS 24
+#define IRQ_MAC_ERROR_POS 28
/* IAR1 BIT FIELDS */
#define IRQ_SPORT0_ERROR_POS 0
#define IRQ_SPORT1_ERROR_POS 4
#define IRQ_PTP_ERROR_POS 8
-#define IRQ_UART0_ERROR_POS 16
-#define IRQ_UART1_ERROR_POS 20
-#define IRQ_RTC_POS 24
-#define IRQ_PPI_POS 28
+#define IRQ_UART0_ERROR_POS 16
+#define IRQ_UART1_ERROR_POS 20
+#define IRQ_RTC_POS 24
+#define IRQ_PPI_POS 28
/* IAR2 BIT FIELDS */
#define IRQ_SPORT0_RX_POS 0
@@ -199,19 +159,19 @@
#define IRQ_SPORT1_RX_POS 8
#define IRQ_SPI1_POS 8
#define IRQ_SPORT1_TX_POS 12
-#define IRQ_TWI_POS 16
-#define IRQ_SPI0_POS 20
-#define IRQ_UART0_RX_POS 24
-#define IRQ_UART0_TX_POS 28
+#define IRQ_TWI_POS 16
+#define IRQ_SPI0_POS 20
+#define IRQ_UART0_RX_POS 24
+#define IRQ_UART0_TX_POS 28
/* IAR3 BIT FIELDS */
-#define IRQ_UART1_RX_POS 0
-#define IRQ_UART1_TX_POS 4
-#define IRQ_OPTSEC_POS 8
-#define IRQ_CNT_POS 12
-#define IRQ_MAC_RX_POS 16
+#define IRQ_UART1_RX_POS 0
+#define IRQ_UART1_TX_POS 4
+#define IRQ_OPTSEC_POS 8
+#define IRQ_CNT_POS 12
+#define IRQ_MAC_RX_POS 16
#define IRQ_PORTH_INTA_POS 20
-#define IRQ_MAC_TX_POS 24
+#define IRQ_MAC_TX_POS 24
#define IRQ_PORTH_INTB_POS 28
/* IAR4 BIT FIELDS */
@@ -227,19 +187,19 @@
/* IAR5 BIT FIELDS */
#define IRQ_PORTG_INTA_POS 0
#define IRQ_PORTG_INTB_POS 4
-#define IRQ_MEM_DMA0_POS 8
-#define IRQ_MEM_DMA1_POS 12
-#define IRQ_WATCH_POS 16
+#define IRQ_MEM_DMA0_POS 8
+#define IRQ_MEM_DMA1_POS 12
+#define IRQ_WATCH_POS 16
#define IRQ_PORTF_INTA_POS 20
#define IRQ_PORTF_INTB_POS 24
-#define IRQ_SPI0_ERROR_POS 28
+#define IRQ_SPI0_ERROR_POS 28
/* IAR6 BIT FIELDS */
-#define IRQ_SPI1_ERROR_POS 0
-#define IRQ_RSI_INT0_POS 12
-#define IRQ_RSI_INT1_POS 16
-#define IRQ_PWM_TRIP_POS 20
-#define IRQ_PWM_SYNC_POS 24
-#define IRQ_PTP_STAT_POS 28
+#define IRQ_SPI1_ERROR_POS 0
+#define IRQ_RSI_INT0_POS 12
+#define IRQ_RSI_INT1_POS 16
+#define IRQ_PWM_TRIP_POS 20
+#define IRQ_PWM_SYNC_POS 24
+#define IRQ_PTP_STAT_POS 28
-#endif /* _BF518_IRQ_H_ */
+#endif
diff --git a/arch/blackfin/mach-bf527/boards/ezkit.c b/arch/blackfin/mach-bf527/boards/ezkit.c
index 2cd2ff6..e67ac77 100644
--- a/arch/blackfin/mach-bf527/boards/ezkit.c
+++ b/arch/blackfin/mach-bf527/boards/ezkit.c
@@ -26,6 +26,7 @@
#include <asm/portmux.h>
#include <asm/dpmc.h>
#include <linux/spi/ad7877.h>
+#include <asm/bfin_sport.h>
/*
* Name the Board for the /proc/cpuinfo
@@ -526,11 +527,69 @@
};
#endif
+#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) || \
+ defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
+
+static const u16 bfin_snd_pin[][7] = {
+ {P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
+ P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0, 0},
+ {P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
+ P_SPORT1_DRPRI, P_SPORT1_RSCLK, P_SPORT1_TFS, 0},
+};
+
+static struct bfin_snd_platform_data bfin_snd_data[] = {
+ {
+ .pin_req = &bfin_snd_pin[0][0],
+ },
+ {
+ .pin_req = &bfin_snd_pin[1][0],
+ },
+};
+
+#define BFIN_SND_RES(x) \
+ [x] = { \
+ { \
+ .start = SPORT##x##_TCR1, \
+ .end = SPORT##x##_TCR1, \
+ .flags = IORESOURCE_MEM \
+ }, \
+ { \
+ .start = CH_SPORT##x##_RX, \
+ .end = CH_SPORT##x##_RX, \
+ .flags = IORESOURCE_DMA, \
+ }, \
+ { \
+ .start = CH_SPORT##x##_TX, \
+ .end = CH_SPORT##x##_TX, \
+ .flags = IORESOURCE_DMA, \
+ }, \
+ { \
+ .start = IRQ_SPORT##x##_ERROR, \
+ .end = IRQ_SPORT##x##_ERROR, \
+ .flags = IORESOURCE_IRQ, \
+ } \
+ }
+
+static struct resource bfin_snd_resources[][4] = {
+ BFIN_SND_RES(0),
+ BFIN_SND_RES(1),
+};
+
+static struct platform_device bfin_pcm = {
+ .name = "bfin-pcm-audio",
+ .id = -1,
+};
+#endif
+
#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
static struct platform_device bfin_i2s = {
.name = "bfin-i2s",
.id = CONFIG_SND_BF5XX_SPORT_NUM,
- /* TODO: add platform data here */
+ .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
+ .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
+ .dev = {
+ .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
+ },
};
#endif
@@ -538,7 +597,11 @@
static struct platform_device bfin_tdm = {
.name = "bfin-tdm",
.id = CONFIG_SND_BF5XX_SPORT_NUM,
- /* TODO: add platform data here */
+ .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
+ .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
+ .dev = {
+ .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
+ },
};
#endif
@@ -583,7 +646,9 @@
.max_speed_hz = 3125000, /* max spi clock (SCK) speed in HZ */
.bus_num = 0,
.chip_select = 4,
+ .platform_data = "ad1836",
.controller_data = &ad1836_spi_chip_info,
+ .mode = SPI_MODE_3,
},
#endif
#if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
@@ -1211,6 +1276,11 @@
&ezkit_flash_device,
#endif
+#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) || \
+ defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
+ &bfin_pcm,
+#endif
+
#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
&bfin_i2s,
#endif
diff --git a/arch/blackfin/mach-bf527/include/mach/anomaly.h b/arch/blackfin/mach-bf527/include/mach/anomaly.h
index 9358afa0..e66a7e8 100644
--- a/arch/blackfin/mach-bf527/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf527/include/mach/anomaly.h
@@ -5,14 +5,14 @@
* and can be replaced with that version at any time
* DO NOT EDIT THIS FILE
*
- * Copyright 2004-2010 Analog Devices Inc.
+ * Copyright 2004-2011 Analog Devices Inc.
* Licensed under the ADI BSD license.
* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
*/
/* This file should be up to date with:
* - Revision E, 03/15/2010; ADSP-BF526 Blackfin Processor Anomaly List
- * - Revision G, 08/25/2009; ADSP-BF527 Blackfin Processor Anomaly List
+ * - Revision H, 04/29/2010; ADSP-BF527 Blackfin Processor Anomaly List
*/
#ifndef _MACH_ANOMALY_H_
@@ -220,6 +220,8 @@
#define ANOMALY_05000483 (1)
/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
#define ANOMALY_05000485 (_ANOMALY_BF526_BF527(< 2, < 3))
+/* The CODEC Zero-Cross Detect Feature is not Functional */
+#define ANOMALY_05000487 (1)
/* IFLUSH sucks at life */
#define ANOMALY_05000491 (1)
@@ -268,11 +270,13 @@
#define ANOMALY_05000323 (0)
#define ANOMALY_05000362 (1)
#define ANOMALY_05000363 (0)
+#define ANOMALY_05000383 (0)
#define ANOMALY_05000400 (0)
#define ANOMALY_05000402 (0)
#define ANOMALY_05000412 (0)
#define ANOMALY_05000447 (0)
#define ANOMALY_05000448 (0)
#define ANOMALY_05000474 (0)
+#define ANOMALY_05000480 (0)
#endif
diff --git a/arch/blackfin/mach-bf527/include/mach/cdefBF522.h b/arch/blackfin/mach-bf527/include/mach/cdefBF522.h
index 618dfcd..2c12e87 100644
--- a/arch/blackfin/mach-bf527/include/mach/cdefBF522.h
+++ b/arch/blackfin/mach-bf527/include/mach/cdefBF522.h
@@ -1007,18 +1007,18 @@
#define bfin_write_PORTG_SLEW(val) bfin_write16(PORTG_SLEW, val)
#define bfin_read_PORTH_SLEW() bfin_read16(PORTH_SLEW)
#define bfin_write_PORTH_SLEW(val) bfin_write16(PORTH_SLEW, val)
-#define bfin_read_PORTF_HYSTERISIS() bfin_read16(PORTF_HYSTERISIS)
-#define bfin_write_PORTF_HYSTERISIS(val) bfin_write16(PORTF_HYSTERISIS, val)
-#define bfin_read_PORTG_HYSTERISIS() bfin_read16(PORTG_HYSTERISIS)
-#define bfin_write_PORTG_HYSTERISIS(val) bfin_write16(PORTG_HYSTERISIS, val)
-#define bfin_read_PORTH_HYSTERISIS() bfin_read16(PORTH_HYSTERISIS)
-#define bfin_write_PORTH_HYSTERISIS(val) bfin_write16(PORTH_HYSTERISIS, val)
+#define bfin_read_PORTF_HYSTERESIS() bfin_read16(PORTF_HYSTERESIS)
+#define bfin_write_PORTF_HYSTERESIS(val) bfin_write16(PORTF_HYSTERESIS, val)
+#define bfin_read_PORTG_HYSTERESIS() bfin_read16(PORTG_HYSTERESIS)
+#define bfin_write_PORTG_HYSTERESIS(val) bfin_write16(PORTG_HYSTERESIS, val)
+#define bfin_read_PORTH_HYSTERESIS() bfin_read16(PORTH_HYSTERESIS)
+#define bfin_write_PORTH_HYSTERESIS(val) bfin_write16(PORTH_HYSTERESIS, val)
#define bfin_read_MISCPORT_DRIVE() bfin_read16(MISCPORT_DRIVE)
#define bfin_write_MISCPORT_DRIVE(val) bfin_write16(MISCPORT_DRIVE, val)
#define bfin_read_MISCPORT_SLEW() bfin_read16(MISCPORT_SLEW)
#define bfin_write_MISCPORT_SLEW(val) bfin_write16(MISCPORT_SLEW, val)
-#define bfin_read_MISCPORT_HYSTERISIS() bfin_read16(MISCPORT_HYSTERISIS)
-#define bfin_write_MISCPORT_HYSTERISIS(val) bfin_write16(MISCPORT_HYSTERISIS, val)
+#define bfin_read_MISCPORT_HYSTERESIS() bfin_read16(MISCPORT_HYSTERESIS)
+#define bfin_write_MISCPORT_HYSTERESIS(val) bfin_write16(MISCPORT_HYSTERESIS, val)
/* HOST Port Registers */
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF522.h b/arch/blackfin/mach-bf527/include/mach/defBF522.h
index 84ef11e..37d353a 100644
--- a/arch/blackfin/mach-bf527/include/mach/defBF522.h
+++ b/arch/blackfin/mach-bf527/include/mach/defBF522.h
@@ -562,12 +562,12 @@
#define PORTF_SLEW 0xFFC03230 /* Port F slew control */
#define PORTG_SLEW 0xFFC03234 /* Port G slew control */
#define PORTH_SLEW 0xFFC03238 /* Port H slew control */
-#define PORTF_HYSTERISIS 0xFFC03240 /* Port F Schmitt trigger control */
-#define PORTG_HYSTERISIS 0xFFC03244 /* Port G Schmitt trigger control */
-#define PORTH_HYSTERISIS 0xFFC03248 /* Port H Schmitt trigger control */
+#define PORTF_HYSTERESIS 0xFFC03240 /* Port F Schmitt trigger control */
+#define PORTG_HYSTERESIS 0xFFC03244 /* Port G Schmitt trigger control */
+#define PORTH_HYSTERESIS 0xFFC03248 /* Port H Schmitt trigger control */
#define MISCPORT_DRIVE 0xFFC03280 /* Misc Port drive strength control */
#define MISCPORT_SLEW 0xFFC03284 /* Misc Port slew control */
-#define MISCPORT_HYSTERISIS 0xFFC03288 /* Misc Port Schmitt trigger control */
+#define MISCPORT_HYSTERESIS 0xFFC03288 /* Misc Port Schmitt trigger control */
/***********************************************************************************
diff --git a/arch/blackfin/mach-bf527/include/mach/irq.h b/arch/blackfin/mach-bf527/include/mach/irq.h
index 704d925..ed7310f 100644
--- a/arch/blackfin/mach-bf527/include/mach/irq.h
+++ b/arch/blackfin/mach-bf527/include/mach/irq.h
@@ -7,38 +7,9 @@
#ifndef _BF527_IRQ_H_
#define _BF527_IRQ_H_
-/*
- * Interrupt source definitions
- Event Source Core Event Name
- Core Emulation **
- Events (highest priority) EMU 0
- Reset RST 1
- NMI NMI 2
- Exception EVX 3
- Reserved -- 4
- Hardware Error IVHW 5
- Core Timer IVTMR 6 *
+#include <mach-common/irq.h>
- .....
-
- Software Interrupt 1 IVG14 31
- Software Interrupt 2 --
- (lowest priority) IVG15 32 *
-*/
-
-#define NR_PERI_INTS (2 * 32)
-
-/* The ABSTRACT IRQ definitions */
-/** the first seven of the following are fixed, the rest you change if you need to **/
-#define IRQ_EMU 0 /* Emulation */
-#define IRQ_RST 1 /* reset */
-#define IRQ_NMI 2 /* Non Maskable */
-#define IRQ_EVX 3 /* Exception */
-#define IRQ_UNUSED 4 /* - unused interrupt */
-#define IRQ_HWERR 5 /* Hardware Error */
-#define IRQ_CORETMR 6 /* Core timer */
-
-#define BFIN_IRQ(x) ((x) + 7)
+#define NR_PERI_INTS (2 * 32)
#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */
@@ -53,21 +24,21 @@
#define IRQ_UART0_ERROR BFIN_IRQ(12) /* UART0 Status */
#define IRQ_UART1_ERROR BFIN_IRQ(13) /* UART1 Status */
#define IRQ_RTC BFIN_IRQ(14) /* RTC */
-#define IRQ_PPI BFIN_IRQ(15) /* DMA Channel 0 (PPI/NAND) */
+#define IRQ_PPI BFIN_IRQ(15) /* DMA Channel 0 (PPI/NAND) */
#define IRQ_SPORT0_RX BFIN_IRQ(16) /* DMA 3 Channel (SPORT0 RX) */
#define IRQ_SPORT0_TX BFIN_IRQ(17) /* DMA 4 Channel (SPORT0 TX) */
#define IRQ_SPORT1_RX BFIN_IRQ(18) /* DMA 5 Channel (SPORT1 RX) */
#define IRQ_SPORT1_TX BFIN_IRQ(19) /* DMA 6 Channel (SPORT1 TX) */
-#define IRQ_TWI BFIN_IRQ(20) /* TWI */
-#define IRQ_SPI BFIN_IRQ(21) /* DMA 7 Channel (SPI) */
-#define IRQ_UART0_RX BFIN_IRQ(22) /* DMA8 Channel (UART0 RX) */
-#define IRQ_UART0_TX BFIN_IRQ(23) /* DMA9 Channel (UART0 TX) */
-#define IRQ_UART1_RX BFIN_IRQ(24) /* DMA10 Channel (UART1 RX) */
-#define IRQ_UART1_TX BFIN_IRQ(25) /* DMA11 Channel (UART1 TX) */
-#define IRQ_OPTSEC BFIN_IRQ(26) /* OTPSEC Interrupt */
-#define IRQ_CNT BFIN_IRQ(27) /* GP Counter */
-#define IRQ_MAC_RX BFIN_IRQ(28) /* DMA1 Channel (MAC RX/HDMA) */
-#define IRQ_PORTH_INTA BFIN_IRQ(29) /* Port H Interrupt A */
+#define IRQ_TWI BFIN_IRQ(20) /* TWI */
+#define IRQ_SPI BFIN_IRQ(21) /* DMA 7 Channel (SPI) */
+#define IRQ_UART0_RX BFIN_IRQ(22) /* DMA8 Channel (UART0 RX) */
+#define IRQ_UART0_TX BFIN_IRQ(23) /* DMA9 Channel (UART0 TX) */
+#define IRQ_UART1_RX BFIN_IRQ(24) /* DMA10 Channel (UART1 RX) */
+#define IRQ_UART1_TX BFIN_IRQ(25) /* DMA11 Channel (UART1 TX) */
+#define IRQ_OPTSEC BFIN_IRQ(26) /* OTPSEC Interrupt */
+#define IRQ_CNT BFIN_IRQ(27) /* GP Counter */
+#define IRQ_MAC_RX BFIN_IRQ(28) /* DMA1 Channel (MAC RX/HDMA) */
+#define IRQ_PORTH_INTA BFIN_IRQ(29) /* Port H Interrupt A */
#define IRQ_MAC_TX BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */
#define IRQ_NFC BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */
#define IRQ_PORTH_INTB BFIN_IRQ(31) /* Port H Interrupt B */
@@ -96,119 +67,108 @@
#define IRQ_USB_INT2 BFIN_IRQ(54) /* USB_INT2 Interrupt */
#define IRQ_USB_DMA BFIN_IRQ(55) /* USB_DMAINT Interrupt */
-#define SYS_IRQS BFIN_IRQ(63) /* 70 */
+#define SYS_IRQS BFIN_IRQ(63) /* 70 */
-#define IRQ_PF0 71
-#define IRQ_PF1 72
-#define IRQ_PF2 73
-#define IRQ_PF3 74
-#define IRQ_PF4 75
-#define IRQ_PF5 76
-#define IRQ_PF6 77
-#define IRQ_PF7 78
-#define IRQ_PF8 79
-#define IRQ_PF9 80
-#define IRQ_PF10 81
-#define IRQ_PF11 82
-#define IRQ_PF12 83
-#define IRQ_PF13 84
-#define IRQ_PF14 85
-#define IRQ_PF15 86
+#define IRQ_PF0 71
+#define IRQ_PF1 72
+#define IRQ_PF2 73
+#define IRQ_PF3 74
+#define IRQ_PF4 75
+#define IRQ_PF5 76
+#define IRQ_PF6 77
+#define IRQ_PF7 78
+#define IRQ_PF8 79
+#define IRQ_PF9 80
+#define IRQ_PF10 81
+#define IRQ_PF11 82
+#define IRQ_PF12 83
+#define IRQ_PF13 84
+#define IRQ_PF14 85
+#define IRQ_PF15 86
-#define IRQ_PG0 87
-#define IRQ_PG1 88
-#define IRQ_PG2 89
-#define IRQ_PG3 90
-#define IRQ_PG4 91
-#define IRQ_PG5 92
-#define IRQ_PG6 93
-#define IRQ_PG7 94
-#define IRQ_PG8 95
-#define IRQ_PG9 96
-#define IRQ_PG10 97
-#define IRQ_PG11 98
-#define IRQ_PG12 99
-#define IRQ_PG13 100
-#define IRQ_PG14 101
-#define IRQ_PG15 102
+#define IRQ_PG0 87
+#define IRQ_PG1 88
+#define IRQ_PG2 89
+#define IRQ_PG3 90
+#define IRQ_PG4 91
+#define IRQ_PG5 92
+#define IRQ_PG6 93
+#define IRQ_PG7 94
+#define IRQ_PG8 95
+#define IRQ_PG9 96
+#define IRQ_PG10 97
+#define IRQ_PG11 98
+#define IRQ_PG12 99
+#define IRQ_PG13 100
+#define IRQ_PG14 101
+#define IRQ_PG15 102
-#define IRQ_PH0 103
-#define IRQ_PH1 104
-#define IRQ_PH2 105
-#define IRQ_PH3 106
-#define IRQ_PH4 107
-#define IRQ_PH5 108
-#define IRQ_PH6 109
-#define IRQ_PH7 110
-#define IRQ_PH8 111
-#define IRQ_PH9 112
-#define IRQ_PH10 113
-#define IRQ_PH11 114
-#define IRQ_PH12 115
-#define IRQ_PH13 116
-#define IRQ_PH14 117
-#define IRQ_PH15 118
+#define IRQ_PH0 103
+#define IRQ_PH1 104
+#define IRQ_PH2 105
+#define IRQ_PH3 106
+#define IRQ_PH4 107
+#define IRQ_PH5 108
+#define IRQ_PH6 109
+#define IRQ_PH7 110
+#define IRQ_PH8 111
+#define IRQ_PH9 112
+#define IRQ_PH10 113
+#define IRQ_PH11 114
+#define IRQ_PH12 115
+#define IRQ_PH13 116
+#define IRQ_PH14 117
+#define IRQ_PH15 118
-#define GPIO_IRQ_BASE IRQ_PF0
+#define GPIO_IRQ_BASE IRQ_PF0
-#define IRQ_MAC_PHYINT 119 /* PHY_INT Interrupt */
-#define IRQ_MAC_MMCINT 120 /* MMC Counter Interrupt */
-#define IRQ_MAC_RXFSINT 121 /* RX Frame-Status Interrupt */
-#define IRQ_MAC_TXFSINT 122 /* TX Frame-Status Interrupt */
-#define IRQ_MAC_WAKEDET 123 /* Wake-Up Interrupt */
-#define IRQ_MAC_RXDMAERR 124 /* RX DMA Direction Error Interrupt */
-#define IRQ_MAC_TXDMAERR 125 /* TX DMA Direction Error Interrupt */
-#define IRQ_MAC_STMDONE 126 /* Station Mgt. Transfer Done Interrupt */
+#define IRQ_MAC_PHYINT 119 /* PHY_INT Interrupt */
+#define IRQ_MAC_MMCINT 120 /* MMC Counter Interrupt */
+#define IRQ_MAC_RXFSINT 121 /* RX Frame-Status Interrupt */
+#define IRQ_MAC_TXFSINT 122 /* TX Frame-Status Interrupt */
+#define IRQ_MAC_WAKEDET 123 /* Wake-Up Interrupt */
+#define IRQ_MAC_RXDMAERR 124 /* RX DMA Direction Error Interrupt */
+#define IRQ_MAC_TXDMAERR 125 /* TX DMA Direction Error Interrupt */
+#define IRQ_MAC_STMDONE 126 /* Station Mgt. Transfer Done Interrupt */
-#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1)
-#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
-
-#define IVG7 7
-#define IVG8 8
-#define IVG9 9
-#define IVG10 10
-#define IVG11 11
-#define IVG12 12
-#define IVG13 13
-#define IVG14 14
-#define IVG15 15
+#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1)
/* IAR0 BIT FIELDS */
#define IRQ_PLL_WAKEUP_POS 0
#define IRQ_DMA0_ERROR_POS 4
-#define IRQ_DMAR0_BLK_POS 8
-#define IRQ_DMAR1_BLK_POS 12
-#define IRQ_DMAR0_OVR_POS 16
-#define IRQ_DMAR1_OVR_POS 20
-#define IRQ_PPI_ERROR_POS 24
-#define IRQ_MAC_ERROR_POS 28
+#define IRQ_DMAR0_BLK_POS 8
+#define IRQ_DMAR1_BLK_POS 12
+#define IRQ_DMAR0_OVR_POS 16
+#define IRQ_DMAR1_OVR_POS 20
+#define IRQ_PPI_ERROR_POS 24
+#define IRQ_MAC_ERROR_POS 28
/* IAR1 BIT FIELDS */
#define IRQ_SPORT0_ERROR_POS 0
#define IRQ_SPORT1_ERROR_POS 4
-#define IRQ_UART0_ERROR_POS 16
-#define IRQ_UART1_ERROR_POS 20
-#define IRQ_RTC_POS 24
-#define IRQ_PPI_POS 28
+#define IRQ_UART0_ERROR_POS 16
+#define IRQ_UART1_ERROR_POS 20
+#define IRQ_RTC_POS 24
+#define IRQ_PPI_POS 28
/* IAR2 BIT FIELDS */
#define IRQ_SPORT0_RX_POS 0
#define IRQ_SPORT0_TX_POS 4
#define IRQ_SPORT1_RX_POS 8
#define IRQ_SPORT1_TX_POS 12
-#define IRQ_TWI_POS 16
-#define IRQ_SPI_POS 20
-#define IRQ_UART0_RX_POS 24
-#define IRQ_UART0_TX_POS 28
+#define IRQ_TWI_POS 16
+#define IRQ_SPI_POS 20
+#define IRQ_UART0_RX_POS 24
+#define IRQ_UART0_TX_POS 28
/* IAR3 BIT FIELDS */
-#define IRQ_UART1_RX_POS 0
-#define IRQ_UART1_TX_POS 4
-#define IRQ_OPTSEC_POS 8
-#define IRQ_CNT_POS 12
-#define IRQ_MAC_RX_POS 16
+#define IRQ_UART1_RX_POS 0
+#define IRQ_UART1_TX_POS 4
+#define IRQ_OPTSEC_POS 8
+#define IRQ_CNT_POS 12
+#define IRQ_MAC_RX_POS 16
#define IRQ_PORTH_INTA_POS 20
-#define IRQ_MAC_TX_POS 24
+#define IRQ_MAC_TX_POS 24
#define IRQ_PORTH_INTB_POS 28
/* IAR4 BIT FIELDS */
@@ -224,21 +184,21 @@
/* IAR5 BIT FIELDS */
#define IRQ_PORTG_INTA_POS 0
#define IRQ_PORTG_INTB_POS 4
-#define IRQ_MEM_DMA0_POS 8
-#define IRQ_MEM_DMA1_POS 12
-#define IRQ_WATCH_POS 16
+#define IRQ_MEM_DMA0_POS 8
+#define IRQ_MEM_DMA1_POS 12
+#define IRQ_WATCH_POS 16
#define IRQ_PORTF_INTA_POS 20
#define IRQ_PORTF_INTB_POS 24
-#define IRQ_SPI_ERROR_POS 28
+#define IRQ_SPI_ERROR_POS 28
/* IAR6 BIT FIELDS */
-#define IRQ_NFC_ERROR_POS 0
-#define IRQ_HDMA_ERROR_POS 4
-#define IRQ_HDMA_POS 8
-#define IRQ_USB_EINT_POS 12
-#define IRQ_USB_INT0_POS 16
-#define IRQ_USB_INT1_POS 20
-#define IRQ_USB_INT2_POS 24
-#define IRQ_USB_DMA_POS 28
+#define IRQ_NFC_ERROR_POS 0
+#define IRQ_HDMA_ERROR_POS 4
+#define IRQ_HDMA_POS 8
+#define IRQ_USB_EINT_POS 12
+#define IRQ_USB_INT0_POS 16
+#define IRQ_USB_INT1_POS 20
+#define IRQ_USB_INT2_POS 24
+#define IRQ_USB_DMA_POS 28
-#endif /* _BF527_IRQ_H_ */
+#endif
diff --git a/arch/blackfin/mach-bf533/include/mach/anomaly.h b/arch/blackfin/mach-bf533/include/mach/anomaly.h
index 78f8721..72aa594 100644
--- a/arch/blackfin/mach-bf533/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf533/include/mach/anomaly.h
@@ -5,13 +5,13 @@
* and can be replaced with that version at any time
* DO NOT EDIT THIS FILE
*
- * Copyright 2004-2010 Analog Devices Inc.
+ * Copyright 2004-2011 Analog Devices Inc.
* Licensed under the ADI BSD license.
* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
*/
/* This file should be up to date with:
- * - Revision E, 09/18/2008; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
+ * - Revision F, 05/25/2010; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
*/
#ifndef _MACH_ANOMALY_H_
@@ -206,6 +206,10 @@
#define ANOMALY_05000443 (1)
/* False Hardware Error when RETI Points to Invalid Memory */
#define ANOMALY_05000461 (1)
+/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
+#define ANOMALY_05000462 (1)
+/* Boot Failure When SDRAM Control Signals Toggle Coming Out Of Reset */
+#define ANOMALY_05000471 (1)
/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
#define ANOMALY_05000473 (1)
/* Possible Lockup Condition whem Modifying PLL from External Memory */
@@ -351,12 +355,14 @@
#define ANOMALY_05000362 (1)
#define ANOMALY_05000364 (0)
#define ANOMALY_05000380 (0)
+#define ANOMALY_05000383 (0)
#define ANOMALY_05000386 (1)
#define ANOMALY_05000389 (0)
#define ANOMALY_05000412 (0)
#define ANOMALY_05000430 (0)
#define ANOMALY_05000432 (0)
#define ANOMALY_05000435 (0)
+#define ANOMALY_05000440 (0)
#define ANOMALY_05000447 (0)
#define ANOMALY_05000448 (0)
#define ANOMALY_05000456 (0)
@@ -364,6 +370,7 @@
#define ANOMALY_05000465 (0)
#define ANOMALY_05000467 (0)
#define ANOMALY_05000474 (0)
+#define ANOMALY_05000480 (0)
#define ANOMALY_05000485 (0)
#endif
diff --git a/arch/blackfin/mach-bf533/include/mach/irq.h b/arch/blackfin/mach-bf533/include/mach/irq.h
index 1f7e976..7097337 100644
--- a/arch/blackfin/mach-bf533/include/mach/irq.h
+++ b/arch/blackfin/mach-bf533/include/mach/irq.h
@@ -7,83 +7,36 @@
#ifndef _BF533_IRQ_H_
#define _BF533_IRQ_H_
-/*
- * Interrupt source definitions
- Event Source Core Event Name
-Core Emulation **
- Events (highest priority) EMU 0
- Reset RST 1
- NMI NMI 2
- Exception EVX 3
- Reserved -- 4
- Hardware Error IVHW 5
- Core Timer IVTMR 6 *
- PLL Wakeup Interrupt IVG7 7
- DMA Error (generic) IVG7 8
- PPI Error Interrupt IVG7 9
- SPORT0 Error Interrupt IVG7 10
- SPORT1 Error Interrupt IVG7 11
- SPI Error Interrupt IVG7 12
- UART Error Interrupt IVG7 13
- RTC Interrupt IVG8 14
- DMA0 Interrupt (PPI) IVG8 15
- DMA1 (SPORT0 RX) IVG9 16
- DMA2 (SPORT0 TX) IVG9 17
- DMA3 (SPORT1 RX) IVG9 18
- DMA4 (SPORT1 TX) IVG9 19
- DMA5 (PPI) IVG10 20
- DMA6 (UART RX) IVG10 21
- DMA7 (UART TX) IVG10 22
- Timer0 IVG11 23
- Timer1 IVG11 24
- Timer2 IVG11 25
- PF Interrupt A IVG12 26
- PF Interrupt B IVG12 27
- DMA8/9 Interrupt IVG13 28
- DMA10/11 Interrupt IVG13 29
- Watchdog Timer IVG13 30
+#include <mach-common/irq.h>
- Softirq IVG14 31
- System Call --
- (lowest priority) IVG15 32 *
- */
-#define SYS_IRQS 31
-#define NR_PERI_INTS 24
+#define NR_PERI_INTS 24
-/* The ABSTRACT IRQ definitions */
-/** the first seven of the following are fixed, the rest you change if you need to **/
-#define IRQ_EMU 0 /*Emulation */
-#define IRQ_RST 1 /*reset */
-#define IRQ_NMI 2 /*Non Maskable */
-#define IRQ_EVX 3 /*Exception */
-#define IRQ_UNUSED 4 /*- unused interrupt*/
-#define IRQ_HWERR 5 /*Hardware Error */
-#define IRQ_CORETMR 6 /*Core timer */
+#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
+#define IRQ_DMA_ERROR BFIN_IRQ(1) /* DMA Error (general) */
+#define IRQ_PPI_ERROR BFIN_IRQ(2) /* PPI Error Interrupt */
+#define IRQ_SPORT0_ERROR BFIN_IRQ(3) /* SPORT0 Error Interrupt */
+#define IRQ_SPORT1_ERROR BFIN_IRQ(4) /* SPORT1 Error Interrupt */
+#define IRQ_SPI_ERROR BFIN_IRQ(5) /* SPI Error Interrupt */
+#define IRQ_UART0_ERROR BFIN_IRQ(6) /* UART Error Interrupt */
+#define IRQ_RTC BFIN_IRQ(7) /* RTC Interrupt */
+#define IRQ_PPI BFIN_IRQ(8) /* DMA0 Interrupt (PPI) */
+#define IRQ_SPORT0_RX BFIN_IRQ(9) /* DMA1 Interrupt (SPORT0 RX) */
+#define IRQ_SPORT0_TX BFIN_IRQ(10) /* DMA2 Interrupt (SPORT0 TX) */
+#define IRQ_SPORT1_RX BFIN_IRQ(11) /* DMA3 Interrupt (SPORT1 RX) */
+#define IRQ_SPORT1_TX BFIN_IRQ(12) /* DMA4 Interrupt (SPORT1 TX) */
+#define IRQ_SPI BFIN_IRQ(13) /* DMA5 Interrupt (SPI) */
+#define IRQ_UART0_RX BFIN_IRQ(14) /* DMA6 Interrupt (UART RX) */
+#define IRQ_UART0_TX BFIN_IRQ(15) /* DMA7 Interrupt (UART TX) */
+#define IRQ_TIMER0 BFIN_IRQ(16) /* Timer 0 */
+#define IRQ_TIMER1 BFIN_IRQ(17) /* Timer 1 */
+#define IRQ_TIMER2 BFIN_IRQ(18) /* Timer 2 */
+#define IRQ_PROG_INTA BFIN_IRQ(19) /* Programmable Flags A (8) */
+#define IRQ_PROG_INTB BFIN_IRQ(20) /* Programmable Flags B (8) */
+#define IRQ_MEM_DMA0 BFIN_IRQ(21) /* DMA8/9 Interrupt (Memory DMA Stream 0) */
+#define IRQ_MEM_DMA1 BFIN_IRQ(22) /* DMA10/11 Interrupt (Memory DMA Stream 1) */
+#define IRQ_WATCH BFIN_IRQ(23) /* Watch Dog Timer */
-#define IRQ_PLL_WAKEUP 7 /*PLL Wakeup Interrupt */
-#define IRQ_DMA_ERROR 8 /*DMA Error (general) */
-#define IRQ_PPI_ERROR 9 /*PPI Error Interrupt */
-#define IRQ_SPORT0_ERROR 10 /*SPORT0 Error Interrupt */
-#define IRQ_SPORT1_ERROR 11 /*SPORT1 Error Interrupt */
-#define IRQ_SPI_ERROR 12 /*SPI Error Interrupt */
-#define IRQ_UART0_ERROR 13 /*UART Error Interrupt */
-#define IRQ_RTC 14 /*RTC Interrupt */
-#define IRQ_PPI 15 /*DMA0 Interrupt (PPI) */
-#define IRQ_SPORT0_RX 16 /*DMA1 Interrupt (SPORT0 RX) */
-#define IRQ_SPORT0_TX 17 /*DMA2 Interrupt (SPORT0 TX) */
-#define IRQ_SPORT1_RX 18 /*DMA3 Interrupt (SPORT1 RX) */
-#define IRQ_SPORT1_TX 19 /*DMA4 Interrupt (SPORT1 TX) */
-#define IRQ_SPI 20 /*DMA5 Interrupt (SPI) */
-#define IRQ_UART0_RX 21 /*DMA6 Interrupt (UART RX) */
-#define IRQ_UART0_TX 22 /*DMA7 Interrupt (UART TX) */
-#define IRQ_TIMER0 23 /*Timer 0 */
-#define IRQ_TIMER1 24 /*Timer 1 */
-#define IRQ_TIMER2 25 /*Timer 2 */
-#define IRQ_PROG_INTA 26 /*Programmable Flags A (8) */
-#define IRQ_PROG_INTB 27 /*Programmable Flags B (8) */
-#define IRQ_MEM_DMA0 28 /*DMA8/9 Interrupt (Memory DMA Stream 0) */
-#define IRQ_MEM_DMA1 29 /*DMA10/11 Interrupt (Memory DMA Stream 1) */
-#define IRQ_WATCH 30 /*Watch Dog Timer */
+#define SYS_IRQS 31
#define IRQ_PF0 33
#define IRQ_PF1 34
@@ -105,46 +58,35 @@
#define GPIO_IRQ_BASE IRQ_PF0
#define NR_MACH_IRQS (IRQ_PF15 + 1)
-#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
-#define IVG7 7
-#define IVG8 8
-#define IVG9 9
-#define IVG10 10
-#define IVG11 11
-#define IVG12 12
-#define IVG13 13
-#define IVG14 14
-#define IVG15 15
+/* IAR0 BIT FIELDS */
+#define RTC_ERROR_POS 28
+#define UART_ERROR_POS 24
+#define SPORT1_ERROR_POS 20
+#define SPI_ERROR_POS 16
+#define SPORT0_ERROR_POS 12
+#define PPI_ERROR_POS 8
+#define DMA_ERROR_POS 4
+#define PLLWAKE_ERROR_POS 0
-/* IAR0 BIT FIELDS*/
-#define RTC_ERROR_POS 28
-#define UART_ERROR_POS 24
-#define SPORT1_ERROR_POS 20
-#define SPI_ERROR_POS 16
-#define SPORT0_ERROR_POS 12
-#define PPI_ERROR_POS 8
-#define DMA_ERROR_POS 4
-#define PLLWAKE_ERROR_POS 0
+/* IAR1 BIT FIELDS */
+#define DMA7_UARTTX_POS 28
+#define DMA6_UARTRX_POS 24
+#define DMA5_SPI_POS 20
+#define DMA4_SPORT1TX_POS 16
+#define DMA3_SPORT1RX_POS 12
+#define DMA2_SPORT0TX_POS 8
+#define DMA1_SPORT0RX_POS 4
+#define DMA0_PPI_POS 0
-/* IAR1 BIT FIELDS*/
-#define DMA7_UARTTX_POS 28
-#define DMA6_UARTRX_POS 24
-#define DMA5_SPI_POS 20
-#define DMA4_SPORT1TX_POS 16
-#define DMA3_SPORT1RX_POS 12
-#define DMA2_SPORT0TX_POS 8
-#define DMA1_SPORT0RX_POS 4
-#define DMA0_PPI_POS 0
+/* IAR2 BIT FIELDS */
+#define WDTIMER_POS 28
+#define MEMDMA1_POS 24
+#define MEMDMA0_POS 20
+#define PFB_POS 16
+#define PFA_POS 12
+#define TIMER2_POS 8
+#define TIMER1_POS 4
+#define TIMER0_POS 0
-/* IAR2 BIT FIELDS*/
-#define WDTIMER_POS 28
-#define MEMDMA1_POS 24
-#define MEMDMA0_POS 20
-#define PFB_POS 16
-#define PFA_POS 12
-#define TIMER2_POS 8
-#define TIMER1_POS 4
-#define TIMER0_POS 0
-
-#endif /* _BF533_IRQ_H_ */
+#endif
diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c
index 3fa3354..e16dc45 100644
--- a/arch/blackfin/mach-bf537/boards/stamp.c
+++ b/arch/blackfin/mach-bf537/boards/stamp.c
@@ -35,6 +35,7 @@
#include <asm/reboot.h>
#include <asm/portmux.h>
#include <asm/dpmc.h>
+#include <asm/bfin_sport.h>
#ifdef CONFIG_REGULATOR_FIXED_VOLTAGE
#include <linux/regulator/fixed.h>
#endif
@@ -2585,27 +2586,103 @@
},
};
-#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
+#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) || \
+ defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) || \
+ defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
+
+#define SPORT_REQ(x) \
+ [x] = {P_SPORT##x##_TFS, P_SPORT##x##_DTPRI, P_SPORT##x##_TSCLK, \
+ P_SPORT##x##_RFS, P_SPORT##x##_DRPRI, P_SPORT##x##_RSCLK, 0}
+
+static const u16 bfin_snd_pin[][7] = {
+ SPORT_REQ(0),
+ SPORT_REQ(1),
+};
+
+static struct bfin_snd_platform_data bfin_snd_data[] = {
+ {
+ .pin_req = &bfin_snd_pin[0][0],
+ },
+ {
+ .pin_req = &bfin_snd_pin[1][0],
+ },
+};
+
+#define BFIN_SND_RES(x) \
+ [x] = { \
+ { \
+ .start = SPORT##x##_TCR1, \
+ .end = SPORT##x##_TCR1, \
+ .flags = IORESOURCE_MEM \
+ }, \
+ { \
+ .start = CH_SPORT##x##_RX, \
+ .end = CH_SPORT##x##_RX, \
+ .flags = IORESOURCE_DMA, \
+ }, \
+ { \
+ .start = CH_SPORT##x##_TX, \
+ .end = CH_SPORT##x##_TX, \
+ .flags = IORESOURCE_DMA, \
+ }, \
+ { \
+ .start = IRQ_SPORT##x##_ERROR, \
+ .end = IRQ_SPORT##x##_ERROR, \
+ .flags = IORESOURCE_IRQ, \
+ } \
+ }
+
+static struct resource bfin_snd_resources[][4] = {
+ BFIN_SND_RES(0),
+ BFIN_SND_RES(1),
+};
+
+static struct platform_device bfin_pcm = {
+ .name = "bfin-pcm-audio",
+ .id = -1,
+};
+#endif
+
+#if defined(CONFIG_SND_BF5XX_SOC_AD73311) || defined(CONFIG_SND_BF5XX_SOC_AD73311_MODULE)
+static struct platform_device bfin_ad73311_codec_device = {
+ .name = "ad73311",
+ .id = -1,
+};
+#endif
+
+#if defined(CONFIG_SND_BF5XX_SOC_I2S) || defined(CONFIG_SND_BF5XX_SOC_I2S_MODULE)
static struct platform_device bfin_i2s = {
.name = "bfin-i2s",
.id = CONFIG_SND_BF5XX_SPORT_NUM,
- /* TODO: add platform data here */
+ .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
+ .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
+ .dev = {
+ .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
+ },
};
#endif
-#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
+#if defined(CONFIG_SND_BF5XX_SOC_TDM) || defined(CONFIG_SND_BF5XX_SOC_TDM_MODULE)
static struct platform_device bfin_tdm = {
.name = "bfin-tdm",
.id = CONFIG_SND_BF5XX_SPORT_NUM,
- /* TODO: add platform data here */
+ .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
+ .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
+ .dev = {
+ .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
+ },
};
#endif
-#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
+#if defined(CONFIG_SND_BF5XX_SOC_AC97) || defined(CONFIG_SND_BF5XX_SOC_AC97_MODULE)
static struct platform_device bfin_ac97 = {
.name = "bfin-ac97",
.id = CONFIG_SND_BF5XX_SPORT_NUM,
- /* TODO: add platform data here */
+ .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
+ .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
+ .dev = {
+ .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
+ },
};
#endif
@@ -2796,17 +2873,28 @@
&stamp_flash_device,
#endif
-#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
+#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) || \
+ defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) || \
+ defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
+ &bfin_pcm,
+#endif
+
+#if defined(CONFIG_SND_BF5XX_SOC_AD73311) || defined(CONFIG_SND_BF5XX_SOC_AD73311_MODULE)
+ &bfin_ad73311_codec_device,
+#endif
+
+#if defined(CONFIG_SND_BF5XX_SOC_I2S) || defined(CONFIG_SND_BF5XX_SOC_I2S_MODULE)
&bfin_i2s,
#endif
-#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
+#if defined(CONFIG_SND_BF5XX_SOC_TDM) || defined(CONFIG_SND_BF5XX_SOC_TDM_MODULE)
&bfin_tdm,
#endif
-#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
+#if defined(CONFIG_SND_BF5XX_SOC_AC97) || defined(CONFIG_SND_BF5XX_SOC_AC97_MODULE)
&bfin_ac97,
#endif
+
#if defined(CONFIG_REGULATOR_AD5398) || defined(CONFIG_REGULATOR_AD5398_MODULE)
#if defined(CONFIG_REGULATOR_VIRTUAL_CONSUMER) || \
defined(CONFIG_REGULATOR_VIRTUAL_CONSUMER_MODULE)
diff --git a/arch/blackfin/mach-bf537/include/mach/anomaly.h b/arch/blackfin/mach-bf537/include/mach/anomaly.h
index 43df6af..7f8e5a9 100644
--- a/arch/blackfin/mach-bf537/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf537/include/mach/anomaly.h
@@ -5,13 +5,13 @@
* and can be replaced with that version at any time
* DO NOT EDIT THIS FILE
*
- * Copyright 2004-2010 Analog Devices Inc.
+ * Copyright 2004-2011 Analog Devices Inc.
* Licensed under the ADI BSD license.
* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
*/
/* This file should be up to date with:
- * - Revision D, 09/18/2008; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
+ * - Revision E, 05/25/2010; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
*/
#ifndef _MACH_ANOMALY_H_
@@ -160,12 +160,16 @@
#define ANOMALY_05000443 (1)
/* False Hardware Error when RETI Points to Invalid Memory */
#define ANOMALY_05000461 (1)
+/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
+#define ANOMALY_05000462 (1)
/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
#define ANOMALY_05000473 (1)
/* Possible Lockup Condition whem Modifying PLL from External Memory */
#define ANOMALY_05000475 (1)
/* TESTSET Instruction Cannot Be Interrupted */
#define ANOMALY_05000477 (1)
+/* Multiple Simultaneous Urgent DMA Requests May Cause DMA System Instability */
+#define ANOMALY_05000480 (__SILICON_REVISION__ < 3)
/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
#define ANOMALY_05000481 (1)
/* IFLUSH sucks at life */
@@ -204,6 +208,7 @@
#define ANOMALY_05000363 (0)
#define ANOMALY_05000364 (0)
#define ANOMALY_05000380 (0)
+#define ANOMALY_05000383 (0)
#define ANOMALY_05000386 (1)
#define ANOMALY_05000389 (0)
#define ANOMALY_05000400 (0)
@@ -211,6 +216,7 @@
#define ANOMALY_05000430 (0)
#define ANOMALY_05000432 (0)
#define ANOMALY_05000435 (0)
+#define ANOMALY_05000440 (0)
#define ANOMALY_05000447 (0)
#define ANOMALY_05000448 (0)
#define ANOMALY_05000456 (0)
diff --git a/arch/blackfin/mach-bf537/include/mach/irq.h b/arch/blackfin/mach-bf537/include/mach/irq.h
index 1a6d617..b6ed823 100644
--- a/arch/blackfin/mach-bf537/include/mach/irq.h
+++ b/arch/blackfin/mach-bf537/include/mach/irq.h
@@ -7,193 +7,178 @@
#ifndef _BF537_IRQ_H_
#define _BF537_IRQ_H_
-/*
- * Interrupt source definitions
- * Event Source Core Event Name
- * Core Emulation **
- * Events (highest priority) EMU 0
- * Reset RST 1
- * NMI NMI 2
- * Exception EVX 3
- * Reserved -- 4
- * Hardware Error IVHW 5
- * Core Timer IVTMR 6
- * .....
- *
- * Softirq IVG14
- * System Call --
- * (lowest priority) IVG15
- */
+#include <mach-common/irq.h>
-#define SYS_IRQS 39
-#define NR_PERI_INTS 32
+#define NR_PERI_INTS 32
-/* The ABSTRACT IRQ definitions */
-/** the first seven of the following are fixed, the rest you change if you need to **/
-#define IRQ_EMU 0 /*Emulation */
-#define IRQ_RST 1 /*reset */
-#define IRQ_NMI 2 /*Non Maskable */
-#define IRQ_EVX 3 /*Exception */
-#define IRQ_UNUSED 4 /*- unused interrupt*/
-#define IRQ_HWERR 5 /*Hardware Error */
-#define IRQ_CORETMR 6 /*Core timer */
+#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
+#define IRQ_DMA_ERROR BFIN_IRQ(1) /* DMA Error (general) */
+#define IRQ_GENERIC_ERROR BFIN_IRQ(2) /* GENERIC Error Interrupt */
+#define IRQ_RTC BFIN_IRQ(3) /* RTC Interrupt */
+#define IRQ_PPI BFIN_IRQ(4) /* DMA0 Interrupt (PPI) */
+#define IRQ_SPORT0_RX BFIN_IRQ(5) /* DMA3 Interrupt (SPORT0 RX) */
+#define IRQ_SPORT0_TX BFIN_IRQ(6) /* DMA4 Interrupt (SPORT0 TX) */
+#define IRQ_SPORT1_RX BFIN_IRQ(7) /* DMA5 Interrupt (SPORT1 RX) */
+#define IRQ_SPORT1_TX BFIN_IRQ(8) /* DMA6 Interrupt (SPORT1 TX) */
+#define IRQ_TWI BFIN_IRQ(9) /* TWI Interrupt */
+#define IRQ_SPI BFIN_IRQ(10) /* DMA7 Interrupt (SPI) */
+#define IRQ_UART0_RX BFIN_IRQ(11) /* DMA8 Interrupt (UART0 RX) */
+#define IRQ_UART0_TX BFIN_IRQ(12) /* DMA9 Interrupt (UART0 TX) */
+#define IRQ_UART1_RX BFIN_IRQ(13) /* DMA10 Interrupt (UART1 RX) */
+#define IRQ_UART1_TX BFIN_IRQ(14) /* DMA11 Interrupt (UART1 TX) */
+#define IRQ_CAN_RX BFIN_IRQ(15) /* CAN Receive Interrupt */
+#define IRQ_CAN_TX BFIN_IRQ(16) /* CAN Transmit Interrupt */
+#define IRQ_PH_INTA_MAC_RX BFIN_IRQ(17) /* Port H Interrupt A & DMA1 Interrupt (Ethernet RX) */
+#define IRQ_PH_INTB_MAC_TX BFIN_IRQ(18) /* Port H Interrupt B & DMA2 Interrupt (Ethernet TX) */
+#define IRQ_TIMER0 BFIN_IRQ(19) /* Timer 0 */
+#define IRQ_TIMER1 BFIN_IRQ(20) /* Timer 1 */
+#define IRQ_TIMER2 BFIN_IRQ(21) /* Timer 2 */
+#define IRQ_TIMER3 BFIN_IRQ(22) /* Timer 3 */
+#define IRQ_TIMER4 BFIN_IRQ(23) /* Timer 4 */
+#define IRQ_TIMER5 BFIN_IRQ(24) /* Timer 5 */
+#define IRQ_TIMER6 BFIN_IRQ(25) /* Timer 6 */
+#define IRQ_TIMER7 BFIN_IRQ(26) /* Timer 7 */
+#define IRQ_PF_INTA_PG_INTA BFIN_IRQ(27) /* Ports F&G Interrupt A */
+#define IRQ_PORTG_INTB BFIN_IRQ(28) /* Port G Interrupt B */
+#define IRQ_MEM_DMA0 BFIN_IRQ(29) /* (Memory DMA Stream 0) */
+#define IRQ_MEM_DMA1 BFIN_IRQ(30) /* (Memory DMA Stream 1) */
+#define IRQ_PF_INTB_WATCH BFIN_IRQ(31) /* Watchdog & Port F Interrupt B */
-#define IRQ_PLL_WAKEUP 7 /*PLL Wakeup Interrupt */
-#define IRQ_DMA_ERROR 8 /*DMA Error (general) */
-#define IRQ_GENERIC_ERROR 9 /*GENERIC Error Interrupt */
-#define IRQ_RTC 10 /*RTC Interrupt */
-#define IRQ_PPI 11 /*DMA0 Interrupt (PPI) */
-#define IRQ_SPORT0_RX 12 /*DMA3 Interrupt (SPORT0 RX) */
-#define IRQ_SPORT0_TX 13 /*DMA4 Interrupt (SPORT0 TX) */
-#define IRQ_SPORT1_RX 14 /*DMA5 Interrupt (SPORT1 RX) */
-#define IRQ_SPORT1_TX 15 /*DMA6 Interrupt (SPORT1 TX) */
-#define IRQ_TWI 16 /*TWI Interrupt */
-#define IRQ_SPI 17 /*DMA7 Interrupt (SPI) */
-#define IRQ_UART0_RX 18 /*DMA8 Interrupt (UART0 RX) */
-#define IRQ_UART0_TX 19 /*DMA9 Interrupt (UART0 TX) */
-#define IRQ_UART1_RX 20 /*DMA10 Interrupt (UART1 RX) */
-#define IRQ_UART1_TX 21 /*DMA11 Interrupt (UART1 TX) */
-#define IRQ_CAN_RX 22 /*CAN Receive Interrupt */
-#define IRQ_CAN_TX 23 /*CAN Transmit Interrupt */
-#define IRQ_MAC_RX 24 /*DMA1 (Ethernet RX) Interrupt */
-#define IRQ_MAC_TX 25 /*DMA2 (Ethernet TX) Interrupt */
-#define IRQ_TIMER0 26 /*Timer 0 */
-#define IRQ_TIMER1 27 /*Timer 1 */
-#define IRQ_TIMER2 28 /*Timer 2 */
-#define IRQ_TIMER3 29 /*Timer 3 */
-#define IRQ_TIMER4 30 /*Timer 4 */
-#define IRQ_TIMER5 31 /*Timer 5 */
-#define IRQ_TIMER6 32 /*Timer 6 */
-#define IRQ_TIMER7 33 /*Timer 7 */
-#define IRQ_PROG_INTA 34 /* PF Ports F&G (PF15:0) Interrupt A */
-#define IRQ_PORTG_INTB 35 /* PF Port G (PF15:0) Interrupt B */
-#define IRQ_MEM_DMA0 36 /*(Memory DMA Stream 0) */
-#define IRQ_MEM_DMA1 37 /*(Memory DMA Stream 1) */
-#define IRQ_PROG_INTB 38 /* PF Ports F (PF15:0) Interrupt B */
-#define IRQ_WATCH 38 /*Watch Dog Timer */
+#define SYS_IRQS 39
-#define IRQ_PPI_ERROR 42 /*PPI Error Interrupt */
-#define IRQ_CAN_ERROR 43 /*CAN Error Interrupt */
-#define IRQ_MAC_ERROR 44 /*MAC Status/Error Interrupt */
-#define IRQ_SPORT0_ERROR 45 /*SPORT0 Error Interrupt */
-#define IRQ_SPORT1_ERROR 46 /*SPORT1 Error Interrupt */
-#define IRQ_SPI_ERROR 47 /*SPI Error Interrupt */
-#define IRQ_UART0_ERROR 48 /*UART Error Interrupt */
-#define IRQ_UART1_ERROR 49 /*UART Error Interrupt */
+#define IRQ_PPI_ERROR 42 /* PPI Error Interrupt */
+#define IRQ_CAN_ERROR 43 /* CAN Error Interrupt */
+#define IRQ_MAC_ERROR 44 /* MAC Status/Error Interrupt */
+#define IRQ_SPORT0_ERROR 45 /* SPORT0 Error Interrupt */
+#define IRQ_SPORT1_ERROR 46 /* SPORT1 Error Interrupt */
+#define IRQ_SPI_ERROR 47 /* SPI Error Interrupt */
+#define IRQ_UART0_ERROR 48 /* UART Error Interrupt */
+#define IRQ_UART1_ERROR 49 /* UART Error Interrupt */
-#define IRQ_PF0 50
-#define IRQ_PF1 51
-#define IRQ_PF2 52
-#define IRQ_PF3 53
-#define IRQ_PF4 54
-#define IRQ_PF5 55
-#define IRQ_PF6 56
-#define IRQ_PF7 57
-#define IRQ_PF8 58
-#define IRQ_PF9 59
-#define IRQ_PF10 60
-#define IRQ_PF11 61
-#define IRQ_PF12 62
-#define IRQ_PF13 63
-#define IRQ_PF14 64
-#define IRQ_PF15 65
+#define IRQ_PF0 50
+#define IRQ_PF1 51
+#define IRQ_PF2 52
+#define IRQ_PF3 53
+#define IRQ_PF4 54
+#define IRQ_PF5 55
+#define IRQ_PF6 56
+#define IRQ_PF7 57
+#define IRQ_PF8 58
+#define IRQ_PF9 59
+#define IRQ_PF10 60
+#define IRQ_PF11 61
+#define IRQ_PF12 62
+#define IRQ_PF13 63
+#define IRQ_PF14 64
+#define IRQ_PF15 65
-#define IRQ_PG0 66
-#define IRQ_PG1 67
-#define IRQ_PG2 68
-#define IRQ_PG3 69
-#define IRQ_PG4 70
-#define IRQ_PG5 71
-#define IRQ_PG6 72
-#define IRQ_PG7 73
-#define IRQ_PG8 74
-#define IRQ_PG9 75
-#define IRQ_PG10 76
-#define IRQ_PG11 77
-#define IRQ_PG12 78
-#define IRQ_PG13 79
-#define IRQ_PG14 80
-#define IRQ_PG15 81
+#define IRQ_PG0 66
+#define IRQ_PG1 67
+#define IRQ_PG2 68
+#define IRQ_PG3 69
+#define IRQ_PG4 70
+#define IRQ_PG5 71
+#define IRQ_PG6 72
+#define IRQ_PG7 73
+#define IRQ_PG8 74
+#define IRQ_PG9 75
+#define IRQ_PG10 76
+#define IRQ_PG11 77
+#define IRQ_PG12 78
+#define IRQ_PG13 79
+#define IRQ_PG14 80
+#define IRQ_PG15 81
-#define IRQ_PH0 82
-#define IRQ_PH1 83
-#define IRQ_PH2 84
-#define IRQ_PH3 85
-#define IRQ_PH4 86
-#define IRQ_PH5 87
-#define IRQ_PH6 88
-#define IRQ_PH7 89
-#define IRQ_PH8 90
-#define IRQ_PH9 91
-#define IRQ_PH10 92
-#define IRQ_PH11 93
-#define IRQ_PH12 94
-#define IRQ_PH13 95
-#define IRQ_PH14 96
-#define IRQ_PH15 97
+#define IRQ_PH0 82
+#define IRQ_PH1 83
+#define IRQ_PH2 84
+#define IRQ_PH3 85
+#define IRQ_PH4 86
+#define IRQ_PH5 87
+#define IRQ_PH6 88
+#define IRQ_PH7 89
+#define IRQ_PH8 90
+#define IRQ_PH9 91
+#define IRQ_PH10 92
+#define IRQ_PH11 93
+#define IRQ_PH12 94
+#define IRQ_PH13 95
+#define IRQ_PH14 96
+#define IRQ_PH15 97
-#define GPIO_IRQ_BASE IRQ_PF0
+#define GPIO_IRQ_BASE IRQ_PF0
-#define IRQ_MAC_PHYINT 98 /* PHY_INT Interrupt */
-#define IRQ_MAC_MMCINT 99 /* MMC Counter Interrupt */
-#define IRQ_MAC_RXFSINT 100 /* RX Frame-Status Interrupt */
-#define IRQ_MAC_TXFSINT 101 /* TX Frame-Status Interrupt */
-#define IRQ_MAC_WAKEDET 102 /* Wake-Up Interrupt */
-#define IRQ_MAC_RXDMAERR 103 /* RX DMA Direction Error Interrupt */
-#define IRQ_MAC_TXDMAERR 104 /* TX DMA Direction Error Interrupt */
-#define IRQ_MAC_STMDONE 105 /* Station Mgt. Transfer Done Interrupt */
+#define IRQ_MAC_PHYINT 98 /* PHY_INT Interrupt */
+#define IRQ_MAC_MMCINT 99 /* MMC Counter Interrupt */
+#define IRQ_MAC_RXFSINT 100 /* RX Frame-Status Interrupt */
+#define IRQ_MAC_TXFSINT 101 /* TX Frame-Status Interrupt */
+#define IRQ_MAC_WAKEDET 102 /* Wake-Up Interrupt */
+#define IRQ_MAC_RXDMAERR 103 /* RX DMA Direction Error Interrupt */
+#define IRQ_MAC_TXDMAERR 104 /* TX DMA Direction Error Interrupt */
+#define IRQ_MAC_STMDONE 105 /* Station Mgt. Transfer Done Interrupt */
-#define NR_MACH_IRQS (IRQ_MAC_STMDONE + 1)
-#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
+#define IRQ_MAC_RX 106 /* DMA1 Interrupt (Ethernet RX) */
+#define IRQ_PORTH_INTA 107 /* Port H Interrupt A */
-#define IVG7 7
-#define IVG8 8
-#define IVG9 9
-#define IVG10 10
-#define IVG11 11
-#define IVG12 12
-#define IVG13 13
-#define IVG14 14
-#define IVG15 15
+#if 0 /* No Interrupt B support (yet) */
+#define IRQ_MAC_TX 108 /* DMA2 Interrupt (Ethernet TX) */
+#define IRQ_PORTH_INTB 109 /* Port H Interrupt B */
+#else
+#define IRQ_MAC_TX IRQ_PH_INTB_MAC_TX
+#endif
-/* IAR0 BIT FIELDS*/
-#define IRQ_PLL_WAKEUP_POS 0
-#define IRQ_DMA_ERROR_POS 4
-#define IRQ_ERROR_POS 8
-#define IRQ_RTC_POS 12
-#define IRQ_PPI_POS 16
-#define IRQ_SPORT0_RX_POS 20
-#define IRQ_SPORT0_TX_POS 24
-#define IRQ_SPORT1_RX_POS 28
+#define IRQ_PORTF_INTA 110 /* Port F Interrupt A */
+#define IRQ_PORTG_INTA 111 /* Port G Interrupt A */
-/* IAR1 BIT FIELDS*/
-#define IRQ_SPORT1_TX_POS 0
-#define IRQ_TWI_POS 4
-#define IRQ_SPI_POS 8
-#define IRQ_UART0_RX_POS 12
-#define IRQ_UART0_TX_POS 16
-#define IRQ_UART1_RX_POS 20
-#define IRQ_UART1_TX_POS 24
-#define IRQ_CAN_RX_POS 28
+#if 0 /* No Interrupt B support (yet) */
+#define IRQ_WATCH 112 /* Watchdog Timer */
+#define IRQ_PORTF_INTB 113 /* Port F Interrupt B */
+#else
+#define IRQ_WATCH IRQ_PF_INTB_WATCH
+#endif
-/* IAR2 BIT FIELDS*/
-#define IRQ_CAN_TX_POS 0
-#define IRQ_MAC_RX_POS 4
-#define IRQ_MAC_TX_POS 8
-#define IRQ_TIMER0_POS 12
-#define IRQ_TIMER1_POS 16
-#define IRQ_TIMER2_POS 20
-#define IRQ_TIMER3_POS 24
-#define IRQ_TIMER4_POS 28
+#define NR_MACH_IRQS (113 + 1)
-/* IAR3 BIT FIELDS*/
-#define IRQ_TIMER5_POS 0
-#define IRQ_TIMER6_POS 4
-#define IRQ_TIMER7_POS 8
-#define IRQ_PROG_INTA_POS 12
-#define IRQ_PORTG_INTB_POS 16
-#define IRQ_MEM_DMA0_POS 20
-#define IRQ_MEM_DMA1_POS 24
-#define IRQ_WATCH_POS 28
+/* IAR0 BIT FIELDS */
+#define IRQ_PLL_WAKEUP_POS 0
+#define IRQ_DMA_ERROR_POS 4
+#define IRQ_ERROR_POS 8
+#define IRQ_RTC_POS 12
+#define IRQ_PPI_POS 16
+#define IRQ_SPORT0_RX_POS 20
+#define IRQ_SPORT0_TX_POS 24
+#define IRQ_SPORT1_RX_POS 28
-#endif /* _BF537_IRQ_H_ */
+/* IAR1 BIT FIELDS */
+#define IRQ_SPORT1_TX_POS 0
+#define IRQ_TWI_POS 4
+#define IRQ_SPI_POS 8
+#define IRQ_UART0_RX_POS 12
+#define IRQ_UART0_TX_POS 16
+#define IRQ_UART1_RX_POS 20
+#define IRQ_UART1_TX_POS 24
+#define IRQ_CAN_RX_POS 28
+
+/* IAR2 BIT FIELDS */
+#define IRQ_CAN_TX_POS 0
+#define IRQ_MAC_RX_POS 4
+#define IRQ_MAC_TX_POS 8
+#define IRQ_TIMER0_POS 12
+#define IRQ_TIMER1_POS 16
+#define IRQ_TIMER2_POS 20
+#define IRQ_TIMER3_POS 24
+#define IRQ_TIMER4_POS 28
+
+/* IAR3 BIT FIELDS */
+#define IRQ_TIMER5_POS 0
+#define IRQ_TIMER6_POS 4
+#define IRQ_TIMER7_POS 8
+#define IRQ_PROG_INTA_POS 12
+#define IRQ_PORTG_INTB_POS 16
+#define IRQ_MEM_DMA0_POS 20
+#define IRQ_MEM_DMA1_POS 24
+#define IRQ_WATCH_POS 28
+
+#define init_mach_irq init_mach_irq
+
+#endif
diff --git a/arch/blackfin/mach-bf537/ints-priority.c b/arch/blackfin/mach-bf537/ints-priority.c
index f650062..2137a20 100644
--- a/arch/blackfin/mach-bf537/ints-priority.c
+++ b/arch/blackfin/mach-bf537/ints-priority.c
@@ -10,6 +10,13 @@
#include <linux/irq.h>
#include <asm/blackfin.h>
+#include <asm/irq_handler.h>
+#include <asm/bfin5xx_spi.h>
+#include <asm/bfin_sport.h>
+#include <asm/bfin_can.h>
+#include <asm/bfin_dma.h>
+#include <asm/dpmc.h>
+
void __init program_IAR(void)
{
/* Program the IAR0 Register with the configured priority */
@@ -51,3 +58,159 @@
SSYNC();
}
+
+#define SPI_ERR_MASK (BIT_STAT_TXCOL | BIT_STAT_RBSY | BIT_STAT_MODF | BIT_STAT_TXE) /* SPI_STAT */
+#define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF) /* SPORT_STAT */
+#define PPI_ERR_MASK (0xFFFF & ~FLD) /* PPI_STATUS */
+#define EMAC_ERR_MASK (PHYINT | MMCINT | RXFSINT | TXFSINT | WAKEDET | RXDMAERR | TXDMAERR | STMDONE) /* EMAC_SYSTAT */
+#define UART_ERR_MASK (0x6) /* UART_IIR */
+#define CAN_ERR_MASK (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | RMLIF | UCEIF | EXTIF | ADIF) /* CAN_GIF */
+
+static int error_int_mask;
+
+static void bf537_generic_error_mask_irq(struct irq_data *d)
+{
+ error_int_mask &= ~(1L << (d->irq - IRQ_PPI_ERROR));
+ if (!error_int_mask)
+ bfin_internal_mask_irq(IRQ_GENERIC_ERROR);
+}
+
+static void bf537_generic_error_unmask_irq(struct irq_data *d)
+{
+ bfin_internal_unmask_irq(IRQ_GENERIC_ERROR);
+ error_int_mask |= 1L << (d->irq - IRQ_PPI_ERROR);
+}
+
+static struct irq_chip bf537_generic_error_irqchip = {
+ .name = "ERROR",
+ .irq_ack = bfin_ack_noop,
+ .irq_mask_ack = bf537_generic_error_mask_irq,
+ .irq_mask = bf537_generic_error_mask_irq,
+ .irq_unmask = bf537_generic_error_unmask_irq,
+};
+
+static void bf537_demux_error_irq(unsigned int int_err_irq,
+ struct irq_desc *inta_desc)
+{
+ int irq = 0;
+
+#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
+ if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK)
+ irq = IRQ_MAC_ERROR;
+ else
+#endif
+ if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK)
+ irq = IRQ_SPORT0_ERROR;
+ else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK)
+ irq = IRQ_SPORT1_ERROR;
+ else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK)
+ irq = IRQ_PPI_ERROR;
+ else if (bfin_read_CAN_GIF() & CAN_ERR_MASK)
+ irq = IRQ_CAN_ERROR;
+ else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
+ irq = IRQ_SPI_ERROR;
+ else if ((bfin_read_UART0_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
+ irq = IRQ_UART0_ERROR;
+ else if ((bfin_read_UART1_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
+ irq = IRQ_UART1_ERROR;
+
+ if (irq) {
+ if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR)))
+ bfin_handle_irq(irq);
+ else {
+
+ switch (irq) {
+ case IRQ_PPI_ERROR:
+ bfin_write_PPI_STATUS(PPI_ERR_MASK);
+ break;
+#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
+ case IRQ_MAC_ERROR:
+ bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK);
+ break;
+#endif
+ case IRQ_SPORT0_ERROR:
+ bfin_write_SPORT0_STAT(SPORT_ERR_MASK);
+ break;
+
+ case IRQ_SPORT1_ERROR:
+ bfin_write_SPORT1_STAT(SPORT_ERR_MASK);
+ break;
+
+ case IRQ_CAN_ERROR:
+ bfin_write_CAN_GIS(CAN_ERR_MASK);
+ break;
+
+ case IRQ_SPI_ERROR:
+ bfin_write_SPI_STAT(SPI_ERR_MASK);
+ break;
+
+ default:
+ break;
+ }
+
+ pr_debug("IRQ %d:"
+ " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
+ irq);
+ }
+ } else
+ pr_err("%s: IRQ ?: PERIPHERAL ERROR INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
+ __func__);
+
+}
+
+#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
+static int mac_rx_int_mask;
+
+static void bf537_mac_rx_mask_irq(struct irq_data *d)
+{
+ mac_rx_int_mask &= ~(1L << (d->irq - IRQ_MAC_RX));
+ if (!mac_rx_int_mask)
+ bfin_internal_mask_irq(IRQ_PH_INTA_MAC_RX);
+}
+
+static void bf537_mac_rx_unmask_irq(struct irq_data *d)
+{
+ bfin_internal_unmask_irq(IRQ_PH_INTA_MAC_RX);
+ mac_rx_int_mask |= 1L << (d->irq - IRQ_MAC_RX);
+}
+
+static struct irq_chip bf537_mac_rx_irqchip = {
+ .name = "ERROR",
+ .irq_ack = bfin_ack_noop,
+ .irq_mask_ack = bf537_mac_rx_mask_irq,
+ .irq_mask = bf537_mac_rx_mask_irq,
+ .irq_unmask = bf537_mac_rx_unmask_irq,
+};
+
+static void bf537_demux_mac_rx_irq(unsigned int int_irq,
+ struct irq_desc *desc)
+{
+ if (bfin_read_DMA1_IRQ_STATUS() & (DMA_DONE | DMA_ERR))
+ bfin_handle_irq(IRQ_MAC_RX);
+ else
+ bfin_demux_gpio_irq(int_irq, desc);
+}
+#endif
+
+void __init init_mach_irq(void)
+{
+ int irq;
+
+#if defined(CONFIG_BF537) || defined(CONFIG_BF536)
+ /* Clear EMAC Interrupt Status bits so we can demux it later */
+ bfin_write_EMAC_SYSTAT(-1);
+#endif
+
+ irq_set_chained_handler(IRQ_GENERIC_ERROR, bf537_demux_error_irq);
+ for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++)
+ irq_set_chip_and_handler(irq, &bf537_generic_error_irqchip,
+ handle_level_irq);
+
+#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
+ irq_set_chained_handler(IRQ_PH_INTA_MAC_RX, bf537_demux_mac_rx_irq);
+ irq_set_chip_and_handler(IRQ_MAC_RX, &bf537_mac_rx_irqchip, handle_level_irq);
+ irq_set_chip_and_handler(IRQ_PORTH_INTA, &bf537_mac_rx_irqchip, handle_level_irq);
+
+ irq_set_chained_handler(IRQ_MAC_ERROR, bfin_demux_mac_status_irq);
+#endif
+}
diff --git a/arch/blackfin/mach-bf538/include/mach/anomaly.h b/arch/blackfin/mach-bf538/include/mach/anomaly.h
index 8774b48..55e7d07 100644
--- a/arch/blackfin/mach-bf538/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf538/include/mach/anomaly.h
@@ -5,14 +5,14 @@
* and can be replaced with that version at any time
* DO NOT EDIT THIS FILE
*
- * Copyright 2004-2010 Analog Devices Inc.
+ * Copyright 2004-2011 Analog Devices Inc.
* Licensed under the ADI BSD license.
* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
*/
/* This file should be up to date with:
- * - Revision H, 07/10/2009; ADSP-BF538/BF538F Blackfin Processor Anomaly List
- * - Revision M, 07/10/2009; ADSP-BF539/BF539F Blackfin Processor Anomaly List
+ * - Revision I, 05/25/2010; ADSP-BF538/BF538F Blackfin Processor Anomaly List
+ * - Revision N, 05/25/2010; ADSP-BF539/BF539F Blackfin Processor Anomaly List
*/
#ifndef _MACH_ANOMALY_H_
@@ -179,6 +179,7 @@
#define ANOMALY_05000363 (0)
#define ANOMALY_05000364 (0)
#define ANOMALY_05000380 (0)
+#define ANOMALY_05000383 (0)
#define ANOMALY_05000386 (1)
#define ANOMALY_05000389 (0)
#define ANOMALY_05000400 (0)
@@ -186,6 +187,7 @@
#define ANOMALY_05000430 (0)
#define ANOMALY_05000432 (0)
#define ANOMALY_05000435 (0)
+#define ANOMALY_05000440 (0)
#define ANOMALY_05000447 (0)
#define ANOMALY_05000448 (0)
#define ANOMALY_05000456 (0)
@@ -193,6 +195,7 @@
#define ANOMALY_05000465 (0)
#define ANOMALY_05000467 (0)
#define ANOMALY_05000474 (0)
+#define ANOMALY_05000480 (0)
#define ANOMALY_05000485 (0)
#endif
diff --git a/arch/blackfin/mach-bf538/include/mach/irq.h b/arch/blackfin/mach-bf538/include/mach/irq.h
index 7a479d2..07ca069 100644
--- a/arch/blackfin/mach-bf538/include/mach/irq.h
+++ b/arch/blackfin/mach-bf538/include/mach/irq.h
@@ -7,38 +7,9 @@
#ifndef _BF538_IRQ_H_
#define _BF538_IRQ_H_
-/*
- * Interrupt source definitions
- Event Source Core Event Name
- Core Emulation **
- Events (highest priority) EMU 0
- Reset RST 1
- NMI NMI 2
- Exception EVX 3
- Reserved -- 4
- Hardware Error IVHW 5
- Core Timer IVTMR 6 *
+#include <mach-common/irq.h>
- .....
-
- Software Interrupt 1 IVG14 31
- Software Interrupt 2 --
- (lowest priority) IVG15 32 *
-*/
-
-#define NR_PERI_INTS (2 * 32)
-
-/* The ABSTRACT IRQ definitions */
-/** the first seven of the following are fixed, the rest you change if you need to **/
-#define IRQ_EMU 0 /* Emulation */
-#define IRQ_RST 1 /* reset */
-#define IRQ_NMI 2 /* Non Maskable */
-#define IRQ_EVX 3 /* Exception */
-#define IRQ_UNUSED 4 /* - unused interrupt */
-#define IRQ_HWERR 5 /* Hardware Error */
-#define IRQ_CORETMR 6 /* Core timer */
-
-#define BFIN_IRQ(x) ((x) + 7)
+#define NR_PERI_INTS (2 * 32)
#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
#define IRQ_DMA0_ERROR BFIN_IRQ(1) /* DMA Error 0 (generic) */
@@ -91,37 +62,26 @@
#define SYS_IRQS BFIN_IRQ(63) /* 70 */
-#define IRQ_PF0 71
-#define IRQ_PF1 72
-#define IRQ_PF2 73
-#define IRQ_PF3 74
-#define IRQ_PF4 75
-#define IRQ_PF5 76
-#define IRQ_PF6 77
-#define IRQ_PF7 78
-#define IRQ_PF8 79
-#define IRQ_PF9 80
-#define IRQ_PF10 81
-#define IRQ_PF11 82
-#define IRQ_PF12 83
-#define IRQ_PF13 84
-#define IRQ_PF14 85
-#define IRQ_PF15 86
+#define IRQ_PF0 71
+#define IRQ_PF1 72
+#define IRQ_PF2 73
+#define IRQ_PF3 74
+#define IRQ_PF4 75
+#define IRQ_PF5 76
+#define IRQ_PF6 77
+#define IRQ_PF7 78
+#define IRQ_PF8 79
+#define IRQ_PF9 80
+#define IRQ_PF10 81
+#define IRQ_PF11 82
+#define IRQ_PF12 83
+#define IRQ_PF13 84
+#define IRQ_PF14 85
+#define IRQ_PF15 86
-#define GPIO_IRQ_BASE IRQ_PF0
+#define GPIO_IRQ_BASE IRQ_PF0
-#define NR_MACH_IRQS (IRQ_PF15 + 1)
-#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
-
-#define IVG7 7
-#define IVG8 8
-#define IVG9 9
-#define IVG10 10
-#define IVG11 11
-#define IVG12 12
-#define IVG13 13
-#define IVG14 14
-#define IVG15 15
+#define NR_MACH_IRQS (IRQ_PF15 + 1)
/* IAR0 BIT FIELDS */
#define IRQ_PLL_WAKEUP_POS 0
@@ -184,4 +144,5 @@
#define IRQ_CAN_TX_POS 0
#define IRQ_MEM1_DMA0_POS 4
#define IRQ_MEM1_DMA1_POS 8
-#endif /* _BF538_IRQ_H_ */
+
+#endif
diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c
index 93e19a5..311bf99 100644
--- a/arch/blackfin/mach-bf548/boards/ezkit.c
+++ b/arch/blackfin/mach-bf548/boards/ezkit.c
@@ -22,6 +22,7 @@
#include <asm/gpio.h>
#include <asm/nand.h>
#include <asm/dpmc.h>
+#include <asm/bfin_sport.h>
#include <asm/portmux.h>
#include <asm/bfin_sdh.h>
#include <mach/bf54x_keys.h>
@@ -956,7 +957,15 @@
.offset = MTDPART_OFS_APPEND,
}, {
.name = "file system(nor)",
- .size = MTDPART_SIZ_FULL,
+ .size = 0x1000000 - 0x80000 - 0x400000 - 0x8000 * 4,
+ .offset = MTDPART_OFS_APPEND,
+ }, {
+ .name = "config(nor)",
+ .size = 0x8000 * 3,
+ .offset = MTDPART_OFS_APPEND,
+ }, {
+ .name = "u-boot env(nor)",
+ .size = 0x8000,
.offset = MTDPART_OFS_APPEND,
}
};
@@ -1312,27 +1321,110 @@
},
};
-#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
+#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) || \
+ defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) || \
+ defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
+
+#define SPORT_REQ(x) \
+ [x] = {P_SPORT##x##_TFS, P_SPORT##x##_DTPRI, P_SPORT##x##_TSCLK, \
+ P_SPORT##x##_RFS, P_SPORT##x##_DRPRI, P_SPORT##x##_RSCLK, 0}
+
+static const u16 bfin_snd_pin[][7] = {
+ SPORT_REQ(0),
+ SPORT_REQ(1),
+};
+
+static struct bfin_snd_platform_data bfin_snd_data[] = {
+ {
+ .pin_req = &bfin_snd_pin[0][0],
+ },
+ {
+ .pin_req = &bfin_snd_pin[1][0],
+ },
+};
+
+#define BFIN_SND_RES(x) \
+ [x] = { \
+ { \
+ .start = SPORT##x##_TCR1, \
+ .end = SPORT##x##_TCR1, \
+ .flags = IORESOURCE_MEM \
+ }, \
+ { \
+ .start = CH_SPORT##x##_RX, \
+ .end = CH_SPORT##x##_RX, \
+ .flags = IORESOURCE_DMA, \
+ }, \
+ { \
+ .start = CH_SPORT##x##_TX, \
+ .end = CH_SPORT##x##_TX, \
+ .flags = IORESOURCE_DMA, \
+ }, \
+ { \
+ .start = IRQ_SPORT##x##_ERROR, \
+ .end = IRQ_SPORT##x##_ERROR, \
+ .flags = IORESOURCE_IRQ, \
+ } \
+ }
+
+static struct resource bfin_snd_resources[][4] = {
+ BFIN_SND_RES(0),
+ BFIN_SND_RES(1),
+};
+
+static struct platform_device bfin_pcm = {
+ .name = "bfin-pcm-audio",
+ .id = -1,
+};
+#endif
+
+#if defined(CONFIG_SND_BF5XX_SOC_AD73311) || defined(CONFIG_SND_BF5XX_SOC_AD73311_MODULE)
+static struct platform_device bfin_ad73311_codec_device = {
+ .name = "ad73311",
+ .id = -1,
+};
+#endif
+
+#if defined(CONFIG_SND_BF5XX_SOC_AD1980) || defined(CONFIG_SND_BF5XX_SOC_AD1980_MODULE)
+static struct platform_device bfin_ad1980_codec_device = {
+ .name = "ad1980",
+ .id = -1,
+};
+#endif
+
+#if defined(CONFIG_SND_BF5XX_SOC_I2S) || defined(CONFIG_SND_BF5XX_SOC_I2S_MODULE)
static struct platform_device bfin_i2s = {
.name = "bfin-i2s",
.id = CONFIG_SND_BF5XX_SPORT_NUM,
- /* TODO: add platform data here */
+ .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
+ .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
+ .dev = {
+ .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
+ },
};
#endif
-#if defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE)
+#if defined(CONFIG_SND_BF5XX_SOC_TDM) || defined(CONFIG_SND_BF5XX_SOC_TDM_MODULE)
static struct platform_device bfin_tdm = {
.name = "bfin-tdm",
.id = CONFIG_SND_BF5XX_SPORT_NUM,
- /* TODO: add platform data here */
+ .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
+ .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
+ .dev = {
+ .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
+ },
};
#endif
-#if defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
+#if defined(CONFIG_SND_BF5XX_SOC_AC97) || defined(CONFIG_SND_BF5XX_SOC_AC97_MODULE)
static struct platform_device bfin_ac97 = {
.name = "bfin-ac97",
.id = CONFIG_SND_BF5XX_SPORT_NUM,
- /* TODO: add platform data here */
+ .num_resources = ARRAY_SIZE(bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM]),
+ .resource = bfin_snd_resources[CONFIG_SND_BF5XX_SPORT_NUM],
+ .dev = {
+ .platform_data = &bfin_snd_data[CONFIG_SND_BF5XX_SPORT_NUM],
+ },
};
#endif
@@ -1450,6 +1542,16 @@
&ezkit_flash_device,
#endif
+#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE) || \
+ defined(CONFIG_SND_BF5XX_TDM) || defined(CONFIG_SND_BF5XX_TDM_MODULE) || \
+ defined(CONFIG_SND_BF5XX_AC97) || defined(CONFIG_SND_BF5XX_AC97_MODULE)
+ &bfin_pcm,
+#endif
+
+#if defined(CONFIG_SND_BF5XX_SOC_AD1980) || defined(CONFIG_SND_BF5XX_SOC_AD1980_MODULE)
+ &bfin_ad1980_codec_device,
+#endif
+
#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
&bfin_i2s,
#endif
diff --git a/arch/blackfin/mach-bf548/include/mach/anomaly.h b/arch/blackfin/mach-bf548/include/mach/anomaly.h
index ffd0537..9e70785 100644
--- a/arch/blackfin/mach-bf548/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf548/include/mach/anomaly.h
@@ -5,13 +5,13 @@
* and can be replaced with that version at any time
* DO NOT EDIT THIS FILE
*
- * Copyright 2004-2010 Analog Devices Inc.
+ * Copyright 2004-2011 Analog Devices Inc.
* Licensed under the ADI BSD license.
* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
*/
/* This file should be up to date with:
- * - Revision I, 07/23/2009; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
+ * - Revision J, 06/03/2010; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
*/
#ifndef _MACH_ANOMALY_H_
@@ -220,6 +220,8 @@
#define ANOMALY_05000481 (1)
/* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */
#define ANOMALY_05000483 (1)
+/* DDR Trim May Not Be Performed for Certain VLEV Values in OTP Page PBS00L */
+#define ANOMALY_05000484 (__SILICON_REVISION__ < 3)
/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
#define ANOMALY_05000485 (__SILICON_REVISION__ >= 2)
/* IFLUSH sucks at life */
@@ -274,6 +276,8 @@
#define ANOMALY_05000412 (0)
#define ANOMALY_05000432 (0)
#define ANOMALY_05000435 (0)
+#define ANOMALY_05000440 (0)
#define ANOMALY_05000475 (0)
+#define ANOMALY_05000480 (0)
#endif
diff --git a/arch/blackfin/mach-bf548/include/mach/irq.h b/arch/blackfin/mach-bf548/include/mach/irq.h
index 7f87787..533b809 100644
--- a/arch/blackfin/mach-bf548/include/mach/irq.h
+++ b/arch/blackfin/mach-bf548/include/mach/irq.h
@@ -7,38 +7,9 @@
#ifndef _BF548_IRQ_H_
#define _BF548_IRQ_H_
-/*
- * Interrupt source definitions
- Event Source Core Event Name
-Core Emulation **
-Events (highest priority) EMU 0
- Reset RST 1
- NMI NMI 2
- Exception EVX 3
- Reserved -- 4
- Hardware Error IVHW 5
- Core Timer IVTMR 6 *
+#include <mach-common/irq.h>
-.....
-
- Software Interrupt 1 IVG14 31
- Software Interrupt 2 --
- (lowest priority) IVG15 32 *
- */
-
-#define NR_PERI_INTS (32 * 3)
-
-/* The ABSTRACT IRQ definitions */
-/** the first seven of the following are fixed, the rest you change if you need to **/
-#define IRQ_EMU 0 /* Emulation */
-#define IRQ_RST 1 /* reset */
-#define IRQ_NMI 2 /* Non Maskable */
-#define IRQ_EVX 3 /* Exception */
-#define IRQ_UNUSED 4 /* - unused interrupt*/
-#define IRQ_HWERR 5 /* Hardware Error */
-#define IRQ_CORETMR 6 /* Core timer */
-
-#define BFIN_IRQ(x) ((x) + 7)
+#define NR_PERI_INTS (3 * 32)
#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
#define IRQ_DMAC0_ERROR BFIN_IRQ(1) /* DMAC0 Status Interrupt */
@@ -311,49 +282,37 @@
#define IRQ_PJ14 BFIN_PJ_IRQ(14) /* N/A */
#define IRQ_PJ15 BFIN_PJ_IRQ(15) /* N/A */
-#define GPIO_IRQ_BASE IRQ_PA0
+#define GPIO_IRQ_BASE IRQ_PA0
-#define NR_MACH_IRQS (IRQ_PJ15 + 1)
-#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
+#define NR_MACH_IRQS (IRQ_PJ15 + 1)
/* For compatibility reasons with existing code */
-#define IRQ_DMAC0_ERR IRQ_DMAC0_ERROR
-#define IRQ_EPPI0_ERR IRQ_EPPI0_ERROR
+#define IRQ_DMAC0_ERR IRQ_DMAC0_ERROR
+#define IRQ_EPPI0_ERR IRQ_EPPI0_ERROR
#define IRQ_SPORT0_ERR IRQ_SPORT0_ERROR
#define IRQ_SPORT1_ERR IRQ_SPORT1_ERROR
-#define IRQ_SPI0_ERR IRQ_SPI0_ERROR
-#define IRQ_UART0_ERR IRQ_UART0_ERROR
-#define IRQ_DMAC1_ERR IRQ_DMAC1_ERROR
+#define IRQ_SPI0_ERR IRQ_SPI0_ERROR
+#define IRQ_UART0_ERR IRQ_UART0_ERROR
+#define IRQ_DMAC1_ERR IRQ_DMAC1_ERROR
#define IRQ_SPORT2_ERR IRQ_SPORT2_ERROR
#define IRQ_SPORT3_ERR IRQ_SPORT3_ERROR
-#define IRQ_SPI1_ERR IRQ_SPI1_ERROR
-#define IRQ_SPI2_ERR IRQ_SPI2_ERROR
-#define IRQ_UART1_ERR IRQ_UART1_ERROR
-#define IRQ_UART2_ERR IRQ_UART2_ERROR
-#define IRQ_CAN0_ERR IRQ_CAN0_ERROR
-#define IRQ_MXVR_ERR IRQ_MXVR_ERROR
-#define IRQ_EPPI1_ERR IRQ_EPPI1_ERROR
-#define IRQ_EPPI2_ERR IRQ_EPPI2_ERROR
-#define IRQ_UART3_ERR IRQ_UART3_ERROR
-#define IRQ_HOST_ERR IRQ_HOST_ERROR
-#define IRQ_PIXC_ERR IRQ_PIXC_ERROR
-#define IRQ_NFC_ERR IRQ_NFC_ERROR
-#define IRQ_ATAPI_ERR IRQ_ATAPI_ERROR
-#define IRQ_CAN1_ERR IRQ_CAN1_ERROR
+#define IRQ_SPI1_ERR IRQ_SPI1_ERROR
+#define IRQ_SPI2_ERR IRQ_SPI2_ERROR
+#define IRQ_UART1_ERR IRQ_UART1_ERROR
+#define IRQ_UART2_ERR IRQ_UART2_ERROR
+#define IRQ_CAN0_ERR IRQ_CAN0_ERROR
+#define IRQ_MXVR_ERR IRQ_MXVR_ERROR
+#define IRQ_EPPI1_ERR IRQ_EPPI1_ERROR
+#define IRQ_EPPI2_ERR IRQ_EPPI2_ERROR
+#define IRQ_UART3_ERR IRQ_UART3_ERROR
+#define IRQ_HOST_ERR IRQ_HOST_ERROR
+#define IRQ_PIXC_ERR IRQ_PIXC_ERROR
+#define IRQ_NFC_ERR IRQ_NFC_ERROR
+#define IRQ_ATAPI_ERR IRQ_ATAPI_ERROR
+#define IRQ_CAN1_ERR IRQ_CAN1_ERROR
#define IRQ_HS_DMA_ERR IRQ_HS_DMA_ERROR
-
-#define IVG7 7
-#define IVG8 8
-#define IVG9 9
-#define IVG10 10
-#define IVG11 11
-#define IVG12 12
-#define IVG13 13
-#define IVG14 14
-#define IVG15 15
-
/* IAR0 BIT FIELDS */
#define IRQ_PLL_WAKEUP_POS 0
#define IRQ_DMAC0_ERR_POS 4
@@ -492,4 +451,4 @@
#endif
-#endif /* _BF548_IRQ_H_ */
+#endif
diff --git a/arch/blackfin/mach-bf561/boards/ezkit.c b/arch/blackfin/mach-bf561/boards/ezkit.c
index f667e77..5067984 100644
--- a/arch/blackfin/mach-bf561/boards/ezkit.c
+++ b/arch/blackfin/mach-bf561/boards/ezkit.c
@@ -247,7 +247,15 @@
.offset = MTDPART_OFS_APPEND,
}, {
.name = "file system(nor)",
- .size = MTDPART_SIZ_FULL,
+ .size = 0x800000 - 0x40000 - 0x1C0000 - 0x2000 * 8,
+ .offset = MTDPART_OFS_APPEND,
+ }, {
+ .name = "config(nor)",
+ .size = 0x2000 * 7,
+ .offset = MTDPART_OFS_APPEND,
+ }, {
+ .name = "u-boot env(nor)",
+ .size = 0x2000,
.offset = MTDPART_OFS_APPEND,
}
};
diff --git a/arch/blackfin/mach-bf561/include/mach/anomaly.h b/arch/blackfin/mach-bf561/include/mach/anomaly.h
index 6a3499b..22b5ab7 100644
--- a/arch/blackfin/mach-bf561/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf561/include/mach/anomaly.h
@@ -5,13 +5,13 @@
* and can be replaced with that version at any time
* DO NOT EDIT THIS FILE
*
- * Copyright 2004-2010 Analog Devices Inc.
+ * Copyright 2004-2011 Analog Devices Inc.
* Licensed under the ADI BSD license.
* https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
*/
/* This file should be up to date with:
- * - Revision Q, 11/07/2008; ADSP-BF561 Blackfin Processor Anomaly List
+ * - Revision R, 05/25/2010; ADSP-BF561 Blackfin Processor Anomaly List
*/
#ifndef _MACH_ANOMALY_H_
@@ -290,12 +290,18 @@
#define ANOMALY_05000428 (__SILICON_REVISION__ > 3)
/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
#define ANOMALY_05000443 (1)
+/* SCKELOW Feature Is Not Functional */
+#define ANOMALY_05000458 (1)
/* False Hardware Error when RETI Points to Invalid Memory */
#define ANOMALY_05000461 (1)
+/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
+#define ANOMALY_05000462 (1)
+/* Boot Failure When SDRAM Control Signals Toggle Coming Out Of Reset */
+#define ANOMALY_05000471 (1)
/* Interrupted 32-Bit SPORT Data Register Access Results In Underflow */
#define ANOMALY_05000473 (1)
/* Possible Lockup Condition whem Modifying PLL from External Memory */
-#define ANOMALY_05000475 (__SILICON_REVISION__ < 4)
+#define ANOMALY_05000475 (1)
/* TESTSET Instruction Cannot Be Interrupted */
#define ANOMALY_05000477 (1)
/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
@@ -314,12 +320,14 @@
#define ANOMALY_05000353 (1)
#define ANOMALY_05000364 (0)
#define ANOMALY_05000380 (0)
+#define ANOMALY_05000383 (0)
#define ANOMALY_05000386 (1)
#define ANOMALY_05000389 (0)
#define ANOMALY_05000400 (0)
#define ANOMALY_05000430 (0)
#define ANOMALY_05000432 (0)
#define ANOMALY_05000435 (0)
+#define ANOMALY_05000440 (0)
#define ANOMALY_05000447 (0)
#define ANOMALY_05000448 (0)
#define ANOMALY_05000456 (0)
@@ -327,6 +335,7 @@
#define ANOMALY_05000465 (0)
#define ANOMALY_05000467 (0)
#define ANOMALY_05000474 (0)
+#define ANOMALY_05000480 (0)
#define ANOMALY_05000485 (0)
#endif
diff --git a/arch/blackfin/mach-bf561/include/mach/irq.h b/arch/blackfin/mach-bf561/include/mach/irq.h
index c95566a..d699852 100644
--- a/arch/blackfin/mach-bf561/include/mach/irq.h
+++ b/arch/blackfin/mach-bf561/include/mach/irq.h
@@ -7,212 +7,98 @@
#ifndef _BF561_IRQ_H_
#define _BF561_IRQ_H_
-/***********************************************************************
- * Interrupt source definitions:
- Event Source Core Event Name IRQ No
- (highest priority)
- Emulation Events EMU 0
- Reset RST 1
- NMI NMI 2
- Exception EVX 3
- Reserved -- 4
- Hardware Error IVHW 5
- Core Timer IVTMR 6 *
+#include <mach-common/irq.h>
- PLL Wakeup Interrupt IVG7 7
- DMA1 Error (generic) IVG7 8
- DMA2 Error (generic) IVG7 9
- IMDMA Error (generic) IVG7 10
- PPI1 Error Interrupt IVG7 11
- PPI2 Error Interrupt IVG7 12
- SPORT0 Error Interrupt IVG7 13
- SPORT1 Error Interrupt IVG7 14
- SPI Error Interrupt IVG7 15
- UART Error Interrupt IVG7 16
- Reserved Interrupt IVG7 17
+#define NR_PERI_INTS (2 * 32)
- DMA1 0 Interrupt(PPI1) IVG8 18
- DMA1 1 Interrupt(PPI2) IVG8 19
- DMA1 2 Interrupt IVG8 20
- DMA1 3 Interrupt IVG8 21
- DMA1 4 Interrupt IVG8 22
- DMA1 5 Interrupt IVG8 23
- DMA1 6 Interrupt IVG8 24
- DMA1 7 Interrupt IVG8 25
- DMA1 8 Interrupt IVG8 26
- DMA1 9 Interrupt IVG8 27
- DMA1 10 Interrupt IVG8 28
- DMA1 11 Interrupt IVG8 29
-
- DMA2 0 (SPORT0 RX) IVG9 30
- DMA2 1 (SPORT0 TX) IVG9 31
- DMA2 2 (SPORT1 RX) IVG9 32
- DMA2 3 (SPORT2 TX) IVG9 33
- DMA2 4 (SPI) IVG9 34
- DMA2 5 (UART RX) IVG9 35
- DMA2 6 (UART TX) IVG9 36
- DMA2 7 Interrupt IVG9 37
- DMA2 8 Interrupt IVG9 38
- DMA2 9 Interrupt IVG9 39
- DMA2 10 Interrupt IVG9 40
- DMA2 11 Interrupt IVG9 41
-
- TIMER 0 Interrupt IVG10 42
- TIMER 1 Interrupt IVG10 43
- TIMER 2 Interrupt IVG10 44
- TIMER 3 Interrupt IVG10 45
- TIMER 4 Interrupt IVG10 46
- TIMER 5 Interrupt IVG10 47
- TIMER 6 Interrupt IVG10 48
- TIMER 7 Interrupt IVG10 49
- TIMER 8 Interrupt IVG10 50
- TIMER 9 Interrupt IVG10 51
- TIMER 10 Interrupt IVG10 52
- TIMER 11 Interrupt IVG10 53
-
- Programmable Flags0 A (8) IVG11 54
- Programmable Flags0 B (8) IVG11 55
- Programmable Flags1 A (8) IVG11 56
- Programmable Flags1 B (8) IVG11 57
- Programmable Flags2 A (8) IVG11 58
- Programmable Flags2 B (8) IVG11 59
-
- MDMA1 0 write/read INT IVG8 60
- MDMA1 1 write/read INT IVG8 61
-
- MDMA2 0 write/read INT IVG9 62
- MDMA2 1 write/read INT IVG9 63
-
- IMDMA 0 write/read INT IVG12 64
- IMDMA 1 write/read INT IVG12 65
-
- Watch Dog Timer IVG13 66
-
- Reserved interrupt IVG7 67
- Reserved interrupt IVG7 68
- Supplemental interrupt 0 IVG7 69
- supplemental interrupt 1 IVG7 70
-
- Softirq IVG14
- System Call --
- (lowest priority) IVG15
-
- **********************************************************************/
+#define IRQ_PLL_WAKEUP BFIN_IRQ(0) /* PLL Wakeup Interrupt */
+#define IRQ_DMA1_ERROR BFIN_IRQ(1) /* DMA1 Error (general) */
+#define IRQ_DMA_ERROR IRQ_DMA1_ERROR /* DMA1 Error (general) */
+#define IRQ_DMA2_ERROR BFIN_IRQ(2) /* DMA2 Error (general) */
+#define IRQ_IMDMA_ERROR BFIN_IRQ(3) /* IMDMA Error Interrupt */
+#define IRQ_PPI1_ERROR BFIN_IRQ(4) /* PPI1 Error Interrupt */
+#define IRQ_PPI_ERROR IRQ_PPI1_ERROR /* PPI1 Error Interrupt */
+#define IRQ_PPI2_ERROR BFIN_IRQ(5) /* PPI2 Error Interrupt */
+#define IRQ_SPORT0_ERROR BFIN_IRQ(6) /* SPORT0 Error Interrupt */
+#define IRQ_SPORT1_ERROR BFIN_IRQ(7) /* SPORT1 Error Interrupt */
+#define IRQ_SPI_ERROR BFIN_IRQ(8) /* SPI Error Interrupt */
+#define IRQ_UART_ERROR BFIN_IRQ(9) /* UART Error Interrupt */
+#define IRQ_RESERVED_ERROR BFIN_IRQ(10) /* Reversed */
+#define IRQ_DMA1_0 BFIN_IRQ(11) /* DMA1 0 Interrupt(PPI1) */
+#define IRQ_PPI IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */
+#define IRQ_PPI0 IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */
+#define IRQ_DMA1_1 BFIN_IRQ(12) /* DMA1 1 Interrupt(PPI2) */
+#define IRQ_PPI1 IRQ_DMA1_1 /* DMA1 1 Interrupt(PPI2) */
+#define IRQ_DMA1_2 BFIN_IRQ(13) /* DMA1 2 Interrupt */
+#define IRQ_DMA1_3 BFIN_IRQ(14) /* DMA1 3 Interrupt */
+#define IRQ_DMA1_4 BFIN_IRQ(15) /* DMA1 4 Interrupt */
+#define IRQ_DMA1_5 BFIN_IRQ(16) /* DMA1 5 Interrupt */
+#define IRQ_DMA1_6 BFIN_IRQ(17) /* DMA1 6 Interrupt */
+#define IRQ_DMA1_7 BFIN_IRQ(18) /* DMA1 7 Interrupt */
+#define IRQ_DMA1_8 BFIN_IRQ(19) /* DMA1 8 Interrupt */
+#define IRQ_DMA1_9 BFIN_IRQ(20) /* DMA1 9 Interrupt */
+#define IRQ_DMA1_10 BFIN_IRQ(21) /* DMA1 10 Interrupt */
+#define IRQ_DMA1_11 BFIN_IRQ(22) /* DMA1 11 Interrupt */
+#define IRQ_DMA2_0 BFIN_IRQ(23) /* DMA2 0 (SPORT0 RX) */
+#define IRQ_SPORT0_RX IRQ_DMA2_0 /* DMA2 0 (SPORT0 RX) */
+#define IRQ_DMA2_1 BFIN_IRQ(24) /* DMA2 1 (SPORT0 TX) */
+#define IRQ_SPORT0_TX IRQ_DMA2_1 /* DMA2 1 (SPORT0 TX) */
+#define IRQ_DMA2_2 BFIN_IRQ(25) /* DMA2 2 (SPORT1 RX) */
+#define IRQ_SPORT1_RX IRQ_DMA2_2 /* DMA2 2 (SPORT1 RX) */
+#define IRQ_DMA2_3 BFIN_IRQ(26) /* DMA2 3 (SPORT2 TX) */
+#define IRQ_SPORT1_TX IRQ_DMA2_3 /* DMA2 3 (SPORT2 TX) */
+#define IRQ_DMA2_4 BFIN_IRQ(27) /* DMA2 4 (SPI) */
+#define IRQ_SPI IRQ_DMA2_4 /* DMA2 4 (SPI) */
+#define IRQ_DMA2_5 BFIN_IRQ(28) /* DMA2 5 (UART RX) */
+#define IRQ_UART_RX IRQ_DMA2_5 /* DMA2 5 (UART RX) */
+#define IRQ_DMA2_6 BFIN_IRQ(29) /* DMA2 6 (UART TX) */
+#define IRQ_UART_TX IRQ_DMA2_6 /* DMA2 6 (UART TX) */
+#define IRQ_DMA2_7 BFIN_IRQ(30) /* DMA2 7 Interrupt */
+#define IRQ_DMA2_8 BFIN_IRQ(31) /* DMA2 8 Interrupt */
+#define IRQ_DMA2_9 BFIN_IRQ(32) /* DMA2 9 Interrupt */
+#define IRQ_DMA2_10 BFIN_IRQ(33) /* DMA2 10 Interrupt */
+#define IRQ_DMA2_11 BFIN_IRQ(34) /* DMA2 11 Interrupt */
+#define IRQ_TIMER0 BFIN_IRQ(35) /* TIMER 0 Interrupt */
+#define IRQ_TIMER1 BFIN_IRQ(36) /* TIMER 1 Interrupt */
+#define IRQ_TIMER2 BFIN_IRQ(37) /* TIMER 2 Interrupt */
+#define IRQ_TIMER3 BFIN_IRQ(38) /* TIMER 3 Interrupt */
+#define IRQ_TIMER4 BFIN_IRQ(39) /* TIMER 4 Interrupt */
+#define IRQ_TIMER5 BFIN_IRQ(40) /* TIMER 5 Interrupt */
+#define IRQ_TIMER6 BFIN_IRQ(41) /* TIMER 6 Interrupt */
+#define IRQ_TIMER7 BFIN_IRQ(42) /* TIMER 7 Interrupt */
+#define IRQ_TIMER8 BFIN_IRQ(43) /* TIMER 8 Interrupt */
+#define IRQ_TIMER9 BFIN_IRQ(44) /* TIMER 9 Interrupt */
+#define IRQ_TIMER10 BFIN_IRQ(45) /* TIMER 10 Interrupt */
+#define IRQ_TIMER11 BFIN_IRQ(46) /* TIMER 11 Interrupt */
+#define IRQ_PROG0_INTA BFIN_IRQ(47) /* Programmable Flags0 A (8) */
+#define IRQ_PROG_INTA IRQ_PROG0_INTA /* Programmable Flags0 A (8) */
+#define IRQ_PROG0_INTB BFIN_IRQ(48) /* Programmable Flags0 B (8) */
+#define IRQ_PROG_INTB IRQ_PROG0_INTB /* Programmable Flags0 B (8) */
+#define IRQ_PROG1_INTA BFIN_IRQ(49) /* Programmable Flags1 A (8) */
+#define IRQ_PROG1_INTB BFIN_IRQ(50) /* Programmable Flags1 B (8) */
+#define IRQ_PROG2_INTA BFIN_IRQ(51) /* Programmable Flags2 A (8) */
+#define IRQ_PROG2_INTB BFIN_IRQ(52) /* Programmable Flags2 B (8) */
+#define IRQ_DMA1_WRRD0 BFIN_IRQ(53) /* MDMA1 0 write/read INT */
+#define IRQ_DMA_WRRD0 IRQ_DMA1_WRRD0 /* MDMA1 0 write/read INT */
+#define IRQ_MEM_DMA0 IRQ_DMA1_WRRD0
+#define IRQ_DMA1_WRRD1 BFIN_IRQ(54) /* MDMA1 1 write/read INT */
+#define IRQ_DMA_WRRD1 IRQ_DMA1_WRRD1 /* MDMA1 1 write/read INT */
+#define IRQ_MEM_DMA1 IRQ_DMA1_WRRD1
+#define IRQ_DMA2_WRRD0 BFIN_IRQ(55) /* MDMA2 0 write/read INT */
+#define IRQ_MEM_DMA2 IRQ_DMA2_WRRD0
+#define IRQ_DMA2_WRRD1 BFIN_IRQ(56) /* MDMA2 1 write/read INT */
+#define IRQ_MEM_DMA3 IRQ_DMA2_WRRD1
+#define IRQ_IMDMA_WRRD0 BFIN_IRQ(57) /* IMDMA 0 write/read INT */
+#define IRQ_IMEM_DMA0 IRQ_IMDMA_WRRD0
+#define IRQ_IMDMA_WRRD1 BFIN_IRQ(58) /* IMDMA 1 write/read INT */
+#define IRQ_IMEM_DMA1 IRQ_IMDMA_WRRD1
+#define IRQ_WATCH BFIN_IRQ(59) /* Watch Dog Timer */
+#define IRQ_RESERVED_1 BFIN_IRQ(60) /* Reserved interrupt */
+#define IRQ_RESERVED_2 BFIN_IRQ(61) /* Reserved interrupt */
+#define IRQ_SUPPLE_0 BFIN_IRQ(62) /* Supplemental interrupt 0 */
+#define IRQ_SUPPLE_1 BFIN_IRQ(63) /* supplemental interrupt 1 */
#define SYS_IRQS 71
-#define NR_PERI_INTS 64
-
-/*
- * The ABSTRACT IRQ definitions
- * the first seven of the following are fixed,
- * the rest you change if you need to.
- */
-/* IVG 0-6*/
-#define IRQ_EMU 0 /* Emulation */
-#define IRQ_RST 1 /* Reset */
-#define IRQ_NMI 2 /* Non Maskable Interrupt */
-#define IRQ_EVX 3 /* Exception */
-#define IRQ_UNUSED 4 /* Reserved interrupt */
-#define IRQ_HWERR 5 /* Hardware Error */
-#define IRQ_CORETMR 6 /* Core timer */
-
-#define IVG_BASE 7
-/* IVG 7 */
-#define IRQ_PLL_WAKEUP (IVG_BASE + 0) /* PLL Wakeup Interrupt */
-#define IRQ_DMA1_ERROR (IVG_BASE + 1) /* DMA1 Error (general) */
-#define IRQ_DMA_ERROR IRQ_DMA1_ERROR /* DMA1 Error (general) */
-#define IRQ_DMA2_ERROR (IVG_BASE + 2) /* DMA2 Error (general) */
-#define IRQ_IMDMA_ERROR (IVG_BASE + 3) /* IMDMA Error Interrupt */
-#define IRQ_PPI1_ERROR (IVG_BASE + 4) /* PPI1 Error Interrupt */
-#define IRQ_PPI_ERROR IRQ_PPI1_ERROR /* PPI1 Error Interrupt */
-#define IRQ_PPI2_ERROR (IVG_BASE + 5) /* PPI2 Error Interrupt */
-#define IRQ_SPORT0_ERROR (IVG_BASE + 6) /* SPORT0 Error Interrupt */
-#define IRQ_SPORT1_ERROR (IVG_BASE + 7) /* SPORT1 Error Interrupt */
-#define IRQ_SPI_ERROR (IVG_BASE + 8) /* SPI Error Interrupt */
-#define IRQ_UART_ERROR (IVG_BASE + 9) /* UART Error Interrupt */
-#define IRQ_RESERVED_ERROR (IVG_BASE + 10) /* Reversed Interrupt */
-/* IVG 8 */
-#define IRQ_DMA1_0 (IVG_BASE + 11) /* DMA1 0 Interrupt(PPI1) */
-#define IRQ_PPI IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */
-#define IRQ_PPI0 IRQ_DMA1_0 /* DMA1 0 Interrupt(PPI1) */
-#define IRQ_DMA1_1 (IVG_BASE + 12) /* DMA1 1 Interrupt(PPI2) */
-#define IRQ_PPI1 IRQ_DMA1_1 /* DMA1 1 Interrupt(PPI2) */
-#define IRQ_DMA1_2 (IVG_BASE + 13) /* DMA1 2 Interrupt */
-#define IRQ_DMA1_3 (IVG_BASE + 14) /* DMA1 3 Interrupt */
-#define IRQ_DMA1_4 (IVG_BASE + 15) /* DMA1 4 Interrupt */
-#define IRQ_DMA1_5 (IVG_BASE + 16) /* DMA1 5 Interrupt */
-#define IRQ_DMA1_6 (IVG_BASE + 17) /* DMA1 6 Interrupt */
-#define IRQ_DMA1_7 (IVG_BASE + 18) /* DMA1 7 Interrupt */
-#define IRQ_DMA1_8 (IVG_BASE + 19) /* DMA1 8 Interrupt */
-#define IRQ_DMA1_9 (IVG_BASE + 20) /* DMA1 9 Interrupt */
-#define IRQ_DMA1_10 (IVG_BASE + 21) /* DMA1 10 Interrupt */
-#define IRQ_DMA1_11 (IVG_BASE + 22) /* DMA1 11 Interrupt */
-/* IVG 9 */
-#define IRQ_DMA2_0 (IVG_BASE + 23) /* DMA2 0 (SPORT0 RX) */
-#define IRQ_SPORT0_RX IRQ_DMA2_0 /* DMA2 0 (SPORT0 RX) */
-#define IRQ_DMA2_1 (IVG_BASE + 24) /* DMA2 1 (SPORT0 TX) */
-#define IRQ_SPORT0_TX IRQ_DMA2_1 /* DMA2 1 (SPORT0 TX) */
-#define IRQ_DMA2_2 (IVG_BASE + 25) /* DMA2 2 (SPORT1 RX) */
-#define IRQ_SPORT1_RX IRQ_DMA2_2 /* DMA2 2 (SPORT1 RX) */
-#define IRQ_DMA2_3 (IVG_BASE + 26) /* DMA2 3 (SPORT2 TX) */
-#define IRQ_SPORT1_TX IRQ_DMA2_3 /* DMA2 3 (SPORT2 TX) */
-#define IRQ_DMA2_4 (IVG_BASE + 27) /* DMA2 4 (SPI) */
-#define IRQ_SPI IRQ_DMA2_4 /* DMA2 4 (SPI) */
-#define IRQ_DMA2_5 (IVG_BASE + 28) /* DMA2 5 (UART RX) */
-#define IRQ_UART_RX IRQ_DMA2_5 /* DMA2 5 (UART RX) */
-#define IRQ_DMA2_6 (IVG_BASE + 29) /* DMA2 6 (UART TX) */
-#define IRQ_UART_TX IRQ_DMA2_6 /* DMA2 6 (UART TX) */
-#define IRQ_DMA2_7 (IVG_BASE + 30) /* DMA2 7 Interrupt */
-#define IRQ_DMA2_8 (IVG_BASE + 31) /* DMA2 8 Interrupt */
-#define IRQ_DMA2_9 (IVG_BASE + 32) /* DMA2 9 Interrupt */
-#define IRQ_DMA2_10 (IVG_BASE + 33) /* DMA2 10 Interrupt */
-#define IRQ_DMA2_11 (IVG_BASE + 34) /* DMA2 11 Interrupt */
-/* IVG 10 */
-#define IRQ_TIMER0 (IVG_BASE + 35) /* TIMER 0 Interrupt */
-#define IRQ_TIMER1 (IVG_BASE + 36) /* TIMER 1 Interrupt */
-#define IRQ_TIMER2 (IVG_BASE + 37) /* TIMER 2 Interrupt */
-#define IRQ_TIMER3 (IVG_BASE + 38) /* TIMER 3 Interrupt */
-#define IRQ_TIMER4 (IVG_BASE + 39) /* TIMER 4 Interrupt */
-#define IRQ_TIMER5 (IVG_BASE + 40) /* TIMER 5 Interrupt */
-#define IRQ_TIMER6 (IVG_BASE + 41) /* TIMER 6 Interrupt */
-#define IRQ_TIMER7 (IVG_BASE + 42) /* TIMER 7 Interrupt */
-#define IRQ_TIMER8 (IVG_BASE + 43) /* TIMER 8 Interrupt */
-#define IRQ_TIMER9 (IVG_BASE + 44) /* TIMER 9 Interrupt */
-#define IRQ_TIMER10 (IVG_BASE + 45) /* TIMER 10 Interrupt */
-#define IRQ_TIMER11 (IVG_BASE + 46) /* TIMER 11 Interrupt */
-/* IVG 11 */
-#define IRQ_PROG0_INTA (IVG_BASE + 47) /* Programmable Flags0 A (8) */
-#define IRQ_PROG_INTA IRQ_PROG0_INTA /* Programmable Flags0 A (8) */
-#define IRQ_PROG0_INTB (IVG_BASE + 48) /* Programmable Flags0 B (8) */
-#define IRQ_PROG_INTB IRQ_PROG0_INTB /* Programmable Flags0 B (8) */
-#define IRQ_PROG1_INTA (IVG_BASE + 49) /* Programmable Flags1 A (8) */
-#define IRQ_PROG1_INTB (IVG_BASE + 50) /* Programmable Flags1 B (8) */
-#define IRQ_PROG2_INTA (IVG_BASE + 51) /* Programmable Flags2 A (8) */
-#define IRQ_PROG2_INTB (IVG_BASE + 52) /* Programmable Flags2 B (8) */
-/* IVG 8 */
-#define IRQ_DMA1_WRRD0 (IVG_BASE + 53) /* MDMA1 0 write/read INT */
-#define IRQ_DMA_WRRD0 IRQ_DMA1_WRRD0 /* MDMA1 0 write/read INT */
-#define IRQ_MEM_DMA0 IRQ_DMA1_WRRD0
-#define IRQ_DMA1_WRRD1 (IVG_BASE + 54) /* MDMA1 1 write/read INT */
-#define IRQ_DMA_WRRD1 IRQ_DMA1_WRRD1 /* MDMA1 1 write/read INT */
-#define IRQ_MEM_DMA1 IRQ_DMA1_WRRD1
-/* IVG 9 */
-#define IRQ_DMA2_WRRD0 (IVG_BASE + 55) /* MDMA2 0 write/read INT */
-#define IRQ_MEM_DMA2 IRQ_DMA2_WRRD0
-#define IRQ_DMA2_WRRD1 (IVG_BASE + 56) /* MDMA2 1 write/read INT */
-#define IRQ_MEM_DMA3 IRQ_DMA2_WRRD1
-/* IVG 12 */
-#define IRQ_IMDMA_WRRD0 (IVG_BASE + 57) /* IMDMA 0 write/read INT */
-#define IRQ_IMEM_DMA0 IRQ_IMDMA_WRRD0
-#define IRQ_IMDMA_WRRD1 (IVG_BASE + 58) /* IMDMA 1 write/read INT */
-#define IRQ_IMEM_DMA1 IRQ_IMDMA_WRRD1
-/* IVG 13 */
-#define IRQ_WATCH (IVG_BASE + 59) /* Watch Dog Timer */
-/* IVG 7 */
-#define IRQ_RESERVED_1 (IVG_BASE + 60) /* Reserved interrupt */
-#define IRQ_RESERVED_2 (IVG_BASE + 61) /* Reserved interrupt */
-#define IRQ_SUPPLE_0 (IVG_BASE + 62) /* Supplemental interrupt 0 */
-#define IRQ_SUPPLE_1 (IVG_BASE + 63) /* supplemental interrupt 1 */
#define IRQ_PF0 73
#define IRQ_PF1 74
@@ -266,158 +152,85 @@
#define GPIO_IRQ_BASE IRQ_PF0
#define NR_MACH_IRQS (IRQ_PF47 + 1)
-#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
-
-#define IVG7 7
-#define IVG8 8
-#define IVG9 9
-#define IVG10 10
-#define IVG11 11
-#define IVG12 12
-#define IVG13 13
-#define IVG14 14
-#define IVG15 15
-
-/*
- * DEFAULT PRIORITIES:
- */
-
-#define CONFIG_DEF_PLL_WAKEUP 7
-#define CONFIG_DEF_DMA1_ERROR 7
-#define CONFIG_DEF_DMA2_ERROR 7
-#define CONFIG_DEF_IMDMA_ERROR 7
-#define CONFIG_DEF_PPI1_ERROR 7
-#define CONFIG_DEF_PPI2_ERROR 7
-#define CONFIG_DEF_SPORT0_ERROR 7
-#define CONFIG_DEF_SPORT1_ERROR 7
-#define CONFIG_DEF_SPI_ERROR 7
-#define CONFIG_DEF_UART_ERROR 7
-#define CONFIG_DEF_RESERVED_ERROR 7
-#define CONFIG_DEF_DMA1_0 8
-#define CONFIG_DEF_DMA1_1 8
-#define CONFIG_DEF_DMA1_2 8
-#define CONFIG_DEF_DMA1_3 8
-#define CONFIG_DEF_DMA1_4 8
-#define CONFIG_DEF_DMA1_5 8
-#define CONFIG_DEF_DMA1_6 8
-#define CONFIG_DEF_DMA1_7 8
-#define CONFIG_DEF_DMA1_8 8
-#define CONFIG_DEF_DMA1_9 8
-#define CONFIG_DEF_DMA1_10 8
-#define CONFIG_DEF_DMA1_11 8
-#define CONFIG_DEF_DMA2_0 9
-#define CONFIG_DEF_DMA2_1 9
-#define CONFIG_DEF_DMA2_2 9
-#define CONFIG_DEF_DMA2_3 9
-#define CONFIG_DEF_DMA2_4 9
-#define CONFIG_DEF_DMA2_5 9
-#define CONFIG_DEF_DMA2_6 9
-#define CONFIG_DEF_DMA2_7 9
-#define CONFIG_DEF_DMA2_8 9
-#define CONFIG_DEF_DMA2_9 9
-#define CONFIG_DEF_DMA2_10 9
-#define CONFIG_DEF_DMA2_11 9
-#define CONFIG_DEF_TIMER0 10
-#define CONFIG_DEF_TIMER1 10
-#define CONFIG_DEF_TIMER2 10
-#define CONFIG_DEF_TIMER3 10
-#define CONFIG_DEF_TIMER4 10
-#define CONFIG_DEF_TIMER5 10
-#define CONFIG_DEF_TIMER6 10
-#define CONFIG_DEF_TIMER7 10
-#define CONFIG_DEF_TIMER8 10
-#define CONFIG_DEF_TIMER9 10
-#define CONFIG_DEF_TIMER10 10
-#define CONFIG_DEF_TIMER11 10
-#define CONFIG_DEF_PROG0_INTA 11
-#define CONFIG_DEF_PROG0_INTB 11
-#define CONFIG_DEF_PROG1_INTA 11
-#define CONFIG_DEF_PROG1_INTB 11
-#define CONFIG_DEF_PROG2_INTA 11
-#define CONFIG_DEF_PROG2_INTB 11
-#define CONFIG_DEF_DMA1_WRRD0 8
-#define CONFIG_DEF_DMA1_WRRD1 8
-#define CONFIG_DEF_DMA2_WRRD0 9
-#define CONFIG_DEF_DMA2_WRRD1 9
-#define CONFIG_DEF_IMDMA_WRRD0 12
-#define CONFIG_DEF_IMDMA_WRRD1 12
-#define CONFIG_DEF_WATCH 13
-#define CONFIG_DEF_RESERVED_1 7
-#define CONFIG_DEF_RESERVED_2 7
-#define CONFIG_DEF_SUPPLE_0 7
-#define CONFIG_DEF_SUPPLE_1 7
/* IAR0 BIT FIELDS */
-#define IRQ_PLL_WAKEUP_POS 0
-#define IRQ_DMA1_ERROR_POS 4
-#define IRQ_DMA2_ERROR_POS 8
-#define IRQ_IMDMA_ERROR_POS 12
-#define IRQ_PPI0_ERROR_POS 16
-#define IRQ_PPI1_ERROR_POS 20
-#define IRQ_SPORT0_ERROR_POS 24
-#define IRQ_SPORT1_ERROR_POS 28
-/* IAR1 BIT FIELDS */
-#define IRQ_SPI_ERROR_POS 0
-#define IRQ_UART_ERROR_POS 4
-#define IRQ_RESERVED_ERROR_POS 8
-#define IRQ_DMA1_0_POS 12
-#define IRQ_DMA1_1_POS 16
-#define IRQ_DMA1_2_POS 20
-#define IRQ_DMA1_3_POS 24
-#define IRQ_DMA1_4_POS 28
-/* IAR2 BIT FIELDS */
-#define IRQ_DMA1_5_POS 0
-#define IRQ_DMA1_6_POS 4
-#define IRQ_DMA1_7_POS 8
-#define IRQ_DMA1_8_POS 12
-#define IRQ_DMA1_9_POS 16
-#define IRQ_DMA1_10_POS 20
-#define IRQ_DMA1_11_POS 24
-#define IRQ_DMA2_0_POS 28
-/* IAR3 BIT FIELDS */
-#define IRQ_DMA2_1_POS 0
-#define IRQ_DMA2_2_POS 4
-#define IRQ_DMA2_3_POS 8
-#define IRQ_DMA2_4_POS 12
-#define IRQ_DMA2_5_POS 16
-#define IRQ_DMA2_6_POS 20
-#define IRQ_DMA2_7_POS 24
-#define IRQ_DMA2_8_POS 28
-/* IAR4 BIT FIELDS */
-#define IRQ_DMA2_9_POS 0
-#define IRQ_DMA2_10_POS 4
-#define IRQ_DMA2_11_POS 8
-#define IRQ_TIMER0_POS 12
-#define IRQ_TIMER1_POS 16
-#define IRQ_TIMER2_POS 20
-#define IRQ_TIMER3_POS 24
-#define IRQ_TIMER4_POS 28
-/* IAR5 BIT FIELDS */
-#define IRQ_TIMER5_POS 0
-#define IRQ_TIMER6_POS 4
-#define IRQ_TIMER7_POS 8
-#define IRQ_TIMER8_POS 12
-#define IRQ_TIMER9_POS 16
-#define IRQ_TIMER10_POS 20
-#define IRQ_TIMER11_POS 24
-#define IRQ_PROG0_INTA_POS 28
-/* IAR6 BIT FIELDS */
-#define IRQ_PROG0_INTB_POS 0
-#define IRQ_PROG1_INTA_POS 4
-#define IRQ_PROG1_INTB_POS 8
-#define IRQ_PROG2_INTA_POS 12
-#define IRQ_PROG2_INTB_POS 16
-#define IRQ_DMA1_WRRD0_POS 20
-#define IRQ_DMA1_WRRD1_POS 24
-#define IRQ_DMA2_WRRD0_POS 28
-/* IAR7 BIT FIELDS */
-#define IRQ_DMA2_WRRD1_POS 0
-#define IRQ_IMDMA_WRRD0_POS 4
-#define IRQ_IMDMA_WRRD1_POS 8
-#define IRQ_WDTIMER_POS 12
-#define IRQ_RESERVED_1_POS 16
-#define IRQ_RESERVED_2_POS 20
-#define IRQ_SUPPLE_0_POS 24
-#define IRQ_SUPPLE_1_POS 28
+#define IRQ_PLL_WAKEUP_POS 0
+#define IRQ_DMA1_ERROR_POS 4
+#define IRQ_DMA2_ERROR_POS 8
+#define IRQ_IMDMA_ERROR_POS 12
+#define IRQ_PPI0_ERROR_POS 16
+#define IRQ_PPI1_ERROR_POS 20
+#define IRQ_SPORT0_ERROR_POS 24
+#define IRQ_SPORT1_ERROR_POS 28
-#endif /* _BF561_IRQ_H_ */
+/* IAR1 BIT FIELDS */
+#define IRQ_SPI_ERROR_POS 0
+#define IRQ_UART_ERROR_POS 4
+#define IRQ_RESERVED_ERROR_POS 8
+#define IRQ_DMA1_0_POS 12
+#define IRQ_DMA1_1_POS 16
+#define IRQ_DMA1_2_POS 20
+#define IRQ_DMA1_3_POS 24
+#define IRQ_DMA1_4_POS 28
+
+/* IAR2 BIT FIELDS */
+#define IRQ_DMA1_5_POS 0
+#define IRQ_DMA1_6_POS 4
+#define IRQ_DMA1_7_POS 8
+#define IRQ_DMA1_8_POS 12
+#define IRQ_DMA1_9_POS 16
+#define IRQ_DMA1_10_POS 20
+#define IRQ_DMA1_11_POS 24
+#define IRQ_DMA2_0_POS 28
+
+/* IAR3 BIT FIELDS */
+#define IRQ_DMA2_1_POS 0
+#define IRQ_DMA2_2_POS 4
+#define IRQ_DMA2_3_POS 8
+#define IRQ_DMA2_4_POS 12
+#define IRQ_DMA2_5_POS 16
+#define IRQ_DMA2_6_POS 20
+#define IRQ_DMA2_7_POS 24
+#define IRQ_DMA2_8_POS 28
+
+/* IAR4 BIT FIELDS */
+#define IRQ_DMA2_9_POS 0
+#define IRQ_DMA2_10_POS 4
+#define IRQ_DMA2_11_POS 8
+#define IRQ_TIMER0_POS 12
+#define IRQ_TIMER1_POS 16
+#define IRQ_TIMER2_POS 20
+#define IRQ_TIMER3_POS 24
+#define IRQ_TIMER4_POS 28
+
+/* IAR5 BIT FIELDS */
+#define IRQ_TIMER5_POS 0
+#define IRQ_TIMER6_POS 4
+#define IRQ_TIMER7_POS 8
+#define IRQ_TIMER8_POS 12
+#define IRQ_TIMER9_POS 16
+#define IRQ_TIMER10_POS 20
+#define IRQ_TIMER11_POS 24
+#define IRQ_PROG0_INTA_POS 28
+
+/* IAR6 BIT FIELDS */
+#define IRQ_PROG0_INTB_POS 0
+#define IRQ_PROG1_INTA_POS 4
+#define IRQ_PROG1_INTB_POS 8
+#define IRQ_PROG2_INTA_POS 12
+#define IRQ_PROG2_INTB_POS 16
+#define IRQ_DMA1_WRRD0_POS 20
+#define IRQ_DMA1_WRRD1_POS 24
+#define IRQ_DMA2_WRRD0_POS 28
+
+/* IAR7 BIT FIELDS */
+#define IRQ_DMA2_WRRD1_POS 0
+#define IRQ_IMDMA_WRRD0_POS 4
+#define IRQ_IMDMA_WRRD1_POS 8
+#define IRQ_WDTIMER_POS 12
+#define IRQ_RESERVED_1_POS 16
+#define IRQ_RESERVED_2_POS 20
+#define IRQ_SUPPLE_0_POS 24
+#define IRQ_SUPPLE_1_POS 28
+
+#endif
diff --git a/arch/blackfin/mach-bf561/smp.c b/arch/blackfin/mach-bf561/smp.c
index 7b07740..85abd8b 100644
--- a/arch/blackfin/mach-bf561/smp.c
+++ b/arch/blackfin/mach-bf561/smp.c
@@ -24,17 +24,23 @@
void __init platform_init_cpus(void)
{
- cpu_set(0, cpu_possible_map); /* CoreA */
- cpu_set(1, cpu_possible_map); /* CoreB */
+ struct cpumask mask;
+
+ cpumask_set_cpu(0, &mask); /* CoreA */
+ cpumask_set_cpu(1, &mask); /* CoreB */
+ init_cpu_possible(&mask);
}
void __init platform_prepare_cpus(unsigned int max_cpus)
{
+ struct cpumask mask;
+
bfin_relocate_coreb_l1_mem();
/* Both cores ought to be present on a bf561! */
- cpu_set(0, cpu_present_map); /* CoreA */
- cpu_set(1, cpu_present_map); /* CoreB */
+ cpumask_set_cpu(0, &mask); /* CoreA */
+ cpumask_set_cpu(1, &mask); /* CoreB */
+ init_cpu_present(&mask);
}
int __init setup_profiling_timer(unsigned int multiplier) /* not supported */
@@ -62,9 +68,6 @@
bfin_write_SICB_IWR1(IWR_DISABLE_ALL);
SSYNC();
- /* Store CPU-private information to the cpu_data array. */
- bfin_setup_cpudata(cpu);
-
/* We are done with local CPU inits, unblock the boot CPU. */
set_cpu_online(cpu, true);
spin_lock(&boot_lock);
diff --git a/arch/blackfin/mach-common/dpmc.c b/arch/blackfin/mach-common/dpmc.c
index 5e4112e..f5685a4 100644
--- a/arch/blackfin/mach-common/dpmc.c
+++ b/arch/blackfin/mach-common/dpmc.c
@@ -85,10 +85,11 @@
{
unsigned int cpu;
unsigned int this_cpu = smp_processor_id();
- cpumask_t mask = cpu_online_map;
+ cpumask_t mask;
- cpu_clear(this_cpu, mask);
- for_each_cpu_mask(cpu, mask)
+ cpumask_copy(&mask, cpu_online_mask);
+ cpumask_clear_cpu(this_cpu, &mask);
+ for_each_cpu(cpu, &mask)
platform_send_ipi_cpu(cpu, IRQ_SUPPLE_0);
}
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c
index 43d9fb1..1177369 100644
--- a/arch/blackfin/mach-common/ints-priority.c
+++ b/arch/blackfin/mach-common/ints-priority.c
@@ -19,32 +19,14 @@
#ifdef CONFIG_IPIPE
#include <linux/ipipe.h>
#endif
-#ifdef CONFIG_KGDB
-#include <linux/kgdb.h>
-#endif
#include <asm/traps.h>
#include <asm/blackfin.h>
#include <asm/gpio.h>
#include <asm/irq_handler.h>
#include <asm/dpmc.h>
-#include <asm/bfin5xx_spi.h>
-#include <asm/bfin_sport.h>
-#include <asm/bfin_can.h>
#define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1))
-#ifdef BF537_FAMILY
-# define BF537_GENERIC_ERROR_INT_DEMUX
-# define SPI_ERR_MASK (BIT_STAT_TXCOL | BIT_STAT_RBSY | BIT_STAT_MODF | BIT_STAT_TXE) /* SPI_STAT */
-# define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF) /* SPORT_STAT */
-# define PPI_ERR_MASK (0xFFFF & ~FLD) /* PPI_STATUS */
-# define EMAC_ERR_MASK (PHYINT | MMCINT | RXFSINT | TXFSINT | WAKEDET | RXDMAERR | TXDMAERR | STMDONE) /* EMAC_SYSTAT */
-# define UART_ERR_MASK (0x6) /* UART_IIR */
-# define CAN_ERR_MASK (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | RMLIF | UCEIF | EXTIF | ADIF) /* CAN_GIF */
-#else
-# undef BF537_GENERIC_ERROR_INT_DEMUX
-#endif
-
/*
* NOTES:
* - we have separated the physical Hardware interrupt from the
@@ -63,22 +45,19 @@
EXPORT_SYMBOL(bfin_irq_flags);
#endif
-/* The number of spurious interrupts */
-atomic_t num_spurious;
-
#ifdef CONFIG_PM
unsigned long bfin_sic_iwr[3]; /* Up to 3 SIC_IWRx registers */
unsigned vr_wakeup;
#endif
-struct ivgx {
+static struct ivgx {
/* irq number for request_irq, available in mach-bf5xx/irq.h */
unsigned int irqno;
/* corresponding bit in the SIC_ISR register */
unsigned int isrflag;
} ivg_table[NR_PERI_INTS];
-struct ivg_slice {
+static struct ivg_slice {
/* position of first irq in ivg_table for given ivg */
struct ivgx *ifirst;
struct ivgx *istop;
@@ -125,7 +104,7 @@
* This is for core internal IRQs
*/
-static void bfin_ack_noop(struct irq_data *d)
+void bfin_ack_noop(struct irq_data *d)
{
/* Dummy function. */
}
@@ -154,26 +133,24 @@
return;
}
-static void bfin_internal_mask_irq(unsigned int irq)
+void bfin_internal_mask_irq(unsigned int irq)
{
- unsigned long flags;
+ unsigned long flags = hard_local_irq_save();
-#ifdef CONFIG_BF53x
- flags = hard_local_irq_save();
- bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
- ~(1 << SIC_SYSIRQ(irq)));
-#else
- unsigned mask_bank, mask_bit;
- flags = hard_local_irq_save();
- mask_bank = SIC_SYSIRQ(irq) / 32;
- mask_bit = SIC_SYSIRQ(irq) % 32;
+#ifdef SIC_IMASK0
+ unsigned mask_bank = SIC_SYSIRQ(irq) / 32;
+ unsigned mask_bit = SIC_SYSIRQ(irq) % 32;
bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) &
~(1 << mask_bit));
-#ifdef CONFIG_SMP
+# ifdef CONFIG_SMP
bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) &
~(1 << mask_bit));
+# endif
+#else
+ bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() &
+ ~(1 << SIC_SYSIRQ(irq)));
#endif
-#endif
+
hard_local_irq_restore(flags);
}
@@ -186,33 +163,31 @@
static void bfin_internal_unmask_irq_affinity(unsigned int irq,
const struct cpumask *affinity)
#else
-static void bfin_internal_unmask_irq(unsigned int irq)
+void bfin_internal_unmask_irq(unsigned int irq)
#endif
{
- unsigned long flags;
+ unsigned long flags = hard_local_irq_save();
-#ifdef CONFIG_BF53x
- flags = hard_local_irq_save();
- bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
- (1 << SIC_SYSIRQ(irq)));
-#else
- unsigned mask_bank, mask_bit;
- flags = hard_local_irq_save();
- mask_bank = SIC_SYSIRQ(irq) / 32;
- mask_bit = SIC_SYSIRQ(irq) % 32;
-#ifdef CONFIG_SMP
+#ifdef SIC_IMASK0
+ unsigned mask_bank = SIC_SYSIRQ(irq) / 32;
+ unsigned mask_bit = SIC_SYSIRQ(irq) % 32;
+# ifdef CONFIG_SMP
if (cpumask_test_cpu(0, affinity))
-#endif
+# endif
bfin_write_SIC_IMASK(mask_bank,
bfin_read_SIC_IMASK(mask_bank) |
(1 << mask_bit));
-#ifdef CONFIG_SMP
+# ifdef CONFIG_SMP
if (cpumask_test_cpu(1, affinity))
bfin_write_SICB_IMASK(mask_bank,
bfin_read_SICB_IMASK(mask_bank) |
(1 << mask_bit));
+# endif
+#else
+ bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() |
+ (1 << SIC_SYSIRQ(irq)));
#endif
-#endif
+
hard_local_irq_restore(flags);
}
@@ -295,6 +270,8 @@
{
return bfin_internal_set_wake(d->irq, state);
}
+#else
+# define bfin_internal_set_wake_chip NULL
#endif
static struct irq_chip bfin_core_irqchip = {
@@ -315,12 +292,10 @@
#ifdef CONFIG_SMP
.irq_set_affinity = bfin_internal_set_affinity,
#endif
-#ifdef CONFIG_PM
.irq_set_wake = bfin_internal_set_wake_chip,
-#endif
};
-static void bfin_handle_irq(unsigned irq)
+void bfin_handle_irq(unsigned irq)
{
#ifdef CONFIG_IPIPE
struct pt_regs regs; /* Contents not used. */
@@ -332,102 +307,6 @@
#endif /* !CONFIG_IPIPE */
}
-#ifdef BF537_GENERIC_ERROR_INT_DEMUX
-static int error_int_mask;
-
-static void bfin_generic_error_mask_irq(struct irq_data *d)
-{
- error_int_mask &= ~(1L << (d->irq - IRQ_PPI_ERROR));
- if (!error_int_mask)
- bfin_internal_mask_irq(IRQ_GENERIC_ERROR);
-}
-
-static void bfin_generic_error_unmask_irq(struct irq_data *d)
-{
- bfin_internal_unmask_irq(IRQ_GENERIC_ERROR);
- error_int_mask |= 1L << (d->irq - IRQ_PPI_ERROR);
-}
-
-static struct irq_chip bfin_generic_error_irqchip = {
- .name = "ERROR",
- .irq_ack = bfin_ack_noop,
- .irq_mask_ack = bfin_generic_error_mask_irq,
- .irq_mask = bfin_generic_error_mask_irq,
- .irq_unmask = bfin_generic_error_unmask_irq,
-};
-
-static void bfin_demux_error_irq(unsigned int int_err_irq,
- struct irq_desc *inta_desc)
-{
- int irq = 0;
-
-#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
- if (bfin_read_EMAC_SYSTAT() & EMAC_ERR_MASK)
- irq = IRQ_MAC_ERROR;
- else
-#endif
- if (bfin_read_SPORT0_STAT() & SPORT_ERR_MASK)
- irq = IRQ_SPORT0_ERROR;
- else if (bfin_read_SPORT1_STAT() & SPORT_ERR_MASK)
- irq = IRQ_SPORT1_ERROR;
- else if (bfin_read_PPI_STATUS() & PPI_ERR_MASK)
- irq = IRQ_PPI_ERROR;
- else if (bfin_read_CAN_GIF() & CAN_ERR_MASK)
- irq = IRQ_CAN_ERROR;
- else if (bfin_read_SPI_STAT() & SPI_ERR_MASK)
- irq = IRQ_SPI_ERROR;
- else if ((bfin_read_UART0_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
- irq = IRQ_UART0_ERROR;
- else if ((bfin_read_UART1_IIR() & UART_ERR_MASK) == UART_ERR_MASK)
- irq = IRQ_UART1_ERROR;
-
- if (irq) {
- if (error_int_mask & (1L << (irq - IRQ_PPI_ERROR)))
- bfin_handle_irq(irq);
- else {
-
- switch (irq) {
- case IRQ_PPI_ERROR:
- bfin_write_PPI_STATUS(PPI_ERR_MASK);
- break;
-#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
- case IRQ_MAC_ERROR:
- bfin_write_EMAC_SYSTAT(EMAC_ERR_MASK);
- break;
-#endif
- case IRQ_SPORT0_ERROR:
- bfin_write_SPORT0_STAT(SPORT_ERR_MASK);
- break;
-
- case IRQ_SPORT1_ERROR:
- bfin_write_SPORT1_STAT(SPORT_ERR_MASK);
- break;
-
- case IRQ_CAN_ERROR:
- bfin_write_CAN_GIS(CAN_ERR_MASK);
- break;
-
- case IRQ_SPI_ERROR:
- bfin_write_SPI_STAT(SPI_ERR_MASK);
- break;
-
- default:
- break;
- }
-
- pr_debug("IRQ %d:"
- " MASKED PERIPHERAL ERROR INTERRUPT ASSERTED\n",
- irq);
- }
- } else
- printk(KERN_ERR
- "%s : %s : LINE %d :\nIRQ ?: PERIPHERAL ERROR"
- " INTERRUPT ASSERTED BUT NO SOURCE FOUND\n",
- __func__, __FILE__, __LINE__);
-
-}
-#endif /* BF537_GENERIC_ERROR_INT_DEMUX */
-
#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
static int mac_stat_int_mask;
@@ -468,7 +347,7 @@
unsigned int irq = d->irq;
mac_stat_int_mask &= ~(1L << (irq - IRQ_MAC_PHYINT));
-#ifdef BF537_GENERIC_ERROR_INT_DEMUX
+#ifdef BF537_FAMILY
switch (irq) {
case IRQ_MAC_PHYINT:
bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() & ~PHYIE);
@@ -487,7 +366,7 @@
{
unsigned int irq = d->irq;
-#ifdef BF537_GENERIC_ERROR_INT_DEMUX
+#ifdef BF537_FAMILY
switch (irq) {
case IRQ_MAC_PHYINT:
bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() | PHYIE);
@@ -505,12 +384,14 @@
#ifdef CONFIG_PM
int bfin_mac_status_set_wake(struct irq_data *d, unsigned int state)
{
-#ifdef BF537_GENERIC_ERROR_INT_DEMUX
+#ifdef BF537_FAMILY
return bfin_internal_set_wake(IRQ_GENERIC_ERROR, state);
#else
return bfin_internal_set_wake(IRQ_MAC_ERROR, state);
#endif
}
+#else
+# define bfin_mac_status_set_wake NULL
#endif
static struct irq_chip bfin_mac_status_irqchip = {
@@ -519,13 +400,11 @@
.irq_mask_ack = bfin_mac_status_mask_irq,
.irq_mask = bfin_mac_status_mask_irq,
.irq_unmask = bfin_mac_status_unmask_irq,
-#ifdef CONFIG_PM
.irq_set_wake = bfin_mac_status_set_wake,
-#endif
};
-static void bfin_demux_mac_status_irq(unsigned int int_err_irq,
- struct irq_desc *inta_desc)
+void bfin_demux_mac_status_irq(unsigned int int_err_irq,
+ struct irq_desc *inta_desc)
{
int i, irq = 0;
u32 status = bfin_read_EMAC_SYSTAT();
@@ -680,29 +559,48 @@
}
#ifdef CONFIG_PM
-int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
+static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
{
return gpio_pm_wakeup_ctrl(irq_to_gpio(d->irq), state);
}
+#else
+# define bfin_gpio_set_wake NULL
#endif
-static void bfin_demux_gpio_irq(unsigned int inta_irq,
- struct irq_desc *desc)
+static void bfin_demux_gpio_block(unsigned int irq)
{
- unsigned int i, gpio, mask, irq, search = 0;
+ unsigned int gpio, mask;
+
+ gpio = irq_to_gpio(irq);
+ mask = get_gpiop_data(gpio) & get_gpiop_maska(gpio);
+
+ while (mask) {
+ if (mask & 1)
+ bfin_handle_irq(irq);
+ irq++;
+ mask >>= 1;
+ }
+}
+
+void bfin_demux_gpio_irq(unsigned int inta_irq,
+ struct irq_desc *desc)
+{
+ unsigned int irq;
switch (inta_irq) {
-#if defined(CONFIG_BF53x)
- case IRQ_PROG_INTA:
- irq = IRQ_PF0;
- search = 1;
+#if defined(BF537_FAMILY)
+ case IRQ_PF_INTA_PG_INTA:
+ bfin_demux_gpio_block(IRQ_PF0);
+ irq = IRQ_PG0;
break;
-# if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
- case IRQ_MAC_RX:
+ case IRQ_PH_INTA_MAC_RX:
irq = IRQ_PH0;
break;
-# endif
-#elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
+#elif defined(BF533_FAMILY)
+ case IRQ_PROG_INTA:
+ irq = IRQ_PF0;
+ break;
+#elif defined(BF538_FAMILY)
case IRQ_PORTF_INTA:
irq = IRQ_PF0;
break;
@@ -732,31 +630,7 @@
return;
}
- if (search) {
- for (i = 0; i < MAX_BLACKFIN_GPIOS; i += GPIO_BANKSIZE) {
- irq += i;
-
- mask = get_gpiop_data(i) & get_gpiop_maska(i);
-
- while (mask) {
- if (mask & 1)
- bfin_handle_irq(irq);
- irq++;
- mask >>= 1;
- }
- }
- } else {
- gpio = irq_to_gpio(irq);
- mask = get_gpiop_data(gpio) & get_gpiop_maska(gpio);
-
- do {
- if (mask & 1)
- bfin_handle_irq(irq);
- irq++;
- mask >>= 1;
- } while (mask);
- }
-
+ bfin_demux_gpio_block(irq);
}
#else /* CONFIG_BF54x */
@@ -974,15 +848,11 @@
}
#ifdef CONFIG_PM
-u32 pint_saved_masks[NR_PINT_SYS_IRQS];
-u32 pint_wakeup_masks[NR_PINT_SYS_IRQS];
-
-int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
+static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
{
u32 pint_irq;
u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS];
u32 bank = PINT_2_BANK(pint_val);
- u32 pintbit = PINT_BIT(pint_val);
switch (bank) {
case 0:
@@ -1003,46 +873,14 @@
bfin_internal_set_wake(pint_irq, state);
- if (state)
- pint_wakeup_masks[bank] |= pintbit;
- else
- pint_wakeup_masks[bank] &= ~pintbit;
-
return 0;
}
-
-u32 bfin_pm_setup(void)
-{
- u32 val, i;
-
- for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
- val = pint[i]->mask_clear;
- pint_saved_masks[i] = val;
- if (val ^ pint_wakeup_masks[i]) {
- pint[i]->mask_clear = val;
- pint[i]->mask_set = pint_wakeup_masks[i];
- }
- }
-
- return 0;
-}
-
-void bfin_pm_restore(void)
-{
- u32 i, val;
-
- for (i = 0; i < NR_PINT_SYS_IRQS; i++) {
- val = pint_saved_masks[i];
- if (val ^ pint_wakeup_masks[i]) {
- pint[i]->mask_clear = pint[i]->mask_clear;
- pint[i]->mask_set = val;
- }
- }
-}
+#else
+# define bfin_gpio_set_wake NULL
#endif
-static void bfin_demux_gpio_irq(unsigned int inta_irq,
- struct irq_desc *desc)
+void bfin_demux_gpio_irq(unsigned int inta_irq,
+ struct irq_desc *desc)
{
u32 bank, pint_val;
u32 request, irq;
@@ -1091,9 +929,7 @@
.irq_set_type = bfin_gpio_irq_type,
.irq_startup = bfin_gpio_irq_startup,
.irq_shutdown = bfin_gpio_irq_shutdown,
-#ifdef CONFIG_PM
.irq_set_wake = bfin_gpio_set_wake,
-#endif
};
void __cpuinit init_exception_vectors(void)
@@ -1127,12 +963,12 @@
{
int irq;
unsigned long ilat = 0;
+
/* Disable all the peripheral intrs - page 4-29 HW Ref manual */
-#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x) || defined(CONFIG_BF561) \
- || defined(BF538_FAMILY) || defined(CONFIG_BF51x)
+#ifdef SIC_IMASK0
bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
bfin_write_SIC_IMASK1(SIC_UNMASK_ALL);
-# ifdef CONFIG_BF54x
+# ifdef SIC_IMASK2
bfin_write_SIC_IMASK2(SIC_UNMASK_ALL);
# endif
# ifdef CONFIG_SMP
@@ -1145,11 +981,6 @@
local_irq_disable();
-#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
- /* Clear EMAC Interrupt Status bits so we can demux it later */
- bfin_write_EMAC_SYSTAT(-1);
-#endif
-
#ifdef CONFIG_BF54x
# ifdef CONFIG_PINTx_REASSIGN
pint[0]->assign = CONFIG_PINT0_ASSIGN;
@@ -1168,11 +999,11 @@
irq_set_chip(irq, &bfin_internal_irqchip);
switch (irq) {
-#if defined(CONFIG_BF53x)
+#if defined(BF537_FAMILY)
+ case IRQ_PH_INTA_MAC_RX:
+ case IRQ_PF_INTA_PG_INTA:
+#elif defined(BF533_FAMILY)
case IRQ_PROG_INTA:
-# if defined(BF537_FAMILY) && !(defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
- case IRQ_MAC_RX:
-# endif
#elif defined(CONFIG_BF54x)
case IRQ_PINT0:
case IRQ_PINT1:
@@ -1186,16 +1017,11 @@
case IRQ_PROG0_INTA:
case IRQ_PROG1_INTA:
case IRQ_PROG2_INTA:
-#elif defined(CONFIG_BF538) || defined(CONFIG_BF539)
+#elif defined(BF538_FAMILY)
case IRQ_PORTF_INTA:
#endif
irq_set_chained_handler(irq, bfin_demux_gpio_irq);
break;
-#ifdef BF537_GENERIC_ERROR_INT_DEMUX
- case IRQ_GENERIC_ERROR:
- irq_set_chained_handler(irq, bfin_demux_error_irq);
- break;
-#endif
#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
case IRQ_MAC_ERROR:
irq_set_chained_handler(irq,
@@ -1213,11 +1039,10 @@
case IRQ_CORETMR:
# ifdef CONFIG_SMP
irq_set_handler(irq, handle_percpu_irq);
- break;
# else
irq_set_handler(irq, handle_simple_irq);
- break;
# endif
+ break;
#endif
#ifdef CONFIG_TICKSOURCE_GPTMR0
@@ -1226,26 +1051,17 @@
break;
#endif
+ default:
#ifdef CONFIG_IPIPE
- default:
irq_set_handler(irq, handle_level_irq);
- break;
-#else /* !CONFIG_IPIPE */
- default:
+#else
irq_set_handler(irq, handle_simple_irq);
+#endif
break;
-#endif /* !CONFIG_IPIPE */
}
}
-#ifdef BF537_GENERIC_ERROR_INT_DEMUX
- for (irq = IRQ_PPI_ERROR; irq <= IRQ_UART1_ERROR; irq++)
- irq_set_chip_and_handler(irq, &bfin_generic_error_irqchip,
- handle_level_irq);
-#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
- irq_set_chained_handler(IRQ_MAC_ERROR, bfin_demux_mac_status_irq);
-#endif
-#endif
+ init_mach_irq();
#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
for (irq = IRQ_MAC_PHYINT; irq <= IRQ_MAC_STMDONE; irq++)
@@ -1307,53 +1123,54 @@
#ifdef CONFIG_DO_IRQ_L1
__attribute__((l1_text))
#endif
+static int vec_to_irq(int vec)
+{
+ struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
+ struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
+ unsigned long sic_status[3];
+
+ if (likely(vec == EVT_IVTMR_P))
+ return IRQ_CORETMR;
+
+#ifdef SIC_ISR
+ sic_status[0] = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
+#else
+ if (smp_processor_id()) {
+# ifdef SICB_ISR0
+ /* This will be optimized out in UP mode. */
+ sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0();
+ sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1();
+# endif
+ } else {
+ sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
+ sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
+ }
+#endif
+#ifdef SIC_ISR2
+ sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
+#endif
+
+ for (;; ivg++) {
+ if (ivg >= ivg_stop)
+ return -1;
+#ifdef SIC_ISR
+ if (sic_status[0] & ivg->isrflag)
+#else
+ if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
+#endif
+ return ivg->irqno;
+ }
+}
+
+#ifdef CONFIG_DO_IRQ_L1
+__attribute__((l1_text))
+#endif
void do_irq(int vec, struct pt_regs *fp)
{
- if (vec == EVT_IVTMR_P) {
- vec = IRQ_CORETMR;
- } else {
- struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
- struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
-#if defined(SIC_ISR0)
- unsigned long sic_status[3];
-
- if (smp_processor_id()) {
-# ifdef SICB_ISR0
- /* This will be optimized out in UP mode. */
- sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0();
- sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1();
-# endif
- } else {
- sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
- sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
- }
-# ifdef SIC_ISR2
- sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
-# endif
- for (;; ivg++) {
- if (ivg >= ivg_stop) {
- atomic_inc(&num_spurious);
- return;
- }
- if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
- break;
- }
-#else
- unsigned long sic_status;
-
- sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
-
- for (;; ivg++) {
- if (ivg >= ivg_stop) {
- atomic_inc(&num_spurious);
- return;
- } else if (sic_status & ivg->isrflag)
- break;
- }
-#endif
- vec = ivg->irqno;
- }
- asm_do_IRQ(vec, fp);
+ int irq = vec_to_irq(vec);
+ if (irq == -1)
+ return;
+ asm_do_IRQ(irq, fp);
}
#ifdef CONFIG_IPIPE
@@ -1391,40 +1208,9 @@
struct ivgx *ivg = ivg7_13[vec-IVG7].ifirst;
int irq, s = 0;
- if (likely(vec == EVT_IVTMR_P))
- irq = IRQ_CORETMR;
- else {
-#if defined(SIC_ISR0)
- unsigned long sic_status[3];
-
- sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0();
- sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1();
-# ifdef SIC_ISR2
- sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2();
-# endif
- for (;; ivg++) {
- if (ivg >= ivg_stop) {
- atomic_inc(&num_spurious);
- return 0;
- }
- if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag)
- break;
- }
-#else
- unsigned long sic_status;
-
- sic_status = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
-
- for (;; ivg++) {
- if (ivg >= ivg_stop) {
- atomic_inc(&num_spurious);
- return 0;
- } else if (sic_status & ivg->isrflag)
- break;
- }
-#endif
- irq = ivg->irqno;
- }
+ irq = vec_to_irq(vec);
+ if (irq == -1)
+ return 0;
if (irq == IRQ_SYSTMR) {
#if !defined(CONFIG_GENERIC_CLOCKEVENTS) || defined(CONFIG_TICKSOURCE_GPTMR0)
diff --git a/arch/blackfin/mach-common/smp.c b/arch/blackfin/mach-common/smp.c
index 1fbd94c..35e7e1e 100644
--- a/arch/blackfin/mach-common/smp.c
+++ b/arch/blackfin/mach-common/smp.c
@@ -25,6 +25,7 @@
#include <linux/slab.h>
#include <asm/atomic.h>
#include <asm/cacheflush.h>
+#include <asm/irq_handler.h>
#include <asm/mmu_context.h>
#include <asm/pgtable.h>
#include <asm/pgalloc.h>
@@ -96,7 +97,7 @@
dump_stack();
spin_unlock(&stop_lock);
- cpu_clear(cpu, cpu_online_map);
+ set_cpu_online(cpu, false);
local_irq_disable();
@@ -146,7 +147,7 @@
*/
resync_core_dcache();
#endif
- cpu_clear(cpu, *msg->call_struct.waitmask);
+ cpumask_clear_cpu(cpu, msg->call_struct.waitmask);
}
}
@@ -222,9 +223,10 @@
struct ipi_message_queue *msg_queue;
struct ipi_message *msg;
unsigned long flags, next_msg;
- cpumask_t waitmask = callmap; /* waitmask is shared by all cpus */
+ cpumask_t waitmask; /* waitmask is shared by all cpus */
- for_each_cpu_mask(cpu, callmap) {
+ cpumask_copy(&waitmask, &callmap);
+ for_each_cpu(cpu, &callmap) {
msg_queue = &per_cpu(ipi_msg_queue, cpu);
spin_lock_irqsave(&msg_queue->lock, flags);
if (msg_queue->count < BFIN_IPI_MSGQ_LEN) {
@@ -246,7 +248,7 @@
}
if (wait) {
- while (!cpus_empty(waitmask))
+ while (!cpumask_empty(&waitmask))
blackfin_dcache_invalidate_range(
(unsigned long)(&waitmask),
(unsigned long)(&waitmask));
@@ -265,9 +267,9 @@
cpumask_t callmap;
preempt_disable();
- callmap = cpu_online_map;
- cpu_clear(smp_processor_id(), callmap);
- if (!cpus_empty(callmap))
+ cpumask_copy(&callmap, cpu_online_mask);
+ cpumask_clear_cpu(smp_processor_id(), &callmap);
+ if (!cpumask_empty(&callmap))
smp_send_message(callmap, BFIN_IPI_CALL_FUNC, func, info, wait);
preempt_enable();
@@ -284,8 +286,8 @@
if (cpu_is_offline(cpu))
return 0;
- cpus_clear(callmap);
- cpu_set(cpu, callmap);
+ cpumask_clear(&callmap);
+ cpumask_set_cpu(cpu, &callmap);
smp_send_message(callmap, BFIN_IPI_CALL_FUNC, func, info, wait);
@@ -308,9 +310,9 @@
cpumask_t callmap;
preempt_disable();
- callmap = cpu_online_map;
- cpu_clear(smp_processor_id(), callmap);
- if (!cpus_empty(callmap))
+ cpumask_copy(&callmap, cpu_online_mask);
+ cpumask_clear_cpu(smp_processor_id(), &callmap);
+ if (!cpumask_empty(&callmap))
smp_send_message(callmap, BFIN_IPI_CPU_STOP, NULL, NULL, 0);
preempt_enable();
diff --git a/arch/blackfin/mm/sram-alloc.c b/arch/blackfin/mm/sram-alloc.c
index dfd304a..29d98fa 100644
--- a/arch/blackfin/mm/sram-alloc.c
+++ b/arch/blackfin/mm/sram-alloc.c
@@ -15,6 +15,7 @@
#include <linux/init.h>
#include <linux/poll.h>
#include <linux/proc_fs.h>
+#include <linux/seq_file.h>
#include <linux/spinlock.h>
#include <linux/rtc.h>
#include <linux/slab.h>
@@ -764,7 +765,7 @@
/* Need to keep line of output the same. Currently, that is 44 bytes
* (including newline).
*/
-static int _sram_proc_read(char *buf, int *len, int count, const char *desc,
+static int _sram_proc_show(struct seq_file *m, const char *desc,
struct sram_piece *pfree_head,
struct sram_piece *pused_head)
{
@@ -773,13 +774,13 @@
if (!pfree_head || !pused_head)
return -1;
- *len += sprintf(&buf[*len], "--- SRAM %-14s Size PID State \n", desc);
+ seq_printf(m, "--- SRAM %-14s Size PID State \n", desc);
/* search the relevant memory slot */
pslot = pused_head->next;
while (pslot != NULL) {
- *len += sprintf(&buf[*len], "%p-%p %10i %5i %-10s\n",
+ seq_printf(m, "%p-%p %10i %5i %-10s\n",
pslot->paddr, pslot->paddr + pslot->size,
pslot->size, pslot->pid, "ALLOCATED");
@@ -789,7 +790,7 @@
pslot = pfree_head->next;
while (pslot != NULL) {
- *len += sprintf(&buf[*len], "%p-%p %10i %5i %-10s\n",
+ seq_printf(m, "%p-%p %10i %5i %-10s\n",
pslot->paddr, pslot->paddr + pslot->size,
pslot->size, pslot->pid, "FREE");
@@ -798,54 +799,62 @@
return 0;
}
-static int sram_proc_read(char *buf, char **start, off_t offset, int count,
- int *eof, void *data)
+static int sram_proc_show(struct seq_file *m, void *v)
{
- int len = 0;
unsigned int cpu;
for (cpu = 0; cpu < num_possible_cpus(); ++cpu) {
- if (_sram_proc_read(buf, &len, count, "Scratchpad",
+ if (_sram_proc_show(m, "Scratchpad",
&per_cpu(free_l1_ssram_head, cpu), &per_cpu(used_l1_ssram_head, cpu)))
goto not_done;
#if L1_DATA_A_LENGTH != 0
- if (_sram_proc_read(buf, &len, count, "L1 Data A",
+ if (_sram_proc_show(m, "L1 Data A",
&per_cpu(free_l1_data_A_sram_head, cpu),
&per_cpu(used_l1_data_A_sram_head, cpu)))
goto not_done;
#endif
#if L1_DATA_B_LENGTH != 0
- if (_sram_proc_read(buf, &len, count, "L1 Data B",
+ if (_sram_proc_show(m, "L1 Data B",
&per_cpu(free_l1_data_B_sram_head, cpu),
&per_cpu(used_l1_data_B_sram_head, cpu)))
goto not_done;
#endif
#if L1_CODE_LENGTH != 0
- if (_sram_proc_read(buf, &len, count, "L1 Instruction",
+ if (_sram_proc_show(m, "L1 Instruction",
&per_cpu(free_l1_inst_sram_head, cpu),
&per_cpu(used_l1_inst_sram_head, cpu)))
goto not_done;
#endif
}
#if L2_LENGTH != 0
- if (_sram_proc_read(buf, &len, count, "L2", &free_l2_sram_head,
- &used_l2_sram_head))
+ if (_sram_proc_show(m, "L2", &free_l2_sram_head, &used_l2_sram_head))
goto not_done;
#endif
- *eof = 1;
not_done:
- return len;
+ return 0;
}
+static int sram_proc_open(struct inode *inode, struct file *file)
+{
+ return single_open(file, sram_proc_show, NULL);
+}
+
+static const struct file_operations sram_proc_ops = {
+ .open = sram_proc_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = single_release,
+};
+
static int __init sram_proc_init(void)
{
struct proc_dir_entry *ptr;
- ptr = create_proc_entry("sram", S_IFREG | S_IRUGO, NULL);
+
+ ptr = proc_create("sram", S_IRUGO, NULL, &sram_proc_ops);
if (!ptr) {
printk(KERN_WARNING "unable to create /proc/sram\n");
return -1;
}
- ptr->read_proc = sram_proc_read;
return 0;
}
late_initcall(sram_proc_init);
diff --git a/arch/cris/arch-v32/kernel/irq.c b/arch/cris/arch-v32/kernel/irq.c
index 68a1a59..5ebe6e8 100644
--- a/arch/cris/arch-v32/kernel/irq.c
+++ b/arch/cris/arch-v32/kernel/irq.c
@@ -266,11 +266,11 @@
/* Let the interrupt stay if possible */
- if (cpu_isset(cpu, irq_allocations[irq - FIRST_IRQ].mask))
+ if (cpumask_test_cpu(cpu, &irq_allocations[irq - FIRST_IRQ].mask))
goto out;
/* IRQ must be moved to another CPU. */
- cpu = first_cpu(irq_allocations[irq - FIRST_IRQ].mask);
+ cpu = cpumask_first(&irq_allocations[irq - FIRST_IRQ].mask);
irq_allocations[irq - FIRST_IRQ].cpu = cpu;
out:
spin_unlock_irqrestore(&irq_lock, flags);
diff --git a/arch/cris/arch-v32/kernel/smp.c b/arch/cris/arch-v32/kernel/smp.c
index 66cc756..a0843a7 100644
--- a/arch/cris/arch-v32/kernel/smp.c
+++ b/arch/cris/arch-v32/kernel/smp.c
@@ -81,7 +81,7 @@
/* Mark all possible CPUs as present */
for (i = 0; i < max_cpus; i++)
- cpu_set(i, phys_cpu_present_map);
+ cpumask_set_cpu(i, &phys_cpu_present_map);
}
void __devinit smp_prepare_boot_cpu(void)
@@ -98,7 +98,7 @@
SUPP_REG_WR(RW_MM_TLB_PGD, pgd);
set_cpu_online(0, true);
- cpu_set(0, phys_cpu_present_map);
+ cpumask_set_cpu(0, &phys_cpu_present_map);
set_cpu_possible(0, true);
}
@@ -112,8 +112,9 @@
{
unsigned timeout;
struct task_struct *idle;
- cpumask_t cpu_mask = CPU_MASK_NONE;
+ cpumask_t cpu_mask;
+ cpumask_clear(&cpu_mask);
idle = fork_idle(cpuid);
if (IS_ERR(idle))
panic("SMP: fork failed for CPU:%d", cpuid);
@@ -125,10 +126,10 @@
cpu_now_booting = cpuid;
/* Kick it */
- cpu_set(cpuid, cpu_online_map);
- cpu_set(cpuid, cpu_mask);
+ set_cpu_online(cpuid, true);
+ cpumask_set_cpu(cpuid, &cpu_mask);
send_ipi(IPI_BOOT, 0, cpu_mask);
- cpu_clear(cpuid, cpu_online_map);
+ set_cpu_online(cpuid, false);
/* Wait for CPU to come online */
for (timeout = 0; timeout < 10000; timeout++) {
@@ -176,7 +177,7 @@
notify_cpu_starting(cpu);
local_irq_enable();
- cpu_set(cpu, cpu_online_map);
+ set_cpu_online(cpu, true);
cpu_idle();
}
@@ -214,8 +215,9 @@
void smp_send_reschedule(int cpu)
{
- cpumask_t cpu_mask = CPU_MASK_NONE;
- cpu_set(cpu, cpu_mask);
+ cpumask_t cpu_mask;
+ cpumask_clear(&cpu_mask);
+ cpumask_set_cpu(cpu, &cpu_mask);
send_ipi(IPI_SCHEDULE, 0, cpu_mask);
}
@@ -232,7 +234,7 @@
spin_lock_irqsave(&tlbstate_lock, flags);
cpu_mask = (mm == FLUSH_ALL ? cpu_all_mask : *mm_cpumask(mm));
- cpu_clear(smp_processor_id(), cpu_mask);
+ cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
flush_mm = mm;
flush_vma = vma;
flush_addr = addr;
@@ -277,10 +279,10 @@
int ret = 0;
/* Calculate CPUs to send to. */
- cpus_and(cpu_mask, cpu_mask, cpu_online_map);
+ cpumask_and(&cpu_mask, &cpu_mask, cpu_online_mask);
/* Send the IPI. */
- for_each_cpu_mask(i, cpu_mask)
+ for_each_cpu(i, &cpu_mask)
{
ipi.vector |= vector;
REG_WR(intr_vect, irq_regs[i], rw_ipi, ipi);
@@ -288,7 +290,7 @@
/* Wait for IPI to finish on other CPUS */
if (wait) {
- for_each_cpu_mask(i, cpu_mask) {
+ for_each_cpu(i, &cpu_mask) {
int j;
for (j = 0 ; j < 1000; j++) {
ipi = REG_RD(intr_vect, irq_regs[i], rw_ipi);
@@ -314,11 +316,12 @@
*/
int smp_call_function(void (*func)(void *info), void *info, int wait)
{
- cpumask_t cpu_mask = CPU_MASK_ALL;
+ cpumask_t cpu_mask;
struct call_data_struct data;
int ret;
- cpu_clear(smp_processor_id(), cpu_mask);
+ cpumask_setall(&cpu_mask);
+ cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
WARN_ON(irqs_disabled());
diff --git a/arch/cris/kernel/vmlinux.lds.S b/arch/cris/kernel/vmlinux.lds.S
index 728bbd9..a6990cb 100644
--- a/arch/cris/kernel/vmlinux.lds.S
+++ b/arch/cris/kernel/vmlinux.lds.S
@@ -102,7 +102,7 @@
#endif
__vmlinux_end = .; /* Last address of the physical file. */
#ifdef CONFIG_ETRAX_ARCH_V32
- PERCPU(32, PAGE_SIZE)
+ PERCPU_SECTION(32)
.init.ramfs : {
INIT_RAM_FS
diff --git a/arch/cris/mm/init.c b/arch/cris/mm/init.c
index df33ab8..d72ab58 100644
--- a/arch/cris/mm/init.c
+++ b/arch/cris/mm/init.c
@@ -13,8 +13,6 @@
#include <linux/bootmem.h>
#include <asm/tlb.h>
-DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
-
unsigned long empty_zero_page;
extern char _stext, _edata, _etext; /* From linkerscript */
diff --git a/arch/frv/kernel/vmlinux.lds.S b/arch/frv/kernel/vmlinux.lds.S
index 0daae8a..7e958d8 100644
--- a/arch/frv/kernel/vmlinux.lds.S
+++ b/arch/frv/kernel/vmlinux.lds.S
@@ -37,7 +37,7 @@
_einittext = .;
INIT_DATA_SECTION(8)
- PERCPU(L1_CACHE_BYTES, 4096)
+ PERCPU_SECTION(L1_CACHE_BYTES)
. = ALIGN(PAGE_SIZE);
__init_end = .;
diff --git a/arch/frv/mm/init.c b/arch/frv/mm/init.c
index ed64588..fbe5f0d 100644
--- a/arch/frv/mm/init.c
+++ b/arch/frv/mm/init.c
@@ -41,8 +41,6 @@
#undef DEBUG
-DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
-
/*
* BAD_PAGE is the page that is used for page faults when linux
* is out-of-memory. Older versions of linux just did a
diff --git a/arch/ia64/include/asm/tlb.h b/arch/ia64/include/asm/tlb.h
index 23cce99..c3ffe3e 100644
--- a/arch/ia64/include/asm/tlb.h
+++ b/arch/ia64/include/asm/tlb.h
@@ -47,21 +47,27 @@
#include <asm/machvec.h>
#ifdef CONFIG_SMP
-# define FREE_PTE_NR 2048
# define tlb_fast_mode(tlb) ((tlb)->nr == ~0U)
#else
-# define FREE_PTE_NR 0
# define tlb_fast_mode(tlb) (1)
#endif
+/*
+ * If we can't allocate a page to make a big batch of page pointers
+ * to work on, then just handle a few from the on-stack structure.
+ */
+#define IA64_GATHER_BUNDLE 8
+
struct mmu_gather {
struct mm_struct *mm;
unsigned int nr; /* == ~0U => fast mode */
+ unsigned int max;
unsigned char fullmm; /* non-zero means full mm flush */
unsigned char need_flush; /* really unmapped some PTEs? */
unsigned long start_addr;
unsigned long end_addr;
- struct page *pages[FREE_PTE_NR];
+ struct page **pages;
+ struct page *local[IA64_GATHER_BUNDLE];
};
struct ia64_tr_entry {
@@ -90,9 +96,6 @@
#define RR_RID_MASK 0x00000000ffffff00L
#define RR_TO_RID(val) ((val >> 8) & 0xffffff)
-/* Users of the generic TLB shootdown code must declare this storage space. */
-DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
-
/*
* Flush the TLB for address range START to END and, if not in fast mode, release the
* freed pages that where gathered up to this point.
@@ -147,15 +150,23 @@
}
}
-/*
- * Return a pointer to an initialized struct mmu_gather.
- */
-static inline struct mmu_gather *
-tlb_gather_mmu (struct mm_struct *mm, unsigned int full_mm_flush)
+static inline void __tlb_alloc_page(struct mmu_gather *tlb)
{
- struct mmu_gather *tlb = &get_cpu_var(mmu_gathers);
+ unsigned long addr = __get_free_pages(GFP_NOWAIT | __GFP_NOWARN, 0);
+ if (addr) {
+ tlb->pages = (void *)addr;
+ tlb->max = PAGE_SIZE / sizeof(void *);
+ }
+}
+
+
+static inline void
+tlb_gather_mmu(struct mmu_gather *tlb, struct mm_struct *mm, unsigned int full_mm_flush)
+{
tlb->mm = mm;
+ tlb->max = ARRAY_SIZE(tlb->local);
+ tlb->pages = tlb->local;
/*
* Use fast mode if only 1 CPU is online.
*
@@ -172,7 +183,6 @@
tlb->nr = (num_online_cpus() == 1) ? ~0U : 0;
tlb->fullmm = full_mm_flush;
tlb->start_addr = ~0UL;
- return tlb;
}
/*
@@ -180,7 +190,7 @@
* collected.
*/
static inline void
-tlb_finish_mmu (struct mmu_gather *tlb, unsigned long start, unsigned long end)
+tlb_finish_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end)
{
/*
* Note: tlb->nr may be 0 at this point, so we can't rely on tlb->start_addr and
@@ -191,7 +201,8 @@
/* keep the page table cache within bounds */
check_pgt_cache();
- put_cpu_var(mmu_gathers);
+ if (tlb->pages != tlb->local)
+ free_pages((unsigned long)tlb->pages, 0);
}
/*
@@ -199,18 +210,33 @@
* must be delayed until after the TLB has been flushed (see comments at the beginning of
* this file).
*/
-static inline void
-tlb_remove_page (struct mmu_gather *tlb, struct page *page)
+static inline int __tlb_remove_page(struct mmu_gather *tlb, struct page *page)
{
tlb->need_flush = 1;
if (tlb_fast_mode(tlb)) {
free_page_and_swap_cache(page);
- return;
+ return 1; /* avoid calling tlb_flush_mmu */
}
+
+ if (!tlb->nr && tlb->pages == tlb->local)
+ __tlb_alloc_page(tlb);
+
tlb->pages[tlb->nr++] = page;
- if (tlb->nr >= FREE_PTE_NR)
- ia64_tlb_flush_mmu(tlb, tlb->start_addr, tlb->end_addr);
+ VM_BUG_ON(tlb->nr > tlb->max);
+
+ return tlb->max - tlb->nr;
+}
+
+static inline void tlb_flush_mmu(struct mmu_gather *tlb)
+{
+ ia64_tlb_flush_mmu(tlb, tlb->start_addr, tlb->end_addr);
+}
+
+static inline void tlb_remove_page(struct mmu_gather *tlb, struct page *page)
+{
+ if (!__tlb_remove_page(tlb, page))
+ tlb_flush_mmu(tlb);
}
/*
diff --git a/arch/ia64/mm/contig.c b/arch/ia64/mm/contig.c
index 9a018cd..f114a3b 100644
--- a/arch/ia64/mm/contig.c
+++ b/arch/ia64/mm/contig.c
@@ -44,13 +44,16 @@
pg_data_t *pgdat;
printk(KERN_INFO "Mem-info:\n");
- show_free_areas();
+ show_free_areas(filter);
printk(KERN_INFO "Node memory in pages:\n");
for_each_online_pgdat(pgdat) {
unsigned long present;
unsigned long flags;
int shared = 0, cached = 0, reserved = 0;
+ int nid = pgdat->node_id;
+ if (skip_free_areas_node(filter, nid))
+ continue;
pgdat_resize_lock(pgdat, &flags);
present = pgdat->node_present_pages;
for(i = 0; i < pgdat->node_spanned_pages; i++) {
@@ -64,8 +67,7 @@
if (max_gap < LARGE_GAP)
continue;
#endif
- i = vmemmap_find_next_valid_pfn(pgdat->node_id,
- i) - 1;
+ i = vmemmap_find_next_valid_pfn(nid, i) - 1;
continue;
}
if (PageReserved(page))
@@ -81,7 +83,7 @@
total_cached += cached;
total_shared += shared;
printk(KERN_INFO "Node %4d: RAM: %11ld, rsvd: %8d, "
- "shrd: %10d, swpd: %10d\n", pgdat->node_id,
+ "shrd: %10d, swpd: %10d\n", nid,
present, reserved, shared, cached);
}
printk(KERN_INFO "%ld pages of RAM\n", total_present);
diff --git a/arch/ia64/mm/discontig.c b/arch/ia64/mm/discontig.c
index 82ab1bc..c641333 100644
--- a/arch/ia64/mm/discontig.c
+++ b/arch/ia64/mm/discontig.c
@@ -622,13 +622,16 @@
pg_data_t *pgdat;
printk(KERN_INFO "Mem-info:\n");
- show_free_areas();
+ show_free_areas(filter);
printk(KERN_INFO "Node memory in pages:\n");
for_each_online_pgdat(pgdat) {
unsigned long present;
unsigned long flags;
int shared = 0, cached = 0, reserved = 0;
+ int nid = pgdat->node_id;
+ if (skip_free_areas_node(filter, nid))
+ continue;
pgdat_resize_lock(pgdat, &flags);
present = pgdat->node_present_pages;
for(i = 0; i < pgdat->node_spanned_pages; i++) {
@@ -638,8 +641,7 @@
if (pfn_valid(pgdat->node_start_pfn + i))
page = pfn_to_page(pgdat->node_start_pfn + i);
else {
- i = vmemmap_find_next_valid_pfn(pgdat->node_id,
- i) - 1;
+ i = vmemmap_find_next_valid_pfn(nid, i) - 1;
continue;
}
if (PageReserved(page))
@@ -655,7 +657,7 @@
total_cached += cached;
total_shared += shared;
printk(KERN_INFO "Node %4d: RAM: %11ld, rsvd: %8d, "
- "shrd: %10d, swpd: %10d\n", pgdat->node_id,
+ "shrd: %10d, swpd: %10d\n", nid,
present, reserved, shared, cached);
}
printk(KERN_INFO "%ld pages of RAM\n", total_present);
diff --git a/arch/ia64/mm/init.c b/arch/ia64/mm/init.c
index ed41759..00cb0e2 100644
--- a/arch/ia64/mm/init.c
+++ b/arch/ia64/mm/init.c
@@ -36,8 +36,6 @@
#include <asm/mca.h>
#include <asm/paravirt.h>
-DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
-
extern void ia64_tlb_init (void);
unsigned long MAX_DMA_ADDRESS = PAGE_OFFSET + 0x100000000UL;
diff --git a/arch/m32r/Kconfig.debug b/arch/m32r/Kconfig.debug
index 2e1019d..bb1afc1 100644
--- a/arch/m32r/Kconfig.debug
+++ b/arch/m32r/Kconfig.debug
@@ -9,15 +9,6 @@
This option will cause messages to be printed if free stack space
drops below a certain limit.
-config DEBUG_STACK_USAGE
- bool "Stack utilization instrumentation"
- depends on DEBUG_KERNEL
- help
- Enables the display of the minimum amount of free stack which each
- task has ever had available in the sysrq-T and sysrq-P debug output.
-
- This option will slow down process creation somewhat.
-
config DEBUG_PAGEALLOC
bool "Debug page memory allocations"
depends on DEBUG_KERNEL && BROKEN
diff --git a/arch/m32r/include/asm/smp.h b/arch/m32r/include/asm/smp.h
index e67ded1..8accc1b 100644
--- a/arch/m32r/include/asm/smp.h
+++ b/arch/m32r/include/asm/smp.h
@@ -94,8 +94,6 @@
#define NO_PROC_ID (0xff) /* No processor magic marker */
-#define PROC_CHANGE_PENALTY (15) /* Schedule penalty */
-
/*
* M32R-mp IPI
*/
diff --git a/arch/m32r/kernel/vmlinux.lds.S b/arch/m32r/kernel/vmlinux.lds.S
index cf95aec..018e4a7 100644
--- a/arch/m32r/kernel/vmlinux.lds.S
+++ b/arch/m32r/kernel/vmlinux.lds.S
@@ -54,7 +54,7 @@
__init_begin = .;
INIT_TEXT_SECTION(PAGE_SIZE)
INIT_DATA_SECTION(16)
- PERCPU(32, PAGE_SIZE)
+ PERCPU_SECTION(32)
. = ALIGN(PAGE_SIZE);
__init_end = .;
/* freed after init ends here */
diff --git a/arch/m32r/mm/discontig.c b/arch/m32r/mm/discontig.c
index 5d2858f..2c468e8 100644
--- a/arch/m32r/mm/discontig.c
+++ b/arch/m32r/mm/discontig.c
@@ -149,6 +149,7 @@
zholes_size[ZONE_DMA] = mp->holes;
holes += zholes_size[ZONE_DMA];
+ node_set_state(nid, N_NORMAL_MEMORY);
free_area_init_node(nid, zones_size, start_pfn, zholes_size);
}
diff --git a/arch/m32r/mm/init.c b/arch/m32r/mm/init.c
index 73e2205..78b660e 100644
--- a/arch/m32r/mm/init.c
+++ b/arch/m32r/mm/init.c
@@ -35,8 +35,6 @@
pgd_t swapper_pg_dir[1024];
-DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
-
/*
* Cache of MMU context last used.
*/
diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig
index 75531da..d66e34c 100644
--- a/arch/m68k/Kconfig
+++ b/arch/m68k/Kconfig
@@ -5,6 +5,7 @@
select HAVE_AOUT if MMU
select GENERIC_ATOMIC64 if MMU
select HAVE_GENERIC_HARDIRQS if !MMU
+ select GENERIC_IRQ_SHOW if !MMU
config RWSEM_GENERIC_SPINLOCK
bool
diff --git a/arch/m68k/include/asm/bitops_no.h b/arch/m68k/include/asm/bitops_no.h
index 7d3779f..6b0e2d3 100644
--- a/arch/m68k/include/asm/bitops_no.h
+++ b/arch/m68k/include/asm/bitops_no.h
@@ -246,23 +246,7 @@
return retval;
}
-#define ext2_set_bit_atomic(lock, nr, addr) \
- ({ \
- int ret; \
- spin_lock(lock); \
- ret = __test_and_set_bit_le((nr), (addr)); \
- spin_unlock(lock); \
- ret; \
- })
-
-#define ext2_clear_bit_atomic(lock, nr, addr) \
- ({ \
- int ret; \
- spin_lock(lock); \
- ret = __test_and_clear_bit_le((nr), (addr)); \
- spin_unlock(lock); \
- ret; \
- })
+#include <asm-generic/bitops/ext2-atomic.h>
static inline int test_bit_le(int nr, const volatile void *addr)
{
diff --git a/arch/m68k/include/asm/io_no.h b/arch/m68k/include/asm/io_no.h
index cf20f30..353bf75 100644
--- a/arch/m68k/include/asm/io_no.h
+++ b/arch/m68k/include/asm/io_no.h
@@ -144,8 +144,10 @@
#define IOMAP_NOCACHE_NONSER 2
#define IOMAP_WRITETHROUGH 3
-extern void *__ioremap(unsigned long physaddr, unsigned long size, int cacheflag);
-
+static inline void *__ioremap(unsigned long physaddr, unsigned long size, int cacheflag)
+{
+ return (void *) physaddr;
+}
static inline void *ioremap(unsigned long physaddr, unsigned long size)
{
return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
@@ -163,7 +165,7 @@
return __ioremap(physaddr, size, IOMAP_FULL_CACHING);
}
-extern void iounmap(void *addr);
+#define iounmap(addr) do { } while(0)
/*
* Convert a physical pointer to a virtual kernel pointer for /dev/mem
diff --git a/arch/m68k/kernel/asm-offsets.c b/arch/m68k/kernel/asm-offsets.c
index 59a69a5..983fed9 100644
--- a/arch/m68k/kernel/asm-offsets.c
+++ b/arch/m68k/kernel/asm-offsets.c
@@ -1,5 +1,105 @@
-#ifdef CONFIG_MMU
-#include "asm-offsets_mm.c"
+/*
+ * This program is used to generate definitions needed by
+ * assembly language modules.
+ *
+ * We use the technique used in the OSF Mach kernel code:
+ * generate asm statements containing #defines,
+ * compile this file to assembler, and then extract the
+ * #defines from the assembly-language output.
+ */
+
+#define ASM_OFFSETS_C
+
+#include <linux/stddef.h>
+#include <linux/sched.h>
+#include <linux/kernel_stat.h>
+#include <linux/kbuild.h>
+#include <asm/bootinfo.h>
+#include <asm/irq.h>
+#include <asm/amigahw.h>
+#include <linux/font.h>
+
+int main(void)
+{
+ /* offsets into the task struct */
+ DEFINE(TASK_THREAD, offsetof(struct task_struct, thread));
+ DEFINE(TASK_MM, offsetof(struct task_struct, mm));
+ DEFINE(TASK_INFO, offsetof(struct task_struct, thread.info));
+ DEFINE(TASK_TINFO, offsetof(struct task_struct, thread.info));
+
+ /* offsets into the thread struct */
+ DEFINE(THREAD_KSP, offsetof(struct thread_struct, ksp));
+ DEFINE(THREAD_USP, offsetof(struct thread_struct, usp));
+ DEFINE(THREAD_SR, offsetof(struct thread_struct, sr));
+ DEFINE(THREAD_FS, offsetof(struct thread_struct, fs));
+ DEFINE(THREAD_CRP, offsetof(struct thread_struct, crp));
+ DEFINE(THREAD_ESP0, offsetof(struct thread_struct, esp0));
+ DEFINE(THREAD_FPREG, offsetof(struct thread_struct, fp));
+ DEFINE(THREAD_FPCNTL, offsetof(struct thread_struct, fpcntl));
+ DEFINE(THREAD_FPSTATE, offsetof(struct thread_struct, fpstate));
+
+ /* offsets into the thread_info struct */
+ DEFINE(TINFO_PREEMPT, offsetof(struct thread_info, preempt_count));
+ DEFINE(TINFO_FLAGS, offsetof(struct thread_info, flags));
+
+ /* offsets into the pt_regs */
+ DEFINE(PT_OFF_D0, offsetof(struct pt_regs, d0));
+ DEFINE(PT_OFF_ORIG_D0, offsetof(struct pt_regs, orig_d0));
+ DEFINE(PT_OFF_D1, offsetof(struct pt_regs, d1));
+ DEFINE(PT_OFF_D2, offsetof(struct pt_regs, d2));
+ DEFINE(PT_OFF_D3, offsetof(struct pt_regs, d3));
+ DEFINE(PT_OFF_D4, offsetof(struct pt_regs, d4));
+ DEFINE(PT_OFF_D5, offsetof(struct pt_regs, d5));
+ DEFINE(PT_OFF_A0, offsetof(struct pt_regs, a0));
+ DEFINE(PT_OFF_A1, offsetof(struct pt_regs, a1));
+ DEFINE(PT_OFF_A2, offsetof(struct pt_regs, a2));
+ DEFINE(PT_OFF_PC, offsetof(struct pt_regs, pc));
+ DEFINE(PT_OFF_SR, offsetof(struct pt_regs, sr));
+
+ /* bitfields are a bit difficult */
+#ifdef CONFIG_COLDFIRE
+ DEFINE(PT_OFF_FORMATVEC, offsetof(struct pt_regs, sr) - 2);
#else
-#include "asm-offsets_no.c"
+ DEFINE(PT_OFF_FORMATVEC, offsetof(struct pt_regs, pc) + 4);
#endif
+
+ /* offsets into the irq_cpustat_t struct */
+ DEFINE(CPUSTAT_SOFTIRQ_PENDING, offsetof(irq_cpustat_t, __softirq_pending));
+
+ /* signal defines */
+ DEFINE(LSIGSEGV, SIGSEGV);
+ DEFINE(LSEGV_MAPERR, SEGV_MAPERR);
+ DEFINE(LSIGTRAP, SIGTRAP);
+ DEFINE(LTRAP_TRACE, TRAP_TRACE);
+
+#ifdef CONFIG_MMU
+ /* offsets into the bi_record struct */
+ DEFINE(BIR_TAG, offsetof(struct bi_record, tag));
+ DEFINE(BIR_SIZE, offsetof(struct bi_record, size));
+ DEFINE(BIR_DATA, offsetof(struct bi_record, data));
+
+ /* offsets into font_desc (drivers/video/console/font.h) */
+ DEFINE(FONT_DESC_IDX, offsetof(struct font_desc, idx));
+ DEFINE(FONT_DESC_NAME, offsetof(struct font_desc, name));
+ DEFINE(FONT_DESC_WIDTH, offsetof(struct font_desc, width));
+ DEFINE(FONT_DESC_HEIGHT, offsetof(struct font_desc, height));
+ DEFINE(FONT_DESC_DATA, offsetof(struct font_desc, data));
+ DEFINE(FONT_DESC_PREF, offsetof(struct font_desc, pref));
+
+ /* offsets into the custom struct */
+ DEFINE(CUSTOMBASE, &amiga_custom);
+ DEFINE(C_INTENAR, offsetof(struct CUSTOM, intenar));
+ DEFINE(C_INTREQR, offsetof(struct CUSTOM, intreqr));
+ DEFINE(C_INTENA, offsetof(struct CUSTOM, intena));
+ DEFINE(C_INTREQ, offsetof(struct CUSTOM, intreq));
+ DEFINE(C_SERDATR, offsetof(struct CUSTOM, serdatr));
+ DEFINE(C_SERDAT, offsetof(struct CUSTOM, serdat));
+ DEFINE(C_SERPER, offsetof(struct CUSTOM, serper));
+ DEFINE(CIAABASE, &ciaa);
+ DEFINE(CIABBASE, &ciab);
+ DEFINE(C_PRA, offsetof(struct CIA, pra));
+ DEFINE(ZTWOBASE, zTwoBase);
+#endif
+
+ return 0;
+}
diff --git a/arch/m68k/kernel/asm-offsets_mm.c b/arch/m68k/kernel/asm-offsets_mm.c
deleted file mode 100644
index 78e59b8..0000000
--- a/arch/m68k/kernel/asm-offsets_mm.c
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * This program is used to generate definitions needed by
- * assembly language modules.
- *
- * We use the technique used in the OSF Mach kernel code:
- * generate asm statements containing #defines,
- * compile this file to assembler, and then extract the
- * #defines from the assembly-language output.
- */
-
-#define ASM_OFFSETS_C
-
-#include <linux/stddef.h>
-#include <linux/sched.h>
-#include <linux/kernel_stat.h>
-#include <linux/kbuild.h>
-#include <asm/bootinfo.h>
-#include <asm/irq.h>
-#include <asm/amigahw.h>
-#include <linux/font.h>
-
-int main(void)
-{
- /* offsets into the task struct */
- DEFINE(TASK_THREAD, offsetof(struct task_struct, thread));
- DEFINE(TASK_INFO, offsetof(struct task_struct, thread.info));
- DEFINE(TASK_MM, offsetof(struct task_struct, mm));
-#ifdef CONFIG_MMU
- DEFINE(TASK_TINFO, offsetof(struct task_struct, thread.info));
-#endif
-
- /* offsets into the thread struct */
- DEFINE(THREAD_KSP, offsetof(struct thread_struct, ksp));
- DEFINE(THREAD_USP, offsetof(struct thread_struct, usp));
- DEFINE(THREAD_SR, offsetof(struct thread_struct, sr));
- DEFINE(THREAD_FS, offsetof(struct thread_struct, fs));
- DEFINE(THREAD_CRP, offsetof(struct thread_struct, crp));
- DEFINE(THREAD_ESP0, offsetof(struct thread_struct, esp0));
- DEFINE(THREAD_FPREG, offsetof(struct thread_struct, fp));
- DEFINE(THREAD_FPCNTL, offsetof(struct thread_struct, fpcntl));
- DEFINE(THREAD_FPSTATE, offsetof(struct thread_struct, fpstate));
-
- /* offsets into the thread_info struct */
- DEFINE(TINFO_PREEMPT, offsetof(struct thread_info, preempt_count));
- DEFINE(TINFO_FLAGS, offsetof(struct thread_info, flags));
-
- /* offsets into the pt_regs */
- DEFINE(PT_OFF_D0, offsetof(struct pt_regs, d0));
- DEFINE(PT_OFF_ORIG_D0, offsetof(struct pt_regs, orig_d0));
- DEFINE(PT_OFF_D1, offsetof(struct pt_regs, d1));
- DEFINE(PT_OFF_D2, offsetof(struct pt_regs, d2));
- DEFINE(PT_OFF_D3, offsetof(struct pt_regs, d3));
- DEFINE(PT_OFF_D4, offsetof(struct pt_regs, d4));
- DEFINE(PT_OFF_D5, offsetof(struct pt_regs, d5));
- DEFINE(PT_OFF_A0, offsetof(struct pt_regs, a0));
- DEFINE(PT_OFF_A1, offsetof(struct pt_regs, a1));
- DEFINE(PT_OFF_A2, offsetof(struct pt_regs, a2));
- DEFINE(PT_OFF_PC, offsetof(struct pt_regs, pc));
- DEFINE(PT_OFF_SR, offsetof(struct pt_regs, sr));
- /* bitfields are a bit difficult */
- DEFINE(PT_OFF_FORMATVEC, offsetof(struct pt_regs, pc) + 4);
-
- /* offsets into the irq_cpustat_t struct */
- DEFINE(CPUSTAT_SOFTIRQ_PENDING, offsetof(irq_cpustat_t, __softirq_pending));
-
- /* offsets into the bi_record struct */
- DEFINE(BIR_TAG, offsetof(struct bi_record, tag));
- DEFINE(BIR_SIZE, offsetof(struct bi_record, size));
- DEFINE(BIR_DATA, offsetof(struct bi_record, data));
-
- /* offsets into font_desc (drivers/video/console/font.h) */
- DEFINE(FONT_DESC_IDX, offsetof(struct font_desc, idx));
- DEFINE(FONT_DESC_NAME, offsetof(struct font_desc, name));
- DEFINE(FONT_DESC_WIDTH, offsetof(struct font_desc, width));
- DEFINE(FONT_DESC_HEIGHT, offsetof(struct font_desc, height));
- DEFINE(FONT_DESC_DATA, offsetof(struct font_desc, data));
- DEFINE(FONT_DESC_PREF, offsetof(struct font_desc, pref));
-
- /* signal defines */
- DEFINE(LSIGSEGV, SIGSEGV);
- DEFINE(LSEGV_MAPERR, SEGV_MAPERR);
- DEFINE(LSIGTRAP, SIGTRAP);
- DEFINE(LTRAP_TRACE, TRAP_TRACE);
-
- /* offsets into the custom struct */
- DEFINE(CUSTOMBASE, &amiga_custom);
- DEFINE(C_INTENAR, offsetof(struct CUSTOM, intenar));
- DEFINE(C_INTREQR, offsetof(struct CUSTOM, intreqr));
- DEFINE(C_INTENA, offsetof(struct CUSTOM, intena));
- DEFINE(C_INTREQ, offsetof(struct CUSTOM, intreq));
- DEFINE(C_SERDATR, offsetof(struct CUSTOM, serdatr));
- DEFINE(C_SERDAT, offsetof(struct CUSTOM, serdat));
- DEFINE(C_SERPER, offsetof(struct CUSTOM, serper));
- DEFINE(CIAABASE, &ciaa);
- DEFINE(CIABBASE, &ciab);
- DEFINE(C_PRA, offsetof(struct CIA, pra));
- DEFINE(ZTWOBASE, zTwoBase);
-
- return 0;
-}
diff --git a/arch/m68k/kernel/asm-offsets_no.c b/arch/m68k/kernel/asm-offsets_no.c
deleted file mode 100644
index ffe02f4..0000000
--- a/arch/m68k/kernel/asm-offsets_no.c
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * This program is used to generate definitions needed by
- * assembly language modules.
- *
- * We use the technique used in the OSF Mach kernel code:
- * generate asm statements containing #defines,
- * compile this file to assembler, and then extract the
- * #defines from the assembly-language output.
- */
-
-#include <linux/stddef.h>
-#include <linux/sched.h>
-#include <linux/kernel_stat.h>
-#include <linux/ptrace.h>
-#include <linux/hardirq.h>
-#include <linux/kbuild.h>
-#include <asm/bootinfo.h>
-#include <asm/irq.h>
-#include <asm/thread_info.h>
-
-int main(void)
-{
- /* offsets into the task struct */
- DEFINE(TASK_THREAD, offsetof(struct task_struct, thread));
- DEFINE(TASK_MM, offsetof(struct task_struct, mm));
-
- /* offsets into the irq_cpustat_t struct */
- DEFINE(CPUSTAT_SOFTIRQ_PENDING, offsetof(irq_cpustat_t, __softirq_pending));
-
- /* offsets into the thread struct */
- DEFINE(THREAD_KSP, offsetof(struct thread_struct, ksp));
- DEFINE(THREAD_USP, offsetof(struct thread_struct, usp));
- DEFINE(THREAD_SR, offsetof(struct thread_struct, sr));
- DEFINE(THREAD_FS, offsetof(struct thread_struct, fs));
- DEFINE(THREAD_CRP, offsetof(struct thread_struct, crp));
- DEFINE(THREAD_ESP0, offsetof(struct thread_struct, esp0));
- DEFINE(THREAD_FPREG, offsetof(struct thread_struct, fp));
- DEFINE(THREAD_FPCNTL, offsetof(struct thread_struct, fpcntl));
- DEFINE(THREAD_FPSTATE, offsetof(struct thread_struct, fpstate));
-
- /* offsets into the pt_regs */
- DEFINE(PT_OFF_D0, offsetof(struct pt_regs, d0));
- DEFINE(PT_OFF_ORIG_D0, offsetof(struct pt_regs, orig_d0));
- DEFINE(PT_OFF_D1, offsetof(struct pt_regs, d1));
- DEFINE(PT_OFF_D2, offsetof(struct pt_regs, d2));
- DEFINE(PT_OFF_D3, offsetof(struct pt_regs, d3));
- DEFINE(PT_OFF_D4, offsetof(struct pt_regs, d4));
- DEFINE(PT_OFF_D5, offsetof(struct pt_regs, d5));
- DEFINE(PT_OFF_A0, offsetof(struct pt_regs, a0));
- DEFINE(PT_OFF_A1, offsetof(struct pt_regs, a1));
- DEFINE(PT_OFF_A2, offsetof(struct pt_regs, a2));
- DEFINE(PT_OFF_PC, offsetof(struct pt_regs, pc));
- DEFINE(PT_OFF_SR, offsetof(struct pt_regs, sr));
-
-#ifdef CONFIG_COLDFIRE
- /* bitfields are a bit difficult */
- DEFINE(PT_OFF_FORMATVEC, offsetof(struct pt_regs, sr) - 2);
-#else
- /* bitfields are a bit difficult */
- DEFINE(PT_OFF_FORMATVEC, offsetof(struct pt_regs, pc) + 4);
-#endif
-
- /* signal defines */
- DEFINE(SIGSEGV, SIGSEGV);
- DEFINE(SEGV_MAPERR, SEGV_MAPERR);
- DEFINE(SIGTRAP, SIGTRAP);
- DEFINE(TRAP_TRACE, TRAP_TRACE);
-
- DEFINE(PT_PTRACED, PT_PTRACED);
-
- /* Offsets in thread_info structure */
- DEFINE(TI_FLAGS, offsetof(struct thread_info, flags));
- DEFINE(TI_PREEMPTCOUNT, offsetof(struct thread_info, preempt_count));
-
- return 0;
-}
diff --git a/arch/m68k/kernel/entry_no.S b/arch/m68k/kernel/entry_no.S
index 2783f25..5f0f6b5 100644
--- a/arch/m68k/kernel/entry_no.S
+++ b/arch/m68k/kernel/entry_no.S
@@ -24,7 +24,6 @@
* linux 2.4 support David McCullough <davidm@snapgear.com>
*/
-#include <linux/sys.h>
#include <linux/linkage.h>
#include <asm/errno.h>
#include <asm/setup.h>
diff --git a/arch/m68k/kernel/irq.c b/arch/m68k/kernel/irq.c
index 15dbc3e..544b871 100644
--- a/arch/m68k/kernel/irq.c
+++ b/arch/m68k/kernel/irq.c
@@ -28,31 +28,3 @@
set_irq_regs(oldregs);
}
-
-int show_interrupts(struct seq_file *p, void *v)
-{
- struct irqaction *ap;
- int irq = *((loff_t *) v);
-
- if (irq == 0)
- seq_puts(p, " CPU0\n");
-
- if (irq < NR_IRQS) {
- struct irq_desc *desc = irq_to_desc(irq);
-
- ap = desc->action;
- if (ap) {
- seq_printf(p, "%3d: ", irq);
- seq_printf(p, "%10u ", kstat_irqs(irq));
- seq_printf(p, "%14s ", irq_desc_get_chip(desc)->name);
-
- seq_printf(p, "%s", ap->name);
- for (ap = ap->next; ap; ap = ap->next)
- seq_printf(p, ", %s", ap->name);
- seq_putc(p, '\n');
- }
- }
-
- return 0;
-}
-
diff --git a/arch/m68k/kernel/m68k_ksyms.c b/arch/m68k/kernel/m68k_ksyms.c
index 4752c28..33f8276 100644
--- a/arch/m68k/kernel/m68k_ksyms.c
+++ b/arch/m68k/kernel/m68k_ksyms.c
@@ -1,5 +1,33 @@
-#ifdef CONFIG_MMU
-#include "m68k_ksyms_mm.c"
-#else
-#include "m68k_ksyms_no.c"
+#include <linux/module.h>
+
+asmlinkage long long __ashldi3 (long long, int);
+asmlinkage long long __ashrdi3 (long long, int);
+asmlinkage long long __lshrdi3 (long long, int);
+asmlinkage long long __muldi3 (long long, long long);
+
+/* The following are special because they're not called
+ explicitly (the C compiler generates them). Fortunately,
+ their interface isn't gonna change any time soon now, so
+ it's OK to leave it out of version control. */
+EXPORT_SYMBOL(__ashldi3);
+EXPORT_SYMBOL(__ashrdi3);
+EXPORT_SYMBOL(__lshrdi3);
+EXPORT_SYMBOL(__muldi3);
+
+#if !defined(__mc68020__) && !defined(__mc68030__) && \
+ !defined(__mc68040__) && !defined(__mc68060__) && !defined(__mcpu32__)
+/*
+ * Simpler 68k and ColdFire parts also need a few other gcc functions.
+ */
+extern long long __divsi3(long long, long long);
+extern long long __modsi3(long long, long long);
+extern long long __mulsi3(long long, long long);
+extern long long __udivsi3(long long, long long);
+extern long long __umodsi3(long long, long long);
+
+EXPORT_SYMBOL(__divsi3);
+EXPORT_SYMBOL(__modsi3);
+EXPORT_SYMBOL(__mulsi3);
+EXPORT_SYMBOL(__udivsi3);
+EXPORT_SYMBOL(__umodsi3);
#endif
diff --git a/arch/m68k/kernel/m68k_ksyms_mm.c b/arch/m68k/kernel/m68k_ksyms_mm.c
deleted file mode 100644
index d900e77..0000000
--- a/arch/m68k/kernel/m68k_ksyms_mm.c
+++ /dev/null
@@ -1,16 +0,0 @@
-#include <linux/module.h>
-
-asmlinkage long long __ashldi3 (long long, int);
-asmlinkage long long __ashrdi3 (long long, int);
-asmlinkage long long __lshrdi3 (long long, int);
-asmlinkage long long __muldi3 (long long, long long);
-
-/* The following are special because they're not called
- explicitly (the C compiler generates them). Fortunately,
- their interface isn't gonna change any time soon now, so
- it's OK to leave it out of version control. */
-EXPORT_SYMBOL(__ashldi3);
-EXPORT_SYMBOL(__ashrdi3);
-EXPORT_SYMBOL(__lshrdi3);
-EXPORT_SYMBOL(__muldi3);
-
diff --git a/arch/m68k/kernel/m68k_ksyms_no.c b/arch/m68k/kernel/m68k_ksyms_no.c
deleted file mode 100644
index 39fe0a7..0000000
--- a/arch/m68k/kernel/m68k_ksyms_no.c
+++ /dev/null
@@ -1,78 +0,0 @@
-#include <linux/module.h>
-#include <linux/linkage.h>
-#include <linux/sched.h>
-#include <linux/string.h>
-#include <linux/mm.h>
-#include <linux/user.h>
-#include <linux/elfcore.h>
-#include <linux/in6.h>
-#include <linux/interrupt.h>
-
-#include <asm/setup.h>
-#include <asm/machdep.h>
-#include <asm/pgalloc.h>
-#include <asm/irq.h>
-#include <asm/io.h>
-#include <asm/checksum.h>
-#include <asm/current.h>
-
-extern int dump_fpu(struct pt_regs *, elf_fpregset_t *);
-
-/* platform dependent support */
-
-EXPORT_SYMBOL(__ioremap);
-EXPORT_SYMBOL(iounmap);
-EXPORT_SYMBOL(dump_fpu);
-
-EXPORT_SYMBOL(ip_fast_csum);
-
-EXPORT_SYMBOL(kernel_thread);
-
-/* Networking helper routines. */
-EXPORT_SYMBOL(csum_partial_copy_nocheck);
-
-/* The following are special because they're not called
- explicitly (the C compiler generates them). Fortunately,
- their interface isn't gonna change any time soon now, so
- it's OK to leave it out of version control. */
-EXPORT_SYMBOL(memcpy);
-EXPORT_SYMBOL(memset);
-
-/*
- * libgcc functions - functions that are used internally by the
- * compiler... (prototypes are not correct though, but that
- * doesn't really matter since they're not versioned).
- */
-extern void __ashldi3(void);
-extern void __ashrdi3(void);
-extern void __divsi3(void);
-extern void __lshrdi3(void);
-extern void __modsi3(void);
-extern void __muldi3(void);
-extern void __mulsi3(void);
-extern void __udivsi3(void);
-extern void __umodsi3(void);
-
- /* gcc lib functions */
-EXPORT_SYMBOL(__ashldi3);
-EXPORT_SYMBOL(__ashrdi3);
-EXPORT_SYMBOL(__divsi3);
-EXPORT_SYMBOL(__lshrdi3);
-EXPORT_SYMBOL(__modsi3);
-EXPORT_SYMBOL(__muldi3);
-EXPORT_SYMBOL(__mulsi3);
-EXPORT_SYMBOL(__udivsi3);
-EXPORT_SYMBOL(__umodsi3);
-
-#ifdef CONFIG_COLDFIRE
-extern unsigned int *dma_device_address;
-extern unsigned long dma_base_addr, _ramend;
-EXPORT_SYMBOL(dma_base_addr);
-EXPORT_SYMBOL(dma_device_address);
-EXPORT_SYMBOL(_ramend);
-
-extern asmlinkage void trap(void);
-extern void *_ramvec;
-EXPORT_SYMBOL(trap);
-EXPORT_SYMBOL(_ramvec);
-#endif /* CONFIG_COLDFIRE */
diff --git a/arch/m68k/kernel/process_no.c b/arch/m68k/kernel/process_no.c
index e2a63af..9b86ad1 100644
--- a/arch/m68k/kernel/process_no.c
+++ b/arch/m68k/kernel/process_no.c
@@ -151,6 +151,7 @@
set_fs(fs);
return retval;
}
+EXPORT_SYMBOL(kernel_thread);
void flush_thread(void)
{
@@ -283,6 +284,7 @@
#endif
return 1;
}
+EXPORT_SYMBOL(dump_fpu);
/*
* Generic dumping code. Used for panic and debug.
diff --git a/arch/m68k/kernel/sys_m68k.c b/arch/m68k/kernel/sys_m68k.c
index 63013df..8623f8d 100644
--- a/arch/m68k/kernel/sys_m68k.c
+++ b/arch/m68k/kernel/sys_m68k.c
@@ -1,5 +1,580 @@
+/*
+ * linux/arch/m68k/kernel/sys_m68k.c
+ *
+ * This file contains various random system calls that
+ * have a non-standard calling sequence on the Linux/m68k
+ * platform.
+ */
+
+#include <linux/capability.h>
+#include <linux/errno.h>
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/fs.h>
+#include <linux/smp.h>
+#include <linux/sem.h>
+#include <linux/msg.h>
+#include <linux/shm.h>
+#include <linux/stat.h>
+#include <linux/syscalls.h>
+#include <linux/mman.h>
+#include <linux/file.h>
+#include <linux/ipc.h>
+
+#include <asm/setup.h>
+#include <asm/uaccess.h>
+#include <asm/cachectl.h>
+#include <asm/traps.h>
+#include <asm/page.h>
+#include <asm/unistd.h>
+#include <asm/cacheflush.h>
+
#ifdef CONFIG_MMU
-#include "sys_m68k_mm.c"
+
+#include <asm/tlb.h>
+
+asmlinkage int do_page_fault(struct pt_regs *regs, unsigned long address,
+ unsigned long error_code);
+
+asmlinkage long sys_mmap2(unsigned long addr, unsigned long len,
+ unsigned long prot, unsigned long flags,
+ unsigned long fd, unsigned long pgoff)
+{
+ /*
+ * This is wrong for sun3 - there PAGE_SIZE is 8Kb,
+ * so we need to shift the argument down by 1; m68k mmap64(3)
+ * (in libc) expects the last argument of mmap2 in 4Kb units.
+ */
+ return sys_mmap_pgoff(addr, len, prot, flags, fd, pgoff);
+}
+
+/* Convert virtual (user) address VADDR to physical address PADDR */
+#define virt_to_phys_040(vaddr) \
+({ \
+ unsigned long _mmusr, _paddr; \
+ \
+ __asm__ __volatile__ (".chip 68040\n\t" \
+ "ptestr (%1)\n\t" \
+ "movec %%mmusr,%0\n\t" \
+ ".chip 68k" \
+ : "=r" (_mmusr) \
+ : "a" (vaddr)); \
+ _paddr = (_mmusr & MMU_R_040) ? (_mmusr & PAGE_MASK) : 0; \
+ _paddr; \
+})
+
+static inline int
+cache_flush_040 (unsigned long addr, int scope, int cache, unsigned long len)
+{
+ unsigned long paddr, i;
+
+ switch (scope)
+ {
+ case FLUSH_SCOPE_ALL:
+ switch (cache)
+ {
+ case FLUSH_CACHE_DATA:
+ /* This nop is needed for some broken versions of the 68040. */
+ __asm__ __volatile__ ("nop\n\t"
+ ".chip 68040\n\t"
+ "cpusha %dc\n\t"
+ ".chip 68k");
+ break;
+ case FLUSH_CACHE_INSN:
+ __asm__ __volatile__ ("nop\n\t"
+ ".chip 68040\n\t"
+ "cpusha %ic\n\t"
+ ".chip 68k");
+ break;
+ default:
+ case FLUSH_CACHE_BOTH:
+ __asm__ __volatile__ ("nop\n\t"
+ ".chip 68040\n\t"
+ "cpusha %bc\n\t"
+ ".chip 68k");
+ break;
+ }
+ break;
+
+ case FLUSH_SCOPE_LINE:
+ /* Find the physical address of the first mapped page in the
+ address range. */
+ if ((paddr = virt_to_phys_040(addr))) {
+ paddr += addr & ~(PAGE_MASK | 15);
+ len = (len + (addr & 15) + 15) >> 4;
+ } else {
+ unsigned long tmp = PAGE_SIZE - (addr & ~PAGE_MASK);
+
+ if (len <= tmp)
+ return 0;
+ addr += tmp;
+ len -= tmp;
+ tmp = PAGE_SIZE;
+ for (;;)
+ {
+ if ((paddr = virt_to_phys_040(addr)))
+ break;
+ if (len <= tmp)
+ return 0;
+ addr += tmp;
+ len -= tmp;
+ }
+ len = (len + 15) >> 4;
+ }
+ i = (PAGE_SIZE - (paddr & ~PAGE_MASK)) >> 4;
+ while (len--)
+ {
+ switch (cache)
+ {
+ case FLUSH_CACHE_DATA:
+ __asm__ __volatile__ ("nop\n\t"
+ ".chip 68040\n\t"
+ "cpushl %%dc,(%0)\n\t"
+ ".chip 68k"
+ : : "a" (paddr));
+ break;
+ case FLUSH_CACHE_INSN:
+ __asm__ __volatile__ ("nop\n\t"
+ ".chip 68040\n\t"
+ "cpushl %%ic,(%0)\n\t"
+ ".chip 68k"
+ : : "a" (paddr));
+ break;
+ default:
+ case FLUSH_CACHE_BOTH:
+ __asm__ __volatile__ ("nop\n\t"
+ ".chip 68040\n\t"
+ "cpushl %%bc,(%0)\n\t"
+ ".chip 68k"
+ : : "a" (paddr));
+ break;
+ }
+ if (!--i && len)
+ {
+ /*
+ * No need to page align here since it is done by
+ * virt_to_phys_040().
+ */
+ addr += PAGE_SIZE;
+ i = PAGE_SIZE / 16;
+ /* Recompute physical address when crossing a page
+ boundary. */
+ for (;;)
+ {
+ if ((paddr = virt_to_phys_040(addr)))
+ break;
+ if (len <= i)
+ return 0;
+ len -= i;
+ addr += PAGE_SIZE;
+ }
+ }
+ else
+ paddr += 16;
+ }
+ break;
+
+ default:
+ case FLUSH_SCOPE_PAGE:
+ len += (addr & ~PAGE_MASK) + (PAGE_SIZE - 1);
+ for (len >>= PAGE_SHIFT; len--; addr += PAGE_SIZE)
+ {
+ if (!(paddr = virt_to_phys_040(addr)))
+ continue;
+ switch (cache)
+ {
+ case FLUSH_CACHE_DATA:
+ __asm__ __volatile__ ("nop\n\t"
+ ".chip 68040\n\t"
+ "cpushp %%dc,(%0)\n\t"
+ ".chip 68k"
+ : : "a" (paddr));
+ break;
+ case FLUSH_CACHE_INSN:
+ __asm__ __volatile__ ("nop\n\t"
+ ".chip 68040\n\t"
+ "cpushp %%ic,(%0)\n\t"
+ ".chip 68k"
+ : : "a" (paddr));
+ break;
+ default:
+ case FLUSH_CACHE_BOTH:
+ __asm__ __volatile__ ("nop\n\t"
+ ".chip 68040\n\t"
+ "cpushp %%bc,(%0)\n\t"
+ ".chip 68k"
+ : : "a" (paddr));
+ break;
+ }
+ }
+ break;
+ }
+ return 0;
+}
+
+#define virt_to_phys_060(vaddr) \
+({ \
+ unsigned long paddr; \
+ __asm__ __volatile__ (".chip 68060\n\t" \
+ "plpar (%0)\n\t" \
+ ".chip 68k" \
+ : "=a" (paddr) \
+ : "0" (vaddr)); \
+ (paddr); /* XXX */ \
+})
+
+static inline int
+cache_flush_060 (unsigned long addr, int scope, int cache, unsigned long len)
+{
+ unsigned long paddr, i;
+
+ /*
+ * 68060 manual says:
+ * cpush %dc : flush DC, remains valid (with our %cacr setup)
+ * cpush %ic : invalidate IC
+ * cpush %bc : flush DC + invalidate IC
+ */
+ switch (scope)
+ {
+ case FLUSH_SCOPE_ALL:
+ switch (cache)
+ {
+ case FLUSH_CACHE_DATA:
+ __asm__ __volatile__ (".chip 68060\n\t"
+ "cpusha %dc\n\t"
+ ".chip 68k");
+ break;
+ case FLUSH_CACHE_INSN:
+ __asm__ __volatile__ (".chip 68060\n\t"
+ "cpusha %ic\n\t"
+ ".chip 68k");
+ break;
+ default:
+ case FLUSH_CACHE_BOTH:
+ __asm__ __volatile__ (".chip 68060\n\t"
+ "cpusha %bc\n\t"
+ ".chip 68k");
+ break;
+ }
+ break;
+
+ case FLUSH_SCOPE_LINE:
+ /* Find the physical address of the first mapped page in the
+ address range. */
+ len += addr & 15;
+ addr &= -16;
+ if (!(paddr = virt_to_phys_060(addr))) {
+ unsigned long tmp = PAGE_SIZE - (addr & ~PAGE_MASK);
+
+ if (len <= tmp)
+ return 0;
+ addr += tmp;
+ len -= tmp;
+ tmp = PAGE_SIZE;
+ for (;;)
+ {
+ if ((paddr = virt_to_phys_060(addr)))
+ break;
+ if (len <= tmp)
+ return 0;
+ addr += tmp;
+ len -= tmp;
+ }
+ }
+ len = (len + 15) >> 4;
+ i = (PAGE_SIZE - (paddr & ~PAGE_MASK)) >> 4;
+ while (len--)
+ {
+ switch (cache)
+ {
+ case FLUSH_CACHE_DATA:
+ __asm__ __volatile__ (".chip 68060\n\t"
+ "cpushl %%dc,(%0)\n\t"
+ ".chip 68k"
+ : : "a" (paddr));
+ break;
+ case FLUSH_CACHE_INSN:
+ __asm__ __volatile__ (".chip 68060\n\t"
+ "cpushl %%ic,(%0)\n\t"
+ ".chip 68k"
+ : : "a" (paddr));
+ break;
+ default:
+ case FLUSH_CACHE_BOTH:
+ __asm__ __volatile__ (".chip 68060\n\t"
+ "cpushl %%bc,(%0)\n\t"
+ ".chip 68k"
+ : : "a" (paddr));
+ break;
+ }
+ if (!--i && len)
+ {
+
+ /*
+ * We just want to jump to the first cache line
+ * in the next page.
+ */
+ addr += PAGE_SIZE;
+ addr &= PAGE_MASK;
+
+ i = PAGE_SIZE / 16;
+ /* Recompute physical address when crossing a page
+ boundary. */
+ for (;;)
+ {
+ if ((paddr = virt_to_phys_060(addr)))
+ break;
+ if (len <= i)
+ return 0;
+ len -= i;
+ addr += PAGE_SIZE;
+ }
+ }
+ else
+ paddr += 16;
+ }
+ break;
+
+ default:
+ case FLUSH_SCOPE_PAGE:
+ len += (addr & ~PAGE_MASK) + (PAGE_SIZE - 1);
+ addr &= PAGE_MASK; /* Workaround for bug in some
+ revisions of the 68060 */
+ for (len >>= PAGE_SHIFT; len--; addr += PAGE_SIZE)
+ {
+ if (!(paddr = virt_to_phys_060(addr)))
+ continue;
+ switch (cache)
+ {
+ case FLUSH_CACHE_DATA:
+ __asm__ __volatile__ (".chip 68060\n\t"
+ "cpushp %%dc,(%0)\n\t"
+ ".chip 68k"
+ : : "a" (paddr));
+ break;
+ case FLUSH_CACHE_INSN:
+ __asm__ __volatile__ (".chip 68060\n\t"
+ "cpushp %%ic,(%0)\n\t"
+ ".chip 68k"
+ : : "a" (paddr));
+ break;
+ default:
+ case FLUSH_CACHE_BOTH:
+ __asm__ __volatile__ (".chip 68060\n\t"
+ "cpushp %%bc,(%0)\n\t"
+ ".chip 68k"
+ : : "a" (paddr));
+ break;
+ }
+ }
+ break;
+ }
+ return 0;
+}
+
+/* sys_cacheflush -- flush (part of) the processor cache. */
+asmlinkage int
+sys_cacheflush (unsigned long addr, int scope, int cache, unsigned long len)
+{
+ struct vm_area_struct *vma;
+ int ret = -EINVAL;
+
+ if (scope < FLUSH_SCOPE_LINE || scope > FLUSH_SCOPE_ALL ||
+ cache & ~FLUSH_CACHE_BOTH)
+ goto out;
+
+ if (scope == FLUSH_SCOPE_ALL) {
+ /* Only the superuser may explicitly flush the whole cache. */
+ ret = -EPERM;
+ if (!capable(CAP_SYS_ADMIN))
+ goto out;
+ } else {
+ /*
+ * Verify that the specified address region actually belongs
+ * to this process.
+ */
+ vma = find_vma (current->mm, addr);
+ ret = -EINVAL;
+ /* Check for overflow. */
+ if (addr + len < addr)
+ goto out;
+ if (vma == NULL || addr < vma->vm_start || addr + len > vma->vm_end)
+ goto out;
+ }
+
+ if (CPU_IS_020_OR_030) {
+ if (scope == FLUSH_SCOPE_LINE && len < 256) {
+ unsigned long cacr;
+ __asm__ ("movec %%cacr, %0" : "=r" (cacr));
+ if (cache & FLUSH_CACHE_INSN)
+ cacr |= 4;
+ if (cache & FLUSH_CACHE_DATA)
+ cacr |= 0x400;
+ len >>= 2;
+ while (len--) {
+ __asm__ __volatile__ ("movec %1, %%caar\n\t"
+ "movec %0, %%cacr"
+ : /* no outputs */
+ : "r" (cacr), "r" (addr));
+ addr += 4;
+ }
+ } else {
+ /* Flush the whole cache, even if page granularity requested. */
+ unsigned long cacr;
+ __asm__ ("movec %%cacr, %0" : "=r" (cacr));
+ if (cache & FLUSH_CACHE_INSN)
+ cacr |= 8;
+ if (cache & FLUSH_CACHE_DATA)
+ cacr |= 0x800;
+ __asm__ __volatile__ ("movec %0, %%cacr" : : "r" (cacr));
+ }
+ ret = 0;
+ goto out;
+ } else {
+ /*
+ * 040 or 060: don't blindly trust 'scope', someone could
+ * try to flush a few megs of memory.
+ */
+
+ if (len>=3*PAGE_SIZE && scope<FLUSH_SCOPE_PAGE)
+ scope=FLUSH_SCOPE_PAGE;
+ if (len>=10*PAGE_SIZE && scope<FLUSH_SCOPE_ALL)
+ scope=FLUSH_SCOPE_ALL;
+ if (CPU_IS_040) {
+ ret = cache_flush_040 (addr, scope, cache, len);
+ } else if (CPU_IS_060) {
+ ret = cache_flush_060 (addr, scope, cache, len);
+ }
+ }
+out:
+ return ret;
+}
+
+/* This syscall gets its arguments in A0 (mem), D2 (oldval) and
+ D1 (newval). */
+asmlinkage int
+sys_atomic_cmpxchg_32(unsigned long newval, int oldval, int d3, int d4, int d5,
+ unsigned long __user * mem)
+{
+ /* This was borrowed from ARM's implementation. */
+ for (;;) {
+ struct mm_struct *mm = current->mm;
+ pgd_t *pgd;
+ pmd_t *pmd;
+ pte_t *pte;
+ spinlock_t *ptl;
+ unsigned long mem_value;
+
+ down_read(&mm->mmap_sem);
+ pgd = pgd_offset(mm, (unsigned long)mem);
+ if (!pgd_present(*pgd))
+ goto bad_access;
+ pmd = pmd_offset(pgd, (unsigned long)mem);
+ if (!pmd_present(*pmd))
+ goto bad_access;
+ pte = pte_offset_map_lock(mm, pmd, (unsigned long)mem, &ptl);
+ if (!pte_present(*pte) || !pte_dirty(*pte)
+ || !pte_write(*pte)) {
+ pte_unmap_unlock(pte, ptl);
+ goto bad_access;
+ }
+
+ mem_value = *mem;
+ if (mem_value == oldval)
+ *mem = newval;
+
+ pte_unmap_unlock(pte, ptl);
+ up_read(&mm->mmap_sem);
+ return mem_value;
+
+ bad_access:
+ up_read(&mm->mmap_sem);
+ /* This is not necessarily a bad access, we can get here if
+ a memory we're trying to write to should be copied-on-write.
+ Make the kernel do the necessary page stuff, then re-iterate.
+ Simulate a write access fault to do that. */
+ {
+ /* The first argument of the function corresponds to
+ D1, which is the first field of struct pt_regs. */
+ struct pt_regs *fp = (struct pt_regs *)&newval;
+
+ /* '3' is an RMW flag. */
+ if (do_page_fault(fp, (unsigned long)mem, 3))
+ /* If the do_page_fault() failed, we don't
+ have anything meaningful to return.
+ There should be a SIGSEGV pending for
+ the process. */
+ return 0xdeadbeef;
+ }
+ }
+}
+
#else
-#include "sys_m68k_no.c"
-#endif
+
+/* sys_cacheflush -- flush (part of) the processor cache. */
+asmlinkage int
+sys_cacheflush (unsigned long addr, int scope, int cache, unsigned long len)
+{
+ flush_cache_all();
+ return 0;
+}
+
+/* This syscall gets its arguments in A0 (mem), D2 (oldval) and
+ D1 (newval). */
+asmlinkage int
+sys_atomic_cmpxchg_32(unsigned long newval, int oldval, int d3, int d4, int d5,
+ unsigned long __user * mem)
+{
+ struct mm_struct *mm = current->mm;
+ unsigned long mem_value;
+
+ down_read(&mm->mmap_sem);
+
+ mem_value = *mem;
+ if (mem_value == oldval)
+ *mem = newval;
+
+ up_read(&mm->mmap_sem);
+ return mem_value;
+}
+
+#endif /* CONFIG_MMU */
+
+asmlinkage int sys_getpagesize(void)
+{
+ return PAGE_SIZE;
+}
+
+/*
+ * Do a system call from kernel instead of calling sys_execve so we
+ * end up with proper pt_regs.
+ */
+int kernel_execve(const char *filename,
+ const char *const argv[],
+ const char *const envp[])
+{
+ register long __res asm ("%d0") = __NR_execve;
+ register long __a asm ("%d1") = (long)(filename);
+ register long __b asm ("%d2") = (long)(argv);
+ register long __c asm ("%d3") = (long)(envp);
+ asm volatile ("trap #0" : "+d" (__res)
+ : "d" (__a), "d" (__b), "d" (__c));
+ return __res;
+}
+
+asmlinkage unsigned long sys_get_thread_area(void)
+{
+ return current_thread_info()->tp_value;
+}
+
+asmlinkage int sys_set_thread_area(unsigned long tp)
+{
+ current_thread_info()->tp_value = tp;
+ return 0;
+}
+
+asmlinkage int sys_atomic_barrier(void)
+{
+ /* no code needed for uniprocs */
+ return 0;
+}
diff --git a/arch/m68k/kernel/sys_m68k_mm.c b/arch/m68k/kernel/sys_m68k_mm.c
deleted file mode 100644
index 3db2e7f..0000000
--- a/arch/m68k/kernel/sys_m68k_mm.c
+++ /dev/null
@@ -1,546 +0,0 @@
-/*
- * linux/arch/m68k/kernel/sys_m68k.c
- *
- * This file contains various random system calls that
- * have a non-standard calling sequence on the Linux/m68k
- * platform.
- */
-
-#include <linux/capability.h>
-#include <linux/errno.h>
-#include <linux/sched.h>
-#include <linux/mm.h>
-#include <linux/fs.h>
-#include <linux/smp.h>
-#include <linux/sem.h>
-#include <linux/msg.h>
-#include <linux/shm.h>
-#include <linux/stat.h>
-#include <linux/syscalls.h>
-#include <linux/mman.h>
-#include <linux/file.h>
-#include <linux/ipc.h>
-
-#include <asm/setup.h>
-#include <asm/uaccess.h>
-#include <asm/cachectl.h>
-#include <asm/traps.h>
-#include <asm/page.h>
-#include <asm/unistd.h>
-#include <linux/elf.h>
-#include <asm/tlb.h>
-
-asmlinkage int do_page_fault(struct pt_regs *regs, unsigned long address,
- unsigned long error_code);
-
-asmlinkage long sys_mmap2(unsigned long addr, unsigned long len,
- unsigned long prot, unsigned long flags,
- unsigned long fd, unsigned long pgoff)
-{
- /*
- * This is wrong for sun3 - there PAGE_SIZE is 8Kb,
- * so we need to shift the argument down by 1; m68k mmap64(3)
- * (in libc) expects the last argument of mmap2 in 4Kb units.
- */
- return sys_mmap_pgoff(addr, len, prot, flags, fd, pgoff);
-}
-
-/* Convert virtual (user) address VADDR to physical address PADDR */
-#define virt_to_phys_040(vaddr) \
-({ \
- unsigned long _mmusr, _paddr; \
- \
- __asm__ __volatile__ (".chip 68040\n\t" \
- "ptestr (%1)\n\t" \
- "movec %%mmusr,%0\n\t" \
- ".chip 68k" \
- : "=r" (_mmusr) \
- : "a" (vaddr)); \
- _paddr = (_mmusr & MMU_R_040) ? (_mmusr & PAGE_MASK) : 0; \
- _paddr; \
-})
-
-static inline int
-cache_flush_040 (unsigned long addr, int scope, int cache, unsigned long len)
-{
- unsigned long paddr, i;
-
- switch (scope)
- {
- case FLUSH_SCOPE_ALL:
- switch (cache)
- {
- case FLUSH_CACHE_DATA:
- /* This nop is needed for some broken versions of the 68040. */
- __asm__ __volatile__ ("nop\n\t"
- ".chip 68040\n\t"
- "cpusha %dc\n\t"
- ".chip 68k");
- break;
- case FLUSH_CACHE_INSN:
- __asm__ __volatile__ ("nop\n\t"
- ".chip 68040\n\t"
- "cpusha %ic\n\t"
- ".chip 68k");
- break;
- default:
- case FLUSH_CACHE_BOTH:
- __asm__ __volatile__ ("nop\n\t"
- ".chip 68040\n\t"
- "cpusha %bc\n\t"
- ".chip 68k");
- break;
- }
- break;
-
- case FLUSH_SCOPE_LINE:
- /* Find the physical address of the first mapped page in the
- address range. */
- if ((paddr = virt_to_phys_040(addr))) {
- paddr += addr & ~(PAGE_MASK | 15);
- len = (len + (addr & 15) + 15) >> 4;
- } else {
- unsigned long tmp = PAGE_SIZE - (addr & ~PAGE_MASK);
-
- if (len <= tmp)
- return 0;
- addr += tmp;
- len -= tmp;
- tmp = PAGE_SIZE;
- for (;;)
- {
- if ((paddr = virt_to_phys_040(addr)))
- break;
- if (len <= tmp)
- return 0;
- addr += tmp;
- len -= tmp;
- }
- len = (len + 15) >> 4;
- }
- i = (PAGE_SIZE - (paddr & ~PAGE_MASK)) >> 4;
- while (len--)
- {
- switch (cache)
- {
- case FLUSH_CACHE_DATA:
- __asm__ __volatile__ ("nop\n\t"
- ".chip 68040\n\t"
- "cpushl %%dc,(%0)\n\t"
- ".chip 68k"
- : : "a" (paddr));
- break;
- case FLUSH_CACHE_INSN:
- __asm__ __volatile__ ("nop\n\t"
- ".chip 68040\n\t"
- "cpushl %%ic,(%0)\n\t"
- ".chip 68k"
- : : "a" (paddr));
- break;
- default:
- case FLUSH_CACHE_BOTH:
- __asm__ __volatile__ ("nop\n\t"
- ".chip 68040\n\t"
- "cpushl %%bc,(%0)\n\t"
- ".chip 68k"
- : : "a" (paddr));
- break;
- }
- if (!--i && len)
- {
- /*
- * No need to page align here since it is done by
- * virt_to_phys_040().
- */
- addr += PAGE_SIZE;
- i = PAGE_SIZE / 16;
- /* Recompute physical address when crossing a page
- boundary. */
- for (;;)
- {
- if ((paddr = virt_to_phys_040(addr)))
- break;
- if (len <= i)
- return 0;
- len -= i;
- addr += PAGE_SIZE;
- }
- }
- else
- paddr += 16;
- }
- break;
-
- default:
- case FLUSH_SCOPE_PAGE:
- len += (addr & ~PAGE_MASK) + (PAGE_SIZE - 1);
- for (len >>= PAGE_SHIFT; len--; addr += PAGE_SIZE)
- {
- if (!(paddr = virt_to_phys_040(addr)))
- continue;
- switch (cache)
- {
- case FLUSH_CACHE_DATA:
- __asm__ __volatile__ ("nop\n\t"
- ".chip 68040\n\t"
- "cpushp %%dc,(%0)\n\t"
- ".chip 68k"
- : : "a" (paddr));
- break;
- case FLUSH_CACHE_INSN:
- __asm__ __volatile__ ("nop\n\t"
- ".chip 68040\n\t"
- "cpushp %%ic,(%0)\n\t"
- ".chip 68k"
- : : "a" (paddr));
- break;
- default:
- case FLUSH_CACHE_BOTH:
- __asm__ __volatile__ ("nop\n\t"
- ".chip 68040\n\t"
- "cpushp %%bc,(%0)\n\t"
- ".chip 68k"
- : : "a" (paddr));
- break;
- }
- }
- break;
- }
- return 0;
-}
-
-#define virt_to_phys_060(vaddr) \
-({ \
- unsigned long paddr; \
- __asm__ __volatile__ (".chip 68060\n\t" \
- "plpar (%0)\n\t" \
- ".chip 68k" \
- : "=a" (paddr) \
- : "0" (vaddr)); \
- (paddr); /* XXX */ \
-})
-
-static inline int
-cache_flush_060 (unsigned long addr, int scope, int cache, unsigned long len)
-{
- unsigned long paddr, i;
-
- /*
- * 68060 manual says:
- * cpush %dc : flush DC, remains valid (with our %cacr setup)
- * cpush %ic : invalidate IC
- * cpush %bc : flush DC + invalidate IC
- */
- switch (scope)
- {
- case FLUSH_SCOPE_ALL:
- switch (cache)
- {
- case FLUSH_CACHE_DATA:
- __asm__ __volatile__ (".chip 68060\n\t"
- "cpusha %dc\n\t"
- ".chip 68k");
- break;
- case FLUSH_CACHE_INSN:
- __asm__ __volatile__ (".chip 68060\n\t"
- "cpusha %ic\n\t"
- ".chip 68k");
- break;
- default:
- case FLUSH_CACHE_BOTH:
- __asm__ __volatile__ (".chip 68060\n\t"
- "cpusha %bc\n\t"
- ".chip 68k");
- break;
- }
- break;
-
- case FLUSH_SCOPE_LINE:
- /* Find the physical address of the first mapped page in the
- address range. */
- len += addr & 15;
- addr &= -16;
- if (!(paddr = virt_to_phys_060(addr))) {
- unsigned long tmp = PAGE_SIZE - (addr & ~PAGE_MASK);
-
- if (len <= tmp)
- return 0;
- addr += tmp;
- len -= tmp;
- tmp = PAGE_SIZE;
- for (;;)
- {
- if ((paddr = virt_to_phys_060(addr)))
- break;
- if (len <= tmp)
- return 0;
- addr += tmp;
- len -= tmp;
- }
- }
- len = (len + 15) >> 4;
- i = (PAGE_SIZE - (paddr & ~PAGE_MASK)) >> 4;
- while (len--)
- {
- switch (cache)
- {
- case FLUSH_CACHE_DATA:
- __asm__ __volatile__ (".chip 68060\n\t"
- "cpushl %%dc,(%0)\n\t"
- ".chip 68k"
- : : "a" (paddr));
- break;
- case FLUSH_CACHE_INSN:
- __asm__ __volatile__ (".chip 68060\n\t"
- "cpushl %%ic,(%0)\n\t"
- ".chip 68k"
- : : "a" (paddr));
- break;
- default:
- case FLUSH_CACHE_BOTH:
- __asm__ __volatile__ (".chip 68060\n\t"
- "cpushl %%bc,(%0)\n\t"
- ".chip 68k"
- : : "a" (paddr));
- break;
- }
- if (!--i && len)
- {
-
- /*
- * We just want to jump to the first cache line
- * in the next page.
- */
- addr += PAGE_SIZE;
- addr &= PAGE_MASK;
-
- i = PAGE_SIZE / 16;
- /* Recompute physical address when crossing a page
- boundary. */
- for (;;)
- {
- if ((paddr = virt_to_phys_060(addr)))
- break;
- if (len <= i)
- return 0;
- len -= i;
- addr += PAGE_SIZE;
- }
- }
- else
- paddr += 16;
- }
- break;
-
- default:
- case FLUSH_SCOPE_PAGE:
- len += (addr & ~PAGE_MASK) + (PAGE_SIZE - 1);
- addr &= PAGE_MASK; /* Workaround for bug in some
- revisions of the 68060 */
- for (len >>= PAGE_SHIFT; len--; addr += PAGE_SIZE)
- {
- if (!(paddr = virt_to_phys_060(addr)))
- continue;
- switch (cache)
- {
- case FLUSH_CACHE_DATA:
- __asm__ __volatile__ (".chip 68060\n\t"
- "cpushp %%dc,(%0)\n\t"
- ".chip 68k"
- : : "a" (paddr));
- break;
- case FLUSH_CACHE_INSN:
- __asm__ __volatile__ (".chip 68060\n\t"
- "cpushp %%ic,(%0)\n\t"
- ".chip 68k"
- : : "a" (paddr));
- break;
- default:
- case FLUSH_CACHE_BOTH:
- __asm__ __volatile__ (".chip 68060\n\t"
- "cpushp %%bc,(%0)\n\t"
- ".chip 68k"
- : : "a" (paddr));
- break;
- }
- }
- break;
- }
- return 0;
-}
-
-/* sys_cacheflush -- flush (part of) the processor cache. */
-asmlinkage int
-sys_cacheflush (unsigned long addr, int scope, int cache, unsigned long len)
-{
- struct vm_area_struct *vma;
- int ret = -EINVAL;
-
- if (scope < FLUSH_SCOPE_LINE || scope > FLUSH_SCOPE_ALL ||
- cache & ~FLUSH_CACHE_BOTH)
- goto out;
-
- if (scope == FLUSH_SCOPE_ALL) {
- /* Only the superuser may explicitly flush the whole cache. */
- ret = -EPERM;
- if (!capable(CAP_SYS_ADMIN))
- goto out;
- } else {
- /*
- * Verify that the specified address region actually belongs
- * to this process.
- */
- vma = find_vma (current->mm, addr);
- ret = -EINVAL;
- /* Check for overflow. */
- if (addr + len < addr)
- goto out;
- if (vma == NULL || addr < vma->vm_start || addr + len > vma->vm_end)
- goto out;
- }
-
- if (CPU_IS_020_OR_030) {
- if (scope == FLUSH_SCOPE_LINE && len < 256) {
- unsigned long cacr;
- __asm__ ("movec %%cacr, %0" : "=r" (cacr));
- if (cache & FLUSH_CACHE_INSN)
- cacr |= 4;
- if (cache & FLUSH_CACHE_DATA)
- cacr |= 0x400;
- len >>= 2;
- while (len--) {
- __asm__ __volatile__ ("movec %1, %%caar\n\t"
- "movec %0, %%cacr"
- : /* no outputs */
- : "r" (cacr), "r" (addr));
- addr += 4;
- }
- } else {
- /* Flush the whole cache, even if page granularity requested. */
- unsigned long cacr;
- __asm__ ("movec %%cacr, %0" : "=r" (cacr));
- if (cache & FLUSH_CACHE_INSN)
- cacr |= 8;
- if (cache & FLUSH_CACHE_DATA)
- cacr |= 0x800;
- __asm__ __volatile__ ("movec %0, %%cacr" : : "r" (cacr));
- }
- ret = 0;
- goto out;
- } else {
- /*
- * 040 or 060: don't blindly trust 'scope', someone could
- * try to flush a few megs of memory.
- */
-
- if (len>=3*PAGE_SIZE && scope<FLUSH_SCOPE_PAGE)
- scope=FLUSH_SCOPE_PAGE;
- if (len>=10*PAGE_SIZE && scope<FLUSH_SCOPE_ALL)
- scope=FLUSH_SCOPE_ALL;
- if (CPU_IS_040) {
- ret = cache_flush_040 (addr, scope, cache, len);
- } else if (CPU_IS_060) {
- ret = cache_flush_060 (addr, scope, cache, len);
- }
- }
-out:
- return ret;
-}
-
-asmlinkage int sys_getpagesize(void)
-{
- return PAGE_SIZE;
-}
-
-/*
- * Do a system call from kernel instead of calling sys_execve so we
- * end up with proper pt_regs.
- */
-int kernel_execve(const char *filename,
- const char *const argv[],
- const char *const envp[])
-{
- register long __res asm ("%d0") = __NR_execve;
- register long __a asm ("%d1") = (long)(filename);
- register long __b asm ("%d2") = (long)(argv);
- register long __c asm ("%d3") = (long)(envp);
- asm volatile ("trap #0" : "+d" (__res)
- : "d" (__a), "d" (__b), "d" (__c));
- return __res;
-}
-
-asmlinkage unsigned long sys_get_thread_area(void)
-{
- return current_thread_info()->tp_value;
-}
-
-asmlinkage int sys_set_thread_area(unsigned long tp)
-{
- current_thread_info()->tp_value = tp;
- return 0;
-}
-
-/* This syscall gets its arguments in A0 (mem), D2 (oldval) and
- D1 (newval). */
-asmlinkage int
-sys_atomic_cmpxchg_32(unsigned long newval, int oldval, int d3, int d4, int d5,
- unsigned long __user * mem)
-{
- /* This was borrowed from ARM's implementation. */
- for (;;) {
- struct mm_struct *mm = current->mm;
- pgd_t *pgd;
- pmd_t *pmd;
- pte_t *pte;
- spinlock_t *ptl;
- unsigned long mem_value;
-
- down_read(&mm->mmap_sem);
- pgd = pgd_offset(mm, (unsigned long)mem);
- if (!pgd_present(*pgd))
- goto bad_access;
- pmd = pmd_offset(pgd, (unsigned long)mem);
- if (!pmd_present(*pmd))
- goto bad_access;
- pte = pte_offset_map_lock(mm, pmd, (unsigned long)mem, &ptl);
- if (!pte_present(*pte) || !pte_dirty(*pte)
- || !pte_write(*pte)) {
- pte_unmap_unlock(pte, ptl);
- goto bad_access;
- }
-
- mem_value = *mem;
- if (mem_value == oldval)
- *mem = newval;
-
- pte_unmap_unlock(pte, ptl);
- up_read(&mm->mmap_sem);
- return mem_value;
-
- bad_access:
- up_read(&mm->mmap_sem);
- /* This is not necessarily a bad access, we can get here if
- a memory we're trying to write to should be copied-on-write.
- Make the kernel do the necessary page stuff, then re-iterate.
- Simulate a write access fault to do that. */
- {
- /* The first argument of the function corresponds to
- D1, which is the first field of struct pt_regs. */
- struct pt_regs *fp = (struct pt_regs *)&newval;
-
- /* '3' is an RMW flag. */
- if (do_page_fault(fp, (unsigned long)mem, 3))
- /* If the do_page_fault() failed, we don't
- have anything meaningful to return.
- There should be a SIGSEGV pending for
- the process. */
- return 0xdeadbeef;
- }
- }
-}
-
-asmlinkage int sys_atomic_barrier(void)
-{
- /* no code needed for uniprocs */
- return 0;
-}
diff --git a/arch/m68k/kernel/sys_m68k_no.c b/arch/m68k/kernel/sys_m68k_no.c
deleted file mode 100644
index 68488ae..0000000
--- a/arch/m68k/kernel/sys_m68k_no.c
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * linux/arch/m68knommu/kernel/sys_m68k.c
- *
- * This file contains various random system calls that
- * have a non-standard calling sequence on the Linux/m68k
- * platform.
- */
-
-#include <linux/errno.h>
-#include <linux/sched.h>
-#include <linux/mm.h>
-#include <linux/smp.h>
-#include <linux/sem.h>
-#include <linux/msg.h>
-#include <linux/shm.h>
-#include <linux/stat.h>
-#include <linux/syscalls.h>
-#include <linux/mman.h>
-#include <linux/file.h>
-#include <linux/ipc.h>
-#include <linux/fs.h>
-
-#include <asm/setup.h>
-#include <asm/uaccess.h>
-#include <asm/cachectl.h>
-#include <asm/traps.h>
-#include <asm/cacheflush.h>
-#include <asm/unistd.h>
-
-/* sys_cacheflush -- flush (part of) the processor cache. */
-asmlinkage int
-sys_cacheflush (unsigned long addr, int scope, int cache, unsigned long len)
-{
- flush_cache_all();
- return(0);
-}
-
-asmlinkage int sys_getpagesize(void)
-{
- return PAGE_SIZE;
-}
-
-/*
- * Do a system call from kernel instead of calling sys_execve so we
- * end up with proper pt_regs.
- */
-int kernel_execve(const char *filename,
- const char *const argv[],
- const char *const envp[])
-{
- register long __res asm ("%d0") = __NR_execve;
- register long __a asm ("%d1") = (long)(filename);
- register long __b asm ("%d2") = (long)(argv);
- register long __c asm ("%d3") = (long)(envp);
- asm volatile ("trap #0" : "+d" (__res)
- : "d" (__a), "d" (__b), "d" (__c));
- return __res;
-}
-
-asmlinkage unsigned long sys_get_thread_area(void)
-{
- return current_thread_info()->tp_value;
-}
-
-asmlinkage int sys_set_thread_area(unsigned long tp)
-{
- current_thread_info()->tp_value = tp;
- return 0;
-}
-
-/* This syscall gets its arguments in A0 (mem), D2 (oldval) and
- D1 (newval). */
-asmlinkage int
-sys_atomic_cmpxchg_32(unsigned long newval, int oldval, int d3, int d4, int d5,
- unsigned long __user * mem)
-{
- struct mm_struct *mm = current->mm;
- unsigned long mem_value;
-
- down_read(&mm->mmap_sem);
-
- mem_value = *mem;
- if (mem_value == oldval)
- *mem = newval;
-
- up_read(&mm->mmap_sem);
- return mem_value;
-}
-
-asmlinkage int sys_atomic_barrier(void)
-{
- /* no code needed for uniprocs */
- return 0;
-}
diff --git a/arch/m68k/kernel/syscalltable.S b/arch/m68k/kernel/syscalltable.S
index 5909e39..6f7b091 100644
--- a/arch/m68k/kernel/syscalltable.S
+++ b/arch/m68k/kernel/syscalltable.S
@@ -11,7 +11,6 @@
* Linux/m68k support by Hamish Macdonald
*/
-#include <linux/sys.h>
#include <linux/linkage.h>
#ifndef CONFIG_MMU
diff --git a/arch/m68k/lib/Makefile b/arch/m68k/lib/Makefile
index 1f95881..df421e5 100644
--- a/arch/m68k/lib/Makefile
+++ b/arch/m68k/lib/Makefile
@@ -1,5 +1,14 @@
+
+#
+# Makefile for m68k-specific library files..
+#
+
+lib-y := ashldi3.o ashrdi3.o lshrdi3.o muldi3.o \
+ memcpy.o memset.o memmove.o
+
ifdef CONFIG_MMU
-include arch/m68k/lib/Makefile_mm
+lib-y += string.o uaccess.o checksum_mm.o
else
-include arch/m68k/lib/Makefile_no
+lib-y += mulsi3.o divsi3.o udivsi3.o modsi3.o umodsi3.o delay.o checksum_no.o
endif
+
diff --git a/arch/m68k/lib/Makefile_mm b/arch/m68k/lib/Makefile_mm
deleted file mode 100644
index af9abf8..0000000
--- a/arch/m68k/lib/Makefile_mm
+++ /dev/null
@@ -1,6 +0,0 @@
-#
-# Makefile for m68k-specific library files..
-#
-
-lib-y := ashldi3.o ashrdi3.o lshrdi3.o muldi3.o \
- checksum.o string.o uaccess.o
diff --git a/arch/m68k/lib/Makefile_no b/arch/m68k/lib/Makefile_no
deleted file mode 100644
index 32d852e..0000000
--- a/arch/m68k/lib/Makefile_no
+++ /dev/null
@@ -1,7 +0,0 @@
-#
-# Makefile for m68knommu specific library files..
-#
-
-lib-y := ashldi3.o ashrdi3.o lshrdi3.o \
- muldi3.o mulsi3.o divsi3.o udivsi3.o modsi3.o umodsi3.o \
- checksum.o memcpy.o memmove.o memset.o delay.o
diff --git a/arch/m68k/lib/checksum.c b/arch/m68k/lib/checksum.c
deleted file mode 100644
index 1297536..0000000
--- a/arch/m68k/lib/checksum.c
+++ /dev/null
@@ -1,5 +0,0 @@
-#ifdef CONFIG_MMU
-#include "checksum_mm.c"
-#else
-#include "checksum_no.c"
-#endif
diff --git a/arch/m68k/lib/checksum_no.c b/arch/m68k/lib/checksum_no.c
index eccf25d..e4c6354 100644
--- a/arch/m68k/lib/checksum_no.c
+++ b/arch/m68k/lib/checksum_no.c
@@ -101,6 +101,7 @@
{
return (__force __sum16)~do_csum(iph,ihl*4);
}
+EXPORT_SYMBOL(ip_fast_csum);
#endif
/*
@@ -140,6 +141,7 @@
memcpy(dst, (__force const void *)src, len);
return csum_partial(dst, len, sum);
}
+EXPORT_SYMBOL(csum_partial_copy_from_user);
/*
* copy from ds while checksumming, otherwise like csum_partial
@@ -151,3 +153,4 @@
memcpy(dst, src, len);
return csum_partial(dst, len, sum);
}
+EXPORT_SYMBOL(csum_partial_copy_nocheck);
diff --git a/arch/m68k/lib/memcpy.c b/arch/m68k/lib/memcpy.c
index b50dbca..62182c8 100644
--- a/arch/m68k/lib/memcpy.c
+++ b/arch/m68k/lib/memcpy.c
@@ -1,62 +1,80 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file COPYING in the main directory of this archive
+ * for more details.
+ */
-#include <linux/types.h>
+#include <linux/module.h>
+#include <linux/string.h>
-void * memcpy(void * to, const void * from, size_t n)
+void *memcpy(void *to, const void *from, size_t n)
{
-#ifdef CONFIG_COLDFIRE
- void *xto = to;
- size_t temp;
+ void *xto = to;
+ size_t temp, temp1;
- if (!n)
- return xto;
- if ((long) to & 1)
- {
- char *cto = to;
- const char *cfrom = from;
- *cto++ = *cfrom++;
- to = cto;
- from = cfrom;
- n--;
- }
- if (n > 2 && (long) to & 2)
- {
- short *sto = to;
- const short *sfrom = from;
- *sto++ = *sfrom++;
- to = sto;
- from = sfrom;
- n -= 2;
- }
- temp = n >> 2;
- if (temp)
- {
- long *lto = to;
- const long *lfrom = from;
- for (; temp; temp--)
- *lto++ = *lfrom++;
- to = lto;
- from = lfrom;
- }
- if (n & 2)
- {
- short *sto = to;
- const short *sfrom = from;
- *sto++ = *sfrom++;
- to = sto;
- from = sfrom;
- }
- if (n & 1)
- {
- char *cto = to;
- const char *cfrom = from;
- *cto = *cfrom;
- }
- return xto;
+ if (!n)
+ return xto;
+ if ((long)to & 1) {
+ char *cto = to;
+ const char *cfrom = from;
+ *cto++ = *cfrom++;
+ to = cto;
+ from = cfrom;
+ n--;
+ }
+ if (n > 2 && (long)to & 2) {
+ short *sto = to;
+ const short *sfrom = from;
+ *sto++ = *sfrom++;
+ to = sto;
+ from = sfrom;
+ n -= 2;
+ }
+ temp = n >> 2;
+ if (temp) {
+ long *lto = to;
+ const long *lfrom = from;
+#if defined(__mc68020__) || defined(__mc68030__) || \
+ defined(__mc68040__) || defined(__mc68060__) || defined(__mcpu32__)
+ asm volatile (
+ " movel %2,%3\n"
+ " andw #7,%3\n"
+ " lsrl #3,%2\n"
+ " negw %3\n"
+ " jmp %%pc@(1f,%3:w:2)\n"
+ "4: movel %0@+,%1@+\n"
+ " movel %0@+,%1@+\n"
+ " movel %0@+,%1@+\n"
+ " movel %0@+,%1@+\n"
+ " movel %0@+,%1@+\n"
+ " movel %0@+,%1@+\n"
+ " movel %0@+,%1@+\n"
+ " movel %0@+,%1@+\n"
+ "1: dbra %2,4b\n"
+ " clrw %2\n"
+ " subql #1,%2\n"
+ " jpl 4b"
+ : "=a" (lfrom), "=a" (lto), "=d" (temp), "=&d" (temp1)
+ : "0" (lfrom), "1" (lto), "2" (temp));
#else
- const char *c_from = from;
- char *c_to = to;
- while (n-- > 0)
- *c_to++ = *c_from++;
- return((void *) to);
+ for (; temp; temp--)
+ *lto++ = *lfrom++;
#endif
+ to = lto;
+ from = lfrom;
+ }
+ if (n & 2) {
+ short *sto = to;
+ const short *sfrom = from;
+ *sto++ = *sfrom++;
+ to = sto;
+ from = sfrom;
+ }
+ if (n & 1) {
+ char *cto = to;
+ const char *cfrom = from;
+ *cto = *cfrom;
+ }
+ return xto;
}
+EXPORT_SYMBOL(memcpy);
diff --git a/arch/m68k/lib/memmove.c b/arch/m68k/lib/memmove.c
index b3dcfe9..6519f7f 100644
--- a/arch/m68k/lib/memmove.c
+++ b/arch/m68k/lib/memmove.c
@@ -4,8 +4,6 @@
* for more details.
*/
-#define __IN_STRING_C
-
#include <linux/module.h>
#include <linux/string.h>
diff --git a/arch/m68k/lib/memset.c b/arch/m68k/lib/memset.c
index 1389bf4..f649e6a 100644
--- a/arch/m68k/lib/memset.c
+++ b/arch/m68k/lib/memset.c
@@ -1,47 +1,75 @@
-#include <linux/types.h>
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file COPYING in the main directory of this archive
+ * for more details.
+ */
-void * memset(void * s, int c, size_t count)
+#include <linux/module.h>
+#include <linux/string.h>
+
+void *memset(void *s, int c, size_t count)
{
- void *xs = s;
- size_t temp;
+ void *xs = s;
+ size_t temp;
- if (!count)
- return xs;
- c &= 0xff;
- c |= c << 8;
- c |= c << 16;
- if ((long) s & 1)
- {
- char *cs = s;
- *cs++ = c;
- s = cs;
- count--;
- }
- if (count > 2 && (long) s & 2)
- {
- short *ss = s;
- *ss++ = c;
- s = ss;
- count -= 2;
- }
- temp = count >> 2;
- if (temp)
- {
- long *ls = s;
- for (; temp; temp--)
- *ls++ = c;
- s = ls;
- }
- if (count & 2)
- {
- short *ss = s;
- *ss++ = c;
- s = ss;
- }
- if (count & 1)
- {
- char *cs = s;
- *cs = c;
- }
- return xs;
+ if (!count)
+ return xs;
+ c &= 0xff;
+ c |= c << 8;
+ c |= c << 16;
+ if ((long)s & 1) {
+ char *cs = s;
+ *cs++ = c;
+ s = cs;
+ count--;
+ }
+ if (count > 2 && (long)s & 2) {
+ short *ss = s;
+ *ss++ = c;
+ s = ss;
+ count -= 2;
+ }
+ temp = count >> 2;
+ if (temp) {
+ long *ls = s;
+#if defined(__mc68020__) || defined(__mc68030__) || \
+ defined(__mc68040__) || defined(__mc68060__) || defined(__mcpu32__)
+ size_t temp1;
+ asm volatile (
+ " movel %1,%2\n"
+ " andw #7,%2\n"
+ " lsrl #3,%1\n"
+ " negw %2\n"
+ " jmp %%pc@(2f,%2:w:2)\n"
+ "1: movel %3,%0@+\n"
+ " movel %3,%0@+\n"
+ " movel %3,%0@+\n"
+ " movel %3,%0@+\n"
+ " movel %3,%0@+\n"
+ " movel %3,%0@+\n"
+ " movel %3,%0@+\n"
+ " movel %3,%0@+\n"
+ "2: dbra %1,1b\n"
+ " clrw %1\n"
+ " subql #1,%1\n"
+ " jpl 1b"
+ : "=a" (ls), "=d" (temp), "=&d" (temp1)
+ : "d" (c), "0" (ls), "1" (temp));
+#else
+ for (; temp; temp--)
+ *ls++ = c;
+#endif
+ s = ls;
+ }
+ if (count & 2) {
+ short *ss = s;
+ *ss++ = c;
+ s = ss;
+ }
+ if (count & 1) {
+ char *cs = s;
+ *cs = c;
+ }
+ return xs;
}
+EXPORT_SYMBOL(memset);
diff --git a/arch/m68k/lib/muldi3.c b/arch/m68k/lib/muldi3.c
index 16e0eb3..079bafc 100644
--- a/arch/m68k/lib/muldi3.c
+++ b/arch/m68k/lib/muldi3.c
@@ -1,5 +1,98 @@
-#ifdef CONFIG_MMU
-#include "muldi3_mm.c"
+/* muldi3.c extracted from gcc-2.7.2.3/libgcc2.c and
+ gcc-2.7.2.3/longlong.h which is: */
+/* Copyright (C) 1989, 1992, 1993, 1994, 1995 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING. If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA. */
+
+#if defined(__mc68020__) || defined(__mc68030__) || \
+ defined(__mc68040__) || defined(__mc68060__) || defined(__mcpu32__)
+
+#define umul_ppmm(w1, w0, u, v) \
+ __asm__ ("mulu%.l %3,%1:%0" \
+ : "=d" ((USItype)(w0)), \
+ "=d" ((USItype)(w1)) \
+ : "%0" ((USItype)(u)), \
+ "dmi" ((USItype)(v)))
+
#else
-#include "muldi3_no.c"
+
+#define SI_TYPE_SIZE 32
+#define __BITS4 (SI_TYPE_SIZE / 4)
+#define __ll_B (1L << (SI_TYPE_SIZE / 2))
+#define __ll_lowpart(t) ((USItype) (t) % __ll_B)
+#define __ll_highpart(t) ((USItype) (t) / __ll_B)
+
+#define umul_ppmm(w1, w0, u, v) \
+ do { \
+ USItype __x0, __x1, __x2, __x3; \
+ USItype __ul, __vl, __uh, __vh; \
+ \
+ __ul = __ll_lowpart (u); \
+ __uh = __ll_highpart (u); \
+ __vl = __ll_lowpart (v); \
+ __vh = __ll_highpart (v); \
+ \
+ __x0 = (USItype) __ul * __vl; \
+ __x1 = (USItype) __ul * __vh; \
+ __x2 = (USItype) __uh * __vl; \
+ __x3 = (USItype) __uh * __vh; \
+ \
+ __x1 += __ll_highpart (__x0);/* this can't give carry */ \
+ __x1 += __x2; /* but this indeed can */ \
+ if (__x1 < __x2) /* did we get it? */ \
+ __x3 += __ll_B; /* yes, add it in the proper pos. */ \
+ \
+ (w1) = __x3 + __ll_highpart (__x1); \
+ (w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0); \
+ } while (0)
+
#endif
+
+#define __umulsidi3(u, v) \
+ ({DIunion __w; \
+ umul_ppmm (__w.s.high, __w.s.low, u, v); \
+ __w.ll; })
+
+typedef int SItype __attribute__ ((mode (SI)));
+typedef unsigned int USItype __attribute__ ((mode (SI)));
+typedef int DItype __attribute__ ((mode (DI)));
+typedef int word_type __attribute__ ((mode (__word__)));
+
+struct DIstruct {SItype high, low;};
+
+typedef union
+{
+ struct DIstruct s;
+ DItype ll;
+} DIunion;
+
+DItype
+__muldi3 (DItype u, DItype v)
+{
+ DIunion w;
+ DIunion uu, vv;
+
+ uu.ll = u,
+ vv.ll = v;
+
+ w.ll = __umulsidi3 (uu.s.low, vv.s.low);
+ w.s.high += ((USItype) uu.s.low * (USItype) vv.s.high
+ + (USItype) uu.s.high * (USItype) vv.s.low);
+
+ return w.ll;
+}
diff --git a/arch/m68k/lib/muldi3_mm.c b/arch/m68k/lib/muldi3_mm.c
deleted file mode 100644
index be4f275..0000000
--- a/arch/m68k/lib/muldi3_mm.c
+++ /dev/null
@@ -1,63 +0,0 @@
-/* muldi3.c extracted from gcc-2.7.2.3/libgcc2.c and
- gcc-2.7.2.3/longlong.h which is: */
-/* Copyright (C) 1989, 1992, 1993, 1994, 1995 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#define BITS_PER_UNIT 8
-
-#define umul_ppmm(w1, w0, u, v) \
- __asm__ ("mulu%.l %3,%1:%0" \
- : "=d" ((USItype)(w0)), \
- "=d" ((USItype)(w1)) \
- : "%0" ((USItype)(u)), \
- "dmi" ((USItype)(v)))
-
-#define __umulsidi3(u, v) \
- ({DIunion __w; \
- umul_ppmm (__w.s.high, __w.s.low, u, v); \
- __w.ll; })
-
-typedef int SItype __attribute__ ((mode (SI)));
-typedef unsigned int USItype __attribute__ ((mode (SI)));
-typedef int DItype __attribute__ ((mode (DI)));
-typedef int word_type __attribute__ ((mode (__word__)));
-
-struct DIstruct {SItype high, low;};
-
-typedef union
-{
- struct DIstruct s;
- DItype ll;
-} DIunion;
-
-DItype
-__muldi3 (DItype u, DItype v)
-{
- DIunion w;
- DIunion uu, vv;
-
- uu.ll = u,
- vv.ll = v;
-
- w.ll = __umulsidi3 (uu.s.low, vv.s.low);
- w.s.high += ((USItype) uu.s.low * (USItype) vv.s.high
- + (USItype) uu.s.high * (USItype) vv.s.low);
-
- return w.ll;
-}
diff --git a/arch/m68k/lib/muldi3_no.c b/arch/m68k/lib/muldi3_no.c
deleted file mode 100644
index 34af72c..0000000
--- a/arch/m68k/lib/muldi3_no.c
+++ /dev/null
@@ -1,86 +0,0 @@
-/* muldi3.c extracted from gcc-2.7.2.3/libgcc2.c and
- gcc-2.7.2.3/longlong.h which is: */
-/* Copyright (C) 1989, 1992, 1993, 1994, 1995 Free Software Foundation, Inc.
-
-This file is part of GNU CC.
-
-GNU CC is free software; you can redistribute it and/or modify
-it under the terms of the GNU General Public License as published by
-the Free Software Foundation; either version 2, or (at your option)
-any later version.
-
-GNU CC is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-GNU General Public License for more details.
-
-You should have received a copy of the GNU General Public License
-along with GNU CC; see the file COPYING. If not, write to
-the Free Software Foundation, 59 Temple Place - Suite 330,
-Boston, MA 02111-1307, USA. */
-
-#define BITS_PER_UNIT 8
-#define SI_TYPE_SIZE 32
-
-#define __BITS4 (SI_TYPE_SIZE / 4)
-#define __ll_B (1L << (SI_TYPE_SIZE / 2))
-#define __ll_lowpart(t) ((USItype) (t) % __ll_B)
-#define __ll_highpart(t) ((USItype) (t) / __ll_B)
-
-#define umul_ppmm(w1, w0, u, v) \
- do { \
- USItype __x0, __x1, __x2, __x3; \
- USItype __ul, __vl, __uh, __vh; \
- \
- __ul = __ll_lowpart (u); \
- __uh = __ll_highpart (u); \
- __vl = __ll_lowpart (v); \
- __vh = __ll_highpart (v); \
- \
- __x0 = (USItype) __ul * __vl; \
- __x1 = (USItype) __ul * __vh; \
- __x2 = (USItype) __uh * __vl; \
- __x3 = (USItype) __uh * __vh; \
- \
- __x1 += __ll_highpart (__x0);/* this can't give carry */ \
- __x1 += __x2; /* but this indeed can */ \
- if (__x1 < __x2) /* did we get it? */ \
- __x3 += __ll_B; /* yes, add it in the proper pos. */ \
- \
- (w1) = __x3 + __ll_highpart (__x1); \
- (w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0); \
- } while (0)
-
-#define __umulsidi3(u, v) \
- ({DIunion __w; \
- umul_ppmm (__w.s.high, __w.s.low, u, v); \
- __w.ll; })
-
-typedef int SItype __attribute__ ((mode (SI)));
-typedef unsigned int USItype __attribute__ ((mode (SI)));
-typedef int DItype __attribute__ ((mode (DI)));
-typedef int word_type __attribute__ ((mode (__word__)));
-
-struct DIstruct {SItype high, low;};
-
-typedef union
-{
- struct DIstruct s;
- DItype ll;
-} DIunion;
-
-DItype
-__muldi3 (DItype u, DItype v)
-{
- DIunion w;
- DIunion uu, vv;
-
- uu.ll = u,
- vv.ll = v;
-
- w.ll = __umulsidi3 (uu.s.low, vv.s.low);
- w.s.high += ((USItype) uu.s.low * (USItype) vv.s.high
- + (USItype) uu.s.high * (USItype) vv.s.low);
-
- return w.ll;
-}
diff --git a/arch/m68k/lib/string.c b/arch/m68k/lib/string.c
index d399c5f..b9a57ab 100644
--- a/arch/m68k/lib/string.c
+++ b/arch/m68k/lib/string.c
@@ -20,226 +20,3 @@
return __kernel_strcpy(dest + __kernel_strlen(dest), src);
}
EXPORT_SYMBOL(strcat);
-
-void *memset(void *s, int c, size_t count)
-{
- void *xs = s;
- size_t temp, temp1;
-
- if (!count)
- return xs;
- c &= 0xff;
- c |= c << 8;
- c |= c << 16;
- if ((long)s & 1) {
- char *cs = s;
- *cs++ = c;
- s = cs;
- count--;
- }
- if (count > 2 && (long)s & 2) {
- short *ss = s;
- *ss++ = c;
- s = ss;
- count -= 2;
- }
- temp = count >> 2;
- if (temp) {
- long *ls = s;
-
- asm volatile (
- " movel %1,%2\n"
- " andw #7,%2\n"
- " lsrl #3,%1\n"
- " negw %2\n"
- " jmp %%pc@(2f,%2:w:2)\n"
- "1: movel %3,%0@+\n"
- " movel %3,%0@+\n"
- " movel %3,%0@+\n"
- " movel %3,%0@+\n"
- " movel %3,%0@+\n"
- " movel %3,%0@+\n"
- " movel %3,%0@+\n"
- " movel %3,%0@+\n"
- "2: dbra %1,1b\n"
- " clrw %1\n"
- " subql #1,%1\n"
- " jpl 1b"
- : "=a" (ls), "=d" (temp), "=&d" (temp1)
- : "d" (c), "0" (ls), "1" (temp));
- s = ls;
- }
- if (count & 2) {
- short *ss = s;
- *ss++ = c;
- s = ss;
- }
- if (count & 1) {
- char *cs = s;
- *cs = c;
- }
- return xs;
-}
-EXPORT_SYMBOL(memset);
-
-void *memcpy(void *to, const void *from, size_t n)
-{
- void *xto = to;
- size_t temp, temp1;
-
- if (!n)
- return xto;
- if ((long)to & 1) {
- char *cto = to;
- const char *cfrom = from;
- *cto++ = *cfrom++;
- to = cto;
- from = cfrom;
- n--;
- }
- if (n > 2 && (long)to & 2) {
- short *sto = to;
- const short *sfrom = from;
- *sto++ = *sfrom++;
- to = sto;
- from = sfrom;
- n -= 2;
- }
- temp = n >> 2;
- if (temp) {
- long *lto = to;
- const long *lfrom = from;
-
- asm volatile (
- " movel %2,%3\n"
- " andw #7,%3\n"
- " lsrl #3,%2\n"
- " negw %3\n"
- " jmp %%pc@(1f,%3:w:2)\n"
- "4: movel %0@+,%1@+\n"
- " movel %0@+,%1@+\n"
- " movel %0@+,%1@+\n"
- " movel %0@+,%1@+\n"
- " movel %0@+,%1@+\n"
- " movel %0@+,%1@+\n"
- " movel %0@+,%1@+\n"
- " movel %0@+,%1@+\n"
- "1: dbra %2,4b\n"
- " clrw %2\n"
- " subql #1,%2\n"
- " jpl 4b"
- : "=a" (lfrom), "=a" (lto), "=d" (temp), "=&d" (temp1)
- : "0" (lfrom), "1" (lto), "2" (temp));
- to = lto;
- from = lfrom;
- }
- if (n & 2) {
- short *sto = to;
- const short *sfrom = from;
- *sto++ = *sfrom++;
- to = sto;
- from = sfrom;
- }
- if (n & 1) {
- char *cto = to;
- const char *cfrom = from;
- *cto = *cfrom;
- }
- return xto;
-}
-EXPORT_SYMBOL(memcpy);
-
-void *memmove(void *dest, const void *src, size_t n)
-{
- void *xdest = dest;
- size_t temp;
-
- if (!n)
- return xdest;
-
- if (dest < src) {
- if ((long)dest & 1) {
- char *cdest = dest;
- const char *csrc = src;
- *cdest++ = *csrc++;
- dest = cdest;
- src = csrc;
- n--;
- }
- if (n > 2 && (long)dest & 2) {
- short *sdest = dest;
- const short *ssrc = src;
- *sdest++ = *ssrc++;
- dest = sdest;
- src = ssrc;
- n -= 2;
- }
- temp = n >> 2;
- if (temp) {
- long *ldest = dest;
- const long *lsrc = src;
- temp--;
- do
- *ldest++ = *lsrc++;
- while (temp--);
- dest = ldest;
- src = lsrc;
- }
- if (n & 2) {
- short *sdest = dest;
- const short *ssrc = src;
- *sdest++ = *ssrc++;
- dest = sdest;
- src = ssrc;
- }
- if (n & 1) {
- char *cdest = dest;
- const char *csrc = src;
- *cdest = *csrc;
- }
- } else {
- dest = (char *)dest + n;
- src = (const char *)src + n;
- if ((long)dest & 1) {
- char *cdest = dest;
- const char *csrc = src;
- *--cdest = *--csrc;
- dest = cdest;
- src = csrc;
- n--;
- }
- if (n > 2 && (long)dest & 2) {
- short *sdest = dest;
- const short *ssrc = src;
- *--sdest = *--ssrc;
- dest = sdest;
- src = ssrc;
- n -= 2;
- }
- temp = n >> 2;
- if (temp) {
- long *ldest = dest;
- const long *lsrc = src;
- temp--;
- do
- *--ldest = *--lsrc;
- while (temp--);
- dest = ldest;
- src = lsrc;
- }
- if (n & 2) {
- short *sdest = dest;
- const short *ssrc = src;
- *--sdest = *--ssrc;
- dest = sdest;
- src = ssrc;
- }
- if (n & 1) {
- char *cdest = dest;
- const char *csrc = src;
- *--cdest = *--csrc;
- }
- }
- return xdest;
-}
-EXPORT_SYMBOL(memmove);
diff --git a/arch/m68k/mm/Makefile b/arch/m68k/mm/Makefile
index b60270e..09cadf1 100644
--- a/arch/m68k/mm/Makefile
+++ b/arch/m68k/mm/Makefile
@@ -1,5 +1,9 @@
-ifdef CONFIG_MMU
-include arch/m68k/mm/Makefile_mm
-else
-include arch/m68k/mm/Makefile_no
-endif
+#
+# Makefile for the linux m68k-specific parts of the memory manager.
+#
+
+obj-y := init.o
+
+obj-$(CONFIG_MMU) += cache.o fault.o hwtest.o
+obj-$(CONFIG_MMU_MOTOROLA) += kmap.o memory.o motorola.o
+obj-$(CONFIG_MMU_SUN3) += sun3kmap.o sun3mmu.o
diff --git a/arch/m68k/mm/Makefile_mm b/arch/m68k/mm/Makefile_mm
deleted file mode 100644
index 5eaa43c..0000000
--- a/arch/m68k/mm/Makefile_mm
+++ /dev/null
@@ -1,8 +0,0 @@
-#
-# Makefile for the linux m68k-specific parts of the memory manager.
-#
-
-obj-y := cache.o init.o fault.o hwtest.o
-
-obj-$(CONFIG_MMU_MOTOROLA) += kmap.o memory.o motorola.o
-obj-$(CONFIG_MMU_SUN3) += sun3kmap.o sun3mmu.o
diff --git a/arch/m68k/mm/Makefile_no b/arch/m68k/mm/Makefile_no
deleted file mode 100644
index b54ab6b..0000000
--- a/arch/m68k/mm/Makefile_no
+++ /dev/null
@@ -1,5 +0,0 @@
-#
-# Makefile for the linux m68knommu specific parts of the memory manager.
-#
-
-obj-y += init.o kmap.o
diff --git a/arch/m68k/mm/init_mm.c b/arch/m68k/mm/init_mm.c
index 8bc8425..9113c2f 100644
--- a/arch/m68k/mm/init_mm.c
+++ b/arch/m68k/mm/init_mm.c
@@ -32,8 +32,6 @@
#include <asm/sections.h>
#include <asm/tlb.h>
-DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
-
pg_data_t pg_data_map[MAX_NUMNODES];
EXPORT_SYMBOL(pg_data_map);
diff --git a/arch/m68k/mm/init_no.c b/arch/m68k/mm/init_no.c
index 8a6653f..7cbd7bd 100644
--- a/arch/m68k/mm/init_no.c
+++ b/arch/m68k/mm/init_no.c
@@ -38,28 +38,10 @@
#include <asm/system.h>
#include <asm/machdep.h>
-#undef DEBUG
-
-extern void die_if_kernel(char *,struct pt_regs *,long);
-extern void free_initmem(void);
-
/*
- * BAD_PAGE is the page that is used for page faults when linux
- * is out-of-memory. Older versions of linux just did a
- * do_exit(), but using this instead means there is less risk
- * for a process dying in kernel mode, possibly leaving a inode
- * unused etc..
- *
- * BAD_PAGETABLE is the accompanying page-table: it is initialized
- * to point to BAD_PAGE entries.
- *
* ZERO_PAGE is a special page that is used for zero-initialized
* data and COW.
*/
-static unsigned long empty_bad_page_table;
-
-static unsigned long empty_bad_page;
-
unsigned long empty_zero_page;
extern unsigned long memory_start;
@@ -77,22 +59,9 @@
* Make sure start_mem is page aligned, otherwise bootmem and
* page_alloc get different views of the world.
*/
-#ifdef DEBUG
- unsigned long start_mem = PAGE_ALIGN(memory_start);
-#endif
unsigned long end_mem = memory_end & PAGE_MASK;
+ unsigned long zones_size[MAX_NR_ZONES] = {0, };
-#ifdef DEBUG
- printk (KERN_DEBUG "start_mem is %#lx\nvirtual_end is %#lx\n",
- start_mem, end_mem);
-#endif
-
- /*
- * Initialize the bad page table and bad page to point
- * to a couple of allocated pages.
- */
- empty_bad_page_table = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
- empty_bad_page = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
empty_zero_page = (unsigned long)alloc_bootmem_pages(PAGE_SIZE);
memset((void *)empty_zero_page, 0, PAGE_SIZE);
@@ -101,19 +70,8 @@
*/
set_fs (USER_DS);
-#ifdef DEBUG
- printk (KERN_DEBUG "before free_area_init\n");
-
- printk (KERN_DEBUG "free_area_init -> start_mem is %#lx\nvirtual_end is %#lx\n",
- start_mem, end_mem);
-#endif
-
- {
- unsigned long zones_size[MAX_NR_ZONES] = {0, };
-
- zones_size[ZONE_DMA] = (end_mem - PAGE_OFFSET) >> PAGE_SHIFT;
- free_area_init(zones_size);
- }
+ zones_size[ZONE_DMA] = (end_mem - PAGE_OFFSET) >> PAGE_SHIFT;
+ free_area_init(zones_size);
}
void __init mem_init(void)
@@ -166,8 +124,7 @@
}
#endif
-void
-free_initmem()
+void free_initmem(void)
{
#ifdef CONFIG_RAMKERNEL
unsigned long addr;
diff --git a/arch/m68k/mm/kmap.c b/arch/m68k/mm/kmap.c
index a373d13..6934584 100644
--- a/arch/m68k/mm/kmap.c
+++ b/arch/m68k/mm/kmap.c
@@ -1,5 +1,367 @@
-#ifdef CONFIG_MMU
-#include "kmap_mm.c"
+/*
+ * linux/arch/m68k/mm/kmap.c
+ *
+ * Copyright (C) 1997 Roman Hodek
+ *
+ * 10/01/99 cleaned up the code and changing to the same interface
+ * used by other architectures /Roman Zippel
+ */
+
+#include <linux/module.h>
+#include <linux/mm.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <linux/vmalloc.h>
+
+#include <asm/setup.h>
+#include <asm/segment.h>
+#include <asm/page.h>
+#include <asm/pgalloc.h>
+#include <asm/io.h>
+#include <asm/system.h>
+
+#undef DEBUG
+
+#define PTRTREESIZE (256*1024)
+
+/*
+ * For 040/060 we can use the virtual memory area like other architectures,
+ * but for 020/030 we want to use early termination page descriptor and we
+ * can't mix this with normal page descriptors, so we have to copy that code
+ * (mm/vmalloc.c) and return appriorate aligned addresses.
+ */
+
+#ifdef CPU_M68040_OR_M68060_ONLY
+
+#define IO_SIZE PAGE_SIZE
+
+static inline struct vm_struct *get_io_area(unsigned long size)
+{
+ return get_vm_area(size, VM_IOREMAP);
+}
+
+
+static inline void free_io_area(void *addr)
+{
+ vfree((void *)(PAGE_MASK & (unsigned long)addr));
+}
+
#else
-#include "kmap_no.c"
+
+#define IO_SIZE (256*1024)
+
+static struct vm_struct *iolist;
+
+static struct vm_struct *get_io_area(unsigned long size)
+{
+ unsigned long addr;
+ struct vm_struct **p, *tmp, *area;
+
+ area = kmalloc(sizeof(*area), GFP_KERNEL);
+ if (!area)
+ return NULL;
+ addr = KMAP_START;
+ for (p = &iolist; (tmp = *p) ; p = &tmp->next) {
+ if (size + addr < (unsigned long)tmp->addr)
+ break;
+ if (addr > KMAP_END-size) {
+ kfree(area);
+ return NULL;
+ }
+ addr = tmp->size + (unsigned long)tmp->addr;
+ }
+ area->addr = (void *)addr;
+ area->size = size + IO_SIZE;
+ area->next = *p;
+ *p = area;
+ return area;
+}
+
+static inline void free_io_area(void *addr)
+{
+ struct vm_struct **p, *tmp;
+
+ if (!addr)
+ return;
+ addr = (void *)((unsigned long)addr & -IO_SIZE);
+ for (p = &iolist ; (tmp = *p) ; p = &tmp->next) {
+ if (tmp->addr == addr) {
+ *p = tmp->next;
+ __iounmap(tmp->addr, tmp->size);
+ kfree(tmp);
+ return;
+ }
+ }
+}
+
#endif
+
+/*
+ * Map some physical address range into the kernel address space.
+ */
+/* Rewritten by Andreas Schwab to remove all races. */
+
+void __iomem *__ioremap(unsigned long physaddr, unsigned long size, int cacheflag)
+{
+ struct vm_struct *area;
+ unsigned long virtaddr, retaddr;
+ long offset;
+ pgd_t *pgd_dir;
+ pmd_t *pmd_dir;
+ pte_t *pte_dir;
+
+ /*
+ * Don't allow mappings that wrap..
+ */
+ if (!size || physaddr > (unsigned long)(-size))
+ return NULL;
+
+#ifdef CONFIG_AMIGA
+ if (MACH_IS_AMIGA) {
+ if ((physaddr >= 0x40000000) && (physaddr + size < 0x60000000)
+ && (cacheflag == IOMAP_NOCACHE_SER))
+ return (void __iomem *)physaddr;
+ }
+#endif
+
+#ifdef DEBUG
+ printk("ioremap: 0x%lx,0x%lx(%d) - ", physaddr, size, cacheflag);
+#endif
+ /*
+ * Mappings have to be aligned
+ */
+ offset = physaddr & (IO_SIZE - 1);
+ physaddr &= -IO_SIZE;
+ size = (size + offset + IO_SIZE - 1) & -IO_SIZE;
+
+ /*
+ * Ok, go for it..
+ */
+ area = get_io_area(size);
+ if (!area)
+ return NULL;
+
+ virtaddr = (unsigned long)area->addr;
+ retaddr = virtaddr + offset;
+#ifdef DEBUG
+ printk("0x%lx,0x%lx,0x%lx", physaddr, virtaddr, retaddr);
+#endif
+
+ /*
+ * add cache and table flags to physical address
+ */
+ if (CPU_IS_040_OR_060) {
+ physaddr |= (_PAGE_PRESENT | _PAGE_GLOBAL040 |
+ _PAGE_ACCESSED | _PAGE_DIRTY);
+ switch (cacheflag) {
+ case IOMAP_FULL_CACHING:
+ physaddr |= _PAGE_CACHE040;
+ break;
+ case IOMAP_NOCACHE_SER:
+ default:
+ physaddr |= _PAGE_NOCACHE_S;
+ break;
+ case IOMAP_NOCACHE_NONSER:
+ physaddr |= _PAGE_NOCACHE;
+ break;
+ case IOMAP_WRITETHROUGH:
+ physaddr |= _PAGE_CACHE040W;
+ break;
+ }
+ } else {
+ physaddr |= (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_DIRTY);
+ switch (cacheflag) {
+ case IOMAP_NOCACHE_SER:
+ case IOMAP_NOCACHE_NONSER:
+ default:
+ physaddr |= _PAGE_NOCACHE030;
+ break;
+ case IOMAP_FULL_CACHING:
+ case IOMAP_WRITETHROUGH:
+ break;
+ }
+ }
+
+ while ((long)size > 0) {
+#ifdef DEBUG
+ if (!(virtaddr & (PTRTREESIZE-1)))
+ printk ("\npa=%#lx va=%#lx ", physaddr, virtaddr);
+#endif
+ pgd_dir = pgd_offset_k(virtaddr);
+ pmd_dir = pmd_alloc(&init_mm, pgd_dir, virtaddr);
+ if (!pmd_dir) {
+ printk("ioremap: no mem for pmd_dir\n");
+ return NULL;
+ }
+
+ if (CPU_IS_020_OR_030) {
+ pmd_dir->pmd[(virtaddr/PTRTREESIZE) & 15] = physaddr;
+ physaddr += PTRTREESIZE;
+ virtaddr += PTRTREESIZE;
+ size -= PTRTREESIZE;
+ } else {
+ pte_dir = pte_alloc_kernel(pmd_dir, virtaddr);
+ if (!pte_dir) {
+ printk("ioremap: no mem for pte_dir\n");
+ return NULL;
+ }
+
+ pte_val(*pte_dir) = physaddr;
+ virtaddr += PAGE_SIZE;
+ physaddr += PAGE_SIZE;
+ size -= PAGE_SIZE;
+ }
+ }
+#ifdef DEBUG
+ printk("\n");
+#endif
+ flush_tlb_all();
+
+ return (void __iomem *)retaddr;
+}
+EXPORT_SYMBOL(__ioremap);
+
+/*
+ * Unmap a ioremap()ed region again
+ */
+void iounmap(void __iomem *addr)
+{
+#ifdef CONFIG_AMIGA
+ if ((!MACH_IS_AMIGA) ||
+ (((unsigned long)addr < 0x40000000) ||
+ ((unsigned long)addr > 0x60000000)))
+ free_io_area((__force void *)addr);
+#else
+ free_io_area((__force void *)addr);
+#endif
+}
+EXPORT_SYMBOL(iounmap);
+
+/*
+ * __iounmap unmaps nearly everything, so be careful
+ * it doesn't free currently pointer/page tables anymore but it
+ * wans't used anyway and might be added later.
+ */
+void __iounmap(void *addr, unsigned long size)
+{
+ unsigned long virtaddr = (unsigned long)addr;
+ pgd_t *pgd_dir;
+ pmd_t *pmd_dir;
+ pte_t *pte_dir;
+
+ while ((long)size > 0) {
+ pgd_dir = pgd_offset_k(virtaddr);
+ if (pgd_bad(*pgd_dir)) {
+ printk("iounmap: bad pgd(%08lx)\n", pgd_val(*pgd_dir));
+ pgd_clear(pgd_dir);
+ return;
+ }
+ pmd_dir = pmd_offset(pgd_dir, virtaddr);
+
+ if (CPU_IS_020_OR_030) {
+ int pmd_off = (virtaddr/PTRTREESIZE) & 15;
+ int pmd_type = pmd_dir->pmd[pmd_off] & _DESCTYPE_MASK;
+
+ if (pmd_type == _PAGE_PRESENT) {
+ pmd_dir->pmd[pmd_off] = 0;
+ virtaddr += PTRTREESIZE;
+ size -= PTRTREESIZE;
+ continue;
+ } else if (pmd_type == 0)
+ continue;
+ }
+
+ if (pmd_bad(*pmd_dir)) {
+ printk("iounmap: bad pmd (%08lx)\n", pmd_val(*pmd_dir));
+ pmd_clear(pmd_dir);
+ return;
+ }
+ pte_dir = pte_offset_kernel(pmd_dir, virtaddr);
+
+ pte_val(*pte_dir) = 0;
+ virtaddr += PAGE_SIZE;
+ size -= PAGE_SIZE;
+ }
+
+ flush_tlb_all();
+}
+
+/*
+ * Set new cache mode for some kernel address space.
+ * The caller must push data for that range itself, if such data may already
+ * be in the cache.
+ */
+void kernel_set_cachemode(void *addr, unsigned long size, int cmode)
+{
+ unsigned long virtaddr = (unsigned long)addr;
+ pgd_t *pgd_dir;
+ pmd_t *pmd_dir;
+ pte_t *pte_dir;
+
+ if (CPU_IS_040_OR_060) {
+ switch (cmode) {
+ case IOMAP_FULL_CACHING:
+ cmode = _PAGE_CACHE040;
+ break;
+ case IOMAP_NOCACHE_SER:
+ default:
+ cmode = _PAGE_NOCACHE_S;
+ break;
+ case IOMAP_NOCACHE_NONSER:
+ cmode = _PAGE_NOCACHE;
+ break;
+ case IOMAP_WRITETHROUGH:
+ cmode = _PAGE_CACHE040W;
+ break;
+ }
+ } else {
+ switch (cmode) {
+ case IOMAP_NOCACHE_SER:
+ case IOMAP_NOCACHE_NONSER:
+ default:
+ cmode = _PAGE_NOCACHE030;
+ break;
+ case IOMAP_FULL_CACHING:
+ case IOMAP_WRITETHROUGH:
+ cmode = 0;
+ }
+ }
+
+ while ((long)size > 0) {
+ pgd_dir = pgd_offset_k(virtaddr);
+ if (pgd_bad(*pgd_dir)) {
+ printk("iocachemode: bad pgd(%08lx)\n", pgd_val(*pgd_dir));
+ pgd_clear(pgd_dir);
+ return;
+ }
+ pmd_dir = pmd_offset(pgd_dir, virtaddr);
+
+ if (CPU_IS_020_OR_030) {
+ int pmd_off = (virtaddr/PTRTREESIZE) & 15;
+
+ if ((pmd_dir->pmd[pmd_off] & _DESCTYPE_MASK) == _PAGE_PRESENT) {
+ pmd_dir->pmd[pmd_off] = (pmd_dir->pmd[pmd_off] &
+ _CACHEMASK040) | cmode;
+ virtaddr += PTRTREESIZE;
+ size -= PTRTREESIZE;
+ continue;
+ }
+ }
+
+ if (pmd_bad(*pmd_dir)) {
+ printk("iocachemode: bad pmd (%08lx)\n", pmd_val(*pmd_dir));
+ pmd_clear(pmd_dir);
+ return;
+ }
+ pte_dir = pte_offset_kernel(pmd_dir, virtaddr);
+
+ pte_val(*pte_dir) = (pte_val(*pte_dir) & _CACHEMASK040) | cmode;
+ virtaddr += PAGE_SIZE;
+ size -= PAGE_SIZE;
+ }
+
+ flush_tlb_all();
+}
+EXPORT_SYMBOL(kernel_set_cachemode);
diff --git a/arch/m68k/mm/kmap_mm.c b/arch/m68k/mm/kmap_mm.c
deleted file mode 100644
index 6934584..0000000
--- a/arch/m68k/mm/kmap_mm.c
+++ /dev/null
@@ -1,367 +0,0 @@
-/*
- * linux/arch/m68k/mm/kmap.c
- *
- * Copyright (C) 1997 Roman Hodek
- *
- * 10/01/99 cleaned up the code and changing to the same interface
- * used by other architectures /Roman Zippel
- */
-
-#include <linux/module.h>
-#include <linux/mm.h>
-#include <linux/kernel.h>
-#include <linux/string.h>
-#include <linux/types.h>
-#include <linux/slab.h>
-#include <linux/vmalloc.h>
-
-#include <asm/setup.h>
-#include <asm/segment.h>
-#include <asm/page.h>
-#include <asm/pgalloc.h>
-#include <asm/io.h>
-#include <asm/system.h>
-
-#undef DEBUG
-
-#define PTRTREESIZE (256*1024)
-
-/*
- * For 040/060 we can use the virtual memory area like other architectures,
- * but for 020/030 we want to use early termination page descriptor and we
- * can't mix this with normal page descriptors, so we have to copy that code
- * (mm/vmalloc.c) and return appriorate aligned addresses.
- */
-
-#ifdef CPU_M68040_OR_M68060_ONLY
-
-#define IO_SIZE PAGE_SIZE
-
-static inline struct vm_struct *get_io_area(unsigned long size)
-{
- return get_vm_area(size, VM_IOREMAP);
-}
-
-
-static inline void free_io_area(void *addr)
-{
- vfree((void *)(PAGE_MASK & (unsigned long)addr));
-}
-
-#else
-
-#define IO_SIZE (256*1024)
-
-static struct vm_struct *iolist;
-
-static struct vm_struct *get_io_area(unsigned long size)
-{
- unsigned long addr;
- struct vm_struct **p, *tmp, *area;
-
- area = kmalloc(sizeof(*area), GFP_KERNEL);
- if (!area)
- return NULL;
- addr = KMAP_START;
- for (p = &iolist; (tmp = *p) ; p = &tmp->next) {
- if (size + addr < (unsigned long)tmp->addr)
- break;
- if (addr > KMAP_END-size) {
- kfree(area);
- return NULL;
- }
- addr = tmp->size + (unsigned long)tmp->addr;
- }
- area->addr = (void *)addr;
- area->size = size + IO_SIZE;
- area->next = *p;
- *p = area;
- return area;
-}
-
-static inline void free_io_area(void *addr)
-{
- struct vm_struct **p, *tmp;
-
- if (!addr)
- return;
- addr = (void *)((unsigned long)addr & -IO_SIZE);
- for (p = &iolist ; (tmp = *p) ; p = &tmp->next) {
- if (tmp->addr == addr) {
- *p = tmp->next;
- __iounmap(tmp->addr, tmp->size);
- kfree(tmp);
- return;
- }
- }
-}
-
-#endif
-
-/*
- * Map some physical address range into the kernel address space.
- */
-/* Rewritten by Andreas Schwab to remove all races. */
-
-void __iomem *__ioremap(unsigned long physaddr, unsigned long size, int cacheflag)
-{
- struct vm_struct *area;
- unsigned long virtaddr, retaddr;
- long offset;
- pgd_t *pgd_dir;
- pmd_t *pmd_dir;
- pte_t *pte_dir;
-
- /*
- * Don't allow mappings that wrap..
- */
- if (!size || physaddr > (unsigned long)(-size))
- return NULL;
-
-#ifdef CONFIG_AMIGA
- if (MACH_IS_AMIGA) {
- if ((physaddr >= 0x40000000) && (physaddr + size < 0x60000000)
- && (cacheflag == IOMAP_NOCACHE_SER))
- return (void __iomem *)physaddr;
- }
-#endif
-
-#ifdef DEBUG
- printk("ioremap: 0x%lx,0x%lx(%d) - ", physaddr, size, cacheflag);
-#endif
- /*
- * Mappings have to be aligned
- */
- offset = physaddr & (IO_SIZE - 1);
- physaddr &= -IO_SIZE;
- size = (size + offset + IO_SIZE - 1) & -IO_SIZE;
-
- /*
- * Ok, go for it..
- */
- area = get_io_area(size);
- if (!area)
- return NULL;
-
- virtaddr = (unsigned long)area->addr;
- retaddr = virtaddr + offset;
-#ifdef DEBUG
- printk("0x%lx,0x%lx,0x%lx", physaddr, virtaddr, retaddr);
-#endif
-
- /*
- * add cache and table flags to physical address
- */
- if (CPU_IS_040_OR_060) {
- physaddr |= (_PAGE_PRESENT | _PAGE_GLOBAL040 |
- _PAGE_ACCESSED | _PAGE_DIRTY);
- switch (cacheflag) {
- case IOMAP_FULL_CACHING:
- physaddr |= _PAGE_CACHE040;
- break;
- case IOMAP_NOCACHE_SER:
- default:
- physaddr |= _PAGE_NOCACHE_S;
- break;
- case IOMAP_NOCACHE_NONSER:
- physaddr |= _PAGE_NOCACHE;
- break;
- case IOMAP_WRITETHROUGH:
- physaddr |= _PAGE_CACHE040W;
- break;
- }
- } else {
- physaddr |= (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_DIRTY);
- switch (cacheflag) {
- case IOMAP_NOCACHE_SER:
- case IOMAP_NOCACHE_NONSER:
- default:
- physaddr |= _PAGE_NOCACHE030;
- break;
- case IOMAP_FULL_CACHING:
- case IOMAP_WRITETHROUGH:
- break;
- }
- }
-
- while ((long)size > 0) {
-#ifdef DEBUG
- if (!(virtaddr & (PTRTREESIZE-1)))
- printk ("\npa=%#lx va=%#lx ", physaddr, virtaddr);
-#endif
- pgd_dir = pgd_offset_k(virtaddr);
- pmd_dir = pmd_alloc(&init_mm, pgd_dir, virtaddr);
- if (!pmd_dir) {
- printk("ioremap: no mem for pmd_dir\n");
- return NULL;
- }
-
- if (CPU_IS_020_OR_030) {
- pmd_dir->pmd[(virtaddr/PTRTREESIZE) & 15] = physaddr;
- physaddr += PTRTREESIZE;
- virtaddr += PTRTREESIZE;
- size -= PTRTREESIZE;
- } else {
- pte_dir = pte_alloc_kernel(pmd_dir, virtaddr);
- if (!pte_dir) {
- printk("ioremap: no mem for pte_dir\n");
- return NULL;
- }
-
- pte_val(*pte_dir) = physaddr;
- virtaddr += PAGE_SIZE;
- physaddr += PAGE_SIZE;
- size -= PAGE_SIZE;
- }
- }
-#ifdef DEBUG
- printk("\n");
-#endif
- flush_tlb_all();
-
- return (void __iomem *)retaddr;
-}
-EXPORT_SYMBOL(__ioremap);
-
-/*
- * Unmap a ioremap()ed region again
- */
-void iounmap(void __iomem *addr)
-{
-#ifdef CONFIG_AMIGA
- if ((!MACH_IS_AMIGA) ||
- (((unsigned long)addr < 0x40000000) ||
- ((unsigned long)addr > 0x60000000)))
- free_io_area((__force void *)addr);
-#else
- free_io_area((__force void *)addr);
-#endif
-}
-EXPORT_SYMBOL(iounmap);
-
-/*
- * __iounmap unmaps nearly everything, so be careful
- * it doesn't free currently pointer/page tables anymore but it
- * wans't used anyway and might be added later.
- */
-void __iounmap(void *addr, unsigned long size)
-{
- unsigned long virtaddr = (unsigned long)addr;
- pgd_t *pgd_dir;
- pmd_t *pmd_dir;
- pte_t *pte_dir;
-
- while ((long)size > 0) {
- pgd_dir = pgd_offset_k(virtaddr);
- if (pgd_bad(*pgd_dir)) {
- printk("iounmap: bad pgd(%08lx)\n", pgd_val(*pgd_dir));
- pgd_clear(pgd_dir);
- return;
- }
- pmd_dir = pmd_offset(pgd_dir, virtaddr);
-
- if (CPU_IS_020_OR_030) {
- int pmd_off = (virtaddr/PTRTREESIZE) & 15;
- int pmd_type = pmd_dir->pmd[pmd_off] & _DESCTYPE_MASK;
-
- if (pmd_type == _PAGE_PRESENT) {
- pmd_dir->pmd[pmd_off] = 0;
- virtaddr += PTRTREESIZE;
- size -= PTRTREESIZE;
- continue;
- } else if (pmd_type == 0)
- continue;
- }
-
- if (pmd_bad(*pmd_dir)) {
- printk("iounmap: bad pmd (%08lx)\n", pmd_val(*pmd_dir));
- pmd_clear(pmd_dir);
- return;
- }
- pte_dir = pte_offset_kernel(pmd_dir, virtaddr);
-
- pte_val(*pte_dir) = 0;
- virtaddr += PAGE_SIZE;
- size -= PAGE_SIZE;
- }
-
- flush_tlb_all();
-}
-
-/*
- * Set new cache mode for some kernel address space.
- * The caller must push data for that range itself, if such data may already
- * be in the cache.
- */
-void kernel_set_cachemode(void *addr, unsigned long size, int cmode)
-{
- unsigned long virtaddr = (unsigned long)addr;
- pgd_t *pgd_dir;
- pmd_t *pmd_dir;
- pte_t *pte_dir;
-
- if (CPU_IS_040_OR_060) {
- switch (cmode) {
- case IOMAP_FULL_CACHING:
- cmode = _PAGE_CACHE040;
- break;
- case IOMAP_NOCACHE_SER:
- default:
- cmode = _PAGE_NOCACHE_S;
- break;
- case IOMAP_NOCACHE_NONSER:
- cmode = _PAGE_NOCACHE;
- break;
- case IOMAP_WRITETHROUGH:
- cmode = _PAGE_CACHE040W;
- break;
- }
- } else {
- switch (cmode) {
- case IOMAP_NOCACHE_SER:
- case IOMAP_NOCACHE_NONSER:
- default:
- cmode = _PAGE_NOCACHE030;
- break;
- case IOMAP_FULL_CACHING:
- case IOMAP_WRITETHROUGH:
- cmode = 0;
- }
- }
-
- while ((long)size > 0) {
- pgd_dir = pgd_offset_k(virtaddr);
- if (pgd_bad(*pgd_dir)) {
- printk("iocachemode: bad pgd(%08lx)\n", pgd_val(*pgd_dir));
- pgd_clear(pgd_dir);
- return;
- }
- pmd_dir = pmd_offset(pgd_dir, virtaddr);
-
- if (CPU_IS_020_OR_030) {
- int pmd_off = (virtaddr/PTRTREESIZE) & 15;
-
- if ((pmd_dir->pmd[pmd_off] & _DESCTYPE_MASK) == _PAGE_PRESENT) {
- pmd_dir->pmd[pmd_off] = (pmd_dir->pmd[pmd_off] &
- _CACHEMASK040) | cmode;
- virtaddr += PTRTREESIZE;
- size -= PTRTREESIZE;
- continue;
- }
- }
-
- if (pmd_bad(*pmd_dir)) {
- printk("iocachemode: bad pmd (%08lx)\n", pmd_val(*pmd_dir));
- pmd_clear(pmd_dir);
- return;
- }
- pte_dir = pte_offset_kernel(pmd_dir, virtaddr);
-
- pte_val(*pte_dir) = (pte_val(*pte_dir) & _CACHEMASK040) | cmode;
- virtaddr += PAGE_SIZE;
- size -= PAGE_SIZE;
- }
-
- flush_tlb_all();
-}
-EXPORT_SYMBOL(kernel_set_cachemode);
diff --git a/arch/m68k/mm/kmap_no.c b/arch/m68k/mm/kmap_no.c
deleted file mode 100644
index ece8d5a..0000000
--- a/arch/m68k/mm/kmap_no.c
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * linux/arch/m68knommu/mm/kmap.c
- *
- * Copyright (C) 2000 Lineo, <davidm@snapgear.com>
- * Copyright (C) 2000-2002 David McCullough <davidm@snapgear.com>
- */
-
-#include <linux/mm.h>
-#include <linux/kernel.h>
-#include <linux/string.h>
-#include <linux/types.h>
-#include <linux/vmalloc.h>
-
-#include <asm/setup.h>
-#include <asm/segment.h>
-#include <asm/page.h>
-#include <asm/pgalloc.h>
-#include <asm/io.h>
-#include <asm/system.h>
-
-#undef DEBUG
-
-/*
- * Map some physical address range into the kernel address space.
- */
-void *__ioremap(unsigned long physaddr, unsigned long size, int cacheflag)
-{
- return (void *)physaddr;
-}
-
-/*
- * Unmap a ioremap()ed region again.
- */
-void iounmap(void *addr)
-{
-}
-
-/*
- * Set new cache mode for some kernel address space.
- * The caller must push data for that range itself, if such data may already
- * be in the cache.
- */
-void kernel_set_cachemode(void *addr, unsigned long size, int cmode)
-{
-}
diff --git a/arch/m68k/platform/68328/entry.S b/arch/m68k/platform/68328/entry.S
index 676960c..f68dce7 100644
--- a/arch/m68k/platform/68328/entry.S
+++ b/arch/m68k/platform/68328/entry.S
@@ -10,7 +10,6 @@
* Linux/m68k support by Hamish Macdonald
*/
-#include <linux/sys.h>
#include <linux/linkage.h>
#include <asm/thread_info.h>
#include <asm/unistd.h>
@@ -80,7 +79,7 @@
movel %sp,%d1 /* get thread_info pointer */
andl #-THREAD_SIZE,%d1
movel %d1,%a2
- btst #(TIF_SYSCALL_TRACE%8),%a2@(TI_FLAGS+(31-TIF_SYSCALL_TRACE)/8)
+ btst #(TIF_SYSCALL_TRACE%8),%a2@(TINFO_FLAGS+(31-TIF_SYSCALL_TRACE)/8)
jne do_trace
cmpl #NR_syscalls,%d0
jcc badsys
@@ -107,12 +106,12 @@
andl #-THREAD_SIZE,%d1
movel %d1,%a2
1:
- move %a2@(TI_FLAGS),%d1 /* thread_info->flags */
+ move %a2@(TINFO_FLAGS),%d1 /* thread_info->flags */
jne Lwork_to_do
RESTORE_ALL
Lwork_to_do:
- movel %a2@(TI_FLAGS),%d1 /* thread_info->flags */
+ movel %a2@(TINFO_FLAGS),%d1 /* thread_info->flags */
btst #TIF_NEED_RESCHED,%d1
jne reschedule
diff --git a/arch/m68k/platform/68360/entry.S b/arch/m68k/platform/68360/entry.S
index 46c1b18..a07b14f 100644
--- a/arch/m68k/platform/68360/entry.S
+++ b/arch/m68k/platform/68360/entry.S
@@ -12,7 +12,6 @@
* M68360 Port by SED Systems, and Lineo.
*/
-#include <linux/sys.h>
#include <linux/linkage.h>
#include <asm/thread_info.h>
#include <asm/unistd.h>
@@ -76,7 +75,7 @@
movel %sp,%d1 /* get thread_info pointer */
andl #-THREAD_SIZE,%d1
movel %d1,%a2
- btst #(TIF_SYSCALL_TRACE%8),%a2@(TI_FLAGS+(31-TIF_SYSCALL_TRACE)/8)
+ btst #(TIF_SYSCALL_TRACE%8),%a2@(TINFO_FLAGS+(31-TIF_SYSCALL_TRACE)/8)
jne do_trace
cmpl #NR_syscalls,%d0
jcc badsys
@@ -103,12 +102,12 @@
andl #-THREAD_SIZE,%d1
movel %d1,%a2
1:
- move %a2@(TI_FLAGS),%d1 /* thread_info->flags */
+ move %a2@(TINFO_FLAGS),%d1 /* thread_info->flags */
jne Lwork_to_do
RESTORE_ALL
Lwork_to_do:
- movel %a2@(TI_FLAGS),%d1 /* thread_info->flags */
+ movel %a2@(TINFO_FLAGS),%d1 /* thread_info->flags */
btst #TIF_NEED_RESCHED,%d1
jne reschedule
diff --git a/arch/m68k/platform/coldfire/dma.c b/arch/m68k/platform/coldfire/dma.c
index e88b95e..df5ce20 100644
--- a/arch/m68k/platform/coldfire/dma.c
+++ b/arch/m68k/platform/coldfire/dma.c
@@ -9,6 +9,7 @@
/***************************************************************************/
#include <linux/kernel.h>
+#include <linux/module.h>
#include <asm/dma.h>
#include <asm/coldfire.h>
#include <asm/mcfsim.h>
@@ -33,7 +34,9 @@
MCFDMA_BASE3,
#endif
};
+EXPORT_SYMBOL(dma_base_addr);
unsigned int dma_device_address[MAX_M68K_DMA_CHANNELS];
+EXPORT_SYMBOL(dma_device_address);
/***************************************************************************/
diff --git a/arch/m68k/platform/coldfire/entry.S b/arch/m68k/platform/coldfire/entry.S
index eab63f0..27c2b00 100644
--- a/arch/m68k/platform/coldfire/entry.S
+++ b/arch/m68k/platform/coldfire/entry.S
@@ -26,7 +26,6 @@
* Bug, speed and maintainability fixes by Philippe De Muyter <phdm@macqel.be>
*/
-#include <linux/sys.h>
#include <linux/linkage.h>
#include <asm/unistd.h>
#include <asm/thread_info.h>
@@ -78,7 +77,7 @@
movel %d2,%a0
movel %a0@,%a1 /* save top of frame */
movel %sp,%a1@(TASK_THREAD+THREAD_ESP0)
- btst #(TIF_SYSCALL_TRACE%8),%a0@(TI_FLAGS+(31-TIF_SYSCALL_TRACE)/8)
+ btst #(TIF_SYSCALL_TRACE%8),%a0@(TINFO_FLAGS+(31-TIF_SYSCALL_TRACE)/8)
bnes 1f
movel %d3,%a0
@@ -113,11 +112,11 @@
movel %sp,%d1 /* get thread_info pointer */
andl #-THREAD_SIZE,%d1 /* at base of kernel stack */
movel %d1,%a0
- movel %a0@(TI_FLAGS),%d1 /* get thread_info->flags */
+ movel %a0@(TINFO_FLAGS),%d1 /* get thread_info->flags */
andl #(1<<TIF_NEED_RESCHED),%d1
jeq Lkernel_return
- movel %a0@(TI_PREEMPTCOUNT),%d1
+ movel %a0@(TINFO_PREEMPT),%d1
cmpl #0,%d1
jne Lkernel_return
@@ -137,14 +136,14 @@
movel %sp,%d1 /* get thread_info pointer */
andl #-THREAD_SIZE,%d1 /* at base of kernel stack */
movel %d1,%a0
- movel %a0@(TI_FLAGS),%d1 /* get thread_info->flags */
+ movel %a0@(TINFO_FLAGS),%d1 /* get thread_info->flags */
jne Lwork_to_do /* still work to do */
Lreturn:
RESTORE_USER
Lwork_to_do:
- movel %a0@(TI_FLAGS),%d1 /* get thread_info->flags */
+ movel %a0@(TINFO_FLAGS),%d1 /* get thread_info->flags */
move #0x2000,%sr /* enable intrs again */
btst #TIF_NEED_RESCHED,%d1
jne reschedule
diff --git a/arch/m68k/platform/coldfire/head.S b/arch/m68k/platform/coldfire/head.S
index 6ae91a4..c334838 100644
--- a/arch/m68k/platform/coldfire/head.S
+++ b/arch/m68k/platform/coldfire/head.S
@@ -8,7 +8,6 @@
/*****************************************************************************/
-#include <linux/sys.h>
#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/asm-offsets.h>
diff --git a/arch/microblaze/mm/init.c b/arch/microblaze/mm/init.c
index c843786..213f2d6 100644
--- a/arch/microblaze/mm/init.c
+++ b/arch/microblaze/mm/init.c
@@ -32,8 +32,6 @@
EXPORT_SYMBOL(__page_offset);
#else
-DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
-
static int init_bootmem_done;
#endif /* CONFIG_MMU */
diff --git a/arch/mips/Kconfig.debug b/arch/mips/Kconfig.debug
index 5358f90..83ed00a 100644
--- a/arch/mips/Kconfig.debug
+++ b/arch/mips/Kconfig.debug
@@ -76,15 +76,6 @@
provides another way to check stack overflow happened on kernel mode
stack usually caused by nested interruption.
-config DEBUG_STACK_USAGE
- bool "Enable stack utilization instrumentation"
- depends on DEBUG_KERNEL
- help
- Enables the display of the minimum amount of free stack which each
- task has ever had available in the sysrq-T and sysrq-P debug output.
-
- This option will slow down process creation somewhat.
-
config SMTC_IDLE_HOOK_DEBUG
bool "Enable additional debug checks before going into CPU idle loop"
depends on DEBUG_KERNEL && MIPS_MT_SMTC
diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig
index b058282..4770741 100644
--- a/arch/mips/ath79/Kconfig
+++ b/arch/mips/ath79/Kconfig
@@ -26,12 +26,17 @@
endmenu
config SOC_AR71XX
+ select USB_ARCH_HAS_EHCI
+ select USB_ARCH_HAS_OHCI
def_bool n
config SOC_AR724X
+ select USB_ARCH_HAS_EHCI
+ select USB_ARCH_HAS_OHCI
def_bool n
config SOC_AR913X
+ select USB_ARCH_HAS_EHCI
def_bool n
config ATH79_DEV_AR913X_WMAC
diff --git a/arch/mips/kernel/vmlinux.lds.S b/arch/mips/kernel/vmlinux.lds.S
index 01af387..a81176f 100644
--- a/arch/mips/kernel/vmlinux.lds.S
+++ b/arch/mips/kernel/vmlinux.lds.S
@@ -118,7 +118,7 @@
EXIT_DATA
}
- PERCPU(1 << CONFIG_MIPS_L1_CACHE_SHIFT, PAGE_SIZE)
+ PERCPU_SECTION(1 << CONFIG_MIPS_L1_CACHE_SHIFT)
. = ALIGN(PAGE_SIZE);
__init_end = .;
/* freed after init ends here */
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index 279599e..1aadeb4 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -64,8 +64,6 @@
#endif /* CONFIG_MIPS_MT_SMTC */
-DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
-
/*
* We have up to 8 empty zeroed pages so we can map one of the right colour
* when needed. This is necessary only on R4000 / R4400 SC and MC versions
diff --git a/arch/mn10300/kernel/irq.c b/arch/mn10300/kernel/irq.c
index 86af0d7..2623d19 100644
--- a/arch/mn10300/kernel/irq.c
+++ b/arch/mn10300/kernel/irq.c
@@ -87,7 +87,7 @@
tmp2 = GxICR(irq);
irq_affinity_online[irq] =
- any_online_cpu(*d->affinity);
+ cpumask_any_and(d->affinity, cpu_online_mask);
CROSS_GxICR(irq, irq_affinity_online[irq]) =
(tmp & (GxICR_LEVEL | GxICR_ENABLE)) | GxICR_DETECT;
tmp = CROSS_GxICR(irq, irq_affinity_online[irq]);
@@ -124,7 +124,8 @@
} else {
tmp = GxICR(irq);
- irq_affinity_online[irq] = any_online_cpu(*d->affinity);
+ irq_affinity_online[irq] = cpumask_any_and(d->affinity,
+ cpu_online_mask);
CROSS_GxICR(irq, irq_affinity_online[irq]) = (tmp & GxICR_LEVEL) | GxICR_ENABLE | GxICR_DETECT;
tmp = CROSS_GxICR(irq, irq_affinity_online[irq]);
}
@@ -366,11 +367,11 @@
if (irqd_is_per_cpu(data))
continue;
- if (cpu_isset(self, data->affinity) &&
- !cpus_intersects(irq_affinity[irq], cpu_online_map)) {
+ if (cpumask_test_cpu(self, &data->affinity) &&
+ !cpumask_intersects(&irq_affinity[irq], cpu_online_mask)) {
int cpu_id;
- cpu_id = first_cpu(cpu_online_map);
- cpu_set(cpu_id, data->affinity);
+ cpu_id = cpumask_first(cpu_online_mask);
+ cpumask_set_cpu(cpu_id, &data->affinity);
}
/* We need to operate irq_affinity_online atomically. */
arch_local_cli_save(flags);
@@ -381,7 +382,8 @@
GxICR(irq) = x & GxICR_LEVEL;
tmp = GxICR(irq);
- new = any_online_cpu(data->affinity);
+ new = cpumask_any_and(&data->affinity,
+ cpu_online_mask);
irq_affinity_online[irq] = new;
CROSS_GxICR(irq, new) =
diff --git a/arch/mn10300/kernel/smp.c b/arch/mn10300/kernel/smp.c
index 83fb279..9242e9f 100644
--- a/arch/mn10300/kernel/smp.c
+++ b/arch/mn10300/kernel/smp.c
@@ -309,7 +309,7 @@
u16 tmp;
for (i = 0; i < NR_CPUS; i++) {
- if (cpu_isset(i, *cpumask)) {
+ if (cpumask_test_cpu(i, cpumask)) {
/* send IPI */
tmp = CROSS_GxICR(irq, i);
CROSS_GxICR(irq, i) =
@@ -342,8 +342,8 @@
{
cpumask_t cpumask;
- cpumask = cpu_online_map;
- cpu_clear(smp_processor_id(), cpumask);
+ cpumask_copy(&cpumask, cpu_online_mask);
+ cpumask_clear_cpu(smp_processor_id(), &cpumask);
send_IPI_mask(&cpumask, irq);
}
@@ -393,8 +393,8 @@
data.func = func;
data.info = info;
- data.started = cpu_online_map;
- cpu_clear(smp_processor_id(), data.started);
+ cpumask_copy(&data.started, cpu_online_mask);
+ cpumask_clear_cpu(smp_processor_id(), &data.started);
data.wait = wait;
if (wait)
data.finished = data.started;
@@ -410,14 +410,14 @@
if (CALL_FUNCTION_NMI_IPI_TIMEOUT > 0) {
for (cnt = 0;
cnt < CALL_FUNCTION_NMI_IPI_TIMEOUT &&
- !cpus_empty(data.started);
+ !cpumask_empty(&data.started);
cnt++)
mdelay(1);
if (wait && cnt < CALL_FUNCTION_NMI_IPI_TIMEOUT) {
for (cnt = 0;
cnt < CALL_FUNCTION_NMI_IPI_TIMEOUT &&
- !cpus_empty(data.finished);
+ !cpumask_empty(&data.finished);
cnt++)
mdelay(1);
}
@@ -428,10 +428,10 @@
} else {
/* If timeout value is zero, wait until cpumask has been
* cleared */
- while (!cpus_empty(data.started))
+ while (!cpumask_empty(&data.started))
barrier();
if (wait)
- while (!cpus_empty(data.finished))
+ while (!cpumask_empty(&data.finished))
barrier();
}
@@ -472,12 +472,12 @@
#endif /* CONFIG_GDBSTUB */
flags = arch_local_cli_save();
- cpu_clear(smp_processor_id(), cpu_online_map);
+ set_cpu_online(smp_processor_id(), false);
while (!stopflag)
cpu_relax();
- cpu_set(smp_processor_id(), cpu_online_map);
+ set_cpu_online(smp_processor_id(), true);
arch_local_irq_restore(flags);
}
@@ -529,12 +529,13 @@
* execute the function
*/
smp_mb();
- cpu_clear(smp_processor_id(), nmi_call_data->started);
+ cpumask_clear_cpu(smp_processor_id(), &nmi_call_data->started);
(*func)(info);
if (wait) {
smp_mb();
- cpu_clear(smp_processor_id(), nmi_call_data->finished);
+ cpumask_clear_cpu(smp_processor_id(),
+ &nmi_call_data->finished);
}
}
@@ -657,7 +658,7 @@
{
smp_cpu_init();
smp_callin();
- while (!cpu_isset(smp_processor_id(), smp_commenced_mask))
+ while (!cpumask_test_cpu(smp_processor_id(), &smp_commenced_mask))
cpu_relax();
local_flush_tlb();
@@ -780,13 +781,14 @@
if (send_status == 0) {
/* Allow AP to start initializing */
- cpu_set(cpu_id, cpu_callout_map);
+ cpumask_set_cpu(cpu_id, &cpu_callout_map);
/* Wait for setting cpu_callin_map */
timeout = 0;
do {
udelay(1000);
- callin_status = cpu_isset(cpu_id, cpu_callin_map);
+ callin_status = cpumask_test_cpu(cpu_id,
+ &cpu_callin_map);
} while (callin_status == 0 && timeout++ < 5000);
if (callin_status == 0)
@@ -796,9 +798,9 @@
}
if (send_status == GxICR_REQUEST || callin_status == 0) {
- cpu_clear(cpu_id, cpu_callout_map);
- cpu_clear(cpu_id, cpu_callin_map);
- cpu_clear(cpu_id, cpu_initialized);
+ cpumask_clear_cpu(cpu_id, &cpu_callout_map);
+ cpumask_clear_cpu(cpu_id, &cpu_callin_map);
+ cpumask_clear_cpu(cpu_id, &cpu_initialized);
cpucount--;
return 1;
}
@@ -833,7 +835,7 @@
cpu = smp_processor_id();
timeout = jiffies + (2 * HZ);
- if (cpu_isset(cpu, cpu_callin_map)) {
+ if (cpumask_test_cpu(cpu, &cpu_callin_map)) {
printk(KERN_ERR "CPU#%d already present.\n", cpu);
BUG();
}
@@ -841,7 +843,7 @@
/* Wait for AP startup 2s total */
while (time_before(jiffies, timeout)) {
- if (cpu_isset(cpu, cpu_callout_map))
+ if (cpumask_test_cpu(cpu, &cpu_callout_map))
break;
cpu_relax();
}
@@ -861,11 +863,11 @@
smp_store_cpu_info(cpu);
/* Allow the boot processor to continue */
- cpu_set(cpu, cpu_callin_map);
+ cpumask_set_cpu(cpu, &cpu_callin_map);
}
/**
- * smp_online - Set cpu_online_map
+ * smp_online - Set cpu_online_mask
*/
static void __init smp_online(void)
{
@@ -875,7 +877,7 @@
local_irq_enable();
- cpu_set(cpu, cpu_online_map);
+ set_cpu_online(cpu, true);
smp_wmb();
}
@@ -892,13 +894,13 @@
/*
* smp_prepare_boot_cpu - Set up stuff for the boot processor.
*
- * Set up the cpu_online_map, cpu_callout_map and cpu_callin_map of the boot
+ * Set up the cpu_online_mask, cpu_callout_map and cpu_callin_map of the boot
* processor (CPU 0).
*/
void __devinit smp_prepare_boot_cpu(void)
{
- cpu_set(0, cpu_callout_map);
- cpu_set(0, cpu_callin_map);
+ cpumask_set_cpu(0, &cpu_callout_map);
+ cpumask_set_cpu(0, &cpu_callin_map);
current_thread_info()->cpu = 0;
}
@@ -931,16 +933,16 @@
run_wakeup_cpu(cpu);
#endif /* CONFIG_HOTPLUG_CPU */
- cpu_set(cpu, smp_commenced_mask);
+ cpumask_set_cpu(cpu, &smp_commenced_mask);
/* Wait 5s total for a response */
for (timeout = 0 ; timeout < 5000 ; timeout++) {
- if (cpu_isset(cpu, cpu_online_map))
+ if (cpu_online(cpu))
break;
udelay(1000);
}
- BUG_ON(!cpu_isset(cpu, cpu_online_map));
+ BUG_ON(!cpu_online(cpu));
return 0;
}
@@ -986,7 +988,7 @@
return -EBUSY;
migrate_irqs();
- cpu_clear(cpu, current->active_mm->cpu_vm_mask);
+ cpumask_clear_cpu(cpu, &mm_cpumask(current->active_mm));
return 0;
}
@@ -1091,13 +1093,13 @@
do {
mn10300_local_dcache_inv_range(start, end);
barrier();
- } while (!cpus_empty(nmi_call_func_mask_data.started));
+ } while (!cpumask_empty(&nmi_call_func_mask_data.started));
if (wait) {
do {
mn10300_local_dcache_inv_range(start, end);
barrier();
- } while (!cpus_empty(nmi_call_func_mask_data.finished));
+ } while (!cpumask_empty(&nmi_call_func_mask_data.finished));
}
spin_unlock(&smp_nmi_call_lock);
@@ -1108,9 +1110,9 @@
{
unsigned int cpu = smp_processor_id();
- cpu_set(cpu, cpu_callin_map);
+ cpumask_set_cpu(cpu, &cpu_callin_map);
local_flush_tlb();
- cpu_set(cpu, cpu_online_map);
+ set_cpu_online(cpu, true);
smp_wmb();
}
@@ -1141,8 +1143,9 @@
static void run_sleep_cpu(unsigned int cpu)
{
unsigned long flags;
- cpumask_t cpumask = cpumask_of(cpu);
+ cpumask_t cpumask;
+ cpumask_copy(&cpumask, &cpumask_of(cpu));
flags = arch_local_cli_save();
hotplug_cpu_nmi_call_function(cpumask, prepare_sleep_cpu, NULL, 1);
hotplug_cpu_nmi_call_function(cpumask, sleep_cpu, NULL, 0);
diff --git a/arch/mn10300/kernel/vmlinux.lds.S b/arch/mn10300/kernel/vmlinux.lds.S
index 968bcd2..6f702a6 100644
--- a/arch/mn10300/kernel/vmlinux.lds.S
+++ b/arch/mn10300/kernel/vmlinux.lds.S
@@ -70,7 +70,7 @@
.exit.text : { EXIT_TEXT; }
.exit.data : { EXIT_DATA; }
- PERCPU(32, PAGE_SIZE)
+ PERCPU_SECTION(32)
. = ALIGN(PAGE_SIZE);
__init_end = .;
/* freed after init ends here */
diff --git a/arch/mn10300/mm/cache-smp.c b/arch/mn10300/mm/cache-smp.c
index 4a6e9a4..2d23b9e 100644
--- a/arch/mn10300/mm/cache-smp.c
+++ b/arch/mn10300/mm/cache-smp.c
@@ -74,7 +74,7 @@
break;
}
- cpu_clear(smp_processor_id(), smp_cache_ipi_map);
+ cpumask_clear_cpu(smp_processor_id(), &smp_cache_ipi_map);
}
/**
@@ -94,12 +94,12 @@
smp_cache_mask = opr_mask;
smp_cache_start = start;
smp_cache_end = end;
- smp_cache_ipi_map = cpu_online_map;
- cpu_clear(smp_processor_id(), smp_cache_ipi_map);
+ cpumask_copy(&smp_cache_ipi_map, cpu_online_mask);
+ cpumask_clear_cpu(smp_processor_id(), &smp_cache_ipi_map);
send_IPI_allbutself(FLUSH_CACHE_IPI);
- while (!cpus_empty(smp_cache_ipi_map))
+ while (!cpumask_empty(&smp_cache_ipi_map))
/* nothing. lockup detection does not belong here */
mb();
}
diff --git a/arch/mn10300/mm/init.c b/arch/mn10300/mm/init.c
index 48907cc..1380182 100644
--- a/arch/mn10300/mm/init.c
+++ b/arch/mn10300/mm/init.c
@@ -37,8 +37,6 @@
#include <asm/tlb.h>
#include <asm/sections.h>
-DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
-
unsigned long highstart_pfn, highend_pfn;
#ifdef CONFIG_MN10300_HAS_ATOMIC_OPS_UNIT
diff --git a/arch/mn10300/mm/tlb-smp.c b/arch/mn10300/mm/tlb-smp.c
index 0b6a5ad..9a77749 100644
--- a/arch/mn10300/mm/tlb-smp.c
+++ b/arch/mn10300/mm/tlb-smp.c
@@ -64,7 +64,7 @@
cpu_id = get_cpu();
- if (!cpu_isset(cpu_id, flush_cpumask))
+ if (!cpumask_test_cpu(cpu_id, &flush_cpumask))
/* This was a BUG() but until someone can quote me the line
* from the intel manual that guarantees an IPI to multiple
* CPUs is retried _only_ on the erroring CPUs its staying as a
@@ -80,7 +80,7 @@
local_flush_tlb_page(flush_mm, flush_va);
smp_mb__before_clear_bit();
- cpu_clear(cpu_id, flush_cpumask);
+ cpumask_clear_cpu(cpu_id, &flush_cpumask);
smp_mb__after_clear_bit();
out:
put_cpu();
@@ -103,11 +103,11 @@
* - we do not send IPIs to as-yet unbooted CPUs.
*/
BUG_ON(!mm);
- BUG_ON(cpus_empty(cpumask));
- BUG_ON(cpu_isset(smp_processor_id(), cpumask));
+ BUG_ON(cpumask_empty(&cpumask));
+ BUG_ON(cpumask_test_cpu(smp_processor_id(), &cpumask));
- cpus_and(tmp, cpumask, cpu_online_map);
- BUG_ON(!cpus_equal(cpumask, tmp));
+ cpumask_and(&tmp, &cpumask, cpu_online_mask);
+ BUG_ON(!cpumask_equal(&cpumask, &tmp));
/* I'm not happy about this global shared spinlock in the MM hot path,
* but we'll see how contended it is.
@@ -128,7 +128,7 @@
/* FIXME: if NR_CPUS>=3, change send_IPI_mask */
smp_call_function(smp_flush_tlb, NULL, 1);
- while (!cpus_empty(flush_cpumask))
+ while (!cpumask_empty(&flush_cpumask))
/* Lockup detection does not belong here */
smp_mb();
@@ -146,11 +146,11 @@
cpumask_t cpu_mask;
preempt_disable();
- cpu_mask = mm->cpu_vm_mask;
- cpu_clear(smp_processor_id(), cpu_mask);
+ cpumask_copy(&cpu_mask, mm_cpumask(mm));
+ cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
local_flush_tlb();
- if (!cpus_empty(cpu_mask))
+ if (!cpumask_empty(&cpu_mask))
flush_tlb_others(cpu_mask, mm, FLUSH_ALL);
preempt_enable();
@@ -165,11 +165,11 @@
cpumask_t cpu_mask;
preempt_disable();
- cpu_mask = mm->cpu_vm_mask;
- cpu_clear(smp_processor_id(), cpu_mask);
+ cpumask_copy(&cpu_mask, mm_cpumask(mm));
+ cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
local_flush_tlb();
- if (!cpus_empty(cpu_mask))
+ if (!cpumask_empty(&cpu_mask))
flush_tlb_others(cpu_mask, mm, FLUSH_ALL);
preempt_enable();
@@ -186,11 +186,11 @@
cpumask_t cpu_mask;
preempt_disable();
- cpu_mask = mm->cpu_vm_mask;
- cpu_clear(smp_processor_id(), cpu_mask);
+ cpumask_copy(&cpu_mask, mm_cpumask(mm));
+ cpumask_clear_cpu(smp_processor_id(), &cpu_mask);
local_flush_tlb_page(mm, va);
- if (!cpus_empty(cpu_mask))
+ if (!cpumask_empty(&cpu_mask))
flush_tlb_others(cpu_mask, mm, va);
preempt_enable();
diff --git a/arch/parisc/include/asm/smp.h b/arch/parisc/include/asm/smp.h
index 2e73623..e8f8037 100644
--- a/arch/parisc/include/asm/smp.h
+++ b/arch/parisc/include/asm/smp.h
@@ -33,15 +33,6 @@
#endif /* !ASSEMBLY */
-/*
- * This magic constant controls our willingness to transfer
- * a process across CPUs. Such a transfer incurs cache and tlb
- * misses. The current value is inherited from i386. Still needs
- * to be tuned for parisc.
- */
-
-#define PROC_CHANGE_PENALTY 15 /* Schedule penalty */
-
#define raw_smp_processor_id() (current_thread_info()->cpu)
#else /* CONFIG_SMP */
diff --git a/arch/parisc/kernel/vmlinux.lds.S b/arch/parisc/kernel/vmlinux.lds.S
index e1a5584..fa6f2b8 100644
--- a/arch/parisc/kernel/vmlinux.lds.S
+++ b/arch/parisc/kernel/vmlinux.lds.S
@@ -149,7 +149,7 @@
EXIT_DATA
}
- PERCPU(L1_CACHE_BYTES, PAGE_SIZE)
+ PERCPU_SECTION(L1_CACHE_BYTES)
. = ALIGN(PAGE_SIZE);
__init_end = .;
/* freed after init ends here */
diff --git a/arch/parisc/mm/init.c b/arch/parisc/mm/init.c
index 5fa1e27..82f364e 100644
--- a/arch/parisc/mm/init.c
+++ b/arch/parisc/mm/init.c
@@ -31,8 +31,6 @@
#include <asm/mmzone.h>
#include <asm/sections.h>
-DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
-
extern int data_start;
#ifdef CONFIG_DISCONTIGMEM
@@ -686,7 +684,7 @@
int shared = 0, cached = 0;
printk(KERN_INFO "Mem-info:\n");
- show_free_areas();
+ show_free_areas(filter);
#ifndef CONFIG_DISCONTIGMEM
i = max_mapnr;
while (i-- > 0) {
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index a3128ca..423145a6 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -140,6 +140,7 @@
select IRQ_PER_CPU
select GENERIC_IRQ_SHOW
select GENERIC_IRQ_SHOW_LEVEL
+ select HAVE_RCU_TABLE_FREE if SMP
config EARLY_PRINTK
bool
diff --git a/arch/powerpc/Kconfig.debug b/arch/powerpc/Kconfig.debug
index a597dd7..e72dcf6 100644
--- a/arch/powerpc/Kconfig.debug
+++ b/arch/powerpc/Kconfig.debug
@@ -35,27 +35,6 @@
This option will cause messages to be printed if free stack space
drops below a certain limit.
-config DEBUG_STACK_USAGE
- bool "Stack utilization instrumentation"
- depends on DEBUG_KERNEL
- help
- Enables the display of the minimum amount of free stack which each
- task has ever had available in the sysrq-T and sysrq-P debug output.
-
- This option will slow down process creation somewhat.
-
-config DEBUG_PER_CPU_MAPS
- bool "Debug access to per_cpu maps"
- depends on DEBUG_KERNEL
- depends on SMP
- default n
- ---help---
- Say Y to verify that the per_cpu map being accessed has
- been setup. Adds a fair amount of code to kernel memory
- and decreases performance.
-
- Say N if unsure.
-
config HCALL_STATS
bool "Hypervisor call instrumentation"
depends on PPC_PSERIES && DEBUG_FS && TRACEPOINTS
diff --git a/arch/powerpc/boot/dts/mpc8313erdb.dts b/arch/powerpc/boot/dts/mpc8313erdb.dts
index 761faa7..ac1eb32 100644
--- a/arch/powerpc/boot/dts/mpc8313erdb.dts
+++ b/arch/powerpc/boot/dts/mpc8313erdb.dts
@@ -176,6 +176,19 @@
sleep = <&pmc 0x00300000>;
};
+ ptp_clock@24E00 {
+ compatible = "fsl,etsec-ptp";
+ reg = <0x24E00 0xB0>;
+ interrupts = <12 0x8 13 0x8>;
+ interrupt-parent = < &ipic >;
+ fsl,tclk-period = <10>;
+ fsl,tmr-prsc = <100>;
+ fsl,tmr-add = <0x999999A4>;
+ fsl,tmr-fiper1 = <0x3B9AC9F6>;
+ fsl,tmr-fiper2 = <0x00018696>;
+ fsl,max-adj = <659999998>;
+ };
+
enet0: ethernet@24000 {
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/powerpc/boot/dts/mpc8572ds.dts b/arch/powerpc/boot/dts/mpc8572ds.dts
index cafc128..f6c04d2 100644
--- a/arch/powerpc/boot/dts/mpc8572ds.dts
+++ b/arch/powerpc/boot/dts/mpc8572ds.dts
@@ -324,6 +324,19 @@
};
};
+ ptp_clock@24E00 {
+ compatible = "fsl,etsec-ptp";
+ reg = <0x24E00 0xB0>;
+ interrupts = <68 2 69 2 70 2 71 2>;
+ interrupt-parent = < &mpic >;
+ fsl,tclk-period = <5>;
+ fsl,tmr-prsc = <200>;
+ fsl,tmr-add = <0xAAAAAAAB>;
+ fsl,tmr-fiper1 = <0x3B9AC9FB>;
+ fsl,tmr-fiper2 = <0x3B9AC9FB>;
+ fsl,max-adj = <499999999>;
+ };
+
enet0: ethernet@24000 {
#address-cells = <1>;
#size-cells = <1>;
diff --git a/arch/powerpc/boot/dts/p2020ds.dts b/arch/powerpc/boot/dts/p2020ds.dts
index 2bcf368..dae4031 100644
--- a/arch/powerpc/boot/dts/p2020ds.dts
+++ b/arch/powerpc/boot/dts/p2020ds.dts
@@ -178,6 +178,19 @@
};
+ ptp_clock@24E00 {
+ compatible = "fsl,etsec-ptp";
+ reg = <0x24E00 0xB0>;
+ interrupts = <68 2 69 2 70 2>;
+ interrupt-parent = < &mpic >;
+ fsl,tclk-period = <5>;
+ fsl,tmr-prsc = <200>;
+ fsl,tmr-add = <0xCCCCCCCD>;
+ fsl,tmr-fiper1 = <0x3B9AC9FB>;
+ fsl,tmr-fiper2 = <0x0001869B>;
+ fsl,max-adj = <249999999>;
+ };
+
enet0: ethernet@24000 {
tbi-handle = <&tbi0>;
phy-handle = <&phy0>;
diff --git a/arch/powerpc/boot/dts/p2020rdb.dts b/arch/powerpc/boot/dts/p2020rdb.dts
index 3782a58..1d7a05f 100644
--- a/arch/powerpc/boot/dts/p2020rdb.dts
+++ b/arch/powerpc/boot/dts/p2020rdb.dts
@@ -224,6 +224,19 @@
status = "disabled";
};
+ ptp_clock@24E00 {
+ compatible = "fsl,etsec-ptp";
+ reg = <0x24E00 0xB0>;
+ interrupts = <68 2 69 2 70 2>;
+ interrupt-parent = < &mpic >;
+ fsl,tclk-period = <5>;
+ fsl,tmr-prsc = <200>;
+ fsl,tmr-add = <0xCCCCCCCD>;
+ fsl,tmr-fiper1 = <0x3B9AC9FB>;
+ fsl,tmr-fiper2 = <0x0001869B>;
+ fsl,max-adj = <249999999>;
+ };
+
enet0: ethernet@24000 {
fixed-link = <1 1 1000 0 0>;
phy-connection-type = "rgmii-id";
diff --git a/arch/powerpc/include/asm/pgalloc.h b/arch/powerpc/include/asm/pgalloc.h
index abe8532..bf301ac 100644
--- a/arch/powerpc/include/asm/pgalloc.h
+++ b/arch/powerpc/include/asm/pgalloc.h
@@ -31,14 +31,29 @@
#endif
#ifdef CONFIG_SMP
-extern void pgtable_free_tlb(struct mmu_gather *tlb, void *table, unsigned shift);
-extern void pte_free_finish(void);
+struct mmu_gather;
+extern void tlb_remove_table(struct mmu_gather *, void *);
+
+static inline void pgtable_free_tlb(struct mmu_gather *tlb, void *table, int shift)
+{
+ unsigned long pgf = (unsigned long)table;
+ BUG_ON(shift > MAX_PGTABLE_INDEX_SIZE);
+ pgf |= shift;
+ tlb_remove_table(tlb, (void *)pgf);
+}
+
+static inline void __tlb_remove_table(void *_table)
+{
+ void *table = (void *)((unsigned long)_table & ~MAX_PGTABLE_INDEX_SIZE);
+ unsigned shift = (unsigned long)_table & MAX_PGTABLE_INDEX_SIZE;
+
+ pgtable_free(table, shift);
+}
#else /* CONFIG_SMP */
static inline void pgtable_free_tlb(struct mmu_gather *tlb, void *table, unsigned shift)
{
pgtable_free(table, shift);
}
-static inline void pte_free_finish(void) { }
#endif /* !CONFIG_SMP */
static inline void __pte_free_tlb(struct mmu_gather *tlb, struct page *ptepage,
diff --git a/arch/powerpc/include/asm/thread_info.h b/arch/powerpc/include/asm/thread_info.h
index d8529ef..37c353e 100644
--- a/arch/powerpc/include/asm/thread_info.h
+++ b/arch/powerpc/include/asm/thread_info.h
@@ -139,10 +139,12 @@
#define TLF_NAPPING 0 /* idle thread enabled NAP mode */
#define TLF_SLEEPING 1 /* suspend code enabled SLEEP mode */
#define TLF_RESTORE_SIGMASK 2 /* Restore signal mask in do_signal */
+#define TLF_LAZY_MMU 3 /* tlb_batch is active */
#define _TLF_NAPPING (1 << TLF_NAPPING)
#define _TLF_SLEEPING (1 << TLF_SLEEPING)
#define _TLF_RESTORE_SIGMASK (1 << TLF_RESTORE_SIGMASK)
+#define _TLF_LAZY_MMU (1 << TLF_LAZY_MMU)
#ifndef __ASSEMBLY__
#define HAVE_SET_RESTORE_SIGMASK 1
diff --git a/arch/powerpc/kernel/process.c b/arch/powerpc/kernel/process.c
index 095043d..91e52df 100644
--- a/arch/powerpc/kernel/process.c
+++ b/arch/powerpc/kernel/process.c
@@ -395,6 +395,9 @@
struct thread_struct *new_thread, *old_thread;
unsigned long flags;
struct task_struct *last;
+#ifdef CONFIG_PPC_BOOK3S_64
+ struct ppc64_tlb_batch *batch;
+#endif
#ifdef CONFIG_SMP
/* avoid complexity of lazy save/restore of fpu
@@ -513,7 +516,17 @@
old_thread->accum_tb += (current_tb - start_tb);
new_thread->start_tb = current_tb;
}
-#endif
+#endif /* CONFIG_PPC64 */
+
+#ifdef CONFIG_PPC_BOOK3S_64
+ batch = &__get_cpu_var(ppc64_tlb_batch);
+ if (batch->active) {
+ current_thread_info()->local_flags |= _TLF_LAZY_MMU;
+ if (batch->index)
+ __flush_tlb_pending(batch);
+ batch->active = 0;
+ }
+#endif /* CONFIG_PPC_BOOK3S_64 */
local_irq_save(flags);
@@ -528,6 +541,14 @@
hard_irq_disable();
last = _switch(old_thread, new_thread);
+#ifdef CONFIG_PPC_BOOK3S_64
+ if (current_thread_info()->local_flags & _TLF_LAZY_MMU) {
+ current_thread_info()->local_flags &= ~_TLF_LAZY_MMU;
+ batch = &__get_cpu_var(ppc64_tlb_batch);
+ batch->active = 1;
+ }
+#endif /* CONFIG_PPC_BOOK3S_64 */
+
local_irq_restore(flags);
return last;
diff --git a/arch/powerpc/kernel/vmlinux.lds.S b/arch/powerpc/kernel/vmlinux.lds.S
index b9150f0..920276c 100644
--- a/arch/powerpc/kernel/vmlinux.lds.S
+++ b/arch/powerpc/kernel/vmlinux.lds.S
@@ -160,7 +160,7 @@
INIT_RAM_FS
}
- PERCPU(L1_CACHE_BYTES, PAGE_SIZE)
+ PERCPU_SECTION(L1_CACHE_BYTES)
. = ALIGN(8);
.machine.desc : AT(ADDR(.machine.desc) - LOAD_OFFSET) {
diff --git a/arch/powerpc/mm/pgtable.c b/arch/powerpc/mm/pgtable.c
index 6a3997f..af40c87 100644
--- a/arch/powerpc/mm/pgtable.c
+++ b/arch/powerpc/mm/pgtable.c
@@ -33,110 +33,6 @@
#include "mmu_decl.h"
-DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
-
-#ifdef CONFIG_SMP
-
-/*
- * Handle batching of page table freeing on SMP. Page tables are
- * queued up and send to be freed later by RCU in order to avoid
- * freeing a page table page that is being walked without locks
- */
-
-static DEFINE_PER_CPU(struct pte_freelist_batch *, pte_freelist_cur);
-static unsigned long pte_freelist_forced_free;
-
-struct pte_freelist_batch
-{
- struct rcu_head rcu;
- unsigned int index;
- unsigned long tables[0];
-};
-
-#define PTE_FREELIST_SIZE \
- ((PAGE_SIZE - sizeof(struct pte_freelist_batch)) \
- / sizeof(unsigned long))
-
-static void pte_free_smp_sync(void *arg)
-{
- /* Do nothing, just ensure we sync with all CPUs */
-}
-
-/* This is only called when we are critically out of memory
- * (and fail to get a page in pte_free_tlb).
- */
-static void pgtable_free_now(void *table, unsigned shift)
-{
- pte_freelist_forced_free++;
-
- smp_call_function(pte_free_smp_sync, NULL, 1);
-
- pgtable_free(table, shift);
-}
-
-static void pte_free_rcu_callback(struct rcu_head *head)
-{
- struct pte_freelist_batch *batch =
- container_of(head, struct pte_freelist_batch, rcu);
- unsigned int i;
-
- for (i = 0; i < batch->index; i++) {
- void *table = (void *)(batch->tables[i] & ~MAX_PGTABLE_INDEX_SIZE);
- unsigned shift = batch->tables[i] & MAX_PGTABLE_INDEX_SIZE;
-
- pgtable_free(table, shift);
- }
-
- free_page((unsigned long)batch);
-}
-
-static void pte_free_submit(struct pte_freelist_batch *batch)
-{
- call_rcu_sched(&batch->rcu, pte_free_rcu_callback);
-}
-
-void pgtable_free_tlb(struct mmu_gather *tlb, void *table, unsigned shift)
-{
- /* This is safe since tlb_gather_mmu has disabled preemption */
- struct pte_freelist_batch **batchp = &__get_cpu_var(pte_freelist_cur);
- unsigned long pgf;
-
- if (atomic_read(&tlb->mm->mm_users) < 2 ||
- cpumask_equal(mm_cpumask(tlb->mm), cpumask_of(smp_processor_id()))){
- pgtable_free(table, shift);
- return;
- }
-
- if (*batchp == NULL) {
- *batchp = (struct pte_freelist_batch *)__get_free_page(GFP_ATOMIC);
- if (*batchp == NULL) {
- pgtable_free_now(table, shift);
- return;
- }
- (*batchp)->index = 0;
- }
- BUG_ON(shift > MAX_PGTABLE_INDEX_SIZE);
- pgf = (unsigned long)table | shift;
- (*batchp)->tables[(*batchp)->index++] = pgf;
- if ((*batchp)->index == PTE_FREELIST_SIZE) {
- pte_free_submit(*batchp);
- *batchp = NULL;
- }
-}
-
-void pte_free_finish(void)
-{
- /* This is safe since tlb_gather_mmu has disabled preemption */
- struct pte_freelist_batch **batchp = &__get_cpu_var(pte_freelist_cur);
-
- if (*batchp == NULL)
- return;
- pte_free_submit(*batchp);
- *batchp = NULL;
-}
-
-#endif /* CONFIG_SMP */
-
static inline int is_exec_fault(void)
{
return current->thread.regs && TRAP(current->thread.regs) == 0x400;
diff --git a/arch/powerpc/mm/tlb_hash32.c b/arch/powerpc/mm/tlb_hash32.c
index 690566b..27b863c 100644
--- a/arch/powerpc/mm/tlb_hash32.c
+++ b/arch/powerpc/mm/tlb_hash32.c
@@ -71,9 +71,6 @@
*/
_tlbia();
}
-
- /* Push out batch of freed page tables */
- pte_free_finish();
}
/*
diff --git a/arch/powerpc/mm/tlb_hash64.c b/arch/powerpc/mm/tlb_hash64.c
index c14d09f..31f1820 100644
--- a/arch/powerpc/mm/tlb_hash64.c
+++ b/arch/powerpc/mm/tlb_hash64.c
@@ -155,7 +155,7 @@
void tlb_flush(struct mmu_gather *tlb)
{
- struct ppc64_tlb_batch *tlbbatch = &__get_cpu_var(ppc64_tlb_batch);
+ struct ppc64_tlb_batch *tlbbatch = &get_cpu_var(ppc64_tlb_batch);
/* If there's a TLB batch pending, then we must flush it because the
* pages are going to be freed and we really don't want to have a CPU
@@ -164,8 +164,7 @@
if (tlbbatch->index)
__flush_tlb_pending(tlbbatch);
- /* Push out batch of freed page tables */
- pte_free_finish();
+ put_cpu_var(ppc64_tlb_batch);
}
/**
diff --git a/arch/powerpc/mm/tlb_nohash.c b/arch/powerpc/mm/tlb_nohash.c
index 2a030d8..0bdad3a 100644
--- a/arch/powerpc/mm/tlb_nohash.c
+++ b/arch/powerpc/mm/tlb_nohash.c
@@ -299,9 +299,6 @@
void tlb_flush(struct mmu_gather *tlb)
{
flush_tlb_mm(tlb->mm);
-
- /* Push out batch of freed page tables */
- pte_free_finish();
}
/*
diff --git a/arch/s390/Kconfig b/arch/s390/Kconfig
index 4a7f140..ff2d237 100644
--- a/arch/s390/Kconfig
+++ b/arch/s390/Kconfig
@@ -230,17 +230,6 @@
config AUDIT_ARCH
def_bool y
-config S390_EXEC_PROTECT
- def_bool y
- prompt "Data execute protection"
- help
- This option allows to enable a buffer overflow protection for user
- space programs and it also selects the addressing mode option above.
- The kernel parameter noexec=on will enable this feature and also
- switch the addressing modes, default is disabled. Enabling this (via
- kernel parameter) on machines earlier than IBM System z9 this will
- reduce system performance.
-
comment "Code generation options"
choice
diff --git a/arch/s390/appldata/appldata_base.c b/arch/s390/appldata/appldata_base.c
index 5c91995..24bff4f 100644
--- a/arch/s390/appldata/appldata_base.c
+++ b/arch/s390/appldata/appldata_base.c
@@ -130,9 +130,7 @@
{
struct list_head *lh;
struct appldata_ops *ops;
- int i;
- i = 0;
get_online_cpus();
mutex_lock(&appldata_ops_mutex);
list_for_each(lh, &appldata_ops_list) {
diff --git a/arch/s390/include/asm/cmpxchg.h b/arch/s390/include/asm/cmpxchg.h
index 7488e52..81d7908 100644
--- a/arch/s390/include/asm/cmpxchg.h
+++ b/arch/s390/include/asm/cmpxchg.h
@@ -167,7 +167,6 @@
#ifdef CONFIG_64BIT
#define cmpxchg64(ptr, o, n) \
({ \
- BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
cmpxchg((ptr), (o), (n)); \
})
#else /* CONFIG_64BIT */
diff --git a/arch/s390/include/asm/elf.h b/arch/s390/include/asm/elf.h
index 10c029c..64b61bf 100644
--- a/arch/s390/include/asm/elf.h
+++ b/arch/s390/include/asm/elf.h
@@ -196,18 +196,6 @@
} while (0)
#endif /* __s390x__ */
-/*
- * An executable for which elf_read_implies_exec() returns TRUE will
- * have the READ_IMPLIES_EXEC personality flag set automatically.
- */
-#define elf_read_implies_exec(ex, executable_stack) \
-({ \
- if (current->mm->context.noexec && \
- executable_stack != EXSTACK_DISABLE_X) \
- disable_noexec(current->mm, current); \
- current->mm->context.noexec == 0; \
-})
-
#define STACK_RND_MASK 0x7ffUL
#define ARCH_DLINFO \
diff --git a/arch/s390/include/asm/hugetlb.h b/arch/s390/include/asm/hugetlb.h
index b56403c..799ed0f 100644
--- a/arch/s390/include/asm/hugetlb.h
+++ b/arch/s390/include/asm/hugetlb.h
@@ -111,21 +111,10 @@
{
pmd_t *pmdp = (pmd_t *) ptep;
- if (!MACHINE_HAS_IDTE) {
- __pmd_csp(pmdp);
- if (mm->context.noexec) {
- pmdp = get_shadow_table(pmdp);
- __pmd_csp(pmdp);
- }
- return;
- }
-
- __pmd_idte(address, pmdp);
- if (mm->context.noexec) {
- pmdp = get_shadow_table(pmdp);
+ if (MACHINE_HAS_IDTE)
__pmd_idte(address, pmdp);
- }
- return;
+ else
+ __pmd_csp(pmdp);
}
#define huge_ptep_set_access_flags(__vma, __addr, __ptep, __entry, __dirty) \
diff --git a/arch/s390/include/asm/irq.h b/arch/s390/include/asm/irq.h
index db14a31..1544b90 100644
--- a/arch/s390/include/asm/irq.h
+++ b/arch/s390/include/asm/irq.h
@@ -15,6 +15,7 @@
EXTINT_VRT,
EXTINT_SCP,
EXTINT_IUC,
+ EXTINT_CPM,
IOINT_QAI,
IOINT_QDI,
IOINT_DAS,
diff --git a/arch/s390/include/asm/lowcore.h b/arch/s390/include/asm/lowcore.h
index 65e172f..228cf0b 100644
--- a/arch/s390/include/asm/lowcore.h
+++ b/arch/s390/include/asm/lowcore.h
@@ -124,7 +124,7 @@
/* Address space pointer. */
__u32 kernel_asce; /* 0x02ac */
__u32 user_asce; /* 0x02b0 */
- __u32 user_exec_asce; /* 0x02b4 */
+ __u32 current_pid; /* 0x02b4 */
/* SMP info area */
__u32 cpu_nr; /* 0x02b8 */
@@ -255,7 +255,7 @@
/* Address space pointer. */
__u64 kernel_asce; /* 0x0310 */
__u64 user_asce; /* 0x0318 */
- __u64 user_exec_asce; /* 0x0320 */
+ __u64 current_pid; /* 0x0320 */
/* SMP info area */
__u32 cpu_nr; /* 0x0328 */
diff --git a/arch/s390/include/asm/mmu.h b/arch/s390/include/asm/mmu.h
index 78522cde..82d0847 100644
--- a/arch/s390/include/asm/mmu.h
+++ b/arch/s390/include/asm/mmu.h
@@ -5,19 +5,18 @@
atomic_t attach_count;
unsigned int flush_mm;
spinlock_t list_lock;
- struct list_head crst_list;
struct list_head pgtable_list;
unsigned long asce_bits;
unsigned long asce_limit;
unsigned long vdso_base;
- int noexec;
- int has_pgste; /* The mmu context has extended page tables */
- int alloc_pgste; /* cloned contexts will have extended page tables */
+ /* Cloned contexts will be created with extended page tables. */
+ unsigned int alloc_pgste:1;
+ /* The mmu context has extended page tables. */
+ unsigned int has_pgste:1;
} mm_context_t;
#define INIT_MM_CONTEXT(name) \
.context.list_lock = __SPIN_LOCK_UNLOCKED(name.context.list_lock), \
- .context.crst_list = LIST_HEAD_INIT(name.context.crst_list), \
.context.pgtable_list = LIST_HEAD_INIT(name.context.pgtable_list),
#endif
diff --git a/arch/s390/include/asm/mmu_context.h b/arch/s390/include/asm/mmu_context.h
index 8c277ca..5682f16 100644
--- a/arch/s390/include/asm/mmu_context.h
+++ b/arch/s390/include/asm/mmu_context.h
@@ -35,11 +35,9 @@
* and if has_pgste is set, it will create extended page
* tables.
*/
- mm->context.noexec = 0;
mm->context.has_pgste = 1;
mm->context.alloc_pgste = 1;
} else {
- mm->context.noexec = (user_mode == SECONDARY_SPACE_MODE);
mm->context.has_pgste = 0;
mm->context.alloc_pgste = 0;
}
@@ -63,10 +61,8 @@
S390_lowcore.user_asce = mm->context.asce_bits | __pa(pgd);
if (user_mode != HOME_SPACE_MODE) {
/* Load primary space page table origin. */
- pgd = mm->context.noexec ? get_shadow_table(pgd) : pgd;
- S390_lowcore.user_exec_asce = mm->context.asce_bits | __pa(pgd);
asm volatile(LCTL_OPCODE" 1,1,%0\n"
- : : "m" (S390_lowcore.user_exec_asce) );
+ : : "m" (S390_lowcore.user_asce) );
} else
/* Load home space page table origin. */
asm volatile(LCTL_OPCODE" 13,13,%0"
diff --git a/arch/s390/include/asm/page.h b/arch/s390/include/asm/page.h
index 3c987e9..accb372 100644
--- a/arch/s390/include/asm/page.h
+++ b/arch/s390/include/asm/page.h
@@ -90,6 +90,7 @@
*/
typedef struct { unsigned long pgprot; } pgprot_t;
+typedef struct { unsigned long pgste; } pgste_t;
typedef struct { unsigned long pte; } pte_t;
typedef struct { unsigned long pmd; } pmd_t;
typedef struct { unsigned long pud; } pud_t;
@@ -97,18 +98,21 @@
typedef pte_t *pgtable_t;
#define pgprot_val(x) ((x).pgprot)
+#define pgste_val(x) ((x).pgste)
#define pte_val(x) ((x).pte)
#define pmd_val(x) ((x).pmd)
#define pud_val(x) ((x).pud)
#define pgd_val(x) ((x).pgd)
+#define __pgste(x) ((pgste_t) { (x) } )
#define __pte(x) ((pte_t) { (x) } )
#define __pmd(x) ((pmd_t) { (x) } )
+#define __pud(x) ((pud_t) { (x) } )
#define __pgd(x) ((pgd_t) { (x) } )
#define __pgprot(x) ((pgprot_t) { (x) } )
-static inline void
-page_set_storage_key(unsigned long addr, unsigned int skey, int mapped)
+static inline void page_set_storage_key(unsigned long addr,
+ unsigned char skey, int mapped)
{
if (!mapped)
asm volatile(".insn rrf,0xb22b0000,%0,%1,8,0"
@@ -117,15 +121,59 @@
asm volatile("sske %0,%1" : : "d" (skey), "a" (addr));
}
-static inline unsigned int
-page_get_storage_key(unsigned long addr)
+static inline unsigned char page_get_storage_key(unsigned long addr)
{
- unsigned int skey;
+ unsigned char skey;
- asm volatile("iske %0,%1" : "=d" (skey) : "a" (addr), "0" (0));
+ asm volatile("iske %0,%1" : "=d" (skey) : "a" (addr));
return skey;
}
+static inline int page_reset_referenced(unsigned long addr)
+{
+ unsigned int ipm;
+
+ asm volatile(
+ " rrbe 0,%1\n"
+ " ipm %0\n"
+ : "=d" (ipm) : "a" (addr) : "cc");
+ return !!(ipm & 0x20000000);
+}
+
+/* Bits int the storage key */
+#define _PAGE_CHANGED 0x02 /* HW changed bit */
+#define _PAGE_REFERENCED 0x04 /* HW referenced bit */
+#define _PAGE_FP_BIT 0x08 /* HW fetch protection bit */
+#define _PAGE_ACC_BITS 0xf0 /* HW access control bits */
+
+/*
+ * Test and clear dirty bit in storage key.
+ * We can't clear the changed bit atomically. This is a potential
+ * race against modification of the referenced bit. This function
+ * should therefore only be called if it is not mapped in any
+ * address space.
+ */
+#define __HAVE_ARCH_PAGE_TEST_AND_CLEAR_DIRTY
+static inline int page_test_and_clear_dirty(unsigned long pfn, int mapped)
+{
+ unsigned char skey;
+
+ skey = page_get_storage_key(pfn << PAGE_SHIFT);
+ if (!(skey & _PAGE_CHANGED))
+ return 0;
+ page_set_storage_key(pfn << PAGE_SHIFT, skey & ~_PAGE_CHANGED, mapped);
+ return 1;
+}
+
+/*
+ * Test and clear referenced bit in storage key.
+ */
+#define __HAVE_ARCH_PAGE_TEST_AND_CLEAR_YOUNG
+static inline int page_test_and_clear_young(unsigned long pfn)
+{
+ return page_reset_referenced(pfn << PAGE_SHIFT);
+}
+
struct page;
void arch_free_page(struct page *page, int order);
void arch_alloc_page(struct page *page, int order);
diff --git a/arch/s390/include/asm/percpu.h b/arch/s390/include/asm/percpu.h
index f7ad871..5325c89 100644
--- a/arch/s390/include/asm/percpu.h
+++ b/arch/s390/include/asm/percpu.h
@@ -1,6 +1,9 @@
#ifndef __ARCH_S390_PERCPU__
#define __ARCH_S390_PERCPU__
+#include <linux/preempt.h>
+#include <asm/cmpxchg.h>
+
/*
* s390 uses its own implementation for per cpu data, the offset of
* the cpu local data area is cached in the cpu's lowcore memory.
@@ -16,6 +19,71 @@
#define ARCH_NEEDS_WEAK_PER_CPU
#endif
+#define arch_irqsafe_cpu_to_op(pcp, val, op) \
+do { \
+ typedef typeof(pcp) pcp_op_T__; \
+ pcp_op_T__ old__, new__, prev__; \
+ pcp_op_T__ *ptr__; \
+ preempt_disable(); \
+ ptr__ = __this_cpu_ptr(&(pcp)); \
+ prev__ = *ptr__; \
+ do { \
+ old__ = prev__; \
+ new__ = old__ op (val); \
+ switch (sizeof(*ptr__)) { \
+ case 8: \
+ prev__ = cmpxchg64(ptr__, old__, new__); \
+ break; \
+ default: \
+ prev__ = cmpxchg(ptr__, old__, new__); \
+ } \
+ } while (prev__ != old__); \
+ preempt_enable(); \
+} while (0)
+
+#define irqsafe_cpu_add_1(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, +)
+#define irqsafe_cpu_add_2(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, +)
+#define irqsafe_cpu_add_4(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, +)
+#define irqsafe_cpu_add_8(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, +)
+
+#define irqsafe_cpu_and_1(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, &)
+#define irqsafe_cpu_and_2(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, &)
+#define irqsafe_cpu_and_4(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, &)
+#define irqsafe_cpu_and_8(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, &)
+
+#define irqsafe_cpu_or_1(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, |)
+#define irqsafe_cpu_or_2(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, |)
+#define irqsafe_cpu_or_4(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, |)
+#define irqsafe_cpu_or_8(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, |)
+
+#define irqsafe_cpu_xor_1(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, ^)
+#define irqsafe_cpu_xor_2(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, ^)
+#define irqsafe_cpu_xor_4(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, ^)
+#define irqsafe_cpu_xor_8(pcp, val) arch_irqsafe_cpu_to_op(pcp, val, ^)
+
+#define arch_irqsafe_cpu_cmpxchg(pcp, oval, nval) \
+({ \
+ typedef typeof(pcp) pcp_op_T__; \
+ pcp_op_T__ ret__; \
+ pcp_op_T__ *ptr__; \
+ preempt_disable(); \
+ ptr__ = __this_cpu_ptr(&(pcp)); \
+ switch (sizeof(*ptr__)) { \
+ case 8: \
+ ret__ = cmpxchg64(ptr__, oval, nval); \
+ break; \
+ default: \
+ ret__ = cmpxchg(ptr__, oval, nval); \
+ } \
+ preempt_enable(); \
+ ret__; \
+})
+
+#define irqsafe_cpu_cmpxchg_1(pcp, oval, nval) arch_irqsafe_cpu_cmpxchg(pcp, oval, nval)
+#define irqsafe_cpu_cmpxchg_2(pcp, oval, nval) arch_irqsafe_cpu_cmpxchg(pcp, oval, nval)
+#define irqsafe_cpu_cmpxchg_4(pcp, oval, nval) arch_irqsafe_cpu_cmpxchg(pcp, oval, nval)
+#define irqsafe_cpu_cmpxchg_8(pcp, oval, nval) arch_irqsafe_cpu_cmpxchg(pcp, oval, nval)
+
#include <asm-generic/percpu.h>
#endif /* __ARCH_S390_PERCPU__ */
diff --git a/arch/s390/include/asm/pgalloc.h b/arch/s390/include/asm/pgalloc.h
index 082eb4e..f6314af 100644
--- a/arch/s390/include/asm/pgalloc.h
+++ b/arch/s390/include/asm/pgalloc.h
@@ -19,14 +19,13 @@
#define check_pgt_cache() do {} while (0)
-unsigned long *crst_table_alloc(struct mm_struct *, int);
+unsigned long *crst_table_alloc(struct mm_struct *);
void crst_table_free(struct mm_struct *, unsigned long *);
void crst_table_free_rcu(struct mm_struct *, unsigned long *);
unsigned long *page_table_alloc(struct mm_struct *);
void page_table_free(struct mm_struct *, unsigned long *);
void page_table_free_rcu(struct mm_struct *, unsigned long *);
-void disable_noexec(struct mm_struct *, struct task_struct *);
static inline void clear_table(unsigned long *s, unsigned long val, size_t n)
{
@@ -50,9 +49,6 @@
static inline void crst_table_init(unsigned long *crst, unsigned long entry)
{
clear_table(crst, entry, sizeof(unsigned long)*2048);
- crst = get_shadow_table(crst);
- if (crst)
- clear_table(crst, entry, sizeof(unsigned long)*2048);
}
#ifndef __s390x__
@@ -69,10 +65,7 @@
#define pmd_free(mm, x) do { } while (0)
#define pgd_populate(mm, pgd, pud) BUG()
-#define pgd_populate_kernel(mm, pgd, pud) BUG()
-
#define pud_populate(mm, pud, pmd) BUG()
-#define pud_populate_kernel(mm, pud, pmd) BUG()
#else /* __s390x__ */
@@ -90,7 +83,7 @@
static inline pud_t *pud_alloc_one(struct mm_struct *mm, unsigned long address)
{
- unsigned long *table = crst_table_alloc(mm, mm->context.noexec);
+ unsigned long *table = crst_table_alloc(mm);
if (table)
crst_table_init(table, _REGION3_ENTRY_EMPTY);
return (pud_t *) table;
@@ -99,43 +92,21 @@
static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long vmaddr)
{
- unsigned long *table = crst_table_alloc(mm, mm->context.noexec);
+ unsigned long *table = crst_table_alloc(mm);
if (table)
crst_table_init(table, _SEGMENT_ENTRY_EMPTY);
return (pmd_t *) table;
}
#define pmd_free(mm, pmd) crst_table_free(mm, (unsigned long *) pmd)
-static inline void pgd_populate_kernel(struct mm_struct *mm,
- pgd_t *pgd, pud_t *pud)
+static inline void pgd_populate(struct mm_struct *mm, pgd_t *pgd, pud_t *pud)
{
pgd_val(*pgd) = _REGION2_ENTRY | __pa(pud);
}
-static inline void pgd_populate(struct mm_struct *mm, pgd_t *pgd, pud_t *pud)
-{
- pgd_populate_kernel(mm, pgd, pud);
- if (mm->context.noexec) {
- pgd = get_shadow_table(pgd);
- pud = get_shadow_table(pud);
- pgd_populate_kernel(mm, pgd, pud);
- }
-}
-
-static inline void pud_populate_kernel(struct mm_struct *mm,
- pud_t *pud, pmd_t *pmd)
-{
- pud_val(*pud) = _REGION3_ENTRY | __pa(pmd);
-}
-
static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd)
{
- pud_populate_kernel(mm, pud, pmd);
- if (mm->context.noexec) {
- pud = get_shadow_table(pud);
- pmd = get_shadow_table(pmd);
- pud_populate_kernel(mm, pud, pmd);
- }
+ pud_val(*pud) = _REGION3_ENTRY | __pa(pmd);
}
#endif /* __s390x__ */
@@ -143,29 +114,19 @@
static inline pgd_t *pgd_alloc(struct mm_struct *mm)
{
spin_lock_init(&mm->context.list_lock);
- INIT_LIST_HEAD(&mm->context.crst_list);
INIT_LIST_HEAD(&mm->context.pgtable_list);
- return (pgd_t *)
- crst_table_alloc(mm, user_mode == SECONDARY_SPACE_MODE);
+ return (pgd_t *) crst_table_alloc(mm);
}
#define pgd_free(mm, pgd) crst_table_free(mm, (unsigned long *) pgd)
-static inline void pmd_populate_kernel(struct mm_struct *mm,
- pmd_t *pmd, pte_t *pte)
-{
- pmd_val(*pmd) = _SEGMENT_ENTRY + __pa(pte);
-}
-
static inline void pmd_populate(struct mm_struct *mm,
pmd_t *pmd, pgtable_t pte)
{
- pmd_populate_kernel(mm, pmd, pte);
- if (mm->context.noexec) {
- pmd = get_shadow_table(pmd);
- pmd_populate_kernel(mm, pmd, pte + PTRS_PER_PTE);
- }
+ pmd_val(*pmd) = _SEGMENT_ENTRY + __pa(pte);
}
+#define pmd_populate_kernel(mm, pmd, pte) pmd_populate(mm, pmd, pte)
+
#define pmd_pgtable(pmd) \
(pgtable_t)(pmd_val(pmd) & -sizeof(pte_t)*PTRS_PER_PTE)
diff --git a/arch/s390/include/asm/pgtable.h b/arch/s390/include/asm/pgtable.h
index 02ace34..c4773a2 100644
--- a/arch/s390/include/asm/pgtable.h
+++ b/arch/s390/include/asm/pgtable.h
@@ -31,9 +31,8 @@
#ifndef __ASSEMBLY__
#include <linux/sched.h>
#include <linux/mm_types.h>
-#include <asm/bitops.h>
#include <asm/bug.h>
-#include <asm/processor.h>
+#include <asm/page.h>
extern pgd_t swapper_pg_dir[] __attribute__ ((aligned (4096)));
extern void paging_init(void);
@@ -243,11 +242,13 @@
/* Software bits in the page table entry */
#define _PAGE_SWT 0x001 /* SW pte type bit t */
#define _PAGE_SWX 0x002 /* SW pte type bit x */
-#define _PAGE_SPECIAL 0x004 /* SW associated with special page */
+#define _PAGE_SWC 0x004 /* SW pte changed bit (for KVM) */
+#define _PAGE_SWR 0x008 /* SW pte referenced bit (for KVM) */
+#define _PAGE_SPECIAL 0x010 /* SW associated with special page */
#define __HAVE_ARCH_PTE_SPECIAL
/* Set of bits not changed in pte_modify */
-#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_SPECIAL)
+#define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_SPECIAL | _PAGE_SWC | _PAGE_SWR)
/* Six different types of pages. */
#define _PAGE_TYPE_EMPTY 0x400
@@ -256,8 +257,6 @@
#define _PAGE_TYPE_FILE 0x601 /* bit 0x002 is used for offset !! */
#define _PAGE_TYPE_RO 0x200
#define _PAGE_TYPE_RW 0x000
-#define _PAGE_TYPE_EX_RO 0x202
-#define _PAGE_TYPE_EX_RW 0x002
/*
* Only four types for huge pages, using the invalid bit and protection bit
@@ -287,8 +286,6 @@
* _PAGE_TYPE_FILE 11?1 -> 11?1
* _PAGE_TYPE_RO 0100 -> 1100
* _PAGE_TYPE_RW 0000 -> 1000
- * _PAGE_TYPE_EX_RO 0110 -> 1110
- * _PAGE_TYPE_EX_RW 0010 -> 1010
*
* pte_none is true for bits combinations 1000, 1010, 1100, 1110
* pte_present is true for bits combinations 0000, 0010, 0100, 0110, 1001
@@ -297,14 +294,17 @@
*/
/* Page status table bits for virtualization */
-#define RCP_PCL_BIT 55
-#define RCP_HR_BIT 54
-#define RCP_HC_BIT 53
-#define RCP_GR_BIT 50
-#define RCP_GC_BIT 49
+#define RCP_ACC_BITS 0xf000000000000000UL
+#define RCP_FP_BIT 0x0800000000000000UL
+#define RCP_PCL_BIT 0x0080000000000000UL
+#define RCP_HR_BIT 0x0040000000000000UL
+#define RCP_HC_BIT 0x0020000000000000UL
+#define RCP_GR_BIT 0x0004000000000000UL
+#define RCP_GC_BIT 0x0002000000000000UL
-/* User dirty bit for KVM's migration feature */
-#define KVM_UD_BIT 47
+/* User dirty / referenced bit for KVM's migration feature */
+#define KVM_UR_BIT 0x0000800000000000UL
+#define KVM_UC_BIT 0x0000400000000000UL
#ifndef __s390x__
@@ -377,85 +377,54 @@
#define _ASCE_USER_BITS (_ASCE_SPACE_SWITCH | _ASCE_PRIVATE_SPACE | \
_ASCE_ALT_EVENT)
-/* Bits int the storage key */
-#define _PAGE_CHANGED 0x02 /* HW changed bit */
-#define _PAGE_REFERENCED 0x04 /* HW referenced bit */
-
/*
* Page protection definitions.
*/
#define PAGE_NONE __pgprot(_PAGE_TYPE_NONE)
#define PAGE_RO __pgprot(_PAGE_TYPE_RO)
#define PAGE_RW __pgprot(_PAGE_TYPE_RW)
-#define PAGE_EX_RO __pgprot(_PAGE_TYPE_EX_RO)
-#define PAGE_EX_RW __pgprot(_PAGE_TYPE_EX_RW)
#define PAGE_KERNEL PAGE_RW
#define PAGE_COPY PAGE_RO
/*
- * Dependent on the EXEC_PROTECT option s390 can do execute protection.
- * Write permission always implies read permission. In theory with a
- * primary/secondary page table execute only can be implemented but
- * it would cost an additional bit in the pte to distinguish all the
- * different pte types. To avoid that execute permission currently
- * implies read permission as well.
+ * On s390 the page table entry has an invalid bit and a read-only bit.
+ * Read permission implies execute permission and write permission
+ * implies read permission.
*/
/*xwr*/
#define __P000 PAGE_NONE
#define __P001 PAGE_RO
#define __P010 PAGE_RO
#define __P011 PAGE_RO
-#define __P100 PAGE_EX_RO
-#define __P101 PAGE_EX_RO
-#define __P110 PAGE_EX_RO
-#define __P111 PAGE_EX_RO
+#define __P100 PAGE_RO
+#define __P101 PAGE_RO
+#define __P110 PAGE_RO
+#define __P111 PAGE_RO
#define __S000 PAGE_NONE
#define __S001 PAGE_RO
#define __S010 PAGE_RW
#define __S011 PAGE_RW
-#define __S100 PAGE_EX_RO
-#define __S101 PAGE_EX_RO
-#define __S110 PAGE_EX_RW
-#define __S111 PAGE_EX_RW
+#define __S100 PAGE_RO
+#define __S101 PAGE_RO
+#define __S110 PAGE_RW
+#define __S111 PAGE_RW
-#ifndef __s390x__
-# define PxD_SHADOW_SHIFT 1
-#else /* __s390x__ */
-# define PxD_SHADOW_SHIFT 2
-#endif /* __s390x__ */
-
-static inline void *get_shadow_table(void *table)
+static inline int mm_exclusive(struct mm_struct *mm)
{
- unsigned long addr, offset;
- struct page *page;
-
- addr = (unsigned long) table;
- offset = addr & ((PAGE_SIZE << PxD_SHADOW_SHIFT) - 1);
- page = virt_to_page((void *)(addr ^ offset));
- return (void *)(addr_t)(page->index ? (page->index | offset) : 0UL);
+ return likely(mm == current->active_mm &&
+ atomic_read(&mm->context.attach_count) <= 1);
}
-/*
- * Certain architectures need to do special things when PTEs
- * within a page table are directly modified. Thus, the following
- * hook is made available.
- */
-static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
- pte_t *ptep, pte_t entry)
+static inline int mm_has_pgste(struct mm_struct *mm)
{
- *ptep = entry;
- if (mm->context.noexec) {
- if (!(pte_val(entry) & _PAGE_INVALID) &&
- (pte_val(entry) & _PAGE_SWX))
- pte_val(entry) |= _PAGE_RO;
- else
- pte_val(entry) = _PAGE_TYPE_EMPTY;
- ptep[PTRS_PER_PTE] = entry;
- }
+#ifdef CONFIG_PGSTE
+ if (unlikely(mm->context.has_pgste))
+ return 1;
+#endif
+ return 0;
}
-
/*
* pgd/pmd/pte query functions
*/
@@ -568,52 +537,127 @@
}
#define __HAVE_ARCH_PTE_SAME
-#define pte_same(a,b) (pte_val(a) == pte_val(b))
-
-static inline void rcp_lock(pte_t *ptep)
+static inline int pte_same(pte_t a, pte_t b)
{
-#ifdef CONFIG_PGSTE
- unsigned long *pgste = (unsigned long *) (ptep + PTRS_PER_PTE);
- preempt_disable();
- while (test_and_set_bit(RCP_PCL_BIT, pgste))
- ;
-#endif
+ return pte_val(a) == pte_val(b);
}
-static inline void rcp_unlock(pte_t *ptep)
+static inline pgste_t pgste_get_lock(pte_t *ptep)
+{
+ unsigned long new = 0;
+#ifdef CONFIG_PGSTE
+ unsigned long old;
+
+ preempt_disable();
+ asm(
+ " lg %0,%2\n"
+ "0: lgr %1,%0\n"
+ " nihh %0,0xff7f\n" /* clear RCP_PCL_BIT in old */
+ " oihh %1,0x0080\n" /* set RCP_PCL_BIT in new */
+ " csg %0,%1,%2\n"
+ " jl 0b\n"
+ : "=&d" (old), "=&d" (new), "=Q" (ptep[PTRS_PER_PTE])
+ : "Q" (ptep[PTRS_PER_PTE]) : "cc");
+#endif
+ return __pgste(new);
+}
+
+static inline void pgste_set_unlock(pte_t *ptep, pgste_t pgste)
{
#ifdef CONFIG_PGSTE
- unsigned long *pgste = (unsigned long *) (ptep + PTRS_PER_PTE);
- clear_bit(RCP_PCL_BIT, pgste);
+ asm(
+ " nihh %1,0xff7f\n" /* clear RCP_PCL_BIT */
+ " stg %1,%0\n"
+ : "=Q" (ptep[PTRS_PER_PTE])
+ : "d" (pgste_val(pgste)), "Q" (ptep[PTRS_PER_PTE]) : "cc");
preempt_enable();
#endif
}
-/* forward declaration for SetPageUptodate in page-flags.h*/
-static inline void page_clear_dirty(struct page *page, int mapped);
-#include <linux/page-flags.h>
-
-static inline void ptep_rcp_copy(pte_t *ptep)
+static inline pgste_t pgste_update_all(pte_t *ptep, pgste_t pgste)
{
#ifdef CONFIG_PGSTE
- struct page *page = virt_to_page(pte_val(*ptep));
- unsigned int skey;
- unsigned long *pgste = (unsigned long *) (ptep + PTRS_PER_PTE);
+ unsigned long pfn, bits;
+ unsigned char skey;
- skey = page_get_storage_key(page_to_phys(page));
- if (skey & _PAGE_CHANGED) {
- set_bit_simple(RCP_GC_BIT, pgste);
- set_bit_simple(KVM_UD_BIT, pgste);
+ pfn = pte_val(*ptep) >> PAGE_SHIFT;
+ skey = page_get_storage_key(pfn);
+ bits = skey & (_PAGE_CHANGED | _PAGE_REFERENCED);
+ /* Clear page changed & referenced bit in the storage key */
+ if (bits) {
+ skey ^= bits;
+ page_set_storage_key(pfn, skey, 1);
}
- if (skey & _PAGE_REFERENCED)
- set_bit_simple(RCP_GR_BIT, pgste);
- if (test_and_clear_bit_simple(RCP_HC_BIT, pgste)) {
- SetPageDirty(page);
- set_bit_simple(KVM_UD_BIT, pgste);
- }
- if (test_and_clear_bit_simple(RCP_HR_BIT, pgste))
- SetPageReferenced(page);
+ /* Transfer page changed & referenced bit to guest bits in pgste */
+ pgste_val(pgste) |= bits << 48; /* RCP_GR_BIT & RCP_GC_BIT */
+ /* Get host changed & referenced bits from pgste */
+ bits |= (pgste_val(pgste) & (RCP_HR_BIT | RCP_HC_BIT)) >> 52;
+ /* Clear host bits in pgste. */
+ pgste_val(pgste) &= ~(RCP_HR_BIT | RCP_HC_BIT);
+ pgste_val(pgste) &= ~(RCP_ACC_BITS | RCP_FP_BIT);
+ /* Copy page access key and fetch protection bit to pgste */
+ pgste_val(pgste) |=
+ (unsigned long) (skey & (_PAGE_ACC_BITS | _PAGE_FP_BIT)) << 56;
+ /* Transfer changed and referenced to kvm user bits */
+ pgste_val(pgste) |= bits << 45; /* KVM_UR_BIT & KVM_UC_BIT */
+ /* Transfer changed & referenced to pte sofware bits */
+ pte_val(*ptep) |= bits << 1; /* _PAGE_SWR & _PAGE_SWC */
#endif
+ return pgste;
+
+}
+
+static inline pgste_t pgste_update_young(pte_t *ptep, pgste_t pgste)
+{
+#ifdef CONFIG_PGSTE
+ int young;
+
+ young = page_reset_referenced(pte_val(*ptep) & PAGE_MASK);
+ /* Transfer page referenced bit to pte software bit (host view) */
+ if (young || (pgste_val(pgste) & RCP_HR_BIT))
+ pte_val(*ptep) |= _PAGE_SWR;
+ /* Clear host referenced bit in pgste. */
+ pgste_val(pgste) &= ~RCP_HR_BIT;
+ /* Transfer page referenced bit to guest bit in pgste */
+ pgste_val(pgste) |= (unsigned long) young << 50; /* set RCP_GR_BIT */
+#endif
+ return pgste;
+
+}
+
+static inline void pgste_set_pte(pte_t *ptep, pgste_t pgste)
+{
+#ifdef CONFIG_PGSTE
+ unsigned long pfn;
+ unsigned long okey, nkey;
+
+ pfn = pte_val(*ptep) >> PAGE_SHIFT;
+ okey = nkey = page_get_storage_key(pfn);
+ nkey &= ~(_PAGE_ACC_BITS | _PAGE_FP_BIT);
+ /* Set page access key and fetch protection bit from pgste */
+ nkey |= (pgste_val(pgste) & (RCP_ACC_BITS | RCP_FP_BIT)) >> 56;
+ if (okey != nkey)
+ page_set_storage_key(pfn, nkey, 1);
+#endif
+}
+
+/*
+ * Certain architectures need to do special things when PTEs
+ * within a page table are directly modified. Thus, the following
+ * hook is made available.
+ */
+static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
+ pte_t *ptep, pte_t entry)
+{
+ pgste_t pgste;
+
+ if (mm_has_pgste(mm)) {
+ pgste = pgste_get_lock(ptep);
+ pgste_set_pte(ptep, pgste);
+ *ptep = entry;
+ pgste_set_unlock(ptep, pgste);
+ } else
+ *ptep = entry;
}
/*
@@ -627,19 +671,19 @@
static inline int pte_dirty(pte_t pte)
{
- /* A pte is neither clean nor dirty on s/390. The dirty bit
- * is in the storage key. See page_test_and_clear_dirty for
- * details.
- */
+#ifdef CONFIG_PGSTE
+ if (pte_val(pte) & _PAGE_SWC)
+ return 1;
+#endif
return 0;
}
static inline int pte_young(pte_t pte)
{
- /* A pte is neither young nor old on s/390. The young bit
- * is in the storage key. See page_test_and_clear_young for
- * details.
- */
+#ifdef CONFIG_PGSTE
+ if (pte_val(pte) & _PAGE_SWR)
+ return 1;
+#endif
return 0;
}
@@ -647,64 +691,30 @@
* pgd/pmd/pte modification functions
*/
-#ifndef __s390x__
-
-#define pgd_clear(pgd) do { } while (0)
-#define pud_clear(pud) do { } while (0)
-
-#else /* __s390x__ */
-
-static inline void pgd_clear_kernel(pgd_t * pgd)
+static inline void pgd_clear(pgd_t *pgd)
{
+#ifdef __s390x__
if ((pgd_val(*pgd) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R2)
pgd_val(*pgd) = _REGION2_ENTRY_EMPTY;
-}
-
-static inline void pgd_clear(pgd_t * pgd)
-{
- pgd_t *shadow = get_shadow_table(pgd);
-
- pgd_clear_kernel(pgd);
- if (shadow)
- pgd_clear_kernel(shadow);
-}
-
-static inline void pud_clear_kernel(pud_t *pud)
-{
- if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3)
- pud_val(*pud) = _REGION3_ENTRY_EMPTY;
+#endif
}
static inline void pud_clear(pud_t *pud)
{
- pud_t *shadow = get_shadow_table(pud);
-
- pud_clear_kernel(pud);
- if (shadow)
- pud_clear_kernel(shadow);
+#ifdef __s390x__
+ if ((pud_val(*pud) & _REGION_ENTRY_TYPE_MASK) == _REGION_ENTRY_TYPE_R3)
+ pud_val(*pud) = _REGION3_ENTRY_EMPTY;
+#endif
}
-#endif /* __s390x__ */
-
-static inline void pmd_clear_kernel(pmd_t * pmdp)
+static inline void pmd_clear(pmd_t *pmdp)
{
pmd_val(*pmdp) = _SEGMENT_ENTRY_EMPTY;
}
-static inline void pmd_clear(pmd_t *pmd)
-{
- pmd_t *shadow = get_shadow_table(pmd);
-
- pmd_clear_kernel(pmd);
- if (shadow)
- pmd_clear_kernel(shadow);
-}
-
static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
{
pte_val(*ptep) = _PAGE_TYPE_EMPTY;
- if (mm->context.noexec)
- pte_val(ptep[PTRS_PER_PTE]) = _PAGE_TYPE_EMPTY;
}
/*
@@ -734,35 +744,27 @@
static inline pte_t pte_mkclean(pte_t pte)
{
- /* The only user of pte_mkclean is the fork() code.
- We must *not* clear the *physical* page dirty bit
- just because fork() wants to clear the dirty bit in
- *one* of the page's mappings. So we just do nothing. */
+#ifdef CONFIG_PGSTE
+ pte_val(pte) &= ~_PAGE_SWC;
+#endif
return pte;
}
static inline pte_t pte_mkdirty(pte_t pte)
{
- /* We do not explicitly set the dirty bit because the
- * sske instruction is slow. It is faster to let the
- * next instruction set the dirty bit.
- */
return pte;
}
static inline pte_t pte_mkold(pte_t pte)
{
- /* S/390 doesn't keep its dirty/referenced bit in the pte.
- * There is no point in clearing the real referenced bit.
- */
+#ifdef CONFIG_PGSTE
+ pte_val(pte) &= ~_PAGE_SWR;
+#endif
return pte;
}
static inline pte_t pte_mkyoung(pte_t pte)
{
- /* S/390 doesn't keep its dirty/referenced bit in the pte.
- * There is no point in setting the real referenced bit.
- */
return pte;
}
@@ -800,62 +802,60 @@
}
#endif
-#ifdef CONFIG_PGSTE
/*
- * Get (and clear) the user dirty bit for a PTE.
+ * Get (and clear) the user dirty bit for a pte.
*/
-static inline int kvm_s390_test_and_clear_page_dirty(struct mm_struct *mm,
- pte_t *ptep)
+static inline int ptep_test_and_clear_user_dirty(struct mm_struct *mm,
+ pte_t *ptep)
{
- int dirty;
- unsigned long *pgste;
- struct page *page;
- unsigned int skey;
+ pgste_t pgste;
+ int dirty = 0;
- if (!mm->context.has_pgste)
- return -EINVAL;
- rcp_lock(ptep);
- pgste = (unsigned long *) (ptep + PTRS_PER_PTE);
- page = virt_to_page(pte_val(*ptep));
- skey = page_get_storage_key(page_to_phys(page));
- if (skey & _PAGE_CHANGED) {
- set_bit_simple(RCP_GC_BIT, pgste);
- set_bit_simple(KVM_UD_BIT, pgste);
+ if (mm_has_pgste(mm)) {
+ pgste = pgste_get_lock(ptep);
+ pgste = pgste_update_all(ptep, pgste);
+ dirty = !!(pgste_val(pgste) & KVM_UC_BIT);
+ pgste_val(pgste) &= ~KVM_UC_BIT;
+ pgste_set_unlock(ptep, pgste);
+ return dirty;
}
- if (test_and_clear_bit_simple(RCP_HC_BIT, pgste)) {
- SetPageDirty(page);
- set_bit_simple(KVM_UD_BIT, pgste);
- }
- dirty = test_and_clear_bit_simple(KVM_UD_BIT, pgste);
- if (skey & _PAGE_CHANGED)
- page_clear_dirty(page, 1);
- rcp_unlock(ptep);
return dirty;
}
-#endif
+
+/*
+ * Get (and clear) the user referenced bit for a pte.
+ */
+static inline int ptep_test_and_clear_user_young(struct mm_struct *mm,
+ pte_t *ptep)
+{
+ pgste_t pgste;
+ int young = 0;
+
+ if (mm_has_pgste(mm)) {
+ pgste = pgste_get_lock(ptep);
+ pgste = pgste_update_young(ptep, pgste);
+ young = !!(pgste_val(pgste) & KVM_UR_BIT);
+ pgste_val(pgste) &= ~KVM_UR_BIT;
+ pgste_set_unlock(ptep, pgste);
+ }
+ return young;
+}
#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
unsigned long addr, pte_t *ptep)
{
-#ifdef CONFIG_PGSTE
- unsigned long physpage;
- int young;
- unsigned long *pgste;
+ pgste_t pgste;
+ pte_t pte;
- if (!vma->vm_mm->context.has_pgste)
- return 0;
- physpage = pte_val(*ptep) & PAGE_MASK;
- pgste = (unsigned long *) (ptep + PTRS_PER_PTE);
-
- young = ((page_get_storage_key(physpage) & _PAGE_REFERENCED) != 0);
- rcp_lock(ptep);
- if (young)
- set_bit_simple(RCP_GR_BIT, pgste);
- young |= test_and_clear_bit_simple(RCP_HR_BIT, pgste);
- rcp_unlock(ptep);
- return young;
-#endif
+ if (mm_has_pgste(vma->vm_mm)) {
+ pgste = pgste_get_lock(ptep);
+ pgste = pgste_update_young(ptep, pgste);
+ pte = *ptep;
+ *ptep = pte_mkold(pte);
+ pgste_set_unlock(ptep, pgste);
+ return pte_young(pte);
+ }
return 0;
}
@@ -867,10 +867,7 @@
* On s390 reference bits are in storage key and never in TLB
* With virtualization we handle the reference bit, without we
* we can simply return */
-#ifdef CONFIG_PGSTE
return ptep_test_and_clear_young(vma, address, ptep);
-#endif
- return 0;
}
static inline void __ptep_ipte(unsigned long address, pte_t *ptep)
@@ -890,25 +887,6 @@
}
}
-static inline void ptep_invalidate(struct mm_struct *mm,
- unsigned long address, pte_t *ptep)
-{
- if (mm->context.has_pgste) {
- rcp_lock(ptep);
- __ptep_ipte(address, ptep);
- ptep_rcp_copy(ptep);
- pte_val(*ptep) = _PAGE_TYPE_EMPTY;
- rcp_unlock(ptep);
- return;
- }
- __ptep_ipte(address, ptep);
- pte_val(*ptep) = _PAGE_TYPE_EMPTY;
- if (mm->context.noexec) {
- __ptep_ipte(address, ptep + PTRS_PER_PTE);
- pte_val(*(ptep + PTRS_PER_PTE)) = _PAGE_TYPE_EMPTY;
- }
-}
-
/*
* This is hard to understand. ptep_get_and_clear and ptep_clear_flush
* both clear the TLB for the unmapped pte. The reason is that
@@ -923,24 +901,72 @@
* is a nop.
*/
#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
-#define ptep_get_and_clear(__mm, __address, __ptep) \
-({ \
- pte_t __pte = *(__ptep); \
- (__mm)->context.flush_mm = 1; \
- if (atomic_read(&(__mm)->context.attach_count) > 1 || \
- (__mm) != current->active_mm) \
- ptep_invalidate(__mm, __address, __ptep); \
- else \
- pte_clear((__mm), (__address), (__ptep)); \
- __pte; \
-})
+static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
+ unsigned long address, pte_t *ptep)
+{
+ pgste_t pgste;
+ pte_t pte;
+
+ mm->context.flush_mm = 1;
+ if (mm_has_pgste(mm))
+ pgste = pgste_get_lock(ptep);
+
+ pte = *ptep;
+ if (!mm_exclusive(mm))
+ __ptep_ipte(address, ptep);
+ pte_val(*ptep) = _PAGE_TYPE_EMPTY;
+
+ if (mm_has_pgste(mm)) {
+ pgste = pgste_update_all(&pte, pgste);
+ pgste_set_unlock(ptep, pgste);
+ }
+ return pte;
+}
+
+#define __HAVE_ARCH_PTEP_MODIFY_PROT_TRANSACTION
+static inline pte_t ptep_modify_prot_start(struct mm_struct *mm,
+ unsigned long address,
+ pte_t *ptep)
+{
+ pte_t pte;
+
+ mm->context.flush_mm = 1;
+ if (mm_has_pgste(mm))
+ pgste_get_lock(ptep);
+
+ pte = *ptep;
+ if (!mm_exclusive(mm))
+ __ptep_ipte(address, ptep);
+ return pte;
+}
+
+static inline void ptep_modify_prot_commit(struct mm_struct *mm,
+ unsigned long address,
+ pte_t *ptep, pte_t pte)
+{
+ *ptep = pte;
+ if (mm_has_pgste(mm))
+ pgste_set_unlock(ptep, *(pgste_t *)(ptep + PTRS_PER_PTE));
+}
#define __HAVE_ARCH_PTEP_CLEAR_FLUSH
static inline pte_t ptep_clear_flush(struct vm_area_struct *vma,
unsigned long address, pte_t *ptep)
{
- pte_t pte = *ptep;
- ptep_invalidate(vma->vm_mm, address, ptep);
+ pgste_t pgste;
+ pte_t pte;
+
+ if (mm_has_pgste(vma->vm_mm))
+ pgste = pgste_get_lock(ptep);
+
+ pte = *ptep;
+ __ptep_ipte(address, ptep);
+ pte_val(*ptep) = _PAGE_TYPE_EMPTY;
+
+ if (mm_has_pgste(vma->vm_mm)) {
+ pgste = pgste_update_all(&pte, pgste);
+ pgste_set_unlock(ptep, pgste);
+ }
return pte;
}
@@ -953,76 +979,67 @@
*/
#define __HAVE_ARCH_PTEP_GET_AND_CLEAR_FULL
static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm,
- unsigned long addr,
+ unsigned long address,
pte_t *ptep, int full)
{
- pte_t pte = *ptep;
+ pgste_t pgste;
+ pte_t pte;
- if (full)
- pte_clear(mm, addr, ptep);
- else
- ptep_invalidate(mm, addr, ptep);
+ if (mm_has_pgste(mm))
+ pgste = pgste_get_lock(ptep);
+
+ pte = *ptep;
+ if (!full)
+ __ptep_ipte(address, ptep);
+ pte_val(*ptep) = _PAGE_TYPE_EMPTY;
+
+ if (mm_has_pgste(mm)) {
+ pgste = pgste_update_all(&pte, pgste);
+ pgste_set_unlock(ptep, pgste);
+ }
return pte;
}
#define __HAVE_ARCH_PTEP_SET_WRPROTECT
-#define ptep_set_wrprotect(__mm, __addr, __ptep) \
-({ \
- pte_t __pte = *(__ptep); \
- if (pte_write(__pte)) { \
- (__mm)->context.flush_mm = 1; \
- if (atomic_read(&(__mm)->context.attach_count) > 1 || \
- (__mm) != current->active_mm) \
- ptep_invalidate(__mm, __addr, __ptep); \
- set_pte_at(__mm, __addr, __ptep, pte_wrprotect(__pte)); \
- } \
-})
+static inline pte_t ptep_set_wrprotect(struct mm_struct *mm,
+ unsigned long address, pte_t *ptep)
+{
+ pgste_t pgste;
+ pte_t pte = *ptep;
+
+ if (pte_write(pte)) {
+ mm->context.flush_mm = 1;
+ if (mm_has_pgste(mm))
+ pgste = pgste_get_lock(ptep);
+
+ if (!mm_exclusive(mm))
+ __ptep_ipte(address, ptep);
+ *ptep = pte_wrprotect(pte);
+
+ if (mm_has_pgste(mm))
+ pgste_set_unlock(ptep, pgste);
+ }
+ return pte;
+}
#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
-#define ptep_set_access_flags(__vma, __addr, __ptep, __entry, __dirty) \
-({ \
- int __changed = !pte_same(*(__ptep), __entry); \
- if (__changed) { \
- ptep_invalidate((__vma)->vm_mm, __addr, __ptep); \
- set_pte_at((__vma)->vm_mm, __addr, __ptep, __entry); \
- } \
- __changed; \
-})
-
-/*
- * Test and clear dirty bit in storage key.
- * We can't clear the changed bit atomically. This is a potential
- * race against modification of the referenced bit. This function
- * should therefore only be called if it is not mapped in any
- * address space.
- */
-#define __HAVE_ARCH_PAGE_TEST_DIRTY
-static inline int page_test_dirty(struct page *page)
+static inline int ptep_set_access_flags(struct vm_area_struct *vma,
+ unsigned long address, pte_t *ptep,
+ pte_t entry, int dirty)
{
- return (page_get_storage_key(page_to_phys(page)) & _PAGE_CHANGED) != 0;
-}
+ pgste_t pgste;
-#define __HAVE_ARCH_PAGE_CLEAR_DIRTY
-static inline void page_clear_dirty(struct page *page, int mapped)
-{
- page_set_storage_key(page_to_phys(page), PAGE_DEFAULT_KEY, mapped);
-}
+ if (pte_same(*ptep, entry))
+ return 0;
+ if (mm_has_pgste(vma->vm_mm))
+ pgste = pgste_get_lock(ptep);
-/*
- * Test and clear referenced bit in storage key.
- */
-#define __HAVE_ARCH_PAGE_TEST_AND_CLEAR_YOUNG
-static inline int page_test_and_clear_young(struct page *page)
-{
- unsigned long physpage = page_to_phys(page);
- int ccode;
+ __ptep_ipte(address, ptep);
+ *ptep = entry;
- asm volatile(
- " rrbe 0,%1\n"
- " ipm %0\n"
- " srl %0,28\n"
- : "=d" (ccode) : "a" (physpage) : "cc" );
- return ccode & 2;
+ if (mm_has_pgste(vma->vm_mm))
+ pgste_set_unlock(ptep, pgste);
+ return 1;
}
/*
diff --git a/arch/s390/include/asm/processor.h b/arch/s390/include/asm/processor.h
index 2c79b64..1300c30 100644
--- a/arch/s390/include/asm/processor.h
+++ b/arch/s390/include/asm/processor.h
@@ -84,6 +84,7 @@
struct per_event per_event; /* Cause of the last PER trap */
/* pfault_wait is used to block the process on a pfault event */
unsigned long pfault_wait;
+ struct list_head list;
};
typedef struct thread_struct thread_struct;
diff --git a/arch/s390/include/asm/tlb.h b/arch/s390/include/asm/tlb.h
index 9074a54..77eee54 100644
--- a/arch/s390/include/asm/tlb.h
+++ b/arch/s390/include/asm/tlb.h
@@ -29,65 +29,77 @@
#include <asm/smp.h>
#include <asm/tlbflush.h>
-#ifndef CONFIG_SMP
-#define TLB_NR_PTRS 1
-#else
-#define TLB_NR_PTRS 508
-#endif
-
struct mmu_gather {
struct mm_struct *mm;
unsigned int fullmm;
unsigned int nr_ptes;
unsigned int nr_pxds;
- void *array[TLB_NR_PTRS];
+ unsigned int max;
+ void **array;
+ void *local[8];
};
-DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
-
-static inline struct mmu_gather *tlb_gather_mmu(struct mm_struct *mm,
- unsigned int full_mm_flush)
+static inline void __tlb_alloc_page(struct mmu_gather *tlb)
{
- struct mmu_gather *tlb = &get_cpu_var(mmu_gathers);
+ unsigned long addr = __get_free_pages(GFP_NOWAIT | __GFP_NOWARN, 0);
- tlb->mm = mm;
- tlb->fullmm = full_mm_flush;
- tlb->nr_ptes = 0;
- tlb->nr_pxds = TLB_NR_PTRS;
- if (tlb->fullmm)
- __tlb_flush_mm(mm);
- return tlb;
+ if (addr) {
+ tlb->array = (void *) addr;
+ tlb->max = PAGE_SIZE / sizeof(void *);
+ }
}
-static inline void tlb_flush_mmu(struct mmu_gather *tlb,
- unsigned long start, unsigned long end)
+static inline void tlb_gather_mmu(struct mmu_gather *tlb,
+ struct mm_struct *mm,
+ unsigned int full_mm_flush)
{
- if (!tlb->fullmm && (tlb->nr_ptes > 0 || tlb->nr_pxds < TLB_NR_PTRS))
+ tlb->mm = mm;
+ tlb->max = ARRAY_SIZE(tlb->local);
+ tlb->array = tlb->local;
+ tlb->fullmm = full_mm_flush;
+ if (tlb->fullmm)
+ __tlb_flush_mm(mm);
+ else
+ __tlb_alloc_page(tlb);
+ tlb->nr_ptes = 0;
+ tlb->nr_pxds = tlb->max;
+}
+
+static inline void tlb_flush_mmu(struct mmu_gather *tlb)
+{
+ if (!tlb->fullmm && (tlb->nr_ptes > 0 || tlb->nr_pxds < tlb->max))
__tlb_flush_mm(tlb->mm);
while (tlb->nr_ptes > 0)
page_table_free_rcu(tlb->mm, tlb->array[--tlb->nr_ptes]);
- while (tlb->nr_pxds < TLB_NR_PTRS)
+ while (tlb->nr_pxds < tlb->max)
crst_table_free_rcu(tlb->mm, tlb->array[tlb->nr_pxds++]);
}
static inline void tlb_finish_mmu(struct mmu_gather *tlb,
unsigned long start, unsigned long end)
{
- tlb_flush_mmu(tlb, start, end);
+ tlb_flush_mmu(tlb);
rcu_table_freelist_finish();
/* keep the page table cache within bounds */
check_pgt_cache();
- put_cpu_var(mmu_gathers);
+ if (tlb->array != tlb->local)
+ free_pages((unsigned long) tlb->array, 0);
}
/*
* Release the page cache reference for a pte removed by
- * tlb_ptep_clear_flush. In both flush modes the tlb fo a page cache page
+ * tlb_ptep_clear_flush. In both flush modes the tlb for a page cache page
* has already been freed, so just do free_page_and_swap_cache.
*/
+static inline int __tlb_remove_page(struct mmu_gather *tlb, struct page *page)
+{
+ free_page_and_swap_cache(page);
+ return 1; /* avoid calling tlb_flush_mmu */
+}
+
static inline void tlb_remove_page(struct mmu_gather *tlb, struct page *page)
{
free_page_and_swap_cache(page);
@@ -103,7 +115,7 @@
if (!tlb->fullmm) {
tlb->array[tlb->nr_ptes++] = pte;
if (tlb->nr_ptes >= tlb->nr_pxds)
- tlb_flush_mmu(tlb, 0, 0);
+ tlb_flush_mmu(tlb);
} else
page_table_free(tlb->mm, (unsigned long *) pte);
}
@@ -124,7 +136,7 @@
if (!tlb->fullmm) {
tlb->array[--tlb->nr_pxds] = pmd;
if (tlb->nr_ptes >= tlb->nr_pxds)
- tlb_flush_mmu(tlb, 0, 0);
+ tlb_flush_mmu(tlb);
} else
crst_table_free(tlb->mm, (unsigned long *) pmd);
#endif
@@ -146,7 +158,7 @@
if (!tlb->fullmm) {
tlb->array[--tlb->nr_pxds] = pud;
if (tlb->nr_ptes >= tlb->nr_pxds)
- tlb_flush_mmu(tlb, 0, 0);
+ tlb_flush_mmu(tlb);
} else
crst_table_free(tlb->mm, (unsigned long *) pud);
#endif
diff --git a/arch/s390/include/asm/tlbflush.h b/arch/s390/include/asm/tlbflush.h
index 29d5d6d..b7a4f2e 100644
--- a/arch/s390/include/asm/tlbflush.h
+++ b/arch/s390/include/asm/tlbflush.h
@@ -50,7 +50,7 @@
/*
* If the process only ran on the local cpu, do a local flush.
*/
- local_cpumask = cpumask_of_cpu(smp_processor_id());
+ cpumask_copy(&local_cpumask, cpumask_of(smp_processor_id()));
if (cpumask_equal(mm_cpumask(mm), &local_cpumask))
__tlb_flush_local();
else
@@ -80,16 +80,11 @@
* on all cpus instead of doing a local flush if the mm
* only ran on the local cpu.
*/
- if (MACHINE_HAS_IDTE) {
- if (mm->context.noexec)
- __tlb_flush_idte((unsigned long)
- get_shadow_table(mm->pgd) |
- mm->context.asce_bits);
+ if (MACHINE_HAS_IDTE)
__tlb_flush_idte((unsigned long) mm->pgd |
mm->context.asce_bits);
- return;
- }
- __tlb_flush_full(mm);
+ else
+ __tlb_flush_full(mm);
}
static inline void __tlb_flush_mm_cond(struct mm_struct * mm)
diff --git a/arch/s390/include/asm/unistd.h b/arch/s390/include/asm/unistd.h
index e821525..9208e69 100644
--- a/arch/s390/include/asm/unistd.h
+++ b/arch/s390/include/asm/unistd.h
@@ -385,6 +385,7 @@
/* Ignore system calls that are also reachable via sys_socket */
#define __IGNORE_recvmmsg
+#define __IGNORE_sendmmsg
#define __ARCH_WANT_IPC_PARSE_VERSION
#define __ARCH_WANT_OLD_READDIR
diff --git a/arch/s390/kernel/asm-offsets.c b/arch/s390/kernel/asm-offsets.c
index fe03c14..edfbd17 100644
--- a/arch/s390/kernel/asm-offsets.c
+++ b/arch/s390/kernel/asm-offsets.c
@@ -124,13 +124,11 @@
DEFINE(__LC_LAST_UPDATE_TIMER, offsetof(struct _lowcore, last_update_timer));
DEFINE(__LC_LAST_UPDATE_CLOCK, offsetof(struct _lowcore, last_update_clock));
DEFINE(__LC_CURRENT, offsetof(struct _lowcore, current_task));
+ DEFINE(__LC_CURRENT_PID, offsetof(struct _lowcore, current_pid));
DEFINE(__LC_THREAD_INFO, offsetof(struct _lowcore, thread_info));
DEFINE(__LC_KERNEL_STACK, offsetof(struct _lowcore, kernel_stack));
DEFINE(__LC_ASYNC_STACK, offsetof(struct _lowcore, async_stack));
DEFINE(__LC_PANIC_STACK, offsetof(struct _lowcore, panic_stack));
- DEFINE(__LC_KERNEL_ASCE, offsetof(struct _lowcore, kernel_asce));
- DEFINE(__LC_USER_ASCE, offsetof(struct _lowcore, user_asce));
- DEFINE(__LC_USER_EXEC_ASCE, offsetof(struct _lowcore, user_exec_asce));
DEFINE(__LC_INT_CLOCK, offsetof(struct _lowcore, int_clock));
DEFINE(__LC_MCCK_CLOCK, offsetof(struct _lowcore, mcck_clock));
DEFINE(__LC_MACHINE_FLAGS, offsetof(struct _lowcore, machine_flags));
diff --git a/arch/s390/kernel/entry.S b/arch/s390/kernel/entry.S
index 1b67fc6..0476174 100644
--- a/arch/s390/kernel/entry.S
+++ b/arch/s390/kernel/entry.S
@@ -212,6 +212,7 @@
lctl %c4,%c4,__TASK_pid(%r3) # load pid to control reg. 4
lm %r6,%r15,__SF_GPRS(%r15) # load gprs of next task
st %r3,__LC_CURRENT # store task struct of next
+ mvc __LC_CURRENT_PID(4,%r0),__TASK_pid(%r3) # store pid of next
st %r5,__LC_THREAD_INFO # store thread info of next
ahi %r5,STACK_SIZE # end of kernel stack of next
st %r5,__LC_KERNEL_STACK # store end of kernel stack
diff --git a/arch/s390/kernel/entry64.S b/arch/s390/kernel/entry64.S
index 9fd8645..d61967e 100644
--- a/arch/s390/kernel/entry64.S
+++ b/arch/s390/kernel/entry64.S
@@ -220,6 +220,7 @@
lctl %c4,%c4,__TASK_pid(%r3) # load pid to control reg. 4
lmg %r6,%r15,__SF_GPRS(%r15) # load gprs of next task
stg %r3,__LC_CURRENT # store task struct of next
+ mvc __LC_CURRENT_PID+4(4,%r0),__TASK_pid(%r3) # store pid of next
stg %r5,__LC_THREAD_INFO # store thread info of next
aghi %r5,STACK_SIZE # end of kernel stack of next
stg %r5,__LC_KERNEL_STACK # store end of kernel stack
diff --git a/arch/s390/kernel/irq.c b/arch/s390/kernel/irq.c
index ea5099c..e204f95 100644
--- a/arch/s390/kernel/irq.c
+++ b/arch/s390/kernel/irq.c
@@ -32,6 +32,7 @@
{.name = "VRT", .desc = "[EXT] Virtio" },
{.name = "SCP", .desc = "[EXT] Service Call" },
{.name = "IUC", .desc = "[EXT] IUCV" },
+ {.name = "CPM", .desc = "[EXT] CPU Measurement" },
{.name = "QAI", .desc = "[I/O] QDIO Adapter Interrupt" },
{.name = "QDI", .desc = "[I/O] QDIO Interrupt" },
{.name = "DAS", .desc = "[I/O] DASD" },
diff --git a/arch/s390/kernel/process.c b/arch/s390/kernel/process.c
index a895e69..541a750 100644
--- a/arch/s390/kernel/process.c
+++ b/arch/s390/kernel/process.c
@@ -9,41 +9,26 @@
#include <linux/compiler.h>
#include <linux/cpu.h>
-#include <linux/errno.h>
#include <linux/sched.h>
#include <linux/kernel.h>
#include <linux/mm.h>
-#include <linux/fs.h>
#include <linux/smp.h>
-#include <linux/stddef.h>
#include <linux/slab.h>
-#include <linux/unistd.h>
-#include <linux/ptrace.h>
-#include <linux/vmalloc.h>
-#include <linux/user.h>
#include <linux/interrupt.h>
-#include <linux/delay.h>
-#include <linux/reboot.h>
-#include <linux/init.h>
-#include <linux/module.h>
-#include <linux/notifier.h>
#include <linux/tick.h>
-#include <linux/elfcore.h>
-#include <linux/kernel_stat.h>
#include <linux/personality.h>
#include <linux/syscalls.h>
#include <linux/compat.h>
#include <linux/kprobes.h>
#include <linux/random.h>
-#include <asm/compat.h>
-#include <asm/uaccess.h>
-#include <asm/pgtable.h>
+#include <linux/module.h>
#include <asm/system.h>
#include <asm/io.h>
#include <asm/processor.h>
#include <asm/irq.h>
#include <asm/timer.h>
#include <asm/nmi.h>
+#include <asm/compat.h>
#include <asm/smp.h>
#include "entry.h"
diff --git a/arch/s390/kernel/setup.c b/arch/s390/kernel/setup.c
index f5434d1..0c35dee 100644
--- a/arch/s390/kernel/setup.c
+++ b/arch/s390/kernel/setup.c
@@ -305,8 +305,7 @@
*/
static int __init early_parse_switch_amode(char *p)
{
- if (user_mode != SECONDARY_SPACE_MODE)
- user_mode = PRIMARY_SPACE_MODE;
+ user_mode = PRIMARY_SPACE_MODE;
return 0;
}
early_param("switch_amode", early_parse_switch_amode);
@@ -315,10 +314,6 @@
{
if (p && strcmp(p, "primary") == 0)
user_mode = PRIMARY_SPACE_MODE;
-#ifdef CONFIG_S390_EXEC_PROTECT
- else if (p && strcmp(p, "secondary") == 0)
- user_mode = SECONDARY_SPACE_MODE;
-#endif
else if (!p || strcmp(p, "home") == 0)
user_mode = HOME_SPACE_MODE;
else
@@ -327,31 +322,9 @@
}
early_param("user_mode", early_parse_user_mode);
-#ifdef CONFIG_S390_EXEC_PROTECT
-/*
- * Enable execute protection?
- */
-static int __init early_parse_noexec(char *p)
-{
- if (!strncmp(p, "off", 3))
- return 0;
- user_mode = SECONDARY_SPACE_MODE;
- return 0;
-}
-early_param("noexec", early_parse_noexec);
-#endif /* CONFIG_S390_EXEC_PROTECT */
-
static void setup_addressing_mode(void)
{
- if (user_mode == SECONDARY_SPACE_MODE) {
- if (set_amode_and_uaccess(PSW_ASC_SECONDARY,
- PSW32_ASC_SECONDARY))
- pr_info("Execute protection active, "
- "mvcos available\n");
- else
- pr_info("Execute protection active, "
- "mvcos not available\n");
- } else if (user_mode == PRIMARY_SPACE_MODE) {
+ if (user_mode == PRIMARY_SPACE_MODE) {
if (set_amode_and_uaccess(PSW_ASC_PRIMARY, PSW32_ASC_PRIMARY))
pr_info("Address spaces switched, "
"mvcos available\n");
diff --git a/arch/s390/kernel/smp.c b/arch/s390/kernel/smp.c
index 63c7d9f..f8e85ec 100644
--- a/arch/s390/kernel/smp.c
+++ b/arch/s390/kernel/smp.c
@@ -335,7 +335,7 @@
smp_cpu_polarization[logical_cpu] = POLARIZATION_UNKNWN;
if (!cpu_stopped(logical_cpu))
continue;
- cpu_set(logical_cpu, cpu_present_map);
+ set_cpu_present(logical_cpu, true);
smp_cpu_state[logical_cpu] = CPU_STATE_CONFIGURED;
logical_cpu = cpumask_next(logical_cpu, &avail);
if (logical_cpu >= nr_cpu_ids)
@@ -367,7 +367,7 @@
continue;
__cpu_logical_map[logical_cpu] = cpu_id;
smp_cpu_polarization[logical_cpu] = POLARIZATION_UNKNWN;
- cpu_set(logical_cpu, cpu_present_map);
+ set_cpu_present(logical_cpu, true);
if (cpu >= info->configured)
smp_cpu_state[logical_cpu] = CPU_STATE_STANDBY;
else
@@ -385,7 +385,7 @@
{
cpumask_t avail;
- cpus_xor(avail, cpu_possible_map, cpu_present_map);
+ cpumask_xor(&avail, cpu_possible_mask, cpu_present_mask);
if (smp_use_sigp_detection)
return smp_rescan_cpus_sigp(avail);
else
@@ -467,7 +467,7 @@
notify_cpu_starting(smp_processor_id());
/* Mark this cpu as online */
ipi_call_lock();
- cpu_set(smp_processor_id(), cpu_online_map);
+ set_cpu_online(smp_processor_id(), true);
ipi_call_unlock();
/* Switch on interrupts */
local_irq_enable();
@@ -644,7 +644,7 @@
struct ec_creg_mask_parms cr_parms;
int cpu = smp_processor_id();
- cpu_clear(cpu, cpu_online_map);
+ set_cpu_online(cpu, false);
/* Disable pfault pseudo page faults on this cpu. */
pfault_fini();
@@ -654,8 +654,8 @@
/* disable all external interrupts */
cr_parms.orvals[0] = 0;
- cr_parms.andvals[0] = ~(1 << 15 | 1 << 14 | 1 << 13 | 1 << 12 |
- 1 << 11 | 1 << 10 | 1 << 6 | 1 << 4);
+ cr_parms.andvals[0] = ~(1 << 15 | 1 << 14 | 1 << 13 | 1 << 11 |
+ 1 << 10 | 1 << 9 | 1 << 6 | 1 << 4);
/* disable all I/O interrupts */
cr_parms.orvals[6] = 0;
cr_parms.andvals[6] = ~(1 << 31 | 1 << 30 | 1 << 29 | 1 << 28 |
@@ -681,7 +681,7 @@
atomic_dec(&init_mm.context.attach_count);
}
-void cpu_die(void)
+void __noreturn cpu_die(void)
{
idle_task_exit();
while (sigp(smp_processor_id(), sigp_stop) == sigp_busy)
@@ -738,8 +738,8 @@
BUG_ON(smp_processor_id() != 0);
current_thread_info()->cpu = 0;
- cpu_set(0, cpu_present_map);
- cpu_set(0, cpu_online_map);
+ set_cpu_present(0, true);
+ set_cpu_online(0, true);
S390_lowcore.percpu_offset = __per_cpu_offset[0];
current_set[0] = current;
smp_cpu_state[0] = CPU_STATE_CONFIGURED;
@@ -1016,21 +1016,21 @@
get_online_cpus();
mutex_lock(&smp_cpu_state_mutex);
- newcpus = cpu_present_map;
+ cpumask_copy(&newcpus, cpu_present_mask);
rc = __smp_rescan_cpus();
if (rc)
goto out;
- cpus_andnot(newcpus, cpu_present_map, newcpus);
- for_each_cpu_mask(cpu, newcpus) {
+ cpumask_andnot(&newcpus, cpu_present_mask, &newcpus);
+ for_each_cpu(cpu, &newcpus) {
rc = smp_add_present_cpu(cpu);
if (rc)
- cpu_clear(cpu, cpu_present_map);
+ set_cpu_present(cpu, false);
}
rc = 0;
out:
mutex_unlock(&smp_cpu_state_mutex);
put_online_cpus();
- if (!cpus_empty(newcpus))
+ if (!cpumask_empty(&newcpus))
topology_schedule_update();
return rc;
}
diff --git a/arch/s390/kernel/time.c b/arch/s390/kernel/time.c
index 87be655..a59557f 100644
--- a/arch/s390/kernel/time.c
+++ b/arch/s390/kernel/time.c
@@ -810,7 +810,7 @@
etr_sync.etr_port = port;
get_online_cpus();
atomic_set(&etr_sync.cpus, num_online_cpus() - 1);
- rc = stop_machine(etr_sync_clock, &etr_sync, &cpu_online_map);
+ rc = stop_machine(etr_sync_clock, &etr_sync, cpu_online_mask);
put_online_cpus();
return rc;
}
@@ -1579,7 +1579,7 @@
memset(&stp_sync, 0, sizeof(stp_sync));
get_online_cpus();
atomic_set(&stp_sync.cpus, num_online_cpus() - 1);
- stop_machine(stp_sync_clock, &stp_sync, &cpu_online_map);
+ stop_machine(stp_sync_clock, &stp_sync, cpu_online_mask);
put_online_cpus();
if (!check_sync_clock())
diff --git a/arch/s390/kernel/topology.c b/arch/s390/kernel/topology.c
index 94b06c3..2eafb8c 100644
--- a/arch/s390/kernel/topology.c
+++ b/arch/s390/kernel/topology.c
@@ -52,20 +52,20 @@
{
cpumask_t mask;
- cpus_clear(mask);
+ cpumask_clear(&mask);
if (!topology_enabled || !MACHINE_HAS_TOPOLOGY) {
cpumask_copy(&mask, cpumask_of(cpu));
return mask;
}
while (info) {
- if (cpu_isset(cpu, info->mask)) {
+ if (cpumask_test_cpu(cpu, &info->mask)) {
mask = info->mask;
break;
}
info = info->next;
}
- if (cpus_empty(mask))
- mask = cpumask_of_cpu(cpu);
+ if (cpumask_empty(&mask))
+ cpumask_copy(&mask, cpumask_of(cpu));
return mask;
}
@@ -85,10 +85,10 @@
if (cpu_logical_map(lcpu) != rcpu)
continue;
#ifdef CONFIG_SCHED_BOOK
- cpu_set(lcpu, book->mask);
+ cpumask_set_cpu(lcpu, &book->mask);
cpu_book_id[lcpu] = book->id;
#endif
- cpu_set(lcpu, core->mask);
+ cpumask_set_cpu(lcpu, &core->mask);
cpu_core_id[lcpu] = core->id;
smp_cpu_polarization[lcpu] = tl_cpu->pp;
}
@@ -101,13 +101,13 @@
info = &core_info;
while (info) {
- cpus_clear(info->mask);
+ cpumask_clear(&info->mask);
info = info->next;
}
#ifdef CONFIG_SCHED_BOOK
info = &book_info;
while (info) {
- cpus_clear(info->mask);
+ cpumask_clear(&info->mask);
info = info->next;
}
#endif
diff --git a/arch/s390/kernel/vdso32/Makefile b/arch/s390/kernel/vdso32/Makefile
index d13e875..8ad2b34 100644
--- a/arch/s390/kernel/vdso32/Makefile
+++ b/arch/s390/kernel/vdso32/Makefile
@@ -22,6 +22,9 @@
extra-y += vdso32.lds
CPPFLAGS_vdso32.lds += -P -C -U$(ARCH)
+# Disable gcov profiling for VDSO code
+GCOV_PROFILE := n
+
# Force dependency (incbin is bad)
$(obj)/vdso32_wrapper.o : $(obj)/vdso32.so
diff --git a/arch/s390/kernel/vdso64/Makefile b/arch/s390/kernel/vdso64/Makefile
index 449352d..2a8ddfd 100644
--- a/arch/s390/kernel/vdso64/Makefile
+++ b/arch/s390/kernel/vdso64/Makefile
@@ -22,6 +22,9 @@
extra-y += vdso64.lds
CPPFLAGS_vdso64.lds += -P -C -U$(ARCH)
+# Disable gcov profiling for VDSO code
+GCOV_PROFILE := n
+
# Force dependency (incbin is bad)
$(obj)/vdso64_wrapper.o : $(obj)/vdso64.so
diff --git a/arch/s390/kernel/vmlinux.lds.S b/arch/s390/kernel/vmlinux.lds.S
index 1bc18cd..56fe6bc 100644
--- a/arch/s390/kernel/vmlinux.lds.S
+++ b/arch/s390/kernel/vmlinux.lds.S
@@ -77,7 +77,7 @@
. = ALIGN(PAGE_SIZE);
INIT_DATA_SECTION(0x100)
- PERCPU(0x100, PAGE_SIZE)
+ PERCPU_SECTION(0x100)
. = ALIGN(PAGE_SIZE);
__init_end = .; /* freed after init ends here */
diff --git a/arch/s390/mm/extmem.c b/arch/s390/mm/extmem.c
index 3cc95dd..075ddad 100644
--- a/arch/s390/mm/extmem.c
+++ b/arch/s390/mm/extmem.c
@@ -412,6 +412,7 @@
struct dcss_segment *seg;
int rc, diag_cc;
+ start_addr = end_addr = 0;
seg = kmalloc(sizeof(*seg), GFP_KERNEL | GFP_DMA);
if (seg == NULL) {
rc = -ENOMEM;
@@ -573,6 +574,7 @@
unsigned long start_addr, end_addr, dummy;
int rc, diag_cc;
+ start_addr = end_addr = 0;
mutex_lock(&dcss_lock);
seg = segment_by_name (name);
if (seg == NULL) {
@@ -681,8 +683,6 @@
segment_save(char *name)
{
struct dcss_segment *seg;
- int startpfn = 0;
- int endpfn = 0;
char cmd1[160];
char cmd2[80];
int i, response;
@@ -698,8 +698,6 @@
goto out;
}
- startpfn = seg->start_addr >> PAGE_SHIFT;
- endpfn = (seg->end) >> PAGE_SHIFT;
sprintf(cmd1, "DEFSEG %s", name);
for (i=0; i<seg->segcnt; i++) {
sprintf(cmd1+strlen(cmd1), " %lX-%lX %s",
diff --git a/arch/s390/mm/fault.c b/arch/s390/mm/fault.c
index ab98813..a0f9e73 100644
--- a/arch/s390/mm/fault.c
+++ b/arch/s390/mm/fault.c
@@ -225,33 +225,6 @@
force_sig_info(SIGBUS, &si, tsk);
}
-#ifdef CONFIG_S390_EXEC_PROTECT
-static noinline int signal_return(struct pt_regs *regs, long int_code,
- unsigned long trans_exc_code)
-{
- u16 instruction;
- int rc;
-
- rc = __get_user(instruction, (u16 __user *) regs->psw.addr);
-
- if (!rc && instruction == 0x0a77) {
- clear_tsk_thread_flag(current, TIF_PER_TRAP);
- if (is_compat_task())
- sys32_sigreturn();
- else
- sys_sigreturn();
- } else if (!rc && instruction == 0x0aad) {
- clear_tsk_thread_flag(current, TIF_PER_TRAP);
- if (is_compat_task())
- sys32_rt_sigreturn();
- else
- sys_rt_sigreturn();
- } else
- do_sigsegv(regs, int_code, SEGV_MAPERR, trans_exc_code);
- return 0;
-}
-#endif /* CONFIG_S390_EXEC_PROTECT */
-
static noinline void do_fault_error(struct pt_regs *regs, long int_code,
unsigned long trans_exc_code, int fault)
{
@@ -259,13 +232,6 @@
switch (fault) {
case VM_FAULT_BADACCESS:
-#ifdef CONFIG_S390_EXEC_PROTECT
- if ((regs->psw.mask & PSW_MASK_ASC) == PSW_ASC_SECONDARY &&
- (trans_exc_code & 3) == 0) {
- signal_return(regs, int_code, trans_exc_code);
- break;
- }
-#endif /* CONFIG_S390_EXEC_PROTECT */
case VM_FAULT_BADMAP:
/* Bad memory access. Check if it is kernel or user space. */
if (regs->psw.mask & PSW_MASK_PSTATE) {
@@ -414,11 +380,6 @@
int access, fault;
access = VM_READ | VM_EXEC | VM_WRITE;
-#ifdef CONFIG_S390_EXEC_PROTECT
- if ((regs->psw.mask & PSW_MASK_ASC) == PSW_ASC_SECONDARY &&
- (trans_exc_code & 3) == 0)
- access = VM_EXEC;
-#endif
fault = do_exception(regs, access, trans_exc_code);
if (unlikely(fault))
do_fault_error(regs, pgm_int_code & 255, trans_exc_code, fault);
@@ -491,22 +452,28 @@
__setup("nopfault", nopfault);
-typedef struct {
- __u16 refdiagc;
- __u16 reffcode;
- __u16 refdwlen;
- __u16 refversn;
- __u64 refgaddr;
- __u64 refselmk;
- __u64 refcmpmk;
- __u64 reserved;
-} __attribute__ ((packed, aligned(8))) pfault_refbk_t;
+struct pfault_refbk {
+ u16 refdiagc;
+ u16 reffcode;
+ u16 refdwlen;
+ u16 refversn;
+ u64 refgaddr;
+ u64 refselmk;
+ u64 refcmpmk;
+ u64 reserved;
+} __attribute__ ((packed, aligned(8)));
int pfault_init(void)
{
- pfault_refbk_t refbk =
- { 0x258, 0, 5, 2, __LC_CURRENT, 1ULL << 48, 1ULL << 48,
- __PF_RES_FIELD };
+ struct pfault_refbk refbk = {
+ .refdiagc = 0x258,
+ .reffcode = 0,
+ .refdwlen = 5,
+ .refversn = 2,
+ .refgaddr = __LC_CURRENT_PID,
+ .refselmk = 1ULL << 48,
+ .refcmpmk = 1ULL << 48,
+ .reserved = __PF_RES_FIELD };
int rc;
if (!MACHINE_IS_VM || pfault_disable)
@@ -524,8 +491,12 @@
void pfault_fini(void)
{
- pfault_refbk_t refbk =
- { 0x258, 1, 5, 2, 0ULL, 0ULL, 0ULL, 0ULL };
+ struct pfault_refbk refbk = {
+ .refdiagc = 0x258,
+ .reffcode = 1,
+ .refdwlen = 5,
+ .refversn = 2,
+ };
if (!MACHINE_IS_VM || pfault_disable)
return;
@@ -537,11 +508,15 @@
: : "a" (&refbk), "m" (refbk) : "cc");
}
+static DEFINE_SPINLOCK(pfault_lock);
+static LIST_HEAD(pfault_list);
+
static void pfault_interrupt(unsigned int ext_int_code,
unsigned int param32, unsigned long param64)
{
struct task_struct *tsk;
__u16 subcode;
+ pid_t pid;
/*
* Get the external interruption subcode & pfault
@@ -553,44 +528,79 @@
if ((subcode & 0xff00) != __SUBCODE_MASK)
return;
kstat_cpu(smp_processor_id()).irqs[EXTINT_PFL]++;
-
- /*
- * Get the token (= address of the task structure of the affected task).
- */
-#ifdef CONFIG_64BIT
- tsk = (struct task_struct *) param64;
-#else
- tsk = (struct task_struct *) param32;
-#endif
-
+ if (subcode & 0x0080) {
+ /* Get the token (= pid of the affected task). */
+ pid = sizeof(void *) == 4 ? param32 : param64;
+ rcu_read_lock();
+ tsk = find_task_by_pid_ns(pid, &init_pid_ns);
+ if (tsk)
+ get_task_struct(tsk);
+ rcu_read_unlock();
+ if (!tsk)
+ return;
+ } else {
+ tsk = current;
+ }
+ spin_lock(&pfault_lock);
if (subcode & 0x0080) {
/* signal bit is set -> a page has been swapped in by VM */
- if (xchg(&tsk->thread.pfault_wait, -1) != 0) {
+ if (tsk->thread.pfault_wait == 1) {
/* Initial interrupt was faster than the completion
* interrupt. pfault_wait is valid. Set pfault_wait
* back to zero and wake up the process. This can
* safely be done because the task is still sleeping
* and can't produce new pfaults. */
tsk->thread.pfault_wait = 0;
+ list_del(&tsk->thread.list);
wake_up_process(tsk);
- put_task_struct(tsk);
+ } else {
+ /* Completion interrupt was faster than initial
+ * interrupt. Set pfault_wait to -1 so the initial
+ * interrupt doesn't put the task to sleep. */
+ tsk->thread.pfault_wait = -1;
}
+ put_task_struct(tsk);
} else {
/* signal bit not set -> a real page is missing. */
- get_task_struct(tsk);
- set_task_state(tsk, TASK_UNINTERRUPTIBLE);
- if (xchg(&tsk->thread.pfault_wait, 1) != 0) {
+ if (tsk->thread.pfault_wait == -1) {
/* Completion interrupt was faster than the initial
- * interrupt (swapped in a -1 for pfault_wait). Set
- * pfault_wait back to zero and exit. This can be
- * done safely because tsk is running in kernel
- * mode and can't produce new pfaults. */
+ * interrupt (pfault_wait == -1). Set pfault_wait
+ * back to zero and exit. */
tsk->thread.pfault_wait = 0;
- set_task_state(tsk, TASK_RUNNING);
- put_task_struct(tsk);
- } else
+ } else {
+ /* Initial interrupt arrived before completion
+ * interrupt. Let the task sleep. */
+ tsk->thread.pfault_wait = 1;
+ list_add(&tsk->thread.list, &pfault_list);
+ set_task_state(tsk, TASK_UNINTERRUPTIBLE);
set_tsk_need_resched(tsk);
+ }
}
+ spin_unlock(&pfault_lock);
+}
+
+static int __cpuinit pfault_cpu_notify(struct notifier_block *self,
+ unsigned long action, void *hcpu)
+{
+ struct thread_struct *thread, *next;
+ struct task_struct *tsk;
+
+ switch (action) {
+ case CPU_DEAD:
+ case CPU_DEAD_FROZEN:
+ spin_lock_irq(&pfault_lock);
+ list_for_each_entry_safe(thread, next, &pfault_list, list) {
+ thread->pfault_wait = 0;
+ list_del(&thread->list);
+ tsk = container_of(thread, struct task_struct, thread);
+ wake_up_process(tsk);
+ }
+ spin_unlock_irq(&pfault_lock);
+ break;
+ default:
+ break;
+ }
+ return NOTIFY_OK;
}
static int __init pfault_irq_init(void)
@@ -599,22 +609,21 @@
if (!MACHINE_IS_VM)
return 0;
- /*
- * Try to get pfault pseudo page faults going.
- */
rc = register_external_interrupt(0x2603, pfault_interrupt);
- if (rc) {
- pfault_disable = 1;
- return rc;
- }
- if (pfault_init() == 0)
- return 0;
-
- /* Tough luck, no pfault. */
- pfault_disable = 1;
- unregister_external_interrupt(0x2603, pfault_interrupt);
+ if (rc)
+ goto out_extint;
+ rc = pfault_init() == 0 ? 0 : -EOPNOTSUPP;
+ if (rc)
+ goto out_pfault;
+ hotcpu_notifier(pfault_cpu_notify, 0);
return 0;
+
+out_pfault:
+ unregister_external_interrupt(0x2603, pfault_interrupt);
+out_extint:
+ pfault_disable = 1;
+ return rc;
}
early_initcall(pfault_irq_init);
-#endif
+#endif /* CONFIG_PFAULT */
diff --git a/arch/s390/mm/hugetlbpage.c b/arch/s390/mm/hugetlbpage.c
index 639cd21..a4d856d 100644
--- a/arch/s390/mm/hugetlbpage.c
+++ b/arch/s390/mm/hugetlbpage.c
@@ -13,7 +13,6 @@
pte_t *pteptr, pte_t pteval)
{
pmd_t *pmdp = (pmd_t *) pteptr;
- pte_t shadow_pteval = pteval;
unsigned long mask;
if (!MACHINE_HAS_HPAGE) {
@@ -21,18 +20,9 @@
mask = pte_val(pteval) &
(_SEGMENT_ENTRY_INV | _SEGMENT_ENTRY_RO);
pte_val(pteval) = (_SEGMENT_ENTRY + __pa(pteptr)) | mask;
- if (mm->context.noexec) {
- pteptr += PTRS_PER_PTE;
- pte_val(shadow_pteval) =
- (_SEGMENT_ENTRY + __pa(pteptr)) | mask;
- }
}
pmd_val(*pmdp) = pte_val(pteval);
- if (mm->context.noexec) {
- pmdp = get_shadow_table(pmdp);
- pmd_val(*pmdp) = pte_val(shadow_pteval);
- }
}
int arch_prepare_hugepage(struct page *page)
diff --git a/arch/s390/mm/init.c b/arch/s390/mm/init.c
index bb40933..dfefc21 100644
--- a/arch/s390/mm/init.c
+++ b/arch/s390/mm/init.c
@@ -175,7 +175,8 @@
pmd = pmd_offset(pud, address);
pte = pte_offset_kernel(pmd, address);
if (!enable) {
- ptep_invalidate(&init_mm, address, pte);
+ __ptep_ipte(address, pte);
+ pte_val(*pte) = _PAGE_TYPE_EMPTY;
continue;
}
*pte = mk_pte_phys(address, __pgprot(_PAGE_TYPE_RW));
diff --git a/arch/s390/mm/pageattr.c b/arch/s390/mm/pageattr.c
index f05edcc..d013ed3 100644
--- a/arch/s390/mm/pageattr.c
+++ b/arch/s390/mm/pageattr.c
@@ -28,7 +28,7 @@
pte = *ptep;
pte = set(pte);
- ptep_invalidate(&init_mm, addr, ptep);
+ __ptep_ipte(addr, ptep);
*ptep = pte;
addr += PAGE_SIZE;
}
diff --git a/arch/s390/mm/pgtable.c b/arch/s390/mm/pgtable.c
index e1850c2..14c6fae 100644
--- a/arch/s390/mm/pgtable.c
+++ b/arch/s390/mm/pgtable.c
@@ -36,11 +36,9 @@
((PAGE_SIZE - sizeof(struct rcu_table_freelist)) \
/ sizeof(unsigned long))
-DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
static DEFINE_PER_CPU(struct rcu_table_freelist *, rcu_table_freelist);
static void __page_table_free(struct mm_struct *mm, unsigned long *table);
-static void __crst_table_free(struct mm_struct *mm, unsigned long *table);
static struct rcu_table_freelist *rcu_table_freelist_get(struct mm_struct *mm)
{
@@ -67,7 +65,7 @@
while (batch->pgt_index > 0)
__page_table_free(batch->mm, batch->table[--batch->pgt_index]);
while (batch->crst_index < RCU_FREELIST_SIZE)
- __crst_table_free(batch->mm, batch->table[batch->crst_index++]);
+ crst_table_free(batch->mm, batch->table[batch->crst_index++]);
free_page((unsigned long) batch);
}
@@ -125,63 +123,33 @@
}
early_param("vmalloc", parse_vmalloc);
-unsigned long *crst_table_alloc(struct mm_struct *mm, int noexec)
+unsigned long *crst_table_alloc(struct mm_struct *mm)
{
struct page *page = alloc_pages(GFP_KERNEL, ALLOC_ORDER);
if (!page)
return NULL;
- page->index = 0;
- if (noexec) {
- struct page *shadow = alloc_pages(GFP_KERNEL, ALLOC_ORDER);
- if (!shadow) {
- __free_pages(page, ALLOC_ORDER);
- return NULL;
- }
- page->index = page_to_phys(shadow);
- }
- spin_lock_bh(&mm->context.list_lock);
- list_add(&page->lru, &mm->context.crst_list);
- spin_unlock_bh(&mm->context.list_lock);
return (unsigned long *) page_to_phys(page);
}
-static void __crst_table_free(struct mm_struct *mm, unsigned long *table)
-{
- unsigned long *shadow = get_shadow_table(table);
-
- if (shadow)
- free_pages((unsigned long) shadow, ALLOC_ORDER);
- free_pages((unsigned long) table, ALLOC_ORDER);
-}
-
void crst_table_free(struct mm_struct *mm, unsigned long *table)
{
- struct page *page = virt_to_page(table);
-
- spin_lock_bh(&mm->context.list_lock);
- list_del(&page->lru);
- spin_unlock_bh(&mm->context.list_lock);
- __crst_table_free(mm, table);
+ free_pages((unsigned long) table, ALLOC_ORDER);
}
void crst_table_free_rcu(struct mm_struct *mm, unsigned long *table)
{
struct rcu_table_freelist *batch;
- struct page *page = virt_to_page(table);
- spin_lock_bh(&mm->context.list_lock);
- list_del(&page->lru);
- spin_unlock_bh(&mm->context.list_lock);
if (atomic_read(&mm->mm_users) < 2 &&
cpumask_equal(mm_cpumask(mm), cpumask_of(smp_processor_id()))) {
- __crst_table_free(mm, table);
+ crst_table_free(mm, table);
return;
}
batch = rcu_table_freelist_get(mm);
if (!batch) {
smp_call_function(smp_sync, NULL, 1);
- __crst_table_free(mm, table);
+ crst_table_free(mm, table);
return;
}
batch->table[--batch->crst_index] = table;
@@ -197,7 +165,7 @@
BUG_ON(limit > (1UL << 53));
repeat:
- table = crst_table_alloc(mm, mm->context.noexec);
+ table = crst_table_alloc(mm);
if (!table)
return -ENOMEM;
spin_lock_bh(&mm->page_table_lock);
@@ -273,7 +241,7 @@
unsigned long *table;
unsigned long bits;
- bits = (mm->context.noexec || mm->context.has_pgste) ? 3UL : 1UL;
+ bits = (mm->context.has_pgste) ? 3UL : 1UL;
spin_lock_bh(&mm->context.list_lock);
page = NULL;
if (!list_empty(&mm->context.pgtable_list)) {
@@ -329,7 +297,7 @@
struct page *page;
unsigned long bits;
- bits = (mm->context.noexec || mm->context.has_pgste) ? 3UL : 1UL;
+ bits = (mm->context.has_pgste) ? 3UL : 1UL;
bits <<= (__pa(table) & (PAGE_SIZE - 1)) / 256 / sizeof(unsigned long);
page = pfn_to_page(__pa(table) >> PAGE_SHIFT);
spin_lock_bh(&mm->context.list_lock);
@@ -366,7 +334,7 @@
page_table_free(mm, table);
return;
}
- bits = (mm->context.noexec || mm->context.has_pgste) ? 3UL : 1UL;
+ bits = (mm->context.has_pgste) ? 3UL : 1UL;
bits <<= (__pa(table) & (PAGE_SIZE - 1)) / 256 / sizeof(unsigned long);
page = pfn_to_page(__pa(table) >> PAGE_SHIFT);
spin_lock_bh(&mm->context.list_lock);
@@ -379,25 +347,6 @@
rcu_table_freelist_finish();
}
-void disable_noexec(struct mm_struct *mm, struct task_struct *tsk)
-{
- struct page *page;
-
- spin_lock_bh(&mm->context.list_lock);
- /* Free shadow region and segment tables. */
- list_for_each_entry(page, &mm->context.crst_list, lru)
- if (page->index) {
- free_pages((unsigned long) page->index, ALLOC_ORDER);
- page->index = 0;
- }
- /* "Free" second halves of page tables. */
- list_for_each_entry(page, &mm->context.pgtable_list, lru)
- page->flags &= ~SECOND_HALVES;
- spin_unlock_bh(&mm->context.list_lock);
- mm->context.noexec = 0;
- update_mm(mm, tsk);
-}
-
/*
* switch on pgstes for its userspace process (for kvm)
*/
diff --git a/arch/s390/mm/vmem.c b/arch/s390/mm/vmem.c
index 34c43f2..8c1970d 100644
--- a/arch/s390/mm/vmem.c
+++ b/arch/s390/mm/vmem.c
@@ -95,7 +95,7 @@
pu_dir = vmem_pud_alloc();
if (!pu_dir)
goto out;
- pgd_populate_kernel(&init_mm, pg_dir, pu_dir);
+ pgd_populate(&init_mm, pg_dir, pu_dir);
}
pu_dir = pud_offset(pg_dir, address);
@@ -103,7 +103,7 @@
pm_dir = vmem_pmd_alloc();
if (!pm_dir)
goto out;
- pud_populate_kernel(&init_mm, pu_dir, pm_dir);
+ pud_populate(&init_mm, pu_dir, pm_dir);
}
pte = mk_pte_phys(address, __pgprot(ro ? _PAGE_RO : 0));
@@ -123,7 +123,7 @@
pt_dir = vmem_pte_alloc();
if (!pt_dir)
goto out;
- pmd_populate_kernel(&init_mm, pm_dir, pt_dir);
+ pmd_populate(&init_mm, pm_dir, pt_dir);
}
pt_dir = pte_offset_kernel(pm_dir, address);
@@ -159,7 +159,7 @@
continue;
if (pmd_huge(*pm_dir)) {
- pmd_clear_kernel(pm_dir);
+ pmd_clear(pm_dir);
address += HPAGE_SIZE - PAGE_SIZE;
continue;
}
@@ -192,7 +192,7 @@
pu_dir = vmem_pud_alloc();
if (!pu_dir)
goto out;
- pgd_populate_kernel(&init_mm, pg_dir, pu_dir);
+ pgd_populate(&init_mm, pg_dir, pu_dir);
}
pu_dir = pud_offset(pg_dir, address);
@@ -200,7 +200,7 @@
pm_dir = vmem_pmd_alloc();
if (!pm_dir)
goto out;
- pud_populate_kernel(&init_mm, pu_dir, pm_dir);
+ pud_populate(&init_mm, pu_dir, pm_dir);
}
pm_dir = pmd_offset(pu_dir, address);
@@ -208,7 +208,7 @@
pt_dir = vmem_pte_alloc();
if (!pt_dir)
goto out;
- pmd_populate_kernel(&init_mm, pm_dir, pt_dir);
+ pmd_populate(&init_mm, pm_dir, pt_dir);
}
pt_dir = pte_offset_kernel(pm_dir, address);
diff --git a/arch/s390/oprofile/hwsampler.c b/arch/s390/oprofile/hwsampler.c
index 33cbd37..053caa0 100644
--- a/arch/s390/oprofile/hwsampler.c
+++ b/arch/s390/oprofile/hwsampler.c
@@ -5,6 +5,7 @@
* Author: Heinz Graalfs <graalfs@de.ibm.com>
*/
+#include <linux/kernel_stat.h>
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/smp.h>
@@ -674,17 +675,11 @@
static void hws_ext_handler(unsigned int ext_int_code,
unsigned int param32, unsigned long param64)
{
- int cpu;
struct hws_cpu_buffer *cb;
- cpu = smp_processor_id();
- cb = &per_cpu(sampler_cpu_buffer, cpu);
-
- atomic_xchg(
- &cb->ext_params,
- atomic_read(&cb->ext_params)
- | S390_lowcore.ext_params);
-
+ kstat_cpu(smp_processor_id()).irqs[EXTINT_CPM]++;
+ cb = &__get_cpu_var(sampler_cpu_buffer);
+ atomic_xchg(&cb->ext_params, atomic_read(&cb->ext_params) | param32);
if (hws_wq)
queue_work(hws_wq, &cb->worker);
}
@@ -764,7 +759,7 @@
if (!sdbt || !*sdbt)
return -EINVAL;
- if (ext_params & EI_IEA)
+ if (ext_params & EI_PRA)
cb->req_alert++;
if (ext_params & EI_LSDA)
@@ -1009,7 +1004,7 @@
if (hws_state != HWS_STOPPED)
goto deallocate_exit;
- smp_ctl_clear_bit(0, 5); /* set bit 58 CR0 off */
+ ctl_clear_bit(0, 5); /* set bit 58 CR0 off */
deallocate_sdbt();
hws_state = HWS_DEALLOCATED;
@@ -1123,7 +1118,7 @@
mutex_lock(&hws_sem);
if (hws_state == HWS_STOPPED) {
- smp_ctl_clear_bit(0, 5); /* set bit 58 CR0 off */
+ ctl_clear_bit(0, 5); /* set bit 58 CR0 off */
deallocate_sdbt();
}
if (hws_wq) {
@@ -1198,7 +1193,7 @@
hws_oom = 1;
hws_flush_all = 0;
/* now let them in, 1407 CPUMF external interrupts */
- smp_ctl_set_bit(0, 5); /* set CR0 bit 58 */
+ ctl_set_bit(0, 5); /* set CR0 bit 58 */
return 0;
}
diff --git a/arch/score/Kconfig.debug b/arch/score/Kconfig.debug
index 451ed54..a1f346d 100644
--- a/arch/score/Kconfig.debug
+++ b/arch/score/Kconfig.debug
@@ -16,15 +16,6 @@
other cases you can specify kernel args so that you don't have
to set them up in board prom initialization routines.
-config DEBUG_STACK_USAGE
- bool "Enable stack utilization instrumentation"
- depends on DEBUG_KERNEL
- help
- Enables the display of the minimum amount of free stack which each
- task has ever had available in the sysrq-T and sysrq-P debug output.
-
- This option will slow down process creation somewhat.
-
config RUNTIME_DEBUG
bool "Enable run-time debugging"
depends on DEBUG_KERNEL
diff --git a/arch/score/mm/init.c b/arch/score/mm/init.c
index 50fdec5..cee6bce 100644
--- a/arch/score/mm/init.c
+++ b/arch/score/mm/init.c
@@ -38,8 +38,6 @@
#include <asm/sections.h>
#include <asm/tlb.h>
-DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
-
unsigned long empty_zero_page;
EXPORT_SYMBOL_GPL(empty_zero_page);
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index bc439de..b44e377 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -21,6 +21,7 @@
select HAVE_REGS_AND_STACK_ACCESS_API
select HAVE_GENERIC_HARDIRQS
select HAVE_SPARSE_IRQ
+ select IRQ_FORCED_THREADING
select RTC_LIB
select GENERIC_ATOMIC64
select GENERIC_IRQ_SHOW
diff --git a/arch/sh/Kconfig.debug b/arch/sh/Kconfig.debug
index 1553d56..c1d5a82 100644
--- a/arch/sh/Kconfig.debug
+++ b/arch/sh/Kconfig.debug
@@ -28,15 +28,6 @@
every function call and will therefore incur a major
performance hit. Most users should say N.
-config DEBUG_STACK_USAGE
- bool "Stack utilization instrumentation"
- depends on DEBUG_KERNEL
- help
- Enables the display of the minimum amount of free stack which each
- task has ever had available in the sysrq-T and sysrq-P debug output.
-
- This option will slow down process creation somewhat.
-
config 4KSTACKS
bool "Use 4Kb for kernel stacks instead of 8Kb"
depends on DEBUG_KERNEL && (MMU || BROKEN) && !PAGE_SIZE_64KB
diff --git a/arch/sh/boards/mach-ecovec24/setup.c b/arch/sh/boards/mach-ecovec24/setup.c
index 86a0d56..bb13d0e 100644
--- a/arch/sh/boards/mach-ecovec24/setup.c
+++ b/arch/sh/boards/mach-ecovec24/setup.c
@@ -482,7 +482,7 @@
.irq = IRQ0,
};
-#if defined(CONFIG_MMC_TMIO) || defined(CONFIG_MMC_TMIO_MODULE)
+#if defined(CONFIG_MMC_SDHI) || defined(CONFIG_MMC_SDHI_MODULE)
/* SDHI0 */
static void sdhi0_set_pwr(struct platform_device *pdev, int state)
{
@@ -522,7 +522,7 @@
},
};
-#if !defined(CONFIG_MMC_SH_MMCIF)
+#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
/* SDHI1 */
static void sdhi1_set_pwr(struct platform_device *pdev, int state)
{
@@ -836,7 +836,7 @@
},
};
-#if defined(CONFIG_MMC_SH_MMCIF)
+#if defined(CONFIG_MMC_SH_MMCIF) || defined(CONFIG_MMC_SH_MMCIF_MODULE)
/* SH_MMCIF */
static void mmcif_set_pwr(struct platform_device *pdev, int state)
{
@@ -898,9 +898,9 @@
&ceu0_device,
&ceu1_device,
&keysc_device,
-#if defined(CONFIG_MMC_TMIO) || defined(CONFIG_MMC_TMIO_MODULE)
+#if defined(CONFIG_MMC_SDHI) || defined(CONFIG_MMC_SDHI_MODULE)
&sdhi0_device,
-#if !defined(CONFIG_MMC_SH_MMCIF)
+#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
&sdhi1_device,
#endif
#else
@@ -912,7 +912,7 @@
&fsi_device,
&irda_device,
&vou_device,
-#if defined(CONFIG_MMC_SH_MMCIF)
+#if defined(CONFIG_MMC_SH_MMCIF) || defined(CONFIG_MMC_SH_MMCIF_MODULE)
&sh_mmcif_device,
#endif
};
@@ -1180,7 +1180,7 @@
gpio_direction_input(GPIO_PTR5);
gpio_direction_input(GPIO_PTR6);
-#if defined(CONFIG_MMC_TMIO) || defined(CONFIG_MMC_TMIO_MODULE)
+#if defined(CONFIG_MMC_SDHI) || defined(CONFIG_MMC_SDHI_MODULE)
/* enable SDHI0 on CN11 (needs DS2.4 set to ON) */
gpio_request(GPIO_FN_SDHI0CD, NULL);
gpio_request(GPIO_FN_SDHI0WP, NULL);
@@ -1193,7 +1193,7 @@
gpio_request(GPIO_PTB6, NULL);
gpio_direction_output(GPIO_PTB6, 0);
-#if !defined(CONFIG_MMC_SH_MMCIF)
+#if !defined(CONFIG_MMC_SH_MMCIF) && !defined(CONFIG_MMC_SH_MMCIF_MODULE)
/* enable SDHI1 on CN12 (needs DS2.6,7 set to ON,OFF) */
gpio_request(GPIO_FN_SDHI1CD, NULL);
gpio_request(GPIO_FN_SDHI1WP, NULL);
@@ -1284,7 +1284,7 @@
gpio_request(GPIO_PTU5, NULL);
gpio_direction_output(GPIO_PTU5, 0);
-#if defined(CONFIG_MMC_SH_MMCIF)
+#if defined(CONFIG_MMC_SH_MMCIF) || defined(CONFIG_MMC_SH_MMCIF_MODULE)
/* enable MMCIF (needs DS2.6,7 set to OFF,ON) */
gpio_request(GPIO_FN_MMC_D7, NULL);
gpio_request(GPIO_FN_MMC_D6, NULL);
diff --git a/arch/sh/configs/ecovec24_defconfig b/arch/sh/configs/ecovec24_defconfig
index 8d13e8a..911e30c9 100644
--- a/arch/sh/configs/ecovec24_defconfig
+++ b/arch/sh/configs/ecovec24_defconfig
@@ -115,7 +115,7 @@
CONFIG_USB_FILE_STORAGE=m
CONFIG_MMC=y
CONFIG_MMC_SPI=y
-CONFIG_MMC_TMIO=y
+CONFIG_MMC_SDHI=y
CONFIG_RTC_CLASS=y
CONFIG_RTC_DRV_RS5C372=y
CONFIG_UIO=y
diff --git a/arch/sh/configs/sh7757lcr_defconfig b/arch/sh/configs/sh7757lcr_defconfig
index fa0ecf8..33ddb13 100644
--- a/arch/sh/configs/sh7757lcr_defconfig
+++ b/arch/sh/configs/sh7757lcr_defconfig
@@ -70,7 +70,7 @@
CONFIG_USB_OHCI_HCD=y
CONFIG_USB_STORAGE=y
CONFIG_MMC=y
-CONFIG_MMC_TMIO=y
+CONFIG_MMC_SDHI=y
CONFIG_MMC_SH_MMCIF=y
CONFIG_EXT2_FS=y
CONFIG_EXT3_FS=y
diff --git a/arch/sh/drivers/pci/fixups-se7751.c b/arch/sh/drivers/pci/fixups-se7751.c
index a4c7d3a..fd3e6b0 100644
--- a/arch/sh/drivers/pci/fixups-se7751.c
+++ b/arch/sh/drivers/pci/fixups-se7751.c
@@ -6,7 +6,7 @@
#include <linux/io.h>
#include "pci-sh4.h"
-int __init pcibios_map_platform_irq(u8 slot, u8 pin)
+int __init pcibios_map_platform_irq(struct pci_dev *, u8 slot, u8 pin)
{
switch (slot) {
case 0: return 13;
diff --git a/arch/sh/include/asm/stacktrace.h b/arch/sh/include/asm/stacktrace.h
index 7970182..a7e2d4d 100644
--- a/arch/sh/include/asm/stacktrace.h
+++ b/arch/sh/include/asm/stacktrace.h
@@ -10,9 +10,6 @@
/* Generic stack tracer with callbacks */
struct stacktrace_ops {
- void (*warning)(void *data, char *msg);
- /* msg must contain %s for the symbol */
- void (*warning_symbol)(void *data, char *msg, unsigned long symbol);
void (*address)(void *data, unsigned long address, int reliable);
/* On negative return stop dumping */
int (*stack)(void *data, char *name);
diff --git a/arch/sh/include/asm/tlb.h b/arch/sh/include/asm/tlb.h
index 75abb38..6c308d8 100644
--- a/arch/sh/include/asm/tlb.h
+++ b/arch/sh/include/asm/tlb.h
@@ -23,8 +23,6 @@
unsigned long start, end;
};
-DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
-
static inline void init_tlb_gather(struct mmu_gather *tlb)
{
tlb->start = TASK_SIZE;
@@ -36,17 +34,13 @@
}
}
-static inline struct mmu_gather *
-tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
+static inline void
+tlb_gather_mmu(struct mmu_gather *tlb, struct mm_struct *mm, unsigned int full_mm_flush)
{
- struct mmu_gather *tlb = &get_cpu_var(mmu_gathers);
-
tlb->mm = mm;
tlb->fullmm = full_mm_flush;
init_tlb_gather(tlb);
-
- return tlb;
}
static inline void
@@ -57,8 +51,6 @@
/* keep the page table cache within bounds */
check_pgt_cache();
-
- put_cpu_var(mmu_gathers);
}
static inline void
@@ -91,7 +83,21 @@
}
}
-#define tlb_remove_page(tlb,page) free_page_and_swap_cache(page)
+static inline void tlb_flush_mmu(struct mmu_gather *tlb)
+{
+}
+
+static inline int __tlb_remove_page(struct mmu_gather *tlb, struct page *page)
+{
+ free_page_and_swap_cache(page);
+ return 1; /* avoid calling tlb_flush_mmu */
+}
+
+static inline void tlb_remove_page(struct mmu_gather *tlb, struct page *page)
+{
+ __tlb_remove_page(tlb, page);
+}
+
#define pte_free_tlb(tlb, ptep, addr) pte_free((tlb)->mm, ptep)
#define pmd_free_tlb(tlb, pmdp, addr) pmd_free((tlb)->mm, pmdp)
#define pud_free_tlb(tlb, pudp, addr) pud_free((tlb)->mm, pudp)
diff --git a/arch/sh/include/asm/unistd_32.h b/arch/sh/include/asm/unistd_32.h
index ca7765e..bb7d270 100644
--- a/arch/sh/include/asm/unistd_32.h
+++ b/arch/sh/include/asm/unistd_32.h
@@ -373,8 +373,9 @@
#define __NR_open_by_handle_at 360
#define __NR_clock_adjtime 361
#define __NR_syncfs 362
+#define __NR_sendmmsg 363
-#define NR_syscalls 363
+#define NR_syscalls 364
#ifdef __KERNEL__
diff --git a/arch/sh/include/asm/unistd_64.h b/arch/sh/include/asm/unistd_64.h
index a694009..46327ce 100644
--- a/arch/sh/include/asm/unistd_64.h
+++ b/arch/sh/include/asm/unistd_64.h
@@ -394,10 +394,11 @@
#define __NR_open_by_handle_at 371
#define __NR_clock_adjtime 372
#define __NR_syncfs 373
+#define __NR_sendmmsg 374
#ifdef __KERNEL__
-#define NR_syscalls 374
+#define NR_syscalls 375
#define __ARCH_WANT_IPC_PARSE_VERSION
#define __ARCH_WANT_OLD_READDIR
diff --git a/arch/sh/kernel/cpu/Makefile b/arch/sh/kernel/cpu/Makefile
index d49c213..ae95935 100644
--- a/arch/sh/kernel/cpu/Makefile
+++ b/arch/sh/kernel/cpu/Makefile
@@ -17,7 +17,5 @@
obj-$(CONFIG_SH_ADC) += adc.o
obj-$(CONFIG_SH_CLK_CPG_LEGACY) += clock-cpg.o
-obj-$(CONFIG_SH_FPU) += fpu.o
-obj-$(CONFIG_SH_FPU_EMU) += fpu.o
-obj-y += irq/ init.o clock.o hwblk.o proc.o
+obj-y += irq/ init.o clock.o fpu.o hwblk.o proc.o
diff --git a/arch/sh/kernel/cpu/shmobile/pm_runtime.c b/arch/sh/kernel/cpu/shmobile/pm_runtime.c
index 22db127..64c807c 100644
--- a/arch/sh/kernel/cpu/shmobile/pm_runtime.c
+++ b/arch/sh/kernel/cpu/shmobile/pm_runtime.c
@@ -157,7 +157,7 @@
might_sleep();
/* catch misconfigured drivers not starting with resume */
- if (test_bit(PDEV_ARCHDATA_FLAG_INIT, &pdev->archdata.flags)) {
+ if (test_bit(PDEV_ARCHDATA_FLAG_INIT, &ad->flags)) {
ret = -EINVAL;
goto out;
}
@@ -170,8 +170,8 @@
/* put device on idle list */
spin_lock_irqsave(&hwblk_lock, flags);
- list_add_tail(&pdev->archdata.entry, &hwblk_idle_list);
- __set_bit(PDEV_ARCHDATA_FLAG_IDLE, &pdev->archdata.flags);
+ list_add_tail(&ad->entry, &hwblk_idle_list);
+ __set_bit(PDEV_ARCHDATA_FLAG_IDLE, &ad->flags);
spin_unlock_irqrestore(&hwblk_lock, flags);
/* increase idle count */
diff --git a/arch/sh/kernel/dumpstack.c b/arch/sh/kernel/dumpstack.c
index 6f5ad15..694158b 100644
--- a/arch/sh/kernel/dumpstack.c
+++ b/arch/sh/kernel/dumpstack.c
@@ -69,19 +69,6 @@
}
}
-static void
-print_trace_warning_symbol(void *data, char *msg, unsigned long symbol)
-{
- printk(data);
- print_symbol(msg, symbol);
- printk("\n");
-}
-
-static void print_trace_warning(void *data, char *msg)
-{
- printk("%s%s\n", (char *)data, msg);
-}
-
static int print_trace_stack(void *data, char *name)
{
printk("%s <%s> ", (char *)data, name);
@@ -98,8 +85,6 @@
}
static const struct stacktrace_ops print_trace_ops = {
- .warning = print_trace_warning,
- .warning_symbol = print_trace_warning_symbol,
.stack = print_trace_stack,
.address = print_trace_address,
};
diff --git a/arch/sh/kernel/module.c b/arch/sh/kernel/module.c
index ae0be69..19b1f88 100644
--- a/arch/sh/kernel/module.c
+++ b/arch/sh/kernel/module.c
@@ -93,6 +93,8 @@
#endif
switch (ELF32_R_TYPE(rel[i].r_info)) {
+ case R_SH_NONE:
+ break;
case R_SH_DIR32:
value = get_unaligned(location);
value += relocation;
diff --git a/arch/sh/kernel/perf_callchain.c b/arch/sh/kernel/perf_callchain.c
index d5ca1ef..cc80b61 100644
--- a/arch/sh/kernel/perf_callchain.c
+++ b/arch/sh/kernel/perf_callchain.c
@@ -14,16 +14,6 @@
#include <asm/unwinder.h>
#include <asm/ptrace.h>
-
-static void callchain_warning(void *data, char *msg)
-{
-}
-
-static void
-callchain_warning_symbol(void *data, char *msg, unsigned long symbol)
-{
-}
-
static int callchain_stack(void *data, char *name)
{
return 0;
@@ -38,8 +28,6 @@
}
static const struct stacktrace_ops callchain_ops = {
- .warning = callchain_warning,
- .warning_symbol = callchain_warning_symbol,
.stack = callchain_stack,
.address = callchain_address,
};
diff --git a/arch/sh/kernel/stacktrace.c b/arch/sh/kernel/stacktrace.c
index c2e45c4..bf989e0 100644
--- a/arch/sh/kernel/stacktrace.c
+++ b/arch/sh/kernel/stacktrace.c
@@ -17,15 +17,6 @@
#include <asm/ptrace.h>
#include <asm/stacktrace.h>
-static void save_stack_warning(void *data, char *msg)
-{
-}
-
-static void
-save_stack_warning_symbol(void *data, char *msg, unsigned long symbol)
-{
-}
-
static int save_stack_stack(void *data, char *name)
{
return 0;
@@ -51,8 +42,6 @@
}
static const struct stacktrace_ops save_stack_ops = {
- .warning = save_stack_warning,
- .warning_symbol = save_stack_warning_symbol,
.stack = save_stack_stack,
.address = save_stack_address,
};
@@ -88,8 +77,6 @@
}
static const struct stacktrace_ops save_stack_ops_nosched = {
- .warning = save_stack_warning,
- .warning_symbol = save_stack_warning_symbol,
.stack = save_stack_stack,
.address = save_stack_address_nosched,
};
diff --git a/arch/sh/kernel/syscalls_32.S b/arch/sh/kernel/syscalls_32.S
index 030966a..7c486f3 100644
--- a/arch/sh/kernel/syscalls_32.S
+++ b/arch/sh/kernel/syscalls_32.S
@@ -380,3 +380,4 @@
.long sys_open_by_handle_at /* 360 */
.long sys_clock_adjtime
.long sys_syncfs
+ .long sys_sendmmsg
diff --git a/arch/sh/kernel/syscalls_64.S b/arch/sh/kernel/syscalls_64.S
index ca0a614..ba1a737a 100644
--- a/arch/sh/kernel/syscalls_64.S
+++ b/arch/sh/kernel/syscalls_64.S
@@ -400,3 +400,4 @@
.long sys_open_by_handle_at
.long sys_clock_adjtime
.long sys_syncfs
+ .long sys_sendmmsg
diff --git a/arch/sh/kernel/vmlinux.lds.S b/arch/sh/kernel/vmlinux.lds.S
index af4d461..731c10c 100644
--- a/arch/sh/kernel/vmlinux.lds.S
+++ b/arch/sh/kernel/vmlinux.lds.S
@@ -66,7 +66,7 @@
__machvec_end = .;
}
- PERCPU(L1_CACHE_BYTES, PAGE_SIZE)
+ PERCPU_SECTION(L1_CACHE_BYTES)
/*
* .exit.text is discarded at runtime, not link time, to deal with
diff --git a/arch/sh/mm/init.c b/arch/sh/mm/init.c
index 0d3f912..58a93fb3 100644
--- a/arch/sh/mm/init.c
+++ b/arch/sh/mm/init.c
@@ -28,7 +28,6 @@
#include <asm/cache.h>
#include <asm/sizes.h>
-DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
pgd_t swapper_pg_dir[PTRS_PER_PGD];
void __init generic_mem_init(void)
diff --git a/arch/sh/oprofile/backtrace.c b/arch/sh/oprofile/backtrace.c
index 37f3a75..9c88dcd 100644
--- a/arch/sh/oprofile/backtrace.c
+++ b/arch/sh/oprofile/backtrace.c
@@ -23,17 +23,6 @@
#include <asm/sections.h>
#include <asm/stacktrace.h>
-static void backtrace_warning_symbol(void *data, char *msg,
- unsigned long symbol)
-{
- /* Ignore warnings */
-}
-
-static void backtrace_warning(void *data, char *msg)
-{
- /* Ignore warnings */
-}
-
static int backtrace_stack(void *data, char *name)
{
/* Yes, we want all stacks */
@@ -49,8 +38,6 @@
}
static struct stacktrace_ops backtrace_ops = {
- .warning = backtrace_warning,
- .warning_symbol = backtrace_warning_symbol,
.stack = backtrace_stack,
.address = backtrace_address,
};
diff --git a/arch/sparc/Kconfig.debug b/arch/sparc/Kconfig.debug
index d9a795e..6db35fb 100644
--- a/arch/sparc/Kconfig.debug
+++ b/arch/sparc/Kconfig.debug
@@ -6,15 +6,6 @@
source "lib/Kconfig.debug"
-config DEBUG_STACK_USAGE
- bool "Enable stack utilization instrumentation"
- depends on DEBUG_KERNEL
- help
- Enables the display of the minimum amount of free stack which each
- task has ever had available in the sysrq-T and sysrq-P debug output.
-
- This option will slow down process creation somewhat.
-
config DEBUG_DCFLUSH
bool "D-cache flush debugging"
depends on SPARC64 && DEBUG_KERNEL
diff --git a/arch/sparc/include/asm/pgalloc_64.h b/arch/sparc/include/asm/pgalloc_64.h
index 5bdfa2c..4e5e087 100644
--- a/arch/sparc/include/asm/pgalloc_64.h
+++ b/arch/sparc/include/asm/pgalloc_64.h
@@ -78,4 +78,7 @@
quicklist_trim(0, NULL, 25, 16);
}
+#define __pte_free_tlb(tlb, pte, addr) pte_free((tlb)->mm, pte)
+#define __pmd_free_tlb(tlb, pmd, addr) pmd_free((tlb)->mm, pmd)
+
#endif /* _SPARC64_PGALLOC_H */
diff --git a/arch/sparc/include/asm/pgtable_64.h b/arch/sparc/include/asm/pgtable_64.h
index b77128c..1e03c5a 100644
--- a/arch/sparc/include/asm/pgtable_64.h
+++ b/arch/sparc/include/asm/pgtable_64.h
@@ -655,9 +655,11 @@
#define pte_unmap(pte) do { } while (0)
/* Actual page table PTE updates. */
-extern void tlb_batch_add(struct mm_struct *mm, unsigned long vaddr, pte_t *ptep, pte_t orig);
+extern void tlb_batch_add(struct mm_struct *mm, unsigned long vaddr,
+ pte_t *ptep, pte_t orig, int fullmm);
-static inline void set_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep, pte_t pte)
+static inline void __set_pte_at(struct mm_struct *mm, unsigned long addr,
+ pte_t *ptep, pte_t pte, int fullmm)
{
pte_t orig = *ptep;
@@ -670,12 +672,19 @@
* and SUN4V pte layout, so this inline test is fine.
*/
if (likely(mm != &init_mm) && (pte_val(orig) & _PAGE_VALID))
- tlb_batch_add(mm, addr, ptep, orig);
+ tlb_batch_add(mm, addr, ptep, orig, fullmm);
}
+#define set_pte_at(mm,addr,ptep,pte) \
+ __set_pte_at((mm), (addr), (ptep), (pte), 0)
+
#define pte_clear(mm,addr,ptep) \
set_pte_at((mm), (addr), (ptep), __pte(0UL))
+#define __HAVE_ARCH_PTE_CLEAR_NOT_PRESENT_FULL
+#define pte_clear_not_present_full(mm,addr,ptep,fullmm) \
+ __set_pte_at((mm), (addr), (ptep), __pte(0UL), (fullmm))
+
#ifdef DCACHE_ALIASING_POSSIBLE
#define __HAVE_ARCH_MOVE_PTE
#define move_pte(pte, prot, old_addr, new_addr) \
diff --git a/arch/sparc/include/asm/tlb_64.h b/arch/sparc/include/asm/tlb_64.h
index dca406b..190e189 100644
--- a/arch/sparc/include/asm/tlb_64.h
+++ b/arch/sparc/include/asm/tlb_64.h
@@ -7,66 +7,11 @@
#include <asm/tlbflush.h>
#include <asm/mmu_context.h>
-#define TLB_BATCH_NR 192
-
-/*
- * For UP we don't need to worry about TLB flush
- * and page free order so much..
- */
-#ifdef CONFIG_SMP
- #define FREE_PTE_NR 506
- #define tlb_fast_mode(bp) ((bp)->pages_nr == ~0U)
-#else
- #define FREE_PTE_NR 1
- #define tlb_fast_mode(bp) 1
-#endif
-
-struct mmu_gather {
- struct mm_struct *mm;
- unsigned int pages_nr;
- unsigned int need_flush;
- unsigned int fullmm;
- unsigned int tlb_nr;
- unsigned long vaddrs[TLB_BATCH_NR];
- struct page *pages[FREE_PTE_NR];
-};
-
-DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
-
#ifdef CONFIG_SMP
extern void smp_flush_tlb_pending(struct mm_struct *,
unsigned long, unsigned long *);
#endif
-extern void __flush_tlb_pending(unsigned long, unsigned long, unsigned long *);
-extern void flush_tlb_pending(void);
-
-static inline struct mmu_gather *tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
-{
- struct mmu_gather *mp = &get_cpu_var(mmu_gathers);
-
- BUG_ON(mp->tlb_nr);
-
- mp->mm = mm;
- mp->pages_nr = num_online_cpus() > 1 ? 0U : ~0U;
- mp->fullmm = full_mm_flush;
-
- return mp;
-}
-
-
-static inline void tlb_flush_mmu(struct mmu_gather *mp)
-{
- if (!mp->fullmm)
- flush_tlb_pending();
- if (mp->need_flush) {
- free_pages_and_swap_cache(mp->pages, mp->pages_nr);
- mp->pages_nr = 0;
- mp->need_flush = 0;
- }
-
-}
-
#ifdef CONFIG_SMP
extern void smp_flush_tlb_mm(struct mm_struct *mm);
#define do_flush_tlb_mm(mm) smp_flush_tlb_mm(mm)
@@ -74,38 +19,14 @@
#define do_flush_tlb_mm(mm) __flush_tlb_mm(CTX_HWBITS(mm->context), SECONDARY_CONTEXT)
#endif
-static inline void tlb_finish_mmu(struct mmu_gather *mp, unsigned long start, unsigned long end)
-{
- tlb_flush_mmu(mp);
+extern void __flush_tlb_pending(unsigned long, unsigned long, unsigned long *);
+extern void flush_tlb_pending(void);
- if (mp->fullmm)
- mp->fullmm = 0;
-
- /* keep the page table cache within bounds */
- check_pgt_cache();
-
- put_cpu_var(mmu_gathers);
-}
-
-static inline void tlb_remove_page(struct mmu_gather *mp, struct page *page)
-{
- if (tlb_fast_mode(mp)) {
- free_page_and_swap_cache(page);
- return;
- }
- mp->need_flush = 1;
- mp->pages[mp->pages_nr++] = page;
- if (mp->pages_nr >= FREE_PTE_NR)
- tlb_flush_mmu(mp);
-}
-
-#define tlb_remove_tlb_entry(mp,ptep,addr) do { } while (0)
-#define pte_free_tlb(mp, ptepage, addr) pte_free((mp)->mm, ptepage)
-#define pmd_free_tlb(mp, pmdp, addr) pmd_free((mp)->mm, pmdp)
-#define pud_free_tlb(tlb,pudp, addr) __pud_free_tlb(tlb,pudp,addr)
-
-#define tlb_migrate_finish(mm) do { } while (0)
#define tlb_start_vma(tlb, vma) do { } while (0)
#define tlb_end_vma(tlb, vma) do { } while (0)
+#define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0)
+#define tlb_flush(tlb) flush_tlb_pending()
+
+#include <asm-generic/tlb.h>
#endif /* _SPARC64_TLB_H */
diff --git a/arch/sparc/include/asm/tlbflush_64.h b/arch/sparc/include/asm/tlbflush_64.h
index fbb675d..2ef4634 100644
--- a/arch/sparc/include/asm/tlbflush_64.h
+++ b/arch/sparc/include/asm/tlbflush_64.h
@@ -5,9 +5,17 @@
#include <asm/mmu_context.h>
/* TSB flush operations. */
-struct mmu_gather;
+
+#define TLB_BATCH_NR 192
+
+struct tlb_batch {
+ struct mm_struct *mm;
+ unsigned long tlb_nr;
+ unsigned long vaddrs[TLB_BATCH_NR];
+};
+
extern void flush_tsb_kernel_range(unsigned long start, unsigned long end);
-extern void flush_tsb_user(struct mmu_gather *mp);
+extern void flush_tsb_user(struct tlb_batch *tb);
/* TLB flush operations. */
diff --git a/arch/sparc/kernel/setup_32.c b/arch/sparc/kernel/setup_32.c
index 3609bde..3249d3f 100644
--- a/arch/sparc/kernel/setup_32.c
+++ b/arch/sparc/kernel/setup_32.c
@@ -82,7 +82,7 @@
"nop\n\t" : : "r" (&trapbase));
prom_printf("PROM SYNC COMMAND...\n");
- show_free_areas();
+ show_free_areas(0);
if(current->pid != 0) {
local_irq_enable();
sys_sync();
diff --git a/arch/sparc/kernel/vmlinux.lds.S b/arch/sparc/kernel/vmlinux.lds.S
index 92b557a..c022075 100644
--- a/arch/sparc/kernel/vmlinux.lds.S
+++ b/arch/sparc/kernel/vmlinux.lds.S
@@ -108,7 +108,7 @@
__sun4v_2insn_patch_end = .;
}
- PERCPU(SMP_CACHE_BYTES, PAGE_SIZE)
+ PERCPU_SECTION(SMP_CACHE_BYTES)
. = ALIGN(PAGE_SIZE);
__init_end = .;
diff --git a/arch/sparc/mm/init_32.c b/arch/sparc/mm/init_32.c
index 4c31e2b..ca21732 100644
--- a/arch/sparc/mm/init_32.c
+++ b/arch/sparc/mm/init_32.c
@@ -37,8 +37,6 @@
#include <asm/prom.h>
#include <asm/leon.h>
-DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
-
unsigned long *sparc_valid_addr_bitmap;
EXPORT_SYMBOL(sparc_valid_addr_bitmap);
@@ -78,7 +76,7 @@
void show_mem(unsigned int filter)
{
printk("Mem-info:\n");
- show_free_areas();
+ show_free_areas(filter);
printk("Free swap: %6ldkB\n",
nr_swap_pages << (PAGE_SHIFT-10));
printk("%ld pages of RAM\n", totalram_pages);
diff --git a/arch/sparc/mm/tlb.c b/arch/sparc/mm/tlb.c
index d8f21e2..b1f279c 100644
--- a/arch/sparc/mm/tlb.c
+++ b/arch/sparc/mm/tlb.c
@@ -19,33 +19,34 @@
/* Heavily inspired by the ppc64 code. */
-DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
+static DEFINE_PER_CPU(struct tlb_batch, tlb_batch);
void flush_tlb_pending(void)
{
- struct mmu_gather *mp = &get_cpu_var(mmu_gathers);
+ struct tlb_batch *tb = &get_cpu_var(tlb_batch);
- if (mp->tlb_nr) {
- flush_tsb_user(mp);
+ if (tb->tlb_nr) {
+ flush_tsb_user(tb);
- if (CTX_VALID(mp->mm->context)) {
+ if (CTX_VALID(tb->mm->context)) {
#ifdef CONFIG_SMP
- smp_flush_tlb_pending(mp->mm, mp->tlb_nr,
- &mp->vaddrs[0]);
+ smp_flush_tlb_pending(tb->mm, tb->tlb_nr,
+ &tb->vaddrs[0]);
#else
- __flush_tlb_pending(CTX_HWBITS(mp->mm->context),
- mp->tlb_nr, &mp->vaddrs[0]);
+ __flush_tlb_pending(CTX_HWBITS(tb->mm->context),
+ tb->tlb_nr, &tb->vaddrs[0]);
#endif
}
- mp->tlb_nr = 0;
+ tb->tlb_nr = 0;
}
- put_cpu_var(mmu_gathers);
+ put_cpu_var(tlb_batch);
}
-void tlb_batch_add(struct mm_struct *mm, unsigned long vaddr, pte_t *ptep, pte_t orig)
+void tlb_batch_add(struct mm_struct *mm, unsigned long vaddr,
+ pte_t *ptep, pte_t orig, int fullmm)
{
- struct mmu_gather *mp = &__get_cpu_var(mmu_gathers);
+ struct tlb_batch *tb = &get_cpu_var(tlb_batch);
unsigned long nr;
vaddr &= PAGE_MASK;
@@ -77,21 +78,25 @@
no_cache_flush:
- if (mp->fullmm)
+ if (fullmm) {
+ put_cpu_var(tlb_batch);
return;
+ }
- nr = mp->tlb_nr;
+ nr = tb->tlb_nr;
- if (unlikely(nr != 0 && mm != mp->mm)) {
+ if (unlikely(nr != 0 && mm != tb->mm)) {
flush_tlb_pending();
nr = 0;
}
if (nr == 0)
- mp->mm = mm;
+ tb->mm = mm;
- mp->vaddrs[nr] = vaddr;
- mp->tlb_nr = ++nr;
+ tb->vaddrs[nr] = vaddr;
+ tb->tlb_nr = ++nr;
if (nr >= TLB_BATCH_NR)
flush_tlb_pending();
+
+ put_cpu_var(tlb_batch);
}
diff --git a/arch/sparc/mm/tsb.c b/arch/sparc/mm/tsb.c
index 101d7c8..9484615 100644
--- a/arch/sparc/mm/tsb.c
+++ b/arch/sparc/mm/tsb.c
@@ -47,12 +47,13 @@
}
}
-static void __flush_tsb_one(struct mmu_gather *mp, unsigned long hash_shift, unsigned long tsb, unsigned long nentries)
+static void __flush_tsb_one(struct tlb_batch *tb, unsigned long hash_shift,
+ unsigned long tsb, unsigned long nentries)
{
unsigned long i;
- for (i = 0; i < mp->tlb_nr; i++) {
- unsigned long v = mp->vaddrs[i];
+ for (i = 0; i < tb->tlb_nr; i++) {
+ unsigned long v = tb->vaddrs[i];
unsigned long tag, ent, hash;
v &= ~0x1UL;
@@ -65,9 +66,9 @@
}
}
-void flush_tsb_user(struct mmu_gather *mp)
+void flush_tsb_user(struct tlb_batch *tb)
{
- struct mm_struct *mm = mp->mm;
+ struct mm_struct *mm = tb->mm;
unsigned long nentries, base, flags;
spin_lock_irqsave(&mm->context.lock, flags);
@@ -76,7 +77,7 @@
nentries = mm->context.tsb_block[MM_TSB_BASE].tsb_nentries;
if (tlb_type == cheetah_plus || tlb_type == hypervisor)
base = __pa(base);
- __flush_tsb_one(mp, PAGE_SHIFT, base, nentries);
+ __flush_tsb_one(tb, PAGE_SHIFT, base, nentries);
#ifdef CONFIG_HUGETLB_PAGE
if (mm->context.tsb_block[MM_TSB_HUGE].tsb) {
@@ -84,7 +85,7 @@
nentries = mm->context.tsb_block[MM_TSB_HUGE].tsb_nentries;
if (tlb_type == cheetah_plus || tlb_type == hypervisor)
base = __pa(base);
- __flush_tsb_one(mp, HPAGE_SHIFT, base, nentries);
+ __flush_tsb_one(tb, HPAGE_SHIFT, base, nentries);
}
#endif
spin_unlock_irqrestore(&mm->context.lock, flags);
diff --git a/arch/tile/Kconfig b/arch/tile/Kconfig
index e32b0c2..635e1bf 100644
--- a/arch/tile/Kconfig
+++ b/arch/tile/Kconfig
@@ -339,6 +339,14 @@
source "drivers/pci/Kconfig"
+config HOTPLUG
+ bool "Support for hot-pluggable devices"
+ ---help---
+ Say Y here if you want to plug devices into your computer while
+ the system is running, and be able to use them quickly. In many
+ cases, the devices can likewise be unplugged at any time too.
+ One well-known example of this is USB.
+
source "drivers/pci/hotplug/Kconfig"
endmenu
diff --git a/arch/tile/Kconfig.debug b/arch/tile/Kconfig.debug
index 9bc161a..ddbfc33 100644
--- a/arch/tile/Kconfig.debug
+++ b/arch/tile/Kconfig.debug
@@ -21,15 +21,6 @@
This option will cause messages to be printed if free stack space
drops below a certain limit.
-config DEBUG_STACK_USAGE
- bool "Stack utilization instrumentation"
- depends on DEBUG_KERNEL
- help
- Enables the display of the minimum amount of free stack which each
- task has ever had available in the sysrq-T and sysrq-P debug output.
-
- This option will slow down process creation somewhat.
-
config DEBUG_EXTRA_FLAGS
string "Additional compiler arguments when building with '-g'"
depends on DEBUG_INFO
diff --git a/arch/tile/configs/tile_defconfig b/arch/tile/configs/tile_defconfig
deleted file mode 100644
index 0fe54445..0000000
--- a/arch/tile/configs/tile_defconfig
+++ /dev/null
@@ -1,71 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-# CONFIG_SWAP is not set
-CONFIG_SYSVIPC=y
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_INITRAMFS_SOURCE="usr/contents.txt"
-CONFIG_EXPERT=y
-# CONFIG_COMPAT_BRK is not set
-CONFIG_PROFILING=y
-CONFIG_MODULES=y
-CONFIG_MODULE_UNLOAD=y
-# CONFIG_BLK_DEV_BSG is not set
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
-CONFIG_HZ_100=y
-CONFIG_NET=y
-CONFIG_PACKET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_MULTICAST=y
-# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
-# CONFIG_INET_XFRM_MODE_TUNNEL is not set
-# CONFIG_INET_LRO is not set
-# CONFIG_INET_DIAG is not set
-CONFIG_IPV6=y
-# CONFIG_WIRELESS is not set
-CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
-CONFIG_SCSI=y
-CONFIG_BLK_DEV_SD=y
-CONFIG_SCSI_CONSTANTS=y
-CONFIG_SCSI_LOGGING=y
-CONFIG_NETDEVICES=y
-CONFIG_TUN=y
-# CONFIG_NETDEV_10000 is not set
-# CONFIG_WLAN is not set
-# CONFIG_INPUT_MOUSEDEV is not set
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_SERIO is not set
-# CONFIG_VT is not set
-# CONFIG_LEGACY_PTYS is not set
-# CONFIG_HW_RANDOM is not set
-CONFIG_WATCHDOG=y
-CONFIG_WATCHDOG_NOWAYOUT=y
-# CONFIG_HID_SUPPORT is not set
-CONFIG_RTC_CLASS=y
-# CONFIG_RTC_INTF_SYSFS is not set
-# CONFIG_RTC_INTF_PROC is not set
-CONFIG_EXT2_FS=y
-CONFIG_EXT3_FS=y
-# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
-CONFIG_FUSE_FS=y
-CONFIG_MSDOS_FS=y
-CONFIG_VFAT_FS=m
-CONFIG_TMPFS=y
-CONFIG_HUGETLBFS=y
-CONFIG_NFS_FS=m
-CONFIG_NFS_V3=y
-CONFIG_NLS_CODEPAGE_437=y
-CONFIG_NLS_ISO8859_1=y
-CONFIG_FRAME_WARN=2048
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DETECT_HUNG_TASK=y
-CONFIG_DEBUG_SPINLOCK_SLEEP=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_VM=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_DEBUG_STACKOVERFLOW=y
-CONFIG_DEBUG_EXTRA_FLAGS="-femit-struct-debug-baseonly"
diff --git a/arch/tile/configs/tilegx_defconfig b/arch/tile/configs/tilegx_defconfig
new file mode 100644
index 0000000..09f1c7f
--- /dev/null
+++ b/arch/tile/configs/tilegx_defconfig
@@ -0,0 +1,1833 @@
+#
+# Automatically generated make config: don't edit
+# Linux/tilegx 2.6.39-rc5 Kernel Configuration
+# Wed May 4 11:08:04 2011
+#
+CONFIG_TILE=y
+CONFIG_MMU=y
+CONFIG_GENERIC_CSUM=y
+CONFIG_SEMAPHORE_SLEEPERS=y
+CONFIG_HAVE_ARCH_ALLOC_REMAP=y
+CONFIG_HAVE_SETUP_PER_CPU_AREA=y
+CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y
+CONFIG_SYS_SUPPORTS_HUGETLBFS=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_DEFAULT_MIGRATION_COST=10000000
+CONFIG_ARCH_SUPPORTS_OPTIMIZED_INLINING=y
+CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
+CONFIG_ARCH_DISCONTIGMEM_DEFAULT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_STRICT_DEVMEM=y
+CONFIG_SMP=y
+# CONFIG_DEBUG_COPY_FROM_USER is not set
+CONFIG_HVC_TILE=y
+CONFIG_TILEGX=y
+CONFIG_64BIT=y
+CONFIG_ARCH_DEFCONFIG="arch/tile/configs/tilegx_defconfig"
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_CROSS_COMPILE=""
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_POSIX_MQUEUE_SYSCTL=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+# CONFIG_FHANDLE is not set
+CONFIG_TASKSTATS=y
+CONFIG_TASK_DELAY_ACCT=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_AUDIT=y
+CONFIG_HAVE_GENERIC_HARDIRQS=y
+
+#
+# IRQ subsystem
+#
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_PENDING_IRQ=y
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=64
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_RCU_FAST_NO_HZ is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=19
+CONFIG_CGROUPS=y
+CONFIG_CGROUP_DEBUG=y
+CONFIG_CGROUP_NS=y
+# CONFIG_CGROUP_FREEZER is not set
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CPUSETS=y
+CONFIG_PROC_PID_CPUSET=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RESOURCE_COUNTERS=y
+CONFIG_CGROUP_MEM_RES_CTLR=y
+CONFIG_CGROUP_MEM_RES_CTLR_SWAP=y
+CONFIG_CGROUP_MEM_RES_CTLR_SWAP_ENABLED=y
+CONFIG_CGROUP_SCHED=y
+CONFIG_FAIR_GROUP_SCHED=y
+CONFIG_RT_GROUP_SCHED=y
+CONFIG_BLK_CGROUP=y
+# CONFIG_DEBUG_BLK_CGROUP is not set
+CONFIG_NAMESPACES=y
+CONFIG_UTS_NS=y
+CONFIG_IPC_NS=y
+CONFIG_USER_NS=y
+CONFIG_PID_NS=y
+CONFIG_NET_NS=y
+# CONFIG_SCHED_AUTOGROUP is not set
+CONFIG_MM_OWNER=y
+# CONFIG_SYSFS_DEPRECATED is not set
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE="usr/contents.txt"
+CONFIG_INITRAMFS_ROOT_UID=0
+CONFIG_INITRAMFS_ROOT_GID=0
+CONFIG_RD_GZIP=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+# CONFIG_RD_XZ is not set
+# CONFIG_RD_LZO is not set
+CONFIG_INITRAMFS_COMPRESSION_NONE=y
+# CONFIG_INITRAMFS_COMPRESSION_GZIP is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EXPERT=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_EMBEDDED=y
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_PCI_QUIRKS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_COMPAT_BRK is not set
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+CONFIG_USE_GENERIC_SMP_HELPERS=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_GCOV_KERNEL is not set
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_STOP_MACHINE=y
+CONFIG_BLOCK=y
+CONFIG_BLK_DEV_BSG=y
+CONFIG_BLK_DEV_INTEGRITY=y
+# CONFIG_BLK_DEV_THROTTLING is not set
+CONFIG_BLOCK_COMPAT=y
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+CONFIG_IOSCHED_DEADLINE=y
+CONFIG_IOSCHED_CFQ=y
+CONFIG_CFQ_GROUP_IOSCHED=y
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+CONFIG_PADATA=y
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+CONFIG_INLINE_SPIN_UNLOCK=y
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+CONFIG_INLINE_READ_UNLOCK=y
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+CONFIG_INLINE_READ_UNLOCK_IRQ=y
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+CONFIG_INLINE_WRITE_UNLOCK=y
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+
+#
+# Tilera-specific configuration
+#
+CONFIG_NR_CPUS=100
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_HZ_100=y
+# CONFIG_HZ_250 is not set
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=100
+CONFIG_SCHED_HRTICK=y
+# CONFIG_KEXEC is not set
+CONFIG_COMPAT=y
+CONFIG_SYSVIPC_COMPAT=y
+# CONFIG_HIGHMEM is not set
+CONFIG_NUMA=y
+CONFIG_NODES_SHIFT=2
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_DISCONTIGMEM_MANUAL=y
+CONFIG_DISCONTIGMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_NEED_MULTIPLE_NODES=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_COMPACTION is not set
+CONFIG_MIGRATION=y
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+# CONFIG_CMDLINE_BOOL is not set
+CONFIG_VMALLOC_RESERVE=0x1000000
+CONFIG_HARDWALL=y
+CONFIG_KERNEL_PL=1
+
+#
+# Bus options
+#
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+# CONFIG_NO_IOMEM is not set
+# CONFIG_NO_IOPORT is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+CONFIG_PCI_DEBUG=y
+# CONFIG_PCI_STUB is not set
+# CONFIG_PCI_IOV is not set
+# CONFIG_HOTPLUG_PCI is not set
+
+#
+# Executable file formats
+#
+CONFIG_KCORE_ELF=y
+CONFIG_BINFMT_ELF=y
+CONFIG_COMPAT_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_HAVE_AOUT is not set
+CONFIG_BINFMT_MISC=y
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=y
+CONFIG_XFRM_SUB_POLICY=y
+CONFIG_XFRM_MIGRATE=y
+CONFIG_XFRM_STATISTICS=y
+CONFIG_XFRM_IPCOMP=m
+CONFIG_NET_KEY=m
+CONFIG_NET_KEY_MIGRATE=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+# CONFIG_IP_FIB_TRIE_STATS is not set
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_ROUTE_CLASSID=y
+# CONFIG_IP_PNP is not set
+CONFIG_NET_IPIP=m
+# CONFIG_NET_IPGRE_DEMUX is not set
+CONFIG_IP_MROUTE=y
+# CONFIG_IP_MROUTE_MULTIPLE_TABLES is not set
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
+CONFIG_INET_IPCOMP=m
+CONFIG_INET_XFRM_TUNNEL=m
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=m
+CONFIG_INET_XFRM_MODE_TUNNEL=m
+CONFIG_INET_XFRM_MODE_BEET=m
+CONFIG_INET_LRO=y
+CONFIG_INET_DIAG=m
+CONFIG_INET_TCP_DIAG=m
+CONFIG_TCP_CONG_ADVANCED=y
+CONFIG_TCP_CONG_BIC=m
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_TCP_CONG_WESTWOOD=m
+CONFIG_TCP_CONG_HTCP=m
+CONFIG_TCP_CONG_HSTCP=m
+CONFIG_TCP_CONG_HYBLA=m
+CONFIG_TCP_CONG_VEGAS=m
+CONFIG_TCP_CONG_SCALABLE=m
+CONFIG_TCP_CONG_LP=m
+CONFIG_TCP_CONG_VENO=m
+CONFIG_TCP_CONG_YEAH=m
+CONFIG_TCP_CONG_ILLINOIS=m
+CONFIG_DEFAULT_CUBIC=y
+# CONFIG_DEFAULT_RENO is not set
+CONFIG_DEFAULT_TCP_CONG="cubic"
+CONFIG_TCP_MD5SIG=y
+CONFIG_IPV6=y
+CONFIG_IPV6_PRIVACY=y
+CONFIG_IPV6_ROUTER_PREF=y
+CONFIG_IPV6_ROUTE_INFO=y
+CONFIG_IPV6_OPTIMISTIC_DAD=y
+CONFIG_INET6_AH=m
+CONFIG_INET6_ESP=m
+CONFIG_INET6_IPCOMP=m
+CONFIG_IPV6_MIP6=m
+CONFIG_INET6_XFRM_TUNNEL=m
+CONFIG_INET6_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
+CONFIG_IPV6_SIT=m
+# CONFIG_IPV6_SIT_6RD is not set
+CONFIG_IPV6_NDISC_NODETYPE=y
+CONFIG_IPV6_TUNNEL=m
+CONFIG_IPV6_MULTIPLE_TABLES=y
+# CONFIG_IPV6_SUBTREES is not set
+CONFIG_IPV6_MROUTE=y
+# CONFIG_IPV6_MROUTE_MULTIPLE_TABLES is not set
+CONFIG_IPV6_PIMSM_V2=y
+CONFIG_NETLABEL=y
+CONFIG_NETWORK_SECMARK=y
+# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+CONFIG_NETFILTER_ADVANCED=y
+CONFIG_BRIDGE_NETFILTER=y
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=m
+CONFIG_NETFILTER_NETLINK_QUEUE=m
+CONFIG_NETFILTER_NETLINK_LOG=m
+CONFIG_NF_CONNTRACK=y
+CONFIG_NF_CONNTRACK_MARK=y
+CONFIG_NF_CONNTRACK_SECMARK=y
+CONFIG_NF_CONNTRACK_ZONES=y
+CONFIG_NF_CONNTRACK_EVENTS=y
+# CONFIG_NF_CONNTRACK_TIMESTAMP is not set
+CONFIG_NF_CT_PROTO_DCCP=m
+CONFIG_NF_CT_PROTO_GRE=m
+CONFIG_NF_CT_PROTO_SCTP=m
+CONFIG_NF_CT_PROTO_UDPLITE=m
+CONFIG_NF_CONNTRACK_AMANDA=m
+CONFIG_NF_CONNTRACK_FTP=m
+CONFIG_NF_CONNTRACK_H323=m
+CONFIG_NF_CONNTRACK_IRC=m
+CONFIG_NF_CONNTRACK_BROADCAST=m
+CONFIG_NF_CONNTRACK_NETBIOS_NS=m
+# CONFIG_NF_CONNTRACK_SNMP is not set
+CONFIG_NF_CONNTRACK_PPTP=m
+CONFIG_NF_CONNTRACK_SANE=m
+CONFIG_NF_CONNTRACK_SIP=m
+CONFIG_NF_CONNTRACK_TFTP=m
+# CONFIG_NF_CT_NETLINK is not set
+CONFIG_NETFILTER_TPROXY=m
+CONFIG_NETFILTER_XTABLES=y
+
+#
+# Xtables combined modules
+#
+CONFIG_NETFILTER_XT_MARK=m
+CONFIG_NETFILTER_XT_CONNMARK=m
+
+#
+# Xtables targets
+#
+# CONFIG_NETFILTER_XT_TARGET_AUDIT is not set
+# CONFIG_NETFILTER_XT_TARGET_CHECKSUM is not set
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
+CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m
+CONFIG_NETFILTER_XT_TARGET_CT=m
+CONFIG_NETFILTER_XT_TARGET_DSCP=m
+CONFIG_NETFILTER_XT_TARGET_HL=m
+CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
+CONFIG_NETFILTER_XT_TARGET_MARK=m
+CONFIG_NETFILTER_XT_TARGET_NFLOG=m
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
+CONFIG_NETFILTER_XT_TARGET_RATEEST=m
+CONFIG_NETFILTER_XT_TARGET_TEE=m
+CONFIG_NETFILTER_XT_TARGET_TPROXY=m
+CONFIG_NETFILTER_XT_TARGET_TRACE=m
+CONFIG_NETFILTER_XT_TARGET_SECMARK=m
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
+CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
+
+#
+# Xtables matches
+#
+# CONFIG_NETFILTER_XT_MATCH_ADDRTYPE is not set
+CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=y
+# CONFIG_NETFILTER_XT_MATCH_CPU is not set
+CONFIG_NETFILTER_XT_MATCH_DCCP=m
+# CONFIG_NETFILTER_XT_MATCH_DEVGROUP is not set
+CONFIG_NETFILTER_XT_MATCH_DSCP=m
+CONFIG_NETFILTER_XT_MATCH_ESP=m
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_HELPER=m
+CONFIG_NETFILTER_XT_MATCH_HL=m
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
+CONFIG_NETFILTER_XT_MATCH_IPVS=m
+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
+CONFIG_NETFILTER_XT_MATCH_MAC=m
+CONFIG_NETFILTER_XT_MATCH_MARK=m
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+CONFIG_NETFILTER_XT_MATCH_OSF=m
+CONFIG_NETFILTER_XT_MATCH_OWNER=m
+CONFIG_NETFILTER_XT_MATCH_POLICY=m
+CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
+CONFIG_NETFILTER_XT_MATCH_QUOTA=m
+CONFIG_NETFILTER_XT_MATCH_RATEEST=m
+CONFIG_NETFILTER_XT_MATCH_REALM=m
+CONFIG_NETFILTER_XT_MATCH_RECENT=m
+CONFIG_NETFILTER_XT_MATCH_SCTP=m
+CONFIG_NETFILTER_XT_MATCH_SOCKET=m
+CONFIG_NETFILTER_XT_MATCH_STATE=y
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
+CONFIG_NETFILTER_XT_MATCH_STRING=m
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
+CONFIG_NETFILTER_XT_MATCH_TIME=m
+CONFIG_NETFILTER_XT_MATCH_U32=m
+# CONFIG_IP_SET is not set
+CONFIG_IP_VS=m
+CONFIG_IP_VS_IPV6=y
+# CONFIG_IP_VS_DEBUG is not set
+CONFIG_IP_VS_TAB_BITS=12
+
+#
+# IPVS transport protocol load balancing support
+#
+CONFIG_IP_VS_PROTO_TCP=y
+CONFIG_IP_VS_PROTO_UDP=y
+CONFIG_IP_VS_PROTO_AH_ESP=y
+CONFIG_IP_VS_PROTO_ESP=y
+CONFIG_IP_VS_PROTO_AH=y
+CONFIG_IP_VS_PROTO_SCTP=y
+
+#
+# IPVS scheduler
+#
+CONFIG_IP_VS_RR=m
+CONFIG_IP_VS_WRR=m
+CONFIG_IP_VS_LC=m
+CONFIG_IP_VS_WLC=m
+CONFIG_IP_VS_LBLC=m
+CONFIG_IP_VS_LBLCR=m
+# CONFIG_IP_VS_DH is not set
+# CONFIG_IP_VS_SH is not set
+CONFIG_IP_VS_SED=m
+CONFIG_IP_VS_NQ=m
+
+#
+# IPVS application helper
+#
+# CONFIG_IP_VS_NFCT is not set
+# CONFIG_IP_VS_PE_SIP is not set
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_NF_DEFRAG_IPV4=y
+CONFIG_NF_CONNTRACK_IPV4=y
+# CONFIG_NF_CONNTRACK_PROC_COMPAT is not set
+CONFIG_IP_NF_QUEUE=m
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_IP_NF_MATCH_AH=m
+CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_TTL=m
+CONFIG_IP_NF_FILTER=y
+CONFIG_IP_NF_TARGET_REJECT=y
+CONFIG_IP_NF_TARGET_LOG=m
+CONFIG_IP_NF_TARGET_ULOG=m
+# CONFIG_NF_NAT is not set
+CONFIG_IP_NF_MANGLE=m
+# CONFIG_IP_NF_TARGET_CLUSTERIP is not set
+CONFIG_IP_NF_TARGET_ECN=m
+CONFIG_IP_NF_TARGET_TTL=m
+CONFIG_IP_NF_RAW=m
+CONFIG_IP_NF_SECURITY=m
+CONFIG_IP_NF_ARPTABLES=m
+CONFIG_IP_NF_ARPFILTER=m
+CONFIG_IP_NF_ARP_MANGLE=m
+
+#
+# IPv6: Netfilter Configuration
+#
+CONFIG_NF_DEFRAG_IPV6=m
+CONFIG_NF_CONNTRACK_IPV6=m
+CONFIG_IP6_NF_QUEUE=m
+CONFIG_IP6_NF_IPTABLES=m
+CONFIG_IP6_NF_MATCH_AH=m
+CONFIG_IP6_NF_MATCH_EUI64=m
+CONFIG_IP6_NF_MATCH_FRAG=m
+CONFIG_IP6_NF_MATCH_OPTS=m
+CONFIG_IP6_NF_MATCH_HL=m
+CONFIG_IP6_NF_MATCH_IPV6HEADER=m
+CONFIG_IP6_NF_MATCH_MH=m
+CONFIG_IP6_NF_MATCH_RT=m
+CONFIG_IP6_NF_TARGET_HL=m
+CONFIG_IP6_NF_TARGET_LOG=m
+CONFIG_IP6_NF_FILTER=m
+CONFIG_IP6_NF_TARGET_REJECT=m
+CONFIG_IP6_NF_MANGLE=m
+CONFIG_IP6_NF_RAW=m
+CONFIG_IP6_NF_SECURITY=m
+CONFIG_BRIDGE_NF_EBTABLES=m
+CONFIG_BRIDGE_EBT_BROUTE=m
+CONFIG_BRIDGE_EBT_T_FILTER=m
+CONFIG_BRIDGE_EBT_T_NAT=m
+CONFIG_BRIDGE_EBT_802_3=m
+CONFIG_BRIDGE_EBT_AMONG=m
+CONFIG_BRIDGE_EBT_ARP=m
+CONFIG_BRIDGE_EBT_IP=m
+CONFIG_BRIDGE_EBT_IP6=m
+CONFIG_BRIDGE_EBT_LIMIT=m
+CONFIG_BRIDGE_EBT_MARK=m
+CONFIG_BRIDGE_EBT_PKTTYPE=m
+CONFIG_BRIDGE_EBT_STP=m
+CONFIG_BRIDGE_EBT_VLAN=m
+CONFIG_BRIDGE_EBT_ARPREPLY=m
+CONFIG_BRIDGE_EBT_DNAT=m
+CONFIG_BRIDGE_EBT_MARK_T=m
+CONFIG_BRIDGE_EBT_REDIRECT=m
+CONFIG_BRIDGE_EBT_SNAT=m
+CONFIG_BRIDGE_EBT_LOG=m
+CONFIG_BRIDGE_EBT_ULOG=m
+CONFIG_BRIDGE_EBT_NFLOG=m
+# CONFIG_IP_DCCP is not set
+CONFIG_IP_SCTP=m
+# CONFIG_SCTP_DBG_MSG is not set
+# CONFIG_SCTP_DBG_OBJCNT is not set
+# CONFIG_SCTP_HMAC_NONE is not set
+# CONFIG_SCTP_HMAC_SHA1 is not set
+CONFIG_SCTP_HMAC_MD5=y
+CONFIG_RDS=m
+CONFIG_RDS_TCP=m
+# CONFIG_RDS_DEBUG is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_L2TP is not set
+CONFIG_STP=m
+CONFIG_GARP=m
+CONFIG_BRIDGE=m
+CONFIG_BRIDGE_IGMP_SNOOPING=y
+CONFIG_NET_DSA=y
+CONFIG_NET_DSA_TAG_DSA=y
+CONFIG_NET_DSA_TAG_EDSA=y
+CONFIG_NET_DSA_TAG_TRAILER=y
+CONFIG_NET_DSA_MV88E6XXX=y
+CONFIG_NET_DSA_MV88E6060=y
+CONFIG_NET_DSA_MV88E6XXX_NEED_PPU=y
+CONFIG_NET_DSA_MV88E6131=y
+CONFIG_NET_DSA_MV88E6123_61_65=y
+CONFIG_VLAN_8021Q=m
+CONFIG_VLAN_8021Q_GVRP=y
+# CONFIG_DECNET is not set
+CONFIG_LLC=m
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+CONFIG_PHONET=m
+# CONFIG_IEEE802154 is not set
+CONFIG_NET_SCHED=y
+
+#
+# Queueing/Scheduling
+#
+CONFIG_NET_SCH_CBQ=m
+CONFIG_NET_SCH_HTB=m
+CONFIG_NET_SCH_HFSC=m
+CONFIG_NET_SCH_PRIO=m
+CONFIG_NET_SCH_MULTIQ=m
+CONFIG_NET_SCH_RED=m
+# CONFIG_NET_SCH_SFB is not set
+CONFIG_NET_SCH_SFQ=m
+CONFIG_NET_SCH_TEQL=m
+CONFIG_NET_SCH_TBF=m
+CONFIG_NET_SCH_GRED=m
+CONFIG_NET_SCH_DSMARK=m
+CONFIG_NET_SCH_NETEM=m
+CONFIG_NET_SCH_DRR=m
+# CONFIG_NET_SCH_MQPRIO is not set
+# CONFIG_NET_SCH_CHOKE is not set
+CONFIG_NET_SCH_INGRESS=m
+
+#
+# Classification
+#
+CONFIG_NET_CLS=y
+CONFIG_NET_CLS_BASIC=m
+CONFIG_NET_CLS_TCINDEX=m
+CONFIG_NET_CLS_ROUTE4=m
+CONFIG_NET_CLS_FW=m
+CONFIG_NET_CLS_U32=m
+CONFIG_CLS_U32_PERF=y
+CONFIG_CLS_U32_MARK=y
+CONFIG_NET_CLS_RSVP=m
+CONFIG_NET_CLS_RSVP6=m
+CONFIG_NET_CLS_FLOW=m
+CONFIG_NET_CLS_CGROUP=y
+CONFIG_NET_EMATCH=y
+CONFIG_NET_EMATCH_STACK=32
+CONFIG_NET_EMATCH_CMP=m
+CONFIG_NET_EMATCH_NBYTE=m
+CONFIG_NET_EMATCH_U32=m
+CONFIG_NET_EMATCH_META=m
+CONFIG_NET_EMATCH_TEXT=m
+CONFIG_NET_CLS_ACT=y
+CONFIG_NET_ACT_POLICE=m
+CONFIG_NET_ACT_GACT=m
+CONFIG_GACT_PROB=y
+CONFIG_NET_ACT_MIRRED=m
+CONFIG_NET_ACT_IPT=m
+CONFIG_NET_ACT_NAT=m
+CONFIG_NET_ACT_PEDIT=m
+CONFIG_NET_ACT_SIMP=m
+CONFIG_NET_ACT_SKBEDIT=m
+# CONFIG_NET_ACT_CSUM is not set
+CONFIG_NET_CLS_IND=y
+CONFIG_NET_SCH_FIFO=y
+CONFIG_DCB=y
+CONFIG_DNS_RESOLVER=y
+# CONFIG_BATMAN_ADV is not set
+CONFIG_RPS=y
+CONFIG_RFS_ACCEL=y
+CONFIG_XPS=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+CONFIG_FIB_RULES=y
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+# CONFIG_CAIF is not set
+# CONFIG_CEPH_LIB is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+# CONFIG_FIRMWARE_IN_KERNEL is not set
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+CONFIG_CONNECTOR=y
+CONFIG_PROC_EVENTS=y
+# CONFIG_MTD is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=m
+# CONFIG_BLK_DEV_DRBD is not set
+# CONFIG_BLK_DEV_NBD is not set
+CONFIG_BLK_DEV_SX8=m
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=16384
+# CONFIG_BLK_DEV_XIP is not set
+# CONFIG_CDROM_PKTCDVD is not set
+CONFIG_ATA_OVER_ETH=y
+# CONFIG_BLK_DEV_RBD is not set
+# CONFIG_SENSORS_LIS3LV02D is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_AD525X_DPOT is not set
+# CONFIG_PHANTOM is not set
+# CONFIG_SGI_IOC4 is not set
+# CONFIG_TIFM_CORE is not set
+# CONFIG_ICS932S401 is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_HP_ILO is not set
+# CONFIG_APDS9802ALS is not set
+# CONFIG_ISL29003 is not set
+# CONFIG_ISL29020 is not set
+# CONFIG_SENSORS_TSL2550 is not set
+# CONFIG_SENSORS_BH1780 is not set
+# CONFIG_SENSORS_BH1770 is not set
+# CONFIG_SENSORS_APDS990X is not set
+# CONFIG_HMC6352 is not set
+# CONFIG_DS1682 is not set
+# CONFIG_BMP085 is not set
+# CONFIG_PCH_PHUB is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_AT24 is not set
+# CONFIG_EEPROM_LEGACY is not set
+# CONFIG_EEPROM_MAX6875 is not set
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_CB710_CORE is not set
+
+#
+# Texas Instruments shared transport line discipline
+#
+# CONFIG_SENSORS_LIS3_I2C is not set
+
+#
+# SCSI device support
+#
+CONFIG_SCSI_MOD=m
+CONFIG_RAID_ATTRS=m
+CONFIG_SCSI=m
+CONFIG_SCSI_DMA=y
+CONFIG_SCSI_TGT=m
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=m
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_LOGGING=y
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+CONFIG_SCSI_SAS_ATTRS=m
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_ISCSI_BOOT_SYSFS is not set
+# CONFIG_SCSI_CXGB3_ISCSI is not set
+# CONFIG_SCSI_CXGB4_ISCSI is not set
+# CONFIG_SCSI_BNX2_ISCSI is not set
+# CONFIG_SCSI_BNX2X_FCOE is not set
+# CONFIG_BE2ISCSI is not set
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_HPSA is not set
+# CONFIG_SCSI_3W_9XXX is not set
+# CONFIG_SCSI_3W_SAS is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_AIC79XX is not set
+# CONFIG_SCSI_AIC94XX is not set
+# CONFIG_SCSI_MVSAS is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_ARCMSR is not set
+# CONFIG_MEGARAID_NEWGEN is not set
+# CONFIG_MEGARAID_LEGACY is not set
+# CONFIG_MEGARAID_SAS is not set
+# CONFIG_SCSI_MPT2SAS is not set
+# CONFIG_SCSI_HPTIOP is not set
+# CONFIG_LIBFC is not set
+# CONFIG_LIBFCOE is not set
+# CONFIG_FCOE is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_IPS is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_STEX is not set
+# CONFIG_SCSI_SYM53C8XX_2 is not set
+# CONFIG_SCSI_IPR is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLA_FC is not set
+# CONFIG_SCSI_QLA_ISCSI is not set
+# CONFIG_SCSI_LPFC is not set
+# CONFIG_SCSI_DC395x is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_PMCRAID is not set
+# CONFIG_SCSI_PM8001 is not set
+# CONFIG_SCSI_SRP is not set
+# CONFIG_SCSI_BFA_FC is not set
+# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+CONFIG_ATA=m
+# CONFIG_ATA_NONSTANDARD is not set
+CONFIG_ATA_VERBOSE_ERROR=y
+CONFIG_SATA_PMP=y
+
+#
+# Controllers with non-SFF native interface
+#
+# CONFIG_SATA_AHCI is not set
+# CONFIG_SATA_AHCI_PLATFORM is not set
+# CONFIG_SATA_INIC162X is not set
+# CONFIG_SATA_ACARD_AHCI is not set
+CONFIG_SATA_SIL24=m
+CONFIG_ATA_SFF=y
+
+#
+# SFF controllers with custom DMA interface
+#
+# CONFIG_PDC_ADMA is not set
+# CONFIG_SATA_QSTOR is not set
+# CONFIG_SATA_SX4 is not set
+CONFIG_ATA_BMDMA=y
+
+#
+# SATA SFF controllers with BMDMA
+#
+# CONFIG_ATA_PIIX is not set
+# CONFIG_SATA_MV is not set
+# CONFIG_SATA_NV is not set
+# CONFIG_SATA_PROMISE is not set
+# CONFIG_SATA_SIL is not set
+# CONFIG_SATA_SIS is not set
+# CONFIG_SATA_SVW is not set
+# CONFIG_SATA_ULI is not set
+# CONFIG_SATA_VIA is not set
+# CONFIG_SATA_VITESSE is not set
+
+#
+# PATA SFF controllers with BMDMA
+#
+# CONFIG_PATA_ALI is not set
+# CONFIG_PATA_AMD is not set
+# CONFIG_PATA_ARASAN_CF is not set
+# CONFIG_PATA_ARTOP is not set
+# CONFIG_PATA_ATIIXP is not set
+# CONFIG_PATA_ATP867X is not set
+# CONFIG_PATA_CMD64X is not set
+# CONFIG_PATA_CS5520 is not set
+# CONFIG_PATA_CS5530 is not set
+# CONFIG_PATA_CS5536 is not set
+# CONFIG_PATA_CYPRESS is not set
+# CONFIG_PATA_EFAR is not set
+# CONFIG_PATA_HPT366 is not set
+# CONFIG_PATA_HPT37X is not set
+# CONFIG_PATA_HPT3X2N is not set
+# CONFIG_PATA_HPT3X3 is not set
+# CONFIG_PATA_IT8213 is not set
+# CONFIG_PATA_IT821X is not set
+# CONFIG_PATA_JMICRON is not set
+# CONFIG_PATA_MARVELL is not set
+# CONFIG_PATA_NETCELL is not set
+# CONFIG_PATA_NINJA32 is not set
+# CONFIG_PATA_NS87415 is not set
+# CONFIG_PATA_OLDPIIX is not set
+# CONFIG_PATA_OPTIDMA is not set
+# CONFIG_PATA_PDC2027X is not set
+# CONFIG_PATA_PDC_OLD is not set
+# CONFIG_PATA_RADISYS is not set
+# CONFIG_PATA_RDC is not set
+# CONFIG_PATA_SC1200 is not set
+# CONFIG_PATA_SCH is not set
+# CONFIG_PATA_SERVERWORKS is not set
+# CONFIG_PATA_SIL680 is not set
+# CONFIG_PATA_SIS is not set
+# CONFIG_PATA_TOSHIBA is not set
+# CONFIG_PATA_TRIFLEX is not set
+# CONFIG_PATA_VIA is not set
+# CONFIG_PATA_WINBOND is not set
+
+#
+# PIO-only SFF controllers
+#
+# CONFIG_PATA_CMD640_PCI is not set
+# CONFIG_PATA_MPIIX is not set
+# CONFIG_PATA_NS87410 is not set
+# CONFIG_PATA_OPTI is not set
+# CONFIG_PATA_PLATFORM is not set
+# CONFIG_PATA_RZ1000 is not set
+
+#
+# Generic fallback / legacy drivers
+#
+# CONFIG_ATA_GENERIC is not set
+# CONFIG_PATA_LEGACY is not set
+CONFIG_MD=y
+CONFIG_BLK_DEV_MD=y
+CONFIG_MD_AUTODETECT=y
+CONFIG_MD_LINEAR=m
+CONFIG_MD_RAID0=m
+CONFIG_MD_RAID1=m
+CONFIG_MD_RAID10=m
+CONFIG_MD_RAID456=m
+CONFIG_MULTICORE_RAID456=y
+# CONFIG_MD_MULTIPATH is not set
+CONFIG_MD_FAULTY=m
+CONFIG_BLK_DEV_DM=m
+CONFIG_DM_DEBUG=y
+CONFIG_DM_CRYPT=m
+CONFIG_DM_SNAPSHOT=m
+CONFIG_DM_MIRROR=m
+# CONFIG_DM_RAID is not set
+CONFIG_DM_LOG_USERSPACE=m
+CONFIG_DM_ZERO=m
+CONFIG_DM_MULTIPATH=m
+CONFIG_DM_MULTIPATH_QL=m
+CONFIG_DM_MULTIPATH_ST=m
+CONFIG_DM_DELAY=m
+CONFIG_DM_UEVENT=y
+# CONFIG_DM_FLAKEY is not set
+# CONFIG_TARGET_CORE is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_FIREWIRE_NOSY is not set
+# CONFIG_I2O is not set
+CONFIG_NETDEVICES=y
+CONFIG_IFB=m
+CONFIG_DUMMY=m
+CONFIG_BONDING=m
+CONFIG_MACVLAN=m
+CONFIG_MACVTAP=m
+# CONFIG_EQUALIZER is not set
+CONFIG_TUN=y
+CONFIG_VETH=m
+# CONFIG_ARCNET is not set
+# CONFIG_MII is not set
+CONFIG_PHYLIB=y
+
+#
+# MII PHY device drivers
+#
+# CONFIG_MARVELL_PHY is not set
+# CONFIG_DAVICOM_PHY is not set
+# CONFIG_QSEMI_PHY is not set
+# CONFIG_LXT_PHY is not set
+# CONFIG_CICADA_PHY is not set
+# CONFIG_VITESSE_PHY is not set
+# CONFIG_SMSC_PHY is not set
+# CONFIG_BROADCOM_PHY is not set
+# CONFIG_BCM63XX_PHY is not set
+# CONFIG_ICPLUS_PHY is not set
+# CONFIG_REALTEK_PHY is not set
+# CONFIG_NATIONAL_PHY is not set
+# CONFIG_STE10XP is not set
+# CONFIG_LSI_ET1011C_PHY is not set
+# CONFIG_MICREL_PHY is not set
+# CONFIG_FIXED_PHY is not set
+# CONFIG_MDIO_BITBANG is not set
+# CONFIG_NET_ETHERNET is not set
+CONFIG_NETDEV_1000=y
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+CONFIG_E1000E=m
+# CONFIG_IP1000 is not set
+# CONFIG_IGB is not set
+# CONFIG_IGBVF is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SIS190 is not set
+# CONFIG_SKGE is not set
+# CONFIG_SKY2 is not set
+# CONFIG_VIA_VELOCITY is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+# CONFIG_CNIC is not set
+# CONFIG_QLA3XXX is not set
+# CONFIG_ATL1 is not set
+# CONFIG_ATL1E is not set
+# CONFIG_ATL1C is not set
+# CONFIG_JME is not set
+# CONFIG_STMMAC_ETH is not set
+# CONFIG_PCH_GBE is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_TR is not set
+# CONFIG_WLAN is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+# CONFIG_WAN is not set
+
+#
+# CAIF transport drivers
+#
+# CONFIG_TILE_NET is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NET_FC is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_VMXNET3 is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+# CONFIG_INPUT_SPARSEKMAP is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
+# CONFIG_N_GSM is not set
+CONFIG_DEVKMEM=y
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_MFD_HSU is not set
+# CONFIG_SERIAL_JSM is not set
+# CONFIG_SERIAL_TIMBERDALE is not set
+# CONFIG_SERIAL_ALTERA_JTAGUART is not set
+# CONFIG_SERIAL_ALTERA_UART is not set
+# CONFIG_SERIAL_PCH_UART is not set
+# CONFIG_TTY_PRINTK is not set
+CONFIG_HVC_DRIVER=y
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_TIMERIOMEM=m
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# PCMCIA character devices
+#
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+# CONFIG_RAMOOPS is not set
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_COMPAT=y
+CONFIG_I2C_CHARDEV=y
+# CONFIG_I2C_MUX is not set
+CONFIG_I2C_HELPER_AUTO=y
+
+#
+# I2C Hardware Bus support
+#
+
+#
+# PC SMBus host controller drivers
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_ISCH is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+
+#
+# I2C system bus drivers (mostly embedded / system-on-chip)
+#
+# CONFIG_I2C_INTEL_MID is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PCA_PLATFORM is not set
+# CONFIG_I2C_PXA_PCI is not set
+# CONFIG_I2C_SIMTEC is not set
+# CONFIG_I2C_XILINX is not set
+# CONFIG_I2C_EG20T is not set
+
+#
+# External I2C/SMBus adapter drivers
+#
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_TAOS_EVM is not set
+
+#
+# Other I2C/SMBus bus drivers
+#
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_SPI is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+
+#
+# PPS generators support
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+# CONFIG_HWMON is not set
+# CONFIG_THERMAL is not set
+# CONFIG_WATCHDOG is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+CONFIG_MFD_SUPPORT=y
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_88PM860X is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_TPS6105X is not set
+# CONFIG_TPS6507X is not set
+# CONFIG_TWL4030_CORE is not set
+# CONFIG_MFD_STMPE is not set
+# CONFIG_MFD_TC3589X is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_PMIC_DA903X is not set
+# CONFIG_PMIC_ADP5520 is not set
+# CONFIG_MFD_MAX8925 is not set
+# CONFIG_MFD_MAX8997 is not set
+# CONFIG_MFD_MAX8998 is not set
+# CONFIG_MFD_WM8400 is not set
+# CONFIG_MFD_WM831X_I2C is not set
+# CONFIG_MFD_WM8350_I2C is not set
+# CONFIG_MFD_WM8994 is not set
+# CONFIG_MFD_PCF50633 is not set
+# CONFIG_ABX500_CORE is not set
+# CONFIG_LPC_SCH is not set
+# CONFIG_MFD_RDC321X is not set
+# CONFIG_MFD_JANZ_CMODIO is not set
+# CONFIG_MFD_VX855 is not set
+# CONFIG_MFD_WL1273_CORE is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+# CONFIG_VGA_ARB is not set
+# CONFIG_DRM is not set
+# CONFIG_STUB_POULSBO is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+# CONFIG_USB_SUPPORT is not set
+# CONFIG_UWB is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_NFC_DEVICES is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_INFINIBAND is not set
+# CONFIG_EDAC is not set
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1374 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_DS3232 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_ISL12022 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+# CONFIG_RTC_DRV_M41T80 is not set
+# CONFIG_RTC_DRV_BQ32K is not set
+# CONFIG_RTC_DRV_S35390A is not set
+# CONFIG_RTC_DRV_FM3130 is not set
+# CONFIG_RTC_DRV_RX8581 is not set
+# CONFIG_RTC_DRV_RX8025 is not set
+
+#
+# SPI RTC drivers
+#
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_MSM6242 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_RP5C01 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_TILE=y
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+CONFIG_EXT2_FS_POSIX_ACL=y
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT2_FS_XIP=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_DEFAULTS_TO_ORDERED=y
+CONFIG_EXT3_FS_XATTR=y
+CONFIG_EXT3_FS_POSIX_ACL=y
+CONFIG_EXT3_FS_SECURITY=y
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_XATTR=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+# CONFIG_EXT4_DEBUG is not set
+CONFIG_FS_XIP=y
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_JBD2=y
+CONFIG_JBD2_DEBUG=y
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+CONFIG_XFS_FS=m
+CONFIG_XFS_QUOTA=y
+CONFIG_XFS_POSIX_ACL=y
+# CONFIG_XFS_RT is not set
+# CONFIG_XFS_DEBUG is not set
+CONFIG_GFS2_FS=m
+CONFIG_GFS2_FS_LOCKING_DLM=y
+# CONFIG_OCFS2_FS is not set
+CONFIG_BTRFS_FS=m
+CONFIG_BTRFS_FS_POSIX_ACL=y
+# CONFIG_NILFS2_FS is not set
+CONFIG_FS_POSIX_ACL=y
+CONFIG_EXPORTFS=y
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_FANOTIFY is not set
+CONFIG_QUOTA=y
+CONFIG_QUOTA_NETLINK_INTERFACE=y
+# CONFIG_PRINT_QUOTA_WARNING is not set
+# CONFIG_QUOTA_DEBUG is not set
+CONFIG_QUOTA_TREE=y
+# CONFIG_QFMT_V1 is not set
+CONFIG_QFMT_V2=y
+CONFIG_QUOTACTL=y
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=y
+CONFIG_CUSE=m
+CONFIG_GENERIC_ACL=y
+
+#
+# Caches
+#
+CONFIG_FSCACHE=m
+CONFIG_FSCACHE_STATS=y
+# CONFIG_FSCACHE_HISTOGRAM is not set
+# CONFIG_FSCACHE_DEBUG is not set
+# CONFIG_FSCACHE_OBJECT_LIST is not set
+CONFIG_CACHEFILES=m
+# CONFIG_CACHEFILES_DEBUG is not set
+# CONFIG_CACHEFILES_HISTOGRAM is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=m
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=m
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_HUGETLBFS=y
+CONFIG_HUGETLB_PAGE=y
+CONFIG_CONFIGFS_FS=m
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+CONFIG_ECRYPT_FS=m
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_LOGFS is not set
+CONFIG_CRAMFS=m
+CONFIG_SQUASHFS=m
+# CONFIG_SQUASHFS_XATTR is not set
+# CONFIG_SQUASHFS_LZO is not set
+# CONFIG_SQUASHFS_XZ is not set
+# CONFIG_SQUASHFS_EMBEDDED is not set
+CONFIG_SQUASHFS_FRAGMENT_CACHE_SIZE=3
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_PSTORE is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=m
+CONFIG_NFS_V3=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_NFS_V4_1=y
+CONFIG_PNFS_FILE_LAYOUT=m
+CONFIG_NFS_FSCACHE=y
+# CONFIG_NFS_USE_LEGACY_DNS is not set
+CONFIG_NFS_USE_KERNEL_DNS=y
+# CONFIG_NFS_USE_NEW_IDMAPPER is not set
+CONFIG_NFSD=m
+CONFIG_NFSD_DEPRECATED=y
+CONFIG_NFSD_V2_ACL=y
+CONFIG_NFSD_V3=y
+CONFIG_NFSD_V3_ACL=y
+CONFIG_NFSD_V4=y
+CONFIG_LOCKD=m
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_ACL_SUPPORT=m
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=m
+CONFIG_SUNRPC_GSS=m
+CONFIG_RPCSEC_GSS_KRB5=m
+# CONFIG_CEPH_FS is not set
+CONFIG_CIFS=m
+CONFIG_CIFS_STATS=y
+# CONFIG_CIFS_STATS2 is not set
+CONFIG_CIFS_WEAK_PW_HASH=y
+CONFIG_CIFS_UPCALL=y
+CONFIG_CIFS_XATTR=y
+CONFIG_CIFS_POSIX=y
+# CONFIG_CIFS_DEBUG2 is not set
+CONFIG_CIFS_DFS_UPCALL=y
+CONFIG_CIFS_FSCACHE=y
+# CONFIG_CIFS_ACL is not set
+CONFIG_CIFS_EXPERIMENTAL=y
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+CONFIG_OSF_PARTITION=y
+CONFIG_AMIGA_PARTITION=y
+# CONFIG_ATARI_PARTITION is not set
+CONFIG_MAC_PARTITION=y
+CONFIG_MSDOS_PARTITION=y
+CONFIG_BSD_DISKLABEL=y
+CONFIG_MINIX_SUBPARTITION=y
+CONFIG_SOLARIS_X86_PARTITION=y
+CONFIG_UNIXWARE_DISKLABEL=y
+# CONFIG_LDM_PARTITION is not set
+CONFIG_SGI_PARTITION=y
+# CONFIG_ULTRIX_PARTITION is not set
+CONFIG_SUN_PARTITION=y
+CONFIG_KARMA_PARTITION=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_SYSV68_PARTITION is not set
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="utf8"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_737=m
+CONFIG_NLS_CODEPAGE_775=m
+CONFIG_NLS_CODEPAGE_850=m
+CONFIG_NLS_CODEPAGE_852=m
+CONFIG_NLS_CODEPAGE_855=m
+CONFIG_NLS_CODEPAGE_857=m
+CONFIG_NLS_CODEPAGE_860=m
+CONFIG_NLS_CODEPAGE_861=m
+CONFIG_NLS_CODEPAGE_862=m
+CONFIG_NLS_CODEPAGE_863=m
+CONFIG_NLS_CODEPAGE_864=m
+CONFIG_NLS_CODEPAGE_865=m
+CONFIG_NLS_CODEPAGE_866=m
+CONFIG_NLS_CODEPAGE_869=m
+CONFIG_NLS_CODEPAGE_936=m
+CONFIG_NLS_CODEPAGE_950=m
+CONFIG_NLS_CODEPAGE_932=m
+CONFIG_NLS_CODEPAGE_949=m
+CONFIG_NLS_CODEPAGE_874=m
+CONFIG_NLS_ISO8859_8=m
+CONFIG_NLS_CODEPAGE_1250=m
+CONFIG_NLS_CODEPAGE_1251=m
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=m
+CONFIG_NLS_ISO8859_2=m
+CONFIG_NLS_ISO8859_3=m
+CONFIG_NLS_ISO8859_4=m
+CONFIG_NLS_ISO8859_5=m
+CONFIG_NLS_ISO8859_6=m
+CONFIG_NLS_ISO8859_7=m
+CONFIG_NLS_ISO8859_9=m
+CONFIG_NLS_ISO8859_13=m
+CONFIG_NLS_ISO8859_14=m
+CONFIG_NLS_ISO8859_15=m
+CONFIG_NLS_KOI8_R=m
+CONFIG_NLS_KOI8_U=m
+CONFIG_NLS_UTF8=m
+CONFIG_DLM=m
+CONFIG_DLM_DEBUG=y
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=2048
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_STRIP_ASM_SYMS=y
+# CONFIG_UNUSED_SYMBOLS is not set
+CONFIG_DEBUG_FS=y
+CONFIG_HEADERS_CHECK=y
+# CONFIG_DEBUG_SECTION_MISMATCH is not set
+CONFIG_DEBUG_KERNEL=y
+CONFIG_DEBUG_SHIRQ=y
+CONFIG_LOCKUP_DETECTOR=y
+# CONFIG_HARDLOCKUP_DETECTOR is not set
+# CONFIG_BOOTPARAM_HARDLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_HARDLOCKUP_PANIC_VALUE=0
+# CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC is not set
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC_VALUE=0
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+CONFIG_SCHEDSTATS=y
+CONFIG_TIMER_STATS=y
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_KMEMLEAK is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_SPARSE_RCU_POINTER is not set
+# CONFIG_LOCK_STAT is not set
+CONFIG_DEBUG_SPINLOCK_SLEEP=y
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+CONFIG_STACKTRACE=y
+# CONFIG_DEBUG_KOBJECT is not set
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_INFO_REDUCED=y
+CONFIG_DEBUG_VM=y
+# CONFIG_DEBUG_WRITECOUNT is not set
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_DEBUG_LIST=y
+# CONFIG_TEST_LIST_SORT is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+CONFIG_DEBUG_CREDENTIALS=y
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+CONFIG_DEBUG_FORCE_WEAK_PER_CPU=y
+# CONFIG_LKDTM is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_DEBUG_PAGEALLOC is not set
+CONFIG_TRACING_SUPPORT=y
+CONFIG_FTRACE=y
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_BUILD_DOCSRC is not set
+CONFIG_DYNAMIC_DEBUG=y
+# CONFIG_ATOMIC64_SELFTEST is not set
+CONFIG_ASYNC_RAID6_TEST=m
+# CONFIG_SAMPLES is not set
+# CONFIG_TEST_KSTRTOX is not set
+CONFIG_EARLY_PRINTK=y
+CONFIG_DEBUG_STACKOVERFLOW=y
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_EXTRA_FLAGS=""
+
+#
+# Security options
+#
+CONFIG_KEYS=y
+CONFIG_KEYS_DEBUG_PROC_KEYS=y
+# CONFIG_SECURITY_DMESG_RESTRICT is not set
+CONFIG_SECURITY=y
+CONFIG_SECURITYFS=y
+CONFIG_SECURITY_NETWORK=y
+CONFIG_SECURITY_NETWORK_XFRM=y
+# CONFIG_SECURITY_PATH is not set
+CONFIG_LSM_MMAP_MIN_ADDR=65536
+CONFIG_SECURITY_SELINUX=y
+CONFIG_SECURITY_SELINUX_BOOTPARAM=y
+CONFIG_SECURITY_SELINUX_BOOTPARAM_VALUE=1
+CONFIG_SECURITY_SELINUX_DISABLE=y
+CONFIG_SECURITY_SELINUX_DEVELOP=y
+CONFIG_SECURITY_SELINUX_AVC_STATS=y
+CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=1
+# CONFIG_SECURITY_SELINUX_POLICYDB_VERSION_MAX is not set
+# CONFIG_SECURITY_SMACK is not set
+# CONFIG_SECURITY_TOMOYO is not set
+# CONFIG_SECURITY_APPARMOR is not set
+# CONFIG_IMA is not set
+CONFIG_DEFAULT_SECURITY_SELINUX=y
+# CONFIG_DEFAULT_SECURITY_DAC is not set
+CONFIG_DEFAULT_SECURITY="selinux"
+CONFIG_XOR_BLOCKS=m
+CONFIG_ASYNC_CORE=m
+CONFIG_ASYNC_MEMCPY=m
+CONFIG_ASYNC_XOR=m
+CONFIG_ASYNC_PQ=m
+CONFIG_ASYNC_RAID6_RECOV=m
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_ALGAPI2=y
+CONFIG_CRYPTO_AEAD=m
+CONFIG_CRYPTO_AEAD2=y
+CONFIG_CRYPTO_BLKCIPHER=m
+CONFIG_CRYPTO_BLKCIPHER2=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_HASH2=y
+CONFIG_CRYPTO_RNG=m
+CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_PCOMP=m
+CONFIG_CRYPTO_PCOMP2=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_MANAGER2=y
+CONFIG_CRYPTO_MANAGER_DISABLE_TESTS=y
+CONFIG_CRYPTO_GF128MUL=m
+CONFIG_CRYPTO_NULL=m
+CONFIG_CRYPTO_PCRYPT=m
+CONFIG_CRYPTO_WORKQUEUE=y
+CONFIG_CRYPTO_CRYPTD=m
+CONFIG_CRYPTO_AUTHENC=m
+CONFIG_CRYPTO_TEST=m
+
+#
+# Authenticated Encryption with Associated Data
+#
+CONFIG_CRYPTO_CCM=m
+CONFIG_CRYPTO_GCM=m
+CONFIG_CRYPTO_SEQIV=m
+
+#
+# Block modes
+#
+CONFIG_CRYPTO_CBC=m
+CONFIG_CRYPTO_CTR=m
+CONFIG_CRYPTO_CTS=m
+CONFIG_CRYPTO_ECB=m
+CONFIG_CRYPTO_LRW=m
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_XTS=m
+
+#
+# Hash modes
+#
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_XCBC=m
+CONFIG_CRYPTO_VMAC=m
+
+#
+# Digest
+#
+CONFIG_CRYPTO_CRC32C=y
+CONFIG_CRYPTO_GHASH=m
+CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_MICHAEL_MIC=m
+CONFIG_CRYPTO_RMD128=m
+CONFIG_CRYPTO_RMD160=m
+CONFIG_CRYPTO_RMD256=m
+CONFIG_CRYPTO_RMD320=m
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA256=m
+CONFIG_CRYPTO_SHA512=m
+CONFIG_CRYPTO_TGR192=m
+CONFIG_CRYPTO_WP512=m
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=m
+CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_ARC4=m
+CONFIG_CRYPTO_BLOWFISH=m
+CONFIG_CRYPTO_CAMELLIA=m
+CONFIG_CRYPTO_CAST5=m
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_DES=m
+CONFIG_CRYPTO_FCRYPT=m
+CONFIG_CRYPTO_KHAZAD=m
+# CONFIG_CRYPTO_SALSA20 is not set
+CONFIG_CRYPTO_SEED=m
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_TEA=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
+
+#
+# Compression
+#
+CONFIG_CRYPTO_DEFLATE=m
+CONFIG_CRYPTO_ZLIB=m
+CONFIG_CRYPTO_LZO=m
+
+#
+# Random Number Generation
+#
+CONFIG_CRYPTO_ANSI_CPRNG=m
+# CONFIG_CRYPTO_USER_API_HASH is not set
+# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
+CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_DEV_HIFN_795X=m
+CONFIG_CRYPTO_DEV_HIFN_795X_RNG=y
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_RAID6_PQ=m
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_FIRST_BIT=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+CONFIG_CRC16=y
+CONFIG_CRC_T10DIF=y
+CONFIG_CRC_ITU_T=m
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+CONFIG_LIBCRC32C=m
+CONFIG_AUDIT_GENERIC=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=m
+CONFIG_LZO_COMPRESS=m
+CONFIG_LZO_DECOMPRESS=m
+# CONFIG_XZ_DEC is not set
+# CONFIG_XZ_DEC_BCJ is not set
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_TEXTSEARCH=y
+CONFIG_TEXTSEARCH_KMP=m
+CONFIG_TEXTSEARCH_BM=m
+CONFIG_TEXTSEARCH_FSM=m
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_CPU_RMAP=y
+CONFIG_NLATTR=y
+# CONFIG_AVERAGE is not set
+# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/tile/configs/tilepro_defconfig b/arch/tile/configs/tilepro_defconfig
new file mode 100644
index 0000000..f58dc36
--- /dev/null
+++ b/arch/tile/configs/tilepro_defconfig
@@ -0,0 +1,1163 @@
+#
+# Automatically generated make config: don't edit
+# Linux/tile 2.6.39-rc5 Kernel Configuration
+# Tue May 3 09:15:02 2011
+#
+CONFIG_TILE=y
+CONFIG_MMU=y
+CONFIG_GENERIC_CSUM=y
+CONFIG_SEMAPHORE_SLEEPERS=y
+CONFIG_HAVE_ARCH_ALLOC_REMAP=y
+CONFIG_HAVE_SETUP_PER_CPU_AREA=y
+CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK=y
+CONFIG_SYS_SUPPORTS_HUGETLBFS=y
+CONFIG_GENERIC_TIME=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_RWSEM_GENERIC_SPINLOCK=y
+CONFIG_DEFAULT_MIGRATION_COST=10000000
+CONFIG_ARCH_SUPPORTS_OPTIMIZED_INLINING=y
+CONFIG_ARCH_PHYS_ADDR_T_64BIT=y
+CONFIG_ARCH_DMA_ADDR_T_64BIT=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_ARCH_DISCONTIGMEM_ENABLE=y
+CONFIG_ARCH_DISCONTIGMEM_DEFAULT=y
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_STRICT_DEVMEM=y
+CONFIG_SMP=y
+# CONFIG_DEBUG_COPY_FROM_USER is not set
+CONFIG_HVC_TILE=y
+# CONFIG_TILEGX is not set
+CONFIG_ARCH_DEFCONFIG="arch/tile/configs/tile_defconfig"
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+CONFIG_CONSTRUCTORS=y
+
+#
+# General setup
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+CONFIG_CROSS_COMPILE=""
+CONFIG_LOCALVERSION=""
+CONFIG_LOCALVERSION_AUTO=y
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_SYSVIPC_SYSCTL=y
+# CONFIG_POSIX_MQUEUE is not set
+# CONFIG_BSD_PROCESS_ACCT is not set
+CONFIG_FHANDLE=y
+# CONFIG_TASKSTATS is not set
+# CONFIG_AUDIT is not set
+CONFIG_HAVE_GENERIC_HARDIRQS=y
+
+#
+# IRQ subsystem
+#
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_GENERIC_IRQ_SHOW=y
+CONFIG_GENERIC_PENDING_IRQ=y
+
+#
+# RCU Subsystem
+#
+CONFIG_TREE_RCU=y
+# CONFIG_PREEMPT_RCU is not set
+# CONFIG_RCU_TRACE is not set
+CONFIG_RCU_FANOUT=32
+# CONFIG_RCU_FANOUT_EXACT is not set
+# CONFIG_RCU_FAST_NO_HZ is not set
+# CONFIG_TREE_RCU_TRACE is not set
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=17
+# CONFIG_CGROUPS is not set
+# CONFIG_NAMESPACES is not set
+# CONFIG_SCHED_AUTOGROUP is not set
+# CONFIG_SYSFS_DEPRECATED is not set
+# CONFIG_RELAY is not set
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE="usr/contents.txt"
+CONFIG_INITRAMFS_ROOT_UID=0
+CONFIG_INITRAMFS_ROOT_GID=0
+CONFIG_RD_GZIP=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+# CONFIG_RD_XZ is not set
+# CONFIG_RD_LZO is not set
+CONFIG_INITRAMFS_COMPRESSION_NONE=y
+# CONFIG_INITRAMFS_COMPRESSION_GZIP is not set
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_ANON_INODES=y
+CONFIG_EXPERT=y
+CONFIG_SYSCTL_SYSCALL=y
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+# CONFIG_KALLSYMS_EXTRA_PASS is not set
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+CONFIG_BASE_FULL=y
+CONFIG_FUTEX=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_AIO=y
+CONFIG_EMBEDDED=y
+
+#
+# Kernel Performance Events And Counters
+#
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_PCI_QUIRKS=y
+CONFIG_SLUB_DEBUG=y
+# CONFIG_COMPAT_BRK is not set
+# CONFIG_SLAB is not set
+CONFIG_SLUB=y
+# CONFIG_SLOB is not set
+CONFIG_PROFILING=y
+CONFIG_USE_GENERIC_SMP_HELPERS=y
+
+#
+# GCOV-based kernel profiling
+#
+# CONFIG_HAVE_GENERIC_DMA_COHERENT is not set
+CONFIG_SLABINFO=y
+CONFIG_RT_MUTEXES=y
+CONFIG_BASE_SMALL=0
+CONFIG_MODULES=y
+# CONFIG_MODULE_FORCE_LOAD is not set
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+# CONFIG_MODVERSIONS is not set
+# CONFIG_MODULE_SRCVERSION_ALL is not set
+CONFIG_STOP_MACHINE=y
+CONFIG_BLOCK=y
+CONFIG_LBDAF=y
+# CONFIG_BLK_DEV_BSG is not set
+# CONFIG_BLK_DEV_INTEGRITY is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_IOSCHED_CFQ is not set
+CONFIG_DEFAULT_NOOP=y
+CONFIG_DEFAULT_IOSCHED="noop"
+# CONFIG_INLINE_SPIN_TRYLOCK is not set
+# CONFIG_INLINE_SPIN_TRYLOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK is not set
+# CONFIG_INLINE_SPIN_LOCK_BH is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQ is not set
+# CONFIG_INLINE_SPIN_LOCK_IRQSAVE is not set
+CONFIG_INLINE_SPIN_UNLOCK=y
+# CONFIG_INLINE_SPIN_UNLOCK_BH is not set
+CONFIG_INLINE_SPIN_UNLOCK_IRQ=y
+# CONFIG_INLINE_SPIN_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_READ_TRYLOCK is not set
+# CONFIG_INLINE_READ_LOCK is not set
+# CONFIG_INLINE_READ_LOCK_BH is not set
+# CONFIG_INLINE_READ_LOCK_IRQ is not set
+# CONFIG_INLINE_READ_LOCK_IRQSAVE is not set
+CONFIG_INLINE_READ_UNLOCK=y
+# CONFIG_INLINE_READ_UNLOCK_BH is not set
+CONFIG_INLINE_READ_UNLOCK_IRQ=y
+# CONFIG_INLINE_READ_UNLOCK_IRQRESTORE is not set
+# CONFIG_INLINE_WRITE_TRYLOCK is not set
+# CONFIG_INLINE_WRITE_LOCK is not set
+# CONFIG_INLINE_WRITE_LOCK_BH is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQ is not set
+# CONFIG_INLINE_WRITE_LOCK_IRQSAVE is not set
+CONFIG_INLINE_WRITE_UNLOCK=y
+# CONFIG_INLINE_WRITE_UNLOCK_BH is not set
+CONFIG_INLINE_WRITE_UNLOCK_IRQ=y
+# CONFIG_INLINE_WRITE_UNLOCK_IRQRESTORE is not set
+CONFIG_MUTEX_SPIN_ON_OWNER=y
+
+#
+# Tilera-specific configuration
+#
+CONFIG_NR_CPUS=64
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_GENERIC_CLOCKEVENTS_BUILD=y
+CONFIG_HZ_100=y
+# CONFIG_HZ_250 is not set
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=100
+CONFIG_SCHED_HRTICK=y
+# CONFIG_KEXEC is not set
+CONFIG_HIGHMEM=y
+CONFIG_NUMA=y
+CONFIG_NODES_SHIFT=2
+# CONFIG_VMSPLIT_3_75G is not set
+# CONFIG_VMSPLIT_3_5G is not set
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_2_75G is not set
+# CONFIG_VMSPLIT_2_5G is not set
+# CONFIG_VMSPLIT_2_25G is not set
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_DISCONTIGMEM_MANUAL=y
+CONFIG_DISCONTIGMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_NEED_MULTIPLE_NODES=y
+CONFIG_PAGEFLAGS_EXTENDED=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_COMPACTION is not set
+CONFIG_MIGRATION=y
+CONFIG_PHYS_ADDR_T_64BIT=y
+CONFIG_ZONE_DMA_FLAG=0
+CONFIG_BOUNCE=y
+CONFIG_VIRT_TO_BUS=y
+# CONFIG_KSM is not set
+CONFIG_DEFAULT_MMAP_MIN_ADDR=4096
+# CONFIG_CMDLINE_BOOL is not set
+CONFIG_VMALLOC_RESERVE=0x1000000
+CONFIG_HARDWALL=y
+CONFIG_KERNEL_PL=1
+
+#
+# Bus options
+#
+CONFIG_PCI=y
+CONFIG_PCI_DOMAINS=y
+# CONFIG_NO_IOMEM is not set
+# CONFIG_NO_IOPORT is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCI_DEBUG is not set
+# CONFIG_PCI_STUB is not set
+# CONFIG_PCI_IOV is not set
+# CONFIG_HOTPLUG_PCI is not set
+
+#
+# Executable file formats
+#
+CONFIG_KCORE_ELF=y
+CONFIG_BINFMT_ELF=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+# CONFIG_HAVE_AOUT is not set
+# CONFIG_BINFMT_MISC is not set
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+# CONFIG_XFRM_USER is not set
+# CONFIG_XFRM_SUB_POLICY is not set
+# CONFIG_XFRM_MIGRATE is not set
+# CONFIG_XFRM_STATISTICS is not set
+# CONFIG_NET_KEY is not set
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+# CONFIG_IP_ADVANCED_ROUTER is not set
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE_DEMUX is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+# CONFIG_SYN_COOKIES is not set
+# CONFIG_INET_AH is not set
+# CONFIG_INET_ESP is not set
+# CONFIG_INET_IPCOMP is not set
+# CONFIG_INET_XFRM_TUNNEL is not set
+CONFIG_INET_TUNNEL=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_LRO is not set
+# CONFIG_INET_DIAG is not set
+# CONFIG_TCP_CONG_ADVANCED is not set
+CONFIG_TCP_CONG_CUBIC=y
+CONFIG_DEFAULT_TCP_CONG="cubic"
+# CONFIG_TCP_MD5SIG is not set
+CONFIG_IPV6=y
+# CONFIG_IPV6_PRIVACY is not set
+# CONFIG_IPV6_ROUTER_PREF is not set
+# CONFIG_IPV6_OPTIMISTIC_DAD is not set
+# CONFIG_INET6_AH is not set
+# CONFIG_INET6_ESP is not set
+# CONFIG_INET6_IPCOMP is not set
+# CONFIG_IPV6_MIP6 is not set
+# CONFIG_INET6_XFRM_TUNNEL is not set
+# CONFIG_INET6_TUNNEL is not set
+CONFIG_INET6_XFRM_MODE_TRANSPORT=y
+CONFIG_INET6_XFRM_MODE_TUNNEL=y
+CONFIG_INET6_XFRM_MODE_BEET=y
+# CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION is not set
+CONFIG_IPV6_SIT=y
+# CONFIG_IPV6_SIT_6RD is not set
+CONFIG_IPV6_NDISC_NODETYPE=y
+# CONFIG_IPV6_TUNNEL is not set
+# CONFIG_IPV6_MULTIPLE_TABLES is not set
+# CONFIG_IPV6_MROUTE is not set
+# CONFIG_NETWORK_SECMARK is not set
+# CONFIG_NETWORK_PHY_TIMESTAMPING is not set
+# CONFIG_NETFILTER is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_RDS is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_L2TP is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_NET_DSA is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+# CONFIG_PHONET is not set
+# CONFIG_IEEE802154 is not set
+# CONFIG_NET_SCHED is not set
+# CONFIG_DCB is not set
+# CONFIG_BATMAN_ADV is not set
+CONFIG_RPS=y
+CONFIG_RFS_ACCEL=y
+CONFIG_XPS=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_CAN is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+# CONFIG_WIRELESS is not set
+# CONFIG_WIMAX is not set
+# CONFIG_RFKILL is not set
+# CONFIG_NET_9P is not set
+# CONFIG_CAIF is not set
+# CONFIG_CEPH_LIB is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+# CONFIG_DEVTMPFS is not set
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+CONFIG_FIRMWARE_IN_KERNEL=y
+CONFIG_EXTRA_FIRMWARE=""
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+# CONFIG_CONNECTOR is not set
+# CONFIG_MTD is not set
+# CONFIG_PARPORT is not set
+CONFIG_BLK_DEV=y
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+# CONFIG_BLK_DEV_LOOP is not set
+
+#
+# DRBD disabled because PROC_FS, INET or CONNECTOR not selected
+#
+# CONFIG_BLK_DEV_NBD is not set
+# CONFIG_BLK_DEV_SX8 is not set
+# CONFIG_BLK_DEV_RAM is not set
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+# CONFIG_BLK_DEV_RBD is not set
+# CONFIG_SENSORS_LIS3LV02D is not set
+CONFIG_MISC_DEVICES=y
+# CONFIG_PHANTOM is not set
+# CONFIG_SGI_IOC4 is not set
+# CONFIG_TIFM_CORE is not set
+# CONFIG_ENCLOSURE_SERVICES is not set
+# CONFIG_HP_ILO is not set
+# CONFIG_PCH_PHUB is not set
+# CONFIG_C2PORT is not set
+
+#
+# EEPROM support
+#
+# CONFIG_EEPROM_93CX6 is not set
+# CONFIG_CB710_CORE is not set
+
+#
+# Texas Instruments shared transport line discipline
+#
+
+#
+# SCSI device support
+#
+CONFIG_SCSI_MOD=y
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+CONFIG_SCSI_DMA=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+# CONFIG_BLK_DEV_SR is not set
+# CONFIG_CHR_DEV_SG is not set
+# CONFIG_CHR_DEV_SCH is not set
+# CONFIG_SCSI_MULTI_LUN is not set
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_LOGGING=y
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+# CONFIG_SCSI_SRP_ATTRS is not set
+CONFIG_SCSI_LOWLEVEL=y
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_ISCSI_BOOT_SYSFS is not set
+# CONFIG_SCSI_CXGB3_ISCSI is not set
+# CONFIG_SCSI_CXGB4_ISCSI is not set
+# CONFIG_SCSI_BNX2_ISCSI is not set
+# CONFIG_SCSI_BNX2X_FCOE is not set
+# CONFIG_BE2ISCSI is not set
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_HPSA is not set
+# CONFIG_SCSI_3W_9XXX is not set
+# CONFIG_SCSI_3W_SAS is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_AIC79XX is not set
+# CONFIG_SCSI_AIC94XX is not set
+# CONFIG_SCSI_MVSAS is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_ARCMSR is not set
+# CONFIG_MEGARAID_NEWGEN is not set
+# CONFIG_MEGARAID_LEGACY is not set
+# CONFIG_MEGARAID_SAS is not set
+# CONFIG_SCSI_MPT2SAS is not set
+# CONFIG_SCSI_HPTIOP is not set
+# CONFIG_LIBFC is not set
+# CONFIG_LIBFCOE is not set
+# CONFIG_FCOE is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_IPS is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_STEX is not set
+# CONFIG_SCSI_SYM53C8XX_2 is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLA_FC is not set
+# CONFIG_SCSI_QLA_ISCSI is not set
+# CONFIG_SCSI_LPFC is not set
+# CONFIG_SCSI_DC395x is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_NSP32 is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_PMCRAID is not set
+# CONFIG_SCSI_PM8001 is not set
+# CONFIG_SCSI_SRP is not set
+# CONFIG_SCSI_BFA_FC is not set
+# CONFIG_SCSI_LOWLEVEL_PCMCIA is not set
+# CONFIG_SCSI_DH is not set
+# CONFIG_SCSI_OSD_INITIATOR is not set
+# CONFIG_ATA is not set
+# CONFIG_MD is not set
+# CONFIG_TARGET_CORE is not set
+# CONFIG_FUSION is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_FIREWIRE_NOSY is not set
+# CONFIG_I2O is not set
+CONFIG_NETDEVICES=y
+# CONFIG_DUMMY is not set
+# CONFIG_BONDING is not set
+# CONFIG_MACVLAN is not set
+# CONFIG_EQUALIZER is not set
+CONFIG_TUN=y
+# CONFIG_VETH is not set
+# CONFIG_ARCNET is not set
+# CONFIG_MII is not set
+# CONFIG_PHYLIB is not set
+# CONFIG_NET_ETHERNET is not set
+CONFIG_NETDEV_1000=y
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_E1000E is not set
+# CONFIG_IP1000 is not set
+# CONFIG_IGB is not set
+# CONFIG_IGBVF is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SIS190 is not set
+# CONFIG_SKGE is not set
+# CONFIG_SKY2 is not set
+# CONFIG_VIA_VELOCITY is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+# CONFIG_CNIC is not set
+# CONFIG_QLA3XXX is not set
+# CONFIG_ATL1 is not set
+# CONFIG_ATL1E is not set
+# CONFIG_ATL1C is not set
+# CONFIG_JME is not set
+# CONFIG_STMMAC_ETH is not set
+# CONFIG_PCH_GBE is not set
+# CONFIG_NETDEV_10000 is not set
+# CONFIG_TR is not set
+# CONFIG_WLAN is not set
+
+#
+# Enable WiMAX (Networking options) to see the WiMAX drivers
+#
+# CONFIG_WAN is not set
+
+#
+# CAIF transport drivers
+#
+CONFIG_TILE_NET=y
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+# CONFIG_PPP is not set
+# CONFIG_SLIP is not set
+# CONFIG_NET_FC is not set
+# CONFIG_NETCONSOLE is not set
+# CONFIG_NETPOLL is not set
+# CONFIG_NET_POLL_CONTROLLER is not set
+# CONFIG_VMXNET3 is not set
+# CONFIG_ISDN is not set
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+# CONFIG_INPUT_SPARSEKMAP is not set
+
+#
+# Userland interfaces
+#
+# CONFIG_INPUT_MOUSEDEV is not set
+# CONFIG_INPUT_JOYDEV is not set
+# CONFIG_INPUT_EVDEV is not set
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+# CONFIG_INPUT_MISC is not set
+
+#
+# Hardware I/O ports
+#
+# CONFIG_SERIO is not set
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+# CONFIG_VT is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+# CONFIG_NOZOMI is not set
+# CONFIG_N_GSM is not set
+CONFIG_DEVKMEM=y
+
+#
+# Serial drivers
+#
+# CONFIG_SERIAL_8250 is not set
+
+#
+# Non-8250 serial port support
+#
+# CONFIG_SERIAL_MFD_HSU is not set
+# CONFIG_SERIAL_JSM is not set
+# CONFIG_SERIAL_TIMBERDALE is not set
+# CONFIG_SERIAL_ALTERA_JTAGUART is not set
+# CONFIG_SERIAL_ALTERA_UART is not set
+# CONFIG_SERIAL_PCH_UART is not set
+# CONFIG_TTY_PRINTK is not set
+CONFIG_HVC_DRIVER=y
+# CONFIG_IPMI_HANDLER is not set
+# CONFIG_HW_RANDOM is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+
+#
+# PCMCIA character devices
+#
+# CONFIG_RAW_DRIVER is not set
+# CONFIG_TCG_TPM is not set
+CONFIG_DEVPORT=y
+# CONFIG_RAMOOPS is not set
+# CONFIG_I2C is not set
+# CONFIG_SPI is not set
+
+#
+# PPS support
+#
+# CONFIG_PPS is not set
+
+#
+# PPS generators support
+#
+# CONFIG_W1 is not set
+# CONFIG_POWER_SUPPLY is not set
+CONFIG_HWMON=y
+# CONFIG_HWMON_VID is not set
+# CONFIG_HWMON_DEBUG_CHIP is not set
+
+#
+# Native drivers
+#
+# CONFIG_SENSORS_I5K_AMB is not set
+# CONFIG_SENSORS_F71805F is not set
+# CONFIG_SENSORS_F71882FG is not set
+# CONFIG_SENSORS_IT87 is not set
+# CONFIG_SENSORS_PC87360 is not set
+# CONFIG_SENSORS_PC87427 is not set
+# CONFIG_SENSORS_SIS5595 is not set
+# CONFIG_SENSORS_SMSC47M1 is not set
+# CONFIG_SENSORS_SMSC47B397 is not set
+# CONFIG_SENSORS_SCH5627 is not set
+# CONFIG_SENSORS_VIA686A is not set
+# CONFIG_SENSORS_VT1211 is not set
+# CONFIG_SENSORS_VT8231 is not set
+# CONFIG_SENSORS_W83627HF is not set
+# CONFIG_SENSORS_W83627EHF is not set
+# CONFIG_THERMAL is not set
+CONFIG_WATCHDOG=y
+CONFIG_WATCHDOG_NOWAYOUT=y
+
+#
+# Watchdog Device Drivers
+#
+# CONFIG_SOFT_WATCHDOG is not set
+# CONFIG_ALIM7101_WDT is not set
+
+#
+# PCI-based Watchdog Cards
+#
+# CONFIG_PCIPCWATCHDOG is not set
+# CONFIG_WDTPCI is not set
+CONFIG_SSB_POSSIBLE=y
+
+#
+# Sonics Silicon Backplane
+#
+# CONFIG_SSB is not set
+CONFIG_MFD_SUPPORT=y
+# CONFIG_MFD_CORE is not set
+# CONFIG_MFD_SM501 is not set
+# CONFIG_HTC_PASIC3 is not set
+# CONFIG_MFD_TMIO is not set
+# CONFIG_ABX500_CORE is not set
+# CONFIG_LPC_SCH is not set
+# CONFIG_MFD_RDC321X is not set
+# CONFIG_MFD_JANZ_CMODIO is not set
+# CONFIG_MFD_VX855 is not set
+# CONFIG_REGULATOR is not set
+# CONFIG_MEDIA_SUPPORT is not set
+
+#
+# Graphics support
+#
+CONFIG_VGA_ARB=y
+CONFIG_VGA_ARB_MAX_GPUS=16
+# CONFIG_DRM is not set
+# CONFIG_STUB_POULSBO is not set
+# CONFIG_VGASTATE is not set
+# CONFIG_VIDEO_OUTPUT_CONTROL is not set
+# CONFIG_FB is not set
+# CONFIG_BACKLIGHT_LCD_SUPPORT is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+# CONFIG_SOUND is not set
+# CONFIG_HID_SUPPORT is not set
+CONFIG_USB_SUPPORT=y
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+# CONFIG_USB is not set
+# CONFIG_USB_OTG_WHITELIST is not set
+# CONFIG_USB_OTG_BLACKLIST_HUB is not set
+
+#
+# Enable Host or Gadget support to see Inventra options
+#
+
+#
+# NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may
+#
+# CONFIG_USB_GADGET is not set
+
+#
+# OTG and related infrastructure
+#
+# CONFIG_UWB is not set
+# CONFIG_MMC is not set
+# CONFIG_MEMSTICK is not set
+# CONFIG_NEW_LEDS is not set
+# CONFIG_NFC_DEVICES is not set
+# CONFIG_ACCESSIBILITY is not set
+# CONFIG_INFINIBAND is not set
+CONFIG_EDAC=y
+
+#
+# Reporting subsystems
+#
+# CONFIG_EDAC_DEBUG is not set
+CONFIG_EDAC_MM_EDAC=y
+CONFIG_EDAC_TILE=y
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_HCTOSYS=y
+CONFIG_RTC_HCTOSYS_DEVICE="rtc0"
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+# CONFIG_RTC_INTF_SYSFS is not set
+# CONFIG_RTC_INTF_PROC is not set
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# SPI RTC drivers
+#
+
+#
+# Platform RTC drivers
+#
+# CONFIG_RTC_DRV_DS1286 is not set
+# CONFIG_RTC_DRV_DS1511 is not set
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_STK17TA8 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_M48T35 is not set
+# CONFIG_RTC_DRV_M48T59 is not set
+# CONFIG_RTC_DRV_MSM6242 is not set
+# CONFIG_RTC_DRV_BQ4802 is not set
+# CONFIG_RTC_DRV_RP5C01 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+CONFIG_RTC_DRV_TILE=y
+# CONFIG_DMADEVICES is not set
+# CONFIG_AUXDISPLAY is not set
+# CONFIG_UIO is not set
+# CONFIG_STAGING is not set
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+# CONFIG_EXT2_FS_XATTR is not set
+# CONFIG_EXT2_FS_XIP is not set
+CONFIG_EXT3_FS=y
+# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+# CONFIG_EXT3_FS_SECURITY is not set
+# CONFIG_EXT4_FS is not set
+CONFIG_JBD=y
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_BTRFS_FS is not set
+# CONFIG_NILFS2_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+CONFIG_EXPORTFS=y
+CONFIG_FILE_LOCKING=y
+CONFIG_FSNOTIFY=y
+CONFIG_DNOTIFY=y
+CONFIG_INOTIFY_USER=y
+# CONFIG_FANOTIFY is not set
+# CONFIG_QUOTA is not set
+# CONFIG_QUOTACTL is not set
+# CONFIG_AUTOFS4_FS is not set
+CONFIG_FUSE_FS=y
+# CONFIG_CUSE is not set
+
+#
+# Caches
+#
+# CONFIG_FSCACHE is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+# CONFIG_ISO9660_FS is not set
+# CONFIG_UDF_FS is not set
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=m
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+# CONFIG_PROC_KCORE is not set
+CONFIG_PROC_SYSCTL=y
+CONFIG_PROC_PAGE_MONITOR=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+CONFIG_HUGETLBFS=y
+CONFIG_HUGETLB_PAGE=y
+# CONFIG_CONFIGFS_FS is not set
+CONFIG_MISC_FILESYSTEMS=y
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+# CONFIG_LOGFS is not set
+# CONFIG_CRAMFS is not set
+# CONFIG_SQUASHFS is not set
+# CONFIG_VXFS_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_OMFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_ROMFS_FS is not set
+# CONFIG_PSTORE is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+CONFIG_NETWORK_FILESYSTEMS=y
+CONFIG_NFS_FS=m
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+# CONFIG_NFS_V4 is not set
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=m
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=m
+# CONFIG_RPCSEC_GSS_KRB5 is not set
+# CONFIG_CEPH_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+
+#
+# Partition Types
+#
+# CONFIG_PARTITION_ADVANCED is not set
+CONFIG_MSDOS_PARTITION=y
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="iso8859-1"
+CONFIG_NLS_CODEPAGE_437=y
+# CONFIG_NLS_CODEPAGE_737 is not set
+# CONFIG_NLS_CODEPAGE_775 is not set
+# CONFIG_NLS_CODEPAGE_850 is not set
+# CONFIG_NLS_CODEPAGE_852 is not set
+# CONFIG_NLS_CODEPAGE_855 is not set
+# CONFIG_NLS_CODEPAGE_857 is not set
+# CONFIG_NLS_CODEPAGE_860 is not set
+# CONFIG_NLS_CODEPAGE_861 is not set
+# CONFIG_NLS_CODEPAGE_862 is not set
+# CONFIG_NLS_CODEPAGE_863 is not set
+# CONFIG_NLS_CODEPAGE_864 is not set
+# CONFIG_NLS_CODEPAGE_865 is not set
+# CONFIG_NLS_CODEPAGE_866 is not set
+# CONFIG_NLS_CODEPAGE_869 is not set
+# CONFIG_NLS_CODEPAGE_936 is not set
+# CONFIG_NLS_CODEPAGE_950 is not set
+# CONFIG_NLS_CODEPAGE_932 is not set
+# CONFIG_NLS_CODEPAGE_949 is not set
+# CONFIG_NLS_CODEPAGE_874 is not set
+# CONFIG_NLS_ISO8859_8 is not set
+# CONFIG_NLS_CODEPAGE_1250 is not set
+# CONFIG_NLS_CODEPAGE_1251 is not set
+# CONFIG_NLS_ASCII is not set
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_NLS_ISO8859_2 is not set
+# CONFIG_NLS_ISO8859_3 is not set
+# CONFIG_NLS_ISO8859_4 is not set
+# CONFIG_NLS_ISO8859_5 is not set
+# CONFIG_NLS_ISO8859_6 is not set
+# CONFIG_NLS_ISO8859_7 is not set
+# CONFIG_NLS_ISO8859_9 is not set
+# CONFIG_NLS_ISO8859_13 is not set
+# CONFIG_NLS_ISO8859_14 is not set
+# CONFIG_NLS_ISO8859_15 is not set
+# CONFIG_NLS_KOI8_R is not set
+# CONFIG_NLS_KOI8_U is not set
+# CONFIG_NLS_UTF8 is not set
+
+#
+# Kernel hacking
+#
+# CONFIG_PRINTK_TIME is not set
+CONFIG_DEFAULT_MESSAGE_LOGLEVEL=4
+CONFIG_ENABLE_WARN_DEPRECATED=y
+CONFIG_ENABLE_MUST_CHECK=y
+CONFIG_FRAME_WARN=2048
+CONFIG_MAGIC_SYSRQ=y
+# CONFIG_STRIP_ASM_SYMS is not set
+# CONFIG_UNUSED_SYMBOLS is not set
+# CONFIG_DEBUG_FS is not set
+# CONFIG_HEADERS_CHECK is not set
+# CONFIG_DEBUG_SECTION_MISMATCH is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+# CONFIG_LOCKUP_DETECTOR is not set
+# CONFIG_HARDLOCKUP_DETECTOR is not set
+CONFIG_DETECT_HUNG_TASK=y
+# CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0
+CONFIG_SCHED_DEBUG=y
+# CONFIG_SCHEDSTATS is not set
+# CONFIG_TIMER_STATS is not set
+# CONFIG_DEBUG_OBJECTS is not set
+# CONFIG_SLUB_DEBUG_ON is not set
+# CONFIG_SLUB_STATS is not set
+# CONFIG_DEBUG_KMEMLEAK is not set
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+# CONFIG_DEBUG_SPINLOCK is not set
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+# CONFIG_SPARSE_RCU_POINTER is not set
+# CONFIG_LOCK_STAT is not set
+CONFIG_DEBUG_SPINLOCK_SLEEP=y
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+CONFIG_STACKTRACE=y
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_HIGHMEM is not set
+CONFIG_DEBUG_INFO=y
+# CONFIG_DEBUG_INFO_REDUCED is not set
+CONFIG_DEBUG_VM=y
+# CONFIG_DEBUG_WRITECOUNT is not set
+# CONFIG_DEBUG_MEMORY_INIT is not set
+# CONFIG_DEBUG_LIST is not set
+# CONFIG_TEST_LIST_SORT is not set
+# CONFIG_DEBUG_SG is not set
+# CONFIG_DEBUG_NOTIFIERS is not set
+# CONFIG_DEBUG_CREDENTIALS is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_RCU_CPU_STALL_DETECTOR is not set
+# CONFIG_BACKTRACE_SELF_TEST is not set
+# CONFIG_DEBUG_BLOCK_EXT_DEVT is not set
+# CONFIG_DEBUG_FORCE_WEAK_PER_CPU is not set
+# CONFIG_FAULT_INJECTION is not set
+# CONFIG_SYSCTL_SYSCALL_CHECK is not set
+# CONFIG_DEBUG_PAGEALLOC is not set
+CONFIG_TRACING_SUPPORT=y
+CONFIG_FTRACE=y
+# CONFIG_IRQSOFF_TRACER is not set
+# CONFIG_SCHED_TRACER is not set
+# CONFIG_ENABLE_DEFAULT_TRACERS is not set
+CONFIG_BRANCH_PROFILE_NONE=y
+# CONFIG_PROFILE_ANNOTATED_BRANCHES is not set
+# CONFIG_PROFILE_ALL_BRANCHES is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_ATOMIC64_SELFTEST is not set
+# CONFIG_SAMPLES is not set
+# CONFIG_TEST_KSTRTOX is not set
+CONFIG_EARLY_PRINTK=y
+CONFIG_DEBUG_STACKOVERFLOW=y
+# CONFIG_DEBUG_STACK_USAGE is not set
+CONFIG_DEBUG_EXTRA_FLAGS="-femit-struct-debug-baseonly"
+
+#
+# Security options
+#
+# CONFIG_KEYS is not set
+# CONFIG_SECURITY_DMESG_RESTRICT is not set
+# CONFIG_SECURITY is not set
+# CONFIG_SECURITYFS is not set
+CONFIG_DEFAULT_SECURITY_DAC=y
+CONFIG_DEFAULT_SECURITY=""
+CONFIG_CRYPTO=y
+
+#
+# Crypto core or helper
+#
+# CONFIG_CRYPTO_FIPS is not set
+CONFIG_CRYPTO_ALGAPI=m
+CONFIG_CRYPTO_ALGAPI2=m
+CONFIG_CRYPTO_RNG=m
+CONFIG_CRYPTO_RNG2=m
+# CONFIG_CRYPTO_MANAGER is not set
+# CONFIG_CRYPTO_MANAGER2 is not set
+# CONFIG_CRYPTO_GF128MUL is not set
+# CONFIG_CRYPTO_NULL is not set
+# CONFIG_CRYPTO_PCRYPT is not set
+# CONFIG_CRYPTO_CRYPTD is not set
+# CONFIG_CRYPTO_AUTHENC is not set
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Authenticated Encryption with Associated Data
+#
+# CONFIG_CRYPTO_CCM is not set
+# CONFIG_CRYPTO_GCM is not set
+# CONFIG_CRYPTO_SEQIV is not set
+
+#
+# Block modes
+#
+# CONFIG_CRYPTO_CBC is not set
+# CONFIG_CRYPTO_CTR is not set
+# CONFIG_CRYPTO_CTS is not set
+# CONFIG_CRYPTO_ECB is not set
+# CONFIG_CRYPTO_LRW is not set
+# CONFIG_CRYPTO_PCBC is not set
+# CONFIG_CRYPTO_XTS is not set
+
+#
+# Hash modes
+#
+# CONFIG_CRYPTO_HMAC is not set
+# CONFIG_CRYPTO_XCBC is not set
+# CONFIG_CRYPTO_VMAC is not set
+
+#
+# Digest
+#
+# CONFIG_CRYPTO_CRC32C is not set
+# CONFIG_CRYPTO_GHASH is not set
+# CONFIG_CRYPTO_MD4 is not set
+# CONFIG_CRYPTO_MD5 is not set
+# CONFIG_CRYPTO_MICHAEL_MIC is not set
+# CONFIG_CRYPTO_RMD128 is not set
+# CONFIG_CRYPTO_RMD160 is not set
+# CONFIG_CRYPTO_RMD256 is not set
+# CONFIG_CRYPTO_RMD320 is not set
+# CONFIG_CRYPTO_SHA1 is not set
+# CONFIG_CRYPTO_SHA256 is not set
+# CONFIG_CRYPTO_SHA512 is not set
+# CONFIG_CRYPTO_TGR192 is not set
+# CONFIG_CRYPTO_WP512 is not set
+
+#
+# Ciphers
+#
+CONFIG_CRYPTO_AES=m
+# CONFIG_CRYPTO_ANUBIS is not set
+# CONFIG_CRYPTO_ARC4 is not set
+# CONFIG_CRYPTO_BLOWFISH is not set
+# CONFIG_CRYPTO_CAMELLIA is not set
+# CONFIG_CRYPTO_CAST5 is not set
+# CONFIG_CRYPTO_CAST6 is not set
+# CONFIG_CRYPTO_DES is not set
+# CONFIG_CRYPTO_FCRYPT is not set
+# CONFIG_CRYPTO_KHAZAD is not set
+# CONFIG_CRYPTO_SALSA20 is not set
+# CONFIG_CRYPTO_SEED is not set
+# CONFIG_CRYPTO_SERPENT is not set
+# CONFIG_CRYPTO_TEA is not set
+# CONFIG_CRYPTO_TWOFISH is not set
+
+#
+# Compression
+#
+# CONFIG_CRYPTO_DEFLATE is not set
+# CONFIG_CRYPTO_ZLIB is not set
+# CONFIG_CRYPTO_LZO is not set
+
+#
+# Random Number Generation
+#
+CONFIG_CRYPTO_ANSI_CPRNG=m
+# CONFIG_CRYPTO_USER_API_HASH is not set
+# CONFIG_CRYPTO_USER_API_SKCIPHER is not set
+CONFIG_CRYPTO_HW=y
+# CONFIG_CRYPTO_DEV_HIFN_795X is not set
+# CONFIG_BINARY_PRINTF is not set
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_GENERIC_FIND_FIRST_BIT=y
+CONFIG_GENERIC_FIND_NEXT_BIT=y
+CONFIG_GENERIC_FIND_LAST_BIT=y
+# CONFIG_CRC_CCITT is not set
+# CONFIG_CRC16 is not set
+# CONFIG_CRC_T10DIF is not set
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+# CONFIG_CRC7 is not set
+# CONFIG_LIBCRC32C is not set
+CONFIG_ZLIB_INFLATE=y
+# CONFIG_XZ_DEC is not set
+# CONFIG_XZ_DEC_BCJ is not set
+CONFIG_DECOMPRESS_GZIP=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_CPU_RMAP=y
+CONFIG_NLATTR=y
+# CONFIG_AVERAGE is not set
+CONFIG_HAVE_KVM=y
+# CONFIG_VIRTUALIZATION is not set
diff --git a/arch/tile/include/arch/chip_tilegx.h b/arch/tile/include/arch/chip_tilegx.h
new file mode 100644
index 0000000..ea8e4f2
--- /dev/null
+++ b/arch/tile/include/arch/chip_tilegx.h
@@ -0,0 +1,258 @@
+/*
+ * Copyright 2011 Tilera Corporation. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ * NON INFRINGEMENT. See the GNU General Public License for
+ * more details.
+ */
+
+/*
+ * @file
+ * Global header file.
+ * This header file specifies defines for TILE-Gx.
+ */
+
+#ifndef __ARCH_CHIP_H__
+#define __ARCH_CHIP_H__
+
+/** Specify chip version.
+ * When possible, prefer the CHIP_xxx symbols below for future-proofing.
+ * This is intended for cross-compiling; native compilation should
+ * use the predefined __tile_chip__ symbol.
+ */
+#define TILE_CHIP 10
+
+/** Specify chip revision.
+ * This provides for the case of a respin of a particular chip type;
+ * the normal value for this symbol is "0".
+ * This is intended for cross-compiling; native compilation should
+ * use the predefined __tile_chip_rev__ symbol.
+ */
+#define TILE_CHIP_REV 0
+
+/** The name of this architecture. */
+#define CHIP_ARCH_NAME "tilegx"
+
+/** The ELF e_machine type for binaries for this chip. */
+#define CHIP_ELF_TYPE() EM_TILEGX
+
+/** The alternate ELF e_machine type for binaries for this chip. */
+#define CHIP_COMPAT_ELF_TYPE() 0x2597
+
+/** What is the native word size of the machine? */
+#define CHIP_WORD_SIZE() 64
+
+/** How many bits of a virtual address are used. Extra bits must be
+ * the sign extension of the low bits.
+ */
+#define CHIP_VA_WIDTH() 42
+
+/** How many bits are in a physical address? */
+#define CHIP_PA_WIDTH() 40
+
+/** Size of the L2 cache, in bytes. */
+#define CHIP_L2_CACHE_SIZE() 262144
+
+/** Log size of an L2 cache line in bytes. */
+#define CHIP_L2_LOG_LINE_SIZE() 6
+
+/** Size of an L2 cache line, in bytes. */
+#define CHIP_L2_LINE_SIZE() (1 << CHIP_L2_LOG_LINE_SIZE())
+
+/** Associativity of the L2 cache. */
+#define CHIP_L2_ASSOC() 8
+
+/** Size of the L1 data cache, in bytes. */
+#define CHIP_L1D_CACHE_SIZE() 32768
+
+/** Log size of an L1 data cache line in bytes. */
+#define CHIP_L1D_LOG_LINE_SIZE() 6
+
+/** Size of an L1 data cache line, in bytes. */
+#define CHIP_L1D_LINE_SIZE() (1 << CHIP_L1D_LOG_LINE_SIZE())
+
+/** Associativity of the L1 data cache. */
+#define CHIP_L1D_ASSOC() 2
+
+/** Size of the L1 instruction cache, in bytes. */
+#define CHIP_L1I_CACHE_SIZE() 32768
+
+/** Log size of an L1 instruction cache line in bytes. */
+#define CHIP_L1I_LOG_LINE_SIZE() 6
+
+/** Size of an L1 instruction cache line, in bytes. */
+#define CHIP_L1I_LINE_SIZE() (1 << CHIP_L1I_LOG_LINE_SIZE())
+
+/** Associativity of the L1 instruction cache. */
+#define CHIP_L1I_ASSOC() 2
+
+/** Stride with which flush instructions must be issued. */
+#define CHIP_FLUSH_STRIDE() CHIP_L2_LINE_SIZE()
+
+/** Stride with which inv instructions must be issued. */
+#define CHIP_INV_STRIDE() CHIP_L2_LINE_SIZE()
+
+/** Stride with which finv instructions must be issued. */
+#define CHIP_FINV_STRIDE() CHIP_L2_LINE_SIZE()
+
+/** Can the local cache coherently cache data that is homed elsewhere? */
+#define CHIP_HAS_COHERENT_LOCAL_CACHE() 1
+
+/** How many simultaneous outstanding victims can the L2 cache have? */
+#define CHIP_MAX_OUTSTANDING_VICTIMS() 128
+
+/** Does the TLB support the NC and NOALLOC bits? */
+#define CHIP_HAS_NC_AND_NOALLOC_BITS() 1
+
+/** Does the chip support hash-for-home caching? */
+#define CHIP_HAS_CBOX_HOME_MAP() 1
+
+/** Number of entries in the chip's home map tables. */
+#define CHIP_CBOX_HOME_MAP_SIZE() 128
+
+/** Do uncacheable requests miss in the cache regardless of whether
+ * there is matching data? */
+#define CHIP_HAS_ENFORCED_UNCACHEABLE_REQUESTS() 1
+
+/** Does the mf instruction wait for victims? */
+#define CHIP_HAS_MF_WAITS_FOR_VICTIMS() 0
+
+/** Does the chip have an "inv" instruction that doesn't also flush? */
+#define CHIP_HAS_INV() 1
+
+/** Does the chip have a "wh64" instruction? */
+#define CHIP_HAS_WH64() 1
+
+/** Does this chip have a 'dword_align' instruction? */
+#define CHIP_HAS_DWORD_ALIGN() 0
+
+/** Number of performance counters. */
+#define CHIP_PERFORMANCE_COUNTERS() 4
+
+/** Does this chip have auxiliary performance counters? */
+#define CHIP_HAS_AUX_PERF_COUNTERS() 1
+
+/** Is the CBOX_MSR1 SPR supported? */
+#define CHIP_HAS_CBOX_MSR1() 0
+
+/** Is the TILE_RTF_HWM SPR supported? */
+#define CHIP_HAS_TILE_RTF_HWM() 1
+
+/** Is the TILE_WRITE_PENDING SPR supported? */
+#define CHIP_HAS_TILE_WRITE_PENDING() 0
+
+/** Is the PROC_STATUS SPR supported? */
+#define CHIP_HAS_PROC_STATUS_SPR() 1
+
+/** Is the DSTREAM_PF SPR supported? */
+#define CHIP_HAS_DSTREAM_PF() 1
+
+/** Log of the number of mshims we have. */
+#define CHIP_LOG_NUM_MSHIMS() 2
+
+/** Are the bases of the interrupt vector areas fixed? */
+#define CHIP_HAS_FIXED_INTVEC_BASE() 0
+
+/** Are the interrupt masks split up into 2 SPRs? */
+#define CHIP_HAS_SPLIT_INTR_MASK() 0
+
+/** Is the cycle count split up into 2 SPRs? */
+#define CHIP_HAS_SPLIT_CYCLE() 0
+
+/** Does the chip have a static network? */
+#define CHIP_HAS_SN() 0
+
+/** Does the chip have a static network processor? */
+#define CHIP_HAS_SN_PROC() 0
+
+/** Size of the L1 static network processor instruction cache, in bytes. */
+/* #define CHIP_L1SNI_CACHE_SIZE() -- does not apply to chip 10 */
+
+/** Does the chip have DMA support in each tile? */
+#define CHIP_HAS_TILE_DMA() 0
+
+/** Does the chip have the second revision of the directly accessible
+ * dynamic networks? This encapsulates a number of characteristics,
+ * including the absence of the catch-all, the absence of inline message
+ * tags, the absence of support for network context-switching, and so on.
+ */
+#define CHIP_HAS_REV1_XDN() 1
+
+/** Does the chip have cmpexch and similar (fetchadd, exch, etc.)? */
+#define CHIP_HAS_CMPEXCH() 1
+
+/** Does the chip have memory-mapped I/O support? */
+#define CHIP_HAS_MMIO() 1
+
+/** Does the chip have post-completion interrupts? */
+#define CHIP_HAS_POST_COMPLETION_INTERRUPTS() 1
+
+/** Does the chip have native single step support? */
+#define CHIP_HAS_SINGLE_STEP() 1
+
+#ifndef __OPEN_SOURCE__ /* features only relevant to hypervisor-level code */
+
+/** How many entries are present in the instruction TLB? */
+#define CHIP_ITLB_ENTRIES() 16
+
+/** How many entries are present in the data TLB? */
+#define CHIP_DTLB_ENTRIES() 32
+
+/** How many MAF entries does the XAUI shim have? */
+#define CHIP_XAUI_MAF_ENTRIES() 32
+
+/** Does the memory shim have a source-id table? */
+#define CHIP_HAS_MSHIM_SRCID_TABLE() 0
+
+/** Does the L1 instruction cache clear on reset? */
+#define CHIP_HAS_L1I_CLEAR_ON_RESET() 1
+
+/** Does the chip come out of reset with valid coordinates on all tiles?
+ * Note that if defined, this also implies that the upper left is 1,1.
+ */
+#define CHIP_HAS_VALID_TILE_COORD_RESET() 1
+
+/** Does the chip have unified packet formats? */
+#define CHIP_HAS_UNIFIED_PACKET_FORMATS() 1
+
+/** Does the chip support write reordering? */
+#define CHIP_HAS_WRITE_REORDERING() 1
+
+/** Does the chip support Y-X routing as well as X-Y? */
+#define CHIP_HAS_Y_X_ROUTING() 1
+
+/** Is INTCTRL_3 managed with the correct MPL? */
+#define CHIP_HAS_INTCTRL_3_STATUS_FIX() 1
+
+/** Is it possible to configure the chip to be big-endian? */
+#define CHIP_HAS_BIG_ENDIAN_CONFIG() 1
+
+/** Is the CACHE_RED_WAY_OVERRIDDEN SPR supported? */
+#define CHIP_HAS_CACHE_RED_WAY_OVERRIDDEN() 0
+
+/** Is the DIAG_TRACE_WAY SPR supported? */
+#define CHIP_HAS_DIAG_TRACE_WAY() 0
+
+/** Is the MEM_STRIPE_CONFIG SPR supported? */
+#define CHIP_HAS_MEM_STRIPE_CONFIG() 1
+
+/** Are the TLB_PERF SPRs supported? */
+#define CHIP_HAS_TLB_PERF() 1
+
+/** Is the VDN_SNOOP_SHIM_CTL SPR supported? */
+#define CHIP_HAS_VDN_SNOOP_SHIM_CTL() 0
+
+/** Does the chip support rev1 DMA packets? */
+#define CHIP_HAS_REV1_DMA_PACKETS() 1
+
+/** Does the chip have an IPI shim? */
+#define CHIP_HAS_IPI() 1
+
+#endif /* !__OPEN_SOURCE__ */
+#endif /* __ARCH_CHIP_H__ */
diff --git a/arch/tile/include/arch/icache.h b/arch/tile/include/arch/icache.h
index 5c87c90..762eafa 100644
--- a/arch/tile/include/arch/icache.h
+++ b/arch/tile/include/arch/icache.h
@@ -16,7 +16,7 @@
/**
* @file
*
- * Support for invalidating bytes in the instruction
+ * Support for invalidating bytes in the instruction cache.
*/
#ifndef __ARCH_ICACHE_H__
@@ -30,11 +30,10 @@
*
* @param addr The start of memory to be invalidated.
* @param size The number of bytes to be invalidated.
- * @param page_size The system's page size, typically the PAGE_SIZE constant
- * in sys/page.h. This value must be a power of two no larger
- * than the page containing the code to be invalidated. If the value
- * is smaller than the actual page size, this function will still
- * work, but may run slower than necessary.
+ * @param page_size The system's page size, e.g. getpagesize() in userspace.
+ * This value must be a power of two no larger than the page containing
+ * the code to be invalidated. If the value is smaller than the actual page
+ * size, this function will still work, but may run slower than necessary.
*/
static __inline void
invalidate_icache(const void* addr, unsigned long size,
diff --git a/arch/tile/include/arch/interrupts_64.h b/arch/tile/include/arch/interrupts_64.h
new file mode 100644
index 0000000..5bb58b2
--- /dev/null
+++ b/arch/tile/include/arch/interrupts_64.h
@@ -0,0 +1,276 @@
+/*
+ * Copyright 2011 Tilera Corporation. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ * NON INFRINGEMENT. See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef __ARCH_INTERRUPTS_H__
+#define __ARCH_INTERRUPTS_H__
+
+/** Mask for an interrupt. */
+#ifdef __ASSEMBLER__
+/* Note: must handle breaking interrupts into high and low words manually. */
+#define INT_MASK(intno) (1 << (intno))
+#else
+#define INT_MASK(intno) (1ULL << (intno))
+#endif
+
+
+/** Where a given interrupt executes */
+#define INTERRUPT_VECTOR(i, pl) (0xFC000000 + ((pl) << 24) + ((i) << 8))
+
+/** Where to store a vector for a given interrupt. */
+#define USER_INTERRUPT_VECTOR(i) INTERRUPT_VECTOR(i, 0)
+
+/** The base address of user-level interrupts. */
+#define USER_INTERRUPT_VECTOR_BASE INTERRUPT_VECTOR(0, 0)
+
+
+/** Additional synthetic interrupt. */
+#define INT_BREAKPOINT (63)
+
+#define INT_MEM_ERROR 0
+#define INT_SINGLE_STEP_3 1
+#define INT_SINGLE_STEP_2 2
+#define INT_SINGLE_STEP_1 3
+#define INT_SINGLE_STEP_0 4
+#define INT_IDN_COMPLETE 5
+#define INT_UDN_COMPLETE 6
+#define INT_ITLB_MISS 7
+#define INT_ILL 8
+#define INT_GPV 9
+#define INT_IDN_ACCESS 10
+#define INT_UDN_ACCESS 11
+#define INT_SWINT_3 12
+#define INT_SWINT_2 13
+#define INT_SWINT_1 14
+#define INT_SWINT_0 15
+#define INT_ILL_TRANS 16
+#define INT_UNALIGN_DATA 17
+#define INT_DTLB_MISS 18
+#define INT_DTLB_ACCESS 19
+#define INT_IDN_FIREWALL 20
+#define INT_UDN_FIREWALL 21
+#define INT_TILE_TIMER 22
+#define INT_AUX_TILE_TIMER 23
+#define INT_IDN_TIMER 24
+#define INT_UDN_TIMER 25
+#define INT_IDN_AVAIL 26
+#define INT_UDN_AVAIL 27
+#define INT_IPI_3 28
+#define INT_IPI_2 29
+#define INT_IPI_1 30
+#define INT_IPI_0 31
+#define INT_PERF_COUNT 32
+#define INT_AUX_PERF_COUNT 33
+#define INT_INTCTRL_3 34
+#define INT_INTCTRL_2 35
+#define INT_INTCTRL_1 36
+#define INT_INTCTRL_0 37
+#define INT_BOOT_ACCESS 38
+#define INT_WORLD_ACCESS 39
+#define INT_I_ASID 40
+#define INT_D_ASID 41
+#define INT_DOUBLE_FAULT 42
+
+#define NUM_INTERRUPTS 43
+
+#ifndef __ASSEMBLER__
+#define QUEUED_INTERRUPTS ( \
+ INT_MASK(INT_MEM_ERROR) | \
+ INT_MASK(INT_IDN_COMPLETE) | \
+ INT_MASK(INT_UDN_COMPLETE) | \
+ INT_MASK(INT_IDN_FIREWALL) | \
+ INT_MASK(INT_UDN_FIREWALL) | \
+ INT_MASK(INT_TILE_TIMER) | \
+ INT_MASK(INT_AUX_TILE_TIMER) | \
+ INT_MASK(INT_IDN_TIMER) | \
+ INT_MASK(INT_UDN_TIMER) | \
+ INT_MASK(INT_IDN_AVAIL) | \
+ INT_MASK(INT_UDN_AVAIL) | \
+ INT_MASK(INT_IPI_3) | \
+ INT_MASK(INT_IPI_2) | \
+ INT_MASK(INT_IPI_1) | \
+ INT_MASK(INT_IPI_0) | \
+ INT_MASK(INT_PERF_COUNT) | \
+ INT_MASK(INT_AUX_PERF_COUNT) | \
+ INT_MASK(INT_INTCTRL_3) | \
+ INT_MASK(INT_INTCTRL_2) | \
+ INT_MASK(INT_INTCTRL_1) | \
+ INT_MASK(INT_INTCTRL_0) | \
+ INT_MASK(INT_BOOT_ACCESS) | \
+ INT_MASK(INT_WORLD_ACCESS) | \
+ INT_MASK(INT_I_ASID) | \
+ INT_MASK(INT_D_ASID) | \
+ INT_MASK(INT_DOUBLE_FAULT) | \
+ 0)
+#define NONQUEUED_INTERRUPTS ( \
+ INT_MASK(INT_SINGLE_STEP_3) | \
+ INT_MASK(INT_SINGLE_STEP_2) | \
+ INT_MASK(INT_SINGLE_STEP_1) | \
+ INT_MASK(INT_SINGLE_STEP_0) | \
+ INT_MASK(INT_ITLB_MISS) | \
+ INT_MASK(INT_ILL) | \
+ INT_MASK(INT_GPV) | \
+ INT_MASK(INT_IDN_ACCESS) | \
+ INT_MASK(INT_UDN_ACCESS) | \
+ INT_MASK(INT_SWINT_3) | \
+ INT_MASK(INT_SWINT_2) | \
+ INT_MASK(INT_SWINT_1) | \
+ INT_MASK(INT_SWINT_0) | \
+ INT_MASK(INT_ILL_TRANS) | \
+ INT_MASK(INT_UNALIGN_DATA) | \
+ INT_MASK(INT_DTLB_MISS) | \
+ INT_MASK(INT_DTLB_ACCESS) | \
+ 0)
+#define CRITICAL_MASKED_INTERRUPTS ( \
+ INT_MASK(INT_MEM_ERROR) | \
+ INT_MASK(INT_SINGLE_STEP_3) | \
+ INT_MASK(INT_SINGLE_STEP_2) | \
+ INT_MASK(INT_SINGLE_STEP_1) | \
+ INT_MASK(INT_SINGLE_STEP_0) | \
+ INT_MASK(INT_IDN_COMPLETE) | \
+ INT_MASK(INT_UDN_COMPLETE) | \
+ INT_MASK(INT_IDN_FIREWALL) | \
+ INT_MASK(INT_UDN_FIREWALL) | \
+ INT_MASK(INT_TILE_TIMER) | \
+ INT_MASK(INT_AUX_TILE_TIMER) | \
+ INT_MASK(INT_IDN_TIMER) | \
+ INT_MASK(INT_UDN_TIMER) | \
+ INT_MASK(INT_IDN_AVAIL) | \
+ INT_MASK(INT_UDN_AVAIL) | \
+ INT_MASK(INT_IPI_3) | \
+ INT_MASK(INT_IPI_2) | \
+ INT_MASK(INT_IPI_1) | \
+ INT_MASK(INT_IPI_0) | \
+ INT_MASK(INT_PERF_COUNT) | \
+ INT_MASK(INT_AUX_PERF_COUNT) | \
+ INT_MASK(INT_INTCTRL_3) | \
+ INT_MASK(INT_INTCTRL_2) | \
+ INT_MASK(INT_INTCTRL_1) | \
+ INT_MASK(INT_INTCTRL_0) | \
+ 0)
+#define CRITICAL_UNMASKED_INTERRUPTS ( \
+ INT_MASK(INT_ITLB_MISS) | \
+ INT_MASK(INT_ILL) | \
+ INT_MASK(INT_GPV) | \
+ INT_MASK(INT_IDN_ACCESS) | \
+ INT_MASK(INT_UDN_ACCESS) | \
+ INT_MASK(INT_SWINT_3) | \
+ INT_MASK(INT_SWINT_2) | \
+ INT_MASK(INT_SWINT_1) | \
+ INT_MASK(INT_SWINT_0) | \
+ INT_MASK(INT_ILL_TRANS) | \
+ INT_MASK(INT_UNALIGN_DATA) | \
+ INT_MASK(INT_DTLB_MISS) | \
+ INT_MASK(INT_DTLB_ACCESS) | \
+ INT_MASK(INT_BOOT_ACCESS) | \
+ INT_MASK(INT_WORLD_ACCESS) | \
+ INT_MASK(INT_I_ASID) | \
+ INT_MASK(INT_D_ASID) | \
+ INT_MASK(INT_DOUBLE_FAULT) | \
+ 0)
+#define MASKABLE_INTERRUPTS ( \
+ INT_MASK(INT_MEM_ERROR) | \
+ INT_MASK(INT_SINGLE_STEP_3) | \
+ INT_MASK(INT_SINGLE_STEP_2) | \
+ INT_MASK(INT_SINGLE_STEP_1) | \
+ INT_MASK(INT_SINGLE_STEP_0) | \
+ INT_MASK(INT_IDN_COMPLETE) | \
+ INT_MASK(INT_UDN_COMPLETE) | \
+ INT_MASK(INT_IDN_FIREWALL) | \
+ INT_MASK(INT_UDN_FIREWALL) | \
+ INT_MASK(INT_TILE_TIMER) | \
+ INT_MASK(INT_AUX_TILE_TIMER) | \
+ INT_MASK(INT_IDN_TIMER) | \
+ INT_MASK(INT_UDN_TIMER) | \
+ INT_MASK(INT_IDN_AVAIL) | \
+ INT_MASK(INT_UDN_AVAIL) | \
+ INT_MASK(INT_IPI_3) | \
+ INT_MASK(INT_IPI_2) | \
+ INT_MASK(INT_IPI_1) | \
+ INT_MASK(INT_IPI_0) | \
+ INT_MASK(INT_PERF_COUNT) | \
+ INT_MASK(INT_AUX_PERF_COUNT) | \
+ INT_MASK(INT_INTCTRL_3) | \
+ INT_MASK(INT_INTCTRL_2) | \
+ INT_MASK(INT_INTCTRL_1) | \
+ INT_MASK(INT_INTCTRL_0) | \
+ 0)
+#define UNMASKABLE_INTERRUPTS ( \
+ INT_MASK(INT_ITLB_MISS) | \
+ INT_MASK(INT_ILL) | \
+ INT_MASK(INT_GPV) | \
+ INT_MASK(INT_IDN_ACCESS) | \
+ INT_MASK(INT_UDN_ACCESS) | \
+ INT_MASK(INT_SWINT_3) | \
+ INT_MASK(INT_SWINT_2) | \
+ INT_MASK(INT_SWINT_1) | \
+ INT_MASK(INT_SWINT_0) | \
+ INT_MASK(INT_ILL_TRANS) | \
+ INT_MASK(INT_UNALIGN_DATA) | \
+ INT_MASK(INT_DTLB_MISS) | \
+ INT_MASK(INT_DTLB_ACCESS) | \
+ INT_MASK(INT_BOOT_ACCESS) | \
+ INT_MASK(INT_WORLD_ACCESS) | \
+ INT_MASK(INT_I_ASID) | \
+ INT_MASK(INT_D_ASID) | \
+ INT_MASK(INT_DOUBLE_FAULT) | \
+ 0)
+#define SYNC_INTERRUPTS ( \
+ INT_MASK(INT_SINGLE_STEP_3) | \
+ INT_MASK(INT_SINGLE_STEP_2) | \
+ INT_MASK(INT_SINGLE_STEP_1) | \
+ INT_MASK(INT_SINGLE_STEP_0) | \
+ INT_MASK(INT_IDN_COMPLETE) | \
+ INT_MASK(INT_UDN_COMPLETE) | \
+ INT_MASK(INT_ITLB_MISS) | \
+ INT_MASK(INT_ILL) | \
+ INT_MASK(INT_GPV) | \
+ INT_MASK(INT_IDN_ACCESS) | \
+ INT_MASK(INT_UDN_ACCESS) | \
+ INT_MASK(INT_SWINT_3) | \
+ INT_MASK(INT_SWINT_2) | \
+ INT_MASK(INT_SWINT_1) | \
+ INT_MASK(INT_SWINT_0) | \
+ INT_MASK(INT_ILL_TRANS) | \
+ INT_MASK(INT_UNALIGN_DATA) | \
+ INT_MASK(INT_DTLB_MISS) | \
+ INT_MASK(INT_DTLB_ACCESS) | \
+ 0)
+#define NON_SYNC_INTERRUPTS ( \
+ INT_MASK(INT_MEM_ERROR) | \
+ INT_MASK(INT_IDN_FIREWALL) | \
+ INT_MASK(INT_UDN_FIREWALL) | \
+ INT_MASK(INT_TILE_TIMER) | \
+ INT_MASK(INT_AUX_TILE_TIMER) | \
+ INT_MASK(INT_IDN_TIMER) | \
+ INT_MASK(INT_UDN_TIMER) | \
+ INT_MASK(INT_IDN_AVAIL) | \
+ INT_MASK(INT_UDN_AVAIL) | \
+ INT_MASK(INT_IPI_3) | \
+ INT_MASK(INT_IPI_2) | \
+ INT_MASK(INT_IPI_1) | \
+ INT_MASK(INT_IPI_0) | \
+ INT_MASK(INT_PERF_COUNT) | \
+ INT_MASK(INT_AUX_PERF_COUNT) | \
+ INT_MASK(INT_INTCTRL_3) | \
+ INT_MASK(INT_INTCTRL_2) | \
+ INT_MASK(INT_INTCTRL_1) | \
+ INT_MASK(INT_INTCTRL_0) | \
+ INT_MASK(INT_BOOT_ACCESS) | \
+ INT_MASK(INT_WORLD_ACCESS) | \
+ INT_MASK(INT_I_ASID) | \
+ INT_MASK(INT_D_ASID) | \
+ INT_MASK(INT_DOUBLE_FAULT) | \
+ 0)
+#endif /* !__ASSEMBLER__ */
+#endif /* !__ARCH_INTERRUPTS_H__ */
diff --git a/arch/tile/include/arch/spr_def.h b/arch/tile/include/arch/spr_def.h
index 442fcba..f548efe 100644
--- a/arch/tile/include/arch/spr_def.h
+++ b/arch/tile/include/arch/spr_def.h
@@ -12,6 +12,15 @@
* more details.
*/
+/* Include the proper base SPR definition file. */
+#ifdef __tilegx__
+#include <arch/spr_def_64.h>
+#else
+#include <arch/spr_def_32.h>
+#endif
+
+#ifdef __KERNEL__
+
/*
* In addition to including the proper base SPR definition file, depending
* on machine architecture, this file defines several macros which allow
@@ -29,7 +38,6 @@
#define _concat4(a, b, c, d) __concat4(a, b, c, d)
#ifdef __tilegx__
-#include <arch/spr_def_64.h>
/* TILE-Gx dependent, protection-level dependent SPRs. */
@@ -65,7 +73,6 @@
_concat4(INT_SINGLE_STEP_, CONFIG_KERNEL_PL,,)
#else
-#include <arch/spr_def_32.h>
/* TILEPro dependent, protection-level dependent SPRs. */
@@ -102,3 +109,5 @@
_concat4(SPR_INTCTRL_, CONFIG_KERNEL_PL, _STATUS,)
#define INT_INTCTRL_K \
_concat4(INT_INTCTRL_, CONFIG_KERNEL_PL,,)
+
+#endif /* __KERNEL__ */
diff --git a/arch/tile/include/arch/spr_def_64.h b/arch/tile/include/arch/spr_def_64.h
new file mode 100644
index 0000000..cd3e5f9
--- /dev/null
+++ b/arch/tile/include/arch/spr_def_64.h
@@ -0,0 +1,173 @@
+/*
+ * Copyright 2011 Tilera Corporation. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ * NON INFRINGEMENT. See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef __DOXYGEN__
+
+#ifndef __ARCH_SPR_DEF_H__
+#define __ARCH_SPR_DEF_H__
+
+#define SPR_AUX_PERF_COUNT_0 0x2105
+#define SPR_AUX_PERF_COUNT_1 0x2106
+#define SPR_AUX_PERF_COUNT_CTL 0x2107
+#define SPR_AUX_PERF_COUNT_STS 0x2108
+#define SPR_CMPEXCH_VALUE 0x2780
+#define SPR_CYCLE 0x2781
+#define SPR_DONE 0x2705
+#define SPR_DSTREAM_PF 0x2706
+#define SPR_EVENT_BEGIN 0x2782
+#define SPR_EVENT_END 0x2783
+#define SPR_EX_CONTEXT_0_0 0x2580
+#define SPR_EX_CONTEXT_0_1 0x2581
+#define SPR_EX_CONTEXT_0_1__PL_SHIFT 0
+#define SPR_EX_CONTEXT_0_1__PL_RMASK 0x3
+#define SPR_EX_CONTEXT_0_1__PL_MASK 0x3
+#define SPR_EX_CONTEXT_0_1__ICS_SHIFT 2
+#define SPR_EX_CONTEXT_0_1__ICS_RMASK 0x1
+#define SPR_EX_CONTEXT_0_1__ICS_MASK 0x4
+#define SPR_EX_CONTEXT_1_0 0x2480
+#define SPR_EX_CONTEXT_1_1 0x2481
+#define SPR_EX_CONTEXT_1_1__PL_SHIFT 0
+#define SPR_EX_CONTEXT_1_1__PL_RMASK 0x3
+#define SPR_EX_CONTEXT_1_1__PL_MASK 0x3
+#define SPR_EX_CONTEXT_1_1__ICS_SHIFT 2
+#define SPR_EX_CONTEXT_1_1__ICS_RMASK 0x1
+#define SPR_EX_CONTEXT_1_1__ICS_MASK 0x4
+#define SPR_EX_CONTEXT_2_0 0x2380
+#define SPR_EX_CONTEXT_2_1 0x2381
+#define SPR_EX_CONTEXT_2_1__PL_SHIFT 0
+#define SPR_EX_CONTEXT_2_1__PL_RMASK 0x3
+#define SPR_EX_CONTEXT_2_1__PL_MASK 0x3
+#define SPR_EX_CONTEXT_2_1__ICS_SHIFT 2
+#define SPR_EX_CONTEXT_2_1__ICS_RMASK 0x1
+#define SPR_EX_CONTEXT_2_1__ICS_MASK 0x4
+#define SPR_FAIL 0x2707
+#define SPR_ILL_TRANS_REASON__I_STREAM_VA_RMASK 0x1
+#define SPR_INTCTRL_0_STATUS 0x2505
+#define SPR_INTCTRL_1_STATUS 0x2405
+#define SPR_INTCTRL_2_STATUS 0x2305
+#define SPR_INTERRUPT_CRITICAL_SECTION 0x2708
+#define SPR_INTERRUPT_MASK_0 0x2506
+#define SPR_INTERRUPT_MASK_1 0x2406
+#define SPR_INTERRUPT_MASK_2 0x2306
+#define SPR_INTERRUPT_MASK_RESET_0 0x2507
+#define SPR_INTERRUPT_MASK_RESET_1 0x2407
+#define SPR_INTERRUPT_MASK_RESET_2 0x2307
+#define SPR_INTERRUPT_MASK_SET_0 0x2508
+#define SPR_INTERRUPT_MASK_SET_1 0x2408
+#define SPR_INTERRUPT_MASK_SET_2 0x2308
+#define SPR_INTERRUPT_VECTOR_BASE_0 0x2509
+#define SPR_INTERRUPT_VECTOR_BASE_1 0x2409
+#define SPR_INTERRUPT_VECTOR_BASE_2 0x2309
+#define SPR_INTERRUPT_VECTOR_BASE_3 0x2209
+#define SPR_IPI_EVENT_0 0x1f05
+#define SPR_IPI_EVENT_1 0x1e05
+#define SPR_IPI_EVENT_2 0x1d05
+#define SPR_IPI_EVENT_RESET_0 0x1f06
+#define SPR_IPI_EVENT_RESET_1 0x1e06
+#define SPR_IPI_EVENT_RESET_2 0x1d06
+#define SPR_IPI_EVENT_SET_0 0x1f07
+#define SPR_IPI_EVENT_SET_1 0x1e07
+#define SPR_IPI_EVENT_SET_2 0x1d07
+#define SPR_IPI_MASK_0 0x1f08
+#define SPR_IPI_MASK_1 0x1e08
+#define SPR_IPI_MASK_2 0x1d08
+#define SPR_IPI_MASK_RESET_0 0x1f09
+#define SPR_IPI_MASK_RESET_1 0x1e09
+#define SPR_IPI_MASK_RESET_2 0x1d09
+#define SPR_IPI_MASK_SET_0 0x1f0a
+#define SPR_IPI_MASK_SET_1 0x1e0a
+#define SPR_IPI_MASK_SET_2 0x1d0a
+#define SPR_MPL_AUX_TILE_TIMER_SET_0 0x1700
+#define SPR_MPL_AUX_TILE_TIMER_SET_1 0x1701
+#define SPR_MPL_AUX_TILE_TIMER_SET_2 0x1702
+#define SPR_MPL_INTCTRL_0_SET_0 0x2500
+#define SPR_MPL_INTCTRL_0_SET_1 0x2501
+#define SPR_MPL_INTCTRL_0_SET_2 0x2502
+#define SPR_MPL_INTCTRL_1_SET_0 0x2400
+#define SPR_MPL_INTCTRL_1_SET_1 0x2401
+#define SPR_MPL_INTCTRL_1_SET_2 0x2402
+#define SPR_MPL_INTCTRL_2_SET_0 0x2300
+#define SPR_MPL_INTCTRL_2_SET_1 0x2301
+#define SPR_MPL_INTCTRL_2_SET_2 0x2302
+#define SPR_MPL_UDN_ACCESS_SET_0 0x0b00
+#define SPR_MPL_UDN_ACCESS_SET_1 0x0b01
+#define SPR_MPL_UDN_ACCESS_SET_2 0x0b02
+#define SPR_MPL_UDN_AVAIL_SET_0 0x1b00
+#define SPR_MPL_UDN_AVAIL_SET_1 0x1b01
+#define SPR_MPL_UDN_AVAIL_SET_2 0x1b02
+#define SPR_MPL_UDN_COMPLETE_SET_0 0x0600
+#define SPR_MPL_UDN_COMPLETE_SET_1 0x0601
+#define SPR_MPL_UDN_COMPLETE_SET_2 0x0602
+#define SPR_MPL_UDN_FIREWALL_SET_0 0x1500
+#define SPR_MPL_UDN_FIREWALL_SET_1 0x1501
+#define SPR_MPL_UDN_FIREWALL_SET_2 0x1502
+#define SPR_MPL_UDN_TIMER_SET_0 0x1900
+#define SPR_MPL_UDN_TIMER_SET_1 0x1901
+#define SPR_MPL_UDN_TIMER_SET_2 0x1902
+#define SPR_MPL_WORLD_ACCESS_SET_0 0x2700
+#define SPR_MPL_WORLD_ACCESS_SET_1 0x2701
+#define SPR_MPL_WORLD_ACCESS_SET_2 0x2702
+#define SPR_PASS 0x2709
+#define SPR_PERF_COUNT_0 0x2005
+#define SPR_PERF_COUNT_1 0x2006
+#define SPR_PERF_COUNT_CTL 0x2007
+#define SPR_PERF_COUNT_DN_CTL 0x2008
+#define SPR_PERF_COUNT_STS 0x2009
+#define SPR_PROC_STATUS 0x2784
+#define SPR_SIM_CONTROL 0x2785
+#define SPR_SINGLE_STEP_CONTROL_0 0x0405
+#define SPR_SINGLE_STEP_CONTROL_0__CANCELED_MASK 0x1
+#define SPR_SINGLE_STEP_CONTROL_0__INHIBIT_MASK 0x2
+#define SPR_SINGLE_STEP_CONTROL_1 0x0305
+#define SPR_SINGLE_STEP_CONTROL_1__CANCELED_MASK 0x1
+#define SPR_SINGLE_STEP_CONTROL_1__INHIBIT_MASK 0x2
+#define SPR_SINGLE_STEP_CONTROL_2 0x0205
+#define SPR_SINGLE_STEP_CONTROL_2__CANCELED_MASK 0x1
+#define SPR_SINGLE_STEP_CONTROL_2__INHIBIT_MASK 0x2
+#define SPR_SINGLE_STEP_EN_0_0 0x250a
+#define SPR_SINGLE_STEP_EN_0_1 0x240a
+#define SPR_SINGLE_STEP_EN_0_2 0x230a
+#define SPR_SINGLE_STEP_EN_1_0 0x250b
+#define SPR_SINGLE_STEP_EN_1_1 0x240b
+#define SPR_SINGLE_STEP_EN_1_2 0x230b
+#define SPR_SINGLE_STEP_EN_2_0 0x250c
+#define SPR_SINGLE_STEP_EN_2_1 0x240c
+#define SPR_SINGLE_STEP_EN_2_2 0x230c
+#define SPR_SYSTEM_SAVE_0_0 0x2582
+#define SPR_SYSTEM_SAVE_0_1 0x2583
+#define SPR_SYSTEM_SAVE_0_2 0x2584
+#define SPR_SYSTEM_SAVE_0_3 0x2585
+#define SPR_SYSTEM_SAVE_1_0 0x2482
+#define SPR_SYSTEM_SAVE_1_1 0x2483
+#define SPR_SYSTEM_SAVE_1_2 0x2484
+#define SPR_SYSTEM_SAVE_1_3 0x2485
+#define SPR_SYSTEM_SAVE_2_0 0x2382
+#define SPR_SYSTEM_SAVE_2_1 0x2383
+#define SPR_SYSTEM_SAVE_2_2 0x2384
+#define SPR_SYSTEM_SAVE_2_3 0x2385
+#define SPR_TILE_COORD 0x270b
+#define SPR_TILE_RTF_HWM 0x270c
+#define SPR_TILE_TIMER_CONTROL 0x1605
+#define SPR_UDN_AVAIL_EN 0x1b05
+#define SPR_UDN_DATA_AVAIL 0x0b80
+#define SPR_UDN_DEADLOCK_TIMEOUT 0x1906
+#define SPR_UDN_DEMUX_COUNT_0 0x0b05
+#define SPR_UDN_DEMUX_COUNT_1 0x0b06
+#define SPR_UDN_DEMUX_COUNT_2 0x0b07
+#define SPR_UDN_DEMUX_COUNT_3 0x0b08
+#define SPR_UDN_DIRECTION_PROTECT 0x1505
+
+#endif /* !defined(__ARCH_SPR_DEF_H__) */
+
+#endif /* !defined(__DOXYGEN__) */
diff --git a/arch/tile/include/asm/atomic.h b/arch/tile/include/asm/atomic.h
index 75a1602..739cfe0 100644
--- a/arch/tile/include/asm/atomic.h
+++ b/arch/tile/include/asm/atomic.h
@@ -130,17 +130,52 @@
*/
#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
-
-/*
- * We define xchg() and cmpxchg() in the included headers.
- * Note that we do not define __HAVE_ARCH_CMPXCHG, since that would imply
- * that cmpxchg() is an efficient operation, which is not particularly true.
- */
-
/* Nonexistent functions intended to cause link errors. */
extern unsigned long __xchg_called_with_bad_pointer(void);
extern unsigned long __cmpxchg_called_with_bad_pointer(void);
+#define xchg(ptr, x) \
+ ({ \
+ typeof(*(ptr)) __x; \
+ switch (sizeof(*(ptr))) { \
+ case 4: \
+ __x = (typeof(__x))(typeof(__x-__x))atomic_xchg( \
+ (atomic_t *)(ptr), \
+ (u32)(typeof((x)-(x)))(x)); \
+ break; \
+ case 8: \
+ __x = (typeof(__x))(typeof(__x-__x))atomic64_xchg( \
+ (atomic64_t *)(ptr), \
+ (u64)(typeof((x)-(x)))(x)); \
+ break; \
+ default: \
+ __xchg_called_with_bad_pointer(); \
+ } \
+ __x; \
+ })
+
+#define cmpxchg(ptr, o, n) \
+ ({ \
+ typeof(*(ptr)) __x; \
+ switch (sizeof(*(ptr))) { \
+ case 4: \
+ __x = (typeof(__x))(typeof(__x-__x))atomic_cmpxchg( \
+ (atomic_t *)(ptr), \
+ (u32)(typeof((o)-(o)))(o), \
+ (u32)(typeof((n)-(n)))(n)); \
+ break; \
+ case 8: \
+ __x = (typeof(__x))(typeof(__x-__x))atomic64_cmpxchg( \
+ (atomic64_t *)(ptr), \
+ (u64)(typeof((o)-(o)))(o), \
+ (u64)(typeof((n)-(n)))(n)); \
+ break; \
+ default: \
+ __cmpxchg_called_with_bad_pointer(); \
+ } \
+ __x; \
+ })
+
#define tas(ptr) (xchg((ptr), 1))
#endif /* __ASSEMBLY__ */
diff --git a/arch/tile/include/asm/atomic_32.h b/arch/tile/include/asm/atomic_32.h
index ed359ae..92a8bee 100644
--- a/arch/tile/include/asm/atomic_32.h
+++ b/arch/tile/include/asm/atomic_32.h
@@ -110,16 +110,6 @@
_atomic_xchg(v, n);
}
-#define xchg(ptr, x) ((typeof(*(ptr))) \
- ((sizeof(*(ptr)) == sizeof(atomic_t)) ? \
- atomic_xchg((atomic_t *)(ptr), (long)(x)) : \
- __xchg_called_with_bad_pointer()))
-
-#define cmpxchg(ptr, o, n) ((typeof(*(ptr))) \
- ((sizeof(*(ptr)) == sizeof(atomic_t)) ? \
- atomic_cmpxchg((atomic_t *)(ptr), (long)(o), (long)(n)) : \
- __cmpxchg_called_with_bad_pointer()))
-
/* A 64bit atomic type */
typedef struct {
diff --git a/arch/tile/include/asm/atomic_64.h b/arch/tile/include/asm/atomic_64.h
new file mode 100644
index 0000000..1c1e60d
--- /dev/null
+++ b/arch/tile/include/asm/atomic_64.h
@@ -0,0 +1,156 @@
+/*
+ * Copyright 2011 Tilera Corporation. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ * NON INFRINGEMENT. See the GNU General Public License for
+ * more details.
+ *
+ * Do not include directly; use <asm/atomic.h>.
+ */
+
+#ifndef _ASM_TILE_ATOMIC_64_H
+#define _ASM_TILE_ATOMIC_64_H
+
+#ifndef __ASSEMBLY__
+
+#include <arch/spr_def.h>
+
+/* First, the 32-bit atomic ops that are "real" on our 64-bit platform. */
+
+#define atomic_set(v, i) ((v)->counter = (i))
+
+/*
+ * The smp_mb() operations throughout are to support the fact that
+ * Linux requires memory barriers before and after the operation,
+ * on any routine which updates memory and returns a value.
+ */
+
+static inline int atomic_cmpxchg(atomic_t *v, int o, int n)
+{
+ int val;
+ __insn_mtspr(SPR_CMPEXCH_VALUE, o);
+ smp_mb(); /* barrier for proper semantics */
+ val = __insn_cmpexch4((void *)&v->counter, n);
+ smp_mb(); /* barrier for proper semantics */
+ return val;
+}
+
+static inline int atomic_xchg(atomic_t *v, int n)
+{
+ int val;
+ smp_mb(); /* barrier for proper semantics */
+ val = __insn_exch4((void *)&v->counter, n);
+ smp_mb(); /* barrier for proper semantics */
+ return val;
+}
+
+static inline void atomic_add(int i, atomic_t *v)
+{
+ __insn_fetchadd4((void *)&v->counter, i);
+}
+
+static inline int atomic_add_return(int i, atomic_t *v)
+{
+ int val;
+ smp_mb(); /* barrier for proper semantics */
+ val = __insn_fetchadd4((void *)&v->counter, i) + i;
+ barrier(); /* the "+ i" above will wait on memory */
+ return val;
+}
+
+static inline int atomic_add_unless(atomic_t *v, int a, int u)
+{
+ int guess, oldval = v->counter;
+ do {
+ if (oldval == u)
+ break;
+ guess = oldval;
+ oldval = atomic_cmpxchg(v, guess, guess + a);
+ } while (guess != oldval);
+ return oldval != u;
+}
+
+/* Now the true 64-bit operations. */
+
+#define ATOMIC64_INIT(i) { (i) }
+
+#define atomic64_read(v) ((v)->counter)
+#define atomic64_set(v, i) ((v)->counter = (i))
+
+static inline long atomic64_cmpxchg(atomic64_t *v, long o, long n)
+{
+ long val;
+ smp_mb(); /* barrier for proper semantics */
+ __insn_mtspr(SPR_CMPEXCH_VALUE, o);
+ val = __insn_cmpexch((void *)&v->counter, n);
+ smp_mb(); /* barrier for proper semantics */
+ return val;
+}
+
+static inline long atomic64_xchg(atomic64_t *v, long n)
+{
+ long val;
+ smp_mb(); /* barrier for proper semantics */
+ val = __insn_exch((void *)&v->counter, n);
+ smp_mb(); /* barrier for proper semantics */
+ return val;
+}
+
+static inline void atomic64_add(long i, atomic64_t *v)
+{
+ __insn_fetchadd((void *)&v->counter, i);
+}
+
+static inline long atomic64_add_return(long i, atomic64_t *v)
+{
+ int val;
+ smp_mb(); /* barrier for proper semantics */
+ val = __insn_fetchadd((void *)&v->counter, i) + i;
+ barrier(); /* the "+ i" above will wait on memory */
+ return val;
+}
+
+static inline long atomic64_add_unless(atomic64_t *v, long a, long u)
+{
+ long guess, oldval = v->counter;
+ do {
+ if (oldval == u)
+ break;
+ guess = oldval;
+ oldval = atomic64_cmpxchg(v, guess, guess + a);
+ } while (guess != oldval);
+ return oldval != u;
+}
+
+#define atomic64_sub_return(i, v) atomic64_add_return(-(i), (v))
+#define atomic64_sub(i, v) atomic64_add(-(i), (v))
+#define atomic64_inc_return(v) atomic64_add_return(1, (v))
+#define atomic64_dec_return(v) atomic64_sub_return(1, (v))
+#define atomic64_inc(v) atomic64_add(1, (v))
+#define atomic64_dec(v) atomic64_sub(1, (v))
+
+#define atomic64_inc_and_test(v) (atomic64_inc_return(v) == 0)
+#define atomic64_dec_and_test(v) (atomic64_dec_return(v) == 0)
+#define atomic64_sub_and_test(i, v) (atomic64_sub_return((i), (v)) == 0)
+#define atomic64_add_negative(i, v) (atomic64_add_return((i), (v)) < 0)
+
+#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0)
+
+/* Atomic dec and inc don't implement barrier, so provide them if needed. */
+#define smp_mb__before_atomic_dec() smp_mb()
+#define smp_mb__after_atomic_dec() smp_mb()
+#define smp_mb__before_atomic_inc() smp_mb()
+#define smp_mb__after_atomic_inc() smp_mb()
+
+/* Define this to indicate that cmpxchg is an efficient operation. */
+#define __HAVE_ARCH_CMPXCHG
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* _ASM_TILE_ATOMIC_64_H */
diff --git a/arch/tile/include/asm/backtrace.h b/arch/tile/include/asm/backtrace.h
index f18887d..bd5399a 100644
--- a/arch/tile/include/asm/backtrace.h
+++ b/arch/tile/include/asm/backtrace.h
@@ -12,80 +12,41 @@
* more details.
*/
-#ifndef _TILE_BACKTRACE_H
-#define _TILE_BACKTRACE_H
-
-
+#ifndef _ASM_TILE_BACKTRACE_H
+#define _ASM_TILE_BACKTRACE_H
#include <linux/types.h>
-#include <arch/chip.h>
-
-#if defined(__tile__)
-typedef unsigned long VirtualAddress;
-#elif CHIP_VA_WIDTH() > 32
-typedef unsigned long long VirtualAddress;
-#else
-typedef unsigned int VirtualAddress;
-#endif
-
-
-/** Reads 'size' bytes from 'address' and writes the data to 'result'.
+/* Reads 'size' bytes from 'address' and writes the data to 'result'.
* Returns true if successful, else false (e.g. memory not readable).
*/
typedef bool (*BacktraceMemoryReader)(void *result,
- VirtualAddress address,
+ unsigned long address,
unsigned int size,
void *extra);
typedef struct {
- /** Current PC. */
- VirtualAddress pc;
+ /* Current PC. */
+ unsigned long pc;
- /** Current stack pointer value. */
- VirtualAddress sp;
+ /* Current stack pointer value. */
+ unsigned long sp;
- /** Current frame pointer value (i.e. caller's stack pointer) */
- VirtualAddress fp;
+ /* Current frame pointer value (i.e. caller's stack pointer) */
+ unsigned long fp;
- /** Internal use only: caller's PC for first frame. */
- VirtualAddress initial_frame_caller_pc;
+ /* Internal use only: caller's PC for first frame. */
+ unsigned long initial_frame_caller_pc;
- /** Internal use only: callback to read memory. */
+ /* Internal use only: callback to read memory. */
BacktraceMemoryReader read_memory_func;
- /** Internal use only: arbitrary argument to read_memory_func. */
+ /* Internal use only: arbitrary argument to read_memory_func. */
void *read_memory_func_extra;
} BacktraceIterator;
-/** Initializes a backtracer to start from the given location.
- *
- * If the frame pointer cannot be determined it is set to -1.
- *
- * @param state The state to be filled in.
- * @param read_memory_func A callback that reads memory. If NULL, a default
- * value is provided.
- * @param read_memory_func_extra An arbitrary argument to read_memory_func.
- * @param pc The current PC.
- * @param lr The current value of the 'lr' register.
- * @param sp The current value of the 'sp' register.
- * @param r52 The current value of the 'r52' register.
- */
-extern void backtrace_init(BacktraceIterator *state,
- BacktraceMemoryReader read_memory_func,
- void *read_memory_func_extra,
- VirtualAddress pc, VirtualAddress lr,
- VirtualAddress sp, VirtualAddress r52);
-
-
-/** Advances the backtracing state to the calling frame, returning
- * true iff successful.
- */
-extern bool backtrace_next(BacktraceIterator *state);
-
-
typedef enum {
/* We have no idea what the caller's pc is. */
@@ -138,7 +99,7 @@
};
-/** Internal constants used to define 'info' operands. */
+/* Internal constants used to define 'info' operands. */
enum {
/* 0 and 1 are reserved, as are all negative numbers. */
@@ -147,13 +108,10 @@
CALLER_SP_IN_R52_BASE = 4,
CALLER_SP_OFFSET_BASE = 8,
-
- /* Marks the entry point of certain functions. */
- ENTRY_POINT_INFO_OP = 16
};
-/** Current backtracer state describing where it thinks the caller is. */
+/* Current backtracer state describing where it thinks the caller is. */
typedef struct {
/*
* Public fields
@@ -192,7 +150,13 @@
} CallerLocation;
+extern void backtrace_init(BacktraceIterator *state,
+ BacktraceMemoryReader read_memory_func,
+ void *read_memory_func_extra,
+ unsigned long pc, unsigned long lr,
+ unsigned long sp, unsigned long r52);
+extern bool backtrace_next(BacktraceIterator *state);
-#endif /* _TILE_BACKTRACE_H */
+#endif /* _ASM_TILE_BACKTRACE_H */
diff --git a/arch/tile/include/asm/bitops.h b/arch/tile/include/asm/bitops.h
index 132e6bb..16f1fa5 100644
--- a/arch/tile/include/asm/bitops.h
+++ b/arch/tile/include/asm/bitops.h
@@ -122,6 +122,7 @@
#include <asm-generic/bitops/lock.h>
#include <asm-generic/bitops/find.h>
#include <asm-generic/bitops/sched.h>
+#include <asm-generic/bitops/non-atomic.h>
#include <asm-generic/bitops/le.h>
#endif /* _ASM_TILE_BITOPS_H */
diff --git a/arch/tile/include/asm/bitops_32.h b/arch/tile/include/asm/bitops_32.h
index 2638be5..d31ab90 100644
--- a/arch/tile/include/asm/bitops_32.h
+++ b/arch/tile/include/asm/bitops_32.h
@@ -126,7 +126,6 @@
#define smp_mb__before_clear_bit() smp_mb()
#define smp_mb__after_clear_bit() do {} while (0)
-#include <asm-generic/bitops/non-atomic.h>
#include <asm-generic/bitops/ext2-atomic.h>
#endif /* _ASM_TILE_BITOPS_32_H */
diff --git a/arch/tile/include/asm/bitops_64.h b/arch/tile/include/asm/bitops_64.h
new file mode 100644
index 0000000..99615e8
--- /dev/null
+++ b/arch/tile/include/asm/bitops_64.h
@@ -0,0 +1,105 @@
+/*
+ * Copyright 2011 Tilera Corporation. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ * NON INFRINGEMENT. See the GNU General Public License for
+ * more details.
+ */
+
+#ifndef _ASM_TILE_BITOPS_64_H
+#define _ASM_TILE_BITOPS_64_H
+
+#include <linux/compiler.h>
+#include <asm/atomic.h>
+#include <asm/system.h>
+
+/* See <asm/bitops.h> for API comments. */
+
+static inline void set_bit(unsigned nr, volatile unsigned long *addr)
+{
+ unsigned long mask = (1UL << (nr % BITS_PER_LONG));
+ __insn_fetchor((void *)(addr + nr / BITS_PER_LONG), mask);
+}
+
+static inline void clear_bit(unsigned nr, volatile unsigned long *addr)
+{
+ unsigned long mask = (1UL << (nr % BITS_PER_LONG));
+ __insn_fetchand((void *)(addr + nr / BITS_PER_LONG), ~mask);
+}
+
+#define smp_mb__before_clear_bit() smp_mb()
+#define smp_mb__after_clear_bit() smp_mb()
+
+
+static inline void change_bit(unsigned nr, volatile unsigned long *addr)
+{
+ unsigned long old, mask = (1UL << (nr % BITS_PER_LONG));
+ long guess, oldval;
+ addr += nr / BITS_PER_LONG;
+ old = *addr;
+ do {
+ guess = oldval;
+ oldval = atomic64_cmpxchg((atomic64_t *)addr,
+ guess, guess ^ mask);
+ } while (guess != oldval);
+}
+
+
+/*
+ * The test_and_xxx_bit() routines require a memory fence before we
+ * start the operation, and after the operation completes. We use
+ * smp_mb() before, and rely on the "!= 0" comparison, plus a compiler
+ * barrier(), to block until the atomic op is complete.
+ */
+
+static inline int test_and_set_bit(unsigned nr, volatile unsigned long *addr)
+{
+ int val;
+ unsigned long mask = (1UL << (nr % BITS_PER_LONG));
+ smp_mb(); /* barrier for proper semantics */
+ val = (__insn_fetchor((void *)(addr + nr / BITS_PER_LONG), mask)
+ & mask) != 0;
+ barrier();
+ return val;
+}
+
+
+static inline int test_and_clear_bit(unsigned nr, volatile unsigned long *addr)
+{
+ int val;
+ unsigned long mask = (1UL << (nr % BITS_PER_LONG));
+ smp_mb(); /* barrier for proper semantics */
+ val = (__insn_fetchand((void *)(addr + nr / BITS_PER_LONG), ~mask)
+ & mask) != 0;
+ barrier();
+ return val;
+}
+
+
+static inline int test_and_change_bit(unsigned nr,
+ volatile unsigned long *addr)
+{
+ unsigned long mask = (1UL << (nr % BITS_PER_LONG));
+ long guess, oldval = *addr;
+ addr += nr / BITS_PER_LONG;
+ oldval = *addr;
+ do {
+ guess = oldval;
+ oldval = atomic64_cmpxchg((atomic64_t *)addr,
+ guess, guess ^ mask);
+ } while (guess != oldval);
+ return (oldval & mask) != 0;
+}
+
+#define ext2_set_bit_atomic(lock, nr, addr) \
+ test_and_set_bit((nr), (unsigned long *)(addr))
+#define ext2_clear_bit_atomic(lock, nr, addr) \
+ test_and_clear_bit((nr), (unsigned long *)(addr))
+
+#endif /* _ASM_TILE_BITOPS_64_H */
diff --git a/arch/tile/include/asm/cacheflush.h b/arch/tile/include/asm/cacheflush.h
index 12fb0fb..e925f4b 100644
--- a/arch/tile/include/asm/cacheflush.h
+++ b/arch/tile/include/asm/cacheflush.h
@@ -116,22 +116,28 @@
}
-/* Invalidate a VA range, then memory fence. */
+/* Invalidate a VA range and wait for it to be complete. */
static inline void inv_buffer(void *buffer, size_t size)
{
__inv_buffer(buffer, size);
- mb_incoherent();
+ mb();
}
-/* Flush a VA range, then memory fence. */
-static inline void flush_buffer(void *buffer, size_t size)
+/*
+ * Flush a locally-homecached VA range and wait for the evicted
+ * cachelines to hit memory.
+ */
+static inline void flush_buffer_local(void *buffer, size_t size)
{
__flush_buffer(buffer, size);
mb_incoherent();
}
-/* Flush & invalidate a VA range, then memory fence. */
-static inline void finv_buffer(void *buffer, size_t size)
+/*
+ * Flush and invalidate a locally-homecached VA range and wait for the
+ * evicted cachelines to hit memory.
+ */
+static inline void finv_buffer_local(void *buffer, size_t size)
{
__finv_buffer(buffer, size);
mb_incoherent();
diff --git a/arch/tile/include/asm/compat.h b/arch/tile/include/asm/compat.h
index c3ae570..bf95f55 100644
--- a/arch/tile/include/asm/compat.h
+++ b/arch/tile/include/asm/compat.h
@@ -215,8 +215,8 @@
struct compat_siginfo;
struct compat_sigaltstack;
long compat_sys_execve(const char __user *path,
- const compat_uptr_t __user *argv,
- const compat_uptr_t __user *envp, struct pt_regs *);
+ compat_uptr_t __user *argv,
+ compat_uptr_t __user *envp, struct pt_regs *);
long compat_sys_rt_sigaction(int sig, struct compat_sigaction __user *act,
struct compat_sigaction __user *oact,
size_t sigsetsize);
diff --git a/arch/tile/include/asm/dma-mapping.h b/arch/tile/include/asm/dma-mapping.h
index 15e1dce..eaa06d1 100644
--- a/arch/tile/include/asm/dma-mapping.h
+++ b/arch/tile/include/asm/dma-mapping.h
@@ -65,7 +65,8 @@
extern void dma_sync_single_range_for_device(struct device *, dma_addr_t,
unsigned long offset, size_t,
enum dma_data_direction);
-extern void dma_cache_sync(void *vaddr, size_t, enum dma_data_direction);
+extern void dma_cache_sync(struct device *dev, void *vaddr, size_t,
+ enum dma_data_direction);
static inline int
dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
diff --git a/arch/tile/include/asm/fb.h b/arch/tile/include/asm/fb.h
new file mode 100644
index 0000000..3a4988e
--- /dev/null
+++ b/arch/tile/include/asm/fb.h
@@ -0,0 +1 @@
+#include <asm-generic/fb.h>
diff --git a/arch/tile/include/asm/io.h b/arch/tile/include/asm/io.h
index d3cbb9b..c9ea165 100644
--- a/arch/tile/include/asm/io.h
+++ b/arch/tile/include/asm/io.h
@@ -52,6 +52,7 @@
#endif
#define ioremap_nocache(physaddr, size) ioremap(physaddr, size)
+#define ioremap_wc(physaddr, size) ioremap(physaddr, size)
#define ioremap_writethrough(physaddr, size) ioremap(physaddr, size)
#define ioremap_fullcache(physaddr, size) ioremap(physaddr, size)
@@ -161,6 +162,15 @@
#define iowrite32 writel
#define iowrite64 writeq
+static inline void memset_io(void *dst, int val, size_t len)
+{
+ int x;
+ BUG_ON((unsigned long)dst & 0x3);
+ val = (val & 0xff) * 0x01010101;
+ for (x = 0; x < len; x += 4)
+ writel(val, dst + x);
+}
+
static inline void memcpy_fromio(void *dst, const volatile void __iomem *src,
size_t len)
{
@@ -269,6 +279,11 @@
ioport_panic();
}
+#define ioread16be(addr) be16_to_cpu(ioread16(addr))
+#define ioread32be(addr) be32_to_cpu(ioread32(addr))
+#define iowrite16be(v, addr) iowrite16(be16_to_cpu(v), (addr))
+#define iowrite32be(v, addr) iowrite32(be32_to_cpu(v), (addr))
+
#define ioread8_rep(p, dst, count) \
insb((unsigned long) (p), (dst), (count))
#define ioread16_rep(p, dst, count) \
@@ -283,4 +298,7 @@
#define iowrite32_rep(p, src, count) \
outsl((unsigned long) (p), (src), (count))
+#define virt_to_bus virt_to_phys
+#define bus_to_virt phys_to_virt
+
#endif /* _ASM_TILE_IO_H */
diff --git a/arch/tile/include/asm/irq.h b/arch/tile/include/asm/irq.h
index 572fd3e..94e9a51 100644
--- a/arch/tile/include/asm/irq.h
+++ b/arch/tile/include/asm/irq.h
@@ -23,6 +23,8 @@
/* IRQ numbers used for linux IPIs. */
#define IRQ_RESCHEDULE 1
+#define irq_canonicalize(irq) (irq)
+
void ack_bad_irq(unsigned int irq);
/*
diff --git a/arch/tile/include/asm/mmu_context.h b/arch/tile/include/asm/mmu_context.h
index 9bc0d07..15fb246 100644
--- a/arch/tile/include/asm/mmu_context.h
+++ b/arch/tile/include/asm/mmu_context.h
@@ -100,8 +100,8 @@
__get_cpu_var(current_asid) = asid;
/* Clear cpu from the old mm, and set it in the new one. */
- cpumask_clear_cpu(cpu, &prev->cpu_vm_mask);
- cpumask_set_cpu(cpu, &next->cpu_vm_mask);
+ cpumask_clear_cpu(cpu, mm_cpumask(prev));
+ cpumask_set_cpu(cpu, mm_cpumask(next));
/* Re-load page tables */
install_page_table(next->pgd, asid);
diff --git a/arch/tile/include/asm/opcode-tile_32.h b/arch/tile/include/asm/opcode-tile_32.h
index eda60ec..03df7b1 100644
--- a/arch/tile/include/asm/opcode-tile_32.h
+++ b/arch/tile/include/asm/opcode-tile_32.h
@@ -1502,5 +1502,12 @@
decoded[TILE_MAX_INSTRUCTIONS_PER_BUNDLE]);
+/* Given a set of bundle bits and a specific pipe, returns which
+ * instruction the bundle contains in that pipe.
+ */
+extern const struct tile_opcode *
+find_opcode(tile_bundle_bits bits, tile_pipeline pipe);
+
+
#endif /* opcode_tile_h */
diff --git a/arch/tile/include/asm/opcode-tile_64.h b/arch/tile/include/asm/opcode-tile_64.h
index eda60ec..c063346 100644
--- a/arch/tile/include/asm/opcode-tile_64.h
+++ b/arch/tile/include/asm/opcode-tile_64.h
@@ -5,863 +5,711 @@
#ifndef opcode_tile_h
#define opcode_tile_h
-typedef unsigned long long tile_bundle_bits;
+typedef unsigned long long tilegx_bundle_bits;
enum
{
- TILE_MAX_OPERANDS = 5 /* mm */
+ TILEGX_MAX_OPERANDS = 4 /* bfexts */
};
typedef enum
{
- TILE_OPC_BPT,
- TILE_OPC_INFO,
- TILE_OPC_INFOL,
- TILE_OPC_J,
- TILE_OPC_JAL,
- TILE_OPC_MOVE,
- TILE_OPC_MOVE_SN,
- TILE_OPC_MOVEI,
- TILE_OPC_MOVEI_SN,
- TILE_OPC_MOVELI,
- TILE_OPC_MOVELI_SN,
- TILE_OPC_MOVELIS,
- TILE_OPC_PREFETCH,
- TILE_OPC_RAISE,
- TILE_OPC_ADD,
- TILE_OPC_ADD_SN,
- TILE_OPC_ADDB,
- TILE_OPC_ADDB_SN,
- TILE_OPC_ADDBS_U,
- TILE_OPC_ADDBS_U_SN,
- TILE_OPC_ADDH,
- TILE_OPC_ADDH_SN,
- TILE_OPC_ADDHS,
- TILE_OPC_ADDHS_SN,
- TILE_OPC_ADDI,
- TILE_OPC_ADDI_SN,
- TILE_OPC_ADDIB,
- TILE_OPC_ADDIB_SN,
- TILE_OPC_ADDIH,
- TILE_OPC_ADDIH_SN,
- TILE_OPC_ADDLI,
- TILE_OPC_ADDLI_SN,
- TILE_OPC_ADDLIS,
- TILE_OPC_ADDS,
- TILE_OPC_ADDS_SN,
- TILE_OPC_ADIFFB_U,
- TILE_OPC_ADIFFB_U_SN,
- TILE_OPC_ADIFFH,
- TILE_OPC_ADIFFH_SN,
- TILE_OPC_AND,
- TILE_OPC_AND_SN,
- TILE_OPC_ANDI,
- TILE_OPC_ANDI_SN,
- TILE_OPC_AULI,
- TILE_OPC_AVGB_U,
- TILE_OPC_AVGB_U_SN,
- TILE_OPC_AVGH,
- TILE_OPC_AVGH_SN,
- TILE_OPC_BBNS,
- TILE_OPC_BBNS_SN,
- TILE_OPC_BBNST,
- TILE_OPC_BBNST_SN,
- TILE_OPC_BBS,
- TILE_OPC_BBS_SN,
- TILE_OPC_BBST,
- TILE_OPC_BBST_SN,
- TILE_OPC_BGEZ,
- TILE_OPC_BGEZ_SN,
- TILE_OPC_BGEZT,
- TILE_OPC_BGEZT_SN,
- TILE_OPC_BGZ,
- TILE_OPC_BGZ_SN,
- TILE_OPC_BGZT,
- TILE_OPC_BGZT_SN,
- TILE_OPC_BITX,
- TILE_OPC_BITX_SN,
- TILE_OPC_BLEZ,
- TILE_OPC_BLEZ_SN,
- TILE_OPC_BLEZT,
- TILE_OPC_BLEZT_SN,
- TILE_OPC_BLZ,
- TILE_OPC_BLZ_SN,
- TILE_OPC_BLZT,
- TILE_OPC_BLZT_SN,
- TILE_OPC_BNZ,
- TILE_OPC_BNZ_SN,
- TILE_OPC_BNZT,
- TILE_OPC_BNZT_SN,
- TILE_OPC_BYTEX,
- TILE_OPC_BYTEX_SN,
- TILE_OPC_BZ,
- TILE_OPC_BZ_SN,
- TILE_OPC_BZT,
- TILE_OPC_BZT_SN,
- TILE_OPC_CLZ,
- TILE_OPC_CLZ_SN,
- TILE_OPC_CRC32_32,
- TILE_OPC_CRC32_32_SN,
- TILE_OPC_CRC32_8,
- TILE_OPC_CRC32_8_SN,
- TILE_OPC_CTZ,
- TILE_OPC_CTZ_SN,
- TILE_OPC_DRAIN,
- TILE_OPC_DTLBPR,
- TILE_OPC_DWORD_ALIGN,
- TILE_OPC_DWORD_ALIGN_SN,
- TILE_OPC_FINV,
- TILE_OPC_FLUSH,
- TILE_OPC_FNOP,
- TILE_OPC_ICOH,
- TILE_OPC_ILL,
- TILE_OPC_INTHB,
- TILE_OPC_INTHB_SN,
- TILE_OPC_INTHH,
- TILE_OPC_INTHH_SN,
- TILE_OPC_INTLB,
- TILE_OPC_INTLB_SN,
- TILE_OPC_INTLH,
- TILE_OPC_INTLH_SN,
- TILE_OPC_INV,
- TILE_OPC_IRET,
- TILE_OPC_JALB,
- TILE_OPC_JALF,
- TILE_OPC_JALR,
- TILE_OPC_JALRP,
- TILE_OPC_JB,
- TILE_OPC_JF,
- TILE_OPC_JR,
- TILE_OPC_JRP,
- TILE_OPC_LB,
- TILE_OPC_LB_SN,
- TILE_OPC_LB_U,
- TILE_OPC_LB_U_SN,
- TILE_OPC_LBADD,
- TILE_OPC_LBADD_SN,
- TILE_OPC_LBADD_U,
- TILE_OPC_LBADD_U_SN,
- TILE_OPC_LH,
- TILE_OPC_LH_SN,
- TILE_OPC_LH_U,
- TILE_OPC_LH_U_SN,
- TILE_OPC_LHADD,
- TILE_OPC_LHADD_SN,
- TILE_OPC_LHADD_U,
- TILE_OPC_LHADD_U_SN,
- TILE_OPC_LNK,
- TILE_OPC_LNK_SN,
- TILE_OPC_LW,
- TILE_OPC_LW_SN,
- TILE_OPC_LW_NA,
- TILE_OPC_LW_NA_SN,
- TILE_OPC_LWADD,
- TILE_OPC_LWADD_SN,
- TILE_OPC_LWADD_NA,
- TILE_OPC_LWADD_NA_SN,
- TILE_OPC_MAXB_U,
- TILE_OPC_MAXB_U_SN,
- TILE_OPC_MAXH,
- TILE_OPC_MAXH_SN,
- TILE_OPC_MAXIB_U,
- TILE_OPC_MAXIB_U_SN,
- TILE_OPC_MAXIH,
- TILE_OPC_MAXIH_SN,
- TILE_OPC_MF,
- TILE_OPC_MFSPR,
- TILE_OPC_MINB_U,
- TILE_OPC_MINB_U_SN,
- TILE_OPC_MINH,
- TILE_OPC_MINH_SN,
- TILE_OPC_MINIB_U,
- TILE_OPC_MINIB_U_SN,
- TILE_OPC_MINIH,
- TILE_OPC_MINIH_SN,
- TILE_OPC_MM,
- TILE_OPC_MNZ,
- TILE_OPC_MNZ_SN,
- TILE_OPC_MNZB,
- TILE_OPC_MNZB_SN,
- TILE_OPC_MNZH,
- TILE_OPC_MNZH_SN,
- TILE_OPC_MTSPR,
- TILE_OPC_MULHH_SS,
- TILE_OPC_MULHH_SS_SN,
- TILE_OPC_MULHH_SU,
- TILE_OPC_MULHH_SU_SN,
- TILE_OPC_MULHH_UU,
- TILE_OPC_MULHH_UU_SN,
- TILE_OPC_MULHHA_SS,
- TILE_OPC_MULHHA_SS_SN,
- TILE_OPC_MULHHA_SU,
- TILE_OPC_MULHHA_SU_SN,
- TILE_OPC_MULHHA_UU,
- TILE_OPC_MULHHA_UU_SN,
- TILE_OPC_MULHHSA_UU,
- TILE_OPC_MULHHSA_UU_SN,
- TILE_OPC_MULHL_SS,
- TILE_OPC_MULHL_SS_SN,
- TILE_OPC_MULHL_SU,
- TILE_OPC_MULHL_SU_SN,
- TILE_OPC_MULHL_US,
- TILE_OPC_MULHL_US_SN,
- TILE_OPC_MULHL_UU,
- TILE_OPC_MULHL_UU_SN,
- TILE_OPC_MULHLA_SS,
- TILE_OPC_MULHLA_SS_SN,
- TILE_OPC_MULHLA_SU,
- TILE_OPC_MULHLA_SU_SN,
- TILE_OPC_MULHLA_US,
- TILE_OPC_MULHLA_US_SN,
- TILE_OPC_MULHLA_UU,
- TILE_OPC_MULHLA_UU_SN,
- TILE_OPC_MULHLSA_UU,
- TILE_OPC_MULHLSA_UU_SN,
- TILE_OPC_MULLL_SS,
- TILE_OPC_MULLL_SS_SN,
- TILE_OPC_MULLL_SU,
- TILE_OPC_MULLL_SU_SN,
- TILE_OPC_MULLL_UU,
- TILE_OPC_MULLL_UU_SN,
- TILE_OPC_MULLLA_SS,
- TILE_OPC_MULLLA_SS_SN,
- TILE_OPC_MULLLA_SU,
- TILE_OPC_MULLLA_SU_SN,
- TILE_OPC_MULLLA_UU,
- TILE_OPC_MULLLA_UU_SN,
- TILE_OPC_MULLLSA_UU,
- TILE_OPC_MULLLSA_UU_SN,
- TILE_OPC_MVNZ,
- TILE_OPC_MVNZ_SN,
- TILE_OPC_MVZ,
- TILE_OPC_MVZ_SN,
- TILE_OPC_MZ,
- TILE_OPC_MZ_SN,
- TILE_OPC_MZB,
- TILE_OPC_MZB_SN,
- TILE_OPC_MZH,
- TILE_OPC_MZH_SN,
- TILE_OPC_NAP,
- TILE_OPC_NOP,
- TILE_OPC_NOR,
- TILE_OPC_NOR_SN,
- TILE_OPC_OR,
- TILE_OPC_OR_SN,
- TILE_OPC_ORI,
- TILE_OPC_ORI_SN,
- TILE_OPC_PACKBS_U,
- TILE_OPC_PACKBS_U_SN,
- TILE_OPC_PACKHB,
- TILE_OPC_PACKHB_SN,
- TILE_OPC_PACKHS,
- TILE_OPC_PACKHS_SN,
- TILE_OPC_PACKLB,
- TILE_OPC_PACKLB_SN,
- TILE_OPC_PCNT,
- TILE_OPC_PCNT_SN,
- TILE_OPC_RL,
- TILE_OPC_RL_SN,
- TILE_OPC_RLI,
- TILE_OPC_RLI_SN,
- TILE_OPC_S1A,
- TILE_OPC_S1A_SN,
- TILE_OPC_S2A,
- TILE_OPC_S2A_SN,
- TILE_OPC_S3A,
- TILE_OPC_S3A_SN,
- TILE_OPC_SADAB_U,
- TILE_OPC_SADAB_U_SN,
- TILE_OPC_SADAH,
- TILE_OPC_SADAH_SN,
- TILE_OPC_SADAH_U,
- TILE_OPC_SADAH_U_SN,
- TILE_OPC_SADB_U,
- TILE_OPC_SADB_U_SN,
- TILE_OPC_SADH,
- TILE_OPC_SADH_SN,
- TILE_OPC_SADH_U,
- TILE_OPC_SADH_U_SN,
- TILE_OPC_SB,
- TILE_OPC_SBADD,
- TILE_OPC_SEQ,
- TILE_OPC_SEQ_SN,
- TILE_OPC_SEQB,
- TILE_OPC_SEQB_SN,
- TILE_OPC_SEQH,
- TILE_OPC_SEQH_SN,
- TILE_OPC_SEQI,
- TILE_OPC_SEQI_SN,
- TILE_OPC_SEQIB,
- TILE_OPC_SEQIB_SN,
- TILE_OPC_SEQIH,
- TILE_OPC_SEQIH_SN,
- TILE_OPC_SH,
- TILE_OPC_SHADD,
- TILE_OPC_SHL,
- TILE_OPC_SHL_SN,
- TILE_OPC_SHLB,
- TILE_OPC_SHLB_SN,
- TILE_OPC_SHLH,
- TILE_OPC_SHLH_SN,
- TILE_OPC_SHLI,
- TILE_OPC_SHLI_SN,
- TILE_OPC_SHLIB,
- TILE_OPC_SHLIB_SN,
- TILE_OPC_SHLIH,
- TILE_OPC_SHLIH_SN,
- TILE_OPC_SHR,
- TILE_OPC_SHR_SN,
- TILE_OPC_SHRB,
- TILE_OPC_SHRB_SN,
- TILE_OPC_SHRH,
- TILE_OPC_SHRH_SN,
- TILE_OPC_SHRI,
- TILE_OPC_SHRI_SN,
- TILE_OPC_SHRIB,
- TILE_OPC_SHRIB_SN,
- TILE_OPC_SHRIH,
- TILE_OPC_SHRIH_SN,
- TILE_OPC_SLT,
- TILE_OPC_SLT_SN,
- TILE_OPC_SLT_U,
- TILE_OPC_SLT_U_SN,
- TILE_OPC_SLTB,
- TILE_OPC_SLTB_SN,
- TILE_OPC_SLTB_U,
- TILE_OPC_SLTB_U_SN,
- TILE_OPC_SLTE,
- TILE_OPC_SLTE_SN,
- TILE_OPC_SLTE_U,
- TILE_OPC_SLTE_U_SN,
- TILE_OPC_SLTEB,
- TILE_OPC_SLTEB_SN,
- TILE_OPC_SLTEB_U,
- TILE_OPC_SLTEB_U_SN,
- TILE_OPC_SLTEH,
- TILE_OPC_SLTEH_SN,
- TILE_OPC_SLTEH_U,
- TILE_OPC_SLTEH_U_SN,
- TILE_OPC_SLTH,
- TILE_OPC_SLTH_SN,
- TILE_OPC_SLTH_U,
- TILE_OPC_SLTH_U_SN,
- TILE_OPC_SLTI,
- TILE_OPC_SLTI_SN,
- TILE_OPC_SLTI_U,
- TILE_OPC_SLTI_U_SN,
- TILE_OPC_SLTIB,
- TILE_OPC_SLTIB_SN,
- TILE_OPC_SLTIB_U,
- TILE_OPC_SLTIB_U_SN,
- TILE_OPC_SLTIH,
- TILE_OPC_SLTIH_SN,
- TILE_OPC_SLTIH_U,
- TILE_OPC_SLTIH_U_SN,
- TILE_OPC_SNE,
- TILE_OPC_SNE_SN,
- TILE_OPC_SNEB,
- TILE_OPC_SNEB_SN,
- TILE_OPC_SNEH,
- TILE_OPC_SNEH_SN,
- TILE_OPC_SRA,
- TILE_OPC_SRA_SN,
- TILE_OPC_SRAB,
- TILE_OPC_SRAB_SN,
- TILE_OPC_SRAH,
- TILE_OPC_SRAH_SN,
- TILE_OPC_SRAI,
- TILE_OPC_SRAI_SN,
- TILE_OPC_SRAIB,
- TILE_OPC_SRAIB_SN,
- TILE_OPC_SRAIH,
- TILE_OPC_SRAIH_SN,
- TILE_OPC_SUB,
- TILE_OPC_SUB_SN,
- TILE_OPC_SUBB,
- TILE_OPC_SUBB_SN,
- TILE_OPC_SUBBS_U,
- TILE_OPC_SUBBS_U_SN,
- TILE_OPC_SUBH,
- TILE_OPC_SUBH_SN,
- TILE_OPC_SUBHS,
- TILE_OPC_SUBHS_SN,
- TILE_OPC_SUBS,
- TILE_OPC_SUBS_SN,
- TILE_OPC_SW,
- TILE_OPC_SWADD,
- TILE_OPC_SWINT0,
- TILE_OPC_SWINT1,
- TILE_OPC_SWINT2,
- TILE_OPC_SWINT3,
- TILE_OPC_TBLIDXB0,
- TILE_OPC_TBLIDXB0_SN,
- TILE_OPC_TBLIDXB1,
- TILE_OPC_TBLIDXB1_SN,
- TILE_OPC_TBLIDXB2,
- TILE_OPC_TBLIDXB2_SN,
- TILE_OPC_TBLIDXB3,
- TILE_OPC_TBLIDXB3_SN,
- TILE_OPC_TNS,
- TILE_OPC_TNS_SN,
- TILE_OPC_WH64,
- TILE_OPC_XOR,
- TILE_OPC_XOR_SN,
- TILE_OPC_XORI,
- TILE_OPC_XORI_SN,
- TILE_OPC_NONE
-} tile_mnemonic;
+ TILEGX_OPC_BPT,
+ TILEGX_OPC_INFO,
+ TILEGX_OPC_INFOL,
+ TILEGX_OPC_MOVE,
+ TILEGX_OPC_MOVEI,
+ TILEGX_OPC_MOVELI,
+ TILEGX_OPC_PREFETCH,
+ TILEGX_OPC_PREFETCH_ADD_L1,
+ TILEGX_OPC_PREFETCH_ADD_L1_FAULT,
+ TILEGX_OPC_PREFETCH_ADD_L2,
+ TILEGX_OPC_PREFETCH_ADD_L2_FAULT,
+ TILEGX_OPC_PREFETCH_ADD_L3,
+ TILEGX_OPC_PREFETCH_ADD_L3_FAULT,
+ TILEGX_OPC_PREFETCH_L1,
+ TILEGX_OPC_PREFETCH_L1_FAULT,
+ TILEGX_OPC_PREFETCH_L2,
+ TILEGX_OPC_PREFETCH_L2_FAULT,
+ TILEGX_OPC_PREFETCH_L3,
+ TILEGX_OPC_PREFETCH_L3_FAULT,
+ TILEGX_OPC_RAISE,
+ TILEGX_OPC_ADD,
+ TILEGX_OPC_ADDI,
+ TILEGX_OPC_ADDLI,
+ TILEGX_OPC_ADDX,
+ TILEGX_OPC_ADDXI,
+ TILEGX_OPC_ADDXLI,
+ TILEGX_OPC_ADDXSC,
+ TILEGX_OPC_AND,
+ TILEGX_OPC_ANDI,
+ TILEGX_OPC_BEQZ,
+ TILEGX_OPC_BEQZT,
+ TILEGX_OPC_BFEXTS,
+ TILEGX_OPC_BFEXTU,
+ TILEGX_OPC_BFINS,
+ TILEGX_OPC_BGEZ,
+ TILEGX_OPC_BGEZT,
+ TILEGX_OPC_BGTZ,
+ TILEGX_OPC_BGTZT,
+ TILEGX_OPC_BLBC,
+ TILEGX_OPC_BLBCT,
+ TILEGX_OPC_BLBS,
+ TILEGX_OPC_BLBST,
+ TILEGX_OPC_BLEZ,
+ TILEGX_OPC_BLEZT,
+ TILEGX_OPC_BLTZ,
+ TILEGX_OPC_BLTZT,
+ TILEGX_OPC_BNEZ,
+ TILEGX_OPC_BNEZT,
+ TILEGX_OPC_CLZ,
+ TILEGX_OPC_CMOVEQZ,
+ TILEGX_OPC_CMOVNEZ,
+ TILEGX_OPC_CMPEQ,
+ TILEGX_OPC_CMPEQI,
+ TILEGX_OPC_CMPEXCH,
+ TILEGX_OPC_CMPEXCH4,
+ TILEGX_OPC_CMPLES,
+ TILEGX_OPC_CMPLEU,
+ TILEGX_OPC_CMPLTS,
+ TILEGX_OPC_CMPLTSI,
+ TILEGX_OPC_CMPLTU,
+ TILEGX_OPC_CMPLTUI,
+ TILEGX_OPC_CMPNE,
+ TILEGX_OPC_CMUL,
+ TILEGX_OPC_CMULA,
+ TILEGX_OPC_CMULAF,
+ TILEGX_OPC_CMULF,
+ TILEGX_OPC_CMULFR,
+ TILEGX_OPC_CMULH,
+ TILEGX_OPC_CMULHR,
+ TILEGX_OPC_CRC32_32,
+ TILEGX_OPC_CRC32_8,
+ TILEGX_OPC_CTZ,
+ TILEGX_OPC_DBLALIGN,
+ TILEGX_OPC_DBLALIGN2,
+ TILEGX_OPC_DBLALIGN4,
+ TILEGX_OPC_DBLALIGN6,
+ TILEGX_OPC_DRAIN,
+ TILEGX_OPC_DTLBPR,
+ TILEGX_OPC_EXCH,
+ TILEGX_OPC_EXCH4,
+ TILEGX_OPC_FDOUBLE_ADD_FLAGS,
+ TILEGX_OPC_FDOUBLE_ADDSUB,
+ TILEGX_OPC_FDOUBLE_MUL_FLAGS,
+ TILEGX_OPC_FDOUBLE_PACK1,
+ TILEGX_OPC_FDOUBLE_PACK2,
+ TILEGX_OPC_FDOUBLE_SUB_FLAGS,
+ TILEGX_OPC_FDOUBLE_UNPACK_MAX,
+ TILEGX_OPC_FDOUBLE_UNPACK_MIN,
+ TILEGX_OPC_FETCHADD,
+ TILEGX_OPC_FETCHADD4,
+ TILEGX_OPC_FETCHADDGEZ,
+ TILEGX_OPC_FETCHADDGEZ4,
+ TILEGX_OPC_FETCHAND,
+ TILEGX_OPC_FETCHAND4,
+ TILEGX_OPC_FETCHOR,
+ TILEGX_OPC_FETCHOR4,
+ TILEGX_OPC_FINV,
+ TILEGX_OPC_FLUSH,
+ TILEGX_OPC_FLUSHWB,
+ TILEGX_OPC_FNOP,
+ TILEGX_OPC_FSINGLE_ADD1,
+ TILEGX_OPC_FSINGLE_ADDSUB2,
+ TILEGX_OPC_FSINGLE_MUL1,
+ TILEGX_OPC_FSINGLE_MUL2,
+ TILEGX_OPC_FSINGLE_PACK1,
+ TILEGX_OPC_FSINGLE_PACK2,
+ TILEGX_OPC_FSINGLE_SUB1,
+ TILEGX_OPC_ICOH,
+ TILEGX_OPC_ILL,
+ TILEGX_OPC_INV,
+ TILEGX_OPC_IRET,
+ TILEGX_OPC_J,
+ TILEGX_OPC_JAL,
+ TILEGX_OPC_JALR,
+ TILEGX_OPC_JALRP,
+ TILEGX_OPC_JR,
+ TILEGX_OPC_JRP,
+ TILEGX_OPC_LD,
+ TILEGX_OPC_LD1S,
+ TILEGX_OPC_LD1S_ADD,
+ TILEGX_OPC_LD1U,
+ TILEGX_OPC_LD1U_ADD,
+ TILEGX_OPC_LD2S,
+ TILEGX_OPC_LD2S_ADD,
+ TILEGX_OPC_LD2U,
+ TILEGX_OPC_LD2U_ADD,
+ TILEGX_OPC_LD4S,
+ TILEGX_OPC_LD4S_ADD,
+ TILEGX_OPC_LD4U,
+ TILEGX_OPC_LD4U_ADD,
+ TILEGX_OPC_LD_ADD,
+ TILEGX_OPC_LDNA,
+ TILEGX_OPC_LDNA_ADD,
+ TILEGX_OPC_LDNT,
+ TILEGX_OPC_LDNT1S,
+ TILEGX_OPC_LDNT1S_ADD,
+ TILEGX_OPC_LDNT1U,
+ TILEGX_OPC_LDNT1U_ADD,
+ TILEGX_OPC_LDNT2S,
+ TILEGX_OPC_LDNT2S_ADD,
+ TILEGX_OPC_LDNT2U,
+ TILEGX_OPC_LDNT2U_ADD,
+ TILEGX_OPC_LDNT4S,
+ TILEGX_OPC_LDNT4S_ADD,
+ TILEGX_OPC_LDNT4U,
+ TILEGX_OPC_LDNT4U_ADD,
+ TILEGX_OPC_LDNT_ADD,
+ TILEGX_OPC_LNK,
+ TILEGX_OPC_MF,
+ TILEGX_OPC_MFSPR,
+ TILEGX_OPC_MM,
+ TILEGX_OPC_MNZ,
+ TILEGX_OPC_MTSPR,
+ TILEGX_OPC_MUL_HS_HS,
+ TILEGX_OPC_MUL_HS_HU,
+ TILEGX_OPC_MUL_HS_LS,
+ TILEGX_OPC_MUL_HS_LU,
+ TILEGX_OPC_MUL_HU_HU,
+ TILEGX_OPC_MUL_HU_LS,
+ TILEGX_OPC_MUL_HU_LU,
+ TILEGX_OPC_MUL_LS_LS,
+ TILEGX_OPC_MUL_LS_LU,
+ TILEGX_OPC_MUL_LU_LU,
+ TILEGX_OPC_MULA_HS_HS,
+ TILEGX_OPC_MULA_HS_HU,
+ TILEGX_OPC_MULA_HS_LS,
+ TILEGX_OPC_MULA_HS_LU,
+ TILEGX_OPC_MULA_HU_HU,
+ TILEGX_OPC_MULA_HU_LS,
+ TILEGX_OPC_MULA_HU_LU,
+ TILEGX_OPC_MULA_LS_LS,
+ TILEGX_OPC_MULA_LS_LU,
+ TILEGX_OPC_MULA_LU_LU,
+ TILEGX_OPC_MULAX,
+ TILEGX_OPC_MULX,
+ TILEGX_OPC_MZ,
+ TILEGX_OPC_NAP,
+ TILEGX_OPC_NOP,
+ TILEGX_OPC_NOR,
+ TILEGX_OPC_OR,
+ TILEGX_OPC_ORI,
+ TILEGX_OPC_PCNT,
+ TILEGX_OPC_REVBITS,
+ TILEGX_OPC_REVBYTES,
+ TILEGX_OPC_ROTL,
+ TILEGX_OPC_ROTLI,
+ TILEGX_OPC_SHL,
+ TILEGX_OPC_SHL16INSLI,
+ TILEGX_OPC_SHL1ADD,
+ TILEGX_OPC_SHL1ADDX,
+ TILEGX_OPC_SHL2ADD,
+ TILEGX_OPC_SHL2ADDX,
+ TILEGX_OPC_SHL3ADD,
+ TILEGX_OPC_SHL3ADDX,
+ TILEGX_OPC_SHLI,
+ TILEGX_OPC_SHLX,
+ TILEGX_OPC_SHLXI,
+ TILEGX_OPC_SHRS,
+ TILEGX_OPC_SHRSI,
+ TILEGX_OPC_SHRU,
+ TILEGX_OPC_SHRUI,
+ TILEGX_OPC_SHRUX,
+ TILEGX_OPC_SHRUXI,
+ TILEGX_OPC_SHUFFLEBYTES,
+ TILEGX_OPC_ST,
+ TILEGX_OPC_ST1,
+ TILEGX_OPC_ST1_ADD,
+ TILEGX_OPC_ST2,
+ TILEGX_OPC_ST2_ADD,
+ TILEGX_OPC_ST4,
+ TILEGX_OPC_ST4_ADD,
+ TILEGX_OPC_ST_ADD,
+ TILEGX_OPC_STNT,
+ TILEGX_OPC_STNT1,
+ TILEGX_OPC_STNT1_ADD,
+ TILEGX_OPC_STNT2,
+ TILEGX_OPC_STNT2_ADD,
+ TILEGX_OPC_STNT4,
+ TILEGX_OPC_STNT4_ADD,
+ TILEGX_OPC_STNT_ADD,
+ TILEGX_OPC_SUB,
+ TILEGX_OPC_SUBX,
+ TILEGX_OPC_SUBXSC,
+ TILEGX_OPC_SWINT0,
+ TILEGX_OPC_SWINT1,
+ TILEGX_OPC_SWINT2,
+ TILEGX_OPC_SWINT3,
+ TILEGX_OPC_TBLIDXB0,
+ TILEGX_OPC_TBLIDXB1,
+ TILEGX_OPC_TBLIDXB2,
+ TILEGX_OPC_TBLIDXB3,
+ TILEGX_OPC_V1ADD,
+ TILEGX_OPC_V1ADDI,
+ TILEGX_OPC_V1ADDUC,
+ TILEGX_OPC_V1ADIFFU,
+ TILEGX_OPC_V1AVGU,
+ TILEGX_OPC_V1CMPEQ,
+ TILEGX_OPC_V1CMPEQI,
+ TILEGX_OPC_V1CMPLES,
+ TILEGX_OPC_V1CMPLEU,
+ TILEGX_OPC_V1CMPLTS,
+ TILEGX_OPC_V1CMPLTSI,
+ TILEGX_OPC_V1CMPLTU,
+ TILEGX_OPC_V1CMPLTUI,
+ TILEGX_OPC_V1CMPNE,
+ TILEGX_OPC_V1DDOTPU,
+ TILEGX_OPC_V1DDOTPUA,
+ TILEGX_OPC_V1DDOTPUS,
+ TILEGX_OPC_V1DDOTPUSA,
+ TILEGX_OPC_V1DOTP,
+ TILEGX_OPC_V1DOTPA,
+ TILEGX_OPC_V1DOTPU,
+ TILEGX_OPC_V1DOTPUA,
+ TILEGX_OPC_V1DOTPUS,
+ TILEGX_OPC_V1DOTPUSA,
+ TILEGX_OPC_V1INT_H,
+ TILEGX_OPC_V1INT_L,
+ TILEGX_OPC_V1MAXU,
+ TILEGX_OPC_V1MAXUI,
+ TILEGX_OPC_V1MINU,
+ TILEGX_OPC_V1MINUI,
+ TILEGX_OPC_V1MNZ,
+ TILEGX_OPC_V1MULTU,
+ TILEGX_OPC_V1MULU,
+ TILEGX_OPC_V1MULUS,
+ TILEGX_OPC_V1MZ,
+ TILEGX_OPC_V1SADAU,
+ TILEGX_OPC_V1SADU,
+ TILEGX_OPC_V1SHL,
+ TILEGX_OPC_V1SHLI,
+ TILEGX_OPC_V1SHRS,
+ TILEGX_OPC_V1SHRSI,
+ TILEGX_OPC_V1SHRU,
+ TILEGX_OPC_V1SHRUI,
+ TILEGX_OPC_V1SUB,
+ TILEGX_OPC_V1SUBUC,
+ TILEGX_OPC_V2ADD,
+ TILEGX_OPC_V2ADDI,
+ TILEGX_OPC_V2ADDSC,
+ TILEGX_OPC_V2ADIFFS,
+ TILEGX_OPC_V2AVGS,
+ TILEGX_OPC_V2CMPEQ,
+ TILEGX_OPC_V2CMPEQI,
+ TILEGX_OPC_V2CMPLES,
+ TILEGX_OPC_V2CMPLEU,
+ TILEGX_OPC_V2CMPLTS,
+ TILEGX_OPC_V2CMPLTSI,
+ TILEGX_OPC_V2CMPLTU,
+ TILEGX_OPC_V2CMPLTUI,
+ TILEGX_OPC_V2CMPNE,
+ TILEGX_OPC_V2DOTP,
+ TILEGX_OPC_V2DOTPA,
+ TILEGX_OPC_V2INT_H,
+ TILEGX_OPC_V2INT_L,
+ TILEGX_OPC_V2MAXS,
+ TILEGX_OPC_V2MAXSI,
+ TILEGX_OPC_V2MINS,
+ TILEGX_OPC_V2MINSI,
+ TILEGX_OPC_V2MNZ,
+ TILEGX_OPC_V2MULFSC,
+ TILEGX_OPC_V2MULS,
+ TILEGX_OPC_V2MULTS,
+ TILEGX_OPC_V2MZ,
+ TILEGX_OPC_V2PACKH,
+ TILEGX_OPC_V2PACKL,
+ TILEGX_OPC_V2PACKUC,
+ TILEGX_OPC_V2SADAS,
+ TILEGX_OPC_V2SADAU,
+ TILEGX_OPC_V2SADS,
+ TILEGX_OPC_V2SADU,
+ TILEGX_OPC_V2SHL,
+ TILEGX_OPC_V2SHLI,
+ TILEGX_OPC_V2SHLSC,
+ TILEGX_OPC_V2SHRS,
+ TILEGX_OPC_V2SHRSI,
+ TILEGX_OPC_V2SHRU,
+ TILEGX_OPC_V2SHRUI,
+ TILEGX_OPC_V2SUB,
+ TILEGX_OPC_V2SUBSC,
+ TILEGX_OPC_V4ADD,
+ TILEGX_OPC_V4ADDSC,
+ TILEGX_OPC_V4INT_H,
+ TILEGX_OPC_V4INT_L,
+ TILEGX_OPC_V4PACKSC,
+ TILEGX_OPC_V4SHL,
+ TILEGX_OPC_V4SHLSC,
+ TILEGX_OPC_V4SHRS,
+ TILEGX_OPC_V4SHRU,
+ TILEGX_OPC_V4SUB,
+ TILEGX_OPC_V4SUBSC,
+ TILEGX_OPC_WH64,
+ TILEGX_OPC_XOR,
+ TILEGX_OPC_XORI,
+ TILEGX_OPC_NONE
+} tilegx_mnemonic;
/* 64-bit pattern for a { bpt ; nop } bundle. */
-#define TILE_BPT_BUNDLE 0x400b3cae70166000ULL
+#define TILEGX_BPT_BUNDLE 0x286a44ae51485000ULL
-#define TILE_ELF_MACHINE_CODE EM_TILEPRO
+#define TILE_ELF_MACHINE_CODE EM_TILE64
-#define TILE_ELF_NAME "elf32-tilepro"
+#define TILE_ELF_NAME "elf32-tile64"
static __inline unsigned int
-get_BrOff_SN(tile_bundle_bits num)
+get_BFEnd_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
- return (((n >> 0)) & 0x3ff);
+ return (((n >> 12)) & 0x3f);
}
static __inline unsigned int
-get_BrOff_X1(tile_bundle_bits n)
+get_BFOpcodeExtension_X0(tilegx_bundle_bits num)
{
- return (((unsigned int)(n >> 43)) & 0x00007fff) |
- (((unsigned int)(n >> 20)) & 0x00018000);
+ const unsigned int n = (unsigned int)num;
+ return (((n >> 24)) & 0xf);
}
static __inline unsigned int
-get_BrType_X1(tile_bundle_bits n)
+get_BFStart_X0(tilegx_bundle_bits num)
{
- return (((unsigned int)(n >> 31)) & 0xf);
+ const unsigned int n = (unsigned int)num;
+ return (((n >> 18)) & 0x3f);
}
static __inline unsigned int
-get_Dest_Imm8_X1(tile_bundle_bits n)
+get_BrOff_X1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n >> 31)) & 0x0000003f) |
+ (((unsigned int)(n >> 37)) & 0x0001ffc0);
+}
+
+static __inline unsigned int
+get_BrType_X1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n >> 54)) & 0x1f);
+}
+
+static __inline unsigned int
+get_Dest_Imm8_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 31)) & 0x0000003f) |
(((unsigned int)(n >> 43)) & 0x000000c0);
}
static __inline unsigned int
-get_Dest_SN(tile_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 2)) & 0x3);
-}
-
-static __inline unsigned int
-get_Dest_X0(tile_bundle_bits num)
+get_Dest_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n >> 0)) & 0x3f);
}
static __inline unsigned int
-get_Dest_X1(tile_bundle_bits n)
+get_Dest_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 31)) & 0x3f);
}
static __inline unsigned int
-get_Dest_Y0(tile_bundle_bits num)
+get_Dest_Y0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n >> 0)) & 0x3f);
}
static __inline unsigned int
-get_Dest_Y1(tile_bundle_bits n)
+get_Dest_Y1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 31)) & 0x3f);
}
static __inline unsigned int
-get_Imm16_X0(tile_bundle_bits num)
+get_Imm16_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n >> 12)) & 0xffff);
}
static __inline unsigned int
-get_Imm16_X1(tile_bundle_bits n)
+get_Imm16_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 43)) & 0xffff);
}
static __inline unsigned int
-get_Imm8_SN(tile_bundle_bits num)
+get_Imm8OpcodeExtension_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
- return (((n >> 0)) & 0xff);
+ return (((n >> 20)) & 0xff);
}
static __inline unsigned int
-get_Imm8_X0(tile_bundle_bits num)
+get_Imm8OpcodeExtension_X1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n >> 51)) & 0xff);
+}
+
+static __inline unsigned int
+get_Imm8_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n >> 12)) & 0xff);
}
static __inline unsigned int
-get_Imm8_X1(tile_bundle_bits n)
+get_Imm8_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 43)) & 0xff);
}
static __inline unsigned int
-get_Imm8_Y0(tile_bundle_bits num)
+get_Imm8_Y0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n >> 12)) & 0xff);
}
static __inline unsigned int
-get_Imm8_Y1(tile_bundle_bits n)
+get_Imm8_Y1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 43)) & 0xff);
}
static __inline unsigned int
-get_ImmOpcodeExtension_X0(tile_bundle_bits num)
+get_JumpOff_X1(tilegx_bundle_bits n)
{
- const unsigned int n = (unsigned int)num;
- return (((n >> 20)) & 0x7f);
+ return (((unsigned int)(n >> 31)) & 0x7ffffff);
}
static __inline unsigned int
-get_ImmOpcodeExtension_X1(tile_bundle_bits n)
+get_JumpOpcodeExtension_X1(tilegx_bundle_bits n)
{
- return (((unsigned int)(n >> 51)) & 0x7f);
+ return (((unsigned int)(n >> 58)) & 0x1);
}
static __inline unsigned int
-get_ImmRROpcodeExtension_SN(tile_bundle_bits num)
+get_MF_Imm14_X1(tilegx_bundle_bits n)
{
- const unsigned int n = (unsigned int)num;
- return (((n >> 8)) & 0x3);
+ return (((unsigned int)(n >> 37)) & 0x3fff);
}
static __inline unsigned int
-get_JOffLong_X1(tile_bundle_bits n)
-{
- return (((unsigned int)(n >> 43)) & 0x00007fff) |
- (((unsigned int)(n >> 20)) & 0x00018000) |
- (((unsigned int)(n >> 14)) & 0x001e0000) |
- (((unsigned int)(n >> 16)) & 0x07e00000) |
- (((unsigned int)(n >> 31)) & 0x18000000);
-}
-
-static __inline unsigned int
-get_JOff_X1(tile_bundle_bits n)
-{
- return (((unsigned int)(n >> 43)) & 0x00007fff) |
- (((unsigned int)(n >> 20)) & 0x00018000) |
- (((unsigned int)(n >> 14)) & 0x001e0000) |
- (((unsigned int)(n >> 16)) & 0x07e00000) |
- (((unsigned int)(n >> 31)) & 0x08000000);
-}
-
-static __inline unsigned int
-get_MF_Imm15_X1(tile_bundle_bits n)
-{
- return (((unsigned int)(n >> 37)) & 0x00003fff) |
- (((unsigned int)(n >> 44)) & 0x00004000);
-}
-
-static __inline unsigned int
-get_MMEnd_X0(tile_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 18)) & 0x1f);
-}
-
-static __inline unsigned int
-get_MMEnd_X1(tile_bundle_bits n)
-{
- return (((unsigned int)(n >> 49)) & 0x1f);
-}
-
-static __inline unsigned int
-get_MMStart_X0(tile_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 23)) & 0x1f);
-}
-
-static __inline unsigned int
-get_MMStart_X1(tile_bundle_bits n)
-{
- return (((unsigned int)(n >> 54)) & 0x1f);
-}
-
-static __inline unsigned int
-get_MT_Imm15_X1(tile_bundle_bits n)
+get_MT_Imm14_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 31)) & 0x0000003f) |
- (((unsigned int)(n >> 37)) & 0x00003fc0) |
- (((unsigned int)(n >> 44)) & 0x00004000);
+ (((unsigned int)(n >> 37)) & 0x00003fc0);
}
static __inline unsigned int
-get_Mode(tile_bundle_bits n)
+get_Mode(tilegx_bundle_bits n)
{
- return (((unsigned int)(n >> 63)) & 0x1);
+ return (((unsigned int)(n >> 62)) & 0x3);
}
static __inline unsigned int
-get_NoRegOpcodeExtension_SN(tile_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 0)) & 0xf);
-}
-
-static __inline unsigned int
-get_Opcode_SN(tile_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 10)) & 0x3f);
-}
-
-static __inline unsigned int
-get_Opcode_X0(tile_bundle_bits num)
+get_Opcode_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n >> 28)) & 0x7);
}
static __inline unsigned int
-get_Opcode_X1(tile_bundle_bits n)
+get_Opcode_X1(tilegx_bundle_bits n)
{
- return (((unsigned int)(n >> 59)) & 0xf);
+ return (((unsigned int)(n >> 59)) & 0x7);
}
static __inline unsigned int
-get_Opcode_Y0(tile_bundle_bits num)
+get_Opcode_Y0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n >> 27)) & 0xf);
}
static __inline unsigned int
-get_Opcode_Y1(tile_bundle_bits n)
+get_Opcode_Y1(tilegx_bundle_bits n)
{
- return (((unsigned int)(n >> 59)) & 0xf);
+ return (((unsigned int)(n >> 58)) & 0xf);
}
static __inline unsigned int
-get_Opcode_Y2(tile_bundle_bits n)
+get_Opcode_Y2(tilegx_bundle_bits n)
{
- return (((unsigned int)(n >> 56)) & 0x7);
+ return (((n >> 26)) & 0x00000001) |
+ (((unsigned int)(n >> 56)) & 0x00000002);
}
static __inline unsigned int
-get_RROpcodeExtension_SN(tile_bundle_bits num)
+get_RRROpcodeExtension_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
- return (((n >> 4)) & 0xf);
+ return (((n >> 18)) & 0x3ff);
}
static __inline unsigned int
-get_RRROpcodeExtension_X0(tile_bundle_bits num)
+get_RRROpcodeExtension_X1(tilegx_bundle_bits n)
{
- const unsigned int n = (unsigned int)num;
- return (((n >> 18)) & 0x1ff);
+ return (((unsigned int)(n >> 49)) & 0x3ff);
}
static __inline unsigned int
-get_RRROpcodeExtension_X1(tile_bundle_bits n)
-{
- return (((unsigned int)(n >> 49)) & 0x1ff);
-}
-
-static __inline unsigned int
-get_RRROpcodeExtension_Y0(tile_bundle_bits num)
+get_RRROpcodeExtension_Y0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n >> 18)) & 0x3);
}
static __inline unsigned int
-get_RRROpcodeExtension_Y1(tile_bundle_bits n)
+get_RRROpcodeExtension_Y1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 49)) & 0x3);
}
static __inline unsigned int
-get_RouteOpcodeExtension_SN(tile_bundle_bits num)
+get_ShAmt_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
- return (((n >> 0)) & 0x3ff);
+ return (((n >> 12)) & 0x3f);
}
static __inline unsigned int
-get_S_X0(tile_bundle_bits num)
+get_ShAmt_X1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n >> 43)) & 0x3f);
+}
+
+static __inline unsigned int
+get_ShAmt_Y0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
- return (((n >> 27)) & 0x1);
+ return (((n >> 12)) & 0x3f);
}
static __inline unsigned int
-get_S_X1(tile_bundle_bits n)
+get_ShAmt_Y1(tilegx_bundle_bits n)
{
- return (((unsigned int)(n >> 58)) & 0x1);
+ return (((unsigned int)(n >> 43)) & 0x3f);
}
static __inline unsigned int
-get_ShAmt_X0(tile_bundle_bits num)
+get_ShiftOpcodeExtension_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
- return (((n >> 12)) & 0x1f);
+ return (((n >> 18)) & 0x3ff);
}
static __inline unsigned int
-get_ShAmt_X1(tile_bundle_bits n)
+get_ShiftOpcodeExtension_X1(tilegx_bundle_bits n)
{
- return (((unsigned int)(n >> 43)) & 0x1f);
+ return (((unsigned int)(n >> 49)) & 0x3ff);
}
static __inline unsigned int
-get_ShAmt_Y0(tile_bundle_bits num)
+get_ShiftOpcodeExtension_Y0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
- return (((n >> 12)) & 0x1f);
+ return (((n >> 18)) & 0x3);
}
static __inline unsigned int
-get_ShAmt_Y1(tile_bundle_bits n)
+get_ShiftOpcodeExtension_Y1(tilegx_bundle_bits n)
{
- return (((unsigned int)(n >> 43)) & 0x1f);
+ return (((unsigned int)(n >> 49)) & 0x3);
}
static __inline unsigned int
-get_SrcA_X0(tile_bundle_bits num)
+get_SrcA_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n >> 6)) & 0x3f);
}
static __inline unsigned int
-get_SrcA_X1(tile_bundle_bits n)
+get_SrcA_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 37)) & 0x3f);
}
static __inline unsigned int
-get_SrcA_Y0(tile_bundle_bits num)
+get_SrcA_Y0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n >> 6)) & 0x3f);
}
static __inline unsigned int
-get_SrcA_Y1(tile_bundle_bits n)
+get_SrcA_Y1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 37)) & 0x3f);
}
static __inline unsigned int
-get_SrcA_Y2(tile_bundle_bits n)
-{
- return (((n >> 26)) & 0x00000001) |
- (((unsigned int)(n >> 50)) & 0x0000003e);
-}
-
-static __inline unsigned int
-get_SrcBDest_Y2(tile_bundle_bits num)
+get_SrcA_Y2(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n >> 20)) & 0x3f);
}
static __inline unsigned int
-get_SrcB_X0(tile_bundle_bits num)
+get_SrcBDest_Y2(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n >> 51)) & 0x3f);
+}
+
+static __inline unsigned int
+get_SrcB_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n >> 12)) & 0x3f);
}
static __inline unsigned int
-get_SrcB_X1(tile_bundle_bits n)
+get_SrcB_X1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 43)) & 0x3f);
}
static __inline unsigned int
-get_SrcB_Y0(tile_bundle_bits num)
+get_SrcB_Y0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
return (((n >> 12)) & 0x3f);
}
static __inline unsigned int
-get_SrcB_Y1(tile_bundle_bits n)
+get_SrcB_Y1(tilegx_bundle_bits n)
{
return (((unsigned int)(n >> 43)) & 0x3f);
}
static __inline unsigned int
-get_Src_SN(tile_bundle_bits num)
+get_UnaryOpcodeExtension_X0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
- return (((n >> 0)) & 0x3);
+ return (((n >> 12)) & 0x3f);
}
static __inline unsigned int
-get_UnOpcodeExtension_X0(tile_bundle_bits num)
+get_UnaryOpcodeExtension_X1(tilegx_bundle_bits n)
+{
+ return (((unsigned int)(n >> 43)) & 0x3f);
+}
+
+static __inline unsigned int
+get_UnaryOpcodeExtension_Y0(tilegx_bundle_bits num)
{
const unsigned int n = (unsigned int)num;
- return (((n >> 12)) & 0x1f);
+ return (((n >> 12)) & 0x3f);
}
static __inline unsigned int
-get_UnOpcodeExtension_X1(tile_bundle_bits n)
+get_UnaryOpcodeExtension_Y1(tilegx_bundle_bits n)
{
- return (((unsigned int)(n >> 43)) & 0x1f);
-}
-
-static __inline unsigned int
-get_UnOpcodeExtension_Y0(tile_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 12)) & 0x1f);
-}
-
-static __inline unsigned int
-get_UnOpcodeExtension_Y1(tile_bundle_bits n)
-{
- return (((unsigned int)(n >> 43)) & 0x1f);
-}
-
-static __inline unsigned int
-get_UnShOpcodeExtension_X0(tile_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 17)) & 0x3ff);
-}
-
-static __inline unsigned int
-get_UnShOpcodeExtension_X1(tile_bundle_bits n)
-{
- return (((unsigned int)(n >> 48)) & 0x3ff);
-}
-
-static __inline unsigned int
-get_UnShOpcodeExtension_Y0(tile_bundle_bits num)
-{
- const unsigned int n = (unsigned int)num;
- return (((n >> 17)) & 0x7);
-}
-
-static __inline unsigned int
-get_UnShOpcodeExtension_Y1(tile_bundle_bits n)
-{
- return (((unsigned int)(n >> 48)) & 0x7);
+ return (((unsigned int)(n >> 43)) & 0x3f);
}
@@ -874,546 +722,441 @@
-static __inline tile_bundle_bits
-create_BrOff_SN(int num)
+static __inline tilegx_bundle_bits
+create_BFEnd_X0(int num)
{
const unsigned int n = (unsigned int)num;
- return ((n & 0x3ff) << 0);
+ return ((n & 0x3f) << 12);
}
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
+create_BFOpcodeExtension_X0(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return ((n & 0xf) << 24);
+}
+
+static __inline tilegx_bundle_bits
+create_BFStart_X0(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return ((n & 0x3f) << 18);
+}
+
+static __inline tilegx_bundle_bits
create_BrOff_X1(int num)
{
const unsigned int n = (unsigned int)num;
- return (((tile_bundle_bits)(n & 0x00007fff)) << 43) |
- (((tile_bundle_bits)(n & 0x00018000)) << 20);
+ return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) |
+ (((tilegx_bundle_bits)(n & 0x0001ffc0)) << 37);
}
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
create_BrType_X1(int num)
{
const unsigned int n = (unsigned int)num;
- return (((tile_bundle_bits)(n & 0xf)) << 31);
+ return (((tilegx_bundle_bits)(n & 0x1f)) << 54);
}
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
create_Dest_Imm8_X1(int num)
{
const unsigned int n = (unsigned int)num;
- return (((tile_bundle_bits)(n & 0x0000003f)) << 31) |
- (((tile_bundle_bits)(n & 0x000000c0)) << 43);
+ return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) |
+ (((tilegx_bundle_bits)(n & 0x000000c0)) << 43);
}
-static __inline tile_bundle_bits
-create_Dest_SN(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3) << 2);
-}
-
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
create_Dest_X0(int num)
{
const unsigned int n = (unsigned int)num;
return ((n & 0x3f) << 0);
}
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
create_Dest_X1(int num)
{
const unsigned int n = (unsigned int)num;
- return (((tile_bundle_bits)(n & 0x3f)) << 31);
+ return (((tilegx_bundle_bits)(n & 0x3f)) << 31);
}
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
create_Dest_Y0(int num)
{
const unsigned int n = (unsigned int)num;
return ((n & 0x3f) << 0);
}
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
create_Dest_Y1(int num)
{
const unsigned int n = (unsigned int)num;
- return (((tile_bundle_bits)(n & 0x3f)) << 31);
+ return (((tilegx_bundle_bits)(n & 0x3f)) << 31);
}
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
create_Imm16_X0(int num)
{
const unsigned int n = (unsigned int)num;
return ((n & 0xffff) << 12);
}
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
create_Imm16_X1(int num)
{
const unsigned int n = (unsigned int)num;
- return (((tile_bundle_bits)(n & 0xffff)) << 43);
+ return (((tilegx_bundle_bits)(n & 0xffff)) << 43);
}
-static __inline tile_bundle_bits
-create_Imm8_SN(int num)
+static __inline tilegx_bundle_bits
+create_Imm8OpcodeExtension_X0(int num)
{
const unsigned int n = (unsigned int)num;
- return ((n & 0xff) << 0);
+ return ((n & 0xff) << 20);
}
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
+create_Imm8OpcodeExtension_X1(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((tilegx_bundle_bits)(n & 0xff)) << 51);
+}
+
+static __inline tilegx_bundle_bits
create_Imm8_X0(int num)
{
const unsigned int n = (unsigned int)num;
return ((n & 0xff) << 12);
}
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
create_Imm8_X1(int num)
{
const unsigned int n = (unsigned int)num;
- return (((tile_bundle_bits)(n & 0xff)) << 43);
+ return (((tilegx_bundle_bits)(n & 0xff)) << 43);
}
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
create_Imm8_Y0(int num)
{
const unsigned int n = (unsigned int)num;
return ((n & 0xff) << 12);
}
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
create_Imm8_Y1(int num)
{
const unsigned int n = (unsigned int)num;
- return (((tile_bundle_bits)(n & 0xff)) << 43);
+ return (((tilegx_bundle_bits)(n & 0xff)) << 43);
}
-static __inline tile_bundle_bits
-create_ImmOpcodeExtension_X0(int num)
+static __inline tilegx_bundle_bits
+create_JumpOff_X1(int num)
{
const unsigned int n = (unsigned int)num;
- return ((n & 0x7f) << 20);
+ return (((tilegx_bundle_bits)(n & 0x7ffffff)) << 31);
}
-static __inline tile_bundle_bits
-create_ImmOpcodeExtension_X1(int num)
+static __inline tilegx_bundle_bits
+create_JumpOpcodeExtension_X1(int num)
{
const unsigned int n = (unsigned int)num;
- return (((tile_bundle_bits)(n & 0x7f)) << 51);
+ return (((tilegx_bundle_bits)(n & 0x1)) << 58);
}
-static __inline tile_bundle_bits
-create_ImmRROpcodeExtension_SN(int num)
+static __inline tilegx_bundle_bits
+create_MF_Imm14_X1(int num)
{
const unsigned int n = (unsigned int)num;
- return ((n & 0x3) << 8);
+ return (((tilegx_bundle_bits)(n & 0x3fff)) << 37);
}
-static __inline tile_bundle_bits
-create_JOffLong_X1(int num)
+static __inline tilegx_bundle_bits
+create_MT_Imm14_X1(int num)
{
const unsigned int n = (unsigned int)num;
- return (((tile_bundle_bits)(n & 0x00007fff)) << 43) |
- (((tile_bundle_bits)(n & 0x00018000)) << 20) |
- (((tile_bundle_bits)(n & 0x001e0000)) << 14) |
- (((tile_bundle_bits)(n & 0x07e00000)) << 16) |
- (((tile_bundle_bits)(n & 0x18000000)) << 31);
+ return (((tilegx_bundle_bits)(n & 0x0000003f)) << 31) |
+ (((tilegx_bundle_bits)(n & 0x00003fc0)) << 37);
}
-static __inline tile_bundle_bits
-create_JOff_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tile_bundle_bits)(n & 0x00007fff)) << 43) |
- (((tile_bundle_bits)(n & 0x00018000)) << 20) |
- (((tile_bundle_bits)(n & 0x001e0000)) << 14) |
- (((tile_bundle_bits)(n & 0x07e00000)) << 16) |
- (((tile_bundle_bits)(n & 0x08000000)) << 31);
-}
-
-static __inline tile_bundle_bits
-create_MF_Imm15_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tile_bundle_bits)(n & 0x00003fff)) << 37) |
- (((tile_bundle_bits)(n & 0x00004000)) << 44);
-}
-
-static __inline tile_bundle_bits
-create_MMEnd_X0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x1f) << 18);
-}
-
-static __inline tile_bundle_bits
-create_MMEnd_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tile_bundle_bits)(n & 0x1f)) << 49);
-}
-
-static __inline tile_bundle_bits
-create_MMStart_X0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x1f) << 23);
-}
-
-static __inline tile_bundle_bits
-create_MMStart_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tile_bundle_bits)(n & 0x1f)) << 54);
-}
-
-static __inline tile_bundle_bits
-create_MT_Imm15_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tile_bundle_bits)(n & 0x0000003f)) << 31) |
- (((tile_bundle_bits)(n & 0x00003fc0)) << 37) |
- (((tile_bundle_bits)(n & 0x00004000)) << 44);
-}
-
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
create_Mode(int num)
{
const unsigned int n = (unsigned int)num;
- return (((tile_bundle_bits)(n & 0x1)) << 63);
+ return (((tilegx_bundle_bits)(n & 0x3)) << 62);
}
-static __inline tile_bundle_bits
-create_NoRegOpcodeExtension_SN(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0xf) << 0);
-}
-
-static __inline tile_bundle_bits
-create_Opcode_SN(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3f) << 10);
-}
-
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
create_Opcode_X0(int num)
{
const unsigned int n = (unsigned int)num;
return ((n & 0x7) << 28);
}
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
create_Opcode_X1(int num)
{
const unsigned int n = (unsigned int)num;
- return (((tile_bundle_bits)(n & 0xf)) << 59);
+ return (((tilegx_bundle_bits)(n & 0x7)) << 59);
}
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
create_Opcode_Y0(int num)
{
const unsigned int n = (unsigned int)num;
return ((n & 0xf) << 27);
}
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
create_Opcode_Y1(int num)
{
const unsigned int n = (unsigned int)num;
- return (((tile_bundle_bits)(n & 0xf)) << 59);
+ return (((tilegx_bundle_bits)(n & 0xf)) << 58);
}
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
create_Opcode_Y2(int num)
{
const unsigned int n = (unsigned int)num;
- return (((tile_bundle_bits)(n & 0x7)) << 56);
+ return ((n & 0x00000001) << 26) |
+ (((tilegx_bundle_bits)(n & 0x00000002)) << 56);
}
-static __inline tile_bundle_bits
-create_RROpcodeExtension_SN(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0xf) << 4);
-}
-
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
create_RRROpcodeExtension_X0(int num)
{
const unsigned int n = (unsigned int)num;
- return ((n & 0x1ff) << 18);
+ return ((n & 0x3ff) << 18);
}
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
create_RRROpcodeExtension_X1(int num)
{
const unsigned int n = (unsigned int)num;
- return (((tile_bundle_bits)(n & 0x1ff)) << 49);
+ return (((tilegx_bundle_bits)(n & 0x3ff)) << 49);
}
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
create_RRROpcodeExtension_Y0(int num)
{
const unsigned int n = (unsigned int)num;
return ((n & 0x3) << 18);
}
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
create_RRROpcodeExtension_Y1(int num)
{
const unsigned int n = (unsigned int)num;
- return (((tile_bundle_bits)(n & 0x3)) << 49);
+ return (((tilegx_bundle_bits)(n & 0x3)) << 49);
}
-static __inline tile_bundle_bits
-create_RouteOpcodeExtension_SN(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3ff) << 0);
-}
-
-static __inline tile_bundle_bits
-create_S_X0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x1) << 27);
-}
-
-static __inline tile_bundle_bits
-create_S_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tile_bundle_bits)(n & 0x1)) << 58);
-}
-
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
create_ShAmt_X0(int num)
{
const unsigned int n = (unsigned int)num;
- return ((n & 0x1f) << 12);
+ return ((n & 0x3f) << 12);
}
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
create_ShAmt_X1(int num)
{
const unsigned int n = (unsigned int)num;
- return (((tile_bundle_bits)(n & 0x1f)) << 43);
+ return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
}
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
create_ShAmt_Y0(int num)
{
const unsigned int n = (unsigned int)num;
- return ((n & 0x1f) << 12);
+ return ((n & 0x3f) << 12);
}
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
create_ShAmt_Y1(int num)
{
const unsigned int n = (unsigned int)num;
- return (((tile_bundle_bits)(n & 0x1f)) << 43);
+ return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
}
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
+create_ShiftOpcodeExtension_X0(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return ((n & 0x3ff) << 18);
+}
+
+static __inline tilegx_bundle_bits
+create_ShiftOpcodeExtension_X1(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((tilegx_bundle_bits)(n & 0x3ff)) << 49);
+}
+
+static __inline tilegx_bundle_bits
+create_ShiftOpcodeExtension_Y0(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return ((n & 0x3) << 18);
+}
+
+static __inline tilegx_bundle_bits
+create_ShiftOpcodeExtension_Y1(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((tilegx_bundle_bits)(n & 0x3)) << 49);
+}
+
+static __inline tilegx_bundle_bits
create_SrcA_X0(int num)
{
const unsigned int n = (unsigned int)num;
return ((n & 0x3f) << 6);
}
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
create_SrcA_X1(int num)
{
const unsigned int n = (unsigned int)num;
- return (((tile_bundle_bits)(n & 0x3f)) << 37);
+ return (((tilegx_bundle_bits)(n & 0x3f)) << 37);
}
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
create_SrcA_Y0(int num)
{
const unsigned int n = (unsigned int)num;
return ((n & 0x3f) << 6);
}
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
create_SrcA_Y1(int num)
{
const unsigned int n = (unsigned int)num;
- return (((tile_bundle_bits)(n & 0x3f)) << 37);
+ return (((tilegx_bundle_bits)(n & 0x3f)) << 37);
}
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
create_SrcA_Y2(int num)
{
const unsigned int n = (unsigned int)num;
- return ((n & 0x00000001) << 26) |
- (((tile_bundle_bits)(n & 0x0000003e)) << 50);
-}
-
-static __inline tile_bundle_bits
-create_SrcBDest_Y2(int num)
-{
- const unsigned int n = (unsigned int)num;
return ((n & 0x3f) << 20);
}
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
+create_SrcBDest_Y2(int num)
+{
+ const unsigned int n = (unsigned int)num;
+ return (((tilegx_bundle_bits)(n & 0x3f)) << 51);
+}
+
+static __inline tilegx_bundle_bits
create_SrcB_X0(int num)
{
const unsigned int n = (unsigned int)num;
return ((n & 0x3f) << 12);
}
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
create_SrcB_X1(int num)
{
const unsigned int n = (unsigned int)num;
- return (((tile_bundle_bits)(n & 0x3f)) << 43);
+ return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
}
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
create_SrcB_Y0(int num)
{
const unsigned int n = (unsigned int)num;
return ((n & 0x3f) << 12);
}
-static __inline tile_bundle_bits
+static __inline tilegx_bundle_bits
create_SrcB_Y1(int num)
{
const unsigned int n = (unsigned int)num;
- return (((tile_bundle_bits)(n & 0x3f)) << 43);
+ return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
}
-static __inline tile_bundle_bits
-create_Src_SN(int num)
+static __inline tilegx_bundle_bits
+create_UnaryOpcodeExtension_X0(int num)
{
const unsigned int n = (unsigned int)num;
- return ((n & 0x3) << 0);
+ return ((n & 0x3f) << 12);
}
-static __inline tile_bundle_bits
-create_UnOpcodeExtension_X0(int num)
+static __inline tilegx_bundle_bits
+create_UnaryOpcodeExtension_X1(int num)
{
const unsigned int n = (unsigned int)num;
- return ((n & 0x1f) << 12);
+ return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
}
-static __inline tile_bundle_bits
-create_UnOpcodeExtension_X1(int num)
+static __inline tilegx_bundle_bits
+create_UnaryOpcodeExtension_Y0(int num)
{
const unsigned int n = (unsigned int)num;
- return (((tile_bundle_bits)(n & 0x1f)) << 43);
+ return ((n & 0x3f) << 12);
}
-static __inline tile_bundle_bits
-create_UnOpcodeExtension_Y0(int num)
+static __inline tilegx_bundle_bits
+create_UnaryOpcodeExtension_Y1(int num)
{
const unsigned int n = (unsigned int)num;
- return ((n & 0x1f) << 12);
+ return (((tilegx_bundle_bits)(n & 0x3f)) << 43);
}
-static __inline tile_bundle_bits
-create_UnOpcodeExtension_Y1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tile_bundle_bits)(n & 0x1f)) << 43);
-}
-
-static __inline tile_bundle_bits
-create_UnShOpcodeExtension_X0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x3ff) << 17);
-}
-
-static __inline tile_bundle_bits
-create_UnShOpcodeExtension_X1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tile_bundle_bits)(n & 0x3ff)) << 48);
-}
-
-static __inline tile_bundle_bits
-create_UnShOpcodeExtension_Y0(int num)
-{
- const unsigned int n = (unsigned int)num;
- return ((n & 0x7) << 17);
-}
-
-static __inline tile_bundle_bits
-create_UnShOpcodeExtension_Y1(int num)
-{
- const unsigned int n = (unsigned int)num;
- return (((tile_bundle_bits)(n & 0x7)) << 48);
-}
-
-
typedef enum
{
- TILE_PIPELINE_X0,
- TILE_PIPELINE_X1,
- TILE_PIPELINE_Y0,
- TILE_PIPELINE_Y1,
- TILE_PIPELINE_Y2,
-} tile_pipeline;
+ TILEGX_PIPELINE_X0,
+ TILEGX_PIPELINE_X1,
+ TILEGX_PIPELINE_Y0,
+ TILEGX_PIPELINE_Y1,
+ TILEGX_PIPELINE_Y2,
+} tilegx_pipeline;
-#define tile_is_x_pipeline(p) ((int)(p) <= (int)TILE_PIPELINE_X1)
+#define tilegx_is_x_pipeline(p) ((int)(p) <= (int)TILEGX_PIPELINE_X1)
typedef enum
{
- TILE_OP_TYPE_REGISTER,
- TILE_OP_TYPE_IMMEDIATE,
- TILE_OP_TYPE_ADDRESS,
- TILE_OP_TYPE_SPR
-} tile_operand_type;
+ TILEGX_OP_TYPE_REGISTER,
+ TILEGX_OP_TYPE_IMMEDIATE,
+ TILEGX_OP_TYPE_ADDRESS,
+ TILEGX_OP_TYPE_SPR
+} tilegx_operand_type;
-/* This is the bit that determines if a bundle is in the Y encoding. */
-#define TILE_BUNDLE_Y_ENCODING_MASK ((tile_bundle_bits)1 << 63)
+/* These are the bits that determine if a bundle is in the X encoding. */
+#define TILEGX_BUNDLE_MODE_MASK ((tilegx_bundle_bits)3 << 62)
enum
{
/* Maximum number of instructions in a bundle (2 for X, 3 for Y). */
- TILE_MAX_INSTRUCTIONS_PER_BUNDLE = 3,
+ TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE = 3,
/* How many different pipeline encodings are there? X0, X1, Y0, Y1, Y2. */
- TILE_NUM_PIPELINE_ENCODINGS = 5,
+ TILEGX_NUM_PIPELINE_ENCODINGS = 5,
- /* Log base 2 of TILE_BUNDLE_SIZE_IN_BYTES. */
- TILE_LOG2_BUNDLE_SIZE_IN_BYTES = 3,
+ /* Log base 2 of TILEGX_BUNDLE_SIZE_IN_BYTES. */
+ TILEGX_LOG2_BUNDLE_SIZE_IN_BYTES = 3,
/* Instructions take this many bytes. */
- TILE_BUNDLE_SIZE_IN_BYTES = 1 << TILE_LOG2_BUNDLE_SIZE_IN_BYTES,
+ TILEGX_BUNDLE_SIZE_IN_BYTES = 1 << TILEGX_LOG2_BUNDLE_SIZE_IN_BYTES,
- /* Log base 2 of TILE_BUNDLE_ALIGNMENT_IN_BYTES. */
- TILE_LOG2_BUNDLE_ALIGNMENT_IN_BYTES = 3,
+ /* Log base 2 of TILEGX_BUNDLE_ALIGNMENT_IN_BYTES. */
+ TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES = 3,
/* Bundles should be aligned modulo this number of bytes. */
- TILE_BUNDLE_ALIGNMENT_IN_BYTES =
- (1 << TILE_LOG2_BUNDLE_ALIGNMENT_IN_BYTES),
-
- /* Log base 2 of TILE_SN_INSTRUCTION_SIZE_IN_BYTES. */
- TILE_LOG2_SN_INSTRUCTION_SIZE_IN_BYTES = 1,
-
- /* Static network instructions take this many bytes. */
- TILE_SN_INSTRUCTION_SIZE_IN_BYTES =
- (1 << TILE_LOG2_SN_INSTRUCTION_SIZE_IN_BYTES),
+ TILEGX_BUNDLE_ALIGNMENT_IN_BYTES =
+ (1 << TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES),
/* Number of registers (some are magic, such as network I/O). */
- TILE_NUM_REGISTERS = 64,
-
- /* Number of static network registers. */
- TILE_NUM_SN_REGISTERS = 4
+ TILEGX_NUM_REGISTERS = 64,
};
-struct tile_operand
+struct tilegx_operand
{
/* Is this operand a register, immediate or address? */
- tile_operand_type type;
+ tilegx_operand_type type;
/* The default relocation type for this operand. */
signed int default_reloc : 16;
@@ -1437,27 +1180,27 @@
unsigned int rightshift : 2;
/* Return the bits for this operand to be ORed into an existing bundle. */
- tile_bundle_bits (*insert) (int op);
+ tilegx_bundle_bits (*insert) (int op);
/* Extract this operand and return it. */
- unsigned int (*extract) (tile_bundle_bits bundle);
+ unsigned int (*extract) (tilegx_bundle_bits bundle);
};
-extern const struct tile_operand tile_operands[];
+extern const struct tilegx_operand tilegx_operands[];
/* One finite-state machine per pipe for rapid instruction decoding. */
extern const unsigned short * const
-tile_bundle_decoder_fsms[TILE_NUM_PIPELINE_ENCODINGS];
+tilegx_bundle_decoder_fsms[TILEGX_NUM_PIPELINE_ENCODINGS];
-struct tile_opcode
+struct tilegx_opcode
{
/* The opcode mnemonic, e.g. "add" */
const char *name;
/* The enum value for this mnemonic. */
- tile_mnemonic mnemonic;
+ tilegx_mnemonic mnemonic;
/* A bit mask of which of the five pipes this instruction
is compatible with:
@@ -1478,29 +1221,28 @@
unsigned char can_bundle;
/* The description of the operands. Each of these is an
- * index into the tile_operands[] table. */
- unsigned char operands[TILE_NUM_PIPELINE_ENCODINGS][TILE_MAX_OPERANDS];
+ * index into the tilegx_operands[] table. */
+ unsigned char operands[TILEGX_NUM_PIPELINE_ENCODINGS][TILEGX_MAX_OPERANDS];
};
-extern const struct tile_opcode tile_opcodes[];
-
+extern const struct tilegx_opcode tilegx_opcodes[];
/* Used for non-textual disassembly into structs. */
-struct tile_decoded_instruction
+struct tilegx_decoded_instruction
{
- const struct tile_opcode *opcode;
- const struct tile_operand *operands[TILE_MAX_OPERANDS];
- int operand_values[TILE_MAX_OPERANDS];
+ const struct tilegx_opcode *opcode;
+ const struct tilegx_operand *operands[TILEGX_MAX_OPERANDS];
+ long long operand_values[TILEGX_MAX_OPERANDS];
};
/* Disassemble a bundle into a struct for machine processing. */
-extern int parse_insn_tile(tile_bundle_bits bits,
- unsigned int pc,
- struct tile_decoded_instruction
- decoded[TILE_MAX_INSTRUCTIONS_PER_BUNDLE]);
+extern int parse_insn_tilegx(tilegx_bundle_bits bits,
+ unsigned long long pc,
+ struct tilegx_decoded_instruction
+ decoded[TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE]);
-#endif /* opcode_tile_h */
+#endif /* opcode_tilegx_h */
diff --git a/arch/tile/include/asm/opcode_constants_64.h b/arch/tile/include/asm/opcode_constants_64.h
index 227d033..7101928 100644
--- a/arch/tile/include/asm/opcode_constants_64.h
+++ b/arch/tile/include/asm/opcode_constants_64.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
+ * Copyright 2011 Tilera Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@@ -19,462 +19,591 @@
#define _TILE_OPCODE_CONSTANTS_H
enum
{
- ADDBS_U_SPECIAL_0_OPCODE_X0 = 98,
- ADDBS_U_SPECIAL_0_OPCODE_X1 = 68,
- ADDB_SPECIAL_0_OPCODE_X0 = 1,
- ADDB_SPECIAL_0_OPCODE_X1 = 1,
- ADDHS_SPECIAL_0_OPCODE_X0 = 99,
- ADDHS_SPECIAL_0_OPCODE_X1 = 69,
- ADDH_SPECIAL_0_OPCODE_X0 = 2,
- ADDH_SPECIAL_0_OPCODE_X1 = 2,
- ADDIB_IMM_0_OPCODE_X0 = 1,
- ADDIB_IMM_0_OPCODE_X1 = 1,
- ADDIH_IMM_0_OPCODE_X0 = 2,
- ADDIH_IMM_0_OPCODE_X1 = 2,
- ADDI_IMM_0_OPCODE_X0 = 3,
- ADDI_IMM_0_OPCODE_X1 = 3,
- ADDI_IMM_1_OPCODE_SN = 1,
- ADDI_OPCODE_Y0 = 9,
- ADDI_OPCODE_Y1 = 7,
- ADDLIS_OPCODE_X0 = 1,
- ADDLIS_OPCODE_X1 = 2,
- ADDLI_OPCODE_X0 = 2,
- ADDLI_OPCODE_X1 = 3,
- ADDS_SPECIAL_0_OPCODE_X0 = 96,
- ADDS_SPECIAL_0_OPCODE_X1 = 66,
- ADD_SPECIAL_0_OPCODE_X0 = 3,
- ADD_SPECIAL_0_OPCODE_X1 = 3,
- ADD_SPECIAL_0_OPCODE_Y0 = 0,
- ADD_SPECIAL_0_OPCODE_Y1 = 0,
- ADIFFB_U_SPECIAL_0_OPCODE_X0 = 4,
- ADIFFH_SPECIAL_0_OPCODE_X0 = 5,
- ANDI_IMM_0_OPCODE_X0 = 1,
- ANDI_IMM_0_OPCODE_X1 = 4,
- ANDI_OPCODE_Y0 = 10,
- ANDI_OPCODE_Y1 = 8,
- AND_SPECIAL_0_OPCODE_X0 = 6,
- AND_SPECIAL_0_OPCODE_X1 = 4,
- AND_SPECIAL_2_OPCODE_Y0 = 0,
- AND_SPECIAL_2_OPCODE_Y1 = 0,
- AULI_OPCODE_X0 = 3,
- AULI_OPCODE_X1 = 4,
- AVGB_U_SPECIAL_0_OPCODE_X0 = 7,
- AVGH_SPECIAL_0_OPCODE_X0 = 8,
- BBNST_BRANCH_OPCODE_X1 = 15,
- BBNS_BRANCH_OPCODE_X1 = 14,
- BBNS_OPCODE_SN = 63,
- BBST_BRANCH_OPCODE_X1 = 13,
- BBS_BRANCH_OPCODE_X1 = 12,
- BBS_OPCODE_SN = 62,
- BGEZT_BRANCH_OPCODE_X1 = 7,
- BGEZ_BRANCH_OPCODE_X1 = 6,
- BGEZ_OPCODE_SN = 61,
- BGZT_BRANCH_OPCODE_X1 = 5,
- BGZ_BRANCH_OPCODE_X1 = 4,
- BGZ_OPCODE_SN = 58,
- BITX_UN_0_SHUN_0_OPCODE_X0 = 1,
- BITX_UN_0_SHUN_0_OPCODE_Y0 = 1,
- BLEZT_BRANCH_OPCODE_X1 = 11,
- BLEZ_BRANCH_OPCODE_X1 = 10,
- BLEZ_OPCODE_SN = 59,
- BLZT_BRANCH_OPCODE_X1 = 9,
- BLZ_BRANCH_OPCODE_X1 = 8,
- BLZ_OPCODE_SN = 60,
- BNZT_BRANCH_OPCODE_X1 = 3,
- BNZ_BRANCH_OPCODE_X1 = 2,
- BNZ_OPCODE_SN = 57,
- BPT_NOREG_RR_IMM_0_OPCODE_SN = 1,
- BRANCH_OPCODE_X1 = 5,
- BYTEX_UN_0_SHUN_0_OPCODE_X0 = 2,
- BYTEX_UN_0_SHUN_0_OPCODE_Y0 = 2,
- BZT_BRANCH_OPCODE_X1 = 1,
- BZ_BRANCH_OPCODE_X1 = 0,
- BZ_OPCODE_SN = 56,
- CLZ_UN_0_SHUN_0_OPCODE_X0 = 3,
- CLZ_UN_0_SHUN_0_OPCODE_Y0 = 3,
- CRC32_32_SPECIAL_0_OPCODE_X0 = 9,
- CRC32_8_SPECIAL_0_OPCODE_X0 = 10,
- CTZ_UN_0_SHUN_0_OPCODE_X0 = 4,
- CTZ_UN_0_SHUN_0_OPCODE_Y0 = 4,
- DRAIN_UN_0_SHUN_0_OPCODE_X1 = 1,
- DTLBPR_UN_0_SHUN_0_OPCODE_X1 = 2,
- DWORD_ALIGN_SPECIAL_0_OPCODE_X0 = 95,
- FINV_UN_0_SHUN_0_OPCODE_X1 = 3,
- FLUSH_UN_0_SHUN_0_OPCODE_X1 = 4,
- FNOP_NOREG_RR_IMM_0_OPCODE_SN = 3,
- FNOP_UN_0_SHUN_0_OPCODE_X0 = 5,
- FNOP_UN_0_SHUN_0_OPCODE_X1 = 5,
- FNOP_UN_0_SHUN_0_OPCODE_Y0 = 5,
- FNOP_UN_0_SHUN_0_OPCODE_Y1 = 1,
- HALT_NOREG_RR_IMM_0_OPCODE_SN = 0,
- ICOH_UN_0_SHUN_0_OPCODE_X1 = 6,
- ILL_UN_0_SHUN_0_OPCODE_X1 = 7,
- ILL_UN_0_SHUN_0_OPCODE_Y1 = 2,
- IMM_0_OPCODE_SN = 0,
- IMM_0_OPCODE_X0 = 4,
- IMM_0_OPCODE_X1 = 6,
- IMM_1_OPCODE_SN = 1,
- IMM_OPCODE_0_X0 = 5,
- INTHB_SPECIAL_0_OPCODE_X0 = 11,
- INTHB_SPECIAL_0_OPCODE_X1 = 5,
- INTHH_SPECIAL_0_OPCODE_X0 = 12,
- INTHH_SPECIAL_0_OPCODE_X1 = 6,
- INTLB_SPECIAL_0_OPCODE_X0 = 13,
- INTLB_SPECIAL_0_OPCODE_X1 = 7,
- INTLH_SPECIAL_0_OPCODE_X0 = 14,
- INTLH_SPECIAL_0_OPCODE_X1 = 8,
- INV_UN_0_SHUN_0_OPCODE_X1 = 8,
- IRET_UN_0_SHUN_0_OPCODE_X1 = 9,
- JALB_OPCODE_X1 = 13,
- JALF_OPCODE_X1 = 12,
- JALRP_SPECIAL_0_OPCODE_X1 = 9,
- JALRR_IMM_1_OPCODE_SN = 3,
- JALR_RR_IMM_0_OPCODE_SN = 5,
- JALR_SPECIAL_0_OPCODE_X1 = 10,
- JB_OPCODE_X1 = 11,
- JF_OPCODE_X1 = 10,
- JRP_SPECIAL_0_OPCODE_X1 = 11,
- JRR_IMM_1_OPCODE_SN = 2,
- JR_RR_IMM_0_OPCODE_SN = 4,
- JR_SPECIAL_0_OPCODE_X1 = 12,
- LBADD_IMM_0_OPCODE_X1 = 22,
- LBADD_U_IMM_0_OPCODE_X1 = 23,
- LB_OPCODE_Y2 = 0,
- LB_UN_0_SHUN_0_OPCODE_X1 = 10,
- LB_U_OPCODE_Y2 = 1,
- LB_U_UN_0_SHUN_0_OPCODE_X1 = 11,
- LHADD_IMM_0_OPCODE_X1 = 24,
- LHADD_U_IMM_0_OPCODE_X1 = 25,
- LH_OPCODE_Y2 = 2,
- LH_UN_0_SHUN_0_OPCODE_X1 = 12,
- LH_U_OPCODE_Y2 = 3,
- LH_U_UN_0_SHUN_0_OPCODE_X1 = 13,
- LNK_SPECIAL_0_OPCODE_X1 = 13,
- LWADD_IMM_0_OPCODE_X1 = 26,
- LWADD_NA_IMM_0_OPCODE_X1 = 27,
- LW_NA_UN_0_SHUN_0_OPCODE_X1 = 24,
- LW_OPCODE_Y2 = 4,
- LW_UN_0_SHUN_0_OPCODE_X1 = 14,
- MAXB_U_SPECIAL_0_OPCODE_X0 = 15,
- MAXB_U_SPECIAL_0_OPCODE_X1 = 14,
- MAXH_SPECIAL_0_OPCODE_X0 = 16,
- MAXH_SPECIAL_0_OPCODE_X1 = 15,
- MAXIB_U_IMM_0_OPCODE_X0 = 4,
- MAXIB_U_IMM_0_OPCODE_X1 = 5,
- MAXIH_IMM_0_OPCODE_X0 = 5,
- MAXIH_IMM_0_OPCODE_X1 = 6,
- MFSPR_IMM_0_OPCODE_X1 = 7,
- MF_UN_0_SHUN_0_OPCODE_X1 = 15,
- MINB_U_SPECIAL_0_OPCODE_X0 = 17,
- MINB_U_SPECIAL_0_OPCODE_X1 = 16,
- MINH_SPECIAL_0_OPCODE_X0 = 18,
- MINH_SPECIAL_0_OPCODE_X1 = 17,
- MINIB_U_IMM_0_OPCODE_X0 = 6,
- MINIB_U_IMM_0_OPCODE_X1 = 8,
- MINIH_IMM_0_OPCODE_X0 = 7,
- MINIH_IMM_0_OPCODE_X1 = 9,
- MM_OPCODE_X0 = 6,
- MM_OPCODE_X1 = 7,
- MNZB_SPECIAL_0_OPCODE_X0 = 19,
- MNZB_SPECIAL_0_OPCODE_X1 = 18,
- MNZH_SPECIAL_0_OPCODE_X0 = 20,
- MNZH_SPECIAL_0_OPCODE_X1 = 19,
- MNZ_SPECIAL_0_OPCODE_X0 = 21,
- MNZ_SPECIAL_0_OPCODE_X1 = 20,
- MNZ_SPECIAL_1_OPCODE_Y0 = 0,
- MNZ_SPECIAL_1_OPCODE_Y1 = 1,
- MOVEI_IMM_1_OPCODE_SN = 0,
- MOVE_RR_IMM_0_OPCODE_SN = 8,
- MTSPR_IMM_0_OPCODE_X1 = 10,
- MULHHA_SS_SPECIAL_0_OPCODE_X0 = 22,
- MULHHA_SS_SPECIAL_7_OPCODE_Y0 = 0,
- MULHHA_SU_SPECIAL_0_OPCODE_X0 = 23,
- MULHHA_UU_SPECIAL_0_OPCODE_X0 = 24,
- MULHHA_UU_SPECIAL_7_OPCODE_Y0 = 1,
- MULHHSA_UU_SPECIAL_0_OPCODE_X0 = 25,
- MULHH_SS_SPECIAL_0_OPCODE_X0 = 26,
- MULHH_SS_SPECIAL_6_OPCODE_Y0 = 0,
- MULHH_SU_SPECIAL_0_OPCODE_X0 = 27,
- MULHH_UU_SPECIAL_0_OPCODE_X0 = 28,
- MULHH_UU_SPECIAL_6_OPCODE_Y0 = 1,
- MULHLA_SS_SPECIAL_0_OPCODE_X0 = 29,
- MULHLA_SU_SPECIAL_0_OPCODE_X0 = 30,
- MULHLA_US_SPECIAL_0_OPCODE_X0 = 31,
- MULHLA_UU_SPECIAL_0_OPCODE_X0 = 32,
- MULHLSA_UU_SPECIAL_0_OPCODE_X0 = 33,
- MULHLSA_UU_SPECIAL_5_OPCODE_Y0 = 0,
- MULHL_SS_SPECIAL_0_OPCODE_X0 = 34,
- MULHL_SU_SPECIAL_0_OPCODE_X0 = 35,
- MULHL_US_SPECIAL_0_OPCODE_X0 = 36,
- MULHL_UU_SPECIAL_0_OPCODE_X0 = 37,
- MULLLA_SS_SPECIAL_0_OPCODE_X0 = 38,
- MULLLA_SS_SPECIAL_7_OPCODE_Y0 = 2,
- MULLLA_SU_SPECIAL_0_OPCODE_X0 = 39,
- MULLLA_UU_SPECIAL_0_OPCODE_X0 = 40,
- MULLLA_UU_SPECIAL_7_OPCODE_Y0 = 3,
- MULLLSA_UU_SPECIAL_0_OPCODE_X0 = 41,
- MULLL_SS_SPECIAL_0_OPCODE_X0 = 42,
- MULLL_SS_SPECIAL_6_OPCODE_Y0 = 2,
- MULLL_SU_SPECIAL_0_OPCODE_X0 = 43,
- MULLL_UU_SPECIAL_0_OPCODE_X0 = 44,
- MULLL_UU_SPECIAL_6_OPCODE_Y0 = 3,
- MVNZ_SPECIAL_0_OPCODE_X0 = 45,
- MVNZ_SPECIAL_1_OPCODE_Y0 = 1,
- MVZ_SPECIAL_0_OPCODE_X0 = 46,
- MVZ_SPECIAL_1_OPCODE_Y0 = 2,
- MZB_SPECIAL_0_OPCODE_X0 = 47,
- MZB_SPECIAL_0_OPCODE_X1 = 21,
- MZH_SPECIAL_0_OPCODE_X0 = 48,
- MZH_SPECIAL_0_OPCODE_X1 = 22,
- MZ_SPECIAL_0_OPCODE_X0 = 49,
- MZ_SPECIAL_0_OPCODE_X1 = 23,
- MZ_SPECIAL_1_OPCODE_Y0 = 3,
- MZ_SPECIAL_1_OPCODE_Y1 = 2,
- NAP_UN_0_SHUN_0_OPCODE_X1 = 16,
- NOP_NOREG_RR_IMM_0_OPCODE_SN = 2,
- NOP_UN_0_SHUN_0_OPCODE_X0 = 6,
- NOP_UN_0_SHUN_0_OPCODE_X1 = 17,
- NOP_UN_0_SHUN_0_OPCODE_Y0 = 6,
- NOP_UN_0_SHUN_0_OPCODE_Y1 = 3,
- NOREG_RR_IMM_0_OPCODE_SN = 0,
- NOR_SPECIAL_0_OPCODE_X0 = 50,
- NOR_SPECIAL_0_OPCODE_X1 = 24,
- NOR_SPECIAL_2_OPCODE_Y0 = 1,
- NOR_SPECIAL_2_OPCODE_Y1 = 1,
- ORI_IMM_0_OPCODE_X0 = 8,
- ORI_IMM_0_OPCODE_X1 = 11,
- ORI_OPCODE_Y0 = 11,
- ORI_OPCODE_Y1 = 9,
- OR_SPECIAL_0_OPCODE_X0 = 51,
- OR_SPECIAL_0_OPCODE_X1 = 25,
- OR_SPECIAL_2_OPCODE_Y0 = 2,
- OR_SPECIAL_2_OPCODE_Y1 = 2,
- PACKBS_U_SPECIAL_0_OPCODE_X0 = 103,
- PACKBS_U_SPECIAL_0_OPCODE_X1 = 73,
- PACKHB_SPECIAL_0_OPCODE_X0 = 52,
- PACKHB_SPECIAL_0_OPCODE_X1 = 26,
- PACKHS_SPECIAL_0_OPCODE_X0 = 102,
- PACKHS_SPECIAL_0_OPCODE_X1 = 72,
- PACKLB_SPECIAL_0_OPCODE_X0 = 53,
- PACKLB_SPECIAL_0_OPCODE_X1 = 27,
- PCNT_UN_0_SHUN_0_OPCODE_X0 = 7,
- PCNT_UN_0_SHUN_0_OPCODE_Y0 = 7,
- RLI_SHUN_0_OPCODE_X0 = 1,
- RLI_SHUN_0_OPCODE_X1 = 1,
- RLI_SHUN_0_OPCODE_Y0 = 1,
- RLI_SHUN_0_OPCODE_Y1 = 1,
- RL_SPECIAL_0_OPCODE_X0 = 54,
- RL_SPECIAL_0_OPCODE_X1 = 28,
- RL_SPECIAL_3_OPCODE_Y0 = 0,
- RL_SPECIAL_3_OPCODE_Y1 = 0,
- RR_IMM_0_OPCODE_SN = 0,
- S1A_SPECIAL_0_OPCODE_X0 = 55,
- S1A_SPECIAL_0_OPCODE_X1 = 29,
- S1A_SPECIAL_0_OPCODE_Y0 = 1,
- S1A_SPECIAL_0_OPCODE_Y1 = 1,
- S2A_SPECIAL_0_OPCODE_X0 = 56,
- S2A_SPECIAL_0_OPCODE_X1 = 30,
- S2A_SPECIAL_0_OPCODE_Y0 = 2,
- S2A_SPECIAL_0_OPCODE_Y1 = 2,
- S3A_SPECIAL_0_OPCODE_X0 = 57,
- S3A_SPECIAL_0_OPCODE_X1 = 31,
- S3A_SPECIAL_5_OPCODE_Y0 = 1,
- S3A_SPECIAL_5_OPCODE_Y1 = 1,
- SADAB_U_SPECIAL_0_OPCODE_X0 = 58,
- SADAH_SPECIAL_0_OPCODE_X0 = 59,
- SADAH_U_SPECIAL_0_OPCODE_X0 = 60,
- SADB_U_SPECIAL_0_OPCODE_X0 = 61,
- SADH_SPECIAL_0_OPCODE_X0 = 62,
- SADH_U_SPECIAL_0_OPCODE_X0 = 63,
- SBADD_IMM_0_OPCODE_X1 = 28,
- SB_OPCODE_Y2 = 5,
- SB_SPECIAL_0_OPCODE_X1 = 32,
- SEQB_SPECIAL_0_OPCODE_X0 = 64,
- SEQB_SPECIAL_0_OPCODE_X1 = 33,
- SEQH_SPECIAL_0_OPCODE_X0 = 65,
- SEQH_SPECIAL_0_OPCODE_X1 = 34,
- SEQIB_IMM_0_OPCODE_X0 = 9,
- SEQIB_IMM_0_OPCODE_X1 = 12,
- SEQIH_IMM_0_OPCODE_X0 = 10,
- SEQIH_IMM_0_OPCODE_X1 = 13,
- SEQI_IMM_0_OPCODE_X0 = 11,
- SEQI_IMM_0_OPCODE_X1 = 14,
- SEQI_OPCODE_Y0 = 12,
- SEQI_OPCODE_Y1 = 10,
- SEQ_SPECIAL_0_OPCODE_X0 = 66,
- SEQ_SPECIAL_0_OPCODE_X1 = 35,
- SEQ_SPECIAL_5_OPCODE_Y0 = 2,
- SEQ_SPECIAL_5_OPCODE_Y1 = 2,
- SHADD_IMM_0_OPCODE_X1 = 29,
- SHL8II_IMM_0_OPCODE_SN = 3,
- SHLB_SPECIAL_0_OPCODE_X0 = 67,
- SHLB_SPECIAL_0_OPCODE_X1 = 36,
- SHLH_SPECIAL_0_OPCODE_X0 = 68,
- SHLH_SPECIAL_0_OPCODE_X1 = 37,
- SHLIB_SHUN_0_OPCODE_X0 = 2,
- SHLIB_SHUN_0_OPCODE_X1 = 2,
- SHLIH_SHUN_0_OPCODE_X0 = 3,
- SHLIH_SHUN_0_OPCODE_X1 = 3,
- SHLI_SHUN_0_OPCODE_X0 = 4,
- SHLI_SHUN_0_OPCODE_X1 = 4,
- SHLI_SHUN_0_OPCODE_Y0 = 2,
- SHLI_SHUN_0_OPCODE_Y1 = 2,
- SHL_SPECIAL_0_OPCODE_X0 = 69,
- SHL_SPECIAL_0_OPCODE_X1 = 38,
- SHL_SPECIAL_3_OPCODE_Y0 = 1,
- SHL_SPECIAL_3_OPCODE_Y1 = 1,
- SHR1_RR_IMM_0_OPCODE_SN = 9,
- SHRB_SPECIAL_0_OPCODE_X0 = 70,
- SHRB_SPECIAL_0_OPCODE_X1 = 39,
- SHRH_SPECIAL_0_OPCODE_X0 = 71,
- SHRH_SPECIAL_0_OPCODE_X1 = 40,
- SHRIB_SHUN_0_OPCODE_X0 = 5,
- SHRIB_SHUN_0_OPCODE_X1 = 5,
- SHRIH_SHUN_0_OPCODE_X0 = 6,
- SHRIH_SHUN_0_OPCODE_X1 = 6,
- SHRI_SHUN_0_OPCODE_X0 = 7,
- SHRI_SHUN_0_OPCODE_X1 = 7,
- SHRI_SHUN_0_OPCODE_Y0 = 3,
- SHRI_SHUN_0_OPCODE_Y1 = 3,
- SHR_SPECIAL_0_OPCODE_X0 = 72,
- SHR_SPECIAL_0_OPCODE_X1 = 41,
- SHR_SPECIAL_3_OPCODE_Y0 = 2,
- SHR_SPECIAL_3_OPCODE_Y1 = 2,
- SHUN_0_OPCODE_X0 = 7,
- SHUN_0_OPCODE_X1 = 8,
- SHUN_0_OPCODE_Y0 = 13,
- SHUN_0_OPCODE_Y1 = 11,
- SH_OPCODE_Y2 = 6,
- SH_SPECIAL_0_OPCODE_X1 = 42,
- SLTB_SPECIAL_0_OPCODE_X0 = 73,
- SLTB_SPECIAL_0_OPCODE_X1 = 43,
- SLTB_U_SPECIAL_0_OPCODE_X0 = 74,
- SLTB_U_SPECIAL_0_OPCODE_X1 = 44,
- SLTEB_SPECIAL_0_OPCODE_X0 = 75,
- SLTEB_SPECIAL_0_OPCODE_X1 = 45,
- SLTEB_U_SPECIAL_0_OPCODE_X0 = 76,
- SLTEB_U_SPECIAL_0_OPCODE_X1 = 46,
- SLTEH_SPECIAL_0_OPCODE_X0 = 77,
- SLTEH_SPECIAL_0_OPCODE_X1 = 47,
- SLTEH_U_SPECIAL_0_OPCODE_X0 = 78,
- SLTEH_U_SPECIAL_0_OPCODE_X1 = 48,
- SLTE_SPECIAL_0_OPCODE_X0 = 79,
- SLTE_SPECIAL_0_OPCODE_X1 = 49,
- SLTE_SPECIAL_4_OPCODE_Y0 = 0,
- SLTE_SPECIAL_4_OPCODE_Y1 = 0,
- SLTE_U_SPECIAL_0_OPCODE_X0 = 80,
- SLTE_U_SPECIAL_0_OPCODE_X1 = 50,
- SLTE_U_SPECIAL_4_OPCODE_Y0 = 1,
- SLTE_U_SPECIAL_4_OPCODE_Y1 = 1,
- SLTH_SPECIAL_0_OPCODE_X0 = 81,
- SLTH_SPECIAL_0_OPCODE_X1 = 51,
- SLTH_U_SPECIAL_0_OPCODE_X0 = 82,
- SLTH_U_SPECIAL_0_OPCODE_X1 = 52,
- SLTIB_IMM_0_OPCODE_X0 = 12,
- SLTIB_IMM_0_OPCODE_X1 = 15,
- SLTIB_U_IMM_0_OPCODE_X0 = 13,
- SLTIB_U_IMM_0_OPCODE_X1 = 16,
- SLTIH_IMM_0_OPCODE_X0 = 14,
- SLTIH_IMM_0_OPCODE_X1 = 17,
- SLTIH_U_IMM_0_OPCODE_X0 = 15,
- SLTIH_U_IMM_0_OPCODE_X1 = 18,
- SLTI_IMM_0_OPCODE_X0 = 16,
- SLTI_IMM_0_OPCODE_X1 = 19,
- SLTI_OPCODE_Y0 = 14,
- SLTI_OPCODE_Y1 = 12,
- SLTI_U_IMM_0_OPCODE_X0 = 17,
- SLTI_U_IMM_0_OPCODE_X1 = 20,
- SLTI_U_OPCODE_Y0 = 15,
- SLTI_U_OPCODE_Y1 = 13,
- SLT_SPECIAL_0_OPCODE_X0 = 83,
- SLT_SPECIAL_0_OPCODE_X1 = 53,
- SLT_SPECIAL_4_OPCODE_Y0 = 2,
- SLT_SPECIAL_4_OPCODE_Y1 = 2,
- SLT_U_SPECIAL_0_OPCODE_X0 = 84,
- SLT_U_SPECIAL_0_OPCODE_X1 = 54,
- SLT_U_SPECIAL_4_OPCODE_Y0 = 3,
- SLT_U_SPECIAL_4_OPCODE_Y1 = 3,
- SNEB_SPECIAL_0_OPCODE_X0 = 85,
- SNEB_SPECIAL_0_OPCODE_X1 = 55,
- SNEH_SPECIAL_0_OPCODE_X0 = 86,
- SNEH_SPECIAL_0_OPCODE_X1 = 56,
- SNE_SPECIAL_0_OPCODE_X0 = 87,
- SNE_SPECIAL_0_OPCODE_X1 = 57,
- SNE_SPECIAL_5_OPCODE_Y0 = 3,
- SNE_SPECIAL_5_OPCODE_Y1 = 3,
- SPECIAL_0_OPCODE_X0 = 0,
- SPECIAL_0_OPCODE_X1 = 1,
- SPECIAL_0_OPCODE_Y0 = 1,
- SPECIAL_0_OPCODE_Y1 = 1,
- SPECIAL_1_OPCODE_Y0 = 2,
- SPECIAL_1_OPCODE_Y1 = 2,
- SPECIAL_2_OPCODE_Y0 = 3,
- SPECIAL_2_OPCODE_Y1 = 3,
- SPECIAL_3_OPCODE_Y0 = 4,
- SPECIAL_3_OPCODE_Y1 = 4,
- SPECIAL_4_OPCODE_Y0 = 5,
- SPECIAL_4_OPCODE_Y1 = 5,
- SPECIAL_5_OPCODE_Y0 = 6,
- SPECIAL_5_OPCODE_Y1 = 6,
- SPECIAL_6_OPCODE_Y0 = 7,
- SPECIAL_7_OPCODE_Y0 = 8,
- SRAB_SPECIAL_0_OPCODE_X0 = 88,
- SRAB_SPECIAL_0_OPCODE_X1 = 58,
- SRAH_SPECIAL_0_OPCODE_X0 = 89,
- SRAH_SPECIAL_0_OPCODE_X1 = 59,
- SRAIB_SHUN_0_OPCODE_X0 = 8,
- SRAIB_SHUN_0_OPCODE_X1 = 8,
- SRAIH_SHUN_0_OPCODE_X0 = 9,
- SRAIH_SHUN_0_OPCODE_X1 = 9,
- SRAI_SHUN_0_OPCODE_X0 = 10,
- SRAI_SHUN_0_OPCODE_X1 = 10,
- SRAI_SHUN_0_OPCODE_Y0 = 4,
- SRAI_SHUN_0_OPCODE_Y1 = 4,
- SRA_SPECIAL_0_OPCODE_X0 = 90,
- SRA_SPECIAL_0_OPCODE_X1 = 60,
- SRA_SPECIAL_3_OPCODE_Y0 = 3,
- SRA_SPECIAL_3_OPCODE_Y1 = 3,
- SUBBS_U_SPECIAL_0_OPCODE_X0 = 100,
- SUBBS_U_SPECIAL_0_OPCODE_X1 = 70,
- SUBB_SPECIAL_0_OPCODE_X0 = 91,
- SUBB_SPECIAL_0_OPCODE_X1 = 61,
- SUBHS_SPECIAL_0_OPCODE_X0 = 101,
- SUBHS_SPECIAL_0_OPCODE_X1 = 71,
- SUBH_SPECIAL_0_OPCODE_X0 = 92,
- SUBH_SPECIAL_0_OPCODE_X1 = 62,
- SUBS_SPECIAL_0_OPCODE_X0 = 97,
- SUBS_SPECIAL_0_OPCODE_X1 = 67,
- SUB_SPECIAL_0_OPCODE_X0 = 93,
- SUB_SPECIAL_0_OPCODE_X1 = 63,
- SUB_SPECIAL_0_OPCODE_Y0 = 3,
- SUB_SPECIAL_0_OPCODE_Y1 = 3,
- SWADD_IMM_0_OPCODE_X1 = 30,
- SWINT0_UN_0_SHUN_0_OPCODE_X1 = 18,
- SWINT1_UN_0_SHUN_0_OPCODE_X1 = 19,
- SWINT2_UN_0_SHUN_0_OPCODE_X1 = 20,
- SWINT3_UN_0_SHUN_0_OPCODE_X1 = 21,
- SW_OPCODE_Y2 = 7,
- SW_SPECIAL_0_OPCODE_X1 = 64,
- TBLIDXB0_UN_0_SHUN_0_OPCODE_X0 = 8,
- TBLIDXB0_UN_0_SHUN_0_OPCODE_Y0 = 8,
- TBLIDXB1_UN_0_SHUN_0_OPCODE_X0 = 9,
- TBLIDXB1_UN_0_SHUN_0_OPCODE_Y0 = 9,
- TBLIDXB2_UN_0_SHUN_0_OPCODE_X0 = 10,
- TBLIDXB2_UN_0_SHUN_0_OPCODE_Y0 = 10,
- TBLIDXB3_UN_0_SHUN_0_OPCODE_X0 = 11,
- TBLIDXB3_UN_0_SHUN_0_OPCODE_Y0 = 11,
- TNS_UN_0_SHUN_0_OPCODE_X1 = 22,
- UN_0_SHUN_0_OPCODE_X0 = 11,
- UN_0_SHUN_0_OPCODE_X1 = 11,
- UN_0_SHUN_0_OPCODE_Y0 = 5,
- UN_0_SHUN_0_OPCODE_Y1 = 5,
- WH64_UN_0_SHUN_0_OPCODE_X1 = 23,
- XORI_IMM_0_OPCODE_X0 = 2,
- XORI_IMM_0_OPCODE_X1 = 21,
- XOR_SPECIAL_0_OPCODE_X0 = 94,
- XOR_SPECIAL_0_OPCODE_X1 = 65,
- XOR_SPECIAL_2_OPCODE_Y0 = 3,
- XOR_SPECIAL_2_OPCODE_Y1 = 3
+ ADDI_IMM8_OPCODE_X0 = 1,
+ ADDI_IMM8_OPCODE_X1 = 1,
+ ADDI_OPCODE_Y0 = 0,
+ ADDI_OPCODE_Y1 = 1,
+ ADDLI_OPCODE_X0 = 1,
+ ADDLI_OPCODE_X1 = 0,
+ ADDXI_IMM8_OPCODE_X0 = 2,
+ ADDXI_IMM8_OPCODE_X1 = 2,
+ ADDXI_OPCODE_Y0 = 1,
+ ADDXI_OPCODE_Y1 = 2,
+ ADDXLI_OPCODE_X0 = 2,
+ ADDXLI_OPCODE_X1 = 1,
+ ADDXSC_RRR_0_OPCODE_X0 = 1,
+ ADDXSC_RRR_0_OPCODE_X1 = 1,
+ ADDX_RRR_0_OPCODE_X0 = 2,
+ ADDX_RRR_0_OPCODE_X1 = 2,
+ ADDX_RRR_0_OPCODE_Y0 = 0,
+ ADDX_SPECIAL_0_OPCODE_Y1 = 0,
+ ADD_RRR_0_OPCODE_X0 = 3,
+ ADD_RRR_0_OPCODE_X1 = 3,
+ ADD_RRR_0_OPCODE_Y0 = 1,
+ ADD_SPECIAL_0_OPCODE_Y1 = 1,
+ ANDI_IMM8_OPCODE_X0 = 3,
+ ANDI_IMM8_OPCODE_X1 = 3,
+ ANDI_OPCODE_Y0 = 2,
+ ANDI_OPCODE_Y1 = 3,
+ AND_RRR_0_OPCODE_X0 = 4,
+ AND_RRR_0_OPCODE_X1 = 4,
+ AND_RRR_5_OPCODE_Y0 = 0,
+ AND_RRR_5_OPCODE_Y1 = 0,
+ BEQZT_BRANCH_OPCODE_X1 = 16,
+ BEQZ_BRANCH_OPCODE_X1 = 17,
+ BFEXTS_BF_OPCODE_X0 = 4,
+ BFEXTU_BF_OPCODE_X0 = 5,
+ BFINS_BF_OPCODE_X0 = 6,
+ BF_OPCODE_X0 = 3,
+ BGEZT_BRANCH_OPCODE_X1 = 18,
+ BGEZ_BRANCH_OPCODE_X1 = 19,
+ BGTZT_BRANCH_OPCODE_X1 = 20,
+ BGTZ_BRANCH_OPCODE_X1 = 21,
+ BLBCT_BRANCH_OPCODE_X1 = 22,
+ BLBC_BRANCH_OPCODE_X1 = 23,
+ BLBST_BRANCH_OPCODE_X1 = 24,
+ BLBS_BRANCH_OPCODE_X1 = 25,
+ BLEZT_BRANCH_OPCODE_X1 = 26,
+ BLEZ_BRANCH_OPCODE_X1 = 27,
+ BLTZT_BRANCH_OPCODE_X1 = 28,
+ BLTZ_BRANCH_OPCODE_X1 = 29,
+ BNEZT_BRANCH_OPCODE_X1 = 30,
+ BNEZ_BRANCH_OPCODE_X1 = 31,
+ BRANCH_OPCODE_X1 = 2,
+ CMOVEQZ_RRR_0_OPCODE_X0 = 5,
+ CMOVEQZ_RRR_4_OPCODE_Y0 = 0,
+ CMOVNEZ_RRR_0_OPCODE_X0 = 6,
+ CMOVNEZ_RRR_4_OPCODE_Y0 = 1,
+ CMPEQI_IMM8_OPCODE_X0 = 4,
+ CMPEQI_IMM8_OPCODE_X1 = 4,
+ CMPEQI_OPCODE_Y0 = 3,
+ CMPEQI_OPCODE_Y1 = 4,
+ CMPEQ_RRR_0_OPCODE_X0 = 7,
+ CMPEQ_RRR_0_OPCODE_X1 = 5,
+ CMPEQ_RRR_3_OPCODE_Y0 = 0,
+ CMPEQ_RRR_3_OPCODE_Y1 = 2,
+ CMPEXCH4_RRR_0_OPCODE_X1 = 6,
+ CMPEXCH_RRR_0_OPCODE_X1 = 7,
+ CMPLES_RRR_0_OPCODE_X0 = 8,
+ CMPLES_RRR_0_OPCODE_X1 = 8,
+ CMPLES_RRR_2_OPCODE_Y0 = 0,
+ CMPLES_RRR_2_OPCODE_Y1 = 0,
+ CMPLEU_RRR_0_OPCODE_X0 = 9,
+ CMPLEU_RRR_0_OPCODE_X1 = 9,
+ CMPLEU_RRR_2_OPCODE_Y0 = 1,
+ CMPLEU_RRR_2_OPCODE_Y1 = 1,
+ CMPLTSI_IMM8_OPCODE_X0 = 5,
+ CMPLTSI_IMM8_OPCODE_X1 = 5,
+ CMPLTSI_OPCODE_Y0 = 4,
+ CMPLTSI_OPCODE_Y1 = 5,
+ CMPLTS_RRR_0_OPCODE_X0 = 10,
+ CMPLTS_RRR_0_OPCODE_X1 = 10,
+ CMPLTS_RRR_2_OPCODE_Y0 = 2,
+ CMPLTS_RRR_2_OPCODE_Y1 = 2,
+ CMPLTUI_IMM8_OPCODE_X0 = 6,
+ CMPLTUI_IMM8_OPCODE_X1 = 6,
+ CMPLTU_RRR_0_OPCODE_X0 = 11,
+ CMPLTU_RRR_0_OPCODE_X1 = 11,
+ CMPLTU_RRR_2_OPCODE_Y0 = 3,
+ CMPLTU_RRR_2_OPCODE_Y1 = 3,
+ CMPNE_RRR_0_OPCODE_X0 = 12,
+ CMPNE_RRR_0_OPCODE_X1 = 12,
+ CMPNE_RRR_3_OPCODE_Y0 = 1,
+ CMPNE_RRR_3_OPCODE_Y1 = 3,
+ CMULAF_RRR_0_OPCODE_X0 = 13,
+ CMULA_RRR_0_OPCODE_X0 = 14,
+ CMULFR_RRR_0_OPCODE_X0 = 15,
+ CMULF_RRR_0_OPCODE_X0 = 16,
+ CMULHR_RRR_0_OPCODE_X0 = 17,
+ CMULH_RRR_0_OPCODE_X0 = 18,
+ CMUL_RRR_0_OPCODE_X0 = 19,
+ CNTLZ_UNARY_OPCODE_X0 = 1,
+ CNTLZ_UNARY_OPCODE_Y0 = 1,
+ CNTTZ_UNARY_OPCODE_X0 = 2,
+ CNTTZ_UNARY_OPCODE_Y0 = 2,
+ CRC32_32_RRR_0_OPCODE_X0 = 20,
+ CRC32_8_RRR_0_OPCODE_X0 = 21,
+ DBLALIGN2_RRR_0_OPCODE_X0 = 22,
+ DBLALIGN2_RRR_0_OPCODE_X1 = 13,
+ DBLALIGN4_RRR_0_OPCODE_X0 = 23,
+ DBLALIGN4_RRR_0_OPCODE_X1 = 14,
+ DBLALIGN6_RRR_0_OPCODE_X0 = 24,
+ DBLALIGN6_RRR_0_OPCODE_X1 = 15,
+ DBLALIGN_RRR_0_OPCODE_X0 = 25,
+ DRAIN_UNARY_OPCODE_X1 = 1,
+ DTLBPR_UNARY_OPCODE_X1 = 2,
+ EXCH4_RRR_0_OPCODE_X1 = 16,
+ EXCH_RRR_0_OPCODE_X1 = 17,
+ FDOUBLE_ADDSUB_RRR_0_OPCODE_X0 = 26,
+ FDOUBLE_ADD_FLAGS_RRR_0_OPCODE_X0 = 27,
+ FDOUBLE_MUL_FLAGS_RRR_0_OPCODE_X0 = 28,
+ FDOUBLE_PACK1_RRR_0_OPCODE_X0 = 29,
+ FDOUBLE_PACK2_RRR_0_OPCODE_X0 = 30,
+ FDOUBLE_SUB_FLAGS_RRR_0_OPCODE_X0 = 31,
+ FDOUBLE_UNPACK_MAX_RRR_0_OPCODE_X0 = 32,
+ FDOUBLE_UNPACK_MIN_RRR_0_OPCODE_X0 = 33,
+ FETCHADD4_RRR_0_OPCODE_X1 = 18,
+ FETCHADDGEZ4_RRR_0_OPCODE_X1 = 19,
+ FETCHADDGEZ_RRR_0_OPCODE_X1 = 20,
+ FETCHADD_RRR_0_OPCODE_X1 = 21,
+ FETCHAND4_RRR_0_OPCODE_X1 = 22,
+ FETCHAND_RRR_0_OPCODE_X1 = 23,
+ FETCHOR4_RRR_0_OPCODE_X1 = 24,
+ FETCHOR_RRR_0_OPCODE_X1 = 25,
+ FINV_UNARY_OPCODE_X1 = 3,
+ FLUSHWB_UNARY_OPCODE_X1 = 4,
+ FLUSH_UNARY_OPCODE_X1 = 5,
+ FNOP_UNARY_OPCODE_X0 = 3,
+ FNOP_UNARY_OPCODE_X1 = 6,
+ FNOP_UNARY_OPCODE_Y0 = 3,
+ FNOP_UNARY_OPCODE_Y1 = 8,
+ FSINGLE_ADD1_RRR_0_OPCODE_X0 = 34,
+ FSINGLE_ADDSUB2_RRR_0_OPCODE_X0 = 35,
+ FSINGLE_MUL1_RRR_0_OPCODE_X0 = 36,
+ FSINGLE_MUL2_RRR_0_OPCODE_X0 = 37,
+ FSINGLE_PACK1_UNARY_OPCODE_X0 = 4,
+ FSINGLE_PACK1_UNARY_OPCODE_Y0 = 4,
+ FSINGLE_PACK2_RRR_0_OPCODE_X0 = 38,
+ FSINGLE_SUB1_RRR_0_OPCODE_X0 = 39,
+ ICOH_UNARY_OPCODE_X1 = 7,
+ ILL_UNARY_OPCODE_X1 = 8,
+ ILL_UNARY_OPCODE_Y1 = 9,
+ IMM8_OPCODE_X0 = 4,
+ IMM8_OPCODE_X1 = 3,
+ INV_UNARY_OPCODE_X1 = 9,
+ IRET_UNARY_OPCODE_X1 = 10,
+ JALRP_UNARY_OPCODE_X1 = 11,
+ JALRP_UNARY_OPCODE_Y1 = 10,
+ JALR_UNARY_OPCODE_X1 = 12,
+ JALR_UNARY_OPCODE_Y1 = 11,
+ JAL_JUMP_OPCODE_X1 = 0,
+ JRP_UNARY_OPCODE_X1 = 13,
+ JRP_UNARY_OPCODE_Y1 = 12,
+ JR_UNARY_OPCODE_X1 = 14,
+ JR_UNARY_OPCODE_Y1 = 13,
+ JUMP_OPCODE_X1 = 4,
+ J_JUMP_OPCODE_X1 = 1,
+ LD1S_ADD_IMM8_OPCODE_X1 = 7,
+ LD1S_OPCODE_Y2 = 0,
+ LD1S_UNARY_OPCODE_X1 = 15,
+ LD1U_ADD_IMM8_OPCODE_X1 = 8,
+ LD1U_OPCODE_Y2 = 1,
+ LD1U_UNARY_OPCODE_X1 = 16,
+ LD2S_ADD_IMM8_OPCODE_X1 = 9,
+ LD2S_OPCODE_Y2 = 2,
+ LD2S_UNARY_OPCODE_X1 = 17,
+ LD2U_ADD_IMM8_OPCODE_X1 = 10,
+ LD2U_OPCODE_Y2 = 3,
+ LD2U_UNARY_OPCODE_X1 = 18,
+ LD4S_ADD_IMM8_OPCODE_X1 = 11,
+ LD4S_OPCODE_Y2 = 1,
+ LD4S_UNARY_OPCODE_X1 = 19,
+ LD4U_ADD_IMM8_OPCODE_X1 = 12,
+ LD4U_OPCODE_Y2 = 2,
+ LD4U_UNARY_OPCODE_X1 = 20,
+ LDNA_UNARY_OPCODE_X1 = 21,
+ LDNT1S_ADD_IMM8_OPCODE_X1 = 13,
+ LDNT1S_UNARY_OPCODE_X1 = 22,
+ LDNT1U_ADD_IMM8_OPCODE_X1 = 14,
+ LDNT1U_UNARY_OPCODE_X1 = 23,
+ LDNT2S_ADD_IMM8_OPCODE_X1 = 15,
+ LDNT2S_UNARY_OPCODE_X1 = 24,
+ LDNT2U_ADD_IMM8_OPCODE_X1 = 16,
+ LDNT2U_UNARY_OPCODE_X1 = 25,
+ LDNT4S_ADD_IMM8_OPCODE_X1 = 17,
+ LDNT4S_UNARY_OPCODE_X1 = 26,
+ LDNT4U_ADD_IMM8_OPCODE_X1 = 18,
+ LDNT4U_UNARY_OPCODE_X1 = 27,
+ LDNT_ADD_IMM8_OPCODE_X1 = 19,
+ LDNT_UNARY_OPCODE_X1 = 28,
+ LD_ADD_IMM8_OPCODE_X1 = 20,
+ LD_OPCODE_Y2 = 3,
+ LD_UNARY_OPCODE_X1 = 29,
+ LNK_UNARY_OPCODE_X1 = 30,
+ LNK_UNARY_OPCODE_Y1 = 14,
+ LWNA_ADD_IMM8_OPCODE_X1 = 21,
+ MFSPR_IMM8_OPCODE_X1 = 22,
+ MF_UNARY_OPCODE_X1 = 31,
+ MM_BF_OPCODE_X0 = 7,
+ MNZ_RRR_0_OPCODE_X0 = 40,
+ MNZ_RRR_0_OPCODE_X1 = 26,
+ MNZ_RRR_4_OPCODE_Y0 = 2,
+ MNZ_RRR_4_OPCODE_Y1 = 2,
+ MODE_OPCODE_YA2 = 1,
+ MODE_OPCODE_YB2 = 2,
+ MODE_OPCODE_YC2 = 3,
+ MTSPR_IMM8_OPCODE_X1 = 23,
+ MULAX_RRR_0_OPCODE_X0 = 41,
+ MULAX_RRR_3_OPCODE_Y0 = 2,
+ MULA_HS_HS_RRR_0_OPCODE_X0 = 42,
+ MULA_HS_HS_RRR_9_OPCODE_Y0 = 0,
+ MULA_HS_HU_RRR_0_OPCODE_X0 = 43,
+ MULA_HS_LS_RRR_0_OPCODE_X0 = 44,
+ MULA_HS_LU_RRR_0_OPCODE_X0 = 45,
+ MULA_HU_HU_RRR_0_OPCODE_X0 = 46,
+ MULA_HU_HU_RRR_9_OPCODE_Y0 = 1,
+ MULA_HU_LS_RRR_0_OPCODE_X0 = 47,
+ MULA_HU_LU_RRR_0_OPCODE_X0 = 48,
+ MULA_LS_LS_RRR_0_OPCODE_X0 = 49,
+ MULA_LS_LS_RRR_9_OPCODE_Y0 = 2,
+ MULA_LS_LU_RRR_0_OPCODE_X0 = 50,
+ MULA_LU_LU_RRR_0_OPCODE_X0 = 51,
+ MULA_LU_LU_RRR_9_OPCODE_Y0 = 3,
+ MULX_RRR_0_OPCODE_X0 = 52,
+ MULX_RRR_3_OPCODE_Y0 = 3,
+ MUL_HS_HS_RRR_0_OPCODE_X0 = 53,
+ MUL_HS_HS_RRR_8_OPCODE_Y0 = 0,
+ MUL_HS_HU_RRR_0_OPCODE_X0 = 54,
+ MUL_HS_LS_RRR_0_OPCODE_X0 = 55,
+ MUL_HS_LU_RRR_0_OPCODE_X0 = 56,
+ MUL_HU_HU_RRR_0_OPCODE_X0 = 57,
+ MUL_HU_HU_RRR_8_OPCODE_Y0 = 1,
+ MUL_HU_LS_RRR_0_OPCODE_X0 = 58,
+ MUL_HU_LU_RRR_0_OPCODE_X0 = 59,
+ MUL_LS_LS_RRR_0_OPCODE_X0 = 60,
+ MUL_LS_LS_RRR_8_OPCODE_Y0 = 2,
+ MUL_LS_LU_RRR_0_OPCODE_X0 = 61,
+ MUL_LU_LU_RRR_0_OPCODE_X0 = 62,
+ MUL_LU_LU_RRR_8_OPCODE_Y0 = 3,
+ MZ_RRR_0_OPCODE_X0 = 63,
+ MZ_RRR_0_OPCODE_X1 = 27,
+ MZ_RRR_4_OPCODE_Y0 = 3,
+ MZ_RRR_4_OPCODE_Y1 = 3,
+ NAP_UNARY_OPCODE_X1 = 32,
+ NOP_UNARY_OPCODE_X0 = 5,
+ NOP_UNARY_OPCODE_X1 = 33,
+ NOP_UNARY_OPCODE_Y0 = 5,
+ NOP_UNARY_OPCODE_Y1 = 15,
+ NOR_RRR_0_OPCODE_X0 = 64,
+ NOR_RRR_0_OPCODE_X1 = 28,
+ NOR_RRR_5_OPCODE_Y0 = 1,
+ NOR_RRR_5_OPCODE_Y1 = 1,
+ ORI_IMM8_OPCODE_X0 = 7,
+ ORI_IMM8_OPCODE_X1 = 24,
+ OR_RRR_0_OPCODE_X0 = 65,
+ OR_RRR_0_OPCODE_X1 = 29,
+ OR_RRR_5_OPCODE_Y0 = 2,
+ OR_RRR_5_OPCODE_Y1 = 2,
+ PCNT_UNARY_OPCODE_X0 = 6,
+ PCNT_UNARY_OPCODE_Y0 = 6,
+ REVBITS_UNARY_OPCODE_X0 = 7,
+ REVBITS_UNARY_OPCODE_Y0 = 7,
+ REVBYTES_UNARY_OPCODE_X0 = 8,
+ REVBYTES_UNARY_OPCODE_Y0 = 8,
+ ROTLI_SHIFT_OPCODE_X0 = 1,
+ ROTLI_SHIFT_OPCODE_X1 = 1,
+ ROTLI_SHIFT_OPCODE_Y0 = 0,
+ ROTLI_SHIFT_OPCODE_Y1 = 0,
+ ROTL_RRR_0_OPCODE_X0 = 66,
+ ROTL_RRR_0_OPCODE_X1 = 30,
+ ROTL_RRR_6_OPCODE_Y0 = 0,
+ ROTL_RRR_6_OPCODE_Y1 = 0,
+ RRR_0_OPCODE_X0 = 5,
+ RRR_0_OPCODE_X1 = 5,
+ RRR_0_OPCODE_Y0 = 5,
+ RRR_0_OPCODE_Y1 = 6,
+ RRR_1_OPCODE_Y0 = 6,
+ RRR_1_OPCODE_Y1 = 7,
+ RRR_2_OPCODE_Y0 = 7,
+ RRR_2_OPCODE_Y1 = 8,
+ RRR_3_OPCODE_Y0 = 8,
+ RRR_3_OPCODE_Y1 = 9,
+ RRR_4_OPCODE_Y0 = 9,
+ RRR_4_OPCODE_Y1 = 10,
+ RRR_5_OPCODE_Y0 = 10,
+ RRR_5_OPCODE_Y1 = 11,
+ RRR_6_OPCODE_Y0 = 11,
+ RRR_6_OPCODE_Y1 = 12,
+ RRR_7_OPCODE_Y0 = 12,
+ RRR_7_OPCODE_Y1 = 13,
+ RRR_8_OPCODE_Y0 = 13,
+ RRR_9_OPCODE_Y0 = 14,
+ SHIFT_OPCODE_X0 = 6,
+ SHIFT_OPCODE_X1 = 6,
+ SHIFT_OPCODE_Y0 = 15,
+ SHIFT_OPCODE_Y1 = 14,
+ SHL16INSLI_OPCODE_X0 = 7,
+ SHL16INSLI_OPCODE_X1 = 7,
+ SHL1ADDX_RRR_0_OPCODE_X0 = 67,
+ SHL1ADDX_RRR_0_OPCODE_X1 = 31,
+ SHL1ADDX_RRR_7_OPCODE_Y0 = 1,
+ SHL1ADDX_RRR_7_OPCODE_Y1 = 1,
+ SHL1ADD_RRR_0_OPCODE_X0 = 68,
+ SHL1ADD_RRR_0_OPCODE_X1 = 32,
+ SHL1ADD_RRR_1_OPCODE_Y0 = 0,
+ SHL1ADD_RRR_1_OPCODE_Y1 = 0,
+ SHL2ADDX_RRR_0_OPCODE_X0 = 69,
+ SHL2ADDX_RRR_0_OPCODE_X1 = 33,
+ SHL2ADDX_RRR_7_OPCODE_Y0 = 2,
+ SHL2ADDX_RRR_7_OPCODE_Y1 = 2,
+ SHL2ADD_RRR_0_OPCODE_X0 = 70,
+ SHL2ADD_RRR_0_OPCODE_X1 = 34,
+ SHL2ADD_RRR_1_OPCODE_Y0 = 1,
+ SHL2ADD_RRR_1_OPCODE_Y1 = 1,
+ SHL3ADDX_RRR_0_OPCODE_X0 = 71,
+ SHL3ADDX_RRR_0_OPCODE_X1 = 35,
+ SHL3ADDX_RRR_7_OPCODE_Y0 = 3,
+ SHL3ADDX_RRR_7_OPCODE_Y1 = 3,
+ SHL3ADD_RRR_0_OPCODE_X0 = 72,
+ SHL3ADD_RRR_0_OPCODE_X1 = 36,
+ SHL3ADD_RRR_1_OPCODE_Y0 = 2,
+ SHL3ADD_RRR_1_OPCODE_Y1 = 2,
+ SHLI_SHIFT_OPCODE_X0 = 2,
+ SHLI_SHIFT_OPCODE_X1 = 2,
+ SHLI_SHIFT_OPCODE_Y0 = 1,
+ SHLI_SHIFT_OPCODE_Y1 = 1,
+ SHLXI_SHIFT_OPCODE_X0 = 3,
+ SHLXI_SHIFT_OPCODE_X1 = 3,
+ SHLX_RRR_0_OPCODE_X0 = 73,
+ SHLX_RRR_0_OPCODE_X1 = 37,
+ SHL_RRR_0_OPCODE_X0 = 74,
+ SHL_RRR_0_OPCODE_X1 = 38,
+ SHL_RRR_6_OPCODE_Y0 = 1,
+ SHL_RRR_6_OPCODE_Y1 = 1,
+ SHRSI_SHIFT_OPCODE_X0 = 4,
+ SHRSI_SHIFT_OPCODE_X1 = 4,
+ SHRSI_SHIFT_OPCODE_Y0 = 2,
+ SHRSI_SHIFT_OPCODE_Y1 = 2,
+ SHRS_RRR_0_OPCODE_X0 = 75,
+ SHRS_RRR_0_OPCODE_X1 = 39,
+ SHRS_RRR_6_OPCODE_Y0 = 2,
+ SHRS_RRR_6_OPCODE_Y1 = 2,
+ SHRUI_SHIFT_OPCODE_X0 = 5,
+ SHRUI_SHIFT_OPCODE_X1 = 5,
+ SHRUI_SHIFT_OPCODE_Y0 = 3,
+ SHRUI_SHIFT_OPCODE_Y1 = 3,
+ SHRUXI_SHIFT_OPCODE_X0 = 6,
+ SHRUXI_SHIFT_OPCODE_X1 = 6,
+ SHRUX_RRR_0_OPCODE_X0 = 76,
+ SHRUX_RRR_0_OPCODE_X1 = 40,
+ SHRU_RRR_0_OPCODE_X0 = 77,
+ SHRU_RRR_0_OPCODE_X1 = 41,
+ SHRU_RRR_6_OPCODE_Y0 = 3,
+ SHRU_RRR_6_OPCODE_Y1 = 3,
+ SHUFFLEBYTES_RRR_0_OPCODE_X0 = 78,
+ ST1_ADD_IMM8_OPCODE_X1 = 25,
+ ST1_OPCODE_Y2 = 0,
+ ST1_RRR_0_OPCODE_X1 = 42,
+ ST2_ADD_IMM8_OPCODE_X1 = 26,
+ ST2_OPCODE_Y2 = 1,
+ ST2_RRR_0_OPCODE_X1 = 43,
+ ST4_ADD_IMM8_OPCODE_X1 = 27,
+ ST4_OPCODE_Y2 = 2,
+ ST4_RRR_0_OPCODE_X1 = 44,
+ STNT1_ADD_IMM8_OPCODE_X1 = 28,
+ STNT1_RRR_0_OPCODE_X1 = 45,
+ STNT2_ADD_IMM8_OPCODE_X1 = 29,
+ STNT2_RRR_0_OPCODE_X1 = 46,
+ STNT4_ADD_IMM8_OPCODE_X1 = 30,
+ STNT4_RRR_0_OPCODE_X1 = 47,
+ STNT_ADD_IMM8_OPCODE_X1 = 31,
+ STNT_RRR_0_OPCODE_X1 = 48,
+ ST_ADD_IMM8_OPCODE_X1 = 32,
+ ST_OPCODE_Y2 = 3,
+ ST_RRR_0_OPCODE_X1 = 49,
+ SUBXSC_RRR_0_OPCODE_X0 = 79,
+ SUBXSC_RRR_0_OPCODE_X1 = 50,
+ SUBX_RRR_0_OPCODE_X0 = 80,
+ SUBX_RRR_0_OPCODE_X1 = 51,
+ SUBX_RRR_0_OPCODE_Y0 = 2,
+ SUBX_RRR_0_OPCODE_Y1 = 2,
+ SUB_RRR_0_OPCODE_X0 = 81,
+ SUB_RRR_0_OPCODE_X1 = 52,
+ SUB_RRR_0_OPCODE_Y0 = 3,
+ SUB_RRR_0_OPCODE_Y1 = 3,
+ SWINT0_UNARY_OPCODE_X1 = 34,
+ SWINT1_UNARY_OPCODE_X1 = 35,
+ SWINT2_UNARY_OPCODE_X1 = 36,
+ SWINT3_UNARY_OPCODE_X1 = 37,
+ TBLIDXB0_UNARY_OPCODE_X0 = 9,
+ TBLIDXB0_UNARY_OPCODE_Y0 = 9,
+ TBLIDXB1_UNARY_OPCODE_X0 = 10,
+ TBLIDXB1_UNARY_OPCODE_Y0 = 10,
+ TBLIDXB2_UNARY_OPCODE_X0 = 11,
+ TBLIDXB2_UNARY_OPCODE_Y0 = 11,
+ TBLIDXB3_UNARY_OPCODE_X0 = 12,
+ TBLIDXB3_UNARY_OPCODE_Y0 = 12,
+ UNARY_RRR_0_OPCODE_X0 = 82,
+ UNARY_RRR_0_OPCODE_X1 = 53,
+ UNARY_RRR_1_OPCODE_Y0 = 3,
+ UNARY_RRR_1_OPCODE_Y1 = 3,
+ V1ADDI_IMM8_OPCODE_X0 = 8,
+ V1ADDI_IMM8_OPCODE_X1 = 33,
+ V1ADDUC_RRR_0_OPCODE_X0 = 83,
+ V1ADDUC_RRR_0_OPCODE_X1 = 54,
+ V1ADD_RRR_0_OPCODE_X0 = 84,
+ V1ADD_RRR_0_OPCODE_X1 = 55,
+ V1ADIFFU_RRR_0_OPCODE_X0 = 85,
+ V1AVGU_RRR_0_OPCODE_X0 = 86,
+ V1CMPEQI_IMM8_OPCODE_X0 = 9,
+ V1CMPEQI_IMM8_OPCODE_X1 = 34,
+ V1CMPEQ_RRR_0_OPCODE_X0 = 87,
+ V1CMPEQ_RRR_0_OPCODE_X1 = 56,
+ V1CMPLES_RRR_0_OPCODE_X0 = 88,
+ V1CMPLES_RRR_0_OPCODE_X1 = 57,
+ V1CMPLEU_RRR_0_OPCODE_X0 = 89,
+ V1CMPLEU_RRR_0_OPCODE_X1 = 58,
+ V1CMPLTSI_IMM8_OPCODE_X0 = 10,
+ V1CMPLTSI_IMM8_OPCODE_X1 = 35,
+ V1CMPLTS_RRR_0_OPCODE_X0 = 90,
+ V1CMPLTS_RRR_0_OPCODE_X1 = 59,
+ V1CMPLTUI_IMM8_OPCODE_X0 = 11,
+ V1CMPLTUI_IMM8_OPCODE_X1 = 36,
+ V1CMPLTU_RRR_0_OPCODE_X0 = 91,
+ V1CMPLTU_RRR_0_OPCODE_X1 = 60,
+ V1CMPNE_RRR_0_OPCODE_X0 = 92,
+ V1CMPNE_RRR_0_OPCODE_X1 = 61,
+ V1DDOTPUA_RRR_0_OPCODE_X0 = 161,
+ V1DDOTPUSA_RRR_0_OPCODE_X0 = 93,
+ V1DDOTPUS_RRR_0_OPCODE_X0 = 94,
+ V1DDOTPU_RRR_0_OPCODE_X0 = 162,
+ V1DOTPA_RRR_0_OPCODE_X0 = 95,
+ V1DOTPUA_RRR_0_OPCODE_X0 = 163,
+ V1DOTPUSA_RRR_0_OPCODE_X0 = 96,
+ V1DOTPUS_RRR_0_OPCODE_X0 = 97,
+ V1DOTPU_RRR_0_OPCODE_X0 = 164,
+ V1DOTP_RRR_0_OPCODE_X0 = 98,
+ V1INT_H_RRR_0_OPCODE_X0 = 99,
+ V1INT_H_RRR_0_OPCODE_X1 = 62,
+ V1INT_L_RRR_0_OPCODE_X0 = 100,
+ V1INT_L_RRR_0_OPCODE_X1 = 63,
+ V1MAXUI_IMM8_OPCODE_X0 = 12,
+ V1MAXUI_IMM8_OPCODE_X1 = 37,
+ V1MAXU_RRR_0_OPCODE_X0 = 101,
+ V1MAXU_RRR_0_OPCODE_X1 = 64,
+ V1MINUI_IMM8_OPCODE_X0 = 13,
+ V1MINUI_IMM8_OPCODE_X1 = 38,
+ V1MINU_RRR_0_OPCODE_X0 = 102,
+ V1MINU_RRR_0_OPCODE_X1 = 65,
+ V1MNZ_RRR_0_OPCODE_X0 = 103,
+ V1MNZ_RRR_0_OPCODE_X1 = 66,
+ V1MULTU_RRR_0_OPCODE_X0 = 104,
+ V1MULUS_RRR_0_OPCODE_X0 = 105,
+ V1MULU_RRR_0_OPCODE_X0 = 106,
+ V1MZ_RRR_0_OPCODE_X0 = 107,
+ V1MZ_RRR_0_OPCODE_X1 = 67,
+ V1SADAU_RRR_0_OPCODE_X0 = 108,
+ V1SADU_RRR_0_OPCODE_X0 = 109,
+ V1SHLI_SHIFT_OPCODE_X0 = 7,
+ V1SHLI_SHIFT_OPCODE_X1 = 7,
+ V1SHL_RRR_0_OPCODE_X0 = 110,
+ V1SHL_RRR_0_OPCODE_X1 = 68,
+ V1SHRSI_SHIFT_OPCODE_X0 = 8,
+ V1SHRSI_SHIFT_OPCODE_X1 = 8,
+ V1SHRS_RRR_0_OPCODE_X0 = 111,
+ V1SHRS_RRR_0_OPCODE_X1 = 69,
+ V1SHRUI_SHIFT_OPCODE_X0 = 9,
+ V1SHRUI_SHIFT_OPCODE_X1 = 9,
+ V1SHRU_RRR_0_OPCODE_X0 = 112,
+ V1SHRU_RRR_0_OPCODE_X1 = 70,
+ V1SUBUC_RRR_0_OPCODE_X0 = 113,
+ V1SUBUC_RRR_0_OPCODE_X1 = 71,
+ V1SUB_RRR_0_OPCODE_X0 = 114,
+ V1SUB_RRR_0_OPCODE_X1 = 72,
+ V2ADDI_IMM8_OPCODE_X0 = 14,
+ V2ADDI_IMM8_OPCODE_X1 = 39,
+ V2ADDSC_RRR_0_OPCODE_X0 = 115,
+ V2ADDSC_RRR_0_OPCODE_X1 = 73,
+ V2ADD_RRR_0_OPCODE_X0 = 116,
+ V2ADD_RRR_0_OPCODE_X1 = 74,
+ V2ADIFFS_RRR_0_OPCODE_X0 = 117,
+ V2AVGS_RRR_0_OPCODE_X0 = 118,
+ V2CMPEQI_IMM8_OPCODE_X0 = 15,
+ V2CMPEQI_IMM8_OPCODE_X1 = 40,
+ V2CMPEQ_RRR_0_OPCODE_X0 = 119,
+ V2CMPEQ_RRR_0_OPCODE_X1 = 75,
+ V2CMPLES_RRR_0_OPCODE_X0 = 120,
+ V2CMPLES_RRR_0_OPCODE_X1 = 76,
+ V2CMPLEU_RRR_0_OPCODE_X0 = 121,
+ V2CMPLEU_RRR_0_OPCODE_X1 = 77,
+ V2CMPLTSI_IMM8_OPCODE_X0 = 16,
+ V2CMPLTSI_IMM8_OPCODE_X1 = 41,
+ V2CMPLTS_RRR_0_OPCODE_X0 = 122,
+ V2CMPLTS_RRR_0_OPCODE_X1 = 78,
+ V2CMPLTUI_IMM8_OPCODE_X0 = 17,
+ V2CMPLTUI_IMM8_OPCODE_X1 = 42,
+ V2CMPLTU_RRR_0_OPCODE_X0 = 123,
+ V2CMPLTU_RRR_0_OPCODE_X1 = 79,
+ V2CMPNE_RRR_0_OPCODE_X0 = 124,
+ V2CMPNE_RRR_0_OPCODE_X1 = 80,
+ V2DOTPA_RRR_0_OPCODE_X0 = 125,
+ V2DOTP_RRR_0_OPCODE_X0 = 126,
+ V2INT_H_RRR_0_OPCODE_X0 = 127,
+ V2INT_H_RRR_0_OPCODE_X1 = 81,
+ V2INT_L_RRR_0_OPCODE_X0 = 128,
+ V2INT_L_RRR_0_OPCODE_X1 = 82,
+ V2MAXSI_IMM8_OPCODE_X0 = 18,
+ V2MAXSI_IMM8_OPCODE_X1 = 43,
+ V2MAXS_RRR_0_OPCODE_X0 = 129,
+ V2MAXS_RRR_0_OPCODE_X1 = 83,
+ V2MINSI_IMM8_OPCODE_X0 = 19,
+ V2MINSI_IMM8_OPCODE_X1 = 44,
+ V2MINS_RRR_0_OPCODE_X0 = 130,
+ V2MINS_RRR_0_OPCODE_X1 = 84,
+ V2MNZ_RRR_0_OPCODE_X0 = 131,
+ V2MNZ_RRR_0_OPCODE_X1 = 85,
+ V2MULFSC_RRR_0_OPCODE_X0 = 132,
+ V2MULS_RRR_0_OPCODE_X0 = 133,
+ V2MULTS_RRR_0_OPCODE_X0 = 134,
+ V2MZ_RRR_0_OPCODE_X0 = 135,
+ V2MZ_RRR_0_OPCODE_X1 = 86,
+ V2PACKH_RRR_0_OPCODE_X0 = 136,
+ V2PACKH_RRR_0_OPCODE_X1 = 87,
+ V2PACKL_RRR_0_OPCODE_X0 = 137,
+ V2PACKL_RRR_0_OPCODE_X1 = 88,
+ V2PACKUC_RRR_0_OPCODE_X0 = 138,
+ V2PACKUC_RRR_0_OPCODE_X1 = 89,
+ V2SADAS_RRR_0_OPCODE_X0 = 139,
+ V2SADAU_RRR_0_OPCODE_X0 = 140,
+ V2SADS_RRR_0_OPCODE_X0 = 141,
+ V2SADU_RRR_0_OPCODE_X0 = 142,
+ V2SHLI_SHIFT_OPCODE_X0 = 10,
+ V2SHLI_SHIFT_OPCODE_X1 = 10,
+ V2SHLSC_RRR_0_OPCODE_X0 = 143,
+ V2SHLSC_RRR_0_OPCODE_X1 = 90,
+ V2SHL_RRR_0_OPCODE_X0 = 144,
+ V2SHL_RRR_0_OPCODE_X1 = 91,
+ V2SHRSI_SHIFT_OPCODE_X0 = 11,
+ V2SHRSI_SHIFT_OPCODE_X1 = 11,
+ V2SHRS_RRR_0_OPCODE_X0 = 145,
+ V2SHRS_RRR_0_OPCODE_X1 = 92,
+ V2SHRUI_SHIFT_OPCODE_X0 = 12,
+ V2SHRUI_SHIFT_OPCODE_X1 = 12,
+ V2SHRU_RRR_0_OPCODE_X0 = 146,
+ V2SHRU_RRR_0_OPCODE_X1 = 93,
+ V2SUBSC_RRR_0_OPCODE_X0 = 147,
+ V2SUBSC_RRR_0_OPCODE_X1 = 94,
+ V2SUB_RRR_0_OPCODE_X0 = 148,
+ V2SUB_RRR_0_OPCODE_X1 = 95,
+ V4ADDSC_RRR_0_OPCODE_X0 = 149,
+ V4ADDSC_RRR_0_OPCODE_X1 = 96,
+ V4ADD_RRR_0_OPCODE_X0 = 150,
+ V4ADD_RRR_0_OPCODE_X1 = 97,
+ V4INT_H_RRR_0_OPCODE_X0 = 151,
+ V4INT_H_RRR_0_OPCODE_X1 = 98,
+ V4INT_L_RRR_0_OPCODE_X0 = 152,
+ V4INT_L_RRR_0_OPCODE_X1 = 99,
+ V4PACKSC_RRR_0_OPCODE_X0 = 153,
+ V4PACKSC_RRR_0_OPCODE_X1 = 100,
+ V4SHLSC_RRR_0_OPCODE_X0 = 154,
+ V4SHLSC_RRR_0_OPCODE_X1 = 101,
+ V4SHL_RRR_0_OPCODE_X0 = 155,
+ V4SHL_RRR_0_OPCODE_X1 = 102,
+ V4SHRS_RRR_0_OPCODE_X0 = 156,
+ V4SHRS_RRR_0_OPCODE_X1 = 103,
+ V4SHRU_RRR_0_OPCODE_X0 = 157,
+ V4SHRU_RRR_0_OPCODE_X1 = 104,
+ V4SUBSC_RRR_0_OPCODE_X0 = 158,
+ V4SUBSC_RRR_0_OPCODE_X1 = 105,
+ V4SUB_RRR_0_OPCODE_X0 = 159,
+ V4SUB_RRR_0_OPCODE_X1 = 106,
+ WH64_UNARY_OPCODE_X1 = 38,
+ XORI_IMM8_OPCODE_X0 = 20,
+ XORI_IMM8_OPCODE_X1 = 45,
+ XOR_RRR_0_OPCODE_X0 = 160,
+ XOR_RRR_0_OPCODE_X1 = 107,
+ XOR_RRR_5_OPCODE_Y0 = 3,
+ XOR_RRR_5_OPCODE_Y1 = 3
};
#endif /* !_TILE_OPCODE_CONSTANTS_H */
diff --git a/arch/tile/include/asm/page.h b/arch/tile/include/asm/page.h
index 3eb5352..db93518 100644
--- a/arch/tile/include/asm/page.h
+++ b/arch/tile/include/asm/page.h
@@ -16,7 +16,8 @@
#define _ASM_TILE_PAGE_H
#include <linux/const.h>
-#include <hv/pagesize.h>
+#include <hv/hypervisor.h>
+#include <arch/chip.h>
/* PAGE_SHIFT and HPAGE_SHIFT determine the page sizes. */
#define PAGE_SHIFT HV_LOG2_PAGE_SIZE_SMALL
@@ -28,8 +29,6 @@
#define PAGE_MASK (~(PAGE_SIZE - 1))
#define HPAGE_MASK (~(HPAGE_SIZE - 1))
-#ifdef __KERNEL__
-
/*
* If the Kconfig doesn't specify, set a maximum zone order that
* is enough so that we can create huge pages from small pages given
@@ -39,9 +38,6 @@
#define CONFIG_FORCE_MAX_ZONEORDER (HPAGE_SHIFT - PAGE_SHIFT + 1)
#endif
-#include <hv/hypervisor.h>
-#include <arch/chip.h>
-
#ifndef __ASSEMBLY__
#include <linux/types.h>
@@ -91,6 +87,10 @@
/* Must be a macro since it is used to create constants. */
#define __pgprot(val) hv_pte(val)
+/* Rarely-used initializers, typically with a "zero" value. */
+#define __pte(x) hv_pte(x)
+#define __pgd(x) hv_pte(x)
+
static inline u64 pgprot_val(pgprot_t pgprot)
{
return hv_pte_val(pgprot);
@@ -110,6 +110,8 @@
typedef HV_PTE pmd_t;
+#define __pmd(x) hv_pte(x)
+
static inline u64 pmd_val(pmd_t pmd)
{
return hv_pte_val(pmd);
@@ -318,7 +320,7 @@
/* Provide as macros since these require some other headers included. */
#define page_to_pa(page) ((phys_addr_t)(page_to_pfn(page)) << PAGE_SHIFT)
-#define virt_to_page(kaddr) pfn_to_page(kaddr_to_pfn(kaddr))
+#define virt_to_page(kaddr) pfn_to_page(kaddr_to_pfn((void *)(kaddr)))
#define page_to_virt(page) pfn_to_kaddr(page_to_pfn(page))
struct mm_struct;
@@ -331,6 +333,4 @@
#include <asm-generic/memory_model.h>
-#endif /* __KERNEL__ */
-
#endif /* _ASM_TILE_PAGE_H */
diff --git a/arch/tile/include/asm/parport.h b/arch/tile/include/asm/parport.h
new file mode 100644
index 0000000..cf252af
--- /dev/null
+++ b/arch/tile/include/asm/parport.h
@@ -0,0 +1 @@
+#include <asm-generic/parport.h>
diff --git a/arch/tile/include/asm/pci.h b/arch/tile/include/asm/pci.h
index c3fc458..7f03cef 100644
--- a/arch/tile/include/asm/pci.h
+++ b/arch/tile/include/asm/pci.h
@@ -46,7 +46,8 @@
*/
#define PCI_DMA_BUS_IS_PHYS 1
-int __init tile_pci_init(void);
+int __devinit tile_pci_init(void);
+int __devinit pcibios_init(void);
void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long max);
static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr) {}
diff --git a/arch/tile/include/asm/pgtable_64.h b/arch/tile/include/asm/pgtable_64.h
new file mode 100644
index 0000000..fd80328
--- /dev/null
+++ b/arch/tile/include/asm/pgtable_64.h
@@ -0,0 +1,175 @@
+/*
+ * Copyright 2011 Tilera Corporation. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ * NON INFRINGEMENT. See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#ifndef _ASM_TILE_PGTABLE_64_H
+#define _ASM_TILE_PGTABLE_64_H
+
+/* The level-0 page table breaks the address space into 32-bit chunks. */
+#define PGDIR_SHIFT HV_LOG2_L1_SPAN
+#define PGDIR_SIZE HV_L1_SPAN
+#define PGDIR_MASK (~(PGDIR_SIZE-1))
+#define PTRS_PER_PGD HV_L0_ENTRIES
+#define SIZEOF_PGD (PTRS_PER_PGD * sizeof(pgd_t))
+
+/*
+ * The level-1 index is defined by the huge page size. A PMD is composed
+ * of PTRS_PER_PMD pgd_t's and is the middle level of the page table.
+ */
+#define PMD_SHIFT HV_LOG2_PAGE_SIZE_LARGE
+#define PMD_SIZE HV_PAGE_SIZE_LARGE
+#define PMD_MASK (~(PMD_SIZE-1))
+#define PTRS_PER_PMD (1 << (PGDIR_SHIFT - PMD_SHIFT))
+#define SIZEOF_PMD (PTRS_PER_PMD * sizeof(pmd_t))
+
+/*
+ * The level-2 index is defined by the difference between the huge
+ * page size and the normal page size. A PTE is composed of
+ * PTRS_PER_PTE pte_t's and is the bottom level of the page table.
+ * Note that the hypervisor docs use PTE for what we call pte_t, so
+ * this nomenclature is somewhat confusing.
+ */
+#define PTRS_PER_PTE (1 << (HV_LOG2_PAGE_SIZE_LARGE - HV_LOG2_PAGE_SIZE_SMALL))
+#define SIZEOF_PTE (PTRS_PER_PTE * sizeof(pte_t))
+
+/*
+ * Align the vmalloc area to an L2 page table, and leave a guard page
+ * at the beginning and end. The vmalloc code also puts in an internal
+ * guard page between each allocation.
+ */
+#define _VMALLOC_END HUGE_VMAP_BASE
+#define VMALLOC_END (_VMALLOC_END - PAGE_SIZE)
+#define VMALLOC_START (_VMALLOC_START + PAGE_SIZE)
+
+#define HUGE_VMAP_END (HUGE_VMAP_BASE + PGDIR_SIZE)
+
+#ifndef __ASSEMBLY__
+
+/* We have no pud since we are a three-level page table. */
+#include <asm-generic/pgtable-nopud.h>
+
+static inline int pud_none(pud_t pud)
+{
+ return pud_val(pud) == 0;
+}
+
+static inline int pud_present(pud_t pud)
+{
+ return pud_val(pud) & _PAGE_PRESENT;
+}
+
+#define pmd_ERROR(e) \
+ pr_err("%s:%d: bad pmd 0x%016llx.\n", __FILE__, __LINE__, pmd_val(e))
+
+static inline void pud_clear(pud_t *pudp)
+{
+ __pte_clear(&pudp->pgd);
+}
+
+static inline int pud_bad(pud_t pud)
+{
+ return ((pud_val(pud) & _PAGE_ALL) != _PAGE_TABLE);
+}
+
+/* Return the page-table frame number (ptfn) that a pud_t points at. */
+#define pud_ptfn(pud) hv_pte_get_ptfn((pud).pgd)
+
+/*
+ * A given kernel pud_t maps to a kernel pmd_t table at a specific
+ * virtual address. Since kernel pmd_t tables can be aligned at
+ * sub-page granularity, this macro can return non-page-aligned
+ * pointers, despite its name.
+ */
+#define pud_page_vaddr(pud) \
+ (__va((phys_addr_t)pud_ptfn(pud) << HV_LOG2_PAGE_TABLE_ALIGN))
+
+/*
+ * A pud_t points to a pmd_t array. Since we can have multiple per
+ * page, we don't have a one-to-one mapping of pud_t's to pages.
+ */
+#define pud_page(pud) pfn_to_page(HV_PTFN_TO_PFN(pud_ptfn(pud)))
+
+static inline unsigned long pud_index(unsigned long address)
+{
+ return (address >> PUD_SHIFT) & (PTRS_PER_PUD - 1);
+}
+
+#define pmd_offset(pud, address) \
+ ((pmd_t *)pud_page_vaddr(*(pud)) + pmd_index(address))
+
+static inline void __set_pmd(pmd_t *pmdp, pmd_t pmdval)
+{
+ set_pte(pmdp, pmdval);
+}
+
+/* Create a pmd from a PTFN and pgprot. */
+static inline pmd_t ptfn_pmd(unsigned long ptfn, pgprot_t prot)
+{
+ return hv_pte_set_ptfn(prot, ptfn);
+}
+
+/* Return the page-table frame number (ptfn) that a pmd_t points at. */
+static inline unsigned long pmd_ptfn(pmd_t pmd)
+{
+ return hv_pte_get_ptfn(pmd);
+}
+
+static inline void pmd_clear(pmd_t *pmdp)
+{
+ __pte_clear(pmdp);
+}
+
+/* Normalize an address to having the correct high bits set. */
+#define pgd_addr_normalize pgd_addr_normalize
+static inline unsigned long pgd_addr_normalize(unsigned long addr)
+{
+ return ((long)addr << (CHIP_WORD_SIZE() - CHIP_VA_WIDTH())) >>
+ (CHIP_WORD_SIZE() - CHIP_VA_WIDTH());
+}
+
+/* We don't define any pgds for these addresses. */
+static inline int pgd_addr_invalid(unsigned long addr)
+{
+ return addr >= MEM_HV_START ||
+ (addr > MEM_LOW_END && addr < MEM_HIGH_START);
+}
+
+/*
+ * Use atomic instructions to provide atomicity against the hypervisor.
+ */
+#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
+static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
+ unsigned long addr, pte_t *ptep)
+{
+ return (__insn_fetchand(&ptep->val, ~HV_PTE_ACCESSED) >>
+ HV_PTE_INDEX_ACCESSED) & 0x1;
+}
+
+#define __HAVE_ARCH_PTEP_SET_WRPROTECT
+static inline void ptep_set_wrprotect(struct mm_struct *mm,
+ unsigned long addr, pte_t *ptep)
+{
+ __insn_fetchand(&ptep->val, ~HV_PTE_WRITABLE);
+}
+
+#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
+static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
+ unsigned long addr, pte_t *ptep)
+{
+ return hv_pte(__insn_exch(&ptep->val, 0UL));
+}
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _ASM_TILE_PGTABLE_64_H */
diff --git a/arch/tile/include/asm/processor.h b/arch/tile/include/asm/processor.h
index e688947..34c1e01 100644
--- a/arch/tile/include/asm/processor.h
+++ b/arch/tile/include/asm/processor.h
@@ -215,6 +215,8 @@
extern int kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
+extern int do_work_pending(struct pt_regs *regs, u32 flags);
+
/*
* Return saved (kernel) PC of a blocked thread.
@@ -255,10 +257,6 @@
barrier();
}
-struct siginfo;
-extern void arch_coredump_signal(struct siginfo *, struct pt_regs *);
-#define arch_coredump_signal arch_coredump_signal
-
/* Info on this processor (see fs/proc/cpuinfo.c) */
struct seq_operations;
extern const struct seq_operations cpuinfo_op;
@@ -269,9 +267,6 @@
/* Data on which physical memory controller corresponds to which NUMA node. */
extern int node_controller[];
-/* Do we dump information to the console when a user application crashes? */
-extern int show_crashinfo;
-
#if CHIP_HAS_CBOX_HOME_MAP()
/* Does the heap allocator return hash-for-home pages by default? */
extern int hash_default;
diff --git a/arch/tile/include/asm/serial.h b/arch/tile/include/asm/serial.h
new file mode 100644
index 0000000..a0cb0ca
--- /dev/null
+++ b/arch/tile/include/asm/serial.h
@@ -0,0 +1 @@
+#include <asm-generic/serial.h>
diff --git a/arch/tile/include/asm/signal.h b/arch/tile/include/asm/signal.h
index 81d92a4..1e1e616 100644
--- a/arch/tile/include/asm/signal.h
+++ b/arch/tile/include/asm/signal.h
@@ -28,6 +28,10 @@
int restore_sigcontext(struct pt_regs *, struct sigcontext __user *);
int setup_sigcontext(struct sigcontext __user *, struct pt_regs *);
void do_signal(struct pt_regs *regs);
+void signal_fault(const char *type, struct pt_regs *,
+ void __user *frame, int sig);
+void trace_unhandled_signal(const char *type, struct pt_regs *regs,
+ unsigned long address, int signo);
#endif
#endif /* _ASM_TILE_SIGNAL_H */
diff --git a/arch/tile/include/asm/spinlock_64.h b/arch/tile/include/asm/spinlock_64.h
new file mode 100644
index 0000000..72be590
--- /dev/null
+++ b/arch/tile/include/asm/spinlock_64.h
@@ -0,0 +1,161 @@
+/*
+ * Copyright 2011 Tilera Corporation. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ * NON INFRINGEMENT. See the GNU General Public License for
+ * more details.
+ *
+ * 64-bit SMP ticket spinlocks, allowing only a single CPU anywhere
+ * (the type definitions are in asm/spinlock_types.h)
+ */
+
+#ifndef _ASM_TILE_SPINLOCK_64_H
+#define _ASM_TILE_SPINLOCK_64_H
+
+/* Shifts and masks for the various fields in "lock". */
+#define __ARCH_SPIN_CURRENT_SHIFT 17
+#define __ARCH_SPIN_NEXT_MASK 0x7fff
+#define __ARCH_SPIN_NEXT_OVERFLOW 0x8000
+
+/*
+ * Return the "current" portion of a ticket lock value,
+ * i.e. the number that currently owns the lock.
+ */
+static inline int arch_spin_current(u32 val)
+{
+ return val >> __ARCH_SPIN_CURRENT_SHIFT;
+}
+
+/*
+ * Return the "next" portion of a ticket lock value,
+ * i.e. the number that the next task to try to acquire the lock will get.
+ */
+static inline int arch_spin_next(u32 val)
+{
+ return val & __ARCH_SPIN_NEXT_MASK;
+}
+
+/* The lock is locked if a task would have to wait to get it. */
+static inline int arch_spin_is_locked(arch_spinlock_t *lock)
+{
+ u32 val = lock->lock;
+ return arch_spin_current(val) != arch_spin_next(val);
+}
+
+/* Bump the current ticket so the next task owns the lock. */
+static inline void arch_spin_unlock(arch_spinlock_t *lock)
+{
+ wmb(); /* guarantee anything modified under the lock is visible */
+ __insn_fetchadd4(&lock->lock, 1U << __ARCH_SPIN_CURRENT_SHIFT);
+}
+
+void arch_spin_unlock_wait(arch_spinlock_t *lock);
+
+void arch_spin_lock_slow(arch_spinlock_t *lock, u32 val);
+
+/* Grab the "next" ticket number and bump it atomically.
+ * If the current ticket is not ours, go to the slow path.
+ * We also take the slow path if the "next" value overflows.
+ */
+static inline void arch_spin_lock(arch_spinlock_t *lock)
+{
+ u32 val = __insn_fetchadd4(&lock->lock, 1);
+ u32 ticket = val & (__ARCH_SPIN_NEXT_MASK | __ARCH_SPIN_NEXT_OVERFLOW);
+ if (unlikely(arch_spin_current(val) != ticket))
+ arch_spin_lock_slow(lock, ticket);
+}
+
+/* Try to get the lock, and return whether we succeeded. */
+int arch_spin_trylock(arch_spinlock_t *lock);
+
+/* We cannot take an interrupt after getting a ticket, so don't enable them. */
+#define arch_spin_lock_flags(lock, flags) arch_spin_lock(lock)
+
+/*
+ * Read-write spinlocks, allowing multiple readers
+ * but only one writer.
+ *
+ * We use fetchadd() for readers, and fetchor() with the sign bit
+ * for writers.
+ */
+
+#define __WRITE_LOCK_BIT (1 << 31)
+
+static inline int arch_write_val_locked(int val)
+{
+ return val < 0; /* Optimize "val & __WRITE_LOCK_BIT". */
+}
+
+/**
+ * read_can_lock - would read_trylock() succeed?
+ * @lock: the rwlock in question.
+ */
+static inline int arch_read_can_lock(arch_rwlock_t *rw)
+{
+ return !arch_write_val_locked(rw->lock);
+}
+
+/**
+ * write_can_lock - would write_trylock() succeed?
+ * @lock: the rwlock in question.
+ */
+static inline int arch_write_can_lock(arch_rwlock_t *rw)
+{
+ return rw->lock == 0;
+}
+
+extern void __read_lock_failed(arch_rwlock_t *rw);
+
+static inline void arch_read_lock(arch_rwlock_t *rw)
+{
+ u32 val = __insn_fetchaddgez4(&rw->lock, 1);
+ if (unlikely(arch_write_val_locked(val)))
+ __read_lock_failed(rw);
+}
+
+extern void __write_lock_failed(arch_rwlock_t *rw, u32 val);
+
+static inline void arch_write_lock(arch_rwlock_t *rw)
+{
+ u32 val = __insn_fetchor4(&rw->lock, __WRITE_LOCK_BIT);
+ if (unlikely(val != 0))
+ __write_lock_failed(rw, val);
+}
+
+static inline void arch_read_unlock(arch_rwlock_t *rw)
+{
+ __insn_mf();
+ __insn_fetchadd4(&rw->lock, -1);
+}
+
+static inline void arch_write_unlock(arch_rwlock_t *rw)
+{
+ __insn_mf();
+ rw->lock = 0;
+}
+
+static inline int arch_read_trylock(arch_rwlock_t *rw)
+{
+ return !arch_write_val_locked(__insn_fetchaddgez4(&rw->lock, 1));
+}
+
+static inline int arch_write_trylock(arch_rwlock_t *rw)
+{
+ u32 val = __insn_fetchor4(&rw->lock, __WRITE_LOCK_BIT);
+ if (likely(val == 0))
+ return 1;
+ if (!arch_write_val_locked(val))
+ __insn_fetchand4(&rw->lock, ~__WRITE_LOCK_BIT);
+ return 0;
+}
+
+#define arch_read_lock_flags(lock, flags) arch_read_lock(lock)
+#define arch_write_lock_flags(lock, flags) arch_write_lock(lock)
+
+#endif /* _ASM_TILE_SPINLOCK_64_H */
diff --git a/arch/tile/include/asm/stat.h b/arch/tile/include/asm/stat.h
index b16e5db..c0db34d 100644
--- a/arch/tile/include/asm/stat.h
+++ b/arch/tile/include/asm/stat.h
@@ -1,4 +1,4 @@
-#ifdef CONFIG_COMPAT
+#if defined(__KERNEL__) && defined(CONFIG_COMPAT)
#define __ARCH_WANT_STAT64 /* Used for compat_sys_stat64() etc. */
#endif
#include <asm-generic/stat.h>
diff --git a/arch/tile/include/asm/swab.h b/arch/tile/include/asm/swab.h
index 25c686a..7c37b38 100644
--- a/arch/tile/include/asm/swab.h
+++ b/arch/tile/include/asm/swab.h
@@ -18,12 +18,6 @@
/* Tile gcc is always >= 4.3.0, so we use __builtin_bswap. */
#define __arch_swab32(x) __builtin_bswap32(x)
#define __arch_swab64(x) __builtin_bswap64(x)
-
-/* Use the variant that is natural for the wordsize. */
-#ifdef CONFIG_64BIT
-#define __arch_swab16(x) (__builtin_bswap64(x) >> 48)
-#else
#define __arch_swab16(x) (__builtin_bswap32(x) >> 16)
-#endif
#endif /* _ASM_TILE_SWAB_H */
diff --git a/arch/tile/include/asm/thread_info.h b/arch/tile/include/asm/thread_info.h
index 3405b52..bc4f562 100644
--- a/arch/tile/include/asm/thread_info.h
+++ b/arch/tile/include/asm/thread_info.h
@@ -125,6 +125,7 @@
#define TIF_SYSCALL_AUDIT 5 /* syscall auditing active */
#define TIF_SECCOMP 6 /* secure computing */
#define TIF_MEMDIE 7 /* OOM killer at work */
+#define TIF_NOTIFY_RESUME 8 /* callback before returning to user */
#define _TIF_SIGPENDING (1<<TIF_SIGPENDING)
#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED)
@@ -134,10 +135,12 @@
#define _TIF_SYSCALL_AUDIT (1<<TIF_SYSCALL_AUDIT)
#define _TIF_SECCOMP (1<<TIF_SECCOMP)
#define _TIF_MEMDIE (1<<TIF_MEMDIE)
+#define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME)
/* Work to do on any return to user space. */
#define _TIF_ALLWORK_MASK \
- (_TIF_SIGPENDING|_TIF_NEED_RESCHED|_TIF_SINGLESTEP|_TIF_ASYNC_TLB)
+ (_TIF_SIGPENDING|_TIF_NEED_RESCHED|_TIF_SINGLESTEP|\
+ _TIF_ASYNC_TLB|_TIF_NOTIFY_RESUME)
/*
* Thread-synchronous status.
diff --git a/arch/tile/include/asm/topology.h b/arch/tile/include/asm/topology.h
index 343172d..6fdd0c8 100644
--- a/arch/tile/include/asm/topology.h
+++ b/arch/tile/include/asm/topology.h
@@ -44,25 +44,64 @@
/* For now, use numa node -1 for global allocation. */
#define pcibus_to_node(bus) ((void)(bus), -1)
+/*
+ * TILE architecture has many cores integrated in one processor, so we need
+ * setup bigger balance_interval for both CPU/NODE scheduling domains to
+ * reduce process scheduling costs.
+ */
+
+/* sched_domains SD_CPU_INIT for TILE architecture */
+#define SD_CPU_INIT (struct sched_domain) { \
+ .min_interval = 4, \
+ .max_interval = 128, \
+ .busy_factor = 64, \
+ .imbalance_pct = 125, \
+ .cache_nice_tries = 1, \
+ .busy_idx = 2, \
+ .idle_idx = 1, \
+ .newidle_idx = 0, \
+ .wake_idx = 0, \
+ .forkexec_idx = 0, \
+ \
+ .flags = 1*SD_LOAD_BALANCE \
+ | 1*SD_BALANCE_NEWIDLE \
+ | 1*SD_BALANCE_EXEC \
+ | 1*SD_BALANCE_FORK \
+ | 0*SD_BALANCE_WAKE \
+ | 0*SD_WAKE_AFFINE \
+ | 0*SD_PREFER_LOCAL \
+ | 0*SD_SHARE_CPUPOWER \
+ | 0*SD_SHARE_PKG_RESOURCES \
+ | 0*SD_SERIALIZE \
+ , \
+ .last_balance = jiffies, \
+ .balance_interval = 32, \
+}
+
/* sched_domains SD_NODE_INIT for TILE architecture */
-#define SD_NODE_INIT (struct sched_domain) { \
- .min_interval = 8, \
- .max_interval = 32, \
- .busy_factor = 32, \
- .imbalance_pct = 125, \
- .cache_nice_tries = 1, \
- .busy_idx = 3, \
- .idle_idx = 1, \
- .newidle_idx = 2, \
- .wake_idx = 1, \
- .flags = SD_LOAD_BALANCE \
- | SD_BALANCE_NEWIDLE \
- | SD_BALANCE_EXEC \
- | SD_BALANCE_FORK \
- | SD_WAKE_AFFINE \
- | SD_SERIALIZE, \
- .last_balance = jiffies, \
- .balance_interval = 1, \
+#define SD_NODE_INIT (struct sched_domain) { \
+ .min_interval = 16, \
+ .max_interval = 512, \
+ .busy_factor = 32, \
+ .imbalance_pct = 125, \
+ .cache_nice_tries = 1, \
+ .busy_idx = 3, \
+ .idle_idx = 1, \
+ .newidle_idx = 2, \
+ .wake_idx = 1, \
+ .flags = 1*SD_LOAD_BALANCE \
+ | 1*SD_BALANCE_NEWIDLE \
+ | 1*SD_BALANCE_EXEC \
+ | 1*SD_BALANCE_FORK \
+ | 0*SD_BALANCE_WAKE \
+ | 0*SD_WAKE_AFFINE \
+ | 0*SD_PREFER_LOCAL \
+ | 0*SD_SHARE_CPUPOWER \
+ | 0*SD_SHARE_PKG_RESOURCES \
+ | 1*SD_SERIALIZE \
+ , \
+ .last_balance = jiffies, \
+ .balance_interval = 128, \
}
/* By definition, we create nodes based on online memory. */
diff --git a/arch/tile/include/asm/traps.h b/arch/tile/include/asm/traps.h
index d06e35f..5f20f92 100644
--- a/arch/tile/include/asm/traps.h
+++ b/arch/tile/include/asm/traps.h
@@ -15,10 +15,14 @@
#ifndef _ASM_TILE_TRAPS_H
#define _ASM_TILE_TRAPS_H
+#include <arch/chip.h>
+
/* mm/fault.c */
void do_page_fault(struct pt_regs *, int fault_num,
unsigned long address, unsigned long write);
+#if CHIP_HAS_TILE_DMA() || CHIP_HAS_SN_PROC()
void do_async_page_fault(struct pt_regs *);
+#endif
#ifndef __tilegx__
/*
diff --git a/arch/tile/include/asm/unistd.h b/arch/tile/include/asm/unistd.h
index b35c2db..f70bf1c 100644
--- a/arch/tile/include/asm/unistd.h
+++ b/arch/tile/include/asm/unistd.h
@@ -15,7 +15,7 @@
#if !defined(_ASM_TILE_UNISTD_H) || defined(__SYSCALL)
#define _ASM_TILE_UNISTD_H
-#ifndef __LP64__
+#if !defined(__LP64__) || defined(__SYSCALL_COMPAT)
/* Use the flavor of this syscall that matches the 32-bit API better. */
#define __ARCH_WANT_SYNC_FILE_RANGE2
#endif
diff --git a/arch/tile/include/asm/vga.h b/arch/tile/include/asm/vga.h
new file mode 100644
index 0000000..7b46e754
--- /dev/null
+++ b/arch/tile/include/asm/vga.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright 2010 Tilera Corporation. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ * NON INFRINGEMENT. See the GNU General Public License for
+ * more details.
+ *
+ * Access to VGA videoram.
+ */
+
+#ifndef _ASM_TILE_VGA_H
+#define _ASM_TILE_VGA_H
+
+#include <asm/io.h>
+
+#define VT_BUF_HAVE_RW
+
+static inline void scr_writew(u16 val, volatile u16 *addr)
+{
+ __raw_writew(val, (volatile u16 __iomem *) addr);
+}
+
+static inline u16 scr_readw(volatile const u16 *addr)
+{
+ return __raw_readw((volatile const u16 __iomem *) addr);
+}
+
+#define vga_readb(a) readb((u8 __iomem *)(a))
+#define vga_writeb(v,a) writeb(v, (u8 __iomem *)(a))
+
+#define VGA_MAP_MEM(x,s) ((unsigned long) ioremap(x, s))
+
+#endif
diff --git a/arch/tile/include/hv/hypervisor.h b/arch/tile/include/hv/hypervisor.h
index ee41bca..72ec1e9 100644
--- a/arch/tile/include/hv/hypervisor.h
+++ b/arch/tile/include/hv/hypervisor.h
@@ -22,8 +22,6 @@
#include <arch/chip.h>
-#include <hv/pagesize.h>
-
/* Linux builds want unsigned long constants, but assembler wants numbers */
#ifdef __ASSEMBLER__
/** One, for assembler */
@@ -44,11 +42,21 @@
*/
#define HV_L1_SPAN (__HV_SIZE_ONE << HV_LOG2_L1_SPAN)
+/** The log2 of the size of small pages, in bytes. This value should
+ * be verified at runtime by calling hv_sysconf(HV_SYSCONF_PAGE_SIZE_SMALL).
+ */
+#define HV_LOG2_PAGE_SIZE_SMALL 16
+
/** The size of small pages, in bytes. This value should be verified
* at runtime by calling hv_sysconf(HV_SYSCONF_PAGE_SIZE_SMALL).
*/
#define HV_PAGE_SIZE_SMALL (__HV_SIZE_ONE << HV_LOG2_PAGE_SIZE_SMALL)
+/** The log2 of the size of large pages, in bytes. This value should be
+ * verified at runtime by calling hv_sysconf(HV_SYSCONF_PAGE_SIZE_LARGE).
+ */
+#define HV_LOG2_PAGE_SIZE_LARGE 24
+
/** The size of large pages, in bytes. This value should be verified
* at runtime by calling hv_sysconf(HV_SYSCONF_PAGE_SIZE_LARGE).
*/
diff --git a/arch/tile/include/hv/pagesize.h b/arch/tile/include/hv/pagesize.h
deleted file mode 100644
index 58bed11..0000000
--- a/arch/tile/include/hv/pagesize.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation, version 2.
- *
- * This program is distributed in the hope that it will be useful, but
- * WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
- * NON INFRINGEMENT. See the GNU General Public License for
- * more details.
- */
-
-/**
- * @file pagesize.h
- */
-
-#ifndef _HV_PAGESIZE_H
-#define _HV_PAGESIZE_H
-
-/** The log2 of the size of small pages, in bytes. This value should
- * be verified at runtime by calling hv_sysconf(HV_SYSCONF_PAGE_SIZE_SMALL).
- */
-#define HV_LOG2_PAGE_SIZE_SMALL 16
-
-/** The log2 of the size of large pages, in bytes. This value should be
- * verified at runtime by calling hv_sysconf(HV_SYSCONF_PAGE_SIZE_LARGE).
- */
-#define HV_LOG2_PAGE_SIZE_LARGE 24
-
-#endif /* _HV_PAGESIZE_H */
diff --git a/arch/tile/kernel/backtrace.c b/arch/tile/kernel/backtrace.c
index 55a6a74..1dc71ea 100644
--- a/arch/tile/kernel/backtrace.c
+++ b/arch/tile/kernel/backtrace.c
@@ -14,19 +14,11 @@
#include <linux/kernel.h>
#include <linux/string.h>
-
#include <asm/backtrace.h>
-
-#include <arch/chip.h>
-
#include <asm/opcode-tile.h>
+#include <arch/abi.h>
-
-#define TREG_SP 54
-#define TREG_LR 55
-
-
-#if TILE_CHIP >= 10
+#ifdef __tilegx__
#define tile_bundle_bits tilegx_bundle_bits
#define TILE_MAX_INSTRUCTIONS_PER_BUNDLE TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE
#define TILE_BUNDLE_ALIGNMENT_IN_BYTES TILEGX_BUNDLE_ALIGNMENT_IN_BYTES
@@ -47,7 +39,7 @@
typedef int bt_int_reg_t;
#endif
-/** A decoded bundle used for backtracer analysis. */
+/* A decoded bundle used for backtracer analysis. */
struct BacktraceBundle {
tile_bundle_bits bits;
int num_insns;
@@ -56,23 +48,7 @@
};
-/* This implementation only makes sense for native tools. */
-/** Default function to read memory. */
-static bool bt_read_memory(void *result, VirtualAddress addr,
- unsigned int size, void *extra)
-{
- /* FIXME: this should do some horrible signal stuff to catch
- * SEGV cleanly and fail.
- *
- * Or else the caller should do the setjmp for efficiency.
- */
-
- memcpy(result, (const void *)addr, size);
- return true;
-}
-
-
-/** Locates an instruction inside the given bundle that
+/* Locates an instruction inside the given bundle that
* has the specified mnemonic, and whose first 'num_operands_to_match'
* operands exactly match those in 'operand_values'.
*/
@@ -107,13 +83,13 @@
return NULL;
}
-/** Does this bundle contain an 'iret' instruction? */
+/* Does this bundle contain an 'iret' instruction? */
static inline bool bt_has_iret(const struct BacktraceBundle *bundle)
{
return find_matching_insn(bundle, TILE_OPC_IRET, NULL, 0) != NULL;
}
-/** Does this bundle contain an 'addi sp, sp, OFFSET' or
+/* Does this bundle contain an 'addi sp, sp, OFFSET' or
* 'addli sp, sp, OFFSET' instruction, and if so, what is OFFSET?
*/
static bool bt_has_addi_sp(const struct BacktraceBundle *bundle, int *adjust)
@@ -124,7 +100,7 @@
find_matching_insn(bundle, TILE_OPC_ADDI, vals, 2);
if (insn == NULL)
insn = find_matching_insn(bundle, TILE_OPC_ADDLI, vals, 2);
-#if TILE_CHIP >= 10
+#ifdef __tilegx__
if (insn == NULL)
insn = find_matching_insn(bundle, TILEGX_OPC_ADDXLI, vals, 2);
if (insn == NULL)
@@ -137,7 +113,7 @@
return true;
}
-/** Does this bundle contain any 'info OP' or 'infol OP'
+/* Does this bundle contain any 'info OP' or 'infol OP'
* instruction, and if so, what are their OP? Note that OP is interpreted
* as an unsigned value by this code since that's what the caller wants.
* Returns the number of info ops found.
@@ -161,7 +137,7 @@
return num_ops;
}
-/** Does this bundle contain a jrp instruction, and if so, to which
+/* Does this bundle contain a jrp instruction, and if so, to which
* register is it jumping?
*/
static bool bt_has_jrp(const struct BacktraceBundle *bundle, int *target_reg)
@@ -175,7 +151,7 @@
return true;
}
-/** Does this bundle modify the specified register in any way? */
+/* Does this bundle modify the specified register in any way? */
static bool bt_modifies_reg(const struct BacktraceBundle *bundle, int reg)
{
int i, j;
@@ -195,34 +171,34 @@
return false;
}
-/** Does this bundle modify sp? */
+/* Does this bundle modify sp? */
static inline bool bt_modifies_sp(const struct BacktraceBundle *bundle)
{
return bt_modifies_reg(bundle, TREG_SP);
}
-/** Does this bundle modify lr? */
+/* Does this bundle modify lr? */
static inline bool bt_modifies_lr(const struct BacktraceBundle *bundle)
{
return bt_modifies_reg(bundle, TREG_LR);
}
-/** Does this bundle contain the instruction 'move fp, sp'? */
+/* Does this bundle contain the instruction 'move fp, sp'? */
static inline bool bt_has_move_r52_sp(const struct BacktraceBundle *bundle)
{
static const int vals[2] = { 52, TREG_SP };
return find_matching_insn(bundle, TILE_OPC_MOVE, vals, 2) != NULL;
}
-/** Does this bundle contain a store of lr to sp? */
+/* Does this bundle contain a store of lr to sp? */
static inline bool bt_has_sw_sp_lr(const struct BacktraceBundle *bundle)
{
static const int vals[2] = { TREG_SP, TREG_LR };
return find_matching_insn(bundle, OPCODE_STORE, vals, 2) != NULL;
}
-#if TILE_CHIP >= 10
-/** Track moveli values placed into registers. */
+#ifdef __tilegx__
+/* Track moveli values placed into registers. */
static inline void bt_update_moveli(const struct BacktraceBundle *bundle,
int moveli_args[])
{
@@ -238,7 +214,7 @@
}
}
-/** Does this bundle contain an 'add sp, sp, reg' instruction
+/* Does this bundle contain an 'add sp, sp, reg' instruction
* from a register that we saw a moveli into, and if so, what
* is the value in the register?
*/
@@ -260,11 +236,11 @@
}
#endif
-/** Locates the caller's PC and SP for a program starting at the
+/* Locates the caller's PC and SP for a program starting at the
* given address.
*/
static void find_caller_pc_and_caller_sp(CallerLocation *location,
- const VirtualAddress start_pc,
+ const unsigned long start_pc,
BacktraceMemoryReader read_memory_func,
void *read_memory_func_extra)
{
@@ -288,9 +264,9 @@
tile_bundle_bits prefetched_bundles[32];
int num_bundles_prefetched = 0;
int next_bundle = 0;
- VirtualAddress pc;
+ unsigned long pc;
-#if TILE_CHIP >= 10
+#ifdef __tilegx__
/* Naively try to track moveli values to support addx for -m32. */
int moveli_args[TILEGX_NUM_REGISTERS] = { 0 };
#endif
@@ -369,10 +345,6 @@
/* Weird; reserved value, ignore it. */
continue;
}
- if (info_operand & ENTRY_POINT_INFO_OP) {
- /* This info op is ignored by the backtracer. */
- continue;
- }
/* Skip info ops which are not in the
* "one_ago" mode we want right now.
@@ -453,7 +425,7 @@
if (!sp_determined) {
int adjust;
if (bt_has_addi_sp(&bundle, &adjust)
-#if TILE_CHIP >= 10
+#ifdef __tilegx__
|| bt_has_add_sp(&bundle, &adjust, moveli_args)
#endif
) {
@@ -504,7 +476,7 @@
}
}
-#if TILE_CHIP >= 10
+#ifdef __tilegx__
/* Track moveli arguments for -m32 mode. */
bt_update_moveli(&bundle, moveli_args);
#endif
@@ -546,18 +518,26 @@
}
}
+/* Initializes a backtracer to start from the given location.
+ *
+ * If the frame pointer cannot be determined it is set to -1.
+ *
+ * state: The state to be filled in.
+ * read_memory_func: A callback that reads memory.
+ * read_memory_func_extra: An arbitrary argument to read_memory_func.
+ * pc: The current PC.
+ * lr: The current value of the 'lr' register.
+ * sp: The current value of the 'sp' register.
+ * r52: The current value of the 'r52' register.
+ */
void backtrace_init(BacktraceIterator *state,
BacktraceMemoryReader read_memory_func,
void *read_memory_func_extra,
- VirtualAddress pc, VirtualAddress lr,
- VirtualAddress sp, VirtualAddress r52)
+ unsigned long pc, unsigned long lr,
+ unsigned long sp, unsigned long r52)
{
CallerLocation location;
- VirtualAddress fp, initial_frame_caller_pc;
-
- if (read_memory_func == NULL) {
- read_memory_func = bt_read_memory;
- }
+ unsigned long fp, initial_frame_caller_pc;
/* Find out where we are in the initial frame. */
find_caller_pc_and_caller_sp(&location, pc,
@@ -630,12 +610,15 @@
/* Handle the case where the register holds more bits than the VA. */
static bool valid_addr_reg(bt_int_reg_t reg)
{
- return ((VirtualAddress)reg == reg);
+ return ((unsigned long)reg == reg);
}
+/* Advances the backtracing state to the calling frame, returning
+ * true iff successful.
+ */
bool backtrace_next(BacktraceIterator *state)
{
- VirtualAddress next_fp, next_pc;
+ unsigned long next_fp, next_pc;
bt_int_reg_t next_frame[2];
if (state->fp == -1) {
diff --git a/arch/tile/kernel/compat.c b/arch/tile/kernel/compat.c
index dbc213a..bf5e9d7 100644
--- a/arch/tile/kernel/compat.c
+++ b/arch/tile/kernel/compat.c
@@ -135,26 +135,15 @@
/* Provide the compat syscall number to call mapping. */
#undef __SYSCALL
-#define __SYSCALL(nr, call) [nr] = (compat_##call),
+#define __SYSCALL(nr, call) [nr] = (call),
/* The generic versions of these don't work for Tile. */
#define compat_sys_msgrcv tile_compat_sys_msgrcv
#define compat_sys_msgsnd tile_compat_sys_msgsnd
/* See comments in sys.c */
-#define compat_sys_fadvise64 sys32_fadvise64
#define compat_sys_fadvise64_64 sys32_fadvise64_64
#define compat_sys_readahead sys32_readahead
-#define compat_sys_sync_file_range compat_sys_sync_file_range2
-
-/* We leverage the "struct stat64" type for 32-bit time_t/nsec. */
-#define compat_sys_stat64 sys_stat64
-#define compat_sys_lstat64 sys_lstat64
-#define compat_sys_fstat64 sys_fstat64
-#define compat_sys_fstatat64 sys_fstatat64
-
-/* The native sys_ptrace dynamically handles compat binaries. */
-#define compat_sys_ptrace sys_ptrace
/* Call the trampolines to manage pt_regs where necessary. */
#define compat_sys_execve _compat_sys_execve
diff --git a/arch/tile/kernel/compat_signal.c b/arch/tile/kernel/compat_signal.c
index dbb0dfc..a7869ad 100644
--- a/arch/tile/kernel/compat_signal.c
+++ b/arch/tile/kernel/compat_signal.c
@@ -317,7 +317,7 @@
return 0;
badframe:
- force_sig(SIGSEGV, current);
+ signal_fault("bad sigreturn frame", regs, frame, 0);
return 0;
}
@@ -431,6 +431,6 @@
return 0;
give_sigsegv:
- force_sigsegv(sig, current);
+ signal_fault("bad setup frame", regs, frame, sig);
return -EFAULT;
}
diff --git a/arch/tile/kernel/futex_64.S b/arch/tile/kernel/futex_64.S
new file mode 100644
index 0000000..f465d1e
--- /dev/null
+++ b/arch/tile/kernel/futex_64.S
@@ -0,0 +1,55 @@
+/*
+ * Copyright 2011 Tilera Corporation. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ * NON INFRINGEMENT. See the GNU General Public License for
+ * more details.
+ *
+ * Atomically access user memory, but use MMU to avoid propagating
+ * kernel exceptions.
+ */
+
+#include <linux/linkage.h>
+#include <asm/errno.h>
+#include <asm/futex.h>
+#include <asm/page.h>
+#include <asm/processor.h>
+
+/*
+ * Provide a set of atomic memory operations supporting <asm/futex.h>.
+ *
+ * r0: user address to manipulate
+ * r1: new value to write, or for cmpxchg, old value to compare against
+ * r2: (cmpxchg only) new value to write
+ *
+ * Return __get_user struct, r0 with value, r1 with error.
+ */
+#define FUTEX_OP(name, ...) \
+STD_ENTRY(futex_##name) \
+ __VA_ARGS__; \
+ { \
+ move r1, zero; \
+ jrp lr \
+ }; \
+ STD_ENDPROC(futex_##name); \
+ .pushsection __ex_table,"a"; \
+ .quad 1b, get_user_fault; \
+ .popsection
+
+ .pushsection .fixup,"ax"
+get_user_fault:
+ { movei r1, -EFAULT; jrp lr }
+ ENDPROC(get_user_fault)
+ .popsection
+
+FUTEX_OP(cmpxchg, mtspr CMPEXCH_VALUE, r1; 1: cmpexch4 r0, r0, r2)
+FUTEX_OP(set, 1: exch4 r0, r0, r1)
+FUTEX_OP(add, 1: fetchadd4 r0, r0, r1)
+FUTEX_OP(or, 1: fetchor4 r0, r0, r1)
+FUTEX_OP(andn, nor r1, r1, zero; 1: fetchand4 r0, r0, r1)
diff --git a/arch/tile/kernel/hardwall.c b/arch/tile/kernel/hardwall.c
index e910530..3bddef7 100644
--- a/arch/tile/kernel/hardwall.c
+++ b/arch/tile/kernel/hardwall.c
@@ -268,12 +268,10 @@
found_processes = 0;
list_for_each_entry(p, &rect->task_head, thread.hardwall_list) {
BUG_ON(p->thread.hardwall != rect);
- if (p->sighand) {
+ if (!(p->flags & PF_EXITING)) {
found_processes = 1;
pr_notice("hardwall: killing %d\n", p->pid);
- spin_lock(&p->sighand->siglock);
- __group_send_sig_info(info.si_signo, &info, p);
- spin_unlock(&p->sighand->siglock);
+ do_send_sig_info(info.si_signo, &info, p, false);
}
}
if (!found_processes)
diff --git a/arch/tile/kernel/head_64.S b/arch/tile/kernel/head_64.S
new file mode 100644
index 0000000..6bc3a93
--- /dev/null
+++ b/arch/tile/kernel/head_64.S
@@ -0,0 +1,269 @@
+/*
+ * Copyright 2011 Tilera Corporation. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ * NON INFRINGEMENT. See the GNU General Public License for
+ * more details.
+ *
+ * TILE startup code.
+ */
+
+#include <linux/linkage.h>
+#include <linux/init.h>
+#include <asm/page.h>
+#include <asm/pgtable.h>
+#include <asm/thread_info.h>
+#include <asm/processor.h>
+#include <asm/asm-offsets.h>
+#include <hv/hypervisor.h>
+#include <arch/chip.h>
+#include <arch/spr_def.h>
+
+/*
+ * This module contains the entry code for kernel images. It performs the
+ * minimal setup needed to call the generic C routines.
+ */
+
+ __HEAD
+ENTRY(_start)
+ /* Notify the hypervisor of what version of the API we want */
+ {
+ movei r1, TILE_CHIP
+ movei r2, TILE_CHIP_REV
+ }
+ {
+ moveli r0, _HV_VERSION
+ jal hv_init
+ }
+ /* Get a reasonable default ASID in r0 */
+ {
+ move r0, zero
+ jal hv_inquire_asid
+ }
+
+ /*
+ * Install the default page table. The relocation required to
+ * statically define the table is a bit too complex, so we have
+ * to plug in the pointer from the L0 to the L1 table by hand.
+ * We only do this on the first cpu to boot, though, since the
+ * other CPUs should see a properly-constructed page table.
+ */
+ {
+ v4int_l r2, zero, r0 /* ASID for hv_install_context */
+ moveli r4, hw1_last(swapper_pgprot - PAGE_OFFSET)
+ }
+ {
+ shl16insli r4, r4, hw0(swapper_pgprot - PAGE_OFFSET)
+ }
+ {
+ ld r1, r4 /* access_pte for hv_install_context */
+ }
+ {
+ moveli r0, hw1_last(.Lsv_data_pmd - PAGE_OFFSET)
+ moveli r6, hw1_last(temp_data_pmd - PAGE_OFFSET)
+ }
+ {
+ /* After initializing swapper_pgprot, HV_PTE_GLOBAL is set. */
+ bfextu r7, r1, HV_PTE_INDEX_GLOBAL, HV_PTE_INDEX_GLOBAL
+ inv r4
+ }
+ bnez r7, .Lno_write
+ {
+ shl16insli r0, r0, hw0(.Lsv_data_pmd - PAGE_OFFSET)
+ shl16insli r6, r6, hw0(temp_data_pmd - PAGE_OFFSET)
+ }
+ {
+ /* Cut off the low bits of the PT address. */
+ shrui r6, r6, HV_LOG2_PAGE_TABLE_ALIGN
+ /* Start with our access pte. */
+ move r5, r1
+ }
+ {
+ /* Stuff the address into the page table pointer slot of the PTE. */
+ bfins r5, r6, HV_PTE_INDEX_PTFN, \
+ HV_PTE_INDEX_PTFN + HV_PTE_PTFN_BITS - 1
+ }
+ {
+ /* Store the L0 data PTE. */
+ st r0, r5
+ addli r6, r6, (temp_code_pmd - temp_data_pmd) >> \
+ HV_LOG2_PAGE_TABLE_ALIGN
+ }
+ {
+ addli r0, r0, .Lsv_code_pmd - .Lsv_data_pmd
+ bfins r5, r6, HV_PTE_INDEX_PTFN, \
+ HV_PTE_INDEX_PTFN + HV_PTE_PTFN_BITS - 1
+ }
+ /* Store the L0 code PTE. */
+ st r0, r5
+
+.Lno_write:
+ moveli lr, hw2_last(1f)
+ {
+ shl16insli lr, lr, hw1(1f)
+ moveli r0, hw1_last(swapper_pg_dir - PAGE_OFFSET)
+ }
+ {
+ shl16insli lr, lr, hw0(1f)
+ shl16insli r0, r0, hw0(swapper_pg_dir - PAGE_OFFSET)
+ }
+ {
+ move r3, zero
+ j hv_install_context
+ }
+1:
+
+ /* Install the interrupt base. */
+ moveli r0, hw2_last(MEM_SV_START)
+ shl16insli r0, r0, hw1(MEM_SV_START)
+ shl16insli r0, r0, hw0(MEM_SV_START)
+ mtspr SPR_INTERRUPT_VECTOR_BASE_K, r0
+
+ /*
+ * Get our processor number and save it away in SAVE_K_0.
+ * Extract stuff from the topology structure: r4 = y, r6 = x,
+ * r5 = width. FIXME: consider whether we want to just make these
+ * 64-bit values (and if so fix smp_topology write below, too).
+ */
+ jal hv_inquire_topology
+ {
+ v4int_l r5, zero, r1 /* r5 = width */
+ shrui r4, r0, 32 /* r4 = y */
+ }
+ {
+ v4int_l r6, zero, r0 /* r6 = x */
+ mul_lu_lu r4, r4, r5
+ }
+ {
+ add r4, r4, r6 /* r4 == cpu == y*width + x */
+ }
+
+#ifdef CONFIG_SMP
+ /*
+ * Load up our per-cpu offset. When the first (master) tile
+ * boots, this value is still zero, so we will load boot_pc
+ * with start_kernel, and boot_sp with init_stack + THREAD_SIZE.
+ * The master tile initializes the per-cpu offset array, so that
+ * when subsequent (secondary) tiles boot, they will instead load
+ * from their per-cpu versions of boot_sp and boot_pc.
+ */
+ moveli r5, hw2_last(__per_cpu_offset)
+ shl16insli r5, r5, hw1(__per_cpu_offset)
+ shl16insli r5, r5, hw0(__per_cpu_offset)
+ shl3add r5, r4, r5
+ ld r5, r5
+ bnez r5, 1f
+
+ /*
+ * Save the width and height to the smp_topology variable
+ * for later use.
+ */
+ moveli r0, hw2_last(smp_topology + HV_TOPOLOGY_WIDTH_OFFSET)
+ shl16insli r0, r0, hw1(smp_topology + HV_TOPOLOGY_WIDTH_OFFSET)
+ shl16insli r0, r0, hw0(smp_topology + HV_TOPOLOGY_WIDTH_OFFSET)
+ st r0, r1
+1:
+#else
+ move r5, zero
+#endif
+
+ /* Load and go with the correct pc and sp. */
+ {
+ moveli r1, hw2_last(boot_sp)
+ moveli r0, hw2_last(boot_pc)
+ }
+ {
+ shl16insli r1, r1, hw1(boot_sp)
+ shl16insli r0, r0, hw1(boot_pc)
+ }
+ {
+ shl16insli r1, r1, hw0(boot_sp)
+ shl16insli r0, r0, hw0(boot_pc)
+ }
+ {
+ add r1, r1, r5
+ add r0, r0, r5
+ }
+ ld r0, r0
+ ld sp, r1
+ or r4, sp, r4
+ mtspr SPR_SYSTEM_SAVE_K_0, r4 /* save ksp0 + cpu */
+ addi sp, sp, -STACK_TOP_DELTA
+ {
+ move lr, zero /* stop backtraces in the called function */
+ jr r0
+ }
+ ENDPROC(_start)
+
+__PAGE_ALIGNED_BSS
+ .align PAGE_SIZE
+ENTRY(empty_zero_page)
+ .fill PAGE_SIZE,1,0
+ END(empty_zero_page)
+
+ .macro PTE cpa, bits1
+ .quad HV_PTE_PAGE | HV_PTE_DIRTY | HV_PTE_PRESENT | HV_PTE_ACCESSED |\
+ HV_PTE_GLOBAL | (HV_PTE_MODE_CACHE_NO_L3 << HV_PTE_INDEX_MODE) |\
+ (\bits1) | (HV_CPA_TO_PFN(\cpa) << HV_PTE_INDEX_PFN)
+ .endm
+
+__PAGE_ALIGNED_DATA
+ .align PAGE_SIZE
+ENTRY(swapper_pg_dir)
+ .org swapper_pg_dir + HV_L0_INDEX(PAGE_OFFSET) * HV_PTE_SIZE
+.Lsv_data_pmd:
+ .quad 0 /* PTE temp_data_pmd - PAGE_OFFSET, 0 */
+ .org swapper_pg_dir + HV_L0_INDEX(MEM_SV_START) * HV_PTE_SIZE
+.Lsv_code_pmd:
+ .quad 0 /* PTE temp_code_pmd - PAGE_OFFSET, 0 */
+ .org swapper_pg_dir + HV_L0_SIZE
+ END(swapper_pg_dir)
+
+ .align HV_PAGE_TABLE_ALIGN
+ENTRY(temp_data_pmd)
+ /*
+ * We fill the PAGE_OFFSET pmd with huge pages with
+ * VA = PA + PAGE_OFFSET. We remap things with more precise access
+ * permissions later.
+ */
+ .set addr, 0
+ .rept HV_L1_ENTRIES
+ PTE addr, HV_PTE_READABLE | HV_PTE_WRITABLE
+ .set addr, addr + HV_PAGE_SIZE_LARGE
+ .endr
+ .org temp_data_pmd + HV_L1_SIZE
+ END(temp_data_pmd)
+
+ .align HV_PAGE_TABLE_ALIGN
+ENTRY(temp_code_pmd)
+ /*
+ * We fill the MEM_SV_START pmd with huge pages with
+ * VA = PA + PAGE_OFFSET. We remap things with more precise access
+ * permissions later.
+ */
+ .set addr, 0
+ .rept HV_L1_ENTRIES
+ PTE addr, HV_PTE_READABLE | HV_PTE_EXECUTABLE
+ .set addr, addr + HV_PAGE_SIZE_LARGE
+ .endr
+ .org temp_code_pmd + HV_L1_SIZE
+ END(temp_code_pmd)
+
+ /*
+ * Isolate swapper_pgprot to its own cache line, since each cpu
+ * starting up will read it using VA-is-PA and local homing.
+ * This would otherwise likely conflict with other data on the cache
+ * line, once we have set its permanent home in the page tables.
+ */
+ __INITDATA
+ .align CHIP_L2_LINE_SIZE()
+ENTRY(swapper_pgprot)
+ .quad HV_PTE_PRESENT | (HV_PTE_MODE_CACHE_NO_L3 << HV_PTE_INDEX_MODE)
+ .align CHIP_L2_LINE_SIZE()
+ END(swapper_pgprot)
diff --git a/arch/tile/kernel/intvec_32.S b/arch/tile/kernel/intvec_32.S
index fffcfa6..72ade79 100644
--- a/arch/tile/kernel/intvec_32.S
+++ b/arch/tile/kernel/intvec_32.S
@@ -851,14 +851,27 @@
/* Check to see if there is any work to do before returning to user. */
{
addi r29, r32, THREAD_INFO_FLAGS_OFFSET
- moveli r28, lo16(_TIF_ALLWORK_MASK)
+ moveli r1, lo16(_TIF_ALLWORK_MASK)
}
{
lw r29, r29
- auli r28, r28, ha16(_TIF_ALLWORK_MASK)
+ auli r1, r1, ha16(_TIF_ALLWORK_MASK)
}
- and r28, r29, r28
- bnz r28, .Lwork_pending
+ and r1, r29, r1
+ bzt r1, .Lrestore_all
+
+ /*
+ * Make sure we have all the registers saved for signal
+ * handling or single-step. Call out to C code to figure out
+ * exactly what we need to do for each flag bit, then if
+ * necessary, reload the flags and recheck.
+ */
+ push_extra_callee_saves r0
+ {
+ PTREGS_PTR(r0, PTREGS_OFFSET_BASE)
+ jal do_work_pending
+ }
+ bnz r0, .Lresume_userspace
/*
* In the NMI case we
@@ -1099,99 +1112,6 @@
pop_reg r50
pop_reg r51, sp, PTREGS_OFFSET_REG(29) - PTREGS_OFFSET_REG(51)
j .Lcontinue_restore_regs
-
-.Lwork_pending:
- /* Mask the reschedule flag */
- andi r28, r29, _TIF_NEED_RESCHED
-
- {
- /*
- * If the NEED_RESCHED flag is called, we call schedule(), which
- * may drop this context right here and go do something else.
- * On return, jump back to .Lresume_userspace and recheck.
- */
- bz r28, .Lasync_tlb
-
- /* Mask the async-tlb flag */
- andi r28, r29, _TIF_ASYNC_TLB
- }
-
- jal schedule
- FEEDBACK_REENTER(interrupt_return)
-
- /* Reload the flags and check again */
- j .Lresume_userspace
-
-.Lasync_tlb:
- {
- bz r28, .Lneed_sigpending
-
- /* Mask the sigpending flag */
- andi r28, r29, _TIF_SIGPENDING
- }
-
- PTREGS_PTR(r0, PTREGS_OFFSET_BASE)
- jal do_async_page_fault
- FEEDBACK_REENTER(interrupt_return)
-
- /*
- * Go restart the "resume userspace" process. We may have
- * fired a signal, and we need to disable interrupts again.
- */
- j .Lresume_userspace
-
-.Lneed_sigpending:
- /*
- * At this point we are either doing signal handling or single-step,
- * so either way make sure we have all the registers saved.
- */
- push_extra_callee_saves r0
-
- {
- /* If no signal pending, skip to singlestep check */
- bz r28, .Lneed_singlestep
-
- /* Mask the singlestep flag */
- andi r28, r29, _TIF_SINGLESTEP
- }
-
- jal do_signal
- FEEDBACK_REENTER(interrupt_return)
-
- /* Reload the flags and check again */
- j .Lresume_userspace
-
-.Lneed_singlestep:
- {
- /* Get a pointer to the EX1 field */
- PTREGS_PTR(r29, PTREGS_OFFSET_EX1)
-
- /* If we get here, our bit must be set. */
- bz r28, .Lwork_confusion
- }
- /* If we are in priv mode, don't single step */
- lw r28, r29
- andi r28, r28, SPR_EX_CONTEXT_1_1__PL_MASK /* mask off ICS */
- bnz r28, .Lrestore_all
-
- /* Allow interrupts within the single step code */
- TRACE_IRQS_ON /* Note: clobbers registers r0-r29 */
- IRQ_ENABLE(r20, r21)
-
- /* try to single-step the current instruction */
- PTREGS_PTR(r0, PTREGS_OFFSET_BASE)
- jal single_step_once
- FEEDBACK_REENTER(interrupt_return)
-
- /* Re-disable interrupts. TRACE_IRQS_OFF in .Lrestore_all. */
- IRQ_DISABLE(r20,r21)
-
- j .Lrestore_all
-
-.Lwork_confusion:
- move r0, r28
- panic "thread_info allwork flags unhandled on userspace resume: %#x"
-
STD_ENDPROC(interrupt_return)
/*
@@ -1550,7 +1470,10 @@
* We place it in the __HEAD section to ensure it is relatively
* near to the intvec_SWINT_1 code (reachable by a conditional branch).
*
- * Must match register usage in do_page_fault().
+ * Our use of ATOMIC_LOCK_REG here must match do_page_fault_ics().
+ *
+ * As we do in lib/atomic_asm_32.S, we bypass a store if the value we
+ * would store is the same as the value we just loaded.
*/
__HEAD
.align 64
@@ -1611,17 +1534,7 @@
{
shri r20, r25, 32 - ATOMIC_HASH_L1_SHIFT
slt_u r23, r0, r23
-
- /*
- * Ensure that the TLB is loaded before we take out the lock.
- * On TILEPro, this will start fetching the value all the way
- * into our L1 as well (and if it gets modified before we
- * grab the lock, it will be invalidated from our cache
- * before we reload it). On tile64, we'll start fetching it
- * into our L1 if we're the home, and if we're not, we'll
- * still at least start fetching it into the home's L2.
- */
- lw r26, r0
+ lw r26, r0 /* see comment in the "#else" for the "lw r26". */
}
{
s2a r21, r20, r21
@@ -1637,18 +1550,9 @@
bbs r23, .Lcmpxchg64
andi r23, r0, 7 /* Precompute alignment for cmpxchg64. */
}
-
{
- /*
- * We very carefully align the code that actually runs with
- * the lock held (nine bundles) so that we know it is all in
- * the icache when we start. This instruction (the jump) is
- * at the start of the first cache line, address zero mod 64;
- * we jump to somewhere in the second cache line to issue the
- * tns, then jump back to finish up.
- */
s2a ATOMIC_LOCK_REG_NAME, r25, r21
- j .Lcmpxchg32_tns
+ j .Lcmpxchg32_tns /* see comment in the #else for the jump. */
}
#else /* ATOMIC_LOCKS_FOUND_VIA_TABLE() */
@@ -1713,24 +1617,25 @@
{
/*
* We very carefully align the code that actually runs with
- * the lock held (nine bundles) so that we know it is all in
+ * the lock held (twelve bundles) so that we know it is all in
* the icache when we start. This instruction (the jump) is
* at the start of the first cache line, address zero mod 64;
- * we jump to somewhere in the second cache line to issue the
- * tns, then jump back to finish up.
+ * we jump to the very end of the second cache line to get that
+ * line loaded in the icache, then fall through to issue the tns
+ * in the third cache line, at which point it's all cached.
+ * Note that is for performance, not correctness.
*/
j .Lcmpxchg32_tns
}
#endif /* ATOMIC_LOCKS_FOUND_VIA_TABLE() */
- ENTRY(__sys_cmpxchg_grab_lock)
+/* Symbol for do_page_fault_ics() to use to compare against the PC. */
+.global __sys_cmpxchg_grab_lock
+__sys_cmpxchg_grab_lock:
/*
* Perform the actual cmpxchg or atomic_update.
- * Note that the system <arch/atomic.h> header relies on
- * atomic_update() to always perform an "mf", so don't make
- * it optional or conditional without modifying that code.
*/
.Ldo_cmpxchg32:
{
@@ -1748,10 +1653,13 @@
}
{
mvnz r24, r23, r25 /* Use atomic_update value if appropriate. */
- bbns r22, .Lcmpxchg32_mismatch
+ bbns r22, .Lcmpxchg32_nostore
}
+ seq r22, r24, r21 /* Are we storing the value we loaded? */
+ bbs r22, .Lcmpxchg32_nostore
sw r0, r24
+ /* The following instruction is the start of the second cache line. */
/* Do slow mtspr here so the following "mf" waits less. */
{
move sp, r27
@@ -1759,7 +1667,6 @@
}
mf
- /* The following instruction is the start of the second cache line. */
{
move r0, r21
sw ATOMIC_LOCK_REG_NAME, zero
@@ -1767,7 +1674,7 @@
iret
/* Duplicated code here in the case where we don't overlap "mf" */
-.Lcmpxchg32_mismatch:
+.Lcmpxchg32_nostore:
{
move r0, r21
sw ATOMIC_LOCK_REG_NAME, zero
@@ -1783,8 +1690,6 @@
* and for 64-bit cmpxchg. We provide it as a macro and put
* it into both versions. We can't share the code literally
* since it depends on having the right branch-back address.
- * Note that the first few instructions should share the cache
- * line with the second half of the actual locked code.
*/
.macro cmpxchg_lock, bitwidth
@@ -1810,7 +1715,7 @@
}
/*
* The preceding instruction is the last thing that must be
- * on the second cache line.
+ * hot in the icache before we do the "tns" above.
*/
#ifdef CONFIG_SMP
@@ -1841,6 +1746,12 @@
.endm
.Lcmpxchg32_tns:
+ /*
+ * This is the last instruction on the second cache line.
+ * The nop here loads the second line, then we fall through
+ * to the tns to load the third line before we take the lock.
+ */
+ nop
cmpxchg_lock 32
/*
diff --git a/arch/tile/kernel/intvec_64.S b/arch/tile/kernel/intvec_64.S
new file mode 100644
index 0000000..79c93e1
--- /dev/null
+++ b/arch/tile/kernel/intvec_64.S
@@ -0,0 +1,1231 @@
+/*
+ * Copyright 2011 Tilera Corporation. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ * NON INFRINGEMENT. See the GNU General Public License for
+ * more details.
+ *
+ * Linux interrupt vectors.
+ */
+
+#include <linux/linkage.h>
+#include <linux/errno.h>
+#include <linux/unistd.h>
+#include <asm/ptrace.h>
+#include <asm/thread_info.h>
+#include <asm/irqflags.h>
+#include <asm/asm-offsets.h>
+#include <asm/types.h>
+#include <hv/hypervisor.h>
+#include <arch/abi.h>
+#include <arch/interrupts.h>
+#include <arch/spr_def.h>
+
+#ifdef CONFIG_PREEMPT
+# error "No support for kernel preemption currently"
+#endif
+
+#define PTREGS_PTR(reg, ptreg) addli reg, sp, C_ABI_SAVE_AREA_SIZE + (ptreg)
+
+#define PTREGS_OFFSET_SYSCALL PTREGS_OFFSET_REG(TREG_SYSCALL_NR)
+
+
+ .macro push_reg reg, ptr=sp, delta=-8
+ {
+ st \ptr, \reg
+ addli \ptr, \ptr, \delta
+ }
+ .endm
+
+ .macro pop_reg reg, ptr=sp, delta=8
+ {
+ ld \reg, \ptr
+ addli \ptr, \ptr, \delta
+ }
+ .endm
+
+ .macro pop_reg_zero reg, zreg, ptr=sp, delta=8
+ {
+ move \zreg, zero
+ ld \reg, \ptr
+ addi \ptr, \ptr, \delta
+ }
+ .endm
+
+ .macro push_extra_callee_saves reg
+ PTREGS_PTR(\reg, PTREGS_OFFSET_REG(51))
+ push_reg r51, \reg
+ push_reg r50, \reg
+ push_reg r49, \reg
+ push_reg r48, \reg
+ push_reg r47, \reg
+ push_reg r46, \reg
+ push_reg r45, \reg
+ push_reg r44, \reg
+ push_reg r43, \reg
+ push_reg r42, \reg
+ push_reg r41, \reg
+ push_reg r40, \reg
+ push_reg r39, \reg
+ push_reg r38, \reg
+ push_reg r37, \reg
+ push_reg r36, \reg
+ push_reg r35, \reg
+ push_reg r34, \reg, PTREGS_OFFSET_BASE - PTREGS_OFFSET_REG(34)
+ .endm
+
+ .macro panic str
+ .pushsection .rodata, "a"
+1:
+ .asciz "\str"
+ .popsection
+ {
+ moveli r0, hw2_last(1b)
+ }
+ {
+ shl16insli r0, r0, hw1(1b)
+ }
+ {
+ shl16insli r0, r0, hw0(1b)
+ jal panic
+ }
+ .endm
+
+
+#ifdef __COLLECT_LINKER_FEEDBACK__
+ .pushsection .text.intvec_feedback,"ax"
+intvec_feedback:
+ .popsection
+#endif
+
+ /*
+ * Default interrupt handler.
+ *
+ * vecnum is where we'll put this code.
+ * c_routine is the C routine we'll call.
+ *
+ * The C routine is passed two arguments:
+ * - A pointer to the pt_regs state.
+ * - The interrupt vector number.
+ *
+ * The "processing" argument specifies the code for processing
+ * the interrupt. Defaults to "handle_interrupt".
+ */
+ .macro int_hand vecnum, vecname, c_routine, processing=handle_interrupt
+ .org (\vecnum << 8)
+intvec_\vecname:
+ /* Temporarily save a register so we have somewhere to work. */
+
+ mtspr SPR_SYSTEM_SAVE_K_1, r0
+ mfspr r0, SPR_EX_CONTEXT_K_1
+
+ andi r0, r0, SPR_EX_CONTEXT_1_1__PL_MASK /* mask off ICS */
+
+ .ifc \vecnum, INT_DOUBLE_FAULT
+ /*
+ * For double-faults from user-space, fall through to the normal
+ * register save and stack setup path. Otherwise, it's the
+ * hypervisor giving us one last chance to dump diagnostics, and we
+ * branch to the kernel_double_fault routine to do so.
+ */
+ beqz r0, 1f
+ j _kernel_double_fault
+1:
+ .else
+ /*
+ * If we're coming from user-space, then set sp to the top of
+ * the kernel stack. Otherwise, assume sp is already valid.
+ */
+ {
+ bnez r0, 0f
+ move r0, sp
+ }
+ .endif
+
+ .ifc \c_routine, do_page_fault
+ /*
+ * The page_fault handler may be downcalled directly by the
+ * hypervisor even when Linux is running and has ICS set.
+ *
+ * In this case the contents of EX_CONTEXT_K_1 reflect the
+ * previous fault and can't be relied on to choose whether or
+ * not to reinitialize the stack pointer. So we add a test
+ * to see whether SYSTEM_SAVE_K_2 has the high bit set,
+ * and if so we don't reinitialize sp, since we must be coming
+ * from Linux. (In fact the precise case is !(val & ~1),
+ * but any Linux PC has to have the high bit set.)
+ *
+ * Note that the hypervisor *always* sets SYSTEM_SAVE_K_2 for
+ * any path that turns into a downcall to one of our TLB handlers.
+ *
+ * FIXME: if we end up never using this path, perhaps we should
+ * prevent the hypervisor from generating downcalls in this case.
+ * The advantage of getting a downcall is we can panic in Linux.
+ */
+ mfspr r0, SPR_SYSTEM_SAVE_K_2
+ {
+ bltz r0, 0f /* high bit in S_S_1_2 is for a PC to use */
+ move r0, sp
+ }
+ .endif
+
+
+ /*
+ * SYSTEM_SAVE_K_0 holds the cpu number in the low bits, and
+ * the current stack top in the higher bits. So we recover
+ * our stack top by just masking off the low bits, then
+ * point sp at the top aligned address on the actual stack page.
+ */
+ mfspr r0, SPR_SYSTEM_SAVE_K_0
+ mm r0, zero, LOG2_THREAD_SIZE, 63
+
+0:
+ /*
+ * Align the stack mod 64 so we can properly predict what
+ * cache lines we need to write-hint to reduce memory fetch
+ * latency as we enter the kernel. The layout of memory is
+ * as follows, with cache line 0 at the lowest VA, and cache
+ * line 8 just below the r0 value this "andi" computes.
+ * Note that we never write to cache line 8, and we skip
+ * cache lines 1-3 for syscalls.
+ *
+ * cache line 8: ptregs padding (two words)
+ * cache line 7: sp, lr, pc, ex1, faultnum, orig_r0, flags, cmpexch
+ * cache line 6: r46...r53 (tp)
+ * cache line 5: r38...r45
+ * cache line 4: r30...r37
+ * cache line 3: r22...r29
+ * cache line 2: r14...r21
+ * cache line 1: r6...r13
+ * cache line 0: 2 x frame, r0..r5
+ */
+ andi r0, r0, -64
+
+ /*
+ * Push the first four registers on the stack, so that we can set
+ * them to vector-unique values before we jump to the common code.
+ *
+ * Registers are pushed on the stack as a struct pt_regs,
+ * with the sp initially just above the struct, and when we're
+ * done, sp points to the base of the struct, minus
+ * C_ABI_SAVE_AREA_SIZE, so we can directly jal to C code.
+ *
+ * This routine saves just the first four registers, plus the
+ * stack context so we can do proper backtracing right away,
+ * and defers to handle_interrupt to save the rest.
+ * The backtracer needs pc, ex1, lr, sp, r52, and faultnum.
+ */
+ addli r0, r0, PTREGS_OFFSET_LR - (PTREGS_SIZE + KSTK_PTREGS_GAP)
+ wh64 r0 /* cache line 7 */
+ {
+ st r0, lr
+ addli r0, r0, PTREGS_OFFSET_SP - PTREGS_OFFSET_LR
+ }
+ {
+ st r0, sp
+ addli sp, r0, PTREGS_OFFSET_REG(52) - PTREGS_OFFSET_SP
+ }
+ wh64 sp /* cache line 6 */
+ {
+ st sp, r52
+ addli sp, sp, PTREGS_OFFSET_REG(1) - PTREGS_OFFSET_REG(52)
+ }
+ wh64 sp /* cache line 0 */
+ {
+ st sp, r1
+ addli sp, sp, PTREGS_OFFSET_REG(2) - PTREGS_OFFSET_REG(1)
+ }
+ {
+ st sp, r2
+ addli sp, sp, PTREGS_OFFSET_REG(3) - PTREGS_OFFSET_REG(2)
+ }
+ {
+ st sp, r3
+ addli sp, sp, PTREGS_OFFSET_PC - PTREGS_OFFSET_REG(3)
+ }
+ mfspr r0, SPR_EX_CONTEXT_K_0
+ .ifc \processing,handle_syscall
+ /*
+ * Bump the saved PC by one bundle so that when we return, we won't
+ * execute the same swint instruction again. We need to do this while
+ * we're in the critical section.
+ */
+ addi r0, r0, 8
+ .endif
+ {
+ st sp, r0
+ addli sp, sp, PTREGS_OFFSET_EX1 - PTREGS_OFFSET_PC
+ }
+ mfspr r0, SPR_EX_CONTEXT_K_1
+ {
+ st sp, r0
+ addi sp, sp, PTREGS_OFFSET_FAULTNUM - PTREGS_OFFSET_EX1
+ /*
+ * Use r0 for syscalls so it's a temporary; use r1 for interrupts
+ * so that it gets passed through unchanged to the handler routine.
+ * Note that the .if conditional confusingly spans bundles.
+ */
+ .ifc \processing,handle_syscall
+ movei r0, \vecnum
+ }
+ {
+ st sp, r0
+ .else
+ movei r1, \vecnum
+ }
+ {
+ st sp, r1
+ .endif
+ addli sp, sp, PTREGS_OFFSET_REG(0) - PTREGS_OFFSET_FAULTNUM
+ }
+ mfspr r0, SPR_SYSTEM_SAVE_K_1 /* Original r0 */
+ {
+ st sp, r0
+ addi sp, sp, -PTREGS_OFFSET_REG(0) - 8
+ }
+ {
+ st sp, zero /* write zero into "Next SP" frame pointer */
+ addi sp, sp, -8 /* leave SP pointing at bottom of frame */
+ }
+ .ifc \processing,handle_syscall
+ j handle_syscall
+ .else
+ /* Capture per-interrupt SPR context to registers. */
+ .ifc \c_routine, do_page_fault
+ mfspr r2, SPR_SYSTEM_SAVE_K_3 /* address of page fault */
+ mfspr r3, SPR_SYSTEM_SAVE_K_2 /* info about page fault */
+ .else
+ .ifc \vecnum, INT_ILL_TRANS
+ mfspr r2, ILL_TRANS_REASON
+ .else
+ .ifc \vecnum, INT_DOUBLE_FAULT
+ mfspr r2, SPR_SYSTEM_SAVE_K_2 /* double fault info from HV */
+ .else
+ .ifc \c_routine, do_trap
+ mfspr r2, GPV_REASON
+ .else
+ .ifc \c_routine, op_handle_perf_interrupt
+ mfspr r2, PERF_COUNT_STS
+#if CHIP_HAS_AUX_PERF_COUNTERS()
+ .else
+ .ifc \c_routine, op_handle_aux_perf_interrupt
+ mfspr r2, AUX_PERF_COUNT_STS
+ .endif
+#endif
+ .endif
+ .endif
+ .endif
+ .endif
+ .endif
+ /* Put function pointer in r0 */
+ moveli r0, hw2_last(\c_routine)
+ shl16insli r0, r0, hw1(\c_routine)
+ {
+ shl16insli r0, r0, hw0(\c_routine)
+ j \processing
+ }
+ .endif
+ ENDPROC(intvec_\vecname)
+
+#ifdef __COLLECT_LINKER_FEEDBACK__
+ .pushsection .text.intvec_feedback,"ax"
+ .org (\vecnum << 5)
+ FEEDBACK_ENTER_EXPLICIT(intvec_\vecname, .intrpt1, 1 << 8)
+ jrp lr
+ .popsection
+#endif
+
+ .endm
+
+
+ /*
+ * Save the rest of the registers that we didn't save in the actual
+ * vector itself. We can't use r0-r10 inclusive here.
+ */
+ .macro finish_interrupt_save, function
+
+ /* If it's a syscall, save a proper orig_r0, otherwise just zero. */
+ PTREGS_PTR(r52, PTREGS_OFFSET_ORIG_R0)
+ {
+ .ifc \function,handle_syscall
+ st r52, r0
+ .else
+ st r52, zero
+ .endif
+ PTREGS_PTR(r52, PTREGS_OFFSET_TP)
+ }
+ st r52, tp
+ {
+ mfspr tp, CMPEXCH_VALUE
+ PTREGS_PTR(r52, PTREGS_OFFSET_CMPEXCH)
+ }
+
+ /*
+ * For ordinary syscalls, we save neither caller- nor callee-
+ * save registers, since the syscall invoker doesn't expect the
+ * caller-saves to be saved, and the called kernel functions will
+ * take care of saving the callee-saves for us.
+ *
+ * For interrupts we save just the caller-save registers. Saving
+ * them is required (since the "caller" can't save them). Again,
+ * the called kernel functions will restore the callee-save
+ * registers for us appropriately.
+ *
+ * On return, we normally restore nothing special for syscalls,
+ * and just the caller-save registers for interrupts.
+ *
+ * However, there are some important caveats to all this:
+ *
+ * - We always save a few callee-save registers to give us
+ * some scratchpad registers to carry across function calls.
+ *
+ * - fork/vfork/etc require us to save all the callee-save
+ * registers, which we do in PTREGS_SYSCALL_ALL_REGS, below.
+ *
+ * - We always save r0..r5 and r10 for syscalls, since we need
+ * to reload them a bit later for the actual kernel call, and
+ * since we might need them for -ERESTARTNOINTR, etc.
+ *
+ * - Before invoking a signal handler, we save the unsaved
+ * callee-save registers so they are visible to the
+ * signal handler or any ptracer.
+ *
+ * - If the unsaved callee-save registers are modified, we set
+ * a bit in pt_regs so we know to reload them from pt_regs
+ * and not just rely on the kernel function unwinding.
+ * (Done for ptrace register writes and SA_SIGINFO handler.)
+ */
+ {
+ st r52, tp
+ PTREGS_PTR(r52, PTREGS_OFFSET_REG(33))
+ }
+ wh64 r52 /* cache line 4 */
+ push_reg r33, r52
+ push_reg r32, r52
+ push_reg r31, r52
+ .ifc \function,handle_syscall
+ push_reg r30, r52, PTREGS_OFFSET_SYSCALL - PTREGS_OFFSET_REG(30)
+ push_reg TREG_SYSCALL_NR_NAME, r52, \
+ PTREGS_OFFSET_REG(5) - PTREGS_OFFSET_SYSCALL
+ .else
+
+ push_reg r30, r52, PTREGS_OFFSET_REG(29) - PTREGS_OFFSET_REG(30)
+ wh64 r52 /* cache line 3 */
+ push_reg r29, r52
+ push_reg r28, r52
+ push_reg r27, r52
+ push_reg r26, r52
+ push_reg r25, r52
+ push_reg r24, r52
+ push_reg r23, r52
+ push_reg r22, r52
+ wh64 r52 /* cache line 2 */
+ push_reg r21, r52
+ push_reg r20, r52
+ push_reg r19, r52
+ push_reg r18, r52
+ push_reg r17, r52
+ push_reg r16, r52
+ push_reg r15, r52
+ push_reg r14, r52
+ wh64 r52 /* cache line 1 */
+ push_reg r13, r52
+ push_reg r12, r52
+ push_reg r11, r52
+ push_reg r10, r52
+ push_reg r9, r52
+ push_reg r8, r52
+ push_reg r7, r52
+ push_reg r6, r52
+
+ .endif
+
+ push_reg r5, r52
+ st r52, r4
+
+ /* Load tp with our per-cpu offset. */
+#ifdef CONFIG_SMP
+ {
+ mfspr r20, SPR_SYSTEM_SAVE_K_0
+ moveli r21, hw2_last(__per_cpu_offset)
+ }
+ {
+ shl16insli r21, r21, hw1(__per_cpu_offset)
+ bfextu r20, r20, 0, LOG2_THREAD_SIZE-1
+ }
+ shl16insli r21, r21, hw0(__per_cpu_offset)
+ shl3add r20, r20, r21
+ ld tp, r20
+#else
+ move tp, zero
+#endif
+
+ /*
+ * If we will be returning to the kernel, we will need to
+ * reset the interrupt masks to the state they had before.
+ * Set DISABLE_IRQ in flags iff we came from PL1 with irqs disabled.
+ */
+ mfspr r32, SPR_EX_CONTEXT_K_1
+ {
+ andi r32, r32, SPR_EX_CONTEXT_1_1__PL_MASK /* mask off ICS */
+ PTREGS_PTR(r21, PTREGS_OFFSET_FLAGS)
+ }
+ beqzt r32, 1f /* zero if from user space */
+ IRQS_DISABLED(r32) /* zero if irqs enabled */
+#if PT_FLAGS_DISABLE_IRQ != 1
+# error Value of IRQS_DISABLED used to set PT_FLAGS_DISABLE_IRQ; fix
+#endif
+1:
+ .ifnc \function,handle_syscall
+ /* Record the fact that we saved the caller-save registers above. */
+ ori r32, r32, PT_FLAGS_CALLER_SAVES
+ .endif
+ st r21, r32
+
+#ifdef __COLLECT_LINKER_FEEDBACK__
+ /*
+ * Notify the feedback routines that we were in the
+ * appropriate fixed interrupt vector area. Note that we
+ * still have ICS set at this point, so we can't invoke any
+ * atomic operations or we will panic. The feedback
+ * routines internally preserve r0..r10 and r30 up.
+ */
+ .ifnc \function,handle_syscall
+ shli r20, r1, 5
+ .else
+ moveli r20, INT_SWINT_1 << 5
+ .endif
+ moveli r21, hw2_last(intvec_feedback)
+ shl16insli r21, r21, hw1(intvec_feedback)
+ shl16insli r21, r21, hw0(intvec_feedback)
+ add r20, r20, r21
+ jalr r20
+
+ /* And now notify the feedback routines that we are here. */
+ FEEDBACK_ENTER(\function)
+#endif
+
+ /*
+ * we've captured enough state to the stack (including in
+ * particular our EX_CONTEXT state) that we can now release
+ * the interrupt critical section and replace it with our
+ * standard "interrupts disabled" mask value. This allows
+ * synchronous interrupts (and profile interrupts) to punch
+ * through from this point onwards.
+ */
+ .ifc \function,handle_nmi
+ IRQ_DISABLE_ALL(r20)
+ .else
+ IRQ_DISABLE(r20, r21)
+ .endif
+ mtspr INTERRUPT_CRITICAL_SECTION, zero
+
+ /*
+ * Prepare the first 256 stack bytes to be rapidly accessible
+ * without having to fetch the background data.
+ */
+ addi r52, sp, -64
+ {
+ wh64 r52
+ addi r52, r52, -64
+ }
+ {
+ wh64 r52
+ addi r52, r52, -64
+ }
+ {
+ wh64 r52
+ addi r52, r52, -64
+ }
+ wh64 r52
+
+#ifdef CONFIG_TRACE_IRQFLAGS
+ .ifnc \function,handle_nmi
+ /*
+ * We finally have enough state set up to notify the irq
+ * tracing code that irqs were disabled on entry to the handler.
+ * The TRACE_IRQS_OFF call clobbers registers r0-r29.
+ * For syscalls, we already have the register state saved away
+ * on the stack, so we don't bother to do any register saves here,
+ * and later we pop the registers back off the kernel stack.
+ * For interrupt handlers, save r0-r3 in callee-saved registers.
+ */
+ .ifnc \function,handle_syscall
+ { move r30, r0; move r31, r1 }
+ { move r32, r2; move r33, r3 }
+ .endif
+ TRACE_IRQS_OFF
+ .ifnc \function,handle_syscall
+ { move r0, r30; move r1, r31 }
+ { move r2, r32; move r3, r33 }
+ .endif
+ .endif
+#endif
+
+ .endm
+
+ /*
+ * Redispatch a downcall.
+ */
+ .macro dc_dispatch vecnum, vecname
+ .org (\vecnum << 8)
+intvec_\vecname:
+ j hv_downcall_dispatch
+ ENDPROC(intvec_\vecname)
+ .endm
+
+ /*
+ * Common code for most interrupts. The C function we're eventually
+ * going to is in r0, and the faultnum is in r1; the original
+ * values for those registers are on the stack.
+ */
+ .pushsection .text.handle_interrupt,"ax"
+handle_interrupt:
+ finish_interrupt_save handle_interrupt
+
+ /* Jump to the C routine; it should enable irqs as soon as possible. */
+ {
+ jalr r0
+ PTREGS_PTR(r0, PTREGS_OFFSET_BASE)
+ }
+ FEEDBACK_REENTER(handle_interrupt)
+ {
+ movei r30, 0 /* not an NMI */
+ j interrupt_return
+ }
+ STD_ENDPROC(handle_interrupt)
+
+/*
+ * This routine takes a boolean in r30 indicating if this is an NMI.
+ * If so, we also expect a boolean in r31 indicating whether to
+ * re-enable the oprofile interrupts.
+ */
+STD_ENTRY(interrupt_return)
+ /* If we're resuming to kernel space, don't check thread flags. */
+ {
+ bnez r30, .Lrestore_all /* NMIs don't special-case user-space */
+ PTREGS_PTR(r29, PTREGS_OFFSET_EX1)
+ }
+ ld r29, r29
+ andi r29, r29, SPR_EX_CONTEXT_1_1__PL_MASK /* mask off ICS */
+ {
+ beqzt r29, .Lresume_userspace
+ PTREGS_PTR(r29, PTREGS_OFFSET_PC)
+ }
+
+ /* If we're resuming to _cpu_idle_nap, bump PC forward by 8. */
+ moveli r27, hw2_last(_cpu_idle_nap)
+ {
+ ld r28, r29
+ shl16insli r27, r27, hw1(_cpu_idle_nap)
+ }
+ {
+ shl16insli r27, r27, hw0(_cpu_idle_nap)
+ }
+ {
+ cmpeq r27, r27, r28
+ }
+ {
+ blbc r27, .Lrestore_all
+ addi r28, r28, 8
+ }
+ st r29, r28
+ j .Lrestore_all
+
+.Lresume_userspace:
+ FEEDBACK_REENTER(interrupt_return)
+
+ /*
+ * Disable interrupts so as to make sure we don't
+ * miss an interrupt that sets any of the thread flags (like
+ * need_resched or sigpending) between sampling and the iret.
+ * Routines like schedule() or do_signal() may re-enable
+ * interrupts before returning.
+ */
+ IRQ_DISABLE(r20, r21)
+ TRACE_IRQS_OFF /* Note: clobbers registers r0-r29 */
+
+ /* Get base of stack in r32; note r30/31 are used as arguments here. */
+ GET_THREAD_INFO(r32)
+
+
+ /* Check to see if there is any work to do before returning to user. */
+ {
+ addi r29, r32, THREAD_INFO_FLAGS_OFFSET
+ moveli r1, hw1_last(_TIF_ALLWORK_MASK)
+ }
+ {
+ ld r29, r29
+ shl16insli r1, r1, hw0(_TIF_ALLWORK_MASK)
+ }
+ and r1, r29, r1
+ beqzt r1, .Lrestore_all
+
+ /*
+ * Make sure we have all the registers saved for signal
+ * handling or single-step. Call out to C code to figure out
+ * exactly what we need to do for each flag bit, then if
+ * necessary, reload the flags and recheck.
+ */
+ push_extra_callee_saves r0
+ {
+ PTREGS_PTR(r0, PTREGS_OFFSET_BASE)
+ jal do_work_pending
+ }
+ bnez r0, .Lresume_userspace
+
+ /*
+ * In the NMI case we
+ * omit the call to single_process_check_nohz, which normally checks
+ * to see if we should start or stop the scheduler tick, because
+ * we can't call arbitrary Linux code from an NMI context.
+ * We always call the homecache TLB deferral code to re-trigger
+ * the deferral mechanism.
+ *
+ * The other chunk of responsibility this code has is to reset the
+ * interrupt masks appropriately to reset irqs and NMIs. We have
+ * to call TRACE_IRQS_OFF and TRACE_IRQS_ON to support all the
+ * lockdep-type stuff, but we can't set ICS until afterwards, since
+ * ICS can only be used in very tight chunks of code to avoid
+ * tripping over various assertions that it is off.
+ */
+.Lrestore_all:
+ PTREGS_PTR(r0, PTREGS_OFFSET_EX1)
+ {
+ ld r0, r0
+ PTREGS_PTR(r32, PTREGS_OFFSET_FLAGS)
+ }
+ {
+ andi r0, r0, SPR_EX_CONTEXT_1_1__PL_MASK
+ ld r32, r32
+ }
+ bnez r0, 1f
+ j 2f
+#if PT_FLAGS_DISABLE_IRQ != 1
+# error Assuming PT_FLAGS_DISABLE_IRQ == 1 so we can use blbct below
+#endif
+1: blbct r32, 2f
+ IRQ_DISABLE(r20,r21)
+ TRACE_IRQS_OFF
+ movei r0, 1
+ mtspr INTERRUPT_CRITICAL_SECTION, r0
+ beqzt r30, .Lrestore_regs
+ j 3f
+2: TRACE_IRQS_ON
+ movei r0, 1
+ mtspr INTERRUPT_CRITICAL_SECTION, r0
+ IRQ_ENABLE(r20, r21)
+ beqzt r30, .Lrestore_regs
+3:
+
+
+ /*
+ * We now commit to returning from this interrupt, since we will be
+ * doing things like setting EX_CONTEXT SPRs and unwinding the stack
+ * frame. No calls should be made to any other code after this point.
+ * This code should only be entered with ICS set.
+ * r32 must still be set to ptregs.flags.
+ * We launch loads to each cache line separately first, so we can
+ * get some parallelism out of the memory subsystem.
+ * We start zeroing caller-saved registers throughout, since
+ * that will save some cycles if this turns out to be a syscall.
+ */
+.Lrestore_regs:
+ FEEDBACK_REENTER(interrupt_return) /* called from elsewhere */
+
+ /*
+ * Rotate so we have one high bit and one low bit to test.
+ * - low bit says whether to restore all the callee-saved registers,
+ * or just r30-r33, and r52 up.
+ * - high bit (i.e. sign bit) says whether to restore all the
+ * caller-saved registers, or just r0.
+ */
+#if PT_FLAGS_CALLER_SAVES != 2 || PT_FLAGS_RESTORE_REGS != 4
+# error Rotate trick does not work :-)
+#endif
+ {
+ rotli r20, r32, 62
+ PTREGS_PTR(sp, PTREGS_OFFSET_REG(0))
+ }
+
+ /*
+ * Load cache lines 0, 4, 6 and 7, in that order, then use
+ * the last loaded value, which makes it likely that the other
+ * cache lines have also loaded, at which point we should be
+ * able to safely read all the remaining words on those cache
+ * lines without waiting for the memory subsystem.
+ */
+ pop_reg r0, sp, PTREGS_OFFSET_REG(30) - PTREGS_OFFSET_REG(0)
+ pop_reg r30, sp, PTREGS_OFFSET_REG(52) - PTREGS_OFFSET_REG(30)
+ pop_reg_zero r52, r3, sp, PTREGS_OFFSET_CMPEXCH - PTREGS_OFFSET_REG(52)
+ pop_reg_zero r21, r27, sp, PTREGS_OFFSET_EX1 - PTREGS_OFFSET_CMPEXCH
+ pop_reg_zero lr, r2, sp, PTREGS_OFFSET_PC - PTREGS_OFFSET_EX1
+ {
+ mtspr CMPEXCH_VALUE, r21
+ move r4, zero
+ }
+ pop_reg r21, sp, PTREGS_OFFSET_REG(31) - PTREGS_OFFSET_PC
+ {
+ mtspr SPR_EX_CONTEXT_K_1, lr
+ andi lr, lr, SPR_EX_CONTEXT_1_1__PL_MASK /* mask off ICS */
+ }
+ {
+ mtspr SPR_EX_CONTEXT_K_0, r21
+ move r5, zero
+ }
+
+ /* Restore callee-saveds that we actually use. */
+ pop_reg_zero r31, r6
+ pop_reg_zero r32, r7
+ pop_reg_zero r33, r8, sp, PTREGS_OFFSET_REG(29) - PTREGS_OFFSET_REG(33)
+
+ /*
+ * If we modified other callee-saveds, restore them now.
+ * This is rare, but could be via ptrace or signal handler.
+ */
+ {
+ move r9, zero
+ blbs r20, .Lrestore_callees
+ }
+.Lcontinue_restore_regs:
+
+ /* Check if we're returning from a syscall. */
+ {
+ move r10, zero
+ bltzt r20, 1f /* no, so go restore callee-save registers */
+ }
+
+ /*
+ * Check if we're returning to userspace.
+ * Note that if we're not, we don't worry about zeroing everything.
+ */
+ {
+ addli sp, sp, PTREGS_OFFSET_LR - PTREGS_OFFSET_REG(29)
+ bnez lr, .Lkernel_return
+ }
+
+ /*
+ * On return from syscall, we've restored r0 from pt_regs, but we
+ * clear the remainder of the caller-saved registers. We could
+ * restore the syscall arguments, but there's not much point,
+ * and it ensures user programs aren't trying to use the
+ * caller-saves if we clear them, as well as avoiding leaking
+ * kernel pointers into userspace.
+ */
+ pop_reg_zero lr, r11, sp, PTREGS_OFFSET_TP - PTREGS_OFFSET_LR
+ pop_reg_zero tp, r12, sp, PTREGS_OFFSET_SP - PTREGS_OFFSET_TP
+ {
+ ld sp, sp
+ move r13, zero
+ move r14, zero
+ }
+ { move r15, zero; move r16, zero }
+ { move r17, zero; move r18, zero }
+ { move r19, zero; move r20, zero }
+ { move r21, zero; move r22, zero }
+ { move r23, zero; move r24, zero }
+ { move r25, zero; move r26, zero }
+
+ /* Set r1 to errno if we are returning an error, otherwise zero. */
+ {
+ moveli r29, 4096
+ sub r1, zero, r0
+ }
+ {
+ move r28, zero
+ cmpltu r29, r1, r29
+ }
+ {
+ mnz r1, r29, r1
+ move r29, zero
+ }
+ iret
+
+ /*
+ * Not a syscall, so restore caller-saved registers.
+ * First kick off loads for cache lines 1-3, which we're touching
+ * for the first time here.
+ */
+ .align 64
+1: pop_reg r29, sp, PTREGS_OFFSET_REG(21) - PTREGS_OFFSET_REG(29)
+ pop_reg r21, sp, PTREGS_OFFSET_REG(13) - PTREGS_OFFSET_REG(21)
+ pop_reg r13, sp, PTREGS_OFFSET_REG(1) - PTREGS_OFFSET_REG(13)
+ pop_reg r1
+ pop_reg r2
+ pop_reg r3
+ pop_reg r4
+ pop_reg r5
+ pop_reg r6
+ pop_reg r7
+ pop_reg r8
+ pop_reg r9
+ pop_reg r10
+ pop_reg r11
+ pop_reg r12, sp, 16
+ /* r13 already restored above */
+ pop_reg r14
+ pop_reg r15
+ pop_reg r16
+ pop_reg r17
+ pop_reg r18
+ pop_reg r19
+ pop_reg r20, sp, 16
+ /* r21 already restored above */
+ pop_reg r22
+ pop_reg r23
+ pop_reg r24
+ pop_reg r25
+ pop_reg r26
+ pop_reg r27
+ pop_reg r28, sp, PTREGS_OFFSET_LR - PTREGS_OFFSET_REG(28)
+ /* r29 already restored above */
+ bnez lr, .Lkernel_return
+ pop_reg lr, sp, PTREGS_OFFSET_TP - PTREGS_OFFSET_LR
+ pop_reg tp, sp, PTREGS_OFFSET_SP - PTREGS_OFFSET_TP
+ ld sp, sp
+ iret
+
+ /*
+ * We can't restore tp when in kernel mode, since a thread might
+ * have migrated from another cpu and brought a stale tp value.
+ */
+.Lkernel_return:
+ pop_reg lr, sp, PTREGS_OFFSET_SP - PTREGS_OFFSET_LR
+ ld sp, sp
+ iret
+
+ /* Restore callee-saved registers from r34 to r51. */
+.Lrestore_callees:
+ addli sp, sp, PTREGS_OFFSET_REG(34) - PTREGS_OFFSET_REG(29)
+ pop_reg r34
+ pop_reg r35
+ pop_reg r36
+ pop_reg r37
+ pop_reg r38
+ pop_reg r39
+ pop_reg r40
+ pop_reg r41
+ pop_reg r42
+ pop_reg r43
+ pop_reg r44
+ pop_reg r45
+ pop_reg r46
+ pop_reg r47
+ pop_reg r48
+ pop_reg r49
+ pop_reg r50
+ pop_reg r51, sp, PTREGS_OFFSET_REG(29) - PTREGS_OFFSET_REG(51)
+ j .Lcontinue_restore_regs
+ STD_ENDPROC(interrupt_return)
+
+ /*
+ * "NMI" interrupts mask ALL interrupts before calling the
+ * handler, and don't check thread flags, etc., on the way
+ * back out. In general, the only things we do here for NMIs
+ * are register save/restore and dataplane kernel-TLB management.
+ * We don't (for example) deal with start/stop of the sched tick.
+ */
+ .pushsection .text.handle_nmi,"ax"
+handle_nmi:
+ finish_interrupt_save handle_nmi
+ {
+ jalr r0
+ PTREGS_PTR(r0, PTREGS_OFFSET_BASE)
+ }
+ FEEDBACK_REENTER(handle_nmi)
+ {
+ movei r30, 1
+ move r31, r0
+ }
+ j interrupt_return
+ STD_ENDPROC(handle_nmi)
+
+ /*
+ * Parallel code for syscalls to handle_interrupt.
+ */
+ .pushsection .text.handle_syscall,"ax"
+handle_syscall:
+ finish_interrupt_save handle_syscall
+
+ /* Enable irqs. */
+ TRACE_IRQS_ON
+ IRQ_ENABLE(r20, r21)
+
+ /* Bump the counter for syscalls made on this tile. */
+ moveli r20, hw2_last(irq_stat + IRQ_CPUSTAT_SYSCALL_COUNT_OFFSET)
+ shl16insli r20, r20, hw1(irq_stat + IRQ_CPUSTAT_SYSCALL_COUNT_OFFSET)
+ shl16insli r20, r20, hw0(irq_stat + IRQ_CPUSTAT_SYSCALL_COUNT_OFFSET)
+ add r20, r20, tp
+ ld4s r21, r20
+ addi r21, r21, 1
+ st4 r20, r21
+
+ /* Trace syscalls, if requested. */
+ GET_THREAD_INFO(r31)
+ addi r31, r31, THREAD_INFO_FLAGS_OFFSET
+ ld r30, r31
+ andi r30, r30, _TIF_SYSCALL_TRACE
+ {
+ addi r30, r31, THREAD_INFO_STATUS_OFFSET - THREAD_INFO_FLAGS_OFFSET
+ beqzt r30, .Lrestore_syscall_regs
+ }
+ jal do_syscall_trace
+ FEEDBACK_REENTER(handle_syscall)
+
+ /*
+ * We always reload our registers from the stack at this
+ * point. They might be valid, if we didn't build with
+ * TRACE_IRQFLAGS, and this isn't a dataplane tile, and we're not
+ * doing syscall tracing, but there are enough cases now that it
+ * seems simplest just to do the reload unconditionally.
+ */
+.Lrestore_syscall_regs:
+ {
+ ld r30, r30
+ PTREGS_PTR(r11, PTREGS_OFFSET_REG(0))
+ }
+ pop_reg r0, r11
+ pop_reg r1, r11
+ pop_reg r2, r11
+ pop_reg r3, r11
+ pop_reg r4, r11
+ pop_reg r5, r11, PTREGS_OFFSET_SYSCALL - PTREGS_OFFSET_REG(5)
+ {
+ ld TREG_SYSCALL_NR_NAME, r11
+ moveli r21, __NR_syscalls
+ }
+
+ /* Ensure that the syscall number is within the legal range. */
+ {
+ moveli r20, hw2(sys_call_table)
+ blbs r30, .Lcompat_syscall
+ }
+ {
+ cmpltu r21, TREG_SYSCALL_NR_NAME, r21
+ shl16insli r20, r20, hw1(sys_call_table)
+ }
+ {
+ blbc r21, .Linvalid_syscall
+ shl16insli r20, r20, hw0(sys_call_table)
+ }
+.Lload_syscall_pointer:
+ shl3add r20, TREG_SYSCALL_NR_NAME, r20
+ ld r20, r20
+
+ /* Jump to syscall handler. */
+ jalr r20
+.Lhandle_syscall_link: /* value of "lr" after "jalr r20" above */
+
+ /*
+ * Write our r0 onto the stack so it gets restored instead
+ * of whatever the user had there before.
+ * In compat mode, sign-extend r0 before storing it.
+ */
+ {
+ PTREGS_PTR(r29, PTREGS_OFFSET_REG(0))
+ blbct r30, 1f
+ }
+ addxi r0, r0, 0
+1: st r29, r0
+
+.Lsyscall_sigreturn_skip:
+ FEEDBACK_REENTER(handle_syscall)
+
+ /* Do syscall trace again, if requested. */
+ ld r30, r31
+ andi r30, r30, _TIF_SYSCALL_TRACE
+ beqzt r30, 1f
+ jal do_syscall_trace
+ FEEDBACK_REENTER(handle_syscall)
+1: j .Lresume_userspace /* jump into middle of interrupt_return */
+
+.Lcompat_syscall:
+ /*
+ * Load the base of the compat syscall table in r20, and
+ * range-check the syscall number (duplicated from 64-bit path).
+ * Sign-extend all the user's passed arguments to make them consistent.
+ * Also save the original "r(n)" values away in "r(11+n)" in
+ * case the syscall table entry wants to validate them.
+ */
+ moveli r20, hw2(compat_sys_call_table)
+ {
+ cmpltu r21, TREG_SYSCALL_NR_NAME, r21
+ shl16insli r20, r20, hw1(compat_sys_call_table)
+ }
+ {
+ blbc r21, .Linvalid_syscall
+ shl16insli r20, r20, hw0(compat_sys_call_table)
+ }
+ { move r11, r0; addxi r0, r0, 0 }
+ { move r12, r1; addxi r1, r1, 0 }
+ { move r13, r2; addxi r2, r2, 0 }
+ { move r14, r3; addxi r3, r3, 0 }
+ { move r15, r4; addxi r4, r4, 0 }
+ { move r16, r5; addxi r5, r5, 0 }
+ j .Lload_syscall_pointer
+
+.Linvalid_syscall:
+ /* Report an invalid syscall back to the user program */
+ {
+ PTREGS_PTR(r29, PTREGS_OFFSET_REG(0))
+ movei r28, -ENOSYS
+ }
+ st r29, r28
+ j .Lresume_userspace /* jump into middle of interrupt_return */
+ STD_ENDPROC(handle_syscall)
+
+ /* Return the address for oprofile to suppress in backtraces. */
+STD_ENTRY_SECTION(handle_syscall_link_address, .text.handle_syscall)
+ lnk r0
+ {
+ addli r0, r0, .Lhandle_syscall_link - .
+ jrp lr
+ }
+ STD_ENDPROC(handle_syscall_link_address)
+
+STD_ENTRY(ret_from_fork)
+ jal sim_notify_fork
+ jal schedule_tail
+ FEEDBACK_REENTER(ret_from_fork)
+ j .Lresume_userspace
+ STD_ENDPROC(ret_from_fork)
+
+/* Various stub interrupt handlers and syscall handlers */
+
+STD_ENTRY_LOCAL(_kernel_double_fault)
+ mfspr r1, SPR_EX_CONTEXT_K_0
+ move r2, lr
+ move r3, sp
+ move r4, r52
+ addi sp, sp, -C_ABI_SAVE_AREA_SIZE
+ j kernel_double_fault
+ STD_ENDPROC(_kernel_double_fault)
+
+STD_ENTRY_LOCAL(bad_intr)
+ mfspr r2, SPR_EX_CONTEXT_K_0
+ panic "Unhandled interrupt %#x: PC %#lx"
+ STD_ENDPROC(bad_intr)
+
+/* Put address of pt_regs in reg and jump. */
+#define PTREGS_SYSCALL(x, reg) \
+ STD_ENTRY(_##x); \
+ { \
+ PTREGS_PTR(reg, PTREGS_OFFSET_BASE); \
+ j x \
+ }; \
+ STD_ENDPROC(_##x)
+
+/*
+ * Special-case sigreturn to not write r0 to the stack on return.
+ * This is technically more efficient, but it also avoids difficulties
+ * in the 64-bit OS when handling 32-bit compat code, since we must not
+ * sign-extend r0 for the sigreturn return-value case.
+ */
+#define PTREGS_SYSCALL_SIGRETURN(x, reg) \
+ STD_ENTRY(_##x); \
+ addli lr, lr, .Lsyscall_sigreturn_skip - .Lhandle_syscall_link; \
+ { \
+ PTREGS_PTR(reg, PTREGS_OFFSET_BASE); \
+ j x \
+ }; \
+ STD_ENDPROC(_##x)
+
+PTREGS_SYSCALL(sys_execve, r3)
+PTREGS_SYSCALL(sys_sigaltstack, r2)
+PTREGS_SYSCALL_SIGRETURN(sys_rt_sigreturn, r0)
+#ifdef CONFIG_COMPAT
+PTREGS_SYSCALL(compat_sys_execve, r3)
+PTREGS_SYSCALL(compat_sys_sigaltstack, r2)
+PTREGS_SYSCALL_SIGRETURN(compat_sys_rt_sigreturn, r0)
+#endif
+
+/* Save additional callee-saves to pt_regs, put address in r4 and jump. */
+STD_ENTRY(_sys_clone)
+ push_extra_callee_saves r4
+ j sys_clone
+ STD_ENDPROC(_sys_clone)
+
+/* The single-step support may need to read all the registers. */
+int_unalign:
+ push_extra_callee_saves r0
+ j do_trap
+
+/* Include .intrpt1 array of interrupt vectors */
+ .section ".intrpt1", "ax"
+
+#define op_handle_perf_interrupt bad_intr
+#define op_handle_aux_perf_interrupt bad_intr
+
+#ifndef CONFIG_HARDWALL
+#define do_hardwall_trap bad_intr
+#endif
+
+ int_hand INT_MEM_ERROR, MEM_ERROR, bad_intr
+ int_hand INT_SINGLE_STEP_3, SINGLE_STEP_3, bad_intr
+#if CONFIG_KERNEL_PL == 2
+ int_hand INT_SINGLE_STEP_2, SINGLE_STEP_2, gx_singlestep_handle
+ int_hand INT_SINGLE_STEP_1, SINGLE_STEP_1, bad_intr
+#else
+ int_hand INT_SINGLE_STEP_2, SINGLE_STEP_2, bad_intr
+ int_hand INT_SINGLE_STEP_1, SINGLE_STEP_1, gx_singlestep_handle
+#endif
+ int_hand INT_SINGLE_STEP_0, SINGLE_STEP_0, bad_intr
+ int_hand INT_IDN_COMPLETE, IDN_COMPLETE, bad_intr
+ int_hand INT_UDN_COMPLETE, UDN_COMPLETE, bad_intr
+ int_hand INT_ITLB_MISS, ITLB_MISS, do_page_fault
+ int_hand INT_ILL, ILL, do_trap
+ int_hand INT_GPV, GPV, do_trap
+ int_hand INT_IDN_ACCESS, IDN_ACCESS, do_trap
+ int_hand INT_UDN_ACCESS, UDN_ACCESS, do_trap
+ int_hand INT_SWINT_3, SWINT_3, do_trap
+ int_hand INT_SWINT_2, SWINT_2, do_trap
+ int_hand INT_SWINT_1, SWINT_1, SYSCALL, handle_syscall
+ int_hand INT_SWINT_0, SWINT_0, do_trap
+ int_hand INT_ILL_TRANS, ILL_TRANS, do_trap
+ int_hand INT_UNALIGN_DATA, UNALIGN_DATA, int_unalign
+ int_hand INT_DTLB_MISS, DTLB_MISS, do_page_fault
+ int_hand INT_DTLB_ACCESS, DTLB_ACCESS, do_page_fault
+ int_hand INT_IDN_FIREWALL, IDN_FIREWALL, bad_intr
+ int_hand INT_UDN_FIREWALL, UDN_FIREWALL, do_hardwall_trap
+ int_hand INT_TILE_TIMER, TILE_TIMER, do_timer_interrupt
+ int_hand INT_IDN_TIMER, IDN_TIMER, bad_intr
+ int_hand INT_UDN_TIMER, UDN_TIMER, bad_intr
+ int_hand INT_IDN_AVAIL, IDN_AVAIL, bad_intr
+ int_hand INT_UDN_AVAIL, UDN_AVAIL, bad_intr
+ int_hand INT_IPI_3, IPI_3, bad_intr
+#if CONFIG_KERNEL_PL == 2
+ int_hand INT_IPI_2, IPI_2, tile_dev_intr
+ int_hand INT_IPI_1, IPI_1, bad_intr
+#else
+ int_hand INT_IPI_2, IPI_2, bad_intr
+ int_hand INT_IPI_1, IPI_1, tile_dev_intr
+#endif
+ int_hand INT_IPI_0, IPI_0, bad_intr
+ int_hand INT_PERF_COUNT, PERF_COUNT, \
+ op_handle_perf_interrupt, handle_nmi
+ int_hand INT_AUX_PERF_COUNT, AUX_PERF_COUNT, \
+ op_handle_perf_interrupt, handle_nmi
+ int_hand INT_INTCTRL_3, INTCTRL_3, bad_intr
+#if CONFIG_KERNEL_PL == 2
+ dc_dispatch INT_INTCTRL_2, INTCTRL_2
+ int_hand INT_INTCTRL_1, INTCTRL_1, bad_intr
+#else
+ int_hand INT_INTCTRL_2, INTCTRL_2, bad_intr
+ dc_dispatch INT_INTCTRL_1, INTCTRL_1
+#endif
+ int_hand INT_INTCTRL_0, INTCTRL_0, bad_intr
+ int_hand INT_MESSAGE_RCV_DWNCL, MESSAGE_RCV_DWNCL, \
+ hv_message_intr
+ int_hand INT_DEV_INTR_DWNCL, DEV_INTR_DWNCL, bad_intr
+ int_hand INT_I_ASID, I_ASID, bad_intr
+ int_hand INT_D_ASID, D_ASID, bad_intr
+ int_hand INT_DOUBLE_FAULT, DOUBLE_FAULT, do_trap
+
+ /* Synthetic interrupt delivered only by the simulator */
+ int_hand INT_BREAKPOINT, BREAKPOINT, do_breakpoint
diff --git a/arch/tile/kernel/module.c b/arch/tile/kernel/module.c
index e2ab82b..f68df69 100644
--- a/arch/tile/kernel/module.c
+++ b/arch/tile/kernel/module.c
@@ -22,6 +22,7 @@
#include <linux/kernel.h>
#include <asm/opcode-tile.h>
#include <asm/pgtable.h>
+#include <asm/homecache.h>
#ifdef __tilegx__
# define Elf_Rela Elf64_Rela
@@ -86,8 +87,13 @@
void module_free(struct module *mod, void *module_region)
{
vfree(module_region);
+
+ /* Globally flush the L1 icache. */
+ flush_remote(0, HV_FLUSH_EVICT_L1I, cpu_online_mask,
+ 0, 0, 0, NULL, NULL, 0);
+
/*
- * FIXME: If module_region == mod->init_region, trim exception
+ * FIXME: If module_region == mod->module_init, trim exception
* table entries.
*/
}
diff --git a/arch/tile/kernel/pci-dma.c b/arch/tile/kernel/pci-dma.c
index 658752b2..658f2ce 100644
--- a/arch/tile/kernel/pci-dma.c
+++ b/arch/tile/kernel/pci-dma.c
@@ -244,7 +244,7 @@
* dma_alloc_noncoherent() returns non-cacheable memory, so there's no
* need to do any flushing here.
*/
-void dma_cache_sync(void *vaddr, size_t size,
+void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
enum dma_data_direction direction)
{
}
diff --git a/arch/tile/kernel/pci.c b/arch/tile/kernel/pci.c
index ea38f0c..6d4cb5d 100644
--- a/arch/tile/kernel/pci.c
+++ b/arch/tile/kernel/pci.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2010 Tilera Corporation. All Rights Reserved.
+ * Copyright 2011 Tilera Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
@@ -59,6 +59,7 @@
static struct pci_controller controllers[TILE_NUM_PCIE];
static int num_controllers;
+static int pci_scan_flags[TILE_NUM_PCIE];
static struct pci_ops tile_cfg_ops;
@@ -79,7 +80,7 @@
* controller_id is the controller number, config type is 0 or 1 for
* config0 or config1 operations.
*/
-static int __init tile_pcie_open(int controller_id, int config_type)
+static int __devinit tile_pcie_open(int controller_id, int config_type)
{
char filename[32];
int fd;
@@ -95,7 +96,7 @@
/*
* Get the IRQ numbers from the HV and set up the handlers for them.
*/
-static int __init tile_init_irqs(int controller_id,
+static int __devinit tile_init_irqs(int controller_id,
struct pci_controller *controller)
{
char filename[32];
@@ -139,71 +140,74 @@
*
* Returns the number of controllers discovered.
*/
-int __init tile_pci_init(void)
+int __devinit tile_pci_init(void)
{
int i;
pr_info("PCI: Searching for controllers...\n");
+ /* Re-init number of PCIe controllers to support hot-plug feature. */
+ num_controllers = 0;
+
/* Do any configuration we need before using the PCIe */
for (i = 0; i < TILE_NUM_PCIE; i++) {
- int hv_cfg_fd0 = -1;
- int hv_cfg_fd1 = -1;
- int hv_mem_fd = -1;
- char name[32];
- struct pci_controller *controller;
-
/*
- * Open the fd to the HV. If it fails then this
- * device doesn't exist.
+ * To see whether we need a real config op based on
+ * the results of pcibios_init(), to support PCIe hot-plug.
*/
- hv_cfg_fd0 = tile_pcie_open(i, 0);
- if (hv_cfg_fd0 < 0)
+ if (pci_scan_flags[i] == 0) {
+ int hv_cfg_fd0 = -1;
+ int hv_cfg_fd1 = -1;
+ int hv_mem_fd = -1;
+ char name[32];
+ struct pci_controller *controller;
+
+ /*
+ * Open the fd to the HV. If it fails then this
+ * device doesn't exist.
+ */
+ hv_cfg_fd0 = tile_pcie_open(i, 0);
+ if (hv_cfg_fd0 < 0)
+ continue;
+ hv_cfg_fd1 = tile_pcie_open(i, 1);
+ if (hv_cfg_fd1 < 0) {
+ pr_err("PCI: Couldn't open config fd to HV "
+ "for controller %d\n", i);
+ goto err_cont;
+ }
+
+ sprintf(name, "pcie/%d/mem", i);
+ hv_mem_fd = hv_dev_open((HV_VirtAddr)name, 0);
+ if (hv_mem_fd < 0) {
+ pr_err("PCI: Could not open mem fd to HV!\n");
+ goto err_cont;
+ }
+
+ pr_info("PCI: Found PCI controller #%d\n", i);
+
+ controller = &controllers[i];
+
+ controller->index = i;
+ controller->hv_cfg_fd[0] = hv_cfg_fd0;
+ controller->hv_cfg_fd[1] = hv_cfg_fd1;
+ controller->hv_mem_fd = hv_mem_fd;
+ controller->first_busno = 0;
+ controller->last_busno = 0xff;
+ controller->ops = &tile_cfg_ops;
+
+ num_controllers++;
continue;
- hv_cfg_fd1 = tile_pcie_open(i, 1);
- if (hv_cfg_fd1 < 0) {
- pr_err("PCI: Couldn't open config fd to HV "
- "for controller %d\n", i);
- goto err_cont;
- }
-
- sprintf(name, "pcie/%d/mem", i);
- hv_mem_fd = hv_dev_open((HV_VirtAddr)name, 0);
- if (hv_mem_fd < 0) {
- pr_err("PCI: Could not open mem fd to HV!\n");
- goto err_cont;
- }
-
- pr_info("PCI: Found PCI controller #%d\n", i);
-
- controller = &controllers[num_controllers];
-
- if (tile_init_irqs(i, controller)) {
- pr_err("PCI: Could not initialize "
- "IRQs, aborting.\n");
- goto err_cont;
- }
-
- controller->index = num_controllers;
- controller->hv_cfg_fd[0] = hv_cfg_fd0;
- controller->hv_cfg_fd[1] = hv_cfg_fd1;
- controller->hv_mem_fd = hv_mem_fd;
- controller->first_busno = 0;
- controller->last_busno = 0xff;
- controller->ops = &tile_cfg_ops;
-
- num_controllers++;
- continue;
err_cont:
- if (hv_cfg_fd0 >= 0)
- hv_dev_close(hv_cfg_fd0);
- if (hv_cfg_fd1 >= 0)
- hv_dev_close(hv_cfg_fd1);
- if (hv_mem_fd >= 0)
- hv_dev_close(hv_mem_fd);
- continue;
+ if (hv_cfg_fd0 >= 0)
+ hv_dev_close(hv_cfg_fd0);
+ if (hv_cfg_fd1 >= 0)
+ hv_dev_close(hv_cfg_fd1);
+ if (hv_mem_fd >= 0)
+ hv_dev_close(hv_mem_fd);
+ continue;
+ }
}
/*
@@ -232,7 +236,7 @@
}
-static void __init fixup_read_and_payload_sizes(void)
+static void __devinit fixup_read_and_payload_sizes(void)
{
struct pci_dev *dev = NULL;
int smallest_max_payload = 0x1; /* Tile maxes out at 256 bytes. */
@@ -282,7 +286,7 @@
* The controllers have been set up by the time we get here, by a call to
* tile_pci_init.
*/
-static int __init pcibios_init(void)
+int __devinit pcibios_init(void)
{
int i;
@@ -296,25 +300,36 @@
mdelay(250);
/* Scan all of the recorded PCI controllers. */
- for (i = 0; i < num_controllers; i++) {
- struct pci_controller *controller = &controllers[i];
- struct pci_bus *bus;
-
- pr_info("PCI: initializing controller #%d\n", i);
-
+ for (i = 0; i < TILE_NUM_PCIE; i++) {
/*
- * This comes from the generic Linux PCI driver.
- *
- * It reads the PCI tree for this bus into the Linux
- * data structures.
- *
- * This is inlined in linux/pci.h and calls into
- * pci_scan_bus_parented() in probe.c.
+ * Do real pcibios init ops if the controller is initialized
+ * by tile_pci_init() successfully and not initialized by
+ * pcibios_init() yet to support PCIe hot-plug.
*/
- bus = pci_scan_bus(0, controller->ops, controller);
- controller->root_bus = bus;
- controller->last_busno = bus->subordinate;
+ if (pci_scan_flags[i] == 0 && controllers[i].ops != NULL) {
+ struct pci_controller *controller = &controllers[i];
+ struct pci_bus *bus;
+ if (tile_init_irqs(i, controller)) {
+ pr_err("PCI: Could not initialize IRQs\n");
+ continue;
+ }
+
+ pr_info("PCI: initializing controller #%d\n", i);
+
+ /*
+ * This comes from the generic Linux PCI driver.
+ *
+ * It reads the PCI tree for this bus into the Linux
+ * data structures.
+ *
+ * This is inlined in linux/pci.h and calls into
+ * pci_scan_bus_parented() in probe.c.
+ */
+ bus = pci_scan_bus(0, controller->ops, controller);
+ controller->root_bus = bus;
+ controller->last_busno = bus->subordinate;
+ }
}
/* Do machine dependent PCI interrupt routing */
@@ -326,34 +341,45 @@
* It allocates all of the resources (I/O memory, etc)
* associated with the devices read in above.
*/
-
pci_assign_unassigned_resources();
/* Configure the max_read_size and max_payload_size values. */
fixup_read_and_payload_sizes();
/* Record the I/O resources in the PCI controller structure. */
- for (i = 0; i < num_controllers; i++) {
- struct pci_bus *root_bus = controllers[i].root_bus;
- struct pci_bus *next_bus;
- struct pci_dev *dev;
+ for (i = 0; i < TILE_NUM_PCIE; i++) {
+ /*
+ * Do real pcibios init ops if the controller is initialized
+ * by tile_pci_init() successfully and not initialized by
+ * pcibios_init() yet to support PCIe hot-plug.
+ */
+ if (pci_scan_flags[i] == 0 && controllers[i].ops != NULL) {
+ struct pci_bus *root_bus = controllers[i].root_bus;
+ struct pci_bus *next_bus;
+ struct pci_dev *dev;
- list_for_each_entry(dev, &root_bus->devices, bus_list) {
- /* Find the PCI host controller, ie. the 1st bridge. */
- if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI &&
- (PCI_SLOT(dev->devfn) == 0)) {
- next_bus = dev->subordinate;
- controllers[i].mem_resources[0] =
- *next_bus->resource[0];
- controllers[i].mem_resources[1] =
- *next_bus->resource[1];
- controllers[i].mem_resources[2] =
- *next_bus->resource[2];
+ list_for_each_entry(dev, &root_bus->devices, bus_list) {
+ /*
+ * Find the PCI host controller, ie. the 1st
+ * bridge.
+ */
+ if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI &&
+ (PCI_SLOT(dev->devfn) == 0)) {
+ next_bus = dev->subordinate;
+ controllers[i].mem_resources[0] =
+ *next_bus->resource[0];
+ controllers[i].mem_resources[1] =
+ *next_bus->resource[1];
+ controllers[i].mem_resources[2] =
+ *next_bus->resource[2];
- break;
+ /* Setup flags. */
+ pci_scan_flags[i] = 1;
+
+ break;
+ }
}
}
-
}
return 0;
@@ -381,7 +407,7 @@
/*
* This is called from the generic Linux layer.
*/
-void __init pcibios_update_irq(struct pci_dev *dev, int irq)
+void __devinit pcibios_update_irq(struct pci_dev *dev, int irq)
{
pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
}
diff --git a/arch/tile/kernel/process.c b/arch/tile/kernel/process.c
index d006510..9c45d8b 100644
--- a/arch/tile/kernel/process.c
+++ b/arch/tile/kernel/process.c
@@ -25,10 +25,13 @@
#include <linux/hardirq.h>
#include <linux/syscalls.h>
#include <linux/kernel.h>
+#include <linux/tracehook.h>
+#include <linux/signal.h>
#include <asm/system.h>
#include <asm/stack.h>
#include <asm/homecache.h>
#include <asm/syscalls.h>
+#include <asm/traps.h>
#ifdef CONFIG_HARDWALL
#include <asm/hardwall.h>
#endif
@@ -546,6 +549,51 @@
return __switch_to(prev, next, next_current_ksp0(next));
}
+/*
+ * This routine is called on return from interrupt if any of the
+ * TIF_WORK_MASK flags are set in thread_info->flags. It is
+ * entered with interrupts disabled so we don't miss an event
+ * that modified the thread_info flags. If any flag is set, we
+ * handle it and return, and the calling assembly code will
+ * re-disable interrupts, reload the thread flags, and call back
+ * if more flags need to be handled.
+ *
+ * We return whether we need to check the thread_info flags again
+ * or not. Note that we don't clear TIF_SINGLESTEP here, so it's
+ * important that it be tested last, and then claim that we don't
+ * need to recheck the flags.
+ */
+int do_work_pending(struct pt_regs *regs, u32 thread_info_flags)
+{
+ if (thread_info_flags & _TIF_NEED_RESCHED) {
+ schedule();
+ return 1;
+ }
+#if CHIP_HAS_TILE_DMA() || CHIP_HAS_SN_PROC()
+ if (thread_info_flags & _TIF_ASYNC_TLB) {
+ do_async_page_fault(regs);
+ return 1;
+ }
+#endif
+ if (thread_info_flags & _TIF_SIGPENDING) {
+ do_signal(regs);
+ return 1;
+ }
+ if (thread_info_flags & _TIF_NOTIFY_RESUME) {
+ clear_thread_flag(TIF_NOTIFY_RESUME);
+ tracehook_notify_resume(regs);
+ if (current->replacement_session_keyring)
+ key_replace_session_keyring();
+ return 1;
+ }
+ if (thread_info_flags & _TIF_SINGLESTEP) {
+ if ((regs->ex1 & SPR_EX_CONTEXT_1_1__PL_MASK) == 0)
+ single_step_once(regs);
+ return 0;
+ }
+ panic("work_pending: bad flags %#x\n", thread_info_flags);
+}
+
/* Note there is an implicit fifth argument if (clone_flags & CLONE_SETTLS). */
SYSCALL_DEFINE5(clone, unsigned long, clone_flags, unsigned long, newsp,
void __user *, parent_tidptr, void __user *, child_tidptr,
@@ -582,8 +630,8 @@
#ifdef CONFIG_COMPAT
long compat_sys_execve(const char __user *path,
- const compat_uptr_t __user *argv,
- const compat_uptr_t __user *envp,
+ compat_uptr_t __user *argv,
+ compat_uptr_t __user *envp,
struct pt_regs *regs)
{
long error;
diff --git a/arch/tile/kernel/regs_64.S b/arch/tile/kernel/regs_64.S
new file mode 100644
index 0000000..f748c1e
--- /dev/null
+++ b/arch/tile/kernel/regs_64.S
@@ -0,0 +1,145 @@
+/*
+ * Copyright 2011 Tilera Corporation. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ * NON INFRINGEMENT. See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/linkage.h>
+#include <asm/system.h>
+#include <asm/ptrace.h>
+#include <asm/asm-offsets.h>
+#include <arch/spr_def.h>
+#include <asm/processor.h>
+
+/*
+ * See <asm/system.h>; called with prev and next task_struct pointers.
+ * "prev" is returned in r0 for _switch_to and also for ret_from_fork.
+ *
+ * We want to save pc/sp in "prev", and get the new pc/sp from "next".
+ * We also need to save all the callee-saved registers on the stack.
+ *
+ * Intel enables/disables access to the hardware cycle counter in
+ * seccomp (secure computing) environments if necessary, based on
+ * has_secure_computing(). We might want to do this at some point,
+ * though it would require virtualizing the other SPRs under WORLD_ACCESS.
+ *
+ * Since we're saving to the stack, we omit sp from this list.
+ * And for parallels with other architectures, we save lr separately,
+ * in the thread_struct itself (as the "pc" field).
+ *
+ * This code also needs to be aligned with process.c copy_thread()
+ */
+
+#if CALLEE_SAVED_REGS_COUNT != 24
+# error Mismatch between <asm/system.h> and kernel/entry.S
+#endif
+#define FRAME_SIZE ((2 + CALLEE_SAVED_REGS_COUNT) * 8)
+
+#define SAVE_REG(r) { st r12, r; addi r12, r12, 8 }
+#define LOAD_REG(r) { ld r, r12; addi r12, r12, 8 }
+#define FOR_EACH_CALLEE_SAVED_REG(f) \
+ f(r30); f(r31); \
+ f(r32); f(r33); f(r34); f(r35); f(r36); f(r37); f(r38); f(r39); \
+ f(r40); f(r41); f(r42); f(r43); f(r44); f(r45); f(r46); f(r47); \
+ f(r48); f(r49); f(r50); f(r51); f(r52);
+
+STD_ENTRY_SECTION(__switch_to, .sched.text)
+ {
+ move r10, sp
+ st sp, lr
+ }
+ {
+ addli r11, sp, -FRAME_SIZE + 8
+ addli sp, sp, -FRAME_SIZE
+ }
+ {
+ st r11, r10
+ addli r4, r1, TASK_STRUCT_THREAD_KSP_OFFSET
+ }
+ {
+ ld r13, r4 /* Load new sp to a temp register early. */
+ addi r12, sp, 16
+ }
+ FOR_EACH_CALLEE_SAVED_REG(SAVE_REG)
+ addli r3, r0, TASK_STRUCT_THREAD_KSP_OFFSET
+ {
+ st r3, sp
+ addli r3, r0, TASK_STRUCT_THREAD_PC_OFFSET
+ }
+ {
+ st r3, lr
+ addli r4, r1, TASK_STRUCT_THREAD_PC_OFFSET
+ }
+ {
+ ld lr, r4
+ addi r12, r13, 16
+ }
+ {
+ /* Update sp and ksp0 simultaneously to avoid backtracer warnings. */
+ move sp, r13
+ mtspr SPR_SYSTEM_SAVE_K_0, r2
+ }
+ FOR_EACH_CALLEE_SAVED_REG(LOAD_REG)
+.L__switch_to_pc:
+ {
+ addli sp, sp, FRAME_SIZE
+ jrp lr /* r0 is still valid here, so return it */
+ }
+ STD_ENDPROC(__switch_to)
+
+/* Return a suitable address for the backtracer for suspended threads */
+STD_ENTRY_SECTION(get_switch_to_pc, .sched.text)
+ lnk r0
+ {
+ addli r0, r0, .L__switch_to_pc - .
+ jrp lr
+ }
+ STD_ENDPROC(get_switch_to_pc)
+
+STD_ENTRY(get_pt_regs)
+ .irp reg, r0, r1, r2, r3, r4, r5, r6, r7, \
+ r8, r9, r10, r11, r12, r13, r14, r15, \
+ r16, r17, r18, r19, r20, r21, r22, r23, \
+ r24, r25, r26, r27, r28, r29, r30, r31, \
+ r32, r33, r34, r35, r36, r37, r38, r39, \
+ r40, r41, r42, r43, r44, r45, r46, r47, \
+ r48, r49, r50, r51, r52, tp, sp
+ {
+ st r0, \reg
+ addi r0, r0, 8
+ }
+ .endr
+ {
+ st r0, lr
+ addi r0, r0, PTREGS_OFFSET_PC - PTREGS_OFFSET_LR
+ }
+ lnk r1
+ {
+ st r0, r1
+ addi r0, r0, PTREGS_OFFSET_EX1 - PTREGS_OFFSET_PC
+ }
+ mfspr r1, INTERRUPT_CRITICAL_SECTION
+ shli r1, r1, SPR_EX_CONTEXT_1_1__ICS_SHIFT
+ ori r1, r1, KERNEL_PL
+ {
+ st r0, r1
+ addi r0, r0, PTREGS_OFFSET_FAULTNUM - PTREGS_OFFSET_EX1
+ }
+ {
+ st r0, zero /* clear faultnum */
+ addi r0, r0, PTREGS_OFFSET_ORIG_R0 - PTREGS_OFFSET_FAULTNUM
+ }
+ {
+ st r0, zero /* clear orig_r0 */
+ addli r0, r0, -PTREGS_OFFSET_ORIG_R0 /* restore r0 to base */
+ }
+ jrp lr
+ STD_ENDPROC(get_pt_regs)
diff --git a/arch/tile/kernel/setup.c b/arch/tile/kernel/setup.c
index 3696b18..6cdc9ba 100644
--- a/arch/tile/kernel/setup.c
+++ b/arch/tile/kernel/setup.c
@@ -912,6 +912,8 @@
#endif
}
+#ifdef CONFIG_BLK_DEV_INITRD
+
static int __initdata set_initramfs_file;
static char __initdata initramfs_file[128] = "initramfs.cpio.gz";
@@ -969,6 +971,10 @@
free_bootmem(__pa(begin), end - begin);
}
+#else
+static inline void load_hv_initrd(void) {}
+#endif /* CONFIG_BLK_DEV_INITRD */
+
static void __init validate_hv(void)
{
/*
diff --git a/arch/tile/kernel/signal.c b/arch/tile/kernel/signal.c
index 1260321..bedaf4e 100644
--- a/arch/tile/kernel/signal.c
+++ b/arch/tile/kernel/signal.c
@@ -39,7 +39,6 @@
#define _BLOCKABLE (~(sigmask(SIGKILL) | sigmask(SIGSTOP)))
-
SYSCALL_DEFINE3(sigaltstack, const stack_t __user *, uss,
stack_t __user *, uoss, struct pt_regs *, regs)
{
@@ -78,6 +77,13 @@
return err;
}
+void signal_fault(const char *type, struct pt_regs *regs,
+ void __user *frame, int sig)
+{
+ trace_unhandled_signal(type, regs, (unsigned long)frame, SIGSEGV);
+ force_sigsegv(sig, current);
+}
+
/* The assembly shim for this function arranges to ignore the return value. */
SYSCALL_DEFINE1(rt_sigreturn, struct pt_regs *, regs)
{
@@ -105,7 +111,7 @@
return 0;
badframe:
- force_sig(SIGSEGV, current);
+ signal_fault("bad sigreturn frame", regs, frame, 0);
return 0;
}
@@ -231,7 +237,7 @@
return 0;
give_sigsegv:
- force_sigsegv(sig, current);
+ signal_fault("bad setup frame", regs, frame, sig);
return -EFAULT;
}
@@ -245,7 +251,6 @@
{
int ret;
-
/* Are we from a system call? */
if (regs->faultnum == INT_SWINT_1) {
/* If so, check system call restarting.. */
@@ -363,3 +368,118 @@
/* Avoid double syscall restart if there are nested signals. */
regs->faultnum = INT_SWINT_1_SIGRETURN;
}
+
+int show_unhandled_signals = 1;
+
+static int __init crashinfo(char *str)
+{
+ unsigned long val;
+ const char *word;
+
+ if (*str == '\0')
+ val = 2;
+ else if (*str != '=' || strict_strtoul(++str, 0, &val) != 0)
+ return 0;
+ show_unhandled_signals = val;
+ switch (show_unhandled_signals) {
+ case 0:
+ word = "No";
+ break;
+ case 1:
+ word = "One-line";
+ break;
+ default:
+ word = "Detailed";
+ break;
+ }
+ pr_info("%s crash reports will be generated on the console\n", word);
+ return 1;
+}
+__setup("crashinfo", crashinfo);
+
+static void dump_mem(void __user *address)
+{
+ void __user *addr;
+ enum { region_size = 256, bytes_per_line = 16 };
+ int i, j, k;
+ int found_readable_mem = 0;
+
+ pr_err("\n");
+ if (!access_ok(VERIFY_READ, address, 1)) {
+ pr_err("Not dumping at address 0x%lx (kernel address)\n",
+ (unsigned long)address);
+ return;
+ }
+
+ addr = (void __user *)
+ (((unsigned long)address & -bytes_per_line) - region_size/2);
+ if (addr > address)
+ addr = NULL;
+ for (i = 0; i < region_size;
+ addr += bytes_per_line, i += bytes_per_line) {
+ unsigned char buf[bytes_per_line];
+ char line[100];
+ if (copy_from_user(buf, addr, bytes_per_line))
+ continue;
+ if (!found_readable_mem) {
+ pr_err("Dumping memory around address 0x%lx:\n",
+ (unsigned long)address);
+ found_readable_mem = 1;
+ }
+ j = sprintf(line, REGFMT":", (unsigned long)addr);
+ for (k = 0; k < bytes_per_line; ++k)
+ j += sprintf(&line[j], " %02x", buf[k]);
+ pr_err("%s\n", line);
+ }
+ if (!found_readable_mem)
+ pr_err("No readable memory around address 0x%lx\n",
+ (unsigned long)address);
+}
+
+void trace_unhandled_signal(const char *type, struct pt_regs *regs,
+ unsigned long address, int sig)
+{
+ struct task_struct *tsk = current;
+
+ if (show_unhandled_signals == 0)
+ return;
+
+ /* If the signal is handled, don't show it here. */
+ if (!is_global_init(tsk)) {
+ void __user *handler =
+ tsk->sighand->action[sig-1].sa.sa_handler;
+ if (handler != SIG_IGN && handler != SIG_DFL)
+ return;
+ }
+
+ /* Rate-limit the one-line output, not the detailed output. */
+ if (show_unhandled_signals <= 1 && !printk_ratelimit())
+ return;
+
+ printk("%s%s[%d]: %s at %lx pc "REGFMT" signal %d",
+ task_pid_nr(tsk) > 1 ? KERN_INFO : KERN_EMERG,
+ tsk->comm, task_pid_nr(tsk), type, address, regs->pc, sig);
+
+ print_vma_addr(KERN_CONT " in ", regs->pc);
+
+ printk(KERN_CONT "\n");
+
+ if (show_unhandled_signals > 1) {
+ switch (sig) {
+ case SIGILL:
+ case SIGFPE:
+ case SIGSEGV:
+ case SIGBUS:
+ pr_err("User crash: signal %d,"
+ " trap %ld, address 0x%lx\n",
+ sig, regs->faultnum, address);
+ show_regs(regs);
+ dump_mem((void __user *)address);
+ break;
+ default:
+ pr_err("User crash: signal %d, trap %ld\n",
+ sig, regs->faultnum);
+ break;
+ }
+ }
+}
diff --git a/arch/tile/kernel/single_step.c b/arch/tile/kernel/single_step.c
index 84a729e..4032ca8 100644
--- a/arch/tile/kernel/single_step.c
+++ b/arch/tile/kernel/single_step.c
@@ -186,6 +186,8 @@
.si_code = SEGV_MAPERR,
.si_addr = addr
};
+ trace_unhandled_signal("segfault", regs,
+ (unsigned long)addr, SIGSEGV);
force_sig_info(info.si_signo, &info, current);
return (tile_bundle_bits) 0;
}
@@ -196,6 +198,8 @@
.si_code = BUS_ADRALN,
.si_addr = addr
};
+ trace_unhandled_signal("unaligned trap", regs,
+ (unsigned long)addr, SIGBUS);
force_sig_info(info.si_signo, &info, current);
return (tile_bundle_bits) 0;
}
@@ -318,6 +322,14 @@
" .popsection\n"
);
+ /*
+ * Enable interrupts here to allow touching userspace and the like.
+ * The callers expect this: do_trap() already has interrupts
+ * enabled, and do_work_pending() handles functions that enable
+ * interrupts internally.
+ */
+ local_irq_enable();
+
if (state == NULL) {
/* allocate a page of writable, executable memory */
state = kmalloc(sizeof(struct single_step_state), GFP_KERNEL);
diff --git a/arch/tile/kernel/stack.c b/arch/tile/kernel/stack.c
index dd81713..37ee4d0 100644
--- a/arch/tile/kernel/stack.c
+++ b/arch/tile/kernel/stack.c
@@ -36,7 +36,7 @@
#define KBT_LOOP 3 /* Backtrace entered a loop */
/* Is address on the specified kernel stack? */
-static int in_kernel_stack(struct KBacktraceIterator *kbt, VirtualAddress sp)
+static int in_kernel_stack(struct KBacktraceIterator *kbt, unsigned long sp)
{
ulong kstack_base = (ulong) kbt->task->stack;
if (kstack_base == 0) /* corrupt task pointer; just follow stack... */
@@ -45,7 +45,7 @@
}
/* Is address valid for reading? */
-static int valid_address(struct KBacktraceIterator *kbt, VirtualAddress address)
+static int valid_address(struct KBacktraceIterator *kbt, unsigned long address)
{
HV_PTE *l1_pgtable = kbt->pgtable;
HV_PTE *l2_pgtable;
@@ -97,7 +97,7 @@
}
/* Callback for backtracer; basically a glorified memcpy */
-static bool read_memory_func(void *result, VirtualAddress address,
+static bool read_memory_func(void *result, unsigned long address,
unsigned int size, void *vkbt)
{
int retval;
@@ -124,7 +124,7 @@
{
const char *fault = NULL; /* happy compiler */
char fault_buf[64];
- VirtualAddress sp = kbt->it.sp;
+ unsigned long sp = kbt->it.sp;
struct pt_regs *p;
if (!in_kernel_stack(kbt, sp))
@@ -163,7 +163,7 @@
}
/* Is the pc pointing to a sigreturn trampoline? */
-static int is_sigreturn(VirtualAddress pc)
+static int is_sigreturn(unsigned long pc)
{
return (pc == VDSO_BASE);
}
@@ -260,7 +260,7 @@
void KBacktraceIterator_init(struct KBacktraceIterator *kbt,
struct task_struct *t, struct pt_regs *regs)
{
- VirtualAddress pc, lr, sp, r52;
+ unsigned long pc, lr, sp, r52;
int is_current;
/*
@@ -331,7 +331,7 @@
void KBacktraceIterator_next(struct KBacktraceIterator *kbt)
{
- VirtualAddress old_pc = kbt->it.pc, old_sp = kbt->it.sp;
+ unsigned long old_pc = kbt->it.pc, old_sp = kbt->it.sp;
kbt->new_context = 0;
if (!backtrace_next(&kbt->it) && !KBacktraceIterator_restart(kbt)) {
kbt->end = KBT_DONE;
diff --git a/arch/tile/kernel/sys.c b/arch/tile/kernel/sys.c
index e2187d2..cb44ba7 100644
--- a/arch/tile/kernel/sys.c
+++ b/arch/tile/kernel/sys.c
@@ -56,13 +56,6 @@
return sys_readahead(fd, ((loff_t)offset_hi << 32) | offset_lo, count);
}
-long sys32_fadvise64(int fd, u32 offset_lo, u32 offset_hi,
- u32 len, int advice)
-{
- return sys_fadvise64_64(fd, ((loff_t)offset_hi << 32) | offset_lo,
- len, advice);
-}
-
int sys32_fadvise64_64(int fd, u32 offset_lo, u32 offset_hi,
u32 len_lo, u32 len_hi, int advice)
{
@@ -103,10 +96,8 @@
#ifndef __tilegx__
/* See comments at the top of the file. */
-#define sys_fadvise64 sys32_fadvise64
#define sys_fadvise64_64 sys32_fadvise64_64
#define sys_readahead sys32_readahead
-#define sys_sync_file_range sys_sync_file_range2
#endif
/* Call the trampolines to manage pt_regs where necessary. */
diff --git a/arch/tile/kernel/tile-desc_32.c b/arch/tile/kernel/tile-desc_32.c
index 69af0e1..7e31a12 100644
--- a/arch/tile/kernel/tile-desc_32.c
+++ b/arch/tile/kernel/tile-desc_32.c
@@ -2413,12 +2413,13 @@
-/* Given a set of bundle bits and the lookup FSM for a specific pipe,
- * returns which instruction the bundle contains in that pipe.
+/* Given a set of bundle bits and a specific pipe, returns which
+ * instruction the bundle contains in that pipe.
*/
-static const struct tile_opcode *
-find_opcode(tile_bundle_bits bits, const unsigned short *table)
+const struct tile_opcode *
+find_opcode(tile_bundle_bits bits, tile_pipeline pipe)
{
+ const unsigned short *table = tile_bundle_decoder_fsms[pipe];
int index = 0;
while (1)
@@ -2465,7 +2466,7 @@
int i;
d = &decoded[num_instructions++];
- opc = find_opcode (bits, tile_bundle_decoder_fsms[pipe]);
+ opc = find_opcode (bits, (tile_pipeline)pipe);
d->opcode = opc;
/* Decode each operand, sign extending, etc. as appropriate. */
diff --git a/arch/tile/kernel/tile-desc_64.c b/arch/tile/kernel/tile-desc_64.c
new file mode 100644
index 0000000..d57007be
--- /dev/null
+++ b/arch/tile/kernel/tile-desc_64.c
@@ -0,0 +1,2200 @@
+/* This define is BFD_RELOC_##x for real bfd, or -1 for everyone else. */
+#define BFD_RELOC(x) -1
+
+/* Special registers. */
+#define TREG_LR 55
+#define TREG_SN 56
+#define TREG_ZERO 63
+
+/* FIXME: Rename this. */
+#include <asm/opcode-tile_64.h>
+
+#include <linux/stddef.h>
+
+const struct tilegx_opcode tilegx_opcodes[334] =
+{
+ { "bpt", TILEGX_OPC_BPT, 0x2, 0, TREG_ZERO, 0,
+ { { 0, }, { }, { 0, }, { 0, }, { 0, } },
+ },
+ { "info", TILEGX_OPC_INFO, 0xf, 1, TREG_ZERO, 1,
+ { { 0 }, { 1 }, { 2 }, { 3 }, { 0, } },
+ },
+ { "infol", TILEGX_OPC_INFOL, 0x3, 1, TREG_ZERO, 1,
+ { { 4 }, { 5 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "move", TILEGX_OPC_MOVE, 0xf, 2, TREG_ZERO, 1,
+ { { 6, 7 }, { 8, 9 }, { 10, 11 }, { 12, 13 }, { 0, } },
+ },
+ { "movei", TILEGX_OPC_MOVEI, 0xf, 2, TREG_ZERO, 1,
+ { { 6, 0 }, { 8, 1 }, { 10, 2 }, { 12, 3 }, { 0, } },
+ },
+ { "moveli", TILEGX_OPC_MOVELI, 0x3, 2, TREG_ZERO, 1,
+ { { 6, 4 }, { 8, 5 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "prefetch", TILEGX_OPC_PREFETCH, 0x12, 1, TREG_ZERO, 1,
+ { { 0, }, { 9 }, { 0, }, { 0, }, { 14 } },
+ },
+ { "prefetch_add_l1", TILEGX_OPC_PREFETCH_ADD_L1, 0x2, 2, TREG_ZERO, 1,
+ { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "prefetch_add_l1_fault", TILEGX_OPC_PREFETCH_ADD_L1_FAULT, 0x2, 2, TREG_ZERO, 1,
+ { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "prefetch_add_l2", TILEGX_OPC_PREFETCH_ADD_L2, 0x2, 2, TREG_ZERO, 1,
+ { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "prefetch_add_l2_fault", TILEGX_OPC_PREFETCH_ADD_L2_FAULT, 0x2, 2, TREG_ZERO, 1,
+ { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "prefetch_add_l3", TILEGX_OPC_PREFETCH_ADD_L3, 0x2, 2, TREG_ZERO, 1,
+ { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "prefetch_add_l3_fault", TILEGX_OPC_PREFETCH_ADD_L3_FAULT, 0x2, 2, TREG_ZERO, 1,
+ { { 0, }, { 15, 1 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "prefetch_l1", TILEGX_OPC_PREFETCH_L1, 0x12, 1, TREG_ZERO, 1,
+ { { 0, }, { 9 }, { 0, }, { 0, }, { 14 } },
+ },
+ { "prefetch_l1_fault", TILEGX_OPC_PREFETCH_L1_FAULT, 0x12, 1, TREG_ZERO, 1,
+ { { 0, }, { 9 }, { 0, }, { 0, }, { 14 } },
+ },
+ { "prefetch_l2", TILEGX_OPC_PREFETCH_L2, 0x12, 1, TREG_ZERO, 1,
+ { { 0, }, { 9 }, { 0, }, { 0, }, { 14 } },
+ },
+ { "prefetch_l2_fault", TILEGX_OPC_PREFETCH_L2_FAULT, 0x12, 1, TREG_ZERO, 1,
+ { { 0, }, { 9 }, { 0, }, { 0, }, { 14 } },
+ },
+ { "prefetch_l3", TILEGX_OPC_PREFETCH_L3, 0x12, 1, TREG_ZERO, 1,
+ { { 0, }, { 9 }, { 0, }, { 0, }, { 14 } },
+ },
+ { "prefetch_l3_fault", TILEGX_OPC_PREFETCH_L3_FAULT, 0x12, 1, TREG_ZERO, 1,
+ { { 0, }, { 9 }, { 0, }, { 0, }, { 14 } },
+ },
+ { "raise", TILEGX_OPC_RAISE, 0x2, 0, TREG_ZERO, 1,
+ { { 0, }, { }, { 0, }, { 0, }, { 0, } },
+ },
+ { "add", TILEGX_OPC_ADD, 0xf, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
+ },
+ { "addi", TILEGX_OPC_ADDI, 0xf, 3, TREG_ZERO, 1,
+ { { 6, 7, 0 }, { 8, 9, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } },
+ },
+ { "addli", TILEGX_OPC_ADDLI, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 4 }, { 8, 9, 5 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "addx", TILEGX_OPC_ADDX, 0xf, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
+ },
+ { "addxi", TILEGX_OPC_ADDXI, 0xf, 3, TREG_ZERO, 1,
+ { { 6, 7, 0 }, { 8, 9, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } },
+ },
+ { "addxli", TILEGX_OPC_ADDXLI, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 4 }, { 8, 9, 5 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "addxsc", TILEGX_OPC_ADDXSC, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "and", TILEGX_OPC_AND, 0xf, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
+ },
+ { "andi", TILEGX_OPC_ANDI, 0xf, 3, TREG_ZERO, 1,
+ { { 6, 7, 0 }, { 8, 9, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } },
+ },
+ { "beqz", TILEGX_OPC_BEQZ, 0x2, 2, TREG_ZERO, 1,
+ { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "beqzt", TILEGX_OPC_BEQZT, 0x2, 2, TREG_ZERO, 1,
+ { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "bfexts", TILEGX_OPC_BFEXTS, 0x1, 4, TREG_ZERO, 1,
+ { { 6, 7, 21, 22 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "bfextu", TILEGX_OPC_BFEXTU, 0x1, 4, TREG_ZERO, 1,
+ { { 6, 7, 21, 22 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "bfins", TILEGX_OPC_BFINS, 0x1, 4, TREG_ZERO, 1,
+ { { 23, 7, 21, 22 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "bgez", TILEGX_OPC_BGEZ, 0x2, 2, TREG_ZERO, 1,
+ { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "bgezt", TILEGX_OPC_BGEZT, 0x2, 2, TREG_ZERO, 1,
+ { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "bgtz", TILEGX_OPC_BGTZ, 0x2, 2, TREG_ZERO, 1,
+ { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "bgtzt", TILEGX_OPC_BGTZT, 0x2, 2, TREG_ZERO, 1,
+ { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "blbc", TILEGX_OPC_BLBC, 0x2, 2, TREG_ZERO, 1,
+ { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "blbct", TILEGX_OPC_BLBCT, 0x2, 2, TREG_ZERO, 1,
+ { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "blbs", TILEGX_OPC_BLBS, 0x2, 2, TREG_ZERO, 1,
+ { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "blbst", TILEGX_OPC_BLBST, 0x2, 2, TREG_ZERO, 1,
+ { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "blez", TILEGX_OPC_BLEZ, 0x2, 2, TREG_ZERO, 1,
+ { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "blezt", TILEGX_OPC_BLEZT, 0x2, 2, TREG_ZERO, 1,
+ { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "bltz", TILEGX_OPC_BLTZ, 0x2, 2, TREG_ZERO, 1,
+ { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "bltzt", TILEGX_OPC_BLTZT, 0x2, 2, TREG_ZERO, 1,
+ { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "bnez", TILEGX_OPC_BNEZ, 0x2, 2, TREG_ZERO, 1,
+ { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "bnezt", TILEGX_OPC_BNEZT, 0x2, 2, TREG_ZERO, 1,
+ { { 0, }, { 9, 20 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "clz", TILEGX_OPC_CLZ, 0x5, 2, TREG_ZERO, 1,
+ { { 6, 7 }, { 0, }, { 10, 11 }, { 0, }, { 0, } },
+ },
+ { "cmoveqz", TILEGX_OPC_CMOVEQZ, 0x5, 3, TREG_ZERO, 1,
+ { { 23, 7, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
+ },
+ { "cmovnez", TILEGX_OPC_CMOVNEZ, 0x5, 3, TREG_ZERO, 1,
+ { { 23, 7, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
+ },
+ { "cmpeq", TILEGX_OPC_CMPEQ, 0xf, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
+ },
+ { "cmpeqi", TILEGX_OPC_CMPEQI, 0xf, 3, TREG_ZERO, 1,
+ { { 6, 7, 0 }, { 8, 9, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } },
+ },
+ { "cmpexch", TILEGX_OPC_CMPEXCH, 0x2, 3, TREG_ZERO, 1,
+ { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "cmpexch4", TILEGX_OPC_CMPEXCH4, 0x2, 3, TREG_ZERO, 1,
+ { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "cmples", TILEGX_OPC_CMPLES, 0xf, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
+ },
+ { "cmpleu", TILEGX_OPC_CMPLEU, 0xf, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
+ },
+ { "cmplts", TILEGX_OPC_CMPLTS, 0xf, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
+ },
+ { "cmpltsi", TILEGX_OPC_CMPLTSI, 0xf, 3, TREG_ZERO, 1,
+ { { 6, 7, 0 }, { 8, 9, 1 }, { 10, 11, 2 }, { 12, 13, 3 }, { 0, } },
+ },
+ { "cmpltu", TILEGX_OPC_CMPLTU, 0xf, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
+ },
+ { "cmpltui", TILEGX_OPC_CMPLTUI, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "cmpne", TILEGX_OPC_CMPNE, 0xf, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
+ },
+ { "cmul", TILEGX_OPC_CMUL, 0x1, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "cmula", TILEGX_OPC_CMULA, 0x1, 3, TREG_ZERO, 1,
+ { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "cmulaf", TILEGX_OPC_CMULAF, 0x1, 3, TREG_ZERO, 1,
+ { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "cmulf", TILEGX_OPC_CMULF, 0x1, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "cmulfr", TILEGX_OPC_CMULFR, 0x1, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "cmulh", TILEGX_OPC_CMULH, 0x1, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "cmulhr", TILEGX_OPC_CMULHR, 0x1, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "crc32_32", TILEGX_OPC_CRC32_32, 0x1, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "crc32_8", TILEGX_OPC_CRC32_8, 0x1, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "ctz", TILEGX_OPC_CTZ, 0x5, 2, TREG_ZERO, 1,
+ { { 6, 7 }, { 0, }, { 10, 11 }, { 0, }, { 0, } },
+ },
+ { "dblalign", TILEGX_OPC_DBLALIGN, 0x1, 3, TREG_ZERO, 1,
+ { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "dblalign2", TILEGX_OPC_DBLALIGN2, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "dblalign4", TILEGX_OPC_DBLALIGN4, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "dblalign6", TILEGX_OPC_DBLALIGN6, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "drain", TILEGX_OPC_DRAIN, 0x2, 0, TREG_ZERO, 0,
+ { { 0, }, { }, { 0, }, { 0, }, { 0, } },
+ },
+ { "dtlbpr", TILEGX_OPC_DTLBPR, 0x2, 1, TREG_ZERO, 1,
+ { { 0, }, { 9 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "exch", TILEGX_OPC_EXCH, 0x2, 3, TREG_ZERO, 1,
+ { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "exch4", TILEGX_OPC_EXCH4, 0x2, 3, TREG_ZERO, 1,
+ { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "fdouble_add_flags", TILEGX_OPC_FDOUBLE_ADD_FLAGS, 0x1, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "fdouble_addsub", TILEGX_OPC_FDOUBLE_ADDSUB, 0x1, 3, TREG_ZERO, 1,
+ { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "fdouble_mul_flags", TILEGX_OPC_FDOUBLE_MUL_FLAGS, 0x1, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "fdouble_pack1", TILEGX_OPC_FDOUBLE_PACK1, 0x1, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "fdouble_pack2", TILEGX_OPC_FDOUBLE_PACK2, 0x1, 3, TREG_ZERO, 1,
+ { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "fdouble_sub_flags", TILEGX_OPC_FDOUBLE_SUB_FLAGS, 0x1, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "fdouble_unpack_max", TILEGX_OPC_FDOUBLE_UNPACK_MAX, 0x1, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "fdouble_unpack_min", TILEGX_OPC_FDOUBLE_UNPACK_MIN, 0x1, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "fetchadd", TILEGX_OPC_FETCHADD, 0x2, 3, TREG_ZERO, 1,
+ { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "fetchadd4", TILEGX_OPC_FETCHADD4, 0x2, 3, TREG_ZERO, 1,
+ { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "fetchaddgez", TILEGX_OPC_FETCHADDGEZ, 0x2, 3, TREG_ZERO, 1,
+ { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "fetchaddgez4", TILEGX_OPC_FETCHADDGEZ4, 0x2, 3, TREG_ZERO, 1,
+ { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "fetchand", TILEGX_OPC_FETCHAND, 0x2, 3, TREG_ZERO, 1,
+ { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "fetchand4", TILEGX_OPC_FETCHAND4, 0x2, 3, TREG_ZERO, 1,
+ { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "fetchor", TILEGX_OPC_FETCHOR, 0x2, 3, TREG_ZERO, 1,
+ { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "fetchor4", TILEGX_OPC_FETCHOR4, 0x2, 3, TREG_ZERO, 1,
+ { { 0, }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "finv", TILEGX_OPC_FINV, 0x2, 1, TREG_ZERO, 1,
+ { { 0, }, { 9 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "flush", TILEGX_OPC_FLUSH, 0x2, 1, TREG_ZERO, 1,
+ { { 0, }, { 9 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "flushwb", TILEGX_OPC_FLUSHWB, 0x2, 0, TREG_ZERO, 1,
+ { { 0, }, { }, { 0, }, { 0, }, { 0, } },
+ },
+ { "fnop", TILEGX_OPC_FNOP, 0xf, 0, TREG_ZERO, 1,
+ { { }, { }, { }, { }, { 0, } },
+ },
+ { "fsingle_add1", TILEGX_OPC_FSINGLE_ADD1, 0x1, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "fsingle_addsub2", TILEGX_OPC_FSINGLE_ADDSUB2, 0x1, 3, TREG_ZERO, 1,
+ { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "fsingle_mul1", TILEGX_OPC_FSINGLE_MUL1, 0x1, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "fsingle_mul2", TILEGX_OPC_FSINGLE_MUL2, 0x1, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "fsingle_pack1", TILEGX_OPC_FSINGLE_PACK1, 0x5, 2, TREG_ZERO, 1,
+ { { 6, 7 }, { 0, }, { 10, 11 }, { 0, }, { 0, } },
+ },
+ { "fsingle_pack2", TILEGX_OPC_FSINGLE_PACK2, 0x1, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "fsingle_sub1", TILEGX_OPC_FSINGLE_SUB1, 0x1, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "icoh", TILEGX_OPC_ICOH, 0x2, 1, TREG_ZERO, 1,
+ { { 0, }, { 9 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "ill", TILEGX_OPC_ILL, 0xa, 0, TREG_ZERO, 1,
+ { { 0, }, { }, { 0, }, { }, { 0, } },
+ },
+ { "inv", TILEGX_OPC_INV, 0x2, 1, TREG_ZERO, 1,
+ { { 0, }, { 9 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "iret", TILEGX_OPC_IRET, 0x2, 0, TREG_ZERO, 1,
+ { { 0, }, { }, { 0, }, { 0, }, { 0, } },
+ },
+ { "j", TILEGX_OPC_J, 0x2, 1, TREG_ZERO, 1,
+ { { 0, }, { 25 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "jal", TILEGX_OPC_JAL, 0x2, 1, TREG_LR, 1,
+ { { 0, }, { 25 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "jalr", TILEGX_OPC_JALR, 0xa, 1, TREG_LR, 1,
+ { { 0, }, { 9 }, { 0, }, { 13 }, { 0, } },
+ },
+ { "jalrp", TILEGX_OPC_JALRP, 0xa, 1, TREG_LR, 1,
+ { { 0, }, { 9 }, { 0, }, { 13 }, { 0, } },
+ },
+ { "jr", TILEGX_OPC_JR, 0xa, 1, TREG_ZERO, 1,
+ { { 0, }, { 9 }, { 0, }, { 13 }, { 0, } },
+ },
+ { "jrp", TILEGX_OPC_JRP, 0xa, 1, TREG_ZERO, 1,
+ { { 0, }, { 9 }, { 0, }, { 13 }, { 0, } },
+ },
+ { "ld", TILEGX_OPC_LD, 0x12, 2, TREG_ZERO, 1,
+ { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 26, 14 } },
+ },
+ { "ld1s", TILEGX_OPC_LD1S, 0x12, 2, TREG_ZERO, 1,
+ { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 26, 14 } },
+ },
+ { "ld1s_add", TILEGX_OPC_LD1S_ADD, 0x2, 3, TREG_ZERO, 1,
+ { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "ld1u", TILEGX_OPC_LD1U, 0x12, 2, TREG_ZERO, 1,
+ { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 26, 14 } },
+ },
+ { "ld1u_add", TILEGX_OPC_LD1U_ADD, 0x2, 3, TREG_ZERO, 1,
+ { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "ld2s", TILEGX_OPC_LD2S, 0x12, 2, TREG_ZERO, 1,
+ { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 26, 14 } },
+ },
+ { "ld2s_add", TILEGX_OPC_LD2S_ADD, 0x2, 3, TREG_ZERO, 1,
+ { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "ld2u", TILEGX_OPC_LD2U, 0x12, 2, TREG_ZERO, 1,
+ { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 26, 14 } },
+ },
+ { "ld2u_add", TILEGX_OPC_LD2U_ADD, 0x2, 3, TREG_ZERO, 1,
+ { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "ld4s", TILEGX_OPC_LD4S, 0x12, 2, TREG_ZERO, 1,
+ { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 26, 14 } },
+ },
+ { "ld4s_add", TILEGX_OPC_LD4S_ADD, 0x2, 3, TREG_ZERO, 1,
+ { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "ld4u", TILEGX_OPC_LD4U, 0x12, 2, TREG_ZERO, 1,
+ { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 26, 14 } },
+ },
+ { "ld4u_add", TILEGX_OPC_LD4U_ADD, 0x2, 3, TREG_ZERO, 1,
+ { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "ld_add", TILEGX_OPC_LD_ADD, 0x2, 3, TREG_ZERO, 1,
+ { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "ldna", TILEGX_OPC_LDNA, 0x2, 2, TREG_ZERO, 1,
+ { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "ldna_add", TILEGX_OPC_LDNA_ADD, 0x2, 3, TREG_ZERO, 1,
+ { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "ldnt", TILEGX_OPC_LDNT, 0x2, 2, TREG_ZERO, 1,
+ { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "ldnt1s", TILEGX_OPC_LDNT1S, 0x2, 2, TREG_ZERO, 1,
+ { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "ldnt1s_add", TILEGX_OPC_LDNT1S_ADD, 0x2, 3, TREG_ZERO, 1,
+ { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "ldnt1u", TILEGX_OPC_LDNT1U, 0x2, 2, TREG_ZERO, 1,
+ { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "ldnt1u_add", TILEGX_OPC_LDNT1U_ADD, 0x2, 3, TREG_ZERO, 1,
+ { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "ldnt2s", TILEGX_OPC_LDNT2S, 0x2, 2, TREG_ZERO, 1,
+ { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "ldnt2s_add", TILEGX_OPC_LDNT2S_ADD, 0x2, 3, TREG_ZERO, 1,
+ { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "ldnt2u", TILEGX_OPC_LDNT2U, 0x2, 2, TREG_ZERO, 1,
+ { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "ldnt2u_add", TILEGX_OPC_LDNT2U_ADD, 0x2, 3, TREG_ZERO, 1,
+ { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "ldnt4s", TILEGX_OPC_LDNT4S, 0x2, 2, TREG_ZERO, 1,
+ { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "ldnt4s_add", TILEGX_OPC_LDNT4S_ADD, 0x2, 3, TREG_ZERO, 1,
+ { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "ldnt4u", TILEGX_OPC_LDNT4U, 0x2, 2, TREG_ZERO, 1,
+ { { 0, }, { 8, 9 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "ldnt4u_add", TILEGX_OPC_LDNT4U_ADD, 0x2, 3, TREG_ZERO, 1,
+ { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "ldnt_add", TILEGX_OPC_LDNT_ADD, 0x2, 3, TREG_ZERO, 1,
+ { { 0, }, { 8, 15, 1 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "lnk", TILEGX_OPC_LNK, 0xa, 1, TREG_ZERO, 1,
+ { { 0, }, { 8 }, { 0, }, { 12 }, { 0, } },
+ },
+ { "mf", TILEGX_OPC_MF, 0x2, 0, TREG_ZERO, 1,
+ { { 0, }, { }, { 0, }, { 0, }, { 0, } },
+ },
+ { "mfspr", TILEGX_OPC_MFSPR, 0x2, 2, TREG_ZERO, 1,
+ { { 0, }, { 8, 27 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "mm", TILEGX_OPC_MM, 0x1, 4, TREG_ZERO, 1,
+ { { 23, 7, 21, 22 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "mnz", TILEGX_OPC_MNZ, 0xf, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
+ },
+ { "mtspr", TILEGX_OPC_MTSPR, 0x2, 2, TREG_ZERO, 1,
+ { { 0, }, { 28, 9 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "mul_hs_hs", TILEGX_OPC_MUL_HS_HS, 0x5, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } },
+ },
+ { "mul_hs_hu", TILEGX_OPC_MUL_HS_HU, 0x1, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "mul_hs_ls", TILEGX_OPC_MUL_HS_LS, 0x1, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "mul_hs_lu", TILEGX_OPC_MUL_HS_LU, 0x1, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "mul_hu_hu", TILEGX_OPC_MUL_HU_HU, 0x5, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } },
+ },
+ { "mul_hu_ls", TILEGX_OPC_MUL_HU_LS, 0x1, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "mul_hu_lu", TILEGX_OPC_MUL_HU_LU, 0x1, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "mul_ls_ls", TILEGX_OPC_MUL_LS_LS, 0x5, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } },
+ },
+ { "mul_ls_lu", TILEGX_OPC_MUL_LS_LU, 0x1, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "mul_lu_lu", TILEGX_OPC_MUL_LU_LU, 0x5, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } },
+ },
+ { "mula_hs_hs", TILEGX_OPC_MULA_HS_HS, 0x5, 3, TREG_ZERO, 1,
+ { { 23, 7, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
+ },
+ { "mula_hs_hu", TILEGX_OPC_MULA_HS_HU, 0x1, 3, TREG_ZERO, 1,
+ { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "mula_hs_ls", TILEGX_OPC_MULA_HS_LS, 0x1, 3, TREG_ZERO, 1,
+ { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "mula_hs_lu", TILEGX_OPC_MULA_HS_LU, 0x1, 3, TREG_ZERO, 1,
+ { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "mula_hu_hu", TILEGX_OPC_MULA_HU_HU, 0x5, 3, TREG_ZERO, 1,
+ { { 23, 7, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
+ },
+ { "mula_hu_ls", TILEGX_OPC_MULA_HU_LS, 0x1, 3, TREG_ZERO, 1,
+ { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "mula_hu_lu", TILEGX_OPC_MULA_HU_LU, 0x1, 3, TREG_ZERO, 1,
+ { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "mula_ls_ls", TILEGX_OPC_MULA_LS_LS, 0x5, 3, TREG_ZERO, 1,
+ { { 23, 7, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
+ },
+ { "mula_ls_lu", TILEGX_OPC_MULA_LS_LU, 0x1, 3, TREG_ZERO, 1,
+ { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "mula_lu_lu", TILEGX_OPC_MULA_LU_LU, 0x5, 3, TREG_ZERO, 1,
+ { { 23, 7, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
+ },
+ { "mulax", TILEGX_OPC_MULAX, 0x5, 3, TREG_ZERO, 1,
+ { { 23, 7, 16 }, { 0, }, { 24, 11, 18 }, { 0, }, { 0, } },
+ },
+ { "mulx", TILEGX_OPC_MULX, 0x5, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 0, }, { 10, 11, 18 }, { 0, }, { 0, } },
+ },
+ { "mz", TILEGX_OPC_MZ, 0xf, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
+ },
+ { "nap", TILEGX_OPC_NAP, 0x2, 0, TREG_ZERO, 0,
+ { { 0, }, { }, { 0, }, { 0, }, { 0, } },
+ },
+ { "nop", TILEGX_OPC_NOP, 0xf, 0, TREG_ZERO, 1,
+ { { }, { }, { }, { }, { 0, } },
+ },
+ { "nor", TILEGX_OPC_NOR, 0xf, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
+ },
+ { "or", TILEGX_OPC_OR, 0xf, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
+ },
+ { "ori", TILEGX_OPC_ORI, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "pcnt", TILEGX_OPC_PCNT, 0x5, 2, TREG_ZERO, 1,
+ { { 6, 7 }, { 0, }, { 10, 11 }, { 0, }, { 0, } },
+ },
+ { "revbits", TILEGX_OPC_REVBITS, 0x5, 2, TREG_ZERO, 1,
+ { { 6, 7 }, { 0, }, { 10, 11 }, { 0, }, { 0, } },
+ },
+ { "revbytes", TILEGX_OPC_REVBYTES, 0x5, 2, TREG_ZERO, 1,
+ { { 6, 7 }, { 0, }, { 10, 11 }, { 0, }, { 0, } },
+ },
+ { "rotl", TILEGX_OPC_ROTL, 0xf, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
+ },
+ { "rotli", TILEGX_OPC_ROTLI, 0xf, 3, TREG_ZERO, 1,
+ { { 6, 7, 29 }, { 8, 9, 30 }, { 10, 11, 31 }, { 12, 13, 32 }, { 0, } },
+ },
+ { "shl", TILEGX_OPC_SHL, 0xf, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
+ },
+ { "shl16insli", TILEGX_OPC_SHL16INSLI, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 4 }, { 8, 9, 5 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "shl1add", TILEGX_OPC_SHL1ADD, 0xf, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
+ },
+ { "shl1addx", TILEGX_OPC_SHL1ADDX, 0xf, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
+ },
+ { "shl2add", TILEGX_OPC_SHL2ADD, 0xf, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
+ },
+ { "shl2addx", TILEGX_OPC_SHL2ADDX, 0xf, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
+ },
+ { "shl3add", TILEGX_OPC_SHL3ADD, 0xf, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
+ },
+ { "shl3addx", TILEGX_OPC_SHL3ADDX, 0xf, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
+ },
+ { "shli", TILEGX_OPC_SHLI, 0xf, 3, TREG_ZERO, 1,
+ { { 6, 7, 29 }, { 8, 9, 30 }, { 10, 11, 31 }, { 12, 13, 32 }, { 0, } },
+ },
+ { "shlx", TILEGX_OPC_SHLX, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "shlxi", TILEGX_OPC_SHLXI, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 29 }, { 8, 9, 30 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "shrs", TILEGX_OPC_SHRS, 0xf, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
+ },
+ { "shrsi", TILEGX_OPC_SHRSI, 0xf, 3, TREG_ZERO, 1,
+ { { 6, 7, 29 }, { 8, 9, 30 }, { 10, 11, 31 }, { 12, 13, 32 }, { 0, } },
+ },
+ { "shru", TILEGX_OPC_SHRU, 0xf, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
+ },
+ { "shrui", TILEGX_OPC_SHRUI, 0xf, 3, TREG_ZERO, 1,
+ { { 6, 7, 29 }, { 8, 9, 30 }, { 10, 11, 31 }, { 12, 13, 32 }, { 0, } },
+ },
+ { "shrux", TILEGX_OPC_SHRUX, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "shruxi", TILEGX_OPC_SHRUXI, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 29 }, { 8, 9, 30 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "shufflebytes", TILEGX_OPC_SHUFFLEBYTES, 0x1, 3, TREG_ZERO, 1,
+ { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "st", TILEGX_OPC_ST, 0x12, 2, TREG_ZERO, 1,
+ { { 0, }, { 9, 17 }, { 0, }, { 0, }, { 14, 33 } },
+ },
+ { "st1", TILEGX_OPC_ST1, 0x12, 2, TREG_ZERO, 1,
+ { { 0, }, { 9, 17 }, { 0, }, { 0, }, { 14, 33 } },
+ },
+ { "st1_add", TILEGX_OPC_ST1_ADD, 0x2, 3, TREG_ZERO, 1,
+ { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "st2", TILEGX_OPC_ST2, 0x12, 2, TREG_ZERO, 1,
+ { { 0, }, { 9, 17 }, { 0, }, { 0, }, { 14, 33 } },
+ },
+ { "st2_add", TILEGX_OPC_ST2_ADD, 0x2, 3, TREG_ZERO, 1,
+ { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "st4", TILEGX_OPC_ST4, 0x12, 2, TREG_ZERO, 1,
+ { { 0, }, { 9, 17 }, { 0, }, { 0, }, { 14, 33 } },
+ },
+ { "st4_add", TILEGX_OPC_ST4_ADD, 0x2, 3, TREG_ZERO, 1,
+ { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "st_add", TILEGX_OPC_ST_ADD, 0x2, 3, TREG_ZERO, 1,
+ { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "stnt", TILEGX_OPC_STNT, 0x2, 2, TREG_ZERO, 1,
+ { { 0, }, { 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "stnt1", TILEGX_OPC_STNT1, 0x2, 2, TREG_ZERO, 1,
+ { { 0, }, { 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "stnt1_add", TILEGX_OPC_STNT1_ADD, 0x2, 3, TREG_ZERO, 1,
+ { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "stnt2", TILEGX_OPC_STNT2, 0x2, 2, TREG_ZERO, 1,
+ { { 0, }, { 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "stnt2_add", TILEGX_OPC_STNT2_ADD, 0x2, 3, TREG_ZERO, 1,
+ { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "stnt4", TILEGX_OPC_STNT4, 0x2, 2, TREG_ZERO, 1,
+ { { 0, }, { 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "stnt4_add", TILEGX_OPC_STNT4_ADD, 0x2, 3, TREG_ZERO, 1,
+ { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "stnt_add", TILEGX_OPC_STNT_ADD, 0x2, 3, TREG_ZERO, 1,
+ { { 0, }, { 15, 17, 34 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "sub", TILEGX_OPC_SUB, 0xf, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
+ },
+ { "subx", TILEGX_OPC_SUBX, 0xf, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
+ },
+ { "subxsc", TILEGX_OPC_SUBXSC, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "swint0", TILEGX_OPC_SWINT0, 0x2, 0, TREG_ZERO, 0,
+ { { 0, }, { }, { 0, }, { 0, }, { 0, } },
+ },
+ { "swint1", TILEGX_OPC_SWINT1, 0x2, 0, TREG_ZERO, 0,
+ { { 0, }, { }, { 0, }, { 0, }, { 0, } },
+ },
+ { "swint2", TILEGX_OPC_SWINT2, 0x2, 0, TREG_ZERO, 0,
+ { { 0, }, { }, { 0, }, { 0, }, { 0, } },
+ },
+ { "swint3", TILEGX_OPC_SWINT3, 0x2, 0, TREG_ZERO, 0,
+ { { 0, }, { }, { 0, }, { 0, }, { 0, } },
+ },
+ { "tblidxb0", TILEGX_OPC_TBLIDXB0, 0x5, 2, TREG_ZERO, 1,
+ { { 23, 7 }, { 0, }, { 24, 11 }, { 0, }, { 0, } },
+ },
+ { "tblidxb1", TILEGX_OPC_TBLIDXB1, 0x5, 2, TREG_ZERO, 1,
+ { { 23, 7 }, { 0, }, { 24, 11 }, { 0, }, { 0, } },
+ },
+ { "tblidxb2", TILEGX_OPC_TBLIDXB2, 0x5, 2, TREG_ZERO, 1,
+ { { 23, 7 }, { 0, }, { 24, 11 }, { 0, }, { 0, } },
+ },
+ { "tblidxb3", TILEGX_OPC_TBLIDXB3, 0x5, 2, TREG_ZERO, 1,
+ { { 23, 7 }, { 0, }, { 24, 11 }, { 0, }, { 0, } },
+ },
+ { "v1add", TILEGX_OPC_V1ADD, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v1addi", TILEGX_OPC_V1ADDI, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v1adduc", TILEGX_OPC_V1ADDUC, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v1adiffu", TILEGX_OPC_V1ADIFFU, 0x1, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v1avgu", TILEGX_OPC_V1AVGU, 0x1, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v1cmpeq", TILEGX_OPC_V1CMPEQ, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v1cmpeqi", TILEGX_OPC_V1CMPEQI, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v1cmples", TILEGX_OPC_V1CMPLES, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v1cmpleu", TILEGX_OPC_V1CMPLEU, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v1cmplts", TILEGX_OPC_V1CMPLTS, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v1cmpltsi", TILEGX_OPC_V1CMPLTSI, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v1cmpltu", TILEGX_OPC_V1CMPLTU, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v1cmpltui", TILEGX_OPC_V1CMPLTUI, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v1cmpne", TILEGX_OPC_V1CMPNE, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v1ddotpu", TILEGX_OPC_V1DDOTPU, 0x1, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v1ddotpua", TILEGX_OPC_V1DDOTPUA, 0x1, 3, TREG_ZERO, 1,
+ { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v1ddotpus", TILEGX_OPC_V1DDOTPUS, 0x1, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v1ddotpusa", TILEGX_OPC_V1DDOTPUSA, 0x1, 3, TREG_ZERO, 1,
+ { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v1dotp", TILEGX_OPC_V1DOTP, 0x1, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v1dotpa", TILEGX_OPC_V1DOTPA, 0x1, 3, TREG_ZERO, 1,
+ { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v1dotpu", TILEGX_OPC_V1DOTPU, 0x1, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v1dotpua", TILEGX_OPC_V1DOTPUA, 0x1, 3, TREG_ZERO, 1,
+ { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v1dotpus", TILEGX_OPC_V1DOTPUS, 0x1, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v1dotpusa", TILEGX_OPC_V1DOTPUSA, 0x1, 3, TREG_ZERO, 1,
+ { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v1int_h", TILEGX_OPC_V1INT_H, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v1int_l", TILEGX_OPC_V1INT_L, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v1maxu", TILEGX_OPC_V1MAXU, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v1maxui", TILEGX_OPC_V1MAXUI, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v1minu", TILEGX_OPC_V1MINU, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v1minui", TILEGX_OPC_V1MINUI, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v1mnz", TILEGX_OPC_V1MNZ, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v1multu", TILEGX_OPC_V1MULTU, 0x1, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v1mulu", TILEGX_OPC_V1MULU, 0x1, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v1mulus", TILEGX_OPC_V1MULUS, 0x1, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v1mz", TILEGX_OPC_V1MZ, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v1sadau", TILEGX_OPC_V1SADAU, 0x1, 3, TREG_ZERO, 1,
+ { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v1sadu", TILEGX_OPC_V1SADU, 0x1, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v1shl", TILEGX_OPC_V1SHL, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v1shli", TILEGX_OPC_V1SHLI, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 29 }, { 8, 9, 30 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v1shrs", TILEGX_OPC_V1SHRS, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v1shrsi", TILEGX_OPC_V1SHRSI, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 29 }, { 8, 9, 30 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v1shru", TILEGX_OPC_V1SHRU, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v1shrui", TILEGX_OPC_V1SHRUI, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 29 }, { 8, 9, 30 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v1sub", TILEGX_OPC_V1SUB, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v1subuc", TILEGX_OPC_V1SUBUC, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v2add", TILEGX_OPC_V2ADD, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v2addi", TILEGX_OPC_V2ADDI, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v2addsc", TILEGX_OPC_V2ADDSC, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v2adiffs", TILEGX_OPC_V2ADIFFS, 0x1, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v2avgs", TILEGX_OPC_V2AVGS, 0x1, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v2cmpeq", TILEGX_OPC_V2CMPEQ, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v2cmpeqi", TILEGX_OPC_V2CMPEQI, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v2cmples", TILEGX_OPC_V2CMPLES, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v2cmpleu", TILEGX_OPC_V2CMPLEU, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v2cmplts", TILEGX_OPC_V2CMPLTS, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v2cmpltsi", TILEGX_OPC_V2CMPLTSI, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v2cmpltu", TILEGX_OPC_V2CMPLTU, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v2cmpltui", TILEGX_OPC_V2CMPLTUI, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v2cmpne", TILEGX_OPC_V2CMPNE, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v2dotp", TILEGX_OPC_V2DOTP, 0x1, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v2dotpa", TILEGX_OPC_V2DOTPA, 0x1, 3, TREG_ZERO, 1,
+ { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v2int_h", TILEGX_OPC_V2INT_H, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v2int_l", TILEGX_OPC_V2INT_L, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v2maxs", TILEGX_OPC_V2MAXS, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v2maxsi", TILEGX_OPC_V2MAXSI, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v2mins", TILEGX_OPC_V2MINS, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v2minsi", TILEGX_OPC_V2MINSI, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v2mnz", TILEGX_OPC_V2MNZ, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v2mulfsc", TILEGX_OPC_V2MULFSC, 0x1, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v2muls", TILEGX_OPC_V2MULS, 0x1, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v2mults", TILEGX_OPC_V2MULTS, 0x1, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v2mz", TILEGX_OPC_V2MZ, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v2packh", TILEGX_OPC_V2PACKH, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v2packl", TILEGX_OPC_V2PACKL, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v2packuc", TILEGX_OPC_V2PACKUC, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v2sadas", TILEGX_OPC_V2SADAS, 0x1, 3, TREG_ZERO, 1,
+ { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v2sadau", TILEGX_OPC_V2SADAU, 0x1, 3, TREG_ZERO, 1,
+ { { 23, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v2sads", TILEGX_OPC_V2SADS, 0x1, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v2sadu", TILEGX_OPC_V2SADU, 0x1, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 0, }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v2shl", TILEGX_OPC_V2SHL, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v2shli", TILEGX_OPC_V2SHLI, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 29 }, { 8, 9, 30 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v2shlsc", TILEGX_OPC_V2SHLSC, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v2shrs", TILEGX_OPC_V2SHRS, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v2shrsi", TILEGX_OPC_V2SHRSI, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 29 }, { 8, 9, 30 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v2shru", TILEGX_OPC_V2SHRU, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v2shrui", TILEGX_OPC_V2SHRUI, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 29 }, { 8, 9, 30 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v2sub", TILEGX_OPC_V2SUB, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v2subsc", TILEGX_OPC_V2SUBSC, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v4add", TILEGX_OPC_V4ADD, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v4addsc", TILEGX_OPC_V4ADDSC, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v4int_h", TILEGX_OPC_V4INT_H, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v4int_l", TILEGX_OPC_V4INT_L, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v4packsc", TILEGX_OPC_V4PACKSC, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v4shl", TILEGX_OPC_V4SHL, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v4shlsc", TILEGX_OPC_V4SHLSC, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v4shrs", TILEGX_OPC_V4SHRS, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v4shru", TILEGX_OPC_V4SHRU, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v4sub", TILEGX_OPC_V4SUB, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "v4subsc", TILEGX_OPC_V4SUBSC, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "wh64", TILEGX_OPC_WH64, 0x2, 1, TREG_ZERO, 1,
+ { { 0, }, { 9 }, { 0, }, { 0, }, { 0, } },
+ },
+ { "xor", TILEGX_OPC_XOR, 0xf, 3, TREG_ZERO, 1,
+ { { 6, 7, 16 }, { 8, 9, 17 }, { 10, 11, 18 }, { 12, 13, 19 }, { 0, } },
+ },
+ { "xori", TILEGX_OPC_XORI, 0x3, 3, TREG_ZERO, 1,
+ { { 6, 7, 0 }, { 8, 9, 1 }, { 0, }, { 0, }, { 0, } },
+ },
+ { NULL, TILEGX_OPC_NONE, 0, 0, TREG_ZERO, 0, { { 0, } },
+ }
+};
+#define BITFIELD(start, size) ((start) | (((1 << (size)) - 1) << 6))
+#define CHILD(array_index) (TILEGX_OPC_NONE + (array_index))
+
+static const unsigned short decode_X0_fsm[936] =
+{
+ BITFIELD(22, 9) /* index 0 */,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
+ CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
+ CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
+ CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
+ CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
+ CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
+ CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
+ CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
+ CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
+ CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
+ CHILD(513), CHILD(513), CHILD(513), CHILD(513), TILEGX_OPC_ADDXLI,
+ TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
+ TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
+ TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
+ TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
+ TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
+ TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
+ TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
+ TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
+ TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
+ TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
+ TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
+ TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
+ TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
+ TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
+ TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
+ TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_BFEXTS,
+ TILEGX_OPC_BFEXTS, TILEGX_OPC_BFEXTS, TILEGX_OPC_BFEXTS, TILEGX_OPC_BFEXTU,
+ TILEGX_OPC_BFEXTU, TILEGX_OPC_BFEXTU, TILEGX_OPC_BFEXTU, TILEGX_OPC_BFINS,
+ TILEGX_OPC_BFINS, TILEGX_OPC_BFINS, TILEGX_OPC_BFINS, TILEGX_OPC_MM,
+ TILEGX_OPC_MM, TILEGX_OPC_MM, TILEGX_OPC_MM, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, CHILD(528), CHILD(578),
+ CHILD(583), CHILD(588), CHILD(593), CHILD(598), TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, CHILD(603), CHILD(620), CHILD(637), CHILD(654), CHILD(671),
+ CHILD(703), CHILD(797), CHILD(814), CHILD(831), CHILD(848), CHILD(865),
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, CHILD(889), TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
+ CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
+ CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
+ CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
+ CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
+ CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
+ CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
+ CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
+ CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
+ CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
+ CHILD(906), CHILD(906), CHILD(906), CHILD(906), CHILD(906),
+ BITFIELD(6, 2) /* index 513 */,
+ TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, CHILD(518),
+ BITFIELD(8, 2) /* index 518 */,
+ TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, CHILD(523),
+ BITFIELD(10, 2) /* index 523 */,
+ TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_MOVELI,
+ BITFIELD(20, 2) /* index 528 */,
+ TILEGX_OPC_NONE, CHILD(533), TILEGX_OPC_ADDXI, CHILD(548),
+ BITFIELD(6, 2) /* index 533 */,
+ TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(538),
+ BITFIELD(8, 2) /* index 538 */,
+ TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(543),
+ BITFIELD(10, 2) /* index 543 */,
+ TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_MOVEI,
+ BITFIELD(0, 2) /* index 548 */,
+ TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(553),
+ BITFIELD(2, 2) /* index 553 */,
+ TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(558),
+ BITFIELD(4, 2) /* index 558 */,
+ TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(563),
+ BITFIELD(6, 2) /* index 563 */,
+ TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(568),
+ BITFIELD(8, 2) /* index 568 */,
+ TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(573),
+ BITFIELD(10, 2) /* index 573 */,
+ TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_INFO,
+ BITFIELD(20, 2) /* index 578 */,
+ TILEGX_OPC_CMPEQI, TILEGX_OPC_CMPLTSI, TILEGX_OPC_CMPLTUI, TILEGX_OPC_ORI,
+ BITFIELD(20, 2) /* index 583 */,
+ TILEGX_OPC_V1ADDI, TILEGX_OPC_V1CMPEQI, TILEGX_OPC_V1CMPLTSI,
+ TILEGX_OPC_V1CMPLTUI,
+ BITFIELD(20, 2) /* index 588 */,
+ TILEGX_OPC_V1MAXUI, TILEGX_OPC_V1MINUI, TILEGX_OPC_V2ADDI,
+ TILEGX_OPC_V2CMPEQI,
+ BITFIELD(20, 2) /* index 593 */,
+ TILEGX_OPC_V2CMPLTSI, TILEGX_OPC_V2CMPLTUI, TILEGX_OPC_V2MAXSI,
+ TILEGX_OPC_V2MINSI,
+ BITFIELD(20, 2) /* index 598 */,
+ TILEGX_OPC_XORI, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ BITFIELD(18, 4) /* index 603 */,
+ TILEGX_OPC_NONE, TILEGX_OPC_ADDXSC, TILEGX_OPC_ADDX, TILEGX_OPC_ADD,
+ TILEGX_OPC_AND, TILEGX_OPC_CMOVEQZ, TILEGX_OPC_CMOVNEZ, TILEGX_OPC_CMPEQ,
+ TILEGX_OPC_CMPLES, TILEGX_OPC_CMPLEU, TILEGX_OPC_CMPLTS, TILEGX_OPC_CMPLTU,
+ TILEGX_OPC_CMPNE, TILEGX_OPC_CMULAF, TILEGX_OPC_CMULA, TILEGX_OPC_CMULFR,
+ BITFIELD(18, 4) /* index 620 */,
+ TILEGX_OPC_CMULF, TILEGX_OPC_CMULHR, TILEGX_OPC_CMULH, TILEGX_OPC_CMUL,
+ TILEGX_OPC_CRC32_32, TILEGX_OPC_CRC32_8, TILEGX_OPC_DBLALIGN2,
+ TILEGX_OPC_DBLALIGN4, TILEGX_OPC_DBLALIGN6, TILEGX_OPC_DBLALIGN,
+ TILEGX_OPC_FDOUBLE_ADDSUB, TILEGX_OPC_FDOUBLE_ADD_FLAGS,
+ TILEGX_OPC_FDOUBLE_MUL_FLAGS, TILEGX_OPC_FDOUBLE_PACK1,
+ TILEGX_OPC_FDOUBLE_PACK2, TILEGX_OPC_FDOUBLE_SUB_FLAGS,
+ BITFIELD(18, 4) /* index 637 */,
+ TILEGX_OPC_FDOUBLE_UNPACK_MAX, TILEGX_OPC_FDOUBLE_UNPACK_MIN,
+ TILEGX_OPC_FSINGLE_ADD1, TILEGX_OPC_FSINGLE_ADDSUB2,
+ TILEGX_OPC_FSINGLE_MUL1, TILEGX_OPC_FSINGLE_MUL2, TILEGX_OPC_FSINGLE_PACK2,
+ TILEGX_OPC_FSINGLE_SUB1, TILEGX_OPC_MNZ, TILEGX_OPC_MULAX,
+ TILEGX_OPC_MULA_HS_HS, TILEGX_OPC_MULA_HS_HU, TILEGX_OPC_MULA_HS_LS,
+ TILEGX_OPC_MULA_HS_LU, TILEGX_OPC_MULA_HU_HU, TILEGX_OPC_MULA_HU_LS,
+ BITFIELD(18, 4) /* index 654 */,
+ TILEGX_OPC_MULA_HU_LU, TILEGX_OPC_MULA_LS_LS, TILEGX_OPC_MULA_LS_LU,
+ TILEGX_OPC_MULA_LU_LU, TILEGX_OPC_MULX, TILEGX_OPC_MUL_HS_HS,
+ TILEGX_OPC_MUL_HS_HU, TILEGX_OPC_MUL_HS_LS, TILEGX_OPC_MUL_HS_LU,
+ TILEGX_OPC_MUL_HU_HU, TILEGX_OPC_MUL_HU_LS, TILEGX_OPC_MUL_HU_LU,
+ TILEGX_OPC_MUL_LS_LS, TILEGX_OPC_MUL_LS_LU, TILEGX_OPC_MUL_LU_LU,
+ TILEGX_OPC_MZ,
+ BITFIELD(18, 4) /* index 671 */,
+ TILEGX_OPC_NOR, CHILD(688), TILEGX_OPC_ROTL, TILEGX_OPC_SHL1ADDX,
+ TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL2ADDX, TILEGX_OPC_SHL2ADD,
+ TILEGX_OPC_SHL3ADDX, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHLX, TILEGX_OPC_SHL,
+ TILEGX_OPC_SHRS, TILEGX_OPC_SHRUX, TILEGX_OPC_SHRU, TILEGX_OPC_SHUFFLEBYTES,
+ TILEGX_OPC_SUBXSC,
+ BITFIELD(12, 2) /* index 688 */,
+ TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(693),
+ BITFIELD(14, 2) /* index 693 */,
+ TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(698),
+ BITFIELD(16, 2) /* index 698 */,
+ TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_MOVE,
+ BITFIELD(18, 4) /* index 703 */,
+ TILEGX_OPC_SUBX, TILEGX_OPC_SUB, CHILD(720), TILEGX_OPC_V1ADDUC,
+ TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADIFFU, TILEGX_OPC_V1AVGU,
+ TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLEU,
+ TILEGX_OPC_V1CMPLTS, TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPNE,
+ TILEGX_OPC_V1DDOTPUSA, TILEGX_OPC_V1DDOTPUS, TILEGX_OPC_V1DOTPA,
+ BITFIELD(12, 4) /* index 720 */,
+ TILEGX_OPC_NONE, CHILD(737), CHILD(742), CHILD(747), CHILD(752), CHILD(757),
+ CHILD(762), CHILD(767), CHILD(772), CHILD(777), CHILD(782), CHILD(787),
+ CHILD(792), TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ BITFIELD(16, 2) /* index 737 */,
+ TILEGX_OPC_CLZ, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ BITFIELD(16, 2) /* index 742 */,
+ TILEGX_OPC_CTZ, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ BITFIELD(16, 2) /* index 747 */,
+ TILEGX_OPC_FNOP, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ BITFIELD(16, 2) /* index 752 */,
+ TILEGX_OPC_FSINGLE_PACK1, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ BITFIELD(16, 2) /* index 757 */,
+ TILEGX_OPC_NOP, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ BITFIELD(16, 2) /* index 762 */,
+ TILEGX_OPC_PCNT, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ BITFIELD(16, 2) /* index 767 */,
+ TILEGX_OPC_REVBITS, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ BITFIELD(16, 2) /* index 772 */,
+ TILEGX_OPC_REVBYTES, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ BITFIELD(16, 2) /* index 777 */,
+ TILEGX_OPC_TBLIDXB0, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ BITFIELD(16, 2) /* index 782 */,
+ TILEGX_OPC_TBLIDXB1, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ BITFIELD(16, 2) /* index 787 */,
+ TILEGX_OPC_TBLIDXB2, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ BITFIELD(16, 2) /* index 792 */,
+ TILEGX_OPC_TBLIDXB3, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ BITFIELD(18, 4) /* index 797 */,
+ TILEGX_OPC_V1DOTPUSA, TILEGX_OPC_V1DOTPUS, TILEGX_OPC_V1DOTP,
+ TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_L, TILEGX_OPC_V1MAXU,
+ TILEGX_OPC_V1MINU, TILEGX_OPC_V1MNZ, TILEGX_OPC_V1MULTU, TILEGX_OPC_V1MULUS,
+ TILEGX_OPC_V1MULU, TILEGX_OPC_V1MZ, TILEGX_OPC_V1SADAU, TILEGX_OPC_V1SADU,
+ TILEGX_OPC_V1SHL, TILEGX_OPC_V1SHRS,
+ BITFIELD(18, 4) /* index 814 */,
+ TILEGX_OPC_V1SHRU, TILEGX_OPC_V1SUBUC, TILEGX_OPC_V1SUB, TILEGX_OPC_V2ADDSC,
+ TILEGX_OPC_V2ADD, TILEGX_OPC_V2ADIFFS, TILEGX_OPC_V2AVGS,
+ TILEGX_OPC_V2CMPEQ, TILEGX_OPC_V2CMPLES, TILEGX_OPC_V2CMPLEU,
+ TILEGX_OPC_V2CMPLTS, TILEGX_OPC_V2CMPLTU, TILEGX_OPC_V2CMPNE,
+ TILEGX_OPC_V2DOTPA, TILEGX_OPC_V2DOTP, TILEGX_OPC_V2INT_H,
+ BITFIELD(18, 4) /* index 831 */,
+ TILEGX_OPC_V2INT_L, TILEGX_OPC_V2MAXS, TILEGX_OPC_V2MINS, TILEGX_OPC_V2MNZ,
+ TILEGX_OPC_V2MULFSC, TILEGX_OPC_V2MULS, TILEGX_OPC_V2MULTS, TILEGX_OPC_V2MZ,
+ TILEGX_OPC_V2PACKH, TILEGX_OPC_V2PACKL, TILEGX_OPC_V2PACKUC,
+ TILEGX_OPC_V2SADAS, TILEGX_OPC_V2SADAU, TILEGX_OPC_V2SADS,
+ TILEGX_OPC_V2SADU, TILEGX_OPC_V2SHLSC,
+ BITFIELD(18, 4) /* index 848 */,
+ TILEGX_OPC_V2SHL, TILEGX_OPC_V2SHRS, TILEGX_OPC_V2SHRU, TILEGX_OPC_V2SUBSC,
+ TILEGX_OPC_V2SUB, TILEGX_OPC_V4ADDSC, TILEGX_OPC_V4ADD, TILEGX_OPC_V4INT_H,
+ TILEGX_OPC_V4INT_L, TILEGX_OPC_V4PACKSC, TILEGX_OPC_V4SHLSC,
+ TILEGX_OPC_V4SHL, TILEGX_OPC_V4SHRS, TILEGX_OPC_V4SHRU, TILEGX_OPC_V4SUBSC,
+ TILEGX_OPC_V4SUB,
+ BITFIELD(18, 3) /* index 865 */,
+ CHILD(874), CHILD(877), CHILD(880), CHILD(883), CHILD(886), TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ BITFIELD(21, 1) /* index 874 */,
+ TILEGX_OPC_XOR, TILEGX_OPC_NONE,
+ BITFIELD(21, 1) /* index 877 */,
+ TILEGX_OPC_V1DDOTPUA, TILEGX_OPC_NONE,
+ BITFIELD(21, 1) /* index 880 */,
+ TILEGX_OPC_V1DDOTPU, TILEGX_OPC_NONE,
+ BITFIELD(21, 1) /* index 883 */,
+ TILEGX_OPC_V1DOTPUA, TILEGX_OPC_NONE,
+ BITFIELD(21, 1) /* index 886 */,
+ TILEGX_OPC_V1DOTPU, TILEGX_OPC_NONE,
+ BITFIELD(18, 4) /* index 889 */,
+ TILEGX_OPC_NONE, TILEGX_OPC_ROTLI, TILEGX_OPC_SHLI, TILEGX_OPC_SHLXI,
+ TILEGX_OPC_SHRSI, TILEGX_OPC_SHRUI, TILEGX_OPC_SHRUXI, TILEGX_OPC_V1SHLI,
+ TILEGX_OPC_V1SHRSI, TILEGX_OPC_V1SHRUI, TILEGX_OPC_V2SHLI,
+ TILEGX_OPC_V2SHRSI, TILEGX_OPC_V2SHRUI, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE,
+ BITFIELD(0, 2) /* index 906 */,
+ TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
+ CHILD(911),
+ BITFIELD(2, 2) /* index 911 */,
+ TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
+ CHILD(916),
+ BITFIELD(4, 2) /* index 916 */,
+ TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
+ CHILD(921),
+ BITFIELD(6, 2) /* index 921 */,
+ TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
+ CHILD(926),
+ BITFIELD(8, 2) /* index 926 */,
+ TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
+ CHILD(931),
+ BITFIELD(10, 2) /* index 931 */,
+ TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
+ TILEGX_OPC_INFOL,
+};
+
+static const unsigned short decode_X1_fsm[1206] =
+{
+ BITFIELD(53, 9) /* index 0 */,
+ CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
+ CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
+ CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
+ CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
+ CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
+ CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
+ CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
+ CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
+ CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
+ CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513), CHILD(513),
+ CHILD(513), CHILD(513), CHILD(513), CHILD(513), TILEGX_OPC_ADDXLI,
+ TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
+ TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
+ TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
+ TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
+ TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
+ TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
+ TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
+ TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
+ TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
+ TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
+ TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
+ TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
+ TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
+ TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
+ TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI,
+ TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_ADDXLI, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_BEQZT,
+ TILEGX_OPC_BEQZT, TILEGX_OPC_BEQZ, TILEGX_OPC_BEQZ, TILEGX_OPC_BGEZT,
+ TILEGX_OPC_BGEZT, TILEGX_OPC_BGEZ, TILEGX_OPC_BGEZ, TILEGX_OPC_BGTZT,
+ TILEGX_OPC_BGTZT, TILEGX_OPC_BGTZ, TILEGX_OPC_BGTZ, TILEGX_OPC_BLBCT,
+ TILEGX_OPC_BLBCT, TILEGX_OPC_BLBC, TILEGX_OPC_BLBC, TILEGX_OPC_BLBST,
+ TILEGX_OPC_BLBST, TILEGX_OPC_BLBS, TILEGX_OPC_BLBS, TILEGX_OPC_BLEZT,
+ TILEGX_OPC_BLEZT, TILEGX_OPC_BLEZ, TILEGX_OPC_BLEZ, TILEGX_OPC_BLTZT,
+ TILEGX_OPC_BLTZT, TILEGX_OPC_BLTZ, TILEGX_OPC_BLTZ, TILEGX_OPC_BNEZT,
+ TILEGX_OPC_BNEZT, TILEGX_OPC_BNEZ, TILEGX_OPC_BNEZ, CHILD(528), CHILD(578),
+ CHILD(598), CHILD(663), CHILD(683), CHILD(688), CHILD(693), CHILD(698),
+ CHILD(703), CHILD(708), CHILD(713), CHILD(718), TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_JAL,
+ TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL,
+ TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL,
+ TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL,
+ TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL,
+ TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL,
+ TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL,
+ TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL,
+ TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_JAL, TILEGX_OPC_J, TILEGX_OPC_J,
+ TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J,
+ TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J,
+ TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J,
+ TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J,
+ TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J,
+ TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J, TILEGX_OPC_J,
+ CHILD(723), CHILD(740), CHILD(772), CHILD(789), CHILD(1108), CHILD(1125),
+ CHILD(1142), TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, CHILD(1159), TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, CHILD(1176), CHILD(1176), CHILD(1176),
+ CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
+ CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
+ CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
+ CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
+ CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
+ CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
+ CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
+ CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
+ CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
+ CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
+ CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
+ CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176), CHILD(1176),
+ CHILD(1176),
+ BITFIELD(37, 2) /* index 513 */,
+ TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, CHILD(518),
+ BITFIELD(39, 2) /* index 518 */,
+ TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, CHILD(523),
+ BITFIELD(41, 2) /* index 523 */,
+ TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_ADDLI, TILEGX_OPC_MOVELI,
+ BITFIELD(51, 2) /* index 528 */,
+ TILEGX_OPC_NONE, CHILD(533), TILEGX_OPC_ADDXI, CHILD(548),
+ BITFIELD(37, 2) /* index 533 */,
+ TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(538),
+ BITFIELD(39, 2) /* index 538 */,
+ TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(543),
+ BITFIELD(41, 2) /* index 543 */,
+ TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_MOVEI,
+ BITFIELD(31, 2) /* index 548 */,
+ TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(553),
+ BITFIELD(33, 2) /* index 553 */,
+ TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(558),
+ BITFIELD(35, 2) /* index 558 */,
+ TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(563),
+ BITFIELD(37, 2) /* index 563 */,
+ TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(568),
+ BITFIELD(39, 2) /* index 568 */,
+ TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(573),
+ BITFIELD(41, 2) /* index 573 */,
+ TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_INFO,
+ BITFIELD(51, 2) /* index 578 */,
+ TILEGX_OPC_CMPEQI, TILEGX_OPC_CMPLTSI, TILEGX_OPC_CMPLTUI, CHILD(583),
+ BITFIELD(31, 2) /* index 583 */,
+ TILEGX_OPC_LD1S_ADD, TILEGX_OPC_LD1S_ADD, TILEGX_OPC_LD1S_ADD, CHILD(588),
+ BITFIELD(33, 2) /* index 588 */,
+ TILEGX_OPC_LD1S_ADD, TILEGX_OPC_LD1S_ADD, TILEGX_OPC_LD1S_ADD, CHILD(593),
+ BITFIELD(35, 2) /* index 593 */,
+ TILEGX_OPC_LD1S_ADD, TILEGX_OPC_LD1S_ADD, TILEGX_OPC_LD1S_ADD,
+ TILEGX_OPC_PREFETCH_ADD_L1_FAULT,
+ BITFIELD(51, 2) /* index 598 */,
+ CHILD(603), CHILD(618), CHILD(633), CHILD(648),
+ BITFIELD(31, 2) /* index 603 */,
+ TILEGX_OPC_LD1U_ADD, TILEGX_OPC_LD1U_ADD, TILEGX_OPC_LD1U_ADD, CHILD(608),
+ BITFIELD(33, 2) /* index 608 */,
+ TILEGX_OPC_LD1U_ADD, TILEGX_OPC_LD1U_ADD, TILEGX_OPC_LD1U_ADD, CHILD(613),
+ BITFIELD(35, 2) /* index 613 */,
+ TILEGX_OPC_LD1U_ADD, TILEGX_OPC_LD1U_ADD, TILEGX_OPC_LD1U_ADD,
+ TILEGX_OPC_PREFETCH_ADD_L1,
+ BITFIELD(31, 2) /* index 618 */,
+ TILEGX_OPC_LD2S_ADD, TILEGX_OPC_LD2S_ADD, TILEGX_OPC_LD2S_ADD, CHILD(623),
+ BITFIELD(33, 2) /* index 623 */,
+ TILEGX_OPC_LD2S_ADD, TILEGX_OPC_LD2S_ADD, TILEGX_OPC_LD2S_ADD, CHILD(628),
+ BITFIELD(35, 2) /* index 628 */,
+ TILEGX_OPC_LD2S_ADD, TILEGX_OPC_LD2S_ADD, TILEGX_OPC_LD2S_ADD,
+ TILEGX_OPC_PREFETCH_ADD_L2_FAULT,
+ BITFIELD(31, 2) /* index 633 */,
+ TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD, CHILD(638),
+ BITFIELD(33, 2) /* index 638 */,
+ TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD, CHILD(643),
+ BITFIELD(35, 2) /* index 643 */,
+ TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD, TILEGX_OPC_LD2U_ADD,
+ TILEGX_OPC_PREFETCH_ADD_L2,
+ BITFIELD(31, 2) /* index 648 */,
+ TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD, CHILD(653),
+ BITFIELD(33, 2) /* index 653 */,
+ TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD, CHILD(658),
+ BITFIELD(35, 2) /* index 658 */,
+ TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD, TILEGX_OPC_LD4S_ADD,
+ TILEGX_OPC_PREFETCH_ADD_L3_FAULT,
+ BITFIELD(51, 2) /* index 663 */,
+ CHILD(668), TILEGX_OPC_LDNT1S_ADD, TILEGX_OPC_LDNT1U_ADD,
+ TILEGX_OPC_LDNT2S_ADD,
+ BITFIELD(31, 2) /* index 668 */,
+ TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, CHILD(673),
+ BITFIELD(33, 2) /* index 673 */,
+ TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, CHILD(678),
+ BITFIELD(35, 2) /* index 678 */,
+ TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD, TILEGX_OPC_LD4U_ADD,
+ TILEGX_OPC_PREFETCH_ADD_L3,
+ BITFIELD(51, 2) /* index 683 */,
+ TILEGX_OPC_LDNT2U_ADD, TILEGX_OPC_LDNT4S_ADD, TILEGX_OPC_LDNT4U_ADD,
+ TILEGX_OPC_LDNT_ADD,
+ BITFIELD(51, 2) /* index 688 */,
+ TILEGX_OPC_LD_ADD, TILEGX_OPC_LDNA_ADD, TILEGX_OPC_MFSPR, TILEGX_OPC_MTSPR,
+ BITFIELD(51, 2) /* index 693 */,
+ TILEGX_OPC_ORI, TILEGX_OPC_ST1_ADD, TILEGX_OPC_ST2_ADD, TILEGX_OPC_ST4_ADD,
+ BITFIELD(51, 2) /* index 698 */,
+ TILEGX_OPC_STNT1_ADD, TILEGX_OPC_STNT2_ADD, TILEGX_OPC_STNT4_ADD,
+ TILEGX_OPC_STNT_ADD,
+ BITFIELD(51, 2) /* index 703 */,
+ TILEGX_OPC_ST_ADD, TILEGX_OPC_V1ADDI, TILEGX_OPC_V1CMPEQI,
+ TILEGX_OPC_V1CMPLTSI,
+ BITFIELD(51, 2) /* index 708 */,
+ TILEGX_OPC_V1CMPLTUI, TILEGX_OPC_V1MAXUI, TILEGX_OPC_V1MINUI,
+ TILEGX_OPC_V2ADDI,
+ BITFIELD(51, 2) /* index 713 */,
+ TILEGX_OPC_V2CMPEQI, TILEGX_OPC_V2CMPLTSI, TILEGX_OPC_V2CMPLTUI,
+ TILEGX_OPC_V2MAXSI,
+ BITFIELD(51, 2) /* index 718 */,
+ TILEGX_OPC_V2MINSI, TILEGX_OPC_XORI, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ BITFIELD(49, 4) /* index 723 */,
+ TILEGX_OPC_NONE, TILEGX_OPC_ADDXSC, TILEGX_OPC_ADDX, TILEGX_OPC_ADD,
+ TILEGX_OPC_AND, TILEGX_OPC_CMPEQ, TILEGX_OPC_CMPEXCH4, TILEGX_OPC_CMPEXCH,
+ TILEGX_OPC_CMPLES, TILEGX_OPC_CMPLEU, TILEGX_OPC_CMPLTS, TILEGX_OPC_CMPLTU,
+ TILEGX_OPC_CMPNE, TILEGX_OPC_DBLALIGN2, TILEGX_OPC_DBLALIGN4,
+ TILEGX_OPC_DBLALIGN6,
+ BITFIELD(49, 4) /* index 740 */,
+ TILEGX_OPC_EXCH4, TILEGX_OPC_EXCH, TILEGX_OPC_FETCHADD4,
+ TILEGX_OPC_FETCHADDGEZ4, TILEGX_OPC_FETCHADDGEZ, TILEGX_OPC_FETCHADD,
+ TILEGX_OPC_FETCHAND4, TILEGX_OPC_FETCHAND, TILEGX_OPC_FETCHOR4,
+ TILEGX_OPC_FETCHOR, TILEGX_OPC_MNZ, TILEGX_OPC_MZ, TILEGX_OPC_NOR,
+ CHILD(757), TILEGX_OPC_ROTL, TILEGX_OPC_SHL1ADDX,
+ BITFIELD(43, 2) /* index 757 */,
+ TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(762),
+ BITFIELD(45, 2) /* index 762 */,
+ TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(767),
+ BITFIELD(47, 2) /* index 767 */,
+ TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_MOVE,
+ BITFIELD(49, 4) /* index 772 */,
+ TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL2ADDX, TILEGX_OPC_SHL2ADD,
+ TILEGX_OPC_SHL3ADDX, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHLX, TILEGX_OPC_SHL,
+ TILEGX_OPC_SHRS, TILEGX_OPC_SHRUX, TILEGX_OPC_SHRU, TILEGX_OPC_ST1,
+ TILEGX_OPC_ST2, TILEGX_OPC_ST4, TILEGX_OPC_STNT1, TILEGX_OPC_STNT2,
+ TILEGX_OPC_STNT4,
+ BITFIELD(46, 7) /* index 789 */,
+ TILEGX_OPC_STNT, TILEGX_OPC_STNT, TILEGX_OPC_STNT, TILEGX_OPC_STNT,
+ TILEGX_OPC_STNT, TILEGX_OPC_STNT, TILEGX_OPC_STNT, TILEGX_OPC_STNT,
+ TILEGX_OPC_ST, TILEGX_OPC_ST, TILEGX_OPC_ST, TILEGX_OPC_ST, TILEGX_OPC_ST,
+ TILEGX_OPC_ST, TILEGX_OPC_ST, TILEGX_OPC_ST, TILEGX_OPC_SUBXSC,
+ TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBXSC,
+ TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBXSC, TILEGX_OPC_SUBX,
+ TILEGX_OPC_SUBX, TILEGX_OPC_SUBX, TILEGX_OPC_SUBX, TILEGX_OPC_SUBX,
+ TILEGX_OPC_SUBX, TILEGX_OPC_SUBX, TILEGX_OPC_SUBX, TILEGX_OPC_SUB,
+ TILEGX_OPC_SUB, TILEGX_OPC_SUB, TILEGX_OPC_SUB, TILEGX_OPC_SUB,
+ TILEGX_OPC_SUB, TILEGX_OPC_SUB, TILEGX_OPC_SUB, CHILD(918), CHILD(927),
+ CHILD(1006), CHILD(1090), CHILD(1099), TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADDUC,
+ TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADDUC,
+ TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADDUC, TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADD,
+ TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADD,
+ TILEGX_OPC_V1ADD, TILEGX_OPC_V1ADD, TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPEQ,
+ TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPEQ,
+ TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPEQ, TILEGX_OPC_V1CMPEQ,
+ TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLES,
+ TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLES,
+ TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLES, TILEGX_OPC_V1CMPLEU,
+ TILEGX_OPC_V1CMPLEU, TILEGX_OPC_V1CMPLEU, TILEGX_OPC_V1CMPLEU,
+ TILEGX_OPC_V1CMPLEU, TILEGX_OPC_V1CMPLEU, TILEGX_OPC_V1CMPLEU,
+ TILEGX_OPC_V1CMPLEU, TILEGX_OPC_V1CMPLTS, TILEGX_OPC_V1CMPLTS,
+ TILEGX_OPC_V1CMPLTS, TILEGX_OPC_V1CMPLTS, TILEGX_OPC_V1CMPLTS,
+ TILEGX_OPC_V1CMPLTS, TILEGX_OPC_V1CMPLTS, TILEGX_OPC_V1CMPLTS,
+ TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPLTU,
+ TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPLTU,
+ TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPLTU, TILEGX_OPC_V1CMPNE,
+ TILEGX_OPC_V1CMPNE, TILEGX_OPC_V1CMPNE, TILEGX_OPC_V1CMPNE,
+ TILEGX_OPC_V1CMPNE, TILEGX_OPC_V1CMPNE, TILEGX_OPC_V1CMPNE,
+ TILEGX_OPC_V1CMPNE, TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_H,
+ TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_H,
+ TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_H, TILEGX_OPC_V1INT_H,
+ TILEGX_OPC_V1INT_L, TILEGX_OPC_V1INT_L, TILEGX_OPC_V1INT_L,
+ TILEGX_OPC_V1INT_L, TILEGX_OPC_V1INT_L, TILEGX_OPC_V1INT_L,
+ TILEGX_OPC_V1INT_L, TILEGX_OPC_V1INT_L,
+ BITFIELD(43, 3) /* index 918 */,
+ TILEGX_OPC_NONE, TILEGX_OPC_DRAIN, TILEGX_OPC_DTLBPR, TILEGX_OPC_FINV,
+ TILEGX_OPC_FLUSHWB, TILEGX_OPC_FLUSH, TILEGX_OPC_FNOP, TILEGX_OPC_ICOH,
+ BITFIELD(43, 3) /* index 927 */,
+ CHILD(936), TILEGX_OPC_INV, TILEGX_OPC_IRET, TILEGX_OPC_JALRP,
+ TILEGX_OPC_JALR, TILEGX_OPC_JRP, TILEGX_OPC_JR, CHILD(991),
+ BITFIELD(31, 2) /* index 936 */,
+ CHILD(941), CHILD(966), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
+ BITFIELD(33, 2) /* index 941 */,
+ TILEGX_OPC_ILL, TILEGX_OPC_ILL, TILEGX_OPC_ILL, CHILD(946),
+ BITFIELD(35, 2) /* index 946 */,
+ TILEGX_OPC_ILL, CHILD(951), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
+ BITFIELD(37, 2) /* index 951 */,
+ TILEGX_OPC_ILL, CHILD(956), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
+ BITFIELD(39, 2) /* index 956 */,
+ TILEGX_OPC_ILL, CHILD(961), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
+ BITFIELD(41, 2) /* index 961 */,
+ TILEGX_OPC_ILL, TILEGX_OPC_ILL, TILEGX_OPC_BPT, TILEGX_OPC_ILL,
+ BITFIELD(33, 2) /* index 966 */,
+ TILEGX_OPC_ILL, TILEGX_OPC_ILL, TILEGX_OPC_ILL, CHILD(971),
+ BITFIELD(35, 2) /* index 971 */,
+ TILEGX_OPC_ILL, CHILD(976), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
+ BITFIELD(37, 2) /* index 976 */,
+ TILEGX_OPC_ILL, CHILD(981), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
+ BITFIELD(39, 2) /* index 981 */,
+ TILEGX_OPC_ILL, CHILD(986), TILEGX_OPC_ILL, TILEGX_OPC_ILL,
+ BITFIELD(41, 2) /* index 986 */,
+ TILEGX_OPC_ILL, TILEGX_OPC_ILL, TILEGX_OPC_RAISE, TILEGX_OPC_ILL,
+ BITFIELD(31, 2) /* index 991 */,
+ TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, CHILD(996),
+ BITFIELD(33, 2) /* index 996 */,
+ TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, CHILD(1001),
+ BITFIELD(35, 2) /* index 1001 */,
+ TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, TILEGX_OPC_LD1S,
+ TILEGX_OPC_PREFETCH_L1_FAULT,
+ BITFIELD(43, 3) /* index 1006 */,
+ CHILD(1015), CHILD(1030), CHILD(1045), CHILD(1060), CHILD(1075),
+ TILEGX_OPC_LDNA, TILEGX_OPC_LDNT1S, TILEGX_OPC_LDNT1U,
+ BITFIELD(31, 2) /* index 1015 */,
+ TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, CHILD(1020),
+ BITFIELD(33, 2) /* index 1020 */,
+ TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, CHILD(1025),
+ BITFIELD(35, 2) /* index 1025 */,
+ TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_PREFETCH,
+ BITFIELD(31, 2) /* index 1030 */,
+ TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, CHILD(1035),
+ BITFIELD(33, 2) /* index 1035 */,
+ TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, CHILD(1040),
+ BITFIELD(35, 2) /* index 1040 */,
+ TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, TILEGX_OPC_LD2S,
+ TILEGX_OPC_PREFETCH_L2_FAULT,
+ BITFIELD(31, 2) /* index 1045 */,
+ TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, CHILD(1050),
+ BITFIELD(33, 2) /* index 1050 */,
+ TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, CHILD(1055),
+ BITFIELD(35, 2) /* index 1055 */,
+ TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_PREFETCH_L2,
+ BITFIELD(31, 2) /* index 1060 */,
+ TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, CHILD(1065),
+ BITFIELD(33, 2) /* index 1065 */,
+ TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, CHILD(1070),
+ BITFIELD(35, 2) /* index 1070 */,
+ TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, TILEGX_OPC_LD4S,
+ TILEGX_OPC_PREFETCH_L3_FAULT,
+ BITFIELD(31, 2) /* index 1075 */,
+ TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, CHILD(1080),
+ BITFIELD(33, 2) /* index 1080 */,
+ TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, CHILD(1085),
+ BITFIELD(35, 2) /* index 1085 */,
+ TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_PREFETCH_L3,
+ BITFIELD(43, 3) /* index 1090 */,
+ TILEGX_OPC_LDNT2S, TILEGX_OPC_LDNT2U, TILEGX_OPC_LDNT4S, TILEGX_OPC_LDNT4U,
+ TILEGX_OPC_LDNT, TILEGX_OPC_LD, TILEGX_OPC_LNK, TILEGX_OPC_MF,
+ BITFIELD(43, 3) /* index 1099 */,
+ TILEGX_OPC_NAP, TILEGX_OPC_NOP, TILEGX_OPC_SWINT0, TILEGX_OPC_SWINT1,
+ TILEGX_OPC_SWINT2, TILEGX_OPC_SWINT3, TILEGX_OPC_WH64, TILEGX_OPC_NONE,
+ BITFIELD(49, 4) /* index 1108 */,
+ TILEGX_OPC_V1MAXU, TILEGX_OPC_V1MINU, TILEGX_OPC_V1MNZ, TILEGX_OPC_V1MZ,
+ TILEGX_OPC_V1SHL, TILEGX_OPC_V1SHRS, TILEGX_OPC_V1SHRU, TILEGX_OPC_V1SUBUC,
+ TILEGX_OPC_V1SUB, TILEGX_OPC_V2ADDSC, TILEGX_OPC_V2ADD, TILEGX_OPC_V2CMPEQ,
+ TILEGX_OPC_V2CMPLES, TILEGX_OPC_V2CMPLEU, TILEGX_OPC_V2CMPLTS,
+ TILEGX_OPC_V2CMPLTU,
+ BITFIELD(49, 4) /* index 1125 */,
+ TILEGX_OPC_V2CMPNE, TILEGX_OPC_V2INT_H, TILEGX_OPC_V2INT_L,
+ TILEGX_OPC_V2MAXS, TILEGX_OPC_V2MINS, TILEGX_OPC_V2MNZ, TILEGX_OPC_V2MZ,
+ TILEGX_OPC_V2PACKH, TILEGX_OPC_V2PACKL, TILEGX_OPC_V2PACKUC,
+ TILEGX_OPC_V2SHLSC, TILEGX_OPC_V2SHL, TILEGX_OPC_V2SHRS, TILEGX_OPC_V2SHRU,
+ TILEGX_OPC_V2SUBSC, TILEGX_OPC_V2SUB,
+ BITFIELD(49, 4) /* index 1142 */,
+ TILEGX_OPC_V4ADDSC, TILEGX_OPC_V4ADD, TILEGX_OPC_V4INT_H,
+ TILEGX_OPC_V4INT_L, TILEGX_OPC_V4PACKSC, TILEGX_OPC_V4SHLSC,
+ TILEGX_OPC_V4SHL, TILEGX_OPC_V4SHRS, TILEGX_OPC_V4SHRU, TILEGX_OPC_V4SUBSC,
+ TILEGX_OPC_V4SUB, TILEGX_OPC_XOR, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ BITFIELD(49, 4) /* index 1159 */,
+ TILEGX_OPC_NONE, TILEGX_OPC_ROTLI, TILEGX_OPC_SHLI, TILEGX_OPC_SHLXI,
+ TILEGX_OPC_SHRSI, TILEGX_OPC_SHRUI, TILEGX_OPC_SHRUXI, TILEGX_OPC_V1SHLI,
+ TILEGX_OPC_V1SHRSI, TILEGX_OPC_V1SHRUI, TILEGX_OPC_V2SHLI,
+ TILEGX_OPC_V2SHRSI, TILEGX_OPC_V2SHRUI, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE,
+ BITFIELD(31, 2) /* index 1176 */,
+ TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
+ CHILD(1181),
+ BITFIELD(33, 2) /* index 1181 */,
+ TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
+ CHILD(1186),
+ BITFIELD(35, 2) /* index 1186 */,
+ TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
+ CHILD(1191),
+ BITFIELD(37, 2) /* index 1191 */,
+ TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
+ CHILD(1196),
+ BITFIELD(39, 2) /* index 1196 */,
+ TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
+ CHILD(1201),
+ BITFIELD(41, 2) /* index 1201 */,
+ TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI, TILEGX_OPC_SHL16INSLI,
+ TILEGX_OPC_INFOL,
+};
+
+static const unsigned short decode_Y0_fsm[178] =
+{
+ BITFIELD(27, 4) /* index 0 */,
+ CHILD(17), TILEGX_OPC_ADDXI, CHILD(32), TILEGX_OPC_CMPEQI,
+ TILEGX_OPC_CMPLTSI, CHILD(62), CHILD(67), CHILD(118), CHILD(123),
+ CHILD(128), CHILD(133), CHILD(153), CHILD(158), CHILD(163), CHILD(168),
+ CHILD(173),
+ BITFIELD(6, 2) /* index 17 */,
+ TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(22),
+ BITFIELD(8, 2) /* index 22 */,
+ TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(27),
+ BITFIELD(10, 2) /* index 27 */,
+ TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_MOVEI,
+ BITFIELD(0, 2) /* index 32 */,
+ TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(37),
+ BITFIELD(2, 2) /* index 37 */,
+ TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(42),
+ BITFIELD(4, 2) /* index 42 */,
+ TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(47),
+ BITFIELD(6, 2) /* index 47 */,
+ TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(52),
+ BITFIELD(8, 2) /* index 52 */,
+ TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(57),
+ BITFIELD(10, 2) /* index 57 */,
+ TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_INFO,
+ BITFIELD(18, 2) /* index 62 */,
+ TILEGX_OPC_ADDX, TILEGX_OPC_ADD, TILEGX_OPC_SUBX, TILEGX_OPC_SUB,
+ BITFIELD(15, 5) /* index 67 */,
+ TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD,
+ TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD,
+ TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL2ADD,
+ TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL2ADD,
+ TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL2ADD,
+ TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD,
+ TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD,
+ TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD, CHILD(100),
+ CHILD(109), TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ BITFIELD(12, 3) /* index 100 */,
+ TILEGX_OPC_NONE, TILEGX_OPC_CLZ, TILEGX_OPC_CTZ, TILEGX_OPC_FNOP,
+ TILEGX_OPC_FSINGLE_PACK1, TILEGX_OPC_NOP, TILEGX_OPC_PCNT,
+ TILEGX_OPC_REVBITS,
+ BITFIELD(12, 3) /* index 109 */,
+ TILEGX_OPC_REVBYTES, TILEGX_OPC_TBLIDXB0, TILEGX_OPC_TBLIDXB1,
+ TILEGX_OPC_TBLIDXB2, TILEGX_OPC_TBLIDXB3, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ TILEGX_OPC_NONE,
+ BITFIELD(18, 2) /* index 118 */,
+ TILEGX_OPC_CMPLES, TILEGX_OPC_CMPLEU, TILEGX_OPC_CMPLTS, TILEGX_OPC_CMPLTU,
+ BITFIELD(18, 2) /* index 123 */,
+ TILEGX_OPC_CMPEQ, TILEGX_OPC_CMPNE, TILEGX_OPC_MULAX, TILEGX_OPC_MULX,
+ BITFIELD(18, 2) /* index 128 */,
+ TILEGX_OPC_CMOVEQZ, TILEGX_OPC_CMOVNEZ, TILEGX_OPC_MNZ, TILEGX_OPC_MZ,
+ BITFIELD(18, 2) /* index 133 */,
+ TILEGX_OPC_AND, TILEGX_OPC_NOR, CHILD(138), TILEGX_OPC_XOR,
+ BITFIELD(12, 2) /* index 138 */,
+ TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(143),
+ BITFIELD(14, 2) /* index 143 */,
+ TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(148),
+ BITFIELD(16, 2) /* index 148 */,
+ TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_MOVE,
+ BITFIELD(18, 2) /* index 153 */,
+ TILEGX_OPC_ROTL, TILEGX_OPC_SHL, TILEGX_OPC_SHRS, TILEGX_OPC_SHRU,
+ BITFIELD(18, 2) /* index 158 */,
+ TILEGX_OPC_NONE, TILEGX_OPC_SHL1ADDX, TILEGX_OPC_SHL2ADDX,
+ TILEGX_OPC_SHL3ADDX,
+ BITFIELD(18, 2) /* index 163 */,
+ TILEGX_OPC_MUL_HS_HS, TILEGX_OPC_MUL_HU_HU, TILEGX_OPC_MUL_LS_LS,
+ TILEGX_OPC_MUL_LU_LU,
+ BITFIELD(18, 2) /* index 168 */,
+ TILEGX_OPC_MULA_HS_HS, TILEGX_OPC_MULA_HU_HU, TILEGX_OPC_MULA_LS_LS,
+ TILEGX_OPC_MULA_LU_LU,
+ BITFIELD(18, 2) /* index 173 */,
+ TILEGX_OPC_ROTLI, TILEGX_OPC_SHLI, TILEGX_OPC_SHRSI, TILEGX_OPC_SHRUI,
+};
+
+static const unsigned short decode_Y1_fsm[167] =
+{
+ BITFIELD(58, 4) /* index 0 */,
+ TILEGX_OPC_NONE, CHILD(17), TILEGX_OPC_ADDXI, CHILD(32), TILEGX_OPC_CMPEQI,
+ TILEGX_OPC_CMPLTSI, CHILD(62), CHILD(67), CHILD(117), CHILD(122),
+ CHILD(127), CHILD(132), CHILD(152), CHILD(157), CHILD(162), TILEGX_OPC_NONE,
+ BITFIELD(37, 2) /* index 17 */,
+ TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(22),
+ BITFIELD(39, 2) /* index 22 */,
+ TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, CHILD(27),
+ BITFIELD(41, 2) /* index 27 */,
+ TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_ADDI, TILEGX_OPC_MOVEI,
+ BITFIELD(31, 2) /* index 32 */,
+ TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(37),
+ BITFIELD(33, 2) /* index 37 */,
+ TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(42),
+ BITFIELD(35, 2) /* index 42 */,
+ TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(47),
+ BITFIELD(37, 2) /* index 47 */,
+ TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(52),
+ BITFIELD(39, 2) /* index 52 */,
+ TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, CHILD(57),
+ BITFIELD(41, 2) /* index 57 */,
+ TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_ANDI, TILEGX_OPC_INFO,
+ BITFIELD(49, 2) /* index 62 */,
+ TILEGX_OPC_ADDX, TILEGX_OPC_ADD, TILEGX_OPC_SUBX, TILEGX_OPC_SUB,
+ BITFIELD(47, 4) /* index 67 */,
+ TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL1ADD,
+ TILEGX_OPC_SHL1ADD, TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL2ADD,
+ TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL2ADD, TILEGX_OPC_SHL3ADD,
+ TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD, TILEGX_OPC_SHL3ADD, CHILD(84),
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_NONE,
+ BITFIELD(43, 3) /* index 84 */,
+ CHILD(93), CHILD(96), CHILD(99), CHILD(102), CHILD(105), CHILD(108),
+ CHILD(111), CHILD(114),
+ BITFIELD(46, 1) /* index 93 */,
+ TILEGX_OPC_NONE, TILEGX_OPC_FNOP,
+ BITFIELD(46, 1) /* index 96 */,
+ TILEGX_OPC_NONE, TILEGX_OPC_ILL,
+ BITFIELD(46, 1) /* index 99 */,
+ TILEGX_OPC_NONE, TILEGX_OPC_JALRP,
+ BITFIELD(46, 1) /* index 102 */,
+ TILEGX_OPC_NONE, TILEGX_OPC_JALR,
+ BITFIELD(46, 1) /* index 105 */,
+ TILEGX_OPC_NONE, TILEGX_OPC_JRP,
+ BITFIELD(46, 1) /* index 108 */,
+ TILEGX_OPC_NONE, TILEGX_OPC_JR,
+ BITFIELD(46, 1) /* index 111 */,
+ TILEGX_OPC_NONE, TILEGX_OPC_LNK,
+ BITFIELD(46, 1) /* index 114 */,
+ TILEGX_OPC_NONE, TILEGX_OPC_NOP,
+ BITFIELD(49, 2) /* index 117 */,
+ TILEGX_OPC_CMPLES, TILEGX_OPC_CMPLEU, TILEGX_OPC_CMPLTS, TILEGX_OPC_CMPLTU,
+ BITFIELD(49, 2) /* index 122 */,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_CMPEQ, TILEGX_OPC_CMPNE,
+ BITFIELD(49, 2) /* index 127 */,
+ TILEGX_OPC_NONE, TILEGX_OPC_NONE, TILEGX_OPC_MNZ, TILEGX_OPC_MZ,
+ BITFIELD(49, 2) /* index 132 */,
+ TILEGX_OPC_AND, TILEGX_OPC_NOR, CHILD(137), TILEGX_OPC_XOR,
+ BITFIELD(43, 2) /* index 137 */,
+ TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(142),
+ BITFIELD(45, 2) /* index 142 */,
+ TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, CHILD(147),
+ BITFIELD(47, 2) /* index 147 */,
+ TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_OR, TILEGX_OPC_MOVE,
+ BITFIELD(49, 2) /* index 152 */,
+ TILEGX_OPC_ROTL, TILEGX_OPC_SHL, TILEGX_OPC_SHRS, TILEGX_OPC_SHRU,
+ BITFIELD(49, 2) /* index 157 */,
+ TILEGX_OPC_NONE, TILEGX_OPC_SHL1ADDX, TILEGX_OPC_SHL2ADDX,
+ TILEGX_OPC_SHL3ADDX,
+ BITFIELD(49, 2) /* index 162 */,
+ TILEGX_OPC_ROTLI, TILEGX_OPC_SHLI, TILEGX_OPC_SHRSI, TILEGX_OPC_SHRUI,
+};
+
+static const unsigned short decode_Y2_fsm[118] =
+{
+ BITFIELD(62, 2) /* index 0 */,
+ TILEGX_OPC_NONE, CHILD(5), CHILD(66), CHILD(109),
+ BITFIELD(55, 3) /* index 5 */,
+ CHILD(14), CHILD(14), CHILD(14), CHILD(17), CHILD(40), CHILD(40), CHILD(40),
+ CHILD(43),
+ BITFIELD(26, 1) /* index 14 */,
+ TILEGX_OPC_LD1S, TILEGX_OPC_LD1U,
+ BITFIELD(26, 1) /* index 17 */,
+ CHILD(20), CHILD(30),
+ BITFIELD(51, 2) /* index 20 */,
+ TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, CHILD(25),
+ BITFIELD(53, 2) /* index 25 */,
+ TILEGX_OPC_LD1S, TILEGX_OPC_LD1S, TILEGX_OPC_LD1S,
+ TILEGX_OPC_PREFETCH_L1_FAULT,
+ BITFIELD(51, 2) /* index 30 */,
+ TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, CHILD(35),
+ BITFIELD(53, 2) /* index 35 */,
+ TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_LD1U, TILEGX_OPC_PREFETCH,
+ BITFIELD(26, 1) /* index 40 */,
+ TILEGX_OPC_LD2S, TILEGX_OPC_LD2U,
+ BITFIELD(26, 1) /* index 43 */,
+ CHILD(46), CHILD(56),
+ BITFIELD(51, 2) /* index 46 */,
+ TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, CHILD(51),
+ BITFIELD(53, 2) /* index 51 */,
+ TILEGX_OPC_LD2S, TILEGX_OPC_LD2S, TILEGX_OPC_LD2S,
+ TILEGX_OPC_PREFETCH_L2_FAULT,
+ BITFIELD(51, 2) /* index 56 */,
+ TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, CHILD(61),
+ BITFIELD(53, 2) /* index 61 */,
+ TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_LD2U, TILEGX_OPC_PREFETCH_L2,
+ BITFIELD(56, 2) /* index 66 */,
+ CHILD(71), CHILD(74), CHILD(90), CHILD(93),
+ BITFIELD(26, 1) /* index 71 */,
+ TILEGX_OPC_NONE, TILEGX_OPC_LD4S,
+ BITFIELD(26, 1) /* index 74 */,
+ TILEGX_OPC_NONE, CHILD(77),
+ BITFIELD(51, 2) /* index 77 */,
+ TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, CHILD(82),
+ BITFIELD(53, 2) /* index 82 */,
+ TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, TILEGX_OPC_LD4S, CHILD(87),
+ BITFIELD(55, 1) /* index 87 */,
+ TILEGX_OPC_LD4S, TILEGX_OPC_PREFETCH_L3_FAULT,
+ BITFIELD(26, 1) /* index 90 */,
+ TILEGX_OPC_LD4U, TILEGX_OPC_LD,
+ BITFIELD(26, 1) /* index 93 */,
+ CHILD(96), TILEGX_OPC_LD,
+ BITFIELD(51, 2) /* index 96 */,
+ TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, CHILD(101),
+ BITFIELD(53, 2) /* index 101 */,
+ TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, TILEGX_OPC_LD4U, CHILD(106),
+ BITFIELD(55, 1) /* index 106 */,
+ TILEGX_OPC_LD4U, TILEGX_OPC_PREFETCH_L3,
+ BITFIELD(26, 1) /* index 109 */,
+ CHILD(112), CHILD(115),
+ BITFIELD(57, 1) /* index 112 */,
+ TILEGX_OPC_ST1, TILEGX_OPC_ST4,
+ BITFIELD(57, 1) /* index 115 */,
+ TILEGX_OPC_ST2, TILEGX_OPC_ST,
+};
+
+#undef BITFIELD
+#undef CHILD
+const unsigned short * const
+tilegx_bundle_decoder_fsms[TILEGX_NUM_PIPELINE_ENCODINGS] =
+{
+ decode_X0_fsm,
+ decode_X1_fsm,
+ decode_Y0_fsm,
+ decode_Y1_fsm,
+ decode_Y2_fsm
+};
+const struct tilegx_operand tilegx_operands[35] =
+{
+ {
+ TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_IMM8_X0),
+ 8, 1, 0, 0, 0, 0,
+ create_Imm8_X0, get_Imm8_X0
+ },
+ {
+ TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_IMM8_X1),
+ 8, 1, 0, 0, 0, 0,
+ create_Imm8_X1, get_Imm8_X1
+ },
+ {
+ TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_IMM8_Y0),
+ 8, 1, 0, 0, 0, 0,
+ create_Imm8_Y0, get_Imm8_Y0
+ },
+ {
+ TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_IMM8_Y1),
+ 8, 1, 0, 0, 0, 0,
+ create_Imm8_Y1, get_Imm8_Y1
+ },
+ {
+ TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_IMM16_X0_HW0_LAST),
+ 16, 1, 0, 0, 0, 0,
+ create_Imm16_X0, get_Imm16_X0
+ },
+ {
+ TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_IMM16_X1_HW0_LAST),
+ 16, 1, 0, 0, 0, 0,
+ create_Imm16_X1, get_Imm16_X1
+ },
+ {
+ TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
+ 6, 0, 0, 1, 0, 0,
+ create_Dest_X0, get_Dest_X0
+ },
+ {
+ TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
+ 6, 0, 1, 0, 0, 0,
+ create_SrcA_X0, get_SrcA_X0
+ },
+ {
+ TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
+ 6, 0, 0, 1, 0, 0,
+ create_Dest_X1, get_Dest_X1
+ },
+ {
+ TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
+ 6, 0, 1, 0, 0, 0,
+ create_SrcA_X1, get_SrcA_X1
+ },
+ {
+ TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
+ 6, 0, 0, 1, 0, 0,
+ create_Dest_Y0, get_Dest_Y0
+ },
+ {
+ TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
+ 6, 0, 1, 0, 0, 0,
+ create_SrcA_Y0, get_SrcA_Y0
+ },
+ {
+ TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
+ 6, 0, 0, 1, 0, 0,
+ create_Dest_Y1, get_Dest_Y1
+ },
+ {
+ TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
+ 6, 0, 1, 0, 0, 0,
+ create_SrcA_Y1, get_SrcA_Y1
+ },
+ {
+ TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
+ 6, 0, 1, 0, 0, 0,
+ create_SrcA_Y2, get_SrcA_Y2
+ },
+ {
+ TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
+ 6, 0, 1, 1, 0, 0,
+ create_SrcA_X1, get_SrcA_X1
+ },
+ {
+ TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
+ 6, 0, 1, 0, 0, 0,
+ create_SrcB_X0, get_SrcB_X0
+ },
+ {
+ TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
+ 6, 0, 1, 0, 0, 0,
+ create_SrcB_X1, get_SrcB_X1
+ },
+ {
+ TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
+ 6, 0, 1, 0, 0, 0,
+ create_SrcB_Y0, get_SrcB_Y0
+ },
+ {
+ TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
+ 6, 0, 1, 0, 0, 0,
+ create_SrcB_Y1, get_SrcB_Y1
+ },
+ {
+ TILEGX_OP_TYPE_ADDRESS, BFD_RELOC(TILEGX_BROFF_X1),
+ 17, 1, 0, 0, 1, TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES,
+ create_BrOff_X1, get_BrOff_X1
+ },
+ {
+ TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(NONE),
+ 6, 0, 0, 0, 0, 0,
+ create_BFStart_X0, get_BFStart_X0
+ },
+ {
+ TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(NONE),
+ 6, 0, 0, 0, 0, 0,
+ create_BFEnd_X0, get_BFEnd_X0
+ },
+ {
+ TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
+ 6, 0, 1, 1, 0, 0,
+ create_Dest_X0, get_Dest_X0
+ },
+ {
+ TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
+ 6, 0, 1, 1, 0, 0,
+ create_Dest_Y0, get_Dest_Y0
+ },
+ {
+ TILEGX_OP_TYPE_ADDRESS, BFD_RELOC(TILEGX_JUMPOFF_X1),
+ 27, 1, 0, 0, 1, TILEGX_LOG2_BUNDLE_ALIGNMENT_IN_BYTES,
+ create_JumpOff_X1, get_JumpOff_X1
+ },
+ {
+ TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
+ 6, 0, 0, 1, 0, 0,
+ create_SrcBDest_Y2, get_SrcBDest_Y2
+ },
+ {
+ TILEGX_OP_TYPE_SPR, BFD_RELOC(TILEGX_MF_IMM14_X1),
+ 14, 0, 0, 0, 0, 0,
+ create_MF_Imm14_X1, get_MF_Imm14_X1
+ },
+ {
+ TILEGX_OP_TYPE_SPR, BFD_RELOC(TILEGX_MT_IMM14_X1),
+ 14, 0, 0, 0, 0, 0,
+ create_MT_Imm14_X1, get_MT_Imm14_X1
+ },
+ {
+ TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_SHAMT_X0),
+ 6, 0, 0, 0, 0, 0,
+ create_ShAmt_X0, get_ShAmt_X0
+ },
+ {
+ TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_SHAMT_X1),
+ 6, 0, 0, 0, 0, 0,
+ create_ShAmt_X1, get_ShAmt_X1
+ },
+ {
+ TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_SHAMT_Y0),
+ 6, 0, 0, 0, 0, 0,
+ create_ShAmt_Y0, get_ShAmt_Y0
+ },
+ {
+ TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_SHAMT_Y1),
+ 6, 0, 0, 0, 0, 0,
+ create_ShAmt_Y1, get_ShAmt_Y1
+ },
+ {
+ TILEGX_OP_TYPE_REGISTER, BFD_RELOC(NONE),
+ 6, 0, 1, 0, 0, 0,
+ create_SrcBDest_Y2, get_SrcBDest_Y2
+ },
+ {
+ TILEGX_OP_TYPE_IMMEDIATE, BFD_RELOC(TILEGX_DEST_IMM8_X1),
+ 8, 1, 0, 0, 0, 0,
+ create_Dest_Imm8_X1, get_Dest_Imm8_X1
+ }
+};
+
+
+
+
+/* Given a set of bundle bits and the lookup FSM for a specific pipe,
+ * returns which instruction the bundle contains in that pipe.
+ */
+static const struct tilegx_opcode *
+find_opcode(tilegx_bundle_bits bits, const unsigned short *table)
+{
+ int index = 0;
+
+ while (1)
+ {
+ unsigned short bitspec = table[index];
+ unsigned int bitfield =
+ ((unsigned int)(bits >> (bitspec & 63))) & (bitspec >> 6);
+
+ unsigned short next = table[index + 1 + bitfield];
+ if (next <= TILEGX_OPC_NONE)
+ return &tilegx_opcodes[next];
+
+ index = next - TILEGX_OPC_NONE;
+ }
+}
+
+
+int
+parse_insn_tilegx(tilegx_bundle_bits bits,
+ unsigned long long pc,
+ struct tilegx_decoded_instruction
+ decoded[TILEGX_MAX_INSTRUCTIONS_PER_BUNDLE])
+{
+ int num_instructions = 0;
+ int pipe;
+
+ int min_pipe, max_pipe;
+ if ((bits & TILEGX_BUNDLE_MODE_MASK) == 0)
+ {
+ min_pipe = TILEGX_PIPELINE_X0;
+ max_pipe = TILEGX_PIPELINE_X1;
+ }
+ else
+ {
+ min_pipe = TILEGX_PIPELINE_Y0;
+ max_pipe = TILEGX_PIPELINE_Y2;
+ }
+
+ /* For each pipe, find an instruction that fits. */
+ for (pipe = min_pipe; pipe <= max_pipe; pipe++)
+ {
+ const struct tilegx_opcode *opc;
+ struct tilegx_decoded_instruction *d;
+ int i;
+
+ d = &decoded[num_instructions++];
+ opc = find_opcode (bits, tilegx_bundle_decoder_fsms[pipe]);
+ d->opcode = opc;
+
+ /* Decode each operand, sign extending, etc. as appropriate. */
+ for (i = 0; i < opc->num_operands; i++)
+ {
+ const struct tilegx_operand *op =
+ &tilegx_operands[opc->operands[pipe][i]];
+ int raw_opval = op->extract (bits);
+ long long opval;
+
+ if (op->is_signed)
+ {
+ /* Sign-extend the operand. */
+ int shift = (int)((sizeof(int) * 8) - op->num_bits);
+ raw_opval = (raw_opval << shift) >> shift;
+ }
+
+ /* Adjust PC-relative scaled branch offsets. */
+ if (op->type == TILEGX_OP_TYPE_ADDRESS)
+ opval = (raw_opval * TILEGX_BUNDLE_SIZE_IN_BYTES) + pc;
+ else
+ opval = raw_opval;
+
+ /* Record the final value. */
+ d->operands[i] = op;
+ d->operand_values[i] = opval;
+ }
+ }
+
+ return num_instructions;
+}
diff --git a/arch/tile/kernel/time.c b/arch/tile/kernel/time.c
index 49a605b..c4be58c 100644
--- a/arch/tile/kernel/time.c
+++ b/arch/tile/kernel/time.c
@@ -22,6 +22,7 @@
#include <linux/sched.h>
#include <linux/smp.h>
#include <linux/delay.h>
+#include <linux/module.h>
#include <asm/irq_regs.h>
#include <asm/traps.h>
#include <hv/hypervisor.h>
@@ -56,6 +57,7 @@
return (((cycles_t)high) << 32) | low;
}
+EXPORT_SYMBOL(get_cycles);
#endif
/*
diff --git a/arch/tile/kernel/tlb.c b/arch/tile/kernel/tlb.c
index 2dffc10..a5f241c 100644
--- a/arch/tile/kernel/tlb.c
+++ b/arch/tile/kernel/tlb.c
@@ -34,13 +34,13 @@
{
HV_Remote_ASID asids[NR_CPUS];
int i = 0, cpu;
- for_each_cpu(cpu, &mm->cpu_vm_mask) {
+ for_each_cpu(cpu, mm_cpumask(mm)) {
HV_Remote_ASID *asid = &asids[i++];
asid->y = cpu / smp_topology.width;
asid->x = cpu % smp_topology.width;
asid->asid = per_cpu(current_asid, cpu);
}
- flush_remote(0, HV_FLUSH_EVICT_L1I, &mm->cpu_vm_mask,
+ flush_remote(0, HV_FLUSH_EVICT_L1I, mm_cpumask(mm),
0, 0, 0, NULL, asids, i);
}
@@ -54,8 +54,8 @@
{
unsigned long size = hv_page_size(vma);
int cache = (vma->vm_flags & VM_EXEC) ? HV_FLUSH_EVICT_L1I : 0;
- flush_remote(0, cache, &mm->cpu_vm_mask,
- va, size, size, &mm->cpu_vm_mask, NULL, 0);
+ flush_remote(0, cache, mm_cpumask(mm),
+ va, size, size, mm_cpumask(mm), NULL, 0);
}
void flush_tlb_page(const struct vm_area_struct *vma, unsigned long va)
@@ -70,8 +70,8 @@
unsigned long size = hv_page_size(vma);
struct mm_struct *mm = vma->vm_mm;
int cache = (vma->vm_flags & VM_EXEC) ? HV_FLUSH_EVICT_L1I : 0;
- flush_remote(0, cache, &mm->cpu_vm_mask, start, end - start, size,
- &mm->cpu_vm_mask, NULL, 0);
+ flush_remote(0, cache, mm_cpumask(mm), start, end - start, size,
+ mm_cpumask(mm), NULL, 0);
}
void flush_tlb_all(void)
diff --git a/arch/tile/kernel/traps.c b/arch/tile/kernel/traps.c
index 5474fc2..f9803df 100644
--- a/arch/tile/kernel/traps.c
+++ b/arch/tile/kernel/traps.c
@@ -308,6 +308,7 @@
info.si_addr = (void __user *)address;
if (signo == SIGILL)
info.si_trapno = fault_num;
+ trace_unhandled_signal("trap", regs, address, signo);
force_sig_info(signo, &info, current);
}
diff --git a/arch/tile/kernel/vmlinux.lds.S b/arch/tile/kernel/vmlinux.lds.S
index 38f64fa..631f10d 100644
--- a/arch/tile/kernel/vmlinux.lds.S
+++ b/arch/tile/kernel/vmlinux.lds.S
@@ -60,7 +60,7 @@
. = ALIGN(PAGE_SIZE);
VMLINUX_SYMBOL(_sinitdata) = .;
INIT_DATA_SECTION(16) :data =0
- PERCPU(L2_CACHE_BYTES, PAGE_SIZE)
+ PERCPU_SECTION(L2_CACHE_BYTES)
. = ALIGN(PAGE_SIZE);
VMLINUX_SYMBOL(_einitdata) = .;
diff --git a/arch/tile/lib/atomic_asm_32.S b/arch/tile/lib/atomic_asm_32.S
index 82f64cc..2444873 100644
--- a/arch/tile/lib/atomic_asm_32.S
+++ b/arch/tile/lib/atomic_asm_32.S
@@ -59,7 +59,7 @@
* bad kernel addresses).
*
* Note that if the value we would store is the same as what we
- * loaded, we bypass the load. Other platforms with true atomics can
+ * loaded, we bypass the store. Other platforms with true atomics can
* make the guarantee that a non-atomic __clear_bit(), for example,
* can safely race with an atomic test_and_set_bit(); this example is
* from bit_spinlock.h in slub_lock() / slub_unlock(). We can't do
diff --git a/arch/tile/lib/cacheflush.c b/arch/tile/lib/cacheflush.c
index 35c1d8c..8928aac 100644
--- a/arch/tile/lib/cacheflush.c
+++ b/arch/tile/lib/cacheflush.c
@@ -15,6 +15,7 @@
#include <asm/page.h>
#include <asm/cacheflush.h>
#include <arch/icache.h>
+#include <arch/spr_def.h>
void __flush_icache_range(unsigned long start, unsigned long end)
@@ -39,6 +40,18 @@
char *p, *base;
size_t step_size, load_count;
const unsigned long STRIPE_WIDTH = 8192;
+#ifdef __tilegx__
+ /*
+ * On TILE-Gx, we must disable the dstream prefetcher before doing
+ * a cache flush; otherwise, we could end up with data in the cache
+ * that we don't want there. Note that normally we'd do an mf
+ * after the SPR write to disabling the prefetcher, but we do one
+ * below, before any further loads, so there's no need to do it
+ * here.
+ */
+ uint_reg_t old_dstream_pf = __insn_mfspr(SPR_DSTREAM_PF);
+ __insn_mtspr(SPR_DSTREAM_PF, 0);
+#endif
/*
* Flush and invalidate the buffer out of the local L1/L2
@@ -122,4 +135,9 @@
/* Wait for the load+inv's (and thus finvs) to have completed. */
__insn_mf();
+
+#ifdef __tilegx__
+ /* Reenable the prefetcher. */
+ __insn_mtspr(SPR_DSTREAM_PF, old_dstream_pf);
+#endif
}
diff --git a/arch/tile/lib/memchr_64.c b/arch/tile/lib/memchr_64.c
new file mode 100644
index 0000000..84fdc8d
--- /dev/null
+++ b/arch/tile/lib/memchr_64.c
@@ -0,0 +1,71 @@
+/*
+ * Copyright 2011 Tilera Corporation. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ * NON INFRINGEMENT. See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/module.h>
+
+void *memchr(const void *s, int c, size_t n)
+{
+ const uint64_t *last_word_ptr;
+ const uint64_t *p;
+ const char *last_byte_ptr;
+ uintptr_t s_int;
+ uint64_t goal, before_mask, v, bits;
+ char *ret;
+
+ if (__builtin_expect(n == 0, 0)) {
+ /* Don't dereference any memory if the array is empty. */
+ return NULL;
+ }
+
+ /* Get an aligned pointer. */
+ s_int = (uintptr_t) s;
+ p = (const uint64_t *)(s_int & -8);
+
+ /* Create eight copies of the byte for which we are looking. */
+ goal = 0x0101010101010101ULL * (uint8_t) c;
+
+ /* Read the first word, but munge it so that bytes before the array
+ * will not match goal.
+ *
+ * Note that this shift count expression works because we know
+ * shift counts are taken mod 64.
+ */
+ before_mask = (1ULL << (s_int << 3)) - 1;
+ v = (*p | before_mask) ^ (goal & before_mask);
+
+ /* Compute the address of the last byte. */
+ last_byte_ptr = (const char *)s + n - 1;
+
+ /* Compute the address of the word containing the last byte. */
+ last_word_ptr = (const uint64_t *)((uintptr_t) last_byte_ptr & -8);
+
+ while ((bits = __insn_v1cmpeq(v, goal)) == 0) {
+ if (__builtin_expect(p == last_word_ptr, 0)) {
+ /* We already read the last word in the array,
+ * so give up.
+ */
+ return NULL;
+ }
+ v = *++p;
+ }
+
+ /* We found a match, but it might be in a byte past the end
+ * of the array.
+ */
+ ret = ((char *)p) + (__insn_ctz(bits) >> 3);
+ return (ret <= last_byte_ptr) ? ret : NULL;
+}
+EXPORT_SYMBOL(memchr);
diff --git a/arch/tile/lib/memcpy_64.c b/arch/tile/lib/memcpy_64.c
new file mode 100644
index 0000000..3fab9a6
--- /dev/null
+++ b/arch/tile/lib/memcpy_64.c
@@ -0,0 +1,220 @@
+/*
+ * Copyright 2011 Tilera Corporation. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ * NON INFRINGEMENT. See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/module.h>
+#define __memcpy memcpy
+/* EXPORT_SYMBOL() is in arch/tile/lib/exports.c since this should be asm. */
+
+/* Must be 8 bytes in size. */
+#define word_t uint64_t
+
+#if CHIP_L2_LINE_SIZE() != 64 && CHIP_L2_LINE_SIZE() != 128
+#error "Assumes 64 or 128 byte line size"
+#endif
+
+/* How many cache lines ahead should we prefetch? */
+#define PREFETCH_LINES_AHEAD 3
+
+/*
+ * Provide "base versions" of load and store for the normal code path.
+ * The kernel provides other versions for userspace copies.
+ */
+#define ST(p, v) (*(p) = (v))
+#define LD(p) (*(p))
+
+#ifndef USERCOPY_FUNC
+#define ST1 ST
+#define ST2 ST
+#define ST4 ST
+#define ST8 ST
+#define LD1 LD
+#define LD2 LD
+#define LD4 LD
+#define LD8 LD
+#define RETVAL dstv
+void *memcpy(void *__restrict dstv, const void *__restrict srcv, size_t n)
+#else
+/*
+ * Special kernel version will provide implementation of the LDn/STn
+ * macros to return a count of uncopied bytes due to mm fault.
+ */
+#define RETVAL 0
+int USERCOPY_FUNC(void *__restrict dstv, const void *__restrict srcv, size_t n)
+#endif
+{
+ char *__restrict dst1 = (char *)dstv;
+ const char *__restrict src1 = (const char *)srcv;
+ const char *__restrict src1_end;
+ const char *__restrict prefetch;
+ word_t *__restrict dst8; /* 8-byte pointer to destination memory. */
+ word_t final; /* Final bytes to write to trailing word, if any */
+ long i;
+
+ if (n < 16) {
+ for (; n; n--)
+ ST1(dst1++, LD1(src1++));
+ return RETVAL;
+ }
+
+ /*
+ * Locate the end of source memory we will copy. Don't
+ * prefetch past this.
+ */
+ src1_end = src1 + n - 1;
+
+ /* Prefetch ahead a few cache lines, but not past the end. */
+ prefetch = src1;
+ for (i = 0; i < PREFETCH_LINES_AHEAD; i++) {
+ __insn_prefetch(prefetch);
+ prefetch += CHIP_L2_LINE_SIZE();
+ prefetch = (prefetch > src1_end) ? prefetch : src1;
+ }
+
+ /* Copy bytes until dst is word-aligned. */
+ for (; (uintptr_t)dst1 & (sizeof(word_t) - 1); n--)
+ ST1(dst1++, LD1(src1++));
+
+ /* 8-byte pointer to destination memory. */
+ dst8 = (word_t *)dst1;
+
+ if (__builtin_expect((uintptr_t)src1 & (sizeof(word_t) - 1), 0)) {
+ /*
+ * Misaligned copy. Copy 8 bytes at a time, but don't
+ * bother with other fanciness.
+ *
+ * TODO: Consider prefetching and using wh64 as well.
+ */
+
+ /* Create an aligned src8. */
+ const word_t *__restrict src8 =
+ (const word_t *)((uintptr_t)src1 & -sizeof(word_t));
+ word_t b;
+
+ word_t a = LD8(src8++);
+ for (; n >= sizeof(word_t); n -= sizeof(word_t)) {
+ b = LD8(src8++);
+ a = __insn_dblalign(a, b, src1);
+ ST8(dst8++, a);
+ a = b;
+ }
+
+ if (n == 0)
+ return RETVAL;
+
+ b = ((const char *)src8 <= src1_end) ? *src8 : 0;
+
+ /*
+ * Final source bytes to write to trailing partial
+ * word, if any.
+ */
+ final = __insn_dblalign(a, b, src1);
+ } else {
+ /* Aligned copy. */
+
+ const word_t* __restrict src8 = (const word_t *)src1;
+
+ /* src8 and dst8 are both word-aligned. */
+ if (n >= CHIP_L2_LINE_SIZE()) {
+ /* Copy until 'dst' is cache-line-aligned. */
+ for (; (uintptr_t)dst8 & (CHIP_L2_LINE_SIZE() - 1);
+ n -= sizeof(word_t))
+ ST8(dst8++, LD8(src8++));
+
+ for (; n >= CHIP_L2_LINE_SIZE(); ) {
+ __insn_wh64(dst8);
+
+ /*
+ * Prefetch and advance to next line
+ * to prefetch, but don't go past the end
+ */
+ __insn_prefetch(prefetch);
+ prefetch += CHIP_L2_LINE_SIZE();
+ prefetch = (prefetch > src1_end) ? prefetch :
+ (const char *)src8;
+
+ /*
+ * Copy an entire cache line. Manually
+ * unrolled to avoid idiosyncracies of
+ * compiler unrolling.
+ */
+#define COPY_WORD(offset) ({ ST8(dst8+offset, LD8(src8+offset)); n -= 8; })
+ COPY_WORD(0);
+ COPY_WORD(1);
+ COPY_WORD(2);
+ COPY_WORD(3);
+ COPY_WORD(4);
+ COPY_WORD(5);
+ COPY_WORD(6);
+ COPY_WORD(7);
+#if CHIP_L2_LINE_SIZE() == 128
+ COPY_WORD(8);
+ COPY_WORD(9);
+ COPY_WORD(10);
+ COPY_WORD(11);
+ COPY_WORD(12);
+ COPY_WORD(13);
+ COPY_WORD(14);
+ COPY_WORD(15);
+#elif CHIP_L2_LINE_SIZE() != 64
+# error Fix code that assumes particular L2 cache line sizes
+#endif
+
+ dst8 += CHIP_L2_LINE_SIZE() / sizeof(word_t);
+ src8 += CHIP_L2_LINE_SIZE() / sizeof(word_t);
+ }
+ }
+
+ for (; n >= sizeof(word_t); n -= sizeof(word_t))
+ ST8(dst8++, LD8(src8++));
+
+ if (__builtin_expect(n == 0, 1))
+ return RETVAL;
+
+ final = LD8(src8);
+ }
+
+ /* n != 0 if we get here. Write out any trailing bytes. */
+ dst1 = (char *)dst8;
+ if (n & 4) {
+ ST4((uint32_t *)dst1, final);
+ dst1 += 4;
+ final >>= 32;
+ n &= 3;
+ }
+ if (n & 2) {
+ ST2((uint16_t *)dst1, final);
+ dst1 += 2;
+ final >>= 16;
+ n &= 1;
+ }
+ if (n)
+ ST1((uint8_t *)dst1, final);
+
+ return RETVAL;
+}
+
+
+#ifdef USERCOPY_FUNC
+#undef ST1
+#undef ST2
+#undef ST4
+#undef ST8
+#undef LD1
+#undef LD2
+#undef LD4
+#undef LD8
+#undef USERCOPY_FUNC
+#endif
diff --git a/arch/tile/lib/memcpy_user_64.c b/arch/tile/lib/memcpy_user_64.c
new file mode 100644
index 0000000..4763b3a
--- /dev/null
+++ b/arch/tile/lib/memcpy_user_64.c
@@ -0,0 +1,86 @@
+/*
+ * Copyright 2011 Tilera Corporation. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ * NON INFRINGEMENT. See the GNU General Public License for
+ * more details.
+ *
+ * Do memcpy(), but trap and return "n" when a load or store faults.
+ *
+ * Note: this idiom only works when memcpy() compiles to a leaf function.
+ * If "sp" is updated during memcpy, the "jrp lr" will be incorrect.
+ *
+ * Also note that we are capturing "n" from the containing scope here.
+ */
+
+#define _ST(p, inst, v) \
+ ({ \
+ asm("1: " #inst " %0, %1;" \
+ ".pushsection .coldtext.memcpy,\"ax\";" \
+ "2: { move r0, %2; jrp lr };" \
+ ".section __ex_table,\"a\";" \
+ ".quad 1b, 2b;" \
+ ".popsection" \
+ : "=m" (*(p)) : "r" (v), "r" (n)); \
+ })
+
+#define _LD(p, inst) \
+ ({ \
+ unsigned long __v; \
+ asm("1: " #inst " %0, %1;" \
+ ".pushsection .coldtext.memcpy,\"ax\";" \
+ "2: { move r0, %2; jrp lr };" \
+ ".section __ex_table,\"a\";" \
+ ".quad 1b, 2b;" \
+ ".popsection" \
+ : "=r" (__v) : "m" (*(p)), "r" (n)); \
+ __v; \
+ })
+
+#define USERCOPY_FUNC __copy_to_user_inatomic
+#define ST1(p, v) _ST((p), st1, (v))
+#define ST2(p, v) _ST((p), st2, (v))
+#define ST4(p, v) _ST((p), st4, (v))
+#define ST8(p, v) _ST((p), st, (v))
+#define LD1 LD
+#define LD2 LD
+#define LD4 LD
+#define LD8 LD
+#include "memcpy_64.c"
+
+#define USERCOPY_FUNC __copy_from_user_inatomic
+#define ST1 ST
+#define ST2 ST
+#define ST4 ST
+#define ST8 ST
+#define LD1(p) _LD((p), ld1u)
+#define LD2(p) _LD((p), ld2u)
+#define LD4(p) _LD((p), ld4u)
+#define LD8(p) _LD((p), ld)
+#include "memcpy_64.c"
+
+#define USERCOPY_FUNC __copy_in_user_inatomic
+#define ST1(p, v) _ST((p), st1, (v))
+#define ST2(p, v) _ST((p), st2, (v))
+#define ST4(p, v) _ST((p), st4, (v))
+#define ST8(p, v) _ST((p), st, (v))
+#define LD1(p) _LD((p), ld1u)
+#define LD2(p) _LD((p), ld2u)
+#define LD4(p) _LD((p), ld4u)
+#define LD8(p) _LD((p), ld)
+#include "memcpy_64.c"
+
+unsigned long __copy_from_user_zeroing(void *to, const void __user *from,
+ unsigned long n)
+{
+ unsigned long rc = __copy_from_user_inatomic(to, from, n);
+ if (unlikely(rc))
+ memset(to + n - rc, 0, rc);
+ return rc;
+}
diff --git a/arch/tile/lib/memset_64.c b/arch/tile/lib/memset_64.c
new file mode 100644
index 0000000..3873085
--- /dev/null
+++ b/arch/tile/lib/memset_64.c
@@ -0,0 +1,145 @@
+/*
+ * Copyright 2011 Tilera Corporation. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ * NON INFRINGEMENT. See the GNU General Public License for
+ * more details.
+ */
+
+#include <arch/chip.h>
+
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/module.h>
+
+#undef memset
+
+void *memset(void *s, int c, size_t n)
+{
+ uint64_t *out64;
+ int n64, to_align64;
+ uint64_t v64;
+ uint8_t *out8 = s;
+
+ /* Experimentation shows that a trivial tight loop is a win up until
+ * around a size of 20, where writing a word at a time starts to win.
+ */
+#define BYTE_CUTOFF 20
+
+#if BYTE_CUTOFF < 7
+ /* This must be at least at least this big, or some code later
+ * on doesn't work.
+ */
+#error "BYTE_CUTOFF is too small"
+#endif
+
+ if (n < BYTE_CUTOFF) {
+ /* Strangely, this turns out to be the tightest way to
+ * write this loop.
+ */
+ if (n != 0) {
+ do {
+ /* Strangely, combining these into one line
+ * performs worse.
+ */
+ *out8 = c;
+ out8++;
+ } while (--n != 0);
+ }
+
+ return s;
+ }
+
+ /* Align 'out8'. We know n >= 7 so this won't write past the end. */
+ while (((uintptr_t) out8 & 7) != 0) {
+ *out8++ = c;
+ --n;
+ }
+
+ /* Align 'n'. */
+ while (n & 7)
+ out8[--n] = c;
+
+ out64 = (uint64_t *) out8;
+ n64 = n >> 3;
+
+ /* Tile input byte out to 64 bits. */
+ /* KLUDGE */
+ v64 = 0x0101010101010101ULL * (uint8_t)c;
+
+ /* This must be at least 8 or the following loop doesn't work. */
+#define CACHE_LINE_SIZE_IN_DOUBLEWORDS (CHIP_L2_LINE_SIZE() / 8)
+
+ /* Determine how many words we need to emit before the 'out32'
+ * pointer becomes aligned modulo the cache line size.
+ */
+ to_align64 = (-((uintptr_t)out64 >> 3)) &
+ (CACHE_LINE_SIZE_IN_DOUBLEWORDS - 1);
+
+ /* Only bother aligning and using wh64 if there is at least
+ * one full cache line to process. This check also prevents
+ * overrunning the end of the buffer with alignment words.
+ */
+ if (to_align64 <= n64 - CACHE_LINE_SIZE_IN_DOUBLEWORDS) {
+ int lines_left;
+
+ /* Align out64 mod the cache line size so we can use wh64. */
+ n64 -= to_align64;
+ for (; to_align64 != 0; to_align64--) {
+ *out64 = v64;
+ out64++;
+ }
+
+ /* Use unsigned divide to turn this into a right shift. */
+ lines_left = (unsigned)n64 / CACHE_LINE_SIZE_IN_DOUBLEWORDS;
+
+ do {
+ /* Only wh64 a few lines at a time, so we don't
+ * exceed the maximum number of victim lines.
+ */
+ int x = ((lines_left < CHIP_MAX_OUTSTANDING_VICTIMS())
+ ? lines_left
+ : CHIP_MAX_OUTSTANDING_VICTIMS());
+ uint64_t *wh = out64;
+ int i = x;
+ int j;
+
+ lines_left -= x;
+
+ do {
+ __insn_wh64(wh);
+ wh += CACHE_LINE_SIZE_IN_DOUBLEWORDS;
+ } while (--i);
+
+ for (j = x * (CACHE_LINE_SIZE_IN_DOUBLEWORDS / 4);
+ j != 0; j--) {
+ *out64++ = v64;
+ *out64++ = v64;
+ *out64++ = v64;
+ *out64++ = v64;
+ }
+ } while (lines_left != 0);
+
+ /* We processed all full lines above, so only this many
+ * words remain to be processed.
+ */
+ n64 &= CACHE_LINE_SIZE_IN_DOUBLEWORDS - 1;
+ }
+
+ /* Now handle any leftover values. */
+ if (n64 != 0) {
+ do {
+ *out64 = v64;
+ out64++;
+ } while (--n64 != 0);
+ }
+
+ return s;
+}
+EXPORT_SYMBOL(memset);
diff --git a/arch/tile/lib/spinlock_64.c b/arch/tile/lib/spinlock_64.c
new file mode 100644
index 0000000..d6fb958
--- /dev/null
+++ b/arch/tile/lib/spinlock_64.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright 2011 Tilera Corporation. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ * NON INFRINGEMENT. See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/spinlock.h>
+#include <linux/module.h>
+#include <asm/processor.h>
+
+#include "spinlock_common.h"
+
+/*
+ * Read the spinlock value without allocating in our cache and without
+ * causing an invalidation to another cpu with a copy of the cacheline.
+ * This is important when we are spinning waiting for the lock.
+ */
+static inline u32 arch_spin_read_noalloc(void *lock)
+{
+ return atomic_cmpxchg((atomic_t *)lock, -1, -1);
+}
+
+/*
+ * Wait until the high bits (current) match my ticket.
+ * If we notice the overflow bit set on entry, we clear it.
+ */
+void arch_spin_lock_slow(arch_spinlock_t *lock, u32 my_ticket)
+{
+ if (unlikely(my_ticket & __ARCH_SPIN_NEXT_OVERFLOW)) {
+ __insn_fetchand4(&lock->lock, ~__ARCH_SPIN_NEXT_OVERFLOW);
+ my_ticket &= ~__ARCH_SPIN_NEXT_OVERFLOW;
+ }
+
+ for (;;) {
+ u32 val = arch_spin_read_noalloc(lock);
+ u32 delta = my_ticket - arch_spin_current(val);
+ if (delta == 0)
+ return;
+ relax((128 / CYCLES_PER_RELAX_LOOP) * delta);
+ }
+}
+EXPORT_SYMBOL(arch_spin_lock_slow);
+
+/*
+ * Check the lock to see if it is plausible, and try to get it with cmpxchg().
+ */
+int arch_spin_trylock(arch_spinlock_t *lock)
+{
+ u32 val = arch_spin_read_noalloc(lock);
+ if (unlikely(arch_spin_current(val) != arch_spin_next(val)))
+ return 0;
+ return cmpxchg(&lock->lock, val, (val + 1) & ~__ARCH_SPIN_NEXT_OVERFLOW)
+ == val;
+}
+EXPORT_SYMBOL(arch_spin_trylock);
+
+void arch_spin_unlock_wait(arch_spinlock_t *lock)
+{
+ u32 iterations = 0;
+ while (arch_spin_is_locked(lock))
+ delay_backoff(iterations++);
+}
+EXPORT_SYMBOL(arch_spin_unlock_wait);
+
+/*
+ * If the read lock fails due to a writer, we retry periodically
+ * until the value is positive and we write our incremented reader count.
+ */
+void __read_lock_failed(arch_rwlock_t *rw)
+{
+ u32 val;
+ int iterations = 0;
+ do {
+ delay_backoff(iterations++);
+ val = __insn_fetchaddgez4(&rw->lock, 1);
+ } while (unlikely(arch_write_val_locked(val)));
+}
+EXPORT_SYMBOL(__read_lock_failed);
+
+/*
+ * If we failed because there were readers, clear the "writer" bit
+ * so we don't block additional readers. Otherwise, there was another
+ * writer anyway, so our "fetchor" made no difference. Then wait,
+ * issuing periodic fetchor instructions, till we get the lock.
+ */
+void __write_lock_failed(arch_rwlock_t *rw, u32 val)
+{
+ int iterations = 0;
+ do {
+ if (!arch_write_val_locked(val))
+ val = __insn_fetchand4(&rw->lock, ~__WRITE_LOCK_BIT);
+ delay_backoff(iterations++);
+ val = __insn_fetchor4(&rw->lock, __WRITE_LOCK_BIT);
+ } while (val != 0);
+}
+EXPORT_SYMBOL(__write_lock_failed);
diff --git a/arch/tile/lib/strchr_64.c b/arch/tile/lib/strchr_64.c
new file mode 100644
index 0000000..617a927
--- /dev/null
+++ b/arch/tile/lib/strchr_64.c
@@ -0,0 +1,67 @@
+/*
+ * Copyright 2011 Tilera Corporation. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ * NON INFRINGEMENT. See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/module.h>
+
+#undef strchr
+
+char *strchr(const char *s, int c)
+{
+ int z, g;
+
+ /* Get an aligned pointer. */
+ const uintptr_t s_int = (uintptr_t) s;
+ const uint64_t *p = (const uint64_t *)(s_int & -8);
+
+ /* Create eight copies of the byte for which we are looking. */
+ const uint64_t goal = 0x0101010101010101ULL * (uint8_t) c;
+
+ /* Read the first aligned word, but force bytes before the string to
+ * match neither zero nor goal (we make sure the high bit of each
+ * byte is 1, and the low 7 bits are all the opposite of the goal
+ * byte).
+ *
+ * Note that this shift count expression works because we know shift
+ * counts are taken mod 64.
+ */
+ const uint64_t before_mask = (1ULL << (s_int << 3)) - 1;
+ uint64_t v = (*p | before_mask) ^
+ (goal & __insn_v1shrsi(before_mask, 1));
+
+ uint64_t zero_matches, goal_matches;
+ while (1) {
+ /* Look for a terminating '\0'. */
+ zero_matches = __insn_v1cmpeqi(v, 0);
+
+ /* Look for the goal byte. */
+ goal_matches = __insn_v1cmpeq(v, goal);
+
+ if (__builtin_expect((zero_matches | goal_matches) != 0, 0))
+ break;
+
+ v = *++p;
+ }
+
+ z = __insn_ctz(zero_matches);
+ g = __insn_ctz(goal_matches);
+
+ /* If we found c before '\0' we got a match. Note that if c == '\0'
+ * then g == z, and we correctly return the address of the '\0'
+ * rather than NULL.
+ */
+ return (g <= z) ? ((char *)p) + (g >> 3) : NULL;
+}
+EXPORT_SYMBOL(strchr);
diff --git a/arch/tile/lib/strlen_64.c b/arch/tile/lib/strlen_64.c
new file mode 100644
index 0000000..1c92d46
--- /dev/null
+++ b/arch/tile/lib/strlen_64.c
@@ -0,0 +1,38 @@
+/*
+ * Copyright 2011 Tilera Corporation. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ * NON INFRINGEMENT. See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/module.h>
+
+#undef strlen
+
+size_t strlen(const char *s)
+{
+ /* Get an aligned pointer. */
+ const uintptr_t s_int = (uintptr_t) s;
+ const uint64_t *p = (const uint64_t *)(s_int & -8);
+
+ /* Read the first word, but force bytes before the string to be nonzero.
+ * This expression works because we know shift counts are taken mod 64.
+ */
+ uint64_t v = *p | ((1ULL << (s_int << 3)) - 1);
+
+ uint64_t bits;
+ while ((bits = __insn_v1cmpeqi(v, 0)) == 0)
+ v = *++p;
+
+ return ((const char *)p) + (__insn_ctz(bits) >> 3) - s;
+}
+EXPORT_SYMBOL(strlen);
diff --git a/arch/tile/lib/usercopy_64.S b/arch/tile/lib/usercopy_64.S
new file mode 100644
index 0000000..2ff44f8
--- /dev/null
+++ b/arch/tile/lib/usercopy_64.S
@@ -0,0 +1,196 @@
+/*
+ * Copyright 2011 Tilera Corporation. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ * NON INFRINGEMENT. See the GNU General Public License for
+ * more details.
+ */
+
+#include <linux/linkage.h>
+#include <asm/errno.h>
+#include <asm/cache.h>
+#include <arch/chip.h>
+
+/* Access user memory, but use MMU to avoid propagating kernel exceptions. */
+
+ .pushsection .fixup,"ax"
+
+get_user_fault:
+ { movei r1, -EFAULT; move r0, zero }
+ jrp lr
+ ENDPROC(get_user_fault)
+
+put_user_fault:
+ { movei r0, -EFAULT; jrp lr }
+ ENDPROC(put_user_fault)
+
+ .popsection
+
+/*
+ * __get_user_N functions take a pointer in r0, and return 0 in r1
+ * on success, with the value in r0; or else -EFAULT in r1.
+ */
+#define __get_user_N(bytes, LOAD) \
+ STD_ENTRY(__get_user_##bytes); \
+1: { LOAD r0, r0; move r1, zero }; \
+ jrp lr; \
+ STD_ENDPROC(__get_user_##bytes); \
+ .pushsection __ex_table,"a"; \
+ .quad 1b, get_user_fault; \
+ .popsection
+
+__get_user_N(1, ld1u)
+__get_user_N(2, ld2u)
+__get_user_N(4, ld4u)
+__get_user_N(8, ld)
+
+/*
+ * __put_user_N functions take a value in r0 and a pointer in r1,
+ * and return 0 in r0 on success or -EFAULT on failure.
+ */
+#define __put_user_N(bytes, STORE) \
+ STD_ENTRY(__put_user_##bytes); \
+1: { STORE r1, r0; move r0, zero }; \
+ jrp lr; \
+ STD_ENDPROC(__put_user_##bytes); \
+ .pushsection __ex_table,"a"; \
+ .quad 1b, put_user_fault; \
+ .popsection
+
+__put_user_N(1, st1)
+__put_user_N(2, st2)
+__put_user_N(4, st4)
+__put_user_N(8, st)
+
+/*
+ * strnlen_user_asm takes the pointer in r0, and the length bound in r1.
+ * It returns the length, including the terminating NUL, or zero on exception.
+ * If length is greater than the bound, returns one plus the bound.
+ */
+STD_ENTRY(strnlen_user_asm)
+ { beqz r1, 2f; addi r3, r0, -1 } /* bias down to include NUL */
+1: { ld1u r4, r0; addi r1, r1, -1 }
+ beqz r4, 2f
+ { bnezt r1, 1b; addi r0, r0, 1 }
+2: { sub r0, r0, r3; jrp lr }
+ STD_ENDPROC(strnlen_user_asm)
+ .pushsection .fixup,"ax"
+strnlen_user_fault:
+ { move r0, zero; jrp lr }
+ ENDPROC(strnlen_user_fault)
+ .section __ex_table,"a"
+ .quad 1b, strnlen_user_fault
+ .popsection
+
+/*
+ * strncpy_from_user_asm takes the kernel target pointer in r0,
+ * the userspace source pointer in r1, and the length bound (including
+ * the trailing NUL) in r2. On success, it returns the string length
+ * (not including the trailing NUL), or -EFAULT on failure.
+ */
+STD_ENTRY(strncpy_from_user_asm)
+ { beqz r2, 2f; move r3, r0 }
+1: { ld1u r4, r1; addi r1, r1, 1; addi r2, r2, -1 }
+ { st1 r0, r4; addi r0, r0, 1 }
+ beqz r2, 2f
+ bnezt r4, 1b
+ addi r0, r0, -1 /* don't count the trailing NUL */
+2: { sub r0, r0, r3; jrp lr }
+ STD_ENDPROC(strncpy_from_user_asm)
+ .pushsection .fixup,"ax"
+strncpy_from_user_fault:
+ { movei r0, -EFAULT; jrp lr }
+ ENDPROC(strncpy_from_user_fault)
+ .section __ex_table,"a"
+ .quad 1b, strncpy_from_user_fault
+ .popsection
+
+/*
+ * clear_user_asm takes the user target address in r0 and the
+ * number of bytes to zero in r1.
+ * It returns the number of uncopiable bytes (hopefully zero) in r0.
+ * Note that we don't use a separate .fixup section here since we fall
+ * through into the "fixup" code as the last straight-line bundle anyway.
+ */
+STD_ENTRY(clear_user_asm)
+ { beqz r1, 2f; or r2, r0, r1 }
+ andi r2, r2, 7
+ beqzt r2, .Lclear_aligned_user_asm
+1: { st1 r0, zero; addi r0, r0, 1; addi r1, r1, -1 }
+ bnezt r1, 1b
+2: { move r0, r1; jrp lr }
+ .pushsection __ex_table,"a"
+ .quad 1b, 2b
+ .popsection
+
+.Lclear_aligned_user_asm:
+1: { st r0, zero; addi r0, r0, 8; addi r1, r1, -8 }
+ bnezt r1, 1b
+2: { move r0, r1; jrp lr }
+ STD_ENDPROC(clear_user_asm)
+ .pushsection __ex_table,"a"
+ .quad 1b, 2b
+ .popsection
+
+/*
+ * flush_user_asm takes the user target address in r0 and the
+ * number of bytes to flush in r1.
+ * It returns the number of unflushable bytes (hopefully zero) in r0.
+ */
+STD_ENTRY(flush_user_asm)
+ beqz r1, 2f
+ { movei r2, L2_CACHE_BYTES; add r1, r0, r1 }
+ { sub r2, zero, r2; addi r1, r1, L2_CACHE_BYTES-1 }
+ { and r0, r0, r2; and r1, r1, r2 }
+ { sub r1, r1, r0 }
+1: { flush r0; addi r1, r1, -CHIP_FLUSH_STRIDE() }
+ { addi r0, r0, CHIP_FLUSH_STRIDE(); bnezt r1, 1b }
+2: { move r0, r1; jrp lr }
+ STD_ENDPROC(flush_user_asm)
+ .pushsection __ex_table,"a"
+ .quad 1b, 2b
+ .popsection
+
+/*
+ * inv_user_asm takes the user target address in r0 and the
+ * number of bytes to invalidate in r1.
+ * It returns the number of not inv'able bytes (hopefully zero) in r0.
+ */
+STD_ENTRY(inv_user_asm)
+ beqz r1, 2f
+ { movei r2, L2_CACHE_BYTES; add r1, r0, r1 }
+ { sub r2, zero, r2; addi r1, r1, L2_CACHE_BYTES-1 }
+ { and r0, r0, r2; and r1, r1, r2 }
+ { sub r1, r1, r0 }
+1: { inv r0; addi r1, r1, -CHIP_INV_STRIDE() }
+ { addi r0, r0, CHIP_INV_STRIDE(); bnezt r1, 1b }
+2: { move r0, r1; jrp lr }
+ STD_ENDPROC(inv_user_asm)
+ .pushsection __ex_table,"a"
+ .quad 1b, 2b
+ .popsection
+
+/*
+ * finv_user_asm takes the user target address in r0 and the
+ * number of bytes to flush-invalidate in r1.
+ * It returns the number of not finv'able bytes (hopefully zero) in r0.
+ */
+STD_ENTRY(finv_user_asm)
+ beqz r1, 2f
+ { movei r2, L2_CACHE_BYTES; add r1, r0, r1 }
+ { sub r2, zero, r2; addi r1, r1, L2_CACHE_BYTES-1 }
+ { and r0, r0, r2; and r1, r1, r2 }
+ { sub r1, r1, r0 }
+1: { finv r0; addi r1, r1, -CHIP_FINV_STRIDE() }
+ { addi r0, r0, CHIP_FINV_STRIDE(); bnezt r1, 1b }
+2: { move r0, r1; jrp lr }
+ STD_ENDPROC(finv_user_asm)
+ .pushsection __ex_table,"a"
+ .quad 1b, 2b
+ .popsection
diff --git a/arch/tile/mm/fault.c b/arch/tile/mm/fault.c
index 51f8663..25b7b90 100644
--- a/arch/tile/mm/fault.c
+++ b/arch/tile/mm/fault.c
@@ -43,8 +43,11 @@
#include <arch/interrupts.h>
-static noinline void force_sig_info_fault(int si_signo, int si_code,
- unsigned long address, int fault_num, struct task_struct *tsk)
+static noinline void force_sig_info_fault(const char *type, int si_signo,
+ int si_code, unsigned long address,
+ int fault_num,
+ struct task_struct *tsk,
+ struct pt_regs *regs)
{
siginfo_t info;
@@ -59,6 +62,7 @@
info.si_code = si_code;
info.si_addr = (void __user *)address;
info.si_trapno = fault_num;
+ trace_unhandled_signal(type, regs, address, si_signo);
force_sig_info(si_signo, &info, tsk);
}
@@ -71,11 +75,12 @@
struct pt_regs *, regs)
{
if (address >= PAGE_OFFSET)
- force_sig_info_fault(SIGSEGV, SEGV_MAPERR, address,
- INT_DTLB_MISS, current);
+ force_sig_info_fault("atomic segfault", SIGSEGV, SEGV_MAPERR,
+ address, INT_DTLB_MISS, current, regs);
else
- force_sig_info_fault(SIGBUS, BUS_ADRALN, address,
- INT_UNALIGN_DATA, current);
+ force_sig_info_fault("atomic alignment fault", SIGBUS,
+ BUS_ADRALN, address,
+ INT_UNALIGN_DATA, current, regs);
/*
* Adjust pc to point at the actual instruction, which is unusual
@@ -471,8 +476,8 @@
*/
local_irq_enable();
- force_sig_info_fault(SIGSEGV, si_code, address,
- fault_num, tsk);
+ force_sig_info_fault("segfault", SIGSEGV, si_code, address,
+ fault_num, tsk, regs);
return 0;
}
@@ -547,7 +552,8 @@
if (is_kernel_mode)
goto no_context;
- force_sig_info_fault(SIGBUS, BUS_ADRERR, address, fault_num, tsk);
+ force_sig_info_fault("bus error", SIGBUS, BUS_ADRERR, address,
+ fault_num, tsk, regs);
return 0;
}
@@ -732,6 +738,7 @@
panic("Bad fault number %d in do_page_fault", fault_num);
}
+#if CHIP_HAS_TILE_DMA() || CHIP_HAS_SN_PROC()
if (EX1_PL(regs->ex1) != USER_PL) {
struct async_tlb *async;
switch (fault_num) {
@@ -775,6 +782,7 @@
return;
}
}
+#endif
handle_page_fault(regs, fault_num, is_page_fault, address, write);
}
@@ -801,8 +809,6 @@
async->address, async->is_write);
}
}
-#endif /* CHIP_HAS_TILE_DMA() || CHIP_HAS_SN_PROC() */
-
/*
* This routine effectively re-issues asynchronous page faults
@@ -824,6 +830,8 @@
handle_async_page_fault(regs, ¤t->thread.sn_async_tlb);
#endif
}
+#endif /* CHIP_HAS_TILE_DMA() || CHIP_HAS_SN_PROC() */
+
void vmalloc_sync_all(void)
{
diff --git a/arch/tile/mm/init.c b/arch/tile/mm/init.c
index d6e87fd..4e10c40 100644
--- a/arch/tile/mm/init.c
+++ b/arch/tile/mm/init.c
@@ -60,8 +60,6 @@
EXPORT_SYMBOL(VMALLOC_RESERVE);
#endif
-DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
-
/* Create an L2 page table */
static pte_t * __init alloc_pte(void)
{
diff --git a/arch/tile/mm/migrate_64.S b/arch/tile/mm/migrate_64.S
new file mode 100644
index 0000000..e76fea6
--- /dev/null
+++ b/arch/tile/mm/migrate_64.S
@@ -0,0 +1,187 @@
+/*
+ * Copyright 2011 Tilera Corporation. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ * NON INFRINGEMENT. See the GNU General Public License for
+ * more details.
+ *
+ * This routine is a helper for migrating the home of a set of pages to
+ * a new cpu. See the documentation in homecache.c for more information.
+ */
+
+#include <linux/linkage.h>
+#include <linux/threads.h>
+#include <asm/page.h>
+#include <asm/thread_info.h>
+#include <asm/types.h>
+#include <asm/asm-offsets.h>
+#include <hv/hypervisor.h>
+
+ .text
+
+/*
+ * First, some definitions that apply to all the code in the file.
+ */
+
+/* Locals (caller-save) */
+#define r_tmp r10
+#define r_save_sp r11
+
+/* What we save where in the stack frame; must include all callee-saves. */
+#define FRAME_SP 8
+#define FRAME_R30 16
+#define FRAME_R31 24
+#define FRAME_R32 32
+#define FRAME_R33 40
+#define FRAME_SIZE 48
+
+
+
+
+/*
+ * On entry:
+ *
+ * r0 the new context PA to install (moved to r_context)
+ * r1 PTE to use for context access (moved to r_access)
+ * r2 ASID to use for new context (moved to r_asid)
+ * r3 pointer to cpumask with just this cpu set in it (r_my_cpumask)
+ */
+
+/* Arguments (caller-save) */
+#define r_context_in r0
+#define r_access_in r1
+#define r_asid_in r2
+#define r_my_cpumask r3
+
+/* Locals (callee-save); must not be more than FRAME_xxx above. */
+#define r_save_ics r30
+#define r_context r31
+#define r_access r32
+#define r_asid r33
+
+/*
+ * Caller-save locals and frame constants are the same as
+ * for homecache_migrate_stack_and_flush.
+ */
+
+STD_ENTRY(flush_and_install_context)
+ /*
+ * Create a stack frame; we can't touch it once we flush the
+ * cache until we install the new page table and flush the TLB.
+ */
+ {
+ move r_save_sp, sp
+ st sp, lr
+ addi sp, sp, -FRAME_SIZE
+ }
+ addi r_tmp, sp, FRAME_SP
+ {
+ st r_tmp, r_save_sp
+ addi r_tmp, sp, FRAME_R30
+ }
+ {
+ st r_tmp, r30
+ addi r_tmp, sp, FRAME_R31
+ }
+ {
+ st r_tmp, r31
+ addi r_tmp, sp, FRAME_R32
+ }
+ {
+ st r_tmp, r32
+ addi r_tmp, sp, FRAME_R33
+ }
+ st r_tmp, r33
+
+ /* Move some arguments to callee-save registers. */
+ {
+ move r_context, r_context_in
+ move r_access, r_access_in
+ }
+ move r_asid, r_asid_in
+
+ /* Disable interrupts, since we can't use our stack. */
+ {
+ mfspr r_save_ics, INTERRUPT_CRITICAL_SECTION
+ movei r_tmp, 1
+ }
+ mtspr INTERRUPT_CRITICAL_SECTION, r_tmp
+
+ /* First, flush our L2 cache. */
+ {
+ move r0, zero /* cache_pa */
+ moveli r1, hw2_last(HV_FLUSH_EVICT_L2) /* cache_control */
+ }
+ {
+ shl16insli r1, r1, hw1(HV_FLUSH_EVICT_L2)
+ move r2, r_my_cpumask /* cache_cpumask */
+ }
+ {
+ shl16insli r1, r1, hw0(HV_FLUSH_EVICT_L2)
+ move r3, zero /* tlb_va */
+ }
+ {
+ move r4, zero /* tlb_length */
+ move r5, zero /* tlb_pgsize */
+ }
+ {
+ move r6, zero /* tlb_cpumask */
+ move r7, zero /* asids */
+ }
+ {
+ move r8, zero /* asidcount */
+ jal hv_flush_remote
+ }
+ bnez r0, 1f
+
+ /* Now install the new page table. */
+ {
+ move r0, r_context
+ move r1, r_access
+ }
+ {
+ move r2, r_asid
+ movei r3, HV_CTX_DIRECTIO
+ }
+ jal hv_install_context
+ bnez r0, 1f
+
+ /* Finally, flush the TLB. */
+ {
+ movei r0, 0 /* preserve_global */
+ jal hv_flush_all
+ }
+
+1: /* Reset interrupts back how they were before. */
+ mtspr INTERRUPT_CRITICAL_SECTION, r_save_ics
+
+ /* Restore the callee-saved registers and return. */
+ addli lr, sp, FRAME_SIZE
+ {
+ ld lr, lr
+ addli r_tmp, sp, FRAME_R30
+ }
+ {
+ ld r30, r_tmp
+ addli r_tmp, sp, FRAME_R31
+ }
+ {
+ ld r31, r_tmp
+ addli r_tmp, sp, FRAME_R32
+ }
+ {
+ ld r32, r_tmp
+ addli r_tmp, sp, FRAME_R33
+ }
+ {
+ ld r33, r_tmp
+ addi sp, sp, FRAME_SIZE
+ }
+ jrp lr
+ STD_ENDPROC(flush_and_install_context)
diff --git a/arch/um/Kconfig.debug b/arch/um/Kconfig.debug
index 8fce5e5..68205fd 100644
--- a/arch/um/Kconfig.debug
+++ b/arch/um/Kconfig.debug
@@ -28,13 +28,13 @@
If you're involved in UML kernel development and want to use gcov,
say Y. If you're unsure, say N.
-config DEBUG_STACK_USAGE
- bool "Stack utilization instrumentation"
- default N
- help
- Track the maximum kernel stack usage - this will look at each
- kernel stack at process exit and log it if it's the deepest
- stack seen so far.
+config EARLY_PRINTK
+ bool "Early printk"
+ default y
+ ---help---
+ Write kernel log output directly to stdout.
- This option will slow down process creation and destruction somewhat.
+ This is useful for kernel debugging when your machine crashes very
+ early before the console code is initialized.
+
endmenu
diff --git a/arch/um/Kconfig.x86 b/arch/um/Kconfig.x86
index a9da516..795ea8e 100644
--- a/arch/um/Kconfig.x86
+++ b/arch/um/Kconfig.x86
@@ -29,10 +29,10 @@
def_bool 64BIT
config RWSEM_XCHGADD_ALGORITHM
- def_bool X86_XADD
+ def_bool X86_XADD && 64BIT
config RWSEM_GENERIC_SPINLOCK
- def_bool !X86_XADD
+ def_bool !RWSEM_XCHGADD_ALGORITHM
config 3_LEVEL_PGTABLES
bool "Three-level pagetables (EXPERIMENTAL)" if !64BIT
diff --git a/arch/um/drivers/Makefile b/arch/um/drivers/Makefile
index 1d9b6ae..e7582e1 100644
--- a/arch/um/drivers/Makefile
+++ b/arch/um/drivers/Makefile
@@ -9,7 +9,7 @@
slip-objs := slip_kern.o slip_user.o
slirp-objs := slirp_kern.o slirp_user.o
daemon-objs := daemon_kern.o daemon_user.o
-mcast-objs := mcast_kern.o mcast_user.o
+umcast-objs := umcast_kern.o umcast_user.o
net-objs := net_kern.o net_user.o
mconsole-objs := mconsole_kern.o mconsole_user.o
hostaudio-objs := hostaudio_kern.o
@@ -44,7 +44,7 @@
obj-$(CONFIG_UML_NET_SLIRP) += slirp.o slip_common.o
obj-$(CONFIG_UML_NET_DAEMON) += daemon.o
obj-$(CONFIG_UML_NET_VDE) += vde.o
-obj-$(CONFIG_UML_NET_MCAST) += mcast.o
+obj-$(CONFIG_UML_NET_MCAST) += umcast.o
obj-$(CONFIG_UML_NET_PCAP) += pcap.o
obj-$(CONFIG_UML_NET) += net.o
obj-$(CONFIG_MCONSOLE) += mconsole.o
diff --git a/arch/um/drivers/mcast.h b/arch/um/drivers/mcast.h
deleted file mode 100644
index 6fa282e..0000000
--- a/arch/um/drivers/mcast.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Copyright (C) 2001 - 2007 Jeff Dike (jdike@{addtoit,linux.intel}.com)
- * Licensed under the GPL
- */
-
-#ifndef __DRIVERS_MCAST_H
-#define __DRIVERS_MCAST_H
-
-#include "net_user.h"
-
-struct mcast_data {
- char *addr;
- unsigned short port;
- void *mcast_addr;
- int ttl;
- void *dev;
-};
-
-extern const struct net_user_info mcast_user_info;
-
-extern int mcast_user_write(int fd, void *buf, int len,
- struct mcast_data *pri);
-
-#endif
diff --git a/arch/um/drivers/mcast_kern.c b/arch/um/drivers/mcast_kern.c
deleted file mode 100644
index ffc6416..0000000
--- a/arch/um/drivers/mcast_kern.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * user-mode-linux networking multicast transport
- * Copyright (C) 2001 by Harald Welte <laforge@gnumonks.org>
- * Copyright (C) 2001 - 2007 Jeff Dike (jdike@{addtoit,linux.intel}.com)
- *
- * based on the existing uml-networking code, which is
- * Copyright (C) 2001 Lennert Buytenhek (buytenh@gnu.org) and
- * James Leu (jleu@mindspring.net).
- * Copyright (C) 2001 by various other people who didn't put their name here.
- *
- * Licensed under the GPL.
- */
-
-#include "linux/init.h"
-#include <linux/netdevice.h>
-#include "mcast.h"
-#include "net_kern.h"
-
-struct mcast_init {
- char *addr;
- int port;
- int ttl;
-};
-
-static void mcast_init(struct net_device *dev, void *data)
-{
- struct uml_net_private *pri;
- struct mcast_data *dpri;
- struct mcast_init *init = data;
-
- pri = netdev_priv(dev);
- dpri = (struct mcast_data *) pri->user;
- dpri->addr = init->addr;
- dpri->port = init->port;
- dpri->ttl = init->ttl;
- dpri->dev = dev;
-
- printk("mcast backend multicast address: %s:%u, TTL:%u\n",
- dpri->addr, dpri->port, dpri->ttl);
-}
-
-static int mcast_read(int fd, struct sk_buff *skb, struct uml_net_private *lp)
-{
- return net_recvfrom(fd, skb_mac_header(skb),
- skb->dev->mtu + ETH_HEADER_OTHER);
-}
-
-static int mcast_write(int fd, struct sk_buff *skb, struct uml_net_private *lp)
-{
- return mcast_user_write(fd, skb->data, skb->len,
- (struct mcast_data *) &lp->user);
-}
-
-static const struct net_kern_info mcast_kern_info = {
- .init = mcast_init,
- .protocol = eth_protocol,
- .read = mcast_read,
- .write = mcast_write,
-};
-
-static int mcast_setup(char *str, char **mac_out, void *data)
-{
- struct mcast_init *init = data;
- char *port_str = NULL, *ttl_str = NULL, *remain;
- char *last;
-
- *init = ((struct mcast_init)
- { .addr = "239.192.168.1",
- .port = 1102,
- .ttl = 1 });
-
- remain = split_if_spec(str, mac_out, &init->addr, &port_str, &ttl_str,
- NULL);
- if (remain != NULL) {
- printk(KERN_ERR "mcast_setup - Extra garbage on "
- "specification : '%s'\n", remain);
- return 0;
- }
-
- if (port_str != NULL) {
- init->port = simple_strtoul(port_str, &last, 10);
- if ((*last != '\0') || (last == port_str)) {
- printk(KERN_ERR "mcast_setup - Bad port : '%s'\n",
- port_str);
- return 0;
- }
- }
-
- if (ttl_str != NULL) {
- init->ttl = simple_strtoul(ttl_str, &last, 10);
- if ((*last != '\0') || (last == ttl_str)) {
- printk(KERN_ERR "mcast_setup - Bad ttl : '%s'\n",
- ttl_str);
- return 0;
- }
- }
-
- printk(KERN_INFO "Configured mcast device: %s:%u-%u\n", init->addr,
- init->port, init->ttl);
-
- return 1;
-}
-
-static struct transport mcast_transport = {
- .list = LIST_HEAD_INIT(mcast_transport.list),
- .name = "mcast",
- .setup = mcast_setup,
- .user = &mcast_user_info,
- .kern = &mcast_kern_info,
- .private_size = sizeof(struct mcast_data),
- .setup_size = sizeof(struct mcast_init),
-};
-
-static int register_mcast(void)
-{
- register_transport(&mcast_transport);
- return 0;
-}
-
-late_initcall(register_mcast);
diff --git a/arch/um/drivers/mcast_user.c b/arch/um/drivers/mcast_user.c
deleted file mode 100644
index ee19e91..0000000
--- a/arch/um/drivers/mcast_user.c
+++ /dev/null
@@ -1,165 +0,0 @@
-/*
- * user-mode-linux networking multicast transport
- * Copyright (C) 2001 - 2007 Jeff Dike (jdike@{addtoit,linux.intel}.com)
- * Copyright (C) 2001 by Harald Welte <laforge@gnumonks.org>
- *
- * based on the existing uml-networking code, which is
- * Copyright (C) 2001 Lennert Buytenhek (buytenh@gnu.org) and
- * James Leu (jleu@mindspring.net).
- * Copyright (C) 2001 by various other people who didn't put their name here.
- *
- * Licensed under the GPL.
- *
- */
-
-#include <unistd.h>
-#include <errno.h>
-#include <netinet/in.h>
-#include "kern_constants.h"
-#include "mcast.h"
-#include "net_user.h"
-#include "um_malloc.h"
-#include "user.h"
-
-static struct sockaddr_in *new_addr(char *addr, unsigned short port)
-{
- struct sockaddr_in *sin;
-
- sin = uml_kmalloc(sizeof(struct sockaddr_in), UM_GFP_KERNEL);
- if (sin == NULL) {
- printk(UM_KERN_ERR "new_addr: allocation of sockaddr_in "
- "failed\n");
- return NULL;
- }
- sin->sin_family = AF_INET;
- sin->sin_addr.s_addr = in_aton(addr);
- sin->sin_port = htons(port);
- return sin;
-}
-
-static int mcast_user_init(void *data, void *dev)
-{
- struct mcast_data *pri = data;
-
- pri->mcast_addr = new_addr(pri->addr, pri->port);
- pri->dev = dev;
- return 0;
-}
-
-static void mcast_remove(void *data)
-{
- struct mcast_data *pri = data;
-
- kfree(pri->mcast_addr);
- pri->mcast_addr = NULL;
-}
-
-static int mcast_open(void *data)
-{
- struct mcast_data *pri = data;
- struct sockaddr_in *sin = pri->mcast_addr;
- struct ip_mreq mreq;
- int fd, yes = 1, err = -EINVAL;
-
-
- if ((sin->sin_addr.s_addr == 0) || (sin->sin_port == 0))
- goto out;
-
- fd = socket(AF_INET, SOCK_DGRAM, 0);
-
- if (fd < 0) {
- err = -errno;
- printk(UM_KERN_ERR "mcast_open : data socket failed, "
- "errno = %d\n", errno);
- goto out;
- }
-
- if (setsockopt(fd, SOL_SOCKET, SO_REUSEADDR, &yes, sizeof(yes)) < 0) {
- err = -errno;
- printk(UM_KERN_ERR "mcast_open: SO_REUSEADDR failed, "
- "errno = %d\n", errno);
- goto out_close;
- }
-
- /* set ttl according to config */
- if (setsockopt(fd, SOL_IP, IP_MULTICAST_TTL, &pri->ttl,
- sizeof(pri->ttl)) < 0) {
- err = -errno;
- printk(UM_KERN_ERR "mcast_open: IP_MULTICAST_TTL failed, "
- "error = %d\n", errno);
- goto out_close;
- }
-
- /* set LOOP, so data does get fed back to local sockets */
- if (setsockopt(fd, SOL_IP, IP_MULTICAST_LOOP, &yes, sizeof(yes)) < 0) {
- err = -errno;
- printk(UM_KERN_ERR "mcast_open: IP_MULTICAST_LOOP failed, "
- "error = %d\n", errno);
- goto out_close;
- }
-
- /* bind socket to mcast address */
- if (bind(fd, (struct sockaddr *) sin, sizeof(*sin)) < 0) {
- err = -errno;
- printk(UM_KERN_ERR "mcast_open : data bind failed, "
- "errno = %d\n", errno);
- goto out_close;
- }
-
- /* subscribe to the multicast group */
- mreq.imr_multiaddr.s_addr = sin->sin_addr.s_addr;
- mreq.imr_interface.s_addr = 0;
- if (setsockopt(fd, SOL_IP, IP_ADD_MEMBERSHIP,
- &mreq, sizeof(mreq)) < 0) {
- err = -errno;
- printk(UM_KERN_ERR "mcast_open: IP_ADD_MEMBERSHIP failed, "
- "error = %d\n", errno);
- printk(UM_KERN_ERR "There appears not to be a multicast-"
- "capable network interface on the host.\n");
- printk(UM_KERN_ERR "eth0 should be configured in order to use "
- "the multicast transport.\n");
- goto out_close;
- }
-
- return fd;
-
- out_close:
- close(fd);
- out:
- return err;
-}
-
-static void mcast_close(int fd, void *data)
-{
- struct ip_mreq mreq;
- struct mcast_data *pri = data;
- struct sockaddr_in *sin = pri->mcast_addr;
-
- mreq.imr_multiaddr.s_addr = sin->sin_addr.s_addr;
- mreq.imr_interface.s_addr = 0;
- if (setsockopt(fd, SOL_IP, IP_DROP_MEMBERSHIP,
- &mreq, sizeof(mreq)) < 0) {
- printk(UM_KERN_ERR "mcast_open: IP_DROP_MEMBERSHIP failed, "
- "error = %d\n", errno);
- }
-
- close(fd);
-}
-
-int mcast_user_write(int fd, void *buf, int len, struct mcast_data *pri)
-{
- struct sockaddr_in *data_addr = pri->mcast_addr;
-
- return net_sendto(fd, buf, len, data_addr, sizeof(*data_addr));
-}
-
-const struct net_user_info mcast_user_info = {
- .init = mcast_user_init,
- .open = mcast_open,
- .close = mcast_close,
- .remove = mcast_remove,
- .add_address = NULL,
- .delete_address = NULL,
- .mtu = ETH_MAX_PACKET,
- .max_packet = ETH_MAX_PACKET + ETH_HEADER_OTHER,
-};
diff --git a/arch/um/drivers/umcast.h b/arch/um/drivers/umcast.h
new file mode 100644
index 0000000..6f8c0fe
--- /dev/null
+++ b/arch/um/drivers/umcast.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2001 - 2007 Jeff Dike (jdike@{addtoit,linux.intel}.com)
+ * Licensed under the GPL
+ */
+
+#ifndef __DRIVERS_UMCAST_H
+#define __DRIVERS_UMCAST_H
+
+#include "net_user.h"
+
+struct umcast_data {
+ char *addr;
+ unsigned short lport;
+ unsigned short rport;
+ void *listen_addr;
+ void *remote_addr;
+ int ttl;
+ int unicast;
+ void *dev;
+};
+
+extern const struct net_user_info umcast_user_info;
+
+extern int umcast_user_write(int fd, void *buf, int len,
+ struct umcast_data *pri);
+
+#endif
diff --git a/arch/um/drivers/umcast_kern.c b/arch/um/drivers/umcast_kern.c
new file mode 100644
index 0000000..42dab11
--- /dev/null
+++ b/arch/um/drivers/umcast_kern.c
@@ -0,0 +1,188 @@
+/*
+ * user-mode-linux networking multicast transport
+ * Copyright (C) 2001 by Harald Welte <laforge@gnumonks.org>
+ * Copyright (C) 2001 - 2007 Jeff Dike (jdike@{addtoit,linux.intel}.com)
+ *
+ * based on the existing uml-networking code, which is
+ * Copyright (C) 2001 Lennert Buytenhek (buytenh@gnu.org) and
+ * James Leu (jleu@mindspring.net).
+ * Copyright (C) 2001 by various other people who didn't put their name here.
+ *
+ * Licensed under the GPL.
+ */
+
+#include "linux/init.h"
+#include <linux/netdevice.h>
+#include "umcast.h"
+#include "net_kern.h"
+
+struct umcast_init {
+ char *addr;
+ int lport;
+ int rport;
+ int ttl;
+ bool unicast;
+};
+
+static void umcast_init(struct net_device *dev, void *data)
+{
+ struct uml_net_private *pri;
+ struct umcast_data *dpri;
+ struct umcast_init *init = data;
+
+ pri = netdev_priv(dev);
+ dpri = (struct umcast_data *) pri->user;
+ dpri->addr = init->addr;
+ dpri->lport = init->lport;
+ dpri->rport = init->rport;
+ dpri->unicast = init->unicast;
+ dpri->ttl = init->ttl;
+ dpri->dev = dev;
+
+ if (dpri->unicast) {
+ printk(KERN_INFO "ucast backend address: %s:%u listen port: "
+ "%u\n", dpri->addr, dpri->rport, dpri->lport);
+ } else {
+ printk(KERN_INFO "mcast backend multicast address: %s:%u, "
+ "TTL:%u\n", dpri->addr, dpri->lport, dpri->ttl);
+ }
+}
+
+static int umcast_read(int fd, struct sk_buff *skb, struct uml_net_private *lp)
+{
+ return net_recvfrom(fd, skb_mac_header(skb),
+ skb->dev->mtu + ETH_HEADER_OTHER);
+}
+
+static int umcast_write(int fd, struct sk_buff *skb, struct uml_net_private *lp)
+{
+ return umcast_user_write(fd, skb->data, skb->len,
+ (struct umcast_data *) &lp->user);
+}
+
+static const struct net_kern_info umcast_kern_info = {
+ .init = umcast_init,
+ .protocol = eth_protocol,
+ .read = umcast_read,
+ .write = umcast_write,
+};
+
+static int mcast_setup(char *str, char **mac_out, void *data)
+{
+ struct umcast_init *init = data;
+ char *port_str = NULL, *ttl_str = NULL, *remain;
+ char *last;
+
+ *init = ((struct umcast_init)
+ { .addr = "239.192.168.1",
+ .lport = 1102,
+ .ttl = 1 });
+
+ remain = split_if_spec(str, mac_out, &init->addr, &port_str, &ttl_str,
+ NULL);
+ if (remain != NULL) {
+ printk(KERN_ERR "mcast_setup - Extra garbage on "
+ "specification : '%s'\n", remain);
+ return 0;
+ }
+
+ if (port_str != NULL) {
+ init->lport = simple_strtoul(port_str, &last, 10);
+ if ((*last != '\0') || (last == port_str)) {
+ printk(KERN_ERR "mcast_setup - Bad port : '%s'\n",
+ port_str);
+ return 0;
+ }
+ }
+
+ if (ttl_str != NULL) {
+ init->ttl = simple_strtoul(ttl_str, &last, 10);
+ if ((*last != '\0') || (last == ttl_str)) {
+ printk(KERN_ERR "mcast_setup - Bad ttl : '%s'\n",
+ ttl_str);
+ return 0;
+ }
+ }
+
+ init->unicast = false;
+ init->rport = init->lport;
+
+ printk(KERN_INFO "Configured mcast device: %s:%u-%u\n", init->addr,
+ init->lport, init->ttl);
+
+ return 1;
+}
+
+static int ucast_setup(char *str, char **mac_out, void *data)
+{
+ struct umcast_init *init = data;
+ char *lport_str = NULL, *rport_str = NULL, *remain;
+ char *last;
+
+ *init = ((struct umcast_init)
+ { .addr = "",
+ .lport = 1102,
+ .rport = 1102 });
+
+ remain = split_if_spec(str, mac_out, &init->addr,
+ &lport_str, &rport_str, NULL);
+ if (remain != NULL) {
+ printk(KERN_ERR "ucast_setup - Extra garbage on "
+ "specification : '%s'\n", remain);
+ return 0;
+ }
+
+ if (lport_str != NULL) {
+ init->lport = simple_strtoul(lport_str, &last, 10);
+ if ((*last != '\0') || (last == lport_str)) {
+ printk(KERN_ERR "ucast_setup - Bad listen port : "
+ "'%s'\n", lport_str);
+ return 0;
+ }
+ }
+
+ if (rport_str != NULL) {
+ init->rport = simple_strtoul(rport_str, &last, 10);
+ if ((*last != '\0') || (last == rport_str)) {
+ printk(KERN_ERR "ucast_setup - Bad remote port : "
+ "'%s'\n", rport_str);
+ return 0;
+ }
+ }
+
+ init->unicast = true;
+
+ printk(KERN_INFO "Configured ucast device: :%u -> %s:%u\n",
+ init->lport, init->addr, init->rport);
+
+ return 1;
+}
+
+static struct transport mcast_transport = {
+ .list = LIST_HEAD_INIT(mcast_transport.list),
+ .name = "mcast",
+ .setup = mcast_setup,
+ .user = &umcast_user_info,
+ .kern = &umcast_kern_info,
+ .private_size = sizeof(struct umcast_data),
+ .setup_size = sizeof(struct umcast_init),
+};
+
+static struct transport ucast_transport = {
+ .list = LIST_HEAD_INIT(ucast_transport.list),
+ .name = "ucast",
+ .setup = ucast_setup,
+ .user = &umcast_user_info,
+ .kern = &umcast_kern_info,
+ .private_size = sizeof(struct umcast_data),
+ .setup_size = sizeof(struct umcast_init),
+};
+
+static int register_umcast(void)
+{
+ register_transport(&mcast_transport);
+ register_transport(&ucast_transport);
+ return 0;
+}
+
+late_initcall(register_umcast);
diff --git a/arch/um/drivers/umcast_user.c b/arch/um/drivers/umcast_user.c
new file mode 100644
index 0000000..59c56fd
--- /dev/null
+++ b/arch/um/drivers/umcast_user.c
@@ -0,0 +1,186 @@
+/*
+ * user-mode-linux networking multicast transport
+ * Copyright (C) 2001 - 2007 Jeff Dike (jdike@{addtoit,linux.intel}.com)
+ * Copyright (C) 2001 by Harald Welte <laforge@gnumonks.org>
+ *
+ * based on the existing uml-networking code, which is
+ * Copyright (C) 2001 Lennert Buytenhek (buytenh@gnu.org) and
+ * James Leu (jleu@mindspring.net).
+ * Copyright (C) 2001 by various other people who didn't put their name here.
+ *
+ * Licensed under the GPL.
+ *
+ */
+
+#include <unistd.h>
+#include <errno.h>
+#include <netinet/in.h>
+#include "kern_constants.h"
+#include "umcast.h"
+#include "net_user.h"
+#include "um_malloc.h"
+#include "user.h"
+
+static struct sockaddr_in *new_addr(char *addr, unsigned short port)
+{
+ struct sockaddr_in *sin;
+
+ sin = uml_kmalloc(sizeof(struct sockaddr_in), UM_GFP_KERNEL);
+ if (sin == NULL) {
+ printk(UM_KERN_ERR "new_addr: allocation of sockaddr_in "
+ "failed\n");
+ return NULL;
+ }
+ sin->sin_family = AF_INET;
+ if (addr)
+ sin->sin_addr.s_addr = in_aton(addr);
+ else
+ sin->sin_addr.s_addr = INADDR_ANY;
+ sin->sin_port = htons(port);
+ return sin;
+}
+
+static int umcast_user_init(void *data, void *dev)
+{
+ struct umcast_data *pri = data;
+
+ pri->remote_addr = new_addr(pri->addr, pri->rport);
+ if (pri->unicast)
+ pri->listen_addr = new_addr(NULL, pri->lport);
+ else
+ pri->listen_addr = pri->remote_addr;
+ pri->dev = dev;
+ return 0;
+}
+
+static void umcast_remove(void *data)
+{
+ struct umcast_data *pri = data;
+
+ kfree(pri->listen_addr);
+ if (pri->unicast)
+ kfree(pri->remote_addr);
+ pri->listen_addr = pri->remote_addr = NULL;
+}
+
+static int umcast_open(void *data)
+{
+ struct umcast_data *pri = data;
+ struct sockaddr_in *lsin = pri->listen_addr;
+ struct sockaddr_in *rsin = pri->remote_addr;
+ struct ip_mreq mreq;
+ int fd, yes = 1, err = -EINVAL;
+
+
+ if ((!pri->unicast && lsin->sin_addr.s_addr == 0) ||
+ (rsin->sin_addr.s_addr == 0) ||
+ (lsin->sin_port == 0) || (rsin->sin_port == 0))
+ goto out;
+
+ fd = socket(AF_INET, SOCK_DGRAM, 0);
+
+ if (fd < 0) {
+ err = -errno;
+ printk(UM_KERN_ERR "umcast_open : data socket failed, "
+ "errno = %d\n", errno);
+ goto out;
+ }
+
+ if (setsockopt(fd, SOL_SOCKET, SO_REUSEADDR, &yes, sizeof(yes)) < 0) {
+ err = -errno;
+ printk(UM_KERN_ERR "umcast_open: SO_REUSEADDR failed, "
+ "errno = %d\n", errno);
+ goto out_close;
+ }
+
+ if (!pri->unicast) {
+ /* set ttl according to config */
+ if (setsockopt(fd, SOL_IP, IP_MULTICAST_TTL, &pri->ttl,
+ sizeof(pri->ttl)) < 0) {
+ err = -errno;
+ printk(UM_KERN_ERR "umcast_open: IP_MULTICAST_TTL "
+ "failed, error = %d\n", errno);
+ goto out_close;
+ }
+
+ /* set LOOP, so data does get fed back to local sockets */
+ if (setsockopt(fd, SOL_IP, IP_MULTICAST_LOOP,
+ &yes, sizeof(yes)) < 0) {
+ err = -errno;
+ printk(UM_KERN_ERR "umcast_open: IP_MULTICAST_LOOP "
+ "failed, error = %d\n", errno);
+ goto out_close;
+ }
+ }
+
+ /* bind socket to the address */
+ if (bind(fd, (struct sockaddr *) lsin, sizeof(*lsin)) < 0) {
+ err = -errno;
+ printk(UM_KERN_ERR "umcast_open : data bind failed, "
+ "errno = %d\n", errno);
+ goto out_close;
+ }
+
+ if (!pri->unicast) {
+ /* subscribe to the multicast group */
+ mreq.imr_multiaddr.s_addr = lsin->sin_addr.s_addr;
+ mreq.imr_interface.s_addr = 0;
+ if (setsockopt(fd, SOL_IP, IP_ADD_MEMBERSHIP,
+ &mreq, sizeof(mreq)) < 0) {
+ err = -errno;
+ printk(UM_KERN_ERR "umcast_open: IP_ADD_MEMBERSHIP "
+ "failed, error = %d\n", errno);
+ printk(UM_KERN_ERR "There appears not to be a "
+ "multicast-capable network interface on the "
+ "host.\n");
+ printk(UM_KERN_ERR "eth0 should be configured in order "
+ "to use the multicast transport.\n");
+ goto out_close;
+ }
+ }
+
+ return fd;
+
+ out_close:
+ close(fd);
+ out:
+ return err;
+}
+
+static void umcast_close(int fd, void *data)
+{
+ struct umcast_data *pri = data;
+
+ if (!pri->unicast) {
+ struct ip_mreq mreq;
+ struct sockaddr_in *lsin = pri->listen_addr;
+
+ mreq.imr_multiaddr.s_addr = lsin->sin_addr.s_addr;
+ mreq.imr_interface.s_addr = 0;
+ if (setsockopt(fd, SOL_IP, IP_DROP_MEMBERSHIP,
+ &mreq, sizeof(mreq)) < 0) {
+ printk(UM_KERN_ERR "umcast_close: IP_DROP_MEMBERSHIP "
+ "failed, error = %d\n", errno);
+ }
+ }
+
+ close(fd);
+}
+
+int umcast_user_write(int fd, void *buf, int len, struct umcast_data *pri)
+{
+ struct sockaddr_in *data_addr = pri->remote_addr;
+
+ return net_sendto(fd, buf, len, data_addr, sizeof(*data_addr));
+}
+
+const struct net_user_info umcast_user_info = {
+ .init = umcast_user_init,
+ .open = umcast_open,
+ .close = umcast_close,
+ .remove = umcast_remove,
+ .add_address = NULL,
+ .delete_address = NULL,
+ .mtu = ETH_MAX_PACKET,
+ .max_packet = ETH_MAX_PACKET + ETH_HEADER_OTHER,
+};
diff --git a/arch/um/drivers/xterm.c b/arch/um/drivers/xterm.c
index da2caa5..8ac7146 100644
--- a/arch/um/drivers/xterm.c
+++ b/arch/um/drivers/xterm.c
@@ -90,7 +90,7 @@
int pid, fd, new, err;
char title[256], file[] = "/tmp/xterm-pipeXXXXXX";
char *argv[] = { terminal_emulator, title_switch, title, exec_switch,
- "/usr/lib/uml/port-helper", "-uml-socket",
+ OS_LIB_PATH "/uml/port-helper", "-uml-socket",
file, NULL };
if (access(argv[4], X_OK) < 0)
diff --git a/arch/um/include/asm/common.lds.S b/arch/um/include/asm/common.lds.S
index 34bede8..4938de5 100644
--- a/arch/um/include/asm/common.lds.S
+++ b/arch/um/include/asm/common.lds.S
@@ -42,7 +42,7 @@
INIT_SETUP(0)
}
- PERCPU(32, 32)
+ PERCPU_SECTION(32)
.initcall.init : {
INIT_CALLS
diff --git a/arch/um/include/asm/processor-generic.h b/arch/um/include/asm/processor-generic.h
index d1d1b0d..98d01bc 100644
--- a/arch/um/include/asm/processor-generic.h
+++ b/arch/um/include/asm/processor-generic.h
@@ -14,6 +14,8 @@
#include "registers.h"
#include "sysdep/archsetjmp.h"
+#include <linux/prefetch.h>
+
struct mm_struct;
struct thread_struct {
diff --git a/arch/um/include/asm/smp.h b/arch/um/include/asm/smp.h
index f27a963..4a4b09d 100644
--- a/arch/um/include/asm/smp.h
+++ b/arch/um/include/asm/smp.h
@@ -11,7 +11,6 @@
#define cpu_logical_map(n) (n)
#define cpu_number_map(n) (n)
-#define PROC_CHANGE_PENALTY 15 /* Pick a number, any number */
extern int hard_smp_processor_id(void);
#define NO_PROC_ID -1
diff --git a/arch/um/include/asm/tlb.h b/arch/um/include/asm/tlb.h
index 660caed..4febacd 100644
--- a/arch/um/include/asm/tlb.h
+++ b/arch/um/include/asm/tlb.h
@@ -22,9 +22,6 @@
unsigned int fullmm; /* non-zero means full mm flush */
};
-/* Users of the generic TLB shootdown code must declare this storage space. */
-DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
-
static inline void __tlb_remove_tlb_entry(struct mmu_gather *tlb, pte_t *ptep,
unsigned long address)
{
@@ -47,27 +44,20 @@
}
}
-/* tlb_gather_mmu
- * Return a pointer to an initialized struct mmu_gather.
- */
-static inline struct mmu_gather *
-tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
+static inline void
+tlb_gather_mmu(struct mmu_gather *tlb, struct mm_struct *mm, unsigned int full_mm_flush)
{
- struct mmu_gather *tlb = &get_cpu_var(mmu_gathers);
-
tlb->mm = mm;
tlb->fullmm = full_mm_flush;
init_tlb_gather(tlb);
-
- return tlb;
}
extern void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start,
unsigned long end);
static inline void
-tlb_flush_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end)
+tlb_flush_mmu(struct mmu_gather *tlb)
{
if (!tlb->need_flush)
return;
@@ -83,12 +73,10 @@
static inline void
tlb_finish_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end)
{
- tlb_flush_mmu(tlb, start, end);
+ tlb_flush_mmu(tlb);
/* keep the page table cache within bounds */
check_pgt_cache();
-
- put_cpu_var(mmu_gathers);
}
/* tlb_remove_page
@@ -96,11 +84,16 @@
* while handling the additional races in SMP caused by other CPUs
* caching valid mappings in their TLBs.
*/
-static inline void tlb_remove_page(struct mmu_gather *tlb, struct page *page)
+static inline int __tlb_remove_page(struct mmu_gather *tlb, struct page *page)
{
tlb->need_flush = 1;
free_page_and_swap_cache(page);
- return;
+ return 1; /* avoid calling tlb_flush_mmu */
+}
+
+static inline void tlb_remove_page(struct mmu_gather *tlb, struct page *page)
+{
+ __tlb_remove_page(tlb, page);
}
/**
diff --git a/arch/um/include/shared/os.h b/arch/um/include/shared/os.h
index c4617ba..83c7c2e 100644
--- a/arch/um/include/shared/os.h
+++ b/arch/um/include/shared/os.h
@@ -29,6 +29,12 @@
#define OS_ACC_R_OK 4 /* Test for read permission. */
#define OS_ACC_RW_OK (OS_ACC_W_OK | OS_ACC_R_OK) /* Test for RW permission */
+#ifdef CONFIG_64BIT
+#define OS_LIB_PATH "/usr/lib64/"
+#else
+#define OS_LIB_PATH "/usr/lib/"
+#endif
+
/*
* types taken from stat_file() in hostfs_user.c
* (if they are wrong here, they are wrong there...).
@@ -238,6 +244,7 @@
extern void setup_machinename(char *machine_out);
extern void setup_hostinfo(char *buf, int len);
extern void os_dump_core(void) __attribute__ ((noreturn));
+extern void um_early_printk(const char *s, unsigned int n);
/* time.c */
extern void idle_sleep(unsigned long long nsecs);
diff --git a/arch/um/kernel/Makefile b/arch/um/kernel/Makefile
index 1119233..c4491c1 100644
--- a/arch/um/kernel/Makefile
+++ b/arch/um/kernel/Makefile
@@ -17,6 +17,7 @@
obj-$(CONFIG_BLK_DEV_INITRD) += initrd.o
obj-$(CONFIG_GPROF) += gprof_syms.o
obj-$(CONFIG_GCOV) += gmon_syms.o
+obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
USER_OBJS := config.o
diff --git a/arch/um/kernel/early_printk.c b/arch/um/kernel/early_printk.c
new file mode 100644
index 0000000..ec649bf
--- /dev/null
+++ b/arch/um/kernel/early_printk.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (C) 2011 Richard Weinberger <richrd@nod.at>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/console.h>
+#include <linux/init.h>
+#include "os.h"
+
+static void early_console_write(struct console *con, const char *s, unsigned int n)
+{
+ um_early_printk(s, n);
+}
+
+static struct console early_console = {
+ .name = "earlycon",
+ .write = early_console_write,
+ .flags = CON_BOOT,
+ .index = -1,
+};
+
+static int __init setup_early_printk(char *buf)
+{
+ register_console(&early_console);
+
+ return 0;
+}
+
+early_param("earlyprintk", setup_early_printk);
diff --git a/arch/um/kernel/smp.c b/arch/um/kernel/smp.c
index eefb107..155206a 100644
--- a/arch/um/kernel/smp.c
+++ b/arch/um/kernel/smp.c
@@ -7,9 +7,6 @@
#include "asm/pgalloc.h"
#include "asm/tlb.h"
-/* For some reason, mmu_gathers are referenced when CONFIG_SMP is off. */
-DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
-
#ifdef CONFIG_SMP
#include "linux/sched.h"
diff --git a/arch/um/kernel/trap.c b/arch/um/kernel/trap.c
index 637c650..8c7b882 100644
--- a/arch/um/kernel/trap.c
+++ b/arch/um/kernel/trap.c
@@ -113,6 +113,27 @@
return 0;
}
+static void show_segv_info(struct uml_pt_regs *regs)
+{
+ struct task_struct *tsk = current;
+ struct faultinfo *fi = UPT_FAULTINFO(regs);
+
+ if (!unhandled_signal(tsk, SIGSEGV))
+ return;
+
+ if (!printk_ratelimit())
+ return;
+
+ printk("%s%s[%d]: segfault at %lx ip %p sp %p error %x",
+ task_pid_nr(tsk) > 1 ? KERN_INFO : KERN_EMERG,
+ tsk->comm, task_pid_nr(tsk), FAULT_ADDRESS(*fi),
+ (void *)UPT_IP(regs), (void *)UPT_SP(regs),
+ fi->error_code);
+
+ print_vma_addr(KERN_CONT " in ", UPT_IP(regs));
+ printk(KERN_CONT "\n");
+}
+
static void bad_segv(struct faultinfo fi, unsigned long ip)
{
struct siginfo si;
@@ -141,6 +162,7 @@
struct faultinfo * fi = UPT_FAULTINFO(regs);
if (UPT_IS_USER(regs) && !SEGV_IS_FIXABLE(fi)) {
+ show_segv_info(regs);
bad_segv(*fi, UPT_IP(regs));
return;
}
@@ -202,6 +224,8 @@
address, ip);
}
+ show_segv_info(regs);
+
if (err == -EACCES) {
si.si_signo = SIGBUS;
si.si_errno = 0;
diff --git a/arch/um/os-Linux/main.c b/arch/um/os-Linux/main.c
index eee69b9..fb2a97a 100644
--- a/arch/um/os-Linux/main.c
+++ b/arch/um/os-Linux/main.c
@@ -78,7 +78,7 @@
}
}
-#define UML_LIB_PATH ":/usr/lib/uml"
+#define UML_LIB_PATH ":" OS_LIB_PATH "/uml"
static void setup_env_path(void)
{
@@ -142,7 +142,6 @@
*/
install_fatal_handler(SIGINT);
install_fatal_handler(SIGTERM);
- install_fatal_handler(SIGHUP);
scan_elf_aux(envp);
diff --git a/arch/um/os-Linux/process.c b/arch/um/os-Linux/process.c
index e0477c3..0c45dc8 100644
--- a/arch/um/os-Linux/process.c
+++ b/arch/um/os-Linux/process.c
@@ -253,6 +253,7 @@
SA_ONSTACK | SA_RESTART, SIGUSR1, SIGIO, SIGWINCH, SIGALRM,
SIGVTALRM, -1);
signal(SIGWINCH, SIG_IGN);
+ signal(SIGTERM, SIG_DFL);
}
int run_kernel_thread(int (*fn)(void *), void *arg, jmp_buf **jmp_ptr)
diff --git a/arch/um/os-Linux/util.c b/arch/um/os-Linux/util.c
index 42827ca..5803b18 100644
--- a/arch/um/os-Linux/util.c
+++ b/arch/um/os-Linux/util.c
@@ -139,3 +139,8 @@
uml_abort();
}
+
+void um_early_printk(const char *s, unsigned int n)
+{
+ printf("%.*s", n, s);
+}
diff --git a/arch/unicore32/Kconfig.debug b/arch/unicore32/Kconfig.debug
index 3140151..ae2ec33 100644
--- a/arch/unicore32/Kconfig.debug
+++ b/arch/unicore32/Kconfig.debug
@@ -27,13 +27,6 @@
with klogd/syslogd or the X server. You should normally N here,
unless you want to debug such a crash.
-config DEBUG_STACK_USAGE
- bool "Enable stack utilization instrumentation"
- depends on DEBUG_KERNEL
- help
- Enables the display of the minimum amount of free stack which each
- task has ever had available in the sysrq-T output.
-
# These options are only for real kernel hackers who want to get their hands dirty.
config DEBUG_LL
bool "Kernel low-level debugging functions"
diff --git a/arch/unicore32/mm/init.c b/arch/unicore32/mm/init.c
index 1fc0263..2d3e711 100644
--- a/arch/unicore32/mm/init.c
+++ b/arch/unicore32/mm/init.c
@@ -62,7 +62,7 @@
struct meminfo *mi = &meminfo;
printk(KERN_DEFAULT "Mem-info:\n");
- show_free_areas();
+ show_free_areas(filter);
for_each_bank(i, mi) {
struct membank *bank = &mi->bank[i];
diff --git a/arch/unicore32/mm/mmu.c b/arch/unicore32/mm/mmu.c
index db2d334..3e5c3e5 100644
--- a/arch/unicore32/mm/mmu.c
+++ b/arch/unicore32/mm/mmu.c
@@ -30,8 +30,6 @@
#include "mm.h"
-DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
-
/*
* empty_zero_page is a special page that is used for
* zero-initialized data and COW.
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 880fcb6..483775f 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -17,8 +17,6 @@
config X86
def_bool y
select HAVE_AOUT if X86_32
- select HAVE_READQ
- select HAVE_WRITEQ
select HAVE_UNSTABLE_SCHED_CLOCK
select HAVE_IDE
select HAVE_OPROFILE
@@ -917,6 +915,7 @@
config I8K
tristate "Dell laptop support"
+ select HWMON
---help---
This adds a driver to safely access the System Management Mode
of the CPU on the Dell Inspiron 8000. The System Management Mode
diff --git a/arch/x86/Kconfig.debug b/arch/x86/Kconfig.debug
index 615e188..c0f8a5c 100644
--- a/arch/x86/Kconfig.debug
+++ b/arch/x86/Kconfig.debug
@@ -66,26 +66,6 @@
This option will cause messages to be printed if free stack space
drops below a certain limit.
-config DEBUG_STACK_USAGE
- bool "Stack utilization instrumentation"
- depends on DEBUG_KERNEL
- ---help---
- Enables the display of the minimum amount of free stack which each
- task has ever had available in the sysrq-T and sysrq-P debug output.
-
- This option will slow down process creation somewhat.
-
-config DEBUG_PER_CPU_MAPS
- bool "Debug access to per_cpu maps"
- depends on DEBUG_KERNEL
- depends on SMP
- ---help---
- Say Y to verify that the per_cpu map being accessed has
- been setup. Adds a fair amount of code to kernel memory
- and decreases performance.
-
- Say N if unsure.
-
config X86_PTDUMP
bool "Export kernel pagetable layout to userspace via debugfs"
depends on DEBUG_KERNEL
diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h
index a0c46f0..4a0b7c7 100644
--- a/arch/x86/include/asm/apic.h
+++ b/arch/x86/include/asm/apic.h
@@ -381,6 +381,26 @@
extern struct apic *apic;
/*
+ * APIC drivers are probed based on how they are listed in the .apicdrivers
+ * section. So the order is important and enforced by the ordering
+ * of different apic driver files in the Makefile.
+ *
+ * For the files having two apic drivers, we use apic_drivers()
+ * to enforce the order with in them.
+ */
+#define apic_driver(sym) \
+ static struct apic *__apicdrivers_##sym __used \
+ __aligned(sizeof(struct apic *)) \
+ __section(.apicdrivers) = { &sym }
+
+#define apic_drivers(sym1, sym2) \
+ static struct apic *__apicdrivers_##sym1##sym2[2] __used \
+ __aligned(sizeof(struct apic *)) \
+ __section(.apicdrivers) = { &sym1, &sym2 }
+
+extern struct apic *__apicdrivers[], *__apicdrivers_end[];
+
+/*
* APIC functionality to boot other CPUs - only used on SMP:
*/
#ifdef CONFIG_SMP
@@ -458,15 +478,10 @@
#define DEFAULT_TRAMPOLINE_PHYS_HIGH 0x469
#ifdef CONFIG_X86_64
-extern struct apic apic_flat;
-extern struct apic apic_physflat;
-extern struct apic apic_x2apic_cluster;
-extern struct apic apic_x2apic_phys;
extern int default_acpi_madt_oem_check(char *, char *);
extern void apic_send_IPI_self(int vector);
-extern struct apic apic_x2apic_uv_x;
DECLARE_PER_CPU(int, x2apic_extra_bits);
extern int default_cpu_present_to_apicid(int mps_cpu);
@@ -480,7 +495,7 @@
return;
}
-extern void generic_bigsmp_probe(void);
+extern struct apic *generic_bigsmp_probe(void);
#ifdef CONFIG_X86_LOCAL_APIC
@@ -516,8 +531,6 @@
#ifdef CONFIG_X86_32
-extern struct apic apic_default;
-
static inline int noop_x86_32_early_logical_apicid(int cpu)
{
return BAD_APICID;
diff --git a/arch/x86/include/asm/io.h b/arch/x86/include/asm/io.h
index 0722730..d02804d 100644
--- a/arch/x86/include/asm/io.h
+++ b/arch/x86/include/asm/io.h
@@ -38,7 +38,6 @@
#include <linux/string.h>
#include <linux/compiler.h>
-#include <asm-generic/int-ll64.h>
#include <asm/page.h>
#include <xen/xen.h>
@@ -87,27 +86,6 @@
build_mmio_read(readq, "q", unsigned long, "=r", :"memory")
build_mmio_write(writeq, "q", unsigned long, "r", :"memory")
-#else
-
-static inline __u64 readq(const volatile void __iomem *addr)
-{
- const volatile u32 __iomem *p = addr;
- u32 low, high;
-
- low = readl(p);
- high = readl(p + 1);
-
- return low + ((u64)high << 32);
-}
-
-static inline void writeq(__u64 val, volatile void __iomem *addr)
-{
- writel(val, addr);
- writel(val >> 32, addr+4);
-}
-
-#endif
-
#define readq_relaxed(a) readq(a)
#define __raw_readq(a) readq(a)
@@ -117,6 +95,8 @@
#define readq readq
#define writeq writeq
+#endif
+
/**
* virt_to_phys - map virtual addresses to physical
* @address: address to remap
diff --git a/arch/x86/include/asm/io_apic.h b/arch/x86/include/asm/io_apic.h
index a97a240..690d1cc 100644
--- a/arch/x86/include/asm/io_apic.h
+++ b/arch/x86/include/asm/io_apic.h
@@ -105,13 +105,13 @@
* # of IO-APICs and # of IRQ routing registers
*/
extern int nr_ioapics;
-extern int nr_ioapic_registers[MAX_IO_APICS];
+
+extern int mpc_ioapic_id(int ioapic);
+extern unsigned int mpc_ioapic_addr(int ioapic);
+extern struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int ioapic);
#define MP_MAX_IOAPIC_PIN 127
-/* I/O APIC entries */
-extern struct mpc_ioapic mp_ioapics[MAX_IO_APICS];
-
/* # of MP IRQ source entries */
extern int mp_irq_entries;
@@ -152,11 +152,9 @@
int io_apic_setup_irq_pin_once(unsigned int irq, int node, struct io_apic_irq_attr *attr);
-extern struct IO_APIC_route_entry **alloc_ioapic_entries(void);
-extern void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries);
-extern int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries);
-extern void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries);
-extern int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries);
+extern int save_ioapic_entries(void);
+extern void mask_ioapic_entries(void);
+extern int restore_ioapic_entries(void);
extern int get_nr_irqs_gsi(void);
@@ -192,19 +190,13 @@
static inline int io_apic_set_pci_routing(struct device *dev, int irq,
struct io_apic_irq_attr *irq_attr) { return 0; }
-static inline struct IO_APIC_route_entry **alloc_ioapic_entries(void)
-{
- return NULL;
-}
-
-static inline void free_ioapic_entries(struct IO_APIC_route_entry **ent) { }
-static inline int save_IO_APIC_setup(struct IO_APIC_route_entry **ent)
+static inline int save_ioapic_entries(void)
{
return -ENOMEM;
}
-static inline void mask_IO_APIC_setup(struct IO_APIC_route_entry **ent) { }
-static inline int restore_IO_APIC_setup(struct IO_APIC_route_entry **ent)
+static inline void mask_ioapic_entries(void) { }
+static inline int restore_ioapic_entries(void)
{
return -ENOMEM;
}
diff --git a/arch/x86/include/asm/linkage.h b/arch/x86/include/asm/linkage.h
index 12d55e7..4814297 100644
--- a/arch/x86/include/asm/linkage.h
+++ b/arch/x86/include/asm/linkage.h
@@ -8,11 +8,6 @@
#ifdef CONFIG_X86_32
#define asmlinkage CPP_ASMLINKAGE __attribute__((regparm(0)))
-/*
- * For 32-bit UML - mark functions implemented in assembly that use
- * regparm input parameters:
- */
-#define asmregparm __attribute__((regparm(3)))
/*
* Make sure the compiler doesn't do anything stupid with the
diff --git a/arch/x86/include/asm/pci.h b/arch/x86/include/asm/pci.h
index 6761292..d498943 100644
--- a/arch/x86/include/asm/pci.h
+++ b/arch/x86/include/asm/pci.h
@@ -135,8 +135,6 @@
#include "pci_64.h"
#endif
-void dma32_reserve_bootmem(void);
-
/* implement the pci_ DMA API in terms of the generic device dma_ one */
#include <asm-generic/pci-dma-compat.h>
diff --git a/arch/x86/include/asm/percpu.h b/arch/x86/include/asm/percpu.h
index 53278b0..a0a9779 100644
--- a/arch/x86/include/asm/percpu.h
+++ b/arch/x86/include/asm/percpu.h
@@ -509,6 +509,11 @@
* it in software. The address used in the cmpxchg16 instruction must be
* aligned to a 16 byte boundary.
*/
+#ifdef CONFIG_SMP
+#define CMPXCHG16B_EMU_CALL "call this_cpu_cmpxchg16b_emu\n\t" ASM_NOP3
+#else
+#define CMPXCHG16B_EMU_CALL "call this_cpu_cmpxchg16b_emu\n\t" ASM_NOP2
+#endif
#define percpu_cmpxchg16b_double(pcp1, o1, o2, n1, n2) \
({ \
char __ret; \
@@ -517,7 +522,7 @@
typeof(o2) __o2 = o2; \
typeof(o2) __n2 = n2; \
typeof(o2) __dummy; \
- alternative_io("call this_cpu_cmpxchg16b_emu\n\t" ASM_NOP4, \
+ alternative_io(CMPXCHG16B_EMU_CALL, \
"cmpxchg16b " __percpu_prefix "(%%rsi)\n\tsetz %0\n\t", \
X86_FEATURE_CX16, \
ASM_OUTPUT2("=a"(__ret), "=d"(__dummy)), \
diff --git a/arch/x86/include/asm/x2apic.h b/arch/x86/include/asm/x2apic.h
new file mode 100644
index 0000000..6bf5b8e
--- /dev/null
+++ b/arch/x86/include/asm/x2apic.h
@@ -0,0 +1,62 @@
+/*
+ * Common bits for X2APIC cluster/physical modes.
+ */
+
+#ifndef _ASM_X86_X2APIC_H
+#define _ASM_X86_X2APIC_H
+
+#include <asm/apic.h>
+#include <asm/ipi.h>
+#include <linux/cpumask.h>
+
+/*
+ * Need to use more than cpu 0, because we need more vectors
+ * when MSI-X are used.
+ */
+static const struct cpumask *x2apic_target_cpus(void)
+{
+ return cpu_online_mask;
+}
+
+static int x2apic_apic_id_registered(void)
+{
+ return 1;
+}
+
+/*
+ * For now each logical cpu is in its own vector allocation domain.
+ */
+static void x2apic_vector_allocation_domain(int cpu, struct cpumask *retmask)
+{
+ cpumask_clear(retmask);
+ cpumask_set_cpu(cpu, retmask);
+}
+
+static void
+__x2apic_send_IPI_dest(unsigned int apicid, int vector, unsigned int dest)
+{
+ unsigned long cfg = __prepare_ICR(0, vector, dest);
+ native_x2apic_icr_write(cfg, apicid);
+}
+
+static unsigned int x2apic_get_apic_id(unsigned long id)
+{
+ return id;
+}
+
+static unsigned long x2apic_set_apic_id(unsigned int id)
+{
+ return id;
+}
+
+static int x2apic_phys_pkg_id(int initial_apicid, int index_msb)
+{
+ return initial_apicid >> index_msb;
+}
+
+static void x2apic_send_IPI_self(int vector)
+{
+ apic_write(APIC_SELF_IPI, vector);
+}
+
+#endif /* _ASM_X86_X2APIC_H */
diff --git a/arch/x86/kernel/acpi/boot.c b/arch/x86/kernel/acpi/boot.c
index 9a966c5..4558f0d 100644
--- a/arch/x86/kernel/acpi/boot.c
+++ b/arch/x86/kernel/acpi/boot.c
@@ -970,7 +970,7 @@
mp_irq.irqflag = (trigger << 2) | polarity;
mp_irq.srcbus = MP_ISA_BUS;
mp_irq.srcbusirq = bus_irq; /* IRQ */
- mp_irq.dstapic = mp_ioapics[ioapic].apicid; /* APIC ID */
+ mp_irq.dstapic = mpc_ioapic_id(ioapic); /* APIC ID */
mp_irq.dstirq = pin; /* INTIN# */
mp_save_irq(&mp_irq);
@@ -1021,7 +1021,7 @@
if (ioapic < 0)
continue;
pin = mp_find_ioapic_pin(ioapic, gsi);
- dstapic = mp_ioapics[ioapic].apicid;
+ dstapic = mpc_ioapic_id(ioapic);
for (idx = 0; idx < mp_irq_entries; idx++) {
struct mpc_intsrc *irq = mp_irqs + idx;
@@ -1082,7 +1082,7 @@
mp_irq.srcbus = number;
mp_irq.srcbusirq = (((devfn >> 3) & 0x1f) << 2) | ((pin - 1) & 3);
ioapic = mp_find_ioapic(gsi);
- mp_irq.dstapic = mp_ioapics[ioapic].apicid;
+ mp_irq.dstapic = mpc_ioapic_id(ioapic);
mp_irq.dstirq = mp_find_ioapic_pin(ioapic, gsi);
mp_save_irq(&mp_irq);
@@ -1113,7 +1113,7 @@
if (ioapic_pin > MP_MAX_IOAPIC_PIN) {
printk(KERN_ERR "Invalid reference to IOAPIC pin "
- "%d-%d\n", mp_ioapics[ioapic].apicid,
+ "%d-%d\n", mpc_ioapic_id(ioapic),
ioapic_pin);
return gsi;
}
diff --git a/arch/x86/kernel/apic/Makefile b/arch/x86/kernel/apic/Makefile
index 3966b56..767fd04 100644
--- a/arch/x86/kernel/apic/Makefile
+++ b/arch/x86/kernel/apic/Makefile
@@ -2,20 +2,25 @@
# Makefile for local APIC drivers and for the IO-APIC code
#
-obj-$(CONFIG_X86_LOCAL_APIC) += apic.o apic_noop.o probe_$(BITS).o ipi.o
+obj-$(CONFIG_X86_LOCAL_APIC) += apic.o apic_noop.o ipi.o
obj-y += hw_nmi.o
obj-$(CONFIG_X86_IO_APIC) += io_apic.o
obj-$(CONFIG_SMP) += ipi.o
ifeq ($(CONFIG_X86_64),y)
-obj-y += apic_flat_64.o
-obj-$(CONFIG_X86_X2APIC) += x2apic_cluster.o
-obj-$(CONFIG_X86_X2APIC) += x2apic_phys.o
+# APIC probe will depend on the listing order here
obj-$(CONFIG_X86_UV) += x2apic_uv_x.o
+obj-$(CONFIG_X86_X2APIC) += x2apic_phys.o
+obj-$(CONFIG_X86_X2APIC) += x2apic_cluster.o
+obj-y += apic_flat_64.o
endif
-obj-$(CONFIG_X86_BIGSMP) += bigsmp_32.o
+# APIC probe will depend on the listing order here
obj-$(CONFIG_X86_NUMAQ) += numaq_32.o
-obj-$(CONFIG_X86_ES7000) += es7000_32.o
obj-$(CONFIG_X86_SUMMIT) += summit_32.o
+obj-$(CONFIG_X86_BIGSMP) += bigsmp_32.o
+obj-$(CONFIG_X86_ES7000) += es7000_32.o
+
+# For 32bit, probe_32 need to be listed last
+obj-$(CONFIG_X86_LOCAL_APIC) += probe_$(BITS).o
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index f92a8e5..b961af8 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -1461,7 +1461,6 @@
void __init enable_IR_x2apic(void)
{
unsigned long flags;
- struct IO_APIC_route_entry **ioapic_entries;
int ret, x2apic_enabled = 0;
int dmar_table_init_ret;
@@ -1469,13 +1468,7 @@
if (dmar_table_init_ret && !x2apic_supported())
return;
- ioapic_entries = alloc_ioapic_entries();
- if (!ioapic_entries) {
- pr_err("Allocate ioapic_entries failed\n");
- goto out;
- }
-
- ret = save_IO_APIC_setup(ioapic_entries);
+ ret = save_ioapic_entries();
if (ret) {
pr_info("Saving IO-APIC state failed: %d\n", ret);
goto out;
@@ -1483,7 +1476,7 @@
local_irq_save(flags);
legacy_pic->mask_all();
- mask_IO_APIC_setup(ioapic_entries);
+ mask_ioapic_entries();
if (dmar_table_init_ret)
ret = 0;
@@ -1514,14 +1507,11 @@
nox2apic:
if (!ret) /* IR enabling failed */
- restore_IO_APIC_setup(ioapic_entries);
+ restore_ioapic_entries();
legacy_pic->restore_mask();
local_irq_restore(flags);
out:
- if (ioapic_entries)
- free_ioapic_entries(ioapic_entries);
-
if (x2apic_enabled)
return;
@@ -2095,28 +2085,20 @@
{
unsigned int l, h;
unsigned long flags;
- int maxlvt, ret;
- struct IO_APIC_route_entry **ioapic_entries = NULL;
+ int maxlvt;
if (!apic_pm_state.active)
return;
local_irq_save(flags);
if (intr_remapping_enabled) {
- ioapic_entries = alloc_ioapic_entries();
- if (!ioapic_entries) {
- WARN(1, "Alloc ioapic_entries in lapic resume failed.");
- goto restore;
- }
-
- ret = save_IO_APIC_setup(ioapic_entries);
- if (ret) {
- WARN(1, "Saving IO-APIC state failed: %d\n", ret);
- free_ioapic_entries(ioapic_entries);
- goto restore;
- }
-
- mask_IO_APIC_setup(ioapic_entries);
+ /*
+ * IO-APIC and PIC have their own resume routines.
+ * We just mask them here to make sure the interrupt
+ * subsystem is completely quiet while we enable x2apic
+ * and interrupt-remapping.
+ */
+ mask_ioapic_entries();
legacy_pic->mask_all();
}
@@ -2159,13 +2141,9 @@
apic_write(APIC_ESR, 0);
apic_read(APIC_ESR);
- if (intr_remapping_enabled) {
+ if (intr_remapping_enabled)
reenable_intr_remapping(x2apic_mode);
- legacy_pic->restore_mask();
- restore_IO_APIC_setup(ioapic_entries);
- free_ioapic_entries(ioapic_entries);
- }
-restore:
+
local_irq_restore(flags);
}
diff --git a/arch/x86/kernel/apic/apic_flat_64.c b/arch/x86/kernel/apic/apic_flat_64.c
index 5652d31..f7a41e4 100644
--- a/arch/x86/kernel/apic/apic_flat_64.c
+++ b/arch/x86/kernel/apic/apic_flat_64.c
@@ -16,6 +16,7 @@
#include <linux/ctype.h>
#include <linux/init.h>
#include <linux/hardirq.h>
+#include <linux/module.h>
#include <asm/smp.h>
#include <asm/apic.h>
#include <asm/ipi.h>
@@ -24,6 +25,12 @@
#include <acpi/acpi_bus.h>
#endif
+static struct apic apic_physflat;
+static struct apic apic_flat;
+
+struct apic __read_mostly *apic = &apic_flat;
+EXPORT_SYMBOL_GPL(apic);
+
static int flat_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
{
return 1;
@@ -164,7 +171,7 @@
return initial_apic_id >> index_msb;
}
-struct apic apic_flat = {
+static struct apic apic_flat = {
.name = "flat",
.probe = NULL,
.acpi_madt_oem_check = flat_acpi_madt_oem_check,
@@ -312,10 +319,18 @@
return per_cpu(x86_cpu_to_apicid, cpu);
}
-struct apic apic_physflat = {
+static int physflat_probe(void)
+{
+ if (apic == &apic_physflat || num_possible_cpus() > 8)
+ return 1;
+
+ return 0;
+}
+
+static struct apic apic_physflat = {
.name = "physical flat",
- .probe = NULL,
+ .probe = physflat_probe,
.acpi_madt_oem_check = physflat_acpi_madt_oem_check,
.apic_id_registered = flat_apic_id_registered,
@@ -369,3 +384,8 @@
.wait_icr_idle = native_apic_wait_icr_idle,
.safe_wait_icr_idle = native_safe_apic_wait_icr_idle,
};
+
+/*
+ * We need to check for physflat first, so this order is important.
+ */
+apic_drivers(apic_physflat, apic_flat);
diff --git a/arch/x86/kernel/apic/bigsmp_32.c b/arch/x86/kernel/apic/bigsmp_32.c
index d84ac5a5..efd737e 100644
--- a/arch/x86/kernel/apic/bigsmp_32.c
+++ b/arch/x86/kernel/apic/bigsmp_32.c
@@ -193,7 +193,7 @@
return dmi_bigsmp;
}
-struct apic apic_bigsmp = {
+static struct apic apic_bigsmp = {
.name = "bigsmp",
.probe = probe_bigsmp,
@@ -254,3 +254,13 @@
.x86_32_early_logical_apicid = bigsmp_early_logical_apicid,
};
+
+struct apic * __init generic_bigsmp_probe(void)
+{
+ if (probe_bigsmp())
+ return &apic_bigsmp;
+
+ return NULL;
+}
+
+apic_driver(apic_bigsmp);
diff --git a/arch/x86/kernel/apic/es7000_32.c b/arch/x86/kernel/apic/es7000_32.c
index 70533de..9536b3f 100644
--- a/arch/x86/kernel/apic/es7000_32.c
+++ b/arch/x86/kernel/apic/es7000_32.c
@@ -620,7 +620,7 @@
}
/* We've been warned by a false positive warning.Use __refdata to keep calm. */
-struct apic __refdata apic_es7000_cluster = {
+static struct apic __refdata apic_es7000_cluster = {
.name = "es7000",
.probe = probe_es7000,
@@ -685,7 +685,7 @@
.x86_32_early_logical_apicid = es7000_early_logical_apicid,
};
-struct apic __refdata apic_es7000 = {
+static struct apic __refdata apic_es7000 = {
.name = "es7000",
.probe = probe_es7000,
@@ -747,3 +747,9 @@
.x86_32_early_logical_apicid = es7000_early_logical_apicid,
};
+
+/*
+ * Need to check for es7000 followed by es7000_cluster, so this order
+ * in apic_drivers is important.
+ */
+apic_drivers(apic_es7000, apic_es7000_cluster);
diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c
index 45fd33d..e529339 100644
--- a/arch/x86/kernel/apic/io_apic.c
+++ b/arch/x86/kernel/apic/io_apic.c
@@ -76,18 +76,41 @@
static DEFINE_RAW_SPINLOCK(ioapic_lock);
static DEFINE_RAW_SPINLOCK(vector_lock);
-/*
- * # of IRQ routing registers
- */
-int nr_ioapic_registers[MAX_IO_APICS];
+static struct ioapic {
+ /*
+ * # of IRQ routing registers
+ */
+ int nr_registers;
+ /*
+ * Saved state during suspend/resume, or while enabling intr-remap.
+ */
+ struct IO_APIC_route_entry *saved_registers;
+ /* I/O APIC config */
+ struct mpc_ioapic mp_config;
+ /* IO APIC gsi routing info */
+ struct mp_ioapic_gsi gsi_config;
+ DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1);
+} ioapics[MAX_IO_APICS];
-/* I/O APIC entries */
-struct mpc_ioapic mp_ioapics[MAX_IO_APICS];
+#define mpc_ioapic_ver(id) ioapics[id].mp_config.apicver
+
+int mpc_ioapic_id(int id)
+{
+ return ioapics[id].mp_config.apicid;
+}
+
+unsigned int mpc_ioapic_addr(int id)
+{
+ return ioapics[id].mp_config.apicaddr;
+}
+
+struct mp_ioapic_gsi *mp_ioapic_gsi_routing(int id)
+{
+ return &ioapics[id].gsi_config;
+}
+
int nr_ioapics;
-/* IO APIC gsi routing info */
-struct mp_ioapic_gsi mp_gsi_routing[MAX_IO_APICS];
-
/* The one past the highest gsi number used */
u32 gsi_top;
@@ -179,6 +202,14 @@
io_apic_irqs = ~0UL;
}
+ for (i = 0; i < nr_ioapics; i++) {
+ ioapics[i].saved_registers =
+ kzalloc(sizeof(struct IO_APIC_route_entry) *
+ ioapics[i].nr_registers, GFP_KERNEL);
+ if (!ioapics[i].saved_registers)
+ pr_err("IOAPIC %d: suspend/resume impossible!\n", i);
+ }
+
cfg = irq_cfgx;
count = ARRAY_SIZE(irq_cfgx);
node = cpu_to_node(0);
@@ -297,7 +328,7 @@
static __attribute_const__ struct io_apic __iomem *io_apic_base(int idx)
{
return (void __iomem *) __fix_to_virt(FIX_IO_APIC_BASE_0 + idx)
- + (mp_ioapics[idx].apicaddr & ~PAGE_MASK);
+ + (mpc_ioapic_addr(idx) & ~PAGE_MASK);
}
static inline void io_apic_eoi(unsigned int apic, unsigned int vector)
@@ -573,7 +604,7 @@
int apic, pin;
for (apic = 0; apic < nr_ioapics; apic++)
- for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
+ for (pin = 0; pin < ioapics[apic].nr_registers; pin++)
clear_IO_APIC_pin(apic, pin);
}
@@ -615,74 +646,43 @@
__setup("pirq=", ioapic_pirq_setup);
#endif /* CONFIG_X86_32 */
-struct IO_APIC_route_entry **alloc_ioapic_entries(void)
-{
- int apic;
- struct IO_APIC_route_entry **ioapic_entries;
-
- ioapic_entries = kzalloc(sizeof(*ioapic_entries) * nr_ioapics,
- GFP_KERNEL);
- if (!ioapic_entries)
- return 0;
-
- for (apic = 0; apic < nr_ioapics; apic++) {
- ioapic_entries[apic] =
- kzalloc(sizeof(struct IO_APIC_route_entry) *
- nr_ioapic_registers[apic], GFP_KERNEL);
- if (!ioapic_entries[apic])
- goto nomem;
- }
-
- return ioapic_entries;
-
-nomem:
- while (--apic >= 0)
- kfree(ioapic_entries[apic]);
- kfree(ioapic_entries);
-
- return 0;
-}
-
/*
* Saves all the IO-APIC RTE's
*/
-int save_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
+int save_ioapic_entries(void)
{
int apic, pin;
-
- if (!ioapic_entries)
- return -ENOMEM;
+ int err = 0;
for (apic = 0; apic < nr_ioapics; apic++) {
- if (!ioapic_entries[apic])
- return -ENOMEM;
+ if (!ioapics[apic].saved_registers) {
+ err = -ENOMEM;
+ continue;
+ }
- for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
- ioapic_entries[apic][pin] =
+ for (pin = 0; pin < ioapics[apic].nr_registers; pin++)
+ ioapics[apic].saved_registers[pin] =
ioapic_read_entry(apic, pin);
}
- return 0;
+ return err;
}
/*
* Mask all IO APIC entries.
*/
-void mask_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
+void mask_ioapic_entries(void)
{
int apic, pin;
- if (!ioapic_entries)
- return;
-
for (apic = 0; apic < nr_ioapics; apic++) {
- if (!ioapic_entries[apic])
- break;
+ if (!ioapics[apic].saved_registers)
+ continue;
- for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
+ for (pin = 0; pin < ioapics[apic].nr_registers; pin++) {
struct IO_APIC_route_entry entry;
- entry = ioapic_entries[apic][pin];
+ entry = ioapics[apic].saved_registers[pin];
if (!entry.mask) {
entry.mask = 1;
ioapic_write_entry(apic, pin, entry);
@@ -692,36 +692,23 @@
}
/*
- * Restore IO APIC entries which was saved in ioapic_entries.
+ * Restore IO APIC entries which was saved in the ioapic structure.
*/
-int restore_IO_APIC_setup(struct IO_APIC_route_entry **ioapic_entries)
+int restore_ioapic_entries(void)
{
int apic, pin;
- if (!ioapic_entries)
- return -ENOMEM;
-
for (apic = 0; apic < nr_ioapics; apic++) {
- if (!ioapic_entries[apic])
- return -ENOMEM;
+ if (!ioapics[apic].saved_registers)
+ continue;
- for (pin = 0; pin < nr_ioapic_registers[apic]; pin++)
+ for (pin = 0; pin < ioapics[apic].nr_registers; pin++)
ioapic_write_entry(apic, pin,
- ioapic_entries[apic][pin]);
+ ioapics[apic].saved_registers[pin]);
}
return 0;
}
-void free_ioapic_entries(struct IO_APIC_route_entry **ioapic_entries)
-{
- int apic;
-
- for (apic = 0; apic < nr_ioapics; apic++)
- kfree(ioapic_entries[apic]);
-
- kfree(ioapic_entries);
-}
-
/*
* Find the IRQ entry number of a certain pin.
*/
@@ -731,7 +718,7 @@
for (i = 0; i < mp_irq_entries; i++)
if (mp_irqs[i].irqtype == type &&
- (mp_irqs[i].dstapic == mp_ioapics[apic].apicid ||
+ (mp_irqs[i].dstapic == mpc_ioapic_id(apic) ||
mp_irqs[i].dstapic == MP_APIC_ALL) &&
mp_irqs[i].dstirq == pin)
return i;
@@ -773,7 +760,7 @@
if (i < mp_irq_entries) {
int apic;
for(apic = 0; apic < nr_ioapics; apic++) {
- if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic)
+ if (mpc_ioapic_id(apic) == mp_irqs[i].dstapic)
return apic;
}
}
@@ -942,6 +929,7 @@
{
int irq;
int bus = mp_irqs[idx].srcbus;
+ struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(apic);
/*
* Debugging check, we are in big trouble if this message pops up!
@@ -952,7 +940,7 @@
if (test_bit(bus, mp_bus_not_pci)) {
irq = mp_irqs[idx].srcbusirq;
} else {
- u32 gsi = mp_gsi_routing[apic].gsi_base + pin;
+ u32 gsi = gsi_cfg->gsi_base + pin;
if (gsi >= NR_IRQS_LEGACY)
irq = gsi;
@@ -1003,7 +991,7 @@
int lbus = mp_irqs[i].srcbus;
for (apic = 0; apic < nr_ioapics; apic++)
- if (mp_ioapics[apic].apicid == mp_irqs[i].dstapic ||
+ if (mpc_ioapic_id(apic) == mp_irqs[i].dstapic ||
mp_irqs[i].dstapic == MP_APIC_ALL)
break;
@@ -1222,7 +1210,7 @@
int apic, idx, pin;
for (apic = 0; apic < nr_ioapics; apic++) {
- for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
+ for (pin = 0; pin < ioapics[apic].nr_registers; pin++) {
idx = find_irq_entry(apic, pin, mp_INT);
if ((idx != -1) && (irq == pin_2_irq(idx, apic, pin)))
return irq_trigger(idx);
@@ -1350,14 +1338,14 @@
apic_printk(APIC_VERBOSE,KERN_DEBUG
"IOAPIC[%d]: Set routing entry (%d-%d -> 0x%x -> "
"IRQ %d Mode:%i Active:%i)\n",
- apic_id, mp_ioapics[apic_id].apicid, pin, cfg->vector,
+ apic_id, mpc_ioapic_id(apic_id), pin, cfg->vector,
irq, trigger, polarity);
- if (setup_ioapic_entry(mp_ioapics[apic_id].apicid, irq, &entry,
+ if (setup_ioapic_entry(mpc_ioapic_id(apic_id), irq, &entry,
dest, trigger, polarity, cfg->vector, pin)) {
printk("Failed to setup ioapic entry for ioapic %d, pin %d\n",
- mp_ioapics[apic_id].apicid, pin);
+ mpc_ioapic_id(apic_id), pin);
__clear_irq_vector(irq, cfg);
return;
}
@@ -1369,17 +1357,13 @@
ioapic_write_entry(apic_id, pin, entry);
}
-static struct {
- DECLARE_BITMAP(pin_programmed, MP_MAX_IOAPIC_PIN + 1);
-} mp_ioapic_routing[MAX_IO_APICS];
-
static bool __init io_apic_pin_not_connected(int idx, int apic_id, int pin)
{
if (idx != -1)
return false;
apic_printk(APIC_VERBOSE, KERN_DEBUG " apic %d pin %d not connected\n",
- mp_ioapics[apic_id].apicid, pin);
+ mpc_ioapic_id(apic_id), pin);
return true;
}
@@ -1389,7 +1373,7 @@
struct io_apic_irq_attr attr;
unsigned int pin, irq;
- for (pin = 0; pin < nr_ioapic_registers[apic_id]; pin++) {
+ for (pin = 0; pin < ioapics[apic_id].nr_registers; pin++) {
idx = find_irq_entry(apic_id, pin, mp_INT);
if (io_apic_pin_not_connected(idx, apic_id, pin))
continue;
@@ -1511,7 +1495,7 @@
printk(KERN_DEBUG "number of MP IRQ sources: %d.\n", mp_irq_entries);
for (i = 0; i < nr_ioapics; i++)
printk(KERN_DEBUG "number of IO-APIC #%d registers: %d.\n",
- mp_ioapics[i].apicid, nr_ioapic_registers[i]);
+ mpc_ioapic_id(i), ioapics[i].nr_registers);
/*
* We are a bit conservative about what we expect. We have to
@@ -1531,7 +1515,7 @@
raw_spin_unlock_irqrestore(&ioapic_lock, flags);
printk("\n");
- printk(KERN_DEBUG "IO APIC #%d......\n", mp_ioapics[apic].apicid);
+ printk(KERN_DEBUG "IO APIC #%d......\n", mpc_ioapic_id(apic));
printk(KERN_DEBUG ".... register #00: %08X\n", reg_00.raw);
printk(KERN_DEBUG "....... : physical APIC id: %02X\n", reg_00.bits.ID);
printk(KERN_DEBUG "....... : Delivery Type: %X\n", reg_00.bits.delivery_type);
@@ -1825,7 +1809,7 @@
for(apic = 0; apic < nr_ioapics; apic++) {
int pin;
/* See if any of the pins is in ExtINT mode */
- for (pin = 0; pin < nr_ioapic_registers[apic]; pin++) {
+ for (pin = 0; pin < ioapics[apic].nr_registers; pin++) {
struct IO_APIC_route_entry entry;
entry = ioapic_read_entry(apic, pin);
@@ -1949,14 +1933,14 @@
reg_00.raw = io_apic_read(apic_id, 0);
raw_spin_unlock_irqrestore(&ioapic_lock, flags);
- old_id = mp_ioapics[apic_id].apicid;
+ old_id = mpc_ioapic_id(apic_id);
- if (mp_ioapics[apic_id].apicid >= get_physical_broadcast()) {
+ if (mpc_ioapic_id(apic_id) >= get_physical_broadcast()) {
printk(KERN_ERR "BIOS bug, IO-APIC#%d ID is %d in the MPC table!...\n",
- apic_id, mp_ioapics[apic_id].apicid);
+ apic_id, mpc_ioapic_id(apic_id));
printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
reg_00.bits.ID);
- mp_ioapics[apic_id].apicid = reg_00.bits.ID;
+ ioapics[apic_id].mp_config.apicid = reg_00.bits.ID;
}
/*
@@ -1965,9 +1949,9 @@
* 'stuck on smp_invalidate_needed IPI wait' messages.
*/
if (apic->check_apicid_used(&phys_id_present_map,
- mp_ioapics[apic_id].apicid)) {
+ mpc_ioapic_id(apic_id))) {
printk(KERN_ERR "BIOS bug, IO-APIC#%d ID %d is already used!...\n",
- apic_id, mp_ioapics[apic_id].apicid);
+ apic_id, mpc_ioapic_id(apic_id));
for (i = 0; i < get_physical_broadcast(); i++)
if (!physid_isset(i, phys_id_present_map))
break;
@@ -1976,13 +1960,14 @@
printk(KERN_ERR "... fixing up to %d. (tell your hw vendor)\n",
i);
physid_set(i, phys_id_present_map);
- mp_ioapics[apic_id].apicid = i;
+ ioapics[apic_id].mp_config.apicid = i;
} else {
physid_mask_t tmp;
- apic->apicid_to_cpu_present(mp_ioapics[apic_id].apicid, &tmp);
+ apic->apicid_to_cpu_present(mpc_ioapic_id(apic_id),
+ &tmp);
apic_printk(APIC_VERBOSE, "Setting %d in the "
"phys_id_present_map\n",
- mp_ioapics[apic_id].apicid);
+ mpc_ioapic_id(apic_id));
physids_or(phys_id_present_map, phys_id_present_map, tmp);
}
@@ -1990,24 +1975,24 @@
* We need to adjust the IRQ routing table
* if the ID changed.
*/
- if (old_id != mp_ioapics[apic_id].apicid)
+ if (old_id != mpc_ioapic_id(apic_id))
for (i = 0; i < mp_irq_entries; i++)
if (mp_irqs[i].dstapic == old_id)
mp_irqs[i].dstapic
- = mp_ioapics[apic_id].apicid;
+ = mpc_ioapic_id(apic_id);
/*
* Update the ID register according to the right value
* from the MPC table if they are different.
*/
- if (mp_ioapics[apic_id].apicid == reg_00.bits.ID)
+ if (mpc_ioapic_id(apic_id) == reg_00.bits.ID)
continue;
apic_printk(APIC_VERBOSE, KERN_INFO
"...changing IO-APIC physical APIC ID to %d ...",
- mp_ioapics[apic_id].apicid);
+ mpc_ioapic_id(apic_id));
- reg_00.bits.ID = mp_ioapics[apic_id].apicid;
+ reg_00.bits.ID = mpc_ioapic_id(apic_id);
raw_spin_lock_irqsave(&ioapic_lock, flags);
io_apic_write(apic_id, 0, reg_00.raw);
raw_spin_unlock_irqrestore(&ioapic_lock, flags);
@@ -2018,7 +2003,7 @@
raw_spin_lock_irqsave(&ioapic_lock, flags);
reg_00.raw = io_apic_read(apic_id, 0);
raw_spin_unlock_irqrestore(&ioapic_lock, flags);
- if (reg_00.bits.ID != mp_ioapics[apic_id].apicid)
+ if (reg_00.bits.ID != mpc_ioapic_id(apic_id))
printk("could not set ID!\n");
else
apic_printk(APIC_VERBOSE, " ok.\n");
@@ -2404,7 +2389,7 @@
raw_spin_lock_irqsave(&ioapic_lock, flags);
for_each_irq_pin(entry, cfg->irq_2_pin) {
- if (mp_ioapics[entry->apic].apicver >= 0x20) {
+ if (mpc_ioapic_ver(entry->apic) >= 0x20) {
/*
* Intr-remapping uses pin number as the virtual vector
* in the RTE. Actual vector is programmed in
@@ -2918,49 +2903,19 @@
late_initcall(io_apic_bug_finalize);
-static struct IO_APIC_route_entry *ioapic_saved_data[MAX_IO_APICS];
-
-static void suspend_ioapic(int ioapic_id)
+static void resume_ioapic_id(int ioapic_id)
{
- struct IO_APIC_route_entry *saved_data = ioapic_saved_data[ioapic_id];
- int i;
-
- if (!saved_data)
- return;
-
- for (i = 0; i < nr_ioapic_registers[ioapic_id]; i++)
- saved_data[i] = ioapic_read_entry(ioapic_id, i);
-}
-
-static int ioapic_suspend(void)
-{
- int ioapic_id;
-
- for (ioapic_id = 0; ioapic_id < nr_ioapics; ioapic_id++)
- suspend_ioapic(ioapic_id);
-
- return 0;
-}
-
-static void resume_ioapic(int ioapic_id)
-{
- struct IO_APIC_route_entry *saved_data = ioapic_saved_data[ioapic_id];
unsigned long flags;
union IO_APIC_reg_00 reg_00;
- int i;
- if (!saved_data)
- return;
raw_spin_lock_irqsave(&ioapic_lock, flags);
reg_00.raw = io_apic_read(ioapic_id, 0);
- if (reg_00.bits.ID != mp_ioapics[ioapic_id].apicid) {
- reg_00.bits.ID = mp_ioapics[ioapic_id].apicid;
+ if (reg_00.bits.ID != mpc_ioapic_id(ioapic_id)) {
+ reg_00.bits.ID = mpc_ioapic_id(ioapic_id);
io_apic_write(ioapic_id, 0, reg_00.raw);
}
raw_spin_unlock_irqrestore(&ioapic_lock, flags);
- for (i = 0; i < nr_ioapic_registers[ioapic_id]; i++)
- ioapic_write_entry(ioapic_id, i, saved_data[i]);
}
static void ioapic_resume(void)
@@ -2968,28 +2923,18 @@
int ioapic_id;
for (ioapic_id = nr_ioapics - 1; ioapic_id >= 0; ioapic_id--)
- resume_ioapic(ioapic_id);
+ resume_ioapic_id(ioapic_id);
+
+ restore_ioapic_entries();
}
static struct syscore_ops ioapic_syscore_ops = {
- .suspend = ioapic_suspend,
+ .suspend = save_ioapic_entries,
.resume = ioapic_resume,
};
static int __init ioapic_init_ops(void)
{
- int i;
-
- for (i = 0; i < nr_ioapics; i++) {
- unsigned int size;
-
- size = nr_ioapic_registers[i]
- * sizeof(struct IO_APIC_route_entry);
- ioapic_saved_data[i] = kzalloc(size, GFP_KERNEL);
- if (!ioapic_saved_data[i])
- pr_err("IOAPIC %d: suspend/resume impossible!\n", i);
- }
-
register_syscore_ops(&ioapic_syscore_ops);
return 0;
@@ -3592,14 +3537,14 @@
int ret;
/* Avoid redundant programming */
- if (test_bit(pin, mp_ioapic_routing[id].pin_programmed)) {
+ if (test_bit(pin, ioapics[id].pin_programmed)) {
pr_debug("Pin %d-%d already programmed\n",
- mp_ioapics[id].apicid, pin);
+ mpc_ioapic_id(id), pin);
return 0;
}
ret = io_apic_setup_irq_pin(irq, node, attr);
if (!ret)
- set_bit(pin, mp_ioapic_routing[id].pin_programmed);
+ set_bit(pin, ioapics[id].pin_programmed);
return ret;
}
@@ -3764,8 +3709,7 @@
bitmap_zero(used, 256);
for (i = 0; i < nr_ioapics; i++) {
- struct mpc_ioapic *ia = &mp_ioapics[i];
- __set_bit(ia->apicid, used);
+ __set_bit(mpc_ioapic_id(i), used);
}
if (!test_bit(id, used))
return id;
@@ -3825,7 +3769,7 @@
return;
for (ioapic = 0; ioapic < nr_ioapics; ioapic++)
- for (pin = 0; pin < nr_ioapic_registers[ioapic]; pin++) {
+ for (pin = 0; pin < ioapics[ioapic].nr_registers; pin++) {
irq_entry = find_irq_entry(ioapic, pin, mp_INT);
if (irq_entry == -1)
continue;
@@ -3896,7 +3840,7 @@
ioapic_res = ioapic_setup_resources(nr_ioapics);
for (i = 0; i < nr_ioapics; i++) {
if (smp_found_config) {
- ioapic_phys = mp_ioapics[i].apicaddr;
+ ioapic_phys = mpc_ioapic_addr(i);
#ifdef CONFIG_X86_32
if (!ioapic_phys) {
printk(KERN_ERR
@@ -3956,8 +3900,9 @@
/* Find the IOAPIC that manages this GSI. */
for (i = 0; i < nr_ioapics; i++) {
- if ((gsi >= mp_gsi_routing[i].gsi_base)
- && (gsi <= mp_gsi_routing[i].gsi_end))
+ struct mp_ioapic_gsi *gsi_cfg = mp_ioapic_gsi_routing(i);
+ if ((gsi >= gsi_cfg->gsi_base)
+ && (gsi <= gsi_cfg->gsi_end))
return i;
}
@@ -3967,12 +3912,16 @@
int mp_find_ioapic_pin(int ioapic, u32 gsi)
{
+ struct mp_ioapic_gsi *gsi_cfg;
+
if (WARN_ON(ioapic == -1))
return -1;
- if (WARN_ON(gsi > mp_gsi_routing[ioapic].gsi_end))
+
+ gsi_cfg = mp_ioapic_gsi_routing(ioapic);
+ if (WARN_ON(gsi > gsi_cfg->gsi_end))
return -1;
- return gsi - mp_gsi_routing[ioapic].gsi_base;
+ return gsi - gsi_cfg->gsi_base;
}
static __init int bad_ioapic(unsigned long address)
@@ -3994,40 +3943,42 @@
{
int idx = 0;
int entries;
+ struct mp_ioapic_gsi *gsi_cfg;
if (bad_ioapic(address))
return;
idx = nr_ioapics;
- mp_ioapics[idx].type = MP_IOAPIC;
- mp_ioapics[idx].flags = MPC_APIC_USABLE;
- mp_ioapics[idx].apicaddr = address;
+ ioapics[idx].mp_config.type = MP_IOAPIC;
+ ioapics[idx].mp_config.flags = MPC_APIC_USABLE;
+ ioapics[idx].mp_config.apicaddr = address;
set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
- mp_ioapics[idx].apicid = io_apic_unique_id(id);
- mp_ioapics[idx].apicver = io_apic_get_version(idx);
+ ioapics[idx].mp_config.apicid = io_apic_unique_id(id);
+ ioapics[idx].mp_config.apicver = io_apic_get_version(idx);
/*
* Build basic GSI lookup table to facilitate gsi->io_apic lookups
* and to prevent reprogramming of IOAPIC pins (PCI GSIs).
*/
entries = io_apic_get_redir_entries(idx);
- mp_gsi_routing[idx].gsi_base = gsi_base;
- mp_gsi_routing[idx].gsi_end = gsi_base + entries - 1;
+ gsi_cfg = mp_ioapic_gsi_routing(idx);
+ gsi_cfg->gsi_base = gsi_base;
+ gsi_cfg->gsi_end = gsi_base + entries - 1;
/*
* The number of IO-APIC IRQ registers (== #pins):
*/
- nr_ioapic_registers[idx] = entries;
+ ioapics[idx].nr_registers = entries;
- if (mp_gsi_routing[idx].gsi_end >= gsi_top)
- gsi_top = mp_gsi_routing[idx].gsi_end + 1;
+ if (gsi_cfg->gsi_end >= gsi_top)
+ gsi_top = gsi_cfg->gsi_end + 1;
printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
- "GSI %d-%d\n", idx, mp_ioapics[idx].apicid,
- mp_ioapics[idx].apicver, mp_ioapics[idx].apicaddr,
- mp_gsi_routing[idx].gsi_base, mp_gsi_routing[idx].gsi_end);
+ "GSI %d-%d\n", idx, mpc_ioapic_id(idx),
+ mpc_ioapic_ver(idx), mpc_ioapic_addr(idx),
+ gsi_cfg->gsi_base, gsi_cfg->gsi_end);
nr_ioapics++;
}
diff --git a/arch/x86/kernel/apic/numaq_32.c b/arch/x86/kernel/apic/numaq_32.c
index 30f1331..c4a61ca 100644
--- a/arch/x86/kernel/apic/numaq_32.c
+++ b/arch/x86/kernel/apic/numaq_32.c
@@ -472,8 +472,8 @@
(u_long) xquad_portio, (u_long) num_quads*XQUAD_PORTIO_QUAD);
}
-/* Use __refdata to keep false positive warning calm. */
-struct apic __refdata apic_numaq = {
+/* Use __refdata to keep false positive warning calm. */
+static struct apic __refdata apic_numaq = {
.name = "NUMAQ",
.probe = probe_numaq,
@@ -537,3 +537,5 @@
.x86_32_early_logical_apicid = noop_x86_32_early_logical_apicid,
.x86_32_numa_cpu_node = numaq_numa_cpu_node,
};
+
+apic_driver(apic_numaq);
diff --git a/arch/x86/kernel/apic/probe_32.c b/arch/x86/kernel/apic/probe_32.c
index 6541e47..b5254ad 100644
--- a/arch/x86/kernel/apic/probe_32.c
+++ b/arch/x86/kernel/apic/probe_32.c
@@ -52,31 +52,6 @@
}
late_initcall(print_ipi_mode);
-void __init default_setup_apic_routing(void)
-{
- int version = apic_version[boot_cpu_physical_apicid];
-
- if (num_possible_cpus() > 8) {
- switch (boot_cpu_data.x86_vendor) {
- case X86_VENDOR_INTEL:
- if (!APIC_XAPIC(version)) {
- def_to_bigsmp = 0;
- break;
- }
- /* If P4 and above fall through */
- case X86_VENDOR_AMD:
- def_to_bigsmp = 1;
- }
- }
-
-#ifdef CONFIG_X86_BIGSMP
- generic_bigsmp_probe();
-#endif
-
- if (apic->setup_apic_routing)
- apic->setup_apic_routing();
-}
-
static int default_x86_32_early_logical_apicid(int cpu)
{
return 1 << cpu;
@@ -112,7 +87,7 @@
return 1;
}
-struct apic apic_default = {
+static struct apic apic_default = {
.name = "default",
.probe = probe_default,
@@ -174,44 +149,22 @@
.x86_32_early_logical_apicid = default_x86_32_early_logical_apicid,
};
-extern struct apic apic_numaq;
-extern struct apic apic_summit;
-extern struct apic apic_bigsmp;
-extern struct apic apic_es7000;
-extern struct apic apic_es7000_cluster;
+apic_driver(apic_default);
struct apic *apic = &apic_default;
EXPORT_SYMBOL_GPL(apic);
-static struct apic *apic_probe[] __initdata = {
-#ifdef CONFIG_X86_NUMAQ
- &apic_numaq,
-#endif
-#ifdef CONFIG_X86_SUMMIT
- &apic_summit,
-#endif
-#ifdef CONFIG_X86_BIGSMP
- &apic_bigsmp,
-#endif
-#ifdef CONFIG_X86_ES7000
- &apic_es7000,
- &apic_es7000_cluster,
-#endif
- &apic_default, /* must be last */
- NULL,
-};
-
static int cmdline_apic __initdata;
static int __init parse_apic(char *arg)
{
- int i;
+ struct apic **drv;
if (!arg)
return -EINVAL;
- for (i = 0; apic_probe[i]; i++) {
- if (!strcmp(apic_probe[i]->name, arg)) {
- apic = apic_probe[i];
+ for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) {
+ if (!strcmp((*drv)->name, arg)) {
+ apic = *drv;
cmdline_apic = 1;
return 0;
}
@@ -222,38 +175,58 @@
}
early_param("apic", parse_apic);
-void __init generic_bigsmp_probe(void)
+void __init default_setup_apic_routing(void)
{
+ int version = apic_version[boot_cpu_physical_apicid];
+
+ if (num_possible_cpus() > 8) {
+ switch (boot_cpu_data.x86_vendor) {
+ case X86_VENDOR_INTEL:
+ if (!APIC_XAPIC(version)) {
+ def_to_bigsmp = 0;
+ break;
+ }
+ /* If P4 and above fall through */
+ case X86_VENDOR_AMD:
+ def_to_bigsmp = 1;
+ }
+ }
+
#ifdef CONFIG_X86_BIGSMP
/*
- * This routine is used to switch to bigsmp mode when
+ * This is used to switch to bigsmp mode when
* - There is no apic= option specified by the user
* - generic_apic_probe() has chosen apic_default as the sub_arch
* - we find more than 8 CPUs in acpi LAPIC listing with xAPIC support
*/
if (!cmdline_apic && apic == &apic_default) {
- if (apic_bigsmp.probe()) {
- apic = &apic_bigsmp;
+ struct apic *bigsmp = generic_bigsmp_probe();
+ if (bigsmp) {
+ apic = bigsmp;
printk(KERN_INFO "Overriding APIC driver with %s\n",
apic->name);
}
}
#endif
+
+ if (apic->setup_apic_routing)
+ apic->setup_apic_routing();
}
void __init generic_apic_probe(void)
{
if (!cmdline_apic) {
- int i;
- for (i = 0; apic_probe[i]; i++) {
- if (apic_probe[i]->probe()) {
- apic = apic_probe[i];
+ struct apic **drv;
+
+ for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) {
+ if ((*drv)->probe()) {
+ apic = *drv;
break;
}
}
/* Not visible without early console */
- if (!apic_probe[i])
+ if (drv == __apicdrivers_end)
panic("Didn't find an APIC driver");
}
printk(KERN_INFO "Using APIC driver %s\n", apic->name);
@@ -264,16 +237,16 @@
int __init
generic_mps_oem_check(struct mpc_table *mpc, char *oem, char *productid)
{
- int i;
+ struct apic **drv;
- for (i = 0; apic_probe[i]; ++i) {
- if (!apic_probe[i]->mps_oem_check)
+ for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) {
+ if (!((*drv)->mps_oem_check))
continue;
- if (!apic_probe[i]->mps_oem_check(mpc, oem, productid))
+ if (!(*drv)->mps_oem_check(mpc, oem, productid))
continue;
if (!cmdline_apic) {
- apic = apic_probe[i];
+ apic = *drv;
printk(KERN_INFO "Switched to APIC driver `%s'.\n",
apic->name);
}
@@ -284,16 +257,16 @@
int __init default_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
{
- int i;
+ struct apic **drv;
- for (i = 0; apic_probe[i]; ++i) {
- if (!apic_probe[i]->acpi_madt_oem_check)
+ for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) {
+ if (!(*drv)->acpi_madt_oem_check)
continue;
- if (!apic_probe[i]->acpi_madt_oem_check(oem_id, oem_table_id))
+ if (!(*drv)->acpi_madt_oem_check(oem_id, oem_table_id))
continue;
if (!cmdline_apic) {
- apic = apic_probe[i];
+ apic = *drv;
printk(KERN_INFO "Switched to APIC driver `%s'.\n",
apic->name);
}
diff --git a/arch/x86/kernel/apic/probe_64.c b/arch/x86/kernel/apic/probe_64.c
index d8c4a6f..3fe9866 100644
--- a/arch/x86/kernel/apic/probe_64.c
+++ b/arch/x86/kernel/apic/probe_64.c
@@ -23,27 +23,6 @@
#include <asm/ipi.h>
#include <asm/setup.h>
-extern struct apic apic_flat;
-extern struct apic apic_physflat;
-extern struct apic apic_x2xpic_uv_x;
-extern struct apic apic_x2apic_phys;
-extern struct apic apic_x2apic_cluster;
-
-struct apic __read_mostly *apic = &apic_flat;
-EXPORT_SYMBOL_GPL(apic);
-
-static struct apic *apic_probe[] __initdata = {
-#ifdef CONFIG_X86_UV
- &apic_x2apic_uv_x,
-#endif
-#ifdef CONFIG_X86_X2APIC
- &apic_x2apic_phys,
- &apic_x2apic_cluster,
-#endif
- &apic_physflat,
- NULL,
-};
-
static int apicid_phys_pkg_id(int initial_apic_id, int index_msb)
{
return hard_smp_processor_id() >> index_msb;
@@ -54,26 +33,20 @@
*/
void __init default_setup_apic_routing(void)
{
+ struct apic **drv;
enable_IR_x2apic();
-#ifdef CONFIG_X86_X2APIC
- if (x2apic_mode
-#ifdef CONFIG_X86_UV
- && apic != &apic_x2apic_uv_x
-#endif
- ) {
- if (x2apic_phys)
- apic = &apic_x2apic_phys;
- else
- apic = &apic_x2apic_cluster;
+ for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) {
+ if ((*drv)->probe && (*drv)->probe()) {
+ if (apic != *drv) {
+ apic = *drv;
+ pr_info("Switched APIC routing to %s.\n",
+ apic->name);
+ }
+ break;
+ }
}
-#endif
-
- if (apic == &apic_flat && num_possible_cpus() > 8)
- apic = &apic_physflat;
-
- printk(KERN_INFO "Setting APIC routing to %s\n", apic->name);
if (is_vsmp_box()) {
/* need to update phys_pkg_id */
@@ -90,13 +63,15 @@
int __init default_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
{
- int i;
+ struct apic **drv;
- for (i = 0; apic_probe[i]; ++i) {
- if (apic_probe[i]->acpi_madt_oem_check(oem_id, oem_table_id)) {
- apic = apic_probe[i];
- printk(KERN_INFO "Setting APIC routing to %s.\n",
- apic->name);
+ for (drv = __apicdrivers; drv < __apicdrivers_end; drv++) {
+ if ((*drv)->acpi_madt_oem_check(oem_id, oem_table_id)) {
+ if (apic != *drv) {
+ apic = *drv;
+ pr_info("Setting APIC routing to %s.\n",
+ apic->name);
+ }
return 1;
}
}
diff --git a/arch/x86/kernel/apic/summit_32.c b/arch/x86/kernel/apic/summit_32.c
index 35bcd7d..1911442 100644
--- a/arch/x86/kernel/apic/summit_32.c
+++ b/arch/x86/kernel/apic/summit_32.c
@@ -491,7 +491,7 @@
}
#endif
-struct apic apic_summit = {
+static struct apic apic_summit = {
.name = "summit",
.probe = probe_summit,
@@ -552,3 +552,5 @@
.x86_32_early_logical_apicid = summit_early_logical_apicid,
};
+
+apic_driver(apic_summit);
diff --git a/arch/x86/kernel/apic/x2apic_cluster.c b/arch/x86/kernel/apic/x2apic_cluster.c
index 90949bb..5007958 100644
--- a/arch/x86/kernel/apic/x2apic_cluster.c
+++ b/arch/x86/kernel/apic/x2apic_cluster.c
@@ -5,118 +5,95 @@
#include <linux/ctype.h>
#include <linux/init.h>
#include <linux/dmar.h>
+#include <linux/cpu.h>
#include <asm/smp.h>
-#include <asm/apic.h>
-#include <asm/ipi.h>
+#include <asm/x2apic.h>
static DEFINE_PER_CPU(u32, x86_cpu_to_logical_apicid);
+static DEFINE_PER_CPU(cpumask_var_t, cpus_in_cluster);
+static DEFINE_PER_CPU(cpumask_var_t, ipi_mask);
static int x2apic_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
{
return x2apic_enabled();
}
-/*
- * need to use more than cpu 0, because we need more vectors when
- * MSI-X are used.
- */
-static const struct cpumask *x2apic_target_cpus(void)
+static inline u32 x2apic_cluster(int cpu)
{
- return cpu_online_mask;
-}
-
-/*
- * for now each logical cpu is in its own vector allocation domain.
- */
-static void x2apic_vector_allocation_domain(int cpu, struct cpumask *retmask)
-{
- cpumask_clear(retmask);
- cpumask_set_cpu(cpu, retmask);
+ return per_cpu(x86_cpu_to_logical_apicid, cpu) >> 16;
}
static void
- __x2apic_send_IPI_dest(unsigned int apicid, int vector, unsigned int dest)
+__x2apic_send_IPI_mask(const struct cpumask *mask, int vector, int apic_dest)
{
- unsigned long cfg;
-
- cfg = __prepare_ICR(0, vector, dest);
-
- /*
- * send the IPI.
- */
- native_x2apic_icr_write(cfg, apicid);
-}
-
-/*
- * for now, we send the IPI's one by one in the cpumask.
- * TBD: Based on the cpu mask, we can send the IPI's to the cluster group
- * at once. We have 16 cpu's in a cluster. This will minimize IPI register
- * writes.
- */
-static void x2apic_send_IPI_mask(const struct cpumask *mask, int vector)
-{
- unsigned long query_cpu;
+ struct cpumask *cpus_in_cluster_ptr;
+ struct cpumask *ipi_mask_ptr;
+ unsigned int cpu, this_cpu;
unsigned long flags;
+ u32 dest;
x2apic_wrmsr_fence();
local_irq_save(flags);
- for_each_cpu(query_cpu, mask) {
- __x2apic_send_IPI_dest(
- per_cpu(x86_cpu_to_logical_apicid, query_cpu),
- vector, apic->dest_logical);
+
+ this_cpu = smp_processor_id();
+
+ /*
+ * We are to modify mask, so we need an own copy
+ * and be sure it's manipulated with irq off.
+ */
+ ipi_mask_ptr = __raw_get_cpu_var(ipi_mask);
+ cpumask_copy(ipi_mask_ptr, mask);
+
+ /*
+ * The idea is to send one IPI per cluster.
+ */
+ for_each_cpu(cpu, ipi_mask_ptr) {
+ unsigned long i;
+
+ cpus_in_cluster_ptr = per_cpu(cpus_in_cluster, cpu);
+ dest = 0;
+
+ /* Collect cpus in cluster. */
+ for_each_cpu_and(i, ipi_mask_ptr, cpus_in_cluster_ptr) {
+ if (apic_dest == APIC_DEST_ALLINC || i != this_cpu)
+ dest |= per_cpu(x86_cpu_to_logical_apicid, i);
+ }
+
+ if (!dest)
+ continue;
+
+ __x2apic_send_IPI_dest(dest, vector, apic->dest_logical);
+ /*
+ * Cluster sibling cpus should be discared now so
+ * we would not send IPI them second time.
+ */
+ cpumask_andnot(ipi_mask_ptr, ipi_mask_ptr, cpus_in_cluster_ptr);
}
+
local_irq_restore(flags);
}
+static void x2apic_send_IPI_mask(const struct cpumask *mask, int vector)
+{
+ __x2apic_send_IPI_mask(mask, vector, APIC_DEST_ALLINC);
+}
+
static void
x2apic_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
{
- unsigned long this_cpu = smp_processor_id();
- unsigned long query_cpu;
- unsigned long flags;
-
- x2apic_wrmsr_fence();
-
- local_irq_save(flags);
- for_each_cpu(query_cpu, mask) {
- if (query_cpu == this_cpu)
- continue;
- __x2apic_send_IPI_dest(
- per_cpu(x86_cpu_to_logical_apicid, query_cpu),
- vector, apic->dest_logical);
- }
- local_irq_restore(flags);
+ __x2apic_send_IPI_mask(mask, vector, APIC_DEST_ALLBUT);
}
static void x2apic_send_IPI_allbutself(int vector)
{
- unsigned long this_cpu = smp_processor_id();
- unsigned long query_cpu;
- unsigned long flags;
-
- x2apic_wrmsr_fence();
-
- local_irq_save(flags);
- for_each_online_cpu(query_cpu) {
- if (query_cpu == this_cpu)
- continue;
- __x2apic_send_IPI_dest(
- per_cpu(x86_cpu_to_logical_apicid, query_cpu),
- vector, apic->dest_logical);
- }
- local_irq_restore(flags);
+ __x2apic_send_IPI_mask(cpu_online_mask, vector, APIC_DEST_ALLBUT);
}
static void x2apic_send_IPI_all(int vector)
{
- x2apic_send_IPI_mask(cpu_online_mask, vector);
-}
-
-static int x2apic_apic_id_registered(void)
-{
- return 1;
+ __x2apic_send_IPI_mask(cpu_online_mask, vector, APIC_DEST_ALLINC);
}
static unsigned int x2apic_cpu_mask_to_apicid(const struct cpumask *cpumask)
@@ -151,43 +128,90 @@
return per_cpu(x86_cpu_to_logical_apicid, cpu);
}
-static unsigned int x2apic_cluster_phys_get_apic_id(unsigned long x)
-{
- unsigned int id;
-
- id = x;
- return id;
-}
-
-static unsigned long set_apic_id(unsigned int id)
-{
- unsigned long x;
-
- x = id;
- return x;
-}
-
-static int x2apic_cluster_phys_pkg_id(int initial_apicid, int index_msb)
-{
- return initial_apicid >> index_msb;
-}
-
-static void x2apic_send_IPI_self(int vector)
-{
- apic_write(APIC_SELF_IPI, vector);
-}
-
static void init_x2apic_ldr(void)
{
+ unsigned int this_cpu = smp_processor_id();
+ unsigned int cpu;
+
+ per_cpu(x86_cpu_to_logical_apicid, this_cpu) = apic_read(APIC_LDR);
+
+ __cpu_set(this_cpu, per_cpu(cpus_in_cluster, this_cpu));
+ for_each_online_cpu(cpu) {
+ if (x2apic_cluster(this_cpu) != x2apic_cluster(cpu))
+ continue;
+ __cpu_set(this_cpu, per_cpu(cpus_in_cluster, cpu));
+ __cpu_set(cpu, per_cpu(cpus_in_cluster, this_cpu));
+ }
+}
+
+ /*
+ * At CPU state changes, update the x2apic cluster sibling info.
+ */
+static int __cpuinit
+update_clusterinfo(struct notifier_block *nfb, unsigned long action, void *hcpu)
+{
+ unsigned int this_cpu = (unsigned long)hcpu;
+ unsigned int cpu;
+ int err = 0;
+
+ switch (action) {
+ case CPU_UP_PREPARE:
+ if (!zalloc_cpumask_var(&per_cpu(cpus_in_cluster, this_cpu),
+ GFP_KERNEL)) {
+ err = -ENOMEM;
+ } else if (!zalloc_cpumask_var(&per_cpu(ipi_mask, this_cpu),
+ GFP_KERNEL)) {
+ free_cpumask_var(per_cpu(cpus_in_cluster, this_cpu));
+ err = -ENOMEM;
+ }
+ break;
+ case CPU_UP_CANCELED:
+ case CPU_UP_CANCELED_FROZEN:
+ case CPU_DEAD:
+ for_each_online_cpu(cpu) {
+ if (x2apic_cluster(this_cpu) != x2apic_cluster(cpu))
+ continue;
+ __cpu_clear(this_cpu, per_cpu(cpus_in_cluster, cpu));
+ __cpu_clear(cpu, per_cpu(cpus_in_cluster, this_cpu));
+ }
+ free_cpumask_var(per_cpu(cpus_in_cluster, this_cpu));
+ free_cpumask_var(per_cpu(ipi_mask, this_cpu));
+ break;
+ }
+
+ return notifier_from_errno(err);
+}
+
+static struct notifier_block __refdata x2apic_cpu_notifier = {
+ .notifier_call = update_clusterinfo,
+};
+
+static int x2apic_init_cpu_notifier(void)
+{
int cpu = smp_processor_id();
- per_cpu(x86_cpu_to_logical_apicid, cpu) = apic_read(APIC_LDR);
+ zalloc_cpumask_var(&per_cpu(cpus_in_cluster, cpu), GFP_KERNEL);
+ zalloc_cpumask_var(&per_cpu(ipi_mask, cpu), GFP_KERNEL);
+
+ BUG_ON(!per_cpu(cpus_in_cluster, cpu) || !per_cpu(ipi_mask, cpu));
+
+ __cpu_set(cpu, per_cpu(cpus_in_cluster, cpu));
+ register_hotcpu_notifier(&x2apic_cpu_notifier);
+ return 1;
}
-struct apic apic_x2apic_cluster = {
+static int x2apic_cluster_probe(void)
+{
+ if (x2apic_mode)
+ return x2apic_init_cpu_notifier();
+ else
+ return 0;
+}
+
+static struct apic apic_x2apic_cluster = {
.name = "cluster x2apic",
- .probe = NULL,
+ .probe = x2apic_cluster_probe,
.acpi_madt_oem_check = x2apic_acpi_madt_oem_check,
.apic_id_registered = x2apic_apic_id_registered,
@@ -211,11 +235,11 @@
.setup_portio_remap = NULL,
.check_phys_apicid_present = default_check_phys_apicid_present,
.enable_apic_mode = NULL,
- .phys_pkg_id = x2apic_cluster_phys_pkg_id,
+ .phys_pkg_id = x2apic_phys_pkg_id,
.mps_oem_check = NULL,
- .get_apic_id = x2apic_cluster_phys_get_apic_id,
- .set_apic_id = set_apic_id,
+ .get_apic_id = x2apic_get_apic_id,
+ .set_apic_id = x2apic_set_apic_id,
.apic_id_mask = 0xFFFFFFFFu,
.cpu_mask_to_apicid = x2apic_cpu_mask_to_apicid,
@@ -240,3 +264,5 @@
.wait_icr_idle = native_x2apic_wait_icr_idle,
.safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle,
};
+
+apic_driver(apic_x2apic_cluster);
diff --git a/arch/x86/kernel/apic/x2apic_phys.c b/arch/x86/kernel/apic/x2apic_phys.c
index c7e6d66..f5373df 100644
--- a/arch/x86/kernel/apic/x2apic_phys.c
+++ b/arch/x86/kernel/apic/x2apic_phys.c
@@ -7,11 +7,12 @@
#include <linux/dmar.h>
#include <asm/smp.h>
-#include <asm/apic.h>
-#include <asm/ipi.h>
+#include <asm/x2apic.h>
int x2apic_phys;
+static struct apic apic_x2apic_phys;
+
static int set_x2apic_phys_mode(char *arg)
{
x2apic_phys = 1;
@@ -27,79 +28,20 @@
return 0;
}
-/*
- * need to use more than cpu 0, because we need more vectors when
- * MSI-X are used.
- */
-static const struct cpumask *x2apic_target_cpus(void)
-{
- return cpu_online_mask;
-}
-
-static void x2apic_vector_allocation_domain(int cpu, struct cpumask *retmask)
-{
- cpumask_clear(retmask);
- cpumask_set_cpu(cpu, retmask);
-}
-
-static void __x2apic_send_IPI_dest(unsigned int apicid, int vector,
- unsigned int dest)
-{
- unsigned long cfg;
-
- cfg = __prepare_ICR(0, vector, dest);
-
- /*
- * send the IPI.
- */
- native_x2apic_icr_write(cfg, apicid);
-}
-
-static void x2apic_send_IPI_mask(const struct cpumask *mask, int vector)
-{
- unsigned long query_cpu;
- unsigned long flags;
-
- x2apic_wrmsr_fence();
-
- local_irq_save(flags);
- for_each_cpu(query_cpu, mask) {
- __x2apic_send_IPI_dest(per_cpu(x86_cpu_to_apicid, query_cpu),
- vector, APIC_DEST_PHYSICAL);
- }
- local_irq_restore(flags);
-}
-
static void
- x2apic_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
+__x2apic_send_IPI_mask(const struct cpumask *mask, int vector, int apic_dest)
{
- unsigned long this_cpu = smp_processor_id();
unsigned long query_cpu;
+ unsigned long this_cpu;
unsigned long flags;
x2apic_wrmsr_fence();
local_irq_save(flags);
+
+ this_cpu = smp_processor_id();
for_each_cpu(query_cpu, mask) {
- if (query_cpu != this_cpu)
- __x2apic_send_IPI_dest(
- per_cpu(x86_cpu_to_apicid, query_cpu),
- vector, APIC_DEST_PHYSICAL);
- }
- local_irq_restore(flags);
-}
-
-static void x2apic_send_IPI_allbutself(int vector)
-{
- unsigned long this_cpu = smp_processor_id();
- unsigned long query_cpu;
- unsigned long flags;
-
- x2apic_wrmsr_fence();
-
- local_irq_save(flags);
- for_each_online_cpu(query_cpu) {
- if (query_cpu == this_cpu)
+ if (apic_dest == APIC_DEST_ALLBUT && this_cpu == query_cpu)
continue;
__x2apic_send_IPI_dest(per_cpu(x86_cpu_to_apicid, query_cpu),
vector, APIC_DEST_PHYSICAL);
@@ -107,14 +49,25 @@
local_irq_restore(flags);
}
-static void x2apic_send_IPI_all(int vector)
+static void x2apic_send_IPI_mask(const struct cpumask *mask, int vector)
{
- x2apic_send_IPI_mask(cpu_online_mask, vector);
+ __x2apic_send_IPI_mask(mask, vector, APIC_DEST_ALLINC);
}
-static int x2apic_apic_id_registered(void)
+static void
+ x2apic_send_IPI_mask_allbutself(const struct cpumask *mask, int vector)
{
- return 1;
+ __x2apic_send_IPI_mask(mask, vector, APIC_DEST_ALLBUT);
+}
+
+static void x2apic_send_IPI_allbutself(int vector)
+{
+ __x2apic_send_IPI_mask(cpu_online_mask, vector, APIC_DEST_ALLBUT);
+}
+
+static void x2apic_send_IPI_all(int vector)
+{
+ __x2apic_send_IPI_mask(cpu_online_mask, vector, APIC_DEST_ALLINC);
}
static unsigned int x2apic_cpu_mask_to_apicid(const struct cpumask *cpumask)
@@ -149,34 +102,22 @@
return per_cpu(x86_cpu_to_apicid, cpu);
}
-static unsigned int x2apic_phys_get_apic_id(unsigned long x)
-{
- return x;
-}
-
-static unsigned long set_apic_id(unsigned int id)
-{
- return id;
-}
-
-static int x2apic_phys_pkg_id(int initial_apicid, int index_msb)
-{
- return initial_apicid >> index_msb;
-}
-
-static void x2apic_send_IPI_self(int vector)
-{
- apic_write(APIC_SELF_IPI, vector);
-}
-
static void init_x2apic_ldr(void)
{
}
-struct apic apic_x2apic_phys = {
+static int x2apic_phys_probe(void)
+{
+ if (x2apic_mode && x2apic_phys)
+ return 1;
+
+ return apic == &apic_x2apic_phys;
+}
+
+static struct apic apic_x2apic_phys = {
.name = "physical x2apic",
- .probe = NULL,
+ .probe = x2apic_phys_probe,
.acpi_madt_oem_check = x2apic_acpi_madt_oem_check,
.apic_id_registered = x2apic_apic_id_registered,
@@ -203,8 +144,8 @@
.phys_pkg_id = x2apic_phys_pkg_id,
.mps_oem_check = NULL,
- .get_apic_id = x2apic_phys_get_apic_id,
- .set_apic_id = set_apic_id,
+ .get_apic_id = x2apic_get_apic_id,
+ .set_apic_id = x2apic_set_apic_id,
.apic_id_mask = 0xFFFFFFFFu,
.cpu_mask_to_apicid = x2apic_cpu_mask_to_apicid,
@@ -229,3 +170,5 @@
.wait_icr_idle = native_x2apic_wait_icr_idle,
.safe_wait_icr_idle = native_safe_x2apic_wait_icr_idle,
};
+
+apic_driver(apic_x2apic_phys);
diff --git a/arch/x86/kernel/apic/x2apic_uv_x.c b/arch/x86/kernel/apic/x2apic_uv_x.c
index 7acd2d2..f450b68 100644
--- a/arch/x86/kernel/apic/x2apic_uv_x.c
+++ b/arch/x86/kernel/apic/x2apic_uv_x.c
@@ -58,6 +58,8 @@
EXPORT_SYMBOL_GPL(uv_apicid_hibits);
static DEFINE_SPINLOCK(uv_nmi_lock);
+static struct apic apic_x2apic_uv_x;
+
static unsigned long __init uv_early_read_mmr(unsigned long addr)
{
unsigned long val, *mmr;
@@ -326,10 +328,15 @@
apic_write(APIC_SELF_IPI, vector);
}
-struct apic __refdata apic_x2apic_uv_x = {
+static int uv_probe(void)
+{
+ return apic == &apic_x2apic_uv_x;
+}
+
+static struct apic __refdata apic_x2apic_uv_x = {
.name = "UV large system",
- .probe = NULL,
+ .probe = uv_probe,
.acpi_madt_oem_check = uv_acpi_madt_oem_check,
.apic_id_registered = uv_apic_id_registered,
@@ -859,3 +866,5 @@
if (is_kdump_kernel())
reboot_type = BOOT_ACPI;
}
+
+apic_driver(apic_x2apic_uv_x);
diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c
index e90f084..690bc84 100644
--- a/arch/x86/kernel/devicetree.c
+++ b/arch/x86/kernel/devicetree.c
@@ -369,6 +369,7 @@
static int ioapic_xlate(struct irq_domain *id, const u32 *intspec, u32 intsize,
u32 *out_hwirq, u32 *out_type)
{
+ struct mp_ioapic_gsi *gsi_cfg;
struct io_apic_irq_attr attr;
struct of_ioapic_type *it;
u32 line, idx, type;
@@ -378,7 +379,8 @@
line = *intspec;
idx = (u32) id->priv;
- *out_hwirq = line + mp_gsi_routing[idx].gsi_base;
+ gsi_cfg = mp_ioapic_gsi_routing(idx);
+ *out_hwirq = line + gsi_cfg->gsi_base;
intspec++;
type = *intspec;
@@ -407,7 +409,7 @@
}
for (i = 0; i < nr_ioapics; i++) {
- if (r.start == mp_ioapics[i].apicaddr) {
+ if (r.start == mpc_ioapic_addr(i)) {
struct irq_domain *id;
id = kzalloc(sizeof(*id), GFP_KERNEL);
diff --git a/arch/x86/kernel/mpparse.c b/arch/x86/kernel/mpparse.c
index 6f9bfff..9103b89 100644
--- a/arch/x86/kernel/mpparse.c
+++ b/arch/x86/kernel/mpparse.c
@@ -285,7 +285,7 @@
intsrc.type = MP_INTSRC;
intsrc.irqflag = 0; /* conforming */
intsrc.srcbus = 0;
- intsrc.dstapic = mp_ioapics[0].apicid;
+ intsrc.dstapic = mpc_ioapic_id(0);
intsrc.irqtype = mp_INT;
diff --git a/arch/x86/kernel/pci-dma.c b/arch/x86/kernel/pci-dma.c
index 9ea999a..b49d00d 100644
--- a/arch/x86/kernel/pci-dma.c
+++ b/arch/x86/kernel/pci-dma.c
@@ -68,74 +68,10 @@
}
EXPORT_SYMBOL(dma_set_mask);
-#if defined(CONFIG_X86_64) && !defined(CONFIG_NUMA)
-static __initdata void *dma32_bootmem_ptr;
-static unsigned long dma32_bootmem_size __initdata = (128ULL<<20);
-
-static int __init parse_dma32_size_opt(char *p)
-{
- if (!p)
- return -EINVAL;
- dma32_bootmem_size = memparse(p, &p);
- return 0;
-}
-early_param("dma32_size", parse_dma32_size_opt);
-
-void __init dma32_reserve_bootmem(void)
-{
- unsigned long size, align;
- if (max_pfn <= MAX_DMA32_PFN)
- return;
-
- /*
- * check aperture_64.c allocate_aperture() for reason about
- * using 512M as goal
- */
- align = 64ULL<<20;
- size = roundup(dma32_bootmem_size, align);
- dma32_bootmem_ptr = __alloc_bootmem_nopanic(size, align,
- 512ULL<<20);
- /*
- * Kmemleak should not scan this block as it may not be mapped via the
- * kernel direct mapping.
- */
- kmemleak_ignore(dma32_bootmem_ptr);
- if (dma32_bootmem_ptr)
- dma32_bootmem_size = size;
- else
- dma32_bootmem_size = 0;
-}
-static void __init dma32_free_bootmem(void)
-{
-
- if (max_pfn <= MAX_DMA32_PFN)
- return;
-
- if (!dma32_bootmem_ptr)
- return;
-
- free_bootmem(__pa(dma32_bootmem_ptr), dma32_bootmem_size);
-
- dma32_bootmem_ptr = NULL;
- dma32_bootmem_size = 0;
-}
-#else
-void __init dma32_reserve_bootmem(void)
-{
-}
-static void __init dma32_free_bootmem(void)
-{
-}
-
-#endif
-
void __init pci_iommu_alloc(void)
{
struct iommu_table_entry *p;
- /* free the range so iommu could get some range less than 4G */
- dma32_free_bootmem();
-
sort_iommu_table(__iommu_table, __iommu_table_end);
check_iommu_entries(__iommu_table, __iommu_table_end);
diff --git a/arch/x86/kernel/ptrace.c b/arch/x86/kernel/ptrace.c
index f65e5b5..807c2a2 100644
--- a/arch/x86/kernel/ptrace.c
+++ b/arch/x86/kernel/ptrace.c
@@ -1363,7 +1363,7 @@
* We must return the syscall number to actually look up in the table.
* This can be -1L to skip running any syscall at all.
*/
-asmregparm long syscall_trace_enter(struct pt_regs *regs)
+long syscall_trace_enter(struct pt_regs *regs)
{
long ret = 0;
@@ -1408,7 +1408,7 @@
return ret ?: regs->orig_ax;
}
-asmregparm void syscall_trace_leave(struct pt_regs *regs)
+void syscall_trace_leave(struct pt_regs *regs)
{
bool step;
diff --git a/arch/x86/kernel/setup.c b/arch/x86/kernel/setup.c
index c3050af..a3e5948 100644
--- a/arch/x86/kernel/setup.c
+++ b/arch/x86/kernel/setup.c
@@ -946,6 +946,8 @@
if (init_ohci1394_dma_early)
init_ohci1394_dma_on_all_controllers();
#endif
+ /* Allocate bigger log buffer */
+ setup_log_buf(1);
reserve_initrd();
@@ -964,7 +966,6 @@
initmem_init();
memblock_find_dma_reserve();
- dma32_reserve_bootmem();
#ifdef CONFIG_KVM_CLOCK
kvmclock_init();
diff --git a/arch/x86/kernel/tboot.c b/arch/x86/kernel/tboot.c
index 998e972..30ac65d 100644
--- a/arch/x86/kernel/tboot.c
+++ b/arch/x86/kernel/tboot.c
@@ -110,7 +110,6 @@
.mmap_sem = __RWSEM_INITIALIZER(init_mm.mmap_sem),
.page_table_lock = __SPIN_LOCK_UNLOCKED(init_mm.page_table_lock),
.mmlist = LIST_HEAD_INIT(init_mm.mmlist),
- .cpu_vm_mask = CPU_MASK_ALL,
};
static inline void switch_to_tboot_pt(void)
diff --git a/arch/x86/kernel/vmlinux.lds.S b/arch/x86/kernel/vmlinux.lds.S
index 624a201..61682f0 100644
--- a/arch/x86/kernel/vmlinux.lds.S
+++ b/arch/x86/kernel/vmlinux.lds.S
@@ -306,6 +306,13 @@
}
. = ALIGN(8);
+ .apicdrivers : AT(ADDR(.apicdrivers) - LOAD_OFFSET) {
+ __apicdrivers = .;
+ *(.apicdrivers);
+ __apicdrivers_end = .;
+ }
+
+ . = ALIGN(8);
/*
* .exit.text is discard at runtime, not link time, to deal with
* references from .altinstructions and .eh_frame
@@ -319,7 +326,7 @@
}
#if !defined(CONFIG_X86_64) || !defined(CONFIG_SMP)
- PERCPU(INTERNODE_CACHE_BYTES, PAGE_SIZE)
+ PERCPU_SECTION(INTERNODE_CACHE_BYTES)
#endif
. = ALIGN(PAGE_SIZE);
diff --git a/arch/x86/kvm/mmu.c b/arch/x86/kvm/mmu.c
index 2841805..bd14bb4 100644
--- a/arch/x86/kvm/mmu.c
+++ b/arch/x86/kvm/mmu.c
@@ -3545,10 +3545,11 @@
return kvm_mmu_prepare_zap_page(kvm, page, invalid_list);
}
-static int mmu_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask)
+static int mmu_shrink(struct shrinker *shrink, struct shrink_control *sc)
{
struct kvm *kvm;
struct kvm *kvm_freed = NULL;
+ int nr_to_scan = sc->nr_to_scan;
if (nr_to_scan == 0)
goto out;
diff --git a/arch/x86/mm/fault.c b/arch/x86/mm/fault.c
index bcb394d..f7a2a05 100644
--- a/arch/x86/mm/fault.c
+++ b/arch/x86/mm/fault.c
@@ -965,7 +965,7 @@
struct mm_struct *mm;
int fault;
int write = error_code & PF_WRITE;
- unsigned int flags = FAULT_FLAG_ALLOW_RETRY |
+ unsigned int flags = FAULT_FLAG_ALLOW_RETRY | FAULT_FLAG_KILLABLE |
(write ? FAULT_FLAG_WRITE : 0);
tsk = current;
@@ -1139,6 +1139,16 @@
}
/*
+ * Pagefault was interrupted by SIGKILL. We have no reason to
+ * continue pagefault.
+ */
+ if ((fault & VM_FAULT_RETRY) && fatal_signal_pending(current)) {
+ if (!(error_code & PF_USER))
+ no_context(regs, error_code, address);
+ return;
+ }
+
+ /*
* Major/minor page fault accounting is only done on the
* initial attempt. If we go through a retry, it is extremely
* likely that the page will be found in page cache at that point.
diff --git a/arch/x86/mm/hugetlbpage.c b/arch/x86/mm/hugetlbpage.c
index d420398..f581a18 100644
--- a/arch/x86/mm/hugetlbpage.c
+++ b/arch/x86/mm/hugetlbpage.c
@@ -72,7 +72,7 @@
if (!vma_shareable(vma, addr))
return;
- spin_lock(&mapping->i_mmap_lock);
+ mutex_lock(&mapping->i_mmap_mutex);
vma_prio_tree_foreach(svma, &iter, &mapping->i_mmap, idx, idx) {
if (svma == vma)
continue;
@@ -97,7 +97,7 @@
put_page(virt_to_page(spte));
spin_unlock(&mm->page_table_lock);
out:
- spin_unlock(&mapping->i_mmap_lock);
+ mutex_unlock(&mapping->i_mmap_mutex);
}
/*
diff --git a/arch/x86/mm/init.c b/arch/x86/mm/init.c
index 37b8b0f..3032644 100644
--- a/arch/x86/mm/init.c
+++ b/arch/x86/mm/init.c
@@ -16,8 +16,6 @@
#include <asm/tlb.h>
#include <asm/proto.h>
-DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
-
unsigned long __initdata pgt_buf_start;
unsigned long __meminitdata pgt_buf_end;
unsigned long __meminitdata pgt_buf_top;
diff --git a/arch/x86/pci/direct.c b/arch/x86/pci/direct.c
index bd33620..e6fd847 100644
--- a/arch/x86/pci/direct.c
+++ b/arch/x86/pci/direct.c
@@ -280,12 +280,9 @@
int __init pci_direct_probe(void)
{
- struct resource *region, *region2;
-
if ((pci_probe & PCI_PROBE_CONF1) == 0)
goto type2;
- region = request_region(0xCF8, 8, "PCI conf1");
- if (!region)
+ if (!request_region(0xCF8, 8, "PCI conf1"))
goto type2;
if (pci_check_type1()) {
@@ -293,16 +290,14 @@
port_cf9_safe = true;
return 1;
}
- release_resource(region);
+ release_region(0xCF8, 8);
type2:
if ((pci_probe & PCI_PROBE_CONF2) == 0)
return 0;
- region = request_region(0xCF8, 4, "PCI conf2");
- if (!region)
+ if (!request_region(0xCF8, 4, "PCI conf2"))
return 0;
- region2 = request_region(0xC000, 0x1000, "PCI conf2");
- if (!region2)
+ if (!request_region(0xC000, 0x1000, "PCI conf2"))
goto fail2;
if (pci_check_type2()) {
@@ -311,8 +306,8 @@
return 2;
}
- release_resource(region2);
+ release_region(0xC000, 0x1000);
fail2:
- release_resource(region);
+ release_region(0xCF8, 4);
return 0;
}
diff --git a/arch/x86/pci/irq.c b/arch/x86/pci/irq.c
index 8201165..372e9b8 100644
--- a/arch/x86/pci/irq.c
+++ b/arch/x86/pci/irq.c
@@ -602,7 +602,9 @@
|| (device >= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MIN &&
device <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX)
|| (device >= PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MIN &&
- device <= PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MAX)) {
+ device <= PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MAX)
+ || (device >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN &&
+ device <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX)) {
r->name = "PIIX/ICH";
r->get = pirq_piix_get;
r->set = pirq_piix_set;
diff --git a/arch/x86/pci/mmconfig-shared.c b/arch/x86/pci/mmconfig-shared.c
index e282886..750c346 100644
--- a/arch/x86/pci/mmconfig-shared.c
+++ b/arch/x86/pci/mmconfig-shared.c
@@ -606,6 +606,16 @@
if (list_empty(&pci_mmcfg_list))
return;
+ if (pcibios_last_bus < 0) {
+ const struct pci_mmcfg_region *cfg;
+
+ list_for_each_entry(cfg, &pci_mmcfg_list, list) {
+ if (cfg->segment)
+ break;
+ pcibios_last_bus = cfg->end_bus;
+ }
+ }
+
if (pci_mmcfg_arch_init())
pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;
else {
diff --git a/arch/xtensa/include/asm/page.h b/arch/xtensa/include/asm/page.h
index 161bb89..7a5591a 100644
--- a/arch/xtensa/include/asm/page.h
+++ b/arch/xtensa/include/asm/page.h
@@ -171,10 +171,6 @@
#define virt_addr_valid(kaddr) pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
#define page_to_phys(page) (page_to_pfn(page) << PAGE_SHIFT)
-#ifdef CONFIG_MMU
-#define WANT_PAGE_VIRTUAL
-#endif
-
#endif /* __ASSEMBLY__ */
#define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \
diff --git a/arch/xtensa/kernel/vmlinux.lds.S b/arch/xtensa/kernel/vmlinux.lds.S
index a282006..88ecea3 100644
--- a/arch/xtensa/kernel/vmlinux.lds.S
+++ b/arch/xtensa/kernel/vmlinux.lds.S
@@ -155,7 +155,7 @@
INIT_RAM_FS
}
- PERCPU(XCHAL_ICACHE_LINESIZE, PAGE_SIZE)
+ PERCPU_SECTION(XCHAL_ICACHE_LINESIZE)
/* We need this dummy segment here */
diff --git a/arch/xtensa/mm/mmu.c b/arch/xtensa/mm/mmu.c
index 4bb91a9..ca81654 100644
--- a/arch/xtensa/mm/mmu.c
+++ b/arch/xtensa/mm/mmu.c
@@ -14,8 +14,6 @@
#include <asm/mmu_context.h>
#include <asm/page.h>
-DEFINE_PER_CPU(struct mmu_gather, mmu_gathers);
-
void __init paging_init(void)
{
memset(swapper_pg_dir, 0, PAGE_SIZE);
diff --git a/arch/xtensa/mm/pgtable.c b/arch/xtensa/mm/pgtable.c
deleted file mode 100644
index 6979927..0000000
--- a/arch/xtensa/mm/pgtable.c
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * arch/xtensa/mm/pgtable.c
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2001 - 2005 Tensilica Inc.
- *
- * Chris Zankel <chris@zankel.net>
- */
-
-#if (DCACHE_SIZE > PAGE_SIZE)
-
-pte_t* pte_alloc_one_kernel(struct mm_struct *mm, unsigned long address)
-{
- pte_t *pte = NULL, *p;
- int color = ADDR_COLOR(address);
- int i;
-
- p = (pte_t*) __get_free_pages(GFP_KERNEL|__GFP_REPEAT, COLOR_ORDER);
-
- if (likely(p)) {
- split_page(virt_to_page(p), COLOR_ORDER);
-
- for (i = 0; i < COLOR_SIZE; i++) {
- if (ADDR_COLOR(p) == color)
- pte = p;
- else
- free_page(p);
- p += PTRS_PER_PTE;
- }
- clear_page(pte);
- }
- return pte;
-}
-
-#ifdef PROFILING
-
-int mask;
-int hit;
-int flush;
-
-#endif
-
-struct page* pte_alloc_one(struct mm_struct *mm, unsigned long address)
-{
- struct page *page = NULL, *p;
- int color = ADDR_COLOR(address);
-
- p = alloc_pages(GFP_KERNEL | __GFP_REPEAT, PTE_ORDER);
-
- if (likely(p)) {
- split_page(p, COLOR_ORDER);
-
- for (i = 0; i < PAGE_ORDER; i++) {
- if (PADDR_COLOR(page_address(p)) == color)
- page = p;
- else
- __free_page(p);
- p++;
- }
- clear_highpage(page);
- }
-
- return page;
-}
-
-#endif
-
-
-
diff --git a/block/blk-cgroup.c b/block/blk-cgroup.c
index 471fdcc..07371cf 100644
--- a/block/blk-cgroup.c
+++ b/block/blk-cgroup.c
@@ -385,25 +385,40 @@
spin_lock_irqsave(&blkg->stats_lock, flags);
blkg->stats.time += time;
+#ifdef CONFIG_DEBUG_BLK_CGROUP
blkg->stats.unaccounted_time += unaccounted_time;
+#endif
spin_unlock_irqrestore(&blkg->stats_lock, flags);
}
EXPORT_SYMBOL_GPL(blkiocg_update_timeslice_used);
+/*
+ * should be called under rcu read lock or queue lock to make sure blkg pointer
+ * is valid.
+ */
void blkiocg_update_dispatch_stats(struct blkio_group *blkg,
uint64_t bytes, bool direction, bool sync)
{
- struct blkio_group_stats *stats;
+ struct blkio_group_stats_cpu *stats_cpu;
unsigned long flags;
- spin_lock_irqsave(&blkg->stats_lock, flags);
- stats = &blkg->stats;
- stats->sectors += bytes >> 9;
- blkio_add_stat(stats->stat_arr[BLKIO_STAT_SERVICED], 1, direction,
- sync);
- blkio_add_stat(stats->stat_arr[BLKIO_STAT_SERVICE_BYTES], bytes,
- direction, sync);
- spin_unlock_irqrestore(&blkg->stats_lock, flags);
+ /*
+ * Disabling interrupts to provide mutual exclusion between two
+ * writes on same cpu. It probably is not needed for 64bit. Not
+ * optimizing that case yet.
+ */
+ local_irq_save(flags);
+
+ stats_cpu = this_cpu_ptr(blkg->stats_cpu);
+
+ u64_stats_update_begin(&stats_cpu->syncp);
+ stats_cpu->sectors += bytes >> 9;
+ blkio_add_stat(stats_cpu->stat_arr_cpu[BLKIO_STAT_CPU_SERVICED],
+ 1, direction, sync);
+ blkio_add_stat(stats_cpu->stat_arr_cpu[BLKIO_STAT_CPU_SERVICE_BYTES],
+ bytes, direction, sync);
+ u64_stats_update_end(&stats_cpu->syncp);
+ local_irq_restore(flags);
}
EXPORT_SYMBOL_GPL(blkiocg_update_dispatch_stats);
@@ -426,18 +441,44 @@
}
EXPORT_SYMBOL_GPL(blkiocg_update_completion_stats);
+/* Merged stats are per cpu. */
void blkiocg_update_io_merged_stats(struct blkio_group *blkg, bool direction,
bool sync)
{
+ struct blkio_group_stats_cpu *stats_cpu;
unsigned long flags;
- spin_lock_irqsave(&blkg->stats_lock, flags);
- blkio_add_stat(blkg->stats.stat_arr[BLKIO_STAT_MERGED], 1, direction,
- sync);
- spin_unlock_irqrestore(&blkg->stats_lock, flags);
+ /*
+ * Disabling interrupts to provide mutual exclusion between two
+ * writes on same cpu. It probably is not needed for 64bit. Not
+ * optimizing that case yet.
+ */
+ local_irq_save(flags);
+
+ stats_cpu = this_cpu_ptr(blkg->stats_cpu);
+
+ u64_stats_update_begin(&stats_cpu->syncp);
+ blkio_add_stat(stats_cpu->stat_arr_cpu[BLKIO_STAT_CPU_MERGED], 1,
+ direction, sync);
+ u64_stats_update_end(&stats_cpu->syncp);
+ local_irq_restore(flags);
}
EXPORT_SYMBOL_GPL(blkiocg_update_io_merged_stats);
+/*
+ * This function allocates the per cpu stats for blkio_group. Should be called
+ * from sleepable context as alloc_per_cpu() requires that.
+ */
+int blkio_alloc_blkg_stats(struct blkio_group *blkg)
+{
+ /* Allocate memory for per cpu stats */
+ blkg->stats_cpu = alloc_percpu(struct blkio_group_stats_cpu);
+ if (!blkg->stats_cpu)
+ return -ENOMEM;
+ return 0;
+}
+EXPORT_SYMBOL_GPL(blkio_alloc_blkg_stats);
+
void blkiocg_add_blkio_group(struct blkio_cgroup *blkcg,
struct blkio_group *blkg, void *key, dev_t dev,
enum blkio_policy_id plid)
@@ -508,6 +549,30 @@
}
EXPORT_SYMBOL_GPL(blkiocg_lookup_group);
+static void blkio_reset_stats_cpu(struct blkio_group *blkg)
+{
+ struct blkio_group_stats_cpu *stats_cpu;
+ int i, j, k;
+ /*
+ * Note: On 64 bit arch this should not be an issue. This has the
+ * possibility of returning some inconsistent value on 32bit arch
+ * as 64bit update on 32bit is non atomic. Taking care of this
+ * corner case makes code very complicated, like sending IPIs to
+ * cpus, taking care of stats of offline cpus etc.
+ *
+ * reset stats is anyway more of a debug feature and this sounds a
+ * corner case. So I am not complicating the code yet until and
+ * unless this becomes a real issue.
+ */
+ for_each_possible_cpu(i) {
+ stats_cpu = per_cpu_ptr(blkg->stats_cpu, i);
+ stats_cpu->sectors = 0;
+ for(j = 0; j < BLKIO_STAT_CPU_NR; j++)
+ for (k = 0; k < BLKIO_STAT_TOTAL; k++)
+ stats_cpu->stat_arr_cpu[j][k] = 0;
+ }
+}
+
static int
blkiocg_reset_stats(struct cgroup *cgroup, struct cftype *cftype, u64 val)
{
@@ -552,7 +617,11 @@
}
#endif
spin_unlock(&blkg->stats_lock);
+
+ /* Reset Per cpu stats which don't take blkg->stats_lock */
+ blkio_reset_stats_cpu(blkg);
}
+
spin_unlock_irq(&blkcg->lock);
return 0;
}
@@ -598,6 +667,59 @@
return val;
}
+
+static uint64_t blkio_read_stat_cpu(struct blkio_group *blkg,
+ enum stat_type_cpu type, enum stat_sub_type sub_type)
+{
+ int cpu;
+ struct blkio_group_stats_cpu *stats_cpu;
+ u64 val = 0, tval;
+
+ for_each_possible_cpu(cpu) {
+ unsigned int start;
+ stats_cpu = per_cpu_ptr(blkg->stats_cpu, cpu);
+
+ do {
+ start = u64_stats_fetch_begin(&stats_cpu->syncp);
+ if (type == BLKIO_STAT_CPU_SECTORS)
+ tval = stats_cpu->sectors;
+ else
+ tval = stats_cpu->stat_arr_cpu[type][sub_type];
+ } while(u64_stats_fetch_retry(&stats_cpu->syncp, start));
+
+ val += tval;
+ }
+
+ return val;
+}
+
+static uint64_t blkio_get_stat_cpu(struct blkio_group *blkg,
+ struct cgroup_map_cb *cb, dev_t dev, enum stat_type_cpu type)
+{
+ uint64_t disk_total, val;
+ char key_str[MAX_KEY_LEN];
+ enum stat_sub_type sub_type;
+
+ if (type == BLKIO_STAT_CPU_SECTORS) {
+ val = blkio_read_stat_cpu(blkg, type, 0);
+ return blkio_fill_stat(key_str, MAX_KEY_LEN - 1, val, cb, dev);
+ }
+
+ for (sub_type = BLKIO_STAT_READ; sub_type < BLKIO_STAT_TOTAL;
+ sub_type++) {
+ blkio_get_key_name(sub_type, dev, key_str, MAX_KEY_LEN, false);
+ val = blkio_read_stat_cpu(blkg, type, sub_type);
+ cb->fill(cb, key_str, val);
+ }
+
+ disk_total = blkio_read_stat_cpu(blkg, type, BLKIO_STAT_READ) +
+ blkio_read_stat_cpu(blkg, type, BLKIO_STAT_WRITE);
+
+ blkio_get_key_name(BLKIO_STAT_TOTAL, dev, key_str, MAX_KEY_LEN, false);
+ cb->fill(cb, key_str, disk_total);
+ return disk_total;
+}
+
/* This should be called with blkg->stats_lock held */
static uint64_t blkio_get_stat(struct blkio_group *blkg,
struct cgroup_map_cb *cb, dev_t dev, enum stat_type type)
@@ -609,9 +731,6 @@
if (type == BLKIO_STAT_TIME)
return blkio_fill_stat(key_str, MAX_KEY_LEN - 1,
blkg->stats.time, cb, dev);
- if (type == BLKIO_STAT_SECTORS)
- return blkio_fill_stat(key_str, MAX_KEY_LEN - 1,
- blkg->stats.sectors, cb, dev);
#ifdef CONFIG_DEBUG_BLK_CGROUP
if (type == BLKIO_STAT_UNACCOUNTED_TIME)
return blkio_fill_stat(key_str, MAX_KEY_LEN - 1,
@@ -1075,8 +1194,8 @@
}
static int blkio_read_blkg_stats(struct blkio_cgroup *blkcg,
- struct cftype *cft, struct cgroup_map_cb *cb, enum stat_type type,
- bool show_total)
+ struct cftype *cft, struct cgroup_map_cb *cb,
+ enum stat_type type, bool show_total, bool pcpu)
{
struct blkio_group *blkg;
struct hlist_node *n;
@@ -1087,10 +1206,15 @@
if (blkg->dev) {
if (!cftype_blkg_same_policy(cft, blkg))
continue;
- spin_lock_irq(&blkg->stats_lock);
- cgroup_total += blkio_get_stat(blkg, cb, blkg->dev,
- type);
- spin_unlock_irq(&blkg->stats_lock);
+ if (pcpu)
+ cgroup_total += blkio_get_stat_cpu(blkg, cb,
+ blkg->dev, type);
+ else {
+ spin_lock_irq(&blkg->stats_lock);
+ cgroup_total += blkio_get_stat(blkg, cb,
+ blkg->dev, type);
+ spin_unlock_irq(&blkg->stats_lock);
+ }
}
}
if (show_total)
@@ -1114,47 +1238,47 @@
switch(name) {
case BLKIO_PROP_time:
return blkio_read_blkg_stats(blkcg, cft, cb,
- BLKIO_STAT_TIME, 0);
+ BLKIO_STAT_TIME, 0, 0);
case BLKIO_PROP_sectors:
return blkio_read_blkg_stats(blkcg, cft, cb,
- BLKIO_STAT_SECTORS, 0);
+ BLKIO_STAT_CPU_SECTORS, 0, 1);
case BLKIO_PROP_io_service_bytes:
return blkio_read_blkg_stats(blkcg, cft, cb,
- BLKIO_STAT_SERVICE_BYTES, 1);
+ BLKIO_STAT_CPU_SERVICE_BYTES, 1, 1);
case BLKIO_PROP_io_serviced:
return blkio_read_blkg_stats(blkcg, cft, cb,
- BLKIO_STAT_SERVICED, 1);
+ BLKIO_STAT_CPU_SERVICED, 1, 1);
case BLKIO_PROP_io_service_time:
return blkio_read_blkg_stats(blkcg, cft, cb,
- BLKIO_STAT_SERVICE_TIME, 1);
+ BLKIO_STAT_SERVICE_TIME, 1, 0);
case BLKIO_PROP_io_wait_time:
return blkio_read_blkg_stats(blkcg, cft, cb,
- BLKIO_STAT_WAIT_TIME, 1);
+ BLKIO_STAT_WAIT_TIME, 1, 0);
case BLKIO_PROP_io_merged:
return blkio_read_blkg_stats(blkcg, cft, cb,
- BLKIO_STAT_MERGED, 1);
+ BLKIO_STAT_CPU_MERGED, 1, 1);
case BLKIO_PROP_io_queued:
return blkio_read_blkg_stats(blkcg, cft, cb,
- BLKIO_STAT_QUEUED, 1);
+ BLKIO_STAT_QUEUED, 1, 0);
#ifdef CONFIG_DEBUG_BLK_CGROUP
case BLKIO_PROP_unaccounted_time:
return blkio_read_blkg_stats(blkcg, cft, cb,
- BLKIO_STAT_UNACCOUNTED_TIME, 0);
+ BLKIO_STAT_UNACCOUNTED_TIME, 0, 0);
case BLKIO_PROP_dequeue:
return blkio_read_blkg_stats(blkcg, cft, cb,
- BLKIO_STAT_DEQUEUE, 0);
+ BLKIO_STAT_DEQUEUE, 0, 0);
case BLKIO_PROP_avg_queue_size:
return blkio_read_blkg_stats(blkcg, cft, cb,
- BLKIO_STAT_AVG_QUEUE_SIZE, 0);
+ BLKIO_STAT_AVG_QUEUE_SIZE, 0, 0);
case BLKIO_PROP_group_wait_time:
return blkio_read_blkg_stats(blkcg, cft, cb,
- BLKIO_STAT_GROUP_WAIT_TIME, 0);
+ BLKIO_STAT_GROUP_WAIT_TIME, 0, 0);
case BLKIO_PROP_idle_time:
return blkio_read_blkg_stats(blkcg, cft, cb,
- BLKIO_STAT_IDLE_TIME, 0);
+ BLKIO_STAT_IDLE_TIME, 0, 0);
case BLKIO_PROP_empty_time:
return blkio_read_blkg_stats(blkcg, cft, cb,
- BLKIO_STAT_EMPTY_TIME, 0);
+ BLKIO_STAT_EMPTY_TIME, 0, 0);
#endif
default:
BUG();
@@ -1164,10 +1288,10 @@
switch(name){
case BLKIO_THROTL_io_service_bytes:
return blkio_read_blkg_stats(blkcg, cft, cb,
- BLKIO_STAT_SERVICE_BYTES, 1);
+ BLKIO_STAT_CPU_SERVICE_BYTES, 1, 1);
case BLKIO_THROTL_io_serviced:
return blkio_read_blkg_stats(blkcg, cft, cb,
- BLKIO_STAT_SERVICED, 1);
+ BLKIO_STAT_CPU_SERVICED, 1, 1);
default:
BUG();
}
diff --git a/block/blk-cgroup.h b/block/blk-cgroup.h
index c774930..a71d290 100644
--- a/block/blk-cgroup.h
+++ b/block/blk-cgroup.h
@@ -14,6 +14,7 @@
*/
#include <linux/cgroup.h>
+#include <linux/u64_stats_sync.h>
enum blkio_policy_id {
BLKIO_POLICY_PROP = 0, /* Proportional Bandwidth division */
@@ -36,22 +37,15 @@
* request completion for IOs doen by this cgroup. This may not be
* accurate when NCQ is turned on. */
BLKIO_STAT_SERVICE_TIME = 0,
- /* Total bytes transferred */
- BLKIO_STAT_SERVICE_BYTES,
- /* Total IOs serviced, post merge */
- BLKIO_STAT_SERVICED,
/* Total time spent waiting in scheduler queue in ns */
BLKIO_STAT_WAIT_TIME,
- /* Number of IOs merged */
- BLKIO_STAT_MERGED,
/* Number of IOs queued up */
BLKIO_STAT_QUEUED,
/* All the single valued stats go below this */
BLKIO_STAT_TIME,
- BLKIO_STAT_SECTORS,
+#ifdef CONFIG_DEBUG_BLK_CGROUP
/* Time not charged to this cgroup */
BLKIO_STAT_UNACCOUNTED_TIME,
-#ifdef CONFIG_DEBUG_BLK_CGROUP
BLKIO_STAT_AVG_QUEUE_SIZE,
BLKIO_STAT_IDLE_TIME,
BLKIO_STAT_EMPTY_TIME,
@@ -60,6 +54,18 @@
#endif
};
+/* Per cpu stats */
+enum stat_type_cpu {
+ BLKIO_STAT_CPU_SECTORS,
+ /* Total bytes transferred */
+ BLKIO_STAT_CPU_SERVICE_BYTES,
+ /* Total IOs serviced, post merge */
+ BLKIO_STAT_CPU_SERVICED,
+ /* Number of IOs merged */
+ BLKIO_STAT_CPU_MERGED,
+ BLKIO_STAT_CPU_NR
+};
+
enum stat_sub_type {
BLKIO_STAT_READ = 0,
BLKIO_STAT_WRITE,
@@ -116,11 +122,11 @@
struct blkio_group_stats {
/* total disk time and nr sectors dispatched by this group */
uint64_t time;
- uint64_t sectors;
- /* Time not charged to this cgroup */
- uint64_t unaccounted_time;
uint64_t stat_arr[BLKIO_STAT_QUEUED + 1][BLKIO_STAT_TOTAL];
#ifdef CONFIG_DEBUG_BLK_CGROUP
+ /* Time not charged to this cgroup */
+ uint64_t unaccounted_time;
+
/* Sum of number of IOs queued across all samples */
uint64_t avg_queue_size_sum;
/* Count of samples taken for average */
@@ -145,6 +151,13 @@
#endif
};
+/* Per cpu blkio group stats */
+struct blkio_group_stats_cpu {
+ uint64_t sectors;
+ uint64_t stat_arr_cpu[BLKIO_STAT_CPU_NR][BLKIO_STAT_TOTAL];
+ struct u64_stats_sync syncp;
+};
+
struct blkio_group {
/* An rcu protected unique identifier for the group */
void *key;
@@ -160,6 +173,8 @@
/* Need to serialize the stats in the case of reset/update */
spinlock_t stats_lock;
struct blkio_group_stats stats;
+ /* Per cpu stats pointer */
+ struct blkio_group_stats_cpu __percpu *stats_cpu;
};
struct blkio_policy_node {
@@ -295,6 +310,7 @@
extern void blkiocg_add_blkio_group(struct blkio_cgroup *blkcg,
struct blkio_group *blkg, void *key, dev_t dev,
enum blkio_policy_id plid);
+extern int blkio_alloc_blkg_stats(struct blkio_group *blkg);
extern int blkiocg_del_blkio_group(struct blkio_group *blkg);
extern struct blkio_group *blkiocg_lookup_group(struct blkio_cgroup *blkcg,
void *key);
@@ -322,6 +338,8 @@
struct blkio_group *blkg, void *key, dev_t dev,
enum blkio_policy_id plid) {}
+static inline int blkio_alloc_blkg_stats(struct blkio_group *blkg) { return 0; }
+
static inline int
blkiocg_del_blkio_group(struct blkio_group *blkg) { return 0; }
diff --git a/block/blk-core.c b/block/blk-core.c
index 3fe00a1..c8303e9 100644
--- a/block/blk-core.c
+++ b/block/blk-core.c
@@ -569,8 +569,6 @@
static inline void blk_free_request(struct request_queue *q, struct request *rq)
{
- BUG_ON(rq->cmd_flags & REQ_ON_PLUG);
-
if (rq->cmd_flags & REQ_ELVPRIV)
elv_put_request(q, rq);
mempool_free(rq, q->rq.rq_pool);
@@ -1110,14 +1108,6 @@
{
const int ff = bio->bi_rw & REQ_FAILFAST_MASK;
- /*
- * Debug stuff, kill later
- */
- if (!rq_mergeable(req)) {
- blk_dump_rq_flags(req, "back");
- return false;
- }
-
if (!ll_back_merge_fn(q, req, bio))
return false;
@@ -1132,6 +1122,7 @@
req->ioprio = ioprio_best(req->ioprio, bio_prio(bio));
drive_stat_acct(req, 0);
+ elv_bio_merged(q, req, bio);
return true;
}
@@ -1141,14 +1132,6 @@
const int ff = bio->bi_rw & REQ_FAILFAST_MASK;
sector_t sector;
- /*
- * Debug stuff, kill later
- */
- if (!rq_mergeable(req)) {
- blk_dump_rq_flags(req, "front");
- return false;
- }
-
if (!ll_front_merge_fn(q, req, bio))
return false;
@@ -1173,6 +1156,7 @@
req->ioprio = ioprio_best(req->ioprio, bio_prio(bio));
drive_stat_acct(req, 0);
+ elv_bio_merged(q, req, bio);
return true;
}
@@ -1258,14 +1242,12 @@
el_ret = elv_merge(q, &req, bio);
if (el_ret == ELEVATOR_BACK_MERGE) {
- BUG_ON(req->cmd_flags & REQ_ON_PLUG);
if (bio_attempt_back_merge(q, req, bio)) {
if (!attempt_back_merge(q, req))
elv_merged_request(q, req, el_ret);
goto out_unlock;
}
} else if (el_ret == ELEVATOR_FRONT_MERGE) {
- BUG_ON(req->cmd_flags & REQ_ON_PLUG);
if (bio_attempt_front_merge(q, req, bio)) {
if (!attempt_front_merge(q, req))
elv_merged_request(q, req, el_ret);
@@ -1320,10 +1302,6 @@
if (__rq->q != q)
plug->should_sort = 1;
}
- /*
- * Debug flag, kill later
- */
- req->cmd_flags |= REQ_ON_PLUG;
list_add_tail(&req->queuelist, &plug->list);
drive_stat_acct(req, 1);
} else {
@@ -1550,7 +1528,8 @@
goto end_io;
}
- blk_throtl_bio(q, &bio);
+ if (blk_throtl_bio(q, &bio))
+ goto end_io;
/*
* If bio = NULL, bio has been throttled and will be submitted
@@ -2748,7 +2727,6 @@
while (!list_empty(&list)) {
rq = list_entry_rq(list.next);
list_del_init(&rq->queuelist);
- BUG_ON(!(rq->cmd_flags & REQ_ON_PLUG));
BUG_ON(!rq->q);
if (rq->q != q) {
/*
@@ -2760,8 +2738,6 @@
depth = 0;
spin_lock(q->queue_lock);
}
- rq->cmd_flags &= ~REQ_ON_PLUG;
-
/*
* rq is already accounted, so use raw insert
*/
diff --git a/block/blk-exec.c b/block/blk-exec.c
index 81e3181..8a0e7ec 100644
--- a/block/blk-exec.c
+++ b/block/blk-exec.c
@@ -56,7 +56,7 @@
spin_lock_irq(q->queue_lock);
__elv_add_request(q, rq, where);
__blk_run_queue(q);
- /* the queue is stopped so it won't be plugged+unplugged */
+ /* the queue is stopped so it won't be run */
if (rq->cmd_type == REQ_TYPE_PM_RESUME)
q->request_fn(q);
spin_unlock_irq(q->queue_lock);
diff --git a/block/blk-flush.c b/block/blk-flush.c
index 6c9b5e1..bb21e4c 100644
--- a/block/blk-flush.c
+++ b/block/blk-flush.c
@@ -212,13 +212,19 @@
}
/*
- * Moving a request silently to empty queue_head may stall the
- * queue. Kick the queue in those cases. This function is called
- * from request completion path and calling directly into
- * request_fn may confuse the driver. Always use kblockd.
+ * Kick the queue to avoid stall for two cases:
+ * 1. Moving a request silently to empty queue_head may stall the
+ * queue.
+ * 2. When flush request is running in non-queueable queue, the
+ * queue is hold. Restart the queue after flush request is finished
+ * to avoid stall.
+ * This function is called from request completion path and calling
+ * directly into request_fn may confuse the driver. Always use
+ * kblockd.
*/
- if (queued)
+ if (queued || q->flush_queue_delayed)
blk_run_queue_async(q);
+ q->flush_queue_delayed = 0;
}
/**
diff --git a/block/blk-ioc.c b/block/blk-ioc.c
index b791022..c898049 100644
--- a/block/blk-ioc.c
+++ b/block/blk-ioc.c
@@ -96,6 +96,9 @@
INIT_RADIX_TREE(&ret->radix_root, GFP_ATOMIC | __GFP_HIGH);
INIT_HLIST_HEAD(&ret->cic_list);
ret->ioc_data = NULL;
+#if defined(CONFIG_BLK_CGROUP) || defined(CONFIG_BLK_CGROUP_MODULE)
+ ret->cgroup_changed = 0;
+#endif
}
return ret;
diff --git a/block/blk-lib.c b/block/blk-lib.c
index 25de73e..78e627e 100644
--- a/block/blk-lib.c
+++ b/block/blk-lib.c
@@ -9,17 +9,20 @@
#include "blk.h"
-static void blkdev_discard_end_io(struct bio *bio, int err)
+struct bio_batch {
+ atomic_t done;
+ unsigned long flags;
+ struct completion *wait;
+};
+
+static void bio_batch_end_io(struct bio *bio, int err)
{
- if (err) {
- if (err == -EOPNOTSUPP)
- set_bit(BIO_EOPNOTSUPP, &bio->bi_flags);
- clear_bit(BIO_UPTODATE, &bio->bi_flags);
- }
+ struct bio_batch *bb = bio->bi_private;
- if (bio->bi_private)
- complete(bio->bi_private);
-
+ if (err && (err != -EOPNOTSUPP))
+ clear_bit(BIO_UPTODATE, &bb->flags);
+ if (atomic_dec_and_test(&bb->done))
+ complete(bb->wait);
bio_put(bio);
}
@@ -41,6 +44,7 @@
struct request_queue *q = bdev_get_queue(bdev);
int type = REQ_WRITE | REQ_DISCARD;
unsigned int max_discard_sectors;
+ struct bio_batch bb;
struct bio *bio;
int ret = 0;
@@ -67,7 +71,11 @@
type |= REQ_SECURE;
}
- while (nr_sects && !ret) {
+ atomic_set(&bb.done, 1);
+ bb.flags = 1 << BIO_UPTODATE;
+ bb.wait = &wait;
+
+ while (nr_sects) {
bio = bio_alloc(gfp_mask, 1);
if (!bio) {
ret = -ENOMEM;
@@ -75,9 +83,9 @@
}
bio->bi_sector = sector;
- bio->bi_end_io = blkdev_discard_end_io;
+ bio->bi_end_io = bio_batch_end_io;
bio->bi_bdev = bdev;
- bio->bi_private = &wait;
+ bio->bi_private = &bb;
if (nr_sects > max_discard_sectors) {
bio->bi_size = max_discard_sectors << 9;
@@ -88,45 +96,21 @@
nr_sects = 0;
}
- bio_get(bio);
+ atomic_inc(&bb.done);
submit_bio(type, bio);
+ }
+ /* Wait for bios in-flight */
+ if (!atomic_dec_and_test(&bb.done))
wait_for_completion(&wait);
- if (bio_flagged(bio, BIO_EOPNOTSUPP))
- ret = -EOPNOTSUPP;
- else if (!bio_flagged(bio, BIO_UPTODATE))
- ret = -EIO;
- bio_put(bio);
- }
+ if (!test_bit(BIO_UPTODATE, &bb.flags))
+ ret = -EIO;
return ret;
}
EXPORT_SYMBOL(blkdev_issue_discard);
-struct bio_batch
-{
- atomic_t done;
- unsigned long flags;
- struct completion *wait;
-};
-
-static void bio_batch_end_io(struct bio *bio, int err)
-{
- struct bio_batch *bb = bio->bi_private;
-
- if (err) {
- if (err == -EOPNOTSUPP)
- set_bit(BIO_EOPNOTSUPP, &bb->flags);
- else
- clear_bit(BIO_UPTODATE, &bb->flags);
- }
- if (bb)
- if (atomic_dec_and_test(&bb->done))
- complete(bb->wait);
- bio_put(bio);
-}
-
/**
* blkdev_issue_zeroout - generate number of zero filed write bios
* @bdev: blockdev to issue
@@ -151,7 +135,6 @@
bb.flags = 1 << BIO_UPTODATE;
bb.wait = &wait;
-submit:
ret = 0;
while (nr_sects != 0) {
bio = bio_alloc(gfp_mask,
@@ -168,9 +151,6 @@
while (nr_sects != 0) {
sz = min((sector_t) PAGE_SIZE >> 9 , nr_sects);
- if (sz == 0)
- /* bio has maximum size possible */
- break;
ret = bio_add_page(bio, ZERO_PAGE(0), sz << 9, 0);
nr_sects -= ret >> 9;
sector += ret >> 9;
@@ -190,16 +170,6 @@
/* One of bios in the batch was completed with error.*/
ret = -EIO;
- if (ret)
- goto out;
-
- if (test_bit(BIO_EOPNOTSUPP, &bb.flags)) {
- ret = -EOPNOTSUPP;
- goto out;
- }
- if (nr_sects != 0)
- goto submit;
-out:
return ret;
}
EXPORT_SYMBOL(blkdev_issue_zeroout);
diff --git a/block/blk-settings.c b/block/blk-settings.c
index 1fa7692..fa1eb04 100644
--- a/block/blk-settings.c
+++ b/block/blk-settings.c
@@ -120,7 +120,7 @@
lim->discard_granularity = 0;
lim->discard_alignment = 0;
lim->discard_misaligned = 0;
- lim->discard_zeroes_data = -1;
+ lim->discard_zeroes_data = 1;
lim->logical_block_size = lim->physical_block_size = lim->io_min = 512;
lim->bounce_pfn = (unsigned long)(BLK_BOUNCE_ANY >> PAGE_SHIFT);
lim->alignment_offset = 0;
@@ -166,6 +166,7 @@
blk_set_default_limits(&q->limits);
blk_queue_max_hw_sectors(q, BLK_SAFE_MAX_SECTORS);
+ q->limits.discard_zeroes_data = 0;
/*
* by default assume old behaviour and bounce for any highmem page
@@ -790,6 +791,12 @@
}
EXPORT_SYMBOL_GPL(blk_queue_flush);
+void blk_queue_flush_queueable(struct request_queue *q, bool queueable)
+{
+ q->flush_not_queueable = !queueable;
+}
+EXPORT_SYMBOL_GPL(blk_queue_flush_queueable);
+
static int __init blk_settings_init(void)
{
blk_max_low_pfn = max_low_pfn - 1;
diff --git a/block/blk-sysfs.c b/block/blk-sysfs.c
index bd23631..d935bd8 100644
--- a/block/blk-sysfs.c
+++ b/block/blk-sysfs.c
@@ -152,7 +152,8 @@
static ssize_t queue_discard_max_show(struct request_queue *q, char *page)
{
- return queue_var_show(q->limits.max_discard_sectors << 9, page);
+ return sprintf(page, "%llu\n",
+ (unsigned long long)q->limits.max_discard_sectors << 9);
}
static ssize_t queue_discard_zeroes_data_show(struct request_queue *q, char *page)
diff --git a/block/blk-throttle.c b/block/blk-throttle.c
index 252a81a..a62be8d 100644
--- a/block/blk-throttle.c
+++ b/block/blk-throttle.c
@@ -78,6 +78,8 @@
/* Some throttle limits got updated for the group */
int limits_changed;
+
+ struct rcu_head rcu_head;
};
struct throtl_data
@@ -88,7 +90,7 @@
/* service tree for active throtl groups */
struct throtl_rb_root tg_service_tree;
- struct throtl_grp root_tg;
+ struct throtl_grp *root_tg;
struct request_queue *queue;
/* Total Number of queued bios on READ and WRITE lists */
@@ -151,56 +153,44 @@
return tg;
}
+static void throtl_free_tg(struct rcu_head *head)
+{
+ struct throtl_grp *tg;
+
+ tg = container_of(head, struct throtl_grp, rcu_head);
+ free_percpu(tg->blkg.stats_cpu);
+ kfree(tg);
+}
+
static void throtl_put_tg(struct throtl_grp *tg)
{
BUG_ON(atomic_read(&tg->ref) <= 0);
if (!atomic_dec_and_test(&tg->ref))
return;
- kfree(tg);
+
+ /*
+ * A group is freed in rcu manner. But having an rcu lock does not
+ * mean that one can access all the fields of blkg and assume these
+ * are valid. For example, don't try to follow throtl_data and
+ * request queue links.
+ *
+ * Having a reference to blkg under an rcu allows acess to only
+ * values local to groups like group stats and group rate limits
+ */
+ call_rcu(&tg->rcu_head, throtl_free_tg);
}
-static struct throtl_grp * throtl_find_alloc_tg(struct throtl_data *td,
- struct blkio_cgroup *blkcg)
+static void throtl_init_group(struct throtl_grp *tg)
{
- struct throtl_grp *tg = NULL;
- void *key = td;
- struct backing_dev_info *bdi = &td->queue->backing_dev_info;
- unsigned int major, minor;
-
- /*
- * TODO: Speed up blkiocg_lookup_group() by maintaining a radix
- * tree of blkg (instead of traversing through hash list all
- * the time.
- */
-
- /*
- * This is the common case when there are no blkio cgroups.
- * Avoid lookup in this case
- */
- if (blkcg == &blkio_root_cgroup)
- tg = &td->root_tg;
- else
- tg = tg_of_blkg(blkiocg_lookup_group(blkcg, key));
-
- /* Fill in device details for root group */
- if (tg && !tg->blkg.dev && bdi->dev && dev_name(bdi->dev)) {
- sscanf(dev_name(bdi->dev), "%u:%u", &major, &minor);
- tg->blkg.dev = MKDEV(major, minor);
- goto done;
- }
-
- if (tg)
- goto done;
-
- tg = kzalloc_node(sizeof(*tg), GFP_ATOMIC, td->queue->node);
- if (!tg)
- goto done;
-
INIT_HLIST_NODE(&tg->tg_node);
RB_CLEAR_NODE(&tg->rb_node);
bio_list_init(&tg->bio_lists[0]);
bio_list_init(&tg->bio_lists[1]);
- td->limits_changed = false;
+ tg->limits_changed = false;
+
+ /* Practically unlimited BW */
+ tg->bps[0] = tg->bps[1] = -1;
+ tg->iops[0] = tg->iops[1] = -1;
/*
* Take the initial reference that will be released on destroy
@@ -209,33 +199,181 @@
* exit or cgroup deletion path depending on who is exiting first.
*/
atomic_set(&tg->ref, 1);
+}
+
+/* Should be called with rcu read lock held (needed for blkcg) */
+static void
+throtl_add_group_to_td_list(struct throtl_data *td, struct throtl_grp *tg)
+{
+ hlist_add_head(&tg->tg_node, &td->tg_list);
+ td->nr_undestroyed_grps++;
+}
+
+static void
+__throtl_tg_fill_dev_details(struct throtl_data *td, struct throtl_grp *tg)
+{
+ struct backing_dev_info *bdi = &td->queue->backing_dev_info;
+ unsigned int major, minor;
+
+ if (!tg || tg->blkg.dev)
+ return;
+
+ /*
+ * Fill in device details for a group which might not have been
+ * filled at group creation time as queue was being instantiated
+ * and driver had not attached a device yet
+ */
+ if (bdi->dev && dev_name(bdi->dev)) {
+ sscanf(dev_name(bdi->dev), "%u:%u", &major, &minor);
+ tg->blkg.dev = MKDEV(major, minor);
+ }
+}
+
+/*
+ * Should be called with without queue lock held. Here queue lock will be
+ * taken rarely. It will be taken only once during life time of a group
+ * if need be
+ */
+static void
+throtl_tg_fill_dev_details(struct throtl_data *td, struct throtl_grp *tg)
+{
+ if (!tg || tg->blkg.dev)
+ return;
+
+ spin_lock_irq(td->queue->queue_lock);
+ __throtl_tg_fill_dev_details(td, tg);
+ spin_unlock_irq(td->queue->queue_lock);
+}
+
+static void throtl_init_add_tg_lists(struct throtl_data *td,
+ struct throtl_grp *tg, struct blkio_cgroup *blkcg)
+{
+ __throtl_tg_fill_dev_details(td, tg);
/* Add group onto cgroup list */
- sscanf(dev_name(bdi->dev), "%u:%u", &major, &minor);
blkiocg_add_blkio_group(blkcg, &tg->blkg, (void *)td,
- MKDEV(major, minor), BLKIO_POLICY_THROTL);
+ tg->blkg.dev, BLKIO_POLICY_THROTL);
tg->bps[READ] = blkcg_get_read_bps(blkcg, tg->blkg.dev);
tg->bps[WRITE] = blkcg_get_write_bps(blkcg, tg->blkg.dev);
tg->iops[READ] = blkcg_get_read_iops(blkcg, tg->blkg.dev);
tg->iops[WRITE] = blkcg_get_write_iops(blkcg, tg->blkg.dev);
- hlist_add_head(&tg->tg_node, &td->tg_list);
- td->nr_undestroyed_grps++;
-done:
+ throtl_add_group_to_td_list(td, tg);
+}
+
+/* Should be called without queue lock and outside of rcu period */
+static struct throtl_grp *throtl_alloc_tg(struct throtl_data *td)
+{
+ struct throtl_grp *tg = NULL;
+ int ret;
+
+ tg = kzalloc_node(sizeof(*tg), GFP_ATOMIC, td->queue->node);
+ if (!tg)
+ return NULL;
+
+ ret = blkio_alloc_blkg_stats(&tg->blkg);
+
+ if (ret) {
+ kfree(tg);
+ return NULL;
+ }
+
+ throtl_init_group(tg);
return tg;
}
-static struct throtl_grp * throtl_get_tg(struct throtl_data *td)
+static struct
+throtl_grp *throtl_find_tg(struct throtl_data *td, struct blkio_cgroup *blkcg)
{
struct throtl_grp *tg = NULL;
+ void *key = td;
+
+ /*
+ * This is the common case when there are no blkio cgroups.
+ * Avoid lookup in this case
+ */
+ if (blkcg == &blkio_root_cgroup)
+ tg = td->root_tg;
+ else
+ tg = tg_of_blkg(blkiocg_lookup_group(blkcg, key));
+
+ __throtl_tg_fill_dev_details(td, tg);
+ return tg;
+}
+
+/*
+ * This function returns with queue lock unlocked in case of error, like
+ * request queue is no more
+ */
+static struct throtl_grp * throtl_get_tg(struct throtl_data *td)
+{
+ struct throtl_grp *tg = NULL, *__tg = NULL;
struct blkio_cgroup *blkcg;
+ struct request_queue *q = td->queue;
rcu_read_lock();
blkcg = task_blkio_cgroup(current);
- tg = throtl_find_alloc_tg(td, blkcg);
- if (!tg)
- tg = &td->root_tg;
+ tg = throtl_find_tg(td, blkcg);
+ if (tg) {
+ rcu_read_unlock();
+ return tg;
+ }
+
+ /*
+ * Need to allocate a group. Allocation of group also needs allocation
+ * of per cpu stats which in-turn takes a mutex() and can block. Hence
+ * we need to drop rcu lock and queue_lock before we call alloc
+ *
+ * Take the request queue reference to make sure queue does not
+ * go away once we return from allocation.
+ */
+ blk_get_queue(q);
+ rcu_read_unlock();
+ spin_unlock_irq(q->queue_lock);
+
+ tg = throtl_alloc_tg(td);
+ /*
+ * We might have slept in group allocation. Make sure queue is not
+ * dead
+ */
+ if (unlikely(test_bit(QUEUE_FLAG_DEAD, &q->queue_flags))) {
+ blk_put_queue(q);
+ if (tg)
+ kfree(tg);
+
+ return ERR_PTR(-ENODEV);
+ }
+ blk_put_queue(q);
+
+ /* Group allocated and queue is still alive. take the lock */
+ spin_lock_irq(q->queue_lock);
+
+ /*
+ * Initialize the new group. After sleeping, read the blkcg again.
+ */
+ rcu_read_lock();
+ blkcg = task_blkio_cgroup(current);
+
+ /*
+ * If some other thread already allocated the group while we were
+ * not holding queue lock, free up the group
+ */
+ __tg = throtl_find_tg(td, blkcg);
+
+ if (__tg) {
+ kfree(tg);
+ rcu_read_unlock();
+ return __tg;
+ }
+
+ /* Group allocation failed. Account the IO to root group */
+ if (!tg) {
+ tg = td->root_tg;
+ return tg;
+ }
+
+ throtl_init_add_tg_lists(td, tg, blkcg);
rcu_read_unlock();
return tg;
}
@@ -544,6 +682,12 @@
return 0;
}
+static bool tg_no_rule_group(struct throtl_grp *tg, bool rw) {
+ if (tg->bps[rw] == -1 && tg->iops[rw] == -1)
+ return 1;
+ return 0;
+}
+
/*
* Returns whether one can dispatch a bio or not. Also returns approx number
* of jiffies to wait before this bio is with-in IO rate and can be dispatched
@@ -608,10 +752,6 @@
tg->bytes_disp[rw] += bio->bi_size;
tg->io_disp[rw]++;
- /*
- * TODO: This will take blkg->stats_lock. Figure out a way
- * to avoid this cost.
- */
blkiocg_update_dispatch_stats(&tg->blkg, bio->bi_size, rw, sync);
}
@@ -989,15 +1129,51 @@
struct throtl_grp *tg;
struct bio *bio = *biop;
bool rw = bio_data_dir(bio), update_disptime = true;
+ struct blkio_cgroup *blkcg;
if (bio->bi_rw & REQ_THROTTLED) {
bio->bi_rw &= ~REQ_THROTTLED;
return 0;
}
+ /*
+ * A throtl_grp pointer retrieved under rcu can be used to access
+ * basic fields like stats and io rates. If a group has no rules,
+ * just update the dispatch stats in lockless manner and return.
+ */
+
+ rcu_read_lock();
+ blkcg = task_blkio_cgroup(current);
+ tg = throtl_find_tg(td, blkcg);
+ if (tg) {
+ throtl_tg_fill_dev_details(td, tg);
+
+ if (tg_no_rule_group(tg, rw)) {
+ blkiocg_update_dispatch_stats(&tg->blkg, bio->bi_size,
+ rw, bio->bi_rw & REQ_SYNC);
+ rcu_read_unlock();
+ return 0;
+ }
+ }
+ rcu_read_unlock();
+
+ /*
+ * Either group has not been allocated yet or it is not an unlimited
+ * IO group
+ */
+
spin_lock_irq(q->queue_lock);
tg = throtl_get_tg(td);
+ if (IS_ERR(tg)) {
+ if (PTR_ERR(tg) == -ENODEV) {
+ /*
+ * Queue is gone. No queue lock held here.
+ */
+ return -ENODEV;
+ }
+ }
+
if (tg->nr_queued[rw]) {
/*
* There is already another bio queued in same dir. No
@@ -1060,39 +1236,24 @@
INIT_HLIST_HEAD(&td->tg_list);
td->tg_service_tree = THROTL_RB_ROOT;
td->limits_changed = false;
-
- /* Init root group */
- tg = &td->root_tg;
- INIT_HLIST_NODE(&tg->tg_node);
- RB_CLEAR_NODE(&tg->rb_node);
- bio_list_init(&tg->bio_lists[0]);
- bio_list_init(&tg->bio_lists[1]);
-
- /* Practically unlimited BW */
- tg->bps[0] = tg->bps[1] = -1;
- tg->iops[0] = tg->iops[1] = -1;
- td->limits_changed = false;
-
- /*
- * Set root group reference to 2. One reference will be dropped when
- * all groups on tg_list are being deleted during queue exit. Other
- * reference will remain there as we don't want to delete this group
- * as it is statically allocated and gets destroyed when throtl_data
- * goes away.
- */
- atomic_set(&tg->ref, 2);
- hlist_add_head(&tg->tg_node, &td->tg_list);
- td->nr_undestroyed_grps++;
-
INIT_DELAYED_WORK(&td->throtl_work, blk_throtl_work);
+ /* alloc and Init root group. */
+ td->queue = q;
+ tg = throtl_alloc_tg(td);
+
+ if (!tg) {
+ kfree(td);
+ return -ENOMEM;
+ }
+
+ td->root_tg = tg;
+
rcu_read_lock();
- blkiocg_add_blkio_group(&blkio_root_cgroup, &tg->blkg, (void *)td,
- 0, BLKIO_POLICY_THROTL);
+ throtl_init_add_tg_lists(td, tg, &blkio_root_cgroup);
rcu_read_unlock();
/* Attach throtl data to request queue */
- td->queue = q;
q->td = td;
return 0;
}
diff --git a/block/blk.h b/block/blk.h
index 6126346..d658628 100644
--- a/block/blk.h
+++ b/block/blk.h
@@ -62,7 +62,28 @@
return rq;
}
- if (!q->elevator->ops->elevator_dispatch_fn(q, 0))
+ /*
+ * Flush request is running and flush request isn't queueable
+ * in the drive, we can hold the queue till flush request is
+ * finished. Even we don't do this, driver can't dispatch next
+ * requests and will requeue them. And this can improve
+ * throughput too. For example, we have request flush1, write1,
+ * flush 2. flush1 is dispatched, then queue is hold, write1
+ * isn't inserted to queue. After flush1 is finished, flush2
+ * will be dispatched. Since disk cache is already clean,
+ * flush2 will be finished very soon, so looks like flush2 is
+ * folded to flush1.
+ * Since the queue is hold, a flag is set to indicate the queue
+ * should be restarted later. Please see flush_end_io() for
+ * details.
+ */
+ if (q->flush_pending_idx != q->flush_running_idx &&
+ !queue_flush_queueable(q)) {
+ q->flush_queue_delayed = 1;
+ return NULL;
+ }
+ if (test_bit(QUEUE_FLAG_DEAD, &q->queue_flags) ||
+ !q->elevator->ops->elevator_dispatch_fn(q, 0))
return NULL;
}
}
diff --git a/block/cfq-iosched.c b/block/cfq-iosched.c
index ab7a9e6..7c52d68 100644
--- a/block/cfq-iosched.c
+++ b/block/cfq-iosched.c
@@ -300,7 +300,9 @@
/* List of cfq groups being managed on this device*/
struct hlist_head cfqg_list;
- struct rcu_head rcu;
+
+ /* Number of groups which are on blkcg->blkg_list */
+ unsigned int nr_blkcg_linked_grps;
};
static struct cfq_group *cfq_get_next_cfqg(struct cfq_data *cfqd);
@@ -665,15 +667,11 @@
if (rq2 == NULL)
return rq1;
- if (rq_is_sync(rq1) && !rq_is_sync(rq2))
- return rq1;
- else if (rq_is_sync(rq2) && !rq_is_sync(rq1))
- return rq2;
- if ((rq1->cmd_flags & REQ_META) && !(rq2->cmd_flags & REQ_META))
- return rq1;
- else if ((rq2->cmd_flags & REQ_META) &&
- !(rq1->cmd_flags & REQ_META))
- return rq2;
+ if (rq_is_sync(rq1) != rq_is_sync(rq2))
+ return rq_is_sync(rq1) ? rq1 : rq2;
+
+ if ((rq1->cmd_flags ^ rq2->cmd_flags) & REQ_META)
+ return rq1->cmd_flags & REQ_META ? rq1 : rq2;
s1 = blk_rq_pos(rq1);
s2 = blk_rq_pos(rq2);
@@ -1014,28 +1012,47 @@
cfqg->needs_update = true;
}
-static struct cfq_group * cfq_find_alloc_cfqg(struct cfq_data *cfqd,
- struct blkio_cgroup *blkcg, int create)
+static void cfq_init_add_cfqg_lists(struct cfq_data *cfqd,
+ struct cfq_group *cfqg, struct blkio_cgroup *blkcg)
{
- struct cfq_group *cfqg = NULL;
- void *key = cfqd;
- int i, j;
- struct cfq_rb_root *st;
struct backing_dev_info *bdi = &cfqd->queue->backing_dev_info;
unsigned int major, minor;
- cfqg = cfqg_of_blkg(blkiocg_lookup_group(blkcg, key));
- if (cfqg && !cfqg->blkg.dev && bdi->dev && dev_name(bdi->dev)) {
+ /*
+ * Add group onto cgroup list. It might happen that bdi->dev is
+ * not initialized yet. Initialize this new group without major
+ * and minor info and this info will be filled in once a new thread
+ * comes for IO.
+ */
+ if (bdi->dev) {
sscanf(dev_name(bdi->dev), "%u:%u", &major, &minor);
- cfqg->blkg.dev = MKDEV(major, minor);
- goto done;
- }
- if (cfqg || !create)
- goto done;
+ cfq_blkiocg_add_blkio_group(blkcg, &cfqg->blkg,
+ (void *)cfqd, MKDEV(major, minor));
+ } else
+ cfq_blkiocg_add_blkio_group(blkcg, &cfqg->blkg,
+ (void *)cfqd, 0);
+
+ cfqd->nr_blkcg_linked_grps++;
+ cfqg->weight = blkcg_get_weight(blkcg, cfqg->blkg.dev);
+
+ /* Add group on cfqd list */
+ hlist_add_head(&cfqg->cfqd_node, &cfqd->cfqg_list);
+}
+
+/*
+ * Should be called from sleepable context. No request queue lock as per
+ * cpu stats are allocated dynamically and alloc_percpu needs to be called
+ * from sleepable context.
+ */
+static struct cfq_group * cfq_alloc_cfqg(struct cfq_data *cfqd)
+{
+ struct cfq_group *cfqg = NULL;
+ int i, j, ret;
+ struct cfq_rb_root *st;
cfqg = kzalloc_node(sizeof(*cfqg), GFP_ATOMIC, cfqd->queue->node);
if (!cfqg)
- goto done;
+ return NULL;
for_each_cfqg_st(cfqg, i, j, st)
*st = CFQ_RB_ROOT;
@@ -1049,43 +1066,94 @@
*/
cfqg->ref = 1;
+ ret = blkio_alloc_blkg_stats(&cfqg->blkg);
+ if (ret) {
+ kfree(cfqg);
+ return NULL;
+ }
+
+ return cfqg;
+}
+
+static struct cfq_group *
+cfq_find_cfqg(struct cfq_data *cfqd, struct blkio_cgroup *blkcg)
+{
+ struct cfq_group *cfqg = NULL;
+ void *key = cfqd;
+ struct backing_dev_info *bdi = &cfqd->queue->backing_dev_info;
+ unsigned int major, minor;
+
/*
- * Add group onto cgroup list. It might happen that bdi->dev is
- * not initialized yet. Initialize this new group without major
- * and minor info and this info will be filled in once a new thread
- * comes for IO. See code above.
+ * This is the common case when there are no blkio cgroups.
+ * Avoid lookup in this case
*/
- if (bdi->dev) {
+ if (blkcg == &blkio_root_cgroup)
+ cfqg = &cfqd->root_group;
+ else
+ cfqg = cfqg_of_blkg(blkiocg_lookup_group(blkcg, key));
+
+ if (cfqg && !cfqg->blkg.dev && bdi->dev && dev_name(bdi->dev)) {
sscanf(dev_name(bdi->dev), "%u:%u", &major, &minor);
- cfq_blkiocg_add_blkio_group(blkcg, &cfqg->blkg, (void *)cfqd,
- MKDEV(major, minor));
- } else
- cfq_blkiocg_add_blkio_group(blkcg, &cfqg->blkg, (void *)cfqd,
- 0);
+ cfqg->blkg.dev = MKDEV(major, minor);
+ }
- cfqg->weight = blkcg_get_weight(blkcg, cfqg->blkg.dev);
-
- /* Add group on cfqd list */
- hlist_add_head(&cfqg->cfqd_node, &cfqd->cfqg_list);
-
-done:
return cfqg;
}
/*
- * Search for the cfq group current task belongs to. If create = 1, then also
- * create the cfq group if it does not exist. request_queue lock must be held.
+ * Search for the cfq group current task belongs to. request_queue lock must
+ * be held.
*/
-static struct cfq_group *cfq_get_cfqg(struct cfq_data *cfqd, int create)
+static struct cfq_group *cfq_get_cfqg(struct cfq_data *cfqd)
{
struct blkio_cgroup *blkcg;
- struct cfq_group *cfqg = NULL;
+ struct cfq_group *cfqg = NULL, *__cfqg = NULL;
+ struct request_queue *q = cfqd->queue;
rcu_read_lock();
blkcg = task_blkio_cgroup(current);
- cfqg = cfq_find_alloc_cfqg(cfqd, blkcg, create);
- if (!cfqg && create)
+ cfqg = cfq_find_cfqg(cfqd, blkcg);
+ if (cfqg) {
+ rcu_read_unlock();
+ return cfqg;
+ }
+
+ /*
+ * Need to allocate a group. Allocation of group also needs allocation
+ * of per cpu stats which in-turn takes a mutex() and can block. Hence
+ * we need to drop rcu lock and queue_lock before we call alloc.
+ *
+ * Not taking any queue reference here and assuming that queue is
+ * around by the time we return. CFQ queue allocation code does
+ * the same. It might be racy though.
+ */
+
+ rcu_read_unlock();
+ spin_unlock_irq(q->queue_lock);
+
+ cfqg = cfq_alloc_cfqg(cfqd);
+
+ spin_lock_irq(q->queue_lock);
+
+ rcu_read_lock();
+ blkcg = task_blkio_cgroup(current);
+
+ /*
+ * If some other thread already allocated the group while we were
+ * not holding queue lock, free up the group
+ */
+ __cfqg = cfq_find_cfqg(cfqd, blkcg);
+
+ if (__cfqg) {
+ kfree(cfqg);
+ rcu_read_unlock();
+ return __cfqg;
+ }
+
+ if (!cfqg)
cfqg = &cfqd->root_group;
+
+ cfq_init_add_cfqg_lists(cfqd, cfqg, blkcg);
rcu_read_unlock();
return cfqg;
}
@@ -1118,6 +1186,7 @@
return;
for_each_cfqg_st(cfqg, i, j, st)
BUG_ON(!RB_EMPTY_ROOT(&st->rb));
+ free_percpu(cfqg->blkg.stats_cpu);
kfree(cfqg);
}
@@ -1176,7 +1245,7 @@
}
#else /* GROUP_IOSCHED */
-static struct cfq_group *cfq_get_cfqg(struct cfq_data *cfqd, int create)
+static struct cfq_group *cfq_get_cfqg(struct cfq_data *cfqd)
{
return &cfqd->root_group;
}
@@ -1210,7 +1279,6 @@
struct cfq_rb_root *service_tree;
int left;
int new_cfqq = 1;
- int group_changed = 0;
service_tree = service_tree_for(cfqq->cfqg, cfqq_prio(cfqq),
cfqq_type(cfqq));
@@ -1281,7 +1349,7 @@
rb_link_node(&cfqq->rb_node, parent, p);
rb_insert_color(&cfqq->rb_node, &service_tree->rb);
service_tree->count++;
- if ((add_front || !new_cfqq) && !group_changed)
+ if (add_front || !new_cfqq)
return;
cfq_group_notify_queue_add(cfqd, cfqq->cfqg);
}
@@ -2029,7 +2097,7 @@
WARN_ON(cfqq->ioprio >= IOPRIO_BE_NR);
- return 2 * (base_rq + base_rq * (CFQ_PRIO_LISTS - 1 - cfqq->ioprio));
+ return 2 * base_rq * (IOPRIO_BE_NR - cfqq->ioprio);
}
/*
@@ -2911,7 +2979,7 @@
struct cfq_group *cfqg;
retry:
- cfqg = cfq_get_cfqg(cfqd, 1);
+ cfqg = cfq_get_cfqg(cfqd);
cic = cfq_cic_lookup(cfqd, ioc);
/* cic always exists here */
cfqq = cic_to_cfqq(cic, is_sync);
@@ -3815,15 +3883,11 @@
cfq_put_queue(cfqd->async_idle_cfqq);
}
-static void cfq_cfqd_free(struct rcu_head *head)
-{
- kfree(container_of(head, struct cfq_data, rcu));
-}
-
static void cfq_exit_queue(struct elevator_queue *e)
{
struct cfq_data *cfqd = e->elevator_data;
struct request_queue *q = cfqd->queue;
+ bool wait = false;
cfq_shutdown_timer_wq(cfqd);
@@ -3842,7 +3906,13 @@
cfq_put_async_queues(cfqd);
cfq_release_cfq_groups(cfqd);
- cfq_blkiocg_del_blkio_group(&cfqd->root_group.blkg);
+
+ /*
+ * If there are groups which we could not unlink from blkcg list,
+ * wait for a rcu period for them to be freed.
+ */
+ if (cfqd->nr_blkcg_linked_grps)
+ wait = true;
spin_unlock_irq(q->queue_lock);
@@ -3852,8 +3922,25 @@
ida_remove(&cic_index_ida, cfqd->cic_index);
spin_unlock(&cic_index_lock);
- /* Wait for cfqg->blkg->key accessors to exit their grace periods. */
- call_rcu(&cfqd->rcu, cfq_cfqd_free);
+ /*
+ * Wait for cfqg->blkg->key accessors to exit their grace periods.
+ * Do this wait only if there are other unlinked groups out
+ * there. This can happen if cgroup deletion path claimed the
+ * responsibility of cleaning up a group before queue cleanup code
+ * get to the group.
+ *
+ * Do not call synchronize_rcu() unconditionally as there are drivers
+ * which create/delete request queue hundreds of times during scan/boot
+ * and synchronize_rcu() can take significant time and slow down boot.
+ */
+ if (wait)
+ synchronize_rcu();
+
+#ifdef CONFIG_CFQ_GROUP_IOSCHED
+ /* Free up per cpu stats for root group */
+ free_percpu(cfqd->root_group.blkg.stats_cpu);
+#endif
+ kfree(cfqd);
}
static int cfq_alloc_cic_index(void)
@@ -3886,8 +3973,12 @@
return NULL;
cfqd = kmalloc_node(sizeof(*cfqd), GFP_KERNEL | __GFP_ZERO, q->node);
- if (!cfqd)
+ if (!cfqd) {
+ spin_lock(&cic_index_lock);
+ ida_remove(&cic_index_ida, i);
+ spin_unlock(&cic_index_lock);
return NULL;
+ }
/*
* Don't need take queue_lock in the routine, since we are
@@ -3909,14 +4000,29 @@
#ifdef CONFIG_CFQ_GROUP_IOSCHED
/*
- * Take a reference to root group which we never drop. This is just
- * to make sure that cfq_put_cfqg() does not try to kfree root group
+ * Set root group reference to 2. One reference will be dropped when
+ * all groups on cfqd->cfqg_list are being deleted during queue exit.
+ * Other reference will remain there as we don't want to delete this
+ * group as it is statically allocated and gets destroyed when
+ * throtl_data goes away.
*/
- cfqg->ref = 1;
+ cfqg->ref = 2;
+
+ if (blkio_alloc_blkg_stats(&cfqg->blkg)) {
+ kfree(cfqg);
+ kfree(cfqd);
+ return NULL;
+ }
+
rcu_read_lock();
+
cfq_blkiocg_add_blkio_group(&blkio_root_cgroup, &cfqg->blkg,
(void *)cfqd, 0);
rcu_read_unlock();
+ cfqd->nr_blkcg_linked_grps++;
+
+ /* Add group on cfqd->cfqg_list */
+ hlist_add_head(&cfqg->cfqd_node, &cfqd->cfqg_list);
#endif
/*
* Not strictly needed (since RB_ROOT just clears the node and we
diff --git a/block/elevator.c b/block/elevator.c
index 45ca1e3..b0b38ce 100644
--- a/block/elevator.c
+++ b/block/elevator.c
@@ -155,13 +155,8 @@
e = elevator_find(name);
if (!e) {
- char elv[ELV_NAME_MAX + strlen("-iosched")];
-
spin_unlock(&elv_list_lock);
-
- snprintf(elv, sizeof(elv), "%s-iosched", name);
-
- request_module("%s", elv);
+ request_module("%s-iosched", name);
spin_lock(&elv_list_lock);
e = elevator_find(name);
}
@@ -421,8 +416,6 @@
struct list_head *entry;
int stop_flags;
- BUG_ON(rq->cmd_flags & REQ_ON_PLUG);
-
if (q->last_merge == rq)
q->last_merge = NULL;
@@ -661,8 +654,6 @@
rq->q = q;
- BUG_ON(rq->cmd_flags & REQ_ON_PLUG);
-
if (rq->cmd_flags & REQ_SOFTBARRIER) {
/* barriers are scheduling boundary, update end_sector */
if (rq->cmd_type == REQ_TYPE_FS ||
diff --git a/drivers/Kconfig b/drivers/Kconfig
index 61631ed..3bb154d 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -54,6 +54,8 @@
source "drivers/pps/Kconfig"
+source "drivers/ptp/Kconfig"
+
source "drivers/gpio/Kconfig"
source "drivers/w1/Kconfig"
diff --git a/drivers/Makefile b/drivers/Makefile
index a29527f..6b17f58 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -64,11 +64,10 @@
obj-$(CONFIG_PARIDE) += block/paride/
obj-$(CONFIG_TC) += tc/
obj-$(CONFIG_UWB) += uwb/
-obj-$(CONFIG_USB_OTG_UTILS) += usb/otg/
+obj-$(CONFIG_USB_OTG_UTILS) += usb/
obj-$(CONFIG_USB) += usb/
-obj-$(CONFIG_USB_MUSB_HDRC) += usb/musb/
obj-$(CONFIG_PCI) += usb/
-obj-$(CONFIG_USB_GADGET) += usb/gadget/
+obj-$(CONFIG_USB_GADGET) += usb/
obj-$(CONFIG_SERIO) += input/serio/
obj-$(CONFIG_GAMEPORT) += input/gameport/
obj-$(CONFIG_INPUT) += input/
@@ -76,6 +75,7 @@
obj-$(CONFIG_RTC_LIB) += rtc/
obj-y += i2c/ media/
obj-$(CONFIG_PPS) += pps/
+obj-$(CONFIG_PTP_1588_CLOCK) += ptp/
obj-$(CONFIG_W1) += w1/
obj-$(CONFIG_POWER_SUPPLY) += power/
obj-$(CONFIG_HWMON) += hwmon/
@@ -95,7 +95,7 @@
obj-$(CONFIG_DMA_ENGINE) += dma/
obj-$(CONFIG_MMC) += mmc/
obj-$(CONFIG_MEMSTICK) += memstick/
-obj-$(CONFIG_NEW_LEDS) += leds/
+obj-y += leds/
obj-$(CONFIG_INFINIBAND) += infiniband/
obj-$(CONFIG_SGI_SN) += sn/
obj-y += firmware/
diff --git a/drivers/acpi/Kconfig b/drivers/acpi/Kconfig
index 3a17ca5..bc2218d 100644
--- a/drivers/acpi/Kconfig
+++ b/drivers/acpi/Kconfig
@@ -73,17 +73,6 @@
Say N to delete power /proc/acpi/ directories that have moved to /sys/
-config ACPI_POWER_METER
- tristate "ACPI 4.0 power meter"
- depends on HWMON
- help
- This driver exposes ACPI 4.0 power meters as hardware monitoring
- devices. Say Y (or M) if you have a computer with ACPI 4.0 firmware
- and a power meter.
-
- To compile this driver as a module, choose M here:
- the module will be called power-meter.
-
config ACPI_EC_DEBUGFS
tristate "EC read/write access through /sys/kernel/debug/ec"
default n
diff --git a/drivers/acpi/Makefile b/drivers/acpi/Makefile
index d113fa5..b66fbb2 100644
--- a/drivers/acpi/Makefile
+++ b/drivers/acpi/Makefile
@@ -59,7 +59,6 @@
obj-$(CONFIG_ACPI_BATTERY) += battery.o
obj-$(CONFIG_ACPI_SBS) += sbshc.o
obj-$(CONFIG_ACPI_SBS) += sbs.o
-obj-$(CONFIG_ACPI_POWER_METER) += power_meter.o
obj-$(CONFIG_ACPI_HED) += hed.o
obj-$(CONFIG_ACPI_EC_DEBUGFS) += ec_sys.o
diff --git a/drivers/acpi/apei/einj.c b/drivers/acpi/apei/einj.c
index 096aebf..f74b2ea 100644
--- a/drivers/acpi/apei/einj.c
+++ b/drivers/acpi/apei/einj.c
@@ -101,6 +101,14 @@
static struct einj_parameter *einj_param;
+#ifndef writeq
+static inline void writeq(__u64 val, volatile void __iomem *addr)
+{
+ writel(val, addr);
+ writel(val >> 32, addr+4);
+}
+#endif
+
static void einj_exec_ctx_init(struct apei_exec_context *ctx)
{
apei_exec_ctx_init(ctx, einj_ins_type, ARRAY_SIZE(einj_ins_type),
diff --git a/drivers/acpi/atomicio.c b/drivers/acpi/atomicio.c
index 542e539..7489b89 100644
--- a/drivers/acpi/atomicio.c
+++ b/drivers/acpi/atomicio.c
@@ -280,9 +280,11 @@
case 32:
*val = readl(addr);
break;
+#ifdef readq
case 64:
*val = readq(addr);
break;
+#endif
default:
return -EINVAL;
}
@@ -307,9 +309,11 @@
case 32:
writel(val, addr);
break;
+#ifdef writeq
case 64:
writeq(val, addr);
break;
+#endif
default:
return -EINVAL;
}
diff --git a/drivers/acpi/pci_root.c b/drivers/acpi/pci_root.c
index f911a2f..d06078d 100644
--- a/drivers/acpi/pci_root.c
+++ b/drivers/acpi/pci_root.c
@@ -596,12 +596,18 @@
dev_info(root->bus->bridge,
"ACPI _OSC control (0x%02x) granted\n", flags);
} else {
- dev_dbg(root->bus->bridge,
- "ACPI _OSC request failed (code %d)\n", status);
- printk(KERN_INFO "Unable to assume _OSC PCIe control. "
- "Disabling ASPM\n");
+ dev_info(root->bus->bridge,
+ "ACPI _OSC request failed (%s), "
+ "returned control mask: 0x%02x\n",
+ acpi_format_exception(status), flags);
+ pr_info("ACPI _OSC control for PCIe not granted, "
+ "disabling ASPM\n");
pcie_no_aspm();
}
+ } else {
+ dev_info(root->bus->bridge,
+ "Unable to request _OSC control "
+ "(_OSC support mask: 0x%02x)\n", flags);
}
pci_acpi_add_bus_pm_notifier(device, root->bus);
diff --git a/drivers/ata/libata-scsi.c b/drivers/ata/libata-scsi.c
index 30ea95f..d51f979 100644
--- a/drivers/ata/libata-scsi.c
+++ b/drivers/ata/libata-scsi.c
@@ -1089,21 +1089,21 @@
static int ata_scsi_dev_config(struct scsi_device *sdev,
struct ata_device *dev)
{
+ struct request_queue *q = sdev->request_queue;
+
if (!ata_id_has_unload(dev->id))
dev->flags |= ATA_DFLAG_NO_UNLOAD;
/* configure max sectors */
- blk_queue_max_hw_sectors(sdev->request_queue, dev->max_sectors);
+ blk_queue_max_hw_sectors(q, dev->max_sectors);
if (dev->class == ATA_DEV_ATAPI) {
- struct request_queue *q = sdev->request_queue;
void *buf;
sdev->sector_size = ATA_SECT_SIZE;
/* set DMA padding */
- blk_queue_update_dma_pad(sdev->request_queue,
- ATA_DMA_PAD_SZ - 1);
+ blk_queue_update_dma_pad(q, ATA_DMA_PAD_SZ - 1);
/* configure draining */
buf = kmalloc(ATAPI_MAX_DRAIN, q->bounce_gfp | GFP_KERNEL);
@@ -1131,8 +1131,7 @@
"sector_size=%u > PAGE_SIZE, PIO may malfunction\n",
sdev->sector_size);
- blk_queue_update_dma_alignment(sdev->request_queue,
- sdev->sector_size - 1);
+ blk_queue_update_dma_alignment(q, sdev->sector_size - 1);
if (dev->flags & ATA_DFLAG_AN)
set_bit(SDEV_EVT_MEDIA_CHANGE, sdev->supported_events);
@@ -1145,6 +1144,8 @@
scsi_adjust_queue_depth(sdev, MSG_SIMPLE_TAG, depth);
}
+ blk_queue_flush_queueable(q, false);
+
dev->sdev = sdev;
return 0;
}
diff --git a/drivers/ata/pata_pcmcia.c b/drivers/ata/pata_pcmcia.c
index 29af660..021abe6 100644
--- a/drivers/ata/pata_pcmcia.c
+++ b/drivers/ata/pata_pcmcia.c
@@ -309,7 +309,7 @@
pcmcia_disable_device(pdev);
}
-static struct pcmcia_device_id pcmcia_devices[] = {
+static const struct pcmcia_device_id pcmcia_devices[] = {
PCMCIA_DEVICE_FUNC_ID(4),
PCMCIA_DEVICE_MANF_CARD(0x0000, 0x0000), /* Corsair */
PCMCIA_DEVICE_MANF_CARD(0x0007, 0x0000), /* Hitachi */
diff --git a/drivers/base/node.c b/drivers/base/node.c
index b3b72d6..793f796 100644
--- a/drivers/base/node.c
+++ b/drivers/base/node.c
@@ -7,6 +7,7 @@
#include <linux/init.h>
#include <linux/mm.h>
#include <linux/memory.h>
+#include <linux/vmstat.h>
#include <linux/node.h>
#include <linux/hugetlb.h>
#include <linux/compaction.h>
@@ -179,11 +180,14 @@
struct sysdev_attribute *attr, char *buf)
{
int nid = dev->id;
- return sprintf(buf,
- "nr_written %lu\n"
- "nr_dirtied %lu\n",
- node_page_state(nid, NR_WRITTEN),
- node_page_state(nid, NR_DIRTIED));
+ int i;
+ int n = 0;
+
+ for (i = 0; i < NR_VM_ZONE_STAT_ITEMS; i++)
+ n += sprintf(buf+n, "%s %lu\n", vmstat_text[i],
+ node_page_state(nid, i));
+
+ return n;
}
static SYSDEV_ATTR(vmstat, S_IRUGO, node_read_vmstat, NULL);
diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig
index 83c32cb..717d6e4 100644
--- a/drivers/block/Kconfig
+++ b/drivers/block/Kconfig
@@ -470,6 +470,27 @@
block device driver. It communicates with a back-end driver
in another domain which drives the actual block device.
+config XEN_BLKDEV_BACKEND
+ tristate "Block-device backend driver"
+ depends on XEN_BACKEND
+ help
+ The block-device backend driver allows the kernel to export its
+ block devices to other guests via a high-performance shared-memory
+ interface.
+
+ The corresponding Linux frontend driver is enabled by the
+ CONFIG_XEN_BLKDEV_FRONTEND configuration option.
+
+ The backend driver attaches itself to a any block device specified
+ in the XenBus configuration. There are no limits to what the block
+ device as long as it has a major and minor.
+
+ If you are compiling a kernel to run in a Xen block backend driver
+ domain (often this is domain 0) you should say Y here. To
+ compile this driver as a module, chose M here: the module
+ will be called xen-blkback.
+
+
config VIRTIO_BLK
tristate "Virtio block driver (EXPERIMENTAL)"
depends on EXPERIMENTAL && VIRTIO
diff --git a/drivers/block/Makefile b/drivers/block/Makefile
index 40528ba..76646e9 100644
--- a/drivers/block/Makefile
+++ b/drivers/block/Makefile
@@ -36,6 +36,7 @@
obj-$(CONFIG_BLK_DEV_HD) += hd.o
obj-$(CONFIG_XEN_BLKDEV_FRONTEND) += xen-blkfront.o
+obj-$(CONFIG_XEN_BLKDEV_BACKEND) += xen-blkback/
obj-$(CONFIG_BLK_DEV_DRBD) += drbd/
obj-$(CONFIG_BLK_DEV_RBD) += rbd.o
diff --git a/drivers/block/cciss.c b/drivers/block/cciss.c
index 9bf1398..8f4ef65 100644
--- a/drivers/block/cciss.c
+++ b/drivers/block/cciss.c
@@ -64,6 +64,10 @@
MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers");
MODULE_VERSION("3.6.26");
MODULE_LICENSE("GPL");
+static int cciss_tape_cmds = 6;
+module_param(cciss_tape_cmds, int, 0644);
+MODULE_PARM_DESC(cciss_tape_cmds,
+ "number of commands to allocate for tape devices (default: 6)");
static DEFINE_MUTEX(cciss_mutex);
static struct proc_dir_entry *proc_cciss;
@@ -194,6 +198,8 @@
static int __devinit cciss_pci_find_memory_BAR(struct pci_dev *pdev,
unsigned long *memory_bar);
static inline u32 cciss_tag_discard_error_bits(ctlr_info_t *h, u32 tag);
+static __devinit int write_driver_ver_to_cfgtable(
+ CfgTable_struct __iomem *cfgtable);
/* performant mode helper functions */
static void calc_bucket_map(int *bucket, int num_buckets, int nsgs,
@@ -556,7 +562,7 @@
#define to_hba(n) container_of(n, struct ctlr_info, dev)
#define to_drv(n) container_of(n, drive_info_struct, dev)
-/* List of controllers which cannot be reset on kexec with reset_devices */
+/* List of controllers which cannot be hard reset on kexec with reset_devices */
static u32 unresettable_controller[] = {
0x324a103C, /* Smart Array P712m */
0x324b103C, /* SmartArray P711m */
@@ -574,23 +580,45 @@
0x409D0E11, /* Smart Array 6400 EM */
};
-static int ctlr_is_resettable(struct ctlr_info *h)
+/* List of controllers which cannot even be soft reset */
+static u32 soft_unresettable_controller[] = {
+ 0x409C0E11, /* Smart Array 6400 */
+ 0x409D0E11, /* Smart Array 6400 EM */
+};
+
+static int ctlr_is_hard_resettable(u32 board_id)
{
int i;
for (i = 0; i < ARRAY_SIZE(unresettable_controller); i++)
- if (unresettable_controller[i] == h->board_id)
+ if (unresettable_controller[i] == board_id)
return 0;
return 1;
}
+static int ctlr_is_soft_resettable(u32 board_id)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(soft_unresettable_controller); i++)
+ if (soft_unresettable_controller[i] == board_id)
+ return 0;
+ return 1;
+}
+
+static int ctlr_is_resettable(u32 board_id)
+{
+ return ctlr_is_hard_resettable(board_id) ||
+ ctlr_is_soft_resettable(board_id);
+}
+
static ssize_t host_show_resettable(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct ctlr_info *h = to_hba(dev);
- return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h));
+ return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id));
}
static DEVICE_ATTR(resettable, S_IRUGO, host_show_resettable, NULL);
@@ -2567,7 +2595,7 @@
}
} else if (cmd_type == TYPE_MSG) {
switch (cmd) {
- case 0: /* ABORT message */
+ case CCISS_ABORT_MSG:
c->Request.CDBLen = 12;
c->Request.Type.Attribute = ATTR_SIMPLE;
c->Request.Type.Direction = XFER_WRITE;
@@ -2577,16 +2605,16 @@
/* buff contains the tag of the command to abort */
memcpy(&c->Request.CDB[4], buff, 8);
break;
- case 1: /* RESET message */
+ case CCISS_RESET_MSG:
c->Request.CDBLen = 16;
c->Request.Type.Attribute = ATTR_SIMPLE;
c->Request.Type.Direction = XFER_NONE;
c->Request.Timeout = 0;
memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
c->Request.CDB[0] = cmd; /* reset */
- c->Request.CDB[1] = 0x03; /* reset a target */
+ c->Request.CDB[1] = CCISS_RESET_TYPE_TARGET;
break;
- case 3: /* No-Op message */
+ case CCISS_NOOP_MSG:
c->Request.CDBLen = 1;
c->Request.Type.Attribute = ATTR_SIMPLE;
c->Request.Type.Direction = XFER_WRITE;
@@ -2615,6 +2643,31 @@
return status;
}
+static int __devinit cciss_send_reset(ctlr_info_t *h, unsigned char *scsi3addr,
+ u8 reset_type)
+{
+ CommandList_struct *c;
+ int return_status;
+
+ c = cmd_alloc(h);
+ if (!c)
+ return -ENOMEM;
+ return_status = fill_cmd(h, c, CCISS_RESET_MSG, NULL, 0, 0,
+ CTLR_LUNID, TYPE_MSG);
+ c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */
+ if (return_status != IO_OK) {
+ cmd_special_free(h, c);
+ return return_status;
+ }
+ c->waiting = NULL;
+ enqueue_cmd_and_start_io(h, c);
+ /* Don't wait for completion, the reset won't complete. Don't free
+ * the command either. This is the last command we will send before
+ * re-initializing everything, so it doesn't matter and won't leak.
+ */
+ return 0;
+}
+
static int check_target_status(ctlr_info_t *h, CommandList_struct *c)
{
switch (c->err_info->ScsiStatus) {
@@ -3461,6 +3514,63 @@
return next_command(h);
}
+/* Some controllers, like p400, will give us one interrupt
+ * after a soft reset, even if we turned interrupts off.
+ * Only need to check for this in the cciss_xxx_discard_completions
+ * functions.
+ */
+static int ignore_bogus_interrupt(ctlr_info_t *h)
+{
+ if (likely(!reset_devices))
+ return 0;
+
+ if (likely(h->interrupts_enabled))
+ return 0;
+
+ dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled "
+ "(known firmware bug.) Ignoring.\n");
+
+ return 1;
+}
+
+static irqreturn_t cciss_intx_discard_completions(int irq, void *dev_id)
+{
+ ctlr_info_t *h = dev_id;
+ unsigned long flags;
+ u32 raw_tag;
+
+ if (ignore_bogus_interrupt(h))
+ return IRQ_NONE;
+
+ if (interrupt_not_for_us(h))
+ return IRQ_NONE;
+ spin_lock_irqsave(&h->lock, flags);
+ while (interrupt_pending(h)) {
+ raw_tag = get_next_completion(h);
+ while (raw_tag != FIFO_EMPTY)
+ raw_tag = next_command(h);
+ }
+ spin_unlock_irqrestore(&h->lock, flags);
+ return IRQ_HANDLED;
+}
+
+static irqreturn_t cciss_msix_discard_completions(int irq, void *dev_id)
+{
+ ctlr_info_t *h = dev_id;
+ unsigned long flags;
+ u32 raw_tag;
+
+ if (ignore_bogus_interrupt(h))
+ return IRQ_NONE;
+
+ spin_lock_irqsave(&h->lock, flags);
+ raw_tag = get_next_completion(h);
+ while (raw_tag != FIFO_EMPTY)
+ raw_tag = next_command(h);
+ spin_unlock_irqrestore(&h->lock, flags);
+ return IRQ_HANDLED;
+}
+
static irqreturn_t do_cciss_intx(int irq, void *dev_id)
{
ctlr_info_t *h = dev_id;
@@ -4078,6 +4188,9 @@
cfg_base_addr_index) + cfg_offset, sizeof(h->cfgtable));
if (!h->cfgtable)
return -ENOMEM;
+ rc = write_driver_ver_to_cfgtable(h->cfgtable);
+ if (rc)
+ return rc;
/* Find performant mode table. */
trans_offset = readl(&h->cfgtable->TransMethodOffset);
h->transtable = remap_pci_mem(pci_resource_start(h->pdev,
@@ -4112,7 +4225,7 @@
static void __devinit cciss_find_board_params(ctlr_info_t *h)
{
cciss_get_max_perf_mode_cmds(h);
- h->nr_cmds = h->max_commands - 4; /* Allow room for some ioctls */
+ h->nr_cmds = h->max_commands - 4 - cciss_tape_cmds;
h->maxsgentries = readl(&(h->cfgtable->MaxSGElements));
/*
* Limit in-command s/g elements to 32 save dma'able memory.
@@ -4348,7 +4461,7 @@
tag = readl(vaddr + SA5_REPLY_PORT_OFFSET);
if ((tag & ~3) == paddr32)
break;
- schedule_timeout_uninterruptible(HZ);
+ msleep(CCISS_POST_RESET_NOOP_TIMEOUT_MSECS);
}
iounmap(vaddr);
@@ -4375,11 +4488,10 @@
return 0;
}
-#define cciss_soft_reset_controller(p) cciss_message(p, 1, 0)
#define cciss_noop(p) cciss_message(p, 3, 0)
static int cciss_controller_hard_reset(struct pci_dev *pdev,
- void * __iomem vaddr, bool use_doorbell)
+ void * __iomem vaddr, u32 use_doorbell)
{
u16 pmcsr;
int pos;
@@ -4390,8 +4502,7 @@
* other way using the doorbell register.
*/
dev_info(&pdev->dev, "using doorbell to reset controller\n");
- writel(DOORBELL_CTLR_RESET, vaddr + SA5_DOORBELL);
- msleep(1000);
+ writel(use_doorbell, vaddr + SA5_DOORBELL);
} else { /* Try to do it the PCI power state way */
/* Quoting from the Open CISS Specification: "The Power
@@ -4422,12 +4533,64 @@
pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
pmcsr |= PCI_D0;
pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr);
-
- msleep(500);
}
return 0;
}
+static __devinit void init_driver_version(char *driver_version, int len)
+{
+ memset(driver_version, 0, len);
+ strncpy(driver_version, "cciss " DRIVER_NAME, len - 1);
+}
+
+static __devinit int write_driver_ver_to_cfgtable(
+ CfgTable_struct __iomem *cfgtable)
+{
+ char *driver_version;
+ int i, size = sizeof(cfgtable->driver_version);
+
+ driver_version = kmalloc(size, GFP_KERNEL);
+ if (!driver_version)
+ return -ENOMEM;
+
+ init_driver_version(driver_version, size);
+ for (i = 0; i < size; i++)
+ writeb(driver_version[i], &cfgtable->driver_version[i]);
+ kfree(driver_version);
+ return 0;
+}
+
+static __devinit void read_driver_ver_from_cfgtable(
+ CfgTable_struct __iomem *cfgtable, unsigned char *driver_ver)
+{
+ int i;
+
+ for (i = 0; i < sizeof(cfgtable->driver_version); i++)
+ driver_ver[i] = readb(&cfgtable->driver_version[i]);
+}
+
+static __devinit int controller_reset_failed(
+ CfgTable_struct __iomem *cfgtable)
+{
+
+ char *driver_ver, *old_driver_ver;
+ int rc, size = sizeof(cfgtable->driver_version);
+
+ old_driver_ver = kmalloc(2 * size, GFP_KERNEL);
+ if (!old_driver_ver)
+ return -ENOMEM;
+ driver_ver = old_driver_ver + size;
+
+ /* After a reset, the 32 bytes of "driver version" in the cfgtable
+ * should have been changed, otherwise we know the reset failed.
+ */
+ init_driver_version(old_driver_ver, size);
+ read_driver_ver_from_cfgtable(cfgtable, driver_ver);
+ rc = !memcmp(driver_ver, old_driver_ver, size);
+ kfree(old_driver_ver);
+ return rc;
+}
+
/* This does a hard reset of the controller using PCI power management
* states or using the doorbell register. */
static __devinit int cciss_kdump_hard_reset_controller(struct pci_dev *pdev)
@@ -4437,10 +4600,10 @@
u64 cfg_base_addr_index;
void __iomem *vaddr;
unsigned long paddr;
- u32 misc_fw_support, active_transport;
+ u32 misc_fw_support;
int rc;
CfgTable_struct __iomem *cfgtable;
- bool use_doorbell;
+ u32 use_doorbell;
u32 board_id;
u16 command_register;
@@ -4464,12 +4627,16 @@
* likely not be happy. Just forbid resetting this conjoined mess.
*/
cciss_lookup_board_id(pdev, &board_id);
- if (board_id == 0x409C0E11 || board_id == 0x409D0E11) {
+ if (!ctlr_is_resettable(board_id)) {
dev_warn(&pdev->dev, "Cannot reset Smart Array 640x "
"due to shared cache module.");
return -ENODEV;
}
+ /* if controller is soft- but not hard resettable... */
+ if (!ctlr_is_hard_resettable(board_id))
+ return -ENOTSUPP; /* try soft reset later. */
+
/* Save the PCI command register */
pci_read_config_word(pdev, 4, &command_register);
/* Turn the board off. This is so that later pci_restore_state()
@@ -4497,16 +4664,28 @@
rc = -ENOMEM;
goto unmap_vaddr;
}
+ rc = write_driver_ver_to_cfgtable(cfgtable);
+ if (rc)
+ goto unmap_vaddr;
- /* If reset via doorbell register is supported, use that. */
- misc_fw_support = readl(&cfgtable->misc_fw_support);
- use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET;
-
- /* The doorbell reset seems to cause lockups on some Smart
- * Arrays (e.g. P410, P410i, maybe others). Until this is
- * fixed or at least isolated, avoid the doorbell reset.
+ /* If reset via doorbell register is supported, use that.
+ * There are two such methods. Favor the newest method.
*/
- use_doorbell = 0;
+ misc_fw_support = readl(&cfgtable->misc_fw_support);
+ use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2;
+ if (use_doorbell) {
+ use_doorbell = DOORBELL_CTLR_RESET2;
+ } else {
+ use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET;
+ if (use_doorbell) {
+ dev_warn(&pdev->dev, "Controller claims that "
+ "'Bit 2 doorbell reset' is "
+ "supported, but not 'bit 5 doorbell reset'. "
+ "Firmware update is recommended.\n");
+ rc = -ENOTSUPP; /* use the soft reset */
+ goto unmap_cfgtable;
+ }
+ }
rc = cciss_controller_hard_reset(pdev, vaddr, use_doorbell);
if (rc)
@@ -4524,30 +4703,31 @@
msleep(CCISS_POST_RESET_PAUSE_MSECS);
/* Wait for board to become not ready, then ready. */
- dev_info(&pdev->dev, "Waiting for board to become ready.\n");
+ dev_info(&pdev->dev, "Waiting for board to reset.\n");
rc = cciss_wait_for_board_state(pdev, vaddr, BOARD_NOT_READY);
- if (rc) /* Don't bail, might be E500, etc. which can't be reset */
- dev_warn(&pdev->dev,
- "failed waiting for board to become not ready\n");
+ if (rc) {
+ dev_warn(&pdev->dev, "Failed waiting for board to hard reset."
+ " Will try soft reset.\n");
+ rc = -ENOTSUPP; /* Not expected, but try soft reset later */
+ goto unmap_cfgtable;
+ }
rc = cciss_wait_for_board_state(pdev, vaddr, BOARD_READY);
if (rc) {
dev_warn(&pdev->dev,
- "failed waiting for board to become ready\n");
+ "failed waiting for board to become ready "
+ "after hard reset\n");
goto unmap_cfgtable;
}
- dev_info(&pdev->dev, "board ready.\n");
- /* Controller should be in simple mode at this point. If it's not,
- * It means we're on one of those controllers which doesn't support
- * the doorbell reset method and on which the PCI power management reset
- * method doesn't work (P800, for example.)
- * In those cases, don't try to proceed, as it generally doesn't work.
- */
- active_transport = readl(&cfgtable->TransportActive);
- if (active_transport & PERFORMANT_MODE) {
- dev_warn(&pdev->dev, "Unable to successfully reset controller,"
- " Ignoring controller.\n");
- rc = -ENODEV;
+ rc = controller_reset_failed(vaddr);
+ if (rc < 0)
+ goto unmap_cfgtable;
+ if (rc) {
+ dev_warn(&pdev->dev, "Unable to successfully hard reset "
+ "controller. Will try soft reset.\n");
+ rc = -ENOTSUPP; /* Not expected, but try soft reset later */
+ } else {
+ dev_info(&pdev->dev, "Board ready after hard reset.\n");
}
unmap_cfgtable:
@@ -4574,11 +4754,12 @@
* due to concerns about shared bbwc between 6402/6404 pair.
*/
if (rc == -ENOTSUPP)
- return 0; /* just try to do the kdump anyhow. */
+ return rc; /* just try to do the kdump anyhow. */
if (rc)
return -ENODEV;
/* Now try to get the controller to respond to a no-op */
+ dev_warn(&pdev->dev, "Waiting for controller to respond to no-op\n");
for (i = 0; i < CCISS_POST_RESET_NOOP_RETRIES; i++) {
if (cciss_noop(pdev) == 0)
break;
@@ -4591,6 +4772,148 @@
return 0;
}
+static __devinit int cciss_allocate_cmd_pool(ctlr_info_t *h)
+{
+ h->cmd_pool_bits = kmalloc(
+ DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG) *
+ sizeof(unsigned long), GFP_KERNEL);
+ h->cmd_pool = pci_alloc_consistent(h->pdev,
+ h->nr_cmds * sizeof(CommandList_struct),
+ &(h->cmd_pool_dhandle));
+ h->errinfo_pool = pci_alloc_consistent(h->pdev,
+ h->nr_cmds * sizeof(ErrorInfo_struct),
+ &(h->errinfo_pool_dhandle));
+ if ((h->cmd_pool_bits == NULL)
+ || (h->cmd_pool == NULL)
+ || (h->errinfo_pool == NULL)) {
+ dev_err(&h->pdev->dev, "out of memory");
+ return -ENOMEM;
+ }
+ return 0;
+}
+
+static __devinit int cciss_allocate_scatterlists(ctlr_info_t *h)
+{
+ int i;
+
+ /* zero it, so that on free we need not know how many were alloc'ed */
+ h->scatter_list = kzalloc(h->max_commands *
+ sizeof(struct scatterlist *), GFP_KERNEL);
+ if (!h->scatter_list)
+ return -ENOMEM;
+
+ for (i = 0; i < h->nr_cmds; i++) {
+ h->scatter_list[i] = kmalloc(sizeof(struct scatterlist) *
+ h->maxsgentries, GFP_KERNEL);
+ if (h->scatter_list[i] == NULL) {
+ dev_err(&h->pdev->dev, "could not allocate "
+ "s/g lists\n");
+ return -ENOMEM;
+ }
+ }
+ return 0;
+}
+
+static void cciss_free_scatterlists(ctlr_info_t *h)
+{
+ int i;
+
+ if (h->scatter_list) {
+ for (i = 0; i < h->nr_cmds; i++)
+ kfree(h->scatter_list[i]);
+ kfree(h->scatter_list);
+ }
+}
+
+static void cciss_free_cmd_pool(ctlr_info_t *h)
+{
+ kfree(h->cmd_pool_bits);
+ if (h->cmd_pool)
+ pci_free_consistent(h->pdev,
+ h->nr_cmds * sizeof(CommandList_struct),
+ h->cmd_pool, h->cmd_pool_dhandle);
+ if (h->errinfo_pool)
+ pci_free_consistent(h->pdev,
+ h->nr_cmds * sizeof(ErrorInfo_struct),
+ h->errinfo_pool, h->errinfo_pool_dhandle);
+}
+
+static int cciss_request_irq(ctlr_info_t *h,
+ irqreturn_t (*msixhandler)(int, void *),
+ irqreturn_t (*intxhandler)(int, void *))
+{
+ if (h->msix_vector || h->msi_vector) {
+ if (!request_irq(h->intr[PERF_MODE_INT], msixhandler,
+ IRQF_DISABLED, h->devname, h))
+ return 0;
+ dev_err(&h->pdev->dev, "Unable to get msi irq %d"
+ " for %s\n", h->intr[PERF_MODE_INT],
+ h->devname);
+ return -1;
+ }
+
+ if (!request_irq(h->intr[PERF_MODE_INT], intxhandler,
+ IRQF_DISABLED, h->devname, h))
+ return 0;
+ dev_err(&h->pdev->dev, "Unable to get irq %d for %s\n",
+ h->intr[PERF_MODE_INT], h->devname);
+ return -1;
+}
+
+static int __devinit cciss_kdump_soft_reset(ctlr_info_t *h)
+{
+ if (cciss_send_reset(h, CTLR_LUNID, CCISS_RESET_TYPE_CONTROLLER)) {
+ dev_warn(&h->pdev->dev, "Resetting array controller failed.\n");
+ return -EIO;
+ }
+
+ dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n");
+ if (cciss_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY)) {
+ dev_warn(&h->pdev->dev, "Soft reset had no effect.\n");
+ return -1;
+ }
+
+ dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n");
+ if (cciss_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY)) {
+ dev_warn(&h->pdev->dev, "Board failed to become ready "
+ "after soft reset.\n");
+ return -1;
+ }
+
+ return 0;
+}
+
+static void cciss_undo_allocations_after_kdump_soft_reset(ctlr_info_t *h)
+{
+ int ctlr = h->ctlr;
+
+ free_irq(h->intr[PERF_MODE_INT], h);
+#ifdef CONFIG_PCI_MSI
+ if (h->msix_vector)
+ pci_disable_msix(h->pdev);
+ else if (h->msi_vector)
+ pci_disable_msi(h->pdev);
+#endif /* CONFIG_PCI_MSI */
+ cciss_free_sg_chain_blocks(h->cmd_sg_list, h->nr_cmds);
+ cciss_free_scatterlists(h);
+ cciss_free_cmd_pool(h);
+ kfree(h->blockFetchTable);
+ if (h->reply_pool)
+ pci_free_consistent(h->pdev, h->max_commands * sizeof(__u64),
+ h->reply_pool, h->reply_pool_dhandle);
+ if (h->transtable)
+ iounmap(h->transtable);
+ if (h->cfgtable)
+ iounmap(h->cfgtable);
+ if (h->vaddr)
+ iounmap(h->vaddr);
+ unregister_blkdev(h->major, h->devname);
+ cciss_destroy_hba_sysfs_entry(h);
+ pci_release_regions(h->pdev);
+ kfree(h);
+ hba[ctlr] = NULL;
+}
+
/*
* This is it. Find all the controllers and register them. I really hate
* stealing all these major device numbers.
@@ -4601,15 +4924,28 @@
{
int i;
int j = 0;
- int k = 0;
int rc;
+ int try_soft_reset = 0;
int dac, return_code;
InquiryData_struct *inq_buff;
ctlr_info_t *h;
+ unsigned long flags;
rc = cciss_init_reset_devices(pdev);
- if (rc)
- return rc;
+ if (rc) {
+ if (rc != -ENOTSUPP)
+ return rc;
+ /* If the reset fails in a particular way (it has no way to do
+ * a proper hard reset, so returns -ENOTSUPP) we can try to do
+ * a soft reset once we get the controller configured up to the
+ * point that it can accept a command.
+ */
+ try_soft_reset = 1;
+ rc = 0;
+ }
+
+reinit_after_soft_reset:
+
i = alloc_cciss_hba(pdev);
if (i < 0)
return -1;
@@ -4627,6 +4963,11 @@
sprintf(h->devname, "cciss%d", i);
h->ctlr = i;
+ if (cciss_tape_cmds < 2)
+ cciss_tape_cmds = 2;
+ if (cciss_tape_cmds > 16)
+ cciss_tape_cmds = 16;
+
init_completion(&h->scan_wait);
if (cciss_create_hba_sysfs_entry(h))
@@ -4662,62 +5003,20 @@
/* make sure the board interrupts are off */
h->access.set_intr_mask(h, CCISS_INTR_OFF);
- if (h->msi_vector || h->msix_vector) {
- if (request_irq(h->intr[PERF_MODE_INT],
- do_cciss_msix_intr,
- IRQF_DISABLED, h->devname, h)) {
- dev_err(&h->pdev->dev, "Unable to get irq %d for %s\n",
- h->intr[PERF_MODE_INT], h->devname);
- goto clean2;
- }
- } else {
- if (request_irq(h->intr[PERF_MODE_INT], do_cciss_intx,
- IRQF_DISABLED, h->devname, h)) {
- dev_err(&h->pdev->dev, "Unable to get irq %d for %s\n",
- h->intr[PERF_MODE_INT], h->devname);
- goto clean2;
- }
- }
+ rc = cciss_request_irq(h, do_cciss_msix_intr, do_cciss_intx);
+ if (rc)
+ goto clean2;
dev_info(&h->pdev->dev, "%s: <0x%x> at PCI %s IRQ %d%s using DAC\n",
h->devname, pdev->device, pci_name(pdev),
h->intr[PERF_MODE_INT], dac ? "" : " not");
- h->cmd_pool_bits =
- kmalloc(DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG)
- * sizeof(unsigned long), GFP_KERNEL);
- h->cmd_pool = (CommandList_struct *)
- pci_alloc_consistent(h->pdev,
- h->nr_cmds * sizeof(CommandList_struct),
- &(h->cmd_pool_dhandle));
- h->errinfo_pool = (ErrorInfo_struct *)
- pci_alloc_consistent(h->pdev,
- h->nr_cmds * sizeof(ErrorInfo_struct),
- &(h->errinfo_pool_dhandle));
- if ((h->cmd_pool_bits == NULL)
- || (h->cmd_pool == NULL)
- || (h->errinfo_pool == NULL)) {
- dev_err(&h->pdev->dev, "out of memory");
- goto clean4;
- }
-
- /* Need space for temp scatter list */
- h->scatter_list = kmalloc(h->max_commands *
- sizeof(struct scatterlist *),
- GFP_KERNEL);
- if (!h->scatter_list)
+ if (cciss_allocate_cmd_pool(h))
goto clean4;
- for (k = 0; k < h->nr_cmds; k++) {
- h->scatter_list[k] = kmalloc(sizeof(struct scatterlist) *
- h->maxsgentries,
- GFP_KERNEL);
- if (h->scatter_list[k] == NULL) {
- dev_err(&h->pdev->dev,
- "could not allocate s/g lists\n");
- goto clean4;
- }
- }
+ if (cciss_allocate_scatterlists(h))
+ goto clean4;
+
h->cmd_sg_list = cciss_allocate_sg_chain_blocks(h,
h->chainsize, h->nr_cmds);
if (!h->cmd_sg_list && h->chainsize > 0)
@@ -4741,6 +5040,62 @@
h->gendisk[j] = NULL;
}
+ /* At this point, the controller is ready to take commands.
+ * Now, if reset_devices and the hard reset didn't work, try
+ * the soft reset and see if that works.
+ */
+ if (try_soft_reset) {
+
+ /* This is kind of gross. We may or may not get a completion
+ * from the soft reset command, and if we do, then the value
+ * from the fifo may or may not be valid. So, we wait 10 secs
+ * after the reset throwing away any completions we get during
+ * that time. Unregister the interrupt handler and register
+ * fake ones to scoop up any residual completions.
+ */
+ spin_lock_irqsave(&h->lock, flags);
+ h->access.set_intr_mask(h, CCISS_INTR_OFF);
+ spin_unlock_irqrestore(&h->lock, flags);
+ free_irq(h->intr[PERF_MODE_INT], h);
+ rc = cciss_request_irq(h, cciss_msix_discard_completions,
+ cciss_intx_discard_completions);
+ if (rc) {
+ dev_warn(&h->pdev->dev, "Failed to request_irq after "
+ "soft reset.\n");
+ goto clean4;
+ }
+
+ rc = cciss_kdump_soft_reset(h);
+ if (rc) {
+ dev_warn(&h->pdev->dev, "Soft reset failed.\n");
+ goto clean4;
+ }
+
+ dev_info(&h->pdev->dev, "Board READY.\n");
+ dev_info(&h->pdev->dev,
+ "Waiting for stale completions to drain.\n");
+ h->access.set_intr_mask(h, CCISS_INTR_ON);
+ msleep(10000);
+ h->access.set_intr_mask(h, CCISS_INTR_OFF);
+
+ rc = controller_reset_failed(h->cfgtable);
+ if (rc)
+ dev_info(&h->pdev->dev,
+ "Soft reset appears to have failed.\n");
+
+ /* since the controller's reset, we have to go back and re-init
+ * everything. Easiest to just forget what we've done and do it
+ * all over again.
+ */
+ cciss_undo_allocations_after_kdump_soft_reset(h);
+ try_soft_reset = 0;
+ if (rc)
+ /* don't go to clean4, we already unallocated */
+ return -ENODEV;
+
+ goto reinit_after_soft_reset;
+ }
+
cciss_scsi_setup(h);
/* Turn the interrupts on so we can service requests */
@@ -4775,21 +5130,9 @@
return 1;
clean4:
- kfree(h->cmd_pool_bits);
- /* Free up sg elements */
- for (k-- ; k >= 0; k--)
- kfree(h->scatter_list[k]);
- kfree(h->scatter_list);
+ cciss_free_cmd_pool(h);
+ cciss_free_scatterlists(h);
cciss_free_sg_chain_blocks(h->cmd_sg_list, h->nr_cmds);
- if (h->cmd_pool)
- pci_free_consistent(h->pdev,
- h->nr_cmds * sizeof(CommandList_struct),
- h->cmd_pool, h->cmd_pool_dhandle);
- if (h->errinfo_pool)
- pci_free_consistent(h->pdev,
- h->nr_cmds * sizeof(ErrorInfo_struct),
- h->errinfo_pool,
- h->errinfo_pool_dhandle);
free_irq(h->intr[PERF_MODE_INT], h);
clean2:
unregister_blkdev(h->major, h->devname);
@@ -4887,16 +5230,16 @@
iounmap(h->cfgtable);
iounmap(h->vaddr);
- pci_free_consistent(h->pdev, h->nr_cmds * sizeof(CommandList_struct),
- h->cmd_pool, h->cmd_pool_dhandle);
- pci_free_consistent(h->pdev, h->nr_cmds * sizeof(ErrorInfo_struct),
- h->errinfo_pool, h->errinfo_pool_dhandle);
- kfree(h->cmd_pool_bits);
+ cciss_free_cmd_pool(h);
/* Free up sg elements */
for (j = 0; j < h->nr_cmds; j++)
kfree(h->scatter_list[j]);
kfree(h->scatter_list);
cciss_free_sg_chain_blocks(h->cmd_sg_list, h->nr_cmds);
+ kfree(h->blockFetchTable);
+ if (h->reply_pool)
+ pci_free_consistent(h->pdev, h->max_commands * sizeof(__u64),
+ h->reply_pool, h->reply_pool_dhandle);
/*
* Deliberately omit pci_disable_device(): it does something nasty to
* Smart Array controllers that pci_enable_device does not undo
diff --git a/drivers/block/cciss.h b/drivers/block/cciss.h
index 554bbd9..16b4d58 100644
--- a/drivers/block/cciss.h
+++ b/drivers/block/cciss.h
@@ -200,7 +200,7 @@
* the above.
*/
#define CCISS_BOARD_READY_WAIT_SECS (120)
-#define CCISS_BOARD_NOT_READY_WAIT_SECS (10)
+#define CCISS_BOARD_NOT_READY_WAIT_SECS (100)
#define CCISS_BOARD_READY_POLL_INTERVAL_MSECS (100)
#define CCISS_BOARD_READY_ITERATIONS \
((CCISS_BOARD_READY_WAIT_SECS * 1000) / \
@@ -209,8 +209,9 @@
((CCISS_BOARD_NOT_READY_WAIT_SECS * 1000) / \
CCISS_BOARD_READY_POLL_INTERVAL_MSECS)
#define CCISS_POST_RESET_PAUSE_MSECS (3000)
-#define CCISS_POST_RESET_NOOP_INTERVAL_MSECS (1000)
+#define CCISS_POST_RESET_NOOP_INTERVAL_MSECS (4000)
#define CCISS_POST_RESET_NOOP_RETRIES (12)
+#define CCISS_POST_RESET_NOOP_TIMEOUT_MSECS (10000)
/*
Send the command to the hardware
@@ -239,11 +240,13 @@
{ /* Turn interrupts on */
h->interrupts_enabled = 1;
writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
+ (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
} else /* Turn them off */
{
h->interrupts_enabled = 0;
writel( SA5_INTR_OFF,
h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
+ (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
}
}
/*
@@ -257,11 +260,13 @@
{ /* Turn interrupts on */
h->interrupts_enabled = 1;
writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
+ (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
} else /* Turn them off */
{
h->interrupts_enabled = 0;
writel( SA5B_INTR_OFF,
h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
+ (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
}
}
@@ -271,10 +276,12 @@
if (val) { /* turn on interrupts */
h->interrupts_enabled = 1;
writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
+ (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
} else {
h->interrupts_enabled = 0;
writel(SA5_PERF_INTR_OFF,
h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
+ (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
}
}
diff --git a/drivers/block/cciss_cmd.h b/drivers/block/cciss_cmd.h
index cd441be..d9be6b4 100644
--- a/drivers/block/cciss_cmd.h
+++ b/drivers/block/cciss_cmd.h
@@ -53,6 +53,7 @@
#define CFGTBL_ChangeReq 0x00000001l
#define CFGTBL_AccCmds 0x00000001l
#define DOORBELL_CTLR_RESET 0x00000004l
+#define DOORBELL_CTLR_RESET2 0x00000020l
#define CFGTBL_Trans_Simple 0x00000002l
#define CFGTBL_Trans_Performant 0x00000004l
@@ -142,6 +143,14 @@
#define BMIC_CACHE_FLUSH 0xc2
#define CCISS_CACHE_FLUSH 0x01 /* C2 was already being used by CCISS */
+#define CCISS_ABORT_MSG 0x00
+#define CCISS_RESET_MSG 0x01
+#define CCISS_RESET_TYPE_CONTROLLER 0x00
+#define CCISS_RESET_TYPE_BUS 0x01
+#define CCISS_RESET_TYPE_TARGET 0x03
+#define CCISS_RESET_TYPE_LUN 0x04
+#define CCISS_NOOP_MSG 0x03
+
/* Command List Structure */
#define CTLR_LUNID "\0\0\0\0\0\0\0\0"
@@ -235,6 +244,8 @@
u8 reserved[0x78 - 0x58];
u32 misc_fw_support; /* offset 0x78 */
#define MISC_FW_DOORBELL_RESET (0x02)
+#define MISC_FW_DOORBELL_RESET2 (0x10)
+ u8 driver_version[32];
} CfgTable_struct;
struct TransTable_struct {
diff --git a/drivers/block/cciss_scsi.c b/drivers/block/cciss_scsi.c
index df79380..6961002 100644
--- a/drivers/block/cciss_scsi.c
+++ b/drivers/block/cciss_scsi.c
@@ -84,7 +84,6 @@
.proc_name = "cciss",
.proc_info = cciss_scsi_proc_info,
.queuecommand = cciss_scsi_queue_command,
- .can_queue = SCSI_CCISS_CAN_QUEUE,
.this_id = 7,
.cmd_per_lun = 1,
.use_clustering = DISABLE_CLUSTERING,
@@ -108,16 +107,13 @@
#pragma pack()
-#define CMD_STACK_SIZE (SCSI_CCISS_CAN_QUEUE * \
- CCISS_MAX_SCSI_DEVS_PER_HBA + 2)
- // plus two for init time usage
-
#pragma pack(1)
struct cciss_scsi_cmd_stack_t {
struct cciss_scsi_cmd_stack_elem_t *pool;
- struct cciss_scsi_cmd_stack_elem_t *elem[CMD_STACK_SIZE];
+ struct cciss_scsi_cmd_stack_elem_t **elem;
dma_addr_t cmd_pool_handle;
int top;
+ int nelems;
};
#pragma pack()
@@ -191,7 +187,7 @@
sa = h->scsi_ctlr;
stk = &sa->cmd_stack;
stk->top++;
- if (stk->top >= CMD_STACK_SIZE) {
+ if (stk->top >= stk->nelems) {
dev_err(&h->pdev->dev,
"scsi_cmd_free called too many times.\n");
BUG();
@@ -206,13 +202,14 @@
struct cciss_scsi_cmd_stack_t *stk;
size_t size;
+ stk = &sa->cmd_stack;
+ stk->nelems = cciss_tape_cmds + 2;
sa->cmd_sg_list = cciss_allocate_sg_chain_blocks(h,
- h->chainsize, CMD_STACK_SIZE);
+ h->chainsize, stk->nelems);
if (!sa->cmd_sg_list && h->chainsize > 0)
return -ENOMEM;
- stk = &sa->cmd_stack;
- size = sizeof(struct cciss_scsi_cmd_stack_elem_t) * CMD_STACK_SIZE;
+ size = sizeof(struct cciss_scsi_cmd_stack_elem_t) * stk->nelems;
/* Check alignment, see cciss_cmd.h near CommandList_struct def. */
BUILD_BUG_ON((sizeof(*stk->pool) % COMMANDLIST_ALIGNMENT) != 0);
@@ -221,18 +218,23 @@
pci_alloc_consistent(h->pdev, size, &stk->cmd_pool_handle);
if (stk->pool == NULL) {
- cciss_free_sg_chain_blocks(sa->cmd_sg_list, CMD_STACK_SIZE);
+ cciss_free_sg_chain_blocks(sa->cmd_sg_list, stk->nelems);
sa->cmd_sg_list = NULL;
return -ENOMEM;
}
-
- for (i=0; i<CMD_STACK_SIZE; i++) {
+ stk->elem = kmalloc(sizeof(stk->elem[0]) * stk->nelems, GFP_KERNEL);
+ if (!stk->elem) {
+ pci_free_consistent(h->pdev, size, stk->pool,
+ stk->cmd_pool_handle);
+ return -1;
+ }
+ for (i = 0; i < stk->nelems; i++) {
stk->elem[i] = &stk->pool[i];
stk->elem[i]->busaddr = (__u32) (stk->cmd_pool_handle +
(sizeof(struct cciss_scsi_cmd_stack_elem_t) * i));
stk->elem[i]->cmdindex = i;
}
- stk->top = CMD_STACK_SIZE-1;
+ stk->top = stk->nelems-1;
return 0;
}
@@ -245,16 +247,18 @@
sa = h->scsi_ctlr;
stk = &sa->cmd_stack;
- if (stk->top != CMD_STACK_SIZE-1) {
+ if (stk->top != stk->nelems-1) {
dev_warn(&h->pdev->dev,
"bug: %d scsi commands are still outstanding.\n",
- CMD_STACK_SIZE - stk->top);
+ stk->nelems - stk->top);
}
- size = sizeof(struct cciss_scsi_cmd_stack_elem_t) * CMD_STACK_SIZE;
+ size = sizeof(struct cciss_scsi_cmd_stack_elem_t) * stk->nelems;
pci_free_consistent(h->pdev, size, stk->pool, stk->cmd_pool_handle);
stk->pool = NULL;
- cciss_free_sg_chain_blocks(sa->cmd_sg_list, CMD_STACK_SIZE);
+ cciss_free_sg_chain_blocks(sa->cmd_sg_list, stk->nelems);
+ kfree(stk->elem);
+ stk->elem = NULL;
}
#if 0
@@ -859,6 +863,7 @@
sh->io_port = 0; // good enough? FIXME,
sh->n_io_port = 0; // I don't think we use these two...
sh->this_id = SELF_SCSI_ID;
+ sh->can_queue = cciss_tape_cmds;
sh->sg_tablesize = h->maxsgentries;
sh->max_cmd_len = MAX_COMMAND_SIZE;
diff --git a/drivers/block/cciss_scsi.h b/drivers/block/cciss_scsi.h
index 6d5822f..e71d986 100644
--- a/drivers/block/cciss_scsi.h
+++ b/drivers/block/cciss_scsi.h
@@ -36,13 +36,9 @@
addressible natively, and may in fact turn
out to be not scsi at all. */
-#define SCSI_CCISS_CAN_QUEUE 2
/*
-Note, cmd_per_lun could give us some trouble, so I'm setting it very low.
-Likewise, SCSI_CCISS_CAN_QUEUE is set very conservatively.
-
If the upper scsi layer tries to track how many commands we have
outstanding, it will be operating under the misapprehension that it is
the only one sending us requests. We also have the block interface,
diff --git a/drivers/block/drbd/drbd_actlog.c b/drivers/block/drbd/drbd_actlog.c
index c6828b6..09ef9a8 100644
--- a/drivers/block/drbd/drbd_actlog.c
+++ b/drivers/block/drbd/drbd_actlog.c
@@ -28,7 +28,7 @@
#include "drbd_int.h"
#include "drbd_wrappers.h"
-/* We maintain a trivial check sum in our on disk activity log.
+/* We maintain a trivial checksum in our on disk activity log.
* With that we can ensure correct operation even when the storage
* device might do a partial (last) sector write while losing power.
*/
diff --git a/drivers/block/drbd/drbd_bitmap.c b/drivers/block/drbd/drbd_bitmap.c
index 76210ba..f440a02 100644
--- a/drivers/block/drbd/drbd_bitmap.c
+++ b/drivers/block/drbd/drbd_bitmap.c
@@ -74,7 +74,7 @@
* as we are "attached" to a local disk, which at 32 GiB for 1PiB storage
* seems excessive.
*
- * We plan to reduce the amount of in-core bitmap pages by pageing them in
+ * We plan to reduce the amount of in-core bitmap pages by paging them in
* and out against their on-disk location as necessary, but need to make
* sure we don't cause too much meta data IO, and must not deadlock in
* tight memory situations. This needs some more work.
@@ -200,7 +200,7 @@
* we if bits have been cleared since last IO. */
#define BM_PAGE_LAZY_WRITEOUT 28
-/* store_page_idx uses non-atomic assingment. It is only used directly after
+/* store_page_idx uses non-atomic assignment. It is only used directly after
* allocating the page. All other bm_set_page_* and bm_clear_page_* need to
* use atomic bit manipulation, as set_out_of_sync (and therefore bitmap
* changes) may happen from various contexts, and wait_on_bit/wake_up_bit
@@ -318,7 +318,7 @@
/* word offset from start of bitmap to word number _in_page_
* modulo longs per page
#define MLPP(X) ((X) % (PAGE_SIZE/sizeof(long))
- hm, well, Philipp thinks gcc might not optimze the % into & (... - 1)
+ hm, well, Philipp thinks gcc might not optimize the % into & (... - 1)
so do it explicitly:
*/
#define MLPP(X) ((X) & ((PAGE_SIZE/sizeof(long))-1))
diff --git a/drivers/block/drbd/drbd_int.h b/drivers/block/drbd/drbd_int.h
index d871b14..ef2ceed 100644
--- a/drivers/block/drbd/drbd_int.h
+++ b/drivers/block/drbd/drbd_int.h
@@ -700,7 +700,7 @@
* see drbd_endio_pri(). */
struct bio *private_bio;
- struct hlist_node colision;
+ struct hlist_node collision;
sector_t sector;
unsigned int size;
unsigned int epoch; /* barrier_nr */
@@ -766,7 +766,7 @@
struct drbd_epoch_entry {
struct drbd_work w;
- struct hlist_node colision;
+ struct hlist_node collision;
struct drbd_epoch *epoch; /* for writes */
struct drbd_conf *mdev;
struct page *pages;
@@ -1129,6 +1129,8 @@
int rs_in_flight; /* resync sectors in flight (to proxy, in proxy and from proxy) */
int rs_planed; /* resync sectors already planned */
atomic_t ap_in_flight; /* App sectors in flight (waiting for ack) */
+ int peer_max_bio_size;
+ int local_max_bio_size;
};
static inline struct drbd_conf *minor_to_mdev(unsigned int minor)
@@ -1218,8 +1220,6 @@
extern void tl_release(struct drbd_conf *mdev, unsigned int barrier_nr,
unsigned int set_size);
extern void tl_clear(struct drbd_conf *mdev);
-enum drbd_req_event;
-extern void tl_restart(struct drbd_conf *mdev, enum drbd_req_event what);
extern void _tl_add_barrier(struct drbd_conf *, struct drbd_tl_epoch *);
extern void drbd_free_sock(struct drbd_conf *mdev);
extern int drbd_send(struct drbd_conf *mdev, struct socket *sock,
@@ -1434,6 +1434,7 @@
* hash table. */
#define HT_SHIFT 8
#define DRBD_MAX_BIO_SIZE (1U<<(9+HT_SHIFT))
+#define DRBD_MAX_BIO_SIZE_SAFE (1 << 12) /* Works always = 4k */
#define DRBD_MAX_SIZE_H80_PACKET (1 << 15) /* The old header only allows packets up to 32Kib data */
@@ -1518,9 +1519,9 @@
extern char *ppsize(char *buf, unsigned long long size);
extern sector_t drbd_new_dev_size(struct drbd_conf *, struct drbd_backing_dev *, int);
enum determine_dev_size { dev_size_error = -1, unchanged = 0, shrunk = 1, grew = 2 };
-extern enum determine_dev_size drbd_determin_dev_size(struct drbd_conf *, enum dds_flags) __must_hold(local);
+extern enum determine_dev_size drbd_determine_dev_size(struct drbd_conf *, enum dds_flags) __must_hold(local);
extern void resync_after_online_grow(struct drbd_conf *);
-extern void drbd_setup_queue_param(struct drbd_conf *mdev, unsigned int) __must_hold(local);
+extern void drbd_reconsider_max_bio_size(struct drbd_conf *mdev);
extern enum drbd_state_rv drbd_set_role(struct drbd_conf *mdev,
enum drbd_role new_role,
int force);
@@ -1828,6 +1829,8 @@
if (!forcedetach) {
if (__ratelimit(&drbd_ratelimit_state))
dev_err(DEV, "Local IO failed in %s.\n", where);
+ if (mdev->state.disk > D_INCONSISTENT)
+ _drbd_set_state(_NS(mdev, disk, D_INCONSISTENT), CS_HARD, NULL);
break;
}
/* NOTE fall through to detach case if forcedetach set */
@@ -2153,6 +2156,10 @@
static inline void put_ldev(struct drbd_conf *mdev)
{
int i = atomic_dec_return(&mdev->local_cnt);
+
+ /* This may be called from some endio handler,
+ * so we must not sleep here. */
+
__release(local);
D_ASSERT(i >= 0);
if (i == 0) {
diff --git a/drivers/block/drbd/drbd_main.c b/drivers/block/drbd/drbd_main.c
index 5b525c1..0358e55 100644
--- a/drivers/block/drbd/drbd_main.c
+++ b/drivers/block/drbd/drbd_main.c
@@ -745,6 +745,9 @@
mdev->agreed_pro_version < 88)
rv = SS_NOT_SUPPORTED;
+ else if (ns.conn >= C_CONNECTED && ns.pdsk == D_UNKNOWN)
+ rv = SS_CONNECTED_OUTDATES;
+
return rv;
}
@@ -1565,6 +1568,10 @@
put_ldev(mdev);
}
+ /* Notify peer that I had a local IO error, and did not detached.. */
+ if (os.disk == D_UP_TO_DATE && ns.disk == D_INCONSISTENT)
+ drbd_send_state(mdev);
+
/* Disks got bigger while they were detached */
if (ns.disk > D_NEGOTIATING && ns.pdsk > D_NEGOTIATING &&
test_and_clear_bit(RESYNC_AFTER_NEG, &mdev->flags)) {
@@ -2064,7 +2071,7 @@
{
struct p_sizes p;
sector_t d_size, u_size;
- int q_order_type;
+ int q_order_type, max_bio_size;
int ok;
if (get_ldev_if_state(mdev, D_NEGOTIATING)) {
@@ -2072,17 +2079,20 @@
d_size = drbd_get_max_capacity(mdev->ldev);
u_size = mdev->ldev->dc.disk_size;
q_order_type = drbd_queue_order_type(mdev);
+ max_bio_size = queue_max_hw_sectors(mdev->ldev->backing_bdev->bd_disk->queue) << 9;
+ max_bio_size = min_t(int, max_bio_size, DRBD_MAX_BIO_SIZE);
put_ldev(mdev);
} else {
d_size = 0;
u_size = 0;
q_order_type = QUEUE_ORDERED_NONE;
+ max_bio_size = DRBD_MAX_BIO_SIZE; /* ... multiple BIOs per peer_request */
}
p.d_size = cpu_to_be64(d_size);
p.u_size = cpu_to_be64(u_size);
p.c_size = cpu_to_be64(trigger_reply ? 0 : drbd_get_capacity(mdev->this_bdev));
- p.max_bio_size = cpu_to_be32(queue_max_hw_sectors(mdev->rq_queue) << 9);
+ p.max_bio_size = cpu_to_be32(max_bio_size);
p.queue_order_type = cpu_to_be16(q_order_type);
p.dds_flags = cpu_to_be16(flags);
@@ -2722,7 +2732,7 @@
/* double check digest, sometimes buffers have been modified in flight. */
if (dgs > 0 && dgs <= 64) {
- /* 64 byte, 512 bit, is the larges digest size
+ /* 64 byte, 512 bit, is the largest digest size
* currently supported in kernel crypto. */
unsigned char digest[64];
drbd_csum_bio(mdev, mdev->integrity_w_tfm, req->master_bio, digest);
@@ -3041,6 +3051,8 @@
mdev->agreed_pro_version = PRO_VERSION_MAX;
mdev->write_ordering = WO_bdev_flush;
mdev->resync_wenr = LC_FREE;
+ mdev->peer_max_bio_size = DRBD_MAX_BIO_SIZE_SAFE;
+ mdev->local_max_bio_size = DRBD_MAX_BIO_SIZE_SAFE;
}
void drbd_mdev_cleanup(struct drbd_conf *mdev)
@@ -3275,7 +3287,7 @@
drbd_release_ee_lists(mdev);
- /* should be free'd on disconnect? */
+ /* should be freed on disconnect? */
kfree(mdev->ee_hash);
/*
mdev->ee_hash_s = 0;
@@ -3415,7 +3427,9 @@
q->backing_dev_info.congested_data = mdev;
blk_queue_make_request(q, drbd_make_request);
- blk_queue_max_hw_sectors(q, DRBD_MAX_BIO_SIZE >> 9);
+ /* Setting the max_hw_sectors to an odd value of 8kibyte here
+ This triggers a max_bio_size message upon first attach or connect */
+ blk_queue_max_hw_sectors(q, DRBD_MAX_BIO_SIZE_SAFE >> 8);
blk_queue_bounce_limit(q, BLK_BOUNCE_ANY);
blk_queue_merge_bvec(q, drbd_merge_bvec);
q->queue_lock = &mdev->req_lock;
@@ -3627,7 +3641,8 @@
/* `-- act_log->nr_elements <-- sync_conf.al_extents */
u32 bm_offset; /* offset to the bitmap, from here */
u32 bm_bytes_per_bit; /* BM_BLOCK_SIZE */
- u32 reserved_u32[4];
+ u32 la_peer_max_bio_size; /* last peer max_bio_size */
+ u32 reserved_u32[3];
} __packed;
@@ -3668,6 +3683,7 @@
buffer->device_uuid = cpu_to_be64(mdev->ldev->md.device_uuid);
buffer->bm_offset = cpu_to_be32(mdev->ldev->md.bm_offset);
+ buffer->la_peer_max_bio_size = cpu_to_be32(mdev->peer_max_bio_size);
D_ASSERT(drbd_md_ss__(mdev, mdev->ldev) == mdev->ldev->md.md_offset);
sector = mdev->ldev->md.md_offset;
@@ -3751,6 +3767,15 @@
mdev->sync_conf.al_extents = be32_to_cpu(buffer->al_nr_extents);
bdev->md.device_uuid = be64_to_cpu(buffer->device_uuid);
+ spin_lock_irq(&mdev->req_lock);
+ if (mdev->state.conn < C_CONNECTED) {
+ int peer;
+ peer = be32_to_cpu(buffer->la_peer_max_bio_size);
+ peer = max_t(int, peer, DRBD_MAX_BIO_SIZE_SAFE);
+ mdev->peer_max_bio_size = peer;
+ }
+ spin_unlock_irq(&mdev->req_lock);
+
if (mdev->sync_conf.al_extents < 7)
mdev->sync_conf.al_extents = 127;
diff --git a/drivers/block/drbd/drbd_nl.c b/drivers/block/drbd/drbd_nl.c
index 03b29f7..515bcd9 100644
--- a/drivers/block/drbd/drbd_nl.c
+++ b/drivers/block/drbd/drbd_nl.c
@@ -272,9 +272,28 @@
{
struct drbd_conf *mdev = (struct drbd_conf *)data;
enum drbd_disk_state nps;
+ union drbd_state ns;
nps = drbd_try_outdate_peer(mdev);
- drbd_request_state(mdev, NS(pdsk, nps));
+
+ /* Not using
+ drbd_request_state(mdev, NS(pdsk, nps));
+ here, because we might were able to re-establish the connection
+ in the meantime. This can only partially be solved in the state's
+ engine is_valid_state() and is_valid_state_transition()
+ functions.
+
+ nps can be D_INCONSISTENT, D_OUTDATED or D_UNKNOWN.
+ pdsk == D_INCONSISTENT while conn >= C_CONNECTED is valid,
+ therefore we have to have the pre state change check here.
+ */
+ spin_lock_irq(&mdev->req_lock);
+ ns = mdev->state;
+ if (ns.conn < C_WF_REPORT_PARAMS) {
+ ns.pdsk = nps;
+ _drbd_set_state(mdev, ns, CS_VERBOSE, NULL);
+ }
+ spin_unlock_irq(&mdev->req_lock);
return 0;
}
@@ -577,7 +596,7 @@
* Returns 0 on success, negative return values indicate errors.
* You should call drbd_md_sync() after calling this function.
*/
-enum determine_dev_size drbd_determin_dev_size(struct drbd_conf *mdev, enum dds_flags flags) __must_hold(local)
+enum determine_dev_size drbd_determine_dev_size(struct drbd_conf *mdev, enum dds_flags flags) __must_hold(local)
{
sector_t prev_first_sect, prev_size; /* previous meta location */
sector_t la_size;
@@ -773,30 +792,78 @@
return 0;
}
-void drbd_setup_queue_param(struct drbd_conf *mdev, unsigned int max_bio_size) __must_hold(local)
+static void drbd_setup_queue_param(struct drbd_conf *mdev, unsigned int max_bio_size)
{
struct request_queue * const q = mdev->rq_queue;
- struct request_queue * const b = mdev->ldev->backing_bdev->bd_disk->queue;
- int max_segments = mdev->ldev->dc.max_bio_bvecs;
- int max_hw_sectors = min(queue_max_hw_sectors(b), max_bio_size >> 9);
+ int max_hw_sectors = max_bio_size >> 9;
+ int max_segments = 0;
+
+ if (get_ldev_if_state(mdev, D_ATTACHING)) {
+ struct request_queue * const b = mdev->ldev->backing_bdev->bd_disk->queue;
+
+ max_hw_sectors = min(queue_max_hw_sectors(b), max_bio_size >> 9);
+ max_segments = mdev->ldev->dc.max_bio_bvecs;
+ put_ldev(mdev);
+ }
blk_queue_logical_block_size(q, 512);
blk_queue_max_hw_sectors(q, max_hw_sectors);
/* This is the workaround for "bio would need to, but cannot, be split" */
blk_queue_max_segments(q, max_segments ? max_segments : BLK_MAX_SEGMENTS);
blk_queue_segment_boundary(q, PAGE_CACHE_SIZE-1);
- blk_queue_stack_limits(q, b);
- dev_info(DEV, "max BIO size = %u\n", queue_max_hw_sectors(q) << 9);
+ if (get_ldev_if_state(mdev, D_ATTACHING)) {
+ struct request_queue * const b = mdev->ldev->backing_bdev->bd_disk->queue;
- if (q->backing_dev_info.ra_pages != b->backing_dev_info.ra_pages) {
- dev_info(DEV, "Adjusting my ra_pages to backing device's (%lu -> %lu)\n",
- q->backing_dev_info.ra_pages,
- b->backing_dev_info.ra_pages);
- q->backing_dev_info.ra_pages = b->backing_dev_info.ra_pages;
+ blk_queue_stack_limits(q, b);
+
+ if (q->backing_dev_info.ra_pages != b->backing_dev_info.ra_pages) {
+ dev_info(DEV, "Adjusting my ra_pages to backing device's (%lu -> %lu)\n",
+ q->backing_dev_info.ra_pages,
+ b->backing_dev_info.ra_pages);
+ q->backing_dev_info.ra_pages = b->backing_dev_info.ra_pages;
+ }
+ put_ldev(mdev);
}
}
+void drbd_reconsider_max_bio_size(struct drbd_conf *mdev)
+{
+ int now, new, local, peer;
+
+ now = queue_max_hw_sectors(mdev->rq_queue) << 9;
+ local = mdev->local_max_bio_size; /* Eventually last known value, from volatile memory */
+ peer = mdev->peer_max_bio_size; /* Eventually last known value, from meta data */
+
+ if (get_ldev_if_state(mdev, D_ATTACHING)) {
+ local = queue_max_hw_sectors(mdev->ldev->backing_bdev->bd_disk->queue) << 9;
+ mdev->local_max_bio_size = local;
+ put_ldev(mdev);
+ }
+
+ /* We may ignore peer limits if the peer is modern enough.
+ Because new from 8.3.8 onwards the peer can use multiple
+ BIOs for a single peer_request */
+ if (mdev->state.conn >= C_CONNECTED) {
+ if (mdev->agreed_pro_version < 94)
+ peer = mdev->peer_max_bio_size;
+ else if (mdev->agreed_pro_version == 94)
+ peer = DRBD_MAX_SIZE_H80_PACKET;
+ else /* drbd 8.3.8 onwards */
+ peer = DRBD_MAX_BIO_SIZE;
+ }
+
+ new = min_t(int, local, peer);
+
+ if (mdev->state.role == R_PRIMARY && new < now)
+ dev_err(DEV, "ASSERT FAILED new < now; (%d < %d)\n", new, now);
+
+ if (new != now)
+ dev_info(DEV, "max BIO size = %u\n", new);
+
+ drbd_setup_queue_param(mdev, new);
+}
+
/* serialize deconfig (worker exiting, doing cleanup)
* and reconfig (drbdsetup disk, drbdsetup net)
*
@@ -865,7 +932,6 @@
struct block_device *bdev;
struct lru_cache *resync_lru = NULL;
union drbd_state ns, os;
- unsigned int max_bio_size;
enum drbd_state_rv rv;
int cp_discovered = 0;
int logical_block_size;
@@ -1117,20 +1183,7 @@
mdev->read_cnt = 0;
mdev->writ_cnt = 0;
- max_bio_size = DRBD_MAX_BIO_SIZE;
- if (mdev->state.conn == C_CONNECTED) {
- /* We are Primary, Connected, and now attach a new local
- * backing store. We must not increase the user visible maximum
- * bio size on this device to something the peer may not be
- * able to handle. */
- if (mdev->agreed_pro_version < 94)
- max_bio_size = queue_max_hw_sectors(mdev->rq_queue) << 9;
- else if (mdev->agreed_pro_version == 94)
- max_bio_size = DRBD_MAX_SIZE_H80_PACKET;
- /* else: drbd 8.3.9 and later, stay with default */
- }
-
- drbd_setup_queue_param(mdev, max_bio_size);
+ drbd_reconsider_max_bio_size(mdev);
/* If I am currently not R_PRIMARY,
* but meta data primary indicator is set,
@@ -1152,7 +1205,7 @@
!drbd_md_test_flag(mdev->ldev, MDF_CONNECTED_IND))
set_bit(USE_DEGR_WFC_T, &mdev->flags);
- dd = drbd_determin_dev_size(mdev, 0);
+ dd = drbd_determine_dev_size(mdev, 0);
if (dd == dev_size_error) {
retcode = ERR_NOMEM_BITMAP;
goto force_diskless_dec;
@@ -1281,11 +1334,19 @@
static int drbd_nl_detach(struct drbd_conf *mdev, struct drbd_nl_cfg_req *nlp,
struct drbd_nl_cfg_reply *reply)
{
+ enum drbd_ret_code retcode;
+ int ret;
drbd_suspend_io(mdev); /* so no-one is stuck in drbd_al_begin_io */
- reply->ret_code = drbd_request_state(mdev, NS(disk, D_DISKLESS));
- if (mdev->state.disk == D_DISKLESS)
- wait_event(mdev->misc_wait, !atomic_read(&mdev->local_cnt));
+ retcode = drbd_request_state(mdev, NS(disk, D_FAILED));
+ /* D_FAILED will transition to DISKLESS. */
+ ret = wait_event_interruptible(mdev->misc_wait,
+ mdev->state.disk != D_FAILED);
drbd_resume_io(mdev);
+ if ((int)retcode == (int)SS_IS_DISKLESS)
+ retcode = SS_NOTHING_TO_DO;
+ if (ret)
+ retcode = ERR_INTR;
+ reply->ret_code = retcode;
return 0;
}
@@ -1658,7 +1719,7 @@
mdev->ldev->dc.disk_size = (sector_t)rs.resize_size;
ddsf = (rs.resize_force ? DDSF_FORCED : 0) | (rs.no_resync ? DDSF_NO_RESYNC : 0);
- dd = drbd_determin_dev_size(mdev, ddsf);
+ dd = drbd_determine_dev_size(mdev, ddsf);
drbd_md_sync(mdev);
put_ldev(mdev);
if (dd == dev_size_error) {
diff --git a/drivers/block/drbd/drbd_receiver.c b/drivers/block/drbd/drbd_receiver.c
index fd26666..25d32c5 100644
--- a/drivers/block/drbd/drbd_receiver.c
+++ b/drivers/block/drbd/drbd_receiver.c
@@ -333,7 +333,7 @@
if (!page)
goto fail;
- INIT_HLIST_NODE(&e->colision);
+ INIT_HLIST_NODE(&e->collision);
e->epoch = NULL;
e->mdev = mdev;
e->pages = page;
@@ -356,7 +356,7 @@
kfree(e->digest);
drbd_pp_free(mdev, e->pages, is_net);
D_ASSERT(atomic_read(&e->pending_bios) == 0);
- D_ASSERT(hlist_unhashed(&e->colision));
+ D_ASSERT(hlist_unhashed(&e->collision));
mempool_free(e, drbd_ee_mempool);
}
@@ -787,7 +787,7 @@
}
if (sock && msock) {
- schedule_timeout_interruptible(HZ / 10);
+ schedule_timeout_interruptible(mdev->net_conf->ping_timeo*HZ/10);
ok = drbd_socket_okay(mdev, &sock);
ok = drbd_socket_okay(mdev, &msock) && ok;
if (ok)
@@ -899,11 +899,6 @@
drbd_thread_start(&mdev->asender);
- if (mdev->agreed_pro_version < 95 && get_ldev(mdev)) {
- drbd_setup_queue_param(mdev, DRBD_MAX_SIZE_H80_PACKET);
- put_ldev(mdev);
- }
-
if (drbd_send_protocol(mdev) == -1)
return -1;
drbd_send_sync_param(mdev, &mdev->sync_conf);
@@ -1418,7 +1413,7 @@
sector_t sector = e->sector;
int ok;
- D_ASSERT(hlist_unhashed(&e->colision));
+ D_ASSERT(hlist_unhashed(&e->collision));
if (likely((e->flags & EE_WAS_ERROR) == 0)) {
drbd_set_in_sync(mdev, sector, e->size);
@@ -1487,7 +1482,7 @@
return false;
}
- /* hlist_del(&req->colision) is done in _req_may_be_done, to avoid
+ /* hlist_del(&req->collision) is done in _req_may_be_done, to avoid
* special casing it there for the various failure cases.
* still no race with drbd_fail_pending_reads */
ok = recv_dless_read(mdev, req, sector, data_size);
@@ -1558,11 +1553,11 @@
* P_WRITE_ACK / P_NEG_ACK, to get the sequence number right. */
if (mdev->net_conf->two_primaries) {
spin_lock_irq(&mdev->req_lock);
- D_ASSERT(!hlist_unhashed(&e->colision));
- hlist_del_init(&e->colision);
+ D_ASSERT(!hlist_unhashed(&e->collision));
+ hlist_del_init(&e->collision);
spin_unlock_irq(&mdev->req_lock);
} else {
- D_ASSERT(hlist_unhashed(&e->colision));
+ D_ASSERT(hlist_unhashed(&e->collision));
}
drbd_may_finish_epoch(mdev, e->epoch, EV_PUT + (cancel ? EV_CLEANUP : 0));
@@ -1579,8 +1574,8 @@
ok = drbd_send_ack(mdev, P_DISCARD_ACK, e);
spin_lock_irq(&mdev->req_lock);
- D_ASSERT(!hlist_unhashed(&e->colision));
- hlist_del_init(&e->colision);
+ D_ASSERT(!hlist_unhashed(&e->collision));
+ hlist_del_init(&e->collision);
spin_unlock_irq(&mdev->req_lock);
dec_unacked(mdev);
@@ -1755,7 +1750,7 @@
spin_lock_irq(&mdev->req_lock);
- hlist_add_head(&e->colision, ee_hash_slot(mdev, sector));
+ hlist_add_head(&e->collision, ee_hash_slot(mdev, sector));
#define OVERLAPS overlaps(i->sector, i->size, sector, size)
slot = tl_hash_slot(mdev, sector);
@@ -1765,7 +1760,7 @@
int have_conflict = 0;
prepare_to_wait(&mdev->misc_wait, &wait,
TASK_INTERRUPTIBLE);
- hlist_for_each_entry(i, n, slot, colision) {
+ hlist_for_each_entry(i, n, slot, collision) {
if (OVERLAPS) {
/* only ALERT on first iteration,
* we may be woken up early... */
@@ -1804,7 +1799,7 @@
}
if (signal_pending(current)) {
- hlist_del_init(&e->colision);
+ hlist_del_init(&e->collision);
spin_unlock_irq(&mdev->req_lock);
@@ -1862,7 +1857,7 @@
dev_err(DEV, "submit failed, triggering re-connect\n");
spin_lock_irq(&mdev->req_lock);
list_del(&e->w.list);
- hlist_del_init(&e->colision);
+ hlist_del_init(&e->collision);
spin_unlock_irq(&mdev->req_lock);
if (e->flags & EE_CALL_AL_COMPLETE_IO)
drbd_al_complete_io(mdev, e->sector);
@@ -2916,12 +2911,6 @@
return false;
}
-static void drbd_setup_order_type(struct drbd_conf *mdev, int peer)
-{
- /* sorry, we currently have no working implementation
- * of distributed TCQ */
-}
-
/* warn if the arguments differ by more than 12.5% */
static void warn_if_differ_considerably(struct drbd_conf *mdev,
const char *s, sector_t a, sector_t b)
@@ -2939,7 +2928,6 @@
{
struct p_sizes *p = &mdev->data.rbuf.sizes;
enum determine_dev_size dd = unchanged;
- unsigned int max_bio_size;
sector_t p_size, p_usize, my_usize;
int ldsc = 0; /* local disk size changed */
enum dds_flags ddsf;
@@ -2994,7 +2982,7 @@
ddsf = be16_to_cpu(p->dds_flags);
if (get_ldev(mdev)) {
- dd = drbd_determin_dev_size(mdev, ddsf);
+ dd = drbd_determine_dev_size(mdev, ddsf);
put_ldev(mdev);
if (dd == dev_size_error)
return false;
@@ -3004,23 +2992,15 @@
drbd_set_my_capacity(mdev, p_size);
}
+ mdev->peer_max_bio_size = be32_to_cpu(p->max_bio_size);
+ drbd_reconsider_max_bio_size(mdev);
+
if (get_ldev(mdev)) {
if (mdev->ldev->known_size != drbd_get_capacity(mdev->ldev->backing_bdev)) {
mdev->ldev->known_size = drbd_get_capacity(mdev->ldev->backing_bdev);
ldsc = 1;
}
- if (mdev->agreed_pro_version < 94)
- max_bio_size = be32_to_cpu(p->max_bio_size);
- else if (mdev->agreed_pro_version == 94)
- max_bio_size = DRBD_MAX_SIZE_H80_PACKET;
- else /* drbd 8.3.8 onwards */
- max_bio_size = DRBD_MAX_BIO_SIZE;
-
- if (max_bio_size != queue_max_hw_sectors(mdev->rq_queue) << 9)
- drbd_setup_queue_param(mdev, max_bio_size);
-
- drbd_setup_order_type(mdev, be16_to_cpu(p->queue_order_type));
put_ldev(mdev);
}
@@ -4275,7 +4255,7 @@
struct hlist_node *n;
struct drbd_request *req;
- hlist_for_each_entry(req, n, slot, colision) {
+ hlist_for_each_entry(req, n, slot, collision) {
if ((unsigned long)req == (unsigned long)id) {
if (req->sector != sector) {
dev_err(DEV, "_ack_id_to_req: found req %p but it has "
@@ -4554,6 +4534,7 @@
int received = 0;
int expect = sizeof(struct p_header80);
int empty;
+ int ping_timeout_active = 0;
sprintf(current->comm, "drbd%d_asender", mdev_to_minor(mdev));
@@ -4566,6 +4547,7 @@
ERR_IF(!drbd_send_ping(mdev)) goto reconnect;
mdev->meta.socket->sk->sk_rcvtimeo =
mdev->net_conf->ping_timeo*HZ/10;
+ ping_timeout_active = 1;
}
/* conditionally cork;
@@ -4620,8 +4602,7 @@
dev_err(DEV, "meta connection shut down by peer.\n");
goto reconnect;
} else if (rv == -EAGAIN) {
- if (mdev->meta.socket->sk->sk_rcvtimeo ==
- mdev->net_conf->ping_timeo*HZ/10) {
+ if (ping_timeout_active) {
dev_err(DEV, "PingAck did not arrive in time.\n");
goto reconnect;
}
@@ -4660,6 +4641,11 @@
if (!cmd->process(mdev, h))
goto reconnect;
+ /* the idle_timeout (ping-int)
+ * has been restored in got_PingAck() */
+ if (cmd == get_asender_cmd(P_PING_ACK))
+ ping_timeout_active = 0;
+
buf = h;
received = 0;
expect = sizeof(struct p_header80);
diff --git a/drivers/block/drbd/drbd_req.c b/drivers/block/drbd/drbd_req.c
index 5c0c8be..3424d67 100644
--- a/drivers/block/drbd/drbd_req.c
+++ b/drivers/block/drbd/drbd_req.c
@@ -163,7 +163,7 @@
* they must have been failed on the spot */
#define OVERLAPS overlaps(sector, size, i->sector, i->size)
slot = tl_hash_slot(mdev, sector);
- hlist_for_each_entry(i, n, slot, colision) {
+ hlist_for_each_entry(i, n, slot, collision) {
if (OVERLAPS) {
dev_alert(DEV, "LOGIC BUG: completed: %p %llus +%u; "
"other: %p %llus +%u\n",
@@ -187,7 +187,7 @@
#undef OVERLAPS
#define OVERLAPS overlaps(sector, size, e->sector, e->size)
slot = ee_hash_slot(mdev, req->sector);
- hlist_for_each_entry(e, n, slot, colision) {
+ hlist_for_each_entry(e, n, slot, collision) {
if (OVERLAPS) {
wake_up(&mdev->misc_wait);
break;
@@ -260,8 +260,8 @@
/* remove the request from the conflict detection
* respective block_id verification hash */
- if (!hlist_unhashed(&req->colision))
- hlist_del(&req->colision);
+ if (!hlist_unhashed(&req->collision))
+ hlist_del(&req->collision);
else
D_ASSERT((s & (RQ_NET_MASK & ~RQ_NET_DONE)) == 0);
@@ -329,7 +329,7 @@
struct hlist_node *n;
struct hlist_head *slot;
- D_ASSERT(hlist_unhashed(&req->colision));
+ D_ASSERT(hlist_unhashed(&req->collision));
if (!get_net_conf(mdev))
return 0;
@@ -341,7 +341,7 @@
#define OVERLAPS overlaps(i->sector, i->size, sector, size)
slot = tl_hash_slot(mdev, sector);
- hlist_for_each_entry(i, n, slot, colision) {
+ hlist_for_each_entry(i, n, slot, collision) {
if (OVERLAPS) {
dev_alert(DEV, "%s[%u] Concurrent local write detected! "
"[DISCARD L] new: %llus +%u; "
@@ -359,7 +359,7 @@
#undef OVERLAPS
#define OVERLAPS overlaps(e->sector, e->size, sector, size)
slot = ee_hash_slot(mdev, sector);
- hlist_for_each_entry(e, n, slot, colision) {
+ hlist_for_each_entry(e, n, slot, collision) {
if (OVERLAPS) {
dev_alert(DEV, "%s[%u] Concurrent remote write detected!"
" [DISCARD L] new: %llus +%u; "
@@ -491,7 +491,7 @@
/* so we can verify the handle in the answer packet
* corresponding hlist_del is in _req_may_be_done() */
- hlist_add_head(&req->colision, ar_hash_slot(mdev, req->sector));
+ hlist_add_head(&req->collision, ar_hash_slot(mdev, req->sector));
set_bit(UNPLUG_REMOTE, &mdev->flags);
@@ -507,7 +507,7 @@
/* assert something? */
/* from drbd_make_request_common only */
- hlist_add_head(&req->colision, tl_hash_slot(mdev, req->sector));
+ hlist_add_head(&req->collision, tl_hash_slot(mdev, req->sector));
/* corresponding hlist_del is in _req_may_be_done() */
/* NOTE
@@ -1033,7 +1033,7 @@
err = 0;
fail_free_complete:
- if (rw == WRITE && local)
+ if (req->rq_state & RQ_IN_ACT_LOG)
drbd_al_complete_io(mdev, sector);
fail_and_free_req:
if (local) {
diff --git a/drivers/block/drbd/drbd_req.h b/drivers/block/drbd/drbd_req.h
index 32e2c3e..68a234a 100644
--- a/drivers/block/drbd/drbd_req.h
+++ b/drivers/block/drbd/drbd_req.h
@@ -256,7 +256,7 @@
struct hlist_node *n;
struct drbd_request *req;
- hlist_for_each_entry(req, n, slot, colision) {
+ hlist_for_each_entry(req, n, slot, collision) {
if ((unsigned long)req == (unsigned long)id) {
D_ASSERT(req->sector == sector);
return req;
@@ -291,7 +291,7 @@
req->epoch = 0;
req->sector = bio_src->bi_sector;
req->size = bio_src->bi_size;
- INIT_HLIST_NODE(&req->colision);
+ INIT_HLIST_NODE(&req->collision);
INIT_LIST_HEAD(&req->tl_requests);
INIT_LIST_HEAD(&req->w.list);
}
@@ -323,6 +323,7 @@
extern void complete_master_bio(struct drbd_conf *mdev,
struct bio_and_error *m);
extern void request_timer_fn(unsigned long data);
+extern void tl_restart(struct drbd_conf *mdev, enum drbd_req_event what);
/* use this if you don't want to deal with calling complete_master_bio()
* outside the spinlock, e.g. when walking some list on cleanup. */
diff --git a/drivers/block/drbd/drbd_worker.c b/drivers/block/drbd/drbd_worker.c
index f7e6c92..4d76b06 100644
--- a/drivers/block/drbd/drbd_worker.c
+++ b/drivers/block/drbd/drbd_worker.c
@@ -126,7 +126,7 @@
list_del(&e->w.list); /* has been on active_ee or sync_ee */
list_add_tail(&e->w.list, &mdev->done_ee);
- /* No hlist_del_init(&e->colision) here, we did not send the Ack yet,
+ /* No hlist_del_init(&e->collision) here, we did not send the Ack yet,
* neither did we wake possibly waiting conflicting requests.
* done from "drbd_process_done_ee" within the appropriate w.cb
* (e_end_block/e_end_resync_block) or from _drbd_clear_done_ee */
@@ -297,42 +297,48 @@
crypto_hash_final(&desc, digest);
}
-static int w_e_send_csum(struct drbd_conf *mdev, struct drbd_work *w, int cancel)
+/* TODO merge common code with w_e_end_ov_req */
+int w_e_send_csum(struct drbd_conf *mdev, struct drbd_work *w, int cancel)
{
struct drbd_epoch_entry *e = container_of(w, struct drbd_epoch_entry, w);
int digest_size;
void *digest;
- int ok;
+ int ok = 1;
D_ASSERT(e->block_id == DRBD_MAGIC + 0xbeef);
- if (unlikely(cancel)) {
+ if (unlikely(cancel))
+ goto out;
+
+ if (likely((e->flags & EE_WAS_ERROR) != 0))
+ goto out;
+
+ digest_size = crypto_hash_digestsize(mdev->csums_tfm);
+ digest = kmalloc(digest_size, GFP_NOIO);
+ if (digest) {
+ sector_t sector = e->sector;
+ unsigned int size = e->size;
+ drbd_csum_ee(mdev, mdev->csums_tfm, e, digest);
+ /* Free e and pages before send.
+ * In case we block on congestion, we could otherwise run into
+ * some distributed deadlock, if the other side blocks on
+ * congestion as well, because our receiver blocks in
+ * drbd_pp_alloc due to pp_in_use > max_buffers. */
drbd_free_ee(mdev, e);
- return 1;
+ e = NULL;
+ inc_rs_pending(mdev);
+ ok = drbd_send_drequest_csum(mdev, sector, size,
+ digest, digest_size,
+ P_CSUM_RS_REQUEST);
+ kfree(digest);
+ } else {
+ dev_err(DEV, "kmalloc() of digest failed.\n");
+ ok = 0;
}
- if (likely((e->flags & EE_WAS_ERROR) == 0)) {
- digest_size = crypto_hash_digestsize(mdev->csums_tfm);
- digest = kmalloc(digest_size, GFP_NOIO);
- if (digest) {
- drbd_csum_ee(mdev, mdev->csums_tfm, e, digest);
-
- inc_rs_pending(mdev);
- ok = drbd_send_drequest_csum(mdev,
- e->sector,
- e->size,
- digest,
- digest_size,
- P_CSUM_RS_REQUEST);
- kfree(digest);
- } else {
- dev_err(DEV, "kmalloc() of digest failed.\n");
- ok = 0;
- }
- } else
- ok = 1;
-
- drbd_free_ee(mdev, e);
+out:
+ if (e)
+ drbd_free_ee(mdev, e);
if (unlikely(!ok))
dev_err(DEV, "drbd_send_drequest(..., csum) failed\n");
@@ -834,7 +840,7 @@
const int ratio =
(t == 0) ? 0 :
(t < 100000) ? ((s*100)/t) : (s/(t/100));
- dev_info(DEV, "%u %% had equal check sums, eliminated: %luK; "
+ dev_info(DEV, "%u %% had equal checksums, eliminated: %luK; "
"transferred %luK total %luK\n",
ratio,
Bit2KB(mdev->rs_same_csum),
@@ -1071,9 +1077,12 @@
return ok;
}
+/* TODO merge common code with w_e_send_csum */
int w_e_end_ov_req(struct drbd_conf *mdev, struct drbd_work *w, int cancel)
{
struct drbd_epoch_entry *e = container_of(w, struct drbd_epoch_entry, w);
+ sector_t sector = e->sector;
+ unsigned int size = e->size;
int digest_size;
void *digest;
int ok = 1;
@@ -1093,17 +1102,25 @@
else
memset(digest, 0, digest_size);
+ /* Free e and pages before send.
+ * In case we block on congestion, we could otherwise run into
+ * some distributed deadlock, if the other side blocks on
+ * congestion as well, because our receiver blocks in
+ * drbd_pp_alloc due to pp_in_use > max_buffers. */
+ drbd_free_ee(mdev, e);
+ e = NULL;
inc_rs_pending(mdev);
- ok = drbd_send_drequest_csum(mdev, e->sector, e->size,
- digest, digest_size, P_OV_REPLY);
+ ok = drbd_send_drequest_csum(mdev, sector, size,
+ digest, digest_size,
+ P_OV_REPLY);
if (!ok)
dec_rs_pending(mdev);
kfree(digest);
out:
- drbd_free_ee(mdev, e);
+ if (e)
+ drbd_free_ee(mdev, e);
dec_unacked(mdev);
-
return ok;
}
@@ -1122,8 +1139,10 @@
{
struct drbd_epoch_entry *e = container_of(w, struct drbd_epoch_entry, w);
struct digest_info *di;
- int digest_size;
void *digest;
+ sector_t sector = e->sector;
+ unsigned int size = e->size;
+ int digest_size;
int ok, eq = 0;
if (unlikely(cancel)) {
@@ -1153,16 +1172,21 @@
}
}
- dec_unacked(mdev);
+ /* Free e and pages before send.
+ * In case we block on congestion, we could otherwise run into
+ * some distributed deadlock, if the other side blocks on
+ * congestion as well, because our receiver blocks in
+ * drbd_pp_alloc due to pp_in_use > max_buffers. */
+ drbd_free_ee(mdev, e);
if (!eq)
- drbd_ov_oos_found(mdev, e->sector, e->size);
+ drbd_ov_oos_found(mdev, sector, size);
else
ov_oos_print(mdev);
- ok = drbd_send_ack_ex(mdev, P_OV_RESULT, e->sector, e->size,
+ ok = drbd_send_ack_ex(mdev, P_OV_RESULT, sector, size,
eq ? ID_IN_SYNC : ID_OUT_OF_SYNC);
- drbd_free_ee(mdev, e);
+ dec_unacked(mdev);
--mdev->ov_left;
diff --git a/drivers/block/loop.c b/drivers/block/loop.c
index a076a14..c59a672 100644
--- a/drivers/block/loop.c
+++ b/drivers/block/loop.c
@@ -1658,7 +1658,7 @@
struct kobject *kobj;
mutex_lock(&loop_devices_mutex);
- lo = loop_init_one(dev & MINORMASK);
+ lo = loop_init_one(MINOR(dev) >> part_shift);
kobj = lo ? get_disk(lo->lo_disk) : ERR_PTR(-ENOMEM);
mutex_unlock(&loop_devices_mutex);
@@ -1691,15 +1691,18 @@
if (max_part > 0)
part_shift = fls(max_part);
+ if ((1UL << part_shift) > DISK_MAX_PARTS)
+ return -EINVAL;
+
if (max_loop > 1UL << (MINORBITS - part_shift))
return -EINVAL;
if (max_loop) {
nr = max_loop;
- range = max_loop;
+ range = max_loop << part_shift;
} else {
nr = 8;
- range = 1UL << (MINORBITS - part_shift);
+ range = 1UL << MINORBITS;
}
if (register_blkdev(LOOP_MAJOR, "loop"))
@@ -1738,7 +1741,7 @@
unsigned long range;
struct loop_device *lo, *next;
- range = max_loop ? max_loop : 1UL << (MINORBITS - part_shift);
+ range = max_loop ? max_loop << part_shift : 1UL << MINORBITS;
list_for_each_entry_safe(lo, next, &loop_devices, lo_list)
loop_del_one(lo);
diff --git a/drivers/block/paride/pcd.c b/drivers/block/paride/pcd.c
index 8690e31..a0aabd9 100644
--- a/drivers/block/paride/pcd.c
+++ b/drivers/block/paride/pcd.c
@@ -320,6 +320,8 @@
disk->first_minor = unit;
strcpy(disk->disk_name, cd->name); /* umm... */
disk->fops = &pcd_bdops;
+ disk->flags = GENHD_FL_BLOCK_EVENTS_ON_EXCL_WRITE;
+ disk->events = DISK_EVENT_MEDIA_CHANGE;
}
}
diff --git a/drivers/block/rbd.c b/drivers/block/rbd.c
index 9712fad..1278098 100644
--- a/drivers/block/rbd.c
+++ b/drivers/block/rbd.c
@@ -1191,14 +1191,19 @@
static void rbd_watch_cb(u64 ver, u64 notify_id, u8 opcode, void *data)
{
struct rbd_device *dev = (struct rbd_device *)data;
+ int rc;
+
if (!dev)
return;
dout("rbd_watch_cb %s notify_id=%lld opcode=%d\n", dev->obj_md_name,
notify_id, (int)opcode);
mutex_lock_nested(&ctl_mutex, SINGLE_DEPTH_NESTING);
- __rbd_update_snaps(dev);
+ rc = __rbd_update_snaps(dev);
mutex_unlock(&ctl_mutex);
+ if (rc)
+ pr_warning(DRV_NAME "%d got notification but failed to update"
+ " snaps: %d\n", dev->major, rc);
rbd_req_sync_notify_ack(dev, ver, notify_id, dev->obj_md_name);
}
@@ -1597,7 +1602,7 @@
int name_len = strlen(snap_name);
u64 new_snapid;
int ret;
- void *data, *data_start, *data_end;
+ void *data, *p, *e;
u64 ver;
/* we should create a snapshot only if we're pointing at the head */
@@ -1614,16 +1619,16 @@
if (!data)
return -ENOMEM;
- data_start = data;
- data_end = data + name_len + 16;
+ p = data;
+ e = data + name_len + 16;
- ceph_encode_string_safe(&data, data_end, snap_name, name_len, bad);
- ceph_encode_64_safe(&data, data_end, new_snapid, bad);
+ ceph_encode_string_safe(&p, e, snap_name, name_len, bad);
+ ceph_encode_64_safe(&p, e, new_snapid, bad);
ret = rbd_req_sync_exec(dev, dev->obj_md_name, "rbd", "snap_add",
- data_start, data - data_start, &ver);
+ data, p - data, &ver);
- kfree(data_start);
+ kfree(data);
if (ret < 0)
return ret;
@@ -1659,6 +1664,9 @@
if (ret < 0)
return ret;
+ /* resized? */
+ set_capacity(rbd_dev->disk, h.image_size / 512ULL);
+
down_write(&rbd_dev->header.snap_rwsem);
snap_seq = rbd_dev->header.snapc->seq;
@@ -1716,7 +1724,8 @@
if (!disk)
goto out;
- sprintf(disk->disk_name, DRV_NAME "%d", rbd_dev->id);
+ snprintf(disk->disk_name, sizeof(disk->disk_name), DRV_NAME "%d",
+ rbd_dev->id);
disk->major = rbd_dev->major;
disk->first_minor = 0;
disk->fops = &rbd_bd_ops;
diff --git a/drivers/block/xen-blkback/Makefile b/drivers/block/xen-blkback/Makefile
new file mode 100644
index 0000000..e491c1b
--- /dev/null
+++ b/drivers/block/xen-blkback/Makefile
@@ -0,0 +1,3 @@
+obj-$(CONFIG_XEN_BLKDEV_BACKEND) := xen-blkback.o
+
+xen-blkback-y := blkback.o xenbus.o
diff --git a/drivers/block/xen-blkback/blkback.c b/drivers/block/xen-blkback/blkback.c
new file mode 100644
index 0000000..c73910c
--- /dev/null
+++ b/drivers/block/xen-blkback/blkback.c
@@ -0,0 +1,824 @@
+/******************************************************************************
+ *
+ * Back-end of the driver for virtual block devices. This portion of the
+ * driver exports a 'unified' block-device interface that can be accessed
+ * by any operating system that implements a compatible front end. A
+ * reference front-end implementation can be found in:
+ * drivers/block/xen-blkfront.c
+ *
+ * Copyright (c) 2003-2004, Keir Fraser & Steve Hand
+ * Copyright (c) 2005, Christopher Clark
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation; or, when distributed
+ * separately from the Linux kernel or incorporated into other
+ * software packages, subject to the following license:
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this source file (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy, modify,
+ * merge, publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include <linux/spinlock.h>
+#include <linux/kthread.h>
+#include <linux/list.h>
+#include <linux/delay.h>
+#include <linux/freezer.h>
+
+#include <xen/events.h>
+#include <xen/page.h>
+#include <asm/xen/hypervisor.h>
+#include <asm/xen/hypercall.h>
+#include "common.h"
+
+/*
+ * These are rather arbitrary. They are fairly large because adjacent requests
+ * pulled from a communication ring are quite likely to end up being part of
+ * the same scatter/gather request at the disc.
+ *
+ * ** TRY INCREASING 'xen_blkif_reqs' IF WRITE SPEEDS SEEM TOO LOW **
+ *
+ * This will increase the chances of being able to write whole tracks.
+ * 64 should be enough to keep us competitive with Linux.
+ */
+static int xen_blkif_reqs = 64;
+module_param_named(reqs, xen_blkif_reqs, int, 0);
+MODULE_PARM_DESC(reqs, "Number of blkback requests to allocate");
+
+/* Run-time switchable: /sys/module/blkback/parameters/ */
+static unsigned int log_stats;
+module_param(log_stats, int, 0644);
+
+/*
+ * Each outstanding request that we've passed to the lower device layers has a
+ * 'pending_req' allocated to it. Each buffer_head that completes decrements
+ * the pendcnt towards zero. When it hits zero, the specified domain has a
+ * response queued for it, with the saved 'id' passed back.
+ */
+struct pending_req {
+ struct xen_blkif *blkif;
+ u64 id;
+ int nr_pages;
+ atomic_t pendcnt;
+ unsigned short operation;
+ int status;
+ struct list_head free_list;
+};
+
+#define BLKBACK_INVALID_HANDLE (~0)
+
+struct xen_blkbk {
+ struct pending_req *pending_reqs;
+ /* List of all 'pending_req' available */
+ struct list_head pending_free;
+ /* And its spinlock. */
+ spinlock_t pending_free_lock;
+ wait_queue_head_t pending_free_wq;
+ /* The list of all pages that are available. */
+ struct page **pending_pages;
+ /* And the grant handles that are available. */
+ grant_handle_t *pending_grant_handles;
+};
+
+static struct xen_blkbk *blkbk;
+
+/*
+ * Little helpful macro to figure out the index and virtual address of the
+ * pending_pages[..]. For each 'pending_req' we have have up to
+ * BLKIF_MAX_SEGMENTS_PER_REQUEST (11) pages. The seg would be from 0 through
+ * 10 and would index in the pending_pages[..].
+ */
+static inline int vaddr_pagenr(struct pending_req *req, int seg)
+{
+ return (req - blkbk->pending_reqs) *
+ BLKIF_MAX_SEGMENTS_PER_REQUEST + seg;
+}
+
+#define pending_page(req, seg) pending_pages[vaddr_pagenr(req, seg)]
+
+static inline unsigned long vaddr(struct pending_req *req, int seg)
+{
+ unsigned long pfn = page_to_pfn(blkbk->pending_page(req, seg));
+ return (unsigned long)pfn_to_kaddr(pfn);
+}
+
+#define pending_handle(_req, _seg) \
+ (blkbk->pending_grant_handles[vaddr_pagenr(_req, _seg)])
+
+
+static int do_block_io_op(struct xen_blkif *blkif);
+static int dispatch_rw_block_io(struct xen_blkif *blkif,
+ struct blkif_request *req,
+ struct pending_req *pending_req);
+static void make_response(struct xen_blkif *blkif, u64 id,
+ unsigned short op, int st);
+
+/*
+ * Retrieve from the 'pending_reqs' a free pending_req structure to be used.
+ */
+static struct pending_req *alloc_req(void)
+{
+ struct pending_req *req = NULL;
+ unsigned long flags;
+
+ spin_lock_irqsave(&blkbk->pending_free_lock, flags);
+ if (!list_empty(&blkbk->pending_free)) {
+ req = list_entry(blkbk->pending_free.next, struct pending_req,
+ free_list);
+ list_del(&req->free_list);
+ }
+ spin_unlock_irqrestore(&blkbk->pending_free_lock, flags);
+ return req;
+}
+
+/*
+ * Return the 'pending_req' structure back to the freepool. We also
+ * wake up the thread if it was waiting for a free page.
+ */
+static void free_req(struct pending_req *req)
+{
+ unsigned long flags;
+ int was_empty;
+
+ spin_lock_irqsave(&blkbk->pending_free_lock, flags);
+ was_empty = list_empty(&blkbk->pending_free);
+ list_add(&req->free_list, &blkbk->pending_free);
+ spin_unlock_irqrestore(&blkbk->pending_free_lock, flags);
+ if (was_empty)
+ wake_up(&blkbk->pending_free_wq);
+}
+
+/*
+ * Routines for managing virtual block devices (vbds).
+ */
+static int xen_vbd_translate(struct phys_req *req, struct xen_blkif *blkif,
+ int operation)
+{
+ struct xen_vbd *vbd = &blkif->vbd;
+ int rc = -EACCES;
+
+ if ((operation != READ) && vbd->readonly)
+ goto out;
+
+ if (likely(req->nr_sects)) {
+ blkif_sector_t end = req->sector_number + req->nr_sects;
+
+ if (unlikely(end < req->sector_number))
+ goto out;
+ if (unlikely(end > vbd_sz(vbd)))
+ goto out;
+ }
+
+ req->dev = vbd->pdevice;
+ req->bdev = vbd->bdev;
+ rc = 0;
+
+ out:
+ return rc;
+}
+
+static void xen_vbd_resize(struct xen_blkif *blkif)
+{
+ struct xen_vbd *vbd = &blkif->vbd;
+ struct xenbus_transaction xbt;
+ int err;
+ struct xenbus_device *dev = xen_blkbk_xenbus(blkif->be);
+ unsigned long long new_size = vbd_sz(vbd);
+
+ pr_info(DRV_PFX "VBD Resize: Domid: %d, Device: (%d, %d)\n",
+ blkif->domid, MAJOR(vbd->pdevice), MINOR(vbd->pdevice));
+ pr_info(DRV_PFX "VBD Resize: new size %llu\n", new_size);
+ vbd->size = new_size;
+again:
+ err = xenbus_transaction_start(&xbt);
+ if (err) {
+ pr_warn(DRV_PFX "Error starting transaction");
+ return;
+ }
+ err = xenbus_printf(xbt, dev->nodename, "sectors", "%llu",
+ (unsigned long long)vbd_sz(vbd));
+ if (err) {
+ pr_warn(DRV_PFX "Error writing new size");
+ goto abort;
+ }
+ /*
+ * Write the current state; we will use this to synchronize
+ * the front-end. If the current state is "connected" the
+ * front-end will get the new size information online.
+ */
+ err = xenbus_printf(xbt, dev->nodename, "state", "%d", dev->state);
+ if (err) {
+ pr_warn(DRV_PFX "Error writing the state");
+ goto abort;
+ }
+
+ err = xenbus_transaction_end(xbt, 0);
+ if (err == -EAGAIN)
+ goto again;
+ if (err)
+ pr_warn(DRV_PFX "Error ending transaction");
+ return;
+abort:
+ xenbus_transaction_end(xbt, 1);
+}
+
+/*
+ * Notification from the guest OS.
+ */
+static void blkif_notify_work(struct xen_blkif *blkif)
+{
+ blkif->waiting_reqs = 1;
+ wake_up(&blkif->wq);
+}
+
+irqreturn_t xen_blkif_be_int(int irq, void *dev_id)
+{
+ blkif_notify_work(dev_id);
+ return IRQ_HANDLED;
+}
+
+/*
+ * SCHEDULER FUNCTIONS
+ */
+
+static void print_stats(struct xen_blkif *blkif)
+{
+ pr_info("xen-blkback (%s): oo %3d | rd %4d | wr %4d | f %4d\n",
+ current->comm, blkif->st_oo_req,
+ blkif->st_rd_req, blkif->st_wr_req, blkif->st_f_req);
+ blkif->st_print = jiffies + msecs_to_jiffies(10 * 1000);
+ blkif->st_rd_req = 0;
+ blkif->st_wr_req = 0;
+ blkif->st_oo_req = 0;
+}
+
+int xen_blkif_schedule(void *arg)
+{
+ struct xen_blkif *blkif = arg;
+ struct xen_vbd *vbd = &blkif->vbd;
+
+ xen_blkif_get(blkif);
+
+ while (!kthread_should_stop()) {
+ if (try_to_freeze())
+ continue;
+ if (unlikely(vbd->size != vbd_sz(vbd)))
+ xen_vbd_resize(blkif);
+
+ wait_event_interruptible(
+ blkif->wq,
+ blkif->waiting_reqs || kthread_should_stop());
+ wait_event_interruptible(
+ blkbk->pending_free_wq,
+ !list_empty(&blkbk->pending_free) ||
+ kthread_should_stop());
+
+ blkif->waiting_reqs = 0;
+ smp_mb(); /* clear flag *before* checking for work */
+
+ if (do_block_io_op(blkif))
+ blkif->waiting_reqs = 1;
+
+ if (log_stats && time_after(jiffies, blkif->st_print))
+ print_stats(blkif);
+ }
+
+ if (log_stats)
+ print_stats(blkif);
+
+ blkif->xenblkd = NULL;
+ xen_blkif_put(blkif);
+
+ return 0;
+}
+
+struct seg_buf {
+ unsigned long buf;
+ unsigned int nsec;
+};
+/*
+ * Unmap the grant references, and also remove the M2P over-rides
+ * used in the 'pending_req'.
+ */
+static void xen_blkbk_unmap(struct pending_req *req)
+{
+ struct gnttab_unmap_grant_ref unmap[BLKIF_MAX_SEGMENTS_PER_REQUEST];
+ unsigned int i, invcount = 0;
+ grant_handle_t handle;
+ int ret;
+
+ for (i = 0; i < req->nr_pages; i++) {
+ handle = pending_handle(req, i);
+ if (handle == BLKBACK_INVALID_HANDLE)
+ continue;
+ gnttab_set_unmap_op(&unmap[invcount], vaddr(req, i),
+ GNTMAP_host_map, handle);
+ pending_handle(req, i) = BLKBACK_INVALID_HANDLE;
+ invcount++;
+ }
+
+ ret = HYPERVISOR_grant_table_op(
+ GNTTABOP_unmap_grant_ref, unmap, invcount);
+ BUG_ON(ret);
+ /*
+ * Note, we use invcount, so nr->pages, so we can't index
+ * using vaddr(req, i).
+ */
+ for (i = 0; i < invcount; i++) {
+ ret = m2p_remove_override(
+ virt_to_page(unmap[i].host_addr), false);
+ if (ret) {
+ pr_alert(DRV_PFX "Failed to remove M2P override for %lx\n",
+ (unsigned long)unmap[i].host_addr);
+ continue;
+ }
+ }
+}
+
+static int xen_blkbk_map(struct blkif_request *req,
+ struct pending_req *pending_req,
+ struct seg_buf seg[])
+{
+ struct gnttab_map_grant_ref map[BLKIF_MAX_SEGMENTS_PER_REQUEST];
+ int i;
+ int nseg = req->nr_segments;
+ int ret = 0;
+
+ /*
+ * Fill out preq.nr_sects with proper amount of sectors, and setup
+ * assign map[..] with the PFN of the page in our domain with the
+ * corresponding grant reference for each page.
+ */
+ for (i = 0; i < nseg; i++) {
+ uint32_t flags;
+
+ flags = GNTMAP_host_map;
+ if (pending_req->operation != BLKIF_OP_READ)
+ flags |= GNTMAP_readonly;
+ gnttab_set_map_op(&map[i], vaddr(pending_req, i), flags,
+ req->u.rw.seg[i].gref,
+ pending_req->blkif->domid);
+ }
+
+ ret = HYPERVISOR_grant_table_op(GNTTABOP_map_grant_ref, map, nseg);
+ BUG_ON(ret);
+
+ /*
+ * Now swizzle the MFN in our domain with the MFN from the other domain
+ * so that when we access vaddr(pending_req,i) it has the contents of
+ * the page from the other domain.
+ */
+ for (i = 0; i < nseg; i++) {
+ if (unlikely(map[i].status != 0)) {
+ pr_debug(DRV_PFX "invalid buffer -- could not remap it\n");
+ map[i].handle = BLKBACK_INVALID_HANDLE;
+ ret |= 1;
+ }
+
+ pending_handle(pending_req, i) = map[i].handle;
+
+ if (ret)
+ continue;
+
+ ret = m2p_add_override(PFN_DOWN(map[i].dev_bus_addr),
+ blkbk->pending_page(pending_req, i), false);
+ if (ret) {
+ pr_alert(DRV_PFX "Failed to install M2P override for %lx (ret: %d)\n",
+ (unsigned long)map[i].dev_bus_addr, ret);
+ /* We could switch over to GNTTABOP_copy */
+ continue;
+ }
+
+ seg[i].buf = map[i].dev_bus_addr |
+ (req->u.rw.seg[i].first_sect << 9);
+ }
+ return ret;
+}
+
+/*
+ * Completion callback on the bio's. Called as bh->b_end_io()
+ */
+
+static void __end_block_io_op(struct pending_req *pending_req, int error)
+{
+ /* An error fails the entire request. */
+ if ((pending_req->operation == BLKIF_OP_FLUSH_DISKCACHE) &&
+ (error == -EOPNOTSUPP)) {
+ pr_debug(DRV_PFX "flush diskcache op failed, not supported\n");
+ xen_blkbk_flush_diskcache(XBT_NIL, pending_req->blkif->be, 0);
+ pending_req->status = BLKIF_RSP_EOPNOTSUPP;
+ } else if (error) {
+ pr_debug(DRV_PFX "Buffer not up-to-date at end of operation,"
+ " error=%d\n", error);
+ pending_req->status = BLKIF_RSP_ERROR;
+ }
+
+ /*
+ * If all of the bio's have completed it is time to unmap
+ * the grant references associated with 'request' and provide
+ * the proper response on the ring.
+ */
+ if (atomic_dec_and_test(&pending_req->pendcnt)) {
+ xen_blkbk_unmap(pending_req);
+ make_response(pending_req->blkif, pending_req->id,
+ pending_req->operation, pending_req->status);
+ xen_blkif_put(pending_req->blkif);
+ free_req(pending_req);
+ }
+}
+
+/*
+ * bio callback.
+ */
+static void end_block_io_op(struct bio *bio, int error)
+{
+ __end_block_io_op(bio->bi_private, error);
+ bio_put(bio);
+}
+
+
+
+/*
+ * Function to copy the from the ring buffer the 'struct blkif_request'
+ * (which has the sectors we want, number of them, grant references, etc),
+ * and transmute it to the block API to hand it over to the proper block disk.
+ */
+static int do_block_io_op(struct xen_blkif *blkif)
+{
+ union blkif_back_rings *blk_rings = &blkif->blk_rings;
+ struct blkif_request req;
+ struct pending_req *pending_req;
+ RING_IDX rc, rp;
+ int more_to_do = 0;
+
+ rc = blk_rings->common.req_cons;
+ rp = blk_rings->common.sring->req_prod;
+ rmb(); /* Ensure we see queued requests up to 'rp'. */
+
+ while (rc != rp) {
+
+ if (RING_REQUEST_CONS_OVERFLOW(&blk_rings->common, rc))
+ break;
+
+ if (kthread_should_stop()) {
+ more_to_do = 1;
+ break;
+ }
+
+ pending_req = alloc_req();
+ if (NULL == pending_req) {
+ blkif->st_oo_req++;
+ more_to_do = 1;
+ break;
+ }
+
+ switch (blkif->blk_protocol) {
+ case BLKIF_PROTOCOL_NATIVE:
+ memcpy(&req, RING_GET_REQUEST(&blk_rings->native, rc), sizeof(req));
+ break;
+ case BLKIF_PROTOCOL_X86_32:
+ blkif_get_x86_32_req(&req, RING_GET_REQUEST(&blk_rings->x86_32, rc));
+ break;
+ case BLKIF_PROTOCOL_X86_64:
+ blkif_get_x86_64_req(&req, RING_GET_REQUEST(&blk_rings->x86_64, rc));
+ break;
+ default:
+ BUG();
+ }
+ blk_rings->common.req_cons = ++rc; /* before make_response() */
+
+ /* Apply all sanity checks to /private copy/ of request. */
+ barrier();
+
+ if (dispatch_rw_block_io(blkif, &req, pending_req))
+ break;
+
+ /* Yield point for this unbounded loop. */
+ cond_resched();
+ }
+
+ return more_to_do;
+}
+
+/*
+ * Transmutation of the 'struct blkif_request' to a proper 'struct bio'
+ * and call the 'submit_bio' to pass it to the underlying storage.
+ */
+static int dispatch_rw_block_io(struct xen_blkif *blkif,
+ struct blkif_request *req,
+ struct pending_req *pending_req)
+{
+ struct phys_req preq;
+ struct seg_buf seg[BLKIF_MAX_SEGMENTS_PER_REQUEST];
+ unsigned int nseg;
+ struct bio *bio = NULL;
+ struct bio *biolist[BLKIF_MAX_SEGMENTS_PER_REQUEST];
+ int i, nbio = 0;
+ int operation;
+ struct blk_plug plug;
+
+ switch (req->operation) {
+ case BLKIF_OP_READ:
+ blkif->st_rd_req++;
+ operation = READ;
+ break;
+ case BLKIF_OP_WRITE:
+ blkif->st_wr_req++;
+ operation = WRITE_ODIRECT;
+ break;
+ case BLKIF_OP_FLUSH_DISKCACHE:
+ blkif->st_f_req++;
+ operation = WRITE_FLUSH;
+ break;
+ case BLKIF_OP_WRITE_BARRIER:
+ default:
+ operation = 0; /* make gcc happy */
+ goto fail_response;
+ break;
+ }
+
+ /* Check that the number of segments is sane. */
+ nseg = req->nr_segments;
+ if (unlikely(nseg == 0 && operation != WRITE_FLUSH) ||
+ unlikely(nseg > BLKIF_MAX_SEGMENTS_PER_REQUEST)) {
+ pr_debug(DRV_PFX "Bad number of segments in request (%d)\n",
+ nseg);
+ /* Haven't submitted any bio's yet. */
+ goto fail_response;
+ }
+
+ preq.dev = req->handle;
+ preq.sector_number = req->u.rw.sector_number;
+ preq.nr_sects = 0;
+
+ pending_req->blkif = blkif;
+ pending_req->id = req->id;
+ pending_req->operation = req->operation;
+ pending_req->status = BLKIF_RSP_OKAY;
+ pending_req->nr_pages = nseg;
+
+ for (i = 0; i < nseg; i++) {
+ seg[i].nsec = req->u.rw.seg[i].last_sect -
+ req->u.rw.seg[i].first_sect + 1;
+ if ((req->u.rw.seg[i].last_sect >= (PAGE_SIZE >> 9)) ||
+ (req->u.rw.seg[i].last_sect < req->u.rw.seg[i].first_sect))
+ goto fail_response;
+ preq.nr_sects += seg[i].nsec;
+
+ }
+
+ if (xen_vbd_translate(&preq, blkif, operation) != 0) {
+ pr_debug(DRV_PFX "access denied: %s of [%llu,%llu] on dev=%04x\n",
+ operation == READ ? "read" : "write",
+ preq.sector_number,
+ preq.sector_number + preq.nr_sects, preq.dev);
+ goto fail_response;
+ }
+
+ /*
+ * This check _MUST_ be done after xen_vbd_translate as the preq.bdev
+ * is set there.
+ */
+ for (i = 0; i < nseg; i++) {
+ if (((int)preq.sector_number|(int)seg[i].nsec) &
+ ((bdev_logical_block_size(preq.bdev) >> 9) - 1)) {
+ pr_debug(DRV_PFX "Misaligned I/O request from domain %d",
+ blkif->domid);
+ goto fail_response;
+ }
+ }
+
+ /*
+ * If we have failed at this point, we need to undo the M2P override,
+ * set gnttab_set_unmap_op on all of the grant references and perform
+ * the hypercall to unmap the grants - that is all done in
+ * xen_blkbk_unmap.
+ */
+ if (xen_blkbk_map(req, pending_req, seg))
+ goto fail_flush;
+
+ /* This corresponding xen_blkif_put is done in __end_block_io_op */
+ xen_blkif_get(blkif);
+
+ for (i = 0; i < nseg; i++) {
+ while ((bio == NULL) ||
+ (bio_add_page(bio,
+ blkbk->pending_page(pending_req, i),
+ seg[i].nsec << 9,
+ seg[i].buf & ~PAGE_MASK) == 0)) {
+
+ bio = bio_alloc(GFP_KERNEL, nseg-i);
+ if (unlikely(bio == NULL))
+ goto fail_put_bio;
+
+ biolist[nbio++] = bio;
+ bio->bi_bdev = preq.bdev;
+ bio->bi_private = pending_req;
+ bio->bi_end_io = end_block_io_op;
+ bio->bi_sector = preq.sector_number;
+ }
+
+ preq.sector_number += seg[i].nsec;
+ }
+
+ /* This will be hit if the operation was a flush. */
+ if (!bio) {
+ BUG_ON(operation != WRITE_FLUSH);
+
+ bio = bio_alloc(GFP_KERNEL, 0);
+ if (unlikely(bio == NULL))
+ goto fail_put_bio;
+
+ biolist[nbio++] = bio;
+ bio->bi_bdev = preq.bdev;
+ bio->bi_private = pending_req;
+ bio->bi_end_io = end_block_io_op;
+ }
+
+ /*
+ * We set it one so that the last submit_bio does not have to call
+ * atomic_inc.
+ */
+ atomic_set(&pending_req->pendcnt, nbio);
+
+ /* Get a reference count for the disk queue and start sending I/O */
+ blk_start_plug(&plug);
+
+ for (i = 0; i < nbio; i++)
+ submit_bio(operation, biolist[i]);
+
+ /* Let the I/Os go.. */
+ blk_finish_plug(&plug);
+
+ if (operation == READ)
+ blkif->st_rd_sect += preq.nr_sects;
+ else if (operation == WRITE || operation == WRITE_FLUSH)
+ blkif->st_wr_sect += preq.nr_sects;
+
+ return 0;
+
+ fail_flush:
+ xen_blkbk_unmap(pending_req);
+ fail_response:
+ /* Haven't submitted any bio's yet. */
+ make_response(blkif, req->id, req->operation, BLKIF_RSP_ERROR);
+ free_req(pending_req);
+ msleep(1); /* back off a bit */
+ return -EIO;
+
+ fail_put_bio:
+ for (i = 0; i < nbio; i++)
+ bio_put(biolist[i]);
+ __end_block_io_op(pending_req, -EINVAL);
+ msleep(1); /* back off a bit */
+ return -EIO;
+}
+
+
+
+/*
+ * Put a response on the ring on how the operation fared.
+ */
+static void make_response(struct xen_blkif *blkif, u64 id,
+ unsigned short op, int st)
+{
+ struct blkif_response resp;
+ unsigned long flags;
+ union blkif_back_rings *blk_rings = &blkif->blk_rings;
+ int more_to_do = 0;
+ int notify;
+
+ resp.id = id;
+ resp.operation = op;
+ resp.status = st;
+
+ spin_lock_irqsave(&blkif->blk_ring_lock, flags);
+ /* Place on the response ring for the relevant domain. */
+ switch (blkif->blk_protocol) {
+ case BLKIF_PROTOCOL_NATIVE:
+ memcpy(RING_GET_RESPONSE(&blk_rings->native, blk_rings->native.rsp_prod_pvt),
+ &resp, sizeof(resp));
+ break;
+ case BLKIF_PROTOCOL_X86_32:
+ memcpy(RING_GET_RESPONSE(&blk_rings->x86_32, blk_rings->x86_32.rsp_prod_pvt),
+ &resp, sizeof(resp));
+ break;
+ case BLKIF_PROTOCOL_X86_64:
+ memcpy(RING_GET_RESPONSE(&blk_rings->x86_64, blk_rings->x86_64.rsp_prod_pvt),
+ &resp, sizeof(resp));
+ break;
+ default:
+ BUG();
+ }
+ blk_rings->common.rsp_prod_pvt++;
+ RING_PUSH_RESPONSES_AND_CHECK_NOTIFY(&blk_rings->common, notify);
+ if (blk_rings->common.rsp_prod_pvt == blk_rings->common.req_cons) {
+ /*
+ * Tail check for pending requests. Allows frontend to avoid
+ * notifications if requests are already in flight (lower
+ * overheads and promotes batching).
+ */
+ RING_FINAL_CHECK_FOR_REQUESTS(&blk_rings->common, more_to_do);
+
+ } else if (RING_HAS_UNCONSUMED_REQUESTS(&blk_rings->common)) {
+ more_to_do = 1;
+ }
+
+ spin_unlock_irqrestore(&blkif->blk_ring_lock, flags);
+
+ if (more_to_do)
+ blkif_notify_work(blkif);
+ if (notify)
+ notify_remote_via_irq(blkif->irq);
+}
+
+static int __init xen_blkif_init(void)
+{
+ int i, mmap_pages;
+ int rc = 0;
+
+ if (!xen_pv_domain())
+ return -ENODEV;
+
+ blkbk = kzalloc(sizeof(struct xen_blkbk), GFP_KERNEL);
+ if (!blkbk) {
+ pr_alert(DRV_PFX "%s: out of memory!\n", __func__);
+ return -ENOMEM;
+ }
+
+ mmap_pages = xen_blkif_reqs * BLKIF_MAX_SEGMENTS_PER_REQUEST;
+
+ blkbk->pending_reqs = kmalloc(sizeof(blkbk->pending_reqs[0]) *
+ xen_blkif_reqs, GFP_KERNEL);
+ blkbk->pending_grant_handles = kzalloc(sizeof(blkbk->pending_grant_handles[0]) *
+ mmap_pages, GFP_KERNEL);
+ blkbk->pending_pages = kzalloc(sizeof(blkbk->pending_pages[0]) *
+ mmap_pages, GFP_KERNEL);
+
+ if (!blkbk->pending_reqs || !blkbk->pending_grant_handles ||
+ !blkbk->pending_pages) {
+ rc = -ENOMEM;
+ goto out_of_memory;
+ }
+
+ for (i = 0; i < mmap_pages; i++) {
+ blkbk->pending_grant_handles[i] = BLKBACK_INVALID_HANDLE;
+ blkbk->pending_pages[i] = alloc_page(GFP_KERNEL);
+ if (blkbk->pending_pages[i] == NULL) {
+ rc = -ENOMEM;
+ goto out_of_memory;
+ }
+ }
+ rc = xen_blkif_interface_init();
+ if (rc)
+ goto failed_init;
+
+ memset(blkbk->pending_reqs, 0, sizeof(blkbk->pending_reqs));
+
+ INIT_LIST_HEAD(&blkbk->pending_free);
+ spin_lock_init(&blkbk->pending_free_lock);
+ init_waitqueue_head(&blkbk->pending_free_wq);
+
+ for (i = 0; i < xen_blkif_reqs; i++)
+ list_add_tail(&blkbk->pending_reqs[i].free_list,
+ &blkbk->pending_free);
+
+ rc = xen_blkif_xenbus_init();
+ if (rc)
+ goto failed_init;
+
+ return 0;
+
+ out_of_memory:
+ pr_alert(DRV_PFX "%s: out of memory\n", __func__);
+ failed_init:
+ kfree(blkbk->pending_reqs);
+ kfree(blkbk->pending_grant_handles);
+ for (i = 0; i < mmap_pages; i++) {
+ if (blkbk->pending_pages[i])
+ __free_page(blkbk->pending_pages[i]);
+ }
+ kfree(blkbk->pending_pages);
+ kfree(blkbk);
+ blkbk = NULL;
+ return rc;
+}
+
+module_init(xen_blkif_init);
+
+MODULE_LICENSE("Dual BSD/GPL");
diff --git a/drivers/block/xen-blkback/common.h b/drivers/block/xen-blkback/common.h
new file mode 100644
index 0000000..9e40b28
--- /dev/null
+++ b/drivers/block/xen-blkback/common.h
@@ -0,0 +1,233 @@
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation; or, when distributed
+ * separately from the Linux kernel or incorporated into other
+ * software packages, subject to the following license:
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this source file (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy, modify,
+ * merge, publish, distribute, sublicense, and/or sell copies of the Software,
+ * and to permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#ifndef __XEN_BLKIF__BACKEND__COMMON_H__
+#define __XEN_BLKIF__BACKEND__COMMON_H__
+
+#include <linux/version.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/slab.h>
+#include <linux/blkdev.h>
+#include <linux/vmalloc.h>
+#include <linux/wait.h>
+#include <linux/io.h>
+#include <asm/setup.h>
+#include <asm/pgalloc.h>
+#include <asm/hypervisor.h>
+#include <xen/grant_table.h>
+#include <xen/xenbus.h>
+#include <xen/interface/io/ring.h>
+#include <xen/interface/io/blkif.h>
+#include <xen/interface/io/protocols.h>
+
+#define DRV_PFX "xen-blkback:"
+#define DPRINTK(fmt, args...) \
+ pr_debug(DRV_PFX "(%s:%d) " fmt ".\n", \
+ __func__, __LINE__, ##args)
+
+
+/* Not a real protocol. Used to generate ring structs which contain
+ * the elements common to all protocols only. This way we get a
+ * compiler-checkable way to use common struct elements, so we can
+ * avoid using switch(protocol) in a number of places. */
+struct blkif_common_request {
+ char dummy;
+};
+struct blkif_common_response {
+ char dummy;
+};
+
+/* i386 protocol version */
+#pragma pack(push, 4)
+struct blkif_x86_32_request {
+ uint8_t operation; /* BLKIF_OP_??? */
+ uint8_t nr_segments; /* number of segments */
+ blkif_vdev_t handle; /* only for read/write requests */
+ uint64_t id; /* private guest value, echoed in resp */
+ blkif_sector_t sector_number;/* start sector idx on disk (r/w only) */
+ struct blkif_request_segment seg[BLKIF_MAX_SEGMENTS_PER_REQUEST];
+};
+struct blkif_x86_32_response {
+ uint64_t id; /* copied from request */
+ uint8_t operation; /* copied from request */
+ int16_t status; /* BLKIF_RSP_??? */
+};
+#pragma pack(pop)
+
+/* x86_64 protocol version */
+struct blkif_x86_64_request {
+ uint8_t operation; /* BLKIF_OP_??? */
+ uint8_t nr_segments; /* number of segments */
+ blkif_vdev_t handle; /* only for read/write requests */
+ uint64_t __attribute__((__aligned__(8))) id;
+ blkif_sector_t sector_number;/* start sector idx on disk (r/w only) */
+ struct blkif_request_segment seg[BLKIF_MAX_SEGMENTS_PER_REQUEST];
+};
+struct blkif_x86_64_response {
+ uint64_t __attribute__((__aligned__(8))) id;
+ uint8_t operation; /* copied from request */
+ int16_t status; /* BLKIF_RSP_??? */
+};
+
+DEFINE_RING_TYPES(blkif_common, struct blkif_common_request,
+ struct blkif_common_response);
+DEFINE_RING_TYPES(blkif_x86_32, struct blkif_x86_32_request,
+ struct blkif_x86_32_response);
+DEFINE_RING_TYPES(blkif_x86_64, struct blkif_x86_64_request,
+ struct blkif_x86_64_response);
+
+union blkif_back_rings {
+ struct blkif_back_ring native;
+ struct blkif_common_back_ring common;
+ struct blkif_x86_32_back_ring x86_32;
+ struct blkif_x86_64_back_ring x86_64;
+};
+
+enum blkif_protocol {
+ BLKIF_PROTOCOL_NATIVE = 1,
+ BLKIF_PROTOCOL_X86_32 = 2,
+ BLKIF_PROTOCOL_X86_64 = 3,
+};
+
+struct xen_vbd {
+ /* What the domain refers to this vbd as. */
+ blkif_vdev_t handle;
+ /* Non-zero -> read-only */
+ unsigned char readonly;
+ /* VDISK_xxx */
+ unsigned char type;
+ /* phys device that this vbd maps to. */
+ u32 pdevice;
+ struct block_device *bdev;
+ /* Cached size parameter. */
+ sector_t size;
+ bool flush_support;
+};
+
+struct backend_info;
+
+struct xen_blkif {
+ /* Unique identifier for this interface. */
+ domid_t domid;
+ unsigned int handle;
+ /* Physical parameters of the comms window. */
+ unsigned int irq;
+ /* Comms information. */
+ enum blkif_protocol blk_protocol;
+ union blkif_back_rings blk_rings;
+ struct vm_struct *blk_ring_area;
+ /* The VBD attached to this interface. */
+ struct xen_vbd vbd;
+ /* Back pointer to the backend_info. */
+ struct backend_info *be;
+ /* Private fields. */
+ spinlock_t blk_ring_lock;
+ atomic_t refcnt;
+
+ wait_queue_head_t wq;
+ /* One thread per one blkif. */
+ struct task_struct *xenblkd;
+ unsigned int waiting_reqs;
+
+ /* statistics */
+ unsigned long st_print;
+ int st_rd_req;
+ int st_wr_req;
+ int st_oo_req;
+ int st_f_req;
+ int st_rd_sect;
+ int st_wr_sect;
+
+ wait_queue_head_t waiting_to_free;
+
+ grant_handle_t shmem_handle;
+ grant_ref_t shmem_ref;
+};
+
+
+#define vbd_sz(_v) ((_v)->bdev->bd_part ? \
+ (_v)->bdev->bd_part->nr_sects : \
+ get_capacity((_v)->bdev->bd_disk))
+
+#define xen_blkif_get(_b) (atomic_inc(&(_b)->refcnt))
+#define xen_blkif_put(_b) \
+ do { \
+ if (atomic_dec_and_test(&(_b)->refcnt)) \
+ wake_up(&(_b)->waiting_to_free);\
+ } while (0)
+
+struct phys_req {
+ unsigned short dev;
+ unsigned short nr_sects;
+ struct block_device *bdev;
+ blkif_sector_t sector_number;
+};
+int xen_blkif_interface_init(void);
+
+int xen_blkif_xenbus_init(void);
+
+irqreturn_t xen_blkif_be_int(int irq, void *dev_id);
+int xen_blkif_schedule(void *arg);
+
+int xen_blkbk_flush_diskcache(struct xenbus_transaction xbt,
+ struct backend_info *be, int state);
+
+struct xenbus_device *xen_blkbk_xenbus(struct backend_info *be);
+
+static inline void blkif_get_x86_32_req(struct blkif_request *dst,
+ struct blkif_x86_32_request *src)
+{
+ int i, n = BLKIF_MAX_SEGMENTS_PER_REQUEST;
+ dst->operation = src->operation;
+ dst->nr_segments = src->nr_segments;
+ dst->handle = src->handle;
+ dst->id = src->id;
+ dst->u.rw.sector_number = src->sector_number;
+ barrier();
+ if (n > dst->nr_segments)
+ n = dst->nr_segments;
+ for (i = 0; i < n; i++)
+ dst->u.rw.seg[i] = src->seg[i];
+}
+
+static inline void blkif_get_x86_64_req(struct blkif_request *dst,
+ struct blkif_x86_64_request *src)
+{
+ int i, n = BLKIF_MAX_SEGMENTS_PER_REQUEST;
+ dst->operation = src->operation;
+ dst->nr_segments = src->nr_segments;
+ dst->handle = src->handle;
+ dst->id = src->id;
+ dst->u.rw.sector_number = src->sector_number;
+ barrier();
+ if (n > dst->nr_segments)
+ n = dst->nr_segments;
+ for (i = 0; i < n; i++)
+ dst->u.rw.seg[i] = src->seg[i];
+}
+
+#endif /* __XEN_BLKIF__BACKEND__COMMON_H__ */
diff --git a/drivers/block/xen-blkback/xenbus.c b/drivers/block/xen-blkback/xenbus.c
new file mode 100644
index 0000000..3457082
--- /dev/null
+++ b/drivers/block/xen-blkback/xenbus.c
@@ -0,0 +1,768 @@
+/* Xenbus code for blkif backend
+ Copyright (C) 2005 Rusty Russell <rusty@rustcorp.com.au>
+ Copyright (C) 2005 XenSource Ltd
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+*/
+
+#include <stdarg.h>
+#include <linux/module.h>
+#include <linux/kthread.h>
+#include <xen/events.h>
+#include <xen/grant_table.h>
+#include "common.h"
+
+struct backend_info {
+ struct xenbus_device *dev;
+ struct xen_blkif *blkif;
+ struct xenbus_watch backend_watch;
+ unsigned major;
+ unsigned minor;
+ char *mode;
+};
+
+static struct kmem_cache *xen_blkif_cachep;
+static void connect(struct backend_info *);
+static int connect_ring(struct backend_info *);
+static void backend_changed(struct xenbus_watch *, const char **,
+ unsigned int);
+
+struct xenbus_device *xen_blkbk_xenbus(struct backend_info *be)
+{
+ return be->dev;
+}
+
+static int blkback_name(struct xen_blkif *blkif, char *buf)
+{
+ char *devpath, *devname;
+ struct xenbus_device *dev = blkif->be->dev;
+
+ devpath = xenbus_read(XBT_NIL, dev->nodename, "dev", NULL);
+ if (IS_ERR(devpath))
+ return PTR_ERR(devpath);
+
+ devname = strstr(devpath, "/dev/");
+ if (devname != NULL)
+ devname += strlen("/dev/");
+ else
+ devname = devpath;
+
+ snprintf(buf, TASK_COMM_LEN, "blkback.%d.%s", blkif->domid, devname);
+ kfree(devpath);
+
+ return 0;
+}
+
+static void xen_update_blkif_status(struct xen_blkif *blkif)
+{
+ int err;
+ char name[TASK_COMM_LEN];
+
+ /* Not ready to connect? */
+ if (!blkif->irq || !blkif->vbd.bdev)
+ return;
+
+ /* Already connected? */
+ if (blkif->be->dev->state == XenbusStateConnected)
+ return;
+
+ /* Attempt to connect: exit if we fail to. */
+ connect(blkif->be);
+ if (blkif->be->dev->state != XenbusStateConnected)
+ return;
+
+ err = blkback_name(blkif, name);
+ if (err) {
+ xenbus_dev_error(blkif->be->dev, err, "get blkback dev name");
+ return;
+ }
+
+ err = filemap_write_and_wait(blkif->vbd.bdev->bd_inode->i_mapping);
+ if (err) {
+ xenbus_dev_error(blkif->be->dev, err, "block flush");
+ return;
+ }
+ invalidate_inode_pages2(blkif->vbd.bdev->bd_inode->i_mapping);
+
+ blkif->xenblkd = kthread_run(xen_blkif_schedule, blkif, name);
+ if (IS_ERR(blkif->xenblkd)) {
+ err = PTR_ERR(blkif->xenblkd);
+ blkif->xenblkd = NULL;
+ xenbus_dev_error(blkif->be->dev, err, "start xenblkd");
+ }
+}
+
+static struct xen_blkif *xen_blkif_alloc(domid_t domid)
+{
+ struct xen_blkif *blkif;
+
+ blkif = kmem_cache_alloc(xen_blkif_cachep, GFP_KERNEL);
+ if (!blkif)
+ return ERR_PTR(-ENOMEM);
+
+ memset(blkif, 0, sizeof(*blkif));
+ blkif->domid = domid;
+ spin_lock_init(&blkif->blk_ring_lock);
+ atomic_set(&blkif->refcnt, 1);
+ init_waitqueue_head(&blkif->wq);
+ blkif->st_print = jiffies;
+ init_waitqueue_head(&blkif->waiting_to_free);
+
+ return blkif;
+}
+
+static int map_frontend_page(struct xen_blkif *blkif, unsigned long shared_page)
+{
+ struct gnttab_map_grant_ref op;
+
+ gnttab_set_map_op(&op, (unsigned long)blkif->blk_ring_area->addr,
+ GNTMAP_host_map, shared_page, blkif->domid);
+
+ if (HYPERVISOR_grant_table_op(GNTTABOP_map_grant_ref, &op, 1))
+ BUG();
+
+ if (op.status) {
+ DPRINTK("Grant table operation failure !\n");
+ return op.status;
+ }
+
+ blkif->shmem_ref = shared_page;
+ blkif->shmem_handle = op.handle;
+
+ return 0;
+}
+
+static void unmap_frontend_page(struct xen_blkif *blkif)
+{
+ struct gnttab_unmap_grant_ref op;
+
+ gnttab_set_unmap_op(&op, (unsigned long)blkif->blk_ring_area->addr,
+ GNTMAP_host_map, blkif->shmem_handle);
+
+ if (HYPERVISOR_grant_table_op(GNTTABOP_unmap_grant_ref, &op, 1))
+ BUG();
+}
+
+static int xen_blkif_map(struct xen_blkif *blkif, unsigned long shared_page,
+ unsigned int evtchn)
+{
+ int err;
+
+ /* Already connected through? */
+ if (blkif->irq)
+ return 0;
+
+ blkif->blk_ring_area = alloc_vm_area(PAGE_SIZE);
+ if (!blkif->blk_ring_area)
+ return -ENOMEM;
+
+ err = map_frontend_page(blkif, shared_page);
+ if (err) {
+ free_vm_area(blkif->blk_ring_area);
+ return err;
+ }
+
+ switch (blkif->blk_protocol) {
+ case BLKIF_PROTOCOL_NATIVE:
+ {
+ struct blkif_sring *sring;
+ sring = (struct blkif_sring *)blkif->blk_ring_area->addr;
+ BACK_RING_INIT(&blkif->blk_rings.native, sring, PAGE_SIZE);
+ break;
+ }
+ case BLKIF_PROTOCOL_X86_32:
+ {
+ struct blkif_x86_32_sring *sring_x86_32;
+ sring_x86_32 = (struct blkif_x86_32_sring *)blkif->blk_ring_area->addr;
+ BACK_RING_INIT(&blkif->blk_rings.x86_32, sring_x86_32, PAGE_SIZE);
+ break;
+ }
+ case BLKIF_PROTOCOL_X86_64:
+ {
+ struct blkif_x86_64_sring *sring_x86_64;
+ sring_x86_64 = (struct blkif_x86_64_sring *)blkif->blk_ring_area->addr;
+ BACK_RING_INIT(&blkif->blk_rings.x86_64, sring_x86_64, PAGE_SIZE);
+ break;
+ }
+ default:
+ BUG();
+ }
+
+ err = bind_interdomain_evtchn_to_irqhandler(blkif->domid, evtchn,
+ xen_blkif_be_int, 0,
+ "blkif-backend", blkif);
+ if (err < 0) {
+ unmap_frontend_page(blkif);
+ free_vm_area(blkif->blk_ring_area);
+ blkif->blk_rings.common.sring = NULL;
+ return err;
+ }
+ blkif->irq = err;
+
+ return 0;
+}
+
+static void xen_blkif_disconnect(struct xen_blkif *blkif)
+{
+ if (blkif->xenblkd) {
+ kthread_stop(blkif->xenblkd);
+ blkif->xenblkd = NULL;
+ }
+
+ atomic_dec(&blkif->refcnt);
+ wait_event(blkif->waiting_to_free, atomic_read(&blkif->refcnt) == 0);
+ atomic_inc(&blkif->refcnt);
+
+ if (blkif->irq) {
+ unbind_from_irqhandler(blkif->irq, blkif);
+ blkif->irq = 0;
+ }
+
+ if (blkif->blk_rings.common.sring) {
+ unmap_frontend_page(blkif);
+ free_vm_area(blkif->blk_ring_area);
+ blkif->blk_rings.common.sring = NULL;
+ }
+}
+
+void xen_blkif_free(struct xen_blkif *blkif)
+{
+ if (!atomic_dec_and_test(&blkif->refcnt))
+ BUG();
+ kmem_cache_free(xen_blkif_cachep, blkif);
+}
+
+int __init xen_blkif_interface_init(void)
+{
+ xen_blkif_cachep = kmem_cache_create("blkif_cache",
+ sizeof(struct xen_blkif),
+ 0, 0, NULL);
+ if (!xen_blkif_cachep)
+ return -ENOMEM;
+
+ return 0;
+}
+
+/*
+ * sysfs interface for VBD I/O requests
+ */
+
+#define VBD_SHOW(name, format, args...) \
+ static ssize_t show_##name(struct device *_dev, \
+ struct device_attribute *attr, \
+ char *buf) \
+ { \
+ struct xenbus_device *dev = to_xenbus_device(_dev); \
+ struct backend_info *be = dev_get_drvdata(&dev->dev); \
+ \
+ return sprintf(buf, format, ##args); \
+ } \
+ static DEVICE_ATTR(name, S_IRUGO, show_##name, NULL)
+
+VBD_SHOW(oo_req, "%d\n", be->blkif->st_oo_req);
+VBD_SHOW(rd_req, "%d\n", be->blkif->st_rd_req);
+VBD_SHOW(wr_req, "%d\n", be->blkif->st_wr_req);
+VBD_SHOW(f_req, "%d\n", be->blkif->st_f_req);
+VBD_SHOW(rd_sect, "%d\n", be->blkif->st_rd_sect);
+VBD_SHOW(wr_sect, "%d\n", be->blkif->st_wr_sect);
+
+static struct attribute *xen_vbdstat_attrs[] = {
+ &dev_attr_oo_req.attr,
+ &dev_attr_rd_req.attr,
+ &dev_attr_wr_req.attr,
+ &dev_attr_f_req.attr,
+ &dev_attr_rd_sect.attr,
+ &dev_attr_wr_sect.attr,
+ NULL
+};
+
+static struct attribute_group xen_vbdstat_group = {
+ .name = "statistics",
+ .attrs = xen_vbdstat_attrs,
+};
+
+VBD_SHOW(physical_device, "%x:%x\n", be->major, be->minor);
+VBD_SHOW(mode, "%s\n", be->mode);
+
+int xenvbd_sysfs_addif(struct xenbus_device *dev)
+{
+ int error;
+
+ error = device_create_file(&dev->dev, &dev_attr_physical_device);
+ if (error)
+ goto fail1;
+
+ error = device_create_file(&dev->dev, &dev_attr_mode);
+ if (error)
+ goto fail2;
+
+ error = sysfs_create_group(&dev->dev.kobj, &xen_vbdstat_group);
+ if (error)
+ goto fail3;
+
+ return 0;
+
+fail3: sysfs_remove_group(&dev->dev.kobj, &xen_vbdstat_group);
+fail2: device_remove_file(&dev->dev, &dev_attr_mode);
+fail1: device_remove_file(&dev->dev, &dev_attr_physical_device);
+ return error;
+}
+
+void xenvbd_sysfs_delif(struct xenbus_device *dev)
+{
+ sysfs_remove_group(&dev->dev.kobj, &xen_vbdstat_group);
+ device_remove_file(&dev->dev, &dev_attr_mode);
+ device_remove_file(&dev->dev, &dev_attr_physical_device);
+}
+
+
+static void xen_vbd_free(struct xen_vbd *vbd)
+{
+ if (vbd->bdev)
+ blkdev_put(vbd->bdev, vbd->readonly ? FMODE_READ : FMODE_WRITE);
+ vbd->bdev = NULL;
+}
+
+static int xen_vbd_create(struct xen_blkif *blkif, blkif_vdev_t handle,
+ unsigned major, unsigned minor, int readonly,
+ int cdrom)
+{
+ struct xen_vbd *vbd;
+ struct block_device *bdev;
+ struct request_queue *q;
+
+ vbd = &blkif->vbd;
+ vbd->handle = handle;
+ vbd->readonly = readonly;
+ vbd->type = 0;
+
+ vbd->pdevice = MKDEV(major, minor);
+
+ bdev = blkdev_get_by_dev(vbd->pdevice, vbd->readonly ?
+ FMODE_READ : FMODE_WRITE, NULL);
+
+ if (IS_ERR(bdev)) {
+ DPRINTK("xen_vbd_create: device %08x could not be opened.\n",
+ vbd->pdevice);
+ return -ENOENT;
+ }
+
+ vbd->bdev = bdev;
+ vbd->size = vbd_sz(vbd);
+
+ if (vbd->bdev->bd_disk == NULL) {
+ DPRINTK("xen_vbd_create: device %08x doesn't exist.\n",
+ vbd->pdevice);
+ xen_vbd_free(vbd);
+ return -ENOENT;
+ }
+
+ if (vbd->bdev->bd_disk->flags & GENHD_FL_CD || cdrom)
+ vbd->type |= VDISK_CDROM;
+ if (vbd->bdev->bd_disk->flags & GENHD_FL_REMOVABLE)
+ vbd->type |= VDISK_REMOVABLE;
+
+ q = bdev_get_queue(bdev);
+ if (q && q->flush_flags)
+ vbd->flush_support = true;
+
+ DPRINTK("Successful creation of handle=%04x (dom=%u)\n",
+ handle, blkif->domid);
+ return 0;
+}
+static int xen_blkbk_remove(struct xenbus_device *dev)
+{
+ struct backend_info *be = dev_get_drvdata(&dev->dev);
+
+ DPRINTK("");
+
+ if (be->major || be->minor)
+ xenvbd_sysfs_delif(dev);
+
+ if (be->backend_watch.node) {
+ unregister_xenbus_watch(&be->backend_watch);
+ kfree(be->backend_watch.node);
+ be->backend_watch.node = NULL;
+ }
+
+ if (be->blkif) {
+ xen_blkif_disconnect(be->blkif);
+ xen_vbd_free(&be->blkif->vbd);
+ xen_blkif_free(be->blkif);
+ be->blkif = NULL;
+ }
+
+ kfree(be);
+ dev_set_drvdata(&dev->dev, NULL);
+ return 0;
+}
+
+int xen_blkbk_flush_diskcache(struct xenbus_transaction xbt,
+ struct backend_info *be, int state)
+{
+ struct xenbus_device *dev = be->dev;
+ int err;
+
+ err = xenbus_printf(xbt, dev->nodename, "feature-flush-cache",
+ "%d", state);
+ if (err)
+ xenbus_dev_fatal(dev, err, "writing feature-flush-cache");
+
+ return err;
+}
+
+/*
+ * Entry point to this code when a new device is created. Allocate the basic
+ * structures, and watch the store waiting for the hotplug scripts to tell us
+ * the device's physical major and minor numbers. Switch to InitWait.
+ */
+static int xen_blkbk_probe(struct xenbus_device *dev,
+ const struct xenbus_device_id *id)
+{
+ int err;
+ struct backend_info *be = kzalloc(sizeof(struct backend_info),
+ GFP_KERNEL);
+ if (!be) {
+ xenbus_dev_fatal(dev, -ENOMEM,
+ "allocating backend structure");
+ return -ENOMEM;
+ }
+ be->dev = dev;
+ dev_set_drvdata(&dev->dev, be);
+
+ be->blkif = xen_blkif_alloc(dev->otherend_id);
+ if (IS_ERR(be->blkif)) {
+ err = PTR_ERR(be->blkif);
+ be->blkif = NULL;
+ xenbus_dev_fatal(dev, err, "creating block interface");
+ goto fail;
+ }
+
+ /* setup back pointer */
+ be->blkif->be = be;
+
+ err = xenbus_watch_pathfmt(dev, &be->backend_watch, backend_changed,
+ "%s/%s", dev->nodename, "physical-device");
+ if (err)
+ goto fail;
+
+ err = xenbus_switch_state(dev, XenbusStateInitWait);
+ if (err)
+ goto fail;
+
+ return 0;
+
+fail:
+ DPRINTK("failed");
+ xen_blkbk_remove(dev);
+ return err;
+}
+
+
+/*
+ * Callback received when the hotplug scripts have placed the physical-device
+ * node. Read it and the mode node, and create a vbd. If the frontend is
+ * ready, connect.
+ */
+static void backend_changed(struct xenbus_watch *watch,
+ const char **vec, unsigned int len)
+{
+ int err;
+ unsigned major;
+ unsigned minor;
+ struct backend_info *be
+ = container_of(watch, struct backend_info, backend_watch);
+ struct xenbus_device *dev = be->dev;
+ int cdrom = 0;
+ char *device_type;
+
+ DPRINTK("");
+
+ err = xenbus_scanf(XBT_NIL, dev->nodename, "physical-device", "%x:%x",
+ &major, &minor);
+ if (XENBUS_EXIST_ERR(err)) {
+ /*
+ * Since this watch will fire once immediately after it is
+ * registered, we expect this. Ignore it, and wait for the
+ * hotplug scripts.
+ */
+ return;
+ }
+ if (err != 2) {
+ xenbus_dev_fatal(dev, err, "reading physical-device");
+ return;
+ }
+
+ if ((be->major || be->minor) &&
+ ((be->major != major) || (be->minor != minor))) {
+ pr_warn(DRV_PFX "changing physical device (from %x:%x to %x:%x) not supported.\n",
+ be->major, be->minor, major, minor);
+ return;
+ }
+
+ be->mode = xenbus_read(XBT_NIL, dev->nodename, "mode", NULL);
+ if (IS_ERR(be->mode)) {
+ err = PTR_ERR(be->mode);
+ be->mode = NULL;
+ xenbus_dev_fatal(dev, err, "reading mode");
+ return;
+ }
+
+ device_type = xenbus_read(XBT_NIL, dev->otherend, "device-type", NULL);
+ if (!IS_ERR(device_type)) {
+ cdrom = strcmp(device_type, "cdrom") == 0;
+ kfree(device_type);
+ }
+
+ if (be->major == 0 && be->minor == 0) {
+ /* Front end dir is a number, which is used as the handle. */
+
+ char *p = strrchr(dev->otherend, '/') + 1;
+ long handle;
+ err = strict_strtoul(p, 0, &handle);
+ if (err)
+ return;
+
+ be->major = major;
+ be->minor = minor;
+
+ err = xen_vbd_create(be->blkif, handle, major, minor,
+ (NULL == strchr(be->mode, 'w')), cdrom);
+ if (err) {
+ be->major = 0;
+ be->minor = 0;
+ xenbus_dev_fatal(dev, err, "creating vbd structure");
+ return;
+ }
+
+ err = xenvbd_sysfs_addif(dev);
+ if (err) {
+ xen_vbd_free(&be->blkif->vbd);
+ be->major = 0;
+ be->minor = 0;
+ xenbus_dev_fatal(dev, err, "creating sysfs entries");
+ return;
+ }
+
+ /* We're potentially connected now */
+ xen_update_blkif_status(be->blkif);
+ }
+}
+
+
+/*
+ * Callback received when the frontend's state changes.
+ */
+static void frontend_changed(struct xenbus_device *dev,
+ enum xenbus_state frontend_state)
+{
+ struct backend_info *be = dev_get_drvdata(&dev->dev);
+ int err;
+
+ DPRINTK("%s", xenbus_strstate(frontend_state));
+
+ switch (frontend_state) {
+ case XenbusStateInitialising:
+ if (dev->state == XenbusStateClosed) {
+ pr_info(DRV_PFX "%s: prepare for reconnect\n",
+ dev->nodename);
+ xenbus_switch_state(dev, XenbusStateInitWait);
+ }
+ break;
+
+ case XenbusStateInitialised:
+ case XenbusStateConnected:
+ /*
+ * Ensure we connect even when two watches fire in
+ * close successsion and we miss the intermediate value
+ * of frontend_state.
+ */
+ if (dev->state == XenbusStateConnected)
+ break;
+
+ /*
+ * Enforce precondition before potential leak point.
+ * blkif_disconnect() is idempotent.
+ */
+ xen_blkif_disconnect(be->blkif);
+
+ err = connect_ring(be);
+ if (err)
+ break;
+ xen_update_blkif_status(be->blkif);
+ break;
+
+ case XenbusStateClosing:
+ xen_blkif_disconnect(be->blkif);
+ xenbus_switch_state(dev, XenbusStateClosing);
+ break;
+
+ case XenbusStateClosed:
+ xenbus_switch_state(dev, XenbusStateClosed);
+ if (xenbus_dev_is_online(dev))
+ break;
+ /* fall through if not online */
+ case XenbusStateUnknown:
+ /* implies blkif_disconnect() via blkback_remove() */
+ device_unregister(&dev->dev);
+ break;
+
+ default:
+ xenbus_dev_fatal(dev, -EINVAL, "saw state %d at frontend",
+ frontend_state);
+ break;
+ }
+}
+
+
+/* ** Connection ** */
+
+
+/*
+ * Write the physical details regarding the block device to the store, and
+ * switch to Connected state.
+ */
+static void connect(struct backend_info *be)
+{
+ struct xenbus_transaction xbt;
+ int err;
+ struct xenbus_device *dev = be->dev;
+
+ DPRINTK("%s", dev->otherend);
+
+ /* Supply the information about the device the frontend needs */
+again:
+ err = xenbus_transaction_start(&xbt);
+ if (err) {
+ xenbus_dev_fatal(dev, err, "starting transaction");
+ return;
+ }
+
+ err = xen_blkbk_flush_diskcache(xbt, be, be->blkif->vbd.flush_support);
+ if (err)
+ goto abort;
+
+ err = xenbus_printf(xbt, dev->nodename, "sectors", "%llu",
+ (unsigned long long)vbd_sz(&be->blkif->vbd));
+ if (err) {
+ xenbus_dev_fatal(dev, err, "writing %s/sectors",
+ dev->nodename);
+ goto abort;
+ }
+
+ /* FIXME: use a typename instead */
+ err = xenbus_printf(xbt, dev->nodename, "info", "%u",
+ be->blkif->vbd.type |
+ (be->blkif->vbd.readonly ? VDISK_READONLY : 0));
+ if (err) {
+ xenbus_dev_fatal(dev, err, "writing %s/info",
+ dev->nodename);
+ goto abort;
+ }
+ err = xenbus_printf(xbt, dev->nodename, "sector-size", "%lu",
+ (unsigned long)
+ bdev_logical_block_size(be->blkif->vbd.bdev));
+ if (err) {
+ xenbus_dev_fatal(dev, err, "writing %s/sector-size",
+ dev->nodename);
+ goto abort;
+ }
+
+ err = xenbus_transaction_end(xbt, 0);
+ if (err == -EAGAIN)
+ goto again;
+ if (err)
+ xenbus_dev_fatal(dev, err, "ending transaction");
+
+ err = xenbus_switch_state(dev, XenbusStateConnected);
+ if (err)
+ xenbus_dev_fatal(dev, err, "switching to Connected state",
+ dev->nodename);
+
+ return;
+ abort:
+ xenbus_transaction_end(xbt, 1);
+}
+
+
+static int connect_ring(struct backend_info *be)
+{
+ struct xenbus_device *dev = be->dev;
+ unsigned long ring_ref;
+ unsigned int evtchn;
+ char protocol[64] = "";
+ int err;
+
+ DPRINTK("%s", dev->otherend);
+
+ err = xenbus_gather(XBT_NIL, dev->otherend, "ring-ref", "%lu",
+ &ring_ref, "event-channel", "%u", &evtchn, NULL);
+ if (err) {
+ xenbus_dev_fatal(dev, err,
+ "reading %s/ring-ref and event-channel",
+ dev->otherend);
+ return err;
+ }
+
+ be->blkif->blk_protocol = BLKIF_PROTOCOL_NATIVE;
+ err = xenbus_gather(XBT_NIL, dev->otherend, "protocol",
+ "%63s", protocol, NULL);
+ if (err)
+ strcpy(protocol, "unspecified, assuming native");
+ else if (0 == strcmp(protocol, XEN_IO_PROTO_ABI_NATIVE))
+ be->blkif->blk_protocol = BLKIF_PROTOCOL_NATIVE;
+ else if (0 == strcmp(protocol, XEN_IO_PROTO_ABI_X86_32))
+ be->blkif->blk_protocol = BLKIF_PROTOCOL_X86_32;
+ else if (0 == strcmp(protocol, XEN_IO_PROTO_ABI_X86_64))
+ be->blkif->blk_protocol = BLKIF_PROTOCOL_X86_64;
+ else {
+ xenbus_dev_fatal(dev, err, "unknown fe protocol %s", protocol);
+ return -1;
+ }
+ pr_info(DRV_PFX "ring-ref %ld, event-channel %d, protocol %d (%s)\n",
+ ring_ref, evtchn, be->blkif->blk_protocol, protocol);
+
+ /* Map the shared frame, irq etc. */
+ err = xen_blkif_map(be->blkif, ring_ref, evtchn);
+ if (err) {
+ xenbus_dev_fatal(dev, err, "mapping ring-ref %lu port %u",
+ ring_ref, evtchn);
+ return err;
+ }
+
+ return 0;
+}
+
+
+/* ** Driver Registration ** */
+
+
+static const struct xenbus_device_id xen_blkbk_ids[] = {
+ { "vbd" },
+ { "" }
+};
+
+
+static struct xenbus_driver xen_blkbk = {
+ .name = "vbd",
+ .owner = THIS_MODULE,
+ .ids = xen_blkbk_ids,
+ .probe = xen_blkbk_probe,
+ .remove = xen_blkbk_remove,
+ .otherend_changed = frontend_changed
+};
+
+
+int xen_blkif_xenbus_init(void)
+{
+ return xenbus_register_backend(&xen_blkbk);
+}
diff --git a/drivers/block/xen-blkfront.c b/drivers/block/xen-blkfront.c
index 9cb8668..b536a9c 100644
--- a/drivers/block/xen-blkfront.c
+++ b/drivers/block/xen-blkfront.c
@@ -97,6 +97,7 @@
struct blk_shadow shadow[BLK_RING_SIZE];
unsigned long shadow_free;
unsigned int feature_flush;
+ unsigned int flush_op;
int is_ready;
};
@@ -250,8 +251,7 @@
/*
* Generate a Xen blkfront IO request from a blk layer request. Reads
- * and writes are handled as expected. Since we lack a loose flush
- * request, we map flushes into a full ordered barrier.
+ * and writes are handled as expected.
*
* @req: a request struct
*/
@@ -293,14 +293,13 @@
if (req->cmd_flags & (REQ_FLUSH | REQ_FUA)) {
/*
- * Ideally we could just do an unordered
- * flush-to-disk, but all we have is a full write
- * barrier at the moment. However, a barrier write is
+ * Ideally we can do an unordered flush-to-disk. In case the
+ * backend onlysupports barriers, use that. A barrier request
* a superset of FUA, so we can implement it the same
* way. (It's also a FLUSH+FUA, since it is
* guaranteed ordered WRT previous writes.)
*/
- ring_req->operation = BLKIF_OP_WRITE_BARRIER;
+ ring_req->operation = info->flush_op;
}
ring_req->nr_segments = blk_rq_map_sg(req->q, req, info->sg);
@@ -433,8 +432,11 @@
static void xlvbd_flush(struct blkfront_info *info)
{
blk_queue_flush(info->rq, info->feature_flush);
- printk(KERN_INFO "blkfront: %s: barriers %s\n",
+ printk(KERN_INFO "blkfront: %s: %s: %s\n",
info->gd->disk_name,
+ info->flush_op == BLKIF_OP_WRITE_BARRIER ?
+ "barrier" : (info->flush_op == BLKIF_OP_FLUSH_DISKCACHE ?
+ "flush diskcache" : "barrier or flush"),
info->feature_flush ? "enabled" : "disabled");
}
@@ -720,15 +722,20 @@
error = (bret->status == BLKIF_RSP_OKAY) ? 0 : -EIO;
switch (bret->operation) {
+ case BLKIF_OP_FLUSH_DISKCACHE:
case BLKIF_OP_WRITE_BARRIER:
if (unlikely(bret->status == BLKIF_RSP_EOPNOTSUPP)) {
- printk(KERN_WARNING "blkfront: %s: write barrier op failed\n",
+ printk(KERN_WARNING "blkfront: %s: write %s op failed\n",
+ info->flush_op == BLKIF_OP_WRITE_BARRIER ?
+ "barrier" : "flush disk cache",
info->gd->disk_name);
error = -EOPNOTSUPP;
}
if (unlikely(bret->status == BLKIF_RSP_ERROR &&
info->shadow[id].req.nr_segments == 0)) {
- printk(KERN_WARNING "blkfront: %s: empty write barrier op failed\n",
+ printk(KERN_WARNING "blkfront: %s: empty write %s op failed\n",
+ info->flush_op == BLKIF_OP_WRITE_BARRIER ?
+ "barrier" : "flush disk cache",
info->gd->disk_name);
error = -EOPNOTSUPP;
}
@@ -736,6 +743,7 @@
if (error == -EOPNOTSUPP)
error = 0;
info->feature_flush = 0;
+ info->flush_op = 0;
xlvbd_flush(info);
}
/* fall through */
@@ -1100,7 +1108,7 @@
unsigned long sector_size;
unsigned int binfo;
int err;
- int barrier;
+ int barrier, flush;
switch (info->connected) {
case BLKIF_STATE_CONNECTED:
@@ -1140,8 +1148,11 @@
return;
}
+ info->feature_flush = 0;
+ info->flush_op = 0;
+
err = xenbus_gather(XBT_NIL, info->xbdev->otherend,
- "feature-barrier", "%lu", &barrier,
+ "feature-barrier", "%d", &barrier,
NULL);
/*
@@ -1151,11 +1162,23 @@
*
* If there are barriers, then we use flush.
*/
- info->feature_flush = 0;
-
- if (!err && barrier)
+ if (!err && barrier) {
info->feature_flush = REQ_FLUSH | REQ_FUA;
+ info->flush_op = BLKIF_OP_WRITE_BARRIER;
+ }
+ /*
+ * And if there is "feature-flush-cache" use that above
+ * barriers.
+ */
+ err = xenbus_gather(XBT_NIL, info->xbdev->otherend,
+ "feature-flush-cache", "%d", &flush,
+ NULL);
+ if (!err && flush) {
+ info->feature_flush = REQ_FLUSH;
+ info->flush_op = BLKIF_OP_FLUSH_DISKCACHE;
+ }
+
err = xlvbd_alloc_gendisk(sectors, info, binfo, sector_size);
if (err) {
xenbus_dev_fatal(info->xbdev, err, "xlvbd_add at %s",
diff --git a/drivers/bluetooth/bluecard_cs.c b/drivers/bluetooth/bluecard_cs.c
index 4104b7f..aed1904 100644
--- a/drivers/bluetooth/bluecard_cs.c
+++ b/drivers/bluetooth/bluecard_cs.c
@@ -930,7 +930,7 @@
pcmcia_disable_device(link);
}
-static struct pcmcia_device_id bluecard_ids[] = {
+static const struct pcmcia_device_id bluecard_ids[] = {
PCMCIA_DEVICE_PROD_ID12("BlueCard", "LSE041", 0xbaf16fbf, 0x657cc15e),
PCMCIA_DEVICE_PROD_ID12("BTCFCARD", "LSE139", 0xe3987764, 0x2524b59c),
PCMCIA_DEVICE_PROD_ID12("WSS", "LSE039", 0x0a0736ec, 0x24e6dfab),
diff --git a/drivers/bluetooth/bt3c_cs.c b/drivers/bluetooth/bt3c_cs.c
index 0c8a655..4fc0194 100644
--- a/drivers/bluetooth/bt3c_cs.c
+++ b/drivers/bluetooth/bt3c_cs.c
@@ -761,7 +761,7 @@
}
-static struct pcmcia_device_id bt3c_ids[] = {
+static const struct pcmcia_device_id bt3c_ids[] = {
PCMCIA_DEVICE_PROD_ID13("3COM", "Bluetooth PC Card", 0xefce0a31, 0xd4ce9b02),
PCMCIA_DEVICE_NULL
};
diff --git a/drivers/bluetooth/btuart_cs.c b/drivers/bluetooth/btuart_cs.c
index f8a0708..526b618 100644
--- a/drivers/bluetooth/btuart_cs.c
+++ b/drivers/bluetooth/btuart_cs.c
@@ -689,7 +689,7 @@
pcmcia_disable_device(link);
}
-static struct pcmcia_device_id btuart_ids[] = {
+static const struct pcmcia_device_id btuart_ids[] = {
/* don't use this driver. Use serial_cs + hci_uart instead */
PCMCIA_DEVICE_NULL
};
diff --git a/drivers/bluetooth/dtl1_cs.c b/drivers/bluetooth/dtl1_cs.c
index 26ee0cf..5e4c2de 100644
--- a/drivers/bluetooth/dtl1_cs.c
+++ b/drivers/bluetooth/dtl1_cs.c
@@ -636,7 +636,7 @@
}
-static struct pcmcia_device_id dtl1_ids[] = {
+static const struct pcmcia_device_id dtl1_ids[] = {
PCMCIA_DEVICE_PROD_ID12("Nokia Mobile Phones", "DTL-1", 0xe1bfdd64, 0xe168480d),
PCMCIA_DEVICE_PROD_ID12("Nokia Mobile Phones", "DTL-4", 0xe1bfdd64, 0x9102bc82),
PCMCIA_DEVICE_PROD_ID12("Socket", "CF", 0xb38bcc2e, 0x44ebf863),
diff --git a/drivers/bluetooth/hci_ldisc.c b/drivers/bluetooth/hci_ldisc.c
index 320f718..b3f0199 100644
--- a/drivers/bluetooth/hci_ldisc.c
+++ b/drivers/bluetooth/hci_ldisc.c
@@ -355,26 +355,29 @@
* flags pointer to flags for data
* count count of received data in bytes
*
- * Return Value: None
+ * Return Value: Number of bytes received
*/
-static void hci_uart_tty_receive(struct tty_struct *tty, const u8 *data, char *flags, int count)
+static unsigned int hci_uart_tty_receive(struct tty_struct *tty,
+ const u8 *data, char *flags, int count)
{
- int ret;
struct hci_uart *hu = (void *)tty->disc_data;
+ int received;
if (!hu || tty != hu->tty)
- return;
+ return -ENODEV;
if (!test_bit(HCI_UART_PROTO_SET, &hu->flags))
- return;
+ return -EINVAL;
spin_lock(&hu->rx_lock);
- ret = hu->proto->recv(hu, (void *) data, count);
- if (ret > 0)
- hu->hdev->stat.byte_rx += count;
+ received = hu->proto->recv(hu, (void *) data, count);
+ if (received > 0)
+ hu->hdev->stat.byte_rx += received;
spin_unlock(&hu->rx_lock);
tty_unthrottle(tty);
+
+ return received;
}
static int hci_uart_register_dev(struct hci_uart *hu)
diff --git a/drivers/cdrom/viocd.c b/drivers/cdrom/viocd.c
index e427fbe..ae15a4d 100644
--- a/drivers/cdrom/viocd.c
+++ b/drivers/cdrom/viocd.c
@@ -625,7 +625,9 @@
blk_queue_max_hw_sectors(q, 4096 / 512);
gendisk->queue = q;
gendisk->fops = &viocd_fops;
- gendisk->flags = GENHD_FL_CD|GENHD_FL_REMOVABLE;
+ gendisk->flags = GENHD_FL_CD | GENHD_FL_REMOVABLE |
+ GENHD_FL_BLOCK_EVENTS_ON_EXCL_WRITE;
+ gendisk->events = DISK_EVENT_MEDIA_CHANGE;
set_capacity(gendisk, 0);
gendisk->private_data = d;
d->viocd_disk = gendisk;
diff --git a/drivers/char/agp/intel-agp.c b/drivers/char/agp/intel-agp.c
index b0a0dcc..b427711 100644
--- a/drivers/char/agp/intel-agp.c
+++ b/drivers/char/agp/intel-agp.c
@@ -903,6 +903,9 @@
ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB),
ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB),
ID(PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB),
+ ID(PCI_DEVICE_ID_INTEL_IVYBRIDGE_HB),
+ ID(PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_HB),
+ ID(PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_HB),
{ }
};
diff --git a/drivers/char/agp/intel-agp.h b/drivers/char/agp/intel-agp.h
index 5feebe2..999803c 100644
--- a/drivers/char/agp/intel-agp.h
+++ b/drivers/char/agp/intel-agp.h
@@ -225,6 +225,14 @@
#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG 0x0126
#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB 0x0108 /* Server */
#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG 0x010A
+#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_HB 0x0150 /* Desktop */
+#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT1_IG 0x0152
+#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT2_IG 0x0162
+#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_HB 0x0154 /* Mobile */
+#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT1_IG 0x0156
+#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT2_IG 0x0166
+#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_HB 0x0158 /* Server */
+#define PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT1_IG 0x015A
int intel_gmch_probe(struct pci_dev *pdev,
struct agp_bridge_data *bridge);
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 0d09b53..8515101 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -1420,6 +1420,16 @@
"Sandybridge", &sandybridge_gtt_driver },
{ PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG,
"Sandybridge", &sandybridge_gtt_driver },
+ { PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT1_IG,
+ "Ivybridge", &sandybridge_gtt_driver },
+ { PCI_DEVICE_ID_INTEL_IVYBRIDGE_GT2_IG,
+ "Ivybridge", &sandybridge_gtt_driver },
+ { PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT1_IG,
+ "Ivybridge", &sandybridge_gtt_driver },
+ { PCI_DEVICE_ID_INTEL_IVYBRIDGE_M_GT2_IG,
+ "Ivybridge", &sandybridge_gtt_driver },
+ { PCI_DEVICE_ID_INTEL_IVYBRIDGE_S_GT1_IG,
+ "Ivybridge", &sandybridge_gtt_driver },
{ 0, NULL, NULL }
};
diff --git a/drivers/char/agp/uninorth-agp.c b/drivers/char/agp/uninorth-agp.c
index f845a8f..a32c492 100644
--- a/drivers/char/agp/uninorth-agp.c
+++ b/drivers/char/agp/uninorth-agp.c
@@ -80,7 +80,7 @@
ctrl | UNI_N_CFG_GART_INVAL);
pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL, ctrl);
- if (uninorth_rev <= 0x30) {
+ if (!mem && uninorth_rev <= 0x30) {
pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL,
ctrl | UNI_N_CFG_GART_2xRESET);
pci_write_config_dword(agp_bridge->dev, UNI_N_CFG_GART_CTRL,
diff --git a/drivers/char/i8k.c b/drivers/char/i8k.c
index d72433f..6e40072 100644
--- a/drivers/char/i8k.c
+++ b/drivers/char/i8k.c
@@ -5,6 +5,9 @@
*
* Copyright (C) 2001 Massimo Dal Zotto <dz@debian.org>
*
+ * Hwmon integration:
+ * Copyright (C) 2011 Jean Delvare <khali@linux-fr.org>
+ *
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2, or (at your option) any
@@ -24,6 +27,8 @@
#include <linux/dmi.h>
#include <linux/capability.h>
#include <linux/mutex.h>
+#include <linux/hwmon.h>
+#include <linux/hwmon-sysfs.h>
#include <asm/uaccess.h>
#include <asm/io.h>
@@ -58,6 +63,7 @@
static DEFINE_MUTEX(i8k_mutex);
static char bios_version[4];
+static struct device *i8k_hwmon_dev;
MODULE_AUTHOR("Massimo Dal Zotto (dz@debian.org)");
MODULE_DESCRIPTION("Driver for accessing SMM BIOS on Dell laptops");
@@ -139,8 +145,8 @@
"movl %%edi,20(%%rax)\n\t"
"popq %%rdx\n\t"
"movl %%edx,0(%%rax)\n\t"
- "lahf\n\t"
- "shrl $8,%%eax\n\t"
+ "pushfq\n\t"
+ "popq %%rax\n\t"
"andl $1,%%eax\n"
:"=a"(rc)
: "a"(regs)
@@ -455,6 +461,152 @@
return single_open(file, i8k_proc_show, NULL);
}
+
+/*
+ * Hwmon interface
+ */
+
+static ssize_t i8k_hwmon_show_temp(struct device *dev,
+ struct device_attribute *devattr,
+ char *buf)
+{
+ int cpu_temp;
+
+ cpu_temp = i8k_get_temp(0);
+ if (cpu_temp < 0)
+ return cpu_temp;
+ return sprintf(buf, "%d\n", cpu_temp * 1000);
+}
+
+static ssize_t i8k_hwmon_show_fan(struct device *dev,
+ struct device_attribute *devattr,
+ char *buf)
+{
+ int index = to_sensor_dev_attr(devattr)->index;
+ int fan_speed;
+
+ fan_speed = i8k_get_fan_speed(index);
+ if (fan_speed < 0)
+ return fan_speed;
+ return sprintf(buf, "%d\n", fan_speed);
+}
+
+static ssize_t i8k_hwmon_show_label(struct device *dev,
+ struct device_attribute *devattr,
+ char *buf)
+{
+ static const char *labels[4] = {
+ "i8k",
+ "CPU",
+ "Left Fan",
+ "Right Fan",
+ };
+ int index = to_sensor_dev_attr(devattr)->index;
+
+ return sprintf(buf, "%s\n", labels[index]);
+}
+
+static DEVICE_ATTR(temp1_input, S_IRUGO, i8k_hwmon_show_temp, NULL);
+static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, i8k_hwmon_show_fan, NULL,
+ I8K_FAN_LEFT);
+static SENSOR_DEVICE_ATTR(fan2_input, S_IRUGO, i8k_hwmon_show_fan, NULL,
+ I8K_FAN_RIGHT);
+static SENSOR_DEVICE_ATTR(name, S_IRUGO, i8k_hwmon_show_label, NULL, 0);
+static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, i8k_hwmon_show_label, NULL, 1);
+static SENSOR_DEVICE_ATTR(fan1_label, S_IRUGO, i8k_hwmon_show_label, NULL, 2);
+static SENSOR_DEVICE_ATTR(fan2_label, S_IRUGO, i8k_hwmon_show_label, NULL, 3);
+
+static void i8k_hwmon_remove_files(struct device *dev)
+{
+ device_remove_file(dev, &dev_attr_temp1_input);
+ device_remove_file(dev, &sensor_dev_attr_fan1_input.dev_attr);
+ device_remove_file(dev, &sensor_dev_attr_fan2_input.dev_attr);
+ device_remove_file(dev, &sensor_dev_attr_temp1_label.dev_attr);
+ device_remove_file(dev, &sensor_dev_attr_fan1_label.dev_attr);
+ device_remove_file(dev, &sensor_dev_attr_fan2_label.dev_attr);
+ device_remove_file(dev, &sensor_dev_attr_name.dev_attr);
+}
+
+static int __init i8k_init_hwmon(void)
+{
+ int err;
+
+ i8k_hwmon_dev = hwmon_device_register(NULL);
+ if (IS_ERR(i8k_hwmon_dev)) {
+ err = PTR_ERR(i8k_hwmon_dev);
+ i8k_hwmon_dev = NULL;
+ printk(KERN_ERR "i8k: hwmon registration failed (%d)\n", err);
+ return err;
+ }
+
+ /* Required name attribute */
+ err = device_create_file(i8k_hwmon_dev,
+ &sensor_dev_attr_name.dev_attr);
+ if (err)
+ goto exit_unregister;
+
+ /* CPU temperature attributes, if temperature reading is OK */
+ err = i8k_get_temp(0);
+ if (err < 0) {
+ dev_dbg(i8k_hwmon_dev,
+ "Not creating temperature attributes (%d)\n", err);
+ } else {
+ err = device_create_file(i8k_hwmon_dev, &dev_attr_temp1_input);
+ if (err)
+ goto exit_remove_files;
+ err = device_create_file(i8k_hwmon_dev,
+ &sensor_dev_attr_temp1_label.dev_attr);
+ if (err)
+ goto exit_remove_files;
+ }
+
+ /* Left fan attributes, if left fan is present */
+ err = i8k_get_fan_status(I8K_FAN_LEFT);
+ if (err < 0) {
+ dev_dbg(i8k_hwmon_dev,
+ "Not creating %s fan attributes (%d)\n", "left", err);
+ } else {
+ err = device_create_file(i8k_hwmon_dev,
+ &sensor_dev_attr_fan1_input.dev_attr);
+ if (err)
+ goto exit_remove_files;
+ err = device_create_file(i8k_hwmon_dev,
+ &sensor_dev_attr_fan1_label.dev_attr);
+ if (err)
+ goto exit_remove_files;
+ }
+
+ /* Right fan attributes, if right fan is present */
+ err = i8k_get_fan_status(I8K_FAN_RIGHT);
+ if (err < 0) {
+ dev_dbg(i8k_hwmon_dev,
+ "Not creating %s fan attributes (%d)\n", "right", err);
+ } else {
+ err = device_create_file(i8k_hwmon_dev,
+ &sensor_dev_attr_fan2_input.dev_attr);
+ if (err)
+ goto exit_remove_files;
+ err = device_create_file(i8k_hwmon_dev,
+ &sensor_dev_attr_fan2_label.dev_attr);
+ if (err)
+ goto exit_remove_files;
+ }
+
+ return 0;
+
+ exit_remove_files:
+ i8k_hwmon_remove_files(i8k_hwmon_dev);
+ exit_unregister:
+ hwmon_device_unregister(i8k_hwmon_dev);
+ return err;
+}
+
+static void __exit i8k_exit_hwmon(void)
+{
+ i8k_hwmon_remove_files(i8k_hwmon_dev);
+ hwmon_device_unregister(i8k_hwmon_dev);
+}
+
static struct dmi_system_id __initdata i8k_dmi_table[] = {
{
.ident = "Dell Inspiron",
@@ -580,6 +732,7 @@
static int __init i8k_init(void)
{
struct proc_dir_entry *proc_i8k;
+ int err;
/* Are we running on an supported laptop? */
if (i8k_probe())
@@ -590,15 +743,24 @@
if (!proc_i8k)
return -ENOENT;
+ err = i8k_init_hwmon();
+ if (err)
+ goto exit_remove_proc;
+
printk(KERN_INFO
"Dell laptop SMM driver v%s Massimo Dal Zotto (dz@debian.org)\n",
I8K_VERSION);
return 0;
+
+ exit_remove_proc:
+ remove_proc_entry("i8k", NULL);
+ return err;
}
static void __exit i8k_exit(void)
{
+ i8k_exit_hwmon();
remove_proc_entry("i8k", NULL);
}
diff --git a/drivers/char/pcmcia/cm4000_cs.c b/drivers/char/pcmcia/cm4000_cs.c
index 90bd016..a758486 100644
--- a/drivers/char/pcmcia/cm4000_cs.c
+++ b/drivers/char/pcmcia/cm4000_cs.c
@@ -1869,7 +1869,7 @@
.llseek = no_llseek,
};
-static struct pcmcia_device_id cm4000_ids[] = {
+static const struct pcmcia_device_id cm4000_ids[] = {
PCMCIA_DEVICE_MANF_CARD(0x0223, 0x0002),
PCMCIA_DEVICE_PROD_ID12("CardMan", "4000", 0x2FB368CA, 0xA2BD8C39),
PCMCIA_DEVICE_NULL,
diff --git a/drivers/char/pcmcia/cm4040_cs.c b/drivers/char/pcmcia/cm4040_cs.c
index 5d8d59e..8dd48a2 100644
--- a/drivers/char/pcmcia/cm4040_cs.c
+++ b/drivers/char/pcmcia/cm4040_cs.c
@@ -633,7 +633,7 @@
.llseek = no_llseek,
};
-static struct pcmcia_device_id cm4040_ids[] = {
+static const struct pcmcia_device_id cm4040_ids[] = {
PCMCIA_DEVICE_MANF_CARD(0x0223, 0x0200),
PCMCIA_DEVICE_PROD_ID12("OMNIKEY", "CardMan 4040",
0xE32CDD8C, 0x8F23318B),
diff --git a/drivers/char/pcmcia/synclink_cs.c b/drivers/char/pcmcia/synclink_cs.c
index b575411..1578139 100644
--- a/drivers/char/pcmcia/synclink_cs.c
+++ b/drivers/char/pcmcia/synclink_cs.c
@@ -2758,7 +2758,7 @@
}
}
-static struct pcmcia_device_id mgslpc_ids[] = {
+static const struct pcmcia_device_id mgslpc_ids[] = {
PCMCIA_DEVICE_MANF_CARD(0x02c5, 0x0050),
PCMCIA_DEVICE_NULL
};
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 110aeeb..96c9219 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -1,2 +1,5 @@
config CLKSRC_I8253
bool
+
+config CLKSRC_MMIO
+ bool
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index cfb6383..b995942 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -7,3 +7,4 @@
obj-$(CONFIG_SH_TIMER_MTU2) += sh_mtu2.o
obj-$(CONFIG_SH_TIMER_TMU) += sh_tmu.o
obj-$(CONFIG_CLKSRC_I8253) += i8253.o
+obj-$(CONFIG_CLKSRC_MMIO) += mmio.o
diff --git a/drivers/clocksource/mmio.c b/drivers/clocksource/mmio.c
new file mode 100644
index 0000000..c0e2512
--- /dev/null
+++ b/drivers/clocksource/mmio.c
@@ -0,0 +1,73 @@
+/*
+ * Generic MMIO clocksource support
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/clocksource.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+
+struct clocksource_mmio {
+ void __iomem *reg;
+ struct clocksource clksrc;
+};
+
+static inline struct clocksource_mmio *to_mmio_clksrc(struct clocksource *c)
+{
+ return container_of(c, struct clocksource_mmio, clksrc);
+}
+
+cycle_t clocksource_mmio_readl_up(struct clocksource *c)
+{
+ return readl_relaxed(to_mmio_clksrc(c)->reg);
+}
+
+cycle_t clocksource_mmio_readl_down(struct clocksource *c)
+{
+ return ~readl_relaxed(to_mmio_clksrc(c)->reg);
+}
+
+cycle_t clocksource_mmio_readw_up(struct clocksource *c)
+{
+ return readw_relaxed(to_mmio_clksrc(c)->reg);
+}
+
+cycle_t clocksource_mmio_readw_down(struct clocksource *c)
+{
+ return ~(unsigned)readw_relaxed(to_mmio_clksrc(c)->reg);
+}
+
+/**
+ * clocksource_mmio_init - Initialize a simple mmio based clocksource
+ * @base: Virtual address of the clock readout register
+ * @name: Name of the clocksource
+ * @hz: Frequency of the clocksource in Hz
+ * @rating: Rating of the clocksource
+ * @bits: Number of valid bits
+ * @read: One of clocksource_mmio_read*() above
+ */
+int __init clocksource_mmio_init(void __iomem *base, const char *name,
+ unsigned long hz, int rating, unsigned bits,
+ cycle_t (*read)(struct clocksource *))
+{
+ struct clocksource_mmio *cs;
+
+ if (bits > 32 || bits < 16)
+ return -EINVAL;
+
+ cs = kzalloc(sizeof(struct clocksource_mmio), GFP_KERNEL);
+ if (!cs)
+ return -ENOMEM;
+
+ cs->reg = base;
+ cs->clksrc.name = name;
+ cs->clksrc.rating = rating;
+ cs->clksrc.read = read;
+ cs->clksrc.mask = CLOCKSOURCE_MASK(bits);
+ cs->clksrc.flags = CLOCK_SOURCE_IS_CONTINUOUS;
+
+ return clocksource_register_hz(&cs->clksrc, hz);
+}
diff --git a/drivers/clocksource/sh_cmt.c b/drivers/clocksource/sh_cmt.c
index f975d24..036e586 100644
--- a/drivers/clocksource/sh_cmt.c
+++ b/drivers/clocksource/sh_cmt.c
@@ -24,6 +24,7 @@
#include <linux/ioport.h>
#include <linux/io.h>
#include <linux/clk.h>
+#include <linux/pm_runtime.h>
#include <linux/irq.h>
#include <linux/err.h>
#include <linux/clocksource.h>
@@ -152,10 +153,12 @@
{
int ret;
- /* enable clock */
+ /* wake up device and enable clock */
+ pm_runtime_get_sync(&p->pdev->dev);
ret = clk_enable(p->clk);
if (ret) {
dev_err(&p->pdev->dev, "cannot enable clock\n");
+ pm_runtime_put_sync(&p->pdev->dev);
return ret;
}
@@ -187,8 +190,9 @@
/* disable interrupts in CMT block */
sh_cmt_write(p, CMCSR, 0);
- /* stop clock */
+ /* stop clock and mark device as idle */
clk_disable(p->clk);
+ pm_runtime_put_sync(&p->pdev->dev);
}
/* private flags */
@@ -416,11 +420,15 @@
static int sh_cmt_clocksource_enable(struct clocksource *cs)
{
+ int ret;
struct sh_cmt_priv *p = cs_to_sh_cmt(cs);
p->total_cycles = 0;
- return sh_cmt_start(p, FLAG_CLOCKSOURCE);
+ ret = sh_cmt_start(p, FLAG_CLOCKSOURCE);
+ if (!ret)
+ __clocksource_updatefreq_hz(cs, p->rate);
+ return ret;
}
static void sh_cmt_clocksource_disable(struct clocksource *cs)
@@ -448,19 +456,10 @@
cs->mask = CLOCKSOURCE_MASK(sizeof(unsigned long) * 8);
cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
- /* clk_get_rate() needs an enabled clock */
- clk_enable(p->clk);
- p->rate = clk_get_rate(p->clk) / ((p->width == 16) ? 512 : 8);
- clk_disable(p->clk);
-
- /* TODO: calculate good shift from rate and counter bit width */
- cs->shift = 0;
- cs->mult = clocksource_hz2mult(p->rate, cs->shift);
-
dev_info(&p->pdev->dev, "used as clock source\n");
- clocksource_register(cs);
-
+ /* Register with dummy 1 Hz value, gets updated in ->enable() */
+ clocksource_register_hz(cs, 1);
return 0;
}
@@ -665,6 +664,7 @@
if (p) {
dev_info(&pdev->dev, "kept as earlytimer\n");
+ pm_runtime_enable(&pdev->dev);
return 0;
}
@@ -679,6 +679,9 @@
kfree(p);
platform_set_drvdata(pdev, NULL);
}
+
+ if (!is_early_platform_device(pdev))
+ pm_runtime_enable(&pdev->dev);
return ret;
}
diff --git a/drivers/clocksource/sh_tmu.c b/drivers/clocksource/sh_tmu.c
index 36aba99..1729628 100644
--- a/drivers/clocksource/sh_tmu.c
+++ b/drivers/clocksource/sh_tmu.c
@@ -25,6 +25,7 @@
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/clk.h>
+#include <linux/pm_runtime.h>
#include <linux/irq.h>
#include <linux/err.h>
#include <linux/clocksource.h>
@@ -109,10 +110,12 @@
{
int ret;
- /* enable clock */
+ /* wake up device and enable clock */
+ pm_runtime_get_sync(&p->pdev->dev);
ret = clk_enable(p->clk);
if (ret) {
dev_err(&p->pdev->dev, "cannot enable clock\n");
+ pm_runtime_put_sync(&p->pdev->dev);
return ret;
}
@@ -141,8 +144,9 @@
/* disable interrupts in TMU block */
sh_tmu_write(p, TCR, 0x0000);
- /* stop clock */
+ /* stop clock and mark device as idle */
clk_disable(p->clk);
+ pm_runtime_put_sync(&p->pdev->dev);
}
static void sh_tmu_set_next(struct sh_tmu_priv *p, unsigned long delta,
@@ -199,8 +203,12 @@
static int sh_tmu_clocksource_enable(struct clocksource *cs)
{
struct sh_tmu_priv *p = cs_to_sh_tmu(cs);
+ int ret;
- return sh_tmu_enable(p);
+ ret = sh_tmu_enable(p);
+ if (!ret)
+ __clocksource_updatefreq_hz(cs, p->rate);
+ return ret;
}
static void sh_tmu_clocksource_disable(struct clocksource *cs)
@@ -221,17 +229,10 @@
cs->mask = CLOCKSOURCE_MASK(32);
cs->flags = CLOCK_SOURCE_IS_CONTINUOUS;
- /* clk_get_rate() needs an enabled clock */
- clk_enable(p->clk);
- /* channel will be configured at parent clock / 4 */
- p->rate = clk_get_rate(p->clk) / 4;
- clk_disable(p->clk);
- /* TODO: calculate good shift from rate and counter bit width */
- cs->shift = 10;
- cs->mult = clocksource_hz2mult(p->rate, cs->shift);
-
dev_info(&p->pdev->dev, "used as clock source\n");
- clocksource_register(cs);
+
+ /* Register with dummy 1 Hz value, gets updated in ->enable() */
+ clocksource_register_hz(cs, 1);
return 0;
}
@@ -414,6 +415,7 @@
if (p) {
dev_info(&pdev->dev, "kept as earlytimer\n");
+ pm_runtime_enable(&pdev->dev);
return 0;
}
@@ -428,6 +430,9 @@
kfree(p);
platform_set_drvdata(pdev, NULL);
}
+
+ if (!is_early_platform_device(pdev))
+ pm_runtime_enable(&pdev->dev);
return ret;
}
diff --git a/drivers/cpufreq/Makefile b/drivers/cpufreq/Makefile
index c7f1a6f..e2fc2d2 100644
--- a/drivers/cpufreq/Makefile
+++ b/drivers/cpufreq/Makefile
@@ -39,3 +39,5 @@
##################################################################################d
+# ARM SoC drivers
+obj-$(CONFIG_UX500_SOC_DB8500) += db8500-cpufreq.o
diff --git a/drivers/cpufreq/db8500-cpufreq.c b/drivers/cpufreq/db8500-cpufreq.c
new file mode 100644
index 0000000..d90456a
--- /dev/null
+++ b/drivers/cpufreq/db8500-cpufreq.c
@@ -0,0 +1,169 @@
+/*
+ * Copyright (C) STMicroelectronics 2009
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * License Terms: GNU General Public License v2
+ * Author: Sundar Iyer <sundar.iyer@stericsson.com>
+ * Author: Martin Persson <martin.persson@stericsson.com>
+ * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/cpufreq.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <linux/mfd/db8500-prcmu.h>
+#include <mach/id.h>
+
+static struct cpufreq_frequency_table freq_table[] = {
+ [0] = {
+ .index = 0,
+ .frequency = 300000,
+ },
+ [1] = {
+ .index = 1,
+ .frequency = 600000,
+ },
+ [2] = {
+ /* Used for MAX_OPP, if available */
+ .index = 2,
+ .frequency = CPUFREQ_TABLE_END,
+ },
+ [3] = {
+ .index = 3,
+ .frequency = CPUFREQ_TABLE_END,
+ },
+};
+
+static enum arm_opp idx2opp[] = {
+ ARM_50_OPP,
+ ARM_100_OPP,
+ ARM_MAX_OPP
+};
+
+static struct freq_attr *db8500_cpufreq_attr[] = {
+ &cpufreq_freq_attr_scaling_available_freqs,
+ NULL,
+};
+
+static int db8500_cpufreq_verify_speed(struct cpufreq_policy *policy)
+{
+ return cpufreq_frequency_table_verify(policy, freq_table);
+}
+
+static int db8500_cpufreq_target(struct cpufreq_policy *policy,
+ unsigned int target_freq,
+ unsigned int relation)
+{
+ struct cpufreq_freqs freqs;
+ unsigned int idx;
+
+ /* scale the target frequency to one of the extremes supported */
+ if (target_freq < policy->cpuinfo.min_freq)
+ target_freq = policy->cpuinfo.min_freq;
+ if (target_freq > policy->cpuinfo.max_freq)
+ target_freq = policy->cpuinfo.max_freq;
+
+ /* Lookup the next frequency */
+ if (cpufreq_frequency_table_target
+ (policy, freq_table, target_freq, relation, &idx)) {
+ return -EINVAL;
+ }
+
+ freqs.old = policy->cur;
+ freqs.new = freq_table[idx].frequency;
+ freqs.cpu = policy->cpu;
+
+ if (freqs.old == freqs.new)
+ return 0;
+
+ /* pre-change notification */
+ cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
+
+ /* request the PRCM unit for opp change */
+ if (prcmu_set_arm_opp(idx2opp[idx])) {
+ pr_err("db8500-cpufreq: Failed to set OPP level\n");
+ return -EINVAL;
+ }
+
+ /* post change notification */
+ cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
+
+ return 0;
+}
+
+static unsigned int db8500_cpufreq_getspeed(unsigned int cpu)
+{
+ int i;
+ /* request the prcm to get the current ARM opp */
+ for (i = 0; prcmu_get_arm_opp() != idx2opp[i]; i++)
+ ;
+ return freq_table[i].frequency;
+}
+
+static int __cpuinit db8500_cpufreq_init(struct cpufreq_policy *policy)
+{
+ int res;
+ int i;
+
+ BUILD_BUG_ON(ARRAY_SIZE(idx2opp) + 1 != ARRAY_SIZE(freq_table));
+
+ if (cpu_is_u8500v2() && !prcmu_is_u8400()) {
+ freq_table[0].frequency = 400000;
+ freq_table[1].frequency = 800000;
+ if (prcmu_has_arm_maxopp())
+ freq_table[2].frequency = 1000000;
+ }
+
+ /* get policy fields based on the table */
+ res = cpufreq_frequency_table_cpuinfo(policy, freq_table);
+ if (!res)
+ cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
+ else {
+ pr_err("db8500-cpufreq : Failed to read policy table\n");
+ return res;
+ }
+
+ policy->min = policy->cpuinfo.min_freq;
+ policy->max = policy->cpuinfo.max_freq;
+ policy->cur = db8500_cpufreq_getspeed(policy->cpu);
+
+ for (i = 0; freq_table[i].frequency != policy->cur; i++)
+ ;
+
+ policy->governor = CPUFREQ_DEFAULT_GOVERNOR;
+
+ /*
+ * FIXME : Need to take time measurement across the target()
+ * function with no/some/all drivers in the notification
+ * list.
+ */
+ policy->cpuinfo.transition_latency = 20 * 1000; /* in ns */
+
+ /* policy sharing between dual CPUs */
+ cpumask_copy(policy->cpus, &cpu_present_map);
+
+ policy->shared_type = CPUFREQ_SHARED_TYPE_ALL;
+
+ return 0;
+}
+
+static struct cpufreq_driver db8500_cpufreq_driver = {
+ .flags = CPUFREQ_STICKY,
+ .verify = db8500_cpufreq_verify_speed,
+ .target = db8500_cpufreq_target,
+ .get = db8500_cpufreq_getspeed,
+ .init = db8500_cpufreq_init,
+ .name = "DB8500",
+ .attr = db8500_cpufreq_attr,
+};
+
+static int __init db8500_cpufreq_register(void)
+{
+ if (!cpu_is_u8500v20_or_later())
+ return -ENODEV;
+
+ pr_info("cpufreq for DB8500 started\n");
+ return cpufreq_register_driver(&db8500_cpufreq_driver);
+}
+device_initcall(db8500_cpufreq_register);
diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index c64c380..e0b25de 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -74,6 +74,8 @@
+ PCI-X Cryptographic Coprocessor (PCIXCC)
+ Crypto Express2 Coprocessor (CEX2C)
+ Crypto Express2 Accelerator (CEX2A)
+ + Crypto Express3 Coprocessor (CEX3C)
+ + Crypto Express3 Accelerator (CEX3A)
config ZCRYPT_MONOLITHIC
bool "Monolithic zcrypt module"
diff --git a/drivers/dma/shdma.c b/drivers/dma/shdma.c
index d50da41..636e409 100644
--- a/drivers/dma/shdma.c
+++ b/drivers/dma/shdma.c
@@ -48,7 +48,7 @@
/*
* Used for write-side mutual exclusion for the global device list,
- * read-side synchronization by way of RCU.
+ * read-side synchronization by way of RCU, and per-controller data.
*/
static DEFINE_SPINLOCK(sh_dmae_lock);
static LIST_HEAD(sh_dmae_devices);
@@ -85,22 +85,35 @@
*/
static void sh_dmae_ctl_stop(struct sh_dmae_device *shdev)
{
- unsigned short dmaor = dmaor_read(shdev);
+ unsigned short dmaor;
+ unsigned long flags;
+ spin_lock_irqsave(&sh_dmae_lock, flags);
+
+ dmaor = dmaor_read(shdev);
dmaor_write(shdev, dmaor & ~(DMAOR_NMIF | DMAOR_AE | DMAOR_DME));
+
+ spin_unlock_irqrestore(&sh_dmae_lock, flags);
}
static int sh_dmae_rst(struct sh_dmae_device *shdev)
{
unsigned short dmaor;
+ unsigned long flags;
- sh_dmae_ctl_stop(shdev);
- dmaor = dmaor_read(shdev) | shdev->pdata->dmaor_init;
+ spin_lock_irqsave(&sh_dmae_lock, flags);
- dmaor_write(shdev, dmaor);
- if (dmaor_read(shdev) & (DMAOR_AE | DMAOR_NMIF)) {
- pr_warning("dma-sh: Can't initialize DMAOR.\n");
- return -EINVAL;
+ dmaor = dmaor_read(shdev) & ~(DMAOR_NMIF | DMAOR_AE | DMAOR_DME);
+
+ dmaor_write(shdev, dmaor | shdev->pdata->dmaor_init);
+
+ dmaor = dmaor_read(shdev);
+
+ spin_unlock_irqrestore(&sh_dmae_lock, flags);
+
+ if (dmaor & (DMAOR_AE | DMAOR_NMIF)) {
+ dev_warn(shdev->common.dev, "Can't initialize DMAOR.\n");
+ return -EIO;
}
return 0;
}
@@ -184,7 +197,7 @@
static int dmae_set_chcr(struct sh_dmae_chan *sh_chan, u32 val)
{
- /* When DMA was working, can not set data to CHCR */
+ /* If DMA is active, cannot set CHCR. TODO: remove this superfluous check */
if (dmae_is_busy(sh_chan))
return -EBUSY;
@@ -200,12 +213,17 @@
struct sh_dmae_device, common);
struct sh_dmae_pdata *pdata = shdev->pdata;
const struct sh_dmae_channel *chan_pdata = &pdata->channel[sh_chan->id];
- u16 __iomem *addr = shdev->dmars + chan_pdata->dmars / sizeof(u16);
+ u16 __iomem *addr = shdev->dmars;
int shift = chan_pdata->dmars_bit;
if (dmae_is_busy(sh_chan))
return -EBUSY;
+ /* in the case of a missing DMARS resource use first memory window */
+ if (!addr)
+ addr = (u16 __iomem *)shdev->chan_reg;
+ addr += chan_pdata->dmars / sizeof(u16);
+
__raw_writew((__raw_readw(addr) & (0xff00 >> shift)) | (val << shift),
addr);
@@ -374,7 +392,12 @@
LIST_HEAD(list);
int descs = sh_chan->descs_allocated;
+ /* Protect against ISR */
+ spin_lock_irq(&sh_chan->desc_lock);
dmae_halt(sh_chan);
+ spin_unlock_irq(&sh_chan->desc_lock);
+
+ /* Now no new interrupts will occur */
/* Prepared and not submitted descriptors can still be on the queue */
if (!list_empty(&sh_chan->ld_queue))
@@ -384,6 +407,7 @@
/* The caller is holding dma_list_mutex */
struct sh_dmae_slave *param = chan->private;
clear_bit(param->slave_id, sh_dmae_slave_used);
+ chan->private = NULL;
}
spin_lock_bh(&sh_chan->desc_lock);
@@ -563,8 +587,6 @@
if (!chan || !len)
return NULL;
- chan->private = NULL;
-
sh_chan = to_sh_chan(chan);
sg_init_table(&sg, 1);
@@ -620,9 +642,9 @@
if (!chan)
return -EINVAL;
+ spin_lock_bh(&sh_chan->desc_lock);
dmae_halt(sh_chan);
- spin_lock_bh(&sh_chan->desc_lock);
if (!list_empty(&sh_chan->ld_queue)) {
/* Record partial transfer */
struct sh_desc *desc = list_entry(sh_chan->ld_queue.next,
@@ -716,6 +738,14 @@
list_move(&desc->node, &sh_chan->ld_free);
}
}
+
+ if (all && !callback)
+ /*
+ * Terminating and the loop completed normally: forgive
+ * uncompleted cookies
+ */
+ sh_chan->completed_cookie = sh_chan->common.cookie;
+
spin_unlock_bh(&sh_chan->desc_lock);
if (callback)
@@ -733,10 +763,6 @@
{
while (__ld_cleanup(sh_chan, all))
;
-
- if (all)
- /* Terminating - forgive uncompleted cookies */
- sh_chan->completed_cookie = sh_chan->common.cookie;
}
static void sh_chan_xfer_ld_queue(struct sh_dmae_chan *sh_chan)
@@ -782,8 +808,10 @@
sh_dmae_chan_ld_cleanup(sh_chan, false);
- last_used = chan->cookie;
+ /* First read completed cookie to avoid a skew */
last_complete = sh_chan->completed_cookie;
+ rmb();
+ last_used = chan->cookie;
BUG_ON(last_complete < 0);
dma_set_tx_state(txstate, last_complete, last_used, 0);
@@ -813,8 +841,12 @@
static irqreturn_t sh_dmae_interrupt(int irq, void *data)
{
irqreturn_t ret = IRQ_NONE;
- struct sh_dmae_chan *sh_chan = (struct sh_dmae_chan *)data;
- u32 chcr = sh_dmae_readl(sh_chan, CHCR);
+ struct sh_dmae_chan *sh_chan = data;
+ u32 chcr;
+
+ spin_lock(&sh_chan->desc_lock);
+
+ chcr = sh_dmae_readl(sh_chan, CHCR);
if (chcr & CHCR_TE) {
/* DMA stop */
@@ -824,10 +856,13 @@
tasklet_schedule(&sh_chan->tasklet);
}
+ spin_unlock(&sh_chan->desc_lock);
+
return ret;
}
-static unsigned int sh_dmae_reset(struct sh_dmae_device *shdev)
+/* Called from error IRQ or NMI */
+static bool sh_dmae_reset(struct sh_dmae_device *shdev)
{
unsigned int handled = 0;
int i;
@@ -839,22 +874,32 @@
for (i = 0; i < SH_DMAC_MAX_CHANNELS; i++) {
struct sh_dmae_chan *sh_chan = shdev->chan[i];
struct sh_desc *desc;
+ LIST_HEAD(dl);
if (!sh_chan)
continue;
+ spin_lock(&sh_chan->desc_lock);
+
/* Stop the channel */
dmae_halt(sh_chan);
+ list_splice_init(&sh_chan->ld_queue, &dl);
+
+ spin_unlock(&sh_chan->desc_lock);
+
/* Complete all */
- list_for_each_entry(desc, &sh_chan->ld_queue, node) {
+ list_for_each_entry(desc, &dl, node) {
struct dma_async_tx_descriptor *tx = &desc->async_tx;
desc->mark = DESC_IDLE;
if (tx->callback)
tx->callback(tx->callback_param);
}
- list_splice_init(&sh_chan->ld_queue, &sh_chan->ld_free);
+ spin_lock(&sh_chan->desc_lock);
+ list_splice(&dl, &sh_chan->ld_free);
+ spin_unlock(&sh_chan->desc_lock);
+
handled++;
}
@@ -867,10 +912,11 @@
{
struct sh_dmae_device *shdev = data;
- if (dmaor_read(shdev) & DMAOR_AE)
- return IRQ_RETVAL(sh_dmae_reset(data));
- else
+ if (!(dmaor_read(shdev) & DMAOR_AE))
return IRQ_NONE;
+
+ sh_dmae_reset(data);
+ return IRQ_HANDLED;
}
static void dmae_do_tasklet(unsigned long data)
@@ -902,17 +948,11 @@
static bool sh_dmae_nmi_notify(struct sh_dmae_device *shdev)
{
- unsigned int handled;
-
/* Fast path out if NMIF is not asserted for this controller */
if ((dmaor_read(shdev) & DMAOR_NMIF) == 0)
return false;
- handled = sh_dmae_reset(shdev);
- if (handled)
- return true;
-
- return false;
+ return sh_dmae_reset(shdev);
}
static int sh_dmae_nmi_handler(struct notifier_block *self,
@@ -982,9 +1022,6 @@
tasklet_init(&new_sh_chan->tasklet, dmae_do_tasklet,
(unsigned long)new_sh_chan);
- /* Init the channel */
- dmae_init(new_sh_chan);
-
spin_lock_init(&new_sh_chan->desc_lock);
/* Init descripter manage list */
@@ -1045,9 +1082,8 @@
struct sh_dmae_pdata *pdata = pdev->dev.platform_data;
unsigned long irqflags = IRQF_DISABLED,
chan_flag[SH_DMAC_MAX_CHANNELS] = {};
- unsigned long flags;
int errirq, chan_irq[SH_DMAC_MAX_CHANNELS];
- int err, i, irq_cnt = 0, irqres = 0;
+ int err, i, irq_cnt = 0, irqres = 0, irq_cap = 0;
struct sh_dmae_device *shdev;
struct resource *chan, *dmars, *errirq_res, *chanirq_res;
@@ -1056,7 +1092,7 @@
return -ENODEV;
chan = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- /* DMARS area is optional, if absent, this controller cannot do slave DMA */
+ /* DMARS area is optional */
dmars = platform_get_resource(pdev, IORESOURCE_MEM, 1);
/*
* IRQ resources:
@@ -1111,11 +1147,11 @@
pm_runtime_enable(&pdev->dev);
pm_runtime_get_sync(&pdev->dev);
- spin_lock_irqsave(&sh_dmae_lock, flags);
+ spin_lock_irq(&sh_dmae_lock);
list_add_tail_rcu(&shdev->node, &sh_dmae_devices);
- spin_unlock_irqrestore(&sh_dmae_lock, flags);
+ spin_unlock_irq(&sh_dmae_lock);
- /* reset dma controller */
+ /* reset dma controller - only needed as a test */
err = sh_dmae_rst(shdev);
if (err)
goto rst_err;
@@ -1123,7 +1159,7 @@
INIT_LIST_HEAD(&shdev->common.channels);
dma_cap_set(DMA_MEMCPY, shdev->common.cap_mask);
- if (dmars)
+ if (pdata->slave && pdata->slave_num)
dma_cap_set(DMA_SLAVE, shdev->common.cap_mask);
shdev->common.device_alloc_chan_resources
@@ -1172,8 +1208,13 @@
!platform_get_resource(pdev, IORESOURCE_IRQ, 1)) {
/* Special case - all multiplexed */
for (; irq_cnt < pdata->channel_num; irq_cnt++) {
- chan_irq[irq_cnt] = chanirq_res->start;
- chan_flag[irq_cnt] = IRQF_SHARED;
+ if (irq_cnt < SH_DMAC_MAX_CHANNELS) {
+ chan_irq[irq_cnt] = chanirq_res->start;
+ chan_flag[irq_cnt] = IRQF_SHARED;
+ } else {
+ irq_cap = 1;
+ break;
+ }
}
} else {
do {
@@ -1187,22 +1228,32 @@
"Found IRQ %d for channel %d\n",
i, irq_cnt);
chan_irq[irq_cnt++] = i;
+
+ if (irq_cnt >= SH_DMAC_MAX_CHANNELS)
+ break;
+ }
+
+ if (irq_cnt >= SH_DMAC_MAX_CHANNELS) {
+ irq_cap = 1;
+ break;
}
chanirq_res = platform_get_resource(pdev,
IORESOURCE_IRQ, ++irqres);
} while (irq_cnt < pdata->channel_num && chanirq_res);
}
- if (irq_cnt < pdata->channel_num)
- goto eirqres;
-
/* Create DMA Channel */
- for (i = 0; i < pdata->channel_num; i++) {
+ for (i = 0; i < irq_cnt; i++) {
err = sh_dmae_chan_probe(shdev, i, chan_irq[i], chan_flag[i]);
if (err)
goto chan_probe_err;
}
+ if (irq_cap)
+ dev_notice(&pdev->dev, "Attempting to register %d DMA "
+ "channels when a maximum of %d are supported.\n",
+ pdata->channel_num, SH_DMAC_MAX_CHANNELS);
+
pm_runtime_put(&pdev->dev);
platform_set_drvdata(pdev, shdev);
@@ -1212,21 +1263,24 @@
chan_probe_err:
sh_dmae_chan_remove(shdev);
-eirqres:
+
#if defined(CONFIG_CPU_SH4) || defined(CONFIG_ARCH_SHMOBILE)
free_irq(errirq, shdev);
eirq_err:
#endif
rst_err:
- spin_lock_irqsave(&sh_dmae_lock, flags);
+ spin_lock_irq(&sh_dmae_lock);
list_del_rcu(&shdev->node);
- spin_unlock_irqrestore(&sh_dmae_lock, flags);
+ spin_unlock_irq(&sh_dmae_lock);
pm_runtime_put(&pdev->dev);
+ pm_runtime_disable(&pdev->dev);
+
if (dmars)
iounmap(shdev->dmars);
emapdmars:
iounmap(shdev->chan_reg);
+ synchronize_rcu();
emapchan:
kfree(shdev);
ealloc:
@@ -1242,7 +1296,6 @@
{
struct sh_dmae_device *shdev = platform_get_drvdata(pdev);
struct resource *res;
- unsigned long flags;
int errirq = platform_get_irq(pdev, 0);
dma_async_device_unregister(&shdev->common);
@@ -1250,9 +1303,9 @@
if (errirq > 0)
free_irq(errirq, shdev);
- spin_lock_irqsave(&sh_dmae_lock, flags);
+ spin_lock_irq(&sh_dmae_lock);
list_del_rcu(&shdev->node);
- spin_unlock_irqrestore(&sh_dmae_lock, flags);
+ spin_unlock_irq(&sh_dmae_lock);
/* channel data remove */
sh_dmae_chan_remove(shdev);
@@ -1263,6 +1316,7 @@
iounmap(shdev->dmars);
iounmap(shdev->chan_reg);
+ synchronize_rcu();
kfree(shdev);
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -1281,12 +1335,78 @@
sh_dmae_ctl_stop(shdev);
}
+static int sh_dmae_runtime_suspend(struct device *dev)
+{
+ return 0;
+}
+
+static int sh_dmae_runtime_resume(struct device *dev)
+{
+ struct sh_dmae_device *shdev = dev_get_drvdata(dev);
+
+ return sh_dmae_rst(shdev);
+}
+
+#ifdef CONFIG_PM
+static int sh_dmae_suspend(struct device *dev)
+{
+ struct sh_dmae_device *shdev = dev_get_drvdata(dev);
+ int i;
+
+ for (i = 0; i < shdev->pdata->channel_num; i++) {
+ struct sh_dmae_chan *sh_chan = shdev->chan[i];
+ if (sh_chan->descs_allocated)
+ sh_chan->pm_error = pm_runtime_put_sync(dev);
+ }
+
+ return 0;
+}
+
+static int sh_dmae_resume(struct device *dev)
+{
+ struct sh_dmae_device *shdev = dev_get_drvdata(dev);
+ int i;
+
+ for (i = 0; i < shdev->pdata->channel_num; i++) {
+ struct sh_dmae_chan *sh_chan = shdev->chan[i];
+ struct sh_dmae_slave *param = sh_chan->common.private;
+
+ if (!sh_chan->descs_allocated)
+ continue;
+
+ if (!sh_chan->pm_error)
+ pm_runtime_get_sync(dev);
+
+ if (param) {
+ const struct sh_dmae_slave_config *cfg = param->config;
+ dmae_set_dmars(sh_chan, cfg->mid_rid);
+ dmae_set_chcr(sh_chan, cfg->chcr);
+ } else {
+ dmae_init(sh_chan);
+ }
+ }
+
+ return 0;
+}
+#else
+#define sh_dmae_suspend NULL
+#define sh_dmae_resume NULL
+#endif
+
+const struct dev_pm_ops sh_dmae_pm = {
+ .suspend = sh_dmae_suspend,
+ .resume = sh_dmae_resume,
+ .runtime_suspend = sh_dmae_runtime_suspend,
+ .runtime_resume = sh_dmae_runtime_resume,
+};
+
static struct platform_driver sh_dmae_driver = {
.remove = __exit_p(sh_dmae_remove),
.shutdown = sh_dmae_shutdown,
.driver = {
.owner = THIS_MODULE,
.name = "sh-dma-engine",
+ .pm = &sh_dmae_pm,
},
};
diff --git a/drivers/dma/shdma.h b/drivers/dma/shdma.h
index 52e4fb1..5ae9fc51 100644
--- a/drivers/dma/shdma.h
+++ b/drivers/dma/shdma.h
@@ -17,7 +17,7 @@
#include <linux/interrupt.h>
#include <linux/list.h>
-#define SH_DMAC_MAX_CHANNELS 6
+#define SH_DMAC_MAX_CHANNELS 20
#define SH_DMA_SLAVE_NUMBER 256
#define SH_DMA_TCR_MAX 0x00FFFFFF /* 16MB */
@@ -37,6 +37,7 @@
int id; /* Raw id of this channel */
u32 __iomem *base;
char dev_id[16]; /* unique name per DMAC of channel */
+ int pm_error;
};
struct sh_dmae_device {
diff --git a/drivers/edac/i3200_edac.c b/drivers/edac/i3200_edac.c
index d41f900..aa08497 100644
--- a/drivers/edac/i3200_edac.c
+++ b/drivers/edac/i3200_edac.c
@@ -101,6 +101,19 @@
static int nr_channels;
+#ifndef readq
+static inline __u64 readq(const volatile void __iomem *addr)
+{
+ const volatile u32 __iomem *p = addr;
+ u32 low, high;
+
+ low = readl(p);
+ high = readl(p + 1);
+
+ return low + ((u64)high << 32);
+}
+#endif
+
static int how_many_channels(struct pci_dev *pdev)
{
unsigned char capid0_8b; /* 8th byte of CAPID0 */
diff --git a/drivers/gpio/ml_ioh_gpio.c b/drivers/gpio/ml_ioh_gpio.c
index 0a775f7..1bc621a 100644
--- a/drivers/gpio/ml_ioh_gpio.c
+++ b/drivers/gpio/ml_ioh_gpio.c
@@ -15,6 +15,7 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
*/
#include <linux/kernel.h>
+#include <linux/slab.h>
#include <linux/pci.h>
#include <linux/gpio.h>
@@ -138,6 +139,7 @@
return 0;
}
+#ifdef CONFIG_PM
/*
* Save register configuration and disable interrupts.
*/
@@ -157,6 +159,7 @@
/* to store contents of PM register */
iowrite32(chip->ioh_gpio_reg.pm_reg, &chip->reg->regs[chip->ch].pm);
}
+#endif
static void ioh_gpio_setup(struct ioh_gpio *chip, int num_port)
{
diff --git a/drivers/gpio/vx855_gpio.c b/drivers/gpio/vx855_gpio.c
index 8a98ee5..ef5aabd 100644
--- a/drivers/gpio/vx855_gpio.c
+++ b/drivers/gpio/vx855_gpio.c
@@ -26,6 +26,7 @@
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/gpio.h>
+#include <linux/slab.h>
#include <linux/device.h>
#include <linux/platform_device.h>
#include <linux/pci.h>
diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
index adc9358..0a9357c 100644
--- a/drivers/gpu/drm/drm_edid.c
+++ b/drivers/gpu/drm/drm_edid.c
@@ -1413,6 +1413,64 @@
EXPORT_SYMBOL(drm_detect_monitor_audio);
/**
+ * drm_add_display_info - pull display info out if present
+ * @edid: EDID data
+ * @info: display info (attached to connector)
+ *
+ * Grab any available display info and stuff it into the drm_display_info
+ * structure that's part of the connector. Useful for tracking bpp and
+ * color spaces.
+ */
+static void drm_add_display_info(struct edid *edid,
+ struct drm_display_info *info)
+{
+ info->width_mm = edid->width_cm * 10;
+ info->height_mm = edid->height_cm * 10;
+
+ /* driver figures it out in this case */
+ info->bpc = 0;
+ info->color_formats = 0;
+
+ /* Only defined for 1.4 with digital displays */
+ if (edid->revision < 4)
+ return;
+
+ if (!(edid->input & DRM_EDID_INPUT_DIGITAL))
+ return;
+
+ switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) {
+ case DRM_EDID_DIGITAL_DEPTH_6:
+ info->bpc = 6;
+ break;
+ case DRM_EDID_DIGITAL_DEPTH_8:
+ info->bpc = 8;
+ break;
+ case DRM_EDID_DIGITAL_DEPTH_10:
+ info->bpc = 10;
+ break;
+ case DRM_EDID_DIGITAL_DEPTH_12:
+ info->bpc = 12;
+ break;
+ case DRM_EDID_DIGITAL_DEPTH_14:
+ info->bpc = 14;
+ break;
+ case DRM_EDID_DIGITAL_DEPTH_16:
+ info->bpc = 16;
+ break;
+ case DRM_EDID_DIGITAL_DEPTH_UNDEF:
+ default:
+ info->bpc = 0;
+ break;
+ }
+
+ info->color_formats = DRM_COLOR_FORMAT_RGB444;
+ if (info->color_formats & DRM_EDID_FEATURE_RGB_YCRCB444)
+ info->color_formats = DRM_COLOR_FORMAT_YCRCB444;
+ if (info->color_formats & DRM_EDID_FEATURE_RGB_YCRCB422)
+ info->color_formats = DRM_COLOR_FORMAT_YCRCB422;
+}
+
+/**
* drm_add_edid_modes - add modes from EDID data, if available
* @connector: connector we're probing
* @edid: edid data
@@ -1460,8 +1518,7 @@
if (quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75))
edid_fixup_preferred(connector, quirks);
- connector->display_info.width_mm = edid->width_cm * 10;
- connector->display_info.height_mm = edid->height_cm * 10;
+ drm_add_display_info(edid, &connector->display_info);
return num_modes;
}
diff --git a/drivers/gpu/drm/drm_fb_helper.c b/drivers/gpu/drm/drm_fb_helper.c
index 140b952..802b61a 100644
--- a/drivers/gpu/drm/drm_fb_helper.c
+++ b/drivers/gpu/drm/drm_fb_helper.c
@@ -70,174 +70,50 @@
}
EXPORT_SYMBOL(drm_fb_helper_single_add_all_connectors);
-/**
- * drm_fb_helper_connector_parse_command_line - parse command line for connector
- * @connector - connector to parse line for
- * @mode_option - per connector mode option
- *
- * This parses the connector specific then generic command lines for
- * modes and options to configure the connector.
- *
- * This uses the same parameters as the fb modedb.c, except for extra
- * <xres>x<yres>[M][R][-<bpp>][@<refresh>][i][m][eDd]
- *
- * enable/enable Digital/disable bit at the end
- */
-static bool drm_fb_helper_connector_parse_command_line(struct drm_fb_helper_connector *fb_helper_conn,
- const char *mode_option)
-{
- const char *name;
- unsigned int namelen;
- int res_specified = 0, bpp_specified = 0, refresh_specified = 0;
- unsigned int xres = 0, yres = 0, bpp = 32, refresh = 0;
- int yres_specified = 0, cvt = 0, rb = 0, interlace = 0, margins = 0;
- int i;
- enum drm_connector_force force = DRM_FORCE_UNSPECIFIED;
- struct drm_fb_helper_cmdline_mode *cmdline_mode;
- struct drm_connector *connector;
-
- if (!fb_helper_conn)
- return false;
- connector = fb_helper_conn->connector;
-
- cmdline_mode = &fb_helper_conn->cmdline_mode;
- if (!mode_option)
- mode_option = fb_mode_option;
-
- if (!mode_option) {
- cmdline_mode->specified = false;
- return false;
- }
-
- name = mode_option;
- namelen = strlen(name);
- for (i = namelen-1; i >= 0; i--) {
- switch (name[i]) {
- case '@':
- namelen = i;
- if (!refresh_specified && !bpp_specified &&
- !yres_specified) {
- refresh = simple_strtol(&name[i+1], NULL, 10);
- refresh_specified = 1;
- if (cvt || rb)
- cvt = 0;
- } else
- goto done;
- break;
- case '-':
- namelen = i;
- if (!bpp_specified && !yres_specified) {
- bpp = simple_strtol(&name[i+1], NULL, 10);
- bpp_specified = 1;
- if (cvt || rb)
- cvt = 0;
- } else
- goto done;
- break;
- case 'x':
- if (!yres_specified) {
- yres = simple_strtol(&name[i+1], NULL, 10);
- yres_specified = 1;
- } else
- goto done;
- case '0' ... '9':
- break;
- case 'M':
- if (!yres_specified)
- cvt = 1;
- break;
- case 'R':
- if (cvt)
- rb = 1;
- break;
- case 'm':
- if (!cvt)
- margins = 1;
- break;
- case 'i':
- if (!cvt)
- interlace = 1;
- break;
- case 'e':
- force = DRM_FORCE_ON;
- break;
- case 'D':
- if ((connector->connector_type != DRM_MODE_CONNECTOR_DVII) &&
- (connector->connector_type != DRM_MODE_CONNECTOR_HDMIB))
- force = DRM_FORCE_ON;
- else
- force = DRM_FORCE_ON_DIGITAL;
- break;
- case 'd':
- force = DRM_FORCE_OFF;
- break;
- default:
- goto done;
- }
- }
- if (i < 0 && yres_specified) {
- xres = simple_strtol(name, NULL, 10);
- res_specified = 1;
- }
-done:
-
- DRM_DEBUG_KMS("cmdline mode for connector %s %dx%d@%dHz%s%s%s\n",
- drm_get_connector_name(connector), xres, yres,
- (refresh) ? refresh : 60, (rb) ? " reduced blanking" :
- "", (margins) ? " with margins" : "", (interlace) ?
- " interlaced" : "");
-
- if (force) {
- const char *s;
- switch (force) {
- case DRM_FORCE_OFF: s = "OFF"; break;
- case DRM_FORCE_ON_DIGITAL: s = "ON - dig"; break;
- default:
- case DRM_FORCE_ON: s = "ON"; break;
- }
-
- DRM_INFO("forcing %s connector %s\n",
- drm_get_connector_name(connector), s);
- connector->force = force;
- }
-
- if (res_specified) {
- cmdline_mode->specified = true;
- cmdline_mode->xres = xres;
- cmdline_mode->yres = yres;
- }
-
- if (refresh_specified) {
- cmdline_mode->refresh_specified = true;
- cmdline_mode->refresh = refresh;
- }
-
- if (bpp_specified) {
- cmdline_mode->bpp_specified = true;
- cmdline_mode->bpp = bpp;
- }
- cmdline_mode->rb = rb ? true : false;
- cmdline_mode->cvt = cvt ? true : false;
- cmdline_mode->interlace = interlace ? true : false;
-
- return true;
-}
-
static int drm_fb_helper_parse_command_line(struct drm_fb_helper *fb_helper)
{
struct drm_fb_helper_connector *fb_helper_conn;
int i;
for (i = 0; i < fb_helper->connector_count; i++) {
+ struct drm_cmdline_mode *mode;
+ struct drm_connector *connector;
char *option = NULL;
fb_helper_conn = fb_helper->connector_info[i];
+ connector = fb_helper_conn->connector;
+ mode = &fb_helper_conn->cmdline_mode;
/* do something on return - turn off connector maybe */
- if (fb_get_options(drm_get_connector_name(fb_helper_conn->connector), &option))
+ if (fb_get_options(drm_get_connector_name(connector), &option))
continue;
- drm_fb_helper_connector_parse_command_line(fb_helper_conn, option);
+ if (drm_mode_parse_command_line_for_connector(option,
+ connector,
+ mode)) {
+ if (mode->force) {
+ const char *s;
+ switch (mode->force) {
+ case DRM_FORCE_OFF: s = "OFF"; break;
+ case DRM_FORCE_ON_DIGITAL: s = "ON - dig"; break;
+ default:
+ case DRM_FORCE_ON: s = "ON"; break;
+ }
+
+ DRM_INFO("forcing %s connector %s\n",
+ drm_get_connector_name(connector), s);
+ connector->force = mode->force;
+ }
+
+ DRM_DEBUG_KMS("cmdline mode for connector %s %dx%d@%dHz%s%s%s\n",
+ drm_get_connector_name(connector),
+ mode->xres, mode->yres,
+ mode->refresh_specified ? mode->refresh : 60,
+ mode->rb ? " reduced blanking" : "",
+ mode->margins ? " with margins" : "",
+ mode->interlace ? " interlaced" : "");
+ }
+
}
return 0;
}
@@ -901,7 +777,7 @@
/* first up get a count of crtcs now in use and new min/maxes width/heights */
for (i = 0; i < fb_helper->connector_count; i++) {
struct drm_fb_helper_connector *fb_helper_conn = fb_helper->connector_info[i];
- struct drm_fb_helper_cmdline_mode *cmdline_mode;
+ struct drm_cmdline_mode *cmdline_mode;
cmdline_mode = &fb_helper_conn->cmdline_mode;
@@ -1123,7 +999,7 @@
static bool drm_has_cmdline_mode(struct drm_fb_helper_connector *fb_connector)
{
- struct drm_fb_helper_cmdline_mode *cmdline_mode;
+ struct drm_cmdline_mode *cmdline_mode;
cmdline_mode = &fb_connector->cmdline_mode;
return cmdline_mode->specified;
}
@@ -1131,7 +1007,7 @@
static struct drm_display_mode *drm_pick_cmdline_mode(struct drm_fb_helper_connector *fb_helper_conn,
int width, int height)
{
- struct drm_fb_helper_cmdline_mode *cmdline_mode;
+ struct drm_cmdline_mode *cmdline_mode;
struct drm_display_mode *mode = NULL;
cmdline_mode = &fb_helper_conn->cmdline_mode;
@@ -1163,19 +1039,8 @@
}
create_mode:
- if (cmdline_mode->cvt)
- mode = drm_cvt_mode(fb_helper_conn->connector->dev,
- cmdline_mode->xres, cmdline_mode->yres,
- cmdline_mode->refresh_specified ? cmdline_mode->refresh : 60,
- cmdline_mode->rb, cmdline_mode->interlace,
- cmdline_mode->margins);
- else
- mode = drm_gtf_mode(fb_helper_conn->connector->dev,
- cmdline_mode->xres, cmdline_mode->yres,
- cmdline_mode->refresh_specified ? cmdline_mode->refresh : 60,
- cmdline_mode->interlace,
- cmdline_mode->margins);
- drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V);
+ mode = drm_mode_create_from_cmdline_mode(fb_helper_conn->connector->dev,
+ cmdline_mode);
list_add(&mode->head, &fb_helper_conn->connector->modes);
return mode;
}
diff --git a/drivers/gpu/drm/drm_irq.c b/drivers/gpu/drm/drm_irq.c
index a1f12cb..2022a5c 100644
--- a/drivers/gpu/drm/drm_irq.c
+++ b/drivers/gpu/drm/drm_irq.c
@@ -684,10 +684,11 @@
*/
*vblank_time = ns_to_timeval(timeval_to_ns(&raw_time) - delta_ns);
- DRM_DEBUG("crtc %d : v %d p(%d,%d)@ %d.%d -> %d.%d [e %d us, %d rep]\n",
- crtc, (int) vbl_status, hpos, vpos, raw_time.tv_sec,
- raw_time.tv_usec, vblank_time->tv_sec, vblank_time->tv_usec,
- (int) duration_ns/1000, i);
+ DRM_DEBUG("crtc %d : v %d p(%d,%d)@ %ld.%ld -> %ld.%ld [e %d us, %d rep]\n",
+ crtc, (int)vbl_status, hpos, vpos,
+ (long)raw_time.tv_sec, (long)raw_time.tv_usec,
+ (long)vblank_time->tv_sec, (long)vblank_time->tv_usec,
+ (int)duration_ns/1000, i);
vbl_status = DRM_VBLANKTIME_SCANOUTPOS_METHOD;
if (invbl)
diff --git a/drivers/gpu/drm/drm_modes.c b/drivers/gpu/drm/drm_modes.c
index 25bf873..c2d32f2 100644
--- a/drivers/gpu/drm/drm_modes.c
+++ b/drivers/gpu/drm/drm_modes.c
@@ -974,3 +974,159 @@
}
}
EXPORT_SYMBOL(drm_mode_connector_list_update);
+
+/**
+ * drm_mode_parse_command_line_for_connector - parse command line for connector
+ * @mode_option - per connector mode option
+ * @connector - connector to parse line for
+ *
+ * This parses the connector specific then generic command lines for
+ * modes and options to configure the connector.
+ *
+ * This uses the same parameters as the fb modedb.c, except for extra
+ * <xres>x<yres>[M][R][-<bpp>][@<refresh>][i][m][eDd]
+ *
+ * enable/enable Digital/disable bit at the end
+ */
+bool drm_mode_parse_command_line_for_connector(const char *mode_option,
+ struct drm_connector *connector,
+ struct drm_cmdline_mode *mode)
+{
+ const char *name;
+ unsigned int namelen;
+ int res_specified = 0, bpp_specified = 0, refresh_specified = 0;
+ unsigned int xres = 0, yres = 0, bpp = 32, refresh = 0;
+ int yres_specified = 0, cvt = 0, rb = 0, interlace = 0, margins = 0;
+ int i;
+ enum drm_connector_force force = DRM_FORCE_UNSPECIFIED;
+
+#ifdef CONFIG_FB
+ if (!mode_option)
+ mode_option = fb_mode_option;
+#endif
+
+ if (!mode_option) {
+ mode->specified = false;
+ return false;
+ }
+
+ name = mode_option;
+ namelen = strlen(name);
+ for (i = namelen-1; i >= 0; i--) {
+ switch (name[i]) {
+ case '@':
+ namelen = i;
+ if (!refresh_specified && !bpp_specified &&
+ !yres_specified) {
+ refresh = simple_strtol(&name[i+1], NULL, 10);
+ refresh_specified = 1;
+ if (cvt || rb)
+ cvt = 0;
+ } else
+ goto done;
+ break;
+ case '-':
+ namelen = i;
+ if (!bpp_specified && !yres_specified) {
+ bpp = simple_strtol(&name[i+1], NULL, 10);
+ bpp_specified = 1;
+ if (cvt || rb)
+ cvt = 0;
+ } else
+ goto done;
+ break;
+ case 'x':
+ if (!yres_specified) {
+ yres = simple_strtol(&name[i+1], NULL, 10);
+ yres_specified = 1;
+ } else
+ goto done;
+ case '0' ... '9':
+ break;
+ case 'M':
+ if (!yres_specified)
+ cvt = 1;
+ break;
+ case 'R':
+ if (cvt)
+ rb = 1;
+ break;
+ case 'm':
+ if (!cvt)
+ margins = 1;
+ break;
+ case 'i':
+ if (!cvt)
+ interlace = 1;
+ break;
+ case 'e':
+ force = DRM_FORCE_ON;
+ break;
+ case 'D':
+ if ((connector->connector_type != DRM_MODE_CONNECTOR_DVII) &&
+ (connector->connector_type != DRM_MODE_CONNECTOR_HDMIB))
+ force = DRM_FORCE_ON;
+ else
+ force = DRM_FORCE_ON_DIGITAL;
+ break;
+ case 'd':
+ force = DRM_FORCE_OFF;
+ break;
+ default:
+ goto done;
+ }
+ }
+ if (i < 0 && yres_specified) {
+ xres = simple_strtol(name, NULL, 10);
+ res_specified = 1;
+ }
+done:
+ if (res_specified) {
+ mode->specified = true;
+ mode->xres = xres;
+ mode->yres = yres;
+ }
+
+ if (refresh_specified) {
+ mode->refresh_specified = true;
+ mode->refresh = refresh;
+ }
+
+ if (bpp_specified) {
+ mode->bpp_specified = true;
+ mode->bpp = bpp;
+ }
+ mode->rb = rb ? true : false;
+ mode->cvt = cvt ? true : false;
+ mode->interlace = interlace ? true : false;
+ mode->force = force;
+
+ return true;
+}
+EXPORT_SYMBOL(drm_mode_parse_command_line_for_connector);
+
+struct drm_display_mode *
+drm_mode_create_from_cmdline_mode(struct drm_device *dev,
+ struct drm_cmdline_mode *cmd)
+{
+ struct drm_display_mode *mode;
+
+ if (cmd->cvt)
+ mode = drm_cvt_mode(dev,
+ cmd->xres, cmd->yres,
+ cmd->refresh_specified ? cmd->refresh : 60,
+ cmd->rb, cmd->interlace,
+ cmd->margins);
+ else
+ mode = drm_gtf_mode(dev,
+ cmd->xres, cmd->yres,
+ cmd->refresh_specified ? cmd->refresh : 60,
+ cmd->interlace,
+ cmd->margins);
+ if (!mode)
+ return NULL;
+
+ drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V);
+ return mode;
+}
+EXPORT_SYMBOL(drm_mode_create_from_cmdline_mode);
diff --git a/drivers/gpu/drm/drm_stub.c b/drivers/gpu/drm/drm_stub.c
index 001273d..6d7b083 100644
--- a/drivers/gpu/drm/drm_stub.c
+++ b/drivers/gpu/drm/drm_stub.c
@@ -62,6 +62,26 @@
struct class *drm_class;
struct proc_dir_entry *drm_proc_root;
struct dentry *drm_debugfs_root;
+
+int drm_err(const char *func, const char *format, ...)
+{
+ struct va_format vaf;
+ va_list args;
+ int r;
+
+ va_start(args, format);
+
+ vaf.fmt = format;
+ vaf.va = &args;
+
+ r = printk(KERN_ERR "[" DRM_NAME ":%s] *ERROR* %pV", func, &vaf);
+
+ va_end(args);
+
+ return r;
+}
+EXPORT_SYMBOL(drm_err);
+
void drm_ut_debug_printk(unsigned int request_level,
const char *prefix,
const char *function_name,
@@ -78,6 +98,7 @@
}
}
EXPORT_SYMBOL(drm_ut_debug_printk);
+
static int drm_minor_get_id(struct drm_device *dev, int type)
{
int new_id;
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 87c8e29..51c2257 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -106,11 +106,12 @@
}
}
-static const char *agp_type_str(int type)
+static const char *cache_level_str(int type)
{
switch (type) {
- case 0: return " uncached";
- case 1: return " snooped";
+ case I915_CACHE_NONE: return " uncached";
+ case I915_CACHE_LLC: return " snooped (LLC)";
+ case I915_CACHE_LLC_MLC: return " snooped (LLC+MLC)";
default: return "";
}
}
@@ -127,7 +128,7 @@
obj->base.write_domain,
obj->last_rendering_seqno,
obj->last_fenced_seqno,
- agp_type_str(obj->agp_type == AGP_USER_CACHED_MEMORY),
+ cache_level_str(obj->cache_level),
obj->dirty ? " dirty" : "",
obj->madv == I915_MADV_DONTNEED ? " purgeable" : "");
if (obj->base.name)
@@ -714,7 +715,7 @@
dirty_flag(err->dirty),
purgeable_flag(err->purgeable),
ring_str(err->ring),
- agp_type_str(err->agp_type));
+ cache_level_str(err->cache_level));
if (err->name)
seq_printf(m, " (name: %d)", err->name);
@@ -852,6 +853,7 @@
struct drm_info_node *node = (struct drm_info_node *) m->private;
struct drm_device *dev = node->minor->dev;
drm_i915_private_t *dev_priv = dev->dev_private;
+ int ret;
if (IS_GEN5(dev)) {
u16 rgvswctl = I915_READ16(MEMSWCTL);
@@ -873,7 +875,11 @@
int max_freq;
/* RPSTAT1 is in the GT power well */
- __gen6_gt_force_wake_get(dev_priv);
+ ret = mutex_lock_interruptible(&dev->struct_mutex);
+ if (ret)
+ return ret;
+
+ gen6_gt_force_wake_get(dev_priv);
rpstat = I915_READ(GEN6_RPSTAT1);
rpupei = I915_READ(GEN6_RP_CUR_UP_EI);
@@ -883,6 +889,9 @@
rpcurdown = I915_READ(GEN6_RP_CUR_DOWN);
rpprevdown = I915_READ(GEN6_RP_PREV_DOWN);
+ gen6_gt_force_wake_put(dev_priv);
+ mutex_unlock(&dev->struct_mutex);
+
seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
seq_printf(m, "Render p-state ratio: %d\n",
@@ -917,8 +926,6 @@
max_freq = rp_state_cap & 0xff;
seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
max_freq * 50);
-
- __gen6_gt_force_wake_put(dev_priv);
} else {
seq_printf(m, "no P-state info available\n");
}
@@ -1058,6 +1065,9 @@
case FBC_MULTIPLE_PIPES:
seq_printf(m, "multiple pipes are enabled");
break;
+ case FBC_MODULE_PARAM:
+ seq_printf(m, "disabled per module param (default off)");
+ break;
default:
seq_printf(m, "unknown reason");
}
@@ -1186,6 +1196,42 @@
return 0;
}
+static int i915_context_status(struct seq_file *m, void *unused)
+{
+ struct drm_info_node *node = (struct drm_info_node *) m->private;
+ struct drm_device *dev = node->minor->dev;
+ drm_i915_private_t *dev_priv = dev->dev_private;
+ int ret;
+
+ ret = mutex_lock_interruptible(&dev->mode_config.mutex);
+ if (ret)
+ return ret;
+
+ seq_printf(m, "power context ");
+ describe_obj(m, dev_priv->pwrctx);
+ seq_printf(m, "\n");
+
+ seq_printf(m, "render context ");
+ describe_obj(m, dev_priv->renderctx);
+ seq_printf(m, "\n");
+
+ mutex_unlock(&dev->mode_config.mutex);
+
+ return 0;
+}
+
+static int i915_gen6_forcewake_count_info(struct seq_file *m, void *data)
+{
+ struct drm_info_node *node = (struct drm_info_node *) m->private;
+ struct drm_device *dev = node->minor->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ seq_printf(m, "forcewake count = %d\n",
+ atomic_read(&dev_priv->forcewake_count));
+
+ return 0;
+}
+
static int
i915_wedged_open(struct inode *inode,
struct file *filp)
@@ -1288,6 +1334,67 @@
return drm_add_fake_info_node(minor, ent, &i915_wedged_fops);
}
+static int i915_forcewake_open(struct inode *inode, struct file *file)
+{
+ struct drm_device *dev = inode->i_private;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ int ret;
+
+ if (!IS_GEN6(dev))
+ return 0;
+
+ ret = mutex_lock_interruptible(&dev->struct_mutex);
+ if (ret)
+ return ret;
+ gen6_gt_force_wake_get(dev_priv);
+ mutex_unlock(&dev->struct_mutex);
+
+ return 0;
+}
+
+int i915_forcewake_release(struct inode *inode, struct file *file)
+{
+ struct drm_device *dev = inode->i_private;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ if (!IS_GEN6(dev))
+ return 0;
+
+ /*
+ * It's bad that we can potentially hang userspace if struct_mutex gets
+ * forever stuck. However, if we cannot acquire this lock it means that
+ * almost certainly the driver has hung, is not unload-able. Therefore
+ * hanging here is probably a minor inconvenience not to be seen my
+ * almost every user.
+ */
+ mutex_lock(&dev->struct_mutex);
+ gen6_gt_force_wake_put(dev_priv);
+ mutex_unlock(&dev->struct_mutex);
+
+ return 0;
+}
+
+static const struct file_operations i915_forcewake_fops = {
+ .owner = THIS_MODULE,
+ .open = i915_forcewake_open,
+ .release = i915_forcewake_release,
+};
+
+static int i915_forcewake_create(struct dentry *root, struct drm_minor *minor)
+{
+ struct drm_device *dev = minor->dev;
+ struct dentry *ent;
+
+ ent = debugfs_create_file("i915_forcewake_user",
+ S_IRUSR,
+ root, dev,
+ &i915_forcewake_fops);
+ if (IS_ERR(ent))
+ return PTR_ERR(ent);
+
+ return drm_add_fake_info_node(minor, ent, &i915_forcewake_fops);
+}
+
static struct drm_info_list i915_debugfs_list[] = {
{"i915_capabilities", i915_capabilities, 0},
{"i915_gem_objects", i915_gem_object_info, 0},
@@ -1324,6 +1431,8 @@
{"i915_sr_status", i915_sr_status, 0},
{"i915_opregion", i915_opregion, 0},
{"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
+ {"i915_context_status", i915_context_status, 0},
+ {"i915_gen6_forcewake_count", i915_gen6_forcewake_count_info, 0},
};
#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
@@ -1335,6 +1444,10 @@
if (ret)
return ret;
+ ret = i915_forcewake_create(minor->debugfs_root, minor);
+ if (ret)
+ return ret;
+
return drm_debugfs_create_files(i915_debugfs_list,
I915_DEBUGFS_ENTRIES,
minor->debugfs_root, minor);
@@ -1344,6 +1457,8 @@
{
drm_debugfs_remove_files(i915_debugfs_list,
I915_DEBUGFS_ENTRIES, minor);
+ drm_debugfs_remove_files((struct drm_info_list *) &i915_forcewake_fops,
+ 1, minor);
drm_debugfs_remove_files((struct drm_info_list *) &i915_wedged_fops,
1, minor);
}
diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c
index 12876f2..0239e99 100644
--- a/drivers/gpu/drm/i915/i915_dma.c
+++ b/drivers/gpu/drm/i915/i915_dma.c
@@ -571,7 +571,7 @@
struct intel_ring_buffer *ring = LP_RING(dev->dev_private);
i915_kernel_lost_context(dev);
- return intel_wait_ring_buffer(ring, ring->size - 8);
+ return intel_wait_ring_idle(ring);
}
static int i915_flush_ioctl(struct drm_device *dev, void *data,
@@ -1176,11 +1176,11 @@
return can_switch;
}
-static int i915_load_modeset_init(struct drm_device *dev)
+static int i915_load_gem_init(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
unsigned long prealloc_size, gtt_size, mappable_size;
- int ret = 0;
+ int ret;
prealloc_size = dev_priv->mm.gtt->stolen_size;
gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT;
@@ -1204,7 +1204,7 @@
ret = i915_gem_init_ringbuffer(dev);
mutex_unlock(&dev->struct_mutex);
if (ret)
- goto out;
+ return ret;
/* Try to set up FBC with a reasonable compressed buffer size */
if (I915_HAS_FBC(dev) && i915_powersave) {
@@ -1222,6 +1222,13 @@
/* Allow hardware batchbuffers unless told otherwise. */
dev_priv->allow_batchbuffer = 1;
+ return 0;
+}
+
+static int i915_load_modeset_init(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ int ret;
ret = intel_parse_bios(dev);
if (ret)
@@ -1236,7 +1243,7 @@
*/
ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
if (ret && ret != -ENODEV)
- goto cleanup_ringbuffer;
+ goto out;
intel_register_dsm_handler();
@@ -1253,10 +1260,40 @@
intel_modeset_init(dev);
- ret = drm_irq_install(dev);
+ ret = i915_load_gem_init(dev);
if (ret)
goto cleanup_vga_switcheroo;
+ intel_modeset_gem_init(dev);
+
+ if (IS_IVYBRIDGE(dev)) {
+ /* Share pre & uninstall handlers with ILK/SNB */
+ dev->driver->irq_handler = ivybridge_irq_handler;
+ dev->driver->irq_preinstall = ironlake_irq_preinstall;
+ dev->driver->irq_postinstall = ivybridge_irq_postinstall;
+ dev->driver->irq_uninstall = ironlake_irq_uninstall;
+ dev->driver->enable_vblank = ivybridge_enable_vblank;
+ dev->driver->disable_vblank = ivybridge_disable_vblank;
+ } else if (HAS_PCH_SPLIT(dev)) {
+ dev->driver->irq_handler = ironlake_irq_handler;
+ dev->driver->irq_preinstall = ironlake_irq_preinstall;
+ dev->driver->irq_postinstall = ironlake_irq_postinstall;
+ dev->driver->irq_uninstall = ironlake_irq_uninstall;
+ dev->driver->enable_vblank = ironlake_enable_vblank;
+ dev->driver->disable_vblank = ironlake_disable_vblank;
+ } else {
+ dev->driver->irq_preinstall = i915_driver_irq_preinstall;
+ dev->driver->irq_postinstall = i915_driver_irq_postinstall;
+ dev->driver->irq_uninstall = i915_driver_irq_uninstall;
+ dev->driver->irq_handler = i915_driver_irq_handler;
+ dev->driver->enable_vblank = i915_enable_vblank;
+ dev->driver->disable_vblank = i915_disable_vblank;
+ }
+
+ ret = drm_irq_install(dev);
+ if (ret)
+ goto cleanup_gem;
+
/* Always safe in the mode setting case. */
/* FIXME: do pre/post-mode set stuff in core KMS code */
dev->vblank_disable_allowed = 1;
@@ -1274,14 +1311,14 @@
cleanup_irq:
drm_irq_uninstall(dev);
+cleanup_gem:
+ mutex_lock(&dev->struct_mutex);
+ i915_gem_cleanup_ringbuffer(dev);
+ mutex_unlock(&dev->struct_mutex);
cleanup_vga_switcheroo:
vga_switcheroo_unregister_client(dev->pdev);
cleanup_vga_client:
vga_client_register(dev->pdev, NULL, NULL, NULL);
-cleanup_ringbuffer:
- mutex_lock(&dev->struct_mutex);
- i915_gem_cleanup_ringbuffer(dev);
- mutex_unlock(&dev->struct_mutex);
out:
return ret;
}
@@ -1982,7 +2019,7 @@
dev->driver->get_vblank_counter = i915_get_vblank_counter;
dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
- if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev)) {
+ if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
dev->driver->get_vblank_counter = gm45_get_vblank_counter;
}
@@ -2025,6 +2062,7 @@
spin_lock_init(&dev_priv->irq_lock);
spin_lock_init(&dev_priv->error_lock);
+ spin_lock_init(&dev_priv->rps_lock);
if (IS_MOBILE(dev) || !IS_GEN2(dev))
dev_priv->num_pipe = 2;
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 32d1b3e..0defd42 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -52,9 +52,12 @@
unsigned int i915_semaphores = 0;
module_param_named(semaphores, i915_semaphores, int, 0600);
-unsigned int i915_enable_rc6 = 0;
+unsigned int i915_enable_rc6 = 1;
module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600);
+unsigned int i915_enable_fbc = 0;
+module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
+
unsigned int i915_lvds_downclock = 0;
module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
@@ -169,7 +172,7 @@
static const struct intel_device_info intel_ironlake_m_info = {
.gen = 5, .is_mobile = 1,
.need_gfx_hws = 1, .has_hotplug = 1,
- .has_fbc = 0, /* disabled due to buggy hardware */
+ .has_fbc = 1,
.has_bsd_ring = 1,
};
@@ -188,6 +191,21 @@
.has_blt_ring = 1,
};
+static const struct intel_device_info intel_ivybridge_d_info = {
+ .is_ivybridge = 1, .gen = 7,
+ .need_gfx_hws = 1, .has_hotplug = 1,
+ .has_bsd_ring = 1,
+ .has_blt_ring = 1,
+};
+
+static const struct intel_device_info intel_ivybridge_m_info = {
+ .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
+ .need_gfx_hws = 1, .has_hotplug = 1,
+ .has_fbc = 0, /* FBC is not enabled on Ivybridge mobile yet */
+ .has_bsd_ring = 1,
+ .has_blt_ring = 1,
+};
+
static const struct pci_device_id pciidlist[] = { /* aka */
INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */
INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */
@@ -227,6 +245,11 @@
INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
+ INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
+ INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
+ INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
+ INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
+ INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
{0, 0, 0}
};
@@ -235,7 +258,9 @@
#endif
#define INTEL_PCH_DEVICE_ID_MASK 0xff00
+#define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
#define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
+#define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
void intel_detect_pch (struct drm_device *dev)
{
@@ -254,16 +279,23 @@
int id;
id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
- if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
+ if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
+ dev_priv->pch_type = PCH_IBX;
+ DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
+ } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
dev_priv->pch_type = PCH_CPT;
DRM_DEBUG_KMS("Found CougarPoint PCH\n");
+ } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
+ /* PantherPoint is CPT compatible */
+ dev_priv->pch_type = PCH_CPT;
+ DRM_DEBUG_KMS("Found PatherPoint PCH\n");
}
}
pci_dev_put(pch);
}
}
-void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
+static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
{
int count;
@@ -279,12 +311,38 @@
udelay(10);
}
-void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
+/*
+ * Generally this is called implicitly by the register read function. However,
+ * if some sequence requires the GT to not power down then this function should
+ * be called at the beginning of the sequence followed by a call to
+ * gen6_gt_force_wake_put() at the end of the sequence.
+ */
+void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
+{
+ WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
+
+ /* Forcewake is atomic in case we get in here without the lock */
+ if (atomic_add_return(1, &dev_priv->forcewake_count) == 1)
+ __gen6_gt_force_wake_get(dev_priv);
+}
+
+static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
{
I915_WRITE_NOTRACE(FORCEWAKE, 0);
POSTING_READ(FORCEWAKE);
}
+/*
+ * see gen6_gt_force_wake_get()
+ */
+void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
+{
+ WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
+
+ if (atomic_dec_and_test(&dev_priv->forcewake_count))
+ __gen6_gt_force_wake_put(dev_priv);
+}
+
void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
{
int loop = 500;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1c1b27c..ee66035 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -188,7 +188,7 @@
u32 dirty:1;
u32 purgeable:1;
u32 ring:4;
- u32 agp_type:1;
+ u32 cache_level:2;
} *active_bo, *pinned_bo;
u32 active_bo_count, pinned_bo_count;
struct intel_overlay_error_state *overlay;
@@ -203,12 +203,19 @@
int (*get_display_clock_speed)(struct drm_device *dev);
int (*get_fifo_size)(struct drm_device *dev, int plane);
void (*update_wm)(struct drm_device *dev);
+ int (*crtc_mode_set)(struct drm_crtc *crtc,
+ struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode,
+ int x, int y,
+ struct drm_framebuffer *old_fb);
+ void (*fdi_link_train)(struct drm_crtc *crtc);
+ void (*init_clock_gating)(struct drm_device *dev);
+ void (*init_pch_clock_gating)(struct drm_device *dev);
/* clock updates for mode set */
/* cursor updates */
/* render clock increase/decrease */
/* display clock increase/decrease */
/* pll clock increase/decrease */
- /* clock gating init */
};
struct intel_device_info {
@@ -223,6 +230,7 @@
u8 is_pineview : 1;
u8 is_broadwater : 1;
u8 is_crestline : 1;
+ u8 is_ivybridge : 1;
u8 has_fbc : 1;
u8 has_pipe_cxsr : 1;
u8 has_hotplug : 1;
@@ -242,6 +250,7 @@
FBC_BAD_PLANE, /* fbc not supported on plane */
FBC_NOT_TILED, /* buffer not tiled */
FBC_MULTIPLE_PIPES, /* more than one pipe active */
+ FBC_MODULE_PARAM,
};
enum intel_pch {
@@ -676,6 +685,10 @@
bool mchbar_need_disable;
+ struct work_struct rps_work;
+ spinlock_t rps_lock;
+ u32 pm_iir;
+
u8 cur_delay;
u8 min_delay;
u8 max_delay;
@@ -703,8 +716,16 @@
struct intel_fbdev *fbdev;
struct drm_property *broadcast_rgb_property;
+
+ atomic_t forcewake_count;
} drm_i915_private_t;
+enum i915_cache_level {
+ I915_CACHE_NONE,
+ I915_CACHE_LLC,
+ I915_CACHE_LLC_MLC, /* gen6+ */
+};
+
struct drm_i915_gem_object {
struct drm_gem_object base;
@@ -791,6 +812,8 @@
unsigned int pending_fenced_gpu_access:1;
unsigned int fenced_gpu_access:1;
+ unsigned int cache_level:2;
+
struct page **pages;
/**
@@ -827,8 +850,6 @@
/** Record of address bit 17 of each page at last unbind. */
unsigned long *bit_17;
- /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
- uint32_t agp_type;
/**
* If present, while GEM_DOMAIN_CPU is in the read domain this array
@@ -915,13 +936,21 @@
#define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
#define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
#define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
+#define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
#define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
+/*
+ * The genX designation typically refers to the render engine, so render
+ * capability related checks should use IS_GEN, while display and other checks
+ * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
+ * chips, etc.).
+ */
#define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
#define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
#define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
#define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
#define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
+#define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
#define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
#define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
@@ -948,8 +977,8 @@
#define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
#define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
-#define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev))
-#define HAS_PIPE_CONTROL(dev) (IS_GEN5(dev) || IS_GEN6(dev))
+#define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev))
+#define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
#define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
#define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
@@ -967,6 +996,7 @@
extern unsigned int i915_panel_use_ssc;
extern int i915_vbt_sdvo_panel_type;
extern unsigned int i915_enable_rc6;
+extern unsigned int i915_enable_fbc;
extern int i915_suspend(struct drm_device *dev, pm_message_t state);
extern int i915_resume(struct drm_device *dev);
@@ -1010,12 +1040,27 @@
extern void i915_driver_irq_preinstall(struct drm_device * dev);
extern int i915_driver_irq_postinstall(struct drm_device *dev);
extern void i915_driver_irq_uninstall(struct drm_device * dev);
+
+extern irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS);
+extern void ironlake_irq_preinstall(struct drm_device *dev);
+extern int ironlake_irq_postinstall(struct drm_device *dev);
+extern void ironlake_irq_uninstall(struct drm_device *dev);
+
+extern irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS);
+extern void ivybridge_irq_preinstall(struct drm_device *dev);
+extern int ivybridge_irq_postinstall(struct drm_device *dev);
+extern void ivybridge_irq_uninstall(struct drm_device *dev);
+
extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
struct drm_file *file_priv);
extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
struct drm_file *file_priv);
extern int i915_enable_vblank(struct drm_device *dev, int crtc);
extern void i915_disable_vblank(struct drm_device *dev, int crtc);
+extern int ironlake_enable_vblank(struct drm_device *dev, int crtc);
+extern void ironlake_disable_vblank(struct drm_device *dev, int crtc);
+extern int ivybridge_enable_vblank(struct drm_device *dev, int crtc);
+extern void ivybridge_disable_vblank(struct drm_device *dev, int crtc);
extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
extern int i915_vblank_swap(struct drm_device *dev, void *data,
@@ -1265,6 +1310,7 @@
/* modesetting */
extern void intel_modeset_init(struct drm_device *dev);
+extern void intel_modeset_gem_init(struct drm_device *dev);
extern void intel_modeset_cleanup(struct drm_device *dev);
extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
extern void i8xx_disable_fbc(struct drm_device *dev);
@@ -1312,13 +1358,34 @@
LOCK_TEST_WITH_RETURN(dev, file); \
} while (0)
+/* On SNB platform, before reading ring registers forcewake bit
+ * must be set to prevent GT core from power down and stale values being
+ * returned.
+ */
+void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
+void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
+void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
+
+/* We give fast paths for the really cool registers */
+#define NEEDS_FORCE_WAKE(dev_priv, reg) \
+ (((dev_priv)->info->gen >= 6) && \
+ ((reg) < 0x40000) && \
+ ((reg) != FORCEWAKE))
#define __i915_read(x, y) \
static inline u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
- u##x val = read##y(dev_priv->regs + reg); \
+ u##x val = 0; \
+ if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
+ gen6_gt_force_wake_get(dev_priv); \
+ val = read##y(dev_priv->regs + reg); \
+ gen6_gt_force_wake_put(dev_priv); \
+ } else { \
+ val = read##y(dev_priv->regs + reg); \
+ } \
trace_i915_reg_rw(false, reg, val, sizeof(val)); \
return val; \
}
+
__i915_read(8, b)
__i915_read(16, w)
__i915_read(32, l)
@@ -1328,6 +1395,9 @@
#define __i915_write(x, y) \
static inline void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
trace_i915_reg_rw(true, reg, val, sizeof(val)); \
+ if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
+ __gen6_gt_wait_for_fifo(dev_priv); \
+ } \
write##y(val, dev_priv->regs + reg); \
}
__i915_write(8, b)
@@ -1356,33 +1426,4 @@
#define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
-/* On SNB platform, before reading ring registers forcewake bit
- * must be set to prevent GT core from power down and stale values being
- * returned.
- */
-void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
-void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
-void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
-
-static inline u32 i915_gt_read(struct drm_i915_private *dev_priv, u32 reg)
-{
- u32 val;
-
- if (dev_priv->info->gen >= 6) {
- __gen6_gt_force_wake_get(dev_priv);
- val = I915_READ(reg);
- __gen6_gt_force_wake_put(dev_priv);
- } else
- val = I915_READ(reg);
-
- return val;
-}
-
-static inline void i915_gt_write(struct drm_i915_private *dev_priv,
- u32 reg, u32 val)
-{
- if (dev_priv->info->gen >= 6)
- __gen6_gt_wait_for_fifo(dev_priv);
- I915_WRITE(reg, val);
-}
#endif
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 7ce3f35..0b2e167 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -56,9 +56,7 @@
static void i915_gem_free_object_tail(struct drm_i915_gem_object *obj);
static int i915_gem_inactive_shrink(struct shrinker *shrinker,
- int nr_to_scan,
- gfp_t gfp_mask);
-
+ struct shrink_control *sc);
/* some bookkeeping */
static void i915_gem_info_add_obj(struct drm_i915_private *dev_priv,
@@ -2673,6 +2671,7 @@
update:
obj->tiling_changed = false;
switch (INTEL_INFO(dev)->gen) {
+ case 7:
case 6:
ret = sandybridge_write_fence_reg(obj, pipelined);
break;
@@ -2706,6 +2705,7 @@
uint32_t fence_reg = reg - dev_priv->fence_regs;
switch (INTEL_INFO(dev)->gen) {
+ case 7:
case 6:
I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + fence_reg*8, 0);
break;
@@ -2878,6 +2878,17 @@
if (obj->pages == NULL)
return;
+ /* If the GPU is snooping the contents of the CPU cache,
+ * we do not need to manually clear the CPU cache lines. However,
+ * the caches are only snooped when the render cache is
+ * flushed/invalidated. As we always have to emit invalidations
+ * and flushes when moving into and out of the RENDER domain, correct
+ * snooping behaviour occurs naturally as the result of our domain
+ * tracking.
+ */
+ if (obj->cache_level != I915_CACHE_NONE)
+ return;
+
trace_i915_gem_object_clflush(obj);
drm_clflush_pages(obj->pages, obj->base.size / PAGE_SIZE);
@@ -3569,7 +3580,7 @@
obj->base.write_domain = I915_GEM_DOMAIN_CPU;
obj->base.read_domains = I915_GEM_DOMAIN_CPU;
- obj->agp_type = AGP_USER_MEMORY;
+ obj->cache_level = I915_CACHE_NONE;
obj->base.driver_private = NULL;
obj->fence_reg = I915_FENCE_REG_NONE;
INIT_LIST_HEAD(&obj->mm_list);
@@ -3845,25 +3856,10 @@
dev_priv->num_fence_regs = 8;
/* Initialize fence registers to zero */
- switch (INTEL_INFO(dev)->gen) {
- case 6:
- for (i = 0; i < 16; i++)
- I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (i * 8), 0);
- break;
- case 5:
- case 4:
- for (i = 0; i < 16; i++)
- I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0);
- break;
- case 3:
- if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
- for (i = 0; i < 8; i++)
- I915_WRITE(FENCE_REG_945_8 + (i * 4), 0);
- case 2:
- for (i = 0; i < 8; i++)
- I915_WRITE(FENCE_REG_830_0 + (i * 4), 0);
- break;
+ for (i = 0; i < dev_priv->num_fence_regs; i++) {
+ i915_gem_clear_fence_reg(dev, &dev_priv->fence_regs[i]);
}
+
i915_gem_detect_bit_6_swizzle(dev);
init_waitqueue_head(&dev_priv->pending_flip_queue);
@@ -4094,9 +4090,7 @@
}
static int
-i915_gem_inactive_shrink(struct shrinker *shrinker,
- int nr_to_scan,
- gfp_t gfp_mask)
+i915_gem_inactive_shrink(struct shrinker *shrinker, struct shrink_control *sc)
{
struct drm_i915_private *dev_priv =
container_of(shrinker,
@@ -4104,6 +4098,7 @@
mm.inactive_shrinker);
struct drm_device *dev = dev_priv->dev;
struct drm_i915_gem_object *obj, *next;
+ int nr_to_scan = sc->nr_to_scan;
int cnt;
if (!mutex_trylock(&dev->struct_mutex))
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index b0abdc6..e46b645 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -29,6 +29,26 @@
#include "i915_trace.h"
#include "intel_drv.h"
+/* XXX kill agp_type! */
+static unsigned int cache_level_to_agp_type(struct drm_device *dev,
+ enum i915_cache_level cache_level)
+{
+ switch (cache_level) {
+ case I915_CACHE_LLC_MLC:
+ if (INTEL_INFO(dev)->gen >= 6)
+ return AGP_USER_CACHED_MEMORY_LLC_MLC;
+ /* Older chipsets do not have this extra level of CPU
+ * cacheing, so fallthrough and request the PTE simply
+ * as cached.
+ */
+ case I915_CACHE_LLC:
+ return AGP_USER_CACHED_MEMORY;
+ default:
+ case I915_CACHE_NONE:
+ return AGP_USER_MEMORY;
+ }
+}
+
void i915_gem_restore_gtt_mappings(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -39,6 +59,9 @@
(dev_priv->mm.gtt_end - dev_priv->mm.gtt_start) / PAGE_SIZE);
list_for_each_entry(obj, &dev_priv->mm.gtt_list, gtt_list) {
+ unsigned int agp_type =
+ cache_level_to_agp_type(dev, obj->cache_level);
+
i915_gem_clflush_object(obj);
if (dev_priv->mm.gtt->needs_dmar) {
@@ -46,15 +69,14 @@
intel_gtt_insert_sg_entries(obj->sg_list,
obj->num_sg,
- obj->gtt_space->start
- >> PAGE_SHIFT,
- obj->agp_type);
+ obj->gtt_space->start >> PAGE_SHIFT,
+ agp_type);
} else
intel_gtt_insert_pages(obj->gtt_space->start
>> PAGE_SHIFT,
obj->base.size >> PAGE_SHIFT,
obj->pages,
- obj->agp_type);
+ agp_type);
}
intel_gtt_chipset_flush();
@@ -64,6 +86,7 @@
{
struct drm_device *dev = obj->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
+ unsigned int agp_type = cache_level_to_agp_type(dev, obj->cache_level);
int ret;
if (dev_priv->mm.gtt->needs_dmar) {
@@ -77,12 +100,12 @@
intel_gtt_insert_sg_entries(obj->sg_list,
obj->num_sg,
obj->gtt_space->start >> PAGE_SHIFT,
- obj->agp_type);
+ agp_type);
} else
intel_gtt_insert_pages(obj->gtt_space->start >> PAGE_SHIFT,
obj->base.size >> PAGE_SHIFT,
obj->pages,
- obj->agp_type);
+ agp_type);
return 0;
}
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index 281ad3d..82d70fd 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -92,7 +92,7 @@
uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
- if (IS_GEN5(dev) || IS_GEN6(dev)) {
+ if (INTEL_INFO(dev)->gen >= 5) {
/* On Ironlake whatever DRAM config, GPU always do
* same swizzling setup.
*/
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 188b497..b79619a 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -367,22 +367,30 @@
jiffies + msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD));
}
-static void gen6_pm_irq_handler(struct drm_device *dev)
+static void gen6_pm_rps_work(struct work_struct *work)
{
- drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+ drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
+ rps_work);
u8 new_delay = dev_priv->cur_delay;
- u32 pm_iir;
+ u32 pm_iir, pm_imr;
- pm_iir = I915_READ(GEN6_PMIIR);
+ spin_lock_irq(&dev_priv->rps_lock);
+ pm_iir = dev_priv->pm_iir;
+ dev_priv->pm_iir = 0;
+ pm_imr = I915_READ(GEN6_PMIMR);
+ spin_unlock_irq(&dev_priv->rps_lock);
+
if (!pm_iir)
return;
+ mutex_lock(&dev_priv->dev->struct_mutex);
if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
if (dev_priv->cur_delay != dev_priv->max_delay)
new_delay = dev_priv->cur_delay + 1;
if (new_delay > dev_priv->max_delay)
new_delay = dev_priv->max_delay;
} else if (pm_iir & (GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT)) {
+ gen6_gt_force_wake_get(dev_priv);
if (dev_priv->cur_delay != dev_priv->min_delay)
new_delay = dev_priv->cur_delay - 1;
if (new_delay < dev_priv->min_delay) {
@@ -396,13 +404,19 @@
I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
I915_READ(GEN6_RP_INTERRUPT_LIMITS) & ~0x3f0000);
}
-
+ gen6_gt_force_wake_put(dev_priv);
}
- gen6_set_rps(dev, new_delay);
+ gen6_set_rps(dev_priv->dev, new_delay);
dev_priv->cur_delay = new_delay;
- I915_WRITE(GEN6_PMIIR, pm_iir);
+ /*
+ * rps_lock not held here because clearing is non-destructive. There is
+ * an *extremely* unlikely race with gen6_rps_enable() that is prevented
+ * by holding struct_mutex for the duration of the write.
+ */
+ I915_WRITE(GEN6_PMIMR, pm_imr & ~pm_iir);
+ mutex_unlock(&dev_priv->dev->struct_mutex);
}
static void pch_irq_handler(struct drm_device *dev)
@@ -448,8 +462,97 @@
DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
}
-static irqreturn_t ironlake_irq_handler(struct drm_device *dev)
+irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS)
{
+ struct drm_device *dev = (struct drm_device *) arg;
+ drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+ int ret = IRQ_NONE;
+ u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
+ struct drm_i915_master_private *master_priv;
+
+ atomic_inc(&dev_priv->irq_received);
+
+ /* disable master interrupt before clearing iir */
+ de_ier = I915_READ(DEIER);
+ I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
+ POSTING_READ(DEIER);
+
+ de_iir = I915_READ(DEIIR);
+ gt_iir = I915_READ(GTIIR);
+ pch_iir = I915_READ(SDEIIR);
+ pm_iir = I915_READ(GEN6_PMIIR);
+
+ if (de_iir == 0 && gt_iir == 0 && pch_iir == 0 && pm_iir == 0)
+ goto done;
+
+ ret = IRQ_HANDLED;
+
+ if (dev->primary->master) {
+ master_priv = dev->primary->master->driver_priv;
+ if (master_priv->sarea_priv)
+ master_priv->sarea_priv->last_dispatch =
+ READ_BREADCRUMB(dev_priv);
+ }
+
+ if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
+ notify_ring(dev, &dev_priv->ring[RCS]);
+ if (gt_iir & GT_GEN6_BSD_USER_INTERRUPT)
+ notify_ring(dev, &dev_priv->ring[VCS]);
+ if (gt_iir & GT_BLT_USER_INTERRUPT)
+ notify_ring(dev, &dev_priv->ring[BCS]);
+
+ if (de_iir & DE_GSE_IVB)
+ intel_opregion_gse_intr(dev);
+
+ if (de_iir & DE_PLANEA_FLIP_DONE_IVB) {
+ intel_prepare_page_flip(dev, 0);
+ intel_finish_page_flip_plane(dev, 0);
+ }
+
+ if (de_iir & DE_PLANEB_FLIP_DONE_IVB) {
+ intel_prepare_page_flip(dev, 1);
+ intel_finish_page_flip_plane(dev, 1);
+ }
+
+ if (de_iir & DE_PIPEA_VBLANK_IVB)
+ drm_handle_vblank(dev, 0);
+
+ if (de_iir & DE_PIPEB_VBLANK_IVB);
+ drm_handle_vblank(dev, 1);
+
+ /* check event from PCH */
+ if (de_iir & DE_PCH_EVENT_IVB) {
+ if (pch_iir & SDE_HOTPLUG_MASK_CPT)
+ queue_work(dev_priv->wq, &dev_priv->hotplug_work);
+ pch_irq_handler(dev);
+ }
+
+ if (pm_iir & GEN6_PM_DEFERRED_EVENTS) {
+ unsigned long flags;
+ spin_lock_irqsave(&dev_priv->rps_lock, flags);
+ WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n");
+ I915_WRITE(GEN6_PMIMR, pm_iir);
+ dev_priv->pm_iir |= pm_iir;
+ spin_unlock_irqrestore(&dev_priv->rps_lock, flags);
+ queue_work(dev_priv->wq, &dev_priv->rps_work);
+ }
+
+ /* should clear PCH hotplug event before clear CPU irq */
+ I915_WRITE(SDEIIR, pch_iir);
+ I915_WRITE(GTIIR, gt_iir);
+ I915_WRITE(DEIIR, de_iir);
+ I915_WRITE(GEN6_PMIIR, pm_iir);
+
+done:
+ I915_WRITE(DEIER, de_ier);
+ POSTING_READ(DEIER);
+
+ return ret;
+}
+
+irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS)
+{
+ struct drm_device *dev = (struct drm_device *) arg;
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
int ret = IRQ_NONE;
u32 de_iir, gt_iir, de_ier, pch_iir, pm_iir;
@@ -457,6 +560,8 @@
struct drm_i915_master_private *master_priv;
u32 bsd_usr_interrupt = GT_BSD_USER_INTERRUPT;
+ atomic_inc(&dev_priv->irq_received);
+
if (IS_GEN6(dev))
bsd_usr_interrupt = GT_GEN6_BSD_USER_INTERRUPT;
@@ -526,13 +631,30 @@
i915_handle_rps_change(dev);
}
- if (IS_GEN6(dev))
- gen6_pm_irq_handler(dev);
+ if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS) {
+ /*
+ * IIR bits should never already be set because IMR should
+ * prevent an interrupt from being shown in IIR. The warning
+ * displays a case where we've unsafely cleared
+ * dev_priv->pm_iir. Although missing an interrupt of the same
+ * type is not a problem, it displays a problem in the logic.
+ *
+ * The mask bit in IMR is cleared by rps_work.
+ */
+ unsigned long flags;
+ spin_lock_irqsave(&dev_priv->rps_lock, flags);
+ WARN(dev_priv->pm_iir & pm_iir, "Missed a PM interrupt\n");
+ I915_WRITE(GEN6_PMIMR, pm_iir);
+ dev_priv->pm_iir |= pm_iir;
+ spin_unlock_irqrestore(&dev_priv->rps_lock, flags);
+ queue_work(dev_priv->wq, &dev_priv->rps_work);
+ }
/* should clear PCH hotplug event before clear CPU irq */
I915_WRITE(SDEIIR, pch_iir);
I915_WRITE(GTIIR, gt_iir);
I915_WRITE(DEIIR, de_iir);
+ I915_WRITE(GEN6_PMIIR, pm_iir);
done:
I915_WRITE(DEIER, de_ier);
@@ -676,7 +798,7 @@
err->dirty = obj->dirty;
err->purgeable = obj->madv != I915_MADV_WILLNEED;
err->ring = obj->ring ? obj->ring->id : 0;
- err->agp_type = obj->agp_type == AGP_USER_CACHED_MEMORY;
+ err->cache_level = obj->cache_level;
if (++i == count)
break;
@@ -1103,9 +1225,6 @@
atomic_inc(&dev_priv->irq_received);
- if (HAS_PCH_SPLIT(dev))
- return ironlake_irq_handler(dev);
-
iir = I915_READ(IIR);
if (INTEL_INFO(dev)->gen >= 4)
@@ -1344,10 +1463,7 @@
return -EINVAL;
spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
- if (HAS_PCH_SPLIT(dev))
- ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
- DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
- else if (INTEL_INFO(dev)->gen >= 4)
+ if (INTEL_INFO(dev)->gen >= 4)
i915_enable_pipestat(dev_priv, pipe,
PIPE_START_VBLANK_INTERRUPT_ENABLE);
else
@@ -1362,6 +1478,38 @@
return 0;
}
+int ironlake_enable_vblank(struct drm_device *dev, int pipe)
+{
+ drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+ unsigned long irqflags;
+
+ if (!i915_pipe_enabled(dev, pipe))
+ return -EINVAL;
+
+ spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
+ ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
+ DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
+ spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+
+ return 0;
+}
+
+int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
+{
+ drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+ unsigned long irqflags;
+
+ if (!i915_pipe_enabled(dev, pipe))
+ return -EINVAL;
+
+ spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
+ ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
+ DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB);
+ spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+
+ return 0;
+}
+
/* Called from drm generic code, passed 'crtc' which
* we use as a pipe index
*/
@@ -1375,13 +1523,31 @@
I915_WRITE(INSTPM,
INSTPM_AGPBUSY_DIS << 16 | INSTPM_AGPBUSY_DIS);
- if (HAS_PCH_SPLIT(dev))
- ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
- DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
- else
- i915_disable_pipestat(dev_priv, pipe,
- PIPE_VBLANK_INTERRUPT_ENABLE |
- PIPE_START_VBLANK_INTERRUPT_ENABLE);
+ i915_disable_pipestat(dev_priv, pipe,
+ PIPE_VBLANK_INTERRUPT_ENABLE |
+ PIPE_START_VBLANK_INTERRUPT_ENABLE);
+ spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+}
+
+void ironlake_disable_vblank(struct drm_device *dev, int pipe)
+{
+ drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+ unsigned long irqflags;
+
+ spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
+ ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
+ DE_PIPEA_VBLANK: DE_PIPEB_VBLANK);
+ spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
+}
+
+void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
+{
+ drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+ unsigned long irqflags;
+
+ spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
+ ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
+ DE_PIPEA_VBLANK_IVB : DE_PIPEB_VBLANK_IVB);
spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
}
@@ -1562,10 +1728,17 @@
/* drm_dma.h hooks
*/
-static void ironlake_irq_preinstall(struct drm_device *dev)
+void ironlake_irq_preinstall(struct drm_device *dev)
{
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+ atomic_set(&dev_priv->irq_received, 0);
+
+ INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
+ INIT_WORK(&dev_priv->error_work, i915_error_work_func);
+ if (IS_GEN6(dev) || IS_IVYBRIDGE(dev))
+ INIT_WORK(&dev_priv->rps_work, gen6_pm_rps_work);
+
I915_WRITE(HWSTAM, 0xeffe);
/* XXX hotplug from PCH */
@@ -1585,7 +1758,7 @@
POSTING_READ(SDEIER);
}
-static int ironlake_irq_postinstall(struct drm_device *dev)
+int ironlake_irq_postinstall(struct drm_device *dev)
{
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
/* enable kind of interrupts always enabled */
@@ -1594,6 +1767,13 @@
u32 render_irqs;
u32 hotplug_mask;
+ DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue);
+ if (HAS_BSD(dev))
+ DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue);
+ if (HAS_BLT(dev))
+ DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue);
+
+ dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
dev_priv->irq_mask = ~display_mask;
/* should always can generate irq */
@@ -1650,6 +1830,56 @@
return 0;
}
+int ivybridge_irq_postinstall(struct drm_device *dev)
+{
+ drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+ /* enable kind of interrupts always enabled */
+ u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
+ DE_PCH_EVENT_IVB | DE_PLANEA_FLIP_DONE_IVB |
+ DE_PLANEB_FLIP_DONE_IVB;
+ u32 render_irqs;
+ u32 hotplug_mask;
+
+ DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue);
+ if (HAS_BSD(dev))
+ DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue);
+ if (HAS_BLT(dev))
+ DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue);
+
+ dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
+ dev_priv->irq_mask = ~display_mask;
+
+ /* should always can generate irq */
+ I915_WRITE(DEIIR, I915_READ(DEIIR));
+ I915_WRITE(DEIMR, dev_priv->irq_mask);
+ I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK_IVB |
+ DE_PIPEB_VBLANK_IVB);
+ POSTING_READ(DEIER);
+
+ dev_priv->gt_irq_mask = ~0;
+
+ I915_WRITE(GTIIR, I915_READ(GTIIR));
+ I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
+
+ render_irqs = GT_USER_INTERRUPT | GT_GEN6_BSD_USER_INTERRUPT |
+ GT_BLT_USER_INTERRUPT;
+ I915_WRITE(GTIER, render_irqs);
+ POSTING_READ(GTIER);
+
+ hotplug_mask = (SDE_CRT_HOTPLUG_CPT |
+ SDE_PORTB_HOTPLUG_CPT |
+ SDE_PORTC_HOTPLUG_CPT |
+ SDE_PORTD_HOTPLUG_CPT);
+ dev_priv->pch_irq_mask = ~hotplug_mask;
+
+ I915_WRITE(SDEIIR, I915_READ(SDEIIR));
+ I915_WRITE(SDEIMR, dev_priv->pch_irq_mask);
+ I915_WRITE(SDEIER, hotplug_mask);
+ POSTING_READ(SDEIER);
+
+ return 0;
+}
+
void i915_driver_irq_preinstall(struct drm_device * dev)
{
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
@@ -1660,11 +1890,6 @@
INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
INIT_WORK(&dev_priv->error_work, i915_error_work_func);
- if (HAS_PCH_SPLIT(dev)) {
- ironlake_irq_preinstall(dev);
- return;
- }
-
if (I915_HAS_HOTPLUG(dev)) {
I915_WRITE(PORT_HOTPLUG_EN, 0);
I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
@@ -1688,17 +1913,8 @@
u32 enable_mask = I915_INTERRUPT_ENABLE_FIX | I915_INTERRUPT_ENABLE_VAR;
u32 error_mask;
- DRM_INIT_WAITQUEUE(&dev_priv->ring[RCS].irq_queue);
- if (HAS_BSD(dev))
- DRM_INIT_WAITQUEUE(&dev_priv->ring[VCS].irq_queue);
- if (HAS_BLT(dev))
- DRM_INIT_WAITQUEUE(&dev_priv->ring[BCS].irq_queue);
-
dev_priv->vblank_pipe = DRM_I915_VBLANK_PIPE_A | DRM_I915_VBLANK_PIPE_B;
- if (HAS_PCH_SPLIT(dev))
- return ironlake_irq_postinstall(dev);
-
/* Unmask the interrupts that we always want on. */
dev_priv->irq_mask = ~I915_INTERRUPT_ENABLE_FIX;
@@ -1767,9 +1983,15 @@
return 0;
}
-static void ironlake_irq_uninstall(struct drm_device *dev)
+void ironlake_irq_uninstall(struct drm_device *dev)
{
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
+
+ if (!dev_priv)
+ return;
+
+ dev_priv->vblank_pipe = 0;
+
I915_WRITE(HWSTAM, 0xffffffff);
I915_WRITE(DEIMR, 0xffffffff);
@@ -1791,11 +2013,6 @@
dev_priv->vblank_pipe = 0;
- if (HAS_PCH_SPLIT(dev)) {
- ironlake_irq_uninstall(dev);
- return;
- }
-
if (I915_HAS_HOTPLUG(dev)) {
I915_WRITE(PORT_HOTPLUG_EN, 0);
I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f39ac3a..2f967af 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -291,6 +291,9 @@
#define RING_MAX_IDLE(base) ((base)+0x54)
#define RING_HWS_PGA(base) ((base)+0x80)
#define RING_HWS_PGA_GEN6(base) ((base)+0x2080)
+#define RENDER_HWS_PGA_GEN7 (0x04080)
+#define BSD_HWS_PGA_GEN7 (0x04180)
+#define BLT_HWS_PGA_GEN7 (0x04280)
#define RING_ACTHD(base) ((base)+0x74)
#define RING_NOPID(base) ((base)+0x94)
#define RING_IMR(base) ((base)+0xa8)
@@ -2778,6 +2781,19 @@
#define DE_PIPEA_VSYNC (1 << 3)
#define DE_PIPEA_FIFO_UNDERRUN (1 << 0)
+/* More Ivybridge lolz */
+#define DE_ERR_DEBUG_IVB (1<<30)
+#define DE_GSE_IVB (1<<29)
+#define DE_PCH_EVENT_IVB (1<<28)
+#define DE_DP_A_HOTPLUG_IVB (1<<27)
+#define DE_AUX_CHANNEL_A_IVB (1<<26)
+#define DE_SPRITEB_FLIP_DONE_IVB (1<<9)
+#define DE_SPRITEA_FLIP_DONE_IVB (1<<4)
+#define DE_PLANEB_FLIP_DONE_IVB (1<<8)
+#define DE_PLANEA_FLIP_DONE_IVB (1<<3)
+#define DE_PIPEB_VBLANK_IVB (1<<5)
+#define DE_PIPEA_VBLANK_IVB (1<<0)
+
#define DEISR 0x44000
#define DEIMR 0x44004
#define DEIIR 0x44008
@@ -2809,6 +2825,7 @@
#define ILK_eDP_A_DISABLE (1<<24)
#define ILK_DESKTOP (1<<23)
#define ILK_DSPCLK_GATE 0x42020
+#define IVB_VRHUNIT_CLK_GATE (1<<28)
#define ILK_DPARB_CLK_GATE (1<<5)
#define ILK_DPFD_CLK_GATE (1<<7)
@@ -3057,6 +3074,9 @@
#define TRANS_6BPC (2<<5)
#define TRANS_12BPC (3<<5)
+#define SOUTH_CHICKEN2 0xc2004
+#define DPLS_EDP_PPS_FIX_DIS (1<<0)
+
#define _FDI_RXA_CHICKEN 0xc200c
#define _FDI_RXB_CHICKEN 0xc2010
#define FDI_RX_PHASE_SYNC_POINTER_OVR (1<<1)
@@ -3104,7 +3124,15 @@
#define FDI_TX_ENHANCE_FRAME_ENABLE (1<<18)
/* Ironlake: hardwired to 1 */
#define FDI_TX_PLL_ENABLE (1<<14)
+
+/* Ivybridge has different bits for lolz */
+#define FDI_LINK_TRAIN_PATTERN_1_IVB (0<<8)
+#define FDI_LINK_TRAIN_PATTERN_2_IVB (1<<8)
+#define FDI_LINK_TRAIN_PATTERN_IDLE_IVB (2<<8)
+#define FDI_LINK_TRAIN_NONE_IVB (3<<8)
+
/* both Tx and Rx */
+#define FDI_LINK_TRAIN_AUTO (1<<10)
#define FDI_SCRAMBLING_ENABLE (0<<7)
#define FDI_SCRAMBLING_DISABLE (1<<7)
@@ -3114,6 +3142,8 @@
#define FDI_RX_CTL(pipe) _PIPE(pipe, _FDI_RXA_CTL, _FDI_RXB_CTL)
#define FDI_RX_ENABLE (1<<31)
/* train, dp width same as FDI_TX */
+#define FDI_FS_ERRC_ENABLE (1<<27)
+#define FDI_FE_ERRC_ENABLE (1<<26)
#define FDI_DP_PORT_WIDTH_X8 (7<<19)
#define FDI_8BPC (0<<16)
#define FDI_10BPC (1<<16)
@@ -3386,7 +3416,7 @@
#define GEN6_PMINTRMSK 0xA168
#define GEN6_PMISR 0x44020
-#define GEN6_PMIMR 0x44024
+#define GEN6_PMIMR 0x44024 /* rps_lock */
#define GEN6_PMIIR 0x44028
#define GEN6_PMIER 0x4402C
#define GEN6_PM_MBOX_EVENT (1<<25)
@@ -3396,6 +3426,9 @@
#define GEN6_PM_RP_DOWN_THRESHOLD (1<<4)
#define GEN6_PM_RP_UP_EI_EXPIRED (1<<2)
#define GEN6_PM_RP_DOWN_EI_EXPIRED (1<<1)
+#define GEN6_PM_DEFERRED_EVENTS (GEN6_PM_RP_UP_THRESHOLD | \
+ GEN6_PM_RP_DOWN_THRESHOLD | \
+ GEN6_PM_RP_DOWN_TIMEOUT)
#define GEN6_PCODE_MAILBOX 0x138124
#define GEN6_PCODE_READY (1<<31)
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index da47415..60a94d2 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -863,8 +863,7 @@
I915_WRITE(IMR, dev_priv->saveIMR);
}
- /* Clock gating state */
- intel_enable_clock_gating(dev);
+ intel_init_clock_gating(dev);
if (IS_IRONLAKE_M(dev)) {
ironlake_enable_drps(dev);
diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
index fb5b4d4..927442a 100644
--- a/drivers/gpu/drm/i915/intel_bios.c
+++ b/drivers/gpu/drm/i915/intel_bios.c
@@ -214,9 +214,9 @@
i915_lvds_downclock) {
dev_priv->lvds_downclock_avail = 1;
dev_priv->lvds_downclock = temp_downclock;
- DRM_DEBUG_KMS("LVDS downclock is found in VBT. ",
- "Normal Clock %dKHz, downclock %dKHz\n",
- temp_downclock, panel_fixed_mode->clock);
+ DRM_DEBUG_KMS("LVDS downclock is found in VBT. "
+ "Normal Clock %dKHz, downclock %dKHz\n",
+ temp_downclock, panel_fixed_mode->clock);
}
return;
}
diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/intel_crt.c
index d03fc05..e93f93c 100644
--- a/drivers/gpu/drm/i915/intel_crt.c
+++ b/drivers/gpu/drm/i915/intel_crt.c
@@ -305,13 +305,11 @@
}
static enum drm_connector_status
-intel_crt_load_detect(struct drm_crtc *crtc, struct intel_crt *crt)
+intel_crt_load_detect(struct intel_crt *crt)
{
- struct drm_encoder *encoder = &crt->base.base;
- struct drm_device *dev = encoder->dev;
+ struct drm_device *dev = crt->base.base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- uint32_t pipe = intel_crtc->pipe;
+ uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe;
uint32_t save_bclrpat;
uint32_t save_vtotal;
uint32_t vtotal, vactive;
@@ -432,7 +430,6 @@
struct drm_device *dev = connector->dev;
struct intel_crt *crt = intel_attached_crt(connector);
struct drm_crtc *crtc;
- int dpms_mode;
enum drm_connector_status status;
if (I915_HAS_HOTPLUG(dev)) {
@@ -454,17 +451,18 @@
/* for pre-945g platforms use load detect */
crtc = crt->base.base.crtc;
if (crtc && crtc->enabled) {
- status = intel_crt_load_detect(crtc, crt);
+ status = intel_crt_load_detect(crt);
} else {
- crtc = intel_get_load_detect_pipe(&crt->base, connector,
- NULL, &dpms_mode);
- if (crtc) {
+ struct intel_load_detect_pipe tmp;
+
+ if (intel_get_load_detect_pipe(&crt->base, connector, NULL,
+ &tmp)) {
if (intel_crt_detect_ddc(connector))
status = connector_status_connected;
else
- status = intel_crt_load_detect(crtc, crt);
- intel_release_load_detect_pipe(&crt->base,
- connector, dpms_mode);
+ status = intel_crt_load_detect(crt);
+ intel_release_load_detect_pipe(&crt->base, connector,
+ &tmp);
} else
status = connector_status_unknown;
}
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 2166ee0..f553ddfd 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -76,255 +76,6 @@
int, int, intel_clock_t *);
};
-#define I8XX_DOT_MIN 25000
-#define I8XX_DOT_MAX 350000
-#define I8XX_VCO_MIN 930000
-#define I8XX_VCO_MAX 1400000
-#define I8XX_N_MIN 3
-#define I8XX_N_MAX 16
-#define I8XX_M_MIN 96
-#define I8XX_M_MAX 140
-#define I8XX_M1_MIN 18
-#define I8XX_M1_MAX 26
-#define I8XX_M2_MIN 6
-#define I8XX_M2_MAX 16
-#define I8XX_P_MIN 4
-#define I8XX_P_MAX 128
-#define I8XX_P1_MIN 2
-#define I8XX_P1_MAX 33
-#define I8XX_P1_LVDS_MIN 1
-#define I8XX_P1_LVDS_MAX 6
-#define I8XX_P2_SLOW 4
-#define I8XX_P2_FAST 2
-#define I8XX_P2_LVDS_SLOW 14
-#define I8XX_P2_LVDS_FAST 7
-#define I8XX_P2_SLOW_LIMIT 165000
-
-#define I9XX_DOT_MIN 20000
-#define I9XX_DOT_MAX 400000
-#define I9XX_VCO_MIN 1400000
-#define I9XX_VCO_MAX 2800000
-#define PINEVIEW_VCO_MIN 1700000
-#define PINEVIEW_VCO_MAX 3500000
-#define I9XX_N_MIN 1
-#define I9XX_N_MAX 6
-/* Pineview's Ncounter is a ring counter */
-#define PINEVIEW_N_MIN 3
-#define PINEVIEW_N_MAX 6
-#define I9XX_M_MIN 70
-#define I9XX_M_MAX 120
-#define PINEVIEW_M_MIN 2
-#define PINEVIEW_M_MAX 256
-#define I9XX_M1_MIN 10
-#define I9XX_M1_MAX 22
-#define I9XX_M2_MIN 5
-#define I9XX_M2_MAX 9
-/* Pineview M1 is reserved, and must be 0 */
-#define PINEVIEW_M1_MIN 0
-#define PINEVIEW_M1_MAX 0
-#define PINEVIEW_M2_MIN 0
-#define PINEVIEW_M2_MAX 254
-#define I9XX_P_SDVO_DAC_MIN 5
-#define I9XX_P_SDVO_DAC_MAX 80
-#define I9XX_P_LVDS_MIN 7
-#define I9XX_P_LVDS_MAX 98
-#define PINEVIEW_P_LVDS_MIN 7
-#define PINEVIEW_P_LVDS_MAX 112
-#define I9XX_P1_MIN 1
-#define I9XX_P1_MAX 8
-#define I9XX_P2_SDVO_DAC_SLOW 10
-#define I9XX_P2_SDVO_DAC_FAST 5
-#define I9XX_P2_SDVO_DAC_SLOW_LIMIT 200000
-#define I9XX_P2_LVDS_SLOW 14
-#define I9XX_P2_LVDS_FAST 7
-#define I9XX_P2_LVDS_SLOW_LIMIT 112000
-
-/*The parameter is for SDVO on G4x platform*/
-#define G4X_DOT_SDVO_MIN 25000
-#define G4X_DOT_SDVO_MAX 270000
-#define G4X_VCO_MIN 1750000
-#define G4X_VCO_MAX 3500000
-#define G4X_N_SDVO_MIN 1
-#define G4X_N_SDVO_MAX 4
-#define G4X_M_SDVO_MIN 104
-#define G4X_M_SDVO_MAX 138
-#define G4X_M1_SDVO_MIN 17
-#define G4X_M1_SDVO_MAX 23
-#define G4X_M2_SDVO_MIN 5
-#define G4X_M2_SDVO_MAX 11
-#define G4X_P_SDVO_MIN 10
-#define G4X_P_SDVO_MAX 30
-#define G4X_P1_SDVO_MIN 1
-#define G4X_P1_SDVO_MAX 3
-#define G4X_P2_SDVO_SLOW 10
-#define G4X_P2_SDVO_FAST 10
-#define G4X_P2_SDVO_LIMIT 270000
-
-/*The parameter is for HDMI_DAC on G4x platform*/
-#define G4X_DOT_HDMI_DAC_MIN 22000
-#define G4X_DOT_HDMI_DAC_MAX 400000
-#define G4X_N_HDMI_DAC_MIN 1
-#define G4X_N_HDMI_DAC_MAX 4
-#define G4X_M_HDMI_DAC_MIN 104
-#define G4X_M_HDMI_DAC_MAX 138
-#define G4X_M1_HDMI_DAC_MIN 16
-#define G4X_M1_HDMI_DAC_MAX 23
-#define G4X_M2_HDMI_DAC_MIN 5
-#define G4X_M2_HDMI_DAC_MAX 11
-#define G4X_P_HDMI_DAC_MIN 5
-#define G4X_P_HDMI_DAC_MAX 80
-#define G4X_P1_HDMI_DAC_MIN 1
-#define G4X_P1_HDMI_DAC_MAX 8
-#define G4X_P2_HDMI_DAC_SLOW 10
-#define G4X_P2_HDMI_DAC_FAST 5
-#define G4X_P2_HDMI_DAC_LIMIT 165000
-
-/*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
-#define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN 20000
-#define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX 115000
-#define G4X_N_SINGLE_CHANNEL_LVDS_MIN 1
-#define G4X_N_SINGLE_CHANNEL_LVDS_MAX 3
-#define G4X_M_SINGLE_CHANNEL_LVDS_MIN 104
-#define G4X_M_SINGLE_CHANNEL_LVDS_MAX 138
-#define G4X_M1_SINGLE_CHANNEL_LVDS_MIN 17
-#define G4X_M1_SINGLE_CHANNEL_LVDS_MAX 23
-#define G4X_M2_SINGLE_CHANNEL_LVDS_MIN 5
-#define G4X_M2_SINGLE_CHANNEL_LVDS_MAX 11
-#define G4X_P_SINGLE_CHANNEL_LVDS_MIN 28
-#define G4X_P_SINGLE_CHANNEL_LVDS_MAX 112
-#define G4X_P1_SINGLE_CHANNEL_LVDS_MIN 2
-#define G4X_P1_SINGLE_CHANNEL_LVDS_MAX 8
-#define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW 14
-#define G4X_P2_SINGLE_CHANNEL_LVDS_FAST 14
-#define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT 0
-
-/*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
-#define G4X_DOT_DUAL_CHANNEL_LVDS_MIN 80000
-#define G4X_DOT_DUAL_CHANNEL_LVDS_MAX 224000
-#define G4X_N_DUAL_CHANNEL_LVDS_MIN 1
-#define G4X_N_DUAL_CHANNEL_LVDS_MAX 3
-#define G4X_M_DUAL_CHANNEL_LVDS_MIN 104
-#define G4X_M_DUAL_CHANNEL_LVDS_MAX 138
-#define G4X_M1_DUAL_CHANNEL_LVDS_MIN 17
-#define G4X_M1_DUAL_CHANNEL_LVDS_MAX 23
-#define G4X_M2_DUAL_CHANNEL_LVDS_MIN 5
-#define G4X_M2_DUAL_CHANNEL_LVDS_MAX 11
-#define G4X_P_DUAL_CHANNEL_LVDS_MIN 14
-#define G4X_P_DUAL_CHANNEL_LVDS_MAX 42
-#define G4X_P1_DUAL_CHANNEL_LVDS_MIN 2
-#define G4X_P1_DUAL_CHANNEL_LVDS_MAX 6
-#define G4X_P2_DUAL_CHANNEL_LVDS_SLOW 7
-#define G4X_P2_DUAL_CHANNEL_LVDS_FAST 7
-#define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT 0
-
-/*The parameter is for DISPLAY PORT on G4x platform*/
-#define G4X_DOT_DISPLAY_PORT_MIN 161670
-#define G4X_DOT_DISPLAY_PORT_MAX 227000
-#define G4X_N_DISPLAY_PORT_MIN 1
-#define G4X_N_DISPLAY_PORT_MAX 2
-#define G4X_M_DISPLAY_PORT_MIN 97
-#define G4X_M_DISPLAY_PORT_MAX 108
-#define G4X_M1_DISPLAY_PORT_MIN 0x10
-#define G4X_M1_DISPLAY_PORT_MAX 0x12
-#define G4X_M2_DISPLAY_PORT_MIN 0x05
-#define G4X_M2_DISPLAY_PORT_MAX 0x06
-#define G4X_P_DISPLAY_PORT_MIN 10
-#define G4X_P_DISPLAY_PORT_MAX 20
-#define G4X_P1_DISPLAY_PORT_MIN 1
-#define G4X_P1_DISPLAY_PORT_MAX 2
-#define G4X_P2_DISPLAY_PORT_SLOW 10
-#define G4X_P2_DISPLAY_PORT_FAST 10
-#define G4X_P2_DISPLAY_PORT_LIMIT 0
-
-/* Ironlake / Sandybridge */
-/* as we calculate clock using (register_value + 2) for
- N/M1/M2, so here the range value for them is (actual_value-2).
- */
-#define IRONLAKE_DOT_MIN 25000
-#define IRONLAKE_DOT_MAX 350000
-#define IRONLAKE_VCO_MIN 1760000
-#define IRONLAKE_VCO_MAX 3510000
-#define IRONLAKE_M1_MIN 12
-#define IRONLAKE_M1_MAX 22
-#define IRONLAKE_M2_MIN 5
-#define IRONLAKE_M2_MAX 9
-#define IRONLAKE_P2_DOT_LIMIT 225000 /* 225Mhz */
-
-/* We have parameter ranges for different type of outputs. */
-
-/* DAC & HDMI Refclk 120Mhz */
-#define IRONLAKE_DAC_N_MIN 1
-#define IRONLAKE_DAC_N_MAX 5
-#define IRONLAKE_DAC_M_MIN 79
-#define IRONLAKE_DAC_M_MAX 127
-#define IRONLAKE_DAC_P_MIN 5
-#define IRONLAKE_DAC_P_MAX 80
-#define IRONLAKE_DAC_P1_MIN 1
-#define IRONLAKE_DAC_P1_MAX 8
-#define IRONLAKE_DAC_P2_SLOW 10
-#define IRONLAKE_DAC_P2_FAST 5
-
-/* LVDS single-channel 120Mhz refclk */
-#define IRONLAKE_LVDS_S_N_MIN 1
-#define IRONLAKE_LVDS_S_N_MAX 3
-#define IRONLAKE_LVDS_S_M_MIN 79
-#define IRONLAKE_LVDS_S_M_MAX 118
-#define IRONLAKE_LVDS_S_P_MIN 28
-#define IRONLAKE_LVDS_S_P_MAX 112
-#define IRONLAKE_LVDS_S_P1_MIN 2
-#define IRONLAKE_LVDS_S_P1_MAX 8
-#define IRONLAKE_LVDS_S_P2_SLOW 14
-#define IRONLAKE_LVDS_S_P2_FAST 14
-
-/* LVDS dual-channel 120Mhz refclk */
-#define IRONLAKE_LVDS_D_N_MIN 1
-#define IRONLAKE_LVDS_D_N_MAX 3
-#define IRONLAKE_LVDS_D_M_MIN 79
-#define IRONLAKE_LVDS_D_M_MAX 127
-#define IRONLAKE_LVDS_D_P_MIN 14
-#define IRONLAKE_LVDS_D_P_MAX 56
-#define IRONLAKE_LVDS_D_P1_MIN 2
-#define IRONLAKE_LVDS_D_P1_MAX 8
-#define IRONLAKE_LVDS_D_P2_SLOW 7
-#define IRONLAKE_LVDS_D_P2_FAST 7
-
-/* LVDS single-channel 100Mhz refclk */
-#define IRONLAKE_LVDS_S_SSC_N_MIN 1
-#define IRONLAKE_LVDS_S_SSC_N_MAX 2
-#define IRONLAKE_LVDS_S_SSC_M_MIN 79
-#define IRONLAKE_LVDS_S_SSC_M_MAX 126
-#define IRONLAKE_LVDS_S_SSC_P_MIN 28
-#define IRONLAKE_LVDS_S_SSC_P_MAX 112
-#define IRONLAKE_LVDS_S_SSC_P1_MIN 2
-#define IRONLAKE_LVDS_S_SSC_P1_MAX 8
-#define IRONLAKE_LVDS_S_SSC_P2_SLOW 14
-#define IRONLAKE_LVDS_S_SSC_P2_FAST 14
-
-/* LVDS dual-channel 100Mhz refclk */
-#define IRONLAKE_LVDS_D_SSC_N_MIN 1
-#define IRONLAKE_LVDS_D_SSC_N_MAX 3
-#define IRONLAKE_LVDS_D_SSC_M_MIN 79
-#define IRONLAKE_LVDS_D_SSC_M_MAX 126
-#define IRONLAKE_LVDS_D_SSC_P_MIN 14
-#define IRONLAKE_LVDS_D_SSC_P_MAX 42
-#define IRONLAKE_LVDS_D_SSC_P1_MIN 2
-#define IRONLAKE_LVDS_D_SSC_P1_MAX 6
-#define IRONLAKE_LVDS_D_SSC_P2_SLOW 7
-#define IRONLAKE_LVDS_D_SSC_P2_FAST 7
-
-/* DisplayPort */
-#define IRONLAKE_DP_N_MIN 1
-#define IRONLAKE_DP_N_MAX 2
-#define IRONLAKE_DP_M_MIN 81
-#define IRONLAKE_DP_M_MAX 90
-#define IRONLAKE_DP_P_MIN 10
-#define IRONLAKE_DP_P_MAX 20
-#define IRONLAKE_DP_P2_FAST 10
-#define IRONLAKE_DP_P2_SLOW 10
-#define IRONLAKE_DP_P2_LIMIT 0
-#define IRONLAKE_DP_P1_MIN 1
-#define IRONLAKE_DP_P1_MAX 2
-
/* FDI */
#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
@@ -353,292 +104,253 @@
}
static const intel_limit_t intel_limits_i8xx_dvo = {
- .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
- .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
- .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
- .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
- .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
- .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
- .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
- .p1 = { .min = I8XX_P1_MIN, .max = I8XX_P1_MAX },
- .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
- .p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
+ .dot = { .min = 25000, .max = 350000 },
+ .vco = { .min = 930000, .max = 1400000 },
+ .n = { .min = 3, .max = 16 },
+ .m = { .min = 96, .max = 140 },
+ .m1 = { .min = 18, .max = 26 },
+ .m2 = { .min = 6, .max = 16 },
+ .p = { .min = 4, .max = 128 },
+ .p1 = { .min = 2, .max = 33 },
+ .p2 = { .dot_limit = 165000,
+ .p2_slow = 4, .p2_fast = 2 },
.find_pll = intel_find_best_PLL,
};
static const intel_limit_t intel_limits_i8xx_lvds = {
- .dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
- .vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
- .n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
- .m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
- .m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
- .m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
- .p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
- .p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
- .p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
- .p2_slow = I8XX_P2_LVDS_SLOW, .p2_fast = I8XX_P2_LVDS_FAST },
+ .dot = { .min = 25000, .max = 350000 },
+ .vco = { .min = 930000, .max = 1400000 },
+ .n = { .min = 3, .max = 16 },
+ .m = { .min = 96, .max = 140 },
+ .m1 = { .min = 18, .max = 26 },
+ .m2 = { .min = 6, .max = 16 },
+ .p = { .min = 4, .max = 128 },
+ .p1 = { .min = 1, .max = 6 },
+ .p2 = { .dot_limit = 165000,
+ .p2_slow = 14, .p2_fast = 7 },
.find_pll = intel_find_best_PLL,
};
-
+
static const intel_limit_t intel_limits_i9xx_sdvo = {
- .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
- .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
- .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
- .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
- .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
- .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
- .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
- .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
- .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
- .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
+ .dot = { .min = 20000, .max = 400000 },
+ .vco = { .min = 1400000, .max = 2800000 },
+ .n = { .min = 1, .max = 6 },
+ .m = { .min = 70, .max = 120 },
+ .m1 = { .min = 10, .max = 22 },
+ .m2 = { .min = 5, .max = 9 },
+ .p = { .min = 5, .max = 80 },
+ .p1 = { .min = 1, .max = 8 },
+ .p2 = { .dot_limit = 200000,
+ .p2_slow = 10, .p2_fast = 5 },
.find_pll = intel_find_best_PLL,
};
static const intel_limit_t intel_limits_i9xx_lvds = {
- .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
- .vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
- .n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
- .m = { .min = I9XX_M_MIN, .max = I9XX_M_MAX },
- .m1 = { .min = I9XX_M1_MIN, .max = I9XX_M1_MAX },
- .m2 = { .min = I9XX_M2_MIN, .max = I9XX_M2_MAX },
- .p = { .min = I9XX_P_LVDS_MIN, .max = I9XX_P_LVDS_MAX },
- .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
- /* The single-channel range is 25-112Mhz, and dual-channel
- * is 80-224Mhz. Prefer single channel as much as possible.
- */
- .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
- .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_FAST },
+ .dot = { .min = 20000, .max = 400000 },
+ .vco = { .min = 1400000, .max = 2800000 },
+ .n = { .min = 1, .max = 6 },
+ .m = { .min = 70, .max = 120 },
+ .m1 = { .min = 10, .max = 22 },
+ .m2 = { .min = 5, .max = 9 },
+ .p = { .min = 7, .max = 98 },
+ .p1 = { .min = 1, .max = 8 },
+ .p2 = { .dot_limit = 112000,
+ .p2_slow = 14, .p2_fast = 7 },
.find_pll = intel_find_best_PLL,
};
- /* below parameter and function is for G4X Chipset Family*/
+
static const intel_limit_t intel_limits_g4x_sdvo = {
- .dot = { .min = G4X_DOT_SDVO_MIN, .max = G4X_DOT_SDVO_MAX },
- .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
- .n = { .min = G4X_N_SDVO_MIN, .max = G4X_N_SDVO_MAX },
- .m = { .min = G4X_M_SDVO_MIN, .max = G4X_M_SDVO_MAX },
- .m1 = { .min = G4X_M1_SDVO_MIN, .max = G4X_M1_SDVO_MAX },
- .m2 = { .min = G4X_M2_SDVO_MIN, .max = G4X_M2_SDVO_MAX },
- .p = { .min = G4X_P_SDVO_MIN, .max = G4X_P_SDVO_MAX },
- .p1 = { .min = G4X_P1_SDVO_MIN, .max = G4X_P1_SDVO_MAX},
- .p2 = { .dot_limit = G4X_P2_SDVO_LIMIT,
- .p2_slow = G4X_P2_SDVO_SLOW,
- .p2_fast = G4X_P2_SDVO_FAST
+ .dot = { .min = 25000, .max = 270000 },
+ .vco = { .min = 1750000, .max = 3500000},
+ .n = { .min = 1, .max = 4 },
+ .m = { .min = 104, .max = 138 },
+ .m1 = { .min = 17, .max = 23 },
+ .m2 = { .min = 5, .max = 11 },
+ .p = { .min = 10, .max = 30 },
+ .p1 = { .min = 1, .max = 3},
+ .p2 = { .dot_limit = 270000,
+ .p2_slow = 10,
+ .p2_fast = 10
},
.find_pll = intel_g4x_find_best_PLL,
};
static const intel_limit_t intel_limits_g4x_hdmi = {
- .dot = { .min = G4X_DOT_HDMI_DAC_MIN, .max = G4X_DOT_HDMI_DAC_MAX },
- .vco = { .min = G4X_VCO_MIN, .max = G4X_VCO_MAX},
- .n = { .min = G4X_N_HDMI_DAC_MIN, .max = G4X_N_HDMI_DAC_MAX },
- .m = { .min = G4X_M_HDMI_DAC_MIN, .max = G4X_M_HDMI_DAC_MAX },
- .m1 = { .min = G4X_M1_HDMI_DAC_MIN, .max = G4X_M1_HDMI_DAC_MAX },
- .m2 = { .min = G4X_M2_HDMI_DAC_MIN, .max = G4X_M2_HDMI_DAC_MAX },
- .p = { .min = G4X_P_HDMI_DAC_MIN, .max = G4X_P_HDMI_DAC_MAX },
- .p1 = { .min = G4X_P1_HDMI_DAC_MIN, .max = G4X_P1_HDMI_DAC_MAX},
- .p2 = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
- .p2_slow = G4X_P2_HDMI_DAC_SLOW,
- .p2_fast = G4X_P2_HDMI_DAC_FAST
- },
+ .dot = { .min = 22000, .max = 400000 },
+ .vco = { .min = 1750000, .max = 3500000},
+ .n = { .min = 1, .max = 4 },
+ .m = { .min = 104, .max = 138 },
+ .m1 = { .min = 16, .max = 23 },
+ .m2 = { .min = 5, .max = 11 },
+ .p = { .min = 5, .max = 80 },
+ .p1 = { .min = 1, .max = 8},
+ .p2 = { .dot_limit = 165000,
+ .p2_slow = 10, .p2_fast = 5 },
.find_pll = intel_g4x_find_best_PLL,
};
static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
- .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
- .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
- .vco = { .min = G4X_VCO_MIN,
- .max = G4X_VCO_MAX },
- .n = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
- .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
- .m = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
- .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
- .m1 = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
- .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
- .m2 = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
- .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
- .p = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
- .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
- .p1 = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
- .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
- .p2 = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
- .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
- .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
+ .dot = { .min = 20000, .max = 115000 },
+ .vco = { .min = 1750000, .max = 3500000 },
+ .n = { .min = 1, .max = 3 },
+ .m = { .min = 104, .max = 138 },
+ .m1 = { .min = 17, .max = 23 },
+ .m2 = { .min = 5, .max = 11 },
+ .p = { .min = 28, .max = 112 },
+ .p1 = { .min = 2, .max = 8 },
+ .p2 = { .dot_limit = 0,
+ .p2_slow = 14, .p2_fast = 14
},
.find_pll = intel_g4x_find_best_PLL,
};
static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
- .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
- .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
- .vco = { .min = G4X_VCO_MIN,
- .max = G4X_VCO_MAX },
- .n = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
- .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
- .m = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
- .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
- .m1 = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
- .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
- .m2 = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
- .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
- .p = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
- .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
- .p1 = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
- .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
- .p2 = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
- .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
- .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
+ .dot = { .min = 80000, .max = 224000 },
+ .vco = { .min = 1750000, .max = 3500000 },
+ .n = { .min = 1, .max = 3 },
+ .m = { .min = 104, .max = 138 },
+ .m1 = { .min = 17, .max = 23 },
+ .m2 = { .min = 5, .max = 11 },
+ .p = { .min = 14, .max = 42 },
+ .p1 = { .min = 2, .max = 6 },
+ .p2 = { .dot_limit = 0,
+ .p2_slow = 7, .p2_fast = 7
},
.find_pll = intel_g4x_find_best_PLL,
};
static const intel_limit_t intel_limits_g4x_display_port = {
- .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
- .max = G4X_DOT_DISPLAY_PORT_MAX },
- .vco = { .min = G4X_VCO_MIN,
- .max = G4X_VCO_MAX},
- .n = { .min = G4X_N_DISPLAY_PORT_MIN,
- .max = G4X_N_DISPLAY_PORT_MAX },
- .m = { .min = G4X_M_DISPLAY_PORT_MIN,
- .max = G4X_M_DISPLAY_PORT_MAX },
- .m1 = { .min = G4X_M1_DISPLAY_PORT_MIN,
- .max = G4X_M1_DISPLAY_PORT_MAX },
- .m2 = { .min = G4X_M2_DISPLAY_PORT_MIN,
- .max = G4X_M2_DISPLAY_PORT_MAX },
- .p = { .min = G4X_P_DISPLAY_PORT_MIN,
- .max = G4X_P_DISPLAY_PORT_MAX },
- .p1 = { .min = G4X_P1_DISPLAY_PORT_MIN,
- .max = G4X_P1_DISPLAY_PORT_MAX},
- .p2 = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
- .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
- .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
+ .dot = { .min = 161670, .max = 227000 },
+ .vco = { .min = 1750000, .max = 3500000},
+ .n = { .min = 1, .max = 2 },
+ .m = { .min = 97, .max = 108 },
+ .m1 = { .min = 0x10, .max = 0x12 },
+ .m2 = { .min = 0x05, .max = 0x06 },
+ .p = { .min = 10, .max = 20 },
+ .p1 = { .min = 1, .max = 2},
+ .p2 = { .dot_limit = 0,
+ .p2_slow = 10, .p2_fast = 10 },
.find_pll = intel_find_pll_g4x_dp,
};
static const intel_limit_t intel_limits_pineview_sdvo = {
- .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX},
- .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
- .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
- .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
- .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
- .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
- .p = { .min = I9XX_P_SDVO_DAC_MIN, .max = I9XX_P_SDVO_DAC_MAX },
- .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
- .p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
- .p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
+ .dot = { .min = 20000, .max = 400000},
+ .vco = { .min = 1700000, .max = 3500000 },
+ /* Pineview's Ncounter is a ring counter */
+ .n = { .min = 3, .max = 6 },
+ .m = { .min = 2, .max = 256 },
+ /* Pineview only has one combined m divider, which we treat as m2. */
+ .m1 = { .min = 0, .max = 0 },
+ .m2 = { .min = 0, .max = 254 },
+ .p = { .min = 5, .max = 80 },
+ .p1 = { .min = 1, .max = 8 },
+ .p2 = { .dot_limit = 200000,
+ .p2_slow = 10, .p2_fast = 5 },
.find_pll = intel_find_best_PLL,
};
static const intel_limit_t intel_limits_pineview_lvds = {
- .dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
- .vco = { .min = PINEVIEW_VCO_MIN, .max = PINEVIEW_VCO_MAX },
- .n = { .min = PINEVIEW_N_MIN, .max = PINEVIEW_N_MAX },
- .m = { .min = PINEVIEW_M_MIN, .max = PINEVIEW_M_MAX },
- .m1 = { .min = PINEVIEW_M1_MIN, .max = PINEVIEW_M1_MAX },
- .m2 = { .min = PINEVIEW_M2_MIN, .max = PINEVIEW_M2_MAX },
- .p = { .min = PINEVIEW_P_LVDS_MIN, .max = PINEVIEW_P_LVDS_MAX },
- .p1 = { .min = I9XX_P1_MIN, .max = I9XX_P1_MAX },
- /* Pineview only supports single-channel mode. */
- .p2 = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
- .p2_slow = I9XX_P2_LVDS_SLOW, .p2_fast = I9XX_P2_LVDS_SLOW },
+ .dot = { .min = 20000, .max = 400000 },
+ .vco = { .min = 1700000, .max = 3500000 },
+ .n = { .min = 3, .max = 6 },
+ .m = { .min = 2, .max = 256 },
+ .m1 = { .min = 0, .max = 0 },
+ .m2 = { .min = 0, .max = 254 },
+ .p = { .min = 7, .max = 112 },
+ .p1 = { .min = 1, .max = 8 },
+ .p2 = { .dot_limit = 112000,
+ .p2_slow = 14, .p2_fast = 14 },
.find_pll = intel_find_best_PLL,
};
+/* Ironlake / Sandybridge
+ *
+ * We calculate clock using (register_value + 2) for N/M1/M2, so here
+ * the range value for them is (actual_value - 2).
+ */
static const intel_limit_t intel_limits_ironlake_dac = {
- .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
- .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
- .n = { .min = IRONLAKE_DAC_N_MIN, .max = IRONLAKE_DAC_N_MAX },
- .m = { .min = IRONLAKE_DAC_M_MIN, .max = IRONLAKE_DAC_M_MAX },
- .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
- .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
- .p = { .min = IRONLAKE_DAC_P_MIN, .max = IRONLAKE_DAC_P_MAX },
- .p1 = { .min = IRONLAKE_DAC_P1_MIN, .max = IRONLAKE_DAC_P1_MAX },
- .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
- .p2_slow = IRONLAKE_DAC_P2_SLOW,
- .p2_fast = IRONLAKE_DAC_P2_FAST },
+ .dot = { .min = 25000, .max = 350000 },
+ .vco = { .min = 1760000, .max = 3510000 },
+ .n = { .min = 1, .max = 5 },
+ .m = { .min = 79, .max = 127 },
+ .m1 = { .min = 12, .max = 22 },
+ .m2 = { .min = 5, .max = 9 },
+ .p = { .min = 5, .max = 80 },
+ .p1 = { .min = 1, .max = 8 },
+ .p2 = { .dot_limit = 225000,
+ .p2_slow = 10, .p2_fast = 5 },
.find_pll = intel_g4x_find_best_PLL,
};
static const intel_limit_t intel_limits_ironlake_single_lvds = {
- .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
- .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
- .n = { .min = IRONLAKE_LVDS_S_N_MIN, .max = IRONLAKE_LVDS_S_N_MAX },
- .m = { .min = IRONLAKE_LVDS_S_M_MIN, .max = IRONLAKE_LVDS_S_M_MAX },
- .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
- .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
- .p = { .min = IRONLAKE_LVDS_S_P_MIN, .max = IRONLAKE_LVDS_S_P_MAX },
- .p1 = { .min = IRONLAKE_LVDS_S_P1_MIN, .max = IRONLAKE_LVDS_S_P1_MAX },
- .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
- .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
- .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
+ .dot = { .min = 25000, .max = 350000 },
+ .vco = { .min = 1760000, .max = 3510000 },
+ .n = { .min = 1, .max = 3 },
+ .m = { .min = 79, .max = 118 },
+ .m1 = { .min = 12, .max = 22 },
+ .m2 = { .min = 5, .max = 9 },
+ .p = { .min = 28, .max = 112 },
+ .p1 = { .min = 2, .max = 8 },
+ .p2 = { .dot_limit = 225000,
+ .p2_slow = 14, .p2_fast = 14 },
.find_pll = intel_g4x_find_best_PLL,
};
static const intel_limit_t intel_limits_ironlake_dual_lvds = {
- .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
- .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
- .n = { .min = IRONLAKE_LVDS_D_N_MIN, .max = IRONLAKE_LVDS_D_N_MAX },
- .m = { .min = IRONLAKE_LVDS_D_M_MIN, .max = IRONLAKE_LVDS_D_M_MAX },
- .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
- .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
- .p = { .min = IRONLAKE_LVDS_D_P_MIN, .max = IRONLAKE_LVDS_D_P_MAX },
- .p1 = { .min = IRONLAKE_LVDS_D_P1_MIN, .max = IRONLAKE_LVDS_D_P1_MAX },
- .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
- .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
- .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
+ .dot = { .min = 25000, .max = 350000 },
+ .vco = { .min = 1760000, .max = 3510000 },
+ .n = { .min = 1, .max = 3 },
+ .m = { .min = 79, .max = 127 },
+ .m1 = { .min = 12, .max = 22 },
+ .m2 = { .min = 5, .max = 9 },
+ .p = { .min = 14, .max = 56 },
+ .p1 = { .min = 2, .max = 8 },
+ .p2 = { .dot_limit = 225000,
+ .p2_slow = 7, .p2_fast = 7 },
.find_pll = intel_g4x_find_best_PLL,
};
+/* LVDS 100mhz refclk limits. */
static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
- .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
- .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
- .n = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
- .m = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
- .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
- .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
- .p = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
- .p1 = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
- .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
- .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
- .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
+ .dot = { .min = 25000, .max = 350000 },
+ .vco = { .min = 1760000, .max = 3510000 },
+ .n = { .min = 1, .max = 2 },
+ .m = { .min = 79, .max = 126 },
+ .m1 = { .min = 12, .max = 22 },
+ .m2 = { .min = 5, .max = 9 },
+ .p = { .min = 28, .max = 112 },
+ .p1 = { .min = 2,.max = 8 },
+ .p2 = { .dot_limit = 225000,
+ .p2_slow = 14, .p2_fast = 14 },
.find_pll = intel_g4x_find_best_PLL,
};
static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
- .dot = { .min = IRONLAKE_DOT_MIN, .max = IRONLAKE_DOT_MAX },
- .vco = { .min = IRONLAKE_VCO_MIN, .max = IRONLAKE_VCO_MAX },
- .n = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
- .m = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
- .m1 = { .min = IRONLAKE_M1_MIN, .max = IRONLAKE_M1_MAX },
- .m2 = { .min = IRONLAKE_M2_MIN, .max = IRONLAKE_M2_MAX },
- .p = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
- .p1 = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
- .p2 = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
- .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
- .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
+ .dot = { .min = 25000, .max = 350000 },
+ .vco = { .min = 1760000, .max = 3510000 },
+ .n = { .min = 1, .max = 3 },
+ .m = { .min = 79, .max = 126 },
+ .m1 = { .min = 12, .max = 22 },
+ .m2 = { .min = 5, .max = 9 },
+ .p = { .min = 14, .max = 42 },
+ .p1 = { .min = 2,.max = 6 },
+ .p2 = { .dot_limit = 225000,
+ .p2_slow = 7, .p2_fast = 7 },
.find_pll = intel_g4x_find_best_PLL,
};
static const intel_limit_t intel_limits_ironlake_display_port = {
- .dot = { .min = IRONLAKE_DOT_MIN,
- .max = IRONLAKE_DOT_MAX },
- .vco = { .min = IRONLAKE_VCO_MIN,
- .max = IRONLAKE_VCO_MAX},
- .n = { .min = IRONLAKE_DP_N_MIN,
- .max = IRONLAKE_DP_N_MAX },
- .m = { .min = IRONLAKE_DP_M_MIN,
- .max = IRONLAKE_DP_M_MAX },
- .m1 = { .min = IRONLAKE_M1_MIN,
- .max = IRONLAKE_M1_MAX },
- .m2 = { .min = IRONLAKE_M2_MIN,
- .max = IRONLAKE_M2_MAX },
- .p = { .min = IRONLAKE_DP_P_MIN,
- .max = IRONLAKE_DP_P_MAX },
- .p1 = { .min = IRONLAKE_DP_P1_MIN,
- .max = IRONLAKE_DP_P1_MAX},
- .p2 = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
- .p2_slow = IRONLAKE_DP_P2_SLOW,
- .p2_fast = IRONLAKE_DP_P2_FAST },
+ .dot = { .min = 25000, .max = 350000 },
+ .vco = { .min = 1760000, .max = 3510000},
+ .n = { .min = 1, .max = 2 },
+ .m = { .min = 81, .max = 90 },
+ .m1 = { .min = 12, .max = 22 },
+ .m2 = { .min = 5, .max = 9 },
+ .p = { .min = 10, .max = 20 },
+ .p1 = { .min = 1, .max = 2},
+ .p2 = { .dot_limit = 0,
+ .p2_slow = 10, .p2_fast = 10 },
.find_pll = intel_find_pll_ironlake_dp,
};
@@ -1828,7 +1540,7 @@
u32 blt_ecoskpd;
/* Make sure blitter notifies FBC of writes */
- __gen6_gt_force_wake_get(dev_priv);
+ gen6_gt_force_wake_get(dev_priv);
blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
GEN6_BLITTER_LOCK_SHIFT;
@@ -1839,7 +1551,7 @@
GEN6_BLITTER_LOCK_SHIFT);
I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
POSTING_READ(GEN6_BLITTER_ECOSKPD);
- __gen6_gt_force_wake_put(dev_priv);
+ gen6_gt_force_wake_put(dev_priv);
}
static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
@@ -2019,6 +1731,11 @@
intel_fb = to_intel_framebuffer(fb);
obj = intel_fb->obj;
+ if (!i915_enable_fbc) {
+ DRM_DEBUG_KMS("fbc disabled per module param (default off)\n");
+ dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
+ goto out_disable;
+ }
if (intel_fb->obj->base.size > dev_priv->cfb_size) {
DRM_DEBUG_KMS("framebuffer too large, disabling "
"compression\n");
@@ -2339,8 +2056,13 @@
/* enable normal train */
reg = FDI_TX_CTL(pipe);
temp = I915_READ(reg);
- temp &= ~FDI_LINK_TRAIN_NONE;
- temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
+ if (IS_IVYBRIDGE(dev)) {
+ temp &= ~FDI_LINK_TRAIN_NONE_IVB;
+ temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
+ } else {
+ temp &= ~FDI_LINK_TRAIN_NONE;
+ temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
+ }
I915_WRITE(reg, temp);
reg = FDI_RX_CTL(pipe);
@@ -2357,6 +2079,11 @@
/* wait one idle pattern time */
POSTING_READ(reg);
udelay(1000);
+
+ /* IVB wants error correction enabled */
+ if (IS_IVYBRIDGE(dev))
+ I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
+ FDI_FE_ERRC_ENABLE);
}
/* The FDI link training functions for ILK/Ibexpeak. */
@@ -2584,7 +2311,116 @@
DRM_DEBUG_KMS("FDI train done.\n");
}
-static void ironlake_fdi_enable(struct drm_crtc *crtc)
+/* Manual link training for Ivy Bridge A0 parts */
+static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
+{
+ struct drm_device *dev = crtc->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ int pipe = intel_crtc->pipe;
+ u32 reg, temp, i;
+
+ /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
+ for train result */
+ reg = FDI_RX_IMR(pipe);
+ temp = I915_READ(reg);
+ temp &= ~FDI_RX_SYMBOL_LOCK;
+ temp &= ~FDI_RX_BIT_LOCK;
+ I915_WRITE(reg, temp);
+
+ POSTING_READ(reg);
+ udelay(150);
+
+ /* enable CPU FDI TX and PCH FDI RX */
+ reg = FDI_TX_CTL(pipe);
+ temp = I915_READ(reg);
+ temp &= ~(7 << 19);
+ temp |= (intel_crtc->fdi_lanes - 1) << 19;
+ temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
+ temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
+ temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
+ temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
+ I915_WRITE(reg, temp | FDI_TX_ENABLE);
+
+ reg = FDI_RX_CTL(pipe);
+ temp = I915_READ(reg);
+ temp &= ~FDI_LINK_TRAIN_AUTO;
+ temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
+ temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
+ I915_WRITE(reg, temp | FDI_RX_ENABLE);
+
+ POSTING_READ(reg);
+ udelay(150);
+
+ for (i = 0; i < 4; i++ ) {
+ reg = FDI_TX_CTL(pipe);
+ temp = I915_READ(reg);
+ temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
+ temp |= snb_b_fdi_train_param[i];
+ I915_WRITE(reg, temp);
+
+ POSTING_READ(reg);
+ udelay(500);
+
+ reg = FDI_RX_IIR(pipe);
+ temp = I915_READ(reg);
+ DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
+
+ if (temp & FDI_RX_BIT_LOCK ||
+ (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
+ I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
+ DRM_DEBUG_KMS("FDI train 1 done.\n");
+ break;
+ }
+ }
+ if (i == 4)
+ DRM_ERROR("FDI train 1 fail!\n");
+
+ /* Train 2 */
+ reg = FDI_TX_CTL(pipe);
+ temp = I915_READ(reg);
+ temp &= ~FDI_LINK_TRAIN_NONE_IVB;
+ temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
+ temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
+ temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
+ I915_WRITE(reg, temp);
+
+ reg = FDI_RX_CTL(pipe);
+ temp = I915_READ(reg);
+ temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
+ temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
+ I915_WRITE(reg, temp);
+
+ POSTING_READ(reg);
+ udelay(150);
+
+ for (i = 0; i < 4; i++ ) {
+ reg = FDI_TX_CTL(pipe);
+ temp = I915_READ(reg);
+ temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
+ temp |= snb_b_fdi_train_param[i];
+ I915_WRITE(reg, temp);
+
+ POSTING_READ(reg);
+ udelay(500);
+
+ reg = FDI_RX_IIR(pipe);
+ temp = I915_READ(reg);
+ DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
+
+ if (temp & FDI_RX_SYMBOL_LOCK) {
+ I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
+ DRM_DEBUG_KMS("FDI train 2 done.\n");
+ break;
+ }
+ }
+ if (i == 4)
+ DRM_ERROR("FDI train 2 fail!\n");
+
+ DRM_DEBUG_KMS("FDI train done.\n");
+}
+
+static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
{
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
@@ -2757,10 +2593,7 @@
u32 reg, temp;
/* For PCH output, training FDI link */
- if (IS_GEN6(dev))
- gen6_fdi_link_train(crtc);
- else
- ironlake_fdi_link_train(crtc);
+ dev_priv->display.fdi_link_train(crtc);
intel_enable_pch_pll(dev_priv, pipe);
@@ -2850,7 +2683,7 @@
is_pch_port = intel_crtc_driving_pch(crtc);
if (is_pch_port)
- ironlake_fdi_enable(crtc);
+ ironlake_fdi_pll_enable(crtc);
else
ironlake_fdi_disable(crtc);
@@ -2873,7 +2706,11 @@
ironlake_pch_enable(crtc);
intel_crtc_load_lut(crtc);
+
+ mutex_lock(&dev->struct_mutex);
intel_update_fbc(dev);
+ mutex_unlock(&dev->struct_mutex);
+
intel_crtc_update_cursor(crtc, true);
}
@@ -2969,8 +2806,11 @@
intel_crtc->active = false;
intel_update_watermarks(dev);
+
+ mutex_lock(&dev->struct_mutex);
intel_update_fbc(dev);
intel_clear_scanline_wait(dev);
+ mutex_unlock(&dev->struct_mutex);
}
static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
@@ -3497,11 +3337,11 @@
1000;
entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
- DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
+ DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
wm_size = fifo_size - (entries_required + wm->guard_size);
- DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
+ DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
/* Don't promote wm_size to unsigned... */
if (wm_size > (long)wm->max_wm)
@@ -3823,13 +3663,13 @@
display_wm, cursor_wm);
if (display_wm > display->max_wm) {
- DRM_DEBUG_KMS("display watermark is too large(%d), disabling\n",
+ DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
display_wm, display->max_wm);
return false;
}
if (cursor_wm > cursor->max_wm) {
- DRM_DEBUG_KMS("cursor watermark is too large(%d), disabling\n",
+ DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
cursor_wm, cursor->max_wm);
return false;
}
@@ -4516,34 +4356,28 @@
return dev_priv->lvds_use_ssc && i915_panel_use_ssc;
}
-static int intel_crtc_mode_set(struct drm_crtc *crtc,
- struct drm_display_mode *mode,
- struct drm_display_mode *adjusted_mode,
- int x, int y,
- struct drm_framebuffer *old_fb)
+static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
+ struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode,
+ int x, int y,
+ struct drm_framebuffer *old_fb)
{
struct drm_device *dev = crtc->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
int pipe = intel_crtc->pipe;
int plane = intel_crtc->plane;
- u32 fp_reg, dpll_reg;
int refclk, num_connectors = 0;
intel_clock_t clock, reduced_clock;
u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
- struct intel_encoder *has_edp_encoder = NULL;
struct drm_mode_config *mode_config = &dev->mode_config;
struct intel_encoder *encoder;
const intel_limit_t *limit;
int ret;
- struct fdi_m_n m_n = {0};
- u32 reg, temp;
+ u32 temp;
u32 lvds_sync = 0;
- int target_clock;
-
- drm_vblank_pre_modeset(dev, pipe);
list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
if (encoder->base.crtc != crtc)
@@ -4571,9 +4405,6 @@
case INTEL_OUTPUT_DISPLAYPORT:
is_dp = true;
break;
- case INTEL_OUTPUT_EDP:
- has_edp_encoder = encoder;
- break;
}
num_connectors++;
@@ -4585,9 +4416,6 @@
refclk / 1000);
} else if (!IS_GEN2(dev)) {
refclk = 96000;
- if (HAS_PCH_SPLIT(dev) &&
- (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)))
- refclk = 120000; /* 120Mhz refclk */
} else {
refclk = 48000;
}
@@ -4601,7 +4429,397 @@
ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
if (!ok) {
DRM_ERROR("Couldn't find PLL settings for mode!\n");
- drm_vblank_post_modeset(dev, pipe);
+ return -EINVAL;
+ }
+
+ /* Ensure that the cursor is valid for the new mode before changing... */
+ intel_crtc_update_cursor(crtc, true);
+
+ if (is_lvds && dev_priv->lvds_downclock_avail) {
+ has_reduced_clock = limit->find_pll(limit, crtc,
+ dev_priv->lvds_downclock,
+ refclk,
+ &reduced_clock);
+ if (has_reduced_clock && (clock.p != reduced_clock.p)) {
+ /*
+ * If the different P is found, it means that we can't
+ * switch the display clock by using the FP0/FP1.
+ * In such case we will disable the LVDS downclock
+ * feature.
+ */
+ DRM_DEBUG_KMS("Different P is found for "
+ "LVDS clock/downclock\n");
+ has_reduced_clock = 0;
+ }
+ }
+ /* SDVO TV has fixed PLL values depend on its clock range,
+ this mirrors vbios setting. */
+ if (is_sdvo && is_tv) {
+ if (adjusted_mode->clock >= 100000
+ && adjusted_mode->clock < 140500) {
+ clock.p1 = 2;
+ clock.p2 = 10;
+ clock.n = 3;
+ clock.m1 = 16;
+ clock.m2 = 8;
+ } else if (adjusted_mode->clock >= 140500
+ && adjusted_mode->clock <= 200000) {
+ clock.p1 = 1;
+ clock.p2 = 10;
+ clock.n = 6;
+ clock.m1 = 12;
+ clock.m2 = 8;
+ }
+ }
+
+ if (IS_PINEVIEW(dev)) {
+ fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
+ if (has_reduced_clock)
+ fp2 = (1 << reduced_clock.n) << 16 |
+ reduced_clock.m1 << 8 | reduced_clock.m2;
+ } else {
+ fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
+ if (has_reduced_clock)
+ fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
+ reduced_clock.m2;
+ }
+
+ dpll = DPLL_VGA_MODE_DIS;
+
+ if (!IS_GEN2(dev)) {
+ if (is_lvds)
+ dpll |= DPLLB_MODE_LVDS;
+ else
+ dpll |= DPLLB_MODE_DAC_SERIAL;
+ if (is_sdvo) {
+ int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
+ if (pixel_multiplier > 1) {
+ if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
+ dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
+ }
+ dpll |= DPLL_DVO_HIGH_SPEED;
+ }
+ if (is_dp)
+ dpll |= DPLL_DVO_HIGH_SPEED;
+
+ /* compute bitmask from p1 value */
+ if (IS_PINEVIEW(dev))
+ dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
+ else {
+ dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
+ if (IS_G4X(dev) && has_reduced_clock)
+ dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
+ }
+ switch (clock.p2) {
+ case 5:
+ dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
+ break;
+ case 7:
+ dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
+ break;
+ case 10:
+ dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
+ break;
+ case 14:
+ dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
+ break;
+ }
+ if (INTEL_INFO(dev)->gen >= 4)
+ dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
+ } else {
+ if (is_lvds) {
+ dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
+ } else {
+ if (clock.p1 == 2)
+ dpll |= PLL_P1_DIVIDE_BY_TWO;
+ else
+ dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
+ if (clock.p2 == 4)
+ dpll |= PLL_P2_DIVIDE_BY_4;
+ }
+ }
+
+ if (is_sdvo && is_tv)
+ dpll |= PLL_REF_INPUT_TVCLKINBC;
+ else if (is_tv)
+ /* XXX: just matching BIOS for now */
+ /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
+ dpll |= 3;
+ else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
+ dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
+ else
+ dpll |= PLL_REF_INPUT_DREFCLK;
+
+ /* setup pipeconf */
+ pipeconf = I915_READ(PIPECONF(pipe));
+
+ /* Set up the display plane register */
+ dspcntr = DISPPLANE_GAMMA_ENABLE;
+
+ /* Ironlake's plane is forced to pipe, bit 24 is to
+ enable color space conversion */
+ if (pipe == 0)
+ dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
+ else
+ dspcntr |= DISPPLANE_SEL_PIPE_B;
+
+ if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
+ /* Enable pixel doubling when the dot clock is > 90% of the (display)
+ * core speed.
+ *
+ * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
+ * pipe == 0 check?
+ */
+ if (mode->clock >
+ dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
+ pipeconf |= PIPECONF_DOUBLE_WIDE;
+ else
+ pipeconf &= ~PIPECONF_DOUBLE_WIDE;
+ }
+
+ dpll |= DPLL_VCO_ENABLE;
+
+ DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
+ drm_mode_debug_printmodeline(mode);
+
+ I915_WRITE(FP0(pipe), fp);
+ I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
+
+ POSTING_READ(DPLL(pipe));
+ udelay(150);
+
+ /* The LVDS pin pair needs to be on before the DPLLs are enabled.
+ * This is an exception to the general rule that mode_set doesn't turn
+ * things on.
+ */
+ if (is_lvds) {
+ temp = I915_READ(LVDS);
+ temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
+ if (pipe == 1) {
+ temp |= LVDS_PIPEB_SELECT;
+ } else {
+ temp &= ~LVDS_PIPEB_SELECT;
+ }
+ /* set the corresponsding LVDS_BORDER bit */
+ temp |= dev_priv->lvds_border_bits;
+ /* Set the B0-B3 data pairs corresponding to whether we're going to
+ * set the DPLLs for dual-channel mode or not.
+ */
+ if (clock.p2 == 7)
+ temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
+ else
+ temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
+
+ /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
+ * appropriately here, but we need to look more thoroughly into how
+ * panels behave in the two modes.
+ */
+ /* set the dithering flag on LVDS as needed */
+ if (INTEL_INFO(dev)->gen >= 4) {
+ if (dev_priv->lvds_dither)
+ temp |= LVDS_ENABLE_DITHER;
+ else
+ temp &= ~LVDS_ENABLE_DITHER;
+ }
+ if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
+ lvds_sync |= LVDS_HSYNC_POLARITY;
+ if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
+ lvds_sync |= LVDS_VSYNC_POLARITY;
+ if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
+ != lvds_sync) {
+ char flags[2] = "-+";
+ DRM_INFO("Changing LVDS panel from "
+ "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
+ flags[!(temp & LVDS_HSYNC_POLARITY)],
+ flags[!(temp & LVDS_VSYNC_POLARITY)],
+ flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
+ flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
+ temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
+ temp |= lvds_sync;
+ }
+ I915_WRITE(LVDS, temp);
+ }
+
+ if (is_dp) {
+ intel_dp_set_m_n(crtc, mode, adjusted_mode);
+ }
+
+ I915_WRITE(DPLL(pipe), dpll);
+
+ /* Wait for the clocks to stabilize. */
+ POSTING_READ(DPLL(pipe));
+ udelay(150);
+
+ if (INTEL_INFO(dev)->gen >= 4) {
+ temp = 0;
+ if (is_sdvo) {
+ temp = intel_mode_get_pixel_multiplier(adjusted_mode);
+ if (temp > 1)
+ temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
+ else
+ temp = 0;
+ }
+ I915_WRITE(DPLL_MD(pipe), temp);
+ } else {
+ /* The pixel multiplier can only be updated once the
+ * DPLL is enabled and the clocks are stable.
+ *
+ * So write it again.
+ */
+ I915_WRITE(DPLL(pipe), dpll);
+ }
+
+ intel_crtc->lowfreq_avail = false;
+ if (is_lvds && has_reduced_clock && i915_powersave) {
+ I915_WRITE(FP1(pipe), fp2);
+ intel_crtc->lowfreq_avail = true;
+ if (HAS_PIPE_CXSR(dev)) {
+ DRM_DEBUG_KMS("enabling CxSR downclocking\n");
+ pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
+ }
+ } else {
+ I915_WRITE(FP1(pipe), fp);
+ if (HAS_PIPE_CXSR(dev)) {
+ DRM_DEBUG_KMS("disabling CxSR downclocking\n");
+ pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
+ }
+ }
+
+ if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
+ pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
+ /* the chip adds 2 halflines automatically */
+ adjusted_mode->crtc_vdisplay -= 1;
+ adjusted_mode->crtc_vtotal -= 1;
+ adjusted_mode->crtc_vblank_start -= 1;
+ adjusted_mode->crtc_vblank_end -= 1;
+ adjusted_mode->crtc_vsync_end -= 1;
+ adjusted_mode->crtc_vsync_start -= 1;
+ } else
+ pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
+
+ I915_WRITE(HTOTAL(pipe),
+ (adjusted_mode->crtc_hdisplay - 1) |
+ ((adjusted_mode->crtc_htotal - 1) << 16));
+ I915_WRITE(HBLANK(pipe),
+ (adjusted_mode->crtc_hblank_start - 1) |
+ ((adjusted_mode->crtc_hblank_end - 1) << 16));
+ I915_WRITE(HSYNC(pipe),
+ (adjusted_mode->crtc_hsync_start - 1) |
+ ((adjusted_mode->crtc_hsync_end - 1) << 16));
+
+ I915_WRITE(VTOTAL(pipe),
+ (adjusted_mode->crtc_vdisplay - 1) |
+ ((adjusted_mode->crtc_vtotal - 1) << 16));
+ I915_WRITE(VBLANK(pipe),
+ (adjusted_mode->crtc_vblank_start - 1) |
+ ((adjusted_mode->crtc_vblank_end - 1) << 16));
+ I915_WRITE(VSYNC(pipe),
+ (adjusted_mode->crtc_vsync_start - 1) |
+ ((adjusted_mode->crtc_vsync_end - 1) << 16));
+
+ /* pipesrc and dspsize control the size that is scaled from,
+ * which should always be the user's requested size.
+ */
+ I915_WRITE(DSPSIZE(plane),
+ ((mode->vdisplay - 1) << 16) |
+ (mode->hdisplay - 1));
+ I915_WRITE(DSPPOS(plane), 0);
+ I915_WRITE(PIPESRC(pipe),
+ ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
+
+ I915_WRITE(PIPECONF(pipe), pipeconf);
+ POSTING_READ(PIPECONF(pipe));
+ intel_enable_pipe(dev_priv, pipe, false);
+
+ intel_wait_for_vblank(dev, pipe);
+
+ I915_WRITE(DSPCNTR(plane), dspcntr);
+ POSTING_READ(DSPCNTR(plane));
+
+ ret = intel_pipe_set_base(crtc, x, y, old_fb);
+
+ intel_update_watermarks(dev);
+
+ return ret;
+}
+
+static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
+ struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode,
+ int x, int y,
+ struct drm_framebuffer *old_fb)
+{
+ struct drm_device *dev = crtc->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ int pipe = intel_crtc->pipe;
+ int plane = intel_crtc->plane;
+ int refclk, num_connectors = 0;
+ intel_clock_t clock, reduced_clock;
+ u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
+ bool ok, has_reduced_clock = false, is_sdvo = false;
+ bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
+ struct intel_encoder *has_edp_encoder = NULL;
+ struct drm_mode_config *mode_config = &dev->mode_config;
+ struct intel_encoder *encoder;
+ const intel_limit_t *limit;
+ int ret;
+ struct fdi_m_n m_n = {0};
+ u32 temp;
+ u32 lvds_sync = 0;
+ int target_clock, pixel_multiplier, lane, link_bw, bpp, factor;
+
+ list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
+ if (encoder->base.crtc != crtc)
+ continue;
+
+ switch (encoder->type) {
+ case INTEL_OUTPUT_LVDS:
+ is_lvds = true;
+ break;
+ case INTEL_OUTPUT_SDVO:
+ case INTEL_OUTPUT_HDMI:
+ is_sdvo = true;
+ if (encoder->needs_tv_clock)
+ is_tv = true;
+ break;
+ case INTEL_OUTPUT_TVOUT:
+ is_tv = true;
+ break;
+ case INTEL_OUTPUT_ANALOG:
+ is_crt = true;
+ break;
+ case INTEL_OUTPUT_DISPLAYPORT:
+ is_dp = true;
+ break;
+ case INTEL_OUTPUT_EDP:
+ has_edp_encoder = encoder;
+ break;
+ }
+
+ num_connectors++;
+ }
+
+ if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
+ refclk = dev_priv->lvds_ssc_freq * 1000;
+ DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
+ refclk / 1000);
+ } else {
+ refclk = 96000;
+ if (!has_edp_encoder ||
+ intel_encoder_is_pch_edp(&has_edp_encoder->base))
+ refclk = 120000; /* 120Mhz refclk */
+ }
+
+ /*
+ * Returns a set of divisors for the desired target clock with the given
+ * refclk, or FALSE. The returned values represent the clock equation:
+ * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
+ */
+ limit = intel_limit(crtc, refclk);
+ ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
+ if (!ok) {
+ DRM_ERROR("Couldn't find PLL settings for mode!\n");
return -EINVAL;
}
@@ -4646,230 +4864,191 @@
}
/* FDI link */
- if (HAS_PCH_SPLIT(dev)) {
- int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
- int lane = 0, link_bw, bpp;
- /* CPU eDP doesn't require FDI link, so just set DP M/N
- according to current link config */
- if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
+ pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
+ lane = 0;
+ /* CPU eDP doesn't require FDI link, so just set DP M/N
+ according to current link config */
+ if (has_edp_encoder &&
+ !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
+ target_clock = mode->clock;
+ intel_edp_link_config(has_edp_encoder,
+ &lane, &link_bw);
+ } else {
+ /* [e]DP over FDI requires target mode clock
+ instead of link clock */
+ if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
target_clock = mode->clock;
- intel_edp_link_config(has_edp_encoder,
- &lane, &link_bw);
- } else {
- /* [e]DP over FDI requires target mode clock
- instead of link clock */
- if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
- target_clock = mode->clock;
- else
- target_clock = adjusted_mode->clock;
+ else
+ target_clock = adjusted_mode->clock;
- /* FDI is a binary signal running at ~2.7GHz, encoding
- * each output octet as 10 bits. The actual frequency
- * is stored as a divider into a 100MHz clock, and the
- * mode pixel clock is stored in units of 1KHz.
- * Hence the bw of each lane in terms of the mode signal
- * is:
- */
- link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
- }
-
- /* determine panel color depth */
- temp = I915_READ(PIPECONF(pipe));
- temp &= ~PIPE_BPC_MASK;
- if (is_lvds) {
- /* the BPC will be 6 if it is 18-bit LVDS panel */
- if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
- temp |= PIPE_8BPC;
- else
- temp |= PIPE_6BPC;
- } else if (has_edp_encoder) {
- switch (dev_priv->edp.bpp/3) {
- case 8:
- temp |= PIPE_8BPC;
- break;
- case 10:
- temp |= PIPE_10BPC;
- break;
- case 6:
- temp |= PIPE_6BPC;
- break;
- case 12:
- temp |= PIPE_12BPC;
- break;
- }
- } else
- temp |= PIPE_8BPC;
- I915_WRITE(PIPECONF(pipe), temp);
-
- switch (temp & PIPE_BPC_MASK) {
- case PIPE_8BPC:
- bpp = 24;
- break;
- case PIPE_10BPC:
- bpp = 30;
- break;
- case PIPE_6BPC:
- bpp = 18;
- break;
- case PIPE_12BPC:
- bpp = 36;
- break;
- default:
- DRM_ERROR("unknown pipe bpc value\n");
- bpp = 24;
- }
-
- if (!lane) {
- /*
- * Account for spread spectrum to avoid
- * oversubscribing the link. Max center spread
- * is 2.5%; use 5% for safety's sake.
- */
- u32 bps = target_clock * bpp * 21 / 20;
- lane = bps / (link_bw * 8) + 1;
- }
-
- intel_crtc->fdi_lanes = lane;
-
- if (pixel_multiplier > 1)
- link_bw *= pixel_multiplier;
- ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
+ /* FDI is a binary signal running at ~2.7GHz, encoding
+ * each output octet as 10 bits. The actual frequency
+ * is stored as a divider into a 100MHz clock, and the
+ * mode pixel clock is stored in units of 1KHz.
+ * Hence the bw of each lane in terms of the mode signal
+ * is:
+ */
+ link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
}
+ /* determine panel color depth */
+ temp = I915_READ(PIPECONF(pipe));
+ temp &= ~PIPE_BPC_MASK;
+ if (is_lvds) {
+ /* the BPC will be 6 if it is 18-bit LVDS panel */
+ if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
+ temp |= PIPE_8BPC;
+ else
+ temp |= PIPE_6BPC;
+ } else if (has_edp_encoder) {
+ switch (dev_priv->edp.bpp/3) {
+ case 8:
+ temp |= PIPE_8BPC;
+ break;
+ case 10:
+ temp |= PIPE_10BPC;
+ break;
+ case 6:
+ temp |= PIPE_6BPC;
+ break;
+ case 12:
+ temp |= PIPE_12BPC;
+ break;
+ }
+ } else
+ temp |= PIPE_8BPC;
+ I915_WRITE(PIPECONF(pipe), temp);
+
+ switch (temp & PIPE_BPC_MASK) {
+ case PIPE_8BPC:
+ bpp = 24;
+ break;
+ case PIPE_10BPC:
+ bpp = 30;
+ break;
+ case PIPE_6BPC:
+ bpp = 18;
+ break;
+ case PIPE_12BPC:
+ bpp = 36;
+ break;
+ default:
+ DRM_ERROR("unknown pipe bpc value\n");
+ bpp = 24;
+ }
+
+ if (!lane) {
+ /*
+ * Account for spread spectrum to avoid
+ * oversubscribing the link. Max center spread
+ * is 2.5%; use 5% for safety's sake.
+ */
+ u32 bps = target_clock * bpp * 21 / 20;
+ lane = bps / (link_bw * 8) + 1;
+ }
+
+ intel_crtc->fdi_lanes = lane;
+
+ if (pixel_multiplier > 1)
+ link_bw *= pixel_multiplier;
+ ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
+
/* Ironlake: try to setup display ref clock before DPLL
* enabling. This is only under driver's control after
* PCH B stepping, previous chipset stepping should be
* ignoring this setting.
*/
- if (HAS_PCH_SPLIT(dev)) {
- temp = I915_READ(PCH_DREF_CONTROL);
- /* Always enable nonspread source */
- temp &= ~DREF_NONSPREAD_SOURCE_MASK;
- temp |= DREF_NONSPREAD_SOURCE_ENABLE;
- temp &= ~DREF_SSC_SOURCE_MASK;
- temp |= DREF_SSC_SOURCE_ENABLE;
- I915_WRITE(PCH_DREF_CONTROL, temp);
+ temp = I915_READ(PCH_DREF_CONTROL);
+ /* Always enable nonspread source */
+ temp &= ~DREF_NONSPREAD_SOURCE_MASK;
+ temp |= DREF_NONSPREAD_SOURCE_ENABLE;
+ temp &= ~DREF_SSC_SOURCE_MASK;
+ temp |= DREF_SSC_SOURCE_ENABLE;
+ I915_WRITE(PCH_DREF_CONTROL, temp);
- POSTING_READ(PCH_DREF_CONTROL);
- udelay(200);
+ POSTING_READ(PCH_DREF_CONTROL);
+ udelay(200);
- if (has_edp_encoder) {
- if (intel_panel_use_ssc(dev_priv)) {
- temp |= DREF_SSC1_ENABLE;
- I915_WRITE(PCH_DREF_CONTROL, temp);
-
- POSTING_READ(PCH_DREF_CONTROL);
- udelay(200);
- }
- temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
-
- /* Enable CPU source on CPU attached eDP */
- if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
- if (intel_panel_use_ssc(dev_priv))
- temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
- else
- temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
- } else {
- /* Enable SSC on PCH eDP if needed */
- if (intel_panel_use_ssc(dev_priv)) {
- DRM_ERROR("enabling SSC on PCH\n");
- temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
- }
- }
+ if (has_edp_encoder) {
+ if (intel_panel_use_ssc(dev_priv)) {
+ temp |= DREF_SSC1_ENABLE;
I915_WRITE(PCH_DREF_CONTROL, temp);
+
POSTING_READ(PCH_DREF_CONTROL);
udelay(200);
}
+ temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
+
+ /* Enable CPU source on CPU attached eDP */
+ if (!intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
+ if (intel_panel_use_ssc(dev_priv))
+ temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
+ else
+ temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
+ } else {
+ /* Enable SSC on PCH eDP if needed */
+ if (intel_panel_use_ssc(dev_priv)) {
+ DRM_ERROR("enabling SSC on PCH\n");
+ temp |= DREF_SUPERSPREAD_SOURCE_ENABLE;
+ }
+ }
+ I915_WRITE(PCH_DREF_CONTROL, temp);
+ POSTING_READ(PCH_DREF_CONTROL);
+ udelay(200);
}
- if (IS_PINEVIEW(dev)) {
- fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
- if (has_reduced_clock)
- fp2 = (1 << reduced_clock.n) << 16 |
- reduced_clock.m1 << 8 | reduced_clock.m2;
- } else {
- fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
- if (has_reduced_clock)
- fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
- reduced_clock.m2;
- }
+ fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
+ if (has_reduced_clock)
+ fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
+ reduced_clock.m2;
/* Enable autotuning of the PLL clock (if permissible) */
- if (HAS_PCH_SPLIT(dev)) {
- int factor = 21;
+ factor = 21;
+ if (is_lvds) {
+ if ((intel_panel_use_ssc(dev_priv) &&
+ dev_priv->lvds_ssc_freq == 100) ||
+ (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
+ factor = 25;
+ } else if (is_sdvo && is_tv)
+ factor = 20;
- if (is_lvds) {
- if ((intel_panel_use_ssc(dev_priv) &&
- dev_priv->lvds_ssc_freq == 100) ||
- (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
- factor = 25;
- } else if (is_sdvo && is_tv)
- factor = 20;
-
- if (clock.m1 < factor * clock.n)
- fp |= FP_CB_TUNE;
- }
+ if (clock.m1 < factor * clock.n)
+ fp |= FP_CB_TUNE;
dpll = 0;
- if (!HAS_PCH_SPLIT(dev))
- dpll = DPLL_VGA_MODE_DIS;
- if (!IS_GEN2(dev)) {
- if (is_lvds)
- dpll |= DPLLB_MODE_LVDS;
- else
- dpll |= DPLLB_MODE_DAC_SERIAL;
- if (is_sdvo) {
- int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
- if (pixel_multiplier > 1) {
- if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
- dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
- else if (HAS_PCH_SPLIT(dev))
- dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
- }
- dpll |= DPLL_DVO_HIGH_SPEED;
+ if (is_lvds)
+ dpll |= DPLLB_MODE_LVDS;
+ else
+ dpll |= DPLLB_MODE_DAC_SERIAL;
+ if (is_sdvo) {
+ int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
+ if (pixel_multiplier > 1) {
+ dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
}
- if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
- dpll |= DPLL_DVO_HIGH_SPEED;
+ dpll |= DPLL_DVO_HIGH_SPEED;
+ }
+ if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
+ dpll |= DPLL_DVO_HIGH_SPEED;
- /* compute bitmask from p1 value */
- if (IS_PINEVIEW(dev))
- dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
- else {
- dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
- /* also FPA1 */
- if (HAS_PCH_SPLIT(dev))
- dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
- if (IS_G4X(dev) && has_reduced_clock)
- dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
- }
- switch (clock.p2) {
- case 5:
- dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
- break;
- case 7:
- dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
- break;
- case 10:
- dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
- break;
- case 14:
- dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
- break;
- }
- if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
- dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
- } else {
- if (is_lvds) {
- dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
- } else {
- if (clock.p1 == 2)
- dpll |= PLL_P1_DIVIDE_BY_TWO;
- else
- dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
- if (clock.p2 == 4)
- dpll |= PLL_P2_DIVIDE_BY_4;
- }
+ /* compute bitmask from p1 value */
+ dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
+ /* also FPA1 */
+ dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
+
+ switch (clock.p2) {
+ case 5:
+ dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
+ break;
+ case 7:
+ dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
+ break;
+ case 10:
+ dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
+ break;
+ case 14:
+ dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
+ break;
}
if (is_sdvo && is_tv)
@@ -4889,50 +5068,15 @@
/* Set up the display plane register */
dspcntr = DISPPLANE_GAMMA_ENABLE;
- /* Ironlake's plane is forced to pipe, bit 24 is to
- enable color space conversion */
- if (!HAS_PCH_SPLIT(dev)) {
- if (pipe == 0)
- dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
- else
- dspcntr |= DISPPLANE_SEL_PIPE_B;
- }
-
- if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
- /* Enable pixel doubling when the dot clock is > 90% of the (display)
- * core speed.
- *
- * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
- * pipe == 0 check?
- */
- if (mode->clock >
- dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
- pipeconf |= PIPECONF_DOUBLE_WIDE;
- else
- pipeconf &= ~PIPECONF_DOUBLE_WIDE;
- }
-
- if (!HAS_PCH_SPLIT(dev))
- dpll |= DPLL_VCO_ENABLE;
-
DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
drm_mode_debug_printmodeline(mode);
- /* assign to Ironlake registers */
- if (HAS_PCH_SPLIT(dev)) {
- fp_reg = PCH_FP0(pipe);
- dpll_reg = PCH_DPLL(pipe);
- } else {
- fp_reg = FP0(pipe);
- dpll_reg = DPLL(pipe);
- }
-
/* PCH eDP needs FDI, but CPU eDP does not */
if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
- I915_WRITE(fp_reg, fp);
- I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
+ I915_WRITE(PCH_FP0(pipe), fp);
+ I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
- POSTING_READ(dpll_reg);
+ POSTING_READ(PCH_DPLL(pipe));
udelay(150);
}
@@ -4964,11 +5108,7 @@
* things on.
*/
if (is_lvds) {
- reg = LVDS;
- if (HAS_PCH_SPLIT(dev))
- reg = PCH_LVDS;
-
- temp = I915_READ(reg);
+ temp = I915_READ(PCH_LVDS);
temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
if (pipe == 1) {
if (HAS_PCH_CPT(dev))
@@ -4995,13 +5135,6 @@
* appropriately here, but we need to look more thoroughly into how
* panels behave in the two modes.
*/
- /* set the dithering flag on non-PCH LVDS as needed */
- if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
- if (dev_priv->lvds_dither)
- temp |= LVDS_ENABLE_DITHER;
- else
- temp &= ~LVDS_ENABLE_DITHER;
- }
if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
lvds_sync |= LVDS_HSYNC_POLARITY;
if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
@@ -5018,22 +5151,20 @@
temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
temp |= lvds_sync;
}
- I915_WRITE(reg, temp);
+ I915_WRITE(PCH_LVDS, temp);
}
/* set the dithering flag and clear for anything other than a panel. */
- if (HAS_PCH_SPLIT(dev)) {
- pipeconf &= ~PIPECONF_DITHER_EN;
- pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
- if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {
- pipeconf |= PIPECONF_DITHER_EN;
- pipeconf |= PIPECONF_DITHER_TYPE_ST1;
- }
+ pipeconf &= ~PIPECONF_DITHER_EN;
+ pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
+ if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {
+ pipeconf |= PIPECONF_DITHER_EN;
+ pipeconf |= PIPECONF_DITHER_TYPE_ST1;
}
if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
intel_dp_set_m_n(crtc, mode, adjusted_mode);
- } else if (HAS_PCH_SPLIT(dev)) {
+ } else {
/* For non-DP output, clear any trans DP clock recovery setting.*/
I915_WRITE(TRANSDATA_M1(pipe), 0);
I915_WRITE(TRANSDATA_N1(pipe), 0);
@@ -5041,43 +5172,32 @@
I915_WRITE(TRANSDPLINK_N1(pipe), 0);
}
- if (!has_edp_encoder || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
- I915_WRITE(dpll_reg, dpll);
+ if (!has_edp_encoder ||
+ intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
+ I915_WRITE(PCH_DPLL(pipe), dpll);
/* Wait for the clocks to stabilize. */
- POSTING_READ(dpll_reg);
+ POSTING_READ(PCH_DPLL(pipe));
udelay(150);
- if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev)) {
- temp = 0;
- if (is_sdvo) {
- temp = intel_mode_get_pixel_multiplier(adjusted_mode);
- if (temp > 1)
- temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
- else
- temp = 0;
- }
- I915_WRITE(DPLL_MD(pipe), temp);
- } else {
- /* The pixel multiplier can only be updated once the
- * DPLL is enabled and the clocks are stable.
- *
- * So write it again.
- */
- I915_WRITE(dpll_reg, dpll);
- }
+ /* The pixel multiplier can only be updated once the
+ * DPLL is enabled and the clocks are stable.
+ *
+ * So write it again.
+ */
+ I915_WRITE(PCH_DPLL(pipe), dpll);
}
intel_crtc->lowfreq_avail = false;
if (is_lvds && has_reduced_clock && i915_powersave) {
- I915_WRITE(fp_reg + 4, fp2);
+ I915_WRITE(PCH_FP1(pipe), fp2);
intel_crtc->lowfreq_avail = true;
if (HAS_PIPE_CXSR(dev)) {
DRM_DEBUG_KMS("enabling CxSR downclocking\n");
pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
}
} else {
- I915_WRITE(fp_reg + 4, fp);
+ I915_WRITE(PCH_FP1(pipe), fp);
if (HAS_PIPE_CXSR(dev)) {
DRM_DEBUG_KMS("disabling CxSR downclocking\n");
pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
@@ -5116,33 +5236,24 @@
(adjusted_mode->crtc_vsync_start - 1) |
((adjusted_mode->crtc_vsync_end - 1) << 16));
- /* pipesrc and dspsize control the size that is scaled from,
- * which should always be the user's requested size.
+ /* pipesrc controls the size that is scaled from, which should
+ * always be the user's requested size.
*/
- if (!HAS_PCH_SPLIT(dev)) {
- I915_WRITE(DSPSIZE(plane),
- ((mode->vdisplay - 1) << 16) |
- (mode->hdisplay - 1));
- I915_WRITE(DSPPOS(plane), 0);
- }
I915_WRITE(PIPESRC(pipe),
((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
- if (HAS_PCH_SPLIT(dev)) {
- I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
- I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
- I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
- I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
+ I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
+ I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
+ I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
+ I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
- if (has_edp_encoder && !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
- ironlake_set_pll_edp(crtc, adjusted_mode->clock);
- }
+ if (has_edp_encoder &&
+ !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
+ ironlake_set_pll_edp(crtc, adjusted_mode->clock);
}
I915_WRITE(PIPECONF(pipe), pipeconf);
POSTING_READ(PIPECONF(pipe));
- if (!HAS_PCH_SPLIT(dev))
- intel_enable_pipe(dev_priv, pipe, false);
intel_wait_for_vblank(dev, pipe);
@@ -5161,6 +5272,26 @@
intel_update_watermarks(dev);
+ return ret;
+}
+
+static int intel_crtc_mode_set(struct drm_crtc *crtc,
+ struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode,
+ int x, int y,
+ struct drm_framebuffer *old_fb)
+{
+ struct drm_device *dev = crtc->dev;
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ int pipe = intel_crtc->pipe;
+ int ret;
+
+ drm_vblank_pre_modeset(dev, pipe);
+
+ ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
+ x, y, old_fb);
+
drm_vblank_post_modeset(dev, pipe);
return ret;
@@ -5483,43 +5614,140 @@
704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
};
-struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
- struct drm_connector *connector,
- struct drm_display_mode *mode,
- int *dpms_mode)
+static struct drm_framebuffer *
+intel_framebuffer_create(struct drm_device *dev,
+ struct drm_mode_fb_cmd *mode_cmd,
+ struct drm_i915_gem_object *obj)
+{
+ struct intel_framebuffer *intel_fb;
+ int ret;
+
+ intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
+ if (!intel_fb) {
+ drm_gem_object_unreference_unlocked(&obj->base);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
+ if (ret) {
+ drm_gem_object_unreference_unlocked(&obj->base);
+ kfree(intel_fb);
+ return ERR_PTR(ret);
+ }
+
+ return &intel_fb->base;
+}
+
+static u32
+intel_framebuffer_pitch_for_width(int width, int bpp)
+{
+ u32 pitch = DIV_ROUND_UP(width * bpp, 8);
+ return ALIGN(pitch, 64);
+}
+
+static u32
+intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
+{
+ u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
+ return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
+}
+
+static struct drm_framebuffer *
+intel_framebuffer_create_for_mode(struct drm_device *dev,
+ struct drm_display_mode *mode,
+ int depth, int bpp)
+{
+ struct drm_i915_gem_object *obj;
+ struct drm_mode_fb_cmd mode_cmd;
+
+ obj = i915_gem_alloc_object(dev,
+ intel_framebuffer_size_for_mode(mode, bpp));
+ if (obj == NULL)
+ return ERR_PTR(-ENOMEM);
+
+ mode_cmd.width = mode->hdisplay;
+ mode_cmd.height = mode->vdisplay;
+ mode_cmd.depth = depth;
+ mode_cmd.bpp = bpp;
+ mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp);
+
+ return intel_framebuffer_create(dev, &mode_cmd, obj);
+}
+
+static struct drm_framebuffer *
+mode_fits_in_fbdev(struct drm_device *dev,
+ struct drm_display_mode *mode)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ struct drm_i915_gem_object *obj;
+ struct drm_framebuffer *fb;
+
+ if (dev_priv->fbdev == NULL)
+ return NULL;
+
+ obj = dev_priv->fbdev->ifb.obj;
+ if (obj == NULL)
+ return NULL;
+
+ fb = &dev_priv->fbdev->ifb.base;
+ if (fb->pitch < intel_framebuffer_pitch_for_width(mode->hdisplay,
+ fb->bits_per_pixel))
+ return NULL;
+
+ if (obj->base.size < mode->vdisplay * fb->pitch)
+ return NULL;
+
+ return fb;
+}
+
+bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
+ struct drm_connector *connector,
+ struct drm_display_mode *mode,
+ struct intel_load_detect_pipe *old)
{
struct intel_crtc *intel_crtc;
struct drm_crtc *possible_crtc;
- struct drm_crtc *supported_crtc =NULL;
struct drm_encoder *encoder = &intel_encoder->base;
struct drm_crtc *crtc = NULL;
struct drm_device *dev = encoder->dev;
- struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
- struct drm_crtc_helper_funcs *crtc_funcs;
+ struct drm_framebuffer *old_fb;
int i = -1;
+ DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
+ connector->base.id, drm_get_connector_name(connector),
+ encoder->base.id, drm_get_encoder_name(encoder));
+
/*
* Algorithm gets a little messy:
+ *
* - if the connector already has an assigned crtc, use it (but make
* sure it's on first)
+ *
* - try to find the first unused crtc that can drive this connector,
* and use that if we find one
- * - if there are no unused crtcs available, try to use the first
- * one we found that supports the connector
*/
/* See if we already have a CRTC for this connector */
if (encoder->crtc) {
crtc = encoder->crtc;
- /* Make sure the crtc and connector are running */
+
intel_crtc = to_intel_crtc(crtc);
- *dpms_mode = intel_crtc->dpms_mode;
+ old->dpms_mode = intel_crtc->dpms_mode;
+ old->load_detect_temp = false;
+
+ /* Make sure the crtc and connector are running */
if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
+ struct drm_encoder_helper_funcs *encoder_funcs;
+ struct drm_crtc_helper_funcs *crtc_funcs;
+
crtc_funcs = crtc->helper_private;
crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
+
+ encoder_funcs = encoder->helper_private;
encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
}
- return crtc;
+
+ return true;
}
/* Find an unused one (if possible) */
@@ -5531,46 +5759,66 @@
crtc = possible_crtc;
break;
}
- if (!supported_crtc)
- supported_crtc = possible_crtc;
}
/*
* If we didn't find an unused CRTC, don't use any.
*/
if (!crtc) {
- return NULL;
+ DRM_DEBUG_KMS("no pipe available for load-detect\n");
+ return false;
}
encoder->crtc = crtc;
connector->encoder = encoder;
- intel_encoder->load_detect_temp = true;
intel_crtc = to_intel_crtc(crtc);
- *dpms_mode = intel_crtc->dpms_mode;
+ old->dpms_mode = intel_crtc->dpms_mode;
+ old->load_detect_temp = true;
+ old->release_fb = NULL;
- if (!crtc->enabled) {
- if (!mode)
- mode = &load_detect_mode;
- drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
- } else {
- if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
- crtc_funcs = crtc->helper_private;
- crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
- }
+ if (!mode)
+ mode = &load_detect_mode;
- /* Add this connector to the crtc */
- encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
- encoder_funcs->commit(encoder);
+ old_fb = crtc->fb;
+
+ /* We need a framebuffer large enough to accommodate all accesses
+ * that the plane may generate whilst we perform load detection.
+ * We can not rely on the fbcon either being present (we get called
+ * during its initialisation to detect all boot displays, or it may
+ * not even exist) or that it is large enough to satisfy the
+ * requested mode.
+ */
+ crtc->fb = mode_fits_in_fbdev(dev, mode);
+ if (crtc->fb == NULL) {
+ DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
+ crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
+ old->release_fb = crtc->fb;
+ } else
+ DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
+ if (IS_ERR(crtc->fb)) {
+ DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
+ crtc->fb = old_fb;
+ return false;
}
+
+ if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
+ DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
+ if (old->release_fb)
+ old->release_fb->funcs->destroy(old->release_fb);
+ crtc->fb = old_fb;
+ return false;
+ }
+
/* let the connector get through one full cycle before testing */
intel_wait_for_vblank(dev, intel_crtc->pipe);
- return crtc;
+ return true;
}
void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
- struct drm_connector *connector, int dpms_mode)
+ struct drm_connector *connector,
+ struct intel_load_detect_pipe *old)
{
struct drm_encoder *encoder = &intel_encoder->base;
struct drm_device *dev = encoder->dev;
@@ -5578,19 +5826,24 @@
struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
- if (intel_encoder->load_detect_temp) {
- encoder->crtc = NULL;
+ DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
+ connector->base.id, drm_get_connector_name(connector),
+ encoder->base.id, drm_get_encoder_name(encoder));
+
+ if (old->load_detect_temp) {
connector->encoder = NULL;
- intel_encoder->load_detect_temp = false;
- crtc->enabled = drm_helper_crtc_in_use(crtc);
drm_helper_disable_unused_functions(dev);
+
+ if (old->release_fb)
+ old->release_fb->funcs->destroy(old->release_fb);
+
+ return;
}
/* Switch crtc and encoder back off if necessary */
- if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
- if (encoder->crtc == crtc)
- encoder_funcs->dpms(encoder, dpms_mode);
- crtc_funcs->dpms(crtc, dpms_mode);
+ if (old->dpms_mode != DRM_MODE_DPMS_ON) {
+ encoder_funcs->dpms(encoder, old->dpms_mode);
+ crtc_funcs->dpms(crtc, old->dpms_mode);
}
}
@@ -6185,6 +6438,7 @@
break;
case 6:
+ case 7:
OUT_RING(MI_DISPLAY_FLIP |
MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
OUT_RING(fb->pitch | obj->tiling_mode);
@@ -6504,6 +6758,9 @@
}
intel_panel_setup_backlight(dev);
+
+ /* disable all the possible outputs/crtcs before entering KMS mode */
+ drm_helper_disable_unused_functions(dev);
}
static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
@@ -6571,27 +6828,12 @@
struct drm_mode_fb_cmd *mode_cmd)
{
struct drm_i915_gem_object *obj;
- struct intel_framebuffer *intel_fb;
- int ret;
obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
if (&obj->base == NULL)
return ERR_PTR(-ENOENT);
- intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
- if (!intel_fb) {
- drm_gem_object_unreference_unlocked(&obj->base);
- return ERR_PTR(-ENOMEM);
- }
-
- ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
- if (ret) {
- drm_gem_object_unreference_unlocked(&obj->base);
- kfree(intel_fb);
- return ERR_PTR(ret);
- }
-
- return &intel_fb->base;
+ return intel_framebuffer_create(dev, mode_cmd, obj);
}
static const struct drm_mode_config_funcs intel_mode_funcs = {
@@ -6605,13 +6847,14 @@
struct drm_i915_gem_object *ctx;
int ret;
+ WARN_ON(!mutex_is_locked(&dev->struct_mutex));
+
ctx = i915_gem_alloc_object(dev, 4096);
if (!ctx) {
DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
return NULL;
}
- mutex_lock(&dev->struct_mutex);
ret = i915_gem_object_pin(ctx, 4096, true);
if (ret) {
DRM_ERROR("failed to pin power context: %d\n", ret);
@@ -6623,7 +6866,6 @@
DRM_ERROR("failed to set-domain on power context: %d\n", ret);
goto err_unpin;
}
- mutex_unlock(&dev->struct_mutex);
return ctx;
@@ -6758,6 +7000,11 @@
I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
I915_WRITE(GEN6_PMIER, 0);
+
+ spin_lock_irq(&dev_priv->rps_lock);
+ dev_priv->pm_iir = 0;
+ spin_unlock_irq(&dev_priv->rps_lock);
+
I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
}
@@ -6851,7 +7098,7 @@
{
u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
- u32 pcu_mbox;
+ u32 pcu_mbox, rc6_mask = 0;
int cur_freq, min_freq, max_freq;
int i;
@@ -6862,7 +7109,8 @@
* userspace...
*/
I915_WRITE(GEN6_RC_STATE, 0);
- __gen6_gt_force_wake_get(dev_priv);
+ mutex_lock(&dev_priv->dev->struct_mutex);
+ gen6_gt_force_wake_get(dev_priv);
/* disable the counters and set deterministic thresholds */
I915_WRITE(GEN6_RC_CONTROL, 0);
@@ -6882,9 +7130,12 @@
I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
+ if (i915_enable_rc6)
+ rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
+ GEN6_RC_CTL_RC6_ENABLE;
+
I915_WRITE(GEN6_RC_CONTROL,
- GEN6_RC_CTL_RC6p_ENABLE |
- GEN6_RC_CTL_RC6_ENABLE |
+ rc6_mask |
GEN6_RC_CTL_EI_MODE(1) |
GEN6_RC_CTL_HW_ENABLE);
@@ -6956,168 +7207,237 @@
GEN6_PM_RP_DOWN_THRESHOLD |
GEN6_PM_RP_UP_EI_EXPIRED |
GEN6_PM_RP_DOWN_EI_EXPIRED);
+ spin_lock_irq(&dev_priv->rps_lock);
+ WARN_ON(dev_priv->pm_iir != 0);
I915_WRITE(GEN6_PMIMR, 0);
+ spin_unlock_irq(&dev_priv->rps_lock);
/* enable all PM interrupts */
I915_WRITE(GEN6_PMINTRMSK, 0);
- __gen6_gt_force_wake_put(dev_priv);
+ gen6_gt_force_wake_put(dev_priv);
+ mutex_unlock(&dev_priv->dev->struct_mutex);
}
-void intel_enable_clock_gating(struct drm_device *dev)
+static void ironlake_init_clock_gating(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
+
+ /* Required for FBC */
+ dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
+ DPFCRUNIT_CLOCK_GATE_DISABLE |
+ DPFDUNIT_CLOCK_GATE_DISABLE;
+ /* Required for CxSR */
+ dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
+
+ I915_WRITE(PCH_3DCGDIS0,
+ MARIUNIT_CLOCK_GATE_DISABLE |
+ SVSMUNIT_CLOCK_GATE_DISABLE);
+ I915_WRITE(PCH_3DCGDIS1,
+ VFMUNIT_CLOCK_GATE_DISABLE);
+
+ I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
+
+ /*
+ * According to the spec the following bits should be set in
+ * order to enable memory self-refresh
+ * The bit 22/21 of 0x42004
+ * The bit 5 of 0x42020
+ * The bit 15 of 0x45000
+ */
+ I915_WRITE(ILK_DISPLAY_CHICKEN2,
+ (I915_READ(ILK_DISPLAY_CHICKEN2) |
+ ILK_DPARB_GATE | ILK_VSDPFD_FULL));
+ I915_WRITE(ILK_DSPCLK_GATE,
+ (I915_READ(ILK_DSPCLK_GATE) |
+ ILK_DPARB_CLK_GATE));
+ I915_WRITE(DISP_ARB_CTL,
+ (I915_READ(DISP_ARB_CTL) |
+ DISP_FBC_WM_DIS));
+ I915_WRITE(WM3_LP_ILK, 0);
+ I915_WRITE(WM2_LP_ILK, 0);
+ I915_WRITE(WM1_LP_ILK, 0);
+
+ /*
+ * Based on the document from hardware guys the following bits
+ * should be set unconditionally in order to enable FBC.
+ * The bit 22 of 0x42000
+ * The bit 22 of 0x42004
+ * The bit 7,8,9 of 0x42020.
+ */
+ if (IS_IRONLAKE_M(dev)) {
+ I915_WRITE(ILK_DISPLAY_CHICKEN1,
+ I915_READ(ILK_DISPLAY_CHICKEN1) |
+ ILK_FBCQ_DIS);
+ I915_WRITE(ILK_DISPLAY_CHICKEN2,
+ I915_READ(ILK_DISPLAY_CHICKEN2) |
+ ILK_DPARB_GATE);
+ I915_WRITE(ILK_DSPCLK_GATE,
+ I915_READ(ILK_DSPCLK_GATE) |
+ ILK_DPFC_DIS1 |
+ ILK_DPFC_DIS2 |
+ ILK_CLK_FBC);
+ }
+
+ I915_WRITE(ILK_DISPLAY_CHICKEN2,
+ I915_READ(ILK_DISPLAY_CHICKEN2) |
+ ILK_ELPIN_409_SELECT);
+ I915_WRITE(_3D_CHICKEN2,
+ _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
+ _3D_CHICKEN2_WM_READ_PIPELINED);
+}
+
+static void gen6_init_clock_gating(struct drm_device *dev)
{
struct drm_i915_private *dev_priv = dev->dev_private;
int pipe;
+ uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
+
+ I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
+
+ I915_WRITE(ILK_DISPLAY_CHICKEN2,
+ I915_READ(ILK_DISPLAY_CHICKEN2) |
+ ILK_ELPIN_409_SELECT);
+
+ I915_WRITE(WM3_LP_ILK, 0);
+ I915_WRITE(WM2_LP_ILK, 0);
+ I915_WRITE(WM1_LP_ILK, 0);
/*
- * Disable clock gating reported to work incorrectly according to the
- * specs, but enable as much else as we can.
+ * According to the spec the following bits should be
+ * set in order to enable memory self-refresh and fbc:
+ * The bit21 and bit22 of 0x42000
+ * The bit21 and bit22 of 0x42004
+ * The bit5 and bit7 of 0x42020
+ * The bit14 of 0x70180
+ * The bit14 of 0x71180
*/
- if (HAS_PCH_SPLIT(dev)) {
- uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
+ I915_WRITE(ILK_DISPLAY_CHICKEN1,
+ I915_READ(ILK_DISPLAY_CHICKEN1) |
+ ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
+ I915_WRITE(ILK_DISPLAY_CHICKEN2,
+ I915_READ(ILK_DISPLAY_CHICKEN2) |
+ ILK_DPARB_GATE | ILK_VSDPFD_FULL);
+ I915_WRITE(ILK_DSPCLK_GATE,
+ I915_READ(ILK_DSPCLK_GATE) |
+ ILK_DPARB_CLK_GATE |
+ ILK_DPFD_CLK_GATE);
- if (IS_GEN5(dev)) {
- /* Required for FBC */
- dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
- DPFCRUNIT_CLOCK_GATE_DISABLE |
- DPFDUNIT_CLOCK_GATE_DISABLE;
- /* Required for CxSR */
- dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
+ for_each_pipe(pipe)
+ I915_WRITE(DSPCNTR(pipe),
+ I915_READ(DSPCNTR(pipe)) |
+ DISPPLANE_TRICKLE_FEED_DISABLE);
+}
- I915_WRITE(PCH_3DCGDIS0,
- MARIUNIT_CLOCK_GATE_DISABLE |
- SVSMUNIT_CLOCK_GATE_DISABLE);
- I915_WRITE(PCH_3DCGDIS1,
- VFMUNIT_CLOCK_GATE_DISABLE);
- }
+static void ivybridge_init_clock_gating(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ int pipe;
+ uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
- I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
+ I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
- /*
- * On Ibex Peak and Cougar Point, we need to disable clock
- * gating for the panel power sequencer or it will fail to
- * start up when no ports are active.
- */
- I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
+ I915_WRITE(WM3_LP_ILK, 0);
+ I915_WRITE(WM2_LP_ILK, 0);
+ I915_WRITE(WM1_LP_ILK, 0);
- /*
- * According to the spec the following bits should be set in
- * order to enable memory self-refresh
- * The bit 22/21 of 0x42004
- * The bit 5 of 0x42020
- * The bit 15 of 0x45000
- */
- if (IS_GEN5(dev)) {
- I915_WRITE(ILK_DISPLAY_CHICKEN2,
- (I915_READ(ILK_DISPLAY_CHICKEN2) |
- ILK_DPARB_GATE | ILK_VSDPFD_FULL));
- I915_WRITE(ILK_DSPCLK_GATE,
- (I915_READ(ILK_DSPCLK_GATE) |
- ILK_DPARB_CLK_GATE));
- I915_WRITE(DISP_ARB_CTL,
- (I915_READ(DISP_ARB_CTL) |
- DISP_FBC_WM_DIS));
- I915_WRITE(WM3_LP_ILK, 0);
- I915_WRITE(WM2_LP_ILK, 0);
- I915_WRITE(WM1_LP_ILK, 0);
- }
- /*
- * Based on the document from hardware guys the following bits
- * should be set unconditionally in order to enable FBC.
- * The bit 22 of 0x42000
- * The bit 22 of 0x42004
- * The bit 7,8,9 of 0x42020.
- */
- if (IS_IRONLAKE_M(dev)) {
- I915_WRITE(ILK_DISPLAY_CHICKEN1,
- I915_READ(ILK_DISPLAY_CHICKEN1) |
- ILK_FBCQ_DIS);
- I915_WRITE(ILK_DISPLAY_CHICKEN2,
- I915_READ(ILK_DISPLAY_CHICKEN2) |
- ILK_DPARB_GATE);
- I915_WRITE(ILK_DSPCLK_GATE,
- I915_READ(ILK_DSPCLK_GATE) |
- ILK_DPFC_DIS1 |
- ILK_DPFC_DIS2 |
- ILK_CLK_FBC);
- }
+ I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
- I915_WRITE(ILK_DISPLAY_CHICKEN2,
- I915_READ(ILK_DISPLAY_CHICKEN2) |
- ILK_ELPIN_409_SELECT);
+ for_each_pipe(pipe)
+ I915_WRITE(DSPCNTR(pipe),
+ I915_READ(DSPCNTR(pipe)) |
+ DISPPLANE_TRICKLE_FEED_DISABLE);
+}
- if (IS_GEN5(dev)) {
- I915_WRITE(_3D_CHICKEN2,
- _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
- _3D_CHICKEN2_WM_READ_PIPELINED);
- }
+static void g4x_init_clock_gating(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ uint32_t dspclk_gate;
- if (IS_GEN6(dev)) {
- I915_WRITE(WM3_LP_ILK, 0);
- I915_WRITE(WM2_LP_ILK, 0);
- I915_WRITE(WM1_LP_ILK, 0);
+ I915_WRITE(RENCLK_GATE_D1, 0);
+ I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
+ GS_UNIT_CLOCK_GATE_DISABLE |
+ CL_UNIT_CLOCK_GATE_DISABLE);
+ I915_WRITE(RAMCLK_GATE_D, 0);
+ dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
+ OVRUNIT_CLOCK_GATE_DISABLE |
+ OVCUNIT_CLOCK_GATE_DISABLE;
+ if (IS_GM45(dev))
+ dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
+ I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
+}
- /*
- * According to the spec the following bits should be
- * set in order to enable memory self-refresh and fbc:
- * The bit21 and bit22 of 0x42000
- * The bit21 and bit22 of 0x42004
- * The bit5 and bit7 of 0x42020
- * The bit14 of 0x70180
- * The bit14 of 0x71180
- */
- I915_WRITE(ILK_DISPLAY_CHICKEN1,
- I915_READ(ILK_DISPLAY_CHICKEN1) |
- ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
- I915_WRITE(ILK_DISPLAY_CHICKEN2,
- I915_READ(ILK_DISPLAY_CHICKEN2) |
- ILK_DPARB_GATE | ILK_VSDPFD_FULL);
- I915_WRITE(ILK_DSPCLK_GATE,
- I915_READ(ILK_DSPCLK_GATE) |
- ILK_DPARB_CLK_GATE |
- ILK_DPFD_CLK_GATE);
+static void crestline_init_clock_gating(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
- for_each_pipe(pipe)
- I915_WRITE(DSPCNTR(pipe),
- I915_READ(DSPCNTR(pipe)) |
- DISPPLANE_TRICKLE_FEED_DISABLE);
- }
- } else if (IS_G4X(dev)) {
- uint32_t dspclk_gate;
- I915_WRITE(RENCLK_GATE_D1, 0);
- I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
- GS_UNIT_CLOCK_GATE_DISABLE |
- CL_UNIT_CLOCK_GATE_DISABLE);
- I915_WRITE(RAMCLK_GATE_D, 0);
- dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
- OVRUNIT_CLOCK_GATE_DISABLE |
- OVCUNIT_CLOCK_GATE_DISABLE;
- if (IS_GM45(dev))
- dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
- I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
- } else if (IS_CRESTLINE(dev)) {
- I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
- I915_WRITE(RENCLK_GATE_D2, 0);
- I915_WRITE(DSPCLK_GATE_D, 0);
- I915_WRITE(RAMCLK_GATE_D, 0);
- I915_WRITE16(DEUC, 0);
- } else if (IS_BROADWATER(dev)) {
- I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
- I965_RCC_CLOCK_GATE_DISABLE |
- I965_RCPB_CLOCK_GATE_DISABLE |
- I965_ISC_CLOCK_GATE_DISABLE |
- I965_FBC_CLOCK_GATE_DISABLE);
- I915_WRITE(RENCLK_GATE_D2, 0);
- } else if (IS_GEN3(dev)) {
- u32 dstate = I915_READ(D_STATE);
+ I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
+ I915_WRITE(RENCLK_GATE_D2, 0);
+ I915_WRITE(DSPCLK_GATE_D, 0);
+ I915_WRITE(RAMCLK_GATE_D, 0);
+ I915_WRITE16(DEUC, 0);
+}
- dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
- DSTATE_DOT_CLOCK_GATING;
- I915_WRITE(D_STATE, dstate);
- } else if (IS_I85X(dev) || IS_I865G(dev)) {
- I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
- } else if (IS_I830(dev)) {
- I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
- }
+static void broadwater_init_clock_gating(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
+ I965_RCC_CLOCK_GATE_DISABLE |
+ I965_RCPB_CLOCK_GATE_DISABLE |
+ I965_ISC_CLOCK_GATE_DISABLE |
+ I965_FBC_CLOCK_GATE_DISABLE);
+ I915_WRITE(RENCLK_GATE_D2, 0);
+}
+
+static void gen3_init_clock_gating(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ u32 dstate = I915_READ(D_STATE);
+
+ dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
+ DSTATE_DOT_CLOCK_GATING;
+ I915_WRITE(D_STATE, dstate);
+}
+
+static void i85x_init_clock_gating(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
+}
+
+static void i830_init_clock_gating(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
+}
+
+static void ibx_init_clock_gating(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ /*
+ * On Ibex Peak and Cougar Point, we need to disable clock
+ * gating for the panel power sequencer or it will fail to
+ * start up when no ports are active.
+ */
+ I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
+}
+
+static void cpt_init_clock_gating(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ /*
+ * On Ibex Peak and Cougar Point, we need to disable clock
+ * gating for the panel power sequencer or it will fail to
+ * start up when no ports are active.
+ */
+ I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
+ I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
+ DPLS_EDP_PPS_FIX_DIS);
}
static void ironlake_teardown_rc6(struct drm_device *dev)
@@ -7187,9 +7507,12 @@
if (!i915_enable_rc6)
return;
+ mutex_lock(&dev->struct_mutex);
ret = ironlake_setup_rc6(dev);
- if (ret)
+ if (ret) {
+ mutex_unlock(&dev->struct_mutex);
return;
+ }
/*
* GPU can automatically power down the render unit if given a page
@@ -7198,6 +7521,7 @@
ret = BEGIN_LP_RING(6);
if (ret) {
ironlake_teardown_rc6(dev);
+ mutex_unlock(&dev->struct_mutex);
return;
}
@@ -7213,10 +7537,33 @@
OUT_RING(MI_FLUSH);
ADVANCE_LP_RING();
+ /*
+ * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
+ * does an implicit flush, combined with MI_FLUSH above, it should be
+ * safe to assume that renderctx is valid
+ */
+ ret = intel_wait_ring_idle(LP_RING(dev_priv));
+ if (ret) {
+ DRM_ERROR("failed to enable ironlake power power savings\n");
+ ironlake_teardown_rc6(dev);
+ mutex_unlock(&dev->struct_mutex);
+ return;
+ }
+
I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
+ mutex_unlock(&dev->struct_mutex);
}
+void intel_init_clock_gating(struct drm_device *dev)
+{
+ struct drm_i915_private *dev_priv = dev->dev_private;
+
+ dev_priv->display.init_clock_gating(dev);
+
+ if (dev_priv->display.init_pch_clock_gating)
+ dev_priv->display.init_pch_clock_gating(dev);
+}
/* Set up chip specific display functions */
static void intel_init_display(struct drm_device *dev)
@@ -7224,10 +7571,13 @@
struct drm_i915_private *dev_priv = dev->dev_private;
/* We always want a DPMS function */
- if (HAS_PCH_SPLIT(dev))
+ if (HAS_PCH_SPLIT(dev)) {
dev_priv->display.dpms = ironlake_crtc_dpms;
- else
+ dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
+ } else {
dev_priv->display.dpms = i9xx_crtc_dpms;
+ dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
+ }
if (I915_HAS_FBC(dev)) {
if (HAS_PCH_SPLIT(dev)) {
@@ -7271,6 +7621,11 @@
/* For FIFO watermark updates */
if (HAS_PCH_SPLIT(dev)) {
+ if (HAS_PCH_IBX(dev))
+ dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
+ else if (HAS_PCH_CPT(dev))
+ dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
+
if (IS_GEN5(dev)) {
if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
dev_priv->display.update_wm = ironlake_update_wm;
@@ -7279,6 +7634,8 @@
"Disable CxSR\n");
dev_priv->display.update_wm = NULL;
}
+ dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
+ dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
} else if (IS_GEN6(dev)) {
if (SNB_READ_WM0_LATENCY()) {
dev_priv->display.update_wm = sandybridge_update_wm;
@@ -7287,6 +7644,20 @@
"Disable CxSR\n");
dev_priv->display.update_wm = NULL;
}
+ dev_priv->display.fdi_link_train = gen6_fdi_link_train;
+ dev_priv->display.init_clock_gating = gen6_init_clock_gating;
+ } else if (IS_IVYBRIDGE(dev)) {
+ /* FIXME: detect B0+ stepping and use auto training */
+ dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
+ if (SNB_READ_WM0_LATENCY()) {
+ dev_priv->display.update_wm = sandybridge_update_wm;
+ } else {
+ DRM_DEBUG_KMS("Failed to read display plane latency. "
+ "Disable CxSR\n");
+ dev_priv->display.update_wm = NULL;
+ }
+ dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
+
} else
dev_priv->display.update_wm = NULL;
} else if (IS_PINEVIEW(dev)) {
@@ -7304,18 +7675,30 @@
dev_priv->display.update_wm = NULL;
} else
dev_priv->display.update_wm = pineview_update_wm;
- } else if (IS_G4X(dev))
+ } else if (IS_G4X(dev)) {
dev_priv->display.update_wm = g4x_update_wm;
- else if (IS_GEN4(dev))
+ dev_priv->display.init_clock_gating = g4x_init_clock_gating;
+ } else if (IS_GEN4(dev)) {
dev_priv->display.update_wm = i965_update_wm;
- else if (IS_GEN3(dev)) {
+ if (IS_CRESTLINE(dev))
+ dev_priv->display.init_clock_gating = crestline_init_clock_gating;
+ else if (IS_BROADWATER(dev))
+ dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
+ } else if (IS_GEN3(dev)) {
dev_priv->display.update_wm = i9xx_update_wm;
dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
+ dev_priv->display.init_clock_gating = gen3_init_clock_gating;
+ } else if (IS_I865G(dev)) {
+ dev_priv->display.update_wm = i830_update_wm;
+ dev_priv->display.init_clock_gating = i85x_init_clock_gating;
+ dev_priv->display.get_fifo_size = i830_get_fifo_size;
} else if (IS_I85X(dev)) {
dev_priv->display.update_wm = i9xx_update_wm;
dev_priv->display.get_fifo_size = i85x_get_fifo_size;
+ dev_priv->display.init_clock_gating = i85x_init_clock_gating;
} else {
dev_priv->display.update_wm = i830_update_wm;
+ dev_priv->display.init_clock_gating = i830_init_clock_gating;
if (IS_845G(dev))
dev_priv->display.get_fifo_size = i845_get_fifo_size;
else
@@ -7441,12 +7824,11 @@
intel_crtc_init(dev, i);
}
- intel_setup_outputs(dev);
-
- intel_enable_clock_gating(dev);
-
/* Just disable it once at startup */
i915_disable_vga(dev);
+ intel_setup_outputs(dev);
+
+ intel_init_clock_gating(dev);
if (IS_IRONLAKE_M(dev)) {
ironlake_enable_drps(dev);
@@ -7456,12 +7838,15 @@
if (IS_GEN6(dev))
gen6_enable_rps(dev_priv);
- if (IS_IRONLAKE_M(dev))
- ironlake_enable_rc6(dev);
-
INIT_WORK(&dev_priv->idle_work, intel_idle_update);
setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
(unsigned long)dev);
+}
+
+void intel_modeset_gem_init(struct drm_device *dev)
+{
+ if (IS_IRONLAKE_M(dev))
+ ironlake_enable_rc6(dev);
intel_setup_overlay(dev);
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 1d20712..831d7a4 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -140,7 +140,6 @@
struct intel_encoder {
struct drm_encoder base;
int type;
- bool load_detect_temp;
bool needs_tv_clock;
void (*hot_plug)(struct intel_encoder *);
int crtc_mask;
@@ -291,13 +290,19 @@
struct drm_file *file_priv);
extern void intel_wait_for_vblank(struct drm_device *dev, int pipe);
extern void intel_wait_for_pipe_off(struct drm_device *dev, int pipe);
-extern struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
- struct drm_connector *connector,
- struct drm_display_mode *mode,
- int *dpms_mode);
+
+struct intel_load_detect_pipe {
+ struct drm_framebuffer *release_fb;
+ bool load_detect_temp;
+ int dpms_mode;
+};
+extern bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
+ struct drm_connector *connector,
+ struct drm_display_mode *mode,
+ struct intel_load_detect_pipe *old);
extern void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
struct drm_connector *connector,
- int dpms_mode);
+ struct intel_load_detect_pipe *old);
extern struct drm_connector* intel_sdvo_find(struct drm_device *dev, int sdvoB);
extern int intel_sdvo_supports_hotplug(struct drm_connector *connector);
@@ -339,4 +344,6 @@
extern void intel_fb_output_poll_changed(struct drm_device *dev);
extern void intel_fb_restore_mode(struct drm_device *dev);
+
+extern void intel_init_clock_gating(struct drm_device *dev);
#endif /* __INTEL_DRV_H__ */
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index e9e6f71..95c4b14 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -236,7 +236,7 @@
ret = -ENOMEM;
goto err;
}
- obj->agp_type = AGP_USER_CACHED_MEMORY;
+ obj->cache_level = I915_CACHE_LLC;
ret = i915_gem_object_pin(obj, 4096, true);
if (ret)
@@ -286,7 +286,7 @@
if (INTEL_INFO(dev)->gen > 3) {
int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH;
- if (IS_GEN6(dev))
+ if (IS_GEN6(dev) || IS_GEN7(dev))
mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE;
I915_WRITE(MI_MODE, mode);
}
@@ -551,10 +551,31 @@
void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
{
+ struct drm_device *dev = ring->dev;
drm_i915_private_t *dev_priv = ring->dev->dev_private;
- u32 mmio = IS_GEN6(ring->dev) ?
- RING_HWS_PGA_GEN6(ring->mmio_base) :
- RING_HWS_PGA(ring->mmio_base);
+ u32 mmio = 0;
+
+ /* The ring status page addresses are no longer next to the rest of
+ * the ring registers as of gen7.
+ */
+ if (IS_GEN7(dev)) {
+ switch (ring->id) {
+ case RING_RENDER:
+ mmio = RENDER_HWS_PGA_GEN7;
+ break;
+ case RING_BLT:
+ mmio = BLT_HWS_PGA_GEN7;
+ break;
+ case RING_BSD:
+ mmio = BSD_HWS_PGA_GEN7;
+ break;
+ }
+ } else if (IS_GEN6(ring->dev)) {
+ mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
+ } else {
+ mmio = RING_HWS_PGA(ring->mmio_base);
+ }
+
I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
POSTING_READ(mmio);
}
@@ -600,35 +621,6 @@
}
static bool
-ring_get_irq(struct intel_ring_buffer *ring, u32 flag)
-{
- struct drm_device *dev = ring->dev;
- drm_i915_private_t *dev_priv = dev->dev_private;
-
- if (!dev->irq_enabled)
- return false;
-
- spin_lock(&ring->irq_lock);
- if (ring->irq_refcount++ == 0)
- ironlake_enable_irq(dev_priv, flag);
- spin_unlock(&ring->irq_lock);
-
- return true;
-}
-
-static void
-ring_put_irq(struct intel_ring_buffer *ring, u32 flag)
-{
- struct drm_device *dev = ring->dev;
- drm_i915_private_t *dev_priv = dev->dev_private;
-
- spin_lock(&ring->irq_lock);
- if (--ring->irq_refcount == 0)
- ironlake_disable_irq(dev_priv, flag);
- spin_unlock(&ring->irq_lock);
-}
-
-static bool
gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
{
struct drm_device *dev = ring->dev;
@@ -666,12 +658,37 @@
static bool
bsd_ring_get_irq(struct intel_ring_buffer *ring)
{
- return ring_get_irq(ring, GT_BSD_USER_INTERRUPT);
+ struct drm_device *dev = ring->dev;
+ drm_i915_private_t *dev_priv = dev->dev_private;
+
+ if (!dev->irq_enabled)
+ return false;
+
+ spin_lock(&ring->irq_lock);
+ if (ring->irq_refcount++ == 0) {
+ if (IS_G4X(dev))
+ i915_enable_irq(dev_priv, I915_BSD_USER_INTERRUPT);
+ else
+ ironlake_enable_irq(dev_priv, GT_BSD_USER_INTERRUPT);
+ }
+ spin_unlock(&ring->irq_lock);
+
+ return true;
}
static void
bsd_ring_put_irq(struct intel_ring_buffer *ring)
{
- ring_put_irq(ring, GT_BSD_USER_INTERRUPT);
+ struct drm_device *dev = ring->dev;
+ drm_i915_private_t *dev_priv = dev->dev_private;
+
+ spin_lock(&ring->irq_lock);
+ if (--ring->irq_refcount == 0) {
+ if (IS_G4X(dev))
+ i915_disable_irq(dev_priv, I915_BSD_USER_INTERRUPT);
+ else
+ ironlake_disable_irq(dev_priv, GT_BSD_USER_INTERRUPT);
+ }
+ spin_unlock(&ring->irq_lock);
}
static int
@@ -759,7 +776,7 @@
ret = -ENOMEM;
goto err;
}
- obj->agp_type = AGP_USER_CACHED_MEMORY;
+ obj->cache_level = I915_CACHE_LLC;
ret = i915_gem_object_pin(obj, 4096, true);
if (ret != 0) {
@@ -800,6 +817,7 @@
INIT_LIST_HEAD(&ring->request_list);
INIT_LIST_HEAD(&ring->gpu_write_list);
+ init_waitqueue_head(&ring->irq_queue);
spin_lock_init(&ring->irq_lock);
ring->irq_mask = ~0;
@@ -872,7 +890,7 @@
/* Disable the ring buffer. The ring must be idle at this point */
dev_priv = ring->dev->dev_private;
- ret = intel_wait_ring_buffer(ring, ring->size - 8);
+ ret = intel_wait_ring_idle(ring);
if (ret)
DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
ring->name, ret);
@@ -1333,7 +1351,7 @@
drm_i915_private_t *dev_priv = dev->dev_private;
struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
- if (IS_GEN6(dev))
+ if (IS_GEN6(dev) || IS_GEN7(dev))
*ring = gen6_bsd_ring;
else
*ring = bsd_ring;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index f23cc5f..c0e0ee6 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -14,27 +14,24 @@
struct drm_i915_gem_object *obj;
};
-#define I915_RING_READ(reg) i915_gt_read(dev_priv, reg)
-#define I915_RING_WRITE(reg, val) i915_gt_write(dev_priv, reg, val)
+#define I915_READ_TAIL(ring) I915_READ(RING_TAIL((ring)->mmio_base))
+#define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val)
-#define I915_READ_TAIL(ring) I915_RING_READ(RING_TAIL((ring)->mmio_base))
-#define I915_WRITE_TAIL(ring, val) I915_RING_WRITE(RING_TAIL((ring)->mmio_base), val)
+#define I915_READ_START(ring) I915_READ(RING_START((ring)->mmio_base))
+#define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val)
-#define I915_READ_START(ring) I915_RING_READ(RING_START((ring)->mmio_base))
-#define I915_WRITE_START(ring, val) I915_RING_WRITE(RING_START((ring)->mmio_base), val)
+#define I915_READ_HEAD(ring) I915_READ(RING_HEAD((ring)->mmio_base))
+#define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val)
-#define I915_READ_HEAD(ring) I915_RING_READ(RING_HEAD((ring)->mmio_base))
-#define I915_WRITE_HEAD(ring, val) I915_RING_WRITE(RING_HEAD((ring)->mmio_base), val)
+#define I915_READ_CTL(ring) I915_READ(RING_CTL((ring)->mmio_base))
+#define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val)
-#define I915_READ_CTL(ring) I915_RING_READ(RING_CTL((ring)->mmio_base))
-#define I915_WRITE_CTL(ring, val) I915_RING_WRITE(RING_CTL((ring)->mmio_base), val)
+#define I915_READ_IMR(ring) I915_READ(RING_IMR((ring)->mmio_base))
+#define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val)
-#define I915_READ_IMR(ring) I915_RING_READ(RING_IMR((ring)->mmio_base))
-#define I915_WRITE_IMR(ring, val) I915_RING_WRITE(RING_IMR((ring)->mmio_base), val)
-
-#define I915_READ_NOPID(ring) I915_RING_READ(RING_NOPID((ring)->mmio_base))
-#define I915_READ_SYNC_0(ring) I915_RING_READ(RING_SYNC_0((ring)->mmio_base))
-#define I915_READ_SYNC_1(ring) I915_RING_READ(RING_SYNC_1((ring)->mmio_base))
+#define I915_READ_NOPID(ring) I915_READ(RING_NOPID((ring)->mmio_base))
+#define I915_READ_SYNC_0(ring) I915_READ(RING_SYNC_0((ring)->mmio_base))
+#define I915_READ_SYNC_1(ring) I915_READ(RING_SYNC_1((ring)->mmio_base))
struct intel_ring_buffer {
const char *name;
@@ -164,7 +161,13 @@
#define I915_BREADCRUMB_INDEX 0x21
void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring);
+
int __must_check intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n);
+static inline int intel_wait_ring_idle(struct intel_ring_buffer *ring)
+{
+ return intel_wait_ring_buffer(ring, ring->space - 8);
+}
+
int __must_check intel_ring_begin(struct intel_ring_buffer *ring, int n);
static inline void intel_ring_emit(struct intel_ring_buffer *ring,
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 4324f33..754086f 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -2544,21 +2544,19 @@
if (!intel_sdvo)
return false;
+ intel_sdvo->sdvo_reg = sdvo_reg;
+ intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, sdvo_reg) >> 1;
+ intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg);
if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev)) {
kfree(intel_sdvo);
return false;
}
- intel_sdvo->sdvo_reg = sdvo_reg;
-
+ /* encoder type will be decided later */
intel_encoder = &intel_sdvo->base;
intel_encoder->type = INTEL_OUTPUT_SDVO;
- /* encoder type will be decided later */
drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0);
- intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, sdvo_reg) >> 1;
- intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg);
-
/* Read the regs to test if we can talk to the device */
for (i = 0; i < 0x40; i++) {
u8 byte;
diff --git a/drivers/gpu/drm/i915/intel_tv.c b/drivers/gpu/drm/i915/intel_tv.c
index 6b22c1d..113e4e7 100644
--- a/drivers/gpu/drm/i915/intel_tv.c
+++ b/drivers/gpu/drm/i915/intel_tv.c
@@ -1361,15 +1361,14 @@
if (intel_tv->base.base.crtc && intel_tv->base.base.crtc->enabled) {
type = intel_tv_detect_type(intel_tv, connector);
} else if (force) {
- struct drm_crtc *crtc;
- int dpms_mode;
+ struct intel_load_detect_pipe tmp;
- crtc = intel_get_load_detect_pipe(&intel_tv->base, connector,
- &mode, &dpms_mode);
- if (crtc) {
+ if (intel_get_load_detect_pipe(&intel_tv->base, connector,
+ &mode, &tmp)) {
type = intel_tv_detect_type(intel_tv, connector);
- intel_release_load_detect_pipe(&intel_tv->base, connector,
- dpms_mode);
+ intel_release_load_detect_pipe(&intel_tv->base,
+ connector,
+ &tmp);
} else
return connector_status_unknown;
} else
diff --git a/drivers/gpu/drm/nouveau/Kconfig b/drivers/gpu/drm/nouveau/Kconfig
index de70959..ca16399 100644
--- a/drivers/gpu/drm/nouveau/Kconfig
+++ b/drivers/gpu/drm/nouveau/Kconfig
@@ -11,6 +11,8 @@
select FRAMEBUFFER_CONSOLE if !EXPERT
select FB_BACKLIGHT if DRM_NOUVEAU_BACKLIGHT
select ACPI_VIDEO if ACPI && X86 && BACKLIGHT_CLASS_DEVICE && VIDEO_OUTPUT_CONTROL && INPUT
+ select ACPI_WMI if ACPI
+ select MXM_WMI if ACPI
help
Choose this option for open-source nVidia support.
diff --git a/drivers/gpu/drm/nouveau/Makefile b/drivers/gpu/drm/nouveau/Makefile
index e12c97f..0583677 100644
--- a/drivers/gpu/drm/nouveau/Makefile
+++ b/drivers/gpu/drm/nouveau/Makefile
@@ -20,6 +20,8 @@
nv40_graph.o nv50_graph.o nvc0_graph.o \
nv40_grctx.o nv50_grctx.o nvc0_grctx.o \
nv84_crypt.o \
+ nva3_copy.o nvc0_copy.o \
+ nv40_mpeg.o nv50_mpeg.o \
nv04_instmem.o nv50_instmem.o nvc0_instmem.o \
nv50_evo.o nv50_crtc.o nv50_dac.o nv50_sor.o \
nv50_cursor.o nv50_display.o \
diff --git a/drivers/gpu/drm/nouveau/nouveau_acpi.c b/drivers/gpu/drm/nouveau/nouveau_acpi.c
index a542380..f0d459b 100644
--- a/drivers/gpu/drm/nouveau/nouveau_acpi.c
+++ b/drivers/gpu/drm/nouveau/nouveau_acpi.c
@@ -4,6 +4,8 @@
#include <acpi/acpi_drivers.h>
#include <acpi/acpi_bus.h>
#include <acpi/video.h>
+#include <acpi/acpi.h>
+#include <linux/mxm-wmi.h>
#include "drmP.h"
#include "drm.h"
@@ -35,15 +37,71 @@
static struct nouveau_dsm_priv {
bool dsm_detected;
+ bool optimus_detected;
acpi_handle dhandle;
acpi_handle rom_handle;
} nouveau_dsm_priv;
+#define NOUVEAU_DSM_HAS_MUX 0x1
+#define NOUVEAU_DSM_HAS_OPT 0x2
+
static const char nouveau_dsm_muid[] = {
0xA0, 0xA0, 0x95, 0x9D, 0x60, 0x00, 0x48, 0x4D,
0xB3, 0x4D, 0x7E, 0x5F, 0xEA, 0x12, 0x9F, 0xD4,
};
+static const char nouveau_op_dsm_muid[] = {
+ 0xF8, 0xD8, 0x86, 0xA4, 0xDA, 0x0B, 0x1B, 0x47,
+ 0xA7, 0x2B, 0x60, 0x42, 0xA6, 0xB5, 0xBE, 0xE0,
+};
+
+static int nouveau_optimus_dsm(acpi_handle handle, int func, int arg, uint32_t *result)
+{
+ struct acpi_buffer output = { ACPI_ALLOCATE_BUFFER, NULL };
+ struct acpi_object_list input;
+ union acpi_object params[4];
+ union acpi_object *obj;
+ int err;
+
+ input.count = 4;
+ input.pointer = params;
+ params[0].type = ACPI_TYPE_BUFFER;
+ params[0].buffer.length = sizeof(nouveau_op_dsm_muid);
+ params[0].buffer.pointer = (char *)nouveau_op_dsm_muid;
+ params[1].type = ACPI_TYPE_INTEGER;
+ params[1].integer.value = 0x00000100;
+ params[2].type = ACPI_TYPE_INTEGER;
+ params[2].integer.value = func;
+ params[3].type = ACPI_TYPE_BUFFER;
+ params[3].buffer.length = 0;
+
+ err = acpi_evaluate_object(handle, "_DSM", &input, &output);
+ if (err) {
+ printk(KERN_INFO "failed to evaluate _DSM: %d\n", err);
+ return err;
+ }
+
+ obj = (union acpi_object *)output.pointer;
+
+ if (obj->type == ACPI_TYPE_INTEGER)
+ if (obj->integer.value == 0x80000002) {
+ return -ENODEV;
+ }
+
+ if (obj->type == ACPI_TYPE_BUFFER) {
+ if (obj->buffer.length == 4 && result) {
+ *result = 0;
+ *result |= obj->buffer.pointer[0];
+ *result |= (obj->buffer.pointer[1] << 8);
+ *result |= (obj->buffer.pointer[2] << 16);
+ *result |= (obj->buffer.pointer[3] << 24);
+ }
+ }
+
+ kfree(output.pointer);
+ return 0;
+}
+
static int nouveau_dsm(acpi_handle handle, int func, int arg, uint32_t *result)
{
struct acpi_buffer output = { ACPI_ALLOCATE_BUFFER, NULL };
@@ -92,6 +150,8 @@
static int nouveau_dsm_switch_mux(acpi_handle handle, int mux_id)
{
+ mxm_wmi_call_mxmx(mux_id == NOUVEAU_DSM_LED_STAMINA ? MXM_MXDS_ADAPTER_IGD : MXM_MXDS_ADAPTER_0);
+ mxm_wmi_call_mxds(mux_id == NOUVEAU_DSM_LED_STAMINA ? MXM_MXDS_ADAPTER_IGD : MXM_MXDS_ADAPTER_0);
return nouveau_dsm(handle, NOUVEAU_DSM_LED, mux_id, NULL);
}
@@ -148,11 +208,11 @@
.get_client_id = nouveau_dsm_get_client_id,
};
-static bool nouveau_dsm_pci_probe(struct pci_dev *pdev)
+static int nouveau_dsm_pci_probe(struct pci_dev *pdev)
{
acpi_handle dhandle, nvidia_handle;
acpi_status status;
- int ret;
+ int ret, retval = 0;
uint32_t result;
dhandle = DEVICE_ACPI_HANDLE(&pdev->dev);
@@ -166,11 +226,17 @@
ret = nouveau_dsm(dhandle, NOUVEAU_DSM_SUPPORTED,
NOUVEAU_DSM_SUPPORTED_FUNCTIONS, &result);
- if (ret < 0)
- return false;
+ if (ret == 0)
+ retval |= NOUVEAU_DSM_HAS_MUX;
- nouveau_dsm_priv.dhandle = dhandle;
- return true;
+ ret = nouveau_optimus_dsm(dhandle, 0, 0, &result);
+ if (ret == 0)
+ retval |= NOUVEAU_DSM_HAS_OPT;
+
+ if (retval)
+ nouveau_dsm_priv.dhandle = dhandle;
+
+ return retval;
}
static bool nouveau_dsm_detect(void)
@@ -179,22 +245,42 @@
struct acpi_buffer buffer = {sizeof(acpi_method_name), acpi_method_name};
struct pci_dev *pdev = NULL;
int has_dsm = 0;
+ int has_optimus;
int vga_count = 0;
+ bool guid_valid;
+ int retval;
+ bool ret = false;
+ /* lookup the MXM GUID */
+ guid_valid = mxm_wmi_supported();
+
+ if (guid_valid)
+ printk("MXM: GUID detected in BIOS\n");
+
+ /* now do DSM detection */
while ((pdev = pci_get_class(PCI_CLASS_DISPLAY_VGA << 8, pdev)) != NULL) {
vga_count++;
- has_dsm |= (nouveau_dsm_pci_probe(pdev) == true);
+ retval = nouveau_dsm_pci_probe(pdev);
+ printk("ret val is %d\n", retval);
+ if (retval & NOUVEAU_DSM_HAS_MUX)
+ has_dsm |= 1;
+ if (retval & NOUVEAU_DSM_HAS_OPT)
+ has_optimus = 1;
}
- if (vga_count == 2 && has_dsm) {
+ if (vga_count == 2 && has_dsm && guid_valid) {
acpi_get_name(nouveau_dsm_priv.dhandle, ACPI_FULL_PATHNAME, &buffer);
printk(KERN_INFO "VGA switcheroo: detected DSM switching method %s handle\n",
acpi_method_name);
nouveau_dsm_priv.dsm_detected = true;
- return true;
+ ret = true;
}
- return false;
+
+ if (has_optimus == 1)
+ nouveau_dsm_priv.optimus_detected = true;
+
+ return ret;
}
void nouveau_register_dsm_handler(void)
@@ -247,7 +333,7 @@
acpi_status status;
acpi_handle dhandle, rom_handle;
- if (!nouveau_dsm_priv.dsm_detected)
+ if (!nouveau_dsm_priv.dsm_detected && !nouveau_dsm_priv.optimus_detected)
return false;
dhandle = DEVICE_ACPI_HANDLE(&pdev->dev);
diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.c b/drivers/gpu/drm/nouveau/nouveau_bios.c
index 90aef64..729d5fd 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bios.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bios.c
@@ -5049,11 +5049,7 @@
pll_lim->vco1.max_n = record[11];
pll_lim->min_p = record[12];
pll_lim->max_p = record[13];
- /* where did this go to?? */
- if ((entry[0] & 0xf0) == 0x80)
- pll_lim->refclk = 27000;
- else
- pll_lim->refclk = 100000;
+ pll_lim->refclk = ROM16(entry[9]) * 1000;
}
/*
@@ -6035,6 +6031,7 @@
case DCB_CONNECTOR_DVI_I:
case DCB_CONNECTOR_DVI_D:
case DCB_CONNECTOR_LVDS:
+ case DCB_CONNECTOR_LVDS_SPWG:
case DCB_CONNECTOR_DP:
case DCB_CONNECTOR_eDP:
case DCB_CONNECTOR_HDMI_0:
diff --git a/drivers/gpu/drm/nouveau/nouveau_bios.h b/drivers/gpu/drm/nouveau/nouveau_bios.h
index 8a54fa7..050c314 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bios.h
+++ b/drivers/gpu/drm/nouveau/nouveau_bios.h
@@ -82,6 +82,7 @@
DCB_CONNECTOR_DVI_I = 0x30,
DCB_CONNECTOR_DVI_D = 0x31,
DCB_CONNECTOR_LVDS = 0x40,
+ DCB_CONNECTOR_LVDS_SPWG = 0x41,
DCB_CONNECTOR_DP = 0x46,
DCB_CONNECTOR_eDP = 0x47,
DCB_CONNECTOR_HDMI_0 = 0x60,
diff --git a/drivers/gpu/drm/nouveau/nouveau_channel.c b/drivers/gpu/drm/nouveau/nouveau_channel.c
index 4cea35c..a7583a8 100644
--- a/drivers/gpu/drm/nouveau/nouveau_channel.c
+++ b/drivers/gpu/drm/nouveau/nouveau_channel.c
@@ -268,9 +268,8 @@
struct drm_device *dev = chan->dev;
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
- struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
- struct nouveau_crypt_engine *pcrypt = &dev_priv->engine.crypt;
unsigned long flags;
+ int i;
/* decrement the refcount, and we're done if there's still refs */
if (likely(!atomic_dec_and_test(&chan->users))) {
@@ -294,19 +293,12 @@
/* boot it off the hardware */
pfifo->reassign(dev, false);
- /* We want to give pgraph a chance to idle and get rid of all
- * potential errors. We need to do this without the context
- * switch lock held, otherwise the irq handler is unable to
- * process them.
- */
- if (pgraph->channel(dev) == chan)
- nouveau_wait_for_idle(dev);
-
/* destroy the engine specific contexts */
pfifo->destroy_context(chan);
- pgraph->destroy_context(chan);
- if (pcrypt->destroy_context)
- pcrypt->destroy_context(chan);
+ for (i = 0; i < NVOBJ_ENGINE_NR; i++) {
+ if (chan->engctx[i])
+ dev_priv->eng[i]->context_del(chan, i);
+ }
pfifo->reassign(dev, true);
@@ -414,7 +406,7 @@
struct nouveau_channel *chan;
int ret;
- if (dev_priv->engine.graph.accel_blocked)
+ if (!dev_priv->eng[NVOBJ_ENGINE_GR])
return -ENODEV;
if (init->fb_ctxdma_handle == ~0 || init->tt_ctxdma_handle == ~0)
diff --git a/drivers/gpu/drm/nouveau/nouveau_connector.c b/drivers/gpu/drm/nouveau/nouveau_connector.c
index 7ae1511..1595d0b 100644
--- a/drivers/gpu/drm/nouveau/nouveau_connector.c
+++ b/drivers/gpu/drm/nouveau/nouveau_connector.c
@@ -442,7 +442,7 @@
}
/* LVDS always needs gpu scaling */
- if (nv_connector->dcb->type == DCB_CONNECTOR_LVDS &&
+ if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS &&
value == DRM_MODE_SCALE_NONE)
return -EINVAL;
@@ -650,6 +650,7 @@
ret = get_slave_funcs(encoder)->get_modes(encoder, connector);
if (nv_connector->dcb->type == DCB_CONNECTOR_LVDS ||
+ nv_connector->dcb->type == DCB_CONNECTOR_LVDS_SPWG ||
nv_connector->dcb->type == DCB_CONNECTOR_eDP)
ret += nouveau_connector_scaler_modes_add(connector);
@@ -810,6 +811,7 @@
type = DRM_MODE_CONNECTOR_HDMIA;
break;
case DCB_CONNECTOR_LVDS:
+ case DCB_CONNECTOR_LVDS_SPWG:
type = DRM_MODE_CONNECTOR_LVDS;
funcs = &nouveau_connector_funcs_lvds;
break;
@@ -838,7 +840,7 @@
drm_connector_helper_add(connector, &nouveau_connector_helper_funcs);
/* Check if we need dithering enabled */
- if (dcb->type == DCB_CONNECTOR_LVDS) {
+ if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS) {
bool dummy, is_24bit = false;
ret = nouveau_bios_parse_lvds_table(dev, 0, &dummy, &is_24bit);
@@ -883,7 +885,7 @@
nv_connector->use_dithering ?
DRM_MODE_DITHERING_ON : DRM_MODE_DITHERING_OFF);
- if (dcb->type != DCB_CONNECTOR_LVDS) {
+ if (connector->connector_type != DRM_MODE_CONNECTOR_LVDS) {
if (dev_priv->card_type >= NV_50)
connector->polled = DRM_CONNECTOR_POLL_HPD;
else
diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c
index 764c15d..eb514ea 100644
--- a/drivers/gpu/drm/nouveau/nouveau_display.c
+++ b/drivers/gpu/drm/nouveau/nouveau_display.c
@@ -276,7 +276,7 @@
struct nouveau_fence *fence;
int ret;
- if (dev_priv->engine.graph.accel_blocked)
+ if (!dev_priv->channel)
return -ENODEV;
s = kzalloc(sizeof(*s), GFP_KERNEL);
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.c b/drivers/gpu/drm/nouveau/nouveau_drv.c
index 155ebdc..02c6f37 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drv.c
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.c
@@ -162,11 +162,10 @@
struct drm_device *dev = pci_get_drvdata(pdev);
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
- struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
struct nouveau_channel *chan;
struct drm_crtc *crtc;
- int ret, i;
+ int ret, i, e;
if (pm_state.event == PM_EVENT_PRETHAW)
return 0;
@@ -206,12 +205,17 @@
nouveau_channel_idle(chan);
}
- pgraph->fifo_access(dev, false);
- nouveau_wait_for_idle(dev);
pfifo->reassign(dev, false);
pfifo->disable(dev);
pfifo->unload_context(dev);
- pgraph->unload_context(dev);
+
+ for (e = NVOBJ_ENGINE_NR - 1; e >= 0; e--) {
+ if (dev_priv->eng[e]) {
+ ret = dev_priv->eng[e]->fini(dev, e);
+ if (ret)
+ goto out_abort;
+ }
+ }
ret = pinstmem->suspend(dev);
if (ret) {
@@ -242,9 +246,12 @@
out_abort:
NV_INFO(dev, "Re-enabling acceleration..\n");
+ for (e = e + 1; e < NVOBJ_ENGINE_NR; e++) {
+ if (dev_priv->eng[e])
+ dev_priv->eng[e]->init(dev, e);
+ }
pfifo->enable(dev);
pfifo->reassign(dev, true);
- pgraph->fifo_access(dev, true);
return ret;
}
@@ -299,8 +306,10 @@
engine->mc.init(dev);
engine->timer.init(dev);
engine->fb.init(dev);
- engine->graph.init(dev);
- engine->crypt.init(dev);
+ for (i = 0; i < NVOBJ_ENGINE_NR; i++) {
+ if (dev_priv->eng[i])
+ dev_priv->eng[i]->init(dev, i);
+ }
engine->fifo.init(dev);
nouveau_irq_postinstall(dev);
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h
index a76514a..9c56331 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drv.h
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.h
@@ -150,13 +150,12 @@
#define NVOBJ_ENGINE_SW 0
#define NVOBJ_ENGINE_GR 1
-#define NVOBJ_ENGINE_PPP 2
-#define NVOBJ_ENGINE_COPY 3
-#define NVOBJ_ENGINE_VP 4
-#define NVOBJ_ENGINE_CRYPT 5
-#define NVOBJ_ENGINE_BSP 6
-#define NVOBJ_ENGINE_DISPLAY 0xcafe0001
-#define NVOBJ_ENGINE_INT 0xdeadbeef
+#define NVOBJ_ENGINE_CRYPT 2
+#define NVOBJ_ENGINE_COPY0 3
+#define NVOBJ_ENGINE_COPY1 4
+#define NVOBJ_ENGINE_MPEG 5
+#define NVOBJ_ENGINE_DISPLAY 15
+#define NVOBJ_ENGINE_NR 16
#define NVOBJ_FLAG_DONT_MAP (1 << 0)
#define NVOBJ_FLAG_ZERO_ALLOC (1 << 1)
@@ -245,11 +244,8 @@
struct nouveau_gpuobj *cache;
void *fifo_priv;
- /* PGRAPH context */
- /* XXX may be merge 2 pointers as private data ??? */
- struct nouveau_gpuobj *ramin_grctx;
- struct nouveau_gpuobj *crypt_ctx;
- void *pgraph_ctx;
+ /* Execution engine contexts */
+ void *engctx[NVOBJ_ENGINE_NR];
/* NV50 VM */
struct nouveau_vm *vm;
@@ -298,6 +294,18 @@
} debugfs;
};
+struct nouveau_exec_engine {
+ void (*destroy)(struct drm_device *, int engine);
+ int (*init)(struct drm_device *, int engine);
+ int (*fini)(struct drm_device *, int engine);
+ int (*context_new)(struct nouveau_channel *, int engine);
+ void (*context_del)(struct nouveau_channel *, int engine);
+ int (*object_new)(struct nouveau_channel *, int engine,
+ u32 handle, u16 class);
+ void (*set_tile_region)(struct drm_device *dev, int i);
+ void (*tlb_flush)(struct drm_device *, int engine);
+};
+
struct nouveau_instmem_engine {
void *priv;
@@ -364,30 +372,6 @@
void (*tlb_flush)(struct drm_device *dev);
};
-struct nouveau_pgraph_engine {
- bool accel_blocked;
- bool registered;
- int grctx_size;
- void *priv;
-
- /* NV2x/NV3x context table (0x400780) */
- struct nouveau_gpuobj *ctx_table;
-
- int (*init)(struct drm_device *);
- void (*takedown)(struct drm_device *);
-
- void (*fifo_access)(struct drm_device *, bool);
-
- struct nouveau_channel *(*channel)(struct drm_device *);
- int (*create_context)(struct nouveau_channel *);
- void (*destroy_context)(struct nouveau_channel *);
- int (*load_context)(struct nouveau_channel *);
- int (*unload_context)(struct drm_device *);
- void (*tlb_flush)(struct drm_device *dev);
-
- void (*set_tile_region)(struct drm_device *dev, int i);
-};
-
struct nouveau_display_engine {
void *priv;
int (*early_init)(struct drm_device *);
@@ -426,6 +410,19 @@
int nr_level;
};
+struct nouveau_pm_memtiming {
+ int id;
+ u32 reg_100220;
+ u32 reg_100224;
+ u32 reg_100228;
+ u32 reg_10022c;
+ u32 reg_100230;
+ u32 reg_100234;
+ u32 reg_100238;
+ u32 reg_10023c;
+ u32 reg_100240;
+};
+
#define NOUVEAU_PM_MAX_LEVEL 8
struct nouveau_pm_level {
struct device_attribute dev_attr;
@@ -436,11 +433,13 @@
u32 memory;
u32 shader;
u32 unk05;
+ u32 unk0a;
u8 voltage;
u8 fanspeed;
u16 memscript;
+ struct nouveau_pm_memtiming *timing;
};
struct nouveau_pm_temp_sensor_constants {
@@ -457,17 +456,6 @@
s16 fan_boost;
};
-struct nouveau_pm_memtiming {
- u32 reg_100220;
- u32 reg_100224;
- u32 reg_100228;
- u32 reg_10022c;
- u32 reg_100230;
- u32 reg_100234;
- u32 reg_100238;
- u32 reg_10023c;
-};
-
struct nouveau_pm_memtimings {
bool supported;
struct nouveau_pm_memtiming *timing;
@@ -499,16 +487,6 @@
int (*temp_get)(struct drm_device *);
};
-struct nouveau_crypt_engine {
- bool registered;
-
- int (*init)(struct drm_device *);
- void (*takedown)(struct drm_device *);
- int (*create_context)(struct nouveau_channel *);
- void (*destroy_context)(struct nouveau_channel *);
- void (*tlb_flush)(struct drm_device *dev);
-};
-
struct nouveau_vram_engine {
int (*init)(struct drm_device *);
int (*get)(struct drm_device *, u64, u32 align, u32 size_nc,
@@ -523,12 +501,10 @@
struct nouveau_mc_engine mc;
struct nouveau_timer_engine timer;
struct nouveau_fb_engine fb;
- struct nouveau_pgraph_engine graph;
struct nouveau_fifo_engine fifo;
struct nouveau_display_engine display;
struct nouveau_gpio_engine gpio;
struct nouveau_pm_engine pm;
- struct nouveau_crypt_engine crypt;
struct nouveau_vram_engine vram;
};
@@ -637,6 +613,7 @@
enum nouveau_card_type card_type;
/* exact chipset, derived from NV_PMC_BOOT_0 */
int chipset;
+ int stepping;
int flags;
void __iomem *mmio;
@@ -647,6 +624,7 @@
u32 ramin_base;
bool ramin_available;
struct drm_mm ramin_heap;
+ struct nouveau_exec_engine *eng[NVOBJ_ENGINE_NR];
struct list_head gpuobj_list;
struct list_head classes;
@@ -745,10 +723,6 @@
uint32_t crtc_owner;
uint32_t dac_users[4];
- struct nouveau_suspend_resume {
- uint32_t *ramin_copy;
- } susres;
-
struct backlight_device *backlight;
struct {
@@ -757,8 +731,6 @@
struct nouveau_fbdev *nfbdev;
struct apertures_struct *apertures;
-
- bool powered_down;
};
static inline struct drm_nouveau_private *
@@ -883,17 +855,27 @@
extern void nouveau_channel_idle(struct nouveau_channel *chan);
/* nouveau_object.c */
-#define NVOBJ_CLASS(d,c,e) do { \
+#define NVOBJ_ENGINE_ADD(d, e, p) do { \
+ struct drm_nouveau_private *dev_priv = (d)->dev_private; \
+ dev_priv->eng[NVOBJ_ENGINE_##e] = (p); \
+} while (0)
+
+#define NVOBJ_ENGINE_DEL(d, e) do { \
+ struct drm_nouveau_private *dev_priv = (d)->dev_private; \
+ dev_priv->eng[NVOBJ_ENGINE_##e] = NULL; \
+} while (0)
+
+#define NVOBJ_CLASS(d, c, e) do { \
int ret = nouveau_gpuobj_class_new((d), (c), NVOBJ_ENGINE_##e); \
if (ret) \
return ret; \
-} while(0)
+} while (0)
-#define NVOBJ_MTHD(d,c,m,e) do { \
+#define NVOBJ_MTHD(d, c, m, e) do { \
int ret = nouveau_gpuobj_mthd_new((d), (c), (m), (e)); \
if (ret) \
return ret; \
-} while(0)
+} while (0)
extern int nouveau_gpuobj_early_init(struct drm_device *);
extern int nouveau_gpuobj_init(struct drm_device *);
@@ -903,7 +885,7 @@
extern int nouveau_gpuobj_class_new(struct drm_device *, u32 class, u32 eng);
extern int nouveau_gpuobj_mthd_new(struct drm_device *, u32 class, u32 mthd,
int (*exec)(struct nouveau_channel *,
- u32 class, u32 mthd, u32 data));
+ u32 class, u32 mthd, u32 data));
extern int nouveau_gpuobj_mthd_call(struct nouveau_channel *, u32, u32, u32);
extern int nouveau_gpuobj_mthd_call2(struct drm_device *, int, u32, u32, u32);
extern int nouveau_gpuobj_channel_init(struct nouveau_channel *,
@@ -1137,81 +1119,50 @@
extern int nvc0_fifo_unload_context(struct drm_device *);
/* nv04_graph.c */
-extern int nv04_graph_init(struct drm_device *);
-extern void nv04_graph_takedown(struct drm_device *);
+extern int nv04_graph_create(struct drm_device *);
extern void nv04_graph_fifo_access(struct drm_device *, bool);
-extern struct nouveau_channel *nv04_graph_channel(struct drm_device *);
-extern int nv04_graph_create_context(struct nouveau_channel *);
-extern void nv04_graph_destroy_context(struct nouveau_channel *);
-extern int nv04_graph_load_context(struct nouveau_channel *);
-extern int nv04_graph_unload_context(struct drm_device *);
+extern int nv04_graph_object_new(struct nouveau_channel *, int, u32, u16);
extern int nv04_graph_mthd_page_flip(struct nouveau_channel *chan,
u32 class, u32 mthd, u32 data);
extern struct nouveau_bitfield nv04_graph_nsource[];
/* nv10_graph.c */
-extern int nv10_graph_init(struct drm_device *);
-extern void nv10_graph_takedown(struct drm_device *);
+extern int nv10_graph_create(struct drm_device *);
extern struct nouveau_channel *nv10_graph_channel(struct drm_device *);
-extern int nv10_graph_create_context(struct nouveau_channel *);
-extern void nv10_graph_destroy_context(struct nouveau_channel *);
-extern int nv10_graph_load_context(struct nouveau_channel *);
-extern int nv10_graph_unload_context(struct drm_device *);
-extern void nv10_graph_set_tile_region(struct drm_device *dev, int i);
extern struct nouveau_bitfield nv10_graph_intr[];
extern struct nouveau_bitfield nv10_graph_nstatus[];
/* nv20_graph.c */
-extern int nv20_graph_create_context(struct nouveau_channel *);
-extern void nv20_graph_destroy_context(struct nouveau_channel *);
-extern int nv20_graph_load_context(struct nouveau_channel *);
-extern int nv20_graph_unload_context(struct drm_device *);
-extern int nv20_graph_init(struct drm_device *);
-extern void nv20_graph_takedown(struct drm_device *);
-extern int nv30_graph_init(struct drm_device *);
-extern void nv20_graph_set_tile_region(struct drm_device *dev, int i);
+extern int nv20_graph_create(struct drm_device *);
/* nv40_graph.c */
-extern int nv40_graph_init(struct drm_device *);
-extern void nv40_graph_takedown(struct drm_device *);
-extern struct nouveau_channel *nv40_graph_channel(struct drm_device *);
-extern int nv40_graph_create_context(struct nouveau_channel *);
-extern void nv40_graph_destroy_context(struct nouveau_channel *);
-extern int nv40_graph_load_context(struct nouveau_channel *);
-extern int nv40_graph_unload_context(struct drm_device *);
+extern int nv40_graph_create(struct drm_device *);
extern void nv40_grctx_init(struct nouveau_grctx *);
-extern void nv40_graph_set_tile_region(struct drm_device *dev, int i);
/* nv50_graph.c */
-extern int nv50_graph_init(struct drm_device *);
-extern void nv50_graph_takedown(struct drm_device *);
-extern void nv50_graph_fifo_access(struct drm_device *, bool);
-extern struct nouveau_channel *nv50_graph_channel(struct drm_device *);
-extern int nv50_graph_create_context(struct nouveau_channel *);
-extern void nv50_graph_destroy_context(struct nouveau_channel *);
-extern int nv50_graph_load_context(struct nouveau_channel *);
-extern int nv50_graph_unload_context(struct drm_device *);
+extern int nv50_graph_create(struct drm_device *);
extern int nv50_grctx_init(struct nouveau_grctx *);
-extern void nv50_graph_tlb_flush(struct drm_device *dev);
-extern void nv84_graph_tlb_flush(struct drm_device *dev);
extern struct nouveau_enum nv50_data_error_names[];
+extern int nv50_graph_isr_chid(struct drm_device *dev, u64 inst);
/* nvc0_graph.c */
-extern int nvc0_graph_init(struct drm_device *);
-extern void nvc0_graph_takedown(struct drm_device *);
-extern void nvc0_graph_fifo_access(struct drm_device *, bool);
-extern struct nouveau_channel *nvc0_graph_channel(struct drm_device *);
-extern int nvc0_graph_create_context(struct nouveau_channel *);
-extern void nvc0_graph_destroy_context(struct nouveau_channel *);
-extern int nvc0_graph_load_context(struct nouveau_channel *);
-extern int nvc0_graph_unload_context(struct drm_device *);
+extern int nvc0_graph_create(struct drm_device *);
+extern int nvc0_graph_isr_chid(struct drm_device *dev, u64 inst);
/* nv84_crypt.c */
-extern int nv84_crypt_init(struct drm_device *dev);
-extern void nv84_crypt_fini(struct drm_device *dev);
-extern int nv84_crypt_create_context(struct nouveau_channel *);
-extern void nv84_crypt_destroy_context(struct nouveau_channel *);
-extern void nv84_crypt_tlb_flush(struct drm_device *dev);
+extern int nv84_crypt_create(struct drm_device *);
+
+/* nva3_copy.c */
+extern int nva3_copy_create(struct drm_device *dev);
+
+/* nvc0_copy.c */
+extern int nvc0_copy_create(struct drm_device *dev, int engine);
+
+/* nv40_mpeg.c */
+extern int nv40_mpeg_create(struct drm_device *dev);
+
+/* nv50_mpeg.c */
+extern int nv50_mpeg_create(struct drm_device *dev);
/* nv04_instmem.c */
extern int nv04_instmem_init(struct drm_device *);
@@ -1402,8 +1353,8 @@
/* nv50_calc. */
int nv50_calc_pll(struct drm_device *, struct pll_lims *, int clk,
int *N1, int *M1, int *N2, int *M2, int *P);
-int nv50_calc_pll2(struct drm_device *, struct pll_lims *,
- int clk, int *N, int *fN, int *M, int *P);
+int nva3_calc_pll(struct drm_device *, struct pll_lims *,
+ int clk, int *N, int *fN, int *M, int *P);
#ifndef ioread32_native
#ifdef __BIG_ENDIAN
@@ -1579,6 +1530,13 @@
dev->pdev->subsystem_device == sub_device;
}
+static inline void *
+nv_engine(struct drm_device *dev, int engine)
+{
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+ return (void *)dev_priv->eng[engine];
+}
+
/* returns 1 if device is one of the nv4x using the 0x4497 object class,
* helpful to determine a number of other hardware features
*/
diff --git a/drivers/gpu/drm/nouveau/nouveau_grctx.h b/drivers/gpu/drm/nouveau/nouveau_grctx.h
index 4a8ad13..86c2e37 100644
--- a/drivers/gpu/drm/nouveau/nouveau_grctx.h
+++ b/drivers/gpu/drm/nouveau/nouveau_grctx.h
@@ -87,10 +87,10 @@
cp_out(ctx, CP_BRA | (mod << 18) | ip | flag |
(state ? 0 : CP_BRA_IF_CLEAR));
}
-#define cp_bra(c,f,s,n) _cp_bra((c), 0, CP_FLAG_##f, CP_FLAG_##f##_##s, n)
+#define cp_bra(c, f, s, n) _cp_bra((c), 0, CP_FLAG_##f, CP_FLAG_##f##_##s, n)
#ifdef CP_BRA_MOD
-#define cp_cal(c,f,s,n) _cp_bra((c), 1, CP_FLAG_##f, CP_FLAG_##f##_##s, n)
-#define cp_ret(c,f,s) _cp_bra((c), 2, CP_FLAG_##f, CP_FLAG_##f##_##s, 0)
+#define cp_cal(c, f, s, n) _cp_bra((c), 1, CP_FLAG_##f, CP_FLAG_##f##_##s, n)
+#define cp_ret(c, f, s) _cp_bra((c), 2, CP_FLAG_##f, CP_FLAG_##f##_##s, 0)
#endif
static inline void
@@ -98,14 +98,14 @@
{
cp_out(ctx, CP_WAIT | flag | (state ? CP_WAIT_SET : 0));
}
-#define cp_wait(c,f,s) _cp_wait((c), CP_FLAG_##f, CP_FLAG_##f##_##s)
+#define cp_wait(c, f, s) _cp_wait((c), CP_FLAG_##f, CP_FLAG_##f##_##s)
static inline void
_cp_set(struct nouveau_grctx *ctx, int flag, int state)
{
cp_out(ctx, CP_SET | flag | (state ? CP_SET_1 : 0));
}
-#define cp_set(c,f,s) _cp_set((c), CP_FLAG_##f, CP_FLAG_##f##_##s)
+#define cp_set(c, f, s) _cp_set((c), CP_FLAG_##f, CP_FLAG_##f##_##s)
static inline void
cp_pos(struct nouveau_grctx *ctx, int offset)
diff --git a/drivers/gpu/drm/nouveau/nouveau_mem.c b/drivers/gpu/drm/nouveau/nouveau_mem.c
index c3e953b..2960f58 100644
--- a/drivers/gpu/drm/nouveau/nouveau_mem.c
+++ b/drivers/gpu/drm/nouveau/nouveau_mem.c
@@ -51,8 +51,7 @@
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
- struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
- int i = tile - dev_priv->tile.reg;
+ int i = tile - dev_priv->tile.reg, j;
unsigned long save;
nouveau_fence_unref(&tile->fence);
@@ -70,7 +69,10 @@
nouveau_wait_for_idle(dev);
pfb->set_tile_region(dev, i);
- pgraph->set_tile_region(dev, i);
+ for (j = 0; j < NVOBJ_ENGINE_NR; j++) {
+ if (dev_priv->eng[j] && dev_priv->eng[j]->set_tile_region)
+ dev_priv->eng[j]->set_tile_region(dev, i);
+ }
pfifo->cache_pull(dev, true);
pfifo->reassign(dev, true);
@@ -595,10 +597,10 @@
if (!memtimings->timing)
return;
- /* Get "some number" from the timing reg for NV_40
+ /* Get "some number" from the timing reg for NV_40 and NV_50
* Used in calculations later */
- if(dev_priv->card_type == NV_40) {
- magic_number = (nv_rd32(dev,0x100228) & 0x0f000000) >> 24;
+ if (dev_priv->card_type >= NV_40 && dev_priv->chipset < 0x98) {
+ magic_number = (nv_rd32(dev, 0x100228) & 0x0f000000) >> 24;
}
entry = mem + mem[1];
@@ -641,51 +643,68 @@
/* XXX: I don't trust the -1's and +1's... they must come
* from somewhere! */
timing->reg_100224 = (tUNK_0 + tUNK_19 + 1 + magic_number) << 24 |
- tUNK_18 << 16 |
+ max(tUNK_18, (u8) 1) << 16 |
(tUNK_1 + tUNK_19 + 1 + magic_number) << 8;
- if(dev_priv->chipset == 0xa8) {
+ if (dev_priv->chipset == 0xa8) {
timing->reg_100224 |= (tUNK_2 - 1);
} else {
timing->reg_100224 |= (tUNK_2 + 2 - magic_number);
}
timing->reg_100228 = (tUNK_12 << 16 | tUNK_11 << 8 | tUNK_10);
- if(dev_priv->chipset >= 0xa3 && dev_priv->chipset < 0xaa) {
+ if (dev_priv->chipset >= 0xa3 && dev_priv->chipset < 0xaa)
timing->reg_100228 |= (tUNK_19 - 1) << 24;
- }
+ else
+ timing->reg_100228 |= magic_number << 24;
- if(dev_priv->card_type == NV_40) {
+ if (dev_priv->card_type == NV_40) {
/* NV40: don't know what the rest of the regs are..
* And don't need to know either */
- timing->reg_100228 |= 0x20200000 | magic_number << 24;
- } else if(dev_priv->card_type >= NV_50) {
- /* XXX: reg_10022c */
- timing->reg_10022c = tUNK_2 - 1;
+ timing->reg_100228 |= 0x20200000;
+ } else if (dev_priv->card_type >= NV_50) {
+ if (dev_priv->chipset < 0x98 ||
+ (dev_priv->chipset == 0x98 &&
+ dev_priv->stepping <= 0xa1)) {
+ timing->reg_10022c = (0x14 + tUNK_2) << 24 |
+ 0x16 << 16 |
+ (tUNK_2 - 1) << 8 |
+ (tUNK_2 - 1);
+ } else {
+ /* XXX: reg_10022c for recentish cards */
+ timing->reg_10022c = tUNK_2 - 1;
+ }
timing->reg_100230 = (tUNK_20 << 24 | tUNK_21 << 16 |
tUNK_13 << 8 | tUNK_13);
timing->reg_100234 = (tRAS << 24 | tRC);
- timing->reg_100234 += max(tUNK_10,tUNK_11) << 16;
+ timing->reg_100234 += max(tUNK_10, tUNK_11) << 16;
- if(dev_priv->chipset < 0xa3) {
+ if (dev_priv->chipset < 0x98 ||
+ (dev_priv->chipset == 0x98 &&
+ dev_priv->stepping <= 0xa1)) {
timing->reg_100234 |= (tUNK_2 + 2) << 8;
} else {
/* XXX: +6? */
timing->reg_100234 |= (tUNK_19 + 6) << 8;
}
- /* XXX; reg_100238, reg_10023c
- * reg_100238: 0x00??????
- * reg_10023c: 0x!!??0202 for NV50+ cards (empirical evidence) */
+ /* XXX; reg_100238
+ * reg_100238: 0x00?????? */
timing->reg_10023c = 0x202;
- if(dev_priv->chipset < 0xa3) {
+ if (dev_priv->chipset < 0x98 ||
+ (dev_priv->chipset == 0x98 &&
+ dev_priv->stepping <= 0xa1)) {
timing->reg_10023c |= 0x4000000 | (tUNK_2 - 1) << 16;
} else {
- /* currently unknown
+ /* XXX: reg_10023c
+ * currently unknown
* 10023c seen as 06xxxxxx, 0bxxxxxx or 0fxxxxxx */
}
+
+ /* XXX: reg_100240? */
}
+ timing->id = i;
NV_DEBUG(dev, "Entry %d: 220: %08x %08x %08x %08x\n", i,
timing->reg_100220, timing->reg_100224,
@@ -693,10 +712,11 @@
NV_DEBUG(dev, " 230: %08x %08x %08x %08x\n",
timing->reg_100230, timing->reg_100234,
timing->reg_100238, timing->reg_10023c);
+ NV_DEBUG(dev, " 240: %08x\n", timing->reg_100240);
}
memtimings->nr_timing = entries;
- memtimings->supported = true;
+ memtimings->supported = (dev_priv->chipset <= 0x98);
}
void
diff --git a/drivers/gpu/drm/nouveau/nouveau_object.c b/drivers/gpu/drm/nouveau/nouveau_object.c
index 67a16e0..8f97016 100644
--- a/drivers/gpu/drm/nouveau/nouveau_object.c
+++ b/drivers/gpu/drm/nouveau/nouveau_object.c
@@ -361,20 +361,6 @@
return 0;
}
-
-static uint32_t
-nouveau_gpuobj_class_instmem_size(struct drm_device *dev, int class)
-{
- struct drm_nouveau_private *dev_priv = dev->dev_private;
-
- /*XXX: dodgy hack for now */
- if (dev_priv->card_type >= NV_50)
- return 24;
- if (dev_priv->card_type >= NV_40)
- return 32;
- return 16;
-}
-
/*
DMA objects are used to reference a piece of memory in the
framebuffer, PCI or AGP address space. Each object is 16 bytes big
@@ -606,11 +592,11 @@
set to 0?
*/
static int
-nouveau_gpuobj_sw_new(struct nouveau_channel *chan, int class,
- struct nouveau_gpuobj **gpuobj_ret)
+nouveau_gpuobj_sw_new(struct nouveau_channel *chan, u32 handle, u16 class)
{
struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
struct nouveau_gpuobj *gpuobj;
+ int ret;
gpuobj = kzalloc(sizeof(*gpuobj), GFP_KERNEL);
if (!gpuobj)
@@ -624,8 +610,10 @@
spin_lock(&dev_priv->ramin_lock);
list_add_tail(&gpuobj->list, &dev_priv->gpuobj_list);
spin_unlock(&dev_priv->ramin_lock);
- *gpuobj_ret = gpuobj;
- return 0;
+
+ ret = nouveau_ramht_insert(chan, handle, gpuobj);
+ nouveau_gpuobj_ref(NULL, &gpuobj);
+ return ret;
}
int
@@ -634,101 +622,30 @@
struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
struct drm_device *dev = chan->dev;
struct nouveau_gpuobj_class *oc;
- struct nouveau_gpuobj *gpuobj;
int ret;
NV_DEBUG(dev, "ch%d class=0x%04x\n", chan->id, class);
list_for_each_entry(oc, &dev_priv->classes, head) {
- if (oc->id == class)
- goto found;
+ struct nouveau_exec_engine *eng = dev_priv->eng[oc->engine];
+
+ if (oc->id != class)
+ continue;
+
+ if (oc->engine == NVOBJ_ENGINE_SW)
+ return nouveau_gpuobj_sw_new(chan, handle, class);
+
+ if (!chan->engctx[oc->engine]) {
+ ret = eng->context_new(chan, oc->engine);
+ if (ret)
+ return ret;
+ }
+
+ return eng->object_new(chan, oc->engine, handle, class);
}
NV_ERROR(dev, "illegal object class: 0x%x\n", class);
return -EINVAL;
-
-found:
- switch (oc->engine) {
- case NVOBJ_ENGINE_SW:
- if (dev_priv->card_type < NV_C0) {
- ret = nouveau_gpuobj_sw_new(chan, class, &gpuobj);
- if (ret)
- return ret;
- goto insert;
- }
- break;
- case NVOBJ_ENGINE_GR:
- if ((dev_priv->card_type >= NV_20 && !chan->ramin_grctx) ||
- (dev_priv->card_type < NV_20 && !chan->pgraph_ctx)) {
- struct nouveau_pgraph_engine *pgraph =
- &dev_priv->engine.graph;
-
- ret = pgraph->create_context(chan);
- if (ret)
- return ret;
- }
- break;
- case NVOBJ_ENGINE_CRYPT:
- if (!chan->crypt_ctx) {
- struct nouveau_crypt_engine *pcrypt =
- &dev_priv->engine.crypt;
-
- ret = pcrypt->create_context(chan);
- if (ret)
- return ret;
- }
- break;
- }
-
- /* we're done if this is fermi */
- if (dev_priv->card_type >= NV_C0)
- return 0;
-
- ret = nouveau_gpuobj_new(dev, chan,
- nouveau_gpuobj_class_instmem_size(dev, class),
- 16,
- NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ZERO_FREE,
- &gpuobj);
- if (ret) {
- NV_ERROR(dev, "error creating gpuobj: %d\n", ret);
- return ret;
- }
-
- if (dev_priv->card_type >= NV_50) {
- nv_wo32(gpuobj, 0, class);
- nv_wo32(gpuobj, 20, 0x00010000);
- } else {
- switch (class) {
- case NV_CLASS_NULL:
- nv_wo32(gpuobj, 0, 0x00001030);
- nv_wo32(gpuobj, 4, 0xFFFFFFFF);
- break;
- default:
- if (dev_priv->card_type >= NV_40) {
- nv_wo32(gpuobj, 0, class);
-#ifdef __BIG_ENDIAN
- nv_wo32(gpuobj, 8, 0x01000000);
-#endif
- } else {
-#ifdef __BIG_ENDIAN
- nv_wo32(gpuobj, 0, class | 0x00080000);
-#else
- nv_wo32(gpuobj, 0, class);
-#endif
- }
- }
- }
- dev_priv->engine.instmem.flush(dev);
-
- gpuobj->engine = oc->engine;
- gpuobj->class = oc->id;
-
-insert:
- ret = nouveau_ramht_insert(chan, handle, gpuobj);
- if (ret)
- NV_ERROR(dev, "error adding gpuobj to RAMHT: %d\n", ret);
- nouveau_gpuobj_ref(NULL, &gpuobj);
- return ret;
}
static int
@@ -746,9 +663,6 @@
size = 0x2000;
base = 0;
- /* PGRAPH context */
- size += dev_priv->engine.graph.grctx_size;
-
if (dev_priv->card_type == NV_50) {
/* Various fixed table thingos */
size += 0x1400; /* mostly unknown stuff */
diff --git a/drivers/gpu/drm/nouveau/nouveau_perf.c b/drivers/gpu/drm/nouveau/nouveau_perf.c
index 670e3cb..922fb6b 100644
--- a/drivers/gpu/drm/nouveau/nouveau_perf.c
+++ b/drivers/gpu/drm/nouveau/nouveau_perf.c
@@ -72,6 +72,68 @@
pm->nr_perflvl = 1;
}
+static struct nouveau_pm_memtiming *
+nouveau_perf_timing(struct drm_device *dev, struct bit_entry *P,
+ u16 memclk, u8 *entry, u8 recordlen, u8 entries)
+{
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+ struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
+ struct nvbios *bios = &dev_priv->vbios;
+ u8 ramcfg;
+ int i;
+
+ /* perf v2 has a separate "timing map" table, we have to match
+ * the target memory clock to a specific entry, *then* use
+ * ramcfg to select the correct subentry
+ */
+ if (P->version == 2) {
+ u8 *tmap = ROMPTR(bios, P->data[4]);
+ if (!tmap) {
+ NV_DEBUG(dev, "no timing map pointer\n");
+ return NULL;
+ }
+
+ if (tmap[0] != 0x10) {
+ NV_WARN(dev, "timing map 0x%02x unknown\n", tmap[0]);
+ return NULL;
+ }
+
+ entry = tmap + tmap[1];
+ recordlen = tmap[2] + (tmap[4] * tmap[3]);
+ for (i = 0; i < tmap[5]; i++, entry += recordlen) {
+ if (memclk >= ROM16(entry[0]) &&
+ memclk <= ROM16(entry[2]))
+ break;
+ }
+
+ if (i == tmap[5]) {
+ NV_WARN(dev, "no match in timing map table\n");
+ return NULL;
+ }
+
+ entry += tmap[2];
+ recordlen = tmap[3];
+ entries = tmap[4];
+ }
+
+ ramcfg = (nv_rd32(dev, NV_PEXTDEV_BOOT_0) & 0x0000003c) >> 2;
+ if (bios->ram_restrict_tbl_ptr)
+ ramcfg = bios->data[bios->ram_restrict_tbl_ptr + ramcfg];
+
+ if (ramcfg >= entries) {
+ NV_WARN(dev, "ramcfg strap out of bounds!\n");
+ return NULL;
+ }
+
+ entry += ramcfg * recordlen;
+ if (entry[1] >= pm->memtimings.nr_timing) {
+ NV_WARN(dev, "timingset %d does not exist\n", entry[1]);
+ return NULL;
+ }
+
+ return &pm->memtimings.timing[entry[1]];
+}
+
void
nouveau_perf_init(struct drm_device *dev)
{
@@ -124,6 +186,8 @@
for (i = 0; i < entries; i++) {
struct nouveau_pm_level *perflvl = &pm->perflvl[pm->nr_perflvl];
+ perflvl->timing = NULL;
+
if (entry[0] == 0xff) {
entry += recordlen;
continue;
@@ -174,9 +238,21 @@
#define subent(n) entry[perf[2] + ((n) * perf[3])]
perflvl->fanspeed = 0; /*XXX*/
perflvl->voltage = entry[2];
- perflvl->core = (ROM16(subent(0)) & 0xfff) * 1000;
- perflvl->shader = (ROM16(subent(1)) & 0xfff) * 1000;
- perflvl->memory = (ROM16(subent(2)) & 0xfff) * 1000;
+ if (dev_priv->card_type == NV_50) {
+ perflvl->core = ROM16(subent(0)) & 0xfff;
+ perflvl->shader = ROM16(subent(1)) & 0xfff;
+ perflvl->memory = ROM16(subent(2)) & 0xfff;
+ } else {
+ perflvl->shader = ROM16(subent(3)) & 0xfff;
+ perflvl->core = perflvl->shader / 2;
+ perflvl->unk0a = ROM16(subent(4)) & 0xfff;
+ perflvl->memory = ROM16(subent(5)) & 0xfff;
+ }
+
+ perflvl->core *= 1000;
+ perflvl->shader *= 1000;
+ perflvl->memory *= 1000;
+ perflvl->unk0a *= 1000;
break;
}
@@ -190,6 +266,16 @@
}
}
+ /* get the corresponding memory timings */
+ if (version > 0x15) {
+ /* last 3 args are for < 0x40, ignored for >= 0x40 */
+ perflvl->timing =
+ nouveau_perf_timing(dev, &P,
+ perflvl->memory / 1000,
+ entry + perf[3],
+ perf[5], perf[4]);
+ }
+
snprintf(perflvl->name, sizeof(perflvl->name),
"performance_level_%d", i);
perflvl->id = i;
diff --git a/drivers/gpu/drm/nouveau/nouveau_pm.c b/drivers/gpu/drm/nouveau/nouveau_pm.c
index 4399e2f..da8d994 100644
--- a/drivers/gpu/drm/nouveau/nouveau_pm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_pm.c
@@ -156,7 +156,7 @@
static void
nouveau_pm_perflvl_info(struct nouveau_pm_level *perflvl, char *ptr, int len)
{
- char c[16], s[16], v[16], f[16];
+ char c[16], s[16], v[16], f[16], t[16];
c[0] = '\0';
if (perflvl->core)
@@ -174,8 +174,12 @@
if (perflvl->fanspeed)
snprintf(f, sizeof(f), " fanspeed %d%%", perflvl->fanspeed);
- snprintf(ptr, len, "memory %dMHz%s%s%s%s\n", perflvl->memory / 1000,
- c, s, v, f);
+ t[0] = '\0';
+ if (perflvl->timing)
+ snprintf(t, sizeof(t), " timing %d", perflvl->timing->id);
+
+ snprintf(ptr, len, "memory %dMHz%s%s%s%s%s\n", perflvl->memory / 1000,
+ c, s, v, f, t);
}
static ssize_t
@@ -449,7 +453,7 @@
#endif
}
-#ifdef CONFIG_ACPI
+#if defined(CONFIG_ACPI) && defined(CONFIG_POWER_SUPPLY)
static int
nouveau_pm_acpi_event(struct notifier_block *nb, unsigned long val, void *data)
{
@@ -476,10 +480,10 @@
char info[256];
int ret, i;
+ nouveau_mem_timing_init(dev);
nouveau_volt_init(dev);
nouveau_perf_init(dev);
nouveau_temp_init(dev);
- nouveau_mem_timing_init(dev);
NV_INFO(dev, "%d available performance level(s)\n", pm->nr_perflvl);
for (i = 0; i < pm->nr_perflvl; i++) {
@@ -490,6 +494,7 @@
/* determine current ("boot") performance level */
ret = nouveau_pm_perflvl_get(dev, &pm->boot);
if (ret == 0) {
+ strncpy(pm->boot.name, "boot", 4);
pm->cur = &pm->boot;
nouveau_pm_perflvl_info(&pm->boot, info, sizeof(info));
@@ -507,7 +512,7 @@
nouveau_sysfs_init(dev);
nouveau_hwmon_init(dev);
-#ifdef CONFIG_ACPI
+#if defined(CONFIG_ACPI) && defined(CONFIG_POWER_SUPPLY)
pm->acpi_nb.notifier_call = nouveau_pm_acpi_event;
register_acpi_notifier(&pm->acpi_nb);
#endif
@@ -524,12 +529,12 @@
if (pm->cur != &pm->boot)
nouveau_pm_perflvl_set(dev, &pm->boot);
- nouveau_mem_timing_fini(dev);
nouveau_temp_fini(dev);
nouveau_perf_fini(dev);
nouveau_volt_fini(dev);
+ nouveau_mem_timing_fini(dev);
-#ifdef CONFIG_ACPI
+#if defined(CONFIG_ACPI) && defined(CONFIG_POWER_SUPPLY)
unregister_acpi_notifier(&pm->acpi_nb);
#endif
nouveau_hwmon_fini(dev);
diff --git a/drivers/gpu/drm/nouveau/nouveau_reg.h b/drivers/gpu/drm/nouveau/nouveau_reg.h
index 04e8fb7..f18cdfc 100644
--- a/drivers/gpu/drm/nouveau/nouveau_reg.h
+++ b/drivers/gpu/drm/nouveau/nouveau_reg.h
@@ -639,9 +639,9 @@
# define NV50_PCONNECTOR_I2C_PORT_4 0x0000e240
# define NV50_PCONNECTOR_I2C_PORT_5 0x0000e258
-#define NV50_AUXCH_DATA_OUT(i,n) ((n) * 4 + (i) * 0x50 + 0x0000e4c0)
+#define NV50_AUXCH_DATA_OUT(i, n) ((n) * 4 + (i) * 0x50 + 0x0000e4c0)
#define NV50_AUXCH_DATA_OUT__SIZE 4
-#define NV50_AUXCH_DATA_IN(i,n) ((n) * 4 + (i) * 0x50 + 0x0000e4d0)
+#define NV50_AUXCH_DATA_IN(i, n) ((n) * 4 + (i) * 0x50 + 0x0000e4d0)
#define NV50_AUXCH_DATA_IN__SIZE 4
#define NV50_AUXCH_ADDR(i) ((i) * 0x50 + 0x0000e4e0)
#define NV50_AUXCH_CTRL(i) ((i) * 0x50 + 0x0000e4e4)
@@ -829,7 +829,7 @@
#define NV50_PDISPLAY_SOR_BACKLIGHT 0x0061c084
#define NV50_PDISPLAY_SOR_BACKLIGHT_ENABLE 0x80000000
#define NV50_PDISPLAY_SOR_BACKLIGHT_LEVEL 0x00000fff
-#define NV50_SOR_DP_CTRL(i,l) (0x0061c10c + (i) * 0x800 + (l) * 0x80)
+#define NV50_SOR_DP_CTRL(i, l) (0x0061c10c + (i) * 0x800 + (l) * 0x80)
#define NV50_SOR_DP_CTRL_ENABLED 0x00000001
#define NV50_SOR_DP_CTRL_ENHANCED_FRAME_ENABLED 0x00004000
#define NV50_SOR_DP_CTRL_LANE_MASK 0x001f0000
@@ -841,10 +841,10 @@
#define NV50_SOR_DP_CTRL_TRAINING_PATTERN_DISABLED 0x00000000
#define NV50_SOR_DP_CTRL_TRAINING_PATTERN_1 0x01000000
#define NV50_SOR_DP_CTRL_TRAINING_PATTERN_2 0x02000000
-#define NV50_SOR_DP_UNK118(i,l) (0x0061c118 + (i) * 0x800 + (l) * 0x80)
-#define NV50_SOR_DP_UNK120(i,l) (0x0061c120 + (i) * 0x800 + (l) * 0x80)
-#define NV50_SOR_DP_UNK128(i,l) (0x0061c128 + (i) * 0x800 + (l) * 0x80)
-#define NV50_SOR_DP_UNK130(i,l) (0x0061c130 + (i) * 0x800 + (l) * 0x80)
+#define NV50_SOR_DP_UNK118(i, l) (0x0061c118 + (i) * 0x800 + (l) * 0x80)
+#define NV50_SOR_DP_UNK120(i, l) (0x0061c120 + (i) * 0x800 + (l) * 0x80)
+#define NV50_SOR_DP_UNK128(i, l) (0x0061c128 + (i) * 0x800 + (l) * 0x80)
+#define NV50_SOR_DP_UNK130(i, l) (0x0061c130 + (i) * 0x800 + (l) * 0x80)
#define NV50_PDISPLAY_USER(i) ((i) * 0x1000 + 0x00640000)
#define NV50_PDISPLAY_USER_PUT(i) ((i) * 0x1000 + 0x00640000)
diff --git a/drivers/gpu/drm/nouveau/nouveau_state.c b/drivers/gpu/drm/nouveau/nouveau_state.c
index 915fbce..38ea662 100644
--- a/drivers/gpu/drm/nouveau/nouveau_state.c
+++ b/drivers/gpu/drm/nouveau/nouveau_state.c
@@ -65,14 +65,6 @@
engine->timer.takedown = nv04_timer_takedown;
engine->fb.init = nv04_fb_init;
engine->fb.takedown = nv04_fb_takedown;
- engine->graph.init = nv04_graph_init;
- engine->graph.takedown = nv04_graph_takedown;
- engine->graph.fifo_access = nv04_graph_fifo_access;
- engine->graph.channel = nv04_graph_channel;
- engine->graph.create_context = nv04_graph_create_context;
- engine->graph.destroy_context = nv04_graph_destroy_context;
- engine->graph.load_context = nv04_graph_load_context;
- engine->graph.unload_context = nv04_graph_unload_context;
engine->fifo.channels = 16;
engine->fifo.init = nv04_fifo_init;
engine->fifo.takedown = nv04_fifo_fini;
@@ -98,8 +90,6 @@
engine->pm.clock_get = nv04_pm_clock_get;
engine->pm.clock_pre = nv04_pm_clock_pre;
engine->pm.clock_set = nv04_pm_clock_set;
- engine->crypt.init = nouveau_stub_init;
- engine->crypt.takedown = nouveau_stub_takedown;
engine->vram.init = nouveau_mem_detect;
engine->vram.flags_valid = nouveau_mem_flags_valid;
break;
@@ -123,15 +113,6 @@
engine->fb.init_tile_region = nv10_fb_init_tile_region;
engine->fb.set_tile_region = nv10_fb_set_tile_region;
engine->fb.free_tile_region = nv10_fb_free_tile_region;
- engine->graph.init = nv10_graph_init;
- engine->graph.takedown = nv10_graph_takedown;
- engine->graph.channel = nv10_graph_channel;
- engine->graph.create_context = nv10_graph_create_context;
- engine->graph.destroy_context = nv10_graph_destroy_context;
- engine->graph.fifo_access = nv04_graph_fifo_access;
- engine->graph.load_context = nv10_graph_load_context;
- engine->graph.unload_context = nv10_graph_unload_context;
- engine->graph.set_tile_region = nv10_graph_set_tile_region;
engine->fifo.channels = 32;
engine->fifo.init = nv10_fifo_init;
engine->fifo.takedown = nv04_fifo_fini;
@@ -157,8 +138,6 @@
engine->pm.clock_get = nv04_pm_clock_get;
engine->pm.clock_pre = nv04_pm_clock_pre;
engine->pm.clock_set = nv04_pm_clock_set;
- engine->crypt.init = nouveau_stub_init;
- engine->crypt.takedown = nouveau_stub_takedown;
engine->vram.init = nouveau_mem_detect;
engine->vram.flags_valid = nouveau_mem_flags_valid;
break;
@@ -182,15 +161,6 @@
engine->fb.init_tile_region = nv10_fb_init_tile_region;
engine->fb.set_tile_region = nv10_fb_set_tile_region;
engine->fb.free_tile_region = nv10_fb_free_tile_region;
- engine->graph.init = nv20_graph_init;
- engine->graph.takedown = nv20_graph_takedown;
- engine->graph.channel = nv10_graph_channel;
- engine->graph.create_context = nv20_graph_create_context;
- engine->graph.destroy_context = nv20_graph_destroy_context;
- engine->graph.fifo_access = nv04_graph_fifo_access;
- engine->graph.load_context = nv20_graph_load_context;
- engine->graph.unload_context = nv20_graph_unload_context;
- engine->graph.set_tile_region = nv20_graph_set_tile_region;
engine->fifo.channels = 32;
engine->fifo.init = nv10_fifo_init;
engine->fifo.takedown = nv04_fifo_fini;
@@ -216,8 +186,6 @@
engine->pm.clock_get = nv04_pm_clock_get;
engine->pm.clock_pre = nv04_pm_clock_pre;
engine->pm.clock_set = nv04_pm_clock_set;
- engine->crypt.init = nouveau_stub_init;
- engine->crypt.takedown = nouveau_stub_takedown;
engine->vram.init = nouveau_mem_detect;
engine->vram.flags_valid = nouveau_mem_flags_valid;
break;
@@ -241,15 +209,6 @@
engine->fb.init_tile_region = nv30_fb_init_tile_region;
engine->fb.set_tile_region = nv10_fb_set_tile_region;
engine->fb.free_tile_region = nv30_fb_free_tile_region;
- engine->graph.init = nv30_graph_init;
- engine->graph.takedown = nv20_graph_takedown;
- engine->graph.fifo_access = nv04_graph_fifo_access;
- engine->graph.channel = nv10_graph_channel;
- engine->graph.create_context = nv20_graph_create_context;
- engine->graph.destroy_context = nv20_graph_destroy_context;
- engine->graph.load_context = nv20_graph_load_context;
- engine->graph.unload_context = nv20_graph_unload_context;
- engine->graph.set_tile_region = nv20_graph_set_tile_region;
engine->fifo.channels = 32;
engine->fifo.init = nv10_fifo_init;
engine->fifo.takedown = nv04_fifo_fini;
@@ -277,8 +236,6 @@
engine->pm.clock_set = nv04_pm_clock_set;
engine->pm.voltage_get = nouveau_voltage_gpio_get;
engine->pm.voltage_set = nouveau_voltage_gpio_set;
- engine->crypt.init = nouveau_stub_init;
- engine->crypt.takedown = nouveau_stub_takedown;
engine->vram.init = nouveau_mem_detect;
engine->vram.flags_valid = nouveau_mem_flags_valid;
break;
@@ -303,15 +260,6 @@
engine->fb.init_tile_region = nv30_fb_init_tile_region;
engine->fb.set_tile_region = nv40_fb_set_tile_region;
engine->fb.free_tile_region = nv30_fb_free_tile_region;
- engine->graph.init = nv40_graph_init;
- engine->graph.takedown = nv40_graph_takedown;
- engine->graph.fifo_access = nv04_graph_fifo_access;
- engine->graph.channel = nv40_graph_channel;
- engine->graph.create_context = nv40_graph_create_context;
- engine->graph.destroy_context = nv40_graph_destroy_context;
- engine->graph.load_context = nv40_graph_load_context;
- engine->graph.unload_context = nv40_graph_unload_context;
- engine->graph.set_tile_region = nv40_graph_set_tile_region;
engine->fifo.channels = 32;
engine->fifo.init = nv40_fifo_init;
engine->fifo.takedown = nv04_fifo_fini;
@@ -340,8 +288,6 @@
engine->pm.voltage_get = nouveau_voltage_gpio_get;
engine->pm.voltage_set = nouveau_voltage_gpio_set;
engine->pm.temp_get = nv40_temp_get;
- engine->crypt.init = nouveau_stub_init;
- engine->crypt.takedown = nouveau_stub_takedown;
engine->vram.init = nouveau_mem_detect;
engine->vram.flags_valid = nouveau_mem_flags_valid;
break;
@@ -368,19 +314,6 @@
engine->timer.takedown = nv04_timer_takedown;
engine->fb.init = nv50_fb_init;
engine->fb.takedown = nv50_fb_takedown;
- engine->graph.init = nv50_graph_init;
- engine->graph.takedown = nv50_graph_takedown;
- engine->graph.fifo_access = nv50_graph_fifo_access;
- engine->graph.channel = nv50_graph_channel;
- engine->graph.create_context = nv50_graph_create_context;
- engine->graph.destroy_context = nv50_graph_destroy_context;
- engine->graph.load_context = nv50_graph_load_context;
- engine->graph.unload_context = nv50_graph_unload_context;
- if (dev_priv->chipset == 0x50 ||
- dev_priv->chipset == 0xac)
- engine->graph.tlb_flush = nv50_graph_tlb_flush;
- else
- engine->graph.tlb_flush = nv84_graph_tlb_flush;
engine->fifo.channels = 128;
engine->fifo.init = nv50_fifo_init;
engine->fifo.takedown = nv50_fifo_takedown;
@@ -432,24 +365,6 @@
engine->pm.temp_get = nv84_temp_get;
else
engine->pm.temp_get = nv40_temp_get;
- switch (dev_priv->chipset) {
- case 0x84:
- case 0x86:
- case 0x92:
- case 0x94:
- case 0x96:
- case 0xa0:
- engine->crypt.init = nv84_crypt_init;
- engine->crypt.takedown = nv84_crypt_fini;
- engine->crypt.create_context = nv84_crypt_create_context;
- engine->crypt.destroy_context = nv84_crypt_destroy_context;
- engine->crypt.tlb_flush = nv84_crypt_tlb_flush;
- break;
- default:
- engine->crypt.init = nouveau_stub_init;
- engine->crypt.takedown = nouveau_stub_takedown;
- break;
- }
engine->vram.init = nv50_vram_init;
engine->vram.get = nv50_vram_new;
engine->vram.put = nv50_vram_del;
@@ -472,14 +387,6 @@
engine->timer.takedown = nv04_timer_takedown;
engine->fb.init = nvc0_fb_init;
engine->fb.takedown = nvc0_fb_takedown;
- engine->graph.init = nvc0_graph_init;
- engine->graph.takedown = nvc0_graph_takedown;
- engine->graph.fifo_access = nvc0_graph_fifo_access;
- engine->graph.channel = nvc0_graph_channel;
- engine->graph.create_context = nvc0_graph_create_context;
- engine->graph.destroy_context = nvc0_graph_destroy_context;
- engine->graph.load_context = nvc0_graph_load_context;
- engine->graph.unload_context = nvc0_graph_unload_context;
engine->fifo.channels = 128;
engine->fifo.init = nvc0_fifo_init;
engine->fifo.takedown = nvc0_fifo_takedown;
@@ -503,8 +410,6 @@
engine->gpio.irq_register = nv50_gpio_irq_register;
engine->gpio.irq_unregister = nv50_gpio_irq_unregister;
engine->gpio.irq_enable = nv50_gpio_irq_enable;
- engine->crypt.init = nouveau_stub_init;
- engine->crypt.takedown = nouveau_stub_takedown;
engine->vram.init = nvc0_vram_init;
engine->vram.get = nvc0_vram_new;
engine->vram.put = nv50_vram_del;
@@ -593,7 +498,7 @@
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_engine *engine;
- int ret;
+ int ret, e = 0;
vga_client_register(dev->pdev, dev, NULL, nouveau_vga_set_decode);
vga_switcheroo_register_client(dev->pdev, nouveau_switcheroo_set_state,
@@ -658,23 +563,80 @@
if (ret)
goto out_timer;
- if (nouveau_noaccel)
- engine->graph.accel_blocked = true;
- else {
- /* PGRAPH */
- ret = engine->graph.init(dev);
- if (ret)
- goto out_fb;
+ switch (dev_priv->card_type) {
+ case NV_04:
+ nv04_graph_create(dev);
+ break;
+ case NV_10:
+ nv10_graph_create(dev);
+ break;
+ case NV_20:
+ case NV_30:
+ nv20_graph_create(dev);
+ break;
+ case NV_40:
+ nv40_graph_create(dev);
+ break;
+ case NV_50:
+ nv50_graph_create(dev);
+ break;
+ case NV_C0:
+ nvc0_graph_create(dev);
+ break;
+ default:
+ break;
+ }
- /* PCRYPT */
- ret = engine->crypt.init(dev);
- if (ret)
- goto out_graph;
+ switch (dev_priv->chipset) {
+ case 0x84:
+ case 0x86:
+ case 0x92:
+ case 0x94:
+ case 0x96:
+ case 0xa0:
+ nv84_crypt_create(dev);
+ break;
+ }
+
+ switch (dev_priv->card_type) {
+ case NV_50:
+ switch (dev_priv->chipset) {
+ case 0xa3:
+ case 0xa5:
+ case 0xa8:
+ case 0xaf:
+ nva3_copy_create(dev);
+ break;
+ }
+ break;
+ case NV_C0:
+ nvc0_copy_create(dev, 0);
+ nvc0_copy_create(dev, 1);
+ break;
+ default:
+ break;
+ }
+
+ if (dev_priv->card_type == NV_40)
+ nv40_mpeg_create(dev);
+ else
+ if (dev_priv->card_type == NV_50 &&
+ (dev_priv->chipset < 0x98 || dev_priv->chipset == 0xa0))
+ nv50_mpeg_create(dev);
+
+ if (!nouveau_noaccel) {
+ for (e = 0; e < NVOBJ_ENGINE_NR; e++) {
+ if (dev_priv->eng[e]) {
+ ret = dev_priv->eng[e]->init(dev, e);
+ if (ret)
+ goto out_engine;
+ }
+ }
/* PFIFO */
ret = engine->fifo.init(dev);
if (ret)
- goto out_crypt;
+ goto out_engine;
}
ret = engine->display.create(dev);
@@ -691,7 +653,7 @@
/* what about PVIDEO/PCRTC/PRAMDAC etc? */
- if (!engine->graph.accel_blocked) {
+ if (dev_priv->eng[NVOBJ_ENGINE_GR]) {
ret = nouveau_fence_init(dev);
if (ret)
goto out_irq;
@@ -715,13 +677,16 @@
out_fifo:
if (!nouveau_noaccel)
engine->fifo.takedown(dev);
-out_crypt:
- if (!nouveau_noaccel)
- engine->crypt.takedown(dev);
-out_graph:
- if (!nouveau_noaccel)
- engine->graph.takedown(dev);
-out_fb:
+out_engine:
+ if (!nouveau_noaccel) {
+ for (e = e - 1; e >= 0; e--) {
+ if (!dev_priv->eng[e])
+ continue;
+ dev_priv->eng[e]->fini(dev, e);
+ dev_priv->eng[e]->destroy(dev,e );
+ }
+ }
+
engine->fb.takedown(dev);
out_timer:
engine->timer.takedown(dev);
@@ -751,16 +716,21 @@
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_engine *engine = &dev_priv->engine;
+ int e;
- if (!engine->graph.accel_blocked) {
+ if (dev_priv->channel) {
nouveau_fence_fini(dev);
nouveau_channel_put_unlocked(&dev_priv->channel);
}
if (!nouveau_noaccel) {
engine->fifo.takedown(dev);
- engine->crypt.takedown(dev);
- engine->graph.takedown(dev);
+ for (e = NVOBJ_ENGINE_NR - 1; e >= 0; e--) {
+ if (dev_priv->eng[e]) {
+ dev_priv->eng[e]->fini(dev, e);
+ dev_priv->eng[e]->destroy(dev,e );
+ }
+ }
}
engine->fb.takedown(dev);
engine->timer.takedown(dev);
@@ -866,7 +836,7 @@
#ifdef CONFIG_X86
primary = dev->pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
#endif
-
+
remove_conflicting_framebuffers(dev_priv->apertures, "nouveaufb", primary);
return 0;
}
@@ -918,11 +888,13 @@
/* Time to determine the card architecture */
reg0 = nv_rd32(dev, NV03_PMC_BOOT_0);
+ dev_priv->stepping = 0; /* XXX: add stepping for pre-NV10? */
/* We're dealing with >=NV10 */
if ((reg0 & 0x0f000000) > 0) {
/* Bit 27-20 contain the architecture in hex */
dev_priv->chipset = (reg0 & 0xff00000) >> 20;
+ dev_priv->stepping = (reg0 & 0xff);
/* NV04 or NV05 */
} else if ((reg0 & 0xff00fff0) == 0x20004000) {
if (reg0 & 0x00f00000)
diff --git a/drivers/gpu/drm/nouveau/nouveau_vm.h b/drivers/gpu/drm/nouveau/nouveau_vm.h
index 2e06b55..c48a9fc 100644
--- a/drivers/gpu/drm/nouveau/nouveau_vm.h
+++ b/drivers/gpu/drm/nouveau/nouveau_vm.h
@@ -53,8 +53,7 @@
int refcount;
struct list_head pgd_list;
- atomic_t pgraph_refs;
- atomic_t pcrypt_refs;
+ atomic_t engref[16];
struct nouveau_vm_pgt *pgt;
u32 fpde;
diff --git a/drivers/gpu/drm/nouveau/nouveau_volt.c b/drivers/gpu/drm/nouveau/nouveau_volt.c
index 04fdc00..75e87274 100644
--- a/drivers/gpu/drm/nouveau/nouveau_volt.c
+++ b/drivers/gpu/drm/nouveau/nouveau_volt.c
@@ -159,8 +159,16 @@
headerlen = volt[1];
recordlen = volt[2];
entries = volt[3];
- vidshift = hweight8(volt[5]);
vidmask = volt[4];
+ /* no longer certain what volt[5] is, if it's related to
+ * the vid shift then it's definitely not a function of
+ * how many bits are set.
+ *
+ * after looking at a number of nva3+ vbios images, they
+ * all seem likely to have a static shift of 2.. lets
+ * go with that for now until proven otherwise.
+ */
+ vidshift = 2;
break;
default:
NV_WARN(dev, "voltage table 0x%02x unknown\n", volt[0]);
diff --git a/drivers/gpu/drm/nouveau/nv04_crtc.c b/drivers/gpu/drm/nouveau/nv04_crtc.c
index 748b9d9..3c78bc8 100644
--- a/drivers/gpu/drm/nouveau/nv04_crtc.c
+++ b/drivers/gpu/drm/nouveau/nv04_crtc.c
@@ -790,8 +790,7 @@
if (atomic) {
drm_fb = passed_fb;
fb = nouveau_framebuffer(passed_fb);
- }
- else {
+ } else {
/* If not atomic, we can go ahead and pin, and unpin the
* old fb we were passed.
*/
@@ -944,14 +943,14 @@
struct drm_gem_object *gem;
int ret = 0;
- if (width != 64 || height != 64)
- return -EINVAL;
-
if (!buffer_handle) {
nv_crtc->cursor.hide(nv_crtc, true);
return 0;
}
+ if (width != 64 || height != 64)
+ return -EINVAL;
+
gem = drm_gem_object_lookup(dev, file_priv, buffer_handle);
if (!gem)
return -ENOENT;
diff --git a/drivers/gpu/drm/nouveau/nv04_graph.c b/drivers/gpu/drm/nouveau/nv04_graph.c
index af75015..3626ee7 100644
--- a/drivers/gpu/drm/nouveau/nv04_graph.c
+++ b/drivers/gpu/drm/nouveau/nv04_graph.c
@@ -28,9 +28,11 @@
#include "nouveau_drv.h"
#include "nouveau_hw.h"
#include "nouveau_util.h"
+#include "nouveau_ramht.h"
-static int nv04_graph_register(struct drm_device *dev);
-static void nv04_graph_isr(struct drm_device *dev);
+struct nv04_graph_engine {
+ struct nouveau_exec_engine base;
+};
static uint32_t nv04_graph_ctx_regs[] = {
0x0040053c,
@@ -350,7 +352,7 @@
uint32_t nv04[ARRAY_SIZE(nv04_graph_ctx_regs)];
};
-struct nouveau_channel *
+static struct nouveau_channel *
nv04_graph_channel(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
@@ -365,26 +367,6 @@
return dev_priv->channels.ptr[chid];
}
-static void
-nv04_graph_context_switch(struct drm_device *dev)
-{
- struct drm_nouveau_private *dev_priv = dev->dev_private;
- struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
- struct nouveau_channel *chan = NULL;
- int chid;
-
- nouveau_wait_for_idle(dev);
-
- /* If previous context is valid, we need to save it */
- pgraph->unload_context(dev);
-
- /* Load context for next channel */
- chid = dev_priv->engine.fifo.channel_id(dev);
- chan = dev_priv->channels.ptr[chid];
- if (chan)
- nv04_graph_load_context(chan);
-}
-
static uint32_t *ctx_reg(struct graph_state *ctx, uint32_t reg)
{
int i;
@@ -397,48 +379,11 @@
return NULL;
}
-int nv04_graph_create_context(struct nouveau_channel *chan)
+static int
+nv04_graph_load_context(struct nouveau_channel *chan)
{
- struct graph_state *pgraph_ctx;
- NV_DEBUG(chan->dev, "nv04_graph_context_create %d\n", chan->id);
-
- chan->pgraph_ctx = pgraph_ctx = kzalloc(sizeof(*pgraph_ctx),
- GFP_KERNEL);
- if (pgraph_ctx == NULL)
- return -ENOMEM;
-
- *ctx_reg(pgraph_ctx, NV04_PGRAPH_DEBUG_3) = 0xfad4ff31;
-
- return 0;
-}
-
-void nv04_graph_destroy_context(struct nouveau_channel *chan)
-{
+ struct graph_state *pgraph_ctx = chan->engctx[NVOBJ_ENGINE_GR];
struct drm_device *dev = chan->dev;
- struct drm_nouveau_private *dev_priv = dev->dev_private;
- struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
- struct graph_state *pgraph_ctx = chan->pgraph_ctx;
- unsigned long flags;
-
- spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
- pgraph->fifo_access(dev, false);
-
- /* Unload the context if it's the currently active one */
- if (pgraph->channel(dev) == chan)
- pgraph->unload_context(dev);
-
- /* Free the context resources */
- kfree(pgraph_ctx);
- chan->pgraph_ctx = NULL;
-
- pgraph->fifo_access(dev, true);
- spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
-}
-
-int nv04_graph_load_context(struct nouveau_channel *chan)
-{
- struct drm_device *dev = chan->dev;
- struct graph_state *pgraph_ctx = chan->pgraph_ctx;
uint32_t tmp;
int i;
@@ -456,20 +401,19 @@
return 0;
}
-int
+static int
nv04_graph_unload_context(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
- struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
struct nouveau_channel *chan = NULL;
struct graph_state *ctx;
uint32_t tmp;
int i;
- chan = pgraph->channel(dev);
+ chan = nv04_graph_channel(dev);
if (!chan)
return 0;
- ctx = chan->pgraph_ctx;
+ ctx = chan->engctx[NVOBJ_ENGINE_GR];
for (i = 0; i < ARRAY_SIZE(nv04_graph_ctx_regs); i++)
ctx->nv04[i] = nv_rd32(dev, nv04_graph_ctx_regs[i]);
@@ -481,23 +425,85 @@
return 0;
}
-int nv04_graph_init(struct drm_device *dev)
+static int
+nv04_graph_context_new(struct nouveau_channel *chan, int engine)
+{
+ struct graph_state *pgraph_ctx;
+ NV_DEBUG(chan->dev, "nv04_graph_context_create %d\n", chan->id);
+
+ pgraph_ctx = kzalloc(sizeof(*pgraph_ctx), GFP_KERNEL);
+ if (pgraph_ctx == NULL)
+ return -ENOMEM;
+
+ *ctx_reg(pgraph_ctx, NV04_PGRAPH_DEBUG_3) = 0xfad4ff31;
+
+ chan->engctx[engine] = pgraph_ctx;
+ return 0;
+}
+
+static void
+nv04_graph_context_del(struct nouveau_channel *chan, int engine)
+{
+ struct drm_device *dev = chan->dev;
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+ struct graph_state *pgraph_ctx = chan->engctx[engine];
+ unsigned long flags;
+
+ spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
+ nv04_graph_fifo_access(dev, false);
+
+ /* Unload the context if it's the currently active one */
+ if (nv04_graph_channel(dev) == chan)
+ nv04_graph_unload_context(dev);
+
+ nv04_graph_fifo_access(dev, true);
+ spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
+
+ /* Free the context resources */
+ kfree(pgraph_ctx);
+ chan->engctx[engine] = NULL;
+}
+
+int
+nv04_graph_object_new(struct nouveau_channel *chan, int engine,
+ u32 handle, u16 class)
+{
+ struct drm_device *dev = chan->dev;
+ struct nouveau_gpuobj *obj = NULL;
+ int ret;
+
+ ret = nouveau_gpuobj_new(dev, chan, 16, 16, NVOBJ_FLAG_ZERO_FREE, &obj);
+ if (ret)
+ return ret;
+ obj->engine = 1;
+ obj->class = class;
+
+#ifdef __BIG_ENDIAN
+ nv_wo32(obj, 0x00, 0x00080000 | class);
+#else
+ nv_wo32(obj, 0x00, class);
+#endif
+ nv_wo32(obj, 0x04, 0x00000000);
+ nv_wo32(obj, 0x08, 0x00000000);
+ nv_wo32(obj, 0x0c, 0x00000000);
+
+ ret = nouveau_ramht_insert(chan, handle, obj);
+ nouveau_gpuobj_ref(NULL, &obj);
+ return ret;
+}
+
+static int
+nv04_graph_init(struct drm_device *dev, int engine)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
uint32_t tmp;
- int ret;
nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) &
~NV_PMC_ENABLE_PGRAPH);
nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
NV_PMC_ENABLE_PGRAPH);
- ret = nv04_graph_register(dev);
- if (ret)
- return ret;
-
/* Enable PGRAPH interrupts */
- nouveau_irq_register(dev, 12, nv04_graph_isr);
nv_wr32(dev, NV03_PGRAPH_INTR, 0xFFFFFFFF);
nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
@@ -507,7 +513,7 @@
nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x001FFFFF);*/
nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x1231c000);
/*1231C000 blob, 001 haiku*/
- //*V_WRITE(NV04_PGRAPH_DEBUG_1, 0xf2d91100);*/
+ /*V_WRITE(NV04_PGRAPH_DEBUG_1, 0xf2d91100);*/
nv_wr32(dev, NV04_PGRAPH_DEBUG_1, 0x72111100);
/*0x72111100 blob , 01 haiku*/
/*nv_wr32(dev, NV04_PGRAPH_DEBUG_2, 0x11d5f870);*/
@@ -531,10 +537,12 @@
return 0;
}
-void nv04_graph_takedown(struct drm_device *dev)
+static int
+nv04_graph_fini(struct drm_device *dev, int engine)
{
+ nv04_graph_unload_context(dev);
nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0x00000000);
- nouveau_irq_unregister(dev, 12);
+ return 0;
}
void
@@ -969,13 +977,138 @@
return 1;
}
-static int
-nv04_graph_register(struct drm_device *dev)
+static struct nouveau_bitfield nv04_graph_intr[] = {
+ { NV_PGRAPH_INTR_NOTIFY, "NOTIFY" },
+ {}
+};
+
+static struct nouveau_bitfield nv04_graph_nstatus[] = {
+ { NV04_PGRAPH_NSTATUS_STATE_IN_USE, "STATE_IN_USE" },
+ { NV04_PGRAPH_NSTATUS_INVALID_STATE, "INVALID_STATE" },
+ { NV04_PGRAPH_NSTATUS_BAD_ARGUMENT, "BAD_ARGUMENT" },
+ { NV04_PGRAPH_NSTATUS_PROTECTION_FAULT, "PROTECTION_FAULT" },
+ {}
+};
+
+struct nouveau_bitfield nv04_graph_nsource[] = {
+ { NV03_PGRAPH_NSOURCE_NOTIFICATION, "NOTIFICATION" },
+ { NV03_PGRAPH_NSOURCE_DATA_ERROR, "DATA_ERROR" },
+ { NV03_PGRAPH_NSOURCE_PROTECTION_ERROR, "PROTECTION_ERROR" },
+ { NV03_PGRAPH_NSOURCE_RANGE_EXCEPTION, "RANGE_EXCEPTION" },
+ { NV03_PGRAPH_NSOURCE_LIMIT_COLOR, "LIMIT_COLOR" },
+ { NV03_PGRAPH_NSOURCE_LIMIT_ZETA, "LIMIT_ZETA" },
+ { NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD, "ILLEGAL_MTHD" },
+ { NV03_PGRAPH_NSOURCE_DMA_R_PROTECTION, "DMA_R_PROTECTION" },
+ { NV03_PGRAPH_NSOURCE_DMA_W_PROTECTION, "DMA_W_PROTECTION" },
+ { NV03_PGRAPH_NSOURCE_FORMAT_EXCEPTION, "FORMAT_EXCEPTION" },
+ { NV03_PGRAPH_NSOURCE_PATCH_EXCEPTION, "PATCH_EXCEPTION" },
+ { NV03_PGRAPH_NSOURCE_STATE_INVALID, "STATE_INVALID" },
+ { NV03_PGRAPH_NSOURCE_DOUBLE_NOTIFY, "DOUBLE_NOTIFY" },
+ { NV03_PGRAPH_NSOURCE_NOTIFY_IN_USE, "NOTIFY_IN_USE" },
+ { NV03_PGRAPH_NSOURCE_METHOD_CNT, "METHOD_CNT" },
+ { NV03_PGRAPH_NSOURCE_BFR_NOTIFICATION, "BFR_NOTIFICATION" },
+ { NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION, "DMA_VTX_PROTECTION" },
+ { NV03_PGRAPH_NSOURCE_DMA_WIDTH_A, "DMA_WIDTH_A" },
+ { NV03_PGRAPH_NSOURCE_DMA_WIDTH_B, "DMA_WIDTH_B" },
+ {}
+};
+
+static void
+nv04_graph_context_switch(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
+ struct nouveau_channel *chan = NULL;
+ int chid;
- if (dev_priv->engine.graph.registered)
- return 0;
+ nouveau_wait_for_idle(dev);
+
+ /* If previous context is valid, we need to save it */
+ nv04_graph_unload_context(dev);
+
+ /* Load context for next channel */
+ chid = dev_priv->engine.fifo.channel_id(dev);
+ chan = dev_priv->channels.ptr[chid];
+ if (chan)
+ nv04_graph_load_context(chan);
+}
+
+static void
+nv04_graph_isr(struct drm_device *dev)
+{
+ u32 stat;
+
+ while ((stat = nv_rd32(dev, NV03_PGRAPH_INTR))) {
+ u32 nsource = nv_rd32(dev, NV03_PGRAPH_NSOURCE);
+ u32 nstatus = nv_rd32(dev, NV03_PGRAPH_NSTATUS);
+ u32 addr = nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR);
+ u32 chid = (addr & 0x0f000000) >> 24;
+ u32 subc = (addr & 0x0000e000) >> 13;
+ u32 mthd = (addr & 0x00001ffc);
+ u32 data = nv_rd32(dev, NV04_PGRAPH_TRAPPED_DATA);
+ u32 class = nv_rd32(dev, 0x400180 + subc * 4) & 0xff;
+ u32 show = stat;
+
+ if (stat & NV_PGRAPH_INTR_NOTIFY) {
+ if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
+ if (!nouveau_gpuobj_mthd_call2(dev, chid, class, mthd, data))
+ show &= ~NV_PGRAPH_INTR_NOTIFY;
+ }
+ }
+
+ if (stat & NV_PGRAPH_INTR_CONTEXT_SWITCH) {
+ nv_wr32(dev, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_CONTEXT_SWITCH);
+ stat &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
+ show &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
+ nv04_graph_context_switch(dev);
+ }
+
+ nv_wr32(dev, NV03_PGRAPH_INTR, stat);
+ nv_wr32(dev, NV04_PGRAPH_FIFO, 0x00000001);
+
+ if (show && nouveau_ratelimit()) {
+ NV_INFO(dev, "PGRAPH -");
+ nouveau_bitfield_print(nv04_graph_intr, show);
+ printk(" nsource:");
+ nouveau_bitfield_print(nv04_graph_nsource, nsource);
+ printk(" nstatus:");
+ nouveau_bitfield_print(nv04_graph_nstatus, nstatus);
+ printk("\n");
+ NV_INFO(dev, "PGRAPH - ch %d/%d class 0x%04x "
+ "mthd 0x%04x data 0x%08x\n",
+ chid, subc, class, mthd, data);
+ }
+ }
+}
+
+static void
+nv04_graph_destroy(struct drm_device *dev, int engine)
+{
+ struct nv04_graph_engine *pgraph = nv_engine(dev, engine);
+
+ nouveau_irq_unregister(dev, 12);
+
+ NVOBJ_ENGINE_DEL(dev, GR);
+ kfree(pgraph);
+}
+
+int
+nv04_graph_create(struct drm_device *dev)
+{
+ struct nv04_graph_engine *pgraph;
+
+ pgraph = kzalloc(sizeof(*pgraph), GFP_KERNEL);
+ if (!pgraph)
+ return -ENOMEM;
+
+ pgraph->base.destroy = nv04_graph_destroy;
+ pgraph->base.init = nv04_graph_init;
+ pgraph->base.fini = nv04_graph_fini;
+ pgraph->base.context_new = nv04_graph_context_new;
+ pgraph->base.context_del = nv04_graph_context_del;
+ pgraph->base.object_new = nv04_graph_object_new;
+
+ NVOBJ_ENGINE_ADD(dev, GR, &pgraph->base);
+ nouveau_irq_register(dev, 12, nv04_graph_isr);
/* dvd subpicture */
NVOBJ_CLASS(dev, 0x0038, GR);
@@ -1222,93 +1355,5 @@
NVOBJ_CLASS(dev, 0x506e, SW);
NVOBJ_MTHD (dev, 0x506e, 0x0150, nv04_graph_mthd_set_ref);
NVOBJ_MTHD (dev, 0x506e, 0x0500, nv04_graph_mthd_page_flip);
-
- dev_priv->engine.graph.registered = true;
return 0;
-};
-
-static struct nouveau_bitfield nv04_graph_intr[] = {
- { NV_PGRAPH_INTR_NOTIFY, "NOTIFY" },
- {}
-};
-
-static struct nouveau_bitfield nv04_graph_nstatus[] =
-{
- { NV04_PGRAPH_NSTATUS_STATE_IN_USE, "STATE_IN_USE" },
- { NV04_PGRAPH_NSTATUS_INVALID_STATE, "INVALID_STATE" },
- { NV04_PGRAPH_NSTATUS_BAD_ARGUMENT, "BAD_ARGUMENT" },
- { NV04_PGRAPH_NSTATUS_PROTECTION_FAULT, "PROTECTION_FAULT" },
- {}
-};
-
-struct nouveau_bitfield nv04_graph_nsource[] =
-{
- { NV03_PGRAPH_NSOURCE_NOTIFICATION, "NOTIFICATION" },
- { NV03_PGRAPH_NSOURCE_DATA_ERROR, "DATA_ERROR" },
- { NV03_PGRAPH_NSOURCE_PROTECTION_ERROR, "PROTECTION_ERROR" },
- { NV03_PGRAPH_NSOURCE_RANGE_EXCEPTION, "RANGE_EXCEPTION" },
- { NV03_PGRAPH_NSOURCE_LIMIT_COLOR, "LIMIT_COLOR" },
- { NV03_PGRAPH_NSOURCE_LIMIT_ZETA, "LIMIT_ZETA" },
- { NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD, "ILLEGAL_MTHD" },
- { NV03_PGRAPH_NSOURCE_DMA_R_PROTECTION, "DMA_R_PROTECTION" },
- { NV03_PGRAPH_NSOURCE_DMA_W_PROTECTION, "DMA_W_PROTECTION" },
- { NV03_PGRAPH_NSOURCE_FORMAT_EXCEPTION, "FORMAT_EXCEPTION" },
- { NV03_PGRAPH_NSOURCE_PATCH_EXCEPTION, "PATCH_EXCEPTION" },
- { NV03_PGRAPH_NSOURCE_STATE_INVALID, "STATE_INVALID" },
- { NV03_PGRAPH_NSOURCE_DOUBLE_NOTIFY, "DOUBLE_NOTIFY" },
- { NV03_PGRAPH_NSOURCE_NOTIFY_IN_USE, "NOTIFY_IN_USE" },
- { NV03_PGRAPH_NSOURCE_METHOD_CNT, "METHOD_CNT" },
- { NV03_PGRAPH_NSOURCE_BFR_NOTIFICATION, "BFR_NOTIFICATION" },
- { NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION, "DMA_VTX_PROTECTION" },
- { NV03_PGRAPH_NSOURCE_DMA_WIDTH_A, "DMA_WIDTH_A" },
- { NV03_PGRAPH_NSOURCE_DMA_WIDTH_B, "DMA_WIDTH_B" },
- {}
-};
-
-static void
-nv04_graph_isr(struct drm_device *dev)
-{
- u32 stat;
-
- while ((stat = nv_rd32(dev, NV03_PGRAPH_INTR))) {
- u32 nsource = nv_rd32(dev, NV03_PGRAPH_NSOURCE);
- u32 nstatus = nv_rd32(dev, NV03_PGRAPH_NSTATUS);
- u32 addr = nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR);
- u32 chid = (addr & 0x0f000000) >> 24;
- u32 subc = (addr & 0x0000e000) >> 13;
- u32 mthd = (addr & 0x00001ffc);
- u32 data = nv_rd32(dev, NV04_PGRAPH_TRAPPED_DATA);
- u32 class = nv_rd32(dev, 0x400180 + subc * 4) & 0xff;
- u32 show = stat;
-
- if (stat & NV_PGRAPH_INTR_NOTIFY) {
- if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
- if (!nouveau_gpuobj_mthd_call2(dev, chid, class, mthd, data))
- show &= ~NV_PGRAPH_INTR_NOTIFY;
- }
- }
-
- if (stat & NV_PGRAPH_INTR_CONTEXT_SWITCH) {
- nv_wr32(dev, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_CONTEXT_SWITCH);
- stat &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
- show &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
- nv04_graph_context_switch(dev);
- }
-
- nv_wr32(dev, NV03_PGRAPH_INTR, stat);
- nv_wr32(dev, NV04_PGRAPH_FIFO, 0x00000001);
-
- if (show && nouveau_ratelimit()) {
- NV_INFO(dev, "PGRAPH -");
- nouveau_bitfield_print(nv04_graph_intr, show);
- printk(" nsource:");
- nouveau_bitfield_print(nv04_graph_nsource, nsource);
- printk(" nstatus:");
- nouveau_bitfield_print(nv04_graph_nstatus, nstatus);
- printk("\n");
- NV_INFO(dev, "PGRAPH - ch %d/%d class 0x%04x "
- "mthd 0x%04x data 0x%08x\n",
- chid, subc, class, mthd, data);
- }
- }
}
diff --git a/drivers/gpu/drm/nouveau/nv04_instmem.c b/drivers/gpu/drm/nouveau/nv04_instmem.c
index b8e3edb..b8611b9 100644
--- a/drivers/gpu/drm/nouveau/nv04_instmem.c
+++ b/drivers/gpu/drm/nouveau/nv04_instmem.c
@@ -95,6 +95,9 @@
nouveau_ramht_ref(NULL, &dev_priv->ramht, NULL);
nouveau_gpuobj_ref(NULL, &dev_priv->ramro);
nouveau_gpuobj_ref(NULL, &dev_priv->ramfc);
+
+ if (drm_mm_initialized(&dev_priv->ramin_heap))
+ drm_mm_takedown(&dev_priv->ramin_heap);
}
int
diff --git a/drivers/gpu/drm/nouveau/nv10_graph.c b/drivers/gpu/drm/nouveau/nv10_graph.c
index 8c92edb..0930c6c 100644
--- a/drivers/gpu/drm/nouveau/nv10_graph.c
+++ b/drivers/gpu/drm/nouveau/nv10_graph.c
@@ -28,10 +28,9 @@
#include "nouveau_drv.h"
#include "nouveau_util.h"
-static int nv10_graph_register(struct drm_device *);
-static void nv10_graph_isr(struct drm_device *);
-
-#define NV10_FIFO_NUMBER 32
+struct nv10_graph_engine {
+ struct nouveau_exec_engine base;
+};
struct pipe_state {
uint32_t pipe_0x0000[0x040/4];
@@ -414,9 +413,9 @@
static void nv10_graph_save_pipe(struct nouveau_channel *chan)
{
- struct drm_device *dev = chan->dev;
- struct graph_state *pgraph_ctx = chan->pgraph_ctx;
+ struct graph_state *pgraph_ctx = chan->engctx[NVOBJ_ENGINE_GR];
struct pipe_state *pipe = &pgraph_ctx->pipe_state;
+ struct drm_device *dev = chan->dev;
PIPE_SAVE(dev, pipe->pipe_0x4400, 0x4400);
PIPE_SAVE(dev, pipe->pipe_0x0200, 0x0200);
@@ -432,9 +431,9 @@
static void nv10_graph_load_pipe(struct nouveau_channel *chan)
{
- struct drm_device *dev = chan->dev;
- struct graph_state *pgraph_ctx = chan->pgraph_ctx;
+ struct graph_state *pgraph_ctx = chan->engctx[NVOBJ_ENGINE_GR];
struct pipe_state *pipe = &pgraph_ctx->pipe_state;
+ struct drm_device *dev = chan->dev;
uint32_t xfmode0, xfmode1;
int i;
@@ -482,9 +481,9 @@
static void nv10_graph_create_pipe(struct nouveau_channel *chan)
{
- struct drm_device *dev = chan->dev;
- struct graph_state *pgraph_ctx = chan->pgraph_ctx;
+ struct graph_state *pgraph_ctx = chan->engctx[NVOBJ_ENGINE_GR];
struct pipe_state *fifo_pipe_state = &pgraph_ctx->pipe_state;
+ struct drm_device *dev = chan->dev;
uint32_t *fifo_pipe_state_addr;
int i;
#define PIPE_INIT(addr) \
@@ -661,8 +660,6 @@
uint32_t inst)
{
struct drm_device *dev = chan->dev;
- struct drm_nouveau_private *dev_priv = dev->dev_private;
- struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
uint32_t st2, st2_dl, st2_dh, fifo_ptr, fifo[0x60/4];
uint32_t ctx_user, ctx_switch[5];
int i, subchan = -1;
@@ -711,8 +708,8 @@
0x2c000000 | chan->id << 20 | subchan << 16 | 0x18c);
nv_wr32(dev, NV10_PGRAPH_FFINTFC_ST2_DL, inst);
nv_mask(dev, NV10_PGRAPH_CTX_CONTROL, 0, 0x10000);
- pgraph->fifo_access(dev, true);
- pgraph->fifo_access(dev, false);
+ nv04_graph_fifo_access(dev, true);
+ nv04_graph_fifo_access(dev, false);
/* Restore the FIFO state */
for (i = 0; i < ARRAY_SIZE(fifo); i++)
@@ -729,11 +726,12 @@
nv_wr32(dev, NV10_PGRAPH_CTX_USER, ctx_user);
}
-int nv10_graph_load_context(struct nouveau_channel *chan)
+static int
+nv10_graph_load_context(struct nouveau_channel *chan)
{
struct drm_device *dev = chan->dev;
struct drm_nouveau_private *dev_priv = dev->dev_private;
- struct graph_state *pgraph_ctx = chan->pgraph_ctx;
+ struct graph_state *pgraph_ctx = chan->engctx[NVOBJ_ENGINE_GR];
uint32_t tmp;
int i;
@@ -757,21 +755,20 @@
return 0;
}
-int
+static int
nv10_graph_unload_context(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
- struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
struct nouveau_channel *chan;
struct graph_state *ctx;
uint32_t tmp;
int i;
- chan = pgraph->channel(dev);
+ chan = nv10_graph_channel(dev);
if (!chan)
return 0;
- ctx = chan->pgraph_ctx;
+ ctx = chan->engctx[NVOBJ_ENGINE_GR];
for (i = 0; i < ARRAY_SIZE(nv10_graph_ctx_regs); i++)
ctx->nv10[i] = nv_rd32(dev, nv10_graph_ctx_regs[i]);
@@ -805,7 +802,7 @@
/* Load context for next channel */
chid = (nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR) >> 20) & 0x1f;
chan = dev_priv->channels.ptr[chid];
- if (chan && chan->pgraph_ctx)
+ if (chan && chan->engctx[NVOBJ_ENGINE_GR])
nv10_graph_load_context(chan);
}
@@ -836,7 +833,8 @@
return dev_priv->channels.ptr[chid];
}
-int nv10_graph_create_context(struct nouveau_channel *chan)
+static int
+nv10_graph_context_new(struct nouveau_channel *chan, int engine)
{
struct drm_device *dev = chan->dev;
struct drm_nouveau_private *dev_priv = dev->dev_private;
@@ -844,11 +842,10 @@
NV_DEBUG(dev, "nv10_graph_context_create %d\n", chan->id);
- chan->pgraph_ctx = pgraph_ctx = kzalloc(sizeof(*pgraph_ctx),
- GFP_KERNEL);
+ pgraph_ctx = kzalloc(sizeof(*pgraph_ctx), GFP_KERNEL);
if (pgraph_ctx == NULL)
return -ENOMEM;
-
+ chan->engctx[engine] = pgraph_ctx;
NV_WRITE_CTX(0x00400e88, 0x08000000);
NV_WRITE_CTX(0x00400e9c, 0x4b7fffff);
@@ -873,30 +870,30 @@
return 0;
}
-void nv10_graph_destroy_context(struct nouveau_channel *chan)
+static void
+nv10_graph_context_del(struct nouveau_channel *chan, int engine)
{
struct drm_device *dev = chan->dev;
struct drm_nouveau_private *dev_priv = dev->dev_private;
- struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
- struct graph_state *pgraph_ctx = chan->pgraph_ctx;
+ struct graph_state *pgraph_ctx = chan->engctx[engine];
unsigned long flags;
spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
- pgraph->fifo_access(dev, false);
+ nv04_graph_fifo_access(dev, false);
/* Unload the context if it's the currently active one */
- if (pgraph->channel(dev) == chan)
- pgraph->unload_context(dev);
+ if (nv10_graph_channel(dev) == chan)
+ nv10_graph_unload_context(dev);
+
+ nv04_graph_fifo_access(dev, true);
+ spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
/* Free the context resources */
+ chan->engctx[engine] = NULL;
kfree(pgraph_ctx);
- chan->pgraph_ctx = NULL;
-
- pgraph->fifo_access(dev, true);
- spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
}
-void
+static void
nv10_graph_set_tile_region(struct drm_device *dev, int i)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
@@ -907,22 +904,18 @@
nv_wr32(dev, NV10_PGRAPH_TILE(i), tile->addr);
}
-int nv10_graph_init(struct drm_device *dev)
+static int
+nv10_graph_init(struct drm_device *dev, int engine)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
- uint32_t tmp;
- int ret, i;
+ u32 tmp;
+ int i;
nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) &
~NV_PMC_ENABLE_PGRAPH);
nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
NV_PMC_ENABLE_PGRAPH);
- ret = nv10_graph_register(dev);
- if (ret)
- return ret;
-
- nouveau_irq_register(dev, 12, nv10_graph_isr);
nv_wr32(dev, NV03_PGRAPH_INTR , 0xFFFFFFFF);
nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
@@ -963,18 +956,20 @@
return 0;
}
-void nv10_graph_takedown(struct drm_device *dev)
+static int
+nv10_graph_fini(struct drm_device *dev, int engine)
{
+ nv10_graph_unload_context(dev);
nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0x00000000);
- nouveau_irq_unregister(dev, 12);
+ return 0;
}
static int
nv17_graph_mthd_lma_window(struct nouveau_channel *chan,
u32 class, u32 mthd, u32 data)
{
+ struct graph_state *ctx = chan->engctx[NVOBJ_ENGINE_GR];
struct drm_device *dev = chan->dev;
- struct graph_state *ctx = chan->pgraph_ctx;
struct pipe_state *pipe = &ctx->pipe_state;
uint32_t pipe_0x0040[1], pipe_0x64c0[8], pipe_0x6a80[3], pipe_0x6ab0[3];
uint32_t xfmode0, xfmode1;
@@ -1061,64 +1056,13 @@
return 0;
}
-static int
-nv10_graph_register(struct drm_device *dev)
-{
- struct drm_nouveau_private *dev_priv = dev->dev_private;
-
- if (dev_priv->engine.graph.registered)
- return 0;
-
- NVOBJ_CLASS(dev, 0x506e, SW); /* nvsw */
- NVOBJ_CLASS(dev, 0x0030, GR); /* null */
- NVOBJ_CLASS(dev, 0x0039, GR); /* m2mf */
- NVOBJ_CLASS(dev, 0x004a, GR); /* gdirect */
- NVOBJ_CLASS(dev, 0x005f, GR); /* imageblit */
- NVOBJ_CLASS(dev, 0x009f, GR); /* imageblit (nv12) */
- NVOBJ_CLASS(dev, 0x008a, GR); /* ifc */
- NVOBJ_CLASS(dev, 0x0089, GR); /* sifm */
- NVOBJ_CLASS(dev, 0x0062, GR); /* surf2d */
- NVOBJ_CLASS(dev, 0x0043, GR); /* rop */
- NVOBJ_CLASS(dev, 0x0012, GR); /* beta1 */
- NVOBJ_CLASS(dev, 0x0072, GR); /* beta4 */
- NVOBJ_CLASS(dev, 0x0019, GR); /* cliprect */
- NVOBJ_CLASS(dev, 0x0044, GR); /* pattern */
- NVOBJ_CLASS(dev, 0x0052, GR); /* swzsurf */
- NVOBJ_CLASS(dev, 0x0093, GR); /* surf3d */
- NVOBJ_CLASS(dev, 0x0094, GR); /* tex_tri */
- NVOBJ_CLASS(dev, 0x0095, GR); /* multitex_tri */
-
- /* celcius */
- if (dev_priv->chipset <= 0x10) {
- NVOBJ_CLASS(dev, 0x0056, GR);
- } else
- if (dev_priv->chipset < 0x17 || dev_priv->chipset == 0x1a) {
- NVOBJ_CLASS(dev, 0x0096, GR);
- } else {
- NVOBJ_CLASS(dev, 0x0099, GR);
- NVOBJ_MTHD (dev, 0x0099, 0x1638, nv17_graph_mthd_lma_window);
- NVOBJ_MTHD (dev, 0x0099, 0x163c, nv17_graph_mthd_lma_window);
- NVOBJ_MTHD (dev, 0x0099, 0x1640, nv17_graph_mthd_lma_window);
- NVOBJ_MTHD (dev, 0x0099, 0x1644, nv17_graph_mthd_lma_window);
- NVOBJ_MTHD (dev, 0x0099, 0x1658, nv17_graph_mthd_lma_enable);
- }
-
- /* nvsw */
- NVOBJ_CLASS(dev, 0x506e, SW);
- NVOBJ_MTHD (dev, 0x506e, 0x0500, nv04_graph_mthd_page_flip);
-
- dev_priv->engine.graph.registered = true;
- return 0;
-}
-
struct nouveau_bitfield nv10_graph_intr[] = {
{ NV_PGRAPH_INTR_NOTIFY, "NOTIFY" },
{ NV_PGRAPH_INTR_ERROR, "ERROR" },
{}
};
-struct nouveau_bitfield nv10_graph_nstatus[] =
-{
+struct nouveau_bitfield nv10_graph_nstatus[] = {
{ NV10_PGRAPH_NSTATUS_STATE_IN_USE, "STATE_IN_USE" },
{ NV10_PGRAPH_NSTATUS_INVALID_STATE, "INVALID_STATE" },
{ NV10_PGRAPH_NSTATUS_BAD_ARGUMENT, "BAD_ARGUMENT" },
@@ -1173,3 +1117,73 @@
}
}
}
+
+static void
+nv10_graph_destroy(struct drm_device *dev, int engine)
+{
+ struct nv10_graph_engine *pgraph = nv_engine(dev, engine);
+
+ nouveau_irq_unregister(dev, 12);
+ kfree(pgraph);
+}
+
+int
+nv10_graph_create(struct drm_device *dev)
+{
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+ struct nv10_graph_engine *pgraph;
+
+ pgraph = kzalloc(sizeof(*pgraph), GFP_KERNEL);
+ if (!pgraph)
+ return -ENOMEM;
+
+ pgraph->base.destroy = nv10_graph_destroy;
+ pgraph->base.init = nv10_graph_init;
+ pgraph->base.fini = nv10_graph_fini;
+ pgraph->base.context_new = nv10_graph_context_new;
+ pgraph->base.context_del = nv10_graph_context_del;
+ pgraph->base.object_new = nv04_graph_object_new;
+ pgraph->base.set_tile_region = nv10_graph_set_tile_region;
+
+ NVOBJ_ENGINE_ADD(dev, GR, &pgraph->base);
+ nouveau_irq_register(dev, 12, nv10_graph_isr);
+
+ /* nvsw */
+ NVOBJ_CLASS(dev, 0x506e, SW);
+ NVOBJ_MTHD (dev, 0x506e, 0x0500, nv04_graph_mthd_page_flip);
+
+ NVOBJ_CLASS(dev, 0x0030, GR); /* null */
+ NVOBJ_CLASS(dev, 0x0039, GR); /* m2mf */
+ NVOBJ_CLASS(dev, 0x004a, GR); /* gdirect */
+ NVOBJ_CLASS(dev, 0x005f, GR); /* imageblit */
+ NVOBJ_CLASS(dev, 0x009f, GR); /* imageblit (nv12) */
+ NVOBJ_CLASS(dev, 0x008a, GR); /* ifc */
+ NVOBJ_CLASS(dev, 0x0089, GR); /* sifm */
+ NVOBJ_CLASS(dev, 0x0062, GR); /* surf2d */
+ NVOBJ_CLASS(dev, 0x0043, GR); /* rop */
+ NVOBJ_CLASS(dev, 0x0012, GR); /* beta1 */
+ NVOBJ_CLASS(dev, 0x0072, GR); /* beta4 */
+ NVOBJ_CLASS(dev, 0x0019, GR); /* cliprect */
+ NVOBJ_CLASS(dev, 0x0044, GR); /* pattern */
+ NVOBJ_CLASS(dev, 0x0052, GR); /* swzsurf */
+ NVOBJ_CLASS(dev, 0x0093, GR); /* surf3d */
+ NVOBJ_CLASS(dev, 0x0094, GR); /* tex_tri */
+ NVOBJ_CLASS(dev, 0x0095, GR); /* multitex_tri */
+
+ /* celcius */
+ if (dev_priv->chipset <= 0x10) {
+ NVOBJ_CLASS(dev, 0x0056, GR);
+ } else
+ if (dev_priv->chipset < 0x17 || dev_priv->chipset == 0x1a) {
+ NVOBJ_CLASS(dev, 0x0096, GR);
+ } else {
+ NVOBJ_CLASS(dev, 0x0099, GR);
+ NVOBJ_MTHD (dev, 0x0099, 0x1638, nv17_graph_mthd_lma_window);
+ NVOBJ_MTHD (dev, 0x0099, 0x163c, nv17_graph_mthd_lma_window);
+ NVOBJ_MTHD (dev, 0x0099, 0x1640, nv17_graph_mthd_lma_window);
+ NVOBJ_MTHD (dev, 0x0099, 0x1644, nv17_graph_mthd_lma_window);
+ NVOBJ_MTHD (dev, 0x0099, 0x1658, nv17_graph_mthd_lma_enable);
+ }
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/nouveau/nv20_graph.c b/drivers/gpu/drm/nouveau/nv20_graph.c
index 8464b76..affc7d7 100644
--- a/drivers/gpu/drm/nouveau/nv20_graph.c
+++ b/drivers/gpu/drm/nouveau/nv20_graph.c
@@ -24,6 +24,14 @@
*
*/
+struct nv20_graph_engine {
+ struct nouveau_exec_engine base;
+ struct nouveau_gpuobj *ctxtab;
+ void (*grctx_init)(struct nouveau_gpuobj *);
+ u32 grctx_size;
+ u32 grctx_user;
+};
+
#define NV20_GRCTX_SIZE (3580*4)
#define NV25_GRCTX_SIZE (3529*4)
#define NV2A_GRCTX_SIZE (3500*4)
@@ -32,12 +40,54 @@
#define NV34_GRCTX_SIZE (18140)
#define NV35_36_GRCTX_SIZE (22396)
-static int nv20_graph_register(struct drm_device *);
-static int nv30_graph_register(struct drm_device *);
-static void nv20_graph_isr(struct drm_device *);
+int
+nv20_graph_unload_context(struct drm_device *dev)
+{
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+ struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
+ struct nouveau_channel *chan;
+ struct nouveau_gpuobj *grctx;
+ u32 tmp;
+
+ chan = nv10_graph_channel(dev);
+ if (!chan)
+ return 0;
+ grctx = chan->engctx[NVOBJ_ENGINE_GR];
+
+ nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, grctx->pinst >> 4);
+ nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_XFER,
+ NV20_PGRAPH_CHANNEL_CTX_XFER_SAVE);
+
+ nouveau_wait_for_idle(dev);
+
+ nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10000000);
+ tmp = nv_rd32(dev, NV10_PGRAPH_CTX_USER) & 0x00ffffff;
+ tmp |= (pfifo->channels - 1) << 24;
+ nv_wr32(dev, NV10_PGRAPH_CTX_USER, tmp);
+ return 0;
+}
static void
-nv20_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx)
+nv20_graph_rdi(struct drm_device *dev)
+{
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+ int i, writecount = 32;
+ uint32_t rdi_index = 0x2c80000;
+
+ if (dev_priv->chipset == 0x20) {
+ rdi_index = 0x3d0000;
+ writecount = 15;
+ }
+
+ nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, rdi_index);
+ for (i = 0; i < writecount; i++)
+ nv_wr32(dev, NV10_PGRAPH_RDI_DATA, 0);
+
+ nouveau_wait_for_idle(dev);
+}
+
+static void
+nv20_graph_context_init(struct nouveau_gpuobj *ctx)
{
int i;
@@ -87,7 +137,7 @@
}
static void
-nv25_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx)
+nv25_graph_context_init(struct nouveau_gpuobj *ctx)
{
int i;
@@ -146,7 +196,7 @@
}
static void
-nv2a_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx)
+nv2a_graph_context_init(struct nouveau_gpuobj *ctx)
{
int i;
@@ -196,7 +246,7 @@
}
static void
-nv30_31_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx)
+nv30_31_graph_context_init(struct nouveau_gpuobj *ctx)
{
int i;
@@ -254,7 +304,7 @@
}
static void
-nv34_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx)
+nv34_graph_context_init(struct nouveau_gpuobj *ctx)
{
int i;
@@ -312,7 +362,7 @@
}
static void
-nv35_36_graph_context_init(struct drm_device *dev, struct nouveau_gpuobj *ctx)
+nv35_36_graph_context_init(struct nouveau_gpuobj *ctx)
{
int i;
@@ -370,148 +420,57 @@
}
int
-nv20_graph_create_context(struct nouveau_channel *chan)
+nv20_graph_context_new(struct nouveau_channel *chan, int engine)
{
+ struct nv20_graph_engine *pgraph = nv_engine(chan->dev, engine);
+ struct nouveau_gpuobj *grctx = NULL;
struct drm_device *dev = chan->dev;
- struct drm_nouveau_private *dev_priv = dev->dev_private;
- struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
- void (*ctx_init)(struct drm_device *, struct nouveau_gpuobj *);
- unsigned int idoffs = 0x28;
int ret;
- switch (dev_priv->chipset) {
- case 0x20:
- ctx_init = nv20_graph_context_init;
- idoffs = 0;
- break;
- case 0x25:
- case 0x28:
- ctx_init = nv25_graph_context_init;
- break;
- case 0x2a:
- ctx_init = nv2a_graph_context_init;
- idoffs = 0;
- break;
- case 0x30:
- case 0x31:
- ctx_init = nv30_31_graph_context_init;
- break;
- case 0x34:
- ctx_init = nv34_graph_context_init;
- break;
- case 0x35:
- case 0x36:
- ctx_init = nv35_36_graph_context_init;
- break;
- default:
- BUG_ON(1);
- }
-
- ret = nouveau_gpuobj_new(dev, chan, pgraph->grctx_size, 16,
- NVOBJ_FLAG_ZERO_ALLOC, &chan->ramin_grctx);
+ ret = nouveau_gpuobj_new(dev, NULL, pgraph->grctx_size, 16,
+ NVOBJ_FLAG_ZERO_ALLOC, &grctx);
if (ret)
return ret;
/* Initialise default context values */
- ctx_init(dev, chan->ramin_grctx);
+ pgraph->grctx_init(grctx);
/* nv20: nv_wo32(dev, chan->ramin_grctx->gpuobj, 10, chan->id<<24); */
- nv_wo32(chan->ramin_grctx, idoffs,
- (chan->id << 24) | 0x1); /* CTX_USER */
+ /* CTX_USER */
+ nv_wo32(grctx, pgraph->grctx_user, (chan->id << 24) | 0x1);
- nv_wo32(pgraph->ctx_table, chan->id * 4, chan->ramin_grctx->pinst >> 4);
+ nv_wo32(pgraph->ctxtab, chan->id * 4, grctx->pinst >> 4);
+ chan->engctx[engine] = grctx;
return 0;
}
void
-nv20_graph_destroy_context(struct nouveau_channel *chan)
+nv20_graph_context_del(struct nouveau_channel *chan, int engine)
{
+ struct nv20_graph_engine *pgraph = nv_engine(chan->dev, engine);
+ struct nouveau_gpuobj *grctx = chan->engctx[engine];
struct drm_device *dev = chan->dev;
struct drm_nouveau_private *dev_priv = dev->dev_private;
- struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
unsigned long flags;
spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
- pgraph->fifo_access(dev, false);
+ nv04_graph_fifo_access(dev, false);
/* Unload the context if it's the currently active one */
- if (pgraph->channel(dev) == chan)
- pgraph->unload_context(dev);
+ if (nv10_graph_channel(dev) == chan)
+ nv20_graph_unload_context(dev);
- pgraph->fifo_access(dev, true);
+ nv04_graph_fifo_access(dev, true);
spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
/* Free the context resources */
- nv_wo32(pgraph->ctx_table, chan->id * 4, 0);
- nouveau_gpuobj_ref(NULL, &chan->ramin_grctx);
-}
+ nv_wo32(pgraph->ctxtab, chan->id * 4, 0);
-int
-nv20_graph_load_context(struct nouveau_channel *chan)
-{
- struct drm_device *dev = chan->dev;
- uint32_t inst;
-
- if (!chan->ramin_grctx)
- return -EINVAL;
- inst = chan->ramin_grctx->pinst >> 4;
-
- nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
- nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_XFER,
- NV20_PGRAPH_CHANNEL_CTX_XFER_LOAD);
- nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10010100);
-
- nouveau_wait_for_idle(dev);
- return 0;
-}
-
-int
-nv20_graph_unload_context(struct drm_device *dev)
-{
- struct drm_nouveau_private *dev_priv = dev->dev_private;
- struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
- struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
- struct nouveau_channel *chan;
- uint32_t inst, tmp;
-
- chan = pgraph->channel(dev);
- if (!chan)
- return 0;
- inst = chan->ramin_grctx->pinst >> 4;
-
- nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
- nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_XFER,
- NV20_PGRAPH_CHANNEL_CTX_XFER_SAVE);
-
- nouveau_wait_for_idle(dev);
-
- nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10000000);
- tmp = nv_rd32(dev, NV10_PGRAPH_CTX_USER) & 0x00ffffff;
- tmp |= (pfifo->channels - 1) << 24;
- nv_wr32(dev, NV10_PGRAPH_CTX_USER, tmp);
- return 0;
+ nouveau_gpuobj_ref(NULL, &grctx);
+ chan->engctx[engine] = NULL;
}
static void
-nv20_graph_rdi(struct drm_device *dev)
-{
- struct drm_nouveau_private *dev_priv = dev->dev_private;
- int i, writecount = 32;
- uint32_t rdi_index = 0x2c80000;
-
- if (dev_priv->chipset == 0x20) {
- rdi_index = 0x3d0000;
- writecount = 15;
- }
-
- nv_wr32(dev, NV10_PGRAPH_RDI_INDEX, rdi_index);
- for (i = 0; i < writecount; i++)
- nv_wr32(dev, NV10_PGRAPH_RDI_DATA, 0);
-
- nouveau_wait_for_idle(dev);
-}
-
-void
nv20_graph_set_tile_region(struct drm_device *dev, int i)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
@@ -536,56 +495,22 @@
}
int
-nv20_graph_init(struct drm_device *dev)
+nv20_graph_init(struct drm_device *dev, int engine)
{
+ struct nv20_graph_engine *pgraph = nv_engine(dev, engine);
struct drm_nouveau_private *dev_priv = dev->dev_private;
- struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
uint32_t tmp, vramsz;
- int ret, i;
-
- switch (dev_priv->chipset) {
- case 0x20:
- pgraph->grctx_size = NV20_GRCTX_SIZE;
- break;
- case 0x25:
- case 0x28:
- pgraph->grctx_size = NV25_GRCTX_SIZE;
- break;
- case 0x2a:
- pgraph->grctx_size = NV2A_GRCTX_SIZE;
- break;
- default:
- NV_ERROR(dev, "unknown chipset, disabling acceleration\n");
- pgraph->accel_blocked = true;
- return 0;
- }
+ int i;
nv_wr32(dev, NV03_PMC_ENABLE,
nv_rd32(dev, NV03_PMC_ENABLE) & ~NV_PMC_ENABLE_PGRAPH);
nv_wr32(dev, NV03_PMC_ENABLE,
nv_rd32(dev, NV03_PMC_ENABLE) | NV_PMC_ENABLE_PGRAPH);
- if (!pgraph->ctx_table) {
- /* Create Context Pointer Table */
- ret = nouveau_gpuobj_new(dev, NULL, 32 * 4, 16,
- NVOBJ_FLAG_ZERO_ALLOC,
- &pgraph->ctx_table);
- if (ret)
- return ret;
- }
-
- nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_TABLE,
- pgraph->ctx_table->pinst >> 4);
+ nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_TABLE, pgraph->ctxtab->pinst >> 4);
nv20_graph_rdi(dev);
- ret = nv20_graph_register(dev);
- if (ret) {
- nouveau_gpuobj_ref(NULL, &pgraph->ctx_table);
- return ret;
- }
-
- nouveau_irq_register(dev, 12, nv20_graph_isr);
nv_wr32(dev, NV03_PGRAPH_INTR , 0xFFFFFFFF);
nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
@@ -657,67 +582,20 @@
return 0;
}
-void
-nv20_graph_takedown(struct drm_device *dev)
-{
- struct drm_nouveau_private *dev_priv = dev->dev_private;
- struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
-
- nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0x00000000);
- nouveau_irq_unregister(dev, 12);
-
- nouveau_gpuobj_ref(NULL, &pgraph->ctx_table);
-}
-
int
-nv30_graph_init(struct drm_device *dev)
+nv30_graph_init(struct drm_device *dev, int engine)
{
+ struct nv20_graph_engine *pgraph = nv_engine(dev, engine);
struct drm_nouveau_private *dev_priv = dev->dev_private;
- struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
- int ret, i;
-
- switch (dev_priv->chipset) {
- case 0x30:
- case 0x31:
- pgraph->grctx_size = NV30_31_GRCTX_SIZE;
- break;
- case 0x34:
- pgraph->grctx_size = NV34_GRCTX_SIZE;
- break;
- case 0x35:
- case 0x36:
- pgraph->grctx_size = NV35_36_GRCTX_SIZE;
- break;
- default:
- NV_ERROR(dev, "unknown chipset, disabling acceleration\n");
- pgraph->accel_blocked = true;
- return 0;
- }
+ int i;
nv_wr32(dev, NV03_PMC_ENABLE,
nv_rd32(dev, NV03_PMC_ENABLE) & ~NV_PMC_ENABLE_PGRAPH);
nv_wr32(dev, NV03_PMC_ENABLE,
nv_rd32(dev, NV03_PMC_ENABLE) | NV_PMC_ENABLE_PGRAPH);
- if (!pgraph->ctx_table) {
- /* Create Context Pointer Table */
- ret = nouveau_gpuobj_new(dev, NULL, 32 * 4, 16,
- NVOBJ_FLAG_ZERO_ALLOC,
- &pgraph->ctx_table);
- if (ret)
- return ret;
- }
+ nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_TABLE, pgraph->ctxtab->pinst >> 4);
- ret = nv30_graph_register(dev);
- if (ret) {
- nouveau_gpuobj_ref(NULL, &pgraph->ctx_table);
- return ret;
- }
-
- nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_TABLE,
- pgraph->ctx_table->pinst >> 4);
-
- nouveau_irq_register(dev, 12, nv20_graph_isr);
nv_wr32(dev, NV03_PGRAPH_INTR , 0xFFFFFFFF);
nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0xFFFFFFFF);
@@ -775,85 +653,11 @@
return 0;
}
-static int
-nv20_graph_register(struct drm_device *dev)
+int
+nv20_graph_fini(struct drm_device *dev, int engine)
{
- struct drm_nouveau_private *dev_priv = dev->dev_private;
-
- if (dev_priv->engine.graph.registered)
- return 0;
-
- NVOBJ_CLASS(dev, 0x506e, SW); /* nvsw */
- NVOBJ_CLASS(dev, 0x0030, GR); /* null */
- NVOBJ_CLASS(dev, 0x0039, GR); /* m2mf */
- NVOBJ_CLASS(dev, 0x004a, GR); /* gdirect */
- NVOBJ_CLASS(dev, 0x009f, GR); /* imageblit (nv12) */
- NVOBJ_CLASS(dev, 0x008a, GR); /* ifc */
- NVOBJ_CLASS(dev, 0x0089, GR); /* sifm */
- NVOBJ_CLASS(dev, 0x0062, GR); /* surf2d */
- NVOBJ_CLASS(dev, 0x0043, GR); /* rop */
- NVOBJ_CLASS(dev, 0x0012, GR); /* beta1 */
- NVOBJ_CLASS(dev, 0x0072, GR); /* beta4 */
- NVOBJ_CLASS(dev, 0x0019, GR); /* cliprect */
- NVOBJ_CLASS(dev, 0x0044, GR); /* pattern */
- NVOBJ_CLASS(dev, 0x009e, GR); /* swzsurf */
- NVOBJ_CLASS(dev, 0x0096, GR); /* celcius */
-
- /* kelvin */
- if (dev_priv->chipset < 0x25)
- NVOBJ_CLASS(dev, 0x0097, GR);
- else
- NVOBJ_CLASS(dev, 0x0597, GR);
-
- /* nvsw */
- NVOBJ_CLASS(dev, 0x506e, SW);
- NVOBJ_MTHD (dev, 0x506e, 0x0500, nv04_graph_mthd_page_flip);
-
- dev_priv->engine.graph.registered = true;
- return 0;
-}
-
-static int
-nv30_graph_register(struct drm_device *dev)
-{
- struct drm_nouveau_private *dev_priv = dev->dev_private;
-
- if (dev_priv->engine.graph.registered)
- return 0;
-
- NVOBJ_CLASS(dev, 0x506e, SW); /* nvsw */
- NVOBJ_CLASS(dev, 0x0030, GR); /* null */
- NVOBJ_CLASS(dev, 0x0039, GR); /* m2mf */
- NVOBJ_CLASS(dev, 0x004a, GR); /* gdirect */
- NVOBJ_CLASS(dev, 0x009f, GR); /* imageblit (nv12) */
- NVOBJ_CLASS(dev, 0x008a, GR); /* ifc */
- NVOBJ_CLASS(dev, 0x038a, GR); /* ifc (nv30) */
- NVOBJ_CLASS(dev, 0x0089, GR); /* sifm */
- NVOBJ_CLASS(dev, 0x0389, GR); /* sifm (nv30) */
- NVOBJ_CLASS(dev, 0x0062, GR); /* surf2d */
- NVOBJ_CLASS(dev, 0x0362, GR); /* surf2d (nv30) */
- NVOBJ_CLASS(dev, 0x0043, GR); /* rop */
- NVOBJ_CLASS(dev, 0x0012, GR); /* beta1 */
- NVOBJ_CLASS(dev, 0x0072, GR); /* beta4 */
- NVOBJ_CLASS(dev, 0x0019, GR); /* cliprect */
- NVOBJ_CLASS(dev, 0x0044, GR); /* pattern */
- NVOBJ_CLASS(dev, 0x039e, GR); /* swzsurf */
-
- /* rankine */
- if (0x00000003 & (1 << (dev_priv->chipset & 0x0f)))
- NVOBJ_CLASS(dev, 0x0397, GR);
- else
- if (0x00000010 & (1 << (dev_priv->chipset & 0x0f)))
- NVOBJ_CLASS(dev, 0x0697, GR);
- else
- if (0x000001e0 & (1 << (dev_priv->chipset & 0x0f)))
- NVOBJ_CLASS(dev, 0x0497, GR);
-
- /* nvsw */
- NVOBJ_CLASS(dev, 0x506e, SW);
- NVOBJ_MTHD (dev, 0x506e, 0x0500, nv04_graph_mthd_page_flip);
-
- dev_priv->engine.graph.registered = true;
+ nv20_graph_unload_context(dev);
+ nv_wr32(dev, NV03_PGRAPH_INTR_EN, 0x00000000);
return 0;
}
@@ -897,3 +701,135 @@
}
}
}
+
+static void
+nv20_graph_destroy(struct drm_device *dev, int engine)
+{
+ struct nv20_graph_engine *pgraph = nv_engine(dev, engine);
+
+ nouveau_irq_unregister(dev, 12);
+ nouveau_gpuobj_ref(NULL, &pgraph->ctxtab);
+
+ NVOBJ_ENGINE_DEL(dev, GR);
+ kfree(pgraph);
+}
+
+int
+nv20_graph_create(struct drm_device *dev)
+{
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+ struct nv20_graph_engine *pgraph;
+ int ret;
+
+ pgraph = kzalloc(sizeof(*pgraph), GFP_KERNEL);
+ if (!pgraph)
+ return -ENOMEM;
+
+ pgraph->base.destroy = nv20_graph_destroy;
+ pgraph->base.fini = nv20_graph_fini;
+ pgraph->base.context_new = nv20_graph_context_new;
+ pgraph->base.context_del = nv20_graph_context_del;
+ pgraph->base.object_new = nv04_graph_object_new;
+ pgraph->base.set_tile_region = nv20_graph_set_tile_region;
+
+ pgraph->grctx_user = 0x0028;
+ if (dev_priv->card_type == NV_20) {
+ pgraph->base.init = nv20_graph_init;
+ switch (dev_priv->chipset) {
+ case 0x20:
+ pgraph->grctx_init = nv20_graph_context_init;
+ pgraph->grctx_size = NV20_GRCTX_SIZE;
+ pgraph->grctx_user = 0x0000;
+ break;
+ case 0x25:
+ case 0x28:
+ pgraph->grctx_init = nv25_graph_context_init;
+ pgraph->grctx_size = NV25_GRCTX_SIZE;
+ break;
+ case 0x2a:
+ pgraph->grctx_init = nv2a_graph_context_init;
+ pgraph->grctx_size = NV2A_GRCTX_SIZE;
+ pgraph->grctx_user = 0x0000;
+ break;
+ default:
+ NV_ERROR(dev, "PGRAPH: unknown chipset\n");
+ return 0;
+ }
+ } else {
+ pgraph->base.init = nv30_graph_init;
+ switch (dev_priv->chipset) {
+ case 0x30:
+ case 0x31:
+ pgraph->grctx_init = nv30_31_graph_context_init;
+ pgraph->grctx_size = NV30_31_GRCTX_SIZE;
+ break;
+ case 0x34:
+ pgraph->grctx_init = nv34_graph_context_init;
+ pgraph->grctx_size = NV34_GRCTX_SIZE;
+ break;
+ case 0x35:
+ case 0x36:
+ pgraph->grctx_init = nv35_36_graph_context_init;
+ pgraph->grctx_size = NV35_36_GRCTX_SIZE;
+ break;
+ default:
+ NV_ERROR(dev, "PGRAPH: unknown chipset\n");
+ return 0;
+ }
+ }
+
+ /* Create Context Pointer Table */
+ ret = nouveau_gpuobj_new(dev, NULL, 32 * 4, 16, NVOBJ_FLAG_ZERO_ALLOC,
+ &pgraph->ctxtab);
+ if (ret) {
+ kfree(pgraph);
+ return ret;
+ }
+
+ NVOBJ_ENGINE_ADD(dev, GR, &pgraph->base);
+ nouveau_irq_register(dev, 12, nv20_graph_isr);
+
+ /* nvsw */
+ NVOBJ_CLASS(dev, 0x506e, SW);
+ NVOBJ_MTHD (dev, 0x506e, 0x0500, nv04_graph_mthd_page_flip);
+
+ NVOBJ_CLASS(dev, 0x0030, GR); /* null */
+ NVOBJ_CLASS(dev, 0x0039, GR); /* m2mf */
+ NVOBJ_CLASS(dev, 0x004a, GR); /* gdirect */
+ NVOBJ_CLASS(dev, 0x009f, GR); /* imageblit (nv12) */
+ NVOBJ_CLASS(dev, 0x008a, GR); /* ifc */
+ NVOBJ_CLASS(dev, 0x0089, GR); /* sifm */
+ NVOBJ_CLASS(dev, 0x0062, GR); /* surf2d */
+ NVOBJ_CLASS(dev, 0x0043, GR); /* rop */
+ NVOBJ_CLASS(dev, 0x0012, GR); /* beta1 */
+ NVOBJ_CLASS(dev, 0x0072, GR); /* beta4 */
+ NVOBJ_CLASS(dev, 0x0019, GR); /* cliprect */
+ NVOBJ_CLASS(dev, 0x0044, GR); /* pattern */
+ if (dev_priv->card_type == NV_20) {
+ NVOBJ_CLASS(dev, 0x009e, GR); /* swzsurf */
+ NVOBJ_CLASS(dev, 0x0096, GR); /* celcius */
+
+ /* kelvin */
+ if (dev_priv->chipset < 0x25)
+ NVOBJ_CLASS(dev, 0x0097, GR);
+ else
+ NVOBJ_CLASS(dev, 0x0597, GR);
+ } else {
+ NVOBJ_CLASS(dev, 0x038a, GR); /* ifc (nv30) */
+ NVOBJ_CLASS(dev, 0x0389, GR); /* sifm (nv30) */
+ NVOBJ_CLASS(dev, 0x0362, GR); /* surf2d (nv30) */
+ NVOBJ_CLASS(dev, 0x039e, GR); /* swzsurf */
+
+ /* rankine */
+ if (0x00000003 & (1 << (dev_priv->chipset & 0x0f)))
+ NVOBJ_CLASS(dev, 0x0397, GR);
+ else
+ if (0x00000010 & (1 << (dev_priv->chipset & 0x0f)))
+ NVOBJ_CLASS(dev, 0x0697, GR);
+ else
+ if (0x000001e0 & (1 << (dev_priv->chipset & 0x0f)))
+ NVOBJ_CLASS(dev, 0x0497, GR);
+ }
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/nouveau/nv40_fifo.c b/drivers/gpu/drm/nouveau/nv40_fifo.c
index 49b9a35..68cb2d9 100644
--- a/drivers/gpu/drm/nouveau/nv40_fifo.c
+++ b/drivers/gpu/drm/nouveau/nv40_fifo.c
@@ -115,6 +115,7 @@
nv_wr32(dev, 0x32e8, nv_ri32(dev, fc + 68));
nv_wr32(dev, 0x2088, nv_ri32(dev, fc + 76));
nv_wr32(dev, 0x3300, nv_ri32(dev, fc + 80));
+ nv_wr32(dev, 0x330c, nv_ri32(dev, fc + 84));
nv_wr32(dev, NV03_PFIFO_CACHE1_GET, 0);
nv_wr32(dev, NV03_PFIFO_CACHE1_PUT, 0);
@@ -186,6 +187,7 @@
tmp |= (nv_rd32(dev, NV04_PFIFO_CACHE1_PUT) << 16);
nv_wi32(dev, fc + 72, tmp);
#endif
+ nv_wi32(dev, fc + 84, nv_rd32(dev, 0x330c));
nv40_fifo_do_load_context(dev, pfifo->channels - 1);
nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1,
diff --git a/drivers/gpu/drm/nouveau/nv40_graph.c b/drivers/gpu/drm/nouveau/nv40_graph.c
index fceb44c..5beb01b 100644
--- a/drivers/gpu/drm/nouveau/nv40_graph.c
+++ b/drivers/gpu/drm/nouveau/nv40_graph.c
@@ -28,14 +28,18 @@
#include "drm.h"
#include "nouveau_drv.h"
#include "nouveau_grctx.h"
+#include "nouveau_ramht.h"
-static int nv40_graph_register(struct drm_device *);
-static void nv40_graph_isr(struct drm_device *);
+struct nv40_graph_engine {
+ struct nouveau_exec_engine base;
+ u32 grctx_size;
+};
-struct nouveau_channel *
+static struct nouveau_channel *
nv40_graph_channel(struct drm_device *dev)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
+ struct nouveau_gpuobj *grctx;
uint32_t inst;
int i;
@@ -45,74 +49,17 @@
inst = (inst & NV40_PGRAPH_CTXCTL_CUR_INSTANCE) << 4;
for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
- struct nouveau_channel *chan = dev_priv->channels.ptr[i];
+ if (!dev_priv->channels.ptr[i])
+ continue;
- if (chan && chan->ramin_grctx &&
- chan->ramin_grctx->pinst == inst)
- return chan;
+ grctx = dev_priv->channels.ptr[i]->engctx[NVOBJ_ENGINE_GR];
+ if (grctx && grctx->pinst == inst)
+ return dev_priv->channels.ptr[i];
}
return NULL;
}
-int
-nv40_graph_create_context(struct nouveau_channel *chan)
-{
- struct drm_device *dev = chan->dev;
- struct drm_nouveau_private *dev_priv = dev->dev_private;
- struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
- struct nouveau_grctx ctx = {};
- unsigned long flags;
- int ret;
-
- ret = nouveau_gpuobj_new(dev, chan, pgraph->grctx_size, 16,
- NVOBJ_FLAG_ZERO_ALLOC, &chan->ramin_grctx);
- if (ret)
- return ret;
-
- /* Initialise default context values */
- ctx.dev = chan->dev;
- ctx.mode = NOUVEAU_GRCTX_VALS;
- ctx.data = chan->ramin_grctx;
- nv40_grctx_init(&ctx);
-
- nv_wo32(chan->ramin_grctx, 0, chan->ramin_grctx->pinst);
-
- /* init grctx pointer in ramfc, and on PFIFO if channel is
- * already active there
- */
- spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
- nv_wo32(chan->ramfc, 0x38, chan->ramin_grctx->pinst >> 4);
- nv_mask(dev, 0x002500, 0x00000001, 0x00000000);
- if ((nv_rd32(dev, 0x003204) & 0x0000001f) == chan->id)
- nv_wr32(dev, 0x0032e0, chan->ramin_grctx->pinst >> 4);
- nv_mask(dev, 0x002500, 0x00000001, 0x00000001);
- spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
- return 0;
-}
-
-void
-nv40_graph_destroy_context(struct nouveau_channel *chan)
-{
- struct drm_device *dev = chan->dev;
- struct drm_nouveau_private *dev_priv = dev->dev_private;
- struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
- unsigned long flags;
-
- spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
- pgraph->fifo_access(dev, false);
-
- /* Unload the context if it's the currently active one */
- if (pgraph->channel(dev) == chan)
- pgraph->unload_context(dev);
-
- pgraph->fifo_access(dev, true);
- spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
-
- /* Free the context resources */
- nouveau_gpuobj_ref(NULL, &chan->ramin_grctx);
-}
-
static int
nv40_graph_transfer_context(struct drm_device *dev, uint32_t inst, int save)
{
@@ -154,40 +101,7 @@
return 0;
}
-/* Restore the context for a specific channel into PGRAPH */
-int
-nv40_graph_load_context(struct nouveau_channel *chan)
-{
- struct drm_device *dev = chan->dev;
- uint32_t inst;
- int ret;
-
- if (!chan->ramin_grctx)
- return -EINVAL;
- inst = chan->ramin_grctx->pinst >> 4;
-
- ret = nv40_graph_transfer_context(dev, inst, 0);
- if (ret)
- return ret;
-
- /* 0x40032C, no idea of it's exact function. Could simply be a
- * record of the currently active PGRAPH context. It's currently
- * unknown as to what bit 24 does. The nv ddx has it set, so we will
- * set it here too.
- */
- nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
- nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR,
- (inst & NV40_PGRAPH_CTXCTL_CUR_INSTANCE) |
- NV40_PGRAPH_CTXCTL_CUR_LOADED);
- /* 0x32E0 records the instance address of the active FIFO's PGRAPH
- * context. If at any time this doesn't match 0x40032C, you will
- * receive PGRAPH_INTR_CONTEXT_SWITCH
- */
- nv_wr32(dev, NV40_PFIFO_GRCTX_INSTANCE, inst);
- return 0;
-}
-
-int
+static int
nv40_graph_unload_context(struct drm_device *dev)
{
uint32_t inst;
@@ -204,7 +118,98 @@
return ret;
}
-void
+static int
+nv40_graph_context_new(struct nouveau_channel *chan, int engine)
+{
+ struct nv40_graph_engine *pgraph = nv_engine(chan->dev, engine);
+ struct drm_device *dev = chan->dev;
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+ struct nouveau_gpuobj *grctx = NULL;
+ struct nouveau_grctx ctx = {};
+ unsigned long flags;
+ int ret;
+
+ ret = nouveau_gpuobj_new(dev, NULL, pgraph->grctx_size, 16,
+ NVOBJ_FLAG_ZERO_ALLOC, &grctx);
+ if (ret)
+ return ret;
+
+ /* Initialise default context values */
+ ctx.dev = chan->dev;
+ ctx.mode = NOUVEAU_GRCTX_VALS;
+ ctx.data = grctx;
+ nv40_grctx_init(&ctx);
+
+ nv_wo32(grctx, 0, grctx->vinst);
+
+ /* init grctx pointer in ramfc, and on PFIFO if channel is
+ * already active there
+ */
+ spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
+ nv_wo32(chan->ramfc, 0x38, grctx->vinst >> 4);
+ nv_mask(dev, 0x002500, 0x00000001, 0x00000000);
+ if ((nv_rd32(dev, 0x003204) & 0x0000001f) == chan->id)
+ nv_wr32(dev, 0x0032e0, grctx->vinst >> 4);
+ nv_mask(dev, 0x002500, 0x00000001, 0x00000001);
+ spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
+
+ chan->engctx[engine] = grctx;
+ return 0;
+}
+
+static void
+nv40_graph_context_del(struct nouveau_channel *chan, int engine)
+{
+ struct nouveau_gpuobj *grctx = chan->engctx[engine];
+ struct drm_device *dev = chan->dev;
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+ unsigned long flags;
+
+ spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
+ nv04_graph_fifo_access(dev, false);
+
+ /* Unload the context if it's the currently active one */
+ if (nv40_graph_channel(dev) == chan)
+ nv40_graph_unload_context(dev);
+
+ nv04_graph_fifo_access(dev, true);
+ spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
+
+ /* Free the context resources */
+ nouveau_gpuobj_ref(NULL, &grctx);
+ chan->engctx[engine] = NULL;
+}
+
+int
+nv40_graph_object_new(struct nouveau_channel *chan, int engine,
+ u32 handle, u16 class)
+{
+ struct drm_device *dev = chan->dev;
+ struct nouveau_gpuobj *obj = NULL;
+ int ret;
+
+ ret = nouveau_gpuobj_new(dev, chan, 20, 16, NVOBJ_FLAG_ZERO_FREE, &obj);
+ if (ret)
+ return ret;
+ obj->engine = 1;
+ obj->class = class;
+
+ nv_wo32(obj, 0x00, class);
+ nv_wo32(obj, 0x04, 0x00000000);
+#ifndef __BIG_ENDIAN
+ nv_wo32(obj, 0x08, 0x00000000);
+#else
+ nv_wo32(obj, 0x08, 0x01000000);
+#endif
+ nv_wo32(obj, 0x0c, 0x00000000);
+ nv_wo32(obj, 0x10, 0x00000000);
+
+ ret = nouveau_ramht_insert(chan, handle, obj);
+ nouveau_gpuobj_ref(NULL, &obj);
+ return ret;
+}
+
+static void
nv40_graph_set_tile_region(struct drm_device *dev, int i)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
@@ -257,14 +262,14 @@
* C51 0x4e
*/
int
-nv40_graph_init(struct drm_device *dev)
+nv40_graph_init(struct drm_device *dev, int engine)
{
- struct drm_nouveau_private *dev_priv =
- (struct drm_nouveau_private *)dev->dev_private;
+ struct nv40_graph_engine *pgraph = nv_engine(dev, engine);
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
struct nouveau_grctx ctx = {};
uint32_t vramsz, *cp;
- int ret, i, j;
+ int i, j;
nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) &
~NV_PMC_ENABLE_PGRAPH);
@@ -280,7 +285,7 @@
ctx.data = cp;
ctx.ctxprog_max = 256;
nv40_grctx_init(&ctx);
- dev_priv->engine.graph.grctx_size = ctx.ctxvals_pos * 4;
+ pgraph->grctx_size = ctx.ctxvals_pos * 4;
nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
for (i = 0; i < ctx.ctxprog_len; i++)
@@ -288,14 +293,9 @@
kfree(cp);
- ret = nv40_graph_register(dev);
- if (ret)
- return ret;
-
/* No context present currently */
nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0x00000000);
- nouveau_irq_register(dev, 12, nv40_graph_isr);
nv_wr32(dev, NV03_PGRAPH_INTR , 0xFFFFFFFF);
nv_wr32(dev, NV40_PGRAPH_INTR_EN, 0xFFFFFFFF);
@@ -428,47 +428,10 @@
return 0;
}
-void nv40_graph_takedown(struct drm_device *dev)
-{
- nouveau_irq_unregister(dev, 12);
-}
-
static int
-nv40_graph_register(struct drm_device *dev)
+nv40_graph_fini(struct drm_device *dev, int engine)
{
- struct drm_nouveau_private *dev_priv = dev->dev_private;
-
- if (dev_priv->engine.graph.registered)
- return 0;
-
- NVOBJ_CLASS(dev, 0x506e, SW); /* nvsw */
- NVOBJ_CLASS(dev, 0x0030, GR); /* null */
- NVOBJ_CLASS(dev, 0x0039, GR); /* m2mf */
- NVOBJ_CLASS(dev, 0x004a, GR); /* gdirect */
- NVOBJ_CLASS(dev, 0x009f, GR); /* imageblit (nv12) */
- NVOBJ_CLASS(dev, 0x008a, GR); /* ifc */
- NVOBJ_CLASS(dev, 0x0089, GR); /* sifm */
- NVOBJ_CLASS(dev, 0x3089, GR); /* sifm (nv40) */
- NVOBJ_CLASS(dev, 0x0062, GR); /* surf2d */
- NVOBJ_CLASS(dev, 0x3062, GR); /* surf2d (nv40) */
- NVOBJ_CLASS(dev, 0x0043, GR); /* rop */
- NVOBJ_CLASS(dev, 0x0012, GR); /* beta1 */
- NVOBJ_CLASS(dev, 0x0072, GR); /* beta4 */
- NVOBJ_CLASS(dev, 0x0019, GR); /* cliprect */
- NVOBJ_CLASS(dev, 0x0044, GR); /* pattern */
- NVOBJ_CLASS(dev, 0x309e, GR); /* swzsurf */
-
- /* curie */
- if (nv44_graph_class(dev))
- NVOBJ_CLASS(dev, 0x4497, GR);
- else
- NVOBJ_CLASS(dev, 0x4097, GR);
-
- /* nvsw */
- NVOBJ_CLASS(dev, 0x506e, SW);
- NVOBJ_MTHD (dev, 0x506e, 0x0500, nv04_graph_mthd_page_flip);
-
- dev_priv->engine.graph.registered = true;
+ nv40_graph_unload_context(dev);
return 0;
}
@@ -476,17 +439,17 @@
nv40_graph_isr_chid(struct drm_device *dev, u32 inst)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
- struct nouveau_channel *chan;
+ struct nouveau_gpuobj *grctx;
unsigned long flags;
int i;
spin_lock_irqsave(&dev_priv->channels.lock, flags);
for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
- chan = dev_priv->channels.ptr[i];
- if (!chan || !chan->ramin_grctx)
+ if (!dev_priv->channels.ptr[i])
continue;
+ grctx = dev_priv->channels.ptr[i]->engctx[NVOBJ_ENGINE_GR];
- if (inst == chan->ramin_grctx->pinst)
+ if (grctx && grctx->pinst == inst)
break;
}
spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
@@ -537,3 +500,63 @@
}
}
}
+
+static void
+nv40_graph_destroy(struct drm_device *dev, int engine)
+{
+ struct nv40_graph_engine *pgraph = nv_engine(dev, engine);
+
+ nouveau_irq_unregister(dev, 12);
+
+ NVOBJ_ENGINE_DEL(dev, GR);
+ kfree(pgraph);
+}
+
+int
+nv40_graph_create(struct drm_device *dev)
+{
+ struct nv40_graph_engine *pgraph;
+
+ pgraph = kzalloc(sizeof(*pgraph), GFP_KERNEL);
+ if (!pgraph)
+ return -ENOMEM;
+
+ pgraph->base.destroy = nv40_graph_destroy;
+ pgraph->base.init = nv40_graph_init;
+ pgraph->base.fini = nv40_graph_fini;
+ pgraph->base.context_new = nv40_graph_context_new;
+ pgraph->base.context_del = nv40_graph_context_del;
+ pgraph->base.object_new = nv40_graph_object_new;
+ pgraph->base.set_tile_region = nv40_graph_set_tile_region;
+
+ NVOBJ_ENGINE_ADD(dev, GR, &pgraph->base);
+ nouveau_irq_register(dev, 12, nv40_graph_isr);
+
+ NVOBJ_CLASS(dev, 0x506e, SW); /* nvsw */
+ NVOBJ_CLASS(dev, 0x0030, GR); /* null */
+ NVOBJ_CLASS(dev, 0x0039, GR); /* m2mf */
+ NVOBJ_CLASS(dev, 0x004a, GR); /* gdirect */
+ NVOBJ_CLASS(dev, 0x009f, GR); /* imageblit (nv12) */
+ NVOBJ_CLASS(dev, 0x008a, GR); /* ifc */
+ NVOBJ_CLASS(dev, 0x0089, GR); /* sifm */
+ NVOBJ_CLASS(dev, 0x3089, GR); /* sifm (nv40) */
+ NVOBJ_CLASS(dev, 0x0062, GR); /* surf2d */
+ NVOBJ_CLASS(dev, 0x3062, GR); /* surf2d (nv40) */
+ NVOBJ_CLASS(dev, 0x0043, GR); /* rop */
+ NVOBJ_CLASS(dev, 0x0012, GR); /* beta1 */
+ NVOBJ_CLASS(dev, 0x0072, GR); /* beta4 */
+ NVOBJ_CLASS(dev, 0x0019, GR); /* cliprect */
+ NVOBJ_CLASS(dev, 0x0044, GR); /* pattern */
+ NVOBJ_CLASS(dev, 0x309e, GR); /* swzsurf */
+
+ /* curie */
+ if (nv44_graph_class(dev))
+ NVOBJ_CLASS(dev, 0x4497, GR);
+ else
+ NVOBJ_CLASS(dev, 0x4097, GR);
+
+ /* nvsw */
+ NVOBJ_CLASS(dev, 0x506e, SW);
+ NVOBJ_MTHD (dev, 0x506e, 0x0500, nv04_graph_mthd_page_flip);
+ return 0;
+}
diff --git a/drivers/gpu/drm/nouveau/nv40_mpeg.c b/drivers/gpu/drm/nouveau/nv40_mpeg.c
new file mode 100644
index 0000000..6d2af29
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nv40_mpeg.c
@@ -0,0 +1,311 @@
+/*
+ * Copyright 2011 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs
+ */
+
+#include "drmP.h"
+#include "nouveau_drv.h"
+#include "nouveau_ramht.h"
+
+struct nv40_mpeg_engine {
+ struct nouveau_exec_engine base;
+};
+
+static int
+nv40_mpeg_context_new(struct nouveau_channel *chan, int engine)
+{
+ struct drm_device *dev = chan->dev;
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+ struct nouveau_gpuobj *ctx = NULL;
+ unsigned long flags;
+ int ret;
+
+ NV_DEBUG(dev, "ch%d\n", chan->id);
+
+ ret = nouveau_gpuobj_new(dev, NULL, 264 * 4, 16, NVOBJ_FLAG_ZERO_ALLOC |
+ NVOBJ_FLAG_ZERO_FREE, &ctx);
+ if (ret)
+ return ret;
+
+ nv_wo32(ctx, 0x78, 0x02001ec1);
+
+ spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
+ nv_mask(dev, 0x002500, 0x00000001, 0x00000000);
+ if ((nv_rd32(dev, 0x003204) & 0x1f) == chan->id)
+ nv_wr32(dev, 0x00330c, ctx->pinst >> 4);
+ nv_wo32(chan->ramfc, 0x54, ctx->pinst >> 4);
+ nv_mask(dev, 0x002500, 0x00000001, 0x00000001);
+ spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
+
+ chan->engctx[engine] = ctx;
+ return 0;
+}
+
+static void
+nv40_mpeg_context_del(struct nouveau_channel *chan, int engine)
+{
+ struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
+ struct nouveau_gpuobj *ctx = chan->engctx[engine];
+ struct drm_device *dev = chan->dev;
+ unsigned long flags;
+ u32 inst = 0x80000000 | (ctx->pinst >> 4);
+
+ spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
+ nv_mask(dev, 0x00b32c, 0x00000001, 0x00000000);
+ if (nv_rd32(dev, 0x00b318) == inst)
+ nv_mask(dev, 0x00b318, 0x80000000, 0x00000000);
+ nv_mask(dev, 0x00b32c, 0x00000001, 0x00000001);
+ spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
+
+ nouveau_gpuobj_ref(NULL, &ctx);
+ chan->engctx[engine] = NULL;
+}
+
+static int
+nv40_mpeg_object_new(struct nouveau_channel *chan, int engine,
+ u32 handle, u16 class)
+{
+ struct drm_device *dev = chan->dev;
+ struct nouveau_gpuobj *obj = NULL;
+ int ret;
+
+ ret = nouveau_gpuobj_new(dev, chan, 20, 16, NVOBJ_FLAG_ZERO_ALLOC |
+ NVOBJ_FLAG_ZERO_FREE, &obj);
+ if (ret)
+ return ret;
+ obj->engine = 2;
+ obj->class = class;
+
+ nv_wo32(obj, 0x00, class);
+
+ ret = nouveau_ramht_insert(chan, handle, obj);
+ nouveau_gpuobj_ref(NULL, &obj);
+ return ret;
+}
+
+static int
+nv40_mpeg_init(struct drm_device *dev, int engine)
+{
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+ struct nv40_mpeg_engine *pmpeg = nv_engine(dev, engine);
+ int i;
+
+ /* VPE init */
+ nv_mask(dev, 0x000200, 0x00000002, 0x00000000);
+ nv_mask(dev, 0x000200, 0x00000002, 0x00000002);
+ nv_wr32(dev, 0x00b0e0, 0x00000020); /* nvidia: rd 0x01, wr 0x20 */
+ nv_wr32(dev, 0x00b0e8, 0x00000020); /* nvidia: rd 0x01, wr 0x20 */
+
+ for (i = 0; i < dev_priv->engine.fb.num_tiles; i++)
+ pmpeg->base.set_tile_region(dev, i);
+
+ /* PMPEG init */
+ nv_wr32(dev, 0x00b32c, 0x00000000);
+ nv_wr32(dev, 0x00b314, 0x00000100);
+ nv_wr32(dev, 0x00b220, 0x00000044);
+ nv_wr32(dev, 0x00b300, 0x02001ec1);
+ nv_mask(dev, 0x00b32c, 0x00000001, 0x00000001);
+
+ nv_wr32(dev, 0x00b100, 0xffffffff);
+ nv_wr32(dev, 0x00b140, 0xffffffff);
+
+ if (!nv_wait(dev, 0x00b200, 0x00000001, 0x00000000)) {
+ NV_ERROR(dev, "PMPEG init: 0x%08x\n", nv_rd32(dev, 0x00b200));
+ return -EBUSY;
+ }
+
+ return 0;
+}
+
+static int
+nv40_mpeg_fini(struct drm_device *dev, int engine)
+{
+ /*XXX: context save? */
+ nv_mask(dev, 0x00b32c, 0x00000001, 0x00000000);
+ nv_wr32(dev, 0x00b140, 0x00000000);
+ return 0;
+}
+
+static int
+nv40_mpeg_mthd_dma(struct nouveau_channel *chan, u32 class, u32 mthd, u32 data)
+{
+ struct drm_device *dev = chan->dev;
+ u32 inst = data << 4;
+ u32 dma0 = nv_ri32(dev, inst + 0);
+ u32 dma1 = nv_ri32(dev, inst + 4);
+ u32 dma2 = nv_ri32(dev, inst + 8);
+ u32 base = (dma2 & 0xfffff000) | (dma0 >> 20);
+ u32 size = dma1 + 1;
+
+ /* only allow linear DMA objects */
+ if (!(dma0 & 0x00002000))
+ return -EINVAL;
+
+ if (mthd == 0x0190) {
+ /* DMA_CMD */
+ nv_mask(dev, 0x00b300, 0x00030000, (dma0 & 0x00030000));
+ nv_wr32(dev, 0x00b334, base);
+ nv_wr32(dev, 0x00b324, size);
+ } else
+ if (mthd == 0x01a0) {
+ /* DMA_DATA */
+ nv_mask(dev, 0x00b300, 0x000c0000, (dma0 & 0x00030000) << 2);
+ nv_wr32(dev, 0x00b360, base);
+ nv_wr32(dev, 0x00b364, size);
+ } else {
+ /* DMA_IMAGE, VRAM only */
+ if (dma0 & 0x000c0000)
+ return -EINVAL;
+
+ nv_wr32(dev, 0x00b370, base);
+ nv_wr32(dev, 0x00b374, size);
+ }
+
+ return 0;
+}
+
+static int
+nv40_mpeg_isr_chid(struct drm_device *dev, u32 inst)
+{
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+ struct nouveau_gpuobj *ctx;
+ unsigned long flags;
+ int i;
+
+ spin_lock_irqsave(&dev_priv->channels.lock, flags);
+ for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
+ if (!dev_priv->channels.ptr[i])
+ continue;
+
+ ctx = dev_priv->channels.ptr[i]->engctx[NVOBJ_ENGINE_MPEG];
+ if (ctx && ctx->pinst == inst)
+ break;
+ }
+ spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
+ return i;
+}
+
+static void
+nv40_vpe_set_tile_region(struct drm_device *dev, int i)
+{
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+ struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
+
+ nv_wr32(dev, 0x00b008 + (i * 0x10), tile->pitch);
+ nv_wr32(dev, 0x00b004 + (i * 0x10), tile->limit);
+ nv_wr32(dev, 0x00b000 + (i * 0x10), tile->addr);
+}
+
+static void
+nv40_mpeg_isr(struct drm_device *dev)
+{
+ u32 inst = (nv_rd32(dev, 0x00b318) & 0x000fffff) << 4;
+ u32 chid = nv40_mpeg_isr_chid(dev, inst);
+ u32 stat = nv_rd32(dev, 0x00b100);
+ u32 type = nv_rd32(dev, 0x00b230);
+ u32 mthd = nv_rd32(dev, 0x00b234);
+ u32 data = nv_rd32(dev, 0x00b238);
+ u32 show = stat;
+
+ if (stat & 0x01000000) {
+ /* happens on initial binding of the object */
+ if (type == 0x00000020 && mthd == 0x0000) {
+ nv_mask(dev, 0x00b308, 0x00000000, 0x00000000);
+ show &= ~0x01000000;
+ }
+
+ if (type == 0x00000010) {
+ if (!nouveau_gpuobj_mthd_call2(dev, chid, 0x3174, mthd, data))
+ show &= ~0x01000000;
+ }
+ }
+
+ nv_wr32(dev, 0x00b100, stat);
+ nv_wr32(dev, 0x00b230, 0x00000001);
+
+ if (show && nouveau_ratelimit()) {
+ NV_INFO(dev, "PMPEG: Ch %d [0x%08x] 0x%08x 0x%08x 0x%08x 0x%08x\n",
+ chid, inst, stat, type, mthd, data);
+ }
+}
+
+static void
+nv40_vpe_isr(struct drm_device *dev)
+{
+ if (nv_rd32(dev, 0x00b100))
+ nv40_mpeg_isr(dev);
+
+ if (nv_rd32(dev, 0x00b800)) {
+ u32 stat = nv_rd32(dev, 0x00b800);
+ NV_INFO(dev, "PMSRCH: 0x%08x\n", stat);
+ nv_wr32(dev, 0xb800, stat);
+ }
+}
+
+static void
+nv40_mpeg_destroy(struct drm_device *dev, int engine)
+{
+ struct nv40_mpeg_engine *pmpeg = nv_engine(dev, engine);
+
+ nouveau_irq_unregister(dev, 0);
+
+ NVOBJ_ENGINE_DEL(dev, MPEG);
+ kfree(pmpeg);
+}
+
+int
+nv40_mpeg_create(struct drm_device *dev)
+{
+ struct nv40_mpeg_engine *pmpeg;
+
+ pmpeg = kzalloc(sizeof(*pmpeg), GFP_KERNEL);
+ if (!pmpeg)
+ return -ENOMEM;
+
+ pmpeg->base.destroy = nv40_mpeg_destroy;
+ pmpeg->base.init = nv40_mpeg_init;
+ pmpeg->base.fini = nv40_mpeg_fini;
+ pmpeg->base.context_new = nv40_mpeg_context_new;
+ pmpeg->base.context_del = nv40_mpeg_context_del;
+ pmpeg->base.object_new = nv40_mpeg_object_new;
+
+ /* ISR vector, PMC_ENABLE bit, and TILE regs are shared between
+ * all VPE engines, for this driver's purposes the PMPEG engine
+ * will be treated as the "master" and handle the global VPE
+ * bits too
+ */
+ pmpeg->base.set_tile_region = nv40_vpe_set_tile_region;
+ nouveau_irq_register(dev, 0, nv40_vpe_isr);
+
+ NVOBJ_ENGINE_ADD(dev, MPEG, &pmpeg->base);
+ NVOBJ_CLASS(dev, 0x3174, MPEG);
+ NVOBJ_MTHD (dev, 0x3174, 0x0190, nv40_mpeg_mthd_dma);
+ NVOBJ_MTHD (dev, 0x3174, 0x01a0, nv40_mpeg_mthd_dma);
+ NVOBJ_MTHD (dev, 0x3174, 0x01b0, nv40_mpeg_mthd_dma);
+
+#if 0
+ NVOBJ_ENGINE_ADD(dev, ME, &pme->base);
+ NVOBJ_CLASS(dev, 0x4075, ME);
+#endif
+ return 0;
+
+}
diff --git a/drivers/gpu/drm/nouveau/nv50_calc.c b/drivers/gpu/drm/nouveau/nv50_calc.c
index de81151..8cf63a8 100644
--- a/drivers/gpu/drm/nouveau/nv50_calc.c
+++ b/drivers/gpu/drm/nouveau/nv50_calc.c
@@ -23,7 +23,6 @@
*/
#include "drmP.h"
-#include "drm_fixed.h"
#include "nouveau_drv.h"
#include "nouveau_hw.h"
@@ -47,45 +46,52 @@
}
int
-nv50_calc_pll2(struct drm_device *dev, struct pll_lims *pll, int clk,
- int *N, int *fN, int *M, int *P)
+nva3_calc_pll(struct drm_device *dev, struct pll_lims *pll, int clk,
+ int *pN, int *pfN, int *pM, int *P)
{
- fixed20_12 fb_div, a, b;
- u32 refclk = pll->refclk / 10;
- u32 max_vco_freq = pll->vco1.maxfreq / 10;
- u32 max_vco_inputfreq = pll->vco1.max_inputfreq / 10;
- clk /= 10;
+ u32 best_err = ~0, err;
+ int M, lM, hM, N, fN;
- *P = max_vco_freq / clk;
+ *P = pll->vco1.maxfreq / clk;
if (*P > pll->max_p)
*P = pll->max_p;
if (*P < pll->min_p)
*P = pll->min_p;
- /* *M = floor((refclk + max_vco_inputfreq) / max_vco_inputfreq); */
- a.full = dfixed_const(refclk + max_vco_inputfreq);
- b.full = dfixed_const(max_vco_inputfreq);
- a.full = dfixed_div(a, b);
- a.full = dfixed_floor(a);
- *M = dfixed_trunc(a);
+ lM = (pll->refclk + pll->vco1.max_inputfreq) / pll->vco1.max_inputfreq;
+ lM = max(lM, (int)pll->vco1.min_m);
+ hM = (pll->refclk + pll->vco1.min_inputfreq) / pll->vco1.min_inputfreq;
+ hM = min(hM, (int)pll->vco1.max_m);
- /* fb_div = (vco * *M) / refclk; */
- fb_div.full = dfixed_const(clk * *P);
- fb_div.full = dfixed_mul(fb_div, a);
- a.full = dfixed_const(refclk);
- fb_div.full = dfixed_div(fb_div, a);
+ for (M = lM; M <= hM; M++) {
+ u32 tmp = clk * *P * M;
+ N = tmp / pll->refclk;
+ fN = tmp % pll->refclk;
+ if (!pfN && fN >= pll->refclk / 2)
+ N++;
- /* *N = floor(fb_div); */
- a.full = dfixed_floor(fb_div);
- *N = dfixed_trunc(fb_div);
+ if (N < pll->vco1.min_n)
+ continue;
+ if (N > pll->vco1.max_n)
+ break;
- /* *fN = (fmod(fb_div, 1.0) * 8192) - 4096; */
- b.full = dfixed_const(8192);
- a.full = dfixed_mul(a, b);
- fb_div.full = dfixed_mul(fb_div, b);
- fb_div.full = fb_div.full - a.full;
- *fN = dfixed_trunc(fb_div) - 4096;
- *fN &= 0xffff;
+ err = abs(clk - (pll->refclk * N / M / *P));
+ if (err < best_err) {
+ best_err = err;
+ *pN = N;
+ *pM = M;
+ }
- return clk;
+ if (pfN) {
+ *pfN = (((fN << 13) / pll->refclk) - 4096) & 0xffff;
+ return clk;
+ }
+ }
+
+ if (unlikely(best_err == ~0)) {
+ NV_ERROR(dev, "unable to find matching pll values\n");
+ return -EINVAL;
+ }
+
+ return pll->refclk * *pN / *pM / *P;
}
diff --git a/drivers/gpu/drm/nouveau/nv50_crtc.c b/drivers/gpu/drm/nouveau/nv50_crtc.c
index a19ccaa..ebabacf 100644
--- a/drivers/gpu/drm/nouveau/nv50_crtc.c
+++ b/drivers/gpu/drm/nouveau/nv50_crtc.c
@@ -286,7 +286,7 @@
nv_wr32(dev, pll.reg + 8, reg2 | (P << 28) | (M2 << 16) | N2);
} else
if (dev_priv->chipset < NV_C0) {
- ret = nv50_calc_pll2(dev, &pll, pclk, &N1, &N2, &M1, &P);
+ ret = nva3_calc_pll(dev, &pll, pclk, &N1, &N2, &M1, &P);
if (ret <= 0)
return 0;
@@ -298,7 +298,7 @@
nv_wr32(dev, pll.reg + 4, reg1 | (P << 16) | (M1 << 8) | N1);
nv_wr32(dev, pll.reg + 8, N2);
} else {
- ret = nv50_calc_pll2(dev, &pll, pclk, &N1, &N2, &M1, &P);
+ ret = nva3_calc_pll(dev, &pll, pclk, &N1, &N2, &M1, &P);
if (ret <= 0)
return 0;
@@ -349,14 +349,14 @@
struct drm_gem_object *gem;
int ret = 0, i;
- if (width != 64 || height != 64)
- return -EINVAL;
-
if (!buffer_handle) {
nv_crtc->cursor.hide(nv_crtc, true);
return 0;
}
+ if (width != 64 || height != 64)
+ return -EINVAL;
+
gem = drm_gem_object_lookup(dev, file_priv, buffer_handle);
if (!gem)
return -ENOENT;
@@ -532,8 +532,7 @@
if (atomic) {
drm_fb = passed_fb;
fb = nouveau_framebuffer(passed_fb);
- }
- else {
+ } else {
/* If not atomic, we can go ahead and pin, and unpin the
* old fb we were passed.
*/
diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c
index 75a376c..74a3f68 100644
--- a/drivers/gpu/drm/nouveau/nv50_display.c
+++ b/drivers/gpu/drm/nouveau/nv50_display.c
@@ -517,13 +517,25 @@
if (bios->fp.if_is_24bit)
script |= 0x0200;
} else {
+ /* determine number of lvds links */
+ if (nv_connector && nv_connector->edid &&
+ nv_connector->dcb->type == DCB_CONNECTOR_LVDS_SPWG) {
+ /* http://www.spwg.org */
+ if (((u8 *)nv_connector->edid)[121] == 2)
+ script |= 0x0100;
+ } else
if (pxclk >= bios->fp.duallink_transition_clk) {
script |= 0x0100;
+ }
+
+ /* determine panel depth */
+ if (script & 0x0100) {
if (bios->fp.strapless_is_24bit & 2)
script |= 0x0200;
- } else
- if (bios->fp.strapless_is_24bit & 1)
- script |= 0x0200;
+ } else {
+ if (bios->fp.strapless_is_24bit & 1)
+ script |= 0x0200;
+ }
if (nv_connector && nv_connector->edid &&
(nv_connector->edid->revision >= 4) &&
diff --git a/drivers/gpu/drm/nouveau/nv50_graph.c b/drivers/gpu/drm/nouveau/nv50_graph.c
index b02a5b1..e25cbb4 100644
--- a/drivers/gpu/drm/nouveau/nv50_graph.c
+++ b/drivers/gpu/drm/nouveau/nv50_graph.c
@@ -31,10 +31,95 @@
#include "nouveau_grctx.h"
#include "nouveau_dma.h"
#include "nouveau_vm.h"
+#include "nouveau_ramht.h"
#include "nv50_evo.h"
-static int nv50_graph_register(struct drm_device *);
-static void nv50_graph_isr(struct drm_device *);
+struct nv50_graph_engine {
+ struct nouveau_exec_engine base;
+ u32 ctxprog[512];
+ u32 ctxprog_size;
+ u32 grctx_size;
+};
+
+static void
+nv50_graph_fifo_access(struct drm_device *dev, bool enabled)
+{
+ const uint32_t mask = 0x00010001;
+
+ if (enabled)
+ nv_wr32(dev, 0x400500, nv_rd32(dev, 0x400500) | mask);
+ else
+ nv_wr32(dev, 0x400500, nv_rd32(dev, 0x400500) & ~mask);
+}
+
+static struct nouveau_channel *
+nv50_graph_channel(struct drm_device *dev)
+{
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+ uint32_t inst;
+ int i;
+
+ /* Be sure we're not in the middle of a context switch or bad things
+ * will happen, such as unloading the wrong pgraph context.
+ */
+ if (!nv_wait(dev, 0x400300, 0x00000001, 0x00000000))
+ NV_ERROR(dev, "Ctxprog is still running\n");
+
+ inst = nv_rd32(dev, NV50_PGRAPH_CTXCTL_CUR);
+ if (!(inst & NV50_PGRAPH_CTXCTL_CUR_LOADED))
+ return NULL;
+ inst = (inst & NV50_PGRAPH_CTXCTL_CUR_INSTANCE) << 12;
+
+ for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
+ struct nouveau_channel *chan = dev_priv->channels.ptr[i];
+
+ if (chan && chan->ramin && chan->ramin->vinst == inst)
+ return chan;
+ }
+
+ return NULL;
+}
+
+static int
+nv50_graph_do_load_context(struct drm_device *dev, uint32_t inst)
+{
+ uint32_t fifo = nv_rd32(dev, 0x400500);
+
+ nv_wr32(dev, 0x400500, fifo & ~1);
+ nv_wr32(dev, 0x400784, inst);
+ nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) | 0x40);
+ nv_wr32(dev, 0x400320, nv_rd32(dev, 0x400320) | 0x11);
+ nv_wr32(dev, 0x400040, 0xffffffff);
+ (void)nv_rd32(dev, 0x400040);
+ nv_wr32(dev, 0x400040, 0x00000000);
+ nv_wr32(dev, 0x400304, nv_rd32(dev, 0x400304) | 1);
+
+ if (nouveau_wait_for_idle(dev))
+ nv_wr32(dev, 0x40032c, inst | (1<<31));
+ nv_wr32(dev, 0x400500, fifo);
+
+ return 0;
+}
+
+static int
+nv50_graph_unload_context(struct drm_device *dev)
+{
+ uint32_t inst;
+
+ inst = nv_rd32(dev, NV50_PGRAPH_CTXCTL_CUR);
+ if (!(inst & NV50_PGRAPH_CTXCTL_CUR_LOADED))
+ return 0;
+ inst &= NV50_PGRAPH_CTXCTL_CUR_INSTANCE;
+
+ nouveau_wait_for_idle(dev);
+ nv_wr32(dev, 0x400784, inst);
+ nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) | 0x20);
+ nv_wr32(dev, 0x400304, nv_rd32(dev, 0x400304) | 0x01);
+ nouveau_wait_for_idle(dev);
+
+ nv_wr32(dev, NV50_PGRAPH_CTXCTL_CUR, inst);
+ return 0;
+}
static void
nv50_graph_init_reset(struct drm_device *dev)
@@ -52,7 +137,6 @@
{
NV_DEBUG(dev, "\n");
- nouveau_irq_register(dev, 12, nv50_graph_isr);
nv_wr32(dev, NV03_PGRAPH_INTR, 0xffffffff);
nv_wr32(dev, 0x400138, 0xffffffff);
nv_wr32(dev, NV40_PGRAPH_INTR_EN, 0xffffffff);
@@ -135,34 +219,14 @@
static int
nv50_graph_init_ctxctl(struct drm_device *dev)
{
- struct drm_nouveau_private *dev_priv = dev->dev_private;
- struct nouveau_grctx ctx = {};
- uint32_t *cp;
+ struct nv50_graph_engine *pgraph = nv_engine(dev, NVOBJ_ENGINE_GR);
int i;
NV_DEBUG(dev, "\n");
- cp = kmalloc(512 * 4, GFP_KERNEL);
- if (!cp) {
- NV_ERROR(dev, "failed to allocate ctxprog\n");
- dev_priv->engine.graph.accel_blocked = true;
- return 0;
- }
-
- ctx.dev = dev;
- ctx.mode = NOUVEAU_GRCTX_PROG;
- ctx.data = cp;
- ctx.ctxprog_max = 512;
- if (!nv50_grctx_init(&ctx)) {
- dev_priv->engine.graph.grctx_size = ctx.ctxvals_pos * 4;
-
- nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
- for (i = 0; i < ctx.ctxprog_len; i++)
- nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, cp[i]);
- } else {
- dev_priv->engine.graph.accel_blocked = true;
- }
- kfree(cp);
+ nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
+ for (i = 0; i < pgraph->ctxprog_size; i++)
+ nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, pgraph->ctxprog[i]);
nv_wr32(dev, 0x40008c, 0x00000004); /* HW_CTX_SWITCH_ENABLED */
nv_wr32(dev, 0x400320, 4);
@@ -171,8 +235,8 @@
return 0;
}
-int
-nv50_graph_init(struct drm_device *dev)
+static int
+nv50_graph_init(struct drm_device *dev, int engine)
{
int ret;
@@ -186,105 +250,66 @@
if (ret)
return ret;
- ret = nv50_graph_register(dev);
- if (ret)
- return ret;
nv50_graph_init_intr(dev);
return 0;
}
-void
-nv50_graph_takedown(struct drm_device *dev)
+static int
+nv50_graph_fini(struct drm_device *dev, int engine)
{
NV_DEBUG(dev, "\n");
+ nv50_graph_unload_context(dev);
nv_wr32(dev, 0x40013c, 0x00000000);
- nouveau_irq_unregister(dev, 12);
+ return 0;
}
-void
-nv50_graph_fifo_access(struct drm_device *dev, bool enabled)
-{
- const uint32_t mask = 0x00010001;
-
- if (enabled)
- nv_wr32(dev, 0x400500, nv_rd32(dev, 0x400500) | mask);
- else
- nv_wr32(dev, 0x400500, nv_rd32(dev, 0x400500) & ~mask);
-}
-
-struct nouveau_channel *
-nv50_graph_channel(struct drm_device *dev)
-{
- struct drm_nouveau_private *dev_priv = dev->dev_private;
- uint32_t inst;
- int i;
-
- /* Be sure we're not in the middle of a context switch or bad things
- * will happen, such as unloading the wrong pgraph context.
- */
- if (!nv_wait(dev, 0x400300, 0x00000001, 0x00000000))
- NV_ERROR(dev, "Ctxprog is still running\n");
-
- inst = nv_rd32(dev, NV50_PGRAPH_CTXCTL_CUR);
- if (!(inst & NV50_PGRAPH_CTXCTL_CUR_LOADED))
- return NULL;
- inst = (inst & NV50_PGRAPH_CTXCTL_CUR_INSTANCE) << 12;
-
- for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
- struct nouveau_channel *chan = dev_priv->channels.ptr[i];
-
- if (chan && chan->ramin && chan->ramin->vinst == inst)
- return chan;
- }
-
- return NULL;
-}
-
-int
-nv50_graph_create_context(struct nouveau_channel *chan)
+static int
+nv50_graph_context_new(struct nouveau_channel *chan, int engine)
{
struct drm_device *dev = chan->dev;
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_gpuobj *ramin = chan->ramin;
- struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
+ struct nouveau_gpuobj *grctx = NULL;
+ struct nv50_graph_engine *pgraph = nv_engine(dev, engine);
struct nouveau_grctx ctx = {};
int hdr, ret;
NV_DEBUG(dev, "ch%d\n", chan->id);
- ret = nouveau_gpuobj_new(dev, chan, pgraph->grctx_size, 0,
+ ret = nouveau_gpuobj_new(dev, NULL, pgraph->grctx_size, 0,
NVOBJ_FLAG_ZERO_ALLOC |
- NVOBJ_FLAG_ZERO_FREE, &chan->ramin_grctx);
+ NVOBJ_FLAG_ZERO_FREE, &grctx);
if (ret)
return ret;
hdr = (dev_priv->chipset == 0x50) ? 0x200 : 0x20;
nv_wo32(ramin, hdr + 0x00, 0x00190002);
- nv_wo32(ramin, hdr + 0x04, chan->ramin_grctx->vinst +
- pgraph->grctx_size - 1);
- nv_wo32(ramin, hdr + 0x08, chan->ramin_grctx->vinst);
+ nv_wo32(ramin, hdr + 0x04, grctx->vinst + grctx->size - 1);
+ nv_wo32(ramin, hdr + 0x08, grctx->vinst);
nv_wo32(ramin, hdr + 0x0c, 0);
nv_wo32(ramin, hdr + 0x10, 0);
nv_wo32(ramin, hdr + 0x14, 0x00010000);
ctx.dev = chan->dev;
ctx.mode = NOUVEAU_GRCTX_VALS;
- ctx.data = chan->ramin_grctx;
+ ctx.data = grctx;
nv50_grctx_init(&ctx);
- nv_wo32(chan->ramin_grctx, 0x00000, chan->ramin->vinst >> 12);
+ nv_wo32(grctx, 0x00000, chan->ramin->vinst >> 12);
dev_priv->engine.instmem.flush(dev);
- atomic_inc(&chan->vm->pgraph_refs);
+
+ atomic_inc(&chan->vm->engref[NVOBJ_ENGINE_GR]);
+ chan->engctx[NVOBJ_ENGINE_GR] = grctx;
return 0;
}
-void
-nv50_graph_destroy_context(struct nouveau_channel *chan)
+static void
+nv50_graph_context_del(struct nouveau_channel *chan, int engine)
{
+ struct nouveau_gpuobj *grctx = chan->engctx[engine];
struct drm_device *dev = chan->dev;
struct drm_nouveau_private *dev_priv = dev->dev_private;
- struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
int i, hdr = (dev_priv->chipset == 0x50) ? 0x200 : 0x20;
unsigned long flags;
@@ -296,72 +321,49 @@
spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
pfifo->reassign(dev, false);
- pgraph->fifo_access(dev, false);
+ nv50_graph_fifo_access(dev, false);
- if (pgraph->channel(dev) == chan)
- pgraph->unload_context(dev);
+ if (nv50_graph_channel(dev) == chan)
+ nv50_graph_unload_context(dev);
for (i = hdr; i < hdr + 24; i += 4)
nv_wo32(chan->ramin, i, 0);
dev_priv->engine.instmem.flush(dev);
- pgraph->fifo_access(dev, true);
+ nv50_graph_fifo_access(dev, true);
pfifo->reassign(dev, true);
spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
- nouveau_gpuobj_ref(NULL, &chan->ramin_grctx);
+ nouveau_gpuobj_ref(NULL, &grctx);
- atomic_dec(&chan->vm->pgraph_refs);
+ atomic_dec(&chan->vm->engref[engine]);
+ chan->engctx[engine] = NULL;
}
static int
-nv50_graph_do_load_context(struct drm_device *dev, uint32_t inst)
+nv50_graph_object_new(struct nouveau_channel *chan, int engine,
+ u32 handle, u16 class)
{
- uint32_t fifo = nv_rd32(dev, 0x400500);
+ struct drm_device *dev = chan->dev;
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+ struct nouveau_gpuobj *obj = NULL;
+ int ret;
- nv_wr32(dev, 0x400500, fifo & ~1);
- nv_wr32(dev, 0x400784, inst);
- nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) | 0x40);
- nv_wr32(dev, 0x400320, nv_rd32(dev, 0x400320) | 0x11);
- nv_wr32(dev, 0x400040, 0xffffffff);
- (void)nv_rd32(dev, 0x400040);
- nv_wr32(dev, 0x400040, 0x00000000);
- nv_wr32(dev, 0x400304, nv_rd32(dev, 0x400304) | 1);
+ ret = nouveau_gpuobj_new(dev, chan, 16, 16, NVOBJ_FLAG_ZERO_FREE, &obj);
+ if (ret)
+ return ret;
+ obj->engine = 1;
+ obj->class = class;
- if (nouveau_wait_for_idle(dev))
- nv_wr32(dev, 0x40032c, inst | (1<<31));
- nv_wr32(dev, 0x400500, fifo);
+ nv_wo32(obj, 0x00, class);
+ nv_wo32(obj, 0x04, 0x00000000);
+ nv_wo32(obj, 0x08, 0x00000000);
+ nv_wo32(obj, 0x0c, 0x00000000);
+ dev_priv->engine.instmem.flush(dev);
- return 0;
-}
-
-int
-nv50_graph_load_context(struct nouveau_channel *chan)
-{
- uint32_t inst = chan->ramin->vinst >> 12;
-
- NV_DEBUG(chan->dev, "ch%d\n", chan->id);
- return nv50_graph_do_load_context(chan->dev, inst);
-}
-
-int
-nv50_graph_unload_context(struct drm_device *dev)
-{
- uint32_t inst;
-
- inst = nv_rd32(dev, NV50_PGRAPH_CTXCTL_CUR);
- if (!(inst & NV50_PGRAPH_CTXCTL_CUR_LOADED))
- return 0;
- inst &= NV50_PGRAPH_CTXCTL_CUR_INSTANCE;
-
- nouveau_wait_for_idle(dev);
- nv_wr32(dev, 0x400784, inst);
- nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) | 0x20);
- nv_wr32(dev, 0x400304, nv_rd32(dev, 0x400304) | 0x01);
- nouveau_wait_for_idle(dev);
-
- nv_wr32(dev, NV50_PGRAPH_CTXCTL_CUR, inst);
- return 0;
+ ret = nouveau_ramht_insert(chan, handle, obj);
+ nouveau_gpuobj_ref(NULL, &obj);
+ return ret;
}
static void
@@ -442,68 +444,15 @@
return 0;
}
-static int
-nv50_graph_register(struct drm_device *dev)
-{
- struct drm_nouveau_private *dev_priv = dev->dev_private;
- if (dev_priv->engine.graph.registered)
- return 0;
-
- NVOBJ_CLASS(dev, 0x506e, SW); /* nvsw */
- NVOBJ_MTHD (dev, 0x506e, 0x018c, nv50_graph_nvsw_dma_vblsem);
- NVOBJ_MTHD (dev, 0x506e, 0x0400, nv50_graph_nvsw_vblsem_offset);
- NVOBJ_MTHD (dev, 0x506e, 0x0404, nv50_graph_nvsw_vblsem_release_val);
- NVOBJ_MTHD (dev, 0x506e, 0x0408, nv50_graph_nvsw_vblsem_release);
- NVOBJ_MTHD (dev, 0x506e, 0x0500, nv50_graph_nvsw_mthd_page_flip);
-
- NVOBJ_CLASS(dev, 0x0030, GR); /* null */
- NVOBJ_CLASS(dev, 0x5039, GR); /* m2mf */
- NVOBJ_CLASS(dev, 0x502d, GR); /* 2d */
-
- /* tesla */
- if (dev_priv->chipset == 0x50)
- NVOBJ_CLASS(dev, 0x5097, GR); /* tesla (nv50) */
- else
- if (dev_priv->chipset < 0xa0)
- NVOBJ_CLASS(dev, 0x8297, GR); /* tesla (nv8x/nv9x) */
- else {
- switch (dev_priv->chipset) {
- case 0xa0:
- case 0xaa:
- case 0xac:
- NVOBJ_CLASS(dev, 0x8397, GR);
- break;
- case 0xa3:
- case 0xa5:
- case 0xa8:
- NVOBJ_CLASS(dev, 0x8597, GR);
- break;
- case 0xaf:
- NVOBJ_CLASS(dev, 0x8697, GR);
- break;
- }
- }
-
- /* compute */
- NVOBJ_CLASS(dev, 0x50c0, GR);
- if (dev_priv->chipset > 0xa0 &&
- dev_priv->chipset != 0xaa &&
- dev_priv->chipset != 0xac)
- NVOBJ_CLASS(dev, 0x85c0, GR);
-
- dev_priv->engine.graph.registered = true;
- return 0;
-}
-
-void
-nv50_graph_tlb_flush(struct drm_device *dev)
+static void
+nv50_graph_tlb_flush(struct drm_device *dev, int engine)
{
nv50_vm_flush_engine(dev, 0);
}
-void
-nv84_graph_tlb_flush(struct drm_device *dev)
+static void
+nv84_graph_tlb_flush(struct drm_device *dev, int engine)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_timer_engine *ptimer = &dev_priv->engine.timer;
@@ -548,8 +497,7 @@
spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
}
-static struct nouveau_enum nv50_mp_exec_error_names[] =
-{
+static struct nouveau_enum nv50_mp_exec_error_names[] = {
{ 3, "STACK_UNDERFLOW", NULL },
{ 4, "QUADON_ACTIVE", NULL },
{ 8, "TIMEOUT", NULL },
@@ -663,7 +611,7 @@
nv_rd32(dev, addr + 0x20);
pc = nv_rd32(dev, addr + 0x24);
oplow = nv_rd32(dev, addr + 0x70);
- ophigh= nv_rd32(dev, addr + 0x74);
+ ophigh = nv_rd32(dev, addr + 0x74);
NV_INFO(dev, "PGRAPH_TRAP_MP_EXEC - "
"TP %d MP %d: ", tpid, i);
nouveau_enum_print(nv50_mp_exec_error_names, status);
@@ -991,7 +939,7 @@
return 1;
}
-static int
+int
nv50_graph_isr_chid(struct drm_device *dev, u64 inst)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
@@ -1073,3 +1021,101 @@
if (nv_rd32(dev, 0x400824) & (1 << 31))
nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) & ~(1 << 31));
}
+
+static void
+nv50_graph_destroy(struct drm_device *dev, int engine)
+{
+ struct nv50_graph_engine *pgraph = nv_engine(dev, engine);
+
+ NVOBJ_ENGINE_DEL(dev, GR);
+
+ nouveau_irq_unregister(dev, 12);
+ kfree(pgraph);
+}
+
+int
+nv50_graph_create(struct drm_device *dev)
+{
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+ struct nv50_graph_engine *pgraph;
+ struct nouveau_grctx ctx = {};
+ int ret;
+
+ pgraph = kzalloc(sizeof(*pgraph),GFP_KERNEL);
+ if (!pgraph)
+ return -ENOMEM;
+
+ ctx.dev = dev;
+ ctx.mode = NOUVEAU_GRCTX_PROG;
+ ctx.data = pgraph->ctxprog;
+ ctx.ctxprog_max = ARRAY_SIZE(pgraph->ctxprog);
+
+ ret = nv50_grctx_init(&ctx);
+ if (ret) {
+ NV_ERROR(dev, "PGRAPH: ctxprog build failed\n");
+ kfree(pgraph);
+ return 0;
+ }
+
+ pgraph->grctx_size = ctx.ctxvals_pos * 4;
+ pgraph->ctxprog_size = ctx.ctxprog_len;
+
+ pgraph->base.destroy = nv50_graph_destroy;
+ pgraph->base.init = nv50_graph_init;
+ pgraph->base.fini = nv50_graph_fini;
+ pgraph->base.context_new = nv50_graph_context_new;
+ pgraph->base.context_del = nv50_graph_context_del;
+ pgraph->base.object_new = nv50_graph_object_new;
+ if (dev_priv->chipset == 0x50 || dev_priv->chipset == 0xac)
+ pgraph->base.tlb_flush = nv50_graph_tlb_flush;
+ else
+ pgraph->base.tlb_flush = nv84_graph_tlb_flush;
+
+ nouveau_irq_register(dev, 12, nv50_graph_isr);
+
+ /* NVSW really doesn't live here... */
+ NVOBJ_CLASS(dev, 0x506e, SW); /* nvsw */
+ NVOBJ_MTHD (dev, 0x506e, 0x018c, nv50_graph_nvsw_dma_vblsem);
+ NVOBJ_MTHD (dev, 0x506e, 0x0400, nv50_graph_nvsw_vblsem_offset);
+ NVOBJ_MTHD (dev, 0x506e, 0x0404, nv50_graph_nvsw_vblsem_release_val);
+ NVOBJ_MTHD (dev, 0x506e, 0x0408, nv50_graph_nvsw_vblsem_release);
+ NVOBJ_MTHD (dev, 0x506e, 0x0500, nv50_graph_nvsw_mthd_page_flip);
+
+ NVOBJ_ENGINE_ADD(dev, GR, &pgraph->base);
+ NVOBJ_CLASS(dev, 0x0030, GR); /* null */
+ NVOBJ_CLASS(dev, 0x5039, GR); /* m2mf */
+ NVOBJ_CLASS(dev, 0x502d, GR); /* 2d */
+
+ /* tesla */
+ if (dev_priv->chipset == 0x50)
+ NVOBJ_CLASS(dev, 0x5097, GR); /* tesla (nv50) */
+ else
+ if (dev_priv->chipset < 0xa0)
+ NVOBJ_CLASS(dev, 0x8297, GR); /* tesla (nv8x/nv9x) */
+ else {
+ switch (dev_priv->chipset) {
+ case 0xa0:
+ case 0xaa:
+ case 0xac:
+ NVOBJ_CLASS(dev, 0x8397, GR);
+ break;
+ case 0xa3:
+ case 0xa5:
+ case 0xa8:
+ NVOBJ_CLASS(dev, 0x8597, GR);
+ break;
+ case 0xaf:
+ NVOBJ_CLASS(dev, 0x8697, GR);
+ break;
+ }
+ }
+
+ /* compute */
+ NVOBJ_CLASS(dev, 0x50c0, GR);
+ if (dev_priv->chipset > 0xa0 &&
+ dev_priv->chipset != 0xaa &&
+ dev_priv->chipset != 0xac)
+ NVOBJ_CLASS(dev, 0x85c0, GR);
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/nouveau/nv50_grctx.c b/drivers/gpu/drm/nouveau/nv50_grctx.c
index 336aab2..de9abff 100644
--- a/drivers/gpu/drm/nouveau/nv50_grctx.c
+++ b/drivers/gpu/drm/nouveau/nv50_grctx.c
@@ -747,7 +747,7 @@
gr_def(ctx, offset + 0x64, 0x0000001f);
gr_def(ctx, offset + 0x68, 0x0000000f);
gr_def(ctx, offset + 0x6c, 0x0000000f);
- } else if(dev_priv->chipset < 0xa0) {
+ } else if (dev_priv->chipset < 0xa0) {
cp_ctx(ctx, offset + 0x50, 1);
cp_ctx(ctx, offset + 0x70, 1);
} else {
@@ -924,7 +924,7 @@
dd_emit(ctx, 1, 0); /* 0000007f MULTISAMPLE_SAMPLES_LOG2 */
} else {
dd_emit(ctx, 1, 0); /* 0000000f MULTISAMPLE_SAMPLES_LOG2 */
- }
+ }
dd_emit(ctx, 1, 0xc); /* 000000ff SEMANTIC_COLOR.BFC0_ID */
if (dev_priv->chipset != 0x50)
dd_emit(ctx, 1, 0); /* 00000001 SEMANTIC_COLOR.CLMP_EN */
@@ -1803,9 +1803,7 @@
xf_emit(ctx, 1, 0); /* 1ff */
xf_emit(ctx, 8, 0); /* 0? */
xf_emit(ctx, 9, 0); /* ffffffff, 7ff */
- }
- else
- {
+ } else {
xf_emit(ctx, 0xc, 0); /* RO */
/* SEEK */
xf_emit(ctx, 0xe10, 0); /* 190 * 9: 8*ffffffff, 7ff */
@@ -2836,7 +2834,7 @@
xf_emit(ctx, 1, 1); /* 00000001 DST_LINEAR */
if (IS_NVA3F(dev_priv->chipset))
xf_emit(ctx, 1, 1); /* 0000001f tesla UNK169C */
- if(dev_priv->chipset == 0x50)
+ if (dev_priv->chipset == 0x50)
xf_emit(ctx, 1, 0); /* ff */
else
xf_emit(ctx, 3, 0); /* 1, 7, 3ff */
diff --git a/drivers/gpu/drm/nouveau/nv50_mpeg.c b/drivers/gpu/drm/nouveau/nv50_mpeg.c
new file mode 100644
index 0000000..1dc5913
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nv50_mpeg.c
@@ -0,0 +1,256 @@
+/*
+ * Copyright 2011 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs
+ */
+
+#include "drmP.h"
+#include "nouveau_drv.h"
+#include "nouveau_ramht.h"
+
+struct nv50_mpeg_engine {
+ struct nouveau_exec_engine base;
+};
+
+static inline u32
+CTX_PTR(struct drm_device *dev, u32 offset)
+{
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+
+ if (dev_priv->chipset == 0x50)
+ offset += 0x0260;
+ else
+ offset += 0x0060;
+
+ return offset;
+}
+
+static int
+nv50_mpeg_context_new(struct nouveau_channel *chan, int engine)
+{
+ struct drm_device *dev = chan->dev;
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+ struct nouveau_gpuobj *ramin = chan->ramin;
+ struct nouveau_gpuobj *ctx = NULL;
+ int ret;
+
+ NV_DEBUG(dev, "ch%d\n", chan->id);
+
+ ret = nouveau_gpuobj_new(dev, chan, 128 * 4, 0, NVOBJ_FLAG_ZERO_ALLOC |
+ NVOBJ_FLAG_ZERO_FREE, &ctx);
+ if (ret)
+ return ret;
+
+ nv_wo32(ramin, CTX_PTR(dev, 0x00), 0x80190002);
+ nv_wo32(ramin, CTX_PTR(dev, 0x04), ctx->vinst + ctx->size - 1);
+ nv_wo32(ramin, CTX_PTR(dev, 0x08), ctx->vinst);
+ nv_wo32(ramin, CTX_PTR(dev, 0x0c), 0);
+ nv_wo32(ramin, CTX_PTR(dev, 0x10), 0);
+ nv_wo32(ramin, CTX_PTR(dev, 0x14), 0x00010000);
+
+ nv_wo32(ctx, 0x70, 0x00801ec1);
+ nv_wo32(ctx, 0x7c, 0x0000037c);
+ dev_priv->engine.instmem.flush(dev);
+
+ chan->engctx[engine] = ctx;
+ return 0;
+}
+
+static void
+nv50_mpeg_context_del(struct nouveau_channel *chan, int engine)
+{
+ struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
+ struct nouveau_gpuobj *ctx = chan->engctx[engine];
+ struct drm_device *dev = chan->dev;
+ unsigned long flags;
+ u32 inst, i;
+
+ if (!chan->ramin)
+ return;
+
+ inst = chan->ramin->vinst >> 12;
+ inst |= 0x80000000;
+
+ spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
+ nv_mask(dev, 0x00b32c, 0x00000001, 0x00000000);
+ if (nv_rd32(dev, 0x00b318) == inst)
+ nv_mask(dev, 0x00b318, 0x80000000, 0x00000000);
+ nv_mask(dev, 0x00b32c, 0x00000001, 0x00000001);
+ spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
+
+ for (i = 0x00; i <= 0x14; i += 4)
+ nv_wo32(chan->ramin, CTX_PTR(dev, i), 0x00000000);
+ nouveau_gpuobj_ref(NULL, &ctx);
+ chan->engctx[engine] = NULL;
+}
+
+static int
+nv50_mpeg_object_new(struct nouveau_channel *chan, int engine,
+ u32 handle, u16 class)
+{
+ struct drm_device *dev = chan->dev;
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+ struct nouveau_gpuobj *obj = NULL;
+ int ret;
+
+ ret = nouveau_gpuobj_new(dev, chan, 16, 16, NVOBJ_FLAG_ZERO_FREE, &obj);
+ if (ret)
+ return ret;
+ obj->engine = 2;
+ obj->class = class;
+
+ nv_wo32(obj, 0x00, class);
+ nv_wo32(obj, 0x04, 0x00000000);
+ nv_wo32(obj, 0x08, 0x00000000);
+ nv_wo32(obj, 0x0c, 0x00000000);
+ dev_priv->engine.instmem.flush(dev);
+
+ ret = nouveau_ramht_insert(chan, handle, obj);
+ nouveau_gpuobj_ref(NULL, &obj);
+ return ret;
+}
+
+static void
+nv50_mpeg_tlb_flush(struct drm_device *dev, int engine)
+{
+ nv50_vm_flush_engine(dev, 0x08);
+}
+
+static int
+nv50_mpeg_init(struct drm_device *dev, int engine)
+{
+ nv_wr32(dev, 0x00b32c, 0x00000000);
+ nv_wr32(dev, 0x00b314, 0x00000100);
+ nv_wr32(dev, 0x00b0e0, 0x0000001a);
+
+ nv_wr32(dev, 0x00b220, 0x00000044);
+ nv_wr32(dev, 0x00b300, 0x00801ec1);
+ nv_wr32(dev, 0x00b390, 0x00000000);
+ nv_wr32(dev, 0x00b394, 0x00000000);
+ nv_wr32(dev, 0x00b398, 0x00000000);
+ nv_mask(dev, 0x00b32c, 0x00000001, 0x00000001);
+
+ nv_wr32(dev, 0x00b100, 0xffffffff);
+ nv_wr32(dev, 0x00b140, 0xffffffff);
+
+ if (!nv_wait(dev, 0x00b200, 0x00000001, 0x00000000)) {
+ NV_ERROR(dev, "PMPEG init: 0x%08x\n", nv_rd32(dev, 0x00b200));
+ return -EBUSY;
+ }
+
+ return 0;
+}
+
+static int
+nv50_mpeg_fini(struct drm_device *dev, int engine)
+{
+ /*XXX: context save for s/r */
+ nv_mask(dev, 0x00b32c, 0x00000001, 0x00000000);
+ nv_wr32(dev, 0x00b140, 0x00000000);
+ return 0;
+}
+
+static void
+nv50_mpeg_isr(struct drm_device *dev)
+{
+ u32 stat = nv_rd32(dev, 0x00b100);
+ u32 type = nv_rd32(dev, 0x00b230);
+ u32 mthd = nv_rd32(dev, 0x00b234);
+ u32 data = nv_rd32(dev, 0x00b238);
+ u32 show = stat;
+
+ if (stat & 0x01000000) {
+ /* happens on initial binding of the object */
+ if (type == 0x00000020 && mthd == 0x0000) {
+ nv_wr32(dev, 0x00b308, 0x00000100);
+ show &= ~0x01000000;
+ }
+ }
+
+ if (show && nouveau_ratelimit()) {
+ NV_INFO(dev, "PMPEG - 0x%08x 0x%08x 0x%08x 0x%08x\n",
+ stat, type, mthd, data);
+ }
+
+ nv_wr32(dev, 0x00b100, stat);
+ nv_wr32(dev, 0x00b230, 0x00000001);
+ nv50_fb_vm_trap(dev, 1);
+}
+
+static void
+nv50_vpe_isr(struct drm_device *dev)
+{
+ if (nv_rd32(dev, 0x00b100))
+ nv50_mpeg_isr(dev);
+
+ if (nv_rd32(dev, 0x00b800)) {
+ u32 stat = nv_rd32(dev, 0x00b800);
+ NV_INFO(dev, "PMSRCH: 0x%08x\n", stat);
+ nv_wr32(dev, 0xb800, stat);
+ }
+}
+
+static void
+nv50_mpeg_destroy(struct drm_device *dev, int engine)
+{
+ struct nv50_mpeg_engine *pmpeg = nv_engine(dev, engine);
+
+ nouveau_irq_unregister(dev, 0);
+
+ NVOBJ_ENGINE_DEL(dev, MPEG);
+ kfree(pmpeg);
+}
+
+int
+nv50_mpeg_create(struct drm_device *dev)
+{
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+ struct nv50_mpeg_engine *pmpeg;
+
+ pmpeg = kzalloc(sizeof(*pmpeg), GFP_KERNEL);
+ if (!pmpeg)
+ return -ENOMEM;
+
+ pmpeg->base.destroy = nv50_mpeg_destroy;
+ pmpeg->base.init = nv50_mpeg_init;
+ pmpeg->base.fini = nv50_mpeg_fini;
+ pmpeg->base.context_new = nv50_mpeg_context_new;
+ pmpeg->base.context_del = nv50_mpeg_context_del;
+ pmpeg->base.object_new = nv50_mpeg_object_new;
+ pmpeg->base.tlb_flush = nv50_mpeg_tlb_flush;
+
+ if (dev_priv->chipset == 0x50) {
+ nouveau_irq_register(dev, 0, nv50_vpe_isr);
+ NVOBJ_ENGINE_ADD(dev, MPEG, &pmpeg->base);
+ NVOBJ_CLASS(dev, 0x3174, MPEG);
+#if 0
+ NVOBJ_ENGINE_ADD(dev, ME, &pme->base);
+ NVOBJ_CLASS(dev, 0x4075, ME);
+#endif
+ } else {
+ nouveau_irq_register(dev, 0, nv50_mpeg_isr);
+ NVOBJ_ENGINE_ADD(dev, MPEG, &pmpeg->base);
+ NVOBJ_CLASS(dev, 0x8274, MPEG);
+ }
+
+ return 0;
+
+}
diff --git a/drivers/gpu/drm/nouveau/nv50_pm.c b/drivers/gpu/drm/nouveau/nv50_pm.c
index 7dbb305..8a28100 100644
--- a/drivers/gpu/drm/nouveau/nv50_pm.c
+++ b/drivers/gpu/drm/nouveau/nv50_pm.c
@@ -47,6 +47,21 @@
reg0 = nv_rd32(dev, pll.reg + 0);
reg1 = nv_rd32(dev, pll.reg + 4);
+
+ if ((reg0 & 0x80000000) == 0) {
+ if (id == PLL_SHADER) {
+ NV_DEBUG(dev, "Shader PLL is disabled. "
+ "Shader clock is twice the core\n");
+ ret = nv50_pm_clock_get(dev, PLL_CORE);
+ if (ret > 0)
+ return ret << 1;
+ } else if (id == PLL_MEMORY) {
+ NV_DEBUG(dev, "Memory PLL is disabled. "
+ "Memory clock is equal to the ref_clk\n");
+ return pll.refclk;
+ }
+ }
+
P = (reg0 & 0x00070000) >> 16;
N = (reg1 & 0x0000ff00) >> 8;
M = (reg1 & 0x000000ff);
diff --git a/drivers/gpu/drm/nouveau/nv50_vm.c b/drivers/gpu/drm/nouveau/nv50_vm.c
index 6c26944..1a0dd49 100644
--- a/drivers/gpu/drm/nouveau/nv50_vm.c
+++ b/drivers/gpu/drm/nouveau/nv50_vm.c
@@ -151,8 +151,7 @@
struct drm_nouveau_private *dev_priv = vm->dev->dev_private;
struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
- struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
- struct nouveau_crypt_engine *pcrypt = &dev_priv->engine.crypt;
+ int i;
pinstmem->flush(vm->dev);
@@ -163,11 +162,10 @@
}
pfifo->tlb_flush(vm->dev);
-
- if (atomic_read(&vm->pgraph_refs))
- pgraph->tlb_flush(vm->dev);
- if (atomic_read(&vm->pcrypt_refs))
- pcrypt->tlb_flush(vm->dev);
+ for (i = 0; i < NVOBJ_ENGINE_NR; i++) {
+ if (atomic_read(&vm->engref[i]))
+ dev_priv->eng[i]->tlb_flush(vm->dev, i);
+ }
}
void
diff --git a/drivers/gpu/drm/nouveau/nv84_crypt.c b/drivers/gpu/drm/nouveau/nv84_crypt.c
index fabc7fd..75b809a 100644
--- a/drivers/gpu/drm/nouveau/nv84_crypt.c
+++ b/drivers/gpu/drm/nouveau/nv84_crypt.c
@@ -26,46 +26,48 @@
#include "nouveau_drv.h"
#include "nouveau_util.h"
#include "nouveau_vm.h"
+#include "nouveau_ramht.h"
-static void nv84_crypt_isr(struct drm_device *);
+struct nv84_crypt_engine {
+ struct nouveau_exec_engine base;
+};
-int
-nv84_crypt_create_context(struct nouveau_channel *chan)
+static int
+nv84_crypt_context_new(struct nouveau_channel *chan, int engine)
{
struct drm_device *dev = chan->dev;
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_gpuobj *ramin = chan->ramin;
+ struct nouveau_gpuobj *ctx;
int ret;
NV_DEBUG(dev, "ch%d\n", chan->id);
- ret = nouveau_gpuobj_new(dev, chan, 256, 0,
- NVOBJ_FLAG_ZERO_ALLOC | NVOBJ_FLAG_ZERO_FREE,
- &chan->crypt_ctx);
+ ret = nouveau_gpuobj_new(dev, chan, 256, 0, NVOBJ_FLAG_ZERO_ALLOC |
+ NVOBJ_FLAG_ZERO_FREE, &ctx);
if (ret)
return ret;
nv_wo32(ramin, 0xa0, 0x00190000);
- nv_wo32(ramin, 0xa4, chan->crypt_ctx->vinst + 0xff);
- nv_wo32(ramin, 0xa8, chan->crypt_ctx->vinst);
+ nv_wo32(ramin, 0xa4, ctx->vinst + ctx->size - 1);
+ nv_wo32(ramin, 0xa8, ctx->vinst);
nv_wo32(ramin, 0xac, 0);
nv_wo32(ramin, 0xb0, 0);
nv_wo32(ramin, 0xb4, 0);
-
dev_priv->engine.instmem.flush(dev);
- atomic_inc(&chan->vm->pcrypt_refs);
+
+ atomic_inc(&chan->vm->engref[engine]);
+ chan->engctx[engine] = ctx;
return 0;
}
-void
-nv84_crypt_destroy_context(struct nouveau_channel *chan)
+static void
+nv84_crypt_context_del(struct nouveau_channel *chan, int engine)
{
+ struct nouveau_gpuobj *ctx = chan->engctx[engine];
struct drm_device *dev = chan->dev;
u32 inst;
- if (!chan->crypt_ctx)
- return;
-
inst = (chan->ramin->vinst >> 12);
inst |= 0x80000000;
@@ -80,45 +82,41 @@
nv_mask(dev, 0x10218c, 0x80000000, 0x00000000);
nv_wr32(dev, 0x10200c, 0x00000010);
- nouveau_gpuobj_ref(NULL, &chan->crypt_ctx);
- atomic_dec(&chan->vm->pcrypt_refs);
+ nouveau_gpuobj_ref(NULL, &ctx);
+
+ atomic_dec(&chan->vm->engref[engine]);
+ chan->engctx[engine] = NULL;
}
-void
-nv84_crypt_tlb_flush(struct drm_device *dev)
+static int
+nv84_crypt_object_new(struct nouveau_channel *chan, int engine,
+ u32 handle, u16 class)
+{
+ struct drm_device *dev = chan->dev;
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+ struct nouveau_gpuobj *obj = NULL;
+ int ret;
+
+ ret = nouveau_gpuobj_new(dev, chan, 16, 16, NVOBJ_FLAG_ZERO_FREE, &obj);
+ if (ret)
+ return ret;
+ obj->engine = 5;
+ obj->class = class;
+
+ nv_wo32(obj, 0x00, class);
+ dev_priv->engine.instmem.flush(dev);
+
+ ret = nouveau_ramht_insert(chan, handle, obj);
+ nouveau_gpuobj_ref(NULL, &obj);
+ return ret;
+}
+
+static void
+nv84_crypt_tlb_flush(struct drm_device *dev, int engine)
{
nv50_vm_flush_engine(dev, 0x0a);
}
-int
-nv84_crypt_init(struct drm_device *dev)
-{
- struct drm_nouveau_private *dev_priv = dev->dev_private;
- struct nouveau_crypt_engine *pcrypt = &dev_priv->engine.crypt;
-
- if (!pcrypt->registered) {
- NVOBJ_CLASS(dev, 0x74c1, CRYPT);
- pcrypt->registered = true;
- }
-
- nv_mask(dev, 0x000200, 0x00004000, 0x00000000);
- nv_mask(dev, 0x000200, 0x00004000, 0x00004000);
-
- nouveau_irq_register(dev, 14, nv84_crypt_isr);
- nv_wr32(dev, 0x102130, 0xffffffff);
- nv_wr32(dev, 0x102140, 0xffffffbf);
-
- nv_wr32(dev, 0x10200c, 0x00000010);
- return 0;
-}
-
-void
-nv84_crypt_fini(struct drm_device *dev)
-{
- nv_wr32(dev, 0x102140, 0x00000000);
- nouveau_irq_unregister(dev, 14);
-}
-
static void
nv84_crypt_isr(struct drm_device *dev)
{
@@ -138,3 +136,58 @@
nv50_fb_vm_trap(dev, show);
}
+
+static int
+nv84_crypt_fini(struct drm_device *dev, int engine)
+{
+ nv_wr32(dev, 0x102140, 0x00000000);
+ return 0;
+}
+
+static int
+nv84_crypt_init(struct drm_device *dev, int engine)
+{
+ nv_mask(dev, 0x000200, 0x00004000, 0x00000000);
+ nv_mask(dev, 0x000200, 0x00004000, 0x00004000);
+
+ nv_wr32(dev, 0x102130, 0xffffffff);
+ nv_wr32(dev, 0x102140, 0xffffffbf);
+
+ nv_wr32(dev, 0x10200c, 0x00000010);
+ return 0;
+}
+
+static void
+nv84_crypt_destroy(struct drm_device *dev, int engine)
+{
+ struct nv84_crypt_engine *pcrypt = nv_engine(dev, engine);
+
+ NVOBJ_ENGINE_DEL(dev, CRYPT);
+
+ nouveau_irq_unregister(dev, 14);
+ kfree(pcrypt);
+}
+
+int
+nv84_crypt_create(struct drm_device *dev)
+{
+ struct nv84_crypt_engine *pcrypt;
+
+ pcrypt = kzalloc(sizeof(*pcrypt), GFP_KERNEL);
+ if (!pcrypt)
+ return -ENOMEM;
+
+ pcrypt->base.destroy = nv84_crypt_destroy;
+ pcrypt->base.init = nv84_crypt_init;
+ pcrypt->base.fini = nv84_crypt_fini;
+ pcrypt->base.context_new = nv84_crypt_context_new;
+ pcrypt->base.context_del = nv84_crypt_context_del;
+ pcrypt->base.object_new = nv84_crypt_object_new;
+ pcrypt->base.tlb_flush = nv84_crypt_tlb_flush;
+
+ nouveau_irq_register(dev, 14, nv84_crypt_isr);
+
+ NVOBJ_ENGINE_ADD(dev, CRYPT, &pcrypt->base);
+ NVOBJ_CLASS (dev, 0x74c1, CRYPT);
+ return 0;
+}
diff --git a/drivers/gpu/drm/nouveau/nva3_copy.c b/drivers/gpu/drm/nouveau/nva3_copy.c
new file mode 100644
index 0000000..b86820a
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nva3_copy.c
@@ -0,0 +1,226 @@
+/*
+ * Copyright 2011 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs
+ */
+
+#include <linux/firmware.h>
+#include "drmP.h"
+#include "nouveau_drv.h"
+#include "nouveau_util.h"
+#include "nouveau_vm.h"
+#include "nouveau_ramht.h"
+#include "nva3_copy.fuc.h"
+
+struct nva3_copy_engine {
+ struct nouveau_exec_engine base;
+};
+
+static int
+nva3_copy_context_new(struct nouveau_channel *chan, int engine)
+{
+ struct drm_device *dev = chan->dev;
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+ struct nouveau_gpuobj *ramin = chan->ramin;
+ struct nouveau_gpuobj *ctx = NULL;
+ int ret;
+
+ NV_DEBUG(dev, "ch%d\n", chan->id);
+
+ ret = nouveau_gpuobj_new(dev, chan, 256, 0, NVOBJ_FLAG_ZERO_ALLOC |
+ NVOBJ_FLAG_ZERO_FREE, &ctx);
+ if (ret)
+ return ret;
+
+ nv_wo32(ramin, 0xc0, 0x00190000);
+ nv_wo32(ramin, 0xc4, ctx->vinst + ctx->size - 1);
+ nv_wo32(ramin, 0xc8, ctx->vinst);
+ nv_wo32(ramin, 0xcc, 0x00000000);
+ nv_wo32(ramin, 0xd0, 0x00000000);
+ nv_wo32(ramin, 0xd4, 0x00000000);
+ dev_priv->engine.instmem.flush(dev);
+
+ atomic_inc(&chan->vm->engref[engine]);
+ chan->engctx[engine] = ctx;
+ return 0;
+}
+
+static int
+nva3_copy_object_new(struct nouveau_channel *chan, int engine,
+ u32 handle, u16 class)
+{
+ struct nouveau_gpuobj *ctx = chan->engctx[engine];
+
+ /* fuc engine doesn't need an object, our ramht code does.. */
+ ctx->engine = 3;
+ ctx->class = class;
+ return nouveau_ramht_insert(chan, handle, ctx);
+}
+
+static void
+nva3_copy_context_del(struct nouveau_channel *chan, int engine)
+{
+ struct nouveau_gpuobj *ctx = chan->engctx[engine];
+ struct drm_device *dev = chan->dev;
+ u32 inst;
+
+ inst = (chan->ramin->vinst >> 12);
+ inst |= 0x40000000;
+
+ /* disable fifo access */
+ nv_wr32(dev, 0x104048, 0x00000000);
+ /* mark channel as unloaded if it's currently active */
+ if (nv_rd32(dev, 0x104050) == inst)
+ nv_mask(dev, 0x104050, 0x40000000, 0x00000000);
+ /* mark next channel as invalid if it's about to be loaded */
+ if (nv_rd32(dev, 0x104054) == inst)
+ nv_mask(dev, 0x104054, 0x40000000, 0x00000000);
+ /* restore fifo access */
+ nv_wr32(dev, 0x104048, 0x00000003);
+
+ for (inst = 0xc0; inst <= 0xd4; inst += 4)
+ nv_wo32(chan->ramin, inst, 0x00000000);
+
+ nouveau_gpuobj_ref(NULL, &ctx);
+
+ atomic_dec(&chan->vm->engref[engine]);
+ chan->engctx[engine] = ctx;
+}
+
+static void
+nva3_copy_tlb_flush(struct drm_device *dev, int engine)
+{
+ nv50_vm_flush_engine(dev, 0x0d);
+}
+
+static int
+nva3_copy_init(struct drm_device *dev, int engine)
+{
+ int i;
+
+ nv_mask(dev, 0x000200, 0x00002000, 0x00000000);
+ nv_mask(dev, 0x000200, 0x00002000, 0x00002000);
+ nv_wr32(dev, 0x104014, 0xffffffff); /* disable all interrupts */
+
+ /* upload ucode */
+ nv_wr32(dev, 0x1041c0, 0x01000000);
+ for (i = 0; i < sizeof(nva3_pcopy_data) / 4; i++)
+ nv_wr32(dev, 0x1041c4, nva3_pcopy_data[i]);
+
+ nv_wr32(dev, 0x104180, 0x01000000);
+ for (i = 0; i < sizeof(nva3_pcopy_code) / 4; i++) {
+ if ((i & 0x3f) == 0)
+ nv_wr32(dev, 0x104188, i >> 6);
+ nv_wr32(dev, 0x104184, nva3_pcopy_code[i]);
+ }
+
+ /* start it running */
+ nv_wr32(dev, 0x10410c, 0x00000000);
+ nv_wr32(dev, 0x104104, 0x00000000); /* ENTRY */
+ nv_wr32(dev, 0x104100, 0x00000002); /* TRIGGER */
+ return 0;
+}
+
+static int
+nva3_copy_fini(struct drm_device *dev, int engine)
+{
+ nv_mask(dev, 0x104048, 0x00000003, 0x00000000);
+
+ /* trigger fuc context unload */
+ nv_wait(dev, 0x104008, 0x0000000c, 0x00000000);
+ nv_mask(dev, 0x104054, 0x40000000, 0x00000000);
+ nv_wr32(dev, 0x104000, 0x00000008);
+ nv_wait(dev, 0x104008, 0x00000008, 0x00000000);
+
+ nv_wr32(dev, 0x104014, 0xffffffff);
+ return 0;
+}
+
+static struct nouveau_enum nva3_copy_isr_error_name[] = {
+ { 0x0001, "ILLEGAL_MTHD" },
+ { 0x0002, "INVALID_ENUM" },
+ { 0x0003, "INVALID_BITFIELD" },
+ {}
+};
+
+static void
+nva3_copy_isr(struct drm_device *dev)
+{
+ u32 dispatch = nv_rd32(dev, 0x10401c);
+ u32 stat = nv_rd32(dev, 0x104008) & dispatch & ~(dispatch >> 16);
+ u32 inst = nv_rd32(dev, 0x104050) & 0x3fffffff;
+ u32 ssta = nv_rd32(dev, 0x104040) & 0x0000ffff;
+ u32 addr = nv_rd32(dev, 0x104040) >> 16;
+ u32 mthd = (addr & 0x07ff) << 2;
+ u32 subc = (addr & 0x3800) >> 11;
+ u32 data = nv_rd32(dev, 0x104044);
+ int chid = nv50_graph_isr_chid(dev, inst);
+
+ if (stat & 0x00000040) {
+ NV_INFO(dev, "PCOPY: DISPATCH_ERROR [");
+ nouveau_enum_print(nva3_copy_isr_error_name, ssta);
+ printk("] ch %d [0x%08x] subc %d mthd 0x%04x data 0x%08x\n",
+ chid, inst, subc, mthd, data);
+ nv_wr32(dev, 0x104004, 0x00000040);
+ stat &= ~0x00000040;
+ }
+
+ if (stat) {
+ NV_INFO(dev, "PCOPY: unhandled intr 0x%08x\n", stat);
+ nv_wr32(dev, 0x104004, stat);
+ }
+ nv50_fb_vm_trap(dev, 1);
+}
+
+static void
+nva3_copy_destroy(struct drm_device *dev, int engine)
+{
+ struct nva3_copy_engine *pcopy = nv_engine(dev, engine);
+
+ nouveau_irq_unregister(dev, 22);
+
+ NVOBJ_ENGINE_DEL(dev, COPY0);
+ kfree(pcopy);
+}
+
+int
+nva3_copy_create(struct drm_device *dev)
+{
+ struct nva3_copy_engine *pcopy;
+
+ pcopy = kzalloc(sizeof(*pcopy), GFP_KERNEL);
+ if (!pcopy)
+ return -ENOMEM;
+
+ pcopy->base.destroy = nva3_copy_destroy;
+ pcopy->base.init = nva3_copy_init;
+ pcopy->base.fini = nva3_copy_fini;
+ pcopy->base.context_new = nva3_copy_context_new;
+ pcopy->base.context_del = nva3_copy_context_del;
+ pcopy->base.object_new = nva3_copy_object_new;
+ pcopy->base.tlb_flush = nva3_copy_tlb_flush;
+
+ nouveau_irq_register(dev, 22, nva3_copy_isr);
+
+ NVOBJ_ENGINE_ADD(dev, COPY0, &pcopy->base);
+ NVOBJ_CLASS(dev, 0x85b5, COPY0);
+ return 0;
+}
diff --git a/drivers/gpu/drm/nouveau/nva3_copy.fuc b/drivers/gpu/drm/nouveau/nva3_copy.fuc
new file mode 100644
index 0000000..eaf35f8
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nva3_copy.fuc
@@ -0,0 +1,870 @@
+/* fuc microcode for copy engine on nva3- chipsets
+ *
+ * Copyright 2011 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs
+ */
+
+/* To build for nva3:nvc0
+ * m4 -DNVA3 nva3_copy.fuc | envyas -a -w -m fuc -V nva3 -o nva3_copy.fuc.h
+ *
+ * To build for nvc0-
+ * m4 -DNVC0 nva3_copy.fuc | envyas -a -w -m fuc -V nva3 -o nvc0_copy.fuc.h
+ */
+
+ifdef(`NVA3',
+.section nva3_pcopy_data,
+.section nvc0_pcopy_data
+)
+
+ctx_object: .b32 0
+ifdef(`NVA3',
+ctx_dma:
+ctx_dma_query: .b32 0
+ctx_dma_src: .b32 0
+ctx_dma_dst: .b32 0
+,)
+.equ ctx_dma_count 3
+ctx_query_address_high: .b32 0
+ctx_query_address_low: .b32 0
+ctx_query_counter: .b32 0
+ctx_src_address_high: .b32 0
+ctx_src_address_low: .b32 0
+ctx_src_pitch: .b32 0
+ctx_src_tile_mode: .b32 0
+ctx_src_xsize: .b32 0
+ctx_src_ysize: .b32 0
+ctx_src_zsize: .b32 0
+ctx_src_zoff: .b32 0
+ctx_src_xoff: .b32 0
+ctx_src_yoff: .b32 0
+ctx_src_cpp: .b32 0
+ctx_dst_address_high: .b32 0
+ctx_dst_address_low: .b32 0
+ctx_dst_pitch: .b32 0
+ctx_dst_tile_mode: .b32 0
+ctx_dst_xsize: .b32 0
+ctx_dst_ysize: .b32 0
+ctx_dst_zsize: .b32 0
+ctx_dst_zoff: .b32 0
+ctx_dst_xoff: .b32 0
+ctx_dst_yoff: .b32 0
+ctx_dst_cpp: .b32 0
+ctx_format: .b32 0
+ctx_swz_const0: .b32 0
+ctx_swz_const1: .b32 0
+ctx_xcnt: .b32 0
+ctx_ycnt: .b32 0
+.align 256
+
+dispatch_table:
+// mthd 0x0000, NAME
+.b16 0x000 1
+.b32 ctx_object ~0xffffffff
+// mthd 0x0100, NOP
+.b16 0x040 1
+.b32 0x00010000 + cmd_nop ~0xffffffff
+// mthd 0x0140, PM_TRIGGER
+.b16 0x050 1
+.b32 0x00010000 + cmd_pm_trigger ~0xffffffff
+ifdef(`NVA3', `
+// mthd 0x0180-0x018c, DMA_
+.b16 0x060 ctx_dma_count
+dispatch_dma:
+.b32 0x00010000 + cmd_dma ~0xffffffff
+.b32 0x00010000 + cmd_dma ~0xffffffff
+.b32 0x00010000 + cmd_dma ~0xffffffff
+',)
+// mthd 0x0200-0x0218, SRC_TILE
+.b16 0x80 7
+.b32 ctx_src_tile_mode ~0x00000fff
+.b32 ctx_src_xsize ~0x0007ffff
+.b32 ctx_src_ysize ~0x00001fff
+.b32 ctx_src_zsize ~0x000007ff
+.b32 ctx_src_zoff ~0x00000fff
+.b32 ctx_src_xoff ~0x0007ffff
+.b32 ctx_src_yoff ~0x00001fff
+// mthd 0x0220-0x0238, DST_TILE
+.b16 0x88 7
+.b32 ctx_dst_tile_mode ~0x00000fff
+.b32 ctx_dst_xsize ~0x0007ffff
+.b32 ctx_dst_ysize ~0x00001fff
+.b32 ctx_dst_zsize ~0x000007ff
+.b32 ctx_dst_zoff ~0x00000fff
+.b32 ctx_dst_xoff ~0x0007ffff
+.b32 ctx_dst_yoff ~0x00001fff
+// mthd 0x0300-0x0304, EXEC, WRCACHE_FLUSH
+.b16 0xc0 2
+.b32 0x00010000 + cmd_exec ~0xffffffff
+.b32 0x00010000 + cmd_wrcache_flush ~0xffffffff
+// mthd 0x030c-0x0340, various stuff
+.b16 0xc3 14
+.b32 ctx_src_address_high ~0x000000ff
+.b32 ctx_src_address_low ~0xfffffff0
+.b32 ctx_dst_address_high ~0x000000ff
+.b32 ctx_dst_address_low ~0xfffffff0
+.b32 ctx_src_pitch ~0x0007ffff
+.b32 ctx_dst_pitch ~0x0007ffff
+.b32 ctx_xcnt ~0x0000ffff
+.b32 ctx_ycnt ~0x00001fff
+.b32 ctx_format ~0x0333ffff
+.b32 ctx_swz_const0 ~0xffffffff
+.b32 ctx_swz_const1 ~0xffffffff
+.b32 ctx_query_address_high ~0x000000ff
+.b32 ctx_query_address_low ~0xffffffff
+.b32 ctx_query_counter ~0xffffffff
+.b16 0x800 0
+
+ifdef(`NVA3',
+.section nva3_pcopy_code,
+.section nvc0_pcopy_code
+)
+
+main:
+ clear b32 $r0
+ mov $sp $r0
+
+ // setup i0 handler and route fifo and ctxswitch to it
+ mov $r1 ih
+ mov $iv0 $r1
+ mov $r1 0x400
+ movw $r2 0xfff3
+ sethi $r2 0
+ iowr I[$r2 + 0x300] $r2
+
+ // enable interrupts
+ or $r2 0xc
+ iowr I[$r1] $r2
+ bset $flags ie0
+
+ // enable fifo access and context switching
+ mov $r1 0x1200
+ mov $r2 3
+ iowr I[$r1] $r2
+
+ // sleep forever, waking for interrupts
+ bset $flags $p0
+ spin:
+ sleep $p0
+ bra spin
+
+// i0 handler
+ih:
+ iord $r1 I[$r0 + 0x200]
+
+ and $r2 $r1 0x00000008
+ bra e ih_no_chsw
+ call chsw
+ ih_no_chsw:
+ and $r2 $r1 0x00000004
+ bra e ih_no_cmd
+ call dispatch
+
+ ih_no_cmd:
+ and $r1 $r1 0x0000000c
+ iowr I[$r0 + 0x100] $r1
+ iret
+
+// $p1 direction (0 = unload, 1 = load)
+// $r3 channel
+swctx:
+ mov $r4 0x7700
+ mov $xtargets $r4
+ifdef(`NVA3', `
+ // target 7 hardcoded to ctx dma object
+ mov $xdbase $r0
+', ` // NVC0
+ // read SCRATCH3 to decide if we are PCOPY0 or PCOPY1
+ mov $r4 0x2100
+ iord $r4 I[$r4 + 0]
+ and $r4 1
+ shl b32 $r4 4
+ add b32 $r4 0x30
+
+ // channel is in vram
+ mov $r15 0x61c
+ shl b32 $r15 6
+ mov $r5 0x114
+ iowrs I[$r15] $r5
+
+ // read 16-byte PCOPYn info, containing context pointer, from channel
+ shl b32 $r5 $r3 4
+ add b32 $r5 2
+ mov $xdbase $r5
+ mov $r5 $sp
+ // get a chunk of stack space, aligned to 256 byte boundary
+ sub b32 $r5 0x100
+ mov $r6 0xff
+ not b32 $r6
+ and $r5 $r6
+ sethi $r5 0x00020000
+ xdld $r4 $r5
+ xdwait
+ sethi $r5 0
+
+ // set context pointer, from within channel VM
+ mov $r14 0
+ iowrs I[$r15] $r14
+ ld b32 $r4 D[$r5 + 0]
+ shr b32 $r4 8
+ ld b32 $r6 D[$r5 + 4]
+ shl b32 $r6 24
+ or $r4 $r6
+ mov $xdbase $r4
+')
+ // 256-byte context, at start of data segment
+ mov b32 $r4 $r0
+ sethi $r4 0x60000
+
+ // swap!
+ bra $p1 swctx_load
+ xdst $r0 $r4
+ bra swctx_done
+ swctx_load:
+ xdld $r0 $r4
+ swctx_done:
+ xdwait
+ ret
+
+chsw:
+ // read current channel
+ mov $r2 0x1400
+ iord $r3 I[$r2]
+
+ // if it's active, unload it and return
+ xbit $r15 $r3 0x1e
+ bra e chsw_no_unload
+ bclr $flags $p1
+ call swctx
+ bclr $r3 0x1e
+ iowr I[$r2] $r3
+ mov $r4 1
+ iowr I[$r2 + 0x200] $r4
+ ret
+
+ // read next channel
+ chsw_no_unload:
+ iord $r3 I[$r2 + 0x100]
+
+ // is there a channel waiting to be loaded?
+ xbit $r13 $r3 0x1e
+ bra e chsw_finish_load
+ bset $flags $p1
+ call swctx
+ifdef(`NVA3',
+ // load dma objects back into TARGET regs
+ mov $r5 ctx_dma
+ mov $r6 ctx_dma_count
+ chsw_load_ctx_dma:
+ ld b32 $r7 D[$r5 + $r6 * 4]
+ add b32 $r8 $r6 0x180
+ shl b32 $r8 8
+ iowr I[$r8] $r7
+ sub b32 $r6 1
+ bra nc chsw_load_ctx_dma
+,)
+
+ chsw_finish_load:
+ mov $r3 2
+ iowr I[$r2 + 0x200] $r3
+ ret
+
+dispatch:
+ // read incoming fifo command
+ mov $r3 0x1900
+ iord $r2 I[$r3 + 0x100]
+ iord $r3 I[$r3 + 0x000]
+ and $r4 $r2 0x7ff
+ // $r2 will be used to store exception data
+ shl b32 $r2 0x10
+
+ // lookup method in the dispatch table, ILLEGAL_MTHD if not found
+ mov $r5 dispatch_table
+ clear b32 $r6
+ clear b32 $r7
+ dispatch_loop:
+ ld b16 $r6 D[$r5 + 0]
+ ld b16 $r7 D[$r5 + 2]
+ add b32 $r5 4
+ cmpu b32 $r4 $r6
+ bra c dispatch_illegal_mthd
+ add b32 $r7 $r6
+ cmpu b32 $r4 $r7
+ bra c dispatch_valid_mthd
+ sub b32 $r7 $r6
+ shl b32 $r7 3
+ add b32 $r5 $r7
+ bra dispatch_loop
+
+ // ensure no bits set in reserved fields, INVALID_BITFIELD
+ dispatch_valid_mthd:
+ sub b32 $r4 $r6
+ shl b32 $r4 3
+ add b32 $r4 $r5
+ ld b32 $r5 D[$r4 + 4]
+ and $r5 $r3
+ cmpu b32 $r5 0
+ bra ne dispatch_invalid_bitfield
+
+ // depending on dispatch flags: execute method, or save data as state
+ ld b16 $r5 D[$r4 + 0]
+ ld b16 $r6 D[$r4 + 2]
+ cmpu b32 $r6 0
+ bra ne dispatch_cmd
+ st b32 D[$r5] $r3
+ bra dispatch_done
+ dispatch_cmd:
+ bclr $flags $p1
+ call $r5
+ bra $p1 dispatch_error
+ bra dispatch_done
+
+ dispatch_invalid_bitfield:
+ or $r2 2
+ dispatch_illegal_mthd:
+ or $r2 1
+
+ // store exception data in SCRATCH0/SCRATCH1, signal hostirq
+ dispatch_error:
+ mov $r4 0x1000
+ iowr I[$r4 + 0x000] $r2
+ iowr I[$r4 + 0x100] $r3
+ mov $r2 0x40
+ iowr I[$r0] $r2
+ hostirq_wait:
+ iord $r2 I[$r0 + 0x200]
+ and $r2 0x40
+ cmpu b32 $r2 0
+ bra ne hostirq_wait
+
+ dispatch_done:
+ mov $r2 0x1d00
+ mov $r3 1
+ iowr I[$r2] $r3
+ ret
+
+// No-operation
+//
+// Inputs:
+// $r1: irqh state
+// $r2: hostirq state
+// $r3: data
+// $r4: dispatch table entry
+// Outputs:
+// $r1: irqh state
+// $p1: set on error
+// $r2: hostirq state
+// $r3: data
+cmd_nop:
+ ret
+
+// PM_TRIGGER
+//
+// Inputs:
+// $r1: irqh state
+// $r2: hostirq state
+// $r3: data
+// $r4: dispatch table entry
+// Outputs:
+// $r1: irqh state
+// $p1: set on error
+// $r2: hostirq state
+// $r3: data
+cmd_pm_trigger:
+ mov $r2 0x2200
+ clear b32 $r3
+ sethi $r3 0x20000
+ iowr I[$r2] $r3
+ ret
+
+ifdef(`NVA3',
+// SET_DMA_* method handler
+//
+// Inputs:
+// $r1: irqh state
+// $r2: hostirq state
+// $r3: data
+// $r4: dispatch table entry
+// Outputs:
+// $r1: irqh state
+// $p1: set on error
+// $r2: hostirq state
+// $r3: data
+cmd_dma:
+ sub b32 $r4 dispatch_dma
+ shr b32 $r4 1
+ bset $r3 0x1e
+ st b32 D[$r4 + ctx_dma] $r3
+ add b32 $r4 0x600
+ shl b32 $r4 6
+ iowr I[$r4] $r3
+ ret
+,)
+
+// Calculates the hw swizzle mask and adjusts the surface's xcnt to match
+//
+cmd_exec_set_format:
+ // zero out a chunk of the stack to store the swizzle into
+ add $sp -0x10
+ st b32 D[$sp + 0x00] $r0
+ st b32 D[$sp + 0x04] $r0
+ st b32 D[$sp + 0x08] $r0
+ st b32 D[$sp + 0x0c] $r0
+
+ // extract cpp, src_ncomp and dst_ncomp from FORMAT
+ ld b32 $r4 D[$r0 + ctx_format]
+ extr $r5 $r4 16:17
+ add b32 $r5 1
+ extr $r6 $r4 20:21
+ add b32 $r6 1
+ extr $r7 $r4 24:25
+ add b32 $r7 1
+
+ // convert FORMAT swizzle mask to hw swizzle mask
+ bclr $flags $p2
+ clear b32 $r8
+ clear b32 $r9
+ ncomp_loop:
+ and $r10 $r4 0xf
+ shr b32 $r4 4
+ clear b32 $r11
+ bpc_loop:
+ cmpu b8 $r10 4
+ bra nc cmp_c0
+ mulu $r12 $r10 $r5
+ add b32 $r12 $r11
+ bset $flags $p2
+ bra bpc_next
+ cmp_c0:
+ bra ne cmp_c1
+ mov $r12 0x10
+ add b32 $r12 $r11
+ bra bpc_next
+ cmp_c1:
+ cmpu b8 $r10 6
+ bra nc cmp_zero
+ mov $r12 0x14
+ add b32 $r12 $r11
+ bra bpc_next
+ cmp_zero:
+ mov $r12 0x80
+ bpc_next:
+ st b8 D[$sp + $r8] $r12
+ add b32 $r8 1
+ add b32 $r11 1
+ cmpu b32 $r11 $r5
+ bra c bpc_loop
+ add b32 $r9 1
+ cmpu b32 $r9 $r7
+ bra c ncomp_loop
+
+ // SRC_XCNT = (xcnt * src_cpp), or 0 if no src ref in swz (hw will hang)
+ mulu $r6 $r5
+ st b32 D[$r0 + ctx_src_cpp] $r6
+ ld b32 $r8 D[$r0 + ctx_xcnt]
+ mulu $r6 $r8
+ bra $p2 dst_xcnt
+ clear b32 $r6
+
+ dst_xcnt:
+ mulu $r7 $r5
+ st b32 D[$r0 + ctx_dst_cpp] $r7
+ mulu $r7 $r8
+
+ mov $r5 0x810
+ shl b32 $r5 6
+ iowr I[$r5 + 0x000] $r6
+ iowr I[$r5 + 0x100] $r7
+ add b32 $r5 0x800
+ ld b32 $r6 D[$r0 + ctx_dst_cpp]
+ sub b32 $r6 1
+ shl b32 $r6 8
+ ld b32 $r7 D[$r0 + ctx_src_cpp]
+ sub b32 $r7 1
+ or $r6 $r7
+ iowr I[$r5 + 0x000] $r6
+ add b32 $r5 0x100
+ ld b32 $r6 D[$sp + 0x00]
+ iowr I[$r5 + 0x000] $r6
+ ld b32 $r6 D[$sp + 0x04]
+ iowr I[$r5 + 0x100] $r6
+ ld b32 $r6 D[$sp + 0x08]
+ iowr I[$r5 + 0x200] $r6
+ ld b32 $r6 D[$sp + 0x0c]
+ iowr I[$r5 + 0x300] $r6
+ add b32 $r5 0x400
+ ld b32 $r6 D[$r0 + ctx_swz_const0]
+ iowr I[$r5 + 0x000] $r6
+ ld b32 $r6 D[$r0 + ctx_swz_const1]
+ iowr I[$r5 + 0x100] $r6
+ add $sp 0x10
+ ret
+
+// Setup to handle a tiled surface
+//
+// Calculates a number of parameters the hardware requires in order
+// to correctly handle tiling.
+//
+// Offset calculation is performed as follows (Tp/Th/Td from TILE_MODE):
+// nTx = round_up(w * cpp, 1 << Tp) >> Tp
+// nTy = round_up(h, 1 << Th) >> Th
+// Txo = (x * cpp) & ((1 << Tp) - 1)
+// Tx = (x * cpp) >> Tp
+// Tyo = y & ((1 << Th) - 1)
+// Ty = y >> Th
+// Tzo = z & ((1 << Td) - 1)
+// Tz = z >> Td
+//
+// off = (Tzo << Tp << Th) + (Tyo << Tp) + Txo
+// off += ((Tz * nTy * nTx)) + (Ty * nTx) + Tx) << Td << Th << Tp;
+//
+// Inputs:
+// $r4: hw command (0x104800)
+// $r5: ctx offset adjustment for src/dst selection
+// $p2: set if dst surface
+//
+cmd_exec_set_surface_tiled:
+ // translate TILE_MODE into Tp, Th, Td shift values
+ ld b32 $r7 D[$r5 + ctx_src_tile_mode]
+ extr $r9 $r7 8:11
+ extr $r8 $r7 4:7
+ifdef(`NVA3',
+ add b32 $r8 2
+,
+ add b32 $r8 3
+)
+ extr $r7 $r7 0:3
+ cmp b32 $r7 0xe
+ bra ne xtile64
+ mov $r7 4
+ bra xtileok
+ xtile64:
+ xbit $r7 $flags $p2
+ add b32 $r7 17
+ bset $r4 $r7
+ mov $r7 6
+ xtileok:
+
+ // Op = (x * cpp) & ((1 << Tp) - 1)
+ // Tx = (x * cpp) >> Tp
+ ld b32 $r10 D[$r5 + ctx_src_xoff]
+ ld b32 $r11 D[$r5 + ctx_src_cpp]
+ mulu $r10 $r11
+ mov $r11 1
+ shl b32 $r11 $r7
+ sub b32 $r11 1
+ and $r12 $r10 $r11
+ shr b32 $r10 $r7
+
+ // Tyo = y & ((1 << Th) - 1)
+ // Ty = y >> Th
+ ld b32 $r13 D[$r5 + ctx_src_yoff]
+ mov $r14 1
+ shl b32 $r14 $r8
+ sub b32 $r14 1
+ and $r11 $r13 $r14
+ shr b32 $r13 $r8
+
+ // YTILE = ((1 << Th) << 12) | ((1 << Th) - Tyo)
+ add b32 $r14 1
+ shl b32 $r15 $r14 12
+ sub b32 $r14 $r11
+ or $r15 $r14
+ xbit $r6 $flags $p2
+ add b32 $r6 0x208
+ shl b32 $r6 8
+ iowr I[$r6 + 0x000] $r15
+
+ // Op += Tyo << Tp
+ shl b32 $r11 $r7
+ add b32 $r12 $r11
+
+ // nTx = ((w * cpp) + ((1 << Tp) - 1) >> Tp)
+ ld b32 $r15 D[$r5 + ctx_src_xsize]
+ ld b32 $r11 D[$r5 + ctx_src_cpp]
+ mulu $r15 $r11
+ mov $r11 1
+ shl b32 $r11 $r7
+ sub b32 $r11 1
+ add b32 $r15 $r11
+ shr b32 $r15 $r7
+ push $r15
+
+ // nTy = (h + ((1 << Th) - 1)) >> Th
+ ld b32 $r15 D[$r5 + ctx_src_ysize]
+ mov $r11 1
+ shl b32 $r11 $r8
+ sub b32 $r11 1
+ add b32 $r15 $r11
+ shr b32 $r15 $r8
+ push $r15
+
+ // Tys = Tp + Th
+ // CFG_YZ_TILE_SIZE = ((1 << Th) >> 2) << Td
+ add b32 $r7 $r8
+ sub b32 $r8 2
+ mov $r11 1
+ shl b32 $r11 $r8
+ shl b32 $r11 $r9
+
+ // Tzo = z & ((1 << Td) - 1)
+ // Tz = z >> Td
+ // Op += Tzo << Tys
+ // Ts = Tys + Td
+ ld b32 $r8 D[$r5 + ctx_src_zoff]
+ mov $r14 1
+ shl b32 $r14 $r9
+ sub b32 $r14 1
+ and $r15 $r8 $r14
+ shl b32 $r15 $r7
+ add b32 $r12 $r15
+ add b32 $r7 $r9
+ shr b32 $r8 $r9
+
+ // Ot = ((Tz * nTy * nTx) + (Ty * nTx) + Tx) << Ts
+ pop $r15
+ pop $r9
+ mulu $r13 $r9
+ add b32 $r10 $r13
+ mulu $r8 $r9
+ mulu $r8 $r15
+ add b32 $r10 $r8
+ shl b32 $r10 $r7
+
+ // PITCH = (nTx - 1) << Ts
+ sub b32 $r9 1
+ shl b32 $r9 $r7
+ iowr I[$r6 + 0x200] $r9
+
+ // SRC_ADDRESS_LOW = (Ot + Op) & 0xffffffff
+ // CFG_ADDRESS_HIGH |= ((Ot + Op) >> 32) << 16
+ ld b32 $r7 D[$r5 + ctx_src_address_low]
+ ld b32 $r8 D[$r5 + ctx_src_address_high]
+ add b32 $r10 $r12
+ add b32 $r7 $r10
+ adc b32 $r8 0
+ shl b32 $r8 16
+ or $r8 $r11
+ sub b32 $r6 0x600
+ iowr I[$r6 + 0x000] $r7
+ add b32 $r6 0x400
+ iowr I[$r6 + 0x000] $r8
+ ret
+
+// Setup to handle a linear surface
+//
+// Nothing to see here.. Sets ADDRESS and PITCH, pretty non-exciting
+//
+cmd_exec_set_surface_linear:
+ xbit $r6 $flags $p2
+ add b32 $r6 0x202
+ shl b32 $r6 8
+ ld b32 $r7 D[$r5 + ctx_src_address_low]
+ iowr I[$r6 + 0x000] $r7
+ add b32 $r6 0x400
+ ld b32 $r7 D[$r5 + ctx_src_address_high]
+ shl b32 $r7 16
+ iowr I[$r6 + 0x000] $r7
+ add b32 $r6 0x400
+ ld b32 $r7 D[$r5 + ctx_src_pitch]
+ iowr I[$r6 + 0x000] $r7
+ ret
+
+// wait for regs to be available for use
+cmd_exec_wait:
+ push $r0
+ push $r1
+ mov $r0 0x800
+ shl b32 $r0 6
+ loop:
+ iord $r1 I[$r0]
+ and $r1 1
+ bra ne loop
+ pop $r1
+ pop $r0
+ ret
+
+cmd_exec_query:
+ // if QUERY_SHORT not set, write out { -, 0, TIME_LO, TIME_HI }
+ xbit $r4 $r3 13
+ bra ne query_counter
+ call cmd_exec_wait
+ mov $r4 0x80c
+ shl b32 $r4 6
+ ld b32 $r5 D[$r0 + ctx_query_address_low]
+ add b32 $r5 4
+ iowr I[$r4 + 0x000] $r5
+ iowr I[$r4 + 0x100] $r0
+ mov $r5 0xc
+ iowr I[$r4 + 0x200] $r5
+ add b32 $r4 0x400
+ ld b32 $r5 D[$r0 + ctx_query_address_high]
+ shl b32 $r5 16
+ iowr I[$r4 + 0x000] $r5
+ add b32 $r4 0x500
+ mov $r5 0x00000b00
+ sethi $r5 0x00010000
+ iowr I[$r4 + 0x000] $r5
+ mov $r5 0x00004040
+ shl b32 $r5 1
+ sethi $r5 0x80800000
+ iowr I[$r4 + 0x100] $r5
+ mov $r5 0x00001110
+ sethi $r5 0x13120000
+ iowr I[$r4 + 0x200] $r5
+ mov $r5 0x00001514
+ sethi $r5 0x17160000
+ iowr I[$r4 + 0x300] $r5
+ mov $r5 0x00002601
+ sethi $r5 0x00010000
+ mov $r4 0x800
+ shl b32 $r4 6
+ iowr I[$r4 + 0x000] $r5
+
+ // write COUNTER
+ query_counter:
+ call cmd_exec_wait
+ mov $r4 0x80c
+ shl b32 $r4 6
+ ld b32 $r5 D[$r0 + ctx_query_address_low]
+ iowr I[$r4 + 0x000] $r5
+ iowr I[$r4 + 0x100] $r0
+ mov $r5 0x4
+ iowr I[$r4 + 0x200] $r5
+ add b32 $r4 0x400
+ ld b32 $r5 D[$r0 + ctx_query_address_high]
+ shl b32 $r5 16
+ iowr I[$r4 + 0x000] $r5
+ add b32 $r4 0x500
+ mov $r5 0x00000300
+ iowr I[$r4 + 0x000] $r5
+ mov $r5 0x00001110
+ sethi $r5 0x13120000
+ iowr I[$r4 + 0x100] $r5
+ ld b32 $r5 D[$r0 + ctx_query_counter]
+ add b32 $r4 0x500
+ iowr I[$r4 + 0x000] $r5
+ mov $r5 0x00002601
+ sethi $r5 0x00010000
+ mov $r4 0x800
+ shl b32 $r4 6
+ iowr I[$r4 + 0x000] $r5
+ ret
+
+// Execute a copy operation
+//
+// Inputs:
+// $r1: irqh state
+// $r2: hostirq state
+// $r3: data
+// 000002000 QUERY_SHORT
+// 000001000 QUERY
+// 000000100 DST_LINEAR
+// 000000010 SRC_LINEAR
+// 000000001 FORMAT
+// $r4: dispatch table entry
+// Outputs:
+// $r1: irqh state
+// $p1: set on error
+// $r2: hostirq state
+// $r3: data
+cmd_exec:
+ call cmd_exec_wait
+
+ // if format requested, call function to calculate it, otherwise
+ // fill in cpp/xcnt for both surfaces as if (cpp == 1)
+ xbit $r15 $r3 0
+ bra e cmd_exec_no_format
+ call cmd_exec_set_format
+ mov $r4 0x200
+ bra cmd_exec_init_src_surface
+ cmd_exec_no_format:
+ mov $r6 0x810
+ shl b32 $r6 6
+ mov $r7 1
+ st b32 D[$r0 + ctx_src_cpp] $r7
+ st b32 D[$r0 + ctx_dst_cpp] $r7
+ ld b32 $r7 D[$r0 + ctx_xcnt]
+ iowr I[$r6 + 0x000] $r7
+ iowr I[$r6 + 0x100] $r7
+ clear b32 $r4
+
+ cmd_exec_init_src_surface:
+ bclr $flags $p2
+ clear b32 $r5
+ xbit $r15 $r3 4
+ bra e src_tiled
+ call cmd_exec_set_surface_linear
+ bra cmd_exec_init_dst_surface
+ src_tiled:
+ call cmd_exec_set_surface_tiled
+ bset $r4 7
+
+ cmd_exec_init_dst_surface:
+ bset $flags $p2
+ mov $r5 ctx_dst_address_high - ctx_src_address_high
+ xbit $r15 $r3 8
+ bra e dst_tiled
+ call cmd_exec_set_surface_linear
+ bra cmd_exec_kick
+ dst_tiled:
+ call cmd_exec_set_surface_tiled
+ bset $r4 8
+
+ cmd_exec_kick:
+ mov $r5 0x800
+ shl b32 $r5 6
+ ld b32 $r6 D[$r0 + ctx_ycnt]
+ iowr I[$r5 + 0x100] $r6
+ mov $r6 0x0041
+ // SRC_TARGET = 1, DST_TARGET = 2
+ sethi $r6 0x44000000
+ or $r4 $r6
+ iowr I[$r5] $r4
+
+ // if requested, queue up a QUERY write after the copy has completed
+ xbit $r15 $r3 12
+ bra e cmd_exec_done
+ call cmd_exec_query
+
+ cmd_exec_done:
+ ret
+
+// Flush write cache
+//
+// Inputs:
+// $r1: irqh state
+// $r2: hostirq state
+// $r3: data
+// $r4: dispatch table entry
+// Outputs:
+// $r1: irqh state
+// $p1: set on error
+// $r2: hostirq state
+// $r3: data
+cmd_wrcache_flush:
+ mov $r2 0x2200
+ clear b32 $r3
+ sethi $r3 0x10000
+ iowr I[$r2] $r3
+ ret
+
+.align 0x100
diff --git a/drivers/gpu/drm/nouveau/nva3_copy.fuc.h b/drivers/gpu/drm/nouveau/nva3_copy.fuc.h
new file mode 100644
index 0000000..2731de2
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nva3_copy.fuc.h
@@ -0,0 +1,534 @@
+uint32_t nva3_pcopy_data[] = {
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00010000,
+ 0x00000000,
+ 0x00000000,
+ 0x00010040,
+ 0x00010160,
+ 0x00000000,
+ 0x00010050,
+ 0x00010162,
+ 0x00000000,
+ 0x00030060,
+ 0x00010170,
+ 0x00000000,
+ 0x00010170,
+ 0x00000000,
+ 0x00010170,
+ 0x00000000,
+ 0x00070080,
+ 0x00000028,
+ 0xfffff000,
+ 0x0000002c,
+ 0xfff80000,
+ 0x00000030,
+ 0xffffe000,
+ 0x00000034,
+ 0xfffff800,
+ 0x00000038,
+ 0xfffff000,
+ 0x0000003c,
+ 0xfff80000,
+ 0x00000040,
+ 0xffffe000,
+ 0x00070088,
+ 0x00000054,
+ 0xfffff000,
+ 0x00000058,
+ 0xfff80000,
+ 0x0000005c,
+ 0xffffe000,
+ 0x00000060,
+ 0xfffff800,
+ 0x00000064,
+ 0xfffff000,
+ 0x00000068,
+ 0xfff80000,
+ 0x0000006c,
+ 0xffffe000,
+ 0x000200c0,
+ 0x00010492,
+ 0x00000000,
+ 0x0001051b,
+ 0x00000000,
+ 0x000e00c3,
+ 0x0000001c,
+ 0xffffff00,
+ 0x00000020,
+ 0x0000000f,
+ 0x00000048,
+ 0xffffff00,
+ 0x0000004c,
+ 0x0000000f,
+ 0x00000024,
+ 0xfff80000,
+ 0x00000050,
+ 0xfff80000,
+ 0x00000080,
+ 0xffff0000,
+ 0x00000084,
+ 0xffffe000,
+ 0x00000074,
+ 0xfccc0000,
+ 0x00000078,
+ 0x00000000,
+ 0x0000007c,
+ 0x00000000,
+ 0x00000010,
+ 0xffffff00,
+ 0x00000014,
+ 0x00000000,
+ 0x00000018,
+ 0x00000000,
+ 0x00000800,
+};
+
+uint32_t nva3_pcopy_code[] = {
+ 0x04fe04bd,
+ 0x3517f000,
+ 0xf10010fe,
+ 0xf1040017,
+ 0xf0fff327,
+ 0x22d00023,
+ 0x0c25f0c0,
+ 0xf40012d0,
+ 0x17f11031,
+ 0x27f01200,
+ 0x0012d003,
+ 0xf40031f4,
+ 0x0ef40028,
+ 0x8001cffd,
+ 0xf40812c4,
+ 0x21f4060b,
+ 0x0412c472,
+ 0xf4060bf4,
+ 0x11c4c321,
+ 0x4001d00c,
+ 0x47f101f8,
+ 0x4bfe7700,
+ 0x0007fe00,
+ 0xf00204b9,
+ 0x01f40643,
+ 0x0604fa09,
+ 0xfa060ef4,
+ 0x03f80504,
+ 0x27f100f8,
+ 0x23cf1400,
+ 0x1e3fc800,
+ 0xf4170bf4,
+ 0x21f40132,
+ 0x1e3af052,
+ 0xf00023d0,
+ 0x24d00147,
+ 0xcf00f880,
+ 0x3dc84023,
+ 0x220bf41e,
+ 0xf40131f4,
+ 0x57f05221,
+ 0x0367f004,
+ 0xa07856bc,
+ 0xb6018068,
+ 0x87d00884,
+ 0x0162b600,
+ 0xf0f018f4,
+ 0x23d00237,
+ 0xf100f880,
+ 0xcf190037,
+ 0x33cf4032,
+ 0xff24e400,
+ 0x1024b607,
+ 0x010057f1,
+ 0x74bd64bd,
+ 0x58005658,
+ 0x50b60157,
+ 0x0446b804,
+ 0xbb4d08f4,
+ 0x47b80076,
+ 0x0f08f404,
+ 0xb60276bb,
+ 0x57bb0374,
+ 0xdf0ef400,
+ 0xb60246bb,
+ 0x45bb0344,
+ 0x01459800,
+ 0xb00453fd,
+ 0x1bf40054,
+ 0x00455820,
+ 0xb0014658,
+ 0x1bf40064,
+ 0x00538009,
+ 0xf4300ef4,
+ 0x55f90132,
+ 0xf40c01f4,
+ 0x25f0250e,
+ 0x0125f002,
+ 0x100047f1,
+ 0xd00042d0,
+ 0x27f04043,
+ 0x0002d040,
+ 0xf08002cf,
+ 0x24b04024,
+ 0xf71bf400,
+ 0x1d0027f1,
+ 0xd00137f0,
+ 0x00f80023,
+ 0x27f100f8,
+ 0x34bd2200,
+ 0xd00233f0,
+ 0x00f80023,
+ 0x012842b7,
+ 0xf00145b6,
+ 0x43801e39,
+ 0x0040b701,
+ 0x0644b606,
+ 0xf80043d0,
+ 0xf030f400,
+ 0xb00001b0,
+ 0x01b00101,
+ 0x0301b002,
+ 0xc71d0498,
+ 0x50b63045,
+ 0x3446c701,
+ 0xc70160b6,
+ 0x70b63847,
+ 0x0232f401,
+ 0x94bd84bd,
+ 0xb60f4ac4,
+ 0xb4bd0445,
+ 0xf404a430,
+ 0xa5ff0f18,
+ 0x00cbbbc0,
+ 0xf40231f4,
+ 0x1bf4220e,
+ 0x10c7f00c,
+ 0xf400cbbb,
+ 0xa430160e,
+ 0x0c18f406,
+ 0xbb14c7f0,
+ 0x0ef400cb,
+ 0x80c7f107,
+ 0x01c83800,
+ 0xb60180b6,
+ 0xb5b801b0,
+ 0xc308f404,
+ 0xb80190b6,
+ 0x08f40497,
+ 0x0065fdb2,
+ 0x98110680,
+ 0x68fd2008,
+ 0x0502f400,
+ 0x75fd64bd,
+ 0x1c078000,
+ 0xf10078fd,
+ 0xb6081057,
+ 0x56d00654,
+ 0x4057d000,
+ 0x080050b7,
+ 0xb61c0698,
+ 0x64b60162,
+ 0x11079808,
+ 0xfd0172b6,
+ 0x56d00567,
+ 0x0050b700,
+ 0x0060b401,
+ 0xb40056d0,
+ 0x56d00160,
+ 0x0260b440,
+ 0xb48056d0,
+ 0x56d00360,
+ 0x0050b7c0,
+ 0x1e069804,
+ 0x980056d0,
+ 0x56d01f06,
+ 0x1030f440,
+ 0x579800f8,
+ 0x6879c70a,
+ 0xb66478c7,
+ 0x77c70280,
+ 0x0e76b060,
+ 0xf0091bf4,
+ 0x0ef40477,
+ 0x027cf00f,
+ 0xfd1170b6,
+ 0x77f00947,
+ 0x0f5a9806,
+ 0xfd115b98,
+ 0xb7f000ab,
+ 0x04b7bb01,
+ 0xff01b2b6,
+ 0xa7bbc4ab,
+ 0x105d9805,
+ 0xbb01e7f0,
+ 0xe2b604e8,
+ 0xb4deff01,
+ 0xb605d8bb,
+ 0xef9401e0,
+ 0x02ebbb0c,
+ 0xf005fefd,
+ 0x60b7026c,
+ 0x64b60208,
+ 0x006fd008,
+ 0xbb04b7bb,
+ 0x5f9800cb,
+ 0x115b980b,
+ 0xf000fbfd,
+ 0xb7bb01b7,
+ 0x01b2b604,
+ 0xbb00fbbb,
+ 0xf0f905f7,
+ 0xf00c5f98,
+ 0xb8bb01b7,
+ 0x01b2b604,
+ 0xbb00fbbb,
+ 0xf0f905f8,
+ 0xb60078bb,
+ 0xb7f00282,
+ 0x04b8bb01,
+ 0x9804b9bb,
+ 0xe7f00e58,
+ 0x04e9bb01,
+ 0xff01e2b6,
+ 0xf7bbf48e,
+ 0x00cfbb04,
+ 0xbb0079bb,
+ 0xf0fc0589,
+ 0xd9fd90fc,
+ 0x00adbb00,
+ 0xfd0089fd,
+ 0xa8bb008f,
+ 0x04a7bb00,
+ 0xbb0192b6,
+ 0x69d00497,
+ 0x08579880,
+ 0xbb075898,
+ 0x7abb00ac,
+ 0x0081b600,
+ 0xfd1084b6,
+ 0x62b7058b,
+ 0x67d00600,
+ 0x0060b700,
+ 0x0068d004,
+ 0x6cf000f8,
+ 0x0260b702,
+ 0x0864b602,
+ 0xd0085798,
+ 0x60b70067,
+ 0x57980400,
+ 0x1074b607,
+ 0xb70067d0,
+ 0x98040060,
+ 0x67d00957,
+ 0xf900f800,
+ 0xf110f900,
+ 0xb6080007,
+ 0x01cf0604,
+ 0x0114f000,
+ 0xfcfa1bf4,
+ 0xf800fc10,
+ 0x0d34c800,
+ 0xf5701bf4,
+ 0xf103ab21,
+ 0xb6080c47,
+ 0x05980644,
+ 0x0450b605,
+ 0xd00045d0,
+ 0x57f04040,
+ 0x8045d00c,
+ 0x040040b7,
+ 0xb6040598,
+ 0x45d01054,
+ 0x0040b700,
+ 0x0057f105,
+ 0x0153f00b,
+ 0xf10045d0,
+ 0xb6404057,
+ 0x53f10154,
+ 0x45d08080,
+ 0x1057f140,
+ 0x1253f111,
+ 0x8045d013,
+ 0x151457f1,
+ 0x171653f1,
+ 0xf1c045d0,
+ 0xf0260157,
+ 0x47f10153,
+ 0x44b60800,
+ 0x0045d006,
+ 0x03ab21f5,
+ 0x080c47f1,
+ 0x980644b6,
+ 0x45d00505,
+ 0x4040d000,
+ 0xd00457f0,
+ 0x40b78045,
+ 0x05980400,
+ 0x1054b604,
+ 0xb70045d0,
+ 0xf1050040,
+ 0xd0030057,
+ 0x57f10045,
+ 0x53f11110,
+ 0x45d01312,
+ 0x06059840,
+ 0x050040b7,
+ 0xf10045d0,
+ 0xf0260157,
+ 0x47f10153,
+ 0x44b60800,
+ 0x0045d006,
+ 0x21f500f8,
+ 0x3fc803ab,
+ 0x0e0bf400,
+ 0x018921f5,
+ 0x020047f1,
+ 0xf11e0ef4,
+ 0xb6081067,
+ 0x77f00664,
+ 0x11078001,
+ 0x981c0780,
+ 0x67d02007,
+ 0x4067d000,
+ 0x32f444bd,
+ 0xc854bd02,
+ 0x0bf4043f,
+ 0x8221f50a,
+ 0x0a0ef403,
+ 0x027621f5,
+ 0xf40749f0,
+ 0x57f00231,
+ 0x083fc82c,
+ 0xf50a0bf4,
+ 0xf4038221,
+ 0x21f50a0e,
+ 0x49f00276,
+ 0x0057f108,
+ 0x0654b608,
+ 0xd0210698,
+ 0x67f04056,
+ 0x0063f141,
+ 0x0546fd44,
+ 0xc80054d0,
+ 0x0bf40c3f,
+ 0xc521f507,
+ 0xf100f803,
+ 0xbd220027,
+ 0x0133f034,
+ 0xf80023d0,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+};
diff --git a/drivers/gpu/drm/nouveau/nva3_pm.c b/drivers/gpu/drm/nouveau/nva3_pm.c
index dbbafed..e4b2b9e 100644
--- a/drivers/gpu/drm/nouveau/nva3_pm.c
+++ b/drivers/gpu/drm/nouveau/nva3_pm.c
@@ -27,32 +27,74 @@
#include "nouveau_bios.h"
#include "nouveau_pm.h"
-/*XXX: boards using limits 0x40 need fixing, the register layout
- * is correct here, but, there's some other funny magic
- * that modifies things, so it's not likely we'll set/read
- * the correct timings yet.. working on it...
+/* This is actually a lot more complex than it appears here, but hopefully
+ * this should be able to deal with what the VBIOS leaves for us..
+ *
+ * If not, well, I'll jump off that bridge when I come to it.
*/
struct nva3_pm_state {
- struct pll_lims pll;
- int N, M, P;
+ enum pll_types type;
+ u32 src0;
+ u32 src1;
+ u32 ctrl;
+ u32 coef;
+ u32 old_pnm;
+ u32 new_pnm;
+ u32 new_div;
};
+static int
+nva3_pm_pll_offset(u32 id)
+{
+ static const u32 pll_map[] = {
+ 0x00, PLL_CORE,
+ 0x01, PLL_SHADER,
+ 0x02, PLL_MEMORY,
+ 0x00, 0x00
+ };
+ const u32 *map = pll_map;
+
+ while (map[1]) {
+ if (id == map[1])
+ return map[0];
+ map += 2;
+ }
+
+ return -ENOENT;
+}
+
int
nva3_pm_clock_get(struct drm_device *dev, u32 id)
{
+ u32 src0, src1, ctrl, coef;
struct pll_lims pll;
- int P, N, M, ret;
- u32 reg;
+ int ret, off;
+ int P, N, M;
ret = get_pll_limits(dev, id, &pll);
if (ret)
return ret;
- reg = nv_rd32(dev, pll.reg + 4);
- P = (reg & 0x003f0000) >> 16;
- N = (reg & 0x0000ff00) >> 8;
- M = (reg & 0x000000ff);
+ off = nva3_pm_pll_offset(id);
+ if (off < 0)
+ return off;
+
+ src0 = nv_rd32(dev, 0x4120 + (off * 4));
+ src1 = nv_rd32(dev, 0x4160 + (off * 4));
+ ctrl = nv_rd32(dev, pll.reg + 0);
+ coef = nv_rd32(dev, pll.reg + 4);
+ NV_DEBUG(dev, "PLL %02x: 0x%08x 0x%08x 0x%08x 0x%08x\n",
+ id, src0, src1, ctrl, coef);
+
+ if (ctrl & 0x00000008) {
+ u32 div = ((src1 & 0x003c0000) >> 18) + 1;
+ return (pll.refclk * 2) / div;
+ }
+
+ P = (coef & 0x003f0000) >> 16;
+ N = (coef & 0x0000ff00) >> 8;
+ M = (coef & 0x000000ff);
return pll.refclk * N / M / P;
}
@@ -60,36 +102,103 @@
nva3_pm_clock_pre(struct drm_device *dev, struct nouveau_pm_level *perflvl,
u32 id, int khz)
{
- struct nva3_pm_state *state;
- int dummy, ret;
+ struct nva3_pm_state *pll;
+ struct pll_lims limits;
+ int N, M, P, diff;
+ int ret, off;
- state = kzalloc(sizeof(*state), GFP_KERNEL);
- if (!state)
- return ERR_PTR(-ENOMEM);
-
- ret = get_pll_limits(dev, id, &state->pll);
- if (ret < 0) {
- kfree(state);
+ ret = get_pll_limits(dev, id, &limits);
+ if (ret < 0)
return (ret == -ENOENT) ? NULL : ERR_PTR(ret);
+
+ off = nva3_pm_pll_offset(id);
+ if (id < 0)
+ return ERR_PTR(-EINVAL);
+
+
+ pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+ if (!pll)
+ return ERR_PTR(-ENOMEM);
+ pll->type = id;
+ pll->src0 = 0x004120 + (off * 4);
+ pll->src1 = 0x004160 + (off * 4);
+ pll->ctrl = limits.reg + 0;
+ pll->coef = limits.reg + 4;
+
+ /* If target clock is within [-2, 3) MHz of a divisor, we'll
+ * use that instead of calculating MNP values
+ */
+ pll->new_div = min((limits.refclk * 2) / (khz - 2999), 16);
+ if (pll->new_div) {
+ diff = khz - ((limits.refclk * 2) / pll->new_div);
+ if (diff < -2000 || diff >= 3000)
+ pll->new_div = 0;
}
- ret = nv50_calc_pll2(dev, &state->pll, khz, &state->N, &dummy,
- &state->M, &state->P);
- if (ret < 0) {
- kfree(state);
- return ERR_PTR(ret);
+ if (!pll->new_div) {
+ ret = nva3_calc_pll(dev, &limits, khz, &N, NULL, &M, &P);
+ if (ret < 0)
+ return ERR_PTR(ret);
+
+ pll->new_pnm = (P << 16) | (N << 8) | M;
+ pll->new_div = 2 - 1;
+ } else {
+ pll->new_pnm = 0;
+ pll->new_div--;
}
- return state;
+ if ((nv_rd32(dev, pll->src1) & 0x00000101) != 0x00000101)
+ pll->old_pnm = nv_rd32(dev, pll->coef);
+ return pll;
}
void
nva3_pm_clock_set(struct drm_device *dev, void *pre_state)
{
- struct nva3_pm_state *state = pre_state;
- u32 reg = state->pll.reg;
+ struct nva3_pm_state *pll = pre_state;
+ u32 ctrl = 0;
- nv_wr32(dev, reg + 4, (state->P << 16) | (state->N << 8) | state->M);
- kfree(state);
+ /* For the memory clock, NVIDIA will build a "script" describing
+ * the reclocking process and ask PDAEMON to execute it.
+ */
+ if (pll->type == PLL_MEMORY) {
+ nv_wr32(dev, 0x100210, 0);
+ nv_wr32(dev, 0x1002dc, 1);
+ nv_wr32(dev, 0x004018, 0x00001000);
+ ctrl = 0x18000100;
+ }
+
+ if (pll->old_pnm || !pll->new_pnm) {
+ nv_mask(dev, pll->src1, 0x003c0101, 0x00000101 |
+ (pll->new_div << 18));
+ nv_wr32(dev, pll->ctrl, 0x0001001d | ctrl);
+ nv_mask(dev, pll->ctrl, 0x00000001, 0x00000000);
+ }
+
+ if (pll->new_pnm) {
+ nv_mask(dev, pll->src0, 0x00000101, 0x00000101);
+ nv_wr32(dev, pll->coef, pll->new_pnm);
+ nv_wr32(dev, pll->ctrl, 0x0001001d | ctrl);
+ nv_mask(dev, pll->ctrl, 0x00000010, 0x00000000);
+ nv_mask(dev, pll->ctrl, 0x00020010, 0x00020010);
+ nv_wr32(dev, pll->ctrl, 0x00010015 | ctrl);
+ nv_mask(dev, pll->src1, 0x00000100, 0x00000000);
+ nv_mask(dev, pll->src1, 0x00000001, 0x00000000);
+ if (pll->type == PLL_MEMORY)
+ nv_wr32(dev, 0x4018, 0x10005000);
+ } else {
+ nv_mask(dev, pll->ctrl, 0x00000001, 0x00000000);
+ nv_mask(dev, pll->src0, 0x00000100, 0x00000000);
+ nv_mask(dev, pll->src0, 0x00000001, 0x00000000);
+ if (pll->type == PLL_MEMORY)
+ nv_wr32(dev, 0x4018, 0x1000d000);
+ }
+
+ if (pll->type == PLL_MEMORY) {
+ nv_wr32(dev, 0x1002dc, 0);
+ nv_wr32(dev, 0x100210, 0x80000000);
+ }
+
+ kfree(pll);
}
diff --git a/drivers/gpu/drm/nouveau/nvc0_copy.c b/drivers/gpu/drm/nouveau/nvc0_copy.c
new file mode 100644
index 0000000..208fa7a
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvc0_copy.c
@@ -0,0 +1,243 @@
+/*
+ * Copyright 2011 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs
+ */
+
+#include <linux/firmware.h>
+#include "drmP.h"
+#include "nouveau_drv.h"
+#include "nouveau_util.h"
+#include "nouveau_vm.h"
+#include "nouveau_ramht.h"
+#include "nvc0_copy.fuc.h"
+
+struct nvc0_copy_engine {
+ struct nouveau_exec_engine base;
+ u32 irq;
+ u32 pmc;
+ u32 fuc;
+ u32 ctx;
+};
+
+static int
+nvc0_copy_context_new(struct nouveau_channel *chan, int engine)
+{
+ struct nvc0_copy_engine *pcopy = nv_engine(chan->dev, engine);
+ struct drm_device *dev = chan->dev;
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+ struct nouveau_gpuobj *ramin = chan->ramin;
+ struct nouveau_gpuobj *ctx = NULL;
+ int ret;
+
+ ret = nouveau_gpuobj_new(dev, NULL, 256, 256,
+ NVOBJ_FLAG_VM | NVOBJ_FLAG_VM_USER |
+ NVOBJ_FLAG_ZERO_ALLOC, &ctx);
+ if (ret)
+ return ret;
+
+ nv_wo32(ramin, pcopy->ctx + 0, lower_32_bits(ctx->vinst));
+ nv_wo32(ramin, pcopy->ctx + 4, upper_32_bits(ctx->vinst));
+ dev_priv->engine.instmem.flush(dev);
+
+ chan->engctx[engine] = ctx;
+ return 0;
+}
+
+static int
+nvc0_copy_object_new(struct nouveau_channel *chan, int engine,
+ u32 handle, u16 class)
+{
+ return 0;
+}
+
+static void
+nvc0_copy_context_del(struct nouveau_channel *chan, int engine)
+{
+ struct nvc0_copy_engine *pcopy = nv_engine(chan->dev, engine);
+ struct nouveau_gpuobj *ctx = chan->engctx[engine];
+ struct drm_device *dev = chan->dev;
+ u32 inst;
+
+ inst = (chan->ramin->vinst >> 12);
+ inst |= 0x40000000;
+
+ /* disable fifo access */
+ nv_wr32(dev, pcopy->fuc + 0x048, 0x00000000);
+ /* mark channel as unloaded if it's currently active */
+ if (nv_rd32(dev, pcopy->fuc + 0x050) == inst)
+ nv_mask(dev, pcopy->fuc + 0x050, 0x40000000, 0x00000000);
+ /* mark next channel as invalid if it's about to be loaded */
+ if (nv_rd32(dev, pcopy->fuc + 0x054) == inst)
+ nv_mask(dev, pcopy->fuc + 0x054, 0x40000000, 0x00000000);
+ /* restore fifo access */
+ nv_wr32(dev, pcopy->fuc + 0x048, 0x00000003);
+
+ nv_wo32(chan->ramin, pcopy->ctx + 0, 0x00000000);
+ nv_wo32(chan->ramin, pcopy->ctx + 4, 0x00000000);
+ nouveau_gpuobj_ref(NULL, &ctx);
+
+ chan->engctx[engine] = ctx;
+}
+
+static int
+nvc0_copy_init(struct drm_device *dev, int engine)
+{
+ struct nvc0_copy_engine *pcopy = nv_engine(dev, engine);
+ int i;
+
+ nv_mask(dev, 0x000200, pcopy->pmc, 0x00000000);
+ nv_mask(dev, 0x000200, pcopy->pmc, pcopy->pmc);
+ nv_wr32(dev, pcopy->fuc + 0x014, 0xffffffff);
+
+ nv_wr32(dev, pcopy->fuc + 0x1c0, 0x01000000);
+ for (i = 0; i < sizeof(nvc0_pcopy_data) / 4; i++)
+ nv_wr32(dev, pcopy->fuc + 0x1c4, nvc0_pcopy_data[i]);
+
+ nv_wr32(dev, pcopy->fuc + 0x180, 0x01000000);
+ for (i = 0; i < sizeof(nvc0_pcopy_code) / 4; i++) {
+ if ((i & 0x3f) == 0)
+ nv_wr32(dev, pcopy->fuc + 0x188, i >> 6);
+ nv_wr32(dev, pcopy->fuc + 0x184, nvc0_pcopy_code[i]);
+ }
+
+ nv_wr32(dev, pcopy->fuc + 0x084, engine - NVOBJ_ENGINE_COPY0);
+ nv_wr32(dev, pcopy->fuc + 0x10c, 0x00000000);
+ nv_wr32(dev, pcopy->fuc + 0x104, 0x00000000); /* ENTRY */
+ nv_wr32(dev, pcopy->fuc + 0x100, 0x00000002); /* TRIGGER */
+ return 0;
+}
+
+static int
+nvc0_copy_fini(struct drm_device *dev, int engine)
+{
+ struct nvc0_copy_engine *pcopy = nv_engine(dev, engine);
+
+ nv_mask(dev, pcopy->fuc + 0x048, 0x00000003, 0x00000000);
+
+ /* trigger fuc context unload */
+ nv_wait(dev, pcopy->fuc + 0x008, 0x0000000c, 0x00000000);
+ nv_mask(dev, pcopy->fuc + 0x054, 0x40000000, 0x00000000);
+ nv_wr32(dev, pcopy->fuc + 0x000, 0x00000008);
+ nv_wait(dev, pcopy->fuc + 0x008, 0x00000008, 0x00000000);
+
+ nv_wr32(dev, pcopy->fuc + 0x014, 0xffffffff);
+ return 0;
+}
+
+static struct nouveau_enum nvc0_copy_isr_error_name[] = {
+ { 0x0001, "ILLEGAL_MTHD" },
+ { 0x0002, "INVALID_ENUM" },
+ { 0x0003, "INVALID_BITFIELD" },
+ {}
+};
+
+static void
+nvc0_copy_isr(struct drm_device *dev, int engine)
+{
+ struct nvc0_copy_engine *pcopy = nv_engine(dev, engine);
+ u32 disp = nv_rd32(dev, pcopy->fuc + 0x01c);
+ u32 stat = nv_rd32(dev, pcopy->fuc + 0x008) & disp & ~(disp >> 16);
+ u64 inst = (u64)(nv_rd32(dev, pcopy->fuc + 0x050) & 0x0fffffff) << 12;
+ u32 chid = nvc0_graph_isr_chid(dev, inst);
+ u32 ssta = nv_rd32(dev, pcopy->fuc + 0x040) & 0x0000ffff;
+ u32 addr = nv_rd32(dev, pcopy->fuc + 0x040) >> 16;
+ u32 mthd = (addr & 0x07ff) << 2;
+ u32 subc = (addr & 0x3800) >> 11;
+ u32 data = nv_rd32(dev, pcopy->fuc + 0x044);
+
+ if (stat & 0x00000040) {
+ NV_INFO(dev, "PCOPY: DISPATCH_ERROR [");
+ nouveau_enum_print(nvc0_copy_isr_error_name, ssta);
+ printk("] ch %d [0x%010llx] subc %d mthd 0x%04x data 0x%08x\n",
+ chid, inst, subc, mthd, data);
+ nv_wr32(dev, pcopy->fuc + 0x004, 0x00000040);
+ stat &= ~0x00000040;
+ }
+
+ if (stat) {
+ NV_INFO(dev, "PCOPY: unhandled intr 0x%08x\n", stat);
+ nv_wr32(dev, pcopy->fuc + 0x004, stat);
+ }
+}
+
+static void
+nvc0_copy_isr_0(struct drm_device *dev)
+{
+ nvc0_copy_isr(dev, NVOBJ_ENGINE_COPY0);
+}
+
+static void
+nvc0_copy_isr_1(struct drm_device *dev)
+{
+ nvc0_copy_isr(dev, NVOBJ_ENGINE_COPY1);
+}
+
+static void
+nvc0_copy_destroy(struct drm_device *dev, int engine)
+{
+ struct nvc0_copy_engine *pcopy = nv_engine(dev, engine);
+
+ nouveau_irq_unregister(dev, pcopy->irq);
+
+ if (engine == NVOBJ_ENGINE_COPY0)
+ NVOBJ_ENGINE_DEL(dev, COPY0);
+ else
+ NVOBJ_ENGINE_DEL(dev, COPY1);
+ kfree(pcopy);
+}
+
+int
+nvc0_copy_create(struct drm_device *dev, int engine)
+{
+ struct nvc0_copy_engine *pcopy;
+
+ pcopy = kzalloc(sizeof(*pcopy), GFP_KERNEL);
+ if (!pcopy)
+ return -ENOMEM;
+
+ pcopy->base.destroy = nvc0_copy_destroy;
+ pcopy->base.init = nvc0_copy_init;
+ pcopy->base.fini = nvc0_copy_fini;
+ pcopy->base.context_new = nvc0_copy_context_new;
+ pcopy->base.context_del = nvc0_copy_context_del;
+ pcopy->base.object_new = nvc0_copy_object_new;
+
+ if (engine == 0) {
+ pcopy->irq = 5;
+ pcopy->pmc = 0x00000040;
+ pcopy->fuc = 0x104000;
+ pcopy->ctx = 0x0230;
+ nouveau_irq_register(dev, pcopy->irq, nvc0_copy_isr_0);
+ NVOBJ_ENGINE_ADD(dev, COPY0, &pcopy->base);
+ NVOBJ_CLASS(dev, 0x90b5, COPY0);
+ } else {
+ pcopy->irq = 6;
+ pcopy->pmc = 0x00000080;
+ pcopy->fuc = 0x105000;
+ pcopy->ctx = 0x0240;
+ nouveau_irq_register(dev, pcopy->irq, nvc0_copy_isr_1);
+ NVOBJ_ENGINE_ADD(dev, COPY1, &pcopy->base);
+ NVOBJ_CLASS(dev, 0x90b8, COPY1);
+ }
+
+ return 0;
+}
diff --git a/drivers/gpu/drm/nouveau/nvc0_copy.fuc.h b/drivers/gpu/drm/nouveau/nvc0_copy.fuc.h
new file mode 100644
index 0000000..4199038
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvc0_copy.fuc.h
@@ -0,0 +1,527 @@
+uint32_t nvc0_pcopy_data[] = {
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00010000,
+ 0x00000000,
+ 0x00000000,
+ 0x00010040,
+ 0x0001019f,
+ 0x00000000,
+ 0x00010050,
+ 0x000101a1,
+ 0x00000000,
+ 0x00070080,
+ 0x0000001c,
+ 0xfffff000,
+ 0x00000020,
+ 0xfff80000,
+ 0x00000024,
+ 0xffffe000,
+ 0x00000028,
+ 0xfffff800,
+ 0x0000002c,
+ 0xfffff000,
+ 0x00000030,
+ 0xfff80000,
+ 0x00000034,
+ 0xffffe000,
+ 0x00070088,
+ 0x00000048,
+ 0xfffff000,
+ 0x0000004c,
+ 0xfff80000,
+ 0x00000050,
+ 0xffffe000,
+ 0x00000054,
+ 0xfffff800,
+ 0x00000058,
+ 0xfffff000,
+ 0x0000005c,
+ 0xfff80000,
+ 0x00000060,
+ 0xffffe000,
+ 0x000200c0,
+ 0x000104b8,
+ 0x00000000,
+ 0x00010541,
+ 0x00000000,
+ 0x000e00c3,
+ 0x00000010,
+ 0xffffff00,
+ 0x00000014,
+ 0x0000000f,
+ 0x0000003c,
+ 0xffffff00,
+ 0x00000040,
+ 0x0000000f,
+ 0x00000018,
+ 0xfff80000,
+ 0x00000044,
+ 0xfff80000,
+ 0x00000074,
+ 0xffff0000,
+ 0x00000078,
+ 0xffffe000,
+ 0x00000068,
+ 0xfccc0000,
+ 0x0000006c,
+ 0x00000000,
+ 0x00000070,
+ 0x00000000,
+ 0x00000004,
+ 0xffffff00,
+ 0x00000008,
+ 0x00000000,
+ 0x0000000c,
+ 0x00000000,
+ 0x00000800,
+};
+
+uint32_t nvc0_pcopy_code[] = {
+ 0x04fe04bd,
+ 0x3517f000,
+ 0xf10010fe,
+ 0xf1040017,
+ 0xf0fff327,
+ 0x22d00023,
+ 0x0c25f0c0,
+ 0xf40012d0,
+ 0x17f11031,
+ 0x27f01200,
+ 0x0012d003,
+ 0xf40031f4,
+ 0x0ef40028,
+ 0x8001cffd,
+ 0xf40812c4,
+ 0x21f4060b,
+ 0x0412c4ca,
+ 0xf5070bf4,
+ 0xc4010221,
+ 0x01d00c11,
+ 0xf101f840,
+ 0xfe770047,
+ 0x47f1004b,
+ 0x44cf2100,
+ 0x0144f000,
+ 0xb60444b6,
+ 0xf7f13040,
+ 0xf4b6061c,
+ 0x1457f106,
+ 0x00f5d101,
+ 0xb6043594,
+ 0x57fe0250,
+ 0x0145fe00,
+ 0x010052b7,
+ 0x00ff67f1,
+ 0x56fd60bd,
+ 0x0253f004,
+ 0xf80545fa,
+ 0x0053f003,
+ 0xd100e7f0,
+ 0x549800fe,
+ 0x0845b600,
+ 0xb6015698,
+ 0x46fd1864,
+ 0x0047fe05,
+ 0xf00204b9,
+ 0x01f40643,
+ 0x0604fa09,
+ 0xfa060ef4,
+ 0x03f80504,
+ 0x27f100f8,
+ 0x23cf1400,
+ 0x1e3fc800,
+ 0xf4170bf4,
+ 0x21f40132,
+ 0x1e3af053,
+ 0xf00023d0,
+ 0x24d00147,
+ 0xcf00f880,
+ 0x3dc84023,
+ 0x090bf41e,
+ 0xf40131f4,
+ 0x37f05321,
+ 0x8023d002,
+ 0x37f100f8,
+ 0x32cf1900,
+ 0x0033cf40,
+ 0x07ff24e4,
+ 0xf11024b6,
+ 0xbd010057,
+ 0x5874bd64,
+ 0x57580056,
+ 0x0450b601,
+ 0xf40446b8,
+ 0x76bb4d08,
+ 0x0447b800,
+ 0xbb0f08f4,
+ 0x74b60276,
+ 0x0057bb03,
+ 0xbbdf0ef4,
+ 0x44b60246,
+ 0x0045bb03,
+ 0xfd014598,
+ 0x54b00453,
+ 0x201bf400,
+ 0x58004558,
+ 0x64b00146,
+ 0x091bf400,
+ 0xf4005380,
+ 0x32f4300e,
+ 0xf455f901,
+ 0x0ef40c01,
+ 0x0225f025,
+ 0xf10125f0,
+ 0xd0100047,
+ 0x43d00042,
+ 0x4027f040,
+ 0xcf0002d0,
+ 0x24f08002,
+ 0x0024b040,
+ 0xf1f71bf4,
+ 0xf01d0027,
+ 0x23d00137,
+ 0xf800f800,
+ 0x0027f100,
+ 0xf034bd22,
+ 0x23d00233,
+ 0xf400f800,
+ 0x01b0f030,
+ 0x0101b000,
+ 0xb00201b0,
+ 0x04980301,
+ 0x3045c71a,
+ 0xc70150b6,
+ 0x60b63446,
+ 0x3847c701,
+ 0xf40170b6,
+ 0x84bd0232,
+ 0x4ac494bd,
+ 0x0445b60f,
+ 0xa430b4bd,
+ 0x0f18f404,
+ 0xbbc0a5ff,
+ 0x31f400cb,
+ 0x220ef402,
+ 0xf00c1bf4,
+ 0xcbbb10c7,
+ 0x160ef400,
+ 0xf406a430,
+ 0xc7f00c18,
+ 0x00cbbb14,
+ 0xf1070ef4,
+ 0x380080c7,
+ 0x80b601c8,
+ 0x01b0b601,
+ 0xf404b5b8,
+ 0x90b6c308,
+ 0x0497b801,
+ 0xfdb208f4,
+ 0x06800065,
+ 0x1d08980e,
+ 0xf40068fd,
+ 0x64bd0502,
+ 0x800075fd,
+ 0x78fd1907,
+ 0x1057f100,
+ 0x0654b608,
+ 0xd00056d0,
+ 0x50b74057,
+ 0x06980800,
+ 0x0162b619,
+ 0x980864b6,
+ 0x72b60e07,
+ 0x0567fd01,
+ 0xb70056d0,
+ 0xb4010050,
+ 0x56d00060,
+ 0x0160b400,
+ 0xb44056d0,
+ 0x56d00260,
+ 0x0360b480,
+ 0xb7c056d0,
+ 0x98040050,
+ 0x56d01b06,
+ 0x1c069800,
+ 0xf44056d0,
+ 0x00f81030,
+ 0xc7075798,
+ 0x78c76879,
+ 0x0380b664,
+ 0xb06077c7,
+ 0x1bf40e76,
+ 0x0477f009,
+ 0xf00f0ef4,
+ 0x70b6027c,
+ 0x0947fd11,
+ 0x980677f0,
+ 0x5b980c5a,
+ 0x00abfd0e,
+ 0xbb01b7f0,
+ 0xb2b604b7,
+ 0xc4abff01,
+ 0x9805a7bb,
+ 0xe7f00d5d,
+ 0x04e8bb01,
+ 0xff01e2b6,
+ 0xd8bbb4de,
+ 0x01e0b605,
+ 0xbb0cef94,
+ 0xfefd02eb,
+ 0x026cf005,
+ 0x020860b7,
+ 0xd00864b6,
+ 0xb7bb006f,
+ 0x00cbbb04,
+ 0x98085f98,
+ 0xfbfd0e5b,
+ 0x01b7f000,
+ 0xb604b7bb,
+ 0xfbbb01b2,
+ 0x05f7bb00,
+ 0x5f98f0f9,
+ 0x01b7f009,
+ 0xb604b8bb,
+ 0xfbbb01b2,
+ 0x05f8bb00,
+ 0x78bbf0f9,
+ 0x0282b600,
+ 0xbb01b7f0,
+ 0xb9bb04b8,
+ 0x0b589804,
+ 0xbb01e7f0,
+ 0xe2b604e9,
+ 0xf48eff01,
+ 0xbb04f7bb,
+ 0x79bb00cf,
+ 0x0589bb00,
+ 0x90fcf0fc,
+ 0xbb00d9fd,
+ 0x89fd00ad,
+ 0x008ffd00,
+ 0xbb00a8bb,
+ 0x92b604a7,
+ 0x0497bb01,
+ 0x988069d0,
+ 0x58980557,
+ 0x00acbb04,
+ 0xb6007abb,
+ 0x84b60081,
+ 0x058bfd10,
+ 0x060062b7,
+ 0xb70067d0,
+ 0xd0040060,
+ 0x00f80068,
+ 0xb7026cf0,
+ 0xb6020260,
+ 0x57980864,
+ 0x0067d005,
+ 0x040060b7,
+ 0xb6045798,
+ 0x67d01074,
+ 0x0060b700,
+ 0x06579804,
+ 0xf80067d0,
+ 0xf900f900,
+ 0x0007f110,
+ 0x0604b608,
+ 0xf00001cf,
+ 0x1bf40114,
+ 0xfc10fcfa,
+ 0xc800f800,
+ 0x1bf40d34,
+ 0xd121f570,
+ 0x0c47f103,
+ 0x0644b608,
+ 0xb6020598,
+ 0x45d00450,
+ 0x4040d000,
+ 0xd00c57f0,
+ 0x40b78045,
+ 0x05980400,
+ 0x1054b601,
+ 0xb70045d0,
+ 0xf1050040,
+ 0xf00b0057,
+ 0x45d00153,
+ 0x4057f100,
+ 0x0154b640,
+ 0x808053f1,
+ 0xf14045d0,
+ 0xf1111057,
+ 0xd0131253,
+ 0x57f18045,
+ 0x53f11514,
+ 0x45d01716,
+ 0x0157f1c0,
+ 0x0153f026,
+ 0x080047f1,
+ 0xd00644b6,
+ 0x21f50045,
+ 0x47f103d1,
+ 0x44b6080c,
+ 0x02059806,
+ 0xd00045d0,
+ 0x57f04040,
+ 0x8045d004,
+ 0x040040b7,
+ 0xb6010598,
+ 0x45d01054,
+ 0x0040b700,
+ 0x0057f105,
+ 0x0045d003,
+ 0x111057f1,
+ 0x131253f1,
+ 0x984045d0,
+ 0x40b70305,
+ 0x45d00500,
+ 0x0157f100,
+ 0x0153f026,
+ 0x080047f1,
+ 0xd00644b6,
+ 0x00f80045,
+ 0x03d121f5,
+ 0xf4003fc8,
+ 0x21f50e0b,
+ 0x47f101af,
+ 0x0ef40200,
+ 0x1067f11e,
+ 0x0664b608,
+ 0x800177f0,
+ 0x07800e07,
+ 0x1d079819,
+ 0xd00067d0,
+ 0x44bd4067,
+ 0xbd0232f4,
+ 0x043fc854,
+ 0xf50a0bf4,
+ 0xf403a821,
+ 0x21f50a0e,
+ 0x49f0029c,
+ 0x0231f407,
+ 0xc82c57f0,
+ 0x0bf4083f,
+ 0xa821f50a,
+ 0x0a0ef403,
+ 0x029c21f5,
+ 0xf10849f0,
+ 0xb6080057,
+ 0x06980654,
+ 0x4056d01e,
+ 0xf14167f0,
+ 0xfd440063,
+ 0x54d00546,
+ 0x0c3fc800,
+ 0xf5070bf4,
+ 0xf803eb21,
+ 0x0027f100,
+ 0xf034bd22,
+ 0x23d00133,
+ 0x0000f800,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+ 0x00000000,
+};
diff --git a/drivers/gpu/drm/nouveau/nvc0_fifo.c b/drivers/gpu/drm/nouveau/nvc0_fifo.c
index 2886f27..fb4f594 100644
--- a/drivers/gpu/drm/nouveau/nvc0_fifo.c
+++ b/drivers/gpu/drm/nouveau/nvc0_fifo.c
@@ -37,7 +37,7 @@
};
struct nvc0_fifo_chan {
- struct nouveau_bo *user;
+ struct nouveau_gpuobj *user;
struct nouveau_gpuobj *ramfc;
};
@@ -106,7 +106,7 @@
struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
struct nvc0_fifo_priv *priv = pfifo->priv;
struct nvc0_fifo_chan *fifoch;
- u64 ib_virt, user_vinst;
+ u64 ib_virt = chan->pushbuf_base + chan->dma.ib_base * 4;
int ret;
chan->fifo_priv = kzalloc(sizeof(*fifoch), GFP_KERNEL);
@@ -115,28 +115,13 @@
fifoch = chan->fifo_priv;
/* allocate vram for control regs, map into polling area */
- ret = nouveau_bo_new(dev, NULL, 0x1000, 0, TTM_PL_FLAG_VRAM,
- 0, 0, &fifoch->user);
+ ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 0x1000,
+ NVOBJ_FLAG_ZERO_ALLOC, &fifoch->user);
if (ret)
goto error;
- ret = nouveau_bo_pin(fifoch->user, TTM_PL_FLAG_VRAM);
- if (ret) {
- nouveau_bo_ref(NULL, &fifoch->user);
- goto error;
- }
-
- user_vinst = fifoch->user->bo.mem.start << PAGE_SHIFT;
-
- ret = nouveau_bo_map(fifoch->user);
- if (ret) {
- nouveau_bo_unpin(fifoch->user);
- nouveau_bo_ref(NULL, &fifoch->user);
- goto error;
- }
-
nouveau_vm_map_at(&priv->user_vma, chan->id * 0x1000,
- fifoch->user->bo.mem.mm_node);
+ *(struct nouveau_mem **)fifoch->user->node);
chan->user = ioremap_wc(pci_resource_start(dev->pdev, 1) +
priv->user_vma.offset + (chan->id * 0x1000),
@@ -146,20 +131,6 @@
goto error;
}
- ib_virt = chan->pushbuf_base + chan->dma.ib_base * 4;
-
- /* zero channel regs */
- nouveau_bo_wr32(fifoch->user, 0x0040/4, 0);
- nouveau_bo_wr32(fifoch->user, 0x0044/4, 0);
- nouveau_bo_wr32(fifoch->user, 0x0048/4, 0);
- nouveau_bo_wr32(fifoch->user, 0x004c/4, 0);
- nouveau_bo_wr32(fifoch->user, 0x0050/4, 0);
- nouveau_bo_wr32(fifoch->user, 0x0058/4, 0);
- nouveau_bo_wr32(fifoch->user, 0x005c/4, 0);
- nouveau_bo_wr32(fifoch->user, 0x0060/4, 0);
- nouveau_bo_wr32(fifoch->user, 0x0088/4, 0);
- nouveau_bo_wr32(fifoch->user, 0x008c/4, 0);
-
/* ramfc */
ret = nouveau_gpuobj_new_fake(dev, chan->ramin->pinst,
chan->ramin->vinst, 0x100,
@@ -167,8 +138,8 @@
if (ret)
goto error;
- nv_wo32(fifoch->ramfc, 0x08, lower_32_bits(user_vinst));
- nv_wo32(fifoch->ramfc, 0x0c, upper_32_bits(user_vinst));
+ nv_wo32(fifoch->ramfc, 0x08, lower_32_bits(fifoch->user->vinst));
+ nv_wo32(fifoch->ramfc, 0x0c, upper_32_bits(fifoch->user->vinst));
nv_wo32(fifoch->ramfc, 0x10, 0x0000face);
nv_wo32(fifoch->ramfc, 0x30, 0xfffff902);
nv_wo32(fifoch->ramfc, 0x48, lower_32_bits(ib_virt));
@@ -223,11 +194,7 @@
return;
nouveau_gpuobj_ref(NULL, &fifoch->ramfc);
- if (fifoch->user) {
- nouveau_bo_unmap(fifoch->user);
- nouveau_bo_unpin(fifoch->user);
- nouveau_bo_ref(NULL, &fifoch->user);
- }
+ nouveau_gpuobj_ref(NULL, &fifoch->user);
kfree(fifoch);
}
@@ -240,6 +207,21 @@
int
nvc0_fifo_unload_context(struct drm_device *dev)
{
+ int i;
+
+ for (i = 0; i < 128; i++) {
+ if (!(nv_rd32(dev, 0x003004 + (i * 4)) & 1))
+ continue;
+
+ nv_mask(dev, 0x003004 + (i * 4), 0x00000001, 0x00000000);
+ nv_wr32(dev, 0x002634, i);
+ if (!nv_wait(dev, 0x002634, 0xffffffff, i)) {
+ NV_INFO(dev, "PFIFO: kick ch %d failed: 0x%08x\n",
+ i, nv_rd32(dev, 0x002634));
+ return -EBUSY;
+ }
+ }
+
return 0;
}
@@ -309,6 +291,7 @@
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_fifo_engine *pfifo = &dev_priv->engine.fifo;
+ struct nouveau_channel *chan;
struct nvc0_fifo_priv *priv;
int ret, i;
@@ -351,23 +334,74 @@
nv_wr32(dev, 0x002a00, 0xffffffff); /* clears PFIFO.INTR bit 30 */
nv_wr32(dev, 0x002100, 0xffffffff);
nv_wr32(dev, 0x002140, 0xbfffffff);
+
+ /* restore PFIFO context table */
+ for (i = 0; i < 128; i++) {
+ chan = dev_priv->channels.ptr[i];
+ if (!chan || !chan->fifo_priv)
+ continue;
+
+ nv_wr32(dev, 0x003000 + (i * 8), 0xc0000000 |
+ (chan->ramin->vinst >> 12));
+ nv_wr32(dev, 0x003004 + (i * 8), 0x001f0001);
+ }
+ nvc0_fifo_playlist_update(dev);
+
return 0;
}
struct nouveau_enum nvc0_fifo_fault_unit[] = {
- { 0, "PGRAPH" },
- { 3, "PEEPHOLE" },
- { 4, "BAR1" },
- { 5, "BAR3" },
- { 7, "PFIFO" },
+ { 0x00, "PGRAPH" },
+ { 0x03, "PEEPHOLE" },
+ { 0x04, "BAR1" },
+ { 0x05, "BAR3" },
+ { 0x07, "PFIFO" },
+ { 0x10, "PBSP" },
+ { 0x11, "PPPP" },
+ { 0x13, "PCOUNTER" },
+ { 0x14, "PVP" },
+ { 0x15, "PCOPY0" },
+ { 0x16, "PCOPY1" },
+ { 0x17, "PDAEMON" },
{}
};
struct nouveau_enum nvc0_fifo_fault_reason[] = {
- { 0, "PT_NOT_PRESENT" },
- { 1, "PT_TOO_SHORT" },
- { 2, "PAGE_NOT_PRESENT" },
- { 3, "VM_LIMIT_EXCEEDED" },
+ { 0x00, "PT_NOT_PRESENT" },
+ { 0x01, "PT_TOO_SHORT" },
+ { 0x02, "PAGE_NOT_PRESENT" },
+ { 0x03, "VM_LIMIT_EXCEEDED" },
+ { 0x04, "NO_CHANNEL" },
+ { 0x05, "PAGE_SYSTEM_ONLY" },
+ { 0x06, "PAGE_READ_ONLY" },
+ { 0x0a, "COMPRESSED_SYSRAM" },
+ { 0x0c, "INVALID_STORAGE_TYPE" },
+ {}
+};
+
+struct nouveau_enum nvc0_fifo_fault_hubclient[] = {
+ { 0x01, "PCOPY0" },
+ { 0x02, "PCOPY1" },
+ { 0x04, "DISPATCH" },
+ { 0x05, "CTXCTL" },
+ { 0x06, "PFIFO" },
+ { 0x07, "BAR_READ" },
+ { 0x08, "BAR_WRITE" },
+ { 0x0b, "PVP" },
+ { 0x0c, "PPPP" },
+ { 0x0d, "PBSP" },
+ { 0x11, "PCOUNTER" },
+ { 0x12, "PDAEMON" },
+ { 0x14, "CCACHE" },
+ { 0x15, "CCACHE_POST" },
+ {}
+};
+
+struct nouveau_enum nvc0_fifo_fault_gpcclient[] = {
+ { 0x01, "TEX" },
+ { 0x0c, "ESETUP" },
+ { 0x0e, "CTXCTL" },
+ { 0x0f, "PROP" },
{}
};
@@ -385,12 +419,20 @@
u32 valo = nv_rd32(dev, 0x2804 + (unit * 0x10));
u32 vahi = nv_rd32(dev, 0x2808 + (unit * 0x10));
u32 stat = nv_rd32(dev, 0x280c + (unit * 0x10));
+ u32 client = (stat & 0x00001f00) >> 8;
NV_INFO(dev, "PFIFO: %s fault at 0x%010llx [",
(stat & 0x00000080) ? "write" : "read", (u64)vahi << 32 | valo);
nouveau_enum_print(nvc0_fifo_fault_reason, stat & 0x0000000f);
printk("] from ");
nouveau_enum_print(nvc0_fifo_fault_unit, unit);
+ if (stat & 0x00000040) {
+ printk("/");
+ nouveau_enum_print(nvc0_fifo_fault_hubclient, client);
+ } else {
+ printk("/GPC%d/", (stat & 0x1f000000) >> 24);
+ nouveau_enum_print(nvc0_fifo_fault_gpcclient, client);
+ }
printk(" on channel 0x%010llx\n", (u64)inst << 12);
}
diff --git a/drivers/gpu/drm/nouveau/nvc0_graph.c b/drivers/gpu/drm/nouveau/nvc0_graph.c
index 3de9b72..ca6db20 100644
--- a/drivers/gpu/drm/nouveau/nvc0_graph.c
+++ b/drivers/gpu/drm/nouveau/nvc0_graph.c
@@ -30,27 +30,40 @@
#include "nouveau_mm.h"
#include "nvc0_graph.h"
-static void nvc0_graph_isr(struct drm_device *);
-static void nvc0_runk140_isr(struct drm_device *);
-static int nvc0_graph_unload_context_to(struct drm_device *dev, u64 chan);
-
-void
-nvc0_graph_fifo_access(struct drm_device *dev, bool enabled)
+static int
+nvc0_graph_load_context(struct nouveau_channel *chan)
{
+ struct drm_device *dev = chan->dev;
+
+ nv_wr32(dev, 0x409840, 0x00000030);
+ nv_wr32(dev, 0x409500, 0x80000000 | chan->ramin->vinst >> 12);
+ nv_wr32(dev, 0x409504, 0x00000003);
+ if (!nv_wait(dev, 0x409800, 0x00000010, 0x00000010))
+ NV_ERROR(dev, "PGRAPH: load_ctx timeout\n");
+
+ return 0;
}
-struct nouveau_channel *
-nvc0_graph_channel(struct drm_device *dev)
+static int
+nvc0_graph_unload_context_to(struct drm_device *dev, u64 chan)
{
- return NULL;
+ nv_wr32(dev, 0x409840, 0x00000003);
+ nv_wr32(dev, 0x409500, 0x80000000 | chan >> 12);
+ nv_wr32(dev, 0x409504, 0x00000009);
+ if (!nv_wait(dev, 0x409800, 0x00000001, 0x00000000)) {
+ NV_ERROR(dev, "PGRAPH: unload_ctx timeout\n");
+ return -EBUSY;
+ }
+
+ return 0;
}
static int
nvc0_graph_construct_context(struct nouveau_channel *chan)
{
struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
- struct nvc0_graph_priv *priv = dev_priv->engine.graph.priv;
- struct nvc0_graph_chan *grch = chan->pgraph_ctx;
+ struct nvc0_graph_priv *priv = nv_engine(chan->dev, NVOBJ_ENGINE_GR);
+ struct nvc0_graph_chan *grch = chan->engctx[NVOBJ_ENGINE_GR];
struct drm_device *dev = chan->dev;
int ret, i;
u32 *ctx;
@@ -89,9 +102,8 @@
static int
nvc0_graph_create_context_mmio_list(struct nouveau_channel *chan)
{
- struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
- struct nvc0_graph_priv *priv = dev_priv->engine.graph.priv;
- struct nvc0_graph_chan *grch = chan->pgraph_ctx;
+ struct nvc0_graph_priv *priv = nv_engine(chan->dev, NVOBJ_ENGINE_GR);
+ struct nvc0_graph_chan *grch = chan->engctx[NVOBJ_ENGINE_GR];
struct drm_device *dev = chan->dev;
int i = 0, gpc, tp, ret;
u32 magic;
@@ -158,29 +170,27 @@
return 0;
}
-int
-nvc0_graph_create_context(struct nouveau_channel *chan)
+static int
+nvc0_graph_context_new(struct nouveau_channel *chan, int engine)
{
- struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
- struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
- struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
- struct nvc0_graph_priv *priv = pgraph->priv;
- struct nvc0_graph_chan *grch;
struct drm_device *dev = chan->dev;
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+ struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
+ struct nvc0_graph_priv *priv = nv_engine(dev, engine);
+ struct nvc0_graph_chan *grch;
struct nouveau_gpuobj *grctx;
int ret, i;
- chan->pgraph_ctx = kzalloc(sizeof(*grch), GFP_KERNEL);
- if (!chan->pgraph_ctx)
+ grch = kzalloc(sizeof(*grch), GFP_KERNEL);
+ if (!grch)
return -ENOMEM;
- grch = chan->pgraph_ctx;
+ chan->engctx[NVOBJ_ENGINE_GR] = grch;
ret = nouveau_gpuobj_new(dev, NULL, priv->grctx_size, 256,
NVOBJ_FLAG_VM | NVOBJ_FLAG_ZERO_ALLOC,
&grch->grctx);
if (ret)
goto error;
- chan->ramin_grctx = grch->grctx;
grctx = grch->grctx;
ret = nvc0_graph_create_context_mmio_list(chan);
@@ -200,104 +210,49 @@
for (i = 0; i < priv->grctx_size; i += 4)
nv_wo32(grctx, i, priv->grctx_vals[i / 4]);
- nv_wo32(grctx, 0xf4, 0);
- nv_wo32(grctx, 0xf8, 0);
- nv_wo32(grctx, 0x10, grch->mmio_nr);
- nv_wo32(grctx, 0x14, lower_32_bits(grch->mmio->vinst));
- nv_wo32(grctx, 0x18, upper_32_bits(grch->mmio->vinst));
- nv_wo32(grctx, 0x1c, 1);
- nv_wo32(grctx, 0x20, 0);
- nv_wo32(grctx, 0x28, 0);
- nv_wo32(grctx, 0x2c, 0);
+ nv_wo32(grctx, 0xf4, 0);
+ nv_wo32(grctx, 0xf8, 0);
+ nv_wo32(grctx, 0x10, grch->mmio_nr);
+ nv_wo32(grctx, 0x14, lower_32_bits(grch->mmio->vinst));
+ nv_wo32(grctx, 0x18, upper_32_bits(grch->mmio->vinst));
+ nv_wo32(grctx, 0x1c, 1);
+ nv_wo32(grctx, 0x20, 0);
+ nv_wo32(grctx, 0x28, 0);
+ nv_wo32(grctx, 0x2c, 0);
pinstmem->flush(dev);
return 0;
error:
- pgraph->destroy_context(chan);
+ priv->base.context_del(chan, engine);
return ret;
}
-void
-nvc0_graph_destroy_context(struct nouveau_channel *chan)
+static void
+nvc0_graph_context_del(struct nouveau_channel *chan, int engine)
{
- struct nvc0_graph_chan *grch;
-
- grch = chan->pgraph_ctx;
- chan->pgraph_ctx = NULL;
- if (!grch)
- return;
+ struct nvc0_graph_chan *grch = chan->engctx[engine];
nouveau_gpuobj_ref(NULL, &grch->mmio);
nouveau_gpuobj_ref(NULL, &grch->unk418810);
nouveau_gpuobj_ref(NULL, &grch->unk40800c);
nouveau_gpuobj_ref(NULL, &grch->unk408004);
nouveau_gpuobj_ref(NULL, &grch->grctx);
- chan->ramin_grctx = NULL;
+ chan->engctx[engine] = NULL;
}
-int
-nvc0_graph_load_context(struct nouveau_channel *chan)
+static int
+nvc0_graph_object_new(struct nouveau_channel *chan, int engine,
+ u32 handle, u16 class)
{
- struct drm_device *dev = chan->dev;
-
- nv_wr32(dev, 0x409840, 0x00000030);
- nv_wr32(dev, 0x409500, 0x80000000 | chan->ramin->vinst >> 12);
- nv_wr32(dev, 0x409504, 0x00000003);
- if (!nv_wait(dev, 0x409800, 0x00000010, 0x00000010))
- NV_ERROR(dev, "PGRAPH: load_ctx timeout\n");
-
return 0;
}
static int
-nvc0_graph_unload_context_to(struct drm_device *dev, u64 chan)
+nvc0_graph_fini(struct drm_device *dev, int engine)
{
- nv_wr32(dev, 0x409840, 0x00000003);
- nv_wr32(dev, 0x409500, 0x80000000 | chan >> 12);
- nv_wr32(dev, 0x409504, 0x00000009);
- if (!nv_wait(dev, 0x409800, 0x00000001, 0x00000000)) {
- NV_ERROR(dev, "PGRAPH: unload_ctx timeout\n");
- return -EBUSY;
- }
-
return 0;
}
-int
-nvc0_graph_unload_context(struct drm_device *dev)
-{
- u64 inst = (u64)(nv_rd32(dev, 0x409b00) & 0x0fffffff) << 12;
- return nvc0_graph_unload_context_to(dev, inst);
-}
-
-static void
-nvc0_graph_destroy(struct drm_device *dev)
-{
- struct drm_nouveau_private *dev_priv = dev->dev_private;
- struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
- struct nvc0_graph_priv *priv;
-
- priv = pgraph->priv;
- if (!priv)
- return;
-
- nouveau_irq_unregister(dev, 12);
- nouveau_irq_unregister(dev, 25);
-
- nouveau_gpuobj_ref(NULL, &priv->unk4188b8);
- nouveau_gpuobj_ref(NULL, &priv->unk4188b4);
-
- if (priv->grctx_vals)
- kfree(priv->grctx_vals);
- kfree(priv);
-}
-
-void
-nvc0_graph_takedown(struct drm_device *dev)
-{
- nvc0_graph_destroy(dev);
-}
-
static int
nvc0_graph_mthd_page_flip(struct nouveau_channel *chan,
u32 class, u32 mthd, u32 data)
@@ -306,119 +261,10 @@
return 0;
}
-static int
-nvc0_graph_create(struct drm_device *dev)
-{
- struct drm_nouveau_private *dev_priv = dev->dev_private;
- struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
- struct nvc0_graph_priv *priv;
- int ret, gpc, i;
-
- priv = kzalloc(sizeof(*priv), GFP_KERNEL);
- if (!priv)
- return -ENOMEM;
- pgraph->priv = priv;
-
- ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 256, 0, &priv->unk4188b4);
- if (ret)
- goto error;
-
- ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 256, 0, &priv->unk4188b8);
- if (ret)
- goto error;
-
- for (i = 0; i < 0x1000; i += 4) {
- nv_wo32(priv->unk4188b4, i, 0x00000010);
- nv_wo32(priv->unk4188b8, i, 0x00000010);
- }
-
- priv->gpc_nr = nv_rd32(dev, 0x409604) & 0x0000001f;
- priv->rop_nr = (nv_rd32(dev, 0x409604) & 0x001f0000) >> 16;
- for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
- priv->tp_nr[gpc] = nv_rd32(dev, GPC_UNIT(gpc, 0x2608));
- priv->tp_total += priv->tp_nr[gpc];
- }
-
- /*XXX: these need figuring out... */
- switch (dev_priv->chipset) {
- case 0xc0:
- if (priv->tp_total == 11) { /* 465, 3/4/4/0, 4 */
- priv->magic_not_rop_nr = 0x07;
- /* filled values up to tp_total, the rest 0 */
- priv->magicgpc980[0] = 0x22111000;
- priv->magicgpc980[1] = 0x00000233;
- priv->magicgpc980[2] = 0x00000000;
- priv->magicgpc980[3] = 0x00000000;
- priv->magicgpc918 = 0x000ba2e9;
- } else
- if (priv->tp_total == 14) { /* 470, 3/3/4/4, 5 */
- priv->magic_not_rop_nr = 0x05;
- priv->magicgpc980[0] = 0x11110000;
- priv->magicgpc980[1] = 0x00233222;
- priv->magicgpc980[2] = 0x00000000;
- priv->magicgpc980[3] = 0x00000000;
- priv->magicgpc918 = 0x00092493;
- } else
- if (priv->tp_total == 15) { /* 480, 3/4/4/4, 6 */
- priv->magic_not_rop_nr = 0x06;
- priv->magicgpc980[0] = 0x11110000;
- priv->magicgpc980[1] = 0x03332222;
- priv->magicgpc980[2] = 0x00000000;
- priv->magicgpc980[3] = 0x00000000;
- priv->magicgpc918 = 0x00088889;
- }
- break;
- case 0xc3: /* 450, 4/0/0/0, 2 */
- priv->magic_not_rop_nr = 0x03;
- priv->magicgpc980[0] = 0x00003210;
- priv->magicgpc980[1] = 0x00000000;
- priv->magicgpc980[2] = 0x00000000;
- priv->magicgpc980[3] = 0x00000000;
- priv->magicgpc918 = 0x00200000;
- break;
- case 0xc4: /* 460, 3/4/0/0, 4 */
- priv->magic_not_rop_nr = 0x01;
- priv->magicgpc980[0] = 0x02321100;
- priv->magicgpc980[1] = 0x00000000;
- priv->magicgpc980[2] = 0x00000000;
- priv->magicgpc980[3] = 0x00000000;
- priv->magicgpc918 = 0x00124925;
- break;
- }
-
- if (!priv->magic_not_rop_nr) {
- NV_ERROR(dev, "PGRAPH: unknown config: %d/%d/%d/%d, %d\n",
- priv->tp_nr[0], priv->tp_nr[1], priv->tp_nr[2],
- priv->tp_nr[3], priv->rop_nr);
- /* use 0xc3's values... */
- priv->magic_not_rop_nr = 0x03;
- priv->magicgpc980[0] = 0x00003210;
- priv->magicgpc980[1] = 0x00000000;
- priv->magicgpc980[2] = 0x00000000;
- priv->magicgpc980[3] = 0x00000000;
- priv->magicgpc918 = 0x00200000;
- }
-
- nouveau_irq_register(dev, 12, nvc0_graph_isr);
- nouveau_irq_register(dev, 25, nvc0_runk140_isr);
- NVOBJ_CLASS(dev, 0x902d, GR); /* 2D */
- NVOBJ_CLASS(dev, 0x9039, GR); /* M2MF */
- NVOBJ_MTHD (dev, 0x9039, 0x0500, nvc0_graph_mthd_page_flip);
- NVOBJ_CLASS(dev, 0x9097, GR); /* 3D */
- NVOBJ_CLASS(dev, 0x90c0, GR); /* COMPUTE */
- return 0;
-
-error:
- nvc0_graph_destroy(dev);
- return ret;
-}
-
static void
nvc0_graph_init_obj418880(struct drm_device *dev)
{
- struct drm_nouveau_private *dev_priv = dev->dev_private;
- struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
- struct nvc0_graph_priv *priv = pgraph->priv;
+ struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR);
int i;
nv_wr32(dev, GPC_BCAST(0x0880), 0x00000000);
@@ -449,35 +295,42 @@
static void
nvc0_graph_init_gpc_0(struct drm_device *dev)
{
- struct drm_nouveau_private *dev_priv = dev->dev_private;
- struct nvc0_graph_priv *priv = dev_priv->engine.graph.priv;
- int gpc;
-
- // TP ROP UNKVAL(magic_not_rop_nr)
- // 450: 4/0/0/0 2 3
- // 460: 3/4/0/0 4 1
- // 465: 3/4/4/0 4 7
- // 470: 3/3/4/4 5 5
- // 480: 3/4/4/4 6 6
+ struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR);
+ u32 data[TP_MAX / 8];
+ u8 tpnr[GPC_MAX];
+ int i, gpc, tpc;
- // magicgpc918
- // 450: 00200000 00000000001000000000000000000000
- // 460: 00124925 00000000000100100100100100100101
- // 465: 000ba2e9 00000000000010111010001011101001
- // 470: 00092493 00000000000010010010010010010011
- // 480: 00088889 00000000000010001000100010001001
+ /*
+ * TP ROP UNKVAL(magic_not_rop_nr)
+ * 450: 4/0/0/0 2 3
+ * 460: 3/4/0/0 4 1
+ * 465: 3/4/4/0 4 7
+ * 470: 3/3/4/4 5 5
+ * 480: 3/4/4/4 6 6
+ *
+ * magicgpc918
+ * 450: 00200000 00000000001000000000000000000000
+ * 460: 00124925 00000000000100100100100100100101
+ * 465: 000ba2e9 00000000000010111010001011101001
+ * 470: 00092493 00000000000010010010010010010011
+ * 480: 00088889 00000000000010001000100010001001
+ */
- /* filled values up to tp_total, remainder 0 */
- // 450: 00003210 00000000 00000000 00000000
- // 460: 02321100 00000000 00000000 00000000
- // 465: 22111000 00000233 00000000 00000000
- // 470: 11110000 00233222 00000000 00000000
- // 480: 11110000 03332222 00000000 00000000
-
- nv_wr32(dev, GPC_BCAST(0x0980), priv->magicgpc980[0]);
- nv_wr32(dev, GPC_BCAST(0x0984), priv->magicgpc980[1]);
- nv_wr32(dev, GPC_BCAST(0x0988), priv->magicgpc980[2]);
- nv_wr32(dev, GPC_BCAST(0x098c), priv->magicgpc980[3]);
+ memset(data, 0x00, sizeof(data));
+ memcpy(tpnr, priv->tp_nr, sizeof(priv->tp_nr));
+ for (i = 0, gpc = -1; i < priv->tp_total; i++) {
+ do {
+ gpc = (gpc + 1) % priv->gpc_nr;
+ } while (!tpnr[gpc]);
+ tpc = priv->tp_nr[gpc] - tpnr[gpc]--;
+
+ data[i / 8] |= tpc << ((i % 8) * 4);
+ }
+
+ nv_wr32(dev, GPC_BCAST(0x0980), data[0]);
+ nv_wr32(dev, GPC_BCAST(0x0984), data[1]);
+ nv_wr32(dev, GPC_BCAST(0x0988), data[2]);
+ nv_wr32(dev, GPC_BCAST(0x098c), data[3]);
for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
nv_wr32(dev, GPC_UNIT(gpc, 0x0914), priv->magic_not_rop_nr << 8 |
@@ -509,8 +362,7 @@
static void
nvc0_graph_init_gpc_1(struct drm_device *dev)
{
- struct drm_nouveau_private *dev_priv = dev->dev_private;
- struct nvc0_graph_priv *priv = dev_priv->engine.graph.priv;
+ struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR);
int gpc, tp;
for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
@@ -535,8 +387,7 @@
static void
nvc0_graph_init_rop(struct drm_device *dev)
{
- struct drm_nouveau_private *dev_priv = dev->dev_private;
- struct nvc0_graph_priv *priv = dev_priv->engine.graph.priv;
+ struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR);
int rop;
for (rop = 0; rop < priv->rop_nr; rop++) {
@@ -547,62 +398,36 @@
}
}
-static int
-nvc0_fuc_load_fw(struct drm_device *dev, u32 fuc_base,
- const char *code_fw, const char *data_fw)
+static void
+nvc0_graph_init_fuc(struct drm_device *dev, u32 fuc_base,
+ struct nvc0_graph_fuc *code, struct nvc0_graph_fuc *data)
{
- const struct firmware *fw;
- char name[32];
- int ret, i;
-
- snprintf(name, sizeof(name), "nouveau/%s", data_fw);
- ret = request_firmware(&fw, name, &dev->pdev->dev);
- if (ret) {
- NV_ERROR(dev, "failed to load %s\n", data_fw);
- return ret;
- }
+ int i;
nv_wr32(dev, fuc_base + 0x01c0, 0x01000000);
- for (i = 0; i < fw->size / 4; i++)
- nv_wr32(dev, fuc_base + 0x01c4, ((u32 *)fw->data)[i]);
- release_firmware(fw);
-
- snprintf(name, sizeof(name), "nouveau/%s", code_fw);
- ret = request_firmware(&fw, name, &dev->pdev->dev);
- if (ret) {
- NV_ERROR(dev, "failed to load %s\n", code_fw);
- return ret;
- }
+ for (i = 0; i < data->size / 4; i++)
+ nv_wr32(dev, fuc_base + 0x01c4, data->data[i]);
nv_wr32(dev, fuc_base + 0x0180, 0x01000000);
- for (i = 0; i < fw->size / 4; i++) {
+ for (i = 0; i < code->size / 4; i++) {
if ((i & 0x3f) == 0)
nv_wr32(dev, fuc_base + 0x0188, i >> 6);
- nv_wr32(dev, fuc_base + 0x0184, ((u32 *)fw->data)[i]);
+ nv_wr32(dev, fuc_base + 0x0184, code->data[i]);
}
- release_firmware(fw);
-
- return 0;
}
static int
nvc0_graph_init_ctxctl(struct drm_device *dev)
{
- struct drm_nouveau_private *dev_priv = dev->dev_private;
- struct nvc0_graph_priv *priv = dev_priv->engine.graph.priv;
+ struct nvc0_graph_priv *priv = nv_engine(dev, NVOBJ_ENGINE_GR);
u32 r000260;
- int ret;
/* load fuc microcode */
r000260 = nv_mask(dev, 0x000260, 0x00000001, 0x00000000);
- ret = nvc0_fuc_load_fw(dev, 0x409000, "fuc409c", "fuc409d");
- if (ret == 0)
- ret = nvc0_fuc_load_fw(dev, 0x41a000, "fuc41ac", "fuc41ad");
+ nvc0_graph_init_fuc(dev, 0x409000, &priv->fuc409c, &priv->fuc409d);
+ nvc0_graph_init_fuc(dev, 0x41a000, &priv->fuc41ac, &priv->fuc41ad);
nv_wr32(dev, 0x000260, r000260);
- if (ret)
- return ret;
-
/* start both of them running */
nv_wr32(dev, 0x409840, 0xffffffff);
nv_wr32(dev, 0x41a10c, 0x00000000);
@@ -644,41 +469,19 @@
return 0;
}
-int
-nvc0_graph_init(struct drm_device *dev)
+static int
+nvc0_graph_init(struct drm_device *dev, int engine)
{
- struct drm_nouveau_private *dev_priv = dev->dev_private;
- struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
int ret;
- dev_priv->engine.graph.accel_blocked = true;
-
- switch (dev_priv->chipset) {
- case 0xc0:
- case 0xc3:
- case 0xc4:
- break;
- default:
- NV_ERROR(dev, "PGRAPH: unsupported chipset, please report!\n");
- if (nouveau_noaccel != 0)
- return 0;
- break;
- }
-
nv_mask(dev, 0x000200, 0x18001000, 0x00000000);
nv_mask(dev, 0x000200, 0x18001000, 0x18001000);
- if (!pgraph->priv) {
- ret = nvc0_graph_create(dev);
- if (ret)
- return ret;
- }
-
nvc0_graph_init_obj418880(dev);
nvc0_graph_init_regs(dev);
- //nvc0_graph_init_unitplemented_magics(dev);
+ /*nvc0_graph_init_unitplemented_magics(dev);*/
nvc0_graph_init_gpc_0(dev);
- //nvc0_graph_init_unitplemented_c242(dev);
+ /*nvc0_graph_init_unitplemented_c242(dev);*/
nv_wr32(dev, 0x400500, 0x00010001);
nv_wr32(dev, 0x400100, 0xffffffff);
@@ -697,12 +500,13 @@
nv_wr32(dev, 0x400054, 0x34ce3464);
ret = nvc0_graph_init_ctxctl(dev);
- if (ret == 0)
- dev_priv->engine.graph.accel_blocked = false;
+ if (ret)
+ return ret;
+
return 0;
}
-static int
+int
nvc0_graph_isr_chid(struct drm_device *dev, u64 inst)
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
@@ -806,3 +610,187 @@
units &= ~(1 << unit);
}
}
+
+static int
+nvc0_graph_create_fw(struct drm_device *dev, const char *fwname,
+ struct nvc0_graph_fuc *fuc)
+{
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+ const struct firmware *fw;
+ char f[32];
+ int ret;
+
+ snprintf(f, sizeof(f), "nouveau/nv%02x_%s", dev_priv->chipset, fwname);
+ ret = request_firmware(&fw, f, &dev->pdev->dev);
+ if (ret) {
+ snprintf(f, sizeof(f), "nouveau/%s", fwname);
+ ret = request_firmware(&fw, f, &dev->pdev->dev);
+ if (ret) {
+ NV_ERROR(dev, "failed to load %s\n", fwname);
+ return ret;
+ }
+ }
+
+ fuc->size = fw->size;
+ fuc->data = kmemdup(fw->data, fuc->size, GFP_KERNEL);
+ release_firmware(fw);
+ return (fuc->data != NULL) ? 0 : -ENOMEM;
+}
+
+static void
+nvc0_graph_destroy_fw(struct nvc0_graph_fuc *fuc)
+{
+ if (fuc->data) {
+ kfree(fuc->data);
+ fuc->data = NULL;
+ }
+}
+
+static void
+nvc0_graph_destroy(struct drm_device *dev, int engine)
+{
+ struct nvc0_graph_priv *priv = nv_engine(dev, engine);
+
+ nvc0_graph_destroy_fw(&priv->fuc409c);
+ nvc0_graph_destroy_fw(&priv->fuc409d);
+ nvc0_graph_destroy_fw(&priv->fuc41ac);
+ nvc0_graph_destroy_fw(&priv->fuc41ad);
+
+ nouveau_irq_unregister(dev, 12);
+ nouveau_irq_unregister(dev, 25);
+
+ nouveau_gpuobj_ref(NULL, &priv->unk4188b8);
+ nouveau_gpuobj_ref(NULL, &priv->unk4188b4);
+
+ if (priv->grctx_vals)
+ kfree(priv->grctx_vals);
+
+ NVOBJ_ENGINE_DEL(dev, GR);
+ kfree(priv);
+}
+
+int
+nvc0_graph_create(struct drm_device *dev)
+{
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+ struct nvc0_graph_priv *priv;
+ int ret, gpc, i;
+
+ switch (dev_priv->chipset) {
+ case 0xc0:
+ case 0xc3:
+ case 0xc4:
+ break;
+ default:
+ NV_ERROR(dev, "PGRAPH: unsupported chipset, please report!\n");
+ return 0;
+ }
+
+ priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->base.destroy = nvc0_graph_destroy;
+ priv->base.init = nvc0_graph_init;
+ priv->base.fini = nvc0_graph_fini;
+ priv->base.context_new = nvc0_graph_context_new;
+ priv->base.context_del = nvc0_graph_context_del;
+ priv->base.object_new = nvc0_graph_object_new;
+
+ NVOBJ_ENGINE_ADD(dev, GR, &priv->base);
+ nouveau_irq_register(dev, 12, nvc0_graph_isr);
+ nouveau_irq_register(dev, 25, nvc0_runk140_isr);
+
+ if (nvc0_graph_create_fw(dev, "fuc409c", &priv->fuc409c) ||
+ nvc0_graph_create_fw(dev, "fuc409d", &priv->fuc409d) ||
+ nvc0_graph_create_fw(dev, "fuc41ac", &priv->fuc41ac) ||
+ nvc0_graph_create_fw(dev, "fuc41ad", &priv->fuc41ad)) {
+ ret = 0;
+ goto error;
+ }
+
+
+ ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 256, 0, &priv->unk4188b4);
+ if (ret)
+ goto error;
+
+ ret = nouveau_gpuobj_new(dev, NULL, 0x1000, 256, 0, &priv->unk4188b8);
+ if (ret)
+ goto error;
+
+ for (i = 0; i < 0x1000; i += 4) {
+ nv_wo32(priv->unk4188b4, i, 0x00000010);
+ nv_wo32(priv->unk4188b8, i, 0x00000010);
+ }
+
+ priv->gpc_nr = nv_rd32(dev, 0x409604) & 0x0000001f;
+ priv->rop_nr = (nv_rd32(dev, 0x409604) & 0x001f0000) >> 16;
+ for (gpc = 0; gpc < priv->gpc_nr; gpc++) {
+ priv->tp_nr[gpc] = nv_rd32(dev, GPC_UNIT(gpc, 0x2608));
+ priv->tp_total += priv->tp_nr[gpc];
+ }
+
+ /*XXX: these need figuring out... */
+ switch (dev_priv->chipset) {
+ case 0xc0:
+ if (priv->tp_total == 11) { /* 465, 3/4/4/0, 4 */
+ priv->magic_not_rop_nr = 0x07;
+ /* filled values up to tp_total, the rest 0 */
+ priv->magicgpc918 = 0x000ba2e9;
+ } else
+ if (priv->tp_total == 14) { /* 470, 3/3/4/4, 5 */
+ priv->magic_not_rop_nr = 0x05;
+ priv->magicgpc918 = 0x00092493;
+ } else
+ if (priv->tp_total == 15) { /* 480, 3/4/4/4, 6 */
+ priv->magic_not_rop_nr = 0x06;
+ priv->magicgpc918 = 0x00088889;
+ }
+ break;
+ case 0xc3: /* 450, 4/0/0/0, 2 */
+ priv->magic_not_rop_nr = 0x03;
+ priv->magicgpc918 = 0x00200000;
+ break;
+ case 0xc4: /* 460, 3/4/0/0, 4 */
+ priv->magic_not_rop_nr = 0x01;
+ priv->magicgpc918 = 0x00124925;
+ break;
+ }
+
+ if (!priv->magic_not_rop_nr) {
+ NV_ERROR(dev, "PGRAPH: unknown config: %d/%d/%d/%d, %d\n",
+ priv->tp_nr[0], priv->tp_nr[1], priv->tp_nr[2],
+ priv->tp_nr[3], priv->rop_nr);
+ /* use 0xc3's values... */
+ priv->magic_not_rop_nr = 0x03;
+ priv->magicgpc918 = 0x00200000;
+ }
+
+ NVOBJ_CLASS(dev, 0x902d, GR); /* 2D */
+ NVOBJ_CLASS(dev, 0x9039, GR); /* M2MF */
+ NVOBJ_MTHD (dev, 0x9039, 0x0500, nvc0_graph_mthd_page_flip);
+ NVOBJ_CLASS(dev, 0x9097, GR); /* 3D */
+ NVOBJ_CLASS(dev, 0x90c0, GR); /* COMPUTE */
+ return 0;
+
+error:
+ nvc0_graph_destroy(dev, NVOBJ_ENGINE_GR);
+ return ret;
+}
+
+MODULE_FIRMWARE("nouveau/nvc0_fuc409c");
+MODULE_FIRMWARE("nouveau/nvc0_fuc409d");
+MODULE_FIRMWARE("nouveau/nvc0_fuc41ac");
+MODULE_FIRMWARE("nouveau/nvc0_fuc41ad");
+MODULE_FIRMWARE("nouveau/nvc3_fuc409c");
+MODULE_FIRMWARE("nouveau/nvc3_fuc409d");
+MODULE_FIRMWARE("nouveau/nvc3_fuc41ac");
+MODULE_FIRMWARE("nouveau/nvc3_fuc41ad");
+MODULE_FIRMWARE("nouveau/nvc4_fuc409c");
+MODULE_FIRMWARE("nouveau/nvc4_fuc409d");
+MODULE_FIRMWARE("nouveau/nvc4_fuc41ac");
+MODULE_FIRMWARE("nouveau/nvc4_fuc41ad");
+MODULE_FIRMWARE("nouveau/fuc409c");
+MODULE_FIRMWARE("nouveau/fuc409d");
+MODULE_FIRMWARE("nouveau/fuc41ac");
+MODULE_FIRMWARE("nouveau/fuc41ad");
diff --git a/drivers/gpu/drm/nouveau/nvc0_graph.h b/drivers/gpu/drm/nouveau/nvc0_graph.h
index 40e26f9..f5d184e0 100644
--- a/drivers/gpu/drm/nouveau/nvc0_graph.h
+++ b/drivers/gpu/drm/nouveau/nvc0_graph.h
@@ -28,13 +28,25 @@
#define GPC_MAX 4
#define TP_MAX 32
-#define ROP_BCAST(r) (0x408800 + (r))
-#define ROP_UNIT(u,r) (0x410000 + (u) * 0x400 + (r))
-#define GPC_BCAST(r) (0x418000 + (r))
-#define GPC_UNIT(t,r) (0x500000 + (t) * 0x8000 + (r))
-#define TP_UNIT(t,m,r) (0x504000 + (t) * 0x8000 + (m) * 0x800 + (r))
+#define ROP_BCAST(r) (0x408800 + (r))
+#define ROP_UNIT(u, r) (0x410000 + (u) * 0x400 + (r))
+#define GPC_BCAST(r) (0x418000 + (r))
+#define GPC_UNIT(t, r) (0x500000 + (t) * 0x8000 + (r))
+#define TP_UNIT(t, m, r) (0x504000 + (t) * 0x8000 + (m) * 0x800 + (r))
+
+struct nvc0_graph_fuc {
+ u32 *data;
+ u32 size;
+};
struct nvc0_graph_priv {
+ struct nouveau_exec_engine base;
+
+ struct nvc0_graph_fuc fuc409c;
+ struct nvc0_graph_fuc fuc409d;
+ struct nvc0_graph_fuc fuc41ac;
+ struct nvc0_graph_fuc fuc41ad;
+
u8 gpc_nr;
u8 rop_nr;
u8 tp_nr[GPC_MAX];
@@ -46,15 +58,14 @@
struct nouveau_gpuobj *unk4188b8;
u8 magic_not_rop_nr;
- u32 magicgpc980[4];
u32 magicgpc918;
};
struct nvc0_graph_chan {
struct nouveau_gpuobj *grctx;
- struct nouveau_gpuobj *unk408004; // 0x418810 too
- struct nouveau_gpuobj *unk40800c; // 0x419004 too
- struct nouveau_gpuobj *unk418810; // 0x419848 too
+ struct nouveau_gpuobj *unk408004; /* 0x418810 too */
+ struct nouveau_gpuobj *unk40800c; /* 0x419004 too */
+ struct nouveau_gpuobj *unk418810; /* 0x419848 too */
struct nouveau_gpuobj *mmio;
int mmio_nr;
};
diff --git a/drivers/gpu/drm/nouveau/nvc0_grctx.c b/drivers/gpu/drm/nouveau/nvc0_grctx.c
index f880ff7..6df0661 100644
--- a/drivers/gpu/drm/nouveau/nvc0_grctx.c
+++ b/drivers/gpu/drm/nouveau/nvc0_grctx.c
@@ -1623,7 +1623,7 @@
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
- // ROPC_BROADCAST
+ /* ROPC_BROADCAST */
nv_wr32(dev, 0x408800, 0x02802a3c);
nv_wr32(dev, 0x408804, 0x00000040);
nv_wr32(dev, 0x408808, 0x0003e00d);
@@ -1647,7 +1647,7 @@
{
int i;
- // GPC_BROADCAST
+ /* GPC_BROADCAST */
nv_wr32(dev, 0x418380, 0x00000016);
nv_wr32(dev, 0x418400, 0x38004e00);
nv_wr32(dev, 0x418404, 0x71e0ffff);
@@ -1728,7 +1728,7 @@
{
struct drm_nouveau_private *dev_priv = dev->dev_private;
- // GPC_BROADCAST.TP_BROADCAST
+ /* GPC_BROADCAST.TP_BROADCAST */
nv_wr32(dev, 0x419848, 0x00000000);
nv_wr32(dev, 0x419864, 0x0000012a);
nv_wr32(dev, 0x419888, 0x00000000);
@@ -1741,7 +1741,7 @@
nv_wr32(dev, 0x419a1c, 0x00000000);
nv_wr32(dev, 0x419a20, 0x00000800);
if (dev_priv->chipset != 0xc0)
- nv_wr32(dev, 0x00419ac4, 0x0007f440); // 0xc3
+ nv_wr32(dev, 0x00419ac4, 0x0007f440); /* 0xc3 */
nv_wr32(dev, 0x419b00, 0x0a418820);
nv_wr32(dev, 0x419b04, 0x062080e6);
nv_wr32(dev, 0x419b08, 0x020398a4);
@@ -1797,8 +1797,8 @@
nvc0_grctx_generate(struct nouveau_channel *chan)
{
struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
- struct nvc0_graph_priv *priv = dev_priv->engine.graph.priv;
- struct nvc0_graph_chan *grch = chan->pgraph_ctx;
+ struct nvc0_graph_priv *priv = nv_engine(chan->dev, NVOBJ_ENGINE_GR);
+ struct nvc0_graph_chan *grch = chan->engctx[NVOBJ_ENGINE_GR];
struct drm_device *dev = chan->dev;
int i, gpc, tp, id;
u32 r000260, tmp;
@@ -1912,13 +1912,13 @@
for (i = 1; i < 7; i++)
data2[1] |= ((1 << (i + 5)) % ntpcv) << ((i - 1) * 5);
- // GPC_BROADCAST
+ /* GPC_BROADCAST */
nv_wr32(dev, 0x418bb8, (priv->tp_total << 8) |
priv->magic_not_rop_nr);
for (i = 0; i < 6; i++)
nv_wr32(dev, 0x418b08 + (i * 4), data[i]);
- // GPC_BROADCAST.TP_BROADCAST
+ /* GPC_BROADCAST.TP_BROADCAST */
nv_wr32(dev, 0x419bd0, (priv->tp_total << 8) |
priv->magic_not_rop_nr |
data2[0]);
@@ -1926,7 +1926,7 @@
for (i = 0; i < 6; i++)
nv_wr32(dev, 0x419b00 + (i * 4), data[i]);
- // UNK78xx
+ /* UNK78xx */
nv_wr32(dev, 0x4078bc, (priv->tp_total << 8) |
priv->magic_not_rop_nr);
for (i = 0; i < 6; i++)
@@ -1944,7 +1944,7 @@
gpc = -1;
for (i = 0, gpc = -1; i < 32; i++) {
int ltp = i * (priv->tp_total - 1) / 32;
-
+
do {
gpc = (gpc + 1) % priv->gpc_nr;
} while (!tpnr[gpc]);
diff --git a/drivers/gpu/drm/radeon/atom.c b/drivers/gpu/drm/radeon/atom.c
index 7bd7456..ebdb0fd 100644
--- a/drivers/gpu/drm/radeon/atom.c
+++ b/drivers/gpu/drm/radeon/atom.c
@@ -652,12 +652,12 @@
static void atom_op_delay(atom_exec_context *ctx, int *ptr, int arg)
{
- uint8_t count = U8((*ptr)++);
+ unsigned count = U8((*ptr)++);
SDEBUG(" count: %d\n", count);
if (arg == ATOM_UNIT_MICROSEC)
udelay(count);
else
- schedule_timeout_uninterruptible(msecs_to_jiffies(count));
+ msleep(count);
}
static void atom_op_div(atom_exec_context *ctx, int *ptr, int arg)
diff --git a/drivers/gpu/drm/radeon/atombios.h b/drivers/gpu/drm/radeon/atombios.h
index 7fd8849..49611e2 100644
--- a/drivers/gpu/drm/radeon/atombios.h
+++ b/drivers/gpu/drm/radeon/atombios.h
@@ -726,6 +726,7 @@
#define ATOM_ENCODER_CMD_DP_VIDEO_ON 0x0d
#define ATOM_ENCODER_CMD_QUERY_DP_LINK_TRAINING_STATUS 0x0e
#define ATOM_ENCODER_CMD_SETUP 0x0f
+#define ATOM_ENCODER_CMD_SETUP_PANEL_MODE 0x10
// ucStatus
#define ATOM_ENCODER_STATUS_LINK_TRAINING_COMPLETE 0x10
@@ -765,13 +766,19 @@
USHORT usPixelClock; // in 10KHz; for bios convenient
ATOM_DIG_ENCODER_CONFIG_V3 acConfig;
UCHAR ucAction;
- UCHAR ucEncoderMode;
+ union {
+ UCHAR ucEncoderMode;
// =0: DP encoder
// =1: LVDS encoder
// =2: DVI encoder
// =3: HDMI encoder
// =4: SDVO encoder
// =5: DP audio
+ UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE
+ // =0: external DP
+ // =1: internal DP2
+ // =0x11: internal DP1 for NutMeg/Travis DP translator
+ };
UCHAR ucLaneNum; // how many lanes to enable
UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP
UCHAR ucReserved;
@@ -816,13 +823,19 @@
UCHAR ucConfig;
};
UCHAR ucAction;
- UCHAR ucEncoderMode;
+ union {
+ UCHAR ucEncoderMode;
// =0: DP encoder
// =1: LVDS encoder
// =2: DVI encoder
// =3: HDMI encoder
// =4: SDVO encoder
// =5: DP audio
+ UCHAR ucPanelMode; // only valid when ucAction == ATOM_ENCODER_CMD_SETUP_PANEL_MODE
+ // =0: external DP
+ // =1: internal DP2
+ // =0x11: internal DP1 for NutMeg/Travis DP translator
+ };
UCHAR ucLaneNum; // how many lanes to enable
UCHAR ucBitPerColor; // only valid for DP mode when ucAction = ATOM_ENCODER_CMD_SETUP
UCHAR ucHPD_ID; // HPD ID (1-6). =0 means to skip HDP programming. New comparing to previous version
@@ -836,6 +849,11 @@
#define PANEL_12BIT_PER_COLOR 0x04
#define PANEL_16BIT_PER_COLOR 0x05
+//define ucPanelMode
+#define DP_PANEL_MODE_EXTERNAL_DP_MODE 0x00
+#define DP_PANEL_MODE_INTERNAL_DP2_MODE 0x01
+#define DP_PANEL_MODE_INTERNAL_DP1_MODE 0x11
+
/****************************************************************************/
// Structures used by UNIPHYTransmitterControlTable
// LVTMATransmitterControlTable
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 529a3a7..ec84878 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -420,7 +420,7 @@
if (ASIC_IS_DCE5(rdev)) {
args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0);
- args.v3.ucSpreadSpectrumType = ss->type;
+ args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
switch (pll_id) {
case ATOM_PPLL1:
args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL;
@@ -440,10 +440,12 @@
case ATOM_PPLL_INVALID:
return;
}
- args.v2.ucEnable = enable;
+ args.v3.ucEnable = enable;
+ if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK))
+ args.v3.ucEnable = ATOM_DISABLE;
} else if (ASIC_IS_DCE4(rdev)) {
args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
- args.v2.ucSpreadSpectrumType = ss->type;
+ args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
switch (pll_id) {
case ATOM_PPLL1:
args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL;
@@ -464,32 +466,36 @@
return;
}
args.v2.ucEnable = enable;
+ if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK))
+ args.v2.ucEnable = ATOM_DISABLE;
} else if (ASIC_IS_DCE3(rdev)) {
args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
- args.v1.ucSpreadSpectrumType = ss->type;
+ args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
args.v1.ucSpreadSpectrumStep = ss->step;
args.v1.ucSpreadSpectrumDelay = ss->delay;
args.v1.ucSpreadSpectrumRange = ss->range;
args.v1.ucPpll = pll_id;
args.v1.ucEnable = enable;
} else if (ASIC_IS_AVIVO(rdev)) {
- if (enable == ATOM_DISABLE) {
+ if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
+ (ss->type & ATOM_EXTERNAL_SS_MASK)) {
atombios_disable_ss(crtc);
return;
}
args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
- args.lvds_ss_2.ucSpreadSpectrumType = ss->type;
+ args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
args.lvds_ss_2.ucSpreadSpectrumStep = ss->step;
args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay;
args.lvds_ss_2.ucSpreadSpectrumRange = ss->range;
args.lvds_ss_2.ucEnable = enable;
} else {
- if (enable == ATOM_DISABLE) {
+ if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
+ (ss->type & ATOM_EXTERNAL_SS_MASK)) {
atombios_disable_ss(crtc);
return;
}
args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
- args.lvds_ss.ucSpreadSpectrumType = ss->type;
+ args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2;
args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4;
args.lvds_ss.ucEnable = enable;
@@ -512,6 +518,7 @@
struct radeon_device *rdev = dev->dev_private;
struct drm_encoder *encoder = NULL;
struct radeon_encoder *radeon_encoder = NULL;
+ struct drm_connector *connector = NULL;
u32 adjusted_clock = mode->clock;
int encoder_mode = 0;
u32 dp_clock = mode->clock;
@@ -546,9 +553,12 @@
list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
if (encoder->crtc == crtc) {
radeon_encoder = to_radeon_encoder(encoder);
+ connector = radeon_get_connector_for_encoder(encoder);
+ if (connector)
+ bpc = connector->display_info.bpc;
encoder_mode = atombios_get_encoder_mode(encoder);
- if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) {
- struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
+ if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
+ radeon_encoder_is_dp_bridge(encoder)) {
if (connector) {
struct radeon_connector *radeon_connector = to_radeon_connector(connector);
struct radeon_connector_atom_dig *dig_connector =
@@ -612,7 +622,7 @@
args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
args.v1.ucTransmitterID = radeon_encoder->encoder_id;
args.v1.ucEncodeMode = encoder_mode;
- if (ss_enabled)
+ if (ss_enabled && ss->percentage)
args.v1.ucConfig |=
ADJUST_DISPLAY_CONFIG_SS_ENABLE;
@@ -625,10 +635,11 @@
args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
args.v3.sInput.ucEncodeMode = encoder_mode;
args.v3.sInput.ucDispPllConfig = 0;
- if (ss_enabled)
+ if (ss_enabled && ss->percentage)
args.v3.sInput.ucDispPllConfig |=
DISPPLL_CONFIG_SS_ENABLE;
- if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
+ if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT) ||
+ radeon_encoder_is_dp_bridge(encoder)) {
struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
if (encoder_mode == ATOM_ENCODER_MODE_DP) {
args.v3.sInput.ucDispPllConfig |=
@@ -754,7 +765,10 @@
u32 ref_div,
u32 fb_div,
u32 frac_fb_div,
- u32 post_div)
+ u32 post_div,
+ int bpc,
+ bool ss_enabled,
+ struct radeon_atom_ss *ss)
{
struct drm_device *dev = crtc->dev;
struct radeon_device *rdev = dev->dev_private;
@@ -801,6 +815,8 @@
args.v3.ucPostDiv = post_div;
args.v3.ucPpll = pll_id;
args.v3.ucMiscInfo = (pll_id << 2);
+ if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
+ args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC;
args.v3.ucTransmitterId = encoder_id;
args.v3.ucEncoderMode = encoder_mode;
break;
@@ -812,6 +828,17 @@
args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
args.v5.ucPostDiv = post_div;
args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
+ if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
+ args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC;
+ switch (bpc) {
+ case 8:
+ default:
+ args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP;
+ break;
+ case 10:
+ args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP;
+ break;
+ }
args.v5.ucTransmitterID = encoder_id;
args.v5.ucEncoderMode = encoder_mode;
args.v5.ucPpll = pll_id;
@@ -824,6 +851,23 @@
args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
args.v6.ucPostDiv = post_div;
args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
+ if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
+ args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC;
+ switch (bpc) {
+ case 8:
+ default:
+ args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP;
+ break;
+ case 10:
+ args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP;
+ break;
+ case 12:
+ args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP;
+ break;
+ case 16:
+ args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP;
+ break;
+ }
args.v6.ucTransmitterID = encoder_id;
args.v6.ucEncoderMode = encoder_mode;
args.v6.ucPpll = pll_id;
@@ -855,6 +899,7 @@
int encoder_mode = 0;
struct radeon_atom_ss ss;
bool ss_enabled = false;
+ int bpc = 8;
list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
if (encoder->crtc == crtc) {
@@ -891,41 +936,30 @@
struct radeon_connector_atom_dig *dig_connector =
radeon_connector->con_priv;
int dp_clock;
+ bpc = connector->display_info.bpc;
switch (encoder_mode) {
case ATOM_ENCODER_MODE_DP:
/* DP/eDP */
dp_clock = dig_connector->dp_clock / 10;
- if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
- if (ASIC_IS_DCE4(rdev))
- ss_enabled =
- radeon_atombios_get_asic_ss_info(rdev, &ss,
- dig->lcd_ss_id,
- dp_clock);
- else
+ if (ASIC_IS_DCE4(rdev))
+ ss_enabled =
+ radeon_atombios_get_asic_ss_info(rdev, &ss,
+ ASIC_INTERNAL_SS_ON_DP,
+ dp_clock);
+ else {
+ if (dp_clock == 16200) {
ss_enabled =
radeon_atombios_get_ppll_ss_info(rdev, &ss,
- dig->lcd_ss_id);
- } else {
- if (ASIC_IS_DCE4(rdev))
- ss_enabled =
- radeon_atombios_get_asic_ss_info(rdev, &ss,
- ASIC_INTERNAL_SS_ON_DP,
- dp_clock);
- else {
- if (dp_clock == 16200) {
- ss_enabled =
- radeon_atombios_get_ppll_ss_info(rdev, &ss,
- ATOM_DP_SS_ID2);
- if (!ss_enabled)
- ss_enabled =
- radeon_atombios_get_ppll_ss_info(rdev, &ss,
- ATOM_DP_SS_ID1);
- } else
+ ATOM_DP_SS_ID2);
+ if (!ss_enabled)
ss_enabled =
radeon_atombios_get_ppll_ss_info(rdev, &ss,
ATOM_DP_SS_ID1);
- }
+ } else
+ ss_enabled =
+ radeon_atombios_get_ppll_ss_info(rdev, &ss,
+ ATOM_DP_SS_ID1);
}
break;
case ATOM_ENCODER_MODE_LVDS:
@@ -974,7 +1008,7 @@
atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
encoder_mode, radeon_encoder->encoder_id, mode->clock,
- ref_div, fb_div, frac_fb_div, post_div);
+ ref_div, fb_div, frac_fb_div, post_div, bpc, ss_enabled, &ss);
if (ss_enabled) {
/* calculate ss amount and step size */
@@ -982,7 +1016,7 @@
u32 step_size;
u32 amount = (((fb_div * 10) + frac_fb_div) * ss.percentage) / 10000;
ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;
- ss.amount |= ((amount - (ss.amount * 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
+ ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK;
if (ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)
step_size = (4 * amount * ref_div * (ss.rate * 2048)) /
@@ -1395,11 +1429,19 @@
uint32_t pll_in_use = 0;
if (ASIC_IS_DCE4(rdev)) {
- /* if crtc is driving DP and we have an ext clock, use that */
list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
if (test_encoder->crtc && (test_encoder->crtc == crtc)) {
+ /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,
+ * depending on the asic:
+ * DCE4: PPLL or ext clock
+ * DCE5: DCPLL or ext clock
+ *
+ * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip
+ * PPLL/DCPLL programming and only program the DP DTO for the
+ * crtc virtual pixel clock.
+ */
if (atombios_get_encoder_mode(test_encoder) == ATOM_ENCODER_MODE_DP) {
- if (rdev->clock.dp_extclk)
+ if (ASIC_IS_DCE5(rdev) || rdev->clock.dp_extclk)
return ATOM_PPLL_INVALID;
}
}
@@ -1515,6 +1557,8 @@
static void atombios_crtc_disable(struct drm_crtc *crtc)
{
struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
+ struct radeon_atom_ss ss;
+
atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
switch (radeon_crtc->pll_id) {
@@ -1522,7 +1566,7 @@
case ATOM_PPLL2:
/* disable the ppll */
atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
- 0, 0, ATOM_DISABLE, 0, 0, 0, 0);
+ 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
break;
default:
break;
diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c
index 695de9a..8c0f9e3 100644
--- a/drivers/gpu/drm/radeon/atombios_dp.c
+++ b/drivers/gpu/drm/radeon/atombios_dp.c
@@ -43,157 +43,241 @@
"0dB", "3.5dB", "6dB", "9.5dB"
};
-static const int dp_clocks[] = {
- 54000, /* 1 lane, 1.62 Ghz */
- 90000, /* 1 lane, 2.70 Ghz */
- 108000, /* 2 lane, 1.62 Ghz */
- 180000, /* 2 lane, 2.70 Ghz */
- 216000, /* 4 lane, 1.62 Ghz */
- 360000, /* 4 lane, 2.70 Ghz */
+/***** radeon AUX functions *****/
+union aux_channel_transaction {
+ PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1;
+ PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2;
};
-static const int num_dp_clocks = sizeof(dp_clocks) / sizeof(int);
-
-/* common helper functions */
-static int dp_lanes_for_mode_clock(u8 dpcd[DP_DPCD_SIZE], int mode_clock)
+static int radeon_process_aux_ch(struct radeon_i2c_chan *chan,
+ u8 *send, int send_bytes,
+ u8 *recv, int recv_size,
+ u8 delay, u8 *ack)
{
- int i;
- u8 max_link_bw;
- u8 max_lane_count;
+ struct drm_device *dev = chan->dev;
+ struct radeon_device *rdev = dev->dev_private;
+ union aux_channel_transaction args;
+ int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction);
+ unsigned char *base;
+ int recv_bytes;
- if (!dpcd)
- return 0;
+ memset(&args, 0, sizeof(args));
- max_link_bw = dpcd[DP_MAX_LINK_RATE];
- max_lane_count = dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
+ base = (unsigned char *)rdev->mode_info.atom_context->scratch;
- switch (max_link_bw) {
- case DP_LINK_BW_1_62:
- default:
- for (i = 0; i < num_dp_clocks; i++) {
- if (i % 2)
- continue;
- switch (max_lane_count) {
- case 1:
- if (i > 1)
- return 0;
- break;
- case 2:
- if (i > 3)
- return 0;
- break;
- case 4:
- default:
- break;
- }
- if (dp_clocks[i] > mode_clock) {
- if (i < 2)
- return 1;
- else if (i < 4)
- return 2;
- else
- return 4;
- }
- }
+ memcpy(base, send, send_bytes);
+
+ args.v1.lpAuxRequest = 0;
+ args.v1.lpDataOut = 16;
+ args.v1.ucDataOutLen = 0;
+ args.v1.ucChannelID = chan->rec.i2c_id;
+ args.v1.ucDelay = delay / 10;
+ if (ASIC_IS_DCE4(rdev))
+ args.v2.ucHPD_ID = chan->rec.hpd;
+
+ atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
+
+ *ack = args.v1.ucReplyStatus;
+
+ /* timeout */
+ if (args.v1.ucReplyStatus == 1) {
+ DRM_DEBUG_KMS("dp_aux_ch timeout\n");
+ return -ETIMEDOUT;
+ }
+
+ /* flags not zero */
+ if (args.v1.ucReplyStatus == 2) {
+ DRM_DEBUG_KMS("dp_aux_ch flags not zero\n");
+ return -EBUSY;
+ }
+
+ /* error */
+ if (args.v1.ucReplyStatus == 3) {
+ DRM_DEBUG_KMS("dp_aux_ch error\n");
+ return -EIO;
+ }
+
+ recv_bytes = args.v1.ucDataOutLen;
+ if (recv_bytes > recv_size)
+ recv_bytes = recv_size;
+
+ if (recv && recv_size)
+ memcpy(recv, base + 16, recv_bytes);
+
+ return recv_bytes;
+}
+
+static int radeon_dp_aux_native_write(struct radeon_connector *radeon_connector,
+ u16 address, u8 *send, u8 send_bytes, u8 delay)
+{
+ struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
+ int ret;
+ u8 msg[20];
+ int msg_bytes = send_bytes + 4;
+ u8 ack;
+
+ if (send_bytes > 16)
+ return -1;
+
+ msg[0] = address;
+ msg[1] = address >> 8;
+ msg[2] = AUX_NATIVE_WRITE << 4;
+ msg[3] = (msg_bytes << 4) | (send_bytes - 1);
+ memcpy(&msg[4], send, send_bytes);
+
+ while (1) {
+ ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,
+ msg, msg_bytes, NULL, 0, delay, &ack);
+ if (ret < 0)
+ return ret;
+ if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
+ break;
+ else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
+ udelay(400);
+ else
+ return -EIO;
+ }
+
+ return send_bytes;
+}
+
+static int radeon_dp_aux_native_read(struct radeon_connector *radeon_connector,
+ u16 address, u8 *recv, int recv_bytes, u8 delay)
+{
+ struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
+ u8 msg[4];
+ int msg_bytes = 4;
+ u8 ack;
+ int ret;
+
+ msg[0] = address;
+ msg[1] = address >> 8;
+ msg[2] = AUX_NATIVE_READ << 4;
+ msg[3] = (msg_bytes << 4) | (recv_bytes - 1);
+
+ while (1) {
+ ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus,
+ msg, msg_bytes, recv, recv_bytes, delay, &ack);
+ if (ret == 0)
+ return -EPROTO;
+ if (ret < 0)
+ return ret;
+ if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
+ return ret;
+ else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
+ udelay(400);
+ else
+ return -EIO;
+ }
+}
+
+static void radeon_write_dpcd_reg(struct radeon_connector *radeon_connector,
+ u16 reg, u8 val)
+{
+ radeon_dp_aux_native_write(radeon_connector, reg, &val, 1, 0);
+}
+
+static u8 radeon_read_dpcd_reg(struct radeon_connector *radeon_connector,
+ u16 reg)
+{
+ u8 val = 0;
+
+ radeon_dp_aux_native_read(radeon_connector, reg, &val, 1, 0);
+
+ return val;
+}
+
+int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
+ u8 write_byte, u8 *read_byte)
+{
+ struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
+ struct radeon_i2c_chan *auxch = (struct radeon_i2c_chan *)adapter;
+ u16 address = algo_data->address;
+ u8 msg[5];
+ u8 reply[2];
+ unsigned retry;
+ int msg_bytes;
+ int reply_bytes = 1;
+ int ret;
+ u8 ack;
+
+ /* Set up the command byte */
+ if (mode & MODE_I2C_READ)
+ msg[2] = AUX_I2C_READ << 4;
+ else
+ msg[2] = AUX_I2C_WRITE << 4;
+
+ if (!(mode & MODE_I2C_STOP))
+ msg[2] |= AUX_I2C_MOT << 4;
+
+ msg[0] = address;
+ msg[1] = address >> 8;
+
+ switch (mode) {
+ case MODE_I2C_WRITE:
+ msg_bytes = 5;
+ msg[3] = msg_bytes << 4;
+ msg[4] = write_byte;
break;
- case DP_LINK_BW_2_7:
- for (i = 0; i < num_dp_clocks; i++) {
- switch (max_lane_count) {
- case 1:
- if (i > 1)
- return 0;
- break;
- case 2:
- if (i > 3)
- return 0;
- break;
- case 4:
- default:
- break;
- }
- if (dp_clocks[i] > mode_clock) {
- if (i < 2)
- return 1;
- else if (i < 4)
- return 2;
- else
- return 4;
- }
- }
+ case MODE_I2C_READ:
+ msg_bytes = 4;
+ msg[3] = msg_bytes << 4;
+ break;
+ default:
+ msg_bytes = 4;
+ msg[3] = 3 << 4;
break;
}
- return 0;
-}
-
-static int dp_link_clock_for_mode_clock(u8 dpcd[DP_DPCD_SIZE], int mode_clock)
-{
- int i;
- u8 max_link_bw;
- u8 max_lane_count;
-
- if (!dpcd)
- return 0;
-
- max_link_bw = dpcd[DP_MAX_LINK_RATE];
- max_lane_count = dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
-
- switch (max_link_bw) {
- case DP_LINK_BW_1_62:
- default:
- for (i = 0; i < num_dp_clocks; i++) {
- if (i % 2)
- continue;
- switch (max_lane_count) {
- case 1:
- if (i > 1)
- return 0;
- break;
- case 2:
- if (i > 3)
- return 0;
- break;
- case 4:
- default:
- break;
- }
- if (dp_clocks[i] > mode_clock)
- return 162000;
+ for (retry = 0; retry < 4; retry++) {
+ ret = radeon_process_aux_ch(auxch,
+ msg, msg_bytes, reply, reply_bytes, 0, &ack);
+ if (ret < 0) {
+ DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
+ return ret;
}
- break;
- case DP_LINK_BW_2_7:
- for (i = 0; i < num_dp_clocks; i++) {
- switch (max_lane_count) {
- case 1:
- if (i > 1)
- return 0;
- break;
- case 2:
- if (i > 3)
- return 0;
- break;
- case 4:
- default:
- break;
- }
- if (dp_clocks[i] > mode_clock)
- return (i % 2) ? 270000 : 162000;
+
+ switch (ack & AUX_NATIVE_REPLY_MASK) {
+ case AUX_NATIVE_REPLY_ACK:
+ /* I2C-over-AUX Reply field is only valid
+ * when paired with AUX ACK.
+ */
+ break;
+ case AUX_NATIVE_REPLY_NACK:
+ DRM_DEBUG_KMS("aux_ch native nack\n");
+ return -EREMOTEIO;
+ case AUX_NATIVE_REPLY_DEFER:
+ DRM_DEBUG_KMS("aux_ch native defer\n");
+ udelay(400);
+ continue;
+ default:
+ DRM_ERROR("aux_ch invalid native reply 0x%02x\n", ack);
+ return -EREMOTEIO;
+ }
+
+ switch (ack & AUX_I2C_REPLY_MASK) {
+ case AUX_I2C_REPLY_ACK:
+ if (mode == MODE_I2C_READ)
+ *read_byte = reply[0];
+ return ret;
+ case AUX_I2C_REPLY_NACK:
+ DRM_DEBUG_KMS("aux_i2c nack\n");
+ return -EREMOTEIO;
+ case AUX_I2C_REPLY_DEFER:
+ DRM_DEBUG_KMS("aux_i2c defer\n");
+ udelay(400);
+ break;
+ default:
+ DRM_ERROR("aux_i2c invalid reply 0x%02x\n", ack);
+ return -EREMOTEIO;
}
}
- return 0;
+ DRM_ERROR("aux i2c too many retries, giving up\n");
+ return -EREMOTEIO;
}
-int dp_mode_valid(u8 dpcd[DP_DPCD_SIZE], int mode_clock)
-{
- int lanes = dp_lanes_for_mode_clock(dpcd, mode_clock);
- int dp_clock = dp_link_clock_for_mode_clock(dpcd, mode_clock);
-
- if ((lanes == 0) || (dp_clock == 0))
- return MODE_CLOCK_HIGH;
-
- return MODE_OK;
-}
+/***** general DP utility functions *****/
static u8 dp_link_status(u8 link_status[DP_LINK_STATUS_SIZE], int r)
{
@@ -242,7 +326,7 @@
return true;
}
-static u8 dp_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
+static u8 dp_get_adjust_request_voltage(u8 link_status[DP_LINK_STATUS_SIZE],
int lane)
{
@@ -255,7 +339,7 @@
return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
}
-static u8 dp_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
+static u8 dp_get_adjust_request_pre_emphasis(u8 link_status[DP_LINK_STATUS_SIZE],
int lane)
{
int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
@@ -267,22 +351,8 @@
return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
}
-/* XXX fix me -- chip specific */
#define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200
-static u8 dp_pre_emphasis_max(u8 voltage_swing)
-{
- switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
- case DP_TRAIN_VOLTAGE_SWING_400:
- return DP_TRAIN_PRE_EMPHASIS_6;
- case DP_TRAIN_VOLTAGE_SWING_600:
- return DP_TRAIN_PRE_EMPHASIS_6;
- case DP_TRAIN_VOLTAGE_SWING_800:
- return DP_TRAIN_PRE_EMPHASIS_3_5;
- case DP_TRAIN_VOLTAGE_SWING_1200:
- default:
- return DP_TRAIN_PRE_EMPHASIS_0;
- }
-}
+#define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPHASIS_9_5
static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE],
int lane_count,
@@ -308,10 +378,10 @@
}
if (v >= DP_VOLTAGE_MAX)
- v = DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
+ v |= DP_TRAIN_MAX_SWING_REACHED;
- if (p >= dp_pre_emphasis_max(v))
- p = dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
+ if (p >= DP_PRE_EMPHASIS_MAX)
+ p |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
DRM_DEBUG_KMS("using signal parameters: voltage %s pre_emph %s\n",
voltage_names[(v & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT],
@@ -321,110 +391,109 @@
train_set[lane] = v | p;
}
-union aux_channel_transaction {
- PROCESS_AUX_CHANNEL_TRANSACTION_PS_ALLOCATION v1;
- PROCESS_AUX_CHANNEL_TRANSACTION_PARAMETERS_V2 v2;
-};
-
-/* radeon aux chan functions */
-bool radeon_process_aux_ch(struct radeon_i2c_chan *chan, u8 *req_bytes,
- int num_bytes, u8 *read_byte,
- u8 read_buf_len, u8 delay)
+/* convert bits per color to bits per pixel */
+/* get bpc from the EDID */
+static int convert_bpc_to_bpp(int bpc)
{
- struct drm_device *dev = chan->dev;
- struct radeon_device *rdev = dev->dev_private;
- union aux_channel_transaction args;
- int index = GetIndexIntoMasterTable(COMMAND, ProcessAuxChannelTransaction);
- unsigned char *base;
- int retry_count = 0;
+ if (bpc == 0)
+ return 24;
+ else
+ return bpc * 3;
+}
- memset(&args, 0, sizeof(args));
+/* get the max pix clock supported by the link rate and lane num */
+static int dp_get_max_dp_pix_clock(int link_rate,
+ int lane_num,
+ int bpp)
+{
+ return (link_rate * lane_num * 8) / bpp;
+}
- base = (unsigned char *)rdev->mode_info.atom_context->scratch;
+static int dp_get_max_link_rate(u8 dpcd[DP_DPCD_SIZE])
+{
+ switch (dpcd[DP_MAX_LINK_RATE]) {
+ case DP_LINK_BW_1_62:
+ default:
+ return 162000;
+ case DP_LINK_BW_2_7:
+ return 270000;
+ case DP_LINK_BW_5_4:
+ return 540000;
+ }
+}
-retry:
- memcpy(base, req_bytes, num_bytes);
+static u8 dp_get_max_lane_number(u8 dpcd[DP_DPCD_SIZE])
+{
+ return dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MASK;
+}
- args.v1.lpAuxRequest = 0;
- args.v1.lpDataOut = 16;
- args.v1.ucDataOutLen = 0;
- args.v1.ucChannelID = chan->rec.i2c_id;
- args.v1.ucDelay = delay / 10;
- if (ASIC_IS_DCE4(rdev))
- args.v2.ucHPD_ID = chan->rec.hpd;
+static u8 dp_get_dp_link_rate_coded(int link_rate)
+{
+ switch (link_rate) {
+ case 162000:
+ default:
+ return DP_LINK_BW_1_62;
+ case 270000:
+ return DP_LINK_BW_2_7;
+ case 540000:
+ return DP_LINK_BW_5_4;
+ }
+}
- atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
+/***** radeon specific DP functions *****/
- if (args.v1.ucReplyStatus && !args.v1.ucDataOutLen) {
- if (args.v1.ucReplyStatus == 0x20 && retry_count++ < 10)
- goto retry;
- DRM_DEBUG_KMS("failed to get auxch %02x%02x %02x %02x 0x%02x %02x after %d retries\n",
- req_bytes[1], req_bytes[0], req_bytes[2], req_bytes[3],
- chan->rec.i2c_id, args.v1.ucReplyStatus, retry_count);
- return false;
+/* First get the min lane# when low rate is used according to pixel clock
+ * (prefer low rate), second check max lane# supported by DP panel,
+ * if the max lane# < low rate lane# then use max lane# instead.
+ */
+static int radeon_dp_get_dp_lane_number(struct drm_connector *connector,
+ u8 dpcd[DP_DPCD_SIZE],
+ int pix_clock)
+{
+ int bpp = convert_bpc_to_bpp(connector->display_info.bpc);
+ int max_link_rate = dp_get_max_link_rate(dpcd);
+ int max_lane_num = dp_get_max_lane_number(dpcd);
+ int lane_num;
+ int max_dp_pix_clock;
+
+ for (lane_num = 1; lane_num < max_lane_num; lane_num <<= 1) {
+ max_dp_pix_clock = dp_get_max_dp_pix_clock(max_link_rate, lane_num, bpp);
+ if (pix_clock <= max_dp_pix_clock)
+ break;
}
- if (args.v1.ucDataOutLen && read_byte && read_buf_len) {
- if (read_buf_len < args.v1.ucDataOutLen) {
- DRM_ERROR("Buffer to small for return answer %d %d\n",
- read_buf_len, args.v1.ucDataOutLen);
- return false;
- }
- {
- int len = min(read_buf_len, args.v1.ucDataOutLen);
- memcpy(read_byte, base + 16, len);
- }
+ return lane_num;
+}
+
+static int radeon_dp_get_dp_link_clock(struct drm_connector *connector,
+ u8 dpcd[DP_DPCD_SIZE],
+ int pix_clock)
+{
+ int bpp = convert_bpc_to_bpp(connector->display_info.bpc);
+ int lane_num, max_pix_clock;
+
+ if (radeon_connector_encoder_is_dp_bridge(connector))
+ return 270000;
+
+ lane_num = radeon_dp_get_dp_lane_number(connector, dpcd, pix_clock);
+ max_pix_clock = dp_get_max_dp_pix_clock(162000, lane_num, bpp);
+ if (pix_clock <= max_pix_clock)
+ return 162000;
+ max_pix_clock = dp_get_max_dp_pix_clock(270000, lane_num, bpp);
+ if (pix_clock <= max_pix_clock)
+ return 270000;
+ if (radeon_connector_is_dp12_capable(connector)) {
+ max_pix_clock = dp_get_max_dp_pix_clock(540000, lane_num, bpp);
+ if (pix_clock <= max_pix_clock)
+ return 540000;
}
- return true;
+
+ return dp_get_max_link_rate(dpcd);
}
-bool radeon_dp_aux_native_write(struct radeon_connector *radeon_connector, uint16_t address,
- uint8_t send_bytes, uint8_t *send)
-{
- struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
- u8 msg[20];
- u8 msg_len, dp_msg_len;
- bool ret;
-
- dp_msg_len = 4;
- msg[0] = address;
- msg[1] = address >> 8;
- msg[2] = AUX_NATIVE_WRITE << 4;
- dp_msg_len += send_bytes;
- msg[3] = (dp_msg_len << 4) | (send_bytes - 1);
-
- if (send_bytes > 16)
- return false;
-
- memcpy(&msg[4], send, send_bytes);
- msg_len = 4 + send_bytes;
- ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus, msg, msg_len, NULL, 0, 0);
- return ret;
-}
-
-bool radeon_dp_aux_native_read(struct radeon_connector *radeon_connector, uint16_t address,
- uint8_t delay, uint8_t expected_bytes,
- uint8_t *read_p)
-{
- struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
- u8 msg[20];
- u8 msg_len, dp_msg_len;
- bool ret = false;
- msg_len = 4;
- dp_msg_len = 4;
- msg[0] = address;
- msg[1] = address >> 8;
- msg[2] = AUX_NATIVE_READ << 4;
- msg[3] = (dp_msg_len) << 4;
- msg[3] |= expected_bytes - 1;
-
- ret = radeon_process_aux_ch(dig_connector->dp_i2c_bus, msg, msg_len, read_p, expected_bytes, delay);
- return ret;
-}
-
-/* radeon dp functions */
-static u8 radeon_dp_encoder_service(struct radeon_device *rdev, int action, int dp_clock,
- uint8_t ucconfig, uint8_t lane_num)
+static u8 radeon_dp_encoder_service(struct radeon_device *rdev,
+ int action, int dp_clock,
+ u8 ucconfig, u8 lane_num)
{
DP_ENCODER_SERVICE_PARAMETERS args;
int index = GetIndexIntoMasterTable(COMMAND, DPEncoderService);
@@ -454,60 +523,86 @@
{
struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
u8 msg[25];
- int ret;
+ int ret, i;
- ret = radeon_dp_aux_native_read(radeon_connector, DP_DPCD_REV, 0, 8, msg);
- if (ret) {
+ ret = radeon_dp_aux_native_read(radeon_connector, DP_DPCD_REV, msg, 8, 0);
+ if (ret > 0) {
memcpy(dig_connector->dpcd, msg, 8);
- {
- int i;
- DRM_DEBUG_KMS("DPCD: ");
- for (i = 0; i < 8; i++)
- DRM_DEBUG_KMS("%02x ", msg[i]);
- DRM_DEBUG_KMS("\n");
- }
+ DRM_DEBUG_KMS("DPCD: ");
+ for (i = 0; i < 8; i++)
+ DRM_DEBUG_KMS("%02x ", msg[i]);
+ DRM_DEBUG_KMS("\n");
return true;
}
dig_connector->dpcd[0] = 0;
return false;
}
+static void radeon_dp_set_panel_mode(struct drm_encoder *encoder,
+ struct drm_connector *connector)
+{
+ struct drm_device *dev = encoder->dev;
+ struct radeon_device *rdev = dev->dev_private;
+ int panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
+
+ if (!ASIC_IS_DCE4(rdev))
+ return;
+
+ if (radeon_connector_encoder_is_dp_bridge(connector))
+ panel_mode = DP_PANEL_MODE_INTERNAL_DP1_MODE;
+
+ atombios_dig_encoder_setup(encoder,
+ ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
+ panel_mode);
+}
+
void radeon_dp_set_link_config(struct drm_connector *connector,
struct drm_display_mode *mode)
{
- struct radeon_connector *radeon_connector;
+ struct radeon_connector *radeon_connector = to_radeon_connector(connector);
struct radeon_connector_atom_dig *dig_connector;
- if ((connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) &&
- (connector->connector_type != DRM_MODE_CONNECTOR_eDP))
- return;
-
- radeon_connector = to_radeon_connector(connector);
if (!radeon_connector->con_priv)
return;
dig_connector = radeon_connector->con_priv;
- dig_connector->dp_clock =
- dp_link_clock_for_mode_clock(dig_connector->dpcd, mode->clock);
- dig_connector->dp_lane_count =
- dp_lanes_for_mode_clock(dig_connector->dpcd, mode->clock);
+ if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
+ (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
+ dig_connector->dp_clock =
+ radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
+ dig_connector->dp_lane_count =
+ radeon_dp_get_dp_lane_number(connector, dig_connector->dpcd, mode->clock);
+ }
}
-int radeon_dp_mode_valid_helper(struct radeon_connector *radeon_connector,
+int radeon_dp_mode_valid_helper(struct drm_connector *connector,
struct drm_display_mode *mode)
{
- struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
+ struct radeon_connector *radeon_connector = to_radeon_connector(connector);
+ struct radeon_connector_atom_dig *dig_connector;
+ int dp_clock;
- return dp_mode_valid(dig_connector->dpcd, mode->clock);
+ if (!radeon_connector->con_priv)
+ return MODE_CLOCK_HIGH;
+ dig_connector = radeon_connector->con_priv;
+
+ dp_clock =
+ radeon_dp_get_dp_link_clock(connector, dig_connector->dpcd, mode->clock);
+
+ if ((dp_clock == 540000) &&
+ (!radeon_connector_is_dp12_capable(connector)))
+ return MODE_CLOCK_HIGH;
+
+ return MODE_OK;
}
-static bool atom_dp_get_link_status(struct radeon_connector *radeon_connector,
- u8 link_status[DP_LINK_STATUS_SIZE])
+static bool radeon_dp_get_link_status(struct radeon_connector *radeon_connector,
+ u8 link_status[DP_LINK_STATUS_SIZE])
{
int ret;
- ret = radeon_dp_aux_native_read(radeon_connector, DP_LANE0_1_STATUS, 100,
- DP_LINK_STATUS_SIZE, link_status);
- if (!ret) {
+ ret = radeon_dp_aux_native_read(radeon_connector, DP_LANE0_1_STATUS,
+ link_status, DP_LINK_STATUS_SIZE, 100);
+ if (ret <= 0) {
DRM_ERROR("displayport link status failed\n");
return false;
}
@@ -518,66 +613,254 @@
return true;
}
-bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector)
-{
- struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
+struct radeon_dp_link_train_info {
+ struct radeon_device *rdev;
+ struct drm_encoder *encoder;
+ struct drm_connector *connector;
+ struct radeon_connector *radeon_connector;
+ int enc_id;
+ int dp_clock;
+ int dp_lane_count;
+ int rd_interval;
+ bool tp3_supported;
+ u8 dpcd[8];
+ u8 train_set[4];
u8 link_status[DP_LINK_STATUS_SIZE];
+ u8 tries;
+};
- if (!atom_dp_get_link_status(radeon_connector, link_status))
- return false;
- if (dp_channel_eq_ok(link_status, dig_connector->dp_lane_count))
- return false;
- return true;
+static void radeon_dp_update_vs_emph(struct radeon_dp_link_train_info *dp_info)
+{
+ /* set the initial vs/emph on the source */
+ atombios_dig_transmitter_setup(dp_info->encoder,
+ ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH,
+ 0, dp_info->train_set[0]); /* sets all lanes at once */
+
+ /* set the vs/emph on the sink */
+ radeon_dp_aux_native_write(dp_info->radeon_connector, DP_TRAINING_LANE0_SET,
+ dp_info->train_set, dp_info->dp_lane_count, 0);
}
-static void dp_set_power(struct radeon_connector *radeon_connector, u8 power_state)
+static void radeon_dp_set_tp(struct radeon_dp_link_train_info *dp_info, int tp)
{
- struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
+ int rtp = 0;
- if (dig_connector->dpcd[0] >= 0x11) {
- radeon_dp_aux_native_write(radeon_connector, DP_SET_POWER, 1,
- &power_state);
+ /* set training pattern on the source */
+ if (ASIC_IS_DCE4(dp_info->rdev)) {
+ switch (tp) {
+ case DP_TRAINING_PATTERN_1:
+ rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1;
+ break;
+ case DP_TRAINING_PATTERN_2:
+ rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2;
+ break;
+ case DP_TRAINING_PATTERN_3:
+ rtp = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3;
+ break;
+ }
+ atombios_dig_encoder_setup(dp_info->encoder, rtp, 0);
+ } else {
+ switch (tp) {
+ case DP_TRAINING_PATTERN_1:
+ rtp = 0;
+ break;
+ case DP_TRAINING_PATTERN_2:
+ rtp = 1;
+ break;
+ }
+ radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
+ dp_info->dp_clock, dp_info->enc_id, rtp);
+ }
+
+ /* enable training pattern on the sink */
+ radeon_write_dpcd_reg(dp_info->radeon_connector, DP_TRAINING_PATTERN_SET, tp);
+}
+
+static int radeon_dp_link_train_init(struct radeon_dp_link_train_info *dp_info)
+{
+ u8 tmp;
+
+ /* power up the sink */
+ if (dp_info->dpcd[0] >= 0x11)
+ radeon_write_dpcd_reg(dp_info->radeon_connector,
+ DP_SET_POWER, DP_SET_POWER_D0);
+
+ /* possibly enable downspread on the sink */
+ if (dp_info->dpcd[3] & 0x1)
+ radeon_write_dpcd_reg(dp_info->radeon_connector,
+ DP_DOWNSPREAD_CTRL, DP_SPREAD_AMP_0_5);
+ else
+ radeon_write_dpcd_reg(dp_info->radeon_connector,
+ DP_DOWNSPREAD_CTRL, 0);
+
+ radeon_dp_set_panel_mode(dp_info->encoder, dp_info->connector);
+
+ /* set the lane count on the sink */
+ tmp = dp_info->dp_lane_count;
+ if (dp_info->dpcd[0] >= 0x11)
+ tmp |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
+ radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LANE_COUNT_SET, tmp);
+
+ /* set the link rate on the sink */
+ tmp = dp_get_dp_link_rate_coded(dp_info->dp_clock);
+ radeon_write_dpcd_reg(dp_info->radeon_connector, DP_LINK_BW_SET, tmp);
+
+ /* start training on the source */
+ if (ASIC_IS_DCE4(dp_info->rdev))
+ atombios_dig_encoder_setup(dp_info->encoder,
+ ATOM_ENCODER_CMD_DP_LINK_TRAINING_START, 0);
+ else
+ radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_START,
+ dp_info->dp_clock, dp_info->enc_id, 0);
+
+ /* disable the training pattern on the sink */
+ radeon_write_dpcd_reg(dp_info->radeon_connector,
+ DP_TRAINING_PATTERN_SET,
+ DP_TRAINING_PATTERN_DISABLE);
+
+ return 0;
+}
+
+static int radeon_dp_link_train_finish(struct radeon_dp_link_train_info *dp_info)
+{
+ udelay(400);
+
+ /* disable the training pattern on the sink */
+ radeon_write_dpcd_reg(dp_info->radeon_connector,
+ DP_TRAINING_PATTERN_SET,
+ DP_TRAINING_PATTERN_DISABLE);
+
+ /* disable the training pattern on the source */
+ if (ASIC_IS_DCE4(dp_info->rdev))
+ atombios_dig_encoder_setup(dp_info->encoder,
+ ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE, 0);
+ else
+ radeon_dp_encoder_service(dp_info->rdev, ATOM_DP_ACTION_TRAINING_COMPLETE,
+ dp_info->dp_clock, dp_info->enc_id, 0);
+
+ return 0;
+}
+
+static int radeon_dp_link_train_cr(struct radeon_dp_link_train_info *dp_info)
+{
+ bool clock_recovery;
+ u8 voltage;
+ int i;
+
+ radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_1);
+ memset(dp_info->train_set, 0, 4);
+ radeon_dp_update_vs_emph(dp_info);
+
+ udelay(400);
+
+ /* clock recovery loop */
+ clock_recovery = false;
+ dp_info->tries = 0;
+ voltage = 0xff;
+ while (1) {
+ if (dp_info->rd_interval == 0)
+ udelay(100);
+ else
+ mdelay(dp_info->rd_interval * 4);
+
+ if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status))
+ break;
+
+ if (dp_clock_recovery_ok(dp_info->link_status, dp_info->dp_lane_count)) {
+ clock_recovery = true;
+ break;
+ }
+
+ for (i = 0; i < dp_info->dp_lane_count; i++) {
+ if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
+ break;
+ }
+ if (i == dp_info->dp_lane_count) {
+ DRM_ERROR("clock recovery reached max voltage\n");
+ break;
+ }
+
+ if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
+ ++dp_info->tries;
+ if (dp_info->tries == 5) {
+ DRM_ERROR("clock recovery tried 5 times\n");
+ break;
+ }
+ } else
+ dp_info->tries = 0;
+
+ voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
+
+ /* Compute new train_set as requested by sink */
+ dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
+
+ radeon_dp_update_vs_emph(dp_info);
+ }
+ if (!clock_recovery) {
+ DRM_ERROR("clock recovery failed\n");
+ return -1;
+ } else {
+ DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n",
+ dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
+ (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
+ DP_TRAIN_PRE_EMPHASIS_SHIFT);
+ return 0;
}
}
-static void dp_set_downspread(struct radeon_connector *radeon_connector, u8 downspread)
+static int radeon_dp_link_train_ce(struct radeon_dp_link_train_info *dp_info)
{
- radeon_dp_aux_native_write(radeon_connector, DP_DOWNSPREAD_CTRL, 1,
- &downspread);
+ bool channel_eq;
+
+ if (dp_info->tp3_supported)
+ radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_3);
+ else
+ radeon_dp_set_tp(dp_info, DP_TRAINING_PATTERN_2);
+
+ /* channel equalization loop */
+ dp_info->tries = 0;
+ channel_eq = false;
+ while (1) {
+ if (dp_info->rd_interval == 0)
+ udelay(400);
+ else
+ mdelay(dp_info->rd_interval * 4);
+
+ if (!radeon_dp_get_link_status(dp_info->radeon_connector, dp_info->link_status))
+ break;
+
+ if (dp_channel_eq_ok(dp_info->link_status, dp_info->dp_lane_count)) {
+ channel_eq = true;
+ break;
+ }
+
+ /* Try 5 times */
+ if (dp_info->tries > 5) {
+ DRM_ERROR("channel eq failed: 5 tries\n");
+ break;
+ }
+
+ /* Compute new train_set as requested by sink */
+ dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set);
+
+ radeon_dp_update_vs_emph(dp_info);
+ dp_info->tries++;
+ }
+
+ if (!channel_eq) {
+ DRM_ERROR("channel eq failed\n");
+ return -1;
+ } else {
+ DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n",
+ dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
+ (dp_info->train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
+ >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
+ return 0;
+ }
}
-static void dp_set_link_bw_lanes(struct radeon_connector *radeon_connector,
- u8 link_configuration[DP_LINK_CONFIGURATION_SIZE])
-{
- radeon_dp_aux_native_write(radeon_connector, DP_LINK_BW_SET, 2,
- link_configuration);
-}
-
-static void dp_update_dpvs_emph(struct radeon_connector *radeon_connector,
- struct drm_encoder *encoder,
- u8 train_set[4])
-{
- struct radeon_connector_atom_dig *dig_connector = radeon_connector->con_priv;
- int i;
-
- for (i = 0; i < dig_connector->dp_lane_count; i++)
- atombios_dig_transmitter_setup(encoder,
- ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH,
- i, train_set[i]);
-
- radeon_dp_aux_native_write(radeon_connector, DP_TRAINING_LANE0_SET,
- dig_connector->dp_lane_count, train_set);
-}
-
-static void dp_set_training(struct radeon_connector *radeon_connector,
- u8 training)
-{
- radeon_dp_aux_native_write(radeon_connector, DP_TRAINING_PATTERN_SET,
- 1, &training);
-}
-
-void dp_link_train(struct drm_encoder *encoder,
- struct drm_connector *connector)
+void radeon_dp_link_train(struct drm_encoder *encoder,
+ struct drm_connector *connector)
{
struct drm_device *dev = encoder->dev;
struct radeon_device *rdev = dev->dev_private;
@@ -585,17 +868,8 @@
struct radeon_encoder_atom_dig *dig;
struct radeon_connector *radeon_connector;
struct radeon_connector_atom_dig *dig_connector;
- int enc_id = 0;
- bool clock_recovery, channel_eq;
- u8 link_status[DP_LINK_STATUS_SIZE];
- u8 link_configuration[DP_LINK_CONFIGURATION_SIZE];
- u8 tries, voltage;
- u8 train_set[4];
- int i;
-
- if ((connector->connector_type != DRM_MODE_CONNECTOR_DisplayPort) &&
- (connector->connector_type != DRM_MODE_CONNECTOR_eDP))
- return;
+ struct radeon_dp_link_train_info dp_info;
+ u8 tmp;
if (!radeon_encoder->enc_priv)
return;
@@ -606,204 +880,42 @@
return;
dig_connector = radeon_connector->con_priv;
+ if ((dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_DISPLAYPORT) &&
+ (dig_connector->dp_sink_type != CONNECTOR_OBJECT_ID_eDP))
+ return;
+
+ dp_info.enc_id = 0;
if (dig->dig_encoder)
- enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER;
+ dp_info.enc_id |= ATOM_DP_CONFIG_DIG2_ENCODER;
else
- enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER;
+ dp_info.enc_id |= ATOM_DP_CONFIG_DIG1_ENCODER;
if (dig->linkb)
- enc_id |= ATOM_DP_CONFIG_LINK_B;
+ dp_info.enc_id |= ATOM_DP_CONFIG_LINK_B;
else
- enc_id |= ATOM_DP_CONFIG_LINK_A;
+ dp_info.enc_id |= ATOM_DP_CONFIG_LINK_A;
- memset(link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
- if (dig_connector->dp_clock == 270000)
- link_configuration[0] = DP_LINK_BW_2_7;
+ dp_info.rd_interval = radeon_read_dpcd_reg(radeon_connector, DP_TRAINING_AUX_RD_INTERVAL);
+ tmp = radeon_read_dpcd_reg(radeon_connector, DP_MAX_LANE_COUNT);
+ if (ASIC_IS_DCE5(rdev) && (tmp & DP_TPS3_SUPPORTED))
+ dp_info.tp3_supported = true;
else
- link_configuration[0] = DP_LINK_BW_1_62;
- link_configuration[1] = dig_connector->dp_lane_count;
- if (dig_connector->dpcd[0] >= 0x11)
- link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
+ dp_info.tp3_supported = false;
- /* power up the sink */
- dp_set_power(radeon_connector, DP_SET_POWER_D0);
- /* disable the training pattern on the sink */
- dp_set_training(radeon_connector, DP_TRAINING_PATTERN_DISABLE);
- /* set link bw and lanes on the sink */
- dp_set_link_bw_lanes(radeon_connector, link_configuration);
- /* disable downspread on the sink */
- dp_set_downspread(radeon_connector, 0);
- if (ASIC_IS_DCE4(rdev)) {
- /* start training on the source */
- atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_LINK_TRAINING_START);
- /* set training pattern 1 on the source */
- atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1);
- } else {
- /* start training on the source */
- radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_START,
- dig_connector->dp_clock, enc_id, 0);
- /* set training pattern 1 on the source */
- radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
- dig_connector->dp_clock, enc_id, 0);
- }
+ memcpy(dp_info.dpcd, dig_connector->dpcd, 8);
+ dp_info.rdev = rdev;
+ dp_info.encoder = encoder;
+ dp_info.connector = connector;
+ dp_info.radeon_connector = radeon_connector;
+ dp_info.dp_lane_count = dig_connector->dp_lane_count;
+ dp_info.dp_clock = dig_connector->dp_clock;
- /* set initial vs/emph */
- memset(train_set, 0, 4);
- udelay(400);
- /* set training pattern 1 on the sink */
- dp_set_training(radeon_connector, DP_TRAINING_PATTERN_1);
-
- dp_update_dpvs_emph(radeon_connector, encoder, train_set);
-
- /* clock recovery loop */
- clock_recovery = false;
- tries = 0;
- voltage = 0xff;
- for (;;) {
- udelay(100);
- if (!atom_dp_get_link_status(radeon_connector, link_status))
- break;
-
- if (dp_clock_recovery_ok(link_status, dig_connector->dp_lane_count)) {
- clock_recovery = true;
- break;
- }
-
- for (i = 0; i < dig_connector->dp_lane_count; i++) {
- if ((train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
- break;
- }
- if (i == dig_connector->dp_lane_count) {
- DRM_ERROR("clock recovery reached max voltage\n");
- break;
- }
-
- if ((train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
- ++tries;
- if (tries == 5) {
- DRM_ERROR("clock recovery tried 5 times\n");
- break;
- }
- } else
- tries = 0;
-
- voltage = train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
-
- /* Compute new train_set as requested by sink */
- dp_get_adjust_train(link_status, dig_connector->dp_lane_count, train_set);
- dp_update_dpvs_emph(radeon_connector, encoder, train_set);
- }
- if (!clock_recovery)
- DRM_ERROR("clock recovery failed\n");
- else
- DRM_DEBUG_KMS("clock recovery at voltage %d pre-emphasis %d\n",
- train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
- (train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK) >>
- DP_TRAIN_PRE_EMPHASIS_SHIFT);
-
-
- /* set training pattern 2 on the sink */
- dp_set_training(radeon_connector, DP_TRAINING_PATTERN_2);
- /* set training pattern 2 on the source */
- if (ASIC_IS_DCE4(rdev))
- atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2);
- else
- radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_PATTERN_SEL,
- dig_connector->dp_clock, enc_id, 1);
-
- /* channel equalization loop */
- tries = 0;
- channel_eq = false;
- for (;;) {
- udelay(400);
- if (!atom_dp_get_link_status(radeon_connector, link_status))
- break;
-
- if (dp_channel_eq_ok(link_status, dig_connector->dp_lane_count)) {
- channel_eq = true;
- break;
- }
-
- /* Try 5 times */
- if (tries > 5) {
- DRM_ERROR("channel eq failed: 5 tries\n");
- break;
- }
-
- /* Compute new train_set as requested by sink */
- dp_get_adjust_train(link_status, dig_connector->dp_lane_count, train_set);
- dp_update_dpvs_emph(radeon_connector, encoder, train_set);
-
- tries++;
- }
-
- if (!channel_eq)
- DRM_ERROR("channel eq failed\n");
- else
- DRM_DEBUG_KMS("channel eq at voltage %d pre-emphasis %d\n",
- train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK,
- (train_set[0] & DP_TRAIN_PRE_EMPHASIS_MASK)
- >> DP_TRAIN_PRE_EMPHASIS_SHIFT);
-
- /* disable the training pattern on the sink */
- dp_set_training(radeon_connector, DP_TRAINING_PATTERN_DISABLE);
-
- /* disable the training pattern on the source */
- if (ASIC_IS_DCE4(rdev))
- atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_LINK_TRAINING_COMPLETE);
- else
- radeon_dp_encoder_service(rdev, ATOM_DP_ACTION_TRAINING_COMPLETE,
- dig_connector->dp_clock, enc_id, 0);
+ if (radeon_dp_link_train_init(&dp_info))
+ goto done;
+ if (radeon_dp_link_train_cr(&dp_info))
+ goto done;
+ if (radeon_dp_link_train_ce(&dp_info))
+ goto done;
+done:
+ if (radeon_dp_link_train_finish(&dp_info))
+ return;
}
-
-int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
- uint8_t write_byte, uint8_t *read_byte)
-{
- struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
- struct radeon_i2c_chan *auxch = (struct radeon_i2c_chan *)adapter;
- int ret = 0;
- uint16_t address = algo_data->address;
- uint8_t msg[5];
- uint8_t reply[2];
- int msg_len, dp_msg_len;
- int reply_bytes;
-
- /* Set up the command byte */
- if (mode & MODE_I2C_READ)
- msg[2] = AUX_I2C_READ << 4;
- else
- msg[2] = AUX_I2C_WRITE << 4;
-
- if (!(mode & MODE_I2C_STOP))
- msg[2] |= AUX_I2C_MOT << 4;
-
- msg[0] = address;
- msg[1] = address >> 8;
-
- reply_bytes = 1;
-
- msg_len = 4;
- dp_msg_len = 3;
- switch (mode) {
- case MODE_I2C_WRITE:
- msg[4] = write_byte;
- msg_len++;
- dp_msg_len += 2;
- break;
- case MODE_I2C_READ:
- dp_msg_len += 1;
- break;
- default:
- break;
- }
-
- msg[3] = (dp_msg_len) << 4;
- ret = radeon_process_aux_ch(auxch, msg, msg_len, reply, reply_bytes, 0);
-
- if (ret) {
- if (read_byte)
- *read_byte = reply[0];
- return reply_bytes;
- }
- return -EREMOTEIO;
-}
-
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 9073e3b..7c37638 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -1578,7 +1578,7 @@
u32 sq_stack_resource_mgmt_2;
u32 sq_stack_resource_mgmt_3;
u32 vgt_cache_invalidation;
- u32 hdp_host_path_cntl;
+ u32 hdp_host_path_cntl, tmp;
int i, j, num_shader_engines, ps_thread_count;
switch (rdev->family) {
@@ -1936,8 +1936,12 @@
rdev->config.evergreen.tile_config |= (3 << 0);
break;
}
- rdev->config.evergreen.tile_config |=
- ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
+ /* num banks is 8 on all fusion asics */
+ if (rdev->flags & RADEON_IS_IGP)
+ rdev->config.evergreen.tile_config |= 8 << 4;
+ else
+ rdev->config.evergreen.tile_config |=
+ ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
rdev->config.evergreen.tile_config |=
((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) << 8;
rdev->config.evergreen.tile_config |=
@@ -2141,6 +2145,10 @@
for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4)
WREG32(i, 0);
+ tmp = RREG32(HDP_MISC_CNTL);
+ tmp |= HDP_FLUSH_INVALIDATE_CACHE;
+ WREG32(HDP_MISC_CNTL, tmp);
+
hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index fc40e0c..f37e91e 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -64,6 +64,8 @@
#define GB_BACKEND_MAP 0x98FC
#define DMIF_ADDR_CONFIG 0xBD4
#define HDP_ADDR_CONFIG 0x2F48
+#define HDP_MISC_CNTL 0x2F4C
+#define HDP_FLUSH_INVALIDATE_CACHE (1 << 0)
#define CC_SYS_RB_BACKEND_DISABLE 0x3F88
#define GC_USER_RB_BACKEND_DISABLE 0x9B7C
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 3d8a763..b205ba1 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -417,7 +417,7 @@
num_shader_engines = 1;
if (num_shader_engines > rdev->config.cayman.max_shader_engines)
num_shader_engines = rdev->config.cayman.max_shader_engines;
- if (num_backends_per_asic > num_shader_engines)
+ if (num_backends_per_asic < num_shader_engines)
num_backends_per_asic = num_shader_engines;
if (num_backends_per_asic > (rdev->config.cayman.max_backends_per_se * num_shader_engines))
num_backends_per_asic = rdev->config.cayman.max_backends_per_se * num_shader_engines;
@@ -829,7 +829,7 @@
rdev->config.cayman.tile_config |=
((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
rdev->config.cayman.tile_config |=
- (gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT;
+ ((gb_addr_config & PIPE_INTERLEAVE_SIZE_MASK) >> PIPE_INTERLEAVE_SIZE_SHIFT) << 8;
rdev->config.cayman.tile_config |=
((gb_addr_config & ROW_SIZE_MASK) >> ROW_SIZE_SHIFT) << 12;
@@ -931,6 +931,10 @@
WREG32(CB_PERF_CTR3_SEL_0, 0);
WREG32(CB_PERF_CTR3_SEL_1, 0);
+ tmp = RREG32(HDP_MISC_CNTL);
+ tmp |= HDP_FLUSH_INVALIDATE_CACHE;
+ WREG32(HDP_MISC_CNTL, tmp);
+
hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
diff --git a/drivers/gpu/drm/radeon/nid.h b/drivers/gpu/drm/radeon/nid.h
index 0f9a08b..9736746 100644
--- a/drivers/gpu/drm/radeon/nid.h
+++ b/drivers/gpu/drm/radeon/nid.h
@@ -136,6 +136,8 @@
#define HDP_NONSURFACE_INFO 0x2C08
#define HDP_NONSURFACE_SIZE 0x2C0C
#define HDP_ADDR_CONFIG 0x2F48
+#define HDP_MISC_CNTL 0x2F4C
+#define HDP_FLUSH_INVALIDATE_CACHE (1 << 0)
#define CC_SYS_RB_BACKEND_DISABLE 0x3F88
#define GC_USER_SYS_RB_BACKEND_DISABLE 0x3F8C
@@ -351,7 +353,7 @@
#define MULTI_GPU_TILE_SIZE_MASK 0x03000000
#define MULTI_GPU_TILE_SIZE_SHIFT 24
#define ROW_SIZE(x) ((x) << 28)
-#define ROW_SIZE_MASK 0x30000007
+#define ROW_SIZE_MASK 0x30000000
#define ROW_SIZE_SHIFT 28
#define NUM_LOWER_PIPES(x) ((x) << 30)
#define NUM_LOWER_PIPES_MASK 0x40000000
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
index ca57619..d948265 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -782,6 +782,7 @@
.hpd_fini = &evergreen_hpd_fini,
.hpd_sense = &evergreen_hpd_sense,
.hpd_set_polarity = &evergreen_hpd_set_polarity,
+ .ioctl_wait_idle = r600_ioctl_wait_idle,
.gui_idle = &r600_gui_idle,
.pm_misc = &evergreen_pm_misc,
.pm_prepare = &evergreen_pm_prepare,
@@ -828,6 +829,7 @@
.hpd_fini = &evergreen_hpd_fini,
.hpd_sense = &evergreen_hpd_sense,
.hpd_set_polarity = &evergreen_hpd_set_polarity,
+ .ioctl_wait_idle = r600_ioctl_wait_idle,
.gui_idle = &r600_gui_idle,
.pm_misc = &evergreen_pm_misc,
.pm_prepare = &evergreen_pm_prepare,
@@ -874,6 +876,7 @@
.hpd_fini = &evergreen_hpd_fini,
.hpd_sense = &evergreen_hpd_sense,
.hpd_set_polarity = &evergreen_hpd_set_polarity,
+ .ioctl_wait_idle = r600_ioctl_wait_idle,
.gui_idle = &r600_gui_idle,
.pm_misc = &evergreen_pm_misc,
.pm_prepare = &evergreen_pm_prepare,
@@ -920,6 +923,7 @@
.hpd_fini = &evergreen_hpd_fini,
.hpd_sense = &evergreen_hpd_sense,
.hpd_set_polarity = &evergreen_hpd_set_polarity,
+ .ioctl_wait_idle = r600_ioctl_wait_idle,
.gui_idle = &r600_gui_idle,
.pm_misc = &evergreen_pm_misc,
.pm_prepare = &evergreen_pm_prepare,
diff --git a/drivers/gpu/drm/radeon/radeon_combios.c b/drivers/gpu/drm/radeon/radeon_combios.c
index 8caf546..5b991f7 100644
--- a/drivers/gpu/drm/radeon/radeon_combios.c
+++ b/drivers/gpu/drm/radeon/radeon_combios.c
@@ -505,12 +505,18 @@
* DDC_VGA = RADEON_GPIO_VGA_DDC
* DDC_LCD = RADEON_GPIOPAD_MASK
* DDC_GPIO = RADEON_MDGPIO_MASK
- * r1xx/r2xx
+ * r1xx
* DDC_MONID = RADEON_GPIO_MONID
* DDC_CRT2 = RADEON_GPIO_CRT2_DDC
- * r3xx
+ * r200
* DDC_MONID = RADEON_GPIO_MONID
* DDC_CRT2 = RADEON_GPIO_DVI_DDC
+ * r300/r350
+ * DDC_MONID = RADEON_GPIO_DVI_DDC
+ * DDC_CRT2 = RADEON_GPIO_DVI_DDC
+ * rv2xx/rv3xx
+ * DDC_MONID = RADEON_GPIO_MONID
+ * DDC_CRT2 = RADEON_GPIO_MONID
* rs3xx/rs4xx
* DDC_MONID = RADEON_GPIOPAD_MASK
* DDC_CRT2 = RADEON_GPIO_MONID
@@ -537,17 +543,26 @@
rdev->family == CHIP_RS400 ||
rdev->family == CHIP_RS480)
ddc_line = RADEON_GPIOPAD_MASK;
- else
+ else if (rdev->family == CHIP_R300 ||
+ rdev->family == CHIP_R350) {
+ ddc_line = RADEON_GPIO_DVI_DDC;
+ ddc = DDC_DVI;
+ } else
ddc_line = RADEON_GPIO_MONID;
break;
case DDC_CRT2:
- if (rdev->family == CHIP_RS300 ||
- rdev->family == CHIP_RS400 ||
- rdev->family == CHIP_RS480)
- ddc_line = RADEON_GPIO_MONID;
- else if (rdev->family >= CHIP_R300) {
+ if (rdev->family == CHIP_R200 ||
+ rdev->family == CHIP_R300 ||
+ rdev->family == CHIP_R350) {
ddc_line = RADEON_GPIO_DVI_DDC;
ddc = DDC_DVI;
+ } else if (rdev->family == CHIP_RS300 ||
+ rdev->family == CHIP_RS400 ||
+ rdev->family == CHIP_RS480)
+ ddc_line = RADEON_GPIO_MONID;
+ else if (rdev->family >= CHIP_RV350) {
+ ddc_line = RADEON_GPIO_MONID;
+ ddc = DDC_MONID;
} else
ddc_line = RADEON_GPIO_CRT2_DDC;
break;
@@ -709,26 +724,42 @@
struct drm_device *dev = rdev->ddev;
struct radeon_i2c_bus_rec i2c;
+ /* actual hw pads
+ * r1xx/rs2xx/rs3xx
+ * 0x60, 0x64, 0x68, 0x6c, gpiopads, mm
+ * r200
+ * 0x60, 0x64, 0x68, mm
+ * r300/r350
+ * 0x60, 0x64, mm
+ * rv2xx/rv3xx/rs4xx
+ * 0x60, 0x64, 0x68, gpiopads, mm
+ */
+ /* 0x60 */
i2c = combios_setup_i2c_bus(rdev, DDC_DVI, 0, 0);
rdev->i2c_bus[0] = radeon_i2c_create(dev, &i2c, "DVI_DDC");
-
+ /* 0x64 */
i2c = combios_setup_i2c_bus(rdev, DDC_VGA, 0, 0);
rdev->i2c_bus[1] = radeon_i2c_create(dev, &i2c, "VGA_DDC");
+ /* mm i2c */
i2c.valid = true;
i2c.hw_capable = true;
i2c.mm_i2c = true;
i2c.i2c_id = 0xa0;
rdev->i2c_bus[2] = radeon_i2c_create(dev, &i2c, "MM_I2C");
- if (rdev->family == CHIP_RS300 ||
- rdev->family == CHIP_RS400 ||
- rdev->family == CHIP_RS480) {
+ if (rdev->family == CHIP_R300 ||
+ rdev->family == CHIP_R350) {
+ /* only 2 sw i2c pads */
+ } else if (rdev->family == CHIP_RS300 ||
+ rdev->family == CHIP_RS400 ||
+ rdev->family == CHIP_RS480) {
u16 offset;
u8 id, blocks, clk, data;
int i;
+ /* 0x68 */
i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
@@ -740,6 +771,7 @@
if (id == 136) {
clk = RBIOS8(offset + 3 + (i * 5) + 3);
data = RBIOS8(offset + 3 + (i * 5) + 4);
+ /* gpiopad */
i2c = combios_setup_i2c_bus(rdev, DDC_MONID,
(1 << clk), (1 << data));
rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "GPIOPAD_MASK");
@@ -747,14 +779,15 @@
}
}
}
-
- } else if (rdev->family >= CHIP_R300) {
+ } else if (rdev->family >= CHIP_R200) {
+ /* 0x68 */
i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
} else {
+ /* 0x68 */
i2c = combios_setup_i2c_bus(rdev, DDC_MONID, 0, 0);
rdev->i2c_bus[3] = radeon_i2c_create(dev, &i2c, "MONID");
-
+ /* 0x6c */
i2c = combios_setup_i2c_bus(rdev, DDC_CRT2, 0, 0);
rdev->i2c_bus[4] = radeon_i2c_create(dev, &i2c, "CRT2_DDC");
}
@@ -2504,6 +2537,12 @@
return true;
}
+static const char *thermal_controller_names[] = {
+ "NONE",
+ "lm63",
+ "adm1032",
+};
+
void radeon_combios_get_power_modes(struct radeon_device *rdev)
{
struct drm_device *dev = rdev->ddev;
@@ -2524,6 +2563,54 @@
return;
}
+ /* check for a thermal chip */
+ offset = combios_get_table_offset(dev, COMBIOS_OVERDRIVE_INFO_TABLE);
+ if (offset) {
+ u8 thermal_controller = 0, gpio = 0, i2c_addr = 0, clk_bit = 0, data_bit = 0;
+ struct radeon_i2c_bus_rec i2c_bus;
+
+ rev = RBIOS8(offset);
+
+ if (rev == 0) {
+ thermal_controller = RBIOS8(offset + 3);
+ gpio = RBIOS8(offset + 4) & 0x3f;
+ i2c_addr = RBIOS8(offset + 5);
+ } else if (rev == 1) {
+ thermal_controller = RBIOS8(offset + 4);
+ gpio = RBIOS8(offset + 5) & 0x3f;
+ i2c_addr = RBIOS8(offset + 6);
+ } else if (rev == 2) {
+ thermal_controller = RBIOS8(offset + 4);
+ gpio = RBIOS8(offset + 5) & 0x3f;
+ i2c_addr = RBIOS8(offset + 6);
+ clk_bit = RBIOS8(offset + 0xa);
+ data_bit = RBIOS8(offset + 0xb);
+ }
+ if ((thermal_controller > 0) && (thermal_controller < 3)) {
+ DRM_INFO("Possible %s thermal controller at 0x%02x\n",
+ thermal_controller_names[thermal_controller],
+ i2c_addr >> 1);
+ if (gpio == DDC_LCD) {
+ /* MM i2c */
+ i2c_bus.valid = true;
+ i2c_bus.hw_capable = true;
+ i2c_bus.mm_i2c = true;
+ i2c_bus.i2c_id = 0xa0;
+ } else if (gpio == DDC_GPIO)
+ i2c_bus = combios_setup_i2c_bus(rdev, gpio, 1 << clk_bit, 1 << data_bit);
+ else
+ i2c_bus = combios_setup_i2c_bus(rdev, gpio, 0, 0);
+ rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
+ if (rdev->pm.i2c_bus) {
+ struct i2c_board_info info = { };
+ const char *name = thermal_controller_names[thermal_controller];
+ info.addr = i2c_addr >> 1;
+ strlcpy(info.type, name, sizeof(info.type));
+ i2c_new_device(&rdev->pm.i2c_bus->adapter, &info);
+ }
+ }
+ }
+
if (rdev->flags & RADEON_IS_MOBILITY) {
offset = combios_get_table_offset(dev, COMBIOS_POWERPLAY_INFO_TABLE);
if (offset) {
diff --git a/drivers/gpu/drm/radeon/radeon_connectors.c b/drivers/gpu/drm/radeon/radeon_connectors.c
index 5f45fa1..ee1dccb 100644
--- a/drivers/gpu/drm/radeon/radeon_connectors.c
+++ b/drivers/gpu/drm/radeon/radeon_connectors.c
@@ -50,20 +50,21 @@
struct radeon_device *rdev = dev->dev_private;
struct radeon_connector *radeon_connector = to_radeon_connector(connector);
- if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
- radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
+ radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
- if ((connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
- (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
- if ((radeon_dp_getsinktype(radeon_connector) == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
- (radeon_dp_getsinktype(radeon_connector) == CONNECTOR_OBJECT_ID_eDP)) {
- if (radeon_dp_needs_link_train(radeon_connector)) {
- if (connector->encoder)
- dp_link_train(connector->encoder, connector);
- }
- }
+ /* powering up/down the eDP panel generates hpd events which
+ * can interfere with modesetting.
+ */
+ if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
+ return;
+
+ /* pre-r600 did not always have the hpd pins mapped accurately to connectors */
+ if (rdev->family >= CHIP_R600) {
+ if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
+ drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
+ else
+ drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
}
-
}
static void radeon_property_change_mode(struct drm_encoder *encoder)
@@ -1054,23 +1055,124 @@
int ret;
if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
+ struct drm_encoder *encoder;
+ struct drm_display_mode *mode;
+
if (!radeon_dig_connector->edp_on)
atombios_set_edp_panel_power(connector,
ATOM_TRANSMITTER_ACTION_POWER_ON);
- }
- ret = radeon_ddc_get_modes(radeon_connector);
- if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
+ ret = radeon_ddc_get_modes(radeon_connector);
if (!radeon_dig_connector->edp_on)
atombios_set_edp_panel_power(connector,
ATOM_TRANSMITTER_ACTION_POWER_OFF);
- }
+
+ if (ret > 0) {
+ encoder = radeon_best_single_encoder(connector);
+ if (encoder) {
+ radeon_fixup_lvds_native_mode(encoder, connector);
+ /* add scaled modes */
+ radeon_add_common_modes(encoder, connector);
+ }
+ return ret;
+ }
+
+ encoder = radeon_best_single_encoder(connector);
+ if (!encoder)
+ return 0;
+
+ /* we have no EDID modes */
+ mode = radeon_fp_native_mode(encoder);
+ if (mode) {
+ ret = 1;
+ drm_mode_probed_add(connector, mode);
+ /* add the width/height from vbios tables if available */
+ connector->display_info.width_mm = mode->width_mm;
+ connector->display_info.height_mm = mode->height_mm;
+ /* add scaled modes */
+ radeon_add_common_modes(encoder, connector);
+ }
+ } else
+ ret = radeon_ddc_get_modes(radeon_connector);
return ret;
}
+bool radeon_connector_encoder_is_dp_bridge(struct drm_connector *connector)
+{
+ struct drm_mode_object *obj;
+ struct drm_encoder *encoder;
+ struct radeon_encoder *radeon_encoder;
+ int i;
+ bool found = false;
+
+ for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
+ if (connector->encoder_ids[i] == 0)
+ break;
+
+ obj = drm_mode_object_find(connector->dev, connector->encoder_ids[i], DRM_MODE_OBJECT_ENCODER);
+ if (!obj)
+ continue;
+
+ encoder = obj_to_encoder(obj);
+ radeon_encoder = to_radeon_encoder(encoder);
+
+ switch (radeon_encoder->encoder_id) {
+ case ENCODER_OBJECT_ID_TRAVIS:
+ case ENCODER_OBJECT_ID_NUTMEG:
+ found = true;
+ break;
+ default:
+ break;
+ }
+ }
+
+ return found;
+}
+
+bool radeon_connector_encoder_is_hbr2(struct drm_connector *connector)
+{
+ struct drm_mode_object *obj;
+ struct drm_encoder *encoder;
+ struct radeon_encoder *radeon_encoder;
+ int i;
+ bool found = false;
+
+ for (i = 0; i < DRM_CONNECTOR_MAX_ENCODER; i++) {
+ if (connector->encoder_ids[i] == 0)
+ break;
+
+ obj = drm_mode_object_find(connector->dev, connector->encoder_ids[i], DRM_MODE_OBJECT_ENCODER);
+ if (!obj)
+ continue;
+
+ encoder = obj_to_encoder(obj);
+ radeon_encoder = to_radeon_encoder(encoder);
+ if (radeon_encoder->caps & ATOM_ENCODER_CAP_RECORD_HBR2)
+ found = true;
+ }
+
+ return found;
+}
+
+bool radeon_connector_is_dp12_capable(struct drm_connector *connector)
+{
+ struct drm_device *dev = connector->dev;
+ struct radeon_device *rdev = dev->dev_private;
+
+ if (ASIC_IS_DCE5(rdev) &&
+ (rdev->clock.dp_extclk >= 53900) &&
+ radeon_connector_encoder_is_hbr2(connector)) {
+ return true;
+ }
+
+ return false;
+}
+
static enum drm_connector_status
radeon_dp_detect(struct drm_connector *connector, bool force)
{
+ struct drm_device *dev = connector->dev;
+ struct radeon_device *rdev = dev->dev_private;
struct radeon_connector *radeon_connector = to_radeon_connector(connector);
enum drm_connector_status ret = connector_status_disconnected;
struct radeon_connector_atom_dig *radeon_dig_connector = radeon_connector->con_priv;
@@ -1081,6 +1183,15 @@
}
if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
+ struct drm_encoder *encoder = radeon_best_single_encoder(connector);
+ if (encoder) {
+ struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+ struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
+
+ /* check if panel is valid */
+ if (native_mode->hdisplay >= 320 && native_mode->vdisplay >= 240)
+ ret = connector_status_connected;
+ }
/* eDP is always DP */
radeon_dig_connector->dp_sink_type = CONNECTOR_OBJECT_ID_DISPLAYPORT;
if (!radeon_dig_connector->edp_on)
@@ -1093,12 +1204,18 @@
ATOM_TRANSMITTER_ACTION_POWER_OFF);
} else {
radeon_dig_connector->dp_sink_type = radeon_dp_getsinktype(radeon_connector);
- if (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) {
- if (radeon_dp_getdpcd(radeon_connector))
- ret = connector_status_connected;
+ if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd)) {
+ ret = connector_status_connected;
+ if (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT)
+ radeon_dp_getdpcd(radeon_connector);
} else {
- if (radeon_ddc_probe(radeon_connector))
- ret = connector_status_connected;
+ if (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) {
+ if (radeon_dp_getdpcd(radeon_connector))
+ ret = connector_status_connected;
+ } else {
+ if (radeon_ddc_probe(radeon_connector))
+ ret = connector_status_connected;
+ }
}
}
@@ -1114,11 +1231,38 @@
/* XXX check mode bandwidth */
- if ((radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
- (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
- return radeon_dp_mode_valid_helper(radeon_connector, mode);
- else
+ if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
+ struct drm_encoder *encoder = radeon_best_single_encoder(connector);
+
+ if ((mode->hdisplay < 320) || (mode->vdisplay < 240))
+ return MODE_PANEL;
+
+ if (encoder) {
+ struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+ struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
+
+ /* AVIVO hardware supports downscaling modes larger than the panel
+ * to the panel size, but I'm not sure this is desirable.
+ */
+ if ((mode->hdisplay > native_mode->hdisplay) ||
+ (mode->vdisplay > native_mode->vdisplay))
+ return MODE_PANEL;
+
+ /* if scaling is disabled, block non-native modes */
+ if (radeon_encoder->rmx_type == RMX_OFF) {
+ if ((mode->hdisplay != native_mode->hdisplay) ||
+ (mode->vdisplay != native_mode->vdisplay))
+ return MODE_PANEL;
+ }
+ }
return MODE_OK;
+ } else {
+ if ((radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
+ (radeon_dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
+ return radeon_dp_mode_valid_helper(connector, mode);
+ else
+ return MODE_OK;
+ }
}
struct drm_connector_helper_funcs radeon_dp_connector_helper_funcs = {
@@ -1151,8 +1295,11 @@
struct drm_connector *connector;
struct radeon_connector *radeon_connector;
struct radeon_connector_atom_dig *radeon_dig_connector;
+ struct drm_encoder *encoder;
+ struct radeon_encoder *radeon_encoder;
uint32_t subpixel_order = SubPixelNone;
bool shared_ddc = false;
+ bool is_dp_bridge = false;
if (connector_type == DRM_MODE_CONNECTOR_Unknown)
return;
@@ -1184,6 +1331,21 @@
}
}
+ /* check if it's a dp bridge */
+ list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
+ radeon_encoder = to_radeon_encoder(encoder);
+ if (radeon_encoder->devices & supported_device) {
+ switch (radeon_encoder->encoder_id) {
+ case ENCODER_OBJECT_ID_TRAVIS:
+ case ENCODER_OBJECT_ID_NUTMEG:
+ is_dp_bridge = true;
+ break;
+ default:
+ break;
+ }
+ }
+ }
+
radeon_connector = kzalloc(sizeof(struct radeon_connector), GFP_KERNEL);
if (!radeon_connector)
return;
@@ -1201,120 +1363,8 @@
if (!radeon_connector->router_bus)
DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n");
}
- switch (connector_type) {
- case DRM_MODE_CONNECTOR_VGA:
- drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type);
- drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs);
- if (i2c_bus->valid) {
- radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
- if (!radeon_connector->ddc_bus)
- DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
- }
- radeon_connector->dac_load_detect = true;
- drm_connector_attach_property(&radeon_connector->base,
- rdev->mode_info.load_detect_property,
- 1);
- /* no HPD on analog connectors */
- radeon_connector->hpd.hpd = RADEON_HPD_NONE;
- connector->polled = DRM_CONNECTOR_POLL_CONNECT;
- connector->interlace_allowed = true;
- connector->doublescan_allowed = true;
- break;
- case DRM_MODE_CONNECTOR_DVIA:
- drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type);
- drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs);
- if (i2c_bus->valid) {
- radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
- if (!radeon_connector->ddc_bus)
- DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
- }
- radeon_connector->dac_load_detect = true;
- drm_connector_attach_property(&radeon_connector->base,
- rdev->mode_info.load_detect_property,
- 1);
- /* no HPD on analog connectors */
- radeon_connector->hpd.hpd = RADEON_HPD_NONE;
- connector->interlace_allowed = true;
- connector->doublescan_allowed = true;
- break;
- case DRM_MODE_CONNECTOR_DVII:
- case DRM_MODE_CONNECTOR_DVID:
- radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL);
- if (!radeon_dig_connector)
- goto failed;
- radeon_dig_connector->igp_lane_info = igp_lane_info;
- radeon_connector->con_priv = radeon_dig_connector;
- drm_connector_init(dev, &radeon_connector->base, &radeon_dvi_connector_funcs, connector_type);
- drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs);
- if (i2c_bus->valid) {
- radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
- if (!radeon_connector->ddc_bus)
- DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
- }
- subpixel_order = SubPixelHorizontalRGB;
- drm_connector_attach_property(&radeon_connector->base,
- rdev->mode_info.coherent_mode_property,
- 1);
- if (ASIC_IS_AVIVO(rdev)) {
- drm_connector_attach_property(&radeon_connector->base,
- rdev->mode_info.underscan_property,
- UNDERSCAN_OFF);
- drm_connector_attach_property(&radeon_connector->base,
- rdev->mode_info.underscan_hborder_property,
- 0);
- drm_connector_attach_property(&radeon_connector->base,
- rdev->mode_info.underscan_vborder_property,
- 0);
- }
- if (connector_type == DRM_MODE_CONNECTOR_DVII) {
- radeon_connector->dac_load_detect = true;
- drm_connector_attach_property(&radeon_connector->base,
- rdev->mode_info.load_detect_property,
- 1);
- }
- connector->interlace_allowed = true;
- if (connector_type == DRM_MODE_CONNECTOR_DVII)
- connector->doublescan_allowed = true;
- else
- connector->doublescan_allowed = false;
- break;
- case DRM_MODE_CONNECTOR_HDMIA:
- case DRM_MODE_CONNECTOR_HDMIB:
- radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL);
- if (!radeon_dig_connector)
- goto failed;
- radeon_dig_connector->igp_lane_info = igp_lane_info;
- radeon_connector->con_priv = radeon_dig_connector;
- drm_connector_init(dev, &radeon_connector->base, &radeon_dvi_connector_funcs, connector_type);
- drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs);
- if (i2c_bus->valid) {
- radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
- if (!radeon_connector->ddc_bus)
- DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
- }
- drm_connector_attach_property(&radeon_connector->base,
- rdev->mode_info.coherent_mode_property,
- 1);
- if (ASIC_IS_AVIVO(rdev)) {
- drm_connector_attach_property(&radeon_connector->base,
- rdev->mode_info.underscan_property,
- UNDERSCAN_OFF);
- drm_connector_attach_property(&radeon_connector->base,
- rdev->mode_info.underscan_hborder_property,
- 0);
- drm_connector_attach_property(&radeon_connector->base,
- rdev->mode_info.underscan_vborder_property,
- 0);
- }
- subpixel_order = SubPixelHorizontalRGB;
- connector->interlace_allowed = true;
- if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
- connector->doublescan_allowed = true;
- else
- connector->doublescan_allowed = false;
- break;
- case DRM_MODE_CONNECTOR_DisplayPort:
- case DRM_MODE_CONNECTOR_eDP:
+
+ if (is_dp_bridge) {
radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL);
if (!radeon_dig_connector)
goto failed;
@@ -1334,11 +1384,18 @@
if (!radeon_connector->ddc_bus)
DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
}
- subpixel_order = SubPixelHorizontalRGB;
- drm_connector_attach_property(&radeon_connector->base,
- rdev->mode_info.coherent_mode_property,
- 1);
- if (ASIC_IS_AVIVO(rdev)) {
+ switch (connector_type) {
+ case DRM_MODE_CONNECTOR_VGA:
+ case DRM_MODE_CONNECTOR_DVIA:
+ default:
+ connector->interlace_allowed = true;
+ connector->doublescan_allowed = true;
+ break;
+ case DRM_MODE_CONNECTOR_DVII:
+ case DRM_MODE_CONNECTOR_DVID:
+ case DRM_MODE_CONNECTOR_HDMIA:
+ case DRM_MODE_CONNECTOR_HDMIB:
+ case DRM_MODE_CONNECTOR_DisplayPort:
drm_connector_attach_property(&radeon_connector->base,
rdev->mode_info.underscan_property,
UNDERSCAN_OFF);
@@ -1348,48 +1405,234 @@
drm_connector_attach_property(&radeon_connector->base,
rdev->mode_info.underscan_vborder_property,
0);
+ subpixel_order = SubPixelHorizontalRGB;
+ connector->interlace_allowed = true;
+ if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
+ connector->doublescan_allowed = true;
+ else
+ connector->doublescan_allowed = false;
+ break;
+ case DRM_MODE_CONNECTOR_LVDS:
+ case DRM_MODE_CONNECTOR_eDP:
+ drm_connector_attach_property(&radeon_connector->base,
+ dev->mode_config.scaling_mode_property,
+ DRM_MODE_SCALE_FULLSCREEN);
+ subpixel_order = SubPixelHorizontalRGB;
+ connector->interlace_allowed = false;
+ connector->doublescan_allowed = false;
+ break;
}
- connector->interlace_allowed = true;
- /* in theory with a DP to VGA converter... */
- connector->doublescan_allowed = false;
- break;
- case DRM_MODE_CONNECTOR_SVIDEO:
- case DRM_MODE_CONNECTOR_Composite:
- case DRM_MODE_CONNECTOR_9PinDIN:
- drm_connector_init(dev, &radeon_connector->base, &radeon_tv_connector_funcs, connector_type);
- drm_connector_helper_add(&radeon_connector->base, &radeon_tv_connector_helper_funcs);
- radeon_connector->dac_load_detect = true;
- drm_connector_attach_property(&radeon_connector->base,
- rdev->mode_info.load_detect_property,
- 1);
- drm_connector_attach_property(&radeon_connector->base,
- rdev->mode_info.tv_std_property,
- radeon_atombios_get_tv_info(rdev));
- /* no HPD on analog connectors */
- radeon_connector->hpd.hpd = RADEON_HPD_NONE;
- connector->interlace_allowed = false;
- connector->doublescan_allowed = false;
- break;
- case DRM_MODE_CONNECTOR_LVDS:
- radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL);
- if (!radeon_dig_connector)
- goto failed;
- radeon_dig_connector->igp_lane_info = igp_lane_info;
- radeon_connector->con_priv = radeon_dig_connector;
- drm_connector_init(dev, &radeon_connector->base, &radeon_lvds_connector_funcs, connector_type);
- drm_connector_helper_add(&radeon_connector->base, &radeon_lvds_connector_helper_funcs);
- if (i2c_bus->valid) {
- radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
- if (!radeon_connector->ddc_bus)
- DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
+ } else {
+ switch (connector_type) {
+ case DRM_MODE_CONNECTOR_VGA:
+ drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type);
+ drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs);
+ if (i2c_bus->valid) {
+ radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
+ if (!radeon_connector->ddc_bus)
+ DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
+ }
+ radeon_connector->dac_load_detect = true;
+ drm_connector_attach_property(&radeon_connector->base,
+ rdev->mode_info.load_detect_property,
+ 1);
+ /* no HPD on analog connectors */
+ radeon_connector->hpd.hpd = RADEON_HPD_NONE;
+ connector->polled = DRM_CONNECTOR_POLL_CONNECT;
+ connector->interlace_allowed = true;
+ connector->doublescan_allowed = true;
+ break;
+ case DRM_MODE_CONNECTOR_DVIA:
+ drm_connector_init(dev, &radeon_connector->base, &radeon_vga_connector_funcs, connector_type);
+ drm_connector_helper_add(&radeon_connector->base, &radeon_vga_connector_helper_funcs);
+ if (i2c_bus->valid) {
+ radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
+ if (!radeon_connector->ddc_bus)
+ DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
+ }
+ radeon_connector->dac_load_detect = true;
+ drm_connector_attach_property(&radeon_connector->base,
+ rdev->mode_info.load_detect_property,
+ 1);
+ /* no HPD on analog connectors */
+ radeon_connector->hpd.hpd = RADEON_HPD_NONE;
+ connector->interlace_allowed = true;
+ connector->doublescan_allowed = true;
+ break;
+ case DRM_MODE_CONNECTOR_DVII:
+ case DRM_MODE_CONNECTOR_DVID:
+ radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL);
+ if (!radeon_dig_connector)
+ goto failed;
+ radeon_dig_connector->igp_lane_info = igp_lane_info;
+ radeon_connector->con_priv = radeon_dig_connector;
+ drm_connector_init(dev, &radeon_connector->base, &radeon_dvi_connector_funcs, connector_type);
+ drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs);
+ if (i2c_bus->valid) {
+ radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
+ if (!radeon_connector->ddc_bus)
+ DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
+ }
+ subpixel_order = SubPixelHorizontalRGB;
+ drm_connector_attach_property(&radeon_connector->base,
+ rdev->mode_info.coherent_mode_property,
+ 1);
+ if (ASIC_IS_AVIVO(rdev)) {
+ drm_connector_attach_property(&radeon_connector->base,
+ rdev->mode_info.underscan_property,
+ UNDERSCAN_OFF);
+ drm_connector_attach_property(&radeon_connector->base,
+ rdev->mode_info.underscan_hborder_property,
+ 0);
+ drm_connector_attach_property(&radeon_connector->base,
+ rdev->mode_info.underscan_vborder_property,
+ 0);
+ }
+ if (connector_type == DRM_MODE_CONNECTOR_DVII) {
+ radeon_connector->dac_load_detect = true;
+ drm_connector_attach_property(&radeon_connector->base,
+ rdev->mode_info.load_detect_property,
+ 1);
+ }
+ connector->interlace_allowed = true;
+ if (connector_type == DRM_MODE_CONNECTOR_DVII)
+ connector->doublescan_allowed = true;
+ else
+ connector->doublescan_allowed = false;
+ break;
+ case DRM_MODE_CONNECTOR_HDMIA:
+ case DRM_MODE_CONNECTOR_HDMIB:
+ radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL);
+ if (!radeon_dig_connector)
+ goto failed;
+ radeon_dig_connector->igp_lane_info = igp_lane_info;
+ radeon_connector->con_priv = radeon_dig_connector;
+ drm_connector_init(dev, &radeon_connector->base, &radeon_dvi_connector_funcs, connector_type);
+ drm_connector_helper_add(&radeon_connector->base, &radeon_dvi_connector_helper_funcs);
+ if (i2c_bus->valid) {
+ radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
+ if (!radeon_connector->ddc_bus)
+ DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
+ }
+ drm_connector_attach_property(&radeon_connector->base,
+ rdev->mode_info.coherent_mode_property,
+ 1);
+ if (ASIC_IS_AVIVO(rdev)) {
+ drm_connector_attach_property(&radeon_connector->base,
+ rdev->mode_info.underscan_property,
+ UNDERSCAN_OFF);
+ drm_connector_attach_property(&radeon_connector->base,
+ rdev->mode_info.underscan_hborder_property,
+ 0);
+ drm_connector_attach_property(&radeon_connector->base,
+ rdev->mode_info.underscan_vborder_property,
+ 0);
+ }
+ subpixel_order = SubPixelHorizontalRGB;
+ connector->interlace_allowed = true;
+ if (connector_type == DRM_MODE_CONNECTOR_HDMIB)
+ connector->doublescan_allowed = true;
+ else
+ connector->doublescan_allowed = false;
+ break;
+ case DRM_MODE_CONNECTOR_DisplayPort:
+ radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL);
+ if (!radeon_dig_connector)
+ goto failed;
+ radeon_dig_connector->igp_lane_info = igp_lane_info;
+ radeon_connector->con_priv = radeon_dig_connector;
+ drm_connector_init(dev, &radeon_connector->base, &radeon_dp_connector_funcs, connector_type);
+ drm_connector_helper_add(&radeon_connector->base, &radeon_dp_connector_helper_funcs);
+ if (i2c_bus->valid) {
+ /* add DP i2c bus */
+ radeon_dig_connector->dp_i2c_bus = radeon_i2c_create_dp(dev, i2c_bus, "DP-auxch");
+ if (!radeon_dig_connector->dp_i2c_bus)
+ DRM_ERROR("DP: Failed to assign dp ddc bus! Check dmesg for i2c errors.\n");
+ radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
+ if (!radeon_connector->ddc_bus)
+ DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
+ }
+ subpixel_order = SubPixelHorizontalRGB;
+ drm_connector_attach_property(&radeon_connector->base,
+ rdev->mode_info.coherent_mode_property,
+ 1);
+ if (ASIC_IS_AVIVO(rdev)) {
+ drm_connector_attach_property(&radeon_connector->base,
+ rdev->mode_info.underscan_property,
+ UNDERSCAN_OFF);
+ drm_connector_attach_property(&radeon_connector->base,
+ rdev->mode_info.underscan_hborder_property,
+ 0);
+ drm_connector_attach_property(&radeon_connector->base,
+ rdev->mode_info.underscan_vborder_property,
+ 0);
+ }
+ connector->interlace_allowed = true;
+ /* in theory with a DP to VGA converter... */
+ connector->doublescan_allowed = false;
+ break;
+ case DRM_MODE_CONNECTOR_eDP:
+ radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL);
+ if (!radeon_dig_connector)
+ goto failed;
+ radeon_dig_connector->igp_lane_info = igp_lane_info;
+ radeon_connector->con_priv = radeon_dig_connector;
+ drm_connector_init(dev, &radeon_connector->base, &radeon_dp_connector_funcs, connector_type);
+ drm_connector_helper_add(&radeon_connector->base, &radeon_dp_connector_helper_funcs);
+ if (i2c_bus->valid) {
+ /* add DP i2c bus */
+ radeon_dig_connector->dp_i2c_bus = radeon_i2c_create_dp(dev, i2c_bus, "eDP-auxch");
+ if (!radeon_dig_connector->dp_i2c_bus)
+ DRM_ERROR("DP: Failed to assign dp ddc bus! Check dmesg for i2c errors.\n");
+ radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
+ if (!radeon_connector->ddc_bus)
+ DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
+ }
+ drm_connector_attach_property(&radeon_connector->base,
+ dev->mode_config.scaling_mode_property,
+ DRM_MODE_SCALE_FULLSCREEN);
+ subpixel_order = SubPixelHorizontalRGB;
+ connector->interlace_allowed = false;
+ connector->doublescan_allowed = false;
+ break;
+ case DRM_MODE_CONNECTOR_SVIDEO:
+ case DRM_MODE_CONNECTOR_Composite:
+ case DRM_MODE_CONNECTOR_9PinDIN:
+ drm_connector_init(dev, &radeon_connector->base, &radeon_tv_connector_funcs, connector_type);
+ drm_connector_helper_add(&radeon_connector->base, &radeon_tv_connector_helper_funcs);
+ radeon_connector->dac_load_detect = true;
+ drm_connector_attach_property(&radeon_connector->base,
+ rdev->mode_info.load_detect_property,
+ 1);
+ drm_connector_attach_property(&radeon_connector->base,
+ rdev->mode_info.tv_std_property,
+ radeon_atombios_get_tv_info(rdev));
+ /* no HPD on analog connectors */
+ radeon_connector->hpd.hpd = RADEON_HPD_NONE;
+ connector->interlace_allowed = false;
+ connector->doublescan_allowed = false;
+ break;
+ case DRM_MODE_CONNECTOR_LVDS:
+ radeon_dig_connector = kzalloc(sizeof(struct radeon_connector_atom_dig), GFP_KERNEL);
+ if (!radeon_dig_connector)
+ goto failed;
+ radeon_dig_connector->igp_lane_info = igp_lane_info;
+ radeon_connector->con_priv = radeon_dig_connector;
+ drm_connector_init(dev, &radeon_connector->base, &radeon_lvds_connector_funcs, connector_type);
+ drm_connector_helper_add(&radeon_connector->base, &radeon_lvds_connector_helper_funcs);
+ if (i2c_bus->valid) {
+ radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
+ if (!radeon_connector->ddc_bus)
+ DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
+ }
+ drm_connector_attach_property(&radeon_connector->base,
+ dev->mode_config.scaling_mode_property,
+ DRM_MODE_SCALE_FULLSCREEN);
+ subpixel_order = SubPixelHorizontalRGB;
+ connector->interlace_allowed = false;
+ connector->doublescan_allowed = false;
+ break;
}
- drm_connector_attach_property(&radeon_connector->base,
- dev->mode_config.scaling_mode_property,
- DRM_MODE_SCALE_FULLSCREEN);
- subpixel_order = SubPixelHorizontalRGB;
- connector->interlace_allowed = false;
- connector->doublescan_allowed = false;
- break;
}
if (radeon_connector->hpd.hpd == RADEON_HPD_NONE) {
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index 890217e..5b61364 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -923,6 +923,9 @@
radeon_fbdev_set_suspend(rdev, 0);
console_unlock();
+ /* init dig PHYs */
+ if (rdev->is_atom_bios)
+ radeon_atom_encoder_init(rdev);
/* reset hpd state */
radeon_hpd_init(rdev);
/* blat the mode back in */
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index bdbab5c..ae247ee 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -1087,8 +1087,9 @@
*frac_fb_div_p = best_frac_feedback_div;
*ref_div_p = best_ref_div;
*post_div_p = best_post_div;
- DRM_DEBUG_KMS("%d %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
- freq, best_freq / 1000, best_feedback_div, best_frac_feedback_div,
+ DRM_DEBUG_KMS("%lld %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
+ (long long)freq,
+ best_freq / 1000, best_feedback_div, best_frac_feedback_div,
best_ref_div, best_post_div);
}
@@ -1344,6 +1345,11 @@
if (!ret) {
return ret;
}
+
+ /* init dig PHYs */
+ if (rdev->is_atom_bios)
+ radeon_atom_encoder_init(rdev);
+
/* initialize hpd */
radeon_hpd_init(rdev);
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index 63d2de8..1d33060 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -50,9 +50,10 @@
* 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs
* 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query
* 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query
+ * 2.10.0 - fusion 2D tiling
*/
#define KMS_DRIVER_MAJOR 2
-#define KMS_DRIVER_MINOR 9
+#define KMS_DRIVER_MINOR 10
#define KMS_DRIVER_PATCHLEVEL 0
int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
int radeon_driver_unload_kms(struct drm_device *dev);
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c
index b427488..1b55755 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -229,6 +229,22 @@
return NULL;
}
+static struct drm_connector *
+radeon_get_connector_for_encoder_init(struct drm_encoder *encoder)
+{
+ struct drm_device *dev = encoder->dev;
+ struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+ struct drm_connector *connector;
+ struct radeon_connector *radeon_connector;
+
+ list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
+ radeon_connector = to_radeon_connector(connector);
+ if (radeon_encoder->devices & radeon_connector->devices)
+ return connector;
+ }
+ return NULL;
+}
+
struct drm_encoder *radeon_atom_get_external_encoder(struct drm_encoder *encoder)
{
struct drm_device *dev = encoder->dev;
@@ -250,6 +266,25 @@
return NULL;
}
+bool radeon_encoder_is_dp_bridge(struct drm_encoder *encoder)
+{
+ struct drm_encoder *other_encoder = radeon_atom_get_external_encoder(encoder);
+
+ if (other_encoder) {
+ struct radeon_encoder *radeon_encoder = to_radeon_encoder(other_encoder);
+
+ switch (radeon_encoder->encoder_id) {
+ case ENCODER_OBJECT_ID_TRAVIS:
+ case ENCODER_OBJECT_ID_NUTMEG:
+ return true;
+ default:
+ return false;
+ }
+ }
+
+ return false;
+}
+
void radeon_panel_mode_fixup(struct drm_encoder *encoder,
struct drm_display_mode *adjusted_mode)
{
@@ -621,6 +656,10 @@
struct radeon_connector *radeon_connector;
struct radeon_connector_atom_dig *dig_connector;
+ /* dp bridges are always DP */
+ if (radeon_encoder_is_dp_bridge(encoder))
+ return ATOM_ENCODER_MODE_DP;
+
connector = radeon_get_connector_for_encoder(encoder);
if (!connector) {
switch (radeon_encoder->encoder_id) {
@@ -668,7 +707,6 @@
return ATOM_ENCODER_MODE_LVDS;
break;
case DRM_MODE_CONNECTOR_DisplayPort:
- case DRM_MODE_CONNECTOR_eDP:
dig_connector = radeon_connector->con_priv;
if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
(dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
@@ -682,6 +720,8 @@
} else
return ATOM_ENCODER_MODE_DVI;
break;
+ case DRM_MODE_CONNECTOR_eDP:
+ return ATOM_ENCODER_MODE_DP;
case DRM_MODE_CONNECTOR_DVIA:
case DRM_MODE_CONNECTOR_VGA:
return ATOM_ENCODER_MODE_CRT;
@@ -747,7 +787,7 @@
};
void
-atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
+atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
{
struct drm_device *dev = encoder->dev;
struct radeon_device *rdev = dev->dev_private;
@@ -760,6 +800,7 @@
int dp_clock = 0;
int dp_lane_count = 0;
int hpd_id = RADEON_HPD_NONE;
+ int bpc = 8;
if (connector) {
struct radeon_connector *radeon_connector = to_radeon_connector(connector);
@@ -769,6 +810,7 @@
dp_clock = dig_connector->dp_clock;
dp_lane_count = dig_connector->dp_lane_count;
hpd_id = radeon_connector->hpd.hpd;
+ bpc = connector->display_info.bpc;
}
/* no dig encoder assigned */
@@ -791,7 +833,10 @@
args.v1.ucAction = action;
args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
- args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
+ if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
+ args.v3.ucPanelMode = panel_mode;
+ else
+ args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) ||
(args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP_MST))
@@ -810,7 +855,27 @@
args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
}
args.v4.acConfig.ucDigSel = dig->dig_encoder;
- args.v4.ucBitPerColor = PANEL_8BIT_PER_COLOR;
+ switch (bpc) {
+ case 0:
+ args.v4.ucBitPerColor = PANEL_BPC_UNDEFINE;
+ break;
+ case 6:
+ args.v4.ucBitPerColor = PANEL_6BIT_PER_COLOR;
+ break;
+ case 8:
+ default:
+ args.v4.ucBitPerColor = PANEL_8BIT_PER_COLOR;
+ break;
+ case 10:
+ args.v4.ucBitPerColor = PANEL_10BIT_PER_COLOR;
+ break;
+ case 12:
+ args.v4.ucBitPerColor = PANEL_12BIT_PER_COLOR;
+ break;
+ case 16:
+ args.v4.ucBitPerColor = PANEL_16BIT_PER_COLOR;
+ break;
+ }
if (hpd_id == RADEON_HPD_NONE)
args.v4.ucHPD_ID = 0;
else
@@ -819,7 +884,27 @@
if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) && (dp_clock == 270000))
args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
args.v3.acConfig.ucDigSel = dig->dig_encoder;
- args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
+ switch (bpc) {
+ case 0:
+ args.v3.ucBitPerColor = PANEL_BPC_UNDEFINE;
+ break;
+ case 6:
+ args.v3.ucBitPerColor = PANEL_6BIT_PER_COLOR;
+ break;
+ case 8:
+ default:
+ args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
+ break;
+ case 10:
+ args.v3.ucBitPerColor = PANEL_10BIT_PER_COLOR;
+ break;
+ case 12:
+ args.v3.ucBitPerColor = PANEL_12BIT_PER_COLOR;
+ break;
+ case 16:
+ args.v3.ucBitPerColor = PANEL_16BIT_PER_COLOR;
+ break;
+ }
} else {
if ((args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) && (dp_clock == 270000))
args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
@@ -859,7 +944,7 @@
struct radeon_device *rdev = dev->dev_private;
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
- struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
+ struct drm_connector *connector;
union dig_transmitter_control args;
int index = 0;
uint8_t frev, crev;
@@ -870,6 +955,11 @@
int connector_object_id = 0;
int igp_lane_info = 0;
+ if (action == ATOM_TRANSMITTER_ACTION_INIT)
+ connector = radeon_get_connector_for_encoder_init(encoder);
+ else
+ connector = radeon_get_connector_for_encoder(encoder);
+
if (connector) {
struct radeon_connector *radeon_connector = to_radeon_connector(connector);
struct radeon_connector_atom_dig *dig_connector =
@@ -931,10 +1021,10 @@
else
args.v3.ucLaneNum = 4;
- if (dig->linkb) {
+ if (dig->linkb)
args.v3.acConfig.ucLinkSel = 1;
+ if (dig->dig_encoder & 1)
args.v3.acConfig.ucEncoderSel = 1;
- }
/* Select the PLL for the PHY
* DP PHY should be clocked from external src if there is
@@ -946,11 +1036,16 @@
}
if (ASIC_IS_DCE5(rdev)) {
- if (is_dp && rdev->clock.dp_extclk)
- args.v4.acConfig.ucRefClkSource = 3; /* external src */
- else
+ /* On DCE5 DCPLL usually generates the DP ref clock */
+ if (is_dp) {
+ if (rdev->clock.dp_extclk)
+ args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
+ else
+ args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
+ } else
args.v4.acConfig.ucRefClkSource = pll_id;
} else {
+ /* On DCE4, if there is an external clock, it generates the DP ref clock */
if (is_dp && rdev->clock.dp_extclk)
args.v3.acConfig.ucRefClkSource = 2; /* external src */
else
@@ -1047,7 +1142,7 @@
atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
}
-void
+bool
atombios_set_edp_panel_power(struct drm_connector *connector, int action)
{
struct radeon_connector *radeon_connector = to_radeon_connector(connector);
@@ -1058,23 +1153,37 @@
uint8_t frev, crev;
if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
- return;
+ goto done;
if (!ASIC_IS_DCE4(rdev))
- return;
+ goto done;
if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
(action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
- return;
+ goto done;
if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
- return;
+ goto done;
memset(&args, 0, sizeof(args));
args.v1.ucAction = action;
atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
+
+ /* wait for the panel to power up */
+ if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
+ int i;
+
+ for (i = 0; i < 300; i++) {
+ if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
+ return true;
+ mdelay(1);
+ }
+ return false;
+ }
+done:
+ return true;
}
union external_encoder_control {
@@ -1092,13 +1201,19 @@
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
union external_encoder_control args;
- struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
+ struct drm_connector *connector;
int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
u8 frev, crev;
int dp_clock = 0;
int dp_lane_count = 0;
int connector_object_id = 0;
u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
+ int bpc = 8;
+
+ if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
+ connector = radeon_get_connector_for_encoder_init(encoder);
+ else
+ connector = radeon_get_connector_for_encoder(encoder);
if (connector) {
struct radeon_connector *radeon_connector = to_radeon_connector(connector);
@@ -1109,6 +1224,7 @@
dp_lane_count = dig_connector->dp_lane_count;
connector_object_id =
(radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
+ bpc = connector->display_info.bpc;
}
memset(&args, 0, sizeof(args));
@@ -1166,7 +1282,27 @@
args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
break;
}
- args.v3.sExtEncoder.ucBitPerColor = PANEL_8BIT_PER_COLOR;
+ switch (bpc) {
+ case 0:
+ args.v3.sExtEncoder.ucBitPerColor = PANEL_BPC_UNDEFINE;
+ break;
+ case 6:
+ args.v3.sExtEncoder.ucBitPerColor = PANEL_6BIT_PER_COLOR;
+ break;
+ case 8:
+ default:
+ args.v3.sExtEncoder.ucBitPerColor = PANEL_8BIT_PER_COLOR;
+ break;
+ case 10:
+ args.v3.sExtEncoder.ucBitPerColor = PANEL_10BIT_PER_COLOR;
+ break;
+ case 12:
+ args.v3.sExtEncoder.ucBitPerColor = PANEL_12BIT_PER_COLOR;
+ break;
+ case 16:
+ args.v3.sExtEncoder.ucBitPerColor = PANEL_16BIT_PER_COLOR;
+ break;
+ }
break;
default:
DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
@@ -1307,9 +1443,11 @@
ATOM_TRANSMITTER_ACTION_POWER_ON);
radeon_dig_connector->edp_on = true;
}
- dp_link_train(encoder, connector);
if (ASIC_IS_DCE4(rdev))
- atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON);
+ atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
+ radeon_dp_link_train(encoder, connector);
+ if (ASIC_IS_DCE4(rdev))
+ atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
}
if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
@@ -1322,7 +1460,7 @@
struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
if (ASIC_IS_DCE4(rdev))
- atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF);
+ atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
if (connector &&
(connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
struct radeon_connector *radeon_connector = to_radeon_connector(connector);
@@ -1601,12 +1739,9 @@
/* DCE4/5 */
if (ASIC_IS_DCE4(rdev)) {
dig = radeon_encoder->enc_priv;
- if (ASIC_IS_DCE41(rdev)) {
- if (dig->linkb)
- return 1;
- else
- return 0;
- } else {
+ if (ASIC_IS_DCE41(rdev))
+ return radeon_crtc->crtc_id;
+ else {
switch (radeon_encoder->encoder_id) {
case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
if (dig->linkb)
@@ -1662,6 +1797,34 @@
return 1;
}
+/* This only needs to be called once at startup */
+void
+radeon_atom_encoder_init(struct radeon_device *rdev)
+{
+ struct drm_device *dev = rdev->ddev;
+ struct drm_encoder *encoder;
+
+ list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
+ struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
+ struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
+
+ switch (radeon_encoder->encoder_id) {
+ case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
+ case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
+ case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
+ case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
+ atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
+ break;
+ default:
+ break;
+ }
+
+ if (ext_encoder && ASIC_IS_DCE41(rdev))
+ atombios_external_encoder_setup(encoder, ext_encoder,
+ EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
+ }
+}
+
static void
radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
struct drm_display_mode *mode,
@@ -1696,19 +1859,17 @@
/* disable the transmitter */
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
/* setup and enable the encoder */
- atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP);
+ atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
- /* init and enable the transmitter */
- atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
+ /* enable the transmitter */
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
} else {
/* disable the encoder and transmitter */
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
- atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
+ atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
/* setup and enable the encoder and transmitter */
- atombios_dig_encoder_setup(encoder, ATOM_ENABLE);
- atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
+ atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
}
@@ -1733,12 +1894,10 @@
}
if (ext_encoder) {
- if (ASIC_IS_DCE41(rdev)) {
- atombios_external_encoder_setup(encoder, ext_encoder,
- EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
+ if (ASIC_IS_DCE41(rdev))
atombios_external_encoder_setup(encoder, ext_encoder,
EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
- } else
+ else
atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
}
@@ -1845,8 +2004,9 @@
struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
- if (radeon_encoder->active_device &
- (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) {
+ if ((radeon_encoder->active_device &
+ (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
+ radeon_encoder_is_dp_bridge(encoder)) {
struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
if (dig)
dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
@@ -1855,11 +2015,17 @@
radeon_atom_output_lock(encoder, true);
radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
- /* select the clock/data port if it uses a router */
if (connector) {
struct radeon_connector *radeon_connector = to_radeon_connector(connector);
+
+ /* select the clock/data port if it uses a router */
if (radeon_connector->router.cd_valid)
radeon_router_select_cd_port(radeon_connector);
+
+ /* turn eDP panel on for mode set */
+ if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
+ atombios_set_edp_panel_power(connector,
+ ATOM_TRANSMITTER_ACTION_POWER_ON);
}
/* this is needed for the pll/ss setup to work correctly in some cases */
@@ -1914,7 +2080,7 @@
else {
/* disable the encoder and transmitter */
atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
- atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
+ atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
}
break;
case ENCODER_OBJECT_ID_INTERNAL_DDI:
@@ -2116,8 +2282,6 @@
} else {
drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
- if (ASIC_IS_AVIVO(rdev))
- radeon_encoder->underscan_type = UNDERSCAN_AUTO;
}
drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
break;
@@ -2150,8 +2314,6 @@
} else {
drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
- if (ASIC_IS_AVIVO(rdev))
- radeon_encoder->underscan_type = UNDERSCAN_AUTO;
}
drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
break;
diff --git a/drivers/gpu/drm/radeon/radeon_i2c.c b/drivers/gpu/drm/radeon/radeon_i2c.c
index 983cbac..781196d 100644
--- a/drivers/gpu/drm/radeon/radeon_i2c.c
+++ b/drivers/gpu/drm/radeon/radeon_i2c.c
@@ -888,6 +888,7 @@
i2c->rec = *rec;
i2c->adapter.owner = THIS_MODULE;
+ i2c->adapter.class = I2C_CLASS_DDC;
i2c->dev = dev;
i2c_set_adapdata(&i2c->adapter, i2c);
if (rec->mm_i2c ||
@@ -947,6 +948,7 @@
i2c->rec = *rec;
i2c->adapter.owner = THIS_MODULE;
+ i2c->adapter.class = I2C_CLASS_DDC;
i2c->dev = dev;
snprintf(i2c->adapter.name, sizeof(i2c->adapter.name),
"Radeon aux bus %s", name);
diff --git a/drivers/gpu/drm/radeon/radeon_mode.h b/drivers/gpu/drm/radeon/radeon_mode.h
index 9c57538..977a341 100644
--- a/drivers/gpu/drm/radeon/radeon_mode.h
+++ b/drivers/gpu/drm/radeon/radeon_mode.h
@@ -464,22 +464,27 @@
extern struct drm_connector *
radeon_get_connector_for_encoder(struct drm_encoder *encoder);
+extern bool radeon_encoder_is_dp_bridge(struct drm_encoder *encoder);
+extern bool radeon_connector_encoder_is_dp_bridge(struct drm_connector *connector);
+extern bool radeon_connector_encoder_is_hbr2(struct drm_connector *connector);
+extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector);
+
extern void radeon_connector_hotplug(struct drm_connector *connector);
-extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector);
-extern int radeon_dp_mode_valid_helper(struct radeon_connector *radeon_connector,
+extern int radeon_dp_mode_valid_helper(struct drm_connector *connector,
struct drm_display_mode *mode);
extern void radeon_dp_set_link_config(struct drm_connector *connector,
struct drm_display_mode *mode);
-extern void dp_link_train(struct drm_encoder *encoder,
- struct drm_connector *connector);
+extern void radeon_dp_link_train(struct drm_encoder *encoder,
+ struct drm_connector *connector);
extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector);
extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector);
-extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action);
+extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode);
+extern void radeon_atom_encoder_init(struct radeon_device *rdev);
extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
int action, uint8_t lane_num,
uint8_t lane_set);
extern int radeon_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
- uint8_t write_byte, uint8_t *read_byte);
+ u8 write_byte, u8 *read_byte);
extern void radeon_i2c_init(struct radeon_device *rdev);
extern void radeon_i2c_fini(struct radeon_device *rdev);
@@ -545,7 +550,7 @@
extern void atombios_dvo_setup(struct drm_encoder *encoder, int action);
extern void atombios_digital_setup(struct drm_encoder *encoder, int action);
extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
-extern void atombios_set_edp_panel_power(struct drm_connector *connector, int action);
+extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action);
extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);
extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
diff --git a/drivers/gpu/drm/ttm/ttm_page_alloc.c b/drivers/gpu/drm/ttm/ttm_page_alloc.c
index 9d9d929..d948575 100644
--- a/drivers/gpu/drm/ttm/ttm_page_alloc.c
+++ b/drivers/gpu/drm/ttm/ttm_page_alloc.c
@@ -395,12 +395,14 @@
/**
* Callback for mm to request pool to reduce number of page held.
*/
-static int ttm_pool_mm_shrink(struct shrinker *shrink, int shrink_pages, gfp_t gfp_mask)
+static int ttm_pool_mm_shrink(struct shrinker *shrink,
+ struct shrink_control *sc)
{
static atomic_t start_pool = ATOMIC_INIT(0);
unsigned i;
unsigned pool_offset = atomic_add_return(1, &start_pool);
struct ttm_page_pool *pool;
+ int shrink_pages = sc->nr_to_scan;
pool_offset = pool_offset % NUM_POOLS;
/* select start pool in round robin fashion */
diff --git a/drivers/gpu/vga/vga_switcheroo.c b/drivers/gpu/vga/vga_switcheroo.c
index 498b284..58434e8 100644
--- a/drivers/gpu/vga/vga_switcheroo.c
+++ b/drivers/gpu/vga/vga_switcheroo.c
@@ -215,7 +215,6 @@
/* stage one happens before delay */
static int vga_switchto_stage1(struct vga_switcheroo_client *new_client)
{
- int ret;
int i;
struct vga_switcheroo_client *active = NULL;
@@ -228,11 +227,6 @@
if (!active)
return 0;
- /* power up the first device */
- ret = pci_enable_device(new_client->pdev);
- if (ret)
- return ret;
-
if (new_client->pwr_state == VGA_SWITCHEROO_OFF)
vga_switchon(new_client);
diff --git a/drivers/gpu/vga/vgaarb.c b/drivers/gpu/vga/vgaarb.c
index be8d4cb..8a1021f 100644
--- a/drivers/gpu/vga/vgaarb.c
+++ b/drivers/gpu/vga/vgaarb.c
@@ -61,7 +61,7 @@
unsigned int mem_lock_cnt; /* legacy MEM lock count */
unsigned int io_norm_cnt; /* normal IO count */
unsigned int mem_norm_cnt; /* normal MEM count */
-
+ bool bridge_has_one_vga;
/* allow IRQ enable/disable hook */
void *cookie;
void (*irq_set_state)(void *cookie, bool enable);
@@ -165,6 +165,8 @@
unsigned int wants, legacy_wants, match;
struct vga_device *conflict;
unsigned int pci_bits;
+ u32 flags = 0;
+
/* Account for "normal" resources to lock. If we decode the legacy,
* counterpart, we need to request it as well
*/
@@ -237,16 +239,23 @@
/* looks like he doesn't have a lock, we can steal
* them from him
*/
- vga_irq_set_state(conflict, false);
+ flags = 0;
pci_bits = 0;
- if (lwants & (VGA_RSRC_LEGACY_MEM|VGA_RSRC_NORMAL_MEM))
- pci_bits |= PCI_COMMAND_MEMORY;
- if (lwants & (VGA_RSRC_LEGACY_IO|VGA_RSRC_NORMAL_IO))
- pci_bits |= PCI_COMMAND_IO;
- pci_set_vga_state(conflict->pdev, false, pci_bits,
- change_bridge);
+ if (!conflict->bridge_has_one_vga) {
+ vga_irq_set_state(conflict, false);
+ flags |= PCI_VGA_STATE_CHANGE_DECODES;
+ if (lwants & (VGA_RSRC_LEGACY_MEM|VGA_RSRC_NORMAL_MEM))
+ pci_bits |= PCI_COMMAND_MEMORY;
+ if (lwants & (VGA_RSRC_LEGACY_IO|VGA_RSRC_NORMAL_IO))
+ pci_bits |= PCI_COMMAND_IO;
+ }
+
+ if (change_bridge)
+ flags |= PCI_VGA_STATE_CHANGE_BRIDGE;
+
+ pci_set_vga_state(conflict->pdev, false, pci_bits, flags);
conflict->owns &= ~lwants;
/* If he also owned non-legacy, that is no longer the case */
if (lwants & VGA_RSRC_LEGACY_MEM)
@@ -261,14 +270,24 @@
* also have in "decodes". We can lock resources we don't decode but
* not own them.
*/
+ flags = 0;
pci_bits = 0;
- if (wants & (VGA_RSRC_LEGACY_MEM|VGA_RSRC_NORMAL_MEM))
- pci_bits |= PCI_COMMAND_MEMORY;
- if (wants & (VGA_RSRC_LEGACY_IO|VGA_RSRC_NORMAL_IO))
- pci_bits |= PCI_COMMAND_IO;
- pci_set_vga_state(vgadev->pdev, true, pci_bits, !!(wants & VGA_RSRC_LEGACY_MASK));
- vga_irq_set_state(vgadev, true);
+ if (!vgadev->bridge_has_one_vga) {
+ flags |= PCI_VGA_STATE_CHANGE_DECODES;
+ if (wants & (VGA_RSRC_LEGACY_MEM|VGA_RSRC_NORMAL_MEM))
+ pci_bits |= PCI_COMMAND_MEMORY;
+ if (wants & (VGA_RSRC_LEGACY_IO|VGA_RSRC_NORMAL_IO))
+ pci_bits |= PCI_COMMAND_IO;
+ }
+ if (!!(wants & VGA_RSRC_LEGACY_MASK))
+ flags |= PCI_VGA_STATE_CHANGE_BRIDGE;
+
+ pci_set_vga_state(vgadev->pdev, true, pci_bits, flags);
+
+ if (!vgadev->bridge_has_one_vga) {
+ vga_irq_set_state(vgadev, true);
+ }
vgadev->owns |= (wants & vgadev->decodes);
lock_them:
vgadev->locks |= (rsrc & VGA_RSRC_LEGACY_MASK);
@@ -421,6 +440,62 @@
}
EXPORT_SYMBOL(vga_put);
+/* Rules for using a bridge to control a VGA descendant decoding:
+ if a bridge has only one VGA descendant then it can be used
+ to control the VGA routing for that device.
+ It should always use the bridge closest to the device to control it.
+ If a bridge has a direct VGA descendant, but also have a sub-bridge
+ VGA descendant then we cannot use that bridge to control the direct VGA descendant.
+ So for every device we register, we need to iterate all its parent bridges
+ so we can invalidate any devices using them properly.
+*/
+static void vga_arbiter_check_bridge_sharing(struct vga_device *vgadev)
+{
+ struct vga_device *same_bridge_vgadev;
+ struct pci_bus *new_bus, *bus;
+ struct pci_dev *new_bridge, *bridge;
+
+ vgadev->bridge_has_one_vga = true;
+
+ if (list_empty(&vga_list))
+ return;
+
+ /* okay iterate the new devices bridge hierarachy */
+ new_bus = vgadev->pdev->bus;
+ while (new_bus) {
+ new_bridge = new_bus->self;
+
+ if (new_bridge) {
+ /* go through list of devices already registered */
+ list_for_each_entry(same_bridge_vgadev, &vga_list, list) {
+ bus = same_bridge_vgadev->pdev->bus;
+ bridge = bus->self;
+
+ /* see if the share a bridge with this device */
+ if (new_bridge == bridge) {
+ /* if their direct parent bridge is the same
+ as any bridge of this device then it can't be used
+ for that device */
+ same_bridge_vgadev->bridge_has_one_vga = false;
+ }
+
+ /* now iterate the previous devices bridge hierarchy */
+ /* if the new devices parent bridge is in the other devices
+ hierarchy then we can't use it to control this device */
+ while (bus) {
+ bridge = bus->self;
+ if (bridge) {
+ if (bridge == vgadev->pdev->bus->self)
+ vgadev->bridge_has_one_vga = false;
+ }
+ bus = bus->parent;
+ }
+ }
+ }
+ new_bus = new_bus->parent;
+ }
+}
+
/*
* Currently, we assume that the "initial" setup of the system is
* not sane, that is we come up with conflicting devices and let
@@ -500,6 +575,8 @@
vga_default = pci_dev_get(pdev);
#endif
+ vga_arbiter_check_bridge_sharing(vgadev);
+
/* Add to the list */
list_add(&vgadev->list, &vga_list);
vga_count++;
@@ -1222,6 +1299,7 @@
{
int rc;
struct pci_dev *pdev;
+ struct vga_device *vgadev;
rc = misc_register(&vga_arb_device);
if (rc < 0)
@@ -1238,6 +1316,13 @@
vga_arbiter_add_pci_device(pdev);
pr_info("vgaarb: loaded\n");
+
+ list_for_each_entry(vgadev, &vga_list, list) {
+ if (vgadev->bridge_has_one_vga)
+ pr_info("vgaarb: bridge control possible %s\n", pci_name(vgadev->pdev));
+ else
+ pr_info("vgaarb: no bridge control possible %s\n", pci_name(vgadev->pdev));
+ }
return rc;
}
subsys_initcall(vga_arb_device_init);
diff --git a/drivers/hid/hid-core.c b/drivers/hid/hid-core.c
index 4140fd2..c957c4b 100644
--- a/drivers/hid/hid-core.c
+++ b/drivers/hid/hid-core.c
@@ -1775,19 +1775,37 @@
{ HID_USB_DEVICE(USB_VENDOR_ID_KYE, USB_DEVICE_ID_KYE_GPEN_560) },
{ HID_BLUETOOTH_DEVICE(USB_VENDOR_ID_KYE, 0x0058) },
{ HID_USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_CASSY) },
+ { HID_USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_CASSY2) },
{ HID_USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_POCKETCASSY) },
+ { HID_USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_POCKETCASSY2) },
{ HID_USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_MOBILECASSY) },
+ { HID_USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_MOBILECASSY2) },
+ { HID_USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_MICROCASSYVOLTAGE) },
+ { HID_USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_MICROCASSYCURRENT) },
+ { HID_USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_MICROCASSYTIME) },
+ { HID_USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_MICROCASSYTEMPERATURE) },
+ { HID_USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_MICROCASSYPH) },
{ HID_USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_JWM) },
{ HID_USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_DMMP) },
{ HID_USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_UMIP) },
- { HID_USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_XRAY1) },
+ { HID_USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_UMIC) },
+ { HID_USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_UMIB) },
+ { HID_USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_XRAY) },
{ HID_USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_XRAY2) },
{ HID_USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_VIDEOCOM) },
+ { HID_USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_MOTOR) },
{ HID_USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_COM3LAB) },
{ HID_USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_TELEPORT) },
{ HID_USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_NETWORKANALYSER) },
{ HID_USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_POWERCONTROL) },
{ HID_USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_MACHINETEST) },
+ { HID_USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_MOSTANALYSER) },
+ { HID_USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_MOSTANALYSER2) },
+ { HID_USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_ABSESP) },
+ { HID_USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_AUTODATABUS) },
+ { HID_USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_MCT) },
+ { HID_USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_HYBRID) },
+ { HID_USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_HEATCONTROL) },
{ HID_USB_DEVICE(USB_VENDOR_ID_MCC, USB_DEVICE_ID_MCC_PMD1024LS) },
{ HID_USB_DEVICE(USB_VENDOR_ID_MCC, USB_DEVICE_ID_MCC_PMD1208LS) },
{ HID_USB_DEVICE(USB_VENDOR_ID_MICROCHIP, USB_DEVICE_ID_PICKIT1) },
diff --git a/drivers/hid/hid-ids.h b/drivers/hid/hid-ids.h
index e715c43..0b374a6 100644
--- a/drivers/hid/hid-ids.h
+++ b/drivers/hid/hid-ids.h
@@ -380,19 +380,38 @@
#define USB_VENDOR_ID_LD 0x0f11
#define USB_DEVICE_ID_LD_CASSY 0x1000
+#define USB_DEVICE_ID_LD_CASSY2 0x1001
#define USB_DEVICE_ID_LD_POCKETCASSY 0x1010
+#define USB_DEVICE_ID_LD_POCKETCASSY2 0x1011
#define USB_DEVICE_ID_LD_MOBILECASSY 0x1020
+#define USB_DEVICE_ID_LD_MOBILECASSY2 0x1021
+#define USB_DEVICE_ID_LD_MICROCASSYVOLTAGE 0x1031
+#define USB_DEVICE_ID_LD_MICROCASSYCURRENT 0x1032
+#define USB_DEVICE_ID_LD_MICROCASSYTIME 0x1033
+#define USB_DEVICE_ID_LD_MICROCASSYTEMPERATURE 0x1035
+#define USB_DEVICE_ID_LD_MICROCASSYPH 0x1038
#define USB_DEVICE_ID_LD_JWM 0x1080
#define USB_DEVICE_ID_LD_DMMP 0x1081
#define USB_DEVICE_ID_LD_UMIP 0x1090
-#define USB_DEVICE_ID_LD_XRAY1 0x1100
+#define USB_DEVICE_ID_LD_UMIC 0x10A0
+#define USB_DEVICE_ID_LD_UMIB 0x10B0
+#define USB_DEVICE_ID_LD_XRAY 0x1100
#define USB_DEVICE_ID_LD_XRAY2 0x1101
+#define USB_DEVICE_ID_LD_XRAYCT 0x1110
#define USB_DEVICE_ID_LD_VIDEOCOM 0x1200
+#define USB_DEVICE_ID_LD_MOTOR 0x1210
#define USB_DEVICE_ID_LD_COM3LAB 0x2000
#define USB_DEVICE_ID_LD_TELEPORT 0x2010
#define USB_DEVICE_ID_LD_NETWORKANALYSER 0x2020
#define USB_DEVICE_ID_LD_POWERCONTROL 0x2030
#define USB_DEVICE_ID_LD_MACHINETEST 0x2040
+#define USB_DEVICE_ID_LD_MOSTANALYSER 0x2050
+#define USB_DEVICE_ID_LD_MOSTANALYSER2 0x2051
+#define USB_DEVICE_ID_LD_ABSESP 0x2060
+#define USB_DEVICE_ID_LD_AUTODATABUS 0x2070
+#define USB_DEVICE_ID_LD_MCT 0x2080
+#define USB_DEVICE_ID_LD_HYBRID 0x2090
+#define USB_DEVICE_ID_LD_HEATCONTROL 0x20A0
#define USB_VENDOR_ID_LOGITECH 0x046d
#define USB_DEVICE_ID_LOGITECH_RECEIVER 0xc101
diff --git a/drivers/hwmon/Kconfig b/drivers/hwmon/Kconfig
index 43221be..16db83c 100644
--- a/drivers/hwmon/Kconfig
+++ b/drivers/hwmon/Kconfig
@@ -41,7 +41,7 @@
config SENSORS_ABITUGURU
tristate "Abit uGuru (rev 1 & 2)"
- depends on X86 && EXPERIMENTAL
+ depends on X86 && DMI && EXPERIMENTAL
help
If you say yes here you get support for the sensor part of the first
and second revision of the Abit uGuru chip. The voltage and frequency
@@ -56,7 +56,7 @@
config SENSORS_ABITUGURU3
tristate "Abit uGuru (rev 3)"
- depends on X86 && EXPERIMENTAL
+ depends on X86 && DMI && EXPERIMENTAL
help
If you say yes here you get support for the sensor part of the
third revision of the Abit uGuru chip. Only reading the sensors
@@ -213,7 +213,7 @@
config SENSORS_ASC7621
tristate "Andigilog aSC7621"
- depends on HWMON && I2C
+ depends on I2C
help
If you say yes here you get support for the aSC7621
family of SMBus sensors chip found on most Intel X38, X48, X58,
@@ -237,17 +237,27 @@
will be called k8temp.
config SENSORS_K10TEMP
- tristate "AMD Family 10h/11h/12h/14h temperature sensor"
+ tristate "AMD Family 10h+ temperature sensor"
depends on X86 && PCI
help
If you say yes here you get support for the temperature
sensor(s) inside your CPU. Supported are later revisions of
the AMD Family 10h and all revisions of the AMD Family 11h,
- 12h (Llano), and 14h (Brazos) microarchitectures.
+ 12h (Llano), 14h (Brazos) and 15h (Bulldozer) microarchitectures.
This driver can also be built as a module. If so, the module
will be called k10temp.
+config SENSORS_FAM15H_POWER
+ tristate "AMD Family 15h processor power"
+ depends on X86 && PCI
+ help
+ If you say yes here you get support for processor power
+ information of your AMD family 15h CPU.
+
+ This driver can also be built as a module. If so, the module
+ will be called fam15h_power.
+
config SENSORS_ASB100
tristate "Asus ASB100 Bach"
depends on X86 && I2C && EXPERIMENTAL
@@ -319,7 +329,7 @@
If you say yes here you get support for hardware monitoring
features of many Fintek Super-I/O (LPC) chips. The currently
supported chips are:
- F71808E
+ F71808E/A
F71858FG
F71862FG
F71863FG
@@ -978,6 +988,16 @@
This driver can also be built as a module. If so, the module
will be called emc2103.
+config SENSORS_EMC6W201
+ tristate "SMSC EMC6W201"
+ depends on I2C
+ help
+ If you say yes here you get support for the SMSC EMC6W201
+ hardware monitoring chip.
+
+ This driver can also be built as a module. If so, the module
+ will be called emc6w201.
+
config SENSORS_SMSC47M1
tristate "SMSC LPC47M10x and compatibles"
help
@@ -1341,6 +1361,16 @@
comment "ACPI drivers"
+config SENSORS_ACPI_POWER
+ tristate "ACPI 4.0 power meter"
+ help
+ This driver exposes ACPI 4.0 power meters as hardware monitoring
+ devices. Say Y (or M) if you have a computer with ACPI 4.0 firmware
+ and a power meter.
+
+ To compile this driver as a module, choose M here:
+ the module will be called acpi_power_meter.
+
config SENSORS_ATK0110
tristate "ASUS ATK0110"
depends on X86 && EXPERIMENTAL
diff --git a/drivers/hwmon/Makefile b/drivers/hwmon/Makefile
index 28e8d52..28061cf 100644
--- a/drivers/hwmon/Makefile
+++ b/drivers/hwmon/Makefile
@@ -6,6 +6,7 @@
obj-$(CONFIG_HWMON_VID) += hwmon-vid.o
# APCI drivers
+obj-$(CONFIG_SENSORS_ACPI_POWER) += acpi_power_meter.o
obj-$(CONFIG_SENSORS_ATK0110) += asus_atk0110.o
# Native drivers
@@ -45,9 +46,11 @@
obj-$(CONFIG_SENSORS_DS1621) += ds1621.o
obj-$(CONFIG_SENSORS_EMC1403) += emc1403.o
obj-$(CONFIG_SENSORS_EMC2103) += emc2103.o
+obj-$(CONFIG_SENSORS_EMC6W201) += emc6w201.o
obj-$(CONFIG_SENSORS_F71805F) += f71805f.o
obj-$(CONFIG_SENSORS_F71882FG) += f71882fg.o
obj-$(CONFIG_SENSORS_F75375S) += f75375s.o
+obj-$(CONFIG_SENSORS_FAM15H_POWER) += fam15h_power.o
obj-$(CONFIG_SENSORS_FSCHMD) += fschmd.o
obj-$(CONFIG_SENSORS_G760A) += g760a.o
obj-$(CONFIG_SENSORS_GL518SM) += gl518sm.o
diff --git a/drivers/hwmon/abituguru.c b/drivers/hwmon/abituguru.c
index e7d4c46..65a35cf 100644
--- a/drivers/hwmon/abituguru.c
+++ b/drivers/hwmon/abituguru.c
@@ -1448,15 +1448,12 @@
{
int address, err;
struct resource res = { .flags = IORESOURCE_IO };
-
-#ifdef CONFIG_DMI
const char *board_vendor = dmi_get_system_info(DMI_BOARD_VENDOR);
/* safety check, refuse to load on non Abit motherboards */
if (!force && (!board_vendor ||
strcmp(board_vendor, "http://www.abit.com.tw/")))
return -ENODEV;
-#endif
address = abituguru_detect();
if (address < 0)
diff --git a/drivers/hwmon/abituguru3.c b/drivers/hwmon/abituguru3.c
index e89d572..d30855a 100644
--- a/drivers/hwmon/abituguru3.c
+++ b/drivers/hwmon/abituguru3.c
@@ -1119,8 +1119,6 @@
.resume = abituguru3_resume
};
-#ifdef CONFIG_DMI
-
static int __init abituguru3_dmi_detect(void)
{
const char *board_vendor, *board_name;
@@ -1159,15 +1157,6 @@
return 1;
}
-#else /* !CONFIG_DMI */
-
-static inline int abituguru3_dmi_detect(void)
-{
- return 1;
-}
-
-#endif /* CONFIG_DMI */
-
/* FIXME: Manual detection should die eventually; we need to collect stable
* DMI model names first before we can rely entirely on CONFIG_DMI.
*/
@@ -1216,10 +1205,8 @@
if (err)
return err;
-#ifdef CONFIG_DMI
pr_warn("this motherboard was not detected using DMI. "
"Please send the output of \"dmidecode\" to the abituguru3 maintainer (see MAINTAINERS)\n");
-#endif
}
err = platform_driver_register(&abituguru3_driver);
diff --git a/drivers/acpi/power_meter.c b/drivers/hwmon/acpi_power_meter.c
similarity index 100%
rename from drivers/acpi/power_meter.c
rename to drivers/hwmon/acpi_power_meter.c
diff --git a/drivers/hwmon/adcxx.c b/drivers/hwmon/adcxx.c
index fbdc765..b2cacbe 100644
--- a/drivers/hwmon/adcxx.c
+++ b/drivers/hwmon/adcxx.c
@@ -62,7 +62,7 @@
{
struct spi_device *spi = to_spi_device(dev);
struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
- struct adcxx *adc = dev_get_drvdata(&spi->dev);
+ struct adcxx *adc = spi_get_drvdata(spi);
u8 tx_buf[2];
u8 rx_buf[2];
int status;
@@ -105,7 +105,7 @@
struct device_attribute *devattr, char *buf)
{
struct spi_device *spi = to_spi_device(dev);
- struct adcxx *adc = dev_get_drvdata(&spi->dev);
+ struct adcxx *adc = spi_get_drvdata(spi);
u32 reference;
if (mutex_lock_interruptible(&adc->lock))
@@ -122,7 +122,7 @@
struct device_attribute *devattr, const char *buf, size_t count)
{
struct spi_device *spi = to_spi_device(dev);
- struct adcxx *adc = dev_get_drvdata(&spi->dev);
+ struct adcxx *adc = spi_get_drvdata(spi);
unsigned long value;
if (strict_strtoul(buf, 10, &value))
@@ -142,7 +142,7 @@
*devattr, char *buf)
{
struct spi_device *spi = to_spi_device(dev);
- struct adcxx *adc = dev_get_drvdata(&spi->dev);
+ struct adcxx *adc = spi_get_drvdata(spi);
return sprintf(buf, "adcxx%ds\n", adc->channels);
}
@@ -182,7 +182,7 @@
mutex_lock(&adc->lock);
- dev_set_drvdata(&spi->dev, adc);
+ spi_set_drvdata(spi, adc);
for (i = 0; i < 3 + adc->channels; i++) {
status = device_create_file(&spi->dev, &ad_input[i].dev_attr);
@@ -206,7 +206,7 @@
for (i--; i >= 0; i--)
device_remove_file(&spi->dev, &ad_input[i].dev_attr);
- dev_set_drvdata(&spi->dev, NULL);
+ spi_set_drvdata(spi, NULL);
mutex_unlock(&adc->lock);
kfree(adc);
return status;
@@ -214,7 +214,7 @@
static int __devexit adcxx_remove(struct spi_device *spi)
{
- struct adcxx *adc = dev_get_drvdata(&spi->dev);
+ struct adcxx *adc = spi_get_drvdata(spi);
int i;
mutex_lock(&adc->lock);
@@ -222,7 +222,7 @@
for (i = 0; i < 3 + adc->channels; i++)
device_remove_file(&spi->dev, &ad_input[i].dev_attr);
- dev_set_drvdata(&spi->dev, NULL);
+ spi_set_drvdata(spi, NULL);
mutex_unlock(&adc->lock);
kfree(adc);
diff --git a/drivers/hwmon/coretemp.c b/drivers/hwmon/coretemp.c
index 5c7cd60..9577c43 100644
--- a/drivers/hwmon/coretemp.c
+++ b/drivers/hwmon/coretemp.c
@@ -51,10 +51,12 @@
#define TO_PHYS_ID(cpu) cpu_data(cpu).phys_proc_id
#define TO_CORE_ID(cpu) cpu_data(cpu).cpu_core_id
#define TO_ATTR_NO(cpu) (TO_CORE_ID(cpu) + BASE_SYSFS_ATTR_NO)
+#define for_each_sibling(i, cpu) for_each_cpu(i, cpu_sibling_mask(cpu))
#else
#define TO_PHYS_ID(cpu) (cpu)
#define TO_CORE_ID(cpu) (cpu)
#define TO_ATTR_NO(cpu) (cpu)
+#define for_each_sibling(i, cpu) for (i = 0; false; )
#endif
/*
@@ -504,7 +506,13 @@
if (attr_no > MAX_CORE_DATA - 1)
return -ERANGE;
- /* Skip if it is a HT core, Not an error */
+ /*
+ * Provide a single set of attributes for all HT siblings of a core
+ * to avoid duplicate sensors (the processor ID and core ID of all
+ * HT siblings of a core is the same).
+ * Skip if a HT sibling of this core is already online.
+ * This is not an error.
+ */
if (pdata->core_data[attr_no] != NULL)
return 0;
@@ -761,10 +769,20 @@
if (pdata->core_data[indx] && pdata->core_data[indx]->cpu == cpu)
coretemp_remove_core(pdata, &pdev->dev, indx);
- /* Online the HT version of this core, if any */
- for_each_cpu(i, cpu_sibling_mask(cpu)) {
+ /*
+ * If a core is taken offline, but a HT sibling of the same core is
+ * still online, register the alternate sibling. This ensures that
+ * exactly one set of attributes is provided as long as at least one
+ * HT sibling of a core is online.
+ */
+ for_each_sibling(i, cpu) {
if (i != cpu) {
get_core_online(i);
+ /*
+ * Display temperature sensor data for one HT sibling
+ * per core only, so abort the loop after one such
+ * sibling has been found.
+ */
break;
}
}
diff --git a/drivers/hwmon/emc6w201.c b/drivers/hwmon/emc6w201.c
new file mode 100644
index 0000000..e0ef323
--- /dev/null
+++ b/drivers/hwmon/emc6w201.c
@@ -0,0 +1,539 @@
+/*
+ * emc6w201.c - Hardware monitoring driver for the SMSC EMC6W201
+ * Copyright (C) 2011 Jean Delvare <khali@linux-fr.org>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/jiffies.h>
+#include <linux/i2c.h>
+#include <linux/hwmon.h>
+#include <linux/hwmon-sysfs.h>
+#include <linux/err.h>
+#include <linux/mutex.h>
+
+/*
+ * Addresses to scan
+ */
+
+static const unsigned short normal_i2c[] = { 0x2c, 0x2d, 0x2e, I2C_CLIENT_END };
+
+/*
+ * The EMC6W201 registers
+ */
+
+#define EMC6W201_REG_IN(nr) (0x20 + (nr))
+#define EMC6W201_REG_TEMP(nr) (0x26 + (nr))
+#define EMC6W201_REG_FAN(nr) (0x2C + (nr) * 2)
+#define EMC6W201_REG_COMPANY 0x3E
+#define EMC6W201_REG_VERSTEP 0x3F
+#define EMC6W201_REG_CONFIG 0x40
+#define EMC6W201_REG_IN_LOW(nr) (0x4A + (nr) * 2)
+#define EMC6W201_REG_IN_HIGH(nr) (0x4B + (nr) * 2)
+#define EMC6W201_REG_TEMP_LOW(nr) (0x56 + (nr) * 2)
+#define EMC6W201_REG_TEMP_HIGH(nr) (0x57 + (nr) * 2)
+#define EMC6W201_REG_FAN_MIN(nr) (0x62 + (nr) * 2)
+
+enum { input, min, max } subfeature;
+
+/*
+ * Per-device data
+ */
+
+struct emc6w201_data {
+ struct device *hwmon_dev;
+ struct mutex update_lock;
+ char valid; /* zero until following fields are valid */
+ unsigned long last_updated; /* in jiffies */
+
+ /* registers values */
+ u8 in[3][6];
+ s8 temp[3][6];
+ u16 fan[2][5];
+};
+
+/*
+ * Combine LSB and MSB registers in a single value
+ * Locking: must be called with data->update_lock held
+ */
+static u16 emc6w201_read16(struct i2c_client *client, u8 reg)
+{
+ int lsb, msb;
+
+ lsb = i2c_smbus_read_byte_data(client, reg);
+ msb = i2c_smbus_read_byte_data(client, reg + 1);
+ if (lsb < 0 || msb < 0) {
+ dev_err(&client->dev, "16-bit read failed at 0x%02x\n", reg);
+ return 0xFFFF; /* Arbitrary value */
+ }
+
+ return (msb << 8) | lsb;
+}
+
+/*
+ * Write 16-bit value to LSB and MSB registers
+ * Locking: must be called with data->update_lock held
+ */
+static int emc6w201_write16(struct i2c_client *client, u8 reg, u16 val)
+{
+ int err;
+
+ err = i2c_smbus_write_byte_data(client, reg, val & 0xff);
+ if (!err)
+ err = i2c_smbus_write_byte_data(client, reg + 1, val >> 8);
+ if (err < 0)
+ dev_err(&client->dev, "16-bit write failed at 0x%02x\n", reg);
+
+ return err;
+}
+
+static struct emc6w201_data *emc6w201_update_device(struct device *dev)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct emc6w201_data *data = i2c_get_clientdata(client);
+ int nr;
+
+ mutex_lock(&data->update_lock);
+
+ if (time_after(jiffies, data->last_updated + HZ) || !data->valid) {
+ for (nr = 0; nr < 6; nr++) {
+ data->in[input][nr] =
+ i2c_smbus_read_byte_data(client,
+ EMC6W201_REG_IN(nr));
+ data->in[min][nr] =
+ i2c_smbus_read_byte_data(client,
+ EMC6W201_REG_IN_LOW(nr));
+ data->in[max][nr] =
+ i2c_smbus_read_byte_data(client,
+ EMC6W201_REG_IN_HIGH(nr));
+ }
+
+ for (nr = 0; nr < 6; nr++) {
+ data->temp[input][nr] =
+ i2c_smbus_read_byte_data(client,
+ EMC6W201_REG_TEMP(nr));
+ data->temp[min][nr] =
+ i2c_smbus_read_byte_data(client,
+ EMC6W201_REG_TEMP_LOW(nr));
+ data->temp[max][nr] =
+ i2c_smbus_read_byte_data(client,
+ EMC6W201_REG_TEMP_HIGH(nr));
+ }
+
+ for (nr = 0; nr < 5; nr++) {
+ data->fan[input][nr] =
+ emc6w201_read16(client,
+ EMC6W201_REG_FAN(nr));
+ data->fan[min][nr] =
+ emc6w201_read16(client,
+ EMC6W201_REG_FAN_MIN(nr));
+ }
+
+ data->last_updated = jiffies;
+ data->valid = 1;
+ }
+
+ mutex_unlock(&data->update_lock);
+
+ return data;
+}
+
+/*
+ * Sysfs callback functions
+ */
+
+static const u16 nominal_mv[6] = { 2500, 1500, 3300, 5000, 1500, 1500 };
+
+static ssize_t show_in(struct device *dev, struct device_attribute *devattr,
+ char *buf)
+{
+ struct emc6w201_data *data = emc6w201_update_device(dev);
+ int sf = to_sensor_dev_attr_2(devattr)->index;
+ int nr = to_sensor_dev_attr_2(devattr)->nr;
+
+ return sprintf(buf, "%u\n",
+ (unsigned)data->in[sf][nr] * nominal_mv[nr] / 0xC0);
+}
+
+static ssize_t set_in(struct device *dev, struct device_attribute *devattr,
+ const char *buf, size_t count)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct emc6w201_data *data = i2c_get_clientdata(client);
+ int sf = to_sensor_dev_attr_2(devattr)->index;
+ int nr = to_sensor_dev_attr_2(devattr)->nr;
+ int err;
+ long val;
+ u8 reg;
+
+ err = strict_strtol(buf, 10, &val);
+ if (err < 0)
+ return err;
+
+ val = DIV_ROUND_CLOSEST(val * 0xC0, nominal_mv[nr]);
+ reg = (sf == min) ? EMC6W201_REG_IN_LOW(nr)
+ : EMC6W201_REG_IN_HIGH(nr);
+
+ mutex_lock(&data->update_lock);
+ data->in[sf][nr] = SENSORS_LIMIT(val, 0, 255);
+ err = i2c_smbus_write_byte_data(client, reg, data->in[sf][nr]);
+ mutex_unlock(&data->update_lock);
+
+ return err < 0 ? err : count;
+}
+
+static ssize_t show_temp(struct device *dev, struct device_attribute *devattr,
+ char *buf)
+{
+ struct emc6w201_data *data = emc6w201_update_device(dev);
+ int sf = to_sensor_dev_attr_2(devattr)->index;
+ int nr = to_sensor_dev_attr_2(devattr)->nr;
+
+ return sprintf(buf, "%d\n", (int)data->temp[sf][nr] * 1000);
+}
+
+static ssize_t set_temp(struct device *dev, struct device_attribute *devattr,
+ const char *buf, size_t count)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct emc6w201_data *data = i2c_get_clientdata(client);
+ int sf = to_sensor_dev_attr_2(devattr)->index;
+ int nr = to_sensor_dev_attr_2(devattr)->nr;
+ int err;
+ long val;
+ u8 reg;
+
+ err = strict_strtol(buf, 10, &val);
+ if (err < 0)
+ return err;
+
+ val /= 1000;
+ reg = (sf == min) ? EMC6W201_REG_TEMP_LOW(nr)
+ : EMC6W201_REG_TEMP_HIGH(nr);
+
+ mutex_lock(&data->update_lock);
+ data->temp[sf][nr] = SENSORS_LIMIT(val, -127, 128);
+ err = i2c_smbus_write_byte_data(client, reg, data->temp[sf][nr]);
+ mutex_unlock(&data->update_lock);
+
+ return err < 0 ? err : count;
+}
+
+static ssize_t show_fan(struct device *dev, struct device_attribute *devattr,
+ char *buf)
+{
+ struct emc6w201_data *data = emc6w201_update_device(dev);
+ int sf = to_sensor_dev_attr_2(devattr)->index;
+ int nr = to_sensor_dev_attr_2(devattr)->nr;
+ unsigned rpm;
+
+ if (data->fan[sf][nr] == 0 || data->fan[sf][nr] == 0xFFFF)
+ rpm = 0;
+ else
+ rpm = 5400000U / data->fan[sf][nr];
+
+ return sprintf(buf, "%u\n", rpm);
+}
+
+static ssize_t set_fan(struct device *dev, struct device_attribute *devattr,
+ const char *buf, size_t count)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct emc6w201_data *data = i2c_get_clientdata(client);
+ int sf = to_sensor_dev_attr_2(devattr)->index;
+ int nr = to_sensor_dev_attr_2(devattr)->nr;
+ int err;
+ unsigned long val;
+
+ err = strict_strtoul(buf, 10, &val);
+ if (err < 0)
+ return err;
+
+ if (val == 0) {
+ val = 0xFFFF;
+ } else {
+ val = DIV_ROUND_CLOSEST(5400000U, val);
+ val = SENSORS_LIMIT(val, 0, 0xFFFE);
+ }
+
+ mutex_lock(&data->update_lock);
+ data->fan[sf][nr] = val;
+ err = emc6w201_write16(client, EMC6W201_REG_FAN_MIN(nr),
+ data->fan[sf][nr]);
+ mutex_unlock(&data->update_lock);
+
+ return err < 0 ? err : count;
+}
+
+static SENSOR_DEVICE_ATTR_2(in0_input, S_IRUGO, show_in, NULL, 0, input);
+static SENSOR_DEVICE_ATTR_2(in0_min, S_IRUGO | S_IWUSR, show_in, set_in,
+ 0, min);
+static SENSOR_DEVICE_ATTR_2(in0_max, S_IRUGO | S_IWUSR, show_in, set_in,
+ 0, max);
+static SENSOR_DEVICE_ATTR_2(in1_input, S_IRUGO, show_in, NULL, 1, input);
+static SENSOR_DEVICE_ATTR_2(in1_min, S_IRUGO | S_IWUSR, show_in, set_in,
+ 1, min);
+static SENSOR_DEVICE_ATTR_2(in1_max, S_IRUGO | S_IWUSR, show_in, set_in,
+ 1, max);
+static SENSOR_DEVICE_ATTR_2(in2_input, S_IRUGO, show_in, NULL, 2, input);
+static SENSOR_DEVICE_ATTR_2(in2_min, S_IRUGO | S_IWUSR, show_in, set_in,
+ 2, min);
+static SENSOR_DEVICE_ATTR_2(in2_max, S_IRUGO | S_IWUSR, show_in, set_in,
+ 2, max);
+static SENSOR_DEVICE_ATTR_2(in3_input, S_IRUGO, show_in, NULL, 3, input);
+static SENSOR_DEVICE_ATTR_2(in3_min, S_IRUGO | S_IWUSR, show_in, set_in,
+ 3, min);
+static SENSOR_DEVICE_ATTR_2(in3_max, S_IRUGO | S_IWUSR, show_in, set_in,
+ 3, max);
+static SENSOR_DEVICE_ATTR_2(in4_input, S_IRUGO, show_in, NULL, 4, input);
+static SENSOR_DEVICE_ATTR_2(in4_min, S_IRUGO | S_IWUSR, show_in, set_in,
+ 4, min);
+static SENSOR_DEVICE_ATTR_2(in4_max, S_IRUGO | S_IWUSR, show_in, set_in,
+ 4, max);
+static SENSOR_DEVICE_ATTR_2(in5_input, S_IRUGO, show_in, NULL, 5, input);
+static SENSOR_DEVICE_ATTR_2(in5_min, S_IRUGO | S_IWUSR, show_in, set_in,
+ 5, min);
+static SENSOR_DEVICE_ATTR_2(in5_max, S_IRUGO | S_IWUSR, show_in, set_in,
+ 5, max);
+
+static SENSOR_DEVICE_ATTR_2(temp1_input, S_IRUGO, show_temp, NULL, 0, input);
+static SENSOR_DEVICE_ATTR_2(temp1_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
+ 0, min);
+static SENSOR_DEVICE_ATTR_2(temp1_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
+ 0, max);
+static SENSOR_DEVICE_ATTR_2(temp2_input, S_IRUGO, show_temp, NULL, 1, input);
+static SENSOR_DEVICE_ATTR_2(temp2_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
+ 1, min);
+static SENSOR_DEVICE_ATTR_2(temp2_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
+ 1, max);
+static SENSOR_DEVICE_ATTR_2(temp3_input, S_IRUGO, show_temp, NULL, 2, input);
+static SENSOR_DEVICE_ATTR_2(temp3_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
+ 2, min);
+static SENSOR_DEVICE_ATTR_2(temp3_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
+ 2, max);
+static SENSOR_DEVICE_ATTR_2(temp4_input, S_IRUGO, show_temp, NULL, 3, input);
+static SENSOR_DEVICE_ATTR_2(temp4_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
+ 3, min);
+static SENSOR_DEVICE_ATTR_2(temp4_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
+ 3, max);
+static SENSOR_DEVICE_ATTR_2(temp5_input, S_IRUGO, show_temp, NULL, 4, input);
+static SENSOR_DEVICE_ATTR_2(temp5_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
+ 4, min);
+static SENSOR_DEVICE_ATTR_2(temp5_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
+ 4, max);
+static SENSOR_DEVICE_ATTR_2(temp6_input, S_IRUGO, show_temp, NULL, 5, input);
+static SENSOR_DEVICE_ATTR_2(temp6_min, S_IRUGO | S_IWUSR, show_temp, set_temp,
+ 5, min);
+static SENSOR_DEVICE_ATTR_2(temp6_max, S_IRUGO | S_IWUSR, show_temp, set_temp,
+ 5, max);
+
+static SENSOR_DEVICE_ATTR_2(fan1_input, S_IRUGO, show_fan, NULL, 0, input);
+static SENSOR_DEVICE_ATTR_2(fan1_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
+ 0, min);
+static SENSOR_DEVICE_ATTR_2(fan2_input, S_IRUGO, show_fan, NULL, 1, input);
+static SENSOR_DEVICE_ATTR_2(fan2_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
+ 1, min);
+static SENSOR_DEVICE_ATTR_2(fan3_input, S_IRUGO, show_fan, NULL, 2, input);
+static SENSOR_DEVICE_ATTR_2(fan3_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
+ 2, min);
+static SENSOR_DEVICE_ATTR_2(fan4_input, S_IRUGO, show_fan, NULL, 3, input);
+static SENSOR_DEVICE_ATTR_2(fan4_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
+ 3, min);
+static SENSOR_DEVICE_ATTR_2(fan5_input, S_IRUGO, show_fan, NULL, 4, input);
+static SENSOR_DEVICE_ATTR_2(fan5_min, S_IRUGO | S_IWUSR, show_fan, set_fan,
+ 4, min);
+
+static struct attribute *emc6w201_attributes[] = {
+ &sensor_dev_attr_in0_input.dev_attr.attr,
+ &sensor_dev_attr_in0_min.dev_attr.attr,
+ &sensor_dev_attr_in0_max.dev_attr.attr,
+ &sensor_dev_attr_in1_input.dev_attr.attr,
+ &sensor_dev_attr_in1_min.dev_attr.attr,
+ &sensor_dev_attr_in1_max.dev_attr.attr,
+ &sensor_dev_attr_in2_input.dev_attr.attr,
+ &sensor_dev_attr_in2_min.dev_attr.attr,
+ &sensor_dev_attr_in2_max.dev_attr.attr,
+ &sensor_dev_attr_in3_input.dev_attr.attr,
+ &sensor_dev_attr_in3_min.dev_attr.attr,
+ &sensor_dev_attr_in3_max.dev_attr.attr,
+ &sensor_dev_attr_in4_input.dev_attr.attr,
+ &sensor_dev_attr_in4_min.dev_attr.attr,
+ &sensor_dev_attr_in4_max.dev_attr.attr,
+ &sensor_dev_attr_in5_input.dev_attr.attr,
+ &sensor_dev_attr_in5_min.dev_attr.attr,
+ &sensor_dev_attr_in5_max.dev_attr.attr,
+
+ &sensor_dev_attr_temp1_input.dev_attr.attr,
+ &sensor_dev_attr_temp1_min.dev_attr.attr,
+ &sensor_dev_attr_temp1_max.dev_attr.attr,
+ &sensor_dev_attr_temp2_input.dev_attr.attr,
+ &sensor_dev_attr_temp2_min.dev_attr.attr,
+ &sensor_dev_attr_temp2_max.dev_attr.attr,
+ &sensor_dev_attr_temp3_input.dev_attr.attr,
+ &sensor_dev_attr_temp3_min.dev_attr.attr,
+ &sensor_dev_attr_temp3_max.dev_attr.attr,
+ &sensor_dev_attr_temp4_input.dev_attr.attr,
+ &sensor_dev_attr_temp4_min.dev_attr.attr,
+ &sensor_dev_attr_temp4_max.dev_attr.attr,
+ &sensor_dev_attr_temp5_input.dev_attr.attr,
+ &sensor_dev_attr_temp5_min.dev_attr.attr,
+ &sensor_dev_attr_temp5_max.dev_attr.attr,
+ &sensor_dev_attr_temp6_input.dev_attr.attr,
+ &sensor_dev_attr_temp6_min.dev_attr.attr,
+ &sensor_dev_attr_temp6_max.dev_attr.attr,
+
+ &sensor_dev_attr_fan1_input.dev_attr.attr,
+ &sensor_dev_attr_fan1_min.dev_attr.attr,
+ &sensor_dev_attr_fan2_input.dev_attr.attr,
+ &sensor_dev_attr_fan2_min.dev_attr.attr,
+ &sensor_dev_attr_fan3_input.dev_attr.attr,
+ &sensor_dev_attr_fan3_min.dev_attr.attr,
+ &sensor_dev_attr_fan4_input.dev_attr.attr,
+ &sensor_dev_attr_fan4_min.dev_attr.attr,
+ &sensor_dev_attr_fan5_input.dev_attr.attr,
+ &sensor_dev_attr_fan5_min.dev_attr.attr,
+ NULL
+};
+
+static const struct attribute_group emc6w201_group = {
+ .attrs = emc6w201_attributes,
+};
+
+/*
+ * Driver interface
+ */
+
+/* Return 0 if detection is successful, -ENODEV otherwise */
+static int emc6w201_detect(struct i2c_client *client,
+ struct i2c_board_info *info)
+{
+ struct i2c_adapter *adapter = client->adapter;
+ int company, verstep, config;
+
+ if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA))
+ return -ENODEV;
+
+ /* Identification */
+ company = i2c_smbus_read_byte_data(client, EMC6W201_REG_COMPANY);
+ if (company != 0x5C)
+ return -ENODEV;
+ verstep = i2c_smbus_read_byte_data(client, EMC6W201_REG_VERSTEP);
+ if (verstep < 0 || (verstep & 0xF0) != 0xB0)
+ return -ENODEV;
+ if ((verstep & 0x0F) > 2) {
+ dev_dbg(&client->dev, "Unknwown EMC6W201 stepping %d\n",
+ verstep & 0x0F);
+ return -ENODEV;
+ }
+
+ /* Check configuration */
+ config = i2c_smbus_read_byte_data(client, EMC6W201_REG_CONFIG);
+ if ((config & 0xF4) != 0x04)
+ return -ENODEV;
+ if (!(config & 0x01)) {
+ dev_err(&client->dev, "Monitoring not enabled\n");
+ return -ENODEV;
+ }
+
+ strlcpy(info->type, "emc6w201", I2C_NAME_SIZE);
+
+ return 0;
+}
+
+static int emc6w201_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ struct emc6w201_data *data;
+ int err;
+
+ data = kzalloc(sizeof(struct emc6w201_data), GFP_KERNEL);
+ if (!data) {
+ err = -ENOMEM;
+ goto exit;
+ }
+
+ i2c_set_clientdata(client, data);
+ mutex_init(&data->update_lock);
+
+ /* Create sysfs attribute */
+ err = sysfs_create_group(&client->dev.kobj, &emc6w201_group);
+ if (err)
+ goto exit_free;
+
+ /* Expose as a hwmon device */
+ data->hwmon_dev = hwmon_device_register(&client->dev);
+ if (IS_ERR(data->hwmon_dev)) {
+ err = PTR_ERR(data->hwmon_dev);
+ goto exit_remove;
+ }
+
+ return 0;
+
+ exit_remove:
+ sysfs_remove_group(&client->dev.kobj, &emc6w201_group);
+ exit_free:
+ kfree(data);
+ exit:
+ return err;
+}
+
+static int emc6w201_remove(struct i2c_client *client)
+{
+ struct emc6w201_data *data = i2c_get_clientdata(client);
+
+ hwmon_device_unregister(data->hwmon_dev);
+ sysfs_remove_group(&client->dev.kobj, &emc6w201_group);
+ kfree(data);
+
+ return 0;
+}
+
+static const struct i2c_device_id emc6w201_id[] = {
+ { "emc6w201", 0 },
+ { }
+};
+MODULE_DEVICE_TABLE(i2c, emc6w201_id);
+
+static struct i2c_driver emc6w201_driver = {
+ .class = I2C_CLASS_HWMON,
+ .driver = {
+ .name = "emc6w201",
+ },
+ .probe = emc6w201_probe,
+ .remove = emc6w201_remove,
+ .id_table = emc6w201_id,
+ .detect = emc6w201_detect,
+ .address_list = normal_i2c,
+};
+
+static int __init sensors_emc6w201_init(void)
+{
+ return i2c_add_driver(&emc6w201_driver);
+}
+module_init(sensors_emc6w201_init);
+
+static void __exit sensors_emc6w201_exit(void)
+{
+ i2c_del_driver(&emc6w201_driver);
+}
+module_exit(sensors_emc6w201_exit);
+
+MODULE_AUTHOR("Jean Delvare <khali@linux-fr.org>");
+MODULE_DESCRIPTION("SMSC EMC6W201 hardware monitoring driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/hwmon/f71882fg.c b/drivers/hwmon/f71882fg.c
index ca07a32..a4a94a0 100644
--- a/drivers/hwmon/f71882fg.c
+++ b/drivers/hwmon/f71882fg.c
@@ -48,6 +48,7 @@
#define SIO_FINTEK_ID 0x1934 /* Manufacturers ID */
#define SIO_F71808E_ID 0x0901 /* Chipset ID */
+#define SIO_F71808A_ID 0x1001 /* Chipset ID */
#define SIO_F71858_ID 0x0507 /* Chipset ID */
#define SIO_F71862_ID 0x0601 /* Chipset ID */
#define SIO_F71869_ID 0x0814 /* Chipset ID */
@@ -107,11 +108,12 @@
module_param(force_id, ushort, 0);
MODULE_PARM_DESC(force_id, "Override the detected device ID");
-enum chips { f71808e, f71858fg, f71862fg, f71869, f71882fg, f71889fg,
+enum chips { f71808e, f71808a, f71858fg, f71862fg, f71869, f71882fg, f71889fg,
f71889ed, f71889a, f8000, f81865f };
static const char *f71882fg_names[] = {
"f71808e",
+ "f71808a",
"f71858fg",
"f71862fg",
"f71869", /* Both f71869f and f71869e, reg. compatible and same id */
@@ -125,6 +127,7 @@
static const char f71882fg_has_in[][F71882FG_MAX_INS] = {
[f71808e] = { 1, 1, 1, 1, 1, 1, 0, 1, 1 },
+ [f71808a] = { 1, 1, 1, 1, 0, 0, 0, 1, 1 },
[f71858fg] = { 1, 1, 1, 0, 0, 0, 0, 0, 0 },
[f71862fg] = { 1, 1, 1, 1, 1, 1, 1, 1, 1 },
[f71869] = { 1, 1, 1, 1, 1, 1, 1, 1, 1 },
@@ -138,6 +141,7 @@
static const char f71882fg_has_in1_alarm[] = {
[f71808e] = 0,
+ [f71808a] = 0,
[f71858fg] = 0,
[f71862fg] = 0,
[f71869] = 0,
@@ -149,8 +153,9 @@
[f81865f] = 1,
};
-static const char f71882fg_has_beep[] = {
+static const char f71882fg_fan_has_beep[] = {
[f71808e] = 0,
+ [f71808a] = 0,
[f71858fg] = 0,
[f71862fg] = 1,
[f71869] = 1,
@@ -164,6 +169,7 @@
static const char f71882fg_nr_fans[] = {
[f71808e] = 3,
+ [f71808a] = 2, /* +1 fan which is monitor + simple pwm only */
[f71858fg] = 3,
[f71862fg] = 3,
[f71869] = 3,
@@ -171,12 +177,27 @@
[f71889fg] = 3,
[f71889ed] = 3,
[f71889a] = 3,
- [f8000] = 3,
+ [f8000] = 3, /* +1 fan which is monitor only */
[f81865f] = 2,
};
+static const char f71882fg_temp_has_beep[] = {
+ [f71808e] = 0,
+ [f71808a] = 1,
+ [f71858fg] = 0,
+ [f71862fg] = 1,
+ [f71869] = 1,
+ [f71882fg] = 1,
+ [f71889fg] = 1,
+ [f71889ed] = 1,
+ [f71889a] = 1,
+ [f8000] = 0,
+ [f81865f] = 1,
+};
+
static const char f71882fg_nr_temps[] = {
[f71808e] = 2,
+ [f71808a] = 2,
[f71858fg] = 3,
[f71862fg] = 3,
[f71869] = 3,
@@ -301,6 +322,10 @@
char *buf);
static ssize_t store_pwm(struct device *dev, struct device_attribute *devattr,
const char *buf, size_t count);
+static ssize_t show_simple_pwm(struct device *dev,
+ struct device_attribute *devattr, char *buf);
+static ssize_t store_simple_pwm(struct device *dev,
+ struct device_attribute *devattr, const char *buf, size_t count);
static ssize_t show_pwm_enable(struct device *dev,
struct device_attribute *devattr, char *buf);
static ssize_t store_pwm_enable(struct device *dev,
@@ -550,6 +575,14 @@
show_pwm_interpolate, store_pwm_interpolate, 0, 3),
} };
+/* Attr for the third fan of the f71808a, which only has manual pwm */
+static struct sensor_device_attribute_2 f71808a_fan3_attr[] = {
+ SENSOR_ATTR_2(fan3_input, S_IRUGO, show_fan, NULL, 0, 2),
+ SENSOR_ATTR_2(fan3_alarm, S_IRUGO, show_fan_alarm, NULL, 0, 2),
+ SENSOR_ATTR_2(pwm3, S_IRUGO|S_IWUSR,
+ show_simple_pwm, store_simple_pwm, 0, 2),
+};
+
/* Attr for models which can beep on Fan alarm */
static struct sensor_device_attribute_2 fxxxx_fan_beep_attr[] = {
SENSOR_ATTR_2(fan1_beep, S_IRUGO|S_IWUSR, show_fan_beep,
@@ -1146,12 +1179,13 @@
data->temp_type[3] = (reg & 0x08) ? 2 : 4;
}
- if (f71882fg_has_beep[data->type]) {
+ if (f71882fg_fan_has_beep[data->type])
data->fan_beep = f71882fg_read8(data,
F71882FG_REG_FAN_BEEP);
+
+ if (f71882fg_temp_has_beep[data->type])
data->temp_beep = f71882fg_read8(data,
F71882FG_REG_TEMP_BEEP);
- }
data->pwm_enable = f71882fg_read8(data,
F71882FG_REG_PWM_ENABLE);
@@ -1232,7 +1266,13 @@
data->pwm[nr] =
f71882fg_read8(data, F71882FG_REG_PWM(nr));
}
- /* The f8000 can monitor 1 more fan, but has no pwm for it */
+ /* Some models have 1 more fan with limited capabilities */
+ if (data->type == f71808a) {
+ data->fan[2] = f71882fg_read16(data,
+ F71882FG_REG_FAN(2));
+ data->pwm[2] = f71882fg_read8(data,
+ F71882FG_REG_PWM(2));
+ }
if (data->type == f8000)
data->fan[3] = f71882fg_read16(data,
F71882FG_REG_FAN(3));
@@ -1722,6 +1762,38 @@
return count;
}
+static ssize_t show_simple_pwm(struct device *dev,
+ struct device_attribute *devattr, char *buf)
+{
+ struct f71882fg_data *data = f71882fg_update_device(dev);
+ int val, nr = to_sensor_dev_attr_2(devattr)->index;
+
+ val = data->pwm[nr];
+ return sprintf(buf, "%d\n", val);
+}
+
+static ssize_t store_simple_pwm(struct device *dev,
+ struct device_attribute *devattr,
+ const char *buf, size_t count)
+{
+ struct f71882fg_data *data = dev_get_drvdata(dev);
+ int err, nr = to_sensor_dev_attr_2(devattr)->index;
+ long val;
+
+ err = strict_strtol(buf, 10, &val);
+ if (err)
+ return err;
+
+ val = SENSORS_LIMIT(val, 0, 255);
+
+ mutex_lock(&data->update_lock);
+ f71882fg_write8(data, F71882FG_REG_PWM(nr), val);
+ data->pwm[nr] = val;
+ mutex_unlock(&data->update_lock);
+
+ return count;
+}
+
static ssize_t show_pwm_enable(struct device *dev,
struct device_attribute *devattr, char *buf)
{
@@ -2140,7 +2212,7 @@
if (err)
goto exit_unregister_sysfs;
- if (f71882fg_has_beep[data->type]) {
+ if (f71882fg_temp_has_beep[data->type]) {
err = f71882fg_create_sysfs_files(pdev,
&fxxxx_temp_beep_attr[0][0],
ARRAY_SIZE(fxxxx_temp_beep_attr[0])
@@ -2169,6 +2241,7 @@
if (start_reg & 0x02) {
switch (data->type) {
case f71808e:
+ case f71808a:
case f71869:
/* These always have signed auto point temps */
data->auto_point_temp_signed = 1;
@@ -2221,7 +2294,7 @@
if (err)
goto exit_unregister_sysfs;
- if (f71882fg_has_beep[data->type]) {
+ if (f71882fg_fan_has_beep[data->type]) {
err = f71882fg_create_sysfs_files(pdev,
fxxxx_fan_beep_attr, nr_fans);
if (err)
@@ -2230,6 +2303,7 @@
switch (data->type) {
case f71808e:
+ case f71808a:
case f71869:
case f71889fg:
case f71889ed:
@@ -2255,6 +2329,16 @@
}
switch (data->type) {
+ case f71808a:
+ err = f71882fg_create_sysfs_files(pdev,
+ &fxxxx_auto_pwm_attr[0][0],
+ ARRAY_SIZE(fxxxx_auto_pwm_attr[0]) * nr_fans);
+ if (err)
+ goto exit_unregister_sysfs;
+ err = f71882fg_create_sysfs_files(pdev,
+ f71808a_fan3_attr,
+ ARRAY_SIZE(f71808a_fan3_attr));
+ break;
case f71862fg:
err = f71882fg_create_sysfs_files(pdev,
f71862fg_auto_pwm_attr,
@@ -2343,7 +2427,7 @@
&fxxxx_temp_attr[0][0],
ARRAY_SIZE(fxxxx_temp_attr[0]) * nr_temps);
}
- if (f71882fg_has_beep[data->type]) {
+ if (f71882fg_temp_has_beep[data->type]) {
f71882fg_remove_sysfs_files(pdev,
&fxxxx_temp_beep_attr[0][0],
ARRAY_SIZE(fxxxx_temp_beep_attr[0]) * nr_temps);
@@ -2366,12 +2450,20 @@
f71882fg_remove_sysfs_files(pdev, &fxxxx_fan_attr[0][0],
ARRAY_SIZE(fxxxx_fan_attr[0]) * nr_fans);
- if (f71882fg_has_beep[data->type]) {
+ if (f71882fg_fan_has_beep[data->type]) {
f71882fg_remove_sysfs_files(pdev,
fxxxx_fan_beep_attr, nr_fans);
}
switch (data->type) {
+ case f71808a:
+ f71882fg_remove_sysfs_files(pdev,
+ &fxxxx_auto_pwm_attr[0][0],
+ ARRAY_SIZE(fxxxx_auto_pwm_attr[0]) * nr_fans);
+ f71882fg_remove_sysfs_files(pdev,
+ f71808a_fan3_attr,
+ ARRAY_SIZE(f71808a_fan3_attr));
+ break;
case f71862fg:
f71882fg_remove_sysfs_files(pdev,
f71862fg_auto_pwm_attr,
@@ -2424,6 +2516,9 @@
case SIO_F71808E_ID:
sio_data->type = f71808e;
break;
+ case SIO_F71808A_ID:
+ sio_data->type = f71808a;
+ break;
case SIO_F71858_ID:
sio_data->type = f71858fg;
break;
diff --git a/drivers/hwmon/fam15h_power.c b/drivers/hwmon/fam15h_power.c
new file mode 100644
index 0000000..523f8fb
--- /dev/null
+++ b/drivers/hwmon/fam15h_power.c
@@ -0,0 +1,229 @@
+/*
+ * fam15h_power.c - AMD Family 15h processor power monitoring
+ *
+ * Copyright (c) 2011 Advanced Micro Devices, Inc.
+ * Author: Andreas Herrmann <andreas.herrmann3@amd.com>
+ *
+ *
+ * This driver is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License; either
+ * version 2 of the License, or (at your option) any later version.
+ *
+ * This driver is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ * See the GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this driver; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/err.h>
+#include <linux/hwmon.h>
+#include <linux/hwmon-sysfs.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/bitops.h>
+#include <asm/processor.h>
+
+MODULE_DESCRIPTION("AMD Family 15h CPU processor power monitor");
+MODULE_AUTHOR("Andreas Herrmann <andreas.herrmann3@amd.com>");
+MODULE_LICENSE("GPL");
+
+/* D18F3 */
+#define REG_NORTHBRIDGE_CAP 0xe8
+
+/* D18F4 */
+#define REG_PROCESSOR_TDP 0x1b8
+
+/* D18F5 */
+#define REG_TDP_RUNNING_AVERAGE 0xe0
+#define REG_TDP_LIMIT3 0xe8
+
+struct fam15h_power_data {
+ struct device *hwmon_dev;
+ unsigned int tdp_to_watts;
+ unsigned int base_tdp;
+ unsigned int processor_pwr_watts;
+};
+
+static ssize_t show_power(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ u32 val, tdp_limit, running_avg_range;
+ s32 running_avg_capture;
+ u64 curr_pwr_watts;
+ struct pci_dev *f4 = to_pci_dev(dev);
+ struct fam15h_power_data *data = dev_get_drvdata(dev);
+
+ pci_bus_read_config_dword(f4->bus, PCI_DEVFN(PCI_SLOT(f4->devfn), 5),
+ REG_TDP_RUNNING_AVERAGE, &val);
+ running_avg_capture = (val >> 4) & 0x3fffff;
+ running_avg_capture = sign_extend32(running_avg_capture, 22);
+ running_avg_range = val & 0xf;
+
+ pci_bus_read_config_dword(f4->bus, PCI_DEVFN(PCI_SLOT(f4->devfn), 5),
+ REG_TDP_LIMIT3, &val);
+
+ tdp_limit = val >> 16;
+ curr_pwr_watts = tdp_limit + data->base_tdp -
+ (s32)(running_avg_capture >> (running_avg_range + 1));
+ curr_pwr_watts *= data->tdp_to_watts;
+
+ /*
+ * Convert to microWatt
+ *
+ * power is in Watt provided as fixed point integer with
+ * scaling factor 1/(2^16). For conversion we use
+ * (10^6)/(2^16) = 15625/(2^10)
+ */
+ curr_pwr_watts = (curr_pwr_watts * 15625) >> 10;
+ return sprintf(buf, "%u\n", (unsigned int) curr_pwr_watts);
+}
+static DEVICE_ATTR(power1_input, S_IRUGO, show_power, NULL);
+
+static ssize_t show_power_crit(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct fam15h_power_data *data = dev_get_drvdata(dev);
+
+ return sprintf(buf, "%u\n", data->processor_pwr_watts);
+}
+static DEVICE_ATTR(power1_crit, S_IRUGO, show_power_crit, NULL);
+
+static ssize_t show_name(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "fam15h_power\n");
+}
+static DEVICE_ATTR(name, S_IRUGO, show_name, NULL);
+
+static struct attribute *fam15h_power_attrs[] = {
+ &dev_attr_power1_input.attr,
+ &dev_attr_power1_crit.attr,
+ &dev_attr_name.attr,
+ NULL
+};
+
+static const struct attribute_group fam15h_power_attr_group = {
+ .attrs = fam15h_power_attrs,
+};
+
+static bool __devinit fam15h_power_is_internal_node0(struct pci_dev *f4)
+{
+ u32 val;
+
+ pci_bus_read_config_dword(f4->bus, PCI_DEVFN(PCI_SLOT(f4->devfn), 3),
+ REG_NORTHBRIDGE_CAP, &val);
+ if ((val & BIT(29)) && ((val >> 30) & 3))
+ return false;
+
+ return true;
+}
+
+static void __devinit fam15h_power_init_data(struct pci_dev *f4,
+ struct fam15h_power_data *data)
+{
+ u32 val;
+ u64 tmp;
+
+ pci_read_config_dword(f4, REG_PROCESSOR_TDP, &val);
+ data->base_tdp = val >> 16;
+ tmp = val & 0xffff;
+
+ pci_bus_read_config_dword(f4->bus, PCI_DEVFN(PCI_SLOT(f4->devfn), 5),
+ REG_TDP_LIMIT3, &val);
+
+ data->tdp_to_watts = ((val & 0x3ff) << 6) | ((val >> 10) & 0x3f);
+ tmp *= data->tdp_to_watts;
+
+ /* result not allowed to be >= 256W */
+ if ((tmp >> 16) >= 256)
+ dev_warn(&f4->dev, "Bogus value for ProcessorPwrWatts "
+ "(processor_pwr_watts>=%u)\n",
+ (unsigned int) (tmp >> 16));
+
+ /* convert to microWatt */
+ data->processor_pwr_watts = (tmp * 15625) >> 10;
+}
+
+static int __devinit fam15h_power_probe(struct pci_dev *pdev,
+ const struct pci_device_id *id)
+{
+ struct fam15h_power_data *data;
+ struct device *dev;
+ int err;
+
+ if (!fam15h_power_is_internal_node0(pdev)) {
+ err = -ENODEV;
+ goto exit;
+ }
+
+ data = kzalloc(sizeof(struct fam15h_power_data), GFP_KERNEL);
+ if (!data) {
+ err = -ENOMEM;
+ goto exit;
+ }
+ fam15h_power_init_data(pdev, data);
+ dev = &pdev->dev;
+
+ dev_set_drvdata(dev, data);
+ err = sysfs_create_group(&dev->kobj, &fam15h_power_attr_group);
+ if (err)
+ goto exit_free_data;
+
+ data->hwmon_dev = hwmon_device_register(dev);
+ if (IS_ERR(data->hwmon_dev)) {
+ err = PTR_ERR(data->hwmon_dev);
+ goto exit_remove_group;
+ }
+
+ return 0;
+
+exit_remove_group:
+ sysfs_remove_group(&dev->kobj, &fam15h_power_attr_group);
+exit_free_data:
+ kfree(data);
+exit:
+ return err;
+}
+
+static void __devexit fam15h_power_remove(struct pci_dev *pdev)
+{
+ struct device *dev;
+ struct fam15h_power_data *data;
+
+ dev = &pdev->dev;
+ data = dev_get_drvdata(dev);
+ hwmon_device_unregister(data->hwmon_dev);
+ sysfs_remove_group(&dev->kobj, &fam15h_power_attr_group);
+ dev_set_drvdata(dev, NULL);
+ kfree(data);
+}
+
+static DEFINE_PCI_DEVICE_TABLE(fam15h_power_id_table) = {
+ { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F4) },
+ {}
+};
+MODULE_DEVICE_TABLE(pci, fam15h_power_id_table);
+
+static struct pci_driver fam15h_power_driver = {
+ .name = "fam15h_power",
+ .id_table = fam15h_power_id_table,
+ .probe = fam15h_power_probe,
+ .remove = __devexit_p(fam15h_power_remove),
+};
+
+static int __init fam15h_power_init(void)
+{
+ return pci_register_driver(&fam15h_power_driver);
+}
+
+static void __exit fam15h_power_exit(void)
+{
+ pci_unregister_driver(&fam15h_power_driver);
+}
+
+module_init(fam15h_power_init)
+module_exit(fam15h_power_exit)
diff --git a/drivers/hwmon/ibmaem.c b/drivers/hwmon/ibmaem.c
index bc6e2ab..537409d 100644
--- a/drivers/hwmon/ibmaem.c
+++ b/drivers/hwmon/ibmaem.c
@@ -523,7 +523,7 @@
aem_remove_sensors(data);
hwmon_device_unregister(data->hwmon_dev);
ipmi_destroy_user(data->ipmi.user);
- dev_set_drvdata(&data->pdev->dev, NULL);
+ platform_set_drvdata(data->pdev, NULL);
platform_device_unregister(data->pdev);
aem_idr_put(data->id);
kfree(data);
@@ -594,7 +594,7 @@
if (res)
goto ipmi_err;
- dev_set_drvdata(&data->pdev->dev, data);
+ platform_set_drvdata(data->pdev, data);
/* Set up IPMI interface */
if (aem_init_ipmi_data(&data->ipmi, probe->interface,
@@ -630,7 +630,7 @@
hwmon_reg_err:
ipmi_destroy_user(data->ipmi.user);
ipmi_err:
- dev_set_drvdata(&data->pdev->dev, NULL);
+ platform_set_drvdata(data->pdev, NULL);
platform_device_unregister(data->pdev);
dev_err:
aem_idr_put(data->id);
@@ -727,7 +727,7 @@
if (res)
goto ipmi_err;
- dev_set_drvdata(&data->pdev->dev, data);
+ platform_set_drvdata(data->pdev, data);
/* Set up IPMI interface */
if (aem_init_ipmi_data(&data->ipmi, probe->interface,
@@ -763,7 +763,7 @@
hwmon_reg_err:
ipmi_destroy_user(data->ipmi.user);
ipmi_err:
- dev_set_drvdata(&data->pdev->dev, NULL);
+ platform_set_drvdata(data->pdev, NULL);
platform_device_unregister(data->pdev);
dev_err:
aem_idr_put(data->id);
diff --git a/drivers/hwmon/it87.c b/drivers/hwmon/it87.c
index 316b648..bb6405b 100644
--- a/drivers/hwmon/it87.c
+++ b/drivers/hwmon/it87.c
@@ -77,15 +77,13 @@
#define DEVID 0x20 /* Register: Device ID */
#define DEVREV 0x22 /* Register: Device Revision */
-static inline int
-superio_inb(int reg)
+static inline int superio_inb(int reg)
{
outb(reg, REG);
return inb(VAL);
}
-static inline void
-superio_outb(int reg, int val)
+static inline void superio_outb(int reg, int val)
{
outb(reg, REG);
outb(val, VAL);
@@ -101,27 +99,32 @@
return val;
}
-static inline void
-superio_select(int ldn)
+static inline void superio_select(int ldn)
{
outb(DEV, REG);
outb(ldn, VAL);
}
-static inline void
-superio_enter(void)
+static inline int superio_enter(void)
{
+ /*
+ * Try to reserve REG and REG + 1 for exclusive access.
+ */
+ if (!request_muxed_region(REG, 2, DRVNAME))
+ return -EBUSY;
+
outb(0x87, REG);
outb(0x01, REG);
outb(0x55, REG);
outb(0x55, REG);
+ return 0;
}
-static inline void
-superio_exit(void)
+static inline void superio_exit(void)
{
outb(0x02, REG);
outb(0x02, VAL);
+ release_region(REG, 2);
}
/* Logical device 4 registers */
@@ -1542,11 +1545,15 @@
static int __init it87_find(unsigned short *address,
struct it87_sio_data *sio_data)
{
- int err = -ENODEV;
+ int err;
u16 chip_type;
const char *board_vendor, *board_name;
- superio_enter();
+ err = superio_enter();
+ if (err)
+ return err;
+
+ err = -ENODEV;
chip_type = force_id ? force_id : superio_inw(DEVID);
switch (chip_type) {
diff --git a/drivers/hwmon/jc42.c b/drivers/hwmon/jc42.c
index 9349912..02cebb7 100644
--- a/drivers/hwmon/jc42.c
+++ b/drivers/hwmon/jc42.c
@@ -213,7 +213,7 @@
/* This is the driver that will be inserted */
static struct i2c_driver jc42_driver = {
- .class = I2C_CLASS_HWMON,
+ .class = I2C_CLASS_SPD,
.driver = {
.name = "jc42",
.pm = JC42_DEV_PM_OPS,
diff --git a/drivers/hwmon/k10temp.c b/drivers/hwmon/k10temp.c
index 82bf65a..41aa6a3 100644
--- a/drivers/hwmon/k10temp.c
+++ b/drivers/hwmon/k10temp.c
@@ -1,5 +1,5 @@
/*
- * k10temp.c - AMD Family 10h/11h/12h/14h processor hardware monitoring
+ * k10temp.c - AMD Family 10h/11h/12h/14h/15h processor hardware monitoring
*
* Copyright (c) 2009 Clemens Ladisch <clemens@ladisch.de>
*
@@ -25,7 +25,7 @@
#include <linux/pci.h>
#include <asm/processor.h>
-MODULE_DESCRIPTION("AMD Family 10h/11h/12h/14h CPU core temperature monitor");
+MODULE_DESCRIPTION("AMD Family 10h+ CPU core temperature monitor");
MODULE_AUTHOR("Clemens Ladisch <clemens@ladisch.de>");
MODULE_LICENSE("GPL");
@@ -173,7 +173,7 @@
err = PTR_ERR(hwmon_dev);
goto exit_remove;
}
- dev_set_drvdata(&pdev->dev, hwmon_dev);
+ pci_set_drvdata(pdev, hwmon_dev);
if (unreliable && force)
dev_warn(&pdev->dev,
@@ -194,7 +194,7 @@
static void __devexit k10temp_remove(struct pci_dev *pdev)
{
- hwmon_device_unregister(dev_get_drvdata(&pdev->dev));
+ hwmon_device_unregister(pci_get_drvdata(pdev));
device_remove_file(&pdev->dev, &dev_attr_name);
device_remove_file(&pdev->dev, &dev_attr_temp1_input);
device_remove_file(&pdev->dev, &dev_attr_temp1_max);
@@ -202,13 +202,14 @@
&sensor_dev_attr_temp1_crit.dev_attr);
device_remove_file(&pdev->dev,
&sensor_dev_attr_temp1_crit_hyst.dev_attr);
- dev_set_drvdata(&pdev->dev, NULL);
+ pci_set_drvdata(pdev, NULL);
}
static const struct pci_device_id k10temp_id_table[] = {
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_10H_NB_MISC) },
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_11H_NB_MISC) },
{ PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CNB17H_F3) },
+ { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_15H_NB_F3) },
{}
};
MODULE_DEVICE_TABLE(pci, k10temp_id_table);
diff --git a/drivers/hwmon/k8temp.c b/drivers/hwmon/k8temp.c
index 418496f..b923bc2 100644
--- a/drivers/hwmon/k8temp.c
+++ b/drivers/hwmon/k8temp.c
@@ -252,7 +252,7 @@
data->name = "k8temp";
mutex_init(&data->update_lock);
- dev_set_drvdata(&pdev->dev, data);
+ pci_set_drvdata(pdev, data);
/* Register sysfs hooks */
err = device_create_file(&pdev->dev,
@@ -307,7 +307,7 @@
&sensor_dev_attr_temp4_input.dev_attr);
device_remove_file(&pdev->dev, &dev_attr_name);
exit_free:
- dev_set_drvdata(&pdev->dev, NULL);
+ pci_set_drvdata(pdev, NULL);
kfree(data);
exit:
return err;
@@ -315,7 +315,7 @@
static void __devexit k8temp_remove(struct pci_dev *pdev)
{
- struct k8temp_data *data = dev_get_drvdata(&pdev->dev);
+ struct k8temp_data *data = pci_get_drvdata(pdev);
hwmon_device_unregister(data->hwmon_dev);
device_remove_file(&pdev->dev,
@@ -327,7 +327,7 @@
device_remove_file(&pdev->dev,
&sensor_dev_attr_temp4_input.dev_attr);
device_remove_file(&pdev->dev, &dev_attr_name);
- dev_set_drvdata(&pdev->dev, NULL);
+ pci_set_drvdata(pdev, NULL);
kfree(data);
}
diff --git a/drivers/hwmon/lm70.c b/drivers/hwmon/lm70.c
index 3b84fb5..c274ea2 100644
--- a/drivers/hwmon/lm70.c
+++ b/drivers/hwmon/lm70.c
@@ -58,7 +58,7 @@
int status, val = 0;
u8 rxbuf[2];
s16 raw=0;
- struct lm70 *p_lm70 = dev_get_drvdata(&spi->dev);
+ struct lm70 *p_lm70 = spi_get_drvdata(spi);
if (mutex_lock_interruptible(&p_lm70->lock))
return -ERESTARTSYS;
@@ -163,7 +163,7 @@
status = PTR_ERR(p_lm70->hwmon_dev);
goto out_dev_reg_failed;
}
- dev_set_drvdata(&spi->dev, p_lm70);
+ spi_set_drvdata(spi, p_lm70);
if ((status = device_create_file(&spi->dev, &dev_attr_temp1_input))
|| (status = device_create_file(&spi->dev, &dev_attr_name))) {
@@ -177,19 +177,19 @@
device_remove_file(&spi->dev, &dev_attr_temp1_input);
hwmon_device_unregister(p_lm70->hwmon_dev);
out_dev_reg_failed:
- dev_set_drvdata(&spi->dev, NULL);
+ spi_set_drvdata(spi, NULL);
kfree(p_lm70);
return status;
}
static int __devexit lm70_remove(struct spi_device *spi)
{
- struct lm70 *p_lm70 = dev_get_drvdata(&spi->dev);
+ struct lm70 *p_lm70 = spi_get_drvdata(spi);
device_remove_file(&spi->dev, &dev_attr_temp1_input);
device_remove_file(&spi->dev, &dev_attr_name);
hwmon_device_unregister(p_lm70->hwmon_dev);
- dev_set_drvdata(&spi->dev, NULL);
+ spi_set_drvdata(spi, NULL);
kfree(p_lm70);
return 0;
diff --git a/drivers/hwmon/max6650.c b/drivers/hwmon/max6650.c
index 9a11532..ece3aaf 100644
--- a/drivers/hwmon/max6650.c
+++ b/drivers/hwmon/max6650.c
@@ -41,13 +41,6 @@
#include <linux/err.h>
/*
- * Addresses to scan. There are four disjoint possibilities, by pin config.
- */
-
-static const unsigned short normal_i2c[] = {0x1b, 0x1f, 0x48, 0x4b,
- I2C_CLIENT_END};
-
-/*
* Insmod parameters
*/
@@ -114,8 +107,6 @@
static int max6650_probe(struct i2c_client *client,
const struct i2c_device_id *id);
-static int max6650_detect(struct i2c_client *client,
- struct i2c_board_info *info);
static int max6650_init_client(struct i2c_client *client);
static int max6650_remove(struct i2c_client *client);
static struct max6650_data *max6650_update_device(struct device *dev);
@@ -125,21 +116,19 @@
*/
static const struct i2c_device_id max6650_id[] = {
- { "max6650", 0 },
+ { "max6650", 1 },
+ { "max6651", 4 },
{ }
};
MODULE_DEVICE_TABLE(i2c, max6650_id);
static struct i2c_driver max6650_driver = {
- .class = I2C_CLASS_HWMON,
.driver = {
.name = "max6650",
},
.probe = max6650_probe,
.remove = max6650_remove,
.id_table = max6650_id,
- .detect = max6650_detect,
- .address_list = normal_i2c,
};
/*
@@ -150,6 +139,7 @@
{
struct device *hwmon_dev;
struct mutex update_lock;
+ int nr_fans;
char valid; /* zero until following fields are valid */
unsigned long last_updated; /* in jiffies */
@@ -501,9 +491,6 @@
static struct attribute *max6650_attrs[] = {
&sensor_dev_attr_fan1_input.dev_attr.attr,
- &sensor_dev_attr_fan2_input.dev_attr.attr,
- &sensor_dev_attr_fan3_input.dev_attr.attr,
- &sensor_dev_attr_fan4_input.dev_attr.attr,
&dev_attr_fan1_target.attr,
&dev_attr_fan1_div.attr,
&dev_attr_pwm1_enable.attr,
@@ -521,42 +508,21 @@
.is_visible = max6650_attrs_visible,
};
+static struct attribute *max6651_attrs[] = {
+ &sensor_dev_attr_fan2_input.dev_attr.attr,
+ &sensor_dev_attr_fan3_input.dev_attr.attr,
+ &sensor_dev_attr_fan4_input.dev_attr.attr,
+ NULL
+};
+
+static const struct attribute_group max6651_attr_grp = {
+ .attrs = max6651_attrs,
+};
+
/*
* Real code
*/
-/* Return 0 if detection is successful, -ENODEV otherwise */
-static int max6650_detect(struct i2c_client *client,
- struct i2c_board_info *info)
-{
- struct i2c_adapter *adapter = client->adapter;
- int address = client->addr;
-
- dev_dbg(&adapter->dev, "max6650_detect called\n");
-
- if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) {
- dev_dbg(&adapter->dev, "max6650: I2C bus doesn't support "
- "byte read mode, skipping.\n");
- return -ENODEV;
- }
-
- if (((i2c_smbus_read_byte_data(client, MAX6650_REG_CONFIG) & 0xC0)
- ||(i2c_smbus_read_byte_data(client, MAX6650_REG_GPIO_STAT) & 0xE0)
- ||(i2c_smbus_read_byte_data(client, MAX6650_REG_ALARM_EN) & 0xE0)
- ||(i2c_smbus_read_byte_data(client, MAX6650_REG_ALARM) & 0xE0)
- ||(i2c_smbus_read_byte_data(client, MAX6650_REG_COUNT) & 0xFC))) {
- dev_dbg(&adapter->dev,
- "max6650: detection failed at 0x%02x.\n", address);
- return -ENODEV;
- }
-
- dev_info(&adapter->dev, "max6650: chip found at 0x%02x.\n", address);
-
- strlcpy(info->type, "max6650", I2C_NAME_SIZE);
-
- return 0;
-}
-
static int max6650_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
@@ -570,6 +536,7 @@
i2c_set_clientdata(client, data);
mutex_init(&data->update_lock);
+ data->nr_fans = id->driver_data;
/*
* Initialize the max6650 chip
@@ -581,6 +548,12 @@
err = sysfs_create_group(&client->dev.kobj, &max6650_attr_grp);
if (err)
goto err_free;
+ /* 3 additional fan inputs for the MAX6651 */
+ if (data->nr_fans == 4) {
+ err = sysfs_create_group(&client->dev.kobj, &max6651_attr_grp);
+ if (err)
+ goto err_remove;
+ }
data->hwmon_dev = hwmon_device_register(&client->dev);
if (!IS_ERR(data->hwmon_dev))
@@ -588,6 +561,9 @@
err = PTR_ERR(data->hwmon_dev);
dev_err(&client->dev, "error registering hwmon device.\n");
+ if (data->nr_fans == 4)
+ sysfs_remove_group(&client->dev.kobj, &max6651_attr_grp);
+err_remove:
sysfs_remove_group(&client->dev.kobj, &max6650_attr_grp);
err_free:
kfree(data);
@@ -598,8 +574,10 @@
{
struct max6650_data *data = i2c_get_clientdata(client);
- sysfs_remove_group(&client->dev.kobj, &max6650_attr_grp);
hwmon_device_unregister(data->hwmon_dev);
+ if (data->nr_fans == 4)
+ sysfs_remove_group(&client->dev.kobj, &max6651_attr_grp);
+ sysfs_remove_group(&client->dev.kobj, &max6650_attr_grp);
kfree(data);
return 0;
}
@@ -712,7 +690,7 @@
MAX6650_REG_SPEED);
data->config = i2c_smbus_read_byte_data(client,
MAX6650_REG_CONFIG);
- for (i = 0; i < 4; i++) {
+ for (i = 0; i < data->nr_fans; i++) {
data->tach[i] = i2c_smbus_read_byte_data(client,
tach_reg[i]);
}
diff --git a/drivers/hwmon/sch5627.c b/drivers/hwmon/sch5627.c
index 9a51dcc..020c872 100644
--- a/drivers/hwmon/sch5627.c
+++ b/drivers/hwmon/sch5627.c
@@ -52,6 +52,9 @@
#define SCH5627_COMPANY_ID 0x5c
#define SCH5627_PRIMARY_ID 0xa0
+#define SCH5627_CMD_READ 0x02
+#define SCH5627_CMD_WRITE 0x03
+
#define SCH5627_REG_BUILD_CODE 0x39
#define SCH5627_REG_BUILD_ID 0x3a
#define SCH5627_REG_HWMON_ID 0x3c
@@ -94,11 +97,13 @@
struct sch5627_data {
unsigned short addr;
struct device *hwmon_dev;
+ u8 control;
u8 temp_max[SCH5627_NO_TEMPS];
u8 temp_crit[SCH5627_NO_TEMPS];
u16 fan_min[SCH5627_NO_FANS];
struct mutex update_lock;
+ unsigned long last_battery; /* In jiffies */
char valid; /* !=0 if following fields are valid */
unsigned long last_updated; /* In jiffies */
u16 temp[SCH5627_NO_TEMPS];
@@ -140,7 +145,7 @@
release_region(base, 2);
}
-static int sch5627_read_virtual_reg(struct sch5627_data *data, u16 reg)
+static int sch5627_send_cmd(struct sch5627_data *data, u8 cmd, u16 reg, u8 v)
{
u8 val;
int i;
@@ -163,10 +168,14 @@
outb(0x80, data->addr + 3);
/* Write Request Packet Header */
- outb(0x02, data->addr + 4); /* Access Type: VREG read */
+ outb(cmd, data->addr + 4); /* VREG Access Type read:0x02 write:0x03 */
outb(0x01, data->addr + 5); /* # of Entries: 1 Byte (8-bit) */
outb(0x04, data->addr + 2); /* Mailbox AP to first data entry loc. */
+ /* Write Value field */
+ if (cmd == SCH5627_CMD_WRITE)
+ outb(v, data->addr + 4);
+
/* Write Address field */
outb(reg & 0xff, data->addr + 6);
outb(reg >> 8, data->addr + 7);
@@ -224,8 +233,22 @@
* But if we do that things don't work, so let's not.
*/
- /* Read Data from Mailbox */
- return inb(data->addr + 4);
+ /* Read Value field */
+ if (cmd == SCH5627_CMD_READ)
+ return inb(data->addr + 4);
+
+ return 0;
+}
+
+static int sch5627_read_virtual_reg(struct sch5627_data *data, u16 reg)
+{
+ return sch5627_send_cmd(data, SCH5627_CMD_READ, reg, 0);
+}
+
+static int sch5627_write_virtual_reg(struct sch5627_data *data,
+ u16 reg, u8 val)
+{
+ return sch5627_send_cmd(data, SCH5627_CMD_WRITE, reg, val);
}
static int sch5627_read_virtual_reg16(struct sch5627_data *data, u16 reg)
@@ -272,6 +295,13 @@
mutex_lock(&data->update_lock);
+ /* Trigger a Vbat voltage measurement every 5 minutes */
+ if (time_after(jiffies, data->last_battery + 300 * HZ)) {
+ sch5627_write_virtual_reg(data, SCH5627_REG_CTRL,
+ data->control | 0x10);
+ data->last_battery = jiffies;
+ }
+
/* Cache the values for 1 second */
if (time_after(jiffies, data->last_updated + HZ) || !data->valid) {
for (i = 0; i < SCH5627_NO_TEMPS; i++) {
@@ -696,11 +726,17 @@
err = val;
goto error;
}
- if (!(val & 0x01)) {
+ data->control = val;
+ if (!(data->control & 0x01)) {
pr_err("hardware monitoring not enabled\n");
err = -ENODEV;
goto error;
}
+ /* Trigger a Vbat voltage measurement, so that we get a valid reading
+ the first time we read Vbat */
+ sch5627_write_virtual_reg(data, SCH5627_REG_CTRL,
+ data->control | 0x10);
+ data->last_battery = jiffies;
/*
* Read limits, we do this only once as reading a register on
diff --git a/drivers/hwmon/ultra45_env.c b/drivers/hwmon/ultra45_env.c
index 1f36c63..27a6271 100644
--- a/drivers/hwmon/ultra45_env.c
+++ b/drivers/hwmon/ultra45_env.c
@@ -258,7 +258,7 @@
goto out_sysfs_remove_group;
}
- dev_set_drvdata(&op->dev, p);
+ platform_set_drvdata(op, p);
err = 0;
out:
@@ -277,7 +277,7 @@
static int __devexit env_remove(struct platform_device *op)
{
- struct env *p = dev_get_drvdata(&op->dev);
+ struct env *p = platform_get_drvdata(op);
if (p) {
sysfs_remove_group(&op->dev.kobj, &env_group);
diff --git a/drivers/i2c/busses/Kconfig b/drivers/i2c/busses/Kconfig
index 326652f..646068e 100644
--- a/drivers/i2c/busses/Kconfig
+++ b/drivers/i2c/busses/Kconfig
@@ -79,6 +79,7 @@
config I2C_I801
tristate "Intel 82801 (ICH/PCH)"
depends on PCI
+ select CHECK_SIGNATURE if X86 && DMI
help
If you say yes to this option, support will be included for the Intel
801 family of mainboard I2C interfaces. Specifically, the following
@@ -101,6 +102,7 @@
6 Series (PCH)
Patsburg (PCH)
DH89xxCC (PCH)
+ Panther Point (PCH)
This driver can also be built as a module. If so, the module
will be called i2c-i801.
@@ -671,15 +673,19 @@
will be called xilinx_i2c.
config I2C_EG20T
- tristate "Intel EG20T PCH/OKI SEMICONDUCTOR ML7213 IOH"
+ tristate "Intel EG20T PCH / OKI SEMICONDUCTOR IOH(ML7213/ML7223)"
depends on PCI
help
This driver is for PCH(Platform controller Hub) I2C of EG20T which
is an IOH(Input/Output Hub) for x86 embedded processor.
This driver can access PCH I2C bus device.
- This driver also supports the ML7213, a companion chip for the
- Atom E6xx series and compatible with the Intel EG20T PCH.
+ This driver also can be used for OKI SEMICONDUCTOR IOH(Input/
+ Output Hub), ML7213 and ML7223.
+ ML7213 IOH is for IVI(In-Vehicle Infotainment) use and ML7223 IOH is
+ for MP(Media Phone) use.
+ ML7213/ML7223 is companion chip for Intel Atom E6xx series.
+ ML7213/ML7223 is completely compatible for Intel EG20T PCH.
comment "External I2C/SMBus adapter drivers"
diff --git a/drivers/i2c/busses/i2c-eg20t.c b/drivers/i2c/busses/i2c-eg20t.c
index 878a120..8abfa4a 100644
--- a/drivers/i2c/busses/i2c-eg20t.c
+++ b/drivers/i2c/busses/i2c-eg20t.c
@@ -182,10 +182,12 @@
/* Definition for ML7213 by OKI SEMICONDUCTOR */
#define PCI_VENDOR_ID_ROHM 0x10DB
#define PCI_DEVICE_ID_ML7213_I2C 0x802D
+#define PCI_DEVICE_ID_ML7223_I2C 0x8010
static struct pci_device_id __devinitdata pch_pcidev_id[] = {
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PCH_I2C), 1, },
{ PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7213_I2C), 2, },
+ { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ML7223_I2C), 1, },
{0,}
};
diff --git a/drivers/i2c/busses/i2c-i801.c b/drivers/i2c/busses/i2c-i801.c
index 455e909..ab26840d 100644
--- a/drivers/i2c/busses/i2c-i801.c
+++ b/drivers/i2c/busses/i2c-i801.c
@@ -50,6 +50,7 @@
Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes
Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes
DH89xxCC (PCH) 0x2330 32 hard yes yes yes
+ Panther Point (PCH) 0x1e22 32 hard yes yes yes
Features supported by this driver:
Software PEC no
@@ -141,6 +142,7 @@
#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70
#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71
#define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22
#define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330
#define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
@@ -158,6 +160,8 @@
#define FEATURE_BLOCK_BUFFER (1 << 1)
#define FEATURE_BLOCK_PROC (1 << 2)
#define FEATURE_I2C_BLOCK_READ (1 << 3)
+/* Not really a feature, but it's convenient to handle it as such */
+#define FEATURE_IDF (1 << 15)
static const char *i801_feature_names[] = {
"SMBus PEC",
@@ -628,12 +632,13 @@
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
+ { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
{ 0, }
};
MODULE_DEVICE_TABLE(pci, i801_ids);
-#if defined CONFIG_INPUT_APANEL || defined CONFIG_INPUT_APANEL_MODULE
+#if defined CONFIG_X86 && defined CONFIG_DMI
static unsigned char apanel_addr;
/* Scan the system ROM for the signature "FJKEYINF" */
@@ -663,11 +668,7 @@
}
iounmap(bios);
}
-#else
-static void __init input_apanel_init(void) {}
-#endif
-#if defined CONFIG_SENSORS_FSCHMD || defined CONFIG_SENSORS_FSCHMD_MODULE
struct dmi_onboard_device_info {
const char *name;
u8 type;
@@ -733,7 +734,30 @@
dmi_check_onboard_device(type, name, adap);
}
}
-#endif
+
+/* Register optional slaves */
+static void __devinit i801_probe_optional_slaves(struct i801_priv *priv)
+{
+ /* Only register slaves on main SMBus channel */
+ if (priv->features & FEATURE_IDF)
+ return;
+
+ if (apanel_addr) {
+ struct i2c_board_info info;
+
+ memset(&info, 0, sizeof(struct i2c_board_info));
+ info.addr = apanel_addr;
+ strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
+ i2c_new_device(&priv->adapter, &info);
+ }
+
+ if (dmi_name_in_vendors("FUJITSU"))
+ dmi_walk(dmi_check_onboard_devices, &priv->adapter);
+}
+#else
+static void __init input_apanel_init(void) {}
+static void __devinit i801_probe_optional_slaves(struct i801_priv *priv) {}
+#endif /* CONFIG_X86 && CONFIG_DMI */
static int __devinit i801_probe(struct pci_dev *dev,
const struct pci_device_id *id)
@@ -753,6 +777,11 @@
priv->pci_dev = dev;
switch (dev->device) {
+ case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
+ case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
+ case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
+ priv->features |= FEATURE_IDF;
+ /* fall through */
default:
priv->features |= FEATURE_I2C_BLOCK_READ;
/* fall through */
@@ -838,21 +867,7 @@
goto exit_release;
}
- /* Register optional slaves */
-#if defined CONFIG_INPUT_APANEL || defined CONFIG_INPUT_APANEL_MODULE
- if (apanel_addr) {
- struct i2c_board_info info;
-
- memset(&info, 0, sizeof(struct i2c_board_info));
- info.addr = apanel_addr;
- strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
- i2c_new_device(&priv->adapter, &info);
- }
-#endif
-#if defined CONFIG_SENSORS_FSCHMD || defined CONFIG_SENSORS_FSCHMD_MODULE
- if (dmi_name_in_vendors("FUJITSU"))
- dmi_walk(dmi_check_onboard_devices, &priv->adapter);
-#endif
+ i801_probe_optional_slaves(priv);
pci_set_drvdata(dev, priv);
return 0;
@@ -912,7 +927,8 @@
static int __init i2c_i801_init(void)
{
- input_apanel_init();
+ if (dmi_name_in_vendors("FUJITSU"))
+ input_apanel_init();
return pci_register_driver(&i801_driver);
}
diff --git a/drivers/i2c/busses/i2c-nomadik.c b/drivers/i2c/busses/i2c-nomadik.c
index e10e5cf..0c731ca 100644
--- a/drivers/i2c/busses/i2c-nomadik.c
+++ b/drivers/i2c/busses/i2c-nomadik.c
@@ -15,13 +15,14 @@
#include <linux/init.h>
#include <linux/module.h>
#include <linux/platform_device.h>
-#include <linux/delay.h>
#include <linux/slab.h>
#include <linux/interrupt.h>
#include <linux/i2c.h>
#include <linux/err.h>
#include <linux/clk.h>
#include <linux/io.h>
+#include <linux/regulator/consumer.h>
+#include <linux/pm_runtime.h>
#include <plat/i2c.h>
@@ -103,9 +104,6 @@
/* maximum threshold value */
#define MAX_I2C_FIFO_THRESHOLD 15
-/* per-transfer delay, required for the hardware to stabilize */
-#define I2C_DELAY 150
-
enum i2c_status {
I2C_NOP,
I2C_ON_GOING,
@@ -120,9 +118,6 @@
I2C_READ = 0x01
};
-/* controller response timeout in ms */
-#define I2C_TIMEOUT_MS 2000
-
/**
* struct i2c_nmk_client - client specific data
* @slave_adr: 7-bit slave address
@@ -151,6 +146,7 @@
* @stop: stop condition
* @xfer_complete: acknowledge completion for a I2C message
* @result: controller propogated result
+ * @busy: Busy doing transfer
*/
struct nmk_i2c_dev {
struct platform_device *pdev;
@@ -163,6 +159,8 @@
int stop;
struct completion xfer_complete;
int result;
+ struct regulator *regulator;
+ bool busy;
};
/* controller's abort causes */
@@ -209,7 +207,7 @@
writel((I2C_CR_FTX | I2C_CR_FRX), dev->virtbase + I2C_CR);
for (i = 0; i < LOOP_ATTEMPTS; i++) {
- timeout = jiffies + msecs_to_jiffies(I2C_TIMEOUT_MS);
+ timeout = jiffies + dev->adap.timeout;
while (!time_after(jiffies, timeout)) {
if ((readl(dev->virtbase + I2C_CR) &
@@ -253,11 +251,9 @@
{
int stat;
- clk_enable(dev->clk);
-
stat = flush_i2c_fifo(dev);
if (stat)
- return stat;
+ goto exit;
/* disable the controller */
i2c_clr_bit(dev->virtbase + I2C_CR , I2C_CR_PE);
@@ -268,10 +264,8 @@
dev->cli.operation = I2C_NO_OPERATION;
- clk_disable(dev->clk);
-
- udelay(I2C_DELAY);
- return 0;
+exit:
+ return stat;
}
/* enable peripheral, master mode operation */
@@ -424,7 +418,7 @@
dev->virtbase + I2C_IMSCR);
timeout = wait_for_completion_interruptible_timeout(
- &dev->xfer_complete, msecs_to_jiffies(I2C_TIMEOUT_MS));
+ &dev->xfer_complete, dev->adap.timeout);
if (timeout < 0) {
dev_err(&dev->pdev->dev,
@@ -434,14 +428,32 @@
}
if (timeout == 0) {
- /* controller has timedout, re-init the h/w */
- dev_err(&dev->pdev->dev, "controller timed out, re-init h/w\n");
- (void) init_hw(dev);
+ /* Controller timed out */
+ dev_err(&dev->pdev->dev, "read from slave 0x%x timed out\n",
+ dev->cli.slave_adr);
status = -ETIMEDOUT;
}
return status;
}
+static void fill_tx_fifo(struct nmk_i2c_dev *dev, int no_bytes)
+{
+ int count;
+
+ for (count = (no_bytes - 2);
+ (count > 0) &&
+ (dev->cli.count != 0);
+ count--) {
+ /* write to the Tx FIFO */
+ writeb(*dev->cli.buffer,
+ dev->virtbase + I2C_TFR);
+ dev->cli.buffer++;
+ dev->cli.count--;
+ dev->cli.xfer_bytes++;
+ }
+
+}
+
/**
* write_i2c() - Write data to I2C client.
* @dev: private data of I2C Driver
@@ -469,8 +481,13 @@
init_completion(&dev->xfer_complete);
/* enable interrupts by settings the masks */
- irq_mask = (I2C_IT_TXFNE | I2C_IT_TXFOVR |
- I2C_IT_MAL | I2C_IT_BERR);
+ irq_mask = (I2C_IT_TXFOVR | I2C_IT_MAL | I2C_IT_BERR);
+
+ /* Fill the TX FIFO with transmit data */
+ fill_tx_fifo(dev, MAX_I2C_FIFO_THRESHOLD);
+
+ if (dev->cli.count != 0)
+ irq_mask |= I2C_IT_TXFNE;
/*
* check if we want to transfer a single or multiple bytes, if so
@@ -488,7 +505,7 @@
dev->virtbase + I2C_IMSCR);
timeout = wait_for_completion_interruptible_timeout(
- &dev->xfer_complete, msecs_to_jiffies(I2C_TIMEOUT_MS));
+ &dev->xfer_complete, dev->adap.timeout);
if (timeout < 0) {
dev_err(&dev->pdev->dev,
@@ -498,9 +515,9 @@
}
if (timeout == 0) {
- /* controller has timedout, re-init the h/w */
- dev_err(&dev->pdev->dev, "controller timed out, re-init h/w\n");
- (void) init_hw(dev);
+ /* Controller timed out */
+ dev_err(&dev->pdev->dev, "write to slave 0x%x timed out\n",
+ dev->cli.slave_adr);
status = -ETIMEDOUT;
}
@@ -508,6 +525,51 @@
}
/**
+ * nmk_i2c_xfer_one() - transmit a single I2C message
+ * @dev: device with a message encoded into it
+ * @flags: message flags
+ */
+static int nmk_i2c_xfer_one(struct nmk_i2c_dev *dev, u16 flags)
+{
+ int status;
+
+ if (flags & I2C_M_RD) {
+ /* read operation */
+ dev->cli.operation = I2C_READ;
+ status = read_i2c(dev);
+ } else {
+ /* write operation */
+ dev->cli.operation = I2C_WRITE;
+ status = write_i2c(dev);
+ }
+
+ if (status || (dev->result)) {
+ u32 i2c_sr;
+ u32 cause;
+
+ i2c_sr = readl(dev->virtbase + I2C_SR);
+ /*
+ * Check if the controller I2C operation status
+ * is set to ABORT(11b).
+ */
+ if (((i2c_sr >> 2) & 0x3) == 0x3) {
+ /* get the abort cause */
+ cause = (i2c_sr >> 4) & 0x7;
+ dev_err(&dev->pdev->dev, "%s\n", cause
+ >= ARRAY_SIZE(abort_causes) ?
+ "unknown reason" :
+ abort_causes[cause]);
+ }
+
+ (void) init_hw(dev);
+
+ status = status ? status : dev->result;
+ }
+
+ return status;
+}
+
+/**
* nmk_i2c_xfer() - I2C transfer function used by kernel framework
* @i2c_adap: Adapter pointer to the controller
* @msgs: Pointer to data to be written.
@@ -559,53 +621,55 @@
{
int status;
int i;
- u32 cause;
struct nmk_i2c_dev *dev = i2c_get_adapdata(i2c_adap);
+ int j;
- status = init_hw(dev);
- if (status)
- return status;
+ dev->busy = true;
+
+ if (dev->regulator)
+ regulator_enable(dev->regulator);
+ pm_runtime_get_sync(&dev->pdev->dev);
clk_enable(dev->clk);
- /* setup the i2c controller */
- setup_i2c_controller(dev);
+ status = init_hw(dev);
+ if (status)
+ goto out;
- for (i = 0; i < num_msgs; i++) {
- if (unlikely(msgs[i].flags & I2C_M_TEN)) {
- dev_err(&dev->pdev->dev, "10 bit addressing"
- "not supported\n");
- return -EINVAL;
- }
- dev->cli.slave_adr = msgs[i].addr;
- dev->cli.buffer = msgs[i].buf;
- dev->cli.count = msgs[i].len;
- dev->stop = (i < (num_msgs - 1)) ? 0 : 1;
- dev->result = 0;
+ /* Attempt three times to send the message queue */
+ for (j = 0; j < 3; j++) {
+ /* setup the i2c controller */
+ setup_i2c_controller(dev);
- if (msgs[i].flags & I2C_M_RD) {
- /* it is a read operation */
- dev->cli.operation = I2C_READ;
- status = read_i2c(dev);
- } else {
- /* write operation */
- dev->cli.operation = I2C_WRITE;
- status = write_i2c(dev);
+ for (i = 0; i < num_msgs; i++) {
+ if (unlikely(msgs[i].flags & I2C_M_TEN)) {
+ dev_err(&dev->pdev->dev, "10 bit addressing"
+ "not supported\n");
+
+ status = -EINVAL;
+ goto out;
+ }
+ dev->cli.slave_adr = msgs[i].addr;
+ dev->cli.buffer = msgs[i].buf;
+ dev->cli.count = msgs[i].len;
+ dev->stop = (i < (num_msgs - 1)) ? 0 : 1;
+ dev->result = 0;
+
+ status = nmk_i2c_xfer_one(dev, msgs[i].flags);
+ if (status != 0)
+ break;
}
- if (status || (dev->result)) {
- /* get the abort cause */
- cause = (readl(dev->virtbase + I2C_SR) >> 4) & 0x7;
- dev_err(&dev->pdev->dev, "error during I2C"
- "message xfer: %d\n", cause);
- dev_err(&dev->pdev->dev, "%s\n",
- cause >= ARRAY_SIZE(abort_causes)
- ? "unknown reason" : abort_causes[cause]);
- clk_disable(dev->clk);
- return status;
- }
- udelay(I2C_DELAY);
+ if (status == 0)
+ break;
}
+
+out:
clk_disable(dev->clk);
+ pm_runtime_put_sync(&dev->pdev->dev);
+ if (dev->regulator)
+ regulator_disable(dev->regulator);
+
+ dev->busy = false;
/* return the no. messages processed */
if (status)
@@ -666,17 +730,7 @@
*/
disable_interrupts(dev, I2C_IT_TXFNE);
} else {
- for (count = (MAX_I2C_FIFO_THRESHOLD - tft - 2);
- (count > 0) &&
- (dev->cli.count != 0);
- count--) {
- /* write to the Tx FIFO */
- writeb(*dev->cli.buffer,
- dev->virtbase + I2C_TFR);
- dev->cli.buffer++;
- dev->cli.count--;
- dev->cli.xfer_bytes++;
- }
+ fill_tx_fifo(dev, (MAX_I2C_FIFO_THRESHOLD - tft));
/*
* if done, close the transfer by disabling the
* corresponding TXFNE interrupt
@@ -729,16 +783,11 @@
}
}
- i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_MTD);
- i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_MTDWS);
-
- disable_interrupts(dev,
- (I2C_IT_TXFNE | I2C_IT_TXFE | I2C_IT_TXFF
- | I2C_IT_TXFOVR | I2C_IT_RXFNF
- | I2C_IT_RXFF | I2C_IT_RXFE));
+ disable_all_interrupts(dev);
+ clear_all_interrupts(dev);
if (dev->cli.count) {
- dev->result = -1;
+ dev->result = -EIO;
dev_err(&dev->pdev->dev, "%lu bytes still remain to be"
"xfered\n", dev->cli.count);
(void) init_hw(dev);
@@ -749,7 +798,7 @@
/* Master Arbitration lost interrupt */
case I2C_IT_MAL:
- dev->result = -1;
+ dev->result = -EIO;
(void) init_hw(dev);
i2c_set_bit(dev->virtbase + I2C_ICR, I2C_IT_MAL);
@@ -763,7 +812,7 @@
* during the transaction.
*/
case I2C_IT_BERR:
- dev->result = -1;
+ dev->result = -EIO;
/* get the status */
if (((readl(dev->virtbase + I2C_SR) >> 2) & 0x3) == I2C_ABORT)
(void) init_hw(dev);
@@ -779,7 +828,7 @@
* the Tx FIFO is full.
*/
case I2C_IT_TXFOVR:
- dev->result = -1;
+ dev->result = -EIO;
(void) init_hw(dev);
dev_err(&dev->pdev->dev, "Tx Fifo Over run\n");
@@ -805,6 +854,38 @@
return IRQ_HANDLED;
}
+
+#ifdef CONFIG_PM
+static int nmk_i2c_suspend(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct nmk_i2c_dev *nmk_i2c = platform_get_drvdata(pdev);
+
+ if (nmk_i2c->busy)
+ return -EBUSY;
+
+ return 0;
+}
+
+static int nmk_i2c_resume(struct device *dev)
+{
+ return 0;
+}
+#else
+#define nmk_i2c_suspend NULL
+#define nmk_i2c_resume NULL
+#endif
+
+/*
+ * We use noirq so that we suspend late and resume before the wakeup interrupt
+ * to ensure that we do the !pm_runtime_suspended() check in resume before
+ * there has been a regular pm runtime resume (via pm_runtime_get_sync()).
+ */
+static const struct dev_pm_ops nmk_i2c_pm = {
+ .suspend_noirq = nmk_i2c_suspend,
+ .resume_noirq = nmk_i2c_resume,
+};
+
static unsigned int nmk_i2c_functionality(struct i2c_adapter *adap)
{
return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
@@ -830,7 +911,7 @@
ret = -ENOMEM;
goto err_no_mem;
}
-
+ dev->busy = false;
dev->pdev = pdev;
platform_set_drvdata(pdev, dev);
@@ -860,6 +941,15 @@
goto err_irq;
}
+ dev->regulator = regulator_get(&pdev->dev, "v-i2c");
+ if (IS_ERR(dev->regulator)) {
+ dev_warn(&pdev->dev, "could not get i2c regulator\n");
+ dev->regulator = NULL;
+ }
+
+ pm_suspend_ignore_children(&pdev->dev, true);
+ pm_runtime_enable(&pdev->dev);
+
dev->clk = clk_get(&pdev->dev, NULL);
if (IS_ERR(dev->clk)) {
dev_err(&pdev->dev, "could not get i2c clock\n");
@@ -872,6 +962,8 @@
adap->owner = THIS_MODULE;
adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
adap->algo = &nmk_i2c_algo;
+ adap->timeout = pdata->timeout ? msecs_to_jiffies(pdata->timeout) :
+ msecs_to_jiffies(20000);
snprintf(adap->name, sizeof(adap->name),
"Nomadik I2C%d at %lx", pdev->id, (unsigned long)res->start);
@@ -887,12 +979,6 @@
i2c_set_adapdata(adap, dev);
- ret = init_hw(dev);
- if (ret != 0) {
- dev_err(&pdev->dev, "error in initializing i2c hardware\n");
- goto err_init_hw;
- }
-
dev_info(&pdev->dev, "initialize %s on virtual "
"base %p\n", adap->name, dev->virtbase);
@@ -904,10 +990,12 @@
return 0;
- err_init_hw:
err_add_adap:
clk_put(dev->clk);
err_no_clk:
+ if (dev->regulator)
+ regulator_put(dev->regulator);
+ pm_runtime_disable(&pdev->dev);
free_irq(dev->irq, dev);
err_irq:
iounmap(dev->virtbase);
@@ -938,6 +1026,9 @@
if (res)
release_mem_region(res->start, resource_size(res));
clk_put(dev->clk);
+ if (dev->regulator)
+ regulator_put(dev->regulator);
+ pm_runtime_disable(&pdev->dev);
platform_set_drvdata(pdev, NULL);
kfree(dev);
@@ -948,6 +1039,7 @@
.driver = {
.owner = THIS_MODULE,
.name = DRIVER_NAME,
+ .pm = &nmk_i2c_pm,
},
.probe = nmk_i2c_probe,
.remove = __devexit_p(nmk_i2c_remove),
diff --git a/drivers/i2c/busses/i2c-parport-light.c b/drivers/i2c/busses/i2c-parport-light.c
index fc5fbd1..4b95f7a 100644
--- a/drivers/i2c/busses/i2c-parport-light.c
+++ b/drivers/i2c/busses/i2c-parport-light.c
@@ -2,13 +2,13 @@
* i2c-parport-light.c I2C bus over parallel port *
* ------------------------------------------------------------------------ *
Copyright (C) 2003-2010 Jean Delvare <khali@linux-fr.org>
-
+
Based on older i2c-velleman.c driver
Copyright (C) 1995-2000 Simon G. Vogl
With some changes from:
Frodo Looijaard <frodol@dds.nl>
Kyösti Mälkki <kmalkki@cc.hut.fi>
-
+
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
@@ -114,7 +114,7 @@
.getscl = parport_getscl,
.udelay = 50,
.timeout = HZ,
-};
+};
/* ----- Driver registration ---------------------------------------------- */
@@ -132,7 +132,7 @@
static struct i2c_client *ara;
static struct lineop parport_ctrl_irq = {
.val = (1 << 4),
- .port = CTRL,
+ .port = PORT_CTRL,
};
static int __devinit i2c_parport_probe(struct platform_device *pdev)
@@ -245,7 +245,7 @@
if (irq != 0)
pr_info(DRVNAME ": using irq %d\n", irq);
- if (!adapter_parm[type].getscl.val)
+ if (!adapter_parm[type].getscl.val)
parport_algo_data.getscl = NULL;
/* Sets global pdev as a side effect */
diff --git a/drivers/i2c/busses/i2c-parport.c b/drivers/i2c/busses/i2c-parport.c
index 2dbba16..2456568 100644
--- a/drivers/i2c/busses/i2c-parport.c
+++ b/drivers/i2c/busses/i2c-parport.c
@@ -2,13 +2,13 @@
* i2c-parport.c I2C bus over parallel port *
* ------------------------------------------------------------------------ *
Copyright (C) 2003-2011 Jean Delvare <khali@linux-fr.org>
-
+
Based on older i2c-philips-par.c driver
Copyright (C) 1995-2000 Simon G. Vogl
With some changes from:
Frodo Looijaard <frodol@dds.nl>
Kyösti Mälkki <kmalkki@cc.hut.fi>
-
+
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
@@ -78,13 +78,13 @@
return parport_read_control(p);
}
-static void (*port_write[])(struct parport *, unsigned char) = {
+static void (* const port_write[])(struct parport *, unsigned char) = {
port_write_data,
NULL,
port_write_control,
};
-static unsigned char (*port_read[])(struct parport *) = {
+static unsigned char (* const port_read[])(struct parport *) = {
port_read_data,
port_read_status,
port_read_control,
@@ -147,7 +147,7 @@
.getscl = parport_getscl,
.udelay = 10, /* ~50 kbps */
.timeout = HZ,
-};
+};
/* ----- I2c and parallel port call-back functions and structures --------- */
@@ -164,10 +164,10 @@
"SMBus alert received but no ARA client!\n");
}
-static void i2c_parport_attach (struct parport *port)
+static void i2c_parport_attach(struct parport *port)
{
struct i2c_par *adapter;
-
+
adapter = kzalloc(sizeof(struct i2c_par), GFP_KERNEL);
if (adapter == NULL) {
printk(KERN_ERR "i2c-parport: Failed to kzalloc\n");
@@ -180,7 +180,7 @@
NULL, NULL, i2c_parport_irq, PARPORT_FLAG_EXCL, adapter);
if (!adapter->pdev) {
printk(KERN_ERR "i2c-parport: Unable to register with parport\n");
- goto ERROR0;
+ goto err_free;
}
/* Fill the rest of the structure */
@@ -200,7 +200,7 @@
if (parport_claim_or_block(adapter->pdev) < 0) {
printk(KERN_ERR "i2c-parport: Could not claim parallel port\n");
- goto ERROR1;
+ goto err_unregister;
}
/* Reset hardware to a sane state (SCL and SDA high) */
@@ -215,7 +215,7 @@
if (i2c_bit_add_bus(&adapter->adapter) < 0) {
printk(KERN_ERR "i2c-parport: Unable to register with I2C\n");
- goto ERROR1;
+ goto err_unregister;
}
/* Setup SMBus alert if supported */
@@ -234,16 +234,16 @@
mutex_lock(&adapter_list_lock);
list_add_tail(&adapter->node, &adapter_list);
mutex_unlock(&adapter_list_lock);
- return;
+ return;
-ERROR1:
+ err_unregister:
parport_release(adapter->pdev);
parport_unregister_device(adapter->pdev);
-ERROR0:
+ err_free:
kfree(adapter);
}
-static void i2c_parport_detach (struct parport *port)
+static void i2c_parport_detach(struct parport *port)
{
struct i2c_par *adapter, *_n;
@@ -260,7 +260,7 @@
/* Un-init if needed (power off...) */
if (adapter_parm[type].init.val)
line_set(port, 0, &adapter_parm[type].init);
-
+
parport_release(adapter->pdev);
parport_unregister_device(adapter->pdev);
list_del(&adapter->node);
diff --git a/drivers/i2c/busses/i2c-parport.h b/drivers/i2c/busses/i2c-parport.h
index a9f6681..3fe6523 100644
--- a/drivers/i2c/busses/i2c-parport.h
+++ b/drivers/i2c/busses/i2c-parport.h
@@ -2,7 +2,7 @@
* i2c-parport.h I2C bus over parallel port *
* ------------------------------------------------------------------------ *
Copyright (C) 2003-2010 Jean Delvare <khali@linux-fr.org>
-
+
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License, or
@@ -18,13 +18,9 @@
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
* ------------------------------------------------------------------------ */
-#ifdef DATA
-#undef DATA
-#endif
-
-#define DATA 0
-#define STAT 1
-#define CTRL 2
+#define PORT_DATA 0
+#define PORT_STAT 1
+#define PORT_CTRL 2
struct lineop {
u8 val;
@@ -41,61 +37,61 @@
unsigned int smbus_alert:1;
};
-static struct adapter_parm adapter_parm[] = {
+static const struct adapter_parm adapter_parm[] = {
/* type 0: Philips adapter */
{
- .setsda = { 0x80, DATA, 1 },
- .setscl = { 0x08, CTRL, 0 },
- .getsda = { 0x80, STAT, 0 },
- .getscl = { 0x08, STAT, 0 },
+ .setsda = { 0x80, PORT_DATA, 1 },
+ .setscl = { 0x08, PORT_CTRL, 0 },
+ .getsda = { 0x80, PORT_STAT, 0 },
+ .getscl = { 0x08, PORT_STAT, 0 },
},
/* type 1: home brew teletext adapter */
{
- .setsda = { 0x02, DATA, 0 },
- .setscl = { 0x01, DATA, 0 },
- .getsda = { 0x80, STAT, 1 },
+ .setsda = { 0x02, PORT_DATA, 0 },
+ .setscl = { 0x01, PORT_DATA, 0 },
+ .getsda = { 0x80, PORT_STAT, 1 },
},
/* type 2: Velleman K8000 adapter */
{
- .setsda = { 0x02, CTRL, 1 },
- .setscl = { 0x08, CTRL, 1 },
- .getsda = { 0x10, STAT, 0 },
+ .setsda = { 0x02, PORT_CTRL, 1 },
+ .setscl = { 0x08, PORT_CTRL, 1 },
+ .getsda = { 0x10, PORT_STAT, 0 },
},
/* type 3: ELV adapter */
{
- .setsda = { 0x02, DATA, 1 },
- .setscl = { 0x01, DATA, 1 },
- .getsda = { 0x40, STAT, 1 },
- .getscl = { 0x08, STAT, 1 },
+ .setsda = { 0x02, PORT_DATA, 1 },
+ .setscl = { 0x01, PORT_DATA, 1 },
+ .getsda = { 0x40, PORT_STAT, 1 },
+ .getscl = { 0x08, PORT_STAT, 1 },
},
/* type 4: ADM1032 evaluation board */
{
- .setsda = { 0x02, DATA, 1 },
- .setscl = { 0x01, DATA, 1 },
- .getsda = { 0x10, STAT, 1 },
- .init = { 0xf0, DATA, 0 },
+ .setsda = { 0x02, PORT_DATA, 1 },
+ .setscl = { 0x01, PORT_DATA, 1 },
+ .getsda = { 0x10, PORT_STAT, 1 },
+ .init = { 0xf0, PORT_DATA, 0 },
.smbus_alert = 1,
},
/* type 5: ADM1025, ADM1030 and ADM1031 evaluation boards */
{
- .setsda = { 0x02, DATA, 1 },
- .setscl = { 0x01, DATA, 1 },
- .getsda = { 0x10, STAT, 1 },
+ .setsda = { 0x02, PORT_DATA, 1 },
+ .setscl = { 0x01, PORT_DATA, 1 },
+ .getsda = { 0x10, PORT_STAT, 1 },
},
/* type 6: Barco LPT->DVI (K5800236) adapter */
{
- .setsda = { 0x02, DATA, 1 },
- .setscl = { 0x01, DATA, 1 },
- .getsda = { 0x20, STAT, 0 },
- .getscl = { 0x40, STAT, 0 },
- .init = { 0xfc, DATA, 0 },
+ .setsda = { 0x02, PORT_DATA, 1 },
+ .setscl = { 0x01, PORT_DATA, 1 },
+ .getsda = { 0x20, PORT_STAT, 0 },
+ .getscl = { 0x40, PORT_STAT, 0 },
+ .init = { 0xfc, PORT_DATA, 0 },
},
/* type 7: One For All JP1 parallel port adapter */
{
- .setsda = { 0x01, DATA, 0 },
- .setscl = { 0x02, DATA, 0 },
- .getsda = { 0x80, STAT, 1 },
- .init = { 0x04, DATA, 1 },
+ .setsda = { 0x01, PORT_DATA, 0 },
+ .setscl = { 0x02, PORT_DATA, 0 },
+ .getsda = { 0x80, PORT_STAT, 1 },
+ .init = { 0x04, PORT_DATA, 1 },
},
};
diff --git a/drivers/i2c/busses/i2c-sh_mobile.c b/drivers/i2c/busses/i2c-sh_mobile.c
index 2707f5e..f633a53 100644
--- a/drivers/i2c/busses/i2c-sh_mobile.c
+++ b/drivers/i2c/busses/i2c-sh_mobile.c
@@ -32,6 +32,7 @@
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/slab.h>
+#include <linux/i2c/i2c-sh_mobile.h>
/* Transmit operation: */
/* */
@@ -117,7 +118,7 @@
struct device *dev;
void __iomem *reg;
struct i2c_adapter adap;
-
+ unsigned long bus_speed;
struct clk *clk;
u_int8_t icic;
u_int8_t iccl;
@@ -205,7 +206,7 @@
* We also round off the result.
*/
num = i2c_clk * 5;
- denom = NORMAL_SPEED * 9;
+ denom = pd->bus_speed * 9;
tmp = num * 10 / denom;
if (tmp % 10 >= 5)
pd->iccl = (u_int8_t)((num/denom) + 1);
@@ -574,10 +575,10 @@
static int sh_mobile_i2c_probe(struct platform_device *dev)
{
+ struct i2c_sh_mobile_platform_data *pdata = dev->dev.platform_data;
struct sh_mobile_i2c_data *pd;
struct i2c_adapter *adap;
struct resource *res;
- char clk_name[8];
int size;
int ret;
@@ -587,10 +588,9 @@
return -ENOMEM;
}
- snprintf(clk_name, sizeof(clk_name), "i2c%d", dev->id);
- pd->clk = clk_get(&dev->dev, clk_name);
+ pd->clk = clk_get(&dev->dev, NULL);
if (IS_ERR(pd->clk)) {
- dev_err(&dev->dev, "cannot get clock \"%s\"\n", clk_name);
+ dev_err(&dev->dev, "cannot get clock\n");
ret = PTR_ERR(pd->clk);
goto err;
}
@@ -620,6 +620,11 @@
goto err_irq;
}
+ /* Use platformd data bus speed or NORMAL_SPEED */
+ pd->bus_speed = NORMAL_SPEED;
+ if (pdata && pdata->bus_speed)
+ pd->bus_speed = pdata->bus_speed;
+
/* The IIC blocks on SH-Mobile ARM processors
* come with two new bits in ICIC.
*/
@@ -660,6 +665,8 @@
goto err_all;
}
+ dev_info(&dev->dev, "I2C adapter %d with bus speed %lu Hz\n",
+ adap->nr, pd->bus_speed);
return 0;
err_all:
@@ -729,3 +736,4 @@
MODULE_DESCRIPTION("SuperH Mobile I2C Bus Controller driver");
MODULE_AUTHOR("Magnus Damm");
MODULE_LICENSE("GPL v2");
+MODULE_ALIAS("platform:i2c-sh_mobile");
diff --git a/drivers/i2c/busses/i2c-tegra.c b/drivers/i2c/busses/i2c-tegra.c
index b4ab39b..4d93196 100644
--- a/drivers/i2c/busses/i2c-tegra.c
+++ b/drivers/i2c/busses/i2c-tegra.c
@@ -35,8 +35,10 @@
#define BYTES_PER_FIFO_WORD 4
#define I2C_CNFG 0x000
+#define I2C_CNFG_DEBOUNCE_CNT_SHIFT 12
#define I2C_CNFG_PACKET_MODE_EN (1<<10)
#define I2C_CNFG_NEW_MASTER_FSM (1<<11)
+#define I2C_STATUS 0x01C
#define I2C_SL_CNFG 0x020
#define I2C_SL_CNFG_NEWSL (1<<2)
#define I2C_SL_ADDR1 0x02c
@@ -77,6 +79,7 @@
#define I2C_ERR_NONE 0x00
#define I2C_ERR_NO_ACK 0x01
#define I2C_ERR_ARBITRATION_LOST 0x02
+#define I2C_ERR_UNKNOWN_INTERRUPT 0x04
#define PACKET_HEADER0_HEADER_SIZE_SHIFT 28
#define PACKET_HEADER0_PACKET_ID_SHIFT 16
@@ -121,6 +124,7 @@
void __iomem *base;
int cont_id;
int irq;
+ bool irq_disabled;
int is_dvc;
struct completion msg_complete;
int msg_err;
@@ -325,11 +329,17 @@
if (i2c_dev->is_dvc)
tegra_dvc_init(i2c_dev);
- val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN;
+ val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN |
+ (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT);
i2c_writel(i2c_dev, val, I2C_CNFG);
i2c_writel(i2c_dev, 0, I2C_INT_MASK);
clk_set_rate(i2c_dev->clk, i2c_dev->bus_clk_rate * 8);
+ if (!i2c_dev->is_dvc) {
+ u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);
+ i2c_writel(i2c_dev, sl_cfg | I2C_SL_CNFG_NEWSL, I2C_SL_CNFG);
+ }
+
val = 7 << I2C_FIFO_CONTROL_TX_TRIG_SHIFT |
0 << I2C_FIFO_CONTROL_RX_TRIG_SHIFT;
i2c_writel(i2c_dev, val, I2C_FIFO_CONTROL);
@@ -338,6 +348,12 @@
err = -ETIMEDOUT;
clk_disable(i2c_dev->clk);
+
+ if (i2c_dev->irq_disabled) {
+ i2c_dev->irq_disabled = 0;
+ enable_irq(i2c_dev->irq);
+ }
+
return err;
}
@@ -350,8 +366,19 @@
status = i2c_readl(i2c_dev, I2C_INT_STATUS);
if (status == 0) {
- dev_warn(i2c_dev->dev, "interrupt with no status\n");
- return IRQ_NONE;
+ dev_warn(i2c_dev->dev, "irq status 0 %08x %08x %08x\n",
+ i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS),
+ i2c_readl(i2c_dev, I2C_STATUS),
+ i2c_readl(i2c_dev, I2C_CNFG));
+ i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
+
+ if (!i2c_dev->irq_disabled) {
+ disable_irq_nosync(i2c_dev->irq);
+ i2c_dev->irq_disabled = 1;
+ }
+
+ complete(&i2c_dev->msg_complete);
+ goto err;
}
if (unlikely(status & status_err)) {
@@ -391,6 +418,8 @@
I2C_INT_PACKET_XFER_COMPLETE | I2C_INT_TX_FIFO_DATA_REQ |
I2C_INT_RX_FIFO_DATA_REQ);
i2c_writel(i2c_dev, status, I2C_INT_STATUS);
+ if (i2c_dev->is_dvc)
+ dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
return IRQ_HANDLED;
}
@@ -424,12 +453,12 @@
packet_header = msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT;
packet_header |= I2C_HEADER_IE_ENABLE;
+ if (!stop)
+ packet_header |= I2C_HEADER_REPEAT_START;
if (msg->flags & I2C_M_TEN)
packet_header |= I2C_HEADER_10BIT_ADDR;
if (msg->flags & I2C_M_IGNORE_NAK)
packet_header |= I2C_HEADER_CONT_ON_NAK;
- if (msg->flags & I2C_M_NOSTART)
- packet_header |= I2C_HEADER_REPEAT_START;
if (msg->flags & I2C_M_RD)
packet_header |= I2C_HEADER_READ;
i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
diff --git a/drivers/ide/ide-cd.c b/drivers/ide/ide-cd.c
index a5ec5a7..6e5123b 100644
--- a/drivers/ide/ide-cd.c
+++ b/drivers/ide/ide-cd.c
@@ -1781,7 +1781,8 @@
ide_cd_read_toc(drive, &sense);
g->fops = &idecd_ops;
- g->flags |= GENHD_FL_REMOVABLE;
+ g->flags |= GENHD_FL_REMOVABLE | GENHD_FL_BLOCK_EVENTS_ON_EXCL_WRITE;
+ g->events = DISK_EVENT_MEDIA_CHANGE;
add_disk(g);
return 0;
diff --git a/drivers/ide/ide-cs.c b/drivers/ide/ide-cs.c
index 404843e..d2f3db3 100644
--- a/drivers/ide/ide-cs.c
+++ b/drivers/ide/ide-cs.c
@@ -272,7 +272,7 @@
} /* ide_release */
-static struct pcmcia_device_id ide_ids[] = {
+static const struct pcmcia_device_id ide_ids[] = {
PCMCIA_DEVICE_FUNC_ID(4),
PCMCIA_DEVICE_MANF_CARD(0x0000, 0x0000), /* Corsair */
PCMCIA_DEVICE_MANF_CARD(0x0007, 0x0000), /* Hitachi */
diff --git a/drivers/input/evdev.c b/drivers/input/evdev.c
index 88d8e4c..be0921e 100644
--- a/drivers/input/evdev.c
+++ b/drivers/input/evdev.c
@@ -41,6 +41,7 @@
struct evdev_client {
unsigned int head;
unsigned int tail;
+ unsigned int packet_head; /* [future] position of the first element of next packet */
spinlock_t buffer_lock; /* protects access to buffer, head and tail */
struct fasync_struct *fasync;
struct evdev *evdev;
@@ -72,12 +73,16 @@
client->buffer[client->tail].type = EV_SYN;
client->buffer[client->tail].code = SYN_DROPPED;
client->buffer[client->tail].value = 0;
+
+ client->packet_head = client->tail;
+ }
+
+ if (event->type == EV_SYN && event->code == SYN_REPORT) {
+ client->packet_head = client->head;
+ kill_fasync(&client->fasync, SIGIO, POLL_IN);
}
spin_unlock(&client->buffer_lock);
-
- if (event->type == EV_SYN)
- kill_fasync(&client->fasync, SIGIO, POLL_IN);
}
/*
@@ -159,7 +164,6 @@
return error;
rcu_assign_pointer(evdev->grab, client);
- synchronize_rcu();
return 0;
}
@@ -182,7 +186,6 @@
spin_lock(&evdev->client_lock);
list_add_tail_rcu(&client->node, &evdev->client_list);
spin_unlock(&evdev->client_lock);
- synchronize_rcu();
}
static void evdev_detach_client(struct evdev *evdev,
@@ -387,12 +390,12 @@
if (count < input_event_size())
return -EINVAL;
- if (client->head == client->tail && evdev->exist &&
+ if (client->packet_head == client->tail && evdev->exist &&
(file->f_flags & O_NONBLOCK))
return -EAGAIN;
retval = wait_event_interruptible(evdev->wait,
- client->head != client->tail || !evdev->exist);
+ client->packet_head != client->tail || !evdev->exist);
if (retval)
return retval;
@@ -421,7 +424,7 @@
poll_wait(file, &evdev->wait, wait);
mask = evdev->exist ? POLLOUT | POLLWRNORM : POLLHUP | POLLERR;
- if (client->head != client->tail)
+ if (client->packet_head != client->tail)
mask |= POLLIN | POLLRDNORM;
return mask;
diff --git a/drivers/input/input-compat.h b/drivers/input/input-compat.h
index 4d8ea32..22be27b 100644
--- a/drivers/input/input-compat.h
+++ b/drivers/input/input-compat.h
@@ -19,7 +19,7 @@
/* Note to the author of this code: did it ever occur to
you why the ifdefs are needed? Think about it again. -AK */
-#ifdef CONFIG_X86_64
+#if defined(CONFIG_X86_64) || defined(CONFIG_TILE)
# define INPUT_COMPAT_TEST is_compat_task()
#elif defined(CONFIG_S390)
# define INPUT_COMPAT_TEST test_thread_flag(TIF_31BIT)
diff --git a/drivers/input/input-polldev.c b/drivers/input/input-polldev.c
index 3037842..b1aabde 100644
--- a/drivers/input/input-polldev.c
+++ b/drivers/input/input-polldev.c
@@ -13,6 +13,7 @@
#include <linux/jiffies.h>
#include <linux/slab.h>
#include <linux/mutex.h>
+#include <linux/workqueue.h>
#include <linux/input-polldev.h>
MODULE_AUTHOR("Dmitry Torokhov <dtor@mail.ru>");
@@ -20,44 +21,6 @@
MODULE_LICENSE("GPL v2");
MODULE_VERSION("0.1");
-static DEFINE_MUTEX(polldev_mutex);
-static int polldev_users;
-static struct workqueue_struct *polldev_wq;
-
-static int input_polldev_start_workqueue(void)
-{
- int retval;
-
- retval = mutex_lock_interruptible(&polldev_mutex);
- if (retval)
- return retval;
-
- if (!polldev_users) {
- polldev_wq = create_singlethread_workqueue("ipolldevd");
- if (!polldev_wq) {
- pr_err("failed to create ipolldevd workqueue\n");
- retval = -ENOMEM;
- goto out;
- }
- }
-
- polldev_users++;
-
- out:
- mutex_unlock(&polldev_mutex);
- return retval;
-}
-
-static void input_polldev_stop_workqueue(void)
-{
- mutex_lock(&polldev_mutex);
-
- if (!--polldev_users)
- destroy_workqueue(polldev_wq);
-
- mutex_unlock(&polldev_mutex);
-}
-
static void input_polldev_queue_work(struct input_polled_dev *dev)
{
unsigned long delay;
@@ -66,7 +29,7 @@
if (delay >= HZ)
delay = round_jiffies_relative(delay);
- queue_delayed_work(polldev_wq, &dev->work, delay);
+ queue_delayed_work(system_freezable_wq, &dev->work, delay);
}
static void input_polled_device_work(struct work_struct *work)
@@ -81,18 +44,13 @@
static int input_open_polled_device(struct input_dev *input)
{
struct input_polled_dev *dev = input_get_drvdata(input);
- int error;
-
- error = input_polldev_start_workqueue();
- if (error)
- return error;
if (dev->open)
dev->open(dev);
/* Only start polling if polling is enabled */
if (dev->poll_interval > 0)
- queue_delayed_work(polldev_wq, &dev->work, 0);
+ queue_delayed_work(system_freezable_wq, &dev->work, 0);
return 0;
}
@@ -102,13 +60,6 @@
struct input_polled_dev *dev = input_get_drvdata(input);
cancel_delayed_work_sync(&dev->work);
- /*
- * Clean up work struct to remove references to the workqueue.
- * It may be destroyed by the next call. This causes problems
- * at next device open-close in case of poll_interval == 0.
- */
- INIT_DELAYED_WORK(&dev->work, dev->work.work.func);
- input_polldev_stop_workqueue();
if (dev->close)
dev->close(dev);
@@ -295,4 +246,3 @@
input_unregister_device(dev->input);
}
EXPORT_SYMBOL(input_unregister_polled_device);
-
diff --git a/drivers/input/input.c b/drivers/input/input.c
index ebbceed..75e11c7 100644
--- a/drivers/input/input.c
+++ b/drivers/input/input.c
@@ -451,7 +451,6 @@
}
rcu_assign_pointer(dev->grab, handle);
- synchronize_rcu();
out:
mutex_unlock(&dev->mutex);
diff --git a/drivers/input/joydev.c b/drivers/input/joydev.c
index 5688b5c..c24ec2d 100644
--- a/drivers/input/joydev.c
+++ b/drivers/input/joydev.c
@@ -180,7 +180,6 @@
spin_lock(&joydev->client_lock);
list_add_tail_rcu(&client->node, &joydev->client_list);
spin_unlock(&joydev->client_lock);
- synchronize_rcu();
}
static void joydev_detach_client(struct joydev *joydev,
diff --git a/drivers/input/keyboard/Kconfig b/drivers/input/keyboard/Kconfig
index b16bed0..69badb4 100644
--- a/drivers/input/keyboard/Kconfig
+++ b/drivers/input/keyboard/Kconfig
@@ -32,6 +32,16 @@
To compile this driver as a module, choose M here: the
module will be called adp5588-keys.
+config KEYBOARD_ADP5589
+ tristate "ADP5589 I2C QWERTY Keypad and IO Expander"
+ depends on I2C
+ help
+ Say Y here if you want to use a ADP5589 attached to your
+ system I2C bus.
+
+ To compile this driver as a module, choose M here: the
+ module will be called adp5589-keys.
+
config KEYBOARD_AMIGA
tristate "Amiga keyboard"
depends on AMIGA
@@ -325,6 +335,18 @@
To compile this driver as a module, choose M here: the
module will be called mcs_touchkey.
+config KEYBOARD_MPR121
+ tristate "Freescale MPR121 Touchkey"
+ depends on I2C
+ help
+ Say Y here if you have Freescale MPR121 touchkey controller
+ chip in your system.
+
+ If unsure, say N.
+
+ To compile this driver as a module, choose M here: the
+ module will be called mpr121_touchkey.
+
config KEYBOARD_IMX
tristate "IMX keypad support"
depends on ARCH_MXC
diff --git a/drivers/input/keyboard/Makefile b/drivers/input/keyboard/Makefile
index 878e6c2..c49cf8e 100644
--- a/drivers/input/keyboard/Makefile
+++ b/drivers/input/keyboard/Makefile
@@ -6,6 +6,7 @@
obj-$(CONFIG_KEYBOARD_ADP5520) += adp5520-keys.o
obj-$(CONFIG_KEYBOARD_ADP5588) += adp5588-keys.o
+obj-$(CONFIG_KEYBOARD_ADP5589) += adp5589-keys.o
obj-$(CONFIG_KEYBOARD_AMIGA) += amikbd.o
obj-$(CONFIG_KEYBOARD_ATARI) += atakbd.o
obj-$(CONFIG_KEYBOARD_ATKBD) += atkbd.o
@@ -27,6 +28,7 @@
obj-$(CONFIG_KEYBOARD_MATRIX) += matrix_keypad.o
obj-$(CONFIG_KEYBOARD_MAX7359) += max7359_keypad.o
obj-$(CONFIG_KEYBOARD_MCS) += mcs_touchkey.o
+obj-$(CONFIG_KEYBOARD_MPR121) += mpr121_touchkey.o
obj-$(CONFIG_KEYBOARD_NEWTON) += newtonkbd.o
obj-$(CONFIG_KEYBOARD_NOMADIK) += nomadik-ske-keypad.o
obj-$(CONFIG_KEYBOARD_OMAP) += omap-keypad.o
diff --git a/drivers/input/keyboard/adp5589-keys.c b/drivers/input/keyboard/adp5589-keys.c
new file mode 100644
index 0000000..6315986
--- /dev/null
+++ b/drivers/input/keyboard/adp5589-keys.c
@@ -0,0 +1,771 @@
+/*
+ * Description: keypad driver for ADP5589
+ * I2C QWERTY Keypad and IO Expander
+ * Bugs: Enter bugs at http://blackfin.uclinux.org/
+ *
+ * Copyright (C) 2010-2011 Analog Devices Inc.
+ * Licensed under the GPL-2.
+ */
+
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/workqueue.h>
+#include <linux/errno.h>
+#include <linux/pm.h>
+#include <linux/platform_device.h>
+#include <linux/input.h>
+#include <linux/i2c.h>
+#include <linux/gpio.h>
+#include <linux/slab.h>
+
+#include <linux/input/adp5589.h>
+
+/* GENERAL_CFG Register */
+#define OSC_EN (1 << 7)
+#define CORE_CLK(x) (((x) & 0x3) << 5)
+#define LCK_TRK_LOGIC (1 << 4)
+#define LCK_TRK_GPI (1 << 3)
+#define INT_CFG (1 << 1)
+#define RST_CFG (1 << 0)
+
+/* INT_EN Register */
+#define LOGIC2_IEN (1 << 5)
+#define LOGIC1_IEN (1 << 4)
+#define LOCK_IEN (1 << 3)
+#define OVRFLOW_IEN (1 << 2)
+#define GPI_IEN (1 << 1)
+#define EVENT_IEN (1 << 0)
+
+/* Interrupt Status Register */
+#define LOGIC2_INT (1 << 5)
+#define LOGIC1_INT (1 << 4)
+#define LOCK_INT (1 << 3)
+#define OVRFLOW_INT (1 << 2)
+#define GPI_INT (1 << 1)
+#define EVENT_INT (1 << 0)
+
+/* STATUS Register */
+
+#define LOGIC2_STAT (1 << 7)
+#define LOGIC1_STAT (1 << 6)
+#define LOCK_STAT (1 << 5)
+#define KEC 0xF
+
+/* PIN_CONFIG_D Register */
+#define C4_EXTEND_CFG (1 << 6) /* RESET2 */
+#define R4_EXTEND_CFG (1 << 5) /* RESET1 */
+
+/* LOCK_CFG */
+#define LOCK_EN (1 << 0)
+
+#define PTIME_MASK 0x3
+#define LTIME_MASK 0x3
+
+/* Key Event Register xy */
+#define KEY_EV_PRESSED (1 << 7)
+#define KEY_EV_MASK (0x7F)
+
+#define KEYP_MAX_EVENT 16
+
+#define MAXGPIO 19
+#define ADP_BANK(offs) ((offs) >> 3)
+#define ADP_BIT(offs) (1u << ((offs) & 0x7))
+
+struct adp5589_kpad {
+ struct i2c_client *client;
+ struct input_dev *input;
+ unsigned short keycode[ADP5589_KEYMAPSIZE];
+ const struct adp5589_gpi_map *gpimap;
+ unsigned short gpimapsize;
+ unsigned extend_cfg;
+#ifdef CONFIG_GPIOLIB
+ unsigned char gpiomap[MAXGPIO];
+ bool export_gpio;
+ struct gpio_chip gc;
+ struct mutex gpio_lock; /* Protect cached dir, dat_out */
+ u8 dat_out[3];
+ u8 dir[3];
+#endif
+};
+
+static int adp5589_read(struct i2c_client *client, u8 reg)
+{
+ int ret = i2c_smbus_read_byte_data(client, reg);
+
+ if (ret < 0)
+ dev_err(&client->dev, "Read Error\n");
+
+ return ret;
+}
+
+static int adp5589_write(struct i2c_client *client, u8 reg, u8 val)
+{
+ return i2c_smbus_write_byte_data(client, reg, val);
+}
+
+#ifdef CONFIG_GPIOLIB
+static int adp5589_gpio_get_value(struct gpio_chip *chip, unsigned off)
+{
+ struct adp5589_kpad *kpad = container_of(chip, struct adp5589_kpad, gc);
+ unsigned int bank = ADP_BANK(kpad->gpiomap[off]);
+ unsigned int bit = ADP_BIT(kpad->gpiomap[off]);
+
+ return !!(adp5589_read(kpad->client, ADP5589_GPI_STATUS_A + bank) &
+ bit);
+}
+
+static void adp5589_gpio_set_value(struct gpio_chip *chip,
+ unsigned off, int val)
+{
+ struct adp5589_kpad *kpad = container_of(chip, struct adp5589_kpad, gc);
+ unsigned int bank = ADP_BANK(kpad->gpiomap[off]);
+ unsigned int bit = ADP_BIT(kpad->gpiomap[off]);
+
+ mutex_lock(&kpad->gpio_lock);
+
+ if (val)
+ kpad->dat_out[bank] |= bit;
+ else
+ kpad->dat_out[bank] &= ~bit;
+
+ adp5589_write(kpad->client, ADP5589_GPO_DATA_OUT_A + bank,
+ kpad->dat_out[bank]);
+
+ mutex_unlock(&kpad->gpio_lock);
+}
+
+static int adp5589_gpio_direction_input(struct gpio_chip *chip, unsigned off)
+{
+ struct adp5589_kpad *kpad = container_of(chip, struct adp5589_kpad, gc);
+ unsigned int bank = ADP_BANK(kpad->gpiomap[off]);
+ unsigned int bit = ADP_BIT(kpad->gpiomap[off]);
+ int ret;
+
+ mutex_lock(&kpad->gpio_lock);
+
+ kpad->dir[bank] &= ~bit;
+ ret = adp5589_write(kpad->client, ADP5589_GPIO_DIRECTION_A + bank,
+ kpad->dir[bank]);
+
+ mutex_unlock(&kpad->gpio_lock);
+
+ return ret;
+}
+
+static int adp5589_gpio_direction_output(struct gpio_chip *chip,
+ unsigned off, int val)
+{
+ struct adp5589_kpad *kpad = container_of(chip, struct adp5589_kpad, gc);
+ unsigned int bank = ADP_BANK(kpad->gpiomap[off]);
+ unsigned int bit = ADP_BIT(kpad->gpiomap[off]);
+ int ret;
+
+ mutex_lock(&kpad->gpio_lock);
+
+ kpad->dir[bank] |= bit;
+
+ if (val)
+ kpad->dat_out[bank] |= bit;
+ else
+ kpad->dat_out[bank] &= ~bit;
+
+ ret = adp5589_write(kpad->client, ADP5589_GPO_DATA_OUT_A + bank,
+ kpad->dat_out[bank]);
+ ret |= adp5589_write(kpad->client, ADP5589_GPIO_DIRECTION_A + bank,
+ kpad->dir[bank]);
+
+ mutex_unlock(&kpad->gpio_lock);
+
+ return ret;
+}
+
+static int __devinit adp5589_build_gpiomap(struct adp5589_kpad *kpad,
+ const struct adp5589_kpad_platform_data *pdata)
+{
+ bool pin_used[MAXGPIO];
+ int n_unused = 0;
+ int i;
+
+ memset(pin_used, false, sizeof(pin_used));
+
+ for (i = 0; i < MAXGPIO; i++)
+ if (pdata->keypad_en_mask & (1 << i))
+ pin_used[i] = true;
+
+ for (i = 0; i < kpad->gpimapsize; i++)
+ pin_used[kpad->gpimap[i].pin - ADP5589_GPI_PIN_BASE] = true;
+
+ if (kpad->extend_cfg & R4_EXTEND_CFG)
+ pin_used[4] = true;
+
+ if (kpad->extend_cfg & C4_EXTEND_CFG)
+ pin_used[12] = true;
+
+ for (i = 0; i < MAXGPIO; i++)
+ if (!pin_used[i])
+ kpad->gpiomap[n_unused++] = i;
+
+ return n_unused;
+}
+
+static int __devinit adp5589_gpio_add(struct adp5589_kpad *kpad)
+{
+ struct device *dev = &kpad->client->dev;
+ const struct adp5589_kpad_platform_data *pdata = dev->platform_data;
+ const struct adp5589_gpio_platform_data *gpio_data = pdata->gpio_data;
+ int i, error;
+
+ if (!gpio_data)
+ return 0;
+
+ kpad->gc.ngpio = adp5589_build_gpiomap(kpad, pdata);
+ if (kpad->gc.ngpio == 0) {
+ dev_info(dev, "No unused gpios left to export\n");
+ return 0;
+ }
+
+ kpad->export_gpio = true;
+
+ kpad->gc.direction_input = adp5589_gpio_direction_input;
+ kpad->gc.direction_output = adp5589_gpio_direction_output;
+ kpad->gc.get = adp5589_gpio_get_value;
+ kpad->gc.set = adp5589_gpio_set_value;
+ kpad->gc.can_sleep = 1;
+
+ kpad->gc.base = gpio_data->gpio_start;
+ kpad->gc.label = kpad->client->name;
+ kpad->gc.owner = THIS_MODULE;
+
+ mutex_init(&kpad->gpio_lock);
+
+ error = gpiochip_add(&kpad->gc);
+ if (error) {
+ dev_err(dev, "gpiochip_add failed, err: %d\n", error);
+ return error;
+ }
+
+ for (i = 0; i <= ADP_BANK(MAXGPIO); i++) {
+ kpad->dat_out[i] = adp5589_read(kpad->client,
+ ADP5589_GPO_DATA_OUT_A + i);
+ kpad->dir[i] = adp5589_read(kpad->client,
+ ADP5589_GPIO_DIRECTION_A + i);
+ }
+
+ if (gpio_data->setup) {
+ error = gpio_data->setup(kpad->client,
+ kpad->gc.base, kpad->gc.ngpio,
+ gpio_data->context);
+ if (error)
+ dev_warn(dev, "setup failed, %d\n", error);
+ }
+
+ return 0;
+}
+
+static void __devexit adp5589_gpio_remove(struct adp5589_kpad *kpad)
+{
+ struct device *dev = &kpad->client->dev;
+ const struct adp5589_kpad_platform_data *pdata = dev->platform_data;
+ const struct adp5589_gpio_platform_data *gpio_data = pdata->gpio_data;
+ int error;
+
+ if (!kpad->export_gpio)
+ return;
+
+ if (gpio_data->teardown) {
+ error = gpio_data->teardown(kpad->client,
+ kpad->gc.base, kpad->gc.ngpio,
+ gpio_data->context);
+ if (error)
+ dev_warn(dev, "teardown failed %d\n", error);
+ }
+
+ error = gpiochip_remove(&kpad->gc);
+ if (error)
+ dev_warn(dev, "gpiochip_remove failed %d\n", error);
+}
+#else
+static inline int adp5589_gpio_add(struct adp5589_kpad *kpad)
+{
+ return 0;
+}
+
+static inline void adp5589_gpio_remove(struct adp5589_kpad *kpad)
+{
+}
+#endif
+
+static void adp5589_report_switches(struct adp5589_kpad *kpad,
+ int key, int key_val)
+{
+ int i;
+
+ for (i = 0; i < kpad->gpimapsize; i++) {
+ if (key_val == kpad->gpimap[i].pin) {
+ input_report_switch(kpad->input,
+ kpad->gpimap[i].sw_evt,
+ key & KEY_EV_PRESSED);
+ break;
+ }
+ }
+}
+
+static void adp5589_report_events(struct adp5589_kpad *kpad, int ev_cnt)
+{
+ int i;
+
+ for (i = 0; i < ev_cnt; i++) {
+ int key = adp5589_read(kpad->client, ADP5589_FIFO_1 + i);
+ int key_val = key & KEY_EV_MASK;
+
+ if (key_val >= ADP5589_GPI_PIN_BASE &&
+ key_val <= ADP5589_GPI_PIN_END) {
+ adp5589_report_switches(kpad, key, key_val);
+ } else {
+ input_report_key(kpad->input,
+ kpad->keycode[key_val - 1],
+ key & KEY_EV_PRESSED);
+ }
+ }
+}
+
+static irqreturn_t adp5589_irq(int irq, void *handle)
+{
+ struct adp5589_kpad *kpad = handle;
+ struct i2c_client *client = kpad->client;
+ int status, ev_cnt;
+
+ status = adp5589_read(client, ADP5589_INT_STATUS);
+
+ if (status & OVRFLOW_INT) /* Unlikely and should never happen */
+ dev_err(&client->dev, "Event Overflow Error\n");
+
+ if (status & EVENT_INT) {
+ ev_cnt = adp5589_read(client, ADP5589_STATUS) & KEC;
+ if (ev_cnt) {
+ adp5589_report_events(kpad, ev_cnt);
+ input_sync(kpad->input);
+ }
+ }
+
+ adp5589_write(client, ADP5589_INT_STATUS, status); /* Status is W1C */
+
+ return IRQ_HANDLED;
+}
+
+static int __devinit adp5589_get_evcode(struct adp5589_kpad *kpad, unsigned short key)
+{
+ int i;
+
+ for (i = 0; i < ADP5589_KEYMAPSIZE; i++)
+ if (key == kpad->keycode[i])
+ return (i + 1) | KEY_EV_PRESSED;
+
+ dev_err(&kpad->client->dev, "RESET/UNLOCK key not in keycode map\n");
+
+ return -EINVAL;
+}
+
+static int __devinit adp5589_setup(struct adp5589_kpad *kpad)
+{
+ struct i2c_client *client = kpad->client;
+ const struct adp5589_kpad_platform_data *pdata =
+ client->dev.platform_data;
+ int i, ret;
+ unsigned char evt_mode1 = 0, evt_mode2 = 0, evt_mode3 = 0;
+ unsigned char pull_mask = 0;
+
+ ret = adp5589_write(client, ADP5589_PIN_CONFIG_A,
+ pdata->keypad_en_mask & 0xFF);
+ ret |= adp5589_write(client, ADP5589_PIN_CONFIG_B,
+ (pdata->keypad_en_mask >> 8) & 0xFF);
+ ret |= adp5589_write(client, ADP5589_PIN_CONFIG_C,
+ (pdata->keypad_en_mask >> 16) & 0xFF);
+
+ if (pdata->en_keylock) {
+ ret |= adp5589_write(client, ADP5589_UNLOCK1,
+ pdata->unlock_key1);
+ ret |= adp5589_write(client, ADP5589_UNLOCK2,
+ pdata->unlock_key2);
+ ret |= adp5589_write(client, ADP5589_UNLOCK_TIMERS,
+ pdata->unlock_timer & LTIME_MASK);
+ ret |= adp5589_write(client, ADP5589_LOCK_CFG, LOCK_EN);
+ }
+
+ for (i = 0; i < KEYP_MAX_EVENT; i++)
+ ret |= adp5589_read(client, ADP5589_FIFO_1 + i);
+
+ for (i = 0; i < pdata->gpimapsize; i++) {
+ unsigned short pin = pdata->gpimap[i].pin;
+
+ if (pin <= ADP5589_GPI_PIN_ROW_END) {
+ evt_mode1 |= (1 << (pin - ADP5589_GPI_PIN_ROW_BASE));
+ } else {
+ evt_mode2 |=
+ ((1 << (pin - ADP5589_GPI_PIN_COL_BASE)) & 0xFF);
+ evt_mode3 |=
+ ((1 << (pin - ADP5589_GPI_PIN_COL_BASE)) >> 8);
+ }
+ }
+
+ if (pdata->gpimapsize) {
+ ret |= adp5589_write(client, ADP5589_GPI_EVENT_EN_A, evt_mode1);
+ ret |= adp5589_write(client, ADP5589_GPI_EVENT_EN_B, evt_mode2);
+ ret |= adp5589_write(client, ADP5589_GPI_EVENT_EN_C, evt_mode3);
+ }
+
+ if (pdata->pull_dis_mask & pdata->pullup_en_100k &
+ pdata->pullup_en_300k & pdata->pulldown_en_300k)
+ dev_warn(&client->dev, "Conflicting pull resistor config\n");
+
+ for (i = 0; i < MAXGPIO; i++) {
+ unsigned val = 0;
+
+ if (pdata->pullup_en_300k & (1 << i))
+ val = 0;
+ else if (pdata->pulldown_en_300k & (1 << i))
+ val = 1;
+ else if (pdata->pullup_en_100k & (1 << i))
+ val = 2;
+ else if (pdata->pull_dis_mask & (1 << i))
+ val = 3;
+
+ pull_mask |= val << (2 * (i & 0x3));
+
+ if ((i & 0x3) == 0x3 || i == MAXGPIO - 1) {
+ ret |= adp5589_write(client,
+ ADP5589_RPULL_CONFIG_A + (i >> 2),
+ pull_mask);
+ pull_mask = 0;
+ }
+ }
+
+ if (pdata->reset1_key_1 && pdata->reset1_key_2 && pdata->reset1_key_3) {
+ ret |= adp5589_write(client, ADP5589_RESET1_EVENT_A,
+ adp5589_get_evcode(kpad,
+ pdata->reset1_key_1));
+ ret |= adp5589_write(client, ADP5589_RESET1_EVENT_B,
+ adp5589_get_evcode(kpad,
+ pdata->reset1_key_2));
+ ret |= adp5589_write(client, ADP5589_RESET1_EVENT_C,
+ adp5589_get_evcode(kpad,
+ pdata->reset1_key_3));
+ kpad->extend_cfg |= R4_EXTEND_CFG;
+ }
+
+ if (pdata->reset2_key_1 && pdata->reset2_key_2) {
+ ret |= adp5589_write(client, ADP5589_RESET2_EVENT_A,
+ adp5589_get_evcode(kpad,
+ pdata->reset2_key_1));
+ ret |= adp5589_write(client, ADP5589_RESET2_EVENT_B,
+ adp5589_get_evcode(kpad,
+ pdata->reset2_key_2));
+ kpad->extend_cfg |= C4_EXTEND_CFG;
+ }
+
+ if (kpad->extend_cfg) {
+ ret |= adp5589_write(client, ADP5589_RESET_CFG,
+ pdata->reset_cfg);
+ ret |= adp5589_write(client, ADP5589_PIN_CONFIG_D,
+ kpad->extend_cfg);
+ }
+
+ for (i = 0; i <= ADP_BANK(MAXGPIO); i++)
+ ret |= adp5589_write(client, ADP5589_DEBOUNCE_DIS_A + i,
+ pdata->debounce_dis_mask >> (i * 8));
+
+ ret |= adp5589_write(client, ADP5589_POLL_PTIME_CFG,
+ pdata->scan_cycle_time & PTIME_MASK);
+ ret |= adp5589_write(client, ADP5589_INT_STATUS, LOGIC2_INT |
+ LOGIC1_INT | OVRFLOW_INT | LOCK_INT |
+ GPI_INT | EVENT_INT); /* Status is W1C */
+
+ ret |= adp5589_write(client, ADP5589_GENERAL_CFG,
+ INT_CFG | OSC_EN | CORE_CLK(3));
+ ret |= adp5589_write(client, ADP5589_INT_EN,
+ OVRFLOW_IEN | GPI_IEN | EVENT_IEN);
+
+ if (ret < 0) {
+ dev_err(&client->dev, "Write Error\n");
+ return ret;
+ }
+
+ return 0;
+}
+
+static void __devinit adp5589_report_switch_state(struct adp5589_kpad *kpad)
+{
+ int gpi_stat1 = adp5589_read(kpad->client, ADP5589_GPI_STATUS_A);
+ int gpi_stat2 = adp5589_read(kpad->client, ADP5589_GPI_STATUS_B);
+ int gpi_stat3 = adp5589_read(kpad->client, ADP5589_GPI_STATUS_C);
+ int gpi_stat_tmp, pin_loc;
+ int i;
+
+ for (i = 0; i < kpad->gpimapsize; i++) {
+ unsigned short pin = kpad->gpimap[i].pin;
+
+ if (pin <= ADP5589_GPI_PIN_ROW_END) {
+ gpi_stat_tmp = gpi_stat1;
+ pin_loc = pin - ADP5589_GPI_PIN_ROW_BASE;
+ } else if ((pin - ADP5589_GPI_PIN_COL_BASE) < 8) {
+ gpi_stat_tmp = gpi_stat2;
+ pin_loc = pin - ADP5589_GPI_PIN_COL_BASE;
+ } else {
+ gpi_stat_tmp = gpi_stat3;
+ pin_loc = pin - ADP5589_GPI_PIN_COL_BASE - 8;
+ }
+
+ if (gpi_stat_tmp < 0) {
+ dev_err(&kpad->client->dev,
+ "Can't read GPIO_DAT_STAT switch"
+ " %d default to OFF\n", pin);
+ gpi_stat_tmp = 0;
+ }
+
+ input_report_switch(kpad->input,
+ kpad->gpimap[i].sw_evt,
+ !(gpi_stat_tmp & (1 << pin_loc)));
+ }
+
+ input_sync(kpad->input);
+}
+
+static int __devinit adp5589_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ struct adp5589_kpad *kpad;
+ const struct adp5589_kpad_platform_data *pdata;
+ struct input_dev *input;
+ unsigned int revid;
+ int ret, i;
+ int error;
+
+ if (!i2c_check_functionality(client->adapter,
+ I2C_FUNC_SMBUS_BYTE_DATA)) {
+ dev_err(&client->dev, "SMBUS Byte Data not Supported\n");
+ return -EIO;
+ }
+
+ pdata = client->dev.platform_data;
+ if (!pdata) {
+ dev_err(&client->dev, "no platform data?\n");
+ return -EINVAL;
+ }
+
+ if (!((pdata->keypad_en_mask & 0xFF) &&
+ (pdata->keypad_en_mask >> 8)) || !pdata->keymap) {
+ dev_err(&client->dev, "no rows, cols or keymap from pdata\n");
+ return -EINVAL;
+ }
+
+ if (pdata->keymapsize != ADP5589_KEYMAPSIZE) {
+ dev_err(&client->dev, "invalid keymapsize\n");
+ return -EINVAL;
+ }
+
+ if (!pdata->gpimap && pdata->gpimapsize) {
+ dev_err(&client->dev, "invalid gpimap from pdata\n");
+ return -EINVAL;
+ }
+
+ if (pdata->gpimapsize > ADP5589_GPIMAPSIZE_MAX) {
+ dev_err(&client->dev, "invalid gpimapsize\n");
+ return -EINVAL;
+ }
+
+ for (i = 0; i < pdata->gpimapsize; i++) {
+ unsigned short pin = pdata->gpimap[i].pin;
+
+ if (pin < ADP5589_GPI_PIN_BASE || pin > ADP5589_GPI_PIN_END) {
+ dev_err(&client->dev, "invalid gpi pin data\n");
+ return -EINVAL;
+ }
+
+ if ((1 << (pin - ADP5589_GPI_PIN_ROW_BASE)) &
+ pdata->keypad_en_mask) {
+ dev_err(&client->dev, "invalid gpi row/col data\n");
+ return -EINVAL;
+ }
+ }
+
+ if (!client->irq) {
+ dev_err(&client->dev, "no IRQ?\n");
+ return -EINVAL;
+ }
+
+ kpad = kzalloc(sizeof(*kpad), GFP_KERNEL);
+ input = input_allocate_device();
+ if (!kpad || !input) {
+ error = -ENOMEM;
+ goto err_free_mem;
+ }
+
+ kpad->client = client;
+ kpad->input = input;
+
+ ret = adp5589_read(client, ADP5589_ID);
+ if (ret < 0) {
+ error = ret;
+ goto err_free_mem;
+ }
+
+ revid = (u8) ret & ADP5589_DEVICE_ID_MASK;
+
+ input->name = client->name;
+ input->phys = "adp5589-keys/input0";
+ input->dev.parent = &client->dev;
+
+ input_set_drvdata(input, kpad);
+
+ input->id.bustype = BUS_I2C;
+ input->id.vendor = 0x0001;
+ input->id.product = 0x0001;
+ input->id.version = revid;
+
+ input->keycodesize = sizeof(kpad->keycode[0]);
+ input->keycodemax = pdata->keymapsize;
+ input->keycode = kpad->keycode;
+
+ memcpy(kpad->keycode, pdata->keymap,
+ pdata->keymapsize * input->keycodesize);
+
+ kpad->gpimap = pdata->gpimap;
+ kpad->gpimapsize = pdata->gpimapsize;
+
+ /* setup input device */
+ __set_bit(EV_KEY, input->evbit);
+
+ if (pdata->repeat)
+ __set_bit(EV_REP, input->evbit);
+
+ for (i = 0; i < input->keycodemax; i++)
+ __set_bit(kpad->keycode[i] & KEY_MAX, input->keybit);
+ __clear_bit(KEY_RESERVED, input->keybit);
+
+ if (kpad->gpimapsize)
+ __set_bit(EV_SW, input->evbit);
+ for (i = 0; i < kpad->gpimapsize; i++)
+ __set_bit(kpad->gpimap[i].sw_evt, input->swbit);
+
+ error = input_register_device(input);
+ if (error) {
+ dev_err(&client->dev, "unable to register input device\n");
+ goto err_free_mem;
+ }
+
+ error = request_threaded_irq(client->irq, NULL, adp5589_irq,
+ IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
+ client->dev.driver->name, kpad);
+ if (error) {
+ dev_err(&client->dev, "irq %d busy?\n", client->irq);
+ goto err_unreg_dev;
+ }
+
+ error = adp5589_setup(kpad);
+ if (error)
+ goto err_free_irq;
+
+ if (kpad->gpimapsize)
+ adp5589_report_switch_state(kpad);
+
+ error = adp5589_gpio_add(kpad);
+ if (error)
+ goto err_free_irq;
+
+ device_init_wakeup(&client->dev, 1);
+ i2c_set_clientdata(client, kpad);
+
+ dev_info(&client->dev, "Rev.%d keypad, irq %d\n", revid, client->irq);
+ return 0;
+
+err_free_irq:
+ free_irq(client->irq, kpad);
+err_unreg_dev:
+ input_unregister_device(input);
+ input = NULL;
+err_free_mem:
+ input_free_device(input);
+ kfree(kpad);
+
+ return error;
+}
+
+static int __devexit adp5589_remove(struct i2c_client *client)
+{
+ struct adp5589_kpad *kpad = i2c_get_clientdata(client);
+
+ adp5589_write(client, ADP5589_GENERAL_CFG, 0);
+ free_irq(client->irq, kpad);
+ input_unregister_device(kpad->input);
+ adp5589_gpio_remove(kpad);
+ kfree(kpad);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int adp5589_suspend(struct device *dev)
+{
+ struct adp5589_kpad *kpad = dev_get_drvdata(dev);
+ struct i2c_client *client = kpad->client;
+
+ disable_irq(client->irq);
+
+ if (device_may_wakeup(&client->dev))
+ enable_irq_wake(client->irq);
+
+ return 0;
+}
+
+static int adp5589_resume(struct device *dev)
+{
+ struct adp5589_kpad *kpad = dev_get_drvdata(dev);
+ struct i2c_client *client = kpad->client;
+
+ if (device_may_wakeup(&client->dev))
+ disable_irq_wake(client->irq);
+
+ enable_irq(client->irq);
+
+ return 0;
+}
+#endif
+
+static SIMPLE_DEV_PM_OPS(adp5589_dev_pm_ops, adp5589_suspend, adp5589_resume);
+
+static const struct i2c_device_id adp5589_id[] = {
+ {"adp5589-keys", 0},
+ {}
+};
+
+MODULE_DEVICE_TABLE(i2c, adp5589_id);
+
+static struct i2c_driver adp5589_driver = {
+ .driver = {
+ .name = KBUILD_MODNAME,
+ .owner = THIS_MODULE,
+ .pm = &adp5589_dev_pm_ops,
+ },
+ .probe = adp5589_probe,
+ .remove = __devexit_p(adp5589_remove),
+ .id_table = adp5589_id,
+};
+
+static int __init adp5589_init(void)
+{
+ return i2c_add_driver(&adp5589_driver);
+}
+module_init(adp5589_init);
+
+static void __exit adp5589_exit(void)
+{
+ i2c_del_driver(&adp5589_driver);
+}
+module_exit(adp5589_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
+MODULE_DESCRIPTION("ADP5589 Keypad driver");
diff --git a/drivers/input/keyboard/gpio_keys.c b/drivers/input/keyboard/gpio_keys.c
index eb30063..6e6145b 100644
--- a/drivers/input/keyboard/gpio_keys.c
+++ b/drivers/input/keyboard/gpio_keys.c
@@ -324,7 +324,12 @@
unsigned int type = button->type ?: EV_KEY;
int state = (gpio_get_value_cansleep(button->gpio) ? 1 : 0) ^ button->active_low;
- input_event(input, type, button->code, !!state);
+ if (type == EV_ABS) {
+ if (state)
+ input_event(input, type, button->code, button->value);
+ } else {
+ input_event(input, type, button->code, !!state);
+ }
input_sync(input);
}
@@ -363,7 +368,7 @@
struct gpio_button_data *bdata,
struct gpio_keys_button *button)
{
- char *desc = button->desc ? button->desc : "gpio_keys";
+ const char *desc = button->desc ? button->desc : "gpio_keys";
struct device *dev = &pdev->dev;
unsigned long irqflags;
int irq, error;
@@ -468,7 +473,7 @@
platform_set_drvdata(pdev, ddata);
input_set_drvdata(input, ddata);
- input->name = pdev->name;
+ input->name = pdata->name ? : pdev->name;
input->phys = "gpio-keys/input0";
input->dev.parent = &pdev->dev;
input->open = gpio_keys_open;
diff --git a/drivers/input/keyboard/mpr121_touchkey.c b/drivers/input/keyboard/mpr121_touchkey.c
new file mode 100644
index 0000000..0a9e811
--- /dev/null
+++ b/drivers/input/keyboard/mpr121_touchkey.c
@@ -0,0 +1,339 @@
+/*
+ * Touchkey driver for Freescale MPR121 Controllor
+ *
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ * Author: Zhang Jiejing <jiejing.zhang@freescale.com>
+ *
+ * Based on mcs_touchkey.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/input.h>
+#include <linux/i2c.h>
+#include <linux/slab.h>
+#include <linux/delay.h>
+#include <linux/bitops.h>
+#include <linux/interrupt.h>
+#include <linux/i2c/mpr121_touchkey.h>
+
+/* Register definitions */
+#define ELE_TOUCH_STATUS_0_ADDR 0x0
+#define ELE_TOUCH_STATUS_1_ADDR 0X1
+#define MHD_RISING_ADDR 0x2b
+#define NHD_RISING_ADDR 0x2c
+#define NCL_RISING_ADDR 0x2d
+#define FDL_RISING_ADDR 0x2e
+#define MHD_FALLING_ADDR 0x2f
+#define NHD_FALLING_ADDR 0x30
+#define NCL_FALLING_ADDR 0x31
+#define FDL_FALLING_ADDR 0x32
+#define ELE0_TOUCH_THRESHOLD_ADDR 0x41
+#define ELE0_RELEASE_THRESHOLD_ADDR 0x42
+#define AFE_CONF_ADDR 0x5c
+#define FILTER_CONF_ADDR 0x5d
+
+/*
+ * ELECTRODE_CONF_ADDR: This register configures the number of
+ * enabled capacitance sensing inputs and its run/suspend mode.
+ */
+#define ELECTRODE_CONF_ADDR 0x5e
+#define AUTO_CONFIG_CTRL_ADDR 0x7b
+#define AUTO_CONFIG_USL_ADDR 0x7d
+#define AUTO_CONFIG_LSL_ADDR 0x7e
+#define AUTO_CONFIG_TL_ADDR 0x7f
+
+/* Threshold of touch/release trigger */
+#define TOUCH_THRESHOLD 0x0f
+#define RELEASE_THRESHOLD 0x0a
+/* Masks for touch and release triggers */
+#define TOUCH_STATUS_MASK 0xfff
+/* MPR121 has 12 keys */
+#define MPR121_MAX_KEY_COUNT 12
+
+struct mpr121_touchkey {
+ struct i2c_client *client;
+ struct input_dev *input_dev;
+ unsigned int key_val;
+ unsigned int statusbits;
+ unsigned int keycount;
+ u16 keycodes[MPR121_MAX_KEY_COUNT];
+};
+
+struct mpr121_init_register {
+ int addr;
+ u8 val;
+};
+
+static const struct mpr121_init_register init_reg_table[] __devinitconst = {
+ { MHD_RISING_ADDR, 0x1 },
+ { NHD_RISING_ADDR, 0x1 },
+ { MHD_FALLING_ADDR, 0x1 },
+ { NHD_FALLING_ADDR, 0x1 },
+ { NCL_FALLING_ADDR, 0xff },
+ { FDL_FALLING_ADDR, 0x02 },
+ { FILTER_CONF_ADDR, 0x04 },
+ { AFE_CONF_ADDR, 0x0b },
+ { AUTO_CONFIG_CTRL_ADDR, 0x0b },
+};
+
+static irqreturn_t mpr_touchkey_interrupt(int irq, void *dev_id)
+{
+ struct mpr121_touchkey *mpr121 = dev_id;
+ struct i2c_client *client = mpr121->client;
+ struct input_dev *input = mpr121->input_dev;
+ unsigned int key_num, key_val, pressed;
+ int reg;
+
+ reg = i2c_smbus_read_byte_data(client, ELE_TOUCH_STATUS_1_ADDR);
+ if (reg < 0) {
+ dev_err(&client->dev, "i2c read error [%d]\n", reg);
+ goto out;
+ }
+
+ reg <<= 8;
+ reg |= i2c_smbus_read_byte_data(client, ELE_TOUCH_STATUS_0_ADDR);
+ if (reg < 0) {
+ dev_err(&client->dev, "i2c read error [%d]\n", reg);
+ goto out;
+ }
+
+ reg &= TOUCH_STATUS_MASK;
+ /* use old press bit to figure out which bit changed */
+ key_num = ffs(reg ^ mpr121->statusbits) - 1;
+ pressed = reg & (1 << key_num);
+ mpr121->statusbits = reg;
+
+ key_val = mpr121->keycodes[key_num];
+
+ input_event(input, EV_MSC, MSC_SCAN, key_num);
+ input_report_key(input, key_val, pressed);
+ input_sync(input);
+
+ dev_dbg(&client->dev, "key %d %d %s\n", key_num, key_val,
+ pressed ? "pressed" : "released");
+
+out:
+ return IRQ_HANDLED;
+}
+
+static int __devinit mpr121_phys_init(const struct mpr121_platform_data *pdata,
+ struct mpr121_touchkey *mpr121,
+ struct i2c_client *client)
+{
+ const struct mpr121_init_register *reg;
+ unsigned char usl, lsl, tl;
+ int i, t, vdd, ret;
+
+ /* Set up touch/release threshold for ele0-ele11 */
+ for (i = 0; i <= MPR121_MAX_KEY_COUNT; i++) {
+ t = ELE0_TOUCH_THRESHOLD_ADDR + (i * 2);
+ ret = i2c_smbus_write_byte_data(client, t, TOUCH_THRESHOLD);
+ if (ret < 0)
+ goto err_i2c_write;
+ ret = i2c_smbus_write_byte_data(client, t + 1,
+ RELEASE_THRESHOLD);
+ if (ret < 0)
+ goto err_i2c_write;
+ }
+
+ /* Set up init register */
+ for (i = 0; i < ARRAY_SIZE(init_reg_table); i++) {
+ reg = &init_reg_table[i];
+ ret = i2c_smbus_write_byte_data(client, reg->addr, reg->val);
+ if (ret < 0)
+ goto err_i2c_write;
+ }
+
+
+ /*
+ * Capacitance on sensing input varies and needs to be compensated.
+ * The internal MPR121-auto-configuration can do this if it's
+ * registers are set properly (based on pdata->vdd_uv).
+ */
+ vdd = pdata->vdd_uv / 1000;
+ usl = ((vdd - 700) * 256) / vdd;
+ lsl = (usl * 65) / 100;
+ tl = (usl * 90) / 100;
+ ret = i2c_smbus_write_byte_data(client, AUTO_CONFIG_USL_ADDR, usl);
+ ret |= i2c_smbus_write_byte_data(client, AUTO_CONFIG_LSL_ADDR, lsl);
+ ret |= i2c_smbus_write_byte_data(client, AUTO_CONFIG_TL_ADDR, tl);
+ ret |= i2c_smbus_write_byte_data(client, ELECTRODE_CONF_ADDR,
+ mpr121->keycount);
+ if (ret != 0)
+ goto err_i2c_write;
+
+ dev_dbg(&client->dev, "set up with %x keys.\n", mpr121->keycount);
+
+ return 0;
+
+err_i2c_write:
+ dev_err(&client->dev, "i2c write error: %d\n", ret);
+ return ret;
+}
+
+static int __devinit mpr_touchkey_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ const struct mpr121_platform_data *pdata = client->dev.platform_data;
+ struct mpr121_touchkey *mpr121;
+ struct input_dev *input_dev;
+ int error;
+ int i;
+
+ if (!pdata) {
+ dev_err(&client->dev, "no platform data defined\n");
+ return -EINVAL;
+ }
+
+ if (!pdata->keymap || !pdata->keymap_size) {
+ dev_err(&client->dev, "missing keymap data\n");
+ return -EINVAL;
+ }
+
+ if (pdata->keymap_size > MPR121_MAX_KEY_COUNT) {
+ dev_err(&client->dev, "too many keys defined\n");
+ return -EINVAL;
+ }
+
+ if (!client->irq) {
+ dev_err(&client->dev, "irq number should not be zero\n");
+ return -EINVAL;
+ }
+
+ mpr121 = kzalloc(sizeof(struct mpr121_touchkey), GFP_KERNEL);
+ input_dev = input_allocate_device();
+ if (!mpr121 || !input_dev) {
+ dev_err(&client->dev, "Failed to allocate memory\n");
+ error = -ENOMEM;
+ goto err_free_mem;
+ }
+
+ mpr121->client = client;
+ mpr121->input_dev = input_dev;
+ mpr121->keycount = pdata->keymap_size;
+
+ input_dev->name = "Freescale MPR121 Touchkey";
+ input_dev->id.bustype = BUS_I2C;
+ input_dev->dev.parent = &client->dev;
+ input_dev->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_REP);
+
+ input_dev->keycode = mpr121->keycodes;
+ input_dev->keycodesize = sizeof(mpr121->keycodes[0]);
+ input_dev->keycodemax = mpr121->keycount;
+
+ for (i = 0; i < pdata->keymap_size; i++) {
+ input_set_capability(input_dev, EV_KEY, pdata->keymap[i]);
+ mpr121->keycodes[i] = pdata->keymap[i];
+ }
+
+ error = mpr121_phys_init(pdata, mpr121, client);
+ if (error) {
+ dev_err(&client->dev, "Failed to init register\n");
+ goto err_free_mem;
+ }
+
+ error = request_threaded_irq(client->irq, NULL,
+ mpr_touchkey_interrupt,
+ IRQF_TRIGGER_FALLING,
+ client->dev.driver->name, mpr121);
+ if (error) {
+ dev_err(&client->dev, "Failed to register interrupt\n");
+ goto err_free_mem;
+ }
+
+ error = input_register_device(input_dev);
+ if (error)
+ goto err_free_irq;
+
+ i2c_set_clientdata(client, mpr121);
+ device_init_wakeup(&client->dev, pdata->wakeup);
+
+ return 0;
+
+err_free_irq:
+ free_irq(client->irq, mpr121);
+err_free_mem:
+ input_free_device(input_dev);
+ kfree(mpr121);
+ return error;
+}
+
+static int __devexit mpr_touchkey_remove(struct i2c_client *client)
+{
+ struct mpr121_touchkey *mpr121 = i2c_get_clientdata(client);
+
+ free_irq(client->irq, mpr121);
+ input_unregister_device(mpr121->input_dev);
+ kfree(mpr121);
+
+ return 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int mpr_suspend(struct device *dev)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+
+ if (device_may_wakeup(&client->dev))
+ enable_irq_wake(client->irq);
+
+ i2c_smbus_write_byte_data(client, ELECTRODE_CONF_ADDR, 0x00);
+
+ return 0;
+}
+
+static int mpr_resume(struct device *dev)
+{
+ struct i2c_client *client = to_i2c_client(dev);
+ struct mpr121_touchkey *mpr121 = i2c_get_clientdata(client);
+
+ if (device_may_wakeup(&client->dev))
+ disable_irq_wake(client->irq);
+
+ i2c_smbus_write_byte_data(client, ELECTRODE_CONF_ADDR,
+ mpr121->keycount);
+
+ return 0;
+}
+#endif
+
+static SIMPLE_DEV_PM_OPS(mpr121_touchkey_pm_ops, mpr_suspend, mpr_resume);
+
+static const struct i2c_device_id mpr121_id[] = {
+ { "mpr121_touchkey", 0 },
+ { }
+};
+MODULE_DEVICE_TABLE(i2c, mpr121_id);
+
+static struct i2c_driver mpr_touchkey_driver = {
+ .driver = {
+ .name = "mpr121",
+ .owner = THIS_MODULE,
+ .pm = &mpr121_touchkey_pm_ops,
+ },
+ .id_table = mpr121_id,
+ .probe = mpr_touchkey_probe,
+ .remove = __devexit_p(mpr_touchkey_remove),
+};
+
+static int __init mpr_touchkey_init(void)
+{
+ return i2c_add_driver(&mpr_touchkey_driver);
+}
+module_init(mpr_touchkey_init);
+
+static void __exit mpr_touchkey_exit(void)
+{
+ i2c_del_driver(&mpr_touchkey_driver);
+}
+module_exit(mpr_touchkey_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Zhang Jiejing <jiejing.zhang@freescale.com>");
+MODULE_DESCRIPTION("Touch Key driver for Freescale MPR121 Chip");
diff --git a/drivers/input/keyboard/omap-keypad.c b/drivers/input/keyboard/omap-keypad.c
index 0e2a19c..f23a743 100644
--- a/drivers/input/keyboard/omap-keypad.c
+++ b/drivers/input/keyboard/omap-keypad.c
@@ -413,7 +413,7 @@
return 0;
err5:
for (i = irq_idx - 1; i >=0; i--)
- free_irq(row_gpios[i], NULL);
+ free_irq(row_gpios[i], omap_kp);
err4:
input_unregister_device(omap_kp->input);
input_dev = NULL;
@@ -444,11 +444,11 @@
gpio_free(col_gpios[i]);
for (i = 0; i < omap_kp->rows; i++) {
gpio_free(row_gpios[i]);
- free_irq(gpio_to_irq(row_gpios[i]), NULL);
+ free_irq(gpio_to_irq(row_gpios[i]), omap_kp);
}
} else {
omap_writew(1, OMAP1_MPUIO_BASE + OMAP_MPUIO_KBD_MASKIT);
- free_irq(omap_kp->irq, NULL);
+ free_irq(omap_kp->irq, omap_kp);
}
del_timer_sync(&omap_kp->timer);
diff --git a/drivers/input/keyboard/qt1070.c b/drivers/input/keyboard/qt1070.c
index fba8404c..ca7b891 100644
--- a/drivers/input/keyboard/qt1070.c
+++ b/drivers/input/keyboard/qt1070.c
@@ -248,6 +248,7 @@
{ "qt1070", 0 },
{ },
};
+MODULE_DEVICE_TABLE(i2c, qt1070_id);
static struct i2c_driver qt1070_driver = {
.driver = {
diff --git a/drivers/input/keyboard/sh_keysc.c b/drivers/input/keyboard/sh_keysc.c
index d7dafd9..834cf98 100644
--- a/drivers/input/keyboard/sh_keysc.c
+++ b/drivers/input/keyboard/sh_keysc.c
@@ -20,7 +20,7 @@
#include <linux/input.h>
#include <linux/input/sh_keysc.h>
#include <linux/bitmap.h>
-#include <linux/clk.h>
+#include <linux/pm_runtime.h>
#include <linux/io.h>
#include <linux/slab.h>
@@ -37,7 +37,6 @@
struct sh_keysc_priv {
void __iomem *iomem_base;
- struct clk *clk;
DECLARE_BITMAP(last_keys, SH_KEYSC_MAXKEYS);
struct input_dev *input;
struct sh_keysc_info pdata;
@@ -169,7 +168,6 @@
struct sh_keysc_info *pdata;
struct resource *res;
struct input_dev *input;
- char clk_name[8];
int i;
int irq, error;
@@ -210,19 +208,11 @@
goto err1;
}
- snprintf(clk_name, sizeof(clk_name), "keysc%d", pdev->id);
- priv->clk = clk_get(&pdev->dev, clk_name);
- if (IS_ERR(priv->clk)) {
- dev_err(&pdev->dev, "cannot get clock \"%s\"\n", clk_name);
- error = PTR_ERR(priv->clk);
- goto err2;
- }
-
priv->input = input_allocate_device();
if (!priv->input) {
dev_err(&pdev->dev, "failed to allocate input device\n");
error = -ENOMEM;
- goto err3;
+ goto err2;
}
input = priv->input;
@@ -241,10 +231,11 @@
input->keycodesize = sizeof(pdata->keycodes[0]);
input->keycodemax = ARRAY_SIZE(pdata->keycodes);
- error = request_irq(irq, sh_keysc_isr, 0, pdev->name, pdev);
+ error = request_threaded_irq(irq, NULL, sh_keysc_isr, IRQF_ONESHOT,
+ dev_name(&pdev->dev), pdev);
if (error) {
dev_err(&pdev->dev, "failed to request IRQ\n");
- goto err4;
+ goto err3;
}
for (i = 0; i < SH_KEYSC_MAXKEYS; i++)
@@ -254,10 +245,11 @@
error = input_register_device(input);
if (error) {
dev_err(&pdev->dev, "failed to register input device\n");
- goto err5;
+ goto err4;
}
- clk_enable(priv->clk);
+ pm_runtime_enable(&pdev->dev);
+ pm_runtime_get_sync(&pdev->dev);
sh_keysc_write(priv, KYCR1, (sh_keysc_mode[pdata->mode].kymd << 8) |
pdata->scan_timing);
@@ -267,12 +259,10 @@
return 0;
- err5:
- free_irq(irq, pdev);
err4:
- input_free_device(input);
+ free_irq(irq, pdev);
err3:
- clk_put(priv->clk);
+ input_free_device(input);
err2:
iounmap(priv->iomem_base);
err1:
@@ -292,8 +282,8 @@
free_irq(platform_get_irq(pdev, 0), pdev);
iounmap(priv->iomem_base);
- clk_disable(priv->clk);
- clk_put(priv->clk);
+ pm_runtime_put_sync(&pdev->dev);
+ pm_runtime_disable(&pdev->dev);
platform_set_drvdata(pdev, NULL);
kfree(priv);
@@ -301,6 +291,7 @@
return 0;
}
+#if CONFIG_PM_SLEEP
static int sh_keysc_suspend(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
@@ -311,14 +302,13 @@
value = sh_keysc_read(priv, KYCR1);
if (device_may_wakeup(dev)) {
- value |= 0x80;
+ sh_keysc_write(priv, KYCR1, value | 0x80);
enable_irq_wake(irq);
} else {
- value &= ~0x80;
+ sh_keysc_write(priv, KYCR1, value & ~0x80);
+ pm_runtime_put_sync(dev);
}
- sh_keysc_write(priv, KYCR1, value);
-
return 0;
}
@@ -329,16 +319,17 @@
if (device_may_wakeup(dev))
disable_irq_wake(irq);
+ else
+ pm_runtime_get_sync(dev);
return 0;
}
+#endif
-static const struct dev_pm_ops sh_keysc_dev_pm_ops = {
- .suspend = sh_keysc_suspend,
- .resume = sh_keysc_resume,
-};
+static SIMPLE_DEV_PM_OPS(sh_keysc_dev_pm_ops,
+ sh_keysc_suspend, sh_keysc_resume);
-struct platform_driver sh_keysc_device_driver = {
+static struct platform_driver sh_keysc_device_driver = {
.probe = sh_keysc_probe,
.remove = __devexit_p(sh_keysc_remove),
.driver = {
diff --git a/drivers/input/keyboard/tegra-kbc.c b/drivers/input/keyboard/tegra-kbc.c
index 99ce903..2b3b73e 100644
--- a/drivers/input/keyboard/tegra-kbc.c
+++ b/drivers/input/keyboard/tegra-kbc.c
@@ -66,12 +66,11 @@
void __iomem *mmio;
struct input_dev *idev;
unsigned int irq;
- unsigned int wake_enable_rows;
- unsigned int wake_enable_cols;
spinlock_t lock;
unsigned int repoll_dly;
unsigned long cp_dly_jiffies;
bool use_fn_map;
+ bool use_ghost_filter;
const struct tegra_kbc_platform_data *pdata;
unsigned short keycode[KBC_MAX_KEY * 2];
unsigned short current_keys[KBC_MAX_KPENT];
@@ -260,6 +259,8 @@
unsigned int num_down = 0;
unsigned long flags;
bool fn_keypress = false;
+ bool key_in_same_row = false;
+ bool key_in_same_col = false;
spin_lock_irqsave(&kbc->lock, flags);
for (i = 0; i < KBC_MAX_KPENT; i++) {
@@ -285,6 +286,34 @@
}
/*
+ * Matrix keyboard designs are prone to keyboard ghosting.
+ * Ghosting occurs if there are 3 keys such that -
+ * any 2 of the 3 keys share a row, and any 2 of them share a column.
+ * If so ignore the key presses for this iteration.
+ */
+ if ((kbc->use_ghost_filter) && (num_down >= 3)) {
+ for (i = 0; i < num_down; i++) {
+ unsigned int j;
+ u8 curr_col = scancodes[i] & 0x07;
+ u8 curr_row = scancodes[i] >> KBC_ROW_SHIFT;
+
+ /*
+ * Find 2 keys such that one key is in the same row
+ * and the other is in the same column as the i-th key.
+ */
+ for (j = i + 1; j < num_down; j++) {
+ u8 col = scancodes[j] & 0x07;
+ u8 row = scancodes[j] >> KBC_ROW_SHIFT;
+
+ if (col == curr_col)
+ key_in_same_col = true;
+ if (row == curr_row)
+ key_in_same_row = true;
+ }
+ }
+ }
+
+ /*
* If the platform uses Fn keymaps, translate keys on a Fn keypress.
* Function keycodes are KBC_MAX_KEY apart from the plain keycodes.
*/
@@ -297,6 +326,10 @@
spin_unlock_irqrestore(&kbc->lock, flags);
+ /* Ignore the key presses for this iteration? */
+ if (key_in_same_col && key_in_same_row)
+ return;
+
tegra_kbc_report_released_keys(kbc->idev,
kbc->current_keys, kbc->num_pressed_keys,
keycodes, num_down);
@@ -383,21 +416,11 @@
int i;
unsigned int rst_val;
- BUG_ON(pdata->wake_cnt > KBC_MAX_KEY);
- rst_val = (filter && pdata->wake_cnt) ? ~0 : 0;
+ /* Either mask all keys or none. */
+ rst_val = (filter && !pdata->wakeup) ? ~0 : 0;
for (i = 0; i < KBC_MAX_ROW; i++)
writel(rst_val, kbc->mmio + KBC_ROW0_MASK_0 + i * 4);
-
- if (filter) {
- for (i = 0; i < pdata->wake_cnt; i++) {
- u32 val, addr;
- addr = pdata->wake_cfg[i].row * 4 + KBC_ROW0_MASK_0;
- val = readl(kbc->mmio + addr);
- val &= ~(1 << pdata->wake_cfg[i].col);
- writel(val, kbc->mmio + addr);
- }
- }
}
static void tegra_kbc_config_pins(struct tegra_kbc *kbc)
@@ -559,7 +582,6 @@
struct resource *res;
int irq;
int err;
- int i;
int num_rows = 0;
unsigned int debounce_cnt;
unsigned int scan_time_rows;
@@ -616,13 +638,6 @@
goto err_iounmap;
}
- kbc->wake_enable_rows = 0;
- kbc->wake_enable_cols = 0;
- for (i = 0; i < pdata->wake_cnt; i++) {
- kbc->wake_enable_rows |= (1 << pdata->wake_cfg[i].row);
- kbc->wake_enable_cols |= (1 << pdata->wake_cfg[i].col);
- }
-
/*
* The time delay between two consecutive reads of the FIFO is
* the sum of the repeat time and the time taken for scanning
@@ -652,6 +667,7 @@
input_dev->keycodemax *= 2;
kbc->use_fn_map = pdata->use_fn_map;
+ kbc->use_ghost_filter = pdata->use_ghost_filter;
keymap_data = pdata->keymap_data ?: &tegra_kbc_default_keymap_data;
matrix_keypad_build_keymap(keymap_data, KBC_ROW_SHIFT,
input_dev->keycode, input_dev->keybit);
diff --git a/drivers/input/misc/ad714x.c b/drivers/input/misc/ad714x.c
index c431d09..c3a62c4 100644
--- a/drivers/input/misc/ad714x.c
+++ b/drivers/input/misc/ad714x.c
@@ -79,13 +79,7 @@
struct ad714x_wheel_drv {
int abs_pos;
int flt_pos;
- int pre_mean_value;
int pre_highest_stage;
- int pre_mean_value_no_offset;
- int mean_value;
- int mean_value_no_offset;
- int pos_offset;
- int pos_ratio;
int highest_stage;
enum ad714x_device_state state;
struct input_dev *input;
@@ -158,10 +152,10 @@
unsigned short data;
unsigned short mask;
- mask = ((1 << (end_stage + 1)) - 1) - (1 << start_stage);
+ mask = ((1 << (end_stage + 1)) - 1) - ((1 << start_stage) - 1);
ad714x->read(ad714x->dev, STG_COM_INT_EN_REG, &data);
- data |= 1 << start_stage;
+ data |= 1 << end_stage;
ad714x->write(ad714x->dev, STG_COM_INT_EN_REG, data);
ad714x->read(ad714x->dev, STG_HIGH_INT_EN_REG, &data);
@@ -175,10 +169,10 @@
unsigned short data;
unsigned short mask;
- mask = ((1 << (end_stage + 1)) - 1) - (1 << start_stage);
+ mask = ((1 << (end_stage + 1)) - 1) - ((1 << start_stage) - 1);
ad714x->read(ad714x->dev, STG_COM_INT_EN_REG, &data);
- data &= ~(1 << start_stage);
+ data &= ~(1 << end_stage);
ad714x->write(ad714x->dev, STG_COM_INT_EN_REG, data);
ad714x->read(ad714x->dev, STG_HIGH_INT_EN_REG, &data);
@@ -404,7 +398,6 @@
ad714x_slider_cal_highest_stage(ad714x, idx);
ad714x_slider_cal_abs_pos(ad714x, idx);
ad714x_slider_cal_flt_pos(ad714x, idx);
-
input_report_abs(sw->input, ABS_X, sw->flt_pos);
input_report_key(sw->input, BTN_TOUCH, 1);
} else {
@@ -468,104 +461,41 @@
/*
* When the scroll wheel is activated, we compute the absolute position based
* on the sensor values. To calculate the position, we first determine the
- * sensor that has the greatest response among the 8 sensors that constitutes
- * the scrollwheel. Then we determined the 2 sensors on either sides of the
+ * sensor that has the greatest response among the sensors that constitutes
+ * the scrollwheel. Then we determined the sensors on either sides of the
* sensor with the highest response and we apply weights to these sensors. The
- * result of this computation gives us the mean value which defined by the
- * following formula:
- * For i= second_before_highest_stage to i= second_after_highest_stage
- * v += Sensor response(i)*WEIGHT*(i+3)
- * w += Sensor response(i)
- * Mean_Value=v/w
- * pos_on_scrollwheel = (Mean_Value - position_offset) / position_ratio
+ * result of this computation gives us the mean value.
*/
-#define WEIGHT_FACTOR 30
-/* This constant prevents the "PositionOffset" from reaching a big value */
-#define OFFSET_POSITION_CLAMP 120
static void ad714x_wheel_cal_abs_pos(struct ad714x_chip *ad714x, int idx)
{
struct ad714x_wheel_plat *hw = &ad714x->hw->wheel[idx];
struct ad714x_wheel_drv *sw = &ad714x->sw->wheel[idx];
int stage_num = hw->end_stage - hw->start_stage + 1;
- int second_before, first_before, highest, first_after, second_after;
+ int first_before, highest, first_after;
int a_param, b_param;
- /* Calculate Mean value */
-
- second_before = (sw->highest_stage + stage_num - 2) % stage_num;
first_before = (sw->highest_stage + stage_num - 1) % stage_num;
highest = sw->highest_stage;
first_after = (sw->highest_stage + stage_num + 1) % stage_num;
- second_after = (sw->highest_stage + stage_num + 2) % stage_num;
- if (((sw->highest_stage - hw->start_stage) > 1) &&
- ((hw->end_stage - sw->highest_stage) > 1)) {
- a_param = ad714x->sensor_val[second_before] *
- (second_before - hw->start_stage + 3) +
- ad714x->sensor_val[first_before] *
- (second_before - hw->start_stage + 3) +
- ad714x->sensor_val[highest] *
- (second_before - hw->start_stage + 3) +
- ad714x->sensor_val[first_after] *
- (first_after - hw->start_stage + 3) +
- ad714x->sensor_val[second_after] *
- (second_after - hw->start_stage + 3);
- } else {
- a_param = ad714x->sensor_val[second_before] *
- (second_before - hw->start_stage + 1) +
- ad714x->sensor_val[first_before] *
- (second_before - hw->start_stage + 2) +
- ad714x->sensor_val[highest] *
- (second_before - hw->start_stage + 3) +
- ad714x->sensor_val[first_after] *
- (first_after - hw->start_stage + 4) +
- ad714x->sensor_val[second_after] *
- (second_after - hw->start_stage + 5);
- }
- a_param *= WEIGHT_FACTOR;
-
- b_param = ad714x->sensor_val[second_before] +
+ a_param = ad714x->sensor_val[highest] *
+ (highest - hw->start_stage) +
+ ad714x->sensor_val[first_before] *
+ (highest - hw->start_stage - 1) +
+ ad714x->sensor_val[first_after] *
+ (highest - hw->start_stage + 1);
+ b_param = ad714x->sensor_val[highest] +
ad714x->sensor_val[first_before] +
- ad714x->sensor_val[highest] +
- ad714x->sensor_val[first_after] +
- ad714x->sensor_val[second_after];
+ ad714x->sensor_val[first_after];
- sw->pre_mean_value = sw->mean_value;
- sw->mean_value = a_param / b_param;
+ sw->abs_pos = ((hw->max_coord / (hw->end_stage - hw->start_stage)) *
+ a_param) / b_param;
- /* Calculate the offset */
-
- if ((sw->pre_highest_stage == hw->end_stage) &&
- (sw->highest_stage == hw->start_stage))
- sw->pos_offset = sw->mean_value;
- else if ((sw->pre_highest_stage == hw->start_stage) &&
- (sw->highest_stage == hw->end_stage))
- sw->pos_offset = sw->pre_mean_value;
-
- if (sw->pos_offset > OFFSET_POSITION_CLAMP)
- sw->pos_offset = OFFSET_POSITION_CLAMP;
-
- /* Calculate the mean value without the offset */
-
- sw->pre_mean_value_no_offset = sw->mean_value_no_offset;
- sw->mean_value_no_offset = sw->mean_value - sw->pos_offset;
- if (sw->mean_value_no_offset < 0)
- sw->mean_value_no_offset = 0;
-
- /* Calculate ratio to scale down to NUMBER_OF_WANTED_POSITIONS */
-
- if ((sw->pre_highest_stage == hw->end_stage) &&
- (sw->highest_stage == hw->start_stage))
- sw->pos_ratio = (sw->pre_mean_value_no_offset * 100) /
- hw->max_coord;
- else if ((sw->pre_highest_stage == hw->start_stage) &&
- (sw->highest_stage == hw->end_stage))
- sw->pos_ratio = (sw->mean_value_no_offset * 100) /
- hw->max_coord;
- sw->abs_pos = (sw->mean_value_no_offset * 100) / sw->pos_ratio;
if (sw->abs_pos > hw->max_coord)
sw->abs_pos = hw->max_coord;
+ else if (sw->abs_pos < 0)
+ sw->abs_pos = 0;
}
static void ad714x_wheel_cal_flt_pos(struct ad714x_chip *ad714x, int idx)
@@ -639,9 +569,8 @@
ad714x_wheel_cal_highest_stage(ad714x, idx);
ad714x_wheel_cal_abs_pos(ad714x, idx);
ad714x_wheel_cal_flt_pos(ad714x, idx);
-
input_report_abs(sw->input, ABS_WHEEL,
- sw->abs_pos);
+ sw->flt_pos);
input_report_key(sw->input, BTN_TOUCH, 1);
} else {
/* When the user lifts off the sensor, configure
@@ -1149,6 +1078,8 @@
input[alloc_idx]->id.bustype = bus_type;
input[alloc_idx]->id.product = ad714x->product;
input[alloc_idx]->id.version = ad714x->version;
+ input[alloc_idx]->name = "ad714x_captouch_slider";
+ input[alloc_idx]->dev.parent = dev;
error = input_register_device(input[alloc_idx]);
if (error)
@@ -1179,6 +1110,8 @@
input[alloc_idx]->id.bustype = bus_type;
input[alloc_idx]->id.product = ad714x->product;
input[alloc_idx]->id.version = ad714x->version;
+ input[alloc_idx]->name = "ad714x_captouch_wheel";
+ input[alloc_idx]->dev.parent = dev;
error = input_register_device(input[alloc_idx]);
if (error)
@@ -1212,6 +1145,8 @@
input[alloc_idx]->id.bustype = bus_type;
input[alloc_idx]->id.product = ad714x->product;
input[alloc_idx]->id.version = ad714x->version;
+ input[alloc_idx]->name = "ad714x_captouch_pad";
+ input[alloc_idx]->dev.parent = dev;
error = input_register_device(input[alloc_idx]);
if (error)
@@ -1240,6 +1175,8 @@
input[alloc_idx]->id.bustype = bus_type;
input[alloc_idx]->id.product = ad714x->product;
input[alloc_idx]->id.version = ad714x->version;
+ input[alloc_idx]->name = "ad714x_captouch_button";
+ input[alloc_idx]->dev.parent = dev;
error = input_register_device(input[alloc_idx]);
if (error)
@@ -1249,7 +1186,9 @@
}
error = request_threaded_irq(ad714x->irq, NULL, ad714x_interrupt_thread,
- IRQF_TRIGGER_FALLING, "ad714x_captouch", ad714x);
+ plat_data->irqflags ?
+ plat_data->irqflags : IRQF_TRIGGER_FALLING,
+ "ad714x_captouch", ad714x);
if (error) {
dev_err(dev, "can't allocate irq %d\n", ad714x->irq);
goto err_unreg_dev;
diff --git a/drivers/input/misc/ati_remote2.c b/drivers/input/misc/ati_remote2.c
index 9ccdb82..1de58e8 100644
--- a/drivers/input/misc/ati_remote2.c
+++ b/drivers/input/misc/ati_remote2.c
@@ -737,14 +737,17 @@
mutex_lock(&ati_remote2_mutex);
- if (mask != ar2->channel_mask && !ati_remote2_setup(ar2, mask))
- ar2->channel_mask = mask;
+ if (mask != ar2->channel_mask) {
+ r = ati_remote2_setup(ar2, mask);
+ if (!r)
+ ar2->channel_mask = mask;
+ }
mutex_unlock(&ati_remote2_mutex);
usb_autopm_put_interface(ar2->intf[0]);
- return count;
+ return r ? r : count;
}
static ssize_t ati_remote2_show_mode_mask(struct device *dev,
diff --git a/drivers/input/misc/rotary_encoder.c b/drivers/input/misc/rotary_encoder.c
index 7e64d01..2c8b84d 100644
--- a/drivers/input/misc/rotary_encoder.c
+++ b/drivers/input/misc/rotary_encoder.c
@@ -2,6 +2,7 @@
* rotary_encoder.c
*
* (c) 2009 Daniel Mack <daniel@caiaq.de>
+ * Copyright (C) 2011 Johan Hovold <jhovold@gmail.com>
*
* state machine code inspired by code from Tim Ruetz
*
@@ -38,52 +39,66 @@
bool armed;
unsigned char dir; /* 0 - clockwise, 1 - CCW */
+
+ char last_stable;
};
+static int rotary_encoder_get_state(struct rotary_encoder_platform_data *pdata)
+{
+ int a = !!gpio_get_value(pdata->gpio_a);
+ int b = !!gpio_get_value(pdata->gpio_b);
+
+ a ^= pdata->inverted_a;
+ b ^= pdata->inverted_b;
+
+ return ((a << 1) | b);
+}
+
+static void rotary_encoder_report_event(struct rotary_encoder *encoder)
+{
+ struct rotary_encoder_platform_data *pdata = encoder->pdata;
+
+ if (pdata->relative_axis) {
+ input_report_rel(encoder->input,
+ pdata->axis, encoder->dir ? -1 : 1);
+ } else {
+ unsigned int pos = encoder->pos;
+
+ if (encoder->dir) {
+ /* turning counter-clockwise */
+ if (pdata->rollover)
+ pos += pdata->steps;
+ if (pos)
+ pos--;
+ } else {
+ /* turning clockwise */
+ if (pdata->rollover || pos < pdata->steps)
+ pos++;
+ }
+
+ if (pdata->rollover)
+ pos %= pdata->steps;
+
+ encoder->pos = pos;
+ input_report_abs(encoder->input, pdata->axis, encoder->pos);
+ }
+
+ input_sync(encoder->input);
+}
+
static irqreturn_t rotary_encoder_irq(int irq, void *dev_id)
{
struct rotary_encoder *encoder = dev_id;
- struct rotary_encoder_platform_data *pdata = encoder->pdata;
- int a = !!gpio_get_value(pdata->gpio_a);
- int b = !!gpio_get_value(pdata->gpio_b);
int state;
- a ^= pdata->inverted_a;
- b ^= pdata->inverted_b;
- state = (a << 1) | b;
+ state = rotary_encoder_get_state(encoder->pdata);
switch (state) {
-
case 0x0:
- if (!encoder->armed)
- break;
-
- if (pdata->relative_axis) {
- input_report_rel(encoder->input, pdata->axis,
- encoder->dir ? -1 : 1);
- } else {
- unsigned int pos = encoder->pos;
-
- if (encoder->dir) {
- /* turning counter-clockwise */
- if (pdata->rollover)
- pos += pdata->steps;
- if (pos)
- pos--;
- } else {
- /* turning clockwise */
- if (pdata->rollover || pos < pdata->steps)
- pos++;
- }
- if (pdata->rollover)
- pos %= pdata->steps;
- encoder->pos = pos;
- input_report_abs(encoder->input, pdata->axis,
- encoder->pos);
+ if (encoder->armed) {
+ rotary_encoder_report_event(encoder);
+ encoder->armed = false;
}
- input_sync(encoder->input);
-
- encoder->armed = false;
break;
case 0x1:
@@ -100,11 +115,37 @@
return IRQ_HANDLED;
}
+static irqreturn_t rotary_encoder_half_period_irq(int irq, void *dev_id)
+{
+ struct rotary_encoder *encoder = dev_id;
+ int state;
+
+ state = rotary_encoder_get_state(encoder->pdata);
+
+ switch (state) {
+ case 0x00:
+ case 0x03:
+ if (state != encoder->last_stable) {
+ rotary_encoder_report_event(encoder);
+ encoder->last_stable = state;
+ }
+ break;
+
+ case 0x01:
+ case 0x02:
+ encoder->dir = (encoder->last_stable + state) & 0x01;
+ break;
+ }
+
+ return IRQ_HANDLED;
+}
+
static int __devinit rotary_encoder_probe(struct platform_device *pdev)
{
struct rotary_encoder_platform_data *pdata = pdev->dev.platform_data;
struct rotary_encoder *encoder;
struct input_dev *input;
+ irq_handler_t handler;
int err;
if (!pdata) {
@@ -175,7 +216,14 @@
}
/* request the IRQs */
- err = request_irq(encoder->irq_a, &rotary_encoder_irq,
+ if (pdata->half_period) {
+ handler = &rotary_encoder_half_period_irq;
+ encoder->last_stable = rotary_encoder_get_state(pdata);
+ } else {
+ handler = &rotary_encoder_irq;
+ }
+
+ err = request_irq(encoder->irq_a, handler,
IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
DRV_NAME, encoder);
if (err) {
@@ -184,7 +232,7 @@
goto exit_free_gpio_b;
}
- err = request_irq(encoder->irq_b, &rotary_encoder_irq,
+ err = request_irq(encoder->irq_b, handler,
IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
DRV_NAME, encoder);
if (err) {
@@ -252,6 +300,5 @@
MODULE_ALIAS("platform:" DRV_NAME);
MODULE_DESCRIPTION("GPIO rotary encoder driver");
-MODULE_AUTHOR("Daniel Mack <daniel@caiaq.de>");
+MODULE_AUTHOR("Daniel Mack <daniel@caiaq.de>, Johan Hovold");
MODULE_LICENSE("GPL v2");
-
diff --git a/drivers/input/misc/twl4030-pwrbutton.c b/drivers/input/misc/twl4030-pwrbutton.c
index f16972b..38e4b50 100644
--- a/drivers/input/misc/twl4030-pwrbutton.c
+++ b/drivers/input/misc/twl4030-pwrbutton.c
@@ -89,7 +89,7 @@
return 0;
free_irq:
- free_irq(irq, NULL);
+ free_irq(irq, pwr);
free_input_dev:
input_free_device(pwr);
return err;
diff --git a/drivers/input/mouse/elantech.c b/drivers/input/mouse/elantech.c
index 04d9bf3..3250356 100644
--- a/drivers/input/mouse/elantech.c
+++ b/drivers/input/mouse/elantech.c
@@ -16,6 +16,7 @@
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/input.h>
+#include <linux/input/mt.h>
#include <linux/serio.h>
#include <linux/libps2.h>
#include "psmouse.h"
@@ -242,15 +243,37 @@
input_sync(dev);
}
+static void elantech_set_slot(struct input_dev *dev, int slot, bool active,
+ unsigned int x, unsigned int y)
+{
+ input_mt_slot(dev, slot);
+ input_mt_report_slot_state(dev, MT_TOOL_FINGER, active);
+ if (active) {
+ input_report_abs(dev, ABS_MT_POSITION_X, x);
+ input_report_abs(dev, ABS_MT_POSITION_Y, y);
+ }
+}
+
+/* x1 < x2 and y1 < y2 when two fingers, x = y = 0 when not pressed */
+static void elantech_report_semi_mt_data(struct input_dev *dev,
+ unsigned int num_fingers,
+ unsigned int x1, unsigned int y1,
+ unsigned int x2, unsigned int y2)
+{
+ elantech_set_slot(dev, 0, num_fingers != 0, x1, y1);
+ elantech_set_slot(dev, 1, num_fingers == 2, x2, y2);
+}
+
/*
* Interpret complete data packets and report absolute mode input events for
* hardware version 2. (6 byte packets)
*/
static void elantech_report_absolute_v2(struct psmouse *psmouse)
{
+ struct elantech_data *etd = psmouse->private;
struct input_dev *dev = psmouse->dev;
unsigned char *packet = psmouse->packet;
- int fingers, x1, y1, x2, y2;
+ unsigned int fingers, x1 = 0, y1 = 0, x2 = 0, y2 = 0, width = 0, pres = 0;
/* byte 0: n1 n0 . . . . R L */
fingers = (packet[0] & 0xc0) >> 6;
@@ -270,14 +293,18 @@
* byte 1: . . . . . x10 x9 x8
* byte 2: x7 x6 x5 x4 x4 x2 x1 x0
*/
- input_report_abs(dev, ABS_X,
- ((packet[1] & 0x07) << 8) | packet[2]);
+ x1 = ((packet[1] & 0x07) << 8) | packet[2];
/*
* byte 4: . . . . . . y9 y8
* byte 5: y7 y6 y5 y4 y3 y2 y1 y0
*/
- input_report_abs(dev, ABS_Y,
- ETP_YMAX_V2 - (((packet[4] & 0x03) << 8) | packet[5]));
+ y1 = ETP_YMAX_V2 - (((packet[4] & 0x03) << 8) | packet[5]);
+
+ input_report_abs(dev, ABS_X, x1);
+ input_report_abs(dev, ABS_Y, y1);
+
+ pres = (packet[1] & 0xf0) | ((packet[4] & 0xf0) >> 4);
+ width = ((packet[0] & 0x30) >> 2) | ((packet[3] & 0x30) >> 4);
break;
case 2:
@@ -303,23 +330,24 @@
*/
input_report_abs(dev, ABS_X, x1 << 2);
input_report_abs(dev, ABS_Y, y1 << 2);
- /*
- * For compatibility with the proprietary X Elantech driver
- * report both coordinates as hat coordinates
- */
- input_report_abs(dev, ABS_HAT0X, x1);
- input_report_abs(dev, ABS_HAT0Y, y1);
- input_report_abs(dev, ABS_HAT1X, x2);
- input_report_abs(dev, ABS_HAT1Y, y2);
+
+ /* Unknown so just report sensible values */
+ pres = 127;
+ width = 7;
break;
}
+ elantech_report_semi_mt_data(dev, fingers, x1, y1, x2, y2);
input_report_key(dev, BTN_TOOL_FINGER, fingers == 1);
input_report_key(dev, BTN_TOOL_DOUBLETAP, fingers == 2);
input_report_key(dev, BTN_TOOL_TRIPLETAP, fingers == 3);
input_report_key(dev, BTN_TOOL_QUADTAP, fingers == 4);
input_report_key(dev, BTN_LEFT, packet[0] & 0x01);
input_report_key(dev, BTN_RIGHT, packet[0] & 0x02);
+ if (etd->reports_pressure) {
+ input_report_abs(dev, ABS_PRESSURE, pres);
+ input_report_abs(dev, ABS_TOOL_WIDTH, width);
+ }
input_sync(dev);
}
@@ -478,10 +506,16 @@
__set_bit(BTN_TOOL_QUADTAP, dev->keybit);
input_set_abs_params(dev, ABS_X, ETP_XMIN_V2, ETP_XMAX_V2, 0, 0);
input_set_abs_params(dev, ABS_Y, ETP_YMIN_V2, ETP_YMAX_V2, 0, 0);
- input_set_abs_params(dev, ABS_HAT0X, ETP_2FT_XMIN, ETP_2FT_XMAX, 0, 0);
- input_set_abs_params(dev, ABS_HAT0Y, ETP_2FT_YMIN, ETP_2FT_YMAX, 0, 0);
- input_set_abs_params(dev, ABS_HAT1X, ETP_2FT_XMIN, ETP_2FT_XMAX, 0, 0);
- input_set_abs_params(dev, ABS_HAT1Y, ETP_2FT_YMIN, ETP_2FT_YMAX, 0, 0);
+ if (etd->reports_pressure) {
+ input_set_abs_params(dev, ABS_PRESSURE, ETP_PMIN_V2,
+ ETP_PMAX_V2, 0, 0);
+ input_set_abs_params(dev, ABS_TOOL_WIDTH, ETP_WMIN_V2,
+ ETP_WMAX_V2, 0, 0);
+ }
+ __set_bit(INPUT_PROP_SEMI_MT, dev->propbit);
+ input_mt_init_slots(dev, 2);
+ input_set_abs_params(dev, ABS_MT_POSITION_X, ETP_XMIN_V2, ETP_XMAX_V2, 0, 0);
+ input_set_abs_params(dev, ABS_MT_POSITION_Y, ETP_YMIN_V2, ETP_YMAX_V2, 0, 0);
break;
}
}
@@ -725,6 +759,10 @@
etd->debug = 1;
/* Don't know how to do parity checking for version 2 */
etd->paritycheck = 0;
+
+ if (etd->fw_version >= 0x020800)
+ etd->reports_pressure = true;
+
} else {
etd->hw_version = 1;
etd->paritycheck = 1;
diff --git a/drivers/input/mouse/elantech.h b/drivers/input/mouse/elantech.h
index aa4aac5..fabb2b9 100644
--- a/drivers/input/mouse/elantech.h
+++ b/drivers/input/mouse/elantech.h
@@ -77,6 +77,11 @@
#define ETP_YMIN_V2 ( 0 + ETP_EDGE_FUZZ_V2)
#define ETP_YMAX_V2 ( 768 - ETP_EDGE_FUZZ_V2)
+#define ETP_PMIN_V2 0
+#define ETP_PMAX_V2 255
+#define ETP_WMIN_V2 0
+#define ETP_WMAX_V2 15
+
/*
* For two finger touches the coordinate of each finger gets reported
* separately but with reduced resolution.
@@ -102,6 +107,7 @@
unsigned char capabilities;
bool paritycheck;
bool jumpy_cursor;
+ bool reports_pressure;
unsigned char hw_version;
unsigned int fw_version;
unsigned int single_finger_reports;
diff --git a/drivers/input/mousedev.c b/drivers/input/mousedev.c
index 7630273..257e033 100644
--- a/drivers/input/mousedev.c
+++ b/drivers/input/mousedev.c
@@ -508,7 +508,6 @@
spin_lock(&mousedev->client_lock);
list_add_tail_rcu(&client->node, &mousedev->client_list);
spin_unlock(&mousedev->client_lock);
- synchronize_rcu();
}
static void mousedev_detach_client(struct mousedev *mousedev,
diff --git a/drivers/input/serio/serport.c b/drivers/input/serio/serport.c
index 8755f5f..f369896 100644
--- a/drivers/input/serio/serport.c
+++ b/drivers/input/serio/serport.c
@@ -120,17 +120,21 @@
* 'interrupt' routine.
*/
-static void serport_ldisc_receive(struct tty_struct *tty, const unsigned char *cp, char *fp, int count)
+static unsigned int serport_ldisc_receive(struct tty_struct *tty,
+ const unsigned char *cp, char *fp, int count)
{
struct serport *serport = (struct serport*) tty->disc_data;
unsigned long flags;
unsigned int ch_flags;
+ int ret = 0;
int i;
spin_lock_irqsave(&serport->lock, flags);
- if (!test_bit(SERPORT_ACTIVE, &serport->flags))
+ if (!test_bit(SERPORT_ACTIVE, &serport->flags)) {
+ ret = -EINVAL;
goto out;
+ }
for (i = 0; i < count; i++) {
switch (fp[i]) {
@@ -152,6 +156,8 @@
out:
spin_unlock_irqrestore(&serport->lock, flags);
+
+ return ret == 0 ? count : ret;
}
/*
diff --git a/drivers/input/touchscreen/Kconfig b/drivers/input/touchscreen/Kconfig
index 434fd80..cabd9e5 100644
--- a/drivers/input/touchscreen/Kconfig
+++ b/drivers/input/touchscreen/Kconfig
@@ -248,6 +248,18 @@
To compile this driver as a module, choose M here: the
module will be called lpc32xx_ts.
+config TOUCHSCREEN_MAX11801
+ tristate "MAX11801 based touchscreens"
+ depends on I2C
+ help
+ Say Y here if you have a MAX11801 based touchscreen
+ controller.
+
+ If unsure, say N.
+
+ To compile this driver as a module, choose M here: the
+ module will be called max11801_ts.
+
config TOUCHSCREEN_MCS5000
tristate "MELFAS MCS-5000 touchscreen"
depends on I2C
diff --git a/drivers/input/touchscreen/Makefile b/drivers/input/touchscreen/Makefile
index ca94098..282d6f7 100644
--- a/drivers/input/touchscreen/Makefile
+++ b/drivers/input/touchscreen/Makefile
@@ -27,6 +27,7 @@
obj-$(CONFIG_TOUCHSCREEN_INEXIO) += inexio.o
obj-$(CONFIG_TOUCHSCREEN_INTEL_MID) += intel-mid-touch.o
obj-$(CONFIG_TOUCHSCREEN_LPC32XX) += lpc32xx_ts.o
+obj-$(CONFIG_TOUCHSCREEN_MAX11801) += max11801_ts.o
obj-$(CONFIG_TOUCHSCREEN_MC13783) += mc13783_ts.o
obj-$(CONFIG_TOUCHSCREEN_MCS5000) += mcs5000_ts.o
obj-$(CONFIG_TOUCHSCREEN_MIGOR) += migor_ts.o
diff --git a/drivers/input/touchscreen/ads7846.c b/drivers/input/touchscreen/ads7846.c
index 1de1c19..5196861 100644
--- a/drivers/input/touchscreen/ads7846.c
+++ b/drivers/input/touchscreen/ads7846.c
@@ -109,6 +109,7 @@
u16 pressure_max;
bool swap_xy;
+ bool use_internal;
struct ads7846_packet *packet;
@@ -307,7 +308,6 @@
struct ads7846 *ts = dev_get_drvdata(dev);
struct ser_req *req;
int status;
- int use_internal;
req = kzalloc(sizeof *req, GFP_KERNEL);
if (!req)
@@ -315,11 +315,8 @@
spi_message_init(&req->msg);
- /* FIXME boards with ads7846 might use external vref instead ... */
- use_internal = (ts->model == 7846);
-
/* maybe turn on internal vREF, and let it settle */
- if (use_internal) {
+ if (ts->use_internal) {
req->ref_on = REF_ON;
req->xfer[0].tx_buf = &req->ref_on;
req->xfer[0].len = 1;
@@ -331,8 +328,14 @@
/* for 1uF, settle for 800 usec; no cap, 100 usec. */
req->xfer[1].delay_usecs = ts->vref_delay_usecs;
spi_message_add_tail(&req->xfer[1], &req->msg);
+
+ /* Enable reference voltage */
+ command |= ADS_PD10_REF_ON;
}
+ /* Enable ADC in every case */
+ command |= ADS_PD10_ADC_ON;
+
/* take sample */
req->command = (u8) command;
req->xfer[2].tx_buf = &req->command;
@@ -416,7 +419,7 @@
{ \
struct ads7846 *ts = dev_get_drvdata(dev); \
ssize_t v = ads7846_read12_ser(dev, \
- READ_12BIT_SER(var) | ADS_PD10_ALL_ON); \
+ READ_12BIT_SER(var)); \
if (v < 0) \
return v; \
return sprintf(buf, "%u\n", adjust(ts, v)); \
@@ -509,6 +512,7 @@
if (!ts->vref_mv) {
dev_dbg(&spi->dev, "assuming 2.5V internal vREF\n");
ts->vref_mv = 2500;
+ ts->use_internal = true;
}
break;
case 7845:
@@ -969,6 +973,13 @@
pdata->gpio_pendown);
return err;
}
+ err = gpio_direction_input(pdata->gpio_pendown);
+ if (err) {
+ dev_err(&spi->dev, "failed to setup pendown GPIO%d\n",
+ pdata->gpio_pendown);
+ gpio_free(pdata->gpio_pendown);
+ return err;
+ }
ts->gpio_pendown = pdata->gpio_pendown;
@@ -1340,8 +1351,7 @@
if (ts->model == 7845)
ads7845_read12_ser(&spi->dev, PWRDOWN);
else
- (void) ads7846_read12_ser(&spi->dev,
- READ_12BIT_SER(vaux) | ADS_PD10_ALL_ON);
+ (void) ads7846_read12_ser(&spi->dev, READ_12BIT_SER(vaux));
err = sysfs_create_group(&spi->dev.kobj, &ads784x_attr_group);
if (err)
diff --git a/drivers/input/touchscreen/atmel_mxt_ts.c b/drivers/input/touchscreen/atmel_mxt_ts.c
index 4012436..1e61387 100644
--- a/drivers/input/touchscreen/atmel_mxt_ts.c
+++ b/drivers/input/touchscreen/atmel_mxt_ts.c
@@ -17,7 +17,7 @@
#include <linux/firmware.h>
#include <linux/i2c.h>
#include <linux/i2c/atmel_mxt_ts.h>
-#include <linux/input.h>
+#include <linux/input/mt.h>
#include <linux/interrupt.h>
#include <linux/slab.h>
@@ -196,9 +196,12 @@
#define MXT_PRESS (1 << 6)
#define MXT_DETECT (1 << 7)
+/* Touch orient bits */
+#define MXT_XY_SWITCH (1 << 0)
+#define MXT_X_INVERT (1 << 1)
+#define MXT_Y_INVERT (1 << 2)
+
/* Touchscreen absolute values */
-#define MXT_MAX_XC 0x3ff
-#define MXT_MAX_YC 0x3ff
#define MXT_MAX_AREA 0xff
#define MXT_MAX_FINGER 10
@@ -246,6 +249,8 @@
struct mxt_info info;
struct mxt_finger finger[MXT_MAX_FINGER];
unsigned int irq;
+ unsigned int max_x;
+ unsigned int max_y;
};
static bool mxt_object_readable(unsigned int type)
@@ -499,19 +504,21 @@
if (!finger[id].status)
continue;
- input_report_abs(input_dev, ABS_MT_TOUCH_MAJOR,
- finger[id].status != MXT_RELEASE ?
- finger[id].area : 0);
- input_report_abs(input_dev, ABS_MT_POSITION_X,
- finger[id].x);
- input_report_abs(input_dev, ABS_MT_POSITION_Y,
- finger[id].y);
- input_mt_sync(input_dev);
+ input_mt_slot(input_dev, id);
+ input_mt_report_slot_state(input_dev, MT_TOOL_FINGER,
+ finger[id].status != MXT_RELEASE);
- if (finger[id].status == MXT_RELEASE)
- finger[id].status = 0;
- else
+ if (finger[id].status != MXT_RELEASE) {
finger_num++;
+ input_report_abs(input_dev, ABS_MT_TOUCH_MAJOR,
+ finger[id].area);
+ input_report_abs(input_dev, ABS_MT_POSITION_X,
+ finger[id].x);
+ input_report_abs(input_dev, ABS_MT_POSITION_Y,
+ finger[id].y);
+ } else {
+ finger[id].status = 0;
+ }
}
input_report_key(input_dev, BTN_TOUCH, finger_num > 0);
@@ -549,8 +556,13 @@
if (!(status & (MXT_PRESS | MXT_MOVE)))
return;
- x = (message->message[1] << 2) | ((message->message[3] & ~0x3f) >> 6);
- y = (message->message[2] << 2) | ((message->message[3] & ~0xf3) >> 2);
+ x = (message->message[1] << 4) | ((message->message[3] >> 4) & 0xf);
+ y = (message->message[2] << 4) | ((message->message[3] & 0xf));
+ if (data->max_x < 1024)
+ x = x >> 2;
+ if (data->max_y < 1024)
+ y = y >> 2;
+
area = message->message[4];
dev_dbg(dev, "[%d] %s x: %d, y: %d, area: %d\n", id,
@@ -804,10 +816,6 @@
if (error)
return error;
- error = mxt_make_highchg(data);
- if (error)
- return error;
-
mxt_handle_pdata(data);
/* Backup to memory */
@@ -845,6 +853,20 @@
return 0;
}
+static void mxt_calc_resolution(struct mxt_data *data)
+{
+ unsigned int max_x = data->pdata->x_size - 1;
+ unsigned int max_y = data->pdata->y_size - 1;
+
+ if (data->pdata->orient & MXT_XY_SWITCH) {
+ data->max_x = max_y;
+ data->max_y = max_x;
+ } else {
+ data->max_x = max_x;
+ data->max_y = max_y;
+ }
+}
+
static ssize_t mxt_object_show(struct device *dev,
struct device_attribute *attr, char *buf)
{
@@ -981,6 +1003,10 @@
enable_irq(data->irq);
+ error = mxt_make_highchg(data);
+ if (error)
+ return error;
+
return count;
}
@@ -1052,31 +1078,33 @@
input_dev->open = mxt_input_open;
input_dev->close = mxt_input_close;
+ data->client = client;
+ data->input_dev = input_dev;
+ data->pdata = pdata;
+ data->irq = client->irq;
+
+ mxt_calc_resolution(data);
+
__set_bit(EV_ABS, input_dev->evbit);
__set_bit(EV_KEY, input_dev->evbit);
__set_bit(BTN_TOUCH, input_dev->keybit);
/* For single touch */
input_set_abs_params(input_dev, ABS_X,
- 0, MXT_MAX_XC, 0, 0);
+ 0, data->max_x, 0, 0);
input_set_abs_params(input_dev, ABS_Y,
- 0, MXT_MAX_YC, 0, 0);
+ 0, data->max_y, 0, 0);
/* For multi touch */
+ input_mt_init_slots(input_dev, MXT_MAX_FINGER);
input_set_abs_params(input_dev, ABS_MT_TOUCH_MAJOR,
0, MXT_MAX_AREA, 0, 0);
input_set_abs_params(input_dev, ABS_MT_POSITION_X,
- 0, MXT_MAX_XC, 0, 0);
+ 0, data->max_x, 0, 0);
input_set_abs_params(input_dev, ABS_MT_POSITION_Y,
- 0, MXT_MAX_YC, 0, 0);
+ 0, data->max_y, 0, 0);
input_set_drvdata(input_dev, data);
-
- data->client = client;
- data->input_dev = input_dev;
- data->pdata = pdata;
- data->irq = client->irq;
-
i2c_set_clientdata(client, data);
error = mxt_initialize(data);
@@ -1090,6 +1118,10 @@
goto err_free_object;
}
+ error = mxt_make_highchg(data);
+ if (error)
+ goto err_free_irq;
+
error = input_register_device(input_dev);
if (error)
goto err_free_irq;
diff --git a/drivers/input/touchscreen/atmel_tsadcc.c b/drivers/input/touchscreen/atmel_tsadcc.c
index 3d9b516..432c69b 100644
--- a/drivers/input/touchscreen/atmel_tsadcc.c
+++ b/drivers/input/touchscreen/atmel_tsadcc.c
@@ -317,7 +317,7 @@
err_release_mem:
release_mem_region(res->start, resource_size(res));
err_free_dev:
- input_free_device(ts_dev->input);
+ input_free_device(input_dev);
err_free_mem:
kfree(ts_dev);
return err;
diff --git a/drivers/input/touchscreen/h3600_ts_input.c b/drivers/input/touchscreen/h3600_ts_input.c
index 45f93d0..211811a 100644
--- a/drivers/input/touchscreen/h3600_ts_input.c
+++ b/drivers/input/touchscreen/h3600_ts_input.c
@@ -396,14 +396,14 @@
set_GPIO_IRQ_edge(GPIO_BITSY_NPOWER_BUTTON, GPIO_RISING_EDGE);
if (request_irq(IRQ_GPIO_BITSY_ACTION_BUTTON, action_button_handler,
- IRQF_SHARED | IRQF_DISABLED, "h3600_action", &ts->dev)) {
+ IRQF_SHARED | IRQF_DISABLED, "h3600_action", ts->dev)) {
printk(KERN_ERR "h3600ts.c: Could not allocate Action Button IRQ!\n");
err = -EBUSY;
goto fail1;
}
if (request_irq(IRQ_GPIO_BITSY_NPOWER_BUTTON, npower_button_handler,
- IRQF_SHARED | IRQF_DISABLED, "h3600_suspend", &ts->dev)) {
+ IRQF_SHARED | IRQF_DISABLED, "h3600_suspend", ts->dev)) {
printk(KERN_ERR "h3600ts.c: Could not allocate Power Button IRQ!\n");
err = -EBUSY;
goto fail2;
@@ -439,8 +439,8 @@
{
struct h3600_dev *ts = serio_get_drvdata(serio);
- free_irq(IRQ_GPIO_BITSY_ACTION_BUTTON, &ts->dev);
- free_irq(IRQ_GPIO_BITSY_NPOWER_BUTTON, &ts->dev);
+ free_irq(IRQ_GPIO_BITSY_ACTION_BUTTON, ts->dev);
+ free_irq(IRQ_GPIO_BITSY_NPOWER_BUTTON, ts->dev);
input_get_device(ts->dev);
input_unregister_device(ts->dev);
serio_close(serio);
diff --git a/drivers/input/touchscreen/max11801_ts.c b/drivers/input/touchscreen/max11801_ts.c
new file mode 100644
index 0000000..4f2713d
--- /dev/null
+++ b/drivers/input/touchscreen/max11801_ts.c
@@ -0,0 +1,272 @@
+/*
+ * Driver for MAXI MAX11801 - A Resistive touch screen controller with
+ * i2c interface
+ *
+ * Copyright (C) 2011 Freescale Semiconductor, Inc.
+ * Author: Zhang Jiejing <jiejing.zhang@freescale.com>
+ *
+ * Based on mcs5000_ts.c
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License.
+ */
+
+/*
+ * This driver aims to support the series of MAXI touch chips max11801
+ * through max11803. The main difference between these 4 chips can be
+ * found in the table below:
+ * -----------------------------------------------------
+ * | CHIP | AUTO MODE SUPPORT(FIFO) | INTERFACE |
+ * |----------------------------------------------------|
+ * | max11800 | YES | SPI |
+ * | max11801 | YES | I2C |
+ * | max11802 | NO | SPI |
+ * | max11803 | NO | I2C |
+ * ------------------------------------------------------
+ *
+ * Currently, this driver only supports max11801.
+ *
+ * Data Sheet:
+ * http://www.maxim-ic.com/datasheet/index.mvp/id/5943
+ */
+
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/i2c.h>
+#include <linux/interrupt.h>
+#include <linux/input.h>
+#include <linux/slab.h>
+#include <linux/bitops.h>
+
+/* Register Address define */
+#define GENERNAL_STATUS_REG 0x00
+#define GENERNAL_CONF_REG 0x01
+#define MESURE_RES_CONF_REG 0x02
+#define MESURE_AVER_CONF_REG 0x03
+#define ADC_SAMPLE_TIME_CONF_REG 0x04
+#define PANEL_SETUPTIME_CONF_REG 0x05
+#define DELAY_CONVERSION_CONF_REG 0x06
+#define TOUCH_DETECT_PULLUP_CONF_REG 0x07
+#define AUTO_MODE_TIME_CONF_REG 0x08 /* only for max11800/max11801 */
+#define APERTURE_CONF_REG 0x09 /* only for max11800/max11801 */
+#define AUX_MESURE_CONF_REG 0x0a
+#define OP_MODE_CONF_REG 0x0b
+
+/* FIFO is found only in max11800 and max11801 */
+#define FIFO_RD_CMD (0x50 << 1)
+#define MAX11801_FIFO_INT (1 << 2)
+#define MAX11801_FIFO_OVERFLOW (1 << 3)
+
+#define XY_BUFSIZE 4
+#define XY_BUF_OFFSET 4
+
+#define MAX11801_MAX_X 0xfff
+#define MAX11801_MAX_Y 0xfff
+
+#define MEASURE_TAG_OFFSET 2
+#define MEASURE_TAG_MASK (3 << MEASURE_TAG_OFFSET)
+#define EVENT_TAG_OFFSET 0
+#define EVENT_TAG_MASK (3 << EVENT_TAG_OFFSET)
+#define MEASURE_X_TAG (0 << MEASURE_TAG_OFFSET)
+#define MEASURE_Y_TAG (1 << MEASURE_TAG_OFFSET)
+
+/* These are the state of touch event state machine */
+enum {
+ EVENT_INIT,
+ EVENT_MIDDLE,
+ EVENT_RELEASE,
+ EVENT_FIFO_END
+};
+
+struct max11801_data {
+ struct i2c_client *client;
+ struct input_dev *input_dev;
+};
+
+static u8 read_register(struct i2c_client *client, int addr)
+{
+ /* XXX: The chip ignores LSB of register address */
+ return i2c_smbus_read_byte_data(client, addr << 1);
+}
+
+static int max11801_write_reg(struct i2c_client *client, int addr, int data)
+{
+ /* XXX: The chip ignores LSB of register address */
+ return i2c_smbus_write_byte_data(client, addr << 1, data);
+}
+
+static irqreturn_t max11801_ts_interrupt(int irq, void *dev_id)
+{
+ struct max11801_data *data = dev_id;
+ struct i2c_client *client = data->client;
+ int status, i, ret;
+ u8 buf[XY_BUFSIZE];
+ int x = -1;
+ int y = -1;
+
+ status = read_register(data->client, GENERNAL_STATUS_REG);
+
+ if (status & (MAX11801_FIFO_INT | MAX11801_FIFO_OVERFLOW)) {
+ status = read_register(data->client, GENERNAL_STATUS_REG);
+
+ ret = i2c_smbus_read_i2c_block_data(client, FIFO_RD_CMD,
+ XY_BUFSIZE, buf);
+
+ /*
+ * We should get 4 bytes buffer that contains X,Y
+ * and event tag
+ */
+ if (ret < XY_BUFSIZE)
+ goto out;
+
+ for (i = 0; i < XY_BUFSIZE; i += XY_BUFSIZE / 2) {
+ if ((buf[i + 1] & MEASURE_TAG_MASK) == MEASURE_X_TAG)
+ x = (buf[i] << XY_BUF_OFFSET) +
+ (buf[i + 1] >> XY_BUF_OFFSET);
+ else if ((buf[i + 1] & MEASURE_TAG_MASK) == MEASURE_Y_TAG)
+ y = (buf[i] << XY_BUF_OFFSET) +
+ (buf[i + 1] >> XY_BUF_OFFSET);
+ }
+
+ if ((buf[1] & EVENT_TAG_MASK) != (buf[3] & EVENT_TAG_MASK))
+ goto out;
+
+ switch (buf[1] & EVENT_TAG_MASK) {
+ case EVENT_INIT:
+ /* fall through */
+ case EVENT_MIDDLE:
+ input_report_abs(data->input_dev, ABS_X, x);
+ input_report_abs(data->input_dev, ABS_Y, y);
+ input_event(data->input_dev, EV_KEY, BTN_TOUCH, 1);
+ input_sync(data->input_dev);
+ break;
+
+ case EVENT_RELEASE:
+ input_event(data->input_dev, EV_KEY, BTN_TOUCH, 0);
+ input_sync(data->input_dev);
+ break;
+
+ case EVENT_FIFO_END:
+ break;
+ }
+ }
+out:
+ return IRQ_HANDLED;
+}
+
+static void __devinit max11801_ts_phy_init(struct max11801_data *data)
+{
+ struct i2c_client *client = data->client;
+
+ /* Average X,Y, take 16 samples, average eight media sample */
+ max11801_write_reg(client, MESURE_AVER_CONF_REG, 0xff);
+ /* X,Y panel setup time set to 20us */
+ max11801_write_reg(client, PANEL_SETUPTIME_CONF_REG, 0x11);
+ /* Rough pullup time (2uS), Fine pullup time (10us) */
+ max11801_write_reg(client, TOUCH_DETECT_PULLUP_CONF_REG, 0x10);
+ /* Auto mode init period = 5ms , scan period = 5ms*/
+ max11801_write_reg(client, AUTO_MODE_TIME_CONF_REG, 0xaa);
+ /* Aperture X,Y set to +- 4LSB */
+ max11801_write_reg(client, APERTURE_CONF_REG, 0x33);
+ /* Enable Power, enable Automode, enable Aperture, enable Average X,Y */
+ max11801_write_reg(client, OP_MODE_CONF_REG, 0x36);
+}
+
+static int __devinit max11801_ts_probe(struct i2c_client *client,
+ const struct i2c_device_id *id)
+{
+ struct max11801_data *data;
+ struct input_dev *input_dev;
+ int error;
+
+ data = kzalloc(sizeof(struct max11801_data), GFP_KERNEL);
+ input_dev = input_allocate_device();
+ if (!data || !input_dev) {
+ dev_err(&client->dev, "Failed to allocate memory\n");
+ error = -ENOMEM;
+ goto err_free_mem;
+ }
+
+ data->client = client;
+ data->input_dev = input_dev;
+
+ input_dev->name = "max11801_ts";
+ input_dev->id.bustype = BUS_I2C;
+ input_dev->dev.parent = &client->dev;
+
+ __set_bit(EV_ABS, input_dev->evbit);
+ __set_bit(EV_KEY, input_dev->evbit);
+ __set_bit(BTN_TOUCH, input_dev->keybit);
+ input_set_abs_params(input_dev, ABS_X, 0, MAX11801_MAX_X, 0, 0);
+ input_set_abs_params(input_dev, ABS_Y, 0, MAX11801_MAX_Y, 0, 0);
+ input_set_drvdata(input_dev, data);
+
+ max11801_ts_phy_init(data);
+
+ error = request_threaded_irq(client->irq, NULL, max11801_ts_interrupt,
+ IRQF_TRIGGER_LOW | IRQF_ONESHOT,
+ "max11801_ts", data);
+ if (error) {
+ dev_err(&client->dev, "Failed to register interrupt\n");
+ goto err_free_mem;
+ }
+
+ error = input_register_device(data->input_dev);
+ if (error)
+ goto err_free_irq;
+
+ i2c_set_clientdata(client, data);
+ return 0;
+
+err_free_irq:
+ free_irq(client->irq, data);
+err_free_mem:
+ input_free_device(input_dev);
+ kfree(data);
+ return error;
+}
+
+static __devexit int max11801_ts_remove(struct i2c_client *client)
+{
+ struct max11801_data *data = i2c_get_clientdata(client);
+
+ free_irq(client->irq, data);
+ input_unregister_device(data->input_dev);
+ kfree(data);
+
+ return 0;
+}
+
+static const struct i2c_device_id max11801_ts_id[] = {
+ {"max11801", 0},
+ { }
+};
+MODULE_DEVICE_TABLE(i2c, max11801_ts_id);
+
+static struct i2c_driver max11801_ts_driver = {
+ .driver = {
+ .name = "max11801_ts",
+ .owner = THIS_MODULE,
+ },
+ .id_table = max11801_ts_id,
+ .probe = max11801_ts_probe,
+ .remove = __devexit_p(max11801_ts_remove),
+};
+
+static int __init max11801_ts_init(void)
+{
+ return i2c_add_driver(&max11801_ts_driver);
+}
+
+static void __exit max11801_ts_exit(void)
+{
+ i2c_del_driver(&max11801_ts_driver);
+}
+
+module_init(max11801_ts_init);
+module_exit(max11801_ts_exit);
+
+MODULE_AUTHOR("Zhang Jiejing <jiejing.zhang@freescale.com>");
+MODULE_DESCRIPTION("Touchscreen driver for MAXI MAX11801 controller");
+MODULE_LICENSE("GPL");
diff --git a/drivers/input/touchscreen/tsc2007.c b/drivers/input/touchscreen/tsc2007.c
index 80467f2..fadc115 100644
--- a/drivers/input/touchscreen/tsc2007.c
+++ b/drivers/input/touchscreen/tsc2007.c
@@ -27,9 +27,6 @@
#include <linux/i2c.h>
#include <linux/i2c/tsc2007.h>
-#define TS_POLL_DELAY 1 /* ms delay between samples */
-#define TS_POLL_PERIOD 1 /* ms delay between samples */
-
#define TSC2007_MEASURE_TEMP0 (0x0 << 4)
#define TSC2007_MEASURE_AUX (0x2 << 4)
#define TSC2007_MEASURE_TEMP1 (0x4 << 4)
@@ -75,6 +72,9 @@
u16 model;
u16 x_plate_ohms;
+ u16 max_rt;
+ unsigned long poll_delay;
+ unsigned long poll_period;
bool pendown;
int irq;
@@ -156,6 +156,7 @@
{
struct tsc2007 *ts =
container_of(to_delayed_work(work), struct tsc2007, work);
+ bool debounced = false;
struct ts_event tc;
u32 rt;
@@ -184,13 +185,14 @@
tsc2007_read_values(ts, &tc);
rt = tsc2007_calculate_pressure(ts, &tc);
- if (rt > MAX_12BIT) {
+ if (rt > ts->max_rt) {
/*
* Sample found inconsistent by debouncing or pressure is
* beyond the maximum. Don't report it to user space,
* repeat at least once more the measurement.
*/
dev_dbg(&ts->client->dev, "ignored pressure %d\n", rt);
+ debounced = true;
goto out;
}
@@ -225,9 +227,9 @@
}
out:
- if (ts->pendown)
+ if (ts->pendown || debounced)
schedule_delayed_work(&ts->work,
- msecs_to_jiffies(TS_POLL_PERIOD));
+ msecs_to_jiffies(ts->poll_period));
else
enable_irq(ts->irq);
}
@@ -239,7 +241,7 @@
if (!ts->get_pendown_state || likely(ts->get_pendown_state())) {
disable_irq_nosync(ts->irq);
schedule_delayed_work(&ts->work,
- msecs_to_jiffies(TS_POLL_DELAY));
+ msecs_to_jiffies(ts->poll_delay));
}
if (ts->clear_penirq)
@@ -292,6 +294,9 @@
ts->model = pdata->model;
ts->x_plate_ohms = pdata->x_plate_ohms;
+ ts->max_rt = pdata->max_rt ? : MAX_12BIT;
+ ts->poll_delay = pdata->poll_delay ? : 1;
+ ts->poll_period = pdata->poll_period ? : 1;
ts->get_pendown_state = pdata->get_pendown_state;
ts->clear_penirq = pdata->clear_penirq;
@@ -305,9 +310,10 @@
input_dev->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_ABS);
input_dev->keybit[BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH);
- input_set_abs_params(input_dev, ABS_X, 0, MAX_12BIT, 0, 0);
- input_set_abs_params(input_dev, ABS_Y, 0, MAX_12BIT, 0, 0);
- input_set_abs_params(input_dev, ABS_PRESSURE, 0, MAX_12BIT, 0, 0);
+ input_set_abs_params(input_dev, ABS_X, 0, MAX_12BIT, pdata->fuzzx, 0);
+ input_set_abs_params(input_dev, ABS_Y, 0, MAX_12BIT, pdata->fuzzy, 0);
+ input_set_abs_params(input_dev, ABS_PRESSURE, 0, MAX_12BIT,
+ pdata->fuzzz, 0);
if (pdata->init_platform_hw)
pdata->init_platform_hw();
diff --git a/drivers/isdn/gigaset/ser-gigaset.c b/drivers/isdn/gigaset/ser-gigaset.c
index 86a5c4f..1d44d47 100644
--- a/drivers/isdn/gigaset/ser-gigaset.c
+++ b/drivers/isdn/gigaset/ser-gigaset.c
@@ -674,7 +674,7 @@
* cflags buffer containing error flags for received characters (ignored)
* count number of received characters
*/
-static void
+static unsigned int
gigaset_tty_receive(struct tty_struct *tty, const unsigned char *buf,
char *cflags, int count)
{
@@ -683,12 +683,12 @@
struct inbuf_t *inbuf;
if (!cs)
- return;
+ return -ENODEV;
inbuf = cs->inbuf;
if (!inbuf) {
dev_err(cs->dev, "%s: no inbuf\n", __func__);
cs_put(cs);
- return;
+ return -EINVAL;
}
tail = inbuf->tail;
@@ -725,6 +725,8 @@
gig_dbg(DEBUG_INTR, "%s-->BH", __func__);
gigaset_schedule_event(cs);
cs_put(cs);
+
+ return count;
}
/*
diff --git a/drivers/isdn/hardware/avm/avm_cs.c b/drivers/isdn/hardware/avm/avm_cs.c
index 91f06a3..61f516f 100644
--- a/drivers/isdn/hardware/avm/avm_cs.c
+++ b/drivers/isdn/hardware/avm/avm_cs.c
@@ -149,7 +149,7 @@
} /* avmcs_release */
-static struct pcmcia_device_id avmcs_ids[] = {
+static const struct pcmcia_device_id avmcs_ids[] = {
PCMCIA_DEVICE_PROD_ID12("AVM", "ISDN-Controller B1", 0x95d42008, 0x845dc335),
PCMCIA_DEVICE_PROD_ID12("AVM", "Mobile ISDN-Controller M1", 0x95d42008, 0x81e10430),
PCMCIA_DEVICE_PROD_ID12("AVM", "Mobile ISDN-Controller M2", 0x95d42008, 0x18e8558a),
diff --git a/drivers/isdn/hisax/avma1_cs.c b/drivers/isdn/hisax/avma1_cs.c
index ac4dd78..8f0ad2a 100644
--- a/drivers/isdn/hisax/avma1_cs.c
+++ b/drivers/isdn/hisax/avma1_cs.c
@@ -146,7 +146,7 @@
pcmcia_disable_device(link);
} /* avma1cs_release */
-static struct pcmcia_device_id avma1cs_ids[] = {
+static const struct pcmcia_device_id avma1cs_ids[] = {
PCMCIA_DEVICE_PROD_ID12("AVM", "ISDN A", 0x95d42008, 0xadc9d4bb),
PCMCIA_DEVICE_PROD_ID12("ISDN", "CARD", 0x8d9761c8, 0x01c5aa7b),
PCMCIA_DEVICE_NULL
diff --git a/drivers/isdn/hisax/elsa_cs.c b/drivers/isdn/hisax/elsa_cs.c
index 9e5e87b..f0b6c0e 100644
--- a/drivers/isdn/hisax/elsa_cs.c
+++ b/drivers/isdn/hisax/elsa_cs.c
@@ -200,7 +200,7 @@
return 0;
}
-static struct pcmcia_device_id elsa_ids[] = {
+static const struct pcmcia_device_id elsa_ids[] = {
PCMCIA_DEVICE_PROD_ID12("ELSA AG (Aachen, Germany)", "MicroLink ISDN/MC ", 0x983de2c4, 0x333ba257),
PCMCIA_DEVICE_PROD_ID12("ELSA GmbH, Aachen", "MicroLink ISDN/MC ", 0x639e5718, 0x333ba257),
PCMCIA_DEVICE_NULL
diff --git a/drivers/isdn/hisax/sedlbauer_cs.c b/drivers/isdn/hisax/sedlbauer_cs.c
index 360204b..06473f8 100644
--- a/drivers/isdn/hisax/sedlbauer_cs.c
+++ b/drivers/isdn/hisax/sedlbauer_cs.c
@@ -186,7 +186,7 @@
}
-static struct pcmcia_device_id sedlbauer_ids[] = {
+static const struct pcmcia_device_id sedlbauer_ids[] = {
PCMCIA_DEVICE_PROD_ID123("SEDLBAUER", "speed star II", "V 3.1", 0x81fb79f5, 0xf3612e1d, 0x6b95c78a),
PCMCIA_DEVICE_PROD_ID123("SEDLBAUER", "ISDN-Adapter", "4D67", 0x81fb79f5, 0xe4e9bc12, 0x397b7e90),
PCMCIA_DEVICE_PROD_ID123("SEDLBAUER", "ISDN-Adapter", "4D98", 0x81fb79f5, 0xe4e9bc12, 0x2e5c7fce),
diff --git a/drivers/isdn/hisax/teles_cs.c b/drivers/isdn/hisax/teles_cs.c
index 360f9ec..161a193 100644
--- a/drivers/isdn/hisax/teles_cs.c
+++ b/drivers/isdn/hisax/teles_cs.c
@@ -183,7 +183,7 @@
}
-static struct pcmcia_device_id teles_ids[] = {
+static const struct pcmcia_device_id teles_ids[] = {
PCMCIA_DEVICE_PROD_ID12("TELES", "S0/PC", 0x67b50eae, 0xe9e70119),
PCMCIA_DEVICE_NULL,
};
diff --git a/drivers/leds/Kconfig b/drivers/leds/Kconfig
index 9bec869..1d027b4 100644
--- a/drivers/leds/Kconfig
+++ b/drivers/leds/Kconfig
@@ -14,6 +14,13 @@
This option enables the led sysfs class in /sys/class/leds. You'll
need this to do anything useful with LEDs. If unsure, say N.
+config LEDS_GPIO_REGISTER
+ bool
+ help
+ This option provides the function gpio_led_register_device.
+ As this function is used by arch code it must not be compiled as a
+ module.
+
if NEW_LEDS
comment "LED drivers"
@@ -115,13 +122,6 @@
This option enables support for the PCEngines ALIX.2 and ALIX.3 LEDs.
You have to set leds-alix2.force=1 for boards with Award BIOS.
-config LEDS_H1940
- tristate "LED Support for iPAQ H1940 device"
- depends on LEDS_CLASS
- depends on ARCH_H1940
- help
- This option enables support for the LEDs on the h1940.
-
config LEDS_COBALT_QUBE
tristate "LED Support for the Cobalt Qube series front LED"
depends on LEDS_CLASS
@@ -162,6 +162,16 @@
LED controller. It is generally only useful
as a platform driver
+config LEDS_PCA9532_GPIO
+ bool "Enable GPIO support for PCA9532"
+ depends on LEDS_PCA9532
+ depends on GPIOLIB
+ help
+ Allow unused pins on PCA9532 to be used as gpio.
+
+ To use a pin as gpio pca9532_type in pca9532_platform data needs to
+ set to PCA9532_TYPE_GPIO.
+
config LEDS_GPIO
tristate "LED Support for GPIO connected LEDs"
depends on LEDS_CLASS
diff --git a/drivers/leds/Makefile b/drivers/leds/Makefile
index 39c80fc..bccb96c 100644
--- a/drivers/leds/Makefile
+++ b/drivers/leds/Makefile
@@ -17,11 +17,11 @@
obj-$(CONFIG_LEDS_NET5501) += leds-net5501.o
obj-$(CONFIG_LEDS_WRAP) += leds-wrap.o
obj-$(CONFIG_LEDS_ALIX2) += leds-alix2.o
-obj-$(CONFIG_LEDS_H1940) += leds-h1940.o
obj-$(CONFIG_LEDS_COBALT_QUBE) += leds-cobalt-qube.o
obj-$(CONFIG_LEDS_COBALT_RAQ) += leds-cobalt-raq.o
obj-$(CONFIG_LEDS_SUNFIRE) += leds-sunfire.o
obj-$(CONFIG_LEDS_PCA9532) += leds-pca9532.o
+obj-$(CONFIG_LEDS_GPIO_REGISTER) += leds-gpio-register.o
obj-$(CONFIG_LEDS_GPIO) += leds-gpio.o
obj-$(CONFIG_LEDS_LP3944) += leds-lp3944.o
obj-$(CONFIG_LEDS_LP5521) += leds-lp5521.o
diff --git a/drivers/leds/led-class.c b/drivers/leds/led-class.c
index d5a4ade..dc3d3d8 100644
--- a/drivers/leds/led-class.c
+++ b/drivers/leds/led-class.c
@@ -131,7 +131,8 @@
if (!led_cdev->blink_brightness)
led_cdev->blink_brightness = led_cdev->max_brightness;
- if (delay_on == led_cdev->blink_delay_on &&
+ if (led_get_trigger_data(led_cdev) &&
+ delay_on == led_cdev->blink_delay_on &&
delay_off == led_cdev->blink_delay_off)
return;
diff --git a/drivers/leds/leds-gpio-register.c b/drivers/leds/leds-gpio-register.c
new file mode 100644
index 0000000..1c4ed55
--- /dev/null
+++ b/drivers/leds/leds-gpio-register.c
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) 2011 Pengutronix
+ * Uwe Kleine-Koenig <u.kleine-koenig@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify it under
+ * the terms of the GNU General Public License version 2 as published by the
+ * Free Software Foundation.
+ */
+#include <linux/err.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+#include <linux/leds.h>
+
+/**
+ * gpio_led_register_device - register a gpio-led device
+ * @pdata: the platform data used for the new device
+ *
+ * Makes a copy of pdata and pdata->leds and registers a new leds-gpio device
+ * with the result. This allows to have pdata and pdata-leds in .init.rodata
+ * and so saves some bytes compared to a static struct platform_device with
+ * static platform data.
+ *
+ * Returns the registered device or an error pointer.
+ */
+struct platform_device *__init gpio_led_register_device(
+ int id, const struct gpio_led_platform_data *pdata)
+{
+ struct platform_device *ret;
+ struct gpio_led_platform_data _pdata = *pdata;
+
+ _pdata.leds = kmemdup(pdata->leds,
+ pdata->num_leds * sizeof(*pdata->leds), GFP_KERNEL);
+ if (!_pdata.leds)
+ return ERR_PTR(-ENOMEM);
+
+ ret = platform_device_register_resndata(NULL, "leds-gpio", id,
+ NULL, 0, &_pdata, sizeof(_pdata));
+ if (IS_ERR(ret))
+ kfree(_pdata.leds);
+
+ return ret;
+}
diff --git a/drivers/leds/leds-h1940.c b/drivers/leds/leds-h1940.c
deleted file mode 100644
index 173d104..0000000
--- a/drivers/leds/leds-h1940.c
+++ /dev/null
@@ -1,170 +0,0 @@
-/*
- * drivers/leds/leds-h1940.c
- * Copyright (c) Arnaud Patard <arnaud.patard@rtp-net.org>
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file COPYING in the main directory of this archive for
- * more details.
- *
- * H1940 leds driver
- *
- */
-
-#include <linux/module.h>
-#include <linux/platform_device.h>
-#include <linux/delay.h>
-#include <linux/string.h>
-#include <linux/ctype.h>
-#include <linux/leds.h>
-#include <linux/gpio.h>
-
-#include <mach/regs-gpio.h>
-#include <mach/hardware.h>
-#include <mach/h1940-latch.h>
-
-/*
- * Green led.
- */
-static void h1940_greenled_set(struct led_classdev *led_dev,
- enum led_brightness value)
-{
- switch (value) {
- case LED_HALF:
- h1940_latch_control(0, H1940_LATCH_LED_FLASH);
- s3c2410_gpio_setpin(S3C2410_GPA7, 1);
- break;
- case LED_FULL:
- h1940_latch_control(0, H1940_LATCH_LED_GREEN);
- s3c2410_gpio_setpin(S3C2410_GPA7, 1);
- break;
- default:
- case LED_OFF:
- h1940_latch_control(H1940_LATCH_LED_FLASH, 0);
- h1940_latch_control(H1940_LATCH_LED_GREEN, 0);
- s3c2410_gpio_setpin(S3C2410_GPA7, 0);
- break;
- }
-}
-
-static struct led_classdev h1940_greenled = {
- .name = "h1940:green",
- .brightness_set = h1940_greenled_set,
- .default_trigger = "h1940-charger",
-};
-
-/*
- * Red led.
- */
-static void h1940_redled_set(struct led_classdev *led_dev,
- enum led_brightness value)
-{
- switch (value) {
- case LED_HALF:
- h1940_latch_control(0, H1940_LATCH_LED_FLASH);
- s3c2410_gpio_setpin(S3C2410_GPA1, 1);
- break;
- case LED_FULL:
- h1940_latch_control(0, H1940_LATCH_LED_RED);
- s3c2410_gpio_setpin(S3C2410_GPA1, 1);
- break;
- default:
- case LED_OFF:
- h1940_latch_control(H1940_LATCH_LED_FLASH, 0);
- h1940_latch_control(H1940_LATCH_LED_RED, 0);
- s3c2410_gpio_setpin(S3C2410_GPA1, 0);
- break;
- }
-}
-
-static struct led_classdev h1940_redled = {
- .name = "h1940:red",
- .brightness_set = h1940_redled_set,
- .default_trigger = "h1940-charger",
-};
-
-/*
- * Blue led.
- * (it can only be blue flashing led)
- */
-static void h1940_blueled_set(struct led_classdev *led_dev,
- enum led_brightness value)
-{
- if (value) {
- /* flashing Blue */
- h1940_latch_control(0, H1940_LATCH_LED_FLASH);
- s3c2410_gpio_setpin(S3C2410_GPA3, 1);
- } else {
- h1940_latch_control(H1940_LATCH_LED_FLASH, 0);
- s3c2410_gpio_setpin(S3C2410_GPA3, 0);
- }
-
-}
-
-static struct led_classdev h1940_blueled = {
- .name = "h1940:blue",
- .brightness_set = h1940_blueled_set,
- .default_trigger = "h1940-bluetooth",
-};
-
-static int __devinit h1940leds_probe(struct platform_device *pdev)
-{
- int ret;
-
- ret = led_classdev_register(&pdev->dev, &h1940_greenled);
- if (ret)
- goto err_green;
-
- ret = led_classdev_register(&pdev->dev, &h1940_redled);
- if (ret)
- goto err_red;
-
- ret = led_classdev_register(&pdev->dev, &h1940_blueled);
- if (ret)
- goto err_blue;
-
- return 0;
-
-err_blue:
- led_classdev_unregister(&h1940_redled);
-err_red:
- led_classdev_unregister(&h1940_greenled);
-err_green:
- return ret;
-}
-
-static int h1940leds_remove(struct platform_device *pdev)
-{
- led_classdev_unregister(&h1940_greenled);
- led_classdev_unregister(&h1940_redled);
- led_classdev_unregister(&h1940_blueled);
- return 0;
-}
-
-
-static struct platform_driver h1940leds_driver = {
- .driver = {
- .name = "h1940-leds",
- .owner = THIS_MODULE,
- },
- .probe = h1940leds_probe,
- .remove = h1940leds_remove,
-};
-
-
-static int __init h1940leds_init(void)
-{
- return platform_driver_register(&h1940leds_driver);
-}
-
-static void __exit h1940leds_exit(void)
-{
- platform_driver_unregister(&h1940leds_driver);
-}
-
-module_init(h1940leds_init);
-module_exit(h1940leds_exit);
-
-MODULE_AUTHOR("Arnaud Patard <arnaud.patard@rtp-net.org>");
-MODULE_DESCRIPTION("LED driver for the iPAQ H1940");
-MODULE_LICENSE("GPL");
-MODULE_ALIAS("platform:h1940-leds");
diff --git a/drivers/leds/leds-lm3530.c b/drivers/leds/leds-lm3530.c
index b37e618..4d7ce76 100644
--- a/drivers/leds/leds-lm3530.c
+++ b/drivers/leds/leds-lm3530.c
@@ -17,6 +17,7 @@
#include <linux/input.h>
#include <linux/led-lm3530.h>
#include <linux/types.h>
+#include <linux/regulator/consumer.h>
#define LM3530_LED_DEV "lcd-backlight"
#define LM3530_NAME "lm3530-led"
@@ -96,12 +97,18 @@
* @client: i2c client
* @pdata: LM3530 platform data
* @mode: mode of operation - manual, ALS, PWM
+ * @regulator: regulator
+ * @brighness: previous brightness value
+ * @enable: regulator is enabled
*/
struct lm3530_data {
struct led_classdev led_dev;
struct i2c_client *client;
struct lm3530_platform_data *pdata;
enum lm3530_mode mode;
+ struct regulator *regulator;
+ enum led_brightness brightness;
+ bool enable;
};
static const u8 lm3530_reg[LM3530_REG_MAX] = {
@@ -172,7 +179,10 @@
brt_ramp = (pltfm->brt_ramp_fall << LM3530_BRT_RAMP_FALL_SHIFT) |
(pltfm->brt_ramp_rise << LM3530_BRT_RAMP_RISE_SHIFT);
- brightness = pltfm->brt_val;
+ if (drvdata->brightness)
+ brightness = drvdata->brightness;
+ else
+ brightness = drvdata->brightness = pltfm->brt_val;
reg_val[0] = gen_config; /* LM3530_GEN_CONFIG */
reg_val[1] = als_config; /* LM3530_ALS_CONFIG */
@@ -190,6 +200,16 @@
reg_val[13] = LM3530_DEF_ZT_3; /* LM3530_ALS_Z3T_REG */
reg_val[14] = LM3530_DEF_ZT_4; /* LM3530_ALS_Z4T_REG */
+ if (!drvdata->enable) {
+ ret = regulator_enable(drvdata->regulator);
+ if (ret) {
+ dev_err(&drvdata->client->dev,
+ "Enable regulator failed\n");
+ return ret;
+ }
+ drvdata->enable = true;
+ }
+
for (i = 0; i < LM3530_REG_MAX; i++) {
ret = i2c_smbus_write_byte_data(client,
lm3530_reg[i], reg_val[i]);
@@ -210,12 +230,31 @@
switch (drvdata->mode) {
case LM3530_BL_MODE_MANUAL:
+ if (!drvdata->enable) {
+ err = lm3530_init_registers(drvdata);
+ if (err) {
+ dev_err(&drvdata->client->dev,
+ "Register Init failed: %d\n", err);
+ break;
+ }
+ }
+
/* set the brightness in brightness control register*/
err = i2c_smbus_write_byte_data(drvdata->client,
LM3530_BRT_CTRL_REG, brt_val / 2);
if (err)
dev_err(&drvdata->client->dev,
"Unable to set brightness: %d\n", err);
+ else
+ drvdata->brightness = brt_val / 2;
+
+ if (brt_val == 0) {
+ err = regulator_disable(drvdata->regulator);
+ if (err)
+ dev_err(&drvdata->client->dev,
+ "Disable regulator failed\n");
+ drvdata->enable = false;
+ }
break;
case LM3530_BL_MODE_ALS:
break;
@@ -297,20 +336,31 @@
drvdata->mode = pdata->mode;
drvdata->client = client;
drvdata->pdata = pdata;
+ drvdata->brightness = LED_OFF;
+ drvdata->enable = false;
drvdata->led_dev.name = LM3530_LED_DEV;
drvdata->led_dev.brightness_set = lm3530_brightness_set;
i2c_set_clientdata(client, drvdata);
- err = lm3530_init_registers(drvdata);
- if (err < 0) {
- dev_err(&client->dev, "Register Init failed: %d\n", err);
- err = -ENODEV;
- goto err_reg_init;
+ drvdata->regulator = regulator_get(&client->dev, "vin");
+ if (IS_ERR(drvdata->regulator)) {
+ dev_err(&client->dev, "regulator get failed\n");
+ err = PTR_ERR(drvdata->regulator);
+ drvdata->regulator = NULL;
+ goto err_regulator_get;
}
- err = led_classdev_register((struct device *)
- &client->dev, &drvdata->led_dev);
+ if (drvdata->pdata->brt_val) {
+ err = lm3530_init_registers(drvdata);
+ if (err < 0) {
+ dev_err(&client->dev,
+ "Register Init failed: %d\n", err);
+ err = -ENODEV;
+ goto err_reg_init;
+ }
+ }
+ err = led_classdev_register(&client->dev, &drvdata->led_dev);
if (err < 0) {
dev_err(&client->dev, "Register led class failed: %d\n", err);
err = -ENODEV;
@@ -330,6 +380,9 @@
led_classdev_unregister(&drvdata->led_dev);
err_class_register:
err_reg_init:
+ regulator_put(drvdata->regulator);
+err_regulator_get:
+ i2c_set_clientdata(client, NULL);
kfree(drvdata);
err_out:
return err;
@@ -340,6 +393,10 @@
struct lm3530_data *drvdata = i2c_get_clientdata(client);
device_remove_file(drvdata->led_dev.dev, &dev_attr_mode);
+
+ if (drvdata->enable)
+ regulator_disable(drvdata->regulator);
+ regulator_put(drvdata->regulator);
led_classdev_unregister(&drvdata->led_dev);
kfree(drvdata);
return 0;
diff --git a/drivers/leds/leds-pca9532.c b/drivers/leds/leds-pca9532.c
index 5bf63af..d8d3a1e 100644
--- a/drivers/leds/leds-pca9532.c
+++ b/drivers/leds/leds-pca9532.c
@@ -1,13 +1,14 @@
/*
* pca9532.c - 16-bit Led dimmer
*
+ * Copyright (C) 2011 Jan Weitzel
* Copyright (C) 2008 Riku Voipio
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
- * Datasheet: http://www.nxp.com/acrobat/datasheets/PCA9532_3.pdf
+ * Datasheet: http://www.nxp.com/documents/data_sheet/PCA9532.pdf
*
*/
@@ -19,21 +20,32 @@
#include <linux/mutex.h>
#include <linux/workqueue.h>
#include <linux/leds-pca9532.h>
+#include <linux/gpio.h>
-#define PCA9532_REG_PSC(i) (0x2+(i)*2)
-#define PCA9532_REG_PWM(i) (0x3+(i)*2)
-#define PCA9532_REG_LS0 0x6
-#define LED_REG(led) ((led>>2)+PCA9532_REG_LS0)
-#define LED_NUM(led) (led & 0x3)
+/* m = num_leds*/
+#define PCA9532_REG_INPUT(i) ((i) >> 3)
+#define PCA9532_REG_OFFSET(m) ((m) >> 4)
+#define PCA9532_REG_PSC(m, i) (PCA9532_REG_OFFSET(m) + 0x1 + (i) * 2)
+#define PCA9532_REG_PWM(m, i) (PCA9532_REG_OFFSET(m) + 0x2 + (i) * 2)
+#define LED_REG(m, led) (PCA9532_REG_OFFSET(m) + 0x5 + (led >> 2))
+#define LED_NUM(led) (led & 0x3)
#define ldev_to_led(c) container_of(c, struct pca9532_led, ldev)
+struct pca9532_chip_info {
+ u8 num_leds;
+};
+
struct pca9532_data {
struct i2c_client *client;
struct pca9532_led leds[16];
struct mutex update_lock;
struct input_dev *idev;
struct work_struct work;
+#ifdef CONFIG_LEDS_PCA9532_GPIO
+ struct gpio_chip gpio;
+#endif
+ const struct pca9532_chip_info *chip_info;
u8 pwm[2];
u8 psc[2];
};
@@ -42,16 +54,41 @@
const struct i2c_device_id *id);
static int pca9532_remove(struct i2c_client *client);
+enum {
+ pca9530,
+ pca9531,
+ pca9532,
+ pca9533,
+};
+
static const struct i2c_device_id pca9532_id[] = {
- { "pca9532", 0 },
+ { "pca9530", pca9530 },
+ { "pca9531", pca9531 },
+ { "pca9532", pca9532 },
+ { "pca9533", pca9533 },
{ }
};
MODULE_DEVICE_TABLE(i2c, pca9532_id);
+static const struct pca9532_chip_info pca9532_chip_info_tbl[] = {
+ [pca9530] = {
+ .num_leds = 2,
+ },
+ [pca9531] = {
+ .num_leds = 8,
+ },
+ [pca9532] = {
+ .num_leds = 16,
+ },
+ [pca9533] = {
+ .num_leds = 4,
+ },
+};
+
static struct i2c_driver pca9532_driver = {
.driver = {
- .name = "pca9532",
+ .name = "pca953x",
},
.probe = pca9532_probe,
.remove = pca9532_remove,
@@ -68,7 +105,7 @@
{
int a = 0, b = 0, i = 0;
struct pca9532_data *data = i2c_get_clientdata(client);
- for (i = 0; i < 16; i++) {
+ for (i = 0; i < data->chip_info->num_leds; i++) {
if (data->leds[i].type == PCA9532_TYPE_LED &&
data->leds[i].state == PCA9532_PWM0+pwm) {
a++;
@@ -92,10 +129,12 @@
static int pca9532_setpwm(struct i2c_client *client, int pwm)
{
struct pca9532_data *data = i2c_get_clientdata(client);
+ u8 maxleds = data->chip_info->num_leds;
+
mutex_lock(&data->update_lock);
- i2c_smbus_write_byte_data(client, PCA9532_REG_PWM(pwm),
+ i2c_smbus_write_byte_data(client, PCA9532_REG_PWM(maxleds, pwm),
data->pwm[pwm]);
- i2c_smbus_write_byte_data(client, PCA9532_REG_PSC(pwm),
+ i2c_smbus_write_byte_data(client, PCA9532_REG_PSC(maxleds, pwm),
data->psc[pwm]);
mutex_unlock(&data->update_lock);
return 0;
@@ -106,15 +145,16 @@
{
struct i2c_client *client = led->client;
struct pca9532_data *data = i2c_get_clientdata(client);
+ u8 maxleds = data->chip_info->num_leds;
char reg;
mutex_lock(&data->update_lock);
- reg = i2c_smbus_read_byte_data(client, LED_REG(led->id));
+ reg = i2c_smbus_read_byte_data(client, LED_REG(maxleds, led->id));
/* zero led bits */
reg = reg & ~(0x3<<LED_NUM(led->id)*2);
/* set the new value */
reg = reg | (led->state << LED_NUM(led->id)*2);
- i2c_smbus_write_byte_data(client, LED_REG(led->id), reg);
+ i2c_smbus_write_byte_data(client, LED_REG(maxleds, led->id), reg);
mutex_unlock(&data->update_lock);
}
@@ -183,10 +223,12 @@
static void pca9532_input_work(struct work_struct *work)
{
- struct pca9532_data *data;
- data = container_of(work, struct pca9532_data, work);
+ struct pca9532_data *data =
+ container_of(work, struct pca9532_data, work);
+ u8 maxleds = data->chip_info->num_leds;
+
mutex_lock(&data->update_lock);
- i2c_smbus_write_byte_data(data->client, PCA9532_REG_PWM(1),
+ i2c_smbus_write_byte_data(data->client, PCA9532_REG_PWM(maxleds, 1),
data->pwm[1]);
mutex_unlock(&data->update_lock);
}
@@ -200,16 +242,68 @@
pca9532_setled(led);
}
-static void pca9532_destroy_devices(struct pca9532_data *data, int n_devs)
+#ifdef CONFIG_LEDS_PCA9532_GPIO
+static int pca9532_gpio_request_pin(struct gpio_chip *gc, unsigned offset)
+{
+ struct pca9532_data *data = container_of(gc, struct pca9532_data, gpio);
+ struct pca9532_led *led = &data->leds[offset];
+
+ if (led->type == PCA9532_TYPE_GPIO)
+ return 0;
+
+ return -EBUSY;
+}
+
+static void pca9532_gpio_set_value(struct gpio_chip *gc, unsigned offset, int val)
+{
+ struct pca9532_data *data = container_of(gc, struct pca9532_data, gpio);
+ struct pca9532_led *led = &data->leds[offset];
+
+ if (val)
+ led->state = PCA9532_ON;
+ else
+ led->state = PCA9532_OFF;
+
+ pca9532_setled(led);
+}
+
+static int pca9532_gpio_get_value(struct gpio_chip *gc, unsigned offset)
+{
+ struct pca9532_data *data = container_of(gc, struct pca9532_data, gpio);
+ unsigned char reg;
+
+ reg = i2c_smbus_read_byte_data(data->client, PCA9532_REG_INPUT(offset));
+
+ return !!(reg & (1 << (offset % 8)));
+}
+
+static int pca9532_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
+{
+ /* To use as input ensure pin is not driven */
+ pca9532_gpio_set_value(gc, offset, 0);
+
+ return 0;
+}
+
+static int pca9532_gpio_direction_output(struct gpio_chip *gc, unsigned offset, int val)
+{
+ pca9532_gpio_set_value(gc, offset, val);
+
+ return 0;
+}
+#endif /* CONFIG_LEDS_PCA9532_GPIO */
+
+static int pca9532_destroy_devices(struct pca9532_data *data, int n_devs)
{
int i = n_devs;
if (!data)
- return;
+ return -EINVAL;
while (--i >= 0) {
switch (data->leds[i].type) {
case PCA9532_TYPE_NONE:
+ case PCA9532_TYPE_GPIO:
break;
case PCA9532_TYPE_LED:
led_classdev_unregister(&data->leds[i].ldev);
@@ -224,23 +318,38 @@
break;
}
}
+
+#ifdef CONFIG_LEDS_PCA9532_GPIO
+ if (data->gpio.dev) {
+ int err = gpiochip_remove(&data->gpio);
+ if (err) {
+ dev_err(&data->client->dev, "%s failed, %d\n",
+ "gpiochip_remove()", err);
+ return err;
+ }
+ }
+#endif
+
+ return 0;
}
static int pca9532_configure(struct i2c_client *client,
struct pca9532_data *data, struct pca9532_platform_data *pdata)
{
int i, err = 0;
+ int gpios = 0;
+ u8 maxleds = data->chip_info->num_leds;
for (i = 0; i < 2; i++) {
data->pwm[i] = pdata->pwm[i];
data->psc[i] = pdata->psc[i];
- i2c_smbus_write_byte_data(client, PCA9532_REG_PWM(i),
+ i2c_smbus_write_byte_data(client, PCA9532_REG_PWM(maxleds, i),
data->pwm[i]);
- i2c_smbus_write_byte_data(client, PCA9532_REG_PSC(i),
+ i2c_smbus_write_byte_data(client, PCA9532_REG_PSC(maxleds, i),
data->psc[i]);
}
- for (i = 0; i < 16; i++) {
+ for (i = 0; i < data->chip_info->num_leds; i++) {
struct pca9532_led *led = &data->leds[i];
struct pca9532_led *pled = &pdata->leds[i];
led->client = client;
@@ -249,6 +358,9 @@
switch (led->type) {
case PCA9532_TYPE_NONE:
break;
+ case PCA9532_TYPE_GPIO:
+ gpios++;
+ break;
case PCA9532_TYPE_LED:
led->state = pled->state;
led->name = pled->name;
@@ -297,6 +409,34 @@
break;
}
}
+
+#ifdef CONFIG_LEDS_PCA9532_GPIO
+ if (gpios) {
+ data->gpio.label = "gpio-pca9532";
+ data->gpio.direction_input = pca9532_gpio_direction_input;
+ data->gpio.direction_output = pca9532_gpio_direction_output;
+ data->gpio.set = pca9532_gpio_set_value;
+ data->gpio.get = pca9532_gpio_get_value;
+ data->gpio.request = pca9532_gpio_request_pin;
+ data->gpio.can_sleep = 1;
+ data->gpio.base = pdata->gpio_base;
+ data->gpio.ngpio = data->chip_info->num_leds;
+ data->gpio.dev = &client->dev;
+ data->gpio.owner = THIS_MODULE;
+
+ err = gpiochip_add(&data->gpio);
+ if (err) {
+ /* Use data->gpio.dev as a flag for freeing gpiochip */
+ data->gpio.dev = NULL;
+ dev_warn(&client->dev, "could not add gpiochip\n");
+ } else {
+ dev_info(&client->dev, "gpios %i...%i\n",
+ data->gpio.base, data->gpio.base +
+ data->gpio.ngpio - 1);
+ }
+ }
+#endif
+
return 0;
exit:
@@ -322,6 +462,8 @@
if (!data)
return -ENOMEM;
+ data->chip_info = &pca9532_chip_info_tbl[id->driver_data];
+
dev_info(&client->dev, "setting platform data\n");
i2c_set_clientdata(client, data);
data->client = client;
@@ -337,7 +479,12 @@
static int pca9532_remove(struct i2c_client *client)
{
struct pca9532_data *data = i2c_get_clientdata(client);
- pca9532_destroy_devices(data, 16);
+ int err;
+
+ err = pca9532_destroy_devices(data, data->chip_info->num_leds);
+ if (err)
+ return err;
+
kfree(data);
return 0;
}
diff --git a/drivers/leds/leds.h b/drivers/leds/leds.h
index 2dd8ecb..e77c7f8 100644
--- a/drivers/leds/leds.h
+++ b/drivers/leds/leds.h
@@ -40,10 +40,17 @@
void led_trigger_set(struct led_classdev *led_cdev,
struct led_trigger *trigger);
void led_trigger_remove(struct led_classdev *led_cdev);
+
+static inline void *led_get_trigger_data(struct led_classdev *led_cdev)
+{
+ return led_cdev->trigger_data;
+}
+
#else
#define led_trigger_set_default(x) do {} while (0)
#define led_trigger_set(x, y) do {} while (0)
#define led_trigger_remove(x) do {} while (0)
+#define led_get_trigger_data(x) (NULL)
#endif
ssize_t led_trigger_store(struct device *dev, struct device_attribute *attr,
diff --git a/drivers/leds/ledtrig-timer.c b/drivers/leds/ledtrig-timer.c
index b09bcbe..d87c9d0 100644
--- a/drivers/leds/ledtrig-timer.c
+++ b/drivers/leds/ledtrig-timer.c
@@ -91,6 +91,9 @@
if (rc)
goto err_out_delayon;
+ led_blink_set(led_cdev, &led_cdev->blink_delay_on,
+ &led_cdev->blink_delay_off);
+
led_cdev->trigger_data = (void *)1;
return;
diff --git a/drivers/media/common/saa7146_core.c b/drivers/media/common/saa7146_core.c
index 9f47e38..9af2140 100644
--- a/drivers/media/common/saa7146_core.c
+++ b/drivers/media/common/saa7146_core.c
@@ -378,12 +378,7 @@
dev->pci = pci;
/* get chip-revision; this is needed to enable bug-fixes */
- err = pci_read_config_dword(pci, PCI_CLASS_REVISION, &dev->revision);
- if (err < 0) {
- ERR(("pci_read_config_dword() failed.\n"));
- goto err_disable;
- }
- dev->revision &= 0xf;
+ dev->revision = pci->revision;
/* remap the memory from virtual to physical address */
diff --git a/drivers/media/common/tuners/Kconfig b/drivers/media/common/tuners/Kconfig
index 6fc79f1..22d3ca3 100644
--- a/drivers/media/common/tuners/Kconfig
+++ b/drivers/media/common/tuners/Kconfig
@@ -186,4 +186,12 @@
default m if MEDIA_TUNER_CUSTOMISE
help
NXP TDA18218 silicon tuner driver.
+
+config MEDIA_TUNER_TDA18212
+ tristate "NXP TDA18212 silicon tuner"
+ depends on VIDEO_MEDIA && I2C
+ default m if MEDIA_TUNER_CUSTOMISE
+ help
+ NXP TDA18212 silicon tuner driver.
+
endmenu
diff --git a/drivers/media/common/tuners/Makefile b/drivers/media/common/tuners/Makefile
index 96da03d..2cb4f53 100644
--- a/drivers/media/common/tuners/Makefile
+++ b/drivers/media/common/tuners/Makefile
@@ -25,6 +25,7 @@
obj-$(CONFIG_MEDIA_TUNER_MC44S803) += mc44s803.o
obj-$(CONFIG_MEDIA_TUNER_MAX2165) += max2165.o
obj-$(CONFIG_MEDIA_TUNER_TDA18218) += tda18218.o
+obj-$(CONFIG_MEDIA_TUNER_TDA18212) += tda18212.o
EXTRA_CFLAGS += -Idrivers/media/dvb/dvb-core
EXTRA_CFLAGS += -Idrivers/media/dvb/frontends
diff --git a/drivers/media/common/tuners/mxl5005s.c b/drivers/media/common/tuners/mxl5005s.c
index 0d6e094..56fe75c 100644
--- a/drivers/media/common/tuners/mxl5005s.c
+++ b/drivers/media/common/tuners/mxl5005s.c
@@ -4024,6 +4024,8 @@
case BANDWIDTH_8_MHZ:
req_bw = MXL5005S_BANDWIDTH_8MHZ;
break;
+ default:
+ return -EINVAL;
}
}
diff --git a/drivers/media/common/tuners/tda18212.c b/drivers/media/common/tuners/tda18212.c
new file mode 100644
index 0000000..1f1db20
--- /dev/null
+++ b/drivers/media/common/tuners/tda18212.c
@@ -0,0 +1,265 @@
+/*
+ * NXP TDA18212HN silicon tuner driver
+ *
+ * Copyright (C) 2011 Antti Palosaari <crope@iki.fi>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include "tda18212_priv.h"
+
+static int debug;
+module_param(debug, int, 0644);
+MODULE_PARM_DESC(debug, "Turn on/off debugging (default:off).");
+
+/* write multiple registers */
+static int tda18212_wr_regs(struct tda18212_priv *priv, u8 reg, u8 *val,
+ int len)
+{
+ int ret;
+ u8 buf[len+1];
+ struct i2c_msg msg[1] = {
+ {
+ .addr = priv->cfg->i2c_address,
+ .flags = 0,
+ .len = sizeof(buf),
+ .buf = buf,
+ }
+ };
+
+ buf[0] = reg;
+ memcpy(&buf[1], val, len);
+
+ ret = i2c_transfer(priv->i2c, msg, 1);
+ if (ret == 1) {
+ ret = 0;
+ } else {
+ warn("i2c wr failed ret:%d reg:%02x len:%d", ret, reg, len);
+ ret = -EREMOTEIO;
+ }
+ return ret;
+}
+
+/* read multiple registers */
+static int tda18212_rd_regs(struct tda18212_priv *priv, u8 reg, u8 *val,
+ int len)
+{
+ int ret;
+ u8 buf[len];
+ struct i2c_msg msg[2] = {
+ {
+ .addr = priv->cfg->i2c_address,
+ .flags = 0,
+ .len = 1,
+ .buf = ®,
+ }, {
+ .addr = priv->cfg->i2c_address,
+ .flags = I2C_M_RD,
+ .len = sizeof(buf),
+ .buf = buf,
+ }
+ };
+
+ ret = i2c_transfer(priv->i2c, msg, 2);
+ if (ret == 2) {
+ memcpy(val, buf, len);
+ ret = 0;
+ } else {
+ warn("i2c rd failed ret:%d reg:%02x len:%d", ret, reg, len);
+ ret = -EREMOTEIO;
+ }
+
+ return ret;
+}
+
+/* write single register */
+static int tda18212_wr_reg(struct tda18212_priv *priv, u8 reg, u8 val)
+{
+ return tda18212_wr_regs(priv, reg, &val, 1);
+}
+
+/* read single register */
+static int tda18212_rd_reg(struct tda18212_priv *priv, u8 reg, u8 *val)
+{
+ return tda18212_rd_regs(priv, reg, val, 1);
+}
+
+#if 0 /* keep, useful when developing driver */
+static void tda18212_dump_regs(struct tda18212_priv *priv)
+{
+ int i;
+ u8 buf[256];
+
+ #define TDA18212_RD_LEN 32
+ for (i = 0; i < sizeof(buf); i += TDA18212_RD_LEN)
+ tda18212_rd_regs(priv, i, &buf[i], TDA18212_RD_LEN);
+
+ print_hex_dump(KERN_INFO, "", DUMP_PREFIX_OFFSET, 32, 1, buf,
+ sizeof(buf), true);
+
+ return;
+}
+#endif
+
+static int tda18212_set_params(struct dvb_frontend *fe,
+ struct dvb_frontend_parameters *p)
+{
+ struct tda18212_priv *priv = fe->tuner_priv;
+ struct dtv_frontend_properties *c = &fe->dtv_property_cache;
+ int ret, i;
+ u32 if_khz;
+ u8 buf[9];
+ static const u8 bw_params[][3] = {
+ /* 0f 13 23 */
+ { 0xb3, 0x20, 0x03 }, /* DVB-T 6 MHz */
+ { 0xb3, 0x31, 0x01 }, /* DVB-T 7 MHz */
+ { 0xb3, 0x22, 0x01 }, /* DVB-T 8 MHz */
+ { 0x92, 0x53, 0x03 }, /* DVB-C */
+ };
+
+ dbg("%s: delsys=%d RF=%d BW=%d", __func__,
+ c->delivery_system, c->frequency, c->bandwidth_hz);
+
+ if (fe->ops.i2c_gate_ctrl)
+ fe->ops.i2c_gate_ctrl(fe, 1); /* open I2C-gate */
+
+ switch (c->delivery_system) {
+ case SYS_DVBT:
+ switch (c->bandwidth_hz) {
+ case 6000000:
+ if_khz = priv->cfg->if_dvbt_6;
+ i = 0;
+ break;
+ case 7000000:
+ if_khz = priv->cfg->if_dvbt_7;
+ i = 1;
+ break;
+ case 8000000:
+ if_khz = priv->cfg->if_dvbt_8;
+ i = 2;
+ break;
+ default:
+ ret = -EINVAL;
+ goto error;
+ }
+ break;
+ case SYS_DVBC_ANNEX_AC:
+ if_khz = priv->cfg->if_dvbc;
+ i = 3;
+ break;
+ default:
+ ret = -EINVAL;
+ goto error;
+ }
+
+ ret = tda18212_wr_reg(priv, 0x23, bw_params[i][2]);
+ if (ret)
+ goto error;
+
+ ret = tda18212_wr_reg(priv, 0x06, 0x00);
+ if (ret)
+ goto error;
+
+ ret = tda18212_wr_reg(priv, 0x0f, bw_params[i][0]);
+ if (ret)
+ goto error;
+
+ buf[0] = 0x02;
+ buf[1] = bw_params[i][1];
+ buf[2] = 0x03; /* default value */
+ buf[3] = if_khz / 50;
+ buf[4] = ((c->frequency / 1000) >> 16) & 0xff;
+ buf[5] = ((c->frequency / 1000) >> 8) & 0xff;
+ buf[6] = ((c->frequency / 1000) >> 0) & 0xff;
+ buf[7] = 0xc1;
+ buf[8] = 0x01;
+ ret = tda18212_wr_regs(priv, 0x12, buf, sizeof(buf));
+ if (ret)
+ goto error;
+
+exit:
+ if (fe->ops.i2c_gate_ctrl)
+ fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */
+
+ return ret;
+
+error:
+ dbg("%s: failed:%d", __func__, ret);
+ goto exit;
+}
+
+static int tda18212_release(struct dvb_frontend *fe)
+{
+ kfree(fe->tuner_priv);
+ fe->tuner_priv = NULL;
+ return 0;
+}
+
+static const struct dvb_tuner_ops tda18212_tuner_ops = {
+ .info = {
+ .name = "NXP TDA18212",
+
+ .frequency_min = 48000000,
+ .frequency_max = 864000000,
+ .frequency_step = 1000,
+ },
+
+ .release = tda18212_release,
+
+ .set_params = tda18212_set_params,
+};
+
+struct dvb_frontend *tda18212_attach(struct dvb_frontend *fe,
+ struct i2c_adapter *i2c, struct tda18212_config *cfg)
+{
+ struct tda18212_priv *priv = NULL;
+ int ret;
+ u8 val;
+
+ priv = kzalloc(sizeof(struct tda18212_priv), GFP_KERNEL);
+ if (priv == NULL)
+ return NULL;
+
+ priv->cfg = cfg;
+ priv->i2c = i2c;
+ fe->tuner_priv = priv;
+
+ if (fe->ops.i2c_gate_ctrl)
+ fe->ops.i2c_gate_ctrl(fe, 1); /* open I2C-gate */
+
+ /* check if the tuner is there */
+ ret = tda18212_rd_reg(priv, 0x00, &val);
+
+ if (fe->ops.i2c_gate_ctrl)
+ fe->ops.i2c_gate_ctrl(fe, 0); /* close I2C-gate */
+
+ dbg("%s: ret:%d chip ID:%02x", __func__, ret, val);
+ if (ret || val != 0xc7) {
+ kfree(priv);
+ return NULL;
+ }
+
+ info("NXP TDA18212HN successfully identified.");
+
+ memcpy(&fe->ops.tuner_ops, &tda18212_tuner_ops,
+ sizeof(struct dvb_tuner_ops));
+
+ return fe;
+}
+EXPORT_SYMBOL(tda18212_attach);
+
+MODULE_DESCRIPTION("NXP TDA18212HN silicon tuner driver");
+MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/common/tuners/tda18212.h b/drivers/media/common/tuners/tda18212.h
new file mode 100644
index 0000000..83b497f
--- /dev/null
+++ b/drivers/media/common/tuners/tda18212.h
@@ -0,0 +1,48 @@
+/*
+ * NXP TDA18212HN silicon tuner driver
+ *
+ * Copyright (C) 2011 Antti Palosaari <crope@iki.fi>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef TDA18212_H
+#define TDA18212_H
+
+#include "dvb_frontend.h"
+
+struct tda18212_config {
+ u8 i2c_address;
+
+ u16 if_dvbt_6;
+ u16 if_dvbt_7;
+ u16 if_dvbt_8;
+ u16 if_dvbc;
+};
+
+#if defined(CONFIG_MEDIA_TUNER_TDA18212) || \
+ (defined(CONFIG_MEDIA_TUNER_TDA18212_MODULE) && defined(MODULE))
+extern struct dvb_frontend *tda18212_attach(struct dvb_frontend *fe,
+ struct i2c_adapter *i2c, struct tda18212_config *cfg);
+#else
+static inline struct dvb_frontend *tda18212_attach(struct dvb_frontend *fe,
+ struct i2c_adapter *i2c, struct tda18212_config *cfg)
+{
+ printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+ return NULL;
+}
+#endif
+
+#endif
diff --git a/drivers/media/common/tuners/tda18212_priv.h b/drivers/media/common/tuners/tda18212_priv.h
new file mode 100644
index 0000000..9adff93
--- /dev/null
+++ b/drivers/media/common/tuners/tda18212_priv.h
@@ -0,0 +1,44 @@
+/*
+ * NXP TDA18212HN silicon tuner driver
+ *
+ * Copyright (C) 2011 Antti Palosaari <crope@iki.fi>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#ifndef TDA18212_PRIV_H
+#define TDA18212_PRIV_H
+
+#include "tda18212.h"
+
+#define LOG_PREFIX "tda18212"
+
+#undef dbg
+#define dbg(f, arg...) \
+ if (debug) \
+ printk(KERN_INFO LOG_PREFIX": " f "\n" , ## arg)
+#undef err
+#define err(f, arg...) printk(KERN_ERR LOG_PREFIX": " f "\n" , ## arg)
+#undef info
+#define info(f, arg...) printk(KERN_INFO LOG_PREFIX": " f "\n" , ## arg)
+#undef warn
+#define warn(f, arg...) printk(KERN_WARNING LOG_PREFIX": " f "\n" , ## arg)
+
+struct tda18212_priv {
+ struct tda18212_config *cfg;
+ struct i2c_adapter *i2c;
+};
+
+#endif
diff --git a/drivers/media/common/tuners/tda18271-fe.c b/drivers/media/common/tuners/tda18271-fe.c
index d884f5e..57022e8 100644
--- a/drivers/media/common/tuners/tda18271-fe.c
+++ b/drivers/media/common/tuners/tda18271-fe.c
@@ -976,6 +976,10 @@
tda_warn("bandwidth not set!\n");
return -EINVAL;
}
+ } else if (fe->ops.info.type == FE_QAM) {
+ /* DVB-C */
+ map = &std_map->qam_8;
+ bw = 8000000;
} else {
tda_warn("modulation type not supported!\n");
return -EINVAL;
diff --git a/drivers/media/common/tuners/xc5000.c b/drivers/media/common/tuners/xc5000.c
index 1e28f7d..aa1b2e8 100644
--- a/drivers/media/common/tuners/xc5000.c
+++ b/drivers/media/common/tuners/xc5000.c
@@ -628,6 +628,15 @@
dprintk(1, "*** Quality (0:<8dB, 7:>56dB) = %d\n", quality);
}
+/*
+ * As defined on EN 300 429, the DVB-C roll-off factor is 0.15.
+ * So, the amount of the needed bandwith is given by:
+ * Bw = Symbol_rate * (1 + 0.15)
+ * As such, the maximum symbol rate supported by 6 MHz is given by:
+ * max_symbol_rate = 6 MHz / 1.15 = 5217391 Bauds
+ */
+#define MAX_SYMBOL_RATE_6MHz 5217391
+
static int xc5000_set_params(struct dvb_frontend *fe,
struct dvb_frontend_parameters *params)
{
@@ -688,21 +697,32 @@
}
priv->rf_mode = XC_RF_MODE_AIR;
} else if (fe->ops.info.type == FE_QAM) {
- dprintk(1, "%s() QAM\n", __func__);
switch (params->u.qam.modulation) {
+ case QAM_256:
+ case QAM_AUTO:
case QAM_16:
case QAM_32:
case QAM_64:
case QAM_128:
- case QAM_256:
- case QAM_AUTO:
dprintk(1, "%s() QAM modulation\n", __func__);
- priv->bandwidth = BANDWIDTH_8_MHZ;
- priv->video_standard = DTV7_8;
- priv->freq_hz = params->frequency - 2750000;
priv->rf_mode = XC_RF_MODE_CABLE;
+ /*
+ * Using a 8MHz bandwidth sometimes fail
+ * with 6MHz-spaced channels, due to inter-carrier
+ * interference. So, use DTV6 firmware
+ */
+ if (params->u.qam.symbol_rate <= MAX_SYMBOL_RATE_6MHz) {
+ priv->bandwidth = BANDWIDTH_6_MHZ;
+ priv->video_standard = DTV6;
+ priv->freq_hz = params->frequency - 1750000;
+ } else {
+ priv->bandwidth = BANDWIDTH_8_MHZ;
+ priv->video_standard = DTV7_8;
+ priv->freq_hz = params->frequency - 2750000;
+ }
break;
default:
+ dprintk(1, "%s() Unsupported QAM type\n", __func__);
return -EINVAL;
}
} else {
diff --git a/drivers/media/dvb/b2c2/flexcop-pci.c b/drivers/media/dvb/b2c2/flexcop-pci.c
index 03f96d6..44f8fb5 100644
--- a/drivers/media/dvb/b2c2/flexcop-pci.c
+++ b/drivers/media/dvb/b2c2/flexcop-pci.c
@@ -290,10 +290,8 @@
static int flexcop_pci_init(struct flexcop_pci *fc_pci)
{
int ret;
- u8 card_rev;
- pci_read_config_byte(fc_pci->pdev, PCI_CLASS_REVISION, &card_rev);
- info("card revision %x", card_rev);
+ info("card revision %x", fc_pci->pdev->revision);
if ((ret = pci_enable_device(fc_pci->pdev)) != 0)
return ret;
diff --git a/drivers/media/dvb/bt8xx/bt878.c b/drivers/media/dvb/bt8xx/bt878.c
index 99d6209..b34fa95 100644
--- a/drivers/media/dvb/bt8xx/bt878.c
+++ b/drivers/media/dvb/bt8xx/bt878.c
@@ -460,7 +460,7 @@
goto fail0;
}
- pci_read_config_byte(dev, PCI_CLASS_REVISION, &bt->revision);
+ bt->revision = dev->revision;
pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
diff --git a/drivers/media/dvb/dvb-core/dvb_demux.c b/drivers/media/dvb/dvb-core/dvb_demux.c
index 4a88a3e..faa3671 100644
--- a/drivers/media/dvb/dvb-core/dvb_demux.c
+++ b/drivers/media/dvb/dvb-core/dvb_demux.c
@@ -478,97 +478,94 @@
EXPORT_SYMBOL(dvb_dmx_swfilter_packets);
-void dvb_dmx_swfilter(struct dvb_demux *demux, const u8 *buf, size_t count)
+static inline int find_next_packet(const u8 *buf, int pos, size_t count,
+ const int pktsize)
+{
+ int start = pos, lost;
+
+ while (pos < count) {
+ if (buf[pos] == 0x47 ||
+ (pktsize == 204 && buf[pos] == 0xB8))
+ break;
+ pos++;
+ }
+
+ lost = pos - start;
+ if (lost) {
+ /* This garbage is part of a valid packet? */
+ int backtrack = pos - pktsize;
+ if (backtrack >= 0 && (buf[backtrack] == 0x47 ||
+ (pktsize == 204 && buf[backtrack] == 0xB8)))
+ return backtrack;
+ }
+
+ return pos;
+}
+
+/* Filter all pktsize= 188 or 204 sized packets and skip garbage. */
+static inline void _dvb_dmx_swfilter(struct dvb_demux *demux, const u8 *buf,
+ size_t count, const int pktsize)
{
int p = 0, i, j;
+ const u8 *q;
spin_lock(&demux->lock);
- if (demux->tsbufp) {
+ if (demux->tsbufp) { /* tsbuf[0] is now 0x47. */
i = demux->tsbufp;
- j = 188 - i;
+ j = pktsize - i;
if (count < j) {
memcpy(&demux->tsbuf[i], buf, count);
demux->tsbufp += count;
goto bailout;
}
memcpy(&demux->tsbuf[i], buf, j);
- if (demux->tsbuf[0] == 0x47)
+ if (demux->tsbuf[0] == 0x47) /* double check */
dvb_dmx_swfilter_packet(demux, demux->tsbuf);
demux->tsbufp = 0;
p += j;
}
- while (p < count) {
- if (buf[p] == 0x47) {
- if (count - p >= 188) {
- dvb_dmx_swfilter_packet(demux, &buf[p]);
- p += 188;
- } else {
- i = count - p;
- memcpy(demux->tsbuf, &buf[p], i);
- demux->tsbufp = i;
- goto bailout;
- }
- } else
- p++;
+ while (1) {
+ p = find_next_packet(buf, p, count, pktsize);
+ if (p >= count)
+ break;
+ if (count - p < pktsize)
+ break;
+
+ q = &buf[p];
+
+ if (pktsize == 204 && (*q == 0xB8)) {
+ memcpy(demux->tsbuf, q, 188);
+ demux->tsbuf[0] = 0x47;
+ q = demux->tsbuf;
+ }
+ dvb_dmx_swfilter_packet(demux, q);
+ p += pktsize;
+ }
+
+ i = count - p;
+ if (i) {
+ memcpy(demux->tsbuf, &buf[p], i);
+ demux->tsbufp = i;
+ if (pktsize == 204 && demux->tsbuf[0] == 0xB8)
+ demux->tsbuf[0] = 0x47;
}
bailout:
spin_unlock(&demux->lock);
}
+void dvb_dmx_swfilter(struct dvb_demux *demux, const u8 *buf, size_t count)
+{
+ _dvb_dmx_swfilter(demux, buf, count, 188);
+}
EXPORT_SYMBOL(dvb_dmx_swfilter);
void dvb_dmx_swfilter_204(struct dvb_demux *demux, const u8 *buf, size_t count)
{
- int p = 0, i, j;
- u8 tmppack[188];
-
- spin_lock(&demux->lock);
-
- if (demux->tsbufp) {
- i = demux->tsbufp;
- j = 204 - i;
- if (count < j) {
- memcpy(&demux->tsbuf[i], buf, count);
- demux->tsbufp += count;
- goto bailout;
- }
- memcpy(&demux->tsbuf[i], buf, j);
- if ((demux->tsbuf[0] == 0x47) || (demux->tsbuf[0] == 0xB8)) {
- memcpy(tmppack, demux->tsbuf, 188);
- if (tmppack[0] == 0xB8)
- tmppack[0] = 0x47;
- dvb_dmx_swfilter_packet(demux, tmppack);
- }
- demux->tsbufp = 0;
- p += j;
- }
-
- while (p < count) {
- if ((buf[p] == 0x47) || (buf[p] == 0xB8)) {
- if (count - p >= 204) {
- memcpy(tmppack, &buf[p], 188);
- if (tmppack[0] == 0xB8)
- tmppack[0] = 0x47;
- dvb_dmx_swfilter_packet(demux, tmppack);
- p += 204;
- } else {
- i = count - p;
- memcpy(demux->tsbuf, &buf[p], i);
- demux->tsbufp = i;
- goto bailout;
- }
- } else {
- p++;
- }
- }
-
-bailout:
- spin_unlock(&demux->lock);
+ _dvb_dmx_swfilter(demux, buf, count, 204);
}
-
EXPORT_SYMBOL(dvb_dmx_swfilter_204);
static struct dvb_demux_filter *dvb_dmx_filter_alloc(struct dvb_demux *demux)
diff --git a/drivers/media/dvb/dvb-core/dvb_frontend.c b/drivers/media/dvb/dvb-core/dvb_frontend.c
index 31e2c0d..9827804 100644
--- a/drivers/media/dvb/dvb-core/dvb_frontend.c
+++ b/drivers/media/dvb/dvb-core/dvb_frontend.c
@@ -105,7 +105,8 @@
/* thread/frontend values */
struct dvb_device *dvbdev;
- struct dvb_frontend_parameters parameters;
+ struct dvb_frontend_parameters parameters_in;
+ struct dvb_frontend_parameters parameters_out;
struct dvb_fe_events events;
struct semaphore sem;
struct list_head list_head;
@@ -160,12 +161,11 @@
e = &events->events[events->eventw];
- memcpy (&e->parameters, &fepriv->parameters,
- sizeof (struct dvb_frontend_parameters));
-
if (status & FE_HAS_LOCK)
if (fe->ops.get_frontend)
- fe->ops.get_frontend(fe, &e->parameters);
+ fe->ops.get_frontend(fe, &fepriv->parameters_out);
+
+ e->parameters = fepriv->parameters_out;
events->eventw = wp;
@@ -277,12 +277,12 @@
int ready = 0;
int fe_set_err = 0;
struct dvb_frontend_private *fepriv = fe->frontend_priv;
- int original_inversion = fepriv->parameters.inversion;
- u32 original_frequency = fepriv->parameters.frequency;
+ int original_inversion = fepriv->parameters_in.inversion;
+ u32 original_frequency = fepriv->parameters_in.frequency;
/* are we using autoinversion? */
autoinversion = ((!(fe->ops.info.caps & FE_CAN_INVERSION_AUTO)) &&
- (fepriv->parameters.inversion == INVERSION_AUTO));
+ (fepriv->parameters_in.inversion == INVERSION_AUTO));
/* setup parameters correctly */
while(!ready) {
@@ -348,18 +348,19 @@
fepriv->auto_step, fepriv->auto_sub_step, fepriv->started_auto_step);
/* set the frontend itself */
- fepriv->parameters.frequency += fepriv->lnb_drift;
+ fepriv->parameters_in.frequency += fepriv->lnb_drift;
if (autoinversion)
- fepriv->parameters.inversion = fepriv->inversion;
+ fepriv->parameters_in.inversion = fepriv->inversion;
if (fe->ops.set_frontend)
- fe_set_err = fe->ops.set_frontend(fe, &fepriv->parameters);
+ fe_set_err = fe->ops.set_frontend(fe, &fepriv->parameters_in);
+ fepriv->parameters_out = fepriv->parameters_in;
if (fe_set_err < 0) {
fepriv->state = FESTATE_ERROR;
return fe_set_err;
}
- fepriv->parameters.frequency = original_frequency;
- fepriv->parameters.inversion = original_inversion;
+ fepriv->parameters_in.frequency = original_frequency;
+ fepriv->parameters_in.inversion = original_inversion;
fepriv->auto_sub_step++;
return 0;
@@ -383,7 +384,8 @@
if (fepriv->state & FESTATE_RETUNE) {
if (fe->ops.set_frontend)
retval = fe->ops.set_frontend(fe,
- &fepriv->parameters);
+ &fepriv->parameters_in);
+ fepriv->parameters_out = fepriv->parameters_in;
if (retval < 0)
fepriv->state = FESTATE_ERROR;
else
@@ -413,8 +415,8 @@
/* if we're tuned, then we have determined the correct inversion */
if ((!(fe->ops.info.caps & FE_CAN_INVERSION_AUTO)) &&
- (fepriv->parameters.inversion == INVERSION_AUTO)) {
- fepriv->parameters.inversion = fepriv->inversion;
+ (fepriv->parameters_in.inversion == INVERSION_AUTO)) {
+ fepriv->parameters_in.inversion = fepriv->inversion;
}
return;
}
@@ -594,12 +596,14 @@
if (fepriv->state & FESTATE_RETUNE) {
dprintk("%s: Retune requested, FESTATE_RETUNE\n", __func__);
- params = &fepriv->parameters;
+ params = &fepriv->parameters_in;
fepriv->state = FESTATE_TUNED;
}
if (fe->ops.tune)
fe->ops.tune(fe, params, fepriv->tune_mode_flags, &fepriv->delay, &s);
+ if (params)
+ fepriv->parameters_out = *params;
if (s != fepriv->status && !(fepriv->tune_mode_flags & FE_TUNE_MODE_ONESHOT)) {
dprintk("%s: state changed, adding current state\n", __func__);
@@ -612,11 +616,9 @@
dvb_frontend_swzigzag(fe);
break;
case DVBFE_ALGO_CUSTOM:
- params = NULL; /* have we been asked to RETUNE ? */
dprintk("%s: Frontend ALGO = DVBFE_ALGO_CUSTOM, state=%d\n", __func__, fepriv->state);
if (fepriv->state & FESTATE_RETUNE) {
dprintk("%s: Retune requested, FESTAT_RETUNE\n", __func__);
- params = &fepriv->parameters;
fepriv->state = FESTATE_TUNED;
}
/* Case where we are going to search for a carrier
@@ -625,7 +627,7 @@
*/
if (fepriv->algo_status & DVBFE_ALGO_SEARCH_AGAIN) {
if (fe->ops.search) {
- fepriv->algo_status = fe->ops.search(fe, &fepriv->parameters);
+ fepriv->algo_status = fe->ops.search(fe, &fepriv->parameters_in);
/* We did do a search as was requested, the flags are
* now unset as well and has the flags wrt to search.
*/
@@ -636,11 +638,12 @@
/* Track the carrier if the search was successful */
if (fepriv->algo_status == DVBFE_ALGO_SEARCH_SUCCESS) {
if (fe->ops.track)
- fe->ops.track(fe, &fepriv->parameters);
+ fe->ops.track(fe, &fepriv->parameters_in);
} else {
fepriv->algo_status |= DVBFE_ALGO_SEARCH_AGAIN;
fepriv->delay = HZ / 2;
}
+ fepriv->parameters_out = fepriv->parameters_in;
fe->ops.read_status(fe, &s);
if (s != fepriv->status) {
dvb_frontend_add_event(fe, s); /* update event list */
@@ -860,34 +863,34 @@
static int dvb_frontend_clear_cache(struct dvb_frontend *fe)
{
+ struct dtv_frontend_properties *c = &fe->dtv_property_cache;
int i;
- memset(&(fe->dtv_property_cache), 0,
- sizeof(struct dtv_frontend_properties));
+ memset(c, 0, sizeof(struct dtv_frontend_properties));
- fe->dtv_property_cache.state = DTV_CLEAR;
- fe->dtv_property_cache.delivery_system = SYS_UNDEFINED;
- fe->dtv_property_cache.inversion = INVERSION_AUTO;
- fe->dtv_property_cache.fec_inner = FEC_AUTO;
- fe->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_AUTO;
- fe->dtv_property_cache.bandwidth_hz = BANDWIDTH_AUTO;
- fe->dtv_property_cache.guard_interval = GUARD_INTERVAL_AUTO;
- fe->dtv_property_cache.hierarchy = HIERARCHY_AUTO;
- fe->dtv_property_cache.symbol_rate = QAM_AUTO;
- fe->dtv_property_cache.code_rate_HP = FEC_AUTO;
- fe->dtv_property_cache.code_rate_LP = FEC_AUTO;
+ c->state = DTV_CLEAR;
+ c->delivery_system = SYS_UNDEFINED;
+ c->inversion = INVERSION_AUTO;
+ c->fec_inner = FEC_AUTO;
+ c->transmission_mode = TRANSMISSION_MODE_AUTO;
+ c->bandwidth_hz = BANDWIDTH_AUTO;
+ c->guard_interval = GUARD_INTERVAL_AUTO;
+ c->hierarchy = HIERARCHY_AUTO;
+ c->symbol_rate = QAM_AUTO;
+ c->code_rate_HP = FEC_AUTO;
+ c->code_rate_LP = FEC_AUTO;
- fe->dtv_property_cache.isdbt_partial_reception = -1;
- fe->dtv_property_cache.isdbt_sb_mode = -1;
- fe->dtv_property_cache.isdbt_sb_subchannel = -1;
- fe->dtv_property_cache.isdbt_sb_segment_idx = -1;
- fe->dtv_property_cache.isdbt_sb_segment_count = -1;
- fe->dtv_property_cache.isdbt_layer_enabled = 0x7;
+ c->isdbt_partial_reception = -1;
+ c->isdbt_sb_mode = -1;
+ c->isdbt_sb_subchannel = -1;
+ c->isdbt_sb_segment_idx = -1;
+ c->isdbt_sb_segment_count = -1;
+ c->isdbt_layer_enabled = 0x7;
for (i = 0; i < 3; i++) {
- fe->dtv_property_cache.layer[i].fec = FEC_AUTO;
- fe->dtv_property_cache.layer[i].modulation = QAM_AUTO;
- fe->dtv_property_cache.layer[i].interleaving = -1;
- fe->dtv_property_cache.layer[i].segment_count = -1;
+ c->layer[i].fec = FEC_AUTO;
+ c->layer[i].modulation = QAM_AUTO;
+ c->layer[i].interleaving = -1;
+ c->layer[i].segment_count = -1;
}
return 0;
@@ -1020,10 +1023,9 @@
* it's being used for the legacy or new API, reducing code and complexity.
*/
static void dtv_property_cache_sync(struct dvb_frontend *fe,
- struct dvb_frontend_parameters *p)
+ struct dtv_frontend_properties *c,
+ const struct dvb_frontend_parameters *p)
{
- struct dtv_frontend_properties *c = &fe->dtv_property_cache;
-
c->frequency = p->frequency;
c->inversion = p->inversion;
@@ -1074,9 +1076,9 @@
*/
static void dtv_property_legacy_params_sync(struct dvb_frontend *fe)
{
- struct dtv_frontend_properties *c = &fe->dtv_property_cache;
+ const struct dtv_frontend_properties *c = &fe->dtv_property_cache;
struct dvb_frontend_private *fepriv = fe->frontend_priv;
- struct dvb_frontend_parameters *p = &fepriv->parameters;
+ struct dvb_frontend_parameters *p = &fepriv->parameters_in;
p->frequency = c->frequency;
p->inversion = c->inversion;
@@ -1086,14 +1088,12 @@
dprintk("%s() Preparing QPSK req\n", __func__);
p->u.qpsk.symbol_rate = c->symbol_rate;
p->u.qpsk.fec_inner = c->fec_inner;
- c->delivery_system = SYS_DVBS;
break;
case FE_QAM:
dprintk("%s() Preparing QAM req\n", __func__);
p->u.qam.symbol_rate = c->symbol_rate;
p->u.qam.fec_inner = c->fec_inner;
p->u.qam.modulation = c->modulation;
- c->delivery_system = SYS_DVBC_ANNEX_AC;
break;
case FE_OFDM:
dprintk("%s() Preparing OFDM req\n", __func__);
@@ -1111,15 +1111,10 @@
p->u.ofdm.transmission_mode = c->transmission_mode;
p->u.ofdm.guard_interval = c->guard_interval;
p->u.ofdm.hierarchy_information = c->hierarchy;
- c->delivery_system = SYS_DVBT;
break;
case FE_ATSC:
dprintk("%s() Preparing VSB req\n", __func__);
p->u.vsb.modulation = c->modulation;
- if ((c->modulation == VSB_8) || (c->modulation == VSB_16))
- c->delivery_system = SYS_ATSC;
- else
- c->delivery_system = SYS_DVBC_ANNEX_B;
break;
}
}
@@ -1129,9 +1124,9 @@
*/
static void dtv_property_adv_params_sync(struct dvb_frontend *fe)
{
- struct dtv_frontend_properties *c = &fe->dtv_property_cache;
+ const struct dtv_frontend_properties *c = &fe->dtv_property_cache;
struct dvb_frontend_private *fepriv = fe->frontend_priv;
- struct dvb_frontend_parameters *p = &fepriv->parameters;
+ struct dvb_frontend_parameters *p = &fepriv->parameters_in;
p->frequency = c->frequency;
p->inversion = c->inversion;
@@ -1148,10 +1143,9 @@
break;
}
- if(c->delivery_system == SYS_ISDBT) {
- /* Fake out a generic DVB-T request so we pass validation in the ioctl */
- p->frequency = c->frequency;
- p->inversion = c->inversion;
+ /* Fake out a generic DVB-T request so we pass validation in the ioctl */
+ if ((c->delivery_system == SYS_ISDBT) ||
+ (c->delivery_system == SYS_DVBT2)) {
p->u.ofdm.constellation = QAM_AUTO;
p->u.ofdm.code_rate_HP = FEC_AUTO;
p->u.ofdm.code_rate_LP = FEC_AUTO;
@@ -1171,7 +1165,7 @@
static void dtv_property_cache_submit(struct dvb_frontend *fe)
{
- struct dtv_frontend_properties *c = &fe->dtv_property_cache;
+ const struct dtv_frontend_properties *c = &fe->dtv_property_cache;
/* For legacy delivery systems we don't need the delivery_system to
* be specified, but we populate the older structures from the cache
@@ -1204,133 +1198,149 @@
struct dtv_property *tvp,
struct file *file)
{
- int r = 0;
+ const struct dtv_frontend_properties *c = &fe->dtv_property_cache;
+ struct dvb_frontend_private *fepriv = fe->frontend_priv;
+ struct dtv_frontend_properties cdetected;
+ int r;
- /* Allow the frontend to validate incoming properties */
- if (fe->ops.get_property)
- r = fe->ops.get_property(fe, tvp);
-
- if (r < 0)
- return r;
+ /*
+ * If the driver implements a get_frontend function, then convert
+ * detected parameters to S2API properties.
+ */
+ if (fe->ops.get_frontend) {
+ cdetected = *c;
+ dtv_property_cache_sync(fe, &cdetected, &fepriv->parameters_out);
+ c = &cdetected;
+ }
switch(tvp->cmd) {
case DTV_FREQUENCY:
- tvp->u.data = fe->dtv_property_cache.frequency;
+ tvp->u.data = c->frequency;
break;
case DTV_MODULATION:
- tvp->u.data = fe->dtv_property_cache.modulation;
+ tvp->u.data = c->modulation;
break;
case DTV_BANDWIDTH_HZ:
- tvp->u.data = fe->dtv_property_cache.bandwidth_hz;
+ tvp->u.data = c->bandwidth_hz;
break;
case DTV_INVERSION:
- tvp->u.data = fe->dtv_property_cache.inversion;
+ tvp->u.data = c->inversion;
break;
case DTV_SYMBOL_RATE:
- tvp->u.data = fe->dtv_property_cache.symbol_rate;
+ tvp->u.data = c->symbol_rate;
break;
case DTV_INNER_FEC:
- tvp->u.data = fe->dtv_property_cache.fec_inner;
+ tvp->u.data = c->fec_inner;
break;
case DTV_PILOT:
- tvp->u.data = fe->dtv_property_cache.pilot;
+ tvp->u.data = c->pilot;
break;
case DTV_ROLLOFF:
- tvp->u.data = fe->dtv_property_cache.rolloff;
+ tvp->u.data = c->rolloff;
break;
case DTV_DELIVERY_SYSTEM:
- tvp->u.data = fe->dtv_property_cache.delivery_system;
+ tvp->u.data = c->delivery_system;
break;
case DTV_VOLTAGE:
- tvp->u.data = fe->dtv_property_cache.voltage;
+ tvp->u.data = c->voltage;
break;
case DTV_TONE:
- tvp->u.data = fe->dtv_property_cache.sectone;
+ tvp->u.data = c->sectone;
break;
case DTV_API_VERSION:
tvp->u.data = (DVB_API_VERSION << 8) | DVB_API_VERSION_MINOR;
break;
case DTV_CODE_RATE_HP:
- tvp->u.data = fe->dtv_property_cache.code_rate_HP;
+ tvp->u.data = c->code_rate_HP;
break;
case DTV_CODE_RATE_LP:
- tvp->u.data = fe->dtv_property_cache.code_rate_LP;
+ tvp->u.data = c->code_rate_LP;
break;
case DTV_GUARD_INTERVAL:
- tvp->u.data = fe->dtv_property_cache.guard_interval;
+ tvp->u.data = c->guard_interval;
break;
case DTV_TRANSMISSION_MODE:
- tvp->u.data = fe->dtv_property_cache.transmission_mode;
+ tvp->u.data = c->transmission_mode;
break;
case DTV_HIERARCHY:
- tvp->u.data = fe->dtv_property_cache.hierarchy;
+ tvp->u.data = c->hierarchy;
break;
/* ISDB-T Support here */
case DTV_ISDBT_PARTIAL_RECEPTION:
- tvp->u.data = fe->dtv_property_cache.isdbt_partial_reception;
+ tvp->u.data = c->isdbt_partial_reception;
break;
case DTV_ISDBT_SOUND_BROADCASTING:
- tvp->u.data = fe->dtv_property_cache.isdbt_sb_mode;
+ tvp->u.data = c->isdbt_sb_mode;
break;
case DTV_ISDBT_SB_SUBCHANNEL_ID:
- tvp->u.data = fe->dtv_property_cache.isdbt_sb_subchannel;
+ tvp->u.data = c->isdbt_sb_subchannel;
break;
case DTV_ISDBT_SB_SEGMENT_IDX:
- tvp->u.data = fe->dtv_property_cache.isdbt_sb_segment_idx;
+ tvp->u.data = c->isdbt_sb_segment_idx;
break;
case DTV_ISDBT_SB_SEGMENT_COUNT:
- tvp->u.data = fe->dtv_property_cache.isdbt_sb_segment_count;
+ tvp->u.data = c->isdbt_sb_segment_count;
break;
case DTV_ISDBT_LAYER_ENABLED:
- tvp->u.data = fe->dtv_property_cache.isdbt_layer_enabled;
+ tvp->u.data = c->isdbt_layer_enabled;
break;
case DTV_ISDBT_LAYERA_FEC:
- tvp->u.data = fe->dtv_property_cache.layer[0].fec;
+ tvp->u.data = c->layer[0].fec;
break;
case DTV_ISDBT_LAYERA_MODULATION:
- tvp->u.data = fe->dtv_property_cache.layer[0].modulation;
+ tvp->u.data = c->layer[0].modulation;
break;
case DTV_ISDBT_LAYERA_SEGMENT_COUNT:
- tvp->u.data = fe->dtv_property_cache.layer[0].segment_count;
+ tvp->u.data = c->layer[0].segment_count;
break;
case DTV_ISDBT_LAYERA_TIME_INTERLEAVING:
- tvp->u.data = fe->dtv_property_cache.layer[0].interleaving;
+ tvp->u.data = c->layer[0].interleaving;
break;
case DTV_ISDBT_LAYERB_FEC:
- tvp->u.data = fe->dtv_property_cache.layer[1].fec;
+ tvp->u.data = c->layer[1].fec;
break;
case DTV_ISDBT_LAYERB_MODULATION:
- tvp->u.data = fe->dtv_property_cache.layer[1].modulation;
+ tvp->u.data = c->layer[1].modulation;
break;
case DTV_ISDBT_LAYERB_SEGMENT_COUNT:
- tvp->u.data = fe->dtv_property_cache.layer[1].segment_count;
+ tvp->u.data = c->layer[1].segment_count;
break;
case DTV_ISDBT_LAYERB_TIME_INTERLEAVING:
- tvp->u.data = fe->dtv_property_cache.layer[1].interleaving;
+ tvp->u.data = c->layer[1].interleaving;
break;
case DTV_ISDBT_LAYERC_FEC:
- tvp->u.data = fe->dtv_property_cache.layer[2].fec;
+ tvp->u.data = c->layer[2].fec;
break;
case DTV_ISDBT_LAYERC_MODULATION:
- tvp->u.data = fe->dtv_property_cache.layer[2].modulation;
+ tvp->u.data = c->layer[2].modulation;
break;
case DTV_ISDBT_LAYERC_SEGMENT_COUNT:
- tvp->u.data = fe->dtv_property_cache.layer[2].segment_count;
+ tvp->u.data = c->layer[2].segment_count;
break;
case DTV_ISDBT_LAYERC_TIME_INTERLEAVING:
- tvp->u.data = fe->dtv_property_cache.layer[2].interleaving;
+ tvp->u.data = c->layer[2].interleaving;
break;
case DTV_ISDBS_TS_ID:
- tvp->u.data = fe->dtv_property_cache.isdbs_ts_id;
+ tvp->u.data = c->isdbs_ts_id;
+ break;
+ case DTV_DVBT2_PLP_ID:
+ tvp->u.data = c->dvbt2_plp_id;
break;
default:
- r = -1;
+ return -EINVAL;
+ }
+
+ /* Allow the frontend to override outgoing properties */
+ if (fe->ops.get_property) {
+ r = fe->ops.get_property(fe, tvp);
+ if (r < 0)
+ return r;
}
dtv_property_dump(tvp);
- return r;
+ return 0;
}
static int dtv_property_process_set(struct dvb_frontend *fe,
@@ -1338,15 +1348,16 @@
struct file *file)
{
int r = 0;
+ struct dtv_frontend_properties *c = &fe->dtv_property_cache;
struct dvb_frontend_private *fepriv = fe->frontend_priv;
dtv_property_dump(tvp);
/* Allow the frontend to validate incoming properties */
- if (fe->ops.set_property)
+ if (fe->ops.set_property) {
r = fe->ops.set_property(fe, tvp);
-
- if (r < 0)
- return r;
+ if (r < 0)
+ return r;
+ }
switch(tvp->cmd) {
case DTV_CLEAR:
@@ -1361,126 +1372,129 @@
* tunerequest so we can pass validation in the FE_SET_FRONTEND
* ioctl.
*/
- fe->dtv_property_cache.state = tvp->cmd;
+ c->state = tvp->cmd;
dprintk("%s() Finalised property cache\n", __func__);
dtv_property_cache_submit(fe);
- r |= dvb_frontend_ioctl_legacy(file, FE_SET_FRONTEND,
- &fepriv->parameters);
+ r = dvb_frontend_ioctl_legacy(file, FE_SET_FRONTEND,
+ &fepriv->parameters_in);
break;
case DTV_FREQUENCY:
- fe->dtv_property_cache.frequency = tvp->u.data;
+ c->frequency = tvp->u.data;
break;
case DTV_MODULATION:
- fe->dtv_property_cache.modulation = tvp->u.data;
+ c->modulation = tvp->u.data;
break;
case DTV_BANDWIDTH_HZ:
- fe->dtv_property_cache.bandwidth_hz = tvp->u.data;
+ c->bandwidth_hz = tvp->u.data;
break;
case DTV_INVERSION:
- fe->dtv_property_cache.inversion = tvp->u.data;
+ c->inversion = tvp->u.data;
break;
case DTV_SYMBOL_RATE:
- fe->dtv_property_cache.symbol_rate = tvp->u.data;
+ c->symbol_rate = tvp->u.data;
break;
case DTV_INNER_FEC:
- fe->dtv_property_cache.fec_inner = tvp->u.data;
+ c->fec_inner = tvp->u.data;
break;
case DTV_PILOT:
- fe->dtv_property_cache.pilot = tvp->u.data;
+ c->pilot = tvp->u.data;
break;
case DTV_ROLLOFF:
- fe->dtv_property_cache.rolloff = tvp->u.data;
+ c->rolloff = tvp->u.data;
break;
case DTV_DELIVERY_SYSTEM:
- fe->dtv_property_cache.delivery_system = tvp->u.data;
+ c->delivery_system = tvp->u.data;
break;
case DTV_VOLTAGE:
- fe->dtv_property_cache.voltage = tvp->u.data;
+ c->voltage = tvp->u.data;
r = dvb_frontend_ioctl_legacy(file, FE_SET_VOLTAGE,
- (void *)fe->dtv_property_cache.voltage);
+ (void *)c->voltage);
break;
case DTV_TONE:
- fe->dtv_property_cache.sectone = tvp->u.data;
+ c->sectone = tvp->u.data;
r = dvb_frontend_ioctl_legacy(file, FE_SET_TONE,
- (void *)fe->dtv_property_cache.sectone);
+ (void *)c->sectone);
break;
case DTV_CODE_RATE_HP:
- fe->dtv_property_cache.code_rate_HP = tvp->u.data;
+ c->code_rate_HP = tvp->u.data;
break;
case DTV_CODE_RATE_LP:
- fe->dtv_property_cache.code_rate_LP = tvp->u.data;
+ c->code_rate_LP = tvp->u.data;
break;
case DTV_GUARD_INTERVAL:
- fe->dtv_property_cache.guard_interval = tvp->u.data;
+ c->guard_interval = tvp->u.data;
break;
case DTV_TRANSMISSION_MODE:
- fe->dtv_property_cache.transmission_mode = tvp->u.data;
+ c->transmission_mode = tvp->u.data;
break;
case DTV_HIERARCHY:
- fe->dtv_property_cache.hierarchy = tvp->u.data;
+ c->hierarchy = tvp->u.data;
break;
/* ISDB-T Support here */
case DTV_ISDBT_PARTIAL_RECEPTION:
- fe->dtv_property_cache.isdbt_partial_reception = tvp->u.data;
+ c->isdbt_partial_reception = tvp->u.data;
break;
case DTV_ISDBT_SOUND_BROADCASTING:
- fe->dtv_property_cache.isdbt_sb_mode = tvp->u.data;
+ c->isdbt_sb_mode = tvp->u.data;
break;
case DTV_ISDBT_SB_SUBCHANNEL_ID:
- fe->dtv_property_cache.isdbt_sb_subchannel = tvp->u.data;
+ c->isdbt_sb_subchannel = tvp->u.data;
break;
case DTV_ISDBT_SB_SEGMENT_IDX:
- fe->dtv_property_cache.isdbt_sb_segment_idx = tvp->u.data;
+ c->isdbt_sb_segment_idx = tvp->u.data;
break;
case DTV_ISDBT_SB_SEGMENT_COUNT:
- fe->dtv_property_cache.isdbt_sb_segment_count = tvp->u.data;
+ c->isdbt_sb_segment_count = tvp->u.data;
break;
case DTV_ISDBT_LAYER_ENABLED:
- fe->dtv_property_cache.isdbt_layer_enabled = tvp->u.data;
+ c->isdbt_layer_enabled = tvp->u.data;
break;
case DTV_ISDBT_LAYERA_FEC:
- fe->dtv_property_cache.layer[0].fec = tvp->u.data;
+ c->layer[0].fec = tvp->u.data;
break;
case DTV_ISDBT_LAYERA_MODULATION:
- fe->dtv_property_cache.layer[0].modulation = tvp->u.data;
+ c->layer[0].modulation = tvp->u.data;
break;
case DTV_ISDBT_LAYERA_SEGMENT_COUNT:
- fe->dtv_property_cache.layer[0].segment_count = tvp->u.data;
+ c->layer[0].segment_count = tvp->u.data;
break;
case DTV_ISDBT_LAYERA_TIME_INTERLEAVING:
- fe->dtv_property_cache.layer[0].interleaving = tvp->u.data;
+ c->layer[0].interleaving = tvp->u.data;
break;
case DTV_ISDBT_LAYERB_FEC:
- fe->dtv_property_cache.layer[1].fec = tvp->u.data;
+ c->layer[1].fec = tvp->u.data;
break;
case DTV_ISDBT_LAYERB_MODULATION:
- fe->dtv_property_cache.layer[1].modulation = tvp->u.data;
+ c->layer[1].modulation = tvp->u.data;
break;
case DTV_ISDBT_LAYERB_SEGMENT_COUNT:
- fe->dtv_property_cache.layer[1].segment_count = tvp->u.data;
+ c->layer[1].segment_count = tvp->u.data;
break;
case DTV_ISDBT_LAYERB_TIME_INTERLEAVING:
- fe->dtv_property_cache.layer[1].interleaving = tvp->u.data;
+ c->layer[1].interleaving = tvp->u.data;
break;
case DTV_ISDBT_LAYERC_FEC:
- fe->dtv_property_cache.layer[2].fec = tvp->u.data;
+ c->layer[2].fec = tvp->u.data;
break;
case DTV_ISDBT_LAYERC_MODULATION:
- fe->dtv_property_cache.layer[2].modulation = tvp->u.data;
+ c->layer[2].modulation = tvp->u.data;
break;
case DTV_ISDBT_LAYERC_SEGMENT_COUNT:
- fe->dtv_property_cache.layer[2].segment_count = tvp->u.data;
+ c->layer[2].segment_count = tvp->u.data;
break;
case DTV_ISDBT_LAYERC_TIME_INTERLEAVING:
- fe->dtv_property_cache.layer[2].interleaving = tvp->u.data;
+ c->layer[2].interleaving = tvp->u.data;
break;
case DTV_ISDBS_TS_ID:
- fe->dtv_property_cache.isdbs_ts_id = tvp->u.data;
+ c->isdbs_ts_id = tvp->u.data;
+ break;
+ case DTV_DVBT2_PLP_ID:
+ c->dvbt2_plp_id = tvp->u.data;
break;
default:
- r = -1;
+ return -EINVAL;
}
return r;
@@ -1491,6 +1505,7 @@
{
struct dvb_device *dvbdev = file->private_data;
struct dvb_frontend *fe = dvbdev->priv;
+ struct dtv_frontend_properties *c = &fe->dtv_property_cache;
struct dvb_frontend_private *fepriv = fe->frontend_priv;
int err = -EOPNOTSUPP;
@@ -1510,7 +1525,7 @@
if ((cmd == FE_SET_PROPERTY) || (cmd == FE_GET_PROPERTY))
err = dvb_frontend_ioctl_properties(file, cmd, parg);
else {
- fe->dtv_property_cache.state = DTV_UNDEFINED;
+ c->state = DTV_UNDEFINED;
err = dvb_frontend_ioctl_legacy(file, cmd, parg);
}
@@ -1523,6 +1538,7 @@
{
struct dvb_device *dvbdev = file->private_data;
struct dvb_frontend *fe = dvbdev->priv;
+ struct dtv_frontend_properties *c = &fe->dtv_property_cache;
int err = 0;
struct dtv_properties *tvps = NULL;
@@ -1554,11 +1570,13 @@
}
for (i = 0; i < tvps->num; i++) {
- (tvp + i)->result = dtv_property_process_set(fe, tvp + i, file);
- err |= (tvp + i)->result;
+ err = dtv_property_process_set(fe, tvp + i, file);
+ if (err < 0)
+ goto out;
+ (tvp + i)->result = err;
}
- if(fe->dtv_property_cache.state == DTV_TUNE)
+ if (c->state == DTV_TUNE)
dprintk("%s() Property cache is full, tuning\n", __func__);
} else
@@ -1586,8 +1604,10 @@
}
for (i = 0; i < tvps->num; i++) {
- (tvp + i)->result = dtv_property_process_get(fe, tvp + i, file);
- err |= (tvp + i)->result;
+ err = dtv_property_process_get(fe, tvp + i, file);
+ if (err < 0)
+ goto out;
+ (tvp + i)->result = err;
}
if (copy_to_user(tvps->props, tvp, tvps->num * sizeof(struct dtv_property))) {
@@ -1787,10 +1807,11 @@
break;
case FE_SET_FRONTEND: {
+ struct dtv_frontend_properties *c = &fe->dtv_property_cache;
struct dvb_frontend_tune_settings fetunesettings;
- if(fe->dtv_property_cache.state == DTV_TUNE) {
- if (dvb_frontend_check_parameters(fe, &fepriv->parameters) < 0) {
+ if (c->state == DTV_TUNE) {
+ if (dvb_frontend_check_parameters(fe, &fepriv->parameters_in) < 0) {
err = -EINVAL;
break;
}
@@ -1800,9 +1821,9 @@
break;
}
- memcpy (&fepriv->parameters, parg,
+ memcpy (&fepriv->parameters_in, parg,
sizeof (struct dvb_frontend_parameters));
- dtv_property_cache_sync(fe, &fepriv->parameters);
+ dtv_property_cache_sync(fe, c, &fepriv->parameters_in);
}
memset(&fetunesettings, 0, sizeof(struct dvb_frontend_tune_settings));
@@ -1811,15 +1832,15 @@
/* force auto frequency inversion if requested */
if (dvb_force_auto_inversion) {
- fepriv->parameters.inversion = INVERSION_AUTO;
+ fepriv->parameters_in.inversion = INVERSION_AUTO;
fetunesettings.parameters.inversion = INVERSION_AUTO;
}
if (fe->ops.info.type == FE_OFDM) {
/* without hierarchical coding code_rate_LP is irrelevant,
* so we tolerate the otherwise invalid FEC_NONE setting */
- if (fepriv->parameters.u.ofdm.hierarchy_information == HIERARCHY_NONE &&
- fepriv->parameters.u.ofdm.code_rate_LP == FEC_NONE)
- fepriv->parameters.u.ofdm.code_rate_LP = FEC_AUTO;
+ if (fepriv->parameters_in.u.ofdm.hierarchy_information == HIERARCHY_NONE &&
+ fepriv->parameters_in.u.ofdm.code_rate_LP == FEC_NONE)
+ fepriv->parameters_in.u.ofdm.code_rate_LP = FEC_AUTO;
}
/* get frontend-specific tuning settings */
@@ -1832,8 +1853,8 @@
switch(fe->ops.info.type) {
case FE_QPSK:
fepriv->min_delay = HZ/20;
- fepriv->step_size = fepriv->parameters.u.qpsk.symbol_rate / 16000;
- fepriv->max_drift = fepriv->parameters.u.qpsk.symbol_rate / 2000;
+ fepriv->step_size = fepriv->parameters_in.u.qpsk.symbol_rate / 16000;
+ fepriv->max_drift = fepriv->parameters_in.u.qpsk.symbol_rate / 2000;
break;
case FE_QAM:
@@ -1875,8 +1896,8 @@
case FE_GET_FRONTEND:
if (fe->ops.get_frontend) {
- memcpy (parg, &fepriv->parameters, sizeof (struct dvb_frontend_parameters));
- err = fe->ops.get_frontend(fe, (struct dvb_frontend_parameters*) parg);
+ err = fe->ops.get_frontend(fe, &fepriv->parameters_out);
+ memcpy(parg, &fepriv->parameters_out, sizeof(struct dvb_frontend_parameters));
}
break;
diff --git a/drivers/media/dvb/dvb-core/dvb_frontend.h b/drivers/media/dvb/dvb-core/dvb_frontend.h
index 3b86050..5590eb6 100644
--- a/drivers/media/dvb/dvb-core/dvb_frontend.h
+++ b/drivers/media/dvb/dvb-core/dvb_frontend.h
@@ -358,6 +358,9 @@
/* ISDB-T specifics */
u32 isdbs_ts_id;
+
+ /* DVB-T2 specifics */
+ u32 dvbt2_plp_id;
};
struct dvb_frontend {
diff --git a/drivers/media/dvb/dvb-usb/Kconfig b/drivers/media/dvb/dvb-usb/Kconfig
index c545039..e85304c 100644
--- a/drivers/media/dvb/dvb-usb/Kconfig
+++ b/drivers/media/dvb/dvb-usb/Kconfig
@@ -292,6 +292,11 @@
select DVB_MT352 if !DVB_FE_CUSTOMISE
select DVB_ZL10353 if !DVB_FE_CUSTOMISE
select DVB_TDA10023 if !DVB_FE_CUSTOMISE
+ select MEDIA_TUNER_TDA18212 if !MEDIA_TUNER_CUSTOMISE
+ select DVB_CX24116 if !DVB_FE_CUSTOMISE
+ select DVB_STV0900 if !DVB_FE_CUSTOMISE
+ select DVB_STV6110 if !DVB_FE_CUSTOMISE
+ select DVB_ISL6423 if !DVB_FE_CUSTOMISE
help
Say Y here to support the Anysee E30, Anysee E30 Plus or
Anysee E30 C Plus DVB USB2.0 receiver.
diff --git a/drivers/media/dvb/dvb-usb/a800.c b/drivers/media/dvb/dvb-usb/a800.c
index f8e9bf1..b95a95e 100644
--- a/drivers/media/dvb/dvb-usb/a800.c
+++ b/drivers/media/dvb/dvb-usb/a800.c
@@ -78,17 +78,26 @@
static int a800_rc_query(struct dvb_usb_device *d, u32 *event, int *state)
{
- u8 key[5];
+ int ret;
+ u8 *key = kmalloc(5, GFP_KERNEL);
+ if (!key)
+ return -ENOMEM;
+
if (usb_control_msg(d->udev,usb_rcvctrlpipe(d->udev,0),
0x04, USB_TYPE_VENDOR | USB_DIR_IN, 0, 0, key, 5,
- 2000) != 5)
- return -ENODEV;
+ 2000) != 5) {
+ ret = -ENODEV;
+ goto out;
+ }
/* call the universal NEC remote processor, to find out the key's state and event */
dvb_usb_nec_rc_key_to_event(d,key,event,state);
if (key[0] != 0)
deb_rc("key: %x %x %x %x %x\n",key[0],key[1],key[2],key[3],key[4]);
- return 0;
+ ret = 0;
+out:
+ kfree(key);
+ return ret;
}
/* USB Driver stuff */
diff --git a/drivers/media/dvb/dvb-usb/anysee.c b/drivers/media/dvb/dvb-usb/anysee.c
index 6b402e9..4dc1ca3 100644
--- a/drivers/media/dvb/dvb-usb/anysee.c
+++ b/drivers/media/dvb/dvb-usb/anysee.c
@@ -36,6 +36,11 @@
#include "mt352.h"
#include "mt352_priv.h"
#include "zl10353.h"
+#include "tda18212.h"
+#include "cx24116.h"
+#include "stv0900.h"
+#include "stv6110.h"
+#include "isl6423.h"
/* debug */
static int dvb_usb_anysee_debug;
@@ -105,6 +110,27 @@
return anysee_ctrl_msg(d, buf, sizeof(buf), NULL, 0);
}
+/* write single register with mask */
+static int anysee_wr_reg_mask(struct dvb_usb_device *d, u16 reg, u8 val,
+ u8 mask)
+{
+ int ret;
+ u8 tmp;
+
+ /* no need for read if whole reg is written */
+ if (mask != 0xff) {
+ ret = anysee_read_reg(d, reg, &tmp);
+ if (ret)
+ return ret;
+
+ val &= mask;
+ tmp &= ~mask;
+ val |= tmp;
+ }
+
+ return anysee_write_reg(d, reg, val);
+}
+
static int anysee_get_hw_info(struct dvb_usb_device *d, u8 *id)
{
u8 buf[] = {CMD_GET_HW_INFO};
@@ -162,18 +188,18 @@
if (num > i + 1 && (msg[i+1].flags & I2C_M_RD)) {
u8 buf[6];
buf[0] = CMD_I2C_READ;
- buf[1] = msg[i].addr + 1;
+ buf[1] = (msg[i].addr << 1) | 0x01;
buf[2] = msg[i].buf[0];
- buf[3] = 0x00;
- buf[4] = 0x00;
- buf[5] = 0x01;
+ buf[3] = msg[i].buf[1];
+ buf[4] = msg[i].len-1;
+ buf[5] = msg[i+1].len;
ret = anysee_ctrl_msg(d, buf, sizeof(buf), msg[i+1].buf,
msg[i+1].len);
inc = 2;
} else {
u8 buf[4+msg[i].len];
buf[0] = CMD_I2C_WRITE;
- buf[1] = msg[i].addr;
+ buf[1] = (msg[i].addr << 1);
buf[2] = msg[i].len;
buf[3] = 0x01;
memcpy(&buf[4], msg[i].buf, msg[i].len);
@@ -224,7 +250,7 @@
/* Callbacks for DVB USB */
static struct tda10023_config anysee_tda10023_config = {
- .demod_address = 0x1a,
+ .demod_address = (0x1a >> 1),
.invert = 0,
.xtal = 16000000,
.pll_m = 11,
@@ -235,143 +261,539 @@
};
static struct mt352_config anysee_mt352_config = {
- .demod_address = 0x1e,
+ .demod_address = (0x1e >> 1),
.demod_init = anysee_mt352_demod_init,
};
static struct zl10353_config anysee_zl10353_config = {
- .demod_address = 0x1e,
+ .demod_address = (0x1e >> 1),
.parallel_ts = 1,
};
+static struct zl10353_config anysee_zl10353_tda18212_config2 = {
+ .demod_address = (0x1e >> 1),
+ .parallel_ts = 1,
+ .disable_i2c_gate_ctrl = 1,
+ .no_tuner = 1,
+ .if2 = 41500,
+};
+
+static struct zl10353_config anysee_zl10353_tda18212_config = {
+ .demod_address = (0x18 >> 1),
+ .parallel_ts = 1,
+ .disable_i2c_gate_ctrl = 1,
+ .no_tuner = 1,
+ .if2 = 41500,
+};
+
+static struct tda10023_config anysee_tda10023_tda18212_config = {
+ .demod_address = (0x1a >> 1),
+ .xtal = 16000000,
+ .pll_m = 12,
+ .pll_p = 3,
+ .pll_n = 1,
+ .output_mode = TDA10023_OUTPUT_MODE_PARALLEL_C,
+ .deltaf = 0xba02,
+};
+
+static struct tda18212_config anysee_tda18212_config = {
+ .i2c_address = (0xc0 >> 1),
+ .if_dvbt_6 = 4150,
+ .if_dvbt_7 = 4150,
+ .if_dvbt_8 = 4150,
+ .if_dvbc = 5000,
+};
+
+static struct cx24116_config anysee_cx24116_config = {
+ .demod_address = (0xaa >> 1),
+ .mpg_clk_pos_pol = 0x00,
+ .i2c_wr_max = 48,
+};
+
+static struct stv0900_config anysee_stv0900_config = {
+ .demod_address = (0xd0 >> 1),
+ .demod_mode = 0,
+ .xtal = 8000000,
+ .clkmode = 3,
+ .diseqc_mode = 2,
+ .tun1_maddress = 0,
+ .tun1_adc = 1, /* 1 Vpp */
+ .path1_mode = 3,
+};
+
+static struct stv6110_config anysee_stv6110_config = {
+ .i2c_address = (0xc0 >> 1),
+ .mclk = 16000000,
+ .clk_div = 1,
+};
+
+static struct isl6423_config anysee_isl6423_config = {
+ .current_max = SEC_CURRENT_800m,
+ .curlim = SEC_CURRENT_LIM_OFF,
+ .mod_extern = 1,
+ .addr = (0x10 >> 1),
+};
+
+/*
+ * New USB device strings: Mfr=1, Product=2, SerialNumber=0
+ * Manufacturer: AMT.CO.KR
+ *
+ * E30 VID=04b4 PID=861f HW=2 FW=2.1 Product=????????
+ * PCB: ?
+ * parts: DNOS404ZH102A(MT352, DTT7579(?))
+ *
+ * E30 VID=04b4 PID=861f HW=2 FW=2.1 Product=????????
+ * PCB: ?
+ * parts: DNOS404ZH103A(ZL10353, DTT7579(?))
+ *
+ * E30 Plus VID=04b4 PID=861f HW=6 FW=1.0 "anysee"
+ * PCB: 507CD (rev1.1)
+ * parts: DNOS404ZH103A(ZL10353, DTT7579(?)), CST56I01
+ * OEA=80 OEB=00 OEC=00 OED=ff OEF=fe
+ * IOA=4f IOB=ff IOC=00 IOD=06 IOF=01
+ * IOD[0] ZL10353 1=enabled
+ * IOA[7] TS 0=enabled
+ * tuner is not behind ZL10353 I2C-gate (no care if gate disabled or not)
+ *
+ * E30 C Plus VID=04b4 PID=861f HW=10 FW=1.0 "anysee-DC(LP)"
+ * PCB: 507DC (rev0.2)
+ * parts: TDA10023, DTOS403IH102B TM, CST56I01
+ * OEA=80 OEB=00 OEC=00 OED=ff OEF=fe
+ * IOA=4f IOB=ff IOC=00 IOD=26 IOF=01
+ * IOD[0] TDA10023 1=enabled
+ *
+ * E30 S2 Plus VID=04b4 PID=861f HW=11 FW=0.1 "anysee-S2(LP)"
+ * PCB: 507SI (rev2.1)
+ * parts: BS2N10WCC01(CX24116, CX24118), ISL6423, TDA8024
+ * OEA=80 OEB=00 OEC=ff OED=ff OEF=fe
+ * IOA=4d IOB=ff IOC=00 IOD=26 IOF=01
+ * IOD[0] CX24116 1=enabled
+ *
+ * E30 C Plus VID=1c73 PID=861f HW=15 FW=1.2 "anysee-FA(LP)"
+ * PCB: 507FA (rev0.4)
+ * parts: TDA10023, DTOS403IH102B TM, TDA8024
+ * OEA=80 OEB=00 OEC=ff OED=ff OEF=ff
+ * IOA=4d IOB=ff IOC=00 IOD=00 IOF=c0
+ * IOD[5] TDA10023 1=enabled
+ * IOE[0] tuner 1=enabled
+ *
+ * E30 Combo Plus VID=1c73 PID=861f HW=15 FW=1.2 "anysee-FA(LP)"
+ * PCB: 507FA (rev1.1)
+ * parts: ZL10353, TDA10023, DTOS403IH102B TM, TDA8024
+ * OEA=80 OEB=00 OEC=ff OED=ff OEF=ff
+ * IOA=4d IOB=ff IOC=00 IOD=00 IOF=c0
+ * DVB-C:
+ * IOD[5] TDA10023 1=enabled
+ * IOE[0] tuner 1=enabled
+ * DVB-T:
+ * IOD[0] ZL10353 1=enabled
+ * IOE[0] tuner 0=enabled
+ * tuner is behind ZL10353 I2C-gate
+ *
+ * E7 TC VID=1c73 PID=861f HW=18 FW=0.7 AMTCI=0.5 "anysee-E7TC(LP)"
+ * PCB: 508TC (rev0.6)
+ * parts: ZL10353, TDA10023, DNOD44CDH086A(TDA18212)
+ * OEA=80 OEB=00 OEC=03 OED=f7 OEF=ff
+ * IOA=4d IOB=00 IOC=cc IOD=48 IOF=e4
+ * IOA[7] TS 1=enabled
+ * IOE[4] TDA18212 1=enabled
+ * DVB-C:
+ * IOD[6] ZL10353 0=disabled
+ * IOD[5] TDA10023 1=enabled
+ * IOE[0] IF 1=enabled
+ * DVB-T:
+ * IOD[5] TDA10023 0=disabled
+ * IOD[6] ZL10353 1=enabled
+ * IOE[0] IF 0=enabled
+ *
+ * E7 S2 VID=1c73 PID=861f HW=19 FW=0.4 AMTCI=0.5 "anysee-E7S2(LP)"
+ * PCB: 508S2 (rev0.7)
+ * parts: DNBU10512IST(STV0903, STV6110), ISL6423
+ * OEA=80 OEB=00 OEC=03 OED=f7 OEF=ff
+ * IOA=4d IOB=00 IOC=c4 IOD=08 IOF=e4
+ * IOA[7] TS 1=enabled
+ * IOE[5] STV0903 1=enabled
+ *
+ */
+
static int anysee_frontend_attach(struct dvb_usb_adapter *adap)
{
int ret;
struct anysee_state *state = adap->dev->priv;
u8 hw_info[3];
- u8 io_d; /* IO port D */
+ u8 tmp;
+ struct i2c_msg msg[2] = {
+ {
+ .addr = anysee_tda18212_config.i2c_address,
+ .flags = 0,
+ .len = 1,
+ .buf = "\x00",
+ }, {
+ .addr = anysee_tda18212_config.i2c_address,
+ .flags = I2C_M_RD,
+ .len = 1,
+ .buf = &tmp,
+ }
+ };
- /* check which hardware we have
- We must do this call two times to get reliable values (hw bug). */
+ /* Check which hardware we have.
+ * We must do this call two times to get reliable values (hw bug).
+ */
ret = anysee_get_hw_info(adap->dev, hw_info);
if (ret)
- return ret;
+ goto error;
+
ret = anysee_get_hw_info(adap->dev, hw_info);
if (ret)
- return ret;
+ goto error;
/* Meaning of these info bytes are guessed. */
- info("firmware version:%d.%d.%d hardware id:%d",
- 0, hw_info[1], hw_info[2], hw_info[0]);
+ info("firmware version:%d.%d hardware id:%d",
+ hw_info[1], hw_info[2], hw_info[0]);
- ret = anysee_read_reg(adap->dev, 0xb0, &io_d); /* IO port D */
- if (ret)
- return ret;
- deb_info("%s: IO port D:%02x\n", __func__, io_d);
+ state->hw = hw_info[0];
- /* Select demod using trial and error method. */
+ switch (state->hw) {
+ case ANYSEE_HW_02: /* 2 */
+ /* E30 */
- /* Try to attach demodulator in following order:
- model demod hw firmware
- 1. E30 MT352 02 0.2.1
- 2. E30 ZL10353 02 0.2.1
- 3. E30 Combo ZL10353 0f 0.1.2 DVB-T/C combo
- 4. E30 Plus ZL10353 06 0.1.0
- 5. E30C Plus TDA10023 0a 0.1.0 rev 0.2
- E30C Plus TDA10023 0f 0.1.2 rev 0.4
- E30 Combo TDA10023 0f 0.1.2 DVB-T/C combo
- */
+ /* attach demod */
+ adap->fe = dvb_attach(mt352_attach, &anysee_mt352_config,
+ &adap->dev->i2c_adap);
+ if (adap->fe)
+ break;
- /* Zarlink MT352 DVB-T demod inside of Samsung DNOS404ZH102A NIM */
- adap->fe = dvb_attach(mt352_attach, &anysee_mt352_config,
- &adap->dev->i2c_adap);
- if (adap->fe != NULL) {
- state->tuner = DVB_PLL_THOMSON_DTT7579;
- return 0;
- }
-
- /* Zarlink ZL10353 DVB-T demod inside of Samsung DNOS404ZH103A NIM */
- adap->fe = dvb_attach(zl10353_attach, &anysee_zl10353_config,
- &adap->dev->i2c_adap);
- if (adap->fe != NULL) {
- state->tuner = DVB_PLL_THOMSON_DTT7579;
- return 0;
- }
-
- /* for E30 Combo Plus DVB-T demodulator */
- if (dvb_usb_anysee_delsys) {
- ret = anysee_write_reg(adap->dev, 0xb0, 0x01);
- if (ret)
- return ret;
-
- /* Zarlink ZL10353 DVB-T demod */
+ /* attach demod */
adap->fe = dvb_attach(zl10353_attach, &anysee_zl10353_config,
- &adap->dev->i2c_adap);
- if (adap->fe != NULL) {
- state->tuner = DVB_PLL_SAMSUNG_DTOS403IH102A;
- return 0;
+ &adap->dev->i2c_adap);
+
+ break;
+ case ANYSEE_HW_507CD: /* 6 */
+ /* E30 Plus */
+
+ /* enable DVB-T demod on IOD[0] */
+ ret = anysee_wr_reg_mask(adap->dev, REG_IOD, (1 << 0), 0x01);
+ if (ret)
+ goto error;
+
+ /* enable transport stream on IOA[7] */
+ ret = anysee_wr_reg_mask(adap->dev, REG_IOA, (0 << 7), 0x80);
+ if (ret)
+ goto error;
+
+ /* attach demod */
+ adap->fe = dvb_attach(zl10353_attach, &anysee_zl10353_config,
+ &adap->dev->i2c_adap);
+
+ break;
+ case ANYSEE_HW_507DC: /* 10 */
+ /* E30 C Plus */
+
+ /* enable DVB-C demod on IOD[0] */
+ ret = anysee_wr_reg_mask(adap->dev, REG_IOD, (1 << 0), 0x01);
+ if (ret)
+ goto error;
+
+ /* attach demod */
+ adap->fe = dvb_attach(tda10023_attach, &anysee_tda10023_config,
+ &adap->dev->i2c_adap, 0x48);
+
+ break;
+ case ANYSEE_HW_507SI: /* 11 */
+ /* E30 S2 Plus */
+
+ /* enable DVB-S/S2 demod on IOD[0] */
+ ret = anysee_wr_reg_mask(adap->dev, REG_IOD, (1 << 0), 0x01);
+ if (ret)
+ goto error;
+
+ /* attach demod */
+ adap->fe = dvb_attach(cx24116_attach, &anysee_cx24116_config,
+ &adap->dev->i2c_adap);
+
+ break;
+ case ANYSEE_HW_507FA: /* 15 */
+ /* E30 Combo Plus */
+ /* E30 C Plus */
+
+ /* enable tuner on IOE[4] */
+ ret = anysee_wr_reg_mask(adap->dev, REG_IOE, (1 << 4), 0x10);
+ if (ret)
+ goto error;
+
+ /* probe TDA18212 */
+ tmp = 0;
+ ret = i2c_transfer(&adap->dev->i2c_adap, msg, 2);
+ if (ret == 2 && tmp == 0xc7)
+ deb_info("%s: TDA18212 found\n", __func__);
+ else
+ tmp = 0;
+
+ /* disable tuner on IOE[4] */
+ ret = anysee_wr_reg_mask(adap->dev, REG_IOE, (0 << 4), 0x10);
+ if (ret)
+ goto error;
+
+ if (dvb_usb_anysee_delsys) {
+ /* disable DVB-C demod on IOD[5] */
+ ret = anysee_wr_reg_mask(adap->dev, REG_IOD, (0 << 5),
+ 0x20);
+ if (ret)
+ goto error;
+
+ /* enable DVB-T demod on IOD[0] */
+ ret = anysee_wr_reg_mask(adap->dev, REG_IOD, (1 << 0),
+ 0x01);
+ if (ret)
+ goto error;
+
+ /* attach demod */
+ if (tmp == 0xc7) {
+ /* TDA18212 config */
+ adap->fe = dvb_attach(zl10353_attach,
+ &anysee_zl10353_tda18212_config2,
+ &adap->dev->i2c_adap);
+ } else {
+ /* PLL config */
+ adap->fe = dvb_attach(zl10353_attach,
+ &anysee_zl10353_config,
+ &adap->dev->i2c_adap);
+ }
+ } else {
+ /* disable DVB-T demod on IOD[0] */
+ ret = anysee_wr_reg_mask(adap->dev, REG_IOD, (0 << 0),
+ 0x01);
+ if (ret)
+ goto error;
+
+ /* enable DVB-C demod on IOD[5] */
+ ret = anysee_wr_reg_mask(adap->dev, REG_IOD, (1 << 5),
+ 0x20);
+ if (ret)
+ goto error;
+
+ /* attach demod */
+ if (tmp == 0xc7) {
+ /* TDA18212 config */
+ adap->fe = dvb_attach(tda10023_attach,
+ &anysee_tda10023_tda18212_config,
+ &adap->dev->i2c_adap, 0x48);
+ } else {
+ /* PLL config */
+ adap->fe = dvb_attach(tda10023_attach,
+ &anysee_tda10023_config,
+ &adap->dev->i2c_adap, 0x48);
+ }
}
+
+ break;
+ case ANYSEE_HW_508TC: /* 18 */
+ /* E7 TC */
+
+ /* enable transport stream on IOA[7] */
+ ret = anysee_wr_reg_mask(adap->dev, REG_IOA, (1 << 7), 0x80);
+ if (ret)
+ goto error;
+
+ if (dvb_usb_anysee_delsys) {
+ /* disable DVB-C demod on IOD[5] */
+ ret = anysee_wr_reg_mask(adap->dev, REG_IOD, (0 << 5),
+ 0x20);
+ if (ret)
+ goto error;
+
+ /* enable DVB-T demod on IOD[6] */
+ ret = anysee_wr_reg_mask(adap->dev, REG_IOD, (1 << 6),
+ 0x40);
+ if (ret)
+ goto error;
+
+ /* enable IF route on IOE[0] */
+ ret = anysee_wr_reg_mask(adap->dev, REG_IOE, (0 << 0),
+ 0x01);
+ if (ret)
+ goto error;
+
+ /* attach demod */
+ adap->fe = dvb_attach(zl10353_attach,
+ &anysee_zl10353_tda18212_config,
+ &adap->dev->i2c_adap);
+ } else {
+ /* disable DVB-T demod on IOD[6] */
+ ret = anysee_wr_reg_mask(adap->dev, REG_IOD, (0 << 6),
+ 0x40);
+ if (ret)
+ goto error;
+
+ /* enable DVB-C demod on IOD[5] */
+ ret = anysee_wr_reg_mask(adap->dev, REG_IOD, (1 << 5),
+ 0x20);
+ if (ret)
+ goto error;
+
+ /* enable IF route on IOE[0] */
+ ret = anysee_wr_reg_mask(adap->dev, REG_IOE, (1 << 0),
+ 0x01);
+ if (ret)
+ goto error;
+
+ /* attach demod */
+ adap->fe = dvb_attach(tda10023_attach,
+ &anysee_tda10023_tda18212_config,
+ &adap->dev->i2c_adap, 0x48);
+ }
+
+ break;
+ case ANYSEE_HW_508S2: /* 19 */
+ /* E7 S2 */
+
+ /* enable transport stream on IOA[7] */
+ ret = anysee_wr_reg_mask(adap->dev, REG_IOA, (1 << 7), 0x80);
+ if (ret)
+ goto error;
+
+ /* enable DVB-S/S2 demod on IOE[5] */
+ ret = anysee_wr_reg_mask(adap->dev, REG_IOE, (1 << 5), 0x20);
+ if (ret)
+ goto error;
+
+ /* attach demod */
+ adap->fe = dvb_attach(stv0900_attach, &anysee_stv0900_config,
+ &adap->dev->i2c_adap, 0);
+
+ break;
}
- /* connect demod on IO port D for TDA10023 & ZL10353 */
- ret = anysee_write_reg(adap->dev, 0xb0, 0x25);
- if (ret)
- return ret;
-
- /* Zarlink ZL10353 DVB-T demod inside of Samsung DNOS404ZH103A NIM */
- adap->fe = dvb_attach(zl10353_attach, &anysee_zl10353_config,
- &adap->dev->i2c_adap);
- if (adap->fe != NULL) {
- state->tuner = DVB_PLL_THOMSON_DTT7579;
- return 0;
+ if (!adap->fe) {
+ /* we have no frontend :-( */
+ ret = -ENODEV;
+ err("Unsupported Anysee version. " \
+ "Please report the <linux-media@vger.kernel.org>.");
}
-
- /* IO port E - E30C rev 0.4 board requires this */
- ret = anysee_write_reg(adap->dev, 0xb1, 0xa7);
- if (ret)
- return ret;
-
- /* Philips TDA10023 DVB-C demod */
- adap->fe = dvb_attach(tda10023_attach, &anysee_tda10023_config,
- &adap->dev->i2c_adap, 0x48);
- if (adap->fe != NULL) {
- state->tuner = DVB_PLL_SAMSUNG_DTOS403IH102A;
- return 0;
- }
-
- /* return IO port D to init value for safe */
- ret = anysee_write_reg(adap->dev, 0xb0, io_d);
- if (ret)
- return ret;
-
- err("Unknown Anysee version: %02x %02x %02x. "\
- "Please report the <linux-dvb@linuxtv.org>.",
- hw_info[0], hw_info[1], hw_info[2]);
-
- return -ENODEV;
+error:
+ return ret;
}
static int anysee_tuner_attach(struct dvb_usb_adapter *adap)
{
struct anysee_state *state = adap->dev->priv;
+ struct dvb_frontend *fe;
+ int ret;
deb_info("%s:\n", __func__);
- switch (state->tuner) {
- case DVB_PLL_THOMSON_DTT7579:
- /* Thomson dtt7579 (not sure) PLL inside of:
- Samsung DNOS404ZH102A NIM
- Samsung DNOS404ZH103A NIM */
- dvb_attach(dvb_pll_attach, adap->fe, 0x61,
- NULL, DVB_PLL_THOMSON_DTT7579);
+ switch (state->hw) {
+ case ANYSEE_HW_02: /* 2 */
+ /* E30 */
+
+ /* attach tuner */
+ fe = dvb_attach(dvb_pll_attach, adap->fe, (0xc2 >> 1),
+ NULL, DVB_PLL_THOMSON_DTT7579);
+
break;
- case DVB_PLL_SAMSUNG_DTOS403IH102A:
- /* Unknown PLL inside of Samsung DTOS403IH102A tuner module */
- dvb_attach(dvb_pll_attach, adap->fe, 0xc0,
- &adap->dev->i2c_adap, DVB_PLL_SAMSUNG_DTOS403IH102A);
+ case ANYSEE_HW_507CD: /* 6 */
+ /* E30 Plus */
+
+ /* attach tuner */
+ fe = dvb_attach(dvb_pll_attach, adap->fe, (0xc2 >> 1),
+ &adap->dev->i2c_adap, DVB_PLL_THOMSON_DTT7579);
+
break;
+ case ANYSEE_HW_507DC: /* 10 */
+ /* E30 C Plus */
+
+ /* attach tuner */
+ fe = dvb_attach(dvb_pll_attach, adap->fe, (0xc0 >> 1),
+ &adap->dev->i2c_adap, DVB_PLL_SAMSUNG_DTOS403IH102A);
+
+ break;
+ case ANYSEE_HW_507SI: /* 11 */
+ /* E30 S2 Plus */
+
+ /* attach LNB controller */
+ fe = dvb_attach(isl6423_attach, adap->fe, &adap->dev->i2c_adap,
+ &anysee_isl6423_config);
+
+ break;
+ case ANYSEE_HW_507FA: /* 15 */
+ /* E30 Combo Plus */
+ /* E30 C Plus */
+
+ if (dvb_usb_anysee_delsys) {
+ /* enable DVB-T tuner on IOE[0] */
+ ret = anysee_wr_reg_mask(adap->dev, REG_IOE, (0 << 0),
+ 0x01);
+ if (ret)
+ goto error;
+ } else {
+ /* enable DVB-C tuner on IOE[0] */
+ ret = anysee_wr_reg_mask(adap->dev, REG_IOE, (1 << 0),
+ 0x01);
+ if (ret)
+ goto error;
+ }
+
+ /* Try first attach TDA18212 silicon tuner on IOE[4], if that
+ * fails attach old simple PLL. */
+
+ /* enable tuner on IOE[4] */
+ ret = anysee_wr_reg_mask(adap->dev, REG_IOE, (1 << 4), 0x10);
+ if (ret)
+ goto error;
+
+ /* attach tuner */
+ fe = dvb_attach(tda18212_attach, adap->fe, &adap->dev->i2c_adap,
+ &anysee_tda18212_config);
+ if (fe)
+ break;
+
+ /* disable tuner on IOE[4] */
+ ret = anysee_wr_reg_mask(adap->dev, REG_IOE, (0 << 4), 0x10);
+ if (ret)
+ goto error;
+
+ /* attach tuner */
+ fe = dvb_attach(dvb_pll_attach, adap->fe, (0xc0 >> 1),
+ &adap->dev->i2c_adap, DVB_PLL_SAMSUNG_DTOS403IH102A);
+
+ break;
+ case ANYSEE_HW_508TC: /* 18 */
+ /* E7 TC */
+
+ /* enable tuner on IOE[4] */
+ ret = anysee_wr_reg_mask(adap->dev, REG_IOE, (1 << 4), 0x10);
+ if (ret)
+ goto error;
+
+ /* attach tuner */
+ fe = dvb_attach(tda18212_attach, adap->fe, &adap->dev->i2c_adap,
+ &anysee_tda18212_config);
+
+ break;
+ case ANYSEE_HW_508S2: /* 19 */
+ /* E7 S2 */
+
+ /* attach tuner */
+ fe = dvb_attach(stv6110_attach, adap->fe,
+ &anysee_stv6110_config, &adap->dev->i2c_adap);
+
+ if (fe) {
+ /* attach LNB controller */
+ fe = dvb_attach(isl6423_attach, adap->fe,
+ &adap->dev->i2c_adap, &anysee_isl6423_config);
+ }
+
+ break;
+ default:
+ fe = NULL;
}
- return 0;
+ if (fe)
+ ret = 0;
+ else
+ ret = -ENODEV;
+
+error:
+ return ret;
}
static int anysee_rc_query(struct dvb_usb_device *d)
diff --git a/drivers/media/dvb/dvb-usb/anysee.h b/drivers/media/dvb/dvb-usb/anysee.h
index 7ca01ff..a7673aa 100644
--- a/drivers/media/dvb/dvb-usb/anysee.h
+++ b/drivers/media/dvb/dvb-usb/anysee.h
@@ -57,10 +57,29 @@
};
struct anysee_state {
- u8 tuner;
+ u8 hw; /* PCB ID */
u8 seq;
};
+#define ANYSEE_HW_02 2 /* E30 */
+#define ANYSEE_HW_507CD 6 /* E30 Plus */
+#define ANYSEE_HW_507DC 10 /* E30 C Plus */
+#define ANYSEE_HW_507SI 11 /* E30 S2 Plus */
+#define ANYSEE_HW_507FA 15 /* E30 Combo Plus / E30 C Plus */
+#define ANYSEE_HW_508TC 18 /* E7 TC */
+#define ANYSEE_HW_508S2 19 /* E7 S2 */
+
+#define REG_IOA 0x80 /* Port A (bit addressable) */
+#define REG_IOB 0x90 /* Port B (bit addressable) */
+#define REG_IOC 0xa0 /* Port C (bit addressable) */
+#define REG_IOD 0xb0 /* Port D (bit addressable) */
+#define REG_IOE 0xb1 /* Port E (NOT bit addressable) */
+#define REG_OEA 0xb2 /* Port A Output Enable */
+#define REG_OEB 0xb3 /* Port B Output Enable */
+#define REG_OEC 0xb4 /* Port C Output Enable */
+#define REG_OED 0xb5 /* Port D Output Enable */
+#define REG_OEE 0xb6 /* Port E Output Enable */
+
#endif
/***************************************************************************
@@ -136,7 +155,7 @@
----------------------------------------------------------------------------
| 04 | 0x00
----------------------------------------------------------------------------
-| 05 | 0x01
+| 05 | data length
----------------------------------------------------------------------------
| 06-59 | don't care
----------------------------------------------------------------------------
diff --git a/drivers/media/dvb/dvb-usb/au6610.c b/drivers/media/dvb/dvb-usb/au6610.c
index eb34cc3..2351077 100644
--- a/drivers/media/dvb/dvb-usb/au6610.c
+++ b/drivers/media/dvb/dvb-usb/au6610.c
@@ -33,8 +33,16 @@
{
int ret;
u16 index;
- u8 usb_buf[6]; /* enough for all known requests,
- read returns 5 and write 6 bytes */
+ u8 *usb_buf;
+
+ /*
+ * allocate enough for all known requests,
+ * read returns 5 and write 6 bytes
+ */
+ usb_buf = kmalloc(6, GFP_KERNEL);
+ if (!usb_buf)
+ return -ENOMEM;
+
switch (wlen) {
case 1:
index = wbuf[0] << 8;
@@ -45,14 +53,15 @@
break;
default:
warn("wlen = %x, aborting.", wlen);
- return -EINVAL;
+ ret = -EINVAL;
+ goto error;
}
ret = usb_control_msg(d->udev, usb_rcvctrlpipe(d->udev, 0), operation,
USB_TYPE_VENDOR|USB_DIR_IN, addr << 1, index,
- usb_buf, sizeof(usb_buf), AU6610_USB_TIMEOUT);
+ usb_buf, 6, AU6610_USB_TIMEOUT);
if (ret < 0)
- return ret;
+ goto error;
switch (operation) {
case AU6610_REQ_I2C_READ:
@@ -60,7 +69,8 @@
/* requested value is always 5th byte in buffer */
rbuf[0] = usb_buf[4];
}
-
+error:
+ kfree(usb_buf);
return ret;
}
diff --git a/drivers/media/dvb/dvb-usb/ce6230.c b/drivers/media/dvb/dvb-usb/ce6230.c
index 3df2045..6d1a304 100644
--- a/drivers/media/dvb/dvb-usb/ce6230.c
+++ b/drivers/media/dvb/dvb-usb/ce6230.c
@@ -39,7 +39,7 @@
u8 requesttype;
u16 value;
u16 index;
- u8 buf[req->data_len];
+ u8 *buf;
request = req->cmd;
value = req->value;
@@ -62,6 +62,12 @@
goto error;
}
+ buf = kmalloc(req->data_len, GFP_KERNEL);
+ if (!buf) {
+ ret = -ENOMEM;
+ goto error;
+ }
+
if (requesttype == (USB_TYPE_VENDOR | USB_DIR_OUT)) {
/* write */
memcpy(buf, req->data, req->data_len);
@@ -74,7 +80,7 @@
msleep(1); /* avoid I2C errors */
ret = usb_control_msg(udev, pipe, request, requesttype, value, index,
- buf, sizeof(buf), CE6230_USB_TIMEOUT);
+ buf, req->data_len, CE6230_USB_TIMEOUT);
ce6230_debug_dump(request, requesttype, value, index, buf,
req->data_len, deb_xfer);
@@ -88,6 +94,7 @@
if (!ret && requesttype == (USB_TYPE_VENDOR | USB_DIR_IN))
memcpy(req->data, buf, req->data_len);
+ kfree(buf);
error:
return ret;
}
diff --git a/drivers/media/dvb/dvb-usb/dib0700.h b/drivers/media/dvb/dvb-usb/dib0700.h
index b2a87f2..9bd6d51 100644
--- a/drivers/media/dvb/dvb-usb/dib0700.h
+++ b/drivers/media/dvb/dvb-usb/dib0700.h
@@ -46,8 +46,9 @@
u8 is_dib7000pc;
u8 fw_use_new_i2c_api;
u8 disable_streaming_master_mode;
- u32 fw_version;
- u32 nb_packet_buffer_size;
+ u32 fw_version;
+ u32 nb_packet_buffer_size;
+ u8 buf[255];
};
extern int dib0700_get_version(struct dvb_usb_device *d, u32 *hwversion,
diff --git a/drivers/media/dvb/dvb-usb/dib0700_core.c b/drivers/media/dvb/dvb-usb/dib0700_core.c
index b79af68..5eb91b4 100644
--- a/drivers/media/dvb/dvb-usb/dib0700_core.c
+++ b/drivers/media/dvb/dvb-usb/dib0700_core.c
@@ -27,19 +27,25 @@
int dib0700_get_version(struct dvb_usb_device *d, u32 *hwversion,
u32 *romversion, u32 *ramversion, u32 *fwtype)
{
- u8 b[16];
- int ret = usb_control_msg(d->udev, usb_rcvctrlpipe(d->udev, 0),
+ struct dib0700_state *st = d->priv;
+ int ret;
+
+ ret = usb_control_msg(d->udev, usb_rcvctrlpipe(d->udev, 0),
REQUEST_GET_VERSION,
USB_TYPE_VENDOR | USB_DIR_IN, 0, 0,
- b, sizeof(b), USB_CTRL_GET_TIMEOUT);
+ st->buf, 16, USB_CTRL_GET_TIMEOUT);
if (hwversion != NULL)
- *hwversion = (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | b[3];
+ *hwversion = (st->buf[0] << 24) | (st->buf[1] << 16) |
+ (st->buf[2] << 8) | st->buf[3];
if (romversion != NULL)
- *romversion = (b[4] << 24) | (b[5] << 16) | (b[6] << 8) | b[7];
+ *romversion = (st->buf[4] << 24) | (st->buf[5] << 16) |
+ (st->buf[6] << 8) | st->buf[7];
if (ramversion != NULL)
- *ramversion = (b[8] << 24) | (b[9] << 16) | (b[10] << 8) | b[11];
+ *ramversion = (st->buf[8] << 24) | (st->buf[9] << 16) |
+ (st->buf[10] << 8) | st->buf[11];
if (fwtype != NULL)
- *fwtype = (b[12] << 24) | (b[13] << 16) | (b[14] << 8) | b[15];
+ *fwtype = (st->buf[12] << 24) | (st->buf[13] << 16) |
+ (st->buf[14] << 8) | st->buf[15];
return ret;
}
@@ -101,24 +107,31 @@
int dib0700_set_gpio(struct dvb_usb_device *d, enum dib07x0_gpios gpio, u8 gpio_dir, u8 gpio_val)
{
- u8 buf[3] = { REQUEST_SET_GPIO, gpio, ((gpio_dir & 0x01) << 7) | ((gpio_val & 0x01) << 6) };
- return dib0700_ctrl_wr(d, buf, sizeof(buf));
+ struct dib0700_state *st = d->priv;
+ s16 ret;
+
+ st->buf[0] = REQUEST_SET_GPIO;
+ st->buf[1] = gpio;
+ st->buf[2] = ((gpio_dir & 0x01) << 7) | ((gpio_val & 0x01) << 6);
+
+ ret = dib0700_ctrl_wr(d, st->buf, 3);
+
+ return ret;
}
static int dib0700_set_usb_xfer_len(struct dvb_usb_device *d, u16 nb_ts_packets)
{
struct dib0700_state *st = d->priv;
- u8 b[3];
int ret;
if (st->fw_version >= 0x10201) {
- b[0] = REQUEST_SET_USB_XFER_LEN;
- b[1] = (nb_ts_packets >> 8) & 0xff;
- b[2] = nb_ts_packets & 0xff;
+ st->buf[0] = REQUEST_SET_USB_XFER_LEN;
+ st->buf[1] = (nb_ts_packets >> 8) & 0xff;
+ st->buf[2] = nb_ts_packets & 0xff;
deb_info("set the USB xfer len to %i Ts packet\n", nb_ts_packets);
- ret = dib0700_ctrl_wr(d, b, sizeof(b));
+ ret = dib0700_ctrl_wr(d, st->buf, 3);
} else {
deb_info("this firmware does not allow to change the USB xfer len\n");
ret = -EIO;
@@ -137,11 +150,11 @@
properly support i2c read calls not preceded by a write */
struct dvb_usb_device *d = i2c_get_adapdata(adap);
+ struct dib0700_state *st = d->priv;
uint8_t bus_mode = 1; /* 0=eeprom bus, 1=frontend bus */
uint8_t gen_mode = 0; /* 0=master i2c, 1=gpio i2c */
uint8_t en_start = 0;
uint8_t en_stop = 0;
- uint8_t buf[255]; /* TBV: malloc ? */
int result, i;
/* Ensure nobody else hits the i2c bus while we're sending our
@@ -195,24 +208,24 @@
} else {
/* Write request */
- buf[0] = REQUEST_NEW_I2C_WRITE;
- buf[1] = msg[i].addr << 1;
- buf[2] = (en_start << 7) | (en_stop << 6) |
+ st->buf[0] = REQUEST_NEW_I2C_WRITE;
+ st->buf[1] = msg[i].addr << 1;
+ st->buf[2] = (en_start << 7) | (en_stop << 6) |
(msg[i].len & 0x3F);
/* I2C ctrl + FE bus; */
- buf[3] = ((gen_mode << 6) & 0xC0) |
+ st->buf[3] = ((gen_mode << 6) & 0xC0) |
((bus_mode << 4) & 0x30);
/* The Actual i2c payload */
- memcpy(&buf[4], msg[i].buf, msg[i].len);
+ memcpy(&st->buf[4], msg[i].buf, msg[i].len);
deb_data(">>> ");
- debug_dump(buf, msg[i].len + 4, deb_data);
+ debug_dump(st->buf, msg[i].len + 4, deb_data);
result = usb_control_msg(d->udev,
usb_sndctrlpipe(d->udev, 0),
REQUEST_NEW_I2C_WRITE,
USB_TYPE_VENDOR | USB_DIR_OUT,
- 0, 0, buf, msg[i].len + 4,
+ 0, 0, st->buf, msg[i].len + 4,
USB_CTRL_GET_TIMEOUT);
if (result < 0) {
deb_info("i2c write error (status = %d)\n", result);
@@ -231,27 +244,29 @@
struct i2c_msg *msg, int num)
{
struct dvb_usb_device *d = i2c_get_adapdata(adap);
+ struct dib0700_state *st = d->priv;
int i,len;
- u8 buf[255];
if (mutex_lock_interruptible(&d->i2c_mutex) < 0)
return -EAGAIN;
for (i = 0; i < num; i++) {
/* fill in the address */
- buf[1] = msg[i].addr << 1;
+ st->buf[1] = msg[i].addr << 1;
/* fill the buffer */
- memcpy(&buf[2], msg[i].buf, msg[i].len);
+ memcpy(&st->buf[2], msg[i].buf, msg[i].len);
/* write/read request */
if (i+1 < num && (msg[i+1].flags & I2C_M_RD)) {
- buf[0] = REQUEST_I2C_READ;
- buf[1] |= 1;
+ st->buf[0] = REQUEST_I2C_READ;
+ st->buf[1] |= 1;
/* special thing in the current firmware: when length is zero the read-failed */
- if ((len = dib0700_ctrl_rd(d, buf, msg[i].len + 2, msg[i+1].buf, msg[i+1].len)) <= 0) {
+ len = dib0700_ctrl_rd(d, st->buf, msg[i].len + 2,
+ msg[i+1].buf, msg[i+1].len);
+ if (len <= 0) {
deb_info("I2C read failed on address 0x%02x\n",
- msg[i].addr);
+ msg[i].addr);
break;
}
@@ -259,13 +274,13 @@
i++;
} else {
- buf[0] = REQUEST_I2C_WRITE;
- if (dib0700_ctrl_wr(d, buf, msg[i].len + 2) < 0)
+ st->buf[0] = REQUEST_I2C_WRITE;
+ if (dib0700_ctrl_wr(d, st->buf, msg[i].len + 2) < 0)
break;
}
}
-
mutex_unlock(&d->i2c_mutex);
+
return i;
}
@@ -297,15 +312,23 @@
int dib0700_identify_state(struct usb_device *udev, struct dvb_usb_device_properties *props,
struct dvb_usb_device_description **desc, int *cold)
{
- u8 b[16];
- s16 ret = usb_control_msg(udev, usb_rcvctrlpipe(udev,0),
+ s16 ret;
+ u8 *b;
+
+ b = kmalloc(16, GFP_KERNEL);
+ if (!b)
+ return -ENOMEM;
+
+
+ ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
REQUEST_GET_VERSION, USB_TYPE_VENDOR | USB_DIR_IN, 0, 0, b, 16, USB_CTRL_GET_TIMEOUT);
deb_info("FW GET_VERSION length: %d\n",ret);
*cold = ret <= 0;
-
deb_info("cold: %d\n", *cold);
+
+ kfree(b);
return 0;
}
@@ -313,43 +336,50 @@
u8 pll_src, u8 pll_range, u8 clock_gpio3, u16 pll_prediv,
u16 pll_loopdiv, u16 free_div, u16 dsuScaler)
{
- u8 b[10];
- b[0] = REQUEST_SET_CLOCK;
- b[1] = (en_pll << 7) | (pll_src << 6) | (pll_range << 5) | (clock_gpio3 << 4);
- b[2] = (pll_prediv >> 8) & 0xff; // MSB
- b[3] = pll_prediv & 0xff; // LSB
- b[4] = (pll_loopdiv >> 8) & 0xff; // MSB
- b[5] = pll_loopdiv & 0xff; // LSB
- b[6] = (free_div >> 8) & 0xff; // MSB
- b[7] = free_div & 0xff; // LSB
- b[8] = (dsuScaler >> 8) & 0xff; // MSB
- b[9] = dsuScaler & 0xff; // LSB
+ struct dib0700_state *st = d->priv;
+ s16 ret;
- return dib0700_ctrl_wr(d, b, 10);
+ st->buf[0] = REQUEST_SET_CLOCK;
+ st->buf[1] = (en_pll << 7) | (pll_src << 6) |
+ (pll_range << 5) | (clock_gpio3 << 4);
+ st->buf[2] = (pll_prediv >> 8) & 0xff; /* MSB */
+ st->buf[3] = pll_prediv & 0xff; /* LSB */
+ st->buf[4] = (pll_loopdiv >> 8) & 0xff; /* MSB */
+ st->buf[5] = pll_loopdiv & 0xff; /* LSB */
+ st->buf[6] = (free_div >> 8) & 0xff; /* MSB */
+ st->buf[7] = free_div & 0xff; /* LSB */
+ st->buf[8] = (dsuScaler >> 8) & 0xff; /* MSB */
+ st->buf[9] = dsuScaler & 0xff; /* LSB */
+
+ ret = dib0700_ctrl_wr(d, st->buf, 10);
+
+ return ret;
}
int dib0700_set_i2c_speed(struct dvb_usb_device *d, u16 scl_kHz)
{
+ struct dib0700_state *st = d->priv;
u16 divider;
- u8 b[8];
if (scl_kHz == 0)
return -EINVAL;
- b[0] = REQUEST_SET_I2C_PARAM;
+ st->buf[0] = REQUEST_SET_I2C_PARAM;
divider = (u16) (30000 / scl_kHz);
- b[2] = (u8) (divider >> 8);
- b[3] = (u8) (divider & 0xff);
+ st->buf[1] = 0;
+ st->buf[2] = (u8) (divider >> 8);
+ st->buf[3] = (u8) (divider & 0xff);
divider = (u16) (72000 / scl_kHz);
- b[4] = (u8) (divider >> 8);
- b[5] = (u8) (divider & 0xff);
+ st->buf[4] = (u8) (divider >> 8);
+ st->buf[5] = (u8) (divider & 0xff);
divider = (u16) (72000 / scl_kHz); /* clock: 72MHz */
- b[6] = (u8) (divider >> 8);
- b[7] = (u8) (divider & 0xff);
+ st->buf[6] = (u8) (divider >> 8);
+ st->buf[7] = (u8) (divider & 0xff);
deb_info("setting I2C speed: %04x %04x %04x (%d kHz).",
- (b[2] << 8) | (b[3]), (b[4] << 8) | b[5], (b[6] << 8) | b[7], scl_kHz);
- return dib0700_ctrl_wr(d, b, 8);
+ (st->buf[2] << 8) | (st->buf[3]), (st->buf[4] << 8) |
+ st->buf[5], (st->buf[6] << 8) | st->buf[7], scl_kHz);
+ return dib0700_ctrl_wr(d, st->buf, 8);
}
@@ -364,32 +394,45 @@
static int dib0700_jumpram(struct usb_device *udev, u32 address)
{
- int ret, actlen;
- u8 buf[8] = { REQUEST_JUMPRAM, 0, 0, 0,
- (address >> 24) & 0xff,
- (address >> 16) & 0xff,
- (address >> 8) & 0xff,
- address & 0xff };
+ int ret = 0, actlen;
+ u8 *buf;
+
+ buf = kmalloc(8, GFP_KERNEL);
+ if (!buf)
+ return -ENOMEM;
+ buf[0] = REQUEST_JUMPRAM;
+ buf[1] = 0;
+ buf[2] = 0;
+ buf[3] = 0;
+ buf[4] = (address >> 24) & 0xff;
+ buf[5] = (address >> 16) & 0xff;
+ buf[6] = (address >> 8) & 0xff;
+ buf[7] = address & 0xff;
if ((ret = usb_bulk_msg(udev, usb_sndbulkpipe(udev, 0x01),buf,8,&actlen,1000)) < 0) {
deb_fw("jumpram to 0x%x failed\n",address);
- return ret;
+ goto out;
}
if (actlen != 8) {
deb_fw("jumpram to 0x%x failed\n",address);
- return -EIO;
+ ret = -EIO;
+ goto out;
}
- return 0;
+out:
+ kfree(buf);
+ return ret;
}
int dib0700_download_firmware(struct usb_device *udev, const struct firmware *fw)
{
struct hexline hx;
int pos = 0, ret, act_len, i, adap_num;
- u8 b[16];
+ u8 *buf;
u32 fw_version;
- u8 buf[260];
+ buf = kmalloc(260, GFP_KERNEL);
+ if (!buf)
+ return -ENOMEM;
while ((ret = dvb_usb_get_hexline(fw, &hx, &pos)) > 0) {
deb_fwdata("writing to address 0x%08x (buffer: 0x%02x %02x)\n",
@@ -411,7 +454,7 @@
if (ret < 0) {
err("firmware download failed at %d with %d",pos,ret);
- return ret;
+ goto out;
}
}
@@ -432,8 +475,8 @@
usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
REQUEST_GET_VERSION,
USB_TYPE_VENDOR | USB_DIR_IN, 0, 0,
- b, sizeof(b), USB_CTRL_GET_TIMEOUT);
- fw_version = (b[8] << 24) | (b[9] << 16) | (b[10] << 8) | b[11];
+ buf, 16, USB_CTRL_GET_TIMEOUT);
+ fw_version = (buf[8] << 24) | (buf[9] << 16) | (buf[10] << 8) | buf[11];
/* set the buffer size - DVB-USB is allocating URB buffers
* only after the firwmare download was successful */
@@ -451,14 +494,14 @@
}
}
}
-
+out:
+ kfree(buf);
return ret;
}
int dib0700_streaming_ctrl(struct dvb_usb_adapter *adap, int onoff)
{
struct dib0700_state *st = adap->dev->priv;
- u8 b[4];
int ret;
if ((onoff != 0) && (st->fw_version >= 0x10201)) {
@@ -472,15 +515,17 @@
}
}
- b[0] = REQUEST_ENABLE_VIDEO;
- b[1] = (onoff << 4) | 0x00; /* this bit gives a kind of command, rather than enabling something or not */
+ st->buf[0] = REQUEST_ENABLE_VIDEO;
+ /* this bit gives a kind of command,
+ * rather than enabling something or not */
+ st->buf[1] = (onoff << 4) | 0x00;
if (st->disable_streaming_master_mode == 1)
- b[2] = 0x00;
+ st->buf[2] = 0x00;
else
- b[2] = 0x01 << 4; /* Master mode */
+ st->buf[2] = 0x01 << 4; /* Master mode */
- b[3] = 0x00;
+ st->buf[3] = 0x00;
deb_info("modifying (%d) streaming state for %d\n", onoff, adap->id);
@@ -499,20 +544,23 @@
st->channel_state |= 1 << (3-adap->stream.props.endpoint);
}
- b[2] |= st->channel_state;
+ st->buf[2] |= st->channel_state;
- deb_info("data for streaming: %x %x\n", b[1], b[2]);
+ deb_info("data for streaming: %x %x\n", st->buf[1], st->buf[2]);
- return dib0700_ctrl_wr(adap->dev, b, 4);
+ return dib0700_ctrl_wr(adap->dev, st->buf, 4);
}
int dib0700_change_protocol(struct rc_dev *rc, u64 rc_type)
{
struct dvb_usb_device *d = rc->priv;
struct dib0700_state *st = d->priv;
- u8 rc_setup[3] = { REQUEST_SET_RC, 0, 0 };
int new_proto, ret;
+ st->buf[0] = REQUEST_SET_RC;
+ st->buf[1] = 0;
+ st->buf[2] = 0;
+
/* Set the IR mode */
if (rc_type == RC_TYPE_RC5)
new_proto = 1;
@@ -526,9 +574,9 @@
} else
return -EINVAL;
- rc_setup[1] = new_proto;
+ st->buf[1] = new_proto;
- ret = dib0700_ctrl_wr(d, rc_setup, sizeof(rc_setup));
+ ret = dib0700_ctrl_wr(d, st->buf, 3);
if (ret < 0) {
err("ir protocol setup failed");
return ret;
@@ -561,7 +609,6 @@
static void dib0700_rc_urb_completion(struct urb *purb)
{
struct dvb_usb_device *d = purb->context;
- struct dib0700_state *st;
struct dib0700_rc_response *poll_reply;
u32 uninitialized_var(keycode);
u8 toggle;
@@ -576,7 +623,6 @@
return;
}
- st = d->priv;
poll_reply = purb->transfer_buffer;
if (purb->status < 0) {
diff --git a/drivers/media/dvb/dvb-usb/dib0700_devices.c b/drivers/media/dvb/dvb-usb/dib0700_devices.c
index 65214af..c519ad5 100644
--- a/drivers/media/dvb/dvb-usb/dib0700_devices.c
+++ b/drivers/media/dvb/dvb-usb/dib0700_devices.c
@@ -2439,7 +2439,6 @@
dib0700_set_i2c_speed(adap->dev, 340);
adap->fe = dvb_attach(dib7000p_attach, &adap->dev->i2c_adap, 0x90, &tfe7090pvr_dib7000p_config[0]);
-
if (adap->fe == NULL)
return -ENODEV;
@@ -2802,6 +2801,7 @@
{ USB_DEVICE(USB_VID_DIBCOM, USB_PID_DIBCOM_NIM7090) },
{ USB_DEVICE(USB_VID_DIBCOM, USB_PID_DIBCOM_TFE7090PVR) },
{ USB_DEVICE(USB_VID_TECHNISAT, USB_PID_TECHNISAT_AIRSTAR_TELESTICK_2) },
+/* 75 */{ USB_DEVICE(USB_VID_MEDION, USB_PID_CREATIX_CTX1921) },
{ 0 } /* Terminating entry */
};
MODULE_DEVICE_TABLE(usb, dib0700_usb_id_table);
@@ -3411,7 +3411,7 @@
},
},
- .num_device_descs = 3,
+ .num_device_descs = 4,
.devices = {
{ "DiBcom STK7770P reference design",
{ &dib0700_usb_id_table[59], NULL },
@@ -3427,6 +3427,10 @@
{ &dib0700_usb_id_table[74], NULL },
{ NULL },
},
+ { "Medion CTX1921 DVB-T USB",
+ { &dib0700_usb_id_table[75], NULL },
+ { NULL },
+ },
},
.rc.core = {
diff --git a/drivers/media/dvb/dvb-usb/dibusb-common.c b/drivers/media/dvb/dvb-usb/dibusb-common.c
index 956f7ae..4c2a689 100644
--- a/drivers/media/dvb/dvb-usb/dibusb-common.c
+++ b/drivers/media/dvb/dvb-usb/dibusb-common.c
@@ -408,7 +408,7 @@
{ 0x8008, KEY_DVD },
{ 0x8009, KEY_AUDIO },
- { 0x800a, KEY_MEDIA }, /* Pictures */
+ { 0x800a, KEY_IMAGES }, /* Pictures */
{ 0x800b, KEY_VIDEO },
{ 0x800c, KEY_BACK },
diff --git a/drivers/media/dvb/dvb-usb/dvb-usb-dvb.c b/drivers/media/dvb/dvb-usb/dvb-usb-dvb.c
index df1ec3e..b3cb626 100644
--- a/drivers/media/dvb/dvb-usb/dvb-usb-dvb.c
+++ b/drivers/media/dvb/dvb-usb/dvb-usb-dvb.c
@@ -12,7 +12,7 @@
static int dvb_usb_ctrl_feed(struct dvb_demux_feed *dvbdmxfeed, int onoff)
{
struct dvb_usb_adapter *adap = dvbdmxfeed->demux->priv;
- int newfeedcount,ret;
+ int newfeedcount, ret;
if (adap == NULL)
return -ENODEV;
@@ -24,9 +24,13 @@
deb_ts("stop feeding\n");
usb_urb_kill(&adap->stream);
- if (adap->props.streaming_ctrl != NULL)
- if ((ret = adap->props.streaming_ctrl(adap,0)))
+ if (adap->props.streaming_ctrl != NULL) {
+ ret = adap->props.streaming_ctrl(adap, 0);
+ if (ret < 0) {
err("error while stopping stream.");
+ return ret;
+ }
+ }
}
adap->feedcount = newfeedcount;
@@ -49,17 +53,24 @@
deb_ts("controlling pid parser\n");
if (adap->props.caps & DVB_USB_ADAP_HAS_PID_FILTER &&
- adap->props.caps & DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF &&
- adap->props.pid_filter_ctrl != NULL)
- if (adap->props.pid_filter_ctrl(adap,adap->pid_filtering) < 0)
+ adap->props.caps &
+ DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF &&
+ adap->props.pid_filter_ctrl != NULL) {
+ ret = adap->props.pid_filter_ctrl(adap,
+ adap->pid_filtering);
+ if (ret < 0) {
err("could not handle pid_parser");
-
- deb_ts("start feeding\n");
- if (adap->props.streaming_ctrl != NULL)
- if (adap->props.streaming_ctrl(adap,1)) {
- err("error while enabling fifo.");
- return -ENODEV;
+ return ret;
}
+ }
+ deb_ts("start feeding\n");
+ if (adap->props.streaming_ctrl != NULL) {
+ ret = adap->props.streaming_ctrl(adap, 1);
+ if (ret < 0) {
+ err("error while enabling fifo.");
+ return ret;
+ }
+ }
}
return 0;
diff --git a/drivers/media/dvb/dvb-usb/dvb-usb-ids.h b/drivers/media/dvb/dvb-usb/dvb-usb-ids.h
index 3a8b744..21b1549 100644
--- a/drivers/media/dvb/dvb-usb/dvb-usb-ids.h
+++ b/drivers/media/dvb/dvb-usb/dvb-usb-ids.h
@@ -91,6 +91,7 @@
#define USB_PID_COMPRO_VIDEOMATE_U500_PC 0x1e80
#define USB_PID_CONCEPTRONIC_CTVDIGRCU 0xe397
#define USB_PID_CONEXANT_D680_DMB 0x86d6
+#define USB_PID_CREATIX_CTX1921 0x1921
#define USB_PID_DIBCOM_HOOK_DEFAULT 0x0064
#define USB_PID_DIBCOM_HOOK_DEFAULT_REENUM 0x0065
#define USB_PID_DIBCOM_MOD3000_COLD 0x0bb8
diff --git a/drivers/media/dvb/dvb-usb/dw2102.c b/drivers/media/dvb/dvb-usb/dw2102.c
index d312323..058b231 100644
--- a/drivers/media/dvb/dvb-usb/dw2102.c
+++ b/drivers/media/dvb/dvb-usb/dw2102.c
@@ -121,12 +121,16 @@
u16 index, u8 * data, u16 len, int flags)
{
int ret;
- u8 u8buf[len];
-
+ u8 *u8buf;
unsigned int pipe = (flags == DW210X_READ_MSG) ?
usb_rcvctrlpipe(dev, 0) : usb_sndctrlpipe(dev, 0);
u8 request_type = (flags == DW210X_READ_MSG) ? USB_DIR_IN : USB_DIR_OUT;
+ u8buf = kmalloc(len, GFP_KERNEL);
+ if (!u8buf)
+ return -ENOMEM;
+
+
if (flags == DW210X_WRITE_MSG)
memcpy(u8buf, data, len);
ret = usb_control_msg(dev, pipe, request, request_type | USB_TYPE_VENDOR,
@@ -134,6 +138,8 @@
if (flags == DW210X_READ_MSG)
memcpy(data, u8buf, len);
+
+ kfree(u8buf);
return ret;
}
diff --git a/drivers/media/dvb/dvb-usb/ec168.c b/drivers/media/dvb/dvb-usb/ec168.c
index 52f5d4f..1ba3e5d 100644
--- a/drivers/media/dvb/dvb-usb/ec168.c
+++ b/drivers/media/dvb/dvb-usb/ec168.c
@@ -36,7 +36,9 @@
int ret;
unsigned int pipe;
u8 request, requesttype;
- u8 buf[req->size];
+ u8 *buf;
+
+
switch (req->cmd) {
case DOWNLOAD_FIRMWARE:
@@ -72,6 +74,12 @@
goto error;
}
+ buf = kmalloc(req->size, GFP_KERNEL);
+ if (!buf) {
+ ret = -ENOMEM;
+ goto error;
+ }
+
if (requesttype == (USB_TYPE_VENDOR | USB_DIR_OUT)) {
/* write */
memcpy(buf, req->data, req->size);
@@ -84,13 +92,13 @@
msleep(1); /* avoid I2C errors */
ret = usb_control_msg(udev, pipe, request, requesttype, req->value,
- req->index, buf, sizeof(buf), EC168_USB_TIMEOUT);
+ req->index, buf, req->size, EC168_USB_TIMEOUT);
ec168_debug_dump(request, requesttype, req->value, req->index, buf,
req->size, deb_xfer);
if (ret < 0)
- goto error;
+ goto err_dealloc;
else
ret = 0;
@@ -98,7 +106,11 @@
if (!ret && requesttype == (USB_TYPE_VENDOR | USB_DIR_IN))
memcpy(req->data, buf, req->size);
+ kfree(buf);
return ret;
+
+err_dealloc:
+ kfree(buf);
error:
deb_info("%s: failed:%d\n", __func__, ret);
return ret;
diff --git a/drivers/media/dvb/dvb-usb/friio.c b/drivers/media/dvb/dvb-usb/friio.c
index 14a65b4..76159ae 100644
--- a/drivers/media/dvb/dvb-usb/friio.c
+++ b/drivers/media/dvb/dvb-usb/friio.c
@@ -142,17 +142,20 @@
return I2C_FUNC_I2C;
}
-
static int friio_ext_ctl(struct dvb_usb_adapter *adap,
u32 sat_color, int lnb_on)
{
int i;
int ret;
struct i2c_msg msg;
- u8 buf[2];
+ u8 *buf;
u32 mask;
u8 lnb = (lnb_on) ? FRIIO_CTL_LNB : 0;
+ buf = kmalloc(2, GFP_KERNEL);
+ if (!buf)
+ return -ENOMEM;
+
msg.addr = 0x00;
msg.flags = 0;
msg.len = 2;
@@ -189,6 +192,7 @@
buf[1] |= FRIIO_CTL_CLK;
ret += gl861_i2c_xfer(&adap->dev->i2c_adap, &msg, 1);
+ kfree(buf);
return (ret == 70);
}
@@ -219,11 +223,20 @@
int ret;
int i;
int retry = 0;
- u8 rbuf[2];
- u8 wbuf[3];
+ u8 *rbuf, *wbuf;
deb_info("%s called.\n", __func__);
+ wbuf = kmalloc(3, GFP_KERNEL);
+ if (!wbuf)
+ return -ENOMEM;
+
+ rbuf = kmalloc(2, GFP_KERNEL);
+ if (!rbuf) {
+ kfree(wbuf);
+ return -ENOMEM;
+ }
+
/* use gl861_i2c_msg instead of gl861_i2c_xfer(), */
/* because the i2c device is not set up yet. */
wbuf[0] = 0x11;
@@ -358,6 +371,8 @@
return 0;
error:
+ kfree(wbuf);
+ kfree(rbuf);
deb_info("%s:ret == %d\n", __func__, ret);
return -EIO;
}
diff --git a/drivers/media/dvb/dvb-usb/lmedm04.c b/drivers/media/dvb/dvb-usb/lmedm04.c
index f2db012..f36f471 100644
--- a/drivers/media/dvb/dvb-usb/lmedm04.c
+++ b/drivers/media/dvb/dvb-usb/lmedm04.c
@@ -62,8 +62,6 @@
* LME2510: SHARP:BS2F7HZ0194(MV0194) cannot cold reset and share system
* with other tuners. After a cold reset streaming will not start.
*
- * PID functions have been removed from this driver version due to
- * problems with different firmware and application versions.
*/
#define DVB_USB_LOG_PREFIX "LME2510(C)"
#include <linux/usb.h>
@@ -104,6 +102,10 @@
module_param_named(firmware, dvb_usb_lme2510_firmware, int, 0644);
MODULE_PARM_DESC(firmware, "set default firmware 0=Sharp7395 1=LG");
+static int pid_filter;
+module_param_named(pid, pid_filter, int, 0644);
+MODULE_PARM_DESC(pid, "set default 0=on 1=off");
+
DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
@@ -125,6 +127,7 @@
u8 i2c_tuner_gate_r;
u8 i2c_tuner_addr;
u8 stream_on;
+ u8 pid_size;
void *buffer;
struct urb *lme_urb;
void *usb_buffer;
@@ -167,14 +170,14 @@
}
buff = st->usb_buffer;
- /* the read/write capped at 512 */
- memcpy(buff, wbuf, (wlen > 512) ? 512 : wlen);
-
ret = mutex_lock_interruptible(&d->usb_mutex);
if (ret < 0)
return -EAGAIN;
+ /* the read/write capped at 512 */
+ memcpy(buff, wbuf, (wlen > 512) ? 512 : wlen);
+
ret |= usb_clear_halt(d->udev, usb_sndbulkpipe(d->udev, 0x01));
ret |= lme2510_bulk_write(d->udev, buff, wlen , 0x01);
@@ -216,6 +219,37 @@
return 0;
}
+static int lme2510_enable_pid(struct dvb_usb_device *d, u8 index, u16 pid_out)
+{
+ struct lme2510_state *st = d->priv;
+ static u8 pid_buff[] = LME_ZERO_PID;
+ static u8 rbuf[1];
+ u8 pid_no = index * 2;
+ u8 pid_len = pid_no + 2;
+ int ret = 0;
+ deb_info(1, "PID Setting Pid %04x", pid_out);
+
+ if (st->pid_size == 0)
+ ret |= lme2510_stream_restart(d);
+
+ pid_buff[2] = pid_no;
+ pid_buff[3] = (u8)pid_out & 0xff;
+ pid_buff[4] = pid_no + 1;
+ pid_buff[5] = (u8)(pid_out >> 8);
+
+ if (pid_len > st->pid_size)
+ st->pid_size = pid_len;
+ pid_buff[7] = 0x80 + st->pid_size;
+
+ ret |= lme2510_usb_talk(d, pid_buff ,
+ sizeof(pid_buff) , rbuf, sizeof(rbuf));
+
+ if (st->stream_on)
+ ret |= lme2510_stream_restart(d);
+
+ return ret;
+}
+
static void lme2510_int_response(struct urb *lme_urb)
{
struct dvb_usb_adapter *adap = lme_urb->context;
@@ -326,16 +360,68 @@
return 0;
}
+static int lme2510_pid_filter_ctrl(struct dvb_usb_adapter *adap, int onoff)
+{
+ struct lme2510_state *st = adap->dev->priv;
+ static u8 clear_pid_reg[] = LME_CLEAR_PID;
+ static u8 rbuf[1];
+ int ret;
+
+ deb_info(1, "PID Clearing Filter");
+
+ ret = mutex_lock_interruptible(&adap->dev->i2c_mutex);
+ if (ret < 0)
+ return -EAGAIN;
+
+ if (!onoff)
+ ret |= lme2510_usb_talk(adap->dev, clear_pid_reg,
+ sizeof(clear_pid_reg), rbuf, sizeof(rbuf));
+
+ st->pid_size = 0;
+
+ mutex_unlock(&adap->dev->i2c_mutex);
+
+ return 0;
+}
+
+static int lme2510_pid_filter(struct dvb_usb_adapter *adap, int index, u16 pid,
+ int onoff)
+{
+ int ret = 0;
+
+ deb_info(3, "%s PID=%04x Index=%04x onoff=%02x", __func__,
+ pid, index, onoff);
+
+ if (onoff)
+ if (!pid_filter) {
+ ret = mutex_lock_interruptible(&adap->dev->i2c_mutex);
+ if (ret < 0)
+ return -EAGAIN;
+ ret |= lme2510_enable_pid(adap->dev, index, pid);
+ mutex_unlock(&adap->dev->i2c_mutex);
+ }
+
+
+ return ret;
+}
+
+
static int lme2510_return_status(struct usb_device *dev)
{
int ret = 0;
- u8 data[10] = {0};
+ u8 *data;
+
+ data = kzalloc(10, GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
ret |= usb_control_msg(dev, usb_rcvctrlpipe(dev, 0),
0x06, 0x80, 0x0302, 0x00, data, 0x0006, 200);
info("Firmware Status: %x (%x)", ret , data[2]);
- return (ret < 0) ? -ENODEV : data[2];
+ ret = (ret < 0) ? -ENODEV : data[2];
+ kfree(data);
+ return ret;
}
static int lme2510_msg(struct dvb_usb_device *d,
@@ -591,9 +677,10 @@
else {
deb_info(1, "STM Steam Off");
/* mutex is here only to avoid collision with I2C */
- ret = mutex_lock_interruptible(&adap->dev->i2c_mutex);
+ if (mutex_lock_interruptible(&adap->dev->i2c_mutex) < 0)
+ return -EAGAIN;
- ret |= lme2510_usb_talk(adap->dev, clear_reg_3,
+ ret = lme2510_usb_talk(adap->dev, clear_reg_3,
sizeof(clear_reg_3), rbuf, rlen);
st->stream_on = 0;
st->i2c_talk_onoff = 1;
@@ -655,7 +742,7 @@
const struct firmware *fw)
{
int ret = 0;
- u8 data[512] = {0};
+ u8 *data;
u16 j, wlen, len_in, start, end;
u8 packet_size, dlen, i;
u8 *fw_data;
@@ -663,6 +750,11 @@
packet_size = 0x31;
len_in = 1;
+ data = kzalloc(512, GFP_KERNEL);
+ if (!data) {
+ info("FRM Could not start Firmware Download (Buffer allocation failed)");
+ return -ENOMEM;
+ }
info("FRM Starting Firmware Download");
@@ -678,15 +770,15 @@
data[0] = i | 0x80;
dlen = (u8)(end - j)-1;
}
- data[1] = dlen;
- memcpy(&data[2], fw_data, dlen+1);
- wlen = (u8) dlen + 4;
- data[wlen-1] = check_sum(fw_data, dlen+1);
- deb_info(1, "Data S=%02x:E=%02x CS= %02x", data[3],
+ data[1] = dlen;
+ memcpy(&data[2], fw_data, dlen+1);
+ wlen = (u8) dlen + 4;
+ data[wlen-1] = check_sum(fw_data, dlen+1);
+ deb_info(1, "Data S=%02x:E=%02x CS= %02x", data[3],
data[dlen+2], data[dlen+3]);
- ret |= lme2510_bulk_write(dev, data, wlen, 1);
- ret |= lme2510_bulk_read(dev, data, len_in , 1);
- ret |= (data[0] == 0x88) ? 0 : -1;
+ ret |= lme2510_bulk_write(dev, data, wlen, 1);
+ ret |= lme2510_bulk_read(dev, data, len_in , 1);
+ ret |= (data[0] == 0x88) ? 0 : -1;
}
}
@@ -706,7 +798,7 @@
else
info("FRM Firmware Download Completed - Resetting Device");
-
+ kfree(data);
return (ret < 0) ? -ENODEV : 0;
}
@@ -747,7 +839,7 @@
fw_lme = fw_s0194;
ret = request_firmware(&fw, fw_lme, &udev->dev);
if (ret == 0) {
- cold = 0;/*lme2510-s0194 cannot cold reset*/
+ cold = 0;
break;
}
dvb_usb_lme2510_firmware = TUNER_LG;
@@ -769,8 +861,10 @@
case TUNER_S7395:
fw_lme = fw_c_s7395;
ret = request_firmware(&fw, fw_lme, &udev->dev);
- if (ret == 0)
+ if (ret == 0) {
+ cold = 0;
break;
+ }
dvb_usb_lme2510_firmware = TUNER_LG;
case TUNER_LG:
fw_lme = fw_c_lg;
@@ -796,14 +890,14 @@
ret = lme2510_download_firmware(udev, fw);
}
+ release_firmware(fw);
+
if (cold) {
info("FRM Changing to %s firmware", fw_lme);
lme_coldreset(udev);
return -ENODEV;
}
- release_firmware(fw);
-
return ret;
}
@@ -1017,12 +1111,13 @@
static u8 rbuf[1];
int ret, len = 3, rlen = 1;
- ret = mutex_lock_interruptible(&d->i2c_mutex);
+ if (mutex_lock_interruptible(&d->i2c_mutex) < 0)
+ return -EAGAIN;
if (onoff)
- ret |= lme2510_usb_talk(d, lnb_on, len, rbuf, rlen);
+ ret = lme2510_usb_talk(d, lnb_on, len, rbuf, rlen);
else
- ret |= lme2510_usb_talk(d, lnb_off, len, rbuf, rlen);
+ ret = lme2510_usb_talk(d, lnb_off, len, rbuf, rlen);
st->i2c_talk_onoff = 1;
@@ -1086,7 +1181,13 @@
.num_adapters = 1,
.adapter = {
{
+ .caps = DVB_USB_ADAP_HAS_PID_FILTER|
+ DVB_USB_ADAP_NEED_PID_FILTERING|
+ DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF,
.streaming_ctrl = lme2510_streaming_ctrl,
+ .pid_filter_count = 15,
+ .pid_filter = lme2510_pid_filter,
+ .pid_filter_ctrl = lme2510_pid_filter_ctrl,
.frontend_attach = dm04_lme2510_frontend_attach,
.tuner_attach = dm04_lme2510_tuner,
/* parameter for the MPEG2-data transfer */
@@ -1122,7 +1223,13 @@
.num_adapters = 1,
.adapter = {
{
+ .caps = DVB_USB_ADAP_HAS_PID_FILTER|
+ DVB_USB_ADAP_NEED_PID_FILTERING|
+ DVB_USB_ADAP_PID_FILTER_CAN_BE_TURNED_OFF,
.streaming_ctrl = lme2510_streaming_ctrl,
+ .pid_filter_count = 15,
+ .pid_filter = lme2510_pid_filter,
+ .pid_filter_ctrl = lme2510_pid_filter_ctrl,
.frontend_attach = dm04_lme2510_frontend_attach,
.tuner_attach = dm04_lme2510_tuner,
/* parameter for the MPEG2-data transfer */
@@ -1151,7 +1258,7 @@
}
};
-void *lme2510_exit_int(struct dvb_usb_device *d)
+static void *lme2510_exit_int(struct dvb_usb_device *d)
{
struct lme2510_state *st = d->priv;
struct dvb_usb_adapter *adap = &d->adapter[0];
@@ -1178,7 +1285,7 @@
return buffer;
}
-void lme2510_exit(struct usb_interface *intf)
+static void lme2510_exit(struct usb_interface *intf)
{
struct dvb_usb_device *d = usb_get_intfdata(intf);
void *usb_buffer;
@@ -1220,5 +1327,5 @@
MODULE_AUTHOR("Malcolm Priestley <tvboxspy@gmail.com>");
MODULE_DESCRIPTION("LME2510(C) DVB-S USB2.0");
-MODULE_VERSION("1.80");
+MODULE_VERSION("1.86");
MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/dvb-usb/lmedm04.h b/drivers/media/dvb/dvb-usb/lmedm04.h
index e6af16c..ab21e2e 100644
--- a/drivers/media/dvb/dvb-usb/lmedm04.h
+++ b/drivers/media/dvb/dvb-usb/lmedm04.h
@@ -40,6 +40,7 @@
*/
#define LME_ST_ON_W {0x06, 0x00}
#define LME_CLEAR_PID {0x03, 0x02, 0x20, 0xa0}
+#define LME_ZERO_PID {0x03, 0x06, 0x00, 0x00, 0x01, 0x00, 0x20, 0x9c}
/* LNB Voltage
* 07 XX XX
@@ -108,14 +109,14 @@
0x3d, 0x30,
0x40, 0x63,
0x41, 0x04,
- 0x42, 0x60,
+ 0x42, 0x20,
0x43, 0x00,
0x44, 0x00,
0x45, 0x00,
0x46, 0x00,
0x47, 0x00,
0x4a, 0x00,
- 0x50, 0x12,
+ 0x50, 0x10,
0x51, 0x36,
0x52, 0x21,
0x53, 0x94,
diff --git a/drivers/media/dvb/dvb-usb/m920x.c b/drivers/media/dvb/dvb-usb/m920x.c
index da9dc91..9456792 100644
--- a/drivers/media/dvb/dvb-usb/m920x.c
+++ b/drivers/media/dvb/dvb-usb/m920x.c
@@ -134,13 +134,17 @@
{
struct m920x_state *m = d->priv;
int i, ret = 0;
- u8 rc_state[2];
+ u8 *rc_state;
+
+ rc_state = kmalloc(2, GFP_KERNEL);
+ if (!rc_state)
+ return -ENOMEM;
if ((ret = m920x_read(d->udev, M9206_CORE, 0x0, M9206_RC_STATE, rc_state, 1)) != 0)
- goto unlock;
+ goto out;
if ((ret = m920x_read(d->udev, M9206_CORE, 0x0, M9206_RC_KEY, rc_state + 1, 1)) != 0)
- goto unlock;
+ goto out;
for (i = 0; i < d->props.rc.legacy.rc_map_size; i++)
if (rc5_data(&d->props.rc.legacy.rc_map_table[i]) == rc_state[1]) {
@@ -149,7 +153,7 @@
switch(rc_state[0]) {
case 0x80:
*state = REMOTE_NO_KEY_PRESSED;
- goto unlock;
+ goto out;
case 0x88: /* framing error or "invalid code" */
case 0x99:
@@ -157,7 +161,7 @@
case 0xd8:
*state = REMOTE_NO_KEY_PRESSED;
m->rep_count = 0;
- goto unlock;
+ goto out;
case 0x93:
case 0x92:
@@ -165,7 +169,7 @@
case 0x82:
m->rep_count = 0;
*state = REMOTE_KEY_PRESSED;
- goto unlock;
+ goto out;
case 0x91:
case 0x81: /* pinnacle PCTV310e */
@@ -174,12 +178,12 @@
*state = REMOTE_KEY_REPEAT;
else
*state = REMOTE_NO_KEY_PRESSED;
- goto unlock;
+ goto out;
default:
deb("Unexpected rc state %02x\n", rc_state[0]);
*state = REMOTE_NO_KEY_PRESSED;
- goto unlock;
+ goto out;
}
}
@@ -188,8 +192,8 @@
*state = REMOTE_NO_KEY_PRESSED;
- unlock:
-
+ out:
+ kfree(rc_state);
return ret;
}
@@ -339,13 +343,19 @@
static int m920x_firmware_download(struct usb_device *udev, const struct firmware *fw)
{
u16 value, index, size;
- u8 read[4], *buff;
+ u8 *read, *buff;
int i, pass, ret = 0;
buff = kmalloc(65536, GFP_KERNEL);
if (buff == NULL)
return -ENOMEM;
+ read = kmalloc(4, GFP_KERNEL);
+ if (!read) {
+ kfree(buff);
+ return -ENOMEM;
+ }
+
if ((ret = m920x_read(udev, M9206_FILTER, 0x0, 0x8000, read, 4)) != 0)
goto done;
deb("%x %x %x %x\n", read[0], read[1], read[2], read[3]);
@@ -396,6 +406,7 @@
deb("firmware uploaded!\n");
done:
+ kfree(read);
kfree(buff);
return ret;
@@ -632,9 +643,9 @@
{ 0x16, KEY_POWER },
{ 0x17, KEY_FAVORITES },
{ 0x0f, KEY_TEXT },
- { 0x48, KEY_MEDIA }, /* preview */
+ { 0x48, KEY_PROGRAM }, /* preview */
{ 0x1c, KEY_EPG },
- { 0x04, KEY_LIST }, /* record list */
+ { 0x04, KEY_LIST }, /* record list */
{ 0x03, KEY_1 },
{ 0x01, KEY_2 },
{ 0x06, KEY_3 },
@@ -674,14 +685,14 @@
{ 0x0e, KEY_MUTE },
/* { 0x49, KEY_LR }, */ /* L/R */
{ 0x07, KEY_SLEEP }, /* Hibernate */
- { 0x08, KEY_MEDIA }, /* A/V */
- { 0x0e, KEY_MENU }, /* Recall */
+ { 0x08, KEY_VIDEO }, /* A/V */
+ { 0x0e, KEY_MENU }, /* Recall */
{ 0x45, KEY_ZOOMIN },
{ 0x46, KEY_ZOOMOUT },
- { 0x18, KEY_TV }, /* Red */
- { 0x53, KEY_VCR }, /* Green */
- { 0x5e, KEY_SAT }, /* Yellow */
- { 0x5f, KEY_PLAYER }, /* Blue */
+ { 0x18, KEY_RED }, /* Red */
+ { 0x53, KEY_GREEN }, /* Green */
+ { 0x5e, KEY_YELLOW }, /* Yellow */
+ { 0x5f, KEY_BLUE }, /* Blue */
};
/* DVB USB Driver stuff */
diff --git a/drivers/media/dvb/dvb-usb/nova-t-usb2.c b/drivers/media/dvb/dvb-usb/nova-t-usb2.c
index 9d3cd2d..bc350e9 100644
--- a/drivers/media/dvb/dvb-usb/nova-t-usb2.c
+++ b/drivers/media/dvb/dvb-usb/nova-t-usb2.c
@@ -47,7 +47,7 @@
{ 0x1e17, KEY_RIGHT },
{ 0x1e18, KEY_VIDEO },
{ 0x1e19, KEY_AUDIO },
- { 0x1e1a, KEY_MEDIA },
+ { 0x1e1a, KEY_IMAGES },
{ 0x1e1b, KEY_EPG },
{ 0x1e1c, KEY_TV },
{ 0x1e1e, KEY_NEXT },
diff --git a/drivers/media/dvb/dvb-usb/opera1.c b/drivers/media/dvb/dvb-usb/opera1.c
index 7e569f4..2e4fab7 100644
--- a/drivers/media/dvb/dvb-usb/opera1.c
+++ b/drivers/media/dvb/dvb-usb/opera1.c
@@ -53,27 +53,36 @@
u8 * data, u16 len, int flags)
{
int ret;
- u8 r;
- u8 u8buf[len];
-
+ u8 tmp;
+ u8 *buf;
unsigned int pipe = (flags == OPERA_READ_MSG) ?
usb_rcvctrlpipe(dev,0) : usb_sndctrlpipe(dev, 0);
u8 request_type = (flags == OPERA_READ_MSG) ? USB_DIR_IN : USB_DIR_OUT;
+ buf = kmalloc(len, GFP_KERNEL);
+ if (!buf)
+ return -ENOMEM;
+
if (flags == OPERA_WRITE_MSG)
- memcpy(u8buf, data, len);
- ret =
- usb_control_msg(dev, pipe, request, request_type | USB_TYPE_VENDOR,
- value, 0x0, u8buf, len, 2000);
+ memcpy(buf, data, len);
+ ret = usb_control_msg(dev, pipe, request,
+ request_type | USB_TYPE_VENDOR, value, 0x0,
+ buf, len, 2000);
if (request == OPERA_TUNER_REQ) {
+ tmp = buf[0];
if (usb_control_msg(dev, usb_rcvctrlpipe(dev, 0),
- OPERA_TUNER_REQ, USB_DIR_IN | USB_TYPE_VENDOR,
- 0x01, 0x0, &r, 1, 2000)<1 || r!=0x08)
- return 0;
+ OPERA_TUNER_REQ, USB_DIR_IN | USB_TYPE_VENDOR,
+ 0x01, 0x0, buf, 1, 2000) < 1 || buf[0] != 0x08) {
+ ret = 0;
+ goto out;
+ }
+ buf[0] = tmp;
}
if (flags == OPERA_READ_MSG)
- memcpy(data, u8buf, len);
+ memcpy(data, buf, len);
+out:
+ kfree(buf);
return ret;
}
@@ -189,7 +198,7 @@
static u8 opera1_inittab[] = {
0x00, 0xa1,
0x01, 0x15,
- 0x02, 0x00,
+ 0x02, 0x30,
0x03, 0x00,
0x04, 0x7d,
0x05, 0x05,
diff --git a/drivers/media/dvb/dvb-usb/vp702x-fe.c b/drivers/media/dvb/dvb-usb/vp702x-fe.c
index ccc7e44..2bb8d4c 100644
--- a/drivers/media/dvb/dvb-usb/vp702x-fe.c
+++ b/drivers/media/dvb/dvb-usb/vp702x-fe.c
@@ -41,14 +41,23 @@
static int vp702x_fe_refresh_state(struct vp702x_fe_state *st)
{
- u8 buf[10];
- if (time_after(jiffies,st->next_status_check)) {
- vp702x_usb_in_op(st->d,READ_STATUS,0,0,buf,10);
+ struct vp702x_device_state *dst = st->d->priv;
+ u8 *buf;
+ if (time_after(jiffies, st->next_status_check)) {
+ mutex_lock(&dst->buf_mutex);
+ buf = dst->buf;
+
+ vp702x_usb_in_op(st->d, READ_STATUS, 0, 0, buf, 10);
st->lock = buf[4];
- vp702x_usb_in_op(st->d,READ_TUNER_REG_REQ,0x11,0,&st->snr,1);
- vp702x_usb_in_op(st->d,READ_TUNER_REG_REQ,0x15,0,&st->sig,1);
+ vp702x_usb_in_op(st->d, READ_TUNER_REG_REQ, 0x11, 0, buf, 1);
+ st->snr = buf[0];
+
+ vp702x_usb_in_op(st->d, READ_TUNER_REG_REQ, 0x15, 0, buf, 1);
+ st->sig = buf[0];
+
+ mutex_unlock(&dst->buf_mutex);
st->next_status_check = jiffies + (st->status_check_interval*HZ)/1000;
}
return 0;
@@ -130,11 +139,17 @@
struct dvb_frontend_parameters *fep)
{
struct vp702x_fe_state *st = fe->demodulator_priv;
+ struct vp702x_device_state *dst = st->d->priv;
u32 freq = fep->frequency/1000;
/*CalFrequency*/
/* u16 frequencyRef[16] = { 2, 4, 8, 16, 32, 64, 128, 256, 24, 5, 10, 20, 40, 80, 160, 320 }; */
u64 sr;
- u8 cmd[8] = { 0 },ibuf[10];
+ u8 *cmd;
+
+ mutex_lock(&dst->buf_mutex);
+
+ cmd = dst->buf;
+ memset(cmd, 0, 10);
cmd[0] = (freq >> 8) & 0x7f;
cmd[1] = freq & 0xff;
@@ -170,13 +185,15 @@
st->status_check_interval = 250;
st->next_status_check = jiffies;
- vp702x_usb_inout_op(st->d,cmd,8,ibuf,10,100);
+ vp702x_usb_inout_op(st->d, cmd, 8, cmd, 10, 100);
- if (ibuf[2] == 0 && ibuf[3] == 0)
+ if (cmd[2] == 0 && cmd[3] == 0)
deb_fe("tuning failed.\n");
else
deb_fe("tuning succeeded.\n");
+ mutex_unlock(&dst->buf_mutex);
+
return 0;
}
@@ -204,27 +221,32 @@
static int vp702x_fe_send_diseqc_msg (struct dvb_frontend* fe,
struct dvb_diseqc_master_cmd *m)
{
+ u8 *cmd;
struct vp702x_fe_state *st = fe->demodulator_priv;
- u8 cmd[8],ibuf[10];
- memset(cmd,0,8);
+ struct vp702x_device_state *dst = st->d->priv;
deb_fe("%s\n",__func__);
if (m->msg_len > 4)
return -EINVAL;
+ mutex_lock(&dst->buf_mutex);
+
+ cmd = dst->buf;
cmd[1] = SET_DISEQC_CMD;
cmd[2] = m->msg_len;
memcpy(&cmd[3], m->msg, m->msg_len);
- cmd[7] = vp702x_chksum(cmd,0,7);
+ cmd[7] = vp702x_chksum(cmd, 0, 7);
- vp702x_usb_inout_op(st->d,cmd,8,ibuf,10,100);
+ vp702x_usb_inout_op(st->d, cmd, 8, cmd, 10, 100);
- if (ibuf[2] == 0 && ibuf[3] == 0)
+ if (cmd[2] == 0 && cmd[3] == 0)
deb_fe("diseqc cmd failed.\n");
else
deb_fe("diseqc cmd succeeded.\n");
+ mutex_unlock(&dst->buf_mutex);
+
return 0;
}
@@ -237,7 +259,9 @@
static int vp702x_fe_set_tone(struct dvb_frontend* fe, fe_sec_tone_mode_t tone)
{
struct vp702x_fe_state *st = fe->demodulator_priv;
- u8 ibuf[10];
+ struct vp702x_device_state *dst = st->d->priv;
+ u8 *buf;
+
deb_fe("%s\n",__func__);
st->tone_mode = tone;
@@ -247,14 +271,21 @@
else
st->lnb_buf[2] = 0x00;
- st->lnb_buf[7] = vp702x_chksum(st->lnb_buf,0,7);
+ st->lnb_buf[7] = vp702x_chksum(st->lnb_buf, 0, 7);
- vp702x_usb_inout_op(st->d,st->lnb_buf,8,ibuf,10,100);
- if (ibuf[2] == 0 && ibuf[3] == 0)
+ mutex_lock(&dst->buf_mutex);
+
+ buf = dst->buf;
+ memcpy(buf, st->lnb_buf, 8);
+
+ vp702x_usb_inout_op(st->d, buf, 8, buf, 10, 100);
+ if (buf[2] == 0 && buf[3] == 0)
deb_fe("set_tone cmd failed.\n");
else
deb_fe("set_tone cmd succeeded.\n");
+ mutex_unlock(&dst->buf_mutex);
+
return 0;
}
@@ -262,7 +293,8 @@
voltage)
{
struct vp702x_fe_state *st = fe->demodulator_priv;
- u8 ibuf[10];
+ struct vp702x_device_state *dst = st->d->priv;
+ u8 *buf;
deb_fe("%s\n",__func__);
st->voltage = voltage;
@@ -272,14 +304,20 @@
else
st->lnb_buf[4] = 0x00;
- st->lnb_buf[7] = vp702x_chksum(st->lnb_buf,0,7);
+ st->lnb_buf[7] = vp702x_chksum(st->lnb_buf, 0, 7);
- vp702x_usb_inout_op(st->d,st->lnb_buf,8,ibuf,10,100);
- if (ibuf[2] == 0 && ibuf[3] == 0)
+ mutex_lock(&dst->buf_mutex);
+
+ buf = dst->buf;
+ memcpy(buf, st->lnb_buf, 8);
+
+ vp702x_usb_inout_op(st->d, buf, 8, buf, 10, 100);
+ if (buf[2] == 0 && buf[3] == 0)
deb_fe("set_voltage cmd failed.\n");
else
deb_fe("set_voltage cmd succeeded.\n");
+ mutex_unlock(&dst->buf_mutex);
return 0;
}
diff --git a/drivers/media/dvb/dvb-usb/vp702x.c b/drivers/media/dvb/dvb-usb/vp702x.c
index 7890e75..54355f8 100644
--- a/drivers/media/dvb/dvb-usb/vp702x.c
+++ b/drivers/media/dvb/dvb-usb/vp702x.c
@@ -15,6 +15,7 @@
* see Documentation/dvb/README.dvb-usb for more information
*/
#include "vp702x.h"
+#include <linux/mutex.h>
/* debug */
int dvb_usb_vp702x_debug;
@@ -23,27 +24,23 @@
DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
-struct vp702x_state {
+struct vp702x_adapter_state {
int pid_filter_count;
int pid_filter_can_bypass;
u8 pid_filter_state;
};
-struct vp702x_device_state {
- u8 power_state;
-};
-
-/* check for mutex FIXME */
-int vp702x_usb_in_op(struct dvb_usb_device *d, u8 req, u16 value, u16 index, u8 *b, int blen)
+static int vp702x_usb_in_op_unlocked(struct dvb_usb_device *d, u8 req,
+ u16 value, u16 index, u8 *b, int blen)
{
- int ret = -1;
+ int ret;
- ret = usb_control_msg(d->udev,
- usb_rcvctrlpipe(d->udev,0),
- req,
- USB_TYPE_VENDOR | USB_DIR_IN,
- value,index,b,blen,
- 2000);
+ ret = usb_control_msg(d->udev,
+ usb_rcvctrlpipe(d->udev, 0),
+ req,
+ USB_TYPE_VENDOR | USB_DIR_IN,
+ value, index, b, blen,
+ 2000);
if (ret < 0) {
warn("usb in operation failed. (%d)", ret);
@@ -58,8 +55,20 @@
return ret;
}
-static int vp702x_usb_out_op(struct dvb_usb_device *d, u8 req, u16 value,
- u16 index, u8 *b, int blen)
+int vp702x_usb_in_op(struct dvb_usb_device *d, u8 req, u16 value,
+ u16 index, u8 *b, int blen)
+{
+ int ret;
+
+ mutex_lock(&d->usb_mutex);
+ ret = vp702x_usb_in_op_unlocked(d, req, value, index, b, blen);
+ mutex_unlock(&d->usb_mutex);
+
+ return ret;
+}
+
+int vp702x_usb_out_op_unlocked(struct dvb_usb_device *d, u8 req, u16 value,
+ u16 index, u8 *b, int blen)
{
int ret;
deb_xfer("out: req. %02x, val: %04x, ind: %04x, buffer: ",req,value,index);
@@ -77,6 +86,18 @@
return 0;
}
+int vp702x_usb_out_op(struct dvb_usb_device *d, u8 req, u16 value,
+ u16 index, u8 *b, int blen)
+{
+ int ret;
+
+ mutex_lock(&d->usb_mutex);
+ ret = vp702x_usb_out_op_unlocked(d, req, value, index, b, blen);
+ mutex_unlock(&d->usb_mutex);
+
+ return ret;
+}
+
int vp702x_usb_inout_op(struct dvb_usb_device *d, u8 *o, int olen, u8 *i, int ilen, int msec)
{
int ret;
@@ -84,50 +105,93 @@
if ((ret = mutex_lock_interruptible(&d->usb_mutex)))
return ret;
- ret = vp702x_usb_out_op(d,REQUEST_OUT,0,0,o,olen);
+ ret = vp702x_usb_out_op_unlocked(d, REQUEST_OUT, 0, 0, o, olen);
msleep(msec);
- ret = vp702x_usb_in_op(d,REQUEST_IN,0,0,i,ilen);
+ ret = vp702x_usb_in_op_unlocked(d, REQUEST_IN, 0, 0, i, ilen);
mutex_unlock(&d->usb_mutex);
-
return ret;
}
static int vp702x_usb_inout_cmd(struct dvb_usb_device *d, u8 cmd, u8 *o,
int olen, u8 *i, int ilen, int msec)
{
- u8 bout[olen+2];
- u8 bin[ilen+1];
+ struct vp702x_device_state *st = d->priv;
int ret = 0;
+ u8 *buf;
+ int buflen = max(olen + 2, ilen + 1);
- bout[0] = 0x00;
- bout[1] = cmd;
- memcpy(&bout[2],o,olen);
+ ret = mutex_lock_interruptible(&st->buf_mutex);
+ if (ret < 0)
+ return ret;
- ret = vp702x_usb_inout_op(d, bout, olen+2, bin, ilen+1,msec);
+ if (buflen > st->buf_len) {
+ buf = kmalloc(buflen, GFP_KERNEL);
+ if (!buf) {
+ mutex_unlock(&st->buf_mutex);
+ return -ENOMEM;
+ }
+ info("successfully reallocated a bigger buffer");
+ kfree(st->buf);
+ st->buf = buf;
+ st->buf_len = buflen;
+ } else {
+ buf = st->buf;
+ }
+
+ buf[0] = 0x00;
+ buf[1] = cmd;
+ memcpy(&buf[2], o, olen);
+
+ ret = vp702x_usb_inout_op(d, buf, olen+2, buf, ilen+1, msec);
if (ret == 0)
- memcpy(i,&bin[1],ilen);
+ memcpy(i, &buf[1], ilen);
+ mutex_unlock(&st->buf_mutex);
return ret;
}
static int vp702x_set_pld_mode(struct dvb_usb_adapter *adap, u8 bypass)
{
- u8 buf[16] = { 0 };
- return vp702x_usb_in_op(adap->dev, 0xe0, (bypass << 8) | 0x0e, 0, buf, 16);
+ int ret;
+ struct vp702x_device_state *st = adap->dev->priv;
+ u8 *buf;
+
+ mutex_lock(&st->buf_mutex);
+
+ buf = st->buf;
+ memset(buf, 0, 16);
+
+ ret = vp702x_usb_in_op(adap->dev, 0xe0, (bypass << 8) | 0x0e,
+ 0, buf, 16);
+ mutex_unlock(&st->buf_mutex);
+ return ret;
}
static int vp702x_set_pld_state(struct dvb_usb_adapter *adap, u8 state)
{
- u8 buf[16] = { 0 };
- return vp702x_usb_in_op(adap->dev, 0xe0, (state << 8) | 0x0f, 0, buf, 16);
+ int ret;
+ struct vp702x_device_state *st = adap->dev->priv;
+ u8 *buf;
+
+ mutex_lock(&st->buf_mutex);
+
+ buf = st->buf;
+ memset(buf, 0, 16);
+ ret = vp702x_usb_in_op(adap->dev, 0xe0, (state << 8) | 0x0f,
+ 0, buf, 16);
+
+ mutex_unlock(&st->buf_mutex);
+
+ return ret;
}
static int vp702x_set_pid(struct dvb_usb_adapter *adap, u16 pid, u8 id, int onoff)
{
- struct vp702x_state *st = adap->priv;
- u8 buf[16] = { 0 };
+ struct vp702x_adapter_state *st = adap->priv;
+ struct vp702x_device_state *dst = adap->dev->priv;
+ u8 *buf;
if (onoff)
st->pid_filter_state |= (1 << id);
@@ -139,32 +203,45 @@
id = 0x10 + id*2;
vp702x_set_pld_state(adap, st->pid_filter_state);
+
+ mutex_lock(&dst->buf_mutex);
+
+ buf = dst->buf;
+ memset(buf, 0, 16);
vp702x_usb_in_op(adap->dev, 0xe0, (((pid >> 8) & 0xff) << 8) | (id), 0, buf, 16);
vp702x_usb_in_op(adap->dev, 0xe0, (((pid ) & 0xff) << 8) | (id+1), 0, buf, 16);
+
+ mutex_unlock(&dst->buf_mutex);
+
return 0;
}
static int vp702x_init_pid_filter(struct dvb_usb_adapter *adap)
{
- struct vp702x_state *st = adap->priv;
+ struct vp702x_adapter_state *st = adap->priv;
+ struct vp702x_device_state *dst = adap->dev->priv;
int i;
- u8 b[10] = { 0 };
+ u8 *b;
st->pid_filter_count = 8;
st->pid_filter_can_bypass = 1;
st->pid_filter_state = 0x00;
- vp702x_set_pld_mode(adap, 1); // bypass
+ vp702x_set_pld_mode(adap, 1); /* bypass */
for (i = 0; i < st->pid_filter_count; i++)
vp702x_set_pid(adap, 0xffff, i, 1);
+ mutex_lock(&dst->buf_mutex);
+ b = dst->buf;
+ memset(b, 0, 10);
vp702x_usb_in_op(adap->dev, 0xb5, 3, 0, b, 10);
vp702x_usb_in_op(adap->dev, 0xb5, 0, 0, b, 10);
vp702x_usb_in_op(adap->dev, 0xb5, 1, 0, b, 10);
+ mutex_unlock(&dst->buf_mutex);
+ /*vp702x_set_pld_mode(d, 0); // filter */
- //vp702x_set_pld_mode(d, 0); // filter
return 0;
}
@@ -182,18 +259,23 @@
/* remote control stuff (does not work with my box) */
static int vp702x_rc_query(struct dvb_usb_device *d, u32 *event, int *state)
{
- u8 key[10];
+ u8 *key;
int i;
/* remove the following return to enabled remote querying */
return 0;
+ key = kmalloc(10, GFP_KERNEL);
+ if (!key)
+ return -ENOMEM;
+
vp702x_usb_in_op(d,READ_REMOTE_REQ,0,0,key,10);
deb_rc("remote query key: %x %d\n",key[1],key[1]);
if (key[1] == 0x44) {
*state = REMOTE_NO_KEY_PRESSED;
+ kfree(key);
return 0;
}
@@ -203,15 +285,23 @@
*event = rc_map_vp702x_table[i].keycode;
break;
}
+ kfree(key);
return 0;
}
static int vp702x_read_mac_addr(struct dvb_usb_device *d,u8 mac[6])
{
- u8 i;
+ u8 i, *buf;
+ struct vp702x_device_state *st = d->priv;
+
+ mutex_lock(&st->buf_mutex);
+ buf = st->buf;
for (i = 6; i < 12; i++)
- vp702x_usb_in_op(d, READ_EEPROM_REQ, i, 1, &mac[i - 6], 1);
+ vp702x_usb_in_op(d, READ_EEPROM_REQ, i, 1, &buf[i - 6], 1);
+
+ memcpy(mac, buf, 6);
+ mutex_unlock(&st->buf_mutex);
return 0;
}
@@ -221,7 +311,8 @@
vp702x_usb_out_op(adap->dev, SET_TUNER_POWER_REQ, 0, 7, NULL, 0);
- if (vp702x_usb_inout_cmd(adap->dev, GET_SYSTEM_STRING, NULL, 0, buf, 10, 10))
+ if (vp702x_usb_inout_cmd(adap->dev, GET_SYSTEM_STRING, NULL, 0,
+ buf, 10, 10))
return -EIO;
buf[9] = '\0';
@@ -240,8 +331,38 @@
static int vp702x_usb_probe(struct usb_interface *intf,
const struct usb_device_id *id)
{
- return dvb_usb_device_init(intf, &vp702x_properties,
- THIS_MODULE, NULL, adapter_nr);
+ struct dvb_usb_device *d;
+ struct vp702x_device_state *st;
+ int ret;
+
+ ret = dvb_usb_device_init(intf, &vp702x_properties,
+ THIS_MODULE, &d, adapter_nr);
+ if (ret)
+ goto out;
+
+ st = d->priv;
+ st->buf_len = 16;
+ st->buf = kmalloc(st->buf_len, GFP_KERNEL);
+ if (!st->buf) {
+ ret = -ENOMEM;
+ dvb_usb_device_exit(intf);
+ goto out;
+ }
+ mutex_init(&st->buf_mutex);
+
+out:
+ return ret;
+
+}
+
+static void vp702x_usb_disconnect(struct usb_interface *intf)
+{
+ struct dvb_usb_device *d = usb_get_intfdata(intf);
+ struct vp702x_device_state *st = d->priv;
+ mutex_lock(&st->buf_mutex);
+ kfree(st->buf);
+ mutex_unlock(&st->buf_mutex);
+ dvb_usb_device_exit(intf);
}
static struct usb_device_id vp702x_usb_table [] = {
@@ -278,7 +399,7 @@
}
}
},
- .size_of_priv = sizeof(struct vp702x_state),
+ .size_of_priv = sizeof(struct vp702x_adapter_state),
}
},
.read_mac_address = vp702x_read_mac_addr,
@@ -307,9 +428,9 @@
/* usb specific object needed to register this driver with the usb subsystem */
static struct usb_driver vp702x_usb_driver = {
.name = "dvb_usb_vp702x",
- .probe = vp702x_usb_probe,
- .disconnect = dvb_usb_device_exit,
- .id_table = vp702x_usb_table,
+ .probe = vp702x_usb_probe,
+ .disconnect = vp702x_usb_disconnect,
+ .id_table = vp702x_usb_table,
};
/* module stuff */
diff --git a/drivers/media/dvb/dvb-usb/vp702x.h b/drivers/media/dvb/dvb-usb/vp702x.h
index c2f97f9..20b9005 100644
--- a/drivers/media/dvb/dvb-usb/vp702x.h
+++ b/drivers/media/dvb/dvb-usb/vp702x.h
@@ -98,6 +98,13 @@
#define RESET_TUNER 0xBE
/* IN i: 0, v: 0, no extra buffer */
+struct vp702x_device_state {
+ struct mutex buf_mutex;
+ int buf_len;
+ u8 *buf;
+};
+
+
extern struct dvb_frontend * vp702x_fe_attach(struct dvb_usb_device *d);
extern int vp702x_usb_inout_op(struct dvb_usb_device *d, u8 *o, int olen, u8 *i, int ilen, int msec);
diff --git a/drivers/media/dvb/dvb-usb/vp7045.c b/drivers/media/dvb/dvb-usb/vp7045.c
index ab0ab3c..3db89e3 100644
--- a/drivers/media/dvb/dvb-usb/vp7045.c
+++ b/drivers/media/dvb/dvb-usb/vp7045.c
@@ -28,9 +28,9 @@
int vp7045_usb_op(struct dvb_usb_device *d, u8 cmd, u8 *out, int outlen, u8 *in, int inlen, int msec)
{
int ret = 0;
- u8 inbuf[12] = { 0 }, outbuf[20] = { 0 };
+ u8 *buf = d->priv;
- outbuf[0] = cmd;
+ buf[0] = cmd;
if (outlen > 19)
outlen = 19;
@@ -38,19 +38,21 @@
if (inlen > 11)
inlen = 11;
+ ret = mutex_lock_interruptible(&d->usb_mutex);
+ if (ret)
+ return ret;
+
if (out != NULL && outlen > 0)
- memcpy(&outbuf[1], out, outlen);
+ memcpy(&buf[1], out, outlen);
deb_xfer("out buffer: ");
- debug_dump(outbuf,outlen+1,deb_xfer);
+ debug_dump(buf, outlen+1, deb_xfer);
- if ((ret = mutex_lock_interruptible(&d->usb_mutex)))
- return ret;
if (usb_control_msg(d->udev,
usb_sndctrlpipe(d->udev,0),
TH_COMMAND_OUT, USB_TYPE_VENDOR | USB_DIR_OUT, 0, 0,
- outbuf, 20, 2000) != 20) {
+ buf, 20, 2000) != 20) {
err("USB control message 'out' went wrong.");
ret = -EIO;
goto unlock;
@@ -61,17 +63,17 @@
if (usb_control_msg(d->udev,
usb_rcvctrlpipe(d->udev,0),
TH_COMMAND_IN, USB_TYPE_VENDOR | USB_DIR_IN, 0, 0,
- inbuf, 12, 2000) != 12) {
+ buf, 12, 2000) != 12) {
err("USB control message 'in' went wrong.");
ret = -EIO;
goto unlock;
}
deb_xfer("in buffer: ");
- debug_dump(inbuf,12,deb_xfer);
+ debug_dump(buf, 12, deb_xfer);
if (in != NULL && inlen > 0)
- memcpy(in,&inbuf[1],inlen);
+ memcpy(in, &buf[1], inlen);
unlock:
mutex_unlock(&d->usb_mutex);
@@ -222,8 +224,26 @@
static int vp7045_usb_probe(struct usb_interface *intf,
const struct usb_device_id *id)
{
- return dvb_usb_device_init(intf, &vp7045_properties,
- THIS_MODULE, NULL, adapter_nr);
+ struct dvb_usb_device *d;
+ int ret = dvb_usb_device_init(intf, &vp7045_properties,
+ THIS_MODULE, &d, adapter_nr);
+ if (ret)
+ return ret;
+
+ d->priv = kmalloc(20, GFP_KERNEL);
+ if (!d->priv) {
+ dvb_usb_device_exit(intf);
+ return -ENOMEM;
+ }
+
+ return ret;
+}
+
+static void vp7045_usb_disconnect(struct usb_interface *intf)
+{
+ struct dvb_usb_device *d = usb_get_intfdata(intf);
+ kfree(d->priv);
+ dvb_usb_device_exit(intf);
}
static struct usb_device_id vp7045_usb_table [] = {
@@ -238,6 +258,7 @@
static struct dvb_usb_device_properties vp7045_properties = {
.usb_ctrl = CYPRESS_FX2,
.firmware = "dvb-usb-vp7045-01.fw",
+ .size_of_priv = sizeof(u8 *),
.num_adapters = 1,
.adapter = {
@@ -284,7 +305,7 @@
static struct usb_driver vp7045_usb_driver = {
.name = "dvb_usb_vp7045",
.probe = vp7045_usb_probe,
- .disconnect = dvb_usb_device_exit,
+ .disconnect = vp7045_usb_disconnect,
.id_table = vp7045_usb_table,
};
diff --git a/drivers/media/dvb/frontends/Kconfig b/drivers/media/dvb/frontends/Kconfig
index 83093d1..44b816f 100644
--- a/drivers/media/dvb/frontends/Kconfig
+++ b/drivers/media/dvb/frontends/Kconfig
@@ -263,18 +263,16 @@
help
A DVB-T tuner module. Say Y when you want to support this frontend.
-config DVB_DRX397XD
- tristate "Micronas DRX3975D/DRX3977D based"
+config DVB_DRXD
+ tristate "Micronas DRXD driver"
depends on DVB_CORE && I2C
default m if DVB_FE_CUSTOMISE
help
A DVB-T tuner module. Say Y when you want to support this frontend.
- TODO:
- This driver needs external firmware. Please use the command
- "<kerneldir>/Documentation/dvb/get_dvb_firmware drx397xD" to
- download/extract them, and then copy them to /usr/lib/hotplug/firmware
- or /lib/firmware (depending on configuration of firmware hotplug).
+ Note: this driver was based on vendor driver reference code (released
+ under the GPL) as opposed to the existing drx397xd driver, which
+ was written via reverse engineering.
config DVB_L64781
tristate "LSI L64781"
@@ -385,6 +383,13 @@
help
A DVB-T/C tuner module. Say Y when you want to support this frontend.
+config DVB_CXD2820R
+ tristate "Sony CXD2820R"
+ depends on DVB_CORE && I2C
+ default m if DVB_FE_CUSTOMISE
+ help
+ Say Y when you want to support this frontend.
+
comment "DVB-C (cable) frontends"
depends on DVB_CORE
diff --git a/drivers/media/dvb/frontends/Makefile b/drivers/media/dvb/frontends/Makefile
index 3b0c4bd..2f3a6f7 100644
--- a/drivers/media/dvb/frontends/Makefile
+++ b/drivers/media/dvb/frontends/Makefile
@@ -8,6 +8,8 @@
stb0899-objs = stb0899_drv.o stb0899_algo.o
stv0900-objs = stv0900_core.o stv0900_sw.o
au8522-objs = au8522_dig.o au8522_decoder.o
+drxd-objs = drxd_firm.o drxd_hard.o
+cxd2820r-objs = cxd2820r_core.o cxd2820r_c.o cxd2820r_t.o cxd2820r_t2.o
obj-$(CONFIG_DVB_PLL) += dvb-pll.o
obj-$(CONFIG_DVB_STV0299) += stv0299.o
@@ -36,7 +38,7 @@
obj-$(CONFIG_DVB_ZL10039) += zl10039.o
obj-$(CONFIG_DVB_ZL10353) += zl10353.o
obj-$(CONFIG_DVB_CX22702) += cx22702.o
-obj-$(CONFIG_DVB_DRX397XD) += drx397xD.o
+obj-$(CONFIG_DVB_DRXD) += drxd.o
obj-$(CONFIG_DVB_TDA10021) += tda10021.o
obj-$(CONFIG_DVB_TDA10023) += tda10023.o
obj-$(CONFIG_DVB_STV0297) += stv0297.o
@@ -85,3 +87,5 @@
obj-$(CONFIG_DVB_MB86A20S) += mb86a20s.o
obj-$(CONFIG_DVB_IX2505V) += ix2505v.o
obj-$(CONFIG_DVB_STV0367) += stv0367.o
+obj-$(CONFIG_DVB_CXD2820R) += cxd2820r.o
+
diff --git a/drivers/media/dvb/frontends/bsbe1-d01a.h b/drivers/media/dvb/frontends/bsbe1-d01a.h
new file mode 100644
index 0000000..7ed3c42
--- /dev/null
+++ b/drivers/media/dvb/frontends/bsbe1-d01a.h
@@ -0,0 +1,146 @@
+/*
+ * bsbe1-d01a.h - ALPS BSBE1-D01A tuner support
+ *
+ * Copyright (C) 2011 Oliver Endriss <o.endriss@gmx.de>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 2
+ * of the License, or (at your option) any later version.
+ *
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
+ *
+ *
+ * the project's page is at http://www.linuxtv.org
+ */
+
+#ifndef BSBE1_D01A_H
+#define BSBE1_D01A_H
+
+#include "stb6000.h"
+#include "stv0288.h"
+
+static u8 stv0288_bsbe1_d01a_inittab[] = {
+ 0x01, 0x15,
+ 0x02, 0x20,
+ 0x09, 0x0,
+ 0x0a, 0x4,
+ 0x0b, 0x0,
+ 0x0c, 0x0,
+ 0x0d, 0x0,
+ 0x0e, 0xd4,
+ 0x0f, 0x30,
+ 0x11, 0x80,
+ 0x12, 0x03,
+ 0x13, 0x48,
+ 0x14, 0x84,
+ 0x15, 0x45,
+ 0x16, 0xb7,
+ 0x17, 0x9c,
+ 0x18, 0x0,
+ 0x19, 0xa6,
+ 0x1a, 0x88,
+ 0x1b, 0x8f,
+ 0x1c, 0xf0,
+ 0x20, 0x0b,
+ 0x21, 0x54,
+ 0x22, 0x0,
+ 0x23, 0x0,
+ 0x2b, 0xff,
+ 0x2c, 0xf7,
+ 0x30, 0x0,
+ 0x31, 0x1e,
+ 0x32, 0x14,
+ 0x33, 0x0f,
+ 0x34, 0x09,
+ 0x35, 0x0c,
+ 0x36, 0x05,
+ 0x37, 0x2f,
+ 0x38, 0x16,
+ 0x39, 0xbd,
+ 0x3a, 0x03,
+ 0x3b, 0x13,
+ 0x3c, 0x11,
+ 0x3d, 0x30,
+ 0x40, 0x63,
+ 0x41, 0x04,
+ 0x42, 0x60,
+ 0x43, 0x00,
+ 0x44, 0x00,
+ 0x45, 0x00,
+ 0x46, 0x00,
+ 0x47, 0x00,
+ 0x4a, 0x00,
+ 0x50, 0x10,
+ 0x51, 0x36,
+ 0x52, 0x09,
+ 0x53, 0x94,
+ 0x54, 0x62,
+ 0x55, 0x29,
+ 0x56, 0x64,
+ 0x57, 0x2b,
+ 0x58, 0x54,
+ 0x59, 0x86,
+ 0x5a, 0x0,
+ 0x5b, 0x9b,
+ 0x5c, 0x08,
+ 0x5d, 0x7f,
+ 0x5e, 0x0,
+ 0x5f, 0xff,
+ 0x70, 0x0,
+ 0x71, 0x0,
+ 0x72, 0x0,
+ 0x74, 0x0,
+ 0x75, 0x0,
+ 0x76, 0x0,
+ 0x81, 0x0,
+ 0x82, 0x3f,
+ 0x83, 0x3f,
+ 0x84, 0x0,
+ 0x85, 0x0,
+ 0x88, 0x0,
+ 0x89, 0x0,
+ 0x8a, 0x0,
+ 0x8b, 0x0,
+ 0x8c, 0x0,
+ 0x90, 0x0,
+ 0x91, 0x0,
+ 0x92, 0x0,
+ 0x93, 0x0,
+ 0x94, 0x1c,
+ 0x97, 0x0,
+ 0xa0, 0x48,
+ 0xa1, 0x0,
+ 0xb0, 0xb8,
+ 0xb1, 0x3a,
+ 0xb2, 0x10,
+ 0xb3, 0x82,
+ 0xb4, 0x80,
+ 0xb5, 0x82,
+ 0xb6, 0x82,
+ 0xb7, 0x82,
+ 0xb8, 0x20,
+ 0xb9, 0x0,
+ 0xf0, 0x0,
+ 0xf1, 0x0,
+ 0xf2, 0xc0,
+ 0xff, 0xff,
+};
+
+static struct stv0288_config stv0288_bsbe1_d01a_config = {
+ .demod_address = 0x68,
+ .min_delay_ms = 100,
+ .inittab = stv0288_bsbe1_d01a_inittab,
+};
+
+#endif
diff --git a/drivers/media/dvb/frontends/bsru6.h b/drivers/media/dvb/frontends/bsru6.h
index 45a6dfd..c480c83 100644
--- a/drivers/media/dvb/frontends/bsru6.h
+++ b/drivers/media/dvb/frontends/bsru6.h
@@ -27,7 +27,7 @@
static u8 alps_bsru6_inittab[] = {
0x01, 0x15,
- 0x02, 0x00,
+ 0x02, 0x30,
0x03, 0x00,
0x04, 0x7d, /* F22FR = 0x7d, F22 = f_VCO / 128 / 0x7d = 22 kHz */
0x05, 0x35, /* I2CT = 0, SCLT = 1, SDAT = 1 */
diff --git a/drivers/media/dvb/frontends/cx24116.c b/drivers/media/dvb/frontends/cx24116.c
index 2410d8b..95c6465 100644
--- a/drivers/media/dvb/frontends/cx24116.c
+++ b/drivers/media/dvb/frontends/cx24116.c
@@ -137,7 +137,7 @@
/* SNR measurements */
static int esno_snr;
module_param(esno_snr, int, 0644);
-MODULE_PARM_DESC(debug, "SNR return units, 0=PERCENTAGE 0-100, "\
+MODULE_PARM_DESC(esno_snr, "SNR return units, 0=PERCENTAGE 0-100, "\
"1=ESNO(db * 10) (default:0)");
enum cmds {
@@ -566,7 +566,7 @@
{
struct cx24116_state *state = fe->demodulator_priv;
struct cx24116_cmd cmd;
- int i, ret;
+ int i, ret, len, max, remaining;
unsigned char vers[4];
dprintk("%s\n", __func__);
@@ -603,8 +603,21 @@
cx24116_writereg(state, 0xF5, 0x00);
cx24116_writereg(state, 0xF6, 0x00);
- /* write the entire firmware as one transaction */
- cx24116_writeregN(state, 0xF7, fw->data, fw->size);
+ /* Split firmware to the max I2C write len and write.
+ * Writes whole firmware as one write when i2c_wr_max is set to 0. */
+ if (state->config->i2c_wr_max)
+ max = state->config->i2c_wr_max;
+ else
+ max = INT_MAX; /* enough for 32k firmware */
+
+ for (remaining = fw->size; remaining > 0; remaining -= max - 1) {
+ len = remaining;
+ if (len > max - 1)
+ len = max - 1;
+
+ cx24116_writeregN(state, 0xF7, &fw->data[fw->size - remaining],
+ len);
+ }
cx24116_writereg(state, 0xF4, 0x10);
cx24116_writereg(state, 0xF0, 0x00);
diff --git a/drivers/media/dvb/frontends/cx24116.h b/drivers/media/dvb/frontends/cx24116.h
index b1b76b4..7d90ab9 100644
--- a/drivers/media/dvb/frontends/cx24116.h
+++ b/drivers/media/dvb/frontends/cx24116.h
@@ -35,6 +35,9 @@
/* Need to set MPEG parameters */
u8 mpg_clk_pos_pol:0x02;
+
+ /* max bytes I2C provider can write at once */
+ u16 i2c_wr_max;
};
#if defined(CONFIG_DVB_CX24116) || \
diff --git a/drivers/media/dvb/frontends/cxd2820r.h b/drivers/media/dvb/frontends/cxd2820r.h
new file mode 100644
index 0000000..ad17845
--- /dev/null
+++ b/drivers/media/dvb/frontends/cxd2820r.h
@@ -0,0 +1,118 @@
+/*
+ * Sony CXD2820R demodulator driver
+ *
+ * Copyright (C) 2010 Antti Palosaari <crope@iki.fi>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+
+#ifndef CXD2820R_H
+#define CXD2820R_H
+
+#include <linux/dvb/frontend.h>
+
+#define CXD2820R_GPIO_D (0 << 0) /* disable */
+#define CXD2820R_GPIO_E (1 << 0) /* enable */
+#define CXD2820R_GPIO_O (0 << 1) /* output */
+#define CXD2820R_GPIO_I (1 << 1) /* input */
+#define CXD2820R_GPIO_L (0 << 2) /* output low */
+#define CXD2820R_GPIO_H (1 << 2) /* output high */
+
+#define CXD2820R_TS_SERIAL 0x08
+#define CXD2820R_TS_SERIAL_MSB 0x28
+#define CXD2820R_TS_PARALLEL 0x30
+#define CXD2820R_TS_PARALLEL_MSB 0x70
+
+struct cxd2820r_config {
+ /* Demodulator I2C address.
+ * Driver determines DVB-C slave I2C address automatically from master
+ * address.
+ * Default: none, must set
+ * Values: 0x6c, 0x6d
+ */
+ u8 i2c_address;
+
+ /* TS output mode.
+ * Default: none, must set.
+ * Values:
+ */
+ u8 ts_mode;
+
+ /* IF AGC polarity.
+ * Default: 0
+ * Values: 0, 1
+ */
+ int if_agc_polarity:1;
+
+ /* Spectrum inversion.
+ * Default: 0
+ * Values: 0, 1
+ */
+ int spec_inv:1;
+
+ /* IFs for all used modes.
+ * Default: none, must set
+ * Values: <kHz>
+ */
+ u16 if_dvbt_6;
+ u16 if_dvbt_7;
+ u16 if_dvbt_8;
+ u16 if_dvbt2_5;
+ u16 if_dvbt2_6;
+ u16 if_dvbt2_7;
+ u16 if_dvbt2_8;
+ u16 if_dvbc;
+
+ /* GPIOs for all used modes.
+ * Default: none, disabled
+ * Values: <see above>
+ */
+ u8 gpio_dvbt[3];
+ u8 gpio_dvbt2[3];
+ u8 gpio_dvbc[3];
+};
+
+
+#if defined(CONFIG_DVB_CXD2820R) || \
+ (defined(CONFIG_DVB_CXD2820R_MODULE) && defined(MODULE))
+extern struct dvb_frontend *cxd2820r_attach(
+ const struct cxd2820r_config *config,
+ struct i2c_adapter *i2c,
+ struct dvb_frontend *fe
+);
+extern struct i2c_adapter *cxd2820r_get_tuner_i2c_adapter(
+ struct dvb_frontend *fe
+);
+#else
+static inline struct dvb_frontend *cxd2820r_attach(
+ const struct cxd2820r_config *config,
+ struct i2c_adapter *i2c,
+ struct dvb_frontend *fe
+)
+{
+ printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
+ return NULL;
+}
+static inline struct i2c_adapter *cxd2820r_get_tuner_i2c_adapter(
+ struct dvb_frontend *fe
+)
+{
+ return NULL;
+}
+
+#endif
+
+#endif /* CXD2820R_H */
diff --git a/drivers/media/dvb/frontends/cxd2820r_c.c b/drivers/media/dvb/frontends/cxd2820r_c.c
new file mode 100644
index 0000000..3c07d40
--- /dev/null
+++ b/drivers/media/dvb/frontends/cxd2820r_c.c
@@ -0,0 +1,338 @@
+/*
+ * Sony CXD2820R demodulator driver
+ *
+ * Copyright (C) 2010 Antti Palosaari <crope@iki.fi>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+
+#include "cxd2820r_priv.h"
+
+int cxd2820r_set_frontend_c(struct dvb_frontend *fe,
+ struct dvb_frontend_parameters *params)
+{
+ struct cxd2820r_priv *priv = fe->demodulator_priv;
+ struct dtv_frontend_properties *c = &fe->dtv_property_cache;
+ int ret, i;
+ u8 buf[2];
+ u16 if_ctl;
+ u64 num;
+ struct reg_val_mask tab[] = {
+ { 0x00080, 0x01, 0xff },
+ { 0x00081, 0x05, 0xff },
+ { 0x00085, 0x07, 0xff },
+ { 0x00088, 0x01, 0xff },
+
+ { 0x00082, 0x20, 0x60 },
+ { 0x1016a, 0x48, 0xff },
+ { 0x100a5, 0x00, 0x01 },
+ { 0x10020, 0x06, 0x07 },
+ { 0x10059, 0x50, 0xff },
+ { 0x10087, 0x0c, 0x3c },
+ { 0x1008b, 0x07, 0xff },
+ { 0x1001f, priv->cfg.if_agc_polarity << 7, 0x80 },
+ { 0x10070, priv->cfg.ts_mode, 0xff },
+ };
+
+ dbg("%s: RF=%d SR=%d", __func__, c->frequency, c->symbol_rate);
+
+ /* update GPIOs */
+ ret = cxd2820r_gpio(fe);
+ if (ret)
+ goto error;
+
+ /* program tuner */
+ if (fe->ops.tuner_ops.set_params)
+ fe->ops.tuner_ops.set_params(fe, params);
+
+ if (priv->delivery_system != SYS_DVBC_ANNEX_AC) {
+ for (i = 0; i < ARRAY_SIZE(tab); i++) {
+ ret = cxd2820r_wr_reg_mask(priv, tab[i].reg,
+ tab[i].val, tab[i].mask);
+ if (ret)
+ goto error;
+ }
+ }
+
+ priv->delivery_system = SYS_DVBC_ANNEX_AC;
+ priv->ber_running = 0; /* tune stops BER counter */
+
+ num = priv->cfg.if_dvbc;
+ num *= 0x4000;
+ if_ctl = cxd2820r_div_u64_round_closest(num, 41000);
+ buf[0] = (if_ctl >> 8) & 0x3f;
+ buf[1] = (if_ctl >> 0) & 0xff;
+
+ ret = cxd2820r_wr_regs(priv, 0x10042, buf, 2);
+ if (ret)
+ goto error;
+
+ ret = cxd2820r_wr_reg(priv, 0x000ff, 0x08);
+ if (ret)
+ goto error;
+
+ ret = cxd2820r_wr_reg(priv, 0x000fe, 0x01);
+ if (ret)
+ goto error;
+
+ return ret;
+error:
+ dbg("%s: failed:%d", __func__, ret);
+ return ret;
+}
+
+int cxd2820r_get_frontend_c(struct dvb_frontend *fe,
+ struct dvb_frontend_parameters *p)
+{
+ struct cxd2820r_priv *priv = fe->demodulator_priv;
+ struct dtv_frontend_properties *c = &fe->dtv_property_cache;
+ int ret;
+ u8 buf[2];
+
+ ret = cxd2820r_rd_regs(priv, 0x1001a, buf, 2);
+ if (ret)
+ goto error;
+
+ c->symbol_rate = 2500 * ((buf[0] & 0x0f) << 8 | buf[1]);
+
+ ret = cxd2820r_rd_reg(priv, 0x10019, &buf[0]);
+ if (ret)
+ goto error;
+
+ switch ((buf[0] >> 0) & 0x03) {
+ case 0:
+ c->modulation = QAM_16;
+ break;
+ case 1:
+ c->modulation = QAM_32;
+ break;
+ case 2:
+ c->modulation = QAM_64;
+ break;
+ case 3:
+ c->modulation = QAM_128;
+ break;
+ case 4:
+ c->modulation = QAM_256;
+ break;
+ }
+
+ switch ((buf[0] >> 7) & 0x01) {
+ case 0:
+ c->inversion = INVERSION_OFF;
+ break;
+ case 1:
+ c->inversion = INVERSION_ON;
+ break;
+ }
+
+ return ret;
+error:
+ dbg("%s: failed:%d", __func__, ret);
+ return ret;
+}
+
+int cxd2820r_read_ber_c(struct dvb_frontend *fe, u32 *ber)
+{
+ struct cxd2820r_priv *priv = fe->demodulator_priv;
+ int ret;
+ u8 buf[3], start_ber = 0;
+ *ber = 0;
+
+ if (priv->ber_running) {
+ ret = cxd2820r_rd_regs(priv, 0x10076, buf, sizeof(buf));
+ if (ret)
+ goto error;
+
+ if ((buf[2] >> 7) & 0x01 || (buf[2] >> 4) & 0x01) {
+ *ber = (buf[2] & 0x0f) << 16 | buf[1] << 8 | buf[0];
+ start_ber = 1;
+ }
+ } else {
+ priv->ber_running = 1;
+ start_ber = 1;
+ }
+
+ if (start_ber) {
+ /* (re)start BER */
+ ret = cxd2820r_wr_reg(priv, 0x10079, 0x01);
+ if (ret)
+ goto error;
+ }
+
+ return ret;
+error:
+ dbg("%s: failed:%d", __func__, ret);
+ return ret;
+}
+
+int cxd2820r_read_signal_strength_c(struct dvb_frontend *fe,
+ u16 *strength)
+{
+ struct cxd2820r_priv *priv = fe->demodulator_priv;
+ int ret;
+ u8 buf[2];
+ u16 tmp;
+
+ ret = cxd2820r_rd_regs(priv, 0x10049, buf, sizeof(buf));
+ if (ret)
+ goto error;
+
+ tmp = (buf[0] & 0x03) << 8 | buf[1];
+ tmp = (~tmp & 0x03ff);
+
+ if (tmp == 512)
+ /* ~no signal */
+ tmp = 0;
+ else if (tmp > 350)
+ tmp = 350;
+
+ /* scale value to 0x0000-0xffff */
+ *strength = tmp * 0xffff / (350-0);
+
+ return ret;
+error:
+ dbg("%s: failed:%d", __func__, ret);
+ return ret;
+}
+
+int cxd2820r_read_snr_c(struct dvb_frontend *fe, u16 *snr)
+{
+ struct cxd2820r_priv *priv = fe->demodulator_priv;
+ int ret;
+ u8 tmp;
+ unsigned int A, B;
+ /* report SNR in dB * 10 */
+
+ ret = cxd2820r_rd_reg(priv, 0x10019, &tmp);
+ if (ret)
+ goto error;
+
+ if (((tmp >> 0) & 0x03) % 2) {
+ A = 875;
+ B = 650;
+ } else {
+ A = 950;
+ B = 760;
+ }
+
+ ret = cxd2820r_rd_reg(priv, 0x1004d, &tmp);
+ if (ret)
+ goto error;
+
+ #define CXD2820R_LOG2_E_24 24204406 /* log2(e) << 24 */
+ if (tmp)
+ *snr = A * (intlog2(B / tmp) >> 5) / (CXD2820R_LOG2_E_24 >> 5)
+ / 10;
+ else
+ *snr = 0;
+
+ return ret;
+error:
+ dbg("%s: failed:%d", __func__, ret);
+ return ret;
+}
+
+int cxd2820r_read_ucblocks_c(struct dvb_frontend *fe, u32 *ucblocks)
+{
+ *ucblocks = 0;
+ /* no way to read ? */
+ return 0;
+}
+
+int cxd2820r_read_status_c(struct dvb_frontend *fe, fe_status_t *status)
+{
+ struct cxd2820r_priv *priv = fe->demodulator_priv;
+ int ret;
+ u8 buf[2];
+ *status = 0;
+
+ ret = cxd2820r_rd_regs(priv, 0x10088, buf, sizeof(buf));
+ if (ret)
+ goto error;
+
+ if (((buf[0] >> 0) & 0x01) == 1) {
+ *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
+ FE_HAS_VITERBI | FE_HAS_SYNC;
+
+ if (((buf[1] >> 3) & 0x01) == 1) {
+ *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
+ FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
+ }
+ }
+
+ dbg("%s: lock=%02x %02x", __func__, buf[0], buf[1]);
+
+ return ret;
+error:
+ dbg("%s: failed:%d", __func__, ret);
+ return ret;
+}
+
+int cxd2820r_init_c(struct dvb_frontend *fe)
+{
+ struct cxd2820r_priv *priv = fe->demodulator_priv;
+ int ret;
+
+ ret = cxd2820r_wr_reg(priv, 0x00085, 0x07);
+ if (ret)
+ goto error;
+
+ return ret;
+error:
+ dbg("%s: failed:%d", __func__, ret);
+ return ret;
+}
+
+int cxd2820r_sleep_c(struct dvb_frontend *fe)
+{
+ struct cxd2820r_priv *priv = fe->demodulator_priv;
+ int ret, i;
+ struct reg_val_mask tab[] = {
+ { 0x000ff, 0x1f, 0xff },
+ { 0x00085, 0x00, 0xff },
+ { 0x00088, 0x01, 0xff },
+ { 0x00081, 0x00, 0xff },
+ { 0x00080, 0x00, 0xff },
+ };
+
+ dbg("%s", __func__);
+
+ priv->delivery_system = SYS_UNDEFINED;
+
+ for (i = 0; i < ARRAY_SIZE(tab); i++) {
+ ret = cxd2820r_wr_reg_mask(priv, tab[i].reg, tab[i].val,
+ tab[i].mask);
+ if (ret)
+ goto error;
+ }
+
+ return ret;
+error:
+ dbg("%s: failed:%d", __func__, ret);
+ return ret;
+}
+
+int cxd2820r_get_tune_settings_c(struct dvb_frontend *fe,
+ struct dvb_frontend_tune_settings *s)
+{
+ s->min_delay_ms = 500;
+ s->step_size = 0; /* no zigzag */
+ s->max_drift = 0;
+
+ return 0;
+}
+
diff --git a/drivers/media/dvb/frontends/cxd2820r_core.c b/drivers/media/dvb/frontends/cxd2820r_core.c
new file mode 100644
index 0000000..0779f69
--- /dev/null
+++ b/drivers/media/dvb/frontends/cxd2820r_core.c
@@ -0,0 +1,915 @@
+/*
+ * Sony CXD2820R demodulator driver
+ *
+ * Copyright (C) 2010 Antti Palosaari <crope@iki.fi>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+
+#include "cxd2820r_priv.h"
+
+int cxd2820r_debug;
+module_param_named(debug, cxd2820r_debug, int, 0644);
+MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
+
+/* write multiple registers */
+static int cxd2820r_wr_regs_i2c(struct cxd2820r_priv *priv, u8 i2c, u8 reg,
+ u8 *val, int len)
+{
+ int ret;
+ u8 buf[len+1];
+ struct i2c_msg msg[1] = {
+ {
+ .addr = i2c,
+ .flags = 0,
+ .len = sizeof(buf),
+ .buf = buf,
+ }
+ };
+
+ buf[0] = reg;
+ memcpy(&buf[1], val, len);
+
+ ret = i2c_transfer(priv->i2c, msg, 1);
+ if (ret == 1) {
+ ret = 0;
+ } else {
+ warn("i2c wr failed ret:%d reg:%02x len:%d", ret, reg, len);
+ ret = -EREMOTEIO;
+ }
+ return ret;
+}
+
+/* read multiple registers */
+static int cxd2820r_rd_regs_i2c(struct cxd2820r_priv *priv, u8 i2c, u8 reg,
+ u8 *val, int len)
+{
+ int ret;
+ u8 buf[len];
+ struct i2c_msg msg[2] = {
+ {
+ .addr = i2c,
+ .flags = 0,
+ .len = 1,
+ .buf = ®,
+ }, {
+ .addr = i2c,
+ .flags = I2C_M_RD,
+ .len = sizeof(buf),
+ .buf = buf,
+ }
+ };
+
+ ret = i2c_transfer(priv->i2c, msg, 2);
+ if (ret == 2) {
+ memcpy(val, buf, len);
+ ret = 0;
+ } else {
+ warn("i2c rd failed ret:%d reg:%02x len:%d", ret, reg, len);
+ ret = -EREMOTEIO;
+ }
+
+ return ret;
+}
+
+/* write multiple registers */
+int cxd2820r_wr_regs(struct cxd2820r_priv *priv, u32 reginfo, u8 *val,
+ int len)
+{
+ int ret;
+ u8 i2c_addr;
+ u8 reg = (reginfo >> 0) & 0xff;
+ u8 bank = (reginfo >> 8) & 0xff;
+ u8 i2c = (reginfo >> 16) & 0x01;
+
+ /* select I2C */
+ if (i2c)
+ i2c_addr = priv->cfg.i2c_address | (1 << 1); /* DVB-C */
+ else
+ i2c_addr = priv->cfg.i2c_address; /* DVB-T/T2 */
+
+ /* switch bank if needed */
+ if (bank != priv->bank[i2c]) {
+ ret = cxd2820r_wr_regs_i2c(priv, i2c_addr, 0x00, &bank, 1);
+ if (ret)
+ return ret;
+ priv->bank[i2c] = bank;
+ }
+ return cxd2820r_wr_regs_i2c(priv, i2c_addr, reg, val, len);
+}
+
+/* read multiple registers */
+int cxd2820r_rd_regs(struct cxd2820r_priv *priv, u32 reginfo, u8 *val,
+ int len)
+{
+ int ret;
+ u8 i2c_addr;
+ u8 reg = (reginfo >> 0) & 0xff;
+ u8 bank = (reginfo >> 8) & 0xff;
+ u8 i2c = (reginfo >> 16) & 0x01;
+
+ /* select I2C */
+ if (i2c)
+ i2c_addr = priv->cfg.i2c_address | (1 << 1); /* DVB-C */
+ else
+ i2c_addr = priv->cfg.i2c_address; /* DVB-T/T2 */
+
+ /* switch bank if needed */
+ if (bank != priv->bank[i2c]) {
+ ret = cxd2820r_wr_regs_i2c(priv, i2c_addr, 0x00, &bank, 1);
+ if (ret)
+ return ret;
+ priv->bank[i2c] = bank;
+ }
+ return cxd2820r_rd_regs_i2c(priv, i2c_addr, reg, val, len);
+}
+
+/* write single register */
+int cxd2820r_wr_reg(struct cxd2820r_priv *priv, u32 reg, u8 val)
+{
+ return cxd2820r_wr_regs(priv, reg, &val, 1);
+}
+
+/* read single register */
+int cxd2820r_rd_reg(struct cxd2820r_priv *priv, u32 reg, u8 *val)
+{
+ return cxd2820r_rd_regs(priv, reg, val, 1);
+}
+
+/* write single register with mask */
+int cxd2820r_wr_reg_mask(struct cxd2820r_priv *priv, u32 reg, u8 val,
+ u8 mask)
+{
+ int ret;
+ u8 tmp;
+
+ /* no need for read if whole reg is written */
+ if (mask != 0xff) {
+ ret = cxd2820r_rd_reg(priv, reg, &tmp);
+ if (ret)
+ return ret;
+
+ val &= mask;
+ tmp &= ~mask;
+ val |= tmp;
+ }
+
+ return cxd2820r_wr_reg(priv, reg, val);
+}
+
+int cxd2820r_gpio(struct dvb_frontend *fe)
+{
+ struct cxd2820r_priv *priv = fe->demodulator_priv;
+ int ret, i;
+ u8 *gpio, tmp0, tmp1;
+ dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
+
+ switch (fe->dtv_property_cache.delivery_system) {
+ case SYS_DVBT:
+ gpio = priv->cfg.gpio_dvbt;
+ break;
+ case SYS_DVBT2:
+ gpio = priv->cfg.gpio_dvbt2;
+ break;
+ case SYS_DVBC_ANNEX_AC:
+ gpio = priv->cfg.gpio_dvbc;
+ break;
+ default:
+ ret = -EINVAL;
+ goto error;
+ }
+
+ /* update GPIOs only when needed */
+ if (!memcmp(gpio, priv->gpio, sizeof(priv->gpio)))
+ return 0;
+
+ tmp0 = 0x00;
+ tmp1 = 0x00;
+ for (i = 0; i < sizeof(priv->gpio); i++) {
+ /* enable / disable */
+ if (gpio[i] & CXD2820R_GPIO_E)
+ tmp0 |= (2 << 6) >> (2 * i);
+ else
+ tmp0 |= (1 << 6) >> (2 * i);
+
+ /* input / output */
+ if (gpio[i] & CXD2820R_GPIO_I)
+ tmp1 |= (1 << (3 + i));
+ else
+ tmp1 |= (0 << (3 + i));
+
+ /* high / low */
+ if (gpio[i] & CXD2820R_GPIO_H)
+ tmp1 |= (1 << (0 + i));
+ else
+ tmp1 |= (0 << (0 + i));
+
+ dbg("%s: GPIO i=%d %02x %02x", __func__, i, tmp0, tmp1);
+ }
+
+ dbg("%s: wr gpio=%02x %02x", __func__, tmp0, tmp1);
+
+ /* write bits [7:2] */
+ ret = cxd2820r_wr_reg_mask(priv, 0x00089, tmp0, 0xfc);
+ if (ret)
+ goto error;
+
+ /* write bits [5:0] */
+ ret = cxd2820r_wr_reg_mask(priv, 0x0008e, tmp1, 0x3f);
+ if (ret)
+ goto error;
+
+ memcpy(priv->gpio, gpio, sizeof(priv->gpio));
+
+ return ret;
+error:
+ dbg("%s: failed:%d", __func__, ret);
+ return ret;
+}
+
+/* lock FE */
+static int cxd2820r_lock(struct cxd2820r_priv *priv, int active_fe)
+{
+ int ret = 0;
+ dbg("%s: active_fe=%d", __func__, active_fe);
+
+ mutex_lock(&priv->fe_lock);
+
+ /* -1=NONE, 0=DVB-T/T2, 1=DVB-C */
+ if (priv->active_fe == active_fe)
+ ;
+ else if (priv->active_fe == -1)
+ priv->active_fe = active_fe;
+ else
+ ret = -EBUSY;
+
+ mutex_unlock(&priv->fe_lock);
+
+ return ret;
+}
+
+/* unlock FE */
+static void cxd2820r_unlock(struct cxd2820r_priv *priv, int active_fe)
+{
+ dbg("%s: active_fe=%d", __func__, active_fe);
+
+ mutex_lock(&priv->fe_lock);
+
+ /* -1=NONE, 0=DVB-T/T2, 1=DVB-C */
+ if (priv->active_fe == active_fe)
+ priv->active_fe = -1;
+
+ mutex_unlock(&priv->fe_lock);
+
+ return;
+}
+
+/* 64 bit div with round closest, like DIV_ROUND_CLOSEST but 64 bit */
+u32 cxd2820r_div_u64_round_closest(u64 dividend, u32 divisor)
+{
+ return div_u64(dividend + (divisor / 2), divisor);
+}
+
+static int cxd2820r_set_frontend(struct dvb_frontend *fe,
+ struct dvb_frontend_parameters *p)
+{
+ struct cxd2820r_priv *priv = fe->demodulator_priv;
+ struct dtv_frontend_properties *c = &fe->dtv_property_cache;
+ int ret;
+ dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
+
+ if (fe->ops.info.type == FE_OFDM) {
+ /* DVB-T/T2 */
+ ret = cxd2820r_lock(priv, 0);
+ if (ret)
+ return ret;
+
+ switch (priv->delivery_system) {
+ case SYS_UNDEFINED:
+ if (c->delivery_system == SYS_DVBT) {
+ /* SLEEP => DVB-T */
+ ret = cxd2820r_set_frontend_t(fe, p);
+ } else {
+ /* SLEEP => DVB-T2 */
+ ret = cxd2820r_set_frontend_t2(fe, p);
+ }
+ break;
+ case SYS_DVBT:
+ if (c->delivery_system == SYS_DVBT) {
+ /* DVB-T => DVB-T */
+ ret = cxd2820r_set_frontend_t(fe, p);
+ } else if (c->delivery_system == SYS_DVBT2) {
+ /* DVB-T => DVB-T2 */
+ ret = cxd2820r_sleep_t(fe);
+ ret = cxd2820r_set_frontend_t2(fe, p);
+ }
+ break;
+ case SYS_DVBT2:
+ if (c->delivery_system == SYS_DVBT2) {
+ /* DVB-T2 => DVB-T2 */
+ ret = cxd2820r_set_frontend_t2(fe, p);
+ } else if (c->delivery_system == SYS_DVBT) {
+ /* DVB-T2 => DVB-T */
+ ret = cxd2820r_sleep_t2(fe);
+ ret = cxd2820r_set_frontend_t(fe, p);
+ }
+ break;
+ default:
+ dbg("%s: error state=%d", __func__,
+ priv->delivery_system);
+ ret = -EINVAL;
+ }
+ } else {
+ /* DVB-C */
+ ret = cxd2820r_lock(priv, 1);
+ if (ret)
+ return ret;
+
+ ret = cxd2820r_set_frontend_c(fe, p);
+ }
+
+ return ret;
+}
+
+static int cxd2820r_read_status(struct dvb_frontend *fe, fe_status_t *status)
+{
+ struct cxd2820r_priv *priv = fe->demodulator_priv;
+ int ret;
+ dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
+
+ if (fe->ops.info.type == FE_OFDM) {
+ /* DVB-T/T2 */
+ ret = cxd2820r_lock(priv, 0);
+ if (ret)
+ return ret;
+
+ switch (fe->dtv_property_cache.delivery_system) {
+ case SYS_DVBT:
+ ret = cxd2820r_read_status_t(fe, status);
+ break;
+ case SYS_DVBT2:
+ ret = cxd2820r_read_status_t2(fe, status);
+ break;
+ default:
+ ret = -EINVAL;
+ }
+ } else {
+ /* DVB-C */
+ ret = cxd2820r_lock(priv, 1);
+ if (ret)
+ return ret;
+
+ ret = cxd2820r_read_status_c(fe, status);
+ }
+
+ return ret;
+}
+
+static int cxd2820r_get_frontend(struct dvb_frontend *fe,
+ struct dvb_frontend_parameters *p)
+{
+ struct cxd2820r_priv *priv = fe->demodulator_priv;
+ int ret;
+ dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
+
+ if (fe->ops.info.type == FE_OFDM) {
+ /* DVB-T/T2 */
+ ret = cxd2820r_lock(priv, 0);
+ if (ret)
+ return ret;
+
+ switch (fe->dtv_property_cache.delivery_system) {
+ case SYS_DVBT:
+ ret = cxd2820r_get_frontend_t(fe, p);
+ break;
+ case SYS_DVBT2:
+ ret = cxd2820r_get_frontend_t2(fe, p);
+ break;
+ default:
+ ret = -EINVAL;
+ }
+ } else {
+ /* DVB-C */
+ ret = cxd2820r_lock(priv, 1);
+ if (ret)
+ return ret;
+
+ ret = cxd2820r_get_frontend_c(fe, p);
+ }
+
+ return ret;
+}
+
+static int cxd2820r_read_ber(struct dvb_frontend *fe, u32 *ber)
+{
+ struct cxd2820r_priv *priv = fe->demodulator_priv;
+ int ret;
+ dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
+
+ if (fe->ops.info.type == FE_OFDM) {
+ /* DVB-T/T2 */
+ ret = cxd2820r_lock(priv, 0);
+ if (ret)
+ return ret;
+
+ switch (fe->dtv_property_cache.delivery_system) {
+ case SYS_DVBT:
+ ret = cxd2820r_read_ber_t(fe, ber);
+ break;
+ case SYS_DVBT2:
+ ret = cxd2820r_read_ber_t2(fe, ber);
+ break;
+ default:
+ ret = -EINVAL;
+ }
+ } else {
+ /* DVB-C */
+ ret = cxd2820r_lock(priv, 1);
+ if (ret)
+ return ret;
+
+ ret = cxd2820r_read_ber_c(fe, ber);
+ }
+
+ return ret;
+}
+
+static int cxd2820r_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
+{
+ struct cxd2820r_priv *priv = fe->demodulator_priv;
+ int ret;
+ dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
+
+ if (fe->ops.info.type == FE_OFDM) {
+ /* DVB-T/T2 */
+ ret = cxd2820r_lock(priv, 0);
+ if (ret)
+ return ret;
+
+ switch (fe->dtv_property_cache.delivery_system) {
+ case SYS_DVBT:
+ ret = cxd2820r_read_signal_strength_t(fe, strength);
+ break;
+ case SYS_DVBT2:
+ ret = cxd2820r_read_signal_strength_t2(fe, strength);
+ break;
+ default:
+ ret = -EINVAL;
+ }
+ } else {
+ /* DVB-C */
+ ret = cxd2820r_lock(priv, 1);
+ if (ret)
+ return ret;
+
+ ret = cxd2820r_read_signal_strength_c(fe, strength);
+ }
+
+ return ret;
+}
+
+static int cxd2820r_read_snr(struct dvb_frontend *fe, u16 *snr)
+{
+ struct cxd2820r_priv *priv = fe->demodulator_priv;
+ int ret;
+ dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
+
+ if (fe->ops.info.type == FE_OFDM) {
+ /* DVB-T/T2 */
+ ret = cxd2820r_lock(priv, 0);
+ if (ret)
+ return ret;
+
+ switch (fe->dtv_property_cache.delivery_system) {
+ case SYS_DVBT:
+ ret = cxd2820r_read_snr_t(fe, snr);
+ break;
+ case SYS_DVBT2:
+ ret = cxd2820r_read_snr_t2(fe, snr);
+ break;
+ default:
+ ret = -EINVAL;
+ }
+ } else {
+ /* DVB-C */
+ ret = cxd2820r_lock(priv, 1);
+ if (ret)
+ return ret;
+
+ ret = cxd2820r_read_snr_c(fe, snr);
+ }
+
+ return ret;
+}
+
+static int cxd2820r_read_ucblocks(struct dvb_frontend *fe, u32 *ucblocks)
+{
+ struct cxd2820r_priv *priv = fe->demodulator_priv;
+ int ret;
+ dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
+
+ if (fe->ops.info.type == FE_OFDM) {
+ /* DVB-T/T2 */
+ ret = cxd2820r_lock(priv, 0);
+ if (ret)
+ return ret;
+
+ switch (fe->dtv_property_cache.delivery_system) {
+ case SYS_DVBT:
+ ret = cxd2820r_read_ucblocks_t(fe, ucblocks);
+ break;
+ case SYS_DVBT2:
+ ret = cxd2820r_read_ucblocks_t2(fe, ucblocks);
+ break;
+ default:
+ ret = -EINVAL;
+ }
+ } else {
+ /* DVB-C */
+ ret = cxd2820r_lock(priv, 1);
+ if (ret)
+ return ret;
+
+ ret = cxd2820r_read_ucblocks_c(fe, ucblocks);
+ }
+
+ return ret;
+}
+
+static int cxd2820r_init(struct dvb_frontend *fe)
+{
+ struct cxd2820r_priv *priv = fe->demodulator_priv;
+ int ret;
+ dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
+
+ priv->delivery_system = SYS_UNDEFINED;
+ /* delivery system is unknown at that (init) phase */
+
+ if (fe->ops.info.type == FE_OFDM) {
+ /* DVB-T/T2 */
+ ret = cxd2820r_lock(priv, 0);
+ if (ret)
+ return ret;
+
+ ret = cxd2820r_init_t(fe);
+ } else {
+ /* DVB-C */
+ ret = cxd2820r_lock(priv, 1);
+ if (ret)
+ return ret;
+
+ ret = cxd2820r_init_c(fe);
+ }
+
+ return ret;
+}
+
+static int cxd2820r_sleep(struct dvb_frontend *fe)
+{
+ struct cxd2820r_priv *priv = fe->demodulator_priv;
+ int ret;
+ dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
+
+ if (fe->ops.info.type == FE_OFDM) {
+ /* DVB-T/T2 */
+ ret = cxd2820r_lock(priv, 0);
+ if (ret)
+ return ret;
+
+ switch (fe->dtv_property_cache.delivery_system) {
+ case SYS_DVBT:
+ ret = cxd2820r_sleep_t(fe);
+ break;
+ case SYS_DVBT2:
+ ret = cxd2820r_sleep_t2(fe);
+ break;
+ default:
+ ret = -EINVAL;
+ }
+
+ cxd2820r_unlock(priv, 0);
+ } else {
+ /* DVB-C */
+ ret = cxd2820r_lock(priv, 1);
+ if (ret)
+ return ret;
+
+ ret = cxd2820r_sleep_c(fe);
+
+ cxd2820r_unlock(priv, 1);
+ }
+
+ return ret;
+}
+
+static int cxd2820r_get_tune_settings(struct dvb_frontend *fe,
+ struct dvb_frontend_tune_settings *s)
+{
+ struct cxd2820r_priv *priv = fe->demodulator_priv;
+ int ret;
+ dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
+
+ if (fe->ops.info.type == FE_OFDM) {
+ /* DVB-T/T2 */
+ ret = cxd2820r_lock(priv, 0);
+ if (ret)
+ return ret;
+
+ switch (fe->dtv_property_cache.delivery_system) {
+ case SYS_DVBT:
+ ret = cxd2820r_get_tune_settings_t(fe, s);
+ break;
+ case SYS_DVBT2:
+ ret = cxd2820r_get_tune_settings_t2(fe, s);
+ break;
+ default:
+ ret = -EINVAL;
+ }
+ } else {
+ /* DVB-C */
+ ret = cxd2820r_lock(priv, 1);
+ if (ret)
+ return ret;
+
+ ret = cxd2820r_get_tune_settings_c(fe, s);
+ }
+
+ return ret;
+}
+
+static enum dvbfe_search cxd2820r_search(struct dvb_frontend *fe,
+ struct dvb_frontend_parameters *p)
+{
+ struct cxd2820r_priv *priv = fe->demodulator_priv;
+ struct dtv_frontend_properties *c = &fe->dtv_property_cache;
+ int ret, i;
+ fe_status_t status = 0;
+ dbg("%s: delsys=%d", __func__, fe->dtv_property_cache.delivery_system);
+
+ /* switch between DVB-T and DVB-T2 when tune fails */
+ if (priv->last_tune_failed) {
+ if (priv->delivery_system == SYS_DVBT)
+ c->delivery_system = SYS_DVBT2;
+ else
+ c->delivery_system = SYS_DVBT;
+ }
+
+ /* set frontend */
+ ret = cxd2820r_set_frontend(fe, p);
+ if (ret)
+ goto error;
+
+
+ /* frontend lock wait loop count */
+ switch (priv->delivery_system) {
+ case SYS_DVBT:
+ i = 20;
+ break;
+ case SYS_DVBT2:
+ i = 40;
+ break;
+ case SYS_UNDEFINED:
+ default:
+ i = 0;
+ break;
+ }
+
+ /* wait frontend lock */
+ for (; i > 0; i--) {
+ dbg("%s: LOOP=%d", __func__, i);
+ msleep(50);
+ ret = cxd2820r_read_status(fe, &status);
+ if (ret)
+ goto error;
+
+ if (status & FE_HAS_SIGNAL)
+ break;
+ }
+
+ /* check if we have a valid signal */
+ if (status) {
+ priv->last_tune_failed = 0;
+ return DVBFE_ALGO_SEARCH_SUCCESS;
+ } else {
+ priv->last_tune_failed = 1;
+ return DVBFE_ALGO_SEARCH_AGAIN;
+ }
+
+error:
+ dbg("%s: failed:%d", __func__, ret);
+ return DVBFE_ALGO_SEARCH_ERROR;
+}
+
+static int cxd2820r_get_frontend_algo(struct dvb_frontend *fe)
+{
+ return DVBFE_ALGO_CUSTOM;
+}
+
+static void cxd2820r_release(struct dvb_frontend *fe)
+{
+ struct cxd2820r_priv *priv = fe->demodulator_priv;
+ dbg("%s", __func__);
+
+ if (fe->ops.info.type == FE_OFDM) {
+ i2c_del_adapter(&priv->tuner_i2c_adapter);
+ kfree(priv);
+ }
+
+ return;
+}
+
+static u32 cxd2820r_tuner_i2c_func(struct i2c_adapter *adapter)
+{
+ return I2C_FUNC_I2C;
+}
+
+static int cxd2820r_tuner_i2c_xfer(struct i2c_adapter *i2c_adap,
+ struct i2c_msg msg[], int num)
+{
+ struct cxd2820r_priv *priv = i2c_get_adapdata(i2c_adap);
+ u8 obuf[msg[0].len + 2];
+ struct i2c_msg msg2[2] = {
+ {
+ .addr = priv->cfg.i2c_address,
+ .flags = 0,
+ .len = sizeof(obuf),
+ .buf = obuf,
+ }, {
+ .addr = priv->cfg.i2c_address,
+ .flags = I2C_M_RD,
+ .len = msg[1].len,
+ .buf = msg[1].buf,
+ }
+ };
+
+ obuf[0] = 0x09;
+ obuf[1] = (msg[0].addr << 1);
+ if (num == 2) { /* I2C read */
+ obuf[1] = (msg[0].addr << 1) | I2C_M_RD; /* I2C RD flag */
+ msg2[0].len = sizeof(obuf) - 1; /* maybe HW bug ? */
+ }
+ memcpy(&obuf[2], msg[0].buf, msg[0].len);
+
+ return i2c_transfer(priv->i2c, msg2, num);
+}
+
+static struct i2c_algorithm cxd2820r_tuner_i2c_algo = {
+ .master_xfer = cxd2820r_tuner_i2c_xfer,
+ .functionality = cxd2820r_tuner_i2c_func,
+};
+
+struct i2c_adapter *cxd2820r_get_tuner_i2c_adapter(struct dvb_frontend *fe)
+{
+ struct cxd2820r_priv *priv = fe->demodulator_priv;
+ return &priv->tuner_i2c_adapter;
+}
+EXPORT_SYMBOL(cxd2820r_get_tuner_i2c_adapter);
+
+static struct dvb_frontend_ops cxd2820r_ops[2];
+
+struct dvb_frontend *cxd2820r_attach(const struct cxd2820r_config *cfg,
+ struct i2c_adapter *i2c, struct dvb_frontend *fe)
+{
+ int ret;
+ struct cxd2820r_priv *priv = NULL;
+ u8 tmp;
+
+ if (fe == NULL) {
+ /* FE0 */
+ /* allocate memory for the internal priv */
+ priv = kzalloc(sizeof(struct cxd2820r_priv), GFP_KERNEL);
+ if (priv == NULL)
+ goto error;
+
+ /* setup the priv */
+ priv->i2c = i2c;
+ memcpy(&priv->cfg, cfg, sizeof(struct cxd2820r_config));
+ mutex_init(&priv->fe_lock);
+
+ priv->active_fe = -1; /* NONE */
+
+ /* check if the demod is there */
+ priv->bank[0] = priv->bank[1] = 0xff;
+ ret = cxd2820r_rd_reg(priv, 0x000fd, &tmp);
+ dbg("%s: chip id=%02x", __func__, tmp);
+ if (ret || tmp != 0xe1)
+ goto error;
+
+ /* create frontends */
+ memcpy(&priv->fe[0].ops, &cxd2820r_ops[0],
+ sizeof(struct dvb_frontend_ops));
+ memcpy(&priv->fe[1].ops, &cxd2820r_ops[1],
+ sizeof(struct dvb_frontend_ops));
+
+ priv->fe[0].demodulator_priv = priv;
+ priv->fe[1].demodulator_priv = priv;
+
+ /* create tuner i2c adapter */
+ strlcpy(priv->tuner_i2c_adapter.name,
+ "CXD2820R tuner I2C adapter",
+ sizeof(priv->tuner_i2c_adapter.name));
+ priv->tuner_i2c_adapter.algo = &cxd2820r_tuner_i2c_algo;
+ priv->tuner_i2c_adapter.algo_data = NULL;
+ i2c_set_adapdata(&priv->tuner_i2c_adapter, priv);
+ if (i2c_add_adapter(&priv->tuner_i2c_adapter) < 0) {
+ err("tuner I2C bus could not be initialized");
+ goto error;
+ }
+
+ return &priv->fe[0];
+
+ } else {
+ /* FE1: FE0 given as pointer, just return FE1 we have
+ * already created */
+ priv = fe->demodulator_priv;
+ return &priv->fe[1];
+ }
+
+error:
+ kfree(priv);
+ return NULL;
+}
+EXPORT_SYMBOL(cxd2820r_attach);
+
+static struct dvb_frontend_ops cxd2820r_ops[2] = {
+ {
+ /* DVB-T/T2 */
+ .info = {
+ .name = "Sony CXD2820R (DVB-T/T2)",
+ .type = FE_OFDM,
+ .caps =
+ FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
+ FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 |
+ FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
+ FE_CAN_QPSK | FE_CAN_QAM_16 |
+ FE_CAN_QAM_64 | FE_CAN_QAM_256 |
+ FE_CAN_QAM_AUTO |
+ FE_CAN_TRANSMISSION_MODE_AUTO |
+ FE_CAN_GUARD_INTERVAL_AUTO |
+ FE_CAN_HIERARCHY_AUTO |
+ FE_CAN_MUTE_TS |
+ FE_CAN_2G_MODULATION
+ },
+
+ .release = cxd2820r_release,
+ .init = cxd2820r_init,
+ .sleep = cxd2820r_sleep,
+
+ .get_tune_settings = cxd2820r_get_tune_settings,
+
+ .get_frontend = cxd2820r_get_frontend,
+
+ .get_frontend_algo = cxd2820r_get_frontend_algo,
+ .search = cxd2820r_search,
+
+ .read_status = cxd2820r_read_status,
+ .read_snr = cxd2820r_read_snr,
+ .read_ber = cxd2820r_read_ber,
+ .read_ucblocks = cxd2820r_read_ucblocks,
+ .read_signal_strength = cxd2820r_read_signal_strength,
+ },
+ {
+ /* DVB-C */
+ .info = {
+ .name = "Sony CXD2820R (DVB-C)",
+ .type = FE_QAM,
+ .caps =
+ FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 |
+ FE_CAN_QAM_128 | FE_CAN_QAM_256 |
+ FE_CAN_FEC_AUTO
+ },
+
+ .release = cxd2820r_release,
+ .init = cxd2820r_init,
+ .sleep = cxd2820r_sleep,
+
+ .get_tune_settings = cxd2820r_get_tune_settings,
+
+ .set_frontend = cxd2820r_set_frontend,
+ .get_frontend = cxd2820r_get_frontend,
+
+ .read_status = cxd2820r_read_status,
+ .read_snr = cxd2820r_read_snr,
+ .read_ber = cxd2820r_read_ber,
+ .read_ucblocks = cxd2820r_read_ucblocks,
+ .read_signal_strength = cxd2820r_read_signal_strength,
+ },
+};
+
+
+MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
+MODULE_DESCRIPTION("Sony CXD2820R demodulator driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/cxd2820r_priv.h b/drivers/media/dvb/frontends/cxd2820r_priv.h
new file mode 100644
index 0000000..25adbee
--- /dev/null
+++ b/drivers/media/dvb/frontends/cxd2820r_priv.h
@@ -0,0 +1,166 @@
+/*
+ * Sony CXD2820R demodulator driver
+ *
+ * Copyright (C) 2010 Antti Palosaari <crope@iki.fi>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+
+#ifndef CXD2820R_PRIV_H
+#define CXD2820R_PRIV_H
+
+#include <linux/dvb/version.h>
+#include "dvb_frontend.h"
+#include "dvb_math.h"
+#include "cxd2820r.h"
+
+#define LOG_PREFIX "cxd2820r"
+
+#undef dbg
+#define dbg(f, arg...) \
+ if (cxd2820r_debug) \
+ printk(KERN_INFO LOG_PREFIX": " f "\n" , ## arg)
+#undef err
+#define err(f, arg...) printk(KERN_ERR LOG_PREFIX": " f "\n" , ## arg)
+#undef info
+#define info(f, arg...) printk(KERN_INFO LOG_PREFIX": " f "\n" , ## arg)
+#undef warn
+#define warn(f, arg...) printk(KERN_WARNING LOG_PREFIX": " f "\n" , ## arg)
+
+struct reg_val_mask {
+ u32 reg;
+ u8 val;
+ u8 mask;
+};
+
+struct cxd2820r_priv {
+ struct i2c_adapter *i2c;
+ struct dvb_frontend fe[2];
+ struct cxd2820r_config cfg;
+ struct i2c_adapter tuner_i2c_adapter;
+
+ struct mutex fe_lock; /* FE lock */
+ int active_fe:2; /* FE lock, -1=NONE, 0=DVB-T/T2, 1=DVB-C */
+
+ int ber_running:1;
+
+ u8 bank[2];
+ u8 gpio[3];
+
+ fe_delivery_system_t delivery_system;
+ int last_tune_failed:1; /* for switch between T and T2 tune */
+};
+
+/* cxd2820r_core.c */
+
+extern int cxd2820r_debug;
+
+int cxd2820r_gpio(struct dvb_frontend *fe);
+
+int cxd2820r_wr_reg_mask(struct cxd2820r_priv *priv, u32 reg, u8 val,
+ u8 mask);
+
+int cxd2820r_wr_regs(struct cxd2820r_priv *priv, u32 reginfo, u8 *val,
+ int len);
+
+u32 cxd2820r_div_u64_round_closest(u64 dividend, u32 divisor);
+
+int cxd2820r_wr_regs(struct cxd2820r_priv *priv, u32 reginfo, u8 *val,
+ int len);
+
+int cxd2820r_rd_regs(struct cxd2820r_priv *priv, u32 reginfo, u8 *val,
+ int len);
+
+int cxd2820r_wr_reg(struct cxd2820r_priv *priv, u32 reg, u8 val);
+
+int cxd2820r_rd_reg(struct cxd2820r_priv *priv, u32 reg, u8 *val);
+
+/* cxd2820r_c.c */
+
+int cxd2820r_get_frontend_c(struct dvb_frontend *fe,
+ struct dvb_frontend_parameters *p);
+
+int cxd2820r_set_frontend_c(struct dvb_frontend *fe,
+ struct dvb_frontend_parameters *params);
+
+int cxd2820r_read_status_c(struct dvb_frontend *fe, fe_status_t *status);
+
+int cxd2820r_read_ber_c(struct dvb_frontend *fe, u32 *ber);
+
+int cxd2820r_read_signal_strength_c(struct dvb_frontend *fe, u16 *strength);
+
+int cxd2820r_read_snr_c(struct dvb_frontend *fe, u16 *snr);
+
+int cxd2820r_read_ucblocks_c(struct dvb_frontend *fe, u32 *ucblocks);
+
+int cxd2820r_init_c(struct dvb_frontend *fe);
+
+int cxd2820r_sleep_c(struct dvb_frontend *fe);
+
+int cxd2820r_get_tune_settings_c(struct dvb_frontend *fe,
+ struct dvb_frontend_tune_settings *s);
+
+/* cxd2820r_t.c */
+
+int cxd2820r_get_frontend_t(struct dvb_frontend *fe,
+ struct dvb_frontend_parameters *p);
+
+int cxd2820r_set_frontend_t(struct dvb_frontend *fe,
+ struct dvb_frontend_parameters *params);
+
+int cxd2820r_read_status_t(struct dvb_frontend *fe, fe_status_t *status);
+
+int cxd2820r_read_ber_t(struct dvb_frontend *fe, u32 *ber);
+
+int cxd2820r_read_signal_strength_t(struct dvb_frontend *fe, u16 *strength);
+
+int cxd2820r_read_snr_t(struct dvb_frontend *fe, u16 *snr);
+
+int cxd2820r_read_ucblocks_t(struct dvb_frontend *fe, u32 *ucblocks);
+
+int cxd2820r_init_t(struct dvb_frontend *fe);
+
+int cxd2820r_sleep_t(struct dvb_frontend *fe);
+
+int cxd2820r_get_tune_settings_t(struct dvb_frontend *fe,
+ struct dvb_frontend_tune_settings *s);
+
+/* cxd2820r_t2.c */
+
+int cxd2820r_get_frontend_t2(struct dvb_frontend *fe,
+ struct dvb_frontend_parameters *p);
+
+int cxd2820r_set_frontend_t2(struct dvb_frontend *fe,
+ struct dvb_frontend_parameters *params);
+
+int cxd2820r_read_status_t2(struct dvb_frontend *fe, fe_status_t *status);
+
+int cxd2820r_read_ber_t2(struct dvb_frontend *fe, u32 *ber);
+
+int cxd2820r_read_signal_strength_t2(struct dvb_frontend *fe, u16 *strength);
+
+int cxd2820r_read_snr_t2(struct dvb_frontend *fe, u16 *snr);
+
+int cxd2820r_read_ucblocks_t2(struct dvb_frontend *fe, u32 *ucblocks);
+
+int cxd2820r_init_t2(struct dvb_frontend *fe);
+
+int cxd2820r_sleep_t2(struct dvb_frontend *fe);
+
+int cxd2820r_get_tune_settings_t2(struct dvb_frontend *fe,
+ struct dvb_frontend_tune_settings *s);
+
+#endif /* CXD2820R_PRIV_H */
diff --git a/drivers/media/dvb/frontends/cxd2820r_t.c b/drivers/media/dvb/frontends/cxd2820r_t.c
new file mode 100644
index 0000000..6582564
--- /dev/null
+++ b/drivers/media/dvb/frontends/cxd2820r_t.c
@@ -0,0 +1,449 @@
+/*
+ * Sony CXD2820R demodulator driver
+ *
+ * Copyright (C) 2010 Antti Palosaari <crope@iki.fi>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+
+#include "cxd2820r_priv.h"
+
+int cxd2820r_set_frontend_t(struct dvb_frontend *fe,
+ struct dvb_frontend_parameters *p)
+{
+ struct cxd2820r_priv *priv = fe->demodulator_priv;
+ struct dtv_frontend_properties *c = &fe->dtv_property_cache;
+ int ret, i;
+ u32 if_khz, if_ctl;
+ u64 num;
+ u8 buf[3], bw_param;
+ u8 bw_params1[][5] = {
+ { 0x17, 0xea, 0xaa, 0xaa, 0xaa }, /* 6 MHz */
+ { 0x14, 0x80, 0x00, 0x00, 0x00 }, /* 7 MHz */
+ { 0x11, 0xf0, 0x00, 0x00, 0x00 }, /* 8 MHz */
+ };
+ u8 bw_params2[][2] = {
+ { 0x1f, 0xdc }, /* 6 MHz */
+ { 0x12, 0xf8 }, /* 7 MHz */
+ { 0x01, 0xe0 }, /* 8 MHz */
+ };
+ struct reg_val_mask tab[] = {
+ { 0x00080, 0x00, 0xff },
+ { 0x00081, 0x03, 0xff },
+ { 0x00085, 0x07, 0xff },
+ { 0x00088, 0x01, 0xff },
+
+ { 0x00070, priv->cfg.ts_mode, 0xff },
+ { 0x000cb, priv->cfg.if_agc_polarity << 6, 0x40 },
+ { 0x000a5, 0x00, 0x01 },
+ { 0x00082, 0x20, 0x60 },
+ { 0x000c2, 0xc3, 0xff },
+ { 0x0016a, 0x50, 0xff },
+ { 0x00427, 0x41, 0xff },
+ };
+
+ dbg("%s: RF=%d BW=%d", __func__, c->frequency, c->bandwidth_hz);
+
+ /* update GPIOs */
+ ret = cxd2820r_gpio(fe);
+ if (ret)
+ goto error;
+
+ /* program tuner */
+ if (fe->ops.tuner_ops.set_params)
+ fe->ops.tuner_ops.set_params(fe, p);
+
+ if (priv->delivery_system != SYS_DVBT) {
+ for (i = 0; i < ARRAY_SIZE(tab); i++) {
+ ret = cxd2820r_wr_reg_mask(priv, tab[i].reg,
+ tab[i].val, tab[i].mask);
+ if (ret)
+ goto error;
+ }
+ }
+
+ priv->delivery_system = SYS_DVBT;
+ priv->ber_running = 0; /* tune stops BER counter */
+
+ switch (c->bandwidth_hz) {
+ case 6000000:
+ if_khz = priv->cfg.if_dvbt_6;
+ i = 0;
+ bw_param = 2;
+ break;
+ case 7000000:
+ if_khz = priv->cfg.if_dvbt_7;
+ i = 1;
+ bw_param = 1;
+ break;
+ case 8000000:
+ if_khz = priv->cfg.if_dvbt_8;
+ i = 2;
+ bw_param = 0;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ num = if_khz;
+ num *= 0x1000000;
+ if_ctl = cxd2820r_div_u64_round_closest(num, 41000);
+ buf[0] = ((if_ctl >> 16) & 0xff);
+ buf[1] = ((if_ctl >> 8) & 0xff);
+ buf[2] = ((if_ctl >> 0) & 0xff);
+
+ ret = cxd2820r_wr_regs(priv, 0x000b6, buf, 3);
+ if (ret)
+ goto error;
+
+ ret = cxd2820r_wr_regs(priv, 0x0009f, bw_params1[i], 5);
+ if (ret)
+ goto error;
+
+ ret = cxd2820r_wr_reg_mask(priv, 0x000d7, bw_param << 6, 0xc0);
+ if (ret)
+ goto error;
+
+ ret = cxd2820r_wr_regs(priv, 0x000d9, bw_params2[i], 2);
+ if (ret)
+ goto error;
+
+ ret = cxd2820r_wr_reg(priv, 0x000ff, 0x08);
+ if (ret)
+ goto error;
+
+ ret = cxd2820r_wr_reg(priv, 0x000fe, 0x01);
+ if (ret)
+ goto error;
+
+ return ret;
+error:
+ dbg("%s: failed:%d", __func__, ret);
+ return ret;
+}
+
+int cxd2820r_get_frontend_t(struct dvb_frontend *fe,
+ struct dvb_frontend_parameters *p)
+{
+ struct cxd2820r_priv *priv = fe->demodulator_priv;
+ struct dtv_frontend_properties *c = &fe->dtv_property_cache;
+ int ret;
+ u8 buf[2];
+
+ ret = cxd2820r_rd_regs(priv, 0x0002f, buf, sizeof(buf));
+ if (ret)
+ goto error;
+
+ switch ((buf[0] >> 6) & 0x03) {
+ case 0:
+ c->modulation = QPSK;
+ break;
+ case 1:
+ c->modulation = QAM_16;
+ break;
+ case 2:
+ c->modulation = QAM_64;
+ break;
+ }
+
+ switch ((buf[1] >> 1) & 0x03) {
+ case 0:
+ c->transmission_mode = TRANSMISSION_MODE_2K;
+ break;
+ case 1:
+ c->transmission_mode = TRANSMISSION_MODE_8K;
+ break;
+ }
+
+ switch ((buf[1] >> 3) & 0x03) {
+ case 0:
+ c->guard_interval = GUARD_INTERVAL_1_32;
+ break;
+ case 1:
+ c->guard_interval = GUARD_INTERVAL_1_16;
+ break;
+ case 2:
+ c->guard_interval = GUARD_INTERVAL_1_8;
+ break;
+ case 3:
+ c->guard_interval = GUARD_INTERVAL_1_4;
+ break;
+ }
+
+ switch ((buf[0] >> 3) & 0x07) {
+ case 0:
+ c->hierarchy = HIERARCHY_NONE;
+ break;
+ case 1:
+ c->hierarchy = HIERARCHY_1;
+ break;
+ case 2:
+ c->hierarchy = HIERARCHY_2;
+ break;
+ case 3:
+ c->hierarchy = HIERARCHY_4;
+ break;
+ }
+
+ switch ((buf[0] >> 0) & 0x07) {
+ case 0:
+ c->code_rate_HP = FEC_1_2;
+ break;
+ case 1:
+ c->code_rate_HP = FEC_2_3;
+ break;
+ case 2:
+ c->code_rate_HP = FEC_3_4;
+ break;
+ case 3:
+ c->code_rate_HP = FEC_5_6;
+ break;
+ case 4:
+ c->code_rate_HP = FEC_7_8;
+ break;
+ }
+
+ switch ((buf[1] >> 5) & 0x07) {
+ case 0:
+ c->code_rate_LP = FEC_1_2;
+ break;
+ case 1:
+ c->code_rate_LP = FEC_2_3;
+ break;
+ case 2:
+ c->code_rate_LP = FEC_3_4;
+ break;
+ case 3:
+ c->code_rate_LP = FEC_5_6;
+ break;
+ case 4:
+ c->code_rate_LP = FEC_7_8;
+ break;
+ }
+
+ ret = cxd2820r_rd_reg(priv, 0x007c6, &buf[0]);
+ if (ret)
+ goto error;
+
+ switch ((buf[0] >> 0) & 0x01) {
+ case 0:
+ c->inversion = INVERSION_OFF;
+ break;
+ case 1:
+ c->inversion = INVERSION_ON;
+ break;
+ }
+
+ return ret;
+error:
+ dbg("%s: failed:%d", __func__, ret);
+ return ret;
+}
+
+int cxd2820r_read_ber_t(struct dvb_frontend *fe, u32 *ber)
+{
+ struct cxd2820r_priv *priv = fe->demodulator_priv;
+ int ret;
+ u8 buf[3], start_ber = 0;
+ *ber = 0;
+
+ if (priv->ber_running) {
+ ret = cxd2820r_rd_regs(priv, 0x00076, buf, sizeof(buf));
+ if (ret)
+ goto error;
+
+ if ((buf[2] >> 7) & 0x01 || (buf[2] >> 4) & 0x01) {
+ *ber = (buf[2] & 0x0f) << 16 | buf[1] << 8 | buf[0];
+ start_ber = 1;
+ }
+ } else {
+ priv->ber_running = 1;
+ start_ber = 1;
+ }
+
+ if (start_ber) {
+ /* (re)start BER */
+ ret = cxd2820r_wr_reg(priv, 0x00079, 0x01);
+ if (ret)
+ goto error;
+ }
+
+ return ret;
+error:
+ dbg("%s: failed:%d", __func__, ret);
+ return ret;
+}
+
+int cxd2820r_read_signal_strength_t(struct dvb_frontend *fe,
+ u16 *strength)
+{
+ struct cxd2820r_priv *priv = fe->demodulator_priv;
+ int ret;
+ u8 buf[2];
+ u16 tmp;
+
+ ret = cxd2820r_rd_regs(priv, 0x00026, buf, sizeof(buf));
+ if (ret)
+ goto error;
+
+ tmp = (buf[0] & 0x0f) << 8 | buf[1];
+ tmp = ~tmp & 0x0fff;
+
+ /* scale value to 0x0000-0xffff from 0x0000-0x0fff */
+ *strength = tmp * 0xffff / 0x0fff;
+
+ return ret;
+error:
+ dbg("%s: failed:%d", __func__, ret);
+ return ret;
+}
+
+int cxd2820r_read_snr_t(struct dvb_frontend *fe, u16 *snr)
+{
+ struct cxd2820r_priv *priv = fe->demodulator_priv;
+ int ret;
+ u8 buf[2];
+ u16 tmp;
+ /* report SNR in dB * 10 */
+
+ ret = cxd2820r_rd_regs(priv, 0x00028, buf, sizeof(buf));
+ if (ret)
+ goto error;
+
+ tmp = (buf[0] & 0x1f) << 8 | buf[1];
+ #define CXD2820R_LOG10_8_24 15151336 /* log10(8) << 24 */
+ if (tmp)
+ *snr = (intlog10(tmp) - CXD2820R_LOG10_8_24) / ((1 << 24)
+ / 100);
+ else
+ *snr = 0;
+
+ dbg("%s: dBx10=%d val=%04x", __func__, *snr, tmp);
+
+ return ret;
+error:
+ dbg("%s: failed:%d", __func__, ret);
+ return ret;
+}
+
+int cxd2820r_read_ucblocks_t(struct dvb_frontend *fe, u32 *ucblocks)
+{
+ *ucblocks = 0;
+ /* no way to read ? */
+ return 0;
+}
+
+int cxd2820r_read_status_t(struct dvb_frontend *fe, fe_status_t *status)
+{
+ struct cxd2820r_priv *priv = fe->demodulator_priv;
+ int ret;
+ u8 buf[4];
+ *status = 0;
+
+ ret = cxd2820r_rd_reg(priv, 0x00010, &buf[0]);
+ if (ret)
+ goto error;
+
+ if ((buf[0] & 0x07) == 6) {
+ ret = cxd2820r_rd_reg(priv, 0x00073, &buf[1]);
+ if (ret)
+ goto error;
+
+ if (((buf[1] >> 3) & 0x01) == 1) {
+ *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
+ FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
+ } else {
+ *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
+ FE_HAS_VITERBI | FE_HAS_SYNC;
+ }
+ } else {
+ ret = cxd2820r_rd_reg(priv, 0x00014, &buf[2]);
+ if (ret)
+ goto error;
+
+ if ((buf[2] & 0x0f) >= 4) {
+ ret = cxd2820r_rd_reg(priv, 0x00a14, &buf[3]);
+ if (ret)
+ goto error;
+
+ if (((buf[3] >> 4) & 0x01) == 1)
+ *status |= FE_HAS_SIGNAL;
+ }
+ }
+
+ dbg("%s: lock=%02x %02x %02x %02x", __func__,
+ buf[0], buf[1], buf[2], buf[3]);
+
+ return ret;
+error:
+ dbg("%s: failed:%d", __func__, ret);
+ return ret;
+}
+
+int cxd2820r_init_t(struct dvb_frontend *fe)
+{
+ struct cxd2820r_priv *priv = fe->demodulator_priv;
+ int ret;
+
+ ret = cxd2820r_wr_reg(priv, 0x00085, 0x07);
+ if (ret)
+ goto error;
+
+ return ret;
+error:
+ dbg("%s: failed:%d", __func__, ret);
+ return ret;
+}
+
+int cxd2820r_sleep_t(struct dvb_frontend *fe)
+{
+ struct cxd2820r_priv *priv = fe->demodulator_priv;
+ int ret, i;
+ struct reg_val_mask tab[] = {
+ { 0x000ff, 0x1f, 0xff },
+ { 0x00085, 0x00, 0xff },
+ { 0x00088, 0x01, 0xff },
+ { 0x00081, 0x00, 0xff },
+ { 0x00080, 0x00, 0xff },
+ };
+
+ dbg("%s", __func__);
+
+ priv->delivery_system = SYS_UNDEFINED;
+
+ for (i = 0; i < ARRAY_SIZE(tab); i++) {
+ ret = cxd2820r_wr_reg_mask(priv, tab[i].reg, tab[i].val,
+ tab[i].mask);
+ if (ret)
+ goto error;
+ }
+
+ return ret;
+error:
+ dbg("%s: failed:%d", __func__, ret);
+ return ret;
+}
+
+int cxd2820r_get_tune_settings_t(struct dvb_frontend *fe,
+ struct dvb_frontend_tune_settings *s)
+{
+ s->min_delay_ms = 500;
+ s->step_size = fe->ops.info.frequency_stepsize * 2;
+ s->max_drift = (fe->ops.info.frequency_stepsize * 2) + 1;
+
+ return 0;
+}
+
diff --git a/drivers/media/dvb/frontends/cxd2820r_t2.c b/drivers/media/dvb/frontends/cxd2820r_t2.c
new file mode 100644
index 0000000..c47b35c
--- /dev/null
+++ b/drivers/media/dvb/frontends/cxd2820r_t2.c
@@ -0,0 +1,423 @@
+/*
+ * Sony CXD2820R demodulator driver
+ *
+ * Copyright (C) 2010 Antti Palosaari <crope@iki.fi>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+
+#include "cxd2820r_priv.h"
+
+int cxd2820r_set_frontend_t2(struct dvb_frontend *fe,
+ struct dvb_frontend_parameters *params)
+{
+ struct cxd2820r_priv *priv = fe->demodulator_priv;
+ struct dtv_frontend_properties *c = &fe->dtv_property_cache;
+ int ret, i;
+ u32 if_khz, if_ctl;
+ u64 num;
+ u8 buf[3], bw_param;
+ u8 bw_params1[][5] = {
+ { 0x1c, 0xb3, 0x33, 0x33, 0x33 }, /* 5 MHz */
+ { 0x17, 0xea, 0xaa, 0xaa, 0xaa }, /* 6 MHz */
+ { 0x14, 0x80, 0x00, 0x00, 0x00 }, /* 7 MHz */
+ { 0x11, 0xf0, 0x00, 0x00, 0x00 }, /* 8 MHz */
+ };
+ struct reg_val_mask tab[] = {
+ { 0x00080, 0x02, 0xff },
+ { 0x00081, 0x20, 0xff },
+ { 0x00085, 0x07, 0xff },
+ { 0x00088, 0x01, 0xff },
+ { 0x02069, 0x01, 0xff },
+
+ { 0x0207f, 0x2a, 0xff },
+ { 0x02082, 0x0a, 0xff },
+ { 0x02083, 0x0a, 0xff },
+ { 0x020cb, priv->cfg.if_agc_polarity << 6, 0x40 },
+ { 0x02070, priv->cfg.ts_mode, 0xff },
+ { 0x020b5, priv->cfg.spec_inv << 4, 0x10 },
+ { 0x02567, 0x07, 0x0f },
+ { 0x02569, 0x03, 0x03 },
+ { 0x02595, 0x1a, 0xff },
+ { 0x02596, 0x50, 0xff },
+ { 0x02a8c, 0x00, 0xff },
+ { 0x02a8d, 0x34, 0xff },
+ { 0x02a45, 0x06, 0x07 },
+ { 0x03f10, 0x0d, 0xff },
+ { 0x03f11, 0x02, 0xff },
+ { 0x03f12, 0x01, 0xff },
+ { 0x03f23, 0x2c, 0xff },
+ { 0x03f51, 0x13, 0xff },
+ { 0x03f52, 0x01, 0xff },
+ { 0x03f53, 0x00, 0xff },
+ { 0x027e6, 0x14, 0xff },
+ { 0x02786, 0x02, 0x07 },
+ { 0x02787, 0x40, 0xe0 },
+ { 0x027ef, 0x10, 0x18 },
+ };
+
+ dbg("%s: RF=%d BW=%d", __func__, c->frequency, c->bandwidth_hz);
+
+ /* update GPIOs */
+ ret = cxd2820r_gpio(fe);
+ if (ret)
+ goto error;
+
+ /* program tuner */
+ if (fe->ops.tuner_ops.set_params)
+ fe->ops.tuner_ops.set_params(fe, params);
+
+ if (priv->delivery_system != SYS_DVBT2) {
+ for (i = 0; i < ARRAY_SIZE(tab); i++) {
+ ret = cxd2820r_wr_reg_mask(priv, tab[i].reg,
+ tab[i].val, tab[i].mask);
+ if (ret)
+ goto error;
+ }
+ }
+
+ priv->delivery_system = SYS_DVBT2;
+
+ switch (c->bandwidth_hz) {
+ case 5000000:
+ if_khz = priv->cfg.if_dvbt2_5;
+ i = 0;
+ bw_param = 3;
+ break;
+ case 6000000:
+ if_khz = priv->cfg.if_dvbt2_6;
+ i = 1;
+ bw_param = 2;
+ break;
+ case 7000000:
+ if_khz = priv->cfg.if_dvbt2_7;
+ i = 2;
+ bw_param = 1;
+ break;
+ case 8000000:
+ if_khz = priv->cfg.if_dvbt2_8;
+ i = 3;
+ bw_param = 0;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ num = if_khz;
+ num *= 0x1000000;
+ if_ctl = cxd2820r_div_u64_round_closest(num, 41000);
+ buf[0] = ((if_ctl >> 16) & 0xff);
+ buf[1] = ((if_ctl >> 8) & 0xff);
+ buf[2] = ((if_ctl >> 0) & 0xff);
+
+ ret = cxd2820r_wr_regs(priv, 0x020b6, buf, 3);
+ if (ret)
+ goto error;
+
+ ret = cxd2820r_wr_regs(priv, 0x0209f, bw_params1[i], 5);
+ if (ret)
+ goto error;
+
+ ret = cxd2820r_wr_reg_mask(priv, 0x020d7, bw_param << 6, 0xc0);
+ if (ret)
+ goto error;
+
+ ret = cxd2820r_wr_reg(priv, 0x000ff, 0x08);
+ if (ret)
+ goto error;
+
+ ret = cxd2820r_wr_reg(priv, 0x000fe, 0x01);
+ if (ret)
+ goto error;
+
+ return ret;
+error:
+ dbg("%s: failed:%d", __func__, ret);
+ return ret;
+
+}
+
+int cxd2820r_get_frontend_t2(struct dvb_frontend *fe,
+ struct dvb_frontend_parameters *p)
+{
+ struct cxd2820r_priv *priv = fe->demodulator_priv;
+ struct dtv_frontend_properties *c = &fe->dtv_property_cache;
+ int ret;
+ u8 buf[2];
+
+ ret = cxd2820r_rd_regs(priv, 0x0205c, buf, 2);
+ if (ret)
+ goto error;
+
+ switch ((buf[0] >> 0) & 0x07) {
+ case 0:
+ c->transmission_mode = TRANSMISSION_MODE_2K;
+ break;
+ case 1:
+ c->transmission_mode = TRANSMISSION_MODE_8K;
+ break;
+ case 2:
+ c->transmission_mode = TRANSMISSION_MODE_4K;
+ break;
+ case 3:
+ c->transmission_mode = TRANSMISSION_MODE_1K;
+ break;
+ case 4:
+ c->transmission_mode = TRANSMISSION_MODE_16K;
+ break;
+ case 5:
+ c->transmission_mode = TRANSMISSION_MODE_32K;
+ break;
+ }
+
+ switch ((buf[1] >> 4) & 0x07) {
+ case 0:
+ c->guard_interval = GUARD_INTERVAL_1_32;
+ break;
+ case 1:
+ c->guard_interval = GUARD_INTERVAL_1_16;
+ break;
+ case 2:
+ c->guard_interval = GUARD_INTERVAL_1_8;
+ break;
+ case 3:
+ c->guard_interval = GUARD_INTERVAL_1_4;
+ break;
+ case 4:
+ c->guard_interval = GUARD_INTERVAL_1_128;
+ break;
+ case 5:
+ c->guard_interval = GUARD_INTERVAL_19_128;
+ break;
+ case 6:
+ c->guard_interval = GUARD_INTERVAL_19_256;
+ break;
+ }
+
+ ret = cxd2820r_rd_regs(priv, 0x0225b, buf, 2);
+ if (ret)
+ goto error;
+
+ switch ((buf[0] >> 0) & 0x07) {
+ case 0:
+ c->fec_inner = FEC_1_2;
+ break;
+ case 1:
+ c->fec_inner = FEC_3_5;
+ break;
+ case 2:
+ c->fec_inner = FEC_2_3;
+ break;
+ case 3:
+ c->fec_inner = FEC_3_4;
+ break;
+ case 4:
+ c->fec_inner = FEC_4_5;
+ break;
+ case 5:
+ c->fec_inner = FEC_5_6;
+ break;
+ }
+
+ switch ((buf[1] >> 0) & 0x07) {
+ case 0:
+ c->modulation = QPSK;
+ break;
+ case 1:
+ c->modulation = QAM_16;
+ break;
+ case 2:
+ c->modulation = QAM_64;
+ break;
+ case 3:
+ c->modulation = QAM_256;
+ break;
+ }
+
+ ret = cxd2820r_rd_reg(priv, 0x020b5, &buf[0]);
+ if (ret)
+ goto error;
+
+ switch ((buf[0] >> 4) & 0x01) {
+ case 0:
+ c->inversion = INVERSION_OFF;
+ break;
+ case 1:
+ c->inversion = INVERSION_ON;
+ break;
+ }
+
+ return ret;
+error:
+ dbg("%s: failed:%d", __func__, ret);
+ return ret;
+}
+
+int cxd2820r_read_status_t2(struct dvb_frontend *fe, fe_status_t *status)
+{
+ struct cxd2820r_priv *priv = fe->demodulator_priv;
+ int ret;
+ u8 buf[1];
+ *status = 0;
+
+ ret = cxd2820r_rd_reg(priv, 0x02010 , &buf[0]);
+ if (ret)
+ goto error;
+
+ if ((buf[0] & 0x07) == 6) {
+ if (((buf[0] >> 5) & 0x01) == 1) {
+ *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
+ FE_HAS_VITERBI | FE_HAS_SYNC | FE_HAS_LOCK;
+ } else {
+ *status |= FE_HAS_SIGNAL | FE_HAS_CARRIER |
+ FE_HAS_VITERBI | FE_HAS_SYNC;
+ }
+ }
+
+ dbg("%s: lock=%02x", __func__, buf[0]);
+
+ return ret;
+error:
+ dbg("%s: failed:%d", __func__, ret);
+ return ret;
+}
+
+int cxd2820r_read_ber_t2(struct dvb_frontend *fe, u32 *ber)
+{
+ struct cxd2820r_priv *priv = fe->demodulator_priv;
+ int ret;
+ u8 buf[4];
+ unsigned int errbits;
+ *ber = 0;
+ /* FIXME: correct calculation */
+
+ ret = cxd2820r_rd_regs(priv, 0x02039, buf, sizeof(buf));
+ if (ret)
+ goto error;
+
+ if ((buf[0] >> 4) & 0x01) {
+ errbits = (buf[0] & 0x0f) << 24 | buf[1] << 16 |
+ buf[2] << 8 | buf[3];
+
+ if (errbits)
+ *ber = errbits * 64 / 16588800;
+ }
+
+ return ret;
+error:
+ dbg("%s: failed:%d", __func__, ret);
+ return ret;
+}
+
+int cxd2820r_read_signal_strength_t2(struct dvb_frontend *fe,
+ u16 *strength)
+{
+ struct cxd2820r_priv *priv = fe->demodulator_priv;
+ int ret;
+ u8 buf[2];
+ u16 tmp;
+
+ ret = cxd2820r_rd_regs(priv, 0x02026, buf, sizeof(buf));
+ if (ret)
+ goto error;
+
+ tmp = (buf[0] & 0x0f) << 8 | buf[1];
+ tmp = ~tmp & 0x0fff;
+
+ /* scale value to 0x0000-0xffff from 0x0000-0x0fff */
+ *strength = tmp * 0xffff / 0x0fff;
+
+ return ret;
+error:
+ dbg("%s: failed:%d", __func__, ret);
+ return ret;
+}
+
+int cxd2820r_read_snr_t2(struct dvb_frontend *fe, u16 *snr)
+{
+ struct cxd2820r_priv *priv = fe->demodulator_priv;
+ int ret;
+ u8 buf[2];
+ u16 tmp;
+ /* report SNR in dB * 10 */
+
+ ret = cxd2820r_rd_regs(priv, 0x02028, buf, sizeof(buf));
+ if (ret)
+ goto error;
+
+ tmp = (buf[0] & 0x0f) << 8 | buf[1];
+ #define CXD2820R_LOG10_8_24 15151336 /* log10(8) << 24 */
+ if (tmp)
+ *snr = (intlog10(tmp) - CXD2820R_LOG10_8_24) / ((1 << 24)
+ / 100);
+ else
+ *snr = 0;
+
+ dbg("%s: dBx10=%d val=%04x", __func__, *snr, tmp);
+
+ return ret;
+error:
+ dbg("%s: failed:%d", __func__, ret);
+ return ret;
+}
+
+int cxd2820r_read_ucblocks_t2(struct dvb_frontend *fe, u32 *ucblocks)
+{
+ *ucblocks = 0;
+ /* no way to read ? */
+ return 0;
+}
+
+int cxd2820r_sleep_t2(struct dvb_frontend *fe)
+{
+ struct cxd2820r_priv *priv = fe->demodulator_priv;
+ int ret, i;
+ struct reg_val_mask tab[] = {
+ { 0x000ff, 0x1f, 0xff },
+ { 0x00085, 0x00, 0xff },
+ { 0x00088, 0x01, 0xff },
+ { 0x02069, 0x00, 0xff },
+ { 0x00081, 0x00, 0xff },
+ { 0x00080, 0x00, 0xff },
+ };
+
+ dbg("%s", __func__);
+
+ for (i = 0; i < ARRAY_SIZE(tab); i++) {
+ ret = cxd2820r_wr_reg_mask(priv, tab[i].reg, tab[i].val,
+ tab[i].mask);
+ if (ret)
+ goto error;
+ }
+
+ priv->delivery_system = SYS_UNDEFINED;
+
+ return ret;
+error:
+ dbg("%s: failed:%d", __func__, ret);
+ return ret;
+}
+
+int cxd2820r_get_tune_settings_t2(struct dvb_frontend *fe,
+ struct dvb_frontend_tune_settings *s)
+{
+ s->min_delay_ms = 1500;
+ s->step_size = fe->ops.info.frequency_stepsize * 2;
+ s->max_drift = (fe->ops.info.frequency_stepsize * 2) + 1;
+
+ return 0;
+}
+
diff --git a/drivers/media/dvb/frontends/dib0070.c b/drivers/media/dvb/frontends/dib0070.c
index d4e466a..1d47d4d 100644
--- a/drivers/media/dvb/frontends/dib0070.c
+++ b/drivers/media/dvb/frontends/dib0070.c
@@ -73,27 +73,47 @@
u8 wbd_gain_current;
u16 wbd_offset_3_3[2];
+
+ /* for the I2C transfer */
+ struct i2c_msg msg[2];
+ u8 i2c_write_buffer[3];
+ u8 i2c_read_buffer[2];
};
static uint16_t dib0070_read_reg(struct dib0070_state *state, u8 reg)
{
- u8 b[2];
- struct i2c_msg msg[2] = {
- { .addr = state->cfg->i2c_address, .flags = 0, .buf = ®, .len = 1 },
- { .addr = state->cfg->i2c_address, .flags = I2C_M_RD, .buf = b, .len = 2 },
- };
- if (i2c_transfer(state->i2c, msg, 2) != 2) {
+ state->i2c_write_buffer[0] = reg;
+
+ memset(state->msg, 0, 2 * sizeof(struct i2c_msg));
+ state->msg[0].addr = state->cfg->i2c_address;
+ state->msg[0].flags = 0;
+ state->msg[0].buf = state->i2c_write_buffer;
+ state->msg[0].len = 1;
+ state->msg[1].addr = state->cfg->i2c_address;
+ state->msg[1].flags = I2C_M_RD;
+ state->msg[1].buf = state->i2c_read_buffer;
+ state->msg[1].len = 2;
+
+ if (i2c_transfer(state->i2c, state->msg, 2) != 2) {
printk(KERN_WARNING "DiB0070 I2C read failed\n");
return 0;
}
- return (b[0] << 8) | b[1];
+ return (state->i2c_read_buffer[0] << 8) | state->i2c_read_buffer[1];
}
static int dib0070_write_reg(struct dib0070_state *state, u8 reg, u16 val)
{
- u8 b[3] = { reg, val >> 8, val & 0xff };
- struct i2c_msg msg = { .addr = state->cfg->i2c_address, .flags = 0, .buf = b, .len = 3 };
- if (i2c_transfer(state->i2c, &msg, 1) != 1) {
+ state->i2c_write_buffer[0] = reg;
+ state->i2c_write_buffer[1] = val >> 8;
+ state->i2c_write_buffer[2] = val & 0xff;
+
+ memset(state->msg, 0, sizeof(struct i2c_msg));
+ state->msg[0].addr = state->cfg->i2c_address;
+ state->msg[0].flags = 0;
+ state->msg[0].buf = state->i2c_write_buffer;
+ state->msg[0].len = 3;
+
+ if (i2c_transfer(state->i2c, state->msg, 1) != 1) {
printk(KERN_WARNING "DiB0070 I2C write failed\n");
return -EREMOTEIO;
}
diff --git a/drivers/media/dvb/frontends/dib0090.c b/drivers/media/dvb/frontends/dib0090.c
index 52ff1a2..c9c935a 100644
--- a/drivers/media/dvb/frontends/dib0090.c
+++ b/drivers/media/dvb/frontends/dib0090.c
@@ -191,6 +191,11 @@
u8 wbd_calibration_gain;
const struct dib0090_wbd_slope *current_wbd_table;
u16 wbdmux;
+
+ /* for the I2C transfer */
+ struct i2c_msg msg[2];
+ u8 i2c_write_buffer[3];
+ u8 i2c_read_buffer[2];
};
struct dib0090_fw_state {
@@ -198,27 +203,48 @@
struct dvb_frontend *fe;
struct dib0090_identity identity;
const struct dib0090_config *config;
+
+ /* for the I2C transfer */
+ struct i2c_msg msg;
+ u8 i2c_write_buffer[2];
+ u8 i2c_read_buffer[2];
};
static u16 dib0090_read_reg(struct dib0090_state *state, u8 reg)
{
- u8 b[2];
- struct i2c_msg msg[2] = {
- {.addr = state->config->i2c_address, .flags = 0, .buf = ®, .len = 1},
- {.addr = state->config->i2c_address, .flags = I2C_M_RD, .buf = b, .len = 2},
- };
- if (i2c_transfer(state->i2c, msg, 2) != 2) {
+ state->i2c_write_buffer[0] = reg;
+
+ memset(state->msg, 0, 2 * sizeof(struct i2c_msg));
+ state->msg[0].addr = state->config->i2c_address;
+ state->msg[0].flags = 0;
+ state->msg[0].buf = state->i2c_write_buffer;
+ state->msg[0].len = 1;
+ state->msg[1].addr = state->config->i2c_address;
+ state->msg[1].flags = I2C_M_RD;
+ state->msg[1].buf = state->i2c_read_buffer;
+ state->msg[1].len = 2;
+
+ if (i2c_transfer(state->i2c, state->msg, 2) != 2) {
printk(KERN_WARNING "DiB0090 I2C read failed\n");
return 0;
}
- return (b[0] << 8) | b[1];
+
+ return (state->i2c_read_buffer[0] << 8) | state->i2c_read_buffer[1];
}
static int dib0090_write_reg(struct dib0090_state *state, u32 reg, u16 val)
{
- u8 b[3] = { reg & 0xff, val >> 8, val & 0xff };
- struct i2c_msg msg = {.addr = state->config->i2c_address, .flags = 0, .buf = b, .len = 3 };
- if (i2c_transfer(state->i2c, &msg, 1) != 1) {
+ state->i2c_write_buffer[0] = reg & 0xff;
+ state->i2c_write_buffer[1] = val >> 8;
+ state->i2c_write_buffer[2] = val & 0xff;
+
+ memset(state->msg, 0, sizeof(struct i2c_msg));
+ state->msg[0].addr = state->config->i2c_address;
+ state->msg[0].flags = 0;
+ state->msg[0].buf = state->i2c_write_buffer;
+ state->msg[0].len = 3;
+
+ if (i2c_transfer(state->i2c, state->msg, 1) != 1) {
printk(KERN_WARNING "DiB0090 I2C write failed\n");
return -EREMOTEIO;
}
@@ -227,20 +253,31 @@
static u16 dib0090_fw_read_reg(struct dib0090_fw_state *state, u8 reg)
{
- u8 b[2];
- struct i2c_msg msg = {.addr = reg, .flags = I2C_M_RD, .buf = b, .len = 2 };
- if (i2c_transfer(state->i2c, &msg, 1) != 1) {
+ state->i2c_write_buffer[0] = reg;
+
+ memset(&state->msg, 0, sizeof(struct i2c_msg));
+ state->msg.addr = reg;
+ state->msg.flags = I2C_M_RD;
+ state->msg.buf = state->i2c_read_buffer;
+ state->msg.len = 2;
+ if (i2c_transfer(state->i2c, &state->msg, 1) != 1) {
printk(KERN_WARNING "DiB0090 I2C read failed\n");
return 0;
}
- return (b[0] << 8) | b[1];
+ return (state->i2c_read_buffer[0] << 8) | state->i2c_read_buffer[1];
}
static int dib0090_fw_write_reg(struct dib0090_fw_state *state, u8 reg, u16 val)
{
- u8 b[2] = { val >> 8, val & 0xff };
- struct i2c_msg msg = {.addr = reg, .flags = 0, .buf = b, .len = 2 };
- if (i2c_transfer(state->i2c, &msg, 1) != 1) {
+ state->i2c_write_buffer[0] = val >> 8;
+ state->i2c_write_buffer[1] = val & 0xff;
+
+ memset(&state->msg, 0, sizeof(struct i2c_msg));
+ state->msg.addr = reg;
+ state->msg.flags = 0;
+ state->msg.buf = state->i2c_write_buffer;
+ state->msg.len = 2;
+ if (i2c_transfer(state->i2c, &state->msg, 1) != 1) {
printk(KERN_WARNING "DiB0090 I2C write failed\n");
return -EREMOTEIO;
}
diff --git a/drivers/media/dvb/frontends/dib7000m.c b/drivers/media/dvb/frontends/dib7000m.c
index 289a798..79cb1c2 100644
--- a/drivers/media/dvb/frontends/dib7000m.c
+++ b/drivers/media/dvb/frontends/dib7000m.c
@@ -50,6 +50,11 @@
u16 revision;
u8 agc_state;
+
+ /* for the I2C transfer */
+ struct i2c_msg msg[2];
+ u8 i2c_write_buffer[4];
+ u8 i2c_read_buffer[2];
};
enum dib7000m_power_mode {
@@ -64,29 +69,39 @@
static u16 dib7000m_read_word(struct dib7000m_state *state, u16 reg)
{
- u8 wb[2] = { (reg >> 8) | 0x80, reg & 0xff };
- u8 rb[2];
- struct i2c_msg msg[2] = {
- { .addr = state->i2c_addr >> 1, .flags = 0, .buf = wb, .len = 2 },
- { .addr = state->i2c_addr >> 1, .flags = I2C_M_RD, .buf = rb, .len = 2 },
- };
+ state->i2c_write_buffer[0] = (reg >> 8) | 0x80;
+ state->i2c_write_buffer[1] = reg & 0xff;
- if (i2c_transfer(state->i2c_adap, msg, 2) != 2)
+ memset(state->msg, 0, 2 * sizeof(struct i2c_msg));
+ state->msg[0].addr = state->i2c_addr >> 1;
+ state->msg[0].flags = 0;
+ state->msg[0].buf = state->i2c_write_buffer;
+ state->msg[0].len = 2;
+ state->msg[1].addr = state->i2c_addr >> 1;
+ state->msg[1].flags = I2C_M_RD;
+ state->msg[1].buf = state->i2c_read_buffer;
+ state->msg[1].len = 2;
+
+ if (i2c_transfer(state->i2c_adap, state->msg, 2) != 2)
dprintk("i2c read error on %d",reg);
- return (rb[0] << 8) | rb[1];
+ return (state->i2c_read_buffer[0] << 8) | state->i2c_read_buffer[1];
}
static int dib7000m_write_word(struct dib7000m_state *state, u16 reg, u16 val)
{
- u8 b[4] = {
- (reg >> 8) & 0xff, reg & 0xff,
- (val >> 8) & 0xff, val & 0xff,
- };
- struct i2c_msg msg = {
- .addr = state->i2c_addr >> 1, .flags = 0, .buf = b, .len = 4
- };
- return i2c_transfer(state->i2c_adap, &msg, 1) != 1 ? -EREMOTEIO : 0;
+ state->i2c_write_buffer[0] = (reg >> 8) & 0xff;
+ state->i2c_write_buffer[1] = reg & 0xff;
+ state->i2c_write_buffer[2] = (val >> 8) & 0xff;
+ state->i2c_write_buffer[3] = val & 0xff;
+
+ memset(&state->msg[0], 0, sizeof(struct i2c_msg));
+ state->msg[0].addr = state->i2c_addr >> 1;
+ state->msg[0].flags = 0;
+ state->msg[0].buf = state->i2c_write_buffer;
+ state->msg[0].len = 4;
+
+ return i2c_transfer(state->i2c_adap, state->msg, 1) != 1 ? -EREMOTEIO : 0;
}
static void dib7000m_write_tab(struct dib7000m_state *state, u16 *buf)
{
diff --git a/drivers/media/dvb/frontends/dib7000p.c b/drivers/media/dvb/frontends/dib7000p.c
index 900af60..0c9f40c 100644
--- a/drivers/media/dvb/frontends/dib7000p.c
+++ b/drivers/media/dvb/frontends/dib7000p.c
@@ -63,6 +63,11 @@
u16 tuner_enable;
struct i2c_adapter dib7090_tuner_adap;
+
+ /* for the I2C transfer */
+ struct i2c_msg msg[2];
+ u8 i2c_write_buffer[4];
+ u8 i2c_read_buffer[2];
};
enum dib7000p_power_mode {
@@ -76,29 +81,39 @@
static u16 dib7000p_read_word(struct dib7000p_state *state, u16 reg)
{
- u8 wb[2] = { reg >> 8, reg & 0xff };
- u8 rb[2];
- struct i2c_msg msg[2] = {
- {.addr = state->i2c_addr >> 1, .flags = 0, .buf = wb, .len = 2},
- {.addr = state->i2c_addr >> 1, .flags = I2C_M_RD, .buf = rb, .len = 2},
- };
+ state->i2c_write_buffer[0] = reg >> 8;
+ state->i2c_write_buffer[1] = reg & 0xff;
- if (i2c_transfer(state->i2c_adap, msg, 2) != 2)
+ memset(state->msg, 0, 2 * sizeof(struct i2c_msg));
+ state->msg[0].addr = state->i2c_addr >> 1;
+ state->msg[0].flags = 0;
+ state->msg[0].buf = state->i2c_write_buffer;
+ state->msg[0].len = 2;
+ state->msg[1].addr = state->i2c_addr >> 1;
+ state->msg[1].flags = I2C_M_RD;
+ state->msg[1].buf = state->i2c_read_buffer;
+ state->msg[1].len = 2;
+
+ if (i2c_transfer(state->i2c_adap, state->msg, 2) != 2)
dprintk("i2c read error on %d", reg);
- return (rb[0] << 8) | rb[1];
+ return (state->i2c_read_buffer[0] << 8) | state->i2c_read_buffer[1];
}
static int dib7000p_write_word(struct dib7000p_state *state, u16 reg, u16 val)
{
- u8 b[4] = {
- (reg >> 8) & 0xff, reg & 0xff,
- (val >> 8) & 0xff, val & 0xff,
- };
- struct i2c_msg msg = {
- .addr = state->i2c_addr >> 1, .flags = 0, .buf = b, .len = 4
- };
- return i2c_transfer(state->i2c_adap, &msg, 1) != 1 ? -EREMOTEIO : 0;
+ state->i2c_write_buffer[0] = (reg >> 8) & 0xff;
+ state->i2c_write_buffer[1] = reg & 0xff;
+ state->i2c_write_buffer[2] = (val >> 8) & 0xff;
+ state->i2c_write_buffer[3] = val & 0xff;
+
+ memset(&state->msg[0], 0, sizeof(struct i2c_msg));
+ state->msg[0].addr = state->i2c_addr >> 1;
+ state->msg[0].flags = 0;
+ state->msg[0].buf = state->i2c_write_buffer;
+ state->msg[0].len = 4;
+
+ return i2c_transfer(state->i2c_adap, state->msg, 1) != 1 ? -EREMOTEIO : 0;
}
static void dib7000p_write_tab(struct dib7000p_state *state, u16 * buf)
@@ -1550,11 +1565,24 @@
int dib7000pc_detection(struct i2c_adapter *i2c_adap)
{
- u8 tx[2], rx[2];
+ u8 *tx, *rx;
struct i2c_msg msg[2] = {
- {.addr = 18 >> 1, .flags = 0, .buf = tx, .len = 2},
- {.addr = 18 >> 1, .flags = I2C_M_RD, .buf = rx, .len = 2},
+ {.addr = 18 >> 1, .flags = 0, .len = 2},
+ {.addr = 18 >> 1, .flags = I2C_M_RD, .len = 2},
};
+ int ret = 0;
+
+ tx = kzalloc(2*sizeof(u8), GFP_KERNEL);
+ if (!tx)
+ return -ENOMEM;
+ rx = kzalloc(2*sizeof(u8), GFP_KERNEL);
+ if (!rx) {
+ goto rx_memory_error;
+ ret = -ENOMEM;
+ }
+
+ msg[0].buf = tx;
+ msg[1].buf = rx;
tx[0] = 0x03;
tx[1] = 0x00;
@@ -1574,7 +1602,11 @@
}
dprintk("-D- DiB7000PC not detected");
- return 0;
+
+ kfree(rx);
+rx_memory_error:
+ kfree(tx);
+ return ret;
}
EXPORT_SYMBOL(dib7000pc_detection);
diff --git a/drivers/media/dvb/frontends/dib8000.c b/drivers/media/dvb/frontends/dib8000.c
index c1c3e26..7d2ea11 100644
--- a/drivers/media/dvb/frontends/dib8000.c
+++ b/drivers/media/dvb/frontends/dib8000.c
@@ -35,6 +35,8 @@
struct i2c_device {
struct i2c_adapter *adap;
u8 addr;
+ u8 *i2c_write_buffer;
+ u8 *i2c_read_buffer;
};
struct dib8000_state {
@@ -70,6 +72,11 @@
u32 status;
struct dvb_frontend *fe[MAX_NUMBER_OF_FRONTENDS];
+
+ /* for the I2C transfer */
+ struct i2c_msg msg[2];
+ u8 i2c_write_buffer[4];
+ u8 i2c_read_buffer[2];
};
enum dib8000_power_mode {
@@ -79,22 +86,41 @@
static u16 dib8000_i2c_read16(struct i2c_device *i2c, u16 reg)
{
- u8 wb[2] = { reg >> 8, reg & 0xff };
- u8 rb[2];
struct i2c_msg msg[2] = {
- {.addr = i2c->addr >> 1,.flags = 0,.buf = wb,.len = 2},
- {.addr = i2c->addr >> 1,.flags = I2C_M_RD,.buf = rb,.len = 2},
+ {.addr = i2c->addr >> 1, .flags = 0,
+ .buf = i2c->i2c_write_buffer, .len = 2},
+ {.addr = i2c->addr >> 1, .flags = I2C_M_RD,
+ .buf = i2c->i2c_read_buffer, .len = 2},
};
+ msg[0].buf[0] = reg >> 8;
+ msg[0].buf[1] = reg & 0xff;
+
if (i2c_transfer(i2c->adap, msg, 2) != 2)
dprintk("i2c read error on %d", reg);
- return (rb[0] << 8) | rb[1];
+ return (msg[1].buf[0] << 8) | msg[1].buf[1];
}
static u16 dib8000_read_word(struct dib8000_state *state, u16 reg)
{
- return dib8000_i2c_read16(&state->i2c, reg);
+ state->i2c_write_buffer[0] = reg >> 8;
+ state->i2c_write_buffer[1] = reg & 0xff;
+
+ memset(state->msg, 0, 2 * sizeof(struct i2c_msg));
+ state->msg[0].addr = state->i2c.addr >> 1;
+ state->msg[0].flags = 0;
+ state->msg[0].buf = state->i2c_write_buffer;
+ state->msg[0].len = 2;
+ state->msg[1].addr = state->i2c.addr >> 1;
+ state->msg[1].flags = I2C_M_RD;
+ state->msg[1].buf = state->i2c_read_buffer;
+ state->msg[1].len = 2;
+
+ if (i2c_transfer(state->i2c.adap, state->msg, 2) != 2)
+ dprintk("i2c read error on %d", reg);
+
+ return (state->i2c_read_buffer[0] << 8) | state->i2c_read_buffer[1];
}
static u32 dib8000_read32(struct dib8000_state *state, u16 reg)
@@ -109,19 +135,34 @@
static int dib8000_i2c_write16(struct i2c_device *i2c, u16 reg, u16 val)
{
- u8 b[4] = {
- (reg >> 8) & 0xff, reg & 0xff,
- (val >> 8) & 0xff, val & 0xff,
- };
- struct i2c_msg msg = {
- .addr = i2c->addr >> 1,.flags = 0,.buf = b,.len = 4
- };
- return i2c_transfer(i2c->adap, &msg, 1) != 1 ? -EREMOTEIO : 0;
+ struct i2c_msg msg = {.addr = i2c->addr >> 1, .flags = 0,
+ .buf = i2c->i2c_write_buffer, .len = 4};
+ int ret = 0;
+
+ msg.buf[0] = (reg >> 8) & 0xff;
+ msg.buf[1] = reg & 0xff;
+ msg.buf[2] = (val >> 8) & 0xff;
+ msg.buf[3] = val & 0xff;
+
+ ret = i2c_transfer(i2c->adap, &msg, 1) != 1 ? -EREMOTEIO : 0;
+
+ return ret;
}
static int dib8000_write_word(struct dib8000_state *state, u16 reg, u16 val)
{
- return dib8000_i2c_write16(&state->i2c, reg, val);
+ state->i2c_write_buffer[0] = (reg >> 8) & 0xff;
+ state->i2c_write_buffer[1] = reg & 0xff;
+ state->i2c_write_buffer[2] = (val >> 8) & 0xff;
+ state->i2c_write_buffer[3] = val & 0xff;
+
+ memset(&state->msg[0], 0, sizeof(struct i2c_msg));
+ state->msg[0].addr = state->i2c.addr >> 1;
+ state->msg[0].flags = 0;
+ state->msg[0].buf = state->i2c_write_buffer;
+ state->msg[0].len = 4;
+
+ return i2c_transfer(state->i2c.adap, state->msg, 1) != 1 ? -EREMOTEIO : 0;
}
static const s16 coeff_2k_sb_1seg_dqpsk[8] = {
@@ -980,30 +1021,31 @@
dprintk("Updated timing frequency: %d (default: %d)", state->timf, state->timf_default);
}
+static const u16 adc_target_16dB[11] = {
+ (1 << 13) - 825 - 117,
+ (1 << 13) - 837 - 117,
+ (1 << 13) - 811 - 117,
+ (1 << 13) - 766 - 117,
+ (1 << 13) - 737 - 117,
+ (1 << 13) - 693 - 117,
+ (1 << 13) - 648 - 117,
+ (1 << 13) - 619 - 117,
+ (1 << 13) - 575 - 117,
+ (1 << 13) - 531 - 117,
+ (1 << 13) - 501 - 117
+};
+static const u8 permu_seg[] = { 6, 5, 7, 4, 8, 3, 9, 2, 10, 1, 11, 0, 12 };
+
static void dib8000_set_channel(struct dib8000_state *state, u8 seq, u8 autosearching)
{
u16 mode, max_constellation, seg_diff_mask = 0, nbseg_diff = 0;
u8 guard, crate, constellation, timeI;
- u8 permu_seg[] = { 6, 5, 7, 4, 8, 3, 9, 2, 10, 1, 11, 0, 12 };
u16 i, coeff[4], P_cfr_left_edge = 0, P_cfr_right_edge = 0, seg_mask13 = 0x1fff; // All 13 segments enabled
const s16 *ncoeff = NULL, *ana_fe;
u16 tmcc_pow = 0;
u16 coff_pow = 0x2800;
u16 init_prbs = 0xfff;
u16 ana_gain = 0;
- u16 adc_target_16dB[11] = {
- (1 << 13) - 825 - 117,
- (1 << 13) - 837 - 117,
- (1 << 13) - 811 - 117,
- (1 << 13) - 766 - 117,
- (1 << 13) - 737 - 117,
- (1 << 13) - 693 - 117,
- (1 << 13) - 648 - 117,
- (1 << 13) - 619 - 117,
- (1 << 13) - 575 - 117,
- (1 << 13) - 531 - 117,
- (1 << 13) - 501 - 117
- };
if (state->ber_monitored_layer != LAYER_ALL)
dib8000_write_word(state, 285, (dib8000_read_word(state, 285) & 0x60) | state->ber_monitored_layer);
@@ -2379,10 +2421,22 @@
int dib8000_i2c_enumeration(struct i2c_adapter *host, int no_of_demods, u8 default_addr, u8 first_addr)
{
- int k = 0;
+ int k = 0, ret = 0;
u8 new_addr = 0;
struct i2c_device client = {.adap = host };
+ client.i2c_write_buffer = kzalloc(4 * sizeof(u8), GFP_KERNEL);
+ if (!client.i2c_write_buffer) {
+ dprintk("%s: not enough memory", __func__);
+ return -ENOMEM;
+ }
+ client.i2c_read_buffer = kzalloc(4 * sizeof(u8), GFP_KERNEL);
+ if (!client.i2c_read_buffer) {
+ dprintk("%s: not enough memory", __func__);
+ ret = -ENOMEM;
+ goto error_memory;
+ }
+
for (k = no_of_demods - 1; k >= 0; k--) {
/* designated i2c address */
new_addr = first_addr + (k << 1);
@@ -2394,7 +2448,8 @@
client.addr = default_addr;
if (dib8000_identify(&client) == 0) {
dprintk("#%d: not identified", k);
- return -EINVAL;
+ ret = -EINVAL;
+ goto error;
}
}
@@ -2420,7 +2475,12 @@
dib8000_i2c_write16(&client, 1286, 0);
}
- return 0;
+error:
+ kfree(client.i2c_read_buffer);
+error_memory:
+ kfree(client.i2c_write_buffer);
+
+ return ret;
}
EXPORT_SYMBOL(dib8000_i2c_enumeration);
@@ -2519,6 +2579,8 @@
memcpy(&state->cfg, cfg, sizeof(struct dib8000_config));
state->i2c.adap = i2c_adap;
state->i2c.addr = i2c_addr;
+ state->i2c.i2c_write_buffer = state->i2c_write_buffer;
+ state->i2c.i2c_read_buffer = state->i2c_read_buffer;
state->gpio_val = cfg->gpio_val;
state->gpio_dir = cfg->gpio_dir;
diff --git a/drivers/media/dvb/frontends/dib9000.c b/drivers/media/dvb/frontends/dib9000.c
index 9151876..a085588 100644
--- a/drivers/media/dvb/frontends/dib9000.c
+++ b/drivers/media/dvb/frontends/dib9000.c
@@ -27,6 +27,8 @@
struct i2c_device {
struct i2c_adapter *i2c_adap;
u8 i2c_addr;
+ u8 *i2c_read_buffer;
+ u8 *i2c_write_buffer;
};
/* lock */
@@ -92,11 +94,16 @@
struct dvb_frontend *fe[MAX_NUMBER_OF_FRONTENDS];
u16 component_bus_speed;
+
+ /* for the I2C transfer */
+ struct i2c_msg msg[2];
+ u8 i2c_write_buffer[255];
+ u8 i2c_read_buffer[255];
};
-u32 fe_info[44] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+static const u32 fe_info[44] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
- 0, 0, 0
+ 0, 0, 0, 0, 0, 0, 0, 0
};
enum dib9000_power_mode {
@@ -217,25 +224,33 @@
u32 chunk_size = 126;
u32 l;
int ret;
- u8 wb[2] = { reg >> 8, reg & 0xff };
- struct i2c_msg msg[2] = {
- {.addr = state->i2c.i2c_addr >> 1, .flags = 0, .buf = wb, .len = 2},
- {.addr = state->i2c.i2c_addr >> 1, .flags = I2C_M_RD, .buf = b, .len = len},
- };
if (state->platform.risc.fw_is_running && (reg < 1024))
return dib9000_risc_apb_access_read(state, reg, attribute, NULL, 0, b, len);
+ memset(state->msg, 0, 2 * sizeof(struct i2c_msg));
+ state->msg[0].addr = state->i2c.i2c_addr >> 1;
+ state->msg[0].flags = 0;
+ state->msg[0].buf = state->i2c_write_buffer;
+ state->msg[0].len = 2;
+ state->msg[1].addr = state->i2c.i2c_addr >> 1;
+ state->msg[1].flags = I2C_M_RD;
+ state->msg[1].buf = b;
+ state->msg[1].len = len;
+
+ state->i2c_write_buffer[0] = reg >> 8;
+ state->i2c_write_buffer[1] = reg & 0xff;
+
if (attribute & DATA_BUS_ACCESS_MODE_8BIT)
- wb[0] |= (1 << 5);
+ state->i2c_write_buffer[0] |= (1 << 5);
if (attribute & DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT)
- wb[0] |= (1 << 4);
+ state->i2c_write_buffer[0] |= (1 << 4);
do {
l = len < chunk_size ? len : chunk_size;
- msg[1].len = l;
- msg[1].buf = b;
- ret = i2c_transfer(state->i2c.i2c_adap, msg, 2) != 2 ? -EREMOTEIO : 0;
+ state->msg[1].len = l;
+ state->msg[1].buf = b;
+ ret = i2c_transfer(state->i2c.i2c_adap, state->msg, 2) != 2 ? -EREMOTEIO : 0;
if (ret != 0) {
dprintk("i2c read error on %d", reg);
return -EREMOTEIO;
@@ -253,50 +268,47 @@
static u16 dib9000_i2c_read16(struct i2c_device *i2c, u16 reg)
{
- u8 b[2];
- u8 wb[2] = { reg >> 8, reg & 0xff };
struct i2c_msg msg[2] = {
- {.addr = i2c->i2c_addr >> 1, .flags = 0, .buf = wb, .len = 2},
- {.addr = i2c->i2c_addr >> 1, .flags = I2C_M_RD, .buf = b, .len = 2},
+ {.addr = i2c->i2c_addr >> 1, .flags = 0,
+ .buf = i2c->i2c_write_buffer, .len = 2},
+ {.addr = i2c->i2c_addr >> 1, .flags = I2C_M_RD,
+ .buf = i2c->i2c_read_buffer, .len = 2},
};
+ i2c->i2c_write_buffer[0] = reg >> 8;
+ i2c->i2c_write_buffer[1] = reg & 0xff;
+
if (i2c_transfer(i2c->i2c_adap, msg, 2) != 2) {
dprintk("read register %x error", reg);
return 0;
}
- return (b[0] << 8) | b[1];
+ return (i2c->i2c_read_buffer[0] << 8) | i2c->i2c_read_buffer[1];
}
static inline u16 dib9000_read_word(struct dib9000_state *state, u16 reg)
{
- u8 b[2];
- if (dib9000_read16_attr(state, reg, b, 2, 0) != 0)
+ if (dib9000_read16_attr(state, reg, state->i2c_read_buffer, 2, 0) != 0)
return 0;
- return (b[0] << 8 | b[1]);
+ return (state->i2c_read_buffer[0] << 8) | state->i2c_read_buffer[1];
}
static inline u16 dib9000_read_word_attr(struct dib9000_state *state, u16 reg, u16 attribute)
{
- u8 b[2];
- if (dib9000_read16_attr(state, reg, b, 2, attribute) != 0)
+ if (dib9000_read16_attr(state, reg, state->i2c_read_buffer, 2,
+ attribute) != 0)
return 0;
- return (b[0] << 8 | b[1]);
+ return (state->i2c_read_buffer[0] << 8) | state->i2c_read_buffer[1];
}
#define dib9000_read16_noinc_attr(state, reg, b, len, attribute) dib9000_read16_attr(state, reg, b, len, (attribute) | DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT)
static u16 dib9000_write16_attr(struct dib9000_state *state, u16 reg, const u8 * buf, u32 len, u16 attribute)
{
- u8 b[255];
u32 chunk_size = 126;
u32 l;
int ret;
- struct i2c_msg msg = {
- .addr = state->i2c.i2c_addr >> 1, .flags = 0, .buf = b, .len = len + 2
- };
-
if (state->platform.risc.fw_is_running && (reg < 1024)) {
if (dib9000_risc_apb_access_write
(state, reg, DATA_BUS_ACCESS_MODE_16BIT | DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT | attribute, buf, len) != 0)
@@ -304,20 +316,26 @@
return 0;
}
- b[0] = (reg >> 8) & 0xff;
- b[1] = (reg) & 0xff;
+ memset(&state->msg[0], 0, sizeof(struct i2c_msg));
+ state->msg[0].addr = state->i2c.i2c_addr >> 1;
+ state->msg[0].flags = 0;
+ state->msg[0].buf = state->i2c_write_buffer;
+ state->msg[0].len = len + 2;
+
+ state->i2c_write_buffer[0] = (reg >> 8) & 0xff;
+ state->i2c_write_buffer[1] = (reg) & 0xff;
if (attribute & DATA_BUS_ACCESS_MODE_8BIT)
- b[0] |= (1 << 5);
+ state->i2c_write_buffer[0] |= (1 << 5);
if (attribute & DATA_BUS_ACCESS_MODE_NO_ADDRESS_INCREMENT)
- b[0] |= (1 << 4);
+ state->i2c_write_buffer[0] |= (1 << 4);
do {
l = len < chunk_size ? len : chunk_size;
- msg.len = l + 2;
- memcpy(&b[2], buf, l);
+ state->msg[0].len = l + 2;
+ memcpy(&state->i2c_write_buffer[2], buf, l);
- ret = i2c_transfer(state->i2c.i2c_adap, &msg, 1) != 1 ? -EREMOTEIO : 0;
+ ret = i2c_transfer(state->i2c.i2c_adap, state->msg, 1) != 1 ? -EREMOTEIO : 0;
buf += l;
len -= l;
@@ -331,11 +349,16 @@
static int dib9000_i2c_write16(struct i2c_device *i2c, u16 reg, u16 val)
{
- u8 b[4] = { (reg >> 8) & 0xff, reg & 0xff, (val >> 8) & 0xff, val & 0xff };
struct i2c_msg msg = {
- .addr = i2c->i2c_addr >> 1, .flags = 0, .buf = b, .len = 4
+ .addr = i2c->i2c_addr >> 1, .flags = 0,
+ .buf = i2c->i2c_write_buffer, .len = 4
};
+ i2c->i2c_write_buffer[0] = (reg >> 8) & 0xff;
+ i2c->i2c_write_buffer[1] = reg & 0xff;
+ i2c->i2c_write_buffer[2] = (val >> 8) & 0xff;
+ i2c->i2c_write_buffer[3] = val & 0xff;
+
return i2c_transfer(i2c->i2c_adap, &msg, 1) != 1 ? -EREMOTEIO : 0;
}
@@ -1015,8 +1038,8 @@
return 0;
dib9000_risc_mem_write(state, FE_MM_RW_SYNC, &i);
do {
- dib9000_risc_mem_read(state, FE_MM_RW_SYNC, &i, 1);
- } while (i && index_loop--);
+ dib9000_risc_mem_read(state, FE_MM_RW_SYNC, state->i2c_read_buffer, 1);
+ } while (state->i2c_read_buffer[0] && index_loop--);
if (index_loop > 0)
return 0;
@@ -1139,7 +1162,7 @@
s8 intlv_native;
};
- struct dibDVBTChannel ch;
+ struct dibDVBTChannel *ch;
int ret = 0;
DibAcquireLock(&state->platform.risc.mem_mbx_lock);
@@ -1148,9 +1171,12 @@
ret = -EIO;
}
- dib9000_risc_mem_read(state, FE_MM_R_CHANNEL_UNION, (u8 *) &ch, sizeof(struct dibDVBTChannel));
+ dib9000_risc_mem_read(state, FE_MM_R_CHANNEL_UNION,
+ state->i2c_read_buffer, sizeof(struct dibDVBTChannel));
+ ch = (struct dibDVBTChannel *)state->i2c_read_buffer;
- switch (ch.spectrum_inversion & 0x7) {
+
+ switch (ch->spectrum_inversion & 0x7) {
case 1:
state->fe[0]->dtv_property_cache.inversion = INVERSION_ON;
break;
@@ -1162,7 +1188,7 @@
state->fe[0]->dtv_property_cache.inversion = INVERSION_AUTO;
break;
}
- switch (ch.nfft) {
+ switch (ch->nfft) {
case 0:
state->fe[0]->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_2K;
break;
@@ -1177,7 +1203,7 @@
state->fe[0]->dtv_property_cache.transmission_mode = TRANSMISSION_MODE_AUTO;
break;
}
- switch (ch.guard) {
+ switch (ch->guard) {
case 0:
state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_1_32;
break;
@@ -1195,7 +1221,7 @@
state->fe[0]->dtv_property_cache.guard_interval = GUARD_INTERVAL_AUTO;
break;
}
- switch (ch.constellation) {
+ switch (ch->constellation) {
case 2:
state->fe[0]->dtv_property_cache.modulation = QAM_64;
break;
@@ -1210,7 +1236,7 @@
state->fe[0]->dtv_property_cache.modulation = QAM_AUTO;
break;
}
- switch (ch.hrch) {
+ switch (ch->hrch) {
case 0:
state->fe[0]->dtv_property_cache.hierarchy = HIERARCHY_NONE;
break;
@@ -1222,7 +1248,7 @@
state->fe[0]->dtv_property_cache.hierarchy = HIERARCHY_AUTO;
break;
}
- switch (ch.code_rate_hp) {
+ switch (ch->code_rate_hp) {
case 1:
state->fe[0]->dtv_property_cache.code_rate_HP = FEC_1_2;
break;
@@ -1243,7 +1269,7 @@
state->fe[0]->dtv_property_cache.code_rate_HP = FEC_AUTO;
break;
}
- switch (ch.code_rate_lp) {
+ switch (ch->code_rate_lp) {
case 1:
state->fe[0]->dtv_property_cache.code_rate_LP = FEC_1_2;
break;
@@ -1439,9 +1465,10 @@
break;
case CT_DEMOD_STEP_1:
if (search)
- dib9000_risc_mem_read(state, FE_MM_R_CHANNEL_SEARCH_STATE, (u8 *) &i, 1);
+ dib9000_risc_mem_read(state, FE_MM_R_CHANNEL_SEARCH_STATE, state->i2c_read_buffer, 1);
else
- dib9000_risc_mem_read(state, FE_MM_R_CHANNEL_TUNE_STATE, (u8 *) &i, 1);
+ dib9000_risc_mem_read(state, FE_MM_R_CHANNEL_TUNE_STATE, state->i2c_read_buffer, 1);
+ i = (s8)state->i2c_read_buffer[0];
switch (i) { /* something happened */
case 0:
break;
@@ -2038,14 +2065,17 @@
static int dib9000_read_ber(struct dvb_frontend *fe, u32 * ber)
{
struct dib9000_state *state = fe->demodulator_priv;
- u16 c[16];
+ u16 *c;
DibAcquireLock(&state->platform.risc.mem_mbx_lock);
if (dib9000_fw_memmbx_sync(state, FE_SYNC_CHANNEL) < 0)
return -EIO;
- dib9000_risc_mem_read(state, FE_MM_R_FE_MONITOR, (u8 *) c, sizeof(c));
+ dib9000_risc_mem_read(state, FE_MM_R_FE_MONITOR,
+ state->i2c_read_buffer, 16 * 2);
DibReleaseLock(&state->platform.risc.mem_mbx_lock);
+ c = (u16 *)state->i2c_read_buffer;
+
*ber = c[10] << 16 | c[11];
return 0;
}
@@ -2054,7 +2084,7 @@
{
struct dib9000_state *state = fe->demodulator_priv;
u8 index_frontend;
- u16 c[16];
+ u16 *c = (u16 *)state->i2c_read_buffer;
u16 val;
*strength = 0;
@@ -2069,7 +2099,7 @@
DibAcquireLock(&state->platform.risc.mem_mbx_lock);
if (dib9000_fw_memmbx_sync(state, FE_SYNC_CHANNEL) < 0)
return -EIO;
- dib9000_risc_mem_read(state, FE_MM_R_FE_MONITOR, (u8 *) c, sizeof(c));
+ dib9000_risc_mem_read(state, FE_MM_R_FE_MONITOR, (u8 *) c, 16 * 2);
DibReleaseLock(&state->platform.risc.mem_mbx_lock);
val = 65535 - c[4];
@@ -2083,14 +2113,14 @@
static u32 dib9000_get_snr(struct dvb_frontend *fe)
{
struct dib9000_state *state = fe->demodulator_priv;
- u16 c[16];
+ u16 *c = (u16 *)state->i2c_read_buffer;
u32 n, s, exp;
u16 val;
DibAcquireLock(&state->platform.risc.mem_mbx_lock);
if (dib9000_fw_memmbx_sync(state, FE_SYNC_CHANNEL) < 0)
return -EIO;
- dib9000_risc_mem_read(state, FE_MM_R_FE_MONITOR, (u8 *) c, sizeof(c));
+ dib9000_risc_mem_read(state, FE_MM_R_FE_MONITOR, (u8 *) c, 16 * 2);
DibReleaseLock(&state->platform.risc.mem_mbx_lock);
val = c[7];
@@ -2137,12 +2167,12 @@
static int dib9000_read_unc_blocks(struct dvb_frontend *fe, u32 * unc)
{
struct dib9000_state *state = fe->demodulator_priv;
- u16 c[16];
+ u16 *c = (u16 *)state->i2c_read_buffer;
DibAcquireLock(&state->platform.risc.mem_mbx_lock);
if (dib9000_fw_memmbx_sync(state, FE_SYNC_CHANNEL) < 0)
return -EIO;
- dib9000_risc_mem_read(state, FE_MM_R_FE_MONITOR, (u8 *) c, sizeof(c));
+ dib9000_risc_mem_read(state, FE_MM_R_FE_MONITOR, (u8 *) c, 16 * 2);
DibReleaseLock(&state->platform.risc.mem_mbx_lock);
*unc = c[12];
@@ -2151,10 +2181,22 @@
int dib9000_i2c_enumeration(struct i2c_adapter *i2c, int no_of_demods, u8 default_addr, u8 first_addr)
{
- int k = 0;
+ int k = 0, ret = 0;
u8 new_addr = 0;
struct i2c_device client = {.i2c_adap = i2c };
+ client.i2c_write_buffer = kzalloc(4 * sizeof(u8), GFP_KERNEL);
+ if (!client.i2c_write_buffer) {
+ dprintk("%s: not enough memory", __func__);
+ return -ENOMEM;
+ }
+ client.i2c_read_buffer = kzalloc(4 * sizeof(u8), GFP_KERNEL);
+ if (!client.i2c_read_buffer) {
+ dprintk("%s: not enough memory", __func__);
+ ret = -ENOMEM;
+ goto error_memory;
+ }
+
client.i2c_addr = default_addr + 16;
dib9000_i2c_write16(&client, 1796, 0x0);
@@ -2178,7 +2220,8 @@
client.i2c_addr = default_addr;
if (dib9000_identify(&client) == 0) {
dprintk("DiB9000 #%d: not identified", k);
- return -EIO;
+ ret = -EIO;
+ goto error;
}
}
@@ -2196,7 +2239,12 @@
dib9000_i2c_write16(&client, 1795, 0);
}
- return 0;
+error:
+ kfree(client.i2c_read_buffer);
+error_memory:
+ kfree(client.i2c_write_buffer);
+
+ return ret;
}
EXPORT_SYMBOL(dib9000_i2c_enumeration);
@@ -2255,12 +2303,16 @@
if (st == NULL)
return NULL;
fe = kzalloc(sizeof(struct dvb_frontend), GFP_KERNEL);
- if (fe == NULL)
+ if (fe == NULL) {
+ kfree(st);
return NULL;
+ }
memcpy(&st->chip.d9.cfg, cfg, sizeof(struct dib9000_config));
st->i2c.i2c_adap = i2c_adap;
st->i2c.i2c_addr = i2c_addr;
+ st->i2c.i2c_write_buffer = st->i2c_write_buffer;
+ st->i2c.i2c_read_buffer = st->i2c_read_buffer;
st->gpio_dir = DIB9000_GPIO_DEFAULT_DIRECTIONS;
st->gpio_val = DIB9000_GPIO_DEFAULT_VALUES;
diff --git a/drivers/media/dvb/frontends/dibx000_common.c b/drivers/media/dvb/frontends/dibx000_common.c
index f6938f9..dc5d17a 100644
--- a/drivers/media/dvb/frontends/dibx000_common.c
+++ b/drivers/media/dvb/frontends/dibx000_common.c
@@ -10,30 +10,39 @@
static int dibx000_write_word(struct dibx000_i2c_master *mst, u16 reg, u16 val)
{
- u8 b[4] = {
- (reg >> 8) & 0xff, reg & 0xff,
- (val >> 8) & 0xff, val & 0xff,
- };
- struct i2c_msg msg = {
- .addr = mst->i2c_addr,.flags = 0,.buf = b,.len = 4
- };
+ mst->i2c_write_buffer[0] = (reg >> 8) & 0xff;
+ mst->i2c_write_buffer[1] = reg & 0xff;
+ mst->i2c_write_buffer[2] = (val >> 8) & 0xff;
+ mst->i2c_write_buffer[3] = val & 0xff;
- return i2c_transfer(mst->i2c_adap, &msg, 1) != 1 ? -EREMOTEIO : 0;
+ memset(mst->msg, 0, sizeof(struct i2c_msg));
+ mst->msg[0].addr = mst->i2c_addr;
+ mst->msg[0].flags = 0;
+ mst->msg[0].buf = mst->i2c_write_buffer;
+ mst->msg[0].len = 4;
+
+ return i2c_transfer(mst->i2c_adap, mst->msg, 1) != 1 ? -EREMOTEIO : 0;
}
static u16 dibx000_read_word(struct dibx000_i2c_master *mst, u16 reg)
{
- u8 wb[2] = { reg >> 8, reg & 0xff };
- u8 rb[2];
- struct i2c_msg msg[2] = {
- {.addr = mst->i2c_addr, .flags = 0, .buf = wb, .len = 2},
- {.addr = mst->i2c_addr, .flags = I2C_M_RD, .buf = rb, .len = 2},
- };
+ mst->i2c_write_buffer[0] = reg >> 8;
+ mst->i2c_write_buffer[1] = reg & 0xff;
- if (i2c_transfer(mst->i2c_adap, msg, 2) != 2)
+ memset(mst->msg, 0, 2 * sizeof(struct i2c_msg));
+ mst->msg[0].addr = mst->i2c_addr;
+ mst->msg[0].flags = 0;
+ mst->msg[0].buf = mst->i2c_write_buffer;
+ mst->msg[0].len = 2;
+ mst->msg[1].addr = mst->i2c_addr;
+ mst->msg[1].flags = I2C_M_RD;
+ mst->msg[1].buf = mst->i2c_read_buffer;
+ mst->msg[1].len = 2;
+
+ if (i2c_transfer(mst->i2c_adap, mst->msg, 2) != 2)
dprintk("i2c read error on %d", reg);
- return (rb[0] << 8) | rb[1];
+ return (mst->i2c_read_buffer[0] << 8) | mst->i2c_read_buffer[1];
}
static int dibx000_is_i2c_done(struct dibx000_i2c_master *mst)
@@ -248,26 +257,32 @@
struct i2c_msg msg[], int num)
{
struct dibx000_i2c_master *mst = i2c_get_adapdata(i2c_adap);
- struct i2c_msg m[2 + num];
- u8 tx_open[4], tx_close[4];
- memset(m, 0, sizeof(struct i2c_msg) * (2 + num));
+ if (num > 32) {
+ dprintk("%s: too much I2C message to be transmitted (%i).\
+ Maximum is 32", __func__, num);
+ return -ENOMEM;
+ }
+
+ memset(mst->msg, 0, sizeof(struct i2c_msg) * (2 + num));
dibx000_i2c_select_interface(mst, DIBX000_I2C_INTERFACE_GPIO_6_7);
- dibx000_i2c_gate_ctrl(mst, tx_open, msg[0].addr, 1);
- m[0].addr = mst->i2c_addr;
- m[0].buf = tx_open;
- m[0].len = 4;
+ /* open the gate */
+ dibx000_i2c_gate_ctrl(mst, &mst->i2c_write_buffer[0], msg[0].addr, 1);
+ mst->msg[0].addr = mst->i2c_addr;
+ mst->msg[0].buf = &mst->i2c_write_buffer[0];
+ mst->msg[0].len = 4;
- memcpy(&m[1], msg, sizeof(struct i2c_msg) * num);
+ memcpy(&mst->msg[1], msg, sizeof(struct i2c_msg) * num);
- dibx000_i2c_gate_ctrl(mst, tx_close, 0, 0);
- m[num + 1].addr = mst->i2c_addr;
- m[num + 1].buf = tx_close;
- m[num + 1].len = 4;
+ /* close the gate */
+ dibx000_i2c_gate_ctrl(mst, &mst->i2c_write_buffer[4], 0, 0);
+ mst->msg[num + 1].addr = mst->i2c_addr;
+ mst->msg[num + 1].buf = &mst->i2c_write_buffer[4];
+ mst->msg[num + 1].len = 4;
- return i2c_transfer(mst->i2c_adap, m, 2 + num) == 2 + num ? num : -EIO;
+ return i2c_transfer(mst->i2c_adap, mst->msg, 2 + num) == 2 + num ? num : -EIO;
}
static struct i2c_algorithm dibx000_i2c_gated_gpio67_algo = {
@@ -279,26 +294,32 @@
struct i2c_msg msg[], int num)
{
struct dibx000_i2c_master *mst = i2c_get_adapdata(i2c_adap);
- struct i2c_msg m[2 + num];
- u8 tx_open[4], tx_close[4];
- memset(m, 0, sizeof(struct i2c_msg) * (2 + num));
+ if (num > 32) {
+ dprintk("%s: too much I2C message to be transmitted (%i).\
+ Maximum is 32", __func__, num);
+ return -ENOMEM;
+ }
+
+ memset(mst->msg, 0, sizeof(struct i2c_msg) * (2 + num));
dibx000_i2c_select_interface(mst, DIBX000_I2C_INTERFACE_TUNER);
- dibx000_i2c_gate_ctrl(mst, tx_open, msg[0].addr, 1);
- m[0].addr = mst->i2c_addr;
- m[0].buf = tx_open;
- m[0].len = 4;
+ /* open the gate */
+ dibx000_i2c_gate_ctrl(mst, &mst->i2c_write_buffer[0], msg[0].addr, 1);
+ mst->msg[0].addr = mst->i2c_addr;
+ mst->msg[0].buf = &mst->i2c_write_buffer[0];
+ mst->msg[0].len = 4;
- memcpy(&m[1], msg, sizeof(struct i2c_msg) * num);
+ memcpy(&mst->msg[1], msg, sizeof(struct i2c_msg) * num);
- dibx000_i2c_gate_ctrl(mst, tx_close, 0, 0);
- m[num + 1].addr = mst->i2c_addr;
- m[num + 1].buf = tx_close;
- m[num + 1].len = 4;
+ /* close the gate */
+ dibx000_i2c_gate_ctrl(mst, &mst->i2c_write_buffer[4], 0, 0);
+ mst->msg[num + 1].addr = mst->i2c_addr;
+ mst->msg[num + 1].buf = &mst->i2c_write_buffer[4];
+ mst->msg[num + 1].len = 4;
- return i2c_transfer(mst->i2c_adap, m, 2 + num) == 2 + num ? num : -EIO;
+ return i2c_transfer(mst->i2c_adap, mst->msg, 2 + num) == 2 + num ? num : -EIO;
}
static struct i2c_algorithm dibx000_i2c_gated_tuner_algo = {
diff --git a/drivers/media/dvb/frontends/dibx000_common.h b/drivers/media/dvb/frontends/dibx000_common.h
index 977d343..f031165 100644
--- a/drivers/media/dvb/frontends/dibx000_common.h
+++ b/drivers/media/dvb/frontends/dibx000_common.h
@@ -28,6 +28,11 @@
u8 i2c_addr;
u16 base_reg;
+
+ /* for the I2C transfer */
+ struct i2c_msg msg[34];
+ u8 i2c_write_buffer[8];
+ u8 i2c_read_buffer[2];
};
extern int dibx000_init_i2c_master(struct dibx000_i2c_master *mst,
diff --git a/drivers/media/dvb/frontends/drx397xD.c b/drivers/media/dvb/frontends/drx397xD.c
deleted file mode 100644
index 536f02b..0000000
--- a/drivers/media/dvb/frontends/drx397xD.c
+++ /dev/null
@@ -1,1511 +0,0 @@
-/*
- * Driver for Micronas drx397xD demodulator
- *
- * Copyright (C) 2007 Henk Vergonet <Henk.Vergonet@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; If not, see <http://www.gnu.org/licenses/>.
- */
-
-#define DEBUG /* uncomment if you want debugging output */
-#include <linux/kernel.h>
-#include <linux/module.h>
-#include <linux/moduleparam.h>
-#include <linux/init.h>
-#include <linux/device.h>
-#include <linux/delay.h>
-#include <linux/string.h>
-#include <linux/firmware.h>
-#include <linux/slab.h>
-#include <asm/div64.h>
-
-#include "dvb_frontend.h"
-#include "drx397xD.h"
-
-static const char mod_name[] = "drx397xD";
-
-#define MAX_CLOCK_DRIFT 200 /* maximal 200 PPM allowed */
-
-#define F_SET_0D0h 1
-#define F_SET_0D4h 2
-
-enum fw_ix {
-#define _FW_ENTRY(a, b, c) b
-#include "drx397xD_fw.h"
-};
-
-/* chip specifics */
-struct drx397xD_state {
- struct i2c_adapter *i2c;
- struct dvb_frontend frontend;
- struct drx397xD_config config;
- enum fw_ix chip_rev;
- int flags;
- u32 bandwidth_parm; /* internal bandwidth conversions */
- u32 f_osc; /* w90: actual osc frequency [Hz] */
-};
-
-/* Firmware */
-static const char *blob_name[] = {
-#define _BLOB_ENTRY(a, b) a
-#include "drx397xD_fw.h"
-};
-
-enum blob_ix {
-#define _BLOB_ENTRY(a, b) b
-#include "drx397xD_fw.h"
-};
-
-static struct {
- const char *name;
- const struct firmware *file;
- rwlock_t lock;
- int refcnt;
- const u8 *data[ARRAY_SIZE(blob_name)];
-} fw[] = {
-#define _FW_ENTRY(a, b, c) { \
- .name = a, \
- .file = NULL, \
- .lock = __RW_LOCK_UNLOCKED(fw[c].lock), \
- .refcnt = 0, \
- .data = { } }
-#include "drx397xD_fw.h"
-};
-
-/* use only with writer lock acquired */
-static void _drx_release_fw(struct drx397xD_state *s, enum fw_ix ix)
-{
- memset(&fw[ix].data[0], 0, sizeof(fw[0].data));
- if (fw[ix].file)
- release_firmware(fw[ix].file);
-}
-
-static void drx_release_fw(struct drx397xD_state *s)
-{
- enum fw_ix ix = s->chip_rev;
-
- pr_debug("%s\n", __func__);
-
- write_lock(&fw[ix].lock);
- if (fw[ix].refcnt) {
- fw[ix].refcnt--;
- if (fw[ix].refcnt == 0)
- _drx_release_fw(s, ix);
- }
- write_unlock(&fw[ix].lock);
-}
-
-static int drx_load_fw(struct drx397xD_state *s, enum fw_ix ix)
-{
- const u8 *data;
- size_t size, len;
- int i = 0, j, rc = -EINVAL;
-
- pr_debug("%s\n", __func__);
-
- if (ix < 0 || ix >= ARRAY_SIZE(fw))
- return -EINVAL;
- s->chip_rev = ix;
-
- write_lock(&fw[ix].lock);
- if (fw[ix].file) {
- rc = 0;
- goto exit_ok;
- }
- memset(&fw[ix].data[0], 0, sizeof(fw[0].data));
-
- rc = request_firmware(&fw[ix].file, fw[ix].name, s->i2c->dev.parent);
- if (rc != 0) {
- printk(KERN_ERR "%s: Firmware \"%s\" not available\n",
- mod_name, fw[ix].name);
- goto exit_err;
- }
-
- if (!fw[ix].file->data || fw[ix].file->size < 10)
- goto exit_corrupt;
-
- data = fw[ix].file->data;
- size = fw[ix].file->size;
-
- if (data[i++] != 2) /* check firmware version */
- goto exit_corrupt;
-
- do {
- switch (data[i++]) {
- case 0x00: /* bytecode */
- if (i >= size)
- break;
- i += data[i];
- case 0x01: /* reset */
- case 0x02: /* sleep */
- i++;
- break;
- case 0xfe: /* name */
- len = strnlen(&data[i], size - i);
- if (i + len + 1 >= size)
- goto exit_corrupt;
- if (data[i + len + 1] != 0)
- goto exit_corrupt;
- for (j = 0; j < ARRAY_SIZE(blob_name); j++) {
- if (strcmp(blob_name[j], &data[i]) == 0) {
- fw[ix].data[j] = &data[i + len + 1];
- pr_debug("Loading %s\n", blob_name[j]);
- }
- }
- i += len + 1;
- break;
- case 0xff: /* file terminator */
- if (i == size) {
- rc = 0;
- goto exit_ok;
- }
- default:
- goto exit_corrupt;
- }
- } while (i < size);
-
-exit_corrupt:
- printk(KERN_ERR "%s: Firmware is corrupt\n", mod_name);
-exit_err:
- _drx_release_fw(s, ix);
- fw[ix].refcnt--;
-exit_ok:
- fw[ix].refcnt++;
- write_unlock(&fw[ix].lock);
-
- return rc;
-}
-
-/* i2c bus IO */
-static int write_fw(struct drx397xD_state *s, enum blob_ix ix)
-{
- const u8 *data;
- int len, rc = 0, i = 0;
- struct i2c_msg msg = {
- .addr = s->config.demod_address,
- .flags = 0
- };
-
- if (ix < 0 || ix >= ARRAY_SIZE(blob_name)) {
- pr_debug("%s drx_fw_ix_t out of range\n", __func__);
- return -EINVAL;
- }
- pr_debug("%s %s\n", __func__, blob_name[ix]);
-
- read_lock(&fw[s->chip_rev].lock);
- data = fw[s->chip_rev].data[ix];
- if (!data) {
- rc = -EINVAL;
- goto exit_rc;
- }
-
- for (;;) {
- switch (data[i++]) {
- case 0: /* bytecode */
- len = data[i++];
- msg.len = len;
- msg.buf = (__u8 *) &data[i];
- if (i2c_transfer(s->i2c, &msg, 1) != 1) {
- rc = -EIO;
- goto exit_rc;
- }
- i += len;
- break;
- case 1: /* reset */
- case 2: /* sleep */
- i++;
- break;
- default:
- goto exit_rc;
- }
- }
-exit_rc:
- read_unlock(&fw[s->chip_rev].lock);
-
- return rc;
-}
-
-/* Function is not endian safe, use the RD16 wrapper below */
-static int _read16(struct drx397xD_state *s, __le32 i2c_adr)
-{
- int rc;
- u8 a[4];
- __le16 v;
- struct i2c_msg msg[2] = {
- {
- .addr = s->config.demod_address,
- .flags = 0,
- .buf = a,
- .len = sizeof(a)
- }, {
- .addr = s->config.demod_address,
- .flags = I2C_M_RD,
- .buf = (u8 *)&v,
- .len = sizeof(v)
- }
- };
-
- *(__le32 *) a = i2c_adr;
-
- rc = i2c_transfer(s->i2c, msg, 2);
- if (rc != 2)
- return -EIO;
-
- return le16_to_cpu(v);
-}
-
-/* Function is not endian safe, use the WR16.. wrappers below */
-static int _write16(struct drx397xD_state *s, __le32 i2c_adr, __le16 val)
-{
- u8 a[6];
- int rc;
- struct i2c_msg msg = {
- .addr = s->config.demod_address,
- .flags = 0,
- .buf = a,
- .len = sizeof(a)
- };
-
- *(__le32 *)a = i2c_adr;
- *(__le16 *)&a[4] = val;
-
- rc = i2c_transfer(s->i2c, &msg, 1);
- if (rc != 1)
- return -EIO;
-
- return 0;
-}
-
-#define WR16(ss, adr, val) \
- _write16(ss, I2C_ADR_C0(adr), cpu_to_le16(val))
-#define WR16_E0(ss, adr, val) \
- _write16(ss, I2C_ADR_E0(adr), cpu_to_le16(val))
-#define RD16(ss, adr) \
- _read16(ss, I2C_ADR_C0(adr))
-
-#define EXIT_RC(cmd) \
- if ((rc = (cmd)) < 0) \
- goto exit_rc
-
-/* Tuner callback */
-static int PLL_Set(struct drx397xD_state *s,
- struct dvb_frontend_parameters *fep, int *df_tuner)
-{
- struct dvb_frontend *fe = &s->frontend;
- u32 f_tuner, f = fep->frequency;
- int rc;
-
- pr_debug("%s\n", __func__);
-
- if ((f > s->frontend.ops.tuner_ops.info.frequency_max) ||
- (f < s->frontend.ops.tuner_ops.info.frequency_min))
- return -EINVAL;
-
- *df_tuner = 0;
- if (!s->frontend.ops.tuner_ops.set_params ||
- !s->frontend.ops.tuner_ops.get_frequency)
- return -ENOSYS;
-
- rc = s->frontend.ops.tuner_ops.set_params(fe, fep);
- if (rc < 0)
- return rc;
-
- rc = s->frontend.ops.tuner_ops.get_frequency(fe, &f_tuner);
- if (rc < 0)
- return rc;
-
- *df_tuner = f_tuner - f;
- pr_debug("%s requested %d [Hz] tuner %d [Hz]\n", __func__, f,
- f_tuner);
-
- return 0;
-}
-
-/* Demodulator helper functions */
-static int SC_WaitForReady(struct drx397xD_state *s)
-{
- int cnt = 1000;
- int rc;
-
- pr_debug("%s\n", __func__);
-
- while (cnt--) {
- rc = RD16(s, 0x820043);
- if (rc == 0)
- return 0;
- }
-
- return -1;
-}
-
-static int SC_SendCommand(struct drx397xD_state *s, int cmd)
-{
- int rc;
-
- pr_debug("%s\n", __func__);
-
- WR16(s, 0x820043, cmd);
- SC_WaitForReady(s);
- rc = RD16(s, 0x820042);
- if ((rc & 0xffff) == 0xffff)
- return -1;
-
- return 0;
-}
-
-static int HI_Command(struct drx397xD_state *s, u16 cmd)
-{
- int rc, cnt = 1000;
-
- pr_debug("%s\n", __func__);
-
- rc = WR16(s, 0x420032, cmd);
- if (rc < 0)
- return rc;
-
- do {
- rc = RD16(s, 0x420032);
- if (rc == 0) {
- rc = RD16(s, 0x420031);
- return rc;
- }
- if (rc < 0)
- return rc;
- } while (--cnt);
-
- return rc;
-}
-
-static int HI_CfgCommand(struct drx397xD_state *s)
-{
-
- pr_debug("%s\n", __func__);
-
- WR16(s, 0x420033, 0x3973);
- WR16(s, 0x420034, s->config.w50); /* code 4, log 4 */
- WR16(s, 0x420035, s->config.w52); /* code 15, log 9 */
- WR16(s, 0x420036, s->config.demod_address << 1);
- WR16(s, 0x420037, s->config.w56); /* code (set_i2c ?? initX 1 ), log 1 */
- /* WR16(s, 0x420033, 0x3973); */
- if ((s->config.w56 & 8) == 0)
- return HI_Command(s, 3);
-
- return WR16(s, 0x420032, 0x3);
-}
-
-static const u8 fastIncrDecLUT_15273[] = {
- 0x0e, 0x0f, 0x0f, 0x10, 0x11, 0x12, 0x12, 0x13, 0x14,
- 0x15, 0x16, 0x17, 0x18, 0x1a, 0x1b, 0x1c, 0x1d, 0x1f
-};
-
-static const u8 slowIncrDecLUT_15272[] = {
- 3, 4, 4, 5, 6
-};
-
-static int SetCfgIfAgc(struct drx397xD_state *s, struct drx397xD_CfgIfAgc *agc)
-{
- u16 w06 = agc->w06;
- u16 w08 = agc->w08;
- u16 w0A = agc->w0A;
- u16 w0C = agc->w0C;
- int quot, rem, i, rc = -EINVAL;
-
- pr_debug("%s\n", __func__);
-
- if (agc->w04 > 0x3ff)
- goto exit_rc;
-
- if (agc->d00 == 1) {
- EXIT_RC(RD16(s, 0x0c20010));
- rc &= ~0x10;
- EXIT_RC(WR16(s, 0x0c20010, rc));
- return WR16(s, 0x0c20030, agc->w04 & 0x7ff);
- }
-
- if (agc->d00 != 0)
- goto exit_rc;
- if (w0A < w08)
- goto exit_rc;
- if (w0A > 0x3ff)
- goto exit_rc;
- if (w0C > 0x3ff)
- goto exit_rc;
- if (w06 > 0x3ff)
- goto exit_rc;
-
- EXIT_RC(RD16(s, 0x0c20010));
- rc |= 0x10;
- EXIT_RC(WR16(s, 0x0c20010, rc));
-
- EXIT_RC(WR16(s, 0x0c20025, (w06 >> 1) & 0x1ff));
- EXIT_RC(WR16(s, 0x0c20031, (w0A - w08) >> 1));
- EXIT_RC(WR16(s, 0x0c20032, ((w0A + w08) >> 1) - 0x1ff));
-
- quot = w0C / 113;
- rem = w0C % 113;
- if (quot <= 8) {
- quot = 8 - quot;
- } else {
- quot = 0;
- rem += 113;
- }
-
- EXIT_RC(WR16(s, 0x0c20024, quot));
-
- i = fastIncrDecLUT_15273[rem / 8];
- EXIT_RC(WR16(s, 0x0c2002d, i));
- EXIT_RC(WR16(s, 0x0c2002e, i));
-
- i = slowIncrDecLUT_15272[rem / 28];
- EXIT_RC(WR16(s, 0x0c2002b, i));
- rc = WR16(s, 0x0c2002c, i);
-exit_rc:
- return rc;
-}
-
-static int SetCfgRfAgc(struct drx397xD_state *s, struct drx397xD_CfgRfAgc *agc)
-{
- u16 w04 = agc->w04;
- u16 w06 = agc->w06;
- int rc = -1;
-
- pr_debug("%s %d 0x%x 0x%x\n", __func__, agc->d00, w04, w06);
-
- if (w04 > 0x3ff)
- goto exit_rc;
-
- switch (agc->d00) {
- case 1:
- if (w04 == 0x3ff)
- w04 = 0x400;
-
- EXIT_RC(WR16(s, 0x0c20036, w04));
- s->config.w9C &= ~2;
- EXIT_RC(WR16(s, 0x0c20015, s->config.w9C));
- EXIT_RC(RD16(s, 0x0c20010));
- rc &= 0xbfdf;
- EXIT_RC(WR16(s, 0x0c20010, rc));
- EXIT_RC(RD16(s, 0x0c20013));
- rc &= ~2;
- break;
- case 0:
- /* loc_8000659 */
- s->config.w9C &= ~2;
- EXIT_RC(WR16(s, 0x0c20015, s->config.w9C));
- EXIT_RC(RD16(s, 0x0c20010));
- rc &= 0xbfdf;
- rc |= 0x4000;
- EXIT_RC(WR16(s, 0x0c20010, rc));
- EXIT_RC(WR16(s, 0x0c20051, (w06 >> 4) & 0x3f));
- EXIT_RC(RD16(s, 0x0c20013));
- rc &= ~2;
- break;
- default:
- s->config.w9C |= 2;
- EXIT_RC(WR16(s, 0x0c20015, s->config.w9C));
- EXIT_RC(RD16(s, 0x0c20010));
- rc &= 0xbfdf;
- EXIT_RC(WR16(s, 0x0c20010, rc));
-
- EXIT_RC(WR16(s, 0x0c20036, 0));
-
- EXIT_RC(RD16(s, 0x0c20013));
- rc |= 2;
- }
- rc = WR16(s, 0x0c20013, rc);
-
-exit_rc:
- return rc;
-}
-
-static int GetLockStatus(struct drx397xD_state *s, int *lockstat)
-{
- int rc;
-
- *lockstat = 0;
-
- rc = RD16(s, 0x082004b);
- if (rc < 0)
- return rc;
-
- if (s->config.d60 != 2)
- return 0;
-
- if ((rc & 7) == 7)
- *lockstat |= 1;
- if ((rc & 3) == 3)
- *lockstat |= 2;
- if (rc & 1)
- *lockstat |= 4;
- return 0;
-}
-
-static int CorrectSysClockDeviation(struct drx397xD_state *s)
-{
- int rc = -EINVAL;
- int lockstat;
- u32 clk, clk_limit;
-
- pr_debug("%s\n", __func__);
-
- if (s->config.d5C == 0) {
- EXIT_RC(WR16(s, 0x08200e8, 0x010));
- EXIT_RC(WR16(s, 0x08200e9, 0x113));
- s->config.d5C = 1;
- return rc;
- }
- if (s->config.d5C != 1)
- goto exit_rc;
-
- rc = RD16(s, 0x0820048);
-
- rc = GetLockStatus(s, &lockstat);
- if (rc < 0)
- goto exit_rc;
- if ((lockstat & 1) == 0)
- goto exit_rc;
-
- EXIT_RC(WR16(s, 0x0420033, 0x200));
- EXIT_RC(WR16(s, 0x0420034, 0xc5));
- EXIT_RC(WR16(s, 0x0420035, 0x10));
- EXIT_RC(WR16(s, 0x0420036, 0x1));
- EXIT_RC(WR16(s, 0x0420037, 0xa));
- EXIT_RC(HI_Command(s, 6));
- EXIT_RC(RD16(s, 0x0420040));
- clk = rc;
- EXIT_RC(RD16(s, 0x0420041));
- clk |= rc << 16;
-
- if (clk <= 0x26ffff)
- goto exit_rc;
- if (clk > 0x610000)
- goto exit_rc;
-
- if (!s->bandwidth_parm)
- return -EINVAL;
-
- /* round & convert to Hz */
- clk = ((u64) (clk + 0x800000) * s->bandwidth_parm + (1 << 20)) >> 21;
- clk_limit = s->config.f_osc * MAX_CLOCK_DRIFT / 1000;
-
- if (clk - s->config.f_osc * 1000 + clk_limit <= 2 * clk_limit) {
- s->f_osc = clk;
- pr_debug("%s: osc %d %d [Hz]\n", __func__,
- s->config.f_osc * 1000, clk - s->config.f_osc * 1000);
- }
- rc = WR16(s, 0x08200e8, 0);
-
-exit_rc:
- return rc;
-}
-
-static int ConfigureMPEGOutput(struct drx397xD_state *s, int type)
-{
- int rc, si, bp;
-
- pr_debug("%s\n", __func__);
-
- si = s->config.wA0;
- if (s->config.w98 == 0) {
- si |= 1;
- bp = 0;
- } else {
- si &= ~1;
- bp = 0x200;
- }
- if (s->config.w9A == 0)
- si |= 0x80;
- else
- si &= ~0x80;
-
- EXIT_RC(WR16(s, 0x2150045, 0));
- EXIT_RC(WR16(s, 0x2150010, si));
- EXIT_RC(WR16(s, 0x2150011, bp));
- rc = WR16(s, 0x2150012, (type == 0 ? 0xfff : 0));
-
-exit_rc:
- return rc;
-}
-
-static int drx_tune(struct drx397xD_state *s,
- struct dvb_frontend_parameters *fep)
-{
- u16 v22 = 0;
- u16 v1C = 0;
- u16 v1A = 0;
- u16 v18 = 0;
- u32 edi = 0, ebx = 0, ebp = 0, edx = 0;
- u16 v20 = 0, v1E = 0, v16 = 0, v14 = 0, v12 = 0, v10 = 0, v0E = 0;
-
- int rc, df_tuner = 0;
- int a, b, c, d;
- pr_debug("%s %d\n", __func__, s->config.d60);
-
- if (s->config.d60 != 2)
- goto set_tuner;
- rc = CorrectSysClockDeviation(s);
- if (rc < 0)
- goto set_tuner;
-
- s->config.d60 = 1;
- rc = ConfigureMPEGOutput(s, 0);
- if (rc < 0)
- goto set_tuner;
-set_tuner:
-
- rc = PLL_Set(s, fep, &df_tuner);
- if (rc < 0) {
- printk(KERN_ERR "Error in pll_set\n");
- goto exit_rc;
- }
- msleep(200);
-
- a = rc = RD16(s, 0x2150016);
- if (rc < 0)
- goto exit_rc;
- b = rc = RD16(s, 0x2150010);
- if (rc < 0)
- goto exit_rc;
- c = rc = RD16(s, 0x2150034);
- if (rc < 0)
- goto exit_rc;
- d = rc = RD16(s, 0x2150035);
- if (rc < 0)
- goto exit_rc;
- rc = WR16(s, 0x2150014, c);
- rc = WR16(s, 0x2150015, d);
- rc = WR16(s, 0x2150010, 0);
- rc = WR16(s, 0x2150000, 2);
- rc = WR16(s, 0x2150036, 0x0fff);
- rc = WR16(s, 0x2150016, a);
-
- rc = WR16(s, 0x2150010, 2);
- rc = WR16(s, 0x2150007, 0);
- rc = WR16(s, 0x2150000, 1);
- rc = WR16(s, 0x2110000, 0);
- rc = WR16(s, 0x0800000, 0);
- rc = WR16(s, 0x2800000, 0);
- rc = WR16(s, 0x2110010, 0x664);
-
- rc = write_fw(s, DRXD_ResetECRAM);
- rc = WR16(s, 0x2110000, 1);
-
- rc = write_fw(s, DRXD_InitSC);
- if (rc < 0)
- goto exit_rc;
-
- rc = SetCfgIfAgc(s, &s->config.ifagc);
- if (rc < 0)
- goto exit_rc;
-
- rc = SetCfgRfAgc(s, &s->config.rfagc);
- if (rc < 0)
- goto exit_rc;
-
- if (fep->u.ofdm.transmission_mode != TRANSMISSION_MODE_2K)
- v22 = 1;
- switch (fep->u.ofdm.transmission_mode) {
- case TRANSMISSION_MODE_8K:
- edi = 1;
- if (s->chip_rev == DRXD_FW_B1)
- break;
-
- rc = WR16(s, 0x2010010, 0);
- if (rc < 0)
- break;
- v1C = 0x63;
- v1A = 0x53;
- v18 = 0x43;
- break;
- default:
- edi = 0;
- if (s->chip_rev == DRXD_FW_B1)
- break;
-
- rc = WR16(s, 0x2010010, 1);
- if (rc < 0)
- break;
-
- v1C = 0x61;
- v1A = 0x47;
- v18 = 0x41;
- }
-
- switch (fep->u.ofdm.guard_interval) {
- case GUARD_INTERVAL_1_4:
- edi |= 0x0c;
- break;
- case GUARD_INTERVAL_1_8:
- edi |= 0x08;
- break;
- case GUARD_INTERVAL_1_16:
- edi |= 0x04;
- break;
- case GUARD_INTERVAL_1_32:
- break;
- default:
- v22 |= 2;
- }
-
- ebx = 0;
- ebp = 0;
- v20 = 0;
- v1E = 0;
- v16 = 0;
- v14 = 0;
- v12 = 0;
- v10 = 0;
- v0E = 0;
-
- switch (fep->u.ofdm.hierarchy_information) {
- case HIERARCHY_1:
- edi |= 0x40;
- if (s->chip_rev == DRXD_FW_B1)
- break;
- rc = WR16(s, 0x1c10047, 1);
- if (rc < 0)
- goto exit_rc;
- rc = WR16(s, 0x2010012, 1);
- if (rc < 0)
- goto exit_rc;
- ebx = 0x19f;
- ebp = 0x1fb;
- v20 = 0x0c0;
- v1E = 0x195;
- v16 = 0x1d6;
- v14 = 0x1ef;
- v12 = 4;
- v10 = 5;
- v0E = 5;
- break;
- case HIERARCHY_2:
- edi |= 0x80;
- if (s->chip_rev == DRXD_FW_B1)
- break;
- rc = WR16(s, 0x1c10047, 2);
- if (rc < 0)
- goto exit_rc;
- rc = WR16(s, 0x2010012, 2);
- if (rc < 0)
- goto exit_rc;
- ebx = 0x08f;
- ebp = 0x12f;
- v20 = 0x0c0;
- v1E = 0x11e;
- v16 = 0x1d6;
- v14 = 0x15e;
- v12 = 4;
- v10 = 5;
- v0E = 5;
- break;
- case HIERARCHY_4:
- edi |= 0xc0;
- if (s->chip_rev == DRXD_FW_B1)
- break;
- rc = WR16(s, 0x1c10047, 3);
- if (rc < 0)
- goto exit_rc;
- rc = WR16(s, 0x2010012, 3);
- if (rc < 0)
- goto exit_rc;
- ebx = 0x14d;
- ebp = 0x197;
- v20 = 0x0c0;
- v1E = 0x1ce;
- v16 = 0x1d6;
- v14 = 0x11a;
- v12 = 4;
- v10 = 6;
- v0E = 5;
- break;
- default:
- v22 |= 8;
- if (s->chip_rev == DRXD_FW_B1)
- break;
- rc = WR16(s, 0x1c10047, 0);
- if (rc < 0)
- goto exit_rc;
- rc = WR16(s, 0x2010012, 0);
- if (rc < 0)
- goto exit_rc;
- /* QPSK QAM16 QAM64 */
- ebx = 0x19f; /* 62 */
- ebp = 0x1fb; /* 15 */
- v20 = 0x16a; /* 62 */
- v1E = 0x195; /* 62 */
- v16 = 0x1bb; /* 15 */
- v14 = 0x1ef; /* 15 */
- v12 = 5; /* 16 */
- v10 = 5; /* 16 */
- v0E = 5; /* 16 */
- }
-
- switch (fep->u.ofdm.constellation) {
- default:
- v22 |= 4;
- case QPSK:
- if (s->chip_rev == DRXD_FW_B1)
- break;
-
- rc = WR16(s, 0x1c10046, 0);
- if (rc < 0)
- goto exit_rc;
- rc = WR16(s, 0x2010011, 0);
- if (rc < 0)
- goto exit_rc;
- rc = WR16(s, 0x201001a, 0x10);
- if (rc < 0)
- goto exit_rc;
- rc = WR16(s, 0x201001b, 0);
- if (rc < 0)
- goto exit_rc;
- rc = WR16(s, 0x201001c, 0);
- if (rc < 0)
- goto exit_rc;
- rc = WR16(s, 0x1c10062, v20);
- if (rc < 0)
- goto exit_rc;
- rc = WR16(s, 0x1c1002a, v1C);
- if (rc < 0)
- goto exit_rc;
- rc = WR16(s, 0x1c10015, v16);
- if (rc < 0)
- goto exit_rc;
- rc = WR16(s, 0x1c10016, v12);
- if (rc < 0)
- goto exit_rc;
- break;
- case QAM_16:
- edi |= 0x10;
- if (s->chip_rev == DRXD_FW_B1)
- break;
-
- rc = WR16(s, 0x1c10046, 1);
- if (rc < 0)
- goto exit_rc;
- rc = WR16(s, 0x2010011, 1);
- if (rc < 0)
- goto exit_rc;
- rc = WR16(s, 0x201001a, 0x10);
- if (rc < 0)
- goto exit_rc;
- rc = WR16(s, 0x201001b, 4);
- if (rc < 0)
- goto exit_rc;
- rc = WR16(s, 0x201001c, 0);
- if (rc < 0)
- goto exit_rc;
- rc = WR16(s, 0x1c10062, v1E);
- if (rc < 0)
- goto exit_rc;
- rc = WR16(s, 0x1c1002a, v1A);
- if (rc < 0)
- goto exit_rc;
- rc = WR16(s, 0x1c10015, v14);
- if (rc < 0)
- goto exit_rc;
- rc = WR16(s, 0x1c10016, v10);
- if (rc < 0)
- goto exit_rc;
- break;
- case QAM_64:
- edi |= 0x20;
- rc = WR16(s, 0x1c10046, 2);
- if (rc < 0)
- goto exit_rc;
- rc = WR16(s, 0x2010011, 2);
- if (rc < 0)
- goto exit_rc;
- rc = WR16(s, 0x201001a, 0x20);
- if (rc < 0)
- goto exit_rc;
- rc = WR16(s, 0x201001b, 8);
- if (rc < 0)
- goto exit_rc;
- rc = WR16(s, 0x201001c, 2);
- if (rc < 0)
- goto exit_rc;
- rc = WR16(s, 0x1c10062, ebx);
- if (rc < 0)
- goto exit_rc;
- rc = WR16(s, 0x1c1002a, v18);
- if (rc < 0)
- goto exit_rc;
- rc = WR16(s, 0x1c10015, ebp);
- if (rc < 0)
- goto exit_rc;
- rc = WR16(s, 0x1c10016, v0E);
- if (rc < 0)
- goto exit_rc;
- break;
- }
-
- if (s->config.s20d24 == 1) {
- rc = WR16(s, 0x2010013, 0);
- } else {
- rc = WR16(s, 0x2010013, 1);
- edi |= 0x1000;
- }
-
- switch (fep->u.ofdm.code_rate_HP) {
- default:
- v22 |= 0x10;
- case FEC_1_2:
- if (s->chip_rev == DRXD_FW_B1)
- break;
- rc = WR16(s, 0x2090011, 0);
- break;
- case FEC_2_3:
- edi |= 0x200;
- if (s->chip_rev == DRXD_FW_B1)
- break;
- rc = WR16(s, 0x2090011, 1);
- break;
- case FEC_3_4:
- edi |= 0x400;
- if (s->chip_rev == DRXD_FW_B1)
- break;
- rc = WR16(s, 0x2090011, 2);
- break;
- case FEC_5_6: /* 5 */
- edi |= 0x600;
- if (s->chip_rev == DRXD_FW_B1)
- break;
- rc = WR16(s, 0x2090011, 3);
- break;
- case FEC_7_8: /* 7 */
- edi |= 0x800;
- if (s->chip_rev == DRXD_FW_B1)
- break;
- rc = WR16(s, 0x2090011, 4);
- break;
- };
- if (rc < 0)
- goto exit_rc;
-
- switch (fep->u.ofdm.bandwidth) {
- default:
- rc = -EINVAL;
- goto exit_rc;
- case BANDWIDTH_8_MHZ: /* 0 */
- case BANDWIDTH_AUTO:
- rc = WR16(s, 0x0c2003f, 0x32);
- s->bandwidth_parm = ebx = 0x8b8249;
- edx = 0;
- break;
- case BANDWIDTH_7_MHZ:
- rc = WR16(s, 0x0c2003f, 0x3b);
- s->bandwidth_parm = ebx = 0x7a1200;
- edx = 0x4807;
- break;
- case BANDWIDTH_6_MHZ:
- rc = WR16(s, 0x0c2003f, 0x47);
- s->bandwidth_parm = ebx = 0x68a1b6;
- edx = 0x0f07;
- break;
- };
-
- if (rc < 0)
- goto exit_rc;
-
- rc = WR16(s, 0x08200ec, edx);
- if (rc < 0)
- goto exit_rc;
-
- rc = RD16(s, 0x0820050);
- if (rc < 0)
- goto exit_rc;
- rc = WR16(s, 0x0820050, rc);
-
- {
- /* Configure bandwidth specific factor */
- ebx = div64_u64(((u64) (s->f_osc) << 21) + (ebx >> 1),
- (u64)ebx) - 0x800000;
- EXIT_RC(WR16(s, 0x0c50010, ebx & 0xffff));
- EXIT_RC(WR16(s, 0x0c50011, ebx >> 16));
-
- /* drx397xD oscillator calibration */
- ebx = div64_u64(((u64) (s->config.f_if + df_tuner) << 28) +
- (s->f_osc >> 1), (u64)s->f_osc);
- }
- ebx &= 0xfffffff;
- if (fep->inversion == INVERSION_ON)
- ebx = 0x10000000 - ebx;
-
- EXIT_RC(WR16(s, 0x0c30010, ebx & 0xffff));
- EXIT_RC(WR16(s, 0x0c30011, ebx >> 16));
-
- EXIT_RC(WR16(s, 0x0800000, 1));
- EXIT_RC(RD16(s, 0x0800000));
-
-
- EXIT_RC(SC_WaitForReady(s));
- EXIT_RC(WR16(s, 0x0820042, 0));
- EXIT_RC(WR16(s, 0x0820041, v22));
- EXIT_RC(WR16(s, 0x0820040, edi));
- EXIT_RC(SC_SendCommand(s, 3));
-
- rc = RD16(s, 0x0800000);
-
- SC_WaitForReady(s);
- WR16(s, 0x0820042, 0);
- WR16(s, 0x0820041, 1);
- WR16(s, 0x0820040, 1);
- SC_SendCommand(s, 1);
-
-
- rc = WR16(s, 0x2150000, 2);
- rc = WR16(s, 0x2150016, a);
- rc = WR16(s, 0x2150010, 4);
- rc = WR16(s, 0x2150036, 0);
- rc = WR16(s, 0x2150000, 1);
- s->config.d60 = 2;
-
-exit_rc:
- return rc;
-}
-
-/*******************************************************************************
- * DVB interface
- ******************************************************************************/
-
-static int drx397x_init(struct dvb_frontend *fe)
-{
- struct drx397xD_state *s = fe->demodulator_priv;
- int rc;
-
- pr_debug("%s\n", __func__);
-
- s->config.rfagc.d00 = 2; /* 0x7c */
- s->config.rfagc.w04 = 0;
- s->config.rfagc.w06 = 0x3ff;
-
- s->config.ifagc.d00 = 0; /* 0x68 */
- s->config.ifagc.w04 = 0;
- s->config.ifagc.w06 = 140;
- s->config.ifagc.w08 = 0;
- s->config.ifagc.w0A = 0x3ff;
- s->config.ifagc.w0C = 0x388;
-
- /* for signal strength calculations */
- s->config.ss76 = 820;
- s->config.ss78 = 2200;
- s->config.ss7A = 150;
-
- /* HI_CfgCommand */
- s->config.w50 = 4;
- s->config.w52 = 9;
-
- s->config.f_if = 42800000; /* d14: intermediate frequency [Hz] */
- s->config.f_osc = 48000; /* s66 : oscillator frequency [kHz] */
- s->config.w92 = 12000;
-
- s->config.w9C = 0x000e;
- s->config.w9E = 0x0000;
-
- /* ConfigureMPEGOutput params */
- s->config.wA0 = 4;
- s->config.w98 = 1;
- s->config.w9A = 1;
-
- /* get chip revision */
- rc = RD16(s, 0x2410019);
- if (rc < 0)
- return -ENODEV;
-
- if (rc == 0) {
- printk(KERN_INFO "%s: chip revision A2\n", mod_name);
- rc = drx_load_fw(s, DRXD_FW_A2);
- } else {
-
- rc = (rc >> 12) - 3;
- switch (rc) {
- case 1:
- s->flags |= F_SET_0D4h;
- case 0:
- case 4:
- s->flags |= F_SET_0D0h;
- break;
- case 2:
- case 5:
- break;
- case 3:
- s->flags |= F_SET_0D4h;
- break;
- default:
- return -ENODEV;
- };
- printk(KERN_INFO "%s: chip revision B1.%d\n", mod_name, rc);
- rc = drx_load_fw(s, DRXD_FW_B1);
- }
- if (rc < 0)
- goto error;
-
- rc = WR16(s, 0x0420033, 0x3973);
- if (rc < 0)
- goto error;
-
- rc = HI_Command(s, 2);
-
- msleep(1);
-
- if (s->chip_rev == DRXD_FW_A2) {
- rc = WR16(s, 0x043012d, 0x47F);
- if (rc < 0)
- goto error;
- }
- rc = WR16_E0(s, 0x0400000, 0);
- if (rc < 0)
- goto error;
-
- if (s->config.w92 > 20000 || s->config.w92 % 4000) {
- printk(KERN_ERR "%s: invalid osc frequency\n", mod_name);
- rc = -1;
- goto error;
- }
-
- rc = WR16(s, 0x2410010, 1);
- if (rc < 0)
- goto error;
- rc = WR16(s, 0x2410011, 0x15);
- if (rc < 0)
- goto error;
- rc = WR16(s, 0x2410012, s->config.w92 / 4000);
- if (rc < 0)
- goto error;
-#ifdef ORIG_FW
- rc = WR16(s, 0x2410015, 2);
- if (rc < 0)
- goto error;
-#endif
- rc = WR16(s, 0x2410017, 0x3973);
- if (rc < 0)
- goto error;
-
- s->f_osc = s->config.f_osc * 1000; /* initial estimator */
-
- s->config.w56 = 1;
-
- rc = HI_CfgCommand(s);
- if (rc < 0)
- goto error;
-
- rc = write_fw(s, DRXD_InitAtomicRead);
- if (rc < 0)
- goto error;
-
- if (s->chip_rev == DRXD_FW_A2) {
- rc = WR16(s, 0x2150013, 0);
- if (rc < 0)
- goto error;
- }
-
- rc = WR16_E0(s, 0x0400002, 0);
- if (rc < 0)
- goto error;
- rc = WR16(s, 0x0400002, 0);
- if (rc < 0)
- goto error;
-
- if (s->chip_rev == DRXD_FW_A2) {
- rc = write_fw(s, DRXD_ResetCEFR);
- if (rc < 0)
- goto error;
- }
- rc = write_fw(s, DRXD_microcode);
- if (rc < 0)
- goto error;
-
- s->config.w9C = 0x0e;
- if (s->flags & F_SET_0D0h) {
- s->config.w9C = 0;
- rc = RD16(s, 0x0c20010);
- if (rc < 0)
- goto write_DRXD_InitFE_1;
-
- rc &= ~0x1000;
- rc = WR16(s, 0x0c20010, rc);
- if (rc < 0)
- goto write_DRXD_InitFE_1;
-
- rc = RD16(s, 0x0c20011);
- if (rc < 0)
- goto write_DRXD_InitFE_1;
-
- rc &= ~0x8;
- rc = WR16(s, 0x0c20011, rc);
- if (rc < 0)
- goto write_DRXD_InitFE_1;
-
- rc = WR16(s, 0x0c20012, 1);
- }
-
-write_DRXD_InitFE_1:
-
- rc = write_fw(s, DRXD_InitFE_1);
- if (rc < 0)
- goto error;
-
- rc = 1;
- if (s->chip_rev == DRXD_FW_B1) {
- if (s->flags & F_SET_0D0h)
- rc = 0;
- } else {
- if (s->flags & F_SET_0D0h)
- rc = 4;
- }
-
- rc = WR16(s, 0x0C20012, rc);
- if (rc < 0)
- goto error;
-
- rc = WR16(s, 0x0C20013, s->config.w9E);
- if (rc < 0)
- goto error;
- rc = WR16(s, 0x0C20015, s->config.w9C);
- if (rc < 0)
- goto error;
-
- rc = write_fw(s, DRXD_InitFE_2);
- if (rc < 0)
- goto error;
- rc = write_fw(s, DRXD_InitFT);
- if (rc < 0)
- goto error;
- rc = write_fw(s, DRXD_InitCP);
- if (rc < 0)
- goto error;
- rc = write_fw(s, DRXD_InitCE);
- if (rc < 0)
- goto error;
- rc = write_fw(s, DRXD_InitEQ);
- if (rc < 0)
- goto error;
- rc = write_fw(s, DRXD_InitEC);
- if (rc < 0)
- goto error;
- rc = write_fw(s, DRXD_InitSC);
- if (rc < 0)
- goto error;
-
- rc = SetCfgIfAgc(s, &s->config.ifagc);
- if (rc < 0)
- goto error;
-
- rc = SetCfgRfAgc(s, &s->config.rfagc);
- if (rc < 0)
- goto error;
-
- rc = ConfigureMPEGOutput(s, 1);
- rc = WR16(s, 0x08201fe, 0x0017);
- rc = WR16(s, 0x08201ff, 0x0101);
-
- s->config.d5C = 0;
- s->config.d60 = 1;
- s->config.d48 = 1;
-
-error:
- return rc;
-}
-
-static int drx397x_get_frontend(struct dvb_frontend *fe,
- struct dvb_frontend_parameters *params)
-{
- return 0;
-}
-
-static int drx397x_set_frontend(struct dvb_frontend *fe,
- struct dvb_frontend_parameters *params)
-{
- struct drx397xD_state *s = fe->demodulator_priv;
-
- s->config.s20d24 = 1;
-
- return drx_tune(s, params);
-}
-
-static int drx397x_get_tune_settings(struct dvb_frontend *fe,
- struct dvb_frontend_tune_settings
- *fe_tune_settings)
-{
- fe_tune_settings->min_delay_ms = 10000;
- fe_tune_settings->step_size = 0;
- fe_tune_settings->max_drift = 0;
-
- return 0;
-}
-
-static int drx397x_read_status(struct dvb_frontend *fe, fe_status_t *status)
-{
- struct drx397xD_state *s = fe->demodulator_priv;
- int lockstat;
-
- GetLockStatus(s, &lockstat);
-
- *status = 0;
- if (lockstat & 2) {
- CorrectSysClockDeviation(s);
- ConfigureMPEGOutput(s, 1);
- *status = FE_HAS_LOCK | FE_HAS_SYNC | FE_HAS_VITERBI;
- }
- if (lockstat & 4)
- *status |= FE_HAS_CARRIER | FE_HAS_SIGNAL;
-
- return 0;
-}
-
-static int drx397x_read_ber(struct dvb_frontend *fe, unsigned int *ber)
-{
- *ber = 0;
-
- return 0;
-}
-
-static int drx397x_read_snr(struct dvb_frontend *fe, u16 *snr)
-{
- *snr = 0;
-
- return 0;
-}
-
-static int drx397x_read_signal_strength(struct dvb_frontend *fe, u16 *strength)
-{
- struct drx397xD_state *s = fe->demodulator_priv;
- int rc;
-
- if (s->config.ifagc.d00 == 2) {
- *strength = 0xffff;
- return 0;
- }
- rc = RD16(s, 0x0c20035);
- if (rc < 0) {
- *strength = 0;
- return 0;
- }
- rc &= 0x3ff;
- /* Signal strength is calculated using the following formula:
- *
- * a = 2200 * 150 / (2200 + 150);
- * a = a * 3300 / (a + 820);
- * b = 2200 * 3300 / (2200 + 820);
- * c = (((b-a) * rc) >> 10 + a) << 4;
- * strength = ~c & 0xffff;
- *
- * The following does the same but with less rounding errors:
- */
- *strength = ~(7720 + (rc * 30744 >> 10));
-
- return 0;
-}
-
-static int drx397x_read_ucblocks(struct dvb_frontend *fe,
- unsigned int *ucblocks)
-{
- *ucblocks = 0;
-
- return 0;
-}
-
-static int drx397x_sleep(struct dvb_frontend *fe)
-{
- return 0;
-}
-
-static void drx397x_release(struct dvb_frontend *fe)
-{
- struct drx397xD_state *s = fe->demodulator_priv;
- printk(KERN_INFO "%s: release demodulator\n", mod_name);
- if (s) {
- drx_release_fw(s);
- kfree(s);
- }
-
-}
-
-static struct dvb_frontend_ops drx397x_ops = {
-
- .info = {
- .name = "Micronas DRX397xD DVB-T Frontend",
- .type = FE_OFDM,
- .frequency_min = 47125000,
- .frequency_max = 855250000,
- .frequency_stepsize = 166667,
- .frequency_tolerance = 0,
- .caps = /* 0x0C01B2EAE */
- FE_CAN_FEC_1_2 | /* = 0x2, */
- FE_CAN_FEC_2_3 | /* = 0x4, */
- FE_CAN_FEC_3_4 | /* = 0x8, */
- FE_CAN_FEC_5_6 | /* = 0x20, */
- FE_CAN_FEC_7_8 | /* = 0x80, */
- FE_CAN_FEC_AUTO | /* = 0x200, */
- FE_CAN_QPSK | /* = 0x400, */
- FE_CAN_QAM_16 | /* = 0x800, */
- FE_CAN_QAM_64 | /* = 0x2000, */
- FE_CAN_QAM_AUTO | /* = 0x10000, */
- FE_CAN_TRANSMISSION_MODE_AUTO | /* = 0x20000, */
- FE_CAN_GUARD_INTERVAL_AUTO | /* = 0x80000, */
- FE_CAN_HIERARCHY_AUTO | /* = 0x100000, */
- FE_CAN_RECOVER | /* = 0x40000000, */
- FE_CAN_MUTE_TS /* = 0x80000000 */
- },
-
- .release = drx397x_release,
- .init = drx397x_init,
- .sleep = drx397x_sleep,
-
- .set_frontend = drx397x_set_frontend,
- .get_tune_settings = drx397x_get_tune_settings,
- .get_frontend = drx397x_get_frontend,
-
- .read_status = drx397x_read_status,
- .read_snr = drx397x_read_snr,
- .read_signal_strength = drx397x_read_signal_strength,
- .read_ber = drx397x_read_ber,
- .read_ucblocks = drx397x_read_ucblocks,
-};
-
-struct dvb_frontend *drx397xD_attach(const struct drx397xD_config *config,
- struct i2c_adapter *i2c)
-{
- struct drx397xD_state *state;
-
- /* allocate memory for the internal state */
- state = kzalloc(sizeof(struct drx397xD_state), GFP_KERNEL);
- if (!state)
- goto error;
-
- /* setup the state */
- state->i2c = i2c;
- memcpy(&state->config, config, sizeof(struct drx397xD_config));
-
- /* check if the demod is there */
- if (RD16(state, 0x2410019) < 0)
- goto error;
-
- /* create dvb_frontend */
- memcpy(&state->frontend.ops, &drx397x_ops,
- sizeof(struct dvb_frontend_ops));
- state->frontend.demodulator_priv = state;
-
- return &state->frontend;
-error:
- kfree(state);
-
- return NULL;
-}
-EXPORT_SYMBOL(drx397xD_attach);
-
-MODULE_DESCRIPTION("Micronas DRX397xD DVB-T Frontend");
-MODULE_AUTHOR("Henk Vergonet");
-MODULE_LICENSE("GPL");
-
diff --git a/drivers/media/dvb/frontends/drx397xD.h b/drivers/media/dvb/frontends/drx397xD.h
deleted file mode 100644
index ba05d17..0000000
--- a/drivers/media/dvb/frontends/drx397xD.h
+++ /dev/null
@@ -1,130 +0,0 @@
-/*
- * Driver for Micronas DVB-T drx397xD demodulator
- *
- * Copyright (C) 2007 Henk vergonet <Henk.Vergonet@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- *
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.=
- */
-
-#ifndef _DRX397XD_H_INCLUDED
-#define _DRX397XD_H_INCLUDED
-
-#include <linux/dvb/frontend.h>
-
-#define DRX_F_STEPSIZE 166667
-#define DRX_F_OFFSET 36000000
-
-#define I2C_ADR_C0(x) \
-( cpu_to_le32( \
- (u32)( \
- (((u32)(x) & (u32)0x000000ffUL) ) | \
- (((u32)(x) & (u32)0x0000ff00UL) << 16) | \
- (((u32)(x) & (u32)0x0fff0000UL) >> 8) | \
- ( (u32)0x00c00000UL) \
- )) \
-)
-
-#define I2C_ADR_E0(x) \
-( cpu_to_le32( \
- (u32)( \
- (((u32)(x) & (u32)0x000000ffUL) ) | \
- (((u32)(x) & (u32)0x0000ff00UL) << 16) | \
- (((u32)(x) & (u32)0x0fff0000UL) >> 8) | \
- ( (u32)0x00e00000UL) \
- )) \
-)
-
-struct drx397xD_CfgRfAgc /* 0x7c */
-{
- int d00; /* 2 */
- u16 w04;
- u16 w06;
-};
-
-struct drx397xD_CfgIfAgc /* 0x68 */
-{
- int d00; /* 0 */
- u16 w04; /* 0 */
- u16 w06;
- u16 w08;
- u16 w0A;
- u16 w0C;
-};
-
-struct drx397xD_s20 {
- int d04;
- u32 d18;
- u32 d1C;
- u32 d20;
- u32 d14;
- u32 d24;
- u32 d0C;
- u32 d08;
-};
-
-struct drx397xD_config
-{
- /* demodulator's I2C address */
- u8 demod_address; /* 0x0f */
-
- struct drx397xD_CfgIfAgc ifagc; /* 0x68 */
- struct drx397xD_CfgRfAgc rfagc; /* 0x7c */
- u32 s20d24;
-
- /* HI_CfgCommand parameters */
- u16 w50, w52, /* w54, */ w56;
-
- int d5C;
- int d60;
- int d48;
- int d28;
-
- u32 f_if; /* d14: intermediate frequency [Hz] */
- /* 36000000 on Cinergy 2400i DT */
- /* 42800000 on Pinnacle Hybrid PRO 330e */
-
- u16 f_osc; /* s66: 48000 oscillator frequency [kHz] */
-
- u16 w92; /* 20000 */
-
- u16 wA0;
- u16 w98;
- u16 w9A;
-
- u16 w9C; /* 0xe0 */
- u16 w9E; /* 0x00 */
-
- /* used for signal strength calculations in
- drx397x_read_signal_strength
- */
- u16 ss78; // 2200
- u16 ss7A; // 150
- u16 ss76; // 820
-};
-
-#if defined(CONFIG_DVB_DRX397XD) || (defined(CONFIG_DVB_DRX397XD_MODULE) && defined(MODULE))
-extern struct dvb_frontend* drx397xD_attach(const struct drx397xD_config *config,
- struct i2c_adapter *i2c);
-#else
-static inline struct dvb_frontend* drx397xD_attach(const struct drx397xD_config *config,
- struct i2c_adapter *i2c)
-{
- printk(KERN_WARNING "%s: driver disabled by Kconfig\n", __func__);
- return NULL;
-}
-#endif /* CONFIG_DVB_DRX397XD */
-
-#endif /* _DRX397XD_H_INCLUDED */
diff --git a/drivers/media/dvb/frontends/drx397xD_fw.h b/drivers/media/dvb/frontends/drx397xD_fw.h
deleted file mode 100644
index c8b44c1..0000000
--- a/drivers/media/dvb/frontends/drx397xD_fw.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Firmware definitions for Micronas drx397xD
- *
- * Copyright (C) 2007 Henk Vergonet <Henk.Vergonet@gmail.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifdef _FW_ENTRY
- _FW_ENTRY("drx397xD.A2.fw", DRXD_FW_A2 = 0, DRXD_FW_A2 ),
- _FW_ENTRY("drx397xD.B1.fw", DRXD_FW_B1, DRXD_FW_B1 ),
-#undef _FW_ENTRY
-#endif /* _FW_ENTRY */
-
-#ifdef _BLOB_ENTRY
- _BLOB_ENTRY("InitAtomicRead", DRXD_InitAtomicRead = 0 ),
- _BLOB_ENTRY("InitCE", DRXD_InitCE ),
- _BLOB_ENTRY("InitCP", DRXD_InitCP ),
- _BLOB_ENTRY("InitEC", DRXD_InitEC ),
- _BLOB_ENTRY("InitEQ", DRXD_InitEQ ),
- _BLOB_ENTRY("InitFE_1", DRXD_InitFE_1 ),
- _BLOB_ENTRY("InitFE_2", DRXD_InitFE_2 ),
- _BLOB_ENTRY("InitFT", DRXD_InitFT ),
- _BLOB_ENTRY("InitSC", DRXD_InitSC ),
- _BLOB_ENTRY("ResetCEFR", DRXD_ResetCEFR ),
- _BLOB_ENTRY("ResetECRAM", DRXD_ResetECRAM ),
- _BLOB_ENTRY("microcode", DRXD_microcode ),
-#undef _BLOB_ENTRY
-#endif /* _BLOB_ENTRY */
diff --git a/drivers/media/dvb/frontends/drxd.h b/drivers/media/dvb/frontends/drxd.h
new file mode 100644
index 0000000..7113535
--- /dev/null
+++ b/drivers/media/dvb/frontends/drxd.h
@@ -0,0 +1,61 @@
+/*
+ * drxd.h: DRXD DVB-T demodulator driver
+ *
+ * Copyright (C) 2005-2007 Micronas
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 only, as published by the Free Software Foundation.
+ *
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA
+ * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef _DRXD_H_
+#define _DRXD_H_
+
+#include <linux/types.h>
+#include <linux/i2c.h>
+
+struct drxd_config {
+ u8 index;
+
+ u8 pll_address;
+ u8 pll_type;
+#define DRXD_PLL_NONE 0
+#define DRXD_PLL_DTT7520X 1
+#define DRXD_PLL_MT3X0823 2
+
+ u32 clock;
+ u8 insert_rs_byte;
+
+ u8 demod_address;
+ u8 demoda_address;
+ u8 demod_revision;
+
+ /* If the tuner is not behind an i2c gate, be sure to flip this bit
+ or else the i2c bus could get wedged */
+ u8 disable_i2c_gate_ctrl;
+
+ u32 IF;
+ int (*pll_set) (void *priv, void *priv_params,
+ u8 pll_addr, u8 demoda_addr, s32 *off);
+ s16(*osc_deviation) (void *priv, s16 dev, int flag);
+};
+
+extern
+struct dvb_frontend *drxd_attach(const struct drxd_config *config,
+ void *priv, struct i2c_adapter *i2c,
+ struct device *dev);
+extern int drxd_config_i2c(struct dvb_frontend *, int);
+#endif
diff --git a/drivers/media/dvb/frontends/drxd_firm.c b/drivers/media/dvb/frontends/drxd_firm.c
new file mode 100644
index 0000000..5418b0b
--- /dev/null
+++ b/drivers/media/dvb/frontends/drxd_firm.c
@@ -0,0 +1,929 @@
+/*
+ * drxd_firm.c : DRXD firmware tables
+ *
+ * Copyright (C) 2006-2007 Micronas
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 only, as published by the Free Software Foundation.
+ *
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA
+ * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
+ */
+
+/* TODO: generate this file with a script from a settings file */
+
+/* Contains A2 firmware version: 1.4.2
+ * Contains B1 firmware version: 3.3.33
+ * Contains settings from driver 1.4.23
+*/
+
+#include "drxd_firm.h"
+
+#define ADDRESS(x) ((x) & 0xFF), (((x)>>8) & 0xFF), (((x)>>16) & 0xFF), (((x)>>24) & 0xFF)
+#define LENGTH(x) ((x) & 0xFF), (((x)>>8) & 0xFF)
+
+/* Is written via block write, must be little endian */
+#define DATA16(x) ((x) & 0xFF), (((x)>>8) & 0xFF)
+
+#define WRBLOCK(a, l) ADDRESS(a), LENGTH(l)
+#define WR16(a, d) ADDRESS(a), LENGTH(1), DATA16(d)
+
+#define END_OF_TABLE 0xFF, 0xFF, 0xFF, 0xFF
+
+/* HI firmware patches */
+
+#define HI_TR_FUNC_ADDR HI_IF_RAM_USR_BEGIN__A
+#define HI_TR_FUNC_SIZE 9 /* size of this function in instruction words */
+
+u8 DRXD_InitAtomicRead[] = {
+ WRBLOCK(HI_TR_FUNC_ADDR, HI_TR_FUNC_SIZE),
+ 0x26, 0x00, /* 0 -> ring.rdy; */
+ 0x60, 0x04, /* r0rami.dt -> ring.xba; */
+ 0x61, 0x04, /* r0rami.dt -> ring.xad; */
+ 0xE3, 0x07, /* HI_RA_RAM_USR_BEGIN -> ring.iad; */
+ 0x40, 0x00, /* (long immediate) */
+ 0x64, 0x04, /* r0rami.dt -> ring.len; */
+ 0x65, 0x04, /* r0rami.dt -> ring.ctl; */
+ 0x26, 0x00, /* 0 -> ring.rdy; */
+ 0x38, 0x00, /* 0 -> jumps.ad; */
+ END_OF_TABLE
+};
+
+/* Pins D0 and D1 of the parallel MPEG output can be used
+ to set the I2C address of a device. */
+
+#define HI_RST_FUNC_ADDR (HI_IF_RAM_USR_BEGIN__A + HI_TR_FUNC_SIZE)
+#define HI_RST_FUNC_SIZE 54 /* size of this function in instruction words */
+
+/* D0 Version */
+u8 DRXD_HiI2cPatch_1[] = {
+ WRBLOCK(HI_RST_FUNC_ADDR, HI_RST_FUNC_SIZE),
+ 0xC8, 0x07, 0x01, 0x00, /* MASK -> reg0.dt; */
+ 0xE0, 0x07, 0x15, 0x02, /* (EC__BLK << 6) + EC_OC_REG__BNK -> ring.xba; */
+ 0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */
+ 0xA2, 0x00, /* M_BNK_ID_DAT -> ring.iba; */
+ 0x23, 0x00, /* &data -> ring.iad; */
+ 0x24, 0x00, /* 0 -> ring.len; */
+ 0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */
+ 0x26, 0x00, /* 0 -> ring.rdy; */
+ 0x42, 0x00, /* &data+1 -> w0ram.ad; */
+ 0xC0, 0x07, 0xFF, 0x0F, /* -1 -> w0ram.dt; */
+ 0x63, 0x00, /* &data+1 -> ring.iad; */
+ 0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */
+ 0x26, 0x00, /* 0 -> ring.rdy; */
+ 0xE1, 0x07, 0x38, 0x00, /* EC_OC_REG_OCR_MPG_USR_DAT__A -> ring.xad; */
+ 0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */
+ 0x26, 0x00, /* 0 -> ring.rdy; */
+ 0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */
+ 0x23, 0x00, /* &data -> ring.iad; */
+ 0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */
+ 0x26, 0x00, /* 0 -> ring.rdy; */
+ 0x42, 0x00, /* &data+1 -> w0ram.ad; */
+ 0x0F, 0x04, /* r0ram.dt -> and.op; */
+ 0x1C, 0x06, /* reg0.dt -> and.tr; */
+ 0xCF, 0x04, /* and.rs -> add.op; */
+ 0xD0, 0x07, 0x70, 0x00, /* DEF_DEV_ID -> add.tr; */
+ 0xD0, 0x04, /* add.rs -> add.tr; */
+ 0xC8, 0x04, /* add.rs -> reg0.dt; */
+ 0x60, 0x00, /* reg0.dt -> w0ram.dt; */
+ 0xC2, 0x07, 0x10, 0x00, /* SLV0_BASE -> w0rami.ad; */
+ 0x01, 0x00, /* 0 -> w0rami.dt; */
+ 0x01, 0x06, /* reg0.dt -> w0rami.dt; */
+ 0xC2, 0x07, 0x20, 0x00, /* SLV1_BASE -> w0rami.ad; */
+ 0x01, 0x00, /* 0 -> w0rami.dt; */
+ 0x01, 0x06, /* reg0.dt -> w0rami.dt; */
+ 0xC2, 0x07, 0x30, 0x00, /* CMD_BASE -> w0rami.ad; */
+ 0x01, 0x00, /* 0 -> w0rami.dt; */
+ 0x01, 0x00, /* 0 -> w0rami.dt; */
+ 0x01, 0x00, /* 0 -> w0rami.dt; */
+ 0x68, 0x00, /* M_IC_SEL_PT1 -> i2c.sel; */
+ 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */
+ 0x28, 0x00, /* M_IC_SEL_PT0 -> i2c.sel; */
+ 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */
+ 0xF8, 0x07, 0x2F, 0x00, /* 0x2F -> jumps.ad; */
+
+ WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 0) + 1)),
+ (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
+ WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 1) + 1)),
+ (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
+ WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 2) + 1)),
+ (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
+ WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 3) + 1)),
+ (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
+
+ /* Force quick and dirty reset */
+ WR16(B_HI_CT_REG_COMM_STATE__A, 0),
+ END_OF_TABLE
+};
+
+/* D0,D1 Version */
+u8 DRXD_HiI2cPatch_3[] = {
+ WRBLOCK(HI_RST_FUNC_ADDR, HI_RST_FUNC_SIZE),
+ 0xC8, 0x07, 0x03, 0x00, /* MASK -> reg0.dt; */
+ 0xE0, 0x07, 0x15, 0x02, /* (EC__BLK << 6) + EC_OC_REG__BNK -> ring.xba; */
+ 0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */
+ 0xA2, 0x00, /* M_BNK_ID_DAT -> ring.iba; */
+ 0x23, 0x00, /* &data -> ring.iad; */
+ 0x24, 0x00, /* 0 -> ring.len; */
+ 0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */
+ 0x26, 0x00, /* 0 -> ring.rdy; */
+ 0x42, 0x00, /* &data+1 -> w0ram.ad; */
+ 0xC0, 0x07, 0xFF, 0x0F, /* -1 -> w0ram.dt; */
+ 0x63, 0x00, /* &data+1 -> ring.iad; */
+ 0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */
+ 0x26, 0x00, /* 0 -> ring.rdy; */
+ 0xE1, 0x07, 0x38, 0x00, /* EC_OC_REG_OCR_MPG_USR_DAT__A -> ring.xad; */
+ 0xA5, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_READ -> ring.ctl; */
+ 0x26, 0x00, /* 0 -> ring.rdy; */
+ 0xE1, 0x07, 0x12, 0x00, /* EC_OC_REG_OC_MPG_SIO__A -> ring.xad; */
+ 0x23, 0x00, /* &data -> ring.iad; */
+ 0x65, 0x02, /* M_RC_CTR_SWAP | M_RC_CTR_WRITE -> ring.ctl; */
+ 0x26, 0x00, /* 0 -> ring.rdy; */
+ 0x42, 0x00, /* &data+1 -> w0ram.ad; */
+ 0x0F, 0x04, /* r0ram.dt -> and.op; */
+ 0x1C, 0x06, /* reg0.dt -> and.tr; */
+ 0xCF, 0x04, /* and.rs -> add.op; */
+ 0xD0, 0x07, 0x70, 0x00, /* DEF_DEV_ID -> add.tr; */
+ 0xD0, 0x04, /* add.rs -> add.tr; */
+ 0xC8, 0x04, /* add.rs -> reg0.dt; */
+ 0x60, 0x00, /* reg0.dt -> w0ram.dt; */
+ 0xC2, 0x07, 0x10, 0x00, /* SLV0_BASE -> w0rami.ad; */
+ 0x01, 0x00, /* 0 -> w0rami.dt; */
+ 0x01, 0x06, /* reg0.dt -> w0rami.dt; */
+ 0xC2, 0x07, 0x20, 0x00, /* SLV1_BASE -> w0rami.ad; */
+ 0x01, 0x00, /* 0 -> w0rami.dt; */
+ 0x01, 0x06, /* reg0.dt -> w0rami.dt; */
+ 0xC2, 0x07, 0x30, 0x00, /* CMD_BASE -> w0rami.ad; */
+ 0x01, 0x00, /* 0 -> w0rami.dt; */
+ 0x01, 0x00, /* 0 -> w0rami.dt; */
+ 0x01, 0x00, /* 0 -> w0rami.dt; */
+ 0x68, 0x00, /* M_IC_SEL_PT1 -> i2c.sel; */
+ 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */
+ 0x28, 0x00, /* M_IC_SEL_PT0 -> i2c.sel; */
+ 0x29, 0x00, /* M_IC_CMD_RESET -> i2c.cmd; */
+ 0xF8, 0x07, 0x2F, 0x00, /* 0x2F -> jumps.ad; */
+
+ WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 0) + 1)),
+ (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
+ WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 1) + 1)),
+ (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
+ WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 2) + 1)),
+ (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
+ WR16((B_HI_IF_RAM_TRP_BPT0__AX + ((2 * 3) + 1)),
+ (u16) (HI_RST_FUNC_ADDR & 0x3FF)),
+
+ /* Force quick and dirty reset */
+ WR16(B_HI_CT_REG_COMM_STATE__A, 0),
+ END_OF_TABLE
+};
+
+u8 DRXD_ResetCEFR[] = {
+ WRBLOCK(CE_REG_FR_TREAL00__A, 57),
+ 0x52, 0x00, /* CE_REG_FR_TREAL00__A */
+ 0x00, 0x00, /* CE_REG_FR_TIMAG00__A */
+ 0x52, 0x00, /* CE_REG_FR_TREAL01__A */
+ 0x00, 0x00, /* CE_REG_FR_TIMAG01__A */
+ 0x52, 0x00, /* CE_REG_FR_TREAL02__A */
+ 0x00, 0x00, /* CE_REG_FR_TIMAG02__A */
+ 0x52, 0x00, /* CE_REG_FR_TREAL03__A */
+ 0x00, 0x00, /* CE_REG_FR_TIMAG03__A */
+ 0x52, 0x00, /* CE_REG_FR_TREAL04__A */
+ 0x00, 0x00, /* CE_REG_FR_TIMAG04__A */
+ 0x52, 0x00, /* CE_REG_FR_TREAL05__A */
+ 0x00, 0x00, /* CE_REG_FR_TIMAG05__A */
+ 0x52, 0x00, /* CE_REG_FR_TREAL06__A */
+ 0x00, 0x00, /* CE_REG_FR_TIMAG06__A */
+ 0x52, 0x00, /* CE_REG_FR_TREAL07__A */
+ 0x00, 0x00, /* CE_REG_FR_TIMAG07__A */
+ 0x52, 0x00, /* CE_REG_FR_TREAL08__A */
+ 0x00, 0x00, /* CE_REG_FR_TIMAG08__A */
+ 0x52, 0x00, /* CE_REG_FR_TREAL09__A */
+ 0x00, 0x00, /* CE_REG_FR_TIMAG09__A */
+ 0x52, 0x00, /* CE_REG_FR_TREAL10__A */
+ 0x00, 0x00, /* CE_REG_FR_TIMAG10__A */
+ 0x52, 0x00, /* CE_REG_FR_TREAL11__A */
+ 0x00, 0x00, /* CE_REG_FR_TIMAG11__A */
+
+ 0x52, 0x00, /* CE_REG_FR_MID_TAP__A */
+
+ 0x0B, 0x00, /* CE_REG_FR_SQS_G00__A */
+ 0x0B, 0x00, /* CE_REG_FR_SQS_G01__A */
+ 0x0B, 0x00, /* CE_REG_FR_SQS_G02__A */
+ 0x0B, 0x00, /* CE_REG_FR_SQS_G03__A */
+ 0x0B, 0x00, /* CE_REG_FR_SQS_G04__A */
+ 0x0B, 0x00, /* CE_REG_FR_SQS_G05__A */
+ 0x0B, 0x00, /* CE_REG_FR_SQS_G06__A */
+ 0x0B, 0x00, /* CE_REG_FR_SQS_G07__A */
+ 0x0B, 0x00, /* CE_REG_FR_SQS_G08__A */
+ 0x0B, 0x00, /* CE_REG_FR_SQS_G09__A */
+ 0x0B, 0x00, /* CE_REG_FR_SQS_G10__A */
+ 0x0B, 0x00, /* CE_REG_FR_SQS_G11__A */
+ 0x0B, 0x00, /* CE_REG_FR_SQS_G12__A */
+
+ 0xFF, 0x01, /* CE_REG_FR_RIO_G00__A */
+ 0x90, 0x01, /* CE_REG_FR_RIO_G01__A */
+ 0x0B, 0x01, /* CE_REG_FR_RIO_G02__A */
+ 0xC8, 0x00, /* CE_REG_FR_RIO_G03__A */
+ 0xA0, 0x00, /* CE_REG_FR_RIO_G04__A */
+ 0x85, 0x00, /* CE_REG_FR_RIO_G05__A */
+ 0x72, 0x00, /* CE_REG_FR_RIO_G06__A */
+ 0x64, 0x00, /* CE_REG_FR_RIO_G07__A */
+ 0x59, 0x00, /* CE_REG_FR_RIO_G08__A */
+ 0x50, 0x00, /* CE_REG_FR_RIO_G09__A */
+ 0x49, 0x00, /* CE_REG_FR_RIO_G10__A */
+
+ 0x10, 0x00, /* CE_REG_FR_MODE__A */
+ 0x78, 0x00, /* CE_REG_FR_SQS_TRH__A */
+ 0x00, 0x00, /* CE_REG_FR_RIO_GAIN__A */
+ 0x00, 0x02, /* CE_REG_FR_BYPASS__A */
+ 0x0D, 0x00, /* CE_REG_FR_PM_SET__A */
+ 0x07, 0x00, /* CE_REG_FR_ERR_SH__A */
+ 0x04, 0x00, /* CE_REG_FR_MAN_SH__A */
+ 0x06, 0x00, /* CE_REG_FR_TAP_SH__A */
+
+ END_OF_TABLE
+};
+
+u8 DRXD_InitFEA2_1[] = {
+ WRBLOCK(FE_AD_REG_PD__A, 3),
+ 0x00, 0x00, /* FE_AD_REG_PD__A */
+ 0x01, 0x00, /* FE_AD_REG_INVEXT__A */
+ 0x00, 0x00, /* FE_AD_REG_CLKNEG__A */
+
+ WRBLOCK(FE_AG_REG_DCE_AUR_CNT__A, 2),
+ 0x10, 0x00, /* FE_AG_REG_DCE_AUR_CNT__A */
+ 0x10, 0x00, /* FE_AG_REG_DCE_RUR_CNT__A */
+
+ WRBLOCK(FE_AG_REG_ACE_AUR_CNT__A, 2),
+ 0x0E, 0x00, /* FE_AG_REG_ACE_AUR_CNT__A */
+ 0x00, 0x00, /* FE_AG_REG_ACE_RUR_CNT__A */
+
+ WRBLOCK(FE_AG_REG_EGC_FLA_RGN__A, 5),
+ 0x04, 0x00, /* FE_AG_REG_EGC_FLA_RGN__A */
+ 0x1F, 0x00, /* FE_AG_REG_EGC_SLO_RGN__A */
+ 0x00, 0x00, /* FE_AG_REG_EGC_JMP_PSN__A */
+ 0x00, 0x00, /* FE_AG_REG_EGC_FLA_INC__A */
+ 0x00, 0x00, /* FE_AG_REG_EGC_FLA_DEC__A */
+
+ WRBLOCK(FE_AG_REG_GC1_AGC_MAX__A, 2),
+ 0xFF, 0x01, /* FE_AG_REG_GC1_AGC_MAX__A */
+ 0x00, 0xFE, /* FE_AG_REG_GC1_AGC_MIN__A */
+
+ WRBLOCK(FE_AG_REG_IND_WIN__A, 29),
+ 0x00, 0x00, /* FE_AG_REG_IND_WIN__A */
+ 0x05, 0x00, /* FE_AG_REG_IND_THD_LOL__A */
+ 0x0F, 0x00, /* FE_AG_REG_IND_THD_HIL__A */
+ 0x00, 0x00, /* FE_AG_REG_IND_DEL__A don't care */
+ 0x1E, 0x00, /* FE_AG_REG_IND_PD1_WRI__A */
+ 0x0C, 0x00, /* FE_AG_REG_PDA_AUR_CNT__A */
+ 0x00, 0x00, /* FE_AG_REG_PDA_RUR_CNT__A */
+ 0x00, 0x00, /* FE_AG_REG_PDA_AVE_DAT__A don't care */
+ 0x00, 0x00, /* FE_AG_REG_PDC_RUR_CNT__A */
+ 0x01, 0x00, /* FE_AG_REG_PDC_SET_LVL__A */
+ 0x02, 0x00, /* FE_AG_REG_PDC_FLA_RGN__A */
+ 0x00, 0x00, /* FE_AG_REG_PDC_JMP_PSN__A don't care */
+ 0xFF, 0xFF, /* FE_AG_REG_PDC_FLA_STP__A */
+ 0xFF, 0xFF, /* FE_AG_REG_PDC_SLO_STP__A */
+ 0x00, 0x1F, /* FE_AG_REG_PDC_PD2_WRI__A don't care */
+ 0x00, 0x00, /* FE_AG_REG_PDC_MAP_DAT__A don't care */
+ 0x02, 0x00, /* FE_AG_REG_PDC_MAX__A */
+ 0x0C, 0x00, /* FE_AG_REG_TGA_AUR_CNT__A */
+ 0x00, 0x00, /* FE_AG_REG_TGA_RUR_CNT__A */
+ 0x00, 0x00, /* FE_AG_REG_TGA_AVE_DAT__A don't care */
+ 0x00, 0x00, /* FE_AG_REG_TGC_RUR_CNT__A */
+ 0x22, 0x00, /* FE_AG_REG_TGC_SET_LVL__A */
+ 0x15, 0x00, /* FE_AG_REG_TGC_FLA_RGN__A */
+ 0x00, 0x00, /* FE_AG_REG_TGC_JMP_PSN__A don't care */
+ 0x01, 0x00, /* FE_AG_REG_TGC_FLA_STP__A */
+ 0x0A, 0x00, /* FE_AG_REG_TGC_SLO_STP__A */
+ 0x00, 0x00, /* FE_AG_REG_TGC_MAP_DAT__A don't care */
+ 0x10, 0x00, /* FE_AG_REG_FGA_AUR_CNT__A */
+ 0x10, 0x00, /* FE_AG_REG_FGA_RUR_CNT__A */
+
+ WRBLOCK(FE_AG_REG_BGC_FGC_WRI__A, 2),
+ 0x00, 0x00, /* FE_AG_REG_BGC_FGC_WRI__A */
+ 0x00, 0x00, /* FE_AG_REG_BGC_CGC_WRI__A */
+
+ WRBLOCK(FE_FD_REG_SCL__A, 3),
+ 0x05, 0x00, /* FE_FD_REG_SCL__A */
+ 0x03, 0x00, /* FE_FD_REG_MAX_LEV__A */
+ 0x05, 0x00, /* FE_FD_REG_NR__A */
+
+ WRBLOCK(FE_CF_REG_SCL__A, 5),
+ 0x16, 0x00, /* FE_CF_REG_SCL__A */
+ 0x04, 0x00, /* FE_CF_REG_MAX_LEV__A */
+ 0x06, 0x00, /* FE_CF_REG_NR__A */
+ 0x00, 0x00, /* FE_CF_REG_IMP_VAL__A */
+ 0x01, 0x00, /* FE_CF_REG_MEAS_VAL__A */
+
+ WRBLOCK(FE_CU_REG_FRM_CNT_RST__A, 2),
+ 0x00, 0x08, /* FE_CU_REG_FRM_CNT_RST__A */
+ 0x00, 0x00, /* FE_CU_REG_FRM_CNT_STR__A */
+
+ END_OF_TABLE
+};
+
+ /* with PGA */
+/* WR16COND( DRXD_WITH_PGA, FE_AG_REG_AG_PGA_MODE__A , 0x0004), */
+ /* without PGA */
+/* WR16COND( DRXD_WITHOUT_PGA, FE_AG_REG_AG_PGA_MODE__A , 0x0001), */
+/* WR16(FE_AG_REG_AG_AGC_SIO__A, (extAttr -> FeAgRegAgAgcSio), 0x0000 );*/
+/* WR16(FE_AG_REG_AG_PWD__A ,(extAttr -> FeAgRegAgPwd), 0x0000 );*/
+
+u8 DRXD_InitFEA2_2[] = {
+ WR16(FE_AG_REG_CDR_RUR_CNT__A, 0x0010),
+ WR16(FE_AG_REG_FGM_WRI__A, 48),
+ /* Activate measurement, activate scale */
+ WR16(FE_FD_REG_MEAS_VAL__A, 0x0001),
+
+ WR16(FE_CU_REG_COMM_EXEC__A, 0x0001),
+ WR16(FE_CF_REG_COMM_EXEC__A, 0x0001),
+ WR16(FE_IF_REG_COMM_EXEC__A, 0x0001),
+ WR16(FE_FD_REG_COMM_EXEC__A, 0x0001),
+ WR16(FE_FS_REG_COMM_EXEC__A, 0x0001),
+ WR16(FE_AD_REG_COMM_EXEC__A, 0x0001),
+ WR16(FE_AG_REG_COMM_EXEC__A, 0x0001),
+ WR16(FE_AG_REG_AG_MODE_LOP__A, 0x895E),
+
+ END_OF_TABLE
+};
+
+u8 DRXD_InitFEB1_1[] = {
+ WR16(B_FE_AD_REG_PD__A, 0x0000),
+ WR16(B_FE_AD_REG_CLKNEG__A, 0x0000),
+ WR16(B_FE_AG_REG_BGC_FGC_WRI__A, 0x0000),
+ WR16(B_FE_AG_REG_BGC_CGC_WRI__A, 0x0000),
+ WR16(B_FE_AG_REG_AG_MODE_LOP__A, 0x000a),
+ WR16(B_FE_AG_REG_IND_PD1_WRI__A, 35),
+ WR16(B_FE_AG_REG_IND_WIN__A, 0),
+ WR16(B_FE_AG_REG_IND_THD_LOL__A, 8),
+ WR16(B_FE_AG_REG_IND_THD_HIL__A, 8),
+ WR16(B_FE_CF_REG_IMP_VAL__A, 1),
+ WR16(B_FE_AG_REG_EGC_FLA_RGN__A, 7),
+ END_OF_TABLE
+};
+
+ /* with PGA */
+/* WR16(B_FE_AG_REG_AG_PGA_MODE__A , 0x0000, 0x0000); */
+ /* without PGA */
+/* WR16(B_FE_AG_REG_AG_PGA_MODE__A ,
+ B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0x0000);*/
+ /* WR16(B_FE_AG_REG_AG_AGC_SIO__A,(extAttr -> FeAgRegAgAgcSio), 0x0000 );*//*added HS 23-05-2005 */
+/* WR16(B_FE_AG_REG_AG_PWD__A ,(extAttr -> FeAgRegAgPwd), 0x0000 );*/
+
+u8 DRXD_InitFEB1_2[] = {
+ WR16(B_FE_COMM_EXEC__A, 0x0001),
+
+ /* RF-AGC setup */
+ WR16(B_FE_AG_REG_PDA_AUR_CNT__A, 0x0C),
+ WR16(B_FE_AG_REG_PDC_SET_LVL__A, 0x01),
+ WR16(B_FE_AG_REG_PDC_FLA_RGN__A, 0x02),
+ WR16(B_FE_AG_REG_PDC_FLA_STP__A, 0xFFFF),
+ WR16(B_FE_AG_REG_PDC_SLO_STP__A, 0xFFFF),
+ WR16(B_FE_AG_REG_PDC_MAX__A, 0x02),
+ WR16(B_FE_AG_REG_TGA_AUR_CNT__A, 0x0C),
+ WR16(B_FE_AG_REG_TGC_SET_LVL__A, 0x22),
+ WR16(B_FE_AG_REG_TGC_FLA_RGN__A, 0x15),
+ WR16(B_FE_AG_REG_TGC_FLA_STP__A, 0x01),
+ WR16(B_FE_AG_REG_TGC_SLO_STP__A, 0x0A),
+
+ WR16(B_FE_CU_REG_DIV_NFC_CLP__A, 0),
+ WR16(B_FE_CU_REG_CTR_NFC_OCR__A, 25000),
+ WR16(B_FE_CU_REG_CTR_NFC_ICR__A, 1),
+ END_OF_TABLE
+};
+
+u8 DRXD_InitCPA2[] = {
+ WRBLOCK(CP_REG_BR_SPL_OFFSET__A, 2),
+ 0x07, 0x00, /* CP_REG_BR_SPL_OFFSET__A */
+ 0x0A, 0x00, /* CP_REG_BR_STR_DEL__A */
+
+ WRBLOCK(CP_REG_RT_ANG_INC0__A, 4),
+ 0x00, 0x00, /* CP_REG_RT_ANG_INC0__A */
+ 0x00, 0x00, /* CP_REG_RT_ANG_INC1__A */
+ 0x03, 0x00, /* CP_REG_RT_DETECT_ENA__A */
+ 0x03, 0x00, /* CP_REG_RT_DETECT_TRH__A */
+
+ WRBLOCK(CP_REG_AC_NEXP_OFFS__A, 5),
+ 0x32, 0x00, /* CP_REG_AC_NEXP_OFFS__A */
+ 0x62, 0x00, /* CP_REG_AC_AVER_POW__A */
+ 0x82, 0x00, /* CP_REG_AC_MAX_POW__A */
+ 0x26, 0x00, /* CP_REG_AC_WEIGHT_MAN__A */
+ 0x0F, 0x00, /* CP_REG_AC_WEIGHT_EXP__A */
+
+ WRBLOCK(CP_REG_AC_AMP_MODE__A, 2),
+ 0x02, 0x00, /* CP_REG_AC_AMP_MODE__A */
+ 0x01, 0x00, /* CP_REG_AC_AMP_FIX__A */
+
+ WR16(CP_REG_INTERVAL__A, 0x0005),
+ WR16(CP_REG_RT_EXP_MARG__A, 0x0004),
+ WR16(CP_REG_AC_ANG_MODE__A, 0x0003),
+
+ WR16(CP_REG_COMM_EXEC__A, 0x0001),
+ END_OF_TABLE
+};
+
+u8 DRXD_InitCPB1[] = {
+ WR16(B_CP_REG_BR_SPL_OFFSET__A, 0x0008),
+ WR16(B_CP_COMM_EXEC__A, 0x0001),
+ END_OF_TABLE
+};
+
+u8 DRXD_InitCEA2[] = {
+ WRBLOCK(CE_REG_AVG_POW__A, 4),
+ 0x62, 0x00, /* CE_REG_AVG_POW__A */
+ 0x78, 0x00, /* CE_REG_MAX_POW__A */
+ 0x62, 0x00, /* CE_REG_ATT__A */
+ 0x17, 0x00, /* CE_REG_NRED__A */
+
+ WRBLOCK(CE_REG_NE_ERR_SELECT__A, 2),
+ 0x07, 0x00, /* CE_REG_NE_ERR_SELECT__A */
+ 0xEB, 0xFF, /* CE_REG_NE_TD_CAL__A */
+
+ WRBLOCK(CE_REG_NE_MIXAVG__A, 2),
+ 0x06, 0x00, /* CE_REG_NE_MIXAVG__A */
+ 0x00, 0x00, /* CE_REG_NE_NUPD_OFS__A */
+
+ WRBLOCK(CE_REG_PE_NEXP_OFFS__A, 2),
+ 0x00, 0x00, /* CE_REG_PE_NEXP_OFFS__A */
+ 0x00, 0x00, /* CE_REG_PE_TIMESHIFT__A */
+
+ WRBLOCK(CE_REG_TP_A0_TAP_NEW__A, 3),
+ 0x00, 0x01, /* CE_REG_TP_A0_TAP_NEW__A */
+ 0x01, 0x00, /* CE_REG_TP_A0_TAP_NEW_VALID__A */
+ 0x0E, 0x00, /* CE_REG_TP_A0_MU_LMS_STEP__A */
+
+ WRBLOCK(CE_REG_TP_A1_TAP_NEW__A, 3),
+ 0x00, 0x00, /* CE_REG_TP_A1_TAP_NEW__A */
+ 0x01, 0x00, /* CE_REG_TP_A1_TAP_NEW_VALID__A */
+ 0x0A, 0x00, /* CE_REG_TP_A1_MU_LMS_STEP__A */
+
+ WRBLOCK(CE_REG_FI_SHT_INCR__A, 2),
+ 0x12, 0x00, /* CE_REG_FI_SHT_INCR__A */
+ 0x0C, 0x00, /* CE_REG_FI_EXP_NORM__A */
+
+ WRBLOCK(CE_REG_IR_INPUTSEL__A, 3),
+ 0x00, 0x00, /* CE_REG_IR_INPUTSEL__A */
+ 0x00, 0x00, /* CE_REG_IR_STARTPOS__A */
+ 0xFF, 0x00, /* CE_REG_IR_NEXP_THRES__A */
+
+ WR16(CE_REG_TI_NEXP_OFFS__A, 0x0000),
+
+ END_OF_TABLE
+};
+
+u8 DRXD_InitCEB1[] = {
+ WR16(B_CE_REG_TI_PHN_ENABLE__A, 0x0001),
+ WR16(B_CE_REG_FR_PM_SET__A, 0x000D),
+
+ END_OF_TABLE
+};
+
+u8 DRXD_InitEQA2[] = {
+ WRBLOCK(EQ_REG_OT_QNT_THRES0__A, 4),
+ 0x1E, 0x00, /* EQ_REG_OT_QNT_THRES0__A */
+ 0x1F, 0x00, /* EQ_REG_OT_QNT_THRES1__A */
+ 0x06, 0x00, /* EQ_REG_OT_CSI_STEP__A */
+ 0x02, 0x00, /* EQ_REG_OT_CSI_OFFSET__A */
+
+ WR16(EQ_REG_TD_REQ_SMB_CNT__A, 0x0200),
+ WR16(EQ_REG_IS_CLIP_EXP__A, 0x001F),
+ WR16(EQ_REG_SN_OFFSET__A, (u16) (-7)),
+ WR16(EQ_REG_RC_SEL_CAR__A, 0x0002),
+ WR16(EQ_REG_COMM_EXEC__A, 0x0001),
+ END_OF_TABLE
+};
+
+u8 DRXD_InitEQB1[] = {
+ WR16(B_EQ_REG_COMM_EXEC__A, 0x0001),
+ END_OF_TABLE
+};
+
+u8 DRXD_ResetECRAM[] = {
+ /* Reset packet sync bytes in EC_VD ram */
+ WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (0 * 17), 0x0000),
+ WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (1 * 17), 0x0000),
+ WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (2 * 17), 0x0000),
+ WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (3 * 17), 0x0000),
+ WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (4 * 17), 0x0000),
+ WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (5 * 17), 0x0000),
+ WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (6 * 17), 0x0000),
+ WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (7 * 17), 0x0000),
+ WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (8 * 17), 0x0000),
+ WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (9 * 17), 0x0000),
+ WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10 * 17), 0x0000),
+
+ /* Reset packet sync bytes in EC_RS ram */
+ WR16(EC_RS_EC_RAM__A, 0x0000),
+ WR16(EC_RS_EC_RAM__A + 204, 0x0000),
+ END_OF_TABLE
+};
+
+u8 DRXD_InitECA2[] = {
+ WRBLOCK(EC_SB_REG_CSI_HI__A, 6),
+ 0x1F, 0x00, /* EC_SB_REG_CSI_HI__A */
+ 0x1E, 0x00, /* EC_SB_REG_CSI_LO__A */
+ 0x01, 0x00, /* EC_SB_REG_SMB_TGL__A */
+ 0x7F, 0x00, /* EC_SB_REG_SNR_HI__A */
+ 0x7F, 0x00, /* EC_SB_REG_SNR_MID__A */
+ 0x7F, 0x00, /* EC_SB_REG_SNR_LO__A */
+
+ WRBLOCK(EC_RS_REG_REQ_PCK_CNT__A, 2),
+ 0x00, 0x10, /* EC_RS_REG_REQ_PCK_CNT__A */
+ DATA16(EC_RS_REG_VAL_PCK), /* EC_RS_REG_VAL__A */
+
+ WRBLOCK(EC_OC_REG_TMD_TOP_MODE__A, 5),
+ 0x03, 0x00, /* EC_OC_REG_TMD_TOP_MODE__A */
+ 0xF4, 0x01, /* EC_OC_REG_TMD_TOP_CNT__A */
+ 0xC0, 0x03, /* EC_OC_REG_TMD_HIL_MAR__A */
+ 0x40, 0x00, /* EC_OC_REG_TMD_LOL_MAR__A */
+ 0x03, 0x00, /* EC_OC_REG_TMD_CUR_CNT__A */
+
+ WRBLOCK(EC_OC_REG_AVR_ASH_CNT__A, 2),
+ 0x06, 0x00, /* EC_OC_REG_AVR_ASH_CNT__A */
+ 0x02, 0x00, /* EC_OC_REG_AVR_BSH_CNT__A */
+
+ WRBLOCK(EC_OC_REG_RCN_MODE__A, 7),
+ 0x07, 0x00, /* EC_OC_REG_RCN_MODE__A */
+ 0x00, 0x00, /* EC_OC_REG_RCN_CRA_LOP__A */
+ 0xc0, 0x00, /* EC_OC_REG_RCN_CRA_HIP__A */
+ 0x00, 0x10, /* EC_OC_REG_RCN_CST_LOP__A */
+ 0x00, 0x00, /* EC_OC_REG_RCN_CST_HIP__A */
+ 0xFF, 0x01, /* EC_OC_REG_RCN_SET_LVL__A */
+ 0x0D, 0x00, /* EC_OC_REG_RCN_GAI_LVL__A */
+
+ WRBLOCK(EC_OC_REG_RCN_CLP_LOP__A, 2),
+ 0x00, 0x00, /* EC_OC_REG_RCN_CLP_LOP__A */
+ 0xC0, 0x00, /* EC_OC_REG_RCN_CLP_HIP__A */
+
+ WR16(EC_SB_REG_CSI_OFS__A, 0x0001),
+ WR16(EC_VD_REG_FORCE__A, 0x0002),
+ WR16(EC_VD_REG_REQ_SMB_CNT__A, 0x0001),
+ WR16(EC_VD_REG_RLK_ENA__A, 0x0001),
+ WR16(EC_OD_REG_SYNC__A, 0x0664),
+ WR16(EC_OC_REG_OC_MON_SIO__A, 0x0000),
+ WR16(EC_OC_REG_SNC_ISC_LVL__A, 0x0D0C),
+ /* Output zero on monitorbus pads, power saving */
+ WR16(EC_OC_REG_OCR_MON_UOS__A,
+ (EC_OC_REG_OCR_MON_UOS_DAT_0_ENABLE |
+ EC_OC_REG_OCR_MON_UOS_DAT_1_ENABLE |
+ EC_OC_REG_OCR_MON_UOS_DAT_2_ENABLE |
+ EC_OC_REG_OCR_MON_UOS_DAT_3_ENABLE |
+ EC_OC_REG_OCR_MON_UOS_DAT_4_ENABLE |
+ EC_OC_REG_OCR_MON_UOS_DAT_5_ENABLE |
+ EC_OC_REG_OCR_MON_UOS_DAT_6_ENABLE |
+ EC_OC_REG_OCR_MON_UOS_DAT_7_ENABLE |
+ EC_OC_REG_OCR_MON_UOS_DAT_8_ENABLE |
+ EC_OC_REG_OCR_MON_UOS_DAT_9_ENABLE |
+ EC_OC_REG_OCR_MON_UOS_VAL_ENABLE |
+ EC_OC_REG_OCR_MON_UOS_CLK_ENABLE)),
+ WR16(EC_OC_REG_OCR_MON_WRI__A,
+ EC_OC_REG_OCR_MON_WRI_INIT),
+
+/* CHK_ERROR(ResetECRAM(demod)); */
+ /* Reset packet sync bytes in EC_VD ram */
+ WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (0 * 17), 0x0000),
+ WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (1 * 17), 0x0000),
+ WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (2 * 17), 0x0000),
+ WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (3 * 17), 0x0000),
+ WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (4 * 17), 0x0000),
+ WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (5 * 17), 0x0000),
+ WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (6 * 17), 0x0000),
+ WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (7 * 17), 0x0000),
+ WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (8 * 17), 0x0000),
+ WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (9 * 17), 0x0000),
+ WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10 * 17), 0x0000),
+
+ /* Reset packet sync bytes in EC_RS ram */
+ WR16(EC_RS_EC_RAM__A, 0x0000),
+ WR16(EC_RS_EC_RAM__A + 204, 0x0000),
+
+ WR16(EC_SB_REG_COMM_EXEC__A, 0x0001),
+ WR16(EC_VD_REG_COMM_EXEC__A, 0x0001),
+ WR16(EC_OD_REG_COMM_EXEC__A, 0x0001),
+ WR16(EC_RS_REG_COMM_EXEC__A, 0x0001),
+ END_OF_TABLE
+};
+
+u8 DRXD_InitECB1[] = {
+ WR16(B_EC_SB_REG_CSI_OFS0__A, 0x0001),
+ WR16(B_EC_SB_REG_CSI_OFS1__A, 0x0001),
+ WR16(B_EC_SB_REG_CSI_OFS2__A, 0x0001),
+ WR16(B_EC_SB_REG_CSI_LO__A, 0x000c),
+ WR16(B_EC_SB_REG_CSI_HI__A, 0x0018),
+ WR16(B_EC_SB_REG_SNR_HI__A, 0x007f),
+ WR16(B_EC_SB_REG_SNR_MID__A, 0x007f),
+ WR16(B_EC_SB_REG_SNR_LO__A, 0x007f),
+
+ WR16(B_EC_OC_REG_DTO_CLKMODE__A, 0x0002),
+ WR16(B_EC_OC_REG_DTO_PER__A, 0x0006),
+ WR16(B_EC_OC_REG_DTO_BUR__A, 0x0001),
+ WR16(B_EC_OC_REG_RCR_CLKMODE__A, 0x0000),
+ WR16(B_EC_OC_REG_RCN_GAI_LVL__A, 0x000D),
+ WR16(B_EC_OC_REG_OC_MPG_SIO__A, 0x0000),
+
+ /* Needed because shadow registers do not have correct default value */
+ WR16(B_EC_OC_REG_RCN_CST_LOP__A, 0x1000),
+ WR16(B_EC_OC_REG_RCN_CST_HIP__A, 0x0000),
+ WR16(B_EC_OC_REG_RCN_CRA_LOP__A, 0x0000),
+ WR16(B_EC_OC_REG_RCN_CRA_HIP__A, 0x00C0),
+ WR16(B_EC_OC_REG_RCN_CLP_LOP__A, 0x0000),
+ WR16(B_EC_OC_REG_RCN_CLP_HIP__A, 0x00C0),
+ WR16(B_EC_OC_REG_DTO_INC_LOP__A, 0x0000),
+ WR16(B_EC_OC_REG_DTO_INC_HIP__A, 0x00C0),
+
+ WR16(B_EC_OD_REG_SYNC__A, 0x0664),
+ WR16(B_EC_RS_REG_REQ_PCK_CNT__A, 0x1000),
+
+/* CHK_ERROR(ResetECRAM(demod)); */
+ /* Reset packet sync bytes in EC_VD ram */
+ WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (0 * 17), 0x0000),
+ WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (1 * 17), 0x0000),
+ WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (2 * 17), 0x0000),
+ WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (3 * 17), 0x0000),
+ WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (4 * 17), 0x0000),
+ WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (5 * 17), 0x0000),
+ WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (6 * 17), 0x0000),
+ WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (7 * 17), 0x0000),
+ WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (8 * 17), 0x0000),
+ WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (9 * 17), 0x0000),
+ WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10 * 17), 0x0000),
+
+ /* Reset packet sync bytes in EC_RS ram */
+ WR16(EC_RS_EC_RAM__A, 0x0000),
+ WR16(EC_RS_EC_RAM__A + 204, 0x0000),
+
+ WR16(B_EC_SB_REG_COMM_EXEC__A, 0x0001),
+ WR16(B_EC_VD_REG_COMM_EXEC__A, 0x0001),
+ WR16(B_EC_OD_REG_COMM_EXEC__A, 0x0001),
+ WR16(B_EC_RS_REG_COMM_EXEC__A, 0x0001),
+ END_OF_TABLE
+};
+
+u8 DRXD_ResetECA2[] = {
+
+ WR16(EC_OC_REG_COMM_EXEC__A, 0x0000),
+ WR16(EC_OD_REG_COMM_EXEC__A, 0x0000),
+
+ WRBLOCK(EC_OC_REG_TMD_TOP_MODE__A, 5),
+ 0x03, 0x00, /* EC_OC_REG_TMD_TOP_MODE__A */
+ 0xF4, 0x01, /* EC_OC_REG_TMD_TOP_CNT__A */
+ 0xC0, 0x03, /* EC_OC_REG_TMD_HIL_MAR__A */
+ 0x40, 0x00, /* EC_OC_REG_TMD_LOL_MAR__A */
+ 0x03, 0x00, /* EC_OC_REG_TMD_CUR_CNT__A */
+
+ WRBLOCK(EC_OC_REG_AVR_ASH_CNT__A, 2),
+ 0x06, 0x00, /* EC_OC_REG_AVR_ASH_CNT__A */
+ 0x02, 0x00, /* EC_OC_REG_AVR_BSH_CNT__A */
+
+ WRBLOCK(EC_OC_REG_RCN_MODE__A, 7),
+ 0x07, 0x00, /* EC_OC_REG_RCN_MODE__A */
+ 0x00, 0x00, /* EC_OC_REG_RCN_CRA_LOP__A */
+ 0xc0, 0x00, /* EC_OC_REG_RCN_CRA_HIP__A */
+ 0x00, 0x10, /* EC_OC_REG_RCN_CST_LOP__A */
+ 0x00, 0x00, /* EC_OC_REG_RCN_CST_HIP__A */
+ 0xFF, 0x01, /* EC_OC_REG_RCN_SET_LVL__A */
+ 0x0D, 0x00, /* EC_OC_REG_RCN_GAI_LVL__A */
+
+ WRBLOCK(EC_OC_REG_RCN_CLP_LOP__A, 2),
+ 0x00, 0x00, /* EC_OC_REG_RCN_CLP_LOP__A */
+ 0xC0, 0x00, /* EC_OC_REG_RCN_CLP_HIP__A */
+
+ WR16(EC_OD_REG_SYNC__A, 0x0664),
+ WR16(EC_OC_REG_OC_MON_SIO__A, 0x0000),
+ WR16(EC_OC_REG_SNC_ISC_LVL__A, 0x0D0C),
+ /* Output zero on monitorbus pads, power saving */
+ WR16(EC_OC_REG_OCR_MON_UOS__A,
+ (EC_OC_REG_OCR_MON_UOS_DAT_0_ENABLE |
+ EC_OC_REG_OCR_MON_UOS_DAT_1_ENABLE |
+ EC_OC_REG_OCR_MON_UOS_DAT_2_ENABLE |
+ EC_OC_REG_OCR_MON_UOS_DAT_3_ENABLE |
+ EC_OC_REG_OCR_MON_UOS_DAT_4_ENABLE |
+ EC_OC_REG_OCR_MON_UOS_DAT_5_ENABLE |
+ EC_OC_REG_OCR_MON_UOS_DAT_6_ENABLE |
+ EC_OC_REG_OCR_MON_UOS_DAT_7_ENABLE |
+ EC_OC_REG_OCR_MON_UOS_DAT_8_ENABLE |
+ EC_OC_REG_OCR_MON_UOS_DAT_9_ENABLE |
+ EC_OC_REG_OCR_MON_UOS_VAL_ENABLE |
+ EC_OC_REG_OCR_MON_UOS_CLK_ENABLE)),
+ WR16(EC_OC_REG_OCR_MON_WRI__A,
+ EC_OC_REG_OCR_MON_WRI_INIT),
+
+/* CHK_ERROR(ResetECRAM(demod)); */
+ /* Reset packet sync bytes in EC_VD ram */
+ WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (0 * 17), 0x0000),
+ WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (1 * 17), 0x0000),
+ WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (2 * 17), 0x0000),
+ WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (3 * 17), 0x0000),
+ WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (4 * 17), 0x0000),
+ WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (5 * 17), 0x0000),
+ WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (6 * 17), 0x0000),
+ WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (7 * 17), 0x0000),
+ WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (8 * 17), 0x0000),
+ WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (9 * 17), 0x0000),
+ WR16(EC_OD_DEINT_RAM__A + 0x3b7 + (10 * 17), 0x0000),
+
+ /* Reset packet sync bytes in EC_RS ram */
+ WR16(EC_RS_EC_RAM__A, 0x0000),
+ WR16(EC_RS_EC_RAM__A + 204, 0x0000),
+
+ WR16(EC_OD_REG_COMM_EXEC__A, 0x0001),
+ END_OF_TABLE
+};
+
+u8 DRXD_InitSC[] = {
+ WR16(SC_COMM_EXEC__A, 0),
+ WR16(SC_COMM_STATE__A, 0),
+
+#ifdef COMPILE_FOR_QT
+ WR16(SC_RA_RAM_BE_OPT_DELAY__A, 0x100),
+#endif
+
+ /* SC is not started, this is done in SetChannels() */
+ END_OF_TABLE
+};
+
+/* Diversity settings */
+
+u8 DRXD_InitDiversityFront[] = {
+ /* Start demod ********* RF in , diversity out **************************** */
+ WR16(B_SC_RA_RAM_CONFIG__A, B_SC_RA_RAM_CONFIG_FR_ENABLE__M |
+ B_SC_RA_RAM_CONFIG_FREQSCAN__M),
+
+ WR16(B_SC_RA_RAM_LC_ABS_2K__A, 0x7),
+ WR16(B_SC_RA_RAM_LC_ABS_8K__A, 0x7),
+ WR16(B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A, IRLEN_COARSE_8K),
+ WR16(B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A, 1 << (11 - IRLEN_COARSE_8K)),
+ WR16(B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A, 1 << (17 - IRLEN_COARSE_8K)),
+ WR16(B_SC_RA_RAM_IR_FINE_8K_LENGTH__A, IRLEN_FINE_8K),
+ WR16(B_SC_RA_RAM_IR_FINE_8K_FREQINC__A, 1 << (11 - IRLEN_FINE_8K)),
+ WR16(B_SC_RA_RAM_IR_FINE_8K_KAISINC__A, 1 << (17 - IRLEN_FINE_8K)),
+
+ WR16(B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A, IRLEN_COARSE_2K),
+ WR16(B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A, 1 << (11 - IRLEN_COARSE_2K)),
+ WR16(B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A, 1 << (17 - IRLEN_COARSE_2K)),
+ WR16(B_SC_RA_RAM_IR_FINE_2K_LENGTH__A, IRLEN_FINE_2K),
+ WR16(B_SC_RA_RAM_IR_FINE_2K_FREQINC__A, 1 << (11 - IRLEN_FINE_2K)),
+ WR16(B_SC_RA_RAM_IR_FINE_2K_KAISINC__A, 1 << (17 - IRLEN_FINE_2K)),
+
+ WR16(B_LC_RA_RAM_FILTER_CRMM_A__A, 7),
+ WR16(B_LC_RA_RAM_FILTER_CRMM_B__A, 4),
+ WR16(B_LC_RA_RAM_FILTER_SRMM_A__A, 7),
+ WR16(B_LC_RA_RAM_FILTER_SRMM_B__A, 4),
+ WR16(B_LC_RA_RAM_FILTER_SYM_SET__A, 500),
+
+ WR16(B_CC_REG_DIVERSITY__A, 0x0001),
+ WR16(B_EC_OC_REG_OC_MODE_HIP__A, 0x0010),
+ WR16(B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_PASS_B_CE |
+ B_EQ_REG_RC_SEL_CAR_LOCAL_B_CE | B_EQ_REG_RC_SEL_CAR_MEAS_B_CE),
+
+ /* 0x2a ), *//* CE to PASS mux */
+
+ END_OF_TABLE
+};
+
+u8 DRXD_InitDiversityEnd[] = {
+ /* End demod *********** combining RF in and diversity in, MPEG TS out **** */
+ /* disable near/far; switch on timing slave mode */
+ WR16(B_SC_RA_RAM_CONFIG__A, B_SC_RA_RAM_CONFIG_FR_ENABLE__M |
+ B_SC_RA_RAM_CONFIG_FREQSCAN__M |
+ B_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__M |
+ B_SC_RA_RAM_CONFIG_SLAVE__M |
+ B_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__M
+/* MV from CtrlDiversity */
+ ),
+#ifdef DRXDDIV_SRMM_SLAVING
+ WR16(SC_RA_RAM_LC_ABS_2K__A, 0x3c7),
+ WR16(SC_RA_RAM_LC_ABS_8K__A, 0x3c7),
+#else
+ WR16(SC_RA_RAM_LC_ABS_2K__A, 0x7),
+ WR16(SC_RA_RAM_LC_ABS_8K__A, 0x7),
+#endif
+
+ WR16(B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A, IRLEN_COARSE_8K),
+ WR16(B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A, 1 << (11 - IRLEN_COARSE_8K)),
+ WR16(B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A, 1 << (17 - IRLEN_COARSE_8K)),
+ WR16(B_SC_RA_RAM_IR_FINE_8K_LENGTH__A, IRLEN_FINE_8K),
+ WR16(B_SC_RA_RAM_IR_FINE_8K_FREQINC__A, 1 << (11 - IRLEN_FINE_8K)),
+ WR16(B_SC_RA_RAM_IR_FINE_8K_KAISINC__A, 1 << (17 - IRLEN_FINE_8K)),
+
+ WR16(B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A, IRLEN_COARSE_2K),
+ WR16(B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A, 1 << (11 - IRLEN_COARSE_2K)),
+ WR16(B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A, 1 << (17 - IRLEN_COARSE_2K)),
+ WR16(B_SC_RA_RAM_IR_FINE_2K_LENGTH__A, IRLEN_FINE_2K),
+ WR16(B_SC_RA_RAM_IR_FINE_2K_FREQINC__A, 1 << (11 - IRLEN_FINE_2K)),
+ WR16(B_SC_RA_RAM_IR_FINE_2K_KAISINC__A, 1 << (17 - IRLEN_FINE_2K)),
+
+ WR16(B_LC_RA_RAM_FILTER_CRMM_A__A, 7),
+ WR16(B_LC_RA_RAM_FILTER_CRMM_B__A, 4),
+ WR16(B_LC_RA_RAM_FILTER_SRMM_A__A, 7),
+ WR16(B_LC_RA_RAM_FILTER_SRMM_B__A, 4),
+ WR16(B_LC_RA_RAM_FILTER_SYM_SET__A, 500),
+
+ WR16(B_CC_REG_DIVERSITY__A, 0x0001),
+ END_OF_TABLE
+};
+
+u8 DRXD_DisableDiversity[] = {
+ WR16(B_SC_RA_RAM_LC_ABS_2K__A, B_SC_RA_RAM_LC_ABS_2K__PRE),
+ WR16(B_SC_RA_RAM_LC_ABS_8K__A, B_SC_RA_RAM_LC_ABS_8K__PRE),
+ WR16(B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A,
+ B_SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE),
+ WR16(B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A,
+ B_SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE),
+ WR16(B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A,
+ B_SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE),
+ WR16(B_SC_RA_RAM_IR_FINE_8K_LENGTH__A,
+ B_SC_RA_RAM_IR_FINE_8K_LENGTH__PRE),
+ WR16(B_SC_RA_RAM_IR_FINE_8K_FREQINC__A,
+ B_SC_RA_RAM_IR_FINE_8K_FREQINC__PRE),
+ WR16(B_SC_RA_RAM_IR_FINE_8K_KAISINC__A,
+ B_SC_RA_RAM_IR_FINE_8K_KAISINC__PRE),
+
+ WR16(B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A,
+ B_SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE),
+ WR16(B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A,
+ B_SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE),
+ WR16(B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A,
+ B_SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE),
+ WR16(B_SC_RA_RAM_IR_FINE_2K_LENGTH__A,
+ B_SC_RA_RAM_IR_FINE_2K_LENGTH__PRE),
+ WR16(B_SC_RA_RAM_IR_FINE_2K_FREQINC__A,
+ B_SC_RA_RAM_IR_FINE_2K_FREQINC__PRE),
+ WR16(B_SC_RA_RAM_IR_FINE_2K_KAISINC__A,
+ B_SC_RA_RAM_IR_FINE_2K_KAISINC__PRE),
+
+ WR16(B_LC_RA_RAM_FILTER_CRMM_A__A, B_LC_RA_RAM_FILTER_CRMM_A__PRE),
+ WR16(B_LC_RA_RAM_FILTER_CRMM_B__A, B_LC_RA_RAM_FILTER_CRMM_B__PRE),
+ WR16(B_LC_RA_RAM_FILTER_SRMM_A__A, B_LC_RA_RAM_FILTER_SRMM_A__PRE),
+ WR16(B_LC_RA_RAM_FILTER_SRMM_B__A, B_LC_RA_RAM_FILTER_SRMM_B__PRE),
+ WR16(B_LC_RA_RAM_FILTER_SYM_SET__A, B_LC_RA_RAM_FILTER_SYM_SET__PRE),
+
+ WR16(B_CC_REG_DIVERSITY__A, 0x0000),
+ WR16(B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_INIT), /* combining disabled */
+
+ END_OF_TABLE
+};
+
+u8 DRXD_StartDiversityFront[] = {
+ /* Start demod, RF in and diversity out, no combining */
+ WR16(B_FE_CF_REG_IMP_VAL__A, 0x0),
+ WR16(B_FE_AD_REG_FDB_IN__A, 0x0),
+ WR16(B_FE_AD_REG_INVEXT__A, 0x0),
+ WR16(B_EQ_REG_COMM_MB__A, 0x12), /* EQ to MB out */
+ WR16(B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_PASS_B_CE | /* CE to PASS mux */
+ B_EQ_REG_RC_SEL_CAR_LOCAL_B_CE | B_EQ_REG_RC_SEL_CAR_MEAS_B_CE),
+
+ WR16(SC_RA_RAM_ECHO_SHIFT_LIM__A, 2),
+
+ END_OF_TABLE
+};
+
+u8 DRXD_StartDiversityEnd[] = {
+ /* End demod, combining RF in and diversity in, MPEG TS out */
+ WR16(B_FE_CF_REG_IMP_VAL__A, 0x0), /* disable impulse noise cruncher */
+ WR16(B_FE_AD_REG_INVEXT__A, 0x0), /* clock inversion (for sohard board) */
+ WR16(B_CP_REG_BR_STR_DEL__A, 10), /* apperently no mb delay matching is best */
+
+ WR16(B_EQ_REG_RC_SEL_CAR__A, B_EQ_REG_RC_SEL_CAR_DIV_ON | /* org = 0x81 combining enabled */
+ B_EQ_REG_RC_SEL_CAR_MEAS_A_CC |
+ B_EQ_REG_RC_SEL_CAR_PASS_A_CC | B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC),
+
+ END_OF_TABLE
+};
+
+u8 DRXD_DiversityDelay8MHZ[] = {
+ WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A, 1150 - 50),
+ WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A, 1100 - 50),
+ WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A, 1000 - 50),
+ WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__A, 800 - 50),
+ WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A, 5420 - 50),
+ WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__A, 5200 - 50),
+ WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__A, 4800 - 50),
+ WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__A, 4000 - 50),
+ END_OF_TABLE
+};
+
+u8 DRXD_DiversityDelay6MHZ[] = /* also used ok for 7 MHz */
+{
+ WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A, 1100 - 50),
+ WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A, 1000 - 50),
+ WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A, 900 - 50),
+ WR16(B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__A, 600 - 50),
+ WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A, 5300 - 50),
+ WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__A, 5000 - 50),
+ WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__A, 4500 - 50),
+ WR16(B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__A, 3500 - 50),
+ END_OF_TABLE
+};
diff --git a/drivers/media/dvb/frontends/drxd_firm.h b/drivers/media/dvb/frontends/drxd_firm.h
new file mode 100644
index 0000000..41597e8
--- /dev/null
+++ b/drivers/media/dvb/frontends/drxd_firm.h
@@ -0,0 +1,115 @@
+/*
+ * drxd_firm.h
+ *
+ * Copyright (C) 2006-2007 Micronas
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 only, as published by the Free Software Foundation.
+ *
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA
+ * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef _DRXD_FIRM_H_
+#define _DRXD_FIRM_H_
+
+#include <linux/types.h>
+#include "drxd_map_firm.h"
+
+#define VERSION_MAJOR 1
+#define VERSION_MINOR 4
+#define VERSION_PATCH 23
+
+#define HI_TR_FUNC_ADDR HI_IF_RAM_USR_BEGIN__A
+
+#define DRXD_MAX_RETRIES (1000)
+#define HI_I2C_DELAY 84
+#define HI_I2C_BRIDGE_DELAY 750
+
+#define EQ_TD_TPS_PWR_UNKNOWN 0x00C0 /* Unknown configurations */
+#define EQ_TD_TPS_PWR_QPSK 0x016a
+#define EQ_TD_TPS_PWR_QAM16_ALPHAN 0x0195
+#define EQ_TD_TPS_PWR_QAM16_ALPHA1 0x0195
+#define EQ_TD_TPS_PWR_QAM16_ALPHA2 0x011E
+#define EQ_TD_TPS_PWR_QAM16_ALPHA4 0x01CE
+#define EQ_TD_TPS_PWR_QAM64_ALPHAN 0x019F
+#define EQ_TD_TPS_PWR_QAM64_ALPHA1 0x019F
+#define EQ_TD_TPS_PWR_QAM64_ALPHA2 0x00F8
+#define EQ_TD_TPS_PWR_QAM64_ALPHA4 0x014D
+
+#define DRXD_DEF_AG_PWD_CONSUMER 0x000E
+#define DRXD_DEF_AG_PWD_PRO 0x0000
+#define DRXD_DEF_AG_AGC_SIO 0x0000
+
+#define DRXD_FE_CTRL_MAX 1023
+
+#define DRXD_OSCDEV_DO_SCAN (16)
+
+#define DRXD_OSCDEV_DONT_SCAN (0)
+
+#define DRXD_OSCDEV_STEP (275)
+
+#define DRXD_SCAN_TIMEOUT (650)
+
+#define DRXD_BANDWIDTH_8MHZ_IN_HZ (0x8B8249L)
+#define DRXD_BANDWIDTH_7MHZ_IN_HZ (0x7A1200L)
+#define DRXD_BANDWIDTH_6MHZ_IN_HZ (0x68A1B6L)
+
+#define IRLEN_COARSE_8K (10)
+#define IRLEN_FINE_8K (10)
+#define IRLEN_COARSE_2K (7)
+#define IRLEN_FINE_2K (9)
+#define DIFF_INVALID (511)
+#define DIFF_TARGET (4)
+#define DIFF_MARGIN (1)
+
+extern u8 DRXD_InitAtomicRead[];
+extern u8 DRXD_HiI2cPatch_1[];
+extern u8 DRXD_HiI2cPatch_3[];
+
+extern u8 DRXD_InitSC[];
+
+extern u8 DRXD_ResetCEFR[];
+extern u8 DRXD_InitFEA2_1[];
+extern u8 DRXD_InitFEA2_2[];
+extern u8 DRXD_InitCPA2[];
+extern u8 DRXD_InitCEA2[];
+extern u8 DRXD_InitEQA2[];
+extern u8 DRXD_InitECA2[];
+extern u8 DRXD_ResetECA2[];
+extern u8 DRXD_ResetECRAM[];
+
+extern u8 DRXD_A2_microcode[];
+extern u32 DRXD_A2_microcode_length;
+
+extern u8 DRXD_InitFEB1_1[];
+extern u8 DRXD_InitFEB1_2[];
+extern u8 DRXD_InitCPB1[];
+extern u8 DRXD_InitCEB1[];
+extern u8 DRXD_InitEQB1[];
+extern u8 DRXD_InitECB1[];
+
+extern u8 DRXD_InitDiversityFront[];
+extern u8 DRXD_InitDiversityEnd[];
+extern u8 DRXD_DisableDiversity[];
+extern u8 DRXD_StartDiversityFront[];
+extern u8 DRXD_StartDiversityEnd[];
+
+extern u8 DRXD_DiversityDelay8MHZ[];
+extern u8 DRXD_DiversityDelay6MHZ[];
+
+extern u8 DRXD_B1_microcode[];
+extern u32 DRXD_B1_microcode_length;
+
+#endif
diff --git a/drivers/media/dvb/frontends/drxd_hard.c b/drivers/media/dvb/frontends/drxd_hard.c
new file mode 100644
index 0000000..ea4c1c3
--- /dev/null
+++ b/drivers/media/dvb/frontends/drxd_hard.c
@@ -0,0 +1,3001 @@
+/*
+ * drxd_hard.c: DVB-T Demodulator Micronas DRX3975D-A2,DRX397xD-B1
+ *
+ * Copyright (C) 2003-2007 Micronas
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 only, as published by the Free Software Foundation.
+ *
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA
+ * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/delay.h>
+#include <linux/firmware.h>
+#include <linux/i2c.h>
+#include <linux/version.h>
+#include <asm/div64.h>
+
+#include "dvb_frontend.h"
+#include "drxd.h"
+#include "drxd_firm.h"
+
+#define DRX_FW_FILENAME_A2 "drxd-a2-1.1.fw"
+#define DRX_FW_FILENAME_B1 "drxd-b1-1.1.fw"
+
+#define CHUNK_SIZE 48
+
+#define DRX_I2C_RMW 0x10
+#define DRX_I2C_BROADCAST 0x20
+#define DRX_I2C_CLEARCRC 0x80
+#define DRX_I2C_SINGLE_MASTER 0xC0
+#define DRX_I2C_MODEFLAGS 0xC0
+#define DRX_I2C_FLAGS 0xF0
+
+#ifndef SIZEOF_ARRAY
+#define SIZEOF_ARRAY(array) (sizeof((array))/sizeof((array)[0]))
+#endif
+
+#define DEFAULT_LOCK_TIMEOUT 1100
+
+#define DRX_CHANNEL_AUTO 0
+#define DRX_CHANNEL_HIGH 1
+#define DRX_CHANNEL_LOW 2
+
+#define DRX_LOCK_MPEG 1
+#define DRX_LOCK_FEC 2
+#define DRX_LOCK_DEMOD 4
+
+/****************************************************************************/
+
+enum CSCDState {
+ CSCD_INIT = 0,
+ CSCD_SET,
+ CSCD_SAVED
+};
+
+enum CDrxdState {
+ DRXD_UNINITIALIZED = 0,
+ DRXD_STOPPED,
+ DRXD_STARTED
+};
+
+enum AGC_CTRL_MODE {
+ AGC_CTRL_AUTO = 0,
+ AGC_CTRL_USER,
+ AGC_CTRL_OFF
+};
+
+enum OperationMode {
+ OM_Default,
+ OM_DVBT_Diversity_Front,
+ OM_DVBT_Diversity_End
+};
+
+struct SCfgAgc {
+ enum AGC_CTRL_MODE ctrlMode;
+ u16 outputLevel; /* range [0, ... , 1023], 1/n of fullscale range */
+ u16 settleLevel; /* range [0, ... , 1023], 1/n of fullscale range */
+ u16 minOutputLevel; /* range [0, ... , 1023], 1/n of fullscale range */
+ u16 maxOutputLevel; /* range [0, ... , 1023], 1/n of fullscale range */
+ u16 speed; /* range [0, ... , 1023], 1/n of fullscale range */
+
+ u16 R1;
+ u16 R2;
+ u16 R3;
+};
+
+struct SNoiseCal {
+ int cpOpt;
+ u16 cpNexpOfs;
+ u16 tdCal2k;
+ u16 tdCal8k;
+};
+
+enum app_env {
+ APPENV_STATIC = 0,
+ APPENV_PORTABLE = 1,
+ APPENV_MOBILE = 2
+};
+
+enum EIFFilter {
+ IFFILTER_SAW = 0,
+ IFFILTER_DISCRETE = 1
+};
+
+struct drxd_state {
+ struct dvb_frontend frontend;
+ struct dvb_frontend_ops ops;
+ struct dvb_frontend_parameters param;
+
+ const struct firmware *fw;
+ struct device *dev;
+
+ struct i2c_adapter *i2c;
+ void *priv;
+ struct drxd_config config;
+
+ int i2c_access;
+ int init_done;
+ struct mutex mutex;
+
+ u8 chip_adr;
+ u16 hi_cfg_timing_div;
+ u16 hi_cfg_bridge_delay;
+ u16 hi_cfg_wakeup_key;
+ u16 hi_cfg_ctrl;
+
+ u16 intermediate_freq;
+ u16 osc_clock_freq;
+
+ enum CSCDState cscd_state;
+ enum CDrxdState drxd_state;
+
+ u16 sys_clock_freq;
+ s16 osc_clock_deviation;
+ u16 expected_sys_clock_freq;
+
+ u16 insert_rs_byte;
+ u16 enable_parallel;
+
+ int operation_mode;
+
+ struct SCfgAgc if_agc_cfg;
+ struct SCfgAgc rf_agc_cfg;
+
+ struct SNoiseCal noise_cal;
+
+ u32 fe_fs_add_incr;
+ u32 org_fe_fs_add_incr;
+ u16 current_fe_if_incr;
+
+ u16 m_FeAgRegAgPwd;
+ u16 m_FeAgRegAgAgcSio;
+
+ u16 m_EcOcRegOcModeLop;
+ u16 m_EcOcRegSncSncLvl;
+ u8 *m_InitAtomicRead;
+ u8 *m_HiI2cPatch;
+
+ u8 *m_ResetCEFR;
+ u8 *m_InitFE_1;
+ u8 *m_InitFE_2;
+ u8 *m_InitCP;
+ u8 *m_InitCE;
+ u8 *m_InitEQ;
+ u8 *m_InitSC;
+ u8 *m_InitEC;
+ u8 *m_ResetECRAM;
+ u8 *m_InitDiversityFront;
+ u8 *m_InitDiversityEnd;
+ u8 *m_DisableDiversity;
+ u8 *m_StartDiversityFront;
+ u8 *m_StartDiversityEnd;
+
+ u8 *m_DiversityDelay8MHZ;
+ u8 *m_DiversityDelay6MHZ;
+
+ u8 *microcode;
+ u32 microcode_length;
+
+ int type_A;
+ int PGA;
+ int diversity;
+ int tuner_mirrors;
+
+ enum app_env app_env_default;
+ enum app_env app_env_diversity;
+
+};
+
+/****************************************************************************/
+/* I2C **********************************************************************/
+/****************************************************************************/
+
+static int i2c_write(struct i2c_adapter *adap, u8 adr, u8 * data, int len)
+{
+ struct i2c_msg msg = {.addr = adr, .flags = 0, .buf = data, .len = len };
+
+ if (i2c_transfer(adap, &msg, 1) != 1)
+ return -1;
+ return 0;
+}
+
+static int i2c_read(struct i2c_adapter *adap,
+ u8 adr, u8 *msg, int len, u8 *answ, int alen)
+{
+ struct i2c_msg msgs[2] = {
+ {
+ .addr = adr, .flags = 0,
+ .buf = msg, .len = len
+ }, {
+ .addr = adr, .flags = I2C_M_RD,
+ .buf = answ, .len = alen
+ }
+ };
+ if (i2c_transfer(adap, msgs, 2) != 2)
+ return -1;
+ return 0;
+}
+
+inline u32 MulDiv32(u32 a, u32 b, u32 c)
+{
+ u64 tmp64;
+
+ tmp64 = (u64)a * (u64)b;
+ do_div(tmp64, c);
+
+ return (u32) tmp64;
+}
+
+static int Read16(struct drxd_state *state, u32 reg, u16 *data, u8 flags)
+{
+ u8 adr = state->config.demod_address;
+ u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff,
+ flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
+ };
+ u8 mm2[2];
+ if (i2c_read(state->i2c, adr, mm1, 4, mm2, 2) < 0)
+ return -1;
+ if (data)
+ *data = mm2[0] | (mm2[1] << 8);
+ return mm2[0] | (mm2[1] << 8);
+}
+
+static int Read32(struct drxd_state *state, u32 reg, u32 *data, u8 flags)
+{
+ u8 adr = state->config.demod_address;
+ u8 mm1[4] = { reg & 0xff, (reg >> 16) & 0xff,
+ flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
+ };
+ u8 mm2[4];
+
+ if (i2c_read(state->i2c, adr, mm1, 4, mm2, 4) < 0)
+ return -1;
+ if (data)
+ *data =
+ mm2[0] | (mm2[1] << 8) | (mm2[2] << 16) | (mm2[3] << 24);
+ return 0;
+}
+
+static int Write16(struct drxd_state *state, u32 reg, u16 data, u8 flags)
+{
+ u8 adr = state->config.demod_address;
+ u8 mm[6] = { reg & 0xff, (reg >> 16) & 0xff,
+ flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff,
+ data & 0xff, (data >> 8) & 0xff
+ };
+
+ if (i2c_write(state->i2c, adr, mm, 6) < 0)
+ return -1;
+ return 0;
+}
+
+static int Write32(struct drxd_state *state, u32 reg, u32 data, u8 flags)
+{
+ u8 adr = state->config.demod_address;
+ u8 mm[8] = { reg & 0xff, (reg >> 16) & 0xff,
+ flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff,
+ data & 0xff, (data >> 8) & 0xff,
+ (data >> 16) & 0xff, (data >> 24) & 0xff
+ };
+
+ if (i2c_write(state->i2c, adr, mm, 8) < 0)
+ return -1;
+ return 0;
+}
+
+static int write_chunk(struct drxd_state *state,
+ u32 reg, u8 *data, u32 len, u8 flags)
+{
+ u8 adr = state->config.demod_address;
+ u8 mm[CHUNK_SIZE + 4] = { reg & 0xff, (reg >> 16) & 0xff,
+ flags | ((reg >> 24) & 0xff), (reg >> 8) & 0xff
+ };
+ int i;
+
+ for (i = 0; i < len; i++)
+ mm[4 + i] = data[i];
+ if (i2c_write(state->i2c, adr, mm, 4 + len) < 0) {
+ printk(KERN_ERR "error in write_chunk\n");
+ return -1;
+ }
+ return 0;
+}
+
+static int WriteBlock(struct drxd_state *state,
+ u32 Address, u16 BlockSize, u8 *pBlock, u8 Flags)
+{
+ while (BlockSize > 0) {
+ u16 Chunk = BlockSize > CHUNK_SIZE ? CHUNK_SIZE : BlockSize;
+
+ if (write_chunk(state, Address, pBlock, Chunk, Flags) < 0)
+ return -1;
+ pBlock += Chunk;
+ Address += (Chunk >> 1);
+ BlockSize -= Chunk;
+ }
+ return 0;
+}
+
+static int WriteTable(struct drxd_state *state, u8 * pTable)
+{
+ int status = 0;
+
+ if (pTable == NULL)
+ return 0;
+
+ while (!status) {
+ u16 Length;
+ u32 Address = pTable[0] | (pTable[1] << 8) |
+ (pTable[2] << 16) | (pTable[3] << 24);
+
+ if (Address == 0xFFFFFFFF)
+ break;
+ pTable += sizeof(u32);
+
+ Length = pTable[0] | (pTable[1] << 8);
+ pTable += sizeof(u16);
+ if (!Length)
+ break;
+ status = WriteBlock(state, Address, Length * 2, pTable, 0);
+ pTable += (Length * 2);
+ }
+ return status;
+}
+
+/****************************************************************************/
+/****************************************************************************/
+/****************************************************************************/
+
+static int ResetCEFR(struct drxd_state *state)
+{
+ return WriteTable(state, state->m_ResetCEFR);
+}
+
+static int InitCP(struct drxd_state *state)
+{
+ return WriteTable(state, state->m_InitCP);
+}
+
+static int InitCE(struct drxd_state *state)
+{
+ int status;
+ enum app_env AppEnv = state->app_env_default;
+
+ do {
+ status = WriteTable(state, state->m_InitCE);
+ if (status < 0)
+ break;
+
+ if (state->operation_mode == OM_DVBT_Diversity_Front ||
+ state->operation_mode == OM_DVBT_Diversity_End) {
+ AppEnv = state->app_env_diversity;
+ }
+ if (AppEnv == APPENV_STATIC) {
+ status = Write16(state, CE_REG_TAPSET__A, 0x0000, 0);
+ if (status < 0)
+ break;
+ } else if (AppEnv == APPENV_PORTABLE) {
+ status = Write16(state, CE_REG_TAPSET__A, 0x0001, 0);
+ if (status < 0)
+ break;
+ } else if (AppEnv == APPENV_MOBILE && state->type_A) {
+ status = Write16(state, CE_REG_TAPSET__A, 0x0002, 0);
+ if (status < 0)
+ break;
+ } else if (AppEnv == APPENV_MOBILE && !state->type_A) {
+ status = Write16(state, CE_REG_TAPSET__A, 0x0006, 0);
+ if (status < 0)
+ break;
+ }
+
+ /* start ce */
+ status = Write16(state, B_CE_REG_COMM_EXEC__A, 0x0001, 0);
+ if (status < 0)
+ break;
+ } while (0);
+ return status;
+}
+
+static int StopOC(struct drxd_state *state)
+{
+ int status = 0;
+ u16 ocSyncLvl = 0;
+ u16 ocModeLop = state->m_EcOcRegOcModeLop;
+ u16 dtoIncLop = 0;
+ u16 dtoIncHip = 0;
+
+ do {
+ /* Store output configuration */
+ status = Read16(state, EC_OC_REG_SNC_ISC_LVL__A, &ocSyncLvl, 0);
+ if (status < 0)
+ break;
+ /* CHK_ERROR(Read16(EC_OC_REG_OC_MODE_LOP__A, &ocModeLop)); */
+ state->m_EcOcRegSncSncLvl = ocSyncLvl;
+ /* m_EcOcRegOcModeLop = ocModeLop; */
+
+ /* Flush FIFO (byte-boundary) at fixed rate */
+ status = Read16(state, EC_OC_REG_RCN_MAP_LOP__A, &dtoIncLop, 0);
+ if (status < 0)
+ break;
+ status = Read16(state, EC_OC_REG_RCN_MAP_HIP__A, &dtoIncHip, 0);
+ if (status < 0)
+ break;
+ status = Write16(state, EC_OC_REG_DTO_INC_LOP__A, dtoIncLop, 0);
+ if (status < 0)
+ break;
+ status = Write16(state, EC_OC_REG_DTO_INC_HIP__A, dtoIncHip, 0);
+ if (status < 0)
+ break;
+ ocModeLop &= ~(EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M);
+ ocModeLop |= EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC;
+ status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0);
+ if (status < 0)
+ break;
+ status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0);
+ if (status < 0)
+ break;
+
+ msleep(1);
+ /* Output pins to '0' */
+ status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS__M, 0);
+ if (status < 0)
+ break;
+
+ /* Force the OC out of sync */
+ ocSyncLvl &= ~(EC_OC_REG_SNC_ISC_LVL_OSC__M);
+ status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, ocSyncLvl, 0);
+ if (status < 0)
+ break;
+ ocModeLop &= ~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M);
+ ocModeLop |= EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE;
+ ocModeLop |= 0x2; /* Magically-out-of-sync */
+ status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, ocModeLop, 0);
+ if (status < 0)
+ break;
+ status = Write16(state, EC_OC_REG_COMM_INT_STA__A, 0x0, 0);
+ if (status < 0)
+ break;
+ status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0);
+ if (status < 0)
+ break;
+ } while (0);
+
+ return status;
+}
+
+static int StartOC(struct drxd_state *state)
+{
+ int status = 0;
+
+ do {
+ /* Stop OC */
+ status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_HOLD, 0);
+ if (status < 0)
+ break;
+
+ /* Restore output configuration */
+ status = Write16(state, EC_OC_REG_SNC_ISC_LVL__A, state->m_EcOcRegSncSncLvl, 0);
+ if (status < 0)
+ break;
+ status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, state->m_EcOcRegOcModeLop, 0);
+ if (status < 0)
+ break;
+
+ /* Output pins active again */
+ status = Write16(state, EC_OC_REG_OCR_MPG_UOS__A, EC_OC_REG_OCR_MPG_UOS_INIT, 0);
+ if (status < 0)
+ break;
+
+ /* Start OC */
+ status = Write16(state, EC_OC_REG_COMM_EXEC__A, EC_OC_REG_COMM_EXEC_CTL_ACTIVE, 0);
+ if (status < 0)
+ break;
+ } while (0);
+ return status;
+}
+
+static int InitEQ(struct drxd_state *state)
+{
+ return WriteTable(state, state->m_InitEQ);
+}
+
+static int InitEC(struct drxd_state *state)
+{
+ return WriteTable(state, state->m_InitEC);
+}
+
+static int InitSC(struct drxd_state *state)
+{
+ return WriteTable(state, state->m_InitSC);
+}
+
+static int InitAtomicRead(struct drxd_state *state)
+{
+ return WriteTable(state, state->m_InitAtomicRead);
+}
+
+static int CorrectSysClockDeviation(struct drxd_state *state);
+
+static int DRX_GetLockStatus(struct drxd_state *state, u32 * pLockStatus)
+{
+ u16 ScRaRamLock = 0;
+ const u16 mpeg_lock_mask = (SC_RA_RAM_LOCK_MPEG__M |
+ SC_RA_RAM_LOCK_FEC__M |
+ SC_RA_RAM_LOCK_DEMOD__M);
+ const u16 fec_lock_mask = (SC_RA_RAM_LOCK_FEC__M |
+ SC_RA_RAM_LOCK_DEMOD__M);
+ const u16 demod_lock_mask = SC_RA_RAM_LOCK_DEMOD__M;
+
+ int status;
+
+ *pLockStatus = 0;
+
+ status = Read16(state, SC_RA_RAM_LOCK__A, &ScRaRamLock, 0x0000);
+ if (status < 0) {
+ printk(KERN_ERR "Can't read SC_RA_RAM_LOCK__A status = %08x\n", status);
+ return status;
+ }
+
+ if (state->drxd_state != DRXD_STARTED)
+ return 0;
+
+ if ((ScRaRamLock & mpeg_lock_mask) == mpeg_lock_mask) {
+ *pLockStatus |= DRX_LOCK_MPEG;
+ CorrectSysClockDeviation(state);
+ }
+
+ if ((ScRaRamLock & fec_lock_mask) == fec_lock_mask)
+ *pLockStatus |= DRX_LOCK_FEC;
+
+ if ((ScRaRamLock & demod_lock_mask) == demod_lock_mask)
+ *pLockStatus |= DRX_LOCK_DEMOD;
+ return 0;
+}
+
+/****************************************************************************/
+
+static int SetCfgIfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
+{
+ int status;
+
+ if (cfg->outputLevel > DRXD_FE_CTRL_MAX)
+ return -1;
+
+ if (cfg->ctrlMode == AGC_CTRL_USER) {
+ do {
+ u16 FeAgRegPm1AgcWri;
+ u16 FeAgRegAgModeLop;
+
+ status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0);
+ if (status < 0)
+ break;
+ FeAgRegAgModeLop &= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M);
+ FeAgRegAgModeLop |= FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC;
+ status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0);
+ if (status < 0)
+ break;
+
+ FeAgRegPm1AgcWri = (u16) (cfg->outputLevel &
+ FE_AG_REG_PM1_AGC_WRI__M);
+ status = Write16(state, FE_AG_REG_PM1_AGC_WRI__A, FeAgRegPm1AgcWri, 0);
+ if (status < 0)
+ break;
+ } while (0);
+ } else if (cfg->ctrlMode == AGC_CTRL_AUTO) {
+ if (((cfg->maxOutputLevel) < (cfg->minOutputLevel)) ||
+ ((cfg->maxOutputLevel) > DRXD_FE_CTRL_MAX) ||
+ ((cfg->speed) > DRXD_FE_CTRL_MAX) ||
+ ((cfg->settleLevel) > DRXD_FE_CTRL_MAX)
+ )
+ return -1;
+ do {
+ u16 FeAgRegAgModeLop;
+ u16 FeAgRegEgcSetLvl;
+ u16 slope, offset;
+
+ /* == Mode == */
+
+ status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &FeAgRegAgModeLop, 0);
+ if (status < 0)
+ break;
+ FeAgRegAgModeLop &= (~FE_AG_REG_AG_MODE_LOP_MODE_4__M);
+ FeAgRegAgModeLop |=
+ FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC;
+ status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, FeAgRegAgModeLop, 0);
+ if (status < 0)
+ break;
+
+ /* == Settle level == */
+
+ FeAgRegEgcSetLvl = (u16) ((cfg->settleLevel >> 1) &
+ FE_AG_REG_EGC_SET_LVL__M);
+ status = Write16(state, FE_AG_REG_EGC_SET_LVL__A, FeAgRegEgcSetLvl, 0);
+ if (status < 0)
+ break;
+
+ /* == Min/Max == */
+
+ slope = (u16) ((cfg->maxOutputLevel -
+ cfg->minOutputLevel) / 2);
+ offset = (u16) ((cfg->maxOutputLevel +
+ cfg->minOutputLevel) / 2 - 511);
+
+ status = Write16(state, FE_AG_REG_GC1_AGC_RIC__A, slope, 0);
+ if (status < 0)
+ break;
+ status = Write16(state, FE_AG_REG_GC1_AGC_OFF__A, offset, 0);
+ if (status < 0)
+ break;
+
+ /* == Speed == */
+ {
+ const u16 maxRur = 8;
+ const u16 slowIncrDecLUT[] = { 3, 4, 4, 5, 6 };
+ const u16 fastIncrDecLUT[] = { 14, 15, 15, 16,
+ 17, 18, 18, 19,
+ 20, 21, 22, 23,
+ 24, 26, 27, 28,
+ 29, 31
+ };
+
+ u16 fineSteps = (DRXD_FE_CTRL_MAX + 1) /
+ (maxRur + 1);
+ u16 fineSpeed = (u16) (cfg->speed -
+ ((cfg->speed /
+ fineSteps) *
+ fineSteps));
+ u16 invRurCount = (u16) (cfg->speed /
+ fineSteps);
+ u16 rurCount;
+ if (invRurCount > maxRur) {
+ rurCount = 0;
+ fineSpeed += fineSteps;
+ } else {
+ rurCount = maxRur - invRurCount;
+ }
+
+ /*
+ fastInc = default *
+ (2^(fineSpeed/fineSteps))
+ => range[default...2*default>
+ slowInc = default *
+ (2^(fineSpeed/fineSteps))
+ */
+ {
+ u16 fastIncrDec =
+ fastIncrDecLUT[fineSpeed /
+ ((fineSteps /
+ (14 + 1)) + 1)];
+ u16 slowIncrDec =
+ slowIncrDecLUT[fineSpeed /
+ (fineSteps /
+ (3 + 1))];
+
+ status = Write16(state, FE_AG_REG_EGC_RUR_CNT__A, rurCount, 0);
+ if (status < 0)
+ break;
+ status = Write16(state, FE_AG_REG_EGC_FAS_INC__A, fastIncrDec, 0);
+ if (status < 0)
+ break;
+ status = Write16(state, FE_AG_REG_EGC_FAS_DEC__A, fastIncrDec, 0);
+ if (status < 0)
+ break;
+ status = Write16(state, FE_AG_REG_EGC_SLO_INC__A, slowIncrDec, 0);
+ if (status < 0)
+ break;
+ status = Write16(state, FE_AG_REG_EGC_SLO_DEC__A, slowIncrDec, 0);
+ if (status < 0)
+ break;
+ }
+ }
+ } while (0);
+
+ } else {
+ /* No OFF mode for IF control */
+ return -1;
+ }
+ return status;
+}
+
+static int SetCfgRfAgc(struct drxd_state *state, struct SCfgAgc *cfg)
+{
+ int status = 0;
+
+ if (cfg->outputLevel > DRXD_FE_CTRL_MAX)
+ return -1;
+
+ if (cfg->ctrlMode == AGC_CTRL_USER) {
+ do {
+ u16 AgModeLop = 0;
+ u16 level = (cfg->outputLevel);
+
+ if (level == DRXD_FE_CTRL_MAX)
+ level++;
+
+ status = Write16(state, FE_AG_REG_PM2_AGC_WRI__A, level, 0x0000);
+ if (status < 0)
+ break;
+
+ /*==== Mode ====*/
+
+ /* Powerdown PD2, WRI source */
+ state->m_FeAgRegAgPwd &= ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
+ state->m_FeAgRegAgPwd |=
+ FE_AG_REG_AG_PWD_PWD_PD2_DISABLE;
+ status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000);
+ if (status < 0)
+ break;
+
+ status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
+ if (status < 0)
+ break;
+ AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M |
+ FE_AG_REG_AG_MODE_LOP_MODE_E__M));
+ AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
+ FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC);
+ status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
+ if (status < 0)
+ break;
+
+ /* enable AGC2 pin */
+ {
+ u16 FeAgRegAgAgcSio = 0;
+ status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
+ if (status < 0)
+ break;
+ FeAgRegAgAgcSio &=
+ ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
+ FeAgRegAgAgcSio |=
+ FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT;
+ status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
+ if (status < 0)
+ break;
+ }
+
+ } while (0);
+ } else if (cfg->ctrlMode == AGC_CTRL_AUTO) {
+ u16 AgModeLop = 0;
+
+ do {
+ u16 level;
+ /* Automatic control */
+ /* Powerup PD2, AGC2 as output, TGC source */
+ (state->m_FeAgRegAgPwd) &=
+ ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
+ (state->m_FeAgRegAgPwd) |=
+ FE_AG_REG_AG_PWD_PWD_PD2_DISABLE;
+ status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000);
+ if (status < 0)
+ break;
+
+ status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
+ if (status < 0)
+ break;
+ AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M |
+ FE_AG_REG_AG_MODE_LOP_MODE_E__M));
+ AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
+ FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC);
+ status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
+ if (status < 0)
+ break;
+ /* Settle level */
+ level = (((cfg->settleLevel) >> 4) &
+ FE_AG_REG_TGC_SET_LVL__M);
+ status = Write16(state, FE_AG_REG_TGC_SET_LVL__A, level, 0x0000);
+ if (status < 0)
+ break;
+
+ /* Min/max: don't care */
+
+ /* Speed: TODO */
+
+ /* enable AGC2 pin */
+ {
+ u16 FeAgRegAgAgcSio = 0;
+ status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
+ if (status < 0)
+ break;
+ FeAgRegAgAgcSio &=
+ ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
+ FeAgRegAgAgcSio |=
+ FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT;
+ status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
+ if (status < 0)
+ break;
+ }
+
+ } while (0);
+ } else {
+ u16 AgModeLop = 0;
+
+ do {
+ /* No RF AGC control */
+ /* Powerdown PD2, AGC2 as output, WRI source */
+ (state->m_FeAgRegAgPwd) &=
+ ~(FE_AG_REG_AG_PWD_PWD_PD2__M);
+ (state->m_FeAgRegAgPwd) |=
+ FE_AG_REG_AG_PWD_PWD_PD2_ENABLE;
+ status = Write16(state, FE_AG_REG_AG_PWD__A, (state->m_FeAgRegAgPwd), 0x0000);
+ if (status < 0)
+ break;
+
+ status = Read16(state, FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
+ if (status < 0)
+ break;
+ AgModeLop &= (~(FE_AG_REG_AG_MODE_LOP_MODE_5__M |
+ FE_AG_REG_AG_MODE_LOP_MODE_E__M));
+ AgModeLop |= (FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC |
+ FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC);
+ status = Write16(state, FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
+ if (status < 0)
+ break;
+
+ /* set FeAgRegAgAgcSio AGC2 (RF) as input */
+ {
+ u16 FeAgRegAgAgcSio = 0;
+ status = Read16(state, FE_AG_REG_AG_AGC_SIO__A, &FeAgRegAgAgcSio, 0x0000);
+ if (status < 0)
+ break;
+ FeAgRegAgAgcSio &=
+ ~(FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M);
+ FeAgRegAgAgcSio |=
+ FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT;
+ status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, FeAgRegAgAgcSio, 0x0000);
+ if (status < 0)
+ break;
+ }
+ } while (0);
+ }
+ return status;
+}
+
+static int ReadIFAgc(struct drxd_state *state, u32 * pValue)
+{
+ int status = 0;
+
+ *pValue = 0;
+ if (state->if_agc_cfg.ctrlMode != AGC_CTRL_OFF) {
+ u16 Value;
+ status = Read16(state, FE_AG_REG_GC1_AGC_DAT__A, &Value, 0);
+ Value &= FE_AG_REG_GC1_AGC_DAT__M;
+ if (status >= 0) {
+ /* 3.3V
+ |
+ R1
+ |
+ Vin - R3 - * -- Vout
+ |
+ R2
+ |
+ GND
+ */
+ u32 R1 = state->if_agc_cfg.R1;
+ u32 R2 = state->if_agc_cfg.R2;
+ u32 R3 = state->if_agc_cfg.R3;
+
+ u32 Vmax = (3300 * R2) / (R1 + R2);
+ u32 Rpar = (R2 * R3) / (R3 + R2);
+ u32 Vmin = (3300 * Rpar) / (R1 + Rpar);
+ u32 Vout = Vmin + ((Vmax - Vmin) * Value) / 1024;
+
+ *pValue = Vout;
+ }
+ }
+ return status;
+}
+
+static int load_firmware(struct drxd_state *state, const char *fw_name)
+{
+ const struct firmware *fw;
+
+ if (request_firmware(&fw, fw_name, state->dev) < 0) {
+ printk(KERN_ERR "drxd: firmware load failure [%s]\n", fw_name);
+ return -EIO;
+ }
+
+ state->microcode = kzalloc(fw->size, GFP_KERNEL);
+ if (state->microcode == NULL) {
+ printk(KERN_ERR "drxd: firmware load failure: nomemory\n");
+ return -ENOMEM;
+ }
+
+ memcpy(state->microcode, fw->data, fw->size);
+ state->microcode_length = fw->size;
+ return 0;
+}
+
+static int DownloadMicrocode(struct drxd_state *state,
+ const u8 *pMCImage, u32 Length)
+{
+ u8 *pSrc;
+ u16 Flags;
+ u32 Address;
+ u16 nBlocks;
+ u16 BlockSize;
+ u16 BlockCRC;
+ u32 offset = 0;
+ int i, status = 0;
+
+ pSrc = (u8 *) pMCImage;
+ Flags = (pSrc[0] << 8) | pSrc[1];
+ pSrc += sizeof(u16);
+ offset += sizeof(u16);
+ nBlocks = (pSrc[0] << 8) | pSrc[1];
+ pSrc += sizeof(u16);
+ offset += sizeof(u16);
+
+ for (i = 0; i < nBlocks; i++) {
+ Address = (pSrc[0] << 24) | (pSrc[1] << 16) |
+ (pSrc[2] << 8) | pSrc[3];
+ pSrc += sizeof(u32);
+ offset += sizeof(u32);
+
+ BlockSize = ((pSrc[0] << 8) | pSrc[1]) * sizeof(u16);
+ pSrc += sizeof(u16);
+ offset += sizeof(u16);
+
+ Flags = (pSrc[0] << 8) | pSrc[1];
+ pSrc += sizeof(u16);
+ offset += sizeof(u16);
+
+ BlockCRC = (pSrc[0] << 8) | pSrc[1];
+ pSrc += sizeof(u16);
+ offset += sizeof(u16);
+
+ status = WriteBlock(state, Address, BlockSize,
+ pSrc, DRX_I2C_CLEARCRC);
+ if (status < 0)
+ break;
+ pSrc += BlockSize;
+ offset += BlockSize;
+ }
+
+ return status;
+}
+
+static int HI_Command(struct drxd_state *state, u16 cmd, u16 * pResult)
+{
+ u32 nrRetries = 0;
+ u16 waitCmd;
+ int status;
+
+ status = Write16(state, HI_RA_RAM_SRV_CMD__A, cmd, 0);
+ if (status < 0)
+ return status;
+
+ do {
+ nrRetries += 1;
+ if (nrRetries > DRXD_MAX_RETRIES) {
+ status = -1;
+ break;
+ };
+ status = Read16(state, HI_RA_RAM_SRV_CMD__A, &waitCmd, 0);
+ } while (waitCmd != 0);
+
+ if (status >= 0)
+ status = Read16(state, HI_RA_RAM_SRV_RES__A, pResult, 0);
+ return status;
+}
+
+static int HI_CfgCommand(struct drxd_state *state)
+{
+ int status = 0;
+
+ mutex_lock(&state->mutex);
+ Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0);
+ Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, state->hi_cfg_timing_div, 0);
+ Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, state->hi_cfg_bridge_delay, 0);
+ Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, state->hi_cfg_wakeup_key, 0);
+ Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, state->hi_cfg_ctrl, 0);
+
+ Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, HI_RA_RAM_SRV_RST_KEY_ACT, 0);
+
+ if ((state->hi_cfg_ctrl & HI_RA_RAM_SRV_CFG_ACT_PWD_EXE) ==
+ HI_RA_RAM_SRV_CFG_ACT_PWD_EXE)
+ status = Write16(state, HI_RA_RAM_SRV_CMD__A,
+ HI_RA_RAM_SRV_CMD_CONFIG, 0);
+ else
+ status = HI_Command(state, HI_RA_RAM_SRV_CMD_CONFIG, 0);
+ mutex_unlock(&state->mutex);
+ return status;
+}
+
+static int InitHI(struct drxd_state *state)
+{
+ state->hi_cfg_wakeup_key = (state->chip_adr);
+ /* port/bridge/power down ctrl */
+ state->hi_cfg_ctrl = HI_RA_RAM_SRV_CFG_ACT_SLV0_ON;
+ return HI_CfgCommand(state);
+}
+
+static int HI_ResetCommand(struct drxd_state *state)
+{
+ int status;
+
+ mutex_lock(&state->mutex);
+ status = Write16(state, HI_RA_RAM_SRV_RST_KEY__A,
+ HI_RA_RAM_SRV_RST_KEY_ACT, 0);
+ if (status == 0)
+ status = HI_Command(state, HI_RA_RAM_SRV_CMD_RESET, 0);
+ mutex_unlock(&state->mutex);
+ msleep(1);
+ return status;
+}
+
+static int DRX_ConfigureI2CBridge(struct drxd_state *state, int bEnableBridge)
+{
+ state->hi_cfg_ctrl &= (~HI_RA_RAM_SRV_CFG_ACT_BRD__M);
+ if (bEnableBridge)
+ state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_ON;
+ else
+ state->hi_cfg_ctrl |= HI_RA_RAM_SRV_CFG_ACT_BRD_OFF;
+
+ return HI_CfgCommand(state);
+}
+
+#define HI_TR_WRITE 0x9
+#define HI_TR_READ 0xA
+#define HI_TR_READ_WRITE 0xB
+#define HI_TR_BROADCAST 0x4
+
+#if 0
+static int AtomicReadBlock(struct drxd_state *state,
+ u32 Addr, u16 DataSize, u8 *pData, u8 Flags)
+{
+ int status;
+ int i = 0;
+
+ /* Parameter check */
+ if ((!pData) || ((DataSize & 1) != 0))
+ return -1;
+
+ mutex_lock(&state->mutex);
+
+ do {
+ /* Instruct HI to read n bytes */
+ /* TODO use proper names forthese egisters */
+ status = Write16(state, HI_RA_RAM_SRV_CFG_KEY__A, (HI_TR_FUNC_ADDR & 0xFFFF), 0);
+ if (status < 0)
+ break;
+ status = Write16(state, HI_RA_RAM_SRV_CFG_DIV__A, (u16) (Addr >> 16), 0);
+ if (status < 0)
+ break;
+ status = Write16(state, HI_RA_RAM_SRV_CFG_BDL__A, (u16) (Addr & 0xFFFF), 0);
+ if (status < 0)
+ break;
+ status = Write16(state, HI_RA_RAM_SRV_CFG_WUP__A, (u16) ((DataSize / 2) - 1), 0);
+ if (status < 0)
+ break;
+ status = Write16(state, HI_RA_RAM_SRV_CFG_ACT__A, HI_TR_READ, 0);
+ if (status < 0)
+ break;
+
+ status = HI_Command(state, HI_RA_RAM_SRV_CMD_EXECUTE, 0);
+ if (status < 0)
+ break;
+
+ } while (0);
+
+ if (status >= 0) {
+ for (i = 0; i < (DataSize / 2); i += 1) {
+ u16 word;
+
+ status = Read16(state, (HI_RA_RAM_USR_BEGIN__A + i),
+ &word, 0);
+ if (status < 0)
+ break;
+ pData[2 * i] = (u8) (word & 0xFF);
+ pData[(2 * i) + 1] = (u8) (word >> 8);
+ }
+ }
+ mutex_unlock(&state->mutex);
+ return status;
+}
+
+static int AtomicReadReg32(struct drxd_state *state,
+ u32 Addr, u32 *pData, u8 Flags)
+{
+ u8 buf[sizeof(u32)];
+ int status;
+
+ if (!pData)
+ return -1;
+ status = AtomicReadBlock(state, Addr, sizeof(u32), buf, Flags);
+ *pData = (((u32) buf[0]) << 0) +
+ (((u32) buf[1]) << 8) +
+ (((u32) buf[2]) << 16) + (((u32) buf[3]) << 24);
+ return status;
+}
+#endif
+
+static int StopAllProcessors(struct drxd_state *state)
+{
+ return Write16(state, HI_COMM_EXEC__A,
+ SC_COMM_EXEC_CTL_STOP, DRX_I2C_BROADCAST);
+}
+
+static int EnableAndResetMB(struct drxd_state *state)
+{
+ if (state->type_A) {
+ /* disable? monitor bus observe @ EC_OC */
+ Write16(state, EC_OC_REG_OC_MON_SIO__A, 0x0000, 0x0000);
+ }
+
+ /* do inverse broadcast, followed by explicit write to HI */
+ Write16(state, HI_COMM_MB__A, 0x0000, DRX_I2C_BROADCAST);
+ Write16(state, HI_COMM_MB__A, 0x0000, 0x0000);
+ return 0;
+}
+
+static int InitCC(struct drxd_state *state)
+{
+ if (state->osc_clock_freq == 0 ||
+ state->osc_clock_freq > 20000 ||
+ (state->osc_clock_freq % 4000) != 0) {
+ printk(KERN_ERR "invalid osc frequency %d\n", state->osc_clock_freq);
+ return -1;
+ }
+
+ Write16(state, CC_REG_OSC_MODE__A, CC_REG_OSC_MODE_M20, 0);
+ Write16(state, CC_REG_PLL_MODE__A, CC_REG_PLL_MODE_BYPASS_PLL |
+ CC_REG_PLL_MODE_PUMP_CUR_12, 0);
+ Write16(state, CC_REG_REF_DIVIDE__A, state->osc_clock_freq / 4000, 0);
+ Write16(state, CC_REG_PWD_MODE__A, CC_REG_PWD_MODE_DOWN_PLL, 0);
+ Write16(state, CC_REG_UPDATE__A, CC_REG_UPDATE_KEY, 0);
+
+ return 0;
+}
+
+static int ResetECOD(struct drxd_state *state)
+{
+ int status = 0;
+
+ if (state->type_A)
+ status = Write16(state, EC_OD_REG_SYNC__A, 0x0664, 0);
+ else
+ status = Write16(state, B_EC_OD_REG_SYNC__A, 0x0664, 0);
+
+ if (!(status < 0))
+ status = WriteTable(state, state->m_ResetECRAM);
+ if (!(status < 0))
+ status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0001, 0);
+ return status;
+}
+
+/* Configure PGA switch */
+
+static int SetCfgPga(struct drxd_state *state, int pgaSwitch)
+{
+ int status;
+ u16 AgModeLop = 0;
+ u16 AgModeHip = 0;
+ do {
+ if (pgaSwitch) {
+ /* PGA on */
+ /* fine gain */
+ status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
+ if (status < 0)
+ break;
+ AgModeLop &= (~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M));
+ AgModeLop |= B_FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC;
+ status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
+ if (status < 0)
+ break;
+
+ /* coarse gain */
+ status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000);
+ if (status < 0)
+ break;
+ AgModeHip &= (~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M));
+ AgModeHip |= B_FE_AG_REG_AG_MODE_HIP_MODE_J_DYNAMIC;
+ status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000);
+ if (status < 0)
+ break;
+
+ /* enable fine and coarse gain, enable AAF,
+ no ext resistor */
+ status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN, 0x0000);
+ if (status < 0)
+ break;
+ } else {
+ /* PGA off, bypass */
+
+ /* fine gain */
+ status = Read16(state, B_FE_AG_REG_AG_MODE_LOP__A, &AgModeLop, 0x0000);
+ if (status < 0)
+ break;
+ AgModeLop &= (~(B_FE_AG_REG_AG_MODE_LOP_MODE_C__M));
+ AgModeLop |= B_FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC;
+ status = Write16(state, B_FE_AG_REG_AG_MODE_LOP__A, AgModeLop, 0x0000);
+ if (status < 0)
+ break;
+
+ /* coarse gain */
+ status = Read16(state, B_FE_AG_REG_AG_MODE_HIP__A, &AgModeHip, 0x0000);
+ if (status < 0)
+ break;
+ AgModeHip &= (~(B_FE_AG_REG_AG_MODE_HIP_MODE_J__M));
+ AgModeHip |= B_FE_AG_REG_AG_MODE_HIP_MODE_J_STATIC;
+ status = Write16(state, B_FE_AG_REG_AG_MODE_HIP__A, AgModeHip, 0x0000);
+ if (status < 0)
+ break;
+
+ /* disable fine and coarse gain, enable AAF,
+ no ext resistor */
+ status = Write16(state, B_FE_AG_REG_AG_PGA_MODE__A, B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN, 0x0000);
+ if (status < 0)
+ break;
+ }
+ } while (0);
+ return status;
+}
+
+static int InitFE(struct drxd_state *state)
+{
+ int status;
+
+ do {
+ status = WriteTable(state, state->m_InitFE_1);
+ if (status < 0)
+ break;
+
+ if (state->type_A) {
+ status = Write16(state, FE_AG_REG_AG_PGA_MODE__A,
+ FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN,
+ 0);
+ } else {
+ if (state->PGA)
+ status = SetCfgPga(state, 0);
+ else
+ status =
+ Write16(state, B_FE_AG_REG_AG_PGA_MODE__A,
+ B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN,
+ 0);
+ }
+
+ if (status < 0)
+ break;
+ status = Write16(state, FE_AG_REG_AG_AGC_SIO__A, state->m_FeAgRegAgAgcSio, 0x0000);
+ if (status < 0)
+ break;
+ status = Write16(state, FE_AG_REG_AG_PWD__A, state->m_FeAgRegAgPwd, 0x0000);
+ if (status < 0)
+ break;
+
+ status = WriteTable(state, state->m_InitFE_2);
+ if (status < 0)
+ break;
+
+ } while (0);
+
+ return status;
+}
+
+static int InitFT(struct drxd_state *state)
+{
+ /*
+ norm OFFSET, MB says =2 voor 8K en =3 voor 2K waarschijnlijk
+ SC stuff
+ */
+ return Write16(state, FT_REG_COMM_EXEC__A, 0x0001, 0x0000);
+}
+
+static int SC_WaitForReady(struct drxd_state *state)
+{
+ u16 curCmd;
+ int i;
+
+ for (i = 0; i < DRXD_MAX_RETRIES; i += 1) {
+ int status = Read16(state, SC_RA_RAM_CMD__A, &curCmd, 0);
+ if (status == 0 || curCmd == 0)
+ return status;
+ }
+ return -1;
+}
+
+static int SC_SendCommand(struct drxd_state *state, u16 cmd)
+{
+ int status = 0;
+ u16 errCode;
+
+ Write16(state, SC_RA_RAM_CMD__A, cmd, 0);
+ SC_WaitForReady(state);
+
+ Read16(state, SC_RA_RAM_CMD_ADDR__A, &errCode, 0);
+
+ if (errCode == 0xFFFF) {
+ printk(KERN_ERR "Command Error\n");
+ status = -1;
+ }
+
+ return status;
+}
+
+static int SC_ProcStartCommand(struct drxd_state *state,
+ u16 subCmd, u16 param0, u16 param1)
+{
+ int status = 0;
+ u16 scExec;
+
+ mutex_lock(&state->mutex);
+ do {
+ Read16(state, SC_COMM_EXEC__A, &scExec, 0);
+ if (scExec != 1) {
+ status = -1;
+ break;
+ }
+ SC_WaitForReady(state);
+ Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0);
+ Write16(state, SC_RA_RAM_PARAM1__A, param1, 0);
+ Write16(state, SC_RA_RAM_PARAM0__A, param0, 0);
+
+ SC_SendCommand(state, SC_RA_RAM_CMD_PROC_START);
+ } while (0);
+ mutex_unlock(&state->mutex);
+ return status;
+}
+
+static int SC_SetPrefParamCommand(struct drxd_state *state,
+ u16 subCmd, u16 param0, u16 param1)
+{
+ int status;
+
+ mutex_lock(&state->mutex);
+ do {
+ status = SC_WaitForReady(state);
+ if (status < 0)
+ break;
+ status = Write16(state, SC_RA_RAM_CMD_ADDR__A, subCmd, 0);
+ if (status < 0)
+ break;
+ status = Write16(state, SC_RA_RAM_PARAM1__A, param1, 0);
+ if (status < 0)
+ break;
+ status = Write16(state, SC_RA_RAM_PARAM0__A, param0, 0);
+ if (status < 0)
+ break;
+
+ status = SC_SendCommand(state, SC_RA_RAM_CMD_SET_PREF_PARAM);
+ if (status < 0)
+ break;
+ } while (0);
+ mutex_unlock(&state->mutex);
+ return status;
+}
+
+#if 0
+static int SC_GetOpParamCommand(struct drxd_state *state, u16 * result)
+{
+ int status = 0;
+
+ mutex_lock(&state->mutex);
+ do {
+ status = SC_WaitForReady(state);
+ if (status < 0)
+ break;
+ status = SC_SendCommand(state, SC_RA_RAM_CMD_GET_OP_PARAM);
+ if (status < 0)
+ break;
+ status = Read16(state, SC_RA_RAM_PARAM0__A, result, 0);
+ if (status < 0)
+ break;
+ } while (0);
+ mutex_unlock(&state->mutex);
+ return status;
+}
+#endif
+
+static int ConfigureMPEGOutput(struct drxd_state *state, int bEnableOutput)
+{
+ int status;
+
+ do {
+ u16 EcOcRegIprInvMpg = 0;
+ u16 EcOcRegOcModeLop = 0;
+ u16 EcOcRegOcModeHip = 0;
+ u16 EcOcRegOcMpgSio = 0;
+
+ /*CHK_ERROR(Read16(state, EC_OC_REG_OC_MODE_LOP__A, &EcOcRegOcModeLop, 0)); */
+
+ if (state->operation_mode == OM_DVBT_Diversity_Front) {
+ if (bEnableOutput) {
+ EcOcRegOcModeHip |=
+ B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR;
+ } else
+ EcOcRegOcMpgSio |= EC_OC_REG_OC_MPG_SIO__M;
+ EcOcRegOcModeLop |=
+ EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE;
+ } else {
+ EcOcRegOcModeLop = state->m_EcOcRegOcModeLop;
+
+ if (bEnableOutput)
+ EcOcRegOcMpgSio &= (~(EC_OC_REG_OC_MPG_SIO__M));
+ else
+ EcOcRegOcMpgSio |= EC_OC_REG_OC_MPG_SIO__M;
+
+ /* Don't Insert RS Byte */
+ if (state->insert_rs_byte) {
+ EcOcRegOcModeLop &=
+ (~(EC_OC_REG_OC_MODE_LOP_PAR_ENA__M));
+ EcOcRegOcModeHip &=
+ (~EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M);
+ EcOcRegOcModeHip |=
+ EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_ENABLE;
+ } else {
+ EcOcRegOcModeLop |=
+ EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE;
+ EcOcRegOcModeHip &=
+ (~EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M);
+ EcOcRegOcModeHip |=
+ EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_DISABLE;
+ }
+
+ /* Mode = Parallel */
+ if (state->enable_parallel)
+ EcOcRegOcModeLop &=
+ (~(EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__M));
+ else
+ EcOcRegOcModeLop |=
+ EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_SERIAL;
+ }
+ /* Invert Data */
+ /* EcOcRegIprInvMpg |= 0x00FF; */
+ EcOcRegIprInvMpg &= (~(0x00FF));
+
+ /* Invert Error ( we don't use the pin ) */
+ /* EcOcRegIprInvMpg |= 0x0100; */
+ EcOcRegIprInvMpg &= (~(0x0100));
+
+ /* Invert Start ( we don't use the pin ) */
+ /* EcOcRegIprInvMpg |= 0x0200; */
+ EcOcRegIprInvMpg &= (~(0x0200));
+
+ /* Invert Valid ( we don't use the pin ) */
+ /* EcOcRegIprInvMpg |= 0x0400; */
+ EcOcRegIprInvMpg &= (~(0x0400));
+
+ /* Invert Clock */
+ /* EcOcRegIprInvMpg |= 0x0800; */
+ EcOcRegIprInvMpg &= (~(0x0800));
+
+ /* EcOcRegOcModeLop =0x05; */
+ status = Write16(state, EC_OC_REG_IPR_INV_MPG__A, EcOcRegIprInvMpg, 0);
+ if (status < 0)
+ break;
+ status = Write16(state, EC_OC_REG_OC_MODE_LOP__A, EcOcRegOcModeLop, 0);
+ if (status < 0)
+ break;
+ status = Write16(state, EC_OC_REG_OC_MODE_HIP__A, EcOcRegOcModeHip, 0x0000);
+ if (status < 0)
+ break;
+ status = Write16(state, EC_OC_REG_OC_MPG_SIO__A, EcOcRegOcMpgSio, 0);
+ if (status < 0)
+ break;
+ } while (0);
+ return status;
+}
+
+static int SetDeviceTypeId(struct drxd_state *state)
+{
+ int status = 0;
+ u16 deviceId = 0;
+
+ do {
+ status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0);
+ if (status < 0)
+ break;
+ /* TODO: why twice? */
+ status = Read16(state, CC_REG_JTAGID_L__A, &deviceId, 0);
+ if (status < 0)
+ break;
+ printk(KERN_INFO "drxd: deviceId = %04x\n", deviceId);
+
+ state->type_A = 0;
+ state->PGA = 0;
+ state->diversity = 0;
+ if (deviceId == 0) { /* on A2 only 3975 available */
+ state->type_A = 1;
+ printk(KERN_INFO "DRX3975D-A2\n");
+ } else {
+ deviceId >>= 12;
+ printk(KERN_INFO "DRX397%dD-B1\n", deviceId);
+ switch (deviceId) {
+ case 4:
+ state->diversity = 1;
+ case 3:
+ case 7:
+ state->PGA = 1;
+ break;
+ case 6:
+ state->diversity = 1;
+ case 5:
+ case 8:
+ break;
+ default:
+ status = -1;
+ break;
+ }
+ }
+ } while (0);
+
+ if (status < 0)
+ return status;
+
+ /* Init Table selection */
+ state->m_InitAtomicRead = DRXD_InitAtomicRead;
+ state->m_InitSC = DRXD_InitSC;
+ state->m_ResetECRAM = DRXD_ResetECRAM;
+ if (state->type_A) {
+ state->m_ResetCEFR = DRXD_ResetCEFR;
+ state->m_InitFE_1 = DRXD_InitFEA2_1;
+ state->m_InitFE_2 = DRXD_InitFEA2_2;
+ state->m_InitCP = DRXD_InitCPA2;
+ state->m_InitCE = DRXD_InitCEA2;
+ state->m_InitEQ = DRXD_InitEQA2;
+ state->m_InitEC = DRXD_InitECA2;
+ if (load_firmware(state, DRX_FW_FILENAME_A2))
+ return -EIO;
+ } else {
+ state->m_ResetCEFR = NULL;
+ state->m_InitFE_1 = DRXD_InitFEB1_1;
+ state->m_InitFE_2 = DRXD_InitFEB1_2;
+ state->m_InitCP = DRXD_InitCPB1;
+ state->m_InitCE = DRXD_InitCEB1;
+ state->m_InitEQ = DRXD_InitEQB1;
+ state->m_InitEC = DRXD_InitECB1;
+ if (load_firmware(state, DRX_FW_FILENAME_B1))
+ return -EIO;
+ }
+ if (state->diversity) {
+ state->m_InitDiversityFront = DRXD_InitDiversityFront;
+ state->m_InitDiversityEnd = DRXD_InitDiversityEnd;
+ state->m_DisableDiversity = DRXD_DisableDiversity;
+ state->m_StartDiversityFront = DRXD_StartDiversityFront;
+ state->m_StartDiversityEnd = DRXD_StartDiversityEnd;
+ state->m_DiversityDelay8MHZ = DRXD_DiversityDelay8MHZ;
+ state->m_DiversityDelay6MHZ = DRXD_DiversityDelay6MHZ;
+ } else {
+ state->m_InitDiversityFront = NULL;
+ state->m_InitDiversityEnd = NULL;
+ state->m_DisableDiversity = NULL;
+ state->m_StartDiversityFront = NULL;
+ state->m_StartDiversityEnd = NULL;
+ state->m_DiversityDelay8MHZ = NULL;
+ state->m_DiversityDelay6MHZ = NULL;
+ }
+
+ return status;
+}
+
+static int CorrectSysClockDeviation(struct drxd_state *state)
+{
+ int status;
+ s32 incr = 0;
+ s32 nomincr = 0;
+ u32 bandwidth = 0;
+ u32 sysClockInHz = 0;
+ u32 sysClockFreq = 0; /* in kHz */
+ s16 oscClockDeviation;
+ s16 Diff;
+
+ do {
+ /* Retrieve bandwidth and incr, sanity check */
+
+ /* These accesses should be AtomicReadReg32, but that
+ causes trouble (at least for diversity */
+ status = Read32(state, LC_RA_RAM_IFINCR_NOM_L__A, ((u32 *) &nomincr), 0);
+ if (status < 0)
+ break;
+ status = Read32(state, FE_IF_REG_INCR0__A, (u32 *) &incr, 0);
+ if (status < 0)
+ break;
+
+ if (state->type_A) {
+ if ((nomincr - incr < -500) || (nomincr - incr > 500))
+ break;
+ } else {
+ if ((nomincr - incr < -2000) || (nomincr - incr > 2000))
+ break;
+ }
+
+ switch (state->param.u.ofdm.bandwidth) {
+ case BANDWIDTH_8_MHZ:
+ bandwidth = DRXD_BANDWIDTH_8MHZ_IN_HZ;
+ break;
+ case BANDWIDTH_7_MHZ:
+ bandwidth = DRXD_BANDWIDTH_7MHZ_IN_HZ;
+ break;
+ case BANDWIDTH_6_MHZ:
+ bandwidth = DRXD_BANDWIDTH_6MHZ_IN_HZ;
+ break;
+ default:
+ return -1;
+ break;
+ }
+
+ /* Compute new sysclock value
+ sysClockFreq = (((incr + 2^23)*bandwidth)/2^21)/1000 */
+ incr += (1 << 23);
+ sysClockInHz = MulDiv32(incr, bandwidth, 1 << 21);
+ sysClockFreq = (u32) (sysClockInHz / 1000);
+ /* rounding */
+ if ((sysClockInHz % 1000) > 500)
+ sysClockFreq++;
+
+ /* Compute clock deviation in ppm */
+ oscClockDeviation = (u16) ((((s32) (sysClockFreq) -
+ (s32)
+ (state->expected_sys_clock_freq)) *
+ 1000000L) /
+ (s32)
+ (state->expected_sys_clock_freq));
+
+ Diff = oscClockDeviation - state->osc_clock_deviation;
+ /*printk(KERN_INFO "sysclockdiff=%d\n", Diff); */
+ if (Diff >= -200 && Diff <= 200) {
+ state->sys_clock_freq = (u16) sysClockFreq;
+ if (oscClockDeviation != state->osc_clock_deviation) {
+ if (state->config.osc_deviation) {
+ state->config.osc_deviation(state->priv,
+ oscClockDeviation,
+ 1);
+ state->osc_clock_deviation =
+ oscClockDeviation;
+ }
+ }
+ /* switch OFF SRMM scan in SC */
+ status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DONT_SCAN, 0);
+ if (status < 0)
+ break;
+ /* overrule FE_IF internal value for
+ proper re-locking */
+ status = Write16(state, SC_RA_RAM_IF_SAVE__AX, state->current_fe_if_incr, 0);
+ if (status < 0)
+ break;
+ state->cscd_state = CSCD_SAVED;
+ }
+ } while (0);
+
+ return status;
+}
+
+static int DRX_Stop(struct drxd_state *state)
+{
+ int status;
+
+ if (state->drxd_state != DRXD_STARTED)
+ return 0;
+
+ do {
+ if (state->cscd_state != CSCD_SAVED) {
+ u32 lock;
+ status = DRX_GetLockStatus(state, &lock);
+ if (status < 0)
+ break;
+ }
+
+ status = StopOC(state);
+ if (status < 0)
+ break;
+
+ state->drxd_state = DRXD_STOPPED;
+
+ status = ConfigureMPEGOutput(state, 0);
+ if (status < 0)
+ break;
+
+ if (state->type_A) {
+ /* Stop relevant processors off the device */
+ status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0x0000);
+ if (status < 0)
+ break;
+
+ status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
+ if (status < 0)
+ break;
+ status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
+ if (status < 0)
+ break;
+ } else {
+ /* Stop all processors except HI & CC & FE */
+ status = Write16(state, B_SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
+ if (status < 0)
+ break;
+ status = Write16(state, B_LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
+ if (status < 0)
+ break;
+ status = Write16(state, B_FT_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
+ if (status < 0)
+ break;
+ status = Write16(state, B_CP_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
+ if (status < 0)
+ break;
+ status = Write16(state, B_CE_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
+ if (status < 0)
+ break;
+ status = Write16(state, B_EQ_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
+ if (status < 0)
+ break;
+ status = Write16(state, EC_OD_REG_COMM_EXEC__A, 0x0000, 0);
+ if (status < 0)
+ break;
+ }
+
+ } while (0);
+ return status;
+}
+
+int SetOperationMode(struct drxd_state *state, int oMode)
+{
+ int status;
+
+ do {
+ if (state->drxd_state != DRXD_STOPPED) {
+ status = -1;
+ break;
+ }
+
+ if (oMode == state->operation_mode) {
+ status = 0;
+ break;
+ }
+
+ if (oMode != OM_Default && !state->diversity) {
+ status = -1;
+ break;
+ }
+
+ switch (oMode) {
+ case OM_DVBT_Diversity_Front:
+ status = WriteTable(state, state->m_InitDiversityFront);
+ break;
+ case OM_DVBT_Diversity_End:
+ status = WriteTable(state, state->m_InitDiversityEnd);
+ break;
+ case OM_Default:
+ /* We need to check how to
+ get DRXD out of diversity */
+ default:
+ status = WriteTable(state, state->m_DisableDiversity);
+ break;
+ }
+ } while (0);
+
+ if (!status)
+ state->operation_mode = oMode;
+ return status;
+}
+
+static int StartDiversity(struct drxd_state *state)
+{
+ int status = 0;
+ u16 rcControl;
+
+ do {
+ if (state->operation_mode == OM_DVBT_Diversity_Front) {
+ status = WriteTable(state, state->m_StartDiversityFront);
+ if (status < 0)
+ break;
+ } else if (state->operation_mode == OM_DVBT_Diversity_End) {
+ status = WriteTable(state, state->m_StartDiversityEnd);
+ if (status < 0)
+ break;
+ if (state->param.u.ofdm.bandwidth == BANDWIDTH_8_MHZ) {
+ status = WriteTable(state, state->m_DiversityDelay8MHZ);
+ if (status < 0)
+ break;
+ } else {
+ status = WriteTable(state, state->m_DiversityDelay6MHZ);
+ if (status < 0)
+ break;
+ }
+
+ status = Read16(state, B_EQ_REG_RC_SEL_CAR__A, &rcControl, 0);
+ if (status < 0)
+ break;
+ rcControl &= ~(B_EQ_REG_RC_SEL_CAR_FFTMODE__M);
+ rcControl |= B_EQ_REG_RC_SEL_CAR_DIV_ON |
+ /* combining enabled */
+ B_EQ_REG_RC_SEL_CAR_MEAS_A_CC |
+ B_EQ_REG_RC_SEL_CAR_PASS_A_CC |
+ B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC;
+ status = Write16(state, B_EQ_REG_RC_SEL_CAR__A, rcControl, 0);
+ if (status < 0)
+ break;
+ }
+ } while (0);
+ return status;
+}
+
+static int SetFrequencyShift(struct drxd_state *state,
+ u32 offsetFreq, int channelMirrored)
+{
+ int negativeShift = (state->tuner_mirrors == channelMirrored);
+
+ /* Handle all mirroring
+ *
+ * Note: ADC mirroring (aliasing) is implictly handled by limiting
+ * feFsRegAddInc to 28 bits below
+ * (if the result before masking is more than 28 bits, this means
+ * that the ADC is mirroring.
+ * The masking is in fact the aliasing of the ADC)
+ *
+ */
+
+ /* Compute register value, unsigned computation */
+ state->fe_fs_add_incr = MulDiv32(state->intermediate_freq +
+ offsetFreq,
+ 1 << 28, state->sys_clock_freq);
+ /* Remove integer part */
+ state->fe_fs_add_incr &= 0x0FFFFFFFL;
+ if (negativeShift)
+ state->fe_fs_add_incr = ((1 << 28) - state->fe_fs_add_incr);
+
+ /* Save the frequency shift without tunerOffset compensation
+ for CtrlGetChannel. */
+ state->org_fe_fs_add_incr = MulDiv32(state->intermediate_freq,
+ 1 << 28, state->sys_clock_freq);
+ /* Remove integer part */
+ state->org_fe_fs_add_incr &= 0x0FFFFFFFL;
+ if (negativeShift)
+ state->org_fe_fs_add_incr = ((1L << 28) -
+ state->org_fe_fs_add_incr);
+
+ return Write32(state, FE_FS_REG_ADD_INC_LOP__A,
+ state->fe_fs_add_incr, 0);
+}
+
+static int SetCfgNoiseCalibration(struct drxd_state *state,
+ struct SNoiseCal *noiseCal)
+{
+ u16 beOptEna;
+ int status = 0;
+
+ do {
+ status = Read16(state, SC_RA_RAM_BE_OPT_ENA__A, &beOptEna, 0);
+ if (status < 0)
+ break;
+ if (noiseCal->cpOpt) {
+ beOptEna |= (1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT);
+ } else {
+ beOptEna &= ~(1 << SC_RA_RAM_BE_OPT_ENA_CP_OPT);
+ status = Write16(state, CP_REG_AC_NEXP_OFFS__A, noiseCal->cpNexpOfs, 0);
+ if (status < 0)
+ break;
+ }
+ status = Write16(state, SC_RA_RAM_BE_OPT_ENA__A, beOptEna, 0);
+ if (status < 0)
+ break;
+
+ if (!state->type_A) {
+ status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_2K__A, noiseCal->tdCal2k, 0);
+ if (status < 0)
+ break;
+ status = Write16(state, B_SC_RA_RAM_CO_TD_CAL_8K__A, noiseCal->tdCal8k, 0);
+ if (status < 0)
+ break;
+ }
+ } while (0);
+
+ return status;
+}
+
+static int DRX_Start(struct drxd_state *state, s32 off)
+{
+ struct dvb_ofdm_parameters *p = &state->param.u.ofdm;
+ int status;
+
+ u16 transmissionParams = 0;
+ u16 operationMode = 0;
+ u16 qpskTdTpsPwr = 0;
+ u16 qam16TdTpsPwr = 0;
+ u16 qam64TdTpsPwr = 0;
+ u32 feIfIncr = 0;
+ u32 bandwidth = 0;
+ int mirrorFreqSpect;
+
+ u16 qpskSnCeGain = 0;
+ u16 qam16SnCeGain = 0;
+ u16 qam64SnCeGain = 0;
+ u16 qpskIsGainMan = 0;
+ u16 qam16IsGainMan = 0;
+ u16 qam64IsGainMan = 0;
+ u16 qpskIsGainExp = 0;
+ u16 qam16IsGainExp = 0;
+ u16 qam64IsGainExp = 0;
+ u16 bandwidthParam = 0;
+
+ if (off < 0)
+ off = (off - 500) / 1000;
+ else
+ off = (off + 500) / 1000;
+
+ do {
+ if (state->drxd_state != DRXD_STOPPED)
+ return -1;
+ status = ResetECOD(state);
+ if (status < 0)
+ break;
+ if (state->type_A) {
+ status = InitSC(state);
+ if (status < 0)
+ break;
+ } else {
+ status = InitFT(state);
+ if (status < 0)
+ break;
+ status = InitCP(state);
+ if (status < 0)
+ break;
+ status = InitCE(state);
+ if (status < 0)
+ break;
+ status = InitEQ(state);
+ if (status < 0)
+ break;
+ status = InitSC(state);
+ if (status < 0)
+ break;
+ }
+
+ /* Restore current IF & RF AGC settings */
+
+ status = SetCfgIfAgc(state, &state->if_agc_cfg);
+ if (status < 0)
+ break;
+ status = SetCfgRfAgc(state, &state->rf_agc_cfg);
+ if (status < 0)
+ break;
+
+ mirrorFreqSpect = (state->param.inversion == INVERSION_ON);
+
+ switch (p->transmission_mode) {
+ default: /* Not set, detect it automatically */
+ operationMode |= SC_RA_RAM_OP_AUTO_MODE__M;
+ /* fall through , try first guess DRX_FFTMODE_8K */
+ case TRANSMISSION_MODE_8K:
+ transmissionParams |= SC_RA_RAM_OP_PARAM_MODE_8K;
+ if (state->type_A) {
+ status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_8K, 0x0000);
+ if (status < 0)
+ break;
+ qpskSnCeGain = 99;
+ qam16SnCeGain = 83;
+ qam64SnCeGain = 67;
+ }
+ break;
+ case TRANSMISSION_MODE_2K:
+ transmissionParams |= SC_RA_RAM_OP_PARAM_MODE_2K;
+ if (state->type_A) {
+ status = Write16(state, EC_SB_REG_TR_MODE__A, EC_SB_REG_TR_MODE_2K, 0x0000);
+ if (status < 0)
+ break;
+ qpskSnCeGain = 97;
+ qam16SnCeGain = 71;
+ qam64SnCeGain = 65;
+ }
+ break;
+ }
+
+ switch (p->guard_interval) {
+ case GUARD_INTERVAL_1_4:
+ transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_4;
+ break;
+ case GUARD_INTERVAL_1_8:
+ transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_8;
+ break;
+ case GUARD_INTERVAL_1_16:
+ transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_16;
+ break;
+ case GUARD_INTERVAL_1_32:
+ transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_32;
+ break;
+ default: /* Not set, detect it automatically */
+ operationMode |= SC_RA_RAM_OP_AUTO_GUARD__M;
+ /* try first guess 1/4 */
+ transmissionParams |= SC_RA_RAM_OP_PARAM_GUARD_4;
+ break;
+ }
+
+ switch (p->hierarchy_information) {
+ case HIERARCHY_1:
+ transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A1;
+ if (state->type_A) {
+ status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0001, 0x0000);
+ if (status < 0)
+ break;
+ status = Write16(state, EC_SB_REG_ALPHA__A, 0x0001, 0x0000);
+ if (status < 0)
+ break;
+
+ qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
+ qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA1;
+ qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA1;
+
+ qpskIsGainMan =
+ SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE;
+ qam16IsGainMan =
+ SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE;
+ qam64IsGainMan =
+ SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE;
+
+ qpskIsGainExp =
+ SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE;
+ qam16IsGainExp =
+ SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE;
+ qam64IsGainExp =
+ SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE;
+ }
+ break;
+
+ case HIERARCHY_2:
+ transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A2;
+ if (state->type_A) {
+ status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0002, 0x0000);
+ if (status < 0)
+ break;
+ status = Write16(state, EC_SB_REG_ALPHA__A, 0x0002, 0x0000);
+ if (status < 0)
+ break;
+
+ qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
+ qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA2;
+ qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA2;
+
+ qpskIsGainMan =
+ SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE;
+ qam16IsGainMan =
+ SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE;
+ qam64IsGainMan =
+ SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE;
+
+ qpskIsGainExp =
+ SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE;
+ qam16IsGainExp =
+ SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE;
+ qam64IsGainExp =
+ SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE;
+ }
+ break;
+ case HIERARCHY_4:
+ transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_A4;
+ if (state->type_A) {
+ status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0003, 0x0000);
+ if (status < 0)
+ break;
+ status = Write16(state, EC_SB_REG_ALPHA__A, 0x0003, 0x0000);
+ if (status < 0)
+ break;
+
+ qpskTdTpsPwr = EQ_TD_TPS_PWR_UNKNOWN;
+ qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHA4;
+ qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHA4;
+
+ qpskIsGainMan =
+ SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE;
+ qam16IsGainMan =
+ SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE;
+ qam64IsGainMan =
+ SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE;
+
+ qpskIsGainExp =
+ SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE;
+ qam16IsGainExp =
+ SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE;
+ qam64IsGainExp =
+ SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE;
+ }
+ break;
+ case HIERARCHY_AUTO:
+ default:
+ /* Not set, detect it automatically, start with none */
+ operationMode |= SC_RA_RAM_OP_AUTO_HIER__M;
+ transmissionParams |= SC_RA_RAM_OP_PARAM_HIER_NO;
+ if (state->type_A) {
+ status = Write16(state, EQ_REG_OT_ALPHA__A, 0x0000, 0x0000);
+ if (status < 0)
+ break;
+ status = Write16(state, EC_SB_REG_ALPHA__A, 0x0000, 0x0000);
+ if (status < 0)
+ break;
+
+ qpskTdTpsPwr = EQ_TD_TPS_PWR_QPSK;
+ qam16TdTpsPwr = EQ_TD_TPS_PWR_QAM16_ALPHAN;
+ qam64TdTpsPwr = EQ_TD_TPS_PWR_QAM64_ALPHAN;
+
+ qpskIsGainMan =
+ SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE;
+ qam16IsGainMan =
+ SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE;
+ qam64IsGainMan =
+ SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE;
+
+ qpskIsGainExp =
+ SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE;
+ qam16IsGainExp =
+ SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE;
+ qam64IsGainExp =
+ SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE;
+ }
+ break;
+ }
+ status = status;
+ if (status < 0)
+ break;
+
+ switch (p->constellation) {
+ default:
+ operationMode |= SC_RA_RAM_OP_AUTO_CONST__M;
+ /* fall through , try first guess
+ DRX_CONSTELLATION_QAM64 */
+ case QAM_64:
+ transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QAM64;
+ if (state->type_A) {
+ status = Write16(state, EQ_REG_OT_CONST__A, 0x0002, 0x0000);
+ if (status < 0)
+ break;
+ status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_64QAM, 0x0000);
+ if (status < 0)
+ break;
+ status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0020, 0x0000);
+ if (status < 0)
+ break;
+ status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0008, 0x0000);
+ if (status < 0)
+ break;
+ status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0002, 0x0000);
+ if (status < 0)
+ break;
+
+ status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam64TdTpsPwr, 0x0000);
+ if (status < 0)
+ break;
+ status = Write16(state, EQ_REG_SN_CEGAIN__A, qam64SnCeGain, 0x0000);
+ if (status < 0)
+ break;
+ status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam64IsGainMan, 0x0000);
+ if (status < 0)
+ break;
+ status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam64IsGainExp, 0x0000);
+ if (status < 0)
+ break;
+ }
+ break;
+ case QPSK:
+ transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QPSK;
+ if (state->type_A) {
+ status = Write16(state, EQ_REG_OT_CONST__A, 0x0000, 0x0000);
+ if (status < 0)
+ break;
+ status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_QPSK, 0x0000);
+ if (status < 0)
+ break;
+ status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000);
+ if (status < 0)
+ break;
+ status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0000, 0x0000);
+ if (status < 0)
+ break;
+ status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000);
+ if (status < 0)
+ break;
+
+ status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qpskTdTpsPwr, 0x0000);
+ if (status < 0)
+ break;
+ status = Write16(state, EQ_REG_SN_CEGAIN__A, qpskSnCeGain, 0x0000);
+ if (status < 0)
+ break;
+ status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qpskIsGainMan, 0x0000);
+ if (status < 0)
+ break;
+ status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qpskIsGainExp, 0x0000);
+ if (status < 0)
+ break;
+ }
+ break;
+
+ case QAM_16:
+ transmissionParams |= SC_RA_RAM_OP_PARAM_CONST_QAM16;
+ if (state->type_A) {
+ status = Write16(state, EQ_REG_OT_CONST__A, 0x0001, 0x0000);
+ if (status < 0)
+ break;
+ status = Write16(state, EC_SB_REG_CONST__A, EC_SB_REG_CONST_16QAM, 0x0000);
+ if (status < 0)
+ break;
+ status = Write16(state, EC_SB_REG_SCALE_MSB__A, 0x0010, 0x0000);
+ if (status < 0)
+ break;
+ status = Write16(state, EC_SB_REG_SCALE_BIT2__A, 0x0004, 0x0000);
+ if (status < 0)
+ break;
+ status = Write16(state, EC_SB_REG_SCALE_LSB__A, 0x0000, 0x0000);
+ if (status < 0)
+ break;
+
+ status = Write16(state, EQ_REG_TD_TPS_PWR_OFS__A, qam16TdTpsPwr, 0x0000);
+ if (status < 0)
+ break;
+ status = Write16(state, EQ_REG_SN_CEGAIN__A, qam16SnCeGain, 0x0000);
+ if (status < 0)
+ break;
+ status = Write16(state, EQ_REG_IS_GAIN_MAN__A, qam16IsGainMan, 0x0000);
+ if (status < 0)
+ break;
+ status = Write16(state, EQ_REG_IS_GAIN_EXP__A, qam16IsGainExp, 0x0000);
+ if (status < 0)
+ break;
+ }
+ break;
+
+ }
+ status = status;
+ if (status < 0)
+ break;
+
+ switch (DRX_CHANNEL_HIGH) {
+ default:
+ case DRX_CHANNEL_AUTO:
+ case DRX_CHANNEL_LOW:
+ transmissionParams |= SC_RA_RAM_OP_PARAM_PRIO_LO;
+ status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_LO, 0x0000);
+ if (status < 0)
+ break;
+ break;
+ case DRX_CHANNEL_HIGH:
+ transmissionParams |= SC_RA_RAM_OP_PARAM_PRIO_HI;
+ status = Write16(state, EC_SB_REG_PRIOR__A, EC_SB_REG_PRIOR_HI, 0x0000);
+ if (status < 0)
+ break;
+ break;
+
+ }
+
+ switch (p->code_rate_HP) {
+ case FEC_1_2:
+ transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_1_2;
+ if (state->type_A) {
+ status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C1_2, 0x0000);
+ if (status < 0)
+ break;
+ }
+ break;
+ default:
+ operationMode |= SC_RA_RAM_OP_AUTO_RATE__M;
+ case FEC_2_3:
+ transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_2_3;
+ if (state->type_A) {
+ status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C2_3, 0x0000);
+ if (status < 0)
+ break;
+ }
+ break;
+ case FEC_3_4:
+ transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_3_4;
+ if (state->type_A) {
+ status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C3_4, 0x0000);
+ if (status < 0)
+ break;
+ }
+ break;
+ case FEC_5_6:
+ transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_5_6;
+ if (state->type_A) {
+ status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C5_6, 0x0000);
+ if (status < 0)
+ break;
+ }
+ break;
+ case FEC_7_8:
+ transmissionParams |= SC_RA_RAM_OP_PARAM_RATE_7_8;
+ if (state->type_A) {
+ status = Write16(state, EC_VD_REG_SET_CODERATE__A, EC_VD_REG_SET_CODERATE_C7_8, 0x0000);
+ if (status < 0)
+ break;
+ }
+ break;
+ }
+ status = status;
+ if (status < 0)
+ break;
+
+ /* First determine real bandwidth (Hz) */
+ /* Also set delay for impulse noise cruncher (only A2) */
+ /* Also set parameters for EC_OC fix, note
+ EC_OC_REG_TMD_HIL_MAR is changed
+ by SC for fix for some 8K,1/8 guard but is restored by
+ InitEC and ResetEC
+ functions */
+ switch (p->bandwidth) {
+ case BANDWIDTH_AUTO:
+ case BANDWIDTH_8_MHZ:
+ /* (64/7)*(8/8)*1000000 */
+ bandwidth = DRXD_BANDWIDTH_8MHZ_IN_HZ;
+
+ bandwidthParam = 0;
+ status = Write16(state,
+ FE_AG_REG_IND_DEL__A, 50, 0x0000);
+ break;
+ case BANDWIDTH_7_MHZ:
+ /* (64/7)*(7/8)*1000000 */
+ bandwidth = DRXD_BANDWIDTH_7MHZ_IN_HZ;
+ bandwidthParam = 0x4807; /*binary:0100 1000 0000 0111 */
+ status = Write16(state,
+ FE_AG_REG_IND_DEL__A, 59, 0x0000);
+ break;
+ case BANDWIDTH_6_MHZ:
+ /* (64/7)*(6/8)*1000000 */
+ bandwidth = DRXD_BANDWIDTH_6MHZ_IN_HZ;
+ bandwidthParam = 0x0F07; /*binary: 0000 1111 0000 0111 */
+ status = Write16(state,
+ FE_AG_REG_IND_DEL__A, 71, 0x0000);
+ break;
+ default:
+ status = -EINVAL;
+ }
+ if (status < 0)
+ break;
+
+ status = Write16(state, SC_RA_RAM_BAND__A, bandwidthParam, 0x0000);
+ if (status < 0)
+ break;
+
+ {
+ u16 sc_config;
+ status = Read16(state, SC_RA_RAM_CONFIG__A, &sc_config, 0);
+ if (status < 0)
+ break;
+
+ /* enable SLAVE mode in 2k 1/32 to
+ prevent timing change glitches */
+ if ((p->transmission_mode == TRANSMISSION_MODE_2K) &&
+ (p->guard_interval == GUARD_INTERVAL_1_32)) {
+ /* enable slave */
+ sc_config |= SC_RA_RAM_CONFIG_SLAVE__M;
+ } else {
+ /* disable slave */
+ sc_config &= ~SC_RA_RAM_CONFIG_SLAVE__M;
+ }
+ status = Write16(state, SC_RA_RAM_CONFIG__A, sc_config, 0);
+ if (status < 0)
+ break;
+ }
+
+ status = SetCfgNoiseCalibration(state, &state->noise_cal);
+ if (status < 0)
+ break;
+
+ if (state->cscd_state == CSCD_INIT) {
+ /* switch on SRMM scan in SC */
+ status = Write16(state, SC_RA_RAM_SAMPLE_RATE_COUNT__A, DRXD_OSCDEV_DO_SCAN, 0x0000);
+ if (status < 0)
+ break;
+/* CHK_ERROR(Write16(SC_RA_RAM_SAMPLE_RATE_STEP__A, DRXD_OSCDEV_STEP, 0x0000));*/
+ state->cscd_state = CSCD_SET;
+ }
+
+ /* Now compute FE_IF_REG_INCR */
+ /*((( SysFreq/BandWidth)/2)/2) -1) * 2^23) =>
+ ((SysFreq / BandWidth) * (2^21) ) - (2^23) */
+ feIfIncr = MulDiv32(state->sys_clock_freq * 1000,
+ (1ULL << 21), bandwidth) - (1 << 23);
+ status = Write16(state, FE_IF_REG_INCR0__A, (u16) (feIfIncr & FE_IF_REG_INCR0__M), 0x0000);
+ if (status < 0)
+ break;
+ status = Write16(state, FE_IF_REG_INCR1__A, (u16) ((feIfIncr >> FE_IF_REG_INCR0__W) & FE_IF_REG_INCR1__M), 0x0000);
+ if (status < 0)
+ break;
+ /* Bandwidth setting done */
+
+ /* Mirror & frequency offset */
+ SetFrequencyShift(state, off, mirrorFreqSpect);
+
+ /* Start SC, write channel settings to SC */
+
+ /* Enable SC after setting all other parameters */
+ status = Write16(state, SC_COMM_STATE__A, 0, 0x0000);
+ if (status < 0)
+ break;
+ status = Write16(state, SC_COMM_EXEC__A, 1, 0x0000);
+ if (status < 0)
+ break;
+
+ /* Write SC parameter registers, operation mode */
+#if 1
+ operationMode = (SC_RA_RAM_OP_AUTO_MODE__M |
+ SC_RA_RAM_OP_AUTO_GUARD__M |
+ SC_RA_RAM_OP_AUTO_CONST__M |
+ SC_RA_RAM_OP_AUTO_HIER__M |
+ SC_RA_RAM_OP_AUTO_RATE__M);
+#endif
+ status = SC_SetPrefParamCommand(state, 0x0000, transmissionParams, operationMode);
+ if (status < 0)
+ break;
+
+ /* Start correct processes to get in lock */
+ status = SC_ProcStartCommand(state, SC_RA_RAM_PROC_LOCKTRACK, SC_RA_RAM_SW_EVENT_RUN_NMASK__M, SC_RA_RAM_LOCKTRACK_MIN);
+ if (status < 0)
+ break;
+
+ status = StartOC(state);
+ if (status < 0)
+ break;
+
+ if (state->operation_mode != OM_Default) {
+ status = StartDiversity(state);
+ if (status < 0)
+ break;
+ }
+
+ state->drxd_state = DRXD_STARTED;
+ } while (0);
+
+ return status;
+}
+
+static int CDRXD(struct drxd_state *state, u32 IntermediateFrequency)
+{
+ u32 ulRfAgcOutputLevel = 0xffffffff;
+ u32 ulRfAgcSettleLevel = 528; /* Optimum value for MT2060 */
+ u32 ulRfAgcMinLevel = 0; /* Currently unused */
+ u32 ulRfAgcMaxLevel = DRXD_FE_CTRL_MAX; /* Currently unused */
+ u32 ulRfAgcSpeed = 0; /* Currently unused */
+ u32 ulRfAgcMode = 0; /*2; Off */
+ u32 ulRfAgcR1 = 820;
+ u32 ulRfAgcR2 = 2200;
+ u32 ulRfAgcR3 = 150;
+ u32 ulIfAgcMode = 0; /* Auto */
+ u32 ulIfAgcOutputLevel = 0xffffffff;
+ u32 ulIfAgcSettleLevel = 0xffffffff;
+ u32 ulIfAgcMinLevel = 0xffffffff;
+ u32 ulIfAgcMaxLevel = 0xffffffff;
+ u32 ulIfAgcSpeed = 0xffffffff;
+ u32 ulIfAgcR1 = 820;
+ u32 ulIfAgcR2 = 2200;
+ u32 ulIfAgcR3 = 150;
+ u32 ulClock = state->config.clock;
+ u32 ulSerialMode = 0;
+ u32 ulEcOcRegOcModeLop = 4; /* Dynamic DTO source */
+ u32 ulHiI2cDelay = HI_I2C_DELAY;
+ u32 ulHiI2cBridgeDelay = HI_I2C_BRIDGE_DELAY;
+ u32 ulHiI2cPatch = 0;
+ u32 ulEnvironment = APPENV_PORTABLE;
+ u32 ulEnvironmentDiversity = APPENV_MOBILE;
+ u32 ulIFFilter = IFFILTER_SAW;
+
+ state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
+ state->if_agc_cfg.outputLevel = 0;
+ state->if_agc_cfg.settleLevel = 140;
+ state->if_agc_cfg.minOutputLevel = 0;
+ state->if_agc_cfg.maxOutputLevel = 1023;
+ state->if_agc_cfg.speed = 904;
+
+ if (ulIfAgcMode == 1 && ulIfAgcOutputLevel <= DRXD_FE_CTRL_MAX) {
+ state->if_agc_cfg.ctrlMode = AGC_CTRL_USER;
+ state->if_agc_cfg.outputLevel = (u16) (ulIfAgcOutputLevel);
+ }
+
+ if (ulIfAgcMode == 0 &&
+ ulIfAgcSettleLevel <= DRXD_FE_CTRL_MAX &&
+ ulIfAgcMinLevel <= DRXD_FE_CTRL_MAX &&
+ ulIfAgcMaxLevel <= DRXD_FE_CTRL_MAX &&
+ ulIfAgcSpeed <= DRXD_FE_CTRL_MAX) {
+ state->if_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
+ state->if_agc_cfg.settleLevel = (u16) (ulIfAgcSettleLevel);
+ state->if_agc_cfg.minOutputLevel = (u16) (ulIfAgcMinLevel);
+ state->if_agc_cfg.maxOutputLevel = (u16) (ulIfAgcMaxLevel);
+ state->if_agc_cfg.speed = (u16) (ulIfAgcSpeed);
+ }
+
+ state->if_agc_cfg.R1 = (u16) (ulIfAgcR1);
+ state->if_agc_cfg.R2 = (u16) (ulIfAgcR2);
+ state->if_agc_cfg.R3 = (u16) (ulIfAgcR3);
+
+ state->rf_agc_cfg.R1 = (u16) (ulRfAgcR1);
+ state->rf_agc_cfg.R2 = (u16) (ulRfAgcR2);
+ state->rf_agc_cfg.R3 = (u16) (ulRfAgcR3);
+
+ state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
+ /* rest of the RFAgcCfg structure currently unused */
+ if (ulRfAgcMode == 1 && ulRfAgcOutputLevel <= DRXD_FE_CTRL_MAX) {
+ state->rf_agc_cfg.ctrlMode = AGC_CTRL_USER;
+ state->rf_agc_cfg.outputLevel = (u16) (ulRfAgcOutputLevel);
+ }
+
+ if (ulRfAgcMode == 0 &&
+ ulRfAgcSettleLevel <= DRXD_FE_CTRL_MAX &&
+ ulRfAgcMinLevel <= DRXD_FE_CTRL_MAX &&
+ ulRfAgcMaxLevel <= DRXD_FE_CTRL_MAX &&
+ ulRfAgcSpeed <= DRXD_FE_CTRL_MAX) {
+ state->rf_agc_cfg.ctrlMode = AGC_CTRL_AUTO;
+ state->rf_agc_cfg.settleLevel = (u16) (ulRfAgcSettleLevel);
+ state->rf_agc_cfg.minOutputLevel = (u16) (ulRfAgcMinLevel);
+ state->rf_agc_cfg.maxOutputLevel = (u16) (ulRfAgcMaxLevel);
+ state->rf_agc_cfg.speed = (u16) (ulRfAgcSpeed);
+ }
+
+ if (ulRfAgcMode == 2)
+ state->rf_agc_cfg.ctrlMode = AGC_CTRL_OFF;
+
+ if (ulEnvironment <= 2)
+ state->app_env_default = (enum app_env)
+ (ulEnvironment);
+ if (ulEnvironmentDiversity <= 2)
+ state->app_env_diversity = (enum app_env)
+ (ulEnvironmentDiversity);
+
+ if (ulIFFilter == IFFILTER_DISCRETE) {
+ /* discrete filter */
+ state->noise_cal.cpOpt = 0;
+ state->noise_cal.cpNexpOfs = 40;
+ state->noise_cal.tdCal2k = -40;
+ state->noise_cal.tdCal8k = -24;
+ } else {
+ /* SAW filter */
+ state->noise_cal.cpOpt = 1;
+ state->noise_cal.cpNexpOfs = 0;
+ state->noise_cal.tdCal2k = -21;
+ state->noise_cal.tdCal8k = -24;
+ }
+ state->m_EcOcRegOcModeLop = (u16) (ulEcOcRegOcModeLop);
+
+ state->chip_adr = (state->config.demod_address << 1) | 1;
+ switch (ulHiI2cPatch) {
+ case 1:
+ state->m_HiI2cPatch = DRXD_HiI2cPatch_1;
+ break;
+ case 3:
+ state->m_HiI2cPatch = DRXD_HiI2cPatch_3;
+ break;
+ default:
+ state->m_HiI2cPatch = NULL;
+ }
+
+ /* modify tuner and clock attributes */
+ state->intermediate_freq = (u16) (IntermediateFrequency / 1000);
+ /* expected system clock frequency in kHz */
+ state->expected_sys_clock_freq = 48000;
+ /* real system clock frequency in kHz */
+ state->sys_clock_freq = 48000;
+ state->osc_clock_freq = (u16) ulClock;
+ state->osc_clock_deviation = 0;
+ state->cscd_state = CSCD_INIT;
+ state->drxd_state = DRXD_UNINITIALIZED;
+
+ state->PGA = 0;
+ state->type_A = 0;
+ state->tuner_mirrors = 0;
+
+ /* modify MPEG output attributes */
+ state->insert_rs_byte = state->config.insert_rs_byte;
+ state->enable_parallel = (ulSerialMode != 1);
+
+ /* Timing div, 250ns/Psys */
+ /* Timing div, = ( delay (nano seconds) * sysclk (kHz) )/ 1000 */
+
+ state->hi_cfg_timing_div = (u16) ((state->sys_clock_freq / 1000) *
+ ulHiI2cDelay) / 1000;
+ /* Bridge delay, uses oscilator clock */
+ /* Delay = ( delay (nano seconds) * oscclk (kHz) )/ 1000 */
+ state->hi_cfg_bridge_delay = (u16) ((state->osc_clock_freq / 1000) *
+ ulHiI2cBridgeDelay) / 1000;
+
+ state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER;
+ /* state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO; */
+ state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO;
+ return 0;
+}
+
+int DRXD_init(struct drxd_state *state, const u8 * fw, u32 fw_size)
+{
+ int status = 0;
+ u32 driverVersion;
+
+ if (state->init_done)
+ return 0;
+
+ CDRXD(state, state->config.IF ? state->config.IF : 36000000);
+
+ do {
+ state->operation_mode = OM_Default;
+
+ status = SetDeviceTypeId(state);
+ if (status < 0)
+ break;
+
+ /* Apply I2c address patch to B1 */
+ if (!state->type_A && state->m_HiI2cPatch != NULL)
+ status = WriteTable(state, state->m_HiI2cPatch);
+ if (status < 0)
+ break;
+
+ if (state->type_A) {
+ /* HI firmware patch for UIO readout,
+ avoid clearing of result register */
+ status = Write16(state, 0x43012D, 0x047f, 0);
+ if (status < 0)
+ break;
+ }
+
+ status = HI_ResetCommand(state);
+ if (status < 0)
+ break;
+
+ status = StopAllProcessors(state);
+ if (status < 0)
+ break;
+ status = InitCC(state);
+ if (status < 0)
+ break;
+
+ state->osc_clock_deviation = 0;
+
+ if (state->config.osc_deviation)
+ state->osc_clock_deviation =
+ state->config.osc_deviation(state->priv, 0, 0);
+ {
+ /* Handle clock deviation */
+ s32 devB;
+ s32 devA = (s32) (state->osc_clock_deviation) *
+ (s32) (state->expected_sys_clock_freq);
+ /* deviation in kHz */
+ s32 deviation = (devA / (1000000L));
+ /* rounding, signed */
+ if (devA > 0)
+ devB = (2);
+ else
+ devB = (-2);
+ if ((devB * (devA % 1000000L) > 1000000L)) {
+ /* add +1 or -1 */
+ deviation += (devB / 2);
+ }
+
+ state->sys_clock_freq =
+ (u16) ((state->expected_sys_clock_freq) +
+ deviation);
+ }
+ status = InitHI(state);
+ if (status < 0)
+ break;
+ status = InitAtomicRead(state);
+ if (status < 0)
+ break;
+
+ status = EnableAndResetMB(state);
+ if (status < 0)
+ break;
+ if (state->type_A)
+ status = ResetCEFR(state);
+ if (status < 0)
+ break;
+
+ if (fw) {
+ status = DownloadMicrocode(state, fw, fw_size);
+ if (status < 0)
+ break;
+ } else {
+ status = DownloadMicrocode(state, state->microcode, state->microcode_length);
+ if (status < 0)
+ break;
+ }
+
+ if (state->PGA) {
+ state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_PRO;
+ SetCfgPga(state, 0); /* PGA = 0 dB */
+ } else {
+ state->m_FeAgRegAgPwd = DRXD_DEF_AG_PWD_CONSUMER;
+ }
+
+ state->m_FeAgRegAgAgcSio = DRXD_DEF_AG_AGC_SIO;
+
+ status = InitFE(state);
+ if (status < 0)
+ break;
+ status = InitFT(state);
+ if (status < 0)
+ break;
+ status = InitCP(state);
+ if (status < 0)
+ break;
+ status = InitCE(state);
+ if (status < 0)
+ break;
+ status = InitEQ(state);
+ if (status < 0)
+ break;
+ status = InitEC(state);
+ if (status < 0)
+ break;
+ status = InitSC(state);
+ if (status < 0)
+ break;
+
+ status = SetCfgIfAgc(state, &state->if_agc_cfg);
+ if (status < 0)
+ break;
+ status = SetCfgRfAgc(state, &state->rf_agc_cfg);
+ if (status < 0)
+ break;
+
+ state->cscd_state = CSCD_INIT;
+ status = Write16(state, SC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
+ if (status < 0)
+ break;
+ status = Write16(state, LC_COMM_EXEC__A, SC_COMM_EXEC_CTL_STOP, 0);
+ if (status < 0)
+ break;
+
+ driverVersion = (((VERSION_MAJOR / 10) << 4) +
+ (VERSION_MAJOR % 10)) << 24;
+ driverVersion += (((VERSION_MINOR / 10) << 4) +
+ (VERSION_MINOR % 10)) << 16;
+ driverVersion += ((VERSION_PATCH / 1000) << 12) +
+ ((VERSION_PATCH / 100) << 8) +
+ ((VERSION_PATCH / 10) << 4) + (VERSION_PATCH % 10);
+
+ status = Write32(state, SC_RA_RAM_DRIVER_VERSION__AX, driverVersion, 0);
+ if (status < 0)
+ break;
+
+ status = StopOC(state);
+ if (status < 0)
+ break;
+
+ state->drxd_state = DRXD_STOPPED;
+ state->init_done = 1;
+ status = 0;
+ } while (0);
+ return status;
+}
+
+int DRXD_status(struct drxd_state *state, u32 * pLockStatus)
+{
+ DRX_GetLockStatus(state, pLockStatus);
+
+ /*if (*pLockStatus&DRX_LOCK_MPEG) */
+ if (*pLockStatus & DRX_LOCK_FEC) {
+ ConfigureMPEGOutput(state, 1);
+ /* Get status again, in case we have MPEG lock now */
+ /*DRX_GetLockStatus(state, pLockStatus); */
+ }
+
+ return 0;
+}
+
+/****************************************************************************/
+/****************************************************************************/
+/****************************************************************************/
+
+static int drxd_read_signal_strength(struct dvb_frontend *fe, u16 * strength)
+{
+ struct drxd_state *state = fe->demodulator_priv;
+ u32 value;
+ int res;
+
+ res = ReadIFAgc(state, &value);
+ if (res < 0)
+ *strength = 0;
+ else
+ *strength = 0xffff - (value << 4);
+ return 0;
+}
+
+static int drxd_read_status(struct dvb_frontend *fe, fe_status_t * status)
+{
+ struct drxd_state *state = fe->demodulator_priv;
+ u32 lock;
+
+ DRXD_status(state, &lock);
+ *status = 0;
+ /* No MPEG lock in V255 firmware, bug ? */
+#if 1
+ if (lock & DRX_LOCK_MPEG)
+ *status |= FE_HAS_LOCK;
+#else
+ if (lock & DRX_LOCK_FEC)
+ *status |= FE_HAS_LOCK;
+#endif
+ if (lock & DRX_LOCK_FEC)
+ *status |= FE_HAS_VITERBI | FE_HAS_SYNC;
+ if (lock & DRX_LOCK_DEMOD)
+ *status |= FE_HAS_CARRIER | FE_HAS_SIGNAL;
+
+ return 0;
+}
+
+static int drxd_init(struct dvb_frontend *fe)
+{
+ struct drxd_state *state = fe->demodulator_priv;
+ int err = 0;
+
+/* if (request_firmware(&state->fw, "drxd.fw", state->dev)<0) */
+ return DRXD_init(state, 0, 0);
+
+ err = DRXD_init(state, state->fw->data, state->fw->size);
+ release_firmware(state->fw);
+ return err;
+}
+
+int drxd_config_i2c(struct dvb_frontend *fe, int onoff)
+{
+ struct drxd_state *state = fe->demodulator_priv;
+
+ if (state->config.disable_i2c_gate_ctrl == 1)
+ return 0;
+
+ return DRX_ConfigureI2CBridge(state, onoff);
+}
+EXPORT_SYMBOL(drxd_config_i2c);
+
+static int drxd_get_tune_settings(struct dvb_frontend *fe,
+ struct dvb_frontend_tune_settings *sets)
+{
+ sets->min_delay_ms = 10000;
+ sets->max_drift = 0;
+ sets->step_size = 0;
+ return 0;
+}
+
+static int drxd_read_ber(struct dvb_frontend *fe, u32 * ber)
+{
+ *ber = 0;
+ return 0;
+}
+
+static int drxd_read_snr(struct dvb_frontend *fe, u16 * snr)
+{
+ *snr = 0;
+ return 0;
+}
+
+static int drxd_read_ucblocks(struct dvb_frontend *fe, u32 * ucblocks)
+{
+ *ucblocks = 0;
+ return 0;
+}
+
+static int drxd_sleep(struct dvb_frontend *fe)
+{
+ struct drxd_state *state = fe->demodulator_priv;
+
+ ConfigureMPEGOutput(state, 0);
+ return 0;
+}
+
+static int drxd_get_frontend(struct dvb_frontend *fe,
+ struct dvb_frontend_parameters *param)
+{
+ return 0;
+}
+
+static int drxd_i2c_gate_ctrl(struct dvb_frontend *fe, int enable)
+{
+ return drxd_config_i2c(fe, enable);
+}
+
+static int drxd_set_frontend(struct dvb_frontend *fe,
+ struct dvb_frontend_parameters *param)
+{
+ struct drxd_state *state = fe->demodulator_priv;
+ s32 off = 0;
+
+ state->param = *param;
+ DRX_Stop(state);
+
+ if (fe->ops.tuner_ops.set_params) {
+ fe->ops.tuner_ops.set_params(fe, param);
+ if (fe->ops.i2c_gate_ctrl)
+ fe->ops.i2c_gate_ctrl(fe, 0);
+ }
+
+ /* FIXME: move PLL drivers */
+ if (state->config.pll_set &&
+ state->config.pll_set(state->priv, param,
+ state->config.pll_address,
+ state->config.demoda_address, &off) < 0) {
+ printk(KERN_ERR "Error in pll_set\n");
+ return -1;
+ }
+
+ msleep(200);
+
+ return DRX_Start(state, off);
+}
+
+static void drxd_release(struct dvb_frontend *fe)
+{
+ struct drxd_state *state = fe->demodulator_priv;
+
+ kfree(state);
+}
+
+static struct dvb_frontend_ops drxd_ops = {
+
+ .info = {
+ .name = "Micronas DRXD DVB-T",
+ .type = FE_OFDM,
+ .frequency_min = 47125000,
+ .frequency_max = 855250000,
+ .frequency_stepsize = 166667,
+ .frequency_tolerance = 0,
+ .caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
+ FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
+ FE_CAN_FEC_AUTO |
+ FE_CAN_QAM_16 | FE_CAN_QAM_64 |
+ FE_CAN_QAM_AUTO |
+ FE_CAN_TRANSMISSION_MODE_AUTO |
+ FE_CAN_GUARD_INTERVAL_AUTO |
+ FE_CAN_HIERARCHY_AUTO | FE_CAN_RECOVER | FE_CAN_MUTE_TS},
+
+ .release = drxd_release,
+ .init = drxd_init,
+ .sleep = drxd_sleep,
+ .i2c_gate_ctrl = drxd_i2c_gate_ctrl,
+
+ .set_frontend = drxd_set_frontend,
+ .get_frontend = drxd_get_frontend,
+ .get_tune_settings = drxd_get_tune_settings,
+
+ .read_status = drxd_read_status,
+ .read_ber = drxd_read_ber,
+ .read_signal_strength = drxd_read_signal_strength,
+ .read_snr = drxd_read_snr,
+ .read_ucblocks = drxd_read_ucblocks,
+};
+
+struct dvb_frontend *drxd_attach(const struct drxd_config *config,
+ void *priv, struct i2c_adapter *i2c,
+ struct device *dev)
+{
+ struct drxd_state *state = NULL;
+
+ state = kmalloc(sizeof(struct drxd_state), GFP_KERNEL);
+ if (!state)
+ return NULL;
+ memset(state, 0, sizeof(*state));
+
+ memcpy(&state->ops, &drxd_ops, sizeof(struct dvb_frontend_ops));
+ state->dev = dev;
+ state->config = *config;
+ state->i2c = i2c;
+ state->priv = priv;
+
+ mutex_init(&state->mutex);
+
+ if (Read16(state, 0, 0, 0) < 0)
+ goto error;
+
+ memcpy(&state->frontend.ops, &drxd_ops,
+ sizeof(struct dvb_frontend_ops));
+ state->frontend.demodulator_priv = state;
+ ConfigureMPEGOutput(state, 0);
+ return &state->frontend;
+
+error:
+ printk(KERN_ERR "drxd: not found\n");
+ kfree(state);
+ return NULL;
+}
+EXPORT_SYMBOL(drxd_attach);
+
+MODULE_DESCRIPTION("DRXD driver");
+MODULE_AUTHOR("Micronas");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/dvb/frontends/drxd_map_firm.h b/drivers/media/dvb/frontends/drxd_map_firm.h
new file mode 100644
index 0000000..6bc553a
--- /dev/null
+++ b/drivers/media/dvb/frontends/drxd_map_firm.h
@@ -0,0 +1,1013 @@
+/*
+ * drx3973d_map_firm.h
+ *
+ * Copyright (C) 2006-2007 Micronas
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 only, as published by the Free Software Foundation.
+ *
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
+ * 02110-1301, USA
+ * Or, point your browser to http://www.gnu.org/copyleft/gpl.html
+ */
+
+#ifndef __DRX3973D_MAP__H__
+#define __DRX3973D_MAP__H__
+
+/*
+ * Note: originally, this file contained 12000+ lines of data
+ * Probably a few lines for every firwmare assembler instruction. However,
+ * only a few defines were actually used. So, removed all uneeded lines.
+ * If ever needed, the other lines can be easily obtained via git history.
+ */
+
+#define HI_COMM_EXEC__A 0x400000
+#define HI_COMM_MB__A 0x400002
+#define HI_CT_REG_COMM_STATE__A 0x410001
+#define HI_RA_RAM_SRV_RES__A 0x420031
+#define HI_RA_RAM_SRV_CMD__A 0x420032
+#define HI_RA_RAM_SRV_CMD_RESET 0x2
+#define HI_RA_RAM_SRV_CMD_CONFIG 0x3
+#define HI_RA_RAM_SRV_CMD_EXECUTE 0x6
+#define HI_RA_RAM_SRV_RST_KEY__A 0x420033
+#define HI_RA_RAM_SRV_RST_KEY_ACT 0x3973
+#define HI_RA_RAM_SRV_CFG_KEY__A 0x420033
+#define HI_RA_RAM_SRV_CFG_DIV__A 0x420034
+#define HI_RA_RAM_SRV_CFG_BDL__A 0x420035
+#define HI_RA_RAM_SRV_CFG_WUP__A 0x420036
+#define HI_RA_RAM_SRV_CFG_ACT__A 0x420037
+#define HI_RA_RAM_SRV_CFG_ACT_SLV0_ON 0x1
+#define HI_RA_RAM_SRV_CFG_ACT_BRD__M 0x4
+#define HI_RA_RAM_SRV_CFG_ACT_BRD_OFF 0x0
+#define HI_RA_RAM_SRV_CFG_ACT_BRD_ON 0x4
+#define HI_RA_RAM_SRV_CFG_ACT_PWD_EXE 0x8
+#define HI_RA_RAM_USR_BEGIN__A 0x420040
+#define HI_IF_RAM_TRP_BPT0__AX 0x430000
+#define HI_IF_RAM_USR_BEGIN__A 0x430200
+#define SC_COMM_EXEC__A 0x800000
+#define SC_COMM_EXEC_CTL_STOP 0x0
+#define SC_COMM_STATE__A 0x800001
+#define SC_RA_RAM_PARAM0__A 0x820040
+#define SC_RA_RAM_PARAM1__A 0x820041
+#define SC_RA_RAM_CMD_ADDR__A 0x820042
+#define SC_RA_RAM_CMD__A 0x820043
+#define SC_RA_RAM_CMD_PROC_START 0x1
+#define SC_RA_RAM_CMD_SET_PREF_PARAM 0x3
+#define SC_RA_RAM_CMD_GET_OP_PARAM 0x5
+#define SC_RA_RAM_SW_EVENT_RUN_NMASK__M 0x1
+#define SC_RA_RAM_LOCKTRACK_MIN 0x1
+#define SC_RA_RAM_OP_PARAM_MODE_2K 0x0
+#define SC_RA_RAM_OP_PARAM_MODE_8K 0x1
+#define SC_RA_RAM_OP_PARAM_GUARD_32 0x0
+#define SC_RA_RAM_OP_PARAM_GUARD_16 0x4
+#define SC_RA_RAM_OP_PARAM_GUARD_8 0x8
+#define SC_RA_RAM_OP_PARAM_GUARD_4 0xC
+#define SC_RA_RAM_OP_PARAM_CONST_QPSK 0x0
+#define SC_RA_RAM_OP_PARAM_CONST_QAM16 0x10
+#define SC_RA_RAM_OP_PARAM_CONST_QAM64 0x20
+#define SC_RA_RAM_OP_PARAM_HIER_NO 0x0
+#define SC_RA_RAM_OP_PARAM_HIER_A1 0x40
+#define SC_RA_RAM_OP_PARAM_HIER_A2 0x80
+#define SC_RA_RAM_OP_PARAM_HIER_A4 0xC0
+#define SC_RA_RAM_OP_PARAM_RATE_1_2 0x0
+#define SC_RA_RAM_OP_PARAM_RATE_2_3 0x200
+#define SC_RA_RAM_OP_PARAM_RATE_3_4 0x400
+#define SC_RA_RAM_OP_PARAM_RATE_5_6 0x600
+#define SC_RA_RAM_OP_PARAM_RATE_7_8 0x800
+#define SC_RA_RAM_OP_PARAM_PRIO_HI 0x0
+#define SC_RA_RAM_OP_PARAM_PRIO_LO 0x1000
+#define SC_RA_RAM_OP_AUTO_MODE__M 0x1
+#define SC_RA_RAM_OP_AUTO_GUARD__M 0x2
+#define SC_RA_RAM_OP_AUTO_CONST__M 0x4
+#define SC_RA_RAM_OP_AUTO_HIER__M 0x8
+#define SC_RA_RAM_OP_AUTO_RATE__M 0x10
+#define SC_RA_RAM_LOCK__A 0x82004B
+#define SC_RA_RAM_LOCK_DEMOD__M 0x1
+#define SC_RA_RAM_LOCK_FEC__M 0x2
+#define SC_RA_RAM_LOCK_MPEG__M 0x4
+#define SC_RA_RAM_BE_OPT_ENA__A 0x82004C
+#define SC_RA_RAM_BE_OPT_ENA_CP_OPT 0x1
+#define SC_RA_RAM_BE_OPT_DELAY__A 0x82004D
+#define SC_RA_RAM_CONFIG__A 0x820050
+#define SC_RA_RAM_CONFIG_FR_ENABLE__M 0x4
+#define SC_RA_RAM_CONFIG_FREQSCAN__M 0x10
+#define SC_RA_RAM_CONFIG_SLAVE__M 0x20
+#define SC_RA_RAM_IF_SAVE__AX 0x82008E
+#define SC_RA_RAM_IR_COARSE_2K_LENGTH__A 0x8200D1
+#define SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE 0x9
+#define SC_RA_RAM_IR_COARSE_2K_FREQINC__A 0x8200D2
+#define SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE 0x4
+#define SC_RA_RAM_IR_COARSE_2K_KAISINC__A 0x8200D3
+#define SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE 0x100
+#define SC_RA_RAM_IR_COARSE_8K_LENGTH__A 0x8200D4
+#define SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE 0x8
+#define SC_RA_RAM_IR_COARSE_8K_FREQINC__A 0x8200D5
+#define SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE 0x8
+#define SC_RA_RAM_IR_COARSE_8K_KAISINC__A 0x8200D6
+#define SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE 0x200
+#define SC_RA_RAM_IR_FINE_2K_LENGTH__A 0x8200D7
+#define SC_RA_RAM_IR_FINE_2K_LENGTH__PRE 0x9
+#define SC_RA_RAM_IR_FINE_2K_FREQINC__A 0x8200D8
+#define SC_RA_RAM_IR_FINE_2K_FREQINC__PRE 0x4
+#define SC_RA_RAM_IR_FINE_2K_KAISINC__A 0x8200D9
+#define SC_RA_RAM_IR_FINE_2K_KAISINC__PRE 0x100
+#define SC_RA_RAM_IR_FINE_8K_LENGTH__A 0x8200DA
+#define SC_RA_RAM_IR_FINE_8K_LENGTH__PRE 0xB
+#define SC_RA_RAM_IR_FINE_8K_FREQINC__A 0x8200DB
+#define SC_RA_RAM_IR_FINE_8K_FREQINC__PRE 0x1
+#define SC_RA_RAM_IR_FINE_8K_KAISINC__A 0x8200DC
+#define SC_RA_RAM_IR_FINE_8K_KAISINC__PRE 0x40
+#define SC_RA_RAM_ECHO_SHIFT_LIM__A 0x8200DD
+#define SC_RA_RAM_SAMPLE_RATE_COUNT__A 0x8200E8
+#define SC_RA_RAM_SAMPLE_RATE_STEP__A 0x8200E9
+#define SC_RA_RAM_BAND__A 0x8200EC
+#define SC_RA_RAM_LC_ABS_2K__A 0x8200F4
+#define SC_RA_RAM_LC_ABS_2K__PRE 0x1F
+#define SC_RA_RAM_LC_ABS_8K__A 0x8200F5
+#define SC_RA_RAM_LC_ABS_8K__PRE 0x1F
+#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE 0x1D6
+#define SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE 0x4
+#define SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE 0x1BB
+#define SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE 0x5
+#define SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE 0x1EF
+#define SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE 0x5
+#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE 0x15E
+#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE 0x5
+#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE 0x11A
+#define SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE 0x6
+#define SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE 0x1FB
+#define SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE 0x5
+#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE 0x12F
+#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE 0x5
+#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE 0x197
+#define SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE 0x5
+#define SC_RA_RAM_DRIVER_VERSION__AX 0x8201FE
+#define SC_RA_RAM_PROC_LOCKTRACK 0x0
+#define FE_COMM_EXEC__A 0xC00000
+#define FE_AD_REG_COMM_EXEC__A 0xC10000
+#define FE_AD_REG_FDB_IN__A 0xC10012
+#define FE_AD_REG_PD__A 0xC10013
+#define FE_AD_REG_INVEXT__A 0xC10014
+#define FE_AD_REG_CLKNEG__A 0xC10015
+#define FE_AG_REG_COMM_EXEC__A 0xC20000
+#define FE_AG_REG_AG_MODE_LOP__A 0xC20010
+#define FE_AG_REG_AG_MODE_LOP_MODE_4__M 0x10
+#define FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC 0x0
+#define FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC 0x10
+#define FE_AG_REG_AG_MODE_LOP_MODE_5__M 0x20
+#define FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC 0x0
+#define FE_AG_REG_AG_MODE_LOP_MODE_C__M 0x1000
+#define FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC 0x0
+#define FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC 0x1000
+#define FE_AG_REG_AG_MODE_LOP_MODE_E__M 0x4000
+#define FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC 0x0
+#define FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC 0x4000
+#define FE_AG_REG_AG_MODE_HIP__A 0xC20011
+#define FE_AG_REG_AG_PGA_MODE__A 0xC20012
+#define FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN 0x0
+#define FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN 0x1
+#define FE_AG_REG_AG_AGC_SIO__A 0xC20013
+#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M 0x2
+#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT 0x0
+#define FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT 0x2
+#define FE_AG_REG_AG_PWD__A 0xC20015
+#define FE_AG_REG_AG_PWD_PWD_PD2__M 0x2
+#define FE_AG_REG_AG_PWD_PWD_PD2_DISABLE 0x0
+#define FE_AG_REG_AG_PWD_PWD_PD2_ENABLE 0x2
+#define FE_AG_REG_DCE_AUR_CNT__A 0xC20016
+#define FE_AG_REG_DCE_RUR_CNT__A 0xC20017
+#define FE_AG_REG_ACE_AUR_CNT__A 0xC2001A
+#define FE_AG_REG_ACE_RUR_CNT__A 0xC2001B
+#define FE_AG_REG_CDR_RUR_CNT__A 0xC20020
+#define FE_AG_REG_EGC_RUR_CNT__A 0xC20024
+#define FE_AG_REG_EGC_SET_LVL__A 0xC20025
+#define FE_AG_REG_EGC_SET_LVL__M 0x1FF
+#define FE_AG_REG_EGC_FLA_RGN__A 0xC20026
+#define FE_AG_REG_EGC_SLO_RGN__A 0xC20027
+#define FE_AG_REG_EGC_JMP_PSN__A 0xC20028
+#define FE_AG_REG_EGC_FLA_INC__A 0xC20029
+#define FE_AG_REG_EGC_FLA_DEC__A 0xC2002A
+#define FE_AG_REG_EGC_SLO_INC__A 0xC2002B
+#define FE_AG_REG_EGC_SLO_DEC__A 0xC2002C
+#define FE_AG_REG_EGC_FAS_INC__A 0xC2002D
+#define FE_AG_REG_EGC_FAS_DEC__A 0xC2002E
+#define FE_AG_REG_PM1_AGC_WRI__A 0xC20030
+#define FE_AG_REG_PM1_AGC_WRI__M 0x7FF
+#define FE_AG_REG_GC1_AGC_RIC__A 0xC20031
+#define FE_AG_REG_GC1_AGC_OFF__A 0xC20032
+#define FE_AG_REG_GC1_AGC_MAX__A 0xC20033
+#define FE_AG_REG_GC1_AGC_MIN__A 0xC20034
+#define FE_AG_REG_GC1_AGC_DAT__A 0xC20035
+#define FE_AG_REG_GC1_AGC_DAT__M 0x3FF
+#define FE_AG_REG_PM2_AGC_WRI__A 0xC20036
+#define FE_AG_REG_IND_WIN__A 0xC2003C
+#define FE_AG_REG_IND_THD_LOL__A 0xC2003D
+#define FE_AG_REG_IND_THD_HIL__A 0xC2003E
+#define FE_AG_REG_IND_DEL__A 0xC2003F
+#define FE_AG_REG_IND_PD1_WRI__A 0xC20040
+#define FE_AG_REG_PDA_AUR_CNT__A 0xC20041
+#define FE_AG_REG_PDA_RUR_CNT__A 0xC20042
+#define FE_AG_REG_PDA_AVE_DAT__A 0xC20043
+#define FE_AG_REG_PDC_RUR_CNT__A 0xC20044
+#define FE_AG_REG_PDC_SET_LVL__A 0xC20045
+#define FE_AG_REG_PDC_FLA_RGN__A 0xC20046
+#define FE_AG_REG_PDC_JMP_PSN__A 0xC20047
+#define FE_AG_REG_PDC_FLA_STP__A 0xC20048
+#define FE_AG_REG_PDC_SLO_STP__A 0xC20049
+#define FE_AG_REG_PDC_PD2_WRI__A 0xC2004A
+#define FE_AG_REG_PDC_MAP_DAT__A 0xC2004B
+#define FE_AG_REG_PDC_MAX__A 0xC2004C
+#define FE_AG_REG_TGA_AUR_CNT__A 0xC2004D
+#define FE_AG_REG_TGA_RUR_CNT__A 0xC2004E
+#define FE_AG_REG_TGA_AVE_DAT__A 0xC2004F
+#define FE_AG_REG_TGC_RUR_CNT__A 0xC20050
+#define FE_AG_REG_TGC_SET_LVL__A 0xC20051
+#define FE_AG_REG_TGC_SET_LVL__M 0x3F
+#define FE_AG_REG_TGC_FLA_RGN__A 0xC20052
+#define FE_AG_REG_TGC_JMP_PSN__A 0xC20053
+#define FE_AG_REG_TGC_FLA_STP__A 0xC20054
+#define FE_AG_REG_TGC_SLO_STP__A 0xC20055
+#define FE_AG_REG_TGC_MAP_DAT__A 0xC20056
+#define FE_AG_REG_FGA_AUR_CNT__A 0xC20057
+#define FE_AG_REG_FGA_RUR_CNT__A 0xC20058
+#define FE_AG_REG_FGM_WRI__A 0xC20061
+#define FE_AG_REG_BGC_FGC_WRI__A 0xC20068
+#define FE_AG_REG_BGC_CGC_WRI__A 0xC20069
+#define FE_FS_REG_COMM_EXEC__A 0xC30000
+#define FE_FS_REG_ADD_INC_LOP__A 0xC30010
+#define FE_FD_REG_COMM_EXEC__A 0xC40000
+#define FE_FD_REG_SCL__A 0xC40010
+#define FE_FD_REG_MAX_LEV__A 0xC40011
+#define FE_FD_REG_NR__A 0xC40012
+#define FE_FD_REG_MEAS_VAL__A 0xC40014
+#define FE_IF_REG_COMM_EXEC__A 0xC50000
+#define FE_IF_REG_INCR0__A 0xC50010
+#define FE_IF_REG_INCR0__W 16
+#define FE_IF_REG_INCR0__M 0xFFFF
+#define FE_IF_REG_INCR1__A 0xC50011
+#define FE_IF_REG_INCR1__M 0xFF
+#define FE_CF_REG_COMM_EXEC__A 0xC60000
+#define FE_CF_REG_SCL__A 0xC60010
+#define FE_CF_REG_MAX_LEV__A 0xC60011
+#define FE_CF_REG_NR__A 0xC60012
+#define FE_CF_REG_IMP_VAL__A 0xC60013
+#define FE_CF_REG_MEAS_VAL__A 0xC60014
+#define FE_CU_REG_COMM_EXEC__A 0xC70000
+#define FE_CU_REG_FRM_CNT_RST__A 0xC70011
+#define FE_CU_REG_FRM_CNT_STR__A 0xC70012
+#define FT_COMM_EXEC__A 0x1000000
+#define FT_REG_COMM_EXEC__A 0x1010000
+#define CP_COMM_EXEC__A 0x1400000
+#define CP_REG_COMM_EXEC__A 0x1410000
+#define CP_REG_INTERVAL__A 0x1410011
+#define CP_REG_BR_SPL_OFFSET__A 0x1410023
+#define CP_REG_BR_STR_DEL__A 0x1410024
+#define CP_REG_RT_ANG_INC0__A 0x1410030
+#define CP_REG_RT_ANG_INC1__A 0x1410031
+#define CP_REG_RT_DETECT_ENA__A 0x1410032
+#define CP_REG_RT_DETECT_TRH__A 0x1410033
+#define CP_REG_RT_EXP_MARG__A 0x141003E
+#define CP_REG_AC_NEXP_OFFS__A 0x1410040
+#define CP_REG_AC_AVER_POW__A 0x1410041
+#define CP_REG_AC_MAX_POW__A 0x1410042
+#define CP_REG_AC_WEIGHT_MAN__A 0x1410043
+#define CP_REG_AC_WEIGHT_EXP__A 0x1410044
+#define CP_REG_AC_AMP_MODE__A 0x1410047
+#define CP_REG_AC_AMP_FIX__A 0x1410048
+#define CP_REG_AC_ANG_MODE__A 0x141004A
+#define CE_COMM_EXEC__A 0x1800000
+#define CE_REG_COMM_EXEC__A 0x1810000
+#define CE_REG_TAPSET__A 0x1810011
+#define CE_REG_AVG_POW__A 0x1810012
+#define CE_REG_MAX_POW__A 0x1810013
+#define CE_REG_ATT__A 0x1810014
+#define CE_REG_NRED__A 0x1810015
+#define CE_REG_NE_ERR_SELECT__A 0x1810043
+#define CE_REG_NE_TD_CAL__A 0x1810044
+#define CE_REG_NE_MIXAVG__A 0x1810046
+#define CE_REG_NE_NUPD_OFS__A 0x1810047
+#define CE_REG_PE_NEXP_OFFS__A 0x1810050
+#define CE_REG_PE_TIMESHIFT__A 0x1810051
+#define CE_REG_TP_A0_TAP_NEW__A 0x1810064
+#define CE_REG_TP_A0_TAP_NEW_VALID__A 0x1810065
+#define CE_REG_TP_A0_MU_LMS_STEP__A 0x1810066
+#define CE_REG_TP_A1_TAP_NEW__A 0x1810068
+#define CE_REG_TP_A1_TAP_NEW_VALID__A 0x1810069
+#define CE_REG_TP_A1_MU_LMS_STEP__A 0x181006A
+#define CE_REG_TI_NEXP_OFFS__A 0x1810070
+#define CE_REG_FI_SHT_INCR__A 0x1810090
+#define CE_REG_FI_EXP_NORM__A 0x1810091
+#define CE_REG_IR_INPUTSEL__A 0x18100A0
+#define CE_REG_IR_STARTPOS__A 0x18100A1
+#define CE_REG_IR_NEXP_THRES__A 0x18100A2
+#define CE_REG_FR_TREAL00__A 0x1820010
+#define CE_REG_FR_TIMAG00__A 0x1820011
+#define CE_REG_FR_TREAL01__A 0x1820012
+#define CE_REG_FR_TIMAG01__A 0x1820013
+#define CE_REG_FR_TREAL02__A 0x1820014
+#define CE_REG_FR_TIMAG02__A 0x1820015
+#define CE_REG_FR_TREAL03__A 0x1820016
+#define CE_REG_FR_TIMAG03__A 0x1820017
+#define CE_REG_FR_TREAL04__A 0x1820018
+#define CE_REG_FR_TIMAG04__A 0x1820019
+#define CE_REG_FR_TREAL05__A 0x182001A
+#define CE_REG_FR_TIMAG05__A 0x182001B
+#define CE_REG_FR_TREAL06__A 0x182001C
+#define CE_REG_FR_TIMAG06__A 0x182001D
+#define CE_REG_FR_TREAL07__A 0x182001E
+#define CE_REG_FR_TIMAG07__A 0x182001F
+#define CE_REG_FR_TREAL08__A 0x1820020
+#define CE_REG_FR_TIMAG08__A 0x1820021
+#define CE_REG_FR_TREAL09__A 0x1820022
+#define CE_REG_FR_TIMAG09__A 0x1820023
+#define CE_REG_FR_TREAL10__A 0x1820024
+#define CE_REG_FR_TIMAG10__A 0x1820025
+#define CE_REG_FR_TREAL11__A 0x1820026
+#define CE_REG_FR_TIMAG11__A 0x1820027
+#define CE_REG_FR_MID_TAP__A 0x1820028
+#define CE_REG_FR_SQS_G00__A 0x1820029
+#define CE_REG_FR_SQS_G01__A 0x182002A
+#define CE_REG_FR_SQS_G02__A 0x182002B
+#define CE_REG_FR_SQS_G03__A 0x182002C
+#define CE_REG_FR_SQS_G04__A 0x182002D
+#define CE_REG_FR_SQS_G05__A 0x182002E
+#define CE_REG_FR_SQS_G06__A 0x182002F
+#define CE_REG_FR_SQS_G07__A 0x1820030
+#define CE_REG_FR_SQS_G08__A 0x1820031
+#define CE_REG_FR_SQS_G09__A 0x1820032
+#define CE_REG_FR_SQS_G10__A 0x1820033
+#define CE_REG_FR_SQS_G11__A 0x1820034
+#define CE_REG_FR_SQS_G12__A 0x1820035
+#define CE_REG_FR_RIO_G00__A 0x1820036
+#define CE_REG_FR_RIO_G01__A 0x1820037
+#define CE_REG_FR_RIO_G02__A 0x1820038
+#define CE_REG_FR_RIO_G03__A 0x1820039
+#define CE_REG_FR_RIO_G04__A 0x182003A
+#define CE_REG_FR_RIO_G05__A 0x182003B
+#define CE_REG_FR_RIO_G06__A 0x182003C
+#define CE_REG_FR_RIO_G07__A 0x182003D
+#define CE_REG_FR_RIO_G08__A 0x182003E
+#define CE_REG_FR_RIO_G09__A 0x182003F
+#define CE_REG_FR_RIO_G10__A 0x1820040
+#define CE_REG_FR_MODE__A 0x1820041
+#define CE_REG_FR_SQS_TRH__A 0x1820042
+#define CE_REG_FR_RIO_GAIN__A 0x1820043
+#define CE_REG_FR_BYPASS__A 0x1820044
+#define CE_REG_FR_PM_SET__A 0x1820045
+#define CE_REG_FR_ERR_SH__A 0x1820046
+#define CE_REG_FR_MAN_SH__A 0x1820047
+#define CE_REG_FR_TAP_SH__A 0x1820048
+#define EQ_COMM_EXEC__A 0x1C00000
+#define EQ_REG_COMM_EXEC__A 0x1C10000
+#define EQ_REG_COMM_MB__A 0x1C10002
+#define EQ_REG_IS_GAIN_MAN__A 0x1C10015
+#define EQ_REG_IS_GAIN_EXP__A 0x1C10016
+#define EQ_REG_IS_CLIP_EXP__A 0x1C10017
+#define EQ_REG_SN_CEGAIN__A 0x1C1002A
+#define EQ_REG_SN_OFFSET__A 0x1C1002B
+#define EQ_REG_RC_SEL_CAR__A 0x1C10032
+#define EQ_REG_RC_SEL_CAR_INIT 0x0
+#define EQ_REG_RC_SEL_CAR_DIV_ON 0x1
+#define EQ_REG_RC_SEL_CAR_PASS_A_CC 0x0
+#define EQ_REG_RC_SEL_CAR_PASS_B_CE 0x2
+#define EQ_REG_RC_SEL_CAR_LOCAL_A_CC 0x0
+#define EQ_REG_RC_SEL_CAR_LOCAL_B_CE 0x8
+#define EQ_REG_RC_SEL_CAR_MEAS_A_CC 0x0
+#define EQ_REG_RC_SEL_CAR_MEAS_B_CE 0x20
+#define EQ_REG_OT_CONST__A 0x1C10046
+#define EQ_REG_OT_ALPHA__A 0x1C10047
+#define EQ_REG_OT_QNT_THRES0__A 0x1C10048
+#define EQ_REG_OT_QNT_THRES1__A 0x1C10049
+#define EQ_REG_OT_CSI_STEP__A 0x1C1004A
+#define EQ_REG_OT_CSI_OFFSET__A 0x1C1004B
+#define EQ_REG_TD_REQ_SMB_CNT__A 0x1C10061
+#define EQ_REG_TD_TPS_PWR_OFS__A 0x1C10062
+#define EC_SB_REG_COMM_EXEC__A 0x2010000
+#define EC_SB_REG_TR_MODE__A 0x2010010
+#define EC_SB_REG_TR_MODE_8K 0x0
+#define EC_SB_REG_TR_MODE_2K 0x1
+#define EC_SB_REG_CONST__A 0x2010011
+#define EC_SB_REG_CONST_QPSK 0x0
+#define EC_SB_REG_CONST_16QAM 0x1
+#define EC_SB_REG_CONST_64QAM 0x2
+#define EC_SB_REG_ALPHA__A 0x2010012
+#define EC_SB_REG_PRIOR__A 0x2010013
+#define EC_SB_REG_PRIOR_HI 0x0
+#define EC_SB_REG_PRIOR_LO 0x1
+#define EC_SB_REG_CSI_HI__A 0x2010014
+#define EC_SB_REG_CSI_LO__A 0x2010015
+#define EC_SB_REG_SMB_TGL__A 0x2010016
+#define EC_SB_REG_SNR_HI__A 0x2010017
+#define EC_SB_REG_SNR_MID__A 0x2010018
+#define EC_SB_REG_SNR_LO__A 0x2010019
+#define EC_SB_REG_SCALE_MSB__A 0x201001A
+#define EC_SB_REG_SCALE_BIT2__A 0x201001B
+#define EC_SB_REG_SCALE_LSB__A 0x201001C
+#define EC_SB_REG_CSI_OFS__A 0x201001D
+#define EC_VD_REG_COMM_EXEC__A 0x2090000
+#define EC_VD_REG_FORCE__A 0x2090010
+#define EC_VD_REG_SET_CODERATE__A 0x2090011
+#define EC_VD_REG_SET_CODERATE_C1_2 0x0
+#define EC_VD_REG_SET_CODERATE_C2_3 0x1
+#define EC_VD_REG_SET_CODERATE_C3_4 0x2
+#define EC_VD_REG_SET_CODERATE_C5_6 0x3
+#define EC_VD_REG_SET_CODERATE_C7_8 0x4
+#define EC_VD_REG_REQ_SMB_CNT__A 0x2090012
+#define EC_VD_REG_RLK_ENA__A 0x2090014
+#define EC_OD_REG_COMM_EXEC__A 0x2110000
+#define EC_OD_REG_SYNC__A 0x2110010
+#define EC_OD_DEINT_RAM__A 0x2120000
+#define EC_RS_REG_COMM_EXEC__A 0x2130000
+#define EC_RS_REG_REQ_PCK_CNT__A 0x2130010
+#define EC_RS_REG_VAL__A 0x2130011
+#define EC_RS_REG_VAL_PCK 0x1
+#define EC_RS_EC_RAM__A 0x2140000
+#define EC_OC_REG_COMM_EXEC__A 0x2150000
+#define EC_OC_REG_COMM_EXEC_CTL_ACTIVE 0x1
+#define EC_OC_REG_COMM_EXEC_CTL_HOLD 0x2
+#define EC_OC_REG_COMM_INT_STA__A 0x2150007
+#define EC_OC_REG_OC_MODE_LOP__A 0x2150010
+#define EC_OC_REG_OC_MODE_LOP_PAR_ENA__M 0x1
+#define EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE 0x0
+#define EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE 0x1
+#define EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M 0x4
+#define EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC 0x0
+#define EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__M 0x80
+#define EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_SERIAL 0x80
+#define EC_OC_REG_OC_MODE_HIP__A 0x2150011
+#define EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR 0x10
+#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M 0x200
+#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_DISABLE 0x0
+#define EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_ENABLE 0x200
+#define EC_OC_REG_OC_MPG_SIO__A 0x2150012
+#define EC_OC_REG_OC_MPG_SIO__M 0xFFF
+#define EC_OC_REG_OC_MON_SIO__A 0x2150013
+#define EC_OC_REG_DTO_INC_LOP__A 0x2150014
+#define EC_OC_REG_DTO_INC_HIP__A 0x2150015
+#define EC_OC_REG_SNC_ISC_LVL__A 0x2150016
+#define EC_OC_REG_SNC_ISC_LVL_OSC__M 0xF0
+#define EC_OC_REG_TMD_TOP_MODE__A 0x215001D
+#define EC_OC_REG_TMD_TOP_CNT__A 0x215001E
+#define EC_OC_REG_TMD_HIL_MAR__A 0x215001F
+#define EC_OC_REG_TMD_LOL_MAR__A 0x2150020
+#define EC_OC_REG_TMD_CUR_CNT__A 0x2150021
+#define EC_OC_REG_AVR_ASH_CNT__A 0x2150023
+#define EC_OC_REG_AVR_BSH_CNT__A 0x2150024
+#define EC_OC_REG_RCN_MODE__A 0x2150027
+#define EC_OC_REG_RCN_CRA_LOP__A 0x2150028
+#define EC_OC_REG_RCN_CRA_HIP__A 0x2150029
+#define EC_OC_REG_RCN_CST_LOP__A 0x215002A
+#define EC_OC_REG_RCN_CST_HIP__A 0x215002B
+#define EC_OC_REG_RCN_SET_LVL__A 0x215002C
+#define EC_OC_REG_RCN_GAI_LVL__A 0x215002D
+#define EC_OC_REG_RCN_CLP_LOP__A 0x2150032
+#define EC_OC_REG_RCN_CLP_HIP__A 0x2150033
+#define EC_OC_REG_RCN_MAP_LOP__A 0x2150034
+#define EC_OC_REG_RCN_MAP_HIP__A 0x2150035
+#define EC_OC_REG_OCR_MPG_UOS__A 0x2150036
+#define EC_OC_REG_OCR_MPG_UOS__M 0xFFF
+#define EC_OC_REG_OCR_MPG_UOS_INIT 0x0
+#define EC_OC_REG_OCR_MPG_USR_DAT__A 0x2150038
+#define EC_OC_REG_OCR_MON_UOS__A 0x2150039
+#define EC_OC_REG_OCR_MON_UOS_DAT_0_ENABLE 0x1
+#define EC_OC_REG_OCR_MON_UOS_DAT_1_ENABLE 0x2
+#define EC_OC_REG_OCR_MON_UOS_DAT_2_ENABLE 0x4
+#define EC_OC_REG_OCR_MON_UOS_DAT_3_ENABLE 0x8
+#define EC_OC_REG_OCR_MON_UOS_DAT_4_ENABLE 0x10
+#define EC_OC_REG_OCR_MON_UOS_DAT_5_ENABLE 0x20
+#define EC_OC_REG_OCR_MON_UOS_DAT_6_ENABLE 0x40
+#define EC_OC_REG_OCR_MON_UOS_DAT_7_ENABLE 0x80
+#define EC_OC_REG_OCR_MON_UOS_DAT_8_ENABLE 0x100
+#define EC_OC_REG_OCR_MON_UOS_DAT_9_ENABLE 0x200
+#define EC_OC_REG_OCR_MON_UOS_VAL_ENABLE 0x400
+#define EC_OC_REG_OCR_MON_UOS_CLK_ENABLE 0x800
+#define EC_OC_REG_OCR_MON_WRI__A 0x215003A
+#define EC_OC_REG_OCR_MON_WRI_INIT 0x0
+#define EC_OC_REG_IPR_INV_MPG__A 0x2150045
+#define CC_REG_OSC_MODE__A 0x2410010
+#define CC_REG_OSC_MODE_M20 0x1
+#define CC_REG_PLL_MODE__A 0x2410011
+#define CC_REG_PLL_MODE_BYPASS_PLL 0x1
+#define CC_REG_PLL_MODE_PUMP_CUR_12 0x14
+#define CC_REG_REF_DIVIDE__A 0x2410012
+#define CC_REG_PWD_MODE__A 0x2410015
+#define CC_REG_PWD_MODE_DOWN_PLL 0x2
+#define CC_REG_UPDATE__A 0x2410017
+#define CC_REG_UPDATE_KEY 0x3973
+#define CC_REG_JTAGID_L__A 0x2410019
+#define LC_COMM_EXEC__A 0x2800000
+#define LC_RA_RAM_IFINCR_NOM_L__A 0x282000C
+#define LC_RA_RAM_FILTER_SYM_SET__A 0x282001A
+#define LC_RA_RAM_FILTER_SYM_SET__PRE 0x3E8
+#define LC_RA_RAM_FILTER_CRMM_A__A 0x2820060
+#define LC_RA_RAM_FILTER_CRMM_A__PRE 0x4
+#define LC_RA_RAM_FILTER_CRMM_B__A 0x2820061
+#define LC_RA_RAM_FILTER_CRMM_B__PRE 0x1
+#define LC_RA_RAM_FILTER_SRMM_A__A 0x2820068
+#define LC_RA_RAM_FILTER_SRMM_A__PRE 0x4
+#define LC_RA_RAM_FILTER_SRMM_B__A 0x2820069
+#define LC_RA_RAM_FILTER_SRMM_B__PRE 0x1
+#define B_HI_COMM_EXEC__A 0x400000
+#define B_HI_COMM_MB__A 0x400002
+#define B_HI_CT_REG_COMM_STATE__A 0x410001
+#define B_HI_RA_RAM_SRV_RES__A 0x420031
+#define B_HI_RA_RAM_SRV_CMD__A 0x420032
+#define B_HI_RA_RAM_SRV_CMD_RESET 0x2
+#define B_HI_RA_RAM_SRV_CMD_CONFIG 0x3
+#define B_HI_RA_RAM_SRV_CMD_EXECUTE 0x6
+#define B_HI_RA_RAM_SRV_RST_KEY__A 0x420033
+#define B_HI_RA_RAM_SRV_RST_KEY_ACT 0x3973
+#define B_HI_RA_RAM_SRV_CFG_KEY__A 0x420033
+#define B_HI_RA_RAM_SRV_CFG_DIV__A 0x420034
+#define B_HI_RA_RAM_SRV_CFG_BDL__A 0x420035
+#define B_HI_RA_RAM_SRV_CFG_WUP__A 0x420036
+#define B_HI_RA_RAM_SRV_CFG_ACT__A 0x420037
+#define B_HI_RA_RAM_SRV_CFG_ACT_SLV0_ON 0x1
+#define B_HI_RA_RAM_SRV_CFG_ACT_BRD__M 0x4
+#define B_HI_RA_RAM_SRV_CFG_ACT_BRD_OFF 0x0
+#define B_HI_RA_RAM_SRV_CFG_ACT_BRD_ON 0x4
+#define B_HI_RA_RAM_SRV_CFG_ACT_PWD_EXE 0x8
+#define B_HI_RA_RAM_USR_BEGIN__A 0x420040
+#define B_HI_IF_RAM_TRP_BPT0__AX 0x430000
+#define B_HI_IF_RAM_USR_BEGIN__A 0x430200
+#define B_SC_COMM_EXEC__A 0x800000
+#define B_SC_COMM_EXEC_CTL_STOP 0x0
+#define B_SC_COMM_STATE__A 0x800001
+#define B_SC_RA_RAM_PARAM0__A 0x820040
+#define B_SC_RA_RAM_PARAM1__A 0x820041
+#define B_SC_RA_RAM_CMD_ADDR__A 0x820042
+#define B_SC_RA_RAM_CMD__A 0x820043
+#define B_SC_RA_RAM_CMD_PROC_START 0x1
+#define B_SC_RA_RAM_CMD_SET_PREF_PARAM 0x3
+#define B_SC_RA_RAM_CMD_GET_OP_PARAM 0x5
+#define B_SC_RA_RAM_SW_EVENT_RUN_NMASK__M 0x1
+#define B_SC_RA_RAM_LOCKTRACK_MIN 0x1
+#define B_SC_RA_RAM_OP_PARAM_MODE_2K 0x0
+#define B_SC_RA_RAM_OP_PARAM_MODE_8K 0x1
+#define B_SC_RA_RAM_OP_PARAM_GUARD_32 0x0
+#define B_SC_RA_RAM_OP_PARAM_GUARD_16 0x4
+#define B_SC_RA_RAM_OP_PARAM_GUARD_8 0x8
+#define B_SC_RA_RAM_OP_PARAM_GUARD_4 0xC
+#define B_SC_RA_RAM_OP_PARAM_CONST_QPSK 0x0
+#define B_SC_RA_RAM_OP_PARAM_CONST_QAM16 0x10
+#define B_SC_RA_RAM_OP_PARAM_CONST_QAM64 0x20
+#define B_SC_RA_RAM_OP_PARAM_HIER_NO 0x0
+#define B_SC_RA_RAM_OP_PARAM_HIER_A1 0x40
+#define B_SC_RA_RAM_OP_PARAM_HIER_A2 0x80
+#define B_SC_RA_RAM_OP_PARAM_HIER_A4 0xC0
+#define B_SC_RA_RAM_OP_PARAM_RATE_1_2 0x0
+#define B_SC_RA_RAM_OP_PARAM_RATE_2_3 0x200
+#define B_SC_RA_RAM_OP_PARAM_RATE_3_4 0x400
+#define B_SC_RA_RAM_OP_PARAM_RATE_5_6 0x600
+#define B_SC_RA_RAM_OP_PARAM_RATE_7_8 0x800
+#define B_SC_RA_RAM_OP_PARAM_PRIO_HI 0x0
+#define B_SC_RA_RAM_OP_PARAM_PRIO_LO 0x1000
+#define B_SC_RA_RAM_OP_AUTO_MODE__M 0x1
+#define B_SC_RA_RAM_OP_AUTO_GUARD__M 0x2
+#define B_SC_RA_RAM_OP_AUTO_CONST__M 0x4
+#define B_SC_RA_RAM_OP_AUTO_HIER__M 0x8
+#define B_SC_RA_RAM_OP_AUTO_RATE__M 0x10
+#define B_SC_RA_RAM_LOCK__A 0x82004B
+#define B_SC_RA_RAM_LOCK_DEMOD__M 0x1
+#define B_SC_RA_RAM_LOCK_FEC__M 0x2
+#define B_SC_RA_RAM_LOCK_MPEG__M 0x4
+#define B_SC_RA_RAM_BE_OPT_ENA__A 0x82004C
+#define B_SC_RA_RAM_BE_OPT_ENA_CP_OPT 0x1
+#define B_SC_RA_RAM_BE_OPT_DELAY__A 0x82004D
+#define B_SC_RA_RAM_CONFIG__A 0x820050
+#define B_SC_RA_RAM_CONFIG_FR_ENABLE__M 0x4
+#define B_SC_RA_RAM_CONFIG_FREQSCAN__M 0x10
+#define B_SC_RA_RAM_CONFIG_SLAVE__M 0x20
+#define B_SC_RA_RAM_CONFIG_DIV_BLANK_ENABLE__M 0x200
+#define B_SC_RA_RAM_CONFIG_DIV_ECHO_ENABLE__M 0x400
+#define B_SC_RA_RAM_CO_TD_CAL_2K__A 0x82005D
+#define B_SC_RA_RAM_CO_TD_CAL_8K__A 0x82005E
+#define B_SC_RA_RAM_IF_SAVE__AX 0x82008E
+#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_32__A 0x820098
+#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_16__A 0x820099
+#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_8__A 0x82009A
+#define B_SC_RA_RAM_DIVERSITY_DELAY_2K_4__A 0x82009B
+#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_32__A 0x82009C
+#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_16__A 0x82009D
+#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_8__A 0x82009E
+#define B_SC_RA_RAM_DIVERSITY_DELAY_8K_4__A 0x82009F
+#define B_SC_RA_RAM_IR_COARSE_2K_LENGTH__A 0x8200D1
+#define B_SC_RA_RAM_IR_COARSE_2K_LENGTH__PRE 0x9
+#define B_SC_RA_RAM_IR_COARSE_2K_FREQINC__A 0x8200D2
+#define B_SC_RA_RAM_IR_COARSE_2K_FREQINC__PRE 0x4
+#define B_SC_RA_RAM_IR_COARSE_2K_KAISINC__A 0x8200D3
+#define B_SC_RA_RAM_IR_COARSE_2K_KAISINC__PRE 0x100
+#define B_SC_RA_RAM_IR_COARSE_8K_LENGTH__A 0x8200D4
+#define B_SC_RA_RAM_IR_COARSE_8K_LENGTH__PRE 0x8
+#define B_SC_RA_RAM_IR_COARSE_8K_FREQINC__A 0x8200D5
+#define B_SC_RA_RAM_IR_COARSE_8K_FREQINC__PRE 0x8
+#define B_SC_RA_RAM_IR_COARSE_8K_KAISINC__A 0x8200D6
+#define B_SC_RA_RAM_IR_COARSE_8K_KAISINC__PRE 0x200
+#define B_SC_RA_RAM_IR_FINE_2K_LENGTH__A 0x8200D7
+#define B_SC_RA_RAM_IR_FINE_2K_LENGTH__PRE 0x9
+#define B_SC_RA_RAM_IR_FINE_2K_FREQINC__A 0x8200D8
+#define B_SC_RA_RAM_IR_FINE_2K_FREQINC__PRE 0x4
+#define B_SC_RA_RAM_IR_FINE_2K_KAISINC__A 0x8200D9
+#define B_SC_RA_RAM_IR_FINE_2K_KAISINC__PRE 0x100
+#define B_SC_RA_RAM_IR_FINE_8K_LENGTH__A 0x8200DA
+#define B_SC_RA_RAM_IR_FINE_8K_LENGTH__PRE 0xB
+#define B_SC_RA_RAM_IR_FINE_8K_FREQINC__A 0x8200DB
+#define B_SC_RA_RAM_IR_FINE_8K_FREQINC__PRE 0x1
+#define B_SC_RA_RAM_IR_FINE_8K_KAISINC__A 0x8200DC
+#define B_SC_RA_RAM_IR_FINE_8K_KAISINC__PRE 0x40
+#define B_SC_RA_RAM_ECHO_SHIFT_LIM__A 0x8200DD
+#define B_SC_RA_RAM_SAMPLE_RATE_COUNT__A 0x8200E8
+#define B_SC_RA_RAM_SAMPLE_RATE_STEP__A 0x8200E9
+#define B_SC_RA_RAM_BAND__A 0x8200EC
+#define B_SC_RA_RAM_LC_ABS_2K__A 0x8200F4
+#define B_SC_RA_RAM_LC_ABS_2K__PRE 0x1F
+#define B_SC_RA_RAM_LC_ABS_8K__A 0x8200F5
+#define B_SC_RA_RAM_LC_ABS_8K__PRE 0x1F
+#define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_MAN__PRE 0x100
+#define B_SC_RA_RAM_EQ_IS_GAIN_UNKNOWN_EXP__PRE 0x4
+#define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_MAN__PRE 0x1E2
+#define B_SC_RA_RAM_EQ_IS_GAIN_QPSK_EXP__PRE 0x4
+#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_MAN__PRE 0x10D
+#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_EXP__PRE 0x5
+#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_MAN__PRE 0x17D
+#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A2_EXP__PRE 0x4
+#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_MAN__PRE 0x133
+#define B_SC_RA_RAM_EQ_IS_GAIN_16QAM_A4_EXP__PRE 0x5
+#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_MAN__PRE 0x114
+#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_EXP__PRE 0x5
+#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_MAN__PRE 0x14A
+#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A2_EXP__PRE 0x4
+#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_MAN__PRE 0x1BB
+#define B_SC_RA_RAM_EQ_IS_GAIN_64QAM_A4_EXP__PRE 0x4
+#define B_SC_RA_RAM_DRIVER_VERSION__AX 0x8201FE
+#define B_SC_RA_RAM_PROC_LOCKTRACK 0x0
+#define B_FE_COMM_EXEC__A 0xC00000
+#define B_FE_AD_REG_COMM_EXEC__A 0xC10000
+#define B_FE_AD_REG_FDB_IN__A 0xC10012
+#define B_FE_AD_REG_PD__A 0xC10013
+#define B_FE_AD_REG_INVEXT__A 0xC10014
+#define B_FE_AD_REG_CLKNEG__A 0xC10015
+#define B_FE_AG_REG_COMM_EXEC__A 0xC20000
+#define B_FE_AG_REG_AG_MODE_LOP__A 0xC20010
+#define B_FE_AG_REG_AG_MODE_LOP_MODE_4__M 0x10
+#define B_FE_AG_REG_AG_MODE_LOP_MODE_4_STATIC 0x0
+#define B_FE_AG_REG_AG_MODE_LOP_MODE_4_DYNAMIC 0x10
+#define B_FE_AG_REG_AG_MODE_LOP_MODE_5__M 0x20
+#define B_FE_AG_REG_AG_MODE_LOP_MODE_5_STATIC 0x0
+#define B_FE_AG_REG_AG_MODE_LOP_MODE_C__M 0x1000
+#define B_FE_AG_REG_AG_MODE_LOP_MODE_C_STATIC 0x0
+#define B_FE_AG_REG_AG_MODE_LOP_MODE_C_DYNAMIC 0x1000
+#define B_FE_AG_REG_AG_MODE_LOP_MODE_E__M 0x4000
+#define B_FE_AG_REG_AG_MODE_LOP_MODE_E_STATIC 0x0
+#define B_FE_AG_REG_AG_MODE_LOP_MODE_E_DYNAMIC 0x4000
+#define B_FE_AG_REG_AG_MODE_HIP__A 0xC20011
+#define B_FE_AG_REG_AG_MODE_HIP_MODE_J__M 0x8
+#define B_FE_AG_REG_AG_MODE_HIP_MODE_J_STATIC 0x0
+#define B_FE_AG_REG_AG_MODE_HIP_MODE_J_DYNAMIC 0x8
+#define B_FE_AG_REG_AG_PGA_MODE__A 0xC20012
+#define B_FE_AG_REG_AG_PGA_MODE_PFY_PCY_AFY_REN 0x0
+#define B_FE_AG_REG_AG_PGA_MODE_PFN_PCN_AFY_REN 0x1
+#define B_FE_AG_REG_AG_AGC_SIO__A 0xC20013
+#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2__M 0x2
+#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_OUTPUT 0x0
+#define B_FE_AG_REG_AG_AGC_SIO_AGC_SIO_2_INPUT 0x2
+#define B_FE_AG_REG_AG_PWD__A 0xC20015
+#define B_FE_AG_REG_AG_PWD_PWD_PD2__M 0x2
+#define B_FE_AG_REG_AG_PWD_PWD_PD2_DISABLE 0x0
+#define B_FE_AG_REG_AG_PWD_PWD_PD2_ENABLE 0x2
+#define B_FE_AG_REG_DCE_AUR_CNT__A 0xC20016
+#define B_FE_AG_REG_DCE_RUR_CNT__A 0xC20017
+#define B_FE_AG_REG_ACE_AUR_CNT__A 0xC2001A
+#define B_FE_AG_REG_ACE_RUR_CNT__A 0xC2001B
+#define B_FE_AG_REG_CDR_RUR_CNT__A 0xC20020
+#define B_FE_AG_REG_EGC_RUR_CNT__A 0xC20024
+#define B_FE_AG_REG_EGC_SET_LVL__A 0xC20025
+#define B_FE_AG_REG_EGC_SET_LVL__M 0x1FF
+#define B_FE_AG_REG_EGC_FLA_RGN__A 0xC20026
+#define B_FE_AG_REG_EGC_SLO_RGN__A 0xC20027
+#define B_FE_AG_REG_EGC_JMP_PSN__A 0xC20028
+#define B_FE_AG_REG_EGC_FLA_INC__A 0xC20029
+#define B_FE_AG_REG_EGC_FLA_DEC__A 0xC2002A
+#define B_FE_AG_REG_EGC_SLO_INC__A 0xC2002B
+#define B_FE_AG_REG_EGC_SLO_DEC__A 0xC2002C
+#define B_FE_AG_REG_EGC_FAS_INC__A 0xC2002D
+#define B_FE_AG_REG_EGC_FAS_DEC__A 0xC2002E
+#define B_FE_AG_REG_PM1_AGC_WRI__A 0xC20030
+#define B_FE_AG_REG_PM1_AGC_WRI__M 0x7FF
+#define B_FE_AG_REG_GC1_AGC_RIC__A 0xC20031
+#define B_FE_AG_REG_GC1_AGC_OFF__A 0xC20032
+#define B_FE_AG_REG_GC1_AGC_MAX__A 0xC20033
+#define B_FE_AG_REG_GC1_AGC_MIN__A 0xC20034
+#define B_FE_AG_REG_GC1_AGC_DAT__A 0xC20035
+#define B_FE_AG_REG_GC1_AGC_DAT__M 0x3FF
+#define B_FE_AG_REG_PM2_AGC_WRI__A 0xC20036
+#define B_FE_AG_REG_IND_WIN__A 0xC2003C
+#define B_FE_AG_REG_IND_THD_LOL__A 0xC2003D
+#define B_FE_AG_REG_IND_THD_HIL__A 0xC2003E
+#define B_FE_AG_REG_IND_DEL__A 0xC2003F
+#define B_FE_AG_REG_IND_PD1_WRI__A 0xC20040
+#define B_FE_AG_REG_PDA_AUR_CNT__A 0xC20041
+#define B_FE_AG_REG_PDA_RUR_CNT__A 0xC20042
+#define B_FE_AG_REG_PDA_AVE_DAT__A 0xC20043
+#define B_FE_AG_REG_PDC_RUR_CNT__A 0xC20044
+#define B_FE_AG_REG_PDC_SET_LVL__A 0xC20045
+#define B_FE_AG_REG_PDC_FLA_RGN__A 0xC20046
+#define B_FE_AG_REG_PDC_JMP_PSN__A 0xC20047
+#define B_FE_AG_REG_PDC_FLA_STP__A 0xC20048
+#define B_FE_AG_REG_PDC_SLO_STP__A 0xC20049
+#define B_FE_AG_REG_PDC_PD2_WRI__A 0xC2004A
+#define B_FE_AG_REG_PDC_MAP_DAT__A 0xC2004B
+#define B_FE_AG_REG_PDC_MAX__A 0xC2004C
+#define B_FE_AG_REG_TGA_AUR_CNT__A 0xC2004D
+#define B_FE_AG_REG_TGA_RUR_CNT__A 0xC2004E
+#define B_FE_AG_REG_TGA_AVE_DAT__A 0xC2004F
+#define B_FE_AG_REG_TGC_RUR_CNT__A 0xC20050
+#define B_FE_AG_REG_TGC_SET_LVL__A 0xC20051
+#define B_FE_AG_REG_TGC_SET_LVL__M 0x3F
+#define B_FE_AG_REG_TGC_FLA_RGN__A 0xC20052
+#define B_FE_AG_REG_TGC_JMP_PSN__A 0xC20053
+#define B_FE_AG_REG_TGC_FLA_STP__A 0xC20054
+#define B_FE_AG_REG_TGC_SLO_STP__A 0xC20055
+#define B_FE_AG_REG_TGC_MAP_DAT__A 0xC20056
+#define B_FE_AG_REG_FGM_WRI__A 0xC20061
+#define B_FE_AG_REG_BGC_FGC_WRI__A 0xC20068
+#define B_FE_AG_REG_BGC_CGC_WRI__A 0xC20069
+#define B_FE_FS_REG_COMM_EXEC__A 0xC30000
+#define B_FE_FS_REG_ADD_INC_LOP__A 0xC30010
+#define B_FE_FD_REG_COMM_EXEC__A 0xC40000
+#define B_FE_FD_REG_SCL__A 0xC40010
+#define B_FE_FD_REG_MAX_LEV__A 0xC40011
+#define B_FE_FD_REG_NR__A 0xC40012
+#define B_FE_FD_REG_MEAS_VAL__A 0xC40014
+#define B_FE_IF_REG_COMM_EXEC__A 0xC50000
+#define B_FE_IF_REG_INCR0__A 0xC50010
+#define B_FE_IF_REG_INCR0__W 16
+#define B_FE_IF_REG_INCR0__M 0xFFFF
+#define B_FE_IF_REG_INCR1__A 0xC50011
+#define B_FE_IF_REG_INCR1__M 0xFF
+#define B_FE_CF_REG_COMM_EXEC__A 0xC60000
+#define B_FE_CF_REG_SCL__A 0xC60010
+#define B_FE_CF_REG_MAX_LEV__A 0xC60011
+#define B_FE_CF_REG_NR__A 0xC60012
+#define B_FE_CF_REG_IMP_VAL__A 0xC60013
+#define B_FE_CF_REG_MEAS_VAL__A 0xC60014
+#define B_FE_CU_REG_COMM_EXEC__A 0xC70000
+#define B_FE_CU_REG_FRM_CNT_RST__A 0xC70011
+#define B_FE_CU_REG_FRM_CNT_STR__A 0xC70012
+#define B_FE_CU_REG_CTR_NFC_ICR__A 0xC70020
+#define B_FE_CU_REG_CTR_NFC_OCR__A 0xC70021
+#define B_FE_CU_REG_DIV_NFC_CLP__A 0xC70027
+#define B_FT_COMM_EXEC__A 0x1000000
+#define B_FT_REG_COMM_EXEC__A 0x1010000
+#define B_CP_COMM_EXEC__A 0x1400000
+#define B_CP_REG_COMM_EXEC__A 0x1410000
+#define B_CP_REG_INTERVAL__A 0x1410011
+#define B_CP_REG_BR_SPL_OFFSET__A 0x1410023
+#define B_CP_REG_BR_STR_DEL__A 0x1410024
+#define B_CP_REG_RT_ANG_INC0__A 0x1410030
+#define B_CP_REG_RT_ANG_INC1__A 0x1410031
+#define B_CP_REG_RT_DETECT_TRH__A 0x1410033
+#define B_CP_REG_AC_NEXP_OFFS__A 0x1410040
+#define B_CP_REG_AC_AVER_POW__A 0x1410041
+#define B_CP_REG_AC_MAX_POW__A 0x1410042
+#define B_CP_REG_AC_WEIGHT_MAN__A 0x1410043
+#define B_CP_REG_AC_WEIGHT_EXP__A 0x1410044
+#define B_CP_REG_AC_AMP_MODE__A 0x1410047
+#define B_CP_REG_AC_AMP_FIX__A 0x1410048
+#define B_CP_REG_AC_ANG_MODE__A 0x141004A
+#define B_CE_COMM_EXEC__A 0x1800000
+#define B_CE_REG_COMM_EXEC__A 0x1810000
+#define B_CE_REG_TAPSET__A 0x1810011
+#define B_CE_REG_AVG_POW__A 0x1810012
+#define B_CE_REG_MAX_POW__A 0x1810013
+#define B_CE_REG_ATT__A 0x1810014
+#define B_CE_REG_NRED__A 0x1810015
+#define B_CE_REG_NE_ERR_SELECT__A 0x1810043
+#define B_CE_REG_NE_TD_CAL__A 0x1810044
+#define B_CE_REG_NE_MIXAVG__A 0x1810046
+#define B_CE_REG_NE_NUPD_OFS__A 0x1810047
+#define B_CE_REG_PE_NEXP_OFFS__A 0x1810050
+#define B_CE_REG_PE_TIMESHIFT__A 0x1810051
+#define B_CE_REG_TP_A0_TAP_NEW__A 0x1810064
+#define B_CE_REG_TP_A0_TAP_NEW_VALID__A 0x1810065
+#define B_CE_REG_TP_A0_MU_LMS_STEP__A 0x1810066
+#define B_CE_REG_TP_A1_TAP_NEW__A 0x1810068
+#define B_CE_REG_TP_A1_TAP_NEW_VALID__A 0x1810069
+#define B_CE_REG_TP_A1_MU_LMS_STEP__A 0x181006A
+#define B_CE_REG_TI_PHN_ENABLE__A 0x1810073
+#define B_CE_REG_FI_SHT_INCR__A 0x1810090
+#define B_CE_REG_FI_EXP_NORM__A 0x1810091
+#define B_CE_REG_IR_INPUTSEL__A 0x18100A0
+#define B_CE_REG_IR_STARTPOS__A 0x18100A1
+#define B_CE_REG_IR_NEXP_THRES__A 0x18100A2
+#define B_CE_REG_FR_TREAL00__A 0x1820010
+#define B_CE_REG_FR_TIMAG00__A 0x1820011
+#define B_CE_REG_FR_TREAL01__A 0x1820012
+#define B_CE_REG_FR_TIMAG01__A 0x1820013
+#define B_CE_REG_FR_TREAL02__A 0x1820014
+#define B_CE_REG_FR_TIMAG02__A 0x1820015
+#define B_CE_REG_FR_TREAL03__A 0x1820016
+#define B_CE_REG_FR_TIMAG03__A 0x1820017
+#define B_CE_REG_FR_TREAL04__A 0x1820018
+#define B_CE_REG_FR_TIMAG04__A 0x1820019
+#define B_CE_REG_FR_TREAL05__A 0x182001A
+#define B_CE_REG_FR_TIMAG05__A 0x182001B
+#define B_CE_REG_FR_TREAL06__A 0x182001C
+#define B_CE_REG_FR_TIMAG06__A 0x182001D
+#define B_CE_REG_FR_TREAL07__A 0x182001E
+#define B_CE_REG_FR_TIMAG07__A 0x182001F
+#define B_CE_REG_FR_TREAL08__A 0x1820020
+#define B_CE_REG_FR_TIMAG08__A 0x1820021
+#define B_CE_REG_FR_TREAL09__A 0x1820022
+#define B_CE_REG_FR_TIMAG09__A 0x1820023
+#define B_CE_REG_FR_TREAL10__A 0x1820024
+#define B_CE_REG_FR_TIMAG10__A 0x1820025
+#define B_CE_REG_FR_TREAL11__A 0x1820026
+#define B_CE_REG_FR_TIMAG11__A 0x1820027
+#define B_CE_REG_FR_MID_TAP__A 0x1820028
+#define B_CE_REG_FR_SQS_G00__A 0x1820029
+#define B_CE_REG_FR_SQS_G01__A 0x182002A
+#define B_CE_REG_FR_SQS_G02__A 0x182002B
+#define B_CE_REG_FR_SQS_G03__A 0x182002C
+#define B_CE_REG_FR_SQS_G04__A 0x182002D
+#define B_CE_REG_FR_SQS_G05__A 0x182002E
+#define B_CE_REG_FR_SQS_G06__A 0x182002F
+#define B_CE_REG_FR_SQS_G07__A 0x1820030
+#define B_CE_REG_FR_SQS_G08__A 0x1820031
+#define B_CE_REG_FR_SQS_G09__A 0x1820032
+#define B_CE_REG_FR_SQS_G10__A 0x1820033
+#define B_CE_REG_FR_SQS_G11__A 0x1820034
+#define B_CE_REG_FR_SQS_G12__A 0x1820035
+#define B_CE_REG_FR_RIO_G00__A 0x1820036
+#define B_CE_REG_FR_RIO_G01__A 0x1820037
+#define B_CE_REG_FR_RIO_G02__A 0x1820038
+#define B_CE_REG_FR_RIO_G03__A 0x1820039
+#define B_CE_REG_FR_RIO_G04__A 0x182003A
+#define B_CE_REG_FR_RIO_G05__A 0x182003B
+#define B_CE_REG_FR_RIO_G06__A 0x182003C
+#define B_CE_REG_FR_RIO_G07__A 0x182003D
+#define B_CE_REG_FR_RIO_G08__A 0x182003E
+#define B_CE_REG_FR_RIO_G09__A 0x182003F
+#define B_CE_REG_FR_RIO_G10__A 0x1820040
+#define B_CE_REG_FR_MODE__A 0x1820041
+#define B_CE_REG_FR_SQS_TRH__A 0x1820042
+#define B_CE_REG_FR_RIO_GAIN__A 0x1820043
+#define B_CE_REG_FR_BYPASS__A 0x1820044
+#define B_CE_REG_FR_PM_SET__A 0x1820045
+#define B_CE_REG_FR_ERR_SH__A 0x1820046
+#define B_CE_REG_FR_MAN_SH__A 0x1820047
+#define B_CE_REG_FR_TAP_SH__A 0x1820048
+#define B_EQ_COMM_EXEC__A 0x1C00000
+#define B_EQ_REG_COMM_EXEC__A 0x1C10000
+#define B_EQ_REG_COMM_MB__A 0x1C10002
+#define B_EQ_REG_IS_GAIN_MAN__A 0x1C10015
+#define B_EQ_REG_IS_GAIN_EXP__A 0x1C10016
+#define B_EQ_REG_IS_CLIP_EXP__A 0x1C10017
+#define B_EQ_REG_SN_CEGAIN__A 0x1C1002A
+#define B_EQ_REG_SN_OFFSET__A 0x1C1002B
+#define B_EQ_REG_RC_SEL_CAR__A 0x1C10032
+#define B_EQ_REG_RC_SEL_CAR_INIT 0x2
+#define B_EQ_REG_RC_SEL_CAR_DIV_ON 0x1
+#define B_EQ_REG_RC_SEL_CAR_PASS_A_CC 0x0
+#define B_EQ_REG_RC_SEL_CAR_PASS_B_CE 0x2
+#define B_EQ_REG_RC_SEL_CAR_LOCAL_A_CC 0x0
+#define B_EQ_REG_RC_SEL_CAR_LOCAL_B_CE 0x8
+#define B_EQ_REG_RC_SEL_CAR_MEAS_A_CC 0x0
+#define B_EQ_REG_RC_SEL_CAR_MEAS_B_CE 0x20
+#define B_EQ_REG_RC_SEL_CAR_FFTMODE__M 0x80
+#define B_EQ_REG_OT_CONST__A 0x1C10046
+#define B_EQ_REG_OT_ALPHA__A 0x1C10047
+#define B_EQ_REG_OT_QNT_THRES0__A 0x1C10048
+#define B_EQ_REG_OT_QNT_THRES1__A 0x1C10049
+#define B_EQ_REG_OT_CSI_STEP__A 0x1C1004A
+#define B_EQ_REG_OT_CSI_OFFSET__A 0x1C1004B
+#define B_EQ_REG_TD_REQ_SMB_CNT__A 0x1C10061
+#define B_EQ_REG_TD_TPS_PWR_OFS__A 0x1C10062
+#define B_EC_SB_REG_COMM_EXEC__A 0x2010000
+#define B_EC_SB_REG_TR_MODE__A 0x2010010
+#define B_EC_SB_REG_TR_MODE_8K 0x0
+#define B_EC_SB_REG_TR_MODE_2K 0x1
+#define B_EC_SB_REG_CONST__A 0x2010011
+#define B_EC_SB_REG_CONST_QPSK 0x0
+#define B_EC_SB_REG_CONST_16QAM 0x1
+#define B_EC_SB_REG_CONST_64QAM 0x2
+#define B_EC_SB_REG_ALPHA__A 0x2010012
+#define B_EC_SB_REG_PRIOR__A 0x2010013
+#define B_EC_SB_REG_PRIOR_HI 0x0
+#define B_EC_SB_REG_PRIOR_LO 0x1
+#define B_EC_SB_REG_CSI_HI__A 0x2010014
+#define B_EC_SB_REG_CSI_LO__A 0x2010015
+#define B_EC_SB_REG_SMB_TGL__A 0x2010016
+#define B_EC_SB_REG_SNR_HI__A 0x2010017
+#define B_EC_SB_REG_SNR_MID__A 0x2010018
+#define B_EC_SB_REG_SNR_LO__A 0x2010019
+#define B_EC_SB_REG_SCALE_MSB__A 0x201001A
+#define B_EC_SB_REG_SCALE_BIT2__A 0x201001B
+#define B_EC_SB_REG_SCALE_LSB__A 0x201001C
+#define B_EC_SB_REG_CSI_OFS0__A 0x201001D
+#define B_EC_SB_REG_CSI_OFS1__A 0x201001E
+#define B_EC_SB_REG_CSI_OFS2__A 0x201001F
+#define B_EC_VD_REG_COMM_EXEC__A 0x2090000
+#define B_EC_VD_REG_FORCE__A 0x2090010
+#define B_EC_VD_REG_SET_CODERATE__A 0x2090011
+#define B_EC_VD_REG_SET_CODERATE_C1_2 0x0
+#define B_EC_VD_REG_SET_CODERATE_C2_3 0x1
+#define B_EC_VD_REG_SET_CODERATE_C3_4 0x2
+#define B_EC_VD_REG_SET_CODERATE_C5_6 0x3
+#define B_EC_VD_REG_SET_CODERATE_C7_8 0x4
+#define B_EC_VD_REG_REQ_SMB_CNT__A 0x2090012
+#define B_EC_VD_REG_RLK_ENA__A 0x2090014
+#define B_EC_OD_REG_COMM_EXEC__A 0x2110000
+#define B_EC_OD_REG_SYNC__A 0x2110664
+#define B_EC_OD_DEINT_RAM__A 0x2120000
+#define B_EC_RS_REG_COMM_EXEC__A 0x2130000
+#define B_EC_RS_REG_REQ_PCK_CNT__A 0x2130010
+#define B_EC_RS_REG_VAL__A 0x2130011
+#define B_EC_RS_REG_VAL_PCK 0x1
+#define B_EC_RS_EC_RAM__A 0x2140000
+#define B_EC_OC_REG_COMM_EXEC__A 0x2150000
+#define B_EC_OC_REG_COMM_EXEC_CTL_ACTIVE 0x1
+#define B_EC_OC_REG_COMM_EXEC_CTL_HOLD 0x2
+#define B_EC_OC_REG_COMM_INT_STA__A 0x2150007
+#define B_EC_OC_REG_OC_MODE_LOP__A 0x2150010
+#define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA__M 0x1
+#define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA_ENABLE 0x0
+#define B_EC_OC_REG_OC_MODE_LOP_PAR_ENA_DISABLE 0x1
+#define B_EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC__M 0x4
+#define B_EC_OC_REG_OC_MODE_LOP_DTO_CTR_SRC_STATIC 0x0
+#define B_EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE__M 0x80
+#define B_EC_OC_REG_OC_MODE_LOP_MPG_TRM_MDE_SERIAL 0x80
+#define B_EC_OC_REG_OC_MODE_HIP__A 0x2150011
+#define B_EC_OC_REG_OC_MODE_HIP_MPG_BUS_SRC_MONITOR 0x10
+#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL__M 0x200
+#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_DISABLE 0x0
+#define B_EC_OC_REG_OC_MODE_HIP_MPG_PAR_VAL_ENABLE 0x200
+#define B_EC_OC_REG_OC_MPG_SIO__A 0x2150012
+#define B_EC_OC_REG_OC_MPG_SIO__M 0xFFF
+#define B_EC_OC_REG_DTO_INC_LOP__A 0x2150014
+#define B_EC_OC_REG_DTO_INC_HIP__A 0x2150015
+#define B_EC_OC_REG_SNC_ISC_LVL__A 0x2150016
+#define B_EC_OC_REG_SNC_ISC_LVL_OSC__M 0xF0
+#define B_EC_OC_REG_TMD_TOP_MODE__A 0x215001D
+#define B_EC_OC_REG_TMD_TOP_CNT__A 0x215001E
+#define B_EC_OC_REG_TMD_HIL_MAR__A 0x215001F
+#define B_EC_OC_REG_TMD_LOL_MAR__A 0x2150020
+#define B_EC_OC_REG_TMD_CUR_CNT__A 0x2150021
+#define B_EC_OC_REG_AVR_ASH_CNT__A 0x2150023
+#define B_EC_OC_REG_AVR_BSH_CNT__A 0x2150024
+#define B_EC_OC_REG_RCN_MODE__A 0x2150027
+#define B_EC_OC_REG_RCN_CRA_LOP__A 0x2150028
+#define B_EC_OC_REG_RCN_CRA_HIP__A 0x2150029
+#define B_EC_OC_REG_RCN_CST_LOP__A 0x215002A
+#define B_EC_OC_REG_RCN_CST_HIP__A 0x215002B
+#define B_EC_OC_REG_RCN_SET_LVL__A 0x215002C
+#define B_EC_OC_REG_RCN_GAI_LVL__A 0x215002D
+#define B_EC_OC_REG_RCN_CLP_LOP__A 0x2150032
+#define B_EC_OC_REG_RCN_CLP_HIP__A 0x2150033
+#define B_EC_OC_REG_RCN_MAP_LOP__A 0x2150034
+#define B_EC_OC_REG_RCN_MAP_HIP__A 0x2150035
+#define B_EC_OC_REG_OCR_MPG_UOS__A 0x2150036
+#define B_EC_OC_REG_OCR_MPG_UOS__M 0xFFF
+#define B_EC_OC_REG_OCR_MPG_UOS_INIT 0x0
+#define B_EC_OC_REG_OCR_MPG_USR_DAT__A 0x2150038
+#define B_EC_OC_REG_IPR_INV_MPG__A 0x2150045
+#define B_EC_OC_REG_DTO_CLKMODE__A 0x2150047
+#define B_EC_OC_REG_DTO_PER__A 0x2150048
+#define B_EC_OC_REG_DTO_BUR__A 0x2150049
+#define B_EC_OC_REG_RCR_CLKMODE__A 0x215004A
+#define B_CC_REG_OSC_MODE__A 0x2410010
+#define B_CC_REG_OSC_MODE_M20 0x1
+#define B_CC_REG_PLL_MODE__A 0x2410011
+#define B_CC_REG_PLL_MODE_BYPASS_PLL 0x1
+#define B_CC_REG_PLL_MODE_PUMP_CUR_12 0x14
+#define B_CC_REG_REF_DIVIDE__A 0x2410012
+#define B_CC_REG_PWD_MODE__A 0x2410015
+#define B_CC_REG_PWD_MODE_DOWN_PLL 0x2
+#define B_CC_REG_UPDATE__A 0x2410017
+#define B_CC_REG_UPDATE_KEY 0x3973
+#define B_CC_REG_JTAGID_L__A 0x2410019
+#define B_CC_REG_DIVERSITY__A 0x241001B
+#define B_LC_COMM_EXEC__A 0x2800000
+#define B_LC_RA_RAM_IFINCR_NOM_L__A 0x282000C
+#define B_LC_RA_RAM_FILTER_SYM_SET__A 0x282001A
+#define B_LC_RA_RAM_FILTER_SYM_SET__PRE 0x3E8
+#define B_LC_RA_RAM_FILTER_CRMM_A__A 0x2820060
+#define B_LC_RA_RAM_FILTER_CRMM_A__PRE 0x4
+#define B_LC_RA_RAM_FILTER_CRMM_B__A 0x2820061
+#define B_LC_RA_RAM_FILTER_CRMM_B__PRE 0x1
+#define B_LC_RA_RAM_FILTER_SRMM_A__A 0x2820068
+#define B_LC_RA_RAM_FILTER_SRMM_A__PRE 0x4
+#define B_LC_RA_RAM_FILTER_SRMM_B__A 0x2820069
+#define B_LC_RA_RAM_FILTER_SRMM_B__PRE 0x1
+
+#endif
diff --git a/drivers/media/dvb/frontends/eds1547.h b/drivers/media/dvb/frontends/eds1547.h
index fa79b7c..c983f2f 100644
--- a/drivers/media/dvb/frontends/eds1547.h
+++ b/drivers/media/dvb/frontends/eds1547.h
@@ -61,7 +61,7 @@
0x3d, 0x30,
0x40, 0x63,
0x41, 0x04,
- 0x42, 0x60,
+ 0x42, 0x20,
0x43, 0x00,
0x44, 0x00,
0x45, 0x00,
diff --git a/drivers/media/dvb/frontends/ix2505v.c b/drivers/media/dvb/frontends/ix2505v.c
index 6c2e929..9a517a4 100644
--- a/drivers/media/dvb/frontends/ix2505v.c
+++ b/drivers/media/dvb/frontends/ix2505v.c
@@ -218,11 +218,13 @@
fe->ops.i2c_gate_ctrl(fe, 1);
len = sizeof(data);
-
ret |= ix2505v_write(state, data, len);
data[2] |= 0x4; /* set TM = 1 other bits same */
+ if (fe->ops.i2c_gate_ctrl)
+ fe->ops.i2c_gate_ctrl(fe, 1);
+
len = 1;
ret |= ix2505v_write(state, &data[2], len); /* write byte 4 only */
@@ -233,12 +235,12 @@
deb_info("Data 2=[%x%x]\n", data[2], data[3]);
+ if (fe->ops.i2c_gate_ctrl)
+ fe->ops.i2c_gate_ctrl(fe, 1);
+
len = 2;
ret |= ix2505v_write(state, &data[2], len); /* write byte 4 & 5 */
- if (fe->ops.i2c_gate_ctrl)
- fe->ops.i2c_gate_ctrl(fe, 0);
-
if (state->config->min_delay_ms)
msleep(state->config->min_delay_ms);
diff --git a/drivers/media/dvb/frontends/stv0288.c b/drivers/media/dvb/frontends/stv0288.c
index e3fe17f..8e0cfad 100644
--- a/drivers/media/dvb/frontends/stv0288.c
+++ b/drivers/media/dvb/frontends/stv0288.c
@@ -253,7 +253,7 @@
0x3d, 0x30,
0x40, 0x63,
0x41, 0x04,
- 0x42, 0x60,
+ 0x42, 0x20,
0x43, 0x00,
0x44, 0x00,
0x45, 0x00,
diff --git a/drivers/media/dvb/frontends/stv0299.c b/drivers/media/dvb/frontends/stv0299.c
index 4e3db3a..42684be 100644
--- a/drivers/media/dvb/frontends/stv0299.c
+++ b/drivers/media/dvb/frontends/stv0299.c
@@ -64,6 +64,7 @@
fe_code_rate_t fec_inner;
int errmode;
u32 ucblocks;
+ u8 mcr_reg;
};
#define STATUS_BER 0
@@ -457,6 +458,9 @@
dprintk("stv0299: init chip\n");
+ stv0299_writeregI(state, 0x02, 0x30 | state->mcr_reg);
+ msleep(50);
+
for (i = 0; ; i += 2) {
reg = state->config->inittab[i];
val = state->config->inittab[i+1];
@@ -464,6 +468,8 @@
break;
if (reg == 0x0c && state->config->op0_off)
val &= ~0x10;
+ if (reg == 0x2)
+ state->mcr_reg = val & 0xf;
stv0299_writeregI(state, reg, val);
}
@@ -618,7 +624,7 @@
{
struct stv0299_state* state = fe->demodulator_priv;
- stv0299_writeregI(state, 0x02, 0x80);
+ stv0299_writeregI(state, 0x02, 0xb0 | state->mcr_reg);
state->initialised = 0;
return 0;
@@ -680,7 +686,7 @@
state->errmode = STATUS_BER;
/* check if the demod is there */
- stv0299_writeregI(state, 0x02, 0x34); /* standby off */
+ stv0299_writeregI(state, 0x02, 0x30); /* standby off */
msleep(200);
id = stv0299_readreg(state, 0x00);
diff --git a/drivers/media/dvb/frontends/z0194a.h b/drivers/media/dvb/frontends/z0194a.h
index 07f3fc0..96d86d6 100644
--- a/drivers/media/dvb/frontends/z0194a.h
+++ b/drivers/media/dvb/frontends/z0194a.h
@@ -42,7 +42,7 @@
static u8 sharp_z0194a_inittab[] = {
0x01, 0x15,
- 0x02, 0x00,
+ 0x02, 0x30,
0x03, 0x00,
0x04, 0x7d, /* F22FR = 0x7d, F22 = f_VCO / 128 / 0x7d = 22 kHz */
0x05, 0x35, /* I2CT = 0, SCLT = 1, SDAT = 1 */
diff --git a/drivers/media/dvb/mantis/hopper_cards.c b/drivers/media/dvb/mantis/hopper_cards.c
index 70e73af..1402062 100644
--- a/drivers/media/dvb/mantis/hopper_cards.c
+++ b/drivers/media/dvb/mantis/hopper_cards.c
@@ -44,7 +44,7 @@
static unsigned int verbose;
module_param(verbose, int, 0644);
-MODULE_PARM_DESC(verbose, "verbose startup messages, default is 1 (yes)");
+MODULE_PARM_DESC(verbose, "verbose startup messages, default is 0 (no)");
#define DRIVER_NAME "Hopper"
diff --git a/drivers/media/dvb/mantis/mantis_cards.c b/drivers/media/dvb/mantis/mantis_cards.c
index 40da225..05cbb9d 100644
--- a/drivers/media/dvb/mantis/mantis_cards.c
+++ b/drivers/media/dvb/mantis/mantis_cards.c
@@ -52,7 +52,7 @@
static unsigned int verbose;
module_param(verbose, int, 0644);
-MODULE_PARM_DESC(verbose, "verbose startup messages, default is 1 (yes)");
+MODULE_PARM_DESC(verbose, "verbose startup messages, default is 0 (no)");
static int devs;
diff --git a/drivers/media/dvb/mantis/mantis_pci.c b/drivers/media/dvb/mantis/mantis_pci.c
index 10a432a..371558a 100644
--- a/drivers/media/dvb/mantis/mantis_pci.c
+++ b/drivers/media/dvb/mantis/mantis_pci.c
@@ -48,7 +48,7 @@
int __devinit mantis_pci_init(struct mantis_pci *mantis)
{
- u8 revision, latency;
+ u8 latency;
struct mantis_hwconfig *config = mantis->hwconfig;
struct pci_dev *pdev = mantis->pdev;
int err, ret = 0;
@@ -95,9 +95,8 @@
}
pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &latency);
- pci_read_config_byte(pdev, PCI_CLASS_REVISION, &revision);
mantis->latency = latency;
- mantis->revision = revision;
+ mantis->revision = pdev->revision;
dprintk(MANTIS_ERROR, 0, " Mantis Rev %d [%04x:%04x], ",
mantis->revision,
diff --git a/drivers/media/dvb/mantis/mantis_vp1033.c b/drivers/media/dvb/mantis/mantis_vp1033.c
index deec927..2ae0afa 100644
--- a/drivers/media/dvb/mantis/mantis_vp1033.c
+++ b/drivers/media/dvb/mantis/mantis_vp1033.c
@@ -37,7 +37,7 @@
u8 lgtdqcs001f_inittab[] = {
0x01, 0x15,
- 0x02, 0x00,
+ 0x02, 0x30,
0x03, 0x00,
0x04, 0x2a,
0x05, 0x85,
diff --git a/drivers/media/dvb/pt1/pt1.c b/drivers/media/dvb/pt1/pt1.c
index 0486919..b81df5f 100644
--- a/drivers/media/dvb/pt1/pt1.c
+++ b/drivers/media/dvb/pt1/pt1.c
@@ -1090,6 +1090,7 @@
i2c_adap->algo = &pt1_i2c_algo;
i2c_adap->algo_data = NULL;
i2c_adap->dev.parent = &pdev->dev;
+ strcpy(i2c_adap->name, DRIVER_NAME);
i2c_set_adapdata(i2c_adap, pt1);
ret = i2c_add_adapter(i2c_adap);
if (ret < 0)
@@ -1156,10 +1157,10 @@
pt1->power = 0;
pt1->reset = 1;
pt1_update_power(pt1);
-err_pt1_cleanup_adapters:
- pt1_cleanup_adapters(pt1);
err_i2c_del_adapter:
i2c_del_adapter(i2c_adap);
+err_pt1_cleanup_adapters:
+ pt1_cleanup_adapters(pt1);
err_kfree:
pci_set_drvdata(pdev, NULL);
kfree(pt1);
diff --git a/drivers/media/dvb/siano/smsusb.c b/drivers/media/dvb/siano/smsusb.c
index 0b8da57..0c8164a 100644
--- a/drivers/media/dvb/siano/smsusb.c
+++ b/drivers/media/dvb/siano/smsusb.c
@@ -297,9 +297,8 @@
if (dev->coredev)
smscore_unregister_device(dev->coredev);
- kfree(dev);
-
sms_info("device %p destroyed", dev);
+ kfree(dev);
}
usb_set_intfdata(intf, NULL);
diff --git a/drivers/media/dvb/ttpci/Kconfig b/drivers/media/dvb/ttpci/Kconfig
index 44afab2..9d83ced 100644
--- a/drivers/media/dvb/ttpci/Kconfig
+++ b/drivers/media/dvb/ttpci/Kconfig
@@ -95,6 +95,8 @@
select DVB_STB0899 if !DVB_FE_CUSTOMISE
select DVB_STB6100 if !DVB_FE_CUSTOMISE
select DVB_LNBP21 if !DVB_FE_CUSTOMISE
+ select DVB_STV0288 if !DVB_FE_CUSTOMISE
+ select DVB_STB6000 if !DVB_FE_CUSTOMISE
select DVB_TDA10023 if !DVB_FE_CUSTOMISE
select MEDIA_TUNER_TDA827X if !MEDIA_TUNER_CUSTOMISE
depends on RC_CORE
diff --git a/drivers/media/dvb/ttpci/budget-ci.c b/drivers/media/dvb/ttpci/budget-ci.c
index 1d79ada..926f299 100644
--- a/drivers/media/dvb/ttpci/budget-ci.c
+++ b/drivers/media/dvb/ttpci/budget-ci.c
@@ -52,6 +52,7 @@
#include "bsru6.h"
#include "tda1002x.h"
#include "tda827x.h"
+#include "bsbe1-d01a.h"
#define MODULE_NAME "budget_ci"
@@ -224,6 +225,7 @@
case 0x1017:
case 0x1019:
case 0x101a:
+ case 0x101b:
/* for the Technotrend 1500 bundled remote */
dev->map_name = RC_MAP_TT_1500;
break;
@@ -1388,6 +1390,23 @@
}
break;
+ case 0x101b: /* TT S-1500B (BSBE1-D01A - STV0288/STB6000/LNBP21) */
+ budget_ci->budget.dvb_frontend = dvb_attach(stv0288_attach, &stv0288_bsbe1_d01a_config, &budget_ci->budget.i2c_adap);
+ if (budget_ci->budget.dvb_frontend) {
+ if (dvb_attach(stb6000_attach, budget_ci->budget.dvb_frontend, 0x63, &budget_ci->budget.i2c_adap)) {
+ if (!dvb_attach(lnbp21_attach, budget_ci->budget.dvb_frontend, &budget_ci->budget.i2c_adap, 0, 0)) {
+ printk(KERN_ERR "%s: No LNBP21 found!\n", __func__);
+ dvb_frontend_detach(budget_ci->budget.dvb_frontend);
+ budget_ci->budget.dvb_frontend = NULL;
+ }
+ } else {
+ printk(KERN_ERR "%s: No STB6000 found!\n", __func__);
+ dvb_frontend_detach(budget_ci->budget.dvb_frontend);
+ budget_ci->budget.dvb_frontend = NULL;
+ }
+ }
+ break;
+
case 0x1019: // TT S2-3200 PCI
/*
* NOTE! on some STB0899 versions, the internal PLL takes a longer time
@@ -1518,6 +1537,7 @@
MAKE_BUDGET_INFO(ttbcci, "TT-Budget-C-CI PCI", BUDGET_TT);
MAKE_BUDGET_INFO(ttc1501, "TT-Budget C-1501 PCI", BUDGET_TT);
MAKE_BUDGET_INFO(tt3200, "TT-Budget S2-3200 PCI", BUDGET_TT);
+MAKE_BUDGET_INFO(ttbs1500b, "TT-Budget S-1500B PCI", BUDGET_TT);
static struct pci_device_id pci_tbl[] = {
MAKE_EXTENSION_PCI(ttbci, 0x13c2, 0x100c),
@@ -1528,6 +1548,7 @@
MAKE_EXTENSION_PCI(ttbs2, 0x13c2, 0x1017),
MAKE_EXTENSION_PCI(ttc1501, 0x13c2, 0x101a),
MAKE_EXTENSION_PCI(tt3200, 0x13c2, 0x1019),
+ MAKE_EXTENSION_PCI(ttbs1500b, 0x13c2, 0x101b),
{
.vendor = 0,
}
diff --git a/drivers/media/dvb/ttusb-budget/dvb-ttusb-budget.c b/drivers/media/dvb/ttusb-budget/dvb-ttusb-budget.c
index cbe2f0d..420bb42 100644
--- a/drivers/media/dvb/ttusb-budget/dvb-ttusb-budget.c
+++ b/drivers/media/dvb/ttusb-budget/dvb-ttusb-budget.c
@@ -52,7 +52,7 @@
my TTUSB, so let it undef'd unless you want to implement another
frontend. never tested.
- DEBUG:
+ debug:
define it to > 3 for really hardcore debugging. you probably don't want
this unless the device doesn't load at all. > 2 for bandwidth statistics.
*/
@@ -134,20 +134,19 @@
/* ugly workaround ... don't know why it's necessary to read */
/* all result codes. */
-#define DEBUG 0
static int ttusb_cmd(struct ttusb *ttusb,
const u8 * data, int len, int needresult)
{
int actual_len;
int err;
-#if DEBUG >= 3
int i;
- printk(">");
- for (i = 0; i < len; ++i)
- printk(" %02x", data[i]);
- printk("\n");
-#endif
+ if (debug >= 3) {
+ printk(KERN_DEBUG ">");
+ for (i = 0; i < len; ++i)
+ printk(KERN_CONT " %02x", data[i]);
+ printk(KERN_CONT "\n");
+ }
if (mutex_lock_interruptible(&ttusb->semusb) < 0)
return -EAGAIN;
@@ -176,13 +175,15 @@
mutex_unlock(&ttusb->semusb);
return err;
}
-#if DEBUG >= 3
- actual_len = ttusb->last_result[3] + 4;
- printk("<");
- for (i = 0; i < actual_len; ++i)
- printk(" %02x", ttusb->last_result[i]);
- printk("\n");
-#endif
+
+ if (debug >= 3) {
+ actual_len = ttusb->last_result[3] + 4;
+ printk(KERN_DEBUG "<");
+ for (i = 0; i < actual_len; ++i)
+ printk(KERN_CONT " %02x", ttusb->last_result[i]);
+ printk(KERN_CONT "\n");
+ }
+
if (!needresult)
mutex_unlock(&ttusb->semusb);
return 0;
@@ -636,16 +637,13 @@
++ttusb->mux_state;
else {
ttusb->mux_state = 0;
-#if DEBUG > 3
- if (ttusb->insync)
- printk("%02x ", data[-1]);
-#else
if (ttusb->insync) {
- printk("%s: lost sync.\n",
+ dprintk("%s: %02x\n",
+ __func__, data[-1]);
+ printk(KERN_INFO "%s: lost sync.\n",
__func__);
ttusb->insync = 0;
}
-#endif
}
break;
case 3:
@@ -744,6 +742,9 @@
static void ttusb_iso_irq(struct urb *urb)
{
struct ttusb *ttusb = urb->context;
+ struct usb_iso_packet_descriptor *d;
+ u8 *data;
+ int len, i;
if (!ttusb->iso_streaming)
return;
@@ -755,21 +756,14 @@
#endif
if (!urb->status) {
- int i;
for (i = 0; i < urb->number_of_packets; ++i) {
- struct usb_iso_packet_descriptor *d;
- u8 *data;
- int len;
numpkt++;
if (time_after_eq(jiffies, lastj + HZ)) {
-#if DEBUG > 2
- printk
- ("frames/s: %d (ts: %d, stuff %d, sec: %d, invalid: %d, all: %d)\n",
- numpkt * HZ / (jiffies - lastj),
- numts, numstuff, numsec, numinvalid,
- numts + numstuff + numsec +
- numinvalid);
-#endif
+ dprintk("frames/s: %lu (ts: %d, stuff %d, "
+ "sec: %d, invalid: %d, all: %d)\n",
+ numpkt * HZ / (jiffies - lastj),
+ numts, numstuff, numsec, numinvalid,
+ numts + numstuff + numsec + numinvalid);
numts = numstuff = numsec = numinvalid = 0;
lastj = jiffies;
numpkt = 0;
diff --git a/drivers/media/radio/si470x/radio-si470x-common.c b/drivers/media/radio/si470x/radio-si470x-common.c
index 38ae6cd..0e740c9 100644
--- a/drivers/media/radio/si470x/radio-si470x-common.c
+++ b/drivers/media/radio/si470x/radio-si470x-common.c
@@ -174,15 +174,27 @@
if (retval < 0)
goto done;
- /* wait till tune operation has completed */
- timeout = jiffies + msecs_to_jiffies(tune_timeout);
- do {
- retval = si470x_get_register(radio, STATUSRSSI);
- if (retval < 0)
- goto stop;
- timed_out = time_after(jiffies, timeout);
- } while (((radio->registers[STATUSRSSI] & STATUSRSSI_STC) == 0) &&
- (!timed_out));
+ /* currently I2C driver only uses interrupt way to tune */
+ if (radio->stci_enabled) {
+ INIT_COMPLETION(radio->completion);
+
+ /* wait till tune operation has completed */
+ retval = wait_for_completion_timeout(&radio->completion,
+ msecs_to_jiffies(tune_timeout));
+ if (!retval)
+ timed_out = true;
+ } else {
+ /* wait till tune operation has completed */
+ timeout = jiffies + msecs_to_jiffies(tune_timeout);
+ do {
+ retval = si470x_get_register(radio, STATUSRSSI);
+ if (retval < 0)
+ goto stop;
+ timed_out = time_after(jiffies, timeout);
+ } while (((radio->registers[STATUSRSSI] & STATUSRSSI_STC) == 0)
+ && (!timed_out));
+ }
+
if ((radio->registers[STATUSRSSI] & STATUSRSSI_STC) == 0)
dev_warn(&radio->videodev->dev, "tune does not complete\n");
if (timed_out)
@@ -310,15 +322,27 @@
if (retval < 0)
goto done;
- /* wait till seek operation has completed */
- timeout = jiffies + msecs_to_jiffies(seek_timeout);
- do {
- retval = si470x_get_register(radio, STATUSRSSI);
- if (retval < 0)
- goto stop;
- timed_out = time_after(jiffies, timeout);
- } while (((radio->registers[STATUSRSSI] & STATUSRSSI_STC) == 0) &&
- (!timed_out));
+ /* currently I2C driver only uses interrupt way to seek */
+ if (radio->stci_enabled) {
+ INIT_COMPLETION(radio->completion);
+
+ /* wait till seek operation has completed */
+ retval = wait_for_completion_timeout(&radio->completion,
+ msecs_to_jiffies(seek_timeout));
+ if (!retval)
+ timed_out = true;
+ } else {
+ /* wait till seek operation has completed */
+ timeout = jiffies + msecs_to_jiffies(seek_timeout);
+ do {
+ retval = si470x_get_register(radio, STATUSRSSI);
+ if (retval < 0)
+ goto stop;
+ timed_out = time_after(jiffies, timeout);
+ } while (((radio->registers[STATUSRSSI] & STATUSRSSI_STC) == 0)
+ && (!timed_out));
+ }
+
if ((radio->registers[STATUSRSSI] & STATUSRSSI_STC) == 0)
dev_warn(&radio->videodev->dev, "seek does not complete\n");
if (radio->registers[STATUSRSSI] & STATUSRSSI_SF)
diff --git a/drivers/media/radio/si470x/radio-si470x-i2c.c b/drivers/media/radio/si470x/radio-si470x-i2c.c
index 4ce541a..a2a6777 100644
--- a/drivers/media/radio/si470x/radio-si470x-i2c.c
+++ b/drivers/media/radio/si470x/radio-si470x-i2c.c
@@ -197,8 +197,9 @@
if (retval < 0)
goto done;
- /* enable RDS interrupt */
+ /* enable RDS / STC interrupt */
radio->registers[SYSCONFIG1] |= SYSCONFIG1_RDSIEN;
+ radio->registers[SYSCONFIG1] |= SYSCONFIG1_STCIEN;
radio->registers[SYSCONFIG1] &= ~SYSCONFIG1_GPIO2;
radio->registers[SYSCONFIG1] |= 0x1 << 2;
retval = si470x_set_register(radio, SYSCONFIG1);
@@ -261,12 +262,11 @@
**************************************************************************/
/*
- * si470x_i2c_interrupt_work - rds processing function
+ * si470x_i2c_interrupt - interrupt handler
*/
-static void si470x_i2c_interrupt_work(struct work_struct *work)
+static irqreturn_t si470x_i2c_interrupt(int irq, void *dev_id)
{
- struct si470x_device *radio = container_of(work,
- struct si470x_device, radio_work);
+ struct si470x_device *radio = dev_id;
unsigned char regnr;
unsigned char blocknum;
unsigned short bler; /* rds block errors */
@@ -274,21 +274,29 @@
unsigned char tmpbuf[3];
int retval = 0;
+ /* check Seek/Tune Complete */
+ retval = si470x_get_register(radio, STATUSRSSI);
+ if (retval < 0)
+ goto end;
+
+ if (radio->registers[STATUSRSSI] & STATUSRSSI_STC)
+ complete(&radio->completion);
+
/* safety checks */
if ((radio->registers[SYSCONFIG1] & SYSCONFIG1_RDS) == 0)
- return;
+ goto end;
/* Update RDS registers */
- for (regnr = 0; regnr < RDS_REGISTER_NUM; regnr++) {
+ for (regnr = 1; regnr < RDS_REGISTER_NUM; regnr++) {
retval = si470x_get_register(radio, STATUSRSSI + regnr);
if (retval < 0)
- return;
+ goto end;
}
/* get rds blocks */
if ((radio->registers[STATUSRSSI] & STATUSRSSI_RDSR) == 0)
/* No RDS group ready, better luck next time */
- return;
+ goto end;
for (blocknum = 0; blocknum < 4; blocknum++) {
switch (blocknum) {
@@ -342,19 +350,8 @@
if (radio->wr_index != radio->rd_index)
wake_up_interruptible(&radio->read_queue);
-}
-
-/*
- * si470x_i2c_interrupt - interrupt handler
- */
-static irqreturn_t si470x_i2c_interrupt(int irq, void *dev_id)
-{
- struct si470x_device *radio = dev_id;
-
- if (!work_pending(&radio->radio_work))
- schedule_work(&radio->radio_work);
-
+end:
return IRQ_HANDLED;
}
@@ -376,7 +373,6 @@
goto err_initial;
}
- INIT_WORK(&radio->radio_work, si470x_i2c_interrupt_work);
radio->users = 0;
radio->client = client;
mutex_init(&radio->lock);
@@ -441,7 +437,11 @@
radio->rd_index = 0;
init_waitqueue_head(&radio->read_queue);
- retval = request_irq(client->irq, si470x_i2c_interrupt,
+ /* mark Seek/Tune Complete Interrupt enabled */
+ radio->stci_enabled = true;
+ init_completion(&radio->completion);
+
+ retval = request_threaded_irq(client->irq, NULL, si470x_i2c_interrupt,
IRQF_TRIGGER_FALLING, DRIVER_NAME, radio);
if (retval) {
dev_err(&client->dev, "Failed to register interrupt\n");
@@ -479,7 +479,6 @@
struct si470x_device *radio = i2c_get_clientdata(client);
free_irq(client->irq, radio);
- cancel_work_sync(&radio->radio_work);
video_unregister_device(radio->videodev);
kfree(radio);
@@ -491,8 +490,9 @@
/*
* si470x_i2c_suspend - suspend the device
*/
-static int si470x_i2c_suspend(struct i2c_client *client, pm_message_t mesg)
+static int si470x_i2c_suspend(struct device *dev)
{
+ struct i2c_client *client = to_i2c_client(dev);
struct si470x_device *radio = i2c_get_clientdata(client);
/* power down */
@@ -507,8 +507,9 @@
/*
* si470x_i2c_resume - resume the device
*/
-static int si470x_i2c_resume(struct i2c_client *client)
+static int si470x_i2c_resume(struct device *dev)
{
+ struct i2c_client *client = to_i2c_client(dev);
struct si470x_device *radio = i2c_get_clientdata(client);
/* power up : need 110ms */
@@ -519,9 +520,8 @@
return 0;
}
-#else
-#define si470x_i2c_suspend NULL
-#define si470x_i2c_resume NULL
+
+static SIMPLE_DEV_PM_OPS(si470x_i2c_pm, si470x_i2c_suspend, si470x_i2c_resume);
#endif
@@ -532,11 +532,12 @@
.driver = {
.name = "si470x",
.owner = THIS_MODULE,
+#ifdef CONFIG_PM
+ .pm = &si470x_i2c_pm,
+#endif
},
.probe = si470x_i2c_probe,
.remove = __devexit_p(si470x_i2c_remove),
- .suspend = si470x_i2c_suspend,
- .resume = si470x_i2c_resume,
.id_table = si470x_i2c_id,
};
diff --git a/drivers/media/radio/si470x/radio-si470x.h b/drivers/media/radio/si470x/radio-si470x.h
index 4a4e908..68da001 100644
--- a/drivers/media/radio/si470x/radio-si470x.h
+++ b/drivers/media/radio/si470x/radio-si470x.h
@@ -158,6 +158,9 @@
unsigned int rd_index;
unsigned int wr_index;
+ struct completion completion;
+ bool stci_enabled; /* Seek/Tune Complete Interrupt */
+
#if defined(CONFIG_USB_SI470X) || defined(CONFIG_USB_SI470X_MODULE)
/* reference to USB and video device */
struct usb_device *usbdev;
@@ -179,7 +182,6 @@
#if defined(CONFIG_I2C_SI470X) || defined(CONFIG_I2C_SI470X_MODULE)
struct i2c_client *client;
- struct work_struct radio_work;
#endif
};
diff --git a/drivers/media/radio/wl128x/fmdrv.h b/drivers/media/radio/wl128x/fmdrv.h
index 5db6fd1..1a45a5d 100644
--- a/drivers/media/radio/wl128x/fmdrv.h
+++ b/drivers/media/radio/wl128x/fmdrv.h
@@ -55,8 +55,6 @@
#define FM_DRV_TX_TIMEOUT (5*HZ) /* 5 seconds */
#define FM_DRV_RX_SEEK_TIMEOUT (20*HZ) /* 20 seconds */
-#define NO_OF_ENTRIES_IN_ARRAY(array) (sizeof(array) / sizeof(array[0]))
-
#define fmerr(format, ...) \
printk(KERN_ERR "fmdrv: " format, ## __VA_ARGS__)
#define fmwarn(format, ...) \
diff --git a/drivers/media/rc/Kconfig b/drivers/media/rc/Kconfig
index 7f03142..154c337 100644
--- a/drivers/media/rc/Kconfig
+++ b/drivers/media/rc/Kconfig
@@ -161,6 +161,17 @@
To compile this driver as a module, choose M here: the
module will be called nuvoton-cir.
+config IR_REDRAT3
+ tristate "RedRat3 IR Transceiver"
+ depends on USB_ARCH_HAS_HCD
+ depends on RC_CORE
+ select USB
+ ---help---
+ Say Y here if you want to use a RedRat3 Infrared Transceiver.
+
+ To compile this driver as a module, choose M here: the
+ module will be called redrat3.
+
config IR_STREAMZAP
tristate "Streamzap PC Remote IR Receiver"
depends on USB_ARCH_HAS_HCD
diff --git a/drivers/media/rc/Makefile b/drivers/media/rc/Makefile
index c6cfe70..1f90a21 100644
--- a/drivers/media/rc/Makefile
+++ b/drivers/media/rc/Makefile
@@ -18,6 +18,7 @@
obj-$(CONFIG_IR_MCEUSB) += mceusb.o
obj-$(CONFIG_IR_NUVOTON) += nuvoton-cir.o
obj-$(CONFIG_IR_ENE) += ene_ir.o
+obj-$(CONFIG_IR_REDRAT3) += redrat3.o
obj-$(CONFIG_IR_STREAMZAP) += streamzap.o
obj-$(CONFIG_IR_WINBOND_CIR) += winbond-cir.o
obj-$(CONFIG_RC_LOOPBACK) += rc-loopback.o
diff --git a/drivers/media/rc/imon.c b/drivers/media/rc/imon.c
index 8fc0f08..3f3c707 100644
--- a/drivers/media/rc/imon.c
+++ b/drivers/media/rc/imon.c
@@ -443,16 +443,6 @@
} else {
ictx->display_isopen = false;
dev_dbg(ictx->dev, "display port closed\n");
- if (!ictx->dev_present_intf0) {
- /*
- * Device disconnected before close and IR port is not
- * open. If IR port is open, context will be deleted by
- * ir_close.
- */
- mutex_unlock(&ictx->lock);
- free_imon_context(ictx);
- return retval;
- }
}
mutex_unlock(&ictx->lock);
@@ -1492,7 +1482,6 @@
struct device *dev = ictx->dev;
unsigned long flags;
u32 kc;
- bool norelease = false;
int i;
u64 scancode;
int press_type = 0;
@@ -1560,7 +1549,6 @@
!(buf[1] & 0x1 || buf[1] >> 2 & 0x1))) {
len = 8;
imon_pad_to_keys(ictx, buf);
- norelease = true;
}
if (debug) {
@@ -1982,7 +1970,7 @@
return touch;
touch_register_failed:
- input_free_device(ictx->touch);
+ input_free_device(touch);
touch_alloc_failed:
return NULL;
@@ -2274,14 +2262,12 @@
struct usb_host_interface *iface_desc = NULL;
struct usb_interface *first_if;
struct device *dev = &interface->dev;
- int ifnum, code_length, sysfs_err;
+ int ifnum, sysfs_err;
int ret = 0;
struct imon_context *ictx = NULL;
struct imon_context *first_if_ctx = NULL;
u16 vendor, product;
- code_length = BUF_CHUNK_SIZE * 8;
-
usbdev = usb_get_dev(interface_to_usbdev(interface));
iface_desc = interface->cur_altsetting;
ifnum = iface_desc->desc.bInterfaceNumber;
@@ -2366,8 +2352,6 @@
dev = ictx->dev;
ifnum = interface->cur_altsetting->desc.bInterfaceNumber;
- mutex_lock(&ictx->lock);
-
/*
* sysfs_remove_group is safe to call even if sysfs_create_group
* hasn't been called
@@ -2391,24 +2375,20 @@
if (ictx->display_supported) {
if (ictx->display_type == IMON_DISPLAY_TYPE_LCD)
usb_deregister_dev(interface, &imon_lcd_class);
- else
+ else if (ictx->display_type == IMON_DISPLAY_TYPE_VFD)
usb_deregister_dev(interface, &imon_vfd_class);
}
} else {
ictx->dev_present_intf1 = false;
usb_kill_urb(ictx->rx_urb_intf1);
- if (ictx->display_type == IMON_DISPLAY_TYPE_VGA)
+ if (ictx->display_type == IMON_DISPLAY_TYPE_VGA) {
input_unregister_device(ictx->touch);
+ del_timer_sync(&ictx->ttimer);
+ }
}
- if (!ictx->dev_present_intf0 && !ictx->dev_present_intf1) {
- if (ictx->display_type == IMON_DISPLAY_TYPE_VGA)
- del_timer_sync(&ictx->ttimer);
- mutex_unlock(&ictx->lock);
- if (!ictx->display_isopen)
- free_imon_context(ictx);
- } else
- mutex_unlock(&ictx->lock);
+ if (!ictx->dev_present_intf0 && !ictx->dev_present_intf1)
+ free_imon_context(ictx);
mutex_unlock(&driver_lock);
diff --git a/drivers/media/rc/ite-cir.c b/drivers/media/rc/ite-cir.c
index 43908a7..e716b93 100644
--- a/drivers/media/rc/ite-cir.c
+++ b/drivers/media/rc/ite-cir.c
@@ -1250,11 +1250,9 @@
ite_dbg("%s called", __func__);
/* clear out all interrupt enable flags */
- it8709_wr(dev,
- it8709_rr(dev,
- IT85_C0IER) & ~(IT85_IEC | IT85_RFOIE |
- IT85_RDAIE |
- IT85_TLDLIE), IT85_C0IER);
+ it8709_wr(dev, it8709_rr(dev, IT85_C0IER) &
+ ~(IT85_IEC | IT85_RFOIE | IT85_RDAIE | IT85_TLDLIE),
+ IT85_C0IER);
/* disable the receiver */
it8709_disable_rx(dev);
@@ -1270,11 +1268,9 @@
ite_dbg("%s called", __func__);
/* disable all the interrupts */
- it8709_wr(dev,
- it8709_rr(dev,
- IT85_C0IER) & ~(IT85_IEC | IT85_RFOIE |
- IT85_RDAIE |
- IT85_TLDLIE), IT85_C0IER);
+ it8709_wr(dev, it8709_rr(dev, IT85_C0IER) &
+ ~(IT85_IEC | IT85_RFOIE | IT85_RDAIE | IT85_TLDLIE),
+ IT85_C0IER);
/* program the baud rate divisor */
it8709_wr(dev, ITE_BAUDRATE_DIVISOR & 0xff, IT85_C0BDLR);
@@ -1282,28 +1278,22 @@
IT85_C0BDHR);
/* program the C0MSTCR register defaults */
- it8709_wr(dev, (it8709_rr(dev, IT85_C0MSTCR) & ~(IT85_ILSEL |
- IT85_ILE
- | IT85_FIFOTL
- |
- IT85_FIFOCLR
- |
- IT85_RESET))
- | IT85_FIFOTL_DEFAULT, IT85_C0MSTCR);
+ it8709_wr(dev, (it8709_rr(dev, IT85_C0MSTCR) &
+ ~(IT85_ILSEL | IT85_ILE | IT85_FIFOTL
+ | IT85_FIFOCLR | IT85_RESET)) | IT85_FIFOTL_DEFAULT,
+ IT85_C0MSTCR);
/* program the C0RCR register defaults */
- it8709_wr(dev,
- (it8709_rr(dev, IT85_C0RCR) &
- ~(IT85_RXEN | IT85_RDWOS | IT85_RXEND
- | IT85_RXACT | IT85_RXDCR)) |
- ITE_RXDCR_DEFAULT, IT85_C0RCR);
+ it8709_wr(dev, (it8709_rr(dev, IT85_C0RCR) &
+ ~(IT85_RXEN | IT85_RDWOS | IT85_RXEND | IT85_RXACT
+ | IT85_RXDCR)) | ITE_RXDCR_DEFAULT,
+ IT85_C0RCR);
/* program the C0TCR register defaults */
- it8709_wr(dev, (it8709_rr(dev, IT85_C0TCR)
- &~(IT85_TXMPM | IT85_TXMPW))
- |IT85_TXRLE | IT85_TXENDF |
- IT85_TXMPM_DEFAULT |
- IT85_TXMPW_DEFAULT, IT85_C0TCR);
+ it8709_wr(dev, (it8709_rr(dev, IT85_C0TCR) & ~(IT85_TXMPM | IT85_TXMPW))
+ | IT85_TXRLE | IT85_TXENDF | IT85_TXMPM_DEFAULT
+ | IT85_TXMPW_DEFAULT,
+ IT85_C0TCR);
/* program the carrier parameters */
ite_set_carrier_params(dev);
@@ -1660,6 +1650,9 @@
ite_dbg("%s called", __func__);
+ /* wait for any transmission to end */
+ wait_event_interruptible(dev->tx_ended, !dev->transmitting);
+
spin_lock_irqsave(&dev->lock, flags);
/* disable all interrupts */
@@ -1680,13 +1673,10 @@
spin_lock_irqsave(&dev->lock, flags);
- if (dev->transmitting) {
- /* wake up the transmitter */
- wake_up_interruptible(&dev->tx_queue);
- } else {
- /* enable the receiver */
- dev->params.enable_rx(dev);
- }
+ /* reinitialize hardware config registers */
+ dev->params.init_hardware(dev);
+ /* enable the receiver */
+ dev->params.enable_rx(dev);
spin_unlock_irqrestore(&dev->lock, flags);
diff --git a/drivers/media/rc/keymaps/Makefile b/drivers/media/rc/keymaps/Makefile
index 85cac7d..b57fc83 100644
--- a/drivers/media/rc/keymaps/Makefile
+++ b/drivers/media/rc/keymaps/Makefile
@@ -77,6 +77,7 @@
rc-terratec-slim.o \
rc-terratec-slim-2.o \
rc-tevii-nec.o \
+ rc-tivo.o \
rc-total-media-in-hand.o \
rc-trekstor.o \
rc-tt-1500.o \
diff --git a/drivers/media/rc/keymaps/rc-avermedia-cardbus.c b/drivers/media/rc/keymaps/rc-avermedia-cardbus.c
index bdf97b7..22f54d4 100644
--- a/drivers/media/rc/keymaps/rc-avermedia-cardbus.c
+++ b/drivers/media/rc/keymaps/rc-avermedia-cardbus.c
@@ -52,7 +52,7 @@
{ 0x28, KEY_SELECT }, /* Select */
{ 0x29, KEY_BLUE }, /* Blue/Picture */
{ 0x2a, KEY_BACKSPACE }, /* Back */
- { 0x2b, KEY_MEDIA }, /* PIP (Picture-in-picture) */
+ { 0x2b, KEY_VIDEO }, /* PIP (Picture-in-picture) */
{ 0x2c, KEY_DOWN },
{ 0x2e, KEY_DOT },
{ 0x2f, KEY_TV }, /* Live TV */
diff --git a/drivers/media/rc/keymaps/rc-imon-mce.c b/drivers/media/rc/keymaps/rc-imon-mce.c
index 937a819..0ea2aa1 100644
--- a/drivers/media/rc/keymaps/rc-imon-mce.c
+++ b/drivers/media/rc/keymaps/rc-imon-mce.c
@@ -111,7 +111,7 @@
{ 0x800ff44d, KEY_TITLE },
{ 0x800ff40c, KEY_POWER },
- { 0x800ff40d, KEY_LEFTMETA }, /* Windows MCE button */
+ { 0x800ff40d, KEY_MEDIA }, /* Windows MCE button */
};
diff --git a/drivers/media/rc/keymaps/rc-imon-pad.c b/drivers/media/rc/keymaps/rc-imon-pad.c
index 63d42bd..75d3843 100644
--- a/drivers/media/rc/keymaps/rc-imon-pad.c
+++ b/drivers/media/rc/keymaps/rc-imon-pad.c
@@ -87,7 +87,7 @@
{ 0x2b8515b7, KEY_VIDEO },
{ 0x299195b7, KEY_AUDIO },
- { 0x2ba115b7, KEY_CAMERA },
+ { 0x2ba115b7, KEY_IMAGES },
{ 0x28a515b7, KEY_TV },
{ 0x29a395b7, KEY_DVD },
{ 0x29a295b7, KEY_DVD },
@@ -97,7 +97,7 @@
{ 0x2ba395b7, KEY_MENU },
{ 0x288515b7, KEY_BOOKMARKS },
- { 0x2ab715b7, KEY_MEDIA }, /* Thumbnail */
+ { 0x2ab715b7, KEY_CAMERA }, /* Thumbnail */
{ 0x298595b7, KEY_SUBTITLE },
{ 0x2b8595b7, KEY_LANGUAGE },
@@ -125,7 +125,7 @@
{ 0x2b8195b7, KEY_CONTEXT_MENU }, /* Left Menu*/
{ 0x02000065, KEY_COMPOSE }, /* RightMenu */
{ 0x28b715b7, KEY_COMPOSE }, /* RightMenu */
- { 0x2ab195b7, KEY_LEFTMETA }, /* Go or MultiMon */
+ { 0x2ab195b7, KEY_MEDIA }, /* Go or MultiMon */
{ 0x29b715b7, KEY_DASHBOARD }, /* AppLauncher */
};
diff --git a/drivers/media/rc/keymaps/rc-kworld-plus-tv-analog.c b/drivers/media/rc/keymaps/rc-kworld-plus-tv-analog.c
index 08d1831..7fa17a3 100644
--- a/drivers/media/rc/keymaps/rc-kworld-plus-tv-analog.c
+++ b/drivers/media/rc/keymaps/rc-kworld-plus-tv-analog.c
@@ -17,7 +17,7 @@
*/
static struct rc_map_table kworld_plus_tv_analog[] = {
- { 0x0c, KEY_LEFTMETA }, /* Kworld key */
+ { 0x0c, KEY_MEDIA }, /* Kworld key */
{ 0x16, KEY_CLOSECD }, /* -> ) */
{ 0x1d, KEY_POWER2 },
diff --git a/drivers/media/rc/keymaps/rc-rc6-mce.c b/drivers/media/rc/keymaps/rc-rc6-mce.c
index 8dd519e..01b69bc 100644
--- a/drivers/media/rc/keymaps/rc-rc6-mce.c
+++ b/drivers/media/rc/keymaps/rc-rc6-mce.c
@@ -30,7 +30,7 @@
{ 0x800f040a, KEY_DELETE },
{ 0x800f040b, KEY_ENTER },
{ 0x800f040c, KEY_POWER }, /* PC Power */
- { 0x800f040d, KEY_LEFTMETA }, /* Windows MCE button */
+ { 0x800f040d, KEY_MEDIA }, /* Windows MCE button */
{ 0x800f040e, KEY_MUTE },
{ 0x800f040f, KEY_INFO },
@@ -87,7 +87,7 @@
{ 0x800f0465, KEY_POWER2 }, /* TV Power */
{ 0x800f046e, KEY_PLAYPAUSE },
- { 0x800f046f, KEY_MEDIA }, /* Start media application (NEW) */
+ { 0x800f046f, KEY_PLAYER }, /* Start media application (NEW) */
{ 0x800f0480, KEY_BRIGHTNESSDOWN },
{ 0x800f0481, KEY_PLAYPAUSE },
diff --git a/drivers/media/rc/keymaps/rc-tivo.c b/drivers/media/rc/keymaps/rc-tivo.c
new file mode 100644
index 0000000..98ad085
--- /dev/null
+++ b/drivers/media/rc/keymaps/rc-tivo.c
@@ -0,0 +1,98 @@
+/* rc-tivo.c - Keytable for TiVo remotes
+ *
+ * Copyright (c) 2011 by Jarod Wilson <jarod@redhat.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <media/rc-map.h>
+
+/*
+ * Initial mapping is for the TiVo remote included in the Nero LiquidTV bundle,
+ * which also ships with a TiVo-branded IR transceiver, supported by the mceusb
+ * driver. Note that the remote uses an NEC-ish protocol, but instead of having
+ * a command/not_command pair, it has a vendor ID of 0xa10c, but some keys, the
+ * NEC extended checksums do pass, so the table presently has the intended
+ * values and the checksum-passed versions for those keys.
+ */
+static struct rc_map_table tivo[] = {
+ { 0xa10c900f, KEY_MEDIA }, /* TiVo Button */
+ { 0xa10c0807, KEY_POWER2 }, /* TV Power */
+ { 0xa10c8807, KEY_TV }, /* Live TV/Swap */
+ { 0xa10c2c03, KEY_VIDEO_NEXT }, /* TV Input */
+ { 0xa10cc807, KEY_INFO },
+ { 0xa10cfa05, KEY_CYCLEWINDOWS }, /* Window */
+ { 0x0085305f, KEY_CYCLEWINDOWS },
+ { 0xa10c6c03, KEY_EPG }, /* Guide */
+
+ { 0xa10c2807, KEY_UP },
+ { 0xa10c6807, KEY_DOWN },
+ { 0xa10ce807, KEY_LEFT },
+ { 0xa10ca807, KEY_RIGHT },
+
+ { 0xa10c1807, KEY_SCROLLDOWN }, /* Red Thumbs Down */
+ { 0xa10c9807, KEY_SELECT },
+ { 0xa10c5807, KEY_SCROLLUP }, /* Green Thumbs Up */
+
+ { 0xa10c3807, KEY_VOLUMEUP },
+ { 0xa10cb807, KEY_VOLUMEDOWN },
+ { 0xa10cd807, KEY_MUTE },
+ { 0xa10c040b, KEY_RECORD },
+ { 0xa10c7807, KEY_CHANNELUP },
+ { 0xa10cf807, KEY_CHANNELDOWN },
+ { 0x0085301f, KEY_CHANNELDOWN },
+
+ { 0xa10c840b, KEY_PLAY },
+ { 0xa10cc40b, KEY_PAUSE },
+ { 0xa10ca40b, KEY_SLOW },
+ { 0xa10c440b, KEY_REWIND },
+ { 0xa10c240b, KEY_FASTFORWARD },
+ { 0xa10c640b, KEY_PREVIOUS },
+ { 0xa10ce40b, KEY_NEXT }, /* ->| */
+
+ { 0xa10c220d, KEY_ZOOM }, /* Aspect */
+ { 0xa10c120d, KEY_STOP },
+ { 0xa10c520d, KEY_DVD }, /* DVD Menu */
+
+ { 0xa10c140b, KEY_NUMERIC_1 },
+ { 0xa10c940b, KEY_NUMERIC_2 },
+ { 0xa10c540b, KEY_NUMERIC_3 },
+ { 0xa10cd40b, KEY_NUMERIC_4 },
+ { 0xa10c340b, KEY_NUMERIC_5 },
+ { 0xa10cb40b, KEY_NUMERIC_6 },
+ { 0xa10c740b, KEY_NUMERIC_7 },
+ { 0xa10cf40b, KEY_NUMERIC_8 },
+ { 0x0085302f, KEY_NUMERIC_8 },
+ { 0xa10c0c03, KEY_NUMERIC_9 },
+ { 0xa10c8c03, KEY_NUMERIC_0 },
+ { 0xa10ccc03, KEY_ENTER },
+ { 0xa10c4c03, KEY_CLEAR },
+};
+
+static struct rc_map_list tivo_map = {
+ .map = {
+ .scan = tivo,
+ .size = ARRAY_SIZE(tivo),
+ .rc_type = RC_TYPE_NEC,
+ .name = RC_MAP_TIVO,
+ }
+};
+
+static int __init init_rc_map_tivo(void)
+{
+ return rc_map_register(&tivo_map);
+}
+
+static void __exit exit_rc_map_tivo(void)
+{
+ rc_map_unregister(&tivo_map);
+}
+
+module_init(init_rc_map_tivo)
+module_exit(exit_rc_map_tivo)
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Jarod Wilson <jarod@redhat.com>");
diff --git a/drivers/media/rc/keymaps/rc-winfast.c b/drivers/media/rc/keymaps/rc-winfast.c
index 0062ca2..d8a34c1 100644
--- a/drivers/media/rc/keymaps/rc-winfast.c
+++ b/drivers/media/rc/keymaps/rc-winfast.c
@@ -32,8 +32,8 @@
{ 0x02, KEY_TUNER }, /* TV/FM, not on Y0400052 */
{ 0x1e, KEY_VIDEO }, /* Video Source */
{ 0x16, KEY_INFO }, /* Display information */
- { 0x04, KEY_LEFT },
- { 0x08, KEY_RIGHT },
+ { 0x04, KEY_RIGHT },
+ { 0x08, KEY_LEFT },
{ 0x0c, KEY_UP },
{ 0x10, KEY_DOWN },
{ 0x03, KEY_ZOOM }, /* fullscreen */
diff --git a/drivers/media/rc/mceusb.c b/drivers/media/rc/mceusb.c
index 0c273ec..ad927fc 100644
--- a/drivers/media/rc/mceusb.c
+++ b/drivers/media/rc/mceusb.c
@@ -149,6 +149,8 @@
POLARIS_EVK,
CX_HYBRID_TV,
MULTIFUNCTION,
+ TIVO_KIT,
+ MCE_GEN2_NO_TX,
};
struct mceusb_model {
@@ -172,6 +174,10 @@
[MCE_GEN2] = {
.mce_gen2 = 1,
},
+ [MCE_GEN2_NO_TX] = {
+ .mce_gen2 = 1,
+ .no_tx = 1,
+ },
[MCE_GEN2_TX_INV] = {
.mce_gen2 = 1,
.tx_mask_normal = 1,
@@ -197,6 +203,10 @@
.mce_gen2 = 1,
.ir_intfnum = 2,
},
+ [TIVO_KIT] = {
+ .mce_gen2 = 1,
+ .rc_map = RC_MAP_TIVO,
+ },
};
static struct usb_device_id mceusb_dev_table[] = {
@@ -279,7 +289,8 @@
/* Formosa21 / eHome Infrared Receiver */
{ USB_DEVICE(VENDOR_FORMOSA, 0xe016) },
/* Formosa aim / Trust MCE Infrared Receiver */
- { USB_DEVICE(VENDOR_FORMOSA, 0xe017) },
+ { USB_DEVICE(VENDOR_FORMOSA, 0xe017),
+ .driver_info = MCE_GEN2_NO_TX },
/* Formosa Industrial Computing / Beanbag Emulation Device */
{ USB_DEVICE(VENDOR_FORMOSA, 0xe018) },
/* Formosa21 / eHome Infrared Receiver */
@@ -308,7 +319,8 @@
/* Northstar Systems, Inc. eHome Infrared Transceiver */
{ USB_DEVICE(VENDOR_NORTHSTAR, 0xe004) },
/* TiVo PC IR Receiver */
- { USB_DEVICE(VENDOR_TIVO, 0x2000) },
+ { USB_DEVICE(VENDOR_TIVO, 0x2000),
+ .driver_info = TIVO_KIT },
/* Conexant Hybrid TV "Shelby" Polaris SDK */
{ USB_DEVICE(VENDOR_CONEXANT, 0x58a1),
.driver_info = POLARIS_EVK },
@@ -603,11 +615,10 @@
}
/* request incoming or send outgoing usb packet - used to initialize remote */
-static void mce_request_packet(struct mceusb_dev *ir,
- struct usb_endpoint_descriptor *ep,
- unsigned char *data, int size, int urb_type)
+static void mce_request_packet(struct mceusb_dev *ir, unsigned char *data,
+ int size, int urb_type)
{
- int res;
+ int res, pipe;
struct urb *async_urb;
struct device *dev = ir->dev;
unsigned char *async_buf;
@@ -627,10 +638,11 @@
}
/* outbound data */
- usb_fill_int_urb(async_urb, ir->usbdev,
- usb_sndintpipe(ir->usbdev, ep->bEndpointAddress),
+ pipe = usb_sndintpipe(ir->usbdev,
+ ir->usb_ep_out->bEndpointAddress);
+ usb_fill_int_urb(async_urb, ir->usbdev, pipe,
async_buf, size, (usb_complete_t)mce_async_callback,
- ir, ep->bInterval);
+ ir, ir->usb_ep_out->bInterval);
memcpy(async_buf, data, size);
} else if (urb_type == MCEUSB_RX) {
@@ -658,12 +670,12 @@
static void mce_async_out(struct mceusb_dev *ir, unsigned char *data, int size)
{
- mce_request_packet(ir, ir->usb_ep_out, data, size, MCEUSB_TX);
+ mce_request_packet(ir, data, size, MCEUSB_TX);
}
static void mce_sync_in(struct mceusb_dev *ir, unsigned char *data, int size)
{
- mce_request_packet(ir, ir->usb_ep_in, data, size, MCEUSB_RX);
+ mce_request_packet(ir, data, size, MCEUSB_RX);
}
/* Send data out the IR blaster port(s) */
diff --git a/drivers/media/rc/nuvoton-cir.c b/drivers/media/rc/nuvoton-cir.c
index d4d6449..bf3060e 100644
--- a/drivers/media/rc/nuvoton-cir.c
+++ b/drivers/media/rc/nuvoton-cir.c
@@ -37,8 +37,6 @@
#include "nuvoton-cir.h"
-static char *chip_id = "w836x7hg";
-
/* write val to config reg */
static inline void nvt_cr_write(struct nvt_dev *nvt, u8 val, u8 reg)
{
@@ -233,6 +231,8 @@
unsigned long flags;
u8 chip_major, chip_minor;
int ret = 0;
+ char chip_id[12];
+ bool chip_unknown = false;
nvt_efm_enable(nvt);
@@ -246,15 +246,39 @@
}
chip_minor = nvt_cr_read(nvt, CR_CHIP_ID_LO);
- nvt_dbg("%s: chip id: 0x%02x 0x%02x", chip_id, chip_major, chip_minor);
- if (chip_major != CHIP_ID_HIGH ||
- (chip_minor != CHIP_ID_LOW && chip_minor != CHIP_ID_LOW2)) {
- nvt_pr(KERN_ERR, "%s: unsupported chip, id: 0x%02x 0x%02x",
- chip_id, chip_major, chip_minor);
- ret = -ENODEV;
+ /* these are the known working chip revisions... */
+ switch (chip_major) {
+ case CHIP_ID_HIGH_667:
+ strcpy(chip_id, "w83667hg\0");
+ if (chip_minor != CHIP_ID_LOW_667)
+ chip_unknown = true;
+ break;
+ case CHIP_ID_HIGH_677B:
+ strcpy(chip_id, "w83677hg\0");
+ if (chip_minor != CHIP_ID_LOW_677B2 &&
+ chip_minor != CHIP_ID_LOW_677B3)
+ chip_unknown = true;
+ break;
+ case CHIP_ID_HIGH_677C:
+ strcpy(chip_id, "w83677hg-c\0");
+ if (chip_minor != CHIP_ID_LOW_677C)
+ chip_unknown = true;
+ break;
+ default:
+ strcpy(chip_id, "w836x7hg\0");
+ chip_unknown = true;
+ break;
}
+ /* warn, but still let the driver load, if we don't know this chip */
+ if (chip_unknown)
+ nvt_pr(KERN_WARNING, "%s: unknown chip, id: 0x%02x 0x%02x, "
+ "it may not work...", chip_id, chip_major, chip_minor);
+ else
+ nvt_dbg("%s: chip id: 0x%02x 0x%02x",
+ chip_id, chip_major, chip_minor);
+
nvt_efm_disable(nvt);
spin_lock_irqsave(&nvt->nvt_lock, flags);
@@ -267,13 +291,23 @@
static void nvt_cir_ldev_init(struct nvt_dev *nvt)
{
- u8 val;
+ u8 val, psreg, psmask, psval;
- /* output pin selection (Pin95=CIRRX, Pin96=CIRTX1, WB enabled */
- val = nvt_cr_read(nvt, CR_OUTPUT_PIN_SEL);
- val &= OUTPUT_PIN_SEL_MASK;
- val |= (OUTPUT_ENABLE_CIR | OUTPUT_ENABLE_CIRWB);
- nvt_cr_write(nvt, val, CR_OUTPUT_PIN_SEL);
+ if (nvt->chip_major == CHIP_ID_HIGH_667) {
+ psreg = CR_MULTIFUNC_PIN_SEL;
+ psmask = MULTIFUNC_PIN_SEL_MASK;
+ psval = MULTIFUNC_ENABLE_CIR | MULTIFUNC_ENABLE_CIRWB;
+ } else {
+ psreg = CR_OUTPUT_PIN_SEL;
+ psmask = OUTPUT_PIN_SEL_MASK;
+ psval = OUTPUT_ENABLE_CIR | OUTPUT_ENABLE_CIRWB;
+ }
+
+ /* output pin selection: enable CIR, with WB sensor enabled */
+ val = nvt_cr_read(nvt, psreg);
+ val &= psmask;
+ val |= psval;
+ nvt_cr_write(nvt, val, psreg);
/* Select CIR logical device and enable */
nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
@@ -640,7 +674,7 @@
rawir.pulse ? "pulse" : "space",
rawir.duration);
- ir_raw_event_store(nvt->rdev, &rawir);
+ ir_raw_event_store_with_filter(nvt->rdev, &rawir);
}
/*
@@ -1070,18 +1104,20 @@
rdev->tx_ir = nvt_tx_ir;
rdev->s_tx_carrier = nvt_set_tx_carrier;
rdev->input_name = "Nuvoton w836x7hg Infrared Remote Transceiver";
+ rdev->input_phys = "nuvoton/cir0";
rdev->input_id.bustype = BUS_HOST;
rdev->input_id.vendor = PCI_VENDOR_ID_WINBOND2;
rdev->input_id.product = nvt->chip_major;
rdev->input_id.version = nvt->chip_minor;
+ rdev->dev.parent = &pdev->dev;
rdev->driver_name = NVT_DRIVER_NAME;
rdev->map_name = RC_MAP_RC6_MCE;
+ rdev->timeout = US_TO_NS(1000);
+ /* rx resolution is hardwired to 50us atm, 1, 25, 100 also possible */
+ rdev->rx_resolution = US_TO_NS(CIR_SAMPLE_PERIOD);
#if 0
rdev->min_timeout = XYZ;
rdev->max_timeout = XYZ;
- rdev->timeout = XYZ;
- /* rx resolution is hardwired to 50us atm, 1, 25, 100 also possible */
- rdev->rx_resolution = XYZ;
/* tx bits */
rdev->tx_resolution = XYZ;
#endif
@@ -1090,8 +1126,7 @@
if (ret)
goto failure;
- device_set_wakeup_capable(&pdev->dev, 1);
- device_set_wakeup_enable(&pdev->dev, 1);
+ device_init_wakeup(&pdev->dev, true);
nvt->rdev = rdev;
nvt_pr(KERN_NOTICE, "driver has been successfully loaded\n");
if (debug) {
diff --git a/drivers/media/rc/nuvoton-cir.h b/drivers/media/rc/nuvoton-cir.h
index 048135e..379795d 100644
--- a/drivers/media/rc/nuvoton-cir.h
+++ b/drivers/media/rc/nuvoton-cir.h
@@ -330,9 +330,13 @@
#define EFER_EFM_DISABLE 0xaa
/* Chip IDs found in CR_CHIP_ID_{HI,LO} */
-#define CHIP_ID_HIGH 0xb4
-#define CHIP_ID_LOW 0x72
-#define CHIP_ID_LOW2 0x73
+#define CHIP_ID_HIGH_667 0xa5
+#define CHIP_ID_HIGH_677B 0xb4
+#define CHIP_ID_HIGH_677C 0xc3
+#define CHIP_ID_LOW_667 0x13
+#define CHIP_ID_LOW_677B2 0x72
+#define CHIP_ID_LOW_677B3 0x73
+#define CHIP_ID_LOW_677C 0x33
/* Config regs we need to care about */
#define CR_SOFTWARE_RESET 0x02
@@ -341,6 +345,7 @@
#define CR_CHIP_ID_LO 0x21
#define CR_DEV_POWER_DOWN 0x22 /* bit 2 is CIR power, default power on */
#define CR_OUTPUT_PIN_SEL 0x27
+#define CR_MULTIFUNC_PIN_SEL 0x2c
#define CR_LOGICAL_DEV_EN 0x30 /* valid for all logical devices */
/* next three regs valid for both the CIR and CIR_WAKE logical devices */
#define CR_CIR_BASE_ADDR_HI 0x60
@@ -364,10 +369,16 @@
#define CIR_INTR_MOUSE_IRQ_BIT 0x80
#define PME_INTR_CIR_PASS_BIT 0x08
+/* w83677hg CIR pin config */
#define OUTPUT_PIN_SEL_MASK 0xbc
#define OUTPUT_ENABLE_CIR 0x01 /* Pin95=CIRRX, Pin96=CIRTX1 */
#define OUTPUT_ENABLE_CIRWB 0x40 /* enable wide-band sensor */
+/* w83667hg CIR pin config */
+#define MULTIFUNC_PIN_SEL_MASK 0x1f
+#define MULTIFUNC_ENABLE_CIR 0x80 /* Pin75=CIRRX, Pin76=CIRTX1 */
+#define MULTIFUNC_ENABLE_CIRWB 0x20 /* enable wide-band sensor */
+
/* MCE CIR signal length, related on sample period */
/* MCE CIR controller signal length: about 43ms
diff --git a/drivers/media/rc/rc-loopback.c b/drivers/media/rc/rc-loopback.c
index 49cee61..cc846b2 100644
--- a/drivers/media/rc/rc-loopback.c
+++ b/drivers/media/rc/rc-loopback.c
@@ -146,6 +146,12 @@
if (rawir.duration)
ir_raw_event_store_with_filter(dev, &rawir);
}
+
+ /* Fake a silence long enough to cause us to go idle */
+ rawir.pulse = false;
+ rawir.duration = dev->timeout;
+ ir_raw_event_store_with_filter(dev, &rawir);
+
ir_raw_event_handle(dev);
out:
diff --git a/drivers/media/rc/rc-main.c b/drivers/media/rc/rc-main.c
index a270664..f57cd56 100644
--- a/drivers/media/rc/rc-main.c
+++ b/drivers/media/rc/rc-main.c
@@ -749,6 +749,9 @@
* it is trigged by reading /sys/class/rc/rc?/protocols.
* It returns the protocol names of supported protocols.
* Enabled protocols are printed in brackets.
+ *
+ * dev->lock is taken to guard against races between device
+ * registration, store_protocols and show_protocols.
*/
static ssize_t show_protocols(struct device *device,
struct device_attribute *mattr, char *buf)
@@ -762,6 +765,8 @@
if (!dev)
return -EINVAL;
+ mutex_lock(&dev->lock);
+
if (dev->driver_type == RC_DRIVER_SCANCODE) {
enabled = dev->rc_map.rc_type;
allowed = dev->allowed_protos;
@@ -784,6 +789,9 @@
if (tmp != buf)
tmp--;
*tmp = '\n';
+
+ mutex_unlock(&dev->lock);
+
return tmp + 1 - buf;
}
@@ -802,6 +810,9 @@
* Writing "none" will disable all protocols.
* Returns -EINVAL if an invalid protocol combination or unknown protocol name
* is used, otherwise @len.
+ *
+ * dev->lock is taken to guard against races between device
+ * registration, store_protocols and show_protocols.
*/
static ssize_t store_protocols(struct device *device,
struct device_attribute *mattr,
@@ -815,18 +826,22 @@
u64 mask;
int rc, i, count = 0;
unsigned long flags;
+ ssize_t ret;
/* Device is being removed */
if (!dev)
return -EINVAL;
+ mutex_lock(&dev->lock);
+
if (dev->driver_type == RC_DRIVER_SCANCODE)
type = dev->rc_map.rc_type;
else if (dev->raw)
type = dev->raw->enabled_protocols;
else {
IR_dprintk(1, "Protocol switching not supported\n");
- return -EINVAL;
+ ret = -EINVAL;
+ goto out;
}
while ((tmp = strsep((char **) &data, " \n")) != NULL) {
@@ -860,7 +875,8 @@
}
if (i == ARRAY_SIZE(proto_names)) {
IR_dprintk(1, "Unknown protocol: '%s'\n", tmp);
- return -EINVAL;
+ ret = -EINVAL;
+ goto out;
}
count++;
}
@@ -875,7 +891,8 @@
if (!count) {
IR_dprintk(1, "Protocol not specified\n");
- return -EINVAL;
+ ret = -EINVAL;
+ goto out;
}
if (dev->change_protocol) {
@@ -883,7 +900,8 @@
if (rc < 0) {
IR_dprintk(1, "Error setting protocols to 0x%llx\n",
(long long)type);
- return -EINVAL;
+ ret = -EINVAL;
+ goto out;
}
}
@@ -898,7 +916,11 @@
IR_dprintk(1, "Current protocol(s): 0x%llx\n",
(long long)type);
- return len;
+ ret = len;
+
+out:
+ mutex_unlock(&dev->lock);
+ return ret;
}
static void rc_dev_release(struct device *device)
@@ -974,6 +996,7 @@
spin_lock_init(&dev->rc_map.lock);
spin_lock_init(&dev->keylock);
+ mutex_init(&dev->lock);
setup_timer(&dev->timer_keyup, ir_timer_keyup, (unsigned long)dev);
dev->dev.type = &rc_dev_type;
@@ -1019,12 +1042,21 @@
if (dev->close)
dev->input_dev->close = ir_close;
+ /*
+ * Take the lock here, as the device sysfs node will appear
+ * when device_add() is called, which may trigger an ir-keytable udev
+ * rule, which will in turn call show_protocols and access either
+ * dev->rc_map.rc_type or dev->raw->enabled_protocols before it has
+ * been initialized.
+ */
+ mutex_lock(&dev->lock);
+
dev->devno = (unsigned long)(atomic_inc_return(&devno) - 1);
dev_set_name(&dev->dev, "rc%ld", dev->devno);
dev_set_drvdata(&dev->dev, dev);
rc = device_add(&dev->dev);
if (rc)
- return rc;
+ goto out_unlock;
rc = ir_setkeytable(dev, rc_map);
if (rc)
@@ -1046,6 +1078,13 @@
*/
dev->input_dev->rep[REP_DELAY] = 500;
+ /*
+ * As a repeat event on protocols like RC-5 and NEC take as long as
+ * 110/114ms, using 33ms as a repeat period is not the right thing
+ * to do.
+ */
+ dev->input_dev->rep[REP_PERIOD] = 125;
+
path = kobject_get_path(&dev->dev.kobj, GFP_KERNEL);
printk(KERN_INFO "%s: %s as %s\n",
dev_name(&dev->dev),
@@ -1058,6 +1097,7 @@
if (rc < 0)
goto out_input;
}
+ mutex_unlock(&dev->lock);
if (dev->change_protocol) {
rc = dev->change_protocol(dev, rc_map->rc_type);
@@ -1083,6 +1123,8 @@
ir_free_table(&dev->rc_map);
out_dev:
device_del(&dev->dev);
+out_unlock:
+ mutex_unlock(&dev->lock);
return rc;
}
EXPORT_SYMBOL_GPL(rc_register_device);
diff --git a/drivers/media/rc/redrat3.c b/drivers/media/rc/redrat3.c
new file mode 100644
index 0000000..5147767
--- /dev/null
+++ b/drivers/media/rc/redrat3.c
@@ -0,0 +1,1344 @@
+/*
+ * USB RedRat3 IR Transceiver rc-core driver
+ *
+ * Copyright (c) 2011 by Jarod Wilson <jarod@redhat.com>
+ * based heavily on the work of Stephen Cox, with additional
+ * help from RedRat Ltd.
+ *
+ * This driver began life based an an old version of the first-generation
+ * lirc_mceusb driver from the lirc 0.7.2 distribution. It was then
+ * significantly rewritten by Stephen Cox with the aid of RedRat Ltd's
+ * Chris Dodge.
+ *
+ * The driver was then ported to rc-core and significantly rewritten again,
+ * by Jarod, using the in-kernel mceusb driver as a guide, after an initial
+ * port effort was started by Stephen.
+ *
+ * TODO LIST:
+ * - fix lirc not showing repeats properly
+ * --
+ *
+ * The RedRat3 is a USB transceiver with both send & receive,
+ * with 2 separate sensors available for receive to enable
+ * both good long range reception for general use, and good
+ * short range reception when required for learning a signal.
+ *
+ * http://www.redrat.co.uk/
+ *
+ * It uses its own little protocol to communicate, the required
+ * parts of which are embedded within this driver.
+ * --
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#include <linux/device.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/usb.h>
+#include <linux/usb/input.h>
+#include <media/rc-core.h>
+
+/* Driver Information */
+#define DRIVER_VERSION "0.70"
+#define DRIVER_AUTHOR "Jarod Wilson <jarod@redhat.com>"
+#define DRIVER_AUTHOR2 "The Dweller, Stephen Cox"
+#define DRIVER_DESC "RedRat3 USB IR Transceiver Driver"
+#define DRIVER_NAME "redrat3"
+
+/* module parameters */
+#ifdef CONFIG_USB_DEBUG
+static int debug = 1;
+#else
+static int debug;
+#endif
+
+#define RR3_DEBUG_STANDARD 0x1
+#define RR3_DEBUG_FUNCTION_TRACE 0x2
+
+#define rr3_dbg(dev, fmt, ...) \
+ do { \
+ if (debug & RR3_DEBUG_STANDARD) \
+ dev_info(dev, fmt, ## __VA_ARGS__); \
+ } while (0)
+
+#define rr3_ftr(dev, fmt, ...) \
+ do { \
+ if (debug & RR3_DEBUG_FUNCTION_TRACE) \
+ dev_info(dev, fmt, ## __VA_ARGS__); \
+ } while (0)
+
+/* bulk data transfer types */
+#define RR3_ERROR 0x01
+#define RR3_MOD_SIGNAL_IN 0x20
+#define RR3_MOD_SIGNAL_OUT 0x21
+
+/* Get the RR firmware version */
+#define RR3_FW_VERSION 0xb1
+#define RR3_FW_VERSION_LEN 64
+/* Send encoded signal bulk-sent earlier*/
+#define RR3_TX_SEND_SIGNAL 0xb3
+#define RR3_SET_IR_PARAM 0xb7
+#define RR3_GET_IR_PARAM 0xb8
+/* Blink the red LED on the device */
+#define RR3_BLINK_LED 0xb9
+/* Read serial number of device */
+#define RR3_READ_SER_NO 0xba
+#define RR3_SER_NO_LEN 4
+/* Start capture with the RC receiver */
+#define RR3_RC_DET_ENABLE 0xbb
+/* Stop capture with the RC receiver */
+#define RR3_RC_DET_DISABLE 0xbc
+/* Return the status of RC detector capture */
+#define RR3_RC_DET_STATUS 0xbd
+/* Reset redrat */
+#define RR3_RESET 0xa0
+
+/* Max number of lengths in the signal. */
+#define RR3_IR_IO_MAX_LENGTHS 0x01
+/* Periods to measure mod. freq. */
+#define RR3_IR_IO_PERIODS_MF 0x02
+/* Size of memory for main signal data */
+#define RR3_IR_IO_SIG_MEM_SIZE 0x03
+/* Delta value when measuring lengths */
+#define RR3_IR_IO_LENGTH_FUZZ 0x04
+/* Timeout for end of signal detection */
+#define RR3_IR_IO_SIG_TIMEOUT 0x05
+/* Minumum value for pause recognition. */
+#define RR3_IR_IO_MIN_PAUSE 0x06
+
+/* Clock freq. of EZ-USB chip */
+#define RR3_CLK 24000000
+/* Clock periods per timer count */
+#define RR3_CLK_PER_COUNT 12
+/* (RR3_CLK / RR3_CLK_PER_COUNT) */
+#define RR3_CLK_CONV_FACTOR 2000000
+/* USB bulk-in IR data endpoint address */
+#define RR3_BULK_IN_EP_ADDR 0x82
+
+/* Raw Modulated signal data value offsets */
+#define RR3_PAUSE_OFFSET 0
+#define RR3_FREQ_COUNT_OFFSET 4
+#define RR3_NUM_PERIOD_OFFSET 6
+#define RR3_MAX_LENGTHS_OFFSET 8
+#define RR3_NUM_LENGTHS_OFFSET 9
+#define RR3_MAX_SIGS_OFFSET 10
+#define RR3_NUM_SIGS_OFFSET 12
+#define RR3_REPEATS_OFFSET 14
+
+/* Size of the fixed-length portion of the signal */
+#define RR3_HEADER_LENGTH 15
+#define RR3_DRIVER_MAXLENS 128
+#define RR3_MAX_SIG_SIZE 512
+#define RR3_MAX_BUF_SIZE \
+ ((2 * RR3_HEADER_LENGTH) + RR3_DRIVER_MAXLENS + RR3_MAX_SIG_SIZE)
+#define RR3_TIME_UNIT 50
+#define RR3_END_OF_SIGNAL 0x7f
+#define RR3_TX_HEADER_OFFSET 4
+#define RR3_TX_TRAILER_LEN 2
+#define RR3_RX_MIN_TIMEOUT 5
+#define RR3_RX_MAX_TIMEOUT 2000
+
+/* The 8051's CPUCS Register address */
+#define RR3_CPUCS_REG_ADDR 0x7f92
+
+#define USB_RR3USB_VENDOR_ID 0x112a
+#define USB_RR3USB_PRODUCT_ID 0x0001
+#define USB_RR3IIUSB_PRODUCT_ID 0x0005
+
+/* table of devices that work with this driver */
+static struct usb_device_id redrat3_dev_table[] = {
+ /* Original version of the RedRat3 */
+ {USB_DEVICE(USB_RR3USB_VENDOR_ID, USB_RR3USB_PRODUCT_ID)},
+ /* Second Version/release of the RedRat3 - RetRat3-II */
+ {USB_DEVICE(USB_RR3USB_VENDOR_ID, USB_RR3IIUSB_PRODUCT_ID)},
+ {} /* Terminating entry */
+};
+
+/* Structure to hold all of our device specific stuff */
+struct redrat3_dev {
+ /* core device bits */
+ struct rc_dev *rc;
+ struct device *dev;
+
+ /* save off the usb device pointer */
+ struct usb_device *udev;
+
+ /* the receive endpoint */
+ struct usb_endpoint_descriptor *ep_in;
+ /* the buffer to receive data */
+ unsigned char *bulk_in_buf;
+ /* urb used to read ir data */
+ struct urb *read_urb;
+
+ /* the send endpoint */
+ struct usb_endpoint_descriptor *ep_out;
+ /* the buffer to send data */
+ unsigned char *bulk_out_buf;
+ /* the urb used to send data */
+ struct urb *write_urb;
+
+ /* usb dma */
+ dma_addr_t dma_in;
+ dma_addr_t dma_out;
+
+ /* true if write urb is busy */
+ bool write_busy;
+ /* wait for the write to finish */
+ struct completion write_finished;
+
+ /* locks this structure */
+ struct mutex lock;
+
+ /* rx signal timeout timer */
+ struct timer_list rx_timeout;
+
+ /* Is the device currently receiving? */
+ bool recv_in_progress;
+ /* is the detector enabled*/
+ bool det_enabled;
+ /* Is the device currently transmitting?*/
+ bool transmitting;
+
+ /* store for current packet */
+ char pbuf[RR3_MAX_BUF_SIZE];
+ u16 pktlen;
+ u16 pkttype;
+ u16 bytes_read;
+ /* indicate whether we are going to reprocess
+ * the USB callback with a bigger buffer */
+ int buftoosmall;
+ char *datap;
+
+ u32 carrier;
+
+ char name[128];
+ char phys[64];
+};
+
+/* All incoming data buffers adhere to a very specific data format */
+struct redrat3_signal_header {
+ u16 length; /* Length of data being transferred */
+ u16 transfer_type; /* Type of data transferred */
+ u32 pause; /* Pause between main and repeat signals */
+ u16 mod_freq_count; /* Value of timer on mod. freq. measurement */
+ u16 no_periods; /* No. of periods over which mod. freq. is measured */
+ u8 max_lengths; /* Max no. of lengths (i.e. size of array) */
+ u8 no_lengths; /* Actual no. of elements in lengths array */
+ u16 max_sig_size; /* Max no. of values in signal data array */
+ u16 sig_size; /* Acuto no. of values in signal data array */
+ u8 no_repeats; /* No. of repeats of repeat signal section */
+ /* Here forward is the lengths and signal data */
+};
+
+static void redrat3_dump_signal_header(struct redrat3_signal_header *header)
+{
+ pr_info("%s:\n", __func__);
+ pr_info(" * length: %u, transfer_type: 0x%02x\n",
+ header->length, header->transfer_type);
+ pr_info(" * pause: %u, freq_count: %u, no_periods: %u\n",
+ header->pause, header->mod_freq_count, header->no_periods);
+ pr_info(" * lengths: %u (max: %u)\n",
+ header->no_lengths, header->max_lengths);
+ pr_info(" * sig_size: %u (max: %u)\n",
+ header->sig_size, header->max_sig_size);
+ pr_info(" * repeats: %u\n", header->no_repeats);
+}
+
+static void redrat3_dump_signal_data(char *buffer, u16 len)
+{
+ int offset, i;
+ char *data_vals;
+
+ pr_info("%s:", __func__);
+
+ offset = RR3_TX_HEADER_OFFSET + RR3_HEADER_LENGTH
+ + (RR3_DRIVER_MAXLENS * sizeof(u16));
+
+ /* read RR3_DRIVER_MAXLENS from ctrl msg */
+ data_vals = buffer + offset;
+
+ for (i = 0; i < len; i++) {
+ if (i % 10 == 0)
+ pr_cont("\n * ");
+ pr_cont("%02x ", *data_vals++);
+ }
+
+ pr_cont("\n");
+}
+
+/*
+ * redrat3_issue_async
+ *
+ * Issues an async read to the ir data in port..
+ * sets the callback to be redrat3_handle_async
+ */
+static void redrat3_issue_async(struct redrat3_dev *rr3)
+{
+ int res;
+
+ rr3_ftr(rr3->dev, "Entering %s\n", __func__);
+
+ if (!rr3->det_enabled) {
+ dev_warn(rr3->dev, "not issuing async read, "
+ "detector not enabled\n");
+ return;
+ }
+
+ memset(rr3->bulk_in_buf, 0, rr3->ep_in->wMaxPacketSize);
+ res = usb_submit_urb(rr3->read_urb, GFP_ATOMIC);
+ if (res)
+ rr3_dbg(rr3->dev, "%s: receive request FAILED! "
+ "(res %d, len %d)\n", __func__, res,
+ rr3->read_urb->transfer_buffer_length);
+}
+
+static void redrat3_dump_fw_error(struct redrat3_dev *rr3, int code)
+{
+ if (!rr3->transmitting && (code != 0x40))
+ dev_info(rr3->dev, "fw error code 0x%02x: ", code);
+
+ switch (code) {
+ case 0x00:
+ pr_cont("No Error\n");
+ break;
+
+ /* Codes 0x20 through 0x2f are IR Firmware Errors */
+ case 0x20:
+ pr_cont("Initial signal pulse not long enough "
+ "to measure carrier frequency\n");
+ break;
+ case 0x21:
+ pr_cont("Not enough length values allocated for signal\n");
+ break;
+ case 0x22:
+ pr_cont("Not enough memory allocated for signal data\n");
+ break;
+ case 0x23:
+ pr_cont("Too many signal repeats\n");
+ break;
+ case 0x28:
+ pr_cont("Insufficient memory available for IR signal "
+ "data memory allocation\n");
+ break;
+ case 0x29:
+ pr_cont("Insufficient memory available "
+ "for IrDa signal data memory allocation\n");
+ break;
+
+ /* Codes 0x30 through 0x3f are USB Firmware Errors */
+ case 0x30:
+ pr_cont("Insufficient memory available for bulk "
+ "transfer structure\n");
+ break;
+
+ /*
+ * Other error codes... These are primarily errors that can occur in
+ * the control messages sent to the redrat
+ */
+ case 0x40:
+ if (!rr3->transmitting)
+ pr_cont("Signal capture has been terminated\n");
+ break;
+ case 0x41:
+ pr_cont("Attempt to set/get and unknown signal I/O "
+ "algorithm parameter\n");
+ break;
+ case 0x42:
+ pr_cont("Signal capture already started\n");
+ break;
+
+ default:
+ pr_cont("Unknown Error\n");
+ break;
+ }
+}
+
+static u32 redrat3_val_to_mod_freq(struct redrat3_signal_header *ph)
+{
+ u32 mod_freq = 0;
+
+ if (ph->mod_freq_count != 0)
+ mod_freq = (RR3_CLK * ph->no_periods) /
+ (ph->mod_freq_count * RR3_CLK_PER_COUNT);
+
+ return mod_freq;
+}
+
+/* this function scales down the figures for the same result... */
+static u32 redrat3_len_to_us(u32 length)
+{
+ u32 biglen = length * 1000;
+ u32 divisor = (RR3_CLK_CONV_FACTOR) / 1000;
+ u32 result = (u32) (biglen / divisor);
+
+ /* don't allow zero lengths to go back, breaks lirc */
+ return result ? result : 1;
+}
+
+/*
+ * convert us back into redrat3 lengths
+ *
+ * length * 1000 length * 1000000
+ * ------------- = ---------------- = micro
+ * rr3clk / 1000 rr3clk
+
+ * 6 * 2 4 * 3 micro * rr3clk micro * rr3clk / 1000
+ * ----- = 4 ----- = 6 -------------- = len ---------------------
+ * 3 2 1000000 1000
+ */
+static u32 redrat3_us_to_len(u32 microsec)
+{
+ u32 result;
+ u32 divisor;
+
+ microsec &= IR_MAX_DURATION;
+ divisor = (RR3_CLK_CONV_FACTOR / 1000);
+ result = (u32)(microsec * divisor) / 1000;
+
+ /* don't allow zero lengths to go back, breaks lirc */
+ return result ? result : 1;
+
+}
+
+/* timer callback to send long trailing space on receive timeout */
+static void redrat3_rx_timeout(unsigned long data)
+{
+ struct redrat3_dev *rr3 = (struct redrat3_dev *)data;
+ DEFINE_IR_RAW_EVENT(rawir);
+
+ rawir.pulse = false;
+ rawir.duration = rr3->rc->timeout;
+ rr3_dbg(rr3->dev, "storing trailing space with duration %d\n",
+ rawir.duration);
+ ir_raw_event_store_with_filter(rr3->rc, &rawir);
+
+ rr3_dbg(rr3->dev, "calling ir_raw_event_handle\n");
+ ir_raw_event_handle(rr3->rc);
+
+ rr3_dbg(rr3->dev, "calling ir_raw_event_reset\n");
+ ir_raw_event_reset(rr3->rc);
+}
+
+static void redrat3_process_ir_data(struct redrat3_dev *rr3)
+{
+ DEFINE_IR_RAW_EVENT(rawir);
+ struct redrat3_signal_header header;
+ struct device *dev;
+ int i;
+ unsigned long delay;
+ u32 mod_freq, single_len;
+ u16 *len_vals;
+ u8 *data_vals;
+ u32 tmp32;
+ u16 tmp16;
+ char *sig_data;
+
+ if (!rr3) {
+ pr_err("%s called with no context!\n", __func__);
+ return;
+ }
+
+ rr3_ftr(rr3->dev, "Entered %s\n", __func__);
+
+ dev = rr3->dev;
+ sig_data = rr3->pbuf;
+
+ header.length = rr3->pktlen;
+ header.transfer_type = rr3->pkttype;
+
+ /* Sanity check */
+ if (!(header.length >= RR3_HEADER_LENGTH))
+ dev_warn(dev, "read returned less than rr3 header len\n");
+
+ delay = usecs_to_jiffies(rr3->rc->timeout / 1000);
+ mod_timer(&rr3->rx_timeout, jiffies + delay);
+
+ memcpy(&tmp32, sig_data + RR3_PAUSE_OFFSET, sizeof(tmp32));
+ header.pause = be32_to_cpu(tmp32);
+
+ memcpy(&tmp16, sig_data + RR3_FREQ_COUNT_OFFSET, sizeof(tmp16));
+ header.mod_freq_count = be16_to_cpu(tmp16);
+
+ memcpy(&tmp16, sig_data + RR3_NUM_PERIOD_OFFSET, sizeof(tmp16));
+ header.no_periods = be16_to_cpu(tmp16);
+
+ header.max_lengths = sig_data[RR3_MAX_LENGTHS_OFFSET];
+ header.no_lengths = sig_data[RR3_NUM_LENGTHS_OFFSET];
+
+ memcpy(&tmp16, sig_data + RR3_MAX_SIGS_OFFSET, sizeof(tmp16));
+ header.max_sig_size = be16_to_cpu(tmp16);
+
+ memcpy(&tmp16, sig_data + RR3_NUM_SIGS_OFFSET, sizeof(tmp16));
+ header.sig_size = be16_to_cpu(tmp16);
+
+ header.no_repeats= sig_data[RR3_REPEATS_OFFSET];
+
+ if (debug) {
+ redrat3_dump_signal_header(&header);
+ redrat3_dump_signal_data(sig_data, header.sig_size);
+ }
+
+ mod_freq = redrat3_val_to_mod_freq(&header);
+ rr3_dbg(dev, "Got mod_freq of %u\n", mod_freq);
+
+ /* Here we pull out the 'length' values from the signal */
+ len_vals = (u16 *)(sig_data + RR3_HEADER_LENGTH);
+
+ data_vals = sig_data + RR3_HEADER_LENGTH +
+ (header.max_lengths * sizeof(u16));
+
+ /* process each rr3 encoded byte into an int */
+ for (i = 0; i < header.sig_size; i++) {
+ u16 val = len_vals[data_vals[i]];
+ single_len = redrat3_len_to_us((u32)be16_to_cpu(val));
+
+ /* cap the value to IR_MAX_DURATION */
+ single_len &= IR_MAX_DURATION;
+
+ /* we should always get pulse/space/pulse/space samples */
+ if (i % 2)
+ rawir.pulse = false;
+ else
+ rawir.pulse = true;
+
+ rawir.duration = US_TO_NS(single_len);
+ rr3_dbg(dev, "storing %s with duration %d (i: %d)\n",
+ rawir.pulse ? "pulse" : "space", rawir.duration, i);
+ ir_raw_event_store_with_filter(rr3->rc, &rawir);
+ }
+
+ /* add a trailing space, if need be */
+ if (i % 2) {
+ rawir.pulse = false;
+ /* this duration is made up, and may not be ideal... */
+ rawir.duration = rr3->rc->timeout / 2;
+ rr3_dbg(dev, "storing trailing space with duration %d\n",
+ rawir.duration);
+ ir_raw_event_store_with_filter(rr3->rc, &rawir);
+ }
+
+ rr3_dbg(dev, "calling ir_raw_event_handle\n");
+ ir_raw_event_handle(rr3->rc);
+
+ return;
+}
+
+/* Util fn to send rr3 cmds */
+static u8 redrat3_send_cmd(int cmd, struct redrat3_dev *rr3)
+{
+ struct usb_device *udev;
+ u8 *data;
+ int res;
+
+ data = kzalloc(sizeof(u8), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ udev = rr3->udev;
+ res = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), cmd,
+ USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_DIR_IN,
+ 0x0000, 0x0000, data, sizeof(u8), HZ * 10);
+
+ if (res < 0) {
+ dev_err(rr3->dev, "%s: Error sending rr3 cmd res %d, data %d",
+ __func__, res, *data);
+ res = -EIO;
+ } else
+ res = (u8)data[0];
+
+ kfree(data);
+
+ return res;
+}
+
+/* Enables the long range detector and starts async receive */
+static int redrat3_enable_detector(struct redrat3_dev *rr3)
+{
+ struct device *dev = rr3->dev;
+ u8 ret;
+
+ rr3_ftr(dev, "Entering %s\n", __func__);
+
+ ret = redrat3_send_cmd(RR3_RC_DET_ENABLE, rr3);
+ if (ret != 0)
+ dev_dbg(dev, "%s: unexpected ret of %d\n",
+ __func__, ret);
+
+ ret = redrat3_send_cmd(RR3_RC_DET_STATUS, rr3);
+ if (ret != 1) {
+ dev_err(dev, "%s: detector status: %d, should be 1\n",
+ __func__, ret);
+ return -EIO;
+ }
+
+ rr3->det_enabled = true;
+ redrat3_issue_async(rr3);
+
+ return 0;
+}
+
+/* Disables the rr3 long range detector */
+static void redrat3_disable_detector(struct redrat3_dev *rr3)
+{
+ struct device *dev = rr3->dev;
+ u8 ret;
+
+ rr3_ftr(dev, "Entering %s\n", __func__);
+
+ ret = redrat3_send_cmd(RR3_RC_DET_DISABLE, rr3);
+ if (ret != 0)
+ dev_err(dev, "%s: failure!\n", __func__);
+
+ ret = redrat3_send_cmd(RR3_RC_DET_STATUS, rr3);
+ if (ret != 0)
+ dev_warn(dev, "%s: detector status: %d, should be 0\n",
+ __func__, ret);
+
+ rr3->det_enabled = false;
+}
+
+static inline void redrat3_delete(struct redrat3_dev *rr3,
+ struct usb_device *udev)
+{
+ rr3_ftr(rr3->dev, "%s cleaning up\n", __func__);
+ usb_kill_urb(rr3->read_urb);
+ usb_kill_urb(rr3->write_urb);
+
+ usb_free_urb(rr3->read_urb);
+ usb_free_urb(rr3->write_urb);
+
+ usb_free_coherent(udev, rr3->ep_in->wMaxPacketSize,
+ rr3->bulk_in_buf, rr3->dma_in);
+ usb_free_coherent(udev, rr3->ep_out->wMaxPacketSize,
+ rr3->bulk_out_buf, rr3->dma_out);
+
+ kfree(rr3);
+}
+
+static u32 redrat3_get_timeout(struct device *dev,
+ struct rc_dev *rc, struct usb_device *udev)
+{
+ u32 *tmp;
+ u32 timeout = MS_TO_NS(150); /* a sane default, if things go haywire */
+ int len, ret, pipe;
+
+ len = sizeof(*tmp);
+ tmp = kzalloc(len, GFP_KERNEL);
+ if (!tmp) {
+ dev_warn(dev, "Memory allocation faillure\n");
+ return timeout;
+ }
+
+ pipe = usb_rcvctrlpipe(udev, 0);
+ ret = usb_control_msg(udev, pipe, RR3_GET_IR_PARAM,
+ USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_DIR_IN,
+ RR3_IR_IO_SIG_TIMEOUT, 0, tmp, len, HZ * 5);
+ if (ret != len) {
+ dev_warn(dev, "Failed to read timeout from hardware\n");
+ return timeout;
+ }
+
+ timeout = US_TO_NS(redrat3_len_to_us(be32_to_cpu(*tmp)));
+ if (timeout < rc->min_timeout)
+ timeout = rc->min_timeout;
+ else if (timeout > rc->max_timeout)
+ timeout = rc->max_timeout;
+
+ rr3_dbg(dev, "Got timeout of %d ms\n", timeout / (1000 * 1000));
+ return timeout;
+}
+
+static void redrat3_reset(struct redrat3_dev *rr3)
+{
+ struct usb_device *udev = rr3->udev;
+ struct device *dev = rr3->dev;
+ int rc, rxpipe, txpipe;
+ u8 *val;
+ int len = sizeof(u8);
+
+ rr3_ftr(dev, "Entering %s\n", __func__);
+
+ rxpipe = usb_rcvctrlpipe(udev, 0);
+ txpipe = usb_sndctrlpipe(udev, 0);
+
+ val = kzalloc(len, GFP_KERNEL);
+ if (!val) {
+ dev_err(dev, "Memory allocation failure\n");
+ return;
+ }
+
+ *val = 0x01;
+ rc = usb_control_msg(udev, rxpipe, RR3_RESET,
+ USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_DIR_IN,
+ RR3_CPUCS_REG_ADDR, 0, val, len, HZ * 25);
+ rr3_dbg(dev, "reset returned 0x%02x\n", rc);
+
+ *val = 5;
+ rc = usb_control_msg(udev, txpipe, RR3_SET_IR_PARAM,
+ USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_DIR_OUT,
+ RR3_IR_IO_LENGTH_FUZZ, 0, val, len, HZ * 25);
+ rr3_dbg(dev, "set ir parm len fuzz %d rc 0x%02x\n", *val, rc);
+
+ *val = RR3_DRIVER_MAXLENS;
+ rc = usb_control_msg(udev, txpipe, RR3_SET_IR_PARAM,
+ USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_DIR_OUT,
+ RR3_IR_IO_MAX_LENGTHS, 0, val, len, HZ * 25);
+ rr3_dbg(dev, "set ir parm max lens %d rc 0x%02x\n", *val, rc);
+
+ kfree(val);
+}
+
+static void redrat3_get_firmware_rev(struct redrat3_dev *rr3)
+{
+ int rc = 0;
+ char *buffer;
+
+ rr3_ftr(rr3->dev, "Entering %s\n", __func__);
+
+ buffer = kzalloc(sizeof(char) * (RR3_FW_VERSION_LEN + 1), GFP_KERNEL);
+ if (!buffer) {
+ dev_err(rr3->dev, "Memory allocation failure\n");
+ return;
+ }
+
+ rc = usb_control_msg(rr3->udev, usb_rcvctrlpipe(rr3->udev, 0),
+ RR3_FW_VERSION,
+ USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_DIR_IN,
+ 0, 0, buffer, RR3_FW_VERSION_LEN, HZ * 5);
+
+ if (rc >= 0)
+ dev_info(rr3->dev, "Firmware rev: %s", buffer);
+ else
+ dev_err(rr3->dev, "Problem fetching firmware ID\n");
+
+ kfree(buffer);
+ rr3_ftr(rr3->dev, "Exiting %s\n", __func__);
+}
+
+static void redrat3_read_packet_start(struct redrat3_dev *rr3, int len)
+{
+ u16 tx_error;
+ u16 hdrlen;
+
+ rr3_ftr(rr3->dev, "Entering %s\n", __func__);
+
+ /* grab the Length and type of transfer */
+ memcpy(&(rr3->pktlen), (unsigned char *) rr3->bulk_in_buf,
+ sizeof(rr3->pktlen));
+ memcpy(&(rr3->pkttype), ((unsigned char *) rr3->bulk_in_buf +
+ sizeof(rr3->pktlen)),
+ sizeof(rr3->pkttype));
+
+ /*data needs conversion to know what its real values are*/
+ rr3->pktlen = be16_to_cpu(rr3->pktlen);
+ rr3->pkttype = be16_to_cpu(rr3->pkttype);
+
+ switch (rr3->pkttype) {
+ case RR3_ERROR:
+ memcpy(&tx_error, ((unsigned char *)rr3->bulk_in_buf
+ + (sizeof(rr3->pktlen) + sizeof(rr3->pkttype))),
+ sizeof(tx_error));
+ tx_error = be16_to_cpu(tx_error);
+ redrat3_dump_fw_error(rr3, tx_error);
+ break;
+
+ case RR3_MOD_SIGNAL_IN:
+ hdrlen = sizeof(rr3->pktlen) + sizeof(rr3->pkttype);
+ rr3->bytes_read = len;
+ rr3->bytes_read -= hdrlen;
+ rr3->datap = &(rr3->pbuf[0]);
+
+ memcpy(rr3->datap, ((unsigned char *)rr3->bulk_in_buf + hdrlen),
+ rr3->bytes_read);
+ rr3->datap += rr3->bytes_read;
+ rr3_dbg(rr3->dev, "bytes_read %d, pktlen %d\n",
+ rr3->bytes_read, rr3->pktlen);
+ break;
+
+ default:
+ rr3_dbg(rr3->dev, "ignoring packet with type 0x%02x, "
+ "len of %d, 0x%02x\n", rr3->pkttype, len, rr3->pktlen);
+ break;
+ }
+}
+
+static void redrat3_read_packet_continue(struct redrat3_dev *rr3, int len)
+{
+
+ rr3_ftr(rr3->dev, "Entering %s\n", __func__);
+
+ memcpy(rr3->datap, (unsigned char *)rr3->bulk_in_buf, len);
+ rr3->datap += len;
+
+ rr3->bytes_read += len;
+ rr3_dbg(rr3->dev, "bytes_read %d, pktlen %d\n",
+ rr3->bytes_read, rr3->pktlen);
+}
+
+/* gather IR data from incoming urb, process it when we have enough */
+static int redrat3_get_ir_data(struct redrat3_dev *rr3, int len)
+{
+ struct device *dev = rr3->dev;
+ int ret = 0;
+
+ rr3_ftr(dev, "Entering %s\n", __func__);
+
+ if (rr3->pktlen > RR3_MAX_BUF_SIZE) {
+ dev_err(rr3->dev, "error: packet larger than buffer\n");
+ ret = -EINVAL;
+ goto out;
+ }
+
+ if ((rr3->bytes_read == 0) &&
+ (len >= (sizeof(rr3->pkttype) + sizeof(rr3->pktlen)))) {
+ redrat3_read_packet_start(rr3, len);
+ } else if (rr3->bytes_read != 0) {
+ redrat3_read_packet_continue(rr3, len);
+ } else if (rr3->bytes_read == 0) {
+ dev_err(dev, "error: no packet data read\n");
+ ret = -ENODATA;
+ goto out;
+ }
+
+ if (rr3->bytes_read > rr3->pktlen) {
+ dev_err(dev, "bytes_read (%d) greater than pktlen (%d)\n",
+ rr3->bytes_read, rr3->pktlen);
+ ret = -EINVAL;
+ goto out;
+ } else if (rr3->bytes_read < rr3->pktlen)
+ /* we're still accumulating data */
+ return 0;
+
+ /* if we get here, we've got IR data to decode */
+ if (rr3->pkttype == RR3_MOD_SIGNAL_IN)
+ redrat3_process_ir_data(rr3);
+ else
+ rr3_dbg(dev, "discarding non-signal data packet "
+ "(type 0x%02x)\n", rr3->pkttype);
+
+out:
+ rr3->bytes_read = 0;
+ rr3->pktlen = 0;
+ rr3->pkttype = 0;
+ return ret;
+}
+
+/* callback function from USB when async USB request has completed */
+static void redrat3_handle_async(struct urb *urb, struct pt_regs *regs)
+{
+ struct redrat3_dev *rr3;
+
+ if (!urb)
+ return;
+
+ rr3 = urb->context;
+ if (!rr3) {
+ pr_err("%s called with invalid context!\n", __func__);
+ usb_unlink_urb(urb);
+ return;
+ }
+
+ rr3_ftr(rr3->dev, "Entering %s\n", __func__);
+
+ if (!rr3->det_enabled) {
+ rr3_dbg(rr3->dev, "received a read callback but detector "
+ "disabled - ignoring\n");
+ return;
+ }
+
+ switch (urb->status) {
+ case 0:
+ redrat3_get_ir_data(rr3, urb->actual_length);
+ break;
+
+ case -ECONNRESET:
+ case -ENOENT:
+ case -ESHUTDOWN:
+ usb_unlink_urb(urb);
+ return;
+
+ case -EPIPE:
+ default:
+ dev_warn(rr3->dev, "Error: urb status = %d\n", urb->status);
+ rr3->bytes_read = 0;
+ rr3->pktlen = 0;
+ rr3->pkttype = 0;
+ break;
+ }
+
+ if (!rr3->transmitting)
+ redrat3_issue_async(rr3);
+ else
+ rr3_dbg(rr3->dev, "IR transmit in progress\n");
+}
+
+static void redrat3_write_bulk_callback(struct urb *urb, struct pt_regs *regs)
+{
+ struct redrat3_dev *rr3;
+ int len;
+
+ if (!urb)
+ return;
+
+ rr3 = urb->context;
+ if (rr3) {
+ len = urb->actual_length;
+ rr3_ftr(rr3->dev, "%s: called (status=%d len=%d)\n",
+ __func__, urb->status, len);
+ }
+}
+
+static u16 mod_freq_to_val(unsigned int mod_freq)
+{
+ int mult = 6000000;
+
+ /* Clk used in mod. freq. generation is CLK24/4. */
+ return (u16)(65536 - (mult / mod_freq));
+}
+
+static int redrat3_set_tx_carrier(struct rc_dev *dev, u32 carrier)
+{
+ struct redrat3_dev *rr3 = dev->priv;
+
+ rr3->carrier = carrier;
+
+ return carrier;
+}
+
+static int redrat3_transmit_ir(struct rc_dev *rcdev, int *txbuf, u32 n)
+{
+ struct redrat3_dev *rr3 = rcdev->priv;
+ struct device *dev = rr3->dev;
+ struct redrat3_signal_header header;
+ int i, j, count, ret, ret_len, offset;
+ int lencheck, cur_sample_len, pipe;
+ char *buffer = NULL, *sigdata = NULL;
+ int *sample_lens = NULL;
+ u32 tmpi;
+ u16 tmps;
+ u8 *datap;
+ u8 curlencheck = 0;
+ u16 *lengths_ptr;
+ int sendbuf_len;
+
+ rr3_ftr(dev, "Entering %s\n", __func__);
+
+ if (rr3->transmitting) {
+ dev_warn(dev, "%s: transmitter already in use\n", __func__);
+ return -EAGAIN;
+ }
+
+ count = n / sizeof(int);
+ if (count > (RR3_DRIVER_MAXLENS * 2))
+ return -EINVAL;
+
+ rr3->transmitting = true;
+
+ redrat3_disable_detector(rr3);
+
+ if (rr3->det_enabled) {
+ dev_err(dev, "%s: cannot tx while rx is enabled\n", __func__);
+ ret = -EIO;
+ goto out;
+ }
+
+ sample_lens = kzalloc(sizeof(int) * RR3_DRIVER_MAXLENS, GFP_KERNEL);
+ if (!sample_lens) {
+ ret = -ENOMEM;
+ goto out;
+ }
+
+ for (i = 0; i < count; i++) {
+ for (lencheck = 0; lencheck < curlencheck; lencheck++) {
+ cur_sample_len = redrat3_us_to_len(txbuf[i]);
+ if (sample_lens[lencheck] == cur_sample_len)
+ break;
+ }
+ if (lencheck == curlencheck) {
+ cur_sample_len = redrat3_us_to_len(txbuf[i]);
+ rr3_dbg(dev, "txbuf[%d]=%u, pos %d, enc %u\n",
+ i, txbuf[i], curlencheck, cur_sample_len);
+ if (curlencheck < 255) {
+ /* now convert the value to a proper
+ * rr3 value.. */
+ sample_lens[curlencheck] = cur_sample_len;
+ curlencheck++;
+ } else {
+ dev_err(dev, "signal too long\n");
+ ret = -EINVAL;
+ goto out;
+ }
+ }
+ }
+
+ sigdata = kzalloc((count + RR3_TX_TRAILER_LEN), GFP_KERNEL);
+ if (!sigdata) {
+ ret = -ENOMEM;
+ goto out;
+ }
+
+ sigdata[count] = RR3_END_OF_SIGNAL;
+ sigdata[count + 1] = RR3_END_OF_SIGNAL;
+ for (i = 0; i < count; i++) {
+ for (j = 0; j < curlencheck; j++) {
+ if (sample_lens[j] == redrat3_us_to_len(txbuf[i]))
+ sigdata[i] = j;
+ }
+ }
+
+ offset = RR3_TX_HEADER_OFFSET;
+ sendbuf_len = RR3_HEADER_LENGTH + (sizeof(u16) * RR3_DRIVER_MAXLENS)
+ + count + RR3_TX_TRAILER_LEN + offset;
+
+ buffer = kzalloc(sendbuf_len, GFP_KERNEL);
+ if (!buffer) {
+ ret = -ENOMEM;
+ goto out;
+ }
+
+ /* fill in our packet header */
+ header.length = sendbuf_len - offset;
+ header.transfer_type = RR3_MOD_SIGNAL_OUT;
+ header.pause = redrat3_len_to_us(100);
+ header.mod_freq_count = mod_freq_to_val(rr3->carrier);
+ header.no_periods = 0; /* n/a to transmit */
+ header.max_lengths = RR3_DRIVER_MAXLENS;
+ header.no_lengths = curlencheck;
+ header.max_sig_size = RR3_MAX_SIG_SIZE;
+ header.sig_size = count + RR3_TX_TRAILER_LEN;
+ /* we currently rely on repeat handling in the IR encoding source */
+ header.no_repeats = 0;
+
+ tmps = cpu_to_be16(header.length);
+ memcpy(buffer, &tmps, 2);
+
+ tmps = cpu_to_be16(header.transfer_type);
+ memcpy(buffer + 2, &tmps, 2);
+
+ tmpi = cpu_to_be32(header.pause);
+ memcpy(buffer + offset, &tmpi, sizeof(tmpi));
+
+ tmps = cpu_to_be16(header.mod_freq_count);
+ memcpy(buffer + offset + RR3_FREQ_COUNT_OFFSET, &tmps, 2);
+
+ buffer[offset + RR3_NUM_LENGTHS_OFFSET] = header.no_lengths;
+
+ tmps = cpu_to_be16(header.sig_size);
+ memcpy(buffer + offset + RR3_NUM_SIGS_OFFSET, &tmps, 2);
+
+ buffer[offset + RR3_REPEATS_OFFSET] = header.no_repeats;
+
+ lengths_ptr = (u16 *)(buffer + offset + RR3_HEADER_LENGTH);
+ for (i = 0; i < curlencheck; ++i)
+ lengths_ptr[i] = cpu_to_be16(sample_lens[i]);
+
+ datap = (u8 *)(buffer + offset + RR3_HEADER_LENGTH +
+ (sizeof(u16) * RR3_DRIVER_MAXLENS));
+ memcpy(datap, sigdata, (count + RR3_TX_TRAILER_LEN));
+
+ if (debug) {
+ redrat3_dump_signal_header(&header);
+ redrat3_dump_signal_data(buffer, header.sig_size);
+ }
+
+ pipe = usb_sndbulkpipe(rr3->udev, rr3->ep_out->bEndpointAddress);
+ tmps = usb_bulk_msg(rr3->udev, pipe, buffer,
+ sendbuf_len, &ret_len, 10 * HZ);
+ rr3_dbg(dev, "sent %d bytes, (ret %d)\n", ret_len, tmps);
+
+ /* now tell the hardware to transmit what we sent it */
+ pipe = usb_rcvctrlpipe(rr3->udev, 0);
+ ret = usb_control_msg(rr3->udev, pipe, RR3_TX_SEND_SIGNAL,
+ USB_TYPE_VENDOR | USB_RECIP_DEVICE | USB_DIR_IN,
+ 0, 0, buffer, 2, HZ * 10);
+
+ if (ret < 0)
+ dev_err(dev, "Error: control msg send failed, rc %d\n", ret);
+ else
+ ret = n;
+
+out:
+ kfree(sample_lens);
+ kfree(buffer);
+ kfree(sigdata);
+
+ rr3->transmitting = false;
+
+ redrat3_enable_detector(rr3);
+
+ return ret;
+}
+
+static struct rc_dev *redrat3_init_rc_dev(struct redrat3_dev *rr3)
+{
+ struct device *dev = rr3->dev;
+ struct rc_dev *rc;
+ int ret = -ENODEV;
+ u16 prod = le16_to_cpu(rr3->udev->descriptor.idProduct);
+
+ rc = rc_allocate_device();
+ if (!rc) {
+ dev_err(dev, "remote input dev allocation failed\n");
+ goto out;
+ }
+
+ snprintf(rr3->name, sizeof(rr3->name), "RedRat3%s "
+ "Infrared Remote Transceiver (%04x:%04x)",
+ prod == USB_RR3IIUSB_PRODUCT_ID ? "-II" : "",
+ le16_to_cpu(rr3->udev->descriptor.idVendor), prod);
+
+ usb_make_path(rr3->udev, rr3->phys, sizeof(rr3->phys));
+
+ rc->input_name = rr3->name;
+ rc->input_phys = rr3->phys;
+ usb_to_input_id(rr3->udev, &rc->input_id);
+ rc->dev.parent = dev;
+ rc->priv = rr3;
+ rc->driver_type = RC_DRIVER_IR_RAW;
+ rc->allowed_protos = RC_TYPE_ALL;
+ rc->min_timeout = MS_TO_NS(RR3_RX_MIN_TIMEOUT);
+ rc->max_timeout = MS_TO_NS(RR3_RX_MAX_TIMEOUT);
+ rc->timeout = redrat3_get_timeout(dev, rc, rr3->udev);
+ rc->tx_ir = redrat3_transmit_ir;
+ rc->s_tx_carrier = redrat3_set_tx_carrier;
+ rc->driver_name = DRIVER_NAME;
+ rc->map_name = RC_MAP_HAUPPAUGE;
+
+ ret = rc_register_device(rc);
+ if (ret < 0) {
+ dev_err(dev, "remote dev registration failed\n");
+ goto out;
+ }
+
+ return rc;
+
+out:
+ rc_free_device(rc);
+ return NULL;
+}
+
+static int __devinit redrat3_dev_probe(struct usb_interface *intf,
+ const struct usb_device_id *id)
+{
+ struct usb_device *udev = interface_to_usbdev(intf);
+ struct device *dev = &intf->dev;
+ struct usb_host_interface *uhi;
+ struct redrat3_dev *rr3;
+ struct usb_endpoint_descriptor *ep;
+ struct usb_endpoint_descriptor *ep_in = NULL;
+ struct usb_endpoint_descriptor *ep_out = NULL;
+ u8 addr, attrs;
+ int pipe, i;
+ int retval = -ENOMEM;
+
+ rr3_ftr(dev, "%s called\n", __func__);
+
+ uhi = intf->cur_altsetting;
+
+ /* find our bulk-in and bulk-out endpoints */
+ for (i = 0; i < uhi->desc.bNumEndpoints; ++i) {
+ ep = &uhi->endpoint[i].desc;
+ addr = ep->bEndpointAddress;
+ attrs = ep->bmAttributes;
+
+ if ((ep_in == NULL) &&
+ ((addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN) &&
+ ((attrs & USB_ENDPOINT_XFERTYPE_MASK) ==
+ USB_ENDPOINT_XFER_BULK)) {
+ rr3_dbg(dev, "found bulk-in endpoint at 0x%02x\n",
+ ep->bEndpointAddress);
+ /* data comes in on 0x82, 0x81 is for other data... */
+ if (ep->bEndpointAddress == RR3_BULK_IN_EP_ADDR)
+ ep_in = ep;
+ }
+
+ if ((ep_out == NULL) &&
+ ((addr & USB_ENDPOINT_DIR_MASK) == USB_DIR_OUT) &&
+ ((attrs & USB_ENDPOINT_XFERTYPE_MASK) ==
+ USB_ENDPOINT_XFER_BULK)) {
+ rr3_dbg(dev, "found bulk-out endpoint at 0x%02x\n",
+ ep->bEndpointAddress);
+ ep_out = ep;
+ }
+ }
+
+ if (!ep_in || !ep_out) {
+ dev_err(dev, "Couldn't find both in and out endpoints\n");
+ retval = -ENODEV;
+ goto no_endpoints;
+ }
+
+ /* allocate memory for our device state and initialize it */
+ rr3 = kzalloc(sizeof(*rr3), GFP_KERNEL);
+ if (rr3 == NULL) {
+ dev_err(dev, "Memory allocation failure\n");
+ goto error;
+ }
+
+ rr3->dev = &intf->dev;
+
+ /* set up bulk-in endpoint */
+ rr3->read_urb = usb_alloc_urb(0, GFP_KERNEL);
+ if (!rr3->read_urb) {
+ dev_err(dev, "Read urb allocation failure\n");
+ goto error;
+ }
+
+ rr3->ep_in = ep_in;
+ rr3->bulk_in_buf = usb_alloc_coherent(udev, ep_in->wMaxPacketSize,
+ GFP_ATOMIC, &rr3->dma_in);
+ if (!rr3->bulk_in_buf) {
+ dev_err(dev, "Read buffer allocation failure\n");
+ goto error;
+ }
+
+ pipe = usb_rcvbulkpipe(udev, ep_in->bEndpointAddress);
+ usb_fill_bulk_urb(rr3->read_urb, udev, pipe,
+ rr3->bulk_in_buf, ep_in->wMaxPacketSize,
+ (usb_complete_t)redrat3_handle_async, rr3);
+
+ /* set up bulk-out endpoint*/
+ rr3->write_urb = usb_alloc_urb(0, GFP_KERNEL);
+ if (!rr3->write_urb) {
+ dev_err(dev, "Write urb allocation failure\n");
+ goto error;
+ }
+
+ rr3->ep_out = ep_out;
+ rr3->bulk_out_buf = usb_alloc_coherent(udev, ep_out->wMaxPacketSize,
+ GFP_ATOMIC, &rr3->dma_out);
+ if (!rr3->bulk_out_buf) {
+ dev_err(dev, "Write buffer allocation failure\n");
+ goto error;
+ }
+
+ pipe = usb_sndbulkpipe(udev, ep_out->bEndpointAddress);
+ usb_fill_bulk_urb(rr3->write_urb, udev, pipe,
+ rr3->bulk_out_buf, ep_out->wMaxPacketSize,
+ (usb_complete_t)redrat3_write_bulk_callback, rr3);
+
+ mutex_init(&rr3->lock);
+ rr3->udev = udev;
+
+ redrat3_reset(rr3);
+ redrat3_get_firmware_rev(rr3);
+
+ /* might be all we need to do? */
+ retval = redrat3_enable_detector(rr3);
+ if (retval < 0)
+ goto error;
+
+ /* default.. will get overridden by any sends with a freq defined */
+ rr3->carrier = 38000;
+
+ rr3->rc = redrat3_init_rc_dev(rr3);
+ if (!rr3->rc)
+ goto error;
+
+ setup_timer(&rr3->rx_timeout, redrat3_rx_timeout, (unsigned long)rr3);
+
+ /* we can register the device now, as it is ready */
+ usb_set_intfdata(intf, rr3);
+
+ rr3_ftr(dev, "Exiting %s\n", __func__);
+ return 0;
+
+error:
+ redrat3_delete(rr3, rr3->udev);
+
+no_endpoints:
+ dev_err(dev, "%s: retval = %x", __func__, retval);
+
+ return retval;
+}
+
+static void __devexit redrat3_dev_disconnect(struct usb_interface *intf)
+{
+ struct usb_device *udev = interface_to_usbdev(intf);
+ struct redrat3_dev *rr3 = usb_get_intfdata(intf);
+
+ rr3_ftr(&intf->dev, "Entering %s\n", __func__);
+
+ if (!rr3)
+ return;
+
+ redrat3_disable_detector(rr3);
+
+ usb_set_intfdata(intf, NULL);
+ rc_unregister_device(rr3->rc);
+ redrat3_delete(rr3, udev);
+
+ rr3_ftr(&intf->dev, "RedRat3 IR Transceiver now disconnected\n");
+}
+
+static int redrat3_dev_suspend(struct usb_interface *intf, pm_message_t message)
+{
+ struct redrat3_dev *rr3 = usb_get_intfdata(intf);
+ rr3_ftr(rr3->dev, "suspend\n");
+ usb_kill_urb(rr3->read_urb);
+ return 0;
+}
+
+static int redrat3_dev_resume(struct usb_interface *intf)
+{
+ struct redrat3_dev *rr3 = usb_get_intfdata(intf);
+ rr3_ftr(rr3->dev, "resume\n");
+ if (usb_submit_urb(rr3->read_urb, GFP_ATOMIC))
+ return -EIO;
+ return 0;
+}
+
+static struct usb_driver redrat3_dev_driver = {
+ .name = DRIVER_NAME,
+ .probe = redrat3_dev_probe,
+ .disconnect = redrat3_dev_disconnect,
+ .suspend = redrat3_dev_suspend,
+ .resume = redrat3_dev_resume,
+ .reset_resume = redrat3_dev_resume,
+ .id_table = redrat3_dev_table
+};
+
+static int __init redrat3_dev_init(void)
+{
+ int ret;
+
+ ret = usb_register(&redrat3_dev_driver);
+ if (ret < 0)
+ pr_err(DRIVER_NAME
+ ": usb register failed, result = %d\n", ret);
+
+ return ret;
+}
+
+static void __exit redrat3_dev_exit(void)
+{
+ usb_deregister(&redrat3_dev_driver);
+}
+
+module_init(redrat3_dev_init);
+module_exit(redrat3_dev_exit);
+
+MODULE_DESCRIPTION(DRIVER_DESC);
+MODULE_AUTHOR(DRIVER_AUTHOR);
+MODULE_AUTHOR(DRIVER_AUTHOR2);
+MODULE_LICENSE("GPL");
+MODULE_DEVICE_TABLE(usb, redrat3_dev_table);
+
+module_param(debug, int, S_IRUGO | S_IWUSR);
+MODULE_PARM_DESC(debug, "Enable module debug spew. 0 = no debugging (default) "
+ "0x1 = standard debug messages, 0x2 = function tracing debug. "
+ "Flag bits are addative (i.e., 0x3 for both debug types).");
diff --git a/drivers/media/rc/winbond-cir.c b/drivers/media/rc/winbond-cir.c
index 186de55..5d06b89 100644
--- a/drivers/media/rc/winbond-cir.c
+++ b/drivers/media/rc/winbond-cir.c
@@ -19,11 +19,12 @@
* o DSDT dumps
*
* Supported features:
+ * o IR Receive
+ * o IR Transmit
* o Wake-On-CIR functionality
*
* To do:
* o Learning
- * o IR Transmit
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -50,6 +51,8 @@
#include <linux/io.h>
#include <linux/bitrev.h>
#include <linux/slab.h>
+#include <linux/wait.h>
+#include <linux/sched.h>
#include <media/rc-core.h>
#define DRVNAME "winbond-cir"
@@ -118,14 +121,24 @@
#define WBCIR_IRQ_NONE 0x00
/* RX data bit for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */
#define WBCIR_IRQ_RX 0x01
+/* TX data low bit for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */
+#define WBCIR_IRQ_TX_LOW 0x02
/* Over/Under-flow bit for WBCIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */
#define WBCIR_IRQ_ERR 0x04
+/* TX data empty bit for WBCEIR_REG_SP3_IER and WBCIR_REG_SP3_EIR */
+#define WBCIR_IRQ_TX_EMPTY 0x20
/* Led enable/disable bit for WBCIR_REG_ECEIR_CTS */
#define WBCIR_LED_ENABLE 0x80
/* RX data available bit for WBCIR_REG_SP3_LSR */
#define WBCIR_RX_AVAIL 0x01
+/* RX data overrun error bit for WBCIR_REG_SP3_LSR */
+#define WBCIR_RX_OVERRUN 0x02
+/* TX End-Of-Transmission bit for WBCIR_REG_SP3_ASCR */
+#define WBCIR_TX_EOT 0x04
/* RX disable bit for WBCIR_REG_SP3_ASCR */
#define WBCIR_RX_DISABLE 0x20
+/* TX data underrun error bit for WBCIR_REG_SP3_ASCR */
+#define WBCIR_TX_UNDERRUN 0x40
/* Extended mode enable bit for WBCIR_REG_SP3_EXCR1 */
#define WBCIR_EXT_ENABLE 0x01
/* Select compare register in WBCIR_REG_WCEIR_INDEX (bits 5 & 6) */
@@ -154,6 +167,21 @@
IR_PROTOCOL_RC6 = 0x2,
};
+/* Possible states for IR reception */
+enum wbcir_rxstate {
+ WBCIR_RXSTATE_INACTIVE = 0,
+ WBCIR_RXSTATE_ACTIVE,
+ WBCIR_RXSTATE_ERROR
+};
+
+/* Possible states for IR transmission */
+enum wbcir_txstate {
+ WBCIR_TXSTATE_INACTIVE = 0,
+ WBCIR_TXSTATE_ACTIVE,
+ WBCIR_TXSTATE_DONE,
+ WBCIR_TXSTATE_ERROR
+};
+
/* Misc */
#define WBCIR_NAME "Winbond CIR"
#define WBCIR_ID_FAMILY 0xF1 /* Family ID for the WPCD376I */
@@ -166,22 +194,29 @@
/* Per-device data */
struct wbcir_data {
spinlock_t spinlock;
+ struct rc_dev *dev;
+ struct led_classdev led;
unsigned long wbase; /* Wake-Up Baseaddr */
unsigned long ebase; /* Enhanced Func. Baseaddr */
unsigned long sbase; /* Serial Port Baseaddr */
unsigned int irq; /* Serial Port IRQ */
+ u8 irqmask;
- struct rc_dev *dev;
-
+ /* RX state */
+ enum wbcir_rxstate rxstate;
struct led_trigger *rxtrigger;
- struct led_trigger *txtrigger;
- struct led_classdev led;
+ struct ir_raw_event rxev;
- /* RX irdata state */
- bool irdata_active;
- bool irdata_error;
- struct ir_raw_event ev;
+ /* TX state */
+ enum wbcir_txstate txstate;
+ struct led_trigger *txtrigger;
+ u32 txlen;
+ u32 txoff;
+ u32 *txbuf;
+ wait_queue_head_t txwaitq;
+ u8 txmask;
+ u32 txcarrier;
};
static enum wbcir_protocol protocol = IR_PROTOCOL_RC6;
@@ -193,6 +228,10 @@
module_param(invert, bool, 0444);
MODULE_PARM_DESC(invert, "Invert the signal from the IR receiver");
+static int txandrx; /* default = 0 */
+module_param(txandrx, bool, 0444);
+MODULE_PARM_DESC(invert, "Allow simultaneous TX and RX");
+
static unsigned int wake_sc = 0x800F040C;
module_param(wake_sc, uint, 0644);
MODULE_PARM_DESC(wake_sc, "Scancode of the power-on IR command");
@@ -228,6 +267,17 @@
outb(bank, data->sbase + WBCIR_REG_SP3_BSR);
}
+static inline void
+wbcir_set_irqmask(struct wbcir_data *data, u8 irqmask)
+{
+ if (data->irqmask == irqmask)
+ return;
+
+ wbcir_select_bank(data, WBCIR_BANK_0);
+ outb(irqmask, data->sbase + WBCIR_REG_SP3_IER);
+ data->irqmask = irqmask;
+}
+
static enum led_brightness
wbcir_led_brightness_get(struct led_classdev *led_cdev)
{
@@ -279,97 +329,297 @@
*
*****************************************************************************/
+static void
+wbcir_idle_rx(struct rc_dev *dev, bool idle)
+{
+ struct wbcir_data *data = dev->priv;
+
+ if (!idle && data->rxstate == WBCIR_RXSTATE_INACTIVE) {
+ data->rxstate = WBCIR_RXSTATE_ACTIVE;
+ led_trigger_event(data->rxtrigger, LED_FULL);
+ }
+
+ if (idle && data->rxstate != WBCIR_RXSTATE_INACTIVE)
+ /* Tell hardware to go idle by setting RXINACTIVE */
+ outb(WBCIR_RX_DISABLE, data->sbase + WBCIR_REG_SP3_ASCR);
+}
+
+static void
+wbcir_irq_rx(struct wbcir_data *data, struct pnp_dev *device)
+{
+ u8 irdata;
+ DEFINE_IR_RAW_EVENT(rawir);
+
+ /* Since RXHDLEV is set, at least 8 bytes are in the FIFO */
+ while (inb(data->sbase + WBCIR_REG_SP3_LSR) & WBCIR_RX_AVAIL) {
+ irdata = inb(data->sbase + WBCIR_REG_SP3_RXDATA);
+ if (data->rxstate == WBCIR_RXSTATE_ERROR)
+ continue;
+ rawir.pulse = irdata & 0x80 ? false : true;
+ rawir.duration = US_TO_NS((irdata & 0x7F) * 10);
+ ir_raw_event_store_with_filter(data->dev, &rawir);
+ }
+
+ /* Check if we should go idle */
+ if (data->dev->idle) {
+ led_trigger_event(data->rxtrigger, LED_OFF);
+ data->rxstate = WBCIR_RXSTATE_INACTIVE;
+ }
+
+ ir_raw_event_handle(data->dev);
+}
+
+static void
+wbcir_irq_tx(struct wbcir_data *data)
+{
+ unsigned int space;
+ unsigned int used;
+ u8 bytes[16];
+ u8 byte;
+
+ if (!data->txbuf)
+ return;
+
+ switch (data->txstate) {
+ case WBCIR_TXSTATE_INACTIVE:
+ /* TX FIFO empty */
+ space = 16;
+ led_trigger_event(data->txtrigger, LED_FULL);
+ break;
+ case WBCIR_TXSTATE_ACTIVE:
+ /* TX FIFO low (3 bytes or less) */
+ space = 13;
+ break;
+ case WBCIR_TXSTATE_ERROR:
+ space = 0;
+ break;
+ default:
+ return;
+ }
+
+ /*
+ * TX data is run-length coded in bytes: YXXXXXXX
+ * Y = space (1) or pulse (0)
+ * X = duration, encoded as (X + 1) * 10us (i.e 10 to 1280 us)
+ */
+ for (used = 0; used < space && data->txoff != data->txlen; used++) {
+ if (data->txbuf[data->txoff] == 0) {
+ data->txoff++;
+ continue;
+ }
+ byte = min((u32)0x80, data->txbuf[data->txoff]);
+ data->txbuf[data->txoff] -= byte;
+ byte--;
+ byte |= (data->txoff % 2 ? 0x80 : 0x00); /* pulse/space */
+ bytes[used] = byte;
+ }
+
+ while (data->txbuf[data->txoff] == 0 && data->txoff != data->txlen)
+ data->txoff++;
+
+ if (used == 0) {
+ /* Finished */
+ if (data->txstate == WBCIR_TXSTATE_ERROR)
+ /* Clear TX underrun bit */
+ outb(WBCIR_TX_UNDERRUN, data->sbase + WBCIR_REG_SP3_ASCR);
+ else
+ data->txstate = WBCIR_TXSTATE_DONE;
+ wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR);
+ led_trigger_event(data->txtrigger, LED_OFF);
+ wake_up(&data->txwaitq);
+ } else if (data->txoff == data->txlen) {
+ /* At the end of transmission, tell the hw before last byte */
+ outsb(data->sbase + WBCIR_REG_SP3_TXDATA, bytes, used - 1);
+ outb(WBCIR_TX_EOT, data->sbase + WBCIR_REG_SP3_ASCR);
+ outb(bytes[used - 1], data->sbase + WBCIR_REG_SP3_TXDATA);
+ wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR |
+ WBCIR_IRQ_TX_EMPTY);
+ } else {
+ /* More data to follow... */
+ outsb(data->sbase + WBCIR_REG_SP3_RXDATA, bytes, used);
+ if (data->txstate == WBCIR_TXSTATE_INACTIVE) {
+ wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR |
+ WBCIR_IRQ_TX_LOW);
+ data->txstate = WBCIR_TXSTATE_ACTIVE;
+ }
+ }
+}
+
static irqreturn_t
wbcir_irq_handler(int irqno, void *cookie)
{
struct pnp_dev *device = cookie;
struct wbcir_data *data = pnp_get_drvdata(device);
unsigned long flags;
- u8 irdata[8];
- u8 disable = true;
u8 status;
- int i;
spin_lock_irqsave(&data->spinlock, flags);
-
wbcir_select_bank(data, WBCIR_BANK_0);
-
status = inb(data->sbase + WBCIR_REG_SP3_EIR);
+ status &= data->irqmask;
- if (!(status & (WBCIR_IRQ_RX | WBCIR_IRQ_ERR))) {
+ if (!status) {
spin_unlock_irqrestore(&data->spinlock, flags);
return IRQ_NONE;
}
- /* Check for e.g. buffer overflow */
if (status & WBCIR_IRQ_ERR) {
- data->irdata_error = true;
- ir_raw_event_reset(data->dev);
- }
-
- if (!(status & WBCIR_IRQ_RX))
- goto out;
-
- if (!data->irdata_active) {
- data->irdata_active = true;
- led_trigger_event(data->rxtrigger, LED_FULL);
- }
-
- /* Since RXHDLEV is set, at least 8 bytes are in the FIFO */
- insb(data->sbase + WBCIR_REG_SP3_RXDATA, &irdata[0], 8);
-
- for (i = 0; i < 8; i++) {
- u8 pulse;
- u32 duration;
-
- if (irdata[i] != 0xFF && irdata[i] != 0x00)
- disable = false;
-
- if (data->irdata_error)
- continue;
-
- pulse = irdata[i] & 0x80 ? false : true;
- duration = (irdata[i] & 0x7F) * 10000; /* ns */
-
- if (data->ev.pulse != pulse) {
- if (data->ev.duration != 0) {
- ir_raw_event_store(data->dev, &data->ev);
- data->ev.duration = 0;
- }
-
- data->ev.pulse = pulse;
+ /* RX overflow? (read clears bit) */
+ if (inb(data->sbase + WBCIR_REG_SP3_LSR) & WBCIR_RX_OVERRUN) {
+ data->rxstate = WBCIR_RXSTATE_ERROR;
+ ir_raw_event_reset(data->dev);
}
- data->ev.duration += duration;
+ /* TX underflow? */
+ if (inb(data->sbase + WBCIR_REG_SP3_ASCR) & WBCIR_TX_UNDERRUN)
+ data->txstate = WBCIR_TXSTATE_ERROR;
}
- if (disable) {
- if (data->ev.duration != 0 && !data->irdata_error) {
- ir_raw_event_store(data->dev, &data->ev);
- data->ev.duration = 0;
- }
+ if (status & WBCIR_IRQ_RX)
+ wbcir_irq_rx(data, device);
- /* Set RXINACTIVE */
- outb(WBCIR_RX_DISABLE, data->sbase + WBCIR_REG_SP3_ASCR);
+ if (status & (WBCIR_IRQ_TX_LOW | WBCIR_IRQ_TX_EMPTY))
+ wbcir_irq_tx(data);
- /* Drain the FIFO */
- while (inb(data->sbase + WBCIR_REG_SP3_LSR) & WBCIR_RX_AVAIL)
- inb(data->sbase + WBCIR_REG_SP3_RXDATA);
-
- ir_raw_event_reset(data->dev);
- data->irdata_error = false;
- data->irdata_active = false;
- led_trigger_event(data->rxtrigger, LED_OFF);
- }
-
- ir_raw_event_handle(data->dev);
-
-out:
spin_unlock_irqrestore(&data->spinlock, flags);
return IRQ_HANDLED;
}
+/*****************************************************************************
+ *
+ * RC-CORE INTERFACE FUNCTIONS
+ *
+ *****************************************************************************/
+static int
+wbcir_txcarrier(struct rc_dev *dev, u32 carrier)
+{
+ struct wbcir_data *data = dev->priv;
+ unsigned long flags;
+ u8 val;
+ u32 freq;
+
+ freq = DIV_ROUND_CLOSEST(carrier, 1000);
+ if (freq < 30 || freq > 60)
+ return -EINVAL;
+
+ switch (freq) {
+ case 58:
+ case 59:
+ case 60:
+ val = freq - 58;
+ freq *= 1000;
+ break;
+ case 57:
+ val = freq - 27;
+ freq = 56900;
+ break;
+ default:
+ val = freq - 27;
+ freq *= 1000;
+ break;
+ }
+
+ spin_lock_irqsave(&data->spinlock, flags);
+ if (data->txstate != WBCIR_TXSTATE_INACTIVE) {
+ spin_unlock_irqrestore(&data->spinlock, flags);
+ return -EBUSY;
+ }
+
+ if (data->txcarrier != freq) {
+ wbcir_select_bank(data, WBCIR_BANK_7);
+ wbcir_set_bits(data->sbase + WBCIR_REG_SP3_IRTXMC, val, 0x1F);
+ data->txcarrier = freq;
+ }
+
+ spin_unlock_irqrestore(&data->spinlock, flags);
+ return 0;
+}
+
+static int
+wbcir_txmask(struct rc_dev *dev, u32 mask)
+{
+ struct wbcir_data *data = dev->priv;
+ unsigned long flags;
+ u8 val;
+
+ /* Four outputs, only one output can be enabled at a time */
+ switch (mask) {
+ case 0x1:
+ val = 0x0;
+ break;
+ case 0x2:
+ val = 0x1;
+ break;
+ case 0x4:
+ val = 0x2;
+ break;
+ case 0x8:
+ val = 0x3;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ spin_lock_irqsave(&data->spinlock, flags);
+ if (data->txstate != WBCIR_TXSTATE_INACTIVE) {
+ spin_unlock_irqrestore(&data->spinlock, flags);
+ return -EBUSY;
+ }
+
+ if (data->txmask != mask) {
+ wbcir_set_bits(data->ebase + WBCIR_REG_ECEIR_CTS, val, 0x0c);
+ data->txmask = mask;
+ }
+
+ spin_unlock_irqrestore(&data->spinlock, flags);
+ return 0;
+}
+
+static int
+wbcir_tx(struct rc_dev *dev, int *buf, u32 bufsize)
+{
+ struct wbcir_data *data = dev->priv;
+ u32 count;
+ unsigned i;
+ unsigned long flags;
+
+ /* bufsize has been sanity checked by the caller */
+ count = bufsize / sizeof(int);
+
+ /* Not sure if this is possible, but better safe than sorry */
+ spin_lock_irqsave(&data->spinlock, flags);
+ if (data->txstate != WBCIR_TXSTATE_INACTIVE) {
+ spin_unlock_irqrestore(&data->spinlock, flags);
+ return -EBUSY;
+ }
+
+ /* Convert values to multiples of 10us */
+ for (i = 0; i < count; i++)
+ buf[i] = DIV_ROUND_CLOSEST(buf[i], 10);
+
+ /* Fill the TX fifo once, the irq handler will do the rest */
+ data->txbuf = buf;
+ data->txlen = count;
+ data->txoff = 0;
+ wbcir_irq_tx(data);
+
+ /* Wait for the TX to complete */
+ while (data->txstate == WBCIR_TXSTATE_ACTIVE) {
+ spin_unlock_irqrestore(&data->spinlock, flags);
+ wait_event(data->txwaitq, data->txstate != WBCIR_TXSTATE_ACTIVE);
+ spin_lock_irqsave(&data->spinlock, flags);
+ }
+
+ /* We're done */
+ if (data->txstate == WBCIR_TXSTATE_ERROR)
+ count = -EAGAIN;
+ data->txstate = WBCIR_TXSTATE_INACTIVE;
+ data->txbuf = NULL;
+ spin_unlock_irqrestore(&data->spinlock, flags);
+
+ return count;
+}
/*****************************************************************************
*
@@ -382,7 +632,7 @@
{
struct device *dev = &device->dev;
struct wbcir_data *data = pnp_get_drvdata(device);
- int do_wake = 1;
+ bool do_wake = true;
u8 match[11];
u8 mask[11];
u8 rc6_csl = 0;
@@ -392,14 +642,14 @@
memset(mask, 0, sizeof(mask));
if (wake_sc == INVALID_SCANCODE || !device_may_wakeup(dev)) {
- do_wake = 0;
+ do_wake = false;
goto finish;
}
switch (protocol) {
case IR_PROTOCOL_RC5:
if (wake_sc > 0xFFF) {
- do_wake = 0;
+ do_wake = false;
dev_err(dev, "RC5 - Invalid wake scancode\n");
break;
}
@@ -418,7 +668,7 @@
case IR_PROTOCOL_NEC:
if (wake_sc > 0xFFFFFF) {
- do_wake = 0;
+ do_wake = false;
dev_err(dev, "NEC - Invalid wake scancode\n");
break;
}
@@ -440,7 +690,7 @@
if (wake_rc6mode == 0) {
if (wake_sc > 0xFFFF) {
- do_wake = 0;
+ do_wake = false;
dev_err(dev, "RC6 - Invalid wake scancode\n");
break;
}
@@ -496,7 +746,7 @@
} else if (wake_sc <= 0x007FFFFF) {
rc6_csl = 60;
} else {
- do_wake = 0;
+ do_wake = false;
dev_err(dev, "RC6 - Invalid wake scancode\n");
break;
}
@@ -508,14 +758,14 @@
mask[i++] = 0x0F;
} else {
- do_wake = 0;
+ do_wake = false;
dev_err(dev, "RC6 - Invalid wake mode\n");
}
break;
default:
- do_wake = 0;
+ do_wake = false;
break;
}
@@ -551,21 +801,18 @@
wbcir_set_bits(data->wbase + WBCIR_REG_WCEIR_CTL, 0x00, 0x01);
}
- /* Disable interrupts */
- wbcir_select_bank(data, WBCIR_BANK_0);
- outb(WBCIR_IRQ_NONE, data->sbase + WBCIR_REG_SP3_IER);
-
- /* Disable LED */
- data->irdata_active = false;
- led_trigger_event(data->rxtrigger, LED_OFF);
-
/*
* ACPI will set the HW disable bit for SP3 which means that the
* output signals are left in an undefined state which may cause
* spurious interrupts which we need to ignore until the hardware
* is reinitialized.
*/
+ wbcir_set_irqmask(data, WBCIR_IRQ_NONE);
disable_irq(data->irq);
+
+ /* Disable LED */
+ led_trigger_event(data->rxtrigger, LED_OFF);
+ led_trigger_event(data->txtrigger, LED_OFF);
}
static int
@@ -581,8 +828,7 @@
u8 tmp;
/* Disable interrupts */
- wbcir_select_bank(data, WBCIR_BANK_0);
- outb(WBCIR_IRQ_NONE, data->sbase + WBCIR_REG_SP3_IER);
+ wbcir_set_irqmask(data, WBCIR_IRQ_NONE);
/* Set PROT_SEL, RX_INV, Clear CEIR_EN (needed for the led) */
tmp = protocol << 4;
@@ -606,10 +852,11 @@
outb(0x00, data->ebase + WBCIR_REG_ECEIR_CCTL);
/*
- * Clear IR LED, set SP3 clock to 24Mhz
+ * Clear IR LED, set SP3 clock to 24Mhz, set TX mask to IRTX1,
* set SP3_IRRX_SW to binary 01, helpfully not documented
*/
outb(0x10, data->ebase + WBCIR_REG_ECEIR_CTS);
+ data->txmask = 0x1;
/* Enable extended mode */
wbcir_select_bank(data, WBCIR_BANK_2);
@@ -657,18 +904,21 @@
wbcir_select_bank(data, WBCIR_BANK_4);
outb(0x00, data->sbase + WBCIR_REG_SP3_IRCR1);
- /* Enable MSR interrupt, Clear AUX_IRX */
+ /* Disable MSR interrupt, clear AUX_IRX, mask RX during TX? */
wbcir_select_bank(data, WBCIR_BANK_5);
- outb(0x00, data->sbase + WBCIR_REG_SP3_IRCR2);
+ outb(txandrx ? 0x03 : 0x02, data->sbase + WBCIR_REG_SP3_IRCR2);
/* Disable CRC */
wbcir_select_bank(data, WBCIR_BANK_6);
outb(0x20, data->sbase + WBCIR_REG_SP3_IRCR3);
- /* Set RX/TX (de)modulation freq, not really used */
+ /* Set RX demodulation freq, not really used */
wbcir_select_bank(data, WBCIR_BANK_7);
outb(0xF2, data->sbase + WBCIR_REG_SP3_IRRXDC);
+
+ /* Set TX modulation, 36kHz, 7us pulse width */
outb(0x69, data->sbase + WBCIR_REG_SP3_IRTXMC);
+ data->txcarrier = 36000;
/* Set invert and pin direction */
if (invert)
@@ -683,16 +933,23 @@
/* Clear AUX status bits */
outb(0xE0, data->sbase + WBCIR_REG_SP3_ASCR);
- /* Clear IR decoding state */
- data->irdata_active = false;
- led_trigger_event(data->rxtrigger, LED_OFF);
- data->irdata_error = false;
- data->ev.duration = 0;
+ /* Clear RX state */
+ data->rxstate = WBCIR_RXSTATE_INACTIVE;
+ data->rxev.duration = 0;
ir_raw_event_reset(data->dev);
ir_raw_event_handle(data->dev);
+ /*
+ * Check TX state, if we did a suspend/resume cycle while TX was
+ * active, we will have a process waiting in txwaitq.
+ */
+ if (data->txstate == WBCIR_TXSTATE_ACTIVE) {
+ data->txstate = WBCIR_TXSTATE_ERROR;
+ wake_up(&data->txwaitq);
+ }
+
/* Enable interrupts */
- outb(WBCIR_IRQ_RX | WBCIR_IRQ_ERR, data->sbase + WBCIR_REG_SP3_IER);
+ wbcir_set_irqmask(data, WBCIR_IRQ_RX | WBCIR_IRQ_ERR);
}
static int
@@ -729,6 +986,7 @@
pnp_set_drvdata(device, data);
spin_lock_init(&data->spinlock);
+ init_waitqueue_head(&data->txwaitq);
data->ebase = pnp_port_start(device, 0);
data->wbase = pnp_port_start(device, 1);
data->sbase = pnp_port_start(device, 2);
@@ -807,6 +1065,11 @@
data->dev->input_id.vendor = PCI_VENDOR_ID_WINBOND;
data->dev->input_id.product = WBCIR_ID_FAMILY;
data->dev->input_id.version = WBCIR_ID_CHIP;
+ data->dev->map_name = RC_MAP_RC6_MCE;
+ data->dev->s_idle = wbcir_idle_rx;
+ data->dev->s_tx_mask = wbcir_txmask;
+ data->dev->s_tx_carrier = wbcir_txcarrier;
+ data->dev->tx_ir = wbcir_tx;
data->dev->priv = data;
data->dev->dev.parent = &device->dev;
@@ -849,9 +1112,7 @@
struct wbcir_data *data = pnp_get_drvdata(device);
/* Disable interrupts */
- wbcir_select_bank(data, WBCIR_BANK_0);
- outb(WBCIR_IRQ_NONE, data->sbase + WBCIR_REG_SP3_IER);
-
+ wbcir_set_irqmask(data, WBCIR_IRQ_NONE);
free_irq(data->irq, device);
/* Clear status bits NEC_REP, BUFF, MSG_END, MATCH */
diff --git a/drivers/media/video/Kconfig b/drivers/media/video/Kconfig
index 00f51dd..3be180b 100644
--- a/drivers/media/video/Kconfig
+++ b/drivers/media/video/Kconfig
@@ -128,10 +128,10 @@
# Encoder / Decoder module configuration
#
-menu "Encoders/decoders and other helper chips"
+menu "Encoders, decoders, sensors and other helper chips"
visible if !VIDEO_HELPER_CHIPS_AUTO
-comment "Audio decoders"
+comment "Audio decoders, processors and mixers"
config VIDEO_TVAUDIO
tristate "Simple audio decoder chips"
@@ -210,15 +210,6 @@
To compile this driver as a module, choose M here: the
module will be called cs53l32a.
-config VIDEO_M52790
- tristate "Mitsubishi M52790 A/V switch"
- depends on VIDEO_V4L2 && I2C
- ---help---
- Support for the Mitsubishi M52790 A/V switch.
-
- To compile this driver as a module, choose M here: the
- module will be called m52790.
-
config VIDEO_TLV320AIC23B
tristate "Texas Instruments TLV320AIC23B audio codec"
depends on VIDEO_V4L2 && I2C && EXPERIMENTAL
@@ -321,29 +312,6 @@
To compile this driver as a module, choose M here: the
module will be called ks0127.
-config VIDEO_OV7670
- tristate "OmniVision OV7670 sensor support"
- depends on I2C && VIDEO_V4L2
- ---help---
- This is a Video4Linux2 sensor-level driver for the OmniVision
- OV7670 VGA camera. It currently only works with the M88ALP01
- controller.
-
-config VIDEO_MT9V011
- tristate "Micron mt9v011 sensor support"
- depends on I2C && VIDEO_V4L2
- ---help---
- This is a Video4Linux2 sensor-level driver for the Micron
- mt0v011 1.3 Mpixel camera. It currently only works with the
- em28xx driver.
-
-config VIDEO_TCM825X
- tristate "TCM825x camera sensor support"
- depends on I2C && VIDEO_V4L2
- ---help---
- This is a driver for the Toshiba TCM825x VGA camera sensor.
- It is used for example in Nokia N800.
-
config VIDEO_SAA7110
tristate "Philips SAA7110 video decoder"
depends on VIDEO_V4L2 && I2C
@@ -362,15 +330,6 @@
To compile this driver as a module, choose M here: the
module will be called saa7115.
-config VIDEO_SAA717X
- tristate "Philips SAA7171/3/4 audio/video decoders"
- depends on VIDEO_V4L2 && I2C
- ---help---
- Support for the Philips SAA7171/3/4 audio/video decoders.
-
- To compile this driver as a module, choose M here: the
- module will be called saa717x.
-
config VIDEO_SAA7191
tristate "Philips SAA7191 video decoder"
depends on VIDEO_V4L2 && I2C
@@ -420,6 +379,15 @@
comment "Video and audio decoders"
+config VIDEO_SAA717X
+ tristate "Philips SAA7171/3/4 audio/video decoders"
+ depends on VIDEO_V4L2 && I2C
+ ---help---
+ Support for the Philips SAA7171/3/4 audio/video decoders.
+
+ To compile this driver as a module, choose M here: the
+ module will be called saa717x.
+
source "drivers/media/video/cx25840/Kconfig"
comment "MPEG video encoders"
@@ -474,15 +442,6 @@
To compile this driver as a module, choose M here: the
module will be called adv7175.
-config VIDEO_THS7303
- tristate "THS7303 Video Amplifier"
- depends on I2C
- help
- Support for TI THS7303 video amplifier
-
- To compile this driver as a module, choose M here: the
- module will be called ths7303.
-
config VIDEO_ADV7343
tristate "ADV7343 video encoder"
depends on I2C
@@ -498,6 +457,38 @@
help
Video output driver for AKM AK8813 and AK8814 TV encoders
+comment "Camera sensor devices"
+
+config VIDEO_OV7670
+ tristate "OmniVision OV7670 sensor support"
+ depends on I2C && VIDEO_V4L2
+ ---help---
+ This is a Video4Linux2 sensor-level driver for the OmniVision
+ OV7670 VGA camera. It currently only works with the M88ALP01
+ controller.
+
+config VIDEO_MT9V011
+ tristate "Micron mt9v011 sensor support"
+ depends on I2C && VIDEO_V4L2
+ ---help---
+ This is a Video4Linux2 sensor-level driver for the Micron
+ mt0v011 1.3 Mpixel camera. It currently only works with the
+ em28xx driver.
+
+config VIDEO_MT9V032
+ tristate "Micron MT9V032 sensor support"
+ depends on I2C && VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API
+ ---help---
+ This is a Video4Linux2 sensor-level driver for the Micron
+ MT9V032 752x480 CMOS sensor.
+
+config VIDEO_TCM825X
+ tristate "TCM825x camera sensor support"
+ depends on I2C && VIDEO_V4L2
+ ---help---
+ This is a driver for the Toshiba TCM825x VGA camera sensor.
+ It is used for example in Nokia N800.
+
comment "Video improvement chips"
config VIDEO_UPD64031A
@@ -523,6 +514,26 @@
To compile this driver as a module, choose M here: the
module will be called upd64083.
+comment "Miscelaneous helper chips"
+
+config VIDEO_THS7303
+ tristate "THS7303 Video Amplifier"
+ depends on I2C
+ help
+ Support for TI THS7303 video amplifier
+
+ To compile this driver as a module, choose M here: the
+ module will be called ths7303.
+
+config VIDEO_M52790
+ tristate "Mitsubishi M52790 A/V switch"
+ depends on VIDEO_V4L2 && I2C
+ ---help---
+ Support for the Mitsubishi M52790 A/V switch.
+
+ To compile this driver as a module, choose M here: the
+ module will be called m52790.
+
endmenu # encoder / decoder chips
config VIDEO_SH_VOU
@@ -682,7 +693,7 @@
select VIDEO_ADV7180
select VIDEOBUF_DMA_CONTIG
---help---
- Add support for the Video In peripherial of the timberdale FPGA.
+ Add support for the Video In peripherial of the timberdale FPGA.
source "drivers/media/video/cx88/Kconfig"
@@ -916,7 +927,7 @@
This is a v4l2 driver for the TI OMAP2 camera capture interface
config VIDEO_MX2_HOSTSUPPORT
- bool
+ bool
config VIDEO_MX2
tristate "i.MX27/i.MX25 Camera Sensor Interface driver"
@@ -927,6 +938,26 @@
This is a v4l2 driver for the i.MX27 and the i.MX25 Camera Sensor
Interface
+config VIDEO_SAMSUNG_S5P_FIMC
+ tristate "Samsung S5P and EXYNOS4 camera host interface driver"
+ depends on VIDEO_DEV && VIDEO_V4L2 && PLAT_S5P
+ select VIDEOBUF2_DMA_CONTIG
+ select V4L2_MEM2MEM_DEV
+ ---help---
+ This is a v4l2 driver for Samsung S5P and EXYNOS4 camera
+ host interface and video postprocessor.
+
+ To compile this driver as a module, choose M here: the
+ module will be called s5p-fimc.
+
+config VIDEO_S5P_MIPI_CSIS
+ tristate "Samsung S5P and EXYNOS4 MIPI CSI receiver driver"
+ depends on VIDEO_V4L2 && PM_RUNTIME && VIDEO_V4L2_SUBDEV_API
+ ---help---
+ This is a v4l2 driver for Samsung S5P/EXYNOS4 MIPI-CSI receiver.
+
+ To compile this driver as a module, choose M here: the
+ module will be called s5p-csis.
#
# USB Multimedia device configuration
@@ -983,7 +1014,7 @@
Supported devices are typically found in some Asus laptops,
with USB id 174f:a311 and 05e1:0501. Other Syntek cameras
may be supported by the stk11xx driver, from which this is
- derived, see <http://sourceforge.net/projects/syntekdriver/>
+ derived, see <http://sourceforge.net/projects/syntekdriver/>
To compile this driver as a module, choose M here: the
module will be called stkwebcam.
@@ -1022,13 +1053,5 @@
This is a virtual test device for the memory-to-memory driver
framework.
-config VIDEO_SAMSUNG_S5P_FIMC
- tristate "Samsung S5P FIMC (video postprocessor) driver"
- depends on VIDEO_DEV && VIDEO_V4L2 && PLAT_S5P
- select VIDEOBUF2_DMA_CONTIG
- select V4L2_MEM2MEM_DEV
- help
- This is a v4l2 driver for the S5P camera interface
- (video postprocessor)
endif # V4L_MEM2MEM_DRIVERS
diff --git a/drivers/media/video/Makefile b/drivers/media/video/Makefile
index ace5d8b..9519160 100644
--- a/drivers/media/video/Makefile
+++ b/drivers/media/video/Makefile
@@ -66,6 +66,7 @@
obj-$(CONFIG_VIDEO_TCM825X) += tcm825x.o
obj-$(CONFIG_VIDEO_TVEEPROM) += tveeprom.o
obj-$(CONFIG_VIDEO_MT9V011) += mt9v011.o
+obj-$(CONFIG_VIDEO_MT9V032) += mt9v032.o
obj-$(CONFIG_VIDEO_SR030PC30) += sr030pc30.o
obj-$(CONFIG_VIDEO_NOON010PC30) += noon010pc30.o
@@ -164,6 +165,7 @@
obj-$(CONFIG_VIDEO_SH_MOBILE_CSI2) += sh_mobile_csi2.o
obj-$(CONFIG_VIDEO_SH_MOBILE_CEU) += sh_mobile_ceu_camera.o
obj-$(CONFIG_VIDEO_OMAP1) += omap1_camera.o
+
obj-$(CONFIG_VIDEO_SAMSUNG_S5P_FIMC) += s5p-fimc/
obj-$(CONFIG_ARCH_DAVINCI) += davinci/
diff --git a/drivers/media/video/bt8xx/bttv-driver.c b/drivers/media/video/bt8xx/bttv-driver.c
index 91399c9..a97cf27 100644
--- a/drivers/media/video/bt8xx/bttv-driver.c
+++ b/drivers/media/video/bt8xx/bttv-driver.c
@@ -4303,7 +4303,7 @@
goto fail0;
}
- pci_read_config_byte(dev, PCI_CLASS_REVISION, &btv->revision);
+ btv->revision = dev->revision;
pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
printk(KERN_INFO "bttv%d: Bt%d (rev %d) at %s, ",
bttv_num,btv->id, btv->revision, pci_name(dev));
diff --git a/drivers/media/video/cpia2/cpia2_v4l.c b/drivers/media/video/cpia2/cpia2_v4l.c
index 5111bbc..0073a8c 100644
--- a/drivers/media/video/cpia2/cpia2_v4l.c
+++ b/drivers/media/video/cpia2/cpia2_v4l.c
@@ -1313,7 +1313,7 @@
static int cpia2_s_priority(struct file *file, void *_fh, enum v4l2_priority prio)
{
struct camera_data *cam = video_drvdata(file);
- struct cpia2_fh *fh = fh;
+ struct cpia2_fh *fh = _fh;
if (cam->streaming && prio != fh->prio &&
fh->prio == V4L2_PRIORITY_RECORD)
diff --git a/drivers/media/video/cx18/Kconfig b/drivers/media/video/cx18/Kconfig
index d9d2f6a..53b3c77 100644
--- a/drivers/media/video/cx18/Kconfig
+++ b/drivers/media/video/cx18/Kconfig
@@ -2,6 +2,7 @@
tristate "Conexant cx23418 MPEG encoder support"
depends on VIDEO_V4L2 && DVB_CORE && PCI && I2C && EXPERIMENTAL
select I2C_ALGOBIT
+ select VIDEOBUF_VMALLOC
depends on RC_CORE
select VIDEO_TUNER
select VIDEO_TVEEPROM
@@ -9,6 +10,9 @@
select VIDEO_CS5345
select DVB_S5H1409 if !DVB_FE_CUSTOMISE
select MEDIA_TUNER_MXL5005S if !MEDIA_TUNER_CUSTOMISE
+ select DVB_S5H1411 if !DVB_FE_CUSTOMISE
+ select MEDIA_TUNER_TDA18271 if !MEDIA_TUNER_CUSTOMISE
+ select MEDIA_TUNER_TDA8290 if !MEDIA_TUNER_CUSTOMISE
---help---
This is a video4linux driver for Conexant cx23418 based
PCI combo video recorder devices.
diff --git a/drivers/media/video/cx18/cx18-cards.c b/drivers/media/video/cx18/cx18-cards.c
index 68ad196..c07c849 100644
--- a/drivers/media/video/cx18/cx18-cards.c
+++ b/drivers/media/video/cx18/cx18-cards.c
@@ -39,6 +39,16 @@
.tv = { 0x61, 0x60, I2C_CLIENT_END },
};
+/*
+ * usual i2c tuner addresses to probe with additional demod address for
+ * an NXP TDA8295 at 0x42 (N.B. it can possibly be at 0x4b or 0x4c too).
+ */
+static struct cx18_card_tuner_i2c cx18_i2c_nxp = {
+ .radio = { I2C_CLIENT_END },
+ .demod = { 0x42, 0x43, I2C_CLIENT_END },
+ .tv = { 0x61, 0x60, I2C_CLIENT_END },
+};
+
/* Please add new PCI IDs to: http://pci-ids.ucw.cz/
This keeps the PCI ID database up to date. Note that the entries
must be added under vendor 0x4444 (Conexant) as subsystem IDs.
@@ -131,15 +141,15 @@
.tune_lane = 0,
.initial_emrs = 0,
},
- .gpio_init.initial_value = 0x3001,
- .gpio_init.direction = 0x3001,
+ .gpio_init.initial_value = 0x3801,
+ .gpio_init.direction = 0x3801,
.gpio_i2c_slave_reset = {
- .active_lo_mask = 0x3001,
+ .active_lo_mask = 0x3801,
.msecs_asserted = 10,
.msecs_recovery = 40,
.ir_reset_mask = 0x0001,
},
- .i2c = &cx18_i2c_std,
+ .i2c = &cx18_i2c_nxp,
};
static const struct cx18_card cx18_card_hvr1600_samsung = {
diff --git a/drivers/media/video/cx18/cx18-cards.h b/drivers/media/video/cx18/cx18-cards.h
index 3e75006..add7391 100644
--- a/drivers/media/video/cx18/cx18-cards.h
+++ b/drivers/media/video/cx18/cx18-cards.h
@@ -109,7 +109,7 @@
struct cx18_card_tuner_i2c {
unsigned short radio[2];/* radio tuner i2c address to probe */
- unsigned short demod[2];/* demodulator i2c address to probe */
+ unsigned short demod[3];/* demodulator i2c address to probe */
unsigned short tv[4]; /* tv tuner i2c addresses to probe */
};
diff --git a/drivers/media/video/cx18/cx18-driver.c b/drivers/media/video/cx18/cx18-driver.c
index 321c1b7..9e2f870 100644
--- a/drivers/media/video/cx18/cx18-driver.c
+++ b/drivers/media/video/cx18/cx18-driver.c
@@ -423,7 +423,16 @@
return;
/* autodetect tuner standard */
- if (tv.tuner_formats & V4L2_STD_PAL) {
+#define TVEEPROM_TUNER_FORMAT_ALL (V4L2_STD_B | V4L2_STD_GH | \
+ V4L2_STD_MN | \
+ V4L2_STD_PAL_I | \
+ V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC | \
+ V4L2_STD_DK)
+ if ((tv.tuner_formats & TVEEPROM_TUNER_FORMAT_ALL)
+ == TVEEPROM_TUNER_FORMAT_ALL) {
+ CX18_DEBUG_INFO("Worldwide tuner detected\n");
+ cx->std = V4L2_STD_ALL;
+ } else if (tv.tuner_formats & V4L2_STD_PAL) {
CX18_DEBUG_INFO("PAL tuner detected\n");
cx->std |= V4L2_STD_PAL_BG | V4L2_STD_PAL_H;
} else if (tv.tuner_formats & V4L2_STD_NTSC) {
@@ -818,7 +827,7 @@
cmd |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
pci_write_config_word(pci_dev, PCI_COMMAND, cmd);
- pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &cx->card_rev);
+ cx->card_rev = pci_dev->revision;
pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &pci_latency);
if (pci_latency < 64 && cx18_pci_latency) {
@@ -1001,7 +1010,15 @@
if (cx->card->hw_all & CX18_HW_TVEEPROM) {
/* Based on the model number the cardtype may be changed.
The PCI IDs are not always reliable. */
+ const struct cx18_card *orig_card = cx->card;
cx18_process_eeprom(cx);
+
+ if (cx->card != orig_card) {
+ /* Changed the cardtype; re-reset the I2C chips */
+ cx18_gpio_init(cx);
+ cx18_call_hw(cx, CX18_HW_GPIO_RESET_CTRL,
+ core, reset, (u32) CX18_GPIO_RESET_I2C);
+ }
}
if (cx->card->comment)
CX18_INFO("%s", cx->card->comment);
@@ -1087,6 +1104,8 @@
/* The tuner is fixed to the standard. The other inputs (e.g. S-Video)
are not. */
cx->tuner_std = cx->std;
+ if (cx->std == V4L2_STD_ALL)
+ cx->std = V4L2_STD_NTSC_M;
retval = cx18_streams_setup(cx);
if (retval) {
@@ -1133,6 +1152,7 @@
int fw_retry_count = 3;
struct v4l2_frequency vf;
struct cx18_open_id fh;
+ v4l2_std_id std;
fh.cx = cx;
@@ -1220,7 +1240,8 @@
/* Let the VIDIOC_S_STD ioctl do all the work, keeps the code
in one place. */
cx->std++; /* Force full standard initialization */
- cx18_s_std(NULL, &fh, &cx->tuner_std);
+ std = (cx->tuner_std == V4L2_STD_ALL) ? V4L2_STD_NTSC_M : cx->tuner_std;
+ cx18_s_std(NULL, &fh, &std);
cx18_s_frequency(NULL, &fh, &vf);
return 0;
}
diff --git a/drivers/media/video/cx18/cx18-driver.h b/drivers/media/video/cx18/cx18-driver.h
index b86a740..0864272 100644
--- a/drivers/media/video/cx18/cx18-driver.h
+++ b/drivers/media/video/cx18/cx18-driver.h
@@ -65,6 +65,10 @@
#include "dvb_net.h"
#include "dvbdev.h"
+/* Videobuf / YUV support */
+#include <media/videobuf-core.h>
+#include <media/videobuf-vmalloc.h>
+
#ifndef CONFIG_PCI
# error "This driver requires kernel PCI support."
#endif
@@ -403,6 +407,23 @@
struct cx18_queue q_idle; /* idle - not in rotation */
struct work_struct out_work_order;
+
+ /* Videobuf for YUV video */
+ u32 pixelformat;
+ struct list_head vb_capture; /* video capture queue */
+ spinlock_t vb_lock;
+ struct timer_list vb_timeout;
+
+ struct videobuf_queue vbuf_q;
+ spinlock_t vbuf_q_lock; /* Protect vbuf_q */
+ enum v4l2_buf_type vb_type;
+};
+
+struct cx18_videobuf_buffer {
+ /* Common video buffer sub-system struct */
+ struct videobuf_buffer vb;
+ v4l2_std_id tvnorm; /* selected tv norm */
+ u32 bytes_used;
};
struct cx18_open_id {
@@ -410,6 +431,10 @@
u32 open_id;
int type;
struct cx18 *cx;
+
+ struct videobuf_queue vbuf_q;
+ spinlock_t s_lock; /* Protect vbuf_q */
+ enum v4l2_buf_type vb_type;
};
static inline struct cx18_open_id *fh2id(struct v4l2_fh *fh)
diff --git a/drivers/media/video/cx18/cx18-fileops.c b/drivers/media/video/cx18/cx18-fileops.c
index e9802d9..07411f3 100644
--- a/drivers/media/video/cx18/cx18-fileops.c
+++ b/drivers/media/video/cx18/cx18-fileops.c
@@ -597,6 +597,13 @@
mutex_unlock(&cx->serialize_lock);
if (rc)
return rc;
+
+ if ((s->vb_type == V4L2_BUF_TYPE_VIDEO_CAPTURE) &&
+ (id->type == CX18_ENC_STREAM_TYPE_YUV)) {
+ return videobuf_read_stream(&s->vbuf_q, buf, count, pos, 0,
+ filp->f_flags & O_NONBLOCK);
+ }
+
return cx18_read_pos(s, buf, count, pos, filp->f_flags & O_NONBLOCK);
}
@@ -622,6 +629,15 @@
CX18_DEBUG_FILE("Encoder poll started capture\n");
}
+ if ((s->vb_type == V4L2_BUF_TYPE_VIDEO_CAPTURE) &&
+ (id->type == CX18_ENC_STREAM_TYPE_YUV)) {
+ int videobuf_poll = videobuf_poll_stream(filp, &s->vbuf_q, wait);
+ if (eof && videobuf_poll == POLLERR)
+ return POLLHUP;
+ else
+ return videobuf_poll;
+ }
+
/* add stream's waitq to the poll list */
CX18_DEBUG_HI_FILE("Encoder poll\n");
poll_wait(filp, &s->waitq, wait);
@@ -633,6 +649,58 @@
return 0;
}
+int cx18_v4l2_mmap(struct file *file, struct vm_area_struct *vma)
+{
+ struct cx18_open_id *id = file->private_data;
+ struct cx18 *cx = id->cx;
+ struct cx18_stream *s = &cx->streams[id->type];
+ int eof = test_bit(CX18_F_S_STREAMOFF, &s->s_flags);
+
+ if ((s->vb_type == V4L2_BUF_TYPE_VIDEO_CAPTURE) &&
+ (id->type == CX18_ENC_STREAM_TYPE_YUV)) {
+
+ /* Start a capture if there is none */
+ if (!eof && !test_bit(CX18_F_S_STREAMING, &s->s_flags)) {
+ int rc;
+
+ mutex_lock(&cx->serialize_lock);
+ rc = cx18_start_capture(id);
+ mutex_unlock(&cx->serialize_lock);
+ if (rc) {
+ CX18_DEBUG_INFO(
+ "Could not start capture for %s (%d)\n",
+ s->name, rc);
+ return -EINVAL;
+ }
+ CX18_DEBUG_FILE("Encoder mmap started capture\n");
+ }
+
+ return videobuf_mmap_mapper(&s->vbuf_q, vma);
+ }
+
+ return -EINVAL;
+}
+
+void cx18_vb_timeout(unsigned long data)
+{
+ struct cx18_stream *s = (struct cx18_stream *)data;
+ struct cx18_videobuf_buffer *buf;
+ unsigned long flags;
+
+ /* Return all of the buffers in error state, so the vbi/vid inode
+ * can return from blocking.
+ */
+ spin_lock_irqsave(&s->vb_lock, flags);
+ while (!list_empty(&s->vb_capture)) {
+ buf = list_entry(s->vb_capture.next,
+ struct cx18_videobuf_buffer, vb.queue);
+ list_del(&buf->vb.queue);
+ buf->vb.state = VIDEOBUF_ERROR;
+ wake_up(&buf->vb.done);
+ }
+ spin_unlock_irqrestore(&s->vb_lock, flags);
+}
+
void cx18_stop_capture(struct cx18_open_id *id, int gop_end)
{
struct cx18 *cx = id->cx;
@@ -716,6 +784,8 @@
cx18_release_stream(s);
} else {
cx18_stop_capture(id, 0);
+ if (id->type == CX18_ENC_STREAM_TYPE_YUV)
+ videobuf_mmap_free(&id->vbuf_q);
}
kfree(id);
mutex_unlock(&cx->serialize_lock);
diff --git a/drivers/media/video/cx18/cx18-fileops.h b/drivers/media/video/cx18/cx18-fileops.h
index 5c8fcb8..b9e5110 100644
--- a/drivers/media/video/cx18/cx18-fileops.h
+++ b/drivers/media/video/cx18/cx18-fileops.h
@@ -33,6 +33,8 @@
void cx18_stop_capture(struct cx18_open_id *id, int gop_end);
void cx18_mute(struct cx18 *cx);
void cx18_unmute(struct cx18 *cx);
+int cx18_v4l2_mmap(struct file *file, struct vm_area_struct *vma);
+void cx18_vb_timeout(unsigned long data);
/* Shared with cx18-alsa module */
int cx18_claim_stream(struct cx18_open_id *id, int type);
diff --git a/drivers/media/video/cx18/cx18-ioctl.c b/drivers/media/video/cx18/cx18-ioctl.c
index 4f041c0..1933d4d 100644
--- a/drivers/media/video/cx18/cx18-ioctl.c
+++ b/drivers/media/video/cx18/cx18-ioctl.c
@@ -150,6 +150,7 @@
{
struct cx18_open_id *id = fh2id(fh);
struct cx18 *cx = id->cx;
+ struct cx18_stream *s = &cx->streams[id->type];
struct v4l2_pix_format *pixfmt = &fmt->fmt.pix;
pixfmt->width = cx->cxhdl.width;
@@ -158,9 +159,13 @@
pixfmt->field = V4L2_FIELD_INTERLACED;
pixfmt->priv = 0;
if (id->type == CX18_ENC_STREAM_TYPE_YUV) {
- pixfmt->pixelformat = V4L2_PIX_FMT_HM12;
- /* YUV size is (Y=(h*720) + UV=(h*(720/2))) */
- pixfmt->sizeimage = pixfmt->height * 720 * 3 / 2;
+ pixfmt->pixelformat = s->pixelformat;
+ /* HM12 YUV size is (Y=(h*720) + UV=(h*(720/2)))
+ UYUV YUV size is (Y=(h*720) + UV=(h*(720))) */
+ if (s->pixelformat == V4L2_PIX_FMT_HM12)
+ pixfmt->sizeimage = pixfmt->height * 720 * 3 / 2;
+ else
+ pixfmt->sizeimage = pixfmt->height * 720 * 2;
pixfmt->bytesperline = 720;
} else {
pixfmt->pixelformat = V4L2_PIX_FMT_MPEG;
@@ -237,7 +242,6 @@
h = min(h, cx->is_50hz ? 576 : 480);
h = max(h, min_h);
- cx18_g_fmt_vid_cap(file, fh, fmt);
fmt->fmt.pix.width = w;
fmt->fmt.pix.height = h;
return 0;
@@ -274,6 +278,7 @@
struct cx18_open_id *id = fh2id(fh);
struct cx18 *cx = id->cx;
struct v4l2_mbus_framefmt mbus_fmt;
+ struct cx18_stream *s = &cx->streams[id->type];
int ret;
int w, h;
@@ -283,12 +288,15 @@
w = fmt->fmt.pix.width;
h = fmt->fmt.pix.height;
- if (cx->cxhdl.width == w && cx->cxhdl.height == h)
+ if (cx->cxhdl.width == w && cx->cxhdl.height == h &&
+ s->pixelformat == fmt->fmt.pix.pixelformat)
return 0;
if (atomic_read(&cx->ana_capturing) > 0)
return -EBUSY;
+ s->pixelformat = fmt->fmt.pix.pixelformat;
+
mbus_fmt.width = cx->cxhdl.width = w;
mbus_fmt.height = cx->cxhdl.height = h;
mbus_fmt.code = V4L2_MBUS_FMT_FIXED;
@@ -540,16 +548,19 @@
static int cx18_enum_fmt_vid_cap(struct file *file, void *fh,
struct v4l2_fmtdesc *fmt)
{
- static struct v4l2_fmtdesc formats[] = {
+ static const struct v4l2_fmtdesc formats[] = {
{ 0, V4L2_BUF_TYPE_VIDEO_CAPTURE, 0,
"HM12 (YUV 4:1:1)", V4L2_PIX_FMT_HM12, { 0, 0, 0, 0 }
},
{ 1, V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FMT_FLAG_COMPRESSED,
"MPEG", V4L2_PIX_FMT_MPEG, { 0, 0, 0, 0 }
- }
+ },
+ { 2, V4L2_BUF_TYPE_VIDEO_CAPTURE, 0,
+ "UYVY 4:2:2", V4L2_PIX_FMT_UYVY, { 0, 0, 0, 0 }
+ },
};
- if (fmt->index > 1)
+ if (fmt->index > ARRAY_SIZE(formats) - 1)
return -EINVAL;
*fmt = formats[fmt->index];
return 0;
@@ -863,6 +874,117 @@
return 0;
}
+static struct videobuf_queue *cx18_vb_queue(struct cx18_open_id *id)
+{
+ struct videobuf_queue *q = NULL;
+ struct cx18 *cx = id->cx;
+ struct cx18_stream *s = &cx->streams[id->type];
+
+ switch (s->vb_type) {
+ case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+ q = &s->vbuf_q;
+ break;
+ case V4L2_BUF_TYPE_VBI_CAPTURE:
+ break;
+ default:
+ break;
+ }
+ return q;
+}
+
+static int cx18_streamon(struct file *file, void *priv,
+ enum v4l2_buf_type type)
+{
+ struct cx18_open_id *id = file->private_data;
+ struct cx18 *cx = id->cx;
+ struct cx18_stream *s = &cx->streams[id->type];
+
+ /* Start the hardware only if we're the video device */
+ if ((s->vb_type != V4L2_BUF_TYPE_VIDEO_CAPTURE) &&
+ (s->vb_type != V4L2_BUF_TYPE_VBI_CAPTURE))
+ return -EINVAL;
+
+ if (id->type != CX18_ENC_STREAM_TYPE_YUV)
+ return -EINVAL;
+
+ /* Establish a buffer timeout */
+ mod_timer(&s->vb_timeout, msecs_to_jiffies(2000) + jiffies);
+
+ return videobuf_streamon(cx18_vb_queue(id));
+}
+
+static int cx18_streamoff(struct file *file, void *priv,
+ enum v4l2_buf_type type)
+{
+ struct cx18_open_id *id = file->private_data;
+ struct cx18 *cx = id->cx;
+ struct cx18_stream *s = &cx->streams[id->type];
+
+ /* Start the hardware only if we're the video device */
+ if ((s->vb_type != V4L2_BUF_TYPE_VIDEO_CAPTURE) &&
+ (s->vb_type != V4L2_BUF_TYPE_VBI_CAPTURE))
+ return -EINVAL;
+
+ if (id->type != CX18_ENC_STREAM_TYPE_YUV)
+ return -EINVAL;
+
+ return videobuf_streamoff(cx18_vb_queue(id));
+}
+
+static int cx18_reqbufs(struct file *file, void *priv,
+ struct v4l2_requestbuffers *rb)
+{
+ struct cx18_open_id *id = file->private_data;
+ struct cx18 *cx = id->cx;
+ struct cx18_stream *s = &cx->streams[id->type];
+
+ if ((s->vb_type != V4L2_BUF_TYPE_VIDEO_CAPTURE) &&
+ (s->vb_type != V4L2_BUF_TYPE_VBI_CAPTURE))
+ return -EINVAL;
+
+ return videobuf_reqbufs(cx18_vb_queue(id), rb);
+}
+
+static int cx18_querybuf(struct file *file, void *priv,
+ struct v4l2_buffer *b)
+{
+ struct cx18_open_id *id = file->private_data;
+ struct cx18 *cx = id->cx;
+ struct cx18_stream *s = &cx->streams[id->type];
+
+ if ((s->vb_type != V4L2_BUF_TYPE_VIDEO_CAPTURE) &&
+ (s->vb_type != V4L2_BUF_TYPE_VBI_CAPTURE))
+ return -EINVAL;
+
+ return videobuf_querybuf(cx18_vb_queue(id), b);
+}
+
+static int cx18_qbuf(struct file *file, void *priv, struct v4l2_buffer *b)
+{
+ struct cx18_open_id *id = file->private_data;
+ struct cx18 *cx = id->cx;
+ struct cx18_stream *s = &cx->streams[id->type];
+
+ if ((s->vb_type != V4L2_BUF_TYPE_VIDEO_CAPTURE) &&
+ (s->vb_type != V4L2_BUF_TYPE_VBI_CAPTURE))
+ return -EINVAL;
+
+ return videobuf_qbuf(cx18_vb_queue(id), b);
+}
+
+static int cx18_dqbuf(struct file *file, void *priv, struct v4l2_buffer *b)
+{
+ struct cx18_open_id *id = file->private_data;
+ struct cx18 *cx = id->cx;
+ struct cx18_stream *s = &cx->streams[id->type];
+
+ if ((s->vb_type != V4L2_BUF_TYPE_VIDEO_CAPTURE) &&
+ (s->vb_type != V4L2_BUF_TYPE_VBI_CAPTURE))
+ return -EINVAL;
+
+ return videobuf_dqbuf(cx18_vb_queue(id), b, file->f_flags & O_NONBLOCK);
+}
+
static int cx18_encoder_cmd(struct file *file, void *fh,
struct v4l2_encoder_cmd *enc)
{
@@ -1081,6 +1203,12 @@
.vidioc_s_register = cx18_s_register,
#endif
.vidioc_default = cx18_default,
+ .vidioc_streamon = cx18_streamon,
+ .vidioc_streamoff = cx18_streamoff,
+ .vidioc_reqbufs = cx18_reqbufs,
+ .vidioc_querybuf = cx18_querybuf,
+ .vidioc_qbuf = cx18_qbuf,
+ .vidioc_dqbuf = cx18_dqbuf,
};
void cx18_set_funcs(struct video_device *vdev)
diff --git a/drivers/media/video/cx18/cx18-mailbox.c b/drivers/media/video/cx18/cx18-mailbox.c
index 9605d54..c07191e 100644
--- a/drivers/media/video/cx18/cx18-mailbox.c
+++ b/drivers/media/video/cx18/cx18-mailbox.c
@@ -81,6 +81,7 @@
API_ENTRY(CPU, CX18_CPU_SET_SLICED_VBI_PARAM, 0),
API_ENTRY(CPU, CX18_CPU_SET_USERDATA_PLACE_HOLDER, 0),
API_ENTRY(CPU, CX18_CPU_GET_ENC_PTS, 0),
+ API_ENTRY(CPU, CX18_CPU_SET_VFC_PARAM, 0),
API_ENTRY(CPU, CX18_CPU_DE_SET_MDL_ACK, 0),
API_ENTRY(CPU, CX18_CPU_DE_SET_MDL, API_FAST),
API_ENTRY(CPU, CX18_CPU_DE_RELEASE_MDL, API_SLOW),
@@ -158,6 +159,60 @@
}
}
+static void cx18_mdl_send_to_videobuf(struct cx18_stream *s,
+ struct cx18_mdl *mdl)
+{
+ struct cx18_videobuf_buffer *vb_buf;
+ struct cx18_buffer *buf;
+ u8 *p;
+ u32 offset = 0;
+ int dispatch = 0;
+
+ if (mdl->bytesused == 0)
+ return;
+
+ /* Acquire a videobuf buffer, clone to and and release it */
+ spin_lock(&s->vb_lock);
+ if (list_empty(&s->vb_capture))
+ goto out;
+
+ vb_buf = list_first_entry(&s->vb_capture, struct cx18_videobuf_buffer,
+ vb.queue);
+
+ p = videobuf_to_vmalloc(&vb_buf->vb);
+ if (!p)
+ goto out;
+
+ offset = vb_buf->bytes_used;
+ list_for_each_entry(buf, &mdl->buf_list, list) {
+ if (buf->bytesused == 0)
+ break;
+
+ if ((offset + buf->bytesused) <= vb_buf->vb.bsize) {
+ memcpy(p + offset, buf->buf, buf->bytesused);
+ offset += buf->bytesused;
+ vb_buf->bytes_used += buf->bytesused;
+ }
+ }
+
+ /* If we've filled the buffer as per the callers res then dispatch it */
+ if (vb_buf->bytes_used >= (vb_buf->vb.width * vb_buf->vb.height * 2)) {
+ dispatch = 1;
+ vb_buf->bytes_used = 0;
+ }
+
+ if (dispatch) {
+ vb_buf->vb.ts = ktime_to_timeval(ktime_get());
+ list_del(&vb_buf->vb.queue);
+ vb_buf->vb.state = VIDEOBUF_DONE;
+ wake_up(&vb_buf->vb.done);
+ }
+
+ mod_timer(&s->vb_timeout, msecs_to_jiffies(2000) + jiffies);
+
+out:
+ spin_unlock(&s->vb_lock);
+}
static void cx18_mdl_send_to_alsa(struct cx18 *cx, struct cx18_stream *s,
struct cx18_mdl *mdl)
@@ -263,6 +318,9 @@
} else {
cx18_enqueue(s, mdl, &s->q_full);
}
+ } else if (s->type == CX18_ENC_STREAM_TYPE_YUV) {
+ cx18_mdl_send_to_videobuf(s, mdl);
+ cx18_enqueue(s, mdl, &s->q_free);
} else {
cx18_enqueue(s, mdl, &s->q_full);
if (s->type == CX18_ENC_STREAM_TYPE_IDX)
diff --git a/drivers/media/video/cx18/cx18-streams.c b/drivers/media/video/cx18/cx18-streams.c
index 6fbc356..852f420 100644
--- a/drivers/media/video/cx18/cx18-streams.c
+++ b/drivers/media/video/cx18/cx18-streams.c
@@ -44,6 +44,7 @@
.unlocked_ioctl = cx18_v4l2_ioctl,
.release = cx18_v4l2_close,
.poll = cx18_v4l2_enc_poll,
+ .mmap = cx18_v4l2_mmap,
};
/* offset from 0 to register ts v4l2 minors on */
@@ -97,6 +98,141 @@
},
};
+
+void cx18_dma_free(struct videobuf_queue *q,
+ struct cx18_stream *s, struct cx18_videobuf_buffer *buf)
+{
+ videobuf_waiton(q, &buf->vb, 0, 0);
+ videobuf_vmalloc_free(&buf->vb);
+ buf->vb.state = VIDEOBUF_NEEDS_INIT;
+}
+
+static int cx18_prepare_buffer(struct videobuf_queue *q,
+ struct cx18_stream *s,
+ struct cx18_videobuf_buffer *buf,
+ u32 pixelformat,
+ unsigned int width, unsigned int height,
+ enum v4l2_field field)
+{
+ struct cx18 *cx = s->cx;
+ int rc = 0;
+
+ /* check settings */
+ buf->bytes_used = 0;
+
+ if ((width < 48) || (height < 32))
+ return -EINVAL;
+
+ buf->vb.size = (width * height * 2);
+ if ((buf->vb.baddr != 0) && (buf->vb.bsize < buf->vb.size))
+ return -EINVAL;
+
+ /* alloc + fill struct (if changed) */
+ if (buf->vb.width != width || buf->vb.height != height ||
+ buf->vb.field != field || s->pixelformat != pixelformat ||
+ buf->tvnorm != cx->std) {
+
+ buf->vb.width = width;
+ buf->vb.height = height;
+ buf->vb.field = field;
+ buf->tvnorm = cx->std;
+ s->pixelformat = pixelformat;
+
+ cx18_dma_free(q, s, buf);
+ }
+
+ if ((buf->vb.baddr != 0) && (buf->vb.bsize < buf->vb.size))
+ return -EINVAL;
+
+ if (buf->vb.field == 0)
+ buf->vb.field = V4L2_FIELD_INTERLACED;
+
+ if (VIDEOBUF_NEEDS_INIT == buf->vb.state) {
+ buf->vb.width = width;
+ buf->vb.height = height;
+ buf->vb.field = field;
+ buf->tvnorm = cx->std;
+ s->pixelformat = pixelformat;
+
+ rc = videobuf_iolock(q, &buf->vb, NULL);
+ if (rc != 0)
+ goto fail;
+ }
+ buf->vb.state = VIDEOBUF_PREPARED;
+ return 0;
+
+fail:
+ cx18_dma_free(q, s, buf);
+ return rc;
+
+}
+
+/* VB_MIN_BUFSIZE is lcm(1440 * 480, 1440 * 576)
+ 1440 is a single line of 4:2:2 YUV at 720 luma samples wide
+*/
+#define VB_MIN_BUFFERS 32
+#define VB_MIN_BUFSIZE 4147200
+
+static int buffer_setup(struct videobuf_queue *q,
+ unsigned int *count, unsigned int *size)
+{
+ struct cx18_stream *s = q->priv_data;
+ struct cx18 *cx = s->cx;
+
+ *size = 2 * cx->cxhdl.width * cx->cxhdl.height;
+ if (*count == 0)
+ *count = VB_MIN_BUFFERS;
+
+ while (*size * *count > VB_MIN_BUFFERS * VB_MIN_BUFSIZE)
+ (*count)--;
+
+ q->field = V4L2_FIELD_INTERLACED;
+ q->last = V4L2_FIELD_INTERLACED;
+
+ return 0;
+}
+
+static int buffer_prepare(struct videobuf_queue *q,
+ struct videobuf_buffer *vb,
+ enum v4l2_field field)
+{
+ struct cx18_videobuf_buffer *buf =
+ container_of(vb, struct cx18_videobuf_buffer, vb);
+ struct cx18_stream *s = q->priv_data;
+ struct cx18 *cx = s->cx;
+
+ return cx18_prepare_buffer(q, s, buf, s->pixelformat,
+ cx->cxhdl.width, cx->cxhdl.height, field);
+}
+
+static void buffer_release(struct videobuf_queue *q,
+ struct videobuf_buffer *vb)
+{
+ struct cx18_videobuf_buffer *buf =
+ container_of(vb, struct cx18_videobuf_buffer, vb);
+ struct cx18_stream *s = q->priv_data;
+
+ cx18_dma_free(q, s, buf);
+}
+
+static void buffer_queue(struct videobuf_queue *q, struct videobuf_buffer *vb)
+{
+ struct cx18_videobuf_buffer *buf =
+ container_of(vb, struct cx18_videobuf_buffer, vb);
+ struct cx18_stream *s = q->priv_data;
+
+ buf->vb.state = VIDEOBUF_QUEUED;
+
+ list_add_tail(&buf->vb.queue, &s->vb_capture);
+}
+
+static struct videobuf_queue_ops cx18_videobuf_qops = {
+ .buf_setup = buffer_setup,
+ .buf_prepare = buffer_prepare,
+ .buf_queue = buffer_queue,
+ .buf_release = buffer_release,
+};
+
static void cx18_stream_init(struct cx18 *cx, int type)
{
struct cx18_stream *s = &cx->streams[type];
@@ -132,6 +268,26 @@
cx18_queue_init(&s->q_idle);
INIT_WORK(&s->out_work_order, cx18_out_work_handler);
+
+ INIT_LIST_HEAD(&s->vb_capture);
+ s->vb_timeout.function = cx18_vb_timeout;
+ s->vb_timeout.data = (unsigned long)s;
+ init_timer(&s->vb_timeout);
+ spin_lock_init(&s->vb_lock);
+ if (type == CX18_ENC_STREAM_TYPE_YUV) {
+ spin_lock_init(&s->vbuf_q_lock);
+
+ s->vb_type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
+ videobuf_queue_vmalloc_init(&s->vbuf_q, &cx18_videobuf_qops,
+ &cx->pci_dev->dev, &s->vbuf_q_lock,
+ V4L2_BUF_TYPE_VIDEO_CAPTURE,
+ V4L2_FIELD_INTERLACED,
+ sizeof(struct cx18_videobuf_buffer),
+ s, &cx->serialize_lock);
+
+ /* Assume the previous pixel default */
+ s->pixelformat = V4L2_PIX_FMT_HM12;
+ }
}
static int cx18_prep_dev(struct cx18 *cx, int type)
@@ -372,6 +528,9 @@
if (vdev == NULL)
continue;
+ if (type == CX18_ENC_STREAM_TYPE_YUV)
+ videobuf_mmap_free(&cx->streams[type].vbuf_q);
+
cx18_stream_free(&cx->streams[type]);
/* Unregister or release device */
@@ -581,7 +740,10 @@
* Set the MDL size to the exact size needed for one frame.
* Use enough buffers per MDL to cover the MDL size
*/
- s->mdl_size = 720 * s->cx->cxhdl.height * 3 / 2;
+ if (s->pixelformat == V4L2_PIX_FMT_HM12)
+ s->mdl_size = 720 * s->cx->cxhdl.height * 3 / 2;
+ else
+ s->mdl_size = 720 * s->cx->cxhdl.height * 2;
s->bufs_per_mdl = s->mdl_size / s->buf_size;
if (s->mdl_size % s->buf_size)
s->bufs_per_mdl++;
@@ -729,6 +891,19 @@
test_bit(CX18_F_I_RADIO_USER, &cx->i_flags))
cx18_vapi(cx, CX18_CPU_SET_VIDEO_MUTE, 2, s->handle,
(v4l2_ctrl_g_ctrl(cx->cxhdl.video_mute_yuv) << 8) | 1);
+
+ /* Enable the Video Format Converter for UYVY 4:2:2 support,
+ * rather than the default HM12 Macroblovk 4:2:0 support.
+ */
+ if (captype == CAPTURE_CHANNEL_TYPE_YUV) {
+ if (s->pixelformat == V4L2_PIX_FMT_UYVY)
+ cx18_vapi(cx, CX18_CPU_SET_VFC_PARAM, 2,
+ s->handle, 1);
+ else
+ /* If in doubt, default to HM12 */
+ cx18_vapi(cx, CX18_CPU_SET_VFC_PARAM, 2,
+ s->handle, 0);
+ }
}
if (atomic_read(&cx->tot_capturing) == 0) {
diff --git a/drivers/media/video/cx18/cx18-version.h b/drivers/media/video/cx18/cx18-version.h
index 3e1aec4..cd189b6 100644
--- a/drivers/media/video/cx18/cx18-version.h
+++ b/drivers/media/video/cx18/cx18-version.h
@@ -24,7 +24,7 @@
#define CX18_DRIVER_NAME "cx18"
#define CX18_DRIVER_VERSION_MAJOR 1
-#define CX18_DRIVER_VERSION_MINOR 4
+#define CX18_DRIVER_VERSION_MINOR 5
#define CX18_DRIVER_VERSION_PATCHLEVEL 0
#define CX18_VERSION __stringify(CX18_DRIVER_VERSION_MAJOR) "." __stringify(CX18_DRIVER_VERSION_MINOR) "." __stringify(CX18_DRIVER_VERSION_PATCHLEVEL)
diff --git a/drivers/media/video/cx18/cx23418.h b/drivers/media/video/cx18/cx23418.h
index 935f557..767a8d2 100644
--- a/drivers/media/video/cx18/cx23418.h
+++ b/drivers/media/video/cx18/cx23418.h
@@ -342,6 +342,12 @@
ReturnCode */
#define CX18_CPU_GET_ENC_PTS (CPU_CMD_MASK_CAPTURE | 0x0022)
+/* Description: Set VFC parameters
+ IN[0] - task handle
+ IN[1] - VFC enable flag, 1 - enable, 0 - disable
+*/
+#define CX18_CPU_SET_VFC_PARAM (CPU_CMD_MASK_CAPTURE | 0x0023)
+
/* Below is the list of commands related to the data exchange */
#define CPU_CMD_MASK_DE (CPU_CMD_MASK | 0x040000)
diff --git a/drivers/media/video/cx231xx/cx231xx-cards.c b/drivers/media/video/cx231xx/cx231xx-cards.c
index f49230d..2270381 100644
--- a/drivers/media/video/cx231xx/cx231xx-cards.c
+++ b/drivers/media/video/cx231xx/cx231xx-cards.c
@@ -401,6 +401,44 @@
.gpio = NULL,
} },
},
+ [CX231XX_BOARD_KWORLD_UB430_USB_HYBRID] = {
+ .name = "Kworld UB430 USB Hybrid",
+ .tuner_type = TUNER_NXP_TDA18271,
+ .tuner_addr = 0x60,
+ .decoder = CX231XX_AVDECODER,
+ .output_mode = OUT_MODE_VIP11,
+ .demod_xfer_mode = 0,
+ .ctl_pin_status_mask = 0xFFFFFFC4,
+ .agc_analog_digital_select_gpio = 0x11, /* According with PV cxPolaris.inf file */
+ .tuner_sif_gpio = -1,
+ .tuner_scl_gpio = -1,
+ .tuner_sda_gpio = -1,
+ .gpio_pin_status_mask = 0x4001000,
+ .tuner_i2c_master = 2,
+ .demod_i2c_master = 1,
+ .ir_i2c_master = 2,
+ .has_dvb = 1,
+ .demod_addr = 0x10,
+ .norm = V4L2_STD_PAL_M,
+ .input = {{
+ .type = CX231XX_VMUX_TELEVISION,
+ .vmux = CX231XX_VIN_3_1,
+ .amux = CX231XX_AMUX_VIDEO,
+ .gpio = NULL,
+ }, {
+ .type = CX231XX_VMUX_COMPOSITE1,
+ .vmux = CX231XX_VIN_2_1,
+ .amux = CX231XX_AMUX_LINE_IN,
+ .gpio = NULL,
+ }, {
+ .type = CX231XX_VMUX_SVIDEO,
+ .vmux = CX231XX_VIN_1_1 |
+ (CX231XX_VIN_1_2 << 8) |
+ CX25840_SVIDEO_ON,
+ .amux = CX231XX_AMUX_LINE_IN,
+ .gpio = NULL,
+ } },
+ },
[CX231XX_BOARD_PV_PLAYTV_USB_HYBRID] = {
.name = "Pixelview PlayTV USB Hybrid",
.tuner_type = TUNER_NXP_TDA18271,
@@ -469,6 +507,31 @@
}
},
},
+
+ [CX231XX_BOARD_ICONBIT_U100] = {
+ .name = "Iconbit Analog Stick U100 FM",
+ .tuner_type = TUNER_ABSENT,
+ .decoder = CX231XX_AVDECODER,
+ .output_mode = OUT_MODE_VIP11,
+ .demod_xfer_mode = 0,
+ .ctl_pin_status_mask = 0xFFFFFFC4,
+ .agc_analog_digital_select_gpio = 0x1C,
+ .gpio_pin_status_mask = 0x4001000,
+
+ .input = {{
+ .type = CX231XX_VMUX_COMPOSITE1,
+ .vmux = CX231XX_VIN_2_1,
+ .amux = CX231XX_AMUX_LINE_IN,
+ .gpio = NULL,
+ }, {
+ .type = CX231XX_VMUX_SVIDEO,
+ .vmux = CX231XX_VIN_1_1 |
+ (CX231XX_VIN_1_2 << 8) |
+ CX25840_SVIDEO_ON,
+ .amux = CX231XX_AMUX_LINE_IN,
+ .gpio = NULL,
+ } },
+ },
};
const unsigned int cx231xx_bcount = ARRAY_SIZE(cx231xx_boards);
@@ -500,6 +563,10 @@
.driver_info = CX231XX_BOARD_PV_PLAYTV_USB_HYBRID},
{USB_DEVICE(USB_VID_PIXELVIEW, 0x5014),
.driver_info = CX231XX_BOARD_PV_XCAPTURE_USB},
+ {USB_DEVICE(0x1b80, 0xe424),
+ .driver_info = CX231XX_BOARD_KWORLD_UB430_USB_HYBRID},
+ {USB_DEVICE(0x1f4d, 0x0237),
+ .driver_info = CX231XX_BOARD_ICONBIT_U100},
{},
};
diff --git a/drivers/media/video/cx231xx/cx231xx-dvb.c b/drivers/media/video/cx231xx/cx231xx-dvb.c
index 363aa60..da9a4a0 100644
--- a/drivers/media/video/cx231xx/cx231xx-dvb.c
+++ b/drivers/media/video/cx231xx/cx231xx-dvb.c
@@ -704,6 +704,7 @@
break;
case CX231XX_BOARD_PV_PLAYTV_USB_HYBRID:
+ case CX231XX_BOARD_KWORLD_UB430_USB_HYBRID:
printk(KERN_INFO "%s: looking for demod on i2c bus: %d\n",
__func__, i2c_adapter_id(&dev->i2c_bus[dev->board.tuner_i2c_master].i2c_adap));
diff --git a/drivers/media/video/cx231xx/cx231xx.h b/drivers/media/video/cx231xx/cx231xx.h
index bd4a9cf..46dd840 100644
--- a/drivers/media/video/cx231xx/cx231xx.h
+++ b/drivers/media/video/cx231xx/cx231xx.h
@@ -65,6 +65,8 @@
#define CX231XX_BOARD_HAUPPAUGE_USBLIVE2 9
#define CX231XX_BOARD_PV_PLAYTV_USB_HYBRID 10
#define CX231XX_BOARD_PV_XCAPTURE_USB 11
+#define CX231XX_BOARD_KWORLD_UB430_USB_HYBRID 12
+#define CX231XX_BOARD_ICONBIT_U100 13
/* Limits minimum and default number of buffers */
#define CX231XX_MIN_BUF 4
diff --git a/drivers/media/video/cx23885/cx23885-cards.c b/drivers/media/video/cx23885/cx23885-cards.c
index ea88722..2354336 100644
--- a/drivers/media/video/cx23885/cx23885-cards.c
+++ b/drivers/media/video/cx23885/cx23885-cards.c
@@ -1399,6 +1399,7 @@
else
altera_init(&netup_config, fw);
+ release_firmware(fw);
break;
}
}
diff --git a/drivers/media/video/cx23885/cx23885-core.c b/drivers/media/video/cx23885/cx23885-core.c
index 9933810..64d9b21 100644
--- a/drivers/media/video/cx23885/cx23885-core.c
+++ b/drivers/media/video/cx23885/cx23885-core.c
@@ -2045,7 +2045,7 @@
}
/* print pci info */
- pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &dev->pci_rev);
+ dev->pci_rev = pci_dev->revision;
pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat);
printk(KERN_INFO "%s/0: found at %s, rev: %d, irq: %d, "
"latency: %d, mmio: 0x%llx\n", dev->name,
diff --git a/drivers/media/video/cx88/cx88-blackbird.c b/drivers/media/video/cx88/cx88-blackbird.c
index bca307e..11e49bb 100644
--- a/drivers/media/video/cx88/cx88-blackbird.c
+++ b/drivers/media/video/cx88/cx88-blackbird.c
@@ -1060,18 +1060,21 @@
/* Make sure we can acquire the hardware */
drv = cx8802_get_driver(dev, CX88_MPEG_BLACKBIRD);
- if (drv) {
- err = drv->request_acquire(drv);
- if(err != 0) {
- dprintk(1,"%s: Unable to acquire hardware, %d\n", __func__, err);
- mutex_unlock(&dev->core->lock);
- return err;
- }
+ if (!drv) {
+ dprintk(1, "%s: blackbird driver is not loaded\n", __func__);
+ mutex_unlock(&dev->core->lock);
+ return -ENODEV;
}
- if (!atomic_read(&dev->core->mpeg_users) && blackbird_initialize_codec(dev) < 0) {
- if (drv)
- drv->request_release(drv);
+ err = drv->request_acquire(drv);
+ if (err != 0) {
+ dprintk(1,"%s: Unable to acquire hardware, %d\n", __func__, err);
+ mutex_unlock(&dev->core->lock);
+ return err;
+ }
+
+ if (!dev->core->mpeg_users && blackbird_initialize_codec(dev) < 0) {
+ drv->request_release(drv);
mutex_unlock(&dev->core->lock);
return -EINVAL;
}
@@ -1080,8 +1083,7 @@
/* allocate + initialize per filehandle data */
fh = kzalloc(sizeof(*fh),GFP_KERNEL);
if (NULL == fh) {
- if (drv)
- drv->request_release(drv);
+ drv->request_release(drv);
mutex_unlock(&dev->core->lock);
return -ENOMEM;
}
@@ -1099,7 +1101,7 @@
cx88_set_scale(dev->core, dev->width, dev->height,
fh->mpegq.field);
- atomic_inc(&dev->core->mpeg_users);
+ dev->core->mpeg_users++;
mutex_unlock(&dev->core->lock);
return 0;
}
@@ -1110,7 +1112,9 @@
struct cx8802_dev *dev = fh->dev;
struct cx8802_driver *drv = NULL;
- if (dev->mpeg_active && atomic_read(&dev->core->mpeg_users) == 1)
+ mutex_lock(&dev->core->lock);
+
+ if (dev->mpeg_active && dev->core->mpeg_users == 1)
blackbird_stop_codec(dev);
cx8802_cancel_buffers(fh->dev);
@@ -1119,17 +1123,18 @@
videobuf_mmap_free(&fh->mpegq);
- mutex_lock(&dev->core->lock);
file->private_data = NULL;
kfree(fh);
- mutex_unlock(&dev->core->lock);
/* Make sure we release the hardware */
drv = cx8802_get_driver(dev, CX88_MPEG_BLACKBIRD);
+ WARN_ON(!drv);
if (drv)
drv->request_release(drv);
- atomic_dec(&dev->core->mpeg_users);
+ dev->core->mpeg_users--;
+
+ mutex_unlock(&dev->core->lock);
return 0;
}
@@ -1334,11 +1339,9 @@
blackbird_register_video(dev);
/* initial device configuration: needed ? */
- mutex_lock(&dev->core->lock);
// init_controls(core);
cx88_set_tvnorm(core,core->tvnorm);
cx88_video_mux(core,0);
- mutex_unlock(&dev->core->lock);
return 0;
diff --git a/drivers/media/video/cx88/cx88-dvb.c b/drivers/media/video/cx88/cx88-dvb.c
index 7b8c9d3..c69df7e 100644
--- a/drivers/media/video/cx88/cx88-dvb.c
+++ b/drivers/media/video/cx88/cx88-dvb.c
@@ -133,6 +133,7 @@
return -EINVAL;
}
+ mutex_lock(&dev->core->lock);
drv = cx8802_get_driver(dev, CX88_MPEG_DVB);
if (drv) {
if (acquire){
@@ -143,6 +144,7 @@
dev->frontends.active_fe_id = 0;
}
}
+ mutex_unlock(&dev->core->lock);
return ret;
}
diff --git a/drivers/media/video/cx88/cx88-mpeg.c b/drivers/media/video/cx88/cx88-mpeg.c
index addf954..1a7b983 100644
--- a/drivers/media/video/cx88/cx88-mpeg.c
+++ b/drivers/media/video/cx88/cx88-mpeg.c
@@ -78,6 +78,7 @@
static LIST_HEAD(cx8802_devlist);
+static DEFINE_MUTEX(cx8802_mutex);
/* ------------------------------------------------------------------ */
static int cx8802_start_dma(struct cx8802_dev *dev,
@@ -474,7 +475,7 @@
return -EIO;
}
- pci_read_config_byte(dev->pci, PCI_CLASS_REVISION, &dev->pci_rev);
+ dev->pci_rev = dev->pci->revision;
pci_read_config_byte(dev->pci, PCI_LATENCY_TIMER, &dev->pci_lat);
printk(KERN_INFO "%s/2: found at %s, rev: %d, irq: %d, "
"latency: %d, mmio: 0x%llx\n", dev->core->name,
@@ -624,13 +625,11 @@
if (drv->advise_acquire)
{
- mutex_lock(&drv->core->lock);
core->active_ref++;
if (core->active_type_id == CX88_BOARD_NONE) {
core->active_type_id = drv->type_id;
drv->advise_acquire(drv);
}
- mutex_unlock(&drv->core->lock);
mpeg_dbg(1,"%s() Post acquire GPIO=%x\n", __func__, cx_read(MO_GP0_IO));
}
@@ -643,14 +642,12 @@
{
struct cx88_core *core = drv->core;
- mutex_lock(&drv->core->lock);
if (drv->advise_release && --core->active_ref == 0)
{
drv->advise_release(drv);
core->active_type_id = CX88_BOARD_NONE;
mpeg_dbg(1,"%s() Post release GPIO=%x\n", __func__, cx_read(MO_GP0_IO));
}
- mutex_unlock(&drv->core->lock);
return 0;
}
@@ -693,6 +690,8 @@
return err;
}
+ mutex_lock(&cx8802_mutex);
+
list_for_each_entry(dev, &cx8802_devlist, devlist) {
printk(KERN_INFO
"%s/2: subsystem: %04x:%04x, board: %s [card=%d]\n",
@@ -702,8 +701,10 @@
/* Bring up a new struct for each driver instance */
driver = kzalloc(sizeof(*drv),GFP_KERNEL);
- if (driver == NULL)
- return -ENOMEM;
+ if (driver == NULL) {
+ err = -ENOMEM;
+ goto out;
+ }
/* Snapshot of the driver registration data */
drv->core = dev->core;
@@ -713,21 +714,23 @@
drv->request_release = cx8802_request_release;
memcpy(driver, drv, sizeof(*driver));
+ mutex_lock(&drv->core->lock);
err = drv->probe(driver);
if (err == 0) {
i++;
- mutex_lock(&drv->core->lock);
list_add_tail(&driver->drvlist, &dev->drvlist);
- mutex_unlock(&drv->core->lock);
} else {
printk(KERN_ERR
"%s/2: cx8802 probe failed, err = %d\n",
dev->core->name, err);
}
-
+ mutex_unlock(&drv->core->lock);
}
- return i ? 0 : -ENODEV;
+ err = i ? 0 : -ENODEV;
+out:
+ mutex_unlock(&cx8802_mutex);
+ return err;
}
int cx8802_unregister_driver(struct cx8802_driver *drv)
@@ -741,6 +744,8 @@
drv->type_id == CX88_MPEG_DVB ? "dvb" : "blackbird",
drv->hw_access == CX8802_DRVCTL_SHARED ? "shared" : "exclusive");
+ mutex_lock(&cx8802_mutex);
+
list_for_each_entry(dev, &cx8802_devlist, devlist) {
printk(KERN_INFO
"%s/2: subsystem: %04x:%04x, board: %s [card=%d]\n",
@@ -748,6 +753,8 @@
dev->pci->subsystem_device, dev->core->board.name,
dev->core->boardnr);
+ mutex_lock(&dev->core->lock);
+
list_for_each_entry_safe(d, dtmp, &dev->drvlist, drvlist) {
/* only unregister the correct driver type */
if (d->type_id != drv->type_id)
@@ -755,17 +762,18 @@
err = d->remove(d);
if (err == 0) {
- mutex_lock(&drv->core->lock);
list_del(&d->drvlist);
- mutex_unlock(&drv->core->lock);
kfree(d);
} else
printk(KERN_ERR "%s/2: cx8802 driver remove "
"failed (%d)\n", dev->core->name, err);
}
+ mutex_unlock(&dev->core->lock);
}
+ mutex_unlock(&cx8802_mutex);
+
return err;
}
@@ -803,7 +811,9 @@
goto fail_free;
INIT_LIST_HEAD(&dev->drvlist);
+ mutex_lock(&cx8802_mutex);
list_add_tail(&dev->devlist,&cx8802_devlist);
+ mutex_unlock(&cx8802_mutex);
/* now autoload cx88-dvb or cx88-blackbird */
request_modules(dev);
@@ -827,6 +837,8 @@
flush_request_modules(dev);
+ mutex_lock(&dev->core->lock);
+
if (!list_empty(&dev->drvlist)) {
struct cx8802_driver *drv, *tmp;
int err;
@@ -838,9 +850,7 @@
list_for_each_entry_safe(drv, tmp, &dev->drvlist, drvlist) {
err = drv->remove(drv);
if (err == 0) {
- mutex_lock(&drv->core->lock);
list_del(&drv->drvlist);
- mutex_unlock(&drv->core->lock);
} else
printk(KERN_ERR "%s/2: cx8802 driver remove "
"failed (%d)\n", dev->core->name, err);
@@ -848,6 +858,8 @@
}
}
+ mutex_unlock(&dev->core->lock);
+
/* Destroy any 8802 reference. */
dev->core->dvbdev = NULL;
diff --git a/drivers/media/video/cx88/cx88-video.c b/drivers/media/video/cx88/cx88-video.c
index 287a41e..cef4f28 100644
--- a/drivers/media/video/cx88/cx88-video.c
+++ b/drivers/media/video/cx88/cx88-video.c
@@ -824,7 +824,7 @@
call_all(core, tuner, s_radio);
}
- atomic_inc(&core->users);
+ core->users++;
mutex_unlock(&core->lock);
return 0;
@@ -922,7 +922,8 @@
file->private_data = NULL;
kfree(fh);
- if(atomic_dec_and_test(&dev->core->users))
+ dev->core->users--;
+ if (!dev->core->users)
call_all(dev->core, core, s_power, 0);
mutex_unlock(&dev->core->lock);
@@ -1832,7 +1833,7 @@
dev->core = core;
/* print pci info */
- pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &dev->pci_rev);
+ dev->pci_rev = pci_dev->revision;
pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat);
printk(KERN_INFO "%s/0: found at %s, rev: %d, irq: %d, "
"latency: %d, mmio: 0x%llx\n", core->name,
diff --git a/drivers/media/video/cx88/cx88.h b/drivers/media/video/cx88/cx88.h
index 9b3742a..a399a8b 100644
--- a/drivers/media/video/cx88/cx88.h
+++ b/drivers/media/video/cx88/cx88.h
@@ -389,8 +389,8 @@
struct mutex lock;
/* various v4l controls */
u32 freq;
- atomic_t users;
- atomic_t mpeg_users;
+ int users;
+ int mpeg_users;
/* cx88-video needs to access cx8802 for hybrid tuner pll access. */
struct cx8802_dev *dvbdev;
@@ -505,6 +505,8 @@
int (*suspend)(struct pci_dev *pci_dev, pm_message_t state);
int (*resume)(struct pci_dev *pci_dev);
+ /* Callers to the following functions must hold core->lock */
+
/* MPEG 8802 -> mini driver - Driver probe and configuration */
int (*probe)(struct cx8802_driver *drv);
int (*remove)(struct cx8802_driver *drv);
@@ -561,8 +563,9 @@
/* for switching modulation types */
unsigned char ts_gen_cntrl;
- /* List of attached drivers */
+ /* List of attached drivers; must hold core->lock to access */
struct list_head drvlist;
+
struct work_struct request_module_wk;
};
@@ -685,6 +688,8 @@
int cx8802_register_driver(struct cx8802_driver *drv);
int cx8802_unregister_driver(struct cx8802_driver *drv);
+
+/* Caller must hold core->lock */
struct cx8802_driver * cx8802_get_driver(struct cx8802_dev *dev, enum cx88_board_type btype);
/* ----------------------------------------------------------- */
diff --git a/drivers/media/video/em28xx/Kconfig b/drivers/media/video/em28xx/Kconfig
index 985100e..3cb78f2 100644
--- a/drivers/media/video/em28xx/Kconfig
+++ b/drivers/media/video/em28xx/Kconfig
@@ -38,6 +38,8 @@
select DVB_ZL10353 if !DVB_FE_CUSTOMISE
select DVB_TDA10023 if !DVB_FE_CUSTOMISE
select DVB_S921 if !DVB_FE_CUSTOMISE
+ select DVB_DRXD if !DVB_FE_CUSTOMISE
+ select DVB_CXD2820R if !DVB_FE_CUSTOMISE
select VIDEOBUF_DVB
---help---
This adds support for DVB cards based on the
diff --git a/drivers/media/video/em28xx/em28xx-cards.c b/drivers/media/video/em28xx/em28xx-cards.c
index 69fcea8..4e37375 100644
--- a/drivers/media/video/em28xx/em28xx-cards.c
+++ b/drivers/media/video/em28xx/em28xx-cards.c
@@ -100,6 +100,13 @@
{ -1, -1, -1, -1},
};
+/* Board Hauppauge WinTV HVR 900 (R2) digital */
+static struct em28xx_reg_seq hauppauge_wintv_hvr_900R2_digital[] = {
+ {EM28XX_R08_GPIO, 0x2e, ~EM_GPIO_4, 10},
+ {EM2880_R04_GPO, 0x0c, 0x0f, 10},
+ { -1, -1, -1, -1},
+};
+
/* Boards - EM2880 MSI DIGIVOX AD and EM2880_BOARD_MSI_DIGIVOX_AD_II */
static struct em28xx_reg_seq em2880_msi_digivox_ad_analog[] = {
{EM28XX_R08_GPIO, 0x69, ~EM_GPIO_4, 10},
@@ -282,6 +289,16 @@
{ -1, -1, -1, -1},
};
+/* 2013:024f PCTV Systems nanoStick T2 290e
+ * GPIO_6 - demod reset
+ * GPIO_7 - LED
+ */
+static struct em28xx_reg_seq pctv_290e[] = {
+ {EM2874_R80_GPIO, 0x00, 0xff, 80},
+ {EM2874_R80_GPIO, 0x40, 0xff, 80}, /* GPIO_6 = 1 */
+ {EM2874_R80_GPIO, 0xc0, 0xff, 80}, /* GPIO_7 = 1 */
+ {-1, -1, -1, -1},
+};
/*
* Board definitions
@@ -859,6 +876,8 @@
.tuner_type = TUNER_XC2028,
.tuner_gpio = default_tuner_gpio,
.mts_firmware = 1,
+ .has_dvb = 1,
+ .dvb_gpio = hauppauge_wintv_hvr_900R2_digital,
.ir_codes = RC_MAP_HAUPPAUGE,
.decoder = EM28XX_TVP5150,
.input = { {
@@ -1448,12 +1467,14 @@
.gpio = pinnacle_hybrid_pro_analog,
} },
},
- [EM2882_BOARD_PINNACLE_HYBRID_PRO] = {
- .name = "Pinnacle Hybrid Pro (2)",
- .valid = EM28XX_BOARD_NOT_VALIDATED,
+ [EM2882_BOARD_PINNACLE_HYBRID_PRO_330E] = {
+ .name = "Pinnacle Hybrid Pro (330e)",
.tuner_type = TUNER_XC2028,
.tuner_gpio = default_tuner_gpio,
.mts_firmware = 1,
+ .has_dvb = 1,
+ .dvb_gpio = hauppauge_wintv_hvr_900R2_digital,
+ .ir_codes = RC_MAP_PINNACLE_PCTV_HD,
.decoder = EM28XX_TVP5150,
.input = { {
.type = EM28XX_VMUX_TELEVISION,
@@ -1749,6 +1770,17 @@
.dvb_gpio = kworld_a340_digital,
.tuner_gpio = default_tuner_gpio,
},
+ /* 2013:024f PCTV Systems nanoStick T2 290e.
+ * Empia EM28174, Sony CXD2820R and NXP TDA18271HD/C2 */
+ [EM28174_BOARD_PCTV_290E] = {
+ .i2c_speed = EM2874_I2C_SECONDARY_BUS_SELECT |
+ EM28XX_I2C_CLK_WAIT_ENABLE | EM28XX_I2C_FREQ_100_KHZ,
+ .xclk = EM28XX_XCLK_FREQUENCY_12MHZ,
+ .name = "PCTV Systems nanoStick T2 290e",
+ .tuner_type = TUNER_ABSENT,
+ .tuner_gpio = pctv_290e,
+ .has_dvb = 1,
+ },
};
const unsigned int em28xx_bcount = ARRAY_SIZE(em28xx_boards);
@@ -1863,7 +1895,7 @@
{ USB_DEVICE(0x2304, 0x021a),
.driver_info = EM2820_BOARD_PINNACLE_DVC_90 },
{ USB_DEVICE(0x2304, 0x0226),
- .driver_info = EM2882_BOARD_PINNACLE_HYBRID_PRO },
+ .driver_info = EM2882_BOARD_PINNACLE_HYBRID_PRO_330E },
{ USB_DEVICE(0x2304, 0x0227),
.driver_info = EM2880_BOARD_PINNACLE_PCTV_HD_PRO },
{ USB_DEVICE(0x0413, 0x6023),
@@ -1876,6 +1908,8 @@
.driver_info = EM2860_BOARD_GADMEI_UTV330 },
{ USB_DEVICE(0x1b80, 0xa340),
.driver_info = EM2870_BOARD_KWORLD_A340 },
+ { USB_DEVICE(0x2013, 0x024f),
+ .driver_info = EM28174_BOARD_PCTV_290E },
{ },
};
MODULE_DEVICE_TABLE(usb, em28xx_id_table);
@@ -2229,7 +2263,7 @@
ctl->demod = XC3028_FE_ZARLINK456;
break;
case EM2880_BOARD_HAUPPAUGE_WINTV_HVR_900_R2:
- /* djh - Not sure which demod we need here */
+ case EM2882_BOARD_PINNACLE_HYBRID_PRO_330E:
ctl->demod = XC3028_FE_DEFAULT;
break;
case EM2880_BOARD_AMD_ATI_TV_WONDER_HD_600:
@@ -2799,6 +2833,11 @@
dev->reg_gpio_num = EM2874_R80_GPIO;
dev->wait_after_write = 0;
break;
+ case CHIP_ID_EM28174:
+ em28xx_info("chip ID is em28174\n");
+ dev->reg_gpio_num = EM2874_R80_GPIO;
+ dev->wait_after_write = 0;
+ break;
case CHIP_ID_EM2883:
em28xx_info("chip ID is em2882/em2883\n");
dev->wait_after_write = 0;
diff --git a/drivers/media/video/em28xx/em28xx-core.c b/drivers/media/video/em28xx/em28xx-core.c
index 44c63cbd..e33f145 100644
--- a/drivers/media/video/em28xx/em28xx-core.c
+++ b/drivers/media/video/em28xx/em28xx-core.c
@@ -489,7 +489,8 @@
int vid1, vid2, feat, cfg;
u32 vid;
- if (dev->chip_id == CHIP_ID_EM2870 || dev->chip_id == CHIP_ID_EM2874) {
+ if (dev->chip_id == CHIP_ID_EM2870 || dev->chip_id == CHIP_ID_EM2874
+ || dev->chip_id == CHIP_ID_EM28174) {
/* Digital only device - don't load any alsa module */
dev->audio_mode.has_audio = 0;
dev->has_audio_class = 0;
@@ -614,7 +615,7 @@
{
int rc;
- if (dev->chip_id == CHIP_ID_EM2874) {
+ if (dev->chip_id == CHIP_ID_EM2874 || dev->chip_id == CHIP_ID_EM28174) {
/* The Transport Stream Enable Register moved in em2874 */
if (!start) {
rc = em28xx_write_reg_bits(dev, EM2874_R5F_TS_ENABLE,
@@ -1111,6 +1112,10 @@
/* FIXME - for now assume 564 like it was before, but the
em2874 code should be added to return the proper value... */
packet_size = 564;
+ } else if (dev->chip_id == CHIP_ID_EM28174) {
+ /* FIXME same as em2874. 564 was enough for 22 Mbit DVB-T
+ but too much for 44 Mbit DVB-C. */
+ packet_size = 752;
} else {
/* TS max packet size stored in bits 1-0 of R01 */
chip_cfg2 = em28xx_read_reg(dev, EM28XX_R01_CHIPCFG2);
diff --git a/drivers/media/video/em28xx/em28xx-dvb.c b/drivers/media/video/em28xx/em28xx-dvb.c
index c7c04bf..7904ca4 100644
--- a/drivers/media/video/em28xx/em28xx-dvb.c
+++ b/drivers/media/video/em28xx/em28xx-dvb.c
@@ -38,6 +38,8 @@
#include "tda1002x.h"
#include "tda18271.h"
#include "s921.h"
+#include "drxd.h"
+#include "cxd2820r.h"
MODULE_DESCRIPTION("driver for em28xx based DVB cards");
MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@infradead.org>");
@@ -58,7 +60,7 @@
#define EM28XX_DVB_MAX_PACKETS 64
struct em28xx_dvb {
- struct dvb_frontend *frontend;
+ struct dvb_frontend *fe[2];
/* feed count management */
struct mutex lock;
@@ -285,12 +287,13 @@
.if2 = 45600,
};
-#ifdef EM28XX_DRX397XD_SUPPORT
-/* [TODO] djh - not sure yet what the device config needs to contain */
-static struct drx397xD_config em28xx_drx397xD_with_xc3028 = {
- .demod_address = (0xe0 >> 1),
+static struct drxd_config em28xx_drxd = {
+ .index = 0, .demod_address = 0x70, .demod_revision = 0xa2,
+ .demoda_address = 0x00, .pll_address = 0x00,
+ .pll_type = DRXD_PLL_NONE, .clock = 12000, .insert_rs_byte = 1,
+ .pll_set = NULL, .osc_deviation = NULL, .IF = 42800000,
+ .disable_i2c_gate_ctrl = 1,
};
-#endif
static int mt352_terratec_xs_init(struct dvb_frontend *fe)
{
@@ -332,6 +335,26 @@
.invert = 1,
};
+static struct cxd2820r_config em28xx_cxd2820r_config = {
+ .i2c_address = (0xd8 >> 1),
+ .ts_mode = CXD2820R_TS_SERIAL,
+ .if_dvbt_6 = 3300,
+ .if_dvbt_7 = 3500,
+ .if_dvbt_8 = 4000,
+ .if_dvbt2_6 = 3300,
+ .if_dvbt2_7 = 3500,
+ .if_dvbt2_8 = 4000,
+ .if_dvbc = 5000,
+
+ /* enable LNA for DVB-T2 and DVB-C */
+ .gpio_dvbt2[0] = CXD2820R_GPIO_E | CXD2820R_GPIO_O | CXD2820R_GPIO_L,
+ .gpio_dvbc[0] = CXD2820R_GPIO_E | CXD2820R_GPIO_O | CXD2820R_GPIO_L,
+};
+
+static struct tda18271_config em28xx_cxd2820r_tda18271_config = {
+ .output_opt = TDA18271_OUTPUT_LT_OFF,
+};
+
/* ------------------------------------------------------------------ */
static int attach_xc3028(u8 addr, struct em28xx *dev)
@@ -343,17 +366,17 @@
cfg.i2c_adap = &dev->i2c_adap;
cfg.i2c_addr = addr;
- if (!dev->dvb->frontend) {
+ if (!dev->dvb->fe[0]) {
em28xx_errdev("/2: dvb frontend not attached. "
"Can't attach xc3028\n");
return -EINVAL;
}
- fe = dvb_attach(xc2028_attach, dev->dvb->frontend, &cfg);
+ fe = dvb_attach(xc2028_attach, dev->dvb->fe[0], &cfg);
if (!fe) {
em28xx_errdev("/2: xc3028 attach failed\n");
- dvb_frontend_detach(dev->dvb->frontend);
- dev->dvb->frontend = NULL;
+ dvb_frontend_detach(dev->dvb->fe[0]);
+ dev->dvb->fe[0] = NULL;
return -EINVAL;
}
@@ -383,16 +406,28 @@
}
/* Ensure all frontends negotiate bus access */
- dvb->frontend->ops.ts_bus_ctrl = em28xx_dvb_bus_ctrl;
+ dvb->fe[0]->ops.ts_bus_ctrl = em28xx_dvb_bus_ctrl;
+ if (dvb->fe[1])
+ dvb->fe[1]->ops.ts_bus_ctrl = em28xx_dvb_bus_ctrl;
dvb->adapter.priv = dev;
/* register frontend */
- result = dvb_register_frontend(&dvb->adapter, dvb->frontend);
+ result = dvb_register_frontend(&dvb->adapter, dvb->fe[0]);
if (result < 0) {
printk(KERN_WARNING "%s: dvb_register_frontend failed (errno = %d)\n",
dev->name, result);
- goto fail_frontend;
+ goto fail_frontend0;
+ }
+
+ /* register 2nd frontend */
+ if (dvb->fe[1]) {
+ result = dvb_register_frontend(&dvb->adapter, dvb->fe[1]);
+ if (result < 0) {
+ printk(KERN_WARNING "%s: 2nd dvb_register_frontend failed (errno = %d)\n",
+ dev->name, result);
+ goto fail_frontend1;
+ }
}
/* register demux stuff */
@@ -458,9 +493,14 @@
fail_dmxdev:
dvb_dmx_release(&dvb->demux);
fail_dmx:
- dvb_unregister_frontend(dvb->frontend);
-fail_frontend:
- dvb_frontend_detach(dvb->frontend);
+ if (dvb->fe[1])
+ dvb_unregister_frontend(dvb->fe[1]);
+ dvb_unregister_frontend(dvb->fe[0]);
+fail_frontend1:
+ if (dvb->fe[1])
+ dvb_frontend_detach(dvb->fe[1]);
+fail_frontend0:
+ dvb_frontend_detach(dvb->fe[0]);
dvb_unregister_adapter(&dvb->adapter);
fail_adapter:
return result;
@@ -473,12 +513,15 @@
dvb->demux.dmx.remove_frontend(&dvb->demux.dmx, &dvb->fe_hw);
dvb_dmxdev_release(&dvb->dmxdev);
dvb_dmx_release(&dvb->demux);
- dvb_unregister_frontend(dvb->frontend);
- dvb_frontend_detach(dvb->frontend);
+ if (dvb->fe[1])
+ dvb_unregister_frontend(dvb->fe[1]);
+ dvb_unregister_frontend(dvb->fe[0]);
+ if (dvb->fe[1])
+ dvb_frontend_detach(dvb->fe[1]);
+ dvb_frontend_detach(dvb->fe[0]);
dvb_unregister_adapter(&dvb->adapter);
}
-
static int dvb_init(struct em28xx *dev)
{
int result = 0;
@@ -497,16 +540,17 @@
return -ENOMEM;
}
dev->dvb = dvb;
+ dvb->fe[0] = dvb->fe[1] = NULL;
mutex_lock(&dev->lock);
em28xx_set_mode(dev, EM28XX_DIGITAL_MODE);
/* init frontend */
switch (dev->model) {
case EM2874_LEADERSHIP_ISDBT:
- dvb->frontend = dvb_attach(s921_attach,
+ dvb->fe[0] = dvb_attach(s921_attach,
&sharp_isdbt, &dev->i2c_adap);
- if (!dvb->frontend) {
+ if (!dvb->fe[0]) {
result = -EINVAL;
goto out_free;
}
@@ -516,7 +560,7 @@
case EM2883_BOARD_HAUPPAUGE_WINTV_HVR_950:
case EM2880_BOARD_PINNACLE_PCTV_HD_PRO:
case EM2880_BOARD_AMD_ATI_TV_WONDER_HD_600:
- dvb->frontend = dvb_attach(lgdt330x_attach,
+ dvb->fe[0] = dvb_attach(lgdt330x_attach,
&em2880_lgdt3303_dev,
&dev->i2c_adap);
if (attach_xc3028(0x61, dev) < 0) {
@@ -525,7 +569,7 @@
}
break;
case EM2880_BOARD_KWORLD_DVB_310U:
- dvb->frontend = dvb_attach(zl10353_attach,
+ dvb->fe[0] = dvb_attach(zl10353_attach,
&em28xx_zl10353_with_xc3028,
&dev->i2c_adap);
if (attach_xc3028(0x61, dev) < 0) {
@@ -536,7 +580,7 @@
case EM2880_BOARD_HAUPPAUGE_WINTV_HVR_900:
case EM2882_BOARD_TERRATEC_HYBRID_XS:
case EM2880_BOARD_EMPIRE_DUAL_TV:
- dvb->frontend = dvb_attach(zl10353_attach,
+ dvb->fe[0] = dvb_attach(zl10353_attach,
&em28xx_zl10353_xc3028_no_i2c_gate,
&dev->i2c_adap);
if (attach_xc3028(0x61, dev) < 0) {
@@ -549,13 +593,13 @@
case EM2881_BOARD_PINNACLE_HYBRID_PRO:
case EM2882_BOARD_DIKOM_DK300:
case EM2882_BOARD_KWORLD_VS_DVBT:
- dvb->frontend = dvb_attach(zl10353_attach,
+ dvb->fe[0] = dvb_attach(zl10353_attach,
&em28xx_zl10353_xc3028_no_i2c_gate,
&dev->i2c_adap);
- if (dvb->frontend == NULL) {
+ if (dvb->fe[0] == NULL) {
/* This board could have either a zl10353 or a mt352.
If the chip id isn't for zl10353, try mt352 */
- dvb->frontend = dvb_attach(mt352_attach,
+ dvb->fe[0] = dvb_attach(mt352_attach,
&terratec_xs_mt352_cfg,
&dev->i2c_adap);
}
@@ -567,7 +611,7 @@
break;
case EM2883_BOARD_KWORLD_HYBRID_330U:
case EM2882_BOARD_EVGA_INDTUBE:
- dvb->frontend = dvb_attach(s5h1409_attach,
+ dvb->fe[0] = dvb_attach(s5h1409_attach,
&em28xx_s5h1409_with_xc3028,
&dev->i2c_adap);
if (attach_xc3028(0x61, dev) < 0) {
@@ -576,11 +620,11 @@
}
break;
case EM2882_BOARD_KWORLD_ATSC_315U:
- dvb->frontend = dvb_attach(lgdt330x_attach,
+ dvb->fe[0] = dvb_attach(lgdt330x_attach,
&em2880_lgdt3303_dev,
&dev->i2c_adap);
- if (dvb->frontend != NULL) {
- if (!dvb_attach(simple_tuner_attach, dvb->frontend,
+ if (dvb->fe[0] != NULL) {
+ if (!dvb_attach(simple_tuner_attach, dvb->fe[0],
&dev->i2c_adap, 0x61, TUNER_THOMSON_DTT761X)) {
result = -EINVAL;
goto out_free;
@@ -588,25 +632,21 @@
}
break;
case EM2880_BOARD_HAUPPAUGE_WINTV_HVR_900_R2:
-#ifdef EM28XX_DRX397XD_SUPPORT
- /* We don't have the config structure properly populated, so
- this is commented out for now */
- dvb->frontend = dvb_attach(drx397xD_attach,
- &em28xx_drx397xD_with_xc3028,
- &dev->i2c_adap);
+ case EM2882_BOARD_PINNACLE_HYBRID_PRO_330E:
+ dvb->fe[0] = dvb_attach(drxd_attach, &em28xx_drxd, NULL,
+ &dev->i2c_adap, &dev->udev->dev);
if (attach_xc3028(0x61, dev) < 0) {
result = -EINVAL;
goto out_free;
}
break;
-#endif
case EM2870_BOARD_REDDO_DVB_C_USB_BOX:
/* Philips CU1216L NIM (Philips TDA10023 + Infineon TUA6034) */
- dvb->frontend = dvb_attach(tda10023_attach,
+ dvb->fe[0] = dvb_attach(tda10023_attach,
&em28xx_tda10023_config,
&dev->i2c_adap, 0x48);
- if (dvb->frontend) {
- if (!dvb_attach(simple_tuner_attach, dvb->frontend,
+ if (dvb->fe[0]) {
+ if (!dvb_attach(simple_tuner_attach, dvb->fe[0],
&dev->i2c_adap, 0x60, TUNER_PHILIPS_CU1216L)) {
result = -EINVAL;
goto out_free;
@@ -614,25 +654,53 @@
}
break;
case EM2870_BOARD_KWORLD_A340:
- dvb->frontend = dvb_attach(lgdt3305_attach,
+ dvb->fe[0] = dvb_attach(lgdt3305_attach,
&em2870_lgdt3304_dev,
&dev->i2c_adap);
- if (dvb->frontend != NULL)
- dvb_attach(tda18271_attach, dvb->frontend, 0x60,
+ if (dvb->fe[0] != NULL)
+ dvb_attach(tda18271_attach, dvb->fe[0], 0x60,
&dev->i2c_adap, &kworld_a340_config);
break;
+ case EM28174_BOARD_PCTV_290E:
+ /* MFE
+ * FE 0 = DVB-T/T2 + FE 1 = DVB-C, both sharing same tuner. */
+ /* FE 0 */
+ dvb->fe[0] = dvb_attach(cxd2820r_attach,
+ &em28xx_cxd2820r_config, &dev->i2c_adap, NULL);
+ if (dvb->fe[0]) {
+ struct i2c_adapter *i2c_tuner;
+ i2c_tuner = cxd2820r_get_tuner_i2c_adapter(dvb->fe[0]);
+ /* FE 0 attach tuner */
+ if (!dvb_attach(tda18271_attach, dvb->fe[0], 0x60,
+ i2c_tuner, &em28xx_cxd2820r_tda18271_config)) {
+ dvb_frontend_detach(dvb->fe[0]);
+ result = -EINVAL;
+ goto out_free;
+ }
+ /* FE 1. This dvb_attach() cannot fail. */
+ dvb->fe[1] = dvb_attach(cxd2820r_attach, NULL, NULL,
+ dvb->fe[0]);
+ dvb->fe[1]->id = 1;
+ /* FE 1 attach tuner */
+ if (!dvb_attach(tda18271_attach, dvb->fe[1], 0x60,
+ i2c_tuner, &em28xx_cxd2820r_tda18271_config)) {
+ dvb_frontend_detach(dvb->fe[1]);
+ /* leave FE 0 still active */
+ }
+ }
+ break;
default:
em28xx_errdev("/2: The frontend of your DVB/ATSC card"
" isn't supported yet\n");
break;
}
- if (NULL == dvb->frontend) {
+ if (NULL == dvb->fe[0]) {
em28xx_errdev("/2: frontend initialization failed\n");
result = -EINVAL;
goto out_free;
}
/* define general-purpose callback pointer */
- dvb->frontend->callback = em28xx_tuner_callback;
+ dvb->fe[0]->callback = em28xx_tuner_callback;
/* register everything */
result = register_dvb(dvb, THIS_MODULE, dev, &dev->udev->dev);
diff --git a/drivers/media/video/em28xx/em28xx-i2c.c b/drivers/media/video/em28xx/em28xx-i2c.c
index 71474d3..4739fc7 100644
--- a/drivers/media/video/em28xx/em28xx-i2c.c
+++ b/drivers/media/video/em28xx/em28xx-i2c.c
@@ -332,7 +332,7 @@
struct em28xx_eeprom *em_eeprom = (void *)eedata;
int i, err, size = len, block;
- if (dev->chip_id == CHIP_ID_EM2874) {
+ if (dev->chip_id == CHIP_ID_EM2874 || dev->chip_id == CHIP_ID_EM28174) {
/* Empia switched to a 16-bit addressable eeprom in newer
devices. While we could certainly write a routine to read
the eeprom, there is nothing of use in there that cannot be
diff --git a/drivers/media/video/em28xx/em28xx-reg.h b/drivers/media/video/em28xx/em28xx-reg.h
index 91e9055..e92a28e 100644
--- a/drivers/media/video/em28xx/em28xx-reg.h
+++ b/drivers/media/video/em28xx/em28xx-reg.h
@@ -201,6 +201,7 @@
CHIP_ID_EM2870 = 35,
CHIP_ID_EM2883 = 36,
CHIP_ID_EM2874 = 65,
+ CHIP_ID_EM28174 = 113,
};
/*
diff --git a/drivers/media/video/em28xx/em28xx.h b/drivers/media/video/em28xx/em28xx.h
index 6f2795a..3cca331 100644
--- a/drivers/media/video/em28xx/em28xx.h
+++ b/drivers/media/video/em28xx/em28xx.h
@@ -97,7 +97,7 @@
#define EM2881_BOARD_PINNACLE_HYBRID_PRO 53
#define EM2882_BOARD_KWORLD_VS_DVBT 54
#define EM2882_BOARD_TERRATEC_HYBRID_XS 55
-#define EM2882_BOARD_PINNACLE_HYBRID_PRO 56
+#define EM2882_BOARD_PINNACLE_HYBRID_PRO_330E 56
#define EM2883_BOARD_KWORLD_HYBRID_330U 57
#define EM2820_BOARD_COMPRO_VIDEOMATE_FORYOU 58
#define EM2883_BOARD_HAUPPAUGE_WINTV_HVR_850 60
@@ -118,6 +118,7 @@
#define EM2882_BOARD_DIKOM_DK300 75
#define EM2870_BOARD_KWORLD_A340 76
#define EM2874_LEADERSHIP_ISDBT 77
+#define EM28174_BOARD_PCTV_290E 78
/* Limits minimum and default number of buffers */
diff --git a/drivers/media/video/fsl-viu.c b/drivers/media/video/fsl-viu.c
index 031af161..908d701 100644
--- a/drivers/media/video/fsl-viu.c
+++ b/drivers/media/video/fsl-viu.c
@@ -766,7 +766,7 @@
out_be32(&vr->picture_count, reg_val.picture_count);
}
-static int viu_start_preview(struct viu_dev *dev, struct viu_fh *fh)
+static int viu_setup_preview(struct viu_dev *dev, struct viu_fh *fh)
{
int bpp;
@@ -805,11 +805,6 @@
/* setup the base address of the overlay buffer */
reg_val.field_base_addr = (u32)dev->ovbuf.base;
- dev->ovenable = 1;
- viu_activate_overlay(dev->vr);
-
- /* start dma */
- viu_start_dma(dev);
return 0;
}
@@ -825,13 +820,11 @@
if (err)
return err;
- mutex_lock(&dev->lock);
fh->win = f->fmt.win;
spin_lock_irqsave(&dev->slock, flags);
- viu_start_preview(dev, fh);
+ viu_setup_preview(dev, fh);
spin_unlock_irqrestore(&dev->slock, flags);
- mutex_unlock(&dev->lock);
return 0;
}
@@ -841,6 +834,28 @@
return 0;
}
+static int vidioc_overlay(struct file *file, void *priv, unsigned int on)
+{
+ struct viu_fh *fh = priv;
+ struct viu_dev *dev = (struct viu_dev *)fh->dev;
+ unsigned long flags;
+
+ if (on) {
+ spin_lock_irqsave(&dev->slock, flags);
+ viu_activate_overlay(dev->vr);
+ dev->ovenable = 1;
+
+ /* start dma */
+ viu_start_dma(dev);
+ spin_unlock_irqrestore(&dev->slock, flags);
+ } else {
+ viu_stop_dma(dev);
+ dev->ovenable = 0;
+ }
+
+ return 0;
+}
+
int vidioc_g_fbuf(struct file *file, void *priv, struct v4l2_framebuffer *arg)
{
struct viu_fh *fh = priv;
@@ -911,12 +926,16 @@
static int vidioc_streamon(struct file *file, void *priv, enum v4l2_buf_type i)
{
struct viu_fh *fh = priv;
+ struct viu_dev *dev = fh->dev;
if (fh->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
return -EINVAL;
if (fh->type != i)
return -EINVAL;
+ if (dev->ovenable)
+ dev->ovenable = 0;
+
viu_start_dma(fh->dev);
return videobuf_streamon(&fh->vb_vidq);
@@ -1311,7 +1330,8 @@
videobuf_queue_dma_contig_init(&fh->vb_vidq, &viu_video_qops,
dev->dev, &fh->vbq_lock,
fh->type, V4L2_FIELD_INTERLACED,
- sizeof(struct viu_buf), fh, NULL);
+ sizeof(struct viu_buf), fh,
+ &fh->dev->lock);
return 0;
}
@@ -1401,7 +1421,7 @@
.release = viu_release,
.read = viu_read,
.poll = viu_poll,
- .ioctl = video_ioctl2, /* V4L2 ioctl handler */
+ .unlocked_ioctl = video_ioctl2, /* V4L2 ioctl handler */
.mmap = viu_mmap,
};
@@ -1415,6 +1435,7 @@
.vidioc_g_fmt_vid_overlay = vidioc_g_fmt_overlay,
.vidioc_try_fmt_vid_overlay = vidioc_try_fmt_overlay,
.vidioc_s_fmt_vid_overlay = vidioc_s_fmt_overlay,
+ .vidioc_overlay = vidioc_overlay,
.vidioc_g_fbuf = vidioc_g_fbuf,
.vidioc_s_fbuf = vidioc_s_fbuf,
.vidioc_reqbufs = vidioc_reqbufs,
@@ -1498,9 +1519,6 @@
INIT_LIST_HEAD(&viu_dev->vidq.active);
INIT_LIST_HEAD(&viu_dev->vidq.queued);
- /* initialize locks */
- mutex_init(&viu_dev->lock);
-
snprintf(viu_dev->v4l2_dev.name,
sizeof(viu_dev->v4l2_dev.name), "%s", "VIU");
ret = v4l2_device_register(viu_dev->dev, &viu_dev->v4l2_dev);
@@ -1531,8 +1549,15 @@
viu_dev->vdev = vdev;
+ /* initialize locks */
+ mutex_init(&viu_dev->lock);
+ viu_dev->vdev->lock = &viu_dev->lock;
+ spin_lock_init(&viu_dev->slock);
+
video_set_drvdata(viu_dev->vdev, viu_dev);
+ mutex_lock(&viu_dev->lock);
+
ret = video_register_device(viu_dev->vdev, VFL_TYPE_GRABBER, -1);
if (ret < 0) {
video_device_release(viu_dev->vdev);
@@ -1559,6 +1584,8 @@
goto err_irq;
}
+ mutex_unlock(&viu_dev->lock);
+
dev_info(&op->dev, "Freescale VIU Video Capture Board\n");
return ret;
@@ -1568,6 +1595,7 @@
err_clk:
video_unregister_device(viu_dev->vdev);
err_vdev:
+ mutex_unlock(&viu_dev->lock);
i2c_put_adapter(ad);
v4l2_device_unregister(&viu_dev->v4l2_dev);
err:
diff --git a/drivers/media/video/gspca/Kconfig b/drivers/media/video/gspca/Kconfig
index eb04e8b..34ae2c2 100644
--- a/drivers/media/video/gspca/Kconfig
+++ b/drivers/media/video/gspca/Kconfig
@@ -77,6 +77,15 @@
To compile this driver as a module, choose M here: the
module will be called gspca_jeilinj.
+config USB_GSPCA_KINECT
+ tristate "Kinect sensor device USB Camera Driver"
+ depends on VIDEO_V4L2 && USB_GSPCA
+ help
+ Say Y here if you want support for the Microsoft Kinect sensor device.
+
+ To compile this driver as a module, choose M here: the
+ module will be called gspca_kinect.
+
config USB_GSPCA_KONICA
tristate "Konica USB Camera V4L2 driver"
depends on VIDEO_V4L2 && USB_GSPCA
diff --git a/drivers/media/video/gspca/Makefile b/drivers/media/video/gspca/Makefile
index 855fbc8..802fbe1 100644
--- a/drivers/media/video/gspca/Makefile
+++ b/drivers/media/video/gspca/Makefile
@@ -5,6 +5,7 @@
obj-$(CONFIG_USB_GSPCA_ETOMS) += gspca_etoms.o
obj-$(CONFIG_USB_GSPCA_FINEPIX) += gspca_finepix.o
obj-$(CONFIG_USB_GSPCA_JEILINJ) += gspca_jeilinj.o
+obj-$(CONFIG_USB_GSPCA_KINECT) += gspca_kinect.o
obj-$(CONFIG_USB_GSPCA_KONICA) += gspca_konica.o
obj-$(CONFIG_USB_GSPCA_MARS) += gspca_mars.o
obj-$(CONFIG_USB_GSPCA_MR97310A) += gspca_mr97310a.o
@@ -46,6 +47,7 @@
gspca_etoms-objs := etoms.o
gspca_finepix-objs := finepix.o
gspca_jeilinj-objs := jeilinj.o
+gspca_kinect-objs := kinect.o
gspca_konica-objs := konica.o
gspca_mars-objs := mars.o
gspca_mr97310a-objs := mr97310a.o
diff --git a/drivers/media/video/gspca/cpia1.c b/drivers/media/video/gspca/cpia1.c
index 9ddbac6..f2a9451 100644
--- a/drivers/media/video/gspca/cpia1.c
+++ b/drivers/media/video/gspca/cpia1.c
@@ -1262,7 +1262,7 @@
static void monitor_exposure(struct gspca_dev *gspca_dev)
{
struct sd *sd = (struct sd *) gspca_dev;
- u8 exp_acc, bcomp, gain, coarseL, cmd[8];
+ u8 exp_acc, bcomp, cmd[8];
int ret, light_exp, dark_exp, very_dark_exp;
int old_exposure, new_exposure, framerate;
int setfps = 0, setexp = 0, setflicker = 0;
@@ -1284,8 +1284,6 @@
}
exp_acc = gspca_dev->usb_buf[0];
bcomp = gspca_dev->usb_buf[1];
- gain = gspca_dev->usb_buf[2];
- coarseL = gspca_dev->usb_buf[3];
light_exp = sd->params.colourParams.brightness +
TC - 50 + EXP_ACC_LIGHT;
@@ -1772,9 +1770,7 @@
/* this function is called at probe and resume time */
static int sd_init(struct gspca_dev *gspca_dev)
{
-#ifdef GSPCA_DEBUG
struct sd *sd = (struct sd *) gspca_dev;
-#endif
int ret;
/* Start / Stop the camera to make sure we are talking to
diff --git a/drivers/media/video/gspca/gl860/gl860.c b/drivers/media/video/gspca/gl860/gl860.c
index 9908303..e8e071a 100644
--- a/drivers/media/video/gspca/gl860/gl860.c
+++ b/drivers/media/video/gspca/gl860/gl860.c
@@ -499,21 +499,8 @@
static int sd_probe(struct usb_interface *intf,
const struct usb_device_id *id)
{
- struct gspca_dev *gspca_dev;
- s32 ret;
-
- ret = gspca_dev_probe(intf, id,
+ return gspca_dev_probe(intf, id,
&sd_desc_mi1320, sizeof(struct sd), THIS_MODULE);
-
- if (ret >= 0) {
- gspca_dev = usb_get_intfdata(intf);
-
- PDEBUG(D_PROBE,
- "Camera is now controlling video device %s",
- video_device_node_name(&gspca_dev->vdev));
- }
-
- return ret;
}
static void sd_disconnect(struct usb_interface *intf)
diff --git a/drivers/media/video/gspca/gspca.c b/drivers/media/video/gspca/gspca.c
index e526aa3..08ce994 100644
--- a/drivers/media/video/gspca/gspca.c
+++ b/drivers/media/video/gspca/gspca.c
@@ -55,7 +55,7 @@
MODULE_DESCRIPTION("GSPCA USB Camera Driver");
MODULE_LICENSE("GPL");
-#define DRIVER_VERSION_NUMBER KERNEL_VERSION(2, 12, 0)
+#define DRIVER_VERSION_NUMBER KERNEL_VERSION(2, 13, 0)
#ifdef GSPCA_DEBUG
int gspca_debug = D_ERR | D_PROBE;
@@ -2495,6 +2495,6 @@
module_param_named(debug, gspca_debug, int, 0644);
MODULE_PARM_DESC(debug,
"Debug (bit) 0x01:error 0x02:probe 0x04:config"
- " 0x08:stream 0x10:frame 0x20:packet 0x40:USBin 0x80:USBout"
+ " 0x08:stream 0x10:frame 0x20:packet"
" 0x0100: v4l2");
#endif
diff --git a/drivers/media/video/gspca/gspca.h b/drivers/media/video/gspca/gspca.h
index 4175522..49e2fcb 100644
--- a/drivers/media/video/gspca/gspca.h
+++ b/drivers/media/video/gspca/gspca.h
@@ -9,7 +9,7 @@
#include <linux/mutex.h>
/* compilation option */
-#define GSPCA_DEBUG 1
+/*#define GSPCA_DEBUG 1*/
#ifdef GSPCA_DEBUG
/* GSPCA our debug messages */
@@ -25,8 +25,8 @@
#define D_STREAM 0x08
#define D_FRAM 0x10
#define D_PACK 0x20
-#define D_USBI 0x40
-#define D_USBO 0x80
+#define D_USBI 0x00
+#define D_USBO 0x00
#define D_V4L2 0x0100
#else
#define PDEBUG(level, fmt, args...)
diff --git a/drivers/media/video/gspca/jeilinj.c b/drivers/media/video/gspca/jeilinj.c
index 36dae38..1bd9c4b 100644
--- a/drivers/media/video/gspca/jeilinj.c
+++ b/drivers/media/video/gspca/jeilinj.c
@@ -6,6 +6,9 @@
*
* Copyright (C) 2009 Theodore Kilgore
*
+ * Sportscam DV15 support and control settings are
+ * Copyright (C) 2011 Patrice Chotard
+ *
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
@@ -23,7 +26,6 @@
#define MODULE_NAME "jeilinj"
-#include <linux/workqueue.h>
#include <linux/slab.h>
#include "gspca.h"
#include "jpeg.h"
@@ -34,29 +36,51 @@
/* Default timeouts, in ms */
#define JEILINJ_CMD_TIMEOUT 500
+#define JEILINJ_CMD_DELAY 160
#define JEILINJ_DATA_TIMEOUT 1000
/* Maximum transfer size to use. */
#define JEILINJ_MAX_TRANSFER 0x200
-
#define FRAME_HEADER_LEN 0x10
+#define FRAME_START 0xFFFFFFFF
+
+enum {
+ SAKAR_57379,
+ SPORTSCAM_DV15,
+};
+
+#define CAMQUALITY_MIN 0 /* highest cam quality */
+#define CAMQUALITY_MAX 97 /* lowest cam quality */
+
+enum e_ctrl {
+ LIGHTFREQ,
+ AUTOGAIN,
+ RED,
+ GREEN,
+ BLUE,
+ NCTRLS /* number of controls */
+};
/* Structure to hold all of our device specific stuff */
struct sd {
struct gspca_dev gspca_dev; /* !! must be the first item */
+ struct gspca_ctrl ctrls[NCTRLS];
+ int blocks_left;
const struct v4l2_pix_format *cap_mode;
/* Driver stuff */
- struct work_struct work_struct;
- struct workqueue_struct *work_thread;
+ u8 type;
u8 quality; /* image quality */
- u8 jpegqual; /* webcam quality */
+#define QUALITY_MIN 35
+#define QUALITY_MAX 85
+#define QUALITY_DEF 85
u8 jpeg_hdr[JPEG_HDR_SZ];
};
- struct jlj_command {
- unsigned char instruction[2];
- unsigned char ack_wanted;
- };
+struct jlj_command {
+ unsigned char instruction[2];
+ unsigned char ack_wanted;
+ unsigned char delay;
+};
/* AFAICT these cameras will only do 320x240. */
static struct v4l2_pix_format jlj_mode[] = {
@@ -64,6 +88,11 @@
.bytesperline = 320,
.sizeimage = 320 * 240,
.colorspace = V4L2_COLORSPACE_JPEG,
+ .priv = 0},
+ { 640, 480, V4L2_PIX_FMT_JPEG, V4L2_FIELD_NONE,
+ .bytesperline = 640,
+ .sizeimage = 640 * 480,
+ .colorspace = V4L2_COLORSPACE_JPEG,
.priv = 0}
};
@@ -73,178 +102,295 @@
*/
/* All commands are two bytes only */
-static int jlj_write2(struct gspca_dev *gspca_dev, unsigned char *command)
+static void jlj_write2(struct gspca_dev *gspca_dev, unsigned char *command)
{
int retval;
+ if (gspca_dev->usb_err < 0)
+ return;
memcpy(gspca_dev->usb_buf, command, 2);
retval = usb_bulk_msg(gspca_dev->dev,
usb_sndbulkpipe(gspca_dev->dev, 3),
gspca_dev->usb_buf, 2, NULL, 500);
- if (retval < 0)
+ if (retval < 0) {
err("command write [%02x] error %d",
gspca_dev->usb_buf[0], retval);
- return retval;
+ gspca_dev->usb_err = retval;
+ }
}
/* Responses are one byte only */
-static int jlj_read1(struct gspca_dev *gspca_dev, unsigned char response)
+static void jlj_read1(struct gspca_dev *gspca_dev, unsigned char response)
{
int retval;
+ if (gspca_dev->usb_err < 0)
+ return;
retval = usb_bulk_msg(gspca_dev->dev,
usb_rcvbulkpipe(gspca_dev->dev, 0x84),
gspca_dev->usb_buf, 1, NULL, 500);
response = gspca_dev->usb_buf[0];
- if (retval < 0)
+ if (retval < 0) {
err("read command [%02x] error %d",
gspca_dev->usb_buf[0], retval);
- return retval;
+ gspca_dev->usb_err = retval;
+ }
}
+static void setfreq(struct gspca_dev *gspca_dev)
+{
+ struct sd *sd = (struct sd *) gspca_dev;
+ u8 freq_commands[][2] = {
+ {0x71, 0x80},
+ {0x70, 0x07}
+ };
+
+ freq_commands[0][1] |= (sd->ctrls[LIGHTFREQ].val >> 1);
+
+ jlj_write2(gspca_dev, freq_commands[0]);
+ jlj_write2(gspca_dev, freq_commands[1]);
+}
+
+static void setcamquality(struct gspca_dev *gspca_dev)
+{
+ struct sd *sd = (struct sd *) gspca_dev;
+ u8 quality_commands[][2] = {
+ {0x71, 0x1E},
+ {0x70, 0x06}
+ };
+ u8 camquality;
+
+ /* adapt camera quality from jpeg quality */
+ camquality = ((QUALITY_MAX - sd->quality) * CAMQUALITY_MAX)
+ / (QUALITY_MAX - QUALITY_MIN);
+ quality_commands[0][1] += camquality;
+
+ jlj_write2(gspca_dev, quality_commands[0]);
+ jlj_write2(gspca_dev, quality_commands[1]);
+}
+
+static void setautogain(struct gspca_dev *gspca_dev)
+{
+ struct sd *sd = (struct sd *) gspca_dev;
+ u8 autogain_commands[][2] = {
+ {0x94, 0x02},
+ {0xcf, 0x00}
+ };
+
+ autogain_commands[1][1] = (sd->ctrls[AUTOGAIN].val << 4);
+
+ jlj_write2(gspca_dev, autogain_commands[0]);
+ jlj_write2(gspca_dev, autogain_commands[1]);
+}
+
+static void setred(struct gspca_dev *gspca_dev)
+{
+ struct sd *sd = (struct sd *) gspca_dev;
+ u8 setred_commands[][2] = {
+ {0x94, 0x02},
+ {0xe6, 0x00}
+ };
+
+ setred_commands[1][1] = sd->ctrls[RED].val;
+
+ jlj_write2(gspca_dev, setred_commands[0]);
+ jlj_write2(gspca_dev, setred_commands[1]);
+}
+
+static void setgreen(struct gspca_dev *gspca_dev)
+{
+ struct sd *sd = (struct sd *) gspca_dev;
+ u8 setgreen_commands[][2] = {
+ {0x94, 0x02},
+ {0xe7, 0x00}
+ };
+
+ setgreen_commands[1][1] = sd->ctrls[GREEN].val;
+
+ jlj_write2(gspca_dev, setgreen_commands[0]);
+ jlj_write2(gspca_dev, setgreen_commands[1]);
+}
+
+static void setblue(struct gspca_dev *gspca_dev)
+{
+ struct sd *sd = (struct sd *) gspca_dev;
+ u8 setblue_commands[][2] = {
+ {0x94, 0x02},
+ {0xe9, 0x00}
+ };
+
+ setblue_commands[1][1] = sd->ctrls[BLUE].val;
+
+ jlj_write2(gspca_dev, setblue_commands[0]);
+ jlj_write2(gspca_dev, setblue_commands[1]);
+}
+
+static const struct ctrl sd_ctrls[NCTRLS] = {
+[LIGHTFREQ] = {
+ {
+ .id = V4L2_CID_POWER_LINE_FREQUENCY,
+ .type = V4L2_CTRL_TYPE_MENU,
+ .name = "Light frequency filter",
+ .minimum = V4L2_CID_POWER_LINE_FREQUENCY_DISABLED, /* 1 */
+ .maximum = V4L2_CID_POWER_LINE_FREQUENCY_60HZ, /* 2 */
+ .step = 1,
+ .default_value = V4L2_CID_POWER_LINE_FREQUENCY_60HZ,
+ },
+ .set_control = setfreq
+ },
+[AUTOGAIN] = {
+ {
+ .id = V4L2_CID_AUTOGAIN,
+ .type = V4L2_CTRL_TYPE_INTEGER,
+ .name = "Automatic Gain (and Exposure)",
+ .minimum = 0,
+ .maximum = 3,
+ .step = 1,
+#define AUTOGAIN_DEF 0
+ .default_value = AUTOGAIN_DEF,
+ },
+ .set_control = setautogain
+ },
+[RED] = {
+ {
+ .id = V4L2_CID_RED_BALANCE,
+ .type = V4L2_CTRL_TYPE_INTEGER,
+ .name = "red balance",
+ .minimum = 0,
+ .maximum = 3,
+ .step = 1,
+#define RED_BALANCE_DEF 2
+ .default_value = RED_BALANCE_DEF,
+ },
+ .set_control = setred
+ },
+
+[GREEN] = {
+ {
+ .id = V4L2_CID_GAIN,
+ .type = V4L2_CTRL_TYPE_INTEGER,
+ .name = "green balance",
+ .minimum = 0,
+ .maximum = 3,
+ .step = 1,
+#define GREEN_BALANCE_DEF 2
+ .default_value = GREEN_BALANCE_DEF,
+ },
+ .set_control = setgreen
+ },
+[BLUE] = {
+ {
+ .id = V4L2_CID_BLUE_BALANCE,
+ .type = V4L2_CTRL_TYPE_INTEGER,
+ .name = "blue balance",
+ .minimum = 0,
+ .maximum = 3,
+ .step = 1,
+#define BLUE_BALANCE_DEF 2
+ .default_value = BLUE_BALANCE_DEF,
+ },
+ .set_control = setblue
+ },
+};
+
static int jlj_start(struct gspca_dev *gspca_dev)
{
int i;
- int retval = -1;
+ int start_commands_size;
u8 response = 0xff;
+ struct sd *sd = (struct sd *) gspca_dev;
struct jlj_command start_commands[] = {
- {{0x71, 0x81}, 0},
- {{0x70, 0x05}, 0},
- {{0x95, 0x70}, 1},
- {{0x71, 0x81}, 0},
- {{0x70, 0x04}, 0},
- {{0x95, 0x70}, 1},
- {{0x71, 0x00}, 0},
- {{0x70, 0x08}, 0},
- {{0x95, 0x70}, 1},
- {{0x94, 0x02}, 0},
- {{0xde, 0x24}, 0},
- {{0x94, 0x02}, 0},
- {{0xdd, 0xf0}, 0},
- {{0x94, 0x02}, 0},
- {{0xe3, 0x2c}, 0},
- {{0x94, 0x02}, 0},
- {{0xe4, 0x00}, 0},
- {{0x94, 0x02}, 0},
- {{0xe5, 0x00}, 0},
- {{0x94, 0x02}, 0},
- {{0xe6, 0x2c}, 0},
- {{0x94, 0x03}, 0},
- {{0xaa, 0x00}, 0},
- {{0x71, 0x1e}, 0},
- {{0x70, 0x06}, 0},
- {{0x71, 0x80}, 0},
- {{0x70, 0x07}, 0}
+ {{0x71, 0x81}, 0, 0},
+ {{0x70, 0x05}, 0, JEILINJ_CMD_DELAY},
+ {{0x95, 0x70}, 1, 0},
+ {{0x71, 0x81 - gspca_dev->curr_mode}, 0, 0},
+ {{0x70, 0x04}, 0, JEILINJ_CMD_DELAY},
+ {{0x95, 0x70}, 1, 0},
+ {{0x71, 0x00}, 0, 0}, /* start streaming ??*/
+ {{0x70, 0x08}, 0, JEILINJ_CMD_DELAY},
+ {{0x95, 0x70}, 1, 0},
+#define SPORTSCAM_DV15_CMD_SIZE 9
+ {{0x94, 0x02}, 0, 0},
+ {{0xde, 0x24}, 0, 0},
+ {{0x94, 0x02}, 0, 0},
+ {{0xdd, 0xf0}, 0, 0},
+ {{0x94, 0x02}, 0, 0},
+ {{0xe3, 0x2c}, 0, 0},
+ {{0x94, 0x02}, 0, 0},
+ {{0xe4, 0x00}, 0, 0},
+ {{0x94, 0x02}, 0, 0},
+ {{0xe5, 0x00}, 0, 0},
+ {{0x94, 0x02}, 0, 0},
+ {{0xe6, 0x2c}, 0, 0},
+ {{0x94, 0x03}, 0, 0},
+ {{0xaa, 0x00}, 0, 0}
};
- for (i = 0; i < ARRAY_SIZE(start_commands); i++) {
- retval = jlj_write2(gspca_dev, start_commands[i].instruction);
- if (retval < 0)
- return retval;
+
+ sd->blocks_left = 0;
+ /* Under Windows, USB spy shows that only the 9 first start
+ * commands are used for SPORTSCAM_DV15 webcam
+ */
+ if (sd->type == SPORTSCAM_DV15)
+ start_commands_size = SPORTSCAM_DV15_CMD_SIZE;
+ else
+ start_commands_size = ARRAY_SIZE(start_commands);
+
+ for (i = 0; i < start_commands_size; i++) {
+ jlj_write2(gspca_dev, start_commands[i].instruction);
+ if (start_commands[i].delay)
+ msleep(start_commands[i].delay);
if (start_commands[i].ack_wanted)
- retval = jlj_read1(gspca_dev, response);
- if (retval < 0)
- return retval;
+ jlj_read1(gspca_dev, response);
}
- PDEBUG(D_ERR, "jlj_start retval is %d", retval);
- return retval;
+ setcamquality(gspca_dev);
+ msleep(2);
+ setfreq(gspca_dev);
+ if (gspca_dev->usb_err < 0)
+ PDEBUG(D_ERR, "Start streaming command failed");
+ return gspca_dev->usb_err;
}
-static int jlj_stop(struct gspca_dev *gspca_dev)
+static void sd_pkt_scan(struct gspca_dev *gspca_dev,
+ u8 *data, int len)
{
- int i;
- int retval;
- struct jlj_command stop_commands[] = {
- {{0x71, 0x00}, 0},
- {{0x70, 0x09}, 0},
- {{0x71, 0x80}, 0},
- {{0x70, 0x05}, 0}
- };
- for (i = 0; i < ARRAY_SIZE(stop_commands); i++) {
- retval = jlj_write2(gspca_dev, stop_commands[i].instruction);
- if (retval < 0)
- return retval;
- }
- return retval;
-}
-
-/* This function is called as a workqueue function and runs whenever the camera
- * is streaming data. Because it is a workqueue function it is allowed to sleep
- * so we can use synchronous USB calls. To avoid possible collisions with other
- * threads attempting to use the camera's USB interface the gspca usb_lock is
- * used when performing the one USB control operation inside the workqueue,
- * which tells the camera to close the stream. In practice the only thing
- * which needs to be protected against is the usb_set_interface call that
- * gspca makes during stream_off. Otherwise the camera doesn't provide any
- * controls that the user could try to change.
- */
-
-static void jlj_dostream(struct work_struct *work)
-{
- struct sd *dev = container_of(work, struct sd, work_struct);
- struct gspca_dev *gspca_dev = &dev->gspca_dev;
- int blocks_left; /* 0x200-sized blocks remaining in current frame. */
- int act_len;
+ struct sd *sd = (struct sd *) gspca_dev;
int packet_type;
- int ret;
- u8 *buffer;
+ u32 header_marker;
- buffer = kmalloc(JEILINJ_MAX_TRANSFER, GFP_KERNEL | GFP_DMA);
- if (!buffer) {
- err("Couldn't allocate USB buffer");
- goto quit_stream;
+ PDEBUG(D_STREAM, "Got %d bytes out of %d for Block 0",
+ len, JEILINJ_MAX_TRANSFER);
+ if (len != JEILINJ_MAX_TRANSFER) {
+ PDEBUG(D_PACK, "bad length");
+ goto discard;
}
- while (gspca_dev->present && gspca_dev->streaming) {
- /*
- * Now request data block 0. Line 0 reports the size
- * to download, in blocks of size 0x200, and also tells the
- * "actual" data size, in bytes, which seems best to ignore.
- */
- ret = usb_bulk_msg(gspca_dev->dev,
- usb_rcvbulkpipe(gspca_dev->dev, 0x82),
- buffer, JEILINJ_MAX_TRANSFER, &act_len,
- JEILINJ_DATA_TIMEOUT);
- PDEBUG(D_STREAM,
- "Got %d bytes out of %d for Block 0",
- act_len, JEILINJ_MAX_TRANSFER);
- if (ret < 0 || act_len < FRAME_HEADER_LEN)
- goto quit_stream;
- blocks_left = buffer[0x0a] - 1;
- PDEBUG(D_STREAM, "blocks_left = 0x%x", blocks_left);
-
+ /* check if it's start of frame */
+ header_marker = ((u32 *)data)[0];
+ if (header_marker == FRAME_START) {
+ sd->blocks_left = data[0x0a] - 1;
+ PDEBUG(D_STREAM, "blocks_left = 0x%x", sd->blocks_left);
/* Start a new frame, and add the JPEG header, first thing */
gspca_frame_add(gspca_dev, FIRST_PACKET,
- dev->jpeg_hdr, JPEG_HDR_SZ);
+ sd->jpeg_hdr, JPEG_HDR_SZ);
/* Toss line 0 of data block 0, keep the rest. */
gspca_frame_add(gspca_dev, INTER_PACKET,
- buffer + FRAME_HEADER_LEN,
+ data + FRAME_HEADER_LEN,
JEILINJ_MAX_TRANSFER - FRAME_HEADER_LEN);
-
- while (blocks_left > 0) {
- if (!gspca_dev->present)
- goto quit_stream;
- ret = usb_bulk_msg(gspca_dev->dev,
- usb_rcvbulkpipe(gspca_dev->dev, 0x82),
- buffer, JEILINJ_MAX_TRANSFER, &act_len,
- JEILINJ_DATA_TIMEOUT);
- if (ret < 0 || act_len < JEILINJ_MAX_TRANSFER)
- goto quit_stream;
- PDEBUG(D_STREAM,
- "%d blocks remaining for frame", blocks_left);
- blocks_left -= 1;
- if (blocks_left == 0)
- packet_type = LAST_PACKET;
- else
- packet_type = INTER_PACKET;
- gspca_frame_add(gspca_dev, packet_type,
- buffer, JEILINJ_MAX_TRANSFER);
- }
- }
-quit_stream:
- mutex_lock(&gspca_dev->usb_lock);
- if (gspca_dev->present)
- jlj_stop(gspca_dev);
- mutex_unlock(&gspca_dev->usb_lock);
- kfree(buffer);
+ } else if (sd->blocks_left > 0) {
+ PDEBUG(D_STREAM, "%d blocks remaining for frame",
+ sd->blocks_left);
+ sd->blocks_left -= 1;
+ if (sd->blocks_left == 0)
+ packet_type = LAST_PACKET;
+ else
+ packet_type = INTER_PACKET;
+ gspca_frame_add(gspca_dev, packet_type,
+ data, JEILINJ_MAX_TRANSFER);
+ } else
+ goto discard;
+ return;
+discard:
+ /* Discard data until a new frame starts. */
+ gspca_dev->last_packet_type = DISCARD_PACKET;
}
/* This function is called at probe time just before sd_init */
@@ -254,78 +400,169 @@
struct cam *cam = &gspca_dev->cam;
struct sd *dev = (struct sd *) gspca_dev;
- dev->quality = 85;
- dev->jpegqual = 85;
+ dev->type = id->driver_info;
+ gspca_dev->cam.ctrls = dev->ctrls;
+ dev->quality = QUALITY_DEF;
+ dev->ctrls[LIGHTFREQ].def = V4L2_CID_POWER_LINE_FREQUENCY_60HZ;
+ dev->ctrls[RED].def = RED_BALANCE_DEF;
+ dev->ctrls[GREEN].def = GREEN_BALANCE_DEF;
+ dev->ctrls[BLUE].def = BLUE_BALANCE_DEF;
PDEBUG(D_PROBE,
"JEILINJ camera detected"
" (vid/pid 0x%04X:0x%04X)", id->idVendor, id->idProduct);
cam->cam_mode = jlj_mode;
- cam->nmodes = 1;
+ cam->nmodes = ARRAY_SIZE(jlj_mode);
cam->bulk = 1;
- /* We don't use the buffer gspca allocates so make it small. */
- cam->bulk_size = 32;
- INIT_WORK(&dev->work_struct, jlj_dostream);
+ cam->bulk_nurbs = 1;
+ cam->bulk_size = JEILINJ_MAX_TRANSFER;
return 0;
}
-/* called on streamoff with alt==0 and on disconnect */
-/* the usb_lock is held at entry - restore on exit */
-static void sd_stop0(struct gspca_dev *gspca_dev)
+static void sd_stopN(struct gspca_dev *gspca_dev)
{
- struct sd *dev = (struct sd *) gspca_dev;
+ int i;
+ u8 *buf;
+ u8 stop_commands[][2] = {
+ {0x71, 0x00},
+ {0x70, 0x09},
+ {0x71, 0x80},
+ {0x70, 0x05}
+ };
- /* wait for the work queue to terminate */
- mutex_unlock(&gspca_dev->usb_lock);
- /* This waits for jlj_dostream to finish */
- destroy_workqueue(dev->work_thread);
- dev->work_thread = NULL;
- mutex_lock(&gspca_dev->usb_lock);
+ for (;;) {
+ /* get the image remaining blocks */
+ usb_bulk_msg(gspca_dev->dev,
+ gspca_dev->urb[0]->pipe,
+ gspca_dev->urb[0]->transfer_buffer,
+ JEILINJ_MAX_TRANSFER, NULL,
+ JEILINJ_DATA_TIMEOUT);
+
+ /* search for 0xff 0xd9 (EOF for JPEG) */
+ i = 0;
+ buf = gspca_dev->urb[0]->transfer_buffer;
+ while ((i < (JEILINJ_MAX_TRANSFER - 1)) &&
+ ((buf[i] != 0xff) || (buf[i+1] != 0xd9)))
+ i++;
+
+ if (i != (JEILINJ_MAX_TRANSFER - 1))
+ /* last remaining block found */
+ break;
+ }
+
+ for (i = 0; i < ARRAY_SIZE(stop_commands); i++)
+ jlj_write2(gspca_dev, stop_commands[i]);
}
/* this function is called at probe and resume time */
static int sd_init(struct gspca_dev *gspca_dev)
{
- return 0;
+ return gspca_dev->usb_err;
}
/* Set up for getting frames. */
static int sd_start(struct gspca_dev *gspca_dev)
{
struct sd *dev = (struct sd *) gspca_dev;
- int ret;
/* create the JPEG header */
jpeg_define(dev->jpeg_hdr, gspca_dev->height, gspca_dev->width,
0x21); /* JPEG 422 */
jpeg_set_qual(dev->jpeg_hdr, dev->quality);
- PDEBUG(D_STREAM, "Start streaming at 320x240");
- ret = jlj_start(gspca_dev);
- if (ret < 0) {
- PDEBUG(D_ERR, "Start streaming command failed");
- return ret;
- }
- /* Start the workqueue function to do the streaming */
- dev->work_thread = create_singlethread_workqueue(MODULE_NAME);
- queue_work(dev->work_thread, &dev->work_struct);
-
- return 0;
+ PDEBUG(D_STREAM, "Start streaming at %dx%d",
+ gspca_dev->height, gspca_dev->width);
+ jlj_start(gspca_dev);
+ return gspca_dev->usb_err;
}
/* Table of supported USB devices */
static const struct usb_device_id device_table[] = {
- {USB_DEVICE(0x0979, 0x0280)},
+ {USB_DEVICE(0x0979, 0x0280), .driver_info = SAKAR_57379},
+ {USB_DEVICE(0x0979, 0x0270), .driver_info = SPORTSCAM_DV15},
{}
};
MODULE_DEVICE_TABLE(usb, device_table);
+static int sd_querymenu(struct gspca_dev *gspca_dev,
+ struct v4l2_querymenu *menu)
+{
+ switch (menu->id) {
+ case V4L2_CID_POWER_LINE_FREQUENCY:
+ switch (menu->index) {
+ case 0: /* V4L2_CID_POWER_LINE_FREQUENCY_DISABLED */
+ strcpy((char *) menu->name, "disable");
+ return 0;
+ case 1: /* V4L2_CID_POWER_LINE_FREQUENCY_50HZ */
+ strcpy((char *) menu->name, "50 Hz");
+ return 0;
+ case 2: /* V4L2_CID_POWER_LINE_FREQUENCY_60HZ */
+ strcpy((char *) menu->name, "60 Hz");
+ return 0;
+ }
+ break;
+ }
+ return -EINVAL;
+}
+
+static int sd_set_jcomp(struct gspca_dev *gspca_dev,
+ struct v4l2_jpegcompression *jcomp)
+{
+ struct sd *sd = (struct sd *) gspca_dev;
+
+ if (jcomp->quality < QUALITY_MIN)
+ sd->quality = QUALITY_MIN;
+ else if (jcomp->quality > QUALITY_MAX)
+ sd->quality = QUALITY_MAX;
+ else
+ sd->quality = jcomp->quality;
+ if (gspca_dev->streaming) {
+ jpeg_set_qual(sd->jpeg_hdr, sd->quality);
+ setcamquality(gspca_dev);
+ }
+ return 0;
+}
+
+static int sd_get_jcomp(struct gspca_dev *gspca_dev,
+ struct v4l2_jpegcompression *jcomp)
+{
+ struct sd *sd = (struct sd *) gspca_dev;
+
+ memset(jcomp, 0, sizeof *jcomp);
+ jcomp->quality = sd->quality;
+ jcomp->jpeg_markers = V4L2_JPEG_MARKER_DHT
+ | V4L2_JPEG_MARKER_DQT;
+ return 0;
+}
+
+
/* sub-driver description */
-static const struct sd_desc sd_desc = {
+static const struct sd_desc sd_desc_sakar_57379 = {
.name = MODULE_NAME,
.config = sd_config,
.init = sd_init,
.start = sd_start,
- .stop0 = sd_stop0,
+ .stopN = sd_stopN,
+ .pkt_scan = sd_pkt_scan,
+};
+
+/* sub-driver description */
+static const struct sd_desc sd_desc_sportscam_dv15 = {
+ .name = MODULE_NAME,
+ .config = sd_config,
+ .init = sd_init,
+ .start = sd_start,
+ .stopN = sd_stopN,
+ .pkt_scan = sd_pkt_scan,
+ .ctrls = sd_ctrls,
+ .nctrls = ARRAY_SIZE(sd_ctrls),
+ .querymenu = sd_querymenu,
+ .get_jcomp = sd_get_jcomp,
+ .set_jcomp = sd_set_jcomp,
+};
+
+static const struct sd_desc *sd_desc[2] = {
+ &sd_desc_sakar_57379,
+ &sd_desc_sportscam_dv15
};
/* -- device connect -- */
@@ -333,7 +570,7 @@
const struct usb_device_id *id)
{
return gspca_dev_probe(intf, id,
- &sd_desc,
+ sd_desc[id->driver_info],
sizeof(struct sd),
THIS_MODULE);
}
diff --git a/drivers/media/video/gspca/kinect.c b/drivers/media/video/gspca/kinect.c
new file mode 100644
index 0000000..66671a4
--- /dev/null
+++ b/drivers/media/video/gspca/kinect.c
@@ -0,0 +1,429 @@
+/*
+ * kinect sensor device camera, gspca driver
+ *
+ * Copyright (C) 2011 Antonio Ospite <ospite@studenti.unina.it>
+ *
+ * Based on the OpenKinect project and libfreenect
+ * http://openkinect.org/wiki/Init_Analysis
+ *
+ * Special thanks to Steven Toth and kernellabs.com for sponsoring a Kinect
+ * sensor device which I tested the driver on.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#define MODULE_NAME "kinect"
+
+#include "gspca.h"
+
+#define CTRL_TIMEOUT 500
+
+MODULE_AUTHOR("Antonio Ospite <ospite@studenti.unina.it>");
+MODULE_DESCRIPTION("GSPCA/Kinect Sensor Device USB Camera Driver");
+MODULE_LICENSE("GPL");
+
+#ifdef DEBUG
+int gspca_debug = D_ERR | D_PROBE | D_CONF | D_STREAM | D_FRAM | D_PACK |
+ D_USBI | D_USBO | D_V4L2;
+#endif
+
+struct pkt_hdr {
+ uint8_t magic[2];
+ uint8_t pad;
+ uint8_t flag;
+ uint8_t unk1;
+ uint8_t seq;
+ uint8_t unk2;
+ uint8_t unk3;
+ uint32_t timestamp;
+};
+
+struct cam_hdr {
+ uint8_t magic[2];
+ uint16_t len;
+ uint16_t cmd;
+ uint16_t tag;
+};
+
+/* specific webcam descriptor */
+struct sd {
+ struct gspca_dev gspca_dev; /* !! must be the first item */
+ uint16_t cam_tag; /* a sequence number for packets */
+ uint8_t stream_flag; /* to identify different stream types */
+ uint8_t obuf[0x400]; /* output buffer for control commands */
+ uint8_t ibuf[0x200]; /* input buffer for control commands */
+};
+
+/* V4L2 controls supported by the driver */
+/* controls prototypes here */
+
+static const struct ctrl sd_ctrls[] = {
+};
+
+#define MODE_640x480 0x0001
+#define MODE_640x488 0x0002
+#define MODE_1280x1024 0x0004
+
+#define FORMAT_BAYER 0x0010
+#define FORMAT_UYVY 0x0020
+#define FORMAT_Y10B 0x0040
+
+#define FPS_HIGH 0x0100
+
+static const struct v4l2_pix_format video_camera_mode[] = {
+ {640, 480, V4L2_PIX_FMT_SGRBG8, V4L2_FIELD_NONE,
+ .bytesperline = 640,
+ .sizeimage = 640 * 480,
+ .colorspace = V4L2_COLORSPACE_SRGB,
+ .priv = MODE_640x480 | FORMAT_BAYER | FPS_HIGH},
+ {640, 480, V4L2_PIX_FMT_UYVY, V4L2_FIELD_NONE,
+ .bytesperline = 640 * 2,
+ .sizeimage = 640 * 480 * 2,
+ .colorspace = V4L2_COLORSPACE_SRGB,
+ .priv = MODE_640x480 | FORMAT_UYVY},
+ {1280, 1024, V4L2_PIX_FMT_SGRBG8, V4L2_FIELD_NONE,
+ .bytesperline = 1280,
+ .sizeimage = 1280 * 1024,
+ .colorspace = V4L2_COLORSPACE_SRGB,
+ .priv = MODE_1280x1024 | FORMAT_BAYER},
+ {640, 488, V4L2_PIX_FMT_Y10BPACK, V4L2_FIELD_NONE,
+ .bytesperline = 640 * 10 / 8,
+ .sizeimage = 640 * 488 * 10 / 8,
+ .colorspace = V4L2_COLORSPACE_SRGB,
+ .priv = MODE_640x488 | FORMAT_Y10B | FPS_HIGH},
+ {1280, 1024, V4L2_PIX_FMT_Y10BPACK, V4L2_FIELD_NONE,
+ .bytesperline = 1280 * 10 / 8,
+ .sizeimage = 1280 * 1024 * 10 / 8,
+ .colorspace = V4L2_COLORSPACE_SRGB,
+ .priv = MODE_1280x1024 | FORMAT_Y10B},
+};
+
+static int kinect_write(struct usb_device *udev, uint8_t *data,
+ uint16_t wLength)
+{
+ return usb_control_msg(udev,
+ usb_sndctrlpipe(udev, 0),
+ 0x00,
+ USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
+ 0, 0, data, wLength, CTRL_TIMEOUT);
+}
+
+static int kinect_read(struct usb_device *udev, uint8_t *data, uint16_t wLength)
+{
+ return usb_control_msg(udev,
+ usb_rcvctrlpipe(udev, 0),
+ 0x00,
+ USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
+ 0, 0, data, wLength, CTRL_TIMEOUT);
+}
+
+static int send_cmd(struct gspca_dev *gspca_dev, uint16_t cmd, void *cmdbuf,
+ unsigned int cmd_len, void *replybuf, unsigned int reply_len)
+{
+ struct sd *sd = (struct sd *) gspca_dev;
+ struct usb_device *udev = gspca_dev->dev;
+ int res, actual_len;
+ uint8_t *obuf = sd->obuf;
+ uint8_t *ibuf = sd->ibuf;
+ struct cam_hdr *chdr = (void *)obuf;
+ struct cam_hdr *rhdr = (void *)ibuf;
+
+ if (cmd_len & 1 || cmd_len > (0x400 - sizeof(*chdr))) {
+ err("send_cmd: Invalid command length (0x%x)", cmd_len);
+ return -1;
+ }
+
+ chdr->magic[0] = 0x47;
+ chdr->magic[1] = 0x4d;
+ chdr->cmd = cpu_to_le16(cmd);
+ chdr->tag = cpu_to_le16(sd->cam_tag);
+ chdr->len = cpu_to_le16(cmd_len / 2);
+
+ memcpy(obuf+sizeof(*chdr), cmdbuf, cmd_len);
+
+ res = kinect_write(udev, obuf, cmd_len + sizeof(*chdr));
+ PDEBUG(D_USBO, "Control cmd=%04x tag=%04x len=%04x: %d", cmd,
+ sd->cam_tag, cmd_len, res);
+ if (res < 0) {
+ err("send_cmd: Output control transfer failed (%d)", res);
+ return res;
+ }
+
+ do {
+ actual_len = kinect_read(udev, ibuf, 0x200);
+ } while (actual_len == 0);
+ PDEBUG(D_USBO, "Control reply: %d", res);
+ if (actual_len < sizeof(*rhdr)) {
+ err("send_cmd: Input control transfer failed (%d)", res);
+ return res;
+ }
+ actual_len -= sizeof(*rhdr);
+
+ if (rhdr->magic[0] != 0x52 || rhdr->magic[1] != 0x42) {
+ err("send_cmd: Bad magic %02x %02x", rhdr->magic[0],
+ rhdr->magic[1]);
+ return -1;
+ }
+ if (rhdr->cmd != chdr->cmd) {
+ err("send_cmd: Bad cmd %02x != %02x", rhdr->cmd, chdr->cmd);
+ return -1;
+ }
+ if (rhdr->tag != chdr->tag) {
+ err("send_cmd: Bad tag %04x != %04x", rhdr->tag, chdr->tag);
+ return -1;
+ }
+ if (cpu_to_le16(rhdr->len) != (actual_len/2)) {
+ err("send_cmd: Bad len %04x != %04x",
+ cpu_to_le16(rhdr->len), (int)(actual_len/2));
+ return -1;
+ }
+
+ if (actual_len > reply_len) {
+ warn("send_cmd: Data buffer is %d bytes long, but got %d bytes",
+ reply_len, actual_len);
+ memcpy(replybuf, ibuf+sizeof(*rhdr), reply_len);
+ } else {
+ memcpy(replybuf, ibuf+sizeof(*rhdr), actual_len);
+ }
+
+ sd->cam_tag++;
+
+ return actual_len;
+}
+
+static int write_register(struct gspca_dev *gspca_dev, uint16_t reg,
+ uint16_t data)
+{
+ uint16_t reply[2];
+ uint16_t cmd[2];
+ int res;
+
+ cmd[0] = cpu_to_le16(reg);
+ cmd[1] = cpu_to_le16(data);
+
+ PDEBUG(D_USBO, "Write Reg 0x%04x <= 0x%02x", reg, data);
+ res = send_cmd(gspca_dev, 0x03, cmd, 4, reply, 4);
+ if (res < 0)
+ return res;
+ if (res != 2) {
+ warn("send_cmd returned %d [%04x %04x], 0000 expected",
+ res, reply[0], reply[1]);
+ }
+ return 0;
+}
+
+/* this function is called at probe time */
+static int sd_config(struct gspca_dev *gspca_dev,
+ const struct usb_device_id *id)
+{
+ struct sd *sd = (struct sd *) gspca_dev;
+ struct cam *cam;
+
+ sd->cam_tag = 0;
+
+ /* Only video stream is supported for now,
+ * which has stream flag = 0x80 */
+ sd->stream_flag = 0x80;
+
+ cam = &gspca_dev->cam;
+
+ cam->cam_mode = video_camera_mode;
+ cam->nmodes = ARRAY_SIZE(video_camera_mode);
+
+#if 0
+ /* Setting those values is not needed for video stream */
+ cam->npkt = 15;
+ gspca_dev->pkt_size = 960 * 2;
+#endif
+
+ return 0;
+}
+
+/* this function is called at probe and resume time */
+static int sd_init(struct gspca_dev *gspca_dev)
+{
+ PDEBUG(D_PROBE, "Kinect Camera device.");
+
+ return 0;
+}
+
+static int sd_start(struct gspca_dev *gspca_dev)
+{
+ int mode;
+ uint8_t fmt_reg, fmt_val;
+ uint8_t res_reg, res_val;
+ uint8_t fps_reg, fps_val;
+ uint8_t mode_val;
+
+ mode = gspca_dev->cam.cam_mode[gspca_dev->curr_mode].priv;
+
+ if (mode & FORMAT_Y10B) {
+ fmt_reg = 0x19;
+ res_reg = 0x1a;
+ fps_reg = 0x1b;
+ mode_val = 0x03;
+ } else {
+ fmt_reg = 0x0c;
+ res_reg = 0x0d;
+ fps_reg = 0x0e;
+ mode_val = 0x01;
+ }
+
+ /* format */
+ if (mode & FORMAT_UYVY)
+ fmt_val = 0x05;
+ else
+ fmt_val = 0x00;
+
+ if (mode & MODE_1280x1024)
+ res_val = 0x02;
+ else
+ res_val = 0x01;
+
+ if (mode & FPS_HIGH)
+ fps_val = 0x1e;
+ else
+ fps_val = 0x0f;
+
+
+ /* turn off IR-reset function */
+ write_register(gspca_dev, 0x105, 0x00);
+
+ /* Reset video stream */
+ write_register(gspca_dev, 0x05, 0x00);
+
+ /* Due to some ridiculous condition in the firmware, we have to start
+ * and stop the depth stream before the camera will hand us 1280x1024
+ * IR. This is a stupid workaround, but we've yet to find a better
+ * solution.
+ *
+ * Thanks to Drew Fisher for figuring this out.
+ */
+ if (mode & (FORMAT_Y10B | MODE_1280x1024)) {
+ write_register(gspca_dev, 0x13, 0x01);
+ write_register(gspca_dev, 0x14, 0x1e);
+ write_register(gspca_dev, 0x06, 0x02);
+ write_register(gspca_dev, 0x06, 0x00);
+ }
+
+ write_register(gspca_dev, fmt_reg, fmt_val);
+ write_register(gspca_dev, res_reg, res_val);
+ write_register(gspca_dev, fps_reg, fps_val);
+
+ /* Start video stream */
+ write_register(gspca_dev, 0x05, mode_val);
+
+ /* disable Hflip */
+ write_register(gspca_dev, 0x47, 0x00);
+
+ return 0;
+}
+
+static void sd_stopN(struct gspca_dev *gspca_dev)
+{
+ /* reset video stream */
+ write_register(gspca_dev, 0x05, 0x00);
+}
+
+static void sd_pkt_scan(struct gspca_dev *gspca_dev, u8 *__data, int len)
+{
+ struct sd *sd = (struct sd *) gspca_dev;
+
+ struct pkt_hdr *hdr = (void *)__data;
+ uint8_t *data = __data + sizeof(*hdr);
+ int datalen = len - sizeof(*hdr);
+
+ uint8_t sof = sd->stream_flag | 1;
+ uint8_t mof = sd->stream_flag | 2;
+ uint8_t eof = sd->stream_flag | 5;
+
+ if (len < 12)
+ return;
+
+ if (hdr->magic[0] != 'R' || hdr->magic[1] != 'B') {
+ warn("[Stream %02x] Invalid magic %02x%02x", sd->stream_flag,
+ hdr->magic[0], hdr->magic[1]);
+ return;
+ }
+
+ if (hdr->flag == sof)
+ gspca_frame_add(gspca_dev, FIRST_PACKET, data, datalen);
+
+ else if (hdr->flag == mof)
+ gspca_frame_add(gspca_dev, INTER_PACKET, data, datalen);
+
+ else if (hdr->flag == eof)
+ gspca_frame_add(gspca_dev, LAST_PACKET, data, datalen);
+
+ else
+ warn("Packet type not recognized...");
+}
+
+/* sub-driver description */
+static const struct sd_desc sd_desc = {
+ .name = MODULE_NAME,
+ .ctrls = sd_ctrls,
+ .nctrls = ARRAY_SIZE(sd_ctrls),
+ .config = sd_config,
+ .init = sd_init,
+ .start = sd_start,
+ .stopN = sd_stopN,
+ .pkt_scan = sd_pkt_scan,
+ /*
+ .querymenu = sd_querymenu,
+ .get_streamparm = sd_get_streamparm,
+ .set_streamparm = sd_set_streamparm,
+ */
+};
+
+/* -- module initialisation -- */
+static const struct usb_device_id device_table[] = {
+ {USB_DEVICE(0x045e, 0x02ae)},
+ {}
+};
+
+MODULE_DEVICE_TABLE(usb, device_table);
+
+/* -- device connect -- */
+static int sd_probe(struct usb_interface *intf, const struct usb_device_id *id)
+{
+ return gspca_dev_probe(intf, id, &sd_desc, sizeof(struct sd),
+ THIS_MODULE);
+}
+
+static struct usb_driver sd_driver = {
+ .name = MODULE_NAME,
+ .id_table = device_table,
+ .probe = sd_probe,
+ .disconnect = gspca_disconnect,
+#ifdef CONFIG_PM
+ .suspend = gspca_suspend,
+ .resume = gspca_resume,
+#endif
+};
+
+/* -- module insert / remove -- */
+static int __init sd_mod_init(void)
+{
+ return usb_register(&sd_driver);
+}
+
+static void __exit sd_mod_exit(void)
+{
+ usb_deregister(&sd_driver);
+}
+
+module_init(sd_mod_init);
+module_exit(sd_mod_exit);
diff --git a/drivers/media/video/gspca/spca508.c b/drivers/media/video/gspca/spca508.c
index 41dce49..9d0b460 100644
--- a/drivers/media/video/gspca/spca508.c
+++ b/drivers/media/video/gspca/spca508.c
@@ -1375,7 +1375,6 @@
{
struct sd *sd = (struct sd *) gspca_dev;
struct cam *cam;
- int data1, data2;
const u16 (*init_data)[2];
static const u16 (*(init_data_tb[]))[2] = {
spca508_vista_init_data, /* CreativeVista 0 */
@@ -1386,6 +1385,9 @@
spca508_init_data, /* ViewQuestVQ110 5 */
};
+#ifdef GSPCA_DEBUG
+ int data1, data2;
+
/* Read from global register the USB product and vendor IDs, just to
* prove that we can communicate with the device. This works, which
* confirms at we are communicating properly and that the device
@@ -1400,6 +1402,7 @@
data1 = reg_read(gspca_dev, 0x8621);
PDEBUG(D_PROBE, "Window 1 average luminance: %d", data1);
+#endif
cam = &gspca_dev->cam;
cam->cam_mode = sif_mode;
diff --git a/drivers/media/video/gspca/stk014.c b/drivers/media/video/gspca/stk014.c
index 87be52b..7637477 100644
--- a/drivers/media/video/gspca/stk014.c
+++ b/drivers/media/video/gspca/stk014.c
@@ -436,17 +436,14 @@
static int sd_querymenu(struct gspca_dev *gspca_dev,
struct v4l2_querymenu *menu)
{
+ static const char *freq_nm[3] = {"NoFliker", "50 Hz", "60 Hz"};
+
switch (menu->id) {
case V4L2_CID_POWER_LINE_FREQUENCY:
- switch (menu->index) {
- case 1: /* V4L2_CID_POWER_LINE_FREQUENCY_50HZ */
- strcpy((char *) menu->name, "50 Hz");
- return 0;
- case 2: /* V4L2_CID_POWER_LINE_FREQUENCY_60HZ */
- strcpy((char *) menu->name, "60 Hz");
- return 0;
- }
- break;
+ if ((unsigned) menu->index >= ARRAY_SIZE(freq_nm))
+ break;
+ strcpy((char *) menu->name, freq_nm[menu->index]);
+ return 0;
}
return -EINVAL;
}
diff --git a/drivers/media/video/gspca/stv06xx/stv06xx_pb0100.c b/drivers/media/video/gspca/stv06xx/stv06xx_pb0100.c
index ac47b4c..75a5b9c 100644
--- a/drivers/media/video/gspca/stv06xx/stv06xx_pb0100.c
+++ b/drivers/media/video/gspca/stv06xx/stv06xx_pb0100.c
@@ -217,6 +217,8 @@
intf = usb_ifnum_to_if(sd->gspca_dev.dev, sd->gspca_dev.iface);
alt = usb_altnum_to_altsetting(intf, sd->gspca_dev.alt);
+ if (!alt)
+ return -ENODEV;
packet_size = le16_to_cpu(alt->endpoint[0].desc.wMaxPacketSize);
/* If we don't have enough bandwidth use a lower framerate */
diff --git a/drivers/media/video/gspca/sunplus.c b/drivers/media/video/gspca/sunplus.c
index 543542a..b089c0d 100644
--- a/drivers/media/video/gspca/sunplus.c
+++ b/drivers/media/video/gspca/sunplus.c
@@ -396,57 +396,6 @@
req, index, value);
}
-/* read 1 byte */
-static u8 reg_r_1(struct gspca_dev *gspca_dev,
- u16 value) /* wValue */
-{
- int ret;
-
- if (gspca_dev->usb_err < 0)
- return 0;
- ret = usb_control_msg(gspca_dev->dev,
- usb_rcvctrlpipe(gspca_dev->dev, 0),
- 0x20, /* request */
- USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
- value,
- 0, /* index */
- gspca_dev->usb_buf, 1,
- 500); /* timeout */
- if (ret < 0) {
- err("reg_r_1 err %d", ret);
- gspca_dev->usb_err = ret;
- return 0;
- }
- return gspca_dev->usb_buf[0];
-}
-
-/* read 1 or 2 bytes */
-static u16 reg_r_12(struct gspca_dev *gspca_dev,
- u8 req, /* bRequest */
- u16 index, /* wIndex */
- u16 length) /* wLength (1 or 2 only) */
-{
- int ret;
-
- if (gspca_dev->usb_err < 0)
- return 0;
- gspca_dev->usb_buf[1] = 0;
- ret = usb_control_msg(gspca_dev->dev,
- usb_rcvctrlpipe(gspca_dev->dev, 0),
- req,
- USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
- 0, /* value */
- index,
- gspca_dev->usb_buf, length,
- 500);
- if (ret < 0) {
- err("reg_r_12 err %d", ret);
- gspca_dev->usb_err = ret;
- return 0;
- }
- return (gspca_dev->usb_buf[1] << 8) + gspca_dev->usb_buf[0];
-}
-
static void write_vector(struct gspca_dev *gspca_dev,
const struct cmd *data, int ncmds)
{
@@ -473,44 +422,46 @@
static void spca504_acknowledged_command(struct gspca_dev *gspca_dev,
u8 req, u16 idx, u16 val)
{
- u16 notdone;
-
reg_w_riv(gspca_dev, req, idx, val);
- notdone = reg_r_12(gspca_dev, 0x01, 0x0001, 1);
+ reg_r(gspca_dev, 0x01, 0x0001, 1);
+ PDEBUG(D_FRAM, "before wait 0x%04x", gspca_dev->usb_buf[0]);
reg_w_riv(gspca_dev, req, idx, val);
- PDEBUG(D_FRAM, "before wait 0x%04x", notdone);
-
msleep(200);
- notdone = reg_r_12(gspca_dev, 0x01, 0x0001, 1);
- PDEBUG(D_FRAM, "after wait 0x%04x", notdone);
+ reg_r(gspca_dev, 0x01, 0x0001, 1);
+ PDEBUG(D_FRAM, "after wait 0x%04x", gspca_dev->usb_buf[0]);
}
+#ifdef GSPCA_DEBUG
static void spca504_read_info(struct gspca_dev *gspca_dev)
{
int i;
u8 info[6];
- for (i = 0; i < 6; i++)
- info[i] = reg_r_1(gspca_dev, i);
+ for (i = 0; i < 6; i++) {
+ reg_r(gspca_dev, 0, i, 1);
+ info[i] = gspca_dev->usb_buf[0];
+ }
PDEBUG(D_STREAM,
"Read info: %d %d %d %d %d %d."
" Should be 1,0,2,2,0,0",
info[0], info[1], info[2],
info[3], info[4], info[5]);
}
+#endif
static void spca504A_acknowledged_command(struct gspca_dev *gspca_dev,
u8 req,
- u16 idx, u16 val, u16 endcode, u8 count)
+ u16 idx, u16 val, u8 endcode, u8 count)
{
u16 status;
reg_w_riv(gspca_dev, req, idx, val);
- status = reg_r_12(gspca_dev, 0x01, 0x0001, 1);
+ reg_r(gspca_dev, 0x01, 0x0001, 1);
if (gspca_dev->usb_err < 0)
return;
- PDEBUG(D_FRAM, "Status 0x%04x Need 0x%04x", status, endcode);
+ PDEBUG(D_FRAM, "Status 0x%02x Need 0x%02x",
+ gspca_dev->usb_buf[0], endcode);
if (!count)
return;
count = 200;
@@ -518,7 +469,8 @@
msleep(10);
/* gsmart mini2 write a each wait setting 1 ms is enough */
/* reg_w_riv(gspca_dev, req, idx, val); */
- status = reg_r_12(gspca_dev, 0x01, 0x0001, 1);
+ reg_r(gspca_dev, 0x01, 0x0001, 1);
+ status = gspca_dev->usb_buf[0];
if (status == endcode) {
PDEBUG(D_FRAM, "status 0x%04x after wait %d",
status, 200 - count);
@@ -555,17 +507,19 @@
}
}
+#ifdef GSPCA_DEBUG
static void spca50x_GetFirmware(struct gspca_dev *gspca_dev)
{
u8 *data;
data = gspca_dev->usb_buf;
reg_r(gspca_dev, 0x20, 0, 5);
- PDEBUG(D_STREAM, "FirmWare : %d %d %d %d %d ",
+ PDEBUG(D_STREAM, "FirmWare: %d %d %d %d %d",
data[0], data[1], data[2], data[3], data[4]);
reg_r(gspca_dev, 0x23, 0, 64);
reg_r(gspca_dev, 0x23, 1, 64);
}
+#endif
static void spca504B_SetSizeType(struct gspca_dev *gspca_dev)
{
@@ -578,7 +532,9 @@
reg_w_riv(gspca_dev, 0x31, 0, 0);
spca504B_WaitCmdStatus(gspca_dev);
spca504B_PollingDataReady(gspca_dev);
+#ifdef GSPCA_DEBUG
spca50x_GetFirmware(gspca_dev);
+#endif
reg_w_1(gspca_dev, 0x24, 0, 8, 2); /* type */
reg_r(gspca_dev, 0x24, 8, 1);
@@ -628,7 +584,8 @@
cnt = 256;
while (--cnt > 0) {
/* With this we get the status, when return 0 it's all ok */
- if (reg_r_12(gspca_dev, 0x06, 0x00, 1) == 0)
+ reg_r(gspca_dev, 0x06, 0x00, 1);
+ if (gspca_dev->usb_buf[0] == 0)
return;
msleep(10);
}
@@ -772,10 +729,14 @@
/* fall thru */
case BRIDGE_SPCA533:
spca504B_PollingDataReady(gspca_dev);
+#ifdef GSPCA_DEBUG
spca50x_GetFirmware(gspca_dev);
+#endif
break;
case BRIDGE_SPCA536:
+#ifdef GSPCA_DEBUG
spca50x_GetFirmware(gspca_dev);
+#endif
reg_r(gspca_dev, 0x00, 0x5002, 1);
reg_w_1(gspca_dev, 0x24, 0, 0, 0);
reg_r(gspca_dev, 0x24, 0, 1);
@@ -801,7 +762,9 @@
/* case BRIDGE_SPCA504: */
PDEBUG(D_STREAM, "Opening SPCA504");
if (sd->subtype == AiptekMiniPenCam13) {
+#ifdef GSPCA_DEBUG
spca504_read_info(gspca_dev);
+#endif
/* Set AE AWB Banding Type 3-> 50Hz 2-> 60Hz */
spca504A_acknowledged_command(gspca_dev, 0x24,
@@ -873,7 +836,9 @@
break;
case BRIDGE_SPCA504:
if (sd->subtype == AiptekMiniPenCam13) {
+#ifdef GSPCA_DEBUG
spca504_read_info(gspca_dev);
+#endif
/* Set AE AWB Banding Type 3-> 50Hz 2-> 60Hz */
spca504A_acknowledged_command(gspca_dev, 0x24,
@@ -885,7 +850,9 @@
0, 0, 0x9d, 1);
} else {
spca504_acknowledged_command(gspca_dev, 0x24, 8, 3);
+#ifdef GSPCA_DEBUG
spca504_read_info(gspca_dev);
+#endif
spca504_acknowledged_command(gspca_dev, 0x24, 8, 3);
spca504_acknowledged_command(gspca_dev, 0x24, 0, 0);
}
diff --git a/drivers/media/video/gspca/t613.c b/drivers/media/video/gspca/t613.c
index a3eccd8..7e762d5 100644
--- a/drivers/media/video/gspca/t613.c
+++ b/drivers/media/video/gspca/t613.c
@@ -92,8 +92,6 @@
static int sd_getmirror(struct gspca_dev *gspca_dev, __s32 *val);
static int sd_seteffect(struct gspca_dev *gspca_dev, __s32 val);
static int sd_geteffect(struct gspca_dev *gspca_dev, __s32 *val);
-static int sd_querymenu(struct gspca_dev *gspca_dev,
- struct v4l2_querymenu *menu);
static const struct ctrl sd_ctrls[] = {
{
@@ -1379,17 +1377,14 @@
static int sd_querymenu(struct gspca_dev *gspca_dev,
struct v4l2_querymenu *menu)
{
+ static const char *freq_nm[3] = {"NoFliker", "50 Hz", "60 Hz"};
+
switch (menu->id) {
case V4L2_CID_POWER_LINE_FREQUENCY:
- switch (menu->index) {
- case 1: /* V4L2_CID_POWER_LINE_FREQUENCY_50HZ */
- strcpy((char *) menu->name, "50 Hz");
- return 0;
- case 2: /* V4L2_CID_POWER_LINE_FREQUENCY_60HZ */
- strcpy((char *) menu->name, "60 Hz");
- return 0;
- }
- break;
+ if ((unsigned) menu->index >= ARRAY_SIZE(freq_nm))
+ break;
+ strcpy((char *) menu->name, freq_nm[menu->index]);
+ return 0;
case V4L2_CID_EFFECTS:
if ((unsigned) menu->index < ARRAY_SIZE(effects_control)) {
strncpy((char *) menu->name,
diff --git a/drivers/media/video/gspca/zc3xx.c b/drivers/media/video/gspca/zc3xx.c
index fa164e8..61cdd56 100644
--- a/drivers/media/video/gspca/zc3xx.c
+++ b/drivers/media/video/gspca/zc3xx.c
@@ -3065,15 +3065,10 @@
{0xaa, 0x55, 0x0010}, /* 00,55,10,aa */
{0xa0, 0xf0, 0x0199}, /* 01,99,F0,cc */
{0xa0, 0x80, 0x019a}, /* 01,9A,80,cc */
- {0xaa, 0x03, 0x0003}, /* 00,03,03,aa */
- {0xaa, 0x10, 0x00fc}, /* 00,10,fc,aa */
- {0xaa, 0x36, 0x001d}, /* 00,36,1D,aa */
- {0xaa, 0x37, 0x004c}, /* 00,37,4C,aa */
- {0xaa, 0x3b, 0x001d}, /* 00,3B,1D,aa */
{}
};
-static const struct usb_action mc501cb_50HZScale[] = {
+static const struct usb_action mc501cb_50HZ[] = {
{0xaa, 0x03, 0x0003}, /* 00,03,03,aa */
{0xaa, 0x10, 0x00fc}, /* 00,10,fc,aa */
{0xaa, 0x36, 0x001d}, /* 00,36,1D,aa */
@@ -3082,15 +3077,10 @@
{0xaa, 0x3c, 0x004c}, /* 00,3C,4C,aa */
{0xaa, 0x3d, 0x001d}, /* 00,3D,1D,aa */
{0xaa, 0x3e, 0x004c}, /* 00,3E,4C,aa */
- {0xaa, 0x03, 0x0003}, /* 00,03,03,aa */
- {0xaa, 0x10, 0x00fc}, /* 00,10,fc,aa */
- {0xaa, 0x36, 0x003a}, /* 00,36,3A,aa */
- {0xaa, 0x37, 0x0098}, /* 00,37,98,aa */
- {0xaa, 0x3b, 0x003a}, /* 00,3B,3A,aa */
{}
};
-static const struct usb_action mc501cb_50HZ[] = {
+static const struct usb_action mc501cb_50HZScale[] = {
{0xaa, 0x03, 0x0003}, /* 00,03,03,aa */
{0xaa, 0x10, 0x00fc}, /* 00,10,fc,aa */
{0xaa, 0x36, 0x003a}, /* 00,36,3A,aa */
@@ -3099,15 +3089,10 @@
{0xaa, 0x3c, 0x0098}, /* 00,3C,98,aa */
{0xaa, 0x3d, 0x003a}, /* 00,3D,3A,aa */
{0xaa, 0x3e, 0x0098}, /* 00,3E,98,aa */
- {0xaa, 0x03, 0x0003}, /* 00,03,03,aa */
- {0xaa, 0x10, 0x00fc}, /* 00,10,fc,aa */
- {0xaa, 0x36, 0x0018}, /* 00,36,18,aa */
- {0xaa, 0x37, 0x006a}, /* 00,37,6A,aa */
- {0xaa, 0x3d, 0x0018}, /* 00,3D,18,aa */
{}
};
-static const struct usb_action mc501cb_60HZScale[] = {
+static const struct usb_action mc501cb_60HZ[] = {
{0xaa, 0x03, 0x0003}, /* 00,03,03,aa */
{0xaa, 0x10, 0x00fc}, /* 00,10,fc,aa */
{0xaa, 0x36, 0x0018}, /* 00,36,18,aa */
@@ -3116,15 +3101,10 @@
{0xaa, 0x3e, 0x006a}, /* 00,3E,6A,aa */
{0xaa, 0x3b, 0x0018}, /* 00,3B,18,aa */
{0xaa, 0x3c, 0x006a}, /* 00,3C,6A,aa */
- {0xaa, 0x03, 0x0003}, /* 00,03,03,aa */
- {0xaa, 0x10, 0x00fc}, /* 00,10,fc,aa */
- {0xaa, 0x36, 0x0030}, /* 00,36,30,aa */
- {0xaa, 0x37, 0x00d4}, /* 00,37,D4,aa */
- {0xaa, 0x3d, 0x0030}, /* 00,3D,30,aa */
{}
};
-static const struct usb_action mc501cb_60HZ[] = {
+static const struct usb_action mc501cb_60HZScale[] = {
{0xaa, 0x03, 0x0003}, /* 00,03,03,aa */
{0xaa, 0x10, 0x00fc}, /* 00,10,fc,aa */
{0xaa, 0x36, 0x0030}, /* 00,36,30,aa */
@@ -3133,15 +3113,10 @@
{0xaa, 0x3e, 0x00d4}, /* 00,3E,D4,aa */
{0xaa, 0x3b, 0x0030}, /* 00,3B,30,aa */
{0xaa, 0x3c, 0x00d4}, /* 00,3C,D4,aa */
- {0xaa, 0x03, 0x0003}, /* 00,03,03,aa */
- {0xaa, 0x10, 0x00fc}, /* 00,10,fc,aa */
- {0xaa, 0x36, 0x0018}, /* 00,36,18,aa */
- {0xaa, 0x37, 0x006a}, /* 00,37,6A,aa */
- {0xaa, 0x3d, 0x0018}, /* 00,3D,18,aa */
{}
};
-static const struct usb_action mc501cb_NoFlikerScale[] = {
+static const struct usb_action mc501cb_NoFliker[] = {
{0xaa, 0x03, 0x0003}, /* 00,03,03,aa */
{0xaa, 0x10, 0x00fc}, /* 00,10,fc,aa */
{0xaa, 0x36, 0x0018}, /* 00,36,18,aa */
@@ -3150,15 +3125,10 @@
{0xaa, 0x3e, 0x006a}, /* 00,3E,6A,aa */
{0xaa, 0x3b, 0x0018}, /* 00,3B,18,aa */
{0xaa, 0x3c, 0x006a}, /* 00,3C,6A,aa */
- {0xaa, 0x03, 0x0003}, /* 00,03,03,aa */
- {0xaa, 0x10, 0x00fc}, /* 00,10,fc,aa */
- {0xaa, 0x36, 0x0030}, /* 00,36,30,aa */
- {0xaa, 0x37, 0x00d4}, /* 00,37,D4,aa */
- {0xaa, 0x3d, 0x0030}, /* 00,3D,30,aa */
{}
};
-static const struct usb_action mc501cb_NoFliker[] = {
+static const struct usb_action mc501cb_NoFlikerScale[] = {
{0xaa, 0x03, 0x0003}, /* 00,03,03,aa */
{0xaa, 0x10, 0x00fc}, /* 00,10,fc,aa */
{0xaa, 0x36, 0x0030}, /* 00,36,30,aa */
@@ -6296,7 +6266,6 @@
{
struct sd *sd = (struct sd *) gspca_dev;
int i;
- u8 retbyte;
u16 retword;
/*fixme: lack of 8b=b3 (11,12)-> 10, 8b=e0 (14,15,16)-> 12 found in gspcav1*/
@@ -6389,8 +6358,12 @@
retword |= i2c_read(gspca_dev, 0x01); /* ID 1 */
PDEBUG(D_PROBE, "probe 3wr vga 2 0x%04x", retword);
if (retword == 0x2030) {
+#ifdef GSPCA_DEBUG
+ u8 retbyte;
+
retbyte = i2c_read(gspca_dev, 0x02); /* revision number */
PDEBUG(D_PROBE, "sensor PO2030 rev 0x%02x", retbyte);
+#endif
send_unknown(gspca_dev, SENSOR_PO2030);
return retword;
}
diff --git a/drivers/media/video/ivtv/ivtv-driver.c b/drivers/media/video/ivtv/ivtv-driver.c
index 3994642..a4e4dfd 100644
--- a/drivers/media/video/ivtv/ivtv-driver.c
+++ b/drivers/media/video/ivtv/ivtv-driver.c
@@ -810,7 +810,6 @@
const struct pci_device_id *pci_id)
{
u16 cmd;
- u8 card_rev;
unsigned char pci_latency;
IVTV_DEBUG_INFO("Enabling pci device\n");
@@ -857,7 +856,6 @@
}
IVTV_DEBUG_INFO("Bus Mastering Enabled.\n");
- pci_read_config_byte(pdev, PCI_CLASS_REVISION, &card_rev);
pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &pci_latency);
if (pci_latency < 64 && ivtv_pci_latency) {
@@ -874,7 +872,7 @@
IVTV_DEBUG_INFO("%d (rev %d) at %02x:%02x.%x, "
"irq: %d, latency: %d, memory: 0x%lx\n",
- pdev->device, card_rev, pdev->bus->number,
+ pdev->device, pdev->revision, pdev->bus->number,
PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
pdev->irq, pci_latency, (unsigned long)itv->base_addr);
diff --git a/drivers/media/video/mt9m111.c b/drivers/media/video/mt9m111.c
index 53fa2a7..ebebed9 100644
--- a/drivers/media/video/mt9m111.c
+++ b/drivers/media/video/mt9m111.c
@@ -315,10 +315,20 @@
static int mt9m111_setup_pixfmt(struct i2c_client *client, u16 outfmt)
{
int ret;
+ u16 mask = MT9M111_OUTFMT_PROCESSED_BAYER | MT9M111_OUTFMT_RGB |
+ MT9M111_OUTFMT_BYPASS_IFP | MT9M111_OUTFMT_SWAP_RGB_EVEN |
+ MT9M111_OUTFMT_RGB565 | MT9M111_OUTFMT_RGB555 |
+ MT9M111_OUTFMT_SWAP_YCbCr_Cb_Cr |
+ MT9M111_OUTFMT_SWAP_YCbCr_C_Y;
- ret = reg_write(OUTPUT_FORMAT_CTRL2_A, outfmt);
+ ret = reg_read(OUTPUT_FORMAT_CTRL2_A);
+ if (ret >= 0)
+ ret = reg_write(OUTPUT_FORMAT_CTRL2_A, (ret & ~mask) | outfmt);
if (!ret)
- ret = reg_write(OUTPUT_FORMAT_CTRL2_B, outfmt);
+ ret = reg_read(OUTPUT_FORMAT_CTRL2_B);
+ if (ret >= 0)
+ ret = reg_write(OUTPUT_FORMAT_CTRL2_B, (ret & ~mask) | outfmt);
+
return ret;
}
diff --git a/drivers/media/video/mt9v022.c b/drivers/media/video/mt9v022.c
index e313d83..fc76ed1 100644
--- a/drivers/media/video/mt9v022.c
+++ b/drivers/media/video/mt9v022.c
@@ -228,7 +228,7 @@
flags = soc_camera_apply_sensor_flags(icl, flags);
- if (flags & SOCAM_PCLK_SAMPLE_RISING)
+ if (flags & SOCAM_PCLK_SAMPLE_FALLING)
pixclk |= 0x10;
if (!(flags & SOCAM_HSYNC_ACTIVE_HIGH))
diff --git a/drivers/media/video/mt9v032.c b/drivers/media/video/mt9v032.c
new file mode 100644
index 0000000..1319c2c
--- /dev/null
+++ b/drivers/media/video/mt9v032.c
@@ -0,0 +1,773 @@
+/*
+ * Driver for MT9V032 CMOS Image Sensor from Micron
+ *
+ * Copyright (C) 2010, Laurent Pinchart <laurent.pinchart@ideasonboard.com>
+ *
+ * Based on the MT9M001 driver,
+ *
+ * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/delay.h>
+#include <linux/i2c.h>
+#include <linux/log2.h>
+#include <linux/mutex.h>
+#include <linux/slab.h>
+#include <linux/videodev2.h>
+#include <linux/v4l2-mediabus.h>
+
+#include <media/mt9v032.h>
+#include <media/v4l2-ctrls.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-subdev.h>
+
+#define MT9V032_PIXEL_ARRAY_HEIGHT 492
+#define MT9V032_PIXEL_ARRAY_WIDTH 782
+
+#define MT9V032_CHIP_VERSION 0x00
+#define MT9V032_CHIP_ID_REV1 0x1311
+#define MT9V032_CHIP_ID_REV3 0x1313
+#define MT9V032_ROW_START 0x01
+#define MT9V032_ROW_START_MIN 4
+#define MT9V032_ROW_START_DEF 10
+#define MT9V032_ROW_START_MAX 482
+#define MT9V032_COLUMN_START 0x02
+#define MT9V032_COLUMN_START_MIN 1
+#define MT9V032_COLUMN_START_DEF 2
+#define MT9V032_COLUMN_START_MAX 752
+#define MT9V032_WINDOW_HEIGHT 0x03
+#define MT9V032_WINDOW_HEIGHT_MIN 1
+#define MT9V032_WINDOW_HEIGHT_DEF 480
+#define MT9V032_WINDOW_HEIGHT_MAX 480
+#define MT9V032_WINDOW_WIDTH 0x04
+#define MT9V032_WINDOW_WIDTH_MIN 1
+#define MT9V032_WINDOW_WIDTH_DEF 752
+#define MT9V032_WINDOW_WIDTH_MAX 752
+#define MT9V032_HORIZONTAL_BLANKING 0x05
+#define MT9V032_HORIZONTAL_BLANKING_MIN 43
+#define MT9V032_HORIZONTAL_BLANKING_MAX 1023
+#define MT9V032_VERTICAL_BLANKING 0x06
+#define MT9V032_VERTICAL_BLANKING_MIN 4
+#define MT9V032_VERTICAL_BLANKING_MAX 3000
+#define MT9V032_CHIP_CONTROL 0x07
+#define MT9V032_CHIP_CONTROL_MASTER_MODE (1 << 3)
+#define MT9V032_CHIP_CONTROL_DOUT_ENABLE (1 << 7)
+#define MT9V032_CHIP_CONTROL_SEQUENTIAL (1 << 8)
+#define MT9V032_SHUTTER_WIDTH1 0x08
+#define MT9V032_SHUTTER_WIDTH2 0x09
+#define MT9V032_SHUTTER_WIDTH_CONTROL 0x0a
+#define MT9V032_TOTAL_SHUTTER_WIDTH 0x0b
+#define MT9V032_TOTAL_SHUTTER_WIDTH_MIN 1
+#define MT9V032_TOTAL_SHUTTER_WIDTH_DEF 480
+#define MT9V032_TOTAL_SHUTTER_WIDTH_MAX 32767
+#define MT9V032_RESET 0x0c
+#define MT9V032_READ_MODE 0x0d
+#define MT9V032_READ_MODE_ROW_BIN_MASK (3 << 0)
+#define MT9V032_READ_MODE_ROW_BIN_SHIFT 0
+#define MT9V032_READ_MODE_COLUMN_BIN_MASK (3 << 2)
+#define MT9V032_READ_MODE_COLUMN_BIN_SHIFT 2
+#define MT9V032_READ_MODE_ROW_FLIP (1 << 4)
+#define MT9V032_READ_MODE_COLUMN_FLIP (1 << 5)
+#define MT9V032_READ_MODE_DARK_COLUMNS (1 << 6)
+#define MT9V032_READ_MODE_DARK_ROWS (1 << 7)
+#define MT9V032_PIXEL_OPERATION_MODE 0x0f
+#define MT9V032_PIXEL_OPERATION_MODE_COLOR (1 << 2)
+#define MT9V032_PIXEL_OPERATION_MODE_HDR (1 << 6)
+#define MT9V032_ANALOG_GAIN 0x35
+#define MT9V032_ANALOG_GAIN_MIN 16
+#define MT9V032_ANALOG_GAIN_DEF 16
+#define MT9V032_ANALOG_GAIN_MAX 64
+#define MT9V032_MAX_ANALOG_GAIN 0x36
+#define MT9V032_MAX_ANALOG_GAIN_MAX 127
+#define MT9V032_FRAME_DARK_AVERAGE 0x42
+#define MT9V032_DARK_AVG_THRESH 0x46
+#define MT9V032_DARK_AVG_LOW_THRESH_MASK (255 << 0)
+#define MT9V032_DARK_AVG_LOW_THRESH_SHIFT 0
+#define MT9V032_DARK_AVG_HIGH_THRESH_MASK (255 << 8)
+#define MT9V032_DARK_AVG_HIGH_THRESH_SHIFT 8
+#define MT9V032_ROW_NOISE_CORR_CONTROL 0x70
+#define MT9V032_ROW_NOISE_CORR_ENABLE (1 << 5)
+#define MT9V032_ROW_NOISE_CORR_USE_BLK_AVG (1 << 7)
+#define MT9V032_PIXEL_CLOCK 0x74
+#define MT9V032_PIXEL_CLOCK_INV_LINE (1 << 0)
+#define MT9V032_PIXEL_CLOCK_INV_FRAME (1 << 1)
+#define MT9V032_PIXEL_CLOCK_XOR_LINE (1 << 2)
+#define MT9V032_PIXEL_CLOCK_CONT_LINE (1 << 3)
+#define MT9V032_PIXEL_CLOCK_INV_PXL_CLK (1 << 4)
+#define MT9V032_TEST_PATTERN 0x7f
+#define MT9V032_TEST_PATTERN_DATA_MASK (1023 << 0)
+#define MT9V032_TEST_PATTERN_DATA_SHIFT 0
+#define MT9V032_TEST_PATTERN_USE_DATA (1 << 10)
+#define MT9V032_TEST_PATTERN_GRAY_MASK (3 << 11)
+#define MT9V032_TEST_PATTERN_GRAY_NONE (0 << 11)
+#define MT9V032_TEST_PATTERN_GRAY_VERTICAL (1 << 11)
+#define MT9V032_TEST_PATTERN_GRAY_HORIZONTAL (2 << 11)
+#define MT9V032_TEST_PATTERN_GRAY_DIAGONAL (3 << 11)
+#define MT9V032_TEST_PATTERN_ENABLE (1 << 13)
+#define MT9V032_TEST_PATTERN_FLIP (1 << 14)
+#define MT9V032_AEC_AGC_ENABLE 0xaf
+#define MT9V032_AEC_ENABLE (1 << 0)
+#define MT9V032_AGC_ENABLE (1 << 1)
+#define MT9V032_THERMAL_INFO 0xc1
+
+struct mt9v032 {
+ struct v4l2_subdev subdev;
+ struct media_pad pad;
+
+ struct v4l2_mbus_framefmt format;
+ struct v4l2_rect crop;
+
+ struct v4l2_ctrl_handler ctrls;
+
+ struct mutex power_lock;
+ int power_count;
+
+ struct mt9v032_platform_data *pdata;
+ u16 chip_control;
+ u16 aec_agc;
+};
+
+static struct mt9v032 *to_mt9v032(struct v4l2_subdev *sd)
+{
+ return container_of(sd, struct mt9v032, subdev);
+}
+
+static int mt9v032_read(struct i2c_client *client, const u8 reg)
+{
+ s32 data = i2c_smbus_read_word_data(client, reg);
+ dev_dbg(&client->dev, "%s: read 0x%04x from 0x%02x\n", __func__,
+ swab16(data), reg);
+ return data < 0 ? data : swab16(data);
+}
+
+static int mt9v032_write(struct i2c_client *client, const u8 reg,
+ const u16 data)
+{
+ dev_dbg(&client->dev, "%s: writing 0x%04x to 0x%02x\n", __func__,
+ data, reg);
+ return i2c_smbus_write_word_data(client, reg, swab16(data));
+}
+
+static int mt9v032_set_chip_control(struct mt9v032 *mt9v032, u16 clear, u16 set)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&mt9v032->subdev);
+ u16 value = (mt9v032->chip_control & ~clear) | set;
+ int ret;
+
+ ret = mt9v032_write(client, MT9V032_CHIP_CONTROL, value);
+ if (ret < 0)
+ return ret;
+
+ mt9v032->chip_control = value;
+ return 0;
+}
+
+static int
+mt9v032_update_aec_agc(struct mt9v032 *mt9v032, u16 which, int enable)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&mt9v032->subdev);
+ u16 value = mt9v032->aec_agc;
+ int ret;
+
+ if (enable)
+ value |= which;
+ else
+ value &= ~which;
+
+ ret = mt9v032_write(client, MT9V032_AEC_AGC_ENABLE, value);
+ if (ret < 0)
+ return ret;
+
+ mt9v032->aec_agc = value;
+ return 0;
+}
+
+static int mt9v032_power_on(struct mt9v032 *mt9v032)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&mt9v032->subdev);
+ int ret;
+
+ if (mt9v032->pdata->set_clock) {
+ mt9v032->pdata->set_clock(&mt9v032->subdev, 25000000);
+ udelay(1);
+ }
+
+ /* Reset the chip and stop data read out */
+ ret = mt9v032_write(client, MT9V032_RESET, 1);
+ if (ret < 0)
+ return ret;
+
+ ret = mt9v032_write(client, MT9V032_RESET, 0);
+ if (ret < 0)
+ return ret;
+
+ return mt9v032_write(client, MT9V032_CHIP_CONTROL, 0);
+}
+
+static void mt9v032_power_off(struct mt9v032 *mt9v032)
+{
+ if (mt9v032->pdata->set_clock)
+ mt9v032->pdata->set_clock(&mt9v032->subdev, 0);
+}
+
+static int __mt9v032_set_power(struct mt9v032 *mt9v032, bool on)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(&mt9v032->subdev);
+ int ret;
+
+ if (!on) {
+ mt9v032_power_off(mt9v032);
+ return 0;
+ }
+
+ ret = mt9v032_power_on(mt9v032);
+ if (ret < 0)
+ return ret;
+
+ /* Configure the pixel clock polarity */
+ if (mt9v032->pdata && mt9v032->pdata->clk_pol) {
+ ret = mt9v032_write(client, MT9V032_PIXEL_CLOCK,
+ MT9V032_PIXEL_CLOCK_INV_PXL_CLK);
+ if (ret < 0)
+ return ret;
+ }
+
+ /* Disable the noise correction algorithm and restore the controls. */
+ ret = mt9v032_write(client, MT9V032_ROW_NOISE_CORR_CONTROL, 0);
+ if (ret < 0)
+ return ret;
+
+ return v4l2_ctrl_handler_setup(&mt9v032->ctrls);
+}
+
+/* -----------------------------------------------------------------------------
+ * V4L2 subdev video operations
+ */
+
+static struct v4l2_mbus_framefmt *
+__mt9v032_get_pad_format(struct mt9v032 *mt9v032, struct v4l2_subdev_fh *fh,
+ unsigned int pad, enum v4l2_subdev_format_whence which)
+{
+ switch (which) {
+ case V4L2_SUBDEV_FORMAT_TRY:
+ return v4l2_subdev_get_try_format(fh, pad);
+ case V4L2_SUBDEV_FORMAT_ACTIVE:
+ return &mt9v032->format;
+ default:
+ return NULL;
+ }
+}
+
+static struct v4l2_rect *
+__mt9v032_get_pad_crop(struct mt9v032 *mt9v032, struct v4l2_subdev_fh *fh,
+ unsigned int pad, enum v4l2_subdev_format_whence which)
+{
+ switch (which) {
+ case V4L2_SUBDEV_FORMAT_TRY:
+ return v4l2_subdev_get_try_crop(fh, pad);
+ case V4L2_SUBDEV_FORMAT_ACTIVE:
+ return &mt9v032->crop;
+ default:
+ return NULL;
+ }
+}
+
+static int mt9v032_s_stream(struct v4l2_subdev *subdev, int enable)
+{
+ const u16 mode = MT9V032_CHIP_CONTROL_MASTER_MODE
+ | MT9V032_CHIP_CONTROL_DOUT_ENABLE
+ | MT9V032_CHIP_CONTROL_SEQUENTIAL;
+ struct i2c_client *client = v4l2_get_subdevdata(subdev);
+ struct mt9v032 *mt9v032 = to_mt9v032(subdev);
+ struct v4l2_mbus_framefmt *format = &mt9v032->format;
+ struct v4l2_rect *crop = &mt9v032->crop;
+ unsigned int hratio;
+ unsigned int vratio;
+ int ret;
+
+ if (!enable)
+ return mt9v032_set_chip_control(mt9v032, mode, 0);
+
+ /* Configure the window size and row/column bin */
+ hratio = DIV_ROUND_CLOSEST(crop->width, format->width);
+ vratio = DIV_ROUND_CLOSEST(crop->height, format->height);
+
+ ret = mt9v032_write(client, MT9V032_READ_MODE,
+ (hratio - 1) << MT9V032_READ_MODE_ROW_BIN_SHIFT |
+ (vratio - 1) << MT9V032_READ_MODE_COLUMN_BIN_SHIFT);
+ if (ret < 0)
+ return ret;
+
+ ret = mt9v032_write(client, MT9V032_COLUMN_START, crop->left);
+ if (ret < 0)
+ return ret;
+
+ ret = mt9v032_write(client, MT9V032_ROW_START, crop->top);
+ if (ret < 0)
+ return ret;
+
+ ret = mt9v032_write(client, MT9V032_WINDOW_WIDTH, crop->width);
+ if (ret < 0)
+ return ret;
+
+ ret = mt9v032_write(client, MT9V032_WINDOW_HEIGHT, crop->height);
+ if (ret < 0)
+ return ret;
+
+ ret = mt9v032_write(client, MT9V032_HORIZONTAL_BLANKING,
+ max(43, 660 - crop->width));
+ if (ret < 0)
+ return ret;
+
+ /* Switch to master "normal" mode */
+ return mt9v032_set_chip_control(mt9v032, 0, mode);
+}
+
+static int mt9v032_enum_mbus_code(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_fh *fh,
+ struct v4l2_subdev_mbus_code_enum *code)
+{
+ if (code->index > 0)
+ return -EINVAL;
+
+ code->code = V4L2_MBUS_FMT_SGRBG10_1X10;
+ return 0;
+}
+
+static int mt9v032_enum_frame_size(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_fh *fh,
+ struct v4l2_subdev_frame_size_enum *fse)
+{
+ if (fse->index >= 8 || fse->code != V4L2_MBUS_FMT_SGRBG10_1X10)
+ return -EINVAL;
+
+ fse->min_width = MT9V032_WINDOW_WIDTH_DEF / fse->index;
+ fse->max_width = fse->min_width;
+ fse->min_height = MT9V032_WINDOW_HEIGHT_DEF / fse->index;
+ fse->max_height = fse->min_height;
+
+ return 0;
+}
+
+static int mt9v032_get_format(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_fh *fh,
+ struct v4l2_subdev_format *format)
+{
+ struct mt9v032 *mt9v032 = to_mt9v032(subdev);
+
+ format->format = *__mt9v032_get_pad_format(mt9v032, fh, format->pad,
+ format->which);
+ return 0;
+}
+
+static int mt9v032_set_format(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_fh *fh,
+ struct v4l2_subdev_format *format)
+{
+ struct mt9v032 *mt9v032 = to_mt9v032(subdev);
+ struct v4l2_mbus_framefmt *__format;
+ struct v4l2_rect *__crop;
+ unsigned int width;
+ unsigned int height;
+ unsigned int hratio;
+ unsigned int vratio;
+
+ __crop = __mt9v032_get_pad_crop(mt9v032, fh, format->pad,
+ format->which);
+
+ /* Clamp the width and height to avoid dividing by zero. */
+ width = clamp_t(unsigned int, ALIGN(format->format.width, 2),
+ max(__crop->width / 8, MT9V032_WINDOW_WIDTH_MIN),
+ __crop->width);
+ height = clamp_t(unsigned int, ALIGN(format->format.height, 2),
+ max(__crop->height / 8, MT9V032_WINDOW_HEIGHT_MIN),
+ __crop->height);
+
+ hratio = DIV_ROUND_CLOSEST(__crop->width, width);
+ vratio = DIV_ROUND_CLOSEST(__crop->height, height);
+
+ __format = __mt9v032_get_pad_format(mt9v032, fh, format->pad,
+ format->which);
+ __format->width = __crop->width / hratio;
+ __format->height = __crop->height / vratio;
+
+ format->format = *__format;
+
+ return 0;
+}
+
+static int mt9v032_get_crop(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_fh *fh,
+ struct v4l2_subdev_crop *crop)
+{
+ struct mt9v032 *mt9v032 = to_mt9v032(subdev);
+
+ crop->rect = *__mt9v032_get_pad_crop(mt9v032, fh, crop->pad,
+ crop->which);
+ return 0;
+}
+
+static int mt9v032_set_crop(struct v4l2_subdev *subdev,
+ struct v4l2_subdev_fh *fh,
+ struct v4l2_subdev_crop *crop)
+{
+ struct mt9v032 *mt9v032 = to_mt9v032(subdev);
+ struct v4l2_mbus_framefmt *__format;
+ struct v4l2_rect *__crop;
+ struct v4l2_rect rect;
+
+ /* Clamp the crop rectangle boundaries and align them to a multiple of 2
+ * pixels.
+ */
+ rect.left = clamp(ALIGN(crop->rect.left, 2),
+ MT9V032_COLUMN_START_MIN,
+ MT9V032_COLUMN_START_MAX);
+ rect.top = clamp(ALIGN(crop->rect.top, 2),
+ MT9V032_ROW_START_MIN,
+ MT9V032_ROW_START_MAX);
+ rect.width = clamp(ALIGN(crop->rect.width, 2),
+ MT9V032_WINDOW_WIDTH_MIN,
+ MT9V032_WINDOW_WIDTH_MAX);
+ rect.height = clamp(ALIGN(crop->rect.height, 2),
+ MT9V032_WINDOW_HEIGHT_MIN,
+ MT9V032_WINDOW_HEIGHT_MAX);
+
+ rect.width = min(rect.width, MT9V032_PIXEL_ARRAY_WIDTH - rect.left);
+ rect.height = min(rect.height, MT9V032_PIXEL_ARRAY_HEIGHT - rect.top);
+
+ __crop = __mt9v032_get_pad_crop(mt9v032, fh, crop->pad, crop->which);
+
+ if (rect.width != __crop->width || rect.height != __crop->height) {
+ /* Reset the output image size if the crop rectangle size has
+ * been modified.
+ */
+ __format = __mt9v032_get_pad_format(mt9v032, fh, crop->pad,
+ crop->which);
+ __format->width = rect.width;
+ __format->height = rect.height;
+ }
+
+ *__crop = rect;
+ crop->rect = rect;
+
+ return 0;
+}
+
+/* -----------------------------------------------------------------------------
+ * V4L2 subdev control operations
+ */
+
+#define V4L2_CID_TEST_PATTERN (V4L2_CID_USER_BASE | 0x1001)
+
+static int mt9v032_s_ctrl(struct v4l2_ctrl *ctrl)
+{
+ struct mt9v032 *mt9v032 =
+ container_of(ctrl->handler, struct mt9v032, ctrls);
+ struct i2c_client *client = v4l2_get_subdevdata(&mt9v032->subdev);
+ u16 data;
+
+ switch (ctrl->id) {
+ case V4L2_CID_AUTOGAIN:
+ return mt9v032_update_aec_agc(mt9v032, MT9V032_AGC_ENABLE,
+ ctrl->val);
+
+ case V4L2_CID_GAIN:
+ return mt9v032_write(client, MT9V032_ANALOG_GAIN, ctrl->val);
+
+ case V4L2_CID_EXPOSURE_AUTO:
+ return mt9v032_update_aec_agc(mt9v032, MT9V032_AEC_ENABLE,
+ ctrl->val);
+
+ case V4L2_CID_EXPOSURE:
+ return mt9v032_write(client, MT9V032_TOTAL_SHUTTER_WIDTH,
+ ctrl->val);
+
+ case V4L2_CID_TEST_PATTERN:
+ switch (ctrl->val) {
+ case 0:
+ data = 0;
+ break;
+ case 1:
+ data = MT9V032_TEST_PATTERN_GRAY_VERTICAL
+ | MT9V032_TEST_PATTERN_ENABLE;
+ break;
+ case 2:
+ data = MT9V032_TEST_PATTERN_GRAY_HORIZONTAL
+ | MT9V032_TEST_PATTERN_ENABLE;
+ break;
+ case 3:
+ data = MT9V032_TEST_PATTERN_GRAY_DIAGONAL
+ | MT9V032_TEST_PATTERN_ENABLE;
+ break;
+ default:
+ data = (ctrl->val << MT9V032_TEST_PATTERN_DATA_SHIFT)
+ | MT9V032_TEST_PATTERN_USE_DATA
+ | MT9V032_TEST_PATTERN_ENABLE
+ | MT9V032_TEST_PATTERN_FLIP;
+ break;
+ }
+
+ return mt9v032_write(client, MT9V032_TEST_PATTERN, data);
+ }
+
+ return 0;
+}
+
+static struct v4l2_ctrl_ops mt9v032_ctrl_ops = {
+ .s_ctrl = mt9v032_s_ctrl,
+};
+
+static const struct v4l2_ctrl_config mt9v032_ctrls[] = {
+ {
+ .ops = &mt9v032_ctrl_ops,
+ .id = V4L2_CID_TEST_PATTERN,
+ .type = V4L2_CTRL_TYPE_INTEGER,
+ .name = "Test pattern",
+ .min = 0,
+ .max = 1023,
+ .step = 1,
+ .def = 0,
+ .flags = 0,
+ }
+};
+
+/* -----------------------------------------------------------------------------
+ * V4L2 subdev core operations
+ */
+
+static int mt9v032_set_power(struct v4l2_subdev *subdev, int on)
+{
+ struct mt9v032 *mt9v032 = to_mt9v032(subdev);
+ int ret = 0;
+
+ mutex_lock(&mt9v032->power_lock);
+
+ /* If the power count is modified from 0 to != 0 or from != 0 to 0,
+ * update the power state.
+ */
+ if (mt9v032->power_count == !on) {
+ ret = __mt9v032_set_power(mt9v032, !!on);
+ if (ret < 0)
+ goto done;
+ }
+
+ /* Update the power count. */
+ mt9v032->power_count += on ? 1 : -1;
+ WARN_ON(mt9v032->power_count < 0);
+
+done:
+ mutex_unlock(&mt9v032->power_lock);
+ return ret;
+}
+
+/* -----------------------------------------------------------------------------
+ * V4L2 subdev internal operations
+ */
+
+static int mt9v032_registered(struct v4l2_subdev *subdev)
+{
+ struct i2c_client *client = v4l2_get_subdevdata(subdev);
+ struct mt9v032 *mt9v032 = to_mt9v032(subdev);
+ s32 data;
+ int ret;
+
+ dev_info(&client->dev, "Probing MT9V032 at address 0x%02x\n",
+ client->addr);
+
+ ret = mt9v032_power_on(mt9v032);
+ if (ret < 0) {
+ dev_err(&client->dev, "MT9V032 power up failed\n");
+ return ret;
+ }
+
+ /* Read and check the sensor version */
+ data = mt9v032_read(client, MT9V032_CHIP_VERSION);
+ if (data != MT9V032_CHIP_ID_REV1 && data != MT9V032_CHIP_ID_REV3) {
+ dev_err(&client->dev, "MT9V032 not detected, wrong version "
+ "0x%04x\n", data);
+ return -ENODEV;
+ }
+
+ mt9v032_power_off(mt9v032);
+
+ dev_info(&client->dev, "MT9V032 detected at address 0x%02x\n",
+ client->addr);
+
+ return ret;
+}
+
+static int mt9v032_open(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh)
+{
+ struct v4l2_mbus_framefmt *format;
+ struct v4l2_rect *crop;
+
+ crop = v4l2_subdev_get_try_crop(fh, 0);
+ crop->left = MT9V032_COLUMN_START_DEF;
+ crop->top = MT9V032_ROW_START_DEF;
+ crop->width = MT9V032_WINDOW_WIDTH_DEF;
+ crop->height = MT9V032_WINDOW_HEIGHT_DEF;
+
+ format = v4l2_subdev_get_try_format(fh, 0);
+ format->code = V4L2_MBUS_FMT_SGRBG10_1X10;
+ format->width = MT9V032_WINDOW_WIDTH_DEF;
+ format->height = MT9V032_WINDOW_HEIGHT_DEF;
+ format->field = V4L2_FIELD_NONE;
+ format->colorspace = V4L2_COLORSPACE_SRGB;
+
+ return mt9v032_set_power(subdev, 1);
+}
+
+static int mt9v032_close(struct v4l2_subdev *subdev, struct v4l2_subdev_fh *fh)
+{
+ return mt9v032_set_power(subdev, 0);
+}
+
+static struct v4l2_subdev_core_ops mt9v032_subdev_core_ops = {
+ .s_power = mt9v032_set_power,
+};
+
+static struct v4l2_subdev_video_ops mt9v032_subdev_video_ops = {
+ .s_stream = mt9v032_s_stream,
+};
+
+static struct v4l2_subdev_pad_ops mt9v032_subdev_pad_ops = {
+ .enum_mbus_code = mt9v032_enum_mbus_code,
+ .enum_frame_size = mt9v032_enum_frame_size,
+ .get_fmt = mt9v032_get_format,
+ .set_fmt = mt9v032_set_format,
+ .get_crop = mt9v032_get_crop,
+ .set_crop = mt9v032_set_crop,
+};
+
+static struct v4l2_subdev_ops mt9v032_subdev_ops = {
+ .core = &mt9v032_subdev_core_ops,
+ .video = &mt9v032_subdev_video_ops,
+ .pad = &mt9v032_subdev_pad_ops,
+};
+
+static const struct v4l2_subdev_internal_ops mt9v032_subdev_internal_ops = {
+ .registered = mt9v032_registered,
+ .open = mt9v032_open,
+ .close = mt9v032_close,
+};
+
+/* -----------------------------------------------------------------------------
+ * Driver initialization and probing
+ */
+
+static int mt9v032_probe(struct i2c_client *client,
+ const struct i2c_device_id *did)
+{
+ struct mt9v032 *mt9v032;
+ unsigned int i;
+ int ret;
+
+ if (!i2c_check_functionality(client->adapter,
+ I2C_FUNC_SMBUS_WORD_DATA)) {
+ dev_warn(&client->adapter->dev,
+ "I2C-Adapter doesn't support I2C_FUNC_SMBUS_WORD\n");
+ return -EIO;
+ }
+
+ mt9v032 = kzalloc(sizeof(*mt9v032), GFP_KERNEL);
+ if (!mt9v032)
+ return -ENOMEM;
+
+ mutex_init(&mt9v032->power_lock);
+ mt9v032->pdata = client->dev.platform_data;
+
+ v4l2_ctrl_handler_init(&mt9v032->ctrls, ARRAY_SIZE(mt9v032_ctrls) + 4);
+
+ v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
+ V4L2_CID_AUTOGAIN, 0, 1, 1, 1);
+ v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
+ V4L2_CID_GAIN, MT9V032_ANALOG_GAIN_MIN,
+ MT9V032_ANALOG_GAIN_MAX, 1, MT9V032_ANALOG_GAIN_DEF);
+ v4l2_ctrl_new_std_menu(&mt9v032->ctrls, &mt9v032_ctrl_ops,
+ V4L2_CID_EXPOSURE_AUTO, V4L2_EXPOSURE_MANUAL, 0,
+ V4L2_EXPOSURE_AUTO);
+ v4l2_ctrl_new_std(&mt9v032->ctrls, &mt9v032_ctrl_ops,
+ V4L2_CID_EXPOSURE, MT9V032_TOTAL_SHUTTER_WIDTH_MIN,
+ MT9V032_TOTAL_SHUTTER_WIDTH_MAX, 1,
+ MT9V032_TOTAL_SHUTTER_WIDTH_DEF);
+
+ for (i = 0; i < ARRAY_SIZE(mt9v032_ctrls); ++i)
+ v4l2_ctrl_new_custom(&mt9v032->ctrls, &mt9v032_ctrls[i], NULL);
+
+ mt9v032->subdev.ctrl_handler = &mt9v032->ctrls;
+
+ if (mt9v032->ctrls.error)
+ printk(KERN_INFO "%s: control initialization error %d\n",
+ __func__, mt9v032->ctrls.error);
+
+ mt9v032->crop.left = MT9V032_COLUMN_START_DEF;
+ mt9v032->crop.top = MT9V032_ROW_START_DEF;
+ mt9v032->crop.width = MT9V032_WINDOW_WIDTH_DEF;
+ mt9v032->crop.height = MT9V032_WINDOW_HEIGHT_DEF;
+
+ mt9v032->format.code = V4L2_MBUS_FMT_SGRBG10_1X10;
+ mt9v032->format.width = MT9V032_WINDOW_WIDTH_DEF;
+ mt9v032->format.height = MT9V032_WINDOW_HEIGHT_DEF;
+ mt9v032->format.field = V4L2_FIELD_NONE;
+ mt9v032->format.colorspace = V4L2_COLORSPACE_SRGB;
+
+ mt9v032->aec_agc = MT9V032_AEC_ENABLE | MT9V032_AGC_ENABLE;
+
+ v4l2_i2c_subdev_init(&mt9v032->subdev, client, &mt9v032_subdev_ops);
+ mt9v032->subdev.internal_ops = &mt9v032_subdev_internal_ops;
+ mt9v032->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
+
+ mt9v032->pad.flags = MEDIA_PAD_FL_SOURCE;
+ ret = media_entity_init(&mt9v032->subdev.entity, 1, &mt9v032->pad, 0);
+ if (ret < 0)
+ kfree(mt9v032);
+
+ return ret;
+}
+
+static int mt9v032_remove(struct i2c_client *client)
+{
+ struct v4l2_subdev *subdev = i2c_get_clientdata(client);
+ struct mt9v032 *mt9v032 = to_mt9v032(subdev);
+
+ v4l2_device_unregister_subdev(subdev);
+ media_entity_cleanup(&subdev->entity);
+ kfree(mt9v032);
+ return 0;
+}
+
+static const struct i2c_device_id mt9v032_id[] = {
+ { "mt9v032", 0 },
+ { }
+};
+MODULE_DEVICE_TABLE(i2c, mt9v032_id);
+
+static struct i2c_driver mt9v032_driver = {
+ .driver = {
+ .name = "mt9v032",
+ },
+ .probe = mt9v032_probe,
+ .remove = mt9v032_remove,
+ .id_table = mt9v032_id,
+};
+
+static int __init mt9v032_init(void)
+{
+ return i2c_add_driver(&mt9v032_driver);
+}
+
+static void __exit mt9v032_exit(void)
+{
+ i2c_del_driver(&mt9v032_driver);
+}
+
+module_init(mt9v032_init);
+module_exit(mt9v032_exit);
+
+MODULE_DESCRIPTION("Aptina MT9V032 Camera driver");
+MODULE_AUTHOR("Laurent Pinchart <laurent.pinchart@ideasonboard.com>");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/mx3_camera.c b/drivers/media/video/mx3_camera.c
index 502e2a4..c7680eb 100644
--- a/drivers/media/video/mx3_camera.c
+++ b/drivers/media/video/mx3_camera.c
@@ -400,6 +400,35 @@
return 0;
}
+static int mx3_stop_streaming(struct vb2_queue *q)
+{
+ struct soc_camera_device *icd = soc_camera_from_vb2q(q);
+ struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
+ struct mx3_camera_dev *mx3_cam = ici->priv;
+ struct idmac_channel *ichan = mx3_cam->idmac_channel[0];
+ struct dma_chan *chan;
+ struct mx3_camera_buffer *buf, *tmp;
+ unsigned long flags;
+
+ if (ichan) {
+ chan = &ichan->dma_chan;
+ chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
+ }
+
+ spin_lock_irqsave(&mx3_cam->lock, flags);
+
+ mx3_cam->active = NULL;
+
+ list_for_each_entry_safe(buf, tmp, &mx3_cam->capture, queue) {
+ buf->state = CSI_BUF_NEEDS_INIT;
+ list_del_init(&buf->queue);
+ }
+
+ spin_unlock_irqrestore(&mx3_cam->lock, flags);
+
+ return 0;
+}
+
static struct vb2_ops mx3_videobuf_ops = {
.queue_setup = mx3_videobuf_setup,
.buf_prepare = mx3_videobuf_prepare,
@@ -408,6 +437,7 @@
.buf_init = mx3_videobuf_init,
.wait_prepare = soc_camera_unlock,
.wait_finish = soc_camera_lock,
+ .stop_streaming = mx3_stop_streaming,
};
static int mx3_camera_init_videobuf(struct vb2_queue *q,
@@ -658,8 +688,8 @@
fmt = soc_mbus_get_fmtdesc(code);
if (!fmt) {
- dev_err(icd->dev.parent,
- "Invalid format code #%u: %d\n", idx, code);
+ dev_warn(icd->dev.parent,
+ "Unsupported format code #%u: %d\n", idx, code);
return 0;
}
@@ -712,13 +742,9 @@
static void configure_geometry(struct mx3_camera_dev *mx3_cam,
unsigned int width, unsigned int height,
- enum v4l2_mbus_pixelcode code)
+ const struct soc_mbus_pixelfmt *fmt)
{
u32 ctrl, width_field, height_field;
- const struct soc_mbus_pixelfmt *fmt;
-
- fmt = soc_mbus_get_fmtdesc(code);
- BUG_ON(!fmt);
if (fourcc_to_ipu_pix(fmt->fourcc) == IPU_PIX_FMT_GENERIC) {
/*
@@ -726,8 +752,10 @@
* the width parameter count the number of samples to
* capture to complete the whole image width.
*/
- width *= soc_mbus_samples_per_pixel(fmt);
- BUG_ON(width < 0);
+ unsigned int num, den;
+ int ret = soc_mbus_samples_per_pixel(fmt, &num, &den);
+ BUG_ON(ret < 0);
+ width = width * num / den;
}
/* Setup frame size - this cannot be changed on-the-fly... */
@@ -774,8 +802,8 @@
*/
static inline void stride_align(__u32 *width)
{
- if (((*width + 7) & ~7) < 4096)
- *width = (*width + 7) & ~7;
+ if (ALIGN(*width, 8) < 4096)
+ *width = ALIGN(*width, 8);
else
*width = *width & ~7;
}
@@ -801,11 +829,14 @@
if (ret < 0)
return ret;
- /* The capture device might have changed its output */
+ /* The capture device might have changed its output sizes */
ret = v4l2_subdev_call(sd, video, g_mbus_fmt, &mf);
if (ret < 0)
return ret;
+ if (mf.code != icd->current_fmt->code)
+ return -EINVAL;
+
if (mf.width & 7) {
/* Ouch! We can only handle 8-byte aligned width... */
stride_align(&mf.width);
@@ -815,7 +846,8 @@
}
if (mf.width != icd->user_width || mf.height != icd->user_height)
- configure_geometry(mx3_cam, mf.width, mf.height, mf.code);
+ configure_geometry(mx3_cam, mf.width, mf.height,
+ icd->current_fmt->host_fmt);
dev_dbg(icd->dev.parent, "Sensor cropped %dx%d\n",
mf.width, mf.height);
@@ -853,7 +885,7 @@
* mxc_v4l2_s_fmt()
*/
- configure_geometry(mx3_cam, pix->width, pix->height, xlate->code);
+ configure_geometry(mx3_cam, pix->width, pix->height, xlate->host_fmt);
mf.width = pix->width;
mf.height = pix->height;
diff --git a/drivers/media/video/omap/omap_vout.c b/drivers/media/video/omap/omap_vout.c
index d4fe7bc..4ada9be 100644
--- a/drivers/media/video/omap/omap_vout.c
+++ b/drivers/media/video/omap/omap_vout.c
@@ -47,7 +47,7 @@
#include <plat/dma.h>
#include <plat/vram.h>
#include <plat/vrfb.h>
-#include <plat/display.h>
+#include <video/omapdss.h>
#include "omap_voutlib.h"
#include "omap_voutdef.h"
diff --git a/drivers/media/video/omap/omap_voutdef.h b/drivers/media/video/omap/omap_voutdef.h
index ea3a047..659497b 100644
--- a/drivers/media/video/omap/omap_voutdef.h
+++ b/drivers/media/video/omap/omap_voutdef.h
@@ -11,7 +11,7 @@
#ifndef OMAP_VOUTDEF_H
#define OMAP_VOUTDEF_H
-#include <plat/display.h>
+#include <video/omapdss.h>
#define YUYV_BPP 2
#define RGB565_BPP 2
diff --git a/drivers/media/video/omap1_camera.c b/drivers/media/video/omap1_camera.c
index 5954b93..e7cfc85 100644
--- a/drivers/media/video/omap1_camera.c
+++ b/drivers/media/video/omap1_camera.c
@@ -990,63 +990,80 @@
}
/* Duplicate standard formats based on host capability of byte swapping */
-static const struct soc_mbus_pixelfmt omap1_cam_formats[] = {
- [V4L2_MBUS_FMT_UYVY8_2X8] = {
+static const struct soc_mbus_lookup omap1_cam_formats[] = {
+{
+ .code = V4L2_MBUS_FMT_UYVY8_2X8,
+ .fmt = {
.fourcc = V4L2_PIX_FMT_YUYV,
.name = "YUYV",
.bits_per_sample = 8,
.packing = SOC_MBUS_PACKING_2X8_PADHI,
.order = SOC_MBUS_ORDER_BE,
},
- [V4L2_MBUS_FMT_VYUY8_2X8] = {
+}, {
+ .code = V4L2_MBUS_FMT_VYUY8_2X8,
+ .fmt = {
.fourcc = V4L2_PIX_FMT_YVYU,
.name = "YVYU",
.bits_per_sample = 8,
.packing = SOC_MBUS_PACKING_2X8_PADHI,
.order = SOC_MBUS_ORDER_BE,
},
- [V4L2_MBUS_FMT_YUYV8_2X8] = {
+}, {
+ .code = V4L2_MBUS_FMT_YUYV8_2X8,
+ .fmt = {
.fourcc = V4L2_PIX_FMT_UYVY,
.name = "UYVY",
.bits_per_sample = 8,
.packing = SOC_MBUS_PACKING_2X8_PADHI,
.order = SOC_MBUS_ORDER_BE,
},
- [V4L2_MBUS_FMT_YVYU8_2X8] = {
+}, {
+ .code = V4L2_MBUS_FMT_YVYU8_2X8,
+ .fmt = {
.fourcc = V4L2_PIX_FMT_VYUY,
.name = "VYUY",
.bits_per_sample = 8,
.packing = SOC_MBUS_PACKING_2X8_PADHI,
.order = SOC_MBUS_ORDER_BE,
},
- [V4L2_MBUS_FMT_RGB555_2X8_PADHI_BE] = {
+}, {
+ .code = V4L2_MBUS_FMT_RGB555_2X8_PADHI_BE,
+ .fmt = {
.fourcc = V4L2_PIX_FMT_RGB555,
.name = "RGB555",
.bits_per_sample = 8,
.packing = SOC_MBUS_PACKING_2X8_PADHI,
.order = SOC_MBUS_ORDER_BE,
},
- [V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE] = {
+}, {
+ .code = V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE,
+ .fmt = {
.fourcc = V4L2_PIX_FMT_RGB555X,
.name = "RGB555X",
.bits_per_sample = 8,
.packing = SOC_MBUS_PACKING_2X8_PADHI,
.order = SOC_MBUS_ORDER_BE,
},
- [V4L2_MBUS_FMT_RGB565_2X8_BE] = {
+}, {
+ .code = V4L2_MBUS_FMT_RGB565_2X8_BE,
+ .fmt = {
.fourcc = V4L2_PIX_FMT_RGB565,
.name = "RGB565",
.bits_per_sample = 8,
.packing = SOC_MBUS_PACKING_2X8_PADHI,
.order = SOC_MBUS_ORDER_BE,
},
- [V4L2_MBUS_FMT_RGB565_2X8_LE] = {
+}, {
+ .code = V4L2_MBUS_FMT_RGB565_2X8_LE,
+ .fmt = {
.fourcc = V4L2_PIX_FMT_RGB565X,
.name = "RGB565X",
.bits_per_sample = 8,
.packing = SOC_MBUS_PACKING_2X8_PADHI,
.order = SOC_MBUS_ORDER_BE,
},
+},
};
static int omap1_cam_get_formats(struct soc_camera_device *icd,
@@ -1065,7 +1082,7 @@
fmt = soc_mbus_get_fmtdesc(code);
if (!fmt) {
- dev_err(dev, "%s: invalid format code #%d: %d\n", __func__,
+ dev_warn(dev, "%s: unsupported format code #%d: %d\n", __func__,
idx, code);
return 0;
}
@@ -1085,12 +1102,14 @@
case V4L2_MBUS_FMT_RGB565_2X8_LE:
formats++;
if (xlate) {
- xlate->host_fmt = &omap1_cam_formats[code];
+ xlate->host_fmt = soc_mbus_find_fmtdesc(code,
+ omap1_cam_formats,
+ ARRAY_SIZE(omap1_cam_formats));
xlate->code = code;
xlate++;
dev_dbg(dev,
"%s: providing format %s as byte swapped code #%d\n",
- __func__, omap1_cam_formats[code].name, code);
+ __func__, xlate->host_fmt->name, code);
}
default:
if (xlate)
diff --git a/drivers/media/video/pvrusb2/pvrusb2-std.c b/drivers/media/video/pvrusb2/pvrusb2-std.c
index ca9f83a..453627b 100644
--- a/drivers/media/video/pvrusb2/pvrusb2-std.c
+++ b/drivers/media/video/pvrusb2/pvrusb2-std.c
@@ -278,12 +278,10 @@
}
};
-#define generic_standards_cnt ARRAY_SIZE(generic_standards)
-
static struct v4l2_standard *match_std(v4l2_std_id id)
{
unsigned int idx;
- for (idx = 0; idx < generic_standards_cnt; idx++) {
+ for (idx = 0; idx < ARRAY_SIZE(generic_standards); idx++) {
if (generic_standards[idx].id & id) {
return generic_standards + idx;
}
@@ -370,7 +368,11 @@
stddefs = kzalloc(sizeof(struct v4l2_standard) * std_cnt,
GFP_KERNEL);
- for (idx = 0; idx < std_cnt; idx++) stddefs[idx].index = idx;
+ if (!stddefs)
+ return NULL;
+
+ for (idx = 0; idx < std_cnt; idx++)
+ stddefs[idx].index = idx;
idx = 0;
diff --git a/drivers/media/video/pwc/pwc-if.c b/drivers/media/video/pwc/pwc-if.c
index 780af5f..356cd42 100644
--- a/drivers/media/video/pwc/pwc-if.c
+++ b/drivers/media/video/pwc/pwc-if.c
@@ -1850,7 +1850,6 @@
} else {
/* Device is closed, so we can safely unregister it */
PWC_DEBUG_PROBE("Unregistering video device in disconnect().\n");
- pwc_cleanup(pdev);
disconnect_out:
/* search device_hint[] table if we occupy a slot, by any chance */
@@ -1860,6 +1859,7 @@
}
mutex_unlock(&pdev->modlock);
+ pwc_cleanup(pdev);
}
diff --git a/drivers/media/video/pwc/pwc-v4l.c b/drivers/media/video/pwc/pwc-v4l.c
index aa87e46..f85c512 100644
--- a/drivers/media/video/pwc/pwc-v4l.c
+++ b/drivers/media/video/pwc/pwc-v4l.c
@@ -379,8 +379,27 @@
static int pwc_queryctrl(struct file *file, void *fh, struct v4l2_queryctrl *c)
{
- int i;
+ int i, idx;
+ u32 id;
+ id = c->id;
+ if (id & V4L2_CTRL_FLAG_NEXT_CTRL) {
+ id &= V4L2_CTRL_ID_MASK;
+ id++;
+ idx = -1;
+ for (i = 0; i < ARRAY_SIZE(pwc_controls); i++) {
+ if (pwc_controls[i].id < id)
+ continue;
+ if (idx >= 0
+ && pwc_controls[i].id > pwc_controls[idx].id)
+ continue;
+ idx = i;
+ }
+ if (idx < 0)
+ return -EINVAL;
+ memcpy(c, &pwc_controls[idx], sizeof pwc_controls[0]);
+ return 0;
+ }
for (i = 0; i < sizeof(pwc_controls) / sizeof(struct v4l2_queryctrl); i++) {
if (pwc_controls[i].id == c->id) {
PWC_DEBUG_IOCTL("ioctl(VIDIOC_QUERYCTRL) found\n");
diff --git a/drivers/media/video/pxa_camera.c b/drivers/media/video/pxa_camera.c
index c1ee09a..b42bfa5 100644
--- a/drivers/media/video/pxa_camera.c
+++ b/drivers/media/video/pxa_camera.c
@@ -1155,15 +1155,11 @@
struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
struct pxa_camera_dev *pcdev = ici->priv;
unsigned long bus_flags, camera_flags, common_flags;
- const struct soc_mbus_pixelfmt *fmt;
int ret;
struct pxa_cam *cam = icd->host_priv;
- fmt = soc_mbus_get_fmtdesc(icd->current_fmt->code);
- if (!fmt)
- return -EINVAL;
-
- ret = test_platform_param(pcdev, fmt->bits_per_sample, &bus_flags);
+ ret = test_platform_param(pcdev, icd->current_fmt->host_fmt->bits_per_sample,
+ &bus_flags);
if (ret < 0)
return ret;
diff --git a/drivers/media/video/s2255drv.c b/drivers/media/video/s2255drv.c
index 561909b..5b9dce8 100644
--- a/drivers/media/video/s2255drv.c
+++ b/drivers/media/video/s2255drv.c
@@ -394,12 +394,17 @@
/* start video number */
static int video_nr = -1; /* /dev/videoN, -1 for autodetect */
+/* Enable jpeg capture. */
+static int jpeg_enable = 1;
+
module_param(debug, int, 0644);
MODULE_PARM_DESC(debug, "Debug level(0-100) default 0");
module_param(vid_limit, int, 0644);
MODULE_PARM_DESC(vid_limit, "video memory limit(Mb)");
module_param(video_nr, int, 0644);
MODULE_PARM_DESC(video_nr, "start video minor(-1 default autodetect)");
+module_param(jpeg_enable, int, 0644);
+MODULE_PARM_DESC(jpeg_enable, "Jpeg enable(1-on 0-off) default 1");
/* USB device table */
#define USB_SENSORAY_VID 0x1943
@@ -413,6 +418,7 @@
#define BUFFER_TIMEOUT msecs_to_jiffies(400)
/* image formats. */
+/* JPEG formats must be defined last to support jpeg_enable parameter */
static const struct s2255_fmt formats[] = {
{
.name = "4:2:2, planar, YUV422P",
@@ -429,13 +435,17 @@
.fourcc = V4L2_PIX_FMT_UYVY,
.depth = 16
}, {
+ .name = "8bpp GREY",
+ .fourcc = V4L2_PIX_FMT_GREY,
+ .depth = 8
+ }, {
.name = "JPG",
.fourcc = V4L2_PIX_FMT_JPEG,
.depth = 24
}, {
- .name = "8bpp GREY",
- .fourcc = V4L2_PIX_FMT_GREY,
- .depth = 8
+ .name = "MJPG",
+ .fourcc = V4L2_PIX_FMT_MJPEG,
+ .depth = 24
}
};
@@ -610,6 +620,9 @@
for (i = 0; i < ARRAY_SIZE(formats); i++) {
if (-1 == formats[i].fourcc)
continue;
+ if (!jpeg_enable && ((formats[i].fourcc == V4L2_PIX_FMT_JPEG) ||
+ (formats[i].fourcc == V4L2_PIX_FMT_MJPEG)))
+ continue;
if (formats[i].fourcc == fourcc)
return formats + i;
}
@@ -653,6 +666,7 @@
memcpy(vbuf, tmpbuf, buf->vb.width * buf->vb.height);
break;
case V4L2_PIX_FMT_JPEG:
+ case V4L2_PIX_FMT_MJPEG:
buf->vb.size = jpgsize;
memcpy(vbuf, tmpbuf, buf->vb.size);
break;
@@ -856,7 +870,9 @@
if (index >= ARRAY_SIZE(formats))
return -EINVAL;
-
+ if (!jpeg_enable && ((formats[index].fourcc == V4L2_PIX_FMT_JPEG) ||
+ (formats[index].fourcc == V4L2_PIX_FMT_MJPEG)))
+ return -EINVAL;
dprintk(4, "name %s\n", formats[index].name);
strlcpy(f->description, formats[index].name, sizeof(f->description));
f->pixelformat = formats[index].fourcc;
@@ -1037,6 +1053,7 @@
mode.color |= COLOR_Y8;
break;
case V4L2_PIX_FMT_JPEG:
+ case V4L2_PIX_FMT_MJPEG:
mode.color &= ~MASK_COLOR;
mode.color |= COLOR_JPG;
mode.color |= (channel->jc.quality << 8);
@@ -2382,7 +2399,7 @@
read_pipe_completion, pipe_info);
if (pipe_info->state != 0) {
- if (usb_submit_urb(pipe_info->stream_urb, GFP_KERNEL)) {
+ if (usb_submit_urb(pipe_info->stream_urb, GFP_ATOMIC)) {
dev_err(&dev->udev->dev, "error submitting urb\n");
}
} else {
diff --git a/drivers/media/video/s5p-fimc/Makefile b/drivers/media/video/s5p-fimc/Makefile
index 7ea1b14..df6954a 100644
--- a/drivers/media/video/s5p-fimc/Makefile
+++ b/drivers/media/video/s5p-fimc/Makefile
@@ -1,3 +1,5 @@
+s5p-fimc-objs := fimc-core.o fimc-reg.o fimc-capture.o
+s5p-csis-objs := mipi-csis.o
-obj-$(CONFIG_VIDEO_SAMSUNG_S5P_FIMC) := s5p-fimc.o
-s5p-fimc-y := fimc-core.o fimc-reg.o fimc-capture.o
+obj-$(CONFIG_VIDEO_S5P_MIPI_CSIS) += s5p-csis.o
+obj-$(CONFIG_VIDEO_SAMSUNG_S5P_FIMC) += s5p-fimc.o
diff --git a/drivers/media/video/s5p-fimc/mipi-csis.c b/drivers/media/video/s5p-fimc/mipi-csis.c
new file mode 100644
index 0000000..ef056d6
--- /dev/null
+++ b/drivers/media/video/s5p-fimc/mipi-csis.c
@@ -0,0 +1,724 @@
+/*
+ * Samsung S5P/EXYNOS4 SoC series MIPI-CSI receiver driver
+ *
+ * Copyright (C) 2011 Samsung Electronics Co., Ltd.
+ * Contact: Sylwester Nawrocki, <s.nawrocki@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/errno.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/kernel.h>
+#include <linux/memory.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/regulator/consumer.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/videodev2.h>
+#include <media/v4l2-subdev.h>
+#include <plat/mipi_csis.h>
+#include "mipi-csis.h"
+
+static int debug;
+module_param(debug, int, 0644);
+MODULE_PARM_DESC(debug, "Debug level (0-1)");
+
+/* Register map definition */
+
+/* CSIS global control */
+#define S5PCSIS_CTRL 0x00
+#define S5PCSIS_CTRL_DPDN_DEFAULT (0 << 31)
+#define S5PCSIS_CTRL_DPDN_SWAP (1 << 31)
+#define S5PCSIS_CTRL_ALIGN_32BIT (1 << 20)
+#define S5PCSIS_CTRL_UPDATE_SHADOW (1 << 16)
+#define S5PCSIS_CTRL_WCLK_EXTCLK (1 << 8)
+#define S5PCSIS_CTRL_RESET (1 << 4)
+#define S5PCSIS_CTRL_ENABLE (1 << 0)
+
+/* D-PHY control */
+#define S5PCSIS_DPHYCTRL 0x04
+#define S5PCSIS_DPHYCTRL_HSS_MASK (0x1f << 27)
+#define S5PCSIS_DPHYCTRL_ENABLE (0x1f << 0)
+
+#define S5PCSIS_CONFIG 0x08
+#define S5PCSIS_CFG_FMT_YCBCR422_8BIT (0x1e << 2)
+#define S5PCSIS_CFG_FMT_RAW8 (0x2a << 2)
+#define S5PCSIS_CFG_FMT_RAW10 (0x2b << 2)
+#define S5PCSIS_CFG_FMT_RAW12 (0x2c << 2)
+/* User defined formats, x = 1...4 */
+#define S5PCSIS_CFG_FMT_USER(x) ((0x30 + x - 1) << 2)
+#define S5PCSIS_CFG_FMT_MASK (0x3f << 2)
+#define S5PCSIS_CFG_NR_LANE_MASK 3
+
+/* Interrupt mask. */
+#define S5PCSIS_INTMSK 0x10
+#define S5PCSIS_INTMSK_EN_ALL 0xf000003f
+#define S5PCSIS_INTSRC 0x14
+
+/* Pixel resolution */
+#define S5PCSIS_RESOL 0x2c
+#define CSIS_MAX_PIX_WIDTH 0xffff
+#define CSIS_MAX_PIX_HEIGHT 0xffff
+
+enum {
+ CSIS_CLK_MUX,
+ CSIS_CLK_GATE,
+};
+
+static char *csi_clock_name[] = {
+ [CSIS_CLK_MUX] = "sclk_csis",
+ [CSIS_CLK_GATE] = "csis",
+};
+#define NUM_CSIS_CLOCKS ARRAY_SIZE(csi_clock_name)
+
+enum {
+ ST_POWERED = 1,
+ ST_STREAMING = 2,
+ ST_SUSPENDED = 4,
+};
+
+/**
+ * struct csis_state - the driver's internal state data structure
+ * @lock: mutex serializing the subdev and power management operations,
+ * protecting @format and @flags members
+ * @pads: CSIS pads array
+ * @sd: v4l2_subdev associated with CSIS device instance
+ * @pdev: CSIS platform device
+ * @regs_res: requested I/O register memory resource
+ * @regs: mmaped I/O registers memory
+ * @clock: CSIS clocks
+ * @irq: requested s5p-mipi-csis irq number
+ * @flags: the state variable for power and streaming control
+ * @csis_fmt: current CSIS pixel format
+ * @format: common media bus format for the source and sink pad
+ */
+struct csis_state {
+ struct mutex lock;
+ struct media_pad pads[CSIS_PADS_NUM];
+ struct v4l2_subdev sd;
+ struct platform_device *pdev;
+ struct resource *regs_res;
+ void __iomem *regs;
+ struct clk *clock[NUM_CSIS_CLOCKS];
+ int irq;
+ struct regulator *supply;
+ u32 flags;
+ const struct csis_pix_format *csis_fmt;
+ struct v4l2_mbus_framefmt format;
+};
+
+/**
+ * struct csis_pix_format - CSIS pixel format description
+ * @pix_width_alignment: horizontal pixel alignment, width will be
+ * multiple of 2^pix_width_alignment
+ * @code: corresponding media bus code
+ * @fmt_reg: S5PCSIS_CONFIG register value
+ */
+struct csis_pix_format {
+ unsigned int pix_width_alignment;
+ enum v4l2_mbus_pixelcode code;
+ u32 fmt_reg;
+};
+
+static const struct csis_pix_format s5pcsis_formats[] = {
+ {
+ .code = V4L2_MBUS_FMT_VYUY8_2X8,
+ .fmt_reg = S5PCSIS_CFG_FMT_YCBCR422_8BIT,
+ }, {
+ .code = V4L2_MBUS_FMT_JPEG_1X8,
+ .fmt_reg = S5PCSIS_CFG_FMT_USER(1),
+ },
+};
+
+#define s5pcsis_write(__csis, __r, __v) writel(__v, __csis->regs + __r)
+#define s5pcsis_read(__csis, __r) readl(__csis->regs + __r)
+
+static struct csis_state *sd_to_csis_state(struct v4l2_subdev *sdev)
+{
+ return container_of(sdev, struct csis_state, sd);
+}
+
+static const struct csis_pix_format *find_csis_format(
+ struct v4l2_mbus_framefmt *mf)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(s5pcsis_formats); i++)
+ if (mf->code == s5pcsis_formats[i].code)
+ return &s5pcsis_formats[i];
+ return NULL;
+}
+
+static void s5pcsis_enable_interrupts(struct csis_state *state, bool on)
+{
+ u32 val = s5pcsis_read(state, S5PCSIS_INTMSK);
+
+ val = on ? val | S5PCSIS_INTMSK_EN_ALL :
+ val & ~S5PCSIS_INTMSK_EN_ALL;
+ s5pcsis_write(state, S5PCSIS_INTMSK, val);
+}
+
+static void s5pcsis_reset(struct csis_state *state)
+{
+ u32 val = s5pcsis_read(state, S5PCSIS_CTRL);
+
+ s5pcsis_write(state, S5PCSIS_CTRL, val | S5PCSIS_CTRL_RESET);
+ udelay(10);
+}
+
+static void s5pcsis_system_enable(struct csis_state *state, int on)
+{
+ u32 val;
+
+ val = s5pcsis_read(state, S5PCSIS_CTRL);
+ if (on)
+ val |= S5PCSIS_CTRL_ENABLE;
+ else
+ val &= ~S5PCSIS_CTRL_ENABLE;
+ s5pcsis_write(state, S5PCSIS_CTRL, val);
+
+ val = s5pcsis_read(state, S5PCSIS_DPHYCTRL);
+ if (on)
+ val |= S5PCSIS_DPHYCTRL_ENABLE;
+ else
+ val &= ~S5PCSIS_DPHYCTRL_ENABLE;
+ s5pcsis_write(state, S5PCSIS_DPHYCTRL, val);
+}
+
+/* Called with the state.lock mutex held */
+static void __s5pcsis_set_format(struct csis_state *state)
+{
+ struct v4l2_mbus_framefmt *mf = &state->format;
+ u32 val;
+
+ v4l2_dbg(1, debug, &state->sd, "fmt: %d, %d x %d\n",
+ mf->code, mf->width, mf->height);
+
+ /* Color format */
+ val = s5pcsis_read(state, S5PCSIS_CONFIG);
+ val = (val & ~S5PCSIS_CFG_FMT_MASK) | state->csis_fmt->fmt_reg;
+ s5pcsis_write(state, S5PCSIS_CONFIG, val);
+
+ /* Pixel resolution */
+ val = (mf->width << 16) | mf->height;
+ s5pcsis_write(state, S5PCSIS_RESOL, val);
+}
+
+static void s5pcsis_set_hsync_settle(struct csis_state *state, int settle)
+{
+ u32 val = s5pcsis_read(state, S5PCSIS_DPHYCTRL);
+
+ val = (val & ~S5PCSIS_DPHYCTRL_HSS_MASK) | (settle << 27);
+ s5pcsis_write(state, S5PCSIS_DPHYCTRL, val);
+}
+
+static void s5pcsis_set_params(struct csis_state *state)
+{
+ struct s5p_platform_mipi_csis *pdata = state->pdev->dev.platform_data;
+ u32 val;
+
+ val = s5pcsis_read(state, S5PCSIS_CONFIG);
+ val = (val & ~S5PCSIS_CFG_NR_LANE_MASK) | (pdata->lanes - 1);
+ s5pcsis_write(state, S5PCSIS_CONFIG, val);
+
+ __s5pcsis_set_format(state);
+ s5pcsis_set_hsync_settle(state, pdata->hs_settle);
+
+ val = s5pcsis_read(state, S5PCSIS_CTRL);
+ if (pdata->alignment == 32)
+ val |= S5PCSIS_CTRL_ALIGN_32BIT;
+ else /* 24-bits */
+ val &= ~S5PCSIS_CTRL_ALIGN_32BIT;
+ /* Not using external clock. */
+ val &= ~S5PCSIS_CTRL_WCLK_EXTCLK;
+ s5pcsis_write(state, S5PCSIS_CTRL, val);
+
+ /* Update the shadow register. */
+ val = s5pcsis_read(state, S5PCSIS_CTRL);
+ s5pcsis_write(state, S5PCSIS_CTRL, val | S5PCSIS_CTRL_UPDATE_SHADOW);
+}
+
+static void s5pcsis_clk_put(struct csis_state *state)
+{
+ int i;
+
+ for (i = 0; i < NUM_CSIS_CLOCKS; i++)
+ if (!IS_ERR_OR_NULL(state->clock[i]))
+ clk_put(state->clock[i]);
+}
+
+static int s5pcsis_clk_get(struct csis_state *state)
+{
+ struct device *dev = &state->pdev->dev;
+ int i;
+
+ for (i = 0; i < NUM_CSIS_CLOCKS; i++) {
+ state->clock[i] = clk_get(dev, csi_clock_name[i]);
+ if (IS_ERR(state->clock[i])) {
+ s5pcsis_clk_put(state);
+ dev_err(dev, "failed to get clock: %s\n",
+ csi_clock_name[i]);
+ return -ENXIO;
+ }
+ }
+ return 0;
+}
+
+static int s5pcsis_s_power(struct v4l2_subdev *sd, int on)
+{
+ struct csis_state *state = sd_to_csis_state(sd);
+ struct device *dev = &state->pdev->dev;
+
+ if (on)
+ return pm_runtime_get_sync(dev);
+
+ return pm_runtime_put_sync(dev);
+}
+
+static void s5pcsis_start_stream(struct csis_state *state)
+{
+ s5pcsis_reset(state);
+ s5pcsis_set_params(state);
+ s5pcsis_system_enable(state, true);
+ s5pcsis_enable_interrupts(state, true);
+}
+
+static void s5pcsis_stop_stream(struct csis_state *state)
+{
+ s5pcsis_enable_interrupts(state, false);
+ s5pcsis_system_enable(state, false);
+}
+
+/* v4l2_subdev operations */
+static int s5pcsis_s_stream(struct v4l2_subdev *sd, int enable)
+{
+ struct csis_state *state = sd_to_csis_state(sd);
+ int ret = 0;
+
+ v4l2_dbg(1, debug, sd, "%s: %d, state: 0x%x\n",
+ __func__, enable, state->flags);
+
+ if (enable) {
+ ret = pm_runtime_get_sync(&state->pdev->dev);
+ if (ret && ret != 1)
+ return ret;
+ }
+ mutex_lock(&state->lock);
+ if (enable) {
+ if (state->flags & ST_SUSPENDED) {
+ ret = -EBUSY;
+ goto unlock;
+ }
+ s5pcsis_start_stream(state);
+ state->flags |= ST_STREAMING;
+ } else {
+ s5pcsis_stop_stream(state);
+ state->flags &= ~ST_STREAMING;
+ }
+unlock:
+ mutex_unlock(&state->lock);
+ if (!enable)
+ pm_runtime_put(&state->pdev->dev);
+
+ return ret == 1 ? 0 : ret;
+}
+
+static int s5pcsis_enum_mbus_code(struct v4l2_subdev *sd,
+ struct v4l2_subdev_fh *fh,
+ struct v4l2_subdev_mbus_code_enum *code)
+{
+ if (code->index >= ARRAY_SIZE(s5pcsis_formats))
+ return -EINVAL;
+
+ code->code = s5pcsis_formats[code->index].code;
+ return 0;
+}
+
+static struct csis_pix_format const *s5pcsis_try_format(
+ struct v4l2_mbus_framefmt *mf)
+{
+ struct csis_pix_format const *csis_fmt;
+
+ csis_fmt = find_csis_format(mf);
+ if (csis_fmt == NULL)
+ csis_fmt = &s5pcsis_formats[0];
+
+ mf->code = csis_fmt->code;
+ v4l_bound_align_image(&mf->width, 1, CSIS_MAX_PIX_WIDTH,
+ csis_fmt->pix_width_alignment,
+ &mf->height, 1, CSIS_MAX_PIX_HEIGHT, 1,
+ 0);
+ return csis_fmt;
+}
+
+static struct v4l2_mbus_framefmt *__s5pcsis_get_format(
+ struct csis_state *state, struct v4l2_subdev_fh *fh,
+ u32 pad, enum v4l2_subdev_format_whence which)
+{
+ if (which == V4L2_SUBDEV_FORMAT_TRY)
+ return fh ? v4l2_subdev_get_try_format(fh, pad) : NULL;
+
+ return &state->format;
+}
+
+static int s5pcsis_set_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
+ struct v4l2_subdev_format *fmt)
+{
+ struct csis_state *state = sd_to_csis_state(sd);
+ struct csis_pix_format const *csis_fmt;
+ struct v4l2_mbus_framefmt *mf;
+
+ if (fmt->pad != CSIS_PAD_SOURCE && fmt->pad != CSIS_PAD_SINK)
+ return -EINVAL;
+
+ mf = __s5pcsis_get_format(state, fh, fmt->pad, fmt->which);
+
+ if (fmt->pad == CSIS_PAD_SOURCE) {
+ if (mf) {
+ mutex_lock(&state->lock);
+ fmt->format = *mf;
+ mutex_unlock(&state->lock);
+ }
+ return 0;
+ }
+ csis_fmt = s5pcsis_try_format(&fmt->format);
+ if (mf) {
+ mutex_lock(&state->lock);
+ *mf = fmt->format;
+ if (fmt->which == V4L2_SUBDEV_FORMAT_ACTIVE)
+ state->csis_fmt = csis_fmt;
+ mutex_unlock(&state->lock);
+ }
+ return 0;
+}
+
+static int s5pcsis_get_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh,
+ struct v4l2_subdev_format *fmt)
+{
+ struct csis_state *state = sd_to_csis_state(sd);
+ struct v4l2_mbus_framefmt *mf;
+
+ if (fmt->pad != CSIS_PAD_SOURCE && fmt->pad != CSIS_PAD_SINK)
+ return -EINVAL;
+
+ mf = __s5pcsis_get_format(state, fh, fmt->pad, fmt->which);
+ if (!mf)
+ return -EINVAL;
+
+ mutex_lock(&state->lock);
+ fmt->format = *mf;
+ mutex_unlock(&state->lock);
+ return 0;
+}
+
+static struct v4l2_subdev_core_ops s5pcsis_core_ops = {
+ .s_power = s5pcsis_s_power,
+};
+
+static struct v4l2_subdev_pad_ops s5pcsis_pad_ops = {
+ .enum_mbus_code = s5pcsis_enum_mbus_code,
+ .get_fmt = s5pcsis_get_fmt,
+ .set_fmt = s5pcsis_set_fmt,
+};
+
+static struct v4l2_subdev_video_ops s5pcsis_video_ops = {
+ .s_stream = s5pcsis_s_stream,
+};
+
+static struct v4l2_subdev_ops s5pcsis_subdev_ops = {
+ .core = &s5pcsis_core_ops,
+ .pad = &s5pcsis_pad_ops,
+ .video = &s5pcsis_video_ops,
+};
+
+static irqreturn_t s5pcsis_irq_handler(int irq, void *dev_id)
+{
+ struct csis_state *state = dev_id;
+ u32 val;
+
+ /* Just clear the interrupt pending bits. */
+ val = s5pcsis_read(state, S5PCSIS_INTSRC);
+ s5pcsis_write(state, S5PCSIS_INTSRC, val);
+
+ return IRQ_HANDLED;
+}
+
+static int __devinit s5pcsis_probe(struct platform_device *pdev)
+{
+ struct s5p_platform_mipi_csis *pdata;
+ struct resource *mem_res;
+ struct resource *regs_res;
+ struct csis_state *state;
+ int ret = -ENOMEM;
+
+ state = kzalloc(sizeof(*state), GFP_KERNEL);
+ if (!state)
+ return -ENOMEM;
+
+ mutex_init(&state->lock);
+ state->pdev = pdev;
+
+ pdata = pdev->dev.platform_data;
+ if (pdata == NULL || pdata->phy_enable == NULL) {
+ dev_err(&pdev->dev, "Platform data not fully specified\n");
+ goto e_free;
+ }
+
+ if ((pdev->id == 1 && pdata->lanes > CSIS1_MAX_LANES) ||
+ pdata->lanes > CSIS0_MAX_LANES) {
+ ret = -EINVAL;
+ dev_err(&pdev->dev, "Unsupported number of data lanes: %d\n",
+ pdata->lanes);
+ goto e_free;
+ }
+
+ mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!mem_res) {
+ dev_err(&pdev->dev, "Failed to get IO memory region\n");
+ goto e_free;
+ }
+
+ regs_res = request_mem_region(mem_res->start, resource_size(mem_res),
+ pdev->name);
+ if (!regs_res) {
+ dev_err(&pdev->dev, "Failed to request IO memory region\n");
+ goto e_free;
+ }
+ state->regs_res = regs_res;
+
+ state->regs = ioremap(mem_res->start, resource_size(mem_res));
+ if (!state->regs) {
+ dev_err(&pdev->dev, "Failed to remap IO region\n");
+ goto e_reqmem;
+ }
+
+ ret = s5pcsis_clk_get(state);
+ if (ret)
+ goto e_unmap;
+
+ clk_enable(state->clock[CSIS_CLK_MUX]);
+ if (pdata->clk_rate)
+ clk_set_rate(state->clock[CSIS_CLK_MUX], pdata->clk_rate);
+ else
+ dev_WARN(&pdev->dev, "No clock frequency specified!\n");
+
+ state->irq = platform_get_irq(pdev, 0);
+ if (state->irq < 0) {
+ ret = state->irq;
+ dev_err(&pdev->dev, "Failed to get irq\n");
+ goto e_clkput;
+ }
+
+ if (!pdata->fixed_phy_vdd) {
+ state->supply = regulator_get(&pdev->dev, "vdd");
+ if (IS_ERR(state->supply)) {
+ ret = PTR_ERR(state->supply);
+ state->supply = NULL;
+ goto e_clkput;
+ }
+ }
+
+ ret = request_irq(state->irq, s5pcsis_irq_handler, 0,
+ dev_name(&pdev->dev), state);
+ if (ret) {
+ dev_err(&pdev->dev, "request_irq failed\n");
+ goto e_regput;
+ }
+
+ v4l2_subdev_init(&state->sd, &s5pcsis_subdev_ops);
+ state->sd.owner = THIS_MODULE;
+ strlcpy(state->sd.name, dev_name(&pdev->dev), sizeof(state->sd.name));
+ state->csis_fmt = &s5pcsis_formats[0];
+
+ state->pads[CSIS_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
+ state->pads[CSIS_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
+ ret = media_entity_init(&state->sd.entity,
+ CSIS_PADS_NUM, state->pads, 0);
+ if (ret < 0)
+ goto e_irqfree;
+
+ /* This allows to retrieve the platform device id by the host driver */
+ v4l2_set_subdevdata(&state->sd, pdev);
+
+ /* .. and a pointer to the subdev. */
+ platform_set_drvdata(pdev, &state->sd);
+
+ state->flags = ST_SUSPENDED;
+ pm_runtime_enable(&pdev->dev);
+
+ return 0;
+
+e_irqfree:
+ free_irq(state->irq, state);
+e_regput:
+ if (state->supply)
+ regulator_put(state->supply);
+e_clkput:
+ clk_disable(state->clock[CSIS_CLK_MUX]);
+ s5pcsis_clk_put(state);
+e_unmap:
+ iounmap(state->regs);
+e_reqmem:
+ release_mem_region(regs_res->start, resource_size(regs_res));
+e_free:
+ kfree(state);
+ return ret;
+}
+
+static int s5pcsis_suspend(struct device *dev)
+{
+ struct s5p_platform_mipi_csis *pdata = dev->platform_data;
+ struct platform_device *pdev = to_platform_device(dev);
+ struct v4l2_subdev *sd = platform_get_drvdata(pdev);
+ struct csis_state *state = sd_to_csis_state(sd);
+ int ret = 0;
+
+ v4l2_dbg(1, debug, sd, "%s: flags: 0x%x\n",
+ __func__, state->flags);
+
+ mutex_lock(&state->lock);
+ if (state->flags & ST_POWERED) {
+ s5pcsis_stop_stream(state);
+ ret = pdata->phy_enable(state->pdev, false);
+ if (ret)
+ goto unlock;
+ if (state->supply) {
+ ret = regulator_disable(state->supply);
+ if (ret)
+ goto unlock;
+ }
+ clk_disable(state->clock[CSIS_CLK_GATE]);
+ state->flags &= ~ST_POWERED;
+ }
+ state->flags |= ST_SUSPENDED;
+ unlock:
+ mutex_unlock(&state->lock);
+ return ret ? -EAGAIN : 0;
+}
+
+static int s5pcsis_resume(struct device *dev)
+{
+ struct s5p_platform_mipi_csis *pdata = dev->platform_data;
+ struct platform_device *pdev = to_platform_device(dev);
+ struct v4l2_subdev *sd = platform_get_drvdata(pdev);
+ struct csis_state *state = sd_to_csis_state(sd);
+ int ret = 0;
+
+ v4l2_dbg(1, debug, sd, "%s: flags: 0x%x\n",
+ __func__, state->flags);
+
+ mutex_lock(&state->lock);
+ if (!(state->flags & ST_SUSPENDED))
+ goto unlock;
+
+ if (!(state->flags & ST_POWERED)) {
+ if (state->supply)
+ ret = regulator_enable(state->supply);
+ if (ret)
+ goto unlock;
+
+ ret = pdata->phy_enable(state->pdev, true);
+ if (!ret) {
+ state->flags |= ST_POWERED;
+ } else if (state->supply) {
+ regulator_disable(state->supply);
+ goto unlock;
+ }
+ clk_enable(state->clock[CSIS_CLK_GATE]);
+ }
+ if (state->flags & ST_STREAMING)
+ s5pcsis_start_stream(state);
+
+ state->flags &= ~ST_SUSPENDED;
+ unlock:
+ mutex_unlock(&state->lock);
+ return ret ? -EAGAIN : 0;
+}
+
+#ifdef CONFIG_PM_SLEEP
+static int s5pcsis_pm_suspend(struct device *dev)
+{
+ return s5pcsis_suspend(dev);
+}
+
+static int s5pcsis_pm_resume(struct device *dev)
+{
+ int ret;
+
+ ret = s5pcsis_resume(dev);
+
+ if (!ret) {
+ pm_runtime_disable(dev);
+ ret = pm_runtime_set_active(dev);
+ pm_runtime_enable(dev);
+ }
+
+ return ret;
+}
+#endif
+
+static int __devexit s5pcsis_remove(struct platform_device *pdev)
+{
+ struct v4l2_subdev *sd = platform_get_drvdata(pdev);
+ struct csis_state *state = sd_to_csis_state(sd);
+ struct resource *res = state->regs_res;
+
+ pm_runtime_disable(&pdev->dev);
+ s5pcsis_suspend(&pdev->dev);
+ clk_disable(state->clock[CSIS_CLK_MUX]);
+ pm_runtime_set_suspended(&pdev->dev);
+
+ s5pcsis_clk_put(state);
+ if (state->supply)
+ regulator_put(state->supply);
+
+ media_entity_cleanup(&state->sd.entity);
+ free_irq(state->irq, state);
+ iounmap(state->regs);
+ release_mem_region(res->start, resource_size(res));
+ kfree(state);
+
+ return 0;
+}
+
+static const struct dev_pm_ops s5pcsis_pm_ops = {
+ SET_RUNTIME_PM_OPS(s5pcsis_suspend, s5pcsis_resume, NULL)
+ SET_SYSTEM_SLEEP_PM_OPS(s5pcsis_pm_suspend, s5pcsis_pm_resume)
+};
+
+static struct platform_driver s5pcsis_driver = {
+ .probe = s5pcsis_probe,
+ .remove = __devexit_p(s5pcsis_remove),
+ .driver = {
+ .name = CSIS_DRIVER_NAME,
+ .owner = THIS_MODULE,
+ .pm = &s5pcsis_pm_ops,
+ },
+};
+
+static int __init s5pcsis_init(void)
+{
+ return platform_driver_probe(&s5pcsis_driver, s5pcsis_probe);
+}
+
+static void __exit s5pcsis_exit(void)
+{
+ platform_driver_unregister(&s5pcsis_driver);
+}
+
+module_init(s5pcsis_init);
+module_exit(s5pcsis_exit);
+
+MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
+MODULE_DESCRIPTION("S5P/EXYNOS4 MIPI CSI receiver driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/s5p-fimc/mipi-csis.h b/drivers/media/video/s5p-fimc/mipi-csis.h
new file mode 100644
index 0000000..f569133
--- /dev/null
+++ b/drivers/media/video/s5p-fimc/mipi-csis.h
@@ -0,0 +1,22 @@
+/*
+ * Samsung S5P/EXYNOS4 SoC series MIPI-CSI receiver driver
+ *
+ * Copyright (C) 2011 Samsung Electronics Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef S5P_MIPI_CSIS_H_
+#define S5P_MIPI_CSIS_H_
+
+#define CSIS_DRIVER_NAME "s5p-mipi-csis"
+#define CSIS_MAX_ENTITIES 2
+#define CSIS0_MAX_LANES 4
+#define CSIS1_MAX_LANES 2
+
+#define CSIS_PAD_SINK 0
+#define CSIS_PAD_SOURCE 1
+#define CSIS_PADS_NUM 2
+
+#endif
diff --git a/drivers/media/video/saa7134/saa7134-cards.c b/drivers/media/video/saa7134/saa7134-cards.c
index 50f1be0..e2062b2 100644
--- a/drivers/media/video/saa7134/saa7134-cards.c
+++ b/drivers/media/video/saa7134/saa7134-cards.c
@@ -5591,6 +5591,105 @@
.amux = TV,
},
},
+ [SAA7134_BOARD_MAGICPRO_PROHDTV_PRO2] = {
+ /* Timothy Lee <timothy.lee@siriushk.com> */
+ .name = "MagicPro ProHDTV Pro2 DMB-TH/Hybrid",
+ .audio_clock = 0x00187de7,
+ .tuner_type = TUNER_PHILIPS_TDA8290,
+ .radio_type = UNSET,
+ .tuner_config = 3,
+ .tuner_addr = ADDR_UNSET,
+ .radio_addr = ADDR_UNSET,
+ .gpiomask = 0x02050000,
+ .mpeg = SAA7134_MPEG_DVB,
+ .ts_type = SAA7134_MPEG_TS_PARALLEL,
+ .inputs = { {
+ .name = name_tv,
+ .vmux = 1,
+ .amux = TV,
+ .tv = 1,
+ .gpio = 0x00050000,
+ }, {
+ .name = name_comp1,
+ .vmux = 3,
+ .amux = LINE1,
+ .gpio = 0x00050000,
+ }, {
+ .name = name_svideo,
+ .vmux = 8,
+ .amux = LINE1,
+ .gpio = 0x00050000,
+ } },
+ .radio = {
+ .name = name_radio,
+ .amux = TV,
+ .gpio = 0x00050000,
+ },
+ .mute = {
+ .name = name_mute,
+ .vmux = 0,
+ .amux = TV,
+ .gpio = 0x00050000,
+ },
+ },
+ [SAA7134_BOARD_BEHOLD_501] = {
+ /* Beholder Intl. Ltd. 2010 */
+ /* Dmitry Belimov <d.belimov@gmail.com> */
+ .name = "Beholder BeholdTV 501",
+ .audio_clock = 0x00200000,
+ .tuner_type = TUNER_ABSENT,
+ .radio_type = UNSET,
+ .tuner_addr = ADDR_UNSET,
+ .radio_addr = ADDR_UNSET,
+ .gpiomask = 0x00008000,
+ .inputs = { {
+ .name = name_tv,
+ .vmux = 3,
+ .amux = LINE2,
+ .tv = 1,
+ }, {
+ .name = name_comp1,
+ .vmux = 1,
+ .amux = LINE1,
+ }, {
+ .name = name_svideo,
+ .vmux = 8,
+ .amux = LINE1,
+ } },
+ .mute = {
+ .name = name_mute,
+ .amux = LINE1,
+ },
+ },
+ [SAA7134_BOARD_BEHOLD_503FM] = {
+ /* Beholder Intl. Ltd. 2010 */
+ /* Dmitry Belimov <d.belimov@gmail.com> */
+ .name = "Beholder BeholdTV 503 FM",
+ .audio_clock = 0x00200000,
+ .tuner_type = TUNER_ABSENT,
+ .radio_type = UNSET,
+ .tuner_addr = ADDR_UNSET,
+ .radio_addr = ADDR_UNSET,
+ .gpiomask = 0x00008000,
+ .inputs = { {
+ .name = name_tv,
+ .vmux = 3,
+ .amux = LINE2,
+ .tv = 1,
+ }, {
+ .name = name_comp1,
+ .vmux = 1,
+ .amux = LINE1,
+ }, {
+ .name = name_svideo,
+ .vmux = 8,
+ .amux = LINE1,
+ } },
+ .mute = {
+ .name = name_mute,
+ .amux = LINE1,
+ },
+ },
};
@@ -6796,6 +6895,24 @@
.subdevice = 0xc900,
.driver_data = SAA7134_BOARD_VIDEOMATE_M1F,
}, {
+ .vendor = PCI_VENDOR_ID_PHILIPS,
+ .device = PCI_DEVICE_ID_PHILIPS_SAA7133,
+ .subvendor = 0x5ace,
+ .subdevice = 0x5030,
+ .driver_data = SAA7134_BOARD_BEHOLD_503FM,
+ }, {
+ .vendor = PCI_VENDOR_ID_PHILIPS,
+ .device = PCI_DEVICE_ID_PHILIPS_SAA7130,
+ .subvendor = 0x5ace,
+ .subdevice = 0x5010,
+ .driver_data = SAA7134_BOARD_BEHOLD_501,
+ }, {
+ .vendor = PCI_VENDOR_ID_PHILIPS,
+ .device = PCI_DEVICE_ID_PHILIPS_SAA7134,
+ .subvendor = 0x17de,
+ .subdevice = 0xd136,
+ .driver_data = SAA7134_BOARD_MAGICPRO_PROHDTV_PRO2,
+ }, {
/* --- boards without eeprom + subsystem ID --- */
.vendor = PCI_VENDOR_ID_PHILIPS,
.device = PCI_DEVICE_ID_PHILIPS_SAA7134,
@@ -6988,6 +7105,7 @@
switch (dev->board) {
case SAA7134_BOARD_HAUPPAUGE_HVR1150:
case SAA7134_BOARD_HAUPPAUGE_HVR1120:
+ case SAA7134_BOARD_MAGICPRO_PROHDTV_PRO2:
ret = saa7134_tda18271_hvr11x0_toggle_agc(dev, arg);
break;
case SAA7134_BOARD_KWORLD_PCI_SBTVD_FULLSEG:
@@ -7014,6 +7132,7 @@
case SAA7134_BOARD_HAUPPAUGE_HVR1120:
case SAA7134_BOARD_AVERMEDIA_M733A:
case SAA7134_BOARD_KWORLD_PCI_SBTVD_FULLSEG:
+ case SAA7134_BOARD_MAGICPRO_PROHDTV_PRO2:
/* tda8290 + tda18271 */
ret = saa7134_tda8290_18271_callback(dev, command, arg);
break;
@@ -7264,6 +7383,7 @@
break;
case SAA7134_BOARD_HAUPPAUGE_HVR1150:
case SAA7134_BOARD_HAUPPAUGE_HVR1120:
+ dev->has_remote = SAA7134_REMOTE_GPIO;
/* GPIO 26 high for digital, low for analog */
saa7134_set_gpio(dev, 26, 0);
msleep(1);
@@ -7326,6 +7446,11 @@
saa7134_set_gpio(dev, 1, 1);
dev->has_remote = SAA7134_REMOTE_GPIO;
break;
+ case SAA7134_BOARD_MAGICPRO_PROHDTV_PRO2:
+ /* enable LGS-8G75 */
+ saa_andorl(SAA7134_GPIO_GPMODE0 >> 2, 0x0e050000, 0x0c050000);
+ saa_andorl(SAA7134_GPIO_GPSTATUS0 >> 2, 0x0e050000, 0x0c050000);
+ break;
}
return 0;
}
diff --git a/drivers/media/video/saa7134/saa7134-core.c b/drivers/media/video/saa7134/saa7134-core.c
index 41f836f..f9be737 100644
--- a/drivers/media/video/saa7134/saa7134-core.c
+++ b/drivers/media/video/saa7134/saa7134-core.c
@@ -927,7 +927,7 @@
}
/* print pci info */
- pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &dev->pci_rev);
+ dev->pci_rev = pci_dev->revision;
pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat);
printk(KERN_INFO "%s: found at %s, rev: %d, irq: %d, "
"latency: %d, mmio: 0x%llx\n", dev->name,
diff --git a/drivers/media/video/saa7134/saa7134-dvb.c b/drivers/media/video/saa7134/saa7134-dvb.c
index f65cad2..996a206 100644
--- a/drivers/media/video/saa7134/saa7134-dvb.c
+++ b/drivers/media/video/saa7134/saa7134-dvb.c
@@ -53,6 +53,7 @@
#include "lgdt3305.h"
#include "tda8290.h"
#include "mb86a20s.h"
+#include "lgs8gxx.h"
#include "zl10353.h"
@@ -1123,6 +1124,26 @@
.gate = TDA18271_GATE_ANALOG,
};
+static struct lgs8gxx_config prohdtv_pro2_lgs8g75_config = {
+ .prod = LGS8GXX_PROD_LGS8G75,
+ .demod_address = 0x1d,
+ .serial_ts = 0,
+ .ts_clk_pol = 1,
+ .ts_clk_gated = 0,
+ .if_clk_freq = 30400, /* 30.4 MHz */
+ .if_freq = 4000, /* 4.00 MHz */
+ .if_neg_center = 0,
+ .ext_adc = 0,
+ .adc_signed = 1,
+ .adc_vpp = 3, /* 2.0 Vpp */
+ .if_neg_edge = 1,
+};
+
+static struct tda18271_config prohdtv_pro2_tda18271_config = {
+ .gate = TDA18271_GATE_ANALOG,
+ .output_opt = TDA18271_OUTPUT_LT_OFF,
+};
+
/* ==================================================================
* Core code
*/
@@ -1674,6 +1695,19 @@
/* mb86a20s need to use the I2C gateway */
break;
+ case SAA7134_BOARD_MAGICPRO_PROHDTV_PRO2:
+ fe0->dvb.frontend = dvb_attach(lgs8gxx_attach,
+ &prohdtv_pro2_lgs8g75_config,
+ &dev->i2c_adap);
+ if (fe0->dvb.frontend != NULL) {
+ dvb_attach(tda829x_attach, fe0->dvb.frontend,
+ &dev->i2c_adap, 0x4b,
+ &tda829x_no_probe);
+ dvb_attach(tda18271_attach, fe0->dvb.frontend,
+ 0x60, &dev->i2c_adap,
+ &prohdtv_pro2_tda18271_config);
+ }
+ break;
default:
wprintk("Huh? unknown DVB card?\n");
break;
diff --git a/drivers/media/video/saa7134/saa7134-input.c b/drivers/media/video/saa7134/saa7134-input.c
index be1c2a2..ff6c0e9 100644
--- a/drivers/media/video/saa7134/saa7134-input.c
+++ b/drivers/media/video/saa7134/saa7134-input.c
@@ -756,6 +756,14 @@
mask_keycode = 0x0ff00;
mask_keyup = 0x040000;
break;
+ case SAA7134_BOARD_HAUPPAUGE_HVR1150:
+ case SAA7134_BOARD_HAUPPAUGE_HVR1120:
+ ir_codes = RC_MAP_HAUPPAUGE;
+ mask_keydown = 0x0040000; /* Enable GPIO18 line on both edges */
+ mask_keyup = 0x0040000;
+ mask_keycode = 0xffff;
+ raw_decode = true;
+ break;
}
if (NULL == ir_codes) {
printk("%s: Oops: IR config error [card=%d]\n",
diff --git a/drivers/media/video/saa7134/saa7134.h b/drivers/media/video/saa7134/saa7134.h
index f96cd5d..28eb103 100644
--- a/drivers/media/video/saa7134/saa7134.h
+++ b/drivers/media/video/saa7134/saa7134.h
@@ -328,6 +328,9 @@
#define SAA7134_BOARD_KWORLD_PCI_SBTVD_FULLSEG 182
#define SAA7134_BOARD_VIDEOMATE_M1F 183
#define SAA7134_BOARD_ENCORE_ENLTV_FM3 184
+#define SAA7134_BOARD_MAGICPRO_PROHDTV_PRO2 185
+#define SAA7134_BOARD_BEHOLD_501 186
+#define SAA7134_BOARD_BEHOLD_503FM 187
#define SAA7134_MAXBOARDS 32
#define SAA7134_INPUT_MAX 8
diff --git a/drivers/media/video/saa7164/saa7164-core.c b/drivers/media/video/saa7164/saa7164-core.c
index b813aec..3b7d7b4 100644
--- a/drivers/media/video/saa7164/saa7164-core.c
+++ b/drivers/media/video/saa7164/saa7164-core.c
@@ -1247,7 +1247,7 @@
}
/* print pci info */
- pci_read_config_byte(pci_dev, PCI_CLASS_REVISION, &dev->pci_rev);
+ dev->pci_rev = pci_dev->revision;
pci_read_config_byte(pci_dev, PCI_LATENCY_TIMER, &dev->pci_lat);
printk(KERN_INFO "%s/0: found at %s, rev: %d, irq: %d, "
"latency: %d, mmio: 0x%llx\n", dev->name,
diff --git a/drivers/media/video/sh_mobile_ceu_camera.c b/drivers/media/video/sh_mobile_ceu_camera.c
index 134e86b..3ae5c9c 100644
--- a/drivers/media/video/sh_mobile_ceu_camera.c
+++ b/drivers/media/video/sh_mobile_ceu_camera.c
@@ -17,6 +17,7 @@
#include <linux/init.h>
#include <linux/module.h>
#include <linux/io.h>
+#include <linux/completion.h>
#include <linux/delay.h>
#include <linux/dma-mapping.h>
#include <linux/errno.h>
@@ -106,6 +107,7 @@
struct vb2_alloc_ctx *alloc_ctx;
struct sh_mobile_ceu_info *pdata;
+ struct completion complete;
u32 cflcr;
@@ -114,6 +116,7 @@
unsigned int image_mode:1;
unsigned int is_16bit:1;
+ unsigned int frozen:1;
};
struct sh_mobile_ceu_cam {
@@ -273,7 +276,8 @@
ceu_write(pcdev, CEIER, ceu_read(pcdev, CEIER) & ~CEU_CEIER_MASK);
status = ceu_read(pcdev, CETCR);
ceu_write(pcdev, CETCR, ~status & CEU_CETCR_MAGIC);
- ceu_write(pcdev, CEIER, ceu_read(pcdev, CEIER) | CEU_CEIER_MASK);
+ if (!pcdev->frozen)
+ ceu_write(pcdev, CEIER, ceu_read(pcdev, CEIER) | CEU_CEIER_MASK);
ceu_write(pcdev, CAPCR, ceu_read(pcdev, CAPCR) & ~CEU_CAPCR_CTNCP);
ceu_write(pcdev, CETCR, CEU_CETCR_MAGIC ^ CEU_CETCR_IGRW);
@@ -287,6 +291,11 @@
ret = -EIO;
}
+ if (pcdev->frozen) {
+ complete(&pcdev->complete);
+ return ret;
+ }
+
if (!pcdev->active)
return ret;
@@ -378,12 +387,11 @@
struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
struct sh_mobile_ceu_dev *pcdev = ici->priv;
struct sh_mobile_ceu_buffer *buf = to_ceu_vb(vb);
- unsigned long flags;
dev_dbg(icd->dev.parent, "%s (vb=0x%p) 0x%p %lu\n", __func__,
vb, vb2_plane_vaddr(vb, 0), vb2_get_plane_payload(vb, 0));
- spin_lock_irqsave(&pcdev->lock, flags);
+ spin_lock_irq(&pcdev->lock);
list_add_tail(&buf->queue, &pcdev->capture);
if (!pcdev->active) {
@@ -395,7 +403,7 @@
pcdev->active = vb;
sh_mobile_ceu_capture(pcdev);
}
- spin_unlock_irqrestore(&pcdev->lock, flags);
+ spin_unlock_irq(&pcdev->lock);
}
static void sh_mobile_ceu_videobuf_release(struct vb2_buffer *vb)
@@ -404,9 +412,8 @@
struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
struct sh_mobile_ceu_buffer *buf = to_ceu_vb(vb);
struct sh_mobile_ceu_dev *pcdev = ici->priv;
- unsigned long flags;
- spin_lock_irqsave(&pcdev->lock, flags);
+ spin_lock_irq(&pcdev->lock);
if (pcdev->active == vb) {
/* disable capture (release DMA buffer), reset */
@@ -417,7 +424,7 @@
/* Doesn't hurt also if the list is empty */
list_del_init(&buf->queue);
- spin_unlock_irqrestore(&pcdev->lock, flags);
+ spin_unlock_irq(&pcdev->lock);
}
static int sh_mobile_ceu_videobuf_init(struct vb2_buffer *vb)
@@ -427,6 +434,25 @@
return 0;
}
+static int sh_mobile_ceu_stop_streaming(struct vb2_queue *q)
+{
+ struct soc_camera_device *icd = container_of(q, struct soc_camera_device, vb2_vidq);
+ struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
+ struct sh_mobile_ceu_dev *pcdev = ici->priv;
+ struct list_head *buf_head, *tmp;
+
+ spin_lock_irq(&pcdev->lock);
+
+ pcdev->active = NULL;
+
+ list_for_each_safe(buf_head, tmp, &pcdev->capture)
+ list_del_init(buf_head);
+
+ spin_unlock_irq(&pcdev->lock);
+
+ return sh_mobile_ceu_soft_reset(pcdev);
+}
+
static struct vb2_ops sh_mobile_ceu_videobuf_ops = {
.queue_setup = sh_mobile_ceu_videobuf_setup,
.buf_prepare = sh_mobile_ceu_videobuf_prepare,
@@ -435,6 +461,7 @@
.buf_init = sh_mobile_ceu_videobuf_init,
.wait_prepare = soc_camera_unlock,
.wait_finish = soc_camera_lock,
+ .stop_streaming = sh_mobile_ceu_stop_streaming,
};
static irqreturn_t sh_mobile_ceu_irq(int irq, void *data)
@@ -500,7 +527,6 @@
{
struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
struct sh_mobile_ceu_dev *pcdev = ici->priv;
- unsigned long flags;
BUG_ON(icd != pcdev->icd);
@@ -509,13 +535,13 @@
sh_mobile_ceu_soft_reset(pcdev);
/* make sure active buffer is canceled */
- spin_lock_irqsave(&pcdev->lock, flags);
+ spin_lock_irq(&pcdev->lock);
if (pcdev->active) {
list_del_init(&to_ceu_vb(pcdev->active)->queue);
vb2_buffer_done(pcdev->active, VB2_BUF_STATE_ERROR);
pcdev->active = NULL;
}
- spin_unlock_irqrestore(&pcdev->lock, flags);
+ spin_unlock_irq(&pcdev->lock);
pm_runtime_put_sync(ici->v4l2_dev.dev);
@@ -891,8 +917,8 @@
fmt = soc_mbus_get_fmtdesc(code);
if (!fmt) {
- dev_err(dev, "Invalid format code #%u: %d\n", idx, code);
- return -EINVAL;
+ dev_warn(dev, "unsupported format code #%u: %d\n", idx, code);
+ return 0;
}
if (!pcdev->pdata->csi2_dev) {
@@ -1330,7 +1356,7 @@
/*
* CEU can scale and crop, but we don't want to waste bandwidth and kill the
* framerate by always requesting the maximum image from the client. See
- * Documentation/video4linux/sh_mobile_camera_ceu.txt for a description of
+ * Documentation/video4linux/sh_mobile_ceu_camera.txt for a description of
* scaling and cropping algorithms and for the meaning of referenced here steps.
*/
static int sh_mobile_ceu_set_crop(struct soc_camera_device *icd,
@@ -1377,10 +1403,6 @@
if (mf.width > 2560 || mf.height > 1920)
return -EINVAL;
- /* Cache camera output window */
- cam->width = mf.width;
- cam->height = mf.height;
-
/* 4. Calculate camera scales */
scale_cam_h = calc_generic_scale(cam_rect->width, mf.width);
scale_cam_v = calc_generic_scale(cam_rect->height, mf.height);
@@ -1389,6 +1411,39 @@
interm_width = scale_down(rect->width, scale_cam_h);
interm_height = scale_down(rect->height, scale_cam_v);
+ if (interm_width < icd->user_width) {
+ u32 new_scale_h;
+
+ new_scale_h = calc_generic_scale(rect->width, icd->user_width);
+
+ mf.width = scale_down(cam_rect->width, new_scale_h);
+ }
+
+ if (interm_height < icd->user_height) {
+ u32 new_scale_v;
+
+ new_scale_v = calc_generic_scale(rect->height, icd->user_height);
+
+ mf.height = scale_down(cam_rect->height, new_scale_v);
+ }
+
+ if (interm_width < icd->user_width || interm_height < icd->user_height) {
+ ret = v4l2_device_call_until_err(sd->v4l2_dev, (int)icd, video,
+ s_mbus_fmt, &mf);
+ if (ret < 0)
+ return ret;
+
+ dev_geo(dev, "New camera output %ux%u\n", mf.width, mf.height);
+ scale_cam_h = calc_generic_scale(cam_rect->width, mf.width);
+ scale_cam_v = calc_generic_scale(cam_rect->height, mf.height);
+ interm_width = scale_down(rect->width, scale_cam_h);
+ interm_height = scale_down(rect->height, scale_cam_v);
+ }
+
+ /* Cache camera output window */
+ cam->width = mf.width;
+ cam->height = mf.height;
+
if (pcdev->image_mode) {
out_width = min(interm_width, icd->user_width);
out_height = min(interm_height, icd->user_height);
@@ -1704,6 +1759,63 @@
return ret;
}
+static int sh_mobile_ceu_set_livecrop(struct soc_camera_device *icd,
+ struct v4l2_crop *a)
+{
+ struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
+ struct soc_camera_host *ici = to_soc_camera_host(icd->dev.parent);
+ struct sh_mobile_ceu_dev *pcdev = ici->priv;
+ u32 out_width = icd->user_width, out_height = icd->user_height;
+ int ret;
+
+ /* Freeze queue */
+ pcdev->frozen = 1;
+ /* Wait for frame */
+ ret = wait_for_completion_interruptible(&pcdev->complete);
+ /* Stop the client */
+ ret = v4l2_subdev_call(sd, video, s_stream, 0);
+ if (ret < 0)
+ dev_warn(icd->dev.parent,
+ "Client failed to stop the stream: %d\n", ret);
+ else
+ /* Do the crop, if it fails, there's nothing more we can do */
+ sh_mobile_ceu_set_crop(icd, a);
+
+ dev_geo(icd->dev.parent, "Output after crop: %ux%u\n", icd->user_width, icd->user_height);
+
+ if (icd->user_width != out_width || icd->user_height != out_height) {
+ struct v4l2_format f = {
+ .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,
+ .fmt.pix = {
+ .width = out_width,
+ .height = out_height,
+ .pixelformat = icd->current_fmt->host_fmt->fourcc,
+ .field = pcdev->field,
+ .colorspace = icd->colorspace,
+ },
+ };
+ ret = sh_mobile_ceu_set_fmt(icd, &f);
+ if (!ret && (out_width != f.fmt.pix.width ||
+ out_height != f.fmt.pix.height))
+ ret = -EINVAL;
+ if (!ret) {
+ icd->user_width = out_width;
+ icd->user_height = out_height;
+ ret = sh_mobile_ceu_set_bus_param(icd,
+ icd->current_fmt->host_fmt->fourcc);
+ }
+ }
+
+ /* Thaw the queue */
+ pcdev->frozen = 0;
+ spin_lock_irq(&pcdev->lock);
+ sh_mobile_ceu_capture(pcdev);
+ spin_unlock_irq(&pcdev->lock);
+ /* Start the client */
+ ret = v4l2_subdev_call(sd, video, s_stream, 1);
+ return ret;
+}
+
static unsigned int sh_mobile_ceu_poll(struct file *file, poll_table *pt)
{
struct soc_camera_device *icd = file->private_data;
@@ -1790,6 +1902,7 @@
.put_formats = sh_mobile_ceu_put_formats,
.get_crop = sh_mobile_ceu_get_crop,
.set_crop = sh_mobile_ceu_set_crop,
+ .set_livecrop = sh_mobile_ceu_set_livecrop,
.set_fmt = sh_mobile_ceu_set_fmt,
.try_fmt = sh_mobile_ceu_try_fmt,
.set_ctrl = sh_mobile_ceu_set_ctrl,
@@ -1856,6 +1969,7 @@
INIT_LIST_HEAD(&pcdev->capture);
spin_lock_init(&pcdev->lock);
+ init_completion(&pcdev->complete);
pcdev->pdata = pdev->dev.platform_data;
if (!pcdev->pdata) {
diff --git a/drivers/media/video/soc_camera.c b/drivers/media/video/soc_camera.c
index ddb4c09..3988643 100644
--- a/drivers/media/video/soc_camera.c
+++ b/drivers/media/video/soc_camera.c
@@ -41,6 +41,11 @@
#define DEFAULT_WIDTH 640
#define DEFAULT_HEIGHT 480
+#define is_streaming(ici, icd) \
+ (((ici)->ops->init_videobuf) ? \
+ (icd)->vb_vidq.streaming : \
+ vb2_is_streaming(&(icd)->vb2_vidq))
+
static LIST_HEAD(hosts);
static LIST_HEAD(devices);
static DEFINE_MUTEX(list_lock); /* Protects the list of hosts */
@@ -358,8 +363,6 @@
if (!icd->user_formats)
return -ENOMEM;
- icd->num_user_formats = fmts;
-
dev_dbg(&icd->dev, "Found %d supported formats.\n", fmts);
/* Second pass - actually fill data formats */
@@ -367,9 +370,10 @@
for (i = 0; i < raw_fmts; i++)
if (!ici->ops->get_formats) {
v4l2_subdev_call(sd, video, enum_mbus_fmt, i, &code);
- icd->user_formats[i].host_fmt =
+ icd->user_formats[fmts].host_fmt =
soc_mbus_get_fmtdesc(code);
- icd->user_formats[i].code = code;
+ if (icd->user_formats[fmts].host_fmt)
+ icd->user_formats[fmts++].code = code;
} else {
ret = ici->ops->get_formats(icd, i,
&icd->user_formats[fmts]);
@@ -378,12 +382,12 @@
fmts += ret;
}
+ icd->num_user_formats = fmts;
icd->current_fmt = &icd->user_formats[0];
return 0;
egfmt:
- icd->num_user_formats = 0;
vfree(icd->user_formats);
return ret;
}
@@ -662,7 +666,7 @@
if (icd->streamer && icd->streamer != file)
return -EBUSY;
- if (icd->vb_vidq.bufs[0]) {
+ if (is_streaming(to_soc_camera_host(icd->dev.parent), icd)) {
dev_err(&icd->dev, "S_FMT denied: queue initialised\n");
return -EBUSY;
}
@@ -903,14 +907,17 @@
if (ret < 0) {
dev_err(&icd->dev,
"S_CROP denied: getting current crop failed\n");
- } else if (icd->vb_vidq.bufs[0] &&
- (a->c.width != current_crop.c.width ||
- a->c.height != current_crop.c.height)) {
+ } else if ((a->c.width == current_crop.c.width &&
+ a->c.height == current_crop.c.height) ||
+ !is_streaming(ici, icd)) {
+ /* same size or not streaming - use .set_crop() */
+ ret = ici->ops->set_crop(icd, a);
+ } else if (ici->ops->set_livecrop) {
+ ret = ici->ops->set_livecrop(icd, a);
+ } else {
dev_err(&icd->dev,
"S_CROP denied: queue initialised and sizes differ\n");
ret = -EBUSY;
- } else {
- ret = ici->ops->set_crop(icd, a);
}
return ret;
diff --git a/drivers/media/video/soc_mediabus.c b/drivers/media/video/soc_mediabus.c
index ed77aa0..bea7c9c 100644
--- a/drivers/media/video/soc_mediabus.c
+++ b/drivers/media/video/soc_mediabus.c
@@ -15,132 +15,329 @@
#include <media/v4l2-mediabus.h>
#include <media/soc_mediabus.h>
-#define MBUS_IDX(f) (V4L2_MBUS_FMT_ ## f - V4L2_MBUS_FMT_FIXED - 1)
-
-static const struct soc_mbus_pixelfmt mbus_fmt[] = {
- [MBUS_IDX(YUYV8_2X8)] = {
+static const struct soc_mbus_lookup mbus_fmt[] = {
+{
+ .code = V4L2_MBUS_FMT_YUYV8_2X8,
+ .fmt = {
.fourcc = V4L2_PIX_FMT_YUYV,
.name = "YUYV",
.bits_per_sample = 8,
.packing = SOC_MBUS_PACKING_2X8_PADHI,
.order = SOC_MBUS_ORDER_LE,
},
- [MBUS_IDX(YVYU8_2X8)] = {
+}, {
+ .code = V4L2_MBUS_FMT_YVYU8_2X8,
+ .fmt = {
.fourcc = V4L2_PIX_FMT_YVYU,
.name = "YVYU",
.bits_per_sample = 8,
.packing = SOC_MBUS_PACKING_2X8_PADHI,
.order = SOC_MBUS_ORDER_LE,
},
- [MBUS_IDX(UYVY8_2X8)] = {
+}, {
+ .code = V4L2_MBUS_FMT_UYVY8_2X8,
+ .fmt = {
.fourcc = V4L2_PIX_FMT_UYVY,
.name = "UYVY",
.bits_per_sample = 8,
.packing = SOC_MBUS_PACKING_2X8_PADHI,
.order = SOC_MBUS_ORDER_LE,
},
- [MBUS_IDX(VYUY8_2X8)] = {
+}, {
+ .code = V4L2_MBUS_FMT_VYUY8_2X8,
+ .fmt = {
.fourcc = V4L2_PIX_FMT_VYUY,
.name = "VYUY",
.bits_per_sample = 8,
.packing = SOC_MBUS_PACKING_2X8_PADHI,
.order = SOC_MBUS_ORDER_LE,
},
- [MBUS_IDX(RGB555_2X8_PADHI_LE)] = {
+}, {
+ .code = V4L2_MBUS_FMT_RGB555_2X8_PADHI_LE,
+ .fmt = {
.fourcc = V4L2_PIX_FMT_RGB555,
.name = "RGB555",
.bits_per_sample = 8,
.packing = SOC_MBUS_PACKING_2X8_PADHI,
.order = SOC_MBUS_ORDER_LE,
},
- [MBUS_IDX(RGB555_2X8_PADHI_BE)] = {
+}, {
+ .code = V4L2_MBUS_FMT_RGB555_2X8_PADHI_BE,
+ .fmt = {
.fourcc = V4L2_PIX_FMT_RGB555X,
.name = "RGB555X",
.bits_per_sample = 8,
.packing = SOC_MBUS_PACKING_2X8_PADHI,
.order = SOC_MBUS_ORDER_LE,
},
- [MBUS_IDX(RGB565_2X8_LE)] = {
+}, {
+ .code = V4L2_MBUS_FMT_RGB565_2X8_LE,
+ .fmt = {
.fourcc = V4L2_PIX_FMT_RGB565,
.name = "RGB565",
.bits_per_sample = 8,
.packing = SOC_MBUS_PACKING_2X8_PADHI,
.order = SOC_MBUS_ORDER_LE,
},
- [MBUS_IDX(RGB565_2X8_BE)] = {
+}, {
+ .code = V4L2_MBUS_FMT_RGB565_2X8_BE,
+ .fmt = {
.fourcc = V4L2_PIX_FMT_RGB565X,
.name = "RGB565X",
.bits_per_sample = 8,
.packing = SOC_MBUS_PACKING_2X8_PADHI,
.order = SOC_MBUS_ORDER_LE,
},
- [MBUS_IDX(SBGGR8_1X8)] = {
+}, {
+ .code = V4L2_MBUS_FMT_SBGGR8_1X8,
+ .fmt = {
.fourcc = V4L2_PIX_FMT_SBGGR8,
.name = "Bayer 8 BGGR",
.bits_per_sample = 8,
.packing = SOC_MBUS_PACKING_NONE,
.order = SOC_MBUS_ORDER_LE,
},
- [MBUS_IDX(SBGGR10_1X10)] = {
+}, {
+ .code = V4L2_MBUS_FMT_SBGGR10_1X10,
+ .fmt = {
.fourcc = V4L2_PIX_FMT_SBGGR10,
.name = "Bayer 10 BGGR",
.bits_per_sample = 10,
.packing = SOC_MBUS_PACKING_EXTEND16,
.order = SOC_MBUS_ORDER_LE,
},
- [MBUS_IDX(Y8_1X8)] = {
+}, {
+ .code = V4L2_MBUS_FMT_Y8_1X8,
+ .fmt = {
.fourcc = V4L2_PIX_FMT_GREY,
.name = "Grey",
.bits_per_sample = 8,
.packing = SOC_MBUS_PACKING_NONE,
.order = SOC_MBUS_ORDER_LE,
},
- [MBUS_IDX(Y10_1X10)] = {
+}, {
+ .code = V4L2_MBUS_FMT_Y10_1X10,
+ .fmt = {
.fourcc = V4L2_PIX_FMT_Y10,
.name = "Grey 10bit",
.bits_per_sample = 10,
.packing = SOC_MBUS_PACKING_EXTEND16,
.order = SOC_MBUS_ORDER_LE,
},
- [MBUS_IDX(SBGGR10_2X8_PADHI_LE)] = {
+}, {
+ .code = V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_LE,
+ .fmt = {
.fourcc = V4L2_PIX_FMT_SBGGR10,
.name = "Bayer 10 BGGR",
.bits_per_sample = 8,
.packing = SOC_MBUS_PACKING_2X8_PADHI,
.order = SOC_MBUS_ORDER_LE,
},
- [MBUS_IDX(SBGGR10_2X8_PADLO_LE)] = {
+}, {
+ .code = V4L2_MBUS_FMT_SBGGR10_2X8_PADLO_LE,
+ .fmt = {
.fourcc = V4L2_PIX_FMT_SBGGR10,
.name = "Bayer 10 BGGR",
.bits_per_sample = 8,
.packing = SOC_MBUS_PACKING_2X8_PADLO,
.order = SOC_MBUS_ORDER_LE,
},
- [MBUS_IDX(SBGGR10_2X8_PADHI_BE)] = {
+}, {
+ .code = V4L2_MBUS_FMT_SBGGR10_2X8_PADHI_BE,
+ .fmt = {
.fourcc = V4L2_PIX_FMT_SBGGR10,
.name = "Bayer 10 BGGR",
.bits_per_sample = 8,
.packing = SOC_MBUS_PACKING_2X8_PADHI,
.order = SOC_MBUS_ORDER_BE,
},
- [MBUS_IDX(SBGGR10_2X8_PADLO_BE)] = {
+}, {
+ .code = V4L2_MBUS_FMT_SBGGR10_2X8_PADLO_BE,
+ .fmt = {
.fourcc = V4L2_PIX_FMT_SBGGR10,
.name = "Bayer 10 BGGR",
.bits_per_sample = 8,
.packing = SOC_MBUS_PACKING_2X8_PADLO,
.order = SOC_MBUS_ORDER_BE,
},
+}, {
+ .code = V4L2_MBUS_FMT_JPEG_1X8,
+ .fmt = {
+ .fourcc = V4L2_PIX_FMT_JPEG,
+ .name = "JPEG",
+ .bits_per_sample = 8,
+ .packing = SOC_MBUS_PACKING_VARIABLE,
+ .order = SOC_MBUS_ORDER_LE,
+ },
+}, {
+ .code = V4L2_MBUS_FMT_RGB444_2X8_PADHI_BE,
+ .fmt = {
+ .fourcc = V4L2_PIX_FMT_RGB444,
+ .name = "RGB444",
+ .bits_per_sample = 8,
+ .packing = SOC_MBUS_PACKING_2X8_PADHI,
+ .order = SOC_MBUS_ORDER_BE,
+ },
+}, {
+ .code = V4L2_MBUS_FMT_YUYV8_1_5X8,
+ .fmt = {
+ .fourcc = V4L2_PIX_FMT_YUV420,
+ .name = "YUYV 4:2:0",
+ .bits_per_sample = 8,
+ .packing = SOC_MBUS_PACKING_1_5X8,
+ .order = SOC_MBUS_ORDER_LE,
+ },
+}, {
+ .code = V4L2_MBUS_FMT_YVYU8_1_5X8,
+ .fmt = {
+ .fourcc = V4L2_PIX_FMT_YVU420,
+ .name = "YVYU 4:2:0",
+ .bits_per_sample = 8,
+ .packing = SOC_MBUS_PACKING_1_5X8,
+ .order = SOC_MBUS_ORDER_LE,
+ },
+}, {
+ .code = V4L2_MBUS_FMT_UYVY8_1X16,
+ .fmt = {
+ .fourcc = V4L2_PIX_FMT_UYVY,
+ .name = "UYVY 16bit",
+ .bits_per_sample = 16,
+ .packing = SOC_MBUS_PACKING_EXTEND16,
+ .order = SOC_MBUS_ORDER_LE,
+ },
+}, {
+ .code = V4L2_MBUS_FMT_VYUY8_1X16,
+ .fmt = {
+ .fourcc = V4L2_PIX_FMT_VYUY,
+ .name = "VYUY 16bit",
+ .bits_per_sample = 16,
+ .packing = SOC_MBUS_PACKING_EXTEND16,
+ .order = SOC_MBUS_ORDER_LE,
+ },
+}, {
+ .code = V4L2_MBUS_FMT_YUYV8_1X16,
+ .fmt = {
+ .fourcc = V4L2_PIX_FMT_YUYV,
+ .name = "YUYV 16bit",
+ .bits_per_sample = 16,
+ .packing = SOC_MBUS_PACKING_EXTEND16,
+ .order = SOC_MBUS_ORDER_LE,
+ },
+}, {
+ .code = V4L2_MBUS_FMT_YVYU8_1X16,
+ .fmt = {
+ .fourcc = V4L2_PIX_FMT_YVYU,
+ .name = "YVYU 16bit",
+ .bits_per_sample = 16,
+ .packing = SOC_MBUS_PACKING_EXTEND16,
+ .order = SOC_MBUS_ORDER_LE,
+ },
+}, {
+ .code = V4L2_MBUS_FMT_SGRBG8_1X8,
+ .fmt = {
+ .fourcc = V4L2_PIX_FMT_SGRBG8,
+ .name = "Bayer 8 GRBG",
+ .bits_per_sample = 8,
+ .packing = SOC_MBUS_PACKING_NONE,
+ .order = SOC_MBUS_ORDER_LE,
+ },
+}, {
+ .code = V4L2_MBUS_FMT_SGRBG10_DPCM8_1X8,
+ .fmt = {
+ .fourcc = V4L2_PIX_FMT_SGRBG10DPCM8,
+ .name = "Bayer 10 BGGR DPCM 8",
+ .bits_per_sample = 8,
+ .packing = SOC_MBUS_PACKING_NONE,
+ .order = SOC_MBUS_ORDER_LE,
+ },
+}, {
+ .code = V4L2_MBUS_FMT_SGBRG10_1X10,
+ .fmt = {
+ .fourcc = V4L2_PIX_FMT_SGBRG10,
+ .name = "Bayer 10 GBRG",
+ .bits_per_sample = 10,
+ .packing = SOC_MBUS_PACKING_EXTEND16,
+ .order = SOC_MBUS_ORDER_LE,
+ },
+}, {
+ .code = V4L2_MBUS_FMT_SGRBG10_1X10,
+ .fmt = {
+ .fourcc = V4L2_PIX_FMT_SGRBG10,
+ .name = "Bayer 10 GRBG",
+ .bits_per_sample = 10,
+ .packing = SOC_MBUS_PACKING_EXTEND16,
+ .order = SOC_MBUS_ORDER_LE,
+ },
+}, {
+ .code = V4L2_MBUS_FMT_SRGGB10_1X10,
+ .fmt = {
+ .fourcc = V4L2_PIX_FMT_SRGGB10,
+ .name = "Bayer 10 RGGB",
+ .bits_per_sample = 10,
+ .packing = SOC_MBUS_PACKING_EXTEND16,
+ .order = SOC_MBUS_ORDER_LE,
+ },
+}, {
+ .code = V4L2_MBUS_FMT_SBGGR12_1X12,
+ .fmt = {
+ .fourcc = V4L2_PIX_FMT_SBGGR12,
+ .name = "Bayer 12 BGGR",
+ .bits_per_sample = 12,
+ .packing = SOC_MBUS_PACKING_EXTEND16,
+ .order = SOC_MBUS_ORDER_LE,
+ },
+}, {
+ .code = V4L2_MBUS_FMT_SGBRG12_1X12,
+ .fmt = {
+ .fourcc = V4L2_PIX_FMT_SGBRG12,
+ .name = "Bayer 12 GBRG",
+ .bits_per_sample = 12,
+ .packing = SOC_MBUS_PACKING_EXTEND16,
+ .order = SOC_MBUS_ORDER_LE,
+ },
+}, {
+ .code = V4L2_MBUS_FMT_SGRBG12_1X12,
+ .fmt = {
+ .fourcc = V4L2_PIX_FMT_SGRBG12,
+ .name = "Bayer 12 GRBG",
+ .bits_per_sample = 12,
+ .packing = SOC_MBUS_PACKING_EXTEND16,
+ .order = SOC_MBUS_ORDER_LE,
+ },
+}, {
+ .code = V4L2_MBUS_FMT_SRGGB12_1X12,
+ .fmt = {
+ .fourcc = V4L2_PIX_FMT_SRGGB12,
+ .name = "Bayer 12 RGGB",
+ .bits_per_sample = 12,
+ .packing = SOC_MBUS_PACKING_EXTEND16,
+ .order = SOC_MBUS_ORDER_LE,
+ },
+},
};
-int soc_mbus_samples_per_pixel(const struct soc_mbus_pixelfmt *mf)
+int soc_mbus_samples_per_pixel(const struct soc_mbus_pixelfmt *mf,
+ unsigned int *numerator, unsigned int *denominator)
{
switch (mf->packing) {
case SOC_MBUS_PACKING_NONE:
case SOC_MBUS_PACKING_EXTEND16:
- return 1;
+ *numerator = 1;
+ *denominator = 1;
+ return 0;
case SOC_MBUS_PACKING_2X8_PADHI:
case SOC_MBUS_PACKING_2X8_PADLO:
- return 2;
+ *numerator = 2;
+ *denominator = 1;
+ return 0;
+ case SOC_MBUS_PACKING_1_5X8:
+ *numerator = 3;
+ *denominator = 2;
+ return 0;
+ case SOC_MBUS_PACKING_VARIABLE:
+ *numerator = 0;
+ *denominator = 1;
+ return 0;
}
return -EINVAL;
}
@@ -155,18 +352,34 @@
case SOC_MBUS_PACKING_2X8_PADLO:
case SOC_MBUS_PACKING_EXTEND16:
return width * 2;
+ case SOC_MBUS_PACKING_1_5X8:
+ return width * 3 / 2;
+ case SOC_MBUS_PACKING_VARIABLE:
+ return 0;
}
return -EINVAL;
}
EXPORT_SYMBOL(soc_mbus_bytes_per_line);
+const struct soc_mbus_pixelfmt *soc_mbus_find_fmtdesc(
+ enum v4l2_mbus_pixelcode code,
+ const struct soc_mbus_lookup *lookup,
+ int n)
+{
+ int i;
+
+ for (i = 0; i < n; i++)
+ if (lookup[i].code == code)
+ return &lookup[i].fmt;
+
+ return NULL;
+}
+EXPORT_SYMBOL(soc_mbus_find_fmtdesc);
+
const struct soc_mbus_pixelfmt *soc_mbus_get_fmtdesc(
enum v4l2_mbus_pixelcode code)
{
- if (code - V4L2_MBUS_FMT_FIXED > ARRAY_SIZE(mbus_fmt) ||
- code <= V4L2_MBUS_FMT_FIXED)
- return NULL;
- return mbus_fmt + code - V4L2_MBUS_FMT_FIXED - 1;
+ return soc_mbus_find_fmtdesc(code, mbus_fmt, ARRAY_SIZE(mbus_fmt));
}
EXPORT_SYMBOL(soc_mbus_get_fmtdesc);
diff --git a/drivers/media/video/tveeprom.c b/drivers/media/video/tveeprom.c
index 07fabdd..6103d1b 100644
--- a/drivers/media/video/tveeprom.c
+++ b/drivers/media/video/tveeprom.c
@@ -267,21 +267,27 @@
{ TUNER_ABSENT, "Xceive XC4000"},
{ TUNER_ABSENT, "Dibcom 7070"},
{ TUNER_PHILIPS_TDA8290, "NXP 18271C2"},
- { TUNER_ABSENT, "unknown"},
- { TUNER_ABSENT, "unknown"},
- { TUNER_ABSENT, "unknown"},
- { TUNER_ABSENT, "unknown"},
+ { TUNER_ABSENT, "Siano SMS1010"},
+ { TUNER_ABSENT, "Siano SMS1150"},
+ { TUNER_ABSENT, "MaxLinear 5007"},
+ { TUNER_ABSENT, "TCL M09WPP_2P_E"},
/* 160-169 */
- { TUNER_ABSENT, "unknown"},
- { TUNER_ABSENT, "unknown"},
- { TUNER_ABSENT, "unknown"},
- { TUNER_ABSENT, "unknown"},
- { TUNER_ABSENT, "unknown"},
- { TUNER_ABSENT, "unknown"},
- { TUNER_ABSENT, "unknown"},
- { TUNER_ABSENT, "unknown"},
+ { TUNER_ABSENT, "Siano SMS1180"},
+ { TUNER_ABSENT, "Maxim_MAX2165"},
+ { TUNER_ABSENT, "Siano SMS1140"},
+ { TUNER_ABSENT, "Siano SMS1150 B1"},
+ { TUNER_ABSENT, "MaxLinear 111"},
+ { TUNER_ABSENT, "Dibcom 7770"},
+ { TUNER_ABSENT, "Siano SMS1180VNS"},
+ { TUNER_ABSENT, "Siano SMS1184"},
{ TUNER_PHILIPS_FQ1236_MK5, "TCL M30WTP-4N-E"},
- { TUNER_ABSENT, "unknown"},
+ { TUNER_ABSENT, "TCL_M11WPP_2PN_E"},
+ /* 170-179 */
+ { TUNER_ABSENT, "MaxLinear 301"},
+ { TUNER_ABSENT, "Mirics MSi001"},
+ { TUNER_ABSENT, "MaxLinear MxL241SF"},
+ { TUNER_ABSENT, "Xceive XC5000C"},
+ { TUNER_ABSENT, "Montage M68TS2020"},
};
/* Use V4L2_IDENT_AMBIGUOUS for those audio 'chips' that are
diff --git a/drivers/media/video/usbvision/usbvision-cards.c b/drivers/media/video/usbvision/usbvision-cards.c
index 68b998b..8f52661 100644
--- a/drivers/media/video/usbvision/usbvision-cards.c
+++ b/drivers/media/video/usbvision/usbvision-cards.c
@@ -1025,6 +1025,34 @@
.y_offset = -1,
.model_string = "Hauppauge WinTv-USB",
},
+ [MICROCAM_NTSC] = {
+ .interface = -1,
+ .codec = CODEC_WEBCAM,
+ .video_channels = 1,
+ .video_norm = V4L2_STD_NTSC,
+ .audio_channels = 0,
+ .radio = 0,
+ .vbi = 0,
+ .tuner = 0,
+ .tuner_type = 0,
+ .x_offset = 71,
+ .y_offset = 15,
+ .model_string = "Nogatech USB MicroCam NTSC (NV3000N)",
+ },
+ [MICROCAM_PAL] = {
+ .interface = -1,
+ .codec = CODEC_WEBCAM,
+ .video_channels = 1,
+ .video_norm = V4L2_STD_PAL,
+ .audio_channels = 0,
+ .radio = 0,
+ .vbi = 0,
+ .tuner = 0,
+ .tuner_type = 0,
+ .x_offset = 71,
+ .y_offset = 18,
+ .model_string = "Nogatech USB MicroCam PAL (NV3001P)",
+ },
};
const int usbvision_device_data_size = ARRAY_SIZE(usbvision_device_data);
@@ -1042,6 +1070,8 @@
{ USB_DEVICE(0x0573, 0x2d00), .driver_info = HPG_WINTV_LIVE_PAL_BG },
{ USB_DEVICE(0x0573, 0x2d01), .driver_info = HPG_WINTV_LIVE_PRO_NTSC_MN },
{ USB_DEVICE(0x0573, 0x2101), .driver_info = ZORAN_PMD_NOGATECH },
+ { USB_DEVICE(0x0573, 0x3000), .driver_info = MICROCAM_NTSC },
+ { USB_DEVICE(0x0573, 0x3001), .driver_info = MICROCAM_PAL },
{ USB_DEVICE(0x0573, 0x4100), .driver_info = NOGATECH_USB_TV_NTSC_FM },
{ USB_DEVICE(0x0573, 0x4110), .driver_info = PNY_USB_TV_NTSC_FM },
{ USB_DEVICE(0x0573, 0x4450), .driver_info = PV_PLAYTV_USB_PRO_PAL_FM },
@@ -1088,8 +1118,7 @@
{ USB_DEVICE(0x2304, 0x0110), .driver_info = PINNA_PCTV_USB_PAL_FM },
{ USB_DEVICE(0x2304, 0x0111), .driver_info = MIRO_PCTV_USB },
{ USB_DEVICE(0x2304, 0x0112), .driver_info = PINNA_PCTV_USB_NTSC_FM },
- { USB_DEVICE(0x2304, 0x0113),
- .driver_info = PINNA_PCTV_USB_NTSC_FM_V3 },
+ { USB_DEVICE(0x2304, 0x0113), .driver_info = PINNA_PCTV_USB_NTSC_FM_V3 },
{ USB_DEVICE(0x2304, 0x0210), .driver_info = PINNA_PCTV_USB_PAL_FM_V2 },
{ USB_DEVICE(0x2304, 0x0212), .driver_info = PINNA_PCTV_USB_NTSC_FM_V2 },
{ USB_DEVICE(0x2304, 0x0214), .driver_info = PINNA_PCTV_USB_PAL_FM_V3 },
diff --git a/drivers/media/video/usbvision/usbvision-cards.h b/drivers/media/video/usbvision/usbvision-cards.h
index 9c6ad22..a51cc11 100644
--- a/drivers/media/video/usbvision/usbvision-cards.h
+++ b/drivers/media/video/usbvision/usbvision-cards.h
@@ -63,5 +63,7 @@
#define PINNA_PCTV_BUNGEE_PAL_FM 62
#define HPG_WINTV 63
#define PINNA_PCTV_USB_NTSC_FM_V3 64
+#define MICROCAM_NTSC 65
+#define MICROCAM_PAL 66
extern const int usbvision_device_data_size;
diff --git a/drivers/media/video/usbvision/usbvision-core.c b/drivers/media/video/usbvision/usbvision-core.c
index c8feb0d..f344411 100644
--- a/drivers/media/video/usbvision/usbvision-core.c
+++ b/drivers/media/video/usbvision/usbvision-core.c
@@ -49,10 +49,6 @@
module_param(core_debug, int, 0644);
MODULE_PARM_DESC(core_debug, "enable debug messages [core]");
-static unsigned int force_testpattern;
-module_param(force_testpattern, int, 0644);
-MODULE_PARM_DESC(force_testpattern, "enable test pattern display [core]");
-
static int adjust_compression = 1; /* Set the compression to be adaptive */
module_param(adjust_compression, int, 0444);
MODULE_PARM_DESC(adjust_compression, " Set the ADPCM compression for the device. Default: 1 (On)");
@@ -388,90 +384,6 @@
}
/*
- * usbvision_testpattern()
- *
- * Procedure forms a test pattern (yellow grid on blue background).
- *
- * Parameters:
- * fullframe: if TRUE then entire frame is filled, otherwise the procedure
- * continues from the current scanline.
- * pmode 0: fill the frame with solid blue color (like on VCR or TV)
- * 1: Draw a colored grid
- *
- */
-static void usbvision_testpattern(struct usb_usbvision *usbvision,
- int fullframe, int pmode)
-{
- static const char proc[] = "usbvision_testpattern";
- struct usbvision_frame *frame;
- unsigned char *f;
- int num_cell = 0;
- int scan_length = 0;
- static int num_pass;
-
- if (usbvision == NULL) {
- printk(KERN_ERR "%s: usbvision == NULL\n", proc);
- return;
- }
- if (usbvision->cur_frame == NULL) {
- printk(KERN_ERR "%s: usbvision->cur_frame is NULL.\n", proc);
- return;
- }
-
- /* Grab the current frame */
- frame = usbvision->cur_frame;
-
- /* Optionally start at the beginning */
- if (fullframe) {
- frame->curline = 0;
- frame->scanlength = 0;
- }
-
- /* Form every scan line */
- for (; frame->curline < frame->frmheight; frame->curline++) {
- int i;
-
- f = frame->data + (usbvision->curwidth * 3 * frame->curline);
- for (i = 0; i < usbvision->curwidth; i++) {
- unsigned char cb = 0x80;
- unsigned char cg = 0;
- unsigned char cr = 0;
-
- if (pmode == 1) {
- if (frame->curline % 32 == 0)
- cb = 0, cg = cr = 0xFF;
- else if (i % 32 == 0) {
- if (frame->curline % 32 == 1)
- num_cell++;
- cb = 0, cg = cr = 0xFF;
- } else {
- cb =
- ((num_cell * 7) +
- num_pass) & 0xFF;
- cg =
- ((num_cell * 5) +
- num_pass * 2) & 0xFF;
- cr =
- ((num_cell * 3) +
- num_pass * 3) & 0xFF;
- }
- } else {
- /* Just the blue screen */
- }
-
- *f++ = cb;
- *f++ = cg;
- *f++ = cr;
- scan_length += 3;
- }
- }
-
- frame->grabstate = frame_state_done;
- frame->scanlength += scan_length;
- ++num_pass;
-}
-
-/*
* usbvision_decompress_alloc()
*
* allocates intermediate buffer for decompression
@@ -571,10 +483,6 @@
frame->scanstate = scan_state_lines;
frame->curline = 0;
- if (force_testpattern) {
- usbvision_testpattern(usbvision, 1, 1);
- return parse_state_next_frame;
- }
return parse_state_continue;
}
@@ -1679,6 +1587,55 @@
return err_code;
}
+/* configure webcam image sensor using the serial port */
+static int usbvision_init_webcam(struct usb_usbvision *usbvision)
+{
+ int rc;
+ int i;
+ static char init_values[38][3] = {
+ { 0x04, 0x12, 0x08 }, { 0x05, 0xff, 0xc8 }, { 0x06, 0x18, 0x07 }, { 0x07, 0x90, 0x00 },
+ { 0x09, 0x00, 0x00 }, { 0x0a, 0x00, 0x00 }, { 0x0b, 0x08, 0x00 }, { 0x0d, 0xcc, 0xcc },
+ { 0x0e, 0x13, 0x14 }, { 0x10, 0x9b, 0x83 }, { 0x11, 0x5a, 0x3f }, { 0x12, 0xe4, 0x73 },
+ { 0x13, 0x88, 0x84 }, { 0x14, 0x89, 0x80 }, { 0x15, 0x00, 0x20 }, { 0x16, 0x00, 0x00 },
+ { 0x17, 0xff, 0xa0 }, { 0x18, 0x6b, 0x20 }, { 0x19, 0x22, 0x40 }, { 0x1a, 0x10, 0x07 },
+ { 0x1b, 0x00, 0x47 }, { 0x1c, 0x03, 0xe0 }, { 0x1d, 0x00, 0x00 }, { 0x1e, 0x00, 0x00 },
+ { 0x1f, 0x00, 0x00 }, { 0x20, 0x00, 0x00 }, { 0x21, 0x00, 0x00 }, { 0x22, 0x00, 0x00 },
+ { 0x23, 0x00, 0x00 }, { 0x24, 0x00, 0x00 }, { 0x25, 0x00, 0x00 }, { 0x26, 0x00, 0x00 },
+ { 0x27, 0x00, 0x00 }, { 0x28, 0x00, 0x00 }, { 0x29, 0x00, 0x00 }, { 0x08, 0x80, 0x60 },
+ { 0x0f, 0x2d, 0x24 }, { 0x0c, 0x80, 0x80 }
+ };
+ char value[3];
+
+ /* the only difference between PAL and NTSC init_values */
+ if (usbvision_device_data[usbvision->dev_model].video_norm == V4L2_STD_NTSC)
+ init_values[4][1] = 0x34;
+
+ for (i = 0; i < sizeof(init_values) / 3; i++) {
+ usbvision_write_reg(usbvision, USBVISION_SER_MODE, USBVISION_SER_MODE_SOFT);
+ memcpy(value, init_values[i], 3);
+ rc = usb_control_msg(usbvision->dev,
+ usb_sndctrlpipe(usbvision->dev, 1),
+ USBVISION_OP_CODE,
+ USB_DIR_OUT | USB_TYPE_VENDOR |
+ USB_RECIP_ENDPOINT, 0,
+ (__u16) USBVISION_SER_DAT1, value,
+ 3, HZ);
+ if (rc < 0)
+ return rc;
+ usbvision_write_reg(usbvision, USBVISION_SER_MODE, USBVISION_SER_MODE_SIO);
+ /* write 3 bytes to the serial port using SIO mode */
+ usbvision_write_reg(usbvision, USBVISION_SER_CONT, 3 | 0x10);
+ usbvision_write_reg(usbvision, USBVISION_IOPIN_REG, 0);
+ usbvision_write_reg(usbvision, USBVISION_SER_MODE, USBVISION_SER_MODE_SOFT);
+ usbvision_write_reg(usbvision, USBVISION_IOPIN_REG, USBVISION_IO_2);
+ usbvision_write_reg(usbvision, USBVISION_SER_MODE, USBVISION_SER_MODE_SOFT | USBVISION_CLK_OUT);
+ usbvision_write_reg(usbvision, USBVISION_SER_MODE, USBVISION_SER_MODE_SOFT | USBVISION_DAT_IO);
+ usbvision_write_reg(usbvision, USBVISION_SER_MODE, USBVISION_SER_MODE_SOFT | USBVISION_CLK_OUT | USBVISION_DAT_IO);
+ }
+
+ return 0;
+}
+
/*
* usbvision_set_video_format()
*
@@ -1797,6 +1754,13 @@
frame_drop = FRAMERATE_MAX; /* We can allow the maximum here, because dropping is controlled */
+ if (usbvision_device_data[usbvision->dev_model].codec == CODEC_WEBCAM) {
+ if (usbvision_device_data[usbvision->dev_model].video_norm == V4L2_STD_PAL)
+ frame_drop = 25;
+ else
+ frame_drop = 30;
+ }
+
/* frame_drop = 7; => frame_phase = 1, 5, 9, 13, 17, 21, 25, 0, 4, 8, ...
=> frame_skip = 4;
=> frame_rate = (7 + 1) * 25 / 32 = 200 / 32 = 6.25;
@@ -2046,6 +2010,12 @@
value[7] = 0x00; /* 0x0010 -> 16 Input video v offset */
}
+ /* webcam is only 480 pixels wide, both PAL and NTSC version */
+ if (usbvision_device_data[usbvision->dev_model].codec == CODEC_WEBCAM) {
+ value[0] = 0xe0;
+ value[1] = 0x01; /* 0x01E0 -> 480 Input video line length */
+ }
+
if (usbvision_device_data[usbvision->dev_model].x_offset >= 0) {
value[4] = usbvision_device_data[usbvision->dev_model].x_offset & 0xff;
value[5] = (usbvision_device_data[usbvision->dev_model].x_offset & 0x0300) >> 8;
@@ -2148,7 +2118,7 @@
(__u16) USBVISION_DRM_PRM1, value, 8, HZ);
if (rc < 0) {
- dev_err(&usbvision->dev->dev, "%sERROR=%d\n", __func__, rc);
+ dev_err(&usbvision->dev->dev, "%s: ERROR=%d\n", __func__, rc);
return rc;
}
@@ -2180,8 +2150,15 @@
usbvision_write_reg(usbvision, USBVISION_PWR_REG,
USBVISION_SSPND_EN | USBVISION_RES2);
+ if (usbvision_device_data[usbvision->dev_model].codec == CODEC_WEBCAM) {
+ usbvision_write_reg(usbvision, USBVISION_VIN_REG1,
+ USBVISION_16_422_SYNC | USBVISION_HVALID_PO);
+ usbvision_write_reg(usbvision, USBVISION_VIN_REG2,
+ USBVISION_NOHVALID | USBVISION_KEEP_BLANK);
+ }
usbvision_write_reg(usbvision, USBVISION_PWR_REG,
USBVISION_SSPND_EN | USBVISION_PWR_VID);
+ mdelay(10);
err_code = usbvision_write_reg(usbvision, USBVISION_PWR_REG,
USBVISION_SSPND_EN | USBVISION_PWR_VID | USBVISION_RES2);
if (err_code == 1)
@@ -2310,6 +2287,8 @@
int usbvision_setup(struct usb_usbvision *usbvision, int format)
{
+ if (usbvision_device_data[usbvision->dev_model].codec == CODEC_WEBCAM)
+ usbvision_init_webcam(usbvision);
usbvision_set_video_format(usbvision, format);
usbvision_set_dram_settings(usbvision);
usbvision_set_compress_params(usbvision);
diff --git a/drivers/media/video/usbvision/usbvision-i2c.c b/drivers/media/video/usbvision/usbvision-i2c.c
index 05b1344..d7f9751 100644
--- a/drivers/media/video/usbvision/usbvision-i2c.c
+++ b/drivers/media/video/usbvision/usbvision-i2c.c
@@ -222,7 +222,7 @@
i2c_set_adapdata(&usbvision->i2c_adap, &usbvision->v4l2_dev);
if (usbvision_write_reg(usbvision, USBVISION_SER_MODE, USBVISION_IIC_LRNACK) < 0) {
- printk(KERN_ERR "usbvision_register: can't write reg\n");
+ printk(KERN_ERR "usbvision_i2c_register: can't write reg\n");
return -EBUSY;
}
diff --git a/drivers/media/video/usbvision/usbvision-video.c b/drivers/media/video/usbvision/usbvision-video.c
index 9855fbe..ea8ea8a 100644
--- a/drivers/media/video/usbvision/usbvision-video.c
+++ b/drivers/media/video/usbvision/usbvision-video.c
@@ -1471,7 +1471,8 @@
/* This should be here to make i2c clients to be able to register */
/* first switch off audio */
- usbvision_audio_off(usbvision);
+ if (usbvision_device_data[model].audio_channels > 0)
+ usbvision_audio_off(usbvision);
if (!power_on_at_open) {
/* and then power up the noisy tuner */
usbvision_power_on(usbvision);
diff --git a/drivers/media/video/usbvision/usbvision.h b/drivers/media/video/usbvision/usbvision.h
index 8074787..43cf61f 100644
--- a/drivers/media/video/usbvision/usbvision.h
+++ b/drivers/media/video/usbvision/usbvision.h
@@ -59,6 +59,11 @@
#define USBVISION_AUDIO_RADIO 2
#define USBVISION_AUDIO_MUTE 3
#define USBVISION_SER_MODE 0x07
+ #define USBVISION_CLK_OUT (1 << 0)
+ #define USBVISION_DAT_IO (1 << 1)
+ #define USBVISION_SENS_OUT (1 << 2)
+ #define USBVISION_SER_MODE_SOFT (0 << 4)
+ #define USBVISION_SER_MODE_SIO (1 << 4)
#define USBVISION_SER_ADRS 0x08
#define USBVISION_SER_CONT 0x09
#define USBVISION_SER_DAT1 0x0A
@@ -328,6 +333,7 @@
#define CODEC_SAA7113 7113
#define CODEC_SAA7111 7111
+#define CODEC_WEBCAM 3000
#define BRIDGE_NT1003 1003
#define BRIDGE_NT1004 1004
#define BRIDGE_NT1005 1005
diff --git a/drivers/media/video/uvc/uvc_ctrl.c b/drivers/media/video/uvc/uvc_ctrl.c
index 59f8a9a..a4db26f 100644
--- a/drivers/media/video/uvc/uvc_ctrl.c
+++ b/drivers/media/video/uvc/uvc_ctrl.c
@@ -42,281 +42,313 @@
.selector = UVC_PU_BRIGHTNESS_CONTROL,
.index = 0,
.size = 2,
- .flags = UVC_CONTROL_SET_CUR | UVC_CONTROL_GET_RANGE
- | UVC_CONTROL_RESTORE,
+ .flags = UVC_CTRL_FLAG_SET_CUR
+ | UVC_CTRL_FLAG_GET_RANGE
+ | UVC_CTRL_FLAG_RESTORE,
},
{
.entity = UVC_GUID_UVC_PROCESSING,
.selector = UVC_PU_CONTRAST_CONTROL,
.index = 1,
.size = 2,
- .flags = UVC_CONTROL_SET_CUR | UVC_CONTROL_GET_RANGE
- | UVC_CONTROL_RESTORE,
+ .flags = UVC_CTRL_FLAG_SET_CUR
+ | UVC_CTRL_FLAG_GET_RANGE
+ | UVC_CTRL_FLAG_RESTORE,
},
{
.entity = UVC_GUID_UVC_PROCESSING,
.selector = UVC_PU_HUE_CONTROL,
.index = 2,
.size = 2,
- .flags = UVC_CONTROL_SET_CUR | UVC_CONTROL_GET_RANGE
- | UVC_CONTROL_RESTORE | UVC_CONTROL_AUTO_UPDATE,
+ .flags = UVC_CTRL_FLAG_SET_CUR
+ | UVC_CTRL_FLAG_GET_RANGE
+ | UVC_CTRL_FLAG_RESTORE
+ | UVC_CTRL_FLAG_AUTO_UPDATE,
},
{
.entity = UVC_GUID_UVC_PROCESSING,
.selector = UVC_PU_SATURATION_CONTROL,
.index = 3,
.size = 2,
- .flags = UVC_CONTROL_SET_CUR | UVC_CONTROL_GET_RANGE
- | UVC_CONTROL_RESTORE,
+ .flags = UVC_CTRL_FLAG_SET_CUR
+ | UVC_CTRL_FLAG_GET_RANGE
+ | UVC_CTRL_FLAG_RESTORE,
},
{
.entity = UVC_GUID_UVC_PROCESSING,
.selector = UVC_PU_SHARPNESS_CONTROL,
.index = 4,
.size = 2,
- .flags = UVC_CONTROL_SET_CUR | UVC_CONTROL_GET_RANGE
- | UVC_CONTROL_RESTORE,
+ .flags = UVC_CTRL_FLAG_SET_CUR
+ | UVC_CTRL_FLAG_GET_RANGE
+ | UVC_CTRL_FLAG_RESTORE,
},
{
.entity = UVC_GUID_UVC_PROCESSING,
.selector = UVC_PU_GAMMA_CONTROL,
.index = 5,
.size = 2,
- .flags = UVC_CONTROL_SET_CUR | UVC_CONTROL_GET_RANGE
- | UVC_CONTROL_RESTORE,
+ .flags = UVC_CTRL_FLAG_SET_CUR
+ | UVC_CTRL_FLAG_GET_RANGE
+ | UVC_CTRL_FLAG_RESTORE,
},
{
.entity = UVC_GUID_UVC_PROCESSING,
.selector = UVC_PU_WHITE_BALANCE_TEMPERATURE_CONTROL,
.index = 6,
.size = 2,
- .flags = UVC_CONTROL_SET_CUR | UVC_CONTROL_GET_RANGE
- | UVC_CONTROL_RESTORE | UVC_CONTROL_AUTO_UPDATE,
+ .flags = UVC_CTRL_FLAG_SET_CUR
+ | UVC_CTRL_FLAG_GET_RANGE
+ | UVC_CTRL_FLAG_RESTORE
+ | UVC_CTRL_FLAG_AUTO_UPDATE,
},
{
.entity = UVC_GUID_UVC_PROCESSING,
.selector = UVC_PU_WHITE_BALANCE_COMPONENT_CONTROL,
.index = 7,
.size = 4,
- .flags = UVC_CONTROL_SET_CUR | UVC_CONTROL_GET_RANGE
- | UVC_CONTROL_RESTORE | UVC_CONTROL_AUTO_UPDATE,
+ .flags = UVC_CTRL_FLAG_SET_CUR
+ | UVC_CTRL_FLAG_GET_RANGE
+ | UVC_CTRL_FLAG_RESTORE
+ | UVC_CTRL_FLAG_AUTO_UPDATE,
},
{
.entity = UVC_GUID_UVC_PROCESSING,
.selector = UVC_PU_BACKLIGHT_COMPENSATION_CONTROL,
.index = 8,
.size = 2,
- .flags = UVC_CONTROL_SET_CUR | UVC_CONTROL_GET_RANGE
- | UVC_CONTROL_RESTORE,
+ .flags = UVC_CTRL_FLAG_SET_CUR
+ | UVC_CTRL_FLAG_GET_RANGE
+ | UVC_CTRL_FLAG_RESTORE,
},
{
.entity = UVC_GUID_UVC_PROCESSING,
.selector = UVC_PU_GAIN_CONTROL,
.index = 9,
.size = 2,
- .flags = UVC_CONTROL_SET_CUR | UVC_CONTROL_GET_RANGE
- | UVC_CONTROL_RESTORE,
+ .flags = UVC_CTRL_FLAG_SET_CUR
+ | UVC_CTRL_FLAG_GET_RANGE
+ | UVC_CTRL_FLAG_RESTORE,
},
{
.entity = UVC_GUID_UVC_PROCESSING,
.selector = UVC_PU_POWER_LINE_FREQUENCY_CONTROL,
.index = 10,
.size = 1,
- .flags = UVC_CONTROL_SET_CUR | UVC_CONTROL_GET_CUR
- | UVC_CONTROL_GET_DEF | UVC_CONTROL_RESTORE,
+ .flags = UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_CUR
+ | UVC_CTRL_FLAG_GET_DEF | UVC_CTRL_FLAG_RESTORE,
},
{
.entity = UVC_GUID_UVC_PROCESSING,
.selector = UVC_PU_HUE_AUTO_CONTROL,
.index = 11,
.size = 1,
- .flags = UVC_CONTROL_SET_CUR | UVC_CONTROL_GET_CUR
- | UVC_CONTROL_GET_DEF | UVC_CONTROL_RESTORE,
+ .flags = UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_CUR
+ | UVC_CTRL_FLAG_GET_DEF | UVC_CTRL_FLAG_RESTORE,
},
{
.entity = UVC_GUID_UVC_PROCESSING,
.selector = UVC_PU_WHITE_BALANCE_TEMPERATURE_AUTO_CONTROL,
.index = 12,
.size = 1,
- .flags = UVC_CONTROL_SET_CUR | UVC_CONTROL_GET_CUR
- | UVC_CONTROL_GET_DEF | UVC_CONTROL_RESTORE,
+ .flags = UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_CUR
+ | UVC_CTRL_FLAG_GET_DEF | UVC_CTRL_FLAG_RESTORE,
},
{
.entity = UVC_GUID_UVC_PROCESSING,
.selector = UVC_PU_WHITE_BALANCE_COMPONENT_AUTO_CONTROL,
.index = 13,
.size = 1,
- .flags = UVC_CONTROL_SET_CUR | UVC_CONTROL_GET_CUR
- | UVC_CONTROL_GET_DEF | UVC_CONTROL_RESTORE,
+ .flags = UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_CUR
+ | UVC_CTRL_FLAG_GET_DEF | UVC_CTRL_FLAG_RESTORE,
},
{
.entity = UVC_GUID_UVC_PROCESSING,
.selector = UVC_PU_DIGITAL_MULTIPLIER_CONTROL,
.index = 14,
.size = 2,
- .flags = UVC_CONTROL_SET_CUR | UVC_CONTROL_GET_RANGE
- | UVC_CONTROL_RESTORE,
+ .flags = UVC_CTRL_FLAG_SET_CUR
+ | UVC_CTRL_FLAG_GET_RANGE
+ | UVC_CTRL_FLAG_RESTORE,
},
{
.entity = UVC_GUID_UVC_PROCESSING,
.selector = UVC_PU_DIGITAL_MULTIPLIER_LIMIT_CONTROL,
.index = 15,
.size = 2,
- .flags = UVC_CONTROL_SET_CUR | UVC_CONTROL_GET_RANGE
- | UVC_CONTROL_RESTORE,
+ .flags = UVC_CTRL_FLAG_SET_CUR
+ | UVC_CTRL_FLAG_GET_RANGE
+ | UVC_CTRL_FLAG_RESTORE,
},
{
.entity = UVC_GUID_UVC_PROCESSING,
.selector = UVC_PU_ANALOG_VIDEO_STANDARD_CONTROL,
.index = 16,
.size = 1,
- .flags = UVC_CONTROL_GET_CUR,
+ .flags = UVC_CTRL_FLAG_GET_CUR,
},
{
.entity = UVC_GUID_UVC_PROCESSING,
.selector = UVC_PU_ANALOG_LOCK_STATUS_CONTROL,
.index = 17,
.size = 1,
- .flags = UVC_CONTROL_GET_CUR,
+ .flags = UVC_CTRL_FLAG_GET_CUR,
},
{
.entity = UVC_GUID_UVC_CAMERA,
.selector = UVC_CT_SCANNING_MODE_CONTROL,
.index = 0,
.size = 1,
- .flags = UVC_CONTROL_SET_CUR | UVC_CONTROL_GET_CUR
- | UVC_CONTROL_RESTORE,
+ .flags = UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_CUR
+ | UVC_CTRL_FLAG_RESTORE,
},
{
.entity = UVC_GUID_UVC_CAMERA,
.selector = UVC_CT_AE_MODE_CONTROL,
.index = 1,
.size = 1,
- .flags = UVC_CONTROL_SET_CUR | UVC_CONTROL_GET_CUR
- | UVC_CONTROL_GET_DEF | UVC_CONTROL_GET_RES
- | UVC_CONTROL_RESTORE,
+ .flags = UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_CUR
+ | UVC_CTRL_FLAG_GET_DEF | UVC_CTRL_FLAG_GET_RES
+ | UVC_CTRL_FLAG_RESTORE,
},
{
.entity = UVC_GUID_UVC_CAMERA,
.selector = UVC_CT_AE_PRIORITY_CONTROL,
.index = 2,
.size = 1,
- .flags = UVC_CONTROL_SET_CUR | UVC_CONTROL_GET_CUR
- | UVC_CONTROL_RESTORE,
+ .flags = UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_CUR
+ | UVC_CTRL_FLAG_RESTORE,
},
{
.entity = UVC_GUID_UVC_CAMERA,
.selector = UVC_CT_EXPOSURE_TIME_ABSOLUTE_CONTROL,
.index = 3,
.size = 4,
- .flags = UVC_CONTROL_SET_CUR | UVC_CONTROL_GET_RANGE
- | UVC_CONTROL_RESTORE,
+ .flags = UVC_CTRL_FLAG_SET_CUR
+ | UVC_CTRL_FLAG_GET_RANGE
+ | UVC_CTRL_FLAG_RESTORE,
},
{
.entity = UVC_GUID_UVC_CAMERA,
.selector = UVC_CT_EXPOSURE_TIME_RELATIVE_CONTROL,
.index = 4,
.size = 1,
- .flags = UVC_CONTROL_SET_CUR | UVC_CONTROL_RESTORE,
+ .flags = UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_RESTORE,
},
{
.entity = UVC_GUID_UVC_CAMERA,
.selector = UVC_CT_FOCUS_ABSOLUTE_CONTROL,
.index = 5,
.size = 2,
- .flags = UVC_CONTROL_SET_CUR | UVC_CONTROL_GET_RANGE
- | UVC_CONTROL_RESTORE | UVC_CONTROL_AUTO_UPDATE,
+ .flags = UVC_CTRL_FLAG_SET_CUR
+ | UVC_CTRL_FLAG_GET_RANGE
+ | UVC_CTRL_FLAG_RESTORE
+ | UVC_CTRL_FLAG_AUTO_UPDATE,
},
{
.entity = UVC_GUID_UVC_CAMERA,
.selector = UVC_CT_FOCUS_RELATIVE_CONTROL,
.index = 6,
.size = 2,
- .flags = UVC_CONTROL_SET_CUR | UVC_CONTROL_GET_MIN
- | UVC_CONTROL_GET_MAX | UVC_CONTROL_GET_RES
- | UVC_CONTROL_GET_DEF | UVC_CONTROL_AUTO_UPDATE,
+ .flags = UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_MIN
+ | UVC_CTRL_FLAG_GET_MAX | UVC_CTRL_FLAG_GET_RES
+ | UVC_CTRL_FLAG_GET_DEF
+ | UVC_CTRL_FLAG_AUTO_UPDATE,
},
{
.entity = UVC_GUID_UVC_CAMERA,
.selector = UVC_CT_IRIS_ABSOLUTE_CONTROL,
.index = 7,
.size = 2,
- .flags = UVC_CONTROL_SET_CUR | UVC_CONTROL_GET_RANGE
- | UVC_CONTROL_RESTORE | UVC_CONTROL_AUTO_UPDATE,
+ .flags = UVC_CTRL_FLAG_SET_CUR
+ | UVC_CTRL_FLAG_GET_RANGE
+ | UVC_CTRL_FLAG_RESTORE
+ | UVC_CTRL_FLAG_AUTO_UPDATE,
},
{
.entity = UVC_GUID_UVC_CAMERA,
.selector = UVC_CT_IRIS_RELATIVE_CONTROL,
.index = 8,
.size = 1,
- .flags = UVC_CONTROL_SET_CUR | UVC_CONTROL_AUTO_UPDATE,
+ .flags = UVC_CTRL_FLAG_SET_CUR
+ | UVC_CTRL_FLAG_AUTO_UPDATE,
},
{
.entity = UVC_GUID_UVC_CAMERA,
.selector = UVC_CT_ZOOM_ABSOLUTE_CONTROL,
.index = 9,
.size = 2,
- .flags = UVC_CONTROL_SET_CUR | UVC_CONTROL_GET_RANGE
- | UVC_CONTROL_RESTORE | UVC_CONTROL_AUTO_UPDATE,
+ .flags = UVC_CTRL_FLAG_SET_CUR
+ | UVC_CTRL_FLAG_GET_RANGE
+ | UVC_CTRL_FLAG_RESTORE
+ | UVC_CTRL_FLAG_AUTO_UPDATE,
},
{
.entity = UVC_GUID_UVC_CAMERA,
.selector = UVC_CT_ZOOM_RELATIVE_CONTROL,
.index = 10,
.size = 3,
- .flags = UVC_CONTROL_SET_CUR | UVC_CONTROL_GET_MIN
- | UVC_CONTROL_GET_MAX | UVC_CONTROL_GET_RES
- | UVC_CONTROL_GET_DEF | UVC_CONTROL_AUTO_UPDATE,
+ .flags = UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_MIN
+ | UVC_CTRL_FLAG_GET_MAX | UVC_CTRL_FLAG_GET_RES
+ | UVC_CTRL_FLAG_GET_DEF
+ | UVC_CTRL_FLAG_AUTO_UPDATE,
},
{
.entity = UVC_GUID_UVC_CAMERA,
.selector = UVC_CT_PANTILT_ABSOLUTE_CONTROL,
.index = 11,
.size = 8,
- .flags = UVC_CONTROL_SET_CUR | UVC_CONTROL_GET_RANGE
- | UVC_CONTROL_RESTORE | UVC_CONTROL_AUTO_UPDATE,
+ .flags = UVC_CTRL_FLAG_SET_CUR
+ | UVC_CTRL_FLAG_GET_RANGE
+ | UVC_CTRL_FLAG_RESTORE
+ | UVC_CTRL_FLAG_AUTO_UPDATE,
},
{
.entity = UVC_GUID_UVC_CAMERA,
.selector = UVC_CT_PANTILT_RELATIVE_CONTROL,
.index = 12,
.size = 4,
- .flags = UVC_CONTROL_SET_CUR | UVC_CONTROL_GET_MIN
- | UVC_CONTROL_GET_MAX | UVC_CONTROL_GET_RES
- | UVC_CONTROL_GET_DEF | UVC_CONTROL_AUTO_UPDATE,
+ .flags = UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_MIN
+ | UVC_CTRL_FLAG_GET_MAX | UVC_CTRL_FLAG_GET_RES
+ | UVC_CTRL_FLAG_GET_DEF
+ | UVC_CTRL_FLAG_AUTO_UPDATE,
},
{
.entity = UVC_GUID_UVC_CAMERA,
.selector = UVC_CT_ROLL_ABSOLUTE_CONTROL,
.index = 13,
.size = 2,
- .flags = UVC_CONTROL_SET_CUR | UVC_CONTROL_GET_RANGE
- | UVC_CONTROL_RESTORE | UVC_CONTROL_AUTO_UPDATE,
+ .flags = UVC_CTRL_FLAG_SET_CUR
+ | UVC_CTRL_FLAG_GET_RANGE
+ | UVC_CTRL_FLAG_RESTORE
+ | UVC_CTRL_FLAG_AUTO_UPDATE,
},
{
.entity = UVC_GUID_UVC_CAMERA,
.selector = UVC_CT_ROLL_RELATIVE_CONTROL,
.index = 14,
.size = 2,
- .flags = UVC_CONTROL_SET_CUR | UVC_CONTROL_GET_MIN
- | UVC_CONTROL_GET_MAX | UVC_CONTROL_GET_RES
- | UVC_CONTROL_GET_DEF | UVC_CONTROL_AUTO_UPDATE,
+ .flags = UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_MIN
+ | UVC_CTRL_FLAG_GET_MAX | UVC_CTRL_FLAG_GET_RES
+ | UVC_CTRL_FLAG_GET_DEF
+ | UVC_CTRL_FLAG_AUTO_UPDATE,
},
{
.entity = UVC_GUID_UVC_CAMERA,
.selector = UVC_CT_FOCUS_AUTO_CONTROL,
.index = 17,
.size = 1,
- .flags = UVC_CONTROL_SET_CUR | UVC_CONTROL_GET_CUR
- | UVC_CONTROL_GET_DEF | UVC_CONTROL_RESTORE,
+ .flags = UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_CUR
+ | UVC_CTRL_FLAG_GET_DEF | UVC_CTRL_FLAG_RESTORE,
},
{
.entity = UVC_GUID_UVC_CAMERA,
.selector = UVC_CT_PRIVACY_CONTROL,
.index = 18,
.size = 1,
- .flags = UVC_CONTROL_SET_CUR | UVC_CONTROL_GET_CUR
- | UVC_CONTROL_RESTORE | UVC_CONTROL_AUTO_UPDATE,
+ .flags = UVC_CTRL_FLAG_SET_CUR | UVC_CTRL_FLAG_GET_CUR
+ | UVC_CTRL_FLAG_RESTORE
+ | UVC_CTRL_FLAG_AUTO_UPDATE,
},
};
@@ -816,7 +848,7 @@
{
int ret;
- if (ctrl->info.flags & UVC_CONTROL_GET_DEF) {
+ if (ctrl->info.flags & UVC_CTRL_FLAG_GET_DEF) {
ret = uvc_query_ctrl(chain->dev, UVC_GET_DEF, ctrl->entity->id,
chain->dev->intfnum, ctrl->info.selector,
uvc_ctrl_data(ctrl, UVC_CTRL_DATA_DEF),
@@ -825,7 +857,7 @@
return ret;
}
- if (ctrl->info.flags & UVC_CONTROL_GET_MIN) {
+ if (ctrl->info.flags & UVC_CTRL_FLAG_GET_MIN) {
ret = uvc_query_ctrl(chain->dev, UVC_GET_MIN, ctrl->entity->id,
chain->dev->intfnum, ctrl->info.selector,
uvc_ctrl_data(ctrl, UVC_CTRL_DATA_MIN),
@@ -833,7 +865,7 @@
if (ret < 0)
return ret;
}
- if (ctrl->info.flags & UVC_CONTROL_GET_MAX) {
+ if (ctrl->info.flags & UVC_CTRL_FLAG_GET_MAX) {
ret = uvc_query_ctrl(chain->dev, UVC_GET_MAX, ctrl->entity->id,
chain->dev->intfnum, ctrl->info.selector,
uvc_ctrl_data(ctrl, UVC_CTRL_DATA_MAX),
@@ -841,7 +873,7 @@
if (ret < 0)
return ret;
}
- if (ctrl->info.flags & UVC_CONTROL_GET_RES) {
+ if (ctrl->info.flags & UVC_CTRL_FLAG_GET_RES) {
ret = uvc_query_ctrl(chain->dev, UVC_GET_RES, ctrl->entity->id,
chain->dev->intfnum, ctrl->info.selector,
uvc_ctrl_data(ctrl, UVC_CTRL_DATA_RES),
@@ -879,9 +911,9 @@
strlcpy(v4l2_ctrl->name, mapping->name, sizeof v4l2_ctrl->name);
v4l2_ctrl->flags = 0;
- if (!(ctrl->info.flags & UVC_CONTROL_GET_CUR))
+ if (!(ctrl->info.flags & UVC_CTRL_FLAG_GET_CUR))
v4l2_ctrl->flags |= V4L2_CTRL_FLAG_WRITE_ONLY;
- if (!(ctrl->info.flags & UVC_CONTROL_SET_CUR))
+ if (!(ctrl->info.flags & UVC_CTRL_FLAG_SET_CUR))
v4l2_ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
if (!ctrl->cached) {
@@ -890,7 +922,7 @@
goto done;
}
- if (ctrl->info.flags & UVC_CONTROL_GET_DEF) {
+ if (ctrl->info.flags & UVC_CTRL_FLAG_GET_DEF) {
v4l2_ctrl->default_value = mapping->get(mapping, UVC_GET_DEF,
uvc_ctrl_data(ctrl, UVC_CTRL_DATA_DEF));
}
@@ -927,15 +959,15 @@
break;
}
- if (ctrl->info.flags & UVC_CONTROL_GET_MIN)
+ if (ctrl->info.flags & UVC_CTRL_FLAG_GET_MIN)
v4l2_ctrl->minimum = mapping->get(mapping, UVC_GET_MIN,
uvc_ctrl_data(ctrl, UVC_CTRL_DATA_MIN));
- if (ctrl->info.flags & UVC_CONTROL_GET_MAX)
+ if (ctrl->info.flags & UVC_CTRL_FLAG_GET_MAX)
v4l2_ctrl->maximum = mapping->get(mapping, UVC_GET_MAX,
uvc_ctrl_data(ctrl, UVC_CTRL_DATA_MAX));
- if (ctrl->info.flags & UVC_CONTROL_GET_RES)
+ if (ctrl->info.flags & UVC_CTRL_FLAG_GET_RES)
v4l2_ctrl->step = mapping->get(mapping, UVC_GET_RES,
uvc_ctrl_data(ctrl, UVC_CTRL_DATA_RES));
@@ -983,6 +1015,24 @@
}
menu_info = &mapping->menu_info[query_menu->index];
+
+ if (ctrl->info.flags & UVC_CTRL_FLAG_GET_RES) {
+ s32 bitmap;
+
+ if (!ctrl->cached) {
+ ret = uvc_ctrl_populate_cache(chain, ctrl);
+ if (ret < 0)
+ goto done;
+ }
+
+ bitmap = mapping->get(mapping, UVC_GET_RES,
+ uvc_ctrl_data(ctrl, UVC_CTRL_DATA_RES));
+ if (!(bitmap & menu_info->value)) {
+ ret = -EINVAL;
+ goto done;
+ }
+ }
+
strlcpy(query_menu->name, menu_info->name, sizeof query_menu->name);
done:
@@ -1039,7 +1089,7 @@
* marked as loaded in uvc_ctrl_get/uvc_ctrl_set to prevent
* uvc_ctrl_get from using the cached value.
*/
- if (ctrl->info.flags & UVC_CONTROL_AUTO_UPDATE)
+ if (ctrl->info.flags & UVC_CTRL_FLAG_AUTO_UPDATE)
ctrl->loaded = 0;
if (!ctrl->dirty)
@@ -1094,7 +1144,7 @@
int ret;
ctrl = uvc_find_control(chain, xctrl->id, &mapping);
- if (ctrl == NULL || (ctrl->info.flags & UVC_CONTROL_GET_CUR) == 0)
+ if (ctrl == NULL || (ctrl->info.flags & UVC_CTRL_FLAG_GET_CUR) == 0)
return -EINVAL;
if (!ctrl->loaded) {
@@ -1136,7 +1186,7 @@
int ret;
ctrl = uvc_find_control(chain, xctrl->id, &mapping);
- if (ctrl == NULL || (ctrl->info.flags & UVC_CONTROL_SET_CUR) == 0)
+ if (ctrl == NULL || (ctrl->info.flags & UVC_CTRL_FLAG_SET_CUR) == 0)
return -EINVAL;
/* Clamp out of range values. */
@@ -1171,6 +1221,23 @@
if (xctrl->value < 0 || xctrl->value >= mapping->menu_count)
return -ERANGE;
value = mapping->menu_info[xctrl->value].value;
+
+ /* Valid menu indices are reported by the GET_RES request for
+ * UVC controls that support it.
+ */
+ if (ctrl->info.flags & UVC_CTRL_FLAG_GET_RES) {
+ if (!ctrl->cached) {
+ ret = uvc_ctrl_populate_cache(chain, ctrl);
+ if (ret < 0)
+ return ret;
+ }
+
+ step = mapping->get(mapping, UVC_GET_RES,
+ uvc_ctrl_data(ctrl, UVC_CTRL_DATA_RES));
+ if (!(step & value))
+ return -ERANGE;
+ }
+
break;
default:
@@ -1183,7 +1250,7 @@
* operation.
*/
if (!ctrl->loaded && (ctrl->info.size * 8) != mapping->size) {
- if ((ctrl->info.flags & UVC_CONTROL_GET_CUR) == 0) {
+ if ((ctrl->info.flags & UVC_CTRL_FLAG_GET_CUR) == 0) {
memset(uvc_ctrl_data(ctrl, UVC_CTRL_DATA_CURRENT),
0, ctrl->info.size);
} else {
@@ -1230,17 +1297,17 @@
static const struct uvc_ctrl_fixup fixups[] = {
{ { USB_DEVICE(0x046d, 0x08c2) }, 9, 1,
- UVC_CONTROL_GET_MIN | UVC_CONTROL_GET_MAX |
- UVC_CONTROL_GET_DEF | UVC_CONTROL_SET_CUR |
- UVC_CONTROL_AUTO_UPDATE },
+ UVC_CTRL_FLAG_GET_MIN | UVC_CTRL_FLAG_GET_MAX |
+ UVC_CTRL_FLAG_GET_DEF | UVC_CTRL_FLAG_SET_CUR |
+ UVC_CTRL_FLAG_AUTO_UPDATE },
{ { USB_DEVICE(0x046d, 0x08cc) }, 9, 1,
- UVC_CONTROL_GET_MIN | UVC_CONTROL_GET_MAX |
- UVC_CONTROL_GET_DEF | UVC_CONTROL_SET_CUR |
- UVC_CONTROL_AUTO_UPDATE },
+ UVC_CTRL_FLAG_GET_MIN | UVC_CTRL_FLAG_GET_MAX |
+ UVC_CTRL_FLAG_GET_DEF | UVC_CTRL_FLAG_SET_CUR |
+ UVC_CTRL_FLAG_AUTO_UPDATE },
{ { USB_DEVICE(0x046d, 0x0994) }, 9, 1,
- UVC_CONTROL_GET_MIN | UVC_CONTROL_GET_MAX |
- UVC_CONTROL_GET_DEF | UVC_CONTROL_SET_CUR |
- UVC_CONTROL_AUTO_UPDATE },
+ UVC_CTRL_FLAG_GET_MIN | UVC_CTRL_FLAG_GET_MAX |
+ UVC_CTRL_FLAG_GET_DEF | UVC_CTRL_FLAG_SET_CUR |
+ UVC_CTRL_FLAG_AUTO_UPDATE },
};
unsigned int i;
@@ -1297,21 +1364,23 @@
goto done;
}
- info->flags = UVC_CONTROL_GET_MIN | UVC_CONTROL_GET_MAX
- | UVC_CONTROL_GET_RES | UVC_CONTROL_GET_DEF
- | (data[0] & UVC_CONTROL_CAP_GET ? UVC_CONTROL_GET_CUR : 0)
- | (data[0] & UVC_CONTROL_CAP_SET ? UVC_CONTROL_SET_CUR : 0)
+ info->flags = UVC_CTRL_FLAG_GET_MIN | UVC_CTRL_FLAG_GET_MAX
+ | UVC_CTRL_FLAG_GET_RES | UVC_CTRL_FLAG_GET_DEF
+ | (data[0] & UVC_CONTROL_CAP_GET ?
+ UVC_CTRL_FLAG_GET_CUR : 0)
+ | (data[0] & UVC_CONTROL_CAP_SET ?
+ UVC_CTRL_FLAG_SET_CUR : 0)
| (data[0] & UVC_CONTROL_CAP_AUTOUPDATE ?
- UVC_CONTROL_AUTO_UPDATE : 0);
+ UVC_CTRL_FLAG_AUTO_UPDATE : 0);
uvc_ctrl_fixup_xu_info(dev, ctrl, info);
uvc_trace(UVC_TRACE_CONTROL, "XU control %pUl/%u queried: len %u, "
"flags { get %u set %u auto %u }.\n",
info->entity, info->selector, info->size,
- (info->flags & UVC_CONTROL_GET_CUR) ? 1 : 0,
- (info->flags & UVC_CONTROL_SET_CUR) ? 1 : 0,
- (info->flags & UVC_CONTROL_AUTO_UPDATE) ? 1 : 0);
+ (info->flags & UVC_CTRL_FLAG_GET_CUR) ? 1 : 0,
+ (info->flags & UVC_CTRL_FLAG_SET_CUR) ? 1 : 0,
+ (info->flags & UVC_CTRL_FLAG_AUTO_UPDATE) ? 1 : 0);
done:
kfree(data);
@@ -1344,32 +1413,33 @@
}
int uvc_xu_ctrl_query(struct uvc_video_chain *chain,
- struct uvc_xu_control *xctrl, int set)
+ struct uvc_xu_control_query *xqry)
{
struct uvc_entity *entity;
- struct uvc_control *ctrl = NULL;
+ struct uvc_control *ctrl;
unsigned int i, found = 0;
- int restore = 0;
- __u8 *data;
+ __u32 reqflags;
+ __u16 size;
+ __u8 *data = NULL;
int ret;
/* Find the extension unit. */
list_for_each_entry(entity, &chain->entities, chain) {
if (UVC_ENTITY_TYPE(entity) == UVC_VC_EXTENSION_UNIT &&
- entity->id == xctrl->unit)
+ entity->id == xqry->unit)
break;
}
- if (entity->id != xctrl->unit) {
+ if (entity->id != xqry->unit) {
uvc_trace(UVC_TRACE_CONTROL, "Extension unit %u not found.\n",
- xctrl->unit);
- return -EINVAL;
+ xqry->unit);
+ return -ENOENT;
}
/* Find the control and perform delayed initialization if needed. */
for (i = 0; i < entity->ncontrols; ++i) {
ctrl = &entity->controls[i];
- if (ctrl->index == xctrl->selector - 1) {
+ if (ctrl->index == xqry->selector - 1) {
found = 1;
break;
}
@@ -1377,8 +1447,8 @@
if (!found) {
uvc_trace(UVC_TRACE_CONTROL, "Control %pUl/%u not found.\n",
- entity->extension.guidExtensionCode, xctrl->selector);
- return -EINVAL;
+ entity->extension.guidExtensionCode, xqry->selector);
+ return -ENOENT;
}
if (mutex_lock_interruptible(&chain->ctrl_mutex))
@@ -1390,43 +1460,72 @@
goto done;
}
- /* Validate control data size. */
- if (ctrl->info.size != xctrl->size) {
+ /* Validate the required buffer size and flags for the request */
+ reqflags = 0;
+ size = ctrl->info.size;
+
+ switch (xqry->query) {
+ case UVC_GET_CUR:
+ reqflags = UVC_CTRL_FLAG_GET_CUR;
+ break;
+ case UVC_GET_MIN:
+ reqflags = UVC_CTRL_FLAG_GET_MIN;
+ break;
+ case UVC_GET_MAX:
+ reqflags = UVC_CTRL_FLAG_GET_MAX;
+ break;
+ case UVC_GET_DEF:
+ reqflags = UVC_CTRL_FLAG_GET_DEF;
+ break;
+ case UVC_GET_RES:
+ reqflags = UVC_CTRL_FLAG_GET_RES;
+ break;
+ case UVC_SET_CUR:
+ reqflags = UVC_CTRL_FLAG_SET_CUR;
+ break;
+ case UVC_GET_LEN:
+ size = 2;
+ break;
+ case UVC_GET_INFO:
+ size = 1;
+ break;
+ default:
ret = -EINVAL;
goto done;
}
- if ((set && !(ctrl->info.flags & UVC_CONTROL_SET_CUR)) ||
- (!set && !(ctrl->info.flags & UVC_CONTROL_GET_CUR))) {
- ret = -EINVAL;
+ if (size != xqry->size) {
+ ret = -ENOBUFS;
goto done;
}
- memcpy(uvc_ctrl_data(ctrl, UVC_CTRL_DATA_BACKUP),
- uvc_ctrl_data(ctrl, UVC_CTRL_DATA_CURRENT),
- ctrl->info.size);
- data = uvc_ctrl_data(ctrl, UVC_CTRL_DATA_CURRENT);
- restore = set;
+ if (reqflags && !(ctrl->info.flags & reqflags)) {
+ ret = -EBADRQC;
+ goto done;
+ }
- if (set && copy_from_user(data, xctrl->data, xctrl->size)) {
+ data = kmalloc(size, GFP_KERNEL);
+ if (data == NULL) {
+ ret = -ENOMEM;
+ goto done;
+ }
+
+ if (xqry->query == UVC_SET_CUR &&
+ copy_from_user(data, xqry->data, size)) {
ret = -EFAULT;
goto done;
}
- ret = uvc_query_ctrl(chain->dev, set ? UVC_SET_CUR : UVC_GET_CUR,
- xctrl->unit, chain->dev->intfnum, xctrl->selector,
- data, xctrl->size);
+ ret = uvc_query_ctrl(chain->dev, xqry->query, xqry->unit,
+ chain->dev->intfnum, xqry->selector, data, size);
if (ret < 0)
goto done;
- if (!set && copy_to_user(xctrl->data, data, xctrl->size))
+ if (xqry->query != UVC_SET_CUR &&
+ copy_to_user(xqry->data, data, size))
ret = -EFAULT;
done:
- if (ret && restore)
- memcpy(uvc_ctrl_data(ctrl, UVC_CTRL_DATA_CURRENT),
- uvc_ctrl_data(ctrl, UVC_CTRL_DATA_BACKUP),
- xctrl->size);
-
+ kfree(data);
mutex_unlock(&chain->ctrl_mutex);
return ret;
}
@@ -1458,7 +1557,7 @@
ctrl = &entity->controls[i];
if (!ctrl->initialized || !ctrl->modified ||
- (ctrl->info.flags & UVC_CONTROL_RESTORE) == 0)
+ (ctrl->info.flags & UVC_CTRL_FLAG_RESTORE) == 0)
continue;
printk(KERN_INFO "restoring control %pUl/%u/%u\n",
diff --git a/drivers/media/video/uvc/uvc_driver.c b/drivers/media/video/uvc/uvc_driver.c
index 6459b8c..823f4b3 100644
--- a/drivers/media/video/uvc/uvc_driver.c
+++ b/drivers/media/video/uvc/uvc_driver.c
@@ -84,6 +84,11 @@
.fcc = V4L2_PIX_FMT_YUV420,
},
{
+ .name = "YUV 4:2:0 (M420)",
+ .guid = UVC_GUID_FORMAT_M420,
+ .fcc = V4L2_PIX_FMT_M420,
+ },
+ {
.name = "YUV 4:2:2 (UYVY)",
.guid = UVC_GUID_FORMAT_UYVY,
.fcc = V4L2_PIX_FMT_UYVY,
@@ -103,6 +108,11 @@
.guid = UVC_GUID_FORMAT_BY8,
.fcc = V4L2_PIX_FMT_SBGGR8,
},
+ {
+ .name = "RGB565",
+ .guid = UVC_GUID_FORMAT_RGBP,
+ .fcc = V4L2_PIX_FMT_RGB565,
+ },
};
/* ------------------------------------------------------------------------
@@ -2077,6 +2087,15 @@
.bInterfaceSubClass = 1,
.bInterfaceProtocol = 0,
.driver_info = UVC_QUIRK_STREAM_NO_FID },
+ /* Hercules Classic Silver */
+ { .match_flags = USB_DEVICE_ID_MATCH_DEVICE
+ | USB_DEVICE_ID_MATCH_INT_INFO,
+ .idVendor = 0x06f8,
+ .idProduct = 0x300c,
+ .bInterfaceClass = USB_CLASS_VIDEO,
+ .bInterfaceSubClass = 1,
+ .bInterfaceProtocol = 0,
+ .driver_info = UVC_QUIRK_FIX_BANDWIDTH },
/* ViMicro Vega */
{ .match_flags = USB_DEVICE_ID_MATCH_DEVICE
| USB_DEVICE_ID_MATCH_INT_INFO,
@@ -2123,6 +2142,15 @@
.bInterfaceSubClass = 1,
.bInterfaceProtocol = 0,
.driver_info = UVC_QUIRK_STREAM_NO_FID },
+ /* JMicron USB2.0 XGA WebCam */
+ { .match_flags = USB_DEVICE_ID_MATCH_DEVICE
+ | USB_DEVICE_ID_MATCH_INT_INFO,
+ .idVendor = 0x152d,
+ .idProduct = 0x0310,
+ .bInterfaceClass = USB_CLASS_VIDEO,
+ .bInterfaceSubClass = 1,
+ .bInterfaceProtocol = 0,
+ .driver_info = UVC_QUIRK_PROBE_MINMAX },
/* Syntek (HP Spartan) */
{ .match_flags = USB_DEVICE_ID_MATCH_DEVICE
| USB_DEVICE_ID_MATCH_INT_INFO,
diff --git a/drivers/media/video/uvc/uvc_queue.c b/drivers/media/video/uvc/uvc_queue.c
index f14581b..109a063 100644
--- a/drivers/media/video/uvc/uvc_queue.c
+++ b/drivers/media/video/uvc/uvc_queue.c
@@ -424,7 +424,7 @@
break;
}
- if (i == queue->count || size != queue->buf_size) {
+ if (i == queue->count || PAGE_ALIGN(size) != queue->buf_size) {
ret = -EINVAL;
goto done;
}
@@ -436,6 +436,7 @@
vma->vm_flags |= VM_IO;
addr = (unsigned long)queue->mem + buffer->buf.m.offset;
+#ifdef CONFIG_MMU
while (size > 0) {
page = vmalloc_to_page((void *)addr);
if ((ret = vm_insert_page(vma, start, page)) < 0)
@@ -445,6 +446,7 @@
addr += PAGE_SIZE;
size -= PAGE_SIZE;
}
+#endif
vma->vm_ops = &uvc_vm_ops;
vma->vm_private_data = buffer;
@@ -488,6 +490,36 @@
return mask;
}
+#ifndef CONFIG_MMU
+/*
+ * Get unmapped area.
+ *
+ * NO-MMU arch need this function to make mmap() work correctly.
+ */
+unsigned long uvc_queue_get_unmapped_area(struct uvc_video_queue *queue,
+ unsigned long pgoff)
+{
+ struct uvc_buffer *buffer;
+ unsigned int i;
+ unsigned long ret;
+
+ mutex_lock(&queue->mutex);
+ for (i = 0; i < queue->count; ++i) {
+ buffer = &queue->buffer[i];
+ if ((buffer->buf.m.offset >> PAGE_SHIFT) == pgoff)
+ break;
+ }
+ if (i == queue->count) {
+ ret = -EINVAL;
+ goto done;
+ }
+ ret = (unsigned long)queue->mem + buffer->buf.m.offset;
+done:
+ mutex_unlock(&queue->mutex);
+ return ret;
+}
+#endif
+
/*
* Enable or disable the video buffers queue.
*
diff --git a/drivers/media/video/uvc/uvc_v4l2.c b/drivers/media/video/uvc/uvc_v4l2.c
index 9005a8d..543a803 100644
--- a/drivers/media/video/uvc/uvc_v4l2.c
+++ b/drivers/media/video/uvc/uvc_v4l2.c
@@ -538,6 +538,20 @@
return 0;
}
+static void uvc_v4l2_ioctl_warn(void)
+{
+ static int warned;
+
+ if (warned)
+ return;
+
+ uvc_printk(KERN_INFO, "Deprecated UVCIOC_CTRL_{ADD,MAP_OLD,GET,SET} "
+ "ioctls will be removed in 2.6.42.\n");
+ uvc_printk(KERN_INFO, "See http://www.ideasonboard.org/uvc/upgrade/ "
+ "for upgrade instructions.\n");
+ warned = 1;
+}
+
static long uvc_v4l2_do_ioctl(struct file *file, unsigned int cmd, void *arg)
{
struct video_device *vdev = video_devdata(file);
@@ -1018,21 +1032,40 @@
uvc_trace(UVC_TRACE_IOCTL, "Unsupported ioctl 0x%08x\n", cmd);
return -EINVAL;
- /* Dynamic controls. */
- case UVCIOC_CTRL_ADD:
- /* Legacy ioctl, kept for API compatibility reasons */
+ /* Dynamic controls. UVCIOC_CTRL_ADD, UVCIOC_CTRL_MAP_OLD,
+ * UVCIOC_CTRL_GET and UVCIOC_CTRL_SET are deprecated and scheduled for
+ * removal in 2.6.42.
+ */
+ case __UVCIOC_CTRL_ADD:
+ uvc_v4l2_ioctl_warn();
return -EEXIST;
- case UVCIOC_CTRL_MAP_OLD:
+ case __UVCIOC_CTRL_MAP_OLD:
+ uvc_v4l2_ioctl_warn();
+ case __UVCIOC_CTRL_MAP:
case UVCIOC_CTRL_MAP:
return uvc_ioctl_ctrl_map(chain, arg,
- cmd == UVCIOC_CTRL_MAP_OLD);
+ cmd == __UVCIOC_CTRL_MAP_OLD);
- case UVCIOC_CTRL_GET:
- return uvc_xu_ctrl_query(chain, arg, 0);
+ case __UVCIOC_CTRL_GET:
+ case __UVCIOC_CTRL_SET:
+ {
+ struct uvc_xu_control *xctrl = arg;
+ struct uvc_xu_control_query xqry = {
+ .unit = xctrl->unit,
+ .selector = xctrl->selector,
+ .query = cmd == __UVCIOC_CTRL_GET
+ ? UVC_GET_CUR : UVC_SET_CUR,
+ .size = xctrl->size,
+ .data = xctrl->data,
+ };
- case UVCIOC_CTRL_SET:
- return uvc_xu_ctrl_query(chain, arg, 1);
+ uvc_v4l2_ioctl_warn();
+ return uvc_xu_ctrl_query(chain, &xqry);
+ }
+
+ case UVCIOC_CTRL_QUERY:
+ return uvc_xu_ctrl_query(chain, arg);
default:
uvc_trace(UVC_TRACE_IOCTL, "Unknown ioctl 0x%08x\n", cmd);
@@ -1081,6 +1114,20 @@
return uvc_queue_poll(&stream->queue, file, wait);
}
+#ifndef CONFIG_MMU
+static unsigned long uvc_v4l2_get_unmapped_area(struct file *file,
+ unsigned long addr, unsigned long len, unsigned long pgoff,
+ unsigned long flags)
+{
+ struct uvc_fh *handle = file->private_data;
+ struct uvc_streaming *stream = handle->stream;
+
+ uvc_trace(UVC_TRACE_CALLS, "uvc_v4l2_get_unmapped_area\n");
+
+ return uvc_queue_get_unmapped_area(&stream->queue, pgoff);
+}
+#endif
+
const struct v4l2_file_operations uvc_fops = {
.owner = THIS_MODULE,
.open = uvc_v4l2_open,
@@ -1089,5 +1136,8 @@
.read = uvc_v4l2_read,
.mmap = uvc_v4l2_mmap,
.poll = uvc_v4l2_poll,
+#ifndef CONFIG_MMU
+ .get_unmapped_area = uvc_v4l2_get_unmapped_area,
+#endif
};
diff --git a/drivers/media/video/uvc/uvcvideo.h b/drivers/media/video/uvc/uvcvideo.h
index 45f01e7..7cf224b 100644
--- a/drivers/media/video/uvc/uvcvideo.h
+++ b/drivers/media/video/uvc/uvcvideo.h
@@ -4,6 +4,14 @@
#include <linux/kernel.h>
#include <linux/videodev2.h>
+#ifndef __KERNEL__
+/*
+ * This header provides binary compatibility with applications using the private
+ * uvcvideo API. This API is deprecated and will be removed in 2.6.42.
+ * Applications should be recompiled against the public linux/uvcvideo.h header.
+ */
+#warn "The uvcvideo.h header is deprecated, use linux/uvcvideo.h instead."
+
/*
* Dynamic controls
*/
@@ -23,32 +31,18 @@
#define UVC_CONTROL_GET_MAX (1 << 3)
#define UVC_CONTROL_GET_RES (1 << 4)
#define UVC_CONTROL_GET_DEF (1 << 5)
-/* Control should be saved at suspend and restored at resume. */
#define UVC_CONTROL_RESTORE (1 << 6)
-/* Control can be updated by the camera. */
#define UVC_CONTROL_AUTO_UPDATE (1 << 7)
#define UVC_CONTROL_GET_RANGE (UVC_CONTROL_GET_CUR | UVC_CONTROL_GET_MIN | \
UVC_CONTROL_GET_MAX | UVC_CONTROL_GET_RES | \
UVC_CONTROL_GET_DEF)
-struct uvc_xu_control_info {
- __u8 entity[16];
- __u8 index;
- __u8 selector;
- __u16 size;
- __u32 flags;
-};
-
struct uvc_menu_info {
__u32 value;
__u8 name[32];
};
-struct uvc_xu_control_mapping_old {
- __u8 reserved[64];
-};
-
struct uvc_xu_control_mapping {
__u32 id;
__u8 name[32];
@@ -57,7 +51,7 @@
__u8 size;
__u8 offset;
- enum v4l2_ctrl_type v4l2_type;
+ __u32 v4l2_type;
__u32 data_type;
struct uvc_menu_info __user *menu_info;
@@ -66,6 +60,20 @@
__u32 reserved[4];
};
+#endif
+
+struct uvc_xu_control_info {
+ __u8 entity[16];
+ __u8 index;
+ __u8 selector;
+ __u16 size;
+ __u32 flags;
+};
+
+struct uvc_xu_control_mapping_old {
+ __u8 reserved[64];
+};
+
struct uvc_xu_control {
__u8 unit;
__u8 selector;
@@ -73,16 +81,25 @@
__u8 __user *data;
};
+#ifndef __KERNEL__
#define UVCIOC_CTRL_ADD _IOW('U', 1, struct uvc_xu_control_info)
#define UVCIOC_CTRL_MAP_OLD _IOWR('U', 2, struct uvc_xu_control_mapping_old)
#define UVCIOC_CTRL_MAP _IOWR('U', 2, struct uvc_xu_control_mapping)
#define UVCIOC_CTRL_GET _IOWR('U', 3, struct uvc_xu_control)
#define UVCIOC_CTRL_SET _IOW('U', 4, struct uvc_xu_control)
+#else
+#define __UVCIOC_CTRL_ADD _IOW('U', 1, struct uvc_xu_control_info)
+#define __UVCIOC_CTRL_MAP_OLD _IOWR('U', 2, struct uvc_xu_control_mapping_old)
+#define __UVCIOC_CTRL_MAP _IOWR('U', 2, struct uvc_xu_control_mapping)
+#define __UVCIOC_CTRL_GET _IOWR('U', 3, struct uvc_xu_control)
+#define __UVCIOC_CTRL_SET _IOW('U', 4, struct uvc_xu_control)
+#endif
#ifdef __KERNEL__
#include <linux/poll.h>
#include <linux/usb/video.h>
+#include <linux/uvcvideo.h>
/* --------------------------------------------------------------------------
* UVC constants
@@ -152,13 +169,19 @@
#define UVC_GUID_FORMAT_BY8 \
{ 'B', 'Y', '8', ' ', 0x00, 0x00, 0x10, 0x00, \
0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71}
+#define UVC_GUID_FORMAT_RGBP \
+ { 'R', 'G', 'B', 'P', 0x00, 0x00, 0x10, 0x00, \
+ 0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71}
+#define UVC_GUID_FORMAT_M420 \
+ { 'M', '4', '2', '0', 0x00, 0x00, 0x10, 0x00, \
+ 0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, 0x9b, 0x71}
/* ------------------------------------------------------------------------
* Driver specific constants.
*/
-#define DRIVER_VERSION_NUMBER KERNEL_VERSION(1, 0, 0)
-#define DRIVER_VERSION "v1.0.0"
+#define DRIVER_VERSION_NUMBER KERNEL_VERSION(1, 1, 0)
+#define DRIVER_VERSION "v1.1.0"
/* Number of isochronous URBs. */
#define UVC_URBS 5
@@ -580,6 +603,10 @@
struct vm_area_struct *vma);
extern unsigned int uvc_queue_poll(struct uvc_video_queue *queue,
struct file *file, poll_table *wait);
+#ifndef CONFIG_MMU
+extern unsigned long uvc_queue_get_unmapped_area(struct uvc_video_queue *queue,
+ unsigned long pgoff);
+#endif
extern int uvc_queue_allocated(struct uvc_video_queue *queue);
static inline int uvc_queue_streaming(struct uvc_video_queue *queue)
{
@@ -638,7 +665,7 @@
struct v4l2_ext_control *xctrl);
extern int uvc_xu_ctrl_query(struct uvc_video_chain *chain,
- struct uvc_xu_control *ctrl, int set);
+ struct uvc_xu_control_query *xqry);
/* Utility functions */
extern void uvc_simplify_fraction(uint32_t *numerator, uint32_t *denominator,
@@ -655,4 +682,3 @@
#endif /* __KERNEL__ */
#endif
-
diff --git a/drivers/media/video/v4l2-dev.c b/drivers/media/video/v4l2-dev.c
index 6dc7196..19d5ae2 100644
--- a/drivers/media/video/v4l2-dev.c
+++ b/drivers/media/video/v4l2-dev.c
@@ -352,6 +352,23 @@
return ret;
}
+#ifdef CONFIG_MMU
+#define v4l2_get_unmapped_area NULL
+#else
+static unsigned long v4l2_get_unmapped_area(struct file *filp,
+ unsigned long addr, unsigned long len, unsigned long pgoff,
+ unsigned long flags)
+{
+ struct video_device *vdev = video_devdata(filp);
+
+ if (!vdev->fops->get_unmapped_area)
+ return -ENOSYS;
+ if (!video_is_registered(vdev))
+ return -ENODEV;
+ return vdev->fops->get_unmapped_area(filp, addr, len, pgoff, flags);
+}
+#endif
+
static int v4l2_mmap(struct file *filp, struct vm_area_struct *vm)
{
struct video_device *vdev = video_devdata(filp);
@@ -454,6 +471,7 @@
.read = v4l2_read,
.write = v4l2_write,
.open = v4l2_open,
+ .get_unmapped_area = v4l2_get_unmapped_area,
.mmap = v4l2_mmap,
.unlocked_ioctl = v4l2_ioctl,
#ifdef CONFIG_COMPAT
diff --git a/drivers/media/video/via-camera.c b/drivers/media/video/via-camera.c
index 8c780c2..85d3048 100644
--- a/drivers/media/video/via-camera.c
+++ b/drivers/media/video/via-camera.c
@@ -29,6 +29,7 @@
#include "via-camera.h"
+MODULE_ALIAS("platform:viafb-camera");
MODULE_AUTHOR("Jonathan Corbet <corbet@lwn.net>");
MODULE_DESCRIPTION("VIA framebuffer-based camera controller driver");
MODULE_LICENSE("GPL");
diff --git a/drivers/media/video/zoran/zoran_card.c b/drivers/media/video/zoran/zoran_card.c
index 9f2bac5..79b04ac 100644
--- a/drivers/media/video/zoran/zoran_card.c
+++ b/drivers/media/video/zoran/zoran_card.c
@@ -64,14 +64,6 @@
module_param_array(card, int, NULL, 0444);
MODULE_PARM_DESC(card, "Card type");
-static int encoder[BUZ_MAX] = { [0 ... (BUZ_MAX-1)] = -1 };
-module_param_array(encoder, int, NULL, 0444);
-MODULE_PARM_DESC(encoder, "Video encoder chip");
-
-static int decoder[BUZ_MAX] = { [0 ... (BUZ_MAX-1)] = -1 };
-module_param_array(decoder, int, NULL, 0444);
-MODULE_PARM_DESC(decoder, "Video decoder chip");
-
/*
The video mem address of the video card.
The driver has a little database for some videocards
@@ -1230,7 +1222,7 @@
mutex_init(&zr->other_lock);
if (pci_enable_device(pdev))
goto zr_unreg;
- pci_read_config_byte(zr->pci_dev, PCI_CLASS_REVISION, &zr->revision);
+ zr->revision = zr->pci_dev->revision;
dprintk(1,
KERN_INFO
diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig
index 3ed3ff0..481770a 100644
--- a/drivers/mfd/Kconfig
+++ b/drivers/mfd/Kconfig
@@ -538,7 +538,7 @@
config AB8500_I2C_CORE
bool "AB8500 register access via PRCMU I2C"
- depends on AB8500_CORE && UX500_SOC_DB8500
+ depends on AB8500_CORE && MFD_DB8500_PRCMU
default y
help
This enables register access to the AB8500 chip via PRCMU I2C.
@@ -575,6 +575,26 @@
LEDs, vibrator, system power and temperature, power management
and ALSA sound.
+config MFD_DB8500_PRCMU
+ bool "ST-Ericsson DB8500 Power Reset Control Management Unit"
+ depends on UX500_SOC_DB8500
+ select MFD_CORE
+ help
+ Select this option to enable support for the DB8500 Power Reset
+ and Control Management Unit. This is basically an autonomous
+ system controller running an XP70 microprocessor, which is accessed
+ through a register map.
+
+config MFD_DB5500_PRCMU
+ bool "ST-Ericsson DB5500 Power Reset Control Management Unit"
+ depends on UX500_SOC_DB5500
+ select MFD_CORE
+ help
+ Select this option to enable support for the DB5500 Power Reset
+ and Control Management Unit. This is basically an autonomous
+ system controller running an XP70 microprocessor, which is accessed
+ through a register map.
+
config MFD_CS5535
tristate "Support for CS5535 and CS5536 southbridge core functions"
select MFD_CORE
diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile
index 419caa9..24aa444 100644
--- a/drivers/mfd/Makefile
+++ b/drivers/mfd/Makefile
@@ -74,9 +74,12 @@
obj-$(CONFIG_AB3100_OTP) += ab3100-otp.o
obj-$(CONFIG_AB3550_CORE) += ab3550-core.o
obj-$(CONFIG_AB8500_CORE) += ab8500-core.o ab8500-sysctrl.o
-obj-$(CONFIG_AB8500_I2C_CORE) += ab8500-i2c.o
obj-$(CONFIG_AB8500_DEBUG) += ab8500-debugfs.o
obj-$(CONFIG_AB8500_GPADC) += ab8500-gpadc.o
+obj-$(CONFIG_MFD_DB8500_PRCMU) += db8500-prcmu.o
+# ab8500-i2c need to come after db8500-prcmu (which provides the channel)
+obj-$(CONFIG_AB8500_I2C_CORE) += ab8500-i2c.o
+obj-$(CONFIG_MFD_DB5500_PRCMU) += db5500-prcmu.o
obj-$(CONFIG_MFD_TIMBERDALE) += timberdale.o
obj-$(CONFIG_PMIC_ADP5520) += adp5520.o
obj-$(CONFIG_LPC_SCH) += lpc_sch.o
diff --git a/drivers/mfd/ab8500-i2c.c b/drivers/mfd/ab8500-i2c.c
index 821e6b8..9be541c 100644
--- a/drivers/mfd/ab8500-i2c.c
+++ b/drivers/mfd/ab8500-i2c.c
@@ -11,8 +11,7 @@
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/mfd/ab8500.h>
-
-#include <mach/prcmu.h>
+#include <linux/mfd/db8500-prcmu.h>
static int ab8500_i2c_write(struct ab8500 *ab8500, u16 addr, u8 data)
{
diff --git a/drivers/mfd/db5500-prcmu-regs.h b/drivers/mfd/db5500-prcmu-regs.h
new file mode 100644
index 0000000..9a8e9e4
--- /dev/null
+++ b/drivers/mfd/db5500-prcmu-regs.h
@@ -0,0 +1,115 @@
+/*
+ * Copyright (C) STMicroelectronics 2009
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
+ * Author: Sundar Iyer <sundar.iyer@stericsson.com>
+ *
+ * License Terms: GNU General Public License v2
+ *
+ * PRCM Unit registers
+ */
+
+#ifndef __MACH_PRCMU_REGS_H
+#define __MACH_PRCMU_REGS_H
+
+#include <mach/hardware.h>
+
+#define PRCM_ARM_PLLDIVPS (_PRCMU_BASE + 0x118)
+#define PRCM_ARM_PLLDIVPS_ARM_BRM_RATE 0x3f
+#define PRCM_ARM_PLLDIVPS_MAX_MASK 0xf
+
+#define PRCM_PLLARM_LOCKP (_PRCMU_BASE + 0x0a8)
+#define PRCM_PLLARM_LOCKP_PRCM_PLLARM_LOCKP3 0x2
+
+#define PRCM_ARM_CHGCLKREQ (_PRCMU_BASE + 0x114)
+#define PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ 0x1
+
+#define PRCM_PLLARM_ENABLE (_PRCMU_BASE + 0x98)
+#define PRCM_PLLARM_ENABLE_PRCM_PLLARM_ENABLE 0x1
+#define PRCM_PLLARM_ENABLE_PRCM_PLLARM_COUNTON 0x100
+
+#define PRCM_ARMCLKFIX_MGT (_PRCMU_BASE + 0x0)
+#define PRCM_A9_RESETN_CLR (_PRCMU_BASE + 0x1f4)
+#define PRCM_A9_RESETN_SET (_PRCMU_BASE + 0x1f0)
+#define PRCM_ARM_LS_CLAMP (_PRCMU_BASE + 0x30c)
+#define PRCM_SRAM_A9 (_PRCMU_BASE + 0x308)
+
+/* ARM WFI Standby signal register */
+#define PRCM_ARM_WFI_STANDBY (_PRCMU_BASE + 0x130)
+#define PRCM_IOCR (_PRCMU_BASE + 0x310)
+#define PRCM_IOCR_IOFORCE 0x1
+
+/* CPU mailbox registers */
+#define PRCM_MBOX_CPU_VAL (_PRCMU_BASE + 0x0fc)
+#define PRCM_MBOX_CPU_SET (_PRCMU_BASE + 0x100)
+#define PRCM_MBOX_CPU_CLR (_PRCMU_BASE + 0x104)
+
+/* Dual A9 core interrupt management unit registers */
+#define PRCM_A9_MASK_REQ (_PRCMU_BASE + 0x328)
+#define PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ 0x1
+
+#define PRCM_A9_MASK_ACK (_PRCMU_BASE + 0x32c)
+#define PRCM_ARMITMSK31TO0 (_PRCMU_BASE + 0x11c)
+#define PRCM_ARMITMSK63TO32 (_PRCMU_BASE + 0x120)
+#define PRCM_ARMITMSK95TO64 (_PRCMU_BASE + 0x124)
+#define PRCM_ARMITMSK127TO96 (_PRCMU_BASE + 0x128)
+#define PRCM_POWER_STATE_VAL (_PRCMU_BASE + 0x25C)
+#define PRCM_ARMITVAL31TO0 (_PRCMU_BASE + 0x260)
+#define PRCM_ARMITVAL63TO32 (_PRCMU_BASE + 0x264)
+#define PRCM_ARMITVAL95TO64 (_PRCMU_BASE + 0x268)
+#define PRCM_ARMITVAL127TO96 (_PRCMU_BASE + 0x26C)
+
+#define PRCM_HOSTACCESS_REQ (_PRCMU_BASE + 0x334)
+#define ARM_WAKEUP_MODEM 0x1
+
+#define PRCM_ARM_IT1_CLEAR (_PRCMU_BASE + 0x48C)
+#define PRCM_ARM_IT1_VAL (_PRCMU_BASE + 0x494)
+#define PRCM_HOLD_EVT (_PRCMU_BASE + 0x174)
+
+#define PRCM_ITSTATUS0 (_PRCMU_BASE + 0x148)
+#define PRCM_ITSTATUS1 (_PRCMU_BASE + 0x150)
+#define PRCM_ITSTATUS2 (_PRCMU_BASE + 0x158)
+#define PRCM_ITSTATUS3 (_PRCMU_BASE + 0x160)
+#define PRCM_ITSTATUS4 (_PRCMU_BASE + 0x168)
+#define PRCM_ITSTATUS5 (_PRCMU_BASE + 0x484)
+#define PRCM_ITCLEAR5 (_PRCMU_BASE + 0x488)
+#define PRCM_ARMIT_MASKXP70_IT (_PRCMU_BASE + 0x1018)
+
+/* System reset register */
+#define PRCM_APE_SOFTRST (_PRCMU_BASE + 0x228)
+
+/* Level shifter and clamp control registers */
+#define PRCM_MMIP_LS_CLAMP_SET (_PRCMU_BASE + 0x420)
+#define PRCM_MMIP_LS_CLAMP_CLR (_PRCMU_BASE + 0x424)
+
+/* PRCMU clock/PLL/reset registers */
+#define PRCM_PLLDSI_FREQ (_PRCMU_BASE + 0x500)
+#define PRCM_PLLDSI_ENABLE (_PRCMU_BASE + 0x504)
+#define PRCM_PLLDSI_LOCKP (_PRCMU_BASE + 0x508)
+#define PRCM_LCDCLK_MGT (_PRCMU_BASE + 0x044)
+#define PRCM_MCDECLK_MGT (_PRCMU_BASE + 0x064)
+#define PRCM_HDMICLK_MGT (_PRCMU_BASE + 0x058)
+#define PRCM_TVCLK_MGT (_PRCMU_BASE + 0x07c)
+#define PRCM_DSI_PLLOUT_SEL (_PRCMU_BASE + 0x530)
+#define PRCM_DSITVCLK_DIV (_PRCMU_BASE + 0x52C)
+#define PRCM_PLLDSI_LOCKP (_PRCMU_BASE + 0x508)
+#define PRCM_APE_RESETN_SET (_PRCMU_BASE + 0x1E4)
+#define PRCM_APE_RESETN_CLR (_PRCMU_BASE + 0x1E8)
+#define PRCM_CLKOCR (_PRCMU_BASE + 0x1CC)
+
+/* ePOD and memory power signal control registers */
+#define PRCM_EPOD_C_SET (_PRCMU_BASE + 0x410)
+#define PRCM_SRAM_LS_SLEEP (_PRCMU_BASE + 0x304)
+
+/* Debug power control unit registers */
+#define PRCM_POWER_STATE_SET (_PRCMU_BASE + 0x254)
+
+/* Miscellaneous unit registers */
+#define PRCM_DSI_SW_RESET (_PRCMU_BASE + 0x324)
+#define PRCM_GPIOCR (_PRCMU_BASE + 0x138)
+#define PRCM_GPIOCR_DBG_STM_MOD_CMD1 0x800
+#define PRCM_GPIOCR_DBG_UARTMOD_CMD0 0x1
+
+
+#endif /* __MACH_PRCMU__REGS_H */
diff --git a/drivers/mfd/db5500-prcmu.c b/drivers/mfd/db5500-prcmu.c
new file mode 100644
index 0000000..9dbb3ca
--- /dev/null
+++ b/drivers/mfd/db5500-prcmu.c
@@ -0,0 +1,448 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * License Terms: GNU General Public License v2
+ * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
+ *
+ * U5500 PRCM Unit interface driver
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/mutex.h>
+#include <linux/completion.h>
+#include <linux/irq.h>
+#include <linux/jiffies.h>
+#include <linux/bitops.h>
+#include <linux/interrupt.h>
+#include <linux/mfd/db5500-prcmu.h>
+#include <mach/hardware.h>
+#include <mach/irqs.h>
+#include <mach/db5500-regs.h>
+#include "db5500-prcmu-regs.h"
+
+#define _PRCM_MB_HEADER (tcdm_base + 0xFE8)
+#define PRCM_REQ_MB0_HEADER (_PRCM_MB_HEADER + 0x0)
+#define PRCM_REQ_MB1_HEADER (_PRCM_MB_HEADER + 0x1)
+#define PRCM_REQ_MB2_HEADER (_PRCM_MB_HEADER + 0x2)
+#define PRCM_REQ_MB3_HEADER (_PRCM_MB_HEADER + 0x3)
+#define PRCM_REQ_MB4_HEADER (_PRCM_MB_HEADER + 0x4)
+#define PRCM_REQ_MB5_HEADER (_PRCM_MB_HEADER + 0x5)
+#define PRCM_REQ_MB6_HEADER (_PRCM_MB_HEADER + 0x6)
+#define PRCM_REQ_MB7_HEADER (_PRCM_MB_HEADER + 0x7)
+#define PRCM_ACK_MB0_HEADER (_PRCM_MB_HEADER + 0x8)
+#define PRCM_ACK_MB1_HEADER (_PRCM_MB_HEADER + 0x9)
+#define PRCM_ACK_MB2_HEADER (_PRCM_MB_HEADER + 0xa)
+#define PRCM_ACK_MB3_HEADER (_PRCM_MB_HEADER + 0xb)
+#define PRCM_ACK_MB4_HEADER (_PRCM_MB_HEADER + 0xc)
+#define PRCM_ACK_MB5_HEADER (_PRCM_MB_HEADER + 0xd)
+#define PRCM_ACK_MB6_HEADER (_PRCM_MB_HEADER + 0xe)
+#define PRCM_ACK_MB7_HEADER (_PRCM_MB_HEADER + 0xf)
+
+/* Req Mailboxes */
+#define PRCM_REQ_MB0 (tcdm_base + 0xFD8)
+#define PRCM_REQ_MB1 (tcdm_base + 0xFCC)
+#define PRCM_REQ_MB2 (tcdm_base + 0xFC4)
+#define PRCM_REQ_MB3 (tcdm_base + 0xFC0)
+#define PRCM_REQ_MB4 (tcdm_base + 0xF98)
+#define PRCM_REQ_MB5 (tcdm_base + 0xF90)
+#define PRCM_REQ_MB6 (tcdm_base + 0xF8C)
+#define PRCM_REQ_MB7 (tcdm_base + 0xF84)
+
+/* Ack Mailboxes */
+#define PRCM_ACK_MB0 (tcdm_base + 0xF38)
+#define PRCM_ACK_MB1 (tcdm_base + 0xF30)
+#define PRCM_ACK_MB2 (tcdm_base + 0xF24)
+#define PRCM_ACK_MB3 (tcdm_base + 0xF20)
+#define PRCM_ACK_MB4 (tcdm_base + 0xF1C)
+#define PRCM_ACK_MB5 (tcdm_base + 0xF14)
+#define PRCM_ACK_MB6 (tcdm_base + 0xF0C)
+#define PRCM_ACK_MB7 (tcdm_base + 0xF08)
+
+enum mb_return_code {
+ RC_SUCCESS,
+ RC_FAIL,
+};
+
+/* Mailbox 0 headers. */
+enum mb0_header {
+ /* request */
+ RMB0H_PWR_STATE_TRANS = 1,
+ RMB0H_WAKE_UP_CFG,
+ RMB0H_RD_WAKE_UP_ACK,
+ /* acknowledge */
+ AMB0H_WAKE_UP = 1,
+};
+
+/* Mailbox 5 headers. */
+enum mb5_header {
+ MB5H_I2C_WRITE = 1,
+ MB5H_I2C_READ,
+};
+
+/* Request mailbox 5 fields. */
+#define PRCM_REQ_MB5_I2C_SLAVE (PRCM_REQ_MB5 + 0)
+#define PRCM_REQ_MB5_I2C_REG (PRCM_REQ_MB5 + 1)
+#define PRCM_REQ_MB5_I2C_SIZE (PRCM_REQ_MB5 + 2)
+#define PRCM_REQ_MB5_I2C_DATA (PRCM_REQ_MB5 + 4)
+
+/* Acknowledge mailbox 5 fields. */
+#define PRCM_ACK_MB5_RETURN_CODE (PRCM_ACK_MB5 + 0)
+#define PRCM_ACK_MB5_I2C_DATA (PRCM_ACK_MB5 + 4)
+
+#define NUM_MB 8
+#define MBOX_BIT BIT
+#define ALL_MBOX_BITS (MBOX_BIT(NUM_MB) - 1)
+
+/*
+* Used by MCDE to setup all necessary PRCMU registers
+*/
+#define PRCMU_RESET_DSIPLL 0x00004000
+#define PRCMU_UNCLAMP_DSIPLL 0x00400800
+
+/* HDMI CLK MGT PLLSW=001 (PLLSOC0), PLLDIV=0x8, = 50 Mhz*/
+#define PRCMU_DSI_CLOCK_SETTING 0x00000128
+/* TVCLK_MGT PLLSW=001 (PLLSOC0) PLLDIV=0x13, = 19.05 MHZ */
+#define PRCMU_DSI_LP_CLOCK_SETTING 0x00000135
+#define PRCMU_PLLDSI_FREQ_SETTING 0x0004013C
+#define PRCMU_DSI_PLLOUT_SEL_SETTING 0x00000002
+#define PRCMU_ENABLE_ESCAPE_CLOCK_DIV 0x03000101
+#define PRCMU_DISABLE_ESCAPE_CLOCK_DIV 0x00000101
+
+#define PRCMU_ENABLE_PLLDSI 0x00000001
+#define PRCMU_DISABLE_PLLDSI 0x00000000
+
+#define PRCMU_DSI_RESET_SW 0x00000003
+
+#define PRCMU_PLLDSI_LOCKP_LOCKED 0x3
+
+/*
+ * mb0_transfer - state needed for mailbox 0 communication.
+ * @lock: The transaction lock.
+ */
+static struct {
+ spinlock_t lock;
+} mb0_transfer;
+
+/*
+ * mb5_transfer - state needed for mailbox 5 communication.
+ * @lock: The transaction lock.
+ * @work: The transaction completion structure.
+ * @ack: Reply ("acknowledge") data.
+ */
+static struct {
+ struct mutex lock;
+ struct completion work;
+ struct {
+ u8 header;
+ u8 status;
+ u8 value[4];
+ } ack;
+} mb5_transfer;
+
+/* PRCMU TCDM base IO address. */
+static __iomem void *tcdm_base;
+
+/**
+ * db5500_prcmu_abb_read() - Read register value(s) from the ABB.
+ * @slave: The I2C slave address.
+ * @reg: The (start) register address.
+ * @value: The read out value(s).
+ * @size: The number of registers to read.
+ *
+ * Reads register value(s) from the ABB.
+ * @size has to be <= 4.
+ */
+int db5500_prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
+{
+ int r;
+
+ if ((size < 1) || (4 < size))
+ return -EINVAL;
+
+ mutex_lock(&mb5_transfer.lock);
+
+ while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
+ cpu_relax();
+ writeb(slave, PRCM_REQ_MB5_I2C_SLAVE);
+ writeb(reg, PRCM_REQ_MB5_I2C_REG);
+ writeb(size, PRCM_REQ_MB5_I2C_SIZE);
+ writeb(MB5H_I2C_READ, PRCM_REQ_MB5_HEADER);
+
+ writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
+ wait_for_completion(&mb5_transfer.work);
+
+ r = 0;
+ if ((mb5_transfer.ack.header == MB5H_I2C_READ) &&
+ (mb5_transfer.ack.status == RC_SUCCESS))
+ memcpy(value, mb5_transfer.ack.value, (size_t)size);
+ else
+ r = -EIO;
+
+ mutex_unlock(&mb5_transfer.lock);
+
+ return r;
+}
+
+/**
+ * db5500_prcmu_abb_write() - Write register value(s) to the ABB.
+ * @slave: The I2C slave address.
+ * @reg: The (start) register address.
+ * @value: The value(s) to write.
+ * @size: The number of registers to write.
+ *
+ * Writes register value(s) to the ABB.
+ * @size has to be <= 4.
+ */
+int db5500_prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
+{
+ int r;
+
+ if ((size < 1) || (4 < size))
+ return -EINVAL;
+
+ mutex_lock(&mb5_transfer.lock);
+
+ while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
+ cpu_relax();
+ writeb(slave, PRCM_REQ_MB5_I2C_SLAVE);
+ writeb(reg, PRCM_REQ_MB5_I2C_REG);
+ writeb(size, PRCM_REQ_MB5_I2C_SIZE);
+ memcpy_toio(PRCM_REQ_MB5_I2C_DATA, value, size);
+ writeb(MB5H_I2C_WRITE, PRCM_REQ_MB5_HEADER);
+
+ writel(MBOX_BIT(5), PRCM_MBOX_CPU_SET);
+ wait_for_completion(&mb5_transfer.work);
+
+ if ((mb5_transfer.ack.header == MB5H_I2C_WRITE) &&
+ (mb5_transfer.ack.status == RC_SUCCESS))
+ r = 0;
+ else
+ r = -EIO;
+
+ mutex_unlock(&mb5_transfer.lock);
+
+ return r;
+}
+
+int db5500_prcmu_enable_dsipll(void)
+{
+ int i;
+
+ /* Enable DSIPLL_RESETN resets */
+ writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_CLR);
+ /* Unclamp DSIPLL in/out */
+ writel(PRCMU_UNCLAMP_DSIPLL, PRCM_MMIP_LS_CLAMP_CLR);
+ /* Set DSI PLL FREQ */
+ writel(PRCMU_PLLDSI_FREQ_SETTING, PRCM_PLLDSI_FREQ);
+ writel(PRCMU_DSI_PLLOUT_SEL_SETTING,
+ PRCM_DSI_PLLOUT_SEL);
+ /* Enable Escape clocks */
+ writel(PRCMU_ENABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV);
+
+ /* Start DSI PLL */
+ writel(PRCMU_ENABLE_PLLDSI, PRCM_PLLDSI_ENABLE);
+ /* Reset DSI PLL */
+ writel(PRCMU_DSI_RESET_SW, PRCM_DSI_SW_RESET);
+ for (i = 0; i < 10; i++) {
+ if ((readl(PRCM_PLLDSI_LOCKP) &
+ PRCMU_PLLDSI_LOCKP_LOCKED) == PRCMU_PLLDSI_LOCKP_LOCKED)
+ break;
+ udelay(100);
+ }
+ /* Release DSIPLL_RESETN */
+ writel(PRCMU_RESET_DSIPLL, PRCM_APE_RESETN_SET);
+ return 0;
+}
+
+int db5500_prcmu_disable_dsipll(void)
+{
+ /* Disable dsi pll */
+ writel(PRCMU_DISABLE_PLLDSI, PRCM_PLLDSI_ENABLE);
+ /* Disable escapeclock */
+ writel(PRCMU_DISABLE_ESCAPE_CLOCK_DIV, PRCM_DSITVCLK_DIV);
+ return 0;
+}
+
+int db5500_prcmu_set_display_clocks(void)
+{
+ /* HDMI and TVCLK Should be handled somewhere else */
+ /* PLLDIV=8, PLLSW=2, CLKEN=1 */
+ writel(PRCMU_DSI_CLOCK_SETTING, PRCM_HDMICLK_MGT);
+ /* PLLDIV=14, PLLSW=2, CLKEN=1 */
+ writel(PRCMU_DSI_LP_CLOCK_SETTING, PRCM_TVCLK_MGT);
+ return 0;
+}
+
+static void ack_dbb_wakeup(void)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&mb0_transfer.lock, flags);
+
+ while (readl(PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
+ cpu_relax();
+
+ writeb(RMB0H_RD_WAKE_UP_ACK, PRCM_REQ_MB0_HEADER);
+ writel(MBOX_BIT(0), PRCM_MBOX_CPU_SET);
+
+ spin_unlock_irqrestore(&mb0_transfer.lock, flags);
+}
+
+static inline void print_unknown_header_warning(u8 n, u8 header)
+{
+ pr_warning("prcmu: Unknown message header (%d) in mailbox %d.\n",
+ header, n);
+}
+
+static bool read_mailbox_0(void)
+{
+ bool r;
+ u8 header;
+
+ header = readb(PRCM_ACK_MB0_HEADER);
+ switch (header) {
+ case AMB0H_WAKE_UP:
+ r = true;
+ break;
+ default:
+ print_unknown_header_warning(0, header);
+ r = false;
+ break;
+ }
+ writel(MBOX_BIT(0), PRCM_ARM_IT1_CLEAR);
+ return r;
+}
+
+static bool read_mailbox_1(void)
+{
+ writel(MBOX_BIT(1), PRCM_ARM_IT1_CLEAR);
+ return false;
+}
+
+static bool read_mailbox_2(void)
+{
+ writel(MBOX_BIT(2), PRCM_ARM_IT1_CLEAR);
+ return false;
+}
+
+static bool read_mailbox_3(void)
+{
+ writel(MBOX_BIT(3), PRCM_ARM_IT1_CLEAR);
+ return false;
+}
+
+static bool read_mailbox_4(void)
+{
+ writel(MBOX_BIT(4), PRCM_ARM_IT1_CLEAR);
+ return false;
+}
+
+static bool read_mailbox_5(void)
+{
+ u8 header;
+
+ header = readb(PRCM_ACK_MB5_HEADER);
+ switch (header) {
+ case MB5H_I2C_READ:
+ memcpy_fromio(mb5_transfer.ack.value, PRCM_ACK_MB5_I2C_DATA, 4);
+ case MB5H_I2C_WRITE:
+ mb5_transfer.ack.header = header;
+ mb5_transfer.ack.status = readb(PRCM_ACK_MB5_RETURN_CODE);
+ complete(&mb5_transfer.work);
+ break;
+ default:
+ print_unknown_header_warning(5, header);
+ break;
+ }
+ writel(MBOX_BIT(5), PRCM_ARM_IT1_CLEAR);
+ return false;
+}
+
+static bool read_mailbox_6(void)
+{
+ writel(MBOX_BIT(6), PRCM_ARM_IT1_CLEAR);
+ return false;
+}
+
+static bool read_mailbox_7(void)
+{
+ writel(MBOX_BIT(7), PRCM_ARM_IT1_CLEAR);
+ return false;
+}
+
+static bool (* const read_mailbox[NUM_MB])(void) = {
+ read_mailbox_0,
+ read_mailbox_1,
+ read_mailbox_2,
+ read_mailbox_3,
+ read_mailbox_4,
+ read_mailbox_5,
+ read_mailbox_6,
+ read_mailbox_7
+};
+
+static irqreturn_t prcmu_irq_handler(int irq, void *data)
+{
+ u32 bits;
+ u8 n;
+ irqreturn_t r;
+
+ bits = (readl(PRCM_ARM_IT1_VAL) & ALL_MBOX_BITS);
+ if (unlikely(!bits))
+ return IRQ_NONE;
+
+ r = IRQ_HANDLED;
+ for (n = 0; bits; n++) {
+ if (bits & MBOX_BIT(n)) {
+ bits -= MBOX_BIT(n);
+ if (read_mailbox[n]())
+ r = IRQ_WAKE_THREAD;
+ }
+ }
+ return r;
+}
+
+static irqreturn_t prcmu_irq_thread_fn(int irq, void *data)
+{
+ ack_dbb_wakeup();
+ return IRQ_HANDLED;
+}
+
+void __init db5500_prcmu_early_init(void)
+{
+ tcdm_base = __io_address(U5500_PRCMU_TCDM_BASE);
+ spin_lock_init(&mb0_transfer.lock);
+ mutex_init(&mb5_transfer.lock);
+ init_completion(&mb5_transfer.work);
+}
+
+/**
+ * prcmu_fw_init - arch init call for the Linux PRCMU fw init logic
+ *
+ */
+int __init db5500_prcmu_init(void)
+{
+ int r = 0;
+
+ if (ux500_is_svp() || !cpu_is_u5500())
+ return -ENODEV;
+
+ /* Clean up the mailbox interrupts after pre-kernel code. */
+ writel(ALL_MBOX_BITS, PRCM_ARM_IT1_CLEAR);
+
+ r = request_threaded_irq(IRQ_DB5500_PRCMU1, prcmu_irq_handler,
+ prcmu_irq_thread_fn, 0, "prcmu", NULL);
+ if (r < 0) {
+ pr_err("prcmu: Failed to allocate IRQ_DB5500_PRCMU1.\n");
+ return -EBUSY;
+ }
+ return 0;
+}
+
+arch_initcall(db5500_prcmu_init);
diff --git a/drivers/mfd/db8500-prcmu-regs.h b/drivers/mfd/db8500-prcmu-regs.h
new file mode 100644
index 0000000..3bbf04d
--- /dev/null
+++ b/drivers/mfd/db8500-prcmu-regs.h
@@ -0,0 +1,166 @@
+/*
+ * Copyright (C) STMicroelectronics 2009
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
+ * Author: Sundar Iyer <sundar.iyer@stericsson.com>
+ *
+ * License Terms: GNU General Public License v2
+ *
+ * PRCM Unit registers
+ */
+#ifndef __DB8500_PRCMU_REGS_H
+#define __DB8500_PRCMU_REGS_H
+
+#include <linux/bitops.h>
+#include <mach/hardware.h>
+
+#define BITS(_start, _end) ((BIT(_end) - BIT(_start)) + BIT(_end))
+
+#define PRCM_ARM_PLLDIVPS 0x118
+#define PRCM_ARM_PLLDIVPS_ARM_BRM_RATE BITS(0, 5)
+#define PRCM_ARM_PLLDIVPS_MAX_MASK 0xF
+
+#define PRCM_PLLARM_LOCKP 0x0A8
+#define PRCM_PLLARM_LOCKP_PRCM_PLLARM_LOCKP3 BIT(1)
+
+#define PRCM_ARM_CHGCLKREQ 0x114
+#define PRCM_ARM_CHGCLKREQ_PRCM_ARM_CHGCLKREQ BIT(0)
+
+#define PRCM_PLLARM_ENABLE 0x98
+#define PRCM_PLLARM_ENABLE_PRCM_PLLARM_ENABLE BIT(0)
+#define PRCM_PLLARM_ENABLE_PRCM_PLLARM_COUNTON BIT(8)
+
+#define PRCM_ARMCLKFIX_MGT 0x0
+#define PRCM_A9_RESETN_CLR 0x1f4
+#define PRCM_A9_RESETN_SET 0x1f0
+#define PRCM_ARM_LS_CLAMP 0x30C
+#define PRCM_SRAM_A9 0x308
+
+/* ARM WFI Standby signal register */
+#define PRCM_ARM_WFI_STANDBY 0x130
+#define PRCM_IOCR 0x310
+#define PRCM_IOCR_IOFORCE BIT(0)
+
+/* CPU mailbox registers */
+#define PRCM_MBOX_CPU_VAL 0x0FC
+#define PRCM_MBOX_CPU_SET 0x100
+
+/* Dual A9 core interrupt management unit registers */
+#define PRCM_A9_MASK_REQ 0x328
+#define PRCM_A9_MASK_REQ_PRCM_A9_MASK_REQ BIT(0)
+
+#define PRCM_A9_MASK_ACK 0x32C
+#define PRCM_ARMITMSK31TO0 0x11C
+#define PRCM_ARMITMSK63TO32 0x120
+#define PRCM_ARMITMSK95TO64 0x124
+#define PRCM_ARMITMSK127TO96 0x128
+#define PRCM_POWER_STATE_VAL 0x25C
+#define PRCM_ARMITVAL31TO0 0x260
+#define PRCM_ARMITVAL63TO32 0x264
+#define PRCM_ARMITVAL95TO64 0x268
+#define PRCM_ARMITVAL127TO96 0x26C
+
+#define PRCM_HOSTACCESS_REQ 0x334
+#define PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ BIT(0)
+
+#define PRCM_ARM_IT1_CLR 0x48C
+#define PRCM_ARM_IT1_VAL 0x494
+
+#define PRCM_ITSTATUS0 0x148
+#define PRCM_ITSTATUS1 0x150
+#define PRCM_ITSTATUS2 0x158
+#define PRCM_ITSTATUS3 0x160
+#define PRCM_ITSTATUS4 0x168
+#define PRCM_ITSTATUS5 0x484
+#define PRCM_ITCLEAR5 0x488
+#define PRCM_ARMIT_MASKXP70_IT 0x1018
+
+/* System reset register */
+#define PRCM_APE_SOFTRST 0x228
+
+/* Level shifter and clamp control registers */
+#define PRCM_MMIP_LS_CLAMP_SET 0x420
+#define PRCM_MMIP_LS_CLAMP_CLR 0x424
+
+/* PRCMU HW semaphore */
+#define PRCM_SEM 0x400
+#define PRCM_SEM_PRCM_SEM BIT(0)
+
+/* PRCMU clock/PLL/reset registers */
+#define PRCM_PLLDSI_FREQ 0x500
+#define PRCM_PLLDSI_ENABLE 0x504
+#define PRCM_PLLDSI_LOCKP 0x508
+#define PRCM_DSI_PLLOUT_SEL 0x530
+#define PRCM_DSITVCLK_DIV 0x52C
+#define PRCM_APE_RESETN_SET 0x1E4
+#define PRCM_APE_RESETN_CLR 0x1E8
+
+#define PRCM_TCR 0x1C8
+#define PRCM_TCR_TENSEL_MASK BITS(0, 7)
+#define PRCM_TCR_STOP_TIMERS BIT(16)
+#define PRCM_TCR_DOZE_MODE BIT(17)
+
+#define PRCM_CLKOCR 0x1CC
+#define PRCM_CLKOCR_CLKODIV0_SHIFT 0
+#define PRCM_CLKOCR_CLKODIV0_MASK BITS(0, 5)
+#define PRCM_CLKOCR_CLKOSEL0_SHIFT 6
+#define PRCM_CLKOCR_CLKOSEL0_MASK BITS(6, 8)
+#define PRCM_CLKOCR_CLKODIV1_SHIFT 16
+#define PRCM_CLKOCR_CLKODIV1_MASK BITS(16, 21)
+#define PRCM_CLKOCR_CLKOSEL1_SHIFT 22
+#define PRCM_CLKOCR_CLKOSEL1_MASK BITS(22, 24)
+#define PRCM_CLKOCR_CLK1TYPE BIT(28)
+
+#define PRCM_SGACLK_MGT 0x014
+#define PRCM_UARTCLK_MGT 0x018
+#define PRCM_MSP02CLK_MGT 0x01C
+#define PRCM_MSP1CLK_MGT 0x288
+#define PRCM_I2CCLK_MGT 0x020
+#define PRCM_SDMMCCLK_MGT 0x024
+#define PRCM_SLIMCLK_MGT 0x028
+#define PRCM_PER1CLK_MGT 0x02C
+#define PRCM_PER2CLK_MGT 0x030
+#define PRCM_PER3CLK_MGT 0x034
+#define PRCM_PER5CLK_MGT 0x038
+#define PRCM_PER6CLK_MGT 0x03C
+#define PRCM_PER7CLK_MGT 0x040
+#define PRCM_LCDCLK_MGT 0x044
+#define PRCM_BMLCLK_MGT 0x04C
+#define PRCM_HSITXCLK_MGT 0x050
+#define PRCM_HSIRXCLK_MGT 0x054
+#define PRCM_HDMICLK_MGT 0x058
+#define PRCM_APEATCLK_MGT 0x05C
+#define PRCM_APETRACECLK_MGT 0x060
+#define PRCM_MCDECLK_MGT 0x064
+#define PRCM_IPI2CCLK_MGT 0x068
+#define PRCM_DSIALTCLK_MGT 0x06C
+#define PRCM_DMACLK_MGT 0x074
+#define PRCM_B2R2CLK_MGT 0x078
+#define PRCM_TVCLK_MGT 0x07C
+#define PRCM_UNIPROCLK_MGT 0x278
+#define PRCM_SSPCLK_MGT 0x280
+#define PRCM_RNGCLK_MGT 0x284
+#define PRCM_UICCCLK_MGT 0x27C
+
+#define PRCM_CLK_MGT_CLKPLLDIV_MASK BITS(0, 4)
+#define PRCM_CLK_MGT_CLKPLLSW_MASK BITS(5, 7)
+#define PRCM_CLK_MGT_CLKEN BIT(8)
+
+/* ePOD and memory power signal control registers */
+#define PRCM_EPOD_C_SET 0x410
+#define PRCM_SRAM_LS_SLEEP 0x304
+
+/* Debug power control unit registers */
+#define PRCM_POWER_STATE_SET 0x254
+
+/* Miscellaneous unit registers */
+#define PRCM_DSI_SW_RESET 0x324
+#define PRCM_GPIOCR 0x138
+
+/* GPIOCR register */
+#define PRCM_GPIOCR_SPI2_SELECT BIT(23)
+
+#define PRCM_DDR_SUBSYS_APE_MINBW 0x438
+
+#endif /* __DB8500_PRCMU_REGS_H */
diff --git a/drivers/mfd/db8500-prcmu.c b/drivers/mfd/db8500-prcmu.c
new file mode 100644
index 0000000..e637821
--- /dev/null
+++ b/drivers/mfd/db8500-prcmu.c
@@ -0,0 +1,2069 @@
+/*
+ * Copyright (C) STMicroelectronics 2009
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * License Terms: GNU General Public License v2
+ * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
+ * Author: Sundar Iyer <sundar.iyer@stericsson.com>
+ * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
+ *
+ * U8500 PRCM Unit interface driver
+ *
+ */
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/errno.h>
+#include <linux/err.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/mutex.h>
+#include <linux/completion.h>
+#include <linux/irq.h>
+#include <linux/jiffies.h>
+#include <linux/bitops.h>
+#include <linux/fs.h>
+#include <linux/platform_device.h>
+#include <linux/uaccess.h>
+#include <linux/mfd/core.h>
+#include <linux/mfd/db8500-prcmu.h>
+#include <linux/regulator/db8500-prcmu.h>
+#include <linux/regulator/machine.h>
+#include <mach/hardware.h>
+#include <mach/irqs.h>
+#include <mach/db8500-regs.h>
+#include <mach/id.h>
+#include "db8500-prcmu-regs.h"
+
+/* Offset for the firmware version within the TCPM */
+#define PRCMU_FW_VERSION_OFFSET 0xA4
+
+/* PRCMU project numbers, defined by PRCMU FW */
+#define PRCMU_PROJECT_ID_8500V1_0 1
+#define PRCMU_PROJECT_ID_8500V2_0 2
+#define PRCMU_PROJECT_ID_8400V2_0 3
+
+/* Index of different voltages to be used when accessing AVSData */
+#define PRCM_AVS_BASE 0x2FC
+#define PRCM_AVS_VBB_RET (PRCM_AVS_BASE + 0x0)
+#define PRCM_AVS_VBB_MAX_OPP (PRCM_AVS_BASE + 0x1)
+#define PRCM_AVS_VBB_100_OPP (PRCM_AVS_BASE + 0x2)
+#define PRCM_AVS_VBB_50_OPP (PRCM_AVS_BASE + 0x3)
+#define PRCM_AVS_VARM_MAX_OPP (PRCM_AVS_BASE + 0x4)
+#define PRCM_AVS_VARM_100_OPP (PRCM_AVS_BASE + 0x5)
+#define PRCM_AVS_VARM_50_OPP (PRCM_AVS_BASE + 0x6)
+#define PRCM_AVS_VARM_RET (PRCM_AVS_BASE + 0x7)
+#define PRCM_AVS_VAPE_100_OPP (PRCM_AVS_BASE + 0x8)
+#define PRCM_AVS_VAPE_50_OPP (PRCM_AVS_BASE + 0x9)
+#define PRCM_AVS_VMOD_100_OPP (PRCM_AVS_BASE + 0xA)
+#define PRCM_AVS_VMOD_50_OPP (PRCM_AVS_BASE + 0xB)
+#define PRCM_AVS_VSAFE (PRCM_AVS_BASE + 0xC)
+
+#define PRCM_AVS_VOLTAGE 0
+#define PRCM_AVS_VOLTAGE_MASK 0x3f
+#define PRCM_AVS_ISSLOWSTARTUP 6
+#define PRCM_AVS_ISSLOWSTARTUP_MASK (1 << PRCM_AVS_ISSLOWSTARTUP)
+#define PRCM_AVS_ISMODEENABLE 7
+#define PRCM_AVS_ISMODEENABLE_MASK (1 << PRCM_AVS_ISMODEENABLE)
+
+#define PRCM_BOOT_STATUS 0xFFF
+#define PRCM_ROMCODE_A2P 0xFFE
+#define PRCM_ROMCODE_P2A 0xFFD
+#define PRCM_XP70_CUR_PWR_STATE 0xFFC /* 4 BYTES */
+
+#define PRCM_SW_RST_REASON 0xFF8 /* 2 bytes */
+
+#define _PRCM_MBOX_HEADER 0xFE8 /* 16 bytes */
+#define PRCM_MBOX_HEADER_REQ_MB0 (_PRCM_MBOX_HEADER + 0x0)
+#define PRCM_MBOX_HEADER_REQ_MB1 (_PRCM_MBOX_HEADER + 0x1)
+#define PRCM_MBOX_HEADER_REQ_MB2 (_PRCM_MBOX_HEADER + 0x2)
+#define PRCM_MBOX_HEADER_REQ_MB3 (_PRCM_MBOX_HEADER + 0x3)
+#define PRCM_MBOX_HEADER_REQ_MB4 (_PRCM_MBOX_HEADER + 0x4)
+#define PRCM_MBOX_HEADER_REQ_MB5 (_PRCM_MBOX_HEADER + 0x5)
+#define PRCM_MBOX_HEADER_ACK_MB0 (_PRCM_MBOX_HEADER + 0x8)
+
+/* Req Mailboxes */
+#define PRCM_REQ_MB0 0xFDC /* 12 bytes */
+#define PRCM_REQ_MB1 0xFD0 /* 12 bytes */
+#define PRCM_REQ_MB2 0xFC0 /* 16 bytes */
+#define PRCM_REQ_MB3 0xE4C /* 372 bytes */
+#define PRCM_REQ_MB4 0xE48 /* 4 bytes */
+#define PRCM_REQ_MB5 0xE44 /* 4 bytes */
+
+/* Ack Mailboxes */
+#define PRCM_ACK_MB0 0xE08 /* 52 bytes */
+#define PRCM_ACK_MB1 0xE04 /* 4 bytes */
+#define PRCM_ACK_MB2 0xE00 /* 4 bytes */
+#define PRCM_ACK_MB3 0xDFC /* 4 bytes */
+#define PRCM_ACK_MB4 0xDF8 /* 4 bytes */
+#define PRCM_ACK_MB5 0xDF4 /* 4 bytes */
+
+/* Mailbox 0 headers */
+#define MB0H_POWER_STATE_TRANS 0
+#define MB0H_CONFIG_WAKEUPS_EXE 1
+#define MB0H_READ_WAKEUP_ACK 3
+#define MB0H_CONFIG_WAKEUPS_SLEEP 4
+
+#define MB0H_WAKEUP_EXE 2
+#define MB0H_WAKEUP_SLEEP 5
+
+/* Mailbox 0 REQs */
+#define PRCM_REQ_MB0_AP_POWER_STATE (PRCM_REQ_MB0 + 0x0)
+#define PRCM_REQ_MB0_AP_PLL_STATE (PRCM_REQ_MB0 + 0x1)
+#define PRCM_REQ_MB0_ULP_CLOCK_STATE (PRCM_REQ_MB0 + 0x2)
+#define PRCM_REQ_MB0_DO_NOT_WFI (PRCM_REQ_MB0 + 0x3)
+#define PRCM_REQ_MB0_WAKEUP_8500 (PRCM_REQ_MB0 + 0x4)
+#define PRCM_REQ_MB0_WAKEUP_4500 (PRCM_REQ_MB0 + 0x8)
+
+/* Mailbox 0 ACKs */
+#define PRCM_ACK_MB0_AP_PWRSTTR_STATUS (PRCM_ACK_MB0 + 0x0)
+#define PRCM_ACK_MB0_READ_POINTER (PRCM_ACK_MB0 + 0x1)
+#define PRCM_ACK_MB0_WAKEUP_0_8500 (PRCM_ACK_MB0 + 0x4)
+#define PRCM_ACK_MB0_WAKEUP_0_4500 (PRCM_ACK_MB0 + 0x8)
+#define PRCM_ACK_MB0_WAKEUP_1_8500 (PRCM_ACK_MB0 + 0x1C)
+#define PRCM_ACK_MB0_WAKEUP_1_4500 (PRCM_ACK_MB0 + 0x20)
+#define PRCM_ACK_MB0_EVENT_4500_NUMBERS 20
+
+/* Mailbox 1 headers */
+#define MB1H_ARM_APE_OPP 0x0
+#define MB1H_RESET_MODEM 0x2
+#define MB1H_REQUEST_APE_OPP_100_VOLT 0x3
+#define MB1H_RELEASE_APE_OPP_100_VOLT 0x4
+#define MB1H_RELEASE_USB_WAKEUP 0x5
+
+/* Mailbox 1 Requests */
+#define PRCM_REQ_MB1_ARM_OPP (PRCM_REQ_MB1 + 0x0)
+#define PRCM_REQ_MB1_APE_OPP (PRCM_REQ_MB1 + 0x1)
+#define PRCM_REQ_MB1_APE_OPP_100_RESTORE (PRCM_REQ_MB1 + 0x4)
+#define PRCM_REQ_MB1_ARM_OPP_100_RESTORE (PRCM_REQ_MB1 + 0x8)
+
+/* Mailbox 1 ACKs */
+#define PRCM_ACK_MB1_CURRENT_ARM_OPP (PRCM_ACK_MB1 + 0x0)
+#define PRCM_ACK_MB1_CURRENT_APE_OPP (PRCM_ACK_MB1 + 0x1)
+#define PRCM_ACK_MB1_APE_VOLTAGE_STATUS (PRCM_ACK_MB1 + 0x2)
+#define PRCM_ACK_MB1_DVFS_STATUS (PRCM_ACK_MB1 + 0x3)
+
+/* Mailbox 2 headers */
+#define MB2H_DPS 0x0
+#define MB2H_AUTO_PWR 0x1
+
+/* Mailbox 2 REQs */
+#define PRCM_REQ_MB2_SVA_MMDSP (PRCM_REQ_MB2 + 0x0)
+#define PRCM_REQ_MB2_SVA_PIPE (PRCM_REQ_MB2 + 0x1)
+#define PRCM_REQ_MB2_SIA_MMDSP (PRCM_REQ_MB2 + 0x2)
+#define PRCM_REQ_MB2_SIA_PIPE (PRCM_REQ_MB2 + 0x3)
+#define PRCM_REQ_MB2_SGA (PRCM_REQ_MB2 + 0x4)
+#define PRCM_REQ_MB2_B2R2_MCDE (PRCM_REQ_MB2 + 0x5)
+#define PRCM_REQ_MB2_ESRAM12 (PRCM_REQ_MB2 + 0x6)
+#define PRCM_REQ_MB2_ESRAM34 (PRCM_REQ_MB2 + 0x7)
+#define PRCM_REQ_MB2_AUTO_PM_SLEEP (PRCM_REQ_MB2 + 0x8)
+#define PRCM_REQ_MB2_AUTO_PM_IDLE (PRCM_REQ_MB2 + 0xC)
+
+/* Mailbox 2 ACKs */
+#define PRCM_ACK_MB2_DPS_STATUS (PRCM_ACK_MB2 + 0x0)
+#define HWACC_PWR_ST_OK 0xFE
+
+/* Mailbox 3 headers */
+#define MB3H_ANC 0x0
+#define MB3H_SIDETONE 0x1
+#define MB3H_SYSCLK 0xE
+
+/* Mailbox 3 Requests */
+#define PRCM_REQ_MB3_ANC_FIR_COEFF (PRCM_REQ_MB3 + 0x0)
+#define PRCM_REQ_MB3_ANC_IIR_COEFF (PRCM_REQ_MB3 + 0x20)
+#define PRCM_REQ_MB3_ANC_SHIFTER (PRCM_REQ_MB3 + 0x60)
+#define PRCM_REQ_MB3_ANC_WARP (PRCM_REQ_MB3 + 0x64)
+#define PRCM_REQ_MB3_SIDETONE_FIR_GAIN (PRCM_REQ_MB3 + 0x68)
+#define PRCM_REQ_MB3_SIDETONE_FIR_COEFF (PRCM_REQ_MB3 + 0x6C)
+#define PRCM_REQ_MB3_SYSCLK_MGT (PRCM_REQ_MB3 + 0x16C)
+
+/* Mailbox 4 headers */
+#define MB4H_DDR_INIT 0x0
+#define MB4H_MEM_ST 0x1
+#define MB4H_HOTDOG 0x12
+#define MB4H_HOTMON 0x13
+#define MB4H_HOT_PERIOD 0x14
+
+/* Mailbox 4 Requests */
+#define PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE (PRCM_REQ_MB4 + 0x0)
+#define PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE (PRCM_REQ_MB4 + 0x1)
+#define PRCM_REQ_MB4_ESRAM0_ST (PRCM_REQ_MB4 + 0x3)
+#define PRCM_REQ_MB4_HOTDOG_THRESHOLD (PRCM_REQ_MB4 + 0x0)
+#define PRCM_REQ_MB4_HOTMON_LOW (PRCM_REQ_MB4 + 0x0)
+#define PRCM_REQ_MB4_HOTMON_HIGH (PRCM_REQ_MB4 + 0x1)
+#define PRCM_REQ_MB4_HOTMON_CONFIG (PRCM_REQ_MB4 + 0x2)
+#define PRCM_REQ_MB4_HOT_PERIOD (PRCM_REQ_MB4 + 0x0)
+#define HOTMON_CONFIG_LOW BIT(0)
+#define HOTMON_CONFIG_HIGH BIT(1)
+
+/* Mailbox 5 Requests */
+#define PRCM_REQ_MB5_I2C_SLAVE_OP (PRCM_REQ_MB5 + 0x0)
+#define PRCM_REQ_MB5_I2C_HW_BITS (PRCM_REQ_MB5 + 0x1)
+#define PRCM_REQ_MB5_I2C_REG (PRCM_REQ_MB5 + 0x2)
+#define PRCM_REQ_MB5_I2C_VAL (PRCM_REQ_MB5 + 0x3)
+#define PRCMU_I2C_WRITE(slave) \
+ (((slave) << 1) | (cpu_is_u8500v2() ? BIT(6) : 0))
+#define PRCMU_I2C_READ(slave) \
+ (((slave) << 1) | BIT(0) | (cpu_is_u8500v2() ? BIT(6) : 0))
+#define PRCMU_I2C_STOP_EN BIT(3)
+
+/* Mailbox 5 ACKs */
+#define PRCM_ACK_MB5_I2C_STATUS (PRCM_ACK_MB5 + 0x1)
+#define PRCM_ACK_MB5_I2C_VAL (PRCM_ACK_MB5 + 0x3)
+#define I2C_WR_OK 0x1
+#define I2C_RD_OK 0x2
+
+#define NUM_MB 8
+#define MBOX_BIT BIT
+#define ALL_MBOX_BITS (MBOX_BIT(NUM_MB) - 1)
+
+/*
+ * Wakeups/IRQs
+ */
+
+#define WAKEUP_BIT_RTC BIT(0)
+#define WAKEUP_BIT_RTT0 BIT(1)
+#define WAKEUP_BIT_RTT1 BIT(2)
+#define WAKEUP_BIT_HSI0 BIT(3)
+#define WAKEUP_BIT_HSI1 BIT(4)
+#define WAKEUP_BIT_CA_WAKE BIT(5)
+#define WAKEUP_BIT_USB BIT(6)
+#define WAKEUP_BIT_ABB BIT(7)
+#define WAKEUP_BIT_ABB_FIFO BIT(8)
+#define WAKEUP_BIT_SYSCLK_OK BIT(9)
+#define WAKEUP_BIT_CA_SLEEP BIT(10)
+#define WAKEUP_BIT_AC_WAKE_ACK BIT(11)
+#define WAKEUP_BIT_SIDE_TONE_OK BIT(12)
+#define WAKEUP_BIT_ANC_OK BIT(13)
+#define WAKEUP_BIT_SW_ERROR BIT(14)
+#define WAKEUP_BIT_AC_SLEEP_ACK BIT(15)
+#define WAKEUP_BIT_ARM BIT(17)
+#define WAKEUP_BIT_HOTMON_LOW BIT(18)
+#define WAKEUP_BIT_HOTMON_HIGH BIT(19)
+#define WAKEUP_BIT_MODEM_SW_RESET_REQ BIT(20)
+#define WAKEUP_BIT_GPIO0 BIT(23)
+#define WAKEUP_BIT_GPIO1 BIT(24)
+#define WAKEUP_BIT_GPIO2 BIT(25)
+#define WAKEUP_BIT_GPIO3 BIT(26)
+#define WAKEUP_BIT_GPIO4 BIT(27)
+#define WAKEUP_BIT_GPIO5 BIT(28)
+#define WAKEUP_BIT_GPIO6 BIT(29)
+#define WAKEUP_BIT_GPIO7 BIT(30)
+#define WAKEUP_BIT_GPIO8 BIT(31)
+
+/*
+ * This vector maps irq numbers to the bits in the bit field used in
+ * communication with the PRCMU firmware.
+ *
+ * The reason for having this is to keep the irq numbers contiguous even though
+ * the bits in the bit field are not. (The bits also have a tendency to move
+ * around, to further complicate matters.)
+ */
+#define IRQ_INDEX(_name) ((IRQ_PRCMU_##_name) - IRQ_PRCMU_BASE)
+#define IRQ_ENTRY(_name)[IRQ_INDEX(_name)] = (WAKEUP_BIT_##_name)
+static u32 prcmu_irq_bit[NUM_PRCMU_WAKEUPS] = {
+ IRQ_ENTRY(RTC),
+ IRQ_ENTRY(RTT0),
+ IRQ_ENTRY(RTT1),
+ IRQ_ENTRY(HSI0),
+ IRQ_ENTRY(HSI1),
+ IRQ_ENTRY(CA_WAKE),
+ IRQ_ENTRY(USB),
+ IRQ_ENTRY(ABB),
+ IRQ_ENTRY(ABB_FIFO),
+ IRQ_ENTRY(CA_SLEEP),
+ IRQ_ENTRY(ARM),
+ IRQ_ENTRY(HOTMON_LOW),
+ IRQ_ENTRY(HOTMON_HIGH),
+ IRQ_ENTRY(MODEM_SW_RESET_REQ),
+ IRQ_ENTRY(GPIO0),
+ IRQ_ENTRY(GPIO1),
+ IRQ_ENTRY(GPIO2),
+ IRQ_ENTRY(GPIO3),
+ IRQ_ENTRY(GPIO4),
+ IRQ_ENTRY(GPIO5),
+ IRQ_ENTRY(GPIO6),
+ IRQ_ENTRY(GPIO7),
+ IRQ_ENTRY(GPIO8)
+};
+
+#define VALID_WAKEUPS (BIT(NUM_PRCMU_WAKEUP_INDICES) - 1)
+#define WAKEUP_ENTRY(_name)[PRCMU_WAKEUP_INDEX_##_name] = (WAKEUP_BIT_##_name)
+static u32 prcmu_wakeup_bit[NUM_PRCMU_WAKEUP_INDICES] = {
+ WAKEUP_ENTRY(RTC),
+ WAKEUP_ENTRY(RTT0),
+ WAKEUP_ENTRY(RTT1),
+ WAKEUP_ENTRY(HSI0),
+ WAKEUP_ENTRY(HSI1),
+ WAKEUP_ENTRY(USB),
+ WAKEUP_ENTRY(ABB),
+ WAKEUP_ENTRY(ABB_FIFO),
+ WAKEUP_ENTRY(ARM)
+};
+
+/*
+ * mb0_transfer - state needed for mailbox 0 communication.
+ * @lock: The transaction lock.
+ * @dbb_events_lock: A lock used to handle concurrent access to (parts of)
+ * the request data.
+ * @mask_work: Work structure used for (un)masking wakeup interrupts.
+ * @req: Request data that need to persist between requests.
+ */
+static struct {
+ spinlock_t lock;
+ spinlock_t dbb_irqs_lock;
+ struct work_struct mask_work;
+ struct mutex ac_wake_lock;
+ struct completion ac_wake_work;
+ struct {
+ u32 dbb_irqs;
+ u32 dbb_wakeups;
+ u32 abb_events;
+ } req;
+} mb0_transfer;
+
+/*
+ * mb1_transfer - state needed for mailbox 1 communication.
+ * @lock: The transaction lock.
+ * @work: The transaction completion structure.
+ * @ack: Reply ("acknowledge") data.
+ */
+static struct {
+ struct mutex lock;
+ struct completion work;
+ struct {
+ u8 header;
+ u8 arm_opp;
+ u8 ape_opp;
+ u8 ape_voltage_status;
+ } ack;
+} mb1_transfer;
+
+/*
+ * mb2_transfer - state needed for mailbox 2 communication.
+ * @lock: The transaction lock.
+ * @work: The transaction completion structure.
+ * @auto_pm_lock: The autonomous power management configuration lock.
+ * @auto_pm_enabled: A flag indicating whether autonomous PM is enabled.
+ * @req: Request data that need to persist between requests.
+ * @ack: Reply ("acknowledge") data.
+ */
+static struct {
+ struct mutex lock;
+ struct completion work;
+ spinlock_t auto_pm_lock;
+ bool auto_pm_enabled;
+ struct {
+ u8 status;
+ } ack;
+} mb2_transfer;
+
+/*
+ * mb3_transfer - state needed for mailbox 3 communication.
+ * @lock: The request lock.
+ * @sysclk_lock: A lock used to handle concurrent sysclk requests.
+ * @sysclk_work: Work structure used for sysclk requests.
+ */
+static struct {
+ spinlock_t lock;
+ struct mutex sysclk_lock;
+ struct completion sysclk_work;
+} mb3_transfer;
+
+/*
+ * mb4_transfer - state needed for mailbox 4 communication.
+ * @lock: The transaction lock.
+ * @work: The transaction completion structure.
+ */
+static struct {
+ struct mutex lock;
+ struct completion work;
+} mb4_transfer;
+
+/*
+ * mb5_transfer - state needed for mailbox 5 communication.
+ * @lock: The transaction lock.
+ * @work: The transaction completion structure.
+ * @ack: Reply ("acknowledge") data.
+ */
+static struct {
+ struct mutex lock;
+ struct completion work;
+ struct {
+ u8 status;
+ u8 value;
+ } ack;
+} mb5_transfer;
+
+static atomic_t ac_wake_req_state = ATOMIC_INIT(0);
+
+/* Spinlocks */
+static DEFINE_SPINLOCK(clkout_lock);
+static DEFINE_SPINLOCK(gpiocr_lock);
+
+/* Global var to runtime determine TCDM base for v2 or v1 */
+static __iomem void *tcdm_base;
+
+struct clk_mgt {
+ unsigned int offset;
+ u32 pllsw;
+};
+
+static DEFINE_SPINLOCK(clk_mgt_lock);
+
+#define CLK_MGT_ENTRY(_name)[PRCMU_##_name] = { (PRCM_##_name##_MGT), 0 }
+struct clk_mgt clk_mgt[PRCMU_NUM_REG_CLOCKS] = {
+ CLK_MGT_ENTRY(SGACLK),
+ CLK_MGT_ENTRY(UARTCLK),
+ CLK_MGT_ENTRY(MSP02CLK),
+ CLK_MGT_ENTRY(MSP1CLK),
+ CLK_MGT_ENTRY(I2CCLK),
+ CLK_MGT_ENTRY(SDMMCCLK),
+ CLK_MGT_ENTRY(SLIMCLK),
+ CLK_MGT_ENTRY(PER1CLK),
+ CLK_MGT_ENTRY(PER2CLK),
+ CLK_MGT_ENTRY(PER3CLK),
+ CLK_MGT_ENTRY(PER5CLK),
+ CLK_MGT_ENTRY(PER6CLK),
+ CLK_MGT_ENTRY(PER7CLK),
+ CLK_MGT_ENTRY(LCDCLK),
+ CLK_MGT_ENTRY(BMLCLK),
+ CLK_MGT_ENTRY(HSITXCLK),
+ CLK_MGT_ENTRY(HSIRXCLK),
+ CLK_MGT_ENTRY(HDMICLK),
+ CLK_MGT_ENTRY(APEATCLK),
+ CLK_MGT_ENTRY(APETRACECLK),
+ CLK_MGT_ENTRY(MCDECLK),
+ CLK_MGT_ENTRY(IPI2CCLK),
+ CLK_MGT_ENTRY(DSIALTCLK),
+ CLK_MGT_ENTRY(DMACLK),
+ CLK_MGT_ENTRY(B2R2CLK),
+ CLK_MGT_ENTRY(TVCLK),
+ CLK_MGT_ENTRY(SSPCLK),
+ CLK_MGT_ENTRY(RNGCLK),
+ CLK_MGT_ENTRY(UICCCLK),
+};
+
+/*
+* Used by MCDE to setup all necessary PRCMU registers
+*/
+#define PRCMU_RESET_DSIPLL 0x00004000
+#define PRCMU_UNCLAMP_DSIPLL 0x00400800
+
+#define PRCMU_CLK_PLL_DIV_SHIFT 0
+#define PRCMU_CLK_PLL_SW_SHIFT 5
+#define PRCMU_CLK_38 (1 << 9)
+#define PRCMU_CLK_38_SRC (1 << 10)
+#define PRCMU_CLK_38_DIV (1 << 11)
+
+/* PLLDIV=12, PLLSW=4 (PLLDDR) */
+#define PRCMU_DSI_CLOCK_SETTING 0x0000008C
+
+/* PLLDIV=8, PLLSW=4 (PLLDDR) */
+#define PRCMU_DSI_CLOCK_SETTING_U8400 0x00000088
+
+/* DPI 50000000 Hz */
+#define PRCMU_DPI_CLOCK_SETTING ((1 << PRCMU_CLK_PLL_SW_SHIFT) | \
+ (16 << PRCMU_CLK_PLL_DIV_SHIFT))
+#define PRCMU_DSI_LP_CLOCK_SETTING 0x00000E00
+
+/* D=101, N=1, R=4, SELDIV2=0 */
+#define PRCMU_PLLDSI_FREQ_SETTING 0x00040165
+
+/* D=70, N=1, R=3, SELDIV2=0 */
+#define PRCMU_PLLDSI_FREQ_SETTING_U8400 0x00030146
+
+#define PRCMU_ENABLE_PLLDSI 0x00000001
+#define PRCMU_DISABLE_PLLDSI 0x00000000
+#define PRCMU_RELEASE_RESET_DSS 0x0000400C
+#define PRCMU_DSI_PLLOUT_SEL_SETTING 0x00000202
+/* ESC clk, div0=1, div1=1, div2=3 */
+#define PRCMU_ENABLE_ESCAPE_CLOCK_DIV 0x07030101
+#define PRCMU_DISABLE_ESCAPE_CLOCK_DIV 0x00030101
+#define PRCMU_DSI_RESET_SW 0x00000007
+
+#define PRCMU_PLLDSI_LOCKP_LOCKED 0x3
+
+static struct {
+ u8 project_number;
+ u8 api_version;
+ u8 func_version;
+ u8 errata;
+} prcmu_version;
+
+
+int prcmu_enable_dsipll(void)
+{
+ int i;
+ unsigned int plldsifreq;
+
+ /* Clear DSIPLL_RESETN */
+ writel(PRCMU_RESET_DSIPLL, (_PRCMU_BASE + PRCM_APE_RESETN_CLR));
+ /* Unclamp DSIPLL in/out */
+ writel(PRCMU_UNCLAMP_DSIPLL, (_PRCMU_BASE + PRCM_MMIP_LS_CLAMP_CLR));
+
+ if (prcmu_is_u8400())
+ plldsifreq = PRCMU_PLLDSI_FREQ_SETTING_U8400;
+ else
+ plldsifreq = PRCMU_PLLDSI_FREQ_SETTING;
+ /* Set DSI PLL FREQ */
+ writel(plldsifreq, (_PRCMU_BASE + PRCM_PLLDSI_FREQ));
+ writel(PRCMU_DSI_PLLOUT_SEL_SETTING,
+ (_PRCMU_BASE + PRCM_DSI_PLLOUT_SEL));
+ /* Enable Escape clocks */
+ writel(PRCMU_ENABLE_ESCAPE_CLOCK_DIV,
+ (_PRCMU_BASE + PRCM_DSITVCLK_DIV));
+
+ /* Start DSI PLL */
+ writel(PRCMU_ENABLE_PLLDSI, (_PRCMU_BASE + PRCM_PLLDSI_ENABLE));
+ /* Reset DSI PLL */
+ writel(PRCMU_DSI_RESET_SW, (_PRCMU_BASE + PRCM_DSI_SW_RESET));
+ for (i = 0; i < 10; i++) {
+ if ((readl(_PRCMU_BASE + PRCM_PLLDSI_LOCKP) &
+ PRCMU_PLLDSI_LOCKP_LOCKED)
+ == PRCMU_PLLDSI_LOCKP_LOCKED)
+ break;
+ udelay(100);
+ }
+ /* Set DSIPLL_RESETN */
+ writel(PRCMU_RESET_DSIPLL, (_PRCMU_BASE + PRCM_APE_RESETN_SET));
+ return 0;
+}
+
+int prcmu_disable_dsipll(void)
+{
+ /* Disable dsi pll */
+ writel(PRCMU_DISABLE_PLLDSI, (_PRCMU_BASE + PRCM_PLLDSI_ENABLE));
+ /* Disable escapeclock */
+ writel(PRCMU_DISABLE_ESCAPE_CLOCK_DIV,
+ (_PRCMU_BASE + PRCM_DSITVCLK_DIV));
+ return 0;
+}
+
+int prcmu_set_display_clocks(void)
+{
+ unsigned long flags;
+ unsigned int dsiclk;
+
+ if (prcmu_is_u8400())
+ dsiclk = PRCMU_DSI_CLOCK_SETTING_U8400;
+ else
+ dsiclk = PRCMU_DSI_CLOCK_SETTING;
+
+ spin_lock_irqsave(&clk_mgt_lock, flags);
+
+ /* Grab the HW semaphore. */
+ while ((readl(_PRCMU_BASE + PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
+ cpu_relax();
+
+ writel(dsiclk, (_PRCMU_BASE + PRCM_HDMICLK_MGT));
+ writel(PRCMU_DSI_LP_CLOCK_SETTING, (_PRCMU_BASE + PRCM_TVCLK_MGT));
+ writel(PRCMU_DPI_CLOCK_SETTING, (_PRCMU_BASE + PRCM_LCDCLK_MGT));
+
+ /* Release the HW semaphore. */
+ writel(0, (_PRCMU_BASE + PRCM_SEM));
+
+ spin_unlock_irqrestore(&clk_mgt_lock, flags);
+
+ return 0;
+}
+
+/**
+ * prcmu_enable_spi2 - Enables pin muxing for SPI2 on OtherAlternateC1.
+ */
+void prcmu_enable_spi2(void)
+{
+ u32 reg;
+ unsigned long flags;
+
+ spin_lock_irqsave(&gpiocr_lock, flags);
+ reg = readl(_PRCMU_BASE + PRCM_GPIOCR);
+ writel(reg | PRCM_GPIOCR_SPI2_SELECT, _PRCMU_BASE + PRCM_GPIOCR);
+ spin_unlock_irqrestore(&gpiocr_lock, flags);
+}
+
+/**
+ * prcmu_disable_spi2 - Disables pin muxing for SPI2 on OtherAlternateC1.
+ */
+void prcmu_disable_spi2(void)
+{
+ u32 reg;
+ unsigned long flags;
+
+ spin_lock_irqsave(&gpiocr_lock, flags);
+ reg = readl(_PRCMU_BASE + PRCM_GPIOCR);
+ writel(reg & ~PRCM_GPIOCR_SPI2_SELECT, _PRCMU_BASE + PRCM_GPIOCR);
+ spin_unlock_irqrestore(&gpiocr_lock, flags);
+}
+
+bool prcmu_has_arm_maxopp(void)
+{
+ return (readb(tcdm_base + PRCM_AVS_VARM_MAX_OPP) &
+ PRCM_AVS_ISMODEENABLE_MASK) == PRCM_AVS_ISMODEENABLE_MASK;
+}
+
+bool prcmu_is_u8400(void)
+{
+ return prcmu_version.project_number == PRCMU_PROJECT_ID_8400V2_0;
+}
+
+/**
+ * prcmu_get_boot_status - PRCMU boot status checking
+ * Returns: the current PRCMU boot status
+ */
+int prcmu_get_boot_status(void)
+{
+ return readb(tcdm_base + PRCM_BOOT_STATUS);
+}
+
+/**
+ * prcmu_set_rc_a2p - This function is used to run few power state sequences
+ * @val: Value to be set, i.e. transition requested
+ * Returns: 0 on success, -EINVAL on invalid argument
+ *
+ * This function is used to run the following power state sequences -
+ * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep
+ */
+int prcmu_set_rc_a2p(enum romcode_write val)
+{
+ if (val < RDY_2_DS || val > RDY_2_XP70_RST)
+ return -EINVAL;
+ writeb(val, (tcdm_base + PRCM_ROMCODE_A2P));
+ return 0;
+}
+
+/**
+ * prcmu_get_rc_p2a - This function is used to get power state sequences
+ * Returns: the power transition that has last happened
+ *
+ * This function can return the following transitions-
+ * any state to ApReset, ApDeepSleep to ApExecute, ApExecute to ApDeepSleep
+ */
+enum romcode_read prcmu_get_rc_p2a(void)
+{
+ return readb(tcdm_base + PRCM_ROMCODE_P2A);
+}
+
+/**
+ * prcmu_get_current_mode - Return the current XP70 power mode
+ * Returns: Returns the current AP(ARM) power mode: init,
+ * apBoot, apExecute, apDeepSleep, apSleep, apIdle, apReset
+ */
+enum ap_pwrst prcmu_get_xp70_current_state(void)
+{
+ return readb(tcdm_base + PRCM_XP70_CUR_PWR_STATE);
+}
+
+/**
+ * prcmu_config_clkout - Configure one of the programmable clock outputs.
+ * @clkout: The CLKOUT number (0 or 1).
+ * @source: The clock to be used (one of the PRCMU_CLKSRC_*).
+ * @div: The divider to be applied.
+ *
+ * Configures one of the programmable clock outputs (CLKOUTs).
+ * @div should be in the range [1,63] to request a configuration, or 0 to
+ * inform that the configuration is no longer requested.
+ */
+int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
+{
+ static int requests[2];
+ int r = 0;
+ unsigned long flags;
+ u32 val;
+ u32 bits;
+ u32 mask;
+ u32 div_mask;
+
+ BUG_ON(clkout > 1);
+ BUG_ON(div > 63);
+ BUG_ON((clkout == 0) && (source > PRCMU_CLKSRC_CLK009));
+
+ if (!div && !requests[clkout])
+ return -EINVAL;
+
+ switch (clkout) {
+ case 0:
+ div_mask = PRCM_CLKOCR_CLKODIV0_MASK;
+ mask = (PRCM_CLKOCR_CLKODIV0_MASK | PRCM_CLKOCR_CLKOSEL0_MASK);
+ bits = ((source << PRCM_CLKOCR_CLKOSEL0_SHIFT) |
+ (div << PRCM_CLKOCR_CLKODIV0_SHIFT));
+ break;
+ case 1:
+ div_mask = PRCM_CLKOCR_CLKODIV1_MASK;
+ mask = (PRCM_CLKOCR_CLKODIV1_MASK | PRCM_CLKOCR_CLKOSEL1_MASK |
+ PRCM_CLKOCR_CLK1TYPE);
+ bits = ((source << PRCM_CLKOCR_CLKOSEL1_SHIFT) |
+ (div << PRCM_CLKOCR_CLKODIV1_SHIFT));
+ break;
+ }
+ bits &= mask;
+
+ spin_lock_irqsave(&clkout_lock, flags);
+
+ val = readl(_PRCMU_BASE + PRCM_CLKOCR);
+ if (val & div_mask) {
+ if (div) {
+ if ((val & mask) != bits) {
+ r = -EBUSY;
+ goto unlock_and_return;
+ }
+ } else {
+ if ((val & mask & ~div_mask) != bits) {
+ r = -EINVAL;
+ goto unlock_and_return;
+ }
+ }
+ }
+ writel((bits | (val & ~mask)), (_PRCMU_BASE + PRCM_CLKOCR));
+ requests[clkout] += (div ? 1 : -1);
+
+unlock_and_return:
+ spin_unlock_irqrestore(&clkout_lock, flags);
+
+ return r;
+}
+
+int prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll)
+{
+ unsigned long flags;
+
+ BUG_ON((state < PRCMU_AP_SLEEP) || (PRCMU_AP_DEEP_IDLE < state));
+
+ spin_lock_irqsave(&mb0_transfer.lock, flags);
+
+ while (readl(_PRCMU_BASE + PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
+ cpu_relax();
+
+ writeb(MB0H_POWER_STATE_TRANS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
+ writeb(state, (tcdm_base + PRCM_REQ_MB0_AP_POWER_STATE));
+ writeb((keep_ap_pll ? 1 : 0), (tcdm_base + PRCM_REQ_MB0_AP_PLL_STATE));
+ writeb((keep_ulp_clk ? 1 : 0),
+ (tcdm_base + PRCM_REQ_MB0_ULP_CLOCK_STATE));
+ writeb(0, (tcdm_base + PRCM_REQ_MB0_DO_NOT_WFI));
+ writel(MBOX_BIT(0), (_PRCMU_BASE + PRCM_MBOX_CPU_SET));
+
+ spin_unlock_irqrestore(&mb0_transfer.lock, flags);
+
+ return 0;
+}
+
+/* This function should only be called while mb0_transfer.lock is held. */
+static void config_wakeups(void)
+{
+ const u8 header[2] = {
+ MB0H_CONFIG_WAKEUPS_EXE,
+ MB0H_CONFIG_WAKEUPS_SLEEP
+ };
+ static u32 last_dbb_events;
+ static u32 last_abb_events;
+ u32 dbb_events;
+ u32 abb_events;
+ unsigned int i;
+
+ dbb_events = mb0_transfer.req.dbb_irqs | mb0_transfer.req.dbb_wakeups;
+ dbb_events |= (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK);
+
+ abb_events = mb0_transfer.req.abb_events;
+
+ if ((dbb_events == last_dbb_events) && (abb_events == last_abb_events))
+ return;
+
+ for (i = 0; i < 2; i++) {
+ while (readl(_PRCMU_BASE + PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
+ cpu_relax();
+ writel(dbb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_8500));
+ writel(abb_events, (tcdm_base + PRCM_REQ_MB0_WAKEUP_4500));
+ writeb(header[i], (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
+ writel(MBOX_BIT(0), (_PRCMU_BASE + PRCM_MBOX_CPU_SET));
+ }
+ last_dbb_events = dbb_events;
+ last_abb_events = abb_events;
+}
+
+void prcmu_enable_wakeups(u32 wakeups)
+{
+ unsigned long flags;
+ u32 bits;
+ int i;
+
+ BUG_ON(wakeups != (wakeups & VALID_WAKEUPS));
+
+ for (i = 0, bits = 0; i < NUM_PRCMU_WAKEUP_INDICES; i++) {
+ if (wakeups & BIT(i))
+ bits |= prcmu_wakeup_bit[i];
+ }
+
+ spin_lock_irqsave(&mb0_transfer.lock, flags);
+
+ mb0_transfer.req.dbb_wakeups = bits;
+ config_wakeups();
+
+ spin_unlock_irqrestore(&mb0_transfer.lock, flags);
+}
+
+void prcmu_config_abb_event_readout(u32 abb_events)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&mb0_transfer.lock, flags);
+
+ mb0_transfer.req.abb_events = abb_events;
+ config_wakeups();
+
+ spin_unlock_irqrestore(&mb0_transfer.lock, flags);
+}
+
+void prcmu_get_abb_event_buffer(void __iomem **buf)
+{
+ if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1)
+ *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_1_4500);
+ else
+ *buf = (tcdm_base + PRCM_ACK_MB0_WAKEUP_0_4500);
+}
+
+/**
+ * prcmu_set_arm_opp - set the appropriate ARM OPP
+ * @opp: The new ARM operating point to which transition is to be made
+ * Returns: 0 on success, non-zero on failure
+ *
+ * This function sets the the operating point of the ARM.
+ */
+int prcmu_set_arm_opp(u8 opp)
+{
+ int r;
+
+ if (opp < ARM_NO_CHANGE || opp > ARM_EXTCLK)
+ return -EINVAL;
+
+ r = 0;
+
+ mutex_lock(&mb1_transfer.lock);
+
+ while (readl(_PRCMU_BASE + PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
+ cpu_relax();
+
+ writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
+ writeb(opp, (tcdm_base + PRCM_REQ_MB1_ARM_OPP));
+ writeb(APE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_APE_OPP));
+
+ writel(MBOX_BIT(1), (_PRCMU_BASE + PRCM_MBOX_CPU_SET));
+ wait_for_completion(&mb1_transfer.work);
+
+ if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) ||
+ (mb1_transfer.ack.arm_opp != opp))
+ r = -EIO;
+
+ mutex_unlock(&mb1_transfer.lock);
+
+ return r;
+}
+
+/**
+ * prcmu_get_arm_opp - get the current ARM OPP
+ *
+ * Returns: the current ARM OPP
+ */
+int prcmu_get_arm_opp(void)
+{
+ return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_ARM_OPP);
+}
+
+/**
+ * prcmu_get_ddr_opp - get the current DDR OPP
+ *
+ * Returns: the current DDR OPP
+ */
+int prcmu_get_ddr_opp(void)
+{
+ return readb(_PRCMU_BASE + PRCM_DDR_SUBSYS_APE_MINBW);
+}
+
+/**
+ * set_ddr_opp - set the appropriate DDR OPP
+ * @opp: The new DDR operating point to which transition is to be made
+ * Returns: 0 on success, non-zero on failure
+ *
+ * This function sets the operating point of the DDR.
+ */
+int prcmu_set_ddr_opp(u8 opp)
+{
+ if (opp < DDR_100_OPP || opp > DDR_25_OPP)
+ return -EINVAL;
+ /* Changing the DDR OPP can hang the hardware pre-v21 */
+ if (cpu_is_u8500v20_or_later() && !cpu_is_u8500v20())
+ writeb(opp, (_PRCMU_BASE + PRCM_DDR_SUBSYS_APE_MINBW));
+
+ return 0;
+}
+/**
+ * set_ape_opp - set the appropriate APE OPP
+ * @opp: The new APE operating point to which transition is to be made
+ * Returns: 0 on success, non-zero on failure
+ *
+ * This function sets the operating point of the APE.
+ */
+int prcmu_set_ape_opp(u8 opp)
+{
+ int r = 0;
+
+ mutex_lock(&mb1_transfer.lock);
+
+ while (readl(_PRCMU_BASE + PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
+ cpu_relax();
+
+ writeb(MB1H_ARM_APE_OPP, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
+ writeb(ARM_NO_CHANGE, (tcdm_base + PRCM_REQ_MB1_ARM_OPP));
+ writeb(opp, (tcdm_base + PRCM_REQ_MB1_APE_OPP));
+
+ writel(MBOX_BIT(1), (_PRCMU_BASE + PRCM_MBOX_CPU_SET));
+ wait_for_completion(&mb1_transfer.work);
+
+ if ((mb1_transfer.ack.header != MB1H_ARM_APE_OPP) ||
+ (mb1_transfer.ack.ape_opp != opp))
+ r = -EIO;
+
+ mutex_unlock(&mb1_transfer.lock);
+
+ return r;
+}
+
+/**
+ * prcmu_get_ape_opp - get the current APE OPP
+ *
+ * Returns: the current APE OPP
+ */
+int prcmu_get_ape_opp(void)
+{
+ return readb(tcdm_base + PRCM_ACK_MB1_CURRENT_APE_OPP);
+}
+
+/**
+ * prcmu_request_ape_opp_100_voltage - Request APE OPP 100% voltage
+ * @enable: true to request the higher voltage, false to drop a request.
+ *
+ * Calls to this function to enable and disable requests must be balanced.
+ */
+int prcmu_request_ape_opp_100_voltage(bool enable)
+{
+ int r = 0;
+ u8 header;
+ static unsigned int requests;
+
+ mutex_lock(&mb1_transfer.lock);
+
+ if (enable) {
+ if (0 != requests++)
+ goto unlock_and_return;
+ header = MB1H_REQUEST_APE_OPP_100_VOLT;
+ } else {
+ if (requests == 0) {
+ r = -EIO;
+ goto unlock_and_return;
+ } else if (1 != requests--) {
+ goto unlock_and_return;
+ }
+ header = MB1H_RELEASE_APE_OPP_100_VOLT;
+ }
+
+ while (readl(_PRCMU_BASE + PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
+ cpu_relax();
+
+ writeb(header, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
+
+ writel(MBOX_BIT(1), (_PRCMU_BASE + PRCM_MBOX_CPU_SET));
+ wait_for_completion(&mb1_transfer.work);
+
+ if ((mb1_transfer.ack.header != header) ||
+ ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0))
+ r = -EIO;
+
+unlock_and_return:
+ mutex_unlock(&mb1_transfer.lock);
+
+ return r;
+}
+
+/**
+ * prcmu_release_usb_wakeup_state - release the state required by a USB wakeup
+ *
+ * This function releases the power state requirements of a USB wakeup.
+ */
+int prcmu_release_usb_wakeup_state(void)
+{
+ int r = 0;
+
+ mutex_lock(&mb1_transfer.lock);
+
+ while (readl(_PRCMU_BASE + PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
+ cpu_relax();
+
+ writeb(MB1H_RELEASE_USB_WAKEUP,
+ (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
+
+ writel(MBOX_BIT(1), (_PRCMU_BASE + PRCM_MBOX_CPU_SET));
+ wait_for_completion(&mb1_transfer.work);
+
+ if ((mb1_transfer.ack.header != MB1H_RELEASE_USB_WAKEUP) ||
+ ((mb1_transfer.ack.ape_voltage_status & BIT(0)) != 0))
+ r = -EIO;
+
+ mutex_unlock(&mb1_transfer.lock);
+
+ return r;
+}
+
+/**
+ * prcmu_set_epod - set the state of a EPOD (power domain)
+ * @epod_id: The EPOD to set
+ * @epod_state: The new EPOD state
+ *
+ * This function sets the state of a EPOD (power domain). It may not be called
+ * from interrupt context.
+ */
+int prcmu_set_epod(u16 epod_id, u8 epod_state)
+{
+ int r = 0;
+ bool ram_retention = false;
+ int i;
+
+ /* check argument */
+ BUG_ON(epod_id >= NUM_EPOD_ID);
+
+ /* set flag if retention is possible */
+ switch (epod_id) {
+ case EPOD_ID_SVAMMDSP:
+ case EPOD_ID_SIAMMDSP:
+ case EPOD_ID_ESRAM12:
+ case EPOD_ID_ESRAM34:
+ ram_retention = true;
+ break;
+ }
+
+ /* check argument */
+ BUG_ON(epod_state > EPOD_STATE_ON);
+ BUG_ON(epod_state == EPOD_STATE_RAMRET && !ram_retention);
+
+ /* get lock */
+ mutex_lock(&mb2_transfer.lock);
+
+ /* wait for mailbox */
+ while (readl(_PRCMU_BASE + PRCM_MBOX_CPU_VAL) & MBOX_BIT(2))
+ cpu_relax();
+
+ /* fill in mailbox */
+ for (i = 0; i < NUM_EPOD_ID; i++)
+ writeb(EPOD_STATE_NO_CHANGE, (tcdm_base + PRCM_REQ_MB2 + i));
+ writeb(epod_state, (tcdm_base + PRCM_REQ_MB2 + epod_id));
+
+ writeb(MB2H_DPS, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB2));
+
+ writel(MBOX_BIT(2), (_PRCMU_BASE + PRCM_MBOX_CPU_SET));
+
+ /*
+ * The current firmware version does not handle errors correctly,
+ * and we cannot recover if there is an error.
+ * This is expected to change when the firmware is updated.
+ */
+ if (!wait_for_completion_timeout(&mb2_transfer.work,
+ msecs_to_jiffies(20000))) {
+ pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
+ __func__);
+ r = -EIO;
+ goto unlock_and_return;
+ }
+
+ if (mb2_transfer.ack.status != HWACC_PWR_ST_OK)
+ r = -EIO;
+
+unlock_and_return:
+ mutex_unlock(&mb2_transfer.lock);
+ return r;
+}
+
+/**
+ * prcmu_configure_auto_pm - Configure autonomous power management.
+ * @sleep: Configuration for ApSleep.
+ * @idle: Configuration for ApIdle.
+ */
+void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
+ struct prcmu_auto_pm_config *idle)
+{
+ u32 sleep_cfg;
+ u32 idle_cfg;
+ unsigned long flags;
+
+ BUG_ON((sleep == NULL) || (idle == NULL));
+
+ sleep_cfg = (sleep->sva_auto_pm_enable & 0xF);
+ sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_auto_pm_enable & 0xF));
+ sleep_cfg = ((sleep_cfg << 8) | (sleep->sva_power_on & 0xFF));
+ sleep_cfg = ((sleep_cfg << 8) | (sleep->sia_power_on & 0xFF));
+ sleep_cfg = ((sleep_cfg << 4) | (sleep->sva_policy & 0xF));
+ sleep_cfg = ((sleep_cfg << 4) | (sleep->sia_policy & 0xF));
+
+ idle_cfg = (idle->sva_auto_pm_enable & 0xF);
+ idle_cfg = ((idle_cfg << 4) | (idle->sia_auto_pm_enable & 0xF));
+ idle_cfg = ((idle_cfg << 8) | (idle->sva_power_on & 0xFF));
+ idle_cfg = ((idle_cfg << 8) | (idle->sia_power_on & 0xFF));
+ idle_cfg = ((idle_cfg << 4) | (idle->sva_policy & 0xF));
+ idle_cfg = ((idle_cfg << 4) | (idle->sia_policy & 0xF));
+
+ spin_lock_irqsave(&mb2_transfer.auto_pm_lock, flags);
+
+ /*
+ * The autonomous power management configuration is done through
+ * fields in mailbox 2, but these fields are only used as shared
+ * variables - i.e. there is no need to send a message.
+ */
+ writel(sleep_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_SLEEP));
+ writel(idle_cfg, (tcdm_base + PRCM_REQ_MB2_AUTO_PM_IDLE));
+
+ mb2_transfer.auto_pm_enabled =
+ ((sleep->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
+ (sleep->sia_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
+ (idle->sva_auto_pm_enable == PRCMU_AUTO_PM_ON) ||
+ (idle->sia_auto_pm_enable == PRCMU_AUTO_PM_ON));
+
+ spin_unlock_irqrestore(&mb2_transfer.auto_pm_lock, flags);
+}
+EXPORT_SYMBOL(prcmu_configure_auto_pm);
+
+bool prcmu_is_auto_pm_enabled(void)
+{
+ return mb2_transfer.auto_pm_enabled;
+}
+
+static int request_sysclk(bool enable)
+{
+ int r;
+ unsigned long flags;
+
+ r = 0;
+
+ mutex_lock(&mb3_transfer.sysclk_lock);
+
+ spin_lock_irqsave(&mb3_transfer.lock, flags);
+
+ while (readl(_PRCMU_BASE + PRCM_MBOX_CPU_VAL) & MBOX_BIT(3))
+ cpu_relax();
+
+ writeb((enable ? ON : OFF), (tcdm_base + PRCM_REQ_MB3_SYSCLK_MGT));
+
+ writeb(MB3H_SYSCLK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB3));
+ writel(MBOX_BIT(3), (_PRCMU_BASE + PRCM_MBOX_CPU_SET));
+
+ spin_unlock_irqrestore(&mb3_transfer.lock, flags);
+
+ /*
+ * The firmware only sends an ACK if we want to enable the
+ * SysClk, and it succeeds.
+ */
+ if (enable && !wait_for_completion_timeout(&mb3_transfer.sysclk_work,
+ msecs_to_jiffies(20000))) {
+ pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
+ __func__);
+ r = -EIO;
+ }
+
+ mutex_unlock(&mb3_transfer.sysclk_lock);
+
+ return r;
+}
+
+static int request_timclk(bool enable)
+{
+ u32 val = (PRCM_TCR_DOZE_MODE | PRCM_TCR_TENSEL_MASK);
+
+ if (!enable)
+ val |= PRCM_TCR_STOP_TIMERS;
+ writel(val, (_PRCMU_BASE + PRCM_TCR));
+
+ return 0;
+}
+
+static int request_reg_clock(u8 clock, bool enable)
+{
+ u32 val;
+ unsigned long flags;
+
+ spin_lock_irqsave(&clk_mgt_lock, flags);
+
+ /* Grab the HW semaphore. */
+ while ((readl(_PRCMU_BASE + PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
+ cpu_relax();
+
+ val = readl(_PRCMU_BASE + clk_mgt[clock].offset);
+ if (enable) {
+ val |= (PRCM_CLK_MGT_CLKEN | clk_mgt[clock].pllsw);
+ } else {
+ clk_mgt[clock].pllsw = (val & PRCM_CLK_MGT_CLKPLLSW_MASK);
+ val &= ~(PRCM_CLK_MGT_CLKEN | PRCM_CLK_MGT_CLKPLLSW_MASK);
+ }
+ writel(val, (_PRCMU_BASE + clk_mgt[clock].offset));
+
+ /* Release the HW semaphore. */
+ writel(0, (_PRCMU_BASE + PRCM_SEM));
+
+ spin_unlock_irqrestore(&clk_mgt_lock, flags);
+
+ return 0;
+}
+
+/**
+ * prcmu_request_clock() - Request for a clock to be enabled or disabled.
+ * @clock: The clock for which the request is made.
+ * @enable: Whether the clock should be enabled (true) or disabled (false).
+ *
+ * This function should only be used by the clock implementation.
+ * Do not use it from any other place!
+ */
+int prcmu_request_clock(u8 clock, bool enable)
+{
+ if (clock < PRCMU_NUM_REG_CLOCKS)
+ return request_reg_clock(clock, enable);
+ else if (clock == PRCMU_TIMCLK)
+ return request_timclk(enable);
+ else if (clock == PRCMU_SYSCLK)
+ return request_sysclk(enable);
+ else
+ return -EINVAL;
+}
+
+int prcmu_config_esram0_deep_sleep(u8 state)
+{
+ if ((state > ESRAM0_DEEP_SLEEP_STATE_RET) ||
+ (state < ESRAM0_DEEP_SLEEP_STATE_OFF))
+ return -EINVAL;
+
+ mutex_lock(&mb4_transfer.lock);
+
+ while (readl(_PRCMU_BASE + PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
+ cpu_relax();
+
+ writeb(MB4H_MEM_ST, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
+ writeb(((DDR_PWR_STATE_OFFHIGHLAT << 4) | DDR_PWR_STATE_ON),
+ (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_SLEEP_IDLE));
+ writeb(DDR_PWR_STATE_ON,
+ (tcdm_base + PRCM_REQ_MB4_DDR_ST_AP_DEEP_IDLE));
+ writeb(state, (tcdm_base + PRCM_REQ_MB4_ESRAM0_ST));
+
+ writel(MBOX_BIT(4), (_PRCMU_BASE + PRCM_MBOX_CPU_SET));
+ wait_for_completion(&mb4_transfer.work);
+
+ mutex_unlock(&mb4_transfer.lock);
+
+ return 0;
+}
+
+int prcmu_config_hotdog(u8 threshold)
+{
+ mutex_lock(&mb4_transfer.lock);
+
+ while (readl(_PRCMU_BASE + PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
+ cpu_relax();
+
+ writeb(threshold, (tcdm_base + PRCM_REQ_MB4_HOTDOG_THRESHOLD));
+ writeb(MB4H_HOTDOG, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
+
+ writel(MBOX_BIT(4), (_PRCMU_BASE + PRCM_MBOX_CPU_SET));
+ wait_for_completion(&mb4_transfer.work);
+
+ mutex_unlock(&mb4_transfer.lock);
+
+ return 0;
+}
+
+int prcmu_config_hotmon(u8 low, u8 high)
+{
+ mutex_lock(&mb4_transfer.lock);
+
+ while (readl(_PRCMU_BASE + PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
+ cpu_relax();
+
+ writeb(low, (tcdm_base + PRCM_REQ_MB4_HOTMON_LOW));
+ writeb(high, (tcdm_base + PRCM_REQ_MB4_HOTMON_HIGH));
+ writeb((HOTMON_CONFIG_LOW | HOTMON_CONFIG_HIGH),
+ (tcdm_base + PRCM_REQ_MB4_HOTMON_CONFIG));
+ writeb(MB4H_HOTMON, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
+
+ writel(MBOX_BIT(4), (_PRCMU_BASE + PRCM_MBOX_CPU_SET));
+ wait_for_completion(&mb4_transfer.work);
+
+ mutex_unlock(&mb4_transfer.lock);
+
+ return 0;
+}
+
+static int config_hot_period(u16 val)
+{
+ mutex_lock(&mb4_transfer.lock);
+
+ while (readl(_PRCMU_BASE + PRCM_MBOX_CPU_VAL) & MBOX_BIT(4))
+ cpu_relax();
+
+ writew(val, (tcdm_base + PRCM_REQ_MB4_HOT_PERIOD));
+ writeb(MB4H_HOT_PERIOD, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB4));
+
+ writel(MBOX_BIT(4), (_PRCMU_BASE + PRCM_MBOX_CPU_SET));
+ wait_for_completion(&mb4_transfer.work);
+
+ mutex_unlock(&mb4_transfer.lock);
+
+ return 0;
+}
+
+int prcmu_start_temp_sense(u16 cycles32k)
+{
+ if (cycles32k == 0xFFFF)
+ return -EINVAL;
+
+ return config_hot_period(cycles32k);
+}
+
+int prcmu_stop_temp_sense(void)
+{
+ return config_hot_period(0xFFFF);
+}
+
+/**
+ * prcmu_set_clock_divider() - Configure the clock divider.
+ * @clock: The clock for which the request is made.
+ * @divider: The clock divider. (< 32)
+ *
+ * This function should only be used by the clock implementation.
+ * Do not use it from any other place!
+ */
+int prcmu_set_clock_divider(u8 clock, u8 divider)
+{
+ u32 val;
+ unsigned long flags;
+
+ if ((clock >= PRCMU_NUM_REG_CLOCKS) || (divider < 1) || (31 < divider))
+ return -EINVAL;
+
+ spin_lock_irqsave(&clk_mgt_lock, flags);
+
+ /* Grab the HW semaphore. */
+ while ((readl(_PRCMU_BASE + PRCM_SEM) & PRCM_SEM_PRCM_SEM) != 0)
+ cpu_relax();
+
+ val = readl(_PRCMU_BASE + clk_mgt[clock].offset);
+ val &= ~(PRCM_CLK_MGT_CLKPLLDIV_MASK);
+ val |= (u32)divider;
+ writel(val, (_PRCMU_BASE + clk_mgt[clock].offset));
+
+ /* Release the HW semaphore. */
+ writel(0, (_PRCMU_BASE + PRCM_SEM));
+
+ spin_unlock_irqrestore(&clk_mgt_lock, flags);
+
+ return 0;
+}
+
+/**
+ * prcmu_abb_read() - Read register value(s) from the ABB.
+ * @slave: The I2C slave address.
+ * @reg: The (start) register address.
+ * @value: The read out value(s).
+ * @size: The number of registers to read.
+ *
+ * Reads register value(s) from the ABB.
+ * @size has to be 1 for the current firmware version.
+ */
+int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
+{
+ int r;
+
+ if (size != 1)
+ return -EINVAL;
+
+ mutex_lock(&mb5_transfer.lock);
+
+ while (readl(_PRCMU_BASE + PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
+ cpu_relax();
+
+ writeb(PRCMU_I2C_READ(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP));
+ writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS));
+ writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG));
+ writeb(0, (tcdm_base + PRCM_REQ_MB5_I2C_VAL));
+
+ writel(MBOX_BIT(5), (_PRCMU_BASE + PRCM_MBOX_CPU_SET));
+
+ if (!wait_for_completion_timeout(&mb5_transfer.work,
+ msecs_to_jiffies(20000))) {
+ pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
+ __func__);
+ r = -EIO;
+ } else {
+ r = ((mb5_transfer.ack.status == I2C_RD_OK) ? 0 : -EIO);
+ }
+
+ if (!r)
+ *value = mb5_transfer.ack.value;
+
+ mutex_unlock(&mb5_transfer.lock);
+
+ return r;
+}
+
+/**
+ * prcmu_abb_write() - Write register value(s) to the ABB.
+ * @slave: The I2C slave address.
+ * @reg: The (start) register address.
+ * @value: The value(s) to write.
+ * @size: The number of registers to write.
+ *
+ * Reads register value(s) from the ABB.
+ * @size has to be 1 for the current firmware version.
+ */
+int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
+{
+ int r;
+
+ if (size != 1)
+ return -EINVAL;
+
+ mutex_lock(&mb5_transfer.lock);
+
+ while (readl(_PRCMU_BASE + PRCM_MBOX_CPU_VAL) & MBOX_BIT(5))
+ cpu_relax();
+
+ writeb(PRCMU_I2C_WRITE(slave), (tcdm_base + PRCM_REQ_MB5_I2C_SLAVE_OP));
+ writeb(PRCMU_I2C_STOP_EN, (tcdm_base + PRCM_REQ_MB5_I2C_HW_BITS));
+ writeb(reg, (tcdm_base + PRCM_REQ_MB5_I2C_REG));
+ writeb(*value, (tcdm_base + PRCM_REQ_MB5_I2C_VAL));
+
+ writel(MBOX_BIT(5), (_PRCMU_BASE + PRCM_MBOX_CPU_SET));
+
+ if (!wait_for_completion_timeout(&mb5_transfer.work,
+ msecs_to_jiffies(20000))) {
+ pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
+ __func__);
+ r = -EIO;
+ } else {
+ r = ((mb5_transfer.ack.status == I2C_WR_OK) ? 0 : -EIO);
+ }
+
+ mutex_unlock(&mb5_transfer.lock);
+
+ return r;
+}
+
+/**
+ * prcmu_ac_wake_req - should be called whenever ARM wants to wakeup Modem
+ */
+void prcmu_ac_wake_req(void)
+{
+ u32 val;
+
+ mutex_lock(&mb0_transfer.ac_wake_lock);
+
+ val = readl(_PRCMU_BASE + PRCM_HOSTACCESS_REQ);
+ if (val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ)
+ goto unlock_and_return;
+
+ atomic_set(&ac_wake_req_state, 1);
+
+ writel((val | PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ),
+ (_PRCMU_BASE + PRCM_HOSTACCESS_REQ));
+
+ if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work,
+ msecs_to_jiffies(20000))) {
+ pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
+ __func__);
+ }
+
+unlock_and_return:
+ mutex_unlock(&mb0_transfer.ac_wake_lock);
+}
+
+/**
+ * prcmu_ac_sleep_req - called when ARM no longer needs to talk to modem
+ */
+void prcmu_ac_sleep_req()
+{
+ u32 val;
+
+ mutex_lock(&mb0_transfer.ac_wake_lock);
+
+ val = readl(_PRCMU_BASE + PRCM_HOSTACCESS_REQ);
+ if (!(val & PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ))
+ goto unlock_and_return;
+
+ writel((val & ~PRCM_HOSTACCESS_REQ_HOSTACCESS_REQ),
+ (_PRCMU_BASE + PRCM_HOSTACCESS_REQ));
+
+ if (!wait_for_completion_timeout(&mb0_transfer.ac_wake_work,
+ msecs_to_jiffies(20000))) {
+ pr_err("prcmu: %s timed out (20 s) waiting for a reply.\n",
+ __func__);
+ }
+
+ atomic_set(&ac_wake_req_state, 0);
+
+unlock_and_return:
+ mutex_unlock(&mb0_transfer.ac_wake_lock);
+}
+
+bool prcmu_is_ac_wake_requested(void)
+{
+ return (atomic_read(&ac_wake_req_state) != 0);
+}
+
+/**
+ * prcmu_system_reset - System reset
+ *
+ * Saves the reset reason code and then sets the APE_SOFRST register which
+ * fires interrupt to fw
+ */
+void prcmu_system_reset(u16 reset_code)
+{
+ writew(reset_code, (tcdm_base + PRCM_SW_RST_REASON));
+ writel(1, (_PRCMU_BASE + PRCM_APE_SOFTRST));
+}
+
+/**
+ * prcmu_reset_modem - ask the PRCMU to reset modem
+ */
+void prcmu_modem_reset(void)
+{
+ mutex_lock(&mb1_transfer.lock);
+
+ while (readl(_PRCMU_BASE + PRCM_MBOX_CPU_VAL) & MBOX_BIT(1))
+ cpu_relax();
+
+ writeb(MB1H_RESET_MODEM, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB1));
+ writel(MBOX_BIT(1), (_PRCMU_BASE + PRCM_MBOX_CPU_SET));
+ wait_for_completion(&mb1_transfer.work);
+
+ /*
+ * No need to check return from PRCMU as modem should go in reset state
+ * This state is already managed by upper layer
+ */
+
+ mutex_unlock(&mb1_transfer.lock);
+}
+
+static void ack_dbb_wakeup(void)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&mb0_transfer.lock, flags);
+
+ while (readl(_PRCMU_BASE + PRCM_MBOX_CPU_VAL) & MBOX_BIT(0))
+ cpu_relax();
+
+ writeb(MB0H_READ_WAKEUP_ACK, (tcdm_base + PRCM_MBOX_HEADER_REQ_MB0));
+ writel(MBOX_BIT(0), (_PRCMU_BASE + PRCM_MBOX_CPU_SET));
+
+ spin_unlock_irqrestore(&mb0_transfer.lock, flags);
+}
+
+static inline void print_unknown_header_warning(u8 n, u8 header)
+{
+ pr_warning("prcmu: Unknown message header (%d) in mailbox %d.\n",
+ header, n);
+}
+
+static bool read_mailbox_0(void)
+{
+ bool r;
+ u32 ev;
+ unsigned int n;
+ u8 header;
+
+ header = readb(tcdm_base + PRCM_MBOX_HEADER_ACK_MB0);
+ switch (header) {
+ case MB0H_WAKEUP_EXE:
+ case MB0H_WAKEUP_SLEEP:
+ if (readb(tcdm_base + PRCM_ACK_MB0_READ_POINTER) & 1)
+ ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_1_8500);
+ else
+ ev = readl(tcdm_base + PRCM_ACK_MB0_WAKEUP_0_8500);
+
+ if (ev & (WAKEUP_BIT_AC_WAKE_ACK | WAKEUP_BIT_AC_SLEEP_ACK))
+ complete(&mb0_transfer.ac_wake_work);
+ if (ev & WAKEUP_BIT_SYSCLK_OK)
+ complete(&mb3_transfer.sysclk_work);
+
+ ev &= mb0_transfer.req.dbb_irqs;
+
+ for (n = 0; n < NUM_PRCMU_WAKEUPS; n++) {
+ if (ev & prcmu_irq_bit[n])
+ generic_handle_irq(IRQ_PRCMU_BASE + n);
+ }
+ r = true;
+ break;
+ default:
+ print_unknown_header_warning(0, header);
+ r = false;
+ break;
+ }
+ writel(MBOX_BIT(0), (_PRCMU_BASE + PRCM_ARM_IT1_CLR));
+ return r;
+}
+
+static bool read_mailbox_1(void)
+{
+ mb1_transfer.ack.header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB1);
+ mb1_transfer.ack.arm_opp = readb(tcdm_base +
+ PRCM_ACK_MB1_CURRENT_ARM_OPP);
+ mb1_transfer.ack.ape_opp = readb(tcdm_base +
+ PRCM_ACK_MB1_CURRENT_APE_OPP);
+ mb1_transfer.ack.ape_voltage_status = readb(tcdm_base +
+ PRCM_ACK_MB1_APE_VOLTAGE_STATUS);
+ writel(MBOX_BIT(1), (_PRCMU_BASE + PRCM_ARM_IT1_CLR));
+ complete(&mb1_transfer.work);
+ return false;
+}
+
+static bool read_mailbox_2(void)
+{
+ mb2_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB2_DPS_STATUS);
+ writel(MBOX_BIT(2), (_PRCMU_BASE + PRCM_ARM_IT1_CLR));
+ complete(&mb2_transfer.work);
+ return false;
+}
+
+static bool read_mailbox_3(void)
+{
+ writel(MBOX_BIT(3), (_PRCMU_BASE + PRCM_ARM_IT1_CLR));
+ return false;
+}
+
+static bool read_mailbox_4(void)
+{
+ u8 header;
+ bool do_complete = true;
+
+ header = readb(tcdm_base + PRCM_MBOX_HEADER_REQ_MB4);
+ switch (header) {
+ case MB4H_MEM_ST:
+ case MB4H_HOTDOG:
+ case MB4H_HOTMON:
+ case MB4H_HOT_PERIOD:
+ break;
+ default:
+ print_unknown_header_warning(4, header);
+ do_complete = false;
+ break;
+ }
+
+ writel(MBOX_BIT(4), (_PRCMU_BASE + PRCM_ARM_IT1_CLR));
+
+ if (do_complete)
+ complete(&mb4_transfer.work);
+
+ return false;
+}
+
+static bool read_mailbox_5(void)
+{
+ mb5_transfer.ack.status = readb(tcdm_base + PRCM_ACK_MB5_I2C_STATUS);
+ mb5_transfer.ack.value = readb(tcdm_base + PRCM_ACK_MB5_I2C_VAL);
+ writel(MBOX_BIT(5), (_PRCMU_BASE + PRCM_ARM_IT1_CLR));
+ complete(&mb5_transfer.work);
+ return false;
+}
+
+static bool read_mailbox_6(void)
+{
+ writel(MBOX_BIT(6), (_PRCMU_BASE + PRCM_ARM_IT1_CLR));
+ return false;
+}
+
+static bool read_mailbox_7(void)
+{
+ writel(MBOX_BIT(7), (_PRCMU_BASE + PRCM_ARM_IT1_CLR));
+ return false;
+}
+
+static bool (* const read_mailbox[NUM_MB])(void) = {
+ read_mailbox_0,
+ read_mailbox_1,
+ read_mailbox_2,
+ read_mailbox_3,
+ read_mailbox_4,
+ read_mailbox_5,
+ read_mailbox_6,
+ read_mailbox_7
+};
+
+static irqreturn_t prcmu_irq_handler(int irq, void *data)
+{
+ u32 bits;
+ u8 n;
+ irqreturn_t r;
+
+ bits = (readl(_PRCMU_BASE + PRCM_ARM_IT1_VAL) & ALL_MBOX_BITS);
+ if (unlikely(!bits))
+ return IRQ_NONE;
+
+ r = IRQ_HANDLED;
+ for (n = 0; bits; n++) {
+ if (bits & MBOX_BIT(n)) {
+ bits -= MBOX_BIT(n);
+ if (read_mailbox[n]())
+ r = IRQ_WAKE_THREAD;
+ }
+ }
+ return r;
+}
+
+static irqreturn_t prcmu_irq_thread_fn(int irq, void *data)
+{
+ ack_dbb_wakeup();
+ return IRQ_HANDLED;
+}
+
+static void prcmu_mask_work(struct work_struct *work)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&mb0_transfer.lock, flags);
+
+ config_wakeups();
+
+ spin_unlock_irqrestore(&mb0_transfer.lock, flags);
+}
+
+static void prcmu_irq_mask(struct irq_data *d)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags);
+
+ mb0_transfer.req.dbb_irqs &= ~prcmu_irq_bit[d->irq - IRQ_PRCMU_BASE];
+
+ spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags);
+
+ if (d->irq != IRQ_PRCMU_CA_SLEEP)
+ schedule_work(&mb0_transfer.mask_work);
+}
+
+static void prcmu_irq_unmask(struct irq_data *d)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&mb0_transfer.dbb_irqs_lock, flags);
+
+ mb0_transfer.req.dbb_irqs |= prcmu_irq_bit[d->irq - IRQ_PRCMU_BASE];
+
+ spin_unlock_irqrestore(&mb0_transfer.dbb_irqs_lock, flags);
+
+ if (d->irq != IRQ_PRCMU_CA_SLEEP)
+ schedule_work(&mb0_transfer.mask_work);
+}
+
+static void noop(struct irq_data *d)
+{
+}
+
+static struct irq_chip prcmu_irq_chip = {
+ .name = "prcmu",
+ .irq_disable = prcmu_irq_mask,
+ .irq_ack = noop,
+ .irq_mask = prcmu_irq_mask,
+ .irq_unmask = prcmu_irq_unmask,
+};
+
+void __init prcmu_early_init(void)
+{
+ unsigned int i;
+
+ if (cpu_is_u8500v1()) {
+ tcdm_base = __io_address(U8500_PRCMU_TCDM_BASE_V1);
+ } else if (cpu_is_u8500v2()) {
+ void *tcpm_base = ioremap_nocache(U8500_PRCMU_TCPM_BASE, SZ_4K);
+
+ if (tcpm_base != NULL) {
+ int version;
+ version = readl(tcpm_base + PRCMU_FW_VERSION_OFFSET);
+ prcmu_version.project_number = version & 0xFF;
+ prcmu_version.api_version = (version >> 8) & 0xFF;
+ prcmu_version.func_version = (version >> 16) & 0xFF;
+ prcmu_version.errata = (version >> 24) & 0xFF;
+ pr_info("PRCMU firmware version %d.%d.%d\n",
+ (version >> 8) & 0xFF, (version >> 16) & 0xFF,
+ (version >> 24) & 0xFF);
+ iounmap(tcpm_base);
+ }
+
+ tcdm_base = __io_address(U8500_PRCMU_TCDM_BASE);
+ } else {
+ pr_err("prcmu: Unsupported chip version\n");
+ BUG();
+ }
+
+ spin_lock_init(&mb0_transfer.lock);
+ spin_lock_init(&mb0_transfer.dbb_irqs_lock);
+ mutex_init(&mb0_transfer.ac_wake_lock);
+ init_completion(&mb0_transfer.ac_wake_work);
+ mutex_init(&mb1_transfer.lock);
+ init_completion(&mb1_transfer.work);
+ mutex_init(&mb2_transfer.lock);
+ init_completion(&mb2_transfer.work);
+ spin_lock_init(&mb2_transfer.auto_pm_lock);
+ spin_lock_init(&mb3_transfer.lock);
+ mutex_init(&mb3_transfer.sysclk_lock);
+ init_completion(&mb3_transfer.sysclk_work);
+ mutex_init(&mb4_transfer.lock);
+ init_completion(&mb4_transfer.work);
+ mutex_init(&mb5_transfer.lock);
+ init_completion(&mb5_transfer.work);
+
+ INIT_WORK(&mb0_transfer.mask_work, prcmu_mask_work);
+
+ /* Initalize irqs. */
+ for (i = 0; i < NUM_PRCMU_WAKEUPS; i++) {
+ unsigned int irq;
+
+ irq = IRQ_PRCMU_BASE + i;
+ irq_set_chip_and_handler(irq, &prcmu_irq_chip,
+ handle_simple_irq);
+ set_irq_flags(irq, IRQF_VALID);
+ }
+}
+
+/*
+ * Power domain switches (ePODs) modeled as regulators for the DB8500 SoC
+ */
+static struct regulator_consumer_supply db8500_vape_consumers[] = {
+ REGULATOR_SUPPLY("v-ape", NULL),
+ REGULATOR_SUPPLY("v-i2c", "nmk-i2c.0"),
+ REGULATOR_SUPPLY("v-i2c", "nmk-i2c.1"),
+ REGULATOR_SUPPLY("v-i2c", "nmk-i2c.2"),
+ REGULATOR_SUPPLY("v-i2c", "nmk-i2c.3"),
+ /* "v-mmc" changed to "vcore" in the mainline kernel */
+ REGULATOR_SUPPLY("vcore", "sdi0"),
+ REGULATOR_SUPPLY("vcore", "sdi1"),
+ REGULATOR_SUPPLY("vcore", "sdi2"),
+ REGULATOR_SUPPLY("vcore", "sdi3"),
+ REGULATOR_SUPPLY("vcore", "sdi4"),
+ REGULATOR_SUPPLY("v-dma", "dma40.0"),
+ REGULATOR_SUPPLY("v-ape", "ab8500-usb.0"),
+ /* "v-uart" changed to "vcore" in the mainline kernel */
+ REGULATOR_SUPPLY("vcore", "uart0"),
+ REGULATOR_SUPPLY("vcore", "uart1"),
+ REGULATOR_SUPPLY("vcore", "uart2"),
+ REGULATOR_SUPPLY("v-ape", "nmk-ske-keypad.0"),
+};
+
+static struct regulator_consumer_supply db8500_vsmps2_consumers[] = {
+ /* CG2900 and CW1200 power to off-chip peripherals */
+ REGULATOR_SUPPLY("gbf_1v8", "cg2900-uart.0"),
+ REGULATOR_SUPPLY("wlan_1v8", "cw1200.0"),
+ REGULATOR_SUPPLY("musb_1v8", "ab8500-usb.0"),
+ /* AV8100 regulator */
+ REGULATOR_SUPPLY("hdmi_1v8", "0-0070"),
+};
+
+static struct regulator_consumer_supply db8500_b2r2_mcde_consumers[] = {
+ REGULATOR_SUPPLY("vsupply", "b2r2.0"),
+ REGULATOR_SUPPLY("vsupply", "mcde.0"),
+};
+
+static struct regulator_init_data db8500_regulators[DB8500_NUM_REGULATORS] = {
+ [DB8500_REGULATOR_VAPE] = {
+ .constraints = {
+ .name = "db8500-vape",
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ },
+ .consumer_supplies = db8500_vape_consumers,
+ .num_consumer_supplies = ARRAY_SIZE(db8500_vape_consumers),
+ },
+ [DB8500_REGULATOR_VARM] = {
+ .constraints = {
+ .name = "db8500-varm",
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ },
+ },
+ [DB8500_REGULATOR_VMODEM] = {
+ .constraints = {
+ .name = "db8500-vmodem",
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ },
+ },
+ [DB8500_REGULATOR_VPLL] = {
+ .constraints = {
+ .name = "db8500-vpll",
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ },
+ },
+ [DB8500_REGULATOR_VSMPS1] = {
+ .constraints = {
+ .name = "db8500-vsmps1",
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ },
+ },
+ [DB8500_REGULATOR_VSMPS2] = {
+ .constraints = {
+ .name = "db8500-vsmps2",
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ },
+ .consumer_supplies = db8500_vsmps2_consumers,
+ .num_consumer_supplies = ARRAY_SIZE(db8500_vsmps2_consumers),
+ },
+ [DB8500_REGULATOR_VSMPS3] = {
+ .constraints = {
+ .name = "db8500-vsmps3",
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ },
+ },
+ [DB8500_REGULATOR_VRF1] = {
+ .constraints = {
+ .name = "db8500-vrf1",
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ },
+ },
+ [DB8500_REGULATOR_SWITCH_SVAMMDSP] = {
+ .supply_regulator = "db8500-vape",
+ .constraints = {
+ .name = "db8500-sva-mmdsp",
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ },
+ },
+ [DB8500_REGULATOR_SWITCH_SVAMMDSPRET] = {
+ .constraints = {
+ /* "ret" means "retention" */
+ .name = "db8500-sva-mmdsp-ret",
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ },
+ },
+ [DB8500_REGULATOR_SWITCH_SVAPIPE] = {
+ .supply_regulator = "db8500-vape",
+ .constraints = {
+ .name = "db8500-sva-pipe",
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ },
+ },
+ [DB8500_REGULATOR_SWITCH_SIAMMDSP] = {
+ .supply_regulator = "db8500-vape",
+ .constraints = {
+ .name = "db8500-sia-mmdsp",
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ },
+ },
+ [DB8500_REGULATOR_SWITCH_SIAMMDSPRET] = {
+ .constraints = {
+ .name = "db8500-sia-mmdsp-ret",
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ },
+ },
+ [DB8500_REGULATOR_SWITCH_SIAPIPE] = {
+ .supply_regulator = "db8500-vape",
+ .constraints = {
+ .name = "db8500-sia-pipe",
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ },
+ },
+ [DB8500_REGULATOR_SWITCH_SGA] = {
+ .supply_regulator = "db8500-vape",
+ .constraints = {
+ .name = "db8500-sga",
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ },
+ },
+ [DB8500_REGULATOR_SWITCH_B2R2_MCDE] = {
+ .supply_regulator = "db8500-vape",
+ .constraints = {
+ .name = "db8500-b2r2-mcde",
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ },
+ .consumer_supplies = db8500_b2r2_mcde_consumers,
+ .num_consumer_supplies = ARRAY_SIZE(db8500_b2r2_mcde_consumers),
+ },
+ [DB8500_REGULATOR_SWITCH_ESRAM12] = {
+ .supply_regulator = "db8500-vape",
+ .constraints = {
+ .name = "db8500-esram12",
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ },
+ },
+ [DB8500_REGULATOR_SWITCH_ESRAM12RET] = {
+ .constraints = {
+ .name = "db8500-esram12-ret",
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ },
+ },
+ [DB8500_REGULATOR_SWITCH_ESRAM34] = {
+ .supply_regulator = "db8500-vape",
+ .constraints = {
+ .name = "db8500-esram34",
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ },
+ },
+ [DB8500_REGULATOR_SWITCH_ESRAM34RET] = {
+ .constraints = {
+ .name = "db8500-esram34-ret",
+ .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+ },
+ },
+};
+
+static struct mfd_cell db8500_prcmu_devs[] = {
+ {
+ .name = "db8500-prcmu-regulators",
+ .mfd_data = &db8500_regulators,
+ },
+ {
+ .name = "cpufreq-u8500",
+ },
+};
+
+/**
+ * prcmu_fw_init - arch init call for the Linux PRCMU fw init logic
+ *
+ */
+static int __init db8500_prcmu_probe(struct platform_device *pdev)
+{
+ int err = 0;
+
+ if (ux500_is_svp())
+ return -ENODEV;
+
+ /* Clean up the mailbox interrupts after pre-kernel code. */
+ writel(ALL_MBOX_BITS, (_PRCMU_BASE + PRCM_ARM_IT1_CLR));
+
+ err = request_threaded_irq(IRQ_DB8500_PRCMU1, prcmu_irq_handler,
+ prcmu_irq_thread_fn, IRQF_NO_SUSPEND, "prcmu", NULL);
+ if (err < 0) {
+ pr_err("prcmu: Failed to allocate IRQ_DB8500_PRCMU1.\n");
+ err = -EBUSY;
+ goto no_irq_return;
+ }
+
+ if (cpu_is_u8500v20_or_later())
+ prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET);
+
+ err = mfd_add_devices(&pdev->dev, 0, db8500_prcmu_devs,
+ ARRAY_SIZE(db8500_prcmu_devs), NULL,
+ 0);
+
+ if (err)
+ pr_err("prcmu: Failed to add subdevices\n");
+ else
+ pr_info("DB8500 PRCMU initialized\n");
+
+no_irq_return:
+ return err;
+}
+
+static struct platform_driver db8500_prcmu_driver = {
+ .driver = {
+ .name = "db8500-prcmu",
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init db8500_prcmu_init(void)
+{
+ return platform_driver_probe(&db8500_prcmu_driver, db8500_prcmu_probe);
+}
+
+arch_initcall(db8500_prcmu_init);
+
+MODULE_AUTHOR("Mattias Nilsson <mattias.i.nilsson@stericsson.com>");
+MODULE_DESCRIPTION("DB8500 PRCM Unit driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index d80dcde..4e349cd 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -144,6 +144,19 @@
If you choose to build module, its name will be phantom. If unsure,
say N here.
+config INTEL_MID_PTI
+ tristate "Parallel Trace Interface for MIPI P1149.7 cJTAG standard"
+ default n
+ help
+ The PTI (Parallel Trace Interface) driver directs
+ trace data routed from various parts in the system out
+ through an Intel Penwell PTI port and out of the mobile
+ device for analysis with a debugging tool (Lauterbach or Fido).
+
+ You should select this driver if the target kernel is meant for
+ an Intel Atom (non-netbook) mobile device containing a MIPI
+ P1149.7 standard implementation.
+
config SGI_IOC4
tristate "SGI IOC4 Base IO support"
depends on PCI
@@ -459,7 +472,7 @@
module will be called bmp085.
config PCH_PHUB
- tristate "PCH Packet Hub of Intel Topcliff / OKI SEMICONDUCTOR ML7213"
+ tristate "Intel EG20T PCH / OKI SEMICONDUCTOR IOH(ML7213/ML7223) PHUB"
depends on PCI
help
This driver is for PCH(Platform controller Hub) PHUB(Packet Hub) of
@@ -467,10 +480,12 @@
processor. The Topcliff has MAC address and Option ROM data in SROM.
This driver can access MAC address and Option ROM data in SROM.
- This driver also can be used for OKI SEMICONDUCTOR's ML7213 which is
- for IVI(In-Vehicle Infotainment) use.
- ML7213 is companion chip for Intel Atom E6xx series.
- ML7213 is completely compatible for Intel EG20T PCH.
+ This driver also can be used for OKI SEMICONDUCTOR IOH(Input/
+ Output Hub), ML7213 and ML7223.
+ ML7213 IOH is for IVI(In-Vehicle Infotainment) use and ML7223 IOH is
+ for MP(Media Phone) use.
+ ML7213/ML7223 is companion chip for Intel Atom E6xx series.
+ ML7213/ML7223 is completely compatible for Intel EG20T PCH.
To compile this driver as a module, choose M here: the module will
be called pch_phub.
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index 848e846..5f03172 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -6,6 +6,7 @@
obj-$(CONFIG_AD525X_DPOT) += ad525x_dpot.o
obj-$(CONFIG_AD525X_DPOT_I2C) += ad525x_dpot-i2c.o
obj-$(CONFIG_AD525X_DPOT_SPI) += ad525x_dpot-spi.o
+0bj-$(CONFIG_INTEL_MID_PTI) += pti.o
obj-$(CONFIG_ATMEL_PWM) += atmel_pwm.o
obj-$(CONFIG_ATMEL_SSC) += atmel-ssc.o
obj-$(CONFIG_ATMEL_TCLIB) += atmel_tclib.o
diff --git a/drivers/misc/pch_phub.c b/drivers/misc/pch_phub.c
index a19cb71..5fe79df 100644
--- a/drivers/misc/pch_phub.c
+++ b/drivers/misc/pch_phub.c
@@ -34,12 +34,18 @@
#define PHUB_TIMEOUT 0x05 /* Time out value for Status Register */
#define PCH_PHUB_ROM_WRITE_ENABLE 0x01 /* Enabling for writing ROM */
#define PCH_PHUB_ROM_WRITE_DISABLE 0x00 /* Disabling for writing ROM */
-#define PCH_PHUB_MAC_START_ADDR 0x20C /* MAC data area start address offset */
-#define PCH_PHUB_ROM_START_ADDR_EG20T 0x14 /* ROM data area start address offset
+#define PCH_PHUB_MAC_START_ADDR_EG20T 0x14 /* MAC data area start address
+ offset */
+#define PCH_PHUB_MAC_START_ADDR_ML7223 0x20C /* MAC data area start address
+ offset */
+#define PCH_PHUB_ROM_START_ADDR_EG20T 0x80 /* ROM data area start address offset
(Intel EG20T PCH)*/
#define PCH_PHUB_ROM_START_ADDR_ML7213 0x400 /* ROM data area start address
offset(OKI SEMICONDUCTOR ML7213)
*/
+#define PCH_PHUB_ROM_START_ADDR_ML7223 0x400 /* ROM data area start address
+ offset(OKI SEMICONDUCTOR ML7223)
+ */
/* MAX number of INT_REDUCE_CONTROL registers */
#define MAX_NUM_INT_REDUCE_CONTROL_REG 128
@@ -63,6 +69,10 @@
#define PCI_VENDOR_ID_ROHM 0x10db
#define PCI_DEVICE_ID_ROHM_ML7213_PHUB 0x801A
+/* Macros for ML7223 */
+#define PCI_DEVICE_ID_ROHM_ML7223_mPHUB 0x8012 /* for Bus-m */
+#define PCI_DEVICE_ID_ROHM_ML7223_nPHUB 0x8002 /* for Bus-n */
+
/* SROM ACCESS Macro */
#define PCH_WORD_ADDR_MASK (~((1 << 2) - 1))
@@ -100,6 +110,9 @@
* @clkcfg_reg: CLK CFG register val
* @pch_phub_base_address: Register base address
* @pch_phub_extrom_base_address: external rom base address
+ * @pch_mac_start_address: MAC address area start address
+ * @pch_opt_rom_start_address: Option ROM start address
+ * @ioh_type: Save IOH type
*/
struct pch_phub_reg {
u32 phub_id_reg;
@@ -117,6 +130,9 @@
u32 clkcfg_reg;
void __iomem *pch_phub_base_address;
void __iomem *pch_phub_extrom_base_address;
+ u32 pch_mac_start_address;
+ u32 pch_opt_rom_start_address;
+ int ioh_type;
};
/* SROM SPEC for MAC address assignment offset */
@@ -319,7 +335,7 @@
{
unsigned int mem_addr;
- mem_addr = PCH_PHUB_ROM_START_ADDR_EG20T +
+ mem_addr = chip->pch_mac_start_address +
pch_phub_mac_offset[offset_address];
pch_phub_read_serial_rom(chip, mem_addr, data);
@@ -336,7 +352,7 @@
int retval;
unsigned int mem_addr;
- mem_addr = PCH_PHUB_ROM_START_ADDR_EG20T +
+ mem_addr = chip->pch_mac_start_address +
pch_phub_mac_offset[offset_address];
retval = pch_phub_write_serial_rom(chip, mem_addr, data);
@@ -384,6 +400,48 @@
return retval;
}
+/* pch_phub_gbe_serial_rom_conf_mp - makes SerialROM header format configuration
+ * for Gigabit Ethernet MAC address
+ */
+static int pch_phub_gbe_serial_rom_conf_mp(struct pch_phub_reg *chip)
+{
+ int retval;
+ u32 offset_addr;
+
+ offset_addr = 0x200;
+ retval = pch_phub_write_serial_rom(chip, 0x03 + offset_addr, 0xbc);
+ retval |= pch_phub_write_serial_rom(chip, 0x02 + offset_addr, 0x00);
+ retval |= pch_phub_write_serial_rom(chip, 0x01 + offset_addr, 0x40);
+ retval |= pch_phub_write_serial_rom(chip, 0x00 + offset_addr, 0x02);
+
+ retval |= pch_phub_write_serial_rom(chip, 0x07 + offset_addr, 0x00);
+ retval |= pch_phub_write_serial_rom(chip, 0x06 + offset_addr, 0x00);
+ retval |= pch_phub_write_serial_rom(chip, 0x05 + offset_addr, 0x00);
+ retval |= pch_phub_write_serial_rom(chip, 0x04 + offset_addr, 0x80);
+
+ retval |= pch_phub_write_serial_rom(chip, 0x0b + offset_addr, 0xbc);
+ retval |= pch_phub_write_serial_rom(chip, 0x0a + offset_addr, 0x00);
+ retval |= pch_phub_write_serial_rom(chip, 0x09 + offset_addr, 0x40);
+ retval |= pch_phub_write_serial_rom(chip, 0x08 + offset_addr, 0x18);
+
+ retval |= pch_phub_write_serial_rom(chip, 0x13 + offset_addr, 0xbc);
+ retval |= pch_phub_write_serial_rom(chip, 0x12 + offset_addr, 0x00);
+ retval |= pch_phub_write_serial_rom(chip, 0x11 + offset_addr, 0x40);
+ retval |= pch_phub_write_serial_rom(chip, 0x10 + offset_addr, 0x19);
+
+ retval |= pch_phub_write_serial_rom(chip, 0x1b + offset_addr, 0xbc);
+ retval |= pch_phub_write_serial_rom(chip, 0x1a + offset_addr, 0x00);
+ retval |= pch_phub_write_serial_rom(chip, 0x19 + offset_addr, 0x40);
+ retval |= pch_phub_write_serial_rom(chip, 0x18 + offset_addr, 0x3a);
+
+ retval |= pch_phub_write_serial_rom(chip, 0x1f + offset_addr, 0x01);
+ retval |= pch_phub_write_serial_rom(chip, 0x1e + offset_addr, 0x00);
+ retval |= pch_phub_write_serial_rom(chip, 0x1d + offset_addr, 0x00);
+ retval |= pch_phub_write_serial_rom(chip, 0x1c + offset_addr, 0x00);
+
+ return retval;
+}
+
/**
* pch_phub_read_gbe_mac_addr() - Read Gigabit Ethernet MAC address
* @offset_address: Gigabit Ethernet MAC address offset value.
@@ -406,7 +464,10 @@
int retval;
int i;
- retval = pch_phub_gbe_serial_rom_conf(chip);
+ if (chip->ioh_type == 1) /* EG20T */
+ retval = pch_phub_gbe_serial_rom_conf(chip);
+ else /* ML7223 */
+ retval = pch_phub_gbe_serial_rom_conf_mp(chip);
if (retval)
return retval;
@@ -441,12 +502,16 @@
}
/* Get Rom signature */
- pch_phub_read_serial_rom(chip, 0x80, (unsigned char *)&rom_signature);
+ pch_phub_read_serial_rom(chip, chip->pch_opt_rom_start_address,
+ (unsigned char *)&rom_signature);
rom_signature &= 0xff;
- pch_phub_read_serial_rom(chip, 0x81, (unsigned char *)&tmp);
+ pch_phub_read_serial_rom(chip, chip->pch_opt_rom_start_address + 1,
+ (unsigned char *)&tmp);
rom_signature |= (tmp & 0xff) << 8;
if (rom_signature == 0xAA55) {
- pch_phub_read_serial_rom(chip, 0x82, &rom_length);
+ pch_phub_read_serial_rom(chip,
+ chip->pch_opt_rom_start_address + 2,
+ &rom_length);
orom_size = rom_length * 512;
if (orom_size < off) {
addr_offset = 0;
@@ -458,8 +523,9 @@
}
for (addr_offset = 0; addr_offset < count; addr_offset++) {
- pch_phub_read_serial_rom(chip, 0x80 + addr_offset + off,
- &buf[addr_offset]);
+ pch_phub_read_serial_rom(chip,
+ chip->pch_opt_rom_start_address + addr_offset + off,
+ &buf[addr_offset]);
}
} else {
err = -ENODATA;
@@ -502,8 +568,9 @@
if (PCH_PHUB_OROM_SIZE < off + addr_offset)
goto return_ok;
- ret = pch_phub_write_serial_rom(chip, 0x80 + addr_offset + off,
- buf[addr_offset]);
+ ret = pch_phub_write_serial_rom(chip,
+ chip->pch_opt_rom_start_address + addr_offset + off,
+ buf[addr_offset]);
if (ret) {
err = ret;
goto return_err;
@@ -603,19 +670,22 @@
dev_dbg(&pdev->dev, "%s : pci_iomap SUCCESS and value "
"in pch_phub_base_address variable is %p\n", __func__,
chip->pch_phub_base_address);
- chip->pch_phub_extrom_base_address = pci_map_rom(pdev, &rom_size);
- if (chip->pch_phub_extrom_base_address == 0) {
- dev_err(&pdev->dev, "%s : pci_map_rom FAILED", __func__);
- ret = -ENOMEM;
- goto err_pci_map;
+ if (id->driver_data != 3) {
+ chip->pch_phub_extrom_base_address =\
+ pci_map_rom(pdev, &rom_size);
+ if (chip->pch_phub_extrom_base_address == 0) {
+ dev_err(&pdev->dev, "%s: pci_map_rom FAILED", __func__);
+ ret = -ENOMEM;
+ goto err_pci_map;
+ }
+ dev_dbg(&pdev->dev, "%s : "
+ "pci_map_rom SUCCESS and value in "
+ "pch_phub_extrom_base_address variable is %p\n",
+ __func__, chip->pch_phub_extrom_base_address);
}
- dev_dbg(&pdev->dev, "%s : "
- "pci_map_rom SUCCESS and value in "
- "pch_phub_extrom_base_address variable is %p\n", __func__,
- chip->pch_phub_extrom_base_address);
- if (id->driver_data == 1) {
+ if (id->driver_data == 1) { /* EG20T PCH */
retval = sysfs_create_file(&pdev->dev.kobj,
&dev_attr_pch_mac.attr);
if (retval)
@@ -642,7 +712,9 @@
iowrite32(0x000affaa, chip->pch_phub_base_address + 0x14);
/* set the interrupt delay value */
iowrite32(0x25, chip->pch_phub_base_address + 0x44);
- } else if (id->driver_data == 2) {
+ chip->pch_opt_rom_start_address = PCH_PHUB_ROM_START_ADDR_EG20T;
+ chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_EG20T;
+ } else if (id->driver_data == 2) { /* ML7213 IOH */
retval = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr);
if (retval)
goto err_sysfs_create;
@@ -653,7 +725,38 @@
* Device8(USB OHCI #0/ USB EHCI #0):a
*/
iowrite32(0x000affa0, chip->pch_phub_base_address + 0x14);
+ chip->pch_opt_rom_start_address =\
+ PCH_PHUB_ROM_START_ADDR_ML7213;
+ } else if (id->driver_data == 3) { /* ML7223 IOH Bus-m*/
+ /* set the prefech value
+ * Device8(GbE)
+ */
+ iowrite32(0x000a0000, chip->pch_phub_base_address + 0x14);
+ chip->pch_opt_rom_start_address =\
+ PCH_PHUB_ROM_START_ADDR_ML7223;
+ chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_ML7223;
+ } else if (id->driver_data == 4) { /* ML7223 IOH Bus-n*/
+ retval = sysfs_create_file(&pdev->dev.kobj,
+ &dev_attr_pch_mac.attr);
+ if (retval)
+ goto err_sysfs_create;
+ retval = sysfs_create_bin_file(&pdev->dev.kobj, &pch_bin_attr);
+ if (retval)
+ goto exit_bin_attr;
+ /* set the prefech value
+ * Device2(USB OHCI #0,1,2,3/ USB EHCI #0):a
+ * Device4(SDIO #0,1):f
+ * Device6(SATA 2):f
+ */
+ iowrite32(0x0000ffa0, chip->pch_phub_base_address + 0x14);
+ /* set the interrupt delay value */
+ iowrite32(0x25, chip->pch_phub_base_address + 0x140);
+ chip->pch_opt_rom_start_address =\
+ PCH_PHUB_ROM_START_ADDR_ML7223;
+ chip->pch_mac_start_address = PCH_PHUB_MAC_START_ADDR_ML7223;
}
+
+ chip->ioh_type = id->driver_data;
pci_set_drvdata(pdev, chip);
return 0;
@@ -733,6 +836,8 @@
static struct pci_device_id pch_phub_pcidev_id[] = {
{ PCI_VDEVICE(INTEL, PCI_DEVICE_ID_PCH1_PHUB), 1, },
{ PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7213_PHUB), 2, },
+ { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7223_mPHUB), 3, },
+ { PCI_VDEVICE(ROHM, PCI_DEVICE_ID_ROHM_ML7223_nPHUB), 4, },
{ }
};
MODULE_DEVICE_TABLE(pci, pch_phub_pcidev_id);
@@ -759,5 +864,5 @@
module_init(pch_phub_pci_init);
module_exit(pch_phub_pci_exit);
-MODULE_DESCRIPTION("PCH Packet Hub PCI Driver");
+MODULE_DESCRIPTION("Intel EG20T PCH/OKI SEMICONDUCTOR IOH(ML7213/ML7223) PHUB");
MODULE_LICENSE("GPL");
diff --git a/drivers/misc/pti.c b/drivers/misc/pti.c
new file mode 100644
index 0000000..bb6f925
--- /dev/null
+++ b/drivers/misc/pti.c
@@ -0,0 +1,980 @@
+/*
+ * pti.c - PTI driver for cJTAG data extration
+ *
+ * Copyright (C) Intel 2010
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ * The PTI (Parallel Trace Interface) driver directs trace data routed from
+ * various parts in the system out through the Intel Penwell PTI port and
+ * out of the mobile device for analysis with a debugging tool
+ * (Lauterbach, Fido). This is part of a solution for the MIPI P1149.7,
+ * compact JTAG, standard.
+ */
+
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/console.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/tty.h>
+#include <linux/tty_driver.h>
+#include <linux/pci.h>
+#include <linux/mutex.h>
+#include <linux/miscdevice.h>
+#include <linux/pti.h>
+
+#define DRIVERNAME "pti"
+#define PCINAME "pciPTI"
+#define TTYNAME "ttyPTI"
+#define CHARNAME "pti"
+#define PTITTY_MINOR_START 0
+#define PTITTY_MINOR_NUM 2
+#define MAX_APP_IDS 16 /* 128 channel ids / u8 bit size */
+#define MAX_OS_IDS 16 /* 128 channel ids / u8 bit size */
+#define MAX_MODEM_IDS 16 /* 128 channel ids / u8 bit size */
+#define MODEM_BASE_ID 71 /* modem master ID address */
+#define CONTROL_ID 72 /* control master ID address */
+#define CONSOLE_ID 73 /* console master ID address */
+#define OS_BASE_ID 74 /* base OS master ID address */
+#define APP_BASE_ID 80 /* base App master ID address */
+#define CONTROL_FRAME_LEN 32 /* PTI control frame maximum size */
+#define USER_COPY_SIZE 8192 /* 8Kb buffer for user space copy */
+#define APERTURE_14 0x3800000 /* offset to first OS write addr */
+#define APERTURE_LEN 0x400000 /* address length */
+
+struct pti_tty {
+ struct pti_masterchannel *mc;
+};
+
+struct pti_dev {
+ struct tty_port port;
+ unsigned long pti_addr;
+ unsigned long aperture_base;
+ void __iomem *pti_ioaddr;
+ u8 ia_app[MAX_APP_IDS];
+ u8 ia_os[MAX_OS_IDS];
+ u8 ia_modem[MAX_MODEM_IDS];
+};
+
+/*
+ * This protects access to ia_app, ia_os, and ia_modem,
+ * which keeps track of channels allocated in
+ * an aperture write id.
+ */
+static DEFINE_MUTEX(alloclock);
+
+static struct pci_device_id pci_ids[] __devinitconst = {
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x82B)},
+ {0}
+};
+
+static struct tty_driver *pti_tty_driver;
+static struct pti_dev *drv_data;
+
+static unsigned int pti_console_channel;
+static unsigned int pti_control_channel;
+
+/**
+ * pti_write_to_aperture()- The private write function to PTI HW.
+ *
+ * @mc: The 'aperture'. It's part of a write address that holds
+ * a master and channel ID.
+ * @buf: Data being written to the HW that will ultimately be seen
+ * in a debugging tool (Fido, Lauterbach).
+ * @len: Size of buffer.
+ *
+ * Since each aperture is specified by a unique
+ * master/channel ID, no two processes will be writing
+ * to the same aperture at the same time so no lock is required. The
+ * PTI-Output agent will send these out in the order that they arrived, and
+ * thus, it will intermix these messages. The debug tool can then later
+ * regroup the appropriate message segments together reconstituting each
+ * message.
+ */
+static void pti_write_to_aperture(struct pti_masterchannel *mc,
+ u8 *buf,
+ int len)
+{
+ int dwordcnt;
+ int final;
+ int i;
+ u32 ptiword;
+ u32 __iomem *aperture;
+ u8 *p = buf;
+
+ /*
+ * calculate the aperture offset from the base using the master and
+ * channel id's.
+ */
+ aperture = drv_data->pti_ioaddr + (mc->master << 15)
+ + (mc->channel << 8);
+
+ dwordcnt = len >> 2;
+ final = len - (dwordcnt << 2); /* final = trailing bytes */
+ if (final == 0 && dwordcnt != 0) { /* always need a final dword */
+ final += 4;
+ dwordcnt--;
+ }
+
+ for (i = 0; i < dwordcnt; i++) {
+ ptiword = be32_to_cpu(*(u32 *)p);
+ p += 4;
+ iowrite32(ptiword, aperture);
+ }
+
+ aperture += PTI_LASTDWORD_DTS; /* adding DTS signals that is EOM */
+
+ ptiword = 0;
+ for (i = 0; i < final; i++)
+ ptiword |= *p++ << (24-(8*i));
+
+ iowrite32(ptiword, aperture);
+ return;
+}
+
+/**
+ * pti_control_frame_built_and_sent()- control frame build and send function.
+ *
+ * @mc: The master / channel structure on which the function
+ * built a control frame.
+ *
+ * To be able to post process the PTI contents on host side, a control frame
+ * is added before sending any PTI content. So the host side knows on
+ * each PTI frame the name of the thread using a dedicated master / channel.
+ * The thread name is retrieved from the 'current' global variable.
+ * This function builds this frame and sends it to a master ID CONTROL_ID.
+ * The overhead is only 32 bytes since the driver only writes to HW
+ * in 32 byte chunks.
+ */
+
+static void pti_control_frame_built_and_sent(struct pti_masterchannel *mc)
+{
+ struct pti_masterchannel mccontrol = {.master = CONTROL_ID,
+ .channel = 0};
+ const char *control_format = "%3d %3d %s";
+ u8 control_frame[CONTROL_FRAME_LEN];
+
+ /*
+ * Since we access the comm member in current's task_struct,
+ * we only need to be as large as what 'comm' in that
+ * structure is.
+ */
+ char comm[TASK_COMM_LEN];
+
+ if (!in_interrupt())
+ get_task_comm(comm, current);
+ else
+ strncpy(comm, "Interrupt", TASK_COMM_LEN);
+
+ /* Absolutely ensure our buffer is zero terminated. */
+ comm[TASK_COMM_LEN-1] = 0;
+
+ mccontrol.channel = pti_control_channel;
+ pti_control_channel = (pti_control_channel + 1) & 0x7f;
+
+ snprintf(control_frame, CONTROL_FRAME_LEN, control_format, mc->master,
+ mc->channel, comm);
+ pti_write_to_aperture(&mccontrol, control_frame, strlen(control_frame));
+}
+
+/**
+ * pti_write_full_frame_to_aperture()- high level function to
+ * write to PTI.
+ *
+ * @mc: The 'aperture'. It's part of a write address that holds
+ * a master and channel ID.
+ * @buf: Data being written to the HW that will ultimately be seen
+ * in a debugging tool (Fido, Lauterbach).
+ * @len: Size of buffer.
+ *
+ * All threads sending data (either console, user space application, ...)
+ * are calling the high level function to write to PTI meaning that it is
+ * possible to add a control frame before sending the content.
+ */
+static void pti_write_full_frame_to_aperture(struct pti_masterchannel *mc,
+ const unsigned char *buf,
+ int len)
+{
+ pti_control_frame_built_and_sent(mc);
+ pti_write_to_aperture(mc, (u8 *)buf, len);
+}
+
+/**
+ * get_id()- Allocate a master and channel ID.
+ *
+ * @id_array: an array of bits representing what channel
+ * id's are allocated for writing.
+ * @max_ids: The max amount of available write IDs to use.
+ * @base_id: The starting SW channel ID, based on the Intel
+ * PTI arch.
+ *
+ * Returns:
+ * pti_masterchannel struct with master, channel ID address
+ * 0 for error
+ *
+ * Each bit in the arrays ia_app and ia_os correspond to a master and
+ * channel id. The bit is one if the id is taken and 0 if free. For
+ * every master there are 128 channel id's.
+ */
+static struct pti_masterchannel *get_id(u8 *id_array, int max_ids, int base_id)
+{
+ struct pti_masterchannel *mc;
+ int i, j, mask;
+
+ mc = kmalloc(sizeof(struct pti_masterchannel), GFP_KERNEL);
+ if (mc == NULL)
+ return NULL;
+
+ /* look for a byte with a free bit */
+ for (i = 0; i < max_ids; i++)
+ if (id_array[i] != 0xff)
+ break;
+ if (i == max_ids) {
+ kfree(mc);
+ return NULL;
+ }
+ /* find the bit in the 128 possible channel opportunities */
+ mask = 0x80;
+ for (j = 0; j < 8; j++) {
+ if ((id_array[i] & mask) == 0)
+ break;
+ mask >>= 1;
+ }
+
+ /* grab it */
+ id_array[i] |= mask;
+ mc->master = base_id;
+ mc->channel = ((i & 0xf)<<3) + j;
+ /* write new master Id / channel Id allocation to channel control */
+ pti_control_frame_built_and_sent(mc);
+ return mc;
+}
+
+/*
+ * The following three functions:
+ * pti_request_mastercahannel(), mipi_release_masterchannel()
+ * and pti_writedata() are an API for other kernel drivers to
+ * access PTI.
+ */
+
+/**
+ * pti_request_masterchannel()- Kernel API function used to allocate
+ * a master, channel ID address
+ * to write to PTI HW.
+ *
+ * @type: 0- request Application master, channel aperture ID write address.
+ * 1- request OS master, channel aperture ID write
+ * address.
+ * 2- request Modem master, channel aperture ID
+ * write address.
+ * Other values, error.
+ *
+ * Returns:
+ * pti_masterchannel struct
+ * 0 for error
+ */
+struct pti_masterchannel *pti_request_masterchannel(u8 type)
+{
+ struct pti_masterchannel *mc;
+
+ mutex_lock(&alloclock);
+
+ switch (type) {
+
+ case 0:
+ mc = get_id(drv_data->ia_app, MAX_APP_IDS, APP_BASE_ID);
+ break;
+
+ case 1:
+ mc = get_id(drv_data->ia_os, MAX_OS_IDS, OS_BASE_ID);
+ break;
+
+ case 2:
+ mc = get_id(drv_data->ia_modem, MAX_MODEM_IDS, MODEM_BASE_ID);
+ break;
+ default:
+ mc = NULL;
+ }
+
+ mutex_unlock(&alloclock);
+ return mc;
+}
+EXPORT_SYMBOL_GPL(pti_request_masterchannel);
+
+/**
+ * pti_release_masterchannel()- Kernel API function used to release
+ * a master, channel ID address
+ * used to write to PTI HW.
+ *
+ * @mc: master, channel apeture ID address to be released.
+ */
+void pti_release_masterchannel(struct pti_masterchannel *mc)
+{
+ u8 master, channel, i;
+
+ mutex_lock(&alloclock);
+
+ if (mc) {
+ master = mc->master;
+ channel = mc->channel;
+
+ if (master == APP_BASE_ID) {
+ i = channel >> 3;
+ drv_data->ia_app[i] &= ~(0x80>>(channel & 0x7));
+ } else if (master == OS_BASE_ID) {
+ i = channel >> 3;
+ drv_data->ia_os[i] &= ~(0x80>>(channel & 0x7));
+ } else {
+ i = channel >> 3;
+ drv_data->ia_modem[i] &= ~(0x80>>(channel & 0x7));
+ }
+
+ kfree(mc);
+ }
+
+ mutex_unlock(&alloclock);
+}
+EXPORT_SYMBOL_GPL(pti_release_masterchannel);
+
+/**
+ * pti_writedata()- Kernel API function used to write trace
+ * debugging data to PTI HW.
+ *
+ * @mc: Master, channel aperture ID address to write to.
+ * Null value will return with no write occurring.
+ * @buf: Trace debuging data to write to the PTI HW.
+ * Null value will return with no write occurring.
+ * @count: Size of buf. Value of 0 or a negative number will
+ * return with no write occuring.
+ */
+void pti_writedata(struct pti_masterchannel *mc, u8 *buf, int count)
+{
+ /*
+ * since this function is exported, this is treated like an
+ * API function, thus, all parameters should
+ * be checked for validity.
+ */
+ if ((mc != NULL) && (buf != NULL) && (count > 0))
+ pti_write_to_aperture(mc, buf, count);
+ return;
+}
+EXPORT_SYMBOL_GPL(pti_writedata);
+
+/**
+ * pti_pci_remove()- Driver exit method to remove PTI from
+ * PCI bus.
+ * @pdev: variable containing pci info of PTI.
+ */
+static void __devexit pti_pci_remove(struct pci_dev *pdev)
+{
+ struct pti_dev *drv_data;
+
+ drv_data = pci_get_drvdata(pdev);
+ if (drv_data != NULL) {
+ pci_iounmap(pdev, drv_data->pti_ioaddr);
+ pci_set_drvdata(pdev, NULL);
+ kfree(drv_data);
+ pci_release_region(pdev, 1);
+ pci_disable_device(pdev);
+ }
+}
+
+/*
+ * for the tty_driver_*() basic function descriptions, see tty_driver.h.
+ * Specific header comments made for PTI-related specifics.
+ */
+
+/**
+ * pti_tty_driver_open()- Open an Application master, channel aperture
+ * ID to the PTI device via tty device.
+ *
+ * @tty: tty interface.
+ * @filp: filp interface pased to tty_port_open() call.
+ *
+ * Returns:
+ * int, 0 for success
+ * otherwise, fail value
+ *
+ * The main purpose of using the tty device interface is for
+ * each tty port to have a unique PTI write aperture. In an
+ * example use case, ttyPTI0 gets syslogd and an APP aperture
+ * ID and ttyPTI1 is where the n_tracesink ldisc hooks to route
+ * modem messages into PTI. Modem trace data does not have to
+ * go to ttyPTI1, but ttyPTI0 and ttyPTI1 do need to be distinct
+ * master IDs. These messages go through the PTI HW and out of
+ * the handheld platform and to the Fido/Lauterbach device.
+ */
+static int pti_tty_driver_open(struct tty_struct *tty, struct file *filp)
+{
+ /*
+ * we actually want to allocate a new channel per open, per
+ * system arch. HW gives more than plenty channels for a single
+ * system task to have its own channel to write trace data. This
+ * also removes a locking requirement for the actual write
+ * procedure.
+ */
+ return tty_port_open(&drv_data->port, tty, filp);
+}
+
+/**
+ * pti_tty_driver_close()- close tty device and release Application
+ * master, channel aperture ID to the PTI device via tty device.
+ *
+ * @tty: tty interface.
+ * @filp: filp interface pased to tty_port_close() call.
+ *
+ * The main purpose of using the tty device interface is to route
+ * syslog daemon messages to the PTI HW and out of the handheld platform
+ * and to the Fido/Lauterbach device.
+ */
+static void pti_tty_driver_close(struct tty_struct *tty, struct file *filp)
+{
+ tty_port_close(&drv_data->port, tty, filp);
+}
+
+/**
+ * pti_tty_intstall()- Used to set up specific master-channels
+ * to tty ports for organizational purposes when
+ * tracing viewed from debuging tools.
+ *
+ * @driver: tty driver information.
+ * @tty: tty struct containing pti information.
+ *
+ * Returns:
+ * 0 for success
+ * otherwise, error
+ */
+static int pti_tty_install(struct tty_driver *driver, struct tty_struct *tty)
+{
+ int idx = tty->index;
+ struct pti_tty *pti_tty_data;
+ int ret = tty_init_termios(tty);
+
+ if (ret == 0) {
+ tty_driver_kref_get(driver);
+ tty->count++;
+ driver->ttys[idx] = tty;
+
+ pti_tty_data = kmalloc(sizeof(struct pti_tty), GFP_KERNEL);
+ if (pti_tty_data == NULL)
+ return -ENOMEM;
+
+ if (idx == PTITTY_MINOR_START)
+ pti_tty_data->mc = pti_request_masterchannel(0);
+ else
+ pti_tty_data->mc = pti_request_masterchannel(2);
+
+ if (pti_tty_data->mc == NULL)
+ return -ENXIO;
+ tty->driver_data = pti_tty_data;
+ }
+
+ return ret;
+}
+
+/**
+ * pti_tty_cleanup()- Used to de-allocate master-channel resources
+ * tied to tty's of this driver.
+ *
+ * @tty: tty struct containing pti information.
+ */
+static void pti_tty_cleanup(struct tty_struct *tty)
+{
+ struct pti_tty *pti_tty_data = tty->driver_data;
+ if (pti_tty_data == NULL)
+ return;
+ pti_release_masterchannel(pti_tty_data->mc);
+ kfree(tty->driver_data);
+ tty->driver_data = NULL;
+}
+
+/**
+ * pti_tty_driver_write()- Write trace debugging data through the char
+ * interface to the PTI HW. Part of the misc device implementation.
+ *
+ * @filp: Contains private data which is used to obtain
+ * master, channel write ID.
+ * @data: trace data to be written.
+ * @len: # of byte to write.
+ *
+ * Returns:
+ * int, # of bytes written
+ * otherwise, error
+ */
+static int pti_tty_driver_write(struct tty_struct *tty,
+ const unsigned char *buf, int len)
+{
+ struct pti_tty *pti_tty_data = tty->driver_data;
+ if ((pti_tty_data != NULL) && (pti_tty_data->mc != NULL)) {
+ pti_write_to_aperture(pti_tty_data->mc, (u8 *)buf, len);
+ return len;
+ }
+ /*
+ * we can't write to the pti hardware if the private driver_data
+ * and the mc address is not there.
+ */
+ else
+ return -EFAULT;
+}
+
+/**
+ * pti_tty_write_room()- Always returns 2048.
+ *
+ * @tty: contains tty info of the pti driver.
+ */
+static int pti_tty_write_room(struct tty_struct *tty)
+{
+ return 2048;
+}
+
+/**
+ * pti_char_open()- Open an Application master, channel aperture
+ * ID to the PTI device. Part of the misc device implementation.
+ *
+ * @inode: not used.
+ * @filp: Output- will have a masterchannel struct set containing
+ * the allocated application PTI aperture write address.
+ *
+ * Returns:
+ * int, 0 for success
+ * otherwise, a fail value
+ */
+static int pti_char_open(struct inode *inode, struct file *filp)
+{
+ struct pti_masterchannel *mc;
+
+ /*
+ * We really do want to fail immediately if
+ * pti_request_masterchannel() fails,
+ * before assigning the value to filp->private_data.
+ * Slightly easier to debug if this driver needs debugging.
+ */
+ mc = pti_request_masterchannel(0);
+ if (mc == NULL)
+ return -ENOMEM;
+ filp->private_data = mc;
+ return 0;
+}
+
+/**
+ * pti_char_release()- Close a char channel to the PTI device. Part
+ * of the misc device implementation.
+ *
+ * @inode: Not used in this implementaiton.
+ * @filp: Contains private_data that contains the master, channel
+ * ID to be released by the PTI device.
+ *
+ * Returns:
+ * always 0
+ */
+static int pti_char_release(struct inode *inode, struct file *filp)
+{
+ pti_release_masterchannel(filp->private_data);
+ kfree(filp->private_data);
+ return 0;
+}
+
+/**
+ * pti_char_write()- Write trace debugging data through the char
+ * interface to the PTI HW. Part of the misc device implementation.
+ *
+ * @filp: Contains private data which is used to obtain
+ * master, channel write ID.
+ * @data: trace data to be written.
+ * @len: # of byte to write.
+ * @ppose: Not used in this function implementation.
+ *
+ * Returns:
+ * int, # of bytes written
+ * otherwise, error value
+ *
+ * Notes: From side discussions with Alan Cox and experimenting
+ * with PTI debug HW like Nokia's Fido box and Lauterbach
+ * devices, 8192 byte write buffer used by USER_COPY_SIZE was
+ * deemed an appropriate size for this type of usage with
+ * debugging HW.
+ */
+static ssize_t pti_char_write(struct file *filp, const char __user *data,
+ size_t len, loff_t *ppose)
+{
+ struct pti_masterchannel *mc;
+ void *kbuf;
+ const char __user *tmp;
+ size_t size = USER_COPY_SIZE;
+ size_t n = 0;
+
+ tmp = data;
+ mc = filp->private_data;
+
+ kbuf = kmalloc(size, GFP_KERNEL);
+ if (kbuf == NULL) {
+ pr_err("%s(%d): buf allocation failed\n",
+ __func__, __LINE__);
+ return -ENOMEM;
+ }
+
+ do {
+ if (len - n > USER_COPY_SIZE)
+ size = USER_COPY_SIZE;
+ else
+ size = len - n;
+
+ if (copy_from_user(kbuf, tmp, size)) {
+ kfree(kbuf);
+ return n ? n : -EFAULT;
+ }
+
+ pti_write_to_aperture(mc, kbuf, size);
+ n += size;
+ tmp += size;
+
+ } while (len > n);
+
+ kfree(kbuf);
+ return len;
+}
+
+static const struct tty_operations pti_tty_driver_ops = {
+ .open = pti_tty_driver_open,
+ .close = pti_tty_driver_close,
+ .write = pti_tty_driver_write,
+ .write_room = pti_tty_write_room,
+ .install = pti_tty_install,
+ .cleanup = pti_tty_cleanup
+};
+
+static const struct file_operations pti_char_driver_ops = {
+ .owner = THIS_MODULE,
+ .write = pti_char_write,
+ .open = pti_char_open,
+ .release = pti_char_release,
+};
+
+static struct miscdevice pti_char_driver = {
+ .minor = MISC_DYNAMIC_MINOR,
+ .name = CHARNAME,
+ .fops = &pti_char_driver_ops
+};
+
+/**
+ * pti_console_write()- Write to the console that has been acquired.
+ *
+ * @c: Not used in this implementaiton.
+ * @buf: Data to be written.
+ * @len: Length of buf.
+ */
+static void pti_console_write(struct console *c, const char *buf, unsigned len)
+{
+ static struct pti_masterchannel mc = {.master = CONSOLE_ID,
+ .channel = 0};
+
+ mc.channel = pti_console_channel;
+ pti_console_channel = (pti_console_channel + 1) & 0x7f;
+
+ pti_write_full_frame_to_aperture(&mc, buf, len);
+}
+
+/**
+ * pti_console_device()- Return the driver tty structure and set the
+ * associated index implementation.
+ *
+ * @c: Console device of the driver.
+ * @index: index associated with c.
+ *
+ * Returns:
+ * always value of pti_tty_driver structure when this function
+ * is called.
+ */
+static struct tty_driver *pti_console_device(struct console *c, int *index)
+{
+ *index = c->index;
+ return pti_tty_driver;
+}
+
+/**
+ * pti_console_setup()- Initialize console variables used by the driver.
+ *
+ * @c: Not used.
+ * @opts: Not used.
+ *
+ * Returns:
+ * always 0.
+ */
+static int pti_console_setup(struct console *c, char *opts)
+{
+ pti_console_channel = 0;
+ pti_control_channel = 0;
+ return 0;
+}
+
+/*
+ * pti_console struct, used to capture OS printk()'s and shift
+ * out to the PTI device for debugging. This cannot be
+ * enabled upon boot because of the possibility of eating
+ * any serial console printk's (race condition discovered).
+ * The console should be enabled upon when the tty port is
+ * used for the first time. Since the primary purpose for
+ * the tty port is to hook up syslog to it, the tty port
+ * will be open for a really long time.
+ */
+static struct console pti_console = {
+ .name = TTYNAME,
+ .write = pti_console_write,
+ .device = pti_console_device,
+ .setup = pti_console_setup,
+ .flags = CON_PRINTBUFFER,
+ .index = 0,
+};
+
+/**
+ * pti_port_activate()- Used to start/initialize any items upon
+ * first opening of tty_port().
+ *
+ * @port- The tty port number of the PTI device.
+ * @tty- The tty struct associated with this device.
+ *
+ * Returns:
+ * always returns 0
+ *
+ * Notes: The primary purpose of the PTI tty port 0 is to hook
+ * the syslog daemon to it; thus this port will be open for a
+ * very long time.
+ */
+static int pti_port_activate(struct tty_port *port, struct tty_struct *tty)
+{
+ if (port->tty->index == PTITTY_MINOR_START)
+ console_start(&pti_console);
+ return 0;
+}
+
+/**
+ * pti_port_shutdown()- Used to stop/shutdown any items upon the
+ * last tty port close.
+ *
+ * @port- The tty port number of the PTI device.
+ *
+ * Notes: The primary purpose of the PTI tty port 0 is to hook
+ * the syslog daemon to it; thus this port will be open for a
+ * very long time.
+ */
+static void pti_port_shutdown(struct tty_port *port)
+{
+ if (port->tty->index == PTITTY_MINOR_START)
+ console_stop(&pti_console);
+}
+
+static const struct tty_port_operations tty_port_ops = {
+ .activate = pti_port_activate,
+ .shutdown = pti_port_shutdown,
+};
+
+/*
+ * Note the _probe() call sets everything up and ties the char and tty
+ * to successfully detecting the PTI device on the pci bus.
+ */
+
+/**
+ * pti_pci_probe()- Used to detect pti on the pci bus and set
+ * things up in the driver.
+ *
+ * @pdev- pci_dev struct values for pti.
+ * @ent- pci_device_id struct for pti driver.
+ *
+ * Returns:
+ * 0 for success
+ * otherwise, error
+ */
+static int __devinit pti_pci_probe(struct pci_dev *pdev,
+ const struct pci_device_id *ent)
+{
+ int retval = -EINVAL;
+ int pci_bar = 1;
+
+ dev_dbg(&pdev->dev, "%s %s(%d): PTI PCI ID %04x:%04x\n", __FILE__,
+ __func__, __LINE__, pdev->vendor, pdev->device);
+
+ retval = misc_register(&pti_char_driver);
+ if (retval) {
+ pr_err("%s(%d): CHAR registration failed of pti driver\n",
+ __func__, __LINE__);
+ pr_err("%s(%d): Error value returned: %d\n",
+ __func__, __LINE__, retval);
+ return retval;
+ }
+
+ retval = pci_enable_device(pdev);
+ if (retval != 0) {
+ dev_err(&pdev->dev,
+ "%s: pci_enable_device() returned error %d\n",
+ __func__, retval);
+ return retval;
+ }
+
+ drv_data = kzalloc(sizeof(*drv_data), GFP_KERNEL);
+
+ if (drv_data == NULL) {
+ retval = -ENOMEM;
+ dev_err(&pdev->dev,
+ "%s(%d): kmalloc() returned NULL memory.\n",
+ __func__, __LINE__);
+ return retval;
+ }
+ drv_data->pti_addr = pci_resource_start(pdev, pci_bar);
+
+ retval = pci_request_region(pdev, pci_bar, dev_name(&pdev->dev));
+ if (retval != 0) {
+ dev_err(&pdev->dev,
+ "%s(%d): pci_request_region() returned error %d\n",
+ __func__, __LINE__, retval);
+ kfree(drv_data);
+ return retval;
+ }
+ drv_data->aperture_base = drv_data->pti_addr+APERTURE_14;
+ drv_data->pti_ioaddr =
+ ioremap_nocache((u32)drv_data->aperture_base,
+ APERTURE_LEN);
+ if (!drv_data->pti_ioaddr) {
+ pci_release_region(pdev, pci_bar);
+ retval = -ENOMEM;
+ kfree(drv_data);
+ return retval;
+ }
+
+ pci_set_drvdata(pdev, drv_data);
+
+ tty_port_init(&drv_data->port);
+ drv_data->port.ops = &tty_port_ops;
+
+ tty_register_device(pti_tty_driver, 0, &pdev->dev);
+ tty_register_device(pti_tty_driver, 1, &pdev->dev);
+
+ register_console(&pti_console);
+
+ return retval;
+}
+
+static struct pci_driver pti_pci_driver = {
+ .name = PCINAME,
+ .id_table = pci_ids,
+ .probe = pti_pci_probe,
+ .remove = pti_pci_remove,
+};
+
+/**
+ *
+ * pti_init()- Overall entry/init call to the pti driver.
+ * It starts the registration process with the kernel.
+ *
+ * Returns:
+ * int __init, 0 for success
+ * otherwise value is an error
+ *
+ */
+static int __init pti_init(void)
+{
+ int retval = -EINVAL;
+
+ /* First register module as tty device */
+
+ pti_tty_driver = alloc_tty_driver(1);
+ if (pti_tty_driver == NULL) {
+ pr_err("%s(%d): Memory allocation failed for ptiTTY driver\n",
+ __func__, __LINE__);
+ return -ENOMEM;
+ }
+
+ pti_tty_driver->owner = THIS_MODULE;
+ pti_tty_driver->magic = TTY_DRIVER_MAGIC;
+ pti_tty_driver->driver_name = DRIVERNAME;
+ pti_tty_driver->name = TTYNAME;
+ pti_tty_driver->major = 0;
+ pti_tty_driver->minor_start = PTITTY_MINOR_START;
+ pti_tty_driver->minor_num = PTITTY_MINOR_NUM;
+ pti_tty_driver->num = PTITTY_MINOR_NUM;
+ pti_tty_driver->type = TTY_DRIVER_TYPE_SYSTEM;
+ pti_tty_driver->subtype = SYSTEM_TYPE_SYSCONS;
+ pti_tty_driver->flags = TTY_DRIVER_REAL_RAW |
+ TTY_DRIVER_DYNAMIC_DEV;
+ pti_tty_driver->init_termios = tty_std_termios;
+
+ tty_set_operations(pti_tty_driver, &pti_tty_driver_ops);
+
+ retval = tty_register_driver(pti_tty_driver);
+ if (retval) {
+ pr_err("%s(%d): TTY registration failed of pti driver\n",
+ __func__, __LINE__);
+ pr_err("%s(%d): Error value returned: %d\n",
+ __func__, __LINE__, retval);
+
+ pti_tty_driver = NULL;
+ return retval;
+ }
+
+ retval = pci_register_driver(&pti_pci_driver);
+
+ if (retval) {
+ pr_err("%s(%d): PCI registration failed of pti driver\n",
+ __func__, __LINE__);
+ pr_err("%s(%d): Error value returned: %d\n",
+ __func__, __LINE__, retval);
+
+ tty_unregister_driver(pti_tty_driver);
+ pr_err("%s(%d): Unregistering TTY part of pti driver\n",
+ __func__, __LINE__);
+ pti_tty_driver = NULL;
+ return retval;
+ }
+
+ return retval;
+}
+
+/**
+ * pti_exit()- Unregisters this module as a tty and pci driver.
+ */
+static void __exit pti_exit(void)
+{
+ int retval;
+
+ tty_unregister_device(pti_tty_driver, 0);
+ tty_unregister_device(pti_tty_driver, 1);
+
+ retval = tty_unregister_driver(pti_tty_driver);
+ if (retval) {
+ pr_err("%s(%d): TTY unregistration failed of pti driver\n",
+ __func__, __LINE__);
+ pr_err("%s(%d): Error value returned: %d\n",
+ __func__, __LINE__, retval);
+ }
+
+ pci_unregister_driver(&pti_pci_driver);
+
+ retval = misc_deregister(&pti_char_driver);
+ if (retval) {
+ pr_err("%s(%d): CHAR unregistration failed of pti driver\n",
+ __func__, __LINE__);
+ pr_err("%s(%d): Error value returned: %d\n",
+ __func__, __LINE__, retval);
+ }
+
+ unregister_console(&pti_console);
+ return;
+}
+
+module_init(pti_init);
+module_exit(pti_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Ken Mills, Jay Freyensee");
+MODULE_DESCRIPTION("PTI Driver");
+
diff --git a/drivers/misc/ti-st/st_core.c b/drivers/misc/ti-st/st_core.c
index f91f82e..1a05fe0 100644
--- a/drivers/misc/ti-st/st_core.c
+++ b/drivers/misc/ti-st/st_core.c
@@ -747,8 +747,8 @@
pr_debug("%s: done ", __func__);
}
-static void st_tty_receive(struct tty_struct *tty, const unsigned char *data,
- char *tty_flags, int count)
+static unsigned int st_tty_receive(struct tty_struct *tty,
+ const unsigned char *data, char *tty_flags, int count)
{
#ifdef VERBOSE
print_hex_dump(KERN_DEBUG, ">in>", DUMP_PREFIX_NONE,
@@ -761,6 +761,8 @@
*/
st_recv(tty->disc_data, data, count);
pr_debug("done %s", __func__);
+
+ return count;
}
/* wake-up function called in from the TTY layer
diff --git a/drivers/mmc/card/block.c b/drivers/mmc/card/block.c
index 61d233a..71da564 100644
--- a/drivers/mmc/card/block.c
+++ b/drivers/mmc/card/block.c
@@ -31,7 +31,11 @@
#include <linux/mutex.h>
#include <linux/scatterlist.h>
#include <linux/string_helpers.h>
+#include <linux/delay.h>
+#include <linux/capability.h>
+#include <linux/compat.h>
+#include <linux/mmc/ioctl.h>
#include <linux/mmc/card.h>
#include <linux/mmc/host.h>
#include <linux/mmc/mmc.h>
@@ -48,6 +52,13 @@
#endif
#define MODULE_PARAM_PREFIX "mmcblk."
+#define INAND_CMD38_ARG_EXT_CSD 113
+#define INAND_CMD38_ARG_ERASE 0x00
+#define INAND_CMD38_ARG_TRIM 0x01
+#define INAND_CMD38_ARG_SECERASE 0x80
+#define INAND_CMD38_ARG_SECTRIM1 0x81
+#define INAND_CMD38_ARG_SECTRIM2 0x88
+
static DEFINE_MUTEX(block_mutex);
/*
@@ -64,6 +75,7 @@
/* 256 minors, so at most 256 separate devices */
static DECLARE_BITMAP(dev_use, 256);
+static DECLARE_BITMAP(name_use, 256);
/*
* There is one mmc_blk_data per slot.
@@ -72,9 +84,24 @@
spinlock_t lock;
struct gendisk *disk;
struct mmc_queue queue;
+ struct list_head part;
+
+ unsigned int flags;
+#define MMC_BLK_CMD23 (1 << 0) /* Can do SET_BLOCK_COUNT for multiblock */
+#define MMC_BLK_REL_WR (1 << 1) /* MMC Reliable write support */
unsigned int usage;
unsigned int read_only;
+ unsigned int part_type;
+ unsigned int name_idx;
+
+ /*
+ * Only set in main mmc_blk_data associated
+ * with mmc_card with mmc_set_drvdata, and keeps
+ * track of the current selected device partition.
+ */
+ unsigned int part_curr;
+ struct device_attribute force_ro;
};
static DEFINE_MUTEX(open_lock);
@@ -97,17 +124,22 @@
return md;
}
+static inline int mmc_get_devidx(struct gendisk *disk)
+{
+ int devmaj = MAJOR(disk_devt(disk));
+ int devidx = MINOR(disk_devt(disk)) / perdev_minors;
+
+ if (!devmaj)
+ devidx = disk->first_minor / perdev_minors;
+ return devidx;
+}
+
static void mmc_blk_put(struct mmc_blk_data *md)
{
mutex_lock(&open_lock);
md->usage--;
if (md->usage == 0) {
- int devmaj = MAJOR(disk_devt(md->disk));
- int devidx = MINOR(disk_devt(md->disk)) / perdev_minors;
-
- if (!devmaj)
- devidx = md->disk->first_minor / perdev_minors;
-
+ int devidx = mmc_get_devidx(md->disk);
blk_cleanup_queue(md->queue.queue);
__clear_bit(devidx, dev_use);
@@ -118,6 +150,38 @@
mutex_unlock(&open_lock);
}
+static ssize_t force_ro_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ int ret;
+ struct mmc_blk_data *md = mmc_blk_get(dev_to_disk(dev));
+
+ ret = snprintf(buf, PAGE_SIZE, "%d",
+ get_disk_ro(dev_to_disk(dev)) ^
+ md->read_only);
+ mmc_blk_put(md);
+ return ret;
+}
+
+static ssize_t force_ro_store(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ int ret;
+ char *end;
+ struct mmc_blk_data *md = mmc_blk_get(dev_to_disk(dev));
+ unsigned long set = simple_strtoul(buf, &end, 0);
+ if (end == buf) {
+ ret = -EINVAL;
+ goto out;
+ }
+
+ set_disk_ro(dev_to_disk(dev), set || md->read_only);
+ ret = count;
+out:
+ mmc_blk_put(md);
+ return ret;
+}
+
static int mmc_blk_open(struct block_device *bdev, fmode_t mode)
{
struct mmc_blk_data *md = mmc_blk_get(bdev->bd_disk);
@@ -158,35 +222,255 @@
return 0;
}
+struct mmc_blk_ioc_data {
+ struct mmc_ioc_cmd ic;
+ unsigned char *buf;
+ u64 buf_bytes;
+};
+
+static struct mmc_blk_ioc_data *mmc_blk_ioctl_copy_from_user(
+ struct mmc_ioc_cmd __user *user)
+{
+ struct mmc_blk_ioc_data *idata;
+ int err;
+
+ idata = kzalloc(sizeof(*idata), GFP_KERNEL);
+ if (!idata) {
+ err = -ENOMEM;
+ goto out;
+ }
+
+ if (copy_from_user(&idata->ic, user, sizeof(idata->ic))) {
+ err = -EFAULT;
+ goto idata_err;
+ }
+
+ idata->buf_bytes = (u64) idata->ic.blksz * idata->ic.blocks;
+ if (idata->buf_bytes > MMC_IOC_MAX_BYTES) {
+ err = -EOVERFLOW;
+ goto idata_err;
+ }
+
+ idata->buf = kzalloc(idata->buf_bytes, GFP_KERNEL);
+ if (!idata->buf) {
+ err = -ENOMEM;
+ goto idata_err;
+ }
+
+ if (copy_from_user(idata->buf, (void __user *)(unsigned long)
+ idata->ic.data_ptr, idata->buf_bytes)) {
+ err = -EFAULT;
+ goto copy_err;
+ }
+
+ return idata;
+
+copy_err:
+ kfree(idata->buf);
+idata_err:
+ kfree(idata);
+out:
+ return ERR_PTR(err);
+}
+
+static int mmc_blk_ioctl_cmd(struct block_device *bdev,
+ struct mmc_ioc_cmd __user *ic_ptr)
+{
+ struct mmc_blk_ioc_data *idata;
+ struct mmc_blk_data *md;
+ struct mmc_card *card;
+ struct mmc_command cmd = {0};
+ struct mmc_data data = {0};
+ struct mmc_request mrq = {0};
+ struct scatterlist sg;
+ int err;
+
+ /*
+ * The caller must have CAP_SYS_RAWIO, and must be calling this on the
+ * whole block device, not on a partition. This prevents overspray
+ * between sibling partitions.
+ */
+ if ((!capable(CAP_SYS_RAWIO)) || (bdev != bdev->bd_contains))
+ return -EPERM;
+
+ idata = mmc_blk_ioctl_copy_from_user(ic_ptr);
+ if (IS_ERR(idata))
+ return PTR_ERR(idata);
+
+ cmd.opcode = idata->ic.opcode;
+ cmd.arg = idata->ic.arg;
+ cmd.flags = idata->ic.flags;
+
+ data.sg = &sg;
+ data.sg_len = 1;
+ data.blksz = idata->ic.blksz;
+ data.blocks = idata->ic.blocks;
+
+ sg_init_one(data.sg, idata->buf, idata->buf_bytes);
+
+ if (idata->ic.write_flag)
+ data.flags = MMC_DATA_WRITE;
+ else
+ data.flags = MMC_DATA_READ;
+
+ mrq.cmd = &cmd;
+ mrq.data = &data;
+
+ md = mmc_blk_get(bdev->bd_disk);
+ if (!md) {
+ err = -EINVAL;
+ goto cmd_done;
+ }
+
+ card = md->queue.card;
+ if (IS_ERR(card)) {
+ err = PTR_ERR(card);
+ goto cmd_done;
+ }
+
+ mmc_claim_host(card->host);
+
+ if (idata->ic.is_acmd) {
+ err = mmc_app_cmd(card->host, card);
+ if (err)
+ goto cmd_rel_host;
+ }
+
+ /* data.flags must already be set before doing this. */
+ mmc_set_data_timeout(&data, card);
+ /* Allow overriding the timeout_ns for empirical tuning. */
+ if (idata->ic.data_timeout_ns)
+ data.timeout_ns = idata->ic.data_timeout_ns;
+
+ if ((cmd.flags & MMC_RSP_R1B) == MMC_RSP_R1B) {
+ /*
+ * Pretend this is a data transfer and rely on the host driver
+ * to compute timeout. When all host drivers support
+ * cmd.cmd_timeout for R1B, this can be changed to:
+ *
+ * mrq.data = NULL;
+ * cmd.cmd_timeout = idata->ic.cmd_timeout_ms;
+ */
+ data.timeout_ns = idata->ic.cmd_timeout_ms * 1000000;
+ }
+
+ mmc_wait_for_req(card->host, &mrq);
+
+ if (cmd.error) {
+ dev_err(mmc_dev(card->host), "%s: cmd error %d\n",
+ __func__, cmd.error);
+ err = cmd.error;
+ goto cmd_rel_host;
+ }
+ if (data.error) {
+ dev_err(mmc_dev(card->host), "%s: data error %d\n",
+ __func__, data.error);
+ err = data.error;
+ goto cmd_rel_host;
+ }
+
+ /*
+ * According to the SD specs, some commands require a delay after
+ * issuing the command.
+ */
+ if (idata->ic.postsleep_min_us)
+ usleep_range(idata->ic.postsleep_min_us, idata->ic.postsleep_max_us);
+
+ if (copy_to_user(&(ic_ptr->response), cmd.resp, sizeof(cmd.resp))) {
+ err = -EFAULT;
+ goto cmd_rel_host;
+ }
+
+ if (!idata->ic.write_flag) {
+ if (copy_to_user((void __user *)(unsigned long) idata->ic.data_ptr,
+ idata->buf, idata->buf_bytes)) {
+ err = -EFAULT;
+ goto cmd_rel_host;
+ }
+ }
+
+cmd_rel_host:
+ mmc_release_host(card->host);
+
+cmd_done:
+ mmc_blk_put(md);
+ kfree(idata->buf);
+ kfree(idata);
+ return err;
+}
+
+static int mmc_blk_ioctl(struct block_device *bdev, fmode_t mode,
+ unsigned int cmd, unsigned long arg)
+{
+ int ret = -EINVAL;
+ if (cmd == MMC_IOC_CMD)
+ ret = mmc_blk_ioctl_cmd(bdev, (struct mmc_ioc_cmd __user *)arg);
+ return ret;
+}
+
+#ifdef CONFIG_COMPAT
+static int mmc_blk_compat_ioctl(struct block_device *bdev, fmode_t mode,
+ unsigned int cmd, unsigned long arg)
+{
+ return mmc_blk_ioctl(bdev, mode, cmd, (unsigned long) compat_ptr(arg));
+}
+#endif
+
static const struct block_device_operations mmc_bdops = {
.open = mmc_blk_open,
.release = mmc_blk_release,
.getgeo = mmc_blk_getgeo,
.owner = THIS_MODULE,
+ .ioctl = mmc_blk_ioctl,
+#ifdef CONFIG_COMPAT
+ .compat_ioctl = mmc_blk_compat_ioctl,
+#endif
};
struct mmc_blk_request {
struct mmc_request mrq;
+ struct mmc_command sbc;
struct mmc_command cmd;
struct mmc_command stop;
struct mmc_data data;
};
+static inline int mmc_blk_part_switch(struct mmc_card *card,
+ struct mmc_blk_data *md)
+{
+ int ret;
+ struct mmc_blk_data *main_md = mmc_get_drvdata(card);
+ if (main_md->part_curr == md->part_type)
+ return 0;
+
+ if (mmc_card_mmc(card)) {
+ card->ext_csd.part_config &= ~EXT_CSD_PART_CONFIG_ACC_MASK;
+ card->ext_csd.part_config |= md->part_type;
+
+ ret = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
+ EXT_CSD_PART_CONFIG, card->ext_csd.part_config,
+ card->ext_csd.part_time);
+ if (ret)
+ return ret;
+}
+
+ main_md->part_curr = md->part_type;
+ return 0;
+}
+
static u32 mmc_sd_num_wr_blocks(struct mmc_card *card)
{
int err;
u32 result;
__be32 *blocks;
- struct mmc_request mrq;
- struct mmc_command cmd;
- struct mmc_data data;
+ struct mmc_request mrq = {0};
+ struct mmc_command cmd = {0};
+ struct mmc_data data = {0};
unsigned int timeout_us;
struct scatterlist sg;
- memset(&cmd, 0, sizeof(struct mmc_command));
-
cmd.opcode = MMC_APP_CMD;
cmd.arg = card->rca << 16;
cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_R1 | MMC_CMD_AC;
@@ -203,8 +487,6 @@
cmd.arg = 0;
cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_R1 | MMC_CMD_ADTC;
- memset(&data, 0, sizeof(struct mmc_data));
-
data.timeout_ns = card->csd.tacc_ns * 100;
data.timeout_clks = card->csd.tacc_clks * 100;
@@ -223,8 +505,6 @@
data.sg = &sg;
data.sg_len = 1;
- memset(&mrq, 0, sizeof(struct mmc_request));
-
mrq.cmd = &cmd;
mrq.data = &data;
@@ -247,10 +527,9 @@
static u32 get_card_status(struct mmc_card *card, struct request *req)
{
- struct mmc_command cmd;
+ struct mmc_command cmd = {0};
int err;
- memset(&cmd, 0, sizeof(struct mmc_command));
cmd.opcode = MMC_SEND_STATUS;
if (!mmc_host_is_spi(card->host))
cmd.arg = card->rca << 16;
@@ -269,8 +548,6 @@
unsigned int from, nr, arg;
int err = 0;
- mmc_claim_host(card->host);
-
if (!mmc_can_erase(card)) {
err = -EOPNOTSUPP;
goto out;
@@ -284,14 +561,22 @@
else
arg = MMC_ERASE_ARG;
+ if (card->quirks & MMC_QUIRK_INAND_CMD38) {
+ err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
+ INAND_CMD38_ARG_EXT_CSD,
+ arg == MMC_TRIM_ARG ?
+ INAND_CMD38_ARG_TRIM :
+ INAND_CMD38_ARG_ERASE,
+ 0);
+ if (err)
+ goto out;
+ }
err = mmc_erase(card, from, nr, arg);
out:
spin_lock_irq(&md->lock);
__blk_end_request(req, err, blk_rq_bytes(req));
spin_unlock_irq(&md->lock);
- mmc_release_host(card->host);
-
return err ? 0 : 1;
}
@@ -303,8 +588,6 @@
unsigned int from, nr, arg;
int err = 0;
- mmc_claim_host(card->host);
-
if (!mmc_can_secure_erase_trim(card)) {
err = -EOPNOTSUPP;
goto out;
@@ -318,19 +601,74 @@
else
arg = MMC_SECURE_ERASE_ARG;
+ if (card->quirks & MMC_QUIRK_INAND_CMD38) {
+ err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
+ INAND_CMD38_ARG_EXT_CSD,
+ arg == MMC_SECURE_TRIM1_ARG ?
+ INAND_CMD38_ARG_SECTRIM1 :
+ INAND_CMD38_ARG_SECERASE,
+ 0);
+ if (err)
+ goto out;
+ }
err = mmc_erase(card, from, nr, arg);
- if (!err && arg == MMC_SECURE_TRIM1_ARG)
+ if (!err && arg == MMC_SECURE_TRIM1_ARG) {
+ if (card->quirks & MMC_QUIRK_INAND_CMD38) {
+ err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
+ INAND_CMD38_ARG_EXT_CSD,
+ INAND_CMD38_ARG_SECTRIM2,
+ 0);
+ if (err)
+ goto out;
+ }
err = mmc_erase(card, from, nr, MMC_SECURE_TRIM2_ARG);
+ }
out:
spin_lock_irq(&md->lock);
__blk_end_request(req, err, blk_rq_bytes(req));
spin_unlock_irq(&md->lock);
- mmc_release_host(card->host);
-
return err ? 0 : 1;
}
+static int mmc_blk_issue_flush(struct mmc_queue *mq, struct request *req)
+{
+ struct mmc_blk_data *md = mq->data;
+
+ /*
+ * No-op, only service this because we need REQ_FUA for reliable
+ * writes.
+ */
+ spin_lock_irq(&md->lock);
+ __blk_end_request_all(req, 0);
+ spin_unlock_irq(&md->lock);
+
+ return 1;
+}
+
+/*
+ * Reformat current write as a reliable write, supporting
+ * both legacy and the enhanced reliable write MMC cards.
+ * In each transfer we'll handle only as much as a single
+ * reliable write can handle, thus finish the request in
+ * partial completions.
+ */
+static inline void mmc_apply_rel_rw(struct mmc_blk_request *brq,
+ struct mmc_card *card,
+ struct request *req)
+{
+ if (!(card->ext_csd.rel_param & EXT_CSD_WR_REL_PARAM_EN)) {
+ /* Legacy mode imposes restrictions on transfers. */
+ if (!IS_ALIGNED(brq->cmd.arg, card->ext_csd.rel_sectors))
+ brq->data.blocks = 1;
+
+ if (brq->data.blocks > card->ext_csd.rel_sectors)
+ brq->data.blocks = card->ext_csd.rel_sectors;
+ else if (brq->data.blocks < card->ext_csd.rel_sectors)
+ brq->data.blocks = 1;
+ }
+}
+
static int mmc_blk_issue_rw_rq(struct mmc_queue *mq, struct request *req)
{
struct mmc_blk_data *md = mq->data;
@@ -338,10 +676,17 @@
struct mmc_blk_request brq;
int ret = 1, disable_multi = 0;
- mmc_claim_host(card->host);
+ /*
+ * Reliable writes are used to implement Forced Unit Access and
+ * REQ_META accesses, and are supported only on MMCs.
+ */
+ bool do_rel_wr = ((req->cmd_flags & REQ_FUA) ||
+ (req->cmd_flags & REQ_META)) &&
+ (rq_data_dir(req) == WRITE) &&
+ (md->flags & MMC_BLK_REL_WR);
do {
- struct mmc_command cmd;
+ struct mmc_command cmd = {0};
u32 readcmd, writecmd, status = 0;
memset(&brq, 0, sizeof(struct mmc_blk_request));
@@ -374,12 +719,12 @@
if (disable_multi && brq.data.blocks > 1)
brq.data.blocks = 1;
- if (brq.data.blocks > 1) {
+ if (brq.data.blocks > 1 || do_rel_wr) {
/* SPI multiblock writes terminate using a special
* token, not a STOP_TRANSMISSION request.
*/
- if (!mmc_host_is_spi(card->host)
- || rq_data_dir(req) == READ)
+ if (!mmc_host_is_spi(card->host) ||
+ rq_data_dir(req) == READ)
brq.mrq.stop = &brq.stop;
readcmd = MMC_READ_MULTIPLE_BLOCK;
writecmd = MMC_WRITE_MULTIPLE_BLOCK;
@@ -396,6 +741,38 @@
brq.data.flags |= MMC_DATA_WRITE;
}
+ if (do_rel_wr)
+ mmc_apply_rel_rw(&brq, card, req);
+
+ /*
+ * Pre-defined multi-block transfers are preferable to
+ * open ended-ones (and necessary for reliable writes).
+ * However, it is not sufficient to just send CMD23,
+ * and avoid the final CMD12, as on an error condition
+ * CMD12 (stop) needs to be sent anyway. This, coupled
+ * with Auto-CMD23 enhancements provided by some
+ * hosts, means that the complexity of dealing
+ * with this is best left to the host. If CMD23 is
+ * supported by card and host, we'll fill sbc in and let
+ * the host deal with handling it correctly. This means
+ * that for hosts that don't expose MMC_CAP_CMD23, no
+ * change of behavior will be observed.
+ *
+ * N.B: Some MMC cards experience perf degradation.
+ * We'll avoid using CMD23-bounded multiblock writes for
+ * these, while retaining features like reliable writes.
+ */
+
+ if ((md->flags & MMC_BLK_CMD23) &&
+ mmc_op_multi(brq.cmd.opcode) &&
+ (do_rel_wr || !(card->quirks & MMC_QUIRK_BLK_NO_CMD23))) {
+ brq.sbc.opcode = MMC_SET_BLOCK_COUNT;
+ brq.sbc.arg = brq.data.blocks |
+ (do_rel_wr ? (1 << 31) : 0);
+ brq.sbc.flags = MMC_RSP_R1 | MMC_CMD_AC;
+ brq.mrq.sbc = &brq.sbc;
+ }
+
mmc_set_data_timeout(&brq.data, card);
brq.data.sg = mq->sg;
@@ -431,7 +808,8 @@
* until later as we need to wait for the card to leave
* programming mode even when things go wrong.
*/
- if (brq.cmd.error || brq.data.error || brq.stop.error) {
+ if (brq.sbc.error || brq.cmd.error ||
+ brq.data.error || brq.stop.error) {
if (brq.data.blocks > 1 && rq_data_dir(req) == READ) {
/* Redo read one sector at a time */
printk(KERN_WARNING "%s: retrying using single "
@@ -442,6 +820,13 @@
status = get_card_status(card, req);
}
+ if (brq.sbc.error) {
+ printk(KERN_ERR "%s: error %d sending SET_BLOCK_COUNT "
+ "command, response %#x, card status %#x\n",
+ req->rq_disk->disk_name, brq.sbc.error,
+ brq.sbc.resp[0], status);
+ }
+
if (brq.cmd.error) {
printk(KERN_ERR "%s: error %d sending read/write "
"command, response %#x, card status %#x\n",
@@ -520,8 +905,6 @@
spin_unlock_irq(&md->lock);
} while (ret);
- mmc_release_host(card->host);
-
return 1;
cmd_err:
@@ -548,8 +931,6 @@
spin_unlock_irq(&md->lock);
}
- mmc_release_host(card->host);
-
spin_lock_irq(&md->lock);
while (ret)
ret = __blk_end_request(req, -EIO, blk_rq_cur_bytes(req));
@@ -560,14 +941,31 @@
static int mmc_blk_issue_rq(struct mmc_queue *mq, struct request *req)
{
+ int ret;
+ struct mmc_blk_data *md = mq->data;
+ struct mmc_card *card = md->queue.card;
+
+ mmc_claim_host(card->host);
+ ret = mmc_blk_part_switch(card, md);
+ if (ret) {
+ ret = 0;
+ goto out;
+ }
+
if (req->cmd_flags & REQ_DISCARD) {
if (req->cmd_flags & REQ_SECURE)
- return mmc_blk_issue_secdiscard_rq(mq, req);
+ ret = mmc_blk_issue_secdiscard_rq(mq, req);
else
- return mmc_blk_issue_discard_rq(mq, req);
+ ret = mmc_blk_issue_discard_rq(mq, req);
+ } else if (req->cmd_flags & REQ_FLUSH) {
+ ret = mmc_blk_issue_flush(mq, req);
} else {
- return mmc_blk_issue_rw_rq(mq, req);
+ ret = mmc_blk_issue_rw_rq(mq, req);
}
+
+out:
+ mmc_release_host(card->host);
+ return ret;
}
static inline int mmc_blk_readonly(struct mmc_card *card)
@@ -576,7 +974,11 @@
!(card->csd.cmdclass & CCC_BLOCK_WRITE);
}
-static struct mmc_blk_data *mmc_blk_alloc(struct mmc_card *card)
+static struct mmc_blk_data *mmc_blk_alloc_req(struct mmc_card *card,
+ struct device *parent,
+ sector_t size,
+ bool default_ro,
+ const char *subname)
{
struct mmc_blk_data *md;
int devidx, ret;
@@ -592,6 +994,19 @@
goto out;
}
+ /*
+ * !subname implies we are creating main mmc_blk_data that will be
+ * associated with mmc_card with mmc_set_drvdata. Due to device
+ * partitions, devidx will not coincide with a per-physical card
+ * index anymore so we keep track of a name index.
+ */
+ if (!subname) {
+ md->name_idx = find_first_zero_bit(name_use, max_devices);
+ __set_bit(md->name_idx, name_use);
+ }
+ else
+ md->name_idx = ((struct mmc_blk_data *)
+ dev_to_disk(parent)->private_data)->name_idx;
/*
* Set the read-only status based on the supported commands
@@ -606,6 +1021,7 @@
}
spin_lock_init(&md->lock);
+ INIT_LIST_HEAD(&md->part);
md->usage = 1;
ret = mmc_init_queue(&md->queue, card, &md->lock);
@@ -620,8 +1036,8 @@
md->disk->fops = &mmc_bdops;
md->disk->private_data = md;
md->disk->queue = md->queue.queue;
- md->disk->driverfs_dev = &card->dev;
- set_disk_ro(md->disk, md->read_only);
+ md->disk->driverfs_dev = parent;
+ set_disk_ro(md->disk, md->read_only || default_ro);
/*
* As discussed on lkml, GENHD_FL_REMOVABLE should:
@@ -636,24 +1052,26 @@
*/
snprintf(md->disk->disk_name, sizeof(md->disk->disk_name),
- "mmcblk%d", devidx);
+ "mmcblk%d%s", md->name_idx, subname ? subname : "");
blk_queue_logical_block_size(md->queue.queue, 512);
+ set_capacity(md->disk, size);
- if (!mmc_card_sd(card) && mmc_card_blockaddr(card)) {
- /*
- * The EXT_CSD sector count is in number or 512 byte
- * sectors.
- */
- set_capacity(md->disk, card->ext_csd.sectors);
- } else {
- /*
- * The CSD capacity field is in units of read_blkbits.
- * set_capacity takes units of 512 bytes.
- */
- set_capacity(md->disk,
- card->csd.capacity << (card->csd.read_blkbits - 9));
+ if (mmc_host_cmd23(card->host)) {
+ if (mmc_card_mmc(card) ||
+ (mmc_card_sd(card) &&
+ card->scr.cmds & SD_SCR_CMD23_SUPPORT))
+ md->flags |= MMC_BLK_CMD23;
}
+
+ if (mmc_card_mmc(card) &&
+ md->flags & MMC_BLK_CMD23 &&
+ ((card->ext_csd.rel_param & EXT_CSD_WR_REL_PARAM_EN) ||
+ card->ext_csd.rel_sectors)) {
+ md->flags |= MMC_BLK_REL_WR;
+ blk_queue_flush(md->queue.queue, REQ_FLUSH | REQ_FUA);
+ }
+
return md;
err_putdisk:
@@ -664,6 +1082,79 @@
return ERR_PTR(ret);
}
+static struct mmc_blk_data *mmc_blk_alloc(struct mmc_card *card)
+{
+ sector_t size;
+ struct mmc_blk_data *md;
+
+ if (!mmc_card_sd(card) && mmc_card_blockaddr(card)) {
+ /*
+ * The EXT_CSD sector count is in number or 512 byte
+ * sectors.
+ */
+ size = card->ext_csd.sectors;
+ } else {
+ /*
+ * The CSD capacity field is in units of read_blkbits.
+ * set_capacity takes units of 512 bytes.
+ */
+ size = card->csd.capacity << (card->csd.read_blkbits - 9);
+ }
+
+ md = mmc_blk_alloc_req(card, &card->dev, size, false, NULL);
+ return md;
+}
+
+static int mmc_blk_alloc_part(struct mmc_card *card,
+ struct mmc_blk_data *md,
+ unsigned int part_type,
+ sector_t size,
+ bool default_ro,
+ const char *subname)
+{
+ char cap_str[10];
+ struct mmc_blk_data *part_md;
+
+ part_md = mmc_blk_alloc_req(card, disk_to_dev(md->disk), size, default_ro,
+ subname);
+ if (IS_ERR(part_md))
+ return PTR_ERR(part_md);
+ part_md->part_type = part_type;
+ list_add(&part_md->part, &md->part);
+
+ string_get_size((u64)get_capacity(part_md->disk) << 9, STRING_UNITS_2,
+ cap_str, sizeof(cap_str));
+ printk(KERN_INFO "%s: %s %s partition %u %s\n",
+ part_md->disk->disk_name, mmc_card_id(card),
+ mmc_card_name(card), part_md->part_type, cap_str);
+ return 0;
+}
+
+static int mmc_blk_alloc_parts(struct mmc_card *card, struct mmc_blk_data *md)
+{
+ int ret = 0;
+
+ if (!mmc_card_mmc(card))
+ return 0;
+
+ if (card->ext_csd.boot_size) {
+ ret = mmc_blk_alloc_part(card, md, EXT_CSD_PART_CONFIG_ACC_BOOT0,
+ card->ext_csd.boot_size >> 9,
+ true,
+ "boot0");
+ if (ret)
+ return ret;
+ ret = mmc_blk_alloc_part(card, md, EXT_CSD_PART_CONFIG_ACC_BOOT1,
+ card->ext_csd.boot_size >> 9,
+ true,
+ "boot1");
+ if (ret)
+ return ret;
+ }
+
+ return ret;
+}
+
static int
mmc_blk_set_blksize(struct mmc_blk_data *md, struct mmc_card *card)
{
@@ -682,9 +1173,81 @@
return 0;
}
+static void mmc_blk_remove_req(struct mmc_blk_data *md)
+{
+ if (md) {
+ if (md->disk->flags & GENHD_FL_UP) {
+ device_remove_file(disk_to_dev(md->disk), &md->force_ro);
+
+ /* Stop new requests from getting into the queue */
+ del_gendisk(md->disk);
+ }
+
+ /* Then flush out any already in there */
+ mmc_cleanup_queue(&md->queue);
+ mmc_blk_put(md);
+ }
+}
+
+static void mmc_blk_remove_parts(struct mmc_card *card,
+ struct mmc_blk_data *md)
+{
+ struct list_head *pos, *q;
+ struct mmc_blk_data *part_md;
+
+ __clear_bit(md->name_idx, name_use);
+ list_for_each_safe(pos, q, &md->part) {
+ part_md = list_entry(pos, struct mmc_blk_data, part);
+ list_del(pos);
+ mmc_blk_remove_req(part_md);
+ }
+}
+
+static int mmc_add_disk(struct mmc_blk_data *md)
+{
+ int ret;
+
+ add_disk(md->disk);
+ md->force_ro.show = force_ro_show;
+ md->force_ro.store = force_ro_store;
+ sysfs_attr_init(&md->force_ro.attr);
+ md->force_ro.attr.name = "force_ro";
+ md->force_ro.attr.mode = S_IRUGO | S_IWUSR;
+ ret = device_create_file(disk_to_dev(md->disk), &md->force_ro);
+ if (ret)
+ del_gendisk(md->disk);
+
+ return ret;
+}
+
+static const struct mmc_fixup blk_fixups[] =
+{
+ MMC_FIXUP("SEM02G", 0x2, 0x100, add_quirk, MMC_QUIRK_INAND_CMD38),
+ MMC_FIXUP("SEM04G", 0x2, 0x100, add_quirk, MMC_QUIRK_INAND_CMD38),
+ MMC_FIXUP("SEM08G", 0x2, 0x100, add_quirk, MMC_QUIRK_INAND_CMD38),
+ MMC_FIXUP("SEM16G", 0x2, 0x100, add_quirk, MMC_QUIRK_INAND_CMD38),
+ MMC_FIXUP("SEM32G", 0x2, 0x100, add_quirk, MMC_QUIRK_INAND_CMD38),
+
+ /*
+ * Some MMC cards experience performance degradation with CMD23
+ * instead of CMD12-bounded multiblock transfers. For now we'll
+ * black list what's bad...
+ * - Certain Toshiba cards.
+ *
+ * N.B. This doesn't affect SD cards.
+ */
+ MMC_FIXUP("MMC08G", 0x11, CID_OEMID_ANY, add_quirk_mmc,
+ MMC_QUIRK_BLK_NO_CMD23),
+ MMC_FIXUP("MMC16G", 0x11, CID_OEMID_ANY, add_quirk_mmc,
+ MMC_QUIRK_BLK_NO_CMD23),
+ MMC_FIXUP("MMC32G", 0x11, CID_OEMID_ANY, add_quirk_mmc,
+ MMC_QUIRK_BLK_NO_CMD23),
+ END_FIXUP
+};
+
static int mmc_blk_probe(struct mmc_card *card)
{
- struct mmc_blk_data *md;
+ struct mmc_blk_data *md, *part_md;
int err;
char cap_str[10];
@@ -708,14 +1271,24 @@
md->disk->disk_name, mmc_card_id(card), mmc_card_name(card),
cap_str, md->read_only ? "(ro)" : "");
+ if (mmc_blk_alloc_parts(card, md))
+ goto out;
+
mmc_set_drvdata(card, md);
- add_disk(md->disk);
+ mmc_fixup_device(card, blk_fixups);
+
+ if (mmc_add_disk(md))
+ goto out;
+
+ list_for_each_entry(part_md, &md->part, part) {
+ if (mmc_add_disk(part_md))
+ goto out;
+ }
return 0;
out:
- mmc_cleanup_queue(&md->queue);
- mmc_blk_put(md);
-
+ mmc_blk_remove_parts(card, md);
+ mmc_blk_remove_req(md);
return err;
}
@@ -723,36 +1296,43 @@
{
struct mmc_blk_data *md = mmc_get_drvdata(card);
- if (md) {
- /* Stop new requests from getting into the queue */
- del_gendisk(md->disk);
-
- /* Then flush out any already in there */
- mmc_cleanup_queue(&md->queue);
-
- mmc_blk_put(md);
- }
+ mmc_blk_remove_parts(card, md);
+ mmc_blk_remove_req(md);
mmc_set_drvdata(card, NULL);
}
#ifdef CONFIG_PM
static int mmc_blk_suspend(struct mmc_card *card, pm_message_t state)
{
+ struct mmc_blk_data *part_md;
struct mmc_blk_data *md = mmc_get_drvdata(card);
if (md) {
mmc_queue_suspend(&md->queue);
+ list_for_each_entry(part_md, &md->part, part) {
+ mmc_queue_suspend(&part_md->queue);
+ }
}
return 0;
}
static int mmc_blk_resume(struct mmc_card *card)
{
+ struct mmc_blk_data *part_md;
struct mmc_blk_data *md = mmc_get_drvdata(card);
if (md) {
mmc_blk_set_blksize(md, card);
+
+ /*
+ * Resume involves the card going into idle state,
+ * so current partition is always the main one.
+ */
+ md->part_curr = md->part_type;
mmc_queue_resume(&md->queue);
+ list_for_each_entry(part_md, &md->part, part) {
+ mmc_queue_resume(&part_md->queue);
+ }
}
return 0;
}
diff --git a/drivers/mmc/card/mmc_test.c b/drivers/mmc/card/mmc_test.c
index abc1a63..233cdfa 100644
--- a/drivers/mmc/card/mmc_test.c
+++ b/drivers/mmc/card/mmc_test.c
@@ -212,7 +212,7 @@
static int mmc_test_wait_busy(struct mmc_test_card *test)
{
int ret, busy;
- struct mmc_command cmd;
+ struct mmc_command cmd = {0};
busy = 0;
do {
@@ -246,18 +246,13 @@
{
int ret;
- struct mmc_request mrq;
- struct mmc_command cmd;
- struct mmc_command stop;
- struct mmc_data data;
+ struct mmc_request mrq = {0};
+ struct mmc_command cmd = {0};
+ struct mmc_command stop = {0};
+ struct mmc_data data = {0};
struct scatterlist sg;
- memset(&mrq, 0, sizeof(struct mmc_request));
- memset(&cmd, 0, sizeof(struct mmc_command));
- memset(&data, 0, sizeof(struct mmc_data));
- memset(&stop, 0, sizeof(struct mmc_command));
-
mrq.cmd = &cmd;
mrq.data = &data;
mrq.stop = &stop;
@@ -731,15 +726,10 @@
struct scatterlist *sg, unsigned sg_len, unsigned dev_addr,
unsigned blocks, unsigned blksz, int write)
{
- struct mmc_request mrq;
- struct mmc_command cmd;
- struct mmc_command stop;
- struct mmc_data data;
-
- memset(&mrq, 0, sizeof(struct mmc_request));
- memset(&cmd, 0, sizeof(struct mmc_command));
- memset(&data, 0, sizeof(struct mmc_data));
- memset(&stop, 0, sizeof(struct mmc_command));
+ struct mmc_request mrq = {0};
+ struct mmc_command cmd = {0};
+ struct mmc_command stop = {0};
+ struct mmc_data data = {0};
mrq.cmd = &cmd;
mrq.data = &data;
@@ -761,18 +751,13 @@
static int mmc_test_broken_transfer(struct mmc_test_card *test,
unsigned blocks, unsigned blksz, int write)
{
- struct mmc_request mrq;
- struct mmc_command cmd;
- struct mmc_command stop;
- struct mmc_data data;
+ struct mmc_request mrq = {0};
+ struct mmc_command cmd = {0};
+ struct mmc_command stop = {0};
+ struct mmc_data data = {0};
struct scatterlist sg;
- memset(&mrq, 0, sizeof(struct mmc_request));
- memset(&cmd, 0, sizeof(struct mmc_command));
- memset(&data, 0, sizeof(struct mmc_data));
- memset(&stop, 0, sizeof(struct mmc_command));
-
mrq.cmd = &cmd;
mrq.data = &data;
mrq.stop = &stop;
@@ -1401,8 +1386,9 @@
*/
static int mmc_test_area_fill(struct mmc_test_card *test)
{
- return mmc_test_area_io(test, test->area.max_tfr, test->area.dev_addr,
- 1, 0, 0);
+ struct mmc_test_area *t = &test->area;
+
+ return mmc_test_area_io(test, t->max_tfr, t->dev_addr, 1, 0, 0);
}
/*
@@ -1415,7 +1401,7 @@
if (!mmc_can_erase(test->card))
return 0;
- return mmc_erase(test->card, t->dev_addr, test->area.max_sz >> 9,
+ return mmc_erase(test->card, t->dev_addr, t->max_sz >> 9,
MMC_ERASE_ARG);
}
@@ -1542,8 +1528,10 @@
static int mmc_test_best_performance(struct mmc_test_card *test, int write,
int max_scatter)
{
- return mmc_test_area_io(test, test->area.max_tfr, test->area.dev_addr,
- write, max_scatter, 1);
+ struct mmc_test_area *t = &test->area;
+
+ return mmc_test_area_io(test, t->max_tfr, t->dev_addr, write,
+ max_scatter, 1);
}
/*
@@ -1583,18 +1571,19 @@
*/
static int mmc_test_profile_read_perf(struct mmc_test_card *test)
{
+ struct mmc_test_area *t = &test->area;
unsigned long sz;
unsigned int dev_addr;
int ret;
- for (sz = 512; sz < test->area.max_tfr; sz <<= 1) {
- dev_addr = test->area.dev_addr + (sz >> 9);
+ for (sz = 512; sz < t->max_tfr; sz <<= 1) {
+ dev_addr = t->dev_addr + (sz >> 9);
ret = mmc_test_area_io(test, sz, dev_addr, 0, 0, 1);
if (ret)
return ret;
}
- sz = test->area.max_tfr;
- dev_addr = test->area.dev_addr;
+ sz = t->max_tfr;
+ dev_addr = t->dev_addr;
return mmc_test_area_io(test, sz, dev_addr, 0, 0, 1);
}
@@ -1603,6 +1592,7 @@
*/
static int mmc_test_profile_write_perf(struct mmc_test_card *test)
{
+ struct mmc_test_area *t = &test->area;
unsigned long sz;
unsigned int dev_addr;
int ret;
@@ -1610,8 +1600,8 @@
ret = mmc_test_area_erase(test);
if (ret)
return ret;
- for (sz = 512; sz < test->area.max_tfr; sz <<= 1) {
- dev_addr = test->area.dev_addr + (sz >> 9);
+ for (sz = 512; sz < t->max_tfr; sz <<= 1) {
+ dev_addr = t->dev_addr + (sz >> 9);
ret = mmc_test_area_io(test, sz, dev_addr, 1, 0, 1);
if (ret)
return ret;
@@ -1619,8 +1609,8 @@
ret = mmc_test_area_erase(test);
if (ret)
return ret;
- sz = test->area.max_tfr;
- dev_addr = test->area.dev_addr;
+ sz = t->max_tfr;
+ dev_addr = t->dev_addr;
return mmc_test_area_io(test, sz, dev_addr, 1, 0, 1);
}
@@ -1629,6 +1619,7 @@
*/
static int mmc_test_profile_trim_perf(struct mmc_test_card *test)
{
+ struct mmc_test_area *t = &test->area;
unsigned long sz;
unsigned int dev_addr;
struct timespec ts1, ts2;
@@ -1640,8 +1631,8 @@
if (!mmc_can_erase(test->card))
return RESULT_UNSUP_HOST;
- for (sz = 512; sz < test->area.max_sz; sz <<= 1) {
- dev_addr = test->area.dev_addr + (sz >> 9);
+ for (sz = 512; sz < t->max_sz; sz <<= 1) {
+ dev_addr = t->dev_addr + (sz >> 9);
getnstimeofday(&ts1);
ret = mmc_erase(test->card, dev_addr, sz >> 9, MMC_TRIM_ARG);
if (ret)
@@ -1649,7 +1640,7 @@
getnstimeofday(&ts2);
mmc_test_print_rate(test, sz, &ts1, &ts2);
}
- dev_addr = test->area.dev_addr;
+ dev_addr = t->dev_addr;
getnstimeofday(&ts1);
ret = mmc_erase(test->card, dev_addr, sz >> 9, MMC_TRIM_ARG);
if (ret)
@@ -1661,12 +1652,13 @@
static int mmc_test_seq_read_perf(struct mmc_test_card *test, unsigned long sz)
{
+ struct mmc_test_area *t = &test->area;
unsigned int dev_addr, i, cnt;
struct timespec ts1, ts2;
int ret;
- cnt = test->area.max_sz / sz;
- dev_addr = test->area.dev_addr;
+ cnt = t->max_sz / sz;
+ dev_addr = t->dev_addr;
getnstimeofday(&ts1);
for (i = 0; i < cnt; i++) {
ret = mmc_test_area_io(test, sz, dev_addr, 0, 0, 0);
@@ -1684,20 +1676,22 @@
*/
static int mmc_test_profile_seq_read_perf(struct mmc_test_card *test)
{
+ struct mmc_test_area *t = &test->area;
unsigned long sz;
int ret;
- for (sz = 512; sz < test->area.max_tfr; sz <<= 1) {
+ for (sz = 512; sz < t->max_tfr; sz <<= 1) {
ret = mmc_test_seq_read_perf(test, sz);
if (ret)
return ret;
}
- sz = test->area.max_tfr;
+ sz = t->max_tfr;
return mmc_test_seq_read_perf(test, sz);
}
static int mmc_test_seq_write_perf(struct mmc_test_card *test, unsigned long sz)
{
+ struct mmc_test_area *t = &test->area;
unsigned int dev_addr, i, cnt;
struct timespec ts1, ts2;
int ret;
@@ -1705,8 +1699,8 @@
ret = mmc_test_area_erase(test);
if (ret)
return ret;
- cnt = test->area.max_sz / sz;
- dev_addr = test->area.dev_addr;
+ cnt = t->max_sz / sz;
+ dev_addr = t->dev_addr;
getnstimeofday(&ts1);
for (i = 0; i < cnt; i++) {
ret = mmc_test_area_io(test, sz, dev_addr, 1, 0, 0);
@@ -1724,15 +1718,16 @@
*/
static int mmc_test_profile_seq_write_perf(struct mmc_test_card *test)
{
+ struct mmc_test_area *t = &test->area;
unsigned long sz;
int ret;
- for (sz = 512; sz < test->area.max_tfr; sz <<= 1) {
+ for (sz = 512; sz < t->max_tfr; sz <<= 1) {
ret = mmc_test_seq_write_perf(test, sz);
if (ret)
return ret;
}
- sz = test->area.max_tfr;
+ sz = t->max_tfr;
return mmc_test_seq_write_perf(test, sz);
}
@@ -1741,6 +1736,7 @@
*/
static int mmc_test_profile_seq_trim_perf(struct mmc_test_card *test)
{
+ struct mmc_test_area *t = &test->area;
unsigned long sz;
unsigned int dev_addr, i, cnt;
struct timespec ts1, ts2;
@@ -1752,15 +1748,15 @@
if (!mmc_can_erase(test->card))
return RESULT_UNSUP_HOST;
- for (sz = 512; sz <= test->area.max_sz; sz <<= 1) {
+ for (sz = 512; sz <= t->max_sz; sz <<= 1) {
ret = mmc_test_area_erase(test);
if (ret)
return ret;
ret = mmc_test_area_fill(test);
if (ret)
return ret;
- cnt = test->area.max_sz / sz;
- dev_addr = test->area.dev_addr;
+ cnt = t->max_sz / sz;
+ dev_addr = t->dev_addr;
getnstimeofday(&ts1);
for (i = 0; i < cnt; i++) {
ret = mmc_erase(test->card, dev_addr, sz >> 9,
@@ -1823,11 +1819,12 @@
static int mmc_test_random_perf(struct mmc_test_card *test, int write)
{
+ struct mmc_test_area *t = &test->area;
unsigned int next;
unsigned long sz;
int ret;
- for (sz = 512; sz < test->area.max_tfr; sz <<= 1) {
+ for (sz = 512; sz < t->max_tfr; sz <<= 1) {
/*
* When writing, try to get more consistent results by running
* the test twice with exactly the same I/O but outputting the
@@ -1844,7 +1841,7 @@
if (ret)
return ret;
}
- sz = test->area.max_tfr;
+ sz = t->max_tfr;
if (write) {
next = rnd_next;
ret = mmc_test_rnd_perf(test, write, 0, sz);
@@ -1874,17 +1871,18 @@
static int mmc_test_seq_perf(struct mmc_test_card *test, int write,
unsigned int tot_sz, int max_scatter)
{
+ struct mmc_test_area *t = &test->area;
unsigned int dev_addr, i, cnt, sz, ssz;
struct timespec ts1, ts2;
int ret;
- sz = test->area.max_tfr;
+ sz = t->max_tfr;
+
/*
* In the case of a maximally scattered transfer, the maximum transfer
* size is further limited by using PAGE_SIZE segments.
*/
if (max_scatter) {
- struct mmc_test_area *t = &test->area;
unsigned long max_tfr;
if (t->max_seg_sz >= PAGE_SIZE)
diff --git a/drivers/mmc/card/queue.c b/drivers/mmc/card/queue.c
index 2ae7275..c07322c 100644
--- a/drivers/mmc/card/queue.c
+++ b/drivers/mmc/card/queue.c
@@ -343,18 +343,14 @@
*/
void mmc_queue_bounce_pre(struct mmc_queue *mq)
{
- unsigned long flags;
-
if (!mq->bounce_buf)
return;
if (rq_data_dir(mq->req) != WRITE)
return;
- local_irq_save(flags);
sg_copy_to_buffer(mq->bounce_sg, mq->bounce_sg_len,
mq->bounce_buf, mq->sg[0].length);
- local_irq_restore(flags);
}
/*
@@ -363,17 +359,13 @@
*/
void mmc_queue_bounce_post(struct mmc_queue *mq)
{
- unsigned long flags;
-
if (!mq->bounce_buf)
return;
if (rq_data_dir(mq->req) != READ)
return;
- local_irq_save(flags);
sg_copy_from_buffer(mq->bounce_sg, mq->bounce_sg_len,
mq->bounce_buf, mq->sg[0].length);
- local_irq_restore(flags);
}
diff --git a/drivers/mmc/core/bus.c b/drivers/mmc/core/bus.c
index d6d62fd..393d817 100644
--- a/drivers/mmc/core/bus.c
+++ b/drivers/mmc/core/bus.c
@@ -274,8 +274,12 @@
break;
case MMC_TYPE_SD:
type = "SD";
- if (mmc_card_blockaddr(card))
- type = "SDHC";
+ if (mmc_card_blockaddr(card)) {
+ if (mmc_card_ext_capacity(card))
+ type = "SDXC";
+ else
+ type = "SDHC";
+ }
break;
case MMC_TYPE_SDIO:
type = "SDIO";
@@ -299,7 +303,8 @@
} else {
printk(KERN_INFO "%s: new %s%s%s card at address %04x\n",
mmc_hostname(card->host),
- mmc_card_highspeed(card) ? "high speed " : "",
+ mmc_sd_card_uhs(card) ? "ultra high speed " :
+ (mmc_card_highspeed(card) ? "high speed " : ""),
mmc_card_ddr_mode(card) ? "DDR " : "",
type, card->rca);
}
diff --git a/drivers/mmc/core/core.c b/drivers/mmc/core/core.c
index 1f453ac..68091dd 100644
--- a/drivers/mmc/core/core.c
+++ b/drivers/mmc/core/core.c
@@ -236,12 +236,10 @@
*/
int mmc_wait_for_cmd(struct mmc_host *host, struct mmc_command *cmd, int retries)
{
- struct mmc_request mrq;
+ struct mmc_request mrq = {0};
WARN_ON(!host->claimed);
- memset(&mrq, 0, sizeof(struct mmc_request));
-
memset(cmd->resp, 0, sizeof(cmd->resp));
cmd->retries = retries;
@@ -720,22 +718,12 @@
}
/*
- * Change data bus width and DDR mode of a host.
- */
-void mmc_set_bus_width_ddr(struct mmc_host *host, unsigned int width,
- unsigned int ddr)
-{
- host->ios.bus_width = width;
- host->ios.ddr = ddr;
- mmc_set_ios(host);
-}
-
-/*
* Change data bus width of a host.
*/
void mmc_set_bus_width(struct mmc_host *host, unsigned int width)
{
- mmc_set_bus_width_ddr(host, width, MMC_SDR_MODE);
+ host->ios.bus_width = width;
+ mmc_set_ios(host);
}
/**
@@ -944,6 +932,38 @@
return ocr;
}
+int mmc_set_signal_voltage(struct mmc_host *host, int signal_voltage, bool cmd11)
+{
+ struct mmc_command cmd = {0};
+ int err = 0;
+
+ BUG_ON(!host);
+
+ /*
+ * Send CMD11 only if the request is to switch the card to
+ * 1.8V signalling.
+ */
+ if ((signal_voltage != MMC_SIGNAL_VOLTAGE_330) && cmd11) {
+ cmd.opcode = SD_SWITCH_VOLTAGE;
+ cmd.arg = 0;
+ cmd.flags = MMC_RSP_R1 | MMC_CMD_AC;
+
+ err = mmc_wait_for_cmd(host, &cmd, 0);
+ if (err)
+ return err;
+
+ if (!mmc_host_is_spi(host) && (cmd.resp[0] & R1_ERROR))
+ return -EIO;
+ }
+
+ host->ios.signal_voltage = signal_voltage;
+
+ if (host->ops->start_signal_voltage_switch)
+ err = host->ops->start_signal_voltage_switch(host, &host->ios);
+
+ return err;
+}
+
/*
* Select timing parameters for host.
*/
@@ -954,6 +974,15 @@
}
/*
+ * Select appropriate driver type for host.
+ */
+void mmc_set_driver_type(struct mmc_host *host, unsigned int drv_type)
+{
+ host->ios.drv_type = drv_type;
+ mmc_set_ios(host);
+}
+
+/*
* Apply power to the MMC stack. This is a two-stage process.
* First, we enable power to the card without the clock running.
* We then wait a bit for the power to stabilise. Finally,
@@ -1187,9 +1216,8 @@
}
}
-static void mmc_set_mmc_erase_timeout(struct mmc_card *card,
- struct mmc_command *cmd,
- unsigned int arg, unsigned int qty)
+static unsigned int mmc_mmc_erase_timeout(struct mmc_card *card,
+ unsigned int arg, unsigned int qty)
{
unsigned int erase_timeout;
@@ -1246,44 +1274,48 @@
if (mmc_host_is_spi(card->host) && erase_timeout < 1000)
erase_timeout = 1000;
- cmd->erase_timeout = erase_timeout;
+ return erase_timeout;
}
-static void mmc_set_sd_erase_timeout(struct mmc_card *card,
- struct mmc_command *cmd, unsigned int arg,
- unsigned int qty)
+static unsigned int mmc_sd_erase_timeout(struct mmc_card *card,
+ unsigned int arg,
+ unsigned int qty)
{
+ unsigned int erase_timeout;
+
if (card->ssr.erase_timeout) {
/* Erase timeout specified in SD Status Register (SSR) */
- cmd->erase_timeout = card->ssr.erase_timeout * qty +
- card->ssr.erase_offset;
+ erase_timeout = card->ssr.erase_timeout * qty +
+ card->ssr.erase_offset;
} else {
/*
* Erase timeout not specified in SD Status Register (SSR) so
* use 250ms per write block.
*/
- cmd->erase_timeout = 250 * qty;
+ erase_timeout = 250 * qty;
}
/* Must not be less than 1 second */
- if (cmd->erase_timeout < 1000)
- cmd->erase_timeout = 1000;
+ if (erase_timeout < 1000)
+ erase_timeout = 1000;
+
+ return erase_timeout;
}
-static void mmc_set_erase_timeout(struct mmc_card *card,
- struct mmc_command *cmd, unsigned int arg,
- unsigned int qty)
+static unsigned int mmc_erase_timeout(struct mmc_card *card,
+ unsigned int arg,
+ unsigned int qty)
{
if (mmc_card_sd(card))
- mmc_set_sd_erase_timeout(card, cmd, arg, qty);
+ return mmc_sd_erase_timeout(card, arg, qty);
else
- mmc_set_mmc_erase_timeout(card, cmd, arg, qty);
+ return mmc_mmc_erase_timeout(card, arg, qty);
}
static int mmc_do_erase(struct mmc_card *card, unsigned int from,
unsigned int to, unsigned int arg)
{
- struct mmc_command cmd;
+ struct mmc_command cmd = {0};
unsigned int qty = 0;
int err;
@@ -1317,7 +1349,6 @@
to <<= 9;
}
- memset(&cmd, 0, sizeof(struct mmc_command));
if (mmc_card_sd(card))
cmd.opcode = SD_ERASE_WR_BLK_START;
else
@@ -1351,7 +1382,7 @@
cmd.opcode = MMC_ERASE;
cmd.arg = arg;
cmd.flags = MMC_RSP_SPI_R1B | MMC_RSP_R1B | MMC_CMD_AC;
- mmc_set_erase_timeout(card, &cmd, arg, qty);
+ cmd.cmd_timeout_ms = mmc_erase_timeout(card, arg, qty);
err = mmc_wait_for_cmd(card->host, &cmd, 0);
if (err) {
printk(KERN_ERR "mmc_erase: erase error %d, status %#x\n",
@@ -1487,12 +1518,11 @@
int mmc_set_blocklen(struct mmc_card *card, unsigned int blocklen)
{
- struct mmc_command cmd;
+ struct mmc_command cmd = {0};
if (mmc_card_blockaddr(card) || mmc_card_ddr_mode(card))
return 0;
- memset(&cmd, 0, sizeof(struct mmc_command));
cmd.opcode = MMC_SET_BLOCKLEN;
cmd.arg = blocklen;
cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_R1 | MMC_CMD_AC;
@@ -1578,7 +1608,7 @@
for (i = 0; i < ARRAY_SIZE(freqs); i++) {
if (!mmc_rescan_try_freq(host, max(freqs[i], host->f_min)))
break;
- if (freqs[i] < host->f_min)
+ if (freqs[i] <= host->f_min)
break;
}
mmc_release_host(host);
@@ -1746,7 +1776,7 @@
}
mmc_bus_put(host);
- if (!err && !(host->pm_flags & MMC_PM_KEEP_POWER))
+ if (!err && !mmc_card_keep_power(host))
mmc_power_off(host);
return err;
@@ -1764,7 +1794,7 @@
mmc_bus_get(host);
if (host->bus_ops && !host->bus_dead) {
- if (!(host->pm_flags & MMC_PM_KEEP_POWER)) {
+ if (!mmc_card_keep_power(host)) {
mmc_power_up(host);
mmc_select_voltage(host, host->ocr);
/*
@@ -1789,6 +1819,7 @@
err = 0;
}
}
+ host->pm_flags &= ~MMC_PM_KEEP_POWER;
mmc_bus_put(host);
return err;
diff --git a/drivers/mmc/core/core.h b/drivers/mmc/core/core.h
index 20b1c08..d9411ed 100644
--- a/drivers/mmc/core/core.h
+++ b/drivers/mmc/core/core.h
@@ -38,10 +38,11 @@
void mmc_set_ungated(struct mmc_host *host);
void mmc_set_bus_mode(struct mmc_host *host, unsigned int mode);
void mmc_set_bus_width(struct mmc_host *host, unsigned int width);
-void mmc_set_bus_width_ddr(struct mmc_host *host, unsigned int width,
- unsigned int ddr);
u32 mmc_select_voltage(struct mmc_host *host, u32 ocr);
+int mmc_set_signal_voltage(struct mmc_host *host, int signal_voltage,
+ bool cmd11);
void mmc_set_timing(struct mmc_host *host, unsigned int timing);
+void mmc_set_driver_type(struct mmc_host *host, unsigned int drv_type);
static inline void mmc_delay(unsigned int ms)
{
@@ -61,8 +62,6 @@
int mmc_attach_sd(struct mmc_host *host);
int mmc_attach_sdio(struct mmc_host *host);
-void mmc_fixup_device(struct mmc_card *card);
-
/* Module parameters */
extern int use_spi_crc;
diff --git a/drivers/mmc/core/host.c b/drivers/mmc/core/host.c
index 461e6a1..b29d3e8 100644
--- a/drivers/mmc/core/host.c
+++ b/drivers/mmc/core/host.c
@@ -325,12 +325,12 @@
WARN_ON((host->caps & MMC_CAP_SDIO_IRQ) &&
!host->ops->enable_sdio_irq);
- led_trigger_register_simple(dev_name(&host->class_dev), &host->led);
-
err = device_add(&host->class_dev);
if (err)
return err;
+ led_trigger_register_simple(dev_name(&host->class_dev), &host->led);
+
#ifdef CONFIG_DEBUG_FS
mmc_add_host_debugfs(host);
#endif
diff --git a/drivers/mmc/core/mmc.c b/drivers/mmc/core/mmc.c
index 772d0d0..2a7e43b 100644
--- a/drivers/mmc/core/mmc.c
+++ b/drivers/mmc/core/mmc.c
@@ -20,6 +20,7 @@
#include "core.h"
#include "bus.h"
#include "mmc_ops.h"
+#include "sd_ops.h"
static const unsigned int tran_exp[] = {
10000, 100000, 1000000, 10000000,
@@ -173,14 +174,17 @@
}
/*
- * Read and decode extended CSD.
+ * Read extended CSD.
*/
-static int mmc_read_ext_csd(struct mmc_card *card)
+static int mmc_get_ext_csd(struct mmc_card *card, u8 **new_ext_csd)
{
int err;
u8 *ext_csd;
BUG_ON(!card);
+ BUG_ON(!new_ext_csd);
+
+ *new_ext_csd = NULL;
if (card->csd.mmca_vsn < CSD_SPEC_VER_4)
return 0;
@@ -198,12 +202,15 @@
err = mmc_send_ext_csd(card, ext_csd);
if (err) {
+ kfree(ext_csd);
+ *new_ext_csd = NULL;
+
/* If the host or the card can't do the switch,
* fail more gracefully. */
if ((err != -EINVAL)
&& (err != -ENOSYS)
&& (err != -EFAULT))
- goto out;
+ return err;
/*
* High capacity cards should have this "magic" size
@@ -221,9 +228,23 @@
mmc_hostname(card->host));
err = 0;
}
+ } else
+ *new_ext_csd = ext_csd;
- goto out;
- }
+ return err;
+}
+
+/*
+ * Decode extended CSD.
+ */
+static int mmc_read_ext_csd(struct mmc_card *card, u8 *ext_csd)
+{
+ int err = 0;
+
+ BUG_ON(!card);
+
+ if (!ext_csd)
+ return 0;
/* Version is coded in the CSD_STRUCTURE byte in the EXT_CSD register */
if (card->csd.structure == 3) {
@@ -288,6 +309,10 @@
if (card->ext_csd.rev >= 3) {
u8 sa_shift = ext_csd[EXT_CSD_S_A_TIMEOUT];
+ card->ext_csd.part_config = ext_csd[EXT_CSD_PART_CONFIG];
+
+ /* EXT_CSD value is in units of 10ms, but we store in ms */
+ card->ext_csd.part_time = 10 * ext_csd[EXT_CSD_PART_SWITCH_TIME];
/* Sleep / awake timeout in 100ns units */
if (sa_shift > 0 && sa_shift <= 0x17)
@@ -299,6 +324,14 @@
ext_csd[EXT_CSD_ERASE_TIMEOUT_MULT];
card->ext_csd.hc_erase_size =
ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] << 10;
+
+ card->ext_csd.rel_sectors = ext_csd[EXT_CSD_REL_WR_SEC_C];
+
+ /*
+ * There are two boot regions of equal size, defined in
+ * multiples of 128K.
+ */
+ card->ext_csd.boot_size = ext_csd[EXT_CSD_BOOT_MULT] << 17;
}
if (card->ext_csd.rev >= 4) {
@@ -350,14 +383,78 @@
ext_csd[EXT_CSD_TRIM_MULT];
}
+ if (card->ext_csd.rev >= 5)
+ card->ext_csd.rel_param = ext_csd[EXT_CSD_WR_REL_PARAM];
+
if (ext_csd[EXT_CSD_ERASED_MEM_CONT])
card->erased_byte = 0xFF;
else
card->erased_byte = 0x0;
out:
- kfree(ext_csd);
+ return err;
+}
+static inline void mmc_free_ext_csd(u8 *ext_csd)
+{
+ kfree(ext_csd);
+}
+
+
+static int mmc_compare_ext_csds(struct mmc_card *card, u8 *ext_csd,
+ unsigned bus_width)
+{
+ u8 *bw_ext_csd;
+ int err;
+
+ err = mmc_get_ext_csd(card, &bw_ext_csd);
+ if (err)
+ return err;
+
+ if ((ext_csd == NULL || bw_ext_csd == NULL)) {
+ if (bus_width != MMC_BUS_WIDTH_1)
+ err = -EINVAL;
+ goto out;
+ }
+
+ if (bus_width == MMC_BUS_WIDTH_1)
+ goto out;
+
+ /* only compare read only fields */
+ err = (!(ext_csd[EXT_CSD_PARTITION_SUPPORT] ==
+ bw_ext_csd[EXT_CSD_PARTITION_SUPPORT]) &&
+ (ext_csd[EXT_CSD_ERASED_MEM_CONT] ==
+ bw_ext_csd[EXT_CSD_ERASED_MEM_CONT]) &&
+ (ext_csd[EXT_CSD_REV] ==
+ bw_ext_csd[EXT_CSD_REV]) &&
+ (ext_csd[EXT_CSD_STRUCTURE] ==
+ bw_ext_csd[EXT_CSD_STRUCTURE]) &&
+ (ext_csd[EXT_CSD_CARD_TYPE] ==
+ bw_ext_csd[EXT_CSD_CARD_TYPE]) &&
+ (ext_csd[EXT_CSD_S_A_TIMEOUT] ==
+ bw_ext_csd[EXT_CSD_S_A_TIMEOUT]) &&
+ (ext_csd[EXT_CSD_HC_WP_GRP_SIZE] ==
+ bw_ext_csd[EXT_CSD_HC_WP_GRP_SIZE]) &&
+ (ext_csd[EXT_CSD_ERASE_TIMEOUT_MULT] ==
+ bw_ext_csd[EXT_CSD_ERASE_TIMEOUT_MULT]) &&
+ (ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE] ==
+ bw_ext_csd[EXT_CSD_HC_ERASE_GRP_SIZE]) &&
+ (ext_csd[EXT_CSD_SEC_TRIM_MULT] ==
+ bw_ext_csd[EXT_CSD_SEC_TRIM_MULT]) &&
+ (ext_csd[EXT_CSD_SEC_ERASE_MULT] ==
+ bw_ext_csd[EXT_CSD_SEC_ERASE_MULT]) &&
+ (ext_csd[EXT_CSD_SEC_FEATURE_SUPPORT] ==
+ bw_ext_csd[EXT_CSD_SEC_FEATURE_SUPPORT]) &&
+ (ext_csd[EXT_CSD_TRIM_MULT] ==
+ bw_ext_csd[EXT_CSD_TRIM_MULT]) &&
+ memcmp(&ext_csd[EXT_CSD_SEC_CNT],
+ &bw_ext_csd[EXT_CSD_SEC_CNT],
+ 4) != 0);
+ if (err)
+ err = -EINVAL;
+
+out:
+ mmc_free_ext_csd(bw_ext_csd);
return err;
}
@@ -422,6 +519,7 @@
u32 cid[4];
unsigned int max_dtr;
u32 rocr;
+ u8 *ext_csd = NULL;
BUG_ON(!host);
WARN_ON(!host->claimed);
@@ -520,7 +618,11 @@
/*
* Fetch and process extended CSD.
*/
- err = mmc_read_ext_csd(card);
+
+ err = mmc_get_ext_csd(card, &ext_csd);
+ if (err)
+ goto free_card;
+ err = mmc_read_ext_csd(card, ext_csd);
if (err)
goto free_card;
@@ -542,7 +644,7 @@
*/
if (card->ext_csd.enhanced_area_en) {
err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
- EXT_CSD_ERASE_GROUP_DEF, 1);
+ EXT_CSD_ERASE_GROUP_DEF, 1, 0);
if (err && err != -EBADMSG)
goto free_card;
@@ -568,12 +670,24 @@
}
/*
+ * Ensure eMMC user default partition is enabled
+ */
+ if (card->ext_csd.part_config & EXT_CSD_PART_CONFIG_ACC_MASK) {
+ card->ext_csd.part_config &= ~EXT_CSD_PART_CONFIG_ACC_MASK;
+ err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONFIG,
+ card->ext_csd.part_config,
+ card->ext_csd.part_time);
+ if (err && err != -EBADMSG)
+ goto free_card;
+ }
+
+ /*
* Activate high speed (if supported)
*/
if ((card->ext_csd.hs_max_dtr != 0) &&
(host->caps & MMC_CAP_MMC_HIGHSPEED)) {
err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
- EXT_CSD_HS_TIMING, 1);
+ EXT_CSD_HS_TIMING, 1, 0);
if (err && err != -EBADMSG)
goto free_card;
@@ -606,10 +720,14 @@
*/
if (mmc_card_highspeed(card)) {
if ((card->ext_csd.card_type & EXT_CSD_CARD_TYPE_DDR_1_8V)
- && (host->caps & (MMC_CAP_1_8V_DDR)))
+ && ((host->caps & (MMC_CAP_1_8V_DDR |
+ MMC_CAP_UHS_DDR50))
+ == (MMC_CAP_1_8V_DDR | MMC_CAP_UHS_DDR50)))
ddr = MMC_1_8V_DDR_MODE;
else if ((card->ext_csd.card_type & EXT_CSD_CARD_TYPE_DDR_1_2V)
- && (host->caps & (MMC_CAP_1_2V_DDR)))
+ && ((host->caps & (MMC_CAP_1_2V_DDR |
+ MMC_CAP_UHS_DDR50))
+ == (MMC_CAP_1_2V_DDR | MMC_CAP_UHS_DDR50)))
ddr = MMC_1_2V_DDR_MODE;
}
@@ -640,18 +758,22 @@
ddr = 0; /* no DDR for 1-bit width */
err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
EXT_CSD_BUS_WIDTH,
- ext_csd_bits[idx][0]);
+ ext_csd_bits[idx][0],
+ 0);
if (!err) {
- mmc_set_bus_width_ddr(card->host,
- bus_width, MMC_SDR_MODE);
+ mmc_set_bus_width(card->host, bus_width);
+
/*
* If controller can't handle bus width test,
- * use the highest bus width to maintain
- * compatibility with previous MMC behavior.
+ * compare ext_csd previously read in 1 bit mode
+ * against ext_csd at new bus width
*/
if (!(host->caps & MMC_CAP_BUS_WIDTH_TEST))
- break;
- err = mmc_bus_test(card, bus_width);
+ err = mmc_compare_ext_csds(card,
+ ext_csd,
+ bus_width);
+ else
+ err = mmc_bus_test(card, bus_width);
if (!err)
break;
}
@@ -659,8 +781,9 @@
if (!err && ddr) {
err = mmc_switch(card, EXT_CSD_CMD_SET_NORMAL,
- EXT_CSD_BUS_WIDTH,
- ext_csd_bits[idx][1]);
+ EXT_CSD_BUS_WIDTH,
+ ext_csd_bits[idx][1],
+ 0);
}
if (err) {
printk(KERN_WARNING "%s: switch to bus width %d ddr %d "
@@ -668,20 +791,43 @@
1 << bus_width, ddr);
goto free_card;
} else if (ddr) {
+ /*
+ * eMMC cards can support 3.3V to 1.2V i/o (vccq)
+ * signaling.
+ *
+ * EXT_CSD_CARD_TYPE_DDR_1_8V means 3.3V or 1.8V vccq.
+ *
+ * 1.8V vccq at 3.3V core voltage (vcc) is not required
+ * in the JEDEC spec for DDR.
+ *
+ * Do not force change in vccq since we are obviously
+ * working and no change to vccq is needed.
+ *
+ * WARNING: eMMC rules are NOT the same as SD DDR
+ */
+ if (ddr == EXT_CSD_CARD_TYPE_DDR_1_2V) {
+ err = mmc_set_signal_voltage(host,
+ MMC_SIGNAL_VOLTAGE_120, 0);
+ if (err)
+ goto err;
+ }
mmc_card_set_ddr_mode(card);
- mmc_set_bus_width_ddr(card->host, bus_width, ddr);
+ mmc_set_timing(card->host, MMC_TIMING_UHS_DDR50);
+ mmc_set_bus_width(card->host, bus_width);
}
}
if (!oldcard)
host->card = card;
+ mmc_free_ext_csd(ext_csd);
return 0;
free_card:
if (!oldcard)
mmc_remove_card(card);
err:
+ mmc_free_ext_csd(ext_csd);
return err;
}
diff --git a/drivers/mmc/core/mmc_ops.c b/drivers/mmc/core/mmc_ops.c
index f3b22bf..845ce7c 100644
--- a/drivers/mmc/core/mmc_ops.c
+++ b/drivers/mmc/core/mmc_ops.c
@@ -23,12 +23,10 @@
static int _mmc_select_card(struct mmc_host *host, struct mmc_card *card)
{
int err;
- struct mmc_command cmd;
+ struct mmc_command cmd = {0};
BUG_ON(!host);
- memset(&cmd, 0, sizeof(struct mmc_command));
-
cmd.opcode = MMC_SELECT_CARD;
if (card) {
@@ -60,15 +58,13 @@
int mmc_card_sleepawake(struct mmc_host *host, int sleep)
{
- struct mmc_command cmd;
+ struct mmc_command cmd = {0};
struct mmc_card *card = host->card;
int err;
if (sleep)
mmc_deselect_cards(host);
- memset(&cmd, 0, sizeof(struct mmc_command));
-
cmd.opcode = MMC_SLEEP_AWAKE;
cmd.arg = card->rca << 16;
if (sleep)
@@ -97,7 +93,7 @@
int mmc_go_idle(struct mmc_host *host)
{
int err;
- struct mmc_command cmd;
+ struct mmc_command cmd = {0};
/*
* Non-SPI hosts need to prevent chipselect going active during
@@ -113,8 +109,6 @@
mmc_delay(1);
}
- memset(&cmd, 0, sizeof(struct mmc_command));
-
cmd.opcode = MMC_GO_IDLE_STATE;
cmd.arg = 0;
cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_NONE | MMC_CMD_BC;
@@ -135,13 +129,11 @@
int mmc_send_op_cond(struct mmc_host *host, u32 ocr, u32 *rocr)
{
- struct mmc_command cmd;
+ struct mmc_command cmd = {0};
int i, err = 0;
BUG_ON(!host);
- memset(&cmd, 0, sizeof(struct mmc_command));
-
cmd.opcode = MMC_SEND_OP_COND;
cmd.arg = mmc_host_is_spi(host) ? 0 : ocr;
cmd.flags = MMC_RSP_SPI_R1 | MMC_RSP_R3 | MMC_CMD_BCR;
@@ -178,13 +170,11 @@
int mmc_all_send_cid(struct mmc_host *host, u32 *cid)
{
int err;
- struct mmc_command cmd;
+ struct mmc_command cmd = {0};
BUG_ON(!host);
BUG_ON(!cid);
- memset(&cmd, 0, sizeof(struct mmc_command));
-
cmd.opcode = MMC_ALL_SEND_CID;
cmd.arg = 0;
cmd.flags = MMC_RSP_R2 | MMC_CMD_BCR;
@@ -201,13 +191,11 @@
int mmc_set_relative_addr(struct mmc_card *card)
{
int err;
- struct mmc_command cmd;
+ struct mmc_command cmd = {0};
BUG_ON(!card);
BUG_ON(!card->host);
- memset(&cmd, 0, sizeof(struct mmc_command));
-
cmd.opcode = MMC_SET_RELATIVE_ADDR;
cmd.arg = card->rca << 16;
cmd.flags = MMC_RSP_R1 | MMC_CMD_AC;
@@ -223,13 +211,11 @@
mmc_send_cxd_native(struct mmc_host *host, u32 arg, u32 *cxd, int opcode)
{
int err;
- struct mmc_command cmd;
+ struct mmc_command cmd = {0};
BUG_ON(!host);
BUG_ON(!cxd);
- memset(&cmd, 0, sizeof(struct mmc_command));
-
cmd.opcode = opcode;
cmd.arg = arg;
cmd.flags = MMC_RSP_R2 | MMC_CMD_AC;
@@ -247,9 +233,9 @@
mmc_send_cxd_data(struct mmc_card *card, struct mmc_host *host,
u32 opcode, void *buf, unsigned len)
{
- struct mmc_request mrq;
- struct mmc_command cmd;
- struct mmc_data data;
+ struct mmc_request mrq = {0};
+ struct mmc_command cmd = {0};
+ struct mmc_data data = {0};
struct scatterlist sg;
void *data_buf;
@@ -260,10 +246,6 @@
if (data_buf == NULL)
return -ENOMEM;
- memset(&mrq, 0, sizeof(struct mmc_request));
- memset(&cmd, 0, sizeof(struct mmc_command));
- memset(&data, 0, sizeof(struct mmc_data));
-
mrq.cmd = &cmd;
mrq.data = &data;
@@ -355,11 +337,9 @@
int mmc_spi_read_ocr(struct mmc_host *host, int highcap, u32 *ocrp)
{
- struct mmc_command cmd;
+ struct mmc_command cmd = {0};
int err;
- memset(&cmd, 0, sizeof(struct mmc_command));
-
cmd.opcode = MMC_SPI_READ_OCR;
cmd.arg = highcap ? (1 << 30) : 0;
cmd.flags = MMC_RSP_SPI_R3;
@@ -372,11 +352,9 @@
int mmc_spi_set_crc(struct mmc_host *host, int use_crc)
{
- struct mmc_command cmd;
+ struct mmc_command cmd = {0};
int err;
- memset(&cmd, 0, sizeof(struct mmc_command));
-
cmd.opcode = MMC_SPI_CRC_ON_OFF;
cmd.flags = MMC_RSP_SPI_R1;
cmd.arg = use_crc;
@@ -387,23 +365,34 @@
return err;
}
-int mmc_switch(struct mmc_card *card, u8 set, u8 index, u8 value)
+/**
+ * mmc_switch - modify EXT_CSD register
+ * @card: the MMC card associated with the data transfer
+ * @set: cmd set values
+ * @index: EXT_CSD register index
+ * @value: value to program into EXT_CSD register
+ * @timeout_ms: timeout (ms) for operation performed by register write,
+ * timeout of zero implies maximum possible timeout
+ *
+ * Modifies the EXT_CSD register for selected card.
+ */
+int mmc_switch(struct mmc_card *card, u8 set, u8 index, u8 value,
+ unsigned int timeout_ms)
{
int err;
- struct mmc_command cmd;
+ struct mmc_command cmd = {0};
u32 status;
BUG_ON(!card);
BUG_ON(!card->host);
- memset(&cmd, 0, sizeof(struct mmc_command));
-
cmd.opcode = MMC_SWITCH;
cmd.arg = (MMC_SWITCH_MODE_WRITE_BYTE << 24) |
(index << 16) |
(value << 8) |
set;
cmd.flags = MMC_RSP_SPI_R1B | MMC_RSP_R1B | MMC_CMD_AC;
+ cmd.cmd_timeout_ms = timeout_ms;
err = mmc_wait_for_cmd(card->host, &cmd, MMC_CMD_RETRIES);
if (err)
@@ -433,17 +422,16 @@
return 0;
}
+EXPORT_SYMBOL_GPL(mmc_switch);
int mmc_send_status(struct mmc_card *card, u32 *status)
{
int err;
- struct mmc_command cmd;
+ struct mmc_command cmd = {0};
BUG_ON(!card);
BUG_ON(!card->host);
- memset(&cmd, 0, sizeof(struct mmc_command));
-
cmd.opcode = MMC_SEND_STATUS;
if (!mmc_host_is_spi(card->host))
cmd.arg = card->rca << 16;
@@ -466,9 +454,9 @@
mmc_send_bus_test(struct mmc_card *card, struct mmc_host *host, u8 opcode,
u8 len)
{
- struct mmc_request mrq;
- struct mmc_command cmd;
- struct mmc_data data;
+ struct mmc_request mrq = {0};
+ struct mmc_command cmd = {0};
+ struct mmc_data data = {0};
struct scatterlist sg;
u8 *data_buf;
u8 *test_buf;
@@ -497,10 +485,6 @@
if (opcode == MMC_BUS_TEST_W)
memcpy(data_buf, test_buf, len);
- memset(&mrq, 0, sizeof(struct mmc_request));
- memset(&cmd, 0, sizeof(struct mmc_command));
- memset(&data, 0, sizeof(struct mmc_data));
-
mrq.cmd = &cmd;
mrq.data = &data;
cmd.opcode = opcode;
diff --git a/drivers/mmc/core/mmc_ops.h b/drivers/mmc/core/mmc_ops.h
index e6d44b8..9276946 100644
--- a/drivers/mmc/core/mmc_ops.h
+++ b/drivers/mmc/core/mmc_ops.h
@@ -20,7 +20,6 @@
int mmc_set_relative_addr(struct mmc_card *card);
int mmc_send_csd(struct mmc_card *card, u32 *csd);
int mmc_send_ext_csd(struct mmc_card *card, u8 *ext_csd);
-int mmc_switch(struct mmc_card *card, u8 set, u8 index, u8 value);
int mmc_send_status(struct mmc_card *card, u32 *status);
int mmc_send_cid(struct mmc_host *host, u32 *cid);
int mmc_spi_read_ocr(struct mmc_host *host, int highcap, u32 *ocrp);
diff --git a/drivers/mmc/core/quirks.c b/drivers/mmc/core/quirks.c
index 11118b74..3a59621 100644
--- a/drivers/mmc/core/quirks.c
+++ b/drivers/mmc/core/quirks.c
@@ -1,7 +1,8 @@
/*
- * This file contains work-arounds for many known sdio hardware
- * bugs.
+ * This file contains work-arounds for many known SD/MMC
+ * and SDIO hardware bugs.
*
+ * Copyright (c) 2011 Andrei Warkentin <andreiw@motorola.com>
* Copyright (c) 2011 Pierre Tardy <tardyp@gmail.com>
* Inspired from pci fixup code:
* Copyright (c) 1999 Martin Mares <mj@ucw.cz>
@@ -11,34 +12,14 @@
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/mmc/card.h>
-#include <linux/mod_devicetable.h>
-/*
- * The world is not perfect and supplies us with broken mmc/sdio devices.
- * For at least a part of these bugs we need a work-around
- */
+#ifndef SDIO_VENDOR_ID_TI
+#define SDIO_VENDOR_ID_TI 0x0097
+#endif
-struct mmc_fixup {
- u16 vendor, device; /* You can use SDIO_ANY_ID here of course */
- void (*vendor_fixup)(struct mmc_card *card, int data);
- int data;
-};
-
-/*
- * This hook just adds a quirk unconditionnally
- */
-static void __maybe_unused add_quirk(struct mmc_card *card, int data)
-{
- card->quirks |= data;
-}
-
-/*
- * This hook just removes a quirk unconditionnally
- */
-static void __maybe_unused remove_quirk(struct mmc_card *card, int data)
-{
- card->quirks &= ~data;
-}
+#ifndef SDIO_DEVICE_ID_TI_WL1271
+#define SDIO_DEVICE_ID_TI_WL1271 0x4076
+#endif
/*
* This hook just adds a quirk for all sdio devices
@@ -49,33 +30,47 @@
card->quirks |= data;
}
-#ifndef SDIO_VENDOR_ID_TI
-#define SDIO_VENDOR_ID_TI 0x0097
-#endif
-
-#ifndef SDIO_DEVICE_ID_TI_WL1271
-#define SDIO_DEVICE_ID_TI_WL1271 0x4076
-#endif
-
static const struct mmc_fixup mmc_fixup_methods[] = {
/* by default sdio devices are considered CLK_GATING broken */
/* good cards will be whitelisted as they are tested */
- { SDIO_ANY_ID, SDIO_ANY_ID,
- add_quirk_for_sdio_devices, MMC_QUIRK_BROKEN_CLK_GATING },
- { SDIO_VENDOR_ID_TI, SDIO_DEVICE_ID_TI_WL1271,
- remove_quirk, MMC_QUIRK_BROKEN_CLK_GATING },
- { 0 }
+ SDIO_FIXUP(SDIO_ANY_ID, SDIO_ANY_ID,
+ add_quirk_for_sdio_devices,
+ MMC_QUIRK_BROKEN_CLK_GATING),
+
+ SDIO_FIXUP(SDIO_VENDOR_ID_TI, SDIO_DEVICE_ID_TI_WL1271,
+ remove_quirk, MMC_QUIRK_BROKEN_CLK_GATING),
+
+ SDIO_FIXUP(SDIO_VENDOR_ID_TI, SDIO_DEVICE_ID_TI_WL1271,
+ add_quirk, MMC_QUIRK_NONSTD_FUNC_IF),
+
+ SDIO_FIXUP(SDIO_VENDOR_ID_TI, SDIO_DEVICE_ID_TI_WL1271,
+ add_quirk, MMC_QUIRK_DISABLE_CD),
+
+ END_FIXUP
};
-void mmc_fixup_device(struct mmc_card *card)
+void mmc_fixup_device(struct mmc_card *card, const struct mmc_fixup *table)
{
const struct mmc_fixup *f;
+ u64 rev = cid_rev_card(card);
- for (f = mmc_fixup_methods; f->vendor_fixup; f++) {
- if ((f->vendor == card->cis.vendor
- || f->vendor == (u16) SDIO_ANY_ID) &&
- (f->device == card->cis.device
- || f->device == (u16) SDIO_ANY_ID)) {
+ /* Non-core specific workarounds. */
+ if (!table)
+ table = mmc_fixup_methods;
+
+ for (f = table; f->vendor_fixup; f++) {
+ if ((f->manfid == CID_MANFID_ANY ||
+ f->manfid == card->cid.manfid) &&
+ (f->oemid == CID_OEMID_ANY ||
+ f->oemid == card->cid.oemid) &&
+ (f->name == CID_NAME_ANY ||
+ !strncmp(f->name, card->cid.prod_name,
+ sizeof(card->cid.prod_name))) &&
+ (f->cis_vendor == card->cis.vendor ||
+ f->cis_vendor == (u16) SDIO_ANY_ID) &&
+ (f->cis_device == card->cis.device ||
+ f->cis_device == (u16) SDIO_ANY_ID) &&
+ rev >= f->rev_start && rev <= f->rev_end) {
dev_dbg(&card->dev, "calling %pF\n", f->vendor_fixup);
f->vendor_fixup(card, f->data);
}
diff --git a/drivers/mmc/core/sd.c b/drivers/mmc/core/sd.c
index 6dac89f..ff27741 100644
--- a/drivers/mmc/core/sd.c
+++ b/drivers/mmc/core/sd.c
@@ -130,7 +130,7 @@
break;
case 1:
/*
- * This is a block-addressed SDHC card. Most
+ * This is a block-addressed SDHC or SDXC card. Most
* interesting fields are unused and have fixed
* values. To avoid getting tripped by buggy cards,
* we assume those fixed values ourselves.
@@ -144,6 +144,11 @@
e = UNSTUFF_BITS(resp, 96, 3);
csd->max_dtr = tran_exp[e] * tran_mant[m];
csd->cmdclass = UNSTUFF_BITS(resp, 84, 12);
+ csd->c_size = UNSTUFF_BITS(resp, 48, 22);
+
+ /* SDXC cards have a minimum C_SIZE of 0x00FFFF */
+ if (csd->c_size >= 0xFFFF)
+ mmc_card_set_ext_capacity(card);
m = UNSTUFF_BITS(resp, 48, 22);
csd->capacity = (1 + m) << 10;
@@ -189,12 +194,17 @@
scr->sda_vsn = UNSTUFF_BITS(resp, 56, 4);
scr->bus_widths = UNSTUFF_BITS(resp, 48, 4);
+ if (scr->sda_vsn == SCR_SPEC_VER_2)
+ /* Check if Physical Layer Spec v3.0 is supported */
+ scr->sda_spec3 = UNSTUFF_BITS(resp, 47, 1);
if (UNSTUFF_BITS(resp, 55, 1))
card->erased_byte = 0xFF;
else
card->erased_byte = 0x0;
+ if (scr->sda_spec3)
+ scr->cmds = UNSTUFF_BITS(resp, 32, 2);
return 0;
}
@@ -274,29 +284,74 @@
status = kmalloc(64, GFP_KERNEL);
if (!status) {
printk(KERN_ERR "%s: could not allocate a buffer for "
- "switch capabilities.\n", mmc_hostname(card->host));
+ "switch capabilities.\n",
+ mmc_hostname(card->host));
return -ENOMEM;
}
+ /* Find out the supported Bus Speed Modes. */
err = mmc_sd_switch(card, 0, 0, 1, status);
if (err) {
- /* If the host or the card can't do the switch,
- * fail more gracefully. */
- if ((err != -EINVAL)
- && (err != -ENOSYS)
- && (err != -EFAULT))
+ /*
+ * If the host or the card can't do the switch,
+ * fail more gracefully.
+ */
+ if (err != -EINVAL && err != -ENOSYS && err != -EFAULT)
goto out;
- printk(KERN_WARNING "%s: problem reading switch "
- "capabilities, performance might suffer.\n",
+ printk(KERN_WARNING "%s: problem reading Bus Speed modes.\n",
mmc_hostname(card->host));
err = 0;
goto out;
}
- if (status[13] & 0x02)
- card->sw_caps.hs_max_dtr = 50000000;
+ if (card->scr.sda_spec3) {
+ card->sw_caps.sd3_bus_mode = status[13];
+
+ /* Find out Driver Strengths supported by the card */
+ err = mmc_sd_switch(card, 0, 2, 1, status);
+ if (err) {
+ /*
+ * If the host or the card can't do the switch,
+ * fail more gracefully.
+ */
+ if (err != -EINVAL && err != -ENOSYS && err != -EFAULT)
+ goto out;
+
+ printk(KERN_WARNING "%s: problem reading "
+ "Driver Strength.\n",
+ mmc_hostname(card->host));
+ err = 0;
+
+ goto out;
+ }
+
+ card->sw_caps.sd3_drv_type = status[9];
+
+ /* Find out Current Limits supported by the card */
+ err = mmc_sd_switch(card, 0, 3, 1, status);
+ if (err) {
+ /*
+ * If the host or the card can't do the switch,
+ * fail more gracefully.
+ */
+ if (err != -EINVAL && err != -ENOSYS && err != -EFAULT)
+ goto out;
+
+ printk(KERN_WARNING "%s: problem reading "
+ "Current Limit.\n",
+ mmc_hostname(card->host));
+ err = 0;
+
+ goto out;
+ }
+
+ card->sw_caps.sd3_curr_limit = status[7];
+ } else {
+ if (status[13] & 0x02)
+ card->sw_caps.hs_max_dtr = 50000000;
+ }
out:
kfree(status);
@@ -352,6 +407,232 @@
return err;
}
+static int sd_select_driver_type(struct mmc_card *card, u8 *status)
+{
+ int host_drv_type = 0, card_drv_type = 0;
+ int err;
+
+ /*
+ * If the host doesn't support any of the Driver Types A,C or D,
+ * default Driver Type B is used.
+ */
+ if (!(card->host->caps & (MMC_CAP_DRIVER_TYPE_A | MMC_CAP_DRIVER_TYPE_C
+ | MMC_CAP_DRIVER_TYPE_D)))
+ return 0;
+
+ if (card->host->caps & MMC_CAP_DRIVER_TYPE_A) {
+ host_drv_type = MMC_SET_DRIVER_TYPE_A;
+ if (card->sw_caps.sd3_drv_type & SD_DRIVER_TYPE_A)
+ card_drv_type = MMC_SET_DRIVER_TYPE_A;
+ else if (card->sw_caps.sd3_drv_type & SD_DRIVER_TYPE_B)
+ card_drv_type = MMC_SET_DRIVER_TYPE_B;
+ else if (card->sw_caps.sd3_drv_type & SD_DRIVER_TYPE_C)
+ card_drv_type = MMC_SET_DRIVER_TYPE_C;
+ } else if (card->host->caps & MMC_CAP_DRIVER_TYPE_C) {
+ host_drv_type = MMC_SET_DRIVER_TYPE_C;
+ if (card->sw_caps.sd3_drv_type & SD_DRIVER_TYPE_C)
+ card_drv_type = MMC_SET_DRIVER_TYPE_C;
+ } else if (!(card->host->caps & MMC_CAP_DRIVER_TYPE_D)) {
+ /*
+ * If we are here, that means only the default driver type
+ * B is supported by the host.
+ */
+ host_drv_type = MMC_SET_DRIVER_TYPE_B;
+ if (card->sw_caps.sd3_drv_type & SD_DRIVER_TYPE_B)
+ card_drv_type = MMC_SET_DRIVER_TYPE_B;
+ else if (card->sw_caps.sd3_drv_type & SD_DRIVER_TYPE_C)
+ card_drv_type = MMC_SET_DRIVER_TYPE_C;
+ }
+
+ err = mmc_sd_switch(card, 1, 2, card_drv_type, status);
+ if (err)
+ return err;
+
+ if ((status[15] & 0xF) != card_drv_type) {
+ printk(KERN_WARNING "%s: Problem setting driver strength!\n",
+ mmc_hostname(card->host));
+ return 0;
+ }
+
+ mmc_set_driver_type(card->host, host_drv_type);
+
+ return 0;
+}
+
+static int sd_set_bus_speed_mode(struct mmc_card *card, u8 *status)
+{
+ unsigned int bus_speed = 0, timing = 0;
+ int err;
+
+ /*
+ * If the host doesn't support any of the UHS-I modes, fallback on
+ * default speed.
+ */
+ if (!(card->host->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
+ MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_DDR50)))
+ return 0;
+
+ if ((card->host->caps & MMC_CAP_UHS_SDR104) &&
+ (card->sw_caps.sd3_bus_mode & SD_MODE_UHS_SDR104)) {
+ bus_speed = UHS_SDR104_BUS_SPEED;
+ timing = MMC_TIMING_UHS_SDR104;
+ card->sw_caps.uhs_max_dtr = UHS_SDR104_MAX_DTR;
+ } else if ((card->host->caps & MMC_CAP_UHS_DDR50) &&
+ (card->sw_caps.sd3_bus_mode & SD_MODE_UHS_DDR50)) {
+ bus_speed = UHS_DDR50_BUS_SPEED;
+ timing = MMC_TIMING_UHS_DDR50;
+ card->sw_caps.uhs_max_dtr = UHS_DDR50_MAX_DTR;
+ } else if ((card->host->caps & (MMC_CAP_UHS_SDR104 |
+ MMC_CAP_UHS_SDR50)) && (card->sw_caps.sd3_bus_mode &
+ SD_MODE_UHS_SDR50)) {
+ bus_speed = UHS_SDR50_BUS_SPEED;
+ timing = MMC_TIMING_UHS_SDR50;
+ card->sw_caps.uhs_max_dtr = UHS_SDR50_MAX_DTR;
+ } else if ((card->host->caps & (MMC_CAP_UHS_SDR104 |
+ MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR25)) &&
+ (card->sw_caps.sd3_bus_mode & SD_MODE_UHS_SDR25)) {
+ bus_speed = UHS_SDR25_BUS_SPEED;
+ timing = MMC_TIMING_UHS_SDR25;
+ card->sw_caps.uhs_max_dtr = UHS_SDR25_MAX_DTR;
+ } else if ((card->host->caps & (MMC_CAP_UHS_SDR104 |
+ MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR25 |
+ MMC_CAP_UHS_SDR12)) && (card->sw_caps.sd3_bus_mode &
+ SD_MODE_UHS_SDR12)) {
+ bus_speed = UHS_SDR12_BUS_SPEED;
+ timing = MMC_TIMING_UHS_SDR12;
+ card->sw_caps.uhs_max_dtr = UHS_SDR12_MAX_DTR;
+ }
+
+ card->sd_bus_speed = bus_speed;
+ err = mmc_sd_switch(card, 1, 0, bus_speed, status);
+ if (err)
+ return err;
+
+ if ((status[16] & 0xF) != bus_speed)
+ printk(KERN_WARNING "%s: Problem setting bus speed mode!\n",
+ mmc_hostname(card->host));
+ else {
+ mmc_set_timing(card->host, timing);
+ mmc_set_clock(card->host, card->sw_caps.uhs_max_dtr);
+ }
+
+ return 0;
+}
+
+static int sd_set_current_limit(struct mmc_card *card, u8 *status)
+{
+ int current_limit = 0;
+ int err;
+
+ /*
+ * Current limit switch is only defined for SDR50, SDR104, and DDR50
+ * bus speed modes. For other bus speed modes, we set the default
+ * current limit of 200mA.
+ */
+ if ((card->sd_bus_speed == UHS_SDR50_BUS_SPEED) ||
+ (card->sd_bus_speed == UHS_SDR104_BUS_SPEED) ||
+ (card->sd_bus_speed == UHS_DDR50_BUS_SPEED)) {
+ if (card->host->caps & MMC_CAP_MAX_CURRENT_800) {
+ if (card->sw_caps.sd3_curr_limit & SD_MAX_CURRENT_800)
+ current_limit = SD_SET_CURRENT_LIMIT_800;
+ else if (card->sw_caps.sd3_curr_limit &
+ SD_MAX_CURRENT_600)
+ current_limit = SD_SET_CURRENT_LIMIT_600;
+ else if (card->sw_caps.sd3_curr_limit &
+ SD_MAX_CURRENT_400)
+ current_limit = SD_SET_CURRENT_LIMIT_400;
+ else if (card->sw_caps.sd3_curr_limit &
+ SD_MAX_CURRENT_200)
+ current_limit = SD_SET_CURRENT_LIMIT_200;
+ } else if (card->host->caps & MMC_CAP_MAX_CURRENT_600) {
+ if (card->sw_caps.sd3_curr_limit & SD_MAX_CURRENT_600)
+ current_limit = SD_SET_CURRENT_LIMIT_600;
+ else if (card->sw_caps.sd3_curr_limit &
+ SD_MAX_CURRENT_400)
+ current_limit = SD_SET_CURRENT_LIMIT_400;
+ else if (card->sw_caps.sd3_curr_limit &
+ SD_MAX_CURRENT_200)
+ current_limit = SD_SET_CURRENT_LIMIT_200;
+ } else if (card->host->caps & MMC_CAP_MAX_CURRENT_400) {
+ if (card->sw_caps.sd3_curr_limit & SD_MAX_CURRENT_400)
+ current_limit = SD_SET_CURRENT_LIMIT_400;
+ else if (card->sw_caps.sd3_curr_limit &
+ SD_MAX_CURRENT_200)
+ current_limit = SD_SET_CURRENT_LIMIT_200;
+ } else if (card->host->caps & MMC_CAP_MAX_CURRENT_200) {
+ if (card->sw_caps.sd3_curr_limit & SD_MAX_CURRENT_200)
+ current_limit = SD_SET_CURRENT_LIMIT_200;
+ }
+ } else
+ current_limit = SD_SET_CURRENT_LIMIT_200;
+
+ err = mmc_sd_switch(card, 1, 3, current_limit, status);
+ if (err)
+ return err;
+
+ if (((status[15] >> 4) & 0x0F) != current_limit)
+ printk(KERN_WARNING "%s: Problem setting current limit!\n",
+ mmc_hostname(card->host));
+
+ return 0;
+}
+
+/*
+ * UHS-I specific initialization procedure
+ */
+static int mmc_sd_init_uhs_card(struct mmc_card *card)
+{
+ int err;
+ u8 *status;
+
+ if (!card->scr.sda_spec3)
+ return 0;
+
+ if (!(card->csd.cmdclass & CCC_SWITCH))
+ return 0;
+
+ status = kmalloc(64, GFP_KERNEL);
+ if (!status) {
+ printk(KERN_ERR "%s: could not allocate a buffer for "
+ "switch capabilities.\n", mmc_hostname(card->host));
+ return -ENOMEM;
+ }
+
+ /* Set 4-bit bus width */
+ if ((card->host->caps & MMC_CAP_4_BIT_DATA) &&
+ (card->scr.bus_widths & SD_SCR_BUS_WIDTH_4)) {
+ err = mmc_app_set_bus_width(card, MMC_BUS_WIDTH_4);
+ if (err)
+ goto out;
+
+ mmc_set_bus_width(card->host, MMC_BUS_WIDTH_4);
+ }
+
+ /* Set the driver strength for the card */
+ err = sd_select_driver_type(card, status);
+ if (err)
+ goto out;
+
+ /* Set bus speed mode of the card */
+ err = sd_set_bus_speed_mode(card, status);
+ if (err)
+ goto out;
+
+ /* Set current limit for the card */
+ err = sd_set_current_limit(card, status);
+ if (err)
+ goto out;
+
+ /* SPI mode doesn't define CMD19 */
+ if (!mmc_host_is_spi(card->host) && card->host->ops->execute_tuning)
+ err = card->host->ops->execute_tuning(card->host);
+
+out:
+ kfree(status);
+
+ return err;
+}
+
MMC_DEV_ATTR(cid, "%08x%08x%08x%08x\n", card->raw_cid[0], card->raw_cid[1],
card->raw_cid[2], card->raw_cid[3]);
MMC_DEV_ATTR(csd, "%08x%08x%08x%08x\n", card->raw_csd[0], card->raw_csd[1],
@@ -400,7 +681,7 @@
/*
* Fetch CID from card.
*/
-int mmc_sd_get_cid(struct mmc_host *host, u32 ocr, u32 *cid)
+int mmc_sd_get_cid(struct mmc_host *host, u32 ocr, u32 *cid, u32 *rocr)
{
int err;
@@ -420,12 +701,39 @@
*/
err = mmc_send_if_cond(host, ocr);
if (!err)
- ocr |= 1 << 30;
+ ocr |= SD_OCR_CCS;
- err = mmc_send_app_op_cond(host, ocr, NULL);
+ /*
+ * If the host supports one of UHS-I modes, request the card
+ * to switch to 1.8V signaling level.
+ */
+ if (host->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 |
+ MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_DDR50))
+ ocr |= SD_OCR_S18R;
+
+ /* If the host can supply more than 150mA, XPC should be set to 1. */
+ if (host->caps & (MMC_CAP_SET_XPC_330 | MMC_CAP_SET_XPC_300 |
+ MMC_CAP_SET_XPC_180))
+ ocr |= SD_OCR_XPC;
+
+try_again:
+ err = mmc_send_app_op_cond(host, ocr, rocr);
if (err)
return err;
+ /*
+ * In case CCS and S18A in the response is set, start Signal Voltage
+ * Switch procedure. SPI mode doesn't support CMD11.
+ */
+ if (!mmc_host_is_spi(host) && rocr &&
+ ((*rocr & 0x41000000) == 0x41000000)) {
+ err = mmc_set_signal_voltage(host, MMC_SIGNAL_VOLTAGE_180, true);
+ if (err) {
+ ocr &= ~SD_OCR_S18R;
+ goto try_again;
+ }
+ }
+
if (mmc_host_is_spi(host))
err = mmc_send_cid(host, cid);
else
@@ -553,11 +861,12 @@
struct mmc_card *card;
int err;
u32 cid[4];
+ u32 rocr = 0;
BUG_ON(!host);
WARN_ON(!host->claimed);
- err = mmc_sd_get_cid(host, ocr, cid);
+ err = mmc_sd_get_cid(host, ocr, cid, &rocr);
if (err)
return err;
@@ -610,30 +919,47 @@
if (err)
goto free_card;
- /*
- * Attempt to change to high-speed (if supported)
- */
- err = mmc_sd_switch_hs(card);
- if (err > 0)
- mmc_sd_go_highspeed(card);
- else if (err)
- goto free_card;
-
- /*
- * Set bus speed.
- */
- mmc_set_clock(host, mmc_sd_get_max_clock(card));
-
- /*
- * Switch to wider bus (if supported).
- */
- if ((host->caps & MMC_CAP_4_BIT_DATA) &&
- (card->scr.bus_widths & SD_SCR_BUS_WIDTH_4)) {
- err = mmc_app_set_bus_width(card, MMC_BUS_WIDTH_4);
+ /* Initialization sequence for UHS-I cards */
+ if (rocr & SD_ROCR_S18A) {
+ err = mmc_sd_init_uhs_card(card);
if (err)
goto free_card;
- mmc_set_bus_width(host, MMC_BUS_WIDTH_4);
+ /* Card is an ultra-high-speed card */
+ mmc_sd_card_set_uhs(card);
+
+ /*
+ * Since initialization is now complete, enable preset
+ * value registers for UHS-I cards.
+ */
+ if (host->ops->enable_preset_value)
+ host->ops->enable_preset_value(host, true);
+ } else {
+ /*
+ * Attempt to change to high-speed (if supported)
+ */
+ err = mmc_sd_switch_hs(card);
+ if (err > 0)
+ mmc_sd_go_highspeed(card);
+ else if (err)
+ goto free_card;
+
+ /*
+ * Set bus speed.
+ */
+ mmc_set_clock(host, mmc_sd_get_max_clock(card));
+
+ /*
+ * Switch to wider bus (if supported).
+ */
+ if ((host->caps & MMC_CAP_4_BIT_DATA) &&
+ (card->scr.bus_widths & SD_SCR_BUS_WIDTH_4)) {
+ err = mmc_app_set_bus_width(card, MMC_BUS_WIDTH_4);
+ if (err)
+ goto free_card;
+
+ mmc_set_bus_width(host, MMC_BUS_WIDTH_4);
+ }
}
host->card = card;
@@ -773,6 +1099,15 @@
BUG_ON(!host);
WARN_ON(!host->claimed);
+ /* Make sure we are at 3.3V signalling voltage */
+ err = mmc_set_signal_voltage(host, MMC_SIGNAL_VOLTAGE_330, false);
+ if (err)
+ return err;
+
+ /* Disable preset value enable if already set since last time */
+ if (host->ops->enable_preset_value)
+ host->ops->enable_preset_value(host, false);
+
err = mmc_send_app_op_cond(host, 0, &ocr);
if (err)
return err;
diff --git a/drivers/mmc/core/sd.h b/drivers/mmc/core/sd.h
index 3d8800f..4b34b24 100644
--- a/drivers/mmc/core/sd.h
+++ b/drivers/mmc/core/sd.h
@@ -5,7 +5,7 @@
extern struct device_type sd_type;
-int mmc_sd_get_cid(struct mmc_host *host, u32 ocr, u32 *cid);
+int mmc_sd_get_cid(struct mmc_host *host, u32 ocr, u32 *cid, u32 *rocr);
int mmc_sd_get_csd(struct mmc_host *host, struct mmc_card *card);
void mmc_decode_cid(struct mmc_card *card);
int mmc_sd_setup_card(struct mmc_host *host, struct mmc_card *card,
diff --git a/drivers/mmc/core/sd_ops.c b/drivers/mmc/core/sd_ops.c
index 76af349..021fed1 100644
--- a/drivers/mmc/core/sd_ops.c
+++ b/drivers/mmc/core/sd_ops.c
@@ -21,10 +21,10 @@
#include "core.h"
#include "sd_ops.h"
-static int mmc_app_cmd(struct mmc_host *host, struct mmc_card *card)
+int mmc_app_cmd(struct mmc_host *host, struct mmc_card *card)
{
int err;
- struct mmc_command cmd;
+ struct mmc_command cmd = {0};
BUG_ON(!host);
BUG_ON(card && (card->host != host));
@@ -49,6 +49,7 @@
return 0;
}
+EXPORT_SYMBOL_GPL(mmc_app_cmd);
/**
* mmc_wait_for_app_cmd - start an application command and wait for
@@ -66,7 +67,7 @@
int mmc_wait_for_app_cmd(struct mmc_host *host, struct mmc_card *card,
struct mmc_command *cmd, int retries)
{
- struct mmc_request mrq;
+ struct mmc_request mrq = {0};
int i, err;
@@ -119,13 +120,11 @@
int mmc_app_set_bus_width(struct mmc_card *card, int width)
{
int err;
- struct mmc_command cmd;
+ struct mmc_command cmd = {0};
BUG_ON(!card);
BUG_ON(!card->host);
- memset(&cmd, 0, sizeof(struct mmc_command));
-
cmd.opcode = SD_APP_SET_BUS_WIDTH;
cmd.flags = MMC_RSP_R1 | MMC_CMD_AC;
@@ -149,13 +148,11 @@
int mmc_send_app_op_cond(struct mmc_host *host, u32 ocr, u32 *rocr)
{
- struct mmc_command cmd;
+ struct mmc_command cmd = {0};
int i, err = 0;
BUG_ON(!host);
- memset(&cmd, 0, sizeof(struct mmc_command));
-
cmd.opcode = SD_APP_OP_COND;
if (mmc_host_is_spi(host))
cmd.arg = ocr & (1 << 30); /* SPI only defines one bit */
@@ -194,7 +191,7 @@
int mmc_send_if_cond(struct mmc_host *host, u32 ocr)
{
- struct mmc_command cmd;
+ struct mmc_command cmd = {0};
int err;
static const u8 test_pattern = 0xAA;
u8 result_pattern;
@@ -226,13 +223,11 @@
int mmc_send_relative_addr(struct mmc_host *host, unsigned int *rca)
{
int err;
- struct mmc_command cmd;
+ struct mmc_command cmd = {0};
BUG_ON(!host);
BUG_ON(!rca);
- memset(&cmd, 0, sizeof(struct mmc_command));
-
cmd.opcode = SD_SEND_RELATIVE_ADDR;
cmd.arg = 0;
cmd.flags = MMC_RSP_R6 | MMC_CMD_BCR;
@@ -249,9 +244,9 @@
int mmc_app_send_scr(struct mmc_card *card, u32 *scr)
{
int err;
- struct mmc_request mrq;
- struct mmc_command cmd;
- struct mmc_data data;
+ struct mmc_request mrq = {0};
+ struct mmc_command cmd = {0};
+ struct mmc_data data = {0};
struct scatterlist sg;
void *data_buf;
@@ -272,10 +267,6 @@
if (data_buf == NULL)
return -ENOMEM;
- memset(&mrq, 0, sizeof(struct mmc_request));
- memset(&cmd, 0, sizeof(struct mmc_command));
- memset(&data, 0, sizeof(struct mmc_data));
-
mrq.cmd = &cmd;
mrq.data = &data;
@@ -312,9 +303,9 @@
int mmc_sd_switch(struct mmc_card *card, int mode, int group,
u8 value, u8 *resp)
{
- struct mmc_request mrq;
- struct mmc_command cmd;
- struct mmc_data data;
+ struct mmc_request mrq = {0};
+ struct mmc_command cmd = {0};
+ struct mmc_data data = {0};
struct scatterlist sg;
BUG_ON(!card);
@@ -325,10 +316,6 @@
mode = !!mode;
value &= 0xF;
- memset(&mrq, 0, sizeof(struct mmc_request));
- memset(&cmd, 0, sizeof(struct mmc_command));
- memset(&data, 0, sizeof(struct mmc_data));
-
mrq.cmd = &cmd;
mrq.data = &data;
@@ -361,9 +348,9 @@
int mmc_app_sd_status(struct mmc_card *card, void *ssr)
{
int err;
- struct mmc_request mrq;
- struct mmc_command cmd;
- struct mmc_data data;
+ struct mmc_request mrq = {0};
+ struct mmc_command cmd = {0};
+ struct mmc_data data = {0};
struct scatterlist sg;
BUG_ON(!card);
@@ -376,10 +363,6 @@
if (err)
return err;
- memset(&mrq, 0, sizeof(struct mmc_request));
- memset(&cmd, 0, sizeof(struct mmc_command));
- memset(&data, 0, sizeof(struct mmc_data));
-
mrq.cmd = &cmd;
mrq.data = &data;
diff --git a/drivers/mmc/core/sdio.c b/drivers/mmc/core/sdio.c
index db0f0b4..4d0c15b 100644
--- a/drivers/mmc/core/sdio.c
+++ b/drivers/mmc/core/sdio.c
@@ -16,6 +16,7 @@
#include <linux/mmc/card.h>
#include <linux/mmc/sdio.h>
#include <linux/mmc/sdio_func.h>
+#include <linux/mmc/sdio_ids.h>
#include "core.h"
#include "bus.h"
@@ -31,6 +32,11 @@
int ret;
unsigned char data;
+ if (mmc_card_nonstd_func_interface(func->card)) {
+ func->class = SDIO_CLASS_NONE;
+ return 0;
+ }
+
ret = mmc_io_rw_direct(func->card, 0, 0,
SDIO_FBR_BASE(func->num) + SDIO_FBR_STD_IF, 0, &data);
if (ret)
@@ -181,7 +187,7 @@
int ret;
u8 ctrl;
- if (!card->cccr.disable_cd)
+ if (!mmc_card_disable_cd(card))
return 0;
ret = mmc_io_rw_direct(card, 0, 0, SDIO_CCCR_IF, 0, &ctrl);
@@ -363,8 +369,8 @@
goto err;
}
- if (ocr & R4_MEMORY_PRESENT
- && mmc_sd_get_cid(host, host->ocr & ocr, card->raw_cid) == 0) {
+ if ((ocr & R4_MEMORY_PRESENT) &&
+ mmc_sd_get_cid(host, host->ocr & ocr, card->raw_cid, NULL) == 0) {
card->type = MMC_TYPE_SD_COMBO;
if (oldcard && (oldcard->type != MMC_TYPE_SD_COMBO ||
@@ -466,7 +472,7 @@
card = oldcard;
}
- mmc_fixup_device(card);
+ mmc_fixup_device(card, NULL);
if (card->type == MMC_TYPE_SD_COMBO) {
err = mmc_sd_setup_card(host, card, oldcard != NULL);
@@ -625,7 +631,7 @@
}
}
- if (!err && host->pm_flags & MMC_PM_KEEP_POWER) {
+ if (!err && mmc_card_keep_power(host) && mmc_card_wake_sdio_irq(host)) {
mmc_claim_host(host);
sdio_disable_wide(host->card);
mmc_release_host(host);
@@ -645,10 +651,10 @@
mmc_claim_host(host);
/* No need to reinitialize powered-resumed nonremovable cards */
- if (mmc_card_is_removable(host) || !mmc_card_is_powered_resumed(host))
+ if (mmc_card_is_removable(host) || !mmc_card_keep_power(host))
err = mmc_sdio_init_card(host, host->ocr, host->card,
- (host->pm_flags & MMC_PM_KEEP_POWER));
- else if (mmc_card_is_powered_resumed(host)) {
+ mmc_card_keep_power(host));
+ else if (mmc_card_keep_power(host) && mmc_card_wake_sdio_irq(host)) {
/* We may have switched to 1-bit mode during suspend */
err = sdio_enable_4bit_bus(host->card);
if (err > 0) {
@@ -691,7 +697,7 @@
mmc_claim_host(host);
ret = mmc_sdio_init_card(host, host->ocr, host->card,
- (host->pm_flags & MMC_PM_KEEP_POWER));
+ mmc_card_keep_power(host));
if (!ret && host->sdio_irqs)
mmc_signal_sdio_irq(host);
mmc_release_host(host);
diff --git a/drivers/mmc/core/sdio_irq.c b/drivers/mmc/core/sdio_irq.c
index b300161..03ead02 100644
--- a/drivers/mmc/core/sdio_irq.c
+++ b/drivers/mmc/core/sdio_irq.c
@@ -31,6 +31,17 @@
{
int i, ret, count;
unsigned char pending;
+ struct sdio_func *func;
+
+ /*
+ * Optimization, if there is only 1 function interrupt registered
+ * call irq handler directly
+ */
+ func = card->sdio_single_irq;
+ if (func) {
+ func->irq_handler(func);
+ return 1;
+ }
ret = mmc_io_rw_direct(card, 0, 0, SDIO_CCCR_INTx, 0, &pending);
if (ret) {
@@ -42,7 +53,7 @@
count = 0;
for (i = 1; i <= 7; i++) {
if (pending & (1 << i)) {
- struct sdio_func *func = card->sdio_func[i - 1];
+ func = card->sdio_func[i - 1];
if (!func) {
printk(KERN_WARNING "%s: pending IRQ for "
"non-existent function\n",
@@ -186,6 +197,24 @@
return 0;
}
+/* If there is only 1 function registered set sdio_single_irq */
+static void sdio_single_irq_set(struct mmc_card *card)
+{
+ struct sdio_func *func;
+ int i;
+
+ card->sdio_single_irq = NULL;
+ if ((card->host->caps & MMC_CAP_SDIO_IRQ) &&
+ card->host->sdio_irqs == 1)
+ for (i = 0; i < card->sdio_funcs; i++) {
+ func = card->sdio_func[i];
+ if (func && func->irq_handler) {
+ card->sdio_single_irq = func;
+ break;
+ }
+ }
+}
+
/**
* sdio_claim_irq - claim the IRQ for a SDIO function
* @func: SDIO function
@@ -227,6 +256,7 @@
ret = sdio_card_irq_get(func->card);
if (ret)
func->irq_handler = NULL;
+ sdio_single_irq_set(func->card);
return ret;
}
@@ -251,6 +281,7 @@
if (func->irq_handler) {
func->irq_handler = NULL;
sdio_card_irq_put(func->card);
+ sdio_single_irq_set(func->card);
}
ret = mmc_io_rw_direct(func->card, 0, 0, SDIO_CCCR_IENx, 0, ®);
diff --git a/drivers/mmc/core/sdio_ops.c b/drivers/mmc/core/sdio_ops.c
index dea36d9..f087d87 100644
--- a/drivers/mmc/core/sdio_ops.c
+++ b/drivers/mmc/core/sdio_ops.c
@@ -21,13 +21,11 @@
int mmc_send_io_op_cond(struct mmc_host *host, u32 ocr, u32 *rocr)
{
- struct mmc_command cmd;
+ struct mmc_command cmd = {0};
int i, err = 0;
BUG_ON(!host);
- memset(&cmd, 0, sizeof(struct mmc_command));
-
cmd.opcode = SD_IO_SEND_OP_COND;
cmd.arg = ocr;
cmd.flags = MMC_RSP_SPI_R4 | MMC_RSP_R4 | MMC_CMD_BCR;
@@ -70,7 +68,7 @@
static int mmc_io_rw_direct_host(struct mmc_host *host, int write, unsigned fn,
unsigned addr, u8 in, u8 *out)
{
- struct mmc_command cmd;
+ struct mmc_command cmd = {0};
int err;
BUG_ON(!host);
@@ -80,8 +78,6 @@
if (addr & ~0x1FFFF)
return -EINVAL;
- memset(&cmd, 0, sizeof(struct mmc_command));
-
cmd.opcode = SD_IO_RW_DIRECT;
cmd.arg = write ? 0x80000000 : 0x00000000;
cmd.arg |= fn << 28;
@@ -125,9 +121,9 @@
int mmc_io_rw_extended(struct mmc_card *card, int write, unsigned fn,
unsigned addr, int incr_addr, u8 *buf, unsigned blocks, unsigned blksz)
{
- struct mmc_request mrq;
- struct mmc_command cmd;
- struct mmc_data data;
+ struct mmc_request mrq = {0};
+ struct mmc_command cmd = {0};
+ struct mmc_data data = {0};
struct scatterlist sg;
BUG_ON(!card);
@@ -140,10 +136,6 @@
if (addr & ~0x1FFFF)
return -EINVAL;
- memset(&mrq, 0, sizeof(struct mmc_request));
- memset(&cmd, 0, sizeof(struct mmc_command));
- memset(&data, 0, sizeof(struct mmc_data));
-
mrq.cmd = &cmd;
mrq.data = &data;
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 94df405..56dbf3f 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -154,7 +154,7 @@
If unsure, say N.
config MMC_SDHCI_TEGRA
- tristate "SDHCI platform support for the Tegra SD/MMC Controller"
+ bool "SDHCI platform support for the Tegra SD/MMC Controller"
depends on MMC_SDHCI_PLTFM && ARCH_TEGRA
select MMC_SDHCI_IO_ACCESSORS
help
@@ -535,6 +535,37 @@
If you have a board based on such a SoC and with a SD/MMC slot,
say Y or M here.
+config MMC_VUB300
+ tristate "VUB300 USB to SDIO/SD/MMC Host Controller support"
+ depends on USB
+ help
+ This selects support for Elan Digital Systems' VUB300 chip.
+
+ The VUB300 is a USB-SDIO Host Controller Interface chip
+ that enables the host computer to use SDIO/SD/MMC cards
+ via a USB 2.0 or USB 1.1 host.
+
+ The VUB300 chip will be found in both physically separate
+ USB to SDIO/SD/MMC adapters and embedded on some motherboards.
+
+ The VUB300 chip supports SD and MMC memory cards in addition
+ to single and multifunction SDIO cards.
+
+ Some SDIO cards will need a firmware file to be loaded and
+ sent to VUB300 chip in order to achieve better data throughput.
+ Download these "Offload Pseudocode" from Elan Digital Systems'
+ web-site http://www.elandigitalsystems.com/support/downloads.php
+ and put them in /lib/firmware. Note that without these additional
+ firmware files the VUB300 chip will still function, but not at
+ the best obtainable data rate.
+
+ To compile this mmc host controller driver as a module,
+ choose M here: the module will be called vub300.
+
+ If you have a computer with an embedded VUB300 chip
+ or if you intend connecting a USB adapter based on a
+ VUB300 chip say Y or M here.
+
config MMC_USHC
tristate "USB SD Host Controller (USHC) support"
depends on USB
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index 4f1df0a..58a5cf7 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -41,6 +41,7 @@
obj-$(CONFIG_MMC_DW) += dw_mmc.o
obj-$(CONFIG_MMC_SH_MMCIF) += sh_mmcif.o
obj-$(CONFIG_MMC_JZ4740) += jz4740_mmc.o
+obj-$(CONFIG_MMC_VUB300) += vub300.o
obj-$(CONFIG_MMC_USHC) += ushc.o
obj-$(CONFIG_MMC_SDHCI_PLTFM) += sdhci-platform.o
diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
index 87e1f57..66dcddb 100644
--- a/drivers/mmc/host/dw_mmc.c
+++ b/drivers/mmc/host/dw_mmc.c
@@ -1769,9 +1769,6 @@
int i, ret;
struct dw_mci *host = platform_get_drvdata(pdev);
- if (host->vmmc)
- regulator_enable(host->vmmc);
-
for (i = 0; i < host->num_slots; i++) {
struct dw_mci_slot *slot = host->slot[i];
if (!slot)
@@ -1798,6 +1795,9 @@
int i, ret;
struct dw_mci *host = platform_get_drvdata(pdev);
+ if (host->vmmc)
+ regulator_enable(host->vmmc);
+
if (host->dma_ops->init)
host->dma_ops->init(host);
diff --git a/drivers/mmc/host/mmci.c b/drivers/mmc/host/mmci.c
index b4a7e4f..4941e06 100644
--- a/drivers/mmc/host/mmci.c
+++ b/drivers/mmc/host/mmci.c
@@ -77,7 +77,7 @@
static struct variant_data variant_u300 = {
.fifosize = 16 * 4,
.fifohalfsize = 8 * 4,
- .clkreg_enable = 1 << 13, /* HWFCEN */
+ .clkreg_enable = MCI_ST_U300_HWFCEN,
.datalength_bits = 16,
.sdio = true,
};
@@ -86,7 +86,7 @@
.fifosize = 30 * 4,
.fifohalfsize = 8 * 4,
.clkreg = MCI_CLK_ENABLE,
- .clkreg_enable = 1 << 14, /* HWFCEN */
+ .clkreg_enable = MCI_ST_UX500_HWFCEN,
.datalength_bits = 24,
.sdio = true,
.st_clkdiv = true,
@@ -103,6 +103,8 @@
if (desired) {
if (desired >= host->mclk) {
clk = MCI_CLK_BYPASS;
+ if (variant->st_clkdiv)
+ clk |= MCI_ST_UX500_NEG_EDGE;
host->cclk = host->mclk;
} else if (variant->st_clkdiv) {
/*
diff --git a/drivers/mmc/host/mmci.h b/drivers/mmc/host/mmci.h
index ec9a7bc6..bb32e21 100644
--- a/drivers/mmc/host/mmci.h
+++ b/drivers/mmc/host/mmci.h
@@ -11,23 +11,33 @@
#define MCI_PWR_OFF 0x00
#define MCI_PWR_UP 0x02
#define MCI_PWR_ON 0x03
-#define MCI_DATA2DIREN (1 << 2)
-#define MCI_CMDDIREN (1 << 3)
-#define MCI_DATA0DIREN (1 << 4)
-#define MCI_DATA31DIREN (1 << 5)
#define MCI_OD (1 << 6)
#define MCI_ROD (1 << 7)
-/* The ST Micro version does not have ROD */
-#define MCI_FBCLKEN (1 << 7)
-#define MCI_DATA74DIREN (1 << 8)
+/*
+ * The ST Micro version does not have ROD and reuse the voltage registers
+ * for direction settings
+ */
+#define MCI_ST_DATA2DIREN (1 << 2)
+#define MCI_ST_CMDDIREN (1 << 3)
+#define MCI_ST_DATA0DIREN (1 << 4)
+#define MCI_ST_DATA31DIREN (1 << 5)
+#define MCI_ST_FBCLKEN (1 << 7)
+#define MCI_ST_DATA74DIREN (1 << 8)
#define MMCICLOCK 0x004
#define MCI_CLK_ENABLE (1 << 8)
#define MCI_CLK_PWRSAVE (1 << 9)
#define MCI_CLK_BYPASS (1 << 10)
#define MCI_4BIT_BUS (1 << 11)
-/* 8bit wide buses supported in ST Micro versions */
+/*
+ * 8bit wide buses, hardware flow contronl, negative edges and clock inversion
+ * supported in ST Micro U300 and Ux500 versions
+ */
#define MCI_ST_8BIT_BUS (1 << 12)
+#define MCI_ST_U300_HWFCEN (1 << 13)
+#define MCI_ST_UX500_NEG_EDGE (1 << 13)
+#define MCI_ST_UX500_HWFCEN (1 << 14)
+#define MCI_ST_UX500_CLK_INV (1 << 15)
#define MMCIARGUMENT 0x008
#define MMCICOMMAND 0x00c
@@ -88,8 +98,9 @@
#define MCI_RXFIFOEMPTY (1 << 19)
#define MCI_TXDATAAVLBL (1 << 20)
#define MCI_RXDATAAVLBL (1 << 21)
-#define MCI_SDIOIT (1 << 22)
-#define MCI_CEATAEND (1 << 23)
+/* Extended status bits for the ST Micro variants */
+#define MCI_ST_SDIOIT (1 << 22)
+#define MCI_ST_CEATAEND (1 << 23)
#define MMCICLEAR 0x038
#define MCI_CMDCRCFAILCLR (1 << 0)
@@ -102,8 +113,9 @@
#define MCI_CMDSENTCLR (1 << 7)
#define MCI_DATAENDCLR (1 << 8)
#define MCI_DATABLOCKENDCLR (1 << 10)
-#define MCI_SDIOITC (1 << 22)
-#define MCI_CEATAENDC (1 << 23)
+/* Extended status bits for the ST Micro variants */
+#define MCI_ST_SDIOITC (1 << 22)
+#define MCI_ST_CEATAENDC (1 << 23)
#define MMCIMASK0 0x03c
#define MCI_CMDCRCFAILMASK (1 << 0)
@@ -127,8 +139,9 @@
#define MCI_RXFIFOEMPTYMASK (1 << 19)
#define MCI_TXDATAAVLBLMASK (1 << 20)
#define MCI_RXDATAAVLBLMASK (1 << 21)
-#define MCI_SDIOITMASK (1 << 22)
-#define MCI_CEATAENDMASK (1 << 23)
+/* Extended status bits for the ST Micro variants */
+#define MCI_ST_SDIOITMASK (1 << 22)
+#define MCI_ST_CEATAENDMASK (1 << 23)
#define MMCIMASK1 0x040
#define MMCIFIFOCNT 0x048
diff --git a/drivers/mmc/host/sdhci-pci.c b/drivers/mmc/host/sdhci-pci.c
index f8b5f37..936bbca 100644
--- a/drivers/mmc/host/sdhci-pci.c
+++ b/drivers/mmc/host/sdhci-pci.c
@@ -18,11 +18,9 @@
#include <linux/dma-mapping.h>
#include <linux/slab.h>
#include <linux/device.h>
-
#include <linux/mmc/host.h>
-
-#include <asm/scatterlist.h>
-#include <asm/io.h>
+#include <linux/scatterlist.h>
+#include <linux/io.h>
#include "sdhci.h"
@@ -46,14 +44,14 @@
struct sdhci_pci_fixes {
unsigned int quirks;
- int (*probe)(struct sdhci_pci_chip*);
+ int (*probe) (struct sdhci_pci_chip *);
- int (*probe_slot)(struct sdhci_pci_slot*);
- void (*remove_slot)(struct sdhci_pci_slot*, int);
+ int (*probe_slot) (struct sdhci_pci_slot *);
+ void (*remove_slot) (struct sdhci_pci_slot *, int);
- int (*suspend)(struct sdhci_pci_chip*,
+ int (*suspend) (struct sdhci_pci_chip *,
pm_message_t);
- int (*resume)(struct sdhci_pci_chip*);
+ int (*resume) (struct sdhci_pci_chip *);
};
struct sdhci_pci_slot {
@@ -329,6 +327,11 @@
return ret;
}
+ /* quirk for unsable RO-detection on JM388 chips */
+ if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_SD ||
+ chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD)
+ chip->quirks |= SDHCI_QUIRK_UNSTABLE_RO_DETECT;
+
return 0;
}
@@ -402,7 +405,7 @@
if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
- for (i = 0;i < chip->num_slots;i++)
+ for (i = 0; i < chip->num_slots; i++)
jmicron_enable_mmc(chip->slots[i]->host, 0);
}
@@ -415,7 +418,7 @@
if (chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB38X_MMC ||
chip->pdev->device == PCI_DEVICE_ID_JMICRON_JMB388_ESD) {
- for (i = 0;i < chip->num_slots;i++)
+ for (i = 0; i < chip->num_slots; i++)
jmicron_enable_mmc(chip->slots[i]->host, 1);
}
@@ -798,7 +801,7 @@
#ifdef CONFIG_PM
-static int sdhci_pci_suspend (struct pci_dev *pdev, pm_message_t state)
+static int sdhci_pci_suspend(struct pci_dev *pdev, pm_message_t state)
{
struct sdhci_pci_chip *chip;
struct sdhci_pci_slot *slot;
@@ -810,7 +813,7 @@
if (!chip)
return 0;
- for (i = 0;i < chip->num_slots;i++) {
+ for (i = 0; i < chip->num_slots; i++) {
slot = chip->slots[i];
if (!slot)
continue;
@@ -818,7 +821,7 @@
ret = sdhci_suspend_host(slot->host, state);
if (ret) {
- for (i--;i >= 0;i--)
+ for (i--; i >= 0; i--)
sdhci_resume_host(chip->slots[i]->host);
return ret;
}
@@ -833,7 +836,7 @@
if (chip->fixes && chip->fixes->suspend) {
ret = chip->fixes->suspend(chip, state);
if (ret) {
- for (i = chip->num_slots - 1;i >= 0;i--)
+ for (i = chip->num_slots - 1; i >= 0; i--)
sdhci_resume_host(chip->slots[i]->host);
return ret;
}
@@ -855,7 +858,7 @@
return 0;
}
-static int sdhci_pci_resume (struct pci_dev *pdev)
+static int sdhci_pci_resume(struct pci_dev *pdev)
{
struct sdhci_pci_chip *chip;
struct sdhci_pci_slot *slot;
@@ -877,7 +880,7 @@
return ret;
}
- for (i = 0;i < chip->num_slots;i++) {
+ for (i = 0; i < chip->num_slots; i++) {
slot = chip->slots[i];
if (!slot)
continue;
@@ -1059,7 +1062,7 @@
}
chip->pdev = pdev;
- chip->fixes = (const struct sdhci_pci_fixes*)ent->driver_data;
+ chip->fixes = (const struct sdhci_pci_fixes *)ent->driver_data;
if (chip->fixes)
chip->quirks = chip->fixes->quirks;
chip->num_slots = slots;
@@ -1074,10 +1077,10 @@
slots = chip->num_slots; /* Quirk may have changed this */
- for (i = 0;i < slots;i++) {
+ for (i = 0; i < slots; i++) {
slot = sdhci_pci_probe_slot(pdev, chip, first_bar + i);
if (IS_ERR(slot)) {
- for (i--;i >= 0;i--)
+ for (i--; i >= 0; i--)
sdhci_pci_remove_slot(chip->slots[i]);
ret = PTR_ERR(slot);
goto free;
@@ -1105,7 +1108,7 @@
chip = pci_get_drvdata(pdev);
if (chip) {
- for (i = 0;i < chip->num_slots; i++)
+ for (i = 0; i < chip->num_slots; i++)
sdhci_pci_remove_slot(chip->slots[i]);
pci_set_drvdata(pdev, NULL);
@@ -1116,9 +1119,9 @@
}
static struct pci_driver sdhci_driver = {
- .name = "sdhci-pci",
+ .name = "sdhci-pci",
.id_table = pci_ids,
- .probe = sdhci_pci_probe,
+ .probe = sdhci_pci_probe,
.remove = __devexit_p(sdhci_pci_remove),
.suspend = sdhci_pci_suspend,
.resume = sdhci_pci_resume,
diff --git a/drivers/mmc/host/sdhci-pxa.c b/drivers/mmc/host/sdhci-pxa.c
index 5a61208..089c9a6 100644
--- a/drivers/mmc/host/sdhci-pxa.c
+++ b/drivers/mmc/host/sdhci-pxa.c
@@ -69,7 +69,45 @@
}
}
+static int set_uhs_signaling(struct sdhci_host *host, unsigned int uhs)
+{
+ u16 ctrl_2;
+
+ /*
+ * Set V18_EN -- UHS modes do not work without this.
+ * does not change signaling voltage
+ */
+ ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+
+ /* Select Bus Speed Mode for host */
+ ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
+ switch (uhs) {
+ case MMC_TIMING_UHS_SDR12:
+ ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
+ break;
+ case MMC_TIMING_UHS_SDR25:
+ ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
+ break;
+ case MMC_TIMING_UHS_SDR50:
+ ctrl_2 |= SDHCI_CTRL_UHS_SDR50 | SDHCI_CTRL_VDD_180;
+ break;
+ case MMC_TIMING_UHS_SDR104:
+ ctrl_2 |= SDHCI_CTRL_UHS_SDR104 | SDHCI_CTRL_VDD_180;
+ break;
+ case MMC_TIMING_UHS_DDR50:
+ ctrl_2 |= SDHCI_CTRL_UHS_DDR50 | SDHCI_CTRL_VDD_180;
+ break;
+ }
+
+ sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
+ pr_debug("%s:%s uhs = %d, ctrl_2 = %04X\n",
+ __func__, mmc_hostname(host->mmc), uhs, ctrl_2);
+
+ return 0;
+}
+
static struct sdhci_ops sdhci_pxa_ops = {
+ .set_uhs_signaling = set_uhs_signaling,
.set_clock = set_clock,
};
@@ -136,11 +174,19 @@
host->hw_name = "MMC";
host->ops = &sdhci_pxa_ops;
host->irq = irq;
- host->quirks = SDHCI_QUIRK_BROKEN_ADMA | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL;
+ host->quirks = SDHCI_QUIRK_BROKEN_ADMA
+ | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
+ | SDHCI_QUIRK_32BIT_DMA_ADDR
+ | SDHCI_QUIRK_32BIT_DMA_SIZE
+ | SDHCI_QUIRK_32BIT_ADMA_SIZE
+ | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC;
if (pdata->quirks)
host->quirks |= pdata->quirks;
+ /* enable 1/8V DDR capable */
+ host->mmc->caps |= MMC_CAP_1_8V_DDR;
+
/* If slot design supports 8 bit data, indicate this to MMC. */
if (pdata->flags & PXA_FLAG_SD_8_BIT_CAPABLE_SLOT)
host->mmc->caps |= MMC_CAP_8_BIT_DATA;
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c
index f7e1f96..343c97e 100644
--- a/drivers/mmc/host/sdhci-tegra.c
+++ b/drivers/mmc/host/sdhci-tegra.c
@@ -184,6 +184,8 @@
clk_enable(clk);
pltfm_host->clk = clk;
+ host->mmc->pm_caps = plat->pm_flags;
+
if (plat->is_8bit)
host->mmc->caps |= MMC_CAP_8_BIT_DATA;
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c
index 5d20661..58d5436 100644
--- a/drivers/mmc/host/sdhci.c
+++ b/drivers/mmc/host/sdhci.c
@@ -38,13 +38,16 @@
#define SDHCI_USE_LEDS_CLASS
#endif
+#define MAX_TUNING_LOOP 40
+
static unsigned int debug_quirks = 0;
-static void sdhci_prepare_data(struct sdhci_host *, struct mmc_data *);
static void sdhci_finish_data(struct sdhci_host *);
static void sdhci_send_command(struct sdhci_host *, struct mmc_command *);
static void sdhci_finish_command(struct sdhci_host *);
+static int sdhci_execute_tuning(struct mmc_host *mmc);
+static void sdhci_tuning_timer(unsigned long data);
static void sdhci_dumpregs(struct sdhci_host *host)
{
@@ -84,6 +87,8 @@
printk(KERN_DEBUG DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n",
sdhci_readw(host, SDHCI_COMMAND),
sdhci_readl(host, SDHCI_MAX_CURRENT));
+ printk(KERN_DEBUG DRIVER_NAME ": Host ctl2: 0x%08x\n",
+ sdhci_readw(host, SDHCI_HOST_CONTROL2));
if (host->flags & SDHCI_USE_ADMA)
printk(KERN_DEBUG DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n",
@@ -157,6 +162,9 @@
if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
ier = sdhci_readl(host, SDHCI_INT_ENABLE);
+ if (host->ops->platform_reset_enter)
+ host->ops->platform_reset_enter(host, mask);
+
sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
if (mask & SDHCI_RESET_ALL)
@@ -177,6 +185,9 @@
mdelay(1);
}
+ if (host->ops->platform_reset_exit)
+ host->ops->platform_reset_exit(host, mask);
+
if (host->quirks & SDHCI_QUIRK_RESTORE_IRQS_AFTER_RESET)
sdhci_clear_set_irqs(host, SDHCI_INT_ALL_MASK, ier);
}
@@ -591,9 +602,10 @@
data->sg_len, direction);
}
-static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_data *data)
+static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd)
{
u8 count;
+ struct mmc_data *data = cmd->data;
unsigned target_timeout, current_timeout;
/*
@@ -605,9 +617,16 @@
if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL)
return 0xE;
+ /* Unspecified timeout, assume max */
+ if (!data && !cmd->cmd_timeout_ms)
+ return 0xE;
+
/* timeout in us */
- target_timeout = data->timeout_ns / 1000 +
- data->timeout_clks / host->clock;
+ if (!data)
+ target_timeout = cmd->cmd_timeout_ms * 1000;
+ else
+ target_timeout = data->timeout_ns / 1000 +
+ data->timeout_clks / host->clock;
if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)
host->timeout_clk = host->clock / 1000;
@@ -622,6 +641,7 @@
* =>
* (1) / (2) > 2^6
*/
+ BUG_ON(!host->timeout_clk);
count = 0;
current_timeout = (1 << 13) * 1000 / host->timeout_clk;
while (current_timeout < target_timeout) {
@@ -632,8 +652,8 @@
}
if (count >= 0xF) {
- printk(KERN_WARNING "%s: Too large timeout requested!\n",
- mmc_hostname(host->mmc));
+ printk(KERN_WARNING "%s: Too large timeout requested for CMD%d!\n",
+ mmc_hostname(host->mmc), cmd->opcode);
count = 0xE;
}
@@ -651,15 +671,21 @@
sdhci_clear_set_irqs(host, dma_irqs, pio_irqs);
}
-static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_data *data)
+static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd)
{
u8 count;
u8 ctrl;
+ struct mmc_data *data = cmd->data;
int ret;
WARN_ON(host->data);
- if (data == NULL)
+ if (data || (cmd->flags & MMC_RSP_BUSY)) {
+ count = sdhci_calc_timeout(host, cmd);
+ sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
+ }
+
+ if (!data)
return;
/* Sanity checks */
@@ -669,9 +695,7 @@
host->data = data;
host->data_early = 0;
-
- count = sdhci_calc_timeout(host, data);
- sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL);
+ host->data->bytes_xfered = 0;
if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))
host->flags |= SDHCI_REQ_USE_DMA;
@@ -807,15 +831,17 @@
sdhci_set_transfer_irqs(host);
- /* We do not handle DMA boundaries, so set it to max (512 KiB) */
- sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, data->blksz), SDHCI_BLOCK_SIZE);
+ /* Set the DMA boundary value and block size */
+ sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
+ data->blksz), SDHCI_BLOCK_SIZE);
sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
}
static void sdhci_set_transfer_mode(struct sdhci_host *host,
- struct mmc_data *data)
+ struct mmc_command *cmd)
{
u16 mode;
+ struct mmc_data *data = cmd->data;
if (data == NULL)
return;
@@ -823,12 +849,20 @@
WARN_ON(!host->data);
mode = SDHCI_TRNS_BLK_CNT_EN;
- if (data->blocks > 1) {
- if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
- mode |= SDHCI_TRNS_MULTI | SDHCI_TRNS_ACMD12;
- else
- mode |= SDHCI_TRNS_MULTI;
+ if (mmc_op_multi(cmd->opcode) || data->blocks > 1) {
+ mode |= SDHCI_TRNS_MULTI;
+ /*
+ * If we are sending CMD23, CMD12 never gets sent
+ * on successful completion (so no Auto-CMD12).
+ */
+ if (!host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD12))
+ mode |= SDHCI_TRNS_AUTO_CMD12;
+ else if (host->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) {
+ mode |= SDHCI_TRNS_AUTO_CMD23;
+ sdhci_writel(host, host->mrq->sbc->arg, SDHCI_ARGUMENT2);
+ }
}
+
if (data->flags & MMC_DATA_READ)
mode |= SDHCI_TRNS_READ;
if (host->flags & SDHCI_REQ_USE_DMA)
@@ -868,7 +902,15 @@
else
data->bytes_xfered = data->blksz * data->blocks;
- if (data->stop) {
+ /*
+ * Need to send CMD12 if -
+ * a) open-ended multiblock transfer (no CMD23)
+ * b) error in multiblock transfer
+ */
+ if (data->stop &&
+ (data->error ||
+ !host->mrq->sbc)) {
+
/*
* The controller needs a reset of internal state machines
* upon error conditions.
@@ -920,11 +962,11 @@
host->cmd = cmd;
- sdhci_prepare_data(host, cmd->data);
+ sdhci_prepare_data(host, cmd);
sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT);
- sdhci_set_transfer_mode(host, cmd->data);
+ sdhci_set_transfer_mode(host, cmd);
if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) {
printk(KERN_ERR "%s: Unsupported response type!\n",
@@ -947,7 +989,9 @@
flags |= SDHCI_CMD_CRC;
if (cmd->flags & MMC_RSP_OPCODE)
flags |= SDHCI_CMD_INDEX;
- if (cmd->data)
+
+ /* CMD19 is special in that the Data Present Select should be set */
+ if (cmd->data || (cmd->opcode == MMC_SEND_TUNING_BLOCK))
flags |= SDHCI_CMD_DATA;
sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND);
@@ -977,19 +1021,27 @@
host->cmd->error = 0;
- if (host->data && host->data_early)
- sdhci_finish_data(host);
+ /* Finished CMD23, now send actual command. */
+ if (host->cmd == host->mrq->sbc) {
+ host->cmd = NULL;
+ sdhci_send_command(host, host->mrq->cmd);
+ } else {
- if (!host->cmd->data)
- tasklet_schedule(&host->finish_tasklet);
+ /* Processed actual command. */
+ if (host->data && host->data_early)
+ sdhci_finish_data(host);
- host->cmd = NULL;
+ if (!host->cmd->data)
+ tasklet_schedule(&host->finish_tasklet);
+
+ host->cmd = NULL;
+ }
}
static void sdhci_set_clock(struct sdhci_host *host, unsigned int clock)
{
- int div;
- u16 clk;
+ int div = 0; /* Initialized for compiler warning */
+ u16 clk = 0;
unsigned long timeout;
if (clock == host->clock)
@@ -1007,14 +1059,45 @@
goto out;
if (host->version >= SDHCI_SPEC_300) {
- /* Version 3.00 divisors must be a multiple of 2. */
- if (host->max_clk <= clock)
- div = 1;
- else {
- for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; div += 2) {
- if ((host->max_clk / div) <= clock)
- break;
+ /*
+ * Check if the Host Controller supports Programmable Clock
+ * Mode.
+ */
+ if (host->clk_mul) {
+ u16 ctrl;
+
+ /*
+ * We need to figure out whether the Host Driver needs
+ * to select Programmable Clock Mode, or the value can
+ * be set automatically by the Host Controller based on
+ * the Preset Value registers.
+ */
+ ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+ if (!(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
+ for (div = 1; div <= 1024; div++) {
+ if (((host->max_clk * host->clk_mul) /
+ div) <= clock)
+ break;
+ }
+ /*
+ * Set Programmable Clock Mode in the Clock
+ * Control register.
+ */
+ clk = SDHCI_PROG_CLOCK_MODE;
+ div--;
}
+ } else {
+ /* Version 3.00 divisors must be a multiple of 2. */
+ if (host->max_clk <= clock)
+ div = 1;
+ else {
+ for (div = 2; div < SDHCI_MAX_DIV_SPEC_300;
+ div += 2) {
+ if ((host->max_clk / div) <= clock)
+ break;
+ }
+ }
+ div >>= 1;
}
} else {
/* Version 2.00 divisors must be a power of 2. */
@@ -1022,10 +1105,10 @@
if ((host->max_clk / div) <= clock)
break;
}
+ div >>= 1;
}
- div >>= 1;
- clk = (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
+ clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
<< SDHCI_DIVIDER_HI_SHIFT;
clk |= SDHCI_CLOCK_INT_EN;
@@ -1131,7 +1214,12 @@
#ifndef SDHCI_USE_LEDS_CLASS
sdhci_activate_led(host);
#endif
- if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) {
+
+ /*
+ * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED
+ * requests if Auto-CMD12 is enabled.
+ */
+ if (!mrq->sbc && (host->flags & SDHCI_AUTO_CMD12)) {
if (mrq->stop) {
mrq->data->stop = NULL;
mrq->stop = NULL;
@@ -1150,8 +1238,30 @@
if (!present || host->flags & SDHCI_DEVICE_DEAD) {
host->mrq->cmd->error = -ENOMEDIUM;
tasklet_schedule(&host->finish_tasklet);
- } else
- sdhci_send_command(host, mrq->cmd);
+ } else {
+ u32 present_state;
+
+ present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
+ /*
+ * Check if the re-tuning timer has already expired and there
+ * is no on-going data transfer. If so, we need to execute
+ * tuning procedure before sending command.
+ */
+ if ((host->flags & SDHCI_NEEDS_RETUNING) &&
+ !(present_state & (SDHCI_DOING_WRITE | SDHCI_DOING_READ))) {
+ spin_unlock_irqrestore(&host->lock, flags);
+ sdhci_execute_tuning(mmc);
+ spin_lock_irqsave(&host->lock, flags);
+
+ /* Restore original mmc_request structure */
+ host->mrq = mrq;
+ }
+
+ if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23))
+ sdhci_send_command(host, mrq->sbc);
+ else
+ sdhci_send_command(host, mrq->cmd);
+ }
mmiowb();
spin_unlock_irqrestore(&host->lock, flags);
@@ -1222,7 +1332,84 @@
else
ctrl &= ~SDHCI_CTRL_HISPD;
- sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
+ if (host->version >= SDHCI_SPEC_300) {
+ u16 clk, ctrl_2;
+ unsigned int clock;
+
+ /* In case of UHS-I modes, set High Speed Enable */
+ if ((ios->timing == MMC_TIMING_UHS_SDR50) ||
+ (ios->timing == MMC_TIMING_UHS_SDR104) ||
+ (ios->timing == MMC_TIMING_UHS_DDR50) ||
+ (ios->timing == MMC_TIMING_UHS_SDR25) ||
+ (ios->timing == MMC_TIMING_UHS_SDR12))
+ ctrl |= SDHCI_CTRL_HISPD;
+
+ ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+ if (!(ctrl_2 & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
+ sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
+ /*
+ * We only need to set Driver Strength if the
+ * preset value enable is not set.
+ */
+ ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK;
+ if (ios->drv_type == MMC_SET_DRIVER_TYPE_A)
+ ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A;
+ else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C)
+ ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C;
+
+ sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
+ } else {
+ /*
+ * According to SDHC Spec v3.00, if the Preset Value
+ * Enable in the Host Control 2 register is set, we
+ * need to reset SD Clock Enable before changing High
+ * Speed Enable to avoid generating clock gliches.
+ */
+
+ /* Reset SD Clock Enable */
+ clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
+ clk &= ~SDHCI_CLOCK_CARD_EN;
+ sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
+
+ sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
+
+ /* Re-enable SD Clock */
+ clock = host->clock;
+ host->clock = 0;
+ sdhci_set_clock(host, clock);
+ }
+
+
+ /* Reset SD Clock Enable */
+ clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
+ clk &= ~SDHCI_CLOCK_CARD_EN;
+ sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
+
+ if (host->ops->set_uhs_signaling)
+ host->ops->set_uhs_signaling(host, ios->timing);
+ else {
+ ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+ /* Select Bus Speed Mode for host */
+ ctrl_2 &= ~SDHCI_CTRL_UHS_MASK;
+ if (ios->timing == MMC_TIMING_UHS_SDR12)
+ ctrl_2 |= SDHCI_CTRL_UHS_SDR12;
+ else if (ios->timing == MMC_TIMING_UHS_SDR25)
+ ctrl_2 |= SDHCI_CTRL_UHS_SDR25;
+ else if (ios->timing == MMC_TIMING_UHS_SDR50)
+ ctrl_2 |= SDHCI_CTRL_UHS_SDR50;
+ else if (ios->timing == MMC_TIMING_UHS_SDR104)
+ ctrl_2 |= SDHCI_CTRL_UHS_SDR104;
+ else if (ios->timing == MMC_TIMING_UHS_DDR50)
+ ctrl_2 |= SDHCI_CTRL_UHS_DDR50;
+ sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2);
+ }
+
+ /* Re-enable SD Clock */
+ clock = host->clock;
+ host->clock = 0;
+ sdhci_set_clock(host, clock);
+ } else
+ sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
/*
* Some (ENE) controllers go apeshit on some ios operation,
@@ -1237,14 +1424,11 @@
spin_unlock_irqrestore(&host->lock, flags);
}
-static int sdhci_get_ro(struct mmc_host *mmc)
+static int check_ro(struct sdhci_host *host)
{
- struct sdhci_host *host;
unsigned long flags;
int is_readonly;
- host = mmc_priv(mmc);
-
spin_lock_irqsave(&host->lock, flags);
if (host->flags & SDHCI_DEVICE_DEAD)
@@ -1262,6 +1446,29 @@
!is_readonly : is_readonly;
}
+#define SAMPLE_COUNT 5
+
+static int sdhci_get_ro(struct mmc_host *mmc)
+{
+ struct sdhci_host *host;
+ int i, ro_count;
+
+ host = mmc_priv(mmc);
+
+ if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT))
+ return check_ro(host);
+
+ ro_count = 0;
+ for (i = 0; i < SAMPLE_COUNT; i++) {
+ if (check_ro(host)) {
+ if (++ro_count > SAMPLE_COUNT / 2)
+ return 1;
+ }
+ msleep(30);
+ }
+ return 0;
+}
+
static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable)
{
struct sdhci_host *host;
@@ -1284,11 +1491,322 @@
spin_unlock_irqrestore(&host->lock, flags);
}
+static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
+ struct mmc_ios *ios)
+{
+ struct sdhci_host *host;
+ u8 pwr;
+ u16 clk, ctrl;
+ u32 present_state;
+
+ host = mmc_priv(mmc);
+
+ /*
+ * Signal Voltage Switching is only applicable for Host Controllers
+ * v3.00 and above.
+ */
+ if (host->version < SDHCI_SPEC_300)
+ return 0;
+
+ /*
+ * We first check whether the request is to set signalling voltage
+ * to 3.3V. If so, we change the voltage to 3.3V and return quickly.
+ */
+ ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+ if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) {
+ /* Set 1.8V Signal Enable in the Host Control2 register to 0 */
+ ctrl &= ~SDHCI_CTRL_VDD_180;
+ sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
+
+ /* Wait for 5ms */
+ usleep_range(5000, 5500);
+
+ /* 3.3V regulator output should be stable within 5 ms */
+ ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+ if (!(ctrl & SDHCI_CTRL_VDD_180))
+ return 0;
+ else {
+ printk(KERN_INFO DRIVER_NAME ": Switching to 3.3V "
+ "signalling voltage failed\n");
+ return -EIO;
+ }
+ } else if (!(ctrl & SDHCI_CTRL_VDD_180) &&
+ (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180)) {
+ /* Stop SDCLK */
+ clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
+ clk &= ~SDHCI_CLOCK_CARD_EN;
+ sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
+
+ /* Check whether DAT[3:0] is 0000 */
+ present_state = sdhci_readl(host, SDHCI_PRESENT_STATE);
+ if (!((present_state & SDHCI_DATA_LVL_MASK) >>
+ SDHCI_DATA_LVL_SHIFT)) {
+ /*
+ * Enable 1.8V Signal Enable in the Host Control2
+ * register
+ */
+ ctrl |= SDHCI_CTRL_VDD_180;
+ sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
+
+ /* Wait for 5ms */
+ usleep_range(5000, 5500);
+
+ ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+ if (ctrl & SDHCI_CTRL_VDD_180) {
+ /* Provide SDCLK again and wait for 1ms*/
+ clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
+ clk |= SDHCI_CLOCK_CARD_EN;
+ sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
+ usleep_range(1000, 1500);
+
+ /*
+ * If DAT[3:0] level is 1111b, then the card
+ * was successfully switched to 1.8V signaling.
+ */
+ present_state = sdhci_readl(host,
+ SDHCI_PRESENT_STATE);
+ if ((present_state & SDHCI_DATA_LVL_MASK) ==
+ SDHCI_DATA_LVL_MASK)
+ return 0;
+ }
+ }
+
+ /*
+ * If we are here, that means the switch to 1.8V signaling
+ * failed. We power cycle the card, and retry initialization
+ * sequence by setting S18R to 0.
+ */
+ pwr = sdhci_readb(host, SDHCI_POWER_CONTROL);
+ pwr &= ~SDHCI_POWER_ON;
+ sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
+
+ /* Wait for 1ms as per the spec */
+ usleep_range(1000, 1500);
+ pwr |= SDHCI_POWER_ON;
+ sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
+
+ printk(KERN_INFO DRIVER_NAME ": Switching to 1.8V signalling "
+ "voltage failed, retrying with S18R set to 0\n");
+ return -EAGAIN;
+ } else
+ /* No signal voltage switch required */
+ return 0;
+}
+
+static int sdhci_execute_tuning(struct mmc_host *mmc)
+{
+ struct sdhci_host *host;
+ u16 ctrl;
+ u32 ier;
+ int tuning_loop_counter = MAX_TUNING_LOOP;
+ unsigned long timeout;
+ int err = 0;
+
+ host = mmc_priv(mmc);
+
+ disable_irq(host->irq);
+ spin_lock(&host->lock);
+
+ ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+
+ /*
+ * Host Controller needs tuning only in case of SDR104 mode
+ * and for SDR50 mode when Use Tuning for SDR50 is set in
+ * Capabilities register.
+ */
+ if (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR104) ||
+ (((ctrl & SDHCI_CTRL_UHS_MASK) == SDHCI_CTRL_UHS_SDR50) &&
+ (host->flags & SDHCI_SDR50_NEEDS_TUNING)))
+ ctrl |= SDHCI_CTRL_EXEC_TUNING;
+ else {
+ spin_unlock(&host->lock);
+ enable_irq(host->irq);
+ return 0;
+ }
+
+ sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
+
+ /*
+ * As per the Host Controller spec v3.00, tuning command
+ * generates Buffer Read Ready interrupt, so enable that.
+ *
+ * Note: The spec clearly says that when tuning sequence
+ * is being performed, the controller does not generate
+ * interrupts other than Buffer Read Ready interrupt. But
+ * to make sure we don't hit a controller bug, we _only_
+ * enable Buffer Read Ready interrupt here.
+ */
+ ier = sdhci_readl(host, SDHCI_INT_ENABLE);
+ sdhci_clear_set_irqs(host, ier, SDHCI_INT_DATA_AVAIL);
+
+ /*
+ * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number
+ * of loops reaches 40 times or a timeout of 150ms occurs.
+ */
+ timeout = 150;
+ do {
+ struct mmc_command cmd = {0};
+ struct mmc_request mrq = {0};
+
+ if (!tuning_loop_counter && !timeout)
+ break;
+
+ cmd.opcode = MMC_SEND_TUNING_BLOCK;
+ cmd.arg = 0;
+ cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC;
+ cmd.retries = 0;
+ cmd.data = NULL;
+ cmd.error = 0;
+
+ mrq.cmd = &cmd;
+ host->mrq = &mrq;
+
+ /*
+ * In response to CMD19, the card sends 64 bytes of tuning
+ * block to the Host Controller. So we set the block size
+ * to 64 here.
+ */
+ sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), SDHCI_BLOCK_SIZE);
+
+ /*
+ * The tuning block is sent by the card to the host controller.
+ * So we set the TRNS_READ bit in the Transfer Mode register.
+ * This also takes care of setting DMA Enable and Multi Block
+ * Select in the same register to 0.
+ */
+ sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
+
+ sdhci_send_command(host, &cmd);
+
+ host->cmd = NULL;
+ host->mrq = NULL;
+
+ spin_unlock(&host->lock);
+ enable_irq(host->irq);
+
+ /* Wait for Buffer Read Ready interrupt */
+ wait_event_interruptible_timeout(host->buf_ready_int,
+ (host->tuning_done == 1),
+ msecs_to_jiffies(50));
+ disable_irq(host->irq);
+ spin_lock(&host->lock);
+
+ if (!host->tuning_done) {
+ printk(KERN_INFO DRIVER_NAME ": Timeout waiting for "
+ "Buffer Read Ready interrupt during tuning "
+ "procedure, falling back to fixed sampling "
+ "clock\n");
+ ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+ ctrl &= ~SDHCI_CTRL_TUNED_CLK;
+ ctrl &= ~SDHCI_CTRL_EXEC_TUNING;
+ sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
+
+ err = -EIO;
+ goto out;
+ }
+
+ host->tuning_done = 0;
+
+ ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+ tuning_loop_counter--;
+ timeout--;
+ mdelay(1);
+ } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
+
+ /*
+ * The Host Driver has exhausted the maximum number of loops allowed,
+ * so use fixed sampling frequency.
+ */
+ if (!tuning_loop_counter || !timeout) {
+ ctrl &= ~SDHCI_CTRL_TUNED_CLK;
+ sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
+ } else {
+ if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
+ printk(KERN_INFO DRIVER_NAME ": Tuning procedure"
+ " failed, falling back to fixed sampling"
+ " clock\n");
+ err = -EIO;
+ }
+ }
+
+out:
+ /*
+ * If this is the very first time we are here, we start the retuning
+ * timer. Since only during the first time, SDHCI_NEEDS_RETUNING
+ * flag won't be set, we check this condition before actually starting
+ * the timer.
+ */
+ if (!(host->flags & SDHCI_NEEDS_RETUNING) && host->tuning_count &&
+ (host->tuning_mode == SDHCI_TUNING_MODE_1)) {
+ mod_timer(&host->tuning_timer, jiffies +
+ host->tuning_count * HZ);
+ /* Tuning mode 1 limits the maximum data length to 4MB */
+ mmc->max_blk_count = (4 * 1024 * 1024) / mmc->max_blk_size;
+ } else {
+ host->flags &= ~SDHCI_NEEDS_RETUNING;
+ /* Reload the new initial value for timer */
+ if (host->tuning_mode == SDHCI_TUNING_MODE_1)
+ mod_timer(&host->tuning_timer, jiffies +
+ host->tuning_count * HZ);
+ }
+
+ /*
+ * In case tuning fails, host controllers which support re-tuning can
+ * try tuning again at a later time, when the re-tuning timer expires.
+ * So for these controllers, we return 0. Since there might be other
+ * controllers who do not have this capability, we return error for
+ * them.
+ */
+ if (err && host->tuning_count &&
+ host->tuning_mode == SDHCI_TUNING_MODE_1)
+ err = 0;
+
+ sdhci_clear_set_irqs(host, SDHCI_INT_DATA_AVAIL, ier);
+ spin_unlock(&host->lock);
+ enable_irq(host->irq);
+
+ return err;
+}
+
+static void sdhci_enable_preset_value(struct mmc_host *mmc, bool enable)
+{
+ struct sdhci_host *host;
+ u16 ctrl;
+ unsigned long flags;
+
+ host = mmc_priv(mmc);
+
+ /* Host Controller v3.00 defines preset value registers */
+ if (host->version < SDHCI_SPEC_300)
+ return;
+
+ spin_lock_irqsave(&host->lock, flags);
+
+ ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
+
+ /*
+ * We only enable or disable Preset Value if they are not already
+ * enabled or disabled respectively. Otherwise, we bail out.
+ */
+ if (enable && !(ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
+ ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE;
+ sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
+ } else if (!enable && (ctrl & SDHCI_CTRL_PRESET_VAL_ENABLE)) {
+ ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE;
+ sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
+ }
+
+ spin_unlock_irqrestore(&host->lock, flags);
+}
+
static const struct mmc_host_ops sdhci_ops = {
.request = sdhci_request,
.set_ios = sdhci_set_ios,
.get_ro = sdhci_get_ro,
.enable_sdio_irq = sdhci_enable_sdio_irq,
+ .start_signal_voltage_switch = sdhci_start_signal_voltage_switch,
+ .execute_tuning = sdhci_execute_tuning,
+ .enable_preset_value = sdhci_enable_preset_value,
};
/*****************************************************************************\
@@ -1345,6 +1863,9 @@
del_timer(&host->timer);
+ if (host->version >= SDHCI_SPEC_300)
+ del_timer(&host->tuning_timer);
+
mrq = host->mrq;
/*
@@ -1418,6 +1939,20 @@
spin_unlock_irqrestore(&host->lock, flags);
}
+static void sdhci_tuning_timer(unsigned long data)
+{
+ struct sdhci_host *host;
+ unsigned long flags;
+
+ host = (struct sdhci_host *)data;
+
+ spin_lock_irqsave(&host->lock, flags);
+
+ host->flags |= SDHCI_NEEDS_RETUNING;
+
+ spin_unlock_irqrestore(&host->lock, flags);
+}
+
/*****************************************************************************\
* *
* Interrupt handling *
@@ -1506,6 +2041,16 @@
{
BUG_ON(intmask == 0);
+ /* CMD19 generates _only_ Buffer Read Ready interrupt */
+ if (intmask & SDHCI_INT_DATA_AVAIL) {
+ if (SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) ==
+ MMC_SEND_TUNING_BLOCK) {
+ host->tuning_done = 1;
+ wake_up(&host->buf_ready_int);
+ return;
+ }
+ }
+
if (!host->data) {
/*
* The "data complete" interrupt is also used to
@@ -1551,10 +2096,28 @@
* We currently don't do anything fancy with DMA
* boundaries, but as we can't disable the feature
* we need to at least restart the transfer.
+ *
+ * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS)
+ * should return a valid address to continue from, but as
+ * some controllers are faulty, don't trust them.
*/
- if (intmask & SDHCI_INT_DMA_END)
- sdhci_writel(host, sdhci_readl(host, SDHCI_DMA_ADDRESS),
- SDHCI_DMA_ADDRESS);
+ if (intmask & SDHCI_INT_DMA_END) {
+ u32 dmastart, dmanow;
+ dmastart = sg_dma_address(host->data->sg);
+ dmanow = dmastart + host->data->bytes_xfered;
+ /*
+ * Force update to the next DMA block boundary.
+ */
+ dmanow = (dmanow &
+ ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) +
+ SDHCI_DEFAULT_BOUNDARY_SIZE;
+ host->data->bytes_xfered = dmanow - dmastart;
+ DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes,"
+ " next 0x%08x\n",
+ mmc_hostname(host->mmc), dmastart,
+ host->data->bytes_xfered, dmanow);
+ sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS);
+ }
if (intmask & SDHCI_INT_DATA_END) {
if (host->cmd) {
@@ -1664,6 +2227,14 @@
sdhci_disable_card_detection(host);
+ /* Disable tuning since we are suspending */
+ if (host->version >= SDHCI_SPEC_300 && host->tuning_count &&
+ host->tuning_mode == SDHCI_TUNING_MODE_1) {
+ host->flags &= ~SDHCI_NEEDS_RETUNING;
+ mod_timer(&host->tuning_timer, jiffies +
+ host->tuning_count * HZ);
+ }
+
ret = mmc_suspend_host(host->mmc);
if (ret)
return ret;
@@ -1705,6 +2276,11 @@
ret = mmc_resume_host(host->mmc);
sdhci_enable_card_detection(host);
+ /* Set the re-tuning expiration flag */
+ if ((host->version >= SDHCI_SPEC_300) && host->tuning_count &&
+ (host->tuning_mode == SDHCI_TUNING_MODE_1))
+ host->flags |= SDHCI_NEEDS_RETUNING;
+
return ret;
}
@@ -1751,7 +2327,9 @@
int sdhci_add_host(struct sdhci_host *host)
{
struct mmc_host *mmc;
- unsigned int caps, ocr_avail;
+ u32 caps[2];
+ u32 max_current_caps;
+ unsigned int ocr_avail;
int ret;
WARN_ON(host == NULL);
@@ -1774,12 +2352,15 @@
host->version);
}
- caps = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
+ caps[0] = (host->quirks & SDHCI_QUIRK_MISSING_CAPS) ? host->caps :
sdhci_readl(host, SDHCI_CAPABILITIES);
+ caps[1] = (host->version >= SDHCI_SPEC_300) ?
+ sdhci_readl(host, SDHCI_CAPABILITIES_1) : 0;
+
if (host->quirks & SDHCI_QUIRK_FORCE_DMA)
host->flags |= SDHCI_USE_SDMA;
- else if (!(caps & SDHCI_CAN_DO_SDMA))
+ else if (!(caps[0] & SDHCI_CAN_DO_SDMA))
DBG("Controller doesn't have SDMA capability\n");
else
host->flags |= SDHCI_USE_SDMA;
@@ -1790,7 +2371,8 @@
host->flags &= ~SDHCI_USE_SDMA;
}
- if ((host->version >= SDHCI_SPEC_200) && (caps & SDHCI_CAN_DO_ADMA2))
+ if ((host->version >= SDHCI_SPEC_200) &&
+ (caps[0] & SDHCI_CAN_DO_ADMA2))
host->flags |= SDHCI_USE_ADMA;
if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) &&
@@ -1840,10 +2422,10 @@
}
if (host->version >= SDHCI_SPEC_300)
- host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK)
+ host->max_clk = (caps[0] & SDHCI_CLOCK_V3_BASE_MASK)
>> SDHCI_CLOCK_BASE_SHIFT;
else
- host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK)
+ host->max_clk = (caps[0] & SDHCI_CLOCK_BASE_MASK)
>> SDHCI_CLOCK_BASE_SHIFT;
host->max_clk *= 1000000;
@@ -1859,7 +2441,7 @@
}
host->timeout_clk =
- (caps & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
+ (caps[0] & SDHCI_TIMEOUT_CLK_MASK) >> SDHCI_TIMEOUT_CLK_SHIFT;
if (host->timeout_clk == 0) {
if (host->ops->get_timeout_clock) {
host->timeout_clk = host->ops->get_timeout_clock(host);
@@ -1871,22 +2453,55 @@
return -ENODEV;
}
}
- if (caps & SDHCI_TIMEOUT_CLK_UNIT)
+ if (caps[0] & SDHCI_TIMEOUT_CLK_UNIT)
host->timeout_clk *= 1000;
/*
+ * In case of Host Controller v3.00, find out whether clock
+ * multiplier is supported.
+ */
+ host->clk_mul = (caps[1] & SDHCI_CLOCK_MUL_MASK) >>
+ SDHCI_CLOCK_MUL_SHIFT;
+
+ /*
+ * In case the value in Clock Multiplier is 0, then programmable
+ * clock mode is not supported, otherwise the actual clock
+ * multiplier is one more than the value of Clock Multiplier
+ * in the Capabilities Register.
+ */
+ if (host->clk_mul)
+ host->clk_mul += 1;
+
+ /*
* Set host parameters.
*/
mmc->ops = &sdhci_ops;
+ mmc->f_max = host->max_clk;
if (host->ops->get_min_clock)
mmc->f_min = host->ops->get_min_clock(host);
- else if (host->version >= SDHCI_SPEC_300)
- mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
- else
+ else if (host->version >= SDHCI_SPEC_300) {
+ if (host->clk_mul) {
+ mmc->f_min = (host->max_clk * host->clk_mul) / 1024;
+ mmc->f_max = host->max_clk * host->clk_mul;
+ } else
+ mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300;
+ } else
mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200;
- mmc->f_max = host->max_clk;
- mmc->caps |= MMC_CAP_SDIO_IRQ;
+ mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23;
+
+ if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12)
+ host->flags |= SDHCI_AUTO_CMD12;
+
+ /* Auto-CMD23 stuff only works in ADMA or PIO. */
+ if ((host->version >= SDHCI_SPEC_300) &&
+ ((host->flags & SDHCI_USE_ADMA) ||
+ !(host->flags & SDHCI_USE_SDMA))) {
+ host->flags |= SDHCI_AUTO_CMD23;
+ DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc));
+ } else {
+ DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc));
+ }
/*
* A controller may support 8-bit width, but the board itself
@@ -1898,21 +2513,113 @@
if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA))
mmc->caps |= MMC_CAP_4_BIT_DATA;
- if (caps & SDHCI_CAN_DO_HISPD)
+ if (caps[0] & SDHCI_CAN_DO_HISPD)
mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) &&
mmc_card_is_removable(mmc))
mmc->caps |= MMC_CAP_NEEDS_POLL;
+ /* UHS-I mode(s) supported by the host controller. */
+ if (host->version >= SDHCI_SPEC_300)
+ mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25;
+
+ /* SDR104 supports also implies SDR50 support */
+ if (caps[1] & SDHCI_SUPPORT_SDR104)
+ mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50;
+ else if (caps[1] & SDHCI_SUPPORT_SDR50)
+ mmc->caps |= MMC_CAP_UHS_SDR50;
+
+ if (caps[1] & SDHCI_SUPPORT_DDR50)
+ mmc->caps |= MMC_CAP_UHS_DDR50;
+
+ /* Does the host needs tuning for SDR50? */
+ if (caps[1] & SDHCI_USE_SDR50_TUNING)
+ host->flags |= SDHCI_SDR50_NEEDS_TUNING;
+
+ /* Driver Type(s) (A, C, D) supported by the host */
+ if (caps[1] & SDHCI_DRIVER_TYPE_A)
+ mmc->caps |= MMC_CAP_DRIVER_TYPE_A;
+ if (caps[1] & SDHCI_DRIVER_TYPE_C)
+ mmc->caps |= MMC_CAP_DRIVER_TYPE_C;
+ if (caps[1] & SDHCI_DRIVER_TYPE_D)
+ mmc->caps |= MMC_CAP_DRIVER_TYPE_D;
+
+ /* Initial value for re-tuning timer count */
+ host->tuning_count = (caps[1] & SDHCI_RETUNING_TIMER_COUNT_MASK) >>
+ SDHCI_RETUNING_TIMER_COUNT_SHIFT;
+
+ /*
+ * In case Re-tuning Timer is not disabled, the actual value of
+ * re-tuning timer will be 2 ^ (n - 1).
+ */
+ if (host->tuning_count)
+ host->tuning_count = 1 << (host->tuning_count - 1);
+
+ /* Re-tuning mode supported by the Host Controller */
+ host->tuning_mode = (caps[1] & SDHCI_RETUNING_MODE_MASK) >>
+ SDHCI_RETUNING_MODE_SHIFT;
+
ocr_avail = 0;
- if (caps & SDHCI_CAN_VDD_330)
+ /*
+ * According to SD Host Controller spec v3.00, if the Host System
+ * can afford more than 150mA, Host Driver should set XPC to 1. Also
+ * the value is meaningful only if Voltage Support in the Capabilities
+ * register is set. The actual current value is 4 times the register
+ * value.
+ */
+ max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT);
+
+ if (caps[0] & SDHCI_CAN_VDD_330) {
+ int max_current_330;
+
ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34;
- if (caps & SDHCI_CAN_VDD_300)
+
+ max_current_330 = ((max_current_caps &
+ SDHCI_MAX_CURRENT_330_MASK) >>
+ SDHCI_MAX_CURRENT_330_SHIFT) *
+ SDHCI_MAX_CURRENT_MULTIPLIER;
+
+ if (max_current_330 > 150)
+ mmc->caps |= MMC_CAP_SET_XPC_330;
+ }
+ if (caps[0] & SDHCI_CAN_VDD_300) {
+ int max_current_300;
+
ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31;
- if (caps & SDHCI_CAN_VDD_180)
+
+ max_current_300 = ((max_current_caps &
+ SDHCI_MAX_CURRENT_300_MASK) >>
+ SDHCI_MAX_CURRENT_300_SHIFT) *
+ SDHCI_MAX_CURRENT_MULTIPLIER;
+
+ if (max_current_300 > 150)
+ mmc->caps |= MMC_CAP_SET_XPC_300;
+ }
+ if (caps[0] & SDHCI_CAN_VDD_180) {
+ int max_current_180;
+
ocr_avail |= MMC_VDD_165_195;
+ max_current_180 = ((max_current_caps &
+ SDHCI_MAX_CURRENT_180_MASK) >>
+ SDHCI_MAX_CURRENT_180_SHIFT) *
+ SDHCI_MAX_CURRENT_MULTIPLIER;
+
+ if (max_current_180 > 150)
+ mmc->caps |= MMC_CAP_SET_XPC_180;
+
+ /* Maximum current capabilities of the host at 1.8V */
+ if (max_current_180 >= 800)
+ mmc->caps |= MMC_CAP_MAX_CURRENT_800;
+ else if (max_current_180 >= 600)
+ mmc->caps |= MMC_CAP_MAX_CURRENT_600;
+ else if (max_current_180 >= 400)
+ mmc->caps |= MMC_CAP_MAX_CURRENT_400;
+ else
+ mmc->caps |= MMC_CAP_MAX_CURRENT_200;
+ }
+
mmc->ocr_avail = ocr_avail;
mmc->ocr_avail_sdio = ocr_avail;
if (host->ocr_avail_sdio)
@@ -1972,7 +2679,7 @@
if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) {
mmc->max_blk_size = 2;
} else {
- mmc->max_blk_size = (caps & SDHCI_MAX_BLOCK_MASK) >>
+ mmc->max_blk_size = (caps[0] & SDHCI_MAX_BLOCK_MASK) >>
SDHCI_MAX_BLOCK_SHIFT;
if (mmc->max_blk_size >= 3) {
printk(KERN_WARNING "%s: Invalid maximum block size, "
@@ -1998,6 +2705,15 @@
setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host);
+ if (host->version >= SDHCI_SPEC_300) {
+ init_waitqueue_head(&host->buf_ready_int);
+
+ /* Initialize re-tuning timer */
+ init_timer(&host->tuning_timer);
+ host->tuning_timer.data = (unsigned long)host;
+ host->tuning_timer.function = sdhci_tuning_timer;
+ }
+
ret = request_irq(host->irq, sdhci_irq, IRQF_SHARED,
mmc_hostname(mmc), host);
if (ret)
@@ -2091,6 +2807,8 @@
free_irq(host->irq, host);
del_timer_sync(&host->timer);
+ if (host->version >= SDHCI_SPEC_300)
+ del_timer_sync(&host->tuning_timer);
tasklet_kill(&host->card_tasklet);
tasklet_kill(&host->finish_tasklet);
diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h
index 25e8bde..745c42f 100644
--- a/drivers/mmc/host/sdhci.h
+++ b/drivers/mmc/host/sdhci.h
@@ -25,6 +25,7 @@
*/
#define SDHCI_DMA_ADDRESS 0x00
+#define SDHCI_ARGUMENT2 SDHCI_DMA_ADDRESS
#define SDHCI_BLOCK_SIZE 0x04
#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
@@ -36,7 +37,8 @@
#define SDHCI_TRANSFER_MODE 0x0C
#define SDHCI_TRNS_DMA 0x01
#define SDHCI_TRNS_BLK_CNT_EN 0x02
-#define SDHCI_TRNS_ACMD12 0x04
+#define SDHCI_TRNS_AUTO_CMD12 0x04
+#define SDHCI_TRNS_AUTO_CMD23 0x08
#define SDHCI_TRNS_READ 0x10
#define SDHCI_TRNS_MULTI 0x20
@@ -68,8 +70,10 @@
#define SDHCI_DATA_AVAILABLE 0x00000800
#define SDHCI_CARD_PRESENT 0x00010000
#define SDHCI_WRITE_PROTECT 0x00080000
+#define SDHCI_DATA_LVL_MASK 0x00F00000
+#define SDHCI_DATA_LVL_SHIFT 20
-#define SDHCI_HOST_CONTROL 0x28
+#define SDHCI_HOST_CONTROL 0x28
#define SDHCI_CTRL_LED 0x01
#define SDHCI_CTRL_4BITBUS 0x02
#define SDHCI_CTRL_HISPD 0x04
@@ -99,6 +103,7 @@
#define SDHCI_DIV_MASK 0xFF
#define SDHCI_DIV_MASK_LEN 8
#define SDHCI_DIV_HI_MASK 0x300
+#define SDHCI_PROG_CLOCK_MODE 0x0020
#define SDHCI_CLOCK_CARD_EN 0x0004
#define SDHCI_CLOCK_INT_STABLE 0x0002
#define SDHCI_CLOCK_INT_EN 0x0001
@@ -146,7 +151,22 @@
#define SDHCI_ACMD12_ERR 0x3C
-/* 3E-3F reserved */
+#define SDHCI_HOST_CONTROL2 0x3E
+#define SDHCI_CTRL_UHS_MASK 0x0007
+#define SDHCI_CTRL_UHS_SDR12 0x0000
+#define SDHCI_CTRL_UHS_SDR25 0x0001
+#define SDHCI_CTRL_UHS_SDR50 0x0002
+#define SDHCI_CTRL_UHS_SDR104 0x0003
+#define SDHCI_CTRL_UHS_DDR50 0x0004
+#define SDHCI_CTRL_VDD_180 0x0008
+#define SDHCI_CTRL_DRV_TYPE_MASK 0x0030
+#define SDHCI_CTRL_DRV_TYPE_B 0x0000
+#define SDHCI_CTRL_DRV_TYPE_A 0x0010
+#define SDHCI_CTRL_DRV_TYPE_C 0x0020
+#define SDHCI_CTRL_DRV_TYPE_D 0x0030
+#define SDHCI_CTRL_EXEC_TUNING 0x0040
+#define SDHCI_CTRL_TUNED_CLK 0x0080
+#define SDHCI_CTRL_PRESET_VAL_ENABLE 0x8000
#define SDHCI_CAPABILITIES 0x40
#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F
@@ -167,9 +187,30 @@
#define SDHCI_CAN_VDD_180 0x04000000
#define SDHCI_CAN_64BIT 0x10000000
+#define SDHCI_SUPPORT_SDR50 0x00000001
+#define SDHCI_SUPPORT_SDR104 0x00000002
+#define SDHCI_SUPPORT_DDR50 0x00000004
+#define SDHCI_DRIVER_TYPE_A 0x00000010
+#define SDHCI_DRIVER_TYPE_C 0x00000020
+#define SDHCI_DRIVER_TYPE_D 0x00000040
+#define SDHCI_RETUNING_TIMER_COUNT_MASK 0x00000F00
+#define SDHCI_RETUNING_TIMER_COUNT_SHIFT 8
+#define SDHCI_USE_SDR50_TUNING 0x00002000
+#define SDHCI_RETUNING_MODE_MASK 0x0000C000
+#define SDHCI_RETUNING_MODE_SHIFT 14
+#define SDHCI_CLOCK_MUL_MASK 0x00FF0000
+#define SDHCI_CLOCK_MUL_SHIFT 16
+
#define SDHCI_CAPABILITIES_1 0x44
-#define SDHCI_MAX_CURRENT 0x48
+#define SDHCI_MAX_CURRENT 0x48
+#define SDHCI_MAX_CURRENT_330_MASK 0x0000FF
+#define SDHCI_MAX_CURRENT_330_SHIFT 0
+#define SDHCI_MAX_CURRENT_300_MASK 0x00FF00
+#define SDHCI_MAX_CURRENT_300_SHIFT 8
+#define SDHCI_MAX_CURRENT_180_MASK 0xFF0000
+#define SDHCI_MAX_CURRENT_180_SHIFT 16
+#define SDHCI_MAX_CURRENT_MULTIPLIER 4
/* 4C-4F reserved for more max current */
@@ -202,6 +243,12 @@
#define SDHCI_MAX_DIV_SPEC_200 256
#define SDHCI_MAX_DIV_SPEC_300 2046
+/*
+ * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.
+ */
+#define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024)
+#define SDHCI_DEFAULT_BOUNDARY_ARG (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12)
+
struct sdhci_ops {
#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
u32 (*read_l)(struct sdhci_host *host, int reg);
@@ -223,6 +270,10 @@
void (*platform_send_init_74_clocks)(struct sdhci_host *host,
u8 power_mode);
unsigned int (*get_ro)(struct sdhci_host *host);
+ void (*platform_reset_enter)(struct sdhci_host *host, u8 mask);
+ void (*platform_reset_exit)(struct sdhci_host *host, u8 mask);
+ int (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs);
+
};
#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
diff --git a/drivers/mmc/host/sdricoh_cs.c b/drivers/mmc/host/sdricoh_cs.c
index bbc298f..496b7ef 100644
--- a/drivers/mmc/host/sdricoh_cs.c
+++ b/drivers/mmc/host/sdricoh_cs.c
@@ -76,7 +76,7 @@
#define BUSY_TIMEOUT 32767
/* list of supported pcmcia devices */
-static struct pcmcia_device_id pcmcia_ids[] = {
+static const struct pcmcia_device_id pcmcia_ids[] = {
/* vendor and device strings followed by their crc32 hashes */
PCMCIA_DEVICE_PROD_ID12("RICOH", "Bay1Controller", 0xd9f522ed,
0xc3901202),
diff --git a/drivers/mmc/host/sh_mmcif.c b/drivers/mmc/host/sh_mmcif.c
index af97015..14f8edb 100644
--- a/drivers/mmc/host/sh_mmcif.c
+++ b/drivers/mmc/host/sh_mmcif.c
@@ -29,6 +29,8 @@
#include <linux/mmc/sh_mmcif.h>
#include <linux/pagemap.h>
#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
+#include <linux/spinlock.h>
#define DRIVER_NAME "sh_mmcif"
#define DRIVER_VERSION "2010-04-28"
@@ -153,6 +155,12 @@
#define CLKDEV_MMC_DATA 20000000 /* 20MHz */
#define CLKDEV_INIT 400000 /* 400 KHz */
+enum mmcif_state {
+ STATE_IDLE,
+ STATE_REQUEST,
+ STATE_IOS,
+};
+
struct sh_mmcif_host {
struct mmc_host *mmc;
struct mmc_data *data;
@@ -164,6 +172,9 @@
long timeout;
void __iomem *addr;
struct completion intr_wait;
+ enum mmcif_state state;
+ spinlock_t lock;
+ bool power;
/* DMA support */
struct dma_chan *chan_rx;
@@ -798,17 +809,31 @@
static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq)
{
struct sh_mmcif_host *host = mmc_priv(mmc);
+ unsigned long flags;
+
+ spin_lock_irqsave(&host->lock, flags);
+ if (host->state != STATE_IDLE) {
+ spin_unlock_irqrestore(&host->lock, flags);
+ mrq->cmd->error = -EAGAIN;
+ mmc_request_done(mmc, mrq);
+ return;
+ }
+
+ host->state = STATE_REQUEST;
+ spin_unlock_irqrestore(&host->lock, flags);
switch (mrq->cmd->opcode) {
/* MMCIF does not support SD/SDIO command */
case SD_IO_SEND_OP_COND:
case MMC_APP_CMD:
+ host->state = STATE_IDLE;
mrq->cmd->error = -ETIMEDOUT;
mmc_request_done(mmc, mrq);
return;
case MMC_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */
if (!mrq->data) {
/* send_if_cond cmd (not support) */
+ host->state = STATE_IDLE;
mrq->cmd->error = -ETIMEDOUT;
mmc_request_done(mmc, mrq);
return;
@@ -830,12 +855,9 @@
sh_mmcif_start_cmd(host, mrq, mrq->cmd);
host->data = NULL;
- if (mrq->cmd->error != 0) {
- mmc_request_done(mmc, mrq);
- return;
- }
- if (mrq->stop)
+ if (!mrq->cmd->error && mrq->stop)
sh_mmcif_stop_cmd(host, mrq, mrq->stop);
+ host->state = STATE_IDLE;
mmc_request_done(mmc, mrq);
}
@@ -843,15 +865,39 @@
{
struct sh_mmcif_host *host = mmc_priv(mmc);
struct sh_mmcif_plat_data *p = host->pd->dev.platform_data;
+ unsigned long flags;
+
+ spin_lock_irqsave(&host->lock, flags);
+ if (host->state != STATE_IDLE) {
+ spin_unlock_irqrestore(&host->lock, flags);
+ return;
+ }
+
+ host->state = STATE_IOS;
+ spin_unlock_irqrestore(&host->lock, flags);
if (ios->power_mode == MMC_POWER_UP) {
if (p->set_pwr)
p->set_pwr(host->pd, ios->power_mode);
+ if (!host->power) {
+ /* See if we also get DMA */
+ sh_mmcif_request_dma(host, host->pd->dev.platform_data);
+ pm_runtime_get_sync(&host->pd->dev);
+ host->power = true;
+ }
} else if (ios->power_mode == MMC_POWER_OFF || !ios->clock) {
/* clock stop */
sh_mmcif_clock_control(host, 0);
- if (ios->power_mode == MMC_POWER_OFF && p->down_pwr)
- p->down_pwr(host->pd);
+ if (ios->power_mode == MMC_POWER_OFF) {
+ if (host->power) {
+ pm_runtime_put(&host->pd->dev);
+ sh_mmcif_release_dma(host);
+ host->power = false;
+ }
+ if (p->down_pwr)
+ p->down_pwr(host->pd);
+ }
+ host->state = STATE_IDLE;
return;
}
@@ -859,6 +905,7 @@
sh_mmcif_clock_control(host, ios->clock);
host->bus_width = ios->bus_width;
+ host->state = STATE_IDLE;
}
static int sh_mmcif_get_cd(struct mmc_host *mmc)
@@ -925,7 +972,7 @@
sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state);
err = 1;
} else {
- dev_dbg(&host->pd->dev, "Not support int\n");
+ dev_dbg(&host->pd->dev, "Unsupported interrupt: 0x%x\n", state);
sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state);
sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state);
err = 1;
@@ -996,6 +1043,7 @@
host->pd = pdev;
init_completion(&host->intr_wait);
+ spin_lock_init(&host->lock);
mmc->ops = &sh_mmcif_ops;
mmc->f_max = host->clk;
@@ -1020,24 +1068,29 @@
sh_mmcif_sync_reset(host);
platform_set_drvdata(pdev, host);
- /* See if we also get DMA */
- sh_mmcif_request_dma(host, pd);
+ pm_runtime_enable(&pdev->dev);
+ host->power = false;
+
+ ret = pm_runtime_resume(&pdev->dev);
+ if (ret < 0)
+ goto clean_up2;
mmc_add_host(mmc);
+ sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
+
ret = request_irq(irq[0], sh_mmcif_intr, 0, "sh_mmc:error", host);
if (ret) {
dev_err(&pdev->dev, "request_irq error (sh_mmc:error)\n");
- goto clean_up2;
+ goto clean_up3;
}
ret = request_irq(irq[1], sh_mmcif_intr, 0, "sh_mmc:int", host);
if (ret) {
free_irq(irq[0], host);
dev_err(&pdev->dev, "request_irq error (sh_mmc:int)\n");
- goto clean_up2;
+ goto clean_up3;
}
- sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
sh_mmcif_detect(host->mmc);
dev_info(&pdev->dev, "driver version %s\n", DRIVER_VERSION);
@@ -1045,7 +1098,11 @@
sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0x0000ffff);
return ret;
+clean_up3:
+ mmc_remove_host(mmc);
+ pm_runtime_suspend(&pdev->dev);
clean_up2:
+ pm_runtime_disable(&pdev->dev);
clk_disable(host->hclk);
clean_up1:
mmc_free_host(mmc);
@@ -1060,14 +1117,14 @@
struct sh_mmcif_host *host = platform_get_drvdata(pdev);
int irq[2];
+ pm_runtime_get_sync(&pdev->dev);
+
mmc_remove_host(host->mmc);
- sh_mmcif_release_dma(host);
+ sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
if (host->addr)
iounmap(host->addr);
- sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
-
irq[0] = platform_get_irq(pdev, 0);
irq[1] = platform_get_irq(pdev, 1);
@@ -1078,15 +1135,52 @@
clk_disable(host->hclk);
mmc_free_host(host->mmc);
+ pm_runtime_put_sync(&pdev->dev);
+ pm_runtime_disable(&pdev->dev);
return 0;
}
+#ifdef CONFIG_PM
+static int sh_mmcif_suspend(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct sh_mmcif_host *host = platform_get_drvdata(pdev);
+ int ret = mmc_suspend_host(host->mmc);
+
+ if (!ret) {
+ sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
+ clk_disable(host->hclk);
+ }
+
+ return ret;
+}
+
+static int sh_mmcif_resume(struct device *dev)
+{
+ struct platform_device *pdev = to_platform_device(dev);
+ struct sh_mmcif_host *host = platform_get_drvdata(pdev);
+
+ clk_enable(host->hclk);
+
+ return mmc_resume_host(host->mmc);
+}
+#else
+#define sh_mmcif_suspend NULL
+#define sh_mmcif_resume NULL
+#endif /* CONFIG_PM */
+
+static const struct dev_pm_ops sh_mmcif_dev_pm_ops = {
+ .suspend = sh_mmcif_suspend,
+ .resume = sh_mmcif_resume,
+};
+
static struct platform_driver sh_mmcif_driver = {
.probe = sh_mmcif_probe,
.remove = sh_mmcif_remove,
.driver = {
.name = DRIVER_NAME,
+ .pm = &sh_mmcif_dev_pm_ops,
},
};
diff --git a/drivers/mmc/host/sh_mobile_sdhi.c b/drivers/mmc/host/sh_mobile_sdhi.c
index cc70123..b365429 100644
--- a/drivers/mmc/host/sh_mobile_sdhi.c
+++ b/drivers/mmc/host/sh_mobile_sdhi.c
@@ -62,7 +62,7 @@
struct sh_mobile_sdhi_info *p = pdev->dev.platform_data;
struct tmio_mmc_host *host;
char clk_name[8];
- int ret;
+ int i, irq, ret;
priv = kzalloc(sizeof(struct sh_mobile_sdhi), GFP_KERNEL);
if (priv == NULL) {
@@ -71,6 +71,7 @@
}
mmc_data = &priv->mmc_data;
+ p->pdata = mmc_data;
snprintf(clk_name, sizeof(clk_name), "sdhi%d", pdev->id);
priv->clk = clk_get(&pdev->dev, clk_name);
@@ -116,11 +117,36 @@
if (ret < 0)
goto eprobe;
- pr_info("%s at 0x%08lx irq %d\n", mmc_hostname(host->mmc),
- (unsigned long)host->ctl, host->irq);
+ for (i = 0; i < 3; i++) {
+ irq = platform_get_irq(pdev, i);
+ if (irq < 0) {
+ if (i) {
+ continue;
+ } else {
+ ret = irq;
+ goto eirq;
+ }
+ }
+ ret = request_irq(irq, tmio_mmc_irq, 0,
+ dev_name(&pdev->dev), host);
+ if (ret) {
+ while (i--) {
+ irq = platform_get_irq(pdev, i);
+ if (irq >= 0)
+ free_irq(irq, host);
+ }
+ goto eirq;
+ }
+ }
+ dev_info(&pdev->dev, "%s base at 0x%08lx clock rate %u MHz\n",
+ mmc_hostname(host->mmc), (unsigned long)
+ (platform_get_resource(pdev,IORESOURCE_MEM, 0)->start),
+ mmc_data->hclk / 1000000);
return ret;
+eirq:
+ tmio_mmc_host_remove(host);
eprobe:
clk_disable(priv->clk);
clk_put(priv->clk);
@@ -134,6 +160,16 @@
struct mmc_host *mmc = platform_get_drvdata(pdev);
struct tmio_mmc_host *host = mmc_priv(mmc);
struct sh_mobile_sdhi *priv = container_of(host->pdata, struct sh_mobile_sdhi, mmc_data);
+ struct sh_mobile_sdhi_info *p = pdev->dev.platform_data;
+ int i, irq;
+
+ p->pdata = NULL;
+
+ for (i = 0; i < 3; i++) {
+ irq = platform_get_irq(pdev, i);
+ if (irq >= 0)
+ free_irq(irq, host);
+ }
tmio_mmc_host_remove(host);
clk_disable(priv->clk);
@@ -143,10 +179,18 @@
return 0;
}
+static const struct dev_pm_ops tmio_mmc_dev_pm_ops = {
+ .suspend = tmio_mmc_host_suspend,
+ .resume = tmio_mmc_host_resume,
+ .runtime_suspend = tmio_mmc_host_runtime_suspend,
+ .runtime_resume = tmio_mmc_host_runtime_resume,
+};
+
static struct platform_driver sh_mobile_sdhi_driver = {
.driver = {
.name = "sh_mobile_sdhi",
.owner = THIS_MODULE,
+ .pm = &tmio_mmc_dev_pm_ops,
},
.probe = sh_mobile_sdhi_probe,
.remove = __devexit_p(sh_mobile_sdhi_remove),
diff --git a/drivers/mmc/host/tmio_mmc.c b/drivers/mmc/host/tmio_mmc.c
index 79c5684..14479f9 100644
--- a/drivers/mmc/host/tmio_mmc.c
+++ b/drivers/mmc/host/tmio_mmc.c
@@ -30,7 +30,7 @@
struct mmc_host *mmc = platform_get_drvdata(dev);
int ret;
- ret = mmc_suspend_host(mmc);
+ ret = tmio_mmc_host_suspend(&dev->dev);
/* Tell MFD core it can disable us now.*/
if (!ret && cell->disable)
@@ -46,15 +46,12 @@
int ret = 0;
/* Tell the MFD core we are ready to be enabled */
- if (cell->resume) {
+ if (cell->resume)
ret = cell->resume(dev);
- if (ret)
- goto out;
- }
- mmc_resume_host(mmc);
+ if (!ret)
+ ret = tmio_mmc_host_resume(&dev->dev);
-out:
return ret;
}
#else
@@ -67,7 +64,7 @@
const struct mfd_cell *cell = mfd_get_cell(pdev);
struct tmio_mmc_data *pdata;
struct tmio_mmc_host *host;
- int ret = -EINVAL;
+ int ret = -EINVAL, irq;
if (pdev->num_resources != 2)
goto out;
@@ -76,6 +73,12 @@
if (!pdata || !pdata->hclk)
goto out;
+ irq = platform_get_irq(pdev, 0);
+ if (irq < 0) {
+ ret = irq;
+ goto out;
+ }
+
/* Tell the MFD core we are ready to be enabled */
if (cell->enable) {
ret = cell->enable(pdev);
@@ -87,11 +90,18 @@
if (ret)
goto cell_disable;
+ ret = request_irq(irq, tmio_mmc_irq, IRQF_DISABLED |
+ IRQF_TRIGGER_FALLING, dev_name(&pdev->dev), host);
+ if (ret)
+ goto host_remove;
+
pr_info("%s at 0x%08lx irq %d\n", mmc_hostname(host->mmc),
- (unsigned long)host->ctl, host->irq);
+ (unsigned long)host->ctl, irq);
return 0;
+host_remove:
+ tmio_mmc_host_remove(host);
cell_disable:
if (cell->disable)
cell->disable(pdev);
@@ -107,7 +117,9 @@
platform_set_drvdata(pdev, NULL);
if (mmc) {
- tmio_mmc_host_remove(mmc_priv(mmc));
+ struct tmio_mmc_host *host = mmc_priv(mmc);
+ free_irq(platform_get_irq(pdev, 0), host);
+ tmio_mmc_host_remove(host);
if (cell->disable)
cell->disable(pdev);
}
diff --git a/drivers/mmc/host/tmio_mmc.h b/drivers/mmc/host/tmio_mmc.h
index 099ed49..8260bc2 100644
--- a/drivers/mmc/host/tmio_mmc.h
+++ b/drivers/mmc/host/tmio_mmc.h
@@ -19,6 +19,7 @@
#include <linux/highmem.h>
#include <linux/mmc/tmio.h>
#include <linux/pagemap.h>
+#include <linux/spinlock.h>
/* Definitions for values the CTRL_SDIO_STATUS register can take. */
#define TMIO_SDIO_STAT_IOIRQ 0x0001
@@ -44,13 +45,14 @@
struct mmc_request *mrq;
struct mmc_data *data;
struct mmc_host *mmc;
- int irq;
unsigned int sdio_irq_enabled;
/* Callbacks for clock / power control */
void (*set_pwr)(struct platform_device *host, int state);
void (*set_clk_div)(struct platform_device *host, int state);
+ int pm_error;
+
/* pio related stuff */
struct scatterlist *sg_ptr;
struct scatterlist *sg_orig;
@@ -83,6 +85,7 @@
void tmio_mmc_enable_mmc_irqs(struct tmio_mmc_host *host, u32 i);
void tmio_mmc_disable_mmc_irqs(struct tmio_mmc_host *host, u32 i);
+irqreturn_t tmio_mmc_irq(int irq, void *devid);
static inline char *tmio_mmc_kmap_atomic(struct scatterlist *sg,
unsigned long *flags)
@@ -120,4 +123,15 @@
}
#endif
+#ifdef CONFIG_PM
+int tmio_mmc_host_suspend(struct device *dev);
+int tmio_mmc_host_resume(struct device *dev);
+#else
+#define tmio_mmc_host_suspend NULL
+#define tmio_mmc_host_resume NULL
+#endif
+
+int tmio_mmc_host_runtime_suspend(struct device *dev);
+int tmio_mmc_host_runtime_resume(struct device *dev);
+
#endif
diff --git a/drivers/mmc/host/tmio_mmc_dma.c b/drivers/mmc/host/tmio_mmc_dma.c
index d3de74a..25f1ad6 100644
--- a/drivers/mmc/host/tmio_mmc_dma.c
+++ b/drivers/mmc/host/tmio_mmc_dma.c
@@ -256,7 +256,10 @@
void tmio_mmc_request_dma(struct tmio_mmc_host *host, struct tmio_mmc_data *pdata)
{
/* We can only either use DMA for both Tx and Rx or not use it at all */
- if (pdata->dma) {
+ if (!pdata->dma)
+ return;
+
+ if (!host->chan_tx && !host->chan_rx) {
dma_cap_mask_t mask;
dma_cap_zero(mask);
@@ -284,18 +287,18 @@
tasklet_init(&host->dma_complete, tmio_mmc_tasklet_fn, (unsigned long)host);
tasklet_init(&host->dma_issue, tmio_mmc_issue_tasklet_fn, (unsigned long)host);
-
- tmio_mmc_enable_dma(host, true);
-
- return;
-ebouncebuf:
- dma_release_channel(host->chan_rx);
- host->chan_rx = NULL;
-ereqrx:
- dma_release_channel(host->chan_tx);
- host->chan_tx = NULL;
- return;
}
+
+ tmio_mmc_enable_dma(host, true);
+
+ return;
+
+ebouncebuf:
+ dma_release_channel(host->chan_rx);
+ host->chan_rx = NULL;
+ereqrx:
+ dma_release_channel(host->chan_tx);
+ host->chan_tx = NULL;
}
void tmio_mmc_release_dma(struct tmio_mmc_host *host)
diff --git a/drivers/mmc/host/tmio_mmc_pio.c b/drivers/mmc/host/tmio_mmc_pio.c
index 710339a..ad6347b 100644
--- a/drivers/mmc/host/tmio_mmc_pio.c
+++ b/drivers/mmc/host/tmio_mmc_pio.c
@@ -39,6 +39,7 @@
#include <linux/module.h>
#include <linux/pagemap.h>
#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
#include <linux/scatterlist.h>
#include <linux/workqueue.h>
#include <linux/spinlock.h>
@@ -243,8 +244,12 @@
spin_lock_irqsave(&host->lock, flags);
mrq = host->mrq;
- /* request already finished */
- if (!mrq
+ /*
+ * is request already finished? Since we use a non-blocking
+ * cancel_delayed_work(), it can happen, that a .set_ios() call preempts
+ * us, so, have to check for IS_ERR(host->mrq)
+ */
+ if (IS_ERR_OR_NULL(mrq)
|| time_is_after_jiffies(host->last_req_ts +
msecs_to_jiffies(2000))) {
spin_unlock_irqrestore(&host->lock, flags);
@@ -264,16 +269,19 @@
host->cmd = NULL;
host->data = NULL;
- host->mrq = NULL;
host->force_pio = false;
spin_unlock_irqrestore(&host->lock, flags);
tmio_mmc_reset(host);
+ /* Ready for new calls */
+ host->mrq = NULL;
+
mmc_request_done(host->mmc, mrq);
}
+/* called with host->lock held, interrupts disabled */
static void tmio_mmc_finish_request(struct tmio_mmc_host *host)
{
struct mmc_request *mrq = host->mrq;
@@ -281,13 +289,15 @@
if (!mrq)
return;
- host->mrq = NULL;
host->cmd = NULL;
host->data = NULL;
host->force_pio = false;
cancel_delayed_work(&host->delayed_reset_work);
+ host->mrq = NULL;
+
+ /* FIXME: mmc_request_done() can schedule! */
mmc_request_done(host->mmc, mrq);
}
@@ -554,7 +564,7 @@
spin_unlock(&host->lock);
}
-static irqreturn_t tmio_mmc_irq(int irq, void *devid)
+irqreturn_t tmio_mmc_irq(int irq, void *devid)
{
struct tmio_mmc_host *host = devid;
struct tmio_mmc_data *pdata = host->pdata;
@@ -649,6 +659,7 @@
out:
return IRQ_HANDLED;
}
+EXPORT_SYMBOL(tmio_mmc_irq);
static int tmio_mmc_start_data(struct tmio_mmc_host *host,
struct mmc_data *data)
@@ -685,15 +696,27 @@
static void tmio_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
{
struct tmio_mmc_host *host = mmc_priv(mmc);
+ unsigned long flags;
int ret;
- if (host->mrq)
+ spin_lock_irqsave(&host->lock, flags);
+
+ if (host->mrq) {
pr_debug("request not null\n");
+ if (IS_ERR(host->mrq)) {
+ spin_unlock_irqrestore(&host->lock, flags);
+ mrq->cmd->error = -EAGAIN;
+ mmc_request_done(mmc, mrq);
+ return;
+ }
+ }
host->last_req_ts = jiffies;
wmb();
host->mrq = mrq;
+ spin_unlock_irqrestore(&host->lock, flags);
+
if (mrq->data) {
ret = tmio_mmc_start_data(host, mrq->data);
if (ret)
@@ -708,8 +731,8 @@
}
fail:
- host->mrq = NULL;
host->force_pio = false;
+ host->mrq = NULL;
mrq->cmd->error = ret;
mmc_request_done(mmc, mrq);
}
@@ -723,19 +746,54 @@
static void tmio_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
{
struct tmio_mmc_host *host = mmc_priv(mmc);
+ struct tmio_mmc_data *pdata = host->pdata;
+ unsigned long flags;
+
+ spin_lock_irqsave(&host->lock, flags);
+ if (host->mrq) {
+ if (IS_ERR(host->mrq)) {
+ dev_dbg(&host->pdev->dev,
+ "%s.%d: concurrent .set_ios(), clk %u, mode %u\n",
+ current->comm, task_pid_nr(current),
+ ios->clock, ios->power_mode);
+ host->mrq = ERR_PTR(-EINTR);
+ } else {
+ dev_dbg(&host->pdev->dev,
+ "%s.%d: CMD%u active since %lu, now %lu!\n",
+ current->comm, task_pid_nr(current),
+ host->mrq->cmd->opcode, host->last_req_ts, jiffies);
+ }
+ spin_unlock_irqrestore(&host->lock, flags);
+ return;
+ }
+
+ host->mrq = ERR_PTR(-EBUSY);
+
+ spin_unlock_irqrestore(&host->lock, flags);
if (ios->clock)
tmio_mmc_set_clock(host, ios->clock);
/* Power sequence - OFF -> UP -> ON */
if (ios->power_mode == MMC_POWER_UP) {
+ if ((pdata->flags & TMIO_MMC_HAS_COLD_CD) && !pdata->power) {
+ pm_runtime_get_sync(&host->pdev->dev);
+ pdata->power = true;
+ }
/* power up SD bus */
if (host->set_pwr)
host->set_pwr(host->pdev, 1);
} else if (ios->power_mode == MMC_POWER_OFF || !ios->clock) {
/* power down SD bus */
- if (ios->power_mode == MMC_POWER_OFF && host->set_pwr)
- host->set_pwr(host->pdev, 0);
+ if (ios->power_mode == MMC_POWER_OFF) {
+ if (host->set_pwr)
+ host->set_pwr(host->pdev, 0);
+ if ((pdata->flags & TMIO_MMC_HAS_COLD_CD) &&
+ pdata->power) {
+ pdata->power = false;
+ pm_runtime_put(&host->pdev->dev);
+ }
+ }
tmio_mmc_clk_stop(host);
} else {
/* start bus clock */
@@ -753,6 +811,12 @@
/* Let things settle. delay taken from winCE driver */
udelay(140);
+ if (PTR_ERR(host->mrq) == -EINTR)
+ dev_dbg(&host->pdev->dev,
+ "%s.%d: IOS interrupted: clk %u, mode %u",
+ current->comm, task_pid_nr(current),
+ ios->clock, ios->power_mode);
+ host->mrq = NULL;
}
static int tmio_mmc_get_ro(struct mmc_host *mmc)
@@ -801,6 +865,7 @@
if (!mmc)
return -ENOMEM;
+ pdata->dev = &pdev->dev;
_host = mmc_priv(mmc);
_host->pdata = pdata;
_host->mmc = mmc;
@@ -834,24 +899,19 @@
else
mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
+ pdata->power = false;
+ pm_runtime_enable(&pdev->dev);
+ ret = pm_runtime_resume(&pdev->dev);
+ if (ret < 0)
+ goto pm_disable;
+
tmio_mmc_clk_stop(_host);
tmio_mmc_reset(_host);
- ret = platform_get_irq(pdev, 0);
- if (ret < 0)
- goto unmap_ctl;
-
- _host->irq = ret;
-
tmio_mmc_disable_mmc_irqs(_host, TMIO_MASK_ALL);
if (pdata->flags & TMIO_MMC_SDIO_IRQ)
tmio_mmc_enable_sdio_irq(mmc, 0);
- ret = request_irq(_host->irq, tmio_mmc_irq, IRQF_DISABLED |
- IRQF_TRIGGER_FALLING, dev_name(&pdev->dev), _host);
- if (ret)
- goto unmap_ctl;
-
spin_lock_init(&_host->lock);
/* Init delayed work for request timeouts */
@@ -860,6 +920,10 @@
/* See if we also get DMA */
tmio_mmc_request_dma(_host, pdata);
+ /* We have to keep the device powered for its card detection to work */
+ if (!(pdata->flags & TMIO_MMC_HAS_COLD_CD))
+ pm_runtime_get_noresume(&pdev->dev);
+
mmc_add_host(mmc);
/* Unmask the IRQs we want to know about */
@@ -874,7 +938,8 @@
return 0;
-unmap_ctl:
+pm_disable:
+ pm_runtime_disable(&pdev->dev);
iounmap(_host->ctl);
host_free:
mmc_free_host(mmc);
@@ -885,13 +950,88 @@
void tmio_mmc_host_remove(struct tmio_mmc_host *host)
{
+ struct platform_device *pdev = host->pdev;
+
+ /*
+ * We don't have to manipulate pdata->power here: if there is a card in
+ * the slot, the runtime PM is active and our .runtime_resume() will not
+ * be run. If there is no card in the slot and the platform can suspend
+ * the controller, the runtime PM is suspended and pdata->power == false,
+ * so, our .runtime_resume() will not try to detect a card in the slot.
+ */
+ if (host->pdata->flags & TMIO_MMC_HAS_COLD_CD)
+ pm_runtime_get_sync(&pdev->dev);
+
mmc_remove_host(host->mmc);
cancel_delayed_work_sync(&host->delayed_reset_work);
tmio_mmc_release_dma(host);
- free_irq(host->irq, host);
+
+ pm_runtime_put_sync(&pdev->dev);
+ pm_runtime_disable(&pdev->dev);
+
iounmap(host->ctl);
mmc_free_host(host->mmc);
}
EXPORT_SYMBOL(tmio_mmc_host_remove);
+#ifdef CONFIG_PM
+int tmio_mmc_host_suspend(struct device *dev)
+{
+ struct mmc_host *mmc = dev_get_drvdata(dev);
+ struct tmio_mmc_host *host = mmc_priv(mmc);
+ int ret = mmc_suspend_host(mmc);
+
+ if (!ret)
+ tmio_mmc_disable_mmc_irqs(host, TMIO_MASK_ALL);
+
+ host->pm_error = pm_runtime_put_sync(dev);
+
+ return ret;
+}
+EXPORT_SYMBOL(tmio_mmc_host_suspend);
+
+int tmio_mmc_host_resume(struct device *dev)
+{
+ struct mmc_host *mmc = dev_get_drvdata(dev);
+ struct tmio_mmc_host *host = mmc_priv(mmc);
+
+ /* The MMC core will perform the complete set up */
+ host->pdata->power = false;
+
+ if (!host->pm_error)
+ pm_runtime_get_sync(dev);
+
+ tmio_mmc_reset(mmc_priv(mmc));
+ tmio_mmc_request_dma(host, host->pdata);
+
+ return mmc_resume_host(mmc);
+}
+EXPORT_SYMBOL(tmio_mmc_host_resume);
+
+#endif /* CONFIG_PM */
+
+int tmio_mmc_host_runtime_suspend(struct device *dev)
+{
+ return 0;
+}
+EXPORT_SYMBOL(tmio_mmc_host_runtime_suspend);
+
+int tmio_mmc_host_runtime_resume(struct device *dev)
+{
+ struct mmc_host *mmc = dev_get_drvdata(dev);
+ struct tmio_mmc_host *host = mmc_priv(mmc);
+ struct tmio_mmc_data *pdata = host->pdata;
+
+ tmio_mmc_reset(host);
+
+ if (pdata->power) {
+ /* Only entered after a card-insert interrupt */
+ tmio_mmc_set_ios(mmc, &mmc->ios);
+ mmc_detect_change(mmc, msecs_to_jiffies(100));
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(tmio_mmc_host_runtime_resume);
+
MODULE_LICENSE("GPL v2");
diff --git a/drivers/mmc/host/vub300.c b/drivers/mmc/host/vub300.c
new file mode 100644
index 0000000..cbb0330
--- /dev/null
+++ b/drivers/mmc/host/vub300.c
@@ -0,0 +1,2506 @@
+/*
+ * Remote VUB300 SDIO/SDmem Host Controller Driver
+ *
+ * Copyright (C) 2010 Elan Digital Systems Limited
+ *
+ * based on USB Skeleton driver - 2.2
+ *
+ * Copyright (C) 2001-2004 Greg Kroah-Hartman (greg@kroah.com)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation, version 2
+ *
+ * VUB300: is a USB 2.0 client device with a single SDIO/SDmem/MMC slot
+ * Any SDIO/SDmem/MMC device plugged into the VUB300 will appear,
+ * by virtue of this driver, to have been plugged into a local
+ * SDIO host controller, similar to, say, a PCI Ricoh controller
+ * This is because this kernel device driver is both a USB 2.0
+ * client device driver AND an MMC host controller driver. Thus
+ * if there is an existing driver for the inserted SDIO/SDmem/MMC
+ * device then that driver will be used by the kernel to manage
+ * the device in exactly the same fashion as if it had been
+ * directly plugged into, say, a local pci bus Ricoh controller
+ *
+ * RANT: this driver was written using a display 128x48 - converting it
+ * to a line width of 80 makes it very difficult to support. In
+ * particular functions have been broken down into sub functions
+ * and the original meaningful names have been shortened into
+ * cryptic ones.
+ * The problem is that executing a fragment of code subject to
+ * two conditions means an indentation of 24, thus leaving only
+ * 56 characters for a C statement. And that is quite ridiculous!
+ *
+ * Data types: data passed to/from the VUB300 is fixed to a number of
+ * bits and driver data fields reflect that limit by using
+ * u8, u16, u32
+ */
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/module.h>
+#include <linux/kref.h>
+#include <linux/uaccess.h>
+#include <linux/usb.h>
+#include <linux/mutex.h>
+#include <linux/mmc/host.h>
+#include <linux/mmc/card.h>
+#include <linux/mmc/sdio_func.h>
+#include <linux/mmc/sdio_ids.h>
+#include <linux/workqueue.h>
+#include <linux/ctype.h>
+#include <linux/firmware.h>
+#include <linux/scatterlist.h>
+
+struct host_controller_info {
+ u8 info_size;
+ u16 firmware_version;
+ u8 number_of_ports;
+} __packed;
+
+#define FIRMWARE_BLOCK_BOUNDARY 1024
+struct sd_command_header {
+ u8 header_size;
+ u8 header_type;
+ u8 port_number;
+ u8 command_type; /* Bit7 - Rd/Wr */
+ u8 command_index;
+ u8 transfer_size[4]; /* ReadSize + ReadSize */
+ u8 response_type;
+ u8 arguments[4];
+ u8 block_count[2];
+ u8 block_size[2];
+ u8 block_boundary[2];
+ u8 reserved[44]; /* to pad out to 64 bytes */
+} __packed;
+
+struct sd_irqpoll_header {
+ u8 header_size;
+ u8 header_type;
+ u8 port_number;
+ u8 command_type; /* Bit7 - Rd/Wr */
+ u8 padding[16]; /* don't ask why !! */
+ u8 poll_timeout_msb;
+ u8 poll_timeout_lsb;
+ u8 reserved[42]; /* to pad out to 64 bytes */
+} __packed;
+
+struct sd_common_header {
+ u8 header_size;
+ u8 header_type;
+ u8 port_number;
+} __packed;
+
+struct sd_response_header {
+ u8 header_size;
+ u8 header_type;
+ u8 port_number;
+ u8 command_type;
+ u8 command_index;
+ u8 command_response[0];
+} __packed;
+
+struct sd_status_header {
+ u8 header_size;
+ u8 header_type;
+ u8 port_number;
+ u16 port_flags;
+ u32 sdio_clock;
+ u16 host_header_size;
+ u16 func_header_size;
+ u16 ctrl_header_size;
+} __packed;
+
+struct sd_error_header {
+ u8 header_size;
+ u8 header_type;
+ u8 port_number;
+ u8 error_code;
+} __packed;
+
+struct sd_interrupt_header {
+ u8 header_size;
+ u8 header_type;
+ u8 port_number;
+} __packed;
+
+struct offload_registers_access {
+ u8 command_byte[4];
+ u8 Respond_Byte[4];
+} __packed;
+
+#define INTERRUPT_REGISTER_ACCESSES 15
+struct sd_offloaded_interrupt {
+ u8 header_size;
+ u8 header_type;
+ u8 port_number;
+ struct offload_registers_access reg[INTERRUPT_REGISTER_ACCESSES];
+} __packed;
+
+struct sd_register_header {
+ u8 header_size;
+ u8 header_type;
+ u8 port_number;
+ u8 command_type;
+ u8 command_index;
+ u8 command_response[6];
+} __packed;
+
+#define PIGGYBACK_REGISTER_ACCESSES 14
+struct sd_offloaded_piggyback {
+ struct sd_register_header sdio;
+ struct offload_registers_access reg[PIGGYBACK_REGISTER_ACCESSES];
+} __packed;
+
+union sd_response {
+ struct sd_common_header common;
+ struct sd_status_header status;
+ struct sd_error_header error;
+ struct sd_interrupt_header interrupt;
+ struct sd_response_header response;
+ struct sd_offloaded_interrupt irq;
+ struct sd_offloaded_piggyback pig;
+} __packed;
+
+union sd_command {
+ struct sd_command_header head;
+ struct sd_irqpoll_header poll;
+} __packed;
+
+enum SD_RESPONSE_TYPE {
+ SDRT_UNSPECIFIED = 0,
+ SDRT_NONE,
+ SDRT_1,
+ SDRT_1B,
+ SDRT_2,
+ SDRT_3,
+ SDRT_4,
+ SDRT_5,
+ SDRT_5B,
+ SDRT_6,
+ SDRT_7,
+};
+
+#define RESPONSE_INTERRUPT 0x01
+#define RESPONSE_ERROR 0x02
+#define RESPONSE_STATUS 0x03
+#define RESPONSE_IRQ_DISABLED 0x05
+#define RESPONSE_IRQ_ENABLED 0x06
+#define RESPONSE_PIGGYBACKED 0x07
+#define RESPONSE_NO_INTERRUPT 0x08
+#define RESPONSE_PIG_DISABLED 0x09
+#define RESPONSE_PIG_ENABLED 0x0A
+#define SD_ERROR_1BIT_TIMEOUT 0x01
+#define SD_ERROR_4BIT_TIMEOUT 0x02
+#define SD_ERROR_1BIT_CRC_WRONG 0x03
+#define SD_ERROR_4BIT_CRC_WRONG 0x04
+#define SD_ERROR_1BIT_CRC_ERROR 0x05
+#define SD_ERROR_4BIT_CRC_ERROR 0x06
+#define SD_ERROR_NO_CMD_ENDBIT 0x07
+#define SD_ERROR_NO_1BIT_DATEND 0x08
+#define SD_ERROR_NO_4BIT_DATEND 0x09
+#define SD_ERROR_1BIT_UNEXPECTED_TIMEOUT 0x0A
+#define SD_ERROR_4BIT_UNEXPECTED_TIMEOUT 0x0B
+#define SD_ERROR_ILLEGAL_COMMAND 0x0C
+#define SD_ERROR_NO_DEVICE 0x0D
+#define SD_ERROR_TRANSFER_LENGTH 0x0E
+#define SD_ERROR_1BIT_DATA_TIMEOUT 0x0F
+#define SD_ERROR_4BIT_DATA_TIMEOUT 0x10
+#define SD_ERROR_ILLEGAL_STATE 0x11
+#define SD_ERROR_UNKNOWN_ERROR 0x12
+#define SD_ERROR_RESERVED_ERROR 0x13
+#define SD_ERROR_INVALID_FUNCTION 0x14
+#define SD_ERROR_OUT_OF_RANGE 0x15
+#define SD_ERROR_STAT_CMD 0x16
+#define SD_ERROR_STAT_DATA 0x17
+#define SD_ERROR_STAT_CMD_TIMEOUT 0x18
+#define SD_ERROR_SDCRDY_STUCK 0x19
+#define SD_ERROR_UNHANDLED 0x1A
+#define SD_ERROR_OVERRUN 0x1B
+#define SD_ERROR_PIO_TIMEOUT 0x1C
+
+#define FUN(c) (0x000007 & (c->arg>>28))
+#define REG(c) (0x01FFFF & (c->arg>>9))
+
+static int limit_speed_to_24_MHz;
+module_param(limit_speed_to_24_MHz, bool, 0644);
+MODULE_PARM_DESC(limit_speed_to_24_MHz, "Limit Max SDIO Clock Speed to 24 MHz");
+
+static int pad_input_to_usb_pkt;
+module_param(pad_input_to_usb_pkt, bool, 0644);
+MODULE_PARM_DESC(pad_input_to_usb_pkt,
+ "Pad USB data input transfers to whole USB Packet");
+
+static int disable_offload_processing;
+module_param(disable_offload_processing, bool, 0644);
+MODULE_PARM_DESC(disable_offload_processing, "Disable Offload Processing");
+
+static int force_1_bit_data_xfers;
+module_param(force_1_bit_data_xfers, bool, 0644);
+MODULE_PARM_DESC(force_1_bit_data_xfers,
+ "Force SDIO Data Transfers to 1-bit Mode");
+
+static int force_polling_for_irqs;
+module_param(force_polling_for_irqs, bool, 0644);
+MODULE_PARM_DESC(force_polling_for_irqs, "Force Polling for SDIO interrupts");
+
+static int firmware_irqpoll_timeout = 1024;
+module_param(firmware_irqpoll_timeout, int, 0644);
+MODULE_PARM_DESC(firmware_irqpoll_timeout, "VUB300 firmware irqpoll timeout");
+
+static int force_max_req_size = 128;
+module_param(force_max_req_size, int, 0644);
+MODULE_PARM_DESC(force_max_req_size, "set max request size in kBytes");
+
+#ifdef SMSC_DEVELOPMENT_BOARD
+static int firmware_rom_wait_states = 0x04;
+#else
+static int firmware_rom_wait_states = 0x1C;
+#endif
+
+module_param(firmware_rom_wait_states, bool, 0644);
+MODULE_PARM_DESC(firmware_rom_wait_states,
+ "ROM wait states byte=RRRIIEEE (Reserved Internal External)");
+
+#define ELAN_VENDOR_ID 0x2201
+#define VUB300_VENDOR_ID 0x0424
+#define VUB300_PRODUCT_ID 0x012C
+static struct usb_device_id vub300_table[] = {
+ {USB_DEVICE(ELAN_VENDOR_ID, VUB300_PRODUCT_ID)},
+ {USB_DEVICE(VUB300_VENDOR_ID, VUB300_PRODUCT_ID)},
+ {} /* Terminating entry */
+};
+MODULE_DEVICE_TABLE(usb, vub300_table);
+
+static struct workqueue_struct *cmndworkqueue;
+static struct workqueue_struct *pollworkqueue;
+static struct workqueue_struct *deadworkqueue;
+
+static inline int interface_to_InterfaceNumber(struct usb_interface *interface)
+{
+ if (!interface)
+ return -1;
+ if (!interface->cur_altsetting)
+ return -1;
+ return interface->cur_altsetting->desc.bInterfaceNumber;
+}
+
+struct sdio_register {
+ unsigned func_num:3;
+ unsigned sdio_reg:17;
+ unsigned activate:1;
+ unsigned prepared:1;
+ unsigned regvalue:8;
+ unsigned response:8;
+ unsigned sparebit:26;
+};
+
+struct vub300_mmc_host {
+ struct usb_device *udev;
+ struct usb_interface *interface;
+ struct kref kref;
+ struct mutex cmd_mutex;
+ struct mutex irq_mutex;
+ char vub_name[3 + (9 * 8) + 4 + 1]; /* max of 7 sdio fn's */
+ u8 cmnd_out_ep; /* EndPoint for commands */
+ u8 cmnd_res_ep; /* EndPoint for responses */
+ u8 data_out_ep; /* EndPoint for out data */
+ u8 data_inp_ep; /* EndPoint for inp data */
+ bool card_powered;
+ bool card_present;
+ bool read_only;
+ bool large_usb_packets;
+ bool app_spec; /* ApplicationSpecific */
+ bool irq_enabled; /* by the MMC CORE */
+ bool irq_disabled; /* in the firmware */
+ unsigned bus_width:4;
+ u8 total_offload_count;
+ u8 dynamic_register_count;
+ u8 resp_len;
+ u32 datasize;
+ int errors;
+ int usb_transport_fail;
+ int usb_timed_out;
+ int irqs_queued;
+ struct sdio_register sdio_register[16];
+ struct offload_interrupt_function_register {
+#define MAXREGBITS 4
+#define MAXREGS (1<<MAXREGBITS)
+#define MAXREGMASK (MAXREGS-1)
+ u8 offload_count;
+ u32 offload_point;
+ struct offload_registers_access reg[MAXREGS];
+ } fn[8];
+ u16 fbs[8]; /* Function Block Size */
+ struct mmc_command *cmd;
+ struct mmc_request *req;
+ struct mmc_data *data;
+ struct mmc_host *mmc;
+ struct urb *urb;
+ struct urb *command_out_urb;
+ struct urb *command_res_urb;
+ struct completion command_complete;
+ struct completion irqpoll_complete;
+ union sd_command cmnd;
+ union sd_response resp;
+ struct timer_list sg_transfer_timer;
+ struct usb_sg_request sg_request;
+ struct timer_list inactivity_timer;
+ struct work_struct deadwork;
+ struct work_struct cmndwork;
+ struct delayed_work pollwork;
+ struct host_controller_info hc_info;
+ struct sd_status_header system_port_status;
+ u8 padded_buffer[64];
+};
+
+#define kref_to_vub300_mmc_host(d) container_of(d, struct vub300_mmc_host, kref)
+#define SET_TRANSFER_PSEUDOCODE 21
+#define SET_INTERRUPT_PSEUDOCODE 20
+#define SET_FAILURE_MODE 18
+#define SET_ROM_WAIT_STATES 16
+#define SET_IRQ_ENABLE 13
+#define SET_CLOCK_SPEED 11
+#define SET_FUNCTION_BLOCK_SIZE 9
+#define SET_SD_DATA_MODE 6
+#define SET_SD_POWER 4
+#define ENTER_DFU_MODE 3
+#define GET_HC_INF0 1
+#define GET_SYSTEM_PORT_STATUS 0
+
+static void vub300_delete(struct kref *kref)
+{ /* kref callback - softirq */
+ struct vub300_mmc_host *vub300 = kref_to_vub300_mmc_host(kref);
+ struct mmc_host *mmc = vub300->mmc;
+ usb_free_urb(vub300->command_out_urb);
+ vub300->command_out_urb = NULL;
+ usb_free_urb(vub300->command_res_urb);
+ vub300->command_res_urb = NULL;
+ usb_put_dev(vub300->udev);
+ mmc_free_host(mmc);
+ /*
+ * and hence also frees vub300
+ * which is contained at the end of struct mmc
+ */
+}
+
+static void vub300_queue_cmnd_work(struct vub300_mmc_host *vub300)
+{
+ kref_get(&vub300->kref);
+ if (queue_work(cmndworkqueue, &vub300->cmndwork)) {
+ /*
+ * then the cmndworkqueue was not previously
+ * running and the above get ref is obvious
+ * required and will be put when the thread
+ * terminates by a specific call
+ */
+ } else {
+ /*
+ * the cmndworkqueue was already running from
+ * a previous invocation and thus to keep the
+ * kref counts correct we must undo the get
+ */
+ kref_put(&vub300->kref, vub300_delete);
+ }
+}
+
+static void vub300_queue_poll_work(struct vub300_mmc_host *vub300, int delay)
+{
+ kref_get(&vub300->kref);
+ if (queue_delayed_work(pollworkqueue, &vub300->pollwork, delay)) {
+ /*
+ * then the pollworkqueue was not previously
+ * running and the above get ref is obvious
+ * required and will be put when the thread
+ * terminates by a specific call
+ */
+ } else {
+ /*
+ * the pollworkqueue was already running from
+ * a previous invocation and thus to keep the
+ * kref counts correct we must undo the get
+ */
+ kref_put(&vub300->kref, vub300_delete);
+ }
+}
+
+static void vub300_queue_dead_work(struct vub300_mmc_host *vub300)
+{
+ kref_get(&vub300->kref);
+ if (queue_work(deadworkqueue, &vub300->deadwork)) {
+ /*
+ * then the deadworkqueue was not previously
+ * running and the above get ref is obvious
+ * required and will be put when the thread
+ * terminates by a specific call
+ */
+ } else {
+ /*
+ * the deadworkqueue was already running from
+ * a previous invocation and thus to keep the
+ * kref counts correct we must undo the get
+ */
+ kref_put(&vub300->kref, vub300_delete);
+ }
+}
+
+static void irqpoll_res_completed(struct urb *urb)
+{ /* urb completion handler - hardirq */
+ struct vub300_mmc_host *vub300 = (struct vub300_mmc_host *)urb->context;
+ if (urb->status)
+ vub300->usb_transport_fail = urb->status;
+ complete(&vub300->irqpoll_complete);
+}
+
+static void irqpoll_out_completed(struct urb *urb)
+{ /* urb completion handler - hardirq */
+ struct vub300_mmc_host *vub300 = (struct vub300_mmc_host *)urb->context;
+ if (urb->status) {
+ vub300->usb_transport_fail = urb->status;
+ complete(&vub300->irqpoll_complete);
+ return;
+ } else {
+ int ret;
+ unsigned int pipe =
+ usb_rcvbulkpipe(vub300->udev, vub300->cmnd_res_ep);
+ usb_fill_bulk_urb(vub300->command_res_urb, vub300->udev, pipe,
+ &vub300->resp, sizeof(vub300->resp),
+ irqpoll_res_completed, vub300);
+ vub300->command_res_urb->actual_length = 0;
+ ret = usb_submit_urb(vub300->command_res_urb, GFP_ATOMIC);
+ if (ret) {
+ vub300->usb_transport_fail = ret;
+ complete(&vub300->irqpoll_complete);
+ }
+ return;
+ }
+}
+
+static void send_irqpoll(struct vub300_mmc_host *vub300)
+{
+ /* cmd_mutex is held by vub300_pollwork_thread */
+ int retval;
+ int timeout = 0xFFFF & (0x0001FFFF - firmware_irqpoll_timeout);
+ vub300->cmnd.poll.header_size = 22;
+ vub300->cmnd.poll.header_type = 1;
+ vub300->cmnd.poll.port_number = 0;
+ vub300->cmnd.poll.command_type = 2;
+ vub300->cmnd.poll.poll_timeout_lsb = 0xFF & (unsigned)timeout;
+ vub300->cmnd.poll.poll_timeout_msb = 0xFF & (unsigned)(timeout >> 8);
+ usb_fill_bulk_urb(vub300->command_out_urb, vub300->udev,
+ usb_sndbulkpipe(vub300->udev, vub300->cmnd_out_ep)
+ , &vub300->cmnd, sizeof(vub300->cmnd)
+ , irqpoll_out_completed, vub300);
+ retval = usb_submit_urb(vub300->command_out_urb, GFP_KERNEL);
+ if (0 > retval) {
+ vub300->usb_transport_fail = retval;
+ vub300_queue_poll_work(vub300, 1);
+ complete(&vub300->irqpoll_complete);
+ return;
+ } else {
+ return;
+ }
+}
+
+static void new_system_port_status(struct vub300_mmc_host *vub300)
+{
+ int old_card_present = vub300->card_present;
+ int new_card_present =
+ (0x0001 & vub300->system_port_status.port_flags) ? 1 : 0;
+ vub300->read_only =
+ (0x0010 & vub300->system_port_status.port_flags) ? 1 : 0;
+ if (new_card_present && !old_card_present) {
+ dev_info(&vub300->udev->dev, "card just inserted\n");
+ vub300->card_present = 1;
+ vub300->bus_width = 0;
+ if (disable_offload_processing)
+ strncpy(vub300->vub_name, "EMPTY Processing Disabled",
+ sizeof(vub300->vub_name));
+ else
+ vub300->vub_name[0] = 0;
+ mmc_detect_change(vub300->mmc, 1);
+ } else if (!new_card_present && old_card_present) {
+ dev_info(&vub300->udev->dev, "card just ejected\n");
+ vub300->card_present = 0;
+ mmc_detect_change(vub300->mmc, 0);
+ } else {
+ /* no change */
+ }
+}
+
+static void __add_offloaded_reg_to_fifo(struct vub300_mmc_host *vub300,
+ struct offload_registers_access
+ *register_access, u8 func)
+{
+ u8 r = vub300->fn[func].offload_point + vub300->fn[func].offload_count;
+ memcpy(&vub300->fn[func].reg[MAXREGMASK & r], register_access,
+ sizeof(struct offload_registers_access));
+ vub300->fn[func].offload_count += 1;
+ vub300->total_offload_count += 1;
+}
+
+static void add_offloaded_reg(struct vub300_mmc_host *vub300,
+ struct offload_registers_access *register_access)
+{
+ u32 Register = ((0x03 & register_access->command_byte[0]) << 15)
+ | ((0xFF & register_access->command_byte[1]) << 7)
+ | ((0xFE & register_access->command_byte[2]) >> 1);
+ u8 func = ((0x70 & register_access->command_byte[0]) >> 4);
+ u8 regs = vub300->dynamic_register_count;
+ u8 i = 0;
+ while (0 < regs-- && 1 == vub300->sdio_register[i].activate) {
+ if (vub300->sdio_register[i].func_num == func &&
+ vub300->sdio_register[i].sdio_reg == Register) {
+ if (vub300->sdio_register[i].prepared == 0)
+ vub300->sdio_register[i].prepared = 1;
+ vub300->sdio_register[i].response =
+ register_access->Respond_Byte[2];
+ vub300->sdio_register[i].regvalue =
+ register_access->Respond_Byte[3];
+ return;
+ } else {
+ i += 1;
+ continue;
+ }
+ };
+ __add_offloaded_reg_to_fifo(vub300, register_access, func);
+}
+
+static void check_vub300_port_status(struct vub300_mmc_host *vub300)
+{
+ /*
+ * cmd_mutex is held by vub300_pollwork_thread,
+ * vub300_deadwork_thread or vub300_cmndwork_thread
+ */
+ int retval;
+ retval =
+ usb_control_msg(vub300->udev, usb_rcvctrlpipe(vub300->udev, 0),
+ GET_SYSTEM_PORT_STATUS,
+ USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
+ 0x0000, 0x0000, &vub300->system_port_status,
+ sizeof(vub300->system_port_status), HZ);
+ if (sizeof(vub300->system_port_status) == retval)
+ new_system_port_status(vub300);
+}
+
+static void __vub300_irqpoll_response(struct vub300_mmc_host *vub300)
+{
+ /* cmd_mutex is held by vub300_pollwork_thread */
+ if (vub300->command_res_urb->actual_length == 0)
+ return;
+
+ switch (vub300->resp.common.header_type) {
+ case RESPONSE_INTERRUPT:
+ mutex_lock(&vub300->irq_mutex);
+ if (vub300->irq_enabled)
+ mmc_signal_sdio_irq(vub300->mmc);
+ else
+ vub300->irqs_queued += 1;
+ vub300->irq_disabled = 1;
+ mutex_unlock(&vub300->irq_mutex);
+ break;
+ case RESPONSE_ERROR:
+ if (vub300->resp.error.error_code == SD_ERROR_NO_DEVICE)
+ check_vub300_port_status(vub300);
+ break;
+ case RESPONSE_STATUS:
+ vub300->system_port_status = vub300->resp.status;
+ new_system_port_status(vub300);
+ if (!vub300->card_present)
+ vub300_queue_poll_work(vub300, HZ / 5);
+ break;
+ case RESPONSE_IRQ_DISABLED:
+ {
+ int offloaded_data_length = vub300->resp.common.header_size - 3;
+ int register_count = offloaded_data_length >> 3;
+ int ri = 0;
+ while (register_count--) {
+ add_offloaded_reg(vub300, &vub300->resp.irq.reg[ri]);
+ ri += 1;
+ }
+ mutex_lock(&vub300->irq_mutex);
+ if (vub300->irq_enabled)
+ mmc_signal_sdio_irq(vub300->mmc);
+ else
+ vub300->irqs_queued += 1;
+ vub300->irq_disabled = 1;
+ mutex_unlock(&vub300->irq_mutex);
+ break;
+ }
+ case RESPONSE_IRQ_ENABLED:
+ {
+ int offloaded_data_length = vub300->resp.common.header_size - 3;
+ int register_count = offloaded_data_length >> 3;
+ int ri = 0;
+ while (register_count--) {
+ add_offloaded_reg(vub300, &vub300->resp.irq.reg[ri]);
+ ri += 1;
+ }
+ mutex_lock(&vub300->irq_mutex);
+ if (vub300->irq_enabled)
+ mmc_signal_sdio_irq(vub300->mmc);
+ else if (vub300->irqs_queued)
+ vub300->irqs_queued += 1;
+ else
+ vub300->irqs_queued += 1;
+ vub300->irq_disabled = 0;
+ mutex_unlock(&vub300->irq_mutex);
+ break;
+ }
+ case RESPONSE_NO_INTERRUPT:
+ vub300_queue_poll_work(vub300, 1);
+ break;
+ default:
+ break;
+ }
+}
+
+static void __do_poll(struct vub300_mmc_host *vub300)
+{
+ /* cmd_mutex is held by vub300_pollwork_thread */
+ long commretval;
+ mod_timer(&vub300->inactivity_timer, jiffies + HZ);
+ init_completion(&vub300->irqpoll_complete);
+ send_irqpoll(vub300);
+ commretval = wait_for_completion_timeout(&vub300->irqpoll_complete,
+ msecs_to_jiffies(500));
+ if (vub300->usb_transport_fail) {
+ /* no need to do anything */
+ } else if (commretval == 0) {
+ vub300->usb_timed_out = 1;
+ usb_kill_urb(vub300->command_out_urb);
+ usb_kill_urb(vub300->command_res_urb);
+ } else if (commretval < 0) {
+ vub300_queue_poll_work(vub300, 1);
+ } else { /* commretval > 0 */
+ __vub300_irqpoll_response(vub300);
+ }
+}
+
+/* this thread runs only when the driver
+ * is trying to poll the device for an IRQ
+ */
+static void vub300_pollwork_thread(struct work_struct *work)
+{ /* NOT irq */
+ struct vub300_mmc_host *vub300 = container_of(work,
+ struct vub300_mmc_host, pollwork.work);
+ if (!vub300->interface) {
+ kref_put(&vub300->kref, vub300_delete);
+ return;
+ }
+ mutex_lock(&vub300->cmd_mutex);
+ if (vub300->cmd) {
+ vub300_queue_poll_work(vub300, 1);
+ } else if (!vub300->card_present) {
+ /* no need to do anything */
+ } else { /* vub300->card_present */
+ mutex_lock(&vub300->irq_mutex);
+ if (!vub300->irq_enabled) {
+ mutex_unlock(&vub300->irq_mutex);
+ } else if (vub300->irqs_queued) {
+ vub300->irqs_queued -= 1;
+ mmc_signal_sdio_irq(vub300->mmc);
+ mod_timer(&vub300->inactivity_timer, jiffies + HZ);
+ mutex_unlock(&vub300->irq_mutex);
+ } else { /* NOT vub300->irqs_queued */
+ mutex_unlock(&vub300->irq_mutex);
+ __do_poll(vub300);
+ }
+ }
+ mutex_unlock(&vub300->cmd_mutex);
+ kref_put(&vub300->kref, vub300_delete);
+}
+
+static void vub300_deadwork_thread(struct work_struct *work)
+{ /* NOT irq */
+ struct vub300_mmc_host *vub300 =
+ container_of(work, struct vub300_mmc_host, deadwork);
+ if (!vub300->interface) {
+ kref_put(&vub300->kref, vub300_delete);
+ return;
+ }
+ mutex_lock(&vub300->cmd_mutex);
+ if (vub300->cmd) {
+ /*
+ * a command got in as the inactivity
+ * timer expired - so we just let the
+ * processing of the command show if
+ * the device is dead
+ */
+ } else if (vub300->card_present) {
+ check_vub300_port_status(vub300);
+ } else if (vub300->mmc && vub300->mmc->card &&
+ mmc_card_present(vub300->mmc->card)) {
+ /*
+ * the MMC core must not have responded
+ * to the previous indication - lets
+ * hope that it eventually does so we
+ * will just ignore this for now
+ */
+ } else {
+ check_vub300_port_status(vub300);
+ }
+ mod_timer(&vub300->inactivity_timer, jiffies + HZ);
+ mutex_unlock(&vub300->cmd_mutex);
+ kref_put(&vub300->kref, vub300_delete);
+}
+
+static void vub300_inactivity_timer_expired(unsigned long data)
+{ /* softirq */
+ struct vub300_mmc_host *vub300 = (struct vub300_mmc_host *)data;
+ if (!vub300->interface) {
+ kref_put(&vub300->kref, vub300_delete);
+ } else if (vub300->cmd) {
+ mod_timer(&vub300->inactivity_timer, jiffies + HZ);
+ } else {
+ vub300_queue_dead_work(vub300);
+ mod_timer(&vub300->inactivity_timer, jiffies + HZ);
+ }
+}
+
+static int vub300_response_error(u8 error_code)
+{
+ switch (error_code) {
+ case SD_ERROR_PIO_TIMEOUT:
+ case SD_ERROR_1BIT_TIMEOUT:
+ case SD_ERROR_4BIT_TIMEOUT:
+ return -ETIMEDOUT;
+ case SD_ERROR_STAT_DATA:
+ case SD_ERROR_OVERRUN:
+ case SD_ERROR_STAT_CMD:
+ case SD_ERROR_STAT_CMD_TIMEOUT:
+ case SD_ERROR_SDCRDY_STUCK:
+ case SD_ERROR_UNHANDLED:
+ case SD_ERROR_1BIT_CRC_WRONG:
+ case SD_ERROR_4BIT_CRC_WRONG:
+ case SD_ERROR_1BIT_CRC_ERROR:
+ case SD_ERROR_4BIT_CRC_ERROR:
+ case SD_ERROR_NO_CMD_ENDBIT:
+ case SD_ERROR_NO_1BIT_DATEND:
+ case SD_ERROR_NO_4BIT_DATEND:
+ case SD_ERROR_1BIT_DATA_TIMEOUT:
+ case SD_ERROR_4BIT_DATA_TIMEOUT:
+ case SD_ERROR_1BIT_UNEXPECTED_TIMEOUT:
+ case SD_ERROR_4BIT_UNEXPECTED_TIMEOUT:
+ return -EILSEQ;
+ case 33:
+ return -EILSEQ;
+ case SD_ERROR_ILLEGAL_COMMAND:
+ return -EINVAL;
+ case SD_ERROR_NO_DEVICE:
+ return -ENOMEDIUM;
+ default:
+ return -ENODEV;
+ }
+}
+
+static void command_res_completed(struct urb *urb)
+{ /* urb completion handler - hardirq */
+ struct vub300_mmc_host *vub300 = (struct vub300_mmc_host *)urb->context;
+ if (urb->status) {
+ /* we have to let the initiator handle the error */
+ } else if (vub300->command_res_urb->actual_length == 0) {
+ /*
+ * we have seen this happen once or twice and
+ * we suspect a buggy USB host controller
+ */
+ } else if (!vub300->data) {
+ /* this means that the command (typically CMD52) suceeded */
+ } else if (vub300->resp.common.header_type != 0x02) {
+ /*
+ * this is an error response from the VUB300 chip
+ * and we let the initiator handle it
+ */
+ } else if (vub300->urb) {
+ vub300->cmd->error =
+ vub300_response_error(vub300->resp.error.error_code);
+ usb_unlink_urb(vub300->urb);
+ } else {
+ vub300->cmd->error =
+ vub300_response_error(vub300->resp.error.error_code);
+ usb_sg_cancel(&vub300->sg_request);
+ }
+ complete(&vub300->command_complete); /* got_response_in */
+}
+
+static void command_out_completed(struct urb *urb)
+{ /* urb completion handler - hardirq */
+ struct vub300_mmc_host *vub300 = (struct vub300_mmc_host *)urb->context;
+ if (urb->status) {
+ complete(&vub300->command_complete);
+ } else {
+ int ret;
+ unsigned int pipe =
+ usb_rcvbulkpipe(vub300->udev, vub300->cmnd_res_ep);
+ usb_fill_bulk_urb(vub300->command_res_urb, vub300->udev, pipe,
+ &vub300->resp, sizeof(vub300->resp),
+ command_res_completed, vub300);
+ vub300->command_res_urb->actual_length = 0;
+ ret = usb_submit_urb(vub300->command_res_urb, GFP_ATOMIC);
+ if (ret == 0) {
+ /*
+ * the urb completion handler will call
+ * our completion handler
+ */
+ } else {
+ /*
+ * and thus we only call it directly
+ * when it will not be called
+ */
+ complete(&vub300->command_complete);
+ }
+ }
+}
+
+/*
+ * the STUFF bits are masked out for the comparisons
+ */
+static void snoop_block_size_and_bus_width(struct vub300_mmc_host *vub300,
+ u32 cmd_arg)
+{
+ if ((0xFBFFFE00 & cmd_arg) == 0x80022200)
+ vub300->fbs[1] = (cmd_arg << 8) | (0x00FF & vub300->fbs[1]);
+ else if ((0xFBFFFE00 & cmd_arg) == 0x80022000)
+ vub300->fbs[1] = (0xFF & cmd_arg) | (0xFF00 & vub300->fbs[1]);
+ else if ((0xFBFFFE00 & cmd_arg) == 0x80042200)
+ vub300->fbs[2] = (cmd_arg << 8) | (0x00FF & vub300->fbs[2]);
+ else if ((0xFBFFFE00 & cmd_arg) == 0x80042000)
+ vub300->fbs[2] = (0xFF & cmd_arg) | (0xFF00 & vub300->fbs[2]);
+ else if ((0xFBFFFE00 & cmd_arg) == 0x80062200)
+ vub300->fbs[3] = (cmd_arg << 8) | (0x00FF & vub300->fbs[3]);
+ else if ((0xFBFFFE00 & cmd_arg) == 0x80062000)
+ vub300->fbs[3] = (0xFF & cmd_arg) | (0xFF00 & vub300->fbs[3]);
+ else if ((0xFBFFFE00 & cmd_arg) == 0x80082200)
+ vub300->fbs[4] = (cmd_arg << 8) | (0x00FF & vub300->fbs[4]);
+ else if ((0xFBFFFE00 & cmd_arg) == 0x80082000)
+ vub300->fbs[4] = (0xFF & cmd_arg) | (0xFF00 & vub300->fbs[4]);
+ else if ((0xFBFFFE00 & cmd_arg) == 0x800A2200)
+ vub300->fbs[5] = (cmd_arg << 8) | (0x00FF & vub300->fbs[5]);
+ else if ((0xFBFFFE00 & cmd_arg) == 0x800A2000)
+ vub300->fbs[5] = (0xFF & cmd_arg) | (0xFF00 & vub300->fbs[5]);
+ else if ((0xFBFFFE00 & cmd_arg) == 0x800C2200)
+ vub300->fbs[6] = (cmd_arg << 8) | (0x00FF & vub300->fbs[6]);
+ else if ((0xFBFFFE00 & cmd_arg) == 0x800C2000)
+ vub300->fbs[6] = (0xFF & cmd_arg) | (0xFF00 & vub300->fbs[6]);
+ else if ((0xFBFFFE00 & cmd_arg) == 0x800E2200)
+ vub300->fbs[7] = (cmd_arg << 8) | (0x00FF & vub300->fbs[7]);
+ else if ((0xFBFFFE00 & cmd_arg) == 0x800E2000)
+ vub300->fbs[7] = (0xFF & cmd_arg) | (0xFF00 & vub300->fbs[7]);
+ else if ((0xFBFFFE03 & cmd_arg) == 0x80000E00)
+ vub300->bus_width = 1;
+ else if ((0xFBFFFE03 & cmd_arg) == 0x80000E02)
+ vub300->bus_width = 4;
+}
+
+static void send_command(struct vub300_mmc_host *vub300)
+{
+ /* cmd_mutex is held by vub300_cmndwork_thread */
+ struct mmc_command *cmd = vub300->cmd;
+ struct mmc_data *data = vub300->data;
+ int retval;
+ int i;
+ u8 response_type;
+ if (vub300->app_spec) {
+ switch (cmd->opcode) {
+ case 6:
+ response_type = SDRT_1;
+ vub300->resp_len = 6;
+ if (0x00000000 == (0x00000003 & cmd->arg))
+ vub300->bus_width = 1;
+ else if (0x00000002 == (0x00000003 & cmd->arg))
+ vub300->bus_width = 4;
+ else
+ dev_err(&vub300->udev->dev,
+ "unexpected ACMD6 bus_width=%d\n",
+ 0x00000003 & cmd->arg);
+ break;
+ case 13:
+ response_type = SDRT_1;
+ vub300->resp_len = 6;
+ break;
+ case 22:
+ response_type = SDRT_1;
+ vub300->resp_len = 6;
+ break;
+ case 23:
+ response_type = SDRT_1;
+ vub300->resp_len = 6;
+ break;
+ case 41:
+ response_type = SDRT_3;
+ vub300->resp_len = 6;
+ break;
+ case 42:
+ response_type = SDRT_1;
+ vub300->resp_len = 6;
+ break;
+ case 51:
+ response_type = SDRT_1;
+ vub300->resp_len = 6;
+ break;
+ case 55:
+ response_type = SDRT_1;
+ vub300->resp_len = 6;
+ break;
+ default:
+ vub300->resp_len = 0;
+ cmd->error = -EINVAL;
+ complete(&vub300->command_complete);
+ return;
+ }
+ vub300->app_spec = 0;
+ } else {
+ switch (cmd->opcode) {
+ case 0:
+ response_type = SDRT_NONE;
+ vub300->resp_len = 0;
+ break;
+ case 1:
+ response_type = SDRT_3;
+ vub300->resp_len = 6;
+ break;
+ case 2:
+ response_type = SDRT_2;
+ vub300->resp_len = 17;
+ break;
+ case 3:
+ response_type = SDRT_6;
+ vub300->resp_len = 6;
+ break;
+ case 4:
+ response_type = SDRT_NONE;
+ vub300->resp_len = 0;
+ break;
+ case 5:
+ response_type = SDRT_4;
+ vub300->resp_len = 6;
+ break;
+ case 6:
+ response_type = SDRT_1;
+ vub300->resp_len = 6;
+ break;
+ case 7:
+ response_type = SDRT_1B;
+ vub300->resp_len = 6;
+ break;
+ case 8:
+ response_type = SDRT_7;
+ vub300->resp_len = 6;
+ break;
+ case 9:
+ response_type = SDRT_2;
+ vub300->resp_len = 17;
+ break;
+ case 10:
+ response_type = SDRT_2;
+ vub300->resp_len = 17;
+ break;
+ case 12:
+ response_type = SDRT_1B;
+ vub300->resp_len = 6;
+ break;
+ case 13:
+ response_type = SDRT_1;
+ vub300->resp_len = 6;
+ break;
+ case 15:
+ response_type = SDRT_NONE;
+ vub300->resp_len = 0;
+ break;
+ case 16:
+ for (i = 0; i < ARRAY_SIZE(vub300->fbs); i++)
+ vub300->fbs[i] = 0xFFFF & cmd->arg;
+ response_type = SDRT_1;
+ vub300->resp_len = 6;
+ break;
+ case 17:
+ case 18:
+ case 24:
+ case 25:
+ case 27:
+ response_type = SDRT_1;
+ vub300->resp_len = 6;
+ break;
+ case 28:
+ case 29:
+ response_type = SDRT_1B;
+ vub300->resp_len = 6;
+ break;
+ case 30:
+ case 32:
+ case 33:
+ response_type = SDRT_1;
+ vub300->resp_len = 6;
+ break;
+ case 38:
+ response_type = SDRT_1B;
+ vub300->resp_len = 6;
+ break;
+ case 42:
+ response_type = SDRT_1;
+ vub300->resp_len = 6;
+ break;
+ case 52:
+ response_type = SDRT_5;
+ vub300->resp_len = 6;
+ snoop_block_size_and_bus_width(vub300, cmd->arg);
+ break;
+ case 53:
+ response_type = SDRT_5;
+ vub300->resp_len = 6;
+ break;
+ case 55:
+ response_type = SDRT_1;
+ vub300->resp_len = 6;
+ vub300->app_spec = 1;
+ break;
+ case 56:
+ response_type = SDRT_1;
+ vub300->resp_len = 6;
+ break;
+ default:
+ vub300->resp_len = 0;
+ cmd->error = -EINVAL;
+ complete(&vub300->command_complete);
+ return;
+ }
+ }
+ /*
+ * it is a shame that we can not use "sizeof(struct sd_command_header)"
+ * this is because the packet _must_ be padded to 64 bytes
+ */
+ vub300->cmnd.head.header_size = 20;
+ vub300->cmnd.head.header_type = 0x00;
+ vub300->cmnd.head.port_number = 0; /* "0" means port 1 */
+ vub300->cmnd.head.command_type = 0x00; /* standard read command */
+ vub300->cmnd.head.response_type = response_type;
+ vub300->cmnd.head.command_index = cmd->opcode;
+ vub300->cmnd.head.arguments[0] = cmd->arg >> 24;
+ vub300->cmnd.head.arguments[1] = cmd->arg >> 16;
+ vub300->cmnd.head.arguments[2] = cmd->arg >> 8;
+ vub300->cmnd.head.arguments[3] = cmd->arg >> 0;
+ if (cmd->opcode == 52) {
+ int fn = 0x7 & (cmd->arg >> 28);
+ vub300->cmnd.head.block_count[0] = 0;
+ vub300->cmnd.head.block_count[1] = 0;
+ vub300->cmnd.head.block_size[0] = (vub300->fbs[fn] >> 8) & 0xFF;
+ vub300->cmnd.head.block_size[1] = (vub300->fbs[fn] >> 0) & 0xFF;
+ vub300->cmnd.head.command_type = 0x00;
+ vub300->cmnd.head.transfer_size[0] = 0;
+ vub300->cmnd.head.transfer_size[1] = 0;
+ vub300->cmnd.head.transfer_size[2] = 0;
+ vub300->cmnd.head.transfer_size[3] = 0;
+ } else if (!data) {
+ vub300->cmnd.head.block_count[0] = 0;
+ vub300->cmnd.head.block_count[1] = 0;
+ vub300->cmnd.head.block_size[0] = (vub300->fbs[0] >> 8) & 0xFF;
+ vub300->cmnd.head.block_size[1] = (vub300->fbs[0] >> 0) & 0xFF;
+ vub300->cmnd.head.command_type = 0x00;
+ vub300->cmnd.head.transfer_size[0] = 0;
+ vub300->cmnd.head.transfer_size[1] = 0;
+ vub300->cmnd.head.transfer_size[2] = 0;
+ vub300->cmnd.head.transfer_size[3] = 0;
+ } else if (cmd->opcode == 53) {
+ int fn = 0x7 & (cmd->arg >> 28);
+ if (0x08 & vub300->cmnd.head.arguments[0]) { /* BLOCK MODE */
+ vub300->cmnd.head.block_count[0] =
+ (data->blocks >> 8) & 0xFF;
+ vub300->cmnd.head.block_count[1] =
+ (data->blocks >> 0) & 0xFF;
+ vub300->cmnd.head.block_size[0] =
+ (data->blksz >> 8) & 0xFF;
+ vub300->cmnd.head.block_size[1] =
+ (data->blksz >> 0) & 0xFF;
+ } else { /* BYTE MODE */
+ vub300->cmnd.head.block_count[0] = 0;
+ vub300->cmnd.head.block_count[1] = 0;
+ vub300->cmnd.head.block_size[0] =
+ (vub300->datasize >> 8) & 0xFF;
+ vub300->cmnd.head.block_size[1] =
+ (vub300->datasize >> 0) & 0xFF;
+ }
+ vub300->cmnd.head.command_type =
+ (MMC_DATA_READ & data->flags) ? 0x00 : 0x80;
+ vub300->cmnd.head.transfer_size[0] =
+ (vub300->datasize >> 24) & 0xFF;
+ vub300->cmnd.head.transfer_size[1] =
+ (vub300->datasize >> 16) & 0xFF;
+ vub300->cmnd.head.transfer_size[2] =
+ (vub300->datasize >> 8) & 0xFF;
+ vub300->cmnd.head.transfer_size[3] =
+ (vub300->datasize >> 0) & 0xFF;
+ if (vub300->datasize < vub300->fbs[fn]) {
+ vub300->cmnd.head.block_count[0] = 0;
+ vub300->cmnd.head.block_count[1] = 0;
+ }
+ } else {
+ vub300->cmnd.head.block_count[0] = (data->blocks >> 8) & 0xFF;
+ vub300->cmnd.head.block_count[1] = (data->blocks >> 0) & 0xFF;
+ vub300->cmnd.head.block_size[0] = (data->blksz >> 8) & 0xFF;
+ vub300->cmnd.head.block_size[1] = (data->blksz >> 0) & 0xFF;
+ vub300->cmnd.head.command_type =
+ (MMC_DATA_READ & data->flags) ? 0x00 : 0x80;
+ vub300->cmnd.head.transfer_size[0] =
+ (vub300->datasize >> 24) & 0xFF;
+ vub300->cmnd.head.transfer_size[1] =
+ (vub300->datasize >> 16) & 0xFF;
+ vub300->cmnd.head.transfer_size[2] =
+ (vub300->datasize >> 8) & 0xFF;
+ vub300->cmnd.head.transfer_size[3] =
+ (vub300->datasize >> 0) & 0xFF;
+ if (vub300->datasize < vub300->fbs[0]) {
+ vub300->cmnd.head.block_count[0] = 0;
+ vub300->cmnd.head.block_count[1] = 0;
+ }
+ }
+ if (vub300->cmnd.head.block_size[0] || vub300->cmnd.head.block_size[1]) {
+ u16 block_size = vub300->cmnd.head.block_size[1] |
+ (vub300->cmnd.head.block_size[0] << 8);
+ u16 block_boundary = FIRMWARE_BLOCK_BOUNDARY -
+ (FIRMWARE_BLOCK_BOUNDARY % block_size);
+ vub300->cmnd.head.block_boundary[0] =
+ (block_boundary >> 8) & 0xFF;
+ vub300->cmnd.head.block_boundary[1] =
+ (block_boundary >> 0) & 0xFF;
+ } else {
+ vub300->cmnd.head.block_boundary[0] = 0;
+ vub300->cmnd.head.block_boundary[1] = 0;
+ }
+ usb_fill_bulk_urb(vub300->command_out_urb, vub300->udev,
+ usb_sndbulkpipe(vub300->udev, vub300->cmnd_out_ep),
+ &vub300->cmnd, sizeof(vub300->cmnd),
+ command_out_completed, vub300);
+ retval = usb_submit_urb(vub300->command_out_urb, GFP_KERNEL);
+ if (retval < 0) {
+ cmd->error = retval;
+ complete(&vub300->command_complete);
+ return;
+ } else {
+ return;
+ }
+}
+
+/*
+ * timer callback runs in atomic mode
+ * so it cannot call usb_kill_urb()
+ */
+static void vub300_sg_timed_out(unsigned long data)
+{
+ struct vub300_mmc_host *vub300 = (struct vub300_mmc_host *)data;
+ vub300->usb_timed_out = 1;
+ usb_sg_cancel(&vub300->sg_request);
+ usb_unlink_urb(vub300->command_out_urb);
+ usb_unlink_urb(vub300->command_res_urb);
+}
+
+static u16 roundup_to_multiple_of_64(u16 number)
+{
+ return 0xFFC0 & (0x3F + number);
+}
+
+/*
+ * this is a separate function to solve the 80 column width restriction
+ */
+static void __download_offload_pseudocode(struct vub300_mmc_host *vub300,
+ const struct firmware *fw)
+{
+ u8 register_count = 0;
+ u16 ts = 0;
+ u16 interrupt_size = 0;
+ const u8 *data = fw->data;
+ int size = fw->size;
+ u8 c;
+ dev_info(&vub300->udev->dev, "using %s for SDIO offload processing\n",
+ vub300->vub_name);
+ do {
+ c = *data++;
+ } while (size-- && c); /* skip comment */
+ dev_info(&vub300->udev->dev, "using offload firmware %s %s\n", fw->data,
+ vub300->vub_name);
+ if (size < 4) {
+ dev_err(&vub300->udev->dev,
+ "corrupt offload pseudocode in firmware %s\n",
+ vub300->vub_name);
+ strncpy(vub300->vub_name, "corrupt offload pseudocode",
+ sizeof(vub300->vub_name));
+ return;
+ }
+ interrupt_size += *data++;
+ size -= 1;
+ interrupt_size <<= 8;
+ interrupt_size += *data++;
+ size -= 1;
+ if (interrupt_size < size) {
+ u16 xfer_length = roundup_to_multiple_of_64(interrupt_size);
+ u8 *xfer_buffer = kmalloc(xfer_length, GFP_KERNEL);
+ if (xfer_buffer) {
+ int retval;
+ memcpy(xfer_buffer, data, interrupt_size);
+ memset(xfer_buffer + interrupt_size, 0,
+ xfer_length - interrupt_size);
+ size -= interrupt_size;
+ data += interrupt_size;
+ retval =
+ usb_control_msg(vub300->udev,
+ usb_sndctrlpipe(vub300->udev, 0),
+ SET_INTERRUPT_PSEUDOCODE,
+ USB_DIR_OUT | USB_TYPE_VENDOR |
+ USB_RECIP_DEVICE, 0x0000, 0x0000,
+ xfer_buffer, xfer_length, HZ);
+ kfree(xfer_buffer);
+ if (retval < 0) {
+ strncpy(vub300->vub_name,
+ "SDIO pseudocode download failed",
+ sizeof(vub300->vub_name));
+ return;
+ }
+ } else {
+ dev_err(&vub300->udev->dev,
+ "not enough memory for xfer buffer to send"
+ " INTERRUPT_PSEUDOCODE for %s %s\n", fw->data,
+ vub300->vub_name);
+ strncpy(vub300->vub_name,
+ "SDIO interrupt pseudocode download failed",
+ sizeof(vub300->vub_name));
+ return;
+ }
+ } else {
+ dev_err(&vub300->udev->dev,
+ "corrupt interrupt pseudocode in firmware %s %s\n",
+ fw->data, vub300->vub_name);
+ strncpy(vub300->vub_name, "corrupt interrupt pseudocode",
+ sizeof(vub300->vub_name));
+ return;
+ }
+ ts += *data++;
+ size -= 1;
+ ts <<= 8;
+ ts += *data++;
+ size -= 1;
+ if (ts < size) {
+ u16 xfer_length = roundup_to_multiple_of_64(ts);
+ u8 *xfer_buffer = kmalloc(xfer_length, GFP_KERNEL);
+ if (xfer_buffer) {
+ int retval;
+ memcpy(xfer_buffer, data, ts);
+ memset(xfer_buffer + ts, 0,
+ xfer_length - ts);
+ size -= ts;
+ data += ts;
+ retval =
+ usb_control_msg(vub300->udev,
+ usb_sndctrlpipe(vub300->udev, 0),
+ SET_TRANSFER_PSEUDOCODE,
+ USB_DIR_OUT | USB_TYPE_VENDOR |
+ USB_RECIP_DEVICE, 0x0000, 0x0000,
+ xfer_buffer, xfer_length, HZ);
+ kfree(xfer_buffer);
+ if (retval < 0) {
+ strncpy(vub300->vub_name,
+ "SDIO pseudocode download failed",
+ sizeof(vub300->vub_name));
+ return;
+ }
+ } else {
+ dev_err(&vub300->udev->dev,
+ "not enough memory for xfer buffer to send"
+ " TRANSFER_PSEUDOCODE for %s %s\n", fw->data,
+ vub300->vub_name);
+ strncpy(vub300->vub_name,
+ "SDIO transfer pseudocode download failed",
+ sizeof(vub300->vub_name));
+ return;
+ }
+ } else {
+ dev_err(&vub300->udev->dev,
+ "corrupt transfer pseudocode in firmware %s %s\n",
+ fw->data, vub300->vub_name);
+ strncpy(vub300->vub_name, "corrupt transfer pseudocode",
+ sizeof(vub300->vub_name));
+ return;
+ }
+ register_count += *data++;
+ size -= 1;
+ if (register_count * 4 == size) {
+ int I = vub300->dynamic_register_count = register_count;
+ int i = 0;
+ while (I--) {
+ unsigned int func_num = 0;
+ vub300->sdio_register[i].func_num = *data++;
+ size -= 1;
+ func_num += *data++;
+ size -= 1;
+ func_num <<= 8;
+ func_num += *data++;
+ size -= 1;
+ func_num <<= 8;
+ func_num += *data++;
+ size -= 1;
+ vub300->sdio_register[i].sdio_reg = func_num;
+ vub300->sdio_register[i].activate = 1;
+ vub300->sdio_register[i].prepared = 0;
+ i += 1;
+ }
+ dev_info(&vub300->udev->dev,
+ "initialized %d dynamic pseudocode registers\n",
+ vub300->dynamic_register_count);
+ return;
+ } else {
+ dev_err(&vub300->udev->dev,
+ "corrupt dynamic registers in firmware %s\n",
+ vub300->vub_name);
+ strncpy(vub300->vub_name, "corrupt dynamic registers",
+ sizeof(vub300->vub_name));
+ return;
+ }
+}
+
+/*
+ * if the binary containing the EMPTY PseudoCode can not be found
+ * vub300->vub_name is set anyway in order to prevent an automatic retry
+ */
+static void download_offload_pseudocode(struct vub300_mmc_host *vub300)
+{
+ struct mmc_card *card = vub300->mmc->card;
+ int sdio_funcs = card->sdio_funcs;
+ const struct firmware *fw = NULL;
+ int l = snprintf(vub300->vub_name, sizeof(vub300->vub_name),
+ "vub_%04X%04X", card->cis.vendor, card->cis.device);
+ int n = 0;
+ int retval;
+ for (n = 0; n < sdio_funcs; n++) {
+ struct sdio_func *sf = card->sdio_func[n];
+ l += snprintf(vub300->vub_name + l,
+ sizeof(vub300->vub_name) - l, "_%04X%04X",
+ sf->vendor, sf->device);
+ };
+ snprintf(vub300->vub_name + l, sizeof(vub300->vub_name) - l, ".bin");
+ dev_info(&vub300->udev->dev, "requesting offload firmware %s\n",
+ vub300->vub_name);
+ retval = request_firmware(&fw, vub300->vub_name, &card->dev);
+ if (retval < 0) {
+ strncpy(vub300->vub_name, "vub_default.bin",
+ sizeof(vub300->vub_name));
+ retval = request_firmware(&fw, vub300->vub_name, &card->dev);
+ if (retval < 0) {
+ strncpy(vub300->vub_name,
+ "no SDIO offload firmware found",
+ sizeof(vub300->vub_name));
+ } else {
+ __download_offload_pseudocode(vub300, fw);
+ release_firmware(fw);
+ }
+ } else {
+ __download_offload_pseudocode(vub300, fw);
+ release_firmware(fw);
+ }
+}
+
+static void vub300_usb_bulk_msg_completion(struct urb *urb)
+{ /* urb completion handler - hardirq */
+ complete((struct completion *)urb->context);
+}
+
+static int vub300_usb_bulk_msg(struct vub300_mmc_host *vub300,
+ unsigned int pipe, void *data, int len,
+ int *actual_length, int timeout_msecs)
+{
+ /* cmd_mutex is held by vub300_cmndwork_thread */
+ struct usb_device *usb_dev = vub300->udev;
+ struct completion done;
+ int retval;
+ vub300->urb = usb_alloc_urb(0, GFP_KERNEL);
+ if (!vub300->urb)
+ return -ENOMEM;
+ usb_fill_bulk_urb(vub300->urb, usb_dev, pipe, data, len,
+ vub300_usb_bulk_msg_completion, NULL);
+ init_completion(&done);
+ vub300->urb->context = &done;
+ vub300->urb->actual_length = 0;
+ retval = usb_submit_urb(vub300->urb, GFP_KERNEL);
+ if (unlikely(retval))
+ goto out;
+ if (!wait_for_completion_timeout
+ (&done, msecs_to_jiffies(timeout_msecs))) {
+ retval = -ETIMEDOUT;
+ usb_kill_urb(vub300->urb);
+ } else {
+ retval = vub300->urb->status;
+ }
+out:
+ *actual_length = vub300->urb->actual_length;
+ usb_free_urb(vub300->urb);
+ vub300->urb = NULL;
+ return retval;
+}
+
+static int __command_read_data(struct vub300_mmc_host *vub300,
+ struct mmc_command *cmd, struct mmc_data *data)
+{
+ /* cmd_mutex is held by vub300_cmndwork_thread */
+ int linear_length = vub300->datasize;
+ int padded_length = vub300->large_usb_packets ?
+ ((511 + linear_length) >> 9) << 9 :
+ ((63 + linear_length) >> 6) << 6;
+ if ((padded_length == linear_length) || !pad_input_to_usb_pkt) {
+ int result;
+ unsigned pipe;
+ pipe = usb_rcvbulkpipe(vub300->udev, vub300->data_inp_ep);
+ result = usb_sg_init(&vub300->sg_request, vub300->udev,
+ pipe, 0, data->sg,
+ data->sg_len, 0, GFP_KERNEL);
+ if (result < 0) {
+ usb_unlink_urb(vub300->command_out_urb);
+ usb_unlink_urb(vub300->command_res_urb);
+ cmd->error = result;
+ data->bytes_xfered = 0;
+ return 0;
+ } else {
+ vub300->sg_transfer_timer.expires =
+ jiffies + msecs_to_jiffies(2000 +
+ (linear_length / 16384));
+ add_timer(&vub300->sg_transfer_timer);
+ usb_sg_wait(&vub300->sg_request);
+ del_timer(&vub300->sg_transfer_timer);
+ if (vub300->sg_request.status < 0) {
+ cmd->error = vub300->sg_request.status;
+ data->bytes_xfered = 0;
+ return 0;
+ } else {
+ data->bytes_xfered = vub300->datasize;
+ return linear_length;
+ }
+ }
+ } else {
+ u8 *buf = kmalloc(padded_length, GFP_KERNEL);
+ if (buf) {
+ int result;
+ unsigned pipe = usb_rcvbulkpipe(vub300->udev,
+ vub300->data_inp_ep);
+ int actual_length = 0;
+ result = vub300_usb_bulk_msg(vub300, pipe, buf,
+ padded_length, &actual_length,
+ 2000 + (padded_length / 16384));
+ if (result < 0) {
+ cmd->error = result;
+ data->bytes_xfered = 0;
+ kfree(buf);
+ return 0;
+ } else if (actual_length < linear_length) {
+ cmd->error = -EREMOTEIO;
+ data->bytes_xfered = 0;
+ kfree(buf);
+ return 0;
+ } else {
+ sg_copy_from_buffer(data->sg, data->sg_len, buf,
+ linear_length);
+ kfree(buf);
+ data->bytes_xfered = vub300->datasize;
+ return linear_length;
+ }
+ } else {
+ cmd->error = -ENOMEM;
+ data->bytes_xfered = 0;
+ return 0;
+ }
+ }
+}
+
+static int __command_write_data(struct vub300_mmc_host *vub300,
+ struct mmc_command *cmd, struct mmc_data *data)
+{
+ /* cmd_mutex is held by vub300_cmndwork_thread */
+ unsigned pipe = usb_sndbulkpipe(vub300->udev, vub300->data_out_ep);
+ int linear_length = vub300->datasize;
+ int modulo_64_length = linear_length & 0x003F;
+ int modulo_512_length = linear_length & 0x01FF;
+ if (linear_length < 64) {
+ int result;
+ int actual_length;
+ sg_copy_to_buffer(data->sg, data->sg_len,
+ vub300->padded_buffer,
+ sizeof(vub300->padded_buffer));
+ memset(vub300->padded_buffer + linear_length, 0,
+ sizeof(vub300->padded_buffer) - linear_length);
+ result = vub300_usb_bulk_msg(vub300, pipe, vub300->padded_buffer,
+ sizeof(vub300->padded_buffer),
+ &actual_length, 2000 +
+ (sizeof(vub300->padded_buffer) /
+ 16384));
+ if (result < 0) {
+ cmd->error = result;
+ data->bytes_xfered = 0;
+ } else {
+ data->bytes_xfered = vub300->datasize;
+ }
+ } else if ((!vub300->large_usb_packets && (0 < modulo_64_length)) ||
+ (vub300->large_usb_packets && (64 > modulo_512_length))
+ ) { /* don't you just love these work-rounds */
+ int padded_length = ((63 + linear_length) >> 6) << 6;
+ u8 *buf = kmalloc(padded_length, GFP_KERNEL);
+ if (buf) {
+ int result;
+ int actual_length;
+ sg_copy_to_buffer(data->sg, data->sg_len, buf,
+ padded_length);
+ memset(buf + linear_length, 0,
+ padded_length - linear_length);
+ result =
+ vub300_usb_bulk_msg(vub300, pipe, buf,
+ padded_length, &actual_length,
+ 2000 + padded_length / 16384);
+ kfree(buf);
+ if (result < 0) {
+ cmd->error = result;
+ data->bytes_xfered = 0;
+ } else {
+ data->bytes_xfered = vub300->datasize;
+ }
+ } else {
+ cmd->error = -ENOMEM;
+ data->bytes_xfered = 0;
+ }
+ } else { /* no data padding required */
+ int result;
+ unsigned char buf[64 * 4];
+ sg_copy_to_buffer(data->sg, data->sg_len, buf, sizeof(buf));
+ result = usb_sg_init(&vub300->sg_request, vub300->udev,
+ pipe, 0, data->sg,
+ data->sg_len, 0, GFP_KERNEL);
+ if (result < 0) {
+ usb_unlink_urb(vub300->command_out_urb);
+ usb_unlink_urb(vub300->command_res_urb);
+ cmd->error = result;
+ data->bytes_xfered = 0;
+ } else {
+ vub300->sg_transfer_timer.expires =
+ jiffies + msecs_to_jiffies(2000 +
+ linear_length / 16384);
+ add_timer(&vub300->sg_transfer_timer);
+ usb_sg_wait(&vub300->sg_request);
+ if (cmd->error) {
+ data->bytes_xfered = 0;
+ } else {
+ del_timer(&vub300->sg_transfer_timer);
+ if (vub300->sg_request.status < 0) {
+ cmd->error = vub300->sg_request.status;
+ data->bytes_xfered = 0;
+ } else {
+ data->bytes_xfered = vub300->datasize;
+ }
+ }
+ }
+ }
+ return linear_length;
+}
+
+static void __vub300_command_response(struct vub300_mmc_host *vub300,
+ struct mmc_command *cmd,
+ struct mmc_data *data, int data_length)
+{
+ /* cmd_mutex is held by vub300_cmndwork_thread */
+ long respretval;
+ int msec_timeout = 1000 + data_length / 4;
+ respretval =
+ wait_for_completion_timeout(&vub300->command_complete,
+ msecs_to_jiffies(msec_timeout));
+ if (respretval == 0) { /* TIMED OUT */
+ /* we don't know which of "out" and "res" if any failed */
+ int result;
+ vub300->usb_timed_out = 1;
+ usb_kill_urb(vub300->command_out_urb);
+ usb_kill_urb(vub300->command_res_urb);
+ cmd->error = -ETIMEDOUT;
+ result = usb_lock_device_for_reset(vub300->udev,
+ vub300->interface);
+ if (result == 0) {
+ result = usb_reset_device(vub300->udev);
+ usb_unlock_device(vub300->udev);
+ }
+ } else if (respretval < 0) {
+ /* we don't know which of "out" and "res" if any failed */
+ usb_kill_urb(vub300->command_out_urb);
+ usb_kill_urb(vub300->command_res_urb);
+ cmd->error = respretval;
+ } else if (cmd->error) {
+ /*
+ * the error occured sending the command
+ * or recieving the response
+ */
+ } else if (vub300->command_out_urb->status) {
+ vub300->usb_transport_fail = vub300->command_out_urb->status;
+ cmd->error = -EPROTO == vub300->command_out_urb->status ?
+ -ESHUTDOWN : vub300->command_out_urb->status;
+ } else if (vub300->command_res_urb->status) {
+ vub300->usb_transport_fail = vub300->command_res_urb->status;
+ cmd->error = -EPROTO == vub300->command_res_urb->status ?
+ -ESHUTDOWN : vub300->command_res_urb->status;
+ } else if (vub300->resp.common.header_type == 0x00) {
+ /*
+ * the command completed successfully
+ * and there was no piggybacked data
+ */
+ } else if (vub300->resp.common.header_type == RESPONSE_ERROR) {
+ cmd->error =
+ vub300_response_error(vub300->resp.error.error_code);
+ if (vub300->data)
+ usb_sg_cancel(&vub300->sg_request);
+ } else if (vub300->resp.common.header_type == RESPONSE_PIGGYBACKED) {
+ int offloaded_data_length =
+ vub300->resp.common.header_size -
+ sizeof(struct sd_register_header);
+ int register_count = offloaded_data_length >> 3;
+ int ri = 0;
+ while (register_count--) {
+ add_offloaded_reg(vub300, &vub300->resp.pig.reg[ri]);
+ ri += 1;
+ }
+ vub300->resp.common.header_size =
+ sizeof(struct sd_register_header);
+ vub300->resp.common.header_type = 0x00;
+ cmd->error = 0;
+ } else if (vub300->resp.common.header_type == RESPONSE_PIG_DISABLED) {
+ int offloaded_data_length =
+ vub300->resp.common.header_size -
+ sizeof(struct sd_register_header);
+ int register_count = offloaded_data_length >> 3;
+ int ri = 0;
+ while (register_count--) {
+ add_offloaded_reg(vub300, &vub300->resp.pig.reg[ri]);
+ ri += 1;
+ }
+ mutex_lock(&vub300->irq_mutex);
+ if (vub300->irqs_queued) {
+ vub300->irqs_queued += 1;
+ } else if (vub300->irq_enabled) {
+ vub300->irqs_queued += 1;
+ vub300_queue_poll_work(vub300, 0);
+ } else {
+ vub300->irqs_queued += 1;
+ }
+ vub300->irq_disabled = 1;
+ mutex_unlock(&vub300->irq_mutex);
+ vub300->resp.common.header_size =
+ sizeof(struct sd_register_header);
+ vub300->resp.common.header_type = 0x00;
+ cmd->error = 0;
+ } else if (vub300->resp.common.header_type == RESPONSE_PIG_ENABLED) {
+ int offloaded_data_length =
+ vub300->resp.common.header_size -
+ sizeof(struct sd_register_header);
+ int register_count = offloaded_data_length >> 3;
+ int ri = 0;
+ while (register_count--) {
+ add_offloaded_reg(vub300, &vub300->resp.pig.reg[ri]);
+ ri += 1;
+ }
+ mutex_lock(&vub300->irq_mutex);
+ if (vub300->irqs_queued) {
+ vub300->irqs_queued += 1;
+ } else if (vub300->irq_enabled) {
+ vub300->irqs_queued += 1;
+ vub300_queue_poll_work(vub300, 0);
+ } else {
+ vub300->irqs_queued += 1;
+ }
+ vub300->irq_disabled = 0;
+ mutex_unlock(&vub300->irq_mutex);
+ vub300->resp.common.header_size =
+ sizeof(struct sd_register_header);
+ vub300->resp.common.header_type = 0x00;
+ cmd->error = 0;
+ } else {
+ cmd->error = -EINVAL;
+ }
+}
+
+static void construct_request_response(struct vub300_mmc_host *vub300,
+ struct mmc_command *cmd)
+{
+ int resp_len = vub300->resp_len;
+ int less_cmd = (17 == resp_len) ? resp_len : resp_len - 1;
+ int bytes = 3 & less_cmd;
+ int words = less_cmd >> 2;
+ u8 *r = vub300->resp.response.command_response;
+ if (bytes == 3) {
+ cmd->resp[words] = (r[1 + (words << 2)] << 24)
+ | (r[2 + (words << 2)] << 16)
+ | (r[3 + (words << 2)] << 8);
+ } else if (bytes == 2) {
+ cmd->resp[words] = (r[1 + (words << 2)] << 24)
+ | (r[2 + (words << 2)] << 16);
+ } else if (bytes == 1) {
+ cmd->resp[words] = (r[1 + (words << 2)] << 24);
+ }
+ while (words-- > 0) {
+ cmd->resp[words] = (r[1 + (words << 2)] << 24)
+ | (r[2 + (words << 2)] << 16)
+ | (r[3 + (words << 2)] << 8)
+ | (r[4 + (words << 2)] << 0);
+ }
+ if ((cmd->opcode == 53) && (0x000000FF & cmd->resp[0]))
+ cmd->resp[0] &= 0xFFFFFF00;
+}
+
+/* this thread runs only when there is an upper level command req outstanding */
+static void vub300_cmndwork_thread(struct work_struct *work)
+{
+ struct vub300_mmc_host *vub300 =
+ container_of(work, struct vub300_mmc_host, cmndwork);
+ if (!vub300->interface) {
+ kref_put(&vub300->kref, vub300_delete);
+ return;
+ } else {
+ struct mmc_request *req = vub300->req;
+ struct mmc_command *cmd = vub300->cmd;
+ struct mmc_data *data = vub300->data;
+ int data_length;
+ mutex_lock(&vub300->cmd_mutex);
+ init_completion(&vub300->command_complete);
+ if (likely(vub300->vub_name[0]) || !vub300->mmc->card ||
+ !mmc_card_present(vub300->mmc->card)) {
+ /*
+ * the name of the EMPTY Pseudo firmware file
+ * is used as a flag to indicate that the file
+ * has been already downloaded to the VUB300 chip
+ */
+ } else if (0 == vub300->mmc->card->sdio_funcs) {
+ strncpy(vub300->vub_name, "SD memory device",
+ sizeof(vub300->vub_name));
+ } else {
+ download_offload_pseudocode(vub300);
+ }
+ send_command(vub300);
+ if (!data)
+ data_length = 0;
+ else if (MMC_DATA_READ & data->flags)
+ data_length = __command_read_data(vub300, cmd, data);
+ else
+ data_length = __command_write_data(vub300, cmd, data);
+ __vub300_command_response(vub300, cmd, data, data_length);
+ vub300->req = NULL;
+ vub300->cmd = NULL;
+ vub300->data = NULL;
+ if (cmd->error) {
+ if (cmd->error == -ENOMEDIUM)
+ check_vub300_port_status(vub300);
+ mutex_unlock(&vub300->cmd_mutex);
+ mmc_request_done(vub300->mmc, req);
+ kref_put(&vub300->kref, vub300_delete);
+ return;
+ } else {
+ construct_request_response(vub300, cmd);
+ vub300->resp_len = 0;
+ mutex_unlock(&vub300->cmd_mutex);
+ kref_put(&vub300->kref, vub300_delete);
+ mmc_request_done(vub300->mmc, req);
+ return;
+ }
+ }
+}
+
+static int examine_cyclic_buffer(struct vub300_mmc_host *vub300,
+ struct mmc_command *cmd, u8 Function)
+{
+ /* cmd_mutex is held by vub300_mmc_request */
+ u8 cmd0 = 0xFF & (cmd->arg >> 24);
+ u8 cmd1 = 0xFF & (cmd->arg >> 16);
+ u8 cmd2 = 0xFF & (cmd->arg >> 8);
+ u8 cmd3 = 0xFF & (cmd->arg >> 0);
+ int first = MAXREGMASK & vub300->fn[Function].offload_point;
+ struct offload_registers_access *rf = &vub300->fn[Function].reg[first];
+ if (cmd0 == rf->command_byte[0] &&
+ cmd1 == rf->command_byte[1] &&
+ cmd2 == rf->command_byte[2] &&
+ cmd3 == rf->command_byte[3]) {
+ u8 checksum = 0x00;
+ cmd->resp[1] = checksum << 24;
+ cmd->resp[0] = (rf->Respond_Byte[0] << 24)
+ | (rf->Respond_Byte[1] << 16)
+ | (rf->Respond_Byte[2] << 8)
+ | (rf->Respond_Byte[3] << 0);
+ vub300->fn[Function].offload_point += 1;
+ vub300->fn[Function].offload_count -= 1;
+ vub300->total_offload_count -= 1;
+ return 1;
+ } else {
+ int delta = 1; /* because it does not match the first one */
+ u8 register_count = vub300->fn[Function].offload_count - 1;
+ u32 register_point = vub300->fn[Function].offload_point + 1;
+ while (0 < register_count) {
+ int point = MAXREGMASK & register_point;
+ struct offload_registers_access *r =
+ &vub300->fn[Function].reg[point];
+ if (cmd0 == r->command_byte[0] &&
+ cmd1 == r->command_byte[1] &&
+ cmd2 == r->command_byte[2] &&
+ cmd3 == r->command_byte[3]) {
+ u8 checksum = 0x00;
+ cmd->resp[1] = checksum << 24;
+ cmd->resp[0] = (r->Respond_Byte[0] << 24)
+ | (r->Respond_Byte[1] << 16)
+ | (r->Respond_Byte[2] << 8)
+ | (r->Respond_Byte[3] << 0);
+ vub300->fn[Function].offload_point += delta;
+ vub300->fn[Function].offload_count -= delta;
+ vub300->total_offload_count -= delta;
+ return 1;
+ } else {
+ register_point += 1;
+ register_count -= 1;
+ delta += 1;
+ continue;
+ }
+ }
+ return 0;
+ }
+}
+
+static int satisfy_request_from_offloaded_data(struct vub300_mmc_host *vub300,
+ struct mmc_command *cmd)
+{
+ /* cmd_mutex is held by vub300_mmc_request */
+ u8 regs = vub300->dynamic_register_count;
+ u8 i = 0;
+ u8 func = FUN(cmd);
+ u32 reg = REG(cmd);
+ while (0 < regs--) {
+ if ((vub300->sdio_register[i].func_num == func) &&
+ (vub300->sdio_register[i].sdio_reg == reg)) {
+ if (!vub300->sdio_register[i].prepared) {
+ return 0;
+ } else if ((0x80000000 & cmd->arg) == 0x80000000) {
+ /*
+ * a write to a dynamic register
+ * nullifies our offloaded value
+ */
+ vub300->sdio_register[i].prepared = 0;
+ return 0;
+ } else {
+ u8 checksum = 0x00;
+ u8 rsp0 = 0x00;
+ u8 rsp1 = 0x00;
+ u8 rsp2 = vub300->sdio_register[i].response;
+ u8 rsp3 = vub300->sdio_register[i].regvalue;
+ vub300->sdio_register[i].prepared = 0;
+ cmd->resp[1] = checksum << 24;
+ cmd->resp[0] = (rsp0 << 24)
+ | (rsp1 << 16)
+ | (rsp2 << 8)
+ | (rsp3 << 0);
+ return 1;
+ }
+ } else {
+ i += 1;
+ continue;
+ }
+ };
+ if (vub300->total_offload_count == 0)
+ return 0;
+ else if (vub300->fn[func].offload_count == 0)
+ return 0;
+ else
+ return examine_cyclic_buffer(vub300, cmd, func);
+}
+
+static void vub300_mmc_request(struct mmc_host *mmc, struct mmc_request *req)
+{ /* NOT irq */
+ struct mmc_command *cmd = req->cmd;
+ struct vub300_mmc_host *vub300 = mmc_priv(mmc);
+ if (!vub300->interface) {
+ cmd->error = -ESHUTDOWN;
+ mmc_request_done(mmc, req);
+ return;
+ } else {
+ struct mmc_data *data = req->data;
+ if (!vub300->card_powered) {
+ cmd->error = -ENOMEDIUM;
+ mmc_request_done(mmc, req);
+ return;
+ }
+ if (!vub300->card_present) {
+ cmd->error = -ENOMEDIUM;
+ mmc_request_done(mmc, req);
+ return;
+ }
+ if (vub300->usb_transport_fail) {
+ cmd->error = vub300->usb_transport_fail;
+ mmc_request_done(mmc, req);
+ return;
+ }
+ if (!vub300->interface) {
+ cmd->error = -ENODEV;
+ mmc_request_done(mmc, req);
+ return;
+ }
+ kref_get(&vub300->kref);
+ mutex_lock(&vub300->cmd_mutex);
+ mod_timer(&vub300->inactivity_timer, jiffies + HZ);
+ /*
+ * for performance we have to return immediately
+ * if the requested data has been offloaded
+ */
+ if (cmd->opcode == 52 &&
+ satisfy_request_from_offloaded_data(vub300, cmd)) {
+ cmd->error = 0;
+ mutex_unlock(&vub300->cmd_mutex);
+ kref_put(&vub300->kref, vub300_delete);
+ mmc_request_done(mmc, req);
+ return;
+ } else {
+ vub300->cmd = cmd;
+ vub300->req = req;
+ vub300->data = data;
+ if (data)
+ vub300->datasize = data->blksz * data->blocks;
+ else
+ vub300->datasize = 0;
+ vub300_queue_cmnd_work(vub300);
+ mutex_unlock(&vub300->cmd_mutex);
+ kref_put(&vub300->kref, vub300_delete);
+ /*
+ * the kernel lock diagnostics complain
+ * if the cmd_mutex * is "passed on"
+ * to the cmndwork thread,
+ * so we must release it now
+ * and re-acquire it in the cmndwork thread
+ */
+ }
+ }
+}
+
+static void __set_clock_speed(struct vub300_mmc_host *vub300, u8 buf[8],
+ struct mmc_ios *ios)
+{
+ int buf_array_size = 8; /* ARRAY_SIZE(buf) does not work !!! */
+ int retval;
+ u32 kHzClock;
+ if (ios->clock >= 48000000)
+ kHzClock = 48000;
+ else if (ios->clock >= 24000000)
+ kHzClock = 24000;
+ else if (ios->clock >= 20000000)
+ kHzClock = 20000;
+ else if (ios->clock >= 15000000)
+ kHzClock = 15000;
+ else if (ios->clock >= 200000)
+ kHzClock = 200;
+ else
+ kHzClock = 0;
+ {
+ int i;
+ u64 c = kHzClock;
+ for (i = 0; i < buf_array_size; i++) {
+ buf[i] = c;
+ c >>= 8;
+ }
+ }
+ retval =
+ usb_control_msg(vub300->udev, usb_sndctrlpipe(vub300->udev, 0),
+ SET_CLOCK_SPEED,
+ USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
+ 0x00, 0x00, buf, buf_array_size, HZ);
+ if (retval != 8) {
+ dev_err(&vub300->udev->dev, "SET_CLOCK_SPEED"
+ " %dkHz failed with retval=%d\n", kHzClock, retval);
+ } else {
+ dev_dbg(&vub300->udev->dev, "SET_CLOCK_SPEED"
+ " %dkHz\n", kHzClock);
+ }
+}
+
+static void vub300_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
+{ /* NOT irq */
+ struct vub300_mmc_host *vub300 = mmc_priv(mmc);
+ if (!vub300->interface)
+ return;
+ kref_get(&vub300->kref);
+ mutex_lock(&vub300->cmd_mutex);
+ if ((ios->power_mode == MMC_POWER_OFF) && vub300->card_powered) {
+ vub300->card_powered = 0;
+ usb_control_msg(vub300->udev, usb_sndctrlpipe(vub300->udev, 0),
+ SET_SD_POWER,
+ USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
+ 0x0000, 0x0000, NULL, 0, HZ);
+ /* must wait for the VUB300 u-proc to boot up */
+ msleep(600);
+ } else if ((ios->power_mode == MMC_POWER_UP) && !vub300->card_powered) {
+ usb_control_msg(vub300->udev, usb_sndctrlpipe(vub300->udev, 0),
+ SET_SD_POWER,
+ USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
+ 0x0001, 0x0000, NULL, 0, HZ);
+ msleep(600);
+ vub300->card_powered = 1;
+ } else if (ios->power_mode == MMC_POWER_ON) {
+ u8 *buf = kmalloc(8, GFP_KERNEL);
+ if (buf) {
+ __set_clock_speed(vub300, buf, ios);
+ kfree(buf);
+ }
+ } else {
+ /* this should mean no change of state */
+ }
+ mutex_unlock(&vub300->cmd_mutex);
+ kref_put(&vub300->kref, vub300_delete);
+}
+
+static int vub300_mmc_get_ro(struct mmc_host *mmc)
+{
+ struct vub300_mmc_host *vub300 = mmc_priv(mmc);
+ return vub300->read_only;
+}
+
+static void vub300_enable_sdio_irq(struct mmc_host *mmc, int enable)
+{ /* NOT irq */
+ struct vub300_mmc_host *vub300 = mmc_priv(mmc);
+ if (!vub300->interface)
+ return;
+ kref_get(&vub300->kref);
+ if (enable) {
+ mutex_lock(&vub300->irq_mutex);
+ if (vub300->irqs_queued) {
+ vub300->irqs_queued -= 1;
+ mmc_signal_sdio_irq(vub300->mmc);
+ } else if (vub300->irq_disabled) {
+ vub300->irq_disabled = 0;
+ vub300->irq_enabled = 1;
+ vub300_queue_poll_work(vub300, 0);
+ } else if (vub300->irq_enabled) {
+ /* this should not happen, so we will just ignore it */
+ } else {
+ vub300->irq_enabled = 1;
+ vub300_queue_poll_work(vub300, 0);
+ }
+ mutex_unlock(&vub300->irq_mutex);
+ } else {
+ vub300->irq_enabled = 0;
+ }
+ kref_put(&vub300->kref, vub300_delete);
+}
+
+void vub300_init_card(struct mmc_host *mmc, struct mmc_card *card)
+{ /* NOT irq */
+ struct vub300_mmc_host *vub300 = mmc_priv(mmc);
+ dev_info(&vub300->udev->dev, "NO host QUIRKS for this card\n");
+}
+
+static struct mmc_host_ops vub300_mmc_ops = {
+ .request = vub300_mmc_request,
+ .set_ios = vub300_mmc_set_ios,
+ .get_ro = vub300_mmc_get_ro,
+ .enable_sdio_irq = vub300_enable_sdio_irq,
+ .init_card = vub300_init_card,
+};
+
+static int vub300_probe(struct usb_interface *interface,
+ const struct usb_device_id *id)
+{ /* NOT irq */
+ struct vub300_mmc_host *vub300 = NULL;
+ struct usb_host_interface *iface_desc;
+ struct usb_device *udev = usb_get_dev(interface_to_usbdev(interface));
+ int i;
+ int retval = -ENOMEM;
+ struct urb *command_out_urb;
+ struct urb *command_res_urb;
+ struct mmc_host *mmc;
+ char manufacturer[48];
+ char product[32];
+ char serial_number[32];
+ usb_string(udev, udev->descriptor.iManufacturer, manufacturer,
+ sizeof(manufacturer));
+ usb_string(udev, udev->descriptor.iProduct, product, sizeof(product));
+ usb_string(udev, udev->descriptor.iSerialNumber, serial_number,
+ sizeof(serial_number));
+ dev_info(&udev->dev, "probing VID:PID(%04X:%04X) %s %s %s\n",
+ udev->descriptor.idVendor, udev->descriptor.idProduct,
+ manufacturer, product, serial_number);
+ command_out_urb = usb_alloc_urb(0, GFP_KERNEL);
+ if (!command_out_urb) {
+ retval = -ENOMEM;
+ dev_err(&vub300->udev->dev,
+ "not enough memory for the command_out_urb\n");
+ goto error0;
+ }
+ command_res_urb = usb_alloc_urb(0, GFP_KERNEL);
+ if (!command_res_urb) {
+ retval = -ENOMEM;
+ dev_err(&vub300->udev->dev,
+ "not enough memory for the command_res_urb\n");
+ goto error1;
+ }
+ /* this also allocates memory for our VUB300 mmc host device */
+ mmc = mmc_alloc_host(sizeof(struct vub300_mmc_host), &udev->dev);
+ if (!mmc) {
+ retval = -ENOMEM;
+ dev_err(&vub300->udev->dev,
+ "not enough memory for the mmc_host\n");
+ goto error4;
+ }
+ /* MMC core transfer sizes tunable parameters */
+ mmc->caps = 0;
+ if (!force_1_bit_data_xfers)
+ mmc->caps |= MMC_CAP_4_BIT_DATA;
+ if (!force_polling_for_irqs)
+ mmc->caps |= MMC_CAP_SDIO_IRQ;
+ mmc->caps &= ~MMC_CAP_NEEDS_POLL;
+ /*
+ * MMC_CAP_NEEDS_POLL causes core.c:mmc_rescan() to poll
+ * for devices which results in spurious CMD7's being
+ * issued which stops some SDIO cards from working
+ */
+ if (limit_speed_to_24_MHz) {
+ mmc->caps |= MMC_CAP_MMC_HIGHSPEED;
+ mmc->caps |= MMC_CAP_SD_HIGHSPEED;
+ mmc->f_max = 24000000;
+ dev_info(&udev->dev, "limiting SDIO speed to 24_MHz\n");
+ } else {
+ mmc->caps |= MMC_CAP_MMC_HIGHSPEED;
+ mmc->caps |= MMC_CAP_SD_HIGHSPEED;
+ mmc->f_max = 48000000;
+ }
+ mmc->f_min = 200000;
+ mmc->max_blk_count = 511;
+ mmc->max_blk_size = 512;
+ mmc->max_segs = 128;
+ if (force_max_req_size)
+ mmc->max_req_size = force_max_req_size * 1024;
+ else
+ mmc->max_req_size = 64 * 1024;
+ mmc->max_seg_size = mmc->max_req_size;
+ mmc->ocr_avail = 0;
+ mmc->ocr_avail |= MMC_VDD_165_195;
+ mmc->ocr_avail |= MMC_VDD_20_21;
+ mmc->ocr_avail |= MMC_VDD_21_22;
+ mmc->ocr_avail |= MMC_VDD_22_23;
+ mmc->ocr_avail |= MMC_VDD_23_24;
+ mmc->ocr_avail |= MMC_VDD_24_25;
+ mmc->ocr_avail |= MMC_VDD_25_26;
+ mmc->ocr_avail |= MMC_VDD_26_27;
+ mmc->ocr_avail |= MMC_VDD_27_28;
+ mmc->ocr_avail |= MMC_VDD_28_29;
+ mmc->ocr_avail |= MMC_VDD_29_30;
+ mmc->ocr_avail |= MMC_VDD_30_31;
+ mmc->ocr_avail |= MMC_VDD_31_32;
+ mmc->ocr_avail |= MMC_VDD_32_33;
+ mmc->ocr_avail |= MMC_VDD_33_34;
+ mmc->ocr_avail |= MMC_VDD_34_35;
+ mmc->ocr_avail |= MMC_VDD_35_36;
+ mmc->ops = &vub300_mmc_ops;
+ vub300 = mmc_priv(mmc);
+ vub300->mmc = mmc;
+ vub300->card_powered = 0;
+ vub300->bus_width = 0;
+ vub300->cmnd.head.block_size[0] = 0x00;
+ vub300->cmnd.head.block_size[1] = 0x00;
+ vub300->app_spec = 0;
+ mutex_init(&vub300->cmd_mutex);
+ mutex_init(&vub300->irq_mutex);
+ vub300->command_out_urb = command_out_urb;
+ vub300->command_res_urb = command_res_urb;
+ vub300->usb_timed_out = 0;
+ vub300->dynamic_register_count = 0;
+
+ for (i = 0; i < ARRAY_SIZE(vub300->fn); i++) {
+ vub300->fn[i].offload_point = 0;
+ vub300->fn[i].offload_count = 0;
+ }
+
+ vub300->total_offload_count = 0;
+ vub300->irq_enabled = 0;
+ vub300->irq_disabled = 0;
+ vub300->irqs_queued = 0;
+
+ for (i = 0; i < ARRAY_SIZE(vub300->sdio_register); i++)
+ vub300->sdio_register[i++].activate = 0;
+
+ vub300->udev = udev;
+ vub300->interface = interface;
+ vub300->cmnd_res_ep = 0;
+ vub300->cmnd_out_ep = 0;
+ vub300->data_inp_ep = 0;
+ vub300->data_out_ep = 0;
+
+ for (i = 0; i < ARRAY_SIZE(vub300->fbs); i++)
+ vub300->fbs[i] = 512;
+
+ /*
+ * set up the endpoint information
+ *
+ * use the first pair of bulk-in and bulk-out
+ * endpoints for Command/Response+Interrupt
+ *
+ * use the second pair of bulk-in and bulk-out
+ * endpoints for Data In/Out
+ */
+ vub300->large_usb_packets = 0;
+ iface_desc = interface->cur_altsetting;
+ for (i = 0; i < iface_desc->desc.bNumEndpoints; ++i) {
+ struct usb_endpoint_descriptor *endpoint =
+ &iface_desc->endpoint[i].desc;
+ dev_info(&vub300->udev->dev,
+ "vub300 testing %s EndPoint(%d) %02X\n",
+ usb_endpoint_is_bulk_in(endpoint) ? "BULK IN" :
+ usb_endpoint_is_bulk_out(endpoint) ? "BULK OUT" :
+ "UNKNOWN", i, endpoint->bEndpointAddress);
+ if (endpoint->wMaxPacketSize > 64)
+ vub300->large_usb_packets = 1;
+ if (usb_endpoint_is_bulk_in(endpoint)) {
+ if (!vub300->cmnd_res_ep) {
+ vub300->cmnd_res_ep =
+ endpoint->bEndpointAddress;
+ } else if (!vub300->data_inp_ep) {
+ vub300->data_inp_ep =
+ endpoint->bEndpointAddress;
+ } else {
+ dev_warn(&vub300->udev->dev,
+ "ignoring"
+ " unexpected bulk_in endpoint");
+ }
+ } else if (usb_endpoint_is_bulk_out(endpoint)) {
+ if (!vub300->cmnd_out_ep) {
+ vub300->cmnd_out_ep =
+ endpoint->bEndpointAddress;
+ } else if (!vub300->data_out_ep) {
+ vub300->data_out_ep =
+ endpoint->bEndpointAddress;
+ } else {
+ dev_warn(&vub300->udev->dev,
+ "ignoring"
+ " unexpected bulk_out endpoint");
+ }
+ } else {
+ dev_warn(&vub300->udev->dev,
+ "vub300 ignoring EndPoint(%d) %02X", i,
+ endpoint->bEndpointAddress);
+ }
+ }
+ if (vub300->cmnd_res_ep && vub300->cmnd_out_ep &&
+ vub300->data_inp_ep && vub300->data_out_ep) {
+ dev_info(&vub300->udev->dev,
+ "vub300 %s packets"
+ " using EndPoints %02X %02X %02X %02X\n",
+ vub300->large_usb_packets ? "LARGE" : "SMALL",
+ vub300->cmnd_out_ep, vub300->cmnd_res_ep,
+ vub300->data_out_ep, vub300->data_inp_ep);
+ /* we have the expected EndPoints */
+ } else {
+ dev_err(&vub300->udev->dev,
+ "Could not find two sets of bulk-in/out endpoint pairs\n");
+ retval = -EINVAL;
+ goto error5;
+ }
+ retval =
+ usb_control_msg(vub300->udev, usb_rcvctrlpipe(vub300->udev, 0),
+ GET_HC_INF0,
+ USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
+ 0x0000, 0x0000, &vub300->hc_info,
+ sizeof(vub300->hc_info), HZ);
+ if (retval < 0)
+ goto error5;
+ retval =
+ usb_control_msg(vub300->udev, usb_rcvctrlpipe(vub300->udev, 0),
+ SET_ROM_WAIT_STATES,
+ USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
+ firmware_rom_wait_states, 0x0000, NULL, 0, HZ);
+ if (retval < 0)
+ goto error5;
+ dev_info(&vub300->udev->dev,
+ "operating_mode = %s %s %d MHz %s %d byte USB packets\n",
+ (mmc->caps & MMC_CAP_SDIO_IRQ) ? "IRQs" : "POLL",
+ (mmc->caps & MMC_CAP_4_BIT_DATA) ? "4-bit" : "1-bit",
+ mmc->f_max / 1000000,
+ pad_input_to_usb_pkt ? "padding input data to" : "with",
+ vub300->large_usb_packets ? 512 : 64);
+ retval =
+ usb_control_msg(vub300->udev, usb_rcvctrlpipe(vub300->udev, 0),
+ GET_SYSTEM_PORT_STATUS,
+ USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
+ 0x0000, 0x0000, &vub300->system_port_status,
+ sizeof(vub300->system_port_status), HZ);
+ if (retval < 0) {
+ goto error4;
+ } else if (sizeof(vub300->system_port_status) == retval) {
+ vub300->card_present =
+ (0x0001 & vub300->system_port_status.port_flags) ? 1 : 0;
+ vub300->read_only =
+ (0x0010 & vub300->system_port_status.port_flags) ? 1 : 0;
+ } else {
+ goto error4;
+ }
+ usb_set_intfdata(interface, vub300);
+ INIT_DELAYED_WORK(&vub300->pollwork, vub300_pollwork_thread);
+ INIT_WORK(&vub300->cmndwork, vub300_cmndwork_thread);
+ INIT_WORK(&vub300->deadwork, vub300_deadwork_thread);
+ kref_init(&vub300->kref);
+ init_timer(&vub300->sg_transfer_timer);
+ vub300->sg_transfer_timer.data = (unsigned long)vub300;
+ vub300->sg_transfer_timer.function = vub300_sg_timed_out;
+ kref_get(&vub300->kref);
+ init_timer(&vub300->inactivity_timer);
+ vub300->inactivity_timer.data = (unsigned long)vub300;
+ vub300->inactivity_timer.function = vub300_inactivity_timer_expired;
+ vub300->inactivity_timer.expires = jiffies + HZ;
+ add_timer(&vub300->inactivity_timer);
+ if (vub300->card_present)
+ dev_info(&vub300->udev->dev,
+ "USB vub300 remote SDIO host controller[%d]"
+ "connected with SD/SDIO card inserted\n",
+ interface_to_InterfaceNumber(interface));
+ else
+ dev_info(&vub300->udev->dev,
+ "USB vub300 remote SDIO host controller[%d]"
+ "connected with no SD/SDIO card inserted\n",
+ interface_to_InterfaceNumber(interface));
+ mmc_add_host(mmc);
+ return 0;
+error5:
+ mmc_free_host(mmc);
+ /*
+ * and hence also frees vub300
+ * which is contained at the end of struct mmc
+ */
+error4:
+ usb_free_urb(command_out_urb);
+error1:
+ usb_free_urb(command_res_urb);
+error0:
+ return retval;
+}
+
+static void vub300_disconnect(struct usb_interface *interface)
+{ /* NOT irq */
+ struct vub300_mmc_host *vub300 = usb_get_intfdata(interface);
+ if (!vub300 || !vub300->mmc) {
+ return;
+ } else {
+ struct mmc_host *mmc = vub300->mmc;
+ if (!vub300->mmc) {
+ return;
+ } else {
+ int ifnum = interface_to_InterfaceNumber(interface);
+ usb_set_intfdata(interface, NULL);
+ /* prevent more I/O from starting */
+ vub300->interface = NULL;
+ kref_put(&vub300->kref, vub300_delete);
+ mmc_remove_host(mmc);
+ pr_info("USB vub300 remote SDIO host controller[%d]"
+ " now disconnected", ifnum);
+ return;
+ }
+ }
+}
+
+#ifdef CONFIG_PM
+static int vub300_suspend(struct usb_interface *intf, pm_message_t message)
+{
+ struct vub300_mmc_host *vub300 = usb_get_intfdata(intf);
+ if (!vub300 || !vub300->mmc) {
+ return 0;
+ } else {
+ struct mmc_host *mmc = vub300->mmc;
+ mmc_suspend_host(mmc);
+ return 0;
+ }
+}
+
+static int vub300_resume(struct usb_interface *intf)
+{
+ struct vub300_mmc_host *vub300 = usb_get_intfdata(intf);
+ if (!vub300 || !vub300->mmc) {
+ return 0;
+ } else {
+ struct mmc_host *mmc = vub300->mmc;
+ mmc_resume_host(mmc);
+ return 0;
+ }
+}
+#else
+#define vub300_suspend NULL
+#define vub300_resume NULL
+#endif
+static int vub300_pre_reset(struct usb_interface *intf)
+{ /* NOT irq */
+ struct vub300_mmc_host *vub300 = usb_get_intfdata(intf);
+ mutex_lock(&vub300->cmd_mutex);
+ return 0;
+}
+
+static int vub300_post_reset(struct usb_interface *intf)
+{ /* NOT irq */
+ struct vub300_mmc_host *vub300 = usb_get_intfdata(intf);
+ /* we are sure no URBs are active - no locking needed */
+ vub300->errors = -EPIPE;
+ mutex_unlock(&vub300->cmd_mutex);
+ return 0;
+}
+
+static struct usb_driver vub300_driver = {
+ .name = "vub300",
+ .probe = vub300_probe,
+ .disconnect = vub300_disconnect,
+ .suspend = vub300_suspend,
+ .resume = vub300_resume,
+ .pre_reset = vub300_pre_reset,
+ .post_reset = vub300_post_reset,
+ .id_table = vub300_table,
+ .supports_autosuspend = 1,
+};
+
+static int __init vub300_init(void)
+{ /* NOT irq */
+ int result;
+
+ pr_info("VUB300 Driver rom wait states = %02X irqpoll timeout = %04X",
+ firmware_rom_wait_states, 0x0FFFF & firmware_irqpoll_timeout);
+ cmndworkqueue = create_singlethread_workqueue("kvub300c");
+ if (!cmndworkqueue) {
+ pr_err("not enough memory for the REQUEST workqueue");
+ result = -ENOMEM;
+ goto out1;
+ }
+ pollworkqueue = create_singlethread_workqueue("kvub300p");
+ if (!pollworkqueue) {
+ pr_err("not enough memory for the IRQPOLL workqueue");
+ result = -ENOMEM;
+ goto out2;
+ }
+ deadworkqueue = create_singlethread_workqueue("kvub300d");
+ if (!deadworkqueue) {
+ pr_err("not enough memory for the EXPIRED workqueue");
+ result = -ENOMEM;
+ goto out3;
+ }
+ result = usb_register(&vub300_driver);
+ if (result) {
+ pr_err("usb_register failed. Error number %d", result);
+ goto out4;
+ }
+ return 0;
+out4:
+ destroy_workqueue(deadworkqueue);
+out3:
+ destroy_workqueue(pollworkqueue);
+out2:
+ destroy_workqueue(cmndworkqueue);
+out1:
+ return result;
+}
+
+static void __exit vub300_exit(void)
+{
+ usb_deregister(&vub300_driver);
+ flush_workqueue(cmndworkqueue);
+ flush_workqueue(pollworkqueue);
+ flush_workqueue(deadworkqueue);
+ destroy_workqueue(cmndworkqueue);
+ destroy_workqueue(pollworkqueue);
+ destroy_workqueue(deadworkqueue);
+}
+
+module_init(vub300_init);
+module_exit(vub300_exit);
+
+MODULE_AUTHOR("Tony Olech <tony.olech@elandigitalsystems.com>");
+MODULE_DESCRIPTION("VUB300 USB to SD/MMC/SDIO adapter driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig
index b4567c3..bc50d5e 100644
--- a/drivers/mtd/Kconfig
+++ b/drivers/mtd/Kconfig
@@ -148,8 +148,7 @@
You will still need the parsing functions to be called by the driver
for your particular device. It won't happen automatically. The
- 'armflash' map driver (CONFIG_MTD_ARM_INTEGRATOR) does this, for
- example.
+ 'physmap' map driver (CONFIG_MTD_PHYSMAP) does this, for example.
config MTD_OF_PARTS
def_bool y
diff --git a/drivers/mtd/maps/Makefile b/drivers/mtd/maps/Makefile
index 6adf4c9..cb48b11 100644
--- a/drivers/mtd/maps/Makefile
+++ b/drivers/mtd/maps/Makefile
@@ -8,7 +8,6 @@
# Chip mappings
obj-$(CONFIG_MTD_CDB89712) += cdb89712.o
-obj-$(CONFIG_MTD_ARM_INTEGRATOR)+= integrator-flash.o
obj-$(CONFIG_MTD_CFI_FLAGADM) += cfi_flagadm.o
obj-$(CONFIG_MTD_DC21285) += dc21285.o
obj-$(CONFIG_MTD_DILNETPC) += dilnetpc.o
diff --git a/drivers/mtd/maps/integrator-flash.c b/drivers/mtd/maps/integrator-flash.c
deleted file mode 100644
index e22ff5a..0000000
--- a/drivers/mtd/maps/integrator-flash.c
+++ /dev/null
@@ -1,309 +0,0 @@
-/*======================================================================
-
- drivers/mtd/maps/integrator-flash.c: ARM Integrator flash map driver
-
- Copyright (C) 2000 ARM Limited
- Copyright (C) 2003 Deep Blue Solutions Ltd.
-
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License as published by
- the Free Software Foundation; either version 2 of the License, or
- (at your option) any later version.
-
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
-
- You should have received a copy of the GNU General Public License
- along with this program; if not, write to the Free Software
- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-
- This is access code for flashes using ARM's flash partitioning
- standards.
-
-======================================================================*/
-
-#include <linux/module.h>
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/slab.h>
-#include <linux/ioport.h>
-#include <linux/platform_device.h>
-#include <linux/init.h>
-#include <linux/io.h>
-
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/map.h>
-#include <linux/mtd/partitions.h>
-#include <linux/mtd/concat.h>
-
-#include <asm/mach/flash.h>
-#include <mach/hardware.h>
-#include <asm/system.h>
-
-struct armflash_subdev_info {
- char *name;
- struct mtd_info *mtd;
- struct map_info map;
- struct flash_platform_data *plat;
-};
-
-struct armflash_info {
- struct resource *res;
- struct mtd_partition *parts;
- struct mtd_info *mtd;
- int nr_subdev;
- struct armflash_subdev_info subdev[0];
-};
-
-static void armflash_set_vpp(struct map_info *map, int on)
-{
- struct armflash_subdev_info *info =
- container_of(map, struct armflash_subdev_info, map);
-
- if (info->plat && info->plat->set_vpp)
- info->plat->set_vpp(on);
-}
-
-static const char *probes[] = { "cmdlinepart", "RedBoot", "afs", NULL };
-
-static int armflash_subdev_probe(struct armflash_subdev_info *subdev,
- struct resource *res)
-{
- struct flash_platform_data *plat = subdev->plat;
- resource_size_t size = res->end - res->start + 1;
- void __iomem *base;
- int err = 0;
-
- if (!request_mem_region(res->start, size, subdev->name)) {
- err = -EBUSY;
- goto out;
- }
-
- base = ioremap(res->start, size);
- if (!base) {
- err = -ENOMEM;
- goto no_mem;
- }
-
- /*
- * look for CFI based flash parts fitted to this board
- */
- subdev->map.size = size;
- subdev->map.bankwidth = plat->width;
- subdev->map.phys = res->start;
- subdev->map.virt = base;
- subdev->map.name = subdev->name;
- subdev->map.set_vpp = armflash_set_vpp;
-
- simple_map_init(&subdev->map);
-
- /*
- * Also, the CFI layer automatically works out what size
- * of chips we have, and does the necessary identification
- * for us automatically.
- */
- subdev->mtd = do_map_probe(plat->map_name, &subdev->map);
- if (!subdev->mtd) {
- err = -ENXIO;
- goto no_device;
- }
-
- subdev->mtd->owner = THIS_MODULE;
-
- /* Successful? */
- if (err == 0)
- return err;
-
- if (subdev->mtd)
- map_destroy(subdev->mtd);
- no_device:
- iounmap(base);
- no_mem:
- release_mem_region(res->start, size);
- out:
- return err;
-}
-
-static void armflash_subdev_remove(struct armflash_subdev_info *subdev)
-{
- if (subdev->mtd)
- map_destroy(subdev->mtd);
- if (subdev->map.virt)
- iounmap(subdev->map.virt);
- kfree(subdev->name);
- subdev->name = NULL;
- release_mem_region(subdev->map.phys, subdev->map.size);
-}
-
-static int armflash_probe(struct platform_device *dev)
-{
- struct flash_platform_data *plat = dev->dev.platform_data;
- unsigned int size;
- struct armflash_info *info;
- int i, nr, err;
-
- /* Count the number of devices */
- for (nr = 0; ; nr++)
- if (!platform_get_resource(dev, IORESOURCE_MEM, nr))
- break;
- if (nr == 0) {
- err = -ENODEV;
- goto out;
- }
-
- size = sizeof(struct armflash_info) +
- sizeof(struct armflash_subdev_info) * nr;
- info = kzalloc(size, GFP_KERNEL);
- if (!info) {
- err = -ENOMEM;
- goto out;
- }
-
- if (plat && plat->init) {
- err = plat->init();
- if (err)
- goto no_resource;
- }
-
- for (i = 0; i < nr; i++) {
- struct armflash_subdev_info *subdev = &info->subdev[i];
- struct resource *res;
-
- res = platform_get_resource(dev, IORESOURCE_MEM, i);
- if (!res)
- break;
-
- if (nr == 1)
- /* No MTD concatenation, just use the default name */
- subdev->name = kstrdup(dev_name(&dev->dev), GFP_KERNEL);
- else
- subdev->name = kasprintf(GFP_KERNEL, "%s-%d",
- dev_name(&dev->dev), i);
- if (!subdev->name) {
- err = -ENOMEM;
- break;
- }
- subdev->plat = plat;
-
- err = armflash_subdev_probe(subdev, res);
- if (err) {
- kfree(subdev->name);
- subdev->name = NULL;
- break;
- }
- }
- info->nr_subdev = i;
-
- if (err)
- goto subdev_err;
-
- if (info->nr_subdev == 1)
- info->mtd = info->subdev[0].mtd;
- else if (info->nr_subdev > 1) {
- struct mtd_info *cdev[info->nr_subdev];
-
- /*
- * We detected multiple devices. Concatenate them together.
- */
- for (i = 0; i < info->nr_subdev; i++)
- cdev[i] = info->subdev[i].mtd;
-
- info->mtd = mtd_concat_create(cdev, info->nr_subdev,
- dev_name(&dev->dev));
- if (info->mtd == NULL)
- err = -ENXIO;
- }
-
- if (err < 0)
- goto cleanup;
-
- err = parse_mtd_partitions(info->mtd, probes, &info->parts, 0);
- if (err > 0) {
- err = add_mtd_partitions(info->mtd, info->parts, err);
- if (err)
- printk(KERN_ERR
- "mtd partition registration failed: %d\n", err);
- }
-
- if (err == 0) {
- platform_set_drvdata(dev, info);
- return err;
- }
-
- /*
- * We got an error, free all resources.
- */
- cleanup:
- if (info->mtd) {
- del_mtd_partitions(info->mtd);
- if (info->mtd != info->subdev[0].mtd)
- mtd_concat_destroy(info->mtd);
- }
- kfree(info->parts);
- subdev_err:
- for (i = info->nr_subdev - 1; i >= 0; i--)
- armflash_subdev_remove(&info->subdev[i]);
- no_resource:
- if (plat && plat->exit)
- plat->exit();
- kfree(info);
- out:
- return err;
-}
-
-static int armflash_remove(struct platform_device *dev)
-{
- struct armflash_info *info = platform_get_drvdata(dev);
- struct flash_platform_data *plat = dev->dev.platform_data;
- int i;
-
- platform_set_drvdata(dev, NULL);
-
- if (info) {
- if (info->mtd) {
- del_mtd_partitions(info->mtd);
- if (info->mtd != info->subdev[0].mtd)
- mtd_concat_destroy(info->mtd);
- }
- kfree(info->parts);
-
- for (i = info->nr_subdev - 1; i >= 0; i--)
- armflash_subdev_remove(&info->subdev[i]);
-
- if (plat && plat->exit)
- plat->exit();
-
- kfree(info);
- }
-
- return 0;
-}
-
-static struct platform_driver armflash_driver = {
- .probe = armflash_probe,
- .remove = armflash_remove,
- .driver = {
- .name = "armflash",
- .owner = THIS_MODULE,
- },
-};
-
-static int __init armflash_init(void)
-{
- return platform_driver_register(&armflash_driver);
-}
-
-static void __exit armflash_exit(void)
-{
- platform_driver_unregister(&armflash_driver);
-}
-
-module_init(armflash_init);
-module_exit(armflash_exit);
-
-MODULE_AUTHOR("ARM Ltd");
-MODULE_DESCRIPTION("ARM Integrator CFI map driver");
-MODULE_LICENSE("GPL");
-MODULE_ALIAS("platform:armflash");
diff --git a/drivers/mtd/maps/pcmciamtd.c b/drivers/mtd/maps/pcmciamtd.c
index 6799e75..33dc282 100644
--- a/drivers/mtd/maps/pcmciamtd.c
+++ b/drivers/mtd/maps/pcmciamtd.c
@@ -694,7 +694,7 @@
return pcmciamtd_config(link);
}
-static struct pcmcia_device_id pcmciamtd_ids[] = {
+static const struct pcmcia_device_id pcmciamtd_ids[] = {
PCMCIA_DEVICE_FUNC_ID(1),
PCMCIA_DEVICE_PROD_ID123("IO DATA", "PCS-2M", "2MB SRAM", 0x547e66dc, 0x1fed36cd, 0x36eadd21),
PCMCIA_DEVICE_PROD_ID12("IBM", "2MB SRAM", 0xb569a6e5, 0x36eadd21),
diff --git a/drivers/mtd/maps/physmap.c b/drivers/mtd/maps/physmap.c
index 7522df4..1a9b94f 100644
--- a/drivers/mtd/maps/physmap.c
+++ b/drivers/mtd/maps/physmap.c
@@ -67,9 +67,25 @@
if (info->mtd[i] != NULL)
map_destroy(info->mtd[i]);
}
+
+ if (physmap_data->exit)
+ physmap_data->exit(dev);
+
return 0;
}
+static void physmap_set_vpp(struct map_info *map, int state)
+{
+ struct platform_device *pdev;
+ struct physmap_flash_data *physmap_data;
+
+ pdev = (struct platform_device *)map->map_priv_1;
+ physmap_data = pdev->dev.platform_data;
+
+ if (physmap_data->set_vpp)
+ physmap_data->set_vpp(pdev, state);
+}
+
static const char *rom_probe_types[] = {
"cfi_probe",
"jedec_probe",
@@ -77,7 +93,8 @@
"map_rom",
NULL };
#ifdef CONFIG_MTD_PARTITIONS
-static const char *part_probe_types[] = { "cmdlinepart", "RedBoot", NULL };
+static const char *part_probe_types[] = { "cmdlinepart", "RedBoot", "afs",
+ NULL };
#endif
static int physmap_flash_probe(struct platform_device *dev)
@@ -100,6 +117,12 @@
goto err_out;
}
+ if (physmap_data->init) {
+ err = physmap_data->init(dev);
+ if (err)
+ goto err_out;
+ }
+
platform_set_drvdata(dev, info);
for (i = 0; i < dev->num_resources; i++) {
@@ -120,8 +143,9 @@
info->map[i].phys = dev->resource[i].start;
info->map[i].size = resource_size(&dev->resource[i]);
info->map[i].bankwidth = physmap_data->width;
- info->map[i].set_vpp = physmap_data->set_vpp;
+ info->map[i].set_vpp = physmap_set_vpp;
info->map[i].pfow_base = physmap_data->pfow_base;
+ info->map[i].map_priv_1 = (unsigned long)dev;
info->map[i].virt = devm_ioremap(&dev->dev, info->map[i].phys,
info->map[i].size);
diff --git a/drivers/mtd/maps/pismo.c b/drivers/mtd/maps/pismo.c
index f4ce273..65bd1cd 100644
--- a/drivers/mtd/maps/pismo.c
+++ b/drivers/mtd/maps/pismo.c
@@ -50,39 +50,13 @@
struct platform_device *dev[PISMO_NUM_CS];
};
-/* FIXME: set_vpp could do with a better calling convention */
-static struct pismo_data *vpp_pismo;
-static DEFINE_MUTEX(pismo_mutex);
-
-static int pismo_setvpp_probe_fix(struct pismo_data *pismo)
+static void pismo_set_vpp(struct platform_device *pdev, int on)
{
- mutex_lock(&pismo_mutex);
- if (vpp_pismo) {
- mutex_unlock(&pismo_mutex);
- kfree(pismo);
- return -EBUSY;
- }
- vpp_pismo = pismo;
- mutex_unlock(&pismo_mutex);
- return 0;
-}
-
-static void pismo_setvpp_remove_fix(struct pismo_data *pismo)
-{
- mutex_lock(&pismo_mutex);
- if (vpp_pismo == pismo)
- vpp_pismo = NULL;
- mutex_unlock(&pismo_mutex);
-}
-
-static void pismo_set_vpp(struct map_info *map, int on)
-{
- struct pismo_data *pismo = vpp_pismo;
+ struct i2c_client *client = to_i2c_client(pdev->dev.parent);
+ struct pismo_data *pismo = i2c_get_clientdata(client);
pismo->vpp(pismo->vpp_data, on);
}
-/* end of hack */
-
static unsigned int __devinit pismo_width_to_bytes(unsigned int width)
{
@@ -231,9 +205,6 @@
for (i = 0; i < ARRAY_SIZE(pismo->dev); i++)
platform_device_unregister(pismo->dev[i]);
- /* FIXME: set_vpp needs saner arguments */
- pismo_setvpp_remove_fix(pismo);
-
kfree(pismo);
return 0;
@@ -257,11 +228,6 @@
if (!pismo)
return -ENOMEM;
- /* FIXME: set_vpp needs saner arguments */
- ret = pismo_setvpp_probe_fix(pismo);
- if (ret)
- return ret;
-
pismo->client = client;
if (pdata) {
pismo->vpp = pdata->set_vpp;
diff --git a/drivers/mtd/ubi/cdev.c b/drivers/mtd/ubi/cdev.c
index af9fb0f..191f3bb 100644
--- a/drivers/mtd/ubi/cdev.c
+++ b/drivers/mtd/ubi/cdev.c
@@ -115,7 +115,7 @@
mode = UBI_READONLY;
dbg_gen("open device %d, volume %d, mode %d",
- ubi_num, vol_id, mode);
+ ubi_num, vol_id, mode);
desc = ubi_open_volume(ubi_num, vol_id, mode);
if (IS_ERR(desc))
@@ -158,7 +158,7 @@
loff_t new_offset;
if (vol->updating) {
- /* Update is in progress, seeking is prohibited */
+ /* Update is in progress, seeking is prohibited */
dbg_err("updating");
return -EBUSY;
}
@@ -561,18 +561,18 @@
}
/* Set volume property command */
- case UBI_IOCSETPROP:
+ case UBI_IOCSETVOLPROP:
{
- struct ubi_set_prop_req req;
+ struct ubi_set_vol_prop_req req;
err = copy_from_user(&req, argp,
- sizeof(struct ubi_set_prop_req));
+ sizeof(struct ubi_set_vol_prop_req));
if (err) {
err = -EFAULT;
break;
}
switch (req.property) {
- case UBI_PROP_DIRECT_WRITE:
+ case UBI_VOL_PROP_DIRECT_WRITE:
mutex_lock(&ubi->device_mutex);
desc->vol->direct_writes = !!req.value;
mutex_unlock(&ubi->device_mutex);
@@ -1100,5 +1100,5 @@
.owner = THIS_MODULE,
.unlocked_ioctl = ctrl_cdev_ioctl,
.compat_ioctl = ctrl_cdev_compat_ioctl,
- .llseek = noop_llseek,
+ .llseek = no_llseek,
};
diff --git a/drivers/mtd/ubi/debug.c b/drivers/mtd/ubi/debug.c
index d4d07e5..2224cbe 100644
--- a/drivers/mtd/ubi/debug.c
+++ b/drivers/mtd/ubi/debug.c
@@ -30,15 +30,12 @@
#include <linux/module.h>
#include <linux/moduleparam.h>
-unsigned int ubi_msg_flags;
unsigned int ubi_chk_flags;
unsigned int ubi_tst_flags;
-module_param_named(debug_msgs, ubi_msg_flags, uint, S_IRUGO | S_IWUSR);
module_param_named(debug_chks, ubi_chk_flags, uint, S_IRUGO | S_IWUSR);
module_param_named(debug_tsts, ubi_chk_flags, uint, S_IRUGO | S_IWUSR);
-MODULE_PARM_DESC(debug_msgs, "Debug message type flags");
MODULE_PARM_DESC(debug_chks, "Debug check flags");
MODULE_PARM_DESC(debug_tsts, "Debug special test flags");
@@ -75,15 +72,15 @@
{
printk(KERN_DEBUG "Volume identifier header dump:\n");
printk(KERN_DEBUG "\tmagic %08x\n", be32_to_cpu(vid_hdr->magic));
- printk(KERN_DEBUG "\tversion %d\n", (int)vid_hdr->version);
- printk(KERN_DEBUG "\tvol_type %d\n", (int)vid_hdr->vol_type);
- printk(KERN_DEBUG "\tcopy_flag %d\n", (int)vid_hdr->copy_flag);
- printk(KERN_DEBUG "\tcompat %d\n", (int)vid_hdr->compat);
- printk(KERN_DEBUG "\tvol_id %d\n", be32_to_cpu(vid_hdr->vol_id));
- printk(KERN_DEBUG "\tlnum %d\n", be32_to_cpu(vid_hdr->lnum));
- printk(KERN_DEBUG "\tdata_size %d\n", be32_to_cpu(vid_hdr->data_size));
- printk(KERN_DEBUG "\tused_ebs %d\n", be32_to_cpu(vid_hdr->used_ebs));
- printk(KERN_DEBUG "\tdata_pad %d\n", be32_to_cpu(vid_hdr->data_pad));
+ printk(KERN_DEBUG "\tversion %d\n", (int)vid_hdr->version);
+ printk(KERN_DEBUG "\tvol_type %d\n", (int)vid_hdr->vol_type);
+ printk(KERN_DEBUG "\tcopy_flag %d\n", (int)vid_hdr->copy_flag);
+ printk(KERN_DEBUG "\tcompat %d\n", (int)vid_hdr->compat);
+ printk(KERN_DEBUG "\tvol_id %d\n", be32_to_cpu(vid_hdr->vol_id));
+ printk(KERN_DEBUG "\tlnum %d\n", be32_to_cpu(vid_hdr->lnum));
+ printk(KERN_DEBUG "\tdata_size %d\n", be32_to_cpu(vid_hdr->data_size));
+ printk(KERN_DEBUG "\tused_ebs %d\n", be32_to_cpu(vid_hdr->used_ebs));
+ printk(KERN_DEBUG "\tdata_pad %d\n", be32_to_cpu(vid_hdr->data_pad));
printk(KERN_DEBUG "\tsqnum %llu\n",
(unsigned long long)be64_to_cpu(vid_hdr->sqnum));
printk(KERN_DEBUG "\thdr_crc %08x\n", be32_to_cpu(vid_hdr->hdr_crc));
diff --git a/drivers/mtd/ubi/debug.h b/drivers/mtd/ubi/debug.h
index 0b0c288..3f1a09c 100644
--- a/drivers/mtd/ubi/debug.h
+++ b/drivers/mtd/ubi/debug.h
@@ -21,11 +21,17 @@
#ifndef __UBI_DEBUG_H__
#define __UBI_DEBUG_H__
+struct ubi_ec_hdr;
+struct ubi_vid_hdr;
+struct ubi_volume;
+struct ubi_vtbl_record;
+struct ubi_scan_volume;
+struct ubi_scan_leb;
+struct ubi_mkvol_req;
+
#ifdef CONFIG_MTD_UBI_DEBUG
#include <linux/random.h>
-#define dbg_err(fmt, ...) ubi_err(fmt, ##__VA_ARGS__)
-
#define ubi_assert(expr) do { \
if (unlikely(!(expr))) { \
printk(KERN_CRIT "UBI assert failed in %s at %u (pid %d)\n", \
@@ -34,24 +40,28 @@
} \
} while (0)
-#define dbg_msg(fmt, ...) \
- printk(KERN_DEBUG "UBI DBG (pid %d): %s: " fmt "\n", \
- current->pid, __func__, ##__VA_ARGS__)
-
-#define dbg_do_msg(typ, fmt, ...) do { \
- if (ubi_msg_flags & typ) \
- dbg_msg(fmt, ##__VA_ARGS__); \
-} while (0)
+#define dbg_err(fmt, ...) ubi_err(fmt, ##__VA_ARGS__)
#define ubi_dbg_dump_stack() dump_stack()
-struct ubi_ec_hdr;
-struct ubi_vid_hdr;
-struct ubi_volume;
-struct ubi_vtbl_record;
-struct ubi_scan_volume;
-struct ubi_scan_leb;
-struct ubi_mkvol_req;
+#define ubi_dbg_print_hex_dump(l, ps, pt, r, g, b, len, a) \
+ print_hex_dump(l, ps, pt, r, g, b, len, a)
+
+#define ubi_dbg_msg(type, fmt, ...) \
+ pr_debug("UBI DBG " type ": " fmt "\n", ##__VA_ARGS__)
+
+/* Just a debugging messages not related to any specific UBI subsystem */
+#define dbg_msg(fmt, ...) ubi_dbg_msg("msg", fmt, ##__VA_ARGS__)
+/* General debugging messages */
+#define dbg_gen(fmt, ...) ubi_dbg_msg("gen", fmt, ##__VA_ARGS__)
+/* Messages from the eraseblock association sub-system */
+#define dbg_eba(fmt, ...) ubi_dbg_msg("eba", fmt, ##__VA_ARGS__)
+/* Messages from the wear-leveling sub-system */
+#define dbg_wl(fmt, ...) ubi_dbg_msg("wl", fmt, ##__VA_ARGS__)
+/* Messages from the input/output sub-system */
+#define dbg_io(fmt, ...) ubi_dbg_msg("io", fmt, ##__VA_ARGS__)
+/* Initialization and build messages */
+#define dbg_bld(fmt, ...) ubi_dbg_msg("bld", fmt, ##__VA_ARGS__)
void ubi_dbg_dump_ec_hdr(const struct ubi_ec_hdr *ec_hdr);
void ubi_dbg_dump_vid_hdr(const struct ubi_vid_hdr *vid_hdr);
@@ -62,43 +72,6 @@
void ubi_dbg_dump_mkvol_req(const struct ubi_mkvol_req *req);
void ubi_dbg_dump_flash(struct ubi_device *ubi, int pnum, int offset, int len);
-extern unsigned int ubi_msg_flags;
-
-/*
- * Debugging message type flags (must match msg_type_names in debug.c).
- *
- * UBI_MSG_GEN: general messages
- * UBI_MSG_EBA: journal messages
- * UBI_MSG_WL: mount messages
- * UBI_MSG_IO: commit messages
- * UBI_MSG_BLD: LEB find messages
- */
-enum {
- UBI_MSG_GEN = 0x1,
- UBI_MSG_EBA = 0x2,
- UBI_MSG_WL = 0x4,
- UBI_MSG_IO = 0x8,
- UBI_MSG_BLD = 0x10,
-};
-
-#define ubi_dbg_print_hex_dump(l, ps, pt, r, g, b, len, a) \
- print_hex_dump(l, ps, pt, r, g, b, len, a)
-
-/* General debugging messages */
-#define dbg_gen(fmt, ...) dbg_do_msg(UBI_MSG_GEN, fmt, ##__VA_ARGS__)
-
-/* Messages from the eraseblock association sub-system */
-#define dbg_eba(fmt, ...) dbg_do_msg(UBI_MSG_EBA, fmt, ##__VA_ARGS__)
-
-/* Messages from the wear-leveling sub-system */
-#define dbg_wl(fmt, ...) dbg_do_msg(UBI_MSG_WL, fmt, ##__VA_ARGS__)
-
-/* Messages from the input/output sub-system */
-#define dbg_io(fmt, ...) dbg_do_msg(UBI_MSG_IO, fmt, ##__VA_ARGS__)
-
-/* Initialization and build messages */
-#define dbg_bld(fmt, ...) dbg_do_msg(UBI_MSG_BLD, fmt, ##__VA_ARGS__)
-
extern unsigned int ubi_chk_flags;
/*
@@ -184,31 +157,61 @@
#else
-#define ubi_assert(expr) ({})
-#define dbg_err(fmt, ...) ({})
-#define dbg_msg(fmt, ...) ({})
-#define dbg_gen(fmt, ...) ({})
-#define dbg_eba(fmt, ...) ({})
-#define dbg_wl(fmt, ...) ({})
-#define dbg_io(fmt, ...) ({})
-#define dbg_bld(fmt, ...) ({})
-#define ubi_dbg_dump_stack() ({})
-#define ubi_dbg_dump_ec_hdr(ec_hdr) ({})
-#define ubi_dbg_dump_vid_hdr(vid_hdr) ({})
-#define ubi_dbg_dump_vol_info(vol) ({})
-#define ubi_dbg_dump_vtbl_record(r, idx) ({})
-#define ubi_dbg_dump_sv(sv) ({})
-#define ubi_dbg_dump_seb(seb, type) ({})
-#define ubi_dbg_dump_mkvol_req(req) ({})
-#define ubi_dbg_dump_flash(ubi, pnum, offset, len) ({})
-#define ubi_dbg_print_hex_dump(l, ps, pt, r, g, b, len, a) ({})
+/* Use "if (0)" to make compiler check arguments even if debugging is off */
+#define ubi_assert(expr) do { \
+ if (0) { \
+ printk(KERN_CRIT "UBI assert failed in %s at %u (pid %d)\n", \
+ __func__, __LINE__, current->pid); \
+ } \
+} while (0)
-#define ubi_dbg_is_bgt_disabled() 0
-#define ubi_dbg_is_bitflip() 0
-#define ubi_dbg_is_write_failure() 0
-#define ubi_dbg_is_erase_failure() 0
-#define ubi_dbg_check_all_ff(ubi, pnum, offset, len) 0
-#define ubi_dbg_check_write(ubi, buf, pnum, offset, len) 0
+#define dbg_err(fmt, ...) do { \
+ if (0) \
+ ubi_err(fmt, ##__VA_ARGS__); \
+} while (0)
+
+#define ubi_dbg_msg(fmt, ...) do { \
+ if (0) \
+ pr_debug(fmt "\n", ##__VA_ARGS__); \
+} while (0)
+
+#define dbg_msg(fmt, ...) ubi_dbg_msg(fmt, ##__VA_ARGS__)
+#define dbg_gen(fmt, ...) ubi_dbg_msg(fmt, ##__VA_ARGS__)
+#define dbg_eba(fmt, ...) ubi_dbg_msg(fmt, ##__VA_ARGS__)
+#define dbg_wl(fmt, ...) ubi_dbg_msg(fmt, ##__VA_ARGS__)
+#define dbg_io(fmt, ...) ubi_dbg_msg(fmt, ##__VA_ARGS__)
+#define dbg_bld(fmt, ...) ubi_dbg_msg(fmt, ##__VA_ARGS__)
+
+static inline void ubi_dbg_dump_stack(void) { return; }
+static inline void
+ubi_dbg_dump_ec_hdr(const struct ubi_ec_hdr *ec_hdr) { return; }
+static inline void
+ubi_dbg_dump_vid_hdr(const struct ubi_vid_hdr *vid_hdr) { return; }
+static inline void
+ubi_dbg_dump_vol_info(const struct ubi_volume *vol) { return; }
+static inline void
+ubi_dbg_dump_vtbl_record(const struct ubi_vtbl_record *r, int idx) { return; }
+static inline void ubi_dbg_dump_sv(const struct ubi_scan_volume *sv) { return; }
+static inline void ubi_dbg_dump_seb(const struct ubi_scan_leb *seb,
+ int type) { return; }
+static inline void
+ubi_dbg_dump_mkvol_req(const struct ubi_mkvol_req *req) { return; }
+static inline void ubi_dbg_dump_flash(struct ubi_device *ubi,
+ int pnum, int offset, int len) { return; }
+static inline void
+ubi_dbg_print_hex_dump(const char *l, const char *ps, int pt, int r,
+ int g, const void *b, size_t len, bool a) { return; }
+
+static inline int ubi_dbg_is_bgt_disabled(void) { return 0; }
+static inline int ubi_dbg_is_bitflip(void) { return 0; }
+static inline int ubi_dbg_is_write_failure(void) { return 0; }
+static inline int ubi_dbg_is_erase_failure(void) { return 0; }
+static inline int ubi_dbg_check_all_ff(struct ubi_device *ubi,
+ int pnum, int offset,
+ int len) { return 0; }
+static inline int ubi_dbg_check_write(struct ubi_device *ubi,
+ const void *buf, int pnum,
+ int offset, int len) { return 0; }
#endif /* !CONFIG_MTD_UBI_DEBUG */
#endif /* !__UBI_DEBUG_H__ */
diff --git a/drivers/mtd/ubi/io.c b/drivers/mtd/ubi/io.c
index e347cc4..8c1b1c7 100644
--- a/drivers/mtd/ubi/io.c
+++ b/drivers/mtd/ubi/io.c
@@ -189,8 +189,8 @@
}
if (retries++ < UBI_IO_RETRIES) {
- dbg_io("error %d%s while reading %d bytes from PEB %d:%d,"
- " read only %zd bytes, retry",
+ dbg_io("error %d%s while reading %d bytes from PEB "
+ "%d:%d, read only %zd bytes, retry",
err, errstr, len, pnum, offset, read);
yield();
goto retry;
@@ -465,7 +465,7 @@
}
err = patt_count;
- ubi_msg("PEB %d passed torture test, do not mark it a bad", pnum);
+ ubi_msg("PEB %d passed torture test, do not mark it as bad", pnum);
out:
mutex_unlock(&ubi->buf_mutex);
diff --git a/drivers/mtd/ubi/scan.c b/drivers/mtd/ubi/scan.c
index d2d12ab..2135a53 100644
--- a/drivers/mtd/ubi/scan.c
+++ b/drivers/mtd/ubi/scan.c
@@ -1103,7 +1103,7 @@
* otherwise, only print a warning.
*/
if (si->corr_peb_count >= max_corr) {
- ubi_err("too many corrupted PEBs, refusing this device");
+ ubi_err("too many corrupted PEBs, refusing");
return -EINVAL;
}
}
diff --git a/drivers/mtd/ubi/ubi-media.h b/drivers/mtd/ubi/ubi-media.h
index 503ea9b..6fb8ec2 100644
--- a/drivers/mtd/ubi/ubi-media.h
+++ b/drivers/mtd/ubi/ubi-media.h
@@ -164,7 +164,7 @@
__be32 image_seq;
__u8 padding2[32];
__be32 hdr_crc;
-} __attribute__ ((packed));
+} __packed;
/**
* struct ubi_vid_hdr - on-flash UBI volume identifier header.
@@ -292,7 +292,7 @@
__be64 sqnum;
__u8 padding3[12];
__be32 hdr_crc;
-} __attribute__ ((packed));
+} __packed;
/* Internal UBI volumes count */
#define UBI_INT_VOL_COUNT 1
@@ -373,6 +373,6 @@
__u8 flags;
__u8 padding[23];
__be32 crc;
-} __attribute__ ((packed));
+} __packed;
#endif /* !__UBI_MEDIA_H__ */
diff --git a/drivers/mtd/ubi/ubi.h b/drivers/mtd/ubi/ubi.h
index f1be8b7..c6c2229 100644
--- a/drivers/mtd/ubi/ubi.h
+++ b/drivers/mtd/ubi/ubi.h
@@ -341,8 +341,8 @@
* protected from the wear-leveling worker)
* @pq_head: protection queue head
* @wl_lock: protects the @used, @free, @pq, @pq_head, @lookuptbl, @move_from,
- * @move_to, @move_to_put @erase_pending, @wl_scheduled, @works,
- * @erroneous, and @erroneous_peb_count fields
+ * @move_to, @move_to_put @erase_pending, @wl_scheduled, @works,
+ * @erroneous, and @erroneous_peb_count fields
* @move_mutex: serializes eraseblock moves
* @work_sem: synchronizes the WL worker with use tasks
* @wl_scheduled: non-zero if the wear-leveling was scheduled
diff --git a/drivers/mtd/ubi/wl.c b/drivers/mtd/ubi/wl.c
index b4cf57d..ff2c495 100644
--- a/drivers/mtd/ubi/wl.c
+++ b/drivers/mtd/ubi/wl.c
@@ -1570,7 +1570,8 @@
* @ec: the erase counter to check
*
* This function returns zero if the erase counter of physical eraseblock @pnum
- * is equivalent to @ec, and a negative error code if not or if an error occurred.
+ * is equivalent to @ec, and a negative error code if not or if an error
+ * occurred.
*/
static int paranoid_check_ec(struct ubi_device *ubi, int pnum, int ec)
{
diff --git a/drivers/net/Makefile b/drivers/net/Makefile
index 209fbb7..776a478 100644
--- a/drivers/net/Makefile
+++ b/drivers/net/Makefile
@@ -31,6 +31,7 @@
obj-$(CONFIG_ATL1E) += atl1e/
obj-$(CONFIG_ATL1C) += atl1c/
obj-$(CONFIG_GIANFAR) += gianfar_driver.o
+obj-$(CONFIG_PTP_1588_CLOCK_GIANFAR) += gianfar_ptp.o
obj-$(CONFIG_TEHUTI) += tehuti.o
obj-$(CONFIG_ENIC) += enic/
obj-$(CONFIG_JME) += jme.o
diff --git a/drivers/net/arm/ixp4xx_eth.c b/drivers/net/arm/ixp4xx_eth.c
index 9eb9b98..de51e84 100644
--- a/drivers/net/arm/ixp4xx_eth.c
+++ b/drivers/net/arm/ixp4xx_eth.c
@@ -30,9 +30,12 @@
#include <linux/etherdevice.h>
#include <linux/io.h>
#include <linux/kernel.h>
+#include <linux/net_tstamp.h>
#include <linux/phy.h>
#include <linux/platform_device.h>
+#include <linux/ptp_classify.h>
#include <linux/slab.h>
+#include <mach/ixp46x_ts.h>
#include <mach/npe.h>
#include <mach/qmgr.h>
@@ -67,6 +70,10 @@
#define RXFREE_QUEUE(port_id) (NPE_ID(port_id) + 26)
#define TXDONE_QUEUE 31
+#define PTP_SLAVE_MODE 1
+#define PTP_MASTER_MODE 2
+#define PORT2CHANNEL(p) NPE_ID(p->id)
+
/* TX Control Registers */
#define TX_CNTRL0_TX_EN 0x01
#define TX_CNTRL0_HALFDUPLEX 0x02
@@ -171,6 +178,8 @@
int id; /* logical port ID */
int speed, duplex;
u8 firmware[4];
+ int hwts_tx_en;
+ int hwts_rx_en;
};
/* NPE message structure */
@@ -246,6 +255,172 @@
static struct port *npe_port_tab[MAX_NPES];
static struct dma_pool *dma_pool;
+static struct sock_filter ptp_filter[] = {
+ PTP_FILTER
+};
+
+static int ixp_ptp_match(struct sk_buff *skb, u16 uid_hi, u32 uid_lo, u16 seqid)
+{
+ u8 *data = skb->data;
+ unsigned int offset;
+ u16 *hi, *id;
+ u32 lo;
+
+ if (sk_run_filter(skb, ptp_filter) != PTP_CLASS_V1_IPV4)
+ return 0;
+
+ offset = ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN;
+
+ if (skb->len < offset + OFF_PTP_SEQUENCE_ID + sizeof(seqid))
+ return 0;
+
+ hi = (u16 *)(data + offset + OFF_PTP_SOURCE_UUID);
+ id = (u16 *)(data + offset + OFF_PTP_SEQUENCE_ID);
+
+ memcpy(&lo, &hi[1], sizeof(lo));
+
+ return (uid_hi == ntohs(*hi) &&
+ uid_lo == ntohl(lo) &&
+ seqid == ntohs(*id));
+}
+
+static void ixp_rx_timestamp(struct port *port, struct sk_buff *skb)
+{
+ struct skb_shared_hwtstamps *shhwtstamps;
+ struct ixp46x_ts_regs *regs;
+ u64 ns;
+ u32 ch, hi, lo, val;
+ u16 uid, seq;
+
+ if (!port->hwts_rx_en)
+ return;
+
+ ch = PORT2CHANNEL(port);
+
+ regs = (struct ixp46x_ts_regs __iomem *) IXP4XX_TIMESYNC_BASE_VIRT;
+
+ val = __raw_readl(®s->channel[ch].ch_event);
+
+ if (!(val & RX_SNAPSHOT_LOCKED))
+ return;
+
+ lo = __raw_readl(®s->channel[ch].src_uuid_lo);
+ hi = __raw_readl(®s->channel[ch].src_uuid_hi);
+
+ uid = hi & 0xffff;
+ seq = (hi >> 16) & 0xffff;
+
+ if (!ixp_ptp_match(skb, htons(uid), htonl(lo), htons(seq)))
+ goto out;
+
+ lo = __raw_readl(®s->channel[ch].rx_snap_lo);
+ hi = __raw_readl(®s->channel[ch].rx_snap_hi);
+ ns = ((u64) hi) << 32;
+ ns |= lo;
+ ns <<= TICKS_NS_SHIFT;
+
+ shhwtstamps = skb_hwtstamps(skb);
+ memset(shhwtstamps, 0, sizeof(*shhwtstamps));
+ shhwtstamps->hwtstamp = ns_to_ktime(ns);
+out:
+ __raw_writel(RX_SNAPSHOT_LOCKED, ®s->channel[ch].ch_event);
+}
+
+static void ixp_tx_timestamp(struct port *port, struct sk_buff *skb)
+{
+ struct skb_shared_hwtstamps shhwtstamps;
+ struct ixp46x_ts_regs *regs;
+ struct skb_shared_info *shtx;
+ u64 ns;
+ u32 ch, cnt, hi, lo, val;
+
+ shtx = skb_shinfo(skb);
+ if (unlikely(shtx->tx_flags & SKBTX_HW_TSTAMP && port->hwts_tx_en))
+ shtx->tx_flags |= SKBTX_IN_PROGRESS;
+ else
+ return;
+
+ ch = PORT2CHANNEL(port);
+
+ regs = (struct ixp46x_ts_regs __iomem *) IXP4XX_TIMESYNC_BASE_VIRT;
+
+ /*
+ * This really stinks, but we have to poll for the Tx time stamp.
+ * Usually, the time stamp is ready after 4 to 6 microseconds.
+ */
+ for (cnt = 0; cnt < 100; cnt++) {
+ val = __raw_readl(®s->channel[ch].ch_event);
+ if (val & TX_SNAPSHOT_LOCKED)
+ break;
+ udelay(1);
+ }
+ if (!(val & TX_SNAPSHOT_LOCKED)) {
+ shtx->tx_flags &= ~SKBTX_IN_PROGRESS;
+ return;
+ }
+
+ lo = __raw_readl(®s->channel[ch].tx_snap_lo);
+ hi = __raw_readl(®s->channel[ch].tx_snap_hi);
+ ns = ((u64) hi) << 32;
+ ns |= lo;
+ ns <<= TICKS_NS_SHIFT;
+
+ memset(&shhwtstamps, 0, sizeof(shhwtstamps));
+ shhwtstamps.hwtstamp = ns_to_ktime(ns);
+ skb_tstamp_tx(skb, &shhwtstamps);
+
+ __raw_writel(TX_SNAPSHOT_LOCKED, ®s->channel[ch].ch_event);
+}
+
+static int hwtstamp_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
+{
+ struct hwtstamp_config cfg;
+ struct ixp46x_ts_regs *regs;
+ struct port *port = netdev_priv(netdev);
+ int ch;
+
+ if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
+ return -EFAULT;
+
+ if (cfg.flags) /* reserved for future extensions */
+ return -EINVAL;
+
+ ch = PORT2CHANNEL(port);
+ regs = (struct ixp46x_ts_regs __iomem *) IXP4XX_TIMESYNC_BASE_VIRT;
+
+ switch (cfg.tx_type) {
+ case HWTSTAMP_TX_OFF:
+ port->hwts_tx_en = 0;
+ break;
+ case HWTSTAMP_TX_ON:
+ port->hwts_tx_en = 1;
+ break;
+ default:
+ return -ERANGE;
+ }
+
+ switch (cfg.rx_filter) {
+ case HWTSTAMP_FILTER_NONE:
+ port->hwts_rx_en = 0;
+ break;
+ case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
+ port->hwts_rx_en = PTP_SLAVE_MODE;
+ __raw_writel(0, ®s->channel[ch].ch_control);
+ break;
+ case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
+ port->hwts_rx_en = PTP_MASTER_MODE;
+ __raw_writel(MASTER_MODE, ®s->channel[ch].ch_control);
+ break;
+ default:
+ return -ERANGE;
+ }
+
+ /* Clear out any old time stamps. */
+ __raw_writel(TX_SNAPSHOT_LOCKED | RX_SNAPSHOT_LOCKED,
+ ®s->channel[ch].ch_event);
+
+ return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
+}
static int ixp4xx_mdio_cmd(struct mii_bus *bus, int phy_id, int location,
int write, u16 cmd)
@@ -573,6 +748,7 @@
debug_pkt(dev, "eth_poll", skb->data, skb->len);
+ ixp_rx_timestamp(port, skb);
skb->protocol = eth_type_trans(skb, dev);
dev->stats.rx_packets++;
dev->stats.rx_bytes += skb->len;
@@ -679,14 +855,12 @@
return NETDEV_TX_OK;
}
memcpy_swab32(mem, (u32 *)((int)skb->data & ~3), bytes / 4);
- dev_kfree_skb(skb);
#endif
phys = dma_map_single(&dev->dev, mem, bytes, DMA_TO_DEVICE);
if (dma_mapping_error(&dev->dev, phys)) {
-#ifdef __ARMEB__
dev_kfree_skb(skb);
-#else
+#ifndef __ARMEB__
kfree(mem);
#endif
dev->stats.tx_dropped++;
@@ -728,6 +902,13 @@
#if DEBUG_TX
printk(KERN_DEBUG "%s: eth_xmit end\n", dev->name);
#endif
+
+ ixp_tx_timestamp(port, skb);
+ skb_tx_timestamp(skb);
+
+#ifndef __ARMEB__
+ dev_kfree_skb(skb);
+#endif
return NETDEV_TX_OK;
}
@@ -783,6 +964,9 @@
if (!netif_running(dev))
return -EINVAL;
+ if (cpu_is_ixp46x() && cmd == SIOCSHWTSTAMP)
+ return hwtstamp_ioctl(dev, req, cmd);
+
return phy_mii_ioctl(port->phydev, req, cmd);
}
@@ -1171,6 +1355,11 @@
char phy_id[MII_BUS_ID_SIZE + 3];
int err;
+ if (ptp_filter_init(ptp_filter, ARRAY_SIZE(ptp_filter))) {
+ pr_err("ixp4xx_eth: bad ptp filter\n");
+ return -EINVAL;
+ }
+
if (!(dev = alloc_etherdev(sizeof(struct port))))
return -ENOMEM;
diff --git a/drivers/net/caif/caif_serial.c b/drivers/net/caif/caif_serial.c
index 3df0c0f..73c7e03 100644
--- a/drivers/net/caif/caif_serial.c
+++ b/drivers/net/caif/caif_serial.c
@@ -167,8 +167,8 @@
#endif
-static void ldisc_receive(struct tty_struct *tty, const u8 *data,
- char *flags, int count)
+static unsigned int ldisc_receive(struct tty_struct *tty,
+ const u8 *data, char *flags, int count)
{
struct sk_buff *skb = NULL;
struct ser_device *ser;
@@ -215,6 +215,8 @@
} else
++ser->dev->stats.rx_dropped;
update_tty_status(ser);
+
+ return count;
}
static int handle_tx(struct ser_device *ser)
diff --git a/drivers/net/can/slcan.c b/drivers/net/can/slcan.c
index 1b49df6..75622d5 100644
--- a/drivers/net/can/slcan.c
+++ b/drivers/net/can/slcan.c
@@ -425,16 +425,17 @@
* in parallel
*/
-static void slcan_receive_buf(struct tty_struct *tty,
+static unsigned int slcan_receive_buf(struct tty_struct *tty,
const unsigned char *cp, char *fp, int count)
{
struct slcan *sl = (struct slcan *) tty->disc_data;
+ int bytes = count;
if (!sl || sl->magic != SLCAN_MAGIC || !netif_running(sl->dev))
- return;
+ return -ENODEV;
/* Read the characters out of the buffer */
- while (count--) {
+ while (bytes--) {
if (fp && *fp++) {
if (!test_and_set_bit(SLF_ERROR, &sl->flags))
sl->dev->stats.rx_errors++;
@@ -443,6 +444,8 @@
}
slcan_unesc(sl, *cp++);
}
+
+ return count;
}
/************************************
diff --git a/drivers/net/can/softing/softing_cs.c b/drivers/net/can/softing/softing_cs.c
index c11bb4d..c0e1b1e 100644
--- a/drivers/net/can/softing/softing_cs.c
+++ b/drivers/net/can/softing/softing_cs.c
@@ -315,7 +315,7 @@
return ret ?: -ENODEV;
}
-static /*const*/ struct pcmcia_device_id softingcs_ids[] = {
+static const struct pcmcia_device_id softingcs_ids[] = {
/* softing */
PCMCIA_DEVICE_MANF_CARD(0x0168, 0x0001),
PCMCIA_DEVICE_MANF_CARD(0x0168, 0x0002),
diff --git a/drivers/net/e1000e/netdev.c b/drivers/net/e1000e/netdev.c
index d960056..3310c3d 100644
--- a/drivers/net/e1000e/netdev.c
+++ b/drivers/net/e1000e/netdev.c
@@ -5361,7 +5361,7 @@
#ifdef CONFIG_PCIEASPM
static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
{
- pci_disable_link_state(pdev, state);
+ pci_disable_link_state_locked(pdev, state);
}
#else
static void __e1000e_disable_aspm(struct pci_dev *pdev, u16 state)
diff --git a/drivers/net/gianfar_ptp.c b/drivers/net/gianfar_ptp.c
new file mode 100644
index 0000000..d8e1753
--- /dev/null
+++ b/drivers/net/gianfar_ptp.c
@@ -0,0 +1,588 @@
+/*
+ * PTP 1588 clock using the eTSEC
+ *
+ * Copyright (C) 2010 OMICRON electronics GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/device.h>
+#include <linux/hrtimer.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/timex.h>
+#include <linux/io.h>
+
+#include <linux/ptp_clock_kernel.h>
+
+#include "gianfar.h"
+
+/*
+ * gianfar ptp registers
+ * Generated by regen.tcl on Thu May 13 01:38:57 PM CEST 2010
+ */
+struct gianfar_ptp_registers {
+ u32 tmr_ctrl; /* Timer control register */
+ u32 tmr_tevent; /* Timestamp event register */
+ u32 tmr_temask; /* Timer event mask register */
+ u32 tmr_pevent; /* Timestamp event register */
+ u32 tmr_pemask; /* Timer event mask register */
+ u32 tmr_stat; /* Timestamp status register */
+ u32 tmr_cnt_h; /* Timer counter high register */
+ u32 tmr_cnt_l; /* Timer counter low register */
+ u32 tmr_add; /* Timer drift compensation addend register */
+ u32 tmr_acc; /* Timer accumulator register */
+ u32 tmr_prsc; /* Timer prescale */
+ u8 res1[4];
+ u32 tmroff_h; /* Timer offset high */
+ u32 tmroff_l; /* Timer offset low */
+ u8 res2[8];
+ u32 tmr_alarm1_h; /* Timer alarm 1 high register */
+ u32 tmr_alarm1_l; /* Timer alarm 1 high register */
+ u32 tmr_alarm2_h; /* Timer alarm 2 high register */
+ u32 tmr_alarm2_l; /* Timer alarm 2 high register */
+ u8 res3[48];
+ u32 tmr_fiper1; /* Timer fixed period interval */
+ u32 tmr_fiper2; /* Timer fixed period interval */
+ u32 tmr_fiper3; /* Timer fixed period interval */
+ u8 res4[20];
+ u32 tmr_etts1_h; /* Timestamp of general purpose external trigger */
+ u32 tmr_etts1_l; /* Timestamp of general purpose external trigger */
+ u32 tmr_etts2_h; /* Timestamp of general purpose external trigger */
+ u32 tmr_etts2_l; /* Timestamp of general purpose external trigger */
+};
+
+/* Bit definitions for the TMR_CTRL register */
+#define ALM1P (1<<31) /* Alarm1 output polarity */
+#define ALM2P (1<<30) /* Alarm2 output polarity */
+#define FS (1<<28) /* FIPER start indication */
+#define PP1L (1<<27) /* Fiper1 pulse loopback mode enabled. */
+#define PP2L (1<<26) /* Fiper2 pulse loopback mode enabled. */
+#define TCLK_PERIOD_SHIFT (16) /* 1588 timer reference clock period. */
+#define TCLK_PERIOD_MASK (0x3ff)
+#define RTPE (1<<15) /* Record Tx Timestamp to PAL Enable. */
+#define FRD (1<<14) /* FIPER Realignment Disable */
+#define ESFDP (1<<11) /* External Tx/Rx SFD Polarity. */
+#define ESFDE (1<<10) /* External Tx/Rx SFD Enable. */
+#define ETEP2 (1<<9) /* External trigger 2 edge polarity */
+#define ETEP1 (1<<8) /* External trigger 1 edge polarity */
+#define COPH (1<<7) /* Generated clock output phase. */
+#define CIPH (1<<6) /* External oscillator input clock phase */
+#define TMSR (1<<5) /* Timer soft reset. */
+#define BYP (1<<3) /* Bypass drift compensated clock */
+#define TE (1<<2) /* 1588 timer enable. */
+#define CKSEL_SHIFT (0) /* 1588 Timer reference clock source */
+#define CKSEL_MASK (0x3)
+
+/* Bit definitions for the TMR_TEVENT register */
+#define ETS2 (1<<25) /* External trigger 2 timestamp sampled */
+#define ETS1 (1<<24) /* External trigger 1 timestamp sampled */
+#define ALM2 (1<<17) /* Current time = alarm time register 2 */
+#define ALM1 (1<<16) /* Current time = alarm time register 1 */
+#define PP1 (1<<7) /* periodic pulse generated on FIPER1 */
+#define PP2 (1<<6) /* periodic pulse generated on FIPER2 */
+#define PP3 (1<<5) /* periodic pulse generated on FIPER3 */
+
+/* Bit definitions for the TMR_TEMASK register */
+#define ETS2EN (1<<25) /* External trigger 2 timestamp enable */
+#define ETS1EN (1<<24) /* External trigger 1 timestamp enable */
+#define ALM2EN (1<<17) /* Timer ALM2 event enable */
+#define ALM1EN (1<<16) /* Timer ALM1 event enable */
+#define PP1EN (1<<7) /* Periodic pulse event 1 enable */
+#define PP2EN (1<<6) /* Periodic pulse event 2 enable */
+
+/* Bit definitions for the TMR_PEVENT register */
+#define TXP2 (1<<9) /* PTP transmitted timestamp im TXTS2 */
+#define TXP1 (1<<8) /* PTP transmitted timestamp in TXTS1 */
+#define RXP (1<<0) /* PTP frame has been received */
+
+/* Bit definitions for the TMR_PEMASK register */
+#define TXP2EN (1<<9) /* Transmit PTP packet event 2 enable */
+#define TXP1EN (1<<8) /* Transmit PTP packet event 1 enable */
+#define RXPEN (1<<0) /* Receive PTP packet event enable */
+
+/* Bit definitions for the TMR_STAT register */
+#define STAT_VEC_SHIFT (0) /* Timer general purpose status vector */
+#define STAT_VEC_MASK (0x3f)
+
+/* Bit definitions for the TMR_PRSC register */
+#define PRSC_OCK_SHIFT (0) /* Output clock division/prescale factor. */
+#define PRSC_OCK_MASK (0xffff)
+
+
+#define DRIVER "gianfar_ptp"
+#define DEFAULT_CKSEL 1
+#define N_ALARM 1 /* first alarm is used internally to reset fipers */
+#define N_EXT_TS 2
+#define REG_SIZE sizeof(struct gianfar_ptp_registers)
+
+struct etsects {
+ struct gianfar_ptp_registers *regs;
+ spinlock_t lock; /* protects regs */
+ struct ptp_clock *clock;
+ struct ptp_clock_info caps;
+ struct resource *rsrc;
+ int irq;
+ u64 alarm_interval; /* for periodic alarm */
+ u64 alarm_value;
+ u32 tclk_period; /* nanoseconds */
+ u32 tmr_prsc;
+ u32 tmr_add;
+ u32 cksel;
+ u32 tmr_fiper1;
+ u32 tmr_fiper2;
+};
+
+/*
+ * Register access functions
+ */
+
+/* Caller must hold etsects->lock. */
+static u64 tmr_cnt_read(struct etsects *etsects)
+{
+ u64 ns;
+ u32 lo, hi;
+
+ lo = gfar_read(&etsects->regs->tmr_cnt_l);
+ hi = gfar_read(&etsects->regs->tmr_cnt_h);
+ ns = ((u64) hi) << 32;
+ ns |= lo;
+ return ns;
+}
+
+/* Caller must hold etsects->lock. */
+static void tmr_cnt_write(struct etsects *etsects, u64 ns)
+{
+ u32 hi = ns >> 32;
+ u32 lo = ns & 0xffffffff;
+
+ gfar_write(&etsects->regs->tmr_cnt_l, lo);
+ gfar_write(&etsects->regs->tmr_cnt_h, hi);
+}
+
+/* Caller must hold etsects->lock. */
+static void set_alarm(struct etsects *etsects)
+{
+ u64 ns;
+ u32 lo, hi;
+
+ ns = tmr_cnt_read(etsects) + 1500000000ULL;
+ ns = div_u64(ns, 1000000000UL) * 1000000000ULL;
+ ns -= etsects->tclk_period;
+ hi = ns >> 32;
+ lo = ns & 0xffffffff;
+ gfar_write(&etsects->regs->tmr_alarm1_l, lo);
+ gfar_write(&etsects->regs->tmr_alarm1_h, hi);
+}
+
+/* Caller must hold etsects->lock. */
+static void set_fipers(struct etsects *etsects)
+{
+ u32 tmr_ctrl = gfar_read(&etsects->regs->tmr_ctrl);
+
+ gfar_write(&etsects->regs->tmr_ctrl, tmr_ctrl & (~TE));
+ gfar_write(&etsects->regs->tmr_prsc, etsects->tmr_prsc);
+ gfar_write(&etsects->regs->tmr_fiper1, etsects->tmr_fiper1);
+ gfar_write(&etsects->regs->tmr_fiper2, etsects->tmr_fiper2);
+ set_alarm(etsects);
+ gfar_write(&etsects->regs->tmr_ctrl, tmr_ctrl|TE);
+}
+
+/*
+ * Interrupt service routine
+ */
+
+static irqreturn_t isr(int irq, void *priv)
+{
+ struct etsects *etsects = priv;
+ struct ptp_clock_event event;
+ u64 ns;
+ u32 ack = 0, lo, hi, mask, val;
+
+ val = gfar_read(&etsects->regs->tmr_tevent);
+
+ if (val & ETS1) {
+ ack |= ETS1;
+ hi = gfar_read(&etsects->regs->tmr_etts1_h);
+ lo = gfar_read(&etsects->regs->tmr_etts1_l);
+ event.type = PTP_CLOCK_EXTTS;
+ event.index = 0;
+ event.timestamp = ((u64) hi) << 32;
+ event.timestamp |= lo;
+ ptp_clock_event(etsects->clock, &event);
+ }
+
+ if (val & ETS2) {
+ ack |= ETS2;
+ hi = gfar_read(&etsects->regs->tmr_etts2_h);
+ lo = gfar_read(&etsects->regs->tmr_etts2_l);
+ event.type = PTP_CLOCK_EXTTS;
+ event.index = 1;
+ event.timestamp = ((u64) hi) << 32;
+ event.timestamp |= lo;
+ ptp_clock_event(etsects->clock, &event);
+ }
+
+ if (val & ALM2) {
+ ack |= ALM2;
+ if (etsects->alarm_value) {
+ event.type = PTP_CLOCK_ALARM;
+ event.index = 0;
+ event.timestamp = etsects->alarm_value;
+ ptp_clock_event(etsects->clock, &event);
+ }
+ if (etsects->alarm_interval) {
+ ns = etsects->alarm_value + etsects->alarm_interval;
+ hi = ns >> 32;
+ lo = ns & 0xffffffff;
+ spin_lock(&etsects->lock);
+ gfar_write(&etsects->regs->tmr_alarm2_l, lo);
+ gfar_write(&etsects->regs->tmr_alarm2_h, hi);
+ spin_unlock(&etsects->lock);
+ etsects->alarm_value = ns;
+ } else {
+ gfar_write(&etsects->regs->tmr_tevent, ALM2);
+ spin_lock(&etsects->lock);
+ mask = gfar_read(&etsects->regs->tmr_temask);
+ mask &= ~ALM2EN;
+ gfar_write(&etsects->regs->tmr_temask, mask);
+ spin_unlock(&etsects->lock);
+ etsects->alarm_value = 0;
+ etsects->alarm_interval = 0;
+ }
+ }
+
+ if (val & PP1) {
+ ack |= PP1;
+ event.type = PTP_CLOCK_PPS;
+ ptp_clock_event(etsects->clock, &event);
+ }
+
+ if (ack) {
+ gfar_write(&etsects->regs->tmr_tevent, ack);
+ return IRQ_HANDLED;
+ } else
+ return IRQ_NONE;
+}
+
+/*
+ * PTP clock operations
+ */
+
+static int ptp_gianfar_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
+{
+ u64 adj;
+ u32 diff, tmr_add;
+ int neg_adj = 0;
+ struct etsects *etsects = container_of(ptp, struct etsects, caps);
+
+ if (ppb < 0) {
+ neg_adj = 1;
+ ppb = -ppb;
+ }
+ tmr_add = etsects->tmr_add;
+ adj = tmr_add;
+ adj *= ppb;
+ diff = div_u64(adj, 1000000000ULL);
+
+ tmr_add = neg_adj ? tmr_add - diff : tmr_add + diff;
+
+ gfar_write(&etsects->regs->tmr_add, tmr_add);
+
+ return 0;
+}
+
+static int ptp_gianfar_adjtime(struct ptp_clock_info *ptp, s64 delta)
+{
+ s64 now;
+ unsigned long flags;
+ struct etsects *etsects = container_of(ptp, struct etsects, caps);
+
+ spin_lock_irqsave(&etsects->lock, flags);
+
+ now = tmr_cnt_read(etsects);
+ now += delta;
+ tmr_cnt_write(etsects, now);
+
+ spin_unlock_irqrestore(&etsects->lock, flags);
+
+ set_fipers(etsects);
+
+ return 0;
+}
+
+static int ptp_gianfar_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
+{
+ u64 ns;
+ u32 remainder;
+ unsigned long flags;
+ struct etsects *etsects = container_of(ptp, struct etsects, caps);
+
+ spin_lock_irqsave(&etsects->lock, flags);
+
+ ns = tmr_cnt_read(etsects);
+
+ spin_unlock_irqrestore(&etsects->lock, flags);
+
+ ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
+ ts->tv_nsec = remainder;
+ return 0;
+}
+
+static int ptp_gianfar_settime(struct ptp_clock_info *ptp,
+ const struct timespec *ts)
+{
+ u64 ns;
+ unsigned long flags;
+ struct etsects *etsects = container_of(ptp, struct etsects, caps);
+
+ ns = ts->tv_sec * 1000000000ULL;
+ ns += ts->tv_nsec;
+
+ spin_lock_irqsave(&etsects->lock, flags);
+
+ tmr_cnt_write(etsects, ns);
+ set_fipers(etsects);
+
+ spin_unlock_irqrestore(&etsects->lock, flags);
+
+ return 0;
+}
+
+static int ptp_gianfar_enable(struct ptp_clock_info *ptp,
+ struct ptp_clock_request *rq, int on)
+{
+ struct etsects *etsects = container_of(ptp, struct etsects, caps);
+ unsigned long flags;
+ u32 bit, mask;
+
+ switch (rq->type) {
+ case PTP_CLK_REQ_EXTTS:
+ switch (rq->extts.index) {
+ case 0:
+ bit = ETS1EN;
+ break;
+ case 1:
+ bit = ETS2EN;
+ break;
+ default:
+ return -EINVAL;
+ }
+ spin_lock_irqsave(&etsects->lock, flags);
+ mask = gfar_read(&etsects->regs->tmr_temask);
+ if (on)
+ mask |= bit;
+ else
+ mask &= ~bit;
+ gfar_write(&etsects->regs->tmr_temask, mask);
+ spin_unlock_irqrestore(&etsects->lock, flags);
+ return 0;
+
+ case PTP_CLK_REQ_PPS:
+ spin_lock_irqsave(&etsects->lock, flags);
+ mask = gfar_read(&etsects->regs->tmr_temask);
+ if (on)
+ mask |= PP1EN;
+ else
+ mask &= ~PP1EN;
+ gfar_write(&etsects->regs->tmr_temask, mask);
+ spin_unlock_irqrestore(&etsects->lock, flags);
+ return 0;
+
+ default:
+ break;
+ }
+
+ return -EOPNOTSUPP;
+}
+
+static struct ptp_clock_info ptp_gianfar_caps = {
+ .owner = THIS_MODULE,
+ .name = "gianfar clock",
+ .max_adj = 512000,
+ .n_alarm = N_ALARM,
+ .n_ext_ts = N_EXT_TS,
+ .n_per_out = 0,
+ .pps = 1,
+ .adjfreq = ptp_gianfar_adjfreq,
+ .adjtime = ptp_gianfar_adjtime,
+ .gettime = ptp_gianfar_gettime,
+ .settime = ptp_gianfar_settime,
+ .enable = ptp_gianfar_enable,
+};
+
+/* OF device tree */
+
+static int get_of_u32(struct device_node *node, char *str, u32 *val)
+{
+ int plen;
+ const u32 *prop = of_get_property(node, str, &plen);
+
+ if (!prop || plen != sizeof(*prop))
+ return -1;
+ *val = *prop;
+ return 0;
+}
+
+static int gianfar_ptp_probe(struct platform_device *dev)
+{
+ struct device_node *node = dev->dev.of_node;
+ struct etsects *etsects;
+ struct timespec now;
+ int err = -ENOMEM;
+ u32 tmr_ctrl;
+ unsigned long flags;
+
+ etsects = kzalloc(sizeof(*etsects), GFP_KERNEL);
+ if (!etsects)
+ goto no_memory;
+
+ err = -ENODEV;
+
+ etsects->caps = ptp_gianfar_caps;
+ etsects->cksel = DEFAULT_CKSEL;
+
+ if (get_of_u32(node, "fsl,tclk-period", &etsects->tclk_period) ||
+ get_of_u32(node, "fsl,tmr-prsc", &etsects->tmr_prsc) ||
+ get_of_u32(node, "fsl,tmr-add", &etsects->tmr_add) ||
+ get_of_u32(node, "fsl,tmr-fiper1", &etsects->tmr_fiper1) ||
+ get_of_u32(node, "fsl,tmr-fiper2", &etsects->tmr_fiper2) ||
+ get_of_u32(node, "fsl,max-adj", &etsects->caps.max_adj)) {
+ pr_err("device tree node missing required elements\n");
+ goto no_node;
+ }
+
+ etsects->irq = platform_get_irq(dev, 0);
+
+ if (etsects->irq == NO_IRQ) {
+ pr_err("irq not in device tree\n");
+ goto no_node;
+ }
+ if (request_irq(etsects->irq, isr, 0, DRIVER, etsects)) {
+ pr_err("request_irq failed\n");
+ goto no_node;
+ }
+
+ etsects->rsrc = platform_get_resource(dev, IORESOURCE_MEM, 0);
+ if (!etsects->rsrc) {
+ pr_err("no resource\n");
+ goto no_resource;
+ }
+ if (request_resource(&ioport_resource, etsects->rsrc)) {
+ pr_err("resource busy\n");
+ goto no_resource;
+ }
+
+ spin_lock_init(&etsects->lock);
+
+ etsects->regs = ioremap(etsects->rsrc->start,
+ 1 + etsects->rsrc->end - etsects->rsrc->start);
+ if (!etsects->regs) {
+ pr_err("ioremap ptp registers failed\n");
+ goto no_ioremap;
+ }
+ getnstimeofday(&now);
+ ptp_gianfar_settime(&etsects->caps, &now);
+
+ tmr_ctrl =
+ (etsects->tclk_period & TCLK_PERIOD_MASK) << TCLK_PERIOD_SHIFT |
+ (etsects->cksel & CKSEL_MASK) << CKSEL_SHIFT;
+
+ spin_lock_irqsave(&etsects->lock, flags);
+
+ gfar_write(&etsects->regs->tmr_ctrl, tmr_ctrl);
+ gfar_write(&etsects->regs->tmr_add, etsects->tmr_add);
+ gfar_write(&etsects->regs->tmr_prsc, etsects->tmr_prsc);
+ gfar_write(&etsects->regs->tmr_fiper1, etsects->tmr_fiper1);
+ gfar_write(&etsects->regs->tmr_fiper2, etsects->tmr_fiper2);
+ set_alarm(etsects);
+ gfar_write(&etsects->regs->tmr_ctrl, tmr_ctrl|FS|RTPE|TE);
+
+ spin_unlock_irqrestore(&etsects->lock, flags);
+
+ etsects->clock = ptp_clock_register(&etsects->caps);
+ if (IS_ERR(etsects->clock)) {
+ err = PTR_ERR(etsects->clock);
+ goto no_clock;
+ }
+
+ dev_set_drvdata(&dev->dev, etsects);
+
+ return 0;
+
+no_clock:
+no_ioremap:
+ release_resource(etsects->rsrc);
+no_resource:
+ free_irq(etsects->irq, etsects);
+no_node:
+ kfree(etsects);
+no_memory:
+ return err;
+}
+
+static int gianfar_ptp_remove(struct platform_device *dev)
+{
+ struct etsects *etsects = dev_get_drvdata(&dev->dev);
+
+ gfar_write(&etsects->regs->tmr_temask, 0);
+ gfar_write(&etsects->regs->tmr_ctrl, 0);
+
+ ptp_clock_unregister(etsects->clock);
+ iounmap(etsects->regs);
+ release_resource(etsects->rsrc);
+ free_irq(etsects->irq, etsects);
+ kfree(etsects);
+
+ return 0;
+}
+
+static struct of_device_id match_table[] = {
+ { .compatible = "fsl,etsec-ptp" },
+ {},
+};
+
+static struct platform_driver gianfar_ptp_driver = {
+ .driver = {
+ .name = "gianfar_ptp",
+ .of_match_table = match_table,
+ .owner = THIS_MODULE,
+ },
+ .probe = gianfar_ptp_probe,
+ .remove = gianfar_ptp_remove,
+};
+
+/* module operations */
+
+static int __init ptp_gianfar_init(void)
+{
+ return platform_driver_register(&gianfar_ptp_driver);
+}
+
+module_init(ptp_gianfar_init);
+
+static void __exit ptp_gianfar_exit(void)
+{
+ platform_driver_unregister(&gianfar_ptp_driver);
+}
+
+module_exit(ptp_gianfar_exit);
+
+MODULE_AUTHOR("Richard Cochran <richard.cochran@omicron.at>");
+MODULE_DESCRIPTION("PTP clock using the eTSEC");
+MODULE_LICENSE("GPL");
diff --git a/drivers/net/hamradio/6pack.c b/drivers/net/hamradio/6pack.c
index 3e5d0b6..9920896 100644
--- a/drivers/net/hamradio/6pack.c
+++ b/drivers/net/hamradio/6pack.c
@@ -456,7 +456,7 @@
* a block of 6pack data has been received, which can now be decapsulated
* and sent on to some IP layer for further processing.
*/
-static void sixpack_receive_buf(struct tty_struct *tty,
+static unsigned int sixpack_receive_buf(struct tty_struct *tty,
const unsigned char *cp, char *fp, int count)
{
struct sixpack *sp;
@@ -464,11 +464,11 @@
int count1;
if (!count)
- return;
+ return 0;
sp = sp_get(tty);
if (!sp)
- return;
+ return -ENODEV;
memcpy(buf, cp, count < sizeof(buf) ? count : sizeof(buf));
@@ -487,6 +487,8 @@
sp_put(sp);
tty_unthrottle(tty);
+
+ return count1;
}
/*
diff --git a/drivers/net/hamradio/mkiss.c b/drivers/net/hamradio/mkiss.c
index 4c62839..0e4f235 100644
--- a/drivers/net/hamradio/mkiss.c
+++ b/drivers/net/hamradio/mkiss.c
@@ -923,13 +923,14 @@
* a block of data has been received, which can now be decapsulated
* and sent on to the AX.25 layer for further processing.
*/
-static void mkiss_receive_buf(struct tty_struct *tty, const unsigned char *cp,
- char *fp, int count)
+static unsigned int mkiss_receive_buf(struct tty_struct *tty,
+ const unsigned char *cp, char *fp, int count)
{
struct mkiss *ax = mkiss_get(tty);
+ int bytes = count;
if (!ax)
- return;
+ return -ENODEV;
/*
* Argh! mtu change time! - costs us the packet part received
@@ -939,7 +940,7 @@
ax_changedmtu(ax);
/* Read the characters out of the buffer */
- while (count--) {
+ while (bytes--) {
if (fp != NULL && *fp++) {
if (!test_and_set_bit(AXF_ERROR, &ax->flags))
ax->dev->stats.rx_errors++;
@@ -952,6 +953,8 @@
mkiss_put(ax);
tty_unthrottle(tty);
+
+ return count;
}
/*
diff --git a/drivers/net/ioc3-eth.c b/drivers/net/ioc3-eth.c
index 96c9561..32f07f8 100644
--- a/drivers/net/ioc3-eth.c
+++ b/drivers/net/ioc3-eth.c
@@ -915,7 +915,7 @@
skb = ioc3_alloc_skb(RX_BUF_ALLOC_SIZE, GFP_ATOMIC);
if (!skb) {
- show_free_areas();
+ show_free_areas(0);
continue;
}
diff --git a/drivers/net/irda/irtty-sir.c b/drivers/net/irda/irtty-sir.c
index 3352b24..035861d 100644
--- a/drivers/net/irda/irtty-sir.c
+++ b/drivers/net/irda/irtty-sir.c
@@ -216,23 +216,23 @@
* usbserial: urb-complete-interrupt / softint
*/
-static void irtty_receive_buf(struct tty_struct *tty, const unsigned char *cp,
- char *fp, int count)
+static unsigned int irtty_receive_buf(struct tty_struct *tty,
+ const unsigned char *cp, char *fp, int count)
{
struct sir_dev *dev;
struct sirtty_cb *priv = tty->disc_data;
int i;
- IRDA_ASSERT(priv != NULL, return;);
- IRDA_ASSERT(priv->magic == IRTTY_MAGIC, return;);
+ IRDA_ASSERT(priv != NULL, return -ENODEV;);
+ IRDA_ASSERT(priv->magic == IRTTY_MAGIC, return -EINVAL;);
if (unlikely(count==0)) /* yes, this happens */
- return;
+ return 0;
dev = priv->dev;
if (!dev) {
IRDA_WARNING("%s(), not ready yet!\n", __func__);
- return;
+ return -ENODEV;
}
for (i = 0; i < count; i++) {
@@ -242,11 +242,13 @@
if (fp && *fp++) {
IRDA_DEBUG(0, "Framing or parity error!\n");
sirdev_receive(dev, NULL, 0); /* notify sir_dev (updating stats) */
- return;
+ return -EINVAL;
}
}
sirdev_receive(dev, cp, count);
+
+ return count;
}
/*
diff --git a/drivers/net/pcmcia/3c574_cs.c b/drivers/net/pcmcia/3c574_cs.c
index 81ac330..34c5e1c 100644
--- a/drivers/net/pcmcia/3c574_cs.c
+++ b/drivers/net/pcmcia/3c574_cs.c
@@ -1150,7 +1150,7 @@
return 0;
}
-static struct pcmcia_device_id tc574_ids[] = {
+static const struct pcmcia_device_id tc574_ids[] = {
PCMCIA_DEVICE_MANF_CARD(0x0101, 0x0574),
PCMCIA_MFC_DEVICE_CIS_MANF_CARD(0, 0x0101, 0x0556, "cis/3CCFEM556.cis"),
PCMCIA_DEVICE_NULL,
diff --git a/drivers/net/pcmcia/3c589_cs.c b/drivers/net/pcmcia/3c589_cs.c
index 79b9ca0..4a1a358 100644
--- a/drivers/net/pcmcia/3c589_cs.c
+++ b/drivers/net/pcmcia/3c589_cs.c
@@ -908,7 +908,7 @@
return 0;
}
-static struct pcmcia_device_id tc589_ids[] = {
+static const struct pcmcia_device_id tc589_ids[] = {
PCMCIA_MFC_DEVICE_MANF_CARD(0, 0x0101, 0x0562),
PCMCIA_MFC_DEVICE_PROD_ID1(0, "Motorola MARQUIS", 0xf03e4e77),
PCMCIA_DEVICE_MANF_CARD(0x0101, 0x0589),
diff --git a/drivers/net/pcmcia/axnet_cs.c b/drivers/net/pcmcia/axnet_cs.c
index 3077d72..9953db7 100644
--- a/drivers/net/pcmcia/axnet_cs.c
+++ b/drivers/net/pcmcia/axnet_cs.c
@@ -687,7 +687,7 @@
outsw(nic_base + AXNET_DATAPORT, buf, count>>1);
}
-static struct pcmcia_device_id axnet_ids[] = {
+static const struct pcmcia_device_id axnet_ids[] = {
PCMCIA_PFC_DEVICE_MANF_CARD(0, 0x016c, 0x0081),
PCMCIA_DEVICE_MANF_CARD(0x018a, 0x0301),
PCMCIA_DEVICE_MANF_CARD(0x01bf, 0x2328),
diff --git a/drivers/net/pcmcia/com20020_cs.c b/drivers/net/pcmcia/com20020_cs.c
index 27bfad7..980e65c 100644
--- a/drivers/net/pcmcia/com20020_cs.c
+++ b/drivers/net/pcmcia/com20020_cs.c
@@ -316,7 +316,7 @@
return 0;
}
-static struct pcmcia_device_id com20020_ids[] = {
+static const struct pcmcia_device_id com20020_ids[] = {
PCMCIA_DEVICE_PROD_ID12("Contemporary Control Systems, Inc.",
"PCM20 Arcnet Adapter", 0x59991666, 0x95dfffaf),
PCMCIA_DEVICE_PROD_ID12("SoHard AG",
diff --git a/drivers/net/pcmcia/fmvj18x_cs.c b/drivers/net/pcmcia/fmvj18x_cs.c
index 530ab5a..723815e 100644
--- a/drivers/net/pcmcia/fmvj18x_cs.c
+++ b/drivers/net/pcmcia/fmvj18x_cs.c
@@ -667,7 +667,7 @@
/*====================================================================*/
-static struct pcmcia_device_id fmvj18x_ids[] = {
+static const struct pcmcia_device_id fmvj18x_ids[] = {
PCMCIA_DEVICE_MANF_CARD(0x0004, 0x0004),
PCMCIA_DEVICE_PROD_ID12("EAGLE Technology", "NE200 ETHERNET LAN MBH10302 04", 0x528c88c4, 0x74f91e59),
PCMCIA_DEVICE_PROD_ID12("Eiger Labs,Inc", "EPX-10BT PC Card Ethernet 10BT", 0x53af556e, 0x877f9922),
diff --git a/drivers/net/pcmcia/ibmtr_cs.c b/drivers/net/pcmcia/ibmtr_cs.c
index 15d57f5..6006d54 100644
--- a/drivers/net/pcmcia/ibmtr_cs.c
+++ b/drivers/net/pcmcia/ibmtr_cs.c
@@ -340,7 +340,7 @@
outb(0x40, dev->base_addr);
}
-static struct pcmcia_device_id ibmtr_ids[] = {
+static const struct pcmcia_device_id ibmtr_ids[] = {
PCMCIA_DEVICE_PROD_ID12("3Com", "TokenLink Velocity PC Card", 0x41240e5b, 0x82c3734e),
PCMCIA_DEVICE_PROD_ID12("IBM", "TOKEN RING", 0xb569a6e5, 0xbf8eed47),
PCMCIA_DEVICE_NULL,
diff --git a/drivers/net/pcmcia/nmclan_cs.c b/drivers/net/pcmcia/nmclan_cs.c
index 76683d9..9d70b65 100644
--- a/drivers/net/pcmcia/nmclan_cs.c
+++ b/drivers/net/pcmcia/nmclan_cs.c
@@ -1494,7 +1494,7 @@
} /* set_multicast_list */
-static struct pcmcia_device_id nmclan_ids[] = {
+static const struct pcmcia_device_id nmclan_ids[] = {
PCMCIA_DEVICE_PROD_ID12("New Media Corporation", "Ethernet", 0x085a850b, 0x00b2e941),
PCMCIA_DEVICE_PROD_ID12("Portable Add-ons", "Ethernet+", 0xebf1d60, 0xad673aaf),
PCMCIA_DEVICE_NULL,
diff --git a/drivers/net/pcmcia/pcnet_cs.c b/drivers/net/pcmcia/pcnet_cs.c
index e953793..b4fd7c3 100644
--- a/drivers/net/pcmcia/pcnet_cs.c
+++ b/drivers/net/pcmcia/pcnet_cs.c
@@ -1463,7 +1463,7 @@
/*====================================================================*/
-static struct pcmcia_device_id pcnet_ids[] = {
+static const struct pcmcia_device_id pcnet_ids[] = {
PCMCIA_PFC_DEVICE_MANF_CARD(0, 0x0057, 0x0021),
PCMCIA_PFC_DEVICE_MANF_CARD(0, 0x0104, 0x000a),
PCMCIA_PFC_DEVICE_MANF_CARD(0, 0x0105, 0xea15),
diff --git a/drivers/net/pcmcia/smc91c92_cs.c b/drivers/net/pcmcia/smc91c92_cs.c
index 288e4f1..1cd9394 100644
--- a/drivers/net/pcmcia/smc91c92_cs.c
+++ b/drivers/net/pcmcia/smc91c92_cs.c
@@ -2014,7 +2014,7 @@
return rc;
}
-static struct pcmcia_device_id smc91c92_ids[] = {
+static const struct pcmcia_device_id smc91c92_ids[] = {
PCMCIA_PFC_DEVICE_MANF_CARD(0, 0x0109, 0x0501),
PCMCIA_PFC_DEVICE_MANF_CARD(0, 0x0140, 0x000a),
PCMCIA_PFC_DEVICE_PROD_ID123(0, "MEGAHERTZ", "CC/XJEM3288", "DATA/FAX/CELL ETHERNET MODEM", 0xf510db04, 0x04cd2988, 0x46a52d63),
diff --git a/drivers/net/pcmcia/xirc2ps_cs.c b/drivers/net/pcmcia/xirc2ps_cs.c
index a46b7fd..e33b190 100644
--- a/drivers/net/pcmcia/xirc2ps_cs.c
+++ b/drivers/net/pcmcia/xirc2ps_cs.c
@@ -1738,7 +1738,7 @@
return 0;
}
-static struct pcmcia_device_id xirc2ps_ids[] = {
+static const struct pcmcia_device_id xirc2ps_ids[] = {
PCMCIA_PFC_DEVICE_MANF_CARD(0, 0x0089, 0x110a),
PCMCIA_PFC_DEVICE_MANF_CARD(0, 0x0138, 0x110a),
PCMCIA_PFC_DEVICE_PROD_ID13(0, "Xircom", "CEM28", 0x2e3ee845, 0x0ea978ea),
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 13bebab..2333215 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -19,6 +19,7 @@
obj-$(CONFIG_MDIO_BITBANG) += mdio-bitbang.o
obj-$(CONFIG_MDIO_GPIO) += mdio-gpio.o
obj-$(CONFIG_NATIONAL_PHY) += national.o
+obj-$(CONFIG_DP83640_PHY) += dp83640.o
obj-$(CONFIG_STE10XP) += ste10Xp.o
obj-$(CONFIG_MICREL_PHY) += micrel.o
obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o
diff --git a/drivers/net/phy/dp83640.c b/drivers/net/phy/dp83640.c
new file mode 100644
index 0000000..b0c9522
--- /dev/null
+++ b/drivers/net/phy/dp83640.c
@@ -0,0 +1,1100 @@
+/*
+ * Driver for the National Semiconductor DP83640 PHYTER
+ *
+ * Copyright (C) 2010 OMICRON electronics GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/ethtool.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/mii.h>
+#include <linux/module.h>
+#include <linux/net_tstamp.h>
+#include <linux/netdevice.h>
+#include <linux/phy.h>
+#include <linux/ptp_classify.h>
+#include <linux/ptp_clock_kernel.h>
+
+#include "dp83640_reg.h"
+
+#define DP83640_PHY_ID 0x20005ce1
+#define PAGESEL 0x13
+#define LAYER4 0x02
+#define LAYER2 0x01
+#define MAX_RXTS 4
+#define MAX_TXTS 4
+#define N_EXT_TS 1
+#define PSF_PTPVER 2
+#define PSF_EVNT 0x4000
+#define PSF_RX 0x2000
+#define PSF_TX 0x1000
+#define EXT_EVENT 1
+#define EXT_GPIO 1
+#define CAL_EVENT 2
+#define CAL_GPIO 9
+#define CAL_TRIGGER 2
+
+/* phyter seems to miss the mark by 16 ns */
+#define ADJTIME_FIX 16
+
+#if defined(__BIG_ENDIAN)
+#define ENDIAN_FLAG 0
+#elif defined(__LITTLE_ENDIAN)
+#define ENDIAN_FLAG PSF_ENDIAN
+#endif
+
+#define SKB_PTP_TYPE(__skb) (*(unsigned int *)((__skb)->cb))
+
+struct phy_rxts {
+ u16 ns_lo; /* ns[15:0] */
+ u16 ns_hi; /* overflow[1:0], ns[29:16] */
+ u16 sec_lo; /* sec[15:0] */
+ u16 sec_hi; /* sec[31:16] */
+ u16 seqid; /* sequenceId[15:0] */
+ u16 msgtype; /* messageType[3:0], hash[11:0] */
+};
+
+struct phy_txts {
+ u16 ns_lo; /* ns[15:0] */
+ u16 ns_hi; /* overflow[1:0], ns[29:16] */
+ u16 sec_lo; /* sec[15:0] */
+ u16 sec_hi; /* sec[31:16] */
+};
+
+struct rxts {
+ struct list_head list;
+ unsigned long tmo;
+ u64 ns;
+ u16 seqid;
+ u8 msgtype;
+ u16 hash;
+};
+
+struct dp83640_clock;
+
+struct dp83640_private {
+ struct list_head list;
+ struct dp83640_clock *clock;
+ struct phy_device *phydev;
+ struct work_struct ts_work;
+ int hwts_tx_en;
+ int hwts_rx_en;
+ int layer;
+ int version;
+ /* remember state of cfg0 during calibration */
+ int cfg0;
+ /* remember the last event time stamp */
+ struct phy_txts edata;
+ /* list of rx timestamps */
+ struct list_head rxts;
+ struct list_head rxpool;
+ struct rxts rx_pool_data[MAX_RXTS];
+ /* protects above three fields from concurrent access */
+ spinlock_t rx_lock;
+ /* queues of incoming and outgoing packets */
+ struct sk_buff_head rx_queue;
+ struct sk_buff_head tx_queue;
+};
+
+struct dp83640_clock {
+ /* keeps the instance in the 'phyter_clocks' list */
+ struct list_head list;
+ /* we create one clock instance per MII bus */
+ struct mii_bus *bus;
+ /* protects extended registers from concurrent access */
+ struct mutex extreg_lock;
+ /* remembers which page was last selected */
+ int page;
+ /* our advertised capabilities */
+ struct ptp_clock_info caps;
+ /* protects the three fields below from concurrent access */
+ struct mutex clock_lock;
+ /* the one phyter from which we shall read */
+ struct dp83640_private *chosen;
+ /* list of the other attached phyters, not chosen */
+ struct list_head phylist;
+ /* reference to our PTP hardware clock */
+ struct ptp_clock *ptp_clock;
+};
+
+/* globals */
+
+static int chosen_phy = -1;
+static ushort cal_gpio = 4;
+
+module_param(chosen_phy, int, 0444);
+module_param(cal_gpio, ushort, 0444);
+
+MODULE_PARM_DESC(chosen_phy, \
+ "The address of the PHY to use for the ancillary clock features");
+MODULE_PARM_DESC(cal_gpio, \
+ "Which GPIO line to use for synchronizing multiple PHYs");
+
+/* a list of clocks and a mutex to protect it */
+static LIST_HEAD(phyter_clocks);
+static DEFINE_MUTEX(phyter_clocks_lock);
+
+static void rx_timestamp_work(struct work_struct *work);
+
+/* extended register access functions */
+
+#define BROADCAST_ADDR 31
+
+static inline int broadcast_write(struct mii_bus *bus, u32 regnum, u16 val)
+{
+ return mdiobus_write(bus, BROADCAST_ADDR, regnum, val);
+}
+
+/* Caller must hold extreg_lock. */
+static int ext_read(struct phy_device *phydev, int page, u32 regnum)
+{
+ struct dp83640_private *dp83640 = phydev->priv;
+ int val;
+
+ if (dp83640->clock->page != page) {
+ broadcast_write(phydev->bus, PAGESEL, page);
+ dp83640->clock->page = page;
+ }
+ val = phy_read(phydev, regnum);
+
+ return val;
+}
+
+/* Caller must hold extreg_lock. */
+static void ext_write(int broadcast, struct phy_device *phydev,
+ int page, u32 regnum, u16 val)
+{
+ struct dp83640_private *dp83640 = phydev->priv;
+
+ if (dp83640->clock->page != page) {
+ broadcast_write(phydev->bus, PAGESEL, page);
+ dp83640->clock->page = page;
+ }
+ if (broadcast)
+ broadcast_write(phydev->bus, regnum, val);
+ else
+ phy_write(phydev, regnum, val);
+}
+
+/* Caller must hold extreg_lock. */
+static int tdr_write(int bc, struct phy_device *dev,
+ const struct timespec *ts, u16 cmd)
+{
+ ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec & 0xffff);/* ns[15:0] */
+ ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_nsec >> 16); /* ns[31:16] */
+ ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec & 0xffff); /* sec[15:0] */
+ ext_write(bc, dev, PAGE4, PTP_TDR, ts->tv_sec >> 16); /* sec[31:16]*/
+
+ ext_write(bc, dev, PAGE4, PTP_CTL, cmd);
+
+ return 0;
+}
+
+/* convert phy timestamps into driver timestamps */
+
+static void phy2rxts(struct phy_rxts *p, struct rxts *rxts)
+{
+ u32 sec;
+
+ sec = p->sec_lo;
+ sec |= p->sec_hi << 16;
+
+ rxts->ns = p->ns_lo;
+ rxts->ns |= (p->ns_hi & 0x3fff) << 16;
+ rxts->ns += ((u64)sec) * 1000000000ULL;
+ rxts->seqid = p->seqid;
+ rxts->msgtype = (p->msgtype >> 12) & 0xf;
+ rxts->hash = p->msgtype & 0x0fff;
+ rxts->tmo = jiffies + HZ;
+}
+
+static u64 phy2txts(struct phy_txts *p)
+{
+ u64 ns;
+ u32 sec;
+
+ sec = p->sec_lo;
+ sec |= p->sec_hi << 16;
+
+ ns = p->ns_lo;
+ ns |= (p->ns_hi & 0x3fff) << 16;
+ ns += ((u64)sec) * 1000000000ULL;
+
+ return ns;
+}
+
+/* ptp clock methods */
+
+static int ptp_dp83640_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
+{
+ struct dp83640_clock *clock =
+ container_of(ptp, struct dp83640_clock, caps);
+ struct phy_device *phydev = clock->chosen->phydev;
+ u64 rate;
+ int neg_adj = 0;
+ u16 hi, lo;
+
+ if (ppb < 0) {
+ neg_adj = 1;
+ ppb = -ppb;
+ }
+ rate = ppb;
+ rate <<= 26;
+ rate = div_u64(rate, 1953125);
+
+ hi = (rate >> 16) & PTP_RATE_HI_MASK;
+ if (neg_adj)
+ hi |= PTP_RATE_DIR;
+
+ lo = rate & 0xffff;
+
+ mutex_lock(&clock->extreg_lock);
+
+ ext_write(1, phydev, PAGE4, PTP_RATEH, hi);
+ ext_write(1, phydev, PAGE4, PTP_RATEL, lo);
+
+ mutex_unlock(&clock->extreg_lock);
+
+ return 0;
+}
+
+static int ptp_dp83640_adjtime(struct ptp_clock_info *ptp, s64 delta)
+{
+ struct dp83640_clock *clock =
+ container_of(ptp, struct dp83640_clock, caps);
+ struct phy_device *phydev = clock->chosen->phydev;
+ struct timespec ts;
+ int err;
+
+ delta += ADJTIME_FIX;
+
+ ts = ns_to_timespec(delta);
+
+ mutex_lock(&clock->extreg_lock);
+
+ err = tdr_write(1, phydev, &ts, PTP_STEP_CLK);
+
+ mutex_unlock(&clock->extreg_lock);
+
+ return err;
+}
+
+static int ptp_dp83640_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
+{
+ struct dp83640_clock *clock =
+ container_of(ptp, struct dp83640_clock, caps);
+ struct phy_device *phydev = clock->chosen->phydev;
+ unsigned int val[4];
+
+ mutex_lock(&clock->extreg_lock);
+
+ ext_write(0, phydev, PAGE4, PTP_CTL, PTP_RD_CLK);
+
+ val[0] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[15:0] */
+ val[1] = ext_read(phydev, PAGE4, PTP_TDR); /* ns[31:16] */
+ val[2] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[15:0] */
+ val[3] = ext_read(phydev, PAGE4, PTP_TDR); /* sec[31:16] */
+
+ mutex_unlock(&clock->extreg_lock);
+
+ ts->tv_nsec = val[0] | (val[1] << 16);
+ ts->tv_sec = val[2] | (val[3] << 16);
+
+ return 0;
+}
+
+static int ptp_dp83640_settime(struct ptp_clock_info *ptp,
+ const struct timespec *ts)
+{
+ struct dp83640_clock *clock =
+ container_of(ptp, struct dp83640_clock, caps);
+ struct phy_device *phydev = clock->chosen->phydev;
+ int err;
+
+ mutex_lock(&clock->extreg_lock);
+
+ err = tdr_write(1, phydev, ts, PTP_LOAD_CLK);
+
+ mutex_unlock(&clock->extreg_lock);
+
+ return err;
+}
+
+static int ptp_dp83640_enable(struct ptp_clock_info *ptp,
+ struct ptp_clock_request *rq, int on)
+{
+ struct dp83640_clock *clock =
+ container_of(ptp, struct dp83640_clock, caps);
+ struct phy_device *phydev = clock->chosen->phydev;
+ u16 evnt;
+
+ switch (rq->type) {
+ case PTP_CLK_REQ_EXTTS:
+ if (rq->extts.index != 0)
+ return -EINVAL;
+ evnt = EVNT_WR | (EXT_EVENT & EVNT_SEL_MASK) << EVNT_SEL_SHIFT;
+ if (on) {
+ evnt |= (EXT_GPIO & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT;
+ evnt |= EVNT_RISE;
+ }
+ ext_write(0, phydev, PAGE5, PTP_EVNT, evnt);
+ return 0;
+ default:
+ break;
+ }
+
+ return -EOPNOTSUPP;
+}
+
+static u8 status_frame_dst[6] = { 0x01, 0x1B, 0x19, 0x00, 0x00, 0x00 };
+static u8 status_frame_src[6] = { 0x08, 0x00, 0x17, 0x0B, 0x6B, 0x0F };
+
+static void enable_status_frames(struct phy_device *phydev, bool on)
+{
+ u16 cfg0 = 0, ver;
+
+ if (on)
+ cfg0 = PSF_EVNT_EN | PSF_RXTS_EN | PSF_TXTS_EN | ENDIAN_FLAG;
+
+ ver = (PSF_PTPVER & VERSIONPTP_MASK) << VERSIONPTP_SHIFT;
+
+ ext_write(0, phydev, PAGE5, PSF_CFG0, cfg0);
+ ext_write(0, phydev, PAGE6, PSF_CFG1, ver);
+
+ if (!phydev->attached_dev) {
+ pr_warning("dp83640: expected to find an attached netdevice\n");
+ return;
+ }
+
+ if (on) {
+ if (dev_mc_add(phydev->attached_dev, status_frame_dst))
+ pr_warning("dp83640: failed to add mc address\n");
+ } else {
+ if (dev_mc_del(phydev->attached_dev, status_frame_dst))
+ pr_warning("dp83640: failed to delete mc address\n");
+ }
+}
+
+static bool is_status_frame(struct sk_buff *skb, int type)
+{
+ struct ethhdr *h = eth_hdr(skb);
+
+ if (PTP_CLASS_V2_L2 == type &&
+ !memcmp(h->h_source, status_frame_src, sizeof(status_frame_src)))
+ return true;
+ else
+ return false;
+}
+
+static int expired(struct rxts *rxts)
+{
+ return time_after(jiffies, rxts->tmo);
+}
+
+/* Caller must hold rx_lock. */
+static void prune_rx_ts(struct dp83640_private *dp83640)
+{
+ struct list_head *this, *next;
+ struct rxts *rxts;
+
+ list_for_each_safe(this, next, &dp83640->rxts) {
+ rxts = list_entry(this, struct rxts, list);
+ if (expired(rxts)) {
+ list_del_init(&rxts->list);
+ list_add(&rxts->list, &dp83640->rxpool);
+ }
+ }
+}
+
+/* synchronize the phyters so they act as one clock */
+
+static void enable_broadcast(struct phy_device *phydev, int init_page, int on)
+{
+ int val;
+ phy_write(phydev, PAGESEL, 0);
+ val = phy_read(phydev, PHYCR2);
+ if (on)
+ val |= BC_WRITE;
+ else
+ val &= ~BC_WRITE;
+ phy_write(phydev, PHYCR2, val);
+ phy_write(phydev, PAGESEL, init_page);
+}
+
+static void recalibrate(struct dp83640_clock *clock)
+{
+ s64 now, diff;
+ struct phy_txts event_ts;
+ struct timespec ts;
+ struct list_head *this;
+ struct dp83640_private *tmp;
+ struct phy_device *master = clock->chosen->phydev;
+ u16 cfg0, evnt, ptp_trig, trigger, val;
+
+ trigger = CAL_TRIGGER;
+
+ mutex_lock(&clock->extreg_lock);
+
+ /*
+ * enable broadcast, disable status frames, enable ptp clock
+ */
+ list_for_each(this, &clock->phylist) {
+ tmp = list_entry(this, struct dp83640_private, list);
+ enable_broadcast(tmp->phydev, clock->page, 1);
+ tmp->cfg0 = ext_read(tmp->phydev, PAGE5, PSF_CFG0);
+ ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, 0);
+ ext_write(0, tmp->phydev, PAGE4, PTP_CTL, PTP_ENABLE);
+ }
+ enable_broadcast(master, clock->page, 1);
+ cfg0 = ext_read(master, PAGE5, PSF_CFG0);
+ ext_write(0, master, PAGE5, PSF_CFG0, 0);
+ ext_write(0, master, PAGE4, PTP_CTL, PTP_ENABLE);
+
+ /*
+ * enable an event timestamp
+ */
+ evnt = EVNT_WR | EVNT_RISE | EVNT_SINGLE;
+ evnt |= (CAL_EVENT & EVNT_SEL_MASK) << EVNT_SEL_SHIFT;
+ evnt |= (cal_gpio & EVNT_GPIO_MASK) << EVNT_GPIO_SHIFT;
+
+ list_for_each(this, &clock->phylist) {
+ tmp = list_entry(this, struct dp83640_private, list);
+ ext_write(0, tmp->phydev, PAGE5, PTP_EVNT, evnt);
+ }
+ ext_write(0, master, PAGE5, PTP_EVNT, evnt);
+
+ /*
+ * configure a trigger
+ */
+ ptp_trig = TRIG_WR | TRIG_IF_LATE | TRIG_PULSE;
+ ptp_trig |= (trigger & TRIG_CSEL_MASK) << TRIG_CSEL_SHIFT;
+ ptp_trig |= (cal_gpio & TRIG_GPIO_MASK) << TRIG_GPIO_SHIFT;
+ ext_write(0, master, PAGE5, PTP_TRIG, ptp_trig);
+
+ /* load trigger */
+ val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
+ val |= TRIG_LOAD;
+ ext_write(0, master, PAGE4, PTP_CTL, val);
+
+ /* enable trigger */
+ val &= ~TRIG_LOAD;
+ val |= TRIG_EN;
+ ext_write(0, master, PAGE4, PTP_CTL, val);
+
+ /* disable trigger */
+ val = (trigger & TRIG_SEL_MASK) << TRIG_SEL_SHIFT;
+ val |= TRIG_DIS;
+ ext_write(0, master, PAGE4, PTP_CTL, val);
+
+ /*
+ * read out and correct offsets
+ */
+ val = ext_read(master, PAGE4, PTP_STS);
+ pr_info("master PTP_STS 0x%04hx", val);
+ val = ext_read(master, PAGE4, PTP_ESTS);
+ pr_info("master PTP_ESTS 0x%04hx", val);
+ event_ts.ns_lo = ext_read(master, PAGE4, PTP_EDATA);
+ event_ts.ns_hi = ext_read(master, PAGE4, PTP_EDATA);
+ event_ts.sec_lo = ext_read(master, PAGE4, PTP_EDATA);
+ event_ts.sec_hi = ext_read(master, PAGE4, PTP_EDATA);
+ now = phy2txts(&event_ts);
+
+ list_for_each(this, &clock->phylist) {
+ tmp = list_entry(this, struct dp83640_private, list);
+ val = ext_read(tmp->phydev, PAGE4, PTP_STS);
+ pr_info("slave PTP_STS 0x%04hx", val);
+ val = ext_read(tmp->phydev, PAGE4, PTP_ESTS);
+ pr_info("slave PTP_ESTS 0x%04hx", val);
+ event_ts.ns_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
+ event_ts.ns_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
+ event_ts.sec_lo = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
+ event_ts.sec_hi = ext_read(tmp->phydev, PAGE4, PTP_EDATA);
+ diff = now - (s64) phy2txts(&event_ts);
+ pr_info("slave offset %lld nanoseconds\n", diff);
+ diff += ADJTIME_FIX;
+ ts = ns_to_timespec(diff);
+ tdr_write(0, tmp->phydev, &ts, PTP_STEP_CLK);
+ }
+
+ /*
+ * restore status frames
+ */
+ list_for_each(this, &clock->phylist) {
+ tmp = list_entry(this, struct dp83640_private, list);
+ ext_write(0, tmp->phydev, PAGE5, PSF_CFG0, tmp->cfg0);
+ }
+ ext_write(0, master, PAGE5, PSF_CFG0, cfg0);
+
+ mutex_unlock(&clock->extreg_lock);
+}
+
+/* time stamping methods */
+
+static void decode_evnt(struct dp83640_private *dp83640,
+ struct phy_txts *phy_txts, u16 ests)
+{
+ struct ptp_clock_event event;
+ int words = (ests >> EVNT_TS_LEN_SHIFT) & EVNT_TS_LEN_MASK;
+
+ switch (words) { /* fall through in every case */
+ case 3:
+ dp83640->edata.sec_hi = phy_txts->sec_hi;
+ case 2:
+ dp83640->edata.sec_lo = phy_txts->sec_lo;
+ case 1:
+ dp83640->edata.ns_hi = phy_txts->ns_hi;
+ case 0:
+ dp83640->edata.ns_lo = phy_txts->ns_lo;
+ }
+
+ event.type = PTP_CLOCK_EXTTS;
+ event.index = 0;
+ event.timestamp = phy2txts(&dp83640->edata);
+
+ ptp_clock_event(dp83640->clock->ptp_clock, &event);
+}
+
+static void decode_rxts(struct dp83640_private *dp83640,
+ struct phy_rxts *phy_rxts)
+{
+ struct rxts *rxts;
+ unsigned long flags;
+
+ spin_lock_irqsave(&dp83640->rx_lock, flags);
+
+ prune_rx_ts(dp83640);
+
+ if (list_empty(&dp83640->rxpool)) {
+ pr_warning("dp83640: rx timestamp pool is empty\n");
+ goto out;
+ }
+ rxts = list_first_entry(&dp83640->rxpool, struct rxts, list);
+ list_del_init(&rxts->list);
+ phy2rxts(phy_rxts, rxts);
+ list_add_tail(&rxts->list, &dp83640->rxts);
+out:
+ spin_unlock_irqrestore(&dp83640->rx_lock, flags);
+}
+
+static void decode_txts(struct dp83640_private *dp83640,
+ struct phy_txts *phy_txts)
+{
+ struct skb_shared_hwtstamps shhwtstamps;
+ struct sk_buff *skb;
+ u64 ns;
+
+ /* We must already have the skb that triggered this. */
+
+ skb = skb_dequeue(&dp83640->tx_queue);
+
+ if (!skb) {
+ pr_warning("dp83640: have timestamp but tx_queue empty\n");
+ return;
+ }
+ ns = phy2txts(phy_txts);
+ memset(&shhwtstamps, 0, sizeof(shhwtstamps));
+ shhwtstamps.hwtstamp = ns_to_ktime(ns);
+ skb_complete_tx_timestamp(skb, &shhwtstamps);
+}
+
+static void decode_status_frame(struct dp83640_private *dp83640,
+ struct sk_buff *skb)
+{
+ struct phy_rxts *phy_rxts;
+ struct phy_txts *phy_txts;
+ u8 *ptr;
+ int len, size;
+ u16 ests, type;
+
+ ptr = skb->data + 2;
+
+ for (len = skb_headlen(skb) - 2; len > sizeof(type); len -= size) {
+
+ type = *(u16 *)ptr;
+ ests = type & 0x0fff;
+ type = type & 0xf000;
+ len -= sizeof(type);
+ ptr += sizeof(type);
+
+ if (PSF_RX == type && len >= sizeof(*phy_rxts)) {
+
+ phy_rxts = (struct phy_rxts *) ptr;
+ decode_rxts(dp83640, phy_rxts);
+ size = sizeof(*phy_rxts);
+
+ } else if (PSF_TX == type && len >= sizeof(*phy_txts)) {
+
+ phy_txts = (struct phy_txts *) ptr;
+ decode_txts(dp83640, phy_txts);
+ size = sizeof(*phy_txts);
+
+ } else if (PSF_EVNT == type && len >= sizeof(*phy_txts)) {
+
+ phy_txts = (struct phy_txts *) ptr;
+ decode_evnt(dp83640, phy_txts, ests);
+ size = sizeof(*phy_txts);
+
+ } else {
+ size = 0;
+ break;
+ }
+ ptr += size;
+ }
+}
+
+static int match(struct sk_buff *skb, unsigned int type, struct rxts *rxts)
+{
+ u16 *seqid;
+ unsigned int offset;
+ u8 *msgtype, *data = skb_mac_header(skb);
+
+ /* check sequenceID, messageType, 12 bit hash of offset 20-29 */
+
+ switch (type) {
+ case PTP_CLASS_V1_IPV4:
+ case PTP_CLASS_V2_IPV4:
+ offset = ETH_HLEN + IPV4_HLEN(data) + UDP_HLEN;
+ break;
+ case PTP_CLASS_V1_IPV6:
+ case PTP_CLASS_V2_IPV6:
+ offset = OFF_PTP6;
+ break;
+ case PTP_CLASS_V2_L2:
+ offset = ETH_HLEN;
+ break;
+ case PTP_CLASS_V2_VLAN:
+ offset = ETH_HLEN + VLAN_HLEN;
+ break;
+ default:
+ return 0;
+ }
+
+ if (skb->len + ETH_HLEN < offset + OFF_PTP_SEQUENCE_ID + sizeof(*seqid))
+ return 0;
+
+ if (unlikely(type & PTP_CLASS_V1))
+ msgtype = data + offset + OFF_PTP_CONTROL;
+ else
+ msgtype = data + offset;
+
+ seqid = (u16 *)(data + offset + OFF_PTP_SEQUENCE_ID);
+
+ return (rxts->msgtype == (*msgtype & 0xf) &&
+ rxts->seqid == ntohs(*seqid));
+}
+
+static void dp83640_free_clocks(void)
+{
+ struct dp83640_clock *clock;
+ struct list_head *this, *next;
+
+ mutex_lock(&phyter_clocks_lock);
+
+ list_for_each_safe(this, next, &phyter_clocks) {
+ clock = list_entry(this, struct dp83640_clock, list);
+ if (!list_empty(&clock->phylist)) {
+ pr_warning("phy list non-empty while unloading");
+ BUG();
+ }
+ list_del(&clock->list);
+ mutex_destroy(&clock->extreg_lock);
+ mutex_destroy(&clock->clock_lock);
+ put_device(&clock->bus->dev);
+ kfree(clock);
+ }
+
+ mutex_unlock(&phyter_clocks_lock);
+}
+
+static void dp83640_clock_init(struct dp83640_clock *clock, struct mii_bus *bus)
+{
+ INIT_LIST_HEAD(&clock->list);
+ clock->bus = bus;
+ mutex_init(&clock->extreg_lock);
+ mutex_init(&clock->clock_lock);
+ INIT_LIST_HEAD(&clock->phylist);
+ clock->caps.owner = THIS_MODULE;
+ sprintf(clock->caps.name, "dp83640 timer");
+ clock->caps.max_adj = 1953124;
+ clock->caps.n_alarm = 0;
+ clock->caps.n_ext_ts = N_EXT_TS;
+ clock->caps.n_per_out = 0;
+ clock->caps.pps = 0;
+ clock->caps.adjfreq = ptp_dp83640_adjfreq;
+ clock->caps.adjtime = ptp_dp83640_adjtime;
+ clock->caps.gettime = ptp_dp83640_gettime;
+ clock->caps.settime = ptp_dp83640_settime;
+ clock->caps.enable = ptp_dp83640_enable;
+ /*
+ * Get a reference to this bus instance.
+ */
+ get_device(&bus->dev);
+}
+
+static int choose_this_phy(struct dp83640_clock *clock,
+ struct phy_device *phydev)
+{
+ if (chosen_phy == -1 && !clock->chosen)
+ return 1;
+
+ if (chosen_phy == phydev->addr)
+ return 1;
+
+ return 0;
+}
+
+static struct dp83640_clock *dp83640_clock_get(struct dp83640_clock *clock)
+{
+ if (clock)
+ mutex_lock(&clock->clock_lock);
+ return clock;
+}
+
+/*
+ * Look up and lock a clock by bus instance.
+ * If there is no clock for this bus, then create it first.
+ */
+static struct dp83640_clock *dp83640_clock_get_bus(struct mii_bus *bus)
+{
+ struct dp83640_clock *clock = NULL, *tmp;
+ struct list_head *this;
+
+ mutex_lock(&phyter_clocks_lock);
+
+ list_for_each(this, &phyter_clocks) {
+ tmp = list_entry(this, struct dp83640_clock, list);
+ if (tmp->bus == bus) {
+ clock = tmp;
+ break;
+ }
+ }
+ if (clock)
+ goto out;
+
+ clock = kzalloc(sizeof(struct dp83640_clock), GFP_KERNEL);
+ if (!clock)
+ goto out;
+
+ dp83640_clock_init(clock, bus);
+ list_add_tail(&phyter_clocks, &clock->list);
+out:
+ mutex_unlock(&phyter_clocks_lock);
+
+ return dp83640_clock_get(clock);
+}
+
+static void dp83640_clock_put(struct dp83640_clock *clock)
+{
+ mutex_unlock(&clock->clock_lock);
+}
+
+static int dp83640_probe(struct phy_device *phydev)
+{
+ struct dp83640_clock *clock;
+ struct dp83640_private *dp83640;
+ int err = -ENOMEM, i;
+
+ if (phydev->addr == BROADCAST_ADDR)
+ return 0;
+
+ clock = dp83640_clock_get_bus(phydev->bus);
+ if (!clock)
+ goto no_clock;
+
+ dp83640 = kzalloc(sizeof(struct dp83640_private), GFP_KERNEL);
+ if (!dp83640)
+ goto no_memory;
+
+ dp83640->phydev = phydev;
+ INIT_WORK(&dp83640->ts_work, rx_timestamp_work);
+
+ INIT_LIST_HEAD(&dp83640->rxts);
+ INIT_LIST_HEAD(&dp83640->rxpool);
+ for (i = 0; i < MAX_RXTS; i++)
+ list_add(&dp83640->rx_pool_data[i].list, &dp83640->rxpool);
+
+ phydev->priv = dp83640;
+
+ spin_lock_init(&dp83640->rx_lock);
+ skb_queue_head_init(&dp83640->rx_queue);
+ skb_queue_head_init(&dp83640->tx_queue);
+
+ dp83640->clock = clock;
+
+ if (choose_this_phy(clock, phydev)) {
+ clock->chosen = dp83640;
+ clock->ptp_clock = ptp_clock_register(&clock->caps);
+ if (IS_ERR(clock->ptp_clock)) {
+ err = PTR_ERR(clock->ptp_clock);
+ goto no_register;
+ }
+ } else
+ list_add_tail(&dp83640->list, &clock->phylist);
+
+ if (clock->chosen && !list_empty(&clock->phylist))
+ recalibrate(clock);
+ else
+ enable_broadcast(dp83640->phydev, clock->page, 1);
+
+ dp83640_clock_put(clock);
+ return 0;
+
+no_register:
+ clock->chosen = NULL;
+ kfree(dp83640);
+no_memory:
+ dp83640_clock_put(clock);
+no_clock:
+ return err;
+}
+
+static void dp83640_remove(struct phy_device *phydev)
+{
+ struct dp83640_clock *clock;
+ struct list_head *this, *next;
+ struct dp83640_private *tmp, *dp83640 = phydev->priv;
+
+ if (phydev->addr == BROADCAST_ADDR)
+ return;
+
+ enable_status_frames(phydev, false);
+ cancel_work_sync(&dp83640->ts_work);
+
+ clock = dp83640_clock_get(dp83640->clock);
+
+ if (dp83640 == clock->chosen) {
+ ptp_clock_unregister(clock->ptp_clock);
+ clock->chosen = NULL;
+ } else {
+ list_for_each_safe(this, next, &clock->phylist) {
+ tmp = list_entry(this, struct dp83640_private, list);
+ if (tmp == dp83640) {
+ list_del_init(&tmp->list);
+ break;
+ }
+ }
+ }
+
+ dp83640_clock_put(clock);
+ kfree(dp83640);
+}
+
+static int dp83640_hwtstamp(struct phy_device *phydev, struct ifreq *ifr)
+{
+ struct dp83640_private *dp83640 = phydev->priv;
+ struct hwtstamp_config cfg;
+ u16 txcfg0, rxcfg0;
+
+ if (copy_from_user(&cfg, ifr->ifr_data, sizeof(cfg)))
+ return -EFAULT;
+
+ if (cfg.flags) /* reserved for future extensions */
+ return -EINVAL;
+
+ switch (cfg.tx_type) {
+ case HWTSTAMP_TX_OFF:
+ dp83640->hwts_tx_en = 0;
+ break;
+ case HWTSTAMP_TX_ON:
+ dp83640->hwts_tx_en = 1;
+ break;
+ default:
+ return -ERANGE;
+ }
+
+ switch (cfg.rx_filter) {
+ case HWTSTAMP_FILTER_NONE:
+ dp83640->hwts_rx_en = 0;
+ dp83640->layer = 0;
+ dp83640->version = 0;
+ break;
+ case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
+ case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
+ case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
+ dp83640->hwts_rx_en = 1;
+ dp83640->layer = LAYER4;
+ dp83640->version = 1;
+ break;
+ case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
+ case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
+ case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
+ dp83640->hwts_rx_en = 1;
+ dp83640->layer = LAYER4;
+ dp83640->version = 2;
+ break;
+ case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
+ case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
+ case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
+ dp83640->hwts_rx_en = 1;
+ dp83640->layer = LAYER2;
+ dp83640->version = 2;
+ break;
+ case HWTSTAMP_FILTER_PTP_V2_EVENT:
+ case HWTSTAMP_FILTER_PTP_V2_SYNC:
+ case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
+ dp83640->hwts_rx_en = 1;
+ dp83640->layer = LAYER4|LAYER2;
+ dp83640->version = 2;
+ break;
+ default:
+ return -ERANGE;
+ }
+
+ txcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT;
+ rxcfg0 = (dp83640->version & TX_PTP_VER_MASK) << TX_PTP_VER_SHIFT;
+
+ if (dp83640->layer & LAYER2) {
+ txcfg0 |= TX_L2_EN;
+ rxcfg0 |= RX_L2_EN;
+ }
+ if (dp83640->layer & LAYER4) {
+ txcfg0 |= TX_IPV6_EN | TX_IPV4_EN;
+ rxcfg0 |= RX_IPV6_EN | RX_IPV4_EN;
+ }
+
+ if (dp83640->hwts_tx_en)
+ txcfg0 |= TX_TS_EN;
+
+ if (dp83640->hwts_rx_en)
+ rxcfg0 |= RX_TS_EN;
+
+ mutex_lock(&dp83640->clock->extreg_lock);
+
+ if (dp83640->hwts_tx_en || dp83640->hwts_rx_en) {
+ enable_status_frames(phydev, true);
+ ext_write(0, phydev, PAGE4, PTP_CTL, PTP_ENABLE);
+ }
+
+ ext_write(0, phydev, PAGE5, PTP_TXCFG0, txcfg0);
+ ext_write(0, phydev, PAGE5, PTP_RXCFG0, rxcfg0);
+
+ mutex_unlock(&dp83640->clock->extreg_lock);
+
+ return copy_to_user(ifr->ifr_data, &cfg, sizeof(cfg)) ? -EFAULT : 0;
+}
+
+static void rx_timestamp_work(struct work_struct *work)
+{
+ struct dp83640_private *dp83640 =
+ container_of(work, struct dp83640_private, ts_work);
+ struct list_head *this, *next;
+ struct rxts *rxts;
+ struct skb_shared_hwtstamps *shhwtstamps;
+ struct sk_buff *skb;
+ unsigned int type;
+ unsigned long flags;
+
+ /* Deliver each deferred packet, with or without a time stamp. */
+
+ while ((skb = skb_dequeue(&dp83640->rx_queue)) != NULL) {
+ type = SKB_PTP_TYPE(skb);
+ spin_lock_irqsave(&dp83640->rx_lock, flags);
+ list_for_each_safe(this, next, &dp83640->rxts) {
+ rxts = list_entry(this, struct rxts, list);
+ if (match(skb, type, rxts)) {
+ shhwtstamps = skb_hwtstamps(skb);
+ memset(shhwtstamps, 0, sizeof(*shhwtstamps));
+ shhwtstamps->hwtstamp = ns_to_ktime(rxts->ns);
+ list_del_init(&rxts->list);
+ list_add(&rxts->list, &dp83640->rxpool);
+ break;
+ }
+ }
+ spin_unlock_irqrestore(&dp83640->rx_lock, flags);
+ netif_rx(skb);
+ }
+
+ /* Clear out expired time stamps. */
+
+ spin_lock_irqsave(&dp83640->rx_lock, flags);
+ prune_rx_ts(dp83640);
+ spin_unlock_irqrestore(&dp83640->rx_lock, flags);
+}
+
+static bool dp83640_rxtstamp(struct phy_device *phydev,
+ struct sk_buff *skb, int type)
+{
+ struct dp83640_private *dp83640 = phydev->priv;
+
+ if (!dp83640->hwts_rx_en)
+ return false;
+
+ if (is_status_frame(skb, type)) {
+ decode_status_frame(dp83640, skb);
+ /* Let the stack drop this frame. */
+ return false;
+ }
+
+ SKB_PTP_TYPE(skb) = type;
+ skb_queue_tail(&dp83640->rx_queue, skb);
+ schedule_work(&dp83640->ts_work);
+
+ return true;
+}
+
+static void dp83640_txtstamp(struct phy_device *phydev,
+ struct sk_buff *skb, int type)
+{
+ struct dp83640_private *dp83640 = phydev->priv;
+
+ if (!dp83640->hwts_tx_en) {
+ kfree_skb(skb);
+ return;
+ }
+ skb_queue_tail(&dp83640->tx_queue, skb);
+ schedule_work(&dp83640->ts_work);
+}
+
+static struct phy_driver dp83640_driver = {
+ .phy_id = DP83640_PHY_ID,
+ .phy_id_mask = 0xfffffff0,
+ .name = "NatSemi DP83640",
+ .features = PHY_BASIC_FEATURES,
+ .flags = 0,
+ .probe = dp83640_probe,
+ .remove = dp83640_remove,
+ .config_aneg = genphy_config_aneg,
+ .read_status = genphy_read_status,
+ .hwtstamp = dp83640_hwtstamp,
+ .rxtstamp = dp83640_rxtstamp,
+ .txtstamp = dp83640_txtstamp,
+ .driver = {.owner = THIS_MODULE,}
+};
+
+static int __init dp83640_init(void)
+{
+ return phy_driver_register(&dp83640_driver);
+}
+
+static void __exit dp83640_exit(void)
+{
+ dp83640_free_clocks();
+ phy_driver_unregister(&dp83640_driver);
+}
+
+MODULE_DESCRIPTION("National Semiconductor DP83640 PHY driver");
+MODULE_AUTHOR("Richard Cochran <richard.cochran@omicron.at>");
+MODULE_LICENSE("GPL");
+
+module_init(dp83640_init);
+module_exit(dp83640_exit);
+
+static struct mdio_device_id __maybe_unused dp83640_tbl[] = {
+ { DP83640_PHY_ID, 0xfffffff0 },
+ { }
+};
+
+MODULE_DEVICE_TABLE(mdio, dp83640_tbl);
diff --git a/drivers/net/phy/dp83640_reg.h b/drivers/net/phy/dp83640_reg.h
new file mode 100644
index 0000000..e7fe411
--- /dev/null
+++ b/drivers/net/phy/dp83640_reg.h
@@ -0,0 +1,267 @@
+/* dp83640_reg.h
+ * Generated by regen.tcl on Thu Feb 17 10:02:48 AM CET 2011
+ */
+#ifndef HAVE_DP83640_REGISTERS
+#define HAVE_DP83640_REGISTERS
+
+#define PAGE0 0x0000
+#define PHYCR2 0x001c /* PHY Control Register 2 */
+
+#define PAGE4 0x0004
+#define PTP_CTL 0x0014 /* PTP Control Register */
+#define PTP_TDR 0x0015 /* PTP Time Data Register */
+#define PTP_STS 0x0016 /* PTP Status Register */
+#define PTP_TSTS 0x0017 /* PTP Trigger Status Register */
+#define PTP_RATEL 0x0018 /* PTP Rate Low Register */
+#define PTP_RATEH 0x0019 /* PTP Rate High Register */
+#define PTP_RDCKSUM 0x001a /* PTP Read Checksum */
+#define PTP_WRCKSUM 0x001b /* PTP Write Checksum */
+#define PTP_TXTS 0x001c /* PTP Transmit Timestamp Register, in four 16-bit reads */
+#define PTP_RXTS 0x001d /* PTP Receive Timestamp Register, in six? 16-bit reads */
+#define PTP_ESTS 0x001e /* PTP Event Status Register */
+#define PTP_EDATA 0x001f /* PTP Event Data Register */
+
+#define PAGE5 0x0005
+#define PTP_TRIG 0x0014 /* PTP Trigger Configuration Register */
+#define PTP_EVNT 0x0015 /* PTP Event Configuration Register */
+#define PTP_TXCFG0 0x0016 /* PTP Transmit Configuration Register 0 */
+#define PTP_TXCFG1 0x0017 /* PTP Transmit Configuration Register 1 */
+#define PSF_CFG0 0x0018 /* PHY Status Frame Configuration Register 0 */
+#define PTP_RXCFG0 0x0019 /* PTP Receive Configuration Register 0 */
+#define PTP_RXCFG1 0x001a /* PTP Receive Configuration Register 1 */
+#define PTP_RXCFG2 0x001b /* PTP Receive Configuration Register 2 */
+#define PTP_RXCFG3 0x001c /* PTP Receive Configuration Register 3 */
+#define PTP_RXCFG4 0x001d /* PTP Receive Configuration Register 4 */
+#define PTP_TRDL 0x001e /* PTP Temporary Rate Duration Low Register */
+#define PTP_TRDH 0x001f /* PTP Temporary Rate Duration High Register */
+
+#define PAGE6 0x0006
+#define PTP_COC 0x0014 /* PTP Clock Output Control Register */
+#define PSF_CFG1 0x0015 /* PHY Status Frame Configuration Register 1 */
+#define PSF_CFG2 0x0016 /* PHY Status Frame Configuration Register 2 */
+#define PSF_CFG3 0x0017 /* PHY Status Frame Configuration Register 3 */
+#define PSF_CFG4 0x0018 /* PHY Status Frame Configuration Register 4 */
+#define PTP_SFDCFG 0x0019 /* PTP SFD Configuration Register */
+#define PTP_INTCTL 0x001a /* PTP Interrupt Control Register */
+#define PTP_CLKSRC 0x001b /* PTP Clock Source Register */
+#define PTP_ETR 0x001c /* PTP Ethernet Type Register */
+#define PTP_OFF 0x001d /* PTP Offset Register */
+#define PTP_GPIOMON 0x001e /* PTP GPIO Monitor Register */
+#define PTP_RXHASH 0x001f /* PTP Receive Hash Register */
+
+/* Bit definitions for the PHYCR2 register */
+#define BC_WRITE (1<<11) /* Broadcast Write Enable */
+
+/* Bit definitions for the PTP_CTL register */
+#define TRIG_SEL_SHIFT (10) /* PTP Trigger Select */
+#define TRIG_SEL_MASK (0x7)
+#define TRIG_DIS (1<<9) /* Disable PTP Trigger */
+#define TRIG_EN (1<<8) /* Enable PTP Trigger */
+#define TRIG_READ (1<<7) /* Read PTP Trigger */
+#define TRIG_LOAD (1<<6) /* Load PTP Trigger */
+#define PTP_RD_CLK (1<<5) /* Read PTP Clock */
+#define PTP_LOAD_CLK (1<<4) /* Load PTP Clock */
+#define PTP_STEP_CLK (1<<3) /* Step PTP Clock */
+#define PTP_ENABLE (1<<2) /* Enable PTP Clock */
+#define PTP_DISABLE (1<<1) /* Disable PTP Clock */
+#define PTP_RESET (1<<0) /* Reset PTP Clock */
+
+/* Bit definitions for the PTP_STS register */
+#define TXTS_RDY (1<<11) /* Transmit Timestamp Ready */
+#define RXTS_RDY (1<<10) /* Receive Timestamp Ready */
+#define TRIG_DONE (1<<9) /* PTP Trigger Done */
+#define EVENT_RDY (1<<8) /* PTP Event Timestamp Ready */
+#define TXTS_IE (1<<3) /* Transmit Timestamp Interrupt Enable */
+#define RXTS_IE (1<<2) /* Receive Timestamp Interrupt Enable */
+#define TRIG_IE (1<<1) /* Trigger Interrupt Enable */
+#define EVENT_IE (1<<0) /* Event Interrupt Enable */
+
+/* Bit definitions for the PTP_TSTS register */
+#define TRIG7_ERROR (1<<15) /* Trigger 7 Error */
+#define TRIG7_ACTIVE (1<<14) /* Trigger 7 Active */
+#define TRIG6_ERROR (1<<13) /* Trigger 6 Error */
+#define TRIG6_ACTIVE (1<<12) /* Trigger 6 Active */
+#define TRIG5_ERROR (1<<11) /* Trigger 5 Error */
+#define TRIG5_ACTIVE (1<<10) /* Trigger 5 Active */
+#define TRIG4_ERROR (1<<9) /* Trigger 4 Error */
+#define TRIG4_ACTIVE (1<<8) /* Trigger 4 Active */
+#define TRIG3_ERROR (1<<7) /* Trigger 3 Error */
+#define TRIG3_ACTIVE (1<<6) /* Trigger 3 Active */
+#define TRIG2_ERROR (1<<5) /* Trigger 2 Error */
+#define TRIG2_ACTIVE (1<<4) /* Trigger 2 Active */
+#define TRIG1_ERROR (1<<3) /* Trigger 1 Error */
+#define TRIG1_ACTIVE (1<<2) /* Trigger 1 Active */
+#define TRIG0_ERROR (1<<1) /* Trigger 0 Error */
+#define TRIG0_ACTIVE (1<<0) /* Trigger 0 Active */
+
+/* Bit definitions for the PTP_RATEH register */
+#define PTP_RATE_DIR (1<<15) /* PTP Rate Direction */
+#define PTP_TMP_RATE (1<<14) /* PTP Temporary Rate */
+#define PTP_RATE_HI_SHIFT (0) /* PTP Rate High 10-bits */
+#define PTP_RATE_HI_MASK (0x3ff)
+
+/* Bit definitions for the PTP_ESTS register */
+#define EVNTS_MISSED_SHIFT (8) /* Indicates number of events missed */
+#define EVNTS_MISSED_MASK (0x7)
+#define EVNT_TS_LEN_SHIFT (6) /* Indicates length of the Timestamp field in 16-bit words minus 1 */
+#define EVNT_TS_LEN_MASK (0x3)
+#define EVNT_RF (1<<5) /* Indicates whether the event is a rise or falling event */
+#define EVNT_NUM_SHIFT (2) /* Indicates Event Timestamp Unit which detected an event */
+#define EVNT_NUM_MASK (0x7)
+#define MULT_EVNT (1<<1) /* Indicates multiple events were detected at the same time */
+#define EVENT_DET (1<<0) /* PTP Event Detected */
+
+/* Bit definitions for the PTP_EDATA register */
+#define E7_RISE (1<<15) /* Indicates direction of Event 7 */
+#define E7_DET (1<<14) /* Indicates Event 7 detected */
+#define E6_RISE (1<<13) /* Indicates direction of Event 6 */
+#define E6_DET (1<<12) /* Indicates Event 6 detected */
+#define E5_RISE (1<<11) /* Indicates direction of Event 5 */
+#define E5_DET (1<<10) /* Indicates Event 5 detected */
+#define E4_RISE (1<<9) /* Indicates direction of Event 4 */
+#define E4_DET (1<<8) /* Indicates Event 4 detected */
+#define E3_RISE (1<<7) /* Indicates direction of Event 3 */
+#define E3_DET (1<<6) /* Indicates Event 3 detected */
+#define E2_RISE (1<<5) /* Indicates direction of Event 2 */
+#define E2_DET (1<<4) /* Indicates Event 2 detected */
+#define E1_RISE (1<<3) /* Indicates direction of Event 1 */
+#define E1_DET (1<<2) /* Indicates Event 1 detected */
+#define E0_RISE (1<<1) /* Indicates direction of Event 0 */
+#define E0_DET (1<<0) /* Indicates Event 0 detected */
+
+/* Bit definitions for the PTP_TRIG register */
+#define TRIG_PULSE (1<<15) /* generate a Pulse rather than a single edge */
+#define TRIG_PER (1<<14) /* generate a periodic signal */
+#define TRIG_IF_LATE (1<<13) /* trigger immediately if already past */
+#define TRIG_NOTIFY (1<<12) /* Trigger Notification Enable */
+#define TRIG_GPIO_SHIFT (8) /* Trigger GPIO Connection, value 1-12 */
+#define TRIG_GPIO_MASK (0xf)
+#define TRIG_TOGGLE (1<<7) /* Trigger Toggle Mode Enable */
+#define TRIG_CSEL_SHIFT (1) /* Trigger Configuration Select */
+#define TRIG_CSEL_MASK (0x7)
+#define TRIG_WR (1<<0) /* Trigger Configuration Write */
+
+/* Bit definitions for the PTP_EVNT register */
+#define EVNT_RISE (1<<14) /* Event Rise Detect Enable */
+#define EVNT_FALL (1<<13) /* Event Fall Detect Enable */
+#define EVNT_SINGLE (1<<12) /* enable single event capture operation */
+#define EVNT_GPIO_SHIFT (8) /* Event GPIO Connection, value 1-12 */
+#define EVNT_GPIO_MASK (0xf)
+#define EVNT_SEL_SHIFT (1) /* Event Select */
+#define EVNT_SEL_MASK (0x7)
+#define EVNT_WR (1<<0) /* Event Configuration Write */
+
+/* Bit definitions for the PTP_TXCFG0 register */
+#define SYNC_1STEP (1<<15) /* insert timestamp into transmit Sync Messages */
+#define DR_INSERT (1<<13) /* Insert Delay_Req Timestamp in Delay_Resp (dangerous) */
+#define NTP_TS_EN (1<<12) /* Enable Timestamping of NTP Packets */
+#define IGNORE_2STEP (1<<11) /* Ignore Two_Step flag for One-Step operation */
+#define CRC_1STEP (1<<10) /* Disable checking of CRC for One-Step operation */
+#define CHK_1STEP (1<<9) /* Enable UDP Checksum correction for One-Step Operation */
+#define IP1588_EN (1<<8) /* Enable IEEE 1588 defined IP address filter */
+#define TX_L2_EN (1<<7) /* Layer2 Timestamp Enable */
+#define TX_IPV6_EN (1<<6) /* IPv6 Timestamp Enable */
+#define TX_IPV4_EN (1<<5) /* IPv4 Timestamp Enable */
+#define TX_PTP_VER_SHIFT (1) /* Enable Timestamp capture for IEEE 1588 version X */
+#define TX_PTP_VER_MASK (0xf)
+#define TX_TS_EN (1<<0) /* Transmit Timestamp Enable */
+
+/* Bit definitions for the PTP_TXCFG1 register */
+#define BYTE0_MASK_SHIFT (8) /* Bit mask to be used for matching Byte0 of the PTP Message */
+#define BYTE0_MASK_MASK (0xff)
+#define BYTE0_DATA_SHIFT (0) /* Data to be used for matching Byte0 of the PTP Message */
+#define BYTE0_DATA_MASK (0xff)
+
+/* Bit definitions for the PSF_CFG0 register */
+#define MAC_SRC_ADD_SHIFT (11) /* Status Frame Mac Source Address */
+#define MAC_SRC_ADD_MASK (0x3)
+#define MIN_PRE_SHIFT (8) /* Status Frame Minimum Preamble */
+#define MIN_PRE_MASK (0x7)
+#define PSF_ENDIAN (1<<7) /* Status Frame Endian Control */
+#define PSF_IPV4 (1<<6) /* Status Frame IPv4 Enable */
+#define PSF_PCF_RD (1<<5) /* Control Frame Read PHY Status Frame Enable */
+#define PSF_ERR_EN (1<<4) /* Error PHY Status Frame Enable */
+#define PSF_TXTS_EN (1<<3) /* Transmit Timestamp PHY Status Frame Enable */
+#define PSF_RXTS_EN (1<<2) /* Receive Timestamp PHY Status Frame Enable */
+#define PSF_TRIG_EN (1<<1) /* Trigger PHY Status Frame Enable */
+#define PSF_EVNT_EN (1<<0) /* Event PHY Status Frame Enable */
+
+/* Bit definitions for the PTP_RXCFG0 register */
+#define DOMAIN_EN (1<<15) /* Domain Match Enable */
+#define ALT_MAST_DIS (1<<14) /* Alternate Master Timestamp Disable */
+#define USER_IP_SEL (1<<13) /* Selects portion of IP address accessible thru PTP_RXCFG2 */
+#define USER_IP_EN (1<<12) /* Enable User-programmed IP address filter */
+#define RX_SLAVE (1<<11) /* Receive Slave Only */
+#define IP1588_EN_SHIFT (8) /* Enable IEEE 1588 defined IP address filters */
+#define IP1588_EN_MASK (0xf)
+#define RX_L2_EN (1<<7) /* Layer2 Timestamp Enable */
+#define RX_IPV6_EN (1<<6) /* IPv6 Timestamp Enable */
+#define RX_IPV4_EN (1<<5) /* IPv4 Timestamp Enable */
+#define RX_PTP_VER_SHIFT (1) /* Enable Timestamp capture for IEEE 1588 version X */
+#define RX_PTP_VER_MASK (0xf)
+#define RX_TS_EN (1<<0) /* Receive Timestamp Enable */
+
+/* Bit definitions for the PTP_RXCFG1 register */
+#define BYTE0_MASK_SHIFT (8) /* Bit mask to be used for matching Byte0 of the PTP Message */
+#define BYTE0_MASK_MASK (0xff)
+#define BYTE0_DATA_SHIFT (0) /* Data to be used for matching Byte0 of the PTP Message */
+#define BYTE0_DATA_MASK (0xff)
+
+/* Bit definitions for the PTP_RXCFG3 register */
+#define TS_MIN_IFG_SHIFT (12) /* Minimum Inter-frame Gap */
+#define TS_MIN_IFG_MASK (0xf)
+#define ACC_UDP (1<<11) /* Record Timestamp if UDP Checksum Error */
+#define ACC_CRC (1<<10) /* Record Timestamp if CRC Error */
+#define TS_APPEND (1<<9) /* Append Timestamp for L2 */
+#define TS_INSERT (1<<8) /* Enable Timestamp Insertion */
+#define PTP_DOMAIN_SHIFT (0) /* PTP Message domainNumber field */
+#define PTP_DOMAIN_MASK (0xff)
+
+/* Bit definitions for the PTP_RXCFG4 register */
+#define IPV4_UDP_MOD (1<<15) /* Enable IPV4 UDP Modification */
+#define TS_SEC_EN (1<<14) /* Enable Timestamp Seconds */
+#define TS_SEC_LEN_SHIFT (12) /* Inserted Timestamp Seconds Length */
+#define TS_SEC_LEN_MASK (0x3)
+#define RXTS_NS_OFF_SHIFT (6) /* Receive Timestamp Nanoseconds offset */
+#define RXTS_NS_OFF_MASK (0x3f)
+#define RXTS_SEC_OFF_SHIFT (0) /* Receive Timestamp Seconds offset */
+#define RXTS_SEC_OFF_MASK (0x3f)
+
+/* Bit definitions for the PTP_COC register */
+#define PTP_CLKOUT_EN (1<<15) /* PTP Clock Output Enable */
+#define PTP_CLKOUT_SEL (1<<14) /* PTP Clock Output Source Select */
+#define PTP_CLKOUT_SPEEDSEL (1<<13) /* PTP Clock Output I/O Speed Select */
+#define PTP_CLKDIV_SHIFT (0) /* PTP Clock Divide-by Value */
+#define PTP_CLKDIV_MASK (0xff)
+
+/* Bit definitions for the PSF_CFG1 register */
+#define PTPRESERVED_SHIFT (12) /* PTP v2 reserved field */
+#define PTPRESERVED_MASK (0xf)
+#define VERSIONPTP_SHIFT (8) /* PTP v2 versionPTP field */
+#define VERSIONPTP_MASK (0xf)
+#define TRANSPORT_SPECIFIC_SHIFT (4) /* PTP v2 Header transportSpecific field */
+#define TRANSPORT_SPECIFIC_MASK (0xf)
+#define MESSAGETYPE_SHIFT (0) /* PTP v2 messageType field */
+#define MESSAGETYPE_MASK (0xf)
+
+/* Bit definitions for the PTP_SFDCFG register */
+#define TX_SFD_GPIO_SHIFT (4) /* TX SFD GPIO Select, value 1-12 */
+#define TX_SFD_GPIO_MASK (0xf)
+#define RX_SFD_GPIO_SHIFT (0) /* RX SFD GPIO Select, value 1-12 */
+#define RX_SFD_GPIO_MASK (0xf)
+
+/* Bit definitions for the PTP_INTCTL register */
+#define PTP_INT_GPIO_SHIFT (0) /* PTP Interrupt GPIO Select */
+#define PTP_INT_GPIO_MASK (0xf)
+
+/* Bit definitions for the PTP_CLKSRC register */
+#define CLK_SRC_SHIFT (14) /* PTP Clock Source Select */
+#define CLK_SRC_MASK (0x3)
+#define CLK_SRC_PER_SHIFT (0) /* PTP Clock Source Period */
+#define CLK_SRC_PER_MASK (0x7f)
+
+/* Bit definitions for the PTP_OFF register */
+#define PTP_OFFSET_SHIFT (0) /* PTP Message offset from preceding header */
+#define PTP_OFFSET_MASK (0xff)
+
+#endif
diff --git a/drivers/net/ppp_async.c b/drivers/net/ppp_async.c
index a1b82c9..53872d7 100644
--- a/drivers/net/ppp_async.c
+++ b/drivers/net/ppp_async.c
@@ -340,7 +340,7 @@
}
/* May sleep, don't call from interrupt level or with interrupts disabled */
-static void
+static unsigned int
ppp_asynctty_receive(struct tty_struct *tty, const unsigned char *buf,
char *cflags, int count)
{
@@ -348,7 +348,7 @@
unsigned long flags;
if (!ap)
- return;
+ return -ENODEV;
spin_lock_irqsave(&ap->recv_lock, flags);
ppp_async_input(ap, buf, cflags, count);
spin_unlock_irqrestore(&ap->recv_lock, flags);
@@ -356,6 +356,8 @@
tasklet_schedule(&ap->tsk);
ap_put(ap);
tty_unthrottle(tty);
+
+ return count;
}
static void
diff --git a/drivers/net/ppp_synctty.c b/drivers/net/ppp_synctty.c
index 2573f52..0815790 100644
--- a/drivers/net/ppp_synctty.c
+++ b/drivers/net/ppp_synctty.c
@@ -381,7 +381,7 @@
}
/* May sleep, don't call from interrupt level or with interrupts disabled */
-static void
+static unsigned int
ppp_sync_receive(struct tty_struct *tty, const unsigned char *buf,
char *cflags, int count)
{
@@ -389,7 +389,7 @@
unsigned long flags;
if (!ap)
- return;
+ return -ENODEV;
spin_lock_irqsave(&ap->recv_lock, flags);
ppp_sync_input(ap, buf, cflags, count);
spin_unlock_irqrestore(&ap->recv_lock, flags);
@@ -397,6 +397,8 @@
tasklet_schedule(&ap->tsk);
sp_put(ap);
tty_unthrottle(tty);
+
+ return count;
}
static void
diff --git a/drivers/net/slip.c b/drivers/net/slip.c
index 8ec1a9a..584809c 100644
--- a/drivers/net/slip.c
+++ b/drivers/net/slip.c
@@ -670,16 +670,17 @@
* in parallel
*/
-static void slip_receive_buf(struct tty_struct *tty, const unsigned char *cp,
- char *fp, int count)
+static unsigned int slip_receive_buf(struct tty_struct *tty,
+ const unsigned char *cp, char *fp, int count)
{
struct slip *sl = tty->disc_data;
+ int bytes = count;
if (!sl || sl->magic != SLIP_MAGIC || !netif_running(sl->dev))
- return;
+ return -ENODEV;
/* Read the characters out of the buffer */
- while (count--) {
+ while (bytes--) {
if (fp && *fp++) {
if (!test_and_set_bit(SLF_ERROR, &sl->flags))
sl->dev->stats.rx_errors++;
@@ -693,6 +694,8 @@
#endif
slip_unesc(sl, *cp++);
}
+
+ return count;
}
/************************************
diff --git a/drivers/net/tile/tilepro.c b/drivers/net/tile/tilepro.c
index 1e980fd..1e2af96 100644
--- a/drivers/net/tile/tilepro.c
+++ b/drivers/net/tile/tilepro.c
@@ -1658,11 +1658,9 @@
while (tile_net_lepp_free_comps(dev, true))
/* loop */;
- /* Wipe the EPP queue. */
+ /* Wipe the EPP queue, and wait till the stores hit the EPP. */
memset(priv->eq, 0, sizeof(lepp_queue_t));
-
- /* Evict the EPP queue. */
- finv_buffer(priv->eq, EQ_SIZE);
+ mb();
return 0;
}
@@ -2398,7 +2396,7 @@
struct net_device *dev = tile_net_devs[i];
struct tile_net_priv *priv = netdev_priv(dev);
unregister_netdev(dev);
- finv_buffer(priv->eq, EQ_SIZE);
+ finv_buffer_remote(priv->eq, EQ_SIZE, 0);
__free_pages(priv->eq_pages, EQ_ORDER);
free_netdev(dev);
}
diff --git a/drivers/net/wan/x25_asy.c b/drivers/net/wan/x25_asy.c
index 24297b2..40398bf 100644
--- a/drivers/net/wan/x25_asy.c
+++ b/drivers/net/wan/x25_asy.c
@@ -517,17 +517,18 @@
* and sent on to some IP layer for further processing.
*/
-static void x25_asy_receive_buf(struct tty_struct *tty,
+static unsigned int x25_asy_receive_buf(struct tty_struct *tty,
const unsigned char *cp, char *fp, int count)
{
struct x25_asy *sl = tty->disc_data;
+ int bytes = count;
if (!sl || sl->magic != X25_ASY_MAGIC || !netif_running(sl->dev))
return;
/* Read the characters out of the buffer */
- while (count--) {
+ while (bytes--) {
if (fp && *fp++) {
if (!test_and_set_bit(SLF_ERROR, &sl->flags))
sl->dev->stats.rx_errors++;
@@ -536,6 +537,8 @@
}
x25_asy_unesc(sl, *cp++);
}
+
+ return count;
}
/*
diff --git a/drivers/net/wireless/airo_cs.c b/drivers/net/wireless/airo_cs.c
index df2484d..c983c10 100644
--- a/drivers/net/wireless/airo_cs.c
+++ b/drivers/net/wireless/airo_cs.c
@@ -164,7 +164,7 @@
return 0;
}
-static struct pcmcia_device_id airo_ids[] = {
+static const struct pcmcia_device_id airo_ids[] = {
PCMCIA_DEVICE_MANF_CARD(0x015f, 0x000a),
PCMCIA_DEVICE_MANF_CARD(0x015f, 0x0005),
PCMCIA_DEVICE_MANF_CARD(0x015f, 0x0007),
diff --git a/drivers/net/wireless/atmel_cs.c b/drivers/net/wireless/atmel_cs.c
index 0526351..ec295c4 100644
--- a/drivers/net/wireless/atmel_cs.c
+++ b/drivers/net/wireless/atmel_cs.c
@@ -122,7 +122,7 @@
{
local_info_t *dev;
int ret;
- struct pcmcia_device_id *did;
+ const struct pcmcia_device_id *did;
dev = link->priv;
did = dev_get_drvdata(&link->dev);
@@ -211,7 +211,7 @@
.prod_id_hash = { (vh1), (vh2), 0, 0 }, \
.driver_info = (kernel_ulong_t)(info), }
-static struct pcmcia_device_id atmel_ids[] = {
+static const struct pcmcia_device_id atmel_ids[] = {
PCMCIA_DEVICE_MANF_CARD_INFO(0x0101, 0x0620, ATMEL_FW_TYPE_502_3COM),
PCMCIA_DEVICE_MANF_CARD_INFO(0x0101, 0x0696, ATMEL_FW_TYPE_502_3COM),
PCMCIA_DEVICE_MANF_CARD_INFO(0x01bf, 0x3302, ATMEL_FW_TYPE_502E),
diff --git a/drivers/net/wireless/b43/pcmcia.c b/drivers/net/wireless/b43/pcmcia.c
index 7dcba5f..2c8461d 100644
--- a/drivers/net/wireless/b43/pcmcia.c
+++ b/drivers/net/wireless/b43/pcmcia.c
@@ -32,7 +32,7 @@
#include <pcmcia/cisreg.h>
-static /*const */ struct pcmcia_device_id b43_pcmcia_tbl[] = {
+static const struct pcmcia_device_id b43_pcmcia_tbl[] = {
PCMCIA_DEVICE_MANF_CARD(0x2D0, 0x448),
PCMCIA_DEVICE_MANF_CARD(0x2D0, 0x476),
PCMCIA_DEVICE_NULL,
diff --git a/drivers/net/wireless/hostap/hostap_cs.c b/drivers/net/wireless/hostap/hostap_cs.c
index 2176ede..c052a0d 100644
--- a/drivers/net/wireless/hostap/hostap_cs.c
+++ b/drivers/net/wireless/hostap/hostap_cs.c
@@ -620,7 +620,7 @@
return 0;
}
-static struct pcmcia_device_id hostap_cs_ids[] = {
+static const struct pcmcia_device_id hostap_cs_ids[] = {
PCMCIA_DEVICE_MANF_CARD(0x000b, 0x7100),
PCMCIA_DEVICE_MANF_CARD(0x000b, 0x7300),
PCMCIA_DEVICE_MANF_CARD(0x0101, 0x0777),
diff --git a/drivers/net/wireless/libertas/if_cs.c b/drivers/net/wireless/libertas/if_cs.c
index 63ed579..e269351 100644
--- a/drivers/net/wireless/libertas/if_cs.c
+++ b/drivers/net/wireless/libertas/if_cs.c
@@ -983,7 +983,7 @@
/* Module initialization */
/********************************************************************/
-static struct pcmcia_device_id if_cs_ids[] = {
+static const struct pcmcia_device_id if_cs_ids[] = {
PCMCIA_DEVICE_MANF_CARD(CF8305_MANFID, CF8305_CARDID),
PCMCIA_DEVICE_MANF_CARD(CF8381_MANFID, CF8381_CARDID),
PCMCIA_DEVICE_MANF_CARD(CF8385_MANFID, CF8385_CARDID),
diff --git a/drivers/net/wireless/orinoco/orinoco_cs.c b/drivers/net/wireless/orinoco/orinoco_cs.c
index 32954c4..88e3c0e 100644
--- a/drivers/net/wireless/orinoco/orinoco_cs.c
+++ b/drivers/net/wireless/orinoco/orinoco_cs.c
@@ -237,7 +237,7 @@
/* Module initialization */
/********************************************************************/
-static struct pcmcia_device_id orinoco_cs_ids[] = {
+static const struct pcmcia_device_id orinoco_cs_ids[] = {
PCMCIA_DEVICE_MANF_CARD(0x0101, 0x0777), /* 3Com AirConnect PCI 777A */
PCMCIA_DEVICE_MANF_CARD(0x0156, 0x0002), /* Lucent Orinoco and old Intersil */
PCMCIA_DEVICE_MANF_CARD(0x016b, 0x0001), /* Ericsson WLAN Card C11 */
diff --git a/drivers/net/wireless/orinoco/spectrum_cs.c b/drivers/net/wireless/orinoco/spectrum_cs.c
index db34c28..81f3673 100644
--- a/drivers/net/wireless/orinoco/spectrum_cs.c
+++ b/drivers/net/wireless/orinoco/spectrum_cs.c
@@ -301,7 +301,7 @@
/* Module initialization */
/********************************************************************/
-static struct pcmcia_device_id spectrum_cs_ids[] = {
+static const struct pcmcia_device_id spectrum_cs_ids[] = {
PCMCIA_DEVICE_MANF_CARD(0x026c, 0x0001), /* Symbol Spectrum24 LA4137 */
PCMCIA_DEVICE_MANF_CARD(0x0104, 0x0001), /* Socket Communications CF */
PCMCIA_DEVICE_PROD_ID12("Intel", "PRO/Wireless LAN PC Card", 0x816cc815, 0x6fbf459a), /* 2011B, not 2011 */
diff --git a/drivers/net/wireless/ray_cs.c b/drivers/net/wireless/ray_cs.c
index 0764d1a..2a06ebc 100644
--- a/drivers/net/wireless/ray_cs.c
+++ b/drivers/net/wireless/ray_cs.c
@@ -2781,7 +2781,7 @@
};
#endif
-static struct pcmcia_device_id ray_ids[] = {
+static const struct pcmcia_device_id ray_ids[] = {
PCMCIA_DEVICE_MANF_CARD(0x01a6, 0x0000),
PCMCIA_DEVICE_NULL,
};
diff --git a/drivers/net/wireless/wl3501_cs.c b/drivers/net/wireless/wl3501_cs.c
index fc08f36..6bc7c92 100644
--- a/drivers/net/wireless/wl3501_cs.c
+++ b/drivers/net/wireless/wl3501_cs.c
@@ -2000,7 +2000,7 @@
}
-static struct pcmcia_device_id wl3501_ids[] = {
+static const struct pcmcia_device_id wl3501_ids[] = {
PCMCIA_DEVICE_MANF_CARD(0xd601, 0x0001),
PCMCIA_DEVICE_NULL
};
diff --git a/drivers/parport/parport_cs.c b/drivers/parport/parport_cs.c
index 787ebde..067ad51 100644
--- a/drivers/parport/parport_cs.c
+++ b/drivers/parport/parport_cs.c
@@ -178,7 +178,7 @@
} /* parport_cs_release */
-static struct pcmcia_device_id parport_ids[] = {
+static const struct pcmcia_device_id parport_ids[] = {
PCMCIA_DEVICE_FUNC_ID(3),
PCMCIA_MFC_DEVICE_PROD_ID12(1,"Elan","Serial+Parallel Port: SP230",0x3beb8cf2,0xdb9e58bc),
PCMCIA_DEVICE_MANF_CARD(0x0137, 0x0003),
diff --git a/drivers/parport/parport_pc.c b/drivers/parport/parport_pc.c
index bc8ce48..f330338 100644
--- a/drivers/parport/parport_pc.c
+++ b/drivers/parport/parport_pc.c
@@ -1621,7 +1621,7 @@
u8 origval, r;
if (verbose_probing)
printk(KERN_DEBUG "IT8705 Super-IO detection, now testing port 2E ...\n");
- if (!request_region(0x2e, 2, __func__))
+ if (!request_muxed_region(0x2e, 2, __func__))
return;
origval = inb(0x2e); /* Save original value */
outb(0x87, 0x2e);
diff --git a/drivers/pci/access.c b/drivers/pci/access.c
index 531bc69..fdaa42a 100644
--- a/drivers/pci/access.c
+++ b/drivers/pci/access.c
@@ -143,33 +143,41 @@
__remove_wait_queue(&pci_ucfg_wait, &wait);
}
+/* Returns 0 on success, negative values indicate error. */
#define PCI_USER_READ_CONFIG(size,type) \
int pci_user_read_config_##size \
(struct pci_dev *dev, int pos, type *val) \
{ \
int ret = 0; \
u32 data = -1; \
- if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
+ if (PCI_##size##_BAD) \
+ return -EINVAL; \
raw_spin_lock_irq(&pci_lock); \
if (unlikely(dev->block_ucfg_access)) pci_wait_ucfg(dev); \
ret = dev->bus->ops->read(dev->bus, dev->devfn, \
pos, sizeof(type), &data); \
raw_spin_unlock_irq(&pci_lock); \
*val = (type)data; \
+ if (ret > 0) \
+ ret = -EINVAL; \
return ret; \
}
+/* Returns 0 on success, negative values indicate error. */
#define PCI_USER_WRITE_CONFIG(size,type) \
int pci_user_write_config_##size \
(struct pci_dev *dev, int pos, type val) \
{ \
int ret = -EIO; \
- if (PCI_##size##_BAD) return PCIBIOS_BAD_REGISTER_NUMBER; \
+ if (PCI_##size##_BAD) \
+ return -EINVAL; \
raw_spin_lock_irq(&pci_lock); \
if (unlikely(dev->block_ucfg_access)) pci_wait_ucfg(dev); \
ret = dev->bus->ops->write(dev->bus, dev->devfn, \
pos, sizeof(type), val); \
raw_spin_unlock_irq(&pci_lock); \
+ if (ret > 0) \
+ ret = -EINVAL; \
return ret; \
}
@@ -197,6 +205,8 @@
* This code has to spin since there is no other notification from the PCI
* hardware. Since the VPD is often implemented by serial attachment to an
* EEPROM, it may take many milliseconds to complete.
+ *
+ * Returns 0 on success, negative values indicate error.
*/
static int pci_vpd_pci22_wait(struct pci_dev *dev)
{
@@ -212,7 +222,7 @@
for (;;) {
ret = pci_user_read_config_word(dev, vpd->cap + PCI_VPD_ADDR,
&status);
- if (ret)
+ if (ret < 0)
return ret;
if ((status & PCI_VPD_ADDR_F) == vpd->flag) {
@@ -324,6 +334,8 @@
vpd->busy = true;
vpd->flag = 0;
ret = pci_vpd_pci22_wait(dev);
+ if (ret < 0)
+ break;
pos += sizeof(u32);
}
diff --git a/drivers/pci/bus.c b/drivers/pci/bus.c
index 69546e9..1e2ad92 100644
--- a/drivers/pci/bus.c
+++ b/drivers/pci/bus.c
@@ -163,12 +163,6 @@
bus->is_added = 1;
- retval = device_create_file(&bus->dev, &dev_attr_cpuaffinity);
- if (retval)
- return retval;
-
- retval = device_create_file(&bus->dev, &dev_attr_cpulistaffinity);
-
/* Create legacy_io and legacy_mem files for this bus */
pci_create_legacy_files(bus);
diff --git a/drivers/pci/hotplug/acpiphp_glue.c b/drivers/pci/hotplug/acpiphp_glue.c
index 2f67e9b..a70fa89 100644
--- a/drivers/pci/hotplug/acpiphp_glue.c
+++ b/drivers/pci/hotplug/acpiphp_glue.c
@@ -827,6 +827,13 @@
acpiphp_set_hpp_values(bus);
acpiphp_set_acpi_region(slot);
pci_enable_bridges(bus);
+
+ list_for_each_entry(dev, &bus->devices, bus_list) {
+ /* Assume that newly added devices are powered on already. */
+ if (!dev->is_added)
+ dev->current_state = PCI_D0;
+ }
+
pci_bus_add_devices(bus);
list_for_each_entry(func, &slot->funcs, sibling) {
diff --git a/drivers/pci/hotplug/pcihp_slot.c b/drivers/pci/hotplug/pcihp_slot.c
index 80b461c..749fdf0 100644
--- a/drivers/pci/hotplug/pcihp_slot.c
+++ b/drivers/pci/hotplug/pcihp_slot.c
@@ -158,6 +158,47 @@
*/
}
+/* Program PCIE MaxPayload setting on device: ensure parent maxpayload <= device */
+static int pci_set_payload(struct pci_dev *dev)
+{
+ int pos, ppos;
+ u16 pctl, psz;
+ u16 dctl, dsz, dcap, dmax;
+ struct pci_dev *parent;
+
+ parent = dev->bus->self;
+ pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
+ if (!pos)
+ return 0;
+
+ /* Read Device MaxPayload capability and setting */
+ pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &dctl);
+ pci_read_config_word(dev, pos + PCI_EXP_DEVCAP, &dcap);
+ dsz = (dctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5;
+ dmax = (dcap & PCI_EXP_DEVCAP_PAYLOAD);
+
+ /* Read Parent MaxPayload setting */
+ ppos = pci_find_capability(parent, PCI_CAP_ID_EXP);
+ if (!ppos)
+ return 0;
+ pci_read_config_word(parent, ppos + PCI_EXP_DEVCTL, &pctl);
+ psz = (pctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5;
+
+ /* If parent payload > device max payload -> error
+ * If parent payload > device payload -> set speed
+ * If parent payload <= device payload -> do nothing
+ */
+ if (psz > dmax)
+ return -1;
+ else if (psz > dsz) {
+ dev_info(&dev->dev, "Setting MaxPayload to %d\n", 128 << psz);
+ pci_write_config_word(dev, pos + PCI_EXP_DEVCTL,
+ (dctl & ~PCI_EXP_DEVCTL_PAYLOAD) +
+ (psz << 5));
+ }
+ return 0;
+}
+
void pci_configure_slot(struct pci_dev *dev)
{
struct pci_dev *cdev;
@@ -169,6 +210,10 @@
(dev->class >> 8) == PCI_CLASS_BRIDGE_PCI)))
return;
+ ret = pci_set_payload(dev);
+ if (ret)
+ dev_warn(&dev->dev, "could not set device max payload\n");
+
memset(&hpp, 0, sizeof(hpp));
ret = pci_get_hp_params(dev, &hpp);
if (ret)
diff --git a/drivers/pci/pci-sysfs.c b/drivers/pci/pci-sysfs.c
index f8deb3e..7bcf12a 100644
--- a/drivers/pci/pci-sysfs.c
+++ b/drivers/pci/pci-sysfs.c
@@ -108,6 +108,40 @@
return len;
}
+/*
+ * PCI Bus Class Devices
+ */
+static ssize_t pci_bus_show_cpuaffinity(struct device *dev,
+ int type,
+ struct device_attribute *attr,
+ char *buf)
+{
+ int ret;
+ const struct cpumask *cpumask;
+
+ cpumask = cpumask_of_pcibus(to_pci_bus(dev));
+ ret = type ?
+ cpulist_scnprintf(buf, PAGE_SIZE-2, cpumask) :
+ cpumask_scnprintf(buf, PAGE_SIZE-2, cpumask);
+ buf[ret++] = '\n';
+ buf[ret] = '\0';
+ return ret;
+}
+
+static inline ssize_t pci_bus_show_cpumaskaffinity(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ return pci_bus_show_cpuaffinity(dev, 0, attr, buf);
+}
+
+static inline ssize_t pci_bus_show_cpulistaffinity(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ return pci_bus_show_cpuaffinity(dev, 1, attr, buf);
+}
+
/* show resources */
static ssize_t
resource_show(struct device * dev, struct device_attribute *attr, char * buf)
@@ -318,6 +352,25 @@
count = ret;
return count;
}
+
+static ssize_t
+dev_bus_rescan_store(struct device *dev, struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ unsigned long val;
+ struct pci_bus *bus = to_pci_bus(dev);
+
+ if (strict_strtoul(buf, 0, &val) < 0)
+ return -EINVAL;
+
+ if (val) {
+ mutex_lock(&pci_remove_rescan_mutex);
+ pci_rescan_bus(bus);
+ mutex_unlock(&pci_remove_rescan_mutex);
+ }
+ return count;
+}
+
#endif
struct device_attribute pci_dev_attrs[] = {
@@ -347,6 +400,15 @@
__ATTR_NULL,
};
+struct device_attribute pcibus_dev_attrs[] = {
+#ifdef CONFIG_HOTPLUG
+ __ATTR(rescan, (S_IWUSR|S_IWGRP), NULL, dev_bus_rescan_store),
+#endif
+ __ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpumaskaffinity, NULL),
+ __ATTR(cpulistaffinity, S_IRUGO, pci_bus_show_cpulistaffinity, NULL),
+ __ATTR_NULL,
+};
+
static ssize_t
boot_vga_show(struct device *dev, struct device_attribute *attr, char *buf)
{
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index 2472e71..56098b3 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -830,7 +830,7 @@
dev_err(&dev->dev, "buffer not found in %s\n", __func__);
return -ENOMEM;
}
- cap = (u16 *)&save_state->data[0];
+ cap = (u16 *)&save_state->cap.data[0];
pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
@@ -863,7 +863,7 @@
pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
if (!save_state || pos <= 0)
return;
- cap = (u16 *)&save_state->data[0];
+ cap = (u16 *)&save_state->cap.data[0];
pci_read_config_word(dev, pos + PCI_EXP_FLAGS, &flags);
@@ -899,7 +899,8 @@
return -ENOMEM;
}
- pci_read_config_word(dev, pos + PCI_X_CMD, (u16 *)save_state->data);
+ pci_read_config_word(dev, pos + PCI_X_CMD,
+ (u16 *)save_state->cap.data);
return 0;
}
@@ -914,7 +915,7 @@
pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
if (!save_state || pos <= 0)
return;
- cap = (u16 *)&save_state->data[0];
+ cap = (u16 *)&save_state->cap.data[0];
pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
}
@@ -975,6 +976,104 @@
dev->state_saved = false;
}
+struct pci_saved_state {
+ u32 config_space[16];
+ struct pci_cap_saved_data cap[0];
+};
+
+/**
+ * pci_store_saved_state - Allocate and return an opaque struct containing
+ * the device saved state.
+ * @dev: PCI device that we're dealing with
+ *
+ * Rerturn NULL if no state or error.
+ */
+struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
+{
+ struct pci_saved_state *state;
+ struct pci_cap_saved_state *tmp;
+ struct pci_cap_saved_data *cap;
+ struct hlist_node *pos;
+ size_t size;
+
+ if (!dev->state_saved)
+ return NULL;
+
+ size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
+
+ hlist_for_each_entry(tmp, pos, &dev->saved_cap_space, next)
+ size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
+
+ state = kzalloc(size, GFP_KERNEL);
+ if (!state)
+ return NULL;
+
+ memcpy(state->config_space, dev->saved_config_space,
+ sizeof(state->config_space));
+
+ cap = state->cap;
+ hlist_for_each_entry(tmp, pos, &dev->saved_cap_space, next) {
+ size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
+ memcpy(cap, &tmp->cap, len);
+ cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
+ }
+ /* Empty cap_save terminates list */
+
+ return state;
+}
+EXPORT_SYMBOL_GPL(pci_store_saved_state);
+
+/**
+ * pci_load_saved_state - Reload the provided save state into struct pci_dev.
+ * @dev: PCI device that we're dealing with
+ * @state: Saved state returned from pci_store_saved_state()
+ */
+int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state)
+{
+ struct pci_cap_saved_data *cap;
+
+ dev->state_saved = false;
+
+ if (!state)
+ return 0;
+
+ memcpy(dev->saved_config_space, state->config_space,
+ sizeof(state->config_space));
+
+ cap = state->cap;
+ while (cap->size) {
+ struct pci_cap_saved_state *tmp;
+
+ tmp = pci_find_saved_cap(dev, cap->cap_nr);
+ if (!tmp || tmp->cap.size != cap->size)
+ return -EINVAL;
+
+ memcpy(tmp->cap.data, cap->data, tmp->cap.size);
+ cap = (struct pci_cap_saved_data *)((u8 *)cap +
+ sizeof(struct pci_cap_saved_data) + cap->size);
+ }
+
+ dev->state_saved = true;
+ return 0;
+}
+EXPORT_SYMBOL_GPL(pci_load_saved_state);
+
+/**
+ * pci_load_and_free_saved_state - Reload the save state pointed to by state,
+ * and free the memory allocated for it.
+ * @dev: PCI device that we're dealing with
+ * @state: Pointer to saved state returned from pci_store_saved_state()
+ */
+int pci_load_and_free_saved_state(struct pci_dev *dev,
+ struct pci_saved_state **state)
+{
+ int ret = pci_load_saved_state(dev, *state);
+ kfree(*state);
+ *state = NULL;
+ return ret;
+}
+EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
+
static int do_pci_enable_device(struct pci_dev *dev, int bars)
{
int err;
@@ -1771,7 +1870,8 @@
if (!save_state)
return -ENOMEM;
- save_state->cap_nr = cap;
+ save_state->cap.cap_nr = cap;
+ save_state->cap.size = size;
pci_add_saved_cap(dev, save_state);
return 0;
@@ -1834,6 +1934,300 @@
bridge->ari_enabled = 1;
}
+/**
+ * pci_enable_ido - enable ID-based ordering on a device
+ * @dev: the PCI device
+ * @type: which types of IDO to enable
+ *
+ * Enable ID-based ordering on @dev. @type can contain the bits
+ * %PCI_EXP_IDO_REQUEST and/or %PCI_EXP_IDO_COMPLETION to indicate
+ * which types of transactions are allowed to be re-ordered.
+ */
+void pci_enable_ido(struct pci_dev *dev, unsigned long type)
+{
+ int pos;
+ u16 ctrl;
+
+ pos = pci_pcie_cap(dev);
+ if (!pos)
+ return;
+
+ pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
+ if (type & PCI_EXP_IDO_REQUEST)
+ ctrl |= PCI_EXP_IDO_REQ_EN;
+ if (type & PCI_EXP_IDO_COMPLETION)
+ ctrl |= PCI_EXP_IDO_CMP_EN;
+ pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
+}
+EXPORT_SYMBOL(pci_enable_ido);
+
+/**
+ * pci_disable_ido - disable ID-based ordering on a device
+ * @dev: the PCI device
+ * @type: which types of IDO to disable
+ */
+void pci_disable_ido(struct pci_dev *dev, unsigned long type)
+{
+ int pos;
+ u16 ctrl;
+
+ if (!pci_is_pcie(dev))
+ return;
+
+ pos = pci_pcie_cap(dev);
+ if (!pos)
+ return;
+
+ pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
+ if (type & PCI_EXP_IDO_REQUEST)
+ ctrl &= ~PCI_EXP_IDO_REQ_EN;
+ if (type & PCI_EXP_IDO_COMPLETION)
+ ctrl &= ~PCI_EXP_IDO_CMP_EN;
+ pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
+}
+EXPORT_SYMBOL(pci_disable_ido);
+
+/**
+ * pci_enable_obff - enable optimized buffer flush/fill
+ * @dev: PCI device
+ * @type: type of signaling to use
+ *
+ * Try to enable @type OBFF signaling on @dev. It will try using WAKE#
+ * signaling if possible, falling back to message signaling only if
+ * WAKE# isn't supported. @type should indicate whether the PCIe link
+ * be brought out of L0s or L1 to send the message. It should be either
+ * %PCI_EXP_OBFF_SIGNAL_ALWAYS or %PCI_OBFF_SIGNAL_L0.
+ *
+ * If your device can benefit from receiving all messages, even at the
+ * power cost of bringing the link back up from a low power state, use
+ * %PCI_EXP_OBFF_SIGNAL_ALWAYS. Otherwise, use %PCI_OBFF_SIGNAL_L0 (the
+ * preferred type).
+ *
+ * RETURNS:
+ * Zero on success, appropriate error number on failure.
+ */
+int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type type)
+{
+ int pos;
+ u32 cap;
+ u16 ctrl;
+ int ret;
+
+ if (!pci_is_pcie(dev))
+ return -ENOTSUPP;
+
+ pos = pci_pcie_cap(dev);
+ if (!pos)
+ return -ENOTSUPP;
+
+ pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP2, &cap);
+ if (!(cap & PCI_EXP_OBFF_MASK))
+ return -ENOTSUPP; /* no OBFF support at all */
+
+ /* Make sure the topology supports OBFF as well */
+ if (dev->bus) {
+ ret = pci_enable_obff(dev->bus->self, type);
+ if (ret)
+ return ret;
+ }
+
+ pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
+ if (cap & PCI_EXP_OBFF_WAKE)
+ ctrl |= PCI_EXP_OBFF_WAKE_EN;
+ else {
+ switch (type) {
+ case PCI_EXP_OBFF_SIGNAL_L0:
+ if (!(ctrl & PCI_EXP_OBFF_WAKE_EN))
+ ctrl |= PCI_EXP_OBFF_MSGA_EN;
+ break;
+ case PCI_EXP_OBFF_SIGNAL_ALWAYS:
+ ctrl &= ~PCI_EXP_OBFF_WAKE_EN;
+ ctrl |= PCI_EXP_OBFF_MSGB_EN;
+ break;
+ default:
+ WARN(1, "bad OBFF signal type\n");
+ return -ENOTSUPP;
+ }
+ }
+ pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
+
+ return 0;
+}
+EXPORT_SYMBOL(pci_enable_obff);
+
+/**
+ * pci_disable_obff - disable optimized buffer flush/fill
+ * @dev: PCI device
+ *
+ * Disable OBFF on @dev.
+ */
+void pci_disable_obff(struct pci_dev *dev)
+{
+ int pos;
+ u16 ctrl;
+
+ if (!pci_is_pcie(dev))
+ return;
+
+ pos = pci_pcie_cap(dev);
+ if (!pos)
+ return;
+
+ pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
+ ctrl &= ~PCI_EXP_OBFF_WAKE_EN;
+ pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
+}
+EXPORT_SYMBOL(pci_disable_obff);
+
+/**
+ * pci_ltr_supported - check whether a device supports LTR
+ * @dev: PCI device
+ *
+ * RETURNS:
+ * True if @dev supports latency tolerance reporting, false otherwise.
+ */
+bool pci_ltr_supported(struct pci_dev *dev)
+{
+ int pos;
+ u32 cap;
+
+ if (!pci_is_pcie(dev))
+ return false;
+
+ pos = pci_pcie_cap(dev);
+ if (!pos)
+ return false;
+
+ pci_read_config_dword(dev, pos + PCI_EXP_DEVCAP2, &cap);
+
+ return cap & PCI_EXP_DEVCAP2_LTR;
+}
+EXPORT_SYMBOL(pci_ltr_supported);
+
+/**
+ * pci_enable_ltr - enable latency tolerance reporting
+ * @dev: PCI device
+ *
+ * Enable LTR on @dev if possible, which means enabling it first on
+ * upstream ports.
+ *
+ * RETURNS:
+ * Zero on success, errno on failure.
+ */
+int pci_enable_ltr(struct pci_dev *dev)
+{
+ int pos;
+ u16 ctrl;
+ int ret;
+
+ if (!pci_ltr_supported(dev))
+ return -ENOTSUPP;
+
+ pos = pci_pcie_cap(dev);
+ if (!pos)
+ return -ENOTSUPP;
+
+ /* Only primary function can enable/disable LTR */
+ if (PCI_FUNC(dev->devfn) != 0)
+ return -EINVAL;
+
+ /* Enable upstream ports first */
+ if (dev->bus) {
+ ret = pci_enable_ltr(dev->bus->self);
+ if (ret)
+ return ret;
+ }
+
+ pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
+ ctrl |= PCI_EXP_LTR_EN;
+ pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
+
+ return 0;
+}
+EXPORT_SYMBOL(pci_enable_ltr);
+
+/**
+ * pci_disable_ltr - disable latency tolerance reporting
+ * @dev: PCI device
+ */
+void pci_disable_ltr(struct pci_dev *dev)
+{
+ int pos;
+ u16 ctrl;
+
+ if (!pci_ltr_supported(dev))
+ return;
+
+ pos = pci_pcie_cap(dev);
+ if (!pos)
+ return;
+
+ /* Only primary function can enable/disable LTR */
+ if (PCI_FUNC(dev->devfn) != 0)
+ return;
+
+ pci_read_config_word(dev, pos + PCI_EXP_DEVCTL2, &ctrl);
+ ctrl &= ~PCI_EXP_LTR_EN;
+ pci_write_config_word(dev, pos + PCI_EXP_DEVCTL2, ctrl);
+}
+EXPORT_SYMBOL(pci_disable_ltr);
+
+static int __pci_ltr_scale(int *val)
+{
+ int scale = 0;
+
+ while (*val > 1023) {
+ *val = (*val + 31) / 32;
+ scale++;
+ }
+ return scale;
+}
+
+/**
+ * pci_set_ltr - set LTR latency values
+ * @dev: PCI device
+ * @snoop_lat_ns: snoop latency in nanoseconds
+ * @nosnoop_lat_ns: nosnoop latency in nanoseconds
+ *
+ * Figure out the scale and set the LTR values accordingly.
+ */
+int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns)
+{
+ int pos, ret, snoop_scale, nosnoop_scale;
+ u16 val;
+
+ if (!pci_ltr_supported(dev))
+ return -ENOTSUPP;
+
+ snoop_scale = __pci_ltr_scale(&snoop_lat_ns);
+ nosnoop_scale = __pci_ltr_scale(&nosnoop_lat_ns);
+
+ if (snoop_lat_ns > PCI_LTR_VALUE_MASK ||
+ nosnoop_lat_ns > PCI_LTR_VALUE_MASK)
+ return -EINVAL;
+
+ if ((snoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)) ||
+ (nosnoop_scale > (PCI_LTR_SCALE_MASK >> PCI_LTR_SCALE_SHIFT)))
+ return -EINVAL;
+
+ pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_LTR);
+ if (!pos)
+ return -ENOTSUPP;
+
+ val = (snoop_scale << PCI_LTR_SCALE_SHIFT) | snoop_lat_ns;
+ ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_SNOOP_LAT, val);
+ if (ret != 4)
+ return -EIO;
+
+ val = (nosnoop_scale << PCI_LTR_SCALE_SHIFT) | nosnoop_lat_ns;
+ ret = pci_write_config_word(dev, pos + PCI_LTR_MAX_NOSNOOP_LAT, val);
+ if (ret != 4)
+ return -EIO;
+
+ return 0;
+}
+EXPORT_SYMBOL(pci_set_ltr);
+
static int pci_acs_enable;
/**
@@ -2479,6 +2873,21 @@
return 0;
}
+/**
+ * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
+ * @dev: Device to reset.
+ * @probe: If set, only check if the device can be reset this way.
+ *
+ * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
+ * unset, it will be reinitialized internally when going from PCI_D3hot to
+ * PCI_D0. If that's the case and the device is not in a low-power state
+ * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
+ *
+ * NOTE: This causes the caller to sleep for twice the device power transition
+ * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
+ * by devault (i.e. unless the @dev's d3_delay field has a different value).
+ * Moreover, only devices in D0 can be reset by this function.
+ */
static int pci_pm_reset(struct pci_dev *dev, int probe)
{
u16 csr;
@@ -2875,31 +3284,34 @@
* @dev: the PCI device
* @decode: true = enable decoding, false = disable decoding
* @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
- * @change_bridge: traverse ancestors and change bridges
+ * @change_bridge_flags: traverse ancestors and change bridges
+ * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
*/
int pci_set_vga_state(struct pci_dev *dev, bool decode,
- unsigned int command_bits, bool change_bridge)
+ unsigned int command_bits, u32 flags)
{
struct pci_bus *bus;
struct pci_dev *bridge;
u16 cmd;
int rc;
- WARN_ON(command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY));
+ WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) & (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
/* ARCH specific VGA enables */
- rc = pci_set_vga_state_arch(dev, decode, command_bits, change_bridge);
+ rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
if (rc)
return rc;
- pci_read_config_word(dev, PCI_COMMAND, &cmd);
- if (decode == true)
- cmd |= command_bits;
- else
- cmd &= ~command_bits;
- pci_write_config_word(dev, PCI_COMMAND, cmd);
+ if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
+ pci_read_config_word(dev, PCI_COMMAND, &cmd);
+ if (decode == true)
+ cmd |= command_bits;
+ else
+ cmd &= ~command_bits;
+ pci_write_config_word(dev, PCI_COMMAND, cmd);
+ }
- if (change_bridge == false)
+ if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
return 0;
bus = dev->bus;
diff --git a/drivers/pci/pci.h b/drivers/pci/pci.h
index 4020025..731e202 100644
--- a/drivers/pci/pci.h
+++ b/drivers/pci/pci.h
@@ -156,8 +156,7 @@
}
extern struct device_attribute pci_dev_attrs[];
-extern struct device_attribute dev_attr_cpuaffinity;
-extern struct device_attribute dev_attr_cpulistaffinity;
+extern struct device_attribute pcibus_dev_attrs[];
#ifdef CONFIG_HOTPLUG
extern struct bus_attribute pci_bus_attrs[];
#else
diff --git a/drivers/pci/pcie/aer/aer_inject.c b/drivers/pci/pcie/aer/aer_inject.c
index f62079f..95489cd 100644
--- a/drivers/pci/pcie/aer/aer_inject.c
+++ b/drivers/pci/pcie/aer/aer_inject.c
@@ -326,7 +326,7 @@
unsigned long flags;
unsigned int devfn = PCI_DEVFN(einj->dev, einj->fn);
int pos_cap_err, rp_pos_cap_err;
- u32 sever, cor_mask, uncor_mask, cor_mask_orig, uncor_mask_orig;
+ u32 sever, cor_mask, uncor_mask, cor_mask_orig = 0, uncor_mask_orig = 0;
int ret = 0;
dev = pci_get_domain_bus_and_slot((int)einj->domain, einj->bus, devfn);
diff --git a/drivers/pci/pcie/aer/aerdrv.h b/drivers/pci/pcie/aer/aerdrv.h
index 3eb7708..94a7598 100644
--- a/drivers/pci/pcie/aer/aerdrv.h
+++ b/drivers/pci/pcie/aer/aerdrv.h
@@ -114,15 +114,6 @@
extern void aer_print_port_info(struct pci_dev *dev, struct aer_err_info *info);
extern irqreturn_t aer_irq(int irq, void *context);
-#ifdef CONFIG_ACPI
-extern int aer_osc_setup(struct pcie_device *pciedev);
-#else
-static inline int aer_osc_setup(struct pcie_device *pciedev)
-{
- return 0;
-}
-#endif
-
#ifdef CONFIG_ACPI_APEI
extern int pcie_aer_get_firmware_first(struct pci_dev *pci_dev);
#else
diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c
index eee09f7..6892601 100644
--- a/drivers/pci/pcie/aspm.c
+++ b/drivers/pci/pcie/aspm.c
@@ -608,7 +608,7 @@
* the BIOS's expectation, we'll do so once pci_enable_device() is
* called.
*/
- if (aspm_policy != POLICY_POWERSAVE) {
+ if (aspm_policy != POLICY_POWERSAVE || aspm_clear_state) {
pcie_config_aspm_path(link);
pcie_set_clkpm(link, policy_to_clkpm_state(link));
}
@@ -734,7 +734,7 @@
* pci_disable_link_state - disable pci device's link state, so the link will
* never enter specific states
*/
-void pci_disable_link_state(struct pci_dev *pdev, int state)
+static void __pci_disable_link_state(struct pci_dev *pdev, int state, bool sem)
{
struct pci_dev *parent = pdev->bus->self;
struct pcie_link_state *link;
@@ -747,7 +747,8 @@
if (!parent || !parent->link_state)
return;
- down_read(&pci_bus_sem);
+ if (sem)
+ down_read(&pci_bus_sem);
mutex_lock(&aspm_lock);
link = parent->link_state;
if (state & PCIE_LINK_STATE_L0S)
@@ -761,7 +762,19 @@
pcie_set_clkpm(link, 0);
}
mutex_unlock(&aspm_lock);
- up_read(&pci_bus_sem);
+ if (sem)
+ up_read(&pci_bus_sem);
+}
+
+void pci_disable_link_state_locked(struct pci_dev *pdev, int state)
+{
+ __pci_disable_link_state(pdev, state, false);
+}
+EXPORT_SYMBOL(pci_disable_link_state_locked);
+
+void pci_disable_link_state(struct pci_dev *pdev, int state)
+{
+ __pci_disable_link_state(pdev, state, true);
}
EXPORT_SYMBOL(pci_disable_link_state);
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index 44cbbba..48849ff 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -43,43 +43,6 @@
EXPORT_SYMBOL(no_pci_devices);
/*
- * PCI Bus Class Devices
- */
-static ssize_t pci_bus_show_cpuaffinity(struct device *dev,
- int type,
- struct device_attribute *attr,
- char *buf)
-{
- int ret;
- const struct cpumask *cpumask;
-
- cpumask = cpumask_of_pcibus(to_pci_bus(dev));
- ret = type?
- cpulist_scnprintf(buf, PAGE_SIZE-2, cpumask) :
- cpumask_scnprintf(buf, PAGE_SIZE-2, cpumask);
- buf[ret++] = '\n';
- buf[ret] = '\0';
- return ret;
-}
-
-static ssize_t inline pci_bus_show_cpumaskaffinity(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- return pci_bus_show_cpuaffinity(dev, 0, attr, buf);
-}
-
-static ssize_t inline pci_bus_show_cpulistaffinity(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- return pci_bus_show_cpuaffinity(dev, 1, attr, buf);
-}
-
-DEVICE_ATTR(cpuaffinity, S_IRUGO, pci_bus_show_cpumaskaffinity, NULL);
-DEVICE_ATTR(cpulistaffinity, S_IRUGO, pci_bus_show_cpulistaffinity, NULL);
-
-/*
* PCI Bus Class
*/
static void release_pcibus_dev(struct device *dev)
@@ -95,6 +58,7 @@
static struct class pcibus_class = {
.name = "pci_bus",
.dev_release = &release_pcibus_dev,
+ .dev_attrs = pcibus_dev_attrs,
};
static int __init pcibus_class_init(void)
@@ -1455,9 +1419,6 @@
error = device_register(&b->dev);
if (error)
goto class_dev_reg_err;
- error = device_create_file(&b->dev, &dev_attr_cpuaffinity);
- if (error)
- goto dev_create_file_err;
/* Create legacy_io and legacy_mem files for this bus */
pci_create_legacy_files(b);
@@ -1468,8 +1429,6 @@
return b;
-dev_create_file_err:
- device_unregister(&b->dev);
class_dev_reg_err:
device_unregister(dev);
dev_reg_err:
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 5129ed6..e8a1406 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -606,7 +606,7 @@
}
pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
- if (enable & ICH4_GPIO_EN) {
+ if (enable & ICH6_GPIO_EN) {
pci_read_config_dword(dev, ICH6_GPIOBASE, ®ion);
region &= PCI_BASE_ADDRESS_IO_MASK;
if (region >= PCIBIOS_MIN_IO)
@@ -681,7 +681,7 @@
/* ICH7-10 has the same common LPC generic IO decode registers */
static void __devinit quirk_ich7_lpc(struct pci_dev *dev)
{
- /* We share the common ACPI/DPIO decode with ICH6 */
+ /* We share the common ACPI/GPIO decode with ICH6 */
ich6_lpc_acpi_gpio(dev);
/* And have 4 ICH7+ generic decodes */
@@ -2349,8 +2349,11 @@
*/
static void __devinit nvenet_msi_disable(struct pci_dev *dev)
{
- if (dmi_name_in_vendors("P5N32-SLI PREMIUM") ||
- dmi_name_in_vendors("P5N32-E SLI")) {
+ const char *board_name = dmi_get_system_info(DMI_BOARD_NAME);
+
+ if (board_name &&
+ (strstr(board_name, "P5N32-SLI PREMIUM") ||
+ strstr(board_name, "P5N32-E SLI"))) {
dev_info(&dev->dev,
"Disabling msi for MCP55 NIC on P5N32-SLI\n");
dev->no_msi = 1;
@@ -2784,6 +2787,16 @@
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
#endif
+static void __devinit fixup_ti816x_class(struct pci_dev* dev)
+{
+ /* TI 816x devices do not have class code set when in PCIe boot mode */
+ if (dev->class == PCI_CLASS_NOT_DEFINED) {
+ dev_info(&dev->dev, "Setting PCI class for 816x PCIe device\n");
+ dev->class = PCI_CLASS_MULTIMEDIA_VIDEO;
+ }
+}
+DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_TI, 0xb800, fixup_ti816x_class);
+
static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
struct pci_fixup *end)
{
diff --git a/drivers/pci/remove.c b/drivers/pci/remove.c
index 176615e..7f87bee 100644
--- a/drivers/pci/remove.c
+++ b/drivers/pci/remove.c
@@ -73,8 +73,6 @@
return;
pci_remove_legacy_files(pci_bus);
- device_remove_file(&pci_bus->dev, &dev_attr_cpuaffinity);
- device_remove_file(&pci_bus->dev, &dev_attr_cpulistaffinity);
device_unregister(&pci_bus->dev);
}
EXPORT_SYMBOL(pci_remove_bus);
diff --git a/drivers/pci/setup-bus.c b/drivers/pci/setup-bus.c
index a806cb3..1e9e5a5 100644
--- a/drivers/pci/setup-bus.c
+++ b/drivers/pci/setup-bus.c
@@ -991,30 +991,139 @@
}
}
+static int __init pci_bus_get_depth(struct pci_bus *bus)
+{
+ int depth = 0;
+ struct pci_dev *dev;
+
+ list_for_each_entry(dev, &bus->devices, bus_list) {
+ int ret;
+ struct pci_bus *b = dev->subordinate;
+ if (!b)
+ continue;
+
+ ret = pci_bus_get_depth(b);
+ if (ret + 1 > depth)
+ depth = ret + 1;
+ }
+
+ return depth;
+}
+static int __init pci_get_max_depth(void)
+{
+ int depth = 0;
+ struct pci_bus *bus;
+
+ list_for_each_entry(bus, &pci_root_buses, node) {
+ int ret;
+
+ ret = pci_bus_get_depth(bus);
+ if (ret > depth)
+ depth = ret;
+ }
+
+ return depth;
+}
+
+/*
+ * first try will not touch pci bridge res
+ * second and later try will clear small leaf bridge res
+ * will stop till to the max deepth if can not find good one
+ */
void __init
pci_assign_unassigned_resources(void)
{
struct pci_bus *bus;
struct resource_list_x add_list; /* list of resources that
want additional resources */
+ int tried_times = 0;
+ enum release_type rel_type = leaf_only;
+ struct resource_list_x head, *list;
+ unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
+ IORESOURCE_PREFETCH;
+ unsigned long failed_type;
+ int max_depth = pci_get_max_depth();
+ int pci_try_num;
+
+
+ head.next = NULL;
add_list.next = NULL;
+
+ pci_try_num = max_depth + 1;
+ printk(KERN_DEBUG "PCI: max bus depth: %d pci_try_num: %d\n",
+ max_depth, pci_try_num);
+
+again:
/* Depth first, calculate sizes and alignments of all
subordinate buses. */
- list_for_each_entry(bus, &pci_root_buses, node) {
+ list_for_each_entry(bus, &pci_root_buses, node)
__pci_bus_size_bridges(bus, &add_list);
- }
/* Depth last, allocate resources and update the hardware. */
- list_for_each_entry(bus, &pci_root_buses, node) {
- __pci_bus_assign_resources(bus, &add_list, NULL);
- pci_enable_bridges(bus);
- }
+ list_for_each_entry(bus, &pci_root_buses, node)
+ __pci_bus_assign_resources(bus, &add_list, &head);
BUG_ON(add_list.next);
+ tried_times++;
+
+ /* any device complain? */
+ if (!head.next)
+ goto enable_and_dump;
+ failed_type = 0;
+ for (list = head.next; list;) {
+ failed_type |= list->flags;
+ list = list->next;
+ }
+ /*
+ * io port are tight, don't try extra
+ * or if reach the limit, don't want to try more
+ */
+ failed_type &= type_mask;
+ if ((failed_type == IORESOURCE_IO) || (tried_times >= pci_try_num)) {
+ free_list(resource_list_x, &head);
+ goto enable_and_dump;
+ }
+
+ printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n",
+ tried_times + 1);
+
+ /* third times and later will not check if it is leaf */
+ if ((tried_times + 1) > 2)
+ rel_type = whole_subtree;
+
+ /*
+ * Try to release leaf bridge's resources that doesn't fit resource of
+ * child device under that bridge
+ */
+ for (list = head.next; list;) {
+ bus = list->dev->bus;
+ pci_bus_release_bridge_resources(bus, list->flags & type_mask,
+ rel_type);
+ list = list->next;
+ }
+ /* restore size and flags */
+ for (list = head.next; list;) {
+ struct resource *res = list->res;
+
+ res->start = list->start;
+ res->end = list->end;
+ res->flags = list->flags;
+ if (list->dev->subordinate)
+ res->flags = 0;
+
+ list = list->next;
+ }
+ free_list(resource_list_x, &head);
+
+ goto again;
+
+enable_and_dump:
+ /* Depth last, update the hardware. */
+ list_for_each_entry(bus, &pci_root_buses, node)
+ pci_enable_bridges(bus);
/* dump the resource on buses */
- list_for_each_entry(bus, &pci_root_buses, node) {
+ list_for_each_entry(bus, &pci_root_buses, node)
pci_bus_dump_resources(bus);
- }
}
void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge)
diff --git a/drivers/pcmcia/ds.c b/drivers/pcmcia/ds.c
index 100c441..749c2a1 100644
--- a/drivers/pcmcia/ds.c
+++ b/drivers/pcmcia/ds.c
@@ -45,7 +45,7 @@
static void pcmcia_check_driver(struct pcmcia_driver *p_drv)
{
- struct pcmcia_device_id *did = p_drv->id_table;
+ const struct pcmcia_device_id *did = p_drv->id_table;
unsigned int i;
u32 hash;
@@ -784,7 +784,7 @@
static inline int pcmcia_devmatch(struct pcmcia_device *dev,
- struct pcmcia_device_id *did)
+ const struct pcmcia_device_id *did)
{
if (did->match_flags & PCMCIA_DEV_ID_MATCH_MANF_ID) {
if ((!dev->has_manf_id) || (dev->manf_id != did->manf_id))
@@ -890,7 +890,7 @@
{
struct pcmcia_device *p_dev = to_pcmcia_dev(dev);
struct pcmcia_driver *p_drv = to_pcmcia_drv(drv);
- struct pcmcia_device_id *did = p_drv->id_table;
+ const struct pcmcia_device_id *did = p_drv->id_table;
struct pcmcia_dynid *dynid;
/* match dynamic devices first */
diff --git a/drivers/pcmcia/sa1100_generic.c b/drivers/pcmcia/sa1100_generic.c
index fb9740d..2eea664 100644
--- a/drivers/pcmcia/sa1100_generic.c
+++ b/drivers/pcmcia/sa1100_generic.c
@@ -43,7 +43,7 @@
int __init pcmcia_collie_init(struct device *dev);
-static int (*sa11x0_pcmcia_hw_init[])(struct device *dev) = {
+static int (*sa11x0_pcmcia_hw_init[])(struct device *dev) __devinitdata = {
#ifdef CONFIG_SA1100_ASSABET
pcmcia_assabet_init,
#endif
diff --git a/drivers/platform/x86/Kconfig b/drivers/platform/x86/Kconfig
index 485c09e..5cb999b 100644
--- a/drivers/platform/x86/Kconfig
+++ b/drivers/platform/x86/Kconfig
@@ -753,4 +753,11 @@
To compile this driver as a module, choose M here: the module
will be called samsung-laptop.
+config MXM_WMI
+ tristate "WMI support for MXM Laptop Graphics"
+ depends on ACPI_WMI
+ ---help---
+ MXM is a standard for laptop graphics cards, the WMI interface
+ is required for switchable nvidia graphics machines
+
endif # X86_PLATFORM_DEVICES
diff --git a/drivers/platform/x86/Makefile b/drivers/platform/x86/Makefile
index 029e886..a7ab3bc 100644
--- a/drivers/platform/x86/Makefile
+++ b/drivers/platform/x86/Makefile
@@ -42,3 +42,4 @@
obj-$(CONFIG_IBM_RTL) += ibm_rtl.o
obj-$(CONFIG_SAMSUNG_LAPTOP) += samsung-laptop.o
obj-$(CONFIG_INTEL_MFLD_THERMAL) += intel_mid_thermal.o
+obj-$(CONFIG_MXM_WMI) += mxm-wmi.o
diff --git a/drivers/platform/x86/ibm_rtl.c b/drivers/platform/x86/ibm_rtl.c
index 94a114a..b1396e5 100644
--- a/drivers/platform/x86/ibm_rtl.c
+++ b/drivers/platform/x86/ibm_rtl.c
@@ -81,6 +81,19 @@
static u8 rtl_cmd_type;
static u8 rtl_cmd_width;
+#ifndef readq
+static inline __u64 readq(const volatile void __iomem *addr)
+{
+ const volatile u32 __iomem *p = addr;
+ u32 low, high;
+
+ low = readl(p);
+ high = readl(p + 1);
+
+ return low + ((u64)high << 32);
+}
+#endif
+
static void __iomem *rtl_port_map(phys_addr_t addr, unsigned long len)
{
if (rtl_cmd_type == RTL_ADDR_TYPE_MMIO)
diff --git a/drivers/platform/x86/intel_ips.c b/drivers/platform/x86/intel_ips.c
index 85c8ad4..5ffe7c3 100644
--- a/drivers/platform/x86/intel_ips.c
+++ b/drivers/platform/x86/intel_ips.c
@@ -344,6 +344,19 @@
static bool
ips_gpu_turbo_enabled(struct ips_driver *ips);
+#ifndef readq
+static inline __u64 readq(const volatile void __iomem *addr)
+{
+ const volatile u32 __iomem *p = addr;
+ u32 low, high;
+
+ low = readl(p);
+ high = readl(p + 1);
+
+ return low + ((u64)high << 32);
+}
+#endif
+
/**
* ips_cpu_busy - is CPU busy?
* @ips: IPS driver struct
diff --git a/drivers/platform/x86/mxm-wmi.c b/drivers/platform/x86/mxm-wmi.c
new file mode 100644
index 0000000..0aea63b
--- /dev/null
+++ b/drivers/platform/x86/mxm-wmi.c
@@ -0,0 +1,111 @@
+/*
+ * MXM WMI driver
+ *
+ * Copyright(C) 2010 Red Hat.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <acpi/acpi_bus.h>
+#include <acpi/acpi_drivers.h>
+
+MODULE_AUTHOR("Dave Airlie");
+MODULE_DESCRIPTION("MXM WMI Driver");
+MODULE_LICENSE("GPL");
+
+#define MXM_WMMX_GUID "F6CB5C3C-9CAE-4EBD-B577-931EA32A2CC0"
+
+MODULE_ALIAS("wmi:"MXM_WMMX_GUID);
+
+#define MXM_WMMX_FUNC_MXDS 0x5344584D /* "MXDS" */
+#define MXM_WMMX_FUNC_MXMX 0x53445344 /* "MXMX" */
+
+struct mxds_args {
+ u32 func;
+ u32 args;
+ u32 xarg;
+};
+
+int mxm_wmi_call_mxds(int adapter)
+{
+ struct mxds_args args = {
+ .func = MXM_WMMX_FUNC_MXDS,
+ .args = 0,
+ .xarg = 1,
+ };
+ struct acpi_buffer input = { (acpi_size)sizeof(args), &args };
+ struct acpi_buffer output = { ACPI_ALLOCATE_BUFFER, NULL };
+ acpi_status status;
+
+ printk("calling mux switch %d\n", adapter);
+
+ status = wmi_evaluate_method(MXM_WMMX_GUID, 0x1, adapter, &input,
+ &output);
+
+ if (ACPI_FAILURE(status))
+ return status;
+
+ printk("mux switched %d\n", status);
+ return 0;
+
+}
+EXPORT_SYMBOL_GPL(mxm_wmi_call_mxds);
+
+int mxm_wmi_call_mxmx(int adapter)
+{
+ struct mxds_args args = {
+ .func = MXM_WMMX_FUNC_MXMX,
+ .args = 0,
+ .xarg = 1,
+ };
+ struct acpi_buffer input = { (acpi_size)sizeof(args), &args };
+ struct acpi_buffer output = { ACPI_ALLOCATE_BUFFER, NULL };
+ acpi_status status;
+
+ printk("calling mux switch %d\n", adapter);
+
+ status = wmi_evaluate_method(MXM_WMMX_GUID, 0x1, adapter, &input,
+ &output);
+
+ if (ACPI_FAILURE(status))
+ return status;
+
+ printk("mux mutex set switched %d\n", status);
+ return 0;
+
+}
+EXPORT_SYMBOL_GPL(mxm_wmi_call_mxmx);
+
+bool mxm_wmi_supported(void)
+{
+ bool guid_valid;
+ guid_valid = wmi_has_guid(MXM_WMMX_GUID);
+ return guid_valid;
+}
+EXPORT_SYMBOL_GPL(mxm_wmi_supported);
+
+static int __init mxm_wmi_init(void)
+{
+ return 0;
+}
+
+static void __exit mxm_wmi_exit(void)
+{
+}
+
+module_init(mxm_wmi_init);
+module_exit(mxm_wmi_exit);
diff --git a/drivers/ptp/Kconfig b/drivers/ptp/Kconfig
new file mode 100644
index 0000000..68d7201
--- /dev/null
+++ b/drivers/ptp/Kconfig
@@ -0,0 +1,75 @@
+#
+# PTP clock support configuration
+#
+
+menu "PTP clock support"
+
+comment "Enable Device Drivers -> PPS to see the PTP clock options."
+ depends on PPS=n
+
+config PTP_1588_CLOCK
+ tristate "PTP clock support"
+ depends on EXPERIMENTAL
+ depends on PPS
+ help
+ The IEEE 1588 standard defines a method to precisely
+ synchronize distributed clocks over Ethernet networks. The
+ standard defines a Precision Time Protocol (PTP), which can
+ be used to achieve synchronization within a few dozen
+ microseconds. In addition, with the help of special hardware
+ time stamping units, it can be possible to achieve
+ synchronization to within a few hundred nanoseconds.
+
+ This driver adds support for PTP clocks as character
+ devices. If you want to use a PTP clock, then you should
+ also enable at least one clock driver as well.
+
+ To compile this driver as a module, choose M here: the module
+ will be called ptp.
+
+config PTP_1588_CLOCK_GIANFAR
+ tristate "Freescale eTSEC as PTP clock"
+ depends on PTP_1588_CLOCK
+ depends on GIANFAR
+ help
+ This driver adds support for using the eTSEC as a PTP
+ clock. This clock is only useful if your PTP programs are
+ getting hardware time stamps on the PTP Ethernet packets
+ using the SO_TIMESTAMPING API.
+
+ To compile this driver as a module, choose M here: the module
+ will be called gianfar_ptp.
+
+config PTP_1588_CLOCK_IXP46X
+ tristate "Intel IXP46x as PTP clock"
+ depends on PTP_1588_CLOCK
+ depends on IXP4XX_ETH
+ help
+ This driver adds support for using the IXP46X as a PTP
+ clock. This clock is only useful if your PTP programs are
+ getting hardware time stamps on the PTP Ethernet packets
+ using the SO_TIMESTAMPING API.
+
+ To compile this driver as a module, choose M here: the module
+ will be called ptp_ixp46x.
+
+comment "Enable PHYLIB and NETWORK_PHY_TIMESTAMPING to see the additional clocks."
+ depends on PTP_1588_CLOCK && (PHYLIB=n || NETWORK_PHY_TIMESTAMPING=n)
+
+config DP83640_PHY
+ tristate "Driver for the National Semiconductor DP83640 PHYTER"
+ depends on PTP_1588_CLOCK
+ depends on NETWORK_PHY_TIMESTAMPING
+ depends on PHYLIB
+ ---help---
+ Supports the DP83640 PHYTER with IEEE 1588 features.
+
+ This driver adds support for using the DP83640 as a PTP
+ clock. This clock is only useful if your PTP programs are
+ getting hardware time stamps on the PTP Ethernet packets
+ using the SO_TIMESTAMPING API.
+
+ In order for this to work, your MAC driver must also
+ implement the skb_tx_timetamp() function.
+
+endmenu
diff --git a/drivers/ptp/Makefile b/drivers/ptp/Makefile
new file mode 100644
index 0000000..f6933e8
--- /dev/null
+++ b/drivers/ptp/Makefile
@@ -0,0 +1,7 @@
+#
+# Makefile for PTP 1588 clock support.
+#
+
+ptp-y := ptp_clock.o ptp_chardev.o ptp_sysfs.o
+obj-$(CONFIG_PTP_1588_CLOCK) += ptp.o
+obj-$(CONFIG_PTP_1588_CLOCK_IXP46X) += ptp_ixp46x.o
diff --git a/drivers/ptp/ptp_chardev.c b/drivers/ptp/ptp_chardev.c
new file mode 100644
index 0000000..a8d03ae
--- /dev/null
+++ b/drivers/ptp/ptp_chardev.c
@@ -0,0 +1,159 @@
+/*
+ * PTP 1588 clock support - character device implementation.
+ *
+ * Copyright (C) 2010 OMICRON electronics GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/module.h>
+#include <linux/posix-clock.h>
+#include <linux/poll.h>
+#include <linux/sched.h>
+
+#include "ptp_private.h"
+
+int ptp_open(struct posix_clock *pc, fmode_t fmode)
+{
+ return 0;
+}
+
+long ptp_ioctl(struct posix_clock *pc, unsigned int cmd, unsigned long arg)
+{
+ struct ptp_clock_caps caps;
+ struct ptp_clock_request req;
+ struct ptp_clock *ptp = container_of(pc, struct ptp_clock, clock);
+ struct ptp_clock_info *ops = ptp->info;
+ int enable, err = 0;
+
+ switch (cmd) {
+
+ case PTP_CLOCK_GETCAPS:
+ memset(&caps, 0, sizeof(caps));
+ caps.max_adj = ptp->info->max_adj;
+ caps.n_alarm = ptp->info->n_alarm;
+ caps.n_ext_ts = ptp->info->n_ext_ts;
+ caps.n_per_out = ptp->info->n_per_out;
+ caps.pps = ptp->info->pps;
+ err = copy_to_user((void __user *)arg, &caps, sizeof(caps));
+ break;
+
+ case PTP_EXTTS_REQUEST:
+ if (copy_from_user(&req.extts, (void __user *)arg,
+ sizeof(req.extts))) {
+ err = -EFAULT;
+ break;
+ }
+ if (req.extts.index >= ops->n_ext_ts) {
+ err = -EINVAL;
+ break;
+ }
+ req.type = PTP_CLK_REQ_EXTTS;
+ enable = req.extts.flags & PTP_ENABLE_FEATURE ? 1 : 0;
+ err = ops->enable(ops, &req, enable);
+ break;
+
+ case PTP_PEROUT_REQUEST:
+ if (copy_from_user(&req.perout, (void __user *)arg,
+ sizeof(req.perout))) {
+ err = -EFAULT;
+ break;
+ }
+ if (req.perout.index >= ops->n_per_out) {
+ err = -EINVAL;
+ break;
+ }
+ req.type = PTP_CLK_REQ_PEROUT;
+ enable = req.perout.period.sec || req.perout.period.nsec;
+ err = ops->enable(ops, &req, enable);
+ break;
+
+ case PTP_ENABLE_PPS:
+ if (!capable(CAP_SYS_TIME))
+ return -EPERM;
+ req.type = PTP_CLK_REQ_PPS;
+ enable = arg ? 1 : 0;
+ err = ops->enable(ops, &req, enable);
+ break;
+
+ default:
+ err = -ENOTTY;
+ break;
+ }
+ return err;
+}
+
+unsigned int ptp_poll(struct posix_clock *pc, struct file *fp, poll_table *wait)
+{
+ struct ptp_clock *ptp = container_of(pc, struct ptp_clock, clock);
+
+ poll_wait(fp, &ptp->tsev_wq, wait);
+
+ return queue_cnt(&ptp->tsevq) ? POLLIN : 0;
+}
+
+ssize_t ptp_read(struct posix_clock *pc,
+ uint rdflags, char __user *buf, size_t cnt)
+{
+ struct ptp_clock *ptp = container_of(pc, struct ptp_clock, clock);
+ struct timestamp_event_queue *queue = &ptp->tsevq;
+ struct ptp_extts_event event[PTP_BUF_TIMESTAMPS];
+ unsigned long flags;
+ size_t qcnt, i;
+
+ if (cnt % sizeof(struct ptp_extts_event) != 0)
+ return -EINVAL;
+
+ if (cnt > sizeof(event))
+ cnt = sizeof(event);
+
+ cnt = cnt / sizeof(struct ptp_extts_event);
+
+ if (mutex_lock_interruptible(&ptp->tsevq_mux))
+ return -ERESTARTSYS;
+
+ if (wait_event_interruptible(ptp->tsev_wq,
+ ptp->defunct || queue_cnt(queue))) {
+ mutex_unlock(&ptp->tsevq_mux);
+ return -ERESTARTSYS;
+ }
+
+ if (ptp->defunct)
+ return -ENODEV;
+
+ spin_lock_irqsave(&queue->lock, flags);
+
+ qcnt = queue_cnt(queue);
+
+ if (cnt > qcnt)
+ cnt = qcnt;
+
+ for (i = 0; i < cnt; i++) {
+ event[i] = queue->buf[queue->head];
+ queue->head = (queue->head + 1) % PTP_MAX_TIMESTAMPS;
+ }
+
+ spin_unlock_irqrestore(&queue->lock, flags);
+
+ cnt = cnt * sizeof(struct ptp_extts_event);
+
+ mutex_unlock(&ptp->tsevq_mux);
+
+ if (copy_to_user(buf, event, cnt)) {
+ mutex_unlock(&ptp->tsevq_mux);
+ return -EFAULT;
+ }
+
+ return cnt;
+}
diff --git a/drivers/ptp/ptp_clock.c b/drivers/ptp/ptp_clock.c
new file mode 100644
index 0000000..cf3f999
--- /dev/null
+++ b/drivers/ptp/ptp_clock.c
@@ -0,0 +1,343 @@
+/*
+ * PTP 1588 clock support
+ *
+ * Copyright (C) 2010 OMICRON electronics GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/bitops.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/posix-clock.h>
+#include <linux/pps_kernel.h>
+#include <linux/slab.h>
+#include <linux/syscalls.h>
+#include <linux/uaccess.h>
+
+#include "ptp_private.h"
+
+#define PTP_MAX_ALARMS 4
+#define PTP_MAX_CLOCKS 8
+#define PTP_PPS_DEFAULTS (PPS_CAPTUREASSERT | PPS_OFFSETASSERT)
+#define PTP_PPS_EVENT PPS_CAPTUREASSERT
+#define PTP_PPS_MODE (PTP_PPS_DEFAULTS | PPS_CANWAIT | PPS_TSFMT_TSPEC)
+
+/* private globals */
+
+static dev_t ptp_devt;
+static struct class *ptp_class;
+
+static DECLARE_BITMAP(ptp_clocks_map, PTP_MAX_CLOCKS);
+static DEFINE_MUTEX(ptp_clocks_mutex); /* protects 'ptp_clocks_map' */
+
+/* time stamp event queue operations */
+
+static inline int queue_free(struct timestamp_event_queue *q)
+{
+ return PTP_MAX_TIMESTAMPS - queue_cnt(q) - 1;
+}
+
+static void enqueue_external_timestamp(struct timestamp_event_queue *queue,
+ struct ptp_clock_event *src)
+{
+ struct ptp_extts_event *dst;
+ unsigned long flags;
+ s64 seconds;
+ u32 remainder;
+
+ seconds = div_u64_rem(src->timestamp, 1000000000, &remainder);
+
+ spin_lock_irqsave(&queue->lock, flags);
+
+ dst = &queue->buf[queue->tail];
+ dst->index = src->index;
+ dst->t.sec = seconds;
+ dst->t.nsec = remainder;
+
+ if (!queue_free(queue))
+ queue->head = (queue->head + 1) % PTP_MAX_TIMESTAMPS;
+
+ queue->tail = (queue->tail + 1) % PTP_MAX_TIMESTAMPS;
+
+ spin_unlock_irqrestore(&queue->lock, flags);
+}
+
+static s32 scaled_ppm_to_ppb(long ppm)
+{
+ /*
+ * The 'freq' field in the 'struct timex' is in parts per
+ * million, but with a 16 bit binary fractional field.
+ *
+ * We want to calculate
+ *
+ * ppb = scaled_ppm * 1000 / 2^16
+ *
+ * which simplifies to
+ *
+ * ppb = scaled_ppm * 125 / 2^13
+ */
+ s64 ppb = 1 + ppm;
+ ppb *= 125;
+ ppb >>= 13;
+ return (s32) ppb;
+}
+
+/* posix clock implementation */
+
+static int ptp_clock_getres(struct posix_clock *pc, struct timespec *tp)
+{
+ return 1; /* always round timer functions to one nanosecond */
+}
+
+static int ptp_clock_settime(struct posix_clock *pc, const struct timespec *tp)
+{
+ struct ptp_clock *ptp = container_of(pc, struct ptp_clock, clock);
+ return ptp->info->settime(ptp->info, tp);
+}
+
+static int ptp_clock_gettime(struct posix_clock *pc, struct timespec *tp)
+{
+ struct ptp_clock *ptp = container_of(pc, struct ptp_clock, clock);
+ return ptp->info->gettime(ptp->info, tp);
+}
+
+static int ptp_clock_adjtime(struct posix_clock *pc, struct timex *tx)
+{
+ struct ptp_clock *ptp = container_of(pc, struct ptp_clock, clock);
+ struct ptp_clock_info *ops;
+ int err = -EOPNOTSUPP;
+
+ ops = ptp->info;
+
+ if (tx->modes & ADJ_SETOFFSET) {
+ struct timespec ts;
+ ktime_t kt;
+ s64 delta;
+
+ ts.tv_sec = tx->time.tv_sec;
+ ts.tv_nsec = tx->time.tv_usec;
+
+ if (!(tx->modes & ADJ_NANO))
+ ts.tv_nsec *= 1000;
+
+ if ((unsigned long) ts.tv_nsec >= NSEC_PER_SEC)
+ return -EINVAL;
+
+ kt = timespec_to_ktime(ts);
+ delta = ktime_to_ns(kt);
+ err = ops->adjtime(ops, delta);
+
+ } else if (tx->modes & ADJ_FREQUENCY) {
+
+ err = ops->adjfreq(ops, scaled_ppm_to_ppb(tx->freq));
+ }
+
+ return err;
+}
+
+static struct posix_clock_operations ptp_clock_ops = {
+ .owner = THIS_MODULE,
+ .clock_adjtime = ptp_clock_adjtime,
+ .clock_gettime = ptp_clock_gettime,
+ .clock_getres = ptp_clock_getres,
+ .clock_settime = ptp_clock_settime,
+ .ioctl = ptp_ioctl,
+ .open = ptp_open,
+ .poll = ptp_poll,
+ .read = ptp_read,
+};
+
+static void delete_ptp_clock(struct posix_clock *pc)
+{
+ struct ptp_clock *ptp = container_of(pc, struct ptp_clock, clock);
+
+ mutex_destroy(&ptp->tsevq_mux);
+
+ /* Remove the clock from the bit map. */
+ mutex_lock(&ptp_clocks_mutex);
+ clear_bit(ptp->index, ptp_clocks_map);
+ mutex_unlock(&ptp_clocks_mutex);
+
+ kfree(ptp);
+}
+
+/* public interface */
+
+struct ptp_clock *ptp_clock_register(struct ptp_clock_info *info)
+{
+ struct ptp_clock *ptp;
+ int err = 0, index, major = MAJOR(ptp_devt);
+
+ if (info->n_alarm > PTP_MAX_ALARMS)
+ return ERR_PTR(-EINVAL);
+
+ /* Find a free clock slot and reserve it. */
+ err = -EBUSY;
+ mutex_lock(&ptp_clocks_mutex);
+ index = find_first_zero_bit(ptp_clocks_map, PTP_MAX_CLOCKS);
+ if (index < PTP_MAX_CLOCKS)
+ set_bit(index, ptp_clocks_map);
+ else
+ goto no_slot;
+
+ /* Initialize a clock structure. */
+ err = -ENOMEM;
+ ptp = kzalloc(sizeof(struct ptp_clock), GFP_KERNEL);
+ if (ptp == NULL)
+ goto no_memory;
+
+ ptp->clock.ops = ptp_clock_ops;
+ ptp->clock.release = delete_ptp_clock;
+ ptp->info = info;
+ ptp->devid = MKDEV(major, index);
+ ptp->index = index;
+ spin_lock_init(&ptp->tsevq.lock);
+ mutex_init(&ptp->tsevq_mux);
+ init_waitqueue_head(&ptp->tsev_wq);
+
+ /* Create a new device in our class. */
+ ptp->dev = device_create(ptp_class, NULL, ptp->devid, ptp,
+ "ptp%d", ptp->index);
+ if (IS_ERR(ptp->dev))
+ goto no_device;
+
+ dev_set_drvdata(ptp->dev, ptp);
+
+ err = ptp_populate_sysfs(ptp);
+ if (err)
+ goto no_sysfs;
+
+ /* Register a new PPS source. */
+ if (info->pps) {
+ struct pps_source_info pps;
+ memset(&pps, 0, sizeof(pps));
+ snprintf(pps.name, PPS_MAX_NAME_LEN, "ptp%d", index);
+ pps.mode = PTP_PPS_MODE;
+ pps.owner = info->owner;
+ ptp->pps_source = pps_register_source(&pps, PTP_PPS_DEFAULTS);
+ if (!ptp->pps_source) {
+ pr_err("failed to register pps source\n");
+ goto no_pps;
+ }
+ }
+
+ /* Create a posix clock. */
+ err = posix_clock_register(&ptp->clock, ptp->devid);
+ if (err) {
+ pr_err("failed to create posix clock\n");
+ goto no_clock;
+ }
+
+ mutex_unlock(&ptp_clocks_mutex);
+ return ptp;
+
+no_clock:
+ if (ptp->pps_source)
+ pps_unregister_source(ptp->pps_source);
+no_pps:
+ ptp_cleanup_sysfs(ptp);
+no_sysfs:
+ device_destroy(ptp_class, ptp->devid);
+no_device:
+ mutex_destroy(&ptp->tsevq_mux);
+ kfree(ptp);
+no_memory:
+ clear_bit(index, ptp_clocks_map);
+no_slot:
+ mutex_unlock(&ptp_clocks_mutex);
+ return ERR_PTR(err);
+}
+EXPORT_SYMBOL(ptp_clock_register);
+
+int ptp_clock_unregister(struct ptp_clock *ptp)
+{
+ ptp->defunct = 1;
+ wake_up_interruptible(&ptp->tsev_wq);
+
+ /* Release the clock's resources. */
+ if (ptp->pps_source)
+ pps_unregister_source(ptp->pps_source);
+ ptp_cleanup_sysfs(ptp);
+ device_destroy(ptp_class, ptp->devid);
+
+ posix_clock_unregister(&ptp->clock);
+ return 0;
+}
+EXPORT_SYMBOL(ptp_clock_unregister);
+
+void ptp_clock_event(struct ptp_clock *ptp, struct ptp_clock_event *event)
+{
+ struct pps_event_time evt;
+
+ switch (event->type) {
+
+ case PTP_CLOCK_ALARM:
+ break;
+
+ case PTP_CLOCK_EXTTS:
+ enqueue_external_timestamp(&ptp->tsevq, event);
+ wake_up_interruptible(&ptp->tsev_wq);
+ break;
+
+ case PTP_CLOCK_PPS:
+ pps_get_ts(&evt);
+ pps_event(ptp->pps_source, &evt, PTP_PPS_EVENT, NULL);
+ break;
+ }
+}
+EXPORT_SYMBOL(ptp_clock_event);
+
+/* module operations */
+
+static void __exit ptp_exit(void)
+{
+ class_destroy(ptp_class);
+ unregister_chrdev_region(ptp_devt, PTP_MAX_CLOCKS);
+}
+
+static int __init ptp_init(void)
+{
+ int err;
+
+ ptp_class = class_create(THIS_MODULE, "ptp");
+ if (IS_ERR(ptp_class)) {
+ pr_err("ptp: failed to allocate class\n");
+ return PTR_ERR(ptp_class);
+ }
+
+ err = alloc_chrdev_region(&ptp_devt, 0, PTP_MAX_CLOCKS, "ptp");
+ if (err < 0) {
+ pr_err("ptp: failed to allocate device region\n");
+ goto no_region;
+ }
+
+ ptp_class->dev_attrs = ptp_dev_attrs;
+ pr_info("PTP clock support registered\n");
+ return 0;
+
+no_region:
+ class_destroy(ptp_class);
+ return err;
+}
+
+subsys_initcall(ptp_init);
+module_exit(ptp_exit);
+
+MODULE_AUTHOR("Richard Cochran <richard.cochran@omicron.at>");
+MODULE_DESCRIPTION("PTP clocks support");
+MODULE_LICENSE("GPL");
diff --git a/drivers/ptp/ptp_ixp46x.c b/drivers/ptp/ptp_ixp46x.c
new file mode 100644
index 0000000..803d665
--- /dev/null
+++ b/drivers/ptp/ptp_ixp46x.c
@@ -0,0 +1,332 @@
+/*
+ * PTP 1588 clock using the IXP46X
+ *
+ * Copyright (C) 2010 OMICRON electronics GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/gpio.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+
+#include <linux/ptp_clock_kernel.h>
+#include <mach/ixp46x_ts.h>
+
+#define DRIVER "ptp_ixp46x"
+#define N_EXT_TS 2
+#define MASTER_GPIO 8
+#define MASTER_IRQ 25
+#define SLAVE_GPIO 7
+#define SLAVE_IRQ 24
+
+struct ixp_clock {
+ struct ixp46x_ts_regs *regs;
+ struct ptp_clock *ptp_clock;
+ struct ptp_clock_info caps;
+ int exts0_enabled;
+ int exts1_enabled;
+};
+
+DEFINE_SPINLOCK(register_lock);
+
+/*
+ * Register access functions
+ */
+
+static u64 ixp_systime_read(struct ixp46x_ts_regs *regs)
+{
+ u64 ns;
+ u32 lo, hi;
+
+ lo = __raw_readl(®s->systime_lo);
+ hi = __raw_readl(®s->systime_hi);
+
+ ns = ((u64) hi) << 32;
+ ns |= lo;
+ ns <<= TICKS_NS_SHIFT;
+
+ return ns;
+}
+
+static void ixp_systime_write(struct ixp46x_ts_regs *regs, u64 ns)
+{
+ u32 hi, lo;
+
+ ns >>= TICKS_NS_SHIFT;
+ hi = ns >> 32;
+ lo = ns & 0xffffffff;
+
+ __raw_writel(lo, ®s->systime_lo);
+ __raw_writel(hi, ®s->systime_hi);
+}
+
+/*
+ * Interrupt service routine
+ */
+
+static irqreturn_t isr(int irq, void *priv)
+{
+ struct ixp_clock *ixp_clock = priv;
+ struct ixp46x_ts_regs *regs = ixp_clock->regs;
+ struct ptp_clock_event event;
+ u32 ack = 0, lo, hi, val;
+
+ val = __raw_readl(®s->event);
+
+ if (val & TSER_SNS) {
+ ack |= TSER_SNS;
+ if (ixp_clock->exts0_enabled) {
+ hi = __raw_readl(®s->asms_hi);
+ lo = __raw_readl(®s->asms_lo);
+ event.type = PTP_CLOCK_EXTTS;
+ event.index = 0;
+ event.timestamp = ((u64) hi) << 32;
+ event.timestamp |= lo;
+ event.timestamp <<= TICKS_NS_SHIFT;
+ ptp_clock_event(ixp_clock->ptp_clock, &event);
+ }
+ }
+
+ if (val & TSER_SNM) {
+ ack |= TSER_SNM;
+ if (ixp_clock->exts1_enabled) {
+ hi = __raw_readl(®s->amms_hi);
+ lo = __raw_readl(®s->amms_lo);
+ event.type = PTP_CLOCK_EXTTS;
+ event.index = 1;
+ event.timestamp = ((u64) hi) << 32;
+ event.timestamp |= lo;
+ event.timestamp <<= TICKS_NS_SHIFT;
+ ptp_clock_event(ixp_clock->ptp_clock, &event);
+ }
+ }
+
+ if (val & TTIPEND)
+ ack |= TTIPEND; /* this bit seems to be always set */
+
+ if (ack) {
+ __raw_writel(ack, ®s->event);
+ return IRQ_HANDLED;
+ } else
+ return IRQ_NONE;
+}
+
+/*
+ * PTP clock operations
+ */
+
+static int ptp_ixp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
+{
+ u64 adj;
+ u32 diff, addend;
+ int neg_adj = 0;
+ struct ixp_clock *ixp_clock = container_of(ptp, struct ixp_clock, caps);
+ struct ixp46x_ts_regs *regs = ixp_clock->regs;
+
+ if (ppb < 0) {
+ neg_adj = 1;
+ ppb = -ppb;
+ }
+ addend = DEFAULT_ADDEND;
+ adj = addend;
+ adj *= ppb;
+ diff = div_u64(adj, 1000000000ULL);
+
+ addend = neg_adj ? addend - diff : addend + diff;
+
+ __raw_writel(addend, ®s->addend);
+
+ return 0;
+}
+
+static int ptp_ixp_adjtime(struct ptp_clock_info *ptp, s64 delta)
+{
+ s64 now;
+ unsigned long flags;
+ struct ixp_clock *ixp_clock = container_of(ptp, struct ixp_clock, caps);
+ struct ixp46x_ts_regs *regs = ixp_clock->regs;
+
+ spin_lock_irqsave(®ister_lock, flags);
+
+ now = ixp_systime_read(regs);
+ now += delta;
+ ixp_systime_write(regs, now);
+
+ spin_unlock_irqrestore(®ister_lock, flags);
+
+ return 0;
+}
+
+static int ptp_ixp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
+{
+ u64 ns;
+ u32 remainder;
+ unsigned long flags;
+ struct ixp_clock *ixp_clock = container_of(ptp, struct ixp_clock, caps);
+ struct ixp46x_ts_regs *regs = ixp_clock->regs;
+
+ spin_lock_irqsave(®ister_lock, flags);
+
+ ns = ixp_systime_read(regs);
+
+ spin_unlock_irqrestore(®ister_lock, flags);
+
+ ts->tv_sec = div_u64_rem(ns, 1000000000, &remainder);
+ ts->tv_nsec = remainder;
+ return 0;
+}
+
+static int ptp_ixp_settime(struct ptp_clock_info *ptp,
+ const struct timespec *ts)
+{
+ u64 ns;
+ unsigned long flags;
+ struct ixp_clock *ixp_clock = container_of(ptp, struct ixp_clock, caps);
+ struct ixp46x_ts_regs *regs = ixp_clock->regs;
+
+ ns = ts->tv_sec * 1000000000ULL;
+ ns += ts->tv_nsec;
+
+ spin_lock_irqsave(®ister_lock, flags);
+
+ ixp_systime_write(regs, ns);
+
+ spin_unlock_irqrestore(®ister_lock, flags);
+
+ return 0;
+}
+
+static int ptp_ixp_enable(struct ptp_clock_info *ptp,
+ struct ptp_clock_request *rq, int on)
+{
+ struct ixp_clock *ixp_clock = container_of(ptp, struct ixp_clock, caps);
+
+ switch (rq->type) {
+ case PTP_CLK_REQ_EXTTS:
+ switch (rq->extts.index) {
+ case 0:
+ ixp_clock->exts0_enabled = on ? 1 : 0;
+ break;
+ case 1:
+ ixp_clock->exts1_enabled = on ? 1 : 0;
+ break;
+ default:
+ return -EINVAL;
+ }
+ return 0;
+ default:
+ break;
+ }
+
+ return -EOPNOTSUPP;
+}
+
+static struct ptp_clock_info ptp_ixp_caps = {
+ .owner = THIS_MODULE,
+ .name = "IXP46X timer",
+ .max_adj = 66666655,
+ .n_ext_ts = N_EXT_TS,
+ .pps = 0,
+ .adjfreq = ptp_ixp_adjfreq,
+ .adjtime = ptp_ixp_adjtime,
+ .gettime = ptp_ixp_gettime,
+ .settime = ptp_ixp_settime,
+ .enable = ptp_ixp_enable,
+};
+
+/* module operations */
+
+static struct ixp_clock ixp_clock;
+
+static int setup_interrupt(int gpio)
+{
+ int irq;
+
+ gpio_line_config(gpio, IXP4XX_GPIO_IN);
+
+ irq = gpio_to_irq(gpio);
+
+ if (NO_IRQ == irq)
+ return NO_IRQ;
+
+ if (irq_set_irq_type(irq, IRQF_TRIGGER_FALLING)) {
+ pr_err("cannot set trigger type for irq %d\n", irq);
+ return NO_IRQ;
+ }
+
+ if (request_irq(irq, isr, 0, DRIVER, &ixp_clock)) {
+ pr_err("request_irq failed for irq %d\n", irq);
+ return NO_IRQ;
+ }
+
+ return irq;
+}
+
+static void __exit ptp_ixp_exit(void)
+{
+ free_irq(MASTER_IRQ, &ixp_clock);
+ free_irq(SLAVE_IRQ, &ixp_clock);
+ ptp_clock_unregister(ixp_clock.ptp_clock);
+}
+
+static int __init ptp_ixp_init(void)
+{
+ if (!cpu_is_ixp46x())
+ return -ENODEV;
+
+ ixp_clock.regs =
+ (struct ixp46x_ts_regs __iomem *) IXP4XX_TIMESYNC_BASE_VIRT;
+
+ ixp_clock.caps = ptp_ixp_caps;
+
+ ixp_clock.ptp_clock = ptp_clock_register(&ixp_clock.caps);
+
+ if (IS_ERR(ixp_clock.ptp_clock))
+ return PTR_ERR(ixp_clock.ptp_clock);
+
+ __raw_writel(DEFAULT_ADDEND, &ixp_clock.regs->addend);
+ __raw_writel(1, &ixp_clock.regs->trgt_lo);
+ __raw_writel(0, &ixp_clock.regs->trgt_hi);
+ __raw_writel(TTIPEND, &ixp_clock.regs->event);
+
+ if (MASTER_IRQ != setup_interrupt(MASTER_GPIO)) {
+ pr_err("failed to setup gpio %d as irq\n", MASTER_GPIO);
+ goto no_master;
+ }
+ if (SLAVE_IRQ != setup_interrupt(SLAVE_GPIO)) {
+ pr_err("failed to setup gpio %d as irq\n", SLAVE_GPIO);
+ goto no_slave;
+ }
+
+ return 0;
+no_slave:
+ free_irq(MASTER_IRQ, &ixp_clock);
+no_master:
+ ptp_clock_unregister(ixp_clock.ptp_clock);
+ return -ENODEV;
+}
+
+module_init(ptp_ixp_init);
+module_exit(ptp_ixp_exit);
+
+MODULE_AUTHOR("Richard Cochran <richard.cochran@omicron.at>");
+MODULE_DESCRIPTION("PTP clock using the IXP46X timer");
+MODULE_LICENSE("GPL");
diff --git a/drivers/ptp/ptp_private.h b/drivers/ptp/ptp_private.h
new file mode 100644
index 0000000..4d5b508
--- /dev/null
+++ b/drivers/ptp/ptp_private.h
@@ -0,0 +1,92 @@
+/*
+ * PTP 1588 clock support - private declarations for the core module.
+ *
+ * Copyright (C) 2010 OMICRON electronics GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#ifndef _PTP_PRIVATE_H_
+#define _PTP_PRIVATE_H_
+
+#include <linux/cdev.h>
+#include <linux/device.h>
+#include <linux/mutex.h>
+#include <linux/posix-clock.h>
+#include <linux/ptp_clock.h>
+#include <linux/ptp_clock_kernel.h>
+#include <linux/time.h>
+
+#define PTP_MAX_TIMESTAMPS 128
+#define PTP_BUF_TIMESTAMPS 30
+
+struct timestamp_event_queue {
+ struct ptp_extts_event buf[PTP_MAX_TIMESTAMPS];
+ int head;
+ int tail;
+ spinlock_t lock;
+};
+
+struct ptp_clock {
+ struct posix_clock clock;
+ struct device *dev;
+ struct ptp_clock_info *info;
+ dev_t devid;
+ int index; /* index into clocks.map */
+ struct pps_device *pps_source;
+ struct timestamp_event_queue tsevq; /* simple fifo for time stamps */
+ struct mutex tsevq_mux; /* one process at a time reading the fifo */
+ wait_queue_head_t tsev_wq;
+ int defunct; /* tells readers to go away when clock is being removed */
+};
+
+/*
+ * The function queue_cnt() is safe for readers to call without
+ * holding q->lock. Readers use this function to verify that the queue
+ * is nonempty before proceeding with a dequeue operation. The fact
+ * that a writer might concurrently increment the tail does not
+ * matter, since the queue remains nonempty nonetheless.
+ */
+static inline int queue_cnt(struct timestamp_event_queue *q)
+{
+ int cnt = q->tail - q->head;
+ return cnt < 0 ? PTP_MAX_TIMESTAMPS + cnt : cnt;
+}
+
+/*
+ * see ptp_chardev.c
+ */
+
+long ptp_ioctl(struct posix_clock *pc,
+ unsigned int cmd, unsigned long arg);
+
+int ptp_open(struct posix_clock *pc, fmode_t fmode);
+
+ssize_t ptp_read(struct posix_clock *pc,
+ uint flags, char __user *buf, size_t cnt);
+
+uint ptp_poll(struct posix_clock *pc,
+ struct file *fp, poll_table *wait);
+
+/*
+ * see ptp_sysfs.c
+ */
+
+extern struct device_attribute ptp_dev_attrs[];
+
+int ptp_cleanup_sysfs(struct ptp_clock *ptp);
+
+int ptp_populate_sysfs(struct ptp_clock *ptp);
+
+#endif
diff --git a/drivers/ptp/ptp_sysfs.c b/drivers/ptp/ptp_sysfs.c
new file mode 100644
index 0000000..2f93926
--- /dev/null
+++ b/drivers/ptp/ptp_sysfs.c
@@ -0,0 +1,230 @@
+/*
+ * PTP 1588 clock support - sysfs interface.
+ *
+ * Copyright (C) 2010 OMICRON electronics GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/capability.h>
+
+#include "ptp_private.h"
+
+static ssize_t clock_name_show(struct device *dev,
+ struct device_attribute *attr, char *page)
+{
+ struct ptp_clock *ptp = dev_get_drvdata(dev);
+ return snprintf(page, PAGE_SIZE-1, "%s\n", ptp->info->name);
+}
+
+#define PTP_SHOW_INT(name) \
+static ssize_t name##_show(struct device *dev, \
+ struct device_attribute *attr, char *page) \
+{ \
+ struct ptp_clock *ptp = dev_get_drvdata(dev); \
+ return snprintf(page, PAGE_SIZE-1, "%d\n", ptp->info->name); \
+}
+
+PTP_SHOW_INT(max_adj);
+PTP_SHOW_INT(n_alarm);
+PTP_SHOW_INT(n_ext_ts);
+PTP_SHOW_INT(n_per_out);
+PTP_SHOW_INT(pps);
+
+#define PTP_RO_ATTR(_var, _name) { \
+ .attr = { .name = __stringify(_name), .mode = 0444 }, \
+ .show = _var##_show, \
+}
+
+struct device_attribute ptp_dev_attrs[] = {
+ PTP_RO_ATTR(clock_name, clock_name),
+ PTP_RO_ATTR(max_adj, max_adjustment),
+ PTP_RO_ATTR(n_alarm, n_alarms),
+ PTP_RO_ATTR(n_ext_ts, n_external_timestamps),
+ PTP_RO_ATTR(n_per_out, n_periodic_outputs),
+ PTP_RO_ATTR(pps, pps_available),
+ __ATTR_NULL,
+};
+
+static ssize_t extts_enable_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct ptp_clock *ptp = dev_get_drvdata(dev);
+ struct ptp_clock_info *ops = ptp->info;
+ struct ptp_clock_request req = { .type = PTP_CLK_REQ_EXTTS };
+ int cnt, enable;
+ int err = -EINVAL;
+
+ cnt = sscanf(buf, "%u %d", &req.extts.index, &enable);
+ if (cnt != 2)
+ goto out;
+ if (req.extts.index >= ops->n_ext_ts)
+ goto out;
+
+ err = ops->enable(ops, &req, enable ? 1 : 0);
+ if (err)
+ goto out;
+
+ return count;
+out:
+ return err;
+}
+
+static ssize_t extts_fifo_show(struct device *dev,
+ struct device_attribute *attr, char *page)
+{
+ struct ptp_clock *ptp = dev_get_drvdata(dev);
+ struct timestamp_event_queue *queue = &ptp->tsevq;
+ struct ptp_extts_event event;
+ unsigned long flags;
+ size_t qcnt;
+ int cnt = 0;
+
+ memset(&event, 0, sizeof(event));
+
+ if (mutex_lock_interruptible(&ptp->tsevq_mux))
+ return -ERESTARTSYS;
+
+ spin_lock_irqsave(&queue->lock, flags);
+ qcnt = queue_cnt(queue);
+ if (qcnt) {
+ event = queue->buf[queue->head];
+ queue->head = (queue->head + 1) % PTP_MAX_TIMESTAMPS;
+ }
+ spin_unlock_irqrestore(&queue->lock, flags);
+
+ if (!qcnt)
+ goto out;
+
+ cnt = snprintf(page, PAGE_SIZE, "%u %lld %u\n",
+ event.index, event.t.sec, event.t.nsec);
+out:
+ mutex_unlock(&ptp->tsevq_mux);
+ return cnt;
+}
+
+static ssize_t period_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct ptp_clock *ptp = dev_get_drvdata(dev);
+ struct ptp_clock_info *ops = ptp->info;
+ struct ptp_clock_request req = { .type = PTP_CLK_REQ_PEROUT };
+ int cnt, enable, err = -EINVAL;
+
+ cnt = sscanf(buf, "%u %lld %u %lld %u", &req.perout.index,
+ &req.perout.start.sec, &req.perout.start.nsec,
+ &req.perout.period.sec, &req.perout.period.nsec);
+ if (cnt != 5)
+ goto out;
+ if (req.perout.index >= ops->n_per_out)
+ goto out;
+
+ enable = req.perout.period.sec || req.perout.period.nsec;
+ err = ops->enable(ops, &req, enable);
+ if (err)
+ goto out;
+
+ return count;
+out:
+ return err;
+}
+
+static ssize_t pps_enable_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct ptp_clock *ptp = dev_get_drvdata(dev);
+ struct ptp_clock_info *ops = ptp->info;
+ struct ptp_clock_request req = { .type = PTP_CLK_REQ_PPS };
+ int cnt, enable;
+ int err = -EINVAL;
+
+ if (!capable(CAP_SYS_TIME))
+ return -EPERM;
+
+ cnt = sscanf(buf, "%d", &enable);
+ if (cnt != 1)
+ goto out;
+
+ err = ops->enable(ops, &req, enable ? 1 : 0);
+ if (err)
+ goto out;
+
+ return count;
+out:
+ return err;
+}
+
+static DEVICE_ATTR(extts_enable, 0220, NULL, extts_enable_store);
+static DEVICE_ATTR(fifo, 0444, extts_fifo_show, NULL);
+static DEVICE_ATTR(period, 0220, NULL, period_store);
+static DEVICE_ATTR(pps_enable, 0220, NULL, pps_enable_store);
+
+int ptp_cleanup_sysfs(struct ptp_clock *ptp)
+{
+ struct device *dev = ptp->dev;
+ struct ptp_clock_info *info = ptp->info;
+
+ if (info->n_ext_ts) {
+ device_remove_file(dev, &dev_attr_extts_enable);
+ device_remove_file(dev, &dev_attr_fifo);
+ }
+ if (info->n_per_out)
+ device_remove_file(dev, &dev_attr_period);
+
+ if (info->pps)
+ device_remove_file(dev, &dev_attr_pps_enable);
+
+ return 0;
+}
+
+int ptp_populate_sysfs(struct ptp_clock *ptp)
+{
+ struct device *dev = ptp->dev;
+ struct ptp_clock_info *info = ptp->info;
+ int err;
+
+ if (info->n_ext_ts) {
+ err = device_create_file(dev, &dev_attr_extts_enable);
+ if (err)
+ goto out1;
+ err = device_create_file(dev, &dev_attr_fifo);
+ if (err)
+ goto out2;
+ }
+ if (info->n_per_out) {
+ err = device_create_file(dev, &dev_attr_period);
+ if (err)
+ goto out3;
+ }
+ if (info->pps) {
+ err = device_create_file(dev, &dev_attr_pps_enable);
+ if (err)
+ goto out4;
+ }
+ return 0;
+out4:
+ if (info->n_per_out)
+ device_remove_file(dev, &dev_attr_period);
+out3:
+ if (info->n_ext_ts)
+ device_remove_file(dev, &dev_attr_fifo);
+out2:
+ if (info->n_ext_ts)
+ device_remove_file(dev, &dev_attr_extts_enable);
+out1:
+ return err;
+}
diff --git a/drivers/regulator/Kconfig b/drivers/regulator/Kconfig
index b9f29e0..f0b13a0 100644
--- a/drivers/regulator/Kconfig
+++ b/drivers/regulator/Kconfig
@@ -274,6 +274,13 @@
This driver supports the regulators found on the ST-Ericsson mixed
signal AB8500 PMIC
+config REGULATOR_DB8500_PRCMU
+ bool "ST-Ericsson DB8500 Voltage Domain Regulators"
+ depends on MFD_DB8500_PRCMU
+ help
+ This driver supports the voltage domain regulators controlled by the
+ DB8500 PRCMU
+
config REGULATOR_TPS6586X
tristate "TI TPS6586X Power regulators"
depends on MFD_TPS6586X
diff --git a/drivers/regulator/Makefile b/drivers/regulator/Makefile
index d72a427..165ff53 100644
--- a/drivers/regulator/Makefile
+++ b/drivers/regulator/Makefile
@@ -41,5 +41,6 @@
obj-$(CONFIG_REGULATOR_88PM8607) += 88pm8607.o
obj-$(CONFIG_REGULATOR_ISL6271A) += isl6271a-regulator.o
obj-$(CONFIG_REGULATOR_AB8500) += ab8500.o
+obj-$(CONFIG_REGULATOR_DB8500_PRCMU) += db8500-prcmu.o
ccflags-$(CONFIG_REGULATOR_DEBUG) += -DDEBUG
diff --git a/drivers/regulator/db8500-prcmu.c b/drivers/regulator/db8500-prcmu.c
new file mode 100644
index 0000000..1089a96
--- /dev/null
+++ b/drivers/regulator/db8500-prcmu.c
@@ -0,0 +1,558 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * License Terms: GNU General Public License v2
+ * Authors: Sundar Iyer <sundar.iyer@stericsson.com> for ST-Ericsson
+ * Bengt Jonsson <bengt.g.jonsson@stericsson.com> for ST-Ericsson
+ *
+ * Power domain regulators on DB8500
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/err.h>
+#include <linux/spinlock.h>
+#include <linux/platform_device.h>
+#include <linux/mfd/core.h>
+#include <linux/mfd/db8500-prcmu.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/machine.h>
+#include <linux/regulator/db8500-prcmu.h>
+
+/*
+ * power state reference count
+ */
+static int power_state_active_cnt; /* will initialize to zero */
+static DEFINE_SPINLOCK(power_state_active_lock);
+
+static void power_state_active_enable(void)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&power_state_active_lock, flags);
+ power_state_active_cnt++;
+ spin_unlock_irqrestore(&power_state_active_lock, flags);
+}
+
+static int power_state_active_disable(void)
+{
+ int ret = 0;
+ unsigned long flags;
+
+ spin_lock_irqsave(&power_state_active_lock, flags);
+ if (power_state_active_cnt <= 0) {
+ pr_err("power state: unbalanced enable/disable calls\n");
+ ret = -EINVAL;
+ goto out;
+ }
+
+ power_state_active_cnt--;
+out:
+ spin_unlock_irqrestore(&power_state_active_lock, flags);
+ return ret;
+}
+
+/*
+ * Exported interface for CPUIdle only. This function is called when interrupts
+ * are turned off. Hence, no locking.
+ */
+int power_state_active_is_enabled(void)
+{
+ return (power_state_active_cnt > 0);
+}
+
+/**
+ * struct db8500_regulator_info - db8500 regulator information
+ * @dev: device pointer
+ * @desc: regulator description
+ * @rdev: regulator device pointer
+ * @is_enabled: status of the regulator
+ * @epod_id: id for EPOD (power domain)
+ * @is_ramret: RAM retention switch for EPOD (power domain)
+ * @operating_point: operating point (only for vape, to be removed)
+ *
+ */
+struct db8500_regulator_info {
+ struct device *dev;
+ struct regulator_desc desc;
+ struct regulator_dev *rdev;
+ bool is_enabled;
+ u16 epod_id;
+ bool is_ramret;
+ bool exclude_from_power_state;
+ unsigned int operating_point;
+};
+
+static int db8500_regulator_enable(struct regulator_dev *rdev)
+{
+ struct db8500_regulator_info *info = rdev_get_drvdata(rdev);
+
+ if (info == NULL)
+ return -EINVAL;
+
+ dev_vdbg(rdev_get_dev(rdev), "regulator-%s-enable\n",
+ info->desc.name);
+
+ info->is_enabled = true;
+ if (!info->exclude_from_power_state)
+ power_state_active_enable();
+
+ return 0;
+}
+
+static int db8500_regulator_disable(struct regulator_dev *rdev)
+{
+ struct db8500_regulator_info *info = rdev_get_drvdata(rdev);
+ int ret = 0;
+
+ if (info == NULL)
+ return -EINVAL;
+
+ dev_vdbg(rdev_get_dev(rdev), "regulator-%s-disable\n",
+ info->desc.name);
+
+ info->is_enabled = false;
+ if (!info->exclude_from_power_state)
+ ret = power_state_active_disable();
+
+ return ret;
+}
+
+static int db8500_regulator_is_enabled(struct regulator_dev *rdev)
+{
+ struct db8500_regulator_info *info = rdev_get_drvdata(rdev);
+
+ if (info == NULL)
+ return -EINVAL;
+
+ dev_vdbg(rdev_get_dev(rdev), "regulator-%s-is_enabled (is_enabled):"
+ " %i\n", info->desc.name, info->is_enabled);
+
+ return info->is_enabled;
+}
+
+/* db8500 regulator operations */
+static struct regulator_ops db8500_regulator_ops = {
+ .enable = db8500_regulator_enable,
+ .disable = db8500_regulator_disable,
+ .is_enabled = db8500_regulator_is_enabled,
+};
+
+/*
+ * EPOD control
+ */
+static bool epod_on[NUM_EPOD_ID];
+static bool epod_ramret[NUM_EPOD_ID];
+
+static int enable_epod(u16 epod_id, bool ramret)
+{
+ int ret;
+
+ if (ramret) {
+ if (!epod_on[epod_id]) {
+ ret = prcmu_set_epod(epod_id, EPOD_STATE_RAMRET);
+ if (ret < 0)
+ return ret;
+ }
+ epod_ramret[epod_id] = true;
+ } else {
+ ret = prcmu_set_epod(epod_id, EPOD_STATE_ON);
+ if (ret < 0)
+ return ret;
+ epod_on[epod_id] = true;
+ }
+
+ return 0;
+}
+
+static int disable_epod(u16 epod_id, bool ramret)
+{
+ int ret;
+
+ if (ramret) {
+ if (!epod_on[epod_id]) {
+ ret = prcmu_set_epod(epod_id, EPOD_STATE_OFF);
+ if (ret < 0)
+ return ret;
+ }
+ epod_ramret[epod_id] = false;
+ } else {
+ if (epod_ramret[epod_id]) {
+ ret = prcmu_set_epod(epod_id, EPOD_STATE_RAMRET);
+ if (ret < 0)
+ return ret;
+ } else {
+ ret = prcmu_set_epod(epod_id, EPOD_STATE_OFF);
+ if (ret < 0)
+ return ret;
+ }
+ epod_on[epod_id] = false;
+ }
+
+ return 0;
+}
+
+/*
+ * Regulator switch
+ */
+static int db8500_regulator_switch_enable(struct regulator_dev *rdev)
+{
+ struct db8500_regulator_info *info = rdev_get_drvdata(rdev);
+ int ret;
+
+ if (info == NULL)
+ return -EINVAL;
+
+ dev_vdbg(rdev_get_dev(rdev), "regulator-switch-%s-enable\n",
+ info->desc.name);
+
+ ret = enable_epod(info->epod_id, info->is_ramret);
+ if (ret < 0) {
+ dev_err(rdev_get_dev(rdev),
+ "regulator-switch-%s-enable: prcmu call failed\n",
+ info->desc.name);
+ goto out;
+ }
+
+ info->is_enabled = true;
+out:
+ return ret;
+}
+
+static int db8500_regulator_switch_disable(struct regulator_dev *rdev)
+{
+ struct db8500_regulator_info *info = rdev_get_drvdata(rdev);
+ int ret;
+
+ if (info == NULL)
+ return -EINVAL;
+
+ dev_vdbg(rdev_get_dev(rdev), "regulator-switch-%s-disable\n",
+ info->desc.name);
+
+ ret = disable_epod(info->epod_id, info->is_ramret);
+ if (ret < 0) {
+ dev_err(rdev_get_dev(rdev),
+ "regulator_switch-%s-disable: prcmu call failed\n",
+ info->desc.name);
+ goto out;
+ }
+
+ info->is_enabled = 0;
+out:
+ return ret;
+}
+
+static int db8500_regulator_switch_is_enabled(struct regulator_dev *rdev)
+{
+ struct db8500_regulator_info *info = rdev_get_drvdata(rdev);
+
+ if (info == NULL)
+ return -EINVAL;
+
+ dev_vdbg(rdev_get_dev(rdev),
+ "regulator-switch-%s-is_enabled (is_enabled): %i\n",
+ info->desc.name, info->is_enabled);
+
+ return info->is_enabled;
+}
+
+static struct regulator_ops db8500_regulator_switch_ops = {
+ .enable = db8500_regulator_switch_enable,
+ .disable = db8500_regulator_switch_disable,
+ .is_enabled = db8500_regulator_switch_is_enabled,
+};
+
+/*
+ * Regulator information
+ */
+static struct db8500_regulator_info
+ db8500_regulator_info[DB8500_NUM_REGULATORS] = {
+ [DB8500_REGULATOR_VAPE] = {
+ .desc = {
+ .name = "db8500-vape",
+ .id = DB8500_REGULATOR_VAPE,
+ .ops = &db8500_regulator_ops,
+ .type = REGULATOR_VOLTAGE,
+ .owner = THIS_MODULE,
+ },
+ },
+ [DB8500_REGULATOR_VARM] = {
+ .desc = {
+ .name = "db8500-varm",
+ .id = DB8500_REGULATOR_VARM,
+ .ops = &db8500_regulator_ops,
+ .type = REGULATOR_VOLTAGE,
+ .owner = THIS_MODULE,
+ },
+ },
+ [DB8500_REGULATOR_VMODEM] = {
+ .desc = {
+ .name = "db8500-vmodem",
+ .id = DB8500_REGULATOR_VMODEM,
+ .ops = &db8500_regulator_ops,
+ .type = REGULATOR_VOLTAGE,
+ .owner = THIS_MODULE,
+ },
+ },
+ [DB8500_REGULATOR_VPLL] = {
+ .desc = {
+ .name = "db8500-vpll",
+ .id = DB8500_REGULATOR_VPLL,
+ .ops = &db8500_regulator_ops,
+ .type = REGULATOR_VOLTAGE,
+ .owner = THIS_MODULE,
+ },
+ },
+ [DB8500_REGULATOR_VSMPS1] = {
+ .desc = {
+ .name = "db8500-vsmps1",
+ .id = DB8500_REGULATOR_VSMPS1,
+ .ops = &db8500_regulator_ops,
+ .type = REGULATOR_VOLTAGE,
+ .owner = THIS_MODULE,
+ },
+ },
+ [DB8500_REGULATOR_VSMPS2] = {
+ .desc = {
+ .name = "db8500-vsmps2",
+ .id = DB8500_REGULATOR_VSMPS2,
+ .ops = &db8500_regulator_ops,
+ .type = REGULATOR_VOLTAGE,
+ .owner = THIS_MODULE,
+ },
+ .exclude_from_power_state = true,
+ },
+ [DB8500_REGULATOR_VSMPS3] = {
+ .desc = {
+ .name = "db8500-vsmps3",
+ .id = DB8500_REGULATOR_VSMPS3,
+ .ops = &db8500_regulator_ops,
+ .type = REGULATOR_VOLTAGE,
+ .owner = THIS_MODULE,
+ },
+ },
+ [DB8500_REGULATOR_VRF1] = {
+ .desc = {
+ .name = "db8500-vrf1",
+ .id = DB8500_REGULATOR_VRF1,
+ .ops = &db8500_regulator_ops,
+ .type = REGULATOR_VOLTAGE,
+ .owner = THIS_MODULE,
+ },
+ },
+ [DB8500_REGULATOR_SWITCH_SVAMMDSP] = {
+ .desc = {
+ .name = "db8500-sva-mmdsp",
+ .id = DB8500_REGULATOR_SWITCH_SVAMMDSP,
+ .ops = &db8500_regulator_switch_ops,
+ .type = REGULATOR_VOLTAGE,
+ .owner = THIS_MODULE,
+ },
+ .epod_id = EPOD_ID_SVAMMDSP,
+ },
+ [DB8500_REGULATOR_SWITCH_SVAMMDSPRET] = {
+ .desc = {
+ .name = "db8500-sva-mmdsp-ret",
+ .id = DB8500_REGULATOR_SWITCH_SVAMMDSPRET,
+ .ops = &db8500_regulator_switch_ops,
+ .type = REGULATOR_VOLTAGE,
+ .owner = THIS_MODULE,
+ },
+ .epod_id = EPOD_ID_SVAMMDSP,
+ .is_ramret = true,
+ },
+ [DB8500_REGULATOR_SWITCH_SVAPIPE] = {
+ .desc = {
+ .name = "db8500-sva-pipe",
+ .id = DB8500_REGULATOR_SWITCH_SVAPIPE,
+ .ops = &db8500_regulator_switch_ops,
+ .type = REGULATOR_VOLTAGE,
+ .owner = THIS_MODULE,
+ },
+ .epod_id = EPOD_ID_SVAPIPE,
+ },
+ [DB8500_REGULATOR_SWITCH_SIAMMDSP] = {
+ .desc = {
+ .name = "db8500-sia-mmdsp",
+ .id = DB8500_REGULATOR_SWITCH_SIAMMDSP,
+ .ops = &db8500_regulator_switch_ops,
+ .type = REGULATOR_VOLTAGE,
+ .owner = THIS_MODULE,
+ },
+ .epod_id = EPOD_ID_SIAMMDSP,
+ },
+ [DB8500_REGULATOR_SWITCH_SIAMMDSPRET] = {
+ .desc = {
+ .name = "db8500-sia-mmdsp-ret",
+ .id = DB8500_REGULATOR_SWITCH_SIAMMDSPRET,
+ .ops = &db8500_regulator_switch_ops,
+ .type = REGULATOR_VOLTAGE,
+ .owner = THIS_MODULE,
+ },
+ .epod_id = EPOD_ID_SIAMMDSP,
+ .is_ramret = true,
+ },
+ [DB8500_REGULATOR_SWITCH_SIAPIPE] = {
+ .desc = {
+ .name = "db8500-sia-pipe",
+ .id = DB8500_REGULATOR_SWITCH_SIAPIPE,
+ .ops = &db8500_regulator_switch_ops,
+ .type = REGULATOR_VOLTAGE,
+ .owner = THIS_MODULE,
+ },
+ .epod_id = EPOD_ID_SIAPIPE,
+ },
+ [DB8500_REGULATOR_SWITCH_SGA] = {
+ .desc = {
+ .name = "db8500-sga",
+ .id = DB8500_REGULATOR_SWITCH_SGA,
+ .ops = &db8500_regulator_switch_ops,
+ .type = REGULATOR_VOLTAGE,
+ .owner = THIS_MODULE,
+ },
+ .epod_id = EPOD_ID_SGA,
+ },
+ [DB8500_REGULATOR_SWITCH_B2R2_MCDE] = {
+ .desc = {
+ .name = "db8500-b2r2-mcde",
+ .id = DB8500_REGULATOR_SWITCH_B2R2_MCDE,
+ .ops = &db8500_regulator_switch_ops,
+ .type = REGULATOR_VOLTAGE,
+ .owner = THIS_MODULE,
+ },
+ .epod_id = EPOD_ID_B2R2_MCDE,
+ },
+ [DB8500_REGULATOR_SWITCH_ESRAM12] = {
+ .desc = {
+ .name = "db8500-esram12",
+ .id = DB8500_REGULATOR_SWITCH_ESRAM12,
+ .ops = &db8500_regulator_switch_ops,
+ .type = REGULATOR_VOLTAGE,
+ .owner = THIS_MODULE,
+ },
+ .epod_id = EPOD_ID_ESRAM12,
+ .is_enabled = true,
+ },
+ [DB8500_REGULATOR_SWITCH_ESRAM12RET] = {
+ .desc = {
+ .name = "db8500-esram12-ret",
+ .id = DB8500_REGULATOR_SWITCH_ESRAM12RET,
+ .ops = &db8500_regulator_switch_ops,
+ .type = REGULATOR_VOLTAGE,
+ .owner = THIS_MODULE,
+ },
+ .epod_id = EPOD_ID_ESRAM12,
+ .is_ramret = true,
+ },
+ [DB8500_REGULATOR_SWITCH_ESRAM34] = {
+ .desc = {
+ .name = "db8500-esram34",
+ .id = DB8500_REGULATOR_SWITCH_ESRAM34,
+ .ops = &db8500_regulator_switch_ops,
+ .type = REGULATOR_VOLTAGE,
+ .owner = THIS_MODULE,
+ },
+ .epod_id = EPOD_ID_ESRAM34,
+ .is_enabled = true,
+ },
+ [DB8500_REGULATOR_SWITCH_ESRAM34RET] = {
+ .desc = {
+ .name = "db8500-esram34-ret",
+ .id = DB8500_REGULATOR_SWITCH_ESRAM34RET,
+ .ops = &db8500_regulator_switch_ops,
+ .type = REGULATOR_VOLTAGE,
+ .owner = THIS_MODULE,
+ },
+ .epod_id = EPOD_ID_ESRAM34,
+ .is_ramret = true,
+ },
+};
+
+static int __devinit db8500_regulator_probe(struct platform_device *pdev)
+{
+ struct regulator_init_data *db8500_init_data = mfd_get_data(pdev);
+ int i, err;
+
+ /* register all regulators */
+ for (i = 0; i < ARRAY_SIZE(db8500_regulator_info); i++) {
+ struct db8500_regulator_info *info;
+ struct regulator_init_data *init_data = &db8500_init_data[i];
+
+ /* assign per-regulator data */
+ info = &db8500_regulator_info[i];
+ info->dev = &pdev->dev;
+
+ /* register with the regulator framework */
+ info->rdev = regulator_register(&info->desc, &pdev->dev,
+ init_data, info);
+ if (IS_ERR(info->rdev)) {
+ err = PTR_ERR(info->rdev);
+ dev_err(&pdev->dev, "failed to register %s: err %i\n",
+ info->desc.name, err);
+
+ /* if failing, unregister all earlier regulators */
+ i--;
+ while (i >= 0) {
+ info = &db8500_regulator_info[i];
+ regulator_unregister(info->rdev);
+ i--;
+ }
+ return err;
+ }
+
+ dev_dbg(rdev_get_dev(info->rdev),
+ "regulator-%s-probed\n", info->desc.name);
+ }
+
+ return 0;
+}
+
+static int __exit db8500_regulator_remove(struct platform_device *pdev)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(db8500_regulator_info); i++) {
+ struct db8500_regulator_info *info;
+ info = &db8500_regulator_info[i];
+
+ dev_vdbg(rdev_get_dev(info->rdev),
+ "regulator-%s-remove\n", info->desc.name);
+
+ regulator_unregister(info->rdev);
+ }
+
+ return 0;
+}
+
+static struct platform_driver db8500_regulator_driver = {
+ .driver = {
+ .name = "db8500-prcmu-regulators",
+ .owner = THIS_MODULE,
+ },
+ .probe = db8500_regulator_probe,
+ .remove = __exit_p(db8500_regulator_remove),
+};
+
+static int __init db8500_regulator_init(void)
+{
+ int ret;
+
+ ret = platform_driver_register(&db8500_regulator_driver);
+ if (ret < 0)
+ return -ENODEV;
+
+ return 0;
+}
+
+static void __exit db8500_regulator_exit(void)
+{
+ platform_driver_unregister(&db8500_regulator_driver);
+}
+
+arch_initcall(db8500_regulator_init);
+module_exit(db8500_regulator_exit);
+
+MODULE_AUTHOR("STMicroelectronics/ST-Ericsson");
+MODULE_DESCRIPTION("DB8500 regulator driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index 4289172..b8f4e9e 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -992,4 +992,11 @@
This drive can also be built as a module. If so, the module
will be called rtc-tegra.
+config RTC_DRV_TILE
+ tristate "Tilera hypervisor RTC support"
+ depends on TILE
+ help
+ Enable support for the Linux driver side of the Tilera
+ hypervisor's real-time clock interface.
+
endif # RTC_CLASS
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile
index ca91c3c..9574748 100644
--- a/drivers/rtc/Makefile
+++ b/drivers/rtc/Makefile
@@ -93,6 +93,7 @@
obj-$(CONFIG_RTC_DRV_SUN4V) += rtc-sun4v.o
obj-$(CONFIG_RTC_DRV_TEGRA) += rtc-tegra.o
obj-$(CONFIG_RTC_DRV_TEST) += rtc-test.o
+obj-$(CONFIG_RTC_DRV_TILE) += rtc-tile.o
obj-$(CONFIG_RTC_DRV_TWL4030) += rtc-twl.o
obj-$(CONFIG_RTC_DRV_TX4939) += rtc-tx4939.o
obj-$(CONFIG_RTC_DRV_V3020) += rtc-v3020.o
diff --git a/drivers/rtc/rtc-tile.c b/drivers/rtc/rtc-tile.c
new file mode 100644
index 0000000..eb65daf
--- /dev/null
+++ b/drivers/rtc/rtc-tile.c
@@ -0,0 +1,162 @@
+/*
+ * Copyright 2011 Tilera Corporation. All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation, version 2.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
+ * NON INFRINGEMENT. See the GNU General Public License for
+ * more details.
+ *
+ * Tilera-specific RTC driver.
+ */
+
+#include <linux/module.h>
+#include <linux/device.h>
+#include <linux/rtc.h>
+#include <linux/platform_device.h>
+
+/* Platform device pointer. */
+static struct platform_device *tile_rtc_platform_device;
+
+/*
+ * RTC read routine. Gets time info from RTC chip via hypervisor syscall.
+ */
+static int read_rtc_time(struct device *dev, struct rtc_time *tm)
+{
+ HV_RTCTime hvtm = hv_get_rtc();
+
+ tm->tm_sec = hvtm.tm_sec;
+ tm->tm_min = hvtm.tm_min;
+ tm->tm_hour = hvtm.tm_hour;
+ tm->tm_mday = hvtm.tm_mday;
+ tm->tm_mon = hvtm.tm_mon;
+ tm->tm_year = hvtm.tm_year;
+ tm->tm_wday = 0;
+ tm->tm_yday = 0;
+ tm->tm_isdst = 0;
+
+ if (rtc_valid_tm(tm) < 0)
+ dev_warn(dev, "Read invalid date/time from RTC\n");
+
+ return 0;
+}
+
+/*
+ * RTC write routine. Sends time info to hypervisor via syscall, to be
+ * written to RTC chip.
+ */
+static int set_rtc_time(struct device *dev, struct rtc_time *tm)
+{
+ HV_RTCTime hvtm;
+
+ hvtm.tm_sec = tm->tm_sec;
+ hvtm.tm_min = tm->tm_min;
+ hvtm.tm_hour = tm->tm_hour;
+ hvtm.tm_mday = tm->tm_mday;
+ hvtm.tm_mon = tm->tm_mon;
+ hvtm.tm_year = tm->tm_year;
+
+ hv_set_rtc(hvtm);
+
+ return 0;
+}
+
+/*
+ * RTC read/write ops.
+ */
+static const struct rtc_class_ops tile_rtc_ops = {
+ .read_time = read_rtc_time,
+ .set_time = set_rtc_time,
+};
+
+/*
+ * Device probe routine.
+ */
+static int __devinit tile_rtc_probe(struct platform_device *dev)
+{
+ struct rtc_device *rtc;
+
+ rtc = rtc_device_register("tile",
+ &dev->dev, &tile_rtc_ops, THIS_MODULE);
+
+ if (IS_ERR(rtc))
+ return PTR_ERR(rtc);
+
+ platform_set_drvdata(dev, rtc);
+
+ return 0;
+}
+
+/*
+ * Device cleanup routine.
+ */
+static int __devexit tile_rtc_remove(struct platform_device *dev)
+{
+ struct rtc_device *rtc = platform_get_drvdata(dev);
+
+ if (rtc)
+ rtc_device_unregister(rtc);
+
+ platform_set_drvdata(dev, NULL);
+
+ return 0;
+}
+
+static struct platform_driver tile_rtc_platform_driver = {
+ .driver = {
+ .name = "rtc-tile",
+ .owner = THIS_MODULE,
+ },
+ .probe = tile_rtc_probe,
+ .remove = __devexit_p(tile_rtc_remove),
+};
+
+/*
+ * Driver init routine.
+ */
+static int __init tile_rtc_driver_init(void)
+{
+ int err;
+
+ err = platform_driver_register(&tile_rtc_platform_driver);
+ if (err)
+ return err;
+
+ tile_rtc_platform_device = platform_device_alloc("rtc-tile", 0);
+ if (tile_rtc_platform_device == NULL) {
+ err = -ENOMEM;
+ goto exit_driver_unregister;
+ }
+
+ err = platform_device_add(tile_rtc_platform_device);
+ if (err)
+ goto exit_device_put;
+
+ return 0;
+
+exit_device_put:
+ platform_device_put(tile_rtc_platform_device);
+
+exit_driver_unregister:
+ platform_driver_unregister(&tile_rtc_platform_driver);
+ return err;
+}
+
+/*
+ * Driver cleanup routine.
+ */
+static void __exit tile_rtc_driver_exit(void)
+{
+ platform_driver_unregister(&tile_rtc_platform_driver);
+}
+
+module_init(tile_rtc_driver_init);
+module_exit(tile_rtc_driver_exit);
+
+MODULE_DESCRIPTION("Tilera-specific Real Time Clock Driver");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:rtc-tile");
diff --git a/drivers/s390/block/dasd_alias.c b/drivers/s390/block/dasd_alias.c
index 2b771f1..c388eda 100644
--- a/drivers/s390/block/dasd_alias.c
+++ b/drivers/s390/block/dasd_alias.c
@@ -253,13 +253,11 @@
*/
void dasd_alias_lcu_setup_complete(struct dasd_device *device)
{
- struct dasd_eckd_private *private;
unsigned long flags;
struct alias_server *server;
struct alias_lcu *lcu;
struct dasd_uid uid;
- private = (struct dasd_eckd_private *) device->private;
device->discipline->get_uid(device, &uid);
lcu = NULL;
spin_lock_irqsave(&aliastree.lock, flags);
@@ -279,13 +277,11 @@
void dasd_alias_wait_for_lcu_setup(struct dasd_device *device)
{
- struct dasd_eckd_private *private;
unsigned long flags;
struct alias_server *server;
struct alias_lcu *lcu;
struct dasd_uid uid;
- private = (struct dasd_eckd_private *) device->private;
device->discipline->get_uid(device, &uid);
lcu = NULL;
spin_lock_irqsave(&aliastree.lock, flags);
diff --git a/drivers/s390/block/dasd_eckd.c b/drivers/s390/block/dasd_eckd.c
index 3ebdf5f..30fb979 100644
--- a/drivers/s390/block/dasd_eckd.c
+++ b/drivers/s390/block/dasd_eckd.c
@@ -1611,10 +1611,8 @@
static int dasd_eckd_start_analysis(struct dasd_block *block)
{
- struct dasd_eckd_private *private;
struct dasd_ccw_req *init_cqr;
- private = (struct dasd_eckd_private *) block->base->private;
init_cqr = dasd_eckd_analysis_ccw(block->base);
if (IS_ERR(init_cqr))
return PTR_ERR(init_cqr);
@@ -2264,7 +2262,6 @@
unsigned int blk_per_trk,
unsigned int blksize)
{
- struct dasd_eckd_private *private;
unsigned long *idaws;
struct dasd_ccw_req *cqr;
struct ccw1 *ccw;
@@ -2283,7 +2280,6 @@
unsigned int recoffs;
basedev = block->base;
- private = (struct dasd_eckd_private *) basedev->private;
if (rq_data_dir(req) == READ)
cmd = DASD_ECKD_CCW_READ_TRACK_DATA;
else if (rq_data_dir(req) == WRITE)
@@ -2556,8 +2552,7 @@
dcw = itcw_add_dcw(itcw, pfx_cmd, 0,
&pfxdata, sizeof(pfxdata), total_data_size);
-
- return rc;
+ return IS_ERR(dcw) ? PTR_ERR(dcw) : 0;
}
static struct dasd_ccw_req *dasd_eckd_build_cp_tpm_track(
@@ -2573,7 +2568,6 @@
unsigned int blk_per_trk,
unsigned int blksize)
{
- struct dasd_eckd_private *private;
struct dasd_ccw_req *cqr;
struct req_iterator iter;
struct bio_vec *bv;
@@ -2594,7 +2588,6 @@
unsigned int count, count_to_trk_end;
basedev = block->base;
- private = (struct dasd_eckd_private *) basedev->private;
if (rq_data_dir(req) == READ) {
cmd = DASD_ECKD_CCW_READ_TRACK_DATA;
itcw_op = ITCW_OP_READ;
@@ -2801,7 +2794,6 @@
struct dasd_block *block,
struct request *req)
{
- struct dasd_eckd_private *private;
unsigned long *idaws;
struct dasd_device *basedev;
struct dasd_ccw_req *cqr;
@@ -2836,7 +2828,6 @@
trkcount = last_trk - first_trk + 1;
first_offs = 0;
basedev = block->base;
- private = (struct dasd_eckd_private *) basedev->private;
if (rq_data_dir(req) == READ)
cmd = DASD_ECKD_CCW_READ_TRACK;
diff --git a/drivers/s390/char/Kconfig b/drivers/s390/char/Kconfig
index dcee3c5..a4f117d 100644
--- a/drivers/s390/char/Kconfig
+++ b/drivers/s390/char/Kconfig
@@ -119,18 +119,6 @@
comment "S/390 tape interface support"
depends on S390_TAPE
-config S390_TAPE_BLOCK
- def_bool y
- prompt "Support for tape block devices"
- depends on S390_TAPE && BLOCK
- help
- Select this option if you want to access your channel-attached tape
- devices using the block device interface. This interface is similar
- to CD-ROM devices on other platforms. The tapes can only be
- accessed read-only when using this interface. Have a look at
- <file:Documentation/s390/TAPE> for further information about creating
- volumes for and using this interface. It is safe to say "Y" here.
-
comment "S/390 tape hardware support"
depends on S390_TAPE
diff --git a/drivers/s390/char/Makefile b/drivers/s390/char/Makefile
index efb500a..f3c3252 100644
--- a/drivers/s390/char/Makefile
+++ b/drivers/s390/char/Makefile
@@ -3,7 +3,7 @@
#
obj-y += ctrlchar.o keyboard.o defkeymap.o sclp.o sclp_rw.o sclp_quiesce.o \
- sclp_cmd.o sclp_config.o sclp_cpi_sys.o
+ sclp_cmd.o sclp_config.o sclp_cpi_sys.o sclp_ocf.o
obj-$(CONFIG_TN3270) += raw3270.o
obj-$(CONFIG_TN3270_CONSOLE) += con3270.o
@@ -22,7 +22,6 @@
obj-$(CONFIG_VMLOGRDR) += vmlogrdr.o
obj-$(CONFIG_VMCP) += vmcp.o
-tape-$(CONFIG_S390_TAPE_BLOCK) += tape_block.o
tape-$(CONFIG_PROC_FS) += tape_proc.o
tape-objs := tape_core.o tape_std.o tape_char.o $(tape-y)
obj-$(CONFIG_S390_TAPE) += tape.o tape_class.o
diff --git a/drivers/s390/char/monwriter.c b/drivers/s390/char/monwriter.c
index e0702d3..4600aa1 100644
--- a/drivers/s390/char/monwriter.c
+++ b/drivers/s390/char/monwriter.c
@@ -97,7 +97,7 @@
{
struct monwrite_hdr *monhdr = &monpriv->hdr;
struct mon_buf *monbuf;
- int rc;
+ int rc = 0;
if (monhdr->datalen > MONWRITE_MAX_DATALEN ||
monhdr->mon_function > MONWRITE_START_CONFIG ||
@@ -135,7 +135,7 @@
mon_buf_count++;
}
monpriv->current_buf = monbuf;
- return 0;
+ return rc;
}
static int monwrite_new_data(struct mon_private *monpriv)
diff --git a/drivers/s390/char/raw3270.c b/drivers/s390/char/raw3270.c
index e21a5c3..810ac38 100644
--- a/drivers/s390/char/raw3270.c
+++ b/drivers/s390/char/raw3270.c
@@ -598,7 +598,6 @@
static const unsigned char wbuf[] =
{ 0x00, 0x07, 0x01, 0xff, 0x03, 0x00, 0x81 };
struct raw3270_ua *uap;
- unsigned short count;
int rc;
/*
@@ -653,7 +652,6 @@
if (rc)
return rc;
/* Got a Query Reply */
- count = sizeof(rp->init_data) - rp->init_request.rescnt;
uap = (struct raw3270_ua *) (rp->init_data + 1);
/* Paranoia check. */
if (rp->init_data[0] != 0x88 || uap->uab.qcode != 0x81)
diff --git a/drivers/s390/char/sclp.h b/drivers/s390/char/sclp.h
index 6bb5a6b..49a1bb5 100644
--- a/drivers/s390/char/sclp.h
+++ b/drivers/s390/char/sclp.h
@@ -28,6 +28,7 @@
#define EVTYP_CONFMGMDATA 0x04
#define EVTYP_SDIAS 0x1C
#define EVTYP_ASYNC 0x0A
+#define EVTYP_OCF 0x1E
#define EVTYP_OPCMD_MASK 0x80000000
#define EVTYP_MSG_MASK 0x40000000
@@ -40,6 +41,7 @@
#define EVTYP_CONFMGMDATA_MASK 0x10000000
#define EVTYP_SDIAS_MASK 0x00000010
#define EVTYP_ASYNC_MASK 0x00400000
+#define EVTYP_OCF_MASK 0x00000004
#define GNRLMSGFLGS_DOM 0x8000
#define GNRLMSGFLGS_SNDALRM 0x4000
@@ -186,4 +188,26 @@
(MACHINE_IS_VM) ? ASCEBC(str, nr) : ASCEBC_500(str, nr);
}
+static inline struct gds_vector *
+sclp_find_gds_vector(void *start, void *end, u16 id)
+{
+ struct gds_vector *v;
+
+ for (v = start; (void *) v < end; v = (void *) v + v->length)
+ if (v->gds_id == id)
+ return v;
+ return NULL;
+}
+
+static inline struct gds_subvector *
+sclp_find_gds_subvector(void *start, void *end, u8 key)
+{
+ struct gds_subvector *sv;
+
+ for (sv = start; (void *) sv < end; sv = (void *) sv + sv->length)
+ if (sv->key == key)
+ return sv;
+ return NULL;
+}
+
#endif /* __SCLP_H__ */
diff --git a/drivers/s390/char/sclp_config.c b/drivers/s390/char/sclp_config.c
index 16e232a..95b909a 100644
--- a/drivers/s390/char/sclp_config.c
+++ b/drivers/s390/char/sclp_config.c
@@ -71,21 +71,9 @@
static int __init sclp_conf_init(void)
{
- int rc;
-
INIT_WORK(&sclp_cpu_capability_work, sclp_cpu_capability_notify);
INIT_WORK(&sclp_cpu_change_work, sclp_cpu_change_notify);
-
- rc = sclp_register(&sclp_conf_register);
- if (rc)
- return rc;
-
- if (!(sclp_conf_register.sclp_send_mask & EVTYP_CONFMGMDATA_MASK)) {
- pr_warning("no configuration management.\n");
- sclp_unregister(&sclp_conf_register);
- rc = -ENOSYS;
- }
- return rc;
+ return sclp_register(&sclp_conf_register);
}
__initcall(sclp_conf_init);
diff --git a/drivers/s390/char/sclp_ocf.c b/drivers/s390/char/sclp_ocf.c
new file mode 100644
index 0000000..ab294d5
--- /dev/null
+++ b/drivers/s390/char/sclp_ocf.c
@@ -0,0 +1,145 @@
+/*
+ * drivers/s390/char/sclp_ocf.c
+ * SCLP OCF communication parameters sysfs interface
+ *
+ * Copyright IBM Corp. 2011
+ * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>
+ */
+
+#define KMSG_COMPONENT "sclp_ocf"
+#define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/stat.h>
+#include <linux/device.h>
+#include <linux/string.h>
+#include <linux/ctype.h>
+#include <linux/kmod.h>
+#include <linux/timer.h>
+#include <linux/err.h>
+#include <asm/ebcdic.h>
+#include <asm/sclp.h>
+
+#include "sclp.h"
+
+#define OCF_LENGTH_HMC_NETWORK 8UL
+#define OCF_LENGTH_CPC_NAME 8UL
+
+static char hmc_network[OCF_LENGTH_HMC_NETWORK + 1];
+static char cpc_name[OCF_LENGTH_CPC_NAME + 1];
+
+static DEFINE_SPINLOCK(sclp_ocf_lock);
+static struct work_struct sclp_ocf_change_work;
+
+static struct kset *ocf_kset;
+
+static void sclp_ocf_change_notify(struct work_struct *work)
+{
+ kobject_uevent(&ocf_kset->kobj, KOBJ_CHANGE);
+}
+
+/* Handler for OCF event. Look for the CPC image name. */
+static void sclp_ocf_handler(struct evbuf_header *evbuf)
+{
+ struct gds_vector *v;
+ struct gds_subvector *sv, *netid, *cpc;
+ size_t size;
+
+ /* Find the 0x9f00 block. */
+ v = sclp_find_gds_vector(evbuf + 1, (void *) evbuf + evbuf->length,
+ 0x9f00);
+ if (!v)
+ return;
+ /* Find the 0x9f22 block inside the 0x9f00 block. */
+ v = sclp_find_gds_vector(v + 1, (void *) v + v->length, 0x9f22);
+ if (!v)
+ return;
+ /* Find the 0x81 block inside the 0x9f22 block. */
+ sv = sclp_find_gds_subvector(v + 1, (void *) v + v->length, 0x81);
+ if (!sv)
+ return;
+ /* Find the 0x01 block inside the 0x81 block. */
+ netid = sclp_find_gds_subvector(sv + 1, (void *) sv + sv->length, 1);
+ /* Find the 0x02 block inside the 0x81 block. */
+ cpc = sclp_find_gds_subvector(sv + 1, (void *) sv + sv->length, 2);
+ /* Copy network name and cpc name. */
+ spin_lock(&sclp_ocf_lock);
+ if (netid) {
+ size = min(OCF_LENGTH_HMC_NETWORK, (size_t) netid->length);
+ memcpy(hmc_network, netid + 1, size);
+ EBCASC(hmc_network, size);
+ hmc_network[size] = 0;
+ }
+ if (cpc) {
+ size = min(OCF_LENGTH_CPC_NAME, (size_t) cpc->length);
+ memcpy(cpc_name, cpc + 1, size);
+ EBCASC(cpc_name, size);
+ cpc_name[size] = 0;
+ }
+ spin_unlock(&sclp_ocf_lock);
+ schedule_work(&sclp_ocf_change_work);
+}
+
+static struct sclp_register sclp_ocf_event = {
+ .receive_mask = EVTYP_OCF_MASK,
+ .receiver_fn = sclp_ocf_handler,
+};
+
+static ssize_t cpc_name_show(struct kobject *kobj,
+ struct kobj_attribute *attr, char *page)
+{
+ int rc;
+
+ spin_lock_irq(&sclp_ocf_lock);
+ rc = snprintf(page, PAGE_SIZE, "%s\n", cpc_name);
+ spin_unlock_irq(&sclp_ocf_lock);
+ return rc;
+}
+
+static struct kobj_attribute cpc_name_attr =
+ __ATTR(cpc_name, 0444, cpc_name_show, NULL);
+
+static ssize_t hmc_network_show(struct kobject *kobj,
+ struct kobj_attribute *attr, char *page)
+{
+ int rc;
+
+ spin_lock_irq(&sclp_ocf_lock);
+ rc = snprintf(page, PAGE_SIZE, "%s\n", hmc_network);
+ spin_unlock_irq(&sclp_ocf_lock);
+ return rc;
+}
+
+static struct kobj_attribute hmc_network_attr =
+ __ATTR(hmc_network, 0444, hmc_network_show, NULL);
+
+static struct attribute *ocf_attrs[] = {
+ &cpc_name_attr.attr,
+ &hmc_network_attr.attr,
+ NULL,
+};
+
+static struct attribute_group ocf_attr_group = {
+ .attrs = ocf_attrs,
+};
+
+static int __init ocf_init(void)
+{
+ int rc;
+
+ INIT_WORK(&sclp_ocf_change_work, sclp_ocf_change_notify);
+ ocf_kset = kset_create_and_add("ocf", NULL, firmware_kobj);
+ if (!ocf_kset)
+ return -ENOMEM;
+
+ rc = sysfs_create_group(&ocf_kset->kobj, &ocf_attr_group);
+ if (rc) {
+ kset_unregister(ocf_kset);
+ return rc;
+ }
+
+ return sclp_register(&sclp_ocf_event);
+}
+
+device_initcall(ocf_init);
diff --git a/drivers/s390/char/sclp_sdias.c b/drivers/s390/char/sclp_sdias.c
index 6a1c58d..fa733ec 100644
--- a/drivers/s390/char/sclp_sdias.c
+++ b/drivers/s390/char/sclp_sdias.c
@@ -69,9 +69,6 @@
static void sdias_callback(struct sclp_req *request, void *data)
{
- struct sdias_sccb *cbsccb;
-
- cbsccb = (struct sdias_sccb *) request->sccb;
sclp_req_done = 1;
wake_up(&sdias_wq); /* Inform caller, that request is complete */
TRACE("callback done\n");
diff --git a/drivers/s390/char/sclp_tty.c b/drivers/s390/char/sclp_tty.c
index 8258d59..a879c13 100644
--- a/drivers/s390/char/sclp_tty.c
+++ b/drivers/s390/char/sclp_tty.c
@@ -408,118 +408,72 @@
return op - buf;
}
-static void
-sclp_get_input(unsigned char *start, unsigned char *end)
+static void sclp_get_input(struct gds_subvector *sv)
{
+ unsigned char *str;
int count;
- count = end - start;
+ str = (unsigned char *) (sv + 1);
+ count = sv->length - sizeof(*sv);
if (sclp_tty_tolower)
- EBC_TOLOWER(start, count);
- count = sclp_switch_cases(start, count);
+ EBC_TOLOWER(str, count);
+ count = sclp_switch_cases(str, count);
/* convert EBCDIC to ASCII (modify original input in SCCB) */
- sclp_ebcasc_str(start, count);
+ sclp_ebcasc_str(str, count);
/* transfer input to high level driver */
- sclp_tty_input(start, count);
+ sclp_tty_input(str, count);
}
-static inline struct gds_vector *
-find_gds_vector(struct gds_vector *start, struct gds_vector *end, u16 id)
+static inline void sclp_eval_selfdeftextmsg(struct gds_subvector *sv)
{
- struct gds_vector *vec;
+ void *end;
- for (vec = start; vec < end; vec = (void *) vec + vec->length)
- if (vec->gds_id == id)
- return vec;
- return NULL;
+ end = (void *) sv + sv->length;
+ for (sv = sv + 1; (void *) sv < end; sv = (void *) sv + sv->length)
+ if (sv->key == 0x30)
+ sclp_get_input(sv);
}
-static inline struct gds_subvector *
-find_gds_subvector(struct gds_subvector *start,
- struct gds_subvector *end, u8 key)
+static inline void sclp_eval_textcmd(struct gds_vector *v)
{
- struct gds_subvector *subvec;
+ struct gds_subvector *sv;
+ void *end;
- for (subvec = start; subvec < end;
- subvec = (void *) subvec + subvec->length)
- if (subvec->key == key)
- return subvec;
- return NULL;
+ end = (void *) v + v->length;
+ for (sv = (struct gds_subvector *) (v + 1);
+ (void *) sv < end; sv = (void *) sv + sv->length)
+ if (sv->key == GDS_KEY_SELFDEFTEXTMSG)
+ sclp_eval_selfdeftextmsg(sv);
+
}
-static inline void
-sclp_eval_selfdeftextmsg(struct gds_subvector *start,
- struct gds_subvector *end)
+static inline void sclp_eval_cpmsu(struct gds_vector *v)
{
- struct gds_subvector *subvec;
+ void *end;
- subvec = start;
- while (subvec < end) {
- subvec = find_gds_subvector(subvec, end, 0x30);
- if (!subvec)
- break;
- sclp_get_input((unsigned char *)(subvec + 1),
- (unsigned char *) subvec + subvec->length);
- subvec = (void *) subvec + subvec->length;
- }
-}
-
-static inline void
-sclp_eval_textcmd(struct gds_subvector *start,
- struct gds_subvector *end)
-{
- struct gds_subvector *subvec;
-
- subvec = start;
- while (subvec < end) {
- subvec = find_gds_subvector(subvec, end,
- GDS_KEY_SELFDEFTEXTMSG);
- if (!subvec)
- break;
- sclp_eval_selfdeftextmsg((struct gds_subvector *)(subvec + 1),
- (void *)subvec + subvec->length);
- subvec = (void *) subvec + subvec->length;
- }
-}
-
-static inline void
-sclp_eval_cpmsu(struct gds_vector *start, struct gds_vector *end)
-{
- struct gds_vector *vec;
-
- vec = start;
- while (vec < end) {
- vec = find_gds_vector(vec, end, GDS_ID_TEXTCMD);
- if (!vec)
- break;
- sclp_eval_textcmd((struct gds_subvector *)(vec + 1),
- (void *) vec + vec->length);
- vec = (void *) vec + vec->length;
- }
+ end = (void *) v + v->length;
+ for (v = v + 1; (void *) v < end; v = (void *) v + v->length)
+ if (v->gds_id == GDS_ID_TEXTCMD)
+ sclp_eval_textcmd(v);
}
-static inline void
-sclp_eval_mdsmu(struct gds_vector *start, void *end)
+static inline void sclp_eval_mdsmu(struct gds_vector *v)
{
- struct gds_vector *vec;
-
- vec = find_gds_vector(start, end, GDS_ID_CPMSU);
- if (vec)
- sclp_eval_cpmsu(vec + 1, (void *) vec + vec->length);
+ v = sclp_find_gds_vector(v + 1, (void *) v + v->length, GDS_ID_CPMSU);
+ if (v)
+ sclp_eval_cpmsu(v);
}
-static void
-sclp_tty_receiver(struct evbuf_header *evbuf)
+static void sclp_tty_receiver(struct evbuf_header *evbuf)
{
- struct gds_vector *start, *end, *vec;
+ struct gds_vector *v;
- start = (struct gds_vector *)(evbuf + 1);
- end = (void *) evbuf + evbuf->length;
- vec = find_gds_vector(start, end, GDS_ID_MDSMU);
- if (vec)
- sclp_eval_mdsmu(vec + 1, (void *) vec + vec->length);
+ v = sclp_find_gds_vector(evbuf + 1, (void *) evbuf + evbuf->length,
+ GDS_ID_MDSMU);
+ if (v)
+ sclp_eval_mdsmu(v);
}
static void
diff --git a/drivers/s390/char/tape_3590.c b/drivers/s390/char/tape_3590.c
index b98dcbd..a7d5707 100644
--- a/drivers/s390/char/tape_3590.c
+++ b/drivers/s390/char/tape_3590.c
@@ -796,10 +796,8 @@
static int
tape_3590_done(struct tape_device *device, struct tape_request *request)
{
- struct tape_3590_disc_data *disc_data;
DBF_EVENT(6, "%s done\n", tape_op_verbose[request->op]);
- disc_data = device->discdata;
switch (request->op) {
case TO_BSB:
@@ -1394,17 +1392,12 @@
static int tape_3590_crypt_error(struct tape_device *device,
struct tape_request *request, struct irb *irb)
{
- u8 cu_rc, ekm_rc1;
+ u8 cu_rc;
u16 ekm_rc2;
- u32 drv_rc;
- const char *bus_id;
char *sense;
sense = ((struct tape_3590_sense *) irb->ecw)->fmt.data;
- bus_id = dev_name(&device->cdev->dev);
cu_rc = sense[0];
- drv_rc = *((u32*) &sense[5]) & 0xffffff;
- ekm_rc1 = sense[9];
ekm_rc2 = *((u16*) &sense[10]);
if ((cu_rc == 0) && (ekm_rc2 == 0xee31))
/* key not defined on EKM */
@@ -1429,7 +1422,6 @@
struct irb *irb)
{
struct tape_3590_sense *sense;
- int rc;
#ifdef CONFIG_S390_TAPE_BLOCK
if (request->op == TO_BLOCK) {
@@ -1454,7 +1446,6 @@
* - "break": basic error recovery is done
* - "goto out:": just print error message if available
*/
- rc = -EIO;
switch (sense->rc_rqc) {
case 0x1110:
diff --git a/drivers/s390/char/tape_block.c b/drivers/s390/char/tape_block.c
deleted file mode 100644
index 1b3924c..0000000
--- a/drivers/s390/char/tape_block.c
+++ /dev/null
@@ -1,444 +0,0 @@
-/*
- * drivers/s390/char/tape_block.c
- * block device frontend for tape device driver
- *
- * S390 and zSeries version
- * Copyright (C) 2001,2003 IBM Deutschland Entwicklung GmbH, IBM Corporation
- * Author(s): Carsten Otte <cotte@de.ibm.com>
- * Tuan Ngo-Anh <ngoanh@de.ibm.com>
- * Martin Schwidefsky <schwidefsky@de.ibm.com>
- * Stefan Bader <shbader@de.ibm.com>
- */
-
-#define KMSG_COMPONENT "tape"
-#define pr_fmt(fmt) KMSG_COMPONENT ": " fmt
-
-#include <linux/fs.h>
-#include <linux/module.h>
-#include <linux/blkdev.h>
-#include <linux/mutex.h>
-#include <linux/interrupt.h>
-#include <linux/buffer_head.h>
-#include <linux/kernel.h>
-
-#include <asm/debug.h>
-
-#define TAPE_DBF_AREA tape_core_dbf
-
-#include "tape.h"
-
-#define TAPEBLOCK_MAX_SEC 100
-#define TAPEBLOCK_MIN_REQUEUE 3
-
-/*
- * 2003/11/25 Stefan Bader <shbader@de.ibm.com>
- *
- * In 2.5/2.6 the block device request function is very likely to be called
- * with disabled interrupts (e.g. generic_unplug_device). So the driver can't
- * just call any function that tries to allocate CCW requests from that con-
- * text since it might sleep. There are two choices to work around this:
- * a) do not allocate with kmalloc but use its own memory pool
- * b) take requests from the queue outside that context, knowing that
- * allocation might sleep
- */
-
-/*
- * file operation structure for tape block frontend
- */
-static DEFINE_MUTEX(tape_block_mutex);
-static int tapeblock_open(struct block_device *, fmode_t);
-static int tapeblock_release(struct gendisk *, fmode_t);
-static unsigned int tapeblock_check_events(struct gendisk *, unsigned int);
-static int tapeblock_revalidate_disk(struct gendisk *);
-
-static const struct block_device_operations tapeblock_fops = {
- .owner = THIS_MODULE,
- .open = tapeblock_open,
- .release = tapeblock_release,
- .check_events = tapeblock_check_events,
- .revalidate_disk = tapeblock_revalidate_disk,
-};
-
-static int tapeblock_major = 0;
-
-static void
-tapeblock_trigger_requeue(struct tape_device *device)
-{
- /* Protect against rescheduling. */
- if (atomic_cmpxchg(&device->blk_data.requeue_scheduled, 0, 1) != 0)
- return;
- schedule_work(&device->blk_data.requeue_task);
-}
-
-/*
- * Post finished request.
- */
-static void
-__tapeblock_end_request(struct tape_request *ccw_req, void *data)
-{
- struct tape_device *device;
- struct request *req;
-
- DBF_LH(6, "__tapeblock_end_request()\n");
-
- device = ccw_req->device;
- req = (struct request *) data;
- blk_end_request_all(req, (ccw_req->rc == 0) ? 0 : -EIO);
- if (ccw_req->rc == 0)
- /* Update position. */
- device->blk_data.block_position =
- (blk_rq_pos(req) + blk_rq_sectors(req)) >> TAPEBLOCK_HSEC_S2B;
- else
- /* We lost the position information due to an error. */
- device->blk_data.block_position = -1;
- device->discipline->free_bread(ccw_req);
- if (!list_empty(&device->req_queue) ||
- blk_peek_request(device->blk_data.request_queue))
- tapeblock_trigger_requeue(device);
-}
-
-/*
- * Feed the tape device CCW queue with requests supplied in a list.
- */
-static int
-tapeblock_start_request(struct tape_device *device, struct request *req)
-{
- struct tape_request * ccw_req;
- int rc;
-
- DBF_LH(6, "tapeblock_start_request(%p, %p)\n", device, req);
-
- ccw_req = device->discipline->bread(device, req);
- if (IS_ERR(ccw_req)) {
- DBF_EVENT(1, "TBLOCK: bread failed\n");
- blk_end_request_all(req, -EIO);
- return PTR_ERR(ccw_req);
- }
- ccw_req->callback = __tapeblock_end_request;
- ccw_req->callback_data = (void *) req;
- ccw_req->retries = TAPEBLOCK_RETRIES;
-
- rc = tape_do_io_async(device, ccw_req);
- if (rc) {
- /*
- * Start/enqueueing failed. No retries in
- * this case.
- */
- blk_end_request_all(req, -EIO);
- device->discipline->free_bread(ccw_req);
- }
-
- return rc;
-}
-
-/*
- * Move requests from the block device request queue to the tape device ccw
- * queue.
- */
-static void
-tapeblock_requeue(struct work_struct *work) {
- struct tape_blk_data * blkdat;
- struct tape_device * device;
- struct request_queue * queue;
- int nr_queued;
- struct request * req;
- struct list_head * l;
- int rc;
-
- blkdat = container_of(work, struct tape_blk_data, requeue_task);
- device = blkdat->device;
- if (!device)
- return;
-
- spin_lock_irq(get_ccwdev_lock(device->cdev));
- queue = device->blk_data.request_queue;
-
- /* Count number of requests on ccw queue. */
- nr_queued = 0;
- list_for_each(l, &device->req_queue)
- nr_queued++;
- spin_unlock(get_ccwdev_lock(device->cdev));
-
- spin_lock_irq(&device->blk_data.request_queue_lock);
- while (
- blk_peek_request(queue) &&
- nr_queued < TAPEBLOCK_MIN_REQUEUE
- ) {
- req = blk_fetch_request(queue);
- if (rq_data_dir(req) == WRITE) {
- DBF_EVENT(1, "TBLOCK: Rejecting write request\n");
- spin_unlock_irq(&device->blk_data.request_queue_lock);
- blk_end_request_all(req, -EIO);
- spin_lock_irq(&device->blk_data.request_queue_lock);
- continue;
- }
- nr_queued++;
- spin_unlock_irq(&device->blk_data.request_queue_lock);
- rc = tapeblock_start_request(device, req);
- spin_lock_irq(&device->blk_data.request_queue_lock);
- }
- spin_unlock_irq(&device->blk_data.request_queue_lock);
- atomic_set(&device->blk_data.requeue_scheduled, 0);
-}
-
-/*
- * Tape request queue function. Called from ll_rw_blk.c
- */
-static void
-tapeblock_request_fn(struct request_queue *queue)
-{
- struct tape_device *device;
-
- device = (struct tape_device *) queue->queuedata;
- DBF_LH(6, "tapeblock_request_fn(device=%p)\n", device);
- BUG_ON(device == NULL);
- tapeblock_trigger_requeue(device);
-}
-
-/*
- * This function is called for every new tapedevice
- */
-int
-tapeblock_setup_device(struct tape_device * device)
-{
- struct tape_blk_data * blkdat;
- struct gendisk * disk;
- int rc;
-
- blkdat = &device->blk_data;
- blkdat->device = device;
- spin_lock_init(&blkdat->request_queue_lock);
- atomic_set(&blkdat->requeue_scheduled, 0);
-
- blkdat->request_queue = blk_init_queue(
- tapeblock_request_fn,
- &blkdat->request_queue_lock
- );
- if (!blkdat->request_queue)
- return -ENOMEM;
-
- rc = elevator_change(blkdat->request_queue, "noop");
- if (rc)
- goto cleanup_queue;
-
- blk_queue_logical_block_size(blkdat->request_queue, TAPEBLOCK_HSEC_SIZE);
- blk_queue_max_hw_sectors(blkdat->request_queue, TAPEBLOCK_MAX_SEC);
- blk_queue_max_segments(blkdat->request_queue, -1L);
- blk_queue_max_segment_size(blkdat->request_queue, -1L);
- blk_queue_segment_boundary(blkdat->request_queue, -1L);
-
- disk = alloc_disk(1);
- if (!disk) {
- rc = -ENOMEM;
- goto cleanup_queue;
- }
-
- disk->major = tapeblock_major;
- disk->first_minor = device->first_minor;
- disk->fops = &tapeblock_fops;
- disk->private_data = tape_get_device(device);
- disk->queue = blkdat->request_queue;
- set_capacity(disk, 0);
- sprintf(disk->disk_name, "btibm%d",
- device->first_minor / TAPE_MINORS_PER_DEV);
-
- blkdat->disk = disk;
- blkdat->medium_changed = 1;
- blkdat->request_queue->queuedata = tape_get_device(device);
-
- add_disk(disk);
-
- tape_get_device(device);
- INIT_WORK(&blkdat->requeue_task, tapeblock_requeue);
-
- return 0;
-
-cleanup_queue:
- blk_cleanup_queue(blkdat->request_queue);
- blkdat->request_queue = NULL;
-
- return rc;
-}
-
-void
-tapeblock_cleanup_device(struct tape_device *device)
-{
- flush_work_sync(&device->blk_data.requeue_task);
- tape_put_device(device);
-
- if (!device->blk_data.disk) {
- goto cleanup_queue;
- }
-
- del_gendisk(device->blk_data.disk);
- device->blk_data.disk->private_data = NULL;
- tape_put_device(device);
- put_disk(device->blk_data.disk);
-
- device->blk_data.disk = NULL;
-cleanup_queue:
- device->blk_data.request_queue->queuedata = NULL;
- tape_put_device(device);
-
- blk_cleanup_queue(device->blk_data.request_queue);
- device->blk_data.request_queue = NULL;
-}
-
-/*
- * Detect number of blocks of the tape.
- * FIXME: can we extent this to detect the blocks size as well ?
- */
-static int
-tapeblock_revalidate_disk(struct gendisk *disk)
-{
- struct tape_device * device;
- unsigned int nr_of_blks;
- int rc;
-
- device = (struct tape_device *) disk->private_data;
- BUG_ON(!device);
-
- if (!device->blk_data.medium_changed)
- return 0;
-
- rc = tape_mtop(device, MTFSFM, 1);
- if (rc)
- return rc;
-
- rc = tape_mtop(device, MTTELL, 1);
- if (rc < 0)
- return rc;
-
- pr_info("%s: Determining the size of the recorded area...\n",
- dev_name(&device->cdev->dev));
- DBF_LH(3, "Image file ends at %d\n", rc);
- nr_of_blks = rc;
-
- /* This will fail for the first file. Catch the error by checking the
- * position. */
- tape_mtop(device, MTBSF, 1);
-
- rc = tape_mtop(device, MTTELL, 1);
- if (rc < 0)
- return rc;
-
- if (rc > nr_of_blks)
- return -EINVAL;
-
- DBF_LH(3, "Image file starts at %d\n", rc);
- device->bof = rc;
- nr_of_blks -= rc;
-
- pr_info("%s: The size of the recorded area is %i blocks\n",
- dev_name(&device->cdev->dev), nr_of_blks);
- set_capacity(device->blk_data.disk,
- nr_of_blks*(TAPEBLOCK_HSEC_SIZE/512));
-
- device->blk_data.block_position = 0;
- device->blk_data.medium_changed = 0;
- return 0;
-}
-
-static unsigned int
-tapeblock_check_events(struct gendisk *disk, unsigned int clearing)
-{
- struct tape_device *device;
-
- device = (struct tape_device *) disk->private_data;
- DBF_LH(6, "tapeblock_medium_changed(%p) = %d\n",
- device, device->blk_data.medium_changed);
-
- return device->blk_data.medium_changed ? DISK_EVENT_MEDIA_CHANGE : 0;
-}
-
-/*
- * Block frontend tape device open function.
- */
-static int
-tapeblock_open(struct block_device *bdev, fmode_t mode)
-{
- struct gendisk * disk = bdev->bd_disk;
- struct tape_device * device;
- int rc;
-
- mutex_lock(&tape_block_mutex);
- device = tape_get_device(disk->private_data);
-
- if (device->required_tapemarks) {
- DBF_EVENT(2, "TBLOCK: missing tapemarks\n");
- pr_warning("%s: Opening the tape failed because of missing "
- "end-of-file marks\n", dev_name(&device->cdev->dev));
- rc = -EPERM;
- goto put_device;
- }
-
- rc = tape_open(device);
- if (rc)
- goto put_device;
-
- rc = tapeblock_revalidate_disk(disk);
- if (rc)
- goto release;
-
- /*
- * Note: The reference to <device> is hold until the release function
- * is called.
- */
- tape_state_set(device, TS_BLKUSE);
- mutex_unlock(&tape_block_mutex);
- return 0;
-
-release:
- tape_release(device);
- put_device:
- tape_put_device(device);
- mutex_unlock(&tape_block_mutex);
- return rc;
-}
-
-/*
- * Block frontend tape device release function.
- *
- * Note: One reference to the tape device was made by the open function. So
- * we just get the pointer here and release the reference.
- */
-static int
-tapeblock_release(struct gendisk *disk, fmode_t mode)
-{
- struct tape_device *device = disk->private_data;
-
- mutex_lock(&tape_block_mutex);
- tape_state_set(device, TS_IN_USE);
- tape_release(device);
- tape_put_device(device);
- mutex_unlock(&tape_block_mutex);
-
- return 0;
-}
-
-/*
- * Initialize block device frontend.
- */
-int
-tapeblock_init(void)
-{
- int rc;
-
- /* Register the tape major number to the kernel */
- rc = register_blkdev(tapeblock_major, "tBLK");
- if (rc < 0)
- return rc;
-
- if (tapeblock_major == 0)
- tapeblock_major = rc;
- return 0;
-}
-
-/*
- * Deregister major for block device frontend
- */
-void
-tapeblock_exit(void)
-{
- unregister_blkdev(tapeblock_major, "tBLK");
-}
diff --git a/drivers/s390/char/tape_std.c b/drivers/s390/char/tape_std.c
index 3c3f342..e765017 100644
--- a/drivers/s390/char/tape_std.c
+++ b/drivers/s390/char/tape_std.c
@@ -564,7 +564,6 @@
tape_std_mtreten(struct tape_device *device, int mt_count)
{
struct tape_request *request;
- int rc;
request = tape_alloc_request(4, 0);
if (IS_ERR(request))
@@ -576,7 +575,7 @@
tape_ccw_cc(request->cpaddr + 2, NOP, 0, NULL);
tape_ccw_end(request->cpaddr + 3, CCW_CMD_TIC, 0, request->cpaddr);
/* execute it, MTRETEN rc gets ignored */
- rc = tape_do_io_interruptible(device, request);
+ tape_do_io_interruptible(device, request);
tape_free_request(request);
return tape_mtop(device, MTREW, 1);
}
diff --git a/drivers/s390/cio/chsc.c b/drivers/s390/cio/chsc.c
index 0689fcf..75c3f1f 100644
--- a/drivers/s390/cio/chsc.c
+++ b/drivers/s390/cio/chsc.c
@@ -326,6 +326,36 @@
s390_process_res_acc(&link);
}
+static void chsc_process_sei_chp_avail(struct chsc_sei_area *sei_area)
+{
+ struct channel_path *chp;
+ struct chp_id chpid;
+ u8 *data;
+ int num;
+
+ CIO_CRW_EVENT(4, "chsc: channel path availability information\n");
+ if (sei_area->rs != 0)
+ return;
+ data = sei_area->ccdf;
+ chp_id_init(&chpid);
+ for (num = 0; num <= __MAX_CHPID; num++) {
+ if (!chp_test_bit(data, num))
+ continue;
+ chpid.id = num;
+
+ CIO_CRW_EVENT(4, "Update information for channel path "
+ "%x.%02x\n", chpid.cssid, chpid.id);
+ chp = chpid_to_chp(chpid);
+ if (!chp) {
+ chp_new(chpid);
+ continue;
+ }
+ mutex_lock(&chp->lock);
+ chsc_determine_base_channel_path_desc(chpid, &chp->desc);
+ mutex_unlock(&chp->lock);
+ }
+}
+
struct chp_config_data {
u8 map[32];
u8 op;
@@ -376,9 +406,12 @@
case 1: /* link incident*/
chsc_process_sei_link_incident(sei_area);
break;
- case 2: /* i/o resource accessibiliy */
+ case 2: /* i/o resource accessibility */
chsc_process_sei_res_acc(sei_area);
break;
+ case 7: /* channel-path-availability information */
+ chsc_process_sei_chp_avail(sei_area);
+ break;
case 8: /* channel-path-configuration notification */
chsc_process_sei_chp_config(sei_area);
break;
diff --git a/drivers/s390/cio/device_fsm.c b/drivers/s390/cio/device_fsm.c
index 6084103..52c233f 100644
--- a/drivers/s390/cio/device_fsm.c
+++ b/drivers/s390/cio/device_fsm.c
@@ -408,9 +408,10 @@
CIO_MSG_EVENT(0, "Disconnected device %04x on subchannel "
"%04x\n", cdev->private->dev_id.devno,
sch->schid.sch_no);
- if (ccw_device_notify(cdev, CIO_NO_PATH) != NOTIFY_OK)
+ if (ccw_device_notify(cdev, CIO_NO_PATH) != NOTIFY_OK) {
+ cdev->private->state = DEV_STATE_NOT_OPER;
ccw_device_sched_todo(cdev, CDEV_TODO_UNREG);
- else
+ } else
ccw_device_set_disconnected(cdev);
cdev->private->flags.donotify = 0;
break;
@@ -840,9 +841,6 @@
static void
ccw_device_killing_irq(struct ccw_device *cdev, enum dev_event dev_event)
{
- struct subchannel *sch;
-
- sch = to_subchannel(cdev->dev.parent);
ccw_device_set_timeout(cdev, 0);
/* Start delayed path verification. */
ccw_device_online_verify(cdev, 0);
diff --git a/drivers/s390/cio/device_ops.c b/drivers/s390/cio/device_ops.c
index 651976b..f98698d 100644
--- a/drivers/s390/cio/device_ops.c
+++ b/drivers/s390/cio/device_ops.c
@@ -418,12 +418,9 @@
int
ccw_device_call_handler(struct ccw_device *cdev)
{
- struct subchannel *sch;
unsigned int stctl;
int ending_status;
- sch = to_subchannel(cdev->dev.parent);
-
/*
* we allow for the device action handler if .
* - we received ending status
diff --git a/drivers/s390/cio/qdio_main.c b/drivers/s390/cio/qdio_main.c
index e8f267e..55e8f72 100644
--- a/drivers/s390/cio/qdio_main.c
+++ b/drivers/s390/cio/qdio_main.c
@@ -1446,7 +1446,7 @@
static int handle_outbound(struct qdio_q *q, unsigned int callflags,
int bufnr, int count)
{
- unsigned char state;
+ unsigned char state = 0;
int used, rc = 0;
qperf_inc(q, outbound_call);
diff --git a/drivers/s390/crypto/ap_bus.c b/drivers/s390/crypto/ap_bus.c
index 67302b9..16e4a25 100644
--- a/drivers/s390/crypto/ap_bus.c
+++ b/drivers/s390/crypto/ap_bus.c
@@ -1183,8 +1183,12 @@
INIT_LIST_HEAD(&ap_dev->list);
setup_timer(&ap_dev->timeout, ap_request_timeout,
(unsigned long) ap_dev);
- if (device_type == 0)
- ap_probe_device_type(ap_dev);
+ if (device_type == 0) {
+ if (ap_probe_device_type(ap_dev)) {
+ kfree(ap_dev);
+ continue;
+ }
+ }
else
ap_dev->device_type = device_type;
diff --git a/drivers/scsi/pcmcia/aha152x_stub.c b/drivers/scsi/pcmcia/aha152x_stub.c
index e77dd02..7d1609f 100644
--- a/drivers/scsi/pcmcia/aha152x_stub.c
+++ b/drivers/scsi/pcmcia/aha152x_stub.c
@@ -202,7 +202,7 @@
return 0;
}
-static struct pcmcia_device_id aha152x_ids[] = {
+static const struct pcmcia_device_id aha152x_ids[] = {
PCMCIA_DEVICE_PROD_ID123("New Media", "SCSI", "Bus Toaster", 0xcdf7e4cc, 0x35f26476, 0xa8851d6e),
PCMCIA_DEVICE_PROD_ID123("NOTEWORTHY", "SCSI", "Bus Toaster", 0xad89c6e8, 0x35f26476, 0xa8851d6e),
PCMCIA_DEVICE_PROD_ID12("Adaptec, Inc.", "APA-1460 SCSI Host Adapter", 0x24ba9738, 0x3a3c3d20),
diff --git a/drivers/scsi/pcmcia/fdomain_stub.c b/drivers/scsi/pcmcia/fdomain_stub.c
index cd69c26..714b248 100644
--- a/drivers/scsi/pcmcia/fdomain_stub.c
+++ b/drivers/scsi/pcmcia/fdomain_stub.c
@@ -178,7 +178,7 @@
return 0;
}
-static struct pcmcia_device_id fdomain_ids[] = {
+static const struct pcmcia_device_id fdomain_ids[] = {
PCMCIA_DEVICE_PROD_ID12("IBM Corp.", "SCSI PCMCIA Card", 0xe3736c88, 0x859cad20),
PCMCIA_DEVICE_PROD_ID1("SCSI PCMCIA Adapter Card", 0x8dacb57e),
PCMCIA_DEVICE_PROD_ID12(" SIMPLE TECHNOLOGY Corporation", "SCSI PCMCIA Credit Card Controller", 0x182bdafe, 0xc80d106f),
diff --git a/drivers/scsi/pcmcia/nsp_cs.c b/drivers/scsi/pcmcia/nsp_cs.c
index 54bdf6d..ca86721 100644
--- a/drivers/scsi/pcmcia/nsp_cs.c
+++ b/drivers/scsi/pcmcia/nsp_cs.c
@@ -1752,7 +1752,7 @@
/*======================================================================*
* module entry point
*====================================================================*/
-static struct pcmcia_device_id nsp_cs_ids[] = {
+static const struct pcmcia_device_id nsp_cs_ids[] = {
PCMCIA_DEVICE_PROD_ID123("IO DATA", "CBSC16 ", "1", 0x547e66dc, 0x0d63a3fd, 0x51de003a),
PCMCIA_DEVICE_PROD_ID123("KME ", "SCSI-CARD-001", "1", 0x534c02bc, 0x52008408, 0x51de003a),
PCMCIA_DEVICE_PROD_ID123("KME ", "SCSI-CARD-002", "1", 0x534c02bc, 0xcb09d5b2, 0x51de003a),
diff --git a/drivers/scsi/pcmcia/qlogic_stub.c b/drivers/scsi/pcmcia/qlogic_stub.c
index 9c96ca8..bcaf89f 100644
--- a/drivers/scsi/pcmcia/qlogic_stub.c
+++ b/drivers/scsi/pcmcia/qlogic_stub.c
@@ -270,7 +270,7 @@
return 0;
}
-static struct pcmcia_device_id qlogic_ids[] = {
+static const struct pcmcia_device_id qlogic_ids[] = {
PCMCIA_DEVICE_PROD_ID12("EIger Labs", "PCMCIA-to-SCSI Adapter", 0x88395fa7, 0x33b7a5e6),
PCMCIA_DEVICE_PROD_ID12("EPSON", "SCSI-2 PC Card SC200", 0xd361772f, 0x299d1751),
PCMCIA_DEVICE_PROD_ID12("MACNICA", "MIRACLE SCSI-II mPS110", 0x20841b68, 0xab3c3b6d),
diff --git a/drivers/scsi/pcmcia/sym53c500_cs.c b/drivers/scsi/pcmcia/sym53c500_cs.c
index 8552296..f5b5273 100644
--- a/drivers/scsi/pcmcia/sym53c500_cs.c
+++ b/drivers/scsi/pcmcia/sym53c500_cs.c
@@ -865,7 +865,7 @@
MODULE_DESCRIPTION("SYM53C500 PCMCIA SCSI driver");
MODULE_LICENSE("GPL");
-static struct pcmcia_device_id sym53c500_ids[] = {
+static const struct pcmcia_device_id sym53c500_ids[] = {
PCMCIA_DEVICE_PROD_ID12("BASICS by New Media Corporation", "SCSI Sym53C500", 0x23c78a9d, 0x0099e7f7),
PCMCIA_DEVICE_PROD_ID12("New Media Corporation", "SCSI Bus Toaster Sym53C500", 0x085a850b, 0x45432eb8),
PCMCIA_DEVICE_PROD_ID2("SCSI9000", 0x21648f44),
diff --git a/drivers/scsi/qla4xxx/ql4_nx.c b/drivers/scsi/qla4xxx/ql4_nx.c
index 35381cb..03e522b 100644
--- a/drivers/scsi/qla4xxx/ql4_nx.c
+++ b/drivers/scsi/qla4xxx/ql4_nx.c
@@ -655,6 +655,27 @@
return 0;
}
+#ifndef readq
+static inline __u64 readq(const volatile void __iomem *addr)
+{
+ const volatile u32 __iomem *p = addr;
+ u32 low, high;
+
+ low = readl(p);
+ high = readl(p + 1);
+
+ return low + ((u64)high << 32);
+}
+#endif
+
+#ifndef writeq
+static inline void writeq(__u64 val, volatile void __iomem *addr)
+{
+ writel(val, addr);
+ writel(val >> 32, addr+4);
+}
+#endif
+
static int qla4_8xxx_pci_mem_read_direct(struct scsi_qla_host *ha,
u64 off, void *data, int size)
{
diff --git a/drivers/scsi/sr.c b/drivers/scsi/sr.c
index 95019c7..4778e27 100644
--- a/drivers/scsi/sr.c
+++ b/drivers/scsi/sr.c
@@ -636,7 +636,7 @@
disk->first_minor = minor;
sprintf(disk->disk_name, "sr%d", minor);
disk->fops = &sr_bdops;
- disk->flags = GENHD_FL_CD;
+ disk->flags = GENHD_FL_CD | GENHD_FL_BLOCK_EVENTS_ON_EXCL_WRITE;
disk->events = DISK_EVENT_MEDIA_CHANGE | DISK_EVENT_EJECT_REQUEST;
blk_queue_rq_timeout(sdev->request_queue, SR_TIMEOUT);
diff --git a/drivers/sh/clk/cpg.c b/drivers/sh/clk/cpg.c
index 6172335..82dd6fb 100644
--- a/drivers/sh/clk/cpg.c
+++ b/drivers/sh/clk/cpg.c
@@ -105,7 +105,7 @@
/* Rebuild the frequency table */
clk_rate_table_build(clk, clk->freq_table, table->nr_divisors,
- table, &clk->arch_flags);
+ table, NULL);
return 0;
}
diff --git a/drivers/sh/intc/virq.c b/drivers/sh/intc/virq.c
index ce5f81d..1e6e2d0 100644
--- a/drivers/sh/intc/virq.c
+++ b/drivers/sh/intc/virq.c
@@ -235,6 +235,11 @@
irq_set_handler_data(irq, (void *)entry->handle);
+ /*
+ * Set the virtual IRQ as non-threadable.
+ */
+ irq_set_nothread(irq);
+
irq_set_chained_handler(entry->pirq, intc_virq_handler);
add_virq_to_pirq(entry->pirq, irq);
diff --git a/drivers/spi/coldfire_qspi.c b/drivers/spi/coldfire_qspi.c
index 8856bcc..ae2cd1c 100644
--- a/drivers/spi/coldfire_qspi.c
+++ b/drivers/spi/coldfire_qspi.c
@@ -33,6 +33,7 @@
#include <linux/spi/spi.h>
#include <asm/coldfire.h>
+#include <asm/mcfsim.h>
#include <asm/mcfqspi.h>
#define DRIVER_NAME "mcfqspi"
diff --git a/drivers/staging/Kconfig b/drivers/staging/Kconfig
index e3786f1..dfc16f9 100644
--- a/drivers/staging/Kconfig
+++ b/drivers/staging/Kconfig
@@ -67,10 +67,6 @@
source "drivers/staging/brcm80211/Kconfig"
-source "drivers/staging/rt2860/Kconfig"
-
-source "drivers/staging/rt2870/Kconfig"
-
source "drivers/staging/comedi/Kconfig"
source "drivers/staging/olpc_dcon/Kconfig"
@@ -177,5 +173,9 @@
source "drivers/staging/altera-stapl/Kconfig"
+source "drivers/staging/mei/Kconfig"
+
+source "drivers/staging/nvec/Kconfig"
+
endif # !STAGING_EXCLUDE_BUILD
endif # STAGING
diff --git a/drivers/staging/Makefile b/drivers/staging/Makefile
index f0d5c53..fa41b9c 100644
--- a/drivers/staging/Makefile
+++ b/drivers/staging/Makefile
@@ -12,13 +12,12 @@
obj-$(CONFIG_VIDEO_TM6000) += tm6000/
obj-$(CONFIG_DVB_CXD2099) += cxd2099/
obj-$(CONFIG_LIRC_STAGING) += lirc/
-obj-$(CONFIG_USB_IP_COMMON) += usbip/
+obj-$(CONFIG_USBIP_CORE) += usbip/
obj-$(CONFIG_W35UND) += winbond/
obj-$(CONFIG_PRISM2_USB) += wlan-ng/
obj-$(CONFIG_ECHO) += echo/
-obj-$(CONFIG_BRCM80211) += brcm80211/
-obj-$(CONFIG_RT2860) += rt2860/
-obj-$(CONFIG_RT2870) += rt2870/
+obj-$(CONFIG_BRCMSMAC) += brcm80211/
+obj-$(CONFIG_BRCMFMAC) += brcm80211/
obj-$(CONFIG_COMEDI) += comedi/
obj-$(CONFIG_FB_OLPC_DCON) += olpc_dcon/
obj-$(CONFIG_ASUS_OLED) += asus_oled/
@@ -70,3 +69,5 @@
obj-$(CONFIG_TOUCHSCREEN_CLEARPAD_TM1217) += cptm1217/
obj-$(CONFIG_TOUCHSCREEN_SYNAPTICS_I2C_RMI4) += ste_rmi4/
obj-$(CONFIG_DRM_PSB) += gma500/
+obj-$(CONFIG_INTEL_MEI) += mei/
+obj-$(CONFIG_MFD_NVEC) += nvec/
diff --git a/drivers/staging/ath6kl/Kconfig b/drivers/staging/ath6kl/Kconfig
index 8a5caa3..1f15e1f 100644
--- a/drivers/staging/ath6kl/Kconfig
+++ b/drivers/staging/ath6kl/Kconfig
@@ -100,12 +100,6 @@
help
WLAN GPIO to be used for resetting BT
-config ATH6KL_CFG80211
- bool "CFG80211 support"
- depends on ATH6K_LEGACY && CFG80211
- help
- Enables support for CFG80211 APIs. The default option is to use WEXT. Even with this option enabled, WEXT is not explicitly disabled and the onus of not exercising WEXT lies on the application(s) running in the user space.
-
config ATH6KL_HTC_RAW_INTERFACE
bool "RAW HTC support"
depends on ATH6K_LEGACY
diff --git a/drivers/staging/ath6kl/Makefile b/drivers/staging/ath6kl/Makefile
index ab68078..1d3f239 100644
--- a/drivers/staging/ath6kl/Makefile
+++ b/drivers/staging/ath6kl/Makefile
@@ -29,26 +29,6 @@
ccflags-y += -I$(obj)/bmi/include
ccflags-y += -I$(obj)/include/common/AR6002/hw4.0
-ifeq ($(CONFIG_AR600x_SD31_XXX),y)
-ccflags-y += -DAR600x_SD31_XXX
-endif
-
-ifeq ($(CONFIG_AR600x_WB31_XXX),y)
-ccflags-y += -DAR600x_WB31_XXX
-endif
-
-ifeq ($(CONFIG_AR600x_SD32_XXX),y)
-ccflags-y += -DAR600x_SD32_XXX
-endif
-
-ifeq ($(CONFIG_AR600x_CUSTOM_XXX),y)
-ccflags-y += -DAR600x_CUSTOM_XXX
-endif
-
-ifeq ($(CONFIG_ATH6KL_ENABLE_COEXISTENCE),y)
-ccflags-y += -DENABLE_COEXISTENCE
-endif
-
ifeq ($(CONFIG_AR600x_DUAL_ANTENNA),y)
ccflags-y += -DAR600x_DUAL_ANTENNA
endif
@@ -85,11 +65,6 @@
ccflags-y += -DATH6KL_CONFIG_GPIO_BT_RESET
endif
-ifeq ($(CONFIG_ATH6KL_CFG80211),y)
-ccflags-y += -DATH6K_CONFIG_CFG80211
-ath6kl-y += os/linux/cfg80211.o
-endif
-
ifeq ($(CONFIG_ATH6KL_HTC_RAW_INTERFACE),y)
ccflags-y += -DHTC_RAW_INTERFACE
endif
@@ -115,18 +90,8 @@
ccflags-y += -DATH6KL_SKIP_ABI_VERSION_CHECK
endif
-ccflags-y += -DLINUX -DKERNEL_2_6
-ccflags-y += -DTCMD
-ccflags-y += -DSEND_EVENT_TO_APP
-ccflags-y += -DUSER_KEYS
-ccflags-y += -DNO_SYNC_FLUSH
-ccflags-y += -DHTC_EP_STAT_PROFILING
-ccflags-y += -DATH_AR6K_11N_SUPPORT
ccflags-y += -DWAPI_ENABLE
ccflags-y += -DCHECKSUM_OFFLOAD
-ccflags-y += -DWLAN_HEADERS
-ccflags-y += -DINIT_MODE_DRV_ENABLED
-ccflags-y += -DBMIENABLE_SET
obj-$(CONFIG_ATH6K_LEGACY) := ath6kl.o
ath6kl-y += htc2/AR6000/ar6k.o
@@ -136,14 +101,12 @@
ath6kl-y += htc2/htc_services.o
ath6kl-y += htc2/htc.o
ath6kl-y += bmi/src/bmi.o
+ath6kl-y += os/linux/cfg80211.o
ath6kl-y += os/linux/ar6000_drv.o
ath6kl-y += os/linux/ar6000_raw_if.o
ath6kl-y += os/linux/ar6000_pm.o
ath6kl-y += os/linux/netbuf.o
-ath6kl-y += os/linux/wireless_ext.o
-ath6kl-y += os/linux/ioctl.o
ath6kl-y += os/linux/hci_bridge.o
-ath6kl-y += os/linux/ar6k_pal.o
ath6kl-y += miscdrv/common_drv.o
ath6kl-y += miscdrv/credit_dist.o
ath6kl-y += wmi/wmi.o
diff --git a/drivers/staging/ath6kl/bmi/include/bmi_internal.h b/drivers/staging/ath6kl/bmi/include/bmi_internal.h
index 6ae2ea7..8e25770 100644
--- a/drivers/staging/ath6kl/bmi/include/bmi_internal.h
+++ b/drivers/staging/ath6kl/bmi/include/bmi_internal.h
@@ -26,11 +26,10 @@
#include "a_config.h"
#include "athdefs.h"
-#include "a_types.h"
#include "a_osapi.h"
#define ATH_MODULE_NAME bmi
#include "a_debug.h"
-#include "AR6002/hw2.0/hw/mbox_host_reg.h"
+#include "hw/mbox_host_reg.h"
#include "bmi_msg.h"
#define ATH_DEBUG_BMI ATH_DEBUG_MAKE_MODULE_MASK(0)
diff --git a/drivers/staging/ath6kl/bmi/src/bmi.c b/drivers/staging/ath6kl/bmi/src/bmi.c
index 9268bf3..f1f085e 100644
--- a/drivers/staging/ath6kl/bmi/src/bmi.c
+++ b/drivers/staging/ath6kl/bmi/src/bmi.c
@@ -95,12 +95,12 @@
BMICleanup(void)
{
if (pBMICmdCredits) {
- A_FREE(pBMICmdCredits);
+ kfree(pBMICmdCredits);
pBMICmdCredits = NULL;
}
if (pBMICmdBuf) {
- A_FREE(pBMICmdBuf);
+ kfree(pBMICmdBuf);
pBMICmdBuf = NULL;
}
}
@@ -127,12 +127,12 @@
}
if (pBMICmdCredits) {
- A_FREE(pBMICmdCredits);
+ kfree(pBMICmdCredits);
pBMICmdCredits = NULL;
}
if (pBMICmdBuf) {
- A_FREE(pBMICmdBuf);
+ kfree(pBMICmdBuf);
pBMICmdBuf = NULL;
}
diff --git a/drivers/staging/ath6kl/hif/sdio/linux_sdio/include/hif_internal.h b/drivers/staging/ath6kl/hif/sdio/linux_sdio/include/hif_internal.h
index 6341560..ed7ad47 100644
--- a/drivers/staging/ath6kl/hif/sdio/linux_sdio/include/hif_internal.h
+++ b/drivers/staging/ath6kl/hif/sdio/linux_sdio/include/hif_internal.h
@@ -27,7 +27,6 @@
#include "a_config.h"
#include "athdefs.h"
-#include "a_types.h"
#include "a_osapi.h"
#include "hif.h"
#include "../../../common/hif_sdio_common.h"
diff --git a/drivers/staging/ath6kl/hif/sdio/linux_sdio/src/hif.c b/drivers/staging/ath6kl/hif/sdio/linux_sdio/src/hif.c
index e6d9cd8..5f5d677 100644
--- a/drivers/staging/ath6kl/hif/sdio/linux_sdio/src/hif.c
+++ b/drivers/staging/ath6kl/hif/sdio/linux_sdio/src/hif.c
@@ -37,7 +37,7 @@
#include "hif_internal.h"
#define ATH_MODULE_NAME hif
#include "a_debug.h"
-#include "AR6002/hw2.0/hw/mbox_host_reg.h"
+#include "hw/mbox_host_reg.h"
#if HIF_USE_DMA_BOUNCE_BUFFER
/* macro to check if DMA buffer is WORD-aligned and DMA-able. Most host controllers assume the
@@ -53,62 +53,189 @@
#if defined(CONFIG_PM)
#define dev_to_sdio_func(d) container_of(d, struct sdio_func, dev)
#define to_sdio_driver(d) container_of(d, struct sdio_driver, drv)
-static int hifDeviceSuspend(struct device *dev);
-static int hifDeviceResume(struct device *dev);
#endif /* CONFIG_PM */
-static int hifDeviceInserted(struct sdio_func *func, const struct sdio_device_id *id);
-static void hifDeviceRemoved(struct sdio_func *func);
-static struct hif_device *addHifDevice(struct sdio_func *func);
-static struct hif_device *getHifDevice(struct sdio_func *func);
static void delHifDevice(struct hif_device * device);
static int Func0_CMD52WriteByte(struct mmc_card *card, unsigned int address, unsigned char byte);
static int Func0_CMD52ReadByte(struct mmc_card *card, unsigned int address, unsigned char *byte);
+static int hifEnableFunc(struct hif_device *device, struct sdio_func *func);
+static int hifDisableFunc(struct hif_device *device, struct sdio_func *func);
+OSDRV_CALLBACKS osdrvCallbacks;
+
int reset_sdio_on_unload = 0;
module_param(reset_sdio_on_unload, int, 0644);
extern u32 nohifscattersupport;
+static struct hif_device *ath6kl_alloc_hifdev(struct sdio_func *func)
+{
+ struct hif_device *hifdevice;
-/* ------ Static Variables ------ */
-static const struct sdio_device_id ar6k_id_table[] = {
- { SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6002_BASE | 0x0)) },
- { SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6002_BASE | 0x1)) },
- { SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6003_BASE | 0x0)) },
- { SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6003_BASE | 0x1)) },
- { /* null */ },
-};
-MODULE_DEVICE_TABLE(sdio, ar6k_id_table);
+ hifdevice = kzalloc(sizeof(struct hif_device), GFP_KERNEL);
-static struct sdio_driver ar6k_driver = {
- .name = "ar6k_wlan",
- .id_table = ar6k_id_table,
- .probe = hifDeviceInserted,
- .remove = hifDeviceRemoved,
+#if HIF_USE_DMA_BOUNCE_BUFFER
+ hifdevice->dma_buffer = kmalloc(HIF_DMA_BUFFER_SIZE, GFP_KERNEL);
+#endif
+ hifdevice->func = func;
+ hifdevice->powerConfig = HIF_DEVICE_POWER_UP;
+ sdio_set_drvdata(func, hifdevice);
+
+ return hifdevice;
+}
+
+static struct hif_device *ath6kl_get_hifdev(struct sdio_func *func)
+{
+ return (struct hif_device *) sdio_get_drvdata(func);
+}
+
+static const struct sdio_device_id ath6kl_hifdev_ids[] = {
+ { SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6002_BASE | 0x0)) },
+ { SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6002_BASE | 0x1)) },
+ { SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6003_BASE | 0x0)) },
+ { SDIO_DEVICE(MANUFACTURER_CODE, (MANUFACTURER_ID_AR6003_BASE | 0x1)) },
+ { /* null */ },
};
+MODULE_DEVICE_TABLE(sdio, ath6kl_hifdev_ids);
+
+static int ath6kl_hifdev_probe(struct sdio_func *func,
+ const struct sdio_device_id *id)
+{
+ int ret;
+ struct hif_device *device;
+ int count;
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_TRACE,
+ ("ath6kl: Function: 0x%X, Vendor ID: 0x%X, "
+ "Device ID: 0x%X, block size: 0x%X/0x%X\n",
+ func->num, func->vendor, func->device,
+ func->max_blksize, func->cur_blksize));
+
+ ath6kl_alloc_hifdev(func);
+ device = ath6kl_get_hifdev(func);
+
+ device->id = id;
+ device->is_disabled = true;
+
+ spin_lock_init(&device->lock);
+ spin_lock_init(&device->asynclock);
+
+ DL_LIST_INIT(&device->ScatterReqHead);
+
+ /* Try to allow scatter unless globally overridden */
+ if (!nohifscattersupport)
+ device->scatter_enabled = true;
+
+ A_MEMZERO(device->busRequest, sizeof(device->busRequest));
+
+ for (count = 0; count < BUS_REQUEST_MAX_NUM; count++) {
+ sema_init(&device->busRequest[count].sem_req, 0);
+ hifFreeBusRequest(device, &device->busRequest[count]);
+ }
+
+ sema_init(&device->sem_async, 0);
+
+ ret = hifEnableFunc(device, func);
+
+ return ret;
+}
+
+static void ath6kl_hifdev_remove(struct sdio_func *func)
+{
+ int status = 0;
+ struct hif_device *device;
+
+ device = ath6kl_get_hifdev(func);
+ if (device->claimedContext != NULL)
+ status = osdrvCallbacks.
+ deviceRemovedHandler(device->claimedContext, device);
+
+ if (device->is_disabled)
+ device->is_disabled = false;
+ else
+ status = hifDisableFunc(device, func);
+
+ CleanupHIFScatterResources(device);
+
+ delHifDevice(device);
+}
+
#if defined(CONFIG_PM)
-/* New suspend/resume based on linux-2.6.32
- * Need to patch linux-2.6.32 with mmc2.6.32_suspend.patch
- * Need to patch with msmsdcc2.6.29_suspend.patch for msm_sdcc host
- */
-static struct dev_pm_ops ar6k_device_pm_ops = {
- .suspend = hifDeviceSuspend,
- .resume = hifDeviceResume,
+static int ath6kl_hifdev_suspend(struct device *dev)
+{
+ struct sdio_func *func = dev_to_sdio_func(dev);
+ int status = 0;
+ struct hif_device *device;
+
+ device = ath6kl_get_hifdev(func);
+
+ if (device && device->claimedContext &&
+ osdrvCallbacks.deviceSuspendHandler) {
+ /* set true first for PowerStateChangeNotify(..) */
+ device->is_suspend = true;
+ status = osdrvCallbacks.
+ deviceSuspendHandler(device->claimedContext);
+ if (status)
+ device->is_suspend = false;
+ }
+
+ CleanupHIFScatterResources(device);
+
+ switch (status) {
+ case 0:
+ return 0;
+ case A_EBUSY:
+ /* Hack for kernel in order to support deep sleep and wow */
+ return -EBUSY;
+ default:
+ return -1;
+ }
+}
+
+static int ath6kl_hifdev_resume(struct device *dev)
+{
+ struct sdio_func *func = dev_to_sdio_func(dev);
+ int status = 0;
+ struct hif_device *device;
+
+ device = ath6kl_get_hifdev(func);
+ if (device && device->claimedContext &&
+ osdrvCallbacks.deviceSuspendHandler) {
+ status = osdrvCallbacks.
+ deviceResumeHandler(device->claimedContext);
+ if (status == 0)
+ device->is_suspend = false;
+ }
+
+ return status;
+}
+
+static const struct dev_pm_ops ath6kl_hifdev_pmops = {
+ .suspend = ath6kl_hifdev_suspend,
+ .resume = ath6kl_hifdev_resume,
};
#endif /* CONFIG_PM */
+static struct sdio_driver ath6kl_hifdev_driver = {
+ .name = "ath6kl_hifdev",
+ .id_table = ath6kl_hifdev_ids,
+ .probe = ath6kl_hifdev_probe,
+ .remove = ath6kl_hifdev_remove,
+#if defined(CONFIG_PM)
+ .drv = {
+ .pm = &ath6kl_hifdev_pmops,
+ },
+#endif
+};
+
/* make sure we only unregister when registered. */
static int registered = 0;
-OSDRV_CALLBACKS osdrvCallbacks;
extern u32 onebitmode;
extern u32 busspeedlow;
extern u32 debughif;
static void ResetAllCards(void);
-static int hifDisableFunc(struct hif_device *device, struct sdio_func *func);
-static int hifEnableFunc(struct hif_device *device, struct sdio_func *func);
#ifdef DEBUG
@@ -125,31 +252,22 @@
/* ------ Functions ------ */
int HIFInit(OSDRV_CALLBACKS *callbacks)
{
- int status;
- AR_DEBUG_ASSERT(callbacks != NULL);
+ int r;
+ AR_DEBUG_ASSERT(callbacks != NULL);
- A_REGISTER_MODULE_DEBUG_INFO(hif);
+ A_REGISTER_MODULE_DEBUG_INFO(hif);
- /* store the callback handlers */
- osdrvCallbacks = *callbacks;
+ /* store the callback handlers */
+ osdrvCallbacks = *callbacks;
- /* Register with bus driver core */
- AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: HIFInit registering\n"));
- registered = 1;
-#if defined(CONFIG_PM)
- if (callbacks->deviceSuspendHandler && callbacks->deviceResumeHandler) {
- ar6k_driver.drv.pm = &ar6k_device_pm_ops;
- }
-#endif /* CONFIG_PM */
- status = sdio_register_driver(&ar6k_driver);
- AR_DEBUG_ASSERT(status==0);
+ /* Register with bus driver core */
+ registered = 1;
- if (status != 0) {
- return A_ERROR;
- }
+ r = sdio_register_driver(&ath6kl_hifdev_driver);
+ if (r < 0)
+ return r;
- return 0;
-
+ return 0;
}
static int
@@ -763,7 +881,7 @@
registered = 0;
AR_DEBUG_PRINTF(ATH_DEBUG_TRACE,
("AR6000: Unregistering with the bus driver\n"));
- sdio_unregister_driver(&ar6k_driver);
+ sdio_unregister_driver(&ath6kl_hifdev_driver);
AR_DEBUG_PRINTF(ATH_DEBUG_TRACE,
("AR6000: Unregistered\n"));
}
@@ -778,7 +896,7 @@
struct hif_device *device;
AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: +hifIRQHandler\n"));
- device = getHifDevice(func);
+ device = ath6kl_get_hifdev(func);
atomic_set(&device->irqHandling, 1);
/* release the host during ints so we can pick it back up when we process cmds */
sdio_release_host(device->func);
@@ -823,48 +941,6 @@
}
#endif
-static int hifDeviceInserted(struct sdio_func *func, const struct sdio_device_id *id)
-{
- int ret;
- struct hif_device * device;
- int count;
-
- AR_DEBUG_PRINTF(ATH_DEBUG_TRACE,
- ("AR6000: hifDeviceInserted, Function: 0x%X, Vendor ID: 0x%X, Device ID: 0x%X, block size: 0x%X/0x%X\n",
- func->num, func->vendor, func->device, func->max_blksize, func->cur_blksize));
-
- addHifDevice(func);
- device = getHifDevice(func);
-
- device->id = id;
- device->is_disabled = true;
-
- spin_lock_init(&device->lock);
-
- spin_lock_init(&device->asynclock);
-
- DL_LIST_INIT(&device->ScatterReqHead);
-
- if (!nohifscattersupport) {
- /* try to allow scatter operation on all instances,
- * unless globally overridden */
- device->scatter_enabled = true;
- }
-
- /* Initialize the bus requests to be used later */
- A_MEMZERO(device->busRequest, sizeof(device->busRequest));
- for (count = 0; count < BUS_REQUEST_MAX_NUM; count ++) {
- sema_init(&device->busRequest[count].sem_req, 0);
- hifFreeBusRequest(device, &device->busRequest[count]);
- }
- sema_init(&device->sem_async, 0);
-
- ret = hifEnableFunc(device, func);
-
- return ret;
-}
-
-
void
HIFAckInterrupt(struct hif_device *device)
{
@@ -955,7 +1031,7 @@
int status = 0;
AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: +hifDisableFunc\n"));
- device = getHifDevice(func);
+ device = ath6kl_get_hifdev(func);
if (!IS_ERR(device->async_task)) {
init_completion(&device->async_completion);
device->async_shutdown = 1;
@@ -1004,7 +1080,7 @@
int ret = 0;
AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: +hifEnableFunc\n"));
- device = getHifDevice(func);
+ device = ath6kl_get_hifdev(func);
if (device->is_disabled) {
/* enable the SDIO function */
@@ -1016,7 +1092,7 @@
if (ret) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("AR6000: failed to enable 4-bit ASYNC IRQ mode %d \n",ret));
sdio_release_host(func);
- return A_ERROR;
+ return ret;
}
AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: 4-bit ASYNC IRQ mode enabled\n"));
}
@@ -1027,14 +1103,14 @@
AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("AR6000: %s(), Unable to enable AR6K: 0x%X\n",
__FUNCTION__, ret));
sdio_release_host(func);
- return A_ERROR;
+ return ret;
}
ret = sdio_set_block_size(func, HIF_MBOX_BLOCK_SIZE);
sdio_release_host(func);
if (ret) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("AR6000: %s(), Unable to set block size 0x%x AR6K: 0x%X\n",
__FUNCTION__, HIF_MBOX_BLOCK_SIZE, ret));
- return A_ERROR;
+ return ret;
}
device->is_disabled = false;
/* create async I/O thread */
@@ -1045,7 +1121,7 @@
"AR6K Async");
if (IS_ERR(device->async_task)) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("AR6000: %s(), to create async task\n", __FUNCTION__));
- return A_ERROR;
+ return -ENOMEM;
}
AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: start async task\n"));
wake_up_process(device->async_task );
@@ -1060,14 +1136,14 @@
} else {
taskFunc = enable_task;
taskName = "AR6K enable";
- ret = A_PENDING;
+ ret = -ENOMEM;
#endif /* CONFIG_PM */
}
/* create resume thread */
pTask = kthread_create(taskFunc, (void *)device, taskName);
if (IS_ERR(pTask)) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERROR, ("AR6000: %s(), to create enabel task\n", __FUNCTION__));
- return A_ERROR;
+ return -ENOMEM;
}
wake_up_process(pTask);
AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: -hifEnableFunc\n"));
@@ -1076,79 +1152,6 @@
return ret;
}
-#if defined(CONFIG_PM)
-static int hifDeviceSuspend(struct device *dev)
-{
- struct sdio_func *func=dev_to_sdio_func(dev);
- int status = 0;
- struct hif_device *device;
-
- device = getHifDevice(func);
- AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: +hifDeviceSuspend\n"));
- if (device && device->claimedContext && osdrvCallbacks.deviceSuspendHandler) {
- device->is_suspend = true; /* set true first for PowerStateChangeNotify(..) */
- status = osdrvCallbacks.deviceSuspendHandler(device->claimedContext);
- if (status) {
- device->is_suspend = false;
- }
- }
- CleanupHIFScatterResources(device);
- AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: -hifDeviceSuspend\n"));
-
- switch (status) {
- case 0:
- return 0;
- case A_EBUSY:
- return -EBUSY; /* Hack for kernel in order to support deep sleep and wow */
- default:
- return -1;
- }
-}
-
-static int hifDeviceResume(struct device *dev)
-{
- struct sdio_func *func=dev_to_sdio_func(dev);
- int status = 0;
- struct hif_device *device;
-
- device = getHifDevice(func);
- AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: +hifDeviceResume\n"));
- if (device && device->claimedContext && osdrvCallbacks.deviceSuspendHandler) {
- status = osdrvCallbacks.deviceResumeHandler(device->claimedContext);
- if (status == 0) {
- device->is_suspend = false;
- }
- }
- AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: -hifDeviceResume\n"));
-
- return status;
-}
-#endif /* CONFIG_PM */
-
-static void hifDeviceRemoved(struct sdio_func *func)
-{
- int status = 0;
- struct hif_device *device;
- AR_DEBUG_ASSERT(func != NULL);
-
- AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: +hifDeviceRemoved\n"));
- device = getHifDevice(func);
- if (device->claimedContext != NULL) {
- status = osdrvCallbacks.deviceRemovedHandler(device->claimedContext, device);
- }
-
- if (device->is_disabled) {
- device->is_disabled = false;
- } else {
- status = hifDisableFunc(device, func);
- }
- CleanupHIFScatterResources(device);
-
- delHifDevice(device);
- AR_DEBUG_ASSERT(status == 0);
- AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: -hifDeviceRemoved\n"));
-}
-
/*
* This should be moved to AR6K HTC layer.
*/
@@ -1182,33 +1185,6 @@
return 0;
}
-
-static struct hif_device *
-addHifDevice(struct sdio_func *func)
-{
- struct hif_device *hifdevice;
- AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: addHifDevice\n"));
- AR_DEBUG_ASSERT(func != NULL);
- hifdevice = kzalloc(sizeof(struct hif_device), GFP_KERNEL);
- AR_DEBUG_ASSERT(hifdevice != NULL);
-#if HIF_USE_DMA_BOUNCE_BUFFER
- hifdevice->dma_buffer = kmalloc(HIF_DMA_BUFFER_SIZE, GFP_KERNEL);
- AR_DEBUG_ASSERT(hifdevice->dma_buffer != NULL);
-#endif
- hifdevice->func = func;
- hifdevice->powerConfig = HIF_DEVICE_POWER_UP;
- sdio_set_drvdata(func, hifdevice);
- AR_DEBUG_PRINTF(ATH_DEBUG_TRACE, ("AR6000: addHifDevice; 0x%p\n", hifdevice));
- return hifdevice;
-}
-
-static struct hif_device *
-getHifDevice(struct sdio_func *func)
-{
- AR_DEBUG_ASSERT(func != NULL);
- return (struct hif_device *)sdio_get_drvdata(func);
-}
-
static void
delHifDevice(struct hif_device * device)
{
diff --git a/drivers/staging/ath6kl/hif/sdio/linux_sdio/src/hif_scatter.c b/drivers/staging/ath6kl/hif/sdio/linux_sdio/src/hif_scatter.c
index a1fdcc1..7516d91 100644
--- a/drivers/staging/ath6kl/hif/sdio/linux_sdio/src/hif_scatter.c
+++ b/drivers/staging/ath6kl/hif/sdio/linux_sdio/src/hif_scatter.c
@@ -309,7 +309,7 @@
(MAX_SCATTER_ENTRIES_PER_REQ - 1) * (sizeof(struct hif_scatter_item)));
if (NULL == pReqPriv->pHifScatterReq) {
- A_FREE(pReqPriv);
+ kfree(pReqPriv);
break;
}
/* just zero the main part of the scatter request */
@@ -319,8 +319,8 @@
/* allocate a bus request for this scatter request */
busrequest = hifAllocateBusRequest(device);
if (NULL == busrequest) {
- A_FREE(pReqPriv->pHifScatterReq);
- A_FREE(pReqPriv);
+ kfree(pReqPriv->pHifScatterReq);
+ kfree(pReqPriv);
break;
}
/* assign the scatter request to this bus request */
@@ -382,11 +382,11 @@
}
if (pReqPriv->pHifScatterReq != NULL) {
- A_FREE(pReqPriv->pHifScatterReq);
+ kfree(pReqPriv->pHifScatterReq);
pReqPriv->pHifScatterReq = NULL;
}
- A_FREE(pReqPriv);
+ kfree(pReqPriv);
}
}
diff --git a/drivers/staging/ath6kl/htc2/AR6000/ar6k.c b/drivers/staging/ath6kl/htc2/AR6000/ar6k.c
index eeddf60..f8607bc 100644
--- a/drivers/staging/ath6kl/htc2/AR6000/ar6k.c
+++ b/drivers/staging/ath6kl/htc2/AR6000/ar6k.c
@@ -25,8 +25,7 @@
#include "a_config.h"
#include "athdefs.h"
-#include "a_types.h"
-#include "AR6002/hw2.0/hw/mbox_host_reg.h"
+#include "hw/mbox_host_reg.h"
#include "a_osapi.h"
#include "../htc_debug.h"
#include "hif.h"
@@ -743,7 +742,7 @@
if (NULL == pReq) {
break;
}
- A_FREE(pReq);
+ kfree(pReq);
}
}
diff --git a/drivers/staging/ath6kl/htc2/AR6000/ar6k.h b/drivers/staging/ath6kl/htc2/AR6000/ar6k.h
index 1ff2218..e551dbe 100644
--- a/drivers/staging/ath6kl/htc2/AR6000/ar6k.h
+++ b/drivers/staging/ath6kl/htc2/AR6000/ar6k.h
@@ -42,7 +42,6 @@
//#define MBOXHW_UNIT_TEST 1
-#include "athstartpack.h"
PREPACK struct ar6k_irq_proc_registers {
u8 host_int_status;
u8 cpu_int_status;
@@ -69,8 +68,6 @@
u8 int_status_enable;
} POSTPACK;
-#include "athendpack.h"
-
#define AR6K_IRQ_ENABLE_REGS_SIZE sizeof(struct ar6k_irq_enable_registers)
#define AR6K_REG_IO_BUFFER_SIZE 32
diff --git a/drivers/staging/ath6kl/htc2/AR6000/ar6k_events.c b/drivers/staging/ath6kl/htc2/AR6000/ar6k_events.c
index 5e6d1e0..d7af68f 100644
--- a/drivers/staging/ath6kl/htc2/AR6000/ar6k_events.c
+++ b/drivers/staging/ath6kl/htc2/AR6000/ar6k_events.c
@@ -25,8 +25,7 @@
#include "a_config.h"
#include "athdefs.h"
-#include "a_types.h"
-#include "AR6002/hw2.0/hw/mbox_host_reg.h"
+#include "hw/mbox_host_reg.h"
#include "a_osapi.h"
#include "../htc_debug.h"
#include "hif.h"
diff --git a/drivers/staging/ath6kl/htc2/AR6000/ar6k_gmbox.c b/drivers/staging/ath6kl/htc2/AR6000/ar6k_gmbox.c
index 3740011..725540f 100644
--- a/drivers/staging/ath6kl/htc2/AR6000/ar6k_gmbox.c
+++ b/drivers/staging/ath6kl/htc2/AR6000/ar6k_gmbox.c
@@ -24,7 +24,6 @@
//==============================================================================
#include "a_config.h"
#include "athdefs.h"
-#include "a_types.h"
#include "a_osapi.h"
#include "../htc_debug.h"
#include "hif.h"
diff --git a/drivers/staging/ath6kl/htc2/AR6000/ar6k_gmbox_hciuart.c b/drivers/staging/ath6kl/htc2/AR6000/ar6k_gmbox_hciuart.c
index 41223f9..56a0d71 100644
--- a/drivers/staging/ath6kl/htc2/AR6000/ar6k_gmbox_hciuart.c
+++ b/drivers/staging/ath6kl/htc2/AR6000/ar6k_gmbox_hciuart.c
@@ -24,7 +24,6 @@
//==============================================================================
#include "a_config.h"
#include "athdefs.h"
-#include "a_types.h"
#include "a_osapi.h"
#include "../htc_debug.h"
#include "hif.h"
@@ -108,7 +107,7 @@
A_MUTEX_DELETE(&pProtocol->HCIRxLock);
A_MUTEX_DELETE(&pProtocol->HCITxLock);
- A_FREE(pProtocol);
+ kfree(pProtocol);
}
static int InitTxCreditState(struct gmbox_proto_hci_uart *pProt)
diff --git a/drivers/staging/ath6kl/htc2/htc.c b/drivers/staging/ath6kl/htc2/htc.c
index d40bb14..ae54e64 100644
--- a/drivers/staging/ath6kl/htc2/htc.c
+++ b/drivers/staging/ath6kl/htc2/htc.c
@@ -70,7 +70,7 @@
for (i = 0;i < NUM_CONTROL_BUFFERS;i++) {
if (target->HTCControlBuffers[i].Buffer) {
- A_FREE(target->HTCControlBuffers[i].Buffer);
+ kfree(target->HTCControlBuffers[i].Buffer);
}
}
@@ -86,7 +86,7 @@
A_MUTEX_DELETE(&target->HTCTxLock);
}
/* free our instance */
- A_FREE(target);
+ kfree(target);
}
/* registered target arrival callback from the HIF layer */
@@ -448,9 +448,7 @@
pEndpoint->ServiceID = 0;
pEndpoint->MaxMsgLength = 0;
pEndpoint->MaxTxQueueDepth = 0;
-#ifdef HTC_EP_STAT_PROFILING
A_MEMZERO(&pEndpoint->EndPointStats,sizeof(pEndpoint->EndPointStats));
-#endif
INIT_HTC_PACKET_QUEUE(&pEndpoint->RxBuffers);
INIT_HTC_PACKET_QUEUE(&pEndpoint->TxQueue);
INIT_HTC_PACKET_QUEUE(&pEndpoint->RecvIndicationQueue);
@@ -527,7 +525,6 @@
struct htc_endpoint_stats *pStats)
{
-#ifdef HTC_EP_STAT_PROFILING
struct htc_target *target = GET_HTC_TARGET_FROM_HANDLE(HTCHandle);
bool clearStats = false;
bool sample = false;
@@ -568,9 +565,6 @@
UNLOCK_HTC_TX(target);
return true;
-#else
- return false;
-#endif
}
struct ar6k_device *HTCGetAR6KDevice(void *HTCHandle)
diff --git a/drivers/staging/ath6kl/htc2/htc_internal.h b/drivers/staging/ath6kl/htc2/htc_internal.h
index 9425ed9..cac9735 100644
--- a/drivers/staging/ath6kl/htc2/htc_internal.h
+++ b/drivers/staging/ath6kl/htc2/htc_internal.h
@@ -27,7 +27,6 @@
* processing errors, the last frame header is dump for comparison */
//#define HTC_CAPTURE_LAST_FRAME
-//#define HTC_EP_STAT_PROFILING
#ifdef __cplusplus
extern "C" {
@@ -37,7 +36,6 @@
#include "a_config.h"
#include "athdefs.h"
-#include "a_types.h"
#include "a_osapi.h"
#include "htc_debug.h"
#include "htc.h"
@@ -82,17 +80,10 @@
struct htc_target *target; /* back pointer to target */
u8 SeqNo; /* TX seq no (helpful) for debugging */
u32 LocalConnectionFlags; /* local connection flags */
-#ifdef HTC_EP_STAT_PROFILING
struct htc_endpoint_stats EndPointStats; /* endpoint statistics */
-#endif
};
-#ifdef HTC_EP_STAT_PROFILING
#define INC_HTC_EP_STAT(p,stat,count) (p)->EndPointStats.stat += (count);
-#else
-#define INC_HTC_EP_STAT(p,stat,count)
-#endif
-
#define HTC_SERVICE_TX_PACKET_TAG HTC_TX_PACKET_TAG_INTERNAL
#define NUM_CONTROL_BUFFERS 8
diff --git a/drivers/staging/ath6kl/htc2/htc_recv.c b/drivers/staging/ath6kl/htc2/htc_recv.c
index c208801..974cc8c 100644
--- a/drivers/staging/ath6kl/htc2/htc_recv.c
+++ b/drivers/staging/ath6kl/htc2/htc_recv.c
@@ -36,7 +36,6 @@
(pP)->PktInfo.AsRx.ExpectedHdr, \
(pP)->Endpoint))
-#ifdef HTC_EP_STAT_PROFILING
#define HTC_RX_STAT_PROFILE(t,ep,numLookAheads) \
{ \
INC_HTC_EP_STAT((ep), RxReceived, 1); \
@@ -46,9 +45,6 @@
INC_HTC_EP_STAT((ep), RxBundleLookAheads, 1); \
} \
}
-#else
-#define HTC_RX_STAT_PROFILE(t,ep,lookAhead)
-#endif
static void DoRecvCompletion(struct htc_endpoint *pEndpoint,
struct htc_packet_queue *pQueueToIndicate)
@@ -931,12 +927,10 @@
}
if (!status) {
-#ifdef HTC_EP_STAT_PROFILING
LOCK_HTC_RX(target);
HTC_RX_STAT_PROFILE(target,pEndpoint,numLookAheads);
INC_HTC_EP_STAT(pEndpoint, RxPacketsBundled, 1);
UNLOCK_HTC_RX(target);
-#endif
if (i == (pScatterReq->ValidScatterEntries - 1)) {
/* last packet's more packets flag is set based on the lookahead */
SET_MORE_RX_PACKET_INDICATION_FLAG(lookAheads,numLookAheads,pEndpoint,pPacket);
diff --git a/drivers/staging/ath6kl/htc2/htc_send.c b/drivers/staging/ath6kl/htc2/htc_send.c
index 6f4050a..9310d4d 100644
--- a/drivers/staging/ath6kl/htc2/htc_send.c
+++ b/drivers/staging/ath6kl/htc2/htc_send.c
@@ -776,9 +776,6 @@
AR_DEBUG_PRINTF(ATH_DEBUG_SEND, (" Endpoint %d got %d credits \n",
pRpt->EndpointID, pRpt->Credits));
-
-#ifdef HTC_EP_STAT_PROFILING
-
INC_HTC_EP_STAT(pEndpoint, TxCreditRpts, 1);
INC_HTC_EP_STAT(pEndpoint, TxCreditsReturned, pRpt->Credits);
@@ -797,8 +794,6 @@
INC_HTC_EP_STAT(pEndpoint, TxCreditRptsFromOther, 1);
}
-#endif
-
if (ENDPOINT_0 == pRpt->EndpointID) {
/* always give endpoint 0 credits back */
pEndpoint->CreditDist.TxCredits += pRpt->Credits;
diff --git a/drivers/staging/ath6kl/include/a_config.h b/drivers/staging/ath6kl/include/a_config.h
index 4a0083c..f7c0931 100644
--- a/drivers/staging/ath6kl/include/a_config.h
+++ b/drivers/staging/ath6kl/include/a_config.h
@@ -26,28 +26,6 @@
#ifndef _A_CONFIG_H_
#define _A_CONFIG_H_
-#ifdef UNDER_NWIFI
-#include "../os/windows/include/config.h"
-#endif
-
-#ifdef ATHR_CE_LEGACY
-#include "../os/windows/include/config.h"
-#endif
-
-#if defined(__linux__) && !defined(LINUX_EMULATION)
#include "../os/linux/include/config_linux.h"
-#endif
-
-#ifdef REXOS
-#include "../os/rexos/include/common/config_rexos.h"
-#endif
-
-#ifdef WIN_NWF
-#include "../os/windows/include/win/config_win.h"
-#endif
-
-#ifdef THREADX
-#include "../os/threadx/include/common/config_threadx.h"
-#endif
#endif
diff --git a/drivers/staging/ath6kl/include/a_debug.h b/drivers/staging/ath6kl/include/a_debug.h
index d433942..5154fcb 100644
--- a/drivers/staging/ath6kl/include/a_debug.h
+++ b/drivers/staging/ath6kl/include/a_debug.h
@@ -27,7 +27,6 @@
extern "C" {
#endif /* __cplusplus */
-#include <a_types.h>
#include <a_osapi.h>
/* standard debug print masks bits 0..7 */
@@ -187,35 +186,7 @@
void a_module_debug_support_init(void);
void a_module_debug_support_cleanup(void);
-#ifdef UNDER_NWIFI
-#include "../os/windows/include/debug.h"
-#endif
-
-#ifdef ATHR_CE_LEGACY
-#include "../os/windows/include/debug.h"
-#endif
-
-#if defined(__linux__) && !defined(LINUX_EMULATION)
#include "../os/linux/include/debug_linux.h"
-#endif
-
-#ifdef REXOS
-#include "../os/rexos/include/common/debug_rexos.h"
-#endif
-
-#if defined ART_WIN
-#include "../os/win_art/include/debug_win.h"
-#endif
-
-#ifdef WIN_NWF
-#include <debug_win.h>
-#endif
-
-#ifdef THREADX
-#define ATH_DEBUG_MAKE_MODULE_MASK(index) (1 << (ATH_DEBUG_MODULE_MASK_SHIFT + (index)))
-#include "../os/threadx/include/common/debug_threadx.h"
-#endif
-
#ifdef __cplusplus
}
diff --git a/drivers/staging/ath6kl/include/a_drv.h b/drivers/staging/ath6kl/include/a_drv.h
index 6db10f0..1548604 100644
--- a/drivers/staging/ath6kl/include/a_drv.h
+++ b/drivers/staging/ath6kl/include/a_drv.h
@@ -27,28 +27,6 @@
#ifndef _A_DRV_H_
#define _A_DRV_H_
-#if defined(__linux__) && !defined(LINUX_EMULATION)
#include "../os/linux/include/athdrv_linux.h"
-#endif
-
-#ifdef UNDER_NWIFI
-#include "../os/windows/include/athdrv.h"
-#endif
-
-#ifdef ATHR_CE_LEGACY
-#include "../os/windows/include/athdrv.h"
-#endif
-
-#ifdef REXOS
-#include "../os/rexos/include/common/athdrv_rexos.h"
-#endif
-
-#ifdef WIN_NWF
-#include "../os/windows/include/athdrv.h"
-#endif
-
-#ifdef THREADX
-#include "../os/threadx/include/common/athdrv_threadx.h"
-#endif
#endif /* _ADRV_H_ */
diff --git a/drivers/staging/ath6kl/include/a_drv_api.h b/drivers/staging/ath6kl/include/a_drv_api.h
index 5e098cb..a40d97a 100644
--- a/drivers/staging/ath6kl/include/a_drv_api.h
+++ b/drivers/staging/ath6kl/include/a_drv_api.h
@@ -130,34 +130,6 @@
#define A_WMI_PEER_EVENT(devt, eventCode, bssid) \
ar6000_peer_event ((devt), (eventCode), (bssid))
-#ifdef CONFIG_HOST_GPIO_SUPPORT
-
-#define A_WMI_GPIO_INTR_RX(intr_mask, input_values) \
- ar6000_gpio_intr_rx((intr_mask), (input_values))
-
-#define A_WMI_GPIO_DATA_RX(reg_id, value) \
- ar6000_gpio_data_rx((reg_id), (value))
-
-#define A_WMI_GPIO_ACK_RX() \
- ar6000_gpio_ack_rx()
-
-#endif
-
-#ifdef SEND_EVENT_TO_APP
-
-#define A_WMI_SEND_EVENT_TO_APP(ar, eventId, datap, len) \
- ar6000_send_event_to_app((ar), (eventId), (datap), (len))
-
-#define A_WMI_SEND_GENERIC_EVENT_TO_APP(ar, eventId, datap, len) \
- ar6000_send_generic_event_to_app((ar), (eventId), (datap), (len))
-
-#else
-
-#define A_WMI_SEND_EVENT_TO_APP(ar, eventId, datap, len)
-#define A_WMI_SEND_GENERIC_EVENT_TO_APP(ar, eventId, datap, len)
-
-#endif
-
#ifdef CONFIG_HOST_TCMD_SUPPORT
#define A_WMI_TCMD_RX_REPORT_EVENT(devt, results, len) \
ar6000_tcmd_rx_report_event((devt), (results), (len))
diff --git a/drivers/staging/ath6kl/include/a_osapi.h b/drivers/staging/ath6kl/include/a_osapi.h
index 7bdeeea..fd7ae0d 100644
--- a/drivers/staging/ath6kl/include/a_osapi.h
+++ b/drivers/staging/ath6kl/include/a_osapi.h
@@ -27,35 +27,6 @@
#ifndef _A_OSAPI_H_
#define _A_OSAPI_H_
-#if defined(__linux__) && !defined(LINUX_EMULATION)
#include "../os/linux/include/osapi_linux.h"
-#endif
-
-#ifdef UNDER_NWIFI
-#include "../os/windows/include/osapi.h"
-#include "../os/windows/include/netbuf.h"
-#endif
-
-#ifdef ATHR_CE_LEGACY
-#include "../os/windows/include/osapi.h"
-#include "../os/windows/include/netbuf.h"
-#endif
-
-#ifdef REXOS
-#include "../os/rexos/include/common/osapi_rexos.h"
-#endif
-
-#if defined ART_WIN
-#include "../os/win_art/include/osapi_win.h"
-#include "../os/win_art/include/netbuf.h"
-#endif
-
-#ifdef WIN_NWF
-#include <osapi_win.h>
-#endif
-
-#if defined(THREADX)
-#include "../os/threadx/include/common/osapi_threadx.h"
-#endif
#endif /* _OSAPI_H_ */
diff --git a/drivers/staging/ath6kl/include/a_types.h b/drivers/staging/ath6kl/include/a_types.h
deleted file mode 100644
index 18f4cfe..0000000
--- a/drivers/staging/ath6kl/include/a_types.h
+++ /dev/null
@@ -1,58 +0,0 @@
-//------------------------------------------------------------------------------
-// <copyright file="a_types.h" company="Atheros">
-// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
-//
-//
-// Permission to use, copy, modify, and/or distribute this software for any
-// purpose with or without fee is hereby granted, provided that the above
-// copyright notice and this permission notice appear in all copies.
-//
-// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-//
-//
-//------------------------------------------------------------------------------
-//==============================================================================
-// This file contains the definitions of the basic atheros data types.
-// It is used to map the data types in atheros files to a platform specific
-// type.
-//
-// Author(s): ="Atheros"
-//==============================================================================
-#ifndef _A_TYPES_H_
-#define _A_TYPES_H_
-
-#if defined(__linux__) && !defined(LINUX_EMULATION)
-#include "../os/linux/include/athtypes_linux.h"
-#endif
-
-#ifdef UNDER_NWIFI
-#include "../os/windows/include/athtypes.h"
-#endif
-
-#ifdef ATHR_CE_LEGACY
-#include "../os/windows/include/athtypes.h"
-#endif
-
-#ifdef REXOS
-#include "../os/rexos/include/common/athtypes_rexos.h"
-#endif
-
-#if defined ART_WIN
-#include "../os/win_art/include/athtypes_win.h"
-#endif
-
-#ifdef WIN_NWF
-#include <athtypes_win.h>
-#endif
-
-#ifdef THREADX
-#include "../os/threadx/include/common/athtypes_threadx.h"
-#endif
-
-#endif /* _ATHTYPES_H_ */
diff --git a/drivers/staging/ath6kl/include/ar6000_api.h b/drivers/staging/ath6kl/include/ar6000_api.h
index 1e1d92a..e946080 100644
--- a/drivers/staging/ath6kl/include/ar6000_api.h
+++ b/drivers/staging/ath6kl/include/ar6000_api.h
@@ -26,29 +26,7 @@
#ifndef _AR6000_API_H_
#define _AR6000_API_H_
-#if defined(__linux__) && !defined(LINUX_EMULATION)
#include "../os/linux/include/ar6xapi_linux.h"
-#endif
-
-#ifdef UNDER_NWIFI
-#include "../os/windows/include/ar6xapi.h"
-#endif
-
-#ifdef ATHR_CE_LEGACY
-#include "../os/windows/include/ar6xapi.h"
-#endif
-
-#ifdef REXOS
-#include "../os/rexos/include/common/ar6xapi_rexos.h"
-#endif
-
-#if defined ART_WIN
-#include "../os/win_art/include/ar6xapi_win.h"
-#endif
-
-#ifdef WIN_NWF
-#include "../os/windows/include/ar6xapi.h"
-#endif
#endif /* _AR6000_API_H */
diff --git a/drivers/staging/ath6kl/include/athendpack.h b/drivers/staging/ath6kl/include/athendpack.h
deleted file mode 100644
index 1b94050..0000000
--- a/drivers/staging/ath6kl/include/athendpack.h
+++ /dev/null
@@ -1,52 +0,0 @@
-//------------------------------------------------------------------------------
-// <copyright file="athendpack.h" company="Atheros">
-// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
-//
-//
-// Permission to use, copy, modify, and/or distribute this software for any
-// purpose with or without fee is hereby granted, provided that the above
-// copyright notice and this permission notice appear in all copies.
-//
-// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-//
-//
-//------------------------------------------------------------------------------
-//==============================================================================
-// end compiler-specific structure packing
-//
-// Author(s): ="Atheros"
-//==============================================================================
-#ifdef VXWORKS
-#endif /* VXWORKS */
-
-#if defined(LINUX) || defined(__linux__)
-#endif /* LINUX */
-
-#ifdef QNX
-#endif /* QNX */
-
-#ifdef INTEGRITY
-#include "integrity/athendpack_integrity.h"
-#endif /* INTEGRITY */
-
-#ifdef NUCLEUS
-#endif /* NUCLEUS */
-
-
-#ifdef UNDER_NWIFI
-#include "../os/windows/include/athendpack.h"
-#endif
-
-#ifdef ATHR_CE_LEGACY
-#include "../os/windows/include/athendpack.h"
-#endif /* WINCE */
-
-#ifdef WIN_NWF
-#include <athendpack_win.h>
-#endif
diff --git a/drivers/staging/ath6kl/include/athstartpack.h b/drivers/staging/ath6kl/include/athstartpack.h
deleted file mode 100644
index 1c45f66..0000000
--- a/drivers/staging/ath6kl/include/athstartpack.h
+++ /dev/null
@@ -1,55 +0,0 @@
-//------------------------------------------------------------------------------
-// <copyright file="athstartpack.h" company="Atheros">
-// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
-//
-//
-// Permission to use, copy, modify, and/or distribute this software for any
-// purpose with or without fee is hereby granted, provided that the above
-// copyright notice and this permission notice appear in all copies.
-//
-// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-//
-//
-//------------------------------------------------------------------------------
-//==============================================================================
-// start compiler-specific structure packing
-//
-// Author(s): ="Atheros"
-//==============================================================================
-#ifdef VXWORKS
-#endif /* VXWORKS */
-
-#if defined(LINUX) || defined(__linux__)
-#endif /* LINUX */
-
-#ifdef QNX
-#endif /* QNX */
-
-#ifdef INTEGRITY
-#include "integrity/athstartpack_integrity.h"
-#endif /* INTEGRITY */
-
-#ifdef NUCLEUS
-#endif /* NUCLEUS */
-
-#ifdef UNDER_NWIFI
-#include "../os/windows/include/athstartpack.h"
-#endif
-
-#ifdef ATHR_CE_LEGACY
-#include "../os/windows/include/athstartpack.h"
-#endif /* WINCE */
-
-#ifdef WIN_NWF
-#include <athstartpack_win.h>
-#endif
-
-#ifdef THREADX
-#include "../os/threadx/include/common/osapi_threadx.h"
-#endif
diff --git a/drivers/staging/ath6kl/include/bmi.h b/drivers/staging/ath6kl/include/bmi.h
index eb1e756..d3227f7 100644
--- a/drivers/staging/ath6kl/include/bmi.h
+++ b/drivers/staging/ath6kl/include/bmi.h
@@ -32,7 +32,6 @@
/* Header files */
#include "a_config.h"
#include "athdefs.h"
-#include "a_types.h"
#include "hif.h"
#include "a_osapi.h"
#include "bmi_msg.h"
diff --git a/drivers/staging/ath6kl/include/common/AR6002/AR6002_regdump.h b/drivers/staging/ath6kl/include/common/AR6002/AR6002_regdump.h
deleted file mode 100644
index 4a9b275..0000000
--- a/drivers/staging/ath6kl/include/common/AR6002/AR6002_regdump.h
+++ /dev/null
@@ -1,60 +0,0 @@
-//------------------------------------------------------------------------------
-// Copyright (c) 2006-2010 Atheros Corporation. All rights reserved.
-//
-//
-// Permission to use, copy, modify, and/or distribute this software for any
-// purpose with or without fee is hereby granted, provided that the above
-// copyright notice and this permission notice appear in all copies.
-//
-// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-//
-//
-//------------------------------------------------------------------------------
-//==============================================================================
-// Author(s): ="Atheros"
-//==============================================================================
-
-#ifndef __AR6002_REGDUMP_H__
-#define __AR6002_REGDUMP_H__
-
-#if !defined(__ASSEMBLER__)
-/*
- * XTensa CPU state
- * This must match the state saved by the target exception handler.
- */
-struct XTensa_exception_frame_s {
- u32 xt_pc;
- u32 xt_ps;
- u32 xt_sar;
- u32 xt_vpri;
- u32 xt_a2;
- u32 xt_a3;
- u32 xt_a4;
- u32 xt_a5;
- u32 xt_exccause;
- u32 xt_lcount;
- u32 xt_lbeg;
- u32 xt_lend;
-
- u32 epc1, epc2, epc3, epc4;
-
- /* Extra info to simplify post-mortem stack walkback */
-#define AR6002_REGDUMP_FRAMES 10
- struct {
- u32 a0; /* pc */
- u32 a1; /* sp */
- u32 a2;
- u32 a3;
- } wb[AR6002_REGDUMP_FRAMES];
-};
-typedef struct XTensa_exception_frame_s CPU_exception_frame_t;
-#define RD_SIZE sizeof(CPU_exception_frame_t)
-
-#endif
-#endif /* __AR6002_REGDUMP_H__ */
diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw2.0/hw/analog_intf_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw2.0/hw/analog_intf_reg.h
deleted file mode 100644
index 9c82767..0000000
--- a/drivers/staging/ath6kl/include/common/AR6002/hw2.0/hw/analog_intf_reg.h
+++ /dev/null
@@ -1,64 +0,0 @@
-#ifndef _ANALOG_INTF_REG_REG_H_
-#define _ANALOG_INTF_REG_REG_H_
-
-#define SW_OVERRIDE_ADDRESS 0x00000080
-#define SW_OVERRIDE_OFFSET 0x00000080
-#define SW_OVERRIDE_SUPDATE_DELAY_MSB 1
-#define SW_OVERRIDE_SUPDATE_DELAY_LSB 1
-#define SW_OVERRIDE_SUPDATE_DELAY_MASK 0x00000002
-#define SW_OVERRIDE_SUPDATE_DELAY_GET(x) (((x) & SW_OVERRIDE_SUPDATE_DELAY_MASK) >> SW_OVERRIDE_SUPDATE_DELAY_LSB)
-#define SW_OVERRIDE_SUPDATE_DELAY_SET(x) (((x) << SW_OVERRIDE_SUPDATE_DELAY_LSB) & SW_OVERRIDE_SUPDATE_DELAY_MASK)
-#define SW_OVERRIDE_ENABLE_MSB 0
-#define SW_OVERRIDE_ENABLE_LSB 0
-#define SW_OVERRIDE_ENABLE_MASK 0x00000001
-#define SW_OVERRIDE_ENABLE_GET(x) (((x) & SW_OVERRIDE_ENABLE_MASK) >> SW_OVERRIDE_ENABLE_LSB)
-#define SW_OVERRIDE_ENABLE_SET(x) (((x) << SW_OVERRIDE_ENABLE_LSB) & SW_OVERRIDE_ENABLE_MASK)
-
-#define SIN_VAL_ADDRESS 0x00000084
-#define SIN_VAL_OFFSET 0x00000084
-#define SIN_VAL_SIN_MSB 0
-#define SIN_VAL_SIN_LSB 0
-#define SIN_VAL_SIN_MASK 0x00000001
-#define SIN_VAL_SIN_GET(x) (((x) & SIN_VAL_SIN_MASK) >> SIN_VAL_SIN_LSB)
-#define SIN_VAL_SIN_SET(x) (((x) << SIN_VAL_SIN_LSB) & SIN_VAL_SIN_MASK)
-
-#define SW_SCLK_ADDRESS 0x00000088
-#define SW_SCLK_OFFSET 0x00000088
-#define SW_SCLK_SW_SCLK_MSB 0
-#define SW_SCLK_SW_SCLK_LSB 0
-#define SW_SCLK_SW_SCLK_MASK 0x00000001
-#define SW_SCLK_SW_SCLK_GET(x) (((x) & SW_SCLK_SW_SCLK_MASK) >> SW_SCLK_SW_SCLK_LSB)
-#define SW_SCLK_SW_SCLK_SET(x) (((x) << SW_SCLK_SW_SCLK_LSB) & SW_SCLK_SW_SCLK_MASK)
-
-#define SW_CNTL_ADDRESS 0x0000008c
-#define SW_CNTL_OFFSET 0x0000008c
-#define SW_CNTL_SW_SCAPTURE_MSB 2
-#define SW_CNTL_SW_SCAPTURE_LSB 2
-#define SW_CNTL_SW_SCAPTURE_MASK 0x00000004
-#define SW_CNTL_SW_SCAPTURE_GET(x) (((x) & SW_CNTL_SW_SCAPTURE_MASK) >> SW_CNTL_SW_SCAPTURE_LSB)
-#define SW_CNTL_SW_SCAPTURE_SET(x) (((x) << SW_CNTL_SW_SCAPTURE_LSB) & SW_CNTL_SW_SCAPTURE_MASK)
-#define SW_CNTL_SW_SUPDATE_MSB 1
-#define SW_CNTL_SW_SUPDATE_LSB 1
-#define SW_CNTL_SW_SUPDATE_MASK 0x00000002
-#define SW_CNTL_SW_SUPDATE_GET(x) (((x) & SW_CNTL_SW_SUPDATE_MASK) >> SW_CNTL_SW_SUPDATE_LSB)
-#define SW_CNTL_SW_SUPDATE_SET(x) (((x) << SW_CNTL_SW_SUPDATE_LSB) & SW_CNTL_SW_SUPDATE_MASK)
-#define SW_CNTL_SW_SOUT_MSB 0
-#define SW_CNTL_SW_SOUT_LSB 0
-#define SW_CNTL_SW_SOUT_MASK 0x00000001
-#define SW_CNTL_SW_SOUT_GET(x) (((x) & SW_CNTL_SW_SOUT_MASK) >> SW_CNTL_SW_SOUT_LSB)
-#define SW_CNTL_SW_SOUT_SET(x) (((x) << SW_CNTL_SW_SOUT_LSB) & SW_CNTL_SW_SOUT_MASK)
-
-
-#ifndef __ASSEMBLER__
-
-typedef struct analog_intf_reg_reg_s {
- unsigned char pad0[128]; /* pad to 0x80 */
- volatile unsigned int sw_override;
- volatile unsigned int sin_val;
- volatile unsigned int sw_sclk;
- volatile unsigned int sw_cntl;
-} analog_intf_reg_reg_t;
-
-#endif /* __ASSEMBLER__ */
-
-#endif /* _ANALOG_INTF_REG_H_ */
diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw2.0/hw/analog_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw2.0/hw/analog_reg.h
deleted file mode 100644
index cf562b8..0000000
--- a/drivers/staging/ath6kl/include/common/AR6002/hw2.0/hw/analog_reg.h
+++ /dev/null
@@ -1,1932 +0,0 @@
-#ifndef _ANALOG_REG_REG_H_
-#define _ANALOG_REG_REG_H_
-
-#define SYNTH_SYNTH1_ADDRESS 0x00000000
-#define SYNTH_SYNTH1_OFFSET 0x00000000
-#define SYNTH_SYNTH1_PWD_BIAS_MSB 31
-#define SYNTH_SYNTH1_PWD_BIAS_LSB 31
-#define SYNTH_SYNTH1_PWD_BIAS_MASK 0x80000000
-#define SYNTH_SYNTH1_PWD_BIAS_GET(x) (((x) & SYNTH_SYNTH1_PWD_BIAS_MASK) >> SYNTH_SYNTH1_PWD_BIAS_LSB)
-#define SYNTH_SYNTH1_PWD_BIAS_SET(x) (((x) << SYNTH_SYNTH1_PWD_BIAS_LSB) & SYNTH_SYNTH1_PWD_BIAS_MASK)
-#define SYNTH_SYNTH1_PWD_CP_MSB 30
-#define SYNTH_SYNTH1_PWD_CP_LSB 30
-#define SYNTH_SYNTH1_PWD_CP_MASK 0x40000000
-#define SYNTH_SYNTH1_PWD_CP_GET(x) (((x) & SYNTH_SYNTH1_PWD_CP_MASK) >> SYNTH_SYNTH1_PWD_CP_LSB)
-#define SYNTH_SYNTH1_PWD_CP_SET(x) (((x) << SYNTH_SYNTH1_PWD_CP_LSB) & SYNTH_SYNTH1_PWD_CP_MASK)
-#define SYNTH_SYNTH1_PWD_VCMON_MSB 29
-#define SYNTH_SYNTH1_PWD_VCMON_LSB 29
-#define SYNTH_SYNTH1_PWD_VCMON_MASK 0x20000000
-#define SYNTH_SYNTH1_PWD_VCMON_GET(x) (((x) & SYNTH_SYNTH1_PWD_VCMON_MASK) >> SYNTH_SYNTH1_PWD_VCMON_LSB)
-#define SYNTH_SYNTH1_PWD_VCMON_SET(x) (((x) << SYNTH_SYNTH1_PWD_VCMON_LSB) & SYNTH_SYNTH1_PWD_VCMON_MASK)
-#define SYNTH_SYNTH1_PWD_VCO_MSB 28
-#define SYNTH_SYNTH1_PWD_VCO_LSB 28
-#define SYNTH_SYNTH1_PWD_VCO_MASK 0x10000000
-#define SYNTH_SYNTH1_PWD_VCO_GET(x) (((x) & SYNTH_SYNTH1_PWD_VCO_MASK) >> SYNTH_SYNTH1_PWD_VCO_LSB)
-#define SYNTH_SYNTH1_PWD_VCO_SET(x) (((x) << SYNTH_SYNTH1_PWD_VCO_LSB) & SYNTH_SYNTH1_PWD_VCO_MASK)
-#define SYNTH_SYNTH1_PWD_PRESC_MSB 27
-#define SYNTH_SYNTH1_PWD_PRESC_LSB 27
-#define SYNTH_SYNTH1_PWD_PRESC_MASK 0x08000000
-#define SYNTH_SYNTH1_PWD_PRESC_GET(x) (((x) & SYNTH_SYNTH1_PWD_PRESC_MASK) >> SYNTH_SYNTH1_PWD_PRESC_LSB)
-#define SYNTH_SYNTH1_PWD_PRESC_SET(x) (((x) << SYNTH_SYNTH1_PWD_PRESC_LSB) & SYNTH_SYNTH1_PWD_PRESC_MASK)
-#define SYNTH_SYNTH1_PWD_LODIV_MSB 26
-#define SYNTH_SYNTH1_PWD_LODIV_LSB 26
-#define SYNTH_SYNTH1_PWD_LODIV_MASK 0x04000000
-#define SYNTH_SYNTH1_PWD_LODIV_GET(x) (((x) & SYNTH_SYNTH1_PWD_LODIV_MASK) >> SYNTH_SYNTH1_PWD_LODIV_LSB)
-#define SYNTH_SYNTH1_PWD_LODIV_SET(x) (((x) << SYNTH_SYNTH1_PWD_LODIV_LSB) & SYNTH_SYNTH1_PWD_LODIV_MASK)
-#define SYNTH_SYNTH1_PWD_LOMIX_MSB 25
-#define SYNTH_SYNTH1_PWD_LOMIX_LSB 25
-#define SYNTH_SYNTH1_PWD_LOMIX_MASK 0x02000000
-#define SYNTH_SYNTH1_PWD_LOMIX_GET(x) (((x) & SYNTH_SYNTH1_PWD_LOMIX_MASK) >> SYNTH_SYNTH1_PWD_LOMIX_LSB)
-#define SYNTH_SYNTH1_PWD_LOMIX_SET(x) (((x) << SYNTH_SYNTH1_PWD_LOMIX_LSB) & SYNTH_SYNTH1_PWD_LOMIX_MASK)
-#define SYNTH_SYNTH1_FORCE_LO_ON_MSB 24
-#define SYNTH_SYNTH1_FORCE_LO_ON_LSB 24
-#define SYNTH_SYNTH1_FORCE_LO_ON_MASK 0x01000000
-#define SYNTH_SYNTH1_FORCE_LO_ON_GET(x) (((x) & SYNTH_SYNTH1_FORCE_LO_ON_MASK) >> SYNTH_SYNTH1_FORCE_LO_ON_LSB)
-#define SYNTH_SYNTH1_FORCE_LO_ON_SET(x) (((x) << SYNTH_SYNTH1_FORCE_LO_ON_LSB) & SYNTH_SYNTH1_FORCE_LO_ON_MASK)
-#define SYNTH_SYNTH1_PWD_LOBUF5G_MSB 23
-#define SYNTH_SYNTH1_PWD_LOBUF5G_LSB 23
-#define SYNTH_SYNTH1_PWD_LOBUF5G_MASK 0x00800000
-#define SYNTH_SYNTH1_PWD_LOBUF5G_GET(x) (((x) & SYNTH_SYNTH1_PWD_LOBUF5G_MASK) >> SYNTH_SYNTH1_PWD_LOBUF5G_LSB)
-#define SYNTH_SYNTH1_PWD_LOBUF5G_SET(x) (((x) << SYNTH_SYNTH1_PWD_LOBUF5G_LSB) & SYNTH_SYNTH1_PWD_LOBUF5G_MASK)
-#define SYNTH_SYNTH1_VCOREGBYPASS_MSB 22
-#define SYNTH_SYNTH1_VCOREGBYPASS_LSB 22
-#define SYNTH_SYNTH1_VCOREGBYPASS_MASK 0x00400000
-#define SYNTH_SYNTH1_VCOREGBYPASS_GET(x) (((x) & SYNTH_SYNTH1_VCOREGBYPASS_MASK) >> SYNTH_SYNTH1_VCOREGBYPASS_LSB)
-#define SYNTH_SYNTH1_VCOREGBYPASS_SET(x) (((x) << SYNTH_SYNTH1_VCOREGBYPASS_LSB) & SYNTH_SYNTH1_VCOREGBYPASS_MASK)
-#define SYNTH_SYNTH1_VCOREGLEVEL_MSB 21
-#define SYNTH_SYNTH1_VCOREGLEVEL_LSB 20
-#define SYNTH_SYNTH1_VCOREGLEVEL_MASK 0x00300000
-#define SYNTH_SYNTH1_VCOREGLEVEL_GET(x) (((x) & SYNTH_SYNTH1_VCOREGLEVEL_MASK) >> SYNTH_SYNTH1_VCOREGLEVEL_LSB)
-#define SYNTH_SYNTH1_VCOREGLEVEL_SET(x) (((x) << SYNTH_SYNTH1_VCOREGLEVEL_LSB) & SYNTH_SYNTH1_VCOREGLEVEL_MASK)
-#define SYNTH_SYNTH1_VCOREGBIAS_MSB 19
-#define SYNTH_SYNTH1_VCOREGBIAS_LSB 18
-#define SYNTH_SYNTH1_VCOREGBIAS_MASK 0x000c0000
-#define SYNTH_SYNTH1_VCOREGBIAS_GET(x) (((x) & SYNTH_SYNTH1_VCOREGBIAS_MASK) >> SYNTH_SYNTH1_VCOREGBIAS_LSB)
-#define SYNTH_SYNTH1_VCOREGBIAS_SET(x) (((x) << SYNTH_SYNTH1_VCOREGBIAS_LSB) & SYNTH_SYNTH1_VCOREGBIAS_MASK)
-#define SYNTH_SYNTH1_SLIDINGIF_MSB 17
-#define SYNTH_SYNTH1_SLIDINGIF_LSB 17
-#define SYNTH_SYNTH1_SLIDINGIF_MASK 0x00020000
-#define SYNTH_SYNTH1_SLIDINGIF_GET(x) (((x) & SYNTH_SYNTH1_SLIDINGIF_MASK) >> SYNTH_SYNTH1_SLIDINGIF_LSB)
-#define SYNTH_SYNTH1_SLIDINGIF_SET(x) (((x) << SYNTH_SYNTH1_SLIDINGIF_LSB) & SYNTH_SYNTH1_SLIDINGIF_MASK)
-#define SYNTH_SYNTH1_SPARE_PWD_MSB 16
-#define SYNTH_SYNTH1_SPARE_PWD_LSB 16
-#define SYNTH_SYNTH1_SPARE_PWD_MASK 0x00010000
-#define SYNTH_SYNTH1_SPARE_PWD_GET(x) (((x) & SYNTH_SYNTH1_SPARE_PWD_MASK) >> SYNTH_SYNTH1_SPARE_PWD_LSB)
-#define SYNTH_SYNTH1_SPARE_PWD_SET(x) (((x) << SYNTH_SYNTH1_SPARE_PWD_LSB) & SYNTH_SYNTH1_SPARE_PWD_MASK)
-#define SYNTH_SYNTH1_CON_VDDVCOREG_MSB 15
-#define SYNTH_SYNTH1_CON_VDDVCOREG_LSB 15
-#define SYNTH_SYNTH1_CON_VDDVCOREG_MASK 0x00008000
-#define SYNTH_SYNTH1_CON_VDDVCOREG_GET(x) (((x) & SYNTH_SYNTH1_CON_VDDVCOREG_MASK) >> SYNTH_SYNTH1_CON_VDDVCOREG_LSB)
-#define SYNTH_SYNTH1_CON_VDDVCOREG_SET(x) (((x) << SYNTH_SYNTH1_CON_VDDVCOREG_LSB) & SYNTH_SYNTH1_CON_VDDVCOREG_MASK)
-#define SYNTH_SYNTH1_CON_IVCOREG_MSB 14
-#define SYNTH_SYNTH1_CON_IVCOREG_LSB 14
-#define SYNTH_SYNTH1_CON_IVCOREG_MASK 0x00004000
-#define SYNTH_SYNTH1_CON_IVCOREG_GET(x) (((x) & SYNTH_SYNTH1_CON_IVCOREG_MASK) >> SYNTH_SYNTH1_CON_IVCOREG_LSB)
-#define SYNTH_SYNTH1_CON_IVCOREG_SET(x) (((x) << SYNTH_SYNTH1_CON_IVCOREG_LSB) & SYNTH_SYNTH1_CON_IVCOREG_MASK)
-#define SYNTH_SYNTH1_CON_IVCOBUF_MSB 13
-#define SYNTH_SYNTH1_CON_IVCOBUF_LSB 13
-#define SYNTH_SYNTH1_CON_IVCOBUF_MASK 0x00002000
-#define SYNTH_SYNTH1_CON_IVCOBUF_GET(x) (((x) & SYNTH_SYNTH1_CON_IVCOBUF_MASK) >> SYNTH_SYNTH1_CON_IVCOBUF_LSB)
-#define SYNTH_SYNTH1_CON_IVCOBUF_SET(x) (((x) << SYNTH_SYNTH1_CON_IVCOBUF_LSB) & SYNTH_SYNTH1_CON_IVCOBUF_MASK)
-#define SYNTH_SYNTH1_SEL_VCMONABUS_MSB 12
-#define SYNTH_SYNTH1_SEL_VCMONABUS_LSB 10
-#define SYNTH_SYNTH1_SEL_VCMONABUS_MASK 0x00001c00
-#define SYNTH_SYNTH1_SEL_VCMONABUS_GET(x) (((x) & SYNTH_SYNTH1_SEL_VCMONABUS_MASK) >> SYNTH_SYNTH1_SEL_VCMONABUS_LSB)
-#define SYNTH_SYNTH1_SEL_VCMONABUS_SET(x) (((x) << SYNTH_SYNTH1_SEL_VCMONABUS_LSB) & SYNTH_SYNTH1_SEL_VCMONABUS_MASK)
-#define SYNTH_SYNTH1_PWUP_VCOBUF_PD_MSB 9
-#define SYNTH_SYNTH1_PWUP_VCOBUF_PD_LSB 9
-#define SYNTH_SYNTH1_PWUP_VCOBUF_PD_MASK 0x00000200
-#define SYNTH_SYNTH1_PWUP_VCOBUF_PD_GET(x) (((x) & SYNTH_SYNTH1_PWUP_VCOBUF_PD_MASK) >> SYNTH_SYNTH1_PWUP_VCOBUF_PD_LSB)
-#define SYNTH_SYNTH1_PWUP_VCOBUF_PD_SET(x) (((x) << SYNTH_SYNTH1_PWUP_VCOBUF_PD_LSB) & SYNTH_SYNTH1_PWUP_VCOBUF_PD_MASK)
-#define SYNTH_SYNTH1_PWUP_LODIV_PD_MSB 8
-#define SYNTH_SYNTH1_PWUP_LODIV_PD_LSB 8
-#define SYNTH_SYNTH1_PWUP_LODIV_PD_MASK 0x00000100
-#define SYNTH_SYNTH1_PWUP_LODIV_PD_GET(x) (((x) & SYNTH_SYNTH1_PWUP_LODIV_PD_MASK) >> SYNTH_SYNTH1_PWUP_LODIV_PD_LSB)
-#define SYNTH_SYNTH1_PWUP_LODIV_PD_SET(x) (((x) << SYNTH_SYNTH1_PWUP_LODIV_PD_LSB) & SYNTH_SYNTH1_PWUP_LODIV_PD_MASK)
-#define SYNTH_SYNTH1_PWUP_LOMIX_PD_MSB 7
-#define SYNTH_SYNTH1_PWUP_LOMIX_PD_LSB 7
-#define SYNTH_SYNTH1_PWUP_LOMIX_PD_MASK 0x00000080
-#define SYNTH_SYNTH1_PWUP_LOMIX_PD_GET(x) (((x) & SYNTH_SYNTH1_PWUP_LOMIX_PD_MASK) >> SYNTH_SYNTH1_PWUP_LOMIX_PD_LSB)
-#define SYNTH_SYNTH1_PWUP_LOMIX_PD_SET(x) (((x) << SYNTH_SYNTH1_PWUP_LOMIX_PD_LSB) & SYNTH_SYNTH1_PWUP_LOMIX_PD_MASK)
-#define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_MSB 6
-#define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_LSB 6
-#define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_MASK 0x00000040
-#define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_GET(x) (((x) & SYNTH_SYNTH1_PWUP_LOBUF5G_PD_MASK) >> SYNTH_SYNTH1_PWUP_LOBUF5G_PD_LSB)
-#define SYNTH_SYNTH1_PWUP_LOBUF5G_PD_SET(x) (((x) << SYNTH_SYNTH1_PWUP_LOBUF5G_PD_LSB) & SYNTH_SYNTH1_PWUP_LOBUF5G_PD_MASK)
-#define SYNTH_SYNTH1_MONITOR_FB_MSB 5
-#define SYNTH_SYNTH1_MONITOR_FB_LSB 5
-#define SYNTH_SYNTH1_MONITOR_FB_MASK 0x00000020
-#define SYNTH_SYNTH1_MONITOR_FB_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_FB_MASK) >> SYNTH_SYNTH1_MONITOR_FB_LSB)
-#define SYNTH_SYNTH1_MONITOR_FB_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_FB_LSB) & SYNTH_SYNTH1_MONITOR_FB_MASK)
-#define SYNTH_SYNTH1_MONITOR_REF_MSB 4
-#define SYNTH_SYNTH1_MONITOR_REF_LSB 4
-#define SYNTH_SYNTH1_MONITOR_REF_MASK 0x00000010
-#define SYNTH_SYNTH1_MONITOR_REF_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_REF_MASK) >> SYNTH_SYNTH1_MONITOR_REF_LSB)
-#define SYNTH_SYNTH1_MONITOR_REF_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_REF_LSB) & SYNTH_SYNTH1_MONITOR_REF_MASK)
-#define SYNTH_SYNTH1_MONITOR_FB_DIV2_MSB 3
-#define SYNTH_SYNTH1_MONITOR_FB_DIV2_LSB 3
-#define SYNTH_SYNTH1_MONITOR_FB_DIV2_MASK 0x00000008
-#define SYNTH_SYNTH1_MONITOR_FB_DIV2_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_FB_DIV2_MASK) >> SYNTH_SYNTH1_MONITOR_FB_DIV2_LSB)
-#define SYNTH_SYNTH1_MONITOR_FB_DIV2_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_FB_DIV2_LSB) & SYNTH_SYNTH1_MONITOR_FB_DIV2_MASK)
-#define SYNTH_SYNTH1_MONITOR_VC2HIGH_MSB 2
-#define SYNTH_SYNTH1_MONITOR_VC2HIGH_LSB 2
-#define SYNTH_SYNTH1_MONITOR_VC2HIGH_MASK 0x00000004
-#define SYNTH_SYNTH1_MONITOR_VC2HIGH_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_VC2HIGH_MASK) >> SYNTH_SYNTH1_MONITOR_VC2HIGH_LSB)
-#define SYNTH_SYNTH1_MONITOR_VC2HIGH_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_VC2HIGH_LSB) & SYNTH_SYNTH1_MONITOR_VC2HIGH_MASK)
-#define SYNTH_SYNTH1_MONITOR_VC2LOW_MSB 1
-#define SYNTH_SYNTH1_MONITOR_VC2LOW_LSB 1
-#define SYNTH_SYNTH1_MONITOR_VC2LOW_MASK 0x00000002
-#define SYNTH_SYNTH1_MONITOR_VC2LOW_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_VC2LOW_MASK) >> SYNTH_SYNTH1_MONITOR_VC2LOW_LSB)
-#define SYNTH_SYNTH1_MONITOR_VC2LOW_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_VC2LOW_LSB) & SYNTH_SYNTH1_MONITOR_VC2LOW_MASK)
-#define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_MSB 0
-#define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_LSB 0
-#define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_MASK 0x00000001
-#define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_GET(x) (((x) & SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_MASK) >> SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_LSB)
-#define SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_SET(x) (((x) << SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_LSB) & SYNTH_SYNTH1_MONITOR_SYNTHLOCKVCOK_MASK)
-
-#define SYNTH_SYNTH2_ADDRESS 0x00000004
-#define SYNTH_SYNTH2_OFFSET 0x00000004
-#define SYNTH_SYNTH2_VC_CAL_REF_MSB 31
-#define SYNTH_SYNTH2_VC_CAL_REF_LSB 29
-#define SYNTH_SYNTH2_VC_CAL_REF_MASK 0xe0000000
-#define SYNTH_SYNTH2_VC_CAL_REF_GET(x) (((x) & SYNTH_SYNTH2_VC_CAL_REF_MASK) >> SYNTH_SYNTH2_VC_CAL_REF_LSB)
-#define SYNTH_SYNTH2_VC_CAL_REF_SET(x) (((x) << SYNTH_SYNTH2_VC_CAL_REF_LSB) & SYNTH_SYNTH2_VC_CAL_REF_MASK)
-#define SYNTH_SYNTH2_VC_HI_REF_MSB 28
-#define SYNTH_SYNTH2_VC_HI_REF_LSB 26
-#define SYNTH_SYNTH2_VC_HI_REF_MASK 0x1c000000
-#define SYNTH_SYNTH2_VC_HI_REF_GET(x) (((x) & SYNTH_SYNTH2_VC_HI_REF_MASK) >> SYNTH_SYNTH2_VC_HI_REF_LSB)
-#define SYNTH_SYNTH2_VC_HI_REF_SET(x) (((x) << SYNTH_SYNTH2_VC_HI_REF_LSB) & SYNTH_SYNTH2_VC_HI_REF_MASK)
-#define SYNTH_SYNTH2_VC_MID_REF_MSB 25
-#define SYNTH_SYNTH2_VC_MID_REF_LSB 23
-#define SYNTH_SYNTH2_VC_MID_REF_MASK 0x03800000
-#define SYNTH_SYNTH2_VC_MID_REF_GET(x) (((x) & SYNTH_SYNTH2_VC_MID_REF_MASK) >> SYNTH_SYNTH2_VC_MID_REF_LSB)
-#define SYNTH_SYNTH2_VC_MID_REF_SET(x) (((x) << SYNTH_SYNTH2_VC_MID_REF_LSB) & SYNTH_SYNTH2_VC_MID_REF_MASK)
-#define SYNTH_SYNTH2_VC_LOW_REF_MSB 22
-#define SYNTH_SYNTH2_VC_LOW_REF_LSB 20
-#define SYNTH_SYNTH2_VC_LOW_REF_MASK 0x00700000
-#define SYNTH_SYNTH2_VC_LOW_REF_GET(x) (((x) & SYNTH_SYNTH2_VC_LOW_REF_MASK) >> SYNTH_SYNTH2_VC_LOW_REF_LSB)
-#define SYNTH_SYNTH2_VC_LOW_REF_SET(x) (((x) << SYNTH_SYNTH2_VC_LOW_REF_LSB) & SYNTH_SYNTH2_VC_LOW_REF_MASK)
-#define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_MSB 19
-#define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_LSB 15
-#define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_MASK 0x000f8000
-#define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_GET(x) (((x) & SYNTH_SYNTH2_LOOP_3RD_ORDER_R_MASK) >> SYNTH_SYNTH2_LOOP_3RD_ORDER_R_LSB)
-#define SYNTH_SYNTH2_LOOP_3RD_ORDER_R_SET(x) (((x) << SYNTH_SYNTH2_LOOP_3RD_ORDER_R_LSB) & SYNTH_SYNTH2_LOOP_3RD_ORDER_R_MASK)
-#define SYNTH_SYNTH2_LOOP_CP_MSB 14
-#define SYNTH_SYNTH2_LOOP_CP_LSB 10
-#define SYNTH_SYNTH2_LOOP_CP_MASK 0x00007c00
-#define SYNTH_SYNTH2_LOOP_CP_GET(x) (((x) & SYNTH_SYNTH2_LOOP_CP_MASK) >> SYNTH_SYNTH2_LOOP_CP_LSB)
-#define SYNTH_SYNTH2_LOOP_CP_SET(x) (((x) << SYNTH_SYNTH2_LOOP_CP_LSB) & SYNTH_SYNTH2_LOOP_CP_MASK)
-#define SYNTH_SYNTH2_LOOP_RS_MSB 9
-#define SYNTH_SYNTH2_LOOP_RS_LSB 5
-#define SYNTH_SYNTH2_LOOP_RS_MASK 0x000003e0
-#define SYNTH_SYNTH2_LOOP_RS_GET(x) (((x) & SYNTH_SYNTH2_LOOP_RS_MASK) >> SYNTH_SYNTH2_LOOP_RS_LSB)
-#define SYNTH_SYNTH2_LOOP_RS_SET(x) (((x) << SYNTH_SYNTH2_LOOP_RS_LSB) & SYNTH_SYNTH2_LOOP_RS_MASK)
-#define SYNTH_SYNTH2_LOOP_CS_MSB 4
-#define SYNTH_SYNTH2_LOOP_CS_LSB 3
-#define SYNTH_SYNTH2_LOOP_CS_MASK 0x00000018
-#define SYNTH_SYNTH2_LOOP_CS_GET(x) (((x) & SYNTH_SYNTH2_LOOP_CS_MASK) >> SYNTH_SYNTH2_LOOP_CS_LSB)
-#define SYNTH_SYNTH2_LOOP_CS_SET(x) (((x) << SYNTH_SYNTH2_LOOP_CS_LSB) & SYNTH_SYNTH2_LOOP_CS_MASK)
-#define SYNTH_SYNTH2_SPARE_BITS_MSB 2
-#define SYNTH_SYNTH2_SPARE_BITS_LSB 0
-#define SYNTH_SYNTH2_SPARE_BITS_MASK 0x00000007
-#define SYNTH_SYNTH2_SPARE_BITS_GET(x) (((x) & SYNTH_SYNTH2_SPARE_BITS_MASK) >> SYNTH_SYNTH2_SPARE_BITS_LSB)
-#define SYNTH_SYNTH2_SPARE_BITS_SET(x) (((x) << SYNTH_SYNTH2_SPARE_BITS_LSB) & SYNTH_SYNTH2_SPARE_BITS_MASK)
-
-#define SYNTH_SYNTH3_ADDRESS 0x00000008
-#define SYNTH_SYNTH3_OFFSET 0x00000008
-#define SYNTH_SYNTH3_DIS_CLK_XTAL_MSB 31
-#define SYNTH_SYNTH3_DIS_CLK_XTAL_LSB 31
-#define SYNTH_SYNTH3_DIS_CLK_XTAL_MASK 0x80000000
-#define SYNTH_SYNTH3_DIS_CLK_XTAL_GET(x) (((x) & SYNTH_SYNTH3_DIS_CLK_XTAL_MASK) >> SYNTH_SYNTH3_DIS_CLK_XTAL_LSB)
-#define SYNTH_SYNTH3_DIS_CLK_XTAL_SET(x) (((x) << SYNTH_SYNTH3_DIS_CLK_XTAL_LSB) & SYNTH_SYNTH3_DIS_CLK_XTAL_MASK)
-#define SYNTH_SYNTH3_SEL_CLK_DIV2_MSB 30
-#define SYNTH_SYNTH3_SEL_CLK_DIV2_LSB 30
-#define SYNTH_SYNTH3_SEL_CLK_DIV2_MASK 0x40000000
-#define SYNTH_SYNTH3_SEL_CLK_DIV2_GET(x) (((x) & SYNTH_SYNTH3_SEL_CLK_DIV2_MASK) >> SYNTH_SYNTH3_SEL_CLK_DIV2_LSB)
-#define SYNTH_SYNTH3_SEL_CLK_DIV2_SET(x) (((x) << SYNTH_SYNTH3_SEL_CLK_DIV2_LSB) & SYNTH_SYNTH3_SEL_CLK_DIV2_MASK)
-#define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_MSB 29
-#define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_LSB 24
-#define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_MASK 0x3f000000
-#define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_GET(x) (((x) & SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_MASK) >> SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_LSB)
-#define SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_SET(x) (((x) << SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_LSB) & SYNTH_SYNTH3_WAIT_SHORTR_PWRUP_MASK)
-#define SYNTH_SYNTH3_WAIT_PWRUP_MSB 23
-#define SYNTH_SYNTH3_WAIT_PWRUP_LSB 18
-#define SYNTH_SYNTH3_WAIT_PWRUP_MASK 0x00fc0000
-#define SYNTH_SYNTH3_WAIT_PWRUP_GET(x) (((x) & SYNTH_SYNTH3_WAIT_PWRUP_MASK) >> SYNTH_SYNTH3_WAIT_PWRUP_LSB)
-#define SYNTH_SYNTH3_WAIT_PWRUP_SET(x) (((x) << SYNTH_SYNTH3_WAIT_PWRUP_LSB) & SYNTH_SYNTH3_WAIT_PWRUP_MASK)
-#define SYNTH_SYNTH3_WAIT_CAL_BIN_MSB 17
-#define SYNTH_SYNTH3_WAIT_CAL_BIN_LSB 12
-#define SYNTH_SYNTH3_WAIT_CAL_BIN_MASK 0x0003f000
-#define SYNTH_SYNTH3_WAIT_CAL_BIN_GET(x) (((x) & SYNTH_SYNTH3_WAIT_CAL_BIN_MASK) >> SYNTH_SYNTH3_WAIT_CAL_BIN_LSB)
-#define SYNTH_SYNTH3_WAIT_CAL_BIN_SET(x) (((x) << SYNTH_SYNTH3_WAIT_CAL_BIN_LSB) & SYNTH_SYNTH3_WAIT_CAL_BIN_MASK)
-#define SYNTH_SYNTH3_WAIT_CAL_LIN_MSB 11
-#define SYNTH_SYNTH3_WAIT_CAL_LIN_LSB 6
-#define SYNTH_SYNTH3_WAIT_CAL_LIN_MASK 0x00000fc0
-#define SYNTH_SYNTH3_WAIT_CAL_LIN_GET(x) (((x) & SYNTH_SYNTH3_WAIT_CAL_LIN_MASK) >> SYNTH_SYNTH3_WAIT_CAL_LIN_LSB)
-#define SYNTH_SYNTH3_WAIT_CAL_LIN_SET(x) (((x) << SYNTH_SYNTH3_WAIT_CAL_LIN_LSB) & SYNTH_SYNTH3_WAIT_CAL_LIN_MASK)
-#define SYNTH_SYNTH3_WAIT_VC_CHECK_MSB 5
-#define SYNTH_SYNTH3_WAIT_VC_CHECK_LSB 0
-#define SYNTH_SYNTH3_WAIT_VC_CHECK_MASK 0x0000003f
-#define SYNTH_SYNTH3_WAIT_VC_CHECK_GET(x) (((x) & SYNTH_SYNTH3_WAIT_VC_CHECK_MASK) >> SYNTH_SYNTH3_WAIT_VC_CHECK_LSB)
-#define SYNTH_SYNTH3_WAIT_VC_CHECK_SET(x) (((x) << SYNTH_SYNTH3_WAIT_VC_CHECK_LSB) & SYNTH_SYNTH3_WAIT_VC_CHECK_MASK)
-
-#define SYNTH_SYNTH4_ADDRESS 0x0000000c
-#define SYNTH_SYNTH4_OFFSET 0x0000000c
-#define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_MSB 31
-#define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_LSB 31
-#define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_MASK 0x80000000
-#define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_GET(x) (((x) & SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_MASK) >> SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_LSB)
-#define SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_SET(x) (((x) << SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_LSB) & SYNTH_SYNTH4_DIS_LIN_CAPSEARCH_MASK)
-#define SYNTH_SYNTH4_DIS_LOSTVC_MSB 30
-#define SYNTH_SYNTH4_DIS_LOSTVC_LSB 30
-#define SYNTH_SYNTH4_DIS_LOSTVC_MASK 0x40000000
-#define SYNTH_SYNTH4_DIS_LOSTVC_GET(x) (((x) & SYNTH_SYNTH4_DIS_LOSTVC_MASK) >> SYNTH_SYNTH4_DIS_LOSTVC_LSB)
-#define SYNTH_SYNTH4_DIS_LOSTVC_SET(x) (((x) << SYNTH_SYNTH4_DIS_LOSTVC_LSB) & SYNTH_SYNTH4_DIS_LOSTVC_MASK)
-#define SYNTH_SYNTH4_ALWAYS_SHORTR_MSB 29
-#define SYNTH_SYNTH4_ALWAYS_SHORTR_LSB 29
-#define SYNTH_SYNTH4_ALWAYS_SHORTR_MASK 0x20000000
-#define SYNTH_SYNTH4_ALWAYS_SHORTR_GET(x) (((x) & SYNTH_SYNTH4_ALWAYS_SHORTR_MASK) >> SYNTH_SYNTH4_ALWAYS_SHORTR_LSB)
-#define SYNTH_SYNTH4_ALWAYS_SHORTR_SET(x) (((x) << SYNTH_SYNTH4_ALWAYS_SHORTR_LSB) & SYNTH_SYNTH4_ALWAYS_SHORTR_MASK)
-#define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_MSB 28
-#define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_LSB 28
-#define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_MASK 0x10000000
-#define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_GET(x) (((x) & SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_MASK) >> SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_LSB)
-#define SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_SET(x) (((x) << SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_LSB) & SYNTH_SYNTH4_SHORTR_UNTIL_LOCKED_MASK)
-#define SYNTH_SYNTH4_FORCE_PINVC_MSB 27
-#define SYNTH_SYNTH4_FORCE_PINVC_LSB 27
-#define SYNTH_SYNTH4_FORCE_PINVC_MASK 0x08000000
-#define SYNTH_SYNTH4_FORCE_PINVC_GET(x) (((x) & SYNTH_SYNTH4_FORCE_PINVC_MASK) >> SYNTH_SYNTH4_FORCE_PINVC_LSB)
-#define SYNTH_SYNTH4_FORCE_PINVC_SET(x) (((x) << SYNTH_SYNTH4_FORCE_PINVC_LSB) & SYNTH_SYNTH4_FORCE_PINVC_MASK)
-#define SYNTH_SYNTH4_FORCE_VCOCAP_MSB 26
-#define SYNTH_SYNTH4_FORCE_VCOCAP_LSB 26
-#define SYNTH_SYNTH4_FORCE_VCOCAP_MASK 0x04000000
-#define SYNTH_SYNTH4_FORCE_VCOCAP_GET(x) (((x) & SYNTH_SYNTH4_FORCE_VCOCAP_MASK) >> SYNTH_SYNTH4_FORCE_VCOCAP_LSB)
-#define SYNTH_SYNTH4_FORCE_VCOCAP_SET(x) (((x) << SYNTH_SYNTH4_FORCE_VCOCAP_LSB) & SYNTH_SYNTH4_FORCE_VCOCAP_MASK)
-#define SYNTH_SYNTH4_VCOCAP_OVR_MSB 25
-#define SYNTH_SYNTH4_VCOCAP_OVR_LSB 18
-#define SYNTH_SYNTH4_VCOCAP_OVR_MASK 0x03fc0000
-#define SYNTH_SYNTH4_VCOCAP_OVR_GET(x) (((x) & SYNTH_SYNTH4_VCOCAP_OVR_MASK) >> SYNTH_SYNTH4_VCOCAP_OVR_LSB)
-#define SYNTH_SYNTH4_VCOCAP_OVR_SET(x) (((x) << SYNTH_SYNTH4_VCOCAP_OVR_LSB) & SYNTH_SYNTH4_VCOCAP_OVR_MASK)
-#define SYNTH_SYNTH4_VCOCAPPULLUP_MSB 17
-#define SYNTH_SYNTH4_VCOCAPPULLUP_LSB 17
-#define SYNTH_SYNTH4_VCOCAPPULLUP_MASK 0x00020000
-#define SYNTH_SYNTH4_VCOCAPPULLUP_GET(x) (((x) & SYNTH_SYNTH4_VCOCAPPULLUP_MASK) >> SYNTH_SYNTH4_VCOCAPPULLUP_LSB)
-#define SYNTH_SYNTH4_VCOCAPPULLUP_SET(x) (((x) << SYNTH_SYNTH4_VCOCAPPULLUP_LSB) & SYNTH_SYNTH4_VCOCAPPULLUP_MASK)
-#define SYNTH_SYNTH4_REFDIVSEL_MSB 16
-#define SYNTH_SYNTH4_REFDIVSEL_LSB 15
-#define SYNTH_SYNTH4_REFDIVSEL_MASK 0x00018000
-#define SYNTH_SYNTH4_REFDIVSEL_GET(x) (((x) & SYNTH_SYNTH4_REFDIVSEL_MASK) >> SYNTH_SYNTH4_REFDIVSEL_LSB)
-#define SYNTH_SYNTH4_REFDIVSEL_SET(x) (((x) << SYNTH_SYNTH4_REFDIVSEL_LSB) & SYNTH_SYNTH4_REFDIVSEL_MASK)
-#define SYNTH_SYNTH4_PFDDELAY_MSB 14
-#define SYNTH_SYNTH4_PFDDELAY_LSB 14
-#define SYNTH_SYNTH4_PFDDELAY_MASK 0x00004000
-#define SYNTH_SYNTH4_PFDDELAY_GET(x) (((x) & SYNTH_SYNTH4_PFDDELAY_MASK) >> SYNTH_SYNTH4_PFDDELAY_LSB)
-#define SYNTH_SYNTH4_PFDDELAY_SET(x) (((x) << SYNTH_SYNTH4_PFDDELAY_LSB) & SYNTH_SYNTH4_PFDDELAY_MASK)
-#define SYNTH_SYNTH4_PFD_DISABLE_MSB 13
-#define SYNTH_SYNTH4_PFD_DISABLE_LSB 13
-#define SYNTH_SYNTH4_PFD_DISABLE_MASK 0x00002000
-#define SYNTH_SYNTH4_PFD_DISABLE_GET(x) (((x) & SYNTH_SYNTH4_PFD_DISABLE_MASK) >> SYNTH_SYNTH4_PFD_DISABLE_LSB)
-#define SYNTH_SYNTH4_PFD_DISABLE_SET(x) (((x) << SYNTH_SYNTH4_PFD_DISABLE_LSB) & SYNTH_SYNTH4_PFD_DISABLE_MASK)
-#define SYNTH_SYNTH4_PRESCSEL_MSB 12
-#define SYNTH_SYNTH4_PRESCSEL_LSB 11
-#define SYNTH_SYNTH4_PRESCSEL_MASK 0x00001800
-#define SYNTH_SYNTH4_PRESCSEL_GET(x) (((x) & SYNTH_SYNTH4_PRESCSEL_MASK) >> SYNTH_SYNTH4_PRESCSEL_LSB)
-#define SYNTH_SYNTH4_PRESCSEL_SET(x) (((x) << SYNTH_SYNTH4_PRESCSEL_LSB) & SYNTH_SYNTH4_PRESCSEL_MASK)
-#define SYNTH_SYNTH4_RESET_PRESC_MSB 10
-#define SYNTH_SYNTH4_RESET_PRESC_LSB 10
-#define SYNTH_SYNTH4_RESET_PRESC_MASK 0x00000400
-#define SYNTH_SYNTH4_RESET_PRESC_GET(x) (((x) & SYNTH_SYNTH4_RESET_PRESC_MASK) >> SYNTH_SYNTH4_RESET_PRESC_LSB)
-#define SYNTH_SYNTH4_RESET_PRESC_SET(x) (((x) << SYNTH_SYNTH4_RESET_PRESC_LSB) & SYNTH_SYNTH4_RESET_PRESC_MASK)
-#define SYNTH_SYNTH4_SDM_DISABLE_MSB 9
-#define SYNTH_SYNTH4_SDM_DISABLE_LSB 9
-#define SYNTH_SYNTH4_SDM_DISABLE_MASK 0x00000200
-#define SYNTH_SYNTH4_SDM_DISABLE_GET(x) (((x) & SYNTH_SYNTH4_SDM_DISABLE_MASK) >> SYNTH_SYNTH4_SDM_DISABLE_LSB)
-#define SYNTH_SYNTH4_SDM_DISABLE_SET(x) (((x) << SYNTH_SYNTH4_SDM_DISABLE_LSB) & SYNTH_SYNTH4_SDM_DISABLE_MASK)
-#define SYNTH_SYNTH4_SDM_MODE_MSB 8
-#define SYNTH_SYNTH4_SDM_MODE_LSB 8
-#define SYNTH_SYNTH4_SDM_MODE_MASK 0x00000100
-#define SYNTH_SYNTH4_SDM_MODE_GET(x) (((x) & SYNTH_SYNTH4_SDM_MODE_MASK) >> SYNTH_SYNTH4_SDM_MODE_LSB)
-#define SYNTH_SYNTH4_SDM_MODE_SET(x) (((x) << SYNTH_SYNTH4_SDM_MODE_LSB) & SYNTH_SYNTH4_SDM_MODE_MASK)
-#define SYNTH_SYNTH4_SDM_DITHER_MSB 7
-#define SYNTH_SYNTH4_SDM_DITHER_LSB 6
-#define SYNTH_SYNTH4_SDM_DITHER_MASK 0x000000c0
-#define SYNTH_SYNTH4_SDM_DITHER_GET(x) (((x) & SYNTH_SYNTH4_SDM_DITHER_MASK) >> SYNTH_SYNTH4_SDM_DITHER_LSB)
-#define SYNTH_SYNTH4_SDM_DITHER_SET(x) (((x) << SYNTH_SYNTH4_SDM_DITHER_LSB) & SYNTH_SYNTH4_SDM_DITHER_MASK)
-#define SYNTH_SYNTH4_PSCOUNT_FBSEL_MSB 5
-#define SYNTH_SYNTH4_PSCOUNT_FBSEL_LSB 5
-#define SYNTH_SYNTH4_PSCOUNT_FBSEL_MASK 0x00000020
-#define SYNTH_SYNTH4_PSCOUNT_FBSEL_GET(x) (((x) & SYNTH_SYNTH4_PSCOUNT_FBSEL_MASK) >> SYNTH_SYNTH4_PSCOUNT_FBSEL_LSB)
-#define SYNTH_SYNTH4_PSCOUNT_FBSEL_SET(x) (((x) << SYNTH_SYNTH4_PSCOUNT_FBSEL_LSB) & SYNTH_SYNTH4_PSCOUNT_FBSEL_MASK)
-#define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_MSB 4
-#define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_LSB 4
-#define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_MASK 0x00000010
-#define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_GET(x) (((x) & SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_MASK) >> SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_LSB)
-#define SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_SET(x) (((x) << SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_LSB) & SYNTH_SYNTH4_SEL_CLKXTAL_EDGE_MASK)
-#define SYNTH_SYNTH4_SPARE_MISC_MSB 3
-#define SYNTH_SYNTH4_SPARE_MISC_LSB 2
-#define SYNTH_SYNTH4_SPARE_MISC_MASK 0x0000000c
-#define SYNTH_SYNTH4_SPARE_MISC_GET(x) (((x) & SYNTH_SYNTH4_SPARE_MISC_MASK) >> SYNTH_SYNTH4_SPARE_MISC_LSB)
-#define SYNTH_SYNTH4_SPARE_MISC_SET(x) (((x) << SYNTH_SYNTH4_SPARE_MISC_LSB) & SYNTH_SYNTH4_SPARE_MISC_MASK)
-#define SYNTH_SYNTH4_LONGSHIFTSEL_MSB 1
-#define SYNTH_SYNTH4_LONGSHIFTSEL_LSB 1
-#define SYNTH_SYNTH4_LONGSHIFTSEL_MASK 0x00000002
-#define SYNTH_SYNTH4_LONGSHIFTSEL_GET(x) (((x) & SYNTH_SYNTH4_LONGSHIFTSEL_MASK) >> SYNTH_SYNTH4_LONGSHIFTSEL_LSB)
-#define SYNTH_SYNTH4_LONGSHIFTSEL_SET(x) (((x) << SYNTH_SYNTH4_LONGSHIFTSEL_LSB) & SYNTH_SYNTH4_LONGSHIFTSEL_MASK)
-#define SYNTH_SYNTH4_FORCE_SHIFTREG_MSB 0
-#define SYNTH_SYNTH4_FORCE_SHIFTREG_LSB 0
-#define SYNTH_SYNTH4_FORCE_SHIFTREG_MASK 0x00000001
-#define SYNTH_SYNTH4_FORCE_SHIFTREG_GET(x) (((x) & SYNTH_SYNTH4_FORCE_SHIFTREG_MASK) >> SYNTH_SYNTH4_FORCE_SHIFTREG_LSB)
-#define SYNTH_SYNTH4_FORCE_SHIFTREG_SET(x) (((x) << SYNTH_SYNTH4_FORCE_SHIFTREG_LSB) & SYNTH_SYNTH4_FORCE_SHIFTREG_MASK)
-
-#define SYNTH_SYNTH5_ADDRESS 0x00000010
-#define SYNTH_SYNTH5_OFFSET 0x00000010
-#define SYNTH_SYNTH5_LOOP_IP0_MSB 31
-#define SYNTH_SYNTH5_LOOP_IP0_LSB 28
-#define SYNTH_SYNTH5_LOOP_IP0_MASK 0xf0000000
-#define SYNTH_SYNTH5_LOOP_IP0_GET(x) (((x) & SYNTH_SYNTH5_LOOP_IP0_MASK) >> SYNTH_SYNTH5_LOOP_IP0_LSB)
-#define SYNTH_SYNTH5_LOOP_IP0_SET(x) (((x) << SYNTH_SYNTH5_LOOP_IP0_LSB) & SYNTH_SYNTH5_LOOP_IP0_MASK)
-#define SYNTH_SYNTH5_SLOPE_IP_MSB 27
-#define SYNTH_SYNTH5_SLOPE_IP_LSB 25
-#define SYNTH_SYNTH5_SLOPE_IP_MASK 0x0e000000
-#define SYNTH_SYNTH5_SLOPE_IP_GET(x) (((x) & SYNTH_SYNTH5_SLOPE_IP_MASK) >> SYNTH_SYNTH5_SLOPE_IP_LSB)
-#define SYNTH_SYNTH5_SLOPE_IP_SET(x) (((x) << SYNTH_SYNTH5_SLOPE_IP_LSB) & SYNTH_SYNTH5_SLOPE_IP_MASK)
-#define SYNTH_SYNTH5_CPBIAS_MSB 24
-#define SYNTH_SYNTH5_CPBIAS_LSB 23
-#define SYNTH_SYNTH5_CPBIAS_MASK 0x01800000
-#define SYNTH_SYNTH5_CPBIAS_GET(x) (((x) & SYNTH_SYNTH5_CPBIAS_MASK) >> SYNTH_SYNTH5_CPBIAS_LSB)
-#define SYNTH_SYNTH5_CPBIAS_SET(x) (((x) << SYNTH_SYNTH5_CPBIAS_LSB) & SYNTH_SYNTH5_CPBIAS_MASK)
-#define SYNTH_SYNTH5_CPSTEERING_EN_MSB 22
-#define SYNTH_SYNTH5_CPSTEERING_EN_LSB 22
-#define SYNTH_SYNTH5_CPSTEERING_EN_MASK 0x00400000
-#define SYNTH_SYNTH5_CPSTEERING_EN_GET(x) (((x) & SYNTH_SYNTH5_CPSTEERING_EN_MASK) >> SYNTH_SYNTH5_CPSTEERING_EN_LSB)
-#define SYNTH_SYNTH5_CPSTEERING_EN_SET(x) (((x) << SYNTH_SYNTH5_CPSTEERING_EN_LSB) & SYNTH_SYNTH5_CPSTEERING_EN_MASK)
-#define SYNTH_SYNTH5_CPLOWLK_MSB 21
-#define SYNTH_SYNTH5_CPLOWLK_LSB 21
-#define SYNTH_SYNTH5_CPLOWLK_MASK 0x00200000
-#define SYNTH_SYNTH5_CPLOWLK_GET(x) (((x) & SYNTH_SYNTH5_CPLOWLK_MASK) >> SYNTH_SYNTH5_CPLOWLK_LSB)
-#define SYNTH_SYNTH5_CPLOWLK_SET(x) (((x) << SYNTH_SYNTH5_CPLOWLK_LSB) & SYNTH_SYNTH5_CPLOWLK_MASK)
-#define SYNTH_SYNTH5_LOOPLEAKCUR_MSB 20
-#define SYNTH_SYNTH5_LOOPLEAKCUR_LSB 17
-#define SYNTH_SYNTH5_LOOPLEAKCUR_MASK 0x001e0000
-#define SYNTH_SYNTH5_LOOPLEAKCUR_GET(x) (((x) & SYNTH_SYNTH5_LOOPLEAKCUR_MASK) >> SYNTH_SYNTH5_LOOPLEAKCUR_LSB)
-#define SYNTH_SYNTH5_LOOPLEAKCUR_SET(x) (((x) << SYNTH_SYNTH5_LOOPLEAKCUR_LSB) & SYNTH_SYNTH5_LOOPLEAKCUR_MASK)
-#define SYNTH_SYNTH5_CAPRANGE1_MSB 16
-#define SYNTH_SYNTH5_CAPRANGE1_LSB 13
-#define SYNTH_SYNTH5_CAPRANGE1_MASK 0x0001e000
-#define SYNTH_SYNTH5_CAPRANGE1_GET(x) (((x) & SYNTH_SYNTH5_CAPRANGE1_MASK) >> SYNTH_SYNTH5_CAPRANGE1_LSB)
-#define SYNTH_SYNTH5_CAPRANGE1_SET(x) (((x) << SYNTH_SYNTH5_CAPRANGE1_LSB) & SYNTH_SYNTH5_CAPRANGE1_MASK)
-#define SYNTH_SYNTH5_CAPRANGE2_MSB 12
-#define SYNTH_SYNTH5_CAPRANGE2_LSB 9
-#define SYNTH_SYNTH5_CAPRANGE2_MASK 0x00001e00
-#define SYNTH_SYNTH5_CAPRANGE2_GET(x) (((x) & SYNTH_SYNTH5_CAPRANGE2_MASK) >> SYNTH_SYNTH5_CAPRANGE2_LSB)
-#define SYNTH_SYNTH5_CAPRANGE2_SET(x) (((x) << SYNTH_SYNTH5_CAPRANGE2_LSB) & SYNTH_SYNTH5_CAPRANGE2_MASK)
-#define SYNTH_SYNTH5_CAPRANGE3_MSB 8
-#define SYNTH_SYNTH5_CAPRANGE3_LSB 5
-#define SYNTH_SYNTH5_CAPRANGE3_MASK 0x000001e0
-#define SYNTH_SYNTH5_CAPRANGE3_GET(x) (((x) & SYNTH_SYNTH5_CAPRANGE3_MASK) >> SYNTH_SYNTH5_CAPRANGE3_LSB)
-#define SYNTH_SYNTH5_CAPRANGE3_SET(x) (((x) << SYNTH_SYNTH5_CAPRANGE3_LSB) & SYNTH_SYNTH5_CAPRANGE3_MASK)
-#define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_MSB 4
-#define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_LSB 4
-#define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_MASK 0x00000010
-#define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_GET(x) (((x) & SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_MASK) >> SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_LSB)
-#define SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_SET(x) (((x) << SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_LSB) & SYNTH_SYNTH5_FORCE_LOBUF5GTUNE_MASK)
-#define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_MSB 3
-#define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_LSB 2
-#define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_MASK 0x0000000c
-#define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_GET(x) (((x) & SYNTH_SYNTH5_LOBUF5GTUNE_OVR_MASK) >> SYNTH_SYNTH5_LOBUF5GTUNE_OVR_LSB)
-#define SYNTH_SYNTH5_LOBUF5GTUNE_OVR_SET(x) (((x) << SYNTH_SYNTH5_LOBUF5GTUNE_OVR_LSB) & SYNTH_SYNTH5_LOBUF5GTUNE_OVR_MASK)
-#define SYNTH_SYNTH5_SPARE_MSB 1
-#define SYNTH_SYNTH5_SPARE_LSB 0
-#define SYNTH_SYNTH5_SPARE_MASK 0x00000003
-#define SYNTH_SYNTH5_SPARE_GET(x) (((x) & SYNTH_SYNTH5_SPARE_MASK) >> SYNTH_SYNTH5_SPARE_LSB)
-#define SYNTH_SYNTH5_SPARE_SET(x) (((x) << SYNTH_SYNTH5_SPARE_LSB) & SYNTH_SYNTH5_SPARE_MASK)
-
-#define SYNTH_SYNTH6_ADDRESS 0x00000014
-#define SYNTH_SYNTH6_OFFSET 0x00000014
-#define SYNTH_SYNTH6_IRCP_MSB 31
-#define SYNTH_SYNTH6_IRCP_LSB 29
-#define SYNTH_SYNTH6_IRCP_MASK 0xe0000000
-#define SYNTH_SYNTH6_IRCP_GET(x) (((x) & SYNTH_SYNTH6_IRCP_MASK) >> SYNTH_SYNTH6_IRCP_LSB)
-#define SYNTH_SYNTH6_IRCP_SET(x) (((x) << SYNTH_SYNTH6_IRCP_LSB) & SYNTH_SYNTH6_IRCP_MASK)
-#define SYNTH_SYNTH6_IRVCMON_MSB 28
-#define SYNTH_SYNTH6_IRVCMON_LSB 26
-#define SYNTH_SYNTH6_IRVCMON_MASK 0x1c000000
-#define SYNTH_SYNTH6_IRVCMON_GET(x) (((x) & SYNTH_SYNTH6_IRVCMON_MASK) >> SYNTH_SYNTH6_IRVCMON_LSB)
-#define SYNTH_SYNTH6_IRVCMON_SET(x) (((x) << SYNTH_SYNTH6_IRVCMON_LSB) & SYNTH_SYNTH6_IRVCMON_MASK)
-#define SYNTH_SYNTH6_IRSPARE_MSB 25
-#define SYNTH_SYNTH6_IRSPARE_LSB 23
-#define SYNTH_SYNTH6_IRSPARE_MASK 0x03800000
-#define SYNTH_SYNTH6_IRSPARE_GET(x) (((x) & SYNTH_SYNTH6_IRSPARE_MASK) >> SYNTH_SYNTH6_IRSPARE_LSB)
-#define SYNTH_SYNTH6_IRSPARE_SET(x) (((x) << SYNTH_SYNTH6_IRSPARE_LSB) & SYNTH_SYNTH6_IRSPARE_MASK)
-#define SYNTH_SYNTH6_ICPRESC_MSB 22
-#define SYNTH_SYNTH6_ICPRESC_LSB 20
-#define SYNTH_SYNTH6_ICPRESC_MASK 0x00700000
-#define SYNTH_SYNTH6_ICPRESC_GET(x) (((x) & SYNTH_SYNTH6_ICPRESC_MASK) >> SYNTH_SYNTH6_ICPRESC_LSB)
-#define SYNTH_SYNTH6_ICPRESC_SET(x) (((x) << SYNTH_SYNTH6_ICPRESC_LSB) & SYNTH_SYNTH6_ICPRESC_MASK)
-#define SYNTH_SYNTH6_ICLODIV_MSB 19
-#define SYNTH_SYNTH6_ICLODIV_LSB 17
-#define SYNTH_SYNTH6_ICLODIV_MASK 0x000e0000
-#define SYNTH_SYNTH6_ICLODIV_GET(x) (((x) & SYNTH_SYNTH6_ICLODIV_MASK) >> SYNTH_SYNTH6_ICLODIV_LSB)
-#define SYNTH_SYNTH6_ICLODIV_SET(x) (((x) << SYNTH_SYNTH6_ICLODIV_LSB) & SYNTH_SYNTH6_ICLODIV_MASK)
-#define SYNTH_SYNTH6_ICLOMIX_MSB 16
-#define SYNTH_SYNTH6_ICLOMIX_LSB 14
-#define SYNTH_SYNTH6_ICLOMIX_MASK 0x0001c000
-#define SYNTH_SYNTH6_ICLOMIX_GET(x) (((x) & SYNTH_SYNTH6_ICLOMIX_MASK) >> SYNTH_SYNTH6_ICLOMIX_LSB)
-#define SYNTH_SYNTH6_ICLOMIX_SET(x) (((x) << SYNTH_SYNTH6_ICLOMIX_LSB) & SYNTH_SYNTH6_ICLOMIX_MASK)
-#define SYNTH_SYNTH6_ICSPAREA_MSB 13
-#define SYNTH_SYNTH6_ICSPAREA_LSB 11
-#define SYNTH_SYNTH6_ICSPAREA_MASK 0x00003800
-#define SYNTH_SYNTH6_ICSPAREA_GET(x) (((x) & SYNTH_SYNTH6_ICSPAREA_MASK) >> SYNTH_SYNTH6_ICSPAREA_LSB)
-#define SYNTH_SYNTH6_ICSPAREA_SET(x) (((x) << SYNTH_SYNTH6_ICSPAREA_LSB) & SYNTH_SYNTH6_ICSPAREA_MASK)
-#define SYNTH_SYNTH6_ICSPAREB_MSB 10
-#define SYNTH_SYNTH6_ICSPAREB_LSB 8
-#define SYNTH_SYNTH6_ICSPAREB_MASK 0x00000700
-#define SYNTH_SYNTH6_ICSPAREB_GET(x) (((x) & SYNTH_SYNTH6_ICSPAREB_MASK) >> SYNTH_SYNTH6_ICSPAREB_LSB)
-#define SYNTH_SYNTH6_ICSPAREB_SET(x) (((x) << SYNTH_SYNTH6_ICSPAREB_LSB) & SYNTH_SYNTH6_ICSPAREB_MASK)
-#define SYNTH_SYNTH6_ICVCO_MSB 7
-#define SYNTH_SYNTH6_ICVCO_LSB 5
-#define SYNTH_SYNTH6_ICVCO_MASK 0x000000e0
-#define SYNTH_SYNTH6_ICVCO_GET(x) (((x) & SYNTH_SYNTH6_ICVCO_MASK) >> SYNTH_SYNTH6_ICVCO_LSB)
-#define SYNTH_SYNTH6_ICVCO_SET(x) (((x) << SYNTH_SYNTH6_ICVCO_LSB) & SYNTH_SYNTH6_ICVCO_MASK)
-#define SYNTH_SYNTH6_VCOBUFBIAS_MSB 4
-#define SYNTH_SYNTH6_VCOBUFBIAS_LSB 3
-#define SYNTH_SYNTH6_VCOBUFBIAS_MASK 0x00000018
-#define SYNTH_SYNTH6_VCOBUFBIAS_GET(x) (((x) & SYNTH_SYNTH6_VCOBUFBIAS_MASK) >> SYNTH_SYNTH6_VCOBUFBIAS_LSB)
-#define SYNTH_SYNTH6_VCOBUFBIAS_SET(x) (((x) << SYNTH_SYNTH6_VCOBUFBIAS_LSB) & SYNTH_SYNTH6_VCOBUFBIAS_MASK)
-#define SYNTH_SYNTH6_SPARE_BIAS_MSB 2
-#define SYNTH_SYNTH6_SPARE_BIAS_LSB 0
-#define SYNTH_SYNTH6_SPARE_BIAS_MASK 0x00000007
-#define SYNTH_SYNTH6_SPARE_BIAS_GET(x) (((x) & SYNTH_SYNTH6_SPARE_BIAS_MASK) >> SYNTH_SYNTH6_SPARE_BIAS_LSB)
-#define SYNTH_SYNTH6_SPARE_BIAS_SET(x) (((x) << SYNTH_SYNTH6_SPARE_BIAS_LSB) & SYNTH_SYNTH6_SPARE_BIAS_MASK)
-
-#define SYNTH_SYNTH7_ADDRESS 0x00000018
-#define SYNTH_SYNTH7_OFFSET 0x00000018
-#define SYNTH_SYNTH7_SYNTH_ON_MSB 31
-#define SYNTH_SYNTH7_SYNTH_ON_LSB 31
-#define SYNTH_SYNTH7_SYNTH_ON_MASK 0x80000000
-#define SYNTH_SYNTH7_SYNTH_ON_GET(x) (((x) & SYNTH_SYNTH7_SYNTH_ON_MASK) >> SYNTH_SYNTH7_SYNTH_ON_LSB)
-#define SYNTH_SYNTH7_SYNTH_ON_SET(x) (((x) << SYNTH_SYNTH7_SYNTH_ON_LSB) & SYNTH_SYNTH7_SYNTH_ON_MASK)
-#define SYNTH_SYNTH7_SYNTH_SM_STATE_MSB 30
-#define SYNTH_SYNTH7_SYNTH_SM_STATE_LSB 27
-#define SYNTH_SYNTH7_SYNTH_SM_STATE_MASK 0x78000000
-#define SYNTH_SYNTH7_SYNTH_SM_STATE_GET(x) (((x) & SYNTH_SYNTH7_SYNTH_SM_STATE_MASK) >> SYNTH_SYNTH7_SYNTH_SM_STATE_LSB)
-#define SYNTH_SYNTH7_SYNTH_SM_STATE_SET(x) (((x) << SYNTH_SYNTH7_SYNTH_SM_STATE_LSB) & SYNTH_SYNTH7_SYNTH_SM_STATE_MASK)
-#define SYNTH_SYNTH7_CAP_SEARCH_MSB 26
-#define SYNTH_SYNTH7_CAP_SEARCH_LSB 26
-#define SYNTH_SYNTH7_CAP_SEARCH_MASK 0x04000000
-#define SYNTH_SYNTH7_CAP_SEARCH_GET(x) (((x) & SYNTH_SYNTH7_CAP_SEARCH_MASK) >> SYNTH_SYNTH7_CAP_SEARCH_LSB)
-#define SYNTH_SYNTH7_CAP_SEARCH_SET(x) (((x) << SYNTH_SYNTH7_CAP_SEARCH_LSB) & SYNTH_SYNTH7_CAP_SEARCH_MASK)
-#define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_MSB 25
-#define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_LSB 25
-#define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_MASK 0x02000000
-#define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_GET(x) (((x) & SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_MASK) >> SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_LSB)
-#define SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_SET(x) (((x) << SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_LSB) & SYNTH_SYNTH7_SYNTH_LOCK_VC_OK_MASK)
-#define SYNTH_SYNTH7_PIN_VC_MSB 24
-#define SYNTH_SYNTH7_PIN_VC_LSB 24
-#define SYNTH_SYNTH7_PIN_VC_MASK 0x01000000
-#define SYNTH_SYNTH7_PIN_VC_GET(x) (((x) & SYNTH_SYNTH7_PIN_VC_MASK) >> SYNTH_SYNTH7_PIN_VC_LSB)
-#define SYNTH_SYNTH7_PIN_VC_SET(x) (((x) << SYNTH_SYNTH7_PIN_VC_LSB) & SYNTH_SYNTH7_PIN_VC_MASK)
-#define SYNTH_SYNTH7_VCO_CAP_ST_MSB 23
-#define SYNTH_SYNTH7_VCO_CAP_ST_LSB 16
-#define SYNTH_SYNTH7_VCO_CAP_ST_MASK 0x00ff0000
-#define SYNTH_SYNTH7_VCO_CAP_ST_GET(x) (((x) & SYNTH_SYNTH7_VCO_CAP_ST_MASK) >> SYNTH_SYNTH7_VCO_CAP_ST_LSB)
-#define SYNTH_SYNTH7_VCO_CAP_ST_SET(x) (((x) << SYNTH_SYNTH7_VCO_CAP_ST_LSB) & SYNTH_SYNTH7_VCO_CAP_ST_MASK)
-#define SYNTH_SYNTH7_SHORT_R_MSB 15
-#define SYNTH_SYNTH7_SHORT_R_LSB 15
-#define SYNTH_SYNTH7_SHORT_R_MASK 0x00008000
-#define SYNTH_SYNTH7_SHORT_R_GET(x) (((x) & SYNTH_SYNTH7_SHORT_R_MASK) >> SYNTH_SYNTH7_SHORT_R_LSB)
-#define SYNTH_SYNTH7_SHORT_R_SET(x) (((x) << SYNTH_SYNTH7_SHORT_R_LSB) & SYNTH_SYNTH7_SHORT_R_MASK)
-#define SYNTH_SYNTH7_RESET_RFD_MSB 14
-#define SYNTH_SYNTH7_RESET_RFD_LSB 14
-#define SYNTH_SYNTH7_RESET_RFD_MASK 0x00004000
-#define SYNTH_SYNTH7_RESET_RFD_GET(x) (((x) & SYNTH_SYNTH7_RESET_RFD_MASK) >> SYNTH_SYNTH7_RESET_RFD_LSB)
-#define SYNTH_SYNTH7_RESET_RFD_SET(x) (((x) << SYNTH_SYNTH7_RESET_RFD_LSB) & SYNTH_SYNTH7_RESET_RFD_MASK)
-#define SYNTH_SYNTH7_RESET_PFD_MSB 13
-#define SYNTH_SYNTH7_RESET_PFD_LSB 13
-#define SYNTH_SYNTH7_RESET_PFD_MASK 0x00002000
-#define SYNTH_SYNTH7_RESET_PFD_GET(x) (((x) & SYNTH_SYNTH7_RESET_PFD_MASK) >> SYNTH_SYNTH7_RESET_PFD_LSB)
-#define SYNTH_SYNTH7_RESET_PFD_SET(x) (((x) << SYNTH_SYNTH7_RESET_PFD_LSB) & SYNTH_SYNTH7_RESET_PFD_MASK)
-#define SYNTH_SYNTH7_RESET_PSCOUNTERS_MSB 12
-#define SYNTH_SYNTH7_RESET_PSCOUNTERS_LSB 12
-#define SYNTH_SYNTH7_RESET_PSCOUNTERS_MASK 0x00001000
-#define SYNTH_SYNTH7_RESET_PSCOUNTERS_GET(x) (((x) & SYNTH_SYNTH7_RESET_PSCOUNTERS_MASK) >> SYNTH_SYNTH7_RESET_PSCOUNTERS_LSB)
-#define SYNTH_SYNTH7_RESET_PSCOUNTERS_SET(x) (((x) << SYNTH_SYNTH7_RESET_PSCOUNTERS_LSB) & SYNTH_SYNTH7_RESET_PSCOUNTERS_MASK)
-#define SYNTH_SYNTH7_RESET_SDM_B_MSB 11
-#define SYNTH_SYNTH7_RESET_SDM_B_LSB 11
-#define SYNTH_SYNTH7_RESET_SDM_B_MASK 0x00000800
-#define SYNTH_SYNTH7_RESET_SDM_B_GET(x) (((x) & SYNTH_SYNTH7_RESET_SDM_B_MASK) >> SYNTH_SYNTH7_RESET_SDM_B_LSB)
-#define SYNTH_SYNTH7_RESET_SDM_B_SET(x) (((x) << SYNTH_SYNTH7_RESET_SDM_B_LSB) & SYNTH_SYNTH7_RESET_SDM_B_MASK)
-#define SYNTH_SYNTH7_VC2HIGH_MSB 10
-#define SYNTH_SYNTH7_VC2HIGH_LSB 10
-#define SYNTH_SYNTH7_VC2HIGH_MASK 0x00000400
-#define SYNTH_SYNTH7_VC2HIGH_GET(x) (((x) & SYNTH_SYNTH7_VC2HIGH_MASK) >> SYNTH_SYNTH7_VC2HIGH_LSB)
-#define SYNTH_SYNTH7_VC2HIGH_SET(x) (((x) << SYNTH_SYNTH7_VC2HIGH_LSB) & SYNTH_SYNTH7_VC2HIGH_MASK)
-#define SYNTH_SYNTH7_VC2LOW_MSB 9
-#define SYNTH_SYNTH7_VC2LOW_LSB 9
-#define SYNTH_SYNTH7_VC2LOW_MASK 0x00000200
-#define SYNTH_SYNTH7_VC2LOW_GET(x) (((x) & SYNTH_SYNTH7_VC2LOW_MASK) >> SYNTH_SYNTH7_VC2LOW_LSB)
-#define SYNTH_SYNTH7_VC2LOW_SET(x) (((x) << SYNTH_SYNTH7_VC2LOW_LSB) & SYNTH_SYNTH7_VC2LOW_MASK)
-#define SYNTH_SYNTH7_LOOP_IP_MSB 8
-#define SYNTH_SYNTH7_LOOP_IP_LSB 5
-#define SYNTH_SYNTH7_LOOP_IP_MASK 0x000001e0
-#define SYNTH_SYNTH7_LOOP_IP_GET(x) (((x) & SYNTH_SYNTH7_LOOP_IP_MASK) >> SYNTH_SYNTH7_LOOP_IP_LSB)
-#define SYNTH_SYNTH7_LOOP_IP_SET(x) (((x) << SYNTH_SYNTH7_LOOP_IP_LSB) & SYNTH_SYNTH7_LOOP_IP_MASK)
-#define SYNTH_SYNTH7_LOBUF5GTUNE_MSB 4
-#define SYNTH_SYNTH7_LOBUF5GTUNE_LSB 3
-#define SYNTH_SYNTH7_LOBUF5GTUNE_MASK 0x00000018
-#define SYNTH_SYNTH7_LOBUF5GTUNE_GET(x) (((x) & SYNTH_SYNTH7_LOBUF5GTUNE_MASK) >> SYNTH_SYNTH7_LOBUF5GTUNE_LSB)
-#define SYNTH_SYNTH7_LOBUF5GTUNE_SET(x) (((x) << SYNTH_SYNTH7_LOBUF5GTUNE_LSB) & SYNTH_SYNTH7_LOBUF5GTUNE_MASK)
-#define SYNTH_SYNTH7_SPARE_READ_MSB 2
-#define SYNTH_SYNTH7_SPARE_READ_LSB 0
-#define SYNTH_SYNTH7_SPARE_READ_MASK 0x00000007
-#define SYNTH_SYNTH7_SPARE_READ_GET(x) (((x) & SYNTH_SYNTH7_SPARE_READ_MASK) >> SYNTH_SYNTH7_SPARE_READ_LSB)
-#define SYNTH_SYNTH7_SPARE_READ_SET(x) (((x) << SYNTH_SYNTH7_SPARE_READ_LSB) & SYNTH_SYNTH7_SPARE_READ_MASK)
-
-#define SYNTH_SYNTH8_ADDRESS 0x0000001c
-#define SYNTH_SYNTH8_OFFSET 0x0000001c
-#define SYNTH_SYNTH8_LOADSYNTHCHANNEL_MSB 31
-#define SYNTH_SYNTH8_LOADSYNTHCHANNEL_LSB 31
-#define SYNTH_SYNTH8_LOADSYNTHCHANNEL_MASK 0x80000000
-#define SYNTH_SYNTH8_LOADSYNTHCHANNEL_GET(x) (((x) & SYNTH_SYNTH8_LOADSYNTHCHANNEL_MASK) >> SYNTH_SYNTH8_LOADSYNTHCHANNEL_LSB)
-#define SYNTH_SYNTH8_LOADSYNTHCHANNEL_SET(x) (((x) << SYNTH_SYNTH8_LOADSYNTHCHANNEL_LSB) & SYNTH_SYNTH8_LOADSYNTHCHANNEL_MASK)
-#define SYNTH_SYNTH8_FRACMODE_MSB 30
-#define SYNTH_SYNTH8_FRACMODE_LSB 30
-#define SYNTH_SYNTH8_FRACMODE_MASK 0x40000000
-#define SYNTH_SYNTH8_FRACMODE_GET(x) (((x) & SYNTH_SYNTH8_FRACMODE_MASK) >> SYNTH_SYNTH8_FRACMODE_LSB)
-#define SYNTH_SYNTH8_FRACMODE_SET(x) (((x) << SYNTH_SYNTH8_FRACMODE_LSB) & SYNTH_SYNTH8_FRACMODE_MASK)
-#define SYNTH_SYNTH8_AMODEREFSEL_MSB 29
-#define SYNTH_SYNTH8_AMODEREFSEL_LSB 28
-#define SYNTH_SYNTH8_AMODEREFSEL_MASK 0x30000000
-#define SYNTH_SYNTH8_AMODEREFSEL_GET(x) (((x) & SYNTH_SYNTH8_AMODEREFSEL_MASK) >> SYNTH_SYNTH8_AMODEREFSEL_LSB)
-#define SYNTH_SYNTH8_AMODEREFSEL_SET(x) (((x) << SYNTH_SYNTH8_AMODEREFSEL_LSB) & SYNTH_SYNTH8_AMODEREFSEL_MASK)
-#define SYNTH_SYNTH8_SPARE_MSB 27
-#define SYNTH_SYNTH8_SPARE_LSB 27
-#define SYNTH_SYNTH8_SPARE_MASK 0x08000000
-#define SYNTH_SYNTH8_SPARE_GET(x) (((x) & SYNTH_SYNTH8_SPARE_MASK) >> SYNTH_SYNTH8_SPARE_LSB)
-#define SYNTH_SYNTH8_SPARE_SET(x) (((x) << SYNTH_SYNTH8_SPARE_LSB) & SYNTH_SYNTH8_SPARE_MASK)
-#define SYNTH_SYNTH8_CHANSEL_MSB 26
-#define SYNTH_SYNTH8_CHANSEL_LSB 18
-#define SYNTH_SYNTH8_CHANSEL_MASK 0x07fc0000
-#define SYNTH_SYNTH8_CHANSEL_GET(x) (((x) & SYNTH_SYNTH8_CHANSEL_MASK) >> SYNTH_SYNTH8_CHANSEL_LSB)
-#define SYNTH_SYNTH8_CHANSEL_SET(x) (((x) << SYNTH_SYNTH8_CHANSEL_LSB) & SYNTH_SYNTH8_CHANSEL_MASK)
-#define SYNTH_SYNTH8_CHANFRAC_MSB 17
-#define SYNTH_SYNTH8_CHANFRAC_LSB 1
-#define SYNTH_SYNTH8_CHANFRAC_MASK 0x0003fffe
-#define SYNTH_SYNTH8_CHANFRAC_GET(x) (((x) & SYNTH_SYNTH8_CHANFRAC_MASK) >> SYNTH_SYNTH8_CHANFRAC_LSB)
-#define SYNTH_SYNTH8_CHANFRAC_SET(x) (((x) << SYNTH_SYNTH8_CHANFRAC_LSB) & SYNTH_SYNTH8_CHANFRAC_MASK)
-#define SYNTH_SYNTH8_FORCE_FRACLSB_MSB 0
-#define SYNTH_SYNTH8_FORCE_FRACLSB_LSB 0
-#define SYNTH_SYNTH8_FORCE_FRACLSB_MASK 0x00000001
-#define SYNTH_SYNTH8_FORCE_FRACLSB_GET(x) (((x) & SYNTH_SYNTH8_FORCE_FRACLSB_MASK) >> SYNTH_SYNTH8_FORCE_FRACLSB_LSB)
-#define SYNTH_SYNTH8_FORCE_FRACLSB_SET(x) (((x) << SYNTH_SYNTH8_FORCE_FRACLSB_LSB) & SYNTH_SYNTH8_FORCE_FRACLSB_MASK)
-
-#define RF5G_RF5G1_ADDRESS 0x00000020
-#define RF5G_RF5G1_OFFSET 0x00000020
-#define RF5G_RF5G1_PDTXLO5_MSB 31
-#define RF5G_RF5G1_PDTXLO5_LSB 31
-#define RF5G_RF5G1_PDTXLO5_MASK 0x80000000
-#define RF5G_RF5G1_PDTXLO5_GET(x) (((x) & RF5G_RF5G1_PDTXLO5_MASK) >> RF5G_RF5G1_PDTXLO5_LSB)
-#define RF5G_RF5G1_PDTXLO5_SET(x) (((x) << RF5G_RF5G1_PDTXLO5_LSB) & RF5G_RF5G1_PDTXLO5_MASK)
-#define RF5G_RF5G1_PDTXMIX5_MSB 30
-#define RF5G_RF5G1_PDTXMIX5_LSB 30
-#define RF5G_RF5G1_PDTXMIX5_MASK 0x40000000
-#define RF5G_RF5G1_PDTXMIX5_GET(x) (((x) & RF5G_RF5G1_PDTXMIX5_MASK) >> RF5G_RF5G1_PDTXMIX5_LSB)
-#define RF5G_RF5G1_PDTXMIX5_SET(x) (((x) << RF5G_RF5G1_PDTXMIX5_LSB) & RF5G_RF5G1_PDTXMIX5_MASK)
-#define RF5G_RF5G1_PDTXBUF5_MSB 29
-#define RF5G_RF5G1_PDTXBUF5_LSB 29
-#define RF5G_RF5G1_PDTXBUF5_MASK 0x20000000
-#define RF5G_RF5G1_PDTXBUF5_GET(x) (((x) & RF5G_RF5G1_PDTXBUF5_MASK) >> RF5G_RF5G1_PDTXBUF5_LSB)
-#define RF5G_RF5G1_PDTXBUF5_SET(x) (((x) << RF5G_RF5G1_PDTXBUF5_LSB) & RF5G_RF5G1_PDTXBUF5_MASK)
-#define RF5G_RF5G1_PDPADRV5_MSB 28
-#define RF5G_RF5G1_PDPADRV5_LSB 28
-#define RF5G_RF5G1_PDPADRV5_MASK 0x10000000
-#define RF5G_RF5G1_PDPADRV5_GET(x) (((x) & RF5G_RF5G1_PDPADRV5_MASK) >> RF5G_RF5G1_PDPADRV5_LSB)
-#define RF5G_RF5G1_PDPADRV5_SET(x) (((x) << RF5G_RF5G1_PDPADRV5_LSB) & RF5G_RF5G1_PDPADRV5_MASK)
-#define RF5G_RF5G1_PDPAOUT5_MSB 27
-#define RF5G_RF5G1_PDPAOUT5_LSB 27
-#define RF5G_RF5G1_PDPAOUT5_MASK 0x08000000
-#define RF5G_RF5G1_PDPAOUT5_GET(x) (((x) & RF5G_RF5G1_PDPAOUT5_MASK) >> RF5G_RF5G1_PDPAOUT5_LSB)
-#define RF5G_RF5G1_PDPAOUT5_SET(x) (((x) << RF5G_RF5G1_PDPAOUT5_LSB) & RF5G_RF5G1_PDPAOUT5_MASK)
-#define RF5G_RF5G1_TUNE_PADRV5_MSB 26
-#define RF5G_RF5G1_TUNE_PADRV5_LSB 24
-#define RF5G_RF5G1_TUNE_PADRV5_MASK 0x07000000
-#define RF5G_RF5G1_TUNE_PADRV5_GET(x) (((x) & RF5G_RF5G1_TUNE_PADRV5_MASK) >> RF5G_RF5G1_TUNE_PADRV5_LSB)
-#define RF5G_RF5G1_TUNE_PADRV5_SET(x) (((x) << RF5G_RF5G1_TUNE_PADRV5_LSB) & RF5G_RF5G1_TUNE_PADRV5_MASK)
-#define RF5G_RF5G1_PWDTXPKD_MSB 23
-#define RF5G_RF5G1_PWDTXPKD_LSB 21
-#define RF5G_RF5G1_PWDTXPKD_MASK 0x00e00000
-#define RF5G_RF5G1_PWDTXPKD_GET(x) (((x) & RF5G_RF5G1_PWDTXPKD_MASK) >> RF5G_RF5G1_PWDTXPKD_LSB)
-#define RF5G_RF5G1_PWDTXPKD_SET(x) (((x) << RF5G_RF5G1_PWDTXPKD_LSB) & RF5G_RF5G1_PWDTXPKD_MASK)
-#define RF5G_RF5G1_DB5_MSB 20
-#define RF5G_RF5G1_DB5_LSB 18
-#define RF5G_RF5G1_DB5_MASK 0x001c0000
-#define RF5G_RF5G1_DB5_GET(x) (((x) & RF5G_RF5G1_DB5_MASK) >> RF5G_RF5G1_DB5_LSB)
-#define RF5G_RF5G1_DB5_SET(x) (((x) << RF5G_RF5G1_DB5_LSB) & RF5G_RF5G1_DB5_MASK)
-#define RF5G_RF5G1_OB5_MSB 17
-#define RF5G_RF5G1_OB5_LSB 15
-#define RF5G_RF5G1_OB5_MASK 0x00038000
-#define RF5G_RF5G1_OB5_GET(x) (((x) & RF5G_RF5G1_OB5_MASK) >> RF5G_RF5G1_OB5_LSB)
-#define RF5G_RF5G1_OB5_SET(x) (((x) << RF5G_RF5G1_OB5_LSB) & RF5G_RF5G1_OB5_MASK)
-#define RF5G_RF5G1_TX5_ATB_SEL_MSB 14
-#define RF5G_RF5G1_TX5_ATB_SEL_LSB 12
-#define RF5G_RF5G1_TX5_ATB_SEL_MASK 0x00007000
-#define RF5G_RF5G1_TX5_ATB_SEL_GET(x) (((x) & RF5G_RF5G1_TX5_ATB_SEL_MASK) >> RF5G_RF5G1_TX5_ATB_SEL_LSB)
-#define RF5G_RF5G1_TX5_ATB_SEL_SET(x) (((x) << RF5G_RF5G1_TX5_ATB_SEL_LSB) & RF5G_RF5G1_TX5_ATB_SEL_MASK)
-#define RF5G_RF5G1_PDLO5DIV_MSB 11
-#define RF5G_RF5G1_PDLO5DIV_LSB 11
-#define RF5G_RF5G1_PDLO5DIV_MASK 0x00000800
-#define RF5G_RF5G1_PDLO5DIV_GET(x) (((x) & RF5G_RF5G1_PDLO5DIV_MASK) >> RF5G_RF5G1_PDLO5DIV_LSB)
-#define RF5G_RF5G1_PDLO5DIV_SET(x) (((x) << RF5G_RF5G1_PDLO5DIV_LSB) & RF5G_RF5G1_PDLO5DIV_MASK)
-#define RF5G_RF5G1_PDLO5MIX_MSB 10
-#define RF5G_RF5G1_PDLO5MIX_LSB 10
-#define RF5G_RF5G1_PDLO5MIX_MASK 0x00000400
-#define RF5G_RF5G1_PDLO5MIX_GET(x) (((x) & RF5G_RF5G1_PDLO5MIX_MASK) >> RF5G_RF5G1_PDLO5MIX_LSB)
-#define RF5G_RF5G1_PDLO5MIX_SET(x) (((x) << RF5G_RF5G1_PDLO5MIX_LSB) & RF5G_RF5G1_PDLO5MIX_MASK)
-#define RF5G_RF5G1_PDQBUF5_MSB 9
-#define RF5G_RF5G1_PDQBUF5_LSB 9
-#define RF5G_RF5G1_PDQBUF5_MASK 0x00000200
-#define RF5G_RF5G1_PDQBUF5_GET(x) (((x) & RF5G_RF5G1_PDQBUF5_MASK) >> RF5G_RF5G1_PDQBUF5_LSB)
-#define RF5G_RF5G1_PDQBUF5_SET(x) (((x) << RF5G_RF5G1_PDQBUF5_LSB) & RF5G_RF5G1_PDQBUF5_MASK)
-#define RF5G_RF5G1_PDLO5AGC_MSB 8
-#define RF5G_RF5G1_PDLO5AGC_LSB 8
-#define RF5G_RF5G1_PDLO5AGC_MASK 0x00000100
-#define RF5G_RF5G1_PDLO5AGC_GET(x) (((x) & RF5G_RF5G1_PDLO5AGC_MASK) >> RF5G_RF5G1_PDLO5AGC_LSB)
-#define RF5G_RF5G1_PDLO5AGC_SET(x) (((x) << RF5G_RF5G1_PDLO5AGC_LSB) & RF5G_RF5G1_PDLO5AGC_MASK)
-#define RF5G_RF5G1_PDREGLO5_MSB 7
-#define RF5G_RF5G1_PDREGLO5_LSB 7
-#define RF5G_RF5G1_PDREGLO5_MASK 0x00000080
-#define RF5G_RF5G1_PDREGLO5_GET(x) (((x) & RF5G_RF5G1_PDREGLO5_MASK) >> RF5G_RF5G1_PDREGLO5_LSB)
-#define RF5G_RF5G1_PDREGLO5_SET(x) (((x) << RF5G_RF5G1_PDREGLO5_LSB) & RF5G_RF5G1_PDREGLO5_MASK)
-#define RF5G_RF5G1_LO5_ATB_SEL_MSB 6
-#define RF5G_RF5G1_LO5_ATB_SEL_LSB 4
-#define RF5G_RF5G1_LO5_ATB_SEL_MASK 0x00000070
-#define RF5G_RF5G1_LO5_ATB_SEL_GET(x) (((x) & RF5G_RF5G1_LO5_ATB_SEL_MASK) >> RF5G_RF5G1_LO5_ATB_SEL_LSB)
-#define RF5G_RF5G1_LO5_ATB_SEL_SET(x) (((x) << RF5G_RF5G1_LO5_ATB_SEL_LSB) & RF5G_RF5G1_LO5_ATB_SEL_MASK)
-#define RF5G_RF5G1_LO5CONTROL_MSB 3
-#define RF5G_RF5G1_LO5CONTROL_LSB 3
-#define RF5G_RF5G1_LO5CONTROL_MASK 0x00000008
-#define RF5G_RF5G1_LO5CONTROL_GET(x) (((x) & RF5G_RF5G1_LO5CONTROL_MASK) >> RF5G_RF5G1_LO5CONTROL_LSB)
-#define RF5G_RF5G1_LO5CONTROL_SET(x) (((x) << RF5G_RF5G1_LO5CONTROL_LSB) & RF5G_RF5G1_LO5CONTROL_MASK)
-#define RF5G_RF5G1_REGLO_BYPASS5_MSB 2
-#define RF5G_RF5G1_REGLO_BYPASS5_LSB 2
-#define RF5G_RF5G1_REGLO_BYPASS5_MASK 0x00000004
-#define RF5G_RF5G1_REGLO_BYPASS5_GET(x) (((x) & RF5G_RF5G1_REGLO_BYPASS5_MASK) >> RF5G_RF5G1_REGLO_BYPASS5_LSB)
-#define RF5G_RF5G1_REGLO_BYPASS5_SET(x) (((x) << RF5G_RF5G1_REGLO_BYPASS5_LSB) & RF5G_RF5G1_REGLO_BYPASS5_MASK)
-#define RF5G_RF5G1_SPARE_MSB 1
-#define RF5G_RF5G1_SPARE_LSB 0
-#define RF5G_RF5G1_SPARE_MASK 0x00000003
-#define RF5G_RF5G1_SPARE_GET(x) (((x) & RF5G_RF5G1_SPARE_MASK) >> RF5G_RF5G1_SPARE_LSB)
-#define RF5G_RF5G1_SPARE_SET(x) (((x) << RF5G_RF5G1_SPARE_LSB) & RF5G_RF5G1_SPARE_MASK)
-
-#define RF5G_RF5G2_ADDRESS 0x00000024
-#define RF5G_RF5G2_OFFSET 0x00000024
-#define RF5G_RF5G2_AGCLO_B_MSB 31
-#define RF5G_RF5G2_AGCLO_B_LSB 29
-#define RF5G_RF5G2_AGCLO_B_MASK 0xe0000000
-#define RF5G_RF5G2_AGCLO_B_GET(x) (((x) & RF5G_RF5G2_AGCLO_B_MASK) >> RF5G_RF5G2_AGCLO_B_LSB)
-#define RF5G_RF5G2_AGCLO_B_SET(x) (((x) << RF5G_RF5G2_AGCLO_B_LSB) & RF5G_RF5G2_AGCLO_B_MASK)
-#define RF5G_RF5G2_RX5_ATB_SEL_MSB 28
-#define RF5G_RF5G2_RX5_ATB_SEL_LSB 26
-#define RF5G_RF5G2_RX5_ATB_SEL_MASK 0x1c000000
-#define RF5G_RF5G2_RX5_ATB_SEL_GET(x) (((x) & RF5G_RF5G2_RX5_ATB_SEL_MASK) >> RF5G_RF5G2_RX5_ATB_SEL_LSB)
-#define RF5G_RF5G2_RX5_ATB_SEL_SET(x) (((x) << RF5G_RF5G2_RX5_ATB_SEL_LSB) & RF5G_RF5G2_RX5_ATB_SEL_MASK)
-#define RF5G_RF5G2_PDCMOSLO5_MSB 25
-#define RF5G_RF5G2_PDCMOSLO5_LSB 25
-#define RF5G_RF5G2_PDCMOSLO5_MASK 0x02000000
-#define RF5G_RF5G2_PDCMOSLO5_GET(x) (((x) & RF5G_RF5G2_PDCMOSLO5_MASK) >> RF5G_RF5G2_PDCMOSLO5_LSB)
-#define RF5G_RF5G2_PDCMOSLO5_SET(x) (((x) << RF5G_RF5G2_PDCMOSLO5_LSB) & RF5G_RF5G2_PDCMOSLO5_MASK)
-#define RF5G_RF5G2_PDVGM5_MSB 24
-#define RF5G_RF5G2_PDVGM5_LSB 24
-#define RF5G_RF5G2_PDVGM5_MASK 0x01000000
-#define RF5G_RF5G2_PDVGM5_GET(x) (((x) & RF5G_RF5G2_PDVGM5_MASK) >> RF5G_RF5G2_PDVGM5_LSB)
-#define RF5G_RF5G2_PDVGM5_SET(x) (((x) << RF5G_RF5G2_PDVGM5_LSB) & RF5G_RF5G2_PDVGM5_MASK)
-#define RF5G_RF5G2_PDCSLNA5_MSB 23
-#define RF5G_RF5G2_PDCSLNA5_LSB 23
-#define RF5G_RF5G2_PDCSLNA5_MASK 0x00800000
-#define RF5G_RF5G2_PDCSLNA5_GET(x) (((x) & RF5G_RF5G2_PDCSLNA5_MASK) >> RF5G_RF5G2_PDCSLNA5_LSB)
-#define RF5G_RF5G2_PDCSLNA5_SET(x) (((x) << RF5G_RF5G2_PDCSLNA5_LSB) & RF5G_RF5G2_PDCSLNA5_MASK)
-#define RF5G_RF5G2_PDRFVGA5_MSB 22
-#define RF5G_RF5G2_PDRFVGA5_LSB 22
-#define RF5G_RF5G2_PDRFVGA5_MASK 0x00400000
-#define RF5G_RF5G2_PDRFVGA5_GET(x) (((x) & RF5G_RF5G2_PDRFVGA5_MASK) >> RF5G_RF5G2_PDRFVGA5_LSB)
-#define RF5G_RF5G2_PDRFVGA5_SET(x) (((x) << RF5G_RF5G2_PDRFVGA5_LSB) & RF5G_RF5G2_PDRFVGA5_MASK)
-#define RF5G_RF5G2_PDREGFE5_MSB 21
-#define RF5G_RF5G2_PDREGFE5_LSB 21
-#define RF5G_RF5G2_PDREGFE5_MASK 0x00200000
-#define RF5G_RF5G2_PDREGFE5_GET(x) (((x) & RF5G_RF5G2_PDREGFE5_MASK) >> RF5G_RF5G2_PDREGFE5_LSB)
-#define RF5G_RF5G2_PDREGFE5_SET(x) (((x) << RF5G_RF5G2_PDREGFE5_LSB) & RF5G_RF5G2_PDREGFE5_MASK)
-#define RF5G_RF5G2_TUNE_RFVGA5_MSB 20
-#define RF5G_RF5G2_TUNE_RFVGA5_LSB 18
-#define RF5G_RF5G2_TUNE_RFVGA5_MASK 0x001c0000
-#define RF5G_RF5G2_TUNE_RFVGA5_GET(x) (((x) & RF5G_RF5G2_TUNE_RFVGA5_MASK) >> RF5G_RF5G2_TUNE_RFVGA5_LSB)
-#define RF5G_RF5G2_TUNE_RFVGA5_SET(x) (((x) << RF5G_RF5G2_TUNE_RFVGA5_LSB) & RF5G_RF5G2_TUNE_RFVGA5_MASK)
-#define RF5G_RF5G2_BRFVGA5_MSB 17
-#define RF5G_RF5G2_BRFVGA5_LSB 15
-#define RF5G_RF5G2_BRFVGA5_MASK 0x00038000
-#define RF5G_RF5G2_BRFVGA5_GET(x) (((x) & RF5G_RF5G2_BRFVGA5_MASK) >> RF5G_RF5G2_BRFVGA5_LSB)
-#define RF5G_RF5G2_BRFVGA5_SET(x) (((x) << RF5G_RF5G2_BRFVGA5_LSB) & RF5G_RF5G2_BRFVGA5_MASK)
-#define RF5G_RF5G2_BCSLNA5_MSB 14
-#define RF5G_RF5G2_BCSLNA5_LSB 12
-#define RF5G_RF5G2_BCSLNA5_MASK 0x00007000
-#define RF5G_RF5G2_BCSLNA5_GET(x) (((x) & RF5G_RF5G2_BCSLNA5_MASK) >> RF5G_RF5G2_BCSLNA5_LSB)
-#define RF5G_RF5G2_BCSLNA5_SET(x) (((x) << RF5G_RF5G2_BCSLNA5_LSB) & RF5G_RF5G2_BCSLNA5_MASK)
-#define RF5G_RF5G2_BVGM5_MSB 11
-#define RF5G_RF5G2_BVGM5_LSB 9
-#define RF5G_RF5G2_BVGM5_MASK 0x00000e00
-#define RF5G_RF5G2_BVGM5_GET(x) (((x) & RF5G_RF5G2_BVGM5_MASK) >> RF5G_RF5G2_BVGM5_LSB)
-#define RF5G_RF5G2_BVGM5_SET(x) (((x) << RF5G_RF5G2_BVGM5_LSB) & RF5G_RF5G2_BVGM5_MASK)
-#define RF5G_RF5G2_REGFE_BYPASS5_MSB 8
-#define RF5G_RF5G2_REGFE_BYPASS5_LSB 8
-#define RF5G_RF5G2_REGFE_BYPASS5_MASK 0x00000100
-#define RF5G_RF5G2_REGFE_BYPASS5_GET(x) (((x) & RF5G_RF5G2_REGFE_BYPASS5_MASK) >> RF5G_RF5G2_REGFE_BYPASS5_LSB)
-#define RF5G_RF5G2_REGFE_BYPASS5_SET(x) (((x) << RF5G_RF5G2_REGFE_BYPASS5_LSB) & RF5G_RF5G2_REGFE_BYPASS5_MASK)
-#define RF5G_RF5G2_LNA5_ATTENMODE_MSB 7
-#define RF5G_RF5G2_LNA5_ATTENMODE_LSB 6
-#define RF5G_RF5G2_LNA5_ATTENMODE_MASK 0x000000c0
-#define RF5G_RF5G2_LNA5_ATTENMODE_GET(x) (((x) & RF5G_RF5G2_LNA5_ATTENMODE_MASK) >> RF5G_RF5G2_LNA5_ATTENMODE_LSB)
-#define RF5G_RF5G2_LNA5_ATTENMODE_SET(x) (((x) << RF5G_RF5G2_LNA5_ATTENMODE_LSB) & RF5G_RF5G2_LNA5_ATTENMODE_MASK)
-#define RF5G_RF5G2_ENABLE_PCA_MSB 5
-#define RF5G_RF5G2_ENABLE_PCA_LSB 5
-#define RF5G_RF5G2_ENABLE_PCA_MASK 0x00000020
-#define RF5G_RF5G2_ENABLE_PCA_GET(x) (((x) & RF5G_RF5G2_ENABLE_PCA_MASK) >> RF5G_RF5G2_ENABLE_PCA_LSB)
-#define RF5G_RF5G2_ENABLE_PCA_SET(x) (((x) << RF5G_RF5G2_ENABLE_PCA_LSB) & RF5G_RF5G2_ENABLE_PCA_MASK)
-#define RF5G_RF5G2_TUNE_LO_MSB 4
-#define RF5G_RF5G2_TUNE_LO_LSB 2
-#define RF5G_RF5G2_TUNE_LO_MASK 0x0000001c
-#define RF5G_RF5G2_TUNE_LO_GET(x) (((x) & RF5G_RF5G2_TUNE_LO_MASK) >> RF5G_RF5G2_TUNE_LO_LSB)
-#define RF5G_RF5G2_TUNE_LO_SET(x) (((x) << RF5G_RF5G2_TUNE_LO_LSB) & RF5G_RF5G2_TUNE_LO_MASK)
-#define RF5G_RF5G2_SPARE_MSB 1
-#define RF5G_RF5G2_SPARE_LSB 0
-#define RF5G_RF5G2_SPARE_MASK 0x00000003
-#define RF5G_RF5G2_SPARE_GET(x) (((x) & RF5G_RF5G2_SPARE_MASK) >> RF5G_RF5G2_SPARE_LSB)
-#define RF5G_RF5G2_SPARE_SET(x) (((x) << RF5G_RF5G2_SPARE_LSB) & RF5G_RF5G2_SPARE_MASK)
-
-#define RF2G_RF2G1_ADDRESS 0x00000028
-#define RF2G_RF2G1_OFFSET 0x00000028
-#define RF2G_RF2G1_BLNA1_MSB 31
-#define RF2G_RF2G1_BLNA1_LSB 29
-#define RF2G_RF2G1_BLNA1_MASK 0xe0000000
-#define RF2G_RF2G1_BLNA1_GET(x) (((x) & RF2G_RF2G1_BLNA1_MASK) >> RF2G_RF2G1_BLNA1_LSB)
-#define RF2G_RF2G1_BLNA1_SET(x) (((x) << RF2G_RF2G1_BLNA1_LSB) & RF2G_RF2G1_BLNA1_MASK)
-#define RF2G_RF2G1_BLNA1F_MSB 28
-#define RF2G_RF2G1_BLNA1F_LSB 26
-#define RF2G_RF2G1_BLNA1F_MASK 0x1c000000
-#define RF2G_RF2G1_BLNA1F_GET(x) (((x) & RF2G_RF2G1_BLNA1F_MASK) >> RF2G_RF2G1_BLNA1F_LSB)
-#define RF2G_RF2G1_BLNA1F_SET(x) (((x) << RF2G_RF2G1_BLNA1F_LSB) & RF2G_RF2G1_BLNA1F_MASK)
-#define RF2G_RF2G1_BLNA1BUF_MSB 25
-#define RF2G_RF2G1_BLNA1BUF_LSB 23
-#define RF2G_RF2G1_BLNA1BUF_MASK 0x03800000
-#define RF2G_RF2G1_BLNA1BUF_GET(x) (((x) & RF2G_RF2G1_BLNA1BUF_MASK) >> RF2G_RF2G1_BLNA1BUF_LSB)
-#define RF2G_RF2G1_BLNA1BUF_SET(x) (((x) << RF2G_RF2G1_BLNA1BUF_LSB) & RF2G_RF2G1_BLNA1BUF_MASK)
-#define RF2G_RF2G1_BLNA2_MSB 22
-#define RF2G_RF2G1_BLNA2_LSB 20
-#define RF2G_RF2G1_BLNA2_MASK 0x00700000
-#define RF2G_RF2G1_BLNA2_GET(x) (((x) & RF2G_RF2G1_BLNA2_MASK) >> RF2G_RF2G1_BLNA2_LSB)
-#define RF2G_RF2G1_BLNA2_SET(x) (((x) << RF2G_RF2G1_BLNA2_LSB) & RF2G_RF2G1_BLNA2_MASK)
-#define RF2G_RF2G1_DB_MSB 19
-#define RF2G_RF2G1_DB_LSB 17
-#define RF2G_RF2G1_DB_MASK 0x000e0000
-#define RF2G_RF2G1_DB_GET(x) (((x) & RF2G_RF2G1_DB_MASK) >> RF2G_RF2G1_DB_LSB)
-#define RF2G_RF2G1_DB_SET(x) (((x) << RF2G_RF2G1_DB_LSB) & RF2G_RF2G1_DB_MASK)
-#define RF2G_RF2G1_OB_MSB 16
-#define RF2G_RF2G1_OB_LSB 14
-#define RF2G_RF2G1_OB_MASK 0x0001c000
-#define RF2G_RF2G1_OB_GET(x) (((x) & RF2G_RF2G1_OB_MASK) >> RF2G_RF2G1_OB_LSB)
-#define RF2G_RF2G1_OB_SET(x) (((x) << RF2G_RF2G1_OB_LSB) & RF2G_RF2G1_OB_MASK)
-#define RF2G_RF2G1_FE_ATB_SEL_MSB 13
-#define RF2G_RF2G1_FE_ATB_SEL_LSB 11
-#define RF2G_RF2G1_FE_ATB_SEL_MASK 0x00003800
-#define RF2G_RF2G1_FE_ATB_SEL_GET(x) (((x) & RF2G_RF2G1_FE_ATB_SEL_MASK) >> RF2G_RF2G1_FE_ATB_SEL_LSB)
-#define RF2G_RF2G1_FE_ATB_SEL_SET(x) (((x) << RF2G_RF2G1_FE_ATB_SEL_LSB) & RF2G_RF2G1_FE_ATB_SEL_MASK)
-#define RF2G_RF2G1_RF_ATB_SEL_MSB 10
-#define RF2G_RF2G1_RF_ATB_SEL_LSB 8
-#define RF2G_RF2G1_RF_ATB_SEL_MASK 0x00000700
-#define RF2G_RF2G1_RF_ATB_SEL_GET(x) (((x) & RF2G_RF2G1_RF_ATB_SEL_MASK) >> RF2G_RF2G1_RF_ATB_SEL_LSB)
-#define RF2G_RF2G1_RF_ATB_SEL_SET(x) (((x) << RF2G_RF2G1_RF_ATB_SEL_LSB) & RF2G_RF2G1_RF_ATB_SEL_MASK)
-#define RF2G_RF2G1_SELLNA_MSB 7
-#define RF2G_RF2G1_SELLNA_LSB 7
-#define RF2G_RF2G1_SELLNA_MASK 0x00000080
-#define RF2G_RF2G1_SELLNA_GET(x) (((x) & RF2G_RF2G1_SELLNA_MASK) >> RF2G_RF2G1_SELLNA_LSB)
-#define RF2G_RF2G1_SELLNA_SET(x) (((x) << RF2G_RF2G1_SELLNA_LSB) & RF2G_RF2G1_SELLNA_MASK)
-#define RF2G_RF2G1_LOCONTROL_MSB 6
-#define RF2G_RF2G1_LOCONTROL_LSB 6
-#define RF2G_RF2G1_LOCONTROL_MASK 0x00000040
-#define RF2G_RF2G1_LOCONTROL_GET(x) (((x) & RF2G_RF2G1_LOCONTROL_MASK) >> RF2G_RF2G1_LOCONTROL_LSB)
-#define RF2G_RF2G1_LOCONTROL_SET(x) (((x) << RF2G_RF2G1_LOCONTROL_LSB) & RF2G_RF2G1_LOCONTROL_MASK)
-#define RF2G_RF2G1_SHORTLNA2_MSB 5
-#define RF2G_RF2G1_SHORTLNA2_LSB 5
-#define RF2G_RF2G1_SHORTLNA2_MASK 0x00000020
-#define RF2G_RF2G1_SHORTLNA2_GET(x) (((x) & RF2G_RF2G1_SHORTLNA2_MASK) >> RF2G_RF2G1_SHORTLNA2_LSB)
-#define RF2G_RF2G1_SHORTLNA2_SET(x) (((x) << RF2G_RF2G1_SHORTLNA2_LSB) & RF2G_RF2G1_SHORTLNA2_MASK)
-#define RF2G_RF2G1_SPARE_MSB 4
-#define RF2G_RF2G1_SPARE_LSB 0
-#define RF2G_RF2G1_SPARE_MASK 0x0000001f
-#define RF2G_RF2G1_SPARE_GET(x) (((x) & RF2G_RF2G1_SPARE_MASK) >> RF2G_RF2G1_SPARE_LSB)
-#define RF2G_RF2G1_SPARE_SET(x) (((x) << RF2G_RF2G1_SPARE_LSB) & RF2G_RF2G1_SPARE_MASK)
-
-#define RF2G_RF2G2_ADDRESS 0x0000002c
-#define RF2G_RF2G2_OFFSET 0x0000002c
-#define RF2G_RF2G2_PDCGLNA_MSB 31
-#define RF2G_RF2G2_PDCGLNA_LSB 31
-#define RF2G_RF2G2_PDCGLNA_MASK 0x80000000
-#define RF2G_RF2G2_PDCGLNA_GET(x) (((x) & RF2G_RF2G2_PDCGLNA_MASK) >> RF2G_RF2G2_PDCGLNA_LSB)
-#define RF2G_RF2G2_PDCGLNA_SET(x) (((x) << RF2G_RF2G2_PDCGLNA_LSB) & RF2G_RF2G2_PDCGLNA_MASK)
-#define RF2G_RF2G2_PDCGLNABUF_MSB 30
-#define RF2G_RF2G2_PDCGLNABUF_LSB 30
-#define RF2G_RF2G2_PDCGLNABUF_MASK 0x40000000
-#define RF2G_RF2G2_PDCGLNABUF_GET(x) (((x) & RF2G_RF2G2_PDCGLNABUF_MASK) >> RF2G_RF2G2_PDCGLNABUF_LSB)
-#define RF2G_RF2G2_PDCGLNABUF_SET(x) (((x) << RF2G_RF2G2_PDCGLNABUF_LSB) & RF2G_RF2G2_PDCGLNABUF_MASK)
-#define RF2G_RF2G2_PDCSLNA_MSB 29
-#define RF2G_RF2G2_PDCSLNA_LSB 29
-#define RF2G_RF2G2_PDCSLNA_MASK 0x20000000
-#define RF2G_RF2G2_PDCSLNA_GET(x) (((x) & RF2G_RF2G2_PDCSLNA_MASK) >> RF2G_RF2G2_PDCSLNA_LSB)
-#define RF2G_RF2G2_PDCSLNA_SET(x) (((x) << RF2G_RF2G2_PDCSLNA_LSB) & RF2G_RF2G2_PDCSLNA_MASK)
-#define RF2G_RF2G2_PDDIV_MSB 28
-#define RF2G_RF2G2_PDDIV_LSB 28
-#define RF2G_RF2G2_PDDIV_MASK 0x10000000
-#define RF2G_RF2G2_PDDIV_GET(x) (((x) & RF2G_RF2G2_PDDIV_MASK) >> RF2G_RF2G2_PDDIV_LSB)
-#define RF2G_RF2G2_PDDIV_SET(x) (((x) << RF2G_RF2G2_PDDIV_LSB) & RF2G_RF2G2_PDDIV_MASK)
-#define RF2G_RF2G2_PDPADRV_MSB 27
-#define RF2G_RF2G2_PDPADRV_LSB 27
-#define RF2G_RF2G2_PDPADRV_MASK 0x08000000
-#define RF2G_RF2G2_PDPADRV_GET(x) (((x) & RF2G_RF2G2_PDPADRV_MASK) >> RF2G_RF2G2_PDPADRV_LSB)
-#define RF2G_RF2G2_PDPADRV_SET(x) (((x) << RF2G_RF2G2_PDPADRV_LSB) & RF2G_RF2G2_PDPADRV_MASK)
-#define RF2G_RF2G2_PDPAOUT_MSB 26
-#define RF2G_RF2G2_PDPAOUT_LSB 26
-#define RF2G_RF2G2_PDPAOUT_MASK 0x04000000
-#define RF2G_RF2G2_PDPAOUT_GET(x) (((x) & RF2G_RF2G2_PDPAOUT_MASK) >> RF2G_RF2G2_PDPAOUT_LSB)
-#define RF2G_RF2G2_PDPAOUT_SET(x) (((x) << RF2G_RF2G2_PDPAOUT_LSB) & RF2G_RF2G2_PDPAOUT_MASK)
-#define RF2G_RF2G2_PDREGLNA_MSB 25
-#define RF2G_RF2G2_PDREGLNA_LSB 25
-#define RF2G_RF2G2_PDREGLNA_MASK 0x02000000
-#define RF2G_RF2G2_PDREGLNA_GET(x) (((x) & RF2G_RF2G2_PDREGLNA_MASK) >> RF2G_RF2G2_PDREGLNA_LSB)
-#define RF2G_RF2G2_PDREGLNA_SET(x) (((x) << RF2G_RF2G2_PDREGLNA_LSB) & RF2G_RF2G2_PDREGLNA_MASK)
-#define RF2G_RF2G2_PDREGLO_MSB 24
-#define RF2G_RF2G2_PDREGLO_LSB 24
-#define RF2G_RF2G2_PDREGLO_MASK 0x01000000
-#define RF2G_RF2G2_PDREGLO_GET(x) (((x) & RF2G_RF2G2_PDREGLO_MASK) >> RF2G_RF2G2_PDREGLO_LSB)
-#define RF2G_RF2G2_PDREGLO_SET(x) (((x) << RF2G_RF2G2_PDREGLO_LSB) & RF2G_RF2G2_PDREGLO_MASK)
-#define RF2G_RF2G2_PDRFGM_MSB 23
-#define RF2G_RF2G2_PDRFGM_LSB 23
-#define RF2G_RF2G2_PDRFGM_MASK 0x00800000
-#define RF2G_RF2G2_PDRFGM_GET(x) (((x) & RF2G_RF2G2_PDRFGM_MASK) >> RF2G_RF2G2_PDRFGM_LSB)
-#define RF2G_RF2G2_PDRFGM_SET(x) (((x) << RF2G_RF2G2_PDRFGM_LSB) & RF2G_RF2G2_PDRFGM_MASK)
-#define RF2G_RF2G2_PDRXLO_MSB 22
-#define RF2G_RF2G2_PDRXLO_LSB 22
-#define RF2G_RF2G2_PDRXLO_MASK 0x00400000
-#define RF2G_RF2G2_PDRXLO_GET(x) (((x) & RF2G_RF2G2_PDRXLO_MASK) >> RF2G_RF2G2_PDRXLO_LSB)
-#define RF2G_RF2G2_PDRXLO_SET(x) (((x) << RF2G_RF2G2_PDRXLO_LSB) & RF2G_RF2G2_PDRXLO_MASK)
-#define RF2G_RF2G2_PDTXLO_MSB 21
-#define RF2G_RF2G2_PDTXLO_LSB 21
-#define RF2G_RF2G2_PDTXLO_MASK 0x00200000
-#define RF2G_RF2G2_PDTXLO_GET(x) (((x) & RF2G_RF2G2_PDTXLO_MASK) >> RF2G_RF2G2_PDTXLO_LSB)
-#define RF2G_RF2G2_PDTXLO_SET(x) (((x) << RF2G_RF2G2_PDTXLO_LSB) & RF2G_RF2G2_PDTXLO_MASK)
-#define RF2G_RF2G2_PDTXMIX_MSB 20
-#define RF2G_RF2G2_PDTXMIX_LSB 20
-#define RF2G_RF2G2_PDTXMIX_MASK 0x00100000
-#define RF2G_RF2G2_PDTXMIX_GET(x) (((x) & RF2G_RF2G2_PDTXMIX_MASK) >> RF2G_RF2G2_PDTXMIX_LSB)
-#define RF2G_RF2G2_PDTXMIX_SET(x) (((x) << RF2G_RF2G2_PDTXMIX_LSB) & RF2G_RF2G2_PDTXMIX_MASK)
-#define RF2G_RF2G2_REGLNA_BYPASS_MSB 19
-#define RF2G_RF2G2_REGLNA_BYPASS_LSB 19
-#define RF2G_RF2G2_REGLNA_BYPASS_MASK 0x00080000
-#define RF2G_RF2G2_REGLNA_BYPASS_GET(x) (((x) & RF2G_RF2G2_REGLNA_BYPASS_MASK) >> RF2G_RF2G2_REGLNA_BYPASS_LSB)
-#define RF2G_RF2G2_REGLNA_BYPASS_SET(x) (((x) << RF2G_RF2G2_REGLNA_BYPASS_LSB) & RF2G_RF2G2_REGLNA_BYPASS_MASK)
-#define RF2G_RF2G2_REGLO_BYPASS_MSB 18
-#define RF2G_RF2G2_REGLO_BYPASS_LSB 18
-#define RF2G_RF2G2_REGLO_BYPASS_MASK 0x00040000
-#define RF2G_RF2G2_REGLO_BYPASS_GET(x) (((x) & RF2G_RF2G2_REGLO_BYPASS_MASK) >> RF2G_RF2G2_REGLO_BYPASS_LSB)
-#define RF2G_RF2G2_REGLO_BYPASS_SET(x) (((x) << RF2G_RF2G2_REGLO_BYPASS_LSB) & RF2G_RF2G2_REGLO_BYPASS_MASK)
-#define RF2G_RF2G2_ENABLE_PCB_MSB 17
-#define RF2G_RF2G2_ENABLE_PCB_LSB 17
-#define RF2G_RF2G2_ENABLE_PCB_MASK 0x00020000
-#define RF2G_RF2G2_ENABLE_PCB_GET(x) (((x) & RF2G_RF2G2_ENABLE_PCB_MASK) >> RF2G_RF2G2_ENABLE_PCB_LSB)
-#define RF2G_RF2G2_ENABLE_PCB_SET(x) (((x) << RF2G_RF2G2_ENABLE_PCB_LSB) & RF2G_RF2G2_ENABLE_PCB_MASK)
-#define RF2G_RF2G2_SPARE_MSB 16
-#define RF2G_RF2G2_SPARE_LSB 0
-#define RF2G_RF2G2_SPARE_MASK 0x0001ffff
-#define RF2G_RF2G2_SPARE_GET(x) (((x) & RF2G_RF2G2_SPARE_MASK) >> RF2G_RF2G2_SPARE_LSB)
-#define RF2G_RF2G2_SPARE_SET(x) (((x) << RF2G_RF2G2_SPARE_LSB) & RF2G_RF2G2_SPARE_MASK)
-
-#define TOP_GAIN_ADDRESS 0x00000030
-#define TOP_GAIN_OFFSET 0x00000030
-#define TOP_GAIN_TX6DBLOQGAIN_MSB 31
-#define TOP_GAIN_TX6DBLOQGAIN_LSB 30
-#define TOP_GAIN_TX6DBLOQGAIN_MASK 0xc0000000
-#define TOP_GAIN_TX6DBLOQGAIN_GET(x) (((x) & TOP_GAIN_TX6DBLOQGAIN_MASK) >> TOP_GAIN_TX6DBLOQGAIN_LSB)
-#define TOP_GAIN_TX6DBLOQGAIN_SET(x) (((x) << TOP_GAIN_TX6DBLOQGAIN_LSB) & TOP_GAIN_TX6DBLOQGAIN_MASK)
-#define TOP_GAIN_TX1DBLOQGAIN_MSB 29
-#define TOP_GAIN_TX1DBLOQGAIN_LSB 27
-#define TOP_GAIN_TX1DBLOQGAIN_MASK 0x38000000
-#define TOP_GAIN_TX1DBLOQGAIN_GET(x) (((x) & TOP_GAIN_TX1DBLOQGAIN_MASK) >> TOP_GAIN_TX1DBLOQGAIN_LSB)
-#define TOP_GAIN_TX1DBLOQGAIN_SET(x) (((x) << TOP_GAIN_TX1DBLOQGAIN_LSB) & TOP_GAIN_TX1DBLOQGAIN_MASK)
-#define TOP_GAIN_TXV2IGAIN_MSB 26
-#define TOP_GAIN_TXV2IGAIN_LSB 25
-#define TOP_GAIN_TXV2IGAIN_MASK 0x06000000
-#define TOP_GAIN_TXV2IGAIN_GET(x) (((x) & TOP_GAIN_TXV2IGAIN_MASK) >> TOP_GAIN_TXV2IGAIN_LSB)
-#define TOP_GAIN_TXV2IGAIN_SET(x) (((x) << TOP_GAIN_TXV2IGAIN_LSB) & TOP_GAIN_TXV2IGAIN_MASK)
-#define TOP_GAIN_PABUF5GN_MSB 24
-#define TOP_GAIN_PABUF5GN_LSB 24
-#define TOP_GAIN_PABUF5GN_MASK 0x01000000
-#define TOP_GAIN_PABUF5GN_GET(x) (((x) & TOP_GAIN_PABUF5GN_MASK) >> TOP_GAIN_PABUF5GN_LSB)
-#define TOP_GAIN_PABUF5GN_SET(x) (((x) << TOP_GAIN_PABUF5GN_LSB) & TOP_GAIN_PABUF5GN_MASK)
-#define TOP_GAIN_PADRVGN_MSB 23
-#define TOP_GAIN_PADRVGN_LSB 21
-#define TOP_GAIN_PADRVGN_MASK 0x00e00000
-#define TOP_GAIN_PADRVGN_GET(x) (((x) & TOP_GAIN_PADRVGN_MASK) >> TOP_GAIN_PADRVGN_LSB)
-#define TOP_GAIN_PADRVGN_SET(x) (((x) << TOP_GAIN_PADRVGN_LSB) & TOP_GAIN_PADRVGN_MASK)
-#define TOP_GAIN_PAOUT2GN_MSB 20
-#define TOP_GAIN_PAOUT2GN_LSB 18
-#define TOP_GAIN_PAOUT2GN_MASK 0x001c0000
-#define TOP_GAIN_PAOUT2GN_GET(x) (((x) & TOP_GAIN_PAOUT2GN_MASK) >> TOP_GAIN_PAOUT2GN_LSB)
-#define TOP_GAIN_PAOUT2GN_SET(x) (((x) << TOP_GAIN_PAOUT2GN_LSB) & TOP_GAIN_PAOUT2GN_MASK)
-#define TOP_GAIN_LNAON_MSB 17
-#define TOP_GAIN_LNAON_LSB 17
-#define TOP_GAIN_LNAON_MASK 0x00020000
-#define TOP_GAIN_LNAON_GET(x) (((x) & TOP_GAIN_LNAON_MASK) >> TOP_GAIN_LNAON_LSB)
-#define TOP_GAIN_LNAON_SET(x) (((x) << TOP_GAIN_LNAON_LSB) & TOP_GAIN_LNAON_MASK)
-#define TOP_GAIN_LNAGAIN_MSB 16
-#define TOP_GAIN_LNAGAIN_LSB 13
-#define TOP_GAIN_LNAGAIN_MASK 0x0001e000
-#define TOP_GAIN_LNAGAIN_GET(x) (((x) & TOP_GAIN_LNAGAIN_MASK) >> TOP_GAIN_LNAGAIN_LSB)
-#define TOP_GAIN_LNAGAIN_SET(x) (((x) << TOP_GAIN_LNAGAIN_LSB) & TOP_GAIN_LNAGAIN_MASK)
-#define TOP_GAIN_RFVGA5GAIN_MSB 12
-#define TOP_GAIN_RFVGA5GAIN_LSB 11
-#define TOP_GAIN_RFVGA5GAIN_MASK 0x00001800
-#define TOP_GAIN_RFVGA5GAIN_GET(x) (((x) & TOP_GAIN_RFVGA5GAIN_MASK) >> TOP_GAIN_RFVGA5GAIN_LSB)
-#define TOP_GAIN_RFVGA5GAIN_SET(x) (((x) << TOP_GAIN_RFVGA5GAIN_LSB) & TOP_GAIN_RFVGA5GAIN_MASK)
-#define TOP_GAIN_RFGMGN_MSB 10
-#define TOP_GAIN_RFGMGN_LSB 8
-#define TOP_GAIN_RFGMGN_MASK 0x00000700
-#define TOP_GAIN_RFGMGN_GET(x) (((x) & TOP_GAIN_RFGMGN_MASK) >> TOP_GAIN_RFGMGN_LSB)
-#define TOP_GAIN_RFGMGN_SET(x) (((x) << TOP_GAIN_RFGMGN_LSB) & TOP_GAIN_RFGMGN_MASK)
-#define TOP_GAIN_RX6DBLOQGAIN_MSB 7
-#define TOP_GAIN_RX6DBLOQGAIN_LSB 6
-#define TOP_GAIN_RX6DBLOQGAIN_MASK 0x000000c0
-#define TOP_GAIN_RX6DBLOQGAIN_GET(x) (((x) & TOP_GAIN_RX6DBLOQGAIN_MASK) >> TOP_GAIN_RX6DBLOQGAIN_LSB)
-#define TOP_GAIN_RX6DBLOQGAIN_SET(x) (((x) << TOP_GAIN_RX6DBLOQGAIN_LSB) & TOP_GAIN_RX6DBLOQGAIN_MASK)
-#define TOP_GAIN_RX1DBLOQGAIN_MSB 5
-#define TOP_GAIN_RX1DBLOQGAIN_LSB 3
-#define TOP_GAIN_RX1DBLOQGAIN_MASK 0x00000038
-#define TOP_GAIN_RX1DBLOQGAIN_GET(x) (((x) & TOP_GAIN_RX1DBLOQGAIN_MASK) >> TOP_GAIN_RX1DBLOQGAIN_LSB)
-#define TOP_GAIN_RX1DBLOQGAIN_SET(x) (((x) << TOP_GAIN_RX1DBLOQGAIN_LSB) & TOP_GAIN_RX1DBLOQGAIN_MASK)
-#define TOP_GAIN_RX6DBHIQGAIN_MSB 2
-#define TOP_GAIN_RX6DBHIQGAIN_LSB 1
-#define TOP_GAIN_RX6DBHIQGAIN_MASK 0x00000006
-#define TOP_GAIN_RX6DBHIQGAIN_GET(x) (((x) & TOP_GAIN_RX6DBHIQGAIN_MASK) >> TOP_GAIN_RX6DBHIQGAIN_LSB)
-#define TOP_GAIN_RX6DBHIQGAIN_SET(x) (((x) << TOP_GAIN_RX6DBHIQGAIN_LSB) & TOP_GAIN_RX6DBHIQGAIN_MASK)
-#define TOP_GAIN_SPARE_MSB 0
-#define TOP_GAIN_SPARE_LSB 0
-#define TOP_GAIN_SPARE_MASK 0x00000001
-#define TOP_GAIN_SPARE_GET(x) (((x) & TOP_GAIN_SPARE_MASK) >> TOP_GAIN_SPARE_LSB)
-#define TOP_GAIN_SPARE_SET(x) (((x) << TOP_GAIN_SPARE_LSB) & TOP_GAIN_SPARE_MASK)
-
-#define TOP_TOP_ADDRESS 0x00000034
-#define TOP_TOP_OFFSET 0x00000034
-#define TOP_TOP_LOCALTXGAIN_MSB 31
-#define TOP_TOP_LOCALTXGAIN_LSB 31
-#define TOP_TOP_LOCALTXGAIN_MASK 0x80000000
-#define TOP_TOP_LOCALTXGAIN_GET(x) (((x) & TOP_TOP_LOCALTXGAIN_MASK) >> TOP_TOP_LOCALTXGAIN_LSB)
-#define TOP_TOP_LOCALTXGAIN_SET(x) (((x) << TOP_TOP_LOCALTXGAIN_LSB) & TOP_TOP_LOCALTXGAIN_MASK)
-#define TOP_TOP_LOCALRXGAIN_MSB 30
-#define TOP_TOP_LOCALRXGAIN_LSB 30
-#define TOP_TOP_LOCALRXGAIN_MASK 0x40000000
-#define TOP_TOP_LOCALRXGAIN_GET(x) (((x) & TOP_TOP_LOCALRXGAIN_MASK) >> TOP_TOP_LOCALRXGAIN_LSB)
-#define TOP_TOP_LOCALRXGAIN_SET(x) (((x) << TOP_TOP_LOCALRXGAIN_LSB) & TOP_TOP_LOCALRXGAIN_MASK)
-#define TOP_TOP_LOCALMODE_MSB 29
-#define TOP_TOP_LOCALMODE_LSB 29
-#define TOP_TOP_LOCALMODE_MASK 0x20000000
-#define TOP_TOP_LOCALMODE_GET(x) (((x) & TOP_TOP_LOCALMODE_MASK) >> TOP_TOP_LOCALMODE_LSB)
-#define TOP_TOP_LOCALMODE_SET(x) (((x) << TOP_TOP_LOCALMODE_LSB) & TOP_TOP_LOCALMODE_MASK)
-#define TOP_TOP_CALFC_MSB 28
-#define TOP_TOP_CALFC_LSB 28
-#define TOP_TOP_CALFC_MASK 0x10000000
-#define TOP_TOP_CALFC_GET(x) (((x) & TOP_TOP_CALFC_MASK) >> TOP_TOP_CALFC_LSB)
-#define TOP_TOP_CALFC_SET(x) (((x) << TOP_TOP_CALFC_LSB) & TOP_TOP_CALFC_MASK)
-#define TOP_TOP_CALDC_MSB 27
-#define TOP_TOP_CALDC_LSB 27
-#define TOP_TOP_CALDC_MASK 0x08000000
-#define TOP_TOP_CALDC_GET(x) (((x) & TOP_TOP_CALDC_MASK) >> TOP_TOP_CALDC_LSB)
-#define TOP_TOP_CALDC_SET(x) (((x) << TOP_TOP_CALDC_LSB) & TOP_TOP_CALDC_MASK)
-#define TOP_TOP_CAL_RESIDUE_MSB 26
-#define TOP_TOP_CAL_RESIDUE_LSB 26
-#define TOP_TOP_CAL_RESIDUE_MASK 0x04000000
-#define TOP_TOP_CAL_RESIDUE_GET(x) (((x) & TOP_TOP_CAL_RESIDUE_MASK) >> TOP_TOP_CAL_RESIDUE_LSB)
-#define TOP_TOP_CAL_RESIDUE_SET(x) (((x) << TOP_TOP_CAL_RESIDUE_LSB) & TOP_TOP_CAL_RESIDUE_MASK)
-#define TOP_TOP_BMODE_MSB 25
-#define TOP_TOP_BMODE_LSB 25
-#define TOP_TOP_BMODE_MASK 0x02000000
-#define TOP_TOP_BMODE_GET(x) (((x) & TOP_TOP_BMODE_MASK) >> TOP_TOP_BMODE_LSB)
-#define TOP_TOP_BMODE_SET(x) (((x) << TOP_TOP_BMODE_LSB) & TOP_TOP_BMODE_MASK)
-#define TOP_TOP_SYNTHON_MSB 24
-#define TOP_TOP_SYNTHON_LSB 24
-#define TOP_TOP_SYNTHON_MASK 0x01000000
-#define TOP_TOP_SYNTHON_GET(x) (((x) & TOP_TOP_SYNTHON_MASK) >> TOP_TOP_SYNTHON_LSB)
-#define TOP_TOP_SYNTHON_SET(x) (((x) << TOP_TOP_SYNTHON_LSB) & TOP_TOP_SYNTHON_MASK)
-#define TOP_TOP_RXON_MSB 23
-#define TOP_TOP_RXON_LSB 23
-#define TOP_TOP_RXON_MASK 0x00800000
-#define TOP_TOP_RXON_GET(x) (((x) & TOP_TOP_RXON_MASK) >> TOP_TOP_RXON_LSB)
-#define TOP_TOP_RXON_SET(x) (((x) << TOP_TOP_RXON_LSB) & TOP_TOP_RXON_MASK)
-#define TOP_TOP_TXON_MSB 22
-#define TOP_TOP_TXON_LSB 22
-#define TOP_TOP_TXON_MASK 0x00400000
-#define TOP_TOP_TXON_GET(x) (((x) & TOP_TOP_TXON_MASK) >> TOP_TOP_TXON_LSB)
-#define TOP_TOP_TXON_SET(x) (((x) << TOP_TOP_TXON_LSB) & TOP_TOP_TXON_MASK)
-#define TOP_TOP_PAON_MSB 21
-#define TOP_TOP_PAON_LSB 21
-#define TOP_TOP_PAON_MASK 0x00200000
-#define TOP_TOP_PAON_GET(x) (((x) & TOP_TOP_PAON_MASK) >> TOP_TOP_PAON_LSB)
-#define TOP_TOP_PAON_SET(x) (((x) << TOP_TOP_PAON_LSB) & TOP_TOP_PAON_MASK)
-#define TOP_TOP_CALTX_MSB 20
-#define TOP_TOP_CALTX_LSB 20
-#define TOP_TOP_CALTX_MASK 0x00100000
-#define TOP_TOP_CALTX_GET(x) (((x) & TOP_TOP_CALTX_MASK) >> TOP_TOP_CALTX_LSB)
-#define TOP_TOP_CALTX_SET(x) (((x) << TOP_TOP_CALTX_LSB) & TOP_TOP_CALTX_MASK)
-#define TOP_TOP_LOCALADDAC_MSB 19
-#define TOP_TOP_LOCALADDAC_LSB 19
-#define TOP_TOP_LOCALADDAC_MASK 0x00080000
-#define TOP_TOP_LOCALADDAC_GET(x) (((x) & TOP_TOP_LOCALADDAC_MASK) >> TOP_TOP_LOCALADDAC_LSB)
-#define TOP_TOP_LOCALADDAC_SET(x) (((x) << TOP_TOP_LOCALADDAC_LSB) & TOP_TOP_LOCALADDAC_MASK)
-#define TOP_TOP_PWDPLL_MSB 18
-#define TOP_TOP_PWDPLL_LSB 18
-#define TOP_TOP_PWDPLL_MASK 0x00040000
-#define TOP_TOP_PWDPLL_GET(x) (((x) & TOP_TOP_PWDPLL_MASK) >> TOP_TOP_PWDPLL_LSB)
-#define TOP_TOP_PWDPLL_SET(x) (((x) << TOP_TOP_PWDPLL_LSB) & TOP_TOP_PWDPLL_MASK)
-#define TOP_TOP_PWDADC_MSB 17
-#define TOP_TOP_PWDADC_LSB 17
-#define TOP_TOP_PWDADC_MASK 0x00020000
-#define TOP_TOP_PWDADC_GET(x) (((x) & TOP_TOP_PWDADC_MASK) >> TOP_TOP_PWDADC_LSB)
-#define TOP_TOP_PWDADC_SET(x) (((x) << TOP_TOP_PWDADC_LSB) & TOP_TOP_PWDADC_MASK)
-#define TOP_TOP_PWDDAC_MSB 16
-#define TOP_TOP_PWDDAC_LSB 16
-#define TOP_TOP_PWDDAC_MASK 0x00010000
-#define TOP_TOP_PWDDAC_GET(x) (((x) & TOP_TOP_PWDDAC_MASK) >> TOP_TOP_PWDDAC_LSB)
-#define TOP_TOP_PWDDAC_SET(x) (((x) << TOP_TOP_PWDDAC_LSB) & TOP_TOP_PWDDAC_MASK)
-#define TOP_TOP_LOCALXTAL_MSB 15
-#define TOP_TOP_LOCALXTAL_LSB 15
-#define TOP_TOP_LOCALXTAL_MASK 0x00008000
-#define TOP_TOP_LOCALXTAL_GET(x) (((x) & TOP_TOP_LOCALXTAL_MASK) >> TOP_TOP_LOCALXTAL_LSB)
-#define TOP_TOP_LOCALXTAL_SET(x) (((x) << TOP_TOP_LOCALXTAL_LSB) & TOP_TOP_LOCALXTAL_MASK)
-#define TOP_TOP_PWDCLKIN_MSB 14
-#define TOP_TOP_PWDCLKIN_LSB 14
-#define TOP_TOP_PWDCLKIN_MASK 0x00004000
-#define TOP_TOP_PWDCLKIN_GET(x) (((x) & TOP_TOP_PWDCLKIN_MASK) >> TOP_TOP_PWDCLKIN_LSB)
-#define TOP_TOP_PWDCLKIN_SET(x) (((x) << TOP_TOP_PWDCLKIN_LSB) & TOP_TOP_PWDCLKIN_MASK)
-#define TOP_TOP_OSCON_MSB 13
-#define TOP_TOP_OSCON_LSB 13
-#define TOP_TOP_OSCON_MASK 0x00002000
-#define TOP_TOP_OSCON_GET(x) (((x) & TOP_TOP_OSCON_MASK) >> TOP_TOP_OSCON_LSB)
-#define TOP_TOP_OSCON_SET(x) (((x) << TOP_TOP_OSCON_LSB) & TOP_TOP_OSCON_MASK)
-#define TOP_TOP_SCLKEN_FORCE_MSB 12
-#define TOP_TOP_SCLKEN_FORCE_LSB 12
-#define TOP_TOP_SCLKEN_FORCE_MASK 0x00001000
-#define TOP_TOP_SCLKEN_FORCE_GET(x) (((x) & TOP_TOP_SCLKEN_FORCE_MASK) >> TOP_TOP_SCLKEN_FORCE_LSB)
-#define TOP_TOP_SCLKEN_FORCE_SET(x) (((x) << TOP_TOP_SCLKEN_FORCE_LSB) & TOP_TOP_SCLKEN_FORCE_MASK)
-#define TOP_TOP_SYNTHON_FORCE_MSB 11
-#define TOP_TOP_SYNTHON_FORCE_LSB 11
-#define TOP_TOP_SYNTHON_FORCE_MASK 0x00000800
-#define TOP_TOP_SYNTHON_FORCE_GET(x) (((x) & TOP_TOP_SYNTHON_FORCE_MASK) >> TOP_TOP_SYNTHON_FORCE_LSB)
-#define TOP_TOP_SYNTHON_FORCE_SET(x) (((x) << TOP_TOP_SYNTHON_FORCE_LSB) & TOP_TOP_SYNTHON_FORCE_MASK)
-#define TOP_TOP_PDBIAS_MSB 10
-#define TOP_TOP_PDBIAS_LSB 10
-#define TOP_TOP_PDBIAS_MASK 0x00000400
-#define TOP_TOP_PDBIAS_GET(x) (((x) & TOP_TOP_PDBIAS_MASK) >> TOP_TOP_PDBIAS_LSB)
-#define TOP_TOP_PDBIAS_SET(x) (((x) << TOP_TOP_PDBIAS_LSB) & TOP_TOP_PDBIAS_MASK)
-#define TOP_TOP_DATAOUTSEL_MSB 9
-#define TOP_TOP_DATAOUTSEL_LSB 8
-#define TOP_TOP_DATAOUTSEL_MASK 0x00000300
-#define TOP_TOP_DATAOUTSEL_GET(x) (((x) & TOP_TOP_DATAOUTSEL_MASK) >> TOP_TOP_DATAOUTSEL_LSB)
-#define TOP_TOP_DATAOUTSEL_SET(x) (((x) << TOP_TOP_DATAOUTSEL_LSB) & TOP_TOP_DATAOUTSEL_MASK)
-#define TOP_TOP_REVID_MSB 7
-#define TOP_TOP_REVID_LSB 5
-#define TOP_TOP_REVID_MASK 0x000000e0
-#define TOP_TOP_REVID_GET(x) (((x) & TOP_TOP_REVID_MASK) >> TOP_TOP_REVID_LSB)
-#define TOP_TOP_REVID_SET(x) (((x) << TOP_TOP_REVID_LSB) & TOP_TOP_REVID_MASK)
-#define TOP_TOP_INT2PAD_MSB 4
-#define TOP_TOP_INT2PAD_LSB 4
-#define TOP_TOP_INT2PAD_MASK 0x00000010
-#define TOP_TOP_INT2PAD_GET(x) (((x) & TOP_TOP_INT2PAD_MASK) >> TOP_TOP_INT2PAD_LSB)
-#define TOP_TOP_INT2PAD_SET(x) (((x) << TOP_TOP_INT2PAD_LSB) & TOP_TOP_INT2PAD_MASK)
-#define TOP_TOP_INTH2PAD_MSB 3
-#define TOP_TOP_INTH2PAD_LSB 3
-#define TOP_TOP_INTH2PAD_MASK 0x00000008
-#define TOP_TOP_INTH2PAD_GET(x) (((x) & TOP_TOP_INTH2PAD_MASK) >> TOP_TOP_INTH2PAD_LSB)
-#define TOP_TOP_INTH2PAD_SET(x) (((x) << TOP_TOP_INTH2PAD_LSB) & TOP_TOP_INTH2PAD_MASK)
-#define TOP_TOP_PAD2GND_MSB 2
-#define TOP_TOP_PAD2GND_LSB 2
-#define TOP_TOP_PAD2GND_MASK 0x00000004
-#define TOP_TOP_PAD2GND_GET(x) (((x) & TOP_TOP_PAD2GND_MASK) >> TOP_TOP_PAD2GND_LSB)
-#define TOP_TOP_PAD2GND_SET(x) (((x) << TOP_TOP_PAD2GND_LSB) & TOP_TOP_PAD2GND_MASK)
-#define TOP_TOP_INT2GND_MSB 1
-#define TOP_TOP_INT2GND_LSB 1
-#define TOP_TOP_INT2GND_MASK 0x00000002
-#define TOP_TOP_INT2GND_GET(x) (((x) & TOP_TOP_INT2GND_MASK) >> TOP_TOP_INT2GND_LSB)
-#define TOP_TOP_INT2GND_SET(x) (((x) << TOP_TOP_INT2GND_LSB) & TOP_TOP_INT2GND_MASK)
-#define TOP_TOP_FORCE_XPAON_MSB 0
-#define TOP_TOP_FORCE_XPAON_LSB 0
-#define TOP_TOP_FORCE_XPAON_MASK 0x00000001
-#define TOP_TOP_FORCE_XPAON_GET(x) (((x) & TOP_TOP_FORCE_XPAON_MASK) >> TOP_TOP_FORCE_XPAON_LSB)
-#define TOP_TOP_FORCE_XPAON_SET(x) (((x) << TOP_TOP_FORCE_XPAON_LSB) & TOP_TOP_FORCE_XPAON_MASK)
-
-#define BIAS_BIAS_SEL_ADDRESS 0x00000038
-#define BIAS_BIAS_SEL_OFFSET 0x00000038
-#define BIAS_BIAS_SEL_PADON_MSB 31
-#define BIAS_BIAS_SEL_PADON_LSB 31
-#define BIAS_BIAS_SEL_PADON_MASK 0x80000000
-#define BIAS_BIAS_SEL_PADON_GET(x) (((x) & BIAS_BIAS_SEL_PADON_MASK) >> BIAS_BIAS_SEL_PADON_LSB)
-#define BIAS_BIAS_SEL_PADON_SET(x) (((x) << BIAS_BIAS_SEL_PADON_LSB) & BIAS_BIAS_SEL_PADON_MASK)
-#define BIAS_BIAS_SEL_SEL_BIAS_MSB 30
-#define BIAS_BIAS_SEL_SEL_BIAS_LSB 25
-#define BIAS_BIAS_SEL_SEL_BIAS_MASK 0x7e000000
-#define BIAS_BIAS_SEL_SEL_BIAS_GET(x) (((x) & BIAS_BIAS_SEL_SEL_BIAS_MASK) >> BIAS_BIAS_SEL_SEL_BIAS_LSB)
-#define BIAS_BIAS_SEL_SEL_BIAS_SET(x) (((x) << BIAS_BIAS_SEL_SEL_BIAS_LSB) & BIAS_BIAS_SEL_SEL_BIAS_MASK)
-#define BIAS_BIAS_SEL_SEL_SPARE_MSB 24
-#define BIAS_BIAS_SEL_SEL_SPARE_LSB 21
-#define BIAS_BIAS_SEL_SEL_SPARE_MASK 0x01e00000
-#define BIAS_BIAS_SEL_SEL_SPARE_GET(x) (((x) & BIAS_BIAS_SEL_SEL_SPARE_MASK) >> BIAS_BIAS_SEL_SEL_SPARE_LSB)
-#define BIAS_BIAS_SEL_SEL_SPARE_SET(x) (((x) << BIAS_BIAS_SEL_SEL_SPARE_LSB) & BIAS_BIAS_SEL_SEL_SPARE_MASK)
-#define BIAS_BIAS_SEL_SPARE_MSB 20
-#define BIAS_BIAS_SEL_SPARE_LSB 20
-#define BIAS_BIAS_SEL_SPARE_MASK 0x00100000
-#define BIAS_BIAS_SEL_SPARE_GET(x) (((x) & BIAS_BIAS_SEL_SPARE_MASK) >> BIAS_BIAS_SEL_SPARE_LSB)
-#define BIAS_BIAS_SEL_SPARE_SET(x) (((x) << BIAS_BIAS_SEL_SPARE_LSB) & BIAS_BIAS_SEL_SPARE_MASK)
-#define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_MSB 19
-#define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_LSB 17
-#define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_MASK 0x000e0000
-#define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_MASK) >> BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_LSB)
-#define BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_LSB) & BIAS_BIAS_SEL_PWD_ICREFBUFBIAS12P5_MASK)
-#define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_MSB 16
-#define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_LSB 16
-#define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_MASK 0x00010000
-#define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_GET(x) (((x) & BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_MASK) >> BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_LSB)
-#define BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_SET(x) (((x) << BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_LSB) & BIAS_BIAS_SEL_PWD_IRDACREGREF12P5_MASK)
-#define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_MSB 15
-#define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_LSB 15
-#define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_MASK 0x00008000
-#define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_GET(x) (((x) & BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_MASK) >> BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_LSB)
-#define BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_SET(x) (((x) << BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_LSB) & BIAS_BIAS_SEL_PWD_IRREFMASTERBIAS12P5_MASK)
-#define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_MSB 14
-#define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_LSB 14
-#define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_MASK 0x00004000
-#define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_MASK) >> BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_LSB)
-#define BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_LSB) & BIAS_BIAS_SEL_PWD_ICREFOPAMPBIAS25_MASK)
-#define BIAS_BIAS_SEL_PWD_ICCPLL25_MSB 13
-#define BIAS_BIAS_SEL_PWD_ICCPLL25_LSB 13
-#define BIAS_BIAS_SEL_PWD_ICCPLL25_MASK 0x00002000
-#define BIAS_BIAS_SEL_PWD_ICCPLL25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICCPLL25_MASK) >> BIAS_BIAS_SEL_PWD_ICCPLL25_LSB)
-#define BIAS_BIAS_SEL_PWD_ICCPLL25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICCPLL25_LSB) & BIAS_BIAS_SEL_PWD_ICCPLL25_MASK)
-#define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_MSB 12
-#define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_LSB 10
-#define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_MASK 0x00001c00
-#define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_MASK) >> BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_LSB)
-#define BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_LSB) & BIAS_BIAS_SEL_PWD_ICCOMPBIAS25_MASK)
-#define BIAS_BIAS_SEL_PWD_ICXTAL25_MSB 9
-#define BIAS_BIAS_SEL_PWD_ICXTAL25_LSB 7
-#define BIAS_BIAS_SEL_PWD_ICXTAL25_MASK 0x00000380
-#define BIAS_BIAS_SEL_PWD_ICXTAL25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICXTAL25_MASK) >> BIAS_BIAS_SEL_PWD_ICXTAL25_LSB)
-#define BIAS_BIAS_SEL_PWD_ICXTAL25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICXTAL25_LSB) & BIAS_BIAS_SEL_PWD_ICXTAL25_MASK)
-#define BIAS_BIAS_SEL_PWD_ICTSENS25_MSB 6
-#define BIAS_BIAS_SEL_PWD_ICTSENS25_LSB 4
-#define BIAS_BIAS_SEL_PWD_ICTSENS25_MASK 0x00000070
-#define BIAS_BIAS_SEL_PWD_ICTSENS25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICTSENS25_MASK) >> BIAS_BIAS_SEL_PWD_ICTSENS25_LSB)
-#define BIAS_BIAS_SEL_PWD_ICTSENS25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICTSENS25_LSB) & BIAS_BIAS_SEL_PWD_ICTSENS25_MASK)
-#define BIAS_BIAS_SEL_PWD_ICTXPC25_MSB 3
-#define BIAS_BIAS_SEL_PWD_ICTXPC25_LSB 1
-#define BIAS_BIAS_SEL_PWD_ICTXPC25_MASK 0x0000000e
-#define BIAS_BIAS_SEL_PWD_ICTXPC25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICTXPC25_MASK) >> BIAS_BIAS_SEL_PWD_ICTXPC25_LSB)
-#define BIAS_BIAS_SEL_PWD_ICTXPC25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICTXPC25_LSB) & BIAS_BIAS_SEL_PWD_ICTXPC25_MASK)
-#define BIAS_BIAS_SEL_PWD_ICLDO25_MSB 0
-#define BIAS_BIAS_SEL_PWD_ICLDO25_LSB 0
-#define BIAS_BIAS_SEL_PWD_ICLDO25_MASK 0x00000001
-#define BIAS_BIAS_SEL_PWD_ICLDO25_GET(x) (((x) & BIAS_BIAS_SEL_PWD_ICLDO25_MASK) >> BIAS_BIAS_SEL_PWD_ICLDO25_LSB)
-#define BIAS_BIAS_SEL_PWD_ICLDO25_SET(x) (((x) << BIAS_BIAS_SEL_PWD_ICLDO25_LSB) & BIAS_BIAS_SEL_PWD_ICLDO25_MASK)
-
-#define BIAS_BIAS1_ADDRESS 0x0000003c
-#define BIAS_BIAS1_OFFSET 0x0000003c
-#define BIAS_BIAS1_PWD_ICDAC2BB25_MSB 31
-#define BIAS_BIAS1_PWD_ICDAC2BB25_LSB 29
-#define BIAS_BIAS1_PWD_ICDAC2BB25_MASK 0xe0000000
-#define BIAS_BIAS1_PWD_ICDAC2BB25_GET(x) (((x) & BIAS_BIAS1_PWD_ICDAC2BB25_MASK) >> BIAS_BIAS1_PWD_ICDAC2BB25_LSB)
-#define BIAS_BIAS1_PWD_ICDAC2BB25_SET(x) (((x) << BIAS_BIAS1_PWD_ICDAC2BB25_LSB) & BIAS_BIAS1_PWD_ICDAC2BB25_MASK)
-#define BIAS_BIAS1_PWD_IC2GVGM25_MSB 28
-#define BIAS_BIAS1_PWD_IC2GVGM25_LSB 26
-#define BIAS_BIAS1_PWD_IC2GVGM25_MASK 0x1c000000
-#define BIAS_BIAS1_PWD_IC2GVGM25_GET(x) (((x) & BIAS_BIAS1_PWD_IC2GVGM25_MASK) >> BIAS_BIAS1_PWD_IC2GVGM25_LSB)
-#define BIAS_BIAS1_PWD_IC2GVGM25_SET(x) (((x) << BIAS_BIAS1_PWD_IC2GVGM25_LSB) & BIAS_BIAS1_PWD_IC2GVGM25_MASK)
-#define BIAS_BIAS1_PWD_IC2GRFFE25_MSB 25
-#define BIAS_BIAS1_PWD_IC2GRFFE25_LSB 23
-#define BIAS_BIAS1_PWD_IC2GRFFE25_MASK 0x03800000
-#define BIAS_BIAS1_PWD_IC2GRFFE25_GET(x) (((x) & BIAS_BIAS1_PWD_IC2GRFFE25_MASK) >> BIAS_BIAS1_PWD_IC2GRFFE25_LSB)
-#define BIAS_BIAS1_PWD_IC2GRFFE25_SET(x) (((x) << BIAS_BIAS1_PWD_IC2GRFFE25_LSB) & BIAS_BIAS1_PWD_IC2GRFFE25_MASK)
-#define BIAS_BIAS1_PWD_IC2GLOREG25_MSB 22
-#define BIAS_BIAS1_PWD_IC2GLOREG25_LSB 20
-#define BIAS_BIAS1_PWD_IC2GLOREG25_MASK 0x00700000
-#define BIAS_BIAS1_PWD_IC2GLOREG25_GET(x) (((x) & BIAS_BIAS1_PWD_IC2GLOREG25_MASK) >> BIAS_BIAS1_PWD_IC2GLOREG25_LSB)
-#define BIAS_BIAS1_PWD_IC2GLOREG25_SET(x) (((x) << BIAS_BIAS1_PWD_IC2GLOREG25_LSB) & BIAS_BIAS1_PWD_IC2GLOREG25_MASK)
-#define BIAS_BIAS1_PWD_IC2GLNAREG25_MSB 19
-#define BIAS_BIAS1_PWD_IC2GLNAREG25_LSB 17
-#define BIAS_BIAS1_PWD_IC2GLNAREG25_MASK 0x000e0000
-#define BIAS_BIAS1_PWD_IC2GLNAREG25_GET(x) (((x) & BIAS_BIAS1_PWD_IC2GLNAREG25_MASK) >> BIAS_BIAS1_PWD_IC2GLNAREG25_LSB)
-#define BIAS_BIAS1_PWD_IC2GLNAREG25_SET(x) (((x) << BIAS_BIAS1_PWD_IC2GLNAREG25_LSB) & BIAS_BIAS1_PWD_IC2GLNAREG25_MASK)
-#define BIAS_BIAS1_PWD_ICDETECTORB25_MSB 16
-#define BIAS_BIAS1_PWD_ICDETECTORB25_LSB 16
-#define BIAS_BIAS1_PWD_ICDETECTORB25_MASK 0x00010000
-#define BIAS_BIAS1_PWD_ICDETECTORB25_GET(x) (((x) & BIAS_BIAS1_PWD_ICDETECTORB25_MASK) >> BIAS_BIAS1_PWD_ICDETECTORB25_LSB)
-#define BIAS_BIAS1_PWD_ICDETECTORB25_SET(x) (((x) << BIAS_BIAS1_PWD_ICDETECTORB25_LSB) & BIAS_BIAS1_PWD_ICDETECTORB25_MASK)
-#define BIAS_BIAS1_PWD_ICDETECTORA25_MSB 15
-#define BIAS_BIAS1_PWD_ICDETECTORA25_LSB 15
-#define BIAS_BIAS1_PWD_ICDETECTORA25_MASK 0x00008000
-#define BIAS_BIAS1_PWD_ICDETECTORA25_GET(x) (((x) & BIAS_BIAS1_PWD_ICDETECTORA25_MASK) >> BIAS_BIAS1_PWD_ICDETECTORA25_LSB)
-#define BIAS_BIAS1_PWD_ICDETECTORA25_SET(x) (((x) << BIAS_BIAS1_PWD_ICDETECTORA25_LSB) & BIAS_BIAS1_PWD_ICDETECTORA25_MASK)
-#define BIAS_BIAS1_PWD_IC5GRXRF25_MSB 14
-#define BIAS_BIAS1_PWD_IC5GRXRF25_LSB 14
-#define BIAS_BIAS1_PWD_IC5GRXRF25_MASK 0x00004000
-#define BIAS_BIAS1_PWD_IC5GRXRF25_GET(x) (((x) & BIAS_BIAS1_PWD_IC5GRXRF25_MASK) >> BIAS_BIAS1_PWD_IC5GRXRF25_LSB)
-#define BIAS_BIAS1_PWD_IC5GRXRF25_SET(x) (((x) << BIAS_BIAS1_PWD_IC5GRXRF25_LSB) & BIAS_BIAS1_PWD_IC5GRXRF25_MASK)
-#define BIAS_BIAS1_PWD_IC5GTXPA25_MSB 13
-#define BIAS_BIAS1_PWD_IC5GTXPA25_LSB 11
-#define BIAS_BIAS1_PWD_IC5GTXPA25_MASK 0x00003800
-#define BIAS_BIAS1_PWD_IC5GTXPA25_GET(x) (((x) & BIAS_BIAS1_PWD_IC5GTXPA25_MASK) >> BIAS_BIAS1_PWD_IC5GTXPA25_LSB)
-#define BIAS_BIAS1_PWD_IC5GTXPA25_SET(x) (((x) << BIAS_BIAS1_PWD_IC5GTXPA25_LSB) & BIAS_BIAS1_PWD_IC5GTXPA25_MASK)
-#define BIAS_BIAS1_PWD_IC5GTXBUF25_MSB 10
-#define BIAS_BIAS1_PWD_IC5GTXBUF25_LSB 8
-#define BIAS_BIAS1_PWD_IC5GTXBUF25_MASK 0x00000700
-#define BIAS_BIAS1_PWD_IC5GTXBUF25_GET(x) (((x) & BIAS_BIAS1_PWD_IC5GTXBUF25_MASK) >> BIAS_BIAS1_PWD_IC5GTXBUF25_LSB)
-#define BIAS_BIAS1_PWD_IC5GTXBUF25_SET(x) (((x) << BIAS_BIAS1_PWD_IC5GTXBUF25_LSB) & BIAS_BIAS1_PWD_IC5GTXBUF25_MASK)
-#define BIAS_BIAS1_PWD_IC5GQB25_MSB 7
-#define BIAS_BIAS1_PWD_IC5GQB25_LSB 5
-#define BIAS_BIAS1_PWD_IC5GQB25_MASK 0x000000e0
-#define BIAS_BIAS1_PWD_IC5GQB25_GET(x) (((x) & BIAS_BIAS1_PWD_IC5GQB25_MASK) >> BIAS_BIAS1_PWD_IC5GQB25_LSB)
-#define BIAS_BIAS1_PWD_IC5GQB25_SET(x) (((x) << BIAS_BIAS1_PWD_IC5GQB25_LSB) & BIAS_BIAS1_PWD_IC5GQB25_MASK)
-#define BIAS_BIAS1_PWD_IC5GMIXQ25_MSB 4
-#define BIAS_BIAS1_PWD_IC5GMIXQ25_LSB 2
-#define BIAS_BIAS1_PWD_IC5GMIXQ25_MASK 0x0000001c
-#define BIAS_BIAS1_PWD_IC5GMIXQ25_GET(x) (((x) & BIAS_BIAS1_PWD_IC5GMIXQ25_MASK) >> BIAS_BIAS1_PWD_IC5GMIXQ25_LSB)
-#define BIAS_BIAS1_PWD_IC5GMIXQ25_SET(x) (((x) << BIAS_BIAS1_PWD_IC5GMIXQ25_LSB) & BIAS_BIAS1_PWD_IC5GMIXQ25_MASK)
-#define BIAS_BIAS1_SPARE_MSB 1
-#define BIAS_BIAS1_SPARE_LSB 0
-#define BIAS_BIAS1_SPARE_MASK 0x00000003
-#define BIAS_BIAS1_SPARE_GET(x) (((x) & BIAS_BIAS1_SPARE_MASK) >> BIAS_BIAS1_SPARE_LSB)
-#define BIAS_BIAS1_SPARE_SET(x) (((x) << BIAS_BIAS1_SPARE_LSB) & BIAS_BIAS1_SPARE_MASK)
-
-#define BIAS_BIAS2_ADDRESS 0x00000040
-#define BIAS_BIAS2_OFFSET 0x00000040
-#define BIAS_BIAS2_PWD_IC5GMIXI25_MSB 31
-#define BIAS_BIAS2_PWD_IC5GMIXI25_LSB 29
-#define BIAS_BIAS2_PWD_IC5GMIXI25_MASK 0xe0000000
-#define BIAS_BIAS2_PWD_IC5GMIXI25_GET(x) (((x) & BIAS_BIAS2_PWD_IC5GMIXI25_MASK) >> BIAS_BIAS2_PWD_IC5GMIXI25_LSB)
-#define BIAS_BIAS2_PWD_IC5GMIXI25_SET(x) (((x) << BIAS_BIAS2_PWD_IC5GMIXI25_LSB) & BIAS_BIAS2_PWD_IC5GMIXI25_MASK)
-#define BIAS_BIAS2_PWD_IC5GDIV25_MSB 28
-#define BIAS_BIAS2_PWD_IC5GDIV25_LSB 26
-#define BIAS_BIAS2_PWD_IC5GDIV25_MASK 0x1c000000
-#define BIAS_BIAS2_PWD_IC5GDIV25_GET(x) (((x) & BIAS_BIAS2_PWD_IC5GDIV25_MASK) >> BIAS_BIAS2_PWD_IC5GDIV25_LSB)
-#define BIAS_BIAS2_PWD_IC5GDIV25_SET(x) (((x) << BIAS_BIAS2_PWD_IC5GDIV25_LSB) & BIAS_BIAS2_PWD_IC5GDIV25_MASK)
-#define BIAS_BIAS2_PWD_IC5GLOREG25_MSB 25
-#define BIAS_BIAS2_PWD_IC5GLOREG25_LSB 23
-#define BIAS_BIAS2_PWD_IC5GLOREG25_MASK 0x03800000
-#define BIAS_BIAS2_PWD_IC5GLOREG25_GET(x) (((x) & BIAS_BIAS2_PWD_IC5GLOREG25_MASK) >> BIAS_BIAS2_PWD_IC5GLOREG25_LSB)
-#define BIAS_BIAS2_PWD_IC5GLOREG25_SET(x) (((x) << BIAS_BIAS2_PWD_IC5GLOREG25_LSB) & BIAS_BIAS2_PWD_IC5GLOREG25_MASK)
-#define BIAS_BIAS2_PWD_IRPLL25_MSB 22
-#define BIAS_BIAS2_PWD_IRPLL25_LSB 22
-#define BIAS_BIAS2_PWD_IRPLL25_MASK 0x00400000
-#define BIAS_BIAS2_PWD_IRPLL25_GET(x) (((x) & BIAS_BIAS2_PWD_IRPLL25_MASK) >> BIAS_BIAS2_PWD_IRPLL25_LSB)
-#define BIAS_BIAS2_PWD_IRPLL25_SET(x) (((x) << BIAS_BIAS2_PWD_IRPLL25_LSB) & BIAS_BIAS2_PWD_IRPLL25_MASK)
-#define BIAS_BIAS2_PWD_IRXTAL25_MSB 21
-#define BIAS_BIAS2_PWD_IRXTAL25_LSB 19
-#define BIAS_BIAS2_PWD_IRXTAL25_MASK 0x00380000
-#define BIAS_BIAS2_PWD_IRXTAL25_GET(x) (((x) & BIAS_BIAS2_PWD_IRXTAL25_MASK) >> BIAS_BIAS2_PWD_IRXTAL25_LSB)
-#define BIAS_BIAS2_PWD_IRXTAL25_SET(x) (((x) << BIAS_BIAS2_PWD_IRXTAL25_LSB) & BIAS_BIAS2_PWD_IRXTAL25_MASK)
-#define BIAS_BIAS2_PWD_IRTSENS25_MSB 18
-#define BIAS_BIAS2_PWD_IRTSENS25_LSB 16
-#define BIAS_BIAS2_PWD_IRTSENS25_MASK 0x00070000
-#define BIAS_BIAS2_PWD_IRTSENS25_GET(x) (((x) & BIAS_BIAS2_PWD_IRTSENS25_MASK) >> BIAS_BIAS2_PWD_IRTSENS25_LSB)
-#define BIAS_BIAS2_PWD_IRTSENS25_SET(x) (((x) << BIAS_BIAS2_PWD_IRTSENS25_LSB) & BIAS_BIAS2_PWD_IRTSENS25_MASK)
-#define BIAS_BIAS2_PWD_IRTXPC25_MSB 15
-#define BIAS_BIAS2_PWD_IRTXPC25_LSB 13
-#define BIAS_BIAS2_PWD_IRTXPC25_MASK 0x0000e000
-#define BIAS_BIAS2_PWD_IRTXPC25_GET(x) (((x) & BIAS_BIAS2_PWD_IRTXPC25_MASK) >> BIAS_BIAS2_PWD_IRTXPC25_LSB)
-#define BIAS_BIAS2_PWD_IRTXPC25_SET(x) (((x) << BIAS_BIAS2_PWD_IRTXPC25_LSB) & BIAS_BIAS2_PWD_IRTXPC25_MASK)
-#define BIAS_BIAS2_PWD_IRLDO25_MSB 12
-#define BIAS_BIAS2_PWD_IRLDO25_LSB 12
-#define BIAS_BIAS2_PWD_IRLDO25_MASK 0x00001000
-#define BIAS_BIAS2_PWD_IRLDO25_GET(x) (((x) & BIAS_BIAS2_PWD_IRLDO25_MASK) >> BIAS_BIAS2_PWD_IRLDO25_LSB)
-#define BIAS_BIAS2_PWD_IRLDO25_SET(x) (((x) << BIAS_BIAS2_PWD_IRLDO25_LSB) & BIAS_BIAS2_PWD_IRLDO25_MASK)
-#define BIAS_BIAS2_PWD_IR2GTXMIX25_MSB 11
-#define BIAS_BIAS2_PWD_IR2GTXMIX25_LSB 9
-#define BIAS_BIAS2_PWD_IR2GTXMIX25_MASK 0x00000e00
-#define BIAS_BIAS2_PWD_IR2GTXMIX25_GET(x) (((x) & BIAS_BIAS2_PWD_IR2GTXMIX25_MASK) >> BIAS_BIAS2_PWD_IR2GTXMIX25_LSB)
-#define BIAS_BIAS2_PWD_IR2GTXMIX25_SET(x) (((x) << BIAS_BIAS2_PWD_IR2GTXMIX25_LSB) & BIAS_BIAS2_PWD_IR2GTXMIX25_MASK)
-#define BIAS_BIAS2_PWD_IR2GLOREG25_MSB 8
-#define BIAS_BIAS2_PWD_IR2GLOREG25_LSB 6
-#define BIAS_BIAS2_PWD_IR2GLOREG25_MASK 0x000001c0
-#define BIAS_BIAS2_PWD_IR2GLOREG25_GET(x) (((x) & BIAS_BIAS2_PWD_IR2GLOREG25_MASK) >> BIAS_BIAS2_PWD_IR2GLOREG25_LSB)
-#define BIAS_BIAS2_PWD_IR2GLOREG25_SET(x) (((x) << BIAS_BIAS2_PWD_IR2GLOREG25_LSB) & BIAS_BIAS2_PWD_IR2GLOREG25_MASK)
-#define BIAS_BIAS2_PWD_IR2GLNAREG25_MSB 5
-#define BIAS_BIAS2_PWD_IR2GLNAREG25_LSB 3
-#define BIAS_BIAS2_PWD_IR2GLNAREG25_MASK 0x00000038
-#define BIAS_BIAS2_PWD_IR2GLNAREG25_GET(x) (((x) & BIAS_BIAS2_PWD_IR2GLNAREG25_MASK) >> BIAS_BIAS2_PWD_IR2GLNAREG25_LSB)
-#define BIAS_BIAS2_PWD_IR2GLNAREG25_SET(x) (((x) << BIAS_BIAS2_PWD_IR2GLNAREG25_LSB) & BIAS_BIAS2_PWD_IR2GLNAREG25_MASK)
-#define BIAS_BIAS2_PWD_IR5GRFVREF2525_MSB 2
-#define BIAS_BIAS2_PWD_IR5GRFVREF2525_LSB 0
-#define BIAS_BIAS2_PWD_IR5GRFVREF2525_MASK 0x00000007
-#define BIAS_BIAS2_PWD_IR5GRFVREF2525_GET(x) (((x) & BIAS_BIAS2_PWD_IR5GRFVREF2525_MASK) >> BIAS_BIAS2_PWD_IR5GRFVREF2525_LSB)
-#define BIAS_BIAS2_PWD_IR5GRFVREF2525_SET(x) (((x) << BIAS_BIAS2_PWD_IR5GRFVREF2525_LSB) & BIAS_BIAS2_PWD_IR5GRFVREF2525_MASK)
-
-#define BIAS_BIAS3_ADDRESS 0x00000044
-#define BIAS_BIAS3_OFFSET 0x00000044
-#define BIAS_BIAS3_PWD_IR5GTXMIX25_MSB 31
-#define BIAS_BIAS3_PWD_IR5GTXMIX25_LSB 29
-#define BIAS_BIAS3_PWD_IR5GTXMIX25_MASK 0xe0000000
-#define BIAS_BIAS3_PWD_IR5GTXMIX25_GET(x) (((x) & BIAS_BIAS3_PWD_IR5GTXMIX25_MASK) >> BIAS_BIAS3_PWD_IR5GTXMIX25_LSB)
-#define BIAS_BIAS3_PWD_IR5GTXMIX25_SET(x) (((x) << BIAS_BIAS3_PWD_IR5GTXMIX25_LSB) & BIAS_BIAS3_PWD_IR5GTXMIX25_MASK)
-#define BIAS_BIAS3_PWD_IR5GAGC25_MSB 28
-#define BIAS_BIAS3_PWD_IR5GAGC25_LSB 26
-#define BIAS_BIAS3_PWD_IR5GAGC25_MASK 0x1c000000
-#define BIAS_BIAS3_PWD_IR5GAGC25_GET(x) (((x) & BIAS_BIAS3_PWD_IR5GAGC25_MASK) >> BIAS_BIAS3_PWD_IR5GAGC25_LSB)
-#define BIAS_BIAS3_PWD_IR5GAGC25_SET(x) (((x) << BIAS_BIAS3_PWD_IR5GAGC25_LSB) & BIAS_BIAS3_PWD_IR5GAGC25_MASK)
-#define BIAS_BIAS3_PWD_ICDAC50_MSB 25
-#define BIAS_BIAS3_PWD_ICDAC50_LSB 23
-#define BIAS_BIAS3_PWD_ICDAC50_MASK 0x03800000
-#define BIAS_BIAS3_PWD_ICDAC50_GET(x) (((x) & BIAS_BIAS3_PWD_ICDAC50_MASK) >> BIAS_BIAS3_PWD_ICDAC50_LSB)
-#define BIAS_BIAS3_PWD_ICDAC50_SET(x) (((x) << BIAS_BIAS3_PWD_ICDAC50_LSB) & BIAS_BIAS3_PWD_ICDAC50_MASK)
-#define BIAS_BIAS3_PWD_ICSYNTH50_MSB 22
-#define BIAS_BIAS3_PWD_ICSYNTH50_LSB 22
-#define BIAS_BIAS3_PWD_ICSYNTH50_MASK 0x00400000
-#define BIAS_BIAS3_PWD_ICSYNTH50_GET(x) (((x) & BIAS_BIAS3_PWD_ICSYNTH50_MASK) >> BIAS_BIAS3_PWD_ICSYNTH50_LSB)
-#define BIAS_BIAS3_PWD_ICSYNTH50_SET(x) (((x) << BIAS_BIAS3_PWD_ICSYNTH50_LSB) & BIAS_BIAS3_PWD_ICSYNTH50_MASK)
-#define BIAS_BIAS3_PWD_ICBB50_MSB 21
-#define BIAS_BIAS3_PWD_ICBB50_LSB 21
-#define BIAS_BIAS3_PWD_ICBB50_MASK 0x00200000
-#define BIAS_BIAS3_PWD_ICBB50_GET(x) (((x) & BIAS_BIAS3_PWD_ICBB50_MASK) >> BIAS_BIAS3_PWD_ICBB50_LSB)
-#define BIAS_BIAS3_PWD_ICBB50_SET(x) (((x) << BIAS_BIAS3_PWD_ICBB50_LSB) & BIAS_BIAS3_PWD_ICBB50_MASK)
-#define BIAS_BIAS3_PWD_IC2GDIV50_MSB 20
-#define BIAS_BIAS3_PWD_IC2GDIV50_LSB 18
-#define BIAS_BIAS3_PWD_IC2GDIV50_MASK 0x001c0000
-#define BIAS_BIAS3_PWD_IC2GDIV50_GET(x) (((x) & BIAS_BIAS3_PWD_IC2GDIV50_MASK) >> BIAS_BIAS3_PWD_IC2GDIV50_LSB)
-#define BIAS_BIAS3_PWD_IC2GDIV50_SET(x) (((x) << BIAS_BIAS3_PWD_IC2GDIV50_LSB) & BIAS_BIAS3_PWD_IC2GDIV50_MASK)
-#define BIAS_BIAS3_PWD_IRSYNTH50_MSB 17
-#define BIAS_BIAS3_PWD_IRSYNTH50_LSB 17
-#define BIAS_BIAS3_PWD_IRSYNTH50_MASK 0x00020000
-#define BIAS_BIAS3_PWD_IRSYNTH50_GET(x) (((x) & BIAS_BIAS3_PWD_IRSYNTH50_MASK) >> BIAS_BIAS3_PWD_IRSYNTH50_LSB)
-#define BIAS_BIAS3_PWD_IRSYNTH50_SET(x) (((x) << BIAS_BIAS3_PWD_IRSYNTH50_LSB) & BIAS_BIAS3_PWD_IRSYNTH50_MASK)
-#define BIAS_BIAS3_PWD_IRBB50_MSB 16
-#define BIAS_BIAS3_PWD_IRBB50_LSB 16
-#define BIAS_BIAS3_PWD_IRBB50_MASK 0x00010000
-#define BIAS_BIAS3_PWD_IRBB50_GET(x) (((x) & BIAS_BIAS3_PWD_IRBB50_MASK) >> BIAS_BIAS3_PWD_IRBB50_LSB)
-#define BIAS_BIAS3_PWD_IRBB50_SET(x) (((x) << BIAS_BIAS3_PWD_IRBB50_LSB) & BIAS_BIAS3_PWD_IRBB50_MASK)
-#define BIAS_BIAS3_PWD_IC25SPARE1_MSB 15
-#define BIAS_BIAS3_PWD_IC25SPARE1_LSB 13
-#define BIAS_BIAS3_PWD_IC25SPARE1_MASK 0x0000e000
-#define BIAS_BIAS3_PWD_IC25SPARE1_GET(x) (((x) & BIAS_BIAS3_PWD_IC25SPARE1_MASK) >> BIAS_BIAS3_PWD_IC25SPARE1_LSB)
-#define BIAS_BIAS3_PWD_IC25SPARE1_SET(x) (((x) << BIAS_BIAS3_PWD_IC25SPARE1_LSB) & BIAS_BIAS3_PWD_IC25SPARE1_MASK)
-#define BIAS_BIAS3_PWD_IC25SPARE2_MSB 12
-#define BIAS_BIAS3_PWD_IC25SPARE2_LSB 10
-#define BIAS_BIAS3_PWD_IC25SPARE2_MASK 0x00001c00
-#define BIAS_BIAS3_PWD_IC25SPARE2_GET(x) (((x) & BIAS_BIAS3_PWD_IC25SPARE2_MASK) >> BIAS_BIAS3_PWD_IC25SPARE2_LSB)
-#define BIAS_BIAS3_PWD_IC25SPARE2_SET(x) (((x) << BIAS_BIAS3_PWD_IC25SPARE2_LSB) & BIAS_BIAS3_PWD_IC25SPARE2_MASK)
-#define BIAS_BIAS3_PWD_IR25SPARE1_MSB 9
-#define BIAS_BIAS3_PWD_IR25SPARE1_LSB 7
-#define BIAS_BIAS3_PWD_IR25SPARE1_MASK 0x00000380
-#define BIAS_BIAS3_PWD_IR25SPARE1_GET(x) (((x) & BIAS_BIAS3_PWD_IR25SPARE1_MASK) >> BIAS_BIAS3_PWD_IR25SPARE1_LSB)
-#define BIAS_BIAS3_PWD_IR25SPARE1_SET(x) (((x) << BIAS_BIAS3_PWD_IR25SPARE1_LSB) & BIAS_BIAS3_PWD_IR25SPARE1_MASK)
-#define BIAS_BIAS3_PWD_IR25SPARE2_MSB 6
-#define BIAS_BIAS3_PWD_IR25SPARE2_LSB 4
-#define BIAS_BIAS3_PWD_IR25SPARE2_MASK 0x00000070
-#define BIAS_BIAS3_PWD_IR25SPARE2_GET(x) (((x) & BIAS_BIAS3_PWD_IR25SPARE2_MASK) >> BIAS_BIAS3_PWD_IR25SPARE2_LSB)
-#define BIAS_BIAS3_PWD_IR25SPARE2_SET(x) (((x) << BIAS_BIAS3_PWD_IR25SPARE2_LSB) & BIAS_BIAS3_PWD_IR25SPARE2_MASK)
-#define BIAS_BIAS3_PWD_ICDACREG12P5_MSB 3
-#define BIAS_BIAS3_PWD_ICDACREG12P5_LSB 1
-#define BIAS_BIAS3_PWD_ICDACREG12P5_MASK 0x0000000e
-#define BIAS_BIAS3_PWD_ICDACREG12P5_GET(x) (((x) & BIAS_BIAS3_PWD_ICDACREG12P5_MASK) >> BIAS_BIAS3_PWD_ICDACREG12P5_LSB)
-#define BIAS_BIAS3_PWD_ICDACREG12P5_SET(x) (((x) << BIAS_BIAS3_PWD_ICDACREG12P5_LSB) & BIAS_BIAS3_PWD_ICDACREG12P5_MASK)
-#define BIAS_BIAS3_SPARE_MSB 0
-#define BIAS_BIAS3_SPARE_LSB 0
-#define BIAS_BIAS3_SPARE_MASK 0x00000001
-#define BIAS_BIAS3_SPARE_GET(x) (((x) & BIAS_BIAS3_SPARE_MASK) >> BIAS_BIAS3_SPARE_LSB)
-#define BIAS_BIAS3_SPARE_SET(x) (((x) << BIAS_BIAS3_SPARE_LSB) & BIAS_BIAS3_SPARE_MASK)
-
-#define TXPC_TXPC_ADDRESS 0x00000048
-#define TXPC_TXPC_OFFSET 0x00000048
-#define TXPC_TXPC_SELINTPD_MSB 31
-#define TXPC_TXPC_SELINTPD_LSB 31
-#define TXPC_TXPC_SELINTPD_MASK 0x80000000
-#define TXPC_TXPC_SELINTPD_GET(x) (((x) & TXPC_TXPC_SELINTPD_MASK) >> TXPC_TXPC_SELINTPD_LSB)
-#define TXPC_TXPC_SELINTPD_SET(x) (((x) << TXPC_TXPC_SELINTPD_LSB) & TXPC_TXPC_SELINTPD_MASK)
-#define TXPC_TXPC_TEST_MSB 30
-#define TXPC_TXPC_TEST_LSB 30
-#define TXPC_TXPC_TEST_MASK 0x40000000
-#define TXPC_TXPC_TEST_GET(x) (((x) & TXPC_TXPC_TEST_MASK) >> TXPC_TXPC_TEST_LSB)
-#define TXPC_TXPC_TEST_SET(x) (((x) << TXPC_TXPC_TEST_LSB) & TXPC_TXPC_TEST_MASK)
-#define TXPC_TXPC_TESTGAIN_MSB 29
-#define TXPC_TXPC_TESTGAIN_LSB 28
-#define TXPC_TXPC_TESTGAIN_MASK 0x30000000
-#define TXPC_TXPC_TESTGAIN_GET(x) (((x) & TXPC_TXPC_TESTGAIN_MASK) >> TXPC_TXPC_TESTGAIN_LSB)
-#define TXPC_TXPC_TESTGAIN_SET(x) (((x) << TXPC_TXPC_TESTGAIN_LSB) & TXPC_TXPC_TESTGAIN_MASK)
-#define TXPC_TXPC_TESTDAC_MSB 27
-#define TXPC_TXPC_TESTDAC_LSB 22
-#define TXPC_TXPC_TESTDAC_MASK 0x0fc00000
-#define TXPC_TXPC_TESTDAC_GET(x) (((x) & TXPC_TXPC_TESTDAC_MASK) >> TXPC_TXPC_TESTDAC_LSB)
-#define TXPC_TXPC_TESTDAC_SET(x) (((x) << TXPC_TXPC_TESTDAC_LSB) & TXPC_TXPC_TESTDAC_MASK)
-#define TXPC_TXPC_TESTPWDPC_MSB 21
-#define TXPC_TXPC_TESTPWDPC_LSB 21
-#define TXPC_TXPC_TESTPWDPC_MASK 0x00200000
-#define TXPC_TXPC_TESTPWDPC_GET(x) (((x) & TXPC_TXPC_TESTPWDPC_MASK) >> TXPC_TXPC_TESTPWDPC_LSB)
-#define TXPC_TXPC_TESTPWDPC_SET(x) (((x) << TXPC_TXPC_TESTPWDPC_LSB) & TXPC_TXPC_TESTPWDPC_MASK)
-#define TXPC_TXPC_CURHALF_MSB 20
-#define TXPC_TXPC_CURHALF_LSB 20
-#define TXPC_TXPC_CURHALF_MASK 0x00100000
-#define TXPC_TXPC_CURHALF_GET(x) (((x) & TXPC_TXPC_CURHALF_MASK) >> TXPC_TXPC_CURHALF_LSB)
-#define TXPC_TXPC_CURHALF_SET(x) (((x) << TXPC_TXPC_CURHALF_LSB) & TXPC_TXPC_CURHALF_MASK)
-#define TXPC_TXPC_NEGOUT_MSB 19
-#define TXPC_TXPC_NEGOUT_LSB 19
-#define TXPC_TXPC_NEGOUT_MASK 0x00080000
-#define TXPC_TXPC_NEGOUT_GET(x) (((x) & TXPC_TXPC_NEGOUT_MASK) >> TXPC_TXPC_NEGOUT_LSB)
-#define TXPC_TXPC_NEGOUT_SET(x) (((x) << TXPC_TXPC_NEGOUT_LSB) & TXPC_TXPC_NEGOUT_MASK)
-#define TXPC_TXPC_CLKDELAY_MSB 18
-#define TXPC_TXPC_CLKDELAY_LSB 18
-#define TXPC_TXPC_CLKDELAY_MASK 0x00040000
-#define TXPC_TXPC_CLKDELAY_GET(x) (((x) & TXPC_TXPC_CLKDELAY_MASK) >> TXPC_TXPC_CLKDELAY_LSB)
-#define TXPC_TXPC_CLKDELAY_SET(x) (((x) << TXPC_TXPC_CLKDELAY_LSB) & TXPC_TXPC_CLKDELAY_MASK)
-#define TXPC_TXPC_SELMODREF_MSB 17
-#define TXPC_TXPC_SELMODREF_LSB 17
-#define TXPC_TXPC_SELMODREF_MASK 0x00020000
-#define TXPC_TXPC_SELMODREF_GET(x) (((x) & TXPC_TXPC_SELMODREF_MASK) >> TXPC_TXPC_SELMODREF_LSB)
-#define TXPC_TXPC_SELMODREF_SET(x) (((x) << TXPC_TXPC_SELMODREF_LSB) & TXPC_TXPC_SELMODREF_MASK)
-#define TXPC_TXPC_SELCMOUT_MSB 16
-#define TXPC_TXPC_SELCMOUT_LSB 16
-#define TXPC_TXPC_SELCMOUT_MASK 0x00010000
-#define TXPC_TXPC_SELCMOUT_GET(x) (((x) & TXPC_TXPC_SELCMOUT_MASK) >> TXPC_TXPC_SELCMOUT_LSB)
-#define TXPC_TXPC_SELCMOUT_SET(x) (((x) << TXPC_TXPC_SELCMOUT_LSB) & TXPC_TXPC_SELCMOUT_MASK)
-#define TXPC_TXPC_TSMODE_MSB 15
-#define TXPC_TXPC_TSMODE_LSB 14
-#define TXPC_TXPC_TSMODE_MASK 0x0000c000
-#define TXPC_TXPC_TSMODE_GET(x) (((x) & TXPC_TXPC_TSMODE_MASK) >> TXPC_TXPC_TSMODE_LSB)
-#define TXPC_TXPC_TSMODE_SET(x) (((x) << TXPC_TXPC_TSMODE_LSB) & TXPC_TXPC_TSMODE_MASK)
-#define TXPC_TXPC_N_MSB 13
-#define TXPC_TXPC_N_LSB 6
-#define TXPC_TXPC_N_MASK 0x00003fc0
-#define TXPC_TXPC_N_GET(x) (((x) & TXPC_TXPC_N_MASK) >> TXPC_TXPC_N_LSB)
-#define TXPC_TXPC_N_SET(x) (((x) << TXPC_TXPC_N_LSB) & TXPC_TXPC_N_MASK)
-#define TXPC_TXPC_ON1STSYNTHON_MSB 5
-#define TXPC_TXPC_ON1STSYNTHON_LSB 5
-#define TXPC_TXPC_ON1STSYNTHON_MASK 0x00000020
-#define TXPC_TXPC_ON1STSYNTHON_GET(x) (((x) & TXPC_TXPC_ON1STSYNTHON_MASK) >> TXPC_TXPC_ON1STSYNTHON_LSB)
-#define TXPC_TXPC_ON1STSYNTHON_SET(x) (((x) << TXPC_TXPC_ON1STSYNTHON_LSB) & TXPC_TXPC_ON1STSYNTHON_MASK)
-#define TXPC_TXPC_SELINIT_MSB 4
-#define TXPC_TXPC_SELINIT_LSB 3
-#define TXPC_TXPC_SELINIT_MASK 0x00000018
-#define TXPC_TXPC_SELINIT_GET(x) (((x) & TXPC_TXPC_SELINIT_MASK) >> TXPC_TXPC_SELINIT_LSB)
-#define TXPC_TXPC_SELINIT_SET(x) (((x) << TXPC_TXPC_SELINIT_LSB) & TXPC_TXPC_SELINIT_MASK)
-#define TXPC_TXPC_SELCOUNT_MSB 2
-#define TXPC_TXPC_SELCOUNT_LSB 2
-#define TXPC_TXPC_SELCOUNT_MASK 0x00000004
-#define TXPC_TXPC_SELCOUNT_GET(x) (((x) & TXPC_TXPC_SELCOUNT_MASK) >> TXPC_TXPC_SELCOUNT_LSB)
-#define TXPC_TXPC_SELCOUNT_SET(x) (((x) << TXPC_TXPC_SELCOUNT_LSB) & TXPC_TXPC_SELCOUNT_MASK)
-#define TXPC_TXPC_ATBSEL_MSB 1
-#define TXPC_TXPC_ATBSEL_LSB 0
-#define TXPC_TXPC_ATBSEL_MASK 0x00000003
-#define TXPC_TXPC_ATBSEL_GET(x) (((x) & TXPC_TXPC_ATBSEL_MASK) >> TXPC_TXPC_ATBSEL_LSB)
-#define TXPC_TXPC_ATBSEL_SET(x) (((x) << TXPC_TXPC_ATBSEL_LSB) & TXPC_TXPC_ATBSEL_MASK)
-
-#define TXPC_MISC_ADDRESS 0x0000004c
-#define TXPC_MISC_OFFSET 0x0000004c
-#define TXPC_MISC_FLIPBMODE_MSB 31
-#define TXPC_MISC_FLIPBMODE_LSB 31
-#define TXPC_MISC_FLIPBMODE_MASK 0x80000000
-#define TXPC_MISC_FLIPBMODE_GET(x) (((x) & TXPC_MISC_FLIPBMODE_MASK) >> TXPC_MISC_FLIPBMODE_LSB)
-#define TXPC_MISC_FLIPBMODE_SET(x) (((x) << TXPC_MISC_FLIPBMODE_LSB) & TXPC_MISC_FLIPBMODE_MASK)
-#define TXPC_MISC_LEVEL_MSB 30
-#define TXPC_MISC_LEVEL_LSB 29
-#define TXPC_MISC_LEVEL_MASK 0x60000000
-#define TXPC_MISC_LEVEL_GET(x) (((x) & TXPC_MISC_LEVEL_MASK) >> TXPC_MISC_LEVEL_LSB)
-#define TXPC_MISC_LEVEL_SET(x) (((x) << TXPC_MISC_LEVEL_LSB) & TXPC_MISC_LEVEL_MASK)
-#define TXPC_MISC_LDO_TEST_MODE_MSB 28
-#define TXPC_MISC_LDO_TEST_MODE_LSB 28
-#define TXPC_MISC_LDO_TEST_MODE_MASK 0x10000000
-#define TXPC_MISC_LDO_TEST_MODE_GET(x) (((x) & TXPC_MISC_LDO_TEST_MODE_MASK) >> TXPC_MISC_LDO_TEST_MODE_LSB)
-#define TXPC_MISC_LDO_TEST_MODE_SET(x) (((x) << TXPC_MISC_LDO_TEST_MODE_LSB) & TXPC_MISC_LDO_TEST_MODE_MASK)
-#define TXPC_MISC_NOTCXODET_MSB 27
-#define TXPC_MISC_NOTCXODET_LSB 27
-#define TXPC_MISC_NOTCXODET_MASK 0x08000000
-#define TXPC_MISC_NOTCXODET_GET(x) (((x) & TXPC_MISC_NOTCXODET_MASK) >> TXPC_MISC_NOTCXODET_LSB)
-#define TXPC_MISC_NOTCXODET_SET(x) (((x) << TXPC_MISC_NOTCXODET_LSB) & TXPC_MISC_NOTCXODET_MASK)
-#define TXPC_MISC_PWDCLKIND_MSB 26
-#define TXPC_MISC_PWDCLKIND_LSB 26
-#define TXPC_MISC_PWDCLKIND_MASK 0x04000000
-#define TXPC_MISC_PWDCLKIND_GET(x) (((x) & TXPC_MISC_PWDCLKIND_MASK) >> TXPC_MISC_PWDCLKIND_LSB)
-#define TXPC_MISC_PWDCLKIND_SET(x) (((x) << TXPC_MISC_PWDCLKIND_LSB) & TXPC_MISC_PWDCLKIND_MASK)
-#define TXPC_MISC_PWDXINPAD_MSB 25
-#define TXPC_MISC_PWDXINPAD_LSB 25
-#define TXPC_MISC_PWDXINPAD_MASK 0x02000000
-#define TXPC_MISC_PWDXINPAD_GET(x) (((x) & TXPC_MISC_PWDXINPAD_MASK) >> TXPC_MISC_PWDXINPAD_LSB)
-#define TXPC_MISC_PWDXINPAD_SET(x) (((x) << TXPC_MISC_PWDXINPAD_LSB) & TXPC_MISC_PWDXINPAD_MASK)
-#define TXPC_MISC_LOCALBIAS_MSB 24
-#define TXPC_MISC_LOCALBIAS_LSB 24
-#define TXPC_MISC_LOCALBIAS_MASK 0x01000000
-#define TXPC_MISC_LOCALBIAS_GET(x) (((x) & TXPC_MISC_LOCALBIAS_MASK) >> TXPC_MISC_LOCALBIAS_LSB)
-#define TXPC_MISC_LOCALBIAS_SET(x) (((x) << TXPC_MISC_LOCALBIAS_LSB) & TXPC_MISC_LOCALBIAS_MASK)
-#define TXPC_MISC_LOCALBIAS2X_MSB 23
-#define TXPC_MISC_LOCALBIAS2X_LSB 23
-#define TXPC_MISC_LOCALBIAS2X_MASK 0x00800000
-#define TXPC_MISC_LOCALBIAS2X_GET(x) (((x) & TXPC_MISC_LOCALBIAS2X_MASK) >> TXPC_MISC_LOCALBIAS2X_LSB)
-#define TXPC_MISC_LOCALBIAS2X_SET(x) (((x) << TXPC_MISC_LOCALBIAS2X_LSB) & TXPC_MISC_LOCALBIAS2X_MASK)
-#define TXPC_MISC_SELTSP_MSB 22
-#define TXPC_MISC_SELTSP_LSB 22
-#define TXPC_MISC_SELTSP_MASK 0x00400000
-#define TXPC_MISC_SELTSP_GET(x) (((x) & TXPC_MISC_SELTSP_MASK) >> TXPC_MISC_SELTSP_LSB)
-#define TXPC_MISC_SELTSP_SET(x) (((x) << TXPC_MISC_SELTSP_LSB) & TXPC_MISC_SELTSP_MASK)
-#define TXPC_MISC_SELTSN_MSB 21
-#define TXPC_MISC_SELTSN_LSB 21
-#define TXPC_MISC_SELTSN_MASK 0x00200000
-#define TXPC_MISC_SELTSN_GET(x) (((x) & TXPC_MISC_SELTSN_MASK) >> TXPC_MISC_SELTSN_LSB)
-#define TXPC_MISC_SELTSN_SET(x) (((x) << TXPC_MISC_SELTSN_LSB) & TXPC_MISC_SELTSN_MASK)
-#define TXPC_MISC_SPARE_A_MSB 20
-#define TXPC_MISC_SPARE_A_LSB 18
-#define TXPC_MISC_SPARE_A_MASK 0x001c0000
-#define TXPC_MISC_SPARE_A_GET(x) (((x) & TXPC_MISC_SPARE_A_MASK) >> TXPC_MISC_SPARE_A_LSB)
-#define TXPC_MISC_SPARE_A_SET(x) (((x) << TXPC_MISC_SPARE_A_LSB) & TXPC_MISC_SPARE_A_MASK)
-#define TXPC_MISC_DECOUT_MSB 17
-#define TXPC_MISC_DECOUT_LSB 8
-#define TXPC_MISC_DECOUT_MASK 0x0003ff00
-#define TXPC_MISC_DECOUT_GET(x) (((x) & TXPC_MISC_DECOUT_MASK) >> TXPC_MISC_DECOUT_LSB)
-#define TXPC_MISC_DECOUT_SET(x) (((x) << TXPC_MISC_DECOUT_LSB) & TXPC_MISC_DECOUT_MASK)
-#define TXPC_MISC_XTALDIV_MSB 7
-#define TXPC_MISC_XTALDIV_LSB 6
-#define TXPC_MISC_XTALDIV_MASK 0x000000c0
-#define TXPC_MISC_XTALDIV_GET(x) (((x) & TXPC_MISC_XTALDIV_MASK) >> TXPC_MISC_XTALDIV_LSB)
-#define TXPC_MISC_XTALDIV_SET(x) (((x) << TXPC_MISC_XTALDIV_LSB) & TXPC_MISC_XTALDIV_MASK)
-#define TXPC_MISC_SPARE_MSB 5
-#define TXPC_MISC_SPARE_LSB 0
-#define TXPC_MISC_SPARE_MASK 0x0000003f
-#define TXPC_MISC_SPARE_GET(x) (((x) & TXPC_MISC_SPARE_MASK) >> TXPC_MISC_SPARE_LSB)
-#define TXPC_MISC_SPARE_SET(x) (((x) << TXPC_MISC_SPARE_LSB) & TXPC_MISC_SPARE_MASK)
-
-#define RXTXBB_RXTXBB1_ADDRESS 0x00000050
-#define RXTXBB_RXTXBB1_OFFSET 0x00000050
-#define RXTXBB_RXTXBB1_SPARE_MSB 31
-#define RXTXBB_RXTXBB1_SPARE_LSB 19
-#define RXTXBB_RXTXBB1_SPARE_MASK 0xfff80000
-#define RXTXBB_RXTXBB1_SPARE_GET(x) (((x) & RXTXBB_RXTXBB1_SPARE_MASK) >> RXTXBB_RXTXBB1_SPARE_LSB)
-#define RXTXBB_RXTXBB1_SPARE_SET(x) (((x) << RXTXBB_RXTXBB1_SPARE_LSB) & RXTXBB_RXTXBB1_SPARE_MASK)
-#define RXTXBB_RXTXBB1_FNOTCH_MSB 18
-#define RXTXBB_RXTXBB1_FNOTCH_LSB 17
-#define RXTXBB_RXTXBB1_FNOTCH_MASK 0x00060000
-#define RXTXBB_RXTXBB1_FNOTCH_GET(x) (((x) & RXTXBB_RXTXBB1_FNOTCH_MASK) >> RXTXBB_RXTXBB1_FNOTCH_LSB)
-#define RXTXBB_RXTXBB1_FNOTCH_SET(x) (((x) << RXTXBB_RXTXBB1_FNOTCH_LSB) & RXTXBB_RXTXBB1_FNOTCH_MASK)
-#define RXTXBB_RXTXBB1_SEL_ATB_MSB 16
-#define RXTXBB_RXTXBB1_SEL_ATB_LSB 9
-#define RXTXBB_RXTXBB1_SEL_ATB_MASK 0x0001fe00
-#define RXTXBB_RXTXBB1_SEL_ATB_GET(x) (((x) & RXTXBB_RXTXBB1_SEL_ATB_MASK) >> RXTXBB_RXTXBB1_SEL_ATB_LSB)
-#define RXTXBB_RXTXBB1_SEL_ATB_SET(x) (((x) << RXTXBB_RXTXBB1_SEL_ATB_LSB) & RXTXBB_RXTXBB1_SEL_ATB_MASK)
-#define RXTXBB_RXTXBB1_PDDACINTERFACE_MSB 8
-#define RXTXBB_RXTXBB1_PDDACINTERFACE_LSB 8
-#define RXTXBB_RXTXBB1_PDDACINTERFACE_MASK 0x00000100
-#define RXTXBB_RXTXBB1_PDDACINTERFACE_GET(x) (((x) & RXTXBB_RXTXBB1_PDDACINTERFACE_MASK) >> RXTXBB_RXTXBB1_PDDACINTERFACE_LSB)
-#define RXTXBB_RXTXBB1_PDDACINTERFACE_SET(x) (((x) << RXTXBB_RXTXBB1_PDDACINTERFACE_LSB) & RXTXBB_RXTXBB1_PDDACINTERFACE_MASK)
-#define RXTXBB_RXTXBB1_PDV2I_MSB 7
-#define RXTXBB_RXTXBB1_PDV2I_LSB 7
-#define RXTXBB_RXTXBB1_PDV2I_MASK 0x00000080
-#define RXTXBB_RXTXBB1_PDV2I_GET(x) (((x) & RXTXBB_RXTXBB1_PDV2I_MASK) >> RXTXBB_RXTXBB1_PDV2I_LSB)
-#define RXTXBB_RXTXBB1_PDV2I_SET(x) (((x) << RXTXBB_RXTXBB1_PDV2I_LSB) & RXTXBB_RXTXBB1_PDV2I_MASK)
-#define RXTXBB_RXTXBB1_PDI2V_MSB 6
-#define RXTXBB_RXTXBB1_PDI2V_LSB 6
-#define RXTXBB_RXTXBB1_PDI2V_MASK 0x00000040
-#define RXTXBB_RXTXBB1_PDI2V_GET(x) (((x) & RXTXBB_RXTXBB1_PDI2V_MASK) >> RXTXBB_RXTXBB1_PDI2V_LSB)
-#define RXTXBB_RXTXBB1_PDI2V_SET(x) (((x) << RXTXBB_RXTXBB1_PDI2V_LSB) & RXTXBB_RXTXBB1_PDI2V_MASK)
-#define RXTXBB_RXTXBB1_PDRXTXBB_MSB 5
-#define RXTXBB_RXTXBB1_PDRXTXBB_LSB 5
-#define RXTXBB_RXTXBB1_PDRXTXBB_MASK 0x00000020
-#define RXTXBB_RXTXBB1_PDRXTXBB_GET(x) (((x) & RXTXBB_RXTXBB1_PDRXTXBB_MASK) >> RXTXBB_RXTXBB1_PDRXTXBB_LSB)
-#define RXTXBB_RXTXBB1_PDRXTXBB_SET(x) (((x) << RXTXBB_RXTXBB1_PDRXTXBB_LSB) & RXTXBB_RXTXBB1_PDRXTXBB_MASK)
-#define RXTXBB_RXTXBB1_PDOFFSETLOQ_MSB 4
-#define RXTXBB_RXTXBB1_PDOFFSETLOQ_LSB 4
-#define RXTXBB_RXTXBB1_PDOFFSETLOQ_MASK 0x00000010
-#define RXTXBB_RXTXBB1_PDOFFSETLOQ_GET(x) (((x) & RXTXBB_RXTXBB1_PDOFFSETLOQ_MASK) >> RXTXBB_RXTXBB1_PDOFFSETLOQ_LSB)
-#define RXTXBB_RXTXBB1_PDOFFSETLOQ_SET(x) (((x) << RXTXBB_RXTXBB1_PDOFFSETLOQ_LSB) & RXTXBB_RXTXBB1_PDOFFSETLOQ_MASK)
-#define RXTXBB_RXTXBB1_PDOFFSETHIQ_MSB 3
-#define RXTXBB_RXTXBB1_PDOFFSETHIQ_LSB 3
-#define RXTXBB_RXTXBB1_PDOFFSETHIQ_MASK 0x00000008
-#define RXTXBB_RXTXBB1_PDOFFSETHIQ_GET(x) (((x) & RXTXBB_RXTXBB1_PDOFFSETHIQ_MASK) >> RXTXBB_RXTXBB1_PDOFFSETHIQ_LSB)
-#define RXTXBB_RXTXBB1_PDOFFSETHIQ_SET(x) (((x) << RXTXBB_RXTXBB1_PDOFFSETHIQ_LSB) & RXTXBB_RXTXBB1_PDOFFSETHIQ_MASK)
-#define RXTXBB_RXTXBB1_PDOFFSETI2V_MSB 2
-#define RXTXBB_RXTXBB1_PDOFFSETI2V_LSB 2
-#define RXTXBB_RXTXBB1_PDOFFSETI2V_MASK 0x00000004
-#define RXTXBB_RXTXBB1_PDOFFSETI2V_GET(x) (((x) & RXTXBB_RXTXBB1_PDOFFSETI2V_MASK) >> RXTXBB_RXTXBB1_PDOFFSETI2V_LSB)
-#define RXTXBB_RXTXBB1_PDOFFSETI2V_SET(x) (((x) << RXTXBB_RXTXBB1_PDOFFSETI2V_LSB) & RXTXBB_RXTXBB1_PDOFFSETI2V_MASK)
-#define RXTXBB_RXTXBB1_PDLOQ_MSB 1
-#define RXTXBB_RXTXBB1_PDLOQ_LSB 1
-#define RXTXBB_RXTXBB1_PDLOQ_MASK 0x00000002
-#define RXTXBB_RXTXBB1_PDLOQ_GET(x) (((x) & RXTXBB_RXTXBB1_PDLOQ_MASK) >> RXTXBB_RXTXBB1_PDLOQ_LSB)
-#define RXTXBB_RXTXBB1_PDLOQ_SET(x) (((x) << RXTXBB_RXTXBB1_PDLOQ_LSB) & RXTXBB_RXTXBB1_PDLOQ_MASK)
-#define RXTXBB_RXTXBB1_PDHIQ_MSB 0
-#define RXTXBB_RXTXBB1_PDHIQ_LSB 0
-#define RXTXBB_RXTXBB1_PDHIQ_MASK 0x00000001
-#define RXTXBB_RXTXBB1_PDHIQ_GET(x) (((x) & RXTXBB_RXTXBB1_PDHIQ_MASK) >> RXTXBB_RXTXBB1_PDHIQ_LSB)
-#define RXTXBB_RXTXBB1_PDHIQ_SET(x) (((x) << RXTXBB_RXTXBB1_PDHIQ_LSB) & RXTXBB_RXTXBB1_PDHIQ_MASK)
-
-#define RXTXBB_RXTXBB2_ADDRESS 0x00000054
-#define RXTXBB_RXTXBB2_OFFSET 0x00000054
-#define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_MSB 31
-#define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_LSB 29
-#define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_MASK 0xe0000000
-#define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_GET(x) (((x) & RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_MASK) >> RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_LSB)
-#define RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_SET(x) (((x) << RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_LSB) & RXTXBB_RXTXBB2_IBN_37P5_OSHI_CTRL_MASK)
-#define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_MSB 28
-#define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_LSB 26
-#define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_MASK 0x1c000000
-#define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_GET(x) (((x) & RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_MASK) >> RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_LSB)
-#define RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_SET(x) (((x) << RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_LSB) & RXTXBB_RXTXBB2_IBN_37P5_OSLO_CTRL_MASK)
-#define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_MSB 25
-#define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_LSB 23
-#define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_MASK 0x03800000
-#define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_GET(x) (((x) & RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_MASK) >> RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_LSB)
-#define RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_SET(x) (((x) << RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_LSB) & RXTXBB_RXTXBB2_IBN_37P5_OSI2V_CTRL_MASK)
-#define RXTXBB_RXTXBB2_SPARE_MSB 22
-#define RXTXBB_RXTXBB2_SPARE_LSB 21
-#define RXTXBB_RXTXBB2_SPARE_MASK 0x00600000
-#define RXTXBB_RXTXBB2_SPARE_GET(x) (((x) & RXTXBB_RXTXBB2_SPARE_MASK) >> RXTXBB_RXTXBB2_SPARE_LSB)
-#define RXTXBB_RXTXBB2_SPARE_SET(x) (((x) << RXTXBB_RXTXBB2_SPARE_LSB) & RXTXBB_RXTXBB2_SPARE_MASK)
-#define RXTXBB_RXTXBB2_SHORTBUFFER_MSB 20
-#define RXTXBB_RXTXBB2_SHORTBUFFER_LSB 20
-#define RXTXBB_RXTXBB2_SHORTBUFFER_MASK 0x00100000
-#define RXTXBB_RXTXBB2_SHORTBUFFER_GET(x) (((x) & RXTXBB_RXTXBB2_SHORTBUFFER_MASK) >> RXTXBB_RXTXBB2_SHORTBUFFER_LSB)
-#define RXTXBB_RXTXBB2_SHORTBUFFER_SET(x) (((x) << RXTXBB_RXTXBB2_SHORTBUFFER_LSB) & RXTXBB_RXTXBB2_SHORTBUFFER_MASK)
-#define RXTXBB_RXTXBB2_SELBUFFER_MSB 19
-#define RXTXBB_RXTXBB2_SELBUFFER_LSB 19
-#define RXTXBB_RXTXBB2_SELBUFFER_MASK 0x00080000
-#define RXTXBB_RXTXBB2_SELBUFFER_GET(x) (((x) & RXTXBB_RXTXBB2_SELBUFFER_MASK) >> RXTXBB_RXTXBB2_SELBUFFER_LSB)
-#define RXTXBB_RXTXBB2_SELBUFFER_SET(x) (((x) << RXTXBB_RXTXBB2_SELBUFFER_LSB) & RXTXBB_RXTXBB2_SELBUFFER_MASK)
-#define RXTXBB_RXTXBB2_SEL_DAC_TEST_MSB 18
-#define RXTXBB_RXTXBB2_SEL_DAC_TEST_LSB 18
-#define RXTXBB_RXTXBB2_SEL_DAC_TEST_MASK 0x00040000
-#define RXTXBB_RXTXBB2_SEL_DAC_TEST_GET(x) (((x) & RXTXBB_RXTXBB2_SEL_DAC_TEST_MASK) >> RXTXBB_RXTXBB2_SEL_DAC_TEST_LSB)
-#define RXTXBB_RXTXBB2_SEL_DAC_TEST_SET(x) (((x) << RXTXBB_RXTXBB2_SEL_DAC_TEST_LSB) & RXTXBB_RXTXBB2_SEL_DAC_TEST_MASK)
-#define RXTXBB_RXTXBB2_SEL_LOQ_TEST_MSB 17
-#define RXTXBB_RXTXBB2_SEL_LOQ_TEST_LSB 17
-#define RXTXBB_RXTXBB2_SEL_LOQ_TEST_MASK 0x00020000
-#define RXTXBB_RXTXBB2_SEL_LOQ_TEST_GET(x) (((x) & RXTXBB_RXTXBB2_SEL_LOQ_TEST_MASK) >> RXTXBB_RXTXBB2_SEL_LOQ_TEST_LSB)
-#define RXTXBB_RXTXBB2_SEL_LOQ_TEST_SET(x) (((x) << RXTXBB_RXTXBB2_SEL_LOQ_TEST_LSB) & RXTXBB_RXTXBB2_SEL_LOQ_TEST_MASK)
-#define RXTXBB_RXTXBB2_SEL_HIQ_TEST_MSB 16
-#define RXTXBB_RXTXBB2_SEL_HIQ_TEST_LSB 16
-#define RXTXBB_RXTXBB2_SEL_HIQ_TEST_MASK 0x00010000
-#define RXTXBB_RXTXBB2_SEL_HIQ_TEST_GET(x) (((x) & RXTXBB_RXTXBB2_SEL_HIQ_TEST_MASK) >> RXTXBB_RXTXBB2_SEL_HIQ_TEST_LSB)
-#define RXTXBB_RXTXBB2_SEL_HIQ_TEST_SET(x) (((x) << RXTXBB_RXTXBB2_SEL_HIQ_TEST_LSB) & RXTXBB_RXTXBB2_SEL_HIQ_TEST_MASK)
-#define RXTXBB_RXTXBB2_SEL_I2V_TEST_MSB 15
-#define RXTXBB_RXTXBB2_SEL_I2V_TEST_LSB 15
-#define RXTXBB_RXTXBB2_SEL_I2V_TEST_MASK 0x00008000
-#define RXTXBB_RXTXBB2_SEL_I2V_TEST_GET(x) (((x) & RXTXBB_RXTXBB2_SEL_I2V_TEST_MASK) >> RXTXBB_RXTXBB2_SEL_I2V_TEST_LSB)
-#define RXTXBB_RXTXBB2_SEL_I2V_TEST_SET(x) (((x) << RXTXBB_RXTXBB2_SEL_I2V_TEST_LSB) & RXTXBB_RXTXBB2_SEL_I2V_TEST_MASK)
-#define RXTXBB_RXTXBB2_CMSEL_MSB 14
-#define RXTXBB_RXTXBB2_CMSEL_LSB 13
-#define RXTXBB_RXTXBB2_CMSEL_MASK 0x00006000
-#define RXTXBB_RXTXBB2_CMSEL_GET(x) (((x) & RXTXBB_RXTXBB2_CMSEL_MASK) >> RXTXBB_RXTXBB2_CMSEL_LSB)
-#define RXTXBB_RXTXBB2_CMSEL_SET(x) (((x) << RXTXBB_RXTXBB2_CMSEL_LSB) & RXTXBB_RXTXBB2_CMSEL_MASK)
-#define RXTXBB_RXTXBB2_FILTERFC_MSB 12
-#define RXTXBB_RXTXBB2_FILTERFC_LSB 8
-#define RXTXBB_RXTXBB2_FILTERFC_MASK 0x00001f00
-#define RXTXBB_RXTXBB2_FILTERFC_GET(x) (((x) & RXTXBB_RXTXBB2_FILTERFC_MASK) >> RXTXBB_RXTXBB2_FILTERFC_LSB)
-#define RXTXBB_RXTXBB2_FILTERFC_SET(x) (((x) << RXTXBB_RXTXBB2_FILTERFC_LSB) & RXTXBB_RXTXBB2_FILTERFC_MASK)
-#define RXTXBB_RXTXBB2_LOCALFILTERTUNING_MSB 7
-#define RXTXBB_RXTXBB2_LOCALFILTERTUNING_LSB 7
-#define RXTXBB_RXTXBB2_LOCALFILTERTUNING_MASK 0x00000080
-#define RXTXBB_RXTXBB2_LOCALFILTERTUNING_GET(x) (((x) & RXTXBB_RXTXBB2_LOCALFILTERTUNING_MASK) >> RXTXBB_RXTXBB2_LOCALFILTERTUNING_LSB)
-#define RXTXBB_RXTXBB2_LOCALFILTERTUNING_SET(x) (((x) << RXTXBB_RXTXBB2_LOCALFILTERTUNING_LSB) & RXTXBB_RXTXBB2_LOCALFILTERTUNING_MASK)
-#define RXTXBB_RXTXBB2_FILTERDOUBLEBW_MSB 6
-#define RXTXBB_RXTXBB2_FILTERDOUBLEBW_LSB 6
-#define RXTXBB_RXTXBB2_FILTERDOUBLEBW_MASK 0x00000040
-#define RXTXBB_RXTXBB2_FILTERDOUBLEBW_GET(x) (((x) & RXTXBB_RXTXBB2_FILTERDOUBLEBW_MASK) >> RXTXBB_RXTXBB2_FILTERDOUBLEBW_LSB)
-#define RXTXBB_RXTXBB2_FILTERDOUBLEBW_SET(x) (((x) << RXTXBB_RXTXBB2_FILTERDOUBLEBW_LSB) & RXTXBB_RXTXBB2_FILTERDOUBLEBW_MASK)
-#define RXTXBB_RXTXBB2_PATH2HIQ_EN_MSB 5
-#define RXTXBB_RXTXBB2_PATH2HIQ_EN_LSB 5
-#define RXTXBB_RXTXBB2_PATH2HIQ_EN_MASK 0x00000020
-#define RXTXBB_RXTXBB2_PATH2HIQ_EN_GET(x) (((x) & RXTXBB_RXTXBB2_PATH2HIQ_EN_MASK) >> RXTXBB_RXTXBB2_PATH2HIQ_EN_LSB)
-#define RXTXBB_RXTXBB2_PATH2HIQ_EN_SET(x) (((x) << RXTXBB_RXTXBB2_PATH2HIQ_EN_LSB) & RXTXBB_RXTXBB2_PATH2HIQ_EN_MASK)
-#define RXTXBB_RXTXBB2_PATH1HIQ_EN_MSB 4
-#define RXTXBB_RXTXBB2_PATH1HIQ_EN_LSB 4
-#define RXTXBB_RXTXBB2_PATH1HIQ_EN_MASK 0x00000010
-#define RXTXBB_RXTXBB2_PATH1HIQ_EN_GET(x) (((x) & RXTXBB_RXTXBB2_PATH1HIQ_EN_MASK) >> RXTXBB_RXTXBB2_PATH1HIQ_EN_LSB)
-#define RXTXBB_RXTXBB2_PATH1HIQ_EN_SET(x) (((x) << RXTXBB_RXTXBB2_PATH1HIQ_EN_LSB) & RXTXBB_RXTXBB2_PATH1HIQ_EN_MASK)
-#define RXTXBB_RXTXBB2_PATH3LOQ_EN_MSB 3
-#define RXTXBB_RXTXBB2_PATH3LOQ_EN_LSB 3
-#define RXTXBB_RXTXBB2_PATH3LOQ_EN_MASK 0x00000008
-#define RXTXBB_RXTXBB2_PATH3LOQ_EN_GET(x) (((x) & RXTXBB_RXTXBB2_PATH3LOQ_EN_MASK) >> RXTXBB_RXTXBB2_PATH3LOQ_EN_LSB)
-#define RXTXBB_RXTXBB2_PATH3LOQ_EN_SET(x) (((x) << RXTXBB_RXTXBB2_PATH3LOQ_EN_LSB) & RXTXBB_RXTXBB2_PATH3LOQ_EN_MASK)
-#define RXTXBB_RXTXBB2_PATH2LOQ_EN_MSB 2
-#define RXTXBB_RXTXBB2_PATH2LOQ_EN_LSB 2
-#define RXTXBB_RXTXBB2_PATH2LOQ_EN_MASK 0x00000004
-#define RXTXBB_RXTXBB2_PATH2LOQ_EN_GET(x) (((x) & RXTXBB_RXTXBB2_PATH2LOQ_EN_MASK) >> RXTXBB_RXTXBB2_PATH2LOQ_EN_LSB)
-#define RXTXBB_RXTXBB2_PATH2LOQ_EN_SET(x) (((x) << RXTXBB_RXTXBB2_PATH2LOQ_EN_LSB) & RXTXBB_RXTXBB2_PATH2LOQ_EN_MASK)
-#define RXTXBB_RXTXBB2_PATH1LOQ_EN_MSB 1
-#define RXTXBB_RXTXBB2_PATH1LOQ_EN_LSB 1
-#define RXTXBB_RXTXBB2_PATH1LOQ_EN_MASK 0x00000002
-#define RXTXBB_RXTXBB2_PATH1LOQ_EN_GET(x) (((x) & RXTXBB_RXTXBB2_PATH1LOQ_EN_MASK) >> RXTXBB_RXTXBB2_PATH1LOQ_EN_LSB)
-#define RXTXBB_RXTXBB2_PATH1LOQ_EN_SET(x) (((x) << RXTXBB_RXTXBB2_PATH1LOQ_EN_LSB) & RXTXBB_RXTXBB2_PATH1LOQ_EN_MASK)
-#define RXTXBB_RXTXBB2_PATH_OVERRIDE_MSB 0
-#define RXTXBB_RXTXBB2_PATH_OVERRIDE_LSB 0
-#define RXTXBB_RXTXBB2_PATH_OVERRIDE_MASK 0x00000001
-#define RXTXBB_RXTXBB2_PATH_OVERRIDE_GET(x) (((x) & RXTXBB_RXTXBB2_PATH_OVERRIDE_MASK) >> RXTXBB_RXTXBB2_PATH_OVERRIDE_LSB)
-#define RXTXBB_RXTXBB2_PATH_OVERRIDE_SET(x) (((x) << RXTXBB_RXTXBB2_PATH_OVERRIDE_LSB) & RXTXBB_RXTXBB2_PATH_OVERRIDE_MASK)
-
-#define RXTXBB_RXTXBB3_ADDRESS 0x00000058
-#define RXTXBB_RXTXBB3_OFFSET 0x00000058
-#define RXTXBB_RXTXBB3_SPARE_MSB 31
-#define RXTXBB_RXTXBB3_SPARE_LSB 27
-#define RXTXBB_RXTXBB3_SPARE_MASK 0xf8000000
-#define RXTXBB_RXTXBB3_SPARE_GET(x) (((x) & RXTXBB_RXTXBB3_SPARE_MASK) >> RXTXBB_RXTXBB3_SPARE_LSB)
-#define RXTXBB_RXTXBB3_SPARE_SET(x) (((x) << RXTXBB_RXTXBB3_SPARE_LSB) & RXTXBB_RXTXBB3_SPARE_MASK)
-#define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_MSB 26
-#define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_LSB 24
-#define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_MASK 0x07000000
-#define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_LSB)
-#define RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_CM_BUFAMP_CTRL_MASK)
-#define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_MSB 23
-#define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_LSB 21
-#define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_MASK 0x00e00000
-#define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_LSB)
-#define RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_BKV2I_CTRL_MASK)
-#define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_MSB 20
-#define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_LSB 18
-#define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_MASK 0x001c0000
-#define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_LSB)
-#define RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_I2V_CTRL_MASK)
-#define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_MSB 17
-#define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_LSB 15
-#define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_MASK 0x00038000
-#define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_LSB)
-#define RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_HI1_CTRL_MASK)
-#define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_MSB 14
-#define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_LSB 12
-#define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_MASK 0x00007000
-#define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_LSB)
-#define RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_HI2_CTRL_MASK)
-#define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_MSB 11
-#define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_LSB 9
-#define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_MASK 0x00000e00
-#define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_LSB)
-#define RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_LO1_CTRL_MASK)
-#define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_MSB 8
-#define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_LSB 6
-#define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_MASK 0x000001c0
-#define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_LSB)
-#define RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_25U_LO2_CTRL_MASK)
-#define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_MSB 5
-#define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_LSB 3
-#define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_MASK 0x00000038
-#define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_MASK) >> RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_LSB)
-#define RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_LSB) & RXTXBB_RXTXBB3_IBRN_12P5_CM_CTRL_MASK)
-#define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_MSB 2
-#define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_LSB 0
-#define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_MASK 0x00000007
-#define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_GET(x) (((x) & RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_MASK) >> RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_LSB)
-#define RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_SET(x) (((x) << RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_LSB) & RXTXBB_RXTXBB3_IBN_100U_TEST_CTRL_MASK)
-
-#define RXTXBB_RXTXBB4_ADDRESS 0x0000005c
-#define RXTXBB_RXTXBB4_OFFSET 0x0000005c
-#define RXTXBB_RXTXBB4_SPARE_MSB 31
-#define RXTXBB_RXTXBB4_SPARE_LSB 31
-#define RXTXBB_RXTXBB4_SPARE_MASK 0x80000000
-#define RXTXBB_RXTXBB4_SPARE_GET(x) (((x) & RXTXBB_RXTXBB4_SPARE_MASK) >> RXTXBB_RXTXBB4_SPARE_LSB)
-#define RXTXBB_RXTXBB4_SPARE_SET(x) (((x) << RXTXBB_RXTXBB4_SPARE_LSB) & RXTXBB_RXTXBB4_SPARE_MASK)
-#define RXTXBB_RXTXBB4_LOCALOFFSET_MSB 30
-#define RXTXBB_RXTXBB4_LOCALOFFSET_LSB 30
-#define RXTXBB_RXTXBB4_LOCALOFFSET_MASK 0x40000000
-#define RXTXBB_RXTXBB4_LOCALOFFSET_GET(x) (((x) & RXTXBB_RXTXBB4_LOCALOFFSET_MASK) >> RXTXBB_RXTXBB4_LOCALOFFSET_LSB)
-#define RXTXBB_RXTXBB4_LOCALOFFSET_SET(x) (((x) << RXTXBB_RXTXBB4_LOCALOFFSET_LSB) & RXTXBB_RXTXBB4_LOCALOFFSET_MASK)
-#define RXTXBB_RXTXBB4_OFSTCORRHII_MSB 29
-#define RXTXBB_RXTXBB4_OFSTCORRHII_LSB 25
-#define RXTXBB_RXTXBB4_OFSTCORRHII_MASK 0x3e000000
-#define RXTXBB_RXTXBB4_OFSTCORRHII_GET(x) (((x) & RXTXBB_RXTXBB4_OFSTCORRHII_MASK) >> RXTXBB_RXTXBB4_OFSTCORRHII_LSB)
-#define RXTXBB_RXTXBB4_OFSTCORRHII_SET(x) (((x) << RXTXBB_RXTXBB4_OFSTCORRHII_LSB) & RXTXBB_RXTXBB4_OFSTCORRHII_MASK)
-#define RXTXBB_RXTXBB4_OFSTCORRHIQ_MSB 24
-#define RXTXBB_RXTXBB4_OFSTCORRHIQ_LSB 20
-#define RXTXBB_RXTXBB4_OFSTCORRHIQ_MASK 0x01f00000
-#define RXTXBB_RXTXBB4_OFSTCORRHIQ_GET(x) (((x) & RXTXBB_RXTXBB4_OFSTCORRHIQ_MASK) >> RXTXBB_RXTXBB4_OFSTCORRHIQ_LSB)
-#define RXTXBB_RXTXBB4_OFSTCORRHIQ_SET(x) (((x) << RXTXBB_RXTXBB4_OFSTCORRHIQ_LSB) & RXTXBB_RXTXBB4_OFSTCORRHIQ_MASK)
-#define RXTXBB_RXTXBB4_OFSTCORRLOI_MSB 19
-#define RXTXBB_RXTXBB4_OFSTCORRLOI_LSB 15
-#define RXTXBB_RXTXBB4_OFSTCORRLOI_MASK 0x000f8000
-#define RXTXBB_RXTXBB4_OFSTCORRLOI_GET(x) (((x) & RXTXBB_RXTXBB4_OFSTCORRLOI_MASK) >> RXTXBB_RXTXBB4_OFSTCORRLOI_LSB)
-#define RXTXBB_RXTXBB4_OFSTCORRLOI_SET(x) (((x) << RXTXBB_RXTXBB4_OFSTCORRLOI_LSB) & RXTXBB_RXTXBB4_OFSTCORRLOI_MASK)
-#define RXTXBB_RXTXBB4_OFSTCORRLOQ_MSB 14
-#define RXTXBB_RXTXBB4_OFSTCORRLOQ_LSB 10
-#define RXTXBB_RXTXBB4_OFSTCORRLOQ_MASK 0x00007c00
-#define RXTXBB_RXTXBB4_OFSTCORRLOQ_GET(x) (((x) & RXTXBB_RXTXBB4_OFSTCORRLOQ_MASK) >> RXTXBB_RXTXBB4_OFSTCORRLOQ_LSB)
-#define RXTXBB_RXTXBB4_OFSTCORRLOQ_SET(x) (((x) << RXTXBB_RXTXBB4_OFSTCORRLOQ_LSB) & RXTXBB_RXTXBB4_OFSTCORRLOQ_MASK)
-#define RXTXBB_RXTXBB4_OFSTCORRI2VI_MSB 9
-#define RXTXBB_RXTXBB4_OFSTCORRI2VI_LSB 5
-#define RXTXBB_RXTXBB4_OFSTCORRI2VI_MASK 0x000003e0
-#define RXTXBB_RXTXBB4_OFSTCORRI2VI_GET(x) (((x) & RXTXBB_RXTXBB4_OFSTCORRI2VI_MASK) >> RXTXBB_RXTXBB4_OFSTCORRI2VI_LSB)
-#define RXTXBB_RXTXBB4_OFSTCORRI2VI_SET(x) (((x) << RXTXBB_RXTXBB4_OFSTCORRI2VI_LSB) & RXTXBB_RXTXBB4_OFSTCORRI2VI_MASK)
-#define RXTXBB_RXTXBB4_OFSTCORRI2VQ_MSB 4
-#define RXTXBB_RXTXBB4_OFSTCORRI2VQ_LSB 0
-#define RXTXBB_RXTXBB4_OFSTCORRI2VQ_MASK 0x0000001f
-#define RXTXBB_RXTXBB4_OFSTCORRI2VQ_GET(x) (((x) & RXTXBB_RXTXBB4_OFSTCORRI2VQ_MASK) >> RXTXBB_RXTXBB4_OFSTCORRI2VQ_LSB)
-#define RXTXBB_RXTXBB4_OFSTCORRI2VQ_SET(x) (((x) << RXTXBB_RXTXBB4_OFSTCORRI2VQ_LSB) & RXTXBB_RXTXBB4_OFSTCORRI2VQ_MASK)
-
-#define ADDAC_ADDAC1_ADDRESS 0x00000060
-#define ADDAC_ADDAC1_OFFSET 0x00000060
-#define ADDAC_ADDAC1_PLL_SVREG_MSB 31
-#define ADDAC_ADDAC1_PLL_SVREG_LSB 31
-#define ADDAC_ADDAC1_PLL_SVREG_MASK 0x80000000
-#define ADDAC_ADDAC1_PLL_SVREG_GET(x) (((x) & ADDAC_ADDAC1_PLL_SVREG_MASK) >> ADDAC_ADDAC1_PLL_SVREG_LSB)
-#define ADDAC_ADDAC1_PLL_SVREG_SET(x) (((x) << ADDAC_ADDAC1_PLL_SVREG_LSB) & ADDAC_ADDAC1_PLL_SVREG_MASK)
-#define ADDAC_ADDAC1_PLL_SCLAMP_MSB 30
-#define ADDAC_ADDAC1_PLL_SCLAMP_LSB 28
-#define ADDAC_ADDAC1_PLL_SCLAMP_MASK 0x70000000
-#define ADDAC_ADDAC1_PLL_SCLAMP_GET(x) (((x) & ADDAC_ADDAC1_PLL_SCLAMP_MASK) >> ADDAC_ADDAC1_PLL_SCLAMP_LSB)
-#define ADDAC_ADDAC1_PLL_SCLAMP_SET(x) (((x) << ADDAC_ADDAC1_PLL_SCLAMP_LSB) & ADDAC_ADDAC1_PLL_SCLAMP_MASK)
-#define ADDAC_ADDAC1_PLL_ATB_MSB 27
-#define ADDAC_ADDAC1_PLL_ATB_LSB 26
-#define ADDAC_ADDAC1_PLL_ATB_MASK 0x0c000000
-#define ADDAC_ADDAC1_PLL_ATB_GET(x) (((x) & ADDAC_ADDAC1_PLL_ATB_MASK) >> ADDAC_ADDAC1_PLL_ATB_LSB)
-#define ADDAC_ADDAC1_PLL_ATB_SET(x) (((x) << ADDAC_ADDAC1_PLL_ATB_LSB) & ADDAC_ADDAC1_PLL_ATB_MASK)
-#define ADDAC_ADDAC1_PLL_ICP_MSB 25
-#define ADDAC_ADDAC1_PLL_ICP_LSB 23
-#define ADDAC_ADDAC1_PLL_ICP_MASK 0x03800000
-#define ADDAC_ADDAC1_PLL_ICP_GET(x) (((x) & ADDAC_ADDAC1_PLL_ICP_MASK) >> ADDAC_ADDAC1_PLL_ICP_LSB)
-#define ADDAC_ADDAC1_PLL_ICP_SET(x) (((x) << ADDAC_ADDAC1_PLL_ICP_LSB) & ADDAC_ADDAC1_PLL_ICP_MASK)
-#define ADDAC_ADDAC1_PLL_FILTER_MSB 22
-#define ADDAC_ADDAC1_PLL_FILTER_LSB 15
-#define ADDAC_ADDAC1_PLL_FILTER_MASK 0x007f8000
-#define ADDAC_ADDAC1_PLL_FILTER_GET(x) (((x) & ADDAC_ADDAC1_PLL_FILTER_MASK) >> ADDAC_ADDAC1_PLL_FILTER_LSB)
-#define ADDAC_ADDAC1_PLL_FILTER_SET(x) (((x) << ADDAC_ADDAC1_PLL_FILTER_LSB) & ADDAC_ADDAC1_PLL_FILTER_MASK)
-#define ADDAC_ADDAC1_PWDPLL_MSB 14
-#define ADDAC_ADDAC1_PWDPLL_LSB 14
-#define ADDAC_ADDAC1_PWDPLL_MASK 0x00004000
-#define ADDAC_ADDAC1_PWDPLL_GET(x) (((x) & ADDAC_ADDAC1_PWDPLL_MASK) >> ADDAC_ADDAC1_PWDPLL_LSB)
-#define ADDAC_ADDAC1_PWDPLL_SET(x) (((x) << ADDAC_ADDAC1_PWDPLL_LSB) & ADDAC_ADDAC1_PWDPLL_MASK)
-#define ADDAC_ADDAC1_PWDADC_MSB 13
-#define ADDAC_ADDAC1_PWDADC_LSB 13
-#define ADDAC_ADDAC1_PWDADC_MASK 0x00002000
-#define ADDAC_ADDAC1_PWDADC_GET(x) (((x) & ADDAC_ADDAC1_PWDADC_MASK) >> ADDAC_ADDAC1_PWDADC_LSB)
-#define ADDAC_ADDAC1_PWDADC_SET(x) (((x) << ADDAC_ADDAC1_PWDADC_LSB) & ADDAC_ADDAC1_PWDADC_MASK)
-#define ADDAC_ADDAC1_PWDDAC_MSB 12
-#define ADDAC_ADDAC1_PWDDAC_LSB 12
-#define ADDAC_ADDAC1_PWDDAC_MASK 0x00001000
-#define ADDAC_ADDAC1_PWDDAC_GET(x) (((x) & ADDAC_ADDAC1_PWDDAC_MASK) >> ADDAC_ADDAC1_PWDDAC_LSB)
-#define ADDAC_ADDAC1_PWDDAC_SET(x) (((x) << ADDAC_ADDAC1_PWDDAC_LSB) & ADDAC_ADDAC1_PWDDAC_MASK)
-#define ADDAC_ADDAC1_FORCEMSBLOW_MSB 11
-#define ADDAC_ADDAC1_FORCEMSBLOW_LSB 11
-#define ADDAC_ADDAC1_FORCEMSBLOW_MASK 0x00000800
-#define ADDAC_ADDAC1_FORCEMSBLOW_GET(x) (((x) & ADDAC_ADDAC1_FORCEMSBLOW_MASK) >> ADDAC_ADDAC1_FORCEMSBLOW_LSB)
-#define ADDAC_ADDAC1_FORCEMSBLOW_SET(x) (((x) << ADDAC_ADDAC1_FORCEMSBLOW_LSB) & ADDAC_ADDAC1_FORCEMSBLOW_MASK)
-#define ADDAC_ADDAC1_SELMANPWDS_MSB 10
-#define ADDAC_ADDAC1_SELMANPWDS_LSB 10
-#define ADDAC_ADDAC1_SELMANPWDS_MASK 0x00000400
-#define ADDAC_ADDAC1_SELMANPWDS_GET(x) (((x) & ADDAC_ADDAC1_SELMANPWDS_MASK) >> ADDAC_ADDAC1_SELMANPWDS_LSB)
-#define ADDAC_ADDAC1_SELMANPWDS_SET(x) (((x) << ADDAC_ADDAC1_SELMANPWDS_LSB) & ADDAC_ADDAC1_SELMANPWDS_MASK)
-#define ADDAC_ADDAC1_INV_CLK160_ADC_MSB 9
-#define ADDAC_ADDAC1_INV_CLK160_ADC_LSB 9
-#define ADDAC_ADDAC1_INV_CLK160_ADC_MASK 0x00000200
-#define ADDAC_ADDAC1_INV_CLK160_ADC_GET(x) (((x) & ADDAC_ADDAC1_INV_CLK160_ADC_MASK) >> ADDAC_ADDAC1_INV_CLK160_ADC_LSB)
-#define ADDAC_ADDAC1_INV_CLK160_ADC_SET(x) (((x) << ADDAC_ADDAC1_INV_CLK160_ADC_LSB) & ADDAC_ADDAC1_INV_CLK160_ADC_MASK)
-#define ADDAC_ADDAC1_CM_SEL_MSB 8
-#define ADDAC_ADDAC1_CM_SEL_LSB 7
-#define ADDAC_ADDAC1_CM_SEL_MASK 0x00000180
-#define ADDAC_ADDAC1_CM_SEL_GET(x) (((x) & ADDAC_ADDAC1_CM_SEL_MASK) >> ADDAC_ADDAC1_CM_SEL_LSB)
-#define ADDAC_ADDAC1_CM_SEL_SET(x) (((x) << ADDAC_ADDAC1_CM_SEL_LSB) & ADDAC_ADDAC1_CM_SEL_MASK)
-#define ADDAC_ADDAC1_DISABLE_DAC_REG_MSB 6
-#define ADDAC_ADDAC1_DISABLE_DAC_REG_LSB 6
-#define ADDAC_ADDAC1_DISABLE_DAC_REG_MASK 0x00000040
-#define ADDAC_ADDAC1_DISABLE_DAC_REG_GET(x) (((x) & ADDAC_ADDAC1_DISABLE_DAC_REG_MASK) >> ADDAC_ADDAC1_DISABLE_DAC_REG_LSB)
-#define ADDAC_ADDAC1_DISABLE_DAC_REG_SET(x) (((x) << ADDAC_ADDAC1_DISABLE_DAC_REG_LSB) & ADDAC_ADDAC1_DISABLE_DAC_REG_MASK)
-#define ADDAC_ADDAC1_SPARE_MSB 5
-#define ADDAC_ADDAC1_SPARE_LSB 0
-#define ADDAC_ADDAC1_SPARE_MASK 0x0000003f
-#define ADDAC_ADDAC1_SPARE_GET(x) (((x) & ADDAC_ADDAC1_SPARE_MASK) >> ADDAC_ADDAC1_SPARE_LSB)
-#define ADDAC_ADDAC1_SPARE_SET(x) (((x) << ADDAC_ADDAC1_SPARE_LSB) & ADDAC_ADDAC1_SPARE_MASK)
-
-
-#ifndef __ASSEMBLER__
-
-typedef struct analog_reg_reg_s {
- volatile unsigned int synth_synth1;
- volatile unsigned int synth_synth2;
- volatile unsigned int synth_synth3;
- volatile unsigned int synth_synth4;
- volatile unsigned int synth_synth5;
- volatile unsigned int synth_synth6;
- volatile unsigned int synth_synth7;
- volatile unsigned int synth_synth8;
- volatile unsigned int rf5g_rf5g1;
- volatile unsigned int rf5g_rf5g2;
- volatile unsigned int rf2g_rf2g1;
- volatile unsigned int rf2g_rf2g2;
- volatile unsigned int top_gain;
- volatile unsigned int top_top;
- volatile unsigned int bias_bias_sel;
- volatile unsigned int bias_bias1;
- volatile unsigned int bias_bias2;
- volatile unsigned int bias_bias3;
- volatile unsigned int txpc_txpc;
- volatile unsigned int txpc_misc;
- volatile unsigned int rxtxbb_rxtxbb1;
- volatile unsigned int rxtxbb_rxtxbb2;
- volatile unsigned int rxtxbb_rxtxbb3;
- volatile unsigned int rxtxbb_rxtxbb4;
- volatile unsigned int addac_addac1;
-} analog_reg_reg_t;
-
-#endif /* __ASSEMBLER__ */
-
-#endif /* _ANALOG_REG_H_ */
diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw2.0/hw/apb_map.h b/drivers/staging/ath6kl/include/common/AR6002/hw2.0/hw/apb_map.h
deleted file mode 100644
index f3bf6d6..0000000
--- a/drivers/staging/ath6kl/include/common/AR6002/hw2.0/hw/apb_map.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef _APB_MAP_H_
-#define _APB_MAP_H_
-
-#define RTC_BASE_ADDRESS 0x00004000
-#define VMC_BASE_ADDRESS 0x00008000
-#define UART_BASE_ADDRESS 0x0000c000
-#define SI_BASE_ADDRESS 0x00010000
-#define GPIO_BASE_ADDRESS 0x00014000
-#define MBOX_BASE_ADDRESS 0x00018000
-#define ANALOG_INTF_BASE_ADDRESS 0x0001c000
-#define MAC_BASE_ADDRESS 0x00020000
-
-#endif /* _APB_MAP_REG_H_ */
diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw2.0/hw/gpio_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw2.0/hw/gpio_reg.h
deleted file mode 100644
index 4f2b964..0000000
--- a/drivers/staging/ath6kl/include/common/AR6002/hw2.0/hw/gpio_reg.h
+++ /dev/null
@@ -1,977 +0,0 @@
-#ifndef _GPIO_REG_REG_H_
-#define _GPIO_REG_REG_H_
-
-#define GPIO_OUT_ADDRESS 0x00000000
-#define GPIO_OUT_OFFSET 0x00000000
-#define GPIO_OUT_DATA_MSB 17
-#define GPIO_OUT_DATA_LSB 0
-#define GPIO_OUT_DATA_MASK 0x0003ffff
-#define GPIO_OUT_DATA_GET(x) (((x) & GPIO_OUT_DATA_MASK) >> GPIO_OUT_DATA_LSB)
-#define GPIO_OUT_DATA_SET(x) (((x) << GPIO_OUT_DATA_LSB) & GPIO_OUT_DATA_MASK)
-
-#define GPIO_OUT_W1TS_ADDRESS 0x00000004
-#define GPIO_OUT_W1TS_OFFSET 0x00000004
-#define GPIO_OUT_W1TS_DATA_MSB 17
-#define GPIO_OUT_W1TS_DATA_LSB 0
-#define GPIO_OUT_W1TS_DATA_MASK 0x0003ffff
-#define GPIO_OUT_W1TS_DATA_GET(x) (((x) & GPIO_OUT_W1TS_DATA_MASK) >> GPIO_OUT_W1TS_DATA_LSB)
-#define GPIO_OUT_W1TS_DATA_SET(x) (((x) << GPIO_OUT_W1TS_DATA_LSB) & GPIO_OUT_W1TS_DATA_MASK)
-
-#define GPIO_OUT_W1TC_ADDRESS 0x00000008
-#define GPIO_OUT_W1TC_OFFSET 0x00000008
-#define GPIO_OUT_W1TC_DATA_MSB 17
-#define GPIO_OUT_W1TC_DATA_LSB 0
-#define GPIO_OUT_W1TC_DATA_MASK 0x0003ffff
-#define GPIO_OUT_W1TC_DATA_GET(x) (((x) & GPIO_OUT_W1TC_DATA_MASK) >> GPIO_OUT_W1TC_DATA_LSB)
-#define GPIO_OUT_W1TC_DATA_SET(x) (((x) << GPIO_OUT_W1TC_DATA_LSB) & GPIO_OUT_W1TC_DATA_MASK)
-
-#define GPIO_ENABLE_ADDRESS 0x0000000c
-#define GPIO_ENABLE_OFFSET 0x0000000c
-#define GPIO_ENABLE_DATA_MSB 17
-#define GPIO_ENABLE_DATA_LSB 0
-#define GPIO_ENABLE_DATA_MASK 0x0003ffff
-#define GPIO_ENABLE_DATA_GET(x) (((x) & GPIO_ENABLE_DATA_MASK) >> GPIO_ENABLE_DATA_LSB)
-#define GPIO_ENABLE_DATA_SET(x) (((x) << GPIO_ENABLE_DATA_LSB) & GPIO_ENABLE_DATA_MASK)
-
-#define GPIO_ENABLE_W1TS_ADDRESS 0x00000010
-#define GPIO_ENABLE_W1TS_OFFSET 0x00000010
-#define GPIO_ENABLE_W1TS_DATA_MSB 17
-#define GPIO_ENABLE_W1TS_DATA_LSB 0
-#define GPIO_ENABLE_W1TS_DATA_MASK 0x0003ffff
-#define GPIO_ENABLE_W1TS_DATA_GET(x) (((x) & GPIO_ENABLE_W1TS_DATA_MASK) >> GPIO_ENABLE_W1TS_DATA_LSB)
-#define GPIO_ENABLE_W1TS_DATA_SET(x) (((x) << GPIO_ENABLE_W1TS_DATA_LSB) & GPIO_ENABLE_W1TS_DATA_MASK)
-
-#define GPIO_ENABLE_W1TC_ADDRESS 0x00000014
-#define GPIO_ENABLE_W1TC_OFFSET 0x00000014
-#define GPIO_ENABLE_W1TC_DATA_MSB 17
-#define GPIO_ENABLE_W1TC_DATA_LSB 0
-#define GPIO_ENABLE_W1TC_DATA_MASK 0x0003ffff
-#define GPIO_ENABLE_W1TC_DATA_GET(x) (((x) & GPIO_ENABLE_W1TC_DATA_MASK) >> GPIO_ENABLE_W1TC_DATA_LSB)
-#define GPIO_ENABLE_W1TC_DATA_SET(x) (((x) << GPIO_ENABLE_W1TC_DATA_LSB) & GPIO_ENABLE_W1TC_DATA_MASK)
-
-#define GPIO_IN_ADDRESS 0x00000018
-#define GPIO_IN_OFFSET 0x00000018
-#define GPIO_IN_DATA_MSB 17
-#define GPIO_IN_DATA_LSB 0
-#define GPIO_IN_DATA_MASK 0x0003ffff
-#define GPIO_IN_DATA_GET(x) (((x) & GPIO_IN_DATA_MASK) >> GPIO_IN_DATA_LSB)
-#define GPIO_IN_DATA_SET(x) (((x) << GPIO_IN_DATA_LSB) & GPIO_IN_DATA_MASK)
-
-#define GPIO_STATUS_ADDRESS 0x0000001c
-#define GPIO_STATUS_OFFSET 0x0000001c
-#define GPIO_STATUS_INTERRUPT_MSB 17
-#define GPIO_STATUS_INTERRUPT_LSB 0
-#define GPIO_STATUS_INTERRUPT_MASK 0x0003ffff
-#define GPIO_STATUS_INTERRUPT_GET(x) (((x) & GPIO_STATUS_INTERRUPT_MASK) >> GPIO_STATUS_INTERRUPT_LSB)
-#define GPIO_STATUS_INTERRUPT_SET(x) (((x) << GPIO_STATUS_INTERRUPT_LSB) & GPIO_STATUS_INTERRUPT_MASK)
-
-#define GPIO_STATUS_W1TS_ADDRESS 0x00000020
-#define GPIO_STATUS_W1TS_OFFSET 0x00000020
-#define GPIO_STATUS_W1TS_INTERRUPT_MSB 17
-#define GPIO_STATUS_W1TS_INTERRUPT_LSB 0
-#define GPIO_STATUS_W1TS_INTERRUPT_MASK 0x0003ffff
-#define GPIO_STATUS_W1TS_INTERRUPT_GET(x) (((x) & GPIO_STATUS_W1TS_INTERRUPT_MASK) >> GPIO_STATUS_W1TS_INTERRUPT_LSB)
-#define GPIO_STATUS_W1TS_INTERRUPT_SET(x) (((x) << GPIO_STATUS_W1TS_INTERRUPT_LSB) & GPIO_STATUS_W1TS_INTERRUPT_MASK)
-
-#define GPIO_STATUS_W1TC_ADDRESS 0x00000024
-#define GPIO_STATUS_W1TC_OFFSET 0x00000024
-#define GPIO_STATUS_W1TC_INTERRUPT_MSB 17
-#define GPIO_STATUS_W1TC_INTERRUPT_LSB 0
-#define GPIO_STATUS_W1TC_INTERRUPT_MASK 0x0003ffff
-#define GPIO_STATUS_W1TC_INTERRUPT_GET(x) (((x) & GPIO_STATUS_W1TC_INTERRUPT_MASK) >> GPIO_STATUS_W1TC_INTERRUPT_LSB)
-#define GPIO_STATUS_W1TC_INTERRUPT_SET(x) (((x) << GPIO_STATUS_W1TC_INTERRUPT_LSB) & GPIO_STATUS_W1TC_INTERRUPT_MASK)
-
-#define GPIO_PIN0_ADDRESS 0x00000028
-#define GPIO_PIN0_OFFSET 0x00000028
-#define GPIO_PIN0_CONFIG_MSB 12
-#define GPIO_PIN0_CONFIG_LSB 11
-#define GPIO_PIN0_CONFIG_MASK 0x00001800
-#define GPIO_PIN0_CONFIG_GET(x) (((x) & GPIO_PIN0_CONFIG_MASK) >> GPIO_PIN0_CONFIG_LSB)
-#define GPIO_PIN0_CONFIG_SET(x) (((x) << GPIO_PIN0_CONFIG_LSB) & GPIO_PIN0_CONFIG_MASK)
-#define GPIO_PIN0_WAKEUP_ENABLE_MSB 10
-#define GPIO_PIN0_WAKEUP_ENABLE_LSB 10
-#define GPIO_PIN0_WAKEUP_ENABLE_MASK 0x00000400
-#define GPIO_PIN0_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN0_WAKEUP_ENABLE_MASK) >> GPIO_PIN0_WAKEUP_ENABLE_LSB)
-#define GPIO_PIN0_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN0_WAKEUP_ENABLE_LSB) & GPIO_PIN0_WAKEUP_ENABLE_MASK)
-#define GPIO_PIN0_INT_TYPE_MSB 9
-#define GPIO_PIN0_INT_TYPE_LSB 7
-#define GPIO_PIN0_INT_TYPE_MASK 0x00000380
-#define GPIO_PIN0_INT_TYPE_GET(x) (((x) & GPIO_PIN0_INT_TYPE_MASK) >> GPIO_PIN0_INT_TYPE_LSB)
-#define GPIO_PIN0_INT_TYPE_SET(x) (((x) << GPIO_PIN0_INT_TYPE_LSB) & GPIO_PIN0_INT_TYPE_MASK)
-#define GPIO_PIN0_PAD_DRIVER_MSB 2
-#define GPIO_PIN0_PAD_DRIVER_LSB 2
-#define GPIO_PIN0_PAD_DRIVER_MASK 0x00000004
-#define GPIO_PIN0_PAD_DRIVER_GET(x) (((x) & GPIO_PIN0_PAD_DRIVER_MASK) >> GPIO_PIN0_PAD_DRIVER_LSB)
-#define GPIO_PIN0_PAD_DRIVER_SET(x) (((x) << GPIO_PIN0_PAD_DRIVER_LSB) & GPIO_PIN0_PAD_DRIVER_MASK)
-#define GPIO_PIN0_SOURCE_MSB 0
-#define GPIO_PIN0_SOURCE_LSB 0
-#define GPIO_PIN0_SOURCE_MASK 0x00000001
-#define GPIO_PIN0_SOURCE_GET(x) (((x) & GPIO_PIN0_SOURCE_MASK) >> GPIO_PIN0_SOURCE_LSB)
-#define GPIO_PIN0_SOURCE_SET(x) (((x) << GPIO_PIN0_SOURCE_LSB) & GPIO_PIN0_SOURCE_MASK)
-
-#define GPIO_PIN1_ADDRESS 0x0000002c
-#define GPIO_PIN1_OFFSET 0x0000002c
-#define GPIO_PIN1_CONFIG_MSB 12
-#define GPIO_PIN1_CONFIG_LSB 11
-#define GPIO_PIN1_CONFIG_MASK 0x00001800
-#define GPIO_PIN1_CONFIG_GET(x) (((x) & GPIO_PIN1_CONFIG_MASK) >> GPIO_PIN1_CONFIG_LSB)
-#define GPIO_PIN1_CONFIG_SET(x) (((x) << GPIO_PIN1_CONFIG_LSB) & GPIO_PIN1_CONFIG_MASK)
-#define GPIO_PIN1_WAKEUP_ENABLE_MSB 10
-#define GPIO_PIN1_WAKEUP_ENABLE_LSB 10
-#define GPIO_PIN1_WAKEUP_ENABLE_MASK 0x00000400
-#define GPIO_PIN1_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN1_WAKEUP_ENABLE_MASK) >> GPIO_PIN1_WAKEUP_ENABLE_LSB)
-#define GPIO_PIN1_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN1_WAKEUP_ENABLE_LSB) & GPIO_PIN1_WAKEUP_ENABLE_MASK)
-#define GPIO_PIN1_INT_TYPE_MSB 9
-#define GPIO_PIN1_INT_TYPE_LSB 7
-#define GPIO_PIN1_INT_TYPE_MASK 0x00000380
-#define GPIO_PIN1_INT_TYPE_GET(x) (((x) & GPIO_PIN1_INT_TYPE_MASK) >> GPIO_PIN1_INT_TYPE_LSB)
-#define GPIO_PIN1_INT_TYPE_SET(x) (((x) << GPIO_PIN1_INT_TYPE_LSB) & GPIO_PIN1_INT_TYPE_MASK)
-#define GPIO_PIN1_PAD_DRIVER_MSB 2
-#define GPIO_PIN1_PAD_DRIVER_LSB 2
-#define GPIO_PIN1_PAD_DRIVER_MASK 0x00000004
-#define GPIO_PIN1_PAD_DRIVER_GET(x) (((x) & GPIO_PIN1_PAD_DRIVER_MASK) >> GPIO_PIN1_PAD_DRIVER_LSB)
-#define GPIO_PIN1_PAD_DRIVER_SET(x) (((x) << GPIO_PIN1_PAD_DRIVER_LSB) & GPIO_PIN1_PAD_DRIVER_MASK)
-#define GPIO_PIN1_SOURCE_MSB 0
-#define GPIO_PIN1_SOURCE_LSB 0
-#define GPIO_PIN1_SOURCE_MASK 0x00000001
-#define GPIO_PIN1_SOURCE_GET(x) (((x) & GPIO_PIN1_SOURCE_MASK) >> GPIO_PIN1_SOURCE_LSB)
-#define GPIO_PIN1_SOURCE_SET(x) (((x) << GPIO_PIN1_SOURCE_LSB) & GPIO_PIN1_SOURCE_MASK)
-
-#define GPIO_PIN2_ADDRESS 0x00000030
-#define GPIO_PIN2_OFFSET 0x00000030
-#define GPIO_PIN2_CONFIG_MSB 12
-#define GPIO_PIN2_CONFIG_LSB 11
-#define GPIO_PIN2_CONFIG_MASK 0x00001800
-#define GPIO_PIN2_CONFIG_GET(x) (((x) & GPIO_PIN2_CONFIG_MASK) >> GPIO_PIN2_CONFIG_LSB)
-#define GPIO_PIN2_CONFIG_SET(x) (((x) << GPIO_PIN2_CONFIG_LSB) & GPIO_PIN2_CONFIG_MASK)
-#define GPIO_PIN2_WAKEUP_ENABLE_MSB 10
-#define GPIO_PIN2_WAKEUP_ENABLE_LSB 10
-#define GPIO_PIN2_WAKEUP_ENABLE_MASK 0x00000400
-#define GPIO_PIN2_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN2_WAKEUP_ENABLE_MASK) >> GPIO_PIN2_WAKEUP_ENABLE_LSB)
-#define GPIO_PIN2_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN2_WAKEUP_ENABLE_LSB) & GPIO_PIN2_WAKEUP_ENABLE_MASK)
-#define GPIO_PIN2_INT_TYPE_MSB 9
-#define GPIO_PIN2_INT_TYPE_LSB 7
-#define GPIO_PIN2_INT_TYPE_MASK 0x00000380
-#define GPIO_PIN2_INT_TYPE_GET(x) (((x) & GPIO_PIN2_INT_TYPE_MASK) >> GPIO_PIN2_INT_TYPE_LSB)
-#define GPIO_PIN2_INT_TYPE_SET(x) (((x) << GPIO_PIN2_INT_TYPE_LSB) & GPIO_PIN2_INT_TYPE_MASK)
-#define GPIO_PIN2_PAD_DRIVER_MSB 2
-#define GPIO_PIN2_PAD_DRIVER_LSB 2
-#define GPIO_PIN2_PAD_DRIVER_MASK 0x00000004
-#define GPIO_PIN2_PAD_DRIVER_GET(x) (((x) & GPIO_PIN2_PAD_DRIVER_MASK) >> GPIO_PIN2_PAD_DRIVER_LSB)
-#define GPIO_PIN2_PAD_DRIVER_SET(x) (((x) << GPIO_PIN2_PAD_DRIVER_LSB) & GPIO_PIN2_PAD_DRIVER_MASK)
-#define GPIO_PIN2_SOURCE_MSB 0
-#define GPIO_PIN2_SOURCE_LSB 0
-#define GPIO_PIN2_SOURCE_MASK 0x00000001
-#define GPIO_PIN2_SOURCE_GET(x) (((x) & GPIO_PIN2_SOURCE_MASK) >> GPIO_PIN2_SOURCE_LSB)
-#define GPIO_PIN2_SOURCE_SET(x) (((x) << GPIO_PIN2_SOURCE_LSB) & GPIO_PIN2_SOURCE_MASK)
-
-#define GPIO_PIN3_ADDRESS 0x00000034
-#define GPIO_PIN3_OFFSET 0x00000034
-#define GPIO_PIN3_CONFIG_MSB 12
-#define GPIO_PIN3_CONFIG_LSB 11
-#define GPIO_PIN3_CONFIG_MASK 0x00001800
-#define GPIO_PIN3_CONFIG_GET(x) (((x) & GPIO_PIN3_CONFIG_MASK) >> GPIO_PIN3_CONFIG_LSB)
-#define GPIO_PIN3_CONFIG_SET(x) (((x) << GPIO_PIN3_CONFIG_LSB) & GPIO_PIN3_CONFIG_MASK)
-#define GPIO_PIN3_WAKEUP_ENABLE_MSB 10
-#define GPIO_PIN3_WAKEUP_ENABLE_LSB 10
-#define GPIO_PIN3_WAKEUP_ENABLE_MASK 0x00000400
-#define GPIO_PIN3_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN3_WAKEUP_ENABLE_MASK) >> GPIO_PIN3_WAKEUP_ENABLE_LSB)
-#define GPIO_PIN3_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN3_WAKEUP_ENABLE_LSB) & GPIO_PIN3_WAKEUP_ENABLE_MASK)
-#define GPIO_PIN3_INT_TYPE_MSB 9
-#define GPIO_PIN3_INT_TYPE_LSB 7
-#define GPIO_PIN3_INT_TYPE_MASK 0x00000380
-#define GPIO_PIN3_INT_TYPE_GET(x) (((x) & GPIO_PIN3_INT_TYPE_MASK) >> GPIO_PIN3_INT_TYPE_LSB)
-#define GPIO_PIN3_INT_TYPE_SET(x) (((x) << GPIO_PIN3_INT_TYPE_LSB) & GPIO_PIN3_INT_TYPE_MASK)
-#define GPIO_PIN3_PAD_DRIVER_MSB 2
-#define GPIO_PIN3_PAD_DRIVER_LSB 2
-#define GPIO_PIN3_PAD_DRIVER_MASK 0x00000004
-#define GPIO_PIN3_PAD_DRIVER_GET(x) (((x) & GPIO_PIN3_PAD_DRIVER_MASK) >> GPIO_PIN3_PAD_DRIVER_LSB)
-#define GPIO_PIN3_PAD_DRIVER_SET(x) (((x) << GPIO_PIN3_PAD_DRIVER_LSB) & GPIO_PIN3_PAD_DRIVER_MASK)
-#define GPIO_PIN3_SOURCE_MSB 0
-#define GPIO_PIN3_SOURCE_LSB 0
-#define GPIO_PIN3_SOURCE_MASK 0x00000001
-#define GPIO_PIN3_SOURCE_GET(x) (((x) & GPIO_PIN3_SOURCE_MASK) >> GPIO_PIN3_SOURCE_LSB)
-#define GPIO_PIN3_SOURCE_SET(x) (((x) << GPIO_PIN3_SOURCE_LSB) & GPIO_PIN3_SOURCE_MASK)
-
-#define GPIO_PIN4_ADDRESS 0x00000038
-#define GPIO_PIN4_OFFSET 0x00000038
-#define GPIO_PIN4_CONFIG_MSB 12
-#define GPIO_PIN4_CONFIG_LSB 11
-#define GPIO_PIN4_CONFIG_MASK 0x00001800
-#define GPIO_PIN4_CONFIG_GET(x) (((x) & GPIO_PIN4_CONFIG_MASK) >> GPIO_PIN4_CONFIG_LSB)
-#define GPIO_PIN4_CONFIG_SET(x) (((x) << GPIO_PIN4_CONFIG_LSB) & GPIO_PIN4_CONFIG_MASK)
-#define GPIO_PIN4_WAKEUP_ENABLE_MSB 10
-#define GPIO_PIN4_WAKEUP_ENABLE_LSB 10
-#define GPIO_PIN4_WAKEUP_ENABLE_MASK 0x00000400
-#define GPIO_PIN4_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN4_WAKEUP_ENABLE_MASK) >> GPIO_PIN4_WAKEUP_ENABLE_LSB)
-#define GPIO_PIN4_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN4_WAKEUP_ENABLE_LSB) & GPIO_PIN4_WAKEUP_ENABLE_MASK)
-#define GPIO_PIN4_INT_TYPE_MSB 9
-#define GPIO_PIN4_INT_TYPE_LSB 7
-#define GPIO_PIN4_INT_TYPE_MASK 0x00000380
-#define GPIO_PIN4_INT_TYPE_GET(x) (((x) & GPIO_PIN4_INT_TYPE_MASK) >> GPIO_PIN4_INT_TYPE_LSB)
-#define GPIO_PIN4_INT_TYPE_SET(x) (((x) << GPIO_PIN4_INT_TYPE_LSB) & GPIO_PIN4_INT_TYPE_MASK)
-#define GPIO_PIN4_PAD_DRIVER_MSB 2
-#define GPIO_PIN4_PAD_DRIVER_LSB 2
-#define GPIO_PIN4_PAD_DRIVER_MASK 0x00000004
-#define GPIO_PIN4_PAD_DRIVER_GET(x) (((x) & GPIO_PIN4_PAD_DRIVER_MASK) >> GPIO_PIN4_PAD_DRIVER_LSB)
-#define GPIO_PIN4_PAD_DRIVER_SET(x) (((x) << GPIO_PIN4_PAD_DRIVER_LSB) & GPIO_PIN4_PAD_DRIVER_MASK)
-#define GPIO_PIN4_SOURCE_MSB 0
-#define GPIO_PIN4_SOURCE_LSB 0
-#define GPIO_PIN4_SOURCE_MASK 0x00000001
-#define GPIO_PIN4_SOURCE_GET(x) (((x) & GPIO_PIN4_SOURCE_MASK) >> GPIO_PIN4_SOURCE_LSB)
-#define GPIO_PIN4_SOURCE_SET(x) (((x) << GPIO_PIN4_SOURCE_LSB) & GPIO_PIN4_SOURCE_MASK)
-
-#define GPIO_PIN5_ADDRESS 0x0000003c
-#define GPIO_PIN5_OFFSET 0x0000003c
-#define GPIO_PIN5_CONFIG_MSB 12
-#define GPIO_PIN5_CONFIG_LSB 11
-#define GPIO_PIN5_CONFIG_MASK 0x00001800
-#define GPIO_PIN5_CONFIG_GET(x) (((x) & GPIO_PIN5_CONFIG_MASK) >> GPIO_PIN5_CONFIG_LSB)
-#define GPIO_PIN5_CONFIG_SET(x) (((x) << GPIO_PIN5_CONFIG_LSB) & GPIO_PIN5_CONFIG_MASK)
-#define GPIO_PIN5_WAKEUP_ENABLE_MSB 10
-#define GPIO_PIN5_WAKEUP_ENABLE_LSB 10
-#define GPIO_PIN5_WAKEUP_ENABLE_MASK 0x00000400
-#define GPIO_PIN5_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN5_WAKEUP_ENABLE_MASK) >> GPIO_PIN5_WAKEUP_ENABLE_LSB)
-#define GPIO_PIN5_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN5_WAKEUP_ENABLE_LSB) & GPIO_PIN5_WAKEUP_ENABLE_MASK)
-#define GPIO_PIN5_INT_TYPE_MSB 9
-#define GPIO_PIN5_INT_TYPE_LSB 7
-#define GPIO_PIN5_INT_TYPE_MASK 0x00000380
-#define GPIO_PIN5_INT_TYPE_GET(x) (((x) & GPIO_PIN5_INT_TYPE_MASK) >> GPIO_PIN5_INT_TYPE_LSB)
-#define GPIO_PIN5_INT_TYPE_SET(x) (((x) << GPIO_PIN5_INT_TYPE_LSB) & GPIO_PIN5_INT_TYPE_MASK)
-#define GPIO_PIN5_PAD_DRIVER_MSB 2
-#define GPIO_PIN5_PAD_DRIVER_LSB 2
-#define GPIO_PIN5_PAD_DRIVER_MASK 0x00000004
-#define GPIO_PIN5_PAD_DRIVER_GET(x) (((x) & GPIO_PIN5_PAD_DRIVER_MASK) >> GPIO_PIN5_PAD_DRIVER_LSB)
-#define GPIO_PIN5_PAD_DRIVER_SET(x) (((x) << GPIO_PIN5_PAD_DRIVER_LSB) & GPIO_PIN5_PAD_DRIVER_MASK)
-#define GPIO_PIN5_SOURCE_MSB 0
-#define GPIO_PIN5_SOURCE_LSB 0
-#define GPIO_PIN5_SOURCE_MASK 0x00000001
-#define GPIO_PIN5_SOURCE_GET(x) (((x) & GPIO_PIN5_SOURCE_MASK) >> GPIO_PIN5_SOURCE_LSB)
-#define GPIO_PIN5_SOURCE_SET(x) (((x) << GPIO_PIN5_SOURCE_LSB) & GPIO_PIN5_SOURCE_MASK)
-
-#define GPIO_PIN6_ADDRESS 0x00000040
-#define GPIO_PIN6_OFFSET 0x00000040
-#define GPIO_PIN6_CONFIG_MSB 12
-#define GPIO_PIN6_CONFIG_LSB 11
-#define GPIO_PIN6_CONFIG_MASK 0x00001800
-#define GPIO_PIN6_CONFIG_GET(x) (((x) & GPIO_PIN6_CONFIG_MASK) >> GPIO_PIN6_CONFIG_LSB)
-#define GPIO_PIN6_CONFIG_SET(x) (((x) << GPIO_PIN6_CONFIG_LSB) & GPIO_PIN6_CONFIG_MASK)
-#define GPIO_PIN6_WAKEUP_ENABLE_MSB 10
-#define GPIO_PIN6_WAKEUP_ENABLE_LSB 10
-#define GPIO_PIN6_WAKEUP_ENABLE_MASK 0x00000400
-#define GPIO_PIN6_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN6_WAKEUP_ENABLE_MASK) >> GPIO_PIN6_WAKEUP_ENABLE_LSB)
-#define GPIO_PIN6_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN6_WAKEUP_ENABLE_LSB) & GPIO_PIN6_WAKEUP_ENABLE_MASK)
-#define GPIO_PIN6_INT_TYPE_MSB 9
-#define GPIO_PIN6_INT_TYPE_LSB 7
-#define GPIO_PIN6_INT_TYPE_MASK 0x00000380
-#define GPIO_PIN6_INT_TYPE_GET(x) (((x) & GPIO_PIN6_INT_TYPE_MASK) >> GPIO_PIN6_INT_TYPE_LSB)
-#define GPIO_PIN6_INT_TYPE_SET(x) (((x) << GPIO_PIN6_INT_TYPE_LSB) & GPIO_PIN6_INT_TYPE_MASK)
-#define GPIO_PIN6_PAD_DRIVER_MSB 2
-#define GPIO_PIN6_PAD_DRIVER_LSB 2
-#define GPIO_PIN6_PAD_DRIVER_MASK 0x00000004
-#define GPIO_PIN6_PAD_DRIVER_GET(x) (((x) & GPIO_PIN6_PAD_DRIVER_MASK) >> GPIO_PIN6_PAD_DRIVER_LSB)
-#define GPIO_PIN6_PAD_DRIVER_SET(x) (((x) << GPIO_PIN6_PAD_DRIVER_LSB) & GPIO_PIN6_PAD_DRIVER_MASK)
-#define GPIO_PIN6_SOURCE_MSB 0
-#define GPIO_PIN6_SOURCE_LSB 0
-#define GPIO_PIN6_SOURCE_MASK 0x00000001
-#define GPIO_PIN6_SOURCE_GET(x) (((x) & GPIO_PIN6_SOURCE_MASK) >> GPIO_PIN6_SOURCE_LSB)
-#define GPIO_PIN6_SOURCE_SET(x) (((x) << GPIO_PIN6_SOURCE_LSB) & GPIO_PIN6_SOURCE_MASK)
-
-#define GPIO_PIN7_ADDRESS 0x00000044
-#define GPIO_PIN7_OFFSET 0x00000044
-#define GPIO_PIN7_CONFIG_MSB 12
-#define GPIO_PIN7_CONFIG_LSB 11
-#define GPIO_PIN7_CONFIG_MASK 0x00001800
-#define GPIO_PIN7_CONFIG_GET(x) (((x) & GPIO_PIN7_CONFIG_MASK) >> GPIO_PIN7_CONFIG_LSB)
-#define GPIO_PIN7_CONFIG_SET(x) (((x) << GPIO_PIN7_CONFIG_LSB) & GPIO_PIN7_CONFIG_MASK)
-#define GPIO_PIN7_WAKEUP_ENABLE_MSB 10
-#define GPIO_PIN7_WAKEUP_ENABLE_LSB 10
-#define GPIO_PIN7_WAKEUP_ENABLE_MASK 0x00000400
-#define GPIO_PIN7_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN7_WAKEUP_ENABLE_MASK) >> GPIO_PIN7_WAKEUP_ENABLE_LSB)
-#define GPIO_PIN7_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN7_WAKEUP_ENABLE_LSB) & GPIO_PIN7_WAKEUP_ENABLE_MASK)
-#define GPIO_PIN7_INT_TYPE_MSB 9
-#define GPIO_PIN7_INT_TYPE_LSB 7
-#define GPIO_PIN7_INT_TYPE_MASK 0x00000380
-#define GPIO_PIN7_INT_TYPE_GET(x) (((x) & GPIO_PIN7_INT_TYPE_MASK) >> GPIO_PIN7_INT_TYPE_LSB)
-#define GPIO_PIN7_INT_TYPE_SET(x) (((x) << GPIO_PIN7_INT_TYPE_LSB) & GPIO_PIN7_INT_TYPE_MASK)
-#define GPIO_PIN7_PAD_DRIVER_MSB 2
-#define GPIO_PIN7_PAD_DRIVER_LSB 2
-#define GPIO_PIN7_PAD_DRIVER_MASK 0x00000004
-#define GPIO_PIN7_PAD_DRIVER_GET(x) (((x) & GPIO_PIN7_PAD_DRIVER_MASK) >> GPIO_PIN7_PAD_DRIVER_LSB)
-#define GPIO_PIN7_PAD_DRIVER_SET(x) (((x) << GPIO_PIN7_PAD_DRIVER_LSB) & GPIO_PIN7_PAD_DRIVER_MASK)
-#define GPIO_PIN7_SOURCE_MSB 0
-#define GPIO_PIN7_SOURCE_LSB 0
-#define GPIO_PIN7_SOURCE_MASK 0x00000001
-#define GPIO_PIN7_SOURCE_GET(x) (((x) & GPIO_PIN7_SOURCE_MASK) >> GPIO_PIN7_SOURCE_LSB)
-#define GPIO_PIN7_SOURCE_SET(x) (((x) << GPIO_PIN7_SOURCE_LSB) & GPIO_PIN7_SOURCE_MASK)
-
-#define GPIO_PIN8_ADDRESS 0x00000048
-#define GPIO_PIN8_OFFSET 0x00000048
-#define GPIO_PIN8_CONFIG_MSB 12
-#define GPIO_PIN8_CONFIG_LSB 11
-#define GPIO_PIN8_CONFIG_MASK 0x00001800
-#define GPIO_PIN8_CONFIG_GET(x) (((x) & GPIO_PIN8_CONFIG_MASK) >> GPIO_PIN8_CONFIG_LSB)
-#define GPIO_PIN8_CONFIG_SET(x) (((x) << GPIO_PIN8_CONFIG_LSB) & GPIO_PIN8_CONFIG_MASK)
-#define GPIO_PIN8_WAKEUP_ENABLE_MSB 10
-#define GPIO_PIN8_WAKEUP_ENABLE_LSB 10
-#define GPIO_PIN8_WAKEUP_ENABLE_MASK 0x00000400
-#define GPIO_PIN8_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN8_WAKEUP_ENABLE_MASK) >> GPIO_PIN8_WAKEUP_ENABLE_LSB)
-#define GPIO_PIN8_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN8_WAKEUP_ENABLE_LSB) & GPIO_PIN8_WAKEUP_ENABLE_MASK)
-#define GPIO_PIN8_INT_TYPE_MSB 9
-#define GPIO_PIN8_INT_TYPE_LSB 7
-#define GPIO_PIN8_INT_TYPE_MASK 0x00000380
-#define GPIO_PIN8_INT_TYPE_GET(x) (((x) & GPIO_PIN8_INT_TYPE_MASK) >> GPIO_PIN8_INT_TYPE_LSB)
-#define GPIO_PIN8_INT_TYPE_SET(x) (((x) << GPIO_PIN8_INT_TYPE_LSB) & GPIO_PIN8_INT_TYPE_MASK)
-#define GPIO_PIN8_PAD_DRIVER_MSB 2
-#define GPIO_PIN8_PAD_DRIVER_LSB 2
-#define GPIO_PIN8_PAD_DRIVER_MASK 0x00000004
-#define GPIO_PIN8_PAD_DRIVER_GET(x) (((x) & GPIO_PIN8_PAD_DRIVER_MASK) >> GPIO_PIN8_PAD_DRIVER_LSB)
-#define GPIO_PIN8_PAD_DRIVER_SET(x) (((x) << GPIO_PIN8_PAD_DRIVER_LSB) & GPIO_PIN8_PAD_DRIVER_MASK)
-#define GPIO_PIN8_SOURCE_MSB 0
-#define GPIO_PIN8_SOURCE_LSB 0
-#define GPIO_PIN8_SOURCE_MASK 0x00000001
-#define GPIO_PIN8_SOURCE_GET(x) (((x) & GPIO_PIN8_SOURCE_MASK) >> GPIO_PIN8_SOURCE_LSB)
-#define GPIO_PIN8_SOURCE_SET(x) (((x) << GPIO_PIN8_SOURCE_LSB) & GPIO_PIN8_SOURCE_MASK)
-
-#define GPIO_PIN9_ADDRESS 0x0000004c
-#define GPIO_PIN9_OFFSET 0x0000004c
-#define GPIO_PIN9_CONFIG_MSB 12
-#define GPIO_PIN9_CONFIG_LSB 11
-#define GPIO_PIN9_CONFIG_MASK 0x00001800
-#define GPIO_PIN9_CONFIG_GET(x) (((x) & GPIO_PIN9_CONFIG_MASK) >> GPIO_PIN9_CONFIG_LSB)
-#define GPIO_PIN9_CONFIG_SET(x) (((x) << GPIO_PIN9_CONFIG_LSB) & GPIO_PIN9_CONFIG_MASK)
-#define GPIO_PIN9_WAKEUP_ENABLE_MSB 10
-#define GPIO_PIN9_WAKEUP_ENABLE_LSB 10
-#define GPIO_PIN9_WAKEUP_ENABLE_MASK 0x00000400
-#define GPIO_PIN9_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN9_WAKEUP_ENABLE_MASK) >> GPIO_PIN9_WAKEUP_ENABLE_LSB)
-#define GPIO_PIN9_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN9_WAKEUP_ENABLE_LSB) & GPIO_PIN9_WAKEUP_ENABLE_MASK)
-#define GPIO_PIN9_INT_TYPE_MSB 9
-#define GPIO_PIN9_INT_TYPE_LSB 7
-#define GPIO_PIN9_INT_TYPE_MASK 0x00000380
-#define GPIO_PIN9_INT_TYPE_GET(x) (((x) & GPIO_PIN9_INT_TYPE_MASK) >> GPIO_PIN9_INT_TYPE_LSB)
-#define GPIO_PIN9_INT_TYPE_SET(x) (((x) << GPIO_PIN9_INT_TYPE_LSB) & GPIO_PIN9_INT_TYPE_MASK)
-#define GPIO_PIN9_PAD_DRIVER_MSB 2
-#define GPIO_PIN9_PAD_DRIVER_LSB 2
-#define GPIO_PIN9_PAD_DRIVER_MASK 0x00000004
-#define GPIO_PIN9_PAD_DRIVER_GET(x) (((x) & GPIO_PIN9_PAD_DRIVER_MASK) >> GPIO_PIN9_PAD_DRIVER_LSB)
-#define GPIO_PIN9_PAD_DRIVER_SET(x) (((x) << GPIO_PIN9_PAD_DRIVER_LSB) & GPIO_PIN9_PAD_DRIVER_MASK)
-#define GPIO_PIN9_SOURCE_MSB 0
-#define GPIO_PIN9_SOURCE_LSB 0
-#define GPIO_PIN9_SOURCE_MASK 0x00000001
-#define GPIO_PIN9_SOURCE_GET(x) (((x) & GPIO_PIN9_SOURCE_MASK) >> GPIO_PIN9_SOURCE_LSB)
-#define GPIO_PIN9_SOURCE_SET(x) (((x) << GPIO_PIN9_SOURCE_LSB) & GPIO_PIN9_SOURCE_MASK)
-
-#define GPIO_PIN10_ADDRESS 0x00000050
-#define GPIO_PIN10_OFFSET 0x00000050
-#define GPIO_PIN10_CONFIG_MSB 12
-#define GPIO_PIN10_CONFIG_LSB 11
-#define GPIO_PIN10_CONFIG_MASK 0x00001800
-#define GPIO_PIN10_CONFIG_GET(x) (((x) & GPIO_PIN10_CONFIG_MASK) >> GPIO_PIN10_CONFIG_LSB)
-#define GPIO_PIN10_CONFIG_SET(x) (((x) << GPIO_PIN10_CONFIG_LSB) & GPIO_PIN10_CONFIG_MASK)
-#define GPIO_PIN10_WAKEUP_ENABLE_MSB 10
-#define GPIO_PIN10_WAKEUP_ENABLE_LSB 10
-#define GPIO_PIN10_WAKEUP_ENABLE_MASK 0x00000400
-#define GPIO_PIN10_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN10_WAKEUP_ENABLE_MASK) >> GPIO_PIN10_WAKEUP_ENABLE_LSB)
-#define GPIO_PIN10_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN10_WAKEUP_ENABLE_LSB) & GPIO_PIN10_WAKEUP_ENABLE_MASK)
-#define GPIO_PIN10_INT_TYPE_MSB 9
-#define GPIO_PIN10_INT_TYPE_LSB 7
-#define GPIO_PIN10_INT_TYPE_MASK 0x00000380
-#define GPIO_PIN10_INT_TYPE_GET(x) (((x) & GPIO_PIN10_INT_TYPE_MASK) >> GPIO_PIN10_INT_TYPE_LSB)
-#define GPIO_PIN10_INT_TYPE_SET(x) (((x) << GPIO_PIN10_INT_TYPE_LSB) & GPIO_PIN10_INT_TYPE_MASK)
-#define GPIO_PIN10_PAD_DRIVER_MSB 2
-#define GPIO_PIN10_PAD_DRIVER_LSB 2
-#define GPIO_PIN10_PAD_DRIVER_MASK 0x00000004
-#define GPIO_PIN10_PAD_DRIVER_GET(x) (((x) & GPIO_PIN10_PAD_DRIVER_MASK) >> GPIO_PIN10_PAD_DRIVER_LSB)
-#define GPIO_PIN10_PAD_DRIVER_SET(x) (((x) << GPIO_PIN10_PAD_DRIVER_LSB) & GPIO_PIN10_PAD_DRIVER_MASK)
-#define GPIO_PIN10_SOURCE_MSB 0
-#define GPIO_PIN10_SOURCE_LSB 0
-#define GPIO_PIN10_SOURCE_MASK 0x00000001
-#define GPIO_PIN10_SOURCE_GET(x) (((x) & GPIO_PIN10_SOURCE_MASK) >> GPIO_PIN10_SOURCE_LSB)
-#define GPIO_PIN10_SOURCE_SET(x) (((x) << GPIO_PIN10_SOURCE_LSB) & GPIO_PIN10_SOURCE_MASK)
-
-#define GPIO_PIN11_ADDRESS 0x00000054
-#define GPIO_PIN11_OFFSET 0x00000054
-#define GPIO_PIN11_CONFIG_MSB 12
-#define GPIO_PIN11_CONFIG_LSB 11
-#define GPIO_PIN11_CONFIG_MASK 0x00001800
-#define GPIO_PIN11_CONFIG_GET(x) (((x) & GPIO_PIN11_CONFIG_MASK) >> GPIO_PIN11_CONFIG_LSB)
-#define GPIO_PIN11_CONFIG_SET(x) (((x) << GPIO_PIN11_CONFIG_LSB) & GPIO_PIN11_CONFIG_MASK)
-#define GPIO_PIN11_WAKEUP_ENABLE_MSB 10
-#define GPIO_PIN11_WAKEUP_ENABLE_LSB 10
-#define GPIO_PIN11_WAKEUP_ENABLE_MASK 0x00000400
-#define GPIO_PIN11_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN11_WAKEUP_ENABLE_MASK) >> GPIO_PIN11_WAKEUP_ENABLE_LSB)
-#define GPIO_PIN11_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN11_WAKEUP_ENABLE_LSB) & GPIO_PIN11_WAKEUP_ENABLE_MASK)
-#define GPIO_PIN11_INT_TYPE_MSB 9
-#define GPIO_PIN11_INT_TYPE_LSB 7
-#define GPIO_PIN11_INT_TYPE_MASK 0x00000380
-#define GPIO_PIN11_INT_TYPE_GET(x) (((x) & GPIO_PIN11_INT_TYPE_MASK) >> GPIO_PIN11_INT_TYPE_LSB)
-#define GPIO_PIN11_INT_TYPE_SET(x) (((x) << GPIO_PIN11_INT_TYPE_LSB) & GPIO_PIN11_INT_TYPE_MASK)
-#define GPIO_PIN11_PAD_DRIVER_MSB 2
-#define GPIO_PIN11_PAD_DRIVER_LSB 2
-#define GPIO_PIN11_PAD_DRIVER_MASK 0x00000004
-#define GPIO_PIN11_PAD_DRIVER_GET(x) (((x) & GPIO_PIN11_PAD_DRIVER_MASK) >> GPIO_PIN11_PAD_DRIVER_LSB)
-#define GPIO_PIN11_PAD_DRIVER_SET(x) (((x) << GPIO_PIN11_PAD_DRIVER_LSB) & GPIO_PIN11_PAD_DRIVER_MASK)
-#define GPIO_PIN11_SOURCE_MSB 0
-#define GPIO_PIN11_SOURCE_LSB 0
-#define GPIO_PIN11_SOURCE_MASK 0x00000001
-#define GPIO_PIN11_SOURCE_GET(x) (((x) & GPIO_PIN11_SOURCE_MASK) >> GPIO_PIN11_SOURCE_LSB)
-#define GPIO_PIN11_SOURCE_SET(x) (((x) << GPIO_PIN11_SOURCE_LSB) & GPIO_PIN11_SOURCE_MASK)
-
-#define GPIO_PIN12_ADDRESS 0x00000058
-#define GPIO_PIN12_OFFSET 0x00000058
-#define GPIO_PIN12_CONFIG_MSB 12
-#define GPIO_PIN12_CONFIG_LSB 11
-#define GPIO_PIN12_CONFIG_MASK 0x00001800
-#define GPIO_PIN12_CONFIG_GET(x) (((x) & GPIO_PIN12_CONFIG_MASK) >> GPIO_PIN12_CONFIG_LSB)
-#define GPIO_PIN12_CONFIG_SET(x) (((x) << GPIO_PIN12_CONFIG_LSB) & GPIO_PIN12_CONFIG_MASK)
-#define GPIO_PIN12_WAKEUP_ENABLE_MSB 10
-#define GPIO_PIN12_WAKEUP_ENABLE_LSB 10
-#define GPIO_PIN12_WAKEUP_ENABLE_MASK 0x00000400
-#define GPIO_PIN12_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN12_WAKEUP_ENABLE_MASK) >> GPIO_PIN12_WAKEUP_ENABLE_LSB)
-#define GPIO_PIN12_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN12_WAKEUP_ENABLE_LSB) & GPIO_PIN12_WAKEUP_ENABLE_MASK)
-#define GPIO_PIN12_INT_TYPE_MSB 9
-#define GPIO_PIN12_INT_TYPE_LSB 7
-#define GPIO_PIN12_INT_TYPE_MASK 0x00000380
-#define GPIO_PIN12_INT_TYPE_GET(x) (((x) & GPIO_PIN12_INT_TYPE_MASK) >> GPIO_PIN12_INT_TYPE_LSB)
-#define GPIO_PIN12_INT_TYPE_SET(x) (((x) << GPIO_PIN12_INT_TYPE_LSB) & GPIO_PIN12_INT_TYPE_MASK)
-#define GPIO_PIN12_PAD_DRIVER_MSB 2
-#define GPIO_PIN12_PAD_DRIVER_LSB 2
-#define GPIO_PIN12_PAD_DRIVER_MASK 0x00000004
-#define GPIO_PIN12_PAD_DRIVER_GET(x) (((x) & GPIO_PIN12_PAD_DRIVER_MASK) >> GPIO_PIN12_PAD_DRIVER_LSB)
-#define GPIO_PIN12_PAD_DRIVER_SET(x) (((x) << GPIO_PIN12_PAD_DRIVER_LSB) & GPIO_PIN12_PAD_DRIVER_MASK)
-#define GPIO_PIN12_SOURCE_MSB 0
-#define GPIO_PIN12_SOURCE_LSB 0
-#define GPIO_PIN12_SOURCE_MASK 0x00000001
-#define GPIO_PIN12_SOURCE_GET(x) (((x) & GPIO_PIN12_SOURCE_MASK) >> GPIO_PIN12_SOURCE_LSB)
-#define GPIO_PIN12_SOURCE_SET(x) (((x) << GPIO_PIN12_SOURCE_LSB) & GPIO_PIN12_SOURCE_MASK)
-
-#define GPIO_PIN13_ADDRESS 0x0000005c
-#define GPIO_PIN13_OFFSET 0x0000005c
-#define GPIO_PIN13_CONFIG_MSB 12
-#define GPIO_PIN13_CONFIG_LSB 11
-#define GPIO_PIN13_CONFIG_MASK 0x00001800
-#define GPIO_PIN13_CONFIG_GET(x) (((x) & GPIO_PIN13_CONFIG_MASK) >> GPIO_PIN13_CONFIG_LSB)
-#define GPIO_PIN13_CONFIG_SET(x) (((x) << GPIO_PIN13_CONFIG_LSB) & GPIO_PIN13_CONFIG_MASK)
-#define GPIO_PIN13_WAKEUP_ENABLE_MSB 10
-#define GPIO_PIN13_WAKEUP_ENABLE_LSB 10
-#define GPIO_PIN13_WAKEUP_ENABLE_MASK 0x00000400
-#define GPIO_PIN13_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN13_WAKEUP_ENABLE_MASK) >> GPIO_PIN13_WAKEUP_ENABLE_LSB)
-#define GPIO_PIN13_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN13_WAKEUP_ENABLE_LSB) & GPIO_PIN13_WAKEUP_ENABLE_MASK)
-#define GPIO_PIN13_INT_TYPE_MSB 9
-#define GPIO_PIN13_INT_TYPE_LSB 7
-#define GPIO_PIN13_INT_TYPE_MASK 0x00000380
-#define GPIO_PIN13_INT_TYPE_GET(x) (((x) & GPIO_PIN13_INT_TYPE_MASK) >> GPIO_PIN13_INT_TYPE_LSB)
-#define GPIO_PIN13_INT_TYPE_SET(x) (((x) << GPIO_PIN13_INT_TYPE_LSB) & GPIO_PIN13_INT_TYPE_MASK)
-#define GPIO_PIN13_PAD_DRIVER_MSB 2
-#define GPIO_PIN13_PAD_DRIVER_LSB 2
-#define GPIO_PIN13_PAD_DRIVER_MASK 0x00000004
-#define GPIO_PIN13_PAD_DRIVER_GET(x) (((x) & GPIO_PIN13_PAD_DRIVER_MASK) >> GPIO_PIN13_PAD_DRIVER_LSB)
-#define GPIO_PIN13_PAD_DRIVER_SET(x) (((x) << GPIO_PIN13_PAD_DRIVER_LSB) & GPIO_PIN13_PAD_DRIVER_MASK)
-#define GPIO_PIN13_SOURCE_MSB 0
-#define GPIO_PIN13_SOURCE_LSB 0
-#define GPIO_PIN13_SOURCE_MASK 0x00000001
-#define GPIO_PIN13_SOURCE_GET(x) (((x) & GPIO_PIN13_SOURCE_MASK) >> GPIO_PIN13_SOURCE_LSB)
-#define GPIO_PIN13_SOURCE_SET(x) (((x) << GPIO_PIN13_SOURCE_LSB) & GPIO_PIN13_SOURCE_MASK)
-
-#define GPIO_PIN14_ADDRESS 0x00000060
-#define GPIO_PIN14_OFFSET 0x00000060
-#define GPIO_PIN14_CONFIG_MSB 12
-#define GPIO_PIN14_CONFIG_LSB 11
-#define GPIO_PIN14_CONFIG_MASK 0x00001800
-#define GPIO_PIN14_CONFIG_GET(x) (((x) & GPIO_PIN14_CONFIG_MASK) >> GPIO_PIN14_CONFIG_LSB)
-#define GPIO_PIN14_CONFIG_SET(x) (((x) << GPIO_PIN14_CONFIG_LSB) & GPIO_PIN14_CONFIG_MASK)
-#define GPIO_PIN14_WAKEUP_ENABLE_MSB 10
-#define GPIO_PIN14_WAKEUP_ENABLE_LSB 10
-#define GPIO_PIN14_WAKEUP_ENABLE_MASK 0x00000400
-#define GPIO_PIN14_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN14_WAKEUP_ENABLE_MASK) >> GPIO_PIN14_WAKEUP_ENABLE_LSB)
-#define GPIO_PIN14_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN14_WAKEUP_ENABLE_LSB) & GPIO_PIN14_WAKEUP_ENABLE_MASK)
-#define GPIO_PIN14_INT_TYPE_MSB 9
-#define GPIO_PIN14_INT_TYPE_LSB 7
-#define GPIO_PIN14_INT_TYPE_MASK 0x00000380
-#define GPIO_PIN14_INT_TYPE_GET(x) (((x) & GPIO_PIN14_INT_TYPE_MASK) >> GPIO_PIN14_INT_TYPE_LSB)
-#define GPIO_PIN14_INT_TYPE_SET(x) (((x) << GPIO_PIN14_INT_TYPE_LSB) & GPIO_PIN14_INT_TYPE_MASK)
-#define GPIO_PIN14_PAD_DRIVER_MSB 2
-#define GPIO_PIN14_PAD_DRIVER_LSB 2
-#define GPIO_PIN14_PAD_DRIVER_MASK 0x00000004
-#define GPIO_PIN14_PAD_DRIVER_GET(x) (((x) & GPIO_PIN14_PAD_DRIVER_MASK) >> GPIO_PIN14_PAD_DRIVER_LSB)
-#define GPIO_PIN14_PAD_DRIVER_SET(x) (((x) << GPIO_PIN14_PAD_DRIVER_LSB) & GPIO_PIN14_PAD_DRIVER_MASK)
-#define GPIO_PIN14_SOURCE_MSB 0
-#define GPIO_PIN14_SOURCE_LSB 0
-#define GPIO_PIN14_SOURCE_MASK 0x00000001
-#define GPIO_PIN14_SOURCE_GET(x) (((x) & GPIO_PIN14_SOURCE_MASK) >> GPIO_PIN14_SOURCE_LSB)
-#define GPIO_PIN14_SOURCE_SET(x) (((x) << GPIO_PIN14_SOURCE_LSB) & GPIO_PIN14_SOURCE_MASK)
-
-#define GPIO_PIN15_ADDRESS 0x00000064
-#define GPIO_PIN15_OFFSET 0x00000064
-#define GPIO_PIN15_CONFIG_MSB 12
-#define GPIO_PIN15_CONFIG_LSB 11
-#define GPIO_PIN15_CONFIG_MASK 0x00001800
-#define GPIO_PIN15_CONFIG_GET(x) (((x) & GPIO_PIN15_CONFIG_MASK) >> GPIO_PIN15_CONFIG_LSB)
-#define GPIO_PIN15_CONFIG_SET(x) (((x) << GPIO_PIN15_CONFIG_LSB) & GPIO_PIN15_CONFIG_MASK)
-#define GPIO_PIN15_WAKEUP_ENABLE_MSB 10
-#define GPIO_PIN15_WAKEUP_ENABLE_LSB 10
-#define GPIO_PIN15_WAKEUP_ENABLE_MASK 0x00000400
-#define GPIO_PIN15_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN15_WAKEUP_ENABLE_MASK) >> GPIO_PIN15_WAKEUP_ENABLE_LSB)
-#define GPIO_PIN15_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN15_WAKEUP_ENABLE_LSB) & GPIO_PIN15_WAKEUP_ENABLE_MASK)
-#define GPIO_PIN15_INT_TYPE_MSB 9
-#define GPIO_PIN15_INT_TYPE_LSB 7
-#define GPIO_PIN15_INT_TYPE_MASK 0x00000380
-#define GPIO_PIN15_INT_TYPE_GET(x) (((x) & GPIO_PIN15_INT_TYPE_MASK) >> GPIO_PIN15_INT_TYPE_LSB)
-#define GPIO_PIN15_INT_TYPE_SET(x) (((x) << GPIO_PIN15_INT_TYPE_LSB) & GPIO_PIN15_INT_TYPE_MASK)
-#define GPIO_PIN15_PAD_DRIVER_MSB 2
-#define GPIO_PIN15_PAD_DRIVER_LSB 2
-#define GPIO_PIN15_PAD_DRIVER_MASK 0x00000004
-#define GPIO_PIN15_PAD_DRIVER_GET(x) (((x) & GPIO_PIN15_PAD_DRIVER_MASK) >> GPIO_PIN15_PAD_DRIVER_LSB)
-#define GPIO_PIN15_PAD_DRIVER_SET(x) (((x) << GPIO_PIN15_PAD_DRIVER_LSB) & GPIO_PIN15_PAD_DRIVER_MASK)
-#define GPIO_PIN15_SOURCE_MSB 0
-#define GPIO_PIN15_SOURCE_LSB 0
-#define GPIO_PIN15_SOURCE_MASK 0x00000001
-#define GPIO_PIN15_SOURCE_GET(x) (((x) & GPIO_PIN15_SOURCE_MASK) >> GPIO_PIN15_SOURCE_LSB)
-#define GPIO_PIN15_SOURCE_SET(x) (((x) << GPIO_PIN15_SOURCE_LSB) & GPIO_PIN15_SOURCE_MASK)
-
-#define GPIO_PIN16_ADDRESS 0x00000068
-#define GPIO_PIN16_OFFSET 0x00000068
-#define GPIO_PIN16_CONFIG_MSB 12
-#define GPIO_PIN16_CONFIG_LSB 11
-#define GPIO_PIN16_CONFIG_MASK 0x00001800
-#define GPIO_PIN16_CONFIG_GET(x) (((x) & GPIO_PIN16_CONFIG_MASK) >> GPIO_PIN16_CONFIG_LSB)
-#define GPIO_PIN16_CONFIG_SET(x) (((x) << GPIO_PIN16_CONFIG_LSB) & GPIO_PIN16_CONFIG_MASK)
-#define GPIO_PIN16_WAKEUP_ENABLE_MSB 10
-#define GPIO_PIN16_WAKEUP_ENABLE_LSB 10
-#define GPIO_PIN16_WAKEUP_ENABLE_MASK 0x00000400
-#define GPIO_PIN16_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN16_WAKEUP_ENABLE_MASK) >> GPIO_PIN16_WAKEUP_ENABLE_LSB)
-#define GPIO_PIN16_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN16_WAKEUP_ENABLE_LSB) & GPIO_PIN16_WAKEUP_ENABLE_MASK)
-#define GPIO_PIN16_INT_TYPE_MSB 9
-#define GPIO_PIN16_INT_TYPE_LSB 7
-#define GPIO_PIN16_INT_TYPE_MASK 0x00000380
-#define GPIO_PIN16_INT_TYPE_GET(x) (((x) & GPIO_PIN16_INT_TYPE_MASK) >> GPIO_PIN16_INT_TYPE_LSB)
-#define GPIO_PIN16_INT_TYPE_SET(x) (((x) << GPIO_PIN16_INT_TYPE_LSB) & GPIO_PIN16_INT_TYPE_MASK)
-#define GPIO_PIN16_PAD_DRIVER_MSB 2
-#define GPIO_PIN16_PAD_DRIVER_LSB 2
-#define GPIO_PIN16_PAD_DRIVER_MASK 0x00000004
-#define GPIO_PIN16_PAD_DRIVER_GET(x) (((x) & GPIO_PIN16_PAD_DRIVER_MASK) >> GPIO_PIN16_PAD_DRIVER_LSB)
-#define GPIO_PIN16_PAD_DRIVER_SET(x) (((x) << GPIO_PIN16_PAD_DRIVER_LSB) & GPIO_PIN16_PAD_DRIVER_MASK)
-#define GPIO_PIN16_SOURCE_MSB 0
-#define GPIO_PIN16_SOURCE_LSB 0
-#define GPIO_PIN16_SOURCE_MASK 0x00000001
-#define GPIO_PIN16_SOURCE_GET(x) (((x) & GPIO_PIN16_SOURCE_MASK) >> GPIO_PIN16_SOURCE_LSB)
-#define GPIO_PIN16_SOURCE_SET(x) (((x) << GPIO_PIN16_SOURCE_LSB) & GPIO_PIN16_SOURCE_MASK)
-
-#define GPIO_PIN17_ADDRESS 0x0000006c
-#define GPIO_PIN17_OFFSET 0x0000006c
-#define GPIO_PIN17_CONFIG_MSB 12
-#define GPIO_PIN17_CONFIG_LSB 11
-#define GPIO_PIN17_CONFIG_MASK 0x00001800
-#define GPIO_PIN17_CONFIG_GET(x) (((x) & GPIO_PIN17_CONFIG_MASK) >> GPIO_PIN17_CONFIG_LSB)
-#define GPIO_PIN17_CONFIG_SET(x) (((x) << GPIO_PIN17_CONFIG_LSB) & GPIO_PIN17_CONFIG_MASK)
-#define GPIO_PIN17_WAKEUP_ENABLE_MSB 10
-#define GPIO_PIN17_WAKEUP_ENABLE_LSB 10
-#define GPIO_PIN17_WAKEUP_ENABLE_MASK 0x00000400
-#define GPIO_PIN17_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN17_WAKEUP_ENABLE_MASK) >> GPIO_PIN17_WAKEUP_ENABLE_LSB)
-#define GPIO_PIN17_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN17_WAKEUP_ENABLE_LSB) & GPIO_PIN17_WAKEUP_ENABLE_MASK)
-#define GPIO_PIN17_INT_TYPE_MSB 9
-#define GPIO_PIN17_INT_TYPE_LSB 7
-#define GPIO_PIN17_INT_TYPE_MASK 0x00000380
-#define GPIO_PIN17_INT_TYPE_GET(x) (((x) & GPIO_PIN17_INT_TYPE_MASK) >> GPIO_PIN17_INT_TYPE_LSB)
-#define GPIO_PIN17_INT_TYPE_SET(x) (((x) << GPIO_PIN17_INT_TYPE_LSB) & GPIO_PIN17_INT_TYPE_MASK)
-#define GPIO_PIN17_PAD_DRIVER_MSB 2
-#define GPIO_PIN17_PAD_DRIVER_LSB 2
-#define GPIO_PIN17_PAD_DRIVER_MASK 0x00000004
-#define GPIO_PIN17_PAD_DRIVER_GET(x) (((x) & GPIO_PIN17_PAD_DRIVER_MASK) >> GPIO_PIN17_PAD_DRIVER_LSB)
-#define GPIO_PIN17_PAD_DRIVER_SET(x) (((x) << GPIO_PIN17_PAD_DRIVER_LSB) & GPIO_PIN17_PAD_DRIVER_MASK)
-#define GPIO_PIN17_SOURCE_MSB 0
-#define GPIO_PIN17_SOURCE_LSB 0
-#define GPIO_PIN17_SOURCE_MASK 0x00000001
-#define GPIO_PIN17_SOURCE_GET(x) (((x) & GPIO_PIN17_SOURCE_MASK) >> GPIO_PIN17_SOURCE_LSB)
-#define GPIO_PIN17_SOURCE_SET(x) (((x) << GPIO_PIN17_SOURCE_LSB) & GPIO_PIN17_SOURCE_MASK)
-
-#define SDIO_PIN_ADDRESS 0x00000070
-#define SDIO_PIN_OFFSET 0x00000070
-#define SDIO_PIN_PAD_PULL_MSB 3
-#define SDIO_PIN_PAD_PULL_LSB 2
-#define SDIO_PIN_PAD_PULL_MASK 0x0000000c
-#define SDIO_PIN_PAD_PULL_GET(x) (((x) & SDIO_PIN_PAD_PULL_MASK) >> SDIO_PIN_PAD_PULL_LSB)
-#define SDIO_PIN_PAD_PULL_SET(x) (((x) << SDIO_PIN_PAD_PULL_LSB) & SDIO_PIN_PAD_PULL_MASK)
-#define SDIO_PIN_PAD_STRENGTH_MSB 1
-#define SDIO_PIN_PAD_STRENGTH_LSB 0
-#define SDIO_PIN_PAD_STRENGTH_MASK 0x00000003
-#define SDIO_PIN_PAD_STRENGTH_GET(x) (((x) & SDIO_PIN_PAD_STRENGTH_MASK) >> SDIO_PIN_PAD_STRENGTH_LSB)
-#define SDIO_PIN_PAD_STRENGTH_SET(x) (((x) << SDIO_PIN_PAD_STRENGTH_LSB) & SDIO_PIN_PAD_STRENGTH_MASK)
-
-#define CLK_REQ_PIN_ADDRESS 0x00000074
-#define CLK_REQ_PIN_OFFSET 0x00000074
-#define CLK_REQ_PIN_ATE_OE_L_MSB 4
-#define CLK_REQ_PIN_ATE_OE_L_LSB 4
-#define CLK_REQ_PIN_ATE_OE_L_MASK 0x00000010
-#define CLK_REQ_PIN_ATE_OE_L_GET(x) (((x) & CLK_REQ_PIN_ATE_OE_L_MASK) >> CLK_REQ_PIN_ATE_OE_L_LSB)
-#define CLK_REQ_PIN_ATE_OE_L_SET(x) (((x) << CLK_REQ_PIN_ATE_OE_L_LSB) & CLK_REQ_PIN_ATE_OE_L_MASK)
-#define CLK_REQ_PIN_PAD_PULL_MSB 3
-#define CLK_REQ_PIN_PAD_PULL_LSB 2
-#define CLK_REQ_PIN_PAD_PULL_MASK 0x0000000c
-#define CLK_REQ_PIN_PAD_PULL_GET(x) (((x) & CLK_REQ_PIN_PAD_PULL_MASK) >> CLK_REQ_PIN_PAD_PULL_LSB)
-#define CLK_REQ_PIN_PAD_PULL_SET(x) (((x) << CLK_REQ_PIN_PAD_PULL_LSB) & CLK_REQ_PIN_PAD_PULL_MASK)
-#define CLK_REQ_PIN_PAD_STRENGTH_MSB 1
-#define CLK_REQ_PIN_PAD_STRENGTH_LSB 0
-#define CLK_REQ_PIN_PAD_STRENGTH_MASK 0x00000003
-#define CLK_REQ_PIN_PAD_STRENGTH_GET(x) (((x) & CLK_REQ_PIN_PAD_STRENGTH_MASK) >> CLK_REQ_PIN_PAD_STRENGTH_LSB)
-#define CLK_REQ_PIN_PAD_STRENGTH_SET(x) (((x) << CLK_REQ_PIN_PAD_STRENGTH_LSB) & CLK_REQ_PIN_PAD_STRENGTH_MASK)
-
-#define SIGMA_DELTA_ADDRESS 0x00000078
-#define SIGMA_DELTA_OFFSET 0x00000078
-#define SIGMA_DELTA_ENABLE_MSB 16
-#define SIGMA_DELTA_ENABLE_LSB 16
-#define SIGMA_DELTA_ENABLE_MASK 0x00010000
-#define SIGMA_DELTA_ENABLE_GET(x) (((x) & SIGMA_DELTA_ENABLE_MASK) >> SIGMA_DELTA_ENABLE_LSB)
-#define SIGMA_DELTA_ENABLE_SET(x) (((x) << SIGMA_DELTA_ENABLE_LSB) & SIGMA_DELTA_ENABLE_MASK)
-#define SIGMA_DELTA_PRESCALAR_MSB 15
-#define SIGMA_DELTA_PRESCALAR_LSB 8
-#define SIGMA_DELTA_PRESCALAR_MASK 0x0000ff00
-#define SIGMA_DELTA_PRESCALAR_GET(x) (((x) & SIGMA_DELTA_PRESCALAR_MASK) >> SIGMA_DELTA_PRESCALAR_LSB)
-#define SIGMA_DELTA_PRESCALAR_SET(x) (((x) << SIGMA_DELTA_PRESCALAR_LSB) & SIGMA_DELTA_PRESCALAR_MASK)
-#define SIGMA_DELTA_TARGET_MSB 7
-#define SIGMA_DELTA_TARGET_LSB 0
-#define SIGMA_DELTA_TARGET_MASK 0x000000ff
-#define SIGMA_DELTA_TARGET_GET(x) (((x) & SIGMA_DELTA_TARGET_MASK) >> SIGMA_DELTA_TARGET_LSB)
-#define SIGMA_DELTA_TARGET_SET(x) (((x) << SIGMA_DELTA_TARGET_LSB) & SIGMA_DELTA_TARGET_MASK)
-
-#define DEBUG_CONTROL_ADDRESS 0x0000007c
-#define DEBUG_CONTROL_OFFSET 0x0000007c
-#define DEBUG_CONTROL_OBS_OE_L_MSB 1
-#define DEBUG_CONTROL_OBS_OE_L_LSB 1
-#define DEBUG_CONTROL_OBS_OE_L_MASK 0x00000002
-#define DEBUG_CONTROL_OBS_OE_L_GET(x) (((x) & DEBUG_CONTROL_OBS_OE_L_MASK) >> DEBUG_CONTROL_OBS_OE_L_LSB)
-#define DEBUG_CONTROL_OBS_OE_L_SET(x) (((x) << DEBUG_CONTROL_OBS_OE_L_LSB) & DEBUG_CONTROL_OBS_OE_L_MASK)
-#define DEBUG_CONTROL_ENABLE_MSB 0
-#define DEBUG_CONTROL_ENABLE_LSB 0
-#define DEBUG_CONTROL_ENABLE_MASK 0x00000001
-#define DEBUG_CONTROL_ENABLE_GET(x) (((x) & DEBUG_CONTROL_ENABLE_MASK) >> DEBUG_CONTROL_ENABLE_LSB)
-#define DEBUG_CONTROL_ENABLE_SET(x) (((x) << DEBUG_CONTROL_ENABLE_LSB) & DEBUG_CONTROL_ENABLE_MASK)
-
-#define DEBUG_INPUT_SEL_ADDRESS 0x00000080
-#define DEBUG_INPUT_SEL_OFFSET 0x00000080
-#define DEBUG_INPUT_SEL_SRC_MSB 3
-#define DEBUG_INPUT_SEL_SRC_LSB 0
-#define DEBUG_INPUT_SEL_SRC_MASK 0x0000000f
-#define DEBUG_INPUT_SEL_SRC_GET(x) (((x) & DEBUG_INPUT_SEL_SRC_MASK) >> DEBUG_INPUT_SEL_SRC_LSB)
-#define DEBUG_INPUT_SEL_SRC_SET(x) (((x) << DEBUG_INPUT_SEL_SRC_LSB) & DEBUG_INPUT_SEL_SRC_MASK)
-
-#define DEBUG_OUT_ADDRESS 0x00000084
-#define DEBUG_OUT_OFFSET 0x00000084
-#define DEBUG_OUT_DATA_MSB 17
-#define DEBUG_OUT_DATA_LSB 0
-#define DEBUG_OUT_DATA_MASK 0x0003ffff
-#define DEBUG_OUT_DATA_GET(x) (((x) & DEBUG_OUT_DATA_MASK) >> DEBUG_OUT_DATA_LSB)
-#define DEBUG_OUT_DATA_SET(x) (((x) << DEBUG_OUT_DATA_LSB) & DEBUG_OUT_DATA_MASK)
-
-#define LA_CONTROL_ADDRESS 0x00000088
-#define LA_CONTROL_OFFSET 0x00000088
-#define LA_CONTROL_RUN_MSB 1
-#define LA_CONTROL_RUN_LSB 1
-#define LA_CONTROL_RUN_MASK 0x00000002
-#define LA_CONTROL_RUN_GET(x) (((x) & LA_CONTROL_RUN_MASK) >> LA_CONTROL_RUN_LSB)
-#define LA_CONTROL_RUN_SET(x) (((x) << LA_CONTROL_RUN_LSB) & LA_CONTROL_RUN_MASK)
-#define LA_CONTROL_TRIGGERED_MSB 0
-#define LA_CONTROL_TRIGGERED_LSB 0
-#define LA_CONTROL_TRIGGERED_MASK 0x00000001
-#define LA_CONTROL_TRIGGERED_GET(x) (((x) & LA_CONTROL_TRIGGERED_MASK) >> LA_CONTROL_TRIGGERED_LSB)
-#define LA_CONTROL_TRIGGERED_SET(x) (((x) << LA_CONTROL_TRIGGERED_LSB) & LA_CONTROL_TRIGGERED_MASK)
-
-#define LA_CLOCK_ADDRESS 0x0000008c
-#define LA_CLOCK_OFFSET 0x0000008c
-#define LA_CLOCK_DIV_MSB 7
-#define LA_CLOCK_DIV_LSB 0
-#define LA_CLOCK_DIV_MASK 0x000000ff
-#define LA_CLOCK_DIV_GET(x) (((x) & LA_CLOCK_DIV_MASK) >> LA_CLOCK_DIV_LSB)
-#define LA_CLOCK_DIV_SET(x) (((x) << LA_CLOCK_DIV_LSB) & LA_CLOCK_DIV_MASK)
-
-#define LA_STATUS_ADDRESS 0x00000090
-#define LA_STATUS_OFFSET 0x00000090
-#define LA_STATUS_INTERRUPT_MSB 0
-#define LA_STATUS_INTERRUPT_LSB 0
-#define LA_STATUS_INTERRUPT_MASK 0x00000001
-#define LA_STATUS_INTERRUPT_GET(x) (((x) & LA_STATUS_INTERRUPT_MASK) >> LA_STATUS_INTERRUPT_LSB)
-#define LA_STATUS_INTERRUPT_SET(x) (((x) << LA_STATUS_INTERRUPT_LSB) & LA_STATUS_INTERRUPT_MASK)
-
-#define LA_TRIGGER_SAMPLE_ADDRESS 0x00000094
-#define LA_TRIGGER_SAMPLE_OFFSET 0x00000094
-#define LA_TRIGGER_SAMPLE_COUNT_MSB 15
-#define LA_TRIGGER_SAMPLE_COUNT_LSB 0
-#define LA_TRIGGER_SAMPLE_COUNT_MASK 0x0000ffff
-#define LA_TRIGGER_SAMPLE_COUNT_GET(x) (((x) & LA_TRIGGER_SAMPLE_COUNT_MASK) >> LA_TRIGGER_SAMPLE_COUNT_LSB)
-#define LA_TRIGGER_SAMPLE_COUNT_SET(x) (((x) << LA_TRIGGER_SAMPLE_COUNT_LSB) & LA_TRIGGER_SAMPLE_COUNT_MASK)
-
-#define LA_TRIGGER_POSITION_ADDRESS 0x00000098
-#define LA_TRIGGER_POSITION_OFFSET 0x00000098
-#define LA_TRIGGER_POSITION_VALUE_MSB 15
-#define LA_TRIGGER_POSITION_VALUE_LSB 0
-#define LA_TRIGGER_POSITION_VALUE_MASK 0x0000ffff
-#define LA_TRIGGER_POSITION_VALUE_GET(x) (((x) & LA_TRIGGER_POSITION_VALUE_MASK) >> LA_TRIGGER_POSITION_VALUE_LSB)
-#define LA_TRIGGER_POSITION_VALUE_SET(x) (((x) << LA_TRIGGER_POSITION_VALUE_LSB) & LA_TRIGGER_POSITION_VALUE_MASK)
-
-#define LA_PRE_TRIGGER_ADDRESS 0x0000009c
-#define LA_PRE_TRIGGER_OFFSET 0x0000009c
-#define LA_PRE_TRIGGER_COUNT_MSB 15
-#define LA_PRE_TRIGGER_COUNT_LSB 0
-#define LA_PRE_TRIGGER_COUNT_MASK 0x0000ffff
-#define LA_PRE_TRIGGER_COUNT_GET(x) (((x) & LA_PRE_TRIGGER_COUNT_MASK) >> LA_PRE_TRIGGER_COUNT_LSB)
-#define LA_PRE_TRIGGER_COUNT_SET(x) (((x) << LA_PRE_TRIGGER_COUNT_LSB) & LA_PRE_TRIGGER_COUNT_MASK)
-
-#define LA_POST_TRIGGER_ADDRESS 0x000000a0
-#define LA_POST_TRIGGER_OFFSET 0x000000a0
-#define LA_POST_TRIGGER_COUNT_MSB 15
-#define LA_POST_TRIGGER_COUNT_LSB 0
-#define LA_POST_TRIGGER_COUNT_MASK 0x0000ffff
-#define LA_POST_TRIGGER_COUNT_GET(x) (((x) & LA_POST_TRIGGER_COUNT_MASK) >> LA_POST_TRIGGER_COUNT_LSB)
-#define LA_POST_TRIGGER_COUNT_SET(x) (((x) << LA_POST_TRIGGER_COUNT_LSB) & LA_POST_TRIGGER_COUNT_MASK)
-
-#define LA_FILTER_CONTROL_ADDRESS 0x000000a4
-#define LA_FILTER_CONTROL_OFFSET 0x000000a4
-#define LA_FILTER_CONTROL_DELTA_MSB 0
-#define LA_FILTER_CONTROL_DELTA_LSB 0
-#define LA_FILTER_CONTROL_DELTA_MASK 0x00000001
-#define LA_FILTER_CONTROL_DELTA_GET(x) (((x) & LA_FILTER_CONTROL_DELTA_MASK) >> LA_FILTER_CONTROL_DELTA_LSB)
-#define LA_FILTER_CONTROL_DELTA_SET(x) (((x) << LA_FILTER_CONTROL_DELTA_LSB) & LA_FILTER_CONTROL_DELTA_MASK)
-
-#define LA_FILTER_DATA_ADDRESS 0x000000a8
-#define LA_FILTER_DATA_OFFSET 0x000000a8
-#define LA_FILTER_DATA_MATCH_MSB 17
-#define LA_FILTER_DATA_MATCH_LSB 0
-#define LA_FILTER_DATA_MATCH_MASK 0x0003ffff
-#define LA_FILTER_DATA_MATCH_GET(x) (((x) & LA_FILTER_DATA_MATCH_MASK) >> LA_FILTER_DATA_MATCH_LSB)
-#define LA_FILTER_DATA_MATCH_SET(x) (((x) << LA_FILTER_DATA_MATCH_LSB) & LA_FILTER_DATA_MATCH_MASK)
-
-#define LA_FILTER_WILDCARD_ADDRESS 0x000000ac
-#define LA_FILTER_WILDCARD_OFFSET 0x000000ac
-#define LA_FILTER_WILDCARD_MATCH_MSB 17
-#define LA_FILTER_WILDCARD_MATCH_LSB 0
-#define LA_FILTER_WILDCARD_MATCH_MASK 0x0003ffff
-#define LA_FILTER_WILDCARD_MATCH_GET(x) (((x) & LA_FILTER_WILDCARD_MATCH_MASK) >> LA_FILTER_WILDCARD_MATCH_LSB)
-#define LA_FILTER_WILDCARD_MATCH_SET(x) (((x) << LA_FILTER_WILDCARD_MATCH_LSB) & LA_FILTER_WILDCARD_MATCH_MASK)
-
-#define LA_TRIGGERA_DATA_ADDRESS 0x000000b0
-#define LA_TRIGGERA_DATA_OFFSET 0x000000b0
-#define LA_TRIGGERA_DATA_MATCH_MSB 17
-#define LA_TRIGGERA_DATA_MATCH_LSB 0
-#define LA_TRIGGERA_DATA_MATCH_MASK 0x0003ffff
-#define LA_TRIGGERA_DATA_MATCH_GET(x) (((x) & LA_TRIGGERA_DATA_MATCH_MASK) >> LA_TRIGGERA_DATA_MATCH_LSB)
-#define LA_TRIGGERA_DATA_MATCH_SET(x) (((x) << LA_TRIGGERA_DATA_MATCH_LSB) & LA_TRIGGERA_DATA_MATCH_MASK)
-
-#define LA_TRIGGERA_WILDCARD_ADDRESS 0x000000b4
-#define LA_TRIGGERA_WILDCARD_OFFSET 0x000000b4
-#define LA_TRIGGERA_WILDCARD_MATCH_MSB 17
-#define LA_TRIGGERA_WILDCARD_MATCH_LSB 0
-#define LA_TRIGGERA_WILDCARD_MATCH_MASK 0x0003ffff
-#define LA_TRIGGERA_WILDCARD_MATCH_GET(x) (((x) & LA_TRIGGERA_WILDCARD_MATCH_MASK) >> LA_TRIGGERA_WILDCARD_MATCH_LSB)
-#define LA_TRIGGERA_WILDCARD_MATCH_SET(x) (((x) << LA_TRIGGERA_WILDCARD_MATCH_LSB) & LA_TRIGGERA_WILDCARD_MATCH_MASK)
-
-#define LA_TRIGGERB_DATA_ADDRESS 0x000000b8
-#define LA_TRIGGERB_DATA_OFFSET 0x000000b8
-#define LA_TRIGGERB_DATA_MATCH_MSB 17
-#define LA_TRIGGERB_DATA_MATCH_LSB 0
-#define LA_TRIGGERB_DATA_MATCH_MASK 0x0003ffff
-#define LA_TRIGGERB_DATA_MATCH_GET(x) (((x) & LA_TRIGGERB_DATA_MATCH_MASK) >> LA_TRIGGERB_DATA_MATCH_LSB)
-#define LA_TRIGGERB_DATA_MATCH_SET(x) (((x) << LA_TRIGGERB_DATA_MATCH_LSB) & LA_TRIGGERB_DATA_MATCH_MASK)
-
-#define LA_TRIGGERB_WILDCARD_ADDRESS 0x000000bc
-#define LA_TRIGGERB_WILDCARD_OFFSET 0x000000bc
-#define LA_TRIGGERB_WILDCARD_MATCH_MSB 17
-#define LA_TRIGGERB_WILDCARD_MATCH_LSB 0
-#define LA_TRIGGERB_WILDCARD_MATCH_MASK 0x0003ffff
-#define LA_TRIGGERB_WILDCARD_MATCH_GET(x) (((x) & LA_TRIGGERB_WILDCARD_MATCH_MASK) >> LA_TRIGGERB_WILDCARD_MATCH_LSB)
-#define LA_TRIGGERB_WILDCARD_MATCH_SET(x) (((x) << LA_TRIGGERB_WILDCARD_MATCH_LSB) & LA_TRIGGERB_WILDCARD_MATCH_MASK)
-
-#define LA_TRIGGER_ADDRESS 0x000000c0
-#define LA_TRIGGER_OFFSET 0x000000c0
-#define LA_TRIGGER_EVENT_MSB 2
-#define LA_TRIGGER_EVENT_LSB 0
-#define LA_TRIGGER_EVENT_MASK 0x00000007
-#define LA_TRIGGER_EVENT_GET(x) (((x) & LA_TRIGGER_EVENT_MASK) >> LA_TRIGGER_EVENT_LSB)
-#define LA_TRIGGER_EVENT_SET(x) (((x) << LA_TRIGGER_EVENT_LSB) & LA_TRIGGER_EVENT_MASK)
-
-#define LA_FIFO_ADDRESS 0x000000c4
-#define LA_FIFO_OFFSET 0x000000c4
-#define LA_FIFO_FULL_MSB 1
-#define LA_FIFO_FULL_LSB 1
-#define LA_FIFO_FULL_MASK 0x00000002
-#define LA_FIFO_FULL_GET(x) (((x) & LA_FIFO_FULL_MASK) >> LA_FIFO_FULL_LSB)
-#define LA_FIFO_FULL_SET(x) (((x) << LA_FIFO_FULL_LSB) & LA_FIFO_FULL_MASK)
-#define LA_FIFO_EMPTY_MSB 0
-#define LA_FIFO_EMPTY_LSB 0
-#define LA_FIFO_EMPTY_MASK 0x00000001
-#define LA_FIFO_EMPTY_GET(x) (((x) & LA_FIFO_EMPTY_MASK) >> LA_FIFO_EMPTY_LSB)
-#define LA_FIFO_EMPTY_SET(x) (((x) << LA_FIFO_EMPTY_LSB) & LA_FIFO_EMPTY_MASK)
-
-#define LA_ADDRESS 0x000000c8
-#define LA_OFFSET 0x000000c8
-#define LA_DATA_MSB 17
-#define LA_DATA_LSB 0
-#define LA_DATA_MASK 0x0003ffff
-#define LA_DATA_GET(x) (((x) & LA_DATA_MASK) >> LA_DATA_LSB)
-#define LA_DATA_SET(x) (((x) << LA_DATA_LSB) & LA_DATA_MASK)
-
-#define ANT_PIN_ADDRESS 0x000000d0
-#define ANT_PIN_OFFSET 0x000000d0
-#define ANT_PIN_PAD_PULL_MSB 3
-#define ANT_PIN_PAD_PULL_LSB 2
-#define ANT_PIN_PAD_PULL_MASK 0x0000000c
-#define ANT_PIN_PAD_PULL_GET(x) (((x) & ANT_PIN_PAD_PULL_MASK) >> ANT_PIN_PAD_PULL_LSB)
-#define ANT_PIN_PAD_PULL_SET(x) (((x) << ANT_PIN_PAD_PULL_LSB) & ANT_PIN_PAD_PULL_MASK)
-#define ANT_PIN_PAD_STRENGTH_MSB 1
-#define ANT_PIN_PAD_STRENGTH_LSB 0
-#define ANT_PIN_PAD_STRENGTH_MASK 0x00000003
-#define ANT_PIN_PAD_STRENGTH_GET(x) (((x) & ANT_PIN_PAD_STRENGTH_MASK) >> ANT_PIN_PAD_STRENGTH_LSB)
-#define ANT_PIN_PAD_STRENGTH_SET(x) (((x) << ANT_PIN_PAD_STRENGTH_LSB) & ANT_PIN_PAD_STRENGTH_MASK)
-
-#define ANTD_PIN_ADDRESS 0x000000d4
-#define ANTD_PIN_OFFSET 0x000000d4
-#define ANTD_PIN_PAD_PULL_MSB 1
-#define ANTD_PIN_PAD_PULL_LSB 0
-#define ANTD_PIN_PAD_PULL_MASK 0x00000003
-#define ANTD_PIN_PAD_PULL_GET(x) (((x) & ANTD_PIN_PAD_PULL_MASK) >> ANTD_PIN_PAD_PULL_LSB)
-#define ANTD_PIN_PAD_PULL_SET(x) (((x) << ANTD_PIN_PAD_PULL_LSB) & ANTD_PIN_PAD_PULL_MASK)
-
-#define GPIO_PIN_ADDRESS 0x000000d8
-#define GPIO_PIN_OFFSET 0x000000d8
-#define GPIO_PIN_PAD_PULL_MSB 3
-#define GPIO_PIN_PAD_PULL_LSB 2
-#define GPIO_PIN_PAD_PULL_MASK 0x0000000c
-#define GPIO_PIN_PAD_PULL_GET(x) (((x) & GPIO_PIN_PAD_PULL_MASK) >> GPIO_PIN_PAD_PULL_LSB)
-#define GPIO_PIN_PAD_PULL_SET(x) (((x) << GPIO_PIN_PAD_PULL_LSB) & GPIO_PIN_PAD_PULL_MASK)
-#define GPIO_PIN_PAD_STRENGTH_MSB 1
-#define GPIO_PIN_PAD_STRENGTH_LSB 0
-#define GPIO_PIN_PAD_STRENGTH_MASK 0x00000003
-#define GPIO_PIN_PAD_STRENGTH_GET(x) (((x) & GPIO_PIN_PAD_STRENGTH_MASK) >> GPIO_PIN_PAD_STRENGTH_LSB)
-#define GPIO_PIN_PAD_STRENGTH_SET(x) (((x) << GPIO_PIN_PAD_STRENGTH_LSB) & GPIO_PIN_PAD_STRENGTH_MASK)
-
-#define GPIO_H_PIN_ADDRESS 0x000000dc
-#define GPIO_H_PIN_OFFSET 0x000000dc
-#define GPIO_H_PIN_PAD_PULL_MSB 1
-#define GPIO_H_PIN_PAD_PULL_LSB 0
-#define GPIO_H_PIN_PAD_PULL_MASK 0x00000003
-#define GPIO_H_PIN_PAD_PULL_GET(x) (((x) & GPIO_H_PIN_PAD_PULL_MASK) >> GPIO_H_PIN_PAD_PULL_LSB)
-#define GPIO_H_PIN_PAD_PULL_SET(x) (((x) << GPIO_H_PIN_PAD_PULL_LSB) & GPIO_H_PIN_PAD_PULL_MASK)
-
-#define BT_PIN_ADDRESS 0x000000e0
-#define BT_PIN_OFFSET 0x000000e0
-#define BT_PIN_PAD_PULL_MSB 3
-#define BT_PIN_PAD_PULL_LSB 2
-#define BT_PIN_PAD_PULL_MASK 0x0000000c
-#define BT_PIN_PAD_PULL_GET(x) (((x) & BT_PIN_PAD_PULL_MASK) >> BT_PIN_PAD_PULL_LSB)
-#define BT_PIN_PAD_PULL_SET(x) (((x) << BT_PIN_PAD_PULL_LSB) & BT_PIN_PAD_PULL_MASK)
-#define BT_PIN_PAD_STRENGTH_MSB 1
-#define BT_PIN_PAD_STRENGTH_LSB 0
-#define BT_PIN_PAD_STRENGTH_MASK 0x00000003
-#define BT_PIN_PAD_STRENGTH_GET(x) (((x) & BT_PIN_PAD_STRENGTH_MASK) >> BT_PIN_PAD_STRENGTH_LSB)
-#define BT_PIN_PAD_STRENGTH_SET(x) (((x) << BT_PIN_PAD_STRENGTH_LSB) & BT_PIN_PAD_STRENGTH_MASK)
-
-#define BT_WLAN_PIN_ADDRESS 0x000000e4
-#define BT_WLAN_PIN_OFFSET 0x000000e4
-#define BT_WLAN_PIN_PAD_PULL_MSB 1
-#define BT_WLAN_PIN_PAD_PULL_LSB 0
-#define BT_WLAN_PIN_PAD_PULL_MASK 0x00000003
-#define BT_WLAN_PIN_PAD_PULL_GET(x) (((x) & BT_WLAN_PIN_PAD_PULL_MASK) >> BT_WLAN_PIN_PAD_PULL_LSB)
-#define BT_WLAN_PIN_PAD_PULL_SET(x) (((x) << BT_WLAN_PIN_PAD_PULL_LSB) & BT_WLAN_PIN_PAD_PULL_MASK)
-
-#define SI_UART_PIN_ADDRESS 0x000000e8
-#define SI_UART_PIN_OFFSET 0x000000e8
-#define SI_UART_PIN_PAD_PULL_MSB 3
-#define SI_UART_PIN_PAD_PULL_LSB 2
-#define SI_UART_PIN_PAD_PULL_MASK 0x0000000c
-#define SI_UART_PIN_PAD_PULL_GET(x) (((x) & SI_UART_PIN_PAD_PULL_MASK) >> SI_UART_PIN_PAD_PULL_LSB)
-#define SI_UART_PIN_PAD_PULL_SET(x) (((x) << SI_UART_PIN_PAD_PULL_LSB) & SI_UART_PIN_PAD_PULL_MASK)
-#define SI_UART_PIN_PAD_STRENGTH_MSB 1
-#define SI_UART_PIN_PAD_STRENGTH_LSB 0
-#define SI_UART_PIN_PAD_STRENGTH_MASK 0x00000003
-#define SI_UART_PIN_PAD_STRENGTH_GET(x) (((x) & SI_UART_PIN_PAD_STRENGTH_MASK) >> SI_UART_PIN_PAD_STRENGTH_LSB)
-#define SI_UART_PIN_PAD_STRENGTH_SET(x) (((x) << SI_UART_PIN_PAD_STRENGTH_LSB) & SI_UART_PIN_PAD_STRENGTH_MASK)
-
-#define CLK32K_PIN_ADDRESS 0x000000ec
-#define CLK32K_PIN_OFFSET 0x000000ec
-#define CLK32K_PIN_PAD_PULL_MSB 1
-#define CLK32K_PIN_PAD_PULL_LSB 0
-#define CLK32K_PIN_PAD_PULL_MASK 0x00000003
-#define CLK32K_PIN_PAD_PULL_GET(x) (((x) & CLK32K_PIN_PAD_PULL_MASK) >> CLK32K_PIN_PAD_PULL_LSB)
-#define CLK32K_PIN_PAD_PULL_SET(x) (((x) << CLK32K_PIN_PAD_PULL_LSB) & CLK32K_PIN_PAD_PULL_MASK)
-
-#define RESET_TUPLE_STATUS_ADDRESS 0x000000f0
-#define RESET_TUPLE_STATUS_OFFSET 0x000000f0
-#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MSB 11
-#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB 8
-#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK 0x00000f00
-#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_GET(x) (((x) & RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK) >> RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB)
-#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_SET(x) (((x) << RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB) & RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK)
-#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MSB 7
-#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB 0
-#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK 0x000000ff
-#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_GET(x) (((x) & RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK) >> RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB)
-#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_SET(x) (((x) << RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB) & RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK)
-
-
-#ifndef __ASSEMBLER__
-
-typedef struct gpio_reg_reg_s {
- volatile unsigned int gpio_out;
- volatile unsigned int gpio_out_w1ts;
- volatile unsigned int gpio_out_w1tc;
- volatile unsigned int gpio_enable;
- volatile unsigned int gpio_enable_w1ts;
- volatile unsigned int gpio_enable_w1tc;
- volatile unsigned int gpio_in;
- volatile unsigned int gpio_status;
- volatile unsigned int gpio_status_w1ts;
- volatile unsigned int gpio_status_w1tc;
- volatile unsigned int gpio_pin0;
- volatile unsigned int gpio_pin1;
- volatile unsigned int gpio_pin2;
- volatile unsigned int gpio_pin3;
- volatile unsigned int gpio_pin4;
- volatile unsigned int gpio_pin5;
- volatile unsigned int gpio_pin6;
- volatile unsigned int gpio_pin7;
- volatile unsigned int gpio_pin8;
- volatile unsigned int gpio_pin9;
- volatile unsigned int gpio_pin10;
- volatile unsigned int gpio_pin11;
- volatile unsigned int gpio_pin12;
- volatile unsigned int gpio_pin13;
- volatile unsigned int gpio_pin14;
- volatile unsigned int gpio_pin15;
- volatile unsigned int gpio_pin16;
- volatile unsigned int gpio_pin17;
- volatile unsigned int sdio_pin;
- volatile unsigned int clk_req_pin;
- volatile unsigned int sigma_delta;
- volatile unsigned int debug_control;
- volatile unsigned int debug_input_sel;
- volatile unsigned int debug_out;
- volatile unsigned int la_control;
- volatile unsigned int la_clock;
- volatile unsigned int la_status;
- volatile unsigned int la_trigger_sample;
- volatile unsigned int la_trigger_position;
- volatile unsigned int la_pre_trigger;
- volatile unsigned int la_post_trigger;
- volatile unsigned int la_filter_control;
- volatile unsigned int la_filter_data;
- volatile unsigned int la_filter_wildcard;
- volatile unsigned int la_triggera_data;
- volatile unsigned int la_triggera_wildcard;
- volatile unsigned int la_triggerb_data;
- volatile unsigned int la_triggerb_wildcard;
- volatile unsigned int la_trigger;
- volatile unsigned int la_fifo;
- volatile unsigned int la[2];
- volatile unsigned int ant_pin;
- volatile unsigned int antd_pin;
- volatile unsigned int gpio_pin;
- volatile unsigned int gpio_h_pin;
- volatile unsigned int bt_pin;
- volatile unsigned int bt_wlan_pin;
- volatile unsigned int si_uart_pin;
- volatile unsigned int clk32k_pin;
- volatile unsigned int reset_tuple_status;
-} gpio_reg_reg_t;
-
-#endif /* __ASSEMBLER__ */
-
-#endif /* _GPIO_REG_H_ */
diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw2.0/hw/mbox_host_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw2.0/hw/mbox_host_reg.h
deleted file mode 100644
index f836ae4..0000000
--- a/drivers/staging/ath6kl/include/common/AR6002/hw2.0/hw/mbox_host_reg.h
+++ /dev/null
@@ -1,386 +0,0 @@
-#ifndef _MBOX_HOST_REG_REG_H_
-#define _MBOX_HOST_REG_REG_H_
-
-#define HOST_INT_STATUS_ADDRESS 0x00000400
-#define HOST_INT_STATUS_OFFSET 0x00000400
-#define HOST_INT_STATUS_ERROR_MSB 7
-#define HOST_INT_STATUS_ERROR_LSB 7
-#define HOST_INT_STATUS_ERROR_MASK 0x00000080
-#define HOST_INT_STATUS_ERROR_GET(x) (((x) & HOST_INT_STATUS_ERROR_MASK) >> HOST_INT_STATUS_ERROR_LSB)
-#define HOST_INT_STATUS_ERROR_SET(x) (((x) << HOST_INT_STATUS_ERROR_LSB) & HOST_INT_STATUS_ERROR_MASK)
-#define HOST_INT_STATUS_CPU_MSB 6
-#define HOST_INT_STATUS_CPU_LSB 6
-#define HOST_INT_STATUS_CPU_MASK 0x00000040
-#define HOST_INT_STATUS_CPU_GET(x) (((x) & HOST_INT_STATUS_CPU_MASK) >> HOST_INT_STATUS_CPU_LSB)
-#define HOST_INT_STATUS_CPU_SET(x) (((x) << HOST_INT_STATUS_CPU_LSB) & HOST_INT_STATUS_CPU_MASK)
-#define HOST_INT_STATUS_DRAGON_INT_MSB 5
-#define HOST_INT_STATUS_DRAGON_INT_LSB 5
-#define HOST_INT_STATUS_DRAGON_INT_MASK 0x00000020
-#define HOST_INT_STATUS_DRAGON_INT_GET(x) (((x) & HOST_INT_STATUS_DRAGON_INT_MASK) >> HOST_INT_STATUS_DRAGON_INT_LSB)
-#define HOST_INT_STATUS_DRAGON_INT_SET(x) (((x) << HOST_INT_STATUS_DRAGON_INT_LSB) & HOST_INT_STATUS_DRAGON_INT_MASK)
-#define HOST_INT_STATUS_COUNTER_MSB 4
-#define HOST_INT_STATUS_COUNTER_LSB 4
-#define HOST_INT_STATUS_COUNTER_MASK 0x00000010
-#define HOST_INT_STATUS_COUNTER_GET(x) (((x) & HOST_INT_STATUS_COUNTER_MASK) >> HOST_INT_STATUS_COUNTER_LSB)
-#define HOST_INT_STATUS_COUNTER_SET(x) (((x) << HOST_INT_STATUS_COUNTER_LSB) & HOST_INT_STATUS_COUNTER_MASK)
-#define HOST_INT_STATUS_MBOX_DATA_MSB 3
-#define HOST_INT_STATUS_MBOX_DATA_LSB 0
-#define HOST_INT_STATUS_MBOX_DATA_MASK 0x0000000f
-#define HOST_INT_STATUS_MBOX_DATA_GET(x) (((x) & HOST_INT_STATUS_MBOX_DATA_MASK) >> HOST_INT_STATUS_MBOX_DATA_LSB)
-#define HOST_INT_STATUS_MBOX_DATA_SET(x) (((x) << HOST_INT_STATUS_MBOX_DATA_LSB) & HOST_INT_STATUS_MBOX_DATA_MASK)
-
-#define CPU_INT_STATUS_ADDRESS 0x00000401
-#define CPU_INT_STATUS_OFFSET 0x00000401
-#define CPU_INT_STATUS_BIT_MSB 7
-#define CPU_INT_STATUS_BIT_LSB 0
-#define CPU_INT_STATUS_BIT_MASK 0x000000ff
-#define CPU_INT_STATUS_BIT_GET(x) (((x) & CPU_INT_STATUS_BIT_MASK) >> CPU_INT_STATUS_BIT_LSB)
-#define CPU_INT_STATUS_BIT_SET(x) (((x) << CPU_INT_STATUS_BIT_LSB) & CPU_INT_STATUS_BIT_MASK)
-
-#define ERROR_INT_STATUS_ADDRESS 0x00000402
-#define ERROR_INT_STATUS_OFFSET 0x00000402
-#define ERROR_INT_STATUS_SPI_MSB 3
-#define ERROR_INT_STATUS_SPI_LSB 3
-#define ERROR_INT_STATUS_SPI_MASK 0x00000008
-#define ERROR_INT_STATUS_SPI_GET(x) (((x) & ERROR_INT_STATUS_SPI_MASK) >> ERROR_INT_STATUS_SPI_LSB)
-#define ERROR_INT_STATUS_SPI_SET(x) (((x) << ERROR_INT_STATUS_SPI_LSB) & ERROR_INT_STATUS_SPI_MASK)
-#define ERROR_INT_STATUS_WAKEUP_MSB 2
-#define ERROR_INT_STATUS_WAKEUP_LSB 2
-#define ERROR_INT_STATUS_WAKEUP_MASK 0x00000004
-#define ERROR_INT_STATUS_WAKEUP_GET(x) (((x) & ERROR_INT_STATUS_WAKEUP_MASK) >> ERROR_INT_STATUS_WAKEUP_LSB)
-#define ERROR_INT_STATUS_WAKEUP_SET(x) (((x) << ERROR_INT_STATUS_WAKEUP_LSB) & ERROR_INT_STATUS_WAKEUP_MASK)
-#define ERROR_INT_STATUS_RX_UNDERFLOW_MSB 1
-#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB 1
-#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK 0x00000002
-#define ERROR_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK) >> ERROR_INT_STATUS_RX_UNDERFLOW_LSB)
-#define ERROR_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << ERROR_INT_STATUS_RX_UNDERFLOW_LSB) & ERROR_INT_STATUS_RX_UNDERFLOW_MASK)
-#define ERROR_INT_STATUS_TX_OVERFLOW_MSB 0
-#define ERROR_INT_STATUS_TX_OVERFLOW_LSB 0
-#define ERROR_INT_STATUS_TX_OVERFLOW_MASK 0x00000001
-#define ERROR_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & ERROR_INT_STATUS_TX_OVERFLOW_MASK) >> ERROR_INT_STATUS_TX_OVERFLOW_LSB)
-#define ERROR_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << ERROR_INT_STATUS_TX_OVERFLOW_LSB) & ERROR_INT_STATUS_TX_OVERFLOW_MASK)
-
-#define COUNTER_INT_STATUS_ADDRESS 0x00000403
-#define COUNTER_INT_STATUS_OFFSET 0x00000403
-#define COUNTER_INT_STATUS_COUNTER_MSB 7
-#define COUNTER_INT_STATUS_COUNTER_LSB 0
-#define COUNTER_INT_STATUS_COUNTER_MASK 0x000000ff
-#define COUNTER_INT_STATUS_COUNTER_GET(x) (((x) & COUNTER_INT_STATUS_COUNTER_MASK) >> COUNTER_INT_STATUS_COUNTER_LSB)
-#define COUNTER_INT_STATUS_COUNTER_SET(x) (((x) << COUNTER_INT_STATUS_COUNTER_LSB) & COUNTER_INT_STATUS_COUNTER_MASK)
-
-#define MBOX_FRAME_ADDRESS 0x00000404
-#define MBOX_FRAME_OFFSET 0x00000404
-#define MBOX_FRAME_RX_EOM_MSB 7
-#define MBOX_FRAME_RX_EOM_LSB 4
-#define MBOX_FRAME_RX_EOM_MASK 0x000000f0
-#define MBOX_FRAME_RX_EOM_GET(x) (((x) & MBOX_FRAME_RX_EOM_MASK) >> MBOX_FRAME_RX_EOM_LSB)
-#define MBOX_FRAME_RX_EOM_SET(x) (((x) << MBOX_FRAME_RX_EOM_LSB) & MBOX_FRAME_RX_EOM_MASK)
-#define MBOX_FRAME_RX_SOM_MSB 3
-#define MBOX_FRAME_RX_SOM_LSB 0
-#define MBOX_FRAME_RX_SOM_MASK 0x0000000f
-#define MBOX_FRAME_RX_SOM_GET(x) (((x) & MBOX_FRAME_RX_SOM_MASK) >> MBOX_FRAME_RX_SOM_LSB)
-#define MBOX_FRAME_RX_SOM_SET(x) (((x) << MBOX_FRAME_RX_SOM_LSB) & MBOX_FRAME_RX_SOM_MASK)
-
-#define RX_LOOKAHEAD_VALID_ADDRESS 0x00000405
-#define RX_LOOKAHEAD_VALID_OFFSET 0x00000405
-#define RX_LOOKAHEAD_VALID_MBOX_MSB 3
-#define RX_LOOKAHEAD_VALID_MBOX_LSB 0
-#define RX_LOOKAHEAD_VALID_MBOX_MASK 0x0000000f
-#define RX_LOOKAHEAD_VALID_MBOX_GET(x) (((x) & RX_LOOKAHEAD_VALID_MBOX_MASK) >> RX_LOOKAHEAD_VALID_MBOX_LSB)
-#define RX_LOOKAHEAD_VALID_MBOX_SET(x) (((x) << RX_LOOKAHEAD_VALID_MBOX_LSB) & RX_LOOKAHEAD_VALID_MBOX_MASK)
-
-#define RX_LOOKAHEAD0_ADDRESS 0x00000408
-#define RX_LOOKAHEAD0_OFFSET 0x00000408
-#define RX_LOOKAHEAD0_DATA_MSB 7
-#define RX_LOOKAHEAD0_DATA_LSB 0
-#define RX_LOOKAHEAD0_DATA_MASK 0x000000ff
-#define RX_LOOKAHEAD0_DATA_GET(x) (((x) & RX_LOOKAHEAD0_DATA_MASK) >> RX_LOOKAHEAD0_DATA_LSB)
-#define RX_LOOKAHEAD0_DATA_SET(x) (((x) << RX_LOOKAHEAD0_DATA_LSB) & RX_LOOKAHEAD0_DATA_MASK)
-
-#define RX_LOOKAHEAD1_ADDRESS 0x0000040c
-#define RX_LOOKAHEAD1_OFFSET 0x0000040c
-#define RX_LOOKAHEAD1_DATA_MSB 7
-#define RX_LOOKAHEAD1_DATA_LSB 0
-#define RX_LOOKAHEAD1_DATA_MASK 0x000000ff
-#define RX_LOOKAHEAD1_DATA_GET(x) (((x) & RX_LOOKAHEAD1_DATA_MASK) >> RX_LOOKAHEAD1_DATA_LSB)
-#define RX_LOOKAHEAD1_DATA_SET(x) (((x) << RX_LOOKAHEAD1_DATA_LSB) & RX_LOOKAHEAD1_DATA_MASK)
-
-#define RX_LOOKAHEAD2_ADDRESS 0x00000410
-#define RX_LOOKAHEAD2_OFFSET 0x00000410
-#define RX_LOOKAHEAD2_DATA_MSB 7
-#define RX_LOOKAHEAD2_DATA_LSB 0
-#define RX_LOOKAHEAD2_DATA_MASK 0x000000ff
-#define RX_LOOKAHEAD2_DATA_GET(x) (((x) & RX_LOOKAHEAD2_DATA_MASK) >> RX_LOOKAHEAD2_DATA_LSB)
-#define RX_LOOKAHEAD2_DATA_SET(x) (((x) << RX_LOOKAHEAD2_DATA_LSB) & RX_LOOKAHEAD2_DATA_MASK)
-
-#define RX_LOOKAHEAD3_ADDRESS 0x00000414
-#define RX_LOOKAHEAD3_OFFSET 0x00000414
-#define RX_LOOKAHEAD3_DATA_MSB 7
-#define RX_LOOKAHEAD3_DATA_LSB 0
-#define RX_LOOKAHEAD3_DATA_MASK 0x000000ff
-#define RX_LOOKAHEAD3_DATA_GET(x) (((x) & RX_LOOKAHEAD3_DATA_MASK) >> RX_LOOKAHEAD3_DATA_LSB)
-#define RX_LOOKAHEAD3_DATA_SET(x) (((x) << RX_LOOKAHEAD3_DATA_LSB) & RX_LOOKAHEAD3_DATA_MASK)
-
-#define INT_STATUS_ENABLE_ADDRESS 0x00000418
-#define INT_STATUS_ENABLE_OFFSET 0x00000418
-#define INT_STATUS_ENABLE_ERROR_MSB 7
-#define INT_STATUS_ENABLE_ERROR_LSB 7
-#define INT_STATUS_ENABLE_ERROR_MASK 0x00000080
-#define INT_STATUS_ENABLE_ERROR_GET(x) (((x) & INT_STATUS_ENABLE_ERROR_MASK) >> INT_STATUS_ENABLE_ERROR_LSB)
-#define INT_STATUS_ENABLE_ERROR_SET(x) (((x) << INT_STATUS_ENABLE_ERROR_LSB) & INT_STATUS_ENABLE_ERROR_MASK)
-#define INT_STATUS_ENABLE_CPU_MSB 6
-#define INT_STATUS_ENABLE_CPU_LSB 6
-#define INT_STATUS_ENABLE_CPU_MASK 0x00000040
-#define INT_STATUS_ENABLE_CPU_GET(x) (((x) & INT_STATUS_ENABLE_CPU_MASK) >> INT_STATUS_ENABLE_CPU_LSB)
-#define INT_STATUS_ENABLE_CPU_SET(x) (((x) << INT_STATUS_ENABLE_CPU_LSB) & INT_STATUS_ENABLE_CPU_MASK)
-#define INT_STATUS_ENABLE_DRAGON_INT_MSB 5
-#define INT_STATUS_ENABLE_DRAGON_INT_LSB 5
-#define INT_STATUS_ENABLE_DRAGON_INT_MASK 0x00000020
-#define INT_STATUS_ENABLE_DRAGON_INT_GET(x) (((x) & INT_STATUS_ENABLE_DRAGON_INT_MASK) >> INT_STATUS_ENABLE_DRAGON_INT_LSB)
-#define INT_STATUS_ENABLE_DRAGON_INT_SET(x) (((x) << INT_STATUS_ENABLE_DRAGON_INT_LSB) & INT_STATUS_ENABLE_DRAGON_INT_MASK)
-#define INT_STATUS_ENABLE_COUNTER_MSB 4
-#define INT_STATUS_ENABLE_COUNTER_LSB 4
-#define INT_STATUS_ENABLE_COUNTER_MASK 0x00000010
-#define INT_STATUS_ENABLE_COUNTER_GET(x) (((x) & INT_STATUS_ENABLE_COUNTER_MASK) >> INT_STATUS_ENABLE_COUNTER_LSB)
-#define INT_STATUS_ENABLE_COUNTER_SET(x) (((x) << INT_STATUS_ENABLE_COUNTER_LSB) & INT_STATUS_ENABLE_COUNTER_MASK)
-#define INT_STATUS_ENABLE_MBOX_DATA_MSB 3
-#define INT_STATUS_ENABLE_MBOX_DATA_LSB 0
-#define INT_STATUS_ENABLE_MBOX_DATA_MASK 0x0000000f
-#define INT_STATUS_ENABLE_MBOX_DATA_GET(x) (((x) & INT_STATUS_ENABLE_MBOX_DATA_MASK) >> INT_STATUS_ENABLE_MBOX_DATA_LSB)
-#define INT_STATUS_ENABLE_MBOX_DATA_SET(x) (((x) << INT_STATUS_ENABLE_MBOX_DATA_LSB) & INT_STATUS_ENABLE_MBOX_DATA_MASK)
-
-#define CPU_INT_STATUS_ENABLE_ADDRESS 0x00000419
-#define CPU_INT_STATUS_ENABLE_OFFSET 0x00000419
-#define CPU_INT_STATUS_ENABLE_BIT_MSB 7
-#define CPU_INT_STATUS_ENABLE_BIT_LSB 0
-#define CPU_INT_STATUS_ENABLE_BIT_MASK 0x000000ff
-#define CPU_INT_STATUS_ENABLE_BIT_GET(x) (((x) & CPU_INT_STATUS_ENABLE_BIT_MASK) >> CPU_INT_STATUS_ENABLE_BIT_LSB)
-#define CPU_INT_STATUS_ENABLE_BIT_SET(x) (((x) << CPU_INT_STATUS_ENABLE_BIT_LSB) & CPU_INT_STATUS_ENABLE_BIT_MASK)
-
-#define ERROR_STATUS_ENABLE_ADDRESS 0x0000041a
-#define ERROR_STATUS_ENABLE_OFFSET 0x0000041a
-#define ERROR_STATUS_ENABLE_WAKEUP_MSB 2
-#define ERROR_STATUS_ENABLE_WAKEUP_LSB 2
-#define ERROR_STATUS_ENABLE_WAKEUP_MASK 0x00000004
-#define ERROR_STATUS_ENABLE_WAKEUP_GET(x) (((x) & ERROR_STATUS_ENABLE_WAKEUP_MASK) >> ERROR_STATUS_ENABLE_WAKEUP_LSB)
-#define ERROR_STATUS_ENABLE_WAKEUP_SET(x) (((x) << ERROR_STATUS_ENABLE_WAKEUP_LSB) & ERROR_STATUS_ENABLE_WAKEUP_MASK)
-#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MSB 1
-#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB 1
-#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK 0x00000002
-#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK) >> ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB)
-#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB) & ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK)
-#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MSB 0
-#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB 0
-#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK 0x00000001
-#define ERROR_STATUS_ENABLE_TX_OVERFLOW_GET(x) (((x) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK) >> ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB)
-#define ERROR_STATUS_ENABLE_TX_OVERFLOW_SET(x) (((x) << ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB) & ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK)
-
-#define COUNTER_INT_STATUS_ENABLE_ADDRESS 0x0000041b
-#define COUNTER_INT_STATUS_ENABLE_OFFSET 0x0000041b
-#define COUNTER_INT_STATUS_ENABLE_BIT_MSB 7
-#define COUNTER_INT_STATUS_ENABLE_BIT_LSB 0
-#define COUNTER_INT_STATUS_ENABLE_BIT_MASK 0x000000ff
-#define COUNTER_INT_STATUS_ENABLE_BIT_GET(x) (((x) & COUNTER_INT_STATUS_ENABLE_BIT_MASK) >> COUNTER_INT_STATUS_ENABLE_BIT_LSB)
-#define COUNTER_INT_STATUS_ENABLE_BIT_SET(x) (((x) << COUNTER_INT_STATUS_ENABLE_BIT_LSB) & COUNTER_INT_STATUS_ENABLE_BIT_MASK)
-
-#define COUNT_ADDRESS 0x00000420
-#define COUNT_OFFSET 0x00000420
-#define COUNT_VALUE_MSB 7
-#define COUNT_VALUE_LSB 0
-#define COUNT_VALUE_MASK 0x000000ff
-#define COUNT_VALUE_GET(x) (((x) & COUNT_VALUE_MASK) >> COUNT_VALUE_LSB)
-#define COUNT_VALUE_SET(x) (((x) << COUNT_VALUE_LSB) & COUNT_VALUE_MASK)
-
-#define COUNT_DEC_ADDRESS 0x00000440
-#define COUNT_DEC_OFFSET 0x00000440
-#define COUNT_DEC_VALUE_MSB 7
-#define COUNT_DEC_VALUE_LSB 0
-#define COUNT_DEC_VALUE_MASK 0x000000ff
-#define COUNT_DEC_VALUE_GET(x) (((x) & COUNT_DEC_VALUE_MASK) >> COUNT_DEC_VALUE_LSB)
-#define COUNT_DEC_VALUE_SET(x) (((x) << COUNT_DEC_VALUE_LSB) & COUNT_DEC_VALUE_MASK)
-
-#define SCRATCH_ADDRESS 0x00000460
-#define SCRATCH_OFFSET 0x00000460
-#define SCRATCH_VALUE_MSB 7
-#define SCRATCH_VALUE_LSB 0
-#define SCRATCH_VALUE_MASK 0x000000ff
-#define SCRATCH_VALUE_GET(x) (((x) & SCRATCH_VALUE_MASK) >> SCRATCH_VALUE_LSB)
-#define SCRATCH_VALUE_SET(x) (((x) << SCRATCH_VALUE_LSB) & SCRATCH_VALUE_MASK)
-
-#define FIFO_TIMEOUT_ADDRESS 0x00000468
-#define FIFO_TIMEOUT_OFFSET 0x00000468
-#define FIFO_TIMEOUT_VALUE_MSB 7
-#define FIFO_TIMEOUT_VALUE_LSB 0
-#define FIFO_TIMEOUT_VALUE_MASK 0x000000ff
-#define FIFO_TIMEOUT_VALUE_GET(x) (((x) & FIFO_TIMEOUT_VALUE_MASK) >> FIFO_TIMEOUT_VALUE_LSB)
-#define FIFO_TIMEOUT_VALUE_SET(x) (((x) << FIFO_TIMEOUT_VALUE_LSB) & FIFO_TIMEOUT_VALUE_MASK)
-
-#define FIFO_TIMEOUT_ENABLE_ADDRESS 0x00000469
-#define FIFO_TIMEOUT_ENABLE_OFFSET 0x00000469
-#define FIFO_TIMEOUT_ENABLE_SET_MSB 0
-#define FIFO_TIMEOUT_ENABLE_SET_LSB 0
-#define FIFO_TIMEOUT_ENABLE_SET_MASK 0x00000001
-#define FIFO_TIMEOUT_ENABLE_SET_GET(x) (((x) & FIFO_TIMEOUT_ENABLE_SET_MASK) >> FIFO_TIMEOUT_ENABLE_SET_LSB)
-#define FIFO_TIMEOUT_ENABLE_SET_SET(x) (((x) << FIFO_TIMEOUT_ENABLE_SET_LSB) & FIFO_TIMEOUT_ENABLE_SET_MASK)
-
-#define DISABLE_SLEEP_ADDRESS 0x0000046a
-#define DISABLE_SLEEP_OFFSET 0x0000046a
-#define DISABLE_SLEEP_FOR_INT_MSB 1
-#define DISABLE_SLEEP_FOR_INT_LSB 1
-#define DISABLE_SLEEP_FOR_INT_MASK 0x00000002
-#define DISABLE_SLEEP_FOR_INT_GET(x) (((x) & DISABLE_SLEEP_FOR_INT_MASK) >> DISABLE_SLEEP_FOR_INT_LSB)
-#define DISABLE_SLEEP_FOR_INT_SET(x) (((x) << DISABLE_SLEEP_FOR_INT_LSB) & DISABLE_SLEEP_FOR_INT_MASK)
-#define DISABLE_SLEEP_ON_MSB 0
-#define DISABLE_SLEEP_ON_LSB 0
-#define DISABLE_SLEEP_ON_MASK 0x00000001
-#define DISABLE_SLEEP_ON_GET(x) (((x) & DISABLE_SLEEP_ON_MASK) >> DISABLE_SLEEP_ON_LSB)
-#define DISABLE_SLEEP_ON_SET(x) (((x) << DISABLE_SLEEP_ON_LSB) & DISABLE_SLEEP_ON_MASK)
-
-#define LOCAL_BUS_ADDRESS 0x00000470
-#define LOCAL_BUS_OFFSET 0x00000470
-#define LOCAL_BUS_STATE_MSB 1
-#define LOCAL_BUS_STATE_LSB 0
-#define LOCAL_BUS_STATE_MASK 0x00000003
-#define LOCAL_BUS_STATE_GET(x) (((x) & LOCAL_BUS_STATE_MASK) >> LOCAL_BUS_STATE_LSB)
-#define LOCAL_BUS_STATE_SET(x) (((x) << LOCAL_BUS_STATE_LSB) & LOCAL_BUS_STATE_MASK)
-
-#define INT_WLAN_ADDRESS 0x00000472
-#define INT_WLAN_OFFSET 0x00000472
-#define INT_WLAN_VECTOR_MSB 7
-#define INT_WLAN_VECTOR_LSB 0
-#define INT_WLAN_VECTOR_MASK 0x000000ff
-#define INT_WLAN_VECTOR_GET(x) (((x) & INT_WLAN_VECTOR_MASK) >> INT_WLAN_VECTOR_LSB)
-#define INT_WLAN_VECTOR_SET(x) (((x) << INT_WLAN_VECTOR_LSB) & INT_WLAN_VECTOR_MASK)
-
-#define WINDOW_DATA_ADDRESS 0x00000474
-#define WINDOW_DATA_OFFSET 0x00000474
-#define WINDOW_DATA_DATA_MSB 7
-#define WINDOW_DATA_DATA_LSB 0
-#define WINDOW_DATA_DATA_MASK 0x000000ff
-#define WINDOW_DATA_DATA_GET(x) (((x) & WINDOW_DATA_DATA_MASK) >> WINDOW_DATA_DATA_LSB)
-#define WINDOW_DATA_DATA_SET(x) (((x) << WINDOW_DATA_DATA_LSB) & WINDOW_DATA_DATA_MASK)
-
-#define WINDOW_WRITE_ADDR_ADDRESS 0x00000478
-#define WINDOW_WRITE_ADDR_OFFSET 0x00000478
-#define WINDOW_WRITE_ADDR_ADDR_MSB 7
-#define WINDOW_WRITE_ADDR_ADDR_LSB 0
-#define WINDOW_WRITE_ADDR_ADDR_MASK 0x000000ff
-#define WINDOW_WRITE_ADDR_ADDR_GET(x) (((x) & WINDOW_WRITE_ADDR_ADDR_MASK) >> WINDOW_WRITE_ADDR_ADDR_LSB)
-#define WINDOW_WRITE_ADDR_ADDR_SET(x) (((x) << WINDOW_WRITE_ADDR_ADDR_LSB) & WINDOW_WRITE_ADDR_ADDR_MASK)
-
-#define WINDOW_READ_ADDR_ADDRESS 0x0000047c
-#define WINDOW_READ_ADDR_OFFSET 0x0000047c
-#define WINDOW_READ_ADDR_ADDR_MSB 7
-#define WINDOW_READ_ADDR_ADDR_LSB 0
-#define WINDOW_READ_ADDR_ADDR_MASK 0x000000ff
-#define WINDOW_READ_ADDR_ADDR_GET(x) (((x) & WINDOW_READ_ADDR_ADDR_MASK) >> WINDOW_READ_ADDR_ADDR_LSB)
-#define WINDOW_READ_ADDR_ADDR_SET(x) (((x) << WINDOW_READ_ADDR_ADDR_LSB) & WINDOW_READ_ADDR_ADDR_MASK)
-
-#define SPI_CONFIG_ADDRESS 0x00000480
-#define SPI_CONFIG_OFFSET 0x00000480
-#define SPI_CONFIG_SPI_RESET_MSB 4
-#define SPI_CONFIG_SPI_RESET_LSB 4
-#define SPI_CONFIG_SPI_RESET_MASK 0x00000010
-#define SPI_CONFIG_SPI_RESET_GET(x) (((x) & SPI_CONFIG_SPI_RESET_MASK) >> SPI_CONFIG_SPI_RESET_LSB)
-#define SPI_CONFIG_SPI_RESET_SET(x) (((x) << SPI_CONFIG_SPI_RESET_LSB) & SPI_CONFIG_SPI_RESET_MASK)
-#define SPI_CONFIG_INTERRUPT_ENABLE_MSB 3
-#define SPI_CONFIG_INTERRUPT_ENABLE_LSB 3
-#define SPI_CONFIG_INTERRUPT_ENABLE_MASK 0x00000008
-#define SPI_CONFIG_INTERRUPT_ENABLE_GET(x) (((x) & SPI_CONFIG_INTERRUPT_ENABLE_MASK) >> SPI_CONFIG_INTERRUPT_ENABLE_LSB)
-#define SPI_CONFIG_INTERRUPT_ENABLE_SET(x) (((x) << SPI_CONFIG_INTERRUPT_ENABLE_LSB) & SPI_CONFIG_INTERRUPT_ENABLE_MASK)
-#define SPI_CONFIG_TEST_MODE_MSB 2
-#define SPI_CONFIG_TEST_MODE_LSB 2
-#define SPI_CONFIG_TEST_MODE_MASK 0x00000004
-#define SPI_CONFIG_TEST_MODE_GET(x) (((x) & SPI_CONFIG_TEST_MODE_MASK) >> SPI_CONFIG_TEST_MODE_LSB)
-#define SPI_CONFIG_TEST_MODE_SET(x) (((x) << SPI_CONFIG_TEST_MODE_LSB) & SPI_CONFIG_TEST_MODE_MASK)
-#define SPI_CONFIG_DATA_SIZE_MSB 1
-#define SPI_CONFIG_DATA_SIZE_LSB 0
-#define SPI_CONFIG_DATA_SIZE_MASK 0x00000003
-#define SPI_CONFIG_DATA_SIZE_GET(x) (((x) & SPI_CONFIG_DATA_SIZE_MASK) >> SPI_CONFIG_DATA_SIZE_LSB)
-#define SPI_CONFIG_DATA_SIZE_SET(x) (((x) << SPI_CONFIG_DATA_SIZE_LSB) & SPI_CONFIG_DATA_SIZE_MASK)
-
-#define SPI_STATUS_ADDRESS 0x00000481
-#define SPI_STATUS_OFFSET 0x00000481
-#define SPI_STATUS_ADDR_ERR_MSB 3
-#define SPI_STATUS_ADDR_ERR_LSB 3
-#define SPI_STATUS_ADDR_ERR_MASK 0x00000008
-#define SPI_STATUS_ADDR_ERR_GET(x) (((x) & SPI_STATUS_ADDR_ERR_MASK) >> SPI_STATUS_ADDR_ERR_LSB)
-#define SPI_STATUS_ADDR_ERR_SET(x) (((x) << SPI_STATUS_ADDR_ERR_LSB) & SPI_STATUS_ADDR_ERR_MASK)
-#define SPI_STATUS_RD_ERR_MSB 2
-#define SPI_STATUS_RD_ERR_LSB 2
-#define SPI_STATUS_RD_ERR_MASK 0x00000004
-#define SPI_STATUS_RD_ERR_GET(x) (((x) & SPI_STATUS_RD_ERR_MASK) >> SPI_STATUS_RD_ERR_LSB)
-#define SPI_STATUS_RD_ERR_SET(x) (((x) << SPI_STATUS_RD_ERR_LSB) & SPI_STATUS_RD_ERR_MASK)
-#define SPI_STATUS_WR_ERR_MSB 1
-#define SPI_STATUS_WR_ERR_LSB 1
-#define SPI_STATUS_WR_ERR_MASK 0x00000002
-#define SPI_STATUS_WR_ERR_GET(x) (((x) & SPI_STATUS_WR_ERR_MASK) >> SPI_STATUS_WR_ERR_LSB)
-#define SPI_STATUS_WR_ERR_SET(x) (((x) << SPI_STATUS_WR_ERR_LSB) & SPI_STATUS_WR_ERR_MASK)
-#define SPI_STATUS_READY_MSB 0
-#define SPI_STATUS_READY_LSB 0
-#define SPI_STATUS_READY_MASK 0x00000001
-#define SPI_STATUS_READY_GET(x) (((x) & SPI_STATUS_READY_MASK) >> SPI_STATUS_READY_LSB)
-#define SPI_STATUS_READY_SET(x) (((x) << SPI_STATUS_READY_LSB) & SPI_STATUS_READY_MASK)
-
-#define NON_ASSOC_SLEEP_EN_ADDRESS 0x00000482
-#define NON_ASSOC_SLEEP_EN_OFFSET 0x00000482
-#define NON_ASSOC_SLEEP_EN_BIT_MSB 0
-#define NON_ASSOC_SLEEP_EN_BIT_LSB 0
-#define NON_ASSOC_SLEEP_EN_BIT_MASK 0x00000001
-#define NON_ASSOC_SLEEP_EN_BIT_GET(x) (((x) & NON_ASSOC_SLEEP_EN_BIT_MASK) >> NON_ASSOC_SLEEP_EN_BIT_LSB)
-#define NON_ASSOC_SLEEP_EN_BIT_SET(x) (((x) << NON_ASSOC_SLEEP_EN_BIT_LSB) & NON_ASSOC_SLEEP_EN_BIT_MASK)
-
-#define CIS_WINDOW_ADDRESS 0x00000600
-#define CIS_WINDOW_OFFSET 0x00000600
-#define CIS_WINDOW_DATA_MSB 7
-#define CIS_WINDOW_DATA_LSB 0
-#define CIS_WINDOW_DATA_MASK 0x000000ff
-#define CIS_WINDOW_DATA_GET(x) (((x) & CIS_WINDOW_DATA_MASK) >> CIS_WINDOW_DATA_LSB)
-#define CIS_WINDOW_DATA_SET(x) (((x) << CIS_WINDOW_DATA_LSB) & CIS_WINDOW_DATA_MASK)
-
-
-#ifndef __ASSEMBLER__
-
-typedef struct mbox_host_reg_reg_s {
- unsigned char pad0[1024]; /* pad to 0x400 */
- volatile unsigned char host_int_status;
- volatile unsigned char cpu_int_status;
- volatile unsigned char error_int_status;
- volatile unsigned char counter_int_status;
- volatile unsigned char mbox_frame;
- volatile unsigned char rx_lookahead_valid;
- unsigned char pad1[2]; /* pad to 0x408 */
- volatile unsigned char rx_lookahead0[4];
- volatile unsigned char rx_lookahead1[4];
- volatile unsigned char rx_lookahead2[4];
- volatile unsigned char rx_lookahead3[4];
- volatile unsigned char int_status_enable;
- volatile unsigned char cpu_int_status_enable;
- volatile unsigned char error_status_enable;
- volatile unsigned char counter_int_status_enable;
- unsigned char pad2[4]; /* pad to 0x420 */
- volatile unsigned char count[8];
- unsigned char pad3[24]; /* pad to 0x440 */
- volatile unsigned char count_dec[32];
- volatile unsigned char scratch[8];
- volatile unsigned char fifo_timeout;
- volatile unsigned char fifo_timeout_enable;
- volatile unsigned char disable_sleep;
- unsigned char pad4[5]; /* pad to 0x470 */
- volatile unsigned char local_bus;
- unsigned char pad5[1]; /* pad to 0x472 */
- volatile unsigned char int_wlan;
- unsigned char pad6[1]; /* pad to 0x474 */
- volatile unsigned char window_data[4];
- volatile unsigned char window_write_addr[4];
- volatile unsigned char window_read_addr[4];
- volatile unsigned char spi_config;
- volatile unsigned char spi_status;
- volatile unsigned char non_assoc_sleep_en;
- unsigned char pad7[381]; /* pad to 0x600 */
- volatile unsigned char cis_window[512];
-} mbox_host_reg_reg_t;
-
-#endif /* __ASSEMBLER__ */
-
-#endif /* _MBOX_HOST_REG_H_ */
diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw2.0/hw/mbox_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw2.0/hw/mbox_reg.h
deleted file mode 100644
index 4e07d22..0000000
--- a/drivers/staging/ath6kl/include/common/AR6002/hw2.0/hw/mbox_reg.h
+++ /dev/null
@@ -1,481 +0,0 @@
-#ifndef _MBOX_REG_REG_H_
-#define _MBOX_REG_REG_H_
-
-#define MBOX_FIFO_ADDRESS 0x00000000
-#define MBOX_FIFO_OFFSET 0x00000000
-#define MBOX_FIFO_DATA_MSB 19
-#define MBOX_FIFO_DATA_LSB 0
-#define MBOX_FIFO_DATA_MASK 0x000fffff
-#define MBOX_FIFO_DATA_GET(x) (((x) & MBOX_FIFO_DATA_MASK) >> MBOX_FIFO_DATA_LSB)
-#define MBOX_FIFO_DATA_SET(x) (((x) << MBOX_FIFO_DATA_LSB) & MBOX_FIFO_DATA_MASK)
-
-#define MBOX_FIFO_STATUS_ADDRESS 0x00000010
-#define MBOX_FIFO_STATUS_OFFSET 0x00000010
-#define MBOX_FIFO_STATUS_EMPTY_MSB 19
-#define MBOX_FIFO_STATUS_EMPTY_LSB 16
-#define MBOX_FIFO_STATUS_EMPTY_MASK 0x000f0000
-#define MBOX_FIFO_STATUS_EMPTY_GET(x) (((x) & MBOX_FIFO_STATUS_EMPTY_MASK) >> MBOX_FIFO_STATUS_EMPTY_LSB)
-#define MBOX_FIFO_STATUS_EMPTY_SET(x) (((x) << MBOX_FIFO_STATUS_EMPTY_LSB) & MBOX_FIFO_STATUS_EMPTY_MASK)
-#define MBOX_FIFO_STATUS_FULL_MSB 15
-#define MBOX_FIFO_STATUS_FULL_LSB 12
-#define MBOX_FIFO_STATUS_FULL_MASK 0x0000f000
-#define MBOX_FIFO_STATUS_FULL_GET(x) (((x) & MBOX_FIFO_STATUS_FULL_MASK) >> MBOX_FIFO_STATUS_FULL_LSB)
-#define MBOX_FIFO_STATUS_FULL_SET(x) (((x) << MBOX_FIFO_STATUS_FULL_LSB) & MBOX_FIFO_STATUS_FULL_MASK)
-
-#define MBOX_DMA_POLICY_ADDRESS 0x00000014
-#define MBOX_DMA_POLICY_OFFSET 0x00000014
-#define MBOX_DMA_POLICY_TX_QUANTUM_MSB 3
-#define MBOX_DMA_POLICY_TX_QUANTUM_LSB 3
-#define MBOX_DMA_POLICY_TX_QUANTUM_MASK 0x00000008
-#define MBOX_DMA_POLICY_TX_QUANTUM_GET(x) (((x) & MBOX_DMA_POLICY_TX_QUANTUM_MASK) >> MBOX_DMA_POLICY_TX_QUANTUM_LSB)
-#define MBOX_DMA_POLICY_TX_QUANTUM_SET(x) (((x) << MBOX_DMA_POLICY_TX_QUANTUM_LSB) & MBOX_DMA_POLICY_TX_QUANTUM_MASK)
-#define MBOX_DMA_POLICY_TX_ORDER_MSB 2
-#define MBOX_DMA_POLICY_TX_ORDER_LSB 2
-#define MBOX_DMA_POLICY_TX_ORDER_MASK 0x00000004
-#define MBOX_DMA_POLICY_TX_ORDER_GET(x) (((x) & MBOX_DMA_POLICY_TX_ORDER_MASK) >> MBOX_DMA_POLICY_TX_ORDER_LSB)
-#define MBOX_DMA_POLICY_TX_ORDER_SET(x) (((x) << MBOX_DMA_POLICY_TX_ORDER_LSB) & MBOX_DMA_POLICY_TX_ORDER_MASK)
-#define MBOX_DMA_POLICY_RX_QUANTUM_MSB 1
-#define MBOX_DMA_POLICY_RX_QUANTUM_LSB 1
-#define MBOX_DMA_POLICY_RX_QUANTUM_MASK 0x00000002
-#define MBOX_DMA_POLICY_RX_QUANTUM_GET(x) (((x) & MBOX_DMA_POLICY_RX_QUANTUM_MASK) >> MBOX_DMA_POLICY_RX_QUANTUM_LSB)
-#define MBOX_DMA_POLICY_RX_QUANTUM_SET(x) (((x) << MBOX_DMA_POLICY_RX_QUANTUM_LSB) & MBOX_DMA_POLICY_RX_QUANTUM_MASK)
-#define MBOX_DMA_POLICY_RX_ORDER_MSB 0
-#define MBOX_DMA_POLICY_RX_ORDER_LSB 0
-#define MBOX_DMA_POLICY_RX_ORDER_MASK 0x00000001
-#define MBOX_DMA_POLICY_RX_ORDER_GET(x) (((x) & MBOX_DMA_POLICY_RX_ORDER_MASK) >> MBOX_DMA_POLICY_RX_ORDER_LSB)
-#define MBOX_DMA_POLICY_RX_ORDER_SET(x) (((x) << MBOX_DMA_POLICY_RX_ORDER_LSB) & MBOX_DMA_POLICY_RX_ORDER_MASK)
-
-#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000018
-#define MBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000018
-#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
-#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
-#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
-#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
-#define MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
-
-#define MBOX0_DMA_RX_CONTROL_ADDRESS 0x0000001c
-#define MBOX0_DMA_RX_CONTROL_OFFSET 0x0000001c
-#define MBOX0_DMA_RX_CONTROL_RESUME_MSB 2
-#define MBOX0_DMA_RX_CONTROL_RESUME_LSB 2
-#define MBOX0_DMA_RX_CONTROL_RESUME_MASK 0x00000004
-#define MBOX0_DMA_RX_CONTROL_RESUME_GET(x) (((x) & MBOX0_DMA_RX_CONTROL_RESUME_MASK) >> MBOX0_DMA_RX_CONTROL_RESUME_LSB)
-#define MBOX0_DMA_RX_CONTROL_RESUME_SET(x) (((x) << MBOX0_DMA_RX_CONTROL_RESUME_LSB) & MBOX0_DMA_RX_CONTROL_RESUME_MASK)
-#define MBOX0_DMA_RX_CONTROL_START_MSB 1
-#define MBOX0_DMA_RX_CONTROL_START_LSB 1
-#define MBOX0_DMA_RX_CONTROL_START_MASK 0x00000002
-#define MBOX0_DMA_RX_CONTROL_START_GET(x) (((x) & MBOX0_DMA_RX_CONTROL_START_MASK) >> MBOX0_DMA_RX_CONTROL_START_LSB)
-#define MBOX0_DMA_RX_CONTROL_START_SET(x) (((x) << MBOX0_DMA_RX_CONTROL_START_LSB) & MBOX0_DMA_RX_CONTROL_START_MASK)
-#define MBOX0_DMA_RX_CONTROL_STOP_MSB 0
-#define MBOX0_DMA_RX_CONTROL_STOP_LSB 0
-#define MBOX0_DMA_RX_CONTROL_STOP_MASK 0x00000001
-#define MBOX0_DMA_RX_CONTROL_STOP_GET(x) (((x) & MBOX0_DMA_RX_CONTROL_STOP_MASK) >> MBOX0_DMA_RX_CONTROL_STOP_LSB)
-#define MBOX0_DMA_RX_CONTROL_STOP_SET(x) (((x) << MBOX0_DMA_RX_CONTROL_STOP_LSB) & MBOX0_DMA_RX_CONTROL_STOP_MASK)
-
-#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000020
-#define MBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000020
-#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
-#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
-#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
-#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
-#define MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
-
-#define MBOX0_DMA_TX_CONTROL_ADDRESS 0x00000024
-#define MBOX0_DMA_TX_CONTROL_OFFSET 0x00000024
-#define MBOX0_DMA_TX_CONTROL_RESUME_MSB 2
-#define MBOX0_DMA_TX_CONTROL_RESUME_LSB 2
-#define MBOX0_DMA_TX_CONTROL_RESUME_MASK 0x00000004
-#define MBOX0_DMA_TX_CONTROL_RESUME_GET(x) (((x) & MBOX0_DMA_TX_CONTROL_RESUME_MASK) >> MBOX0_DMA_TX_CONTROL_RESUME_LSB)
-#define MBOX0_DMA_TX_CONTROL_RESUME_SET(x) (((x) << MBOX0_DMA_TX_CONTROL_RESUME_LSB) & MBOX0_DMA_TX_CONTROL_RESUME_MASK)
-#define MBOX0_DMA_TX_CONTROL_START_MSB 1
-#define MBOX0_DMA_TX_CONTROL_START_LSB 1
-#define MBOX0_DMA_TX_CONTROL_START_MASK 0x00000002
-#define MBOX0_DMA_TX_CONTROL_START_GET(x) (((x) & MBOX0_DMA_TX_CONTROL_START_MASK) >> MBOX0_DMA_TX_CONTROL_START_LSB)
-#define MBOX0_DMA_TX_CONTROL_START_SET(x) (((x) << MBOX0_DMA_TX_CONTROL_START_LSB) & MBOX0_DMA_TX_CONTROL_START_MASK)
-#define MBOX0_DMA_TX_CONTROL_STOP_MSB 0
-#define MBOX0_DMA_TX_CONTROL_STOP_LSB 0
-#define MBOX0_DMA_TX_CONTROL_STOP_MASK 0x00000001
-#define MBOX0_DMA_TX_CONTROL_STOP_GET(x) (((x) & MBOX0_DMA_TX_CONTROL_STOP_MASK) >> MBOX0_DMA_TX_CONTROL_STOP_LSB)
-#define MBOX0_DMA_TX_CONTROL_STOP_SET(x) (((x) << MBOX0_DMA_TX_CONTROL_STOP_LSB) & MBOX0_DMA_TX_CONTROL_STOP_MASK)
-
-#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000028
-#define MBOX1_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000028
-#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
-#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
-#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
-#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
-#define MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX1_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
-
-#define MBOX1_DMA_RX_CONTROL_ADDRESS 0x0000002c
-#define MBOX1_DMA_RX_CONTROL_OFFSET 0x0000002c
-#define MBOX1_DMA_RX_CONTROL_RESUME_MSB 2
-#define MBOX1_DMA_RX_CONTROL_RESUME_LSB 2
-#define MBOX1_DMA_RX_CONTROL_RESUME_MASK 0x00000004
-#define MBOX1_DMA_RX_CONTROL_RESUME_GET(x) (((x) & MBOX1_DMA_RX_CONTROL_RESUME_MASK) >> MBOX1_DMA_RX_CONTROL_RESUME_LSB)
-#define MBOX1_DMA_RX_CONTROL_RESUME_SET(x) (((x) << MBOX1_DMA_RX_CONTROL_RESUME_LSB) & MBOX1_DMA_RX_CONTROL_RESUME_MASK)
-#define MBOX1_DMA_RX_CONTROL_START_MSB 1
-#define MBOX1_DMA_RX_CONTROL_START_LSB 1
-#define MBOX1_DMA_RX_CONTROL_START_MASK 0x00000002
-#define MBOX1_DMA_RX_CONTROL_START_GET(x) (((x) & MBOX1_DMA_RX_CONTROL_START_MASK) >> MBOX1_DMA_RX_CONTROL_START_LSB)
-#define MBOX1_DMA_RX_CONTROL_START_SET(x) (((x) << MBOX1_DMA_RX_CONTROL_START_LSB) & MBOX1_DMA_RX_CONTROL_START_MASK)
-#define MBOX1_DMA_RX_CONTROL_STOP_MSB 0
-#define MBOX1_DMA_RX_CONTROL_STOP_LSB 0
-#define MBOX1_DMA_RX_CONTROL_STOP_MASK 0x00000001
-#define MBOX1_DMA_RX_CONTROL_STOP_GET(x) (((x) & MBOX1_DMA_RX_CONTROL_STOP_MASK) >> MBOX1_DMA_RX_CONTROL_STOP_LSB)
-#define MBOX1_DMA_RX_CONTROL_STOP_SET(x) (((x) << MBOX1_DMA_RX_CONTROL_STOP_LSB) & MBOX1_DMA_RX_CONTROL_STOP_MASK)
-
-#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000030
-#define MBOX1_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000030
-#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
-#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
-#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
-#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
-#define MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX1_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
-
-#define MBOX1_DMA_TX_CONTROL_ADDRESS 0x00000034
-#define MBOX1_DMA_TX_CONTROL_OFFSET 0x00000034
-#define MBOX1_DMA_TX_CONTROL_RESUME_MSB 2
-#define MBOX1_DMA_TX_CONTROL_RESUME_LSB 2
-#define MBOX1_DMA_TX_CONTROL_RESUME_MASK 0x00000004
-#define MBOX1_DMA_TX_CONTROL_RESUME_GET(x) (((x) & MBOX1_DMA_TX_CONTROL_RESUME_MASK) >> MBOX1_DMA_TX_CONTROL_RESUME_LSB)
-#define MBOX1_DMA_TX_CONTROL_RESUME_SET(x) (((x) << MBOX1_DMA_TX_CONTROL_RESUME_LSB) & MBOX1_DMA_TX_CONTROL_RESUME_MASK)
-#define MBOX1_DMA_TX_CONTROL_START_MSB 1
-#define MBOX1_DMA_TX_CONTROL_START_LSB 1
-#define MBOX1_DMA_TX_CONTROL_START_MASK 0x00000002
-#define MBOX1_DMA_TX_CONTROL_START_GET(x) (((x) & MBOX1_DMA_TX_CONTROL_START_MASK) >> MBOX1_DMA_TX_CONTROL_START_LSB)
-#define MBOX1_DMA_TX_CONTROL_START_SET(x) (((x) << MBOX1_DMA_TX_CONTROL_START_LSB) & MBOX1_DMA_TX_CONTROL_START_MASK)
-#define MBOX1_DMA_TX_CONTROL_STOP_MSB 0
-#define MBOX1_DMA_TX_CONTROL_STOP_LSB 0
-#define MBOX1_DMA_TX_CONTROL_STOP_MASK 0x00000001
-#define MBOX1_DMA_TX_CONTROL_STOP_GET(x) (((x) & MBOX1_DMA_TX_CONTROL_STOP_MASK) >> MBOX1_DMA_TX_CONTROL_STOP_LSB)
-#define MBOX1_DMA_TX_CONTROL_STOP_SET(x) (((x) << MBOX1_DMA_TX_CONTROL_STOP_LSB) & MBOX1_DMA_TX_CONTROL_STOP_MASK)
-
-#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000038
-#define MBOX2_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000038
-#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
-#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
-#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
-#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
-#define MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX2_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
-
-#define MBOX2_DMA_RX_CONTROL_ADDRESS 0x0000003c
-#define MBOX2_DMA_RX_CONTROL_OFFSET 0x0000003c
-#define MBOX2_DMA_RX_CONTROL_RESUME_MSB 2
-#define MBOX2_DMA_RX_CONTROL_RESUME_LSB 2
-#define MBOX2_DMA_RX_CONTROL_RESUME_MASK 0x00000004
-#define MBOX2_DMA_RX_CONTROL_RESUME_GET(x) (((x) & MBOX2_DMA_RX_CONTROL_RESUME_MASK) >> MBOX2_DMA_RX_CONTROL_RESUME_LSB)
-#define MBOX2_DMA_RX_CONTROL_RESUME_SET(x) (((x) << MBOX2_DMA_RX_CONTROL_RESUME_LSB) & MBOX2_DMA_RX_CONTROL_RESUME_MASK)
-#define MBOX2_DMA_RX_CONTROL_START_MSB 1
-#define MBOX2_DMA_RX_CONTROL_START_LSB 1
-#define MBOX2_DMA_RX_CONTROL_START_MASK 0x00000002
-#define MBOX2_DMA_RX_CONTROL_START_GET(x) (((x) & MBOX2_DMA_RX_CONTROL_START_MASK) >> MBOX2_DMA_RX_CONTROL_START_LSB)
-#define MBOX2_DMA_RX_CONTROL_START_SET(x) (((x) << MBOX2_DMA_RX_CONTROL_START_LSB) & MBOX2_DMA_RX_CONTROL_START_MASK)
-#define MBOX2_DMA_RX_CONTROL_STOP_MSB 0
-#define MBOX2_DMA_RX_CONTROL_STOP_LSB 0
-#define MBOX2_DMA_RX_CONTROL_STOP_MASK 0x00000001
-#define MBOX2_DMA_RX_CONTROL_STOP_GET(x) (((x) & MBOX2_DMA_RX_CONTROL_STOP_MASK) >> MBOX2_DMA_RX_CONTROL_STOP_LSB)
-#define MBOX2_DMA_RX_CONTROL_STOP_SET(x) (((x) << MBOX2_DMA_RX_CONTROL_STOP_LSB) & MBOX2_DMA_RX_CONTROL_STOP_MASK)
-
-#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000040
-#define MBOX2_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000040
-#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
-#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
-#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
-#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
-#define MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX2_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
-
-#define MBOX2_DMA_TX_CONTROL_ADDRESS 0x00000044
-#define MBOX2_DMA_TX_CONTROL_OFFSET 0x00000044
-#define MBOX2_DMA_TX_CONTROL_RESUME_MSB 2
-#define MBOX2_DMA_TX_CONTROL_RESUME_LSB 2
-#define MBOX2_DMA_TX_CONTROL_RESUME_MASK 0x00000004
-#define MBOX2_DMA_TX_CONTROL_RESUME_GET(x) (((x) & MBOX2_DMA_TX_CONTROL_RESUME_MASK) >> MBOX2_DMA_TX_CONTROL_RESUME_LSB)
-#define MBOX2_DMA_TX_CONTROL_RESUME_SET(x) (((x) << MBOX2_DMA_TX_CONTROL_RESUME_LSB) & MBOX2_DMA_TX_CONTROL_RESUME_MASK)
-#define MBOX2_DMA_TX_CONTROL_START_MSB 1
-#define MBOX2_DMA_TX_CONTROL_START_LSB 1
-#define MBOX2_DMA_TX_CONTROL_START_MASK 0x00000002
-#define MBOX2_DMA_TX_CONTROL_START_GET(x) (((x) & MBOX2_DMA_TX_CONTROL_START_MASK) >> MBOX2_DMA_TX_CONTROL_START_LSB)
-#define MBOX2_DMA_TX_CONTROL_START_SET(x) (((x) << MBOX2_DMA_TX_CONTROL_START_LSB) & MBOX2_DMA_TX_CONTROL_START_MASK)
-#define MBOX2_DMA_TX_CONTROL_STOP_MSB 0
-#define MBOX2_DMA_TX_CONTROL_STOP_LSB 0
-#define MBOX2_DMA_TX_CONTROL_STOP_MASK 0x00000001
-#define MBOX2_DMA_TX_CONTROL_STOP_GET(x) (((x) & MBOX2_DMA_TX_CONTROL_STOP_MASK) >> MBOX2_DMA_TX_CONTROL_STOP_LSB)
-#define MBOX2_DMA_TX_CONTROL_STOP_SET(x) (((x) << MBOX2_DMA_TX_CONTROL_STOP_LSB) & MBOX2_DMA_TX_CONTROL_STOP_MASK)
-
-#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000048
-#define MBOX3_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000048
-#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
-#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
-#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
-#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
-#define MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX3_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
-
-#define MBOX3_DMA_RX_CONTROL_ADDRESS 0x0000004c
-#define MBOX3_DMA_RX_CONTROL_OFFSET 0x0000004c
-#define MBOX3_DMA_RX_CONTROL_RESUME_MSB 2
-#define MBOX3_DMA_RX_CONTROL_RESUME_LSB 2
-#define MBOX3_DMA_RX_CONTROL_RESUME_MASK 0x00000004
-#define MBOX3_DMA_RX_CONTROL_RESUME_GET(x) (((x) & MBOX3_DMA_RX_CONTROL_RESUME_MASK) >> MBOX3_DMA_RX_CONTROL_RESUME_LSB)
-#define MBOX3_DMA_RX_CONTROL_RESUME_SET(x) (((x) << MBOX3_DMA_RX_CONTROL_RESUME_LSB) & MBOX3_DMA_RX_CONTROL_RESUME_MASK)
-#define MBOX3_DMA_RX_CONTROL_START_MSB 1
-#define MBOX3_DMA_RX_CONTROL_START_LSB 1
-#define MBOX3_DMA_RX_CONTROL_START_MASK 0x00000002
-#define MBOX3_DMA_RX_CONTROL_START_GET(x) (((x) & MBOX3_DMA_RX_CONTROL_START_MASK) >> MBOX3_DMA_RX_CONTROL_START_LSB)
-#define MBOX3_DMA_RX_CONTROL_START_SET(x) (((x) << MBOX3_DMA_RX_CONTROL_START_LSB) & MBOX3_DMA_RX_CONTROL_START_MASK)
-#define MBOX3_DMA_RX_CONTROL_STOP_MSB 0
-#define MBOX3_DMA_RX_CONTROL_STOP_LSB 0
-#define MBOX3_DMA_RX_CONTROL_STOP_MASK 0x00000001
-#define MBOX3_DMA_RX_CONTROL_STOP_GET(x) (((x) & MBOX3_DMA_RX_CONTROL_STOP_MASK) >> MBOX3_DMA_RX_CONTROL_STOP_LSB)
-#define MBOX3_DMA_RX_CONTROL_STOP_SET(x) (((x) << MBOX3_DMA_RX_CONTROL_STOP_LSB) & MBOX3_DMA_RX_CONTROL_STOP_MASK)
-
-#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000050
-#define MBOX3_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000050
-#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
-#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
-#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
-#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
-#define MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & MBOX3_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
-
-#define MBOX3_DMA_TX_CONTROL_ADDRESS 0x00000054
-#define MBOX3_DMA_TX_CONTROL_OFFSET 0x00000054
-#define MBOX3_DMA_TX_CONTROL_RESUME_MSB 2
-#define MBOX3_DMA_TX_CONTROL_RESUME_LSB 2
-#define MBOX3_DMA_TX_CONTROL_RESUME_MASK 0x00000004
-#define MBOX3_DMA_TX_CONTROL_RESUME_GET(x) (((x) & MBOX3_DMA_TX_CONTROL_RESUME_MASK) >> MBOX3_DMA_TX_CONTROL_RESUME_LSB)
-#define MBOX3_DMA_TX_CONTROL_RESUME_SET(x) (((x) << MBOX3_DMA_TX_CONTROL_RESUME_LSB) & MBOX3_DMA_TX_CONTROL_RESUME_MASK)
-#define MBOX3_DMA_TX_CONTROL_START_MSB 1
-#define MBOX3_DMA_TX_CONTROL_START_LSB 1
-#define MBOX3_DMA_TX_CONTROL_START_MASK 0x00000002
-#define MBOX3_DMA_TX_CONTROL_START_GET(x) (((x) & MBOX3_DMA_TX_CONTROL_START_MASK) >> MBOX3_DMA_TX_CONTROL_START_LSB)
-#define MBOX3_DMA_TX_CONTROL_START_SET(x) (((x) << MBOX3_DMA_TX_CONTROL_START_LSB) & MBOX3_DMA_TX_CONTROL_START_MASK)
-#define MBOX3_DMA_TX_CONTROL_STOP_MSB 0
-#define MBOX3_DMA_TX_CONTROL_STOP_LSB 0
-#define MBOX3_DMA_TX_CONTROL_STOP_MASK 0x00000001
-#define MBOX3_DMA_TX_CONTROL_STOP_GET(x) (((x) & MBOX3_DMA_TX_CONTROL_STOP_MASK) >> MBOX3_DMA_TX_CONTROL_STOP_LSB)
-#define MBOX3_DMA_TX_CONTROL_STOP_SET(x) (((x) << MBOX3_DMA_TX_CONTROL_STOP_LSB) & MBOX3_DMA_TX_CONTROL_STOP_MASK)
-
-#define MBOX_INT_STATUS_ADDRESS 0x00000058
-#define MBOX_INT_STATUS_OFFSET 0x00000058
-#define MBOX_INT_STATUS_RX_DMA_COMPLETE_MSB 31
-#define MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB 28
-#define MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK 0xf0000000
-#define MBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) (((x) & MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) >> MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB)
-#define MBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) (((x) << MBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) & MBOX_INT_STATUS_RX_DMA_COMPLETE_MASK)
-#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB 27
-#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB 24
-#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK 0x0f000000
-#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) (((x) & MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) >> MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB)
-#define MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) (((x) << MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) & MBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK)
-#define MBOX_INT_STATUS_TX_DMA_COMPLETE_MSB 23
-#define MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB 20
-#define MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK 0x00f00000
-#define MBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) (((x) & MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) >> MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB)
-#define MBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) (((x) << MBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) & MBOX_INT_STATUS_TX_DMA_COMPLETE_MASK)
-#define MBOX_INT_STATUS_TX_OVERFLOW_MSB 17
-#define MBOX_INT_STATUS_TX_OVERFLOW_LSB 17
-#define MBOX_INT_STATUS_TX_OVERFLOW_MASK 0x00020000
-#define MBOX_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & MBOX_INT_STATUS_TX_OVERFLOW_MASK) >> MBOX_INT_STATUS_TX_OVERFLOW_LSB)
-#define MBOX_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << MBOX_INT_STATUS_TX_OVERFLOW_LSB) & MBOX_INT_STATUS_TX_OVERFLOW_MASK)
-#define MBOX_INT_STATUS_RX_UNDERFLOW_MSB 16
-#define MBOX_INT_STATUS_RX_UNDERFLOW_LSB 16
-#define MBOX_INT_STATUS_RX_UNDERFLOW_MASK 0x00010000
-#define MBOX_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & MBOX_INT_STATUS_RX_UNDERFLOW_MASK) >> MBOX_INT_STATUS_RX_UNDERFLOW_LSB)
-#define MBOX_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << MBOX_INT_STATUS_RX_UNDERFLOW_LSB) & MBOX_INT_STATUS_RX_UNDERFLOW_MASK)
-#define MBOX_INT_STATUS_TX_NOT_EMPTY_MSB 15
-#define MBOX_INT_STATUS_TX_NOT_EMPTY_LSB 12
-#define MBOX_INT_STATUS_TX_NOT_EMPTY_MASK 0x0000f000
-#define MBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) (((x) & MBOX_INT_STATUS_TX_NOT_EMPTY_MASK) >> MBOX_INT_STATUS_TX_NOT_EMPTY_LSB)
-#define MBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) (((x) << MBOX_INT_STATUS_TX_NOT_EMPTY_LSB) & MBOX_INT_STATUS_TX_NOT_EMPTY_MASK)
-#define MBOX_INT_STATUS_RX_NOT_FULL_MSB 11
-#define MBOX_INT_STATUS_RX_NOT_FULL_LSB 8
-#define MBOX_INT_STATUS_RX_NOT_FULL_MASK 0x00000f00
-#define MBOX_INT_STATUS_RX_NOT_FULL_GET(x) (((x) & MBOX_INT_STATUS_RX_NOT_FULL_MASK) >> MBOX_INT_STATUS_RX_NOT_FULL_LSB)
-#define MBOX_INT_STATUS_RX_NOT_FULL_SET(x) (((x) << MBOX_INT_STATUS_RX_NOT_FULL_LSB) & MBOX_INT_STATUS_RX_NOT_FULL_MASK)
-#define MBOX_INT_STATUS_HOST_MSB 7
-#define MBOX_INT_STATUS_HOST_LSB 0
-#define MBOX_INT_STATUS_HOST_MASK 0x000000ff
-#define MBOX_INT_STATUS_HOST_GET(x) (((x) & MBOX_INT_STATUS_HOST_MASK) >> MBOX_INT_STATUS_HOST_LSB)
-#define MBOX_INT_STATUS_HOST_SET(x) (((x) << MBOX_INT_STATUS_HOST_LSB) & MBOX_INT_STATUS_HOST_MASK)
-
-#define MBOX_INT_ENABLE_ADDRESS 0x0000005c
-#define MBOX_INT_ENABLE_OFFSET 0x0000005c
-#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB 31
-#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB 28
-#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK 0xf0000000
-#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) (((x) & MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) >> MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB)
-#define MBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) (((x) << MBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) & MBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK)
-#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB 27
-#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB 24
-#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK 0x0f000000
-#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) (((x) & MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) >> MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB)
-#define MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) (((x) << MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) & MBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK)
-#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB 23
-#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB 20
-#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK 0x00f00000
-#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) (((x) & MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) >> MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB)
-#define MBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) (((x) << MBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) & MBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK)
-#define MBOX_INT_ENABLE_TX_OVERFLOW_MSB 17
-#define MBOX_INT_ENABLE_TX_OVERFLOW_LSB 17
-#define MBOX_INT_ENABLE_TX_OVERFLOW_MASK 0x00020000
-#define MBOX_INT_ENABLE_TX_OVERFLOW_GET(x) (((x) & MBOX_INT_ENABLE_TX_OVERFLOW_MASK) >> MBOX_INT_ENABLE_TX_OVERFLOW_LSB)
-#define MBOX_INT_ENABLE_TX_OVERFLOW_SET(x) (((x) << MBOX_INT_ENABLE_TX_OVERFLOW_LSB) & MBOX_INT_ENABLE_TX_OVERFLOW_MASK)
-#define MBOX_INT_ENABLE_RX_UNDERFLOW_MSB 16
-#define MBOX_INT_ENABLE_RX_UNDERFLOW_LSB 16
-#define MBOX_INT_ENABLE_RX_UNDERFLOW_MASK 0x00010000
-#define MBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) (((x) & MBOX_INT_ENABLE_RX_UNDERFLOW_MASK) >> MBOX_INT_ENABLE_RX_UNDERFLOW_LSB)
-#define MBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) (((x) << MBOX_INT_ENABLE_RX_UNDERFLOW_LSB) & MBOX_INT_ENABLE_RX_UNDERFLOW_MASK)
-#define MBOX_INT_ENABLE_TX_NOT_EMPTY_MSB 15
-#define MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB 12
-#define MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK 0x0000f000
-#define MBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) (((x) & MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) >> MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB)
-#define MBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) (((x) << MBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) & MBOX_INT_ENABLE_TX_NOT_EMPTY_MASK)
-#define MBOX_INT_ENABLE_RX_NOT_FULL_MSB 11
-#define MBOX_INT_ENABLE_RX_NOT_FULL_LSB 8
-#define MBOX_INT_ENABLE_RX_NOT_FULL_MASK 0x00000f00
-#define MBOX_INT_ENABLE_RX_NOT_FULL_GET(x) (((x) & MBOX_INT_ENABLE_RX_NOT_FULL_MASK) >> MBOX_INT_ENABLE_RX_NOT_FULL_LSB)
-#define MBOX_INT_ENABLE_RX_NOT_FULL_SET(x) (((x) << MBOX_INT_ENABLE_RX_NOT_FULL_LSB) & MBOX_INT_ENABLE_RX_NOT_FULL_MASK)
-#define MBOX_INT_ENABLE_HOST_MSB 7
-#define MBOX_INT_ENABLE_HOST_LSB 0
-#define MBOX_INT_ENABLE_HOST_MASK 0x000000ff
-#define MBOX_INT_ENABLE_HOST_GET(x) (((x) & MBOX_INT_ENABLE_HOST_MASK) >> MBOX_INT_ENABLE_HOST_LSB)
-#define MBOX_INT_ENABLE_HOST_SET(x) (((x) << MBOX_INT_ENABLE_HOST_LSB) & MBOX_INT_ENABLE_HOST_MASK)
-
-#define INT_HOST_ADDRESS 0x00000060
-#define INT_HOST_OFFSET 0x00000060
-#define INT_HOST_VECTOR_MSB 7
-#define INT_HOST_VECTOR_LSB 0
-#define INT_HOST_VECTOR_MASK 0x000000ff
-#define INT_HOST_VECTOR_GET(x) (((x) & INT_HOST_VECTOR_MASK) >> INT_HOST_VECTOR_LSB)
-#define INT_HOST_VECTOR_SET(x) (((x) << INT_HOST_VECTOR_LSB) & INT_HOST_VECTOR_MASK)
-
-#define LOCAL_COUNT_ADDRESS 0x00000080
-#define LOCAL_COUNT_OFFSET 0x00000080
-#define LOCAL_COUNT_VALUE_MSB 7
-#define LOCAL_COUNT_VALUE_LSB 0
-#define LOCAL_COUNT_VALUE_MASK 0x000000ff
-#define LOCAL_COUNT_VALUE_GET(x) (((x) & LOCAL_COUNT_VALUE_MASK) >> LOCAL_COUNT_VALUE_LSB)
-#define LOCAL_COUNT_VALUE_SET(x) (((x) << LOCAL_COUNT_VALUE_LSB) & LOCAL_COUNT_VALUE_MASK)
-
-#define COUNT_INC_ADDRESS 0x000000a0
-#define COUNT_INC_OFFSET 0x000000a0
-#define COUNT_INC_VALUE_MSB 7
-#define COUNT_INC_VALUE_LSB 0
-#define COUNT_INC_VALUE_MASK 0x000000ff
-#define COUNT_INC_VALUE_GET(x) (((x) & COUNT_INC_VALUE_MASK) >> COUNT_INC_VALUE_LSB)
-#define COUNT_INC_VALUE_SET(x) (((x) << COUNT_INC_VALUE_LSB) & COUNT_INC_VALUE_MASK)
-
-#define LOCAL_SCRATCH_ADDRESS 0x000000c0
-#define LOCAL_SCRATCH_OFFSET 0x000000c0
-#define LOCAL_SCRATCH_VALUE_MSB 7
-#define LOCAL_SCRATCH_VALUE_LSB 0
-#define LOCAL_SCRATCH_VALUE_MASK 0x000000ff
-#define LOCAL_SCRATCH_VALUE_GET(x) (((x) & LOCAL_SCRATCH_VALUE_MASK) >> LOCAL_SCRATCH_VALUE_LSB)
-#define LOCAL_SCRATCH_VALUE_SET(x) (((x) << LOCAL_SCRATCH_VALUE_LSB) & LOCAL_SCRATCH_VALUE_MASK)
-
-#define USE_LOCAL_BUS_ADDRESS 0x000000e0
-#define USE_LOCAL_BUS_OFFSET 0x000000e0
-#define USE_LOCAL_BUS_PIN_INIT_MSB 0
-#define USE_LOCAL_BUS_PIN_INIT_LSB 0
-#define USE_LOCAL_BUS_PIN_INIT_MASK 0x00000001
-#define USE_LOCAL_BUS_PIN_INIT_GET(x) (((x) & USE_LOCAL_BUS_PIN_INIT_MASK) >> USE_LOCAL_BUS_PIN_INIT_LSB)
-#define USE_LOCAL_BUS_PIN_INIT_SET(x) (((x) << USE_LOCAL_BUS_PIN_INIT_LSB) & USE_LOCAL_BUS_PIN_INIT_MASK)
-
-#define SDIO_CONFIG_ADDRESS 0x000000e4
-#define SDIO_CONFIG_OFFSET 0x000000e4
-#define SDIO_CONFIG_CCCR_IOR1_MSB 0
-#define SDIO_CONFIG_CCCR_IOR1_LSB 0
-#define SDIO_CONFIG_CCCR_IOR1_MASK 0x00000001
-#define SDIO_CONFIG_CCCR_IOR1_GET(x) (((x) & SDIO_CONFIG_CCCR_IOR1_MASK) >> SDIO_CONFIG_CCCR_IOR1_LSB)
-#define SDIO_CONFIG_CCCR_IOR1_SET(x) (((x) << SDIO_CONFIG_CCCR_IOR1_LSB) & SDIO_CONFIG_CCCR_IOR1_MASK)
-
-#define MBOX_DEBUG_ADDRESS 0x000000e8
-#define MBOX_DEBUG_OFFSET 0x000000e8
-#define MBOX_DEBUG_SEL_MSB 2
-#define MBOX_DEBUG_SEL_LSB 0
-#define MBOX_DEBUG_SEL_MASK 0x00000007
-#define MBOX_DEBUG_SEL_GET(x) (((x) & MBOX_DEBUG_SEL_MASK) >> MBOX_DEBUG_SEL_LSB)
-#define MBOX_DEBUG_SEL_SET(x) (((x) << MBOX_DEBUG_SEL_LSB) & MBOX_DEBUG_SEL_MASK)
-
-#define MBOX_FIFO_RESET_ADDRESS 0x000000ec
-#define MBOX_FIFO_RESET_OFFSET 0x000000ec
-#define MBOX_FIFO_RESET_INIT_MSB 0
-#define MBOX_FIFO_RESET_INIT_LSB 0
-#define MBOX_FIFO_RESET_INIT_MASK 0x00000001
-#define MBOX_FIFO_RESET_INIT_GET(x) (((x) & MBOX_FIFO_RESET_INIT_MASK) >> MBOX_FIFO_RESET_INIT_LSB)
-#define MBOX_FIFO_RESET_INIT_SET(x) (((x) << MBOX_FIFO_RESET_INIT_LSB) & MBOX_FIFO_RESET_INIT_MASK)
-
-#define MBOX_TXFIFO_POP_ADDRESS 0x000000f0
-#define MBOX_TXFIFO_POP_OFFSET 0x000000f0
-#define MBOX_TXFIFO_POP_DATA_MSB 0
-#define MBOX_TXFIFO_POP_DATA_LSB 0
-#define MBOX_TXFIFO_POP_DATA_MASK 0x00000001
-#define MBOX_TXFIFO_POP_DATA_GET(x) (((x) & MBOX_TXFIFO_POP_DATA_MASK) >> MBOX_TXFIFO_POP_DATA_LSB)
-#define MBOX_TXFIFO_POP_DATA_SET(x) (((x) << MBOX_TXFIFO_POP_DATA_LSB) & MBOX_TXFIFO_POP_DATA_MASK)
-
-#define MBOX_RXFIFO_POP_ADDRESS 0x00000100
-#define MBOX_RXFIFO_POP_OFFSET 0x00000100
-#define MBOX_RXFIFO_POP_DATA_MSB 0
-#define MBOX_RXFIFO_POP_DATA_LSB 0
-#define MBOX_RXFIFO_POP_DATA_MASK 0x00000001
-#define MBOX_RXFIFO_POP_DATA_GET(x) (((x) & MBOX_RXFIFO_POP_DATA_MASK) >> MBOX_RXFIFO_POP_DATA_LSB)
-#define MBOX_RXFIFO_POP_DATA_SET(x) (((x) << MBOX_RXFIFO_POP_DATA_LSB) & MBOX_RXFIFO_POP_DATA_MASK)
-
-#define SDIO_DEBUG_ADDRESS 0x00000110
-#define SDIO_DEBUG_OFFSET 0x00000110
-#define SDIO_DEBUG_SEL_MSB 3
-#define SDIO_DEBUG_SEL_LSB 0
-#define SDIO_DEBUG_SEL_MASK 0x0000000f
-#define SDIO_DEBUG_SEL_GET(x) (((x) & SDIO_DEBUG_SEL_MASK) >> SDIO_DEBUG_SEL_LSB)
-#define SDIO_DEBUG_SEL_SET(x) (((x) << SDIO_DEBUG_SEL_LSB) & SDIO_DEBUG_SEL_MASK)
-
-#define HOST_IF_WINDOW_ADDRESS 0x00002000
-#define HOST_IF_WINDOW_OFFSET 0x00002000
-#define HOST_IF_WINDOW_DATA_MSB 7
-#define HOST_IF_WINDOW_DATA_LSB 0
-#define HOST_IF_WINDOW_DATA_MASK 0x000000ff
-#define HOST_IF_WINDOW_DATA_GET(x) (((x) & HOST_IF_WINDOW_DATA_MASK) >> HOST_IF_WINDOW_DATA_LSB)
-#define HOST_IF_WINDOW_DATA_SET(x) (((x) << HOST_IF_WINDOW_DATA_LSB) & HOST_IF_WINDOW_DATA_MASK)
-
-
-#ifndef __ASSEMBLER__
-
-typedef struct mbox_reg_reg_s {
- volatile unsigned int mbox_fifo[4];
- volatile unsigned int mbox_fifo_status;
- volatile unsigned int mbox_dma_policy;
- volatile unsigned int mbox0_dma_rx_descriptor_base;
- volatile unsigned int mbox0_dma_rx_control;
- volatile unsigned int mbox0_dma_tx_descriptor_base;
- volatile unsigned int mbox0_dma_tx_control;
- volatile unsigned int mbox1_dma_rx_descriptor_base;
- volatile unsigned int mbox1_dma_rx_control;
- volatile unsigned int mbox1_dma_tx_descriptor_base;
- volatile unsigned int mbox1_dma_tx_control;
- volatile unsigned int mbox2_dma_rx_descriptor_base;
- volatile unsigned int mbox2_dma_rx_control;
- volatile unsigned int mbox2_dma_tx_descriptor_base;
- volatile unsigned int mbox2_dma_tx_control;
- volatile unsigned int mbox3_dma_rx_descriptor_base;
- volatile unsigned int mbox3_dma_rx_control;
- volatile unsigned int mbox3_dma_tx_descriptor_base;
- volatile unsigned int mbox3_dma_tx_control;
- volatile unsigned int mbox_int_status;
- volatile unsigned int mbox_int_enable;
- volatile unsigned int int_host;
- unsigned char pad0[28]; /* pad to 0x80 */
- volatile unsigned int local_count[8];
- volatile unsigned int count_inc[8];
- volatile unsigned int local_scratch[8];
- volatile unsigned int use_local_bus;
- volatile unsigned int sdio_config;
- volatile unsigned int mbox_debug;
- volatile unsigned int mbox_fifo_reset;
- volatile unsigned int mbox_txfifo_pop[4];
- volatile unsigned int mbox_rxfifo_pop[4];
- volatile unsigned int sdio_debug;
- unsigned char pad1[7916]; /* pad to 0x2000 */
- volatile unsigned int host_if_window[2048];
-} mbox_reg_reg_t;
-
-#endif /* __ASSEMBLER__ */
-
-#endif /* _MBOX_REG_H_ */
diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw2.0/hw/rtc_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw2.0/hw/rtc_reg.h
deleted file mode 100644
index 8b3980a..0000000
--- a/drivers/staging/ath6kl/include/common/AR6002/hw2.0/hw/rtc_reg.h
+++ /dev/null
@@ -1,1163 +0,0 @@
-#ifndef _RTC_REG_REG_H_
-#define _RTC_REG_REG_H_
-
-#define RESET_CONTROL_ADDRESS 0x00000000
-#define RESET_CONTROL_OFFSET 0x00000000
-#define RESET_CONTROL_CPU_INIT_RESET_MSB 11
-#define RESET_CONTROL_CPU_INIT_RESET_LSB 11
-#define RESET_CONTROL_CPU_INIT_RESET_MASK 0x00000800
-#define RESET_CONTROL_CPU_INIT_RESET_GET(x) (((x) & RESET_CONTROL_CPU_INIT_RESET_MASK) >> RESET_CONTROL_CPU_INIT_RESET_LSB)
-#define RESET_CONTROL_CPU_INIT_RESET_SET(x) (((x) << RESET_CONTROL_CPU_INIT_RESET_LSB) & RESET_CONTROL_CPU_INIT_RESET_MASK)
-#define RESET_CONTROL_VMC_REMAP_RESET_MSB 10
-#define RESET_CONTROL_VMC_REMAP_RESET_LSB 10
-#define RESET_CONTROL_VMC_REMAP_RESET_MASK 0x00000400
-#define RESET_CONTROL_VMC_REMAP_RESET_GET(x) (((x) & RESET_CONTROL_VMC_REMAP_RESET_MASK) >> RESET_CONTROL_VMC_REMAP_RESET_LSB)
-#define RESET_CONTROL_VMC_REMAP_RESET_SET(x) (((x) << RESET_CONTROL_VMC_REMAP_RESET_LSB) & RESET_CONTROL_VMC_REMAP_RESET_MASK)
-#define RESET_CONTROL_RST_OUT_MSB 9
-#define RESET_CONTROL_RST_OUT_LSB 9
-#define RESET_CONTROL_RST_OUT_MASK 0x00000200
-#define RESET_CONTROL_RST_OUT_GET(x) (((x) & RESET_CONTROL_RST_OUT_MASK) >> RESET_CONTROL_RST_OUT_LSB)
-#define RESET_CONTROL_RST_OUT_SET(x) (((x) << RESET_CONTROL_RST_OUT_LSB) & RESET_CONTROL_RST_OUT_MASK)
-#define RESET_CONTROL_COLD_RST_MSB 8
-#define RESET_CONTROL_COLD_RST_LSB 8
-#define RESET_CONTROL_COLD_RST_MASK 0x00000100
-#define RESET_CONTROL_COLD_RST_GET(x) (((x) & RESET_CONTROL_COLD_RST_MASK) >> RESET_CONTROL_COLD_RST_LSB)
-#define RESET_CONTROL_COLD_RST_SET(x) (((x) << RESET_CONTROL_COLD_RST_LSB) & RESET_CONTROL_COLD_RST_MASK)
-#define RESET_CONTROL_WARM_RST_MSB 7
-#define RESET_CONTROL_WARM_RST_LSB 7
-#define RESET_CONTROL_WARM_RST_MASK 0x00000080
-#define RESET_CONTROL_WARM_RST_GET(x) (((x) & RESET_CONTROL_WARM_RST_MASK) >> RESET_CONTROL_WARM_RST_LSB)
-#define RESET_CONTROL_WARM_RST_SET(x) (((x) << RESET_CONTROL_WARM_RST_LSB) & RESET_CONTROL_WARM_RST_MASK)
-#define RESET_CONTROL_CPU_WARM_RST_MSB 6
-#define RESET_CONTROL_CPU_WARM_RST_LSB 6
-#define RESET_CONTROL_CPU_WARM_RST_MASK 0x00000040
-#define RESET_CONTROL_CPU_WARM_RST_GET(x) (((x) & RESET_CONTROL_CPU_WARM_RST_MASK) >> RESET_CONTROL_CPU_WARM_RST_LSB)
-#define RESET_CONTROL_CPU_WARM_RST_SET(x) (((x) << RESET_CONTROL_CPU_WARM_RST_LSB) & RESET_CONTROL_CPU_WARM_RST_MASK)
-#define RESET_CONTROL_MAC_COLD_RST_MSB 5
-#define RESET_CONTROL_MAC_COLD_RST_LSB 5
-#define RESET_CONTROL_MAC_COLD_RST_MASK 0x00000020
-#define RESET_CONTROL_MAC_COLD_RST_GET(x) (((x) & RESET_CONTROL_MAC_COLD_RST_MASK) >> RESET_CONTROL_MAC_COLD_RST_LSB)
-#define RESET_CONTROL_MAC_COLD_RST_SET(x) (((x) << RESET_CONTROL_MAC_COLD_RST_LSB) & RESET_CONTROL_MAC_COLD_RST_MASK)
-#define RESET_CONTROL_MAC_WARM_RST_MSB 4
-#define RESET_CONTROL_MAC_WARM_RST_LSB 4
-#define RESET_CONTROL_MAC_WARM_RST_MASK 0x00000010
-#define RESET_CONTROL_MAC_WARM_RST_GET(x) (((x) & RESET_CONTROL_MAC_WARM_RST_MASK) >> RESET_CONTROL_MAC_WARM_RST_LSB)
-#define RESET_CONTROL_MAC_WARM_RST_SET(x) (((x) << RESET_CONTROL_MAC_WARM_RST_LSB) & RESET_CONTROL_MAC_WARM_RST_MASK)
-#define RESET_CONTROL_MBOX_RST_MSB 2
-#define RESET_CONTROL_MBOX_RST_LSB 2
-#define RESET_CONTROL_MBOX_RST_MASK 0x00000004
-#define RESET_CONTROL_MBOX_RST_GET(x) (((x) & RESET_CONTROL_MBOX_RST_MASK) >> RESET_CONTROL_MBOX_RST_LSB)
-#define RESET_CONTROL_MBOX_RST_SET(x) (((x) << RESET_CONTROL_MBOX_RST_LSB) & RESET_CONTROL_MBOX_RST_MASK)
-#define RESET_CONTROL_UART_RST_MSB 1
-#define RESET_CONTROL_UART_RST_LSB 1
-#define RESET_CONTROL_UART_RST_MASK 0x00000002
-#define RESET_CONTROL_UART_RST_GET(x) (((x) & RESET_CONTROL_UART_RST_MASK) >> RESET_CONTROL_UART_RST_LSB)
-#define RESET_CONTROL_UART_RST_SET(x) (((x) << RESET_CONTROL_UART_RST_LSB) & RESET_CONTROL_UART_RST_MASK)
-#define RESET_CONTROL_SI0_RST_MSB 0
-#define RESET_CONTROL_SI0_RST_LSB 0
-#define RESET_CONTROL_SI0_RST_MASK 0x00000001
-#define RESET_CONTROL_SI0_RST_GET(x) (((x) & RESET_CONTROL_SI0_RST_MASK) >> RESET_CONTROL_SI0_RST_LSB)
-#define RESET_CONTROL_SI0_RST_SET(x) (((x) << RESET_CONTROL_SI0_RST_LSB) & RESET_CONTROL_SI0_RST_MASK)
-
-#define XTAL_CONTROL_ADDRESS 0x00000004
-#define XTAL_CONTROL_OFFSET 0x00000004
-#define XTAL_CONTROL_TCXO_MSB 0
-#define XTAL_CONTROL_TCXO_LSB 0
-#define XTAL_CONTROL_TCXO_MASK 0x00000001
-#define XTAL_CONTROL_TCXO_GET(x) (((x) & XTAL_CONTROL_TCXO_MASK) >> XTAL_CONTROL_TCXO_LSB)
-#define XTAL_CONTROL_TCXO_SET(x) (((x) << XTAL_CONTROL_TCXO_LSB) & XTAL_CONTROL_TCXO_MASK)
-
-#define TCXO_DETECT_ADDRESS 0x00000008
-#define TCXO_DETECT_OFFSET 0x00000008
-#define TCXO_DETECT_PRESENT_MSB 0
-#define TCXO_DETECT_PRESENT_LSB 0
-#define TCXO_DETECT_PRESENT_MASK 0x00000001
-#define TCXO_DETECT_PRESENT_GET(x) (((x) & TCXO_DETECT_PRESENT_MASK) >> TCXO_DETECT_PRESENT_LSB)
-#define TCXO_DETECT_PRESENT_SET(x) (((x) << TCXO_DETECT_PRESENT_LSB) & TCXO_DETECT_PRESENT_MASK)
-
-#define XTAL_TEST_ADDRESS 0x0000000c
-#define XTAL_TEST_OFFSET 0x0000000c
-#define XTAL_TEST_NOTCXODET_MSB 0
-#define XTAL_TEST_NOTCXODET_LSB 0
-#define XTAL_TEST_NOTCXODET_MASK 0x00000001
-#define XTAL_TEST_NOTCXODET_GET(x) (((x) & XTAL_TEST_NOTCXODET_MASK) >> XTAL_TEST_NOTCXODET_LSB)
-#define XTAL_TEST_NOTCXODET_SET(x) (((x) << XTAL_TEST_NOTCXODET_LSB) & XTAL_TEST_NOTCXODET_MASK)
-
-#define QUADRATURE_ADDRESS 0x00000010
-#define QUADRATURE_OFFSET 0x00000010
-#define QUADRATURE_ADC_MSB 5
-#define QUADRATURE_ADC_LSB 4
-#define QUADRATURE_ADC_MASK 0x00000030
-#define QUADRATURE_ADC_GET(x) (((x) & QUADRATURE_ADC_MASK) >> QUADRATURE_ADC_LSB)
-#define QUADRATURE_ADC_SET(x) (((x) << QUADRATURE_ADC_LSB) & QUADRATURE_ADC_MASK)
-#define QUADRATURE_SEL_MSB 2
-#define QUADRATURE_SEL_LSB 2
-#define QUADRATURE_SEL_MASK 0x00000004
-#define QUADRATURE_SEL_GET(x) (((x) & QUADRATURE_SEL_MASK) >> QUADRATURE_SEL_LSB)
-#define QUADRATURE_SEL_SET(x) (((x) << QUADRATURE_SEL_LSB) & QUADRATURE_SEL_MASK)
-#define QUADRATURE_DAC_MSB 1
-#define QUADRATURE_DAC_LSB 0
-#define QUADRATURE_DAC_MASK 0x00000003
-#define QUADRATURE_DAC_GET(x) (((x) & QUADRATURE_DAC_MASK) >> QUADRATURE_DAC_LSB)
-#define QUADRATURE_DAC_SET(x) (((x) << QUADRATURE_DAC_LSB) & QUADRATURE_DAC_MASK)
-
-#define PLL_CONTROL_ADDRESS 0x00000014
-#define PLL_CONTROL_OFFSET 0x00000014
-#define PLL_CONTROL_DIG_TEST_CLK_MSB 20
-#define PLL_CONTROL_DIG_TEST_CLK_LSB 20
-#define PLL_CONTROL_DIG_TEST_CLK_MASK 0x00100000
-#define PLL_CONTROL_DIG_TEST_CLK_GET(x) (((x) & PLL_CONTROL_DIG_TEST_CLK_MASK) >> PLL_CONTROL_DIG_TEST_CLK_LSB)
-#define PLL_CONTROL_DIG_TEST_CLK_SET(x) (((x) << PLL_CONTROL_DIG_TEST_CLK_LSB) & PLL_CONTROL_DIG_TEST_CLK_MASK)
-#define PLL_CONTROL_MAC_OVERRIDE_MSB 19
-#define PLL_CONTROL_MAC_OVERRIDE_LSB 19
-#define PLL_CONTROL_MAC_OVERRIDE_MASK 0x00080000
-#define PLL_CONTROL_MAC_OVERRIDE_GET(x) (((x) & PLL_CONTROL_MAC_OVERRIDE_MASK) >> PLL_CONTROL_MAC_OVERRIDE_LSB)
-#define PLL_CONTROL_MAC_OVERRIDE_SET(x) (((x) << PLL_CONTROL_MAC_OVERRIDE_LSB) & PLL_CONTROL_MAC_OVERRIDE_MASK)
-#define PLL_CONTROL_NOPWD_MSB 18
-#define PLL_CONTROL_NOPWD_LSB 18
-#define PLL_CONTROL_NOPWD_MASK 0x00040000
-#define PLL_CONTROL_NOPWD_GET(x) (((x) & PLL_CONTROL_NOPWD_MASK) >> PLL_CONTROL_NOPWD_LSB)
-#define PLL_CONTROL_NOPWD_SET(x) (((x) << PLL_CONTROL_NOPWD_LSB) & PLL_CONTROL_NOPWD_MASK)
-#define PLL_CONTROL_UPDATING_MSB 17
-#define PLL_CONTROL_UPDATING_LSB 17
-#define PLL_CONTROL_UPDATING_MASK 0x00020000
-#define PLL_CONTROL_UPDATING_GET(x) (((x) & PLL_CONTROL_UPDATING_MASK) >> PLL_CONTROL_UPDATING_LSB)
-#define PLL_CONTROL_UPDATING_SET(x) (((x) << PLL_CONTROL_UPDATING_LSB) & PLL_CONTROL_UPDATING_MASK)
-#define PLL_CONTROL_BYPASS_MSB 16
-#define PLL_CONTROL_BYPASS_LSB 16
-#define PLL_CONTROL_BYPASS_MASK 0x00010000
-#define PLL_CONTROL_BYPASS_GET(x) (((x) & PLL_CONTROL_BYPASS_MASK) >> PLL_CONTROL_BYPASS_LSB)
-#define PLL_CONTROL_BYPASS_SET(x) (((x) << PLL_CONTROL_BYPASS_LSB) & PLL_CONTROL_BYPASS_MASK)
-#define PLL_CONTROL_REFDIV_MSB 15
-#define PLL_CONTROL_REFDIV_LSB 12
-#define PLL_CONTROL_REFDIV_MASK 0x0000f000
-#define PLL_CONTROL_REFDIV_GET(x) (((x) & PLL_CONTROL_REFDIV_MASK) >> PLL_CONTROL_REFDIV_LSB)
-#define PLL_CONTROL_REFDIV_SET(x) (((x) << PLL_CONTROL_REFDIV_LSB) & PLL_CONTROL_REFDIV_MASK)
-#define PLL_CONTROL_DIV_MSB 9
-#define PLL_CONTROL_DIV_LSB 0
-#define PLL_CONTROL_DIV_MASK 0x000003ff
-#define PLL_CONTROL_DIV_GET(x) (((x) & PLL_CONTROL_DIV_MASK) >> PLL_CONTROL_DIV_LSB)
-#define PLL_CONTROL_DIV_SET(x) (((x) << PLL_CONTROL_DIV_LSB) & PLL_CONTROL_DIV_MASK)
-
-#define PLL_SETTLE_ADDRESS 0x00000018
-#define PLL_SETTLE_OFFSET 0x00000018
-#define PLL_SETTLE_TIME_MSB 11
-#define PLL_SETTLE_TIME_LSB 0
-#define PLL_SETTLE_TIME_MASK 0x00000fff
-#define PLL_SETTLE_TIME_GET(x) (((x) & PLL_SETTLE_TIME_MASK) >> PLL_SETTLE_TIME_LSB)
-#define PLL_SETTLE_TIME_SET(x) (((x) << PLL_SETTLE_TIME_LSB) & PLL_SETTLE_TIME_MASK)
-
-#define XTAL_SETTLE_ADDRESS 0x0000001c
-#define XTAL_SETTLE_OFFSET 0x0000001c
-#define XTAL_SETTLE_TIME_MSB 7
-#define XTAL_SETTLE_TIME_LSB 0
-#define XTAL_SETTLE_TIME_MASK 0x000000ff
-#define XTAL_SETTLE_TIME_GET(x) (((x) & XTAL_SETTLE_TIME_MASK) >> XTAL_SETTLE_TIME_LSB)
-#define XTAL_SETTLE_TIME_SET(x) (((x) << XTAL_SETTLE_TIME_LSB) & XTAL_SETTLE_TIME_MASK)
-
-#define CPU_CLOCK_ADDRESS 0x00000020
-#define CPU_CLOCK_OFFSET 0x00000020
-#define CPU_CLOCK_STANDARD_MSB 1
-#define CPU_CLOCK_STANDARD_LSB 0
-#define CPU_CLOCK_STANDARD_MASK 0x00000003
-#define CPU_CLOCK_STANDARD_GET(x) (((x) & CPU_CLOCK_STANDARD_MASK) >> CPU_CLOCK_STANDARD_LSB)
-#define CPU_CLOCK_STANDARD_SET(x) (((x) << CPU_CLOCK_STANDARD_LSB) & CPU_CLOCK_STANDARD_MASK)
-
-#define CLOCK_OUT_ADDRESS 0x00000024
-#define CLOCK_OUT_OFFSET 0x00000024
-#define CLOCK_OUT_SELECT_MSB 3
-#define CLOCK_OUT_SELECT_LSB 0
-#define CLOCK_OUT_SELECT_MASK 0x0000000f
-#define CLOCK_OUT_SELECT_GET(x) (((x) & CLOCK_OUT_SELECT_MASK) >> CLOCK_OUT_SELECT_LSB)
-#define CLOCK_OUT_SELECT_SET(x) (((x) << CLOCK_OUT_SELECT_LSB) & CLOCK_OUT_SELECT_MASK)
-
-#define CLOCK_CONTROL_ADDRESS 0x00000028
-#define CLOCK_CONTROL_OFFSET 0x00000028
-#define CLOCK_CONTROL_LF_CLK32_MSB 2
-#define CLOCK_CONTROL_LF_CLK32_LSB 2
-#define CLOCK_CONTROL_LF_CLK32_MASK 0x00000004
-#define CLOCK_CONTROL_LF_CLK32_GET(x) (((x) & CLOCK_CONTROL_LF_CLK32_MASK) >> CLOCK_CONTROL_LF_CLK32_LSB)
-#define CLOCK_CONTROL_LF_CLK32_SET(x) (((x) << CLOCK_CONTROL_LF_CLK32_LSB) & CLOCK_CONTROL_LF_CLK32_MASK)
-#define CLOCK_CONTROL_UART_CLK_MSB 1
-#define CLOCK_CONTROL_UART_CLK_LSB 1
-#define CLOCK_CONTROL_UART_CLK_MASK 0x00000002
-#define CLOCK_CONTROL_UART_CLK_GET(x) (((x) & CLOCK_CONTROL_UART_CLK_MASK) >> CLOCK_CONTROL_UART_CLK_LSB)
-#define CLOCK_CONTROL_UART_CLK_SET(x) (((x) << CLOCK_CONTROL_UART_CLK_LSB) & CLOCK_CONTROL_UART_CLK_MASK)
-#define CLOCK_CONTROL_SI0_CLK_MSB 0
-#define CLOCK_CONTROL_SI0_CLK_LSB 0
-#define CLOCK_CONTROL_SI0_CLK_MASK 0x00000001
-#define CLOCK_CONTROL_SI0_CLK_GET(x) (((x) & CLOCK_CONTROL_SI0_CLK_MASK) >> CLOCK_CONTROL_SI0_CLK_LSB)
-#define CLOCK_CONTROL_SI0_CLK_SET(x) (((x) << CLOCK_CONTROL_SI0_CLK_LSB) & CLOCK_CONTROL_SI0_CLK_MASK)
-
-#define BIAS_OVERRIDE_ADDRESS 0x0000002c
-#define BIAS_OVERRIDE_OFFSET 0x0000002c
-#define BIAS_OVERRIDE_ON_MSB 0
-#define BIAS_OVERRIDE_ON_LSB 0
-#define BIAS_OVERRIDE_ON_MASK 0x00000001
-#define BIAS_OVERRIDE_ON_GET(x) (((x) & BIAS_OVERRIDE_ON_MASK) >> BIAS_OVERRIDE_ON_LSB)
-#define BIAS_OVERRIDE_ON_SET(x) (((x) << BIAS_OVERRIDE_ON_LSB) & BIAS_OVERRIDE_ON_MASK)
-
-#define WDT_CONTROL_ADDRESS 0x00000030
-#define WDT_CONTROL_OFFSET 0x00000030
-#define WDT_CONTROL_ACTION_MSB 2
-#define WDT_CONTROL_ACTION_LSB 0
-#define WDT_CONTROL_ACTION_MASK 0x00000007
-#define WDT_CONTROL_ACTION_GET(x) (((x) & WDT_CONTROL_ACTION_MASK) >> WDT_CONTROL_ACTION_LSB)
-#define WDT_CONTROL_ACTION_SET(x) (((x) << WDT_CONTROL_ACTION_LSB) & WDT_CONTROL_ACTION_MASK)
-
-#define WDT_STATUS_ADDRESS 0x00000034
-#define WDT_STATUS_OFFSET 0x00000034
-#define WDT_STATUS_INTERRUPT_MSB 0
-#define WDT_STATUS_INTERRUPT_LSB 0
-#define WDT_STATUS_INTERRUPT_MASK 0x00000001
-#define WDT_STATUS_INTERRUPT_GET(x) (((x) & WDT_STATUS_INTERRUPT_MASK) >> WDT_STATUS_INTERRUPT_LSB)
-#define WDT_STATUS_INTERRUPT_SET(x) (((x) << WDT_STATUS_INTERRUPT_LSB) & WDT_STATUS_INTERRUPT_MASK)
-
-#define WDT_ADDRESS 0x00000038
-#define WDT_OFFSET 0x00000038
-#define WDT_TARGET_MSB 21
-#define WDT_TARGET_LSB 0
-#define WDT_TARGET_MASK 0x003fffff
-#define WDT_TARGET_GET(x) (((x) & WDT_TARGET_MASK) >> WDT_TARGET_LSB)
-#define WDT_TARGET_SET(x) (((x) << WDT_TARGET_LSB) & WDT_TARGET_MASK)
-
-#define WDT_COUNT_ADDRESS 0x0000003c
-#define WDT_COUNT_OFFSET 0x0000003c
-#define WDT_COUNT_VALUE_MSB 21
-#define WDT_COUNT_VALUE_LSB 0
-#define WDT_COUNT_VALUE_MASK 0x003fffff
-#define WDT_COUNT_VALUE_GET(x) (((x) & WDT_COUNT_VALUE_MASK) >> WDT_COUNT_VALUE_LSB)
-#define WDT_COUNT_VALUE_SET(x) (((x) << WDT_COUNT_VALUE_LSB) & WDT_COUNT_VALUE_MASK)
-
-#define WDT_RESET_ADDRESS 0x00000040
-#define WDT_RESET_OFFSET 0x00000040
-#define WDT_RESET_VALUE_MSB 0
-#define WDT_RESET_VALUE_LSB 0
-#define WDT_RESET_VALUE_MASK 0x00000001
-#define WDT_RESET_VALUE_GET(x) (((x) & WDT_RESET_VALUE_MASK) >> WDT_RESET_VALUE_LSB)
-#define WDT_RESET_VALUE_SET(x) (((x) << WDT_RESET_VALUE_LSB) & WDT_RESET_VALUE_MASK)
-
-#define INT_STATUS_ADDRESS 0x00000044
-#define INT_STATUS_OFFSET 0x00000044
-#define INT_STATUS_RTC_POWER_MSB 14
-#define INT_STATUS_RTC_POWER_LSB 14
-#define INT_STATUS_RTC_POWER_MASK 0x00004000
-#define INT_STATUS_RTC_POWER_GET(x) (((x) & INT_STATUS_RTC_POWER_MASK) >> INT_STATUS_RTC_POWER_LSB)
-#define INT_STATUS_RTC_POWER_SET(x) (((x) << INT_STATUS_RTC_POWER_LSB) & INT_STATUS_RTC_POWER_MASK)
-#define INT_STATUS_MAC_MSB 13
-#define INT_STATUS_MAC_LSB 13
-#define INT_STATUS_MAC_MASK 0x00002000
-#define INT_STATUS_MAC_GET(x) (((x) & INT_STATUS_MAC_MASK) >> INT_STATUS_MAC_LSB)
-#define INT_STATUS_MAC_SET(x) (((x) << INT_STATUS_MAC_LSB) & INT_STATUS_MAC_MASK)
-#define INT_STATUS_MAILBOX_MSB 12
-#define INT_STATUS_MAILBOX_LSB 12
-#define INT_STATUS_MAILBOX_MASK 0x00001000
-#define INT_STATUS_MAILBOX_GET(x) (((x) & INT_STATUS_MAILBOX_MASK) >> INT_STATUS_MAILBOX_LSB)
-#define INT_STATUS_MAILBOX_SET(x) (((x) << INT_STATUS_MAILBOX_LSB) & INT_STATUS_MAILBOX_MASK)
-#define INT_STATUS_RTC_ALARM_MSB 11
-#define INT_STATUS_RTC_ALARM_LSB 11
-#define INT_STATUS_RTC_ALARM_MASK 0x00000800
-#define INT_STATUS_RTC_ALARM_GET(x) (((x) & INT_STATUS_RTC_ALARM_MASK) >> INT_STATUS_RTC_ALARM_LSB)
-#define INT_STATUS_RTC_ALARM_SET(x) (((x) << INT_STATUS_RTC_ALARM_LSB) & INT_STATUS_RTC_ALARM_MASK)
-#define INT_STATUS_HF_TIMER_MSB 10
-#define INT_STATUS_HF_TIMER_LSB 10
-#define INT_STATUS_HF_TIMER_MASK 0x00000400
-#define INT_STATUS_HF_TIMER_GET(x) (((x) & INT_STATUS_HF_TIMER_MASK) >> INT_STATUS_HF_TIMER_LSB)
-#define INT_STATUS_HF_TIMER_SET(x) (((x) << INT_STATUS_HF_TIMER_LSB) & INT_STATUS_HF_TIMER_MASK)
-#define INT_STATUS_LF_TIMER3_MSB 9
-#define INT_STATUS_LF_TIMER3_LSB 9
-#define INT_STATUS_LF_TIMER3_MASK 0x00000200
-#define INT_STATUS_LF_TIMER3_GET(x) (((x) & INT_STATUS_LF_TIMER3_MASK) >> INT_STATUS_LF_TIMER3_LSB)
-#define INT_STATUS_LF_TIMER3_SET(x) (((x) << INT_STATUS_LF_TIMER3_LSB) & INT_STATUS_LF_TIMER3_MASK)
-#define INT_STATUS_LF_TIMER2_MSB 8
-#define INT_STATUS_LF_TIMER2_LSB 8
-#define INT_STATUS_LF_TIMER2_MASK 0x00000100
-#define INT_STATUS_LF_TIMER2_GET(x) (((x) & INT_STATUS_LF_TIMER2_MASK) >> INT_STATUS_LF_TIMER2_LSB)
-#define INT_STATUS_LF_TIMER2_SET(x) (((x) << INT_STATUS_LF_TIMER2_LSB) & INT_STATUS_LF_TIMER2_MASK)
-#define INT_STATUS_LF_TIMER1_MSB 7
-#define INT_STATUS_LF_TIMER1_LSB 7
-#define INT_STATUS_LF_TIMER1_MASK 0x00000080
-#define INT_STATUS_LF_TIMER1_GET(x) (((x) & INT_STATUS_LF_TIMER1_MASK) >> INT_STATUS_LF_TIMER1_LSB)
-#define INT_STATUS_LF_TIMER1_SET(x) (((x) << INT_STATUS_LF_TIMER1_LSB) & INT_STATUS_LF_TIMER1_MASK)
-#define INT_STATUS_LF_TIMER0_MSB 6
-#define INT_STATUS_LF_TIMER0_LSB 6
-#define INT_STATUS_LF_TIMER0_MASK 0x00000040
-#define INT_STATUS_LF_TIMER0_GET(x) (((x) & INT_STATUS_LF_TIMER0_MASK) >> INT_STATUS_LF_TIMER0_LSB)
-#define INT_STATUS_LF_TIMER0_SET(x) (((x) << INT_STATUS_LF_TIMER0_LSB) & INT_STATUS_LF_TIMER0_MASK)
-#define INT_STATUS_KEYPAD_MSB 5
-#define INT_STATUS_KEYPAD_LSB 5
-#define INT_STATUS_KEYPAD_MASK 0x00000020
-#define INT_STATUS_KEYPAD_GET(x) (((x) & INT_STATUS_KEYPAD_MASK) >> INT_STATUS_KEYPAD_LSB)
-#define INT_STATUS_KEYPAD_SET(x) (((x) << INT_STATUS_KEYPAD_LSB) & INT_STATUS_KEYPAD_MASK)
-#define INT_STATUS_SI_MSB 4
-#define INT_STATUS_SI_LSB 4
-#define INT_STATUS_SI_MASK 0x00000010
-#define INT_STATUS_SI_GET(x) (((x) & INT_STATUS_SI_MASK) >> INT_STATUS_SI_LSB)
-#define INT_STATUS_SI_SET(x) (((x) << INT_STATUS_SI_LSB) & INT_STATUS_SI_MASK)
-#define INT_STATUS_GPIO_MSB 3
-#define INT_STATUS_GPIO_LSB 3
-#define INT_STATUS_GPIO_MASK 0x00000008
-#define INT_STATUS_GPIO_GET(x) (((x) & INT_STATUS_GPIO_MASK) >> INT_STATUS_GPIO_LSB)
-#define INT_STATUS_GPIO_SET(x) (((x) << INT_STATUS_GPIO_LSB) & INT_STATUS_GPIO_MASK)
-#define INT_STATUS_UART_MSB 2
-#define INT_STATUS_UART_LSB 2
-#define INT_STATUS_UART_MASK 0x00000004
-#define INT_STATUS_UART_GET(x) (((x) & INT_STATUS_UART_MASK) >> INT_STATUS_UART_LSB)
-#define INT_STATUS_UART_SET(x) (((x) << INT_STATUS_UART_LSB) & INT_STATUS_UART_MASK)
-#define INT_STATUS_ERROR_MSB 1
-#define INT_STATUS_ERROR_LSB 1
-#define INT_STATUS_ERROR_MASK 0x00000002
-#define INT_STATUS_ERROR_GET(x) (((x) & INT_STATUS_ERROR_MASK) >> INT_STATUS_ERROR_LSB)
-#define INT_STATUS_ERROR_SET(x) (((x) << INT_STATUS_ERROR_LSB) & INT_STATUS_ERROR_MASK)
-#define INT_STATUS_WDT_INT_MSB 0
-#define INT_STATUS_WDT_INT_LSB 0
-#define INT_STATUS_WDT_INT_MASK 0x00000001
-#define INT_STATUS_WDT_INT_GET(x) (((x) & INT_STATUS_WDT_INT_MASK) >> INT_STATUS_WDT_INT_LSB)
-#define INT_STATUS_WDT_INT_SET(x) (((x) << INT_STATUS_WDT_INT_LSB) & INT_STATUS_WDT_INT_MASK)
-
-#define LF_TIMER0_ADDRESS 0x00000048
-#define LF_TIMER0_OFFSET 0x00000048
-#define LF_TIMER0_TARGET_MSB 31
-#define LF_TIMER0_TARGET_LSB 0
-#define LF_TIMER0_TARGET_MASK 0xffffffff
-#define LF_TIMER0_TARGET_GET(x) (((x) & LF_TIMER0_TARGET_MASK) >> LF_TIMER0_TARGET_LSB)
-#define LF_TIMER0_TARGET_SET(x) (((x) << LF_TIMER0_TARGET_LSB) & LF_TIMER0_TARGET_MASK)
-
-#define LF_TIMER_COUNT0_ADDRESS 0x0000004c
-#define LF_TIMER_COUNT0_OFFSET 0x0000004c
-#define LF_TIMER_COUNT0_VALUE_MSB 31
-#define LF_TIMER_COUNT0_VALUE_LSB 0
-#define LF_TIMER_COUNT0_VALUE_MASK 0xffffffff
-#define LF_TIMER_COUNT0_VALUE_GET(x) (((x) & LF_TIMER_COUNT0_VALUE_MASK) >> LF_TIMER_COUNT0_VALUE_LSB)
-#define LF_TIMER_COUNT0_VALUE_SET(x) (((x) << LF_TIMER_COUNT0_VALUE_LSB) & LF_TIMER_COUNT0_VALUE_MASK)
-
-#define LF_TIMER_CONTROL0_ADDRESS 0x00000050
-#define LF_TIMER_CONTROL0_OFFSET 0x00000050
-#define LF_TIMER_CONTROL0_ENABLE_MSB 2
-#define LF_TIMER_CONTROL0_ENABLE_LSB 2
-#define LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004
-#define LF_TIMER_CONTROL0_ENABLE_GET(x) (((x) & LF_TIMER_CONTROL0_ENABLE_MASK) >> LF_TIMER_CONTROL0_ENABLE_LSB)
-#define LF_TIMER_CONTROL0_ENABLE_SET(x) (((x) << LF_TIMER_CONTROL0_ENABLE_LSB) & LF_TIMER_CONTROL0_ENABLE_MASK)
-#define LF_TIMER_CONTROL0_AUTO_RESTART_MSB 1
-#define LF_TIMER_CONTROL0_AUTO_RESTART_LSB 1
-#define LF_TIMER_CONTROL0_AUTO_RESTART_MASK 0x00000002
-#define LF_TIMER_CONTROL0_AUTO_RESTART_GET(x) (((x) & LF_TIMER_CONTROL0_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL0_AUTO_RESTART_LSB)
-#define LF_TIMER_CONTROL0_AUTO_RESTART_SET(x) (((x) << LF_TIMER_CONTROL0_AUTO_RESTART_LSB) & LF_TIMER_CONTROL0_AUTO_RESTART_MASK)
-#define LF_TIMER_CONTROL0_RESET_MSB 0
-#define LF_TIMER_CONTROL0_RESET_LSB 0
-#define LF_TIMER_CONTROL0_RESET_MASK 0x00000001
-#define LF_TIMER_CONTROL0_RESET_GET(x) (((x) & LF_TIMER_CONTROL0_RESET_MASK) >> LF_TIMER_CONTROL0_RESET_LSB)
-#define LF_TIMER_CONTROL0_RESET_SET(x) (((x) << LF_TIMER_CONTROL0_RESET_LSB) & LF_TIMER_CONTROL0_RESET_MASK)
-
-#define LF_TIMER_STATUS0_ADDRESS 0x00000054
-#define LF_TIMER_STATUS0_OFFSET 0x00000054
-#define LF_TIMER_STATUS0_INTERRUPT_MSB 0
-#define LF_TIMER_STATUS0_INTERRUPT_LSB 0
-#define LF_TIMER_STATUS0_INTERRUPT_MASK 0x00000001
-#define LF_TIMER_STATUS0_INTERRUPT_GET(x) (((x) & LF_TIMER_STATUS0_INTERRUPT_MASK) >> LF_TIMER_STATUS0_INTERRUPT_LSB)
-#define LF_TIMER_STATUS0_INTERRUPT_SET(x) (((x) << LF_TIMER_STATUS0_INTERRUPT_LSB) & LF_TIMER_STATUS0_INTERRUPT_MASK)
-
-#define LF_TIMER1_ADDRESS 0x00000058
-#define LF_TIMER1_OFFSET 0x00000058
-#define LF_TIMER1_TARGET_MSB 31
-#define LF_TIMER1_TARGET_LSB 0
-#define LF_TIMER1_TARGET_MASK 0xffffffff
-#define LF_TIMER1_TARGET_GET(x) (((x) & LF_TIMER1_TARGET_MASK) >> LF_TIMER1_TARGET_LSB)
-#define LF_TIMER1_TARGET_SET(x) (((x) << LF_TIMER1_TARGET_LSB) & LF_TIMER1_TARGET_MASK)
-
-#define LF_TIMER_COUNT1_ADDRESS 0x0000005c
-#define LF_TIMER_COUNT1_OFFSET 0x0000005c
-#define LF_TIMER_COUNT1_VALUE_MSB 31
-#define LF_TIMER_COUNT1_VALUE_LSB 0
-#define LF_TIMER_COUNT1_VALUE_MASK 0xffffffff
-#define LF_TIMER_COUNT1_VALUE_GET(x) (((x) & LF_TIMER_COUNT1_VALUE_MASK) >> LF_TIMER_COUNT1_VALUE_LSB)
-#define LF_TIMER_COUNT1_VALUE_SET(x) (((x) << LF_TIMER_COUNT1_VALUE_LSB) & LF_TIMER_COUNT1_VALUE_MASK)
-
-#define LF_TIMER_CONTROL1_ADDRESS 0x00000060
-#define LF_TIMER_CONTROL1_OFFSET 0x00000060
-#define LF_TIMER_CONTROL1_ENABLE_MSB 2
-#define LF_TIMER_CONTROL1_ENABLE_LSB 2
-#define LF_TIMER_CONTROL1_ENABLE_MASK 0x00000004
-#define LF_TIMER_CONTROL1_ENABLE_GET(x) (((x) & LF_TIMER_CONTROL1_ENABLE_MASK) >> LF_TIMER_CONTROL1_ENABLE_LSB)
-#define LF_TIMER_CONTROL1_ENABLE_SET(x) (((x) << LF_TIMER_CONTROL1_ENABLE_LSB) & LF_TIMER_CONTROL1_ENABLE_MASK)
-#define LF_TIMER_CONTROL1_AUTO_RESTART_MSB 1
-#define LF_TIMER_CONTROL1_AUTO_RESTART_LSB 1
-#define LF_TIMER_CONTROL1_AUTO_RESTART_MASK 0x00000002
-#define LF_TIMER_CONTROL1_AUTO_RESTART_GET(x) (((x) & LF_TIMER_CONTROL1_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL1_AUTO_RESTART_LSB)
-#define LF_TIMER_CONTROL1_AUTO_RESTART_SET(x) (((x) << LF_TIMER_CONTROL1_AUTO_RESTART_LSB) & LF_TIMER_CONTROL1_AUTO_RESTART_MASK)
-#define LF_TIMER_CONTROL1_RESET_MSB 0
-#define LF_TIMER_CONTROL1_RESET_LSB 0
-#define LF_TIMER_CONTROL1_RESET_MASK 0x00000001
-#define LF_TIMER_CONTROL1_RESET_GET(x) (((x) & LF_TIMER_CONTROL1_RESET_MASK) >> LF_TIMER_CONTROL1_RESET_LSB)
-#define LF_TIMER_CONTROL1_RESET_SET(x) (((x) << LF_TIMER_CONTROL1_RESET_LSB) & LF_TIMER_CONTROL1_RESET_MASK)
-
-#define LF_TIMER_STATUS1_ADDRESS 0x00000064
-#define LF_TIMER_STATUS1_OFFSET 0x00000064
-#define LF_TIMER_STATUS1_INTERRUPT_MSB 0
-#define LF_TIMER_STATUS1_INTERRUPT_LSB 0
-#define LF_TIMER_STATUS1_INTERRUPT_MASK 0x00000001
-#define LF_TIMER_STATUS1_INTERRUPT_GET(x) (((x) & LF_TIMER_STATUS1_INTERRUPT_MASK) >> LF_TIMER_STATUS1_INTERRUPT_LSB)
-#define LF_TIMER_STATUS1_INTERRUPT_SET(x) (((x) << LF_TIMER_STATUS1_INTERRUPT_LSB) & LF_TIMER_STATUS1_INTERRUPT_MASK)
-
-#define LF_TIMER2_ADDRESS 0x00000068
-#define LF_TIMER2_OFFSET 0x00000068
-#define LF_TIMER2_TARGET_MSB 31
-#define LF_TIMER2_TARGET_LSB 0
-#define LF_TIMER2_TARGET_MASK 0xffffffff
-#define LF_TIMER2_TARGET_GET(x) (((x) & LF_TIMER2_TARGET_MASK) >> LF_TIMER2_TARGET_LSB)
-#define LF_TIMER2_TARGET_SET(x) (((x) << LF_TIMER2_TARGET_LSB) & LF_TIMER2_TARGET_MASK)
-
-#define LF_TIMER_COUNT2_ADDRESS 0x0000006c
-#define LF_TIMER_COUNT2_OFFSET 0x0000006c
-#define LF_TIMER_COUNT2_VALUE_MSB 31
-#define LF_TIMER_COUNT2_VALUE_LSB 0
-#define LF_TIMER_COUNT2_VALUE_MASK 0xffffffff
-#define LF_TIMER_COUNT2_VALUE_GET(x) (((x) & LF_TIMER_COUNT2_VALUE_MASK) >> LF_TIMER_COUNT2_VALUE_LSB)
-#define LF_TIMER_COUNT2_VALUE_SET(x) (((x) << LF_TIMER_COUNT2_VALUE_LSB) & LF_TIMER_COUNT2_VALUE_MASK)
-
-#define LF_TIMER_CONTROL2_ADDRESS 0x00000070
-#define LF_TIMER_CONTROL2_OFFSET 0x00000070
-#define LF_TIMER_CONTROL2_ENABLE_MSB 2
-#define LF_TIMER_CONTROL2_ENABLE_LSB 2
-#define LF_TIMER_CONTROL2_ENABLE_MASK 0x00000004
-#define LF_TIMER_CONTROL2_ENABLE_GET(x) (((x) & LF_TIMER_CONTROL2_ENABLE_MASK) >> LF_TIMER_CONTROL2_ENABLE_LSB)
-#define LF_TIMER_CONTROL2_ENABLE_SET(x) (((x) << LF_TIMER_CONTROL2_ENABLE_LSB) & LF_TIMER_CONTROL2_ENABLE_MASK)
-#define LF_TIMER_CONTROL2_AUTO_RESTART_MSB 1
-#define LF_TIMER_CONTROL2_AUTO_RESTART_LSB 1
-#define LF_TIMER_CONTROL2_AUTO_RESTART_MASK 0x00000002
-#define LF_TIMER_CONTROL2_AUTO_RESTART_GET(x) (((x) & LF_TIMER_CONTROL2_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL2_AUTO_RESTART_LSB)
-#define LF_TIMER_CONTROL2_AUTO_RESTART_SET(x) (((x) << LF_TIMER_CONTROL2_AUTO_RESTART_LSB) & LF_TIMER_CONTROL2_AUTO_RESTART_MASK)
-#define LF_TIMER_CONTROL2_RESET_MSB 0
-#define LF_TIMER_CONTROL2_RESET_LSB 0
-#define LF_TIMER_CONTROL2_RESET_MASK 0x00000001
-#define LF_TIMER_CONTROL2_RESET_GET(x) (((x) & LF_TIMER_CONTROL2_RESET_MASK) >> LF_TIMER_CONTROL2_RESET_LSB)
-#define LF_TIMER_CONTROL2_RESET_SET(x) (((x) << LF_TIMER_CONTROL2_RESET_LSB) & LF_TIMER_CONTROL2_RESET_MASK)
-
-#define LF_TIMER_STATUS2_ADDRESS 0x00000074
-#define LF_TIMER_STATUS2_OFFSET 0x00000074
-#define LF_TIMER_STATUS2_INTERRUPT_MSB 0
-#define LF_TIMER_STATUS2_INTERRUPT_LSB 0
-#define LF_TIMER_STATUS2_INTERRUPT_MASK 0x00000001
-#define LF_TIMER_STATUS2_INTERRUPT_GET(x) (((x) & LF_TIMER_STATUS2_INTERRUPT_MASK) >> LF_TIMER_STATUS2_INTERRUPT_LSB)
-#define LF_TIMER_STATUS2_INTERRUPT_SET(x) (((x) << LF_TIMER_STATUS2_INTERRUPT_LSB) & LF_TIMER_STATUS2_INTERRUPT_MASK)
-
-#define LF_TIMER3_ADDRESS 0x00000078
-#define LF_TIMER3_OFFSET 0x00000078
-#define LF_TIMER3_TARGET_MSB 31
-#define LF_TIMER3_TARGET_LSB 0
-#define LF_TIMER3_TARGET_MASK 0xffffffff
-#define LF_TIMER3_TARGET_GET(x) (((x) & LF_TIMER3_TARGET_MASK) >> LF_TIMER3_TARGET_LSB)
-#define LF_TIMER3_TARGET_SET(x) (((x) << LF_TIMER3_TARGET_LSB) & LF_TIMER3_TARGET_MASK)
-
-#define LF_TIMER_COUNT3_ADDRESS 0x0000007c
-#define LF_TIMER_COUNT3_OFFSET 0x0000007c
-#define LF_TIMER_COUNT3_VALUE_MSB 31
-#define LF_TIMER_COUNT3_VALUE_LSB 0
-#define LF_TIMER_COUNT3_VALUE_MASK 0xffffffff
-#define LF_TIMER_COUNT3_VALUE_GET(x) (((x) & LF_TIMER_COUNT3_VALUE_MASK) >> LF_TIMER_COUNT3_VALUE_LSB)
-#define LF_TIMER_COUNT3_VALUE_SET(x) (((x) << LF_TIMER_COUNT3_VALUE_LSB) & LF_TIMER_COUNT3_VALUE_MASK)
-
-#define LF_TIMER_CONTROL3_ADDRESS 0x00000080
-#define LF_TIMER_CONTROL3_OFFSET 0x00000080
-#define LF_TIMER_CONTROL3_ENABLE_MSB 2
-#define LF_TIMER_CONTROL3_ENABLE_LSB 2
-#define LF_TIMER_CONTROL3_ENABLE_MASK 0x00000004
-#define LF_TIMER_CONTROL3_ENABLE_GET(x) (((x) & LF_TIMER_CONTROL3_ENABLE_MASK) >> LF_TIMER_CONTROL3_ENABLE_LSB)
-#define LF_TIMER_CONTROL3_ENABLE_SET(x) (((x) << LF_TIMER_CONTROL3_ENABLE_LSB) & LF_TIMER_CONTROL3_ENABLE_MASK)
-#define LF_TIMER_CONTROL3_AUTO_RESTART_MSB 1
-#define LF_TIMER_CONTROL3_AUTO_RESTART_LSB 1
-#define LF_TIMER_CONTROL3_AUTO_RESTART_MASK 0x00000002
-#define LF_TIMER_CONTROL3_AUTO_RESTART_GET(x) (((x) & LF_TIMER_CONTROL3_AUTO_RESTART_MASK) >> LF_TIMER_CONTROL3_AUTO_RESTART_LSB)
-#define LF_TIMER_CONTROL3_AUTO_RESTART_SET(x) (((x) << LF_TIMER_CONTROL3_AUTO_RESTART_LSB) & LF_TIMER_CONTROL3_AUTO_RESTART_MASK)
-#define LF_TIMER_CONTROL3_RESET_MSB 0
-#define LF_TIMER_CONTROL3_RESET_LSB 0
-#define LF_TIMER_CONTROL3_RESET_MASK 0x00000001
-#define LF_TIMER_CONTROL3_RESET_GET(x) (((x) & LF_TIMER_CONTROL3_RESET_MASK) >> LF_TIMER_CONTROL3_RESET_LSB)
-#define LF_TIMER_CONTROL3_RESET_SET(x) (((x) << LF_TIMER_CONTROL3_RESET_LSB) & LF_TIMER_CONTROL3_RESET_MASK)
-
-#define LF_TIMER_STATUS3_ADDRESS 0x00000084
-#define LF_TIMER_STATUS3_OFFSET 0x00000084
-#define LF_TIMER_STATUS3_INTERRUPT_MSB 0
-#define LF_TIMER_STATUS3_INTERRUPT_LSB 0
-#define LF_TIMER_STATUS3_INTERRUPT_MASK 0x00000001
-#define LF_TIMER_STATUS3_INTERRUPT_GET(x) (((x) & LF_TIMER_STATUS3_INTERRUPT_MASK) >> LF_TIMER_STATUS3_INTERRUPT_LSB)
-#define LF_TIMER_STATUS3_INTERRUPT_SET(x) (((x) << LF_TIMER_STATUS3_INTERRUPT_LSB) & LF_TIMER_STATUS3_INTERRUPT_MASK)
-
-#define HF_TIMER_ADDRESS 0x00000088
-#define HF_TIMER_OFFSET 0x00000088
-#define HF_TIMER_TARGET_MSB 31
-#define HF_TIMER_TARGET_LSB 12
-#define HF_TIMER_TARGET_MASK 0xfffff000
-#define HF_TIMER_TARGET_GET(x) (((x) & HF_TIMER_TARGET_MASK) >> HF_TIMER_TARGET_LSB)
-#define HF_TIMER_TARGET_SET(x) (((x) << HF_TIMER_TARGET_LSB) & HF_TIMER_TARGET_MASK)
-
-#define HF_TIMER_COUNT_ADDRESS 0x0000008c
-#define HF_TIMER_COUNT_OFFSET 0x0000008c
-#define HF_TIMER_COUNT_VALUE_MSB 31
-#define HF_TIMER_COUNT_VALUE_LSB 12
-#define HF_TIMER_COUNT_VALUE_MASK 0xfffff000
-#define HF_TIMER_COUNT_VALUE_GET(x) (((x) & HF_TIMER_COUNT_VALUE_MASK) >> HF_TIMER_COUNT_VALUE_LSB)
-#define HF_TIMER_COUNT_VALUE_SET(x) (((x) << HF_TIMER_COUNT_VALUE_LSB) & HF_TIMER_COUNT_VALUE_MASK)
-
-#define HF_LF_COUNT_ADDRESS 0x00000090
-#define HF_LF_COUNT_OFFSET 0x00000090
-#define HF_LF_COUNT_VALUE_MSB 31
-#define HF_LF_COUNT_VALUE_LSB 0
-#define HF_LF_COUNT_VALUE_MASK 0xffffffff
-#define HF_LF_COUNT_VALUE_GET(x) (((x) & HF_LF_COUNT_VALUE_MASK) >> HF_LF_COUNT_VALUE_LSB)
-#define HF_LF_COUNT_VALUE_SET(x) (((x) << HF_LF_COUNT_VALUE_LSB) & HF_LF_COUNT_VALUE_MASK)
-
-#define HF_TIMER_CONTROL_ADDRESS 0x00000094
-#define HF_TIMER_CONTROL_OFFSET 0x00000094
-#define HF_TIMER_CONTROL_ENABLE_MSB 3
-#define HF_TIMER_CONTROL_ENABLE_LSB 3
-#define HF_TIMER_CONTROL_ENABLE_MASK 0x00000008
-#define HF_TIMER_CONTROL_ENABLE_GET(x) (((x) & HF_TIMER_CONTROL_ENABLE_MASK) >> HF_TIMER_CONTROL_ENABLE_LSB)
-#define HF_TIMER_CONTROL_ENABLE_SET(x) (((x) << HF_TIMER_CONTROL_ENABLE_LSB) & HF_TIMER_CONTROL_ENABLE_MASK)
-#define HF_TIMER_CONTROL_ON_MSB 2
-#define HF_TIMER_CONTROL_ON_LSB 2
-#define HF_TIMER_CONTROL_ON_MASK 0x00000004
-#define HF_TIMER_CONTROL_ON_GET(x) (((x) & HF_TIMER_CONTROL_ON_MASK) >> HF_TIMER_CONTROL_ON_LSB)
-#define HF_TIMER_CONTROL_ON_SET(x) (((x) << HF_TIMER_CONTROL_ON_LSB) & HF_TIMER_CONTROL_ON_MASK)
-#define HF_TIMER_CONTROL_AUTO_RESTART_MSB 1
-#define HF_TIMER_CONTROL_AUTO_RESTART_LSB 1
-#define HF_TIMER_CONTROL_AUTO_RESTART_MASK 0x00000002
-#define HF_TIMER_CONTROL_AUTO_RESTART_GET(x) (((x) & HF_TIMER_CONTROL_AUTO_RESTART_MASK) >> HF_TIMER_CONTROL_AUTO_RESTART_LSB)
-#define HF_TIMER_CONTROL_AUTO_RESTART_SET(x) (((x) << HF_TIMER_CONTROL_AUTO_RESTART_LSB) & HF_TIMER_CONTROL_AUTO_RESTART_MASK)
-#define HF_TIMER_CONTROL_RESET_MSB 0
-#define HF_TIMER_CONTROL_RESET_LSB 0
-#define HF_TIMER_CONTROL_RESET_MASK 0x00000001
-#define HF_TIMER_CONTROL_RESET_GET(x) (((x) & HF_TIMER_CONTROL_RESET_MASK) >> HF_TIMER_CONTROL_RESET_LSB)
-#define HF_TIMER_CONTROL_RESET_SET(x) (((x) << HF_TIMER_CONTROL_RESET_LSB) & HF_TIMER_CONTROL_RESET_MASK)
-
-#define HF_TIMER_STATUS_ADDRESS 0x00000098
-#define HF_TIMER_STATUS_OFFSET 0x00000098
-#define HF_TIMER_STATUS_INTERRUPT_MSB 0
-#define HF_TIMER_STATUS_INTERRUPT_LSB 0
-#define HF_TIMER_STATUS_INTERRUPT_MASK 0x00000001
-#define HF_TIMER_STATUS_INTERRUPT_GET(x) (((x) & HF_TIMER_STATUS_INTERRUPT_MASK) >> HF_TIMER_STATUS_INTERRUPT_LSB)
-#define HF_TIMER_STATUS_INTERRUPT_SET(x) (((x) << HF_TIMER_STATUS_INTERRUPT_LSB) & HF_TIMER_STATUS_INTERRUPT_MASK)
-
-#define RTC_CONTROL_ADDRESS 0x0000009c
-#define RTC_CONTROL_OFFSET 0x0000009c
-#define RTC_CONTROL_ENABLE_MSB 2
-#define RTC_CONTROL_ENABLE_LSB 2
-#define RTC_CONTROL_ENABLE_MASK 0x00000004
-#define RTC_CONTROL_ENABLE_GET(x) (((x) & RTC_CONTROL_ENABLE_MASK) >> RTC_CONTROL_ENABLE_LSB)
-#define RTC_CONTROL_ENABLE_SET(x) (((x) << RTC_CONTROL_ENABLE_LSB) & RTC_CONTROL_ENABLE_MASK)
-#define RTC_CONTROL_LOAD_RTC_MSB 1
-#define RTC_CONTROL_LOAD_RTC_LSB 1
-#define RTC_CONTROL_LOAD_RTC_MASK 0x00000002
-#define RTC_CONTROL_LOAD_RTC_GET(x) (((x) & RTC_CONTROL_LOAD_RTC_MASK) >> RTC_CONTROL_LOAD_RTC_LSB)
-#define RTC_CONTROL_LOAD_RTC_SET(x) (((x) << RTC_CONTROL_LOAD_RTC_LSB) & RTC_CONTROL_LOAD_RTC_MASK)
-#define RTC_CONTROL_LOAD_ALARM_MSB 0
-#define RTC_CONTROL_LOAD_ALARM_LSB 0
-#define RTC_CONTROL_LOAD_ALARM_MASK 0x00000001
-#define RTC_CONTROL_LOAD_ALARM_GET(x) (((x) & RTC_CONTROL_LOAD_ALARM_MASK) >> RTC_CONTROL_LOAD_ALARM_LSB)
-#define RTC_CONTROL_LOAD_ALARM_SET(x) (((x) << RTC_CONTROL_LOAD_ALARM_LSB) & RTC_CONTROL_LOAD_ALARM_MASK)
-
-#define RTC_TIME_ADDRESS 0x000000a0
-#define RTC_TIME_OFFSET 0x000000a0
-#define RTC_TIME_WEEK_DAY_MSB 26
-#define RTC_TIME_WEEK_DAY_LSB 24
-#define RTC_TIME_WEEK_DAY_MASK 0x07000000
-#define RTC_TIME_WEEK_DAY_GET(x) (((x) & RTC_TIME_WEEK_DAY_MASK) >> RTC_TIME_WEEK_DAY_LSB)
-#define RTC_TIME_WEEK_DAY_SET(x) (((x) << RTC_TIME_WEEK_DAY_LSB) & RTC_TIME_WEEK_DAY_MASK)
-#define RTC_TIME_HOUR_MSB 21
-#define RTC_TIME_HOUR_LSB 16
-#define RTC_TIME_HOUR_MASK 0x003f0000
-#define RTC_TIME_HOUR_GET(x) (((x) & RTC_TIME_HOUR_MASK) >> RTC_TIME_HOUR_LSB)
-#define RTC_TIME_HOUR_SET(x) (((x) << RTC_TIME_HOUR_LSB) & RTC_TIME_HOUR_MASK)
-#define RTC_TIME_MINUTE_MSB 14
-#define RTC_TIME_MINUTE_LSB 8
-#define RTC_TIME_MINUTE_MASK 0x00007f00
-#define RTC_TIME_MINUTE_GET(x) (((x) & RTC_TIME_MINUTE_MASK) >> RTC_TIME_MINUTE_LSB)
-#define RTC_TIME_MINUTE_SET(x) (((x) << RTC_TIME_MINUTE_LSB) & RTC_TIME_MINUTE_MASK)
-#define RTC_TIME_SECOND_MSB 6
-#define RTC_TIME_SECOND_LSB 0
-#define RTC_TIME_SECOND_MASK 0x0000007f
-#define RTC_TIME_SECOND_GET(x) (((x) & RTC_TIME_SECOND_MASK) >> RTC_TIME_SECOND_LSB)
-#define RTC_TIME_SECOND_SET(x) (((x) << RTC_TIME_SECOND_LSB) & RTC_TIME_SECOND_MASK)
-
-#define RTC_DATE_ADDRESS 0x000000a4
-#define RTC_DATE_OFFSET 0x000000a4
-#define RTC_DATE_YEAR_MSB 23
-#define RTC_DATE_YEAR_LSB 16
-#define RTC_DATE_YEAR_MASK 0x00ff0000
-#define RTC_DATE_YEAR_GET(x) (((x) & RTC_DATE_YEAR_MASK) >> RTC_DATE_YEAR_LSB)
-#define RTC_DATE_YEAR_SET(x) (((x) << RTC_DATE_YEAR_LSB) & RTC_DATE_YEAR_MASK)
-#define RTC_DATE_MONTH_MSB 12
-#define RTC_DATE_MONTH_LSB 8
-#define RTC_DATE_MONTH_MASK 0x00001f00
-#define RTC_DATE_MONTH_GET(x) (((x) & RTC_DATE_MONTH_MASK) >> RTC_DATE_MONTH_LSB)
-#define RTC_DATE_MONTH_SET(x) (((x) << RTC_DATE_MONTH_LSB) & RTC_DATE_MONTH_MASK)
-#define RTC_DATE_MONTH_DAY_MSB 5
-#define RTC_DATE_MONTH_DAY_LSB 0
-#define RTC_DATE_MONTH_DAY_MASK 0x0000003f
-#define RTC_DATE_MONTH_DAY_GET(x) (((x) & RTC_DATE_MONTH_DAY_MASK) >> RTC_DATE_MONTH_DAY_LSB)
-#define RTC_DATE_MONTH_DAY_SET(x) (((x) << RTC_DATE_MONTH_DAY_LSB) & RTC_DATE_MONTH_DAY_MASK)
-
-#define RTC_SET_TIME_ADDRESS 0x000000a8
-#define RTC_SET_TIME_OFFSET 0x000000a8
-#define RTC_SET_TIME_WEEK_DAY_MSB 26
-#define RTC_SET_TIME_WEEK_DAY_LSB 24
-#define RTC_SET_TIME_WEEK_DAY_MASK 0x07000000
-#define RTC_SET_TIME_WEEK_DAY_GET(x) (((x) & RTC_SET_TIME_WEEK_DAY_MASK) >> RTC_SET_TIME_WEEK_DAY_LSB)
-#define RTC_SET_TIME_WEEK_DAY_SET(x) (((x) << RTC_SET_TIME_WEEK_DAY_LSB) & RTC_SET_TIME_WEEK_DAY_MASK)
-#define RTC_SET_TIME_HOUR_MSB 21
-#define RTC_SET_TIME_HOUR_LSB 16
-#define RTC_SET_TIME_HOUR_MASK 0x003f0000
-#define RTC_SET_TIME_HOUR_GET(x) (((x) & RTC_SET_TIME_HOUR_MASK) >> RTC_SET_TIME_HOUR_LSB)
-#define RTC_SET_TIME_HOUR_SET(x) (((x) << RTC_SET_TIME_HOUR_LSB) & RTC_SET_TIME_HOUR_MASK)
-#define RTC_SET_TIME_MINUTE_MSB 14
-#define RTC_SET_TIME_MINUTE_LSB 8
-#define RTC_SET_TIME_MINUTE_MASK 0x00007f00
-#define RTC_SET_TIME_MINUTE_GET(x) (((x) & RTC_SET_TIME_MINUTE_MASK) >> RTC_SET_TIME_MINUTE_LSB)
-#define RTC_SET_TIME_MINUTE_SET(x) (((x) << RTC_SET_TIME_MINUTE_LSB) & RTC_SET_TIME_MINUTE_MASK)
-#define RTC_SET_TIME_SECOND_MSB 6
-#define RTC_SET_TIME_SECOND_LSB 0
-#define RTC_SET_TIME_SECOND_MASK 0x0000007f
-#define RTC_SET_TIME_SECOND_GET(x) (((x) & RTC_SET_TIME_SECOND_MASK) >> RTC_SET_TIME_SECOND_LSB)
-#define RTC_SET_TIME_SECOND_SET(x) (((x) << RTC_SET_TIME_SECOND_LSB) & RTC_SET_TIME_SECOND_MASK)
-
-#define RTC_SET_DATE_ADDRESS 0x000000ac
-#define RTC_SET_DATE_OFFSET 0x000000ac
-#define RTC_SET_DATE_YEAR_MSB 23
-#define RTC_SET_DATE_YEAR_LSB 16
-#define RTC_SET_DATE_YEAR_MASK 0x00ff0000
-#define RTC_SET_DATE_YEAR_GET(x) (((x) & RTC_SET_DATE_YEAR_MASK) >> RTC_SET_DATE_YEAR_LSB)
-#define RTC_SET_DATE_YEAR_SET(x) (((x) << RTC_SET_DATE_YEAR_LSB) & RTC_SET_DATE_YEAR_MASK)
-#define RTC_SET_DATE_MONTH_MSB 12
-#define RTC_SET_DATE_MONTH_LSB 8
-#define RTC_SET_DATE_MONTH_MASK 0x00001f00
-#define RTC_SET_DATE_MONTH_GET(x) (((x) & RTC_SET_DATE_MONTH_MASK) >> RTC_SET_DATE_MONTH_LSB)
-#define RTC_SET_DATE_MONTH_SET(x) (((x) << RTC_SET_DATE_MONTH_LSB) & RTC_SET_DATE_MONTH_MASK)
-#define RTC_SET_DATE_MONTH_DAY_MSB 5
-#define RTC_SET_DATE_MONTH_DAY_LSB 0
-#define RTC_SET_DATE_MONTH_DAY_MASK 0x0000003f
-#define RTC_SET_DATE_MONTH_DAY_GET(x) (((x) & RTC_SET_DATE_MONTH_DAY_MASK) >> RTC_SET_DATE_MONTH_DAY_LSB)
-#define RTC_SET_DATE_MONTH_DAY_SET(x) (((x) << RTC_SET_DATE_MONTH_DAY_LSB) & RTC_SET_DATE_MONTH_DAY_MASK)
-
-#define RTC_SET_ALARM_ADDRESS 0x000000b0
-#define RTC_SET_ALARM_OFFSET 0x000000b0
-#define RTC_SET_ALARM_HOUR_MSB 21
-#define RTC_SET_ALARM_HOUR_LSB 16
-#define RTC_SET_ALARM_HOUR_MASK 0x003f0000
-#define RTC_SET_ALARM_HOUR_GET(x) (((x) & RTC_SET_ALARM_HOUR_MASK) >> RTC_SET_ALARM_HOUR_LSB)
-#define RTC_SET_ALARM_HOUR_SET(x) (((x) << RTC_SET_ALARM_HOUR_LSB) & RTC_SET_ALARM_HOUR_MASK)
-#define RTC_SET_ALARM_MINUTE_MSB 14
-#define RTC_SET_ALARM_MINUTE_LSB 8
-#define RTC_SET_ALARM_MINUTE_MASK 0x00007f00
-#define RTC_SET_ALARM_MINUTE_GET(x) (((x) & RTC_SET_ALARM_MINUTE_MASK) >> RTC_SET_ALARM_MINUTE_LSB)
-#define RTC_SET_ALARM_MINUTE_SET(x) (((x) << RTC_SET_ALARM_MINUTE_LSB) & RTC_SET_ALARM_MINUTE_MASK)
-#define RTC_SET_ALARM_SECOND_MSB 6
-#define RTC_SET_ALARM_SECOND_LSB 0
-#define RTC_SET_ALARM_SECOND_MASK 0x0000007f
-#define RTC_SET_ALARM_SECOND_GET(x) (((x) & RTC_SET_ALARM_SECOND_MASK) >> RTC_SET_ALARM_SECOND_LSB)
-#define RTC_SET_ALARM_SECOND_SET(x) (((x) << RTC_SET_ALARM_SECOND_LSB) & RTC_SET_ALARM_SECOND_MASK)
-
-#define RTC_CONFIG_ADDRESS 0x000000b4
-#define RTC_CONFIG_OFFSET 0x000000b4
-#define RTC_CONFIG_BCD_MSB 2
-#define RTC_CONFIG_BCD_LSB 2
-#define RTC_CONFIG_BCD_MASK 0x00000004
-#define RTC_CONFIG_BCD_GET(x) (((x) & RTC_CONFIG_BCD_MASK) >> RTC_CONFIG_BCD_LSB)
-#define RTC_CONFIG_BCD_SET(x) (((x) << RTC_CONFIG_BCD_LSB) & RTC_CONFIG_BCD_MASK)
-#define RTC_CONFIG_TWELVE_HOUR_MSB 1
-#define RTC_CONFIG_TWELVE_HOUR_LSB 1
-#define RTC_CONFIG_TWELVE_HOUR_MASK 0x00000002
-#define RTC_CONFIG_TWELVE_HOUR_GET(x) (((x) & RTC_CONFIG_TWELVE_HOUR_MASK) >> RTC_CONFIG_TWELVE_HOUR_LSB)
-#define RTC_CONFIG_TWELVE_HOUR_SET(x) (((x) << RTC_CONFIG_TWELVE_HOUR_LSB) & RTC_CONFIG_TWELVE_HOUR_MASK)
-#define RTC_CONFIG_DSE_MSB 0
-#define RTC_CONFIG_DSE_LSB 0
-#define RTC_CONFIG_DSE_MASK 0x00000001
-#define RTC_CONFIG_DSE_GET(x) (((x) & RTC_CONFIG_DSE_MASK) >> RTC_CONFIG_DSE_LSB)
-#define RTC_CONFIG_DSE_SET(x) (((x) << RTC_CONFIG_DSE_LSB) & RTC_CONFIG_DSE_MASK)
-
-#define RTC_ALARM_STATUS_ADDRESS 0x000000b8
-#define RTC_ALARM_STATUS_OFFSET 0x000000b8
-#define RTC_ALARM_STATUS_ENABLE_MSB 1
-#define RTC_ALARM_STATUS_ENABLE_LSB 1
-#define RTC_ALARM_STATUS_ENABLE_MASK 0x00000002
-#define RTC_ALARM_STATUS_ENABLE_GET(x) (((x) & RTC_ALARM_STATUS_ENABLE_MASK) >> RTC_ALARM_STATUS_ENABLE_LSB)
-#define RTC_ALARM_STATUS_ENABLE_SET(x) (((x) << RTC_ALARM_STATUS_ENABLE_LSB) & RTC_ALARM_STATUS_ENABLE_MASK)
-#define RTC_ALARM_STATUS_INTERRUPT_MSB 0
-#define RTC_ALARM_STATUS_INTERRUPT_LSB 0
-#define RTC_ALARM_STATUS_INTERRUPT_MASK 0x00000001
-#define RTC_ALARM_STATUS_INTERRUPT_GET(x) (((x) & RTC_ALARM_STATUS_INTERRUPT_MASK) >> RTC_ALARM_STATUS_INTERRUPT_LSB)
-#define RTC_ALARM_STATUS_INTERRUPT_SET(x) (((x) << RTC_ALARM_STATUS_INTERRUPT_LSB) & RTC_ALARM_STATUS_INTERRUPT_MASK)
-
-#define UART_WAKEUP_ADDRESS 0x000000bc
-#define UART_WAKEUP_OFFSET 0x000000bc
-#define UART_WAKEUP_ENABLE_MSB 0
-#define UART_WAKEUP_ENABLE_LSB 0
-#define UART_WAKEUP_ENABLE_MASK 0x00000001
-#define UART_WAKEUP_ENABLE_GET(x) (((x) & UART_WAKEUP_ENABLE_MASK) >> UART_WAKEUP_ENABLE_LSB)
-#define UART_WAKEUP_ENABLE_SET(x) (((x) << UART_WAKEUP_ENABLE_LSB) & UART_WAKEUP_ENABLE_MASK)
-
-#define RESET_CAUSE_ADDRESS 0x000000c0
-#define RESET_CAUSE_OFFSET 0x000000c0
-#define RESET_CAUSE_LAST_MSB 2
-#define RESET_CAUSE_LAST_LSB 0
-#define RESET_CAUSE_LAST_MASK 0x00000007
-#define RESET_CAUSE_LAST_GET(x) (((x) & RESET_CAUSE_LAST_MASK) >> RESET_CAUSE_LAST_LSB)
-#define RESET_CAUSE_LAST_SET(x) (((x) << RESET_CAUSE_LAST_LSB) & RESET_CAUSE_LAST_MASK)
-
-#define SYSTEM_SLEEP_ADDRESS 0x000000c4
-#define SYSTEM_SLEEP_OFFSET 0x000000c4
-#define SYSTEM_SLEEP_HOST_IF_MSB 4
-#define SYSTEM_SLEEP_HOST_IF_LSB 4
-#define SYSTEM_SLEEP_HOST_IF_MASK 0x00000010
-#define SYSTEM_SLEEP_HOST_IF_GET(x) (((x) & SYSTEM_SLEEP_HOST_IF_MASK) >> SYSTEM_SLEEP_HOST_IF_LSB)
-#define SYSTEM_SLEEP_HOST_IF_SET(x) (((x) << SYSTEM_SLEEP_HOST_IF_LSB) & SYSTEM_SLEEP_HOST_IF_MASK)
-#define SYSTEM_SLEEP_MBOX_MSB 3
-#define SYSTEM_SLEEP_MBOX_LSB 3
-#define SYSTEM_SLEEP_MBOX_MASK 0x00000008
-#define SYSTEM_SLEEP_MBOX_GET(x) (((x) & SYSTEM_SLEEP_MBOX_MASK) >> SYSTEM_SLEEP_MBOX_LSB)
-#define SYSTEM_SLEEP_MBOX_SET(x) (((x) << SYSTEM_SLEEP_MBOX_LSB) & SYSTEM_SLEEP_MBOX_MASK)
-#define SYSTEM_SLEEP_MAC_IF_MSB 2
-#define SYSTEM_SLEEP_MAC_IF_LSB 2
-#define SYSTEM_SLEEP_MAC_IF_MASK 0x00000004
-#define SYSTEM_SLEEP_MAC_IF_GET(x) (((x) & SYSTEM_SLEEP_MAC_IF_MASK) >> SYSTEM_SLEEP_MAC_IF_LSB)
-#define SYSTEM_SLEEP_MAC_IF_SET(x) (((x) << SYSTEM_SLEEP_MAC_IF_LSB) & SYSTEM_SLEEP_MAC_IF_MASK)
-#define SYSTEM_SLEEP_LIGHT_MSB 1
-#define SYSTEM_SLEEP_LIGHT_LSB 1
-#define SYSTEM_SLEEP_LIGHT_MASK 0x00000002
-#define SYSTEM_SLEEP_LIGHT_GET(x) (((x) & SYSTEM_SLEEP_LIGHT_MASK) >> SYSTEM_SLEEP_LIGHT_LSB)
-#define SYSTEM_SLEEP_LIGHT_SET(x) (((x) << SYSTEM_SLEEP_LIGHT_LSB) & SYSTEM_SLEEP_LIGHT_MASK)
-#define SYSTEM_SLEEP_DISABLE_MSB 0
-#define SYSTEM_SLEEP_DISABLE_LSB 0
-#define SYSTEM_SLEEP_DISABLE_MASK 0x00000001
-#define SYSTEM_SLEEP_DISABLE_GET(x) (((x) & SYSTEM_SLEEP_DISABLE_MASK) >> SYSTEM_SLEEP_DISABLE_LSB)
-#define SYSTEM_SLEEP_DISABLE_SET(x) (((x) << SYSTEM_SLEEP_DISABLE_LSB) & SYSTEM_SLEEP_DISABLE_MASK)
-
-#define SDIO_WRAPPER_ADDRESS 0x000000c8
-#define SDIO_WRAPPER_OFFSET 0x000000c8
-#define SDIO_WRAPPER_SLEEP_MSB 3
-#define SDIO_WRAPPER_SLEEP_LSB 3
-#define SDIO_WRAPPER_SLEEP_MASK 0x00000008
-#define SDIO_WRAPPER_SLEEP_GET(x) (((x) & SDIO_WRAPPER_SLEEP_MASK) >> SDIO_WRAPPER_SLEEP_LSB)
-#define SDIO_WRAPPER_SLEEP_SET(x) (((x) << SDIO_WRAPPER_SLEEP_LSB) & SDIO_WRAPPER_SLEEP_MASK)
-#define SDIO_WRAPPER_WAKEUP_MSB 2
-#define SDIO_WRAPPER_WAKEUP_LSB 2
-#define SDIO_WRAPPER_WAKEUP_MASK 0x00000004
-#define SDIO_WRAPPER_WAKEUP_GET(x) (((x) & SDIO_WRAPPER_WAKEUP_MASK) >> SDIO_WRAPPER_WAKEUP_LSB)
-#define SDIO_WRAPPER_WAKEUP_SET(x) (((x) << SDIO_WRAPPER_WAKEUP_LSB) & SDIO_WRAPPER_WAKEUP_MASK)
-#define SDIO_WRAPPER_SOC_ON_MSB 1
-#define SDIO_WRAPPER_SOC_ON_LSB 1
-#define SDIO_WRAPPER_SOC_ON_MASK 0x00000002
-#define SDIO_WRAPPER_SOC_ON_GET(x) (((x) & SDIO_WRAPPER_SOC_ON_MASK) >> SDIO_WRAPPER_SOC_ON_LSB)
-#define SDIO_WRAPPER_SOC_ON_SET(x) (((x) << SDIO_WRAPPER_SOC_ON_LSB) & SDIO_WRAPPER_SOC_ON_MASK)
-#define SDIO_WRAPPER_ON_MSB 0
-#define SDIO_WRAPPER_ON_LSB 0
-#define SDIO_WRAPPER_ON_MASK 0x00000001
-#define SDIO_WRAPPER_ON_GET(x) (((x) & SDIO_WRAPPER_ON_MASK) >> SDIO_WRAPPER_ON_LSB)
-#define SDIO_WRAPPER_ON_SET(x) (((x) << SDIO_WRAPPER_ON_LSB) & SDIO_WRAPPER_ON_MASK)
-
-#define MAC_SLEEP_CONTROL_ADDRESS 0x000000cc
-#define MAC_SLEEP_CONTROL_OFFSET 0x000000cc
-#define MAC_SLEEP_CONTROL_ENABLE_MSB 1
-#define MAC_SLEEP_CONTROL_ENABLE_LSB 0
-#define MAC_SLEEP_CONTROL_ENABLE_MASK 0x00000003
-#define MAC_SLEEP_CONTROL_ENABLE_GET(x) (((x) & MAC_SLEEP_CONTROL_ENABLE_MASK) >> MAC_SLEEP_CONTROL_ENABLE_LSB)
-#define MAC_SLEEP_CONTROL_ENABLE_SET(x) (((x) << MAC_SLEEP_CONTROL_ENABLE_LSB) & MAC_SLEEP_CONTROL_ENABLE_MASK)
-
-#define KEEP_AWAKE_ADDRESS 0x000000d0
-#define KEEP_AWAKE_OFFSET 0x000000d0
-#define KEEP_AWAKE_COUNT_MSB 7
-#define KEEP_AWAKE_COUNT_LSB 0
-#define KEEP_AWAKE_COUNT_MASK 0x000000ff
-#define KEEP_AWAKE_COUNT_GET(x) (((x) & KEEP_AWAKE_COUNT_MASK) >> KEEP_AWAKE_COUNT_LSB)
-#define KEEP_AWAKE_COUNT_SET(x) (((x) << KEEP_AWAKE_COUNT_LSB) & KEEP_AWAKE_COUNT_MASK)
-
-#define LPO_CAL_TIME_ADDRESS 0x000000d4
-#define LPO_CAL_TIME_OFFSET 0x000000d4
-#define LPO_CAL_TIME_LENGTH_MSB 13
-#define LPO_CAL_TIME_LENGTH_LSB 0
-#define LPO_CAL_TIME_LENGTH_MASK 0x00003fff
-#define LPO_CAL_TIME_LENGTH_GET(x) (((x) & LPO_CAL_TIME_LENGTH_MASK) >> LPO_CAL_TIME_LENGTH_LSB)
-#define LPO_CAL_TIME_LENGTH_SET(x) (((x) << LPO_CAL_TIME_LENGTH_LSB) & LPO_CAL_TIME_LENGTH_MASK)
-
-#define LPO_INIT_DIVIDEND_INT_ADDRESS 0x000000d8
-#define LPO_INIT_DIVIDEND_INT_OFFSET 0x000000d8
-#define LPO_INIT_DIVIDEND_INT_VALUE_MSB 23
-#define LPO_INIT_DIVIDEND_INT_VALUE_LSB 0
-#define LPO_INIT_DIVIDEND_INT_VALUE_MASK 0x00ffffff
-#define LPO_INIT_DIVIDEND_INT_VALUE_GET(x) (((x) & LPO_INIT_DIVIDEND_INT_VALUE_MASK) >> LPO_INIT_DIVIDEND_INT_VALUE_LSB)
-#define LPO_INIT_DIVIDEND_INT_VALUE_SET(x) (((x) << LPO_INIT_DIVIDEND_INT_VALUE_LSB) & LPO_INIT_DIVIDEND_INT_VALUE_MASK)
-
-#define LPO_INIT_DIVIDEND_FRACTION_ADDRESS 0x000000dc
-#define LPO_INIT_DIVIDEND_FRACTION_OFFSET 0x000000dc
-#define LPO_INIT_DIVIDEND_FRACTION_VALUE_MSB 10
-#define LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB 0
-#define LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK 0x000007ff
-#define LPO_INIT_DIVIDEND_FRACTION_VALUE_GET(x) (((x) & LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK) >> LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB)
-#define LPO_INIT_DIVIDEND_FRACTION_VALUE_SET(x) (((x) << LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB) & LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK)
-
-#define LPO_CAL_ADDRESS 0x000000e0
-#define LPO_CAL_OFFSET 0x000000e0
-#define LPO_CAL_ENABLE_MSB 20
-#define LPO_CAL_ENABLE_LSB 20
-#define LPO_CAL_ENABLE_MASK 0x00100000
-#define LPO_CAL_ENABLE_GET(x) (((x) & LPO_CAL_ENABLE_MASK) >> LPO_CAL_ENABLE_LSB)
-#define LPO_CAL_ENABLE_SET(x) (((x) << LPO_CAL_ENABLE_LSB) & LPO_CAL_ENABLE_MASK)
-#define LPO_CAL_COUNT_MSB 19
-#define LPO_CAL_COUNT_LSB 0
-#define LPO_CAL_COUNT_MASK 0x000fffff
-#define LPO_CAL_COUNT_GET(x) (((x) & LPO_CAL_COUNT_MASK) >> LPO_CAL_COUNT_LSB)
-#define LPO_CAL_COUNT_SET(x) (((x) << LPO_CAL_COUNT_LSB) & LPO_CAL_COUNT_MASK)
-
-#define LPO_CAL_TEST_CONTROL_ADDRESS 0x000000e4
-#define LPO_CAL_TEST_CONTROL_OFFSET 0x000000e4
-#define LPO_CAL_TEST_CONTROL_ENABLE_MSB 5
-#define LPO_CAL_TEST_CONTROL_ENABLE_LSB 5
-#define LPO_CAL_TEST_CONTROL_ENABLE_MASK 0x00000020
-#define LPO_CAL_TEST_CONTROL_ENABLE_GET(x) (((x) & LPO_CAL_TEST_CONTROL_ENABLE_MASK) >> LPO_CAL_TEST_CONTROL_ENABLE_LSB)
-#define LPO_CAL_TEST_CONTROL_ENABLE_SET(x) (((x) << LPO_CAL_TEST_CONTROL_ENABLE_LSB) & LPO_CAL_TEST_CONTROL_ENABLE_MASK)
-#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_MSB 4
-#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB 0
-#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK 0x0000001f
-#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_GET(x) (((x) & LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK) >> LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB)
-#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_SET(x) (((x) << LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB) & LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK)
-
-#define LPO_CAL_TEST_STATUS_ADDRESS 0x000000e8
-#define LPO_CAL_TEST_STATUS_OFFSET 0x000000e8
-#define LPO_CAL_TEST_STATUS_READY_MSB 16
-#define LPO_CAL_TEST_STATUS_READY_LSB 16
-#define LPO_CAL_TEST_STATUS_READY_MASK 0x00010000
-#define LPO_CAL_TEST_STATUS_READY_GET(x) (((x) & LPO_CAL_TEST_STATUS_READY_MASK) >> LPO_CAL_TEST_STATUS_READY_LSB)
-#define LPO_CAL_TEST_STATUS_READY_SET(x) (((x) << LPO_CAL_TEST_STATUS_READY_LSB) & LPO_CAL_TEST_STATUS_READY_MASK)
-#define LPO_CAL_TEST_STATUS_COUNT_MSB 15
-#define LPO_CAL_TEST_STATUS_COUNT_LSB 0
-#define LPO_CAL_TEST_STATUS_COUNT_MASK 0x0000ffff
-#define LPO_CAL_TEST_STATUS_COUNT_GET(x) (((x) & LPO_CAL_TEST_STATUS_COUNT_MASK) >> LPO_CAL_TEST_STATUS_COUNT_LSB)
-#define LPO_CAL_TEST_STATUS_COUNT_SET(x) (((x) << LPO_CAL_TEST_STATUS_COUNT_LSB) & LPO_CAL_TEST_STATUS_COUNT_MASK)
-
-#define CHIP_ID_ADDRESS 0x000000ec
-#define CHIP_ID_OFFSET 0x000000ec
-#define CHIP_ID_DEVICE_ID_MSB 31
-#define CHIP_ID_DEVICE_ID_LSB 16
-#define CHIP_ID_DEVICE_ID_MASK 0xffff0000
-#define CHIP_ID_DEVICE_ID_GET(x) (((x) & CHIP_ID_DEVICE_ID_MASK) >> CHIP_ID_DEVICE_ID_LSB)
-#define CHIP_ID_DEVICE_ID_SET(x) (((x) << CHIP_ID_DEVICE_ID_LSB) & CHIP_ID_DEVICE_ID_MASK)
-#define CHIP_ID_CONFIG_ID_MSB 15
-#define CHIP_ID_CONFIG_ID_LSB 4
-#define CHIP_ID_CONFIG_ID_MASK 0x0000fff0
-#define CHIP_ID_CONFIG_ID_GET(x) (((x) & CHIP_ID_CONFIG_ID_MASK) >> CHIP_ID_CONFIG_ID_LSB)
-#define CHIP_ID_CONFIG_ID_SET(x) (((x) << CHIP_ID_CONFIG_ID_LSB) & CHIP_ID_CONFIG_ID_MASK)
-#define CHIP_ID_VERSION_ID_MSB 3
-#define CHIP_ID_VERSION_ID_LSB 0
-#define CHIP_ID_VERSION_ID_MASK 0x0000000f
-#define CHIP_ID_VERSION_ID_GET(x) (((x) & CHIP_ID_VERSION_ID_MASK) >> CHIP_ID_VERSION_ID_LSB)
-#define CHIP_ID_VERSION_ID_SET(x) (((x) << CHIP_ID_VERSION_ID_LSB) & CHIP_ID_VERSION_ID_MASK)
-
-#define DERIVED_RTC_CLK_ADDRESS 0x000000f0
-#define DERIVED_RTC_CLK_OFFSET 0x000000f0
-#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MSB 20
-#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB 20
-#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK 0x00100000
-#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_GET(x) (((x) & DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK) >> DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB)
-#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_SET(x) (((x) << DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB) & DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK)
-#define DERIVED_RTC_CLK_EXTERNAL_DETECT_MSB 18
-#define DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB 18
-#define DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK 0x00040000
-#define DERIVED_RTC_CLK_EXTERNAL_DETECT_GET(x) (((x) & DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK) >> DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB)
-#define DERIVED_RTC_CLK_EXTERNAL_DETECT_SET(x) (((x) << DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB) & DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK)
-#define DERIVED_RTC_CLK_FORCE_MSB 17
-#define DERIVED_RTC_CLK_FORCE_LSB 16
-#define DERIVED_RTC_CLK_FORCE_MASK 0x00030000
-#define DERIVED_RTC_CLK_FORCE_GET(x) (((x) & DERIVED_RTC_CLK_FORCE_MASK) >> DERIVED_RTC_CLK_FORCE_LSB)
-#define DERIVED_RTC_CLK_FORCE_SET(x) (((x) << DERIVED_RTC_CLK_FORCE_LSB) & DERIVED_RTC_CLK_FORCE_MASK)
-#define DERIVED_RTC_CLK_PERIOD_MSB 15
-#define DERIVED_RTC_CLK_PERIOD_LSB 1
-#define DERIVED_RTC_CLK_PERIOD_MASK 0x0000fffe
-#define DERIVED_RTC_CLK_PERIOD_GET(x) (((x) & DERIVED_RTC_CLK_PERIOD_MASK) >> DERIVED_RTC_CLK_PERIOD_LSB)
-#define DERIVED_RTC_CLK_PERIOD_SET(x) (((x) << DERIVED_RTC_CLK_PERIOD_LSB) & DERIVED_RTC_CLK_PERIOD_MASK)
-
-#define MAC_PCU_SLP32_MODE_ADDRESS 0x000000f4
-#define MAC_PCU_SLP32_MODE_OFFSET 0x000000f4
-#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_MSB 21
-#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_LSB 21
-#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_MASK 0x00200000
-#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_GET(x) (((x) & MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_MASK) >> MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_LSB)
-#define MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_SET(x) (((x) << MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_LSB) & MAC_PCU_SLP32_MODE_TSF_WRITE_PENDING_MASK)
-#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MSB 19
-#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB 0
-#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK 0x000fffff
-#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_GET(x) (((x) & MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK) >> MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB)
-#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_SET(x) (((x) << MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB) & MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK)
-
-#define MAC_PCU_SLP32_WAKE_ADDRESS 0x000000f8
-#define MAC_PCU_SLP32_WAKE_OFFSET 0x000000f8
-#define MAC_PCU_SLP32_WAKE_XTL_TIME_MSB 15
-#define MAC_PCU_SLP32_WAKE_XTL_TIME_LSB 0
-#define MAC_PCU_SLP32_WAKE_XTL_TIME_MASK 0x0000ffff
-#define MAC_PCU_SLP32_WAKE_XTL_TIME_GET(x) (((x) & MAC_PCU_SLP32_WAKE_XTL_TIME_MASK) >> MAC_PCU_SLP32_WAKE_XTL_TIME_LSB)
-#define MAC_PCU_SLP32_WAKE_XTL_TIME_SET(x) (((x) << MAC_PCU_SLP32_WAKE_XTL_TIME_LSB) & MAC_PCU_SLP32_WAKE_XTL_TIME_MASK)
-
-#define MAC_PCU_SLP32_INC_ADDRESS 0x000000fc
-#define MAC_PCU_SLP32_INC_OFFSET 0x000000fc
-#define MAC_PCU_SLP32_INC_TSF_INC_MSB 19
-#define MAC_PCU_SLP32_INC_TSF_INC_LSB 0
-#define MAC_PCU_SLP32_INC_TSF_INC_MASK 0x000fffff
-#define MAC_PCU_SLP32_INC_TSF_INC_GET(x) (((x) & MAC_PCU_SLP32_INC_TSF_INC_MASK) >> MAC_PCU_SLP32_INC_TSF_INC_LSB)
-#define MAC_PCU_SLP32_INC_TSF_INC_SET(x) (((x) << MAC_PCU_SLP32_INC_TSF_INC_LSB) & MAC_PCU_SLP32_INC_TSF_INC_MASK)
-
-#define MAC_PCU_SLP_MIB1_ADDRESS 0x00000100
-#define MAC_PCU_SLP_MIB1_OFFSET 0x00000100
-#define MAC_PCU_SLP_MIB1_SLEEP_CNT_MSB 31
-#define MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB 0
-#define MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK 0xffffffff
-#define MAC_PCU_SLP_MIB1_SLEEP_CNT_GET(x) (((x) & MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK) >> MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB)
-#define MAC_PCU_SLP_MIB1_SLEEP_CNT_SET(x) (((x) << MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB) & MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK)
-
-#define MAC_PCU_SLP_MIB2_ADDRESS 0x00000104
-#define MAC_PCU_SLP_MIB2_OFFSET 0x00000104
-#define MAC_PCU_SLP_MIB2_CYCLE_CNT_MSB 31
-#define MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB 0
-#define MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK 0xffffffff
-#define MAC_PCU_SLP_MIB2_CYCLE_CNT_GET(x) (((x) & MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK) >> MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB)
-#define MAC_PCU_SLP_MIB2_CYCLE_CNT_SET(x) (((x) << MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB) & MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK)
-
-#define MAC_PCU_SLP_MIB3_ADDRESS 0x00000108
-#define MAC_PCU_SLP_MIB3_OFFSET 0x00000108
-#define MAC_PCU_SLP_MIB3_PENDING_MSB 1
-#define MAC_PCU_SLP_MIB3_PENDING_LSB 1
-#define MAC_PCU_SLP_MIB3_PENDING_MASK 0x00000002
-#define MAC_PCU_SLP_MIB3_PENDING_GET(x) (((x) & MAC_PCU_SLP_MIB3_PENDING_MASK) >> MAC_PCU_SLP_MIB3_PENDING_LSB)
-#define MAC_PCU_SLP_MIB3_PENDING_SET(x) (((x) << MAC_PCU_SLP_MIB3_PENDING_LSB) & MAC_PCU_SLP_MIB3_PENDING_MASK)
-#define MAC_PCU_SLP_MIB3_CLR_CNT_MSB 0
-#define MAC_PCU_SLP_MIB3_CLR_CNT_LSB 0
-#define MAC_PCU_SLP_MIB3_CLR_CNT_MASK 0x00000001
-#define MAC_PCU_SLP_MIB3_CLR_CNT_GET(x) (((x) & MAC_PCU_SLP_MIB3_CLR_CNT_MASK) >> MAC_PCU_SLP_MIB3_CLR_CNT_LSB)
-#define MAC_PCU_SLP_MIB3_CLR_CNT_SET(x) (((x) << MAC_PCU_SLP_MIB3_CLR_CNT_LSB) & MAC_PCU_SLP_MIB3_CLR_CNT_MASK)
-
-#define MAC_PCU_SLP_BEACON_ADDRESS 0x0000010c
-#define MAC_PCU_SLP_BEACON_OFFSET 0x0000010c
-#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_MSB 24
-#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_LSB 24
-#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_MASK 0x01000000
-#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_GET(x) (((x) & MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_MASK) >> MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_LSB)
-#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_SET(x) (((x) << MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_LSB) & MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_ENABLE_MASK)
-#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_MSB 23
-#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_LSB 0
-#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_MASK 0x00ffffff
-#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_GET(x) (((x) & MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_MASK) >> MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_LSB)
-#define MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_SET(x) (((x) << MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_LSB) & MAC_PCU_SLP_BEACON_BMISS_TIMEOUT_MASK)
-
-#define POWER_REG_ADDRESS 0x00000110
-#define POWER_REG_OFFSET 0x00000110
-#define POWER_REG_VLVL_MSB 11
-#define POWER_REG_VLVL_LSB 8
-#define POWER_REG_VLVL_MASK 0x00000f00
-#define POWER_REG_VLVL_GET(x) (((x) & POWER_REG_VLVL_MASK) >> POWER_REG_VLVL_LSB)
-#define POWER_REG_VLVL_SET(x) (((x) << POWER_REG_VLVL_LSB) & POWER_REG_VLVL_MASK)
-#define POWER_REG_CPU_INT_ENABLE_MSB 7
-#define POWER_REG_CPU_INT_ENABLE_LSB 7
-#define POWER_REG_CPU_INT_ENABLE_MASK 0x00000080
-#define POWER_REG_CPU_INT_ENABLE_GET(x) (((x) & POWER_REG_CPU_INT_ENABLE_MASK) >> POWER_REG_CPU_INT_ENABLE_LSB)
-#define POWER_REG_CPU_INT_ENABLE_SET(x) (((x) << POWER_REG_CPU_INT_ENABLE_LSB) & POWER_REG_CPU_INT_ENABLE_MASK)
-#define POWER_REG_WLAN_ISO_DIS_MSB 6
-#define POWER_REG_WLAN_ISO_DIS_LSB 6
-#define POWER_REG_WLAN_ISO_DIS_MASK 0x00000040
-#define POWER_REG_WLAN_ISO_DIS_GET(x) (((x) & POWER_REG_WLAN_ISO_DIS_MASK) >> POWER_REG_WLAN_ISO_DIS_LSB)
-#define POWER_REG_WLAN_ISO_DIS_SET(x) (((x) << POWER_REG_WLAN_ISO_DIS_LSB) & POWER_REG_WLAN_ISO_DIS_MASK)
-#define POWER_REG_WLAN_ISO_CNTL_MSB 5
-#define POWER_REG_WLAN_ISO_CNTL_LSB 5
-#define POWER_REG_WLAN_ISO_CNTL_MASK 0x00000020
-#define POWER_REG_WLAN_ISO_CNTL_GET(x) (((x) & POWER_REG_WLAN_ISO_CNTL_MASK) >> POWER_REG_WLAN_ISO_CNTL_LSB)
-#define POWER_REG_WLAN_ISO_CNTL_SET(x) (((x) << POWER_REG_WLAN_ISO_CNTL_LSB) & POWER_REG_WLAN_ISO_CNTL_MASK)
-#define POWER_REG_RADIO_PWD_EN_MSB 4
-#define POWER_REG_RADIO_PWD_EN_LSB 4
-#define POWER_REG_RADIO_PWD_EN_MASK 0x00000010
-#define POWER_REG_RADIO_PWD_EN_GET(x) (((x) & POWER_REG_RADIO_PWD_EN_MASK) >> POWER_REG_RADIO_PWD_EN_LSB)
-#define POWER_REG_RADIO_PWD_EN_SET(x) (((x) << POWER_REG_RADIO_PWD_EN_LSB) & POWER_REG_RADIO_PWD_EN_MASK)
-#define POWER_REG_SOC_SCALE_EN_MSB 3
-#define POWER_REG_SOC_SCALE_EN_LSB 3
-#define POWER_REG_SOC_SCALE_EN_MASK 0x00000008
-#define POWER_REG_SOC_SCALE_EN_GET(x) (((x) & POWER_REG_SOC_SCALE_EN_MASK) >> POWER_REG_SOC_SCALE_EN_LSB)
-#define POWER_REG_SOC_SCALE_EN_SET(x) (((x) << POWER_REG_SOC_SCALE_EN_LSB) & POWER_REG_SOC_SCALE_EN_MASK)
-#define POWER_REG_WLAN_SCALE_EN_MSB 2
-#define POWER_REG_WLAN_SCALE_EN_LSB 2
-#define POWER_REG_WLAN_SCALE_EN_MASK 0x00000004
-#define POWER_REG_WLAN_SCALE_EN_GET(x) (((x) & POWER_REG_WLAN_SCALE_EN_MASK) >> POWER_REG_WLAN_SCALE_EN_LSB)
-#define POWER_REG_WLAN_SCALE_EN_SET(x) (((x) << POWER_REG_WLAN_SCALE_EN_LSB) & POWER_REG_WLAN_SCALE_EN_MASK)
-#define POWER_REG_WLAN_PWD_EN_MSB 1
-#define POWER_REG_WLAN_PWD_EN_LSB 1
-#define POWER_REG_WLAN_PWD_EN_MASK 0x00000002
-#define POWER_REG_WLAN_PWD_EN_GET(x) (((x) & POWER_REG_WLAN_PWD_EN_MASK) >> POWER_REG_WLAN_PWD_EN_LSB)
-#define POWER_REG_WLAN_PWD_EN_SET(x) (((x) << POWER_REG_WLAN_PWD_EN_LSB) & POWER_REG_WLAN_PWD_EN_MASK)
-#define POWER_REG_POWER_EN_MSB 0
-#define POWER_REG_POWER_EN_LSB 0
-#define POWER_REG_POWER_EN_MASK 0x00000001
-#define POWER_REG_POWER_EN_GET(x) (((x) & POWER_REG_POWER_EN_MASK) >> POWER_REG_POWER_EN_LSB)
-#define POWER_REG_POWER_EN_SET(x) (((x) << POWER_REG_POWER_EN_LSB) & POWER_REG_POWER_EN_MASK)
-
-#define CORE_CLK_CTRL_ADDRESS 0x00000114
-#define CORE_CLK_CTRL_OFFSET 0x00000114
-#define CORE_CLK_CTRL_DIV_MSB 2
-#define CORE_CLK_CTRL_DIV_LSB 0
-#define CORE_CLK_CTRL_DIV_MASK 0x00000007
-#define CORE_CLK_CTRL_DIV_GET(x) (((x) & CORE_CLK_CTRL_DIV_MASK) >> CORE_CLK_CTRL_DIV_LSB)
-#define CORE_CLK_CTRL_DIV_SET(x) (((x) << CORE_CLK_CTRL_DIV_LSB) & CORE_CLK_CTRL_DIV_MASK)
-
-#define SDIO_SETUP_CIRCUIT_ADDRESS 0x00000120
-#define SDIO_SETUP_CIRCUIT_OFFSET 0x00000120
-#define SDIO_SETUP_CIRCUIT_VECTOR_MSB 7
-#define SDIO_SETUP_CIRCUIT_VECTOR_LSB 0
-#define SDIO_SETUP_CIRCUIT_VECTOR_MASK 0x000000ff
-#define SDIO_SETUP_CIRCUIT_VECTOR_GET(x) (((x) & SDIO_SETUP_CIRCUIT_VECTOR_MASK) >> SDIO_SETUP_CIRCUIT_VECTOR_LSB)
-#define SDIO_SETUP_CIRCUIT_VECTOR_SET(x) (((x) << SDIO_SETUP_CIRCUIT_VECTOR_LSB) & SDIO_SETUP_CIRCUIT_VECTOR_MASK)
-
-#define SDIO_SETUP_CONFIG_ADDRESS 0x00000140
-#define SDIO_SETUP_CONFIG_OFFSET 0x00000140
-#define SDIO_SETUP_CONFIG_ENABLE_MSB 1
-#define SDIO_SETUP_CONFIG_ENABLE_LSB 1
-#define SDIO_SETUP_CONFIG_ENABLE_MASK 0x00000002
-#define SDIO_SETUP_CONFIG_ENABLE_GET(x) (((x) & SDIO_SETUP_CONFIG_ENABLE_MASK) >> SDIO_SETUP_CONFIG_ENABLE_LSB)
-#define SDIO_SETUP_CONFIG_ENABLE_SET(x) (((x) << SDIO_SETUP_CONFIG_ENABLE_LSB) & SDIO_SETUP_CONFIG_ENABLE_MASK)
-#define SDIO_SETUP_CONFIG_CLEAR_MSB 0
-#define SDIO_SETUP_CONFIG_CLEAR_LSB 0
-#define SDIO_SETUP_CONFIG_CLEAR_MASK 0x00000001
-#define SDIO_SETUP_CONFIG_CLEAR_GET(x) (((x) & SDIO_SETUP_CONFIG_CLEAR_MASK) >> SDIO_SETUP_CONFIG_CLEAR_LSB)
-#define SDIO_SETUP_CONFIG_CLEAR_SET(x) (((x) << SDIO_SETUP_CONFIG_CLEAR_LSB) & SDIO_SETUP_CONFIG_CLEAR_MASK)
-
-#define CPU_SETUP_CONFIG_ADDRESS 0x00000144
-#define CPU_SETUP_CONFIG_OFFSET 0x00000144
-#define CPU_SETUP_CONFIG_ENABLE_MSB 1
-#define CPU_SETUP_CONFIG_ENABLE_LSB 1
-#define CPU_SETUP_CONFIG_ENABLE_MASK 0x00000002
-#define CPU_SETUP_CONFIG_ENABLE_GET(x) (((x) & CPU_SETUP_CONFIG_ENABLE_MASK) >> CPU_SETUP_CONFIG_ENABLE_LSB)
-#define CPU_SETUP_CONFIG_ENABLE_SET(x) (((x) << CPU_SETUP_CONFIG_ENABLE_LSB) & CPU_SETUP_CONFIG_ENABLE_MASK)
-#define CPU_SETUP_CONFIG_CLEAR_MSB 0
-#define CPU_SETUP_CONFIG_CLEAR_LSB 0
-#define CPU_SETUP_CONFIG_CLEAR_MASK 0x00000001
-#define CPU_SETUP_CONFIG_CLEAR_GET(x) (((x) & CPU_SETUP_CONFIG_CLEAR_MASK) >> CPU_SETUP_CONFIG_CLEAR_LSB)
-#define CPU_SETUP_CONFIG_CLEAR_SET(x) (((x) << CPU_SETUP_CONFIG_CLEAR_LSB) & CPU_SETUP_CONFIG_CLEAR_MASK)
-
-#define CPU_SETUP_CIRCUIT_ADDRESS 0x00000160
-#define CPU_SETUP_CIRCUIT_OFFSET 0x00000160
-#define CPU_SETUP_CIRCUIT_VECTOR_MSB 7
-#define CPU_SETUP_CIRCUIT_VECTOR_LSB 0
-#define CPU_SETUP_CIRCUIT_VECTOR_MASK 0x000000ff
-#define CPU_SETUP_CIRCUIT_VECTOR_GET(x) (((x) & CPU_SETUP_CIRCUIT_VECTOR_MASK) >> CPU_SETUP_CIRCUIT_VECTOR_LSB)
-#define CPU_SETUP_CIRCUIT_VECTOR_SET(x) (((x) << CPU_SETUP_CIRCUIT_VECTOR_LSB) & CPU_SETUP_CIRCUIT_VECTOR_MASK)
-
-#define BB_SETUP_CONFIG_ADDRESS 0x00000180
-#define BB_SETUP_CONFIG_OFFSET 0x00000180
-#define BB_SETUP_CONFIG_ENABLE_MSB 1
-#define BB_SETUP_CONFIG_ENABLE_LSB 1
-#define BB_SETUP_CONFIG_ENABLE_MASK 0x00000002
-#define BB_SETUP_CONFIG_ENABLE_GET(x) (((x) & BB_SETUP_CONFIG_ENABLE_MASK) >> BB_SETUP_CONFIG_ENABLE_LSB)
-#define BB_SETUP_CONFIG_ENABLE_SET(x) (((x) << BB_SETUP_CONFIG_ENABLE_LSB) & BB_SETUP_CONFIG_ENABLE_MASK)
-#define BB_SETUP_CONFIG_CLEAR_MSB 0
-#define BB_SETUP_CONFIG_CLEAR_LSB 0
-#define BB_SETUP_CONFIG_CLEAR_MASK 0x00000001
-#define BB_SETUP_CONFIG_CLEAR_GET(x) (((x) & BB_SETUP_CONFIG_CLEAR_MASK) >> BB_SETUP_CONFIG_CLEAR_LSB)
-#define BB_SETUP_CONFIG_CLEAR_SET(x) (((x) << BB_SETUP_CONFIG_CLEAR_LSB) & BB_SETUP_CONFIG_CLEAR_MASK)
-
-#define BB_SETUP_CIRCUIT_ADDRESS 0x000001a0
-#define BB_SETUP_CIRCUIT_OFFSET 0x000001a0
-#define BB_SETUP_CIRCUIT_VECTOR_MSB 7
-#define BB_SETUP_CIRCUIT_VECTOR_LSB 0
-#define BB_SETUP_CIRCUIT_VECTOR_MASK 0x000000ff
-#define BB_SETUP_CIRCUIT_VECTOR_GET(x) (((x) & BB_SETUP_CIRCUIT_VECTOR_MASK) >> BB_SETUP_CIRCUIT_VECTOR_LSB)
-#define BB_SETUP_CIRCUIT_VECTOR_SET(x) (((x) << BB_SETUP_CIRCUIT_VECTOR_LSB) & BB_SETUP_CIRCUIT_VECTOR_MASK)
-
-#define GPIO_WAKEUP_CONTROL_ADDRESS 0x000001c0
-#define GPIO_WAKEUP_CONTROL_OFFSET 0x000001c0
-#define GPIO_WAKEUP_CONTROL_ENABLE_MSB 0
-#define GPIO_WAKEUP_CONTROL_ENABLE_LSB 0
-#define GPIO_WAKEUP_CONTROL_ENABLE_MASK 0x00000001
-#define GPIO_WAKEUP_CONTROL_ENABLE_GET(x) (((x) & GPIO_WAKEUP_CONTROL_ENABLE_MASK) >> GPIO_WAKEUP_CONTROL_ENABLE_LSB)
-#define GPIO_WAKEUP_CONTROL_ENABLE_SET(x) (((x) << GPIO_WAKEUP_CONTROL_ENABLE_LSB) & GPIO_WAKEUP_CONTROL_ENABLE_MASK)
-
-
-#ifndef __ASSEMBLER__
-
-typedef struct rtc_reg_reg_s {
- volatile unsigned int reset_control;
- volatile unsigned int xtal_control;
- volatile unsigned int tcxo_detect;
- volatile unsigned int xtal_test;
- volatile unsigned int quadrature;
- volatile unsigned int pll_control;
- volatile unsigned int pll_settle;
- volatile unsigned int xtal_settle;
- volatile unsigned int cpu_clock;
- volatile unsigned int clock_out;
- volatile unsigned int clock_control;
- volatile unsigned int bias_override;
- volatile unsigned int wdt_control;
- volatile unsigned int wdt_status;
- volatile unsigned int wdt;
- volatile unsigned int wdt_count;
- volatile unsigned int wdt_reset;
- volatile unsigned int int_status;
- volatile unsigned int lf_timer0;
- volatile unsigned int lf_timer_count0;
- volatile unsigned int lf_timer_control0;
- volatile unsigned int lf_timer_status0;
- volatile unsigned int lf_timer1;
- volatile unsigned int lf_timer_count1;
- volatile unsigned int lf_timer_control1;
- volatile unsigned int lf_timer_status1;
- volatile unsigned int lf_timer2;
- volatile unsigned int lf_timer_count2;
- volatile unsigned int lf_timer_control2;
- volatile unsigned int lf_timer_status2;
- volatile unsigned int lf_timer3;
- volatile unsigned int lf_timer_count3;
- volatile unsigned int lf_timer_control3;
- volatile unsigned int lf_timer_status3;
- volatile unsigned int hf_timer;
- volatile unsigned int hf_timer_count;
- volatile unsigned int hf_lf_count;
- volatile unsigned int hf_timer_control;
- volatile unsigned int hf_timer_status;
- volatile unsigned int rtc_control;
- volatile unsigned int rtc_time;
- volatile unsigned int rtc_date;
- volatile unsigned int rtc_set_time;
- volatile unsigned int rtc_set_date;
- volatile unsigned int rtc_set_alarm;
- volatile unsigned int rtc_config;
- volatile unsigned int rtc_alarm_status;
- volatile unsigned int uart_wakeup;
- volatile unsigned int reset_cause;
- volatile unsigned int system_sleep;
- volatile unsigned int sdio_wrapper;
- volatile unsigned int mac_sleep_control;
- volatile unsigned int keep_awake;
- volatile unsigned int lpo_cal_time;
- volatile unsigned int lpo_init_dividend_int;
- volatile unsigned int lpo_init_dividend_fraction;
- volatile unsigned int lpo_cal;
- volatile unsigned int lpo_cal_test_control;
- volatile unsigned int lpo_cal_test_status;
- volatile unsigned int chip_id;
- volatile unsigned int derived_rtc_clk;
- volatile unsigned int mac_pcu_slp32_mode;
- volatile unsigned int mac_pcu_slp32_wake;
- volatile unsigned int mac_pcu_slp32_inc;
- volatile unsigned int mac_pcu_slp_mib1;
- volatile unsigned int mac_pcu_slp_mib2;
- volatile unsigned int mac_pcu_slp_mib3;
- volatile unsigned int mac_pcu_slp_beacon;
- volatile unsigned int power_reg;
- volatile unsigned int core_clk_ctrl;
- unsigned char pad0[8]; /* pad to 0x120 */
- volatile unsigned int sdio_setup_circuit[8];
- volatile unsigned int sdio_setup_config;
- volatile unsigned int cpu_setup_config;
- unsigned char pad1[24]; /* pad to 0x160 */
- volatile unsigned int cpu_setup_circuit[8];
- volatile unsigned int bb_setup_config;
- unsigned char pad2[28]; /* pad to 0x1a0 */
- volatile unsigned int bb_setup_circuit[8];
- volatile unsigned int gpio_wakeup_control;
-} rtc_reg_reg_t;
-
-#endif /* __ASSEMBLER__ */
-
-#endif /* _RTC_REG_H_ */
diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw2.0/hw/si_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw2.0/hw/si_reg.h
deleted file mode 100644
index 16fb99c..0000000
--- a/drivers/staging/ath6kl/include/common/AR6002/hw2.0/hw/si_reg.h
+++ /dev/null
@@ -1,186 +0,0 @@
-#ifndef _SI_REG_REG_H_
-#define _SI_REG_REG_H_
-
-#define SI_CONFIG_ADDRESS 0x00000000
-#define SI_CONFIG_OFFSET 0x00000000
-#define SI_CONFIG_ERR_INT_MSB 19
-#define SI_CONFIG_ERR_INT_LSB 19
-#define SI_CONFIG_ERR_INT_MASK 0x00080000
-#define SI_CONFIG_ERR_INT_GET(x) (((x) & SI_CONFIG_ERR_INT_MASK) >> SI_CONFIG_ERR_INT_LSB)
-#define SI_CONFIG_ERR_INT_SET(x) (((x) << SI_CONFIG_ERR_INT_LSB) & SI_CONFIG_ERR_INT_MASK)
-#define SI_CONFIG_BIDIR_OD_DATA_MSB 18
-#define SI_CONFIG_BIDIR_OD_DATA_LSB 18
-#define SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000
-#define SI_CONFIG_BIDIR_OD_DATA_GET(x) (((x) & SI_CONFIG_BIDIR_OD_DATA_MASK) >> SI_CONFIG_BIDIR_OD_DATA_LSB)
-#define SI_CONFIG_BIDIR_OD_DATA_SET(x) (((x) << SI_CONFIG_BIDIR_OD_DATA_LSB) & SI_CONFIG_BIDIR_OD_DATA_MASK)
-#define SI_CONFIG_I2C_MSB 16
-#define SI_CONFIG_I2C_LSB 16
-#define SI_CONFIG_I2C_MASK 0x00010000
-#define SI_CONFIG_I2C_GET(x) (((x) & SI_CONFIG_I2C_MASK) >> SI_CONFIG_I2C_LSB)
-#define SI_CONFIG_I2C_SET(x) (((x) << SI_CONFIG_I2C_LSB) & SI_CONFIG_I2C_MASK)
-#define SI_CONFIG_POS_SAMPLE_MSB 7
-#define SI_CONFIG_POS_SAMPLE_LSB 7
-#define SI_CONFIG_POS_SAMPLE_MASK 0x00000080
-#define SI_CONFIG_POS_SAMPLE_GET(x) (((x) & SI_CONFIG_POS_SAMPLE_MASK) >> SI_CONFIG_POS_SAMPLE_LSB)
-#define SI_CONFIG_POS_SAMPLE_SET(x) (((x) << SI_CONFIG_POS_SAMPLE_LSB) & SI_CONFIG_POS_SAMPLE_MASK)
-#define SI_CONFIG_POS_DRIVE_MSB 6
-#define SI_CONFIG_POS_DRIVE_LSB 6
-#define SI_CONFIG_POS_DRIVE_MASK 0x00000040
-#define SI_CONFIG_POS_DRIVE_GET(x) (((x) & SI_CONFIG_POS_DRIVE_MASK) >> SI_CONFIG_POS_DRIVE_LSB)
-#define SI_CONFIG_POS_DRIVE_SET(x) (((x) << SI_CONFIG_POS_DRIVE_LSB) & SI_CONFIG_POS_DRIVE_MASK)
-#define SI_CONFIG_INACTIVE_DATA_MSB 5
-#define SI_CONFIG_INACTIVE_DATA_LSB 5
-#define SI_CONFIG_INACTIVE_DATA_MASK 0x00000020
-#define SI_CONFIG_INACTIVE_DATA_GET(x) (((x) & SI_CONFIG_INACTIVE_DATA_MASK) >> SI_CONFIG_INACTIVE_DATA_LSB)
-#define SI_CONFIG_INACTIVE_DATA_SET(x) (((x) << SI_CONFIG_INACTIVE_DATA_LSB) & SI_CONFIG_INACTIVE_DATA_MASK)
-#define SI_CONFIG_INACTIVE_CLK_MSB 4
-#define SI_CONFIG_INACTIVE_CLK_LSB 4
-#define SI_CONFIG_INACTIVE_CLK_MASK 0x00000010
-#define SI_CONFIG_INACTIVE_CLK_GET(x) (((x) & SI_CONFIG_INACTIVE_CLK_MASK) >> SI_CONFIG_INACTIVE_CLK_LSB)
-#define SI_CONFIG_INACTIVE_CLK_SET(x) (((x) << SI_CONFIG_INACTIVE_CLK_LSB) & SI_CONFIG_INACTIVE_CLK_MASK)
-#define SI_CONFIG_DIVIDER_MSB 3
-#define SI_CONFIG_DIVIDER_LSB 0
-#define SI_CONFIG_DIVIDER_MASK 0x0000000f
-#define SI_CONFIG_DIVIDER_GET(x) (((x) & SI_CONFIG_DIVIDER_MASK) >> SI_CONFIG_DIVIDER_LSB)
-#define SI_CONFIG_DIVIDER_SET(x) (((x) << SI_CONFIG_DIVIDER_LSB) & SI_CONFIG_DIVIDER_MASK)
-
-#define SI_CS_ADDRESS 0x00000004
-#define SI_CS_OFFSET 0x00000004
-#define SI_CS_BIT_CNT_IN_LAST_BYTE_MSB 13
-#define SI_CS_BIT_CNT_IN_LAST_BYTE_LSB 11
-#define SI_CS_BIT_CNT_IN_LAST_BYTE_MASK 0x00003800
-#define SI_CS_BIT_CNT_IN_LAST_BYTE_GET(x) (((x) & SI_CS_BIT_CNT_IN_LAST_BYTE_MASK) >> SI_CS_BIT_CNT_IN_LAST_BYTE_LSB)
-#define SI_CS_BIT_CNT_IN_LAST_BYTE_SET(x) (((x) << SI_CS_BIT_CNT_IN_LAST_BYTE_LSB) & SI_CS_BIT_CNT_IN_LAST_BYTE_MASK)
-#define SI_CS_DONE_ERR_MSB 10
-#define SI_CS_DONE_ERR_LSB 10
-#define SI_CS_DONE_ERR_MASK 0x00000400
-#define SI_CS_DONE_ERR_GET(x) (((x) & SI_CS_DONE_ERR_MASK) >> SI_CS_DONE_ERR_LSB)
-#define SI_CS_DONE_ERR_SET(x) (((x) << SI_CS_DONE_ERR_LSB) & SI_CS_DONE_ERR_MASK)
-#define SI_CS_DONE_INT_MSB 9
-#define SI_CS_DONE_INT_LSB 9
-#define SI_CS_DONE_INT_MASK 0x00000200
-#define SI_CS_DONE_INT_GET(x) (((x) & SI_CS_DONE_INT_MASK) >> SI_CS_DONE_INT_LSB)
-#define SI_CS_DONE_INT_SET(x) (((x) << SI_CS_DONE_INT_LSB) & SI_CS_DONE_INT_MASK)
-#define SI_CS_START_MSB 8
-#define SI_CS_START_LSB 8
-#define SI_CS_START_MASK 0x00000100
-#define SI_CS_START_GET(x) (((x) & SI_CS_START_MASK) >> SI_CS_START_LSB)
-#define SI_CS_START_SET(x) (((x) << SI_CS_START_LSB) & SI_CS_START_MASK)
-#define SI_CS_RX_CNT_MSB 7
-#define SI_CS_RX_CNT_LSB 4
-#define SI_CS_RX_CNT_MASK 0x000000f0
-#define SI_CS_RX_CNT_GET(x) (((x) & SI_CS_RX_CNT_MASK) >> SI_CS_RX_CNT_LSB)
-#define SI_CS_RX_CNT_SET(x) (((x) << SI_CS_RX_CNT_LSB) & SI_CS_RX_CNT_MASK)
-#define SI_CS_TX_CNT_MSB 3
-#define SI_CS_TX_CNT_LSB 0
-#define SI_CS_TX_CNT_MASK 0x0000000f
-#define SI_CS_TX_CNT_GET(x) (((x) & SI_CS_TX_CNT_MASK) >> SI_CS_TX_CNT_LSB)
-#define SI_CS_TX_CNT_SET(x) (((x) << SI_CS_TX_CNT_LSB) & SI_CS_TX_CNT_MASK)
-
-#define SI_TX_DATA0_ADDRESS 0x00000008
-#define SI_TX_DATA0_OFFSET 0x00000008
-#define SI_TX_DATA0_DATA3_MSB 31
-#define SI_TX_DATA0_DATA3_LSB 24
-#define SI_TX_DATA0_DATA3_MASK 0xff000000
-#define SI_TX_DATA0_DATA3_GET(x) (((x) & SI_TX_DATA0_DATA3_MASK) >> SI_TX_DATA0_DATA3_LSB)
-#define SI_TX_DATA0_DATA3_SET(x) (((x) << SI_TX_DATA0_DATA3_LSB) & SI_TX_DATA0_DATA3_MASK)
-#define SI_TX_DATA0_DATA2_MSB 23
-#define SI_TX_DATA0_DATA2_LSB 16
-#define SI_TX_DATA0_DATA2_MASK 0x00ff0000
-#define SI_TX_DATA0_DATA2_GET(x) (((x) & SI_TX_DATA0_DATA2_MASK) >> SI_TX_DATA0_DATA2_LSB)
-#define SI_TX_DATA0_DATA2_SET(x) (((x) << SI_TX_DATA0_DATA2_LSB) & SI_TX_DATA0_DATA2_MASK)
-#define SI_TX_DATA0_DATA1_MSB 15
-#define SI_TX_DATA0_DATA1_LSB 8
-#define SI_TX_DATA0_DATA1_MASK 0x0000ff00
-#define SI_TX_DATA0_DATA1_GET(x) (((x) & SI_TX_DATA0_DATA1_MASK) >> SI_TX_DATA0_DATA1_LSB)
-#define SI_TX_DATA0_DATA1_SET(x) (((x) << SI_TX_DATA0_DATA1_LSB) & SI_TX_DATA0_DATA1_MASK)
-#define SI_TX_DATA0_DATA0_MSB 7
-#define SI_TX_DATA0_DATA0_LSB 0
-#define SI_TX_DATA0_DATA0_MASK 0x000000ff
-#define SI_TX_DATA0_DATA0_GET(x) (((x) & SI_TX_DATA0_DATA0_MASK) >> SI_TX_DATA0_DATA0_LSB)
-#define SI_TX_DATA0_DATA0_SET(x) (((x) << SI_TX_DATA0_DATA0_LSB) & SI_TX_DATA0_DATA0_MASK)
-
-#define SI_TX_DATA1_ADDRESS 0x0000000c
-#define SI_TX_DATA1_OFFSET 0x0000000c
-#define SI_TX_DATA1_DATA7_MSB 31
-#define SI_TX_DATA1_DATA7_LSB 24
-#define SI_TX_DATA1_DATA7_MASK 0xff000000
-#define SI_TX_DATA1_DATA7_GET(x) (((x) & SI_TX_DATA1_DATA7_MASK) >> SI_TX_DATA1_DATA7_LSB)
-#define SI_TX_DATA1_DATA7_SET(x) (((x) << SI_TX_DATA1_DATA7_LSB) & SI_TX_DATA1_DATA7_MASK)
-#define SI_TX_DATA1_DATA6_MSB 23
-#define SI_TX_DATA1_DATA6_LSB 16
-#define SI_TX_DATA1_DATA6_MASK 0x00ff0000
-#define SI_TX_DATA1_DATA6_GET(x) (((x) & SI_TX_DATA1_DATA6_MASK) >> SI_TX_DATA1_DATA6_LSB)
-#define SI_TX_DATA1_DATA6_SET(x) (((x) << SI_TX_DATA1_DATA6_LSB) & SI_TX_DATA1_DATA6_MASK)
-#define SI_TX_DATA1_DATA5_MSB 15
-#define SI_TX_DATA1_DATA5_LSB 8
-#define SI_TX_DATA1_DATA5_MASK 0x0000ff00
-#define SI_TX_DATA1_DATA5_GET(x) (((x) & SI_TX_DATA1_DATA5_MASK) >> SI_TX_DATA1_DATA5_LSB)
-#define SI_TX_DATA1_DATA5_SET(x) (((x) << SI_TX_DATA1_DATA5_LSB) & SI_TX_DATA1_DATA5_MASK)
-#define SI_TX_DATA1_DATA4_MSB 7
-#define SI_TX_DATA1_DATA4_LSB 0
-#define SI_TX_DATA1_DATA4_MASK 0x000000ff
-#define SI_TX_DATA1_DATA4_GET(x) (((x) & SI_TX_DATA1_DATA4_MASK) >> SI_TX_DATA1_DATA4_LSB)
-#define SI_TX_DATA1_DATA4_SET(x) (((x) << SI_TX_DATA1_DATA4_LSB) & SI_TX_DATA1_DATA4_MASK)
-
-#define SI_RX_DATA0_ADDRESS 0x00000010
-#define SI_RX_DATA0_OFFSET 0x00000010
-#define SI_RX_DATA0_DATA3_MSB 31
-#define SI_RX_DATA0_DATA3_LSB 24
-#define SI_RX_DATA0_DATA3_MASK 0xff000000
-#define SI_RX_DATA0_DATA3_GET(x) (((x) & SI_RX_DATA0_DATA3_MASK) >> SI_RX_DATA0_DATA3_LSB)
-#define SI_RX_DATA0_DATA3_SET(x) (((x) << SI_RX_DATA0_DATA3_LSB) & SI_RX_DATA0_DATA3_MASK)
-#define SI_RX_DATA0_DATA2_MSB 23
-#define SI_RX_DATA0_DATA2_LSB 16
-#define SI_RX_DATA0_DATA2_MASK 0x00ff0000
-#define SI_RX_DATA0_DATA2_GET(x) (((x) & SI_RX_DATA0_DATA2_MASK) >> SI_RX_DATA0_DATA2_LSB)
-#define SI_RX_DATA0_DATA2_SET(x) (((x) << SI_RX_DATA0_DATA2_LSB) & SI_RX_DATA0_DATA2_MASK)
-#define SI_RX_DATA0_DATA1_MSB 15
-#define SI_RX_DATA0_DATA1_LSB 8
-#define SI_RX_DATA0_DATA1_MASK 0x0000ff00
-#define SI_RX_DATA0_DATA1_GET(x) (((x) & SI_RX_DATA0_DATA1_MASK) >> SI_RX_DATA0_DATA1_LSB)
-#define SI_RX_DATA0_DATA1_SET(x) (((x) << SI_RX_DATA0_DATA1_LSB) & SI_RX_DATA0_DATA1_MASK)
-#define SI_RX_DATA0_DATA0_MSB 7
-#define SI_RX_DATA0_DATA0_LSB 0
-#define SI_RX_DATA0_DATA0_MASK 0x000000ff
-#define SI_RX_DATA0_DATA0_GET(x) (((x) & SI_RX_DATA0_DATA0_MASK) >> SI_RX_DATA0_DATA0_LSB)
-#define SI_RX_DATA0_DATA0_SET(x) (((x) << SI_RX_DATA0_DATA0_LSB) & SI_RX_DATA0_DATA0_MASK)
-
-#define SI_RX_DATA1_ADDRESS 0x00000014
-#define SI_RX_DATA1_OFFSET 0x00000014
-#define SI_RX_DATA1_DATA7_MSB 31
-#define SI_RX_DATA1_DATA7_LSB 24
-#define SI_RX_DATA1_DATA7_MASK 0xff000000
-#define SI_RX_DATA1_DATA7_GET(x) (((x) & SI_RX_DATA1_DATA7_MASK) >> SI_RX_DATA1_DATA7_LSB)
-#define SI_RX_DATA1_DATA7_SET(x) (((x) << SI_RX_DATA1_DATA7_LSB) & SI_RX_DATA1_DATA7_MASK)
-#define SI_RX_DATA1_DATA6_MSB 23
-#define SI_RX_DATA1_DATA6_LSB 16
-#define SI_RX_DATA1_DATA6_MASK 0x00ff0000
-#define SI_RX_DATA1_DATA6_GET(x) (((x) & SI_RX_DATA1_DATA6_MASK) >> SI_RX_DATA1_DATA6_LSB)
-#define SI_RX_DATA1_DATA6_SET(x) (((x) << SI_RX_DATA1_DATA6_LSB) & SI_RX_DATA1_DATA6_MASK)
-#define SI_RX_DATA1_DATA5_MSB 15
-#define SI_RX_DATA1_DATA5_LSB 8
-#define SI_RX_DATA1_DATA5_MASK 0x0000ff00
-#define SI_RX_DATA1_DATA5_GET(x) (((x) & SI_RX_DATA1_DATA5_MASK) >> SI_RX_DATA1_DATA5_LSB)
-#define SI_RX_DATA1_DATA5_SET(x) (((x) << SI_RX_DATA1_DATA5_LSB) & SI_RX_DATA1_DATA5_MASK)
-#define SI_RX_DATA1_DATA4_MSB 7
-#define SI_RX_DATA1_DATA4_LSB 0
-#define SI_RX_DATA1_DATA4_MASK 0x000000ff
-#define SI_RX_DATA1_DATA4_GET(x) (((x) & SI_RX_DATA1_DATA4_MASK) >> SI_RX_DATA1_DATA4_LSB)
-#define SI_RX_DATA1_DATA4_SET(x) (((x) << SI_RX_DATA1_DATA4_LSB) & SI_RX_DATA1_DATA4_MASK)
-
-
-#ifndef __ASSEMBLER__
-
-typedef struct si_reg_reg_s {
- volatile unsigned int si_config;
- volatile unsigned int si_cs;
- volatile unsigned int si_tx_data0;
- volatile unsigned int si_tx_data1;
- volatile unsigned int si_rx_data0;
- volatile unsigned int si_rx_data1;
-} si_reg_reg_t;
-
-#endif /* __ASSEMBLER__ */
-
-#endif /* _SI_REG_H_ */
diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw2.0/hw/uart_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw2.0/hw/uart_reg.h
deleted file mode 100644
index 5db321b..0000000
--- a/drivers/staging/ath6kl/include/common/AR6002/hw2.0/hw/uart_reg.h
+++ /dev/null
@@ -1,327 +0,0 @@
-#ifndef _UART_REG_REG_H_
-#define _UART_REG_REG_H_
-
-#define RBR_ADDRESS 0x00000000
-#define RBR_OFFSET 0x00000000
-#define RBR_RBR_MSB 7
-#define RBR_RBR_LSB 0
-#define RBR_RBR_MASK 0x000000ff
-#define RBR_RBR_GET(x) (((x) & RBR_RBR_MASK) >> RBR_RBR_LSB)
-#define RBR_RBR_SET(x) (((x) << RBR_RBR_LSB) & RBR_RBR_MASK)
-
-#define THR_ADDRESS 0x00000000
-#define THR_OFFSET 0x00000000
-#define THR_THR_MSB 7
-#define THR_THR_LSB 0
-#define THR_THR_MASK 0x000000ff
-#define THR_THR_GET(x) (((x) & THR_THR_MASK) >> THR_THR_LSB)
-#define THR_THR_SET(x) (((x) << THR_THR_LSB) & THR_THR_MASK)
-
-#define DLL_ADDRESS 0x00000000
-#define DLL_OFFSET 0x00000000
-#define DLL_DLL_MSB 7
-#define DLL_DLL_LSB 0
-#define DLL_DLL_MASK 0x000000ff
-#define DLL_DLL_GET(x) (((x) & DLL_DLL_MASK) >> DLL_DLL_LSB)
-#define DLL_DLL_SET(x) (((x) << DLL_DLL_LSB) & DLL_DLL_MASK)
-
-#define DLH_ADDRESS 0x00000004
-#define DLH_OFFSET 0x00000004
-#define DLH_DLH_MSB 7
-#define DLH_DLH_LSB 0
-#define DLH_DLH_MASK 0x000000ff
-#define DLH_DLH_GET(x) (((x) & DLH_DLH_MASK) >> DLH_DLH_LSB)
-#define DLH_DLH_SET(x) (((x) << DLH_DLH_LSB) & DLH_DLH_MASK)
-
-#define IER_ADDRESS 0x00000004
-#define IER_OFFSET 0x00000004
-#define IER_EDDSI_MSB 3
-#define IER_EDDSI_LSB 3
-#define IER_EDDSI_MASK 0x00000008
-#define IER_EDDSI_GET(x) (((x) & IER_EDDSI_MASK) >> IER_EDDSI_LSB)
-#define IER_EDDSI_SET(x) (((x) << IER_EDDSI_LSB) & IER_EDDSI_MASK)
-#define IER_ELSI_MSB 2
-#define IER_ELSI_LSB 2
-#define IER_ELSI_MASK 0x00000004
-#define IER_ELSI_GET(x) (((x) & IER_ELSI_MASK) >> IER_ELSI_LSB)
-#define IER_ELSI_SET(x) (((x) << IER_ELSI_LSB) & IER_ELSI_MASK)
-#define IER_ETBEI_MSB 1
-#define IER_ETBEI_LSB 1
-#define IER_ETBEI_MASK 0x00000002
-#define IER_ETBEI_GET(x) (((x) & IER_ETBEI_MASK) >> IER_ETBEI_LSB)
-#define IER_ETBEI_SET(x) (((x) << IER_ETBEI_LSB) & IER_ETBEI_MASK)
-#define IER_ERBFI_MSB 0
-#define IER_ERBFI_LSB 0
-#define IER_ERBFI_MASK 0x00000001
-#define IER_ERBFI_GET(x) (((x) & IER_ERBFI_MASK) >> IER_ERBFI_LSB)
-#define IER_ERBFI_SET(x) (((x) << IER_ERBFI_LSB) & IER_ERBFI_MASK)
-
-#define IIR_ADDRESS 0x00000008
-#define IIR_OFFSET 0x00000008
-#define IIR_FIFO_STATUS_MSB 7
-#define IIR_FIFO_STATUS_LSB 6
-#define IIR_FIFO_STATUS_MASK 0x000000c0
-#define IIR_FIFO_STATUS_GET(x) (((x) & IIR_FIFO_STATUS_MASK) >> IIR_FIFO_STATUS_LSB)
-#define IIR_FIFO_STATUS_SET(x) (((x) << IIR_FIFO_STATUS_LSB) & IIR_FIFO_STATUS_MASK)
-#define IIR_IID_MSB 3
-#define IIR_IID_LSB 0
-#define IIR_IID_MASK 0x0000000f
-#define IIR_IID_GET(x) (((x) & IIR_IID_MASK) >> IIR_IID_LSB)
-#define IIR_IID_SET(x) (((x) << IIR_IID_LSB) & IIR_IID_MASK)
-
-#define FCR_ADDRESS 0x00000008
-#define FCR_OFFSET 0x00000008
-#define FCR_RCVR_TRIG_MSB 7
-#define FCR_RCVR_TRIG_LSB 6
-#define FCR_RCVR_TRIG_MASK 0x000000c0
-#define FCR_RCVR_TRIG_GET(x) (((x) & FCR_RCVR_TRIG_MASK) >> FCR_RCVR_TRIG_LSB)
-#define FCR_RCVR_TRIG_SET(x) (((x) << FCR_RCVR_TRIG_LSB) & FCR_RCVR_TRIG_MASK)
-#define FCR_DMA_MODE_MSB 3
-#define FCR_DMA_MODE_LSB 3
-#define FCR_DMA_MODE_MASK 0x00000008
-#define FCR_DMA_MODE_GET(x) (((x) & FCR_DMA_MODE_MASK) >> FCR_DMA_MODE_LSB)
-#define FCR_DMA_MODE_SET(x) (((x) << FCR_DMA_MODE_LSB) & FCR_DMA_MODE_MASK)
-#define FCR_XMIT_FIFO_RST_MSB 2
-#define FCR_XMIT_FIFO_RST_LSB 2
-#define FCR_XMIT_FIFO_RST_MASK 0x00000004
-#define FCR_XMIT_FIFO_RST_GET(x) (((x) & FCR_XMIT_FIFO_RST_MASK) >> FCR_XMIT_FIFO_RST_LSB)
-#define FCR_XMIT_FIFO_RST_SET(x) (((x) << FCR_XMIT_FIFO_RST_LSB) & FCR_XMIT_FIFO_RST_MASK)
-#define FCR_RCVR_FIFO_RST_MSB 1
-#define FCR_RCVR_FIFO_RST_LSB 1
-#define FCR_RCVR_FIFO_RST_MASK 0x00000002
-#define FCR_RCVR_FIFO_RST_GET(x) (((x) & FCR_RCVR_FIFO_RST_MASK) >> FCR_RCVR_FIFO_RST_LSB)
-#define FCR_RCVR_FIFO_RST_SET(x) (((x) << FCR_RCVR_FIFO_RST_LSB) & FCR_RCVR_FIFO_RST_MASK)
-#define FCR_FIFO_EN_MSB 0
-#define FCR_FIFO_EN_LSB 0
-#define FCR_FIFO_EN_MASK 0x00000001
-#define FCR_FIFO_EN_GET(x) (((x) & FCR_FIFO_EN_MASK) >> FCR_FIFO_EN_LSB)
-#define FCR_FIFO_EN_SET(x) (((x) << FCR_FIFO_EN_LSB) & FCR_FIFO_EN_MASK)
-
-#define LCR_ADDRESS 0x0000000c
-#define LCR_OFFSET 0x0000000c
-#define LCR_DLAB_MSB 7
-#define LCR_DLAB_LSB 7
-#define LCR_DLAB_MASK 0x00000080
-#define LCR_DLAB_GET(x) (((x) & LCR_DLAB_MASK) >> LCR_DLAB_LSB)
-#define LCR_DLAB_SET(x) (((x) << LCR_DLAB_LSB) & LCR_DLAB_MASK)
-#define LCR_BREAK_MSB 6
-#define LCR_BREAK_LSB 6
-#define LCR_BREAK_MASK 0x00000040
-#define LCR_BREAK_GET(x) (((x) & LCR_BREAK_MASK) >> LCR_BREAK_LSB)
-#define LCR_BREAK_SET(x) (((x) << LCR_BREAK_LSB) & LCR_BREAK_MASK)
-#define LCR_EPS_MSB 4
-#define LCR_EPS_LSB 4
-#define LCR_EPS_MASK 0x00000010
-#define LCR_EPS_GET(x) (((x) & LCR_EPS_MASK) >> LCR_EPS_LSB)
-#define LCR_EPS_SET(x) (((x) << LCR_EPS_LSB) & LCR_EPS_MASK)
-#define LCR_PEN_MSB 3
-#define LCR_PEN_LSB 3
-#define LCR_PEN_MASK 0x00000008
-#define LCR_PEN_GET(x) (((x) & LCR_PEN_MASK) >> LCR_PEN_LSB)
-#define LCR_PEN_SET(x) (((x) << LCR_PEN_LSB) & LCR_PEN_MASK)
-#define LCR_STOP_MSB 2
-#define LCR_STOP_LSB 2
-#define LCR_STOP_MASK 0x00000004
-#define LCR_STOP_GET(x) (((x) & LCR_STOP_MASK) >> LCR_STOP_LSB)
-#define LCR_STOP_SET(x) (((x) << LCR_STOP_LSB) & LCR_STOP_MASK)
-#define LCR_CLS_MSB 1
-#define LCR_CLS_LSB 0
-#define LCR_CLS_MASK 0x00000003
-#define LCR_CLS_GET(x) (((x) & LCR_CLS_MASK) >> LCR_CLS_LSB)
-#define LCR_CLS_SET(x) (((x) << LCR_CLS_LSB) & LCR_CLS_MASK)
-
-#define MCR_ADDRESS 0x00000010
-#define MCR_OFFSET 0x00000010
-#define MCR_LOOPBACK_MSB 5
-#define MCR_LOOPBACK_LSB 5
-#define MCR_LOOPBACK_MASK 0x00000020
-#define MCR_LOOPBACK_GET(x) (((x) & MCR_LOOPBACK_MASK) >> MCR_LOOPBACK_LSB)
-#define MCR_LOOPBACK_SET(x) (((x) << MCR_LOOPBACK_LSB) & MCR_LOOPBACK_MASK)
-#define MCR_OUT2_MSB 3
-#define MCR_OUT2_LSB 3
-#define MCR_OUT2_MASK 0x00000008
-#define MCR_OUT2_GET(x) (((x) & MCR_OUT2_MASK) >> MCR_OUT2_LSB)
-#define MCR_OUT2_SET(x) (((x) << MCR_OUT2_LSB) & MCR_OUT2_MASK)
-#define MCR_OUT1_MSB 2
-#define MCR_OUT1_LSB 2
-#define MCR_OUT1_MASK 0x00000004
-#define MCR_OUT1_GET(x) (((x) & MCR_OUT1_MASK) >> MCR_OUT1_LSB)
-#define MCR_OUT1_SET(x) (((x) << MCR_OUT1_LSB) & MCR_OUT1_MASK)
-#define MCR_RTS_MSB 1
-#define MCR_RTS_LSB 1
-#define MCR_RTS_MASK 0x00000002
-#define MCR_RTS_GET(x) (((x) & MCR_RTS_MASK) >> MCR_RTS_LSB)
-#define MCR_RTS_SET(x) (((x) << MCR_RTS_LSB) & MCR_RTS_MASK)
-#define MCR_DTR_MSB 0
-#define MCR_DTR_LSB 0
-#define MCR_DTR_MASK 0x00000001
-#define MCR_DTR_GET(x) (((x) & MCR_DTR_MASK) >> MCR_DTR_LSB)
-#define MCR_DTR_SET(x) (((x) << MCR_DTR_LSB) & MCR_DTR_MASK)
-
-#define LSR_ADDRESS 0x00000014
-#define LSR_OFFSET 0x00000014
-#define LSR_FERR_MSB 7
-#define LSR_FERR_LSB 7
-#define LSR_FERR_MASK 0x00000080
-#define LSR_FERR_GET(x) (((x) & LSR_FERR_MASK) >> LSR_FERR_LSB)
-#define LSR_FERR_SET(x) (((x) << LSR_FERR_LSB) & LSR_FERR_MASK)
-#define LSR_TEMT_MSB 6
-#define LSR_TEMT_LSB 6
-#define LSR_TEMT_MASK 0x00000040
-#define LSR_TEMT_GET(x) (((x) & LSR_TEMT_MASK) >> LSR_TEMT_LSB)
-#define LSR_TEMT_SET(x) (((x) << LSR_TEMT_LSB) & LSR_TEMT_MASK)
-#define LSR_THRE_MSB 5
-#define LSR_THRE_LSB 5
-#define LSR_THRE_MASK 0x00000020
-#define LSR_THRE_GET(x) (((x) & LSR_THRE_MASK) >> LSR_THRE_LSB)
-#define LSR_THRE_SET(x) (((x) << LSR_THRE_LSB) & LSR_THRE_MASK)
-#define LSR_BI_MSB 4
-#define LSR_BI_LSB 4
-#define LSR_BI_MASK 0x00000010
-#define LSR_BI_GET(x) (((x) & LSR_BI_MASK) >> LSR_BI_LSB)
-#define LSR_BI_SET(x) (((x) << LSR_BI_LSB) & LSR_BI_MASK)
-#define LSR_FE_MSB 3
-#define LSR_FE_LSB 3
-#define LSR_FE_MASK 0x00000008
-#define LSR_FE_GET(x) (((x) & LSR_FE_MASK) >> LSR_FE_LSB)
-#define LSR_FE_SET(x) (((x) << LSR_FE_LSB) & LSR_FE_MASK)
-#define LSR_PE_MSB 2
-#define LSR_PE_LSB 2
-#define LSR_PE_MASK 0x00000004
-#define LSR_PE_GET(x) (((x) & LSR_PE_MASK) >> LSR_PE_LSB)
-#define LSR_PE_SET(x) (((x) << LSR_PE_LSB) & LSR_PE_MASK)
-#define LSR_OE_MSB 1
-#define LSR_OE_LSB 1
-#define LSR_OE_MASK 0x00000002
-#define LSR_OE_GET(x) (((x) & LSR_OE_MASK) >> LSR_OE_LSB)
-#define LSR_OE_SET(x) (((x) << LSR_OE_LSB) & LSR_OE_MASK)
-#define LSR_DR_MSB 0
-#define LSR_DR_LSB 0
-#define LSR_DR_MASK 0x00000001
-#define LSR_DR_GET(x) (((x) & LSR_DR_MASK) >> LSR_DR_LSB)
-#define LSR_DR_SET(x) (((x) << LSR_DR_LSB) & LSR_DR_MASK)
-
-#define MSR_ADDRESS 0x00000018
-#define MSR_OFFSET 0x00000018
-#define MSR_DCD_MSB 7
-#define MSR_DCD_LSB 7
-#define MSR_DCD_MASK 0x00000080
-#define MSR_DCD_GET(x) (((x) & MSR_DCD_MASK) >> MSR_DCD_LSB)
-#define MSR_DCD_SET(x) (((x) << MSR_DCD_LSB) & MSR_DCD_MASK)
-#define MSR_RI_MSB 6
-#define MSR_RI_LSB 6
-#define MSR_RI_MASK 0x00000040
-#define MSR_RI_GET(x) (((x) & MSR_RI_MASK) >> MSR_RI_LSB)
-#define MSR_RI_SET(x) (((x) << MSR_RI_LSB) & MSR_RI_MASK)
-#define MSR_DSR_MSB 5
-#define MSR_DSR_LSB 5
-#define MSR_DSR_MASK 0x00000020
-#define MSR_DSR_GET(x) (((x) & MSR_DSR_MASK) >> MSR_DSR_LSB)
-#define MSR_DSR_SET(x) (((x) << MSR_DSR_LSB) & MSR_DSR_MASK)
-#define MSR_CTS_MSB 4
-#define MSR_CTS_LSB 4
-#define MSR_CTS_MASK 0x00000010
-#define MSR_CTS_GET(x) (((x) & MSR_CTS_MASK) >> MSR_CTS_LSB)
-#define MSR_CTS_SET(x) (((x) << MSR_CTS_LSB) & MSR_CTS_MASK)
-#define MSR_DDCD_MSB 3
-#define MSR_DDCD_LSB 3
-#define MSR_DDCD_MASK 0x00000008
-#define MSR_DDCD_GET(x) (((x) & MSR_DDCD_MASK) >> MSR_DDCD_LSB)
-#define MSR_DDCD_SET(x) (((x) << MSR_DDCD_LSB) & MSR_DDCD_MASK)
-#define MSR_TERI_MSB 2
-#define MSR_TERI_LSB 2
-#define MSR_TERI_MASK 0x00000004
-#define MSR_TERI_GET(x) (((x) & MSR_TERI_MASK) >> MSR_TERI_LSB)
-#define MSR_TERI_SET(x) (((x) << MSR_TERI_LSB) & MSR_TERI_MASK)
-#define MSR_DDSR_MSB 1
-#define MSR_DDSR_LSB 1
-#define MSR_DDSR_MASK 0x00000002
-#define MSR_DDSR_GET(x) (((x) & MSR_DDSR_MASK) >> MSR_DDSR_LSB)
-#define MSR_DDSR_SET(x) (((x) << MSR_DDSR_LSB) & MSR_DDSR_MASK)
-#define MSR_DCTS_MSB 0
-#define MSR_DCTS_LSB 0
-#define MSR_DCTS_MASK 0x00000001
-#define MSR_DCTS_GET(x) (((x) & MSR_DCTS_MASK) >> MSR_DCTS_LSB)
-#define MSR_DCTS_SET(x) (((x) << MSR_DCTS_LSB) & MSR_DCTS_MASK)
-
-#define SCR_ADDRESS 0x0000001c
-#define SCR_OFFSET 0x0000001c
-#define SCR_SCR_MSB 7
-#define SCR_SCR_LSB 0
-#define SCR_SCR_MASK 0x000000ff
-#define SCR_SCR_GET(x) (((x) & SCR_SCR_MASK) >> SCR_SCR_LSB)
-#define SCR_SCR_SET(x) (((x) << SCR_SCR_LSB) & SCR_SCR_MASK)
-
-#define SRBR_ADDRESS 0x00000020
-#define SRBR_OFFSET 0x00000020
-#define SRBR_SRBR_MSB 7
-#define SRBR_SRBR_LSB 0
-#define SRBR_SRBR_MASK 0x000000ff
-#define SRBR_SRBR_GET(x) (((x) & SRBR_SRBR_MASK) >> SRBR_SRBR_LSB)
-#define SRBR_SRBR_SET(x) (((x) << SRBR_SRBR_LSB) & SRBR_SRBR_MASK)
-
-#define SIIR_ADDRESS 0x00000028
-#define SIIR_OFFSET 0x00000028
-#define SIIR_SIIR_MSB 7
-#define SIIR_SIIR_LSB 0
-#define SIIR_SIIR_MASK 0x000000ff
-#define SIIR_SIIR_GET(x) (((x) & SIIR_SIIR_MASK) >> SIIR_SIIR_LSB)
-#define SIIR_SIIR_SET(x) (((x) << SIIR_SIIR_LSB) & SIIR_SIIR_MASK)
-
-#define MWR_ADDRESS 0x0000002c
-#define MWR_OFFSET 0x0000002c
-#define MWR_MWR_MSB 31
-#define MWR_MWR_LSB 0
-#define MWR_MWR_MASK 0xffffffff
-#define MWR_MWR_GET(x) (((x) & MWR_MWR_MASK) >> MWR_MWR_LSB)
-#define MWR_MWR_SET(x) (((x) << MWR_MWR_LSB) & MWR_MWR_MASK)
-
-#define SLSR_ADDRESS 0x00000034
-#define SLSR_OFFSET 0x00000034
-#define SLSR_SLSR_MSB 7
-#define SLSR_SLSR_LSB 0
-#define SLSR_SLSR_MASK 0x000000ff
-#define SLSR_SLSR_GET(x) (((x) & SLSR_SLSR_MASK) >> SLSR_SLSR_LSB)
-#define SLSR_SLSR_SET(x) (((x) << SLSR_SLSR_LSB) & SLSR_SLSR_MASK)
-
-#define SMSR_ADDRESS 0x00000038
-#define SMSR_OFFSET 0x00000038
-#define SMSR_SMSR_MSB 7
-#define SMSR_SMSR_LSB 0
-#define SMSR_SMSR_MASK 0x000000ff
-#define SMSR_SMSR_GET(x) (((x) & SMSR_SMSR_MASK) >> SMSR_SMSR_LSB)
-#define SMSR_SMSR_SET(x) (((x) << SMSR_SMSR_LSB) & SMSR_SMSR_MASK)
-
-#define MRR_ADDRESS 0x0000003c
-#define MRR_OFFSET 0x0000003c
-#define MRR_MRR_MSB 31
-#define MRR_MRR_LSB 0
-#define MRR_MRR_MASK 0xffffffff
-#define MRR_MRR_GET(x) (((x) & MRR_MRR_MASK) >> MRR_MRR_LSB)
-#define MRR_MRR_SET(x) (((x) << MRR_MRR_LSB) & MRR_MRR_MASK)
-
-
-#ifndef __ASSEMBLER__
-
-typedef struct uart_reg_reg_s {
- volatile unsigned int rbr;
- volatile unsigned int dlh;
- volatile unsigned int iir;
- volatile unsigned int lcr;
- volatile unsigned int mcr;
- volatile unsigned int lsr;
- volatile unsigned int msr;
- volatile unsigned int scr;
- volatile unsigned int srbr;
- unsigned char pad0[4]; /* pad to 0x28 */
- volatile unsigned int siir;
- volatile unsigned int mwr;
- unsigned char pad1[4]; /* pad to 0x34 */
- volatile unsigned int slsr;
- volatile unsigned int smsr;
- volatile unsigned int mrr;
-} uart_reg_reg_t;
-
-#endif /* __ASSEMBLER__ */
-
-#endif /* _UART_REG_H_ */
diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw2.0/hw/vmc_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw2.0/hw/vmc_reg.h
deleted file mode 100644
index 932ec51..0000000
--- a/drivers/staging/ath6kl/include/common/AR6002/hw2.0/hw/vmc_reg.h
+++ /dev/null
@@ -1,76 +0,0 @@
-#ifndef _VMC_REG_REG_H_
-#define _VMC_REG_REG_H_
-
-#define MC_TCAM_VALID_ADDRESS 0x00000000
-#define MC_TCAM_VALID_OFFSET 0x00000000
-#define MC_TCAM_VALID_BIT_MSB 0
-#define MC_TCAM_VALID_BIT_LSB 0
-#define MC_TCAM_VALID_BIT_MASK 0x00000001
-#define MC_TCAM_VALID_BIT_GET(x) (((x) & MC_TCAM_VALID_BIT_MASK) >> MC_TCAM_VALID_BIT_LSB)
-#define MC_TCAM_VALID_BIT_SET(x) (((x) << MC_TCAM_VALID_BIT_LSB) & MC_TCAM_VALID_BIT_MASK)
-
-#define MC_TCAM_MASK_ADDRESS 0x00000080
-#define MC_TCAM_MASK_OFFSET 0x00000080
-#define MC_TCAM_MASK_SIZE_MSB 2
-#define MC_TCAM_MASK_SIZE_LSB 0
-#define MC_TCAM_MASK_SIZE_MASK 0x00000007
-#define MC_TCAM_MASK_SIZE_GET(x) (((x) & MC_TCAM_MASK_SIZE_MASK) >> MC_TCAM_MASK_SIZE_LSB)
-#define MC_TCAM_MASK_SIZE_SET(x) (((x) << MC_TCAM_MASK_SIZE_LSB) & MC_TCAM_MASK_SIZE_MASK)
-
-#define MC_TCAM_COMPARE_ADDRESS 0x00000100
-#define MC_TCAM_COMPARE_OFFSET 0x00000100
-#define MC_TCAM_COMPARE_KEY_MSB 21
-#define MC_TCAM_COMPARE_KEY_LSB 5
-#define MC_TCAM_COMPARE_KEY_MASK 0x003fffe0
-#define MC_TCAM_COMPARE_KEY_GET(x) (((x) & MC_TCAM_COMPARE_KEY_MASK) >> MC_TCAM_COMPARE_KEY_LSB)
-#define MC_TCAM_COMPARE_KEY_SET(x) (((x) << MC_TCAM_COMPARE_KEY_LSB) & MC_TCAM_COMPARE_KEY_MASK)
-
-#define MC_TCAM_TARGET_ADDRESS 0x00000180
-#define MC_TCAM_TARGET_OFFSET 0x00000180
-#define MC_TCAM_TARGET_ADDR_MSB 21
-#define MC_TCAM_TARGET_ADDR_LSB 5
-#define MC_TCAM_TARGET_ADDR_MASK 0x003fffe0
-#define MC_TCAM_TARGET_ADDR_GET(x) (((x) & MC_TCAM_TARGET_ADDR_MASK) >> MC_TCAM_TARGET_ADDR_LSB)
-#define MC_TCAM_TARGET_ADDR_SET(x) (((x) << MC_TCAM_TARGET_ADDR_LSB) & MC_TCAM_TARGET_ADDR_MASK)
-
-#define ADDR_ERROR_CONTROL_ADDRESS 0x00000200
-#define ADDR_ERROR_CONTROL_OFFSET 0x00000200
-#define ADDR_ERROR_CONTROL_QUAL_ENABLE_MSB 1
-#define ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB 1
-#define ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK 0x00000002
-#define ADDR_ERROR_CONTROL_QUAL_ENABLE_GET(x) (((x) & ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK) >> ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB)
-#define ADDR_ERROR_CONTROL_QUAL_ENABLE_SET(x) (((x) << ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB) & ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK)
-#define ADDR_ERROR_CONTROL_ENABLE_MSB 0
-#define ADDR_ERROR_CONTROL_ENABLE_LSB 0
-#define ADDR_ERROR_CONTROL_ENABLE_MASK 0x00000001
-#define ADDR_ERROR_CONTROL_ENABLE_GET(x) (((x) & ADDR_ERROR_CONTROL_ENABLE_MASK) >> ADDR_ERROR_CONTROL_ENABLE_LSB)
-#define ADDR_ERROR_CONTROL_ENABLE_SET(x) (((x) << ADDR_ERROR_CONTROL_ENABLE_LSB) & ADDR_ERROR_CONTROL_ENABLE_MASK)
-
-#define ADDR_ERROR_STATUS_ADDRESS 0x00000204
-#define ADDR_ERROR_STATUS_OFFSET 0x00000204
-#define ADDR_ERROR_STATUS_WRITE_MSB 25
-#define ADDR_ERROR_STATUS_WRITE_LSB 25
-#define ADDR_ERROR_STATUS_WRITE_MASK 0x02000000
-#define ADDR_ERROR_STATUS_WRITE_GET(x) (((x) & ADDR_ERROR_STATUS_WRITE_MASK) >> ADDR_ERROR_STATUS_WRITE_LSB)
-#define ADDR_ERROR_STATUS_WRITE_SET(x) (((x) << ADDR_ERROR_STATUS_WRITE_LSB) & ADDR_ERROR_STATUS_WRITE_MASK)
-#define ADDR_ERROR_STATUS_ADDRESS_MSB 24
-#define ADDR_ERROR_STATUS_ADDRESS_LSB 0
-#define ADDR_ERROR_STATUS_ADDRESS_MASK 0x01ffffff
-#define ADDR_ERROR_STATUS_ADDRESS_GET(x) (((x) & ADDR_ERROR_STATUS_ADDRESS_MASK) >> ADDR_ERROR_STATUS_ADDRESS_LSB)
-#define ADDR_ERROR_STATUS_ADDRESS_SET(x) (((x) << ADDR_ERROR_STATUS_ADDRESS_LSB) & ADDR_ERROR_STATUS_ADDRESS_MASK)
-
-
-#ifndef __ASSEMBLER__
-
-typedef struct vmc_reg_reg_s {
- volatile unsigned int mc_tcam_valid[32];
- volatile unsigned int mc_tcam_mask[32];
- volatile unsigned int mc_tcam_compare[32];
- volatile unsigned int mc_tcam_target[32];
- volatile unsigned int addr_error_control;
- volatile unsigned int addr_error_status;
-} vmc_reg_reg_t;
-
-#endif /* __ASSEMBLER__ */
-
-#endif /* _VMC_REG_H_ */
diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/analog_intf_ares_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/analog_intf_ares_reg.h
deleted file mode 100644
index 5970fa9..0000000
--- a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/analog_intf_ares_reg.h
+++ /dev/null
@@ -1,3291 +0,0 @@
-// ------------------------------------------------------------------
-// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
-//
-//
-// Permission to use, copy, modify, and/or distribute this software for any
-// purpose with or without fee is hereby granted, provided that the above
-// copyright notice and this permission notice appear in all copies.
-//
-// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-//
-//
-// ------------------------------------------------------------------
-//===================================================================
-// Author(s): ="Atheros"
-//===================================================================
-
-/* Copyright (C) 2009 Denali Software Inc. All rights reserved */
-/* THIS FILE IS AUTOMATICALLY GENERATED BY DENALI BLUEPRINT, DO NOT EDIT */
-
-
-#ifndef _ANALOG_INTF_ARES_REG_REG_H_
-#define _ANALOG_INTF_ARES_REG_REG_H_
-
-
-/* macros for RXRF_BIAS1 */
-#define PHY_ANALOG_RXRF_BIAS1_ADDRESS 0x00000000
-#define PHY_ANALOG_RXRF_BIAS1_OFFSET 0x00000000
-#define PHY_ANALOG_RXRF_BIAS1_SPARE_MSB 0
-#define PHY_ANALOG_RXRF_BIAS1_SPARE_LSB 0
-#define PHY_ANALOG_RXRF_BIAS1_SPARE_MASK 0x00000001
-#define PHY_ANALOG_RXRF_BIAS1_SPARE_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_ANALOG_RXRF_BIAS1_SPARE_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_MSB 3
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_LSB 1
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_MASK 0x0000000e
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_GET(x) (((x) & 0x0000000e) >> 1)
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_SET(x) (((x) << 1) & 0x0000000e)
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_MSB 6
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_LSB 4
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_MASK 0x00000070
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_GET(x) (((x) & 0x00000070) >> 4)
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_SET(x) (((x) << 4) & 0x00000070)
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_MSB 9
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_LSB 7
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_MASK 0x00000380
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_GET(x) (((x) & 0x00000380) >> 7)
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_SET(x) (((x) << 7) & 0x00000380)
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_MSB 12
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_LSB 10
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_MASK 0x00001c00
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_GET(x) (((x) & 0x00001c00) >> 10)
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_SET(x) (((x) << 10) & 0x00001c00)
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_MSB 15
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_LSB 13
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_MASK 0x0000e000
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_GET(x) (((x) & 0x0000e000) >> 13)
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_SET(x) (((x) << 13) & 0x0000e000)
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_MSB 18
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_LSB 16
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_MASK 0x00070000
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_GET(x) (((x) & 0x00070000) >> 16)
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_SET(x) (((x) << 16) & 0x00070000)
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_MSB 21
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_LSB 19
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_MASK 0x00380000
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_GET(x) (((x) & 0x00380000) >> 19)
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_SET(x) (((x) << 19) & 0x00380000)
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_MSB 24
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_LSB 22
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_MASK 0x01c00000
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_GET(x) (((x) & 0x01c00000) >> 22)
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_SET(x) (((x) << 22) & 0x01c00000)
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_MSB 27
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_LSB 25
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_MASK 0x0e000000
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_GET(x) (((x) & 0x0e000000) >> 25)
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_SET(x) (((x) << 25) & 0x0e000000)
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_MSB 30
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_LSB 28
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_MASK 0x70000000
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_GET(x) (((x) & 0x70000000) >> 28)
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_SET(x) (((x) << 28) & 0x70000000)
-#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_MSB 31
-#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_LSB 31
-#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_MASK 0x80000000
-#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_GET(x) (((x) & 0x80000000) >> 31)
-#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_SET(x) (((x) << 31) & 0x80000000)
-
-/* macros for RXRF_BIAS2 */
-#define PHY_ANALOG_RXRF_BIAS2_ADDRESS 0x00000004
-#define PHY_ANALOG_RXRF_BIAS2_OFFSET 0x00000004
-#define PHY_ANALOG_RXRF_BIAS2_SPARE_MSB 0
-#define PHY_ANALOG_RXRF_BIAS2_SPARE_LSB 0
-#define PHY_ANALOG_RXRF_BIAS2_SPARE_MASK 0x00000001
-#define PHY_ANALOG_RXRF_BIAS2_SPARE_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_ANALOG_RXRF_BIAS2_SPARE_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_ANALOG_RXRF_BIAS2_PKEN_MSB 3
-#define PHY_ANALOG_RXRF_BIAS2_PKEN_LSB 1
-#define PHY_ANALOG_RXRF_BIAS2_PKEN_MASK 0x0000000e
-#define PHY_ANALOG_RXRF_BIAS2_PKEN_GET(x) (((x) & 0x0000000e) >> 1)
-#define PHY_ANALOG_RXRF_BIAS2_PKEN_SET(x) (((x) << 1) & 0x0000000e)
-#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_MSB 6
-#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_LSB 4
-#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_MASK 0x00000070
-#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_GET(x) (((x) & 0x00000070) >> 4)
-#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_SET(x) (((x) << 4) & 0x00000070)
-#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_MSB 7
-#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_LSB 7
-#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_MASK 0x00000080
-#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_GET(x) (((x) & 0x00000080) >> 7)
-#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_SET(x) (((x) << 7) & 0x00000080)
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5GH_MSB 10
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5GH_LSB 8
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5GH_MASK 0x00000700
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5GH_GET(x) (((x) & 0x00000700) >> 8)
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5GH_SET(x) (((x) << 8) & 0x00000700)
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5G_MSB 13
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5G_LSB 11
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5G_MASK 0x00003800
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5G_GET(x) (((x) & 0x00003800) >> 11)
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC5G_SET(x) (((x) << 11) & 0x00003800)
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC5G_MSB 16
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC5G_LSB 14
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC5G_MASK 0x0001c000
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC5G_GET(x) (((x) & 0x0001c000) >> 14)
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC5G_SET(x) (((x) << 14) & 0x0001c000)
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2GH_MSB 19
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2GH_LSB 17
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2GH_MASK 0x000e0000
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2GH_GET(x) (((x) & 0x000e0000) >> 17)
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2GH_SET(x) (((x) << 17) & 0x000e0000)
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2G_MSB 22
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2G_LSB 20
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2G_MASK 0x00700000
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2G_GET(x) (((x) & 0x00700000) >> 20)
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC2G_SET(x) (((x) << 20) & 0x00700000)
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC2G_MSB 25
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC2G_LSB 23
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC2G_MASK 0x03800000
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC2G_GET(x) (((x) & 0x03800000) >> 23)
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC2G_SET(x) (((x) << 23) & 0x03800000)
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_MSB 28
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_LSB 26
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_MASK 0x1c000000
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_GET(x) (((x) & 0x1c000000) >> 26)
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_SET(x) (((x) << 26) & 0x1c000000)
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_MSB 31
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_LSB 29
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_MASK 0xe0000000
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_GET(x) (((x) & 0xe0000000) >> 29)
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_SET(x) (((x) << 29) & 0xe0000000)
-
-/* macros for RXRF_GAINSTAGES */
-#define PHY_ANALOG_RXRF_GAINSTAGES_ADDRESS 0x00000008
-#define PHY_ANALOG_RXRF_GAINSTAGES_OFFSET 0x00000008
-#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_MSB 0
-#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_LSB 0
-#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_MASK 0x00000001
-#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_MSB 1
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_LSB 1
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_MASK 0x00000002
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_GET(x) (((x) & 0x00000002) >> 1)
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_SET(x) (((x) << 1) & 0x00000002)
-#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_MSB 3
-#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_LSB 2
-#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_MASK 0x0000000c
-#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_GET(x) (((x) & 0x0000000c) >> 2)
-#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_SET(x) (((x) << 2) & 0x0000000c)
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_MSB 5
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_LSB 4
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_MASK 0x00000030
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_GET(x) (((x) & 0x00000030) >> 4)
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_SET(x) (((x) << 4) & 0x00000030)
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_MSB 6
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_LSB 6
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_MASK 0x00000040
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_GET(x) (((x) & 0x00000040) >> 6)
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_SET(x) (((x) << 6) & 0x00000040)
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_MSB 7
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_LSB 7
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_MASK 0x00000080
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_GET(x) (((x) & 0x00000080) >> 7)
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_SET(x) (((x) << 7) & 0x00000080)
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_MSB 8
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_LSB 8
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_MASK 0x00000100
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_GET(x) (((x) & 0x00000100) >> 8)
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_SET(x) (((x) << 8) & 0x00000100)
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_MSB 9
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_LSB 9
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_MASK 0x00000200
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_GET(x) (((x) & 0x00000200) >> 9)
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_SET(x) (((x) << 9) & 0x00000200)
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_MSB 10
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_LSB 10
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_MASK 0x00000400
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_GET(x) (((x) & 0x00000400) >> 10)
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_SET(x) (((x) << 10) & 0x00000400)
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_MSB 12
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_LSB 11
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_MASK 0x00001800
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_GET(x) (((x) & 0x00001800) >> 11)
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_SET(x) (((x) << 11) & 0x00001800)
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_MSB 13
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_LSB 13
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_MASK 0x00002000
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_GET(x) (((x) & 0x00002000) >> 13)
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_SET(x) (((x) << 13) & 0x00002000)
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_MSB 14
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_LSB 14
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_MASK 0x00004000
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_GET(x) (((x) & 0x00004000) >> 14)
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_SET(x) (((x) << 14) & 0x00004000)
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_MSB 15
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_LSB 15
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_MASK 0x00008000
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_GET(x) (((x) & 0x00008000) >> 15)
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_SET(x) (((x) << 15) & 0x00008000)
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_MSB 16
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_LSB 16
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_MASK 0x00010000
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_GET(x) (((x) & 0x00010000) >> 16)
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_SET(x) (((x) << 16) & 0x00010000)
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_MSB 17
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_LSB 17
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_MASK 0x00020000
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_GET(x) (((x) & 0x00020000) >> 17)
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_SET(x) (((x) << 17) & 0x00020000)
-#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_MSB 19
-#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_LSB 18
-#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_MASK 0x000c0000
-#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_GET(x) (((x) & 0x000c0000) >> 18)
-#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_SET(x) (((x) << 18) & 0x000c0000)
-#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_MSB 22
-#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_LSB 20
-#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_MASK 0x00700000
-#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_GET(x) (((x) & 0x00700000) >> 20)
-#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_SET(x) (((x) << 20) & 0x00700000)
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_MSB 25
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_LSB 23
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_MASK 0x03800000
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_GET(x) (((x) & 0x03800000) >> 23)
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_SET(x) (((x) << 23) & 0x03800000)
-#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_MSB 27
-#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_LSB 26
-#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_MASK 0x0c000000
-#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_GET(x) (((x) & 0x0c000000) >> 26)
-#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_SET(x) (((x) << 26) & 0x0c000000)
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_MSB 30
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_LSB 28
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_MASK 0x70000000
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_GET(x) (((x) & 0x70000000) >> 28)
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_SET(x) (((x) << 28) & 0x70000000)
-#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_MSB 31
-#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_LSB 31
-#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_MASK 0x80000000
-#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_GET(x) (((x) & 0x80000000) >> 31)
-#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_SET(x) (((x) << 31) & 0x80000000)
-
-/* macros for RXRF_AGC */
-#define PHY_ANALOG_RXRF_AGC_ADDRESS 0x0000000c
-#define PHY_ANALOG_RXRF_AGC_OFFSET 0x0000000c
-#define PHY_ANALOG_RXRF_AGC_SPARE_MSB 5
-#define PHY_ANALOG_RXRF_AGC_SPARE_LSB 0
-#define PHY_ANALOG_RXRF_AGC_SPARE_MASK 0x0000003f
-#define PHY_ANALOG_RXRF_AGC_SPARE_GET(x) (((x) & 0x0000003f) >> 0)
-#define PHY_ANALOG_RXRF_AGC_SPARE_SET(x) (((x) << 0) & 0x0000003f)
-#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_MSB 8
-#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_LSB 6
-#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_MASK 0x000001c0
-#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_GET(x) (((x) & 0x000001c0) >> 6)
-#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_SET(x) (((x) << 6) & 0x000001c0)
-#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_MSB 14
-#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_LSB 9
-#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_MASK 0x00007e00
-#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_GET(x) (((x) & 0x00007e00) >> 9)
-#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_SET(x) (((x) << 9) & 0x00007e00)
-#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_MSB 18
-#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_LSB 15
-#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_MASK 0x00078000
-#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_GET(x) (((x) & 0x00078000) >> 15)
-#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_SET(x) (((x) << 15) & 0x00078000)
-#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_MSB 24
-#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_LSB 19
-#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_MASK 0x01f80000
-#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_GET(x) (((x) & 0x01f80000) >> 19)
-#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_SET(x) (((x) << 19) & 0x01f80000)
-#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_MSB 28
-#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_LSB 25
-#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_MASK 0x1e000000
-#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_GET(x) (((x) & 0x1e000000) >> 25)
-#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_SET(x) (((x) << 25) & 0x1e000000)
-#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_MSB 29
-#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_LSB 29
-#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_MASK 0x20000000
-#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_GET(x) (((x) & 0x20000000) >> 29)
-#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_SET(x) (((x) << 29) & 0x20000000)
-#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_MSB 30
-#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_LSB 30
-#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_MASK 0x40000000
-#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_GET(x) (((x) & 0x40000000) >> 30)
-#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_SET(x) (((x) << 30) & 0x40000000)
-#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_MSB 31
-#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_LSB 31
-#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_MASK 0x80000000
-#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_GET(x) (((x) & 0x80000000) >> 31)
-#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_SET(x) (((x) << 31) & 0x80000000)
-
-/* macros for TXRF1 */
-#define PHY_ANALOG_TXRF1_ADDRESS 0x00000040
-#define PHY_ANALOG_TXRF1_OFFSET 0x00000040
-#define PHY_ANALOG_TXRF1_DCAS2G_MSB 2
-#define PHY_ANALOG_TXRF1_DCAS2G_LSB 0
-#define PHY_ANALOG_TXRF1_DCAS2G_MASK 0x00000007
-#define PHY_ANALOG_TXRF1_DCAS2G_GET(x) (((x) & 0x00000007) >> 0)
-#define PHY_ANALOG_TXRF1_DCAS2G_SET(x) (((x) << 0) & 0x00000007)
-#define PHY_ANALOG_TXRF1_OB2G_PALOFF_MSB 5
-#define PHY_ANALOG_TXRF1_OB2G_PALOFF_LSB 3
-#define PHY_ANALOG_TXRF1_OB2G_PALOFF_MASK 0x00000038
-#define PHY_ANALOG_TXRF1_OB2G_PALOFF_GET(x) (((x) & 0x00000038) >> 3)
-#define PHY_ANALOG_TXRF1_OB2G_PALOFF_SET(x) (((x) << 3) & 0x00000038)
-#define PHY_ANALOG_TXRF1_OB2G_QAM_MSB 8
-#define PHY_ANALOG_TXRF1_OB2G_QAM_LSB 6
-#define PHY_ANALOG_TXRF1_OB2G_QAM_MASK 0x000001c0
-#define PHY_ANALOG_TXRF1_OB2G_QAM_GET(x) (((x) & 0x000001c0) >> 6)
-#define PHY_ANALOG_TXRF1_OB2G_QAM_SET(x) (((x) << 6) & 0x000001c0)
-#define PHY_ANALOG_TXRF1_OB2G_PSK_MSB 11
-#define PHY_ANALOG_TXRF1_OB2G_PSK_LSB 9
-#define PHY_ANALOG_TXRF1_OB2G_PSK_MASK 0x00000e00
-#define PHY_ANALOG_TXRF1_OB2G_PSK_GET(x) (((x) & 0x00000e00) >> 9)
-#define PHY_ANALOG_TXRF1_OB2G_PSK_SET(x) (((x) << 9) & 0x00000e00)
-#define PHY_ANALOG_TXRF1_OB2G_CCK_MSB 14
-#define PHY_ANALOG_TXRF1_OB2G_CCK_LSB 12
-#define PHY_ANALOG_TXRF1_OB2G_CCK_MASK 0x00007000
-#define PHY_ANALOG_TXRF1_OB2G_CCK_GET(x) (((x) & 0x00007000) >> 12)
-#define PHY_ANALOG_TXRF1_OB2G_CCK_SET(x) (((x) << 12) & 0x00007000)
-#define PHY_ANALOG_TXRF1_DB2G_MSB 17
-#define PHY_ANALOG_TXRF1_DB2G_LSB 15
-#define PHY_ANALOG_TXRF1_DB2G_MASK 0x00038000
-#define PHY_ANALOG_TXRF1_DB2G_GET(x) (((x) & 0x00038000) >> 15)
-#define PHY_ANALOG_TXRF1_DB2G_SET(x) (((x) << 15) & 0x00038000)
-#define PHY_ANALOG_TXRF1_PDOUT2G_MSB 18
-#define PHY_ANALOG_TXRF1_PDOUT2G_LSB 18
-#define PHY_ANALOG_TXRF1_PDOUT2G_MASK 0x00040000
-#define PHY_ANALOG_TXRF1_PDOUT2G_GET(x) (((x) & 0x00040000) >> 18)
-#define PHY_ANALOG_TXRF1_PDOUT2G_SET(x) (((x) << 18) & 0x00040000)
-#define PHY_ANALOG_TXRF1_PDDR2G_MSB 19
-#define PHY_ANALOG_TXRF1_PDDR2G_LSB 19
-#define PHY_ANALOG_TXRF1_PDDR2G_MASK 0x00080000
-#define PHY_ANALOG_TXRF1_PDDR2G_GET(x) (((x) & 0x00080000) >> 19)
-#define PHY_ANALOG_TXRF1_PDDR2G_SET(x) (((x) << 19) & 0x00080000)
-#define PHY_ANALOG_TXRF1_PDMXR2G_MSB 20
-#define PHY_ANALOG_TXRF1_PDMXR2G_LSB 20
-#define PHY_ANALOG_TXRF1_PDMXR2G_MASK 0x00100000
-#define PHY_ANALOG_TXRF1_PDMXR2G_GET(x) (((x) & 0x00100000) >> 20)
-#define PHY_ANALOG_TXRF1_PDMXR2G_SET(x) (((x) << 20) & 0x00100000)
-#define PHY_ANALOG_TXRF1_PDLO2G_MSB 21
-#define PHY_ANALOG_TXRF1_PDLO2G_LSB 21
-#define PHY_ANALOG_TXRF1_PDLO2G_MASK 0x00200000
-#define PHY_ANALOG_TXRF1_PDLO2G_GET(x) (((x) & 0x00200000) >> 21)
-#define PHY_ANALOG_TXRF1_PDLO2G_SET(x) (((x) << 21) & 0x00200000)
-#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_MSB 22
-#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_LSB 22
-#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_MASK 0x00400000
-#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_GET(x) (((x) & 0x00400000) >> 22)
-#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_SET(x) (((x) << 22) & 0x00400000)
-#define PHY_ANALOG_TXRF1_LODIV2GFORCED_MSB 23
-#define PHY_ANALOG_TXRF1_LODIV2GFORCED_LSB 23
-#define PHY_ANALOG_TXRF1_LODIV2GFORCED_MASK 0x00800000
-#define PHY_ANALOG_TXRF1_LODIV2GFORCED_GET(x) (((x) & 0x00800000) >> 23)
-#define PHY_ANALOG_TXRF1_LODIV2GFORCED_SET(x) (((x) << 23) & 0x00800000)
-#define PHY_ANALOG_TXRF1_PADRVGN2G_MSB 30
-#define PHY_ANALOG_TXRF1_PADRVGN2G_LSB 24
-#define PHY_ANALOG_TXRF1_PADRVGN2G_MASK 0x7f000000
-#define PHY_ANALOG_TXRF1_PADRVGN2G_GET(x) (((x) & 0x7f000000) >> 24)
-#define PHY_ANALOG_TXRF1_PADRVGN2G_SET(x) (((x) << 24) & 0x7f000000)
-#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_MSB 31
-#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_LSB 31
-#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_MASK 0x80000000
-#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_GET(x) (((x) & 0x80000000) >> 31)
-#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_SET(x) (((x) << 31) & 0x80000000)
-
-/* macros for TXRF2 */
-#define PHY_ANALOG_TXRF2_ADDRESS 0x00000044
-#define PHY_ANALOG_TXRF2_OFFSET 0x00000044
-#define PHY_ANALOG_TXRF2_SPARE2_MSB 0
-#define PHY_ANALOG_TXRF2_SPARE2_LSB 0
-#define PHY_ANALOG_TXRF2_SPARE2_MASK 0x00000001
-#define PHY_ANALOG_TXRF2_SPARE2_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_ANALOG_TXRF2_SPARE2_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_ANALOG_TXRF2_D3B5G_MSB 3
-#define PHY_ANALOG_TXRF2_D3B5G_LSB 1
-#define PHY_ANALOG_TXRF2_D3B5G_MASK 0x0000000e
-#define PHY_ANALOG_TXRF2_D3B5G_GET(x) (((x) & 0x0000000e) >> 1)
-#define PHY_ANALOG_TXRF2_D3B5G_SET(x) (((x) << 1) & 0x0000000e)
-#define PHY_ANALOG_TXRF2_D4B5G_MSB 6
-#define PHY_ANALOG_TXRF2_D4B5G_LSB 4
-#define PHY_ANALOG_TXRF2_D4B5G_MASK 0x00000070
-#define PHY_ANALOG_TXRF2_D4B5G_GET(x) (((x) & 0x00000070) >> 4)
-#define PHY_ANALOG_TXRF2_D4B5G_SET(x) (((x) << 4) & 0x00000070)
-#define PHY_ANALOG_TXRF2_PDOUT5G_MSB 10
-#define PHY_ANALOG_TXRF2_PDOUT5G_LSB 7
-#define PHY_ANALOG_TXRF2_PDOUT5G_MASK 0x00000780
-#define PHY_ANALOG_TXRF2_PDOUT5G_GET(x) (((x) & 0x00000780) >> 7)
-#define PHY_ANALOG_TXRF2_PDOUT5G_SET(x) (((x) << 7) & 0x00000780)
-#define PHY_ANALOG_TXRF2_PDMXR5G_MSB 11
-#define PHY_ANALOG_TXRF2_PDMXR5G_LSB 11
-#define PHY_ANALOG_TXRF2_PDMXR5G_MASK 0x00000800
-#define PHY_ANALOG_TXRF2_PDMXR5G_GET(x) (((x) & 0x00000800) >> 11)
-#define PHY_ANALOG_TXRF2_PDMXR5G_SET(x) (((x) << 11) & 0x00000800)
-#define PHY_ANALOG_TXRF2_PDLOBUF5G_MSB 12
-#define PHY_ANALOG_TXRF2_PDLOBUF5G_LSB 12
-#define PHY_ANALOG_TXRF2_PDLOBUF5G_MASK 0x00001000
-#define PHY_ANALOG_TXRF2_PDLOBUF5G_GET(x) (((x) & 0x00001000) >> 12)
-#define PHY_ANALOG_TXRF2_PDLOBUF5G_SET(x) (((x) << 12) & 0x00001000)
-#define PHY_ANALOG_TXRF2_PDLODIV5G_MSB 13
-#define PHY_ANALOG_TXRF2_PDLODIV5G_LSB 13
-#define PHY_ANALOG_TXRF2_PDLODIV5G_MASK 0x00002000
-#define PHY_ANALOG_TXRF2_PDLODIV5G_GET(x) (((x) & 0x00002000) >> 13)
-#define PHY_ANALOG_TXRF2_PDLODIV5G_SET(x) (((x) << 13) & 0x00002000)
-#define PHY_ANALOG_TXRF2_LOBUF5GFORCED_MSB 14
-#define PHY_ANALOG_TXRF2_LOBUF5GFORCED_LSB 14
-#define PHY_ANALOG_TXRF2_LOBUF5GFORCED_MASK 0x00004000
-#define PHY_ANALOG_TXRF2_LOBUF5GFORCED_GET(x) (((x) & 0x00004000) >> 14)
-#define PHY_ANALOG_TXRF2_LOBUF5GFORCED_SET(x) (((x) << 14) & 0x00004000)
-#define PHY_ANALOG_TXRF2_LODIV5GFORCED_MSB 15
-#define PHY_ANALOG_TXRF2_LODIV5GFORCED_LSB 15
-#define PHY_ANALOG_TXRF2_LODIV5GFORCED_MASK 0x00008000
-#define PHY_ANALOG_TXRF2_LODIV5GFORCED_GET(x) (((x) & 0x00008000) >> 15)
-#define PHY_ANALOG_TXRF2_LODIV5GFORCED_SET(x) (((x) << 15) & 0x00008000)
-#define PHY_ANALOG_TXRF2_PADRV2GN5G_MSB 19
-#define PHY_ANALOG_TXRF2_PADRV2GN5G_LSB 16
-#define PHY_ANALOG_TXRF2_PADRV2GN5G_MASK 0x000f0000
-#define PHY_ANALOG_TXRF2_PADRV2GN5G_GET(x) (((x) & 0x000f0000) >> 16)
-#define PHY_ANALOG_TXRF2_PADRV2GN5G_SET(x) (((x) << 16) & 0x000f0000)
-#define PHY_ANALOG_TXRF2_PADRV3GN5G_MSB 23
-#define PHY_ANALOG_TXRF2_PADRV3GN5G_LSB 20
-#define PHY_ANALOG_TXRF2_PADRV3GN5G_MASK 0x00f00000
-#define PHY_ANALOG_TXRF2_PADRV3GN5G_GET(x) (((x) & 0x00f00000) >> 20)
-#define PHY_ANALOG_TXRF2_PADRV3GN5G_SET(x) (((x) << 20) & 0x00f00000)
-#define PHY_ANALOG_TXRF2_PADRV4GN5G_MSB 27
-#define PHY_ANALOG_TXRF2_PADRV4GN5G_LSB 24
-#define PHY_ANALOG_TXRF2_PADRV4GN5G_MASK 0x0f000000
-#define PHY_ANALOG_TXRF2_PADRV4GN5G_GET(x) (((x) & 0x0f000000) >> 24)
-#define PHY_ANALOG_TXRF2_PADRV4GN5G_SET(x) (((x) << 24) & 0x0f000000)
-#define PHY_ANALOG_TXRF2_LOCALTXGAIN5G_MSB 28
-#define PHY_ANALOG_TXRF2_LOCALTXGAIN5G_LSB 28
-#define PHY_ANALOG_TXRF2_LOCALTXGAIN5G_MASK 0x10000000
-#define PHY_ANALOG_TXRF2_LOCALTXGAIN5G_GET(x) (((x) & 0x10000000) >> 28)
-#define PHY_ANALOG_TXRF2_LOCALTXGAIN5G_SET(x) (((x) << 28) & 0x10000000)
-#define PHY_ANALOG_TXRF2_OCAS2G_MSB 31
-#define PHY_ANALOG_TXRF2_OCAS2G_LSB 29
-#define PHY_ANALOG_TXRF2_OCAS2G_MASK 0xe0000000
-#define PHY_ANALOG_TXRF2_OCAS2G_GET(x) (((x) & 0xe0000000) >> 29)
-#define PHY_ANALOG_TXRF2_OCAS2G_SET(x) (((x) << 29) & 0xe0000000)
-
-/* macros for TXRF3 */
-#define PHY_ANALOG_TXRF3_ADDRESS 0x00000048
-#define PHY_ANALOG_TXRF3_OFFSET 0x00000048
-#define PHY_ANALOG_TXRF3_SPARE3_MSB 22
-#define PHY_ANALOG_TXRF3_SPARE3_LSB 0
-#define PHY_ANALOG_TXRF3_SPARE3_MASK 0x007fffff
-#define PHY_ANALOG_TXRF3_SPARE3_GET(x) (((x) & 0x007fffff) >> 0)
-#define PHY_ANALOG_TXRF3_SPARE3_SET(x) (((x) << 0) & 0x007fffff)
-#define PHY_ANALOG_TXRF3_CAS5G_MSB 25
-#define PHY_ANALOG_TXRF3_CAS5G_LSB 23
-#define PHY_ANALOG_TXRF3_CAS5G_MASK 0x03800000
-#define PHY_ANALOG_TXRF3_CAS5G_GET(x) (((x) & 0x03800000) >> 23)
-#define PHY_ANALOG_TXRF3_CAS5G_SET(x) (((x) << 23) & 0x03800000)
-#define PHY_ANALOG_TXRF3_OB5G_MSB 28
-#define PHY_ANALOG_TXRF3_OB5G_LSB 26
-#define PHY_ANALOG_TXRF3_OB5G_MASK 0x1c000000
-#define PHY_ANALOG_TXRF3_OB5G_GET(x) (((x) & 0x1c000000) >> 26)
-#define PHY_ANALOG_TXRF3_OB5G_SET(x) (((x) << 26) & 0x1c000000)
-#define PHY_ANALOG_TXRF3_D2B5G_MSB 31
-#define PHY_ANALOG_TXRF3_D2B5G_LSB 29
-#define PHY_ANALOG_TXRF3_D2B5G_MASK 0xe0000000
-#define PHY_ANALOG_TXRF3_D2B5G_GET(x) (((x) & 0xe0000000) >> 29)
-#define PHY_ANALOG_TXRF3_D2B5G_SET(x) (((x) << 29) & 0xe0000000)
-
-/* macros for TXRF4 */
-#define PHY_ANALOG_TXRF4_ADDRESS 0x0000004c
-#define PHY_ANALOG_TXRF4_OFFSET 0x0000004c
-#define PHY_ANALOG_TXRF4_COMP2G_PSK_MSB 2
-#define PHY_ANALOG_TXRF4_COMP2G_PSK_LSB 0
-#define PHY_ANALOG_TXRF4_COMP2G_PSK_MASK 0x00000007
-#define PHY_ANALOG_TXRF4_COMP2G_PSK_GET(x) (((x) & 0x00000007) >> 0)
-#define PHY_ANALOG_TXRF4_COMP2G_PSK_SET(x) (((x) << 0) & 0x00000007)
-#define PHY_ANALOG_TXRF4_COMP2G_CCK_MSB 5
-#define PHY_ANALOG_TXRF4_COMP2G_CCK_LSB 3
-#define PHY_ANALOG_TXRF4_COMP2G_CCK_MASK 0x00000038
-#define PHY_ANALOG_TXRF4_COMP2G_CCK_GET(x) (((x) & 0x00000038) >> 3)
-#define PHY_ANALOG_TXRF4_COMP2G_CCK_SET(x) (((x) << 3) & 0x00000038)
-#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_MSB 8
-#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_LSB 6
-#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_MASK 0x000001c0
-#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_GET(x) (((x) & 0x000001c0) >> 6)
-#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_SET(x) (((x) << 6) & 0x000001c0)
-#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_MSB 11
-#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_LSB 9
-#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_MASK 0x00000e00
-#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_GET(x) (((x) & 0x00000e00) >> 9)
-#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_SET(x) (((x) << 9) & 0x00000e00)
-#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_MSB 14
-#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_LSB 12
-#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_MASK 0x00007000
-#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_GET(x) (((x) & 0x00007000) >> 12)
-#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_SET(x) (((x) << 12) & 0x00007000)
-#define PHY_ANALOG_TXRF4_AMP2CAS2G_MSB 17
-#define PHY_ANALOG_TXRF4_AMP2CAS2G_LSB 15
-#define PHY_ANALOG_TXRF4_AMP2CAS2G_MASK 0x00038000
-#define PHY_ANALOG_TXRF4_AMP2CAS2G_GET(x) (((x) & 0x00038000) >> 15)
-#define PHY_ANALOG_TXRF4_AMP2CAS2G_SET(x) (((x) << 15) & 0x00038000)
-#define PHY_ANALOG_TXRF4_FILTR2G_MSB 19
-#define PHY_ANALOG_TXRF4_FILTR2G_LSB 18
-#define PHY_ANALOG_TXRF4_FILTR2G_MASK 0x000c0000
-#define PHY_ANALOG_TXRF4_FILTR2G_GET(x) (((x) & 0x000c0000) >> 18)
-#define PHY_ANALOG_TXRF4_FILTR2G_SET(x) (((x) << 18) & 0x000c0000)
-#define PHY_ANALOG_TXRF4_PWDFB2_2G_MSB 20
-#define PHY_ANALOG_TXRF4_PWDFB2_2G_LSB 20
-#define PHY_ANALOG_TXRF4_PWDFB2_2G_MASK 0x00100000
-#define PHY_ANALOG_TXRF4_PWDFB2_2G_GET(x) (((x) & 0x00100000) >> 20)
-#define PHY_ANALOG_TXRF4_PWDFB2_2G_SET(x) (((x) << 20) & 0x00100000)
-#define PHY_ANALOG_TXRF4_PWDFB1_2G_MSB 21
-#define PHY_ANALOG_TXRF4_PWDFB1_2G_LSB 21
-#define PHY_ANALOG_TXRF4_PWDFB1_2G_MASK 0x00200000
-#define PHY_ANALOG_TXRF4_PWDFB1_2G_GET(x) (((x) & 0x00200000) >> 21)
-#define PHY_ANALOG_TXRF4_PWDFB1_2G_SET(x) (((x) << 21) & 0x00200000)
-#define PHY_ANALOG_TXRF4_PDFB2G_MSB 22
-#define PHY_ANALOG_TXRF4_PDFB2G_LSB 22
-#define PHY_ANALOG_TXRF4_PDFB2G_MASK 0x00400000
-#define PHY_ANALOG_TXRF4_PDFB2G_GET(x) (((x) & 0x00400000) >> 22)
-#define PHY_ANALOG_TXRF4_PDFB2G_SET(x) (((x) << 22) & 0x00400000)
-#define PHY_ANALOG_TXRF4_RDIV5G_MSB 24
-#define PHY_ANALOG_TXRF4_RDIV5G_LSB 23
-#define PHY_ANALOG_TXRF4_RDIV5G_MASK 0x01800000
-#define PHY_ANALOG_TXRF4_RDIV5G_GET(x) (((x) & 0x01800000) >> 23)
-#define PHY_ANALOG_TXRF4_RDIV5G_SET(x) (((x) << 23) & 0x01800000)
-#define PHY_ANALOG_TXRF4_CAPDIV5G_MSB 27
-#define PHY_ANALOG_TXRF4_CAPDIV5G_LSB 25
-#define PHY_ANALOG_TXRF4_CAPDIV5G_MASK 0x0e000000
-#define PHY_ANALOG_TXRF4_CAPDIV5G_GET(x) (((x) & 0x0e000000) >> 25)
-#define PHY_ANALOG_TXRF4_CAPDIV5G_SET(x) (((x) << 25) & 0x0e000000)
-#define PHY_ANALOG_TXRF4_PDPREDIST5G_MSB 28
-#define PHY_ANALOG_TXRF4_PDPREDIST5G_LSB 28
-#define PHY_ANALOG_TXRF4_PDPREDIST5G_MASK 0x10000000
-#define PHY_ANALOG_TXRF4_PDPREDIST5G_GET(x) (((x) & 0x10000000) >> 28)
-#define PHY_ANALOG_TXRF4_PDPREDIST5G_SET(x) (((x) << 28) & 0x10000000)
-#define PHY_ANALOG_TXRF4_RDIV2G_MSB 30
-#define PHY_ANALOG_TXRF4_RDIV2G_LSB 29
-#define PHY_ANALOG_TXRF4_RDIV2G_MASK 0x60000000
-#define PHY_ANALOG_TXRF4_RDIV2G_GET(x) (((x) & 0x60000000) >> 29)
-#define PHY_ANALOG_TXRF4_RDIV2G_SET(x) (((x) << 29) & 0x60000000)
-#define PHY_ANALOG_TXRF4_PDPREDIST2G_MSB 31
-#define PHY_ANALOG_TXRF4_PDPREDIST2G_LSB 31
-#define PHY_ANALOG_TXRF4_PDPREDIST2G_MASK 0x80000000
-#define PHY_ANALOG_TXRF4_PDPREDIST2G_GET(x) (((x) & 0x80000000) >> 31)
-#define PHY_ANALOG_TXRF4_PDPREDIST2G_SET(x) (((x) << 31) & 0x80000000)
-
-/* macros for TXRF5 */
-#define PHY_ANALOG_TXRF5_ADDRESS 0x00000050
-#define PHY_ANALOG_TXRF5_OFFSET 0x00000050
-#define PHY_ANALOG_TXRF5_FBHI2G_MSB 0
-#define PHY_ANALOG_TXRF5_FBHI2G_LSB 0
-#define PHY_ANALOG_TXRF5_FBHI2G_MASK 0x00000001
-#define PHY_ANALOG_TXRF5_FBHI2G_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_ANALOG_TXRF5_FBLO2G_MSB 1
-#define PHY_ANALOG_TXRF5_FBLO2G_LSB 1
-#define PHY_ANALOG_TXRF5_FBLO2G_MASK 0x00000002
-#define PHY_ANALOG_TXRF5_FBLO2G_GET(x) (((x) & 0x00000002) >> 1)
-#define PHY_ANALOG_TXRF5_REFHI2G_MSB 4
-#define PHY_ANALOG_TXRF5_REFHI2G_LSB 2
-#define PHY_ANALOG_TXRF5_REFHI2G_MASK 0x0000001c
-#define PHY_ANALOG_TXRF5_REFHI2G_GET(x) (((x) & 0x0000001c) >> 2)
-#define PHY_ANALOG_TXRF5_REFHI2G_SET(x) (((x) << 2) & 0x0000001c)
-#define PHY_ANALOG_TXRF5_REFLO2G_MSB 7
-#define PHY_ANALOG_TXRF5_REFLO2G_LSB 5
-#define PHY_ANALOG_TXRF5_REFLO2G_MASK 0x000000e0
-#define PHY_ANALOG_TXRF5_REFLO2G_GET(x) (((x) & 0x000000e0) >> 5)
-#define PHY_ANALOG_TXRF5_REFLO2G_SET(x) (((x) << 5) & 0x000000e0)
-#define PHY_ANALOG_TXRF5_PK2B2G_QAM_MSB 9
-#define PHY_ANALOG_TXRF5_PK2B2G_QAM_LSB 8
-#define PHY_ANALOG_TXRF5_PK2B2G_QAM_MASK 0x00000300
-#define PHY_ANALOG_TXRF5_PK2B2G_QAM_GET(x) (((x) & 0x00000300) >> 8)
-#define PHY_ANALOG_TXRF5_PK2B2G_QAM_SET(x) (((x) << 8) & 0x00000300)
-#define PHY_ANALOG_TXRF5_PK2B2G_PSK_MSB 11
-#define PHY_ANALOG_TXRF5_PK2B2G_PSK_LSB 10
-#define PHY_ANALOG_TXRF5_PK2B2G_PSK_MASK 0x00000c00
-#define PHY_ANALOG_TXRF5_PK2B2G_PSK_GET(x) (((x) & 0x00000c00) >> 10)
-#define PHY_ANALOG_TXRF5_PK2B2G_PSK_SET(x) (((x) << 10) & 0x00000c00)
-#define PHY_ANALOG_TXRF5_PK2B2G_CCK_MSB 13
-#define PHY_ANALOG_TXRF5_PK2B2G_CCK_LSB 12
-#define PHY_ANALOG_TXRF5_PK2B2G_CCK_MASK 0x00003000
-#define PHY_ANALOG_TXRF5_PK2B2G_CCK_GET(x) (((x) & 0x00003000) >> 12)
-#define PHY_ANALOG_TXRF5_PK2B2G_CCK_SET(x) (((x) << 12) & 0x00003000)
-#define PHY_ANALOG_TXRF5_PK1B2G_QAM_MSB 15
-#define PHY_ANALOG_TXRF5_PK1B2G_QAM_LSB 14
-#define PHY_ANALOG_TXRF5_PK1B2G_QAM_MASK 0x0000c000
-#define PHY_ANALOG_TXRF5_PK1B2G_QAM_GET(x) (((x) & 0x0000c000) >> 14)
-#define PHY_ANALOG_TXRF5_PK1B2G_QAM_SET(x) (((x) << 14) & 0x0000c000)
-#define PHY_ANALOG_TXRF5_PK1B2G_PSK_MSB 17
-#define PHY_ANALOG_TXRF5_PK1B2G_PSK_LSB 16
-#define PHY_ANALOG_TXRF5_PK1B2G_PSK_MASK 0x00030000
-#define PHY_ANALOG_TXRF5_PK1B2G_PSK_GET(x) (((x) & 0x00030000) >> 16)
-#define PHY_ANALOG_TXRF5_PK1B2G_PSK_SET(x) (((x) << 16) & 0x00030000)
-#define PHY_ANALOG_TXRF5_PK1B2G_CCK_MSB 19
-#define PHY_ANALOG_TXRF5_PK1B2G_CCK_LSB 18
-#define PHY_ANALOG_TXRF5_PK1B2G_CCK_MASK 0x000c0000
-#define PHY_ANALOG_TXRF5_PK1B2G_CCK_GET(x) (((x) & 0x000c0000) >> 18)
-#define PHY_ANALOG_TXRF5_PK1B2G_CCK_SET(x) (((x) << 18) & 0x000c0000)
-#define PHY_ANALOG_TXRF5_MIOB2G_QAM_MSB 22
-#define PHY_ANALOG_TXRF5_MIOB2G_QAM_LSB 20
-#define PHY_ANALOG_TXRF5_MIOB2G_QAM_MASK 0x00700000
-#define PHY_ANALOG_TXRF5_MIOB2G_QAM_GET(x) (((x) & 0x00700000) >> 20)
-#define PHY_ANALOG_TXRF5_MIOB2G_QAM_SET(x) (((x) << 20) & 0x00700000)
-#define PHY_ANALOG_TXRF5_MIOB2G_PSK_MSB 25
-#define PHY_ANALOG_TXRF5_MIOB2G_PSK_LSB 23
-#define PHY_ANALOG_TXRF5_MIOB2G_PSK_MASK 0x03800000
-#define PHY_ANALOG_TXRF5_MIOB2G_PSK_GET(x) (((x) & 0x03800000) >> 23)
-#define PHY_ANALOG_TXRF5_MIOB2G_PSK_SET(x) (((x) << 23) & 0x03800000)
-#define PHY_ANALOG_TXRF5_MIOB2G_CCK_MSB 28
-#define PHY_ANALOG_TXRF5_MIOB2G_CCK_LSB 26
-#define PHY_ANALOG_TXRF5_MIOB2G_CCK_MASK 0x1c000000
-#define PHY_ANALOG_TXRF5_MIOB2G_CCK_GET(x) (((x) & 0x1c000000) >> 26)
-#define PHY_ANALOG_TXRF5_MIOB2G_CCK_SET(x) (((x) << 26) & 0x1c000000)
-#define PHY_ANALOG_TXRF5_COMP2G_QAM_MSB 31
-#define PHY_ANALOG_TXRF5_COMP2G_QAM_LSB 29
-#define PHY_ANALOG_TXRF5_COMP2G_QAM_MASK 0xe0000000
-#define PHY_ANALOG_TXRF5_COMP2G_QAM_GET(x) (((x) & 0xe0000000) >> 29)
-#define PHY_ANALOG_TXRF5_COMP2G_QAM_SET(x) (((x) << 29) & 0xe0000000)
-
-/* macros for TXRF6 */
-#define PHY_ANALOG_TXRF6_ADDRESS 0x00000054
-#define PHY_ANALOG_TXRF6_OFFSET 0x00000054
-#define PHY_ANALOG_TXRF6_SPARE6_MSB 0
-#define PHY_ANALOG_TXRF6_SPARE6_LSB 0
-#define PHY_ANALOG_TXRF6_SPARE6_MASK 0x00000001
-#define PHY_ANALOG_TXRF6_SPARE6_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_ANALOG_TXRF6_SPARE6_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_ANALOG_TXRF6_PAL_LOCKED_MSB 1
-#define PHY_ANALOG_TXRF6_PAL_LOCKED_LSB 1
-#define PHY_ANALOG_TXRF6_PAL_LOCKED_MASK 0x00000002
-#define PHY_ANALOG_TXRF6_PAL_LOCKED_GET(x) (((x) & 0x00000002) >> 1)
-#define PHY_ANALOG_TXRF6_PADRVGN2G_SMOUT_MSB 7
-#define PHY_ANALOG_TXRF6_PADRVGN2G_SMOUT_LSB 2
-#define PHY_ANALOG_TXRF6_PADRVGN2G_SMOUT_MASK 0x000000fc
-#define PHY_ANALOG_TXRF6_PADRVGN2G_SMOUT_GET(x) (((x) & 0x000000fc) >> 2)
-#define PHY_ANALOG_TXRF6_GAINSTEP2G_MSB 10
-#define PHY_ANALOG_TXRF6_GAINSTEP2G_LSB 8
-#define PHY_ANALOG_TXRF6_GAINSTEP2G_MASK 0x00000700
-#define PHY_ANALOG_TXRF6_GAINSTEP2G_GET(x) (((x) & 0x00000700) >> 8)
-#define PHY_ANALOG_TXRF6_GAINSTEP2G_SET(x) (((x) << 8) & 0x00000700)
-#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_MSB 11
-#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_LSB 11
-#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_MASK 0x00000800
-#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_GET(x) (((x) & 0x00000800) >> 11)
-#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_SET(x) (((x) << 11) & 0x00000800)
-#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_MSB 15
-#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_LSB 12
-#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_MASK 0x0000f000
-#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_GET(x) (((x) & 0x0000f000) >> 12)
-#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_SET(x) (((x) << 12) & 0x0000f000)
-#define PHY_ANALOG_TXRF6_VCMONDELAY2G_MSB 18
-#define PHY_ANALOG_TXRF6_VCMONDELAY2G_LSB 16
-#define PHY_ANALOG_TXRF6_VCMONDELAY2G_MASK 0x00070000
-#define PHY_ANALOG_TXRF6_VCMONDELAY2G_GET(x) (((x) & 0x00070000) >> 16)
-#define PHY_ANALOG_TXRF6_VCMONDELAY2G_SET(x) (((x) << 16) & 0x00070000)
-#define PHY_ANALOG_TXRF6_CAPDIV2G_MSB 21
-#define PHY_ANALOG_TXRF6_CAPDIV2G_LSB 19
-#define PHY_ANALOG_TXRF6_CAPDIV2G_MASK 0x00380000
-#define PHY_ANALOG_TXRF6_CAPDIV2G_GET(x) (((x) & 0x00380000) >> 19)
-#define PHY_ANALOG_TXRF6_CAPDIV2G_SET(x) (((x) << 19) & 0x00380000)
-#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_MSB 22
-#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_LSB 22
-#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_MASK 0x00400000
-#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_GET(x) (((x) & 0x00400000) >> 22)
-#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_SET(x) (((x) << 22) & 0x00400000)
-#define PHY_ANALOG_TXRF6_ENPACAL2G_MSB 23
-#define PHY_ANALOG_TXRF6_ENPACAL2G_LSB 23
-#define PHY_ANALOG_TXRF6_ENPACAL2G_MASK 0x00800000
-#define PHY_ANALOG_TXRF6_ENPACAL2G_GET(x) (((x) & 0x00800000) >> 23)
-#define PHY_ANALOG_TXRF6_ENPACAL2G_SET(x) (((x) << 23) & 0x00800000)
-#define PHY_ANALOG_TXRF6_OFFSET2G_MSB 30
-#define PHY_ANALOG_TXRF6_OFFSET2G_LSB 24
-#define PHY_ANALOG_TXRF6_OFFSET2G_MASK 0x7f000000
-#define PHY_ANALOG_TXRF6_OFFSET2G_GET(x) (((x) & 0x7f000000) >> 24)
-#define PHY_ANALOG_TXRF6_OFFSET2G_SET(x) (((x) << 24) & 0x7f000000)
-#define PHY_ANALOG_TXRF6_ENOFFSETCAL2G_MSB 31
-#define PHY_ANALOG_TXRF6_ENOFFSETCAL2G_LSB 31
-#define PHY_ANALOG_TXRF6_ENOFFSETCAL2G_MASK 0x80000000
-#define PHY_ANALOG_TXRF6_ENOFFSETCAL2G_GET(x) (((x) & 0x80000000) >> 31)
-#define PHY_ANALOG_TXRF6_ENOFFSETCAL2G_SET(x) (((x) << 31) & 0x80000000)
-
-/* macros for TXRF7 */
-#define PHY_ANALOG_TXRF7_ADDRESS 0x00000058
-#define PHY_ANALOG_TXRF7_OFFSET 0x00000058
-#define PHY_ANALOG_TXRF7_SPARE7_MSB 1
-#define PHY_ANALOG_TXRF7_SPARE7_LSB 0
-#define PHY_ANALOG_TXRF7_SPARE7_MASK 0x00000003
-#define PHY_ANALOG_TXRF7_SPARE7_GET(x) (((x) & 0x00000003) >> 0)
-#define PHY_ANALOG_TXRF7_SPARE7_SET(x) (((x) << 0) & 0x00000003)
-#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_MSB 7
-#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_LSB 2
-#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_MASK 0x000000fc
-#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_GET(x) (((x) & 0x000000fc) >> 2)
-#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_SET(x) (((x) << 2) & 0x000000fc)
-#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_MSB 13
-#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_LSB 8
-#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_MASK 0x00003f00
-#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_GET(x) (((x) & 0x00003f00) >> 8)
-#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_SET(x) (((x) << 8) & 0x00003f00)
-#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_MSB 19
-#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_LSB 14
-#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_MASK 0x000fc000
-#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_GET(x) (((x) & 0x000fc000) >> 14)
-#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_SET(x) (((x) << 14) & 0x000fc000)
-#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_MSB 25
-#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_LSB 20
-#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_MASK 0x03f00000
-#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_GET(x) (((x) & 0x03f00000) >> 20)
-#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_SET(x) (((x) << 20) & 0x03f00000)
-#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_MSB 31
-#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_LSB 26
-#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_MASK 0xfc000000
-#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_GET(x) (((x) & 0xfc000000) >> 26)
-#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_SET(x) (((x) << 26) & 0xfc000000)
-
-/* macros for TXRF8 */
-#define PHY_ANALOG_TXRF8_ADDRESS 0x0000005c
-#define PHY_ANALOG_TXRF8_OFFSET 0x0000005c
-#define PHY_ANALOG_TXRF8_SPARE8_MSB 1
-#define PHY_ANALOG_TXRF8_SPARE8_LSB 0
-#define PHY_ANALOG_TXRF8_SPARE8_MASK 0x00000003
-#define PHY_ANALOG_TXRF8_SPARE8_GET(x) (((x) & 0x00000003) >> 0)
-#define PHY_ANALOG_TXRF8_SPARE8_SET(x) (((x) << 0) & 0x00000003)
-#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_MSB 7
-#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_LSB 2
-#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_MASK 0x000000fc
-#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_GET(x) (((x) & 0x000000fc) >> 2)
-#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_SET(x) (((x) << 2) & 0x000000fc)
-#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_MSB 13
-#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_LSB 8
-#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_MASK 0x00003f00
-#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_GET(x) (((x) & 0x00003f00) >> 8)
-#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_SET(x) (((x) << 8) & 0x00003f00)
-#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_MSB 19
-#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_LSB 14
-#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_MASK 0x000fc000
-#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_GET(x) (((x) & 0x000fc000) >> 14)
-#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_SET(x) (((x) << 14) & 0x000fc000)
-#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_MSB 25
-#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_LSB 20
-#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_MASK 0x03f00000
-#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_GET(x) (((x) & 0x03f00000) >> 20)
-#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_SET(x) (((x) << 20) & 0x03f00000)
-#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_MSB 31
-#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_LSB 26
-#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_MASK 0xfc000000
-#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_GET(x) (((x) & 0xfc000000) >> 26)
-#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_SET(x) (((x) << 26) & 0xfc000000)
-
-/* macros for TXRF9 */
-#define PHY_ANALOG_TXRF9_ADDRESS 0x00000060
-#define PHY_ANALOG_TXRF9_OFFSET 0x00000060
-#define PHY_ANALOG_TXRF9_SPARE9_MSB 1
-#define PHY_ANALOG_TXRF9_SPARE9_LSB 0
-#define PHY_ANALOG_TXRF9_SPARE9_MASK 0x00000003
-#define PHY_ANALOG_TXRF9_SPARE9_GET(x) (((x) & 0x00000003) >> 0)
-#define PHY_ANALOG_TXRF9_SPARE9_SET(x) (((x) << 0) & 0x00000003)
-#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_MSB 7
-#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_LSB 2
-#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_MASK 0x000000fc
-#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_GET(x) (((x) & 0x000000fc) >> 2)
-#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_SET(x) (((x) << 2) & 0x000000fc)
-#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_MSB 13
-#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_LSB 8
-#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_MASK 0x00003f00
-#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_GET(x) (((x) & 0x00003f00) >> 8)
-#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_SET(x) (((x) << 8) & 0x00003f00)
-#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_MSB 19
-#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_LSB 14
-#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_MASK 0x000fc000
-#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_GET(x) (((x) & 0x000fc000) >> 14)
-#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_SET(x) (((x) << 14) & 0x000fc000)
-#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_MSB 25
-#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_LSB 20
-#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_MASK 0x03f00000
-#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_GET(x) (((x) & 0x03f00000) >> 20)
-#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_SET(x) (((x) << 20) & 0x03f00000)
-#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_MSB 31
-#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_LSB 26
-#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_MASK 0xfc000000
-#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_GET(x) (((x) & 0xfc000000) >> 26)
-#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_SET(x) (((x) << 26) & 0xfc000000)
-
-/* macros for TXRF10 */
-#define PHY_ANALOG_TXRF10_ADDRESS 0x00000064
-#define PHY_ANALOG_TXRF10_OFFSET 0x00000064
-#define PHY_ANALOG_TXRF10_SPARE10_MSB 12
-#define PHY_ANALOG_TXRF10_SPARE10_LSB 0
-#define PHY_ANALOG_TXRF10_SPARE10_MASK 0x00001fff
-#define PHY_ANALOG_TXRF10_SPARE10_GET(x) (((x) & 0x00001fff) >> 0)
-#define PHY_ANALOG_TXRF10_SPARE10_SET(x) (((x) << 0) & 0x00001fff)
-#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_MSB 13
-#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_LSB 13
-#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_MASK 0x00002000
-#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_GET(x) (((x) & 0x00002000) >> 13)
-#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_SET(x) (((x) << 13) & 0x00002000)
-#define PHY_ANALOG_TXRF10_D3B5GCALTX_MSB 16
-#define PHY_ANALOG_TXRF10_D3B5GCALTX_LSB 14
-#define PHY_ANALOG_TXRF10_D3B5GCALTX_MASK 0x0001c000
-#define PHY_ANALOG_TXRF10_D3B5GCALTX_GET(x) (((x) & 0x0001c000) >> 14)
-#define PHY_ANALOG_TXRF10_D3B5GCALTX_SET(x) (((x) << 14) & 0x0001c000)
-#define PHY_ANALOG_TXRF10_D4B5GCALTX_MSB 19
-#define PHY_ANALOG_TXRF10_D4B5GCALTX_LSB 17
-#define PHY_ANALOG_TXRF10_D4B5GCALTX_MASK 0x000e0000
-#define PHY_ANALOG_TXRF10_D4B5GCALTX_GET(x) (((x) & 0x000e0000) >> 17)
-#define PHY_ANALOG_TXRF10_D4B5GCALTX_SET(x) (((x) << 17) & 0x000e0000)
-#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_MSB 26
-#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_LSB 20
-#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_MASK 0x07f00000
-#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_GET(x) (((x) & 0x07f00000) >> 20)
-#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_SET(x) (((x) << 20) & 0x07f00000)
-#define PHY_ANALOG_TXRF10_DB2GCALTX_MSB 29
-#define PHY_ANALOG_TXRF10_DB2GCALTX_LSB 27
-#define PHY_ANALOG_TXRF10_DB2GCALTX_MASK 0x38000000
-#define PHY_ANALOG_TXRF10_DB2GCALTX_GET(x) (((x) & 0x38000000) >> 27)
-#define PHY_ANALOG_TXRF10_DB2GCALTX_SET(x) (((x) << 27) & 0x38000000)
-#define PHY_ANALOG_TXRF10_CALTXSHIFT_MSB 30
-#define PHY_ANALOG_TXRF10_CALTXSHIFT_LSB 30
-#define PHY_ANALOG_TXRF10_CALTXSHIFT_MASK 0x40000000
-#define PHY_ANALOG_TXRF10_CALTXSHIFT_GET(x) (((x) & 0x40000000) >> 30)
-#define PHY_ANALOG_TXRF10_CALTXSHIFT_SET(x) (((x) << 30) & 0x40000000)
-#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_MSB 31
-#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_LSB 31
-#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_MASK 0x80000000
-#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_GET(x) (((x) & 0x80000000) >> 31)
-#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_SET(x) (((x) << 31) & 0x80000000)
-
-/* macros for TXRF11 */
-#define PHY_ANALOG_TXRF11_ADDRESS 0x00000068
-#define PHY_ANALOG_TXRF11_OFFSET 0x00000068
-#define PHY_ANALOG_TXRF11_SPARE11_MSB 1
-#define PHY_ANALOG_TXRF11_SPARE11_LSB 0
-#define PHY_ANALOG_TXRF11_SPARE11_MASK 0x00000003
-#define PHY_ANALOG_TXRF11_SPARE11_GET(x) (((x) & 0x00000003) >> 0)
-#define PHY_ANALOG_TXRF11_SPARE11_SET(x) (((x) << 0) & 0x00000003)
-#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS5G_MSB 4
-#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS5G_LSB 2
-#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS5G_MASK 0x0000001c
-#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS5G_GET(x) (((x) & 0x0000001c) >> 2)
-#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS5G_SET(x) (((x) << 2) & 0x0000001c)
-#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_MSB 7
-#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_LSB 5
-#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_MASK 0x000000e0
-#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_GET(x) (((x) & 0x000000e0) >> 5)
-#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_SET(x) (((x) << 5) & 0x000000e0)
-#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_MSB 10
-#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_LSB 8
-#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_MASK 0x00000700
-#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_GET(x) (((x) & 0x00000700) >> 8)
-#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_SET(x) (((x) << 8) & 0x00000700)
-#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_MSB 13
-#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_LSB 11
-#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_MASK 0x00003800
-#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_GET(x) (((x) & 0x00003800) >> 11)
-#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_SET(x) (((x) << 11) & 0x00003800)
-#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_MSB 16
-#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_LSB 14
-#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_MASK 0x0001c000
-#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_GET(x) (((x) & 0x0001c000) >> 14)
-#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_SET(x) (((x) << 14) & 0x0001c000)
-#define PHY_ANALOG_TXRF11_PWD_ICSPARE_MSB 19
-#define PHY_ANALOG_TXRF11_PWD_ICSPARE_LSB 17
-#define PHY_ANALOG_TXRF11_PWD_ICSPARE_MASK 0x000e0000
-#define PHY_ANALOG_TXRF11_PWD_ICSPARE_GET(x) (((x) & 0x000e0000) >> 17)
-#define PHY_ANALOG_TXRF11_PWD_ICSPARE_SET(x) (((x) << 17) & 0x000e0000)
-#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_MSB 22
-#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_LSB 20
-#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_MASK 0x00700000
-#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_GET(x) (((x) & 0x00700000) >> 20)
-#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_SET(x) (((x) << 20) & 0x00700000)
-#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_MSB 25
-#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_LSB 23
-#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_MASK 0x03800000
-#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_GET(x) (((x) & 0x03800000) >> 23)
-#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_SET(x) (((x) << 23) & 0x03800000)
-#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_MSB 28
-#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_LSB 26
-#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_MASK 0x1c000000
-#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_GET(x) (((x) & 0x1c000000) >> 26)
-#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_SET(x) (((x) << 26) & 0x1c000000)
-#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_MSB 31
-#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_LSB 29
-#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_MASK 0xe0000000
-#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_GET(x) (((x) & 0xe0000000) >> 29)
-#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_SET(x) (((x) << 29) & 0xe0000000)
-
-/* macros for TXRF12 */
-#define PHY_ANALOG_TXRF12_ADDRESS 0x0000006c
-#define PHY_ANALOG_TXRF12_OFFSET 0x0000006c
-#define PHY_ANALOG_TXRF12_SPARE12_2_MSB 7
-#define PHY_ANALOG_TXRF12_SPARE12_2_LSB 0
-#define PHY_ANALOG_TXRF12_SPARE12_2_MASK 0x000000ff
-#define PHY_ANALOG_TXRF12_SPARE12_2_GET(x) (((x) & 0x000000ff) >> 0)
-#define PHY_ANALOG_TXRF12_SPARE12_1_MSB 15
-#define PHY_ANALOG_TXRF12_SPARE12_1_LSB 8
-#define PHY_ANALOG_TXRF12_SPARE12_1_MASK 0x0000ff00
-#define PHY_ANALOG_TXRF12_SPARE12_1_GET(x) (((x) & 0x0000ff00) >> 8)
-#define PHY_ANALOG_TXRF12_SPARE12_1_SET(x) (((x) << 8) & 0x0000ff00)
-#define PHY_ANALOG_TXRF12_ATBSEL5G_MSB 19
-#define PHY_ANALOG_TXRF12_ATBSEL5G_LSB 16
-#define PHY_ANALOG_TXRF12_ATBSEL5G_MASK 0x000f0000
-#define PHY_ANALOG_TXRF12_ATBSEL5G_GET(x) (((x) & 0x000f0000) >> 16)
-#define PHY_ANALOG_TXRF12_ATBSEL5G_SET(x) (((x) << 16) & 0x000f0000)
-#define PHY_ANALOG_TXRF12_ATBSEL2G_MSB 22
-#define PHY_ANALOG_TXRF12_ATBSEL2G_LSB 20
-#define PHY_ANALOG_TXRF12_ATBSEL2G_MASK 0x00700000
-#define PHY_ANALOG_TXRF12_ATBSEL2G_GET(x) (((x) & 0x00700000) >> 20)
-#define PHY_ANALOG_TXRF12_ATBSEL2G_SET(x) (((x) << 20) & 0x00700000)
-#define PHY_ANALOG_TXRF12_PWD_IRSPARE_MSB 25
-#define PHY_ANALOG_TXRF12_PWD_IRSPARE_LSB 23
-#define PHY_ANALOG_TXRF12_PWD_IRSPARE_MASK 0x03800000
-#define PHY_ANALOG_TXRF12_PWD_IRSPARE_GET(x) (((x) & 0x03800000) >> 23)
-#define PHY_ANALOG_TXRF12_PWD_IRSPARE_SET(x) (((x) << 23) & 0x03800000)
-#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_MSB 28
-#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_LSB 26
-#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_MASK 0x1c000000
-#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_GET(x) (((x) & 0x1c000000) >> 26)
-#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_SET(x) (((x) << 26) & 0x1c000000)
-#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_MSB 31
-#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_LSB 29
-#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_MASK 0xe0000000
-#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_GET(x) (((x) & 0xe0000000) >> 29)
-#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_SET(x) (((x) << 29) & 0xe0000000)
-
-/* macros for SYNTH1 */
-#define PHY_ANALOG_SYNTH1_ADDRESS 0x00000080
-#define PHY_ANALOG_SYNTH1_OFFSET 0x00000080
-#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_MSB 2
-#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_LSB 0
-#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_MASK 0x00000007
-#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_GET(x) (((x) & 0x00000007) >> 0)
-#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_SET(x) (((x) << 0) & 0x00000007)
-#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_MSB 5
-#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_LSB 3
-#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_MASK 0x00000038
-#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_GET(x) (((x) & 0x00000038) >> 3)
-#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_SET(x) (((x) << 3) & 0x00000038)
-#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_MSB 6
-#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_LSB 6
-#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_MASK 0x00000040
-#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_GET(x) (((x) & 0x00000040) >> 6)
-#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_SET(x) (((x) << 6) & 0x00000040)
-#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_MSB 7
-#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_LSB 7
-#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_MASK 0x00000080
-#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_GET(x) (((x) & 0x00000080) >> 7)
-#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_SET(x) (((x) << 7) & 0x00000080)
-#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_MSB 8
-#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_LSB 8
-#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_MASK 0x00000100
-#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_GET(x) (((x) & 0x00000100) >> 8)
-#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_SET(x) (((x) << 8) & 0x00000100)
-#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_MSB 9
-#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_LSB 9
-#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_MASK 0x00000200
-#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_GET(x) (((x) & 0x00000200) >> 9)
-#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_SET(x) (((x) << 9) & 0x00000200)
-#define PHY_ANALOG_SYNTH1_MONITOR_REF_MSB 10
-#define PHY_ANALOG_SYNTH1_MONITOR_REF_LSB 10
-#define PHY_ANALOG_SYNTH1_MONITOR_REF_MASK 0x00000400
-#define PHY_ANALOG_SYNTH1_MONITOR_REF_GET(x) (((x) & 0x00000400) >> 10)
-#define PHY_ANALOG_SYNTH1_MONITOR_REF_SET(x) (((x) << 10) & 0x00000400)
-#define PHY_ANALOG_SYNTH1_MONITOR_FB_MSB 11
-#define PHY_ANALOG_SYNTH1_MONITOR_FB_LSB 11
-#define PHY_ANALOG_SYNTH1_MONITOR_FB_MASK 0x00000800
-#define PHY_ANALOG_SYNTH1_MONITOR_FB_GET(x) (((x) & 0x00000800) >> 11)
-#define PHY_ANALOG_SYNTH1_MONITOR_FB_SET(x) (((x) << 11) & 0x00000800)
-#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_MSB 12
-#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_LSB 12
-#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_MASK 0x00001000
-#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_GET(x) (((x) & 0x00001000) >> 12)
-#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_SET(x) (((x) << 12) & 0x00001000)
-#define PHY_ANALOG_SYNTH1_PWUP_PD_MSB 15
-#define PHY_ANALOG_SYNTH1_PWUP_PD_LSB 13
-#define PHY_ANALOG_SYNTH1_PWUP_PD_MASK 0x0000e000
-#define PHY_ANALOG_SYNTH1_PWUP_PD_GET(x) (((x) & 0x0000e000) >> 13)
-#define PHY_ANALOG_SYNTH1_PWUP_PD_SET(x) (((x) << 13) & 0x0000e000)
-#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_MSB 16
-#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_LSB 16
-#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_MASK 0x00010000
-#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_GET(x) (((x) & 0x00010000) >> 16)
-#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_SET(x) (((x) << 16) & 0x00010000)
-#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_MSB 18
-#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_LSB 17
-#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_MASK 0x00060000
-#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_GET(x) (((x) & 0x00060000) >> 17)
-#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_SET(x) (((x) << 17) & 0x00060000)
-#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_MSB 20
-#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_LSB 19
-#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_MASK 0x00180000
-#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_GET(x) (((x) & 0x00180000) >> 19)
-#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_SET(x) (((x) << 19) & 0x00180000)
-#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_MSB 21
-#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_LSB 21
-#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_MASK 0x00200000
-#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_GET(x) (((x) & 0x00200000) >> 21)
-#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_SET(x) (((x) << 21) & 0x00200000)
-#define PHY_ANALOG_SYNTH1_PWUP_LOREF_MSB 22
-#define PHY_ANALOG_SYNTH1_PWUP_LOREF_LSB 22
-#define PHY_ANALOG_SYNTH1_PWUP_LOREF_MASK 0x00400000
-#define PHY_ANALOG_SYNTH1_PWUP_LOREF_GET(x) (((x) & 0x00400000) >> 22)
-#define PHY_ANALOG_SYNTH1_PWUP_LOREF_SET(x) (((x) << 22) & 0x00400000)
-#define PHY_ANALOG_SYNTH1_PWD_LOMIX_MSB 23
-#define PHY_ANALOG_SYNTH1_PWD_LOMIX_LSB 23
-#define PHY_ANALOG_SYNTH1_PWD_LOMIX_MASK 0x00800000
-#define PHY_ANALOG_SYNTH1_PWD_LOMIX_GET(x) (((x) & 0x00800000) >> 23)
-#define PHY_ANALOG_SYNTH1_PWD_LOMIX_SET(x) (((x) << 23) & 0x00800000)
-#define PHY_ANALOG_SYNTH1_PWD_LODIV_MSB 24
-#define PHY_ANALOG_SYNTH1_PWD_LODIV_LSB 24
-#define PHY_ANALOG_SYNTH1_PWD_LODIV_MASK 0x01000000
-#define PHY_ANALOG_SYNTH1_PWD_LODIV_GET(x) (((x) & 0x01000000) >> 24)
-#define PHY_ANALOG_SYNTH1_PWD_LODIV_SET(x) (((x) << 24) & 0x01000000)
-#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_MSB 25
-#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_LSB 25
-#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_MASK 0x02000000
-#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_GET(x) (((x) & 0x02000000) >> 25)
-#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_SET(x) (((x) << 25) & 0x02000000)
-#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_MSB 26
-#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_LSB 26
-#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_MASK 0x04000000
-#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_GET(x) (((x) & 0x04000000) >> 26)
-#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_SET(x) (((x) << 26) & 0x04000000)
-#define PHY_ANALOG_SYNTH1_PWD_PRESC_MSB 27
-#define PHY_ANALOG_SYNTH1_PWD_PRESC_LSB 27
-#define PHY_ANALOG_SYNTH1_PWD_PRESC_MASK 0x08000000
-#define PHY_ANALOG_SYNTH1_PWD_PRESC_GET(x) (((x) & 0x08000000) >> 27)
-#define PHY_ANALOG_SYNTH1_PWD_PRESC_SET(x) (((x) << 27) & 0x08000000)
-#define PHY_ANALOG_SYNTH1_PWD_VCO_MSB 28
-#define PHY_ANALOG_SYNTH1_PWD_VCO_LSB 28
-#define PHY_ANALOG_SYNTH1_PWD_VCO_MASK 0x10000000
-#define PHY_ANALOG_SYNTH1_PWD_VCO_GET(x) (((x) & 0x10000000) >> 28)
-#define PHY_ANALOG_SYNTH1_PWD_VCO_SET(x) (((x) << 28) & 0x10000000)
-#define PHY_ANALOG_SYNTH1_PWD_VCMON_MSB 29
-#define PHY_ANALOG_SYNTH1_PWD_VCMON_LSB 29
-#define PHY_ANALOG_SYNTH1_PWD_VCMON_MASK 0x20000000
-#define PHY_ANALOG_SYNTH1_PWD_VCMON_GET(x) (((x) & 0x20000000) >> 29)
-#define PHY_ANALOG_SYNTH1_PWD_VCMON_SET(x) (((x) << 29) & 0x20000000)
-#define PHY_ANALOG_SYNTH1_PWD_CP_MSB 30
-#define PHY_ANALOG_SYNTH1_PWD_CP_LSB 30
-#define PHY_ANALOG_SYNTH1_PWD_CP_MASK 0x40000000
-#define PHY_ANALOG_SYNTH1_PWD_CP_GET(x) (((x) & 0x40000000) >> 30)
-#define PHY_ANALOG_SYNTH1_PWD_CP_SET(x) (((x) << 30) & 0x40000000)
-#define PHY_ANALOG_SYNTH1_PWD_BIAS_MSB 31
-#define PHY_ANALOG_SYNTH1_PWD_BIAS_LSB 31
-#define PHY_ANALOG_SYNTH1_PWD_BIAS_MASK 0x80000000
-#define PHY_ANALOG_SYNTH1_PWD_BIAS_GET(x) (((x) & 0x80000000) >> 31)
-#define PHY_ANALOG_SYNTH1_PWD_BIAS_SET(x) (((x) << 31) & 0x80000000)
-
-/* macros for SYNTH2 */
-#define PHY_ANALOG_SYNTH2_ADDRESS 0x00000084
-#define PHY_ANALOG_SYNTH2_OFFSET 0x00000084
-#define PHY_ANALOG_SYNTH2_CAPRANGE3_MSB 3
-#define PHY_ANALOG_SYNTH2_CAPRANGE3_LSB 0
-#define PHY_ANALOG_SYNTH2_CAPRANGE3_MASK 0x0000000f
-#define PHY_ANALOG_SYNTH2_CAPRANGE3_GET(x) (((x) & 0x0000000f) >> 0)
-#define PHY_ANALOG_SYNTH2_CAPRANGE3_SET(x) (((x) << 0) & 0x0000000f)
-#define PHY_ANALOG_SYNTH2_CAPRANGE2_MSB 7
-#define PHY_ANALOG_SYNTH2_CAPRANGE2_LSB 4
-#define PHY_ANALOG_SYNTH2_CAPRANGE2_MASK 0x000000f0
-#define PHY_ANALOG_SYNTH2_CAPRANGE2_GET(x) (((x) & 0x000000f0) >> 4)
-#define PHY_ANALOG_SYNTH2_CAPRANGE2_SET(x) (((x) << 4) & 0x000000f0)
-#define PHY_ANALOG_SYNTH2_CAPRANGE1_MSB 11
-#define PHY_ANALOG_SYNTH2_CAPRANGE1_LSB 8
-#define PHY_ANALOG_SYNTH2_CAPRANGE1_MASK 0x00000f00
-#define PHY_ANALOG_SYNTH2_CAPRANGE1_GET(x) (((x) & 0x00000f00) >> 8)
-#define PHY_ANALOG_SYNTH2_CAPRANGE1_SET(x) (((x) << 8) & 0x00000f00)
-#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_MSB 15
-#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_LSB 12
-#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_MASK 0x0000f000
-#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_GET(x) (((x) & 0x0000f000) >> 12)
-#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_SET(x) (((x) << 12) & 0x0000f000)
-#define PHY_ANALOG_SYNTH2_CPLOWLK_MSB 16
-#define PHY_ANALOG_SYNTH2_CPLOWLK_LSB 16
-#define PHY_ANALOG_SYNTH2_CPLOWLK_MASK 0x00010000
-#define PHY_ANALOG_SYNTH2_CPLOWLK_GET(x) (((x) & 0x00010000) >> 16)
-#define PHY_ANALOG_SYNTH2_CPLOWLK_SET(x) (((x) << 16) & 0x00010000)
-#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_MSB 17
-#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_LSB 17
-#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_MASK 0x00020000
-#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_GET(x) (((x) & 0x00020000) >> 17)
-#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_SET(x) (((x) << 17) & 0x00020000)
-#define PHY_ANALOG_SYNTH2_CPBIAS_MSB 19
-#define PHY_ANALOG_SYNTH2_CPBIAS_LSB 18
-#define PHY_ANALOG_SYNTH2_CPBIAS_MASK 0x000c0000
-#define PHY_ANALOG_SYNTH2_CPBIAS_GET(x) (((x) & 0x000c0000) >> 18)
-#define PHY_ANALOG_SYNTH2_CPBIAS_SET(x) (((x) << 18) & 0x000c0000)
-#define PHY_ANALOG_SYNTH2_VC_LOW_REF_MSB 22
-#define PHY_ANALOG_SYNTH2_VC_LOW_REF_LSB 20
-#define PHY_ANALOG_SYNTH2_VC_LOW_REF_MASK 0x00700000
-#define PHY_ANALOG_SYNTH2_VC_LOW_REF_GET(x) (((x) & 0x00700000) >> 20)
-#define PHY_ANALOG_SYNTH2_VC_LOW_REF_SET(x) (((x) << 20) & 0x00700000)
-#define PHY_ANALOG_SYNTH2_VC_MID_REF_MSB 25
-#define PHY_ANALOG_SYNTH2_VC_MID_REF_LSB 23
-#define PHY_ANALOG_SYNTH2_VC_MID_REF_MASK 0x03800000
-#define PHY_ANALOG_SYNTH2_VC_MID_REF_GET(x) (((x) & 0x03800000) >> 23)
-#define PHY_ANALOG_SYNTH2_VC_MID_REF_SET(x) (((x) << 23) & 0x03800000)
-#define PHY_ANALOG_SYNTH2_VC_HI_REF_MSB 28
-#define PHY_ANALOG_SYNTH2_VC_HI_REF_LSB 26
-#define PHY_ANALOG_SYNTH2_VC_HI_REF_MASK 0x1c000000
-#define PHY_ANALOG_SYNTH2_VC_HI_REF_GET(x) (((x) & 0x1c000000) >> 26)
-#define PHY_ANALOG_SYNTH2_VC_HI_REF_SET(x) (((x) << 26) & 0x1c000000)
-#define PHY_ANALOG_SYNTH2_VC_CAL_REF_MSB 31
-#define PHY_ANALOG_SYNTH2_VC_CAL_REF_LSB 29
-#define PHY_ANALOG_SYNTH2_VC_CAL_REF_MASK 0xe0000000
-#define PHY_ANALOG_SYNTH2_VC_CAL_REF_GET(x) (((x) & 0xe0000000) >> 29)
-#define PHY_ANALOG_SYNTH2_VC_CAL_REF_SET(x) (((x) << 29) & 0xe0000000)
-
-/* macros for SYNTH3 */
-#define PHY_ANALOG_SYNTH3_ADDRESS 0x00000088
-#define PHY_ANALOG_SYNTH3_OFFSET 0x00000088
-#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_MSB 5
-#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_LSB 0
-#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_MASK 0x0000003f
-#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_GET(x) (((x) & 0x0000003f) >> 0)
-#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_SET(x) (((x) << 0) & 0x0000003f)
-#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_MSB 11
-#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_LSB 6
-#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_MASK 0x00000fc0
-#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_GET(x) (((x) & 0x00000fc0) >> 6)
-#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_SET(x) (((x) << 6) & 0x00000fc0)
-#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_MSB 17
-#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_LSB 12
-#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_MASK 0x0003f000
-#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_GET(x) (((x) & 0x0003f000) >> 12)
-#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_SET(x) (((x) << 12) & 0x0003f000)
-#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_MSB 23
-#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_LSB 18
-#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_MASK 0x00fc0000
-#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_GET(x) (((x) & 0x00fc0000) >> 18)
-#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_SET(x) (((x) << 18) & 0x00fc0000)
-#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_MSB 29
-#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_LSB 24
-#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_MASK 0x3f000000
-#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_GET(x) (((x) & 0x3f000000) >> 24)
-#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_SET(x) (((x) << 24) & 0x3f000000)
-#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_MSB 30
-#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_LSB 30
-#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_MASK 0x40000000
-#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_GET(x) (((x) & 0x40000000) >> 30)
-#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_SET(x) (((x) << 30) & 0x40000000)
-#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_MSB 31
-#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_LSB 31
-#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_MASK 0x80000000
-#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_GET(x) (((x) & 0x80000000) >> 31)
-#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_SET(x) (((x) << 31) & 0x80000000)
-
-/* macros for SYNTH4 */
-#define PHY_ANALOG_SYNTH4_ADDRESS 0x0000008c
-#define PHY_ANALOG_SYNTH4_OFFSET 0x0000008c
-#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_MSB 0
-#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_LSB 0
-#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_MASK 0x00000001
-#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_MSB 1
-#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_LSB 1
-#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_MASK 0x00000002
-#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_GET(x) (((x) & 0x00000002) >> 1)
-#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_SET(x) (((x) << 1) & 0x00000002)
-#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_MSB 3
-#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_LSB 2
-#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_MASK 0x0000000c
-#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_GET(x) (((x) & 0x0000000c) >> 2)
-#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_SET(x) (((x) << 2) & 0x0000000c)
-#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_MSB 4
-#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_LSB 4
-#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_MASK 0x00000010
-#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_GET(x) (((x) & 0x00000010) >> 4)
-#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_SET(x) (((x) << 4) & 0x00000010)
-#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_MSB 5
-#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_LSB 5
-#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_MASK 0x00000020
-#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_GET(x) (((x) & 0x00000020) >> 5)
-#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_SET(x) (((x) << 5) & 0x00000020)
-#define PHY_ANALOG_SYNTH4_SDM_DITHER_MSB 7
-#define PHY_ANALOG_SYNTH4_SDM_DITHER_LSB 6
-#define PHY_ANALOG_SYNTH4_SDM_DITHER_MASK 0x000000c0
-#define PHY_ANALOG_SYNTH4_SDM_DITHER_GET(x) (((x) & 0x000000c0) >> 6)
-#define PHY_ANALOG_SYNTH4_SDM_DITHER_SET(x) (((x) << 6) & 0x000000c0)
-#define PHY_ANALOG_SYNTH4_SDM_MODE_MSB 8
-#define PHY_ANALOG_SYNTH4_SDM_MODE_LSB 8
-#define PHY_ANALOG_SYNTH4_SDM_MODE_MASK 0x00000100
-#define PHY_ANALOG_SYNTH4_SDM_MODE_GET(x) (((x) & 0x00000100) >> 8)
-#define PHY_ANALOG_SYNTH4_SDM_MODE_SET(x) (((x) << 8) & 0x00000100)
-#define PHY_ANALOG_SYNTH4_SDM_DISABLE_MSB 9
-#define PHY_ANALOG_SYNTH4_SDM_DISABLE_LSB 9
-#define PHY_ANALOG_SYNTH4_SDM_DISABLE_MASK 0x00000200
-#define PHY_ANALOG_SYNTH4_SDM_DISABLE_GET(x) (((x) & 0x00000200) >> 9)
-#define PHY_ANALOG_SYNTH4_SDM_DISABLE_SET(x) (((x) << 9) & 0x00000200)
-#define PHY_ANALOG_SYNTH4_RESET_PRESC_MSB 10
-#define PHY_ANALOG_SYNTH4_RESET_PRESC_LSB 10
-#define PHY_ANALOG_SYNTH4_RESET_PRESC_MASK 0x00000400
-#define PHY_ANALOG_SYNTH4_RESET_PRESC_GET(x) (((x) & 0x00000400) >> 10)
-#define PHY_ANALOG_SYNTH4_RESET_PRESC_SET(x) (((x) << 10) & 0x00000400)
-#define PHY_ANALOG_SYNTH4_PRESCSEL_MSB 12
-#define PHY_ANALOG_SYNTH4_PRESCSEL_LSB 11
-#define PHY_ANALOG_SYNTH4_PRESCSEL_MASK 0x00001800
-#define PHY_ANALOG_SYNTH4_PRESCSEL_GET(x) (((x) & 0x00001800) >> 11)
-#define PHY_ANALOG_SYNTH4_PRESCSEL_SET(x) (((x) << 11) & 0x00001800)
-#define PHY_ANALOG_SYNTH4_PFD_DISABLE_MSB 13
-#define PHY_ANALOG_SYNTH4_PFD_DISABLE_LSB 13
-#define PHY_ANALOG_SYNTH4_PFD_DISABLE_MASK 0x00002000
-#define PHY_ANALOG_SYNTH4_PFD_DISABLE_GET(x) (((x) & 0x00002000) >> 13)
-#define PHY_ANALOG_SYNTH4_PFD_DISABLE_SET(x) (((x) << 13) & 0x00002000)
-#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_MSB 14
-#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_LSB 14
-#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_MASK 0x00004000
-#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_GET(x) (((x) & 0x00004000) >> 14)
-#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_SET(x) (((x) << 14) & 0x00004000)
-#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_MSB 15
-#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_LSB 15
-#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_MASK 0x00008000
-#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_GET(x) (((x) & 0x00008000) >> 15)
-#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_SET(x) (((x) << 15) & 0x00008000)
-#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_MSB 16
-#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_LSB 16
-#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_MASK 0x00010000
-#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_GET(x) (((x) & 0x00010000) >> 16)
-#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_SET(x) (((x) << 16) & 0x00010000)
-#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_MSB 17
-#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_LSB 17
-#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_MASK 0x00020000
-#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_GET(x) (((x) & 0x00020000) >> 17)
-#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_SET(x) (((x) << 17) & 0x00020000)
-#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_MSB 25
-#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_LSB 18
-#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_MASK 0x03fc0000
-#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_GET(x) (((x) & 0x03fc0000) >> 18)
-#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_SET(x) (((x) << 18) & 0x03fc0000)
-#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_MSB 26
-#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_LSB 26
-#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_MASK 0x04000000
-#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_GET(x) (((x) & 0x04000000) >> 26)
-#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_SET(x) (((x) << 26) & 0x04000000)
-#define PHY_ANALOG_SYNTH4_FORCE_PINVC_MSB 27
-#define PHY_ANALOG_SYNTH4_FORCE_PINVC_LSB 27
-#define PHY_ANALOG_SYNTH4_FORCE_PINVC_MASK 0x08000000
-#define PHY_ANALOG_SYNTH4_FORCE_PINVC_GET(x) (((x) & 0x08000000) >> 27)
-#define PHY_ANALOG_SYNTH4_FORCE_PINVC_SET(x) (((x) << 27) & 0x08000000)
-#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_MSB 28
-#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_LSB 28
-#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_MASK 0x10000000
-#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_GET(x) (((x) & 0x10000000) >> 28)
-#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_SET(x) (((x) << 28) & 0x10000000)
-#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_MSB 29
-#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_LSB 29
-#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_MASK 0x20000000
-#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_GET(x) (((x) & 0x20000000) >> 29)
-#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_SET(x) (((x) << 29) & 0x20000000)
-#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_MSB 30
-#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_LSB 30
-#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_MASK 0x40000000
-#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_GET(x) (((x) & 0x40000000) >> 30)
-#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_SET(x) (((x) << 30) & 0x40000000)
-#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_MSB 31
-#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_LSB 31
-#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_MASK 0x80000000
-#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_GET(x) (((x) & 0x80000000) >> 31)
-#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_SET(x) (((x) << 31) & 0x80000000)
-
-/* macros for SYNTH5 */
-#define PHY_ANALOG_SYNTH5_ADDRESS 0x00000090
-#define PHY_ANALOG_SYNTH5_OFFSET 0x00000090
-#define PHY_ANALOG_SYNTH5_VCOBIAS_MSB 1
-#define PHY_ANALOG_SYNTH5_VCOBIAS_LSB 0
-#define PHY_ANALOG_SYNTH5_VCOBIAS_MASK 0x00000003
-#define PHY_ANALOG_SYNTH5_VCOBIAS_GET(x) (((x) & 0x00000003) >> 0)
-#define PHY_ANALOG_SYNTH5_VCOBIAS_SET(x) (((x) << 0) & 0x00000003)
-#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_MSB 4
-#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_LSB 2
-#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_MASK 0x0000001c
-#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_GET(x) (((x) & 0x0000001c) >> 2)
-#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_SET(x) (((x) << 2) & 0x0000001c)
-#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_MSB 7
-#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_LSB 5
-#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_MASK 0x000000e0
-#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_GET(x) (((x) & 0x000000e0) >> 5)
-#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_SET(x) (((x) << 5) & 0x000000e0)
-#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_MSB 10
-#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_LSB 8
-#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_MASK 0x00000700
-#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_GET(x) (((x) & 0x00000700) >> 8)
-#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_SET(x) (((x) << 8) & 0x00000700)
-#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_MSB 13
-#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_LSB 11
-#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_MASK 0x00003800
-#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_GET(x) (((x) & 0x00003800) >> 11)
-#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_SET(x) (((x) << 11) & 0x00003800)
-#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_MSB 14
-#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_LSB 14
-#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_MASK 0x00004000
-#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_GET(x) (((x) & 0x00004000) >> 14)
-#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_SET(x) (((x) << 14) & 0x00004000)
-#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_MSB 17
-#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_LSB 15
-#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_MASK 0x00038000
-#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_GET(x) (((x) & 0x00038000) >> 15)
-#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_SET(x) (((x) << 15) & 0x00038000)
-#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_MSB 20
-#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_LSB 18
-#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_MASK 0x001c0000
-#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_GET(x) (((x) & 0x001c0000) >> 18)
-#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_SET(x) (((x) << 18) & 0x001c0000)
-#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_MSB 23
-#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_LSB 21
-#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_MASK 0x00e00000
-#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_GET(x) (((x) & 0x00e00000) >> 21)
-#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_SET(x) (((x) << 21) & 0x00e00000)
-#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_MSB 26
-#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_LSB 24
-#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_MASK 0x07000000
-#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_GET(x) (((x) & 0x07000000) >> 24)
-#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_SET(x) (((x) << 24) & 0x07000000)
-#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_MSB 29
-#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_LSB 27
-#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_MASK 0x38000000
-#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_GET(x) (((x) & 0x38000000) >> 27)
-#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_SET(x) (((x) << 27) & 0x38000000)
-#define PHY_ANALOG_SYNTH5_SPARE5A_MSB 31
-#define PHY_ANALOG_SYNTH5_SPARE5A_LSB 30
-#define PHY_ANALOG_SYNTH5_SPARE5A_MASK 0xc0000000
-#define PHY_ANALOG_SYNTH5_SPARE5A_GET(x) (((x) & 0xc0000000) >> 30)
-#define PHY_ANALOG_SYNTH5_SPARE5A_SET(x) (((x) << 30) & 0xc0000000)
-
-/* macros for SYNTH6 */
-#define PHY_ANALOG_SYNTH6_ADDRESS 0x00000094
-#define PHY_ANALOG_SYNTH6_OFFSET 0x00000094
-#define PHY_ANALOG_SYNTH6_LOBUF5GTUNE_MSB 1
-#define PHY_ANALOG_SYNTH6_LOBUF5GTUNE_LSB 0
-#define PHY_ANALOG_SYNTH6_LOBUF5GTUNE_MASK 0x00000003
-#define PHY_ANALOG_SYNTH6_LOBUF5GTUNE_GET(x) (((x) & 0x00000003) >> 0)
-#define PHY_ANALOG_SYNTH6_LOOP_IP_MSB 8
-#define PHY_ANALOG_SYNTH6_LOOP_IP_LSB 2
-#define PHY_ANALOG_SYNTH6_LOOP_IP_MASK 0x000001fc
-#define PHY_ANALOG_SYNTH6_LOOP_IP_GET(x) (((x) & 0x000001fc) >> 2)
-#define PHY_ANALOG_SYNTH6_VC2LOW_MSB 9
-#define PHY_ANALOG_SYNTH6_VC2LOW_LSB 9
-#define PHY_ANALOG_SYNTH6_VC2LOW_MASK 0x00000200
-#define PHY_ANALOG_SYNTH6_VC2LOW_GET(x) (((x) & 0x00000200) >> 9)
-#define PHY_ANALOG_SYNTH6_VC2HIGH_MSB 10
-#define PHY_ANALOG_SYNTH6_VC2HIGH_LSB 10
-#define PHY_ANALOG_SYNTH6_VC2HIGH_MASK 0x00000400
-#define PHY_ANALOG_SYNTH6_VC2HIGH_GET(x) (((x) & 0x00000400) >> 10)
-#define PHY_ANALOG_SYNTH6_RESET_SDM_B_MSB 11
-#define PHY_ANALOG_SYNTH6_RESET_SDM_B_LSB 11
-#define PHY_ANALOG_SYNTH6_RESET_SDM_B_MASK 0x00000800
-#define PHY_ANALOG_SYNTH6_RESET_SDM_B_GET(x) (((x) & 0x00000800) >> 11)
-#define PHY_ANALOG_SYNTH6_RESET_PSCOUNTERS_MSB 12
-#define PHY_ANALOG_SYNTH6_RESET_PSCOUNTERS_LSB 12
-#define PHY_ANALOG_SYNTH6_RESET_PSCOUNTERS_MASK 0x00001000
-#define PHY_ANALOG_SYNTH6_RESET_PSCOUNTERS_GET(x) (((x) & 0x00001000) >> 12)
-#define PHY_ANALOG_SYNTH6_RESET_PFD_MSB 13
-#define PHY_ANALOG_SYNTH6_RESET_PFD_LSB 13
-#define PHY_ANALOG_SYNTH6_RESET_PFD_MASK 0x00002000
-#define PHY_ANALOG_SYNTH6_RESET_PFD_GET(x) (((x) & 0x00002000) >> 13)
-#define PHY_ANALOG_SYNTH6_RESET_RFD_MSB 14
-#define PHY_ANALOG_SYNTH6_RESET_RFD_LSB 14
-#define PHY_ANALOG_SYNTH6_RESET_RFD_MASK 0x00004000
-#define PHY_ANALOG_SYNTH6_RESET_RFD_GET(x) (((x) & 0x00004000) >> 14)
-#define PHY_ANALOG_SYNTH6_SHORT_R_MSB 15
-#define PHY_ANALOG_SYNTH6_SHORT_R_LSB 15
-#define PHY_ANALOG_SYNTH6_SHORT_R_MASK 0x00008000
-#define PHY_ANALOG_SYNTH6_SHORT_R_GET(x) (((x) & 0x00008000) >> 15)
-#define PHY_ANALOG_SYNTH6_VCO_CAP_ST_MSB 23
-#define PHY_ANALOG_SYNTH6_VCO_CAP_ST_LSB 16
-#define PHY_ANALOG_SYNTH6_VCO_CAP_ST_MASK 0x00ff0000
-#define PHY_ANALOG_SYNTH6_VCO_CAP_ST_GET(x) (((x) & 0x00ff0000) >> 16)
-#define PHY_ANALOG_SYNTH6_PIN_VC_MSB 24
-#define PHY_ANALOG_SYNTH6_PIN_VC_LSB 24
-#define PHY_ANALOG_SYNTH6_PIN_VC_MASK 0x01000000
-#define PHY_ANALOG_SYNTH6_PIN_VC_GET(x) (((x) & 0x01000000) >> 24)
-#define PHY_ANALOG_SYNTH6_SYNTH_LOCK_VC_OK_MSB 25
-#define PHY_ANALOG_SYNTH6_SYNTH_LOCK_VC_OK_LSB 25
-#define PHY_ANALOG_SYNTH6_SYNTH_LOCK_VC_OK_MASK 0x02000000
-#define PHY_ANALOG_SYNTH6_SYNTH_LOCK_VC_OK_GET(x) (((x) & 0x02000000) >> 25)
-#define PHY_ANALOG_SYNTH6_CAP_SEARCH_MSB 26
-#define PHY_ANALOG_SYNTH6_CAP_SEARCH_LSB 26
-#define PHY_ANALOG_SYNTH6_CAP_SEARCH_MASK 0x04000000
-#define PHY_ANALOG_SYNTH6_CAP_SEARCH_GET(x) (((x) & 0x04000000) >> 26)
-#define PHY_ANALOG_SYNTH6_SYNTH_SM_STATE_MSB 30
-#define PHY_ANALOG_SYNTH6_SYNTH_SM_STATE_LSB 27
-#define PHY_ANALOG_SYNTH6_SYNTH_SM_STATE_MASK 0x78000000
-#define PHY_ANALOG_SYNTH6_SYNTH_SM_STATE_GET(x) (((x) & 0x78000000) >> 27)
-#define PHY_ANALOG_SYNTH6_SYNTH_ON_MSB 31
-#define PHY_ANALOG_SYNTH6_SYNTH_ON_LSB 31
-#define PHY_ANALOG_SYNTH6_SYNTH_ON_MASK 0x80000000
-#define PHY_ANALOG_SYNTH6_SYNTH_ON_GET(x) (((x) & 0x80000000) >> 31)
-
-/* macros for SYNTH7 */
-#define PHY_ANALOG_SYNTH7_ADDRESS 0x00000098
-#define PHY_ANALOG_SYNTH7_OFFSET 0x00000098
-#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_MSB 0
-#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_LSB 0
-#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_MASK 0x00000001
-#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_MSB 1
-#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_LSB 1
-#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_MASK 0x00000002
-#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_GET(x) (((x) & 0x00000002) >> 1)
-#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_SET(x) (((x) << 1) & 0x00000002)
-#define PHY_ANALOG_SYNTH7_CHANFRAC_MSB 18
-#define PHY_ANALOG_SYNTH7_CHANFRAC_LSB 2
-#define PHY_ANALOG_SYNTH7_CHANFRAC_MASK 0x0007fffc
-#define PHY_ANALOG_SYNTH7_CHANFRAC_GET(x) (((x) & 0x0007fffc) >> 2)
-#define PHY_ANALOG_SYNTH7_CHANFRAC_SET(x) (((x) << 2) & 0x0007fffc)
-#define PHY_ANALOG_SYNTH7_CHANSEL_MSB 27
-#define PHY_ANALOG_SYNTH7_CHANSEL_LSB 19
-#define PHY_ANALOG_SYNTH7_CHANSEL_MASK 0x0ff80000
-#define PHY_ANALOG_SYNTH7_CHANSEL_GET(x) (((x) & 0x0ff80000) >> 19)
-#define PHY_ANALOG_SYNTH7_CHANSEL_SET(x) (((x) << 19) & 0x0ff80000)
-#define PHY_ANALOG_SYNTH7_AMODEREFSEL_MSB 29
-#define PHY_ANALOG_SYNTH7_AMODEREFSEL_LSB 28
-#define PHY_ANALOG_SYNTH7_AMODEREFSEL_MASK 0x30000000
-#define PHY_ANALOG_SYNTH7_AMODEREFSEL_GET(x) (((x) & 0x30000000) >> 28)
-#define PHY_ANALOG_SYNTH7_AMODEREFSEL_SET(x) (((x) << 28) & 0x30000000)
-#define PHY_ANALOG_SYNTH7_FRACMODE_MSB 30
-#define PHY_ANALOG_SYNTH7_FRACMODE_LSB 30
-#define PHY_ANALOG_SYNTH7_FRACMODE_MASK 0x40000000
-#define PHY_ANALOG_SYNTH7_FRACMODE_GET(x) (((x) & 0x40000000) >> 30)
-#define PHY_ANALOG_SYNTH7_FRACMODE_SET(x) (((x) << 30) & 0x40000000)
-#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_MSB 31
-#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_LSB 31
-#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_MASK 0x80000000
-#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_GET(x) (((x) & 0x80000000) >> 31)
-#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_SET(x) (((x) << 31) & 0x80000000)
-
-/* macros for SYNTH8 */
-#define PHY_ANALOG_SYNTH8_ADDRESS 0x0000009c
-#define PHY_ANALOG_SYNTH8_OFFSET 0x0000009c
-#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_MSB 0
-#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_LSB 0
-#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_MASK 0x00000001
-#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_ANALOG_SYNTH8_LOOP_ICPB_MSB 7
-#define PHY_ANALOG_SYNTH8_LOOP_ICPB_LSB 1
-#define PHY_ANALOG_SYNTH8_LOOP_ICPB_MASK 0x000000fe
-#define PHY_ANALOG_SYNTH8_LOOP_ICPB_GET(x) (((x) & 0x000000fe) >> 1)
-#define PHY_ANALOG_SYNTH8_LOOP_ICPB_SET(x) (((x) << 1) & 0x000000fe)
-#define PHY_ANALOG_SYNTH8_LOOP_CSB_MSB 11
-#define PHY_ANALOG_SYNTH8_LOOP_CSB_LSB 8
-#define PHY_ANALOG_SYNTH8_LOOP_CSB_MASK 0x00000f00
-#define PHY_ANALOG_SYNTH8_LOOP_CSB_GET(x) (((x) & 0x00000f00) >> 8)
-#define PHY_ANALOG_SYNTH8_LOOP_CSB_SET(x) (((x) << 8) & 0x00000f00)
-#define PHY_ANALOG_SYNTH8_LOOP_RSB_MSB 16
-#define PHY_ANALOG_SYNTH8_LOOP_RSB_LSB 12
-#define PHY_ANALOG_SYNTH8_LOOP_RSB_MASK 0x0001f000
-#define PHY_ANALOG_SYNTH8_LOOP_RSB_GET(x) (((x) & 0x0001f000) >> 12)
-#define PHY_ANALOG_SYNTH8_LOOP_RSB_SET(x) (((x) << 12) & 0x0001f000)
-#define PHY_ANALOG_SYNTH8_LOOP_CPB_MSB 21
-#define PHY_ANALOG_SYNTH8_LOOP_CPB_LSB 17
-#define PHY_ANALOG_SYNTH8_LOOP_CPB_MASK 0x003e0000
-#define PHY_ANALOG_SYNTH8_LOOP_CPB_GET(x) (((x) & 0x003e0000) >> 17)
-#define PHY_ANALOG_SYNTH8_LOOP_CPB_SET(x) (((x) << 17) & 0x003e0000)
-#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_MSB 26
-#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_LSB 22
-#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_MASK 0x07c00000
-#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_GET(x) (((x) & 0x07c00000) >> 22)
-#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_SET(x) (((x) << 22) & 0x07c00000)
-#define PHY_ANALOG_SYNTH8_REFDIVB_MSB 31
-#define PHY_ANALOG_SYNTH8_REFDIVB_LSB 27
-#define PHY_ANALOG_SYNTH8_REFDIVB_MASK 0xf8000000
-#define PHY_ANALOG_SYNTH8_REFDIVB_GET(x) (((x) & 0xf8000000) >> 27)
-#define PHY_ANALOG_SYNTH8_REFDIVB_SET(x) (((x) << 27) & 0xf8000000)
-
-/* macros for SYNTH9 */
-#define PHY_ANALOG_SYNTH9_ADDRESS 0x000000a0
-#define PHY_ANALOG_SYNTH9_OFFSET 0x000000a0
-#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_MSB 0
-#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_LSB 0
-#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_MASK 0x00000001
-#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_MSB 3
-#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_LSB 1
-#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_MASK 0x0000000e
-#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_GET(x) (((x) & 0x0000000e) >> 1)
-#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_SET(x) (((x) << 1) & 0x0000000e)
-#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_MSB 7
-#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_LSB 4
-#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_MASK 0x000000f0
-#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_GET(x) (((x) & 0x000000f0) >> 4)
-#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_SET(x) (((x) << 4) & 0x000000f0)
-#define PHY_ANALOG_SYNTH9_LOOP_CSA0_MSB 11
-#define PHY_ANALOG_SYNTH9_LOOP_CSA0_LSB 8
-#define PHY_ANALOG_SYNTH9_LOOP_CSA0_MASK 0x00000f00
-#define PHY_ANALOG_SYNTH9_LOOP_CSA0_GET(x) (((x) & 0x00000f00) >> 8)
-#define PHY_ANALOG_SYNTH9_LOOP_CSA0_SET(x) (((x) << 8) & 0x00000f00)
-#define PHY_ANALOG_SYNTH9_LOOP_RSA0_MSB 16
-#define PHY_ANALOG_SYNTH9_LOOP_RSA0_LSB 12
-#define PHY_ANALOG_SYNTH9_LOOP_RSA0_MASK 0x0001f000
-#define PHY_ANALOG_SYNTH9_LOOP_RSA0_GET(x) (((x) & 0x0001f000) >> 12)
-#define PHY_ANALOG_SYNTH9_LOOP_RSA0_SET(x) (((x) << 12) & 0x0001f000)
-#define PHY_ANALOG_SYNTH9_LOOP_CPA0_MSB 21
-#define PHY_ANALOG_SYNTH9_LOOP_CPA0_LSB 17
-#define PHY_ANALOG_SYNTH9_LOOP_CPA0_MASK 0x003e0000
-#define PHY_ANALOG_SYNTH9_LOOP_CPA0_GET(x) (((x) & 0x003e0000) >> 17)
-#define PHY_ANALOG_SYNTH9_LOOP_CPA0_SET(x) (((x) << 17) & 0x003e0000)
-#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_MSB 26
-#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_LSB 22
-#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_MASK 0x07c00000
-#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_GET(x) (((x) & 0x07c00000) >> 22)
-#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_SET(x) (((x) << 22) & 0x07c00000)
-#define PHY_ANALOG_SYNTH9_REFDIVA_MSB 31
-#define PHY_ANALOG_SYNTH9_REFDIVA_LSB 27
-#define PHY_ANALOG_SYNTH9_REFDIVA_MASK 0xf8000000
-#define PHY_ANALOG_SYNTH9_REFDIVA_GET(x) (((x) & 0xf8000000) >> 27)
-#define PHY_ANALOG_SYNTH9_REFDIVA_SET(x) (((x) << 27) & 0xf8000000)
-
-/* macros for SYNTH10 */
-#define PHY_ANALOG_SYNTH10_ADDRESS 0x000000a4
-#define PHY_ANALOG_SYNTH10_OFFSET 0x000000a4
-#define PHY_ANALOG_SYNTH10_SPARE10A_MSB 0
-#define PHY_ANALOG_SYNTH10_SPARE10A_LSB 0
-#define PHY_ANALOG_SYNTH10_SPARE10A_MASK 0x00000001
-#define PHY_ANALOG_SYNTH10_SPARE10A_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_ANALOG_SYNTH10_SPARE10A_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_MSB 3
-#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_LSB 1
-#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_MASK 0x0000000e
-#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_GET(x) (((x) & 0x0000000e) >> 1)
-#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_SET(x) (((x) << 1) & 0x0000000e)
-#define PHY_ANALOG_SYNTH10_EN_2X_LOOPFILT_MSB 4
-#define PHY_ANALOG_SYNTH10_EN_2X_LOOPFILT_LSB 4
-#define PHY_ANALOG_SYNTH10_EN_2X_LOOPFILT_MASK 0x00000010
-#define PHY_ANALOG_SYNTH10_EN_2X_LOOPFILT_GET(x) (((x) & 0x00000010) >> 4)
-#define PHY_ANALOG_SYNTH10_EN_2X_LOOPFILT_SET(x) (((x) << 4) & 0x00000010)
-#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_MSB 7
-#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_LSB 5
-#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_MASK 0x000000e0
-#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_GET(x) (((x) & 0x000000e0) >> 5)
-#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_SET(x) (((x) << 5) & 0x000000e0)
-#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_MSB 10
-#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_LSB 8
-#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_MASK 0x00000700
-#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_GET(x) (((x) & 0x00000700) >> 8)
-#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_SET(x) (((x) << 8) & 0x00000700)
-#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_MSB 13
-#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_LSB 11
-#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_MASK 0x00003800
-#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_GET(x) (((x) & 0x00003800) >> 11)
-#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_SET(x) (((x) << 11) & 0x00003800)
-#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_MSB 17
-#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_LSB 14
-#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_MASK 0x0003c000
-#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_GET(x) (((x) & 0x0003c000) >> 14)
-#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_SET(x) (((x) << 14) & 0x0003c000)
-#define PHY_ANALOG_SYNTH10_LOOP_CSA1_MSB 21
-#define PHY_ANALOG_SYNTH10_LOOP_CSA1_LSB 18
-#define PHY_ANALOG_SYNTH10_LOOP_CSA1_MASK 0x003c0000
-#define PHY_ANALOG_SYNTH10_LOOP_CSA1_GET(x) (((x) & 0x003c0000) >> 18)
-#define PHY_ANALOG_SYNTH10_LOOP_CSA1_SET(x) (((x) << 18) & 0x003c0000)
-#define PHY_ANALOG_SYNTH10_LOOP_RSA1_MSB 26
-#define PHY_ANALOG_SYNTH10_LOOP_RSA1_LSB 22
-#define PHY_ANALOG_SYNTH10_LOOP_RSA1_MASK 0x07c00000
-#define PHY_ANALOG_SYNTH10_LOOP_RSA1_GET(x) (((x) & 0x07c00000) >> 22)
-#define PHY_ANALOG_SYNTH10_LOOP_RSA1_SET(x) (((x) << 22) & 0x07c00000)
-#define PHY_ANALOG_SYNTH10_LOOP_CPA1_MSB 31
-#define PHY_ANALOG_SYNTH10_LOOP_CPA1_LSB 27
-#define PHY_ANALOG_SYNTH10_LOOP_CPA1_MASK 0xf8000000
-#define PHY_ANALOG_SYNTH10_LOOP_CPA1_GET(x) (((x) & 0xf8000000) >> 27)
-#define PHY_ANALOG_SYNTH10_LOOP_CPA1_SET(x) (((x) << 27) & 0xf8000000)
-
-/* macros for SYNTH11 */
-#define PHY_ANALOG_SYNTH11_ADDRESS 0x000000a8
-#define PHY_ANALOG_SYNTH11_OFFSET 0x000000a8
-#define PHY_ANALOG_SYNTH11_SPARE11A_MSB 4
-#define PHY_ANALOG_SYNTH11_SPARE11A_LSB 0
-#define PHY_ANALOG_SYNTH11_SPARE11A_MASK 0x0000001f
-#define PHY_ANALOG_SYNTH11_SPARE11A_GET(x) (((x) & 0x0000001f) >> 0)
-#define PHY_ANALOG_SYNTH11_SPARE11A_SET(x) (((x) << 0) & 0x0000001f)
-#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_MSB 5
-#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_LSB 5
-#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_MASK 0x00000020
-#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_GET(x) (((x) & 0x00000020) >> 5)
-#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_SET(x) (((x) << 5) & 0x00000020)
-#define PHY_ANALOG_SYNTH11_LOREFSEL_MSB 7
-#define PHY_ANALOG_SYNTH11_LOREFSEL_LSB 6
-#define PHY_ANALOG_SYNTH11_LOREFSEL_MASK 0x000000c0
-#define PHY_ANALOG_SYNTH11_LOREFSEL_GET(x) (((x) & 0x000000c0) >> 6)
-#define PHY_ANALOG_SYNTH11_LOREFSEL_SET(x) (((x) << 6) & 0x000000c0)
-#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_MSB 9
-#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_LSB 8
-#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_MASK 0x00000300
-#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_GET(x) (((x) & 0x00000300) >> 8)
-#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_SET(x) (((x) << 8) & 0x00000300)
-#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_MSB 10
-#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_LSB 10
-#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_MASK 0x00000400
-#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_GET(x) (((x) & 0x00000400) >> 10)
-#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_SET(x) (((x) << 10) & 0x00000400)
-#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_MSB 13
-#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_LSB 11
-#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_MASK 0x00003800
-#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_GET(x) (((x) & 0x00003800) >> 11)
-#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_SET(x) (((x) << 11) & 0x00003800)
-#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_MSB 17
-#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_LSB 14
-#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_MASK 0x0003c000
-#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_GET(x) (((x) & 0x0003c000) >> 14)
-#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_SET(x) (((x) << 14) & 0x0003c000)
-#define PHY_ANALOG_SYNTH11_LOOP_CSA2_MSB 21
-#define PHY_ANALOG_SYNTH11_LOOP_CSA2_LSB 18
-#define PHY_ANALOG_SYNTH11_LOOP_CSA2_MASK 0x003c0000
-#define PHY_ANALOG_SYNTH11_LOOP_CSA2_GET(x) (((x) & 0x003c0000) >> 18)
-#define PHY_ANALOG_SYNTH11_LOOP_CSA2_SET(x) (((x) << 18) & 0x003c0000)
-#define PHY_ANALOG_SYNTH11_LOOP_RSA2_MSB 26
-#define PHY_ANALOG_SYNTH11_LOOP_RSA2_LSB 22
-#define PHY_ANALOG_SYNTH11_LOOP_RSA2_MASK 0x07c00000
-#define PHY_ANALOG_SYNTH11_LOOP_RSA2_GET(x) (((x) & 0x07c00000) >> 22)
-#define PHY_ANALOG_SYNTH11_LOOP_RSA2_SET(x) (((x) << 22) & 0x07c00000)
-#define PHY_ANALOG_SYNTH11_LOOP_CPA2_MSB 31
-#define PHY_ANALOG_SYNTH11_LOOP_CPA2_LSB 27
-#define PHY_ANALOG_SYNTH11_LOOP_CPA2_MASK 0xf8000000
-#define PHY_ANALOG_SYNTH11_LOOP_CPA2_GET(x) (((x) & 0xf8000000) >> 27)
-#define PHY_ANALOG_SYNTH11_LOOP_CPA2_SET(x) (((x) << 27) & 0xf8000000)
-
-/* macros for SYNTH12 */
-#define PHY_ANALOG_SYNTH12_ADDRESS 0x000000ac
-#define PHY_ANALOG_SYNTH12_OFFSET 0x000000ac
-#define PHY_ANALOG_SYNTH12_SPARE12A_MSB 17
-#define PHY_ANALOG_SYNTH12_SPARE12A_LSB 0
-#define PHY_ANALOG_SYNTH12_SPARE12A_MASK 0x0003ffff
-#define PHY_ANALOG_SYNTH12_SPARE12A_GET(x) (((x) & 0x0003ffff) >> 0)
-#define PHY_ANALOG_SYNTH12_SPARE12A_SET(x) (((x) << 0) & 0x0003ffff)
-#define PHY_ANALOG_SYNTH12_STRCONT_MSB 18
-#define PHY_ANALOG_SYNTH12_STRCONT_LSB 18
-#define PHY_ANALOG_SYNTH12_STRCONT_MASK 0x00040000
-#define PHY_ANALOG_SYNTH12_STRCONT_GET(x) (((x) & 0x00040000) >> 18)
-#define PHY_ANALOG_SYNTH12_STRCONT_SET(x) (((x) << 18) & 0x00040000)
-#define PHY_ANALOG_SYNTH12_VREFMUL3_MSB 22
-#define PHY_ANALOG_SYNTH12_VREFMUL3_LSB 19
-#define PHY_ANALOG_SYNTH12_VREFMUL3_MASK 0x00780000
-#define PHY_ANALOG_SYNTH12_VREFMUL3_GET(x) (((x) & 0x00780000) >> 19)
-#define PHY_ANALOG_SYNTH12_VREFMUL3_SET(x) (((x) << 19) & 0x00780000)
-#define PHY_ANALOG_SYNTH12_VREFMUL2_MSB 26
-#define PHY_ANALOG_SYNTH12_VREFMUL2_LSB 23
-#define PHY_ANALOG_SYNTH12_VREFMUL2_MASK 0x07800000
-#define PHY_ANALOG_SYNTH12_VREFMUL2_GET(x) (((x) & 0x07800000) >> 23)
-#define PHY_ANALOG_SYNTH12_VREFMUL2_SET(x) (((x) << 23) & 0x07800000)
-#define PHY_ANALOG_SYNTH12_VREFMUL1_MSB 30
-#define PHY_ANALOG_SYNTH12_VREFMUL1_LSB 27
-#define PHY_ANALOG_SYNTH12_VREFMUL1_MASK 0x78000000
-#define PHY_ANALOG_SYNTH12_VREFMUL1_GET(x) (((x) & 0x78000000) >> 27)
-#define PHY_ANALOG_SYNTH12_VREFMUL1_SET(x) (((x) << 27) & 0x78000000)
-#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_MSB 31
-#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_LSB 31
-#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_MASK 0x80000000
-#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_GET(x) (((x) & 0x80000000) >> 31)
-#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_SET(x) (((x) << 31) & 0x80000000)
-
-/* macros for BIAS1 */
-#define PHY_ANALOG_BIAS1_ADDRESS 0x000000c0
-#define PHY_ANALOG_BIAS1_OFFSET 0x000000c0
-#define PHY_ANALOG_BIAS1_SPARE1_MSB 6
-#define PHY_ANALOG_BIAS1_SPARE1_LSB 0
-#define PHY_ANALOG_BIAS1_SPARE1_MASK 0x0000007f
-#define PHY_ANALOG_BIAS1_SPARE1_GET(x) (((x) & 0x0000007f) >> 0)
-#define PHY_ANALOG_BIAS1_SPARE1_SET(x) (((x) << 0) & 0x0000007f)
-#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_MSB 9
-#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_LSB 7
-#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_MASK 0x00000380
-#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_GET(x) (((x) & 0x00000380) >> 7)
-#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_SET(x) (((x) << 7) & 0x00000380)
-#define PHY_ANALOG_BIAS1_PWD_IC25V2II_MSB 12
-#define PHY_ANALOG_BIAS1_PWD_IC25V2II_LSB 10
-#define PHY_ANALOG_BIAS1_PWD_IC25V2II_MASK 0x00001c00
-#define PHY_ANALOG_BIAS1_PWD_IC25V2II_GET(x) (((x) & 0x00001c00) >> 10)
-#define PHY_ANALOG_BIAS1_PWD_IC25V2II_SET(x) (((x) << 10) & 0x00001c00)
-#define PHY_ANALOG_BIAS1_PWD_IC25BB_MSB 15
-#define PHY_ANALOG_BIAS1_PWD_IC25BB_LSB 13
-#define PHY_ANALOG_BIAS1_PWD_IC25BB_MASK 0x0000e000
-#define PHY_ANALOG_BIAS1_PWD_IC25BB_GET(x) (((x) & 0x0000e000) >> 13)
-#define PHY_ANALOG_BIAS1_PWD_IC25BB_SET(x) (((x) << 13) & 0x0000e000)
-#define PHY_ANALOG_BIAS1_PWD_IC25DAC_MSB 18
-#define PHY_ANALOG_BIAS1_PWD_IC25DAC_LSB 16
-#define PHY_ANALOG_BIAS1_PWD_IC25DAC_MASK 0x00070000
-#define PHY_ANALOG_BIAS1_PWD_IC25DAC_GET(x) (((x) & 0x00070000) >> 16)
-#define PHY_ANALOG_BIAS1_PWD_IC25DAC_SET(x) (((x) << 16) & 0x00070000)
-#define PHY_ANALOG_BIAS1_PWD_IC25FIR_MSB 21
-#define PHY_ANALOG_BIAS1_PWD_IC25FIR_LSB 19
-#define PHY_ANALOG_BIAS1_PWD_IC25FIR_MASK 0x00380000
-#define PHY_ANALOG_BIAS1_PWD_IC25FIR_GET(x) (((x) & 0x00380000) >> 19)
-#define PHY_ANALOG_BIAS1_PWD_IC25FIR_SET(x) (((x) << 19) & 0x00380000)
-#define PHY_ANALOG_BIAS1_PWD_IC25ADC_MSB 24
-#define PHY_ANALOG_BIAS1_PWD_IC25ADC_LSB 22
-#define PHY_ANALOG_BIAS1_PWD_IC25ADC_MASK 0x01c00000
-#define PHY_ANALOG_BIAS1_PWD_IC25ADC_GET(x) (((x) & 0x01c00000) >> 22)
-#define PHY_ANALOG_BIAS1_PWD_IC25ADC_SET(x) (((x) << 22) & 0x01c00000)
-#define PHY_ANALOG_BIAS1_BIAS_SEL_MSB 31
-#define PHY_ANALOG_BIAS1_BIAS_SEL_LSB 25
-#define PHY_ANALOG_BIAS1_BIAS_SEL_MASK 0xfe000000
-#define PHY_ANALOG_BIAS1_BIAS_SEL_GET(x) (((x) & 0xfe000000) >> 25)
-#define PHY_ANALOG_BIAS1_BIAS_SEL_SET(x) (((x) << 25) & 0xfe000000)
-
-/* macros for BIAS2 */
-#define PHY_ANALOG_BIAS2_ADDRESS 0x000000c4
-#define PHY_ANALOG_BIAS2_OFFSET 0x000000c4
-#define PHY_ANALOG_BIAS2_SPARE2_MSB 4
-#define PHY_ANALOG_BIAS2_SPARE2_LSB 0
-#define PHY_ANALOG_BIAS2_SPARE2_MASK 0x0000001f
-#define PHY_ANALOG_BIAS2_SPARE2_GET(x) (((x) & 0x0000001f) >> 0)
-#define PHY_ANALOG_BIAS2_SPARE2_SET(x) (((x) << 0) & 0x0000001f)
-#define PHY_ANALOG_BIAS2_PWD_IC25XTALREG_MSB 7
-#define PHY_ANALOG_BIAS2_PWD_IC25XTALREG_LSB 5
-#define PHY_ANALOG_BIAS2_PWD_IC25XTALREG_MASK 0x000000e0
-#define PHY_ANALOG_BIAS2_PWD_IC25XTALREG_GET(x) (((x) & 0x000000e0) >> 5)
-#define PHY_ANALOG_BIAS2_PWD_IC25XTALREG_SET(x) (((x) << 5) & 0x000000e0)
-#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_MSB 10
-#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_LSB 8
-#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_MASK 0x00000700
-#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_GET(x) (((x) & 0x00000700) >> 8)
-#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_SET(x) (((x) << 8) & 0x00000700)
-#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_MSB 13
-#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_LSB 11
-#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_MASK 0x00003800
-#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_GET(x) (((x) & 0x00003800) >> 11)
-#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_SET(x) (((x) << 11) & 0x00003800)
-#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_MSB 16
-#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_LSB 14
-#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_MASK 0x0001c000
-#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_GET(x) (((x) & 0x0001c000) >> 14)
-#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_SET(x) (((x) << 14) & 0x0001c000)
-#define PHY_ANALOG_BIAS2_PWD_IC50SYNTH_MSB 19
-#define PHY_ANALOG_BIAS2_PWD_IC50SYNTH_LSB 17
-#define PHY_ANALOG_BIAS2_PWD_IC50SYNTH_MASK 0x000e0000
-#define PHY_ANALOG_BIAS2_PWD_IC50SYNTH_GET(x) (((x) & 0x000e0000) >> 17)
-#define PHY_ANALOG_BIAS2_PWD_IC50SYNTH_SET(x) (((x) << 17) & 0x000e0000)
-#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_MSB 22
-#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_LSB 20
-#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_MASK 0x00700000
-#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_GET(x) (((x) & 0x00700000) >> 20)
-#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_SET(x) (((x) << 20) & 0x00700000)
-#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_MSB 25
-#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_LSB 23
-#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_MASK 0x03800000
-#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_GET(x) (((x) & 0x03800000) >> 23)
-#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_SET(x) (((x) << 23) & 0x03800000)
-#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_MSB 28
-#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_LSB 26
-#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_MASK 0x1c000000
-#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_GET(x) (((x) & 0x1c000000) >> 26)
-#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_SET(x) (((x) << 26) & 0x1c000000)
-#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_MSB 31
-#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_LSB 29
-#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_MASK 0xe0000000
-#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_GET(x) (((x) & 0xe0000000) >> 29)
-#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_SET(x) (((x) << 29) & 0xe0000000)
-
-/* macros for BIAS3 */
-#define PHY_ANALOG_BIAS3_ADDRESS 0x000000c8
-#define PHY_ANALOG_BIAS3_OFFSET 0x000000c8
-#define PHY_ANALOG_BIAS3_SPARE3_MSB 1
-#define PHY_ANALOG_BIAS3_SPARE3_LSB 0
-#define PHY_ANALOG_BIAS3_SPARE3_MASK 0x00000003
-#define PHY_ANALOG_BIAS3_SPARE3_GET(x) (((x) & 0x00000003) >> 0)
-#define PHY_ANALOG_BIAS3_SPARE3_SET(x) (((x) << 0) & 0x00000003)
-#define PHY_ANALOG_BIAS3_PWD_IR25XTALREG_MSB 4
-#define PHY_ANALOG_BIAS3_PWD_IR25XTALREG_LSB 2
-#define PHY_ANALOG_BIAS3_PWD_IR25XTALREG_MASK 0x0000001c
-#define PHY_ANALOG_BIAS3_PWD_IR25XTALREG_GET(x) (((x) & 0x0000001c) >> 2)
-#define PHY_ANALOG_BIAS3_PWD_IR25XTALREG_SET(x) (((x) << 2) & 0x0000001c)
-#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_MSB 7
-#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_LSB 5
-#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_MASK 0x000000e0
-#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_GET(x) (((x) & 0x000000e0) >> 5)
-#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_SET(x) (((x) << 5) & 0x000000e0)
-#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_MSB 10
-#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_LSB 8
-#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_MASK 0x00000700
-#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_GET(x) (((x) & 0x00000700) >> 8)
-#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_SET(x) (((x) << 8) & 0x00000700)
-#define PHY_ANALOG_BIAS3_PWD_IR50SYNTH_MSB 13
-#define PHY_ANALOG_BIAS3_PWD_IR50SYNTH_LSB 11
-#define PHY_ANALOG_BIAS3_PWD_IR50SYNTH_MASK 0x00003800
-#define PHY_ANALOG_BIAS3_PWD_IR50SYNTH_GET(x) (((x) & 0x00003800) >> 11)
-#define PHY_ANALOG_BIAS3_PWD_IR50SYNTH_SET(x) (((x) << 11) & 0x00003800)
-#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_MSB 16
-#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_LSB 14
-#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_MASK 0x0001c000
-#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_GET(x) (((x) & 0x0001c000) >> 14)
-#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_SET(x) (((x) << 14) & 0x0001c000)
-#define PHY_ANALOG_BIAS3_PWD_IR25BB_MSB 19
-#define PHY_ANALOG_BIAS3_PWD_IR25BB_LSB 17
-#define PHY_ANALOG_BIAS3_PWD_IR25BB_MASK 0x000e0000
-#define PHY_ANALOG_BIAS3_PWD_IR25BB_GET(x) (((x) & 0x000e0000) >> 17)
-#define PHY_ANALOG_BIAS3_PWD_IR25BB_SET(x) (((x) << 17) & 0x000e0000)
-#define PHY_ANALOG_BIAS3_PWD_IR50DAC_MSB 22
-#define PHY_ANALOG_BIAS3_PWD_IR50DAC_LSB 20
-#define PHY_ANALOG_BIAS3_PWD_IR50DAC_MASK 0x00700000
-#define PHY_ANALOG_BIAS3_PWD_IR50DAC_GET(x) (((x) & 0x00700000) >> 20)
-#define PHY_ANALOG_BIAS3_PWD_IR50DAC_SET(x) (((x) << 20) & 0x00700000)
-#define PHY_ANALOG_BIAS3_PWD_IR25DAC_MSB 25
-#define PHY_ANALOG_BIAS3_PWD_IR25DAC_LSB 23
-#define PHY_ANALOG_BIAS3_PWD_IR25DAC_MASK 0x03800000
-#define PHY_ANALOG_BIAS3_PWD_IR25DAC_GET(x) (((x) & 0x03800000) >> 23)
-#define PHY_ANALOG_BIAS3_PWD_IR25DAC_SET(x) (((x) << 23) & 0x03800000)
-#define PHY_ANALOG_BIAS3_PWD_IR25FIR_MSB 28
-#define PHY_ANALOG_BIAS3_PWD_IR25FIR_LSB 26
-#define PHY_ANALOG_BIAS3_PWD_IR25FIR_MASK 0x1c000000
-#define PHY_ANALOG_BIAS3_PWD_IR25FIR_GET(x) (((x) & 0x1c000000) >> 26)
-#define PHY_ANALOG_BIAS3_PWD_IR25FIR_SET(x) (((x) << 26) & 0x1c000000)
-#define PHY_ANALOG_BIAS3_PWD_IR50ADC_MSB 31
-#define PHY_ANALOG_BIAS3_PWD_IR50ADC_LSB 29
-#define PHY_ANALOG_BIAS3_PWD_IR50ADC_MASK 0xe0000000
-#define PHY_ANALOG_BIAS3_PWD_IR50ADC_GET(x) (((x) & 0xe0000000) >> 29)
-#define PHY_ANALOG_BIAS3_PWD_IR50ADC_SET(x) (((x) << 29) & 0xe0000000)
-
-/* macros for BIAS4 */
-#define PHY_ANALOG_BIAS4_ADDRESS 0x000000cc
-#define PHY_ANALOG_BIAS4_OFFSET 0x000000cc
-#define PHY_ANALOG_BIAS4_SPARE4_MSB 13
-#define PHY_ANALOG_BIAS4_SPARE4_LSB 0
-#define PHY_ANALOG_BIAS4_SPARE4_MASK 0x00003fff
-#define PHY_ANALOG_BIAS4_SPARE4_GET(x) (((x) & 0x00003fff) >> 0)
-#define PHY_ANALOG_BIAS4_SPARE4_SET(x) (((x) << 0) & 0x00003fff)
-#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_MSB 16
-#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_LSB 14
-#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_MASK 0x0001c000
-#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_GET(x) (((x) & 0x0001c000) >> 14)
-#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_SET(x) (((x) << 14) & 0x0001c000)
-#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_MSB 19
-#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_LSB 17
-#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_MASK 0x000e0000
-#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_GET(x) (((x) & 0x000e0000) >> 17)
-#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_SET(x) (((x) << 17) & 0x000e0000)
-#define PHY_ANALOG_BIAS4_PWD_IR25SPAREA_MSB 22
-#define PHY_ANALOG_BIAS4_PWD_IR25SPAREA_LSB 20
-#define PHY_ANALOG_BIAS4_PWD_IR25SPAREA_MASK 0x00700000
-#define PHY_ANALOG_BIAS4_PWD_IR25SPAREA_GET(x) (((x) & 0x00700000) >> 20)
-#define PHY_ANALOG_BIAS4_PWD_IR25SPAREA_SET(x) (((x) << 20) & 0x00700000)
-#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_MSB 25
-#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_LSB 23
-#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_MASK 0x03800000
-#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_GET(x) (((x) & 0x03800000) >> 23)
-#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_SET(x) (((x) << 23) & 0x03800000)
-#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_MSB 28
-#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_LSB 26
-#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_MASK 0x1c000000
-#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_GET(x) (((x) & 0x1c000000) >> 26)
-#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_SET(x) (((x) << 26) & 0x1c000000)
-#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_MSB 31
-#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_LSB 29
-#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_MASK 0xe0000000
-#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_GET(x) (((x) & 0xe0000000) >> 29)
-#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_SET(x) (((x) << 29) & 0xe0000000)
-
-/* macros for RXTX1 */
-#define PHY_ANALOG_RXTX1_ADDRESS 0x00000100
-#define PHY_ANALOG_RXTX1_OFFSET 0x00000100
-#define PHY_ANALOG_RXTX1_SCFIR_GAIN_MSB 0
-#define PHY_ANALOG_RXTX1_SCFIR_GAIN_LSB 0
-#define PHY_ANALOG_RXTX1_SCFIR_GAIN_MASK 0x00000001
-#define PHY_ANALOG_RXTX1_SCFIR_GAIN_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_ANALOG_RXTX1_SCFIR_GAIN_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_ANALOG_RXTX1_MANRXGAIN_MSB 1
-#define PHY_ANALOG_RXTX1_MANRXGAIN_LSB 1
-#define PHY_ANALOG_RXTX1_MANRXGAIN_MASK 0x00000002
-#define PHY_ANALOG_RXTX1_MANRXGAIN_GET(x) (((x) & 0x00000002) >> 1)
-#define PHY_ANALOG_RXTX1_MANRXGAIN_SET(x) (((x) << 1) & 0x00000002)
-#define PHY_ANALOG_RXTX1_AGC_DBDAC_MSB 5
-#define PHY_ANALOG_RXTX1_AGC_DBDAC_LSB 2
-#define PHY_ANALOG_RXTX1_AGC_DBDAC_MASK 0x0000003c
-#define PHY_ANALOG_RXTX1_AGC_DBDAC_GET(x) (((x) & 0x0000003c) >> 2)
-#define PHY_ANALOG_RXTX1_AGC_DBDAC_SET(x) (((x) << 2) & 0x0000003c)
-#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_MSB 6
-#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_LSB 6
-#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_MASK 0x00000040
-#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_GET(x) (((x) & 0x00000040) >> 6)
-#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_SET(x) (((x) << 6) & 0x00000040)
-#define PHY_ANALOG_RXTX1_ENABLE_PAL_MSB 7
-#define PHY_ANALOG_RXTX1_ENABLE_PAL_LSB 7
-#define PHY_ANALOG_RXTX1_ENABLE_PAL_MASK 0x00000080
-#define PHY_ANALOG_RXTX1_ENABLE_PAL_GET(x) (((x) & 0x00000080) >> 7)
-#define PHY_ANALOG_RXTX1_ENABLE_PAL_SET(x) (((x) << 7) & 0x00000080)
-#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_MSB 8
-#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_LSB 8
-#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_MASK 0x00000100
-#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_GET(x) (((x) & 0x00000100) >> 8)
-#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_SET(x) (((x) << 8) & 0x00000100)
-#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_MSB 11
-#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_LSB 9
-#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_MASK 0x00000e00
-#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_GET(x) (((x) & 0x00000e00) >> 9)
-#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_SET(x) (((x) << 9) & 0x00000e00)
-#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_MSB 13
-#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_LSB 12
-#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_MASK 0x00003000
-#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_GET(x) (((x) & 0x00003000) >> 12)
-#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_SET(x) (((x) << 12) & 0x00003000)
-#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_MSB 14
-#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_LSB 14
-#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_MASK 0x00004000
-#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_GET(x) (((x) & 0x00004000) >> 14)
-#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_SET(x) (((x) << 14) & 0x00004000)
-#define PHY_ANALOG_RXTX1_PADRV2GN_MSB 18
-#define PHY_ANALOG_RXTX1_PADRV2GN_LSB 15
-#define PHY_ANALOG_RXTX1_PADRV2GN_MASK 0x00078000
-#define PHY_ANALOG_RXTX1_PADRV2GN_GET(x) (((x) & 0x00078000) >> 15)
-#define PHY_ANALOG_RXTX1_PADRV2GN_SET(x) (((x) << 15) & 0x00078000)
-#define PHY_ANALOG_RXTX1_PADRV3GN5G_MSB 22
-#define PHY_ANALOG_RXTX1_PADRV3GN5G_LSB 19
-#define PHY_ANALOG_RXTX1_PADRV3GN5G_MASK 0x00780000
-#define PHY_ANALOG_RXTX1_PADRV3GN5G_GET(x) (((x) & 0x00780000) >> 19)
-#define PHY_ANALOG_RXTX1_PADRV3GN5G_SET(x) (((x) << 19) & 0x00780000)
-#define PHY_ANALOG_RXTX1_PADRV4GN5G_MSB 26
-#define PHY_ANALOG_RXTX1_PADRV4GN5G_LSB 23
-#define PHY_ANALOG_RXTX1_PADRV4GN5G_MASK 0x07800000
-#define PHY_ANALOG_RXTX1_PADRV4GN5G_GET(x) (((x) & 0x07800000) >> 23)
-#define PHY_ANALOG_RXTX1_PADRV4GN5G_SET(x) (((x) << 23) & 0x07800000)
-#define PHY_ANALOG_RXTX1_TXBB_GC_MSB 30
-#define PHY_ANALOG_RXTX1_TXBB_GC_LSB 27
-#define PHY_ANALOG_RXTX1_TXBB_GC_MASK 0x78000000
-#define PHY_ANALOG_RXTX1_TXBB_GC_GET(x) (((x) & 0x78000000) >> 27)
-#define PHY_ANALOG_RXTX1_TXBB_GC_SET(x) (((x) << 27) & 0x78000000)
-#define PHY_ANALOG_RXTX1_MANTXGAIN_MSB 31
-#define PHY_ANALOG_RXTX1_MANTXGAIN_LSB 31
-#define PHY_ANALOG_RXTX1_MANTXGAIN_MASK 0x80000000
-#define PHY_ANALOG_RXTX1_MANTXGAIN_GET(x) (((x) & 0x80000000) >> 31)
-#define PHY_ANALOG_RXTX1_MANTXGAIN_SET(x) (((x) << 31) & 0x80000000)
-
-/* macros for RXTX2 */
-#define PHY_ANALOG_RXTX2_ADDRESS 0x00000104
-#define PHY_ANALOG_RXTX2_OFFSET 0x00000104
-#define PHY_ANALOG_RXTX2_BMODE_MSB 0
-#define PHY_ANALOG_RXTX2_BMODE_LSB 0
-#define PHY_ANALOG_RXTX2_BMODE_MASK 0x00000001
-#define PHY_ANALOG_RXTX2_BMODE_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_ANALOG_RXTX2_BMODE_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_ANALOG_RXTX2_BMODE_OVR_MSB 1
-#define PHY_ANALOG_RXTX2_BMODE_OVR_LSB 1
-#define PHY_ANALOG_RXTX2_BMODE_OVR_MASK 0x00000002
-#define PHY_ANALOG_RXTX2_BMODE_OVR_GET(x) (((x) & 0x00000002) >> 1)
-#define PHY_ANALOG_RXTX2_BMODE_OVR_SET(x) (((x) << 1) & 0x00000002)
-#define PHY_ANALOG_RXTX2_SYNTHON_MSB 2
-#define PHY_ANALOG_RXTX2_SYNTHON_LSB 2
-#define PHY_ANALOG_RXTX2_SYNTHON_MASK 0x00000004
-#define PHY_ANALOG_RXTX2_SYNTHON_GET(x) (((x) & 0x00000004) >> 2)
-#define PHY_ANALOG_RXTX2_SYNTHON_SET(x) (((x) << 2) & 0x00000004)
-#define PHY_ANALOG_RXTX2_SYNTHON_OVR_MSB 3
-#define PHY_ANALOG_RXTX2_SYNTHON_OVR_LSB 3
-#define PHY_ANALOG_RXTX2_SYNTHON_OVR_MASK 0x00000008
-#define PHY_ANALOG_RXTX2_SYNTHON_OVR_GET(x) (((x) & 0x00000008) >> 3)
-#define PHY_ANALOG_RXTX2_SYNTHON_OVR_SET(x) (((x) << 3) & 0x00000008)
-#define PHY_ANALOG_RXTX2_BW_ST_MSB 5
-#define PHY_ANALOG_RXTX2_BW_ST_LSB 4
-#define PHY_ANALOG_RXTX2_BW_ST_MASK 0x00000030
-#define PHY_ANALOG_RXTX2_BW_ST_GET(x) (((x) & 0x00000030) >> 4)
-#define PHY_ANALOG_RXTX2_BW_ST_SET(x) (((x) << 4) & 0x00000030)
-#define PHY_ANALOG_RXTX2_BW_ST_OVR_MSB 6
-#define PHY_ANALOG_RXTX2_BW_ST_OVR_LSB 6
-#define PHY_ANALOG_RXTX2_BW_ST_OVR_MASK 0x00000040
-#define PHY_ANALOG_RXTX2_BW_ST_OVR_GET(x) (((x) & 0x00000040) >> 6)
-#define PHY_ANALOG_RXTX2_BW_ST_OVR_SET(x) (((x) << 6) & 0x00000040)
-#define PHY_ANALOG_RXTX2_TXON_MSB 7
-#define PHY_ANALOG_RXTX2_TXON_LSB 7
-#define PHY_ANALOG_RXTX2_TXON_MASK 0x00000080
-#define PHY_ANALOG_RXTX2_TXON_GET(x) (((x) & 0x00000080) >> 7)
-#define PHY_ANALOG_RXTX2_TXON_SET(x) (((x) << 7) & 0x00000080)
-#define PHY_ANALOG_RXTX2_TXON_OVR_MSB 8
-#define PHY_ANALOG_RXTX2_TXON_OVR_LSB 8
-#define PHY_ANALOG_RXTX2_TXON_OVR_MASK 0x00000100
-#define PHY_ANALOG_RXTX2_TXON_OVR_GET(x) (((x) & 0x00000100) >> 8)
-#define PHY_ANALOG_RXTX2_TXON_OVR_SET(x) (((x) << 8) & 0x00000100)
-#define PHY_ANALOG_RXTX2_PAON_MSB 9
-#define PHY_ANALOG_RXTX2_PAON_LSB 9
-#define PHY_ANALOG_RXTX2_PAON_MASK 0x00000200
-#define PHY_ANALOG_RXTX2_PAON_GET(x) (((x) & 0x00000200) >> 9)
-#define PHY_ANALOG_RXTX2_PAON_SET(x) (((x) << 9) & 0x00000200)
-#define PHY_ANALOG_RXTX2_PAON_OVR_MSB 10
-#define PHY_ANALOG_RXTX2_PAON_OVR_LSB 10
-#define PHY_ANALOG_RXTX2_PAON_OVR_MASK 0x00000400
-#define PHY_ANALOG_RXTX2_PAON_OVR_GET(x) (((x) & 0x00000400) >> 10)
-#define PHY_ANALOG_RXTX2_PAON_OVR_SET(x) (((x) << 10) & 0x00000400)
-#define PHY_ANALOG_RXTX2_RXON_MSB 11
-#define PHY_ANALOG_RXTX2_RXON_LSB 11
-#define PHY_ANALOG_RXTX2_RXON_MASK 0x00000800
-#define PHY_ANALOG_RXTX2_RXON_GET(x) (((x) & 0x00000800) >> 11)
-#define PHY_ANALOG_RXTX2_RXON_SET(x) (((x) << 11) & 0x00000800)
-#define PHY_ANALOG_RXTX2_RXON_OVR_MSB 12
-#define PHY_ANALOG_RXTX2_RXON_OVR_LSB 12
-#define PHY_ANALOG_RXTX2_RXON_OVR_MASK 0x00001000
-#define PHY_ANALOG_RXTX2_RXON_OVR_GET(x) (((x) & 0x00001000) >> 12)
-#define PHY_ANALOG_RXTX2_RXON_OVR_SET(x) (((x) << 12) & 0x00001000)
-#define PHY_ANALOG_RXTX2_AGCON_MSB 13
-#define PHY_ANALOG_RXTX2_AGCON_LSB 13
-#define PHY_ANALOG_RXTX2_AGCON_MASK 0x00002000
-#define PHY_ANALOG_RXTX2_AGCON_GET(x) (((x) & 0x00002000) >> 13)
-#define PHY_ANALOG_RXTX2_AGCON_SET(x) (((x) << 13) & 0x00002000)
-#define PHY_ANALOG_RXTX2_AGCON_OVR_MSB 14
-#define PHY_ANALOG_RXTX2_AGCON_OVR_LSB 14
-#define PHY_ANALOG_RXTX2_AGCON_OVR_MASK 0x00004000
-#define PHY_ANALOG_RXTX2_AGCON_OVR_GET(x) (((x) & 0x00004000) >> 14)
-#define PHY_ANALOG_RXTX2_AGCON_OVR_SET(x) (((x) << 14) & 0x00004000)
-#define PHY_ANALOG_RXTX2_TXMOD_MSB 17
-#define PHY_ANALOG_RXTX2_TXMOD_LSB 15
-#define PHY_ANALOG_RXTX2_TXMOD_MASK 0x00038000
-#define PHY_ANALOG_RXTX2_TXMOD_GET(x) (((x) & 0x00038000) >> 15)
-#define PHY_ANALOG_RXTX2_TXMOD_SET(x) (((x) << 15) & 0x00038000)
-#define PHY_ANALOG_RXTX2_TXMOD_OVR_MSB 18
-#define PHY_ANALOG_RXTX2_TXMOD_OVR_LSB 18
-#define PHY_ANALOG_RXTX2_TXMOD_OVR_MASK 0x00040000
-#define PHY_ANALOG_RXTX2_TXMOD_OVR_GET(x) (((x) & 0x00040000) >> 18)
-#define PHY_ANALOG_RXTX2_TXMOD_OVR_SET(x) (((x) << 18) & 0x00040000)
-#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_MSB 21
-#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_LSB 19
-#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_MASK 0x00380000
-#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_GET(x) (((x) & 0x00380000) >> 19)
-#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_SET(x) (((x) << 19) & 0x00380000)
-#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_MSB 23
-#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_LSB 22
-#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_MASK 0x00c00000
-#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_GET(x) (((x) & 0x00c00000) >> 22)
-#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_SET(x) (((x) << 22) & 0x00c00000)
-#define PHY_ANALOG_RXTX2_MXRGAIN_MSB 25
-#define PHY_ANALOG_RXTX2_MXRGAIN_LSB 24
-#define PHY_ANALOG_RXTX2_MXRGAIN_MASK 0x03000000
-#define PHY_ANALOG_RXTX2_MXRGAIN_GET(x) (((x) & 0x03000000) >> 24)
-#define PHY_ANALOG_RXTX2_MXRGAIN_SET(x) (((x) << 24) & 0x03000000)
-#define PHY_ANALOG_RXTX2_VGAGAIN_MSB 28
-#define PHY_ANALOG_RXTX2_VGAGAIN_LSB 26
-#define PHY_ANALOG_RXTX2_VGAGAIN_MASK 0x1c000000
-#define PHY_ANALOG_RXTX2_VGAGAIN_GET(x) (((x) & 0x1c000000) >> 26)
-#define PHY_ANALOG_RXTX2_VGAGAIN_SET(x) (((x) << 26) & 0x1c000000)
-#define PHY_ANALOG_RXTX2_LNAGAIN_MSB 31
-#define PHY_ANALOG_RXTX2_LNAGAIN_LSB 29
-#define PHY_ANALOG_RXTX2_LNAGAIN_MASK 0xe0000000
-#define PHY_ANALOG_RXTX2_LNAGAIN_GET(x) (((x) & 0xe0000000) >> 29)
-#define PHY_ANALOG_RXTX2_LNAGAIN_SET(x) (((x) << 29) & 0xe0000000)
-
-/* macros for RXTX3 */
-#define PHY_ANALOG_RXTX3_ADDRESS 0x00000108
-#define PHY_ANALOG_RXTX3_OFFSET 0x00000108
-#define PHY_ANALOG_RXTX3_SPARE3_MSB 2
-#define PHY_ANALOG_RXTX3_SPARE3_LSB 0
-#define PHY_ANALOG_RXTX3_SPARE3_MASK 0x00000007
-#define PHY_ANALOG_RXTX3_SPARE3_GET(x) (((x) & 0x00000007) >> 0)
-#define PHY_ANALOG_RXTX3_SPARE3_SET(x) (((x) << 0) & 0x00000007)
-#define PHY_ANALOG_RXTX3_DACFULLSCALE_MSB 3
-#define PHY_ANALOG_RXTX3_DACFULLSCALE_LSB 3
-#define PHY_ANALOG_RXTX3_DACFULLSCALE_MASK 0x00000008
-#define PHY_ANALOG_RXTX3_DACFULLSCALE_GET(x) (((x) & 0x00000008) >> 3)
-#define PHY_ANALOG_RXTX3_DACFULLSCALE_SET(x) (((x) << 3) & 0x00000008)
-#define PHY_ANALOG_RXTX3_DACRSTB_MSB 4
-#define PHY_ANALOG_RXTX3_DACRSTB_LSB 4
-#define PHY_ANALOG_RXTX3_DACRSTB_MASK 0x00000010
-#define PHY_ANALOG_RXTX3_DACRSTB_GET(x) (((x) & 0x00000010) >> 4)
-#define PHY_ANALOG_RXTX3_DACRSTB_SET(x) (((x) << 4) & 0x00000010)
-#define PHY_ANALOG_RXTX3_ADDACLOOPBACK_MSB 5
-#define PHY_ANALOG_RXTX3_ADDACLOOPBACK_LSB 5
-#define PHY_ANALOG_RXTX3_ADDACLOOPBACK_MASK 0x00000020
-#define PHY_ANALOG_RXTX3_ADDACLOOPBACK_GET(x) (((x) & 0x00000020) >> 5)
-#define PHY_ANALOG_RXTX3_ADDACLOOPBACK_SET(x) (((x) << 5) & 0x00000020)
-#define PHY_ANALOG_RXTX3_ADCSHORT_MSB 6
-#define PHY_ANALOG_RXTX3_ADCSHORT_LSB 6
-#define PHY_ANALOG_RXTX3_ADCSHORT_MASK 0x00000040
-#define PHY_ANALOG_RXTX3_ADCSHORT_GET(x) (((x) & 0x00000040) >> 6)
-#define PHY_ANALOG_RXTX3_ADCSHORT_SET(x) (((x) << 6) & 0x00000040)
-#define PHY_ANALOG_RXTX3_DACPWD_MSB 7
-#define PHY_ANALOG_RXTX3_DACPWD_LSB 7
-#define PHY_ANALOG_RXTX3_DACPWD_MASK 0x00000080
-#define PHY_ANALOG_RXTX3_DACPWD_GET(x) (((x) & 0x00000080) >> 7)
-#define PHY_ANALOG_RXTX3_DACPWD_SET(x) (((x) << 7) & 0x00000080)
-#define PHY_ANALOG_RXTX3_DACPWD_OVR_MSB 8
-#define PHY_ANALOG_RXTX3_DACPWD_OVR_LSB 8
-#define PHY_ANALOG_RXTX3_DACPWD_OVR_MASK 0x00000100
-#define PHY_ANALOG_RXTX3_DACPWD_OVR_GET(x) (((x) & 0x00000100) >> 8)
-#define PHY_ANALOG_RXTX3_DACPWD_OVR_SET(x) (((x) << 8) & 0x00000100)
-#define PHY_ANALOG_RXTX3_ADCPWD_MSB 9
-#define PHY_ANALOG_RXTX3_ADCPWD_LSB 9
-#define PHY_ANALOG_RXTX3_ADCPWD_MASK 0x00000200
-#define PHY_ANALOG_RXTX3_ADCPWD_GET(x) (((x) & 0x00000200) >> 9)
-#define PHY_ANALOG_RXTX3_ADCPWD_SET(x) (((x) << 9) & 0x00000200)
-#define PHY_ANALOG_RXTX3_ADCPWD_OVR_MSB 10
-#define PHY_ANALOG_RXTX3_ADCPWD_OVR_LSB 10
-#define PHY_ANALOG_RXTX3_ADCPWD_OVR_MASK 0x00000400
-#define PHY_ANALOG_RXTX3_ADCPWD_OVR_GET(x) (((x) & 0x00000400) >> 10)
-#define PHY_ANALOG_RXTX3_ADCPWD_OVR_SET(x) (((x) << 10) & 0x00000400)
-#define PHY_ANALOG_RXTX3_AGC_CALDAC_MSB 16
-#define PHY_ANALOG_RXTX3_AGC_CALDAC_LSB 11
-#define PHY_ANALOG_RXTX3_AGC_CALDAC_MASK 0x0001f800
-#define PHY_ANALOG_RXTX3_AGC_CALDAC_GET(x) (((x) & 0x0001f800) >> 11)
-#define PHY_ANALOG_RXTX3_AGC_CALDAC_SET(x) (((x) << 11) & 0x0001f800)
-#define PHY_ANALOG_RXTX3_AGC_CAL_MSB 17
-#define PHY_ANALOG_RXTX3_AGC_CAL_LSB 17
-#define PHY_ANALOG_RXTX3_AGC_CAL_MASK 0x00020000
-#define PHY_ANALOG_RXTX3_AGC_CAL_GET(x) (((x) & 0x00020000) >> 17)
-#define PHY_ANALOG_RXTX3_AGC_CAL_SET(x) (((x) << 17) & 0x00020000)
-#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_MSB 18
-#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_LSB 18
-#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_MASK 0x00040000
-#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_GET(x) (((x) & 0x00040000) >> 18)
-#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_SET(x) (((x) << 18) & 0x00040000)
-#define PHY_ANALOG_RXTX3_LOFORCEDON_MSB 19
-#define PHY_ANALOG_RXTX3_LOFORCEDON_LSB 19
-#define PHY_ANALOG_RXTX3_LOFORCEDON_MASK 0x00080000
-#define PHY_ANALOG_RXTX3_LOFORCEDON_GET(x) (((x) & 0x00080000) >> 19)
-#define PHY_ANALOG_RXTX3_LOFORCEDON_SET(x) (((x) << 19) & 0x00080000)
-#define PHY_ANALOG_RXTX3_CALRESIDUE_MSB 20
-#define PHY_ANALOG_RXTX3_CALRESIDUE_LSB 20
-#define PHY_ANALOG_RXTX3_CALRESIDUE_MASK 0x00100000
-#define PHY_ANALOG_RXTX3_CALRESIDUE_GET(x) (((x) & 0x00100000) >> 20)
-#define PHY_ANALOG_RXTX3_CALRESIDUE_SET(x) (((x) << 20) & 0x00100000)
-#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_MSB 21
-#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_LSB 21
-#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_MASK 0x00200000
-#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_GET(x) (((x) & 0x00200000) >> 21)
-#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_SET(x) (((x) << 21) & 0x00200000)
-#define PHY_ANALOG_RXTX3_CALFC_MSB 22
-#define PHY_ANALOG_RXTX3_CALFC_LSB 22
-#define PHY_ANALOG_RXTX3_CALFC_MASK 0x00400000
-#define PHY_ANALOG_RXTX3_CALFC_GET(x) (((x) & 0x00400000) >> 22)
-#define PHY_ANALOG_RXTX3_CALFC_SET(x) (((x) << 22) & 0x00400000)
-#define PHY_ANALOG_RXTX3_CALFC_OVR_MSB 23
-#define PHY_ANALOG_RXTX3_CALFC_OVR_LSB 23
-#define PHY_ANALOG_RXTX3_CALFC_OVR_MASK 0x00800000
-#define PHY_ANALOG_RXTX3_CALFC_OVR_GET(x) (((x) & 0x00800000) >> 23)
-#define PHY_ANALOG_RXTX3_CALFC_OVR_SET(x) (((x) << 23) & 0x00800000)
-#define PHY_ANALOG_RXTX3_CALTX_MSB 24
-#define PHY_ANALOG_RXTX3_CALTX_LSB 24
-#define PHY_ANALOG_RXTX3_CALTX_MASK 0x01000000
-#define PHY_ANALOG_RXTX3_CALTX_GET(x) (((x) & 0x01000000) >> 24)
-#define PHY_ANALOG_RXTX3_CALTX_SET(x) (((x) << 24) & 0x01000000)
-#define PHY_ANALOG_RXTX3_CALTX_OVR_MSB 25
-#define PHY_ANALOG_RXTX3_CALTX_OVR_LSB 25
-#define PHY_ANALOG_RXTX3_CALTX_OVR_MASK 0x02000000
-#define PHY_ANALOG_RXTX3_CALTX_OVR_GET(x) (((x) & 0x02000000) >> 25)
-#define PHY_ANALOG_RXTX3_CALTX_OVR_SET(x) (((x) << 25) & 0x02000000)
-#define PHY_ANALOG_RXTX3_CALTXSHIFT_MSB 26
-#define PHY_ANALOG_RXTX3_CALTXSHIFT_LSB 26
-#define PHY_ANALOG_RXTX3_CALTXSHIFT_MASK 0x04000000
-#define PHY_ANALOG_RXTX3_CALTXSHIFT_GET(x) (((x) & 0x04000000) >> 26)
-#define PHY_ANALOG_RXTX3_CALTXSHIFT_SET(x) (((x) << 26) & 0x04000000)
-#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_MSB 27
-#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_LSB 27
-#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_MASK 0x08000000
-#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_GET(x) (((x) & 0x08000000) >> 27)
-#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_SET(x) (((x) << 27) & 0x08000000)
-#define PHY_ANALOG_RXTX3_CALPA_MSB 28
-#define PHY_ANALOG_RXTX3_CALPA_LSB 28
-#define PHY_ANALOG_RXTX3_CALPA_MASK 0x10000000
-#define PHY_ANALOG_RXTX3_CALPA_GET(x) (((x) & 0x10000000) >> 28)
-#define PHY_ANALOG_RXTX3_CALPA_SET(x) (((x) << 28) & 0x10000000)
-#define PHY_ANALOG_RXTX3_CALPA_OVR_MSB 29
-#define PHY_ANALOG_RXTX3_CALPA_OVR_LSB 29
-#define PHY_ANALOG_RXTX3_CALPA_OVR_MASK 0x20000000
-#define PHY_ANALOG_RXTX3_CALPA_OVR_GET(x) (((x) & 0x20000000) >> 29)
-#define PHY_ANALOG_RXTX3_CALPA_OVR_SET(x) (((x) << 29) & 0x20000000)
-#define PHY_ANALOG_RXTX3_SPURON_MSB 30
-#define PHY_ANALOG_RXTX3_SPURON_LSB 30
-#define PHY_ANALOG_RXTX3_SPURON_MASK 0x40000000
-#define PHY_ANALOG_RXTX3_SPURON_GET(x) (((x) & 0x40000000) >> 30)
-#define PHY_ANALOG_RXTX3_SPURON_SET(x) (((x) << 30) & 0x40000000)
-#define PHY_ANALOG_RXTX3_SPURON_OVR_MSB 31
-#define PHY_ANALOG_RXTX3_SPURON_OVR_LSB 31
-#define PHY_ANALOG_RXTX3_SPURON_OVR_MASK 0x80000000
-#define PHY_ANALOG_RXTX3_SPURON_OVR_GET(x) (((x) & 0x80000000) >> 31)
-#define PHY_ANALOG_RXTX3_SPURON_OVR_SET(x) (((x) << 31) & 0x80000000)
-
-/* macros for BB1 */
-#define PHY_ANALOG_BB1_ADDRESS 0x00000140
-#define PHY_ANALOG_BB1_OFFSET 0x00000140
-#define PHY_ANALOG_BB1_I2V_CURR2X_MSB 0
-#define PHY_ANALOG_BB1_I2V_CURR2X_LSB 0
-#define PHY_ANALOG_BB1_I2V_CURR2X_MASK 0x00000001
-#define PHY_ANALOG_BB1_I2V_CURR2X_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_ANALOG_BB1_I2V_CURR2X_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_ANALOG_BB1_ENABLE_LOQ_MSB 1
-#define PHY_ANALOG_BB1_ENABLE_LOQ_LSB 1
-#define PHY_ANALOG_BB1_ENABLE_LOQ_MASK 0x00000002
-#define PHY_ANALOG_BB1_ENABLE_LOQ_GET(x) (((x) & 0x00000002) >> 1)
-#define PHY_ANALOG_BB1_ENABLE_LOQ_SET(x) (((x) << 1) & 0x00000002)
-#define PHY_ANALOG_BB1_FORCE_LOQ_MSB 2
-#define PHY_ANALOG_BB1_FORCE_LOQ_LSB 2
-#define PHY_ANALOG_BB1_FORCE_LOQ_MASK 0x00000004
-#define PHY_ANALOG_BB1_FORCE_LOQ_GET(x) (((x) & 0x00000004) >> 2)
-#define PHY_ANALOG_BB1_FORCE_LOQ_SET(x) (((x) << 2) & 0x00000004)
-#define PHY_ANALOG_BB1_ENABLE_NOTCH_MSB 3
-#define PHY_ANALOG_BB1_ENABLE_NOTCH_LSB 3
-#define PHY_ANALOG_BB1_ENABLE_NOTCH_MASK 0x00000008
-#define PHY_ANALOG_BB1_ENABLE_NOTCH_GET(x) (((x) & 0x00000008) >> 3)
-#define PHY_ANALOG_BB1_ENABLE_NOTCH_SET(x) (((x) << 3) & 0x00000008)
-#define PHY_ANALOG_BB1_FORCE_NOTCH_MSB 4
-#define PHY_ANALOG_BB1_FORCE_NOTCH_LSB 4
-#define PHY_ANALOG_BB1_FORCE_NOTCH_MASK 0x00000010
-#define PHY_ANALOG_BB1_FORCE_NOTCH_GET(x) (((x) & 0x00000010) >> 4)
-#define PHY_ANALOG_BB1_FORCE_NOTCH_SET(x) (((x) << 4) & 0x00000010)
-#define PHY_ANALOG_BB1_ENABLE_BIQUAD_MSB 5
-#define PHY_ANALOG_BB1_ENABLE_BIQUAD_LSB 5
-#define PHY_ANALOG_BB1_ENABLE_BIQUAD_MASK 0x00000020
-#define PHY_ANALOG_BB1_ENABLE_BIQUAD_GET(x) (((x) & 0x00000020) >> 5)
-#define PHY_ANALOG_BB1_ENABLE_BIQUAD_SET(x) (((x) << 5) & 0x00000020)
-#define PHY_ANALOG_BB1_FORCE_BIQUAD_MSB 6
-#define PHY_ANALOG_BB1_FORCE_BIQUAD_LSB 6
-#define PHY_ANALOG_BB1_FORCE_BIQUAD_MASK 0x00000040
-#define PHY_ANALOG_BB1_FORCE_BIQUAD_GET(x) (((x) & 0x00000040) >> 6)
-#define PHY_ANALOG_BB1_FORCE_BIQUAD_SET(x) (((x) << 6) & 0x00000040)
-#define PHY_ANALOG_BB1_ENABLE_OSDAC_MSB 7
-#define PHY_ANALOG_BB1_ENABLE_OSDAC_LSB 7
-#define PHY_ANALOG_BB1_ENABLE_OSDAC_MASK 0x00000080
-#define PHY_ANALOG_BB1_ENABLE_OSDAC_GET(x) (((x) & 0x00000080) >> 7)
-#define PHY_ANALOG_BB1_ENABLE_OSDAC_SET(x) (((x) << 7) & 0x00000080)
-#define PHY_ANALOG_BB1_FORCE_OSDAC_MSB 8
-#define PHY_ANALOG_BB1_FORCE_OSDAC_LSB 8
-#define PHY_ANALOG_BB1_FORCE_OSDAC_MASK 0x00000100
-#define PHY_ANALOG_BB1_FORCE_OSDAC_GET(x) (((x) & 0x00000100) >> 8)
-#define PHY_ANALOG_BB1_FORCE_OSDAC_SET(x) (((x) << 8) & 0x00000100)
-#define PHY_ANALOG_BB1_ENABLE_V2I_MSB 9
-#define PHY_ANALOG_BB1_ENABLE_V2I_LSB 9
-#define PHY_ANALOG_BB1_ENABLE_V2I_MASK 0x00000200
-#define PHY_ANALOG_BB1_ENABLE_V2I_GET(x) (((x) & 0x00000200) >> 9)
-#define PHY_ANALOG_BB1_ENABLE_V2I_SET(x) (((x) << 9) & 0x00000200)
-#define PHY_ANALOG_BB1_FORCE_V2I_MSB 10
-#define PHY_ANALOG_BB1_FORCE_V2I_LSB 10
-#define PHY_ANALOG_BB1_FORCE_V2I_MASK 0x00000400
-#define PHY_ANALOG_BB1_FORCE_V2I_GET(x) (((x) & 0x00000400) >> 10)
-#define PHY_ANALOG_BB1_FORCE_V2I_SET(x) (((x) << 10) & 0x00000400)
-#define PHY_ANALOG_BB1_ENABLE_I2V_MSB 11
-#define PHY_ANALOG_BB1_ENABLE_I2V_LSB 11
-#define PHY_ANALOG_BB1_ENABLE_I2V_MASK 0x00000800
-#define PHY_ANALOG_BB1_ENABLE_I2V_GET(x) (((x) & 0x00000800) >> 11)
-#define PHY_ANALOG_BB1_ENABLE_I2V_SET(x) (((x) << 11) & 0x00000800)
-#define PHY_ANALOG_BB1_FORCE_I2V_MSB 12
-#define PHY_ANALOG_BB1_FORCE_I2V_LSB 12
-#define PHY_ANALOG_BB1_FORCE_I2V_MASK 0x00001000
-#define PHY_ANALOG_BB1_FORCE_I2V_GET(x) (((x) & 0x00001000) >> 12)
-#define PHY_ANALOG_BB1_FORCE_I2V_SET(x) (((x) << 12) & 0x00001000)
-#define PHY_ANALOG_BB1_CMSEL_MSB 15
-#define PHY_ANALOG_BB1_CMSEL_LSB 13
-#define PHY_ANALOG_BB1_CMSEL_MASK 0x0000e000
-#define PHY_ANALOG_BB1_CMSEL_GET(x) (((x) & 0x0000e000) >> 13)
-#define PHY_ANALOG_BB1_CMSEL_SET(x) (((x) << 13) & 0x0000e000)
-#define PHY_ANALOG_BB1_ATBSEL_MSB 17
-#define PHY_ANALOG_BB1_ATBSEL_LSB 16
-#define PHY_ANALOG_BB1_ATBSEL_MASK 0x00030000
-#define PHY_ANALOG_BB1_ATBSEL_GET(x) (((x) & 0x00030000) >> 16)
-#define PHY_ANALOG_BB1_ATBSEL_SET(x) (((x) << 16) & 0x00030000)
-#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_MSB 18
-#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_LSB 18
-#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_MASK 0x00040000
-#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_GET(x) (((x) & 0x00040000) >> 18)
-#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_SET(x) (((x) << 18) & 0x00040000)
-#define PHY_ANALOG_BB1_OFSTCORRI2VQ_MSB 23
-#define PHY_ANALOG_BB1_OFSTCORRI2VQ_LSB 19
-#define PHY_ANALOG_BB1_OFSTCORRI2VQ_MASK 0x00f80000
-#define PHY_ANALOG_BB1_OFSTCORRI2VQ_GET(x) (((x) & 0x00f80000) >> 19)
-#define PHY_ANALOG_BB1_OFSTCORRI2VQ_SET(x) (((x) << 19) & 0x00f80000)
-#define PHY_ANALOG_BB1_OFSTCORRI2VI_MSB 28
-#define PHY_ANALOG_BB1_OFSTCORRI2VI_LSB 24
-#define PHY_ANALOG_BB1_OFSTCORRI2VI_MASK 0x1f000000
-#define PHY_ANALOG_BB1_OFSTCORRI2VI_GET(x) (((x) & 0x1f000000) >> 24)
-#define PHY_ANALOG_BB1_OFSTCORRI2VI_SET(x) (((x) << 24) & 0x1f000000)
-#define PHY_ANALOG_BB1_LOCALOFFSET_MSB 29
-#define PHY_ANALOG_BB1_LOCALOFFSET_LSB 29
-#define PHY_ANALOG_BB1_LOCALOFFSET_MASK 0x20000000
-#define PHY_ANALOG_BB1_LOCALOFFSET_GET(x) (((x) & 0x20000000) >> 29)
-#define PHY_ANALOG_BB1_LOCALOFFSET_SET(x) (((x) << 29) & 0x20000000)
-#define PHY_ANALOG_BB1_RANGE_OSDAC_MSB 31
-#define PHY_ANALOG_BB1_RANGE_OSDAC_LSB 30
-#define PHY_ANALOG_BB1_RANGE_OSDAC_MASK 0xc0000000
-#define PHY_ANALOG_BB1_RANGE_OSDAC_GET(x) (((x) & 0xc0000000) >> 30)
-#define PHY_ANALOG_BB1_RANGE_OSDAC_SET(x) (((x) << 30) & 0xc0000000)
-
-/* macros for BB2 */
-#define PHY_ANALOG_BB2_ADDRESS 0x00000144
-#define PHY_ANALOG_BB2_OFFSET 0x00000144
-#define PHY_ANALOG_BB2_SPARE_MSB 6
-#define PHY_ANALOG_BB2_SPARE_LSB 0
-#define PHY_ANALOG_BB2_SPARE_MASK 0x0000007f
-#define PHY_ANALOG_BB2_SPARE_GET(x) (((x) & 0x0000007f) >> 0)
-#define PHY_ANALOG_BB2_SPARE_SET(x) (((x) << 0) & 0x0000007f)
-#define PHY_ANALOG_BB2_SEL_TEST_MSB 9
-#define PHY_ANALOG_BB2_SEL_TEST_LSB 7
-#define PHY_ANALOG_BB2_SEL_TEST_MASK 0x00000380
-#define PHY_ANALOG_BB2_SEL_TEST_GET(x) (((x) & 0x00000380) >> 7)
-#define PHY_ANALOG_BB2_SEL_TEST_SET(x) (((x) << 7) & 0x00000380)
-#define PHY_ANALOG_BB2_SCFIR_CAP_MSB 14
-#define PHY_ANALOG_BB2_SCFIR_CAP_LSB 10
-#define PHY_ANALOG_BB2_SCFIR_CAP_MASK 0x00007c00
-#define PHY_ANALOG_BB2_SCFIR_CAP_GET(x) (((x) & 0x00007c00) >> 10)
-#define PHY_ANALOG_BB2_SCFIR_CAP_SET(x) (((x) << 10) & 0x00007c00)
-#define PHY_ANALOG_BB2_OVERRIDE_SCFIR_CAP_MSB 15
-#define PHY_ANALOG_BB2_OVERRIDE_SCFIR_CAP_LSB 15
-#define PHY_ANALOG_BB2_OVERRIDE_SCFIR_CAP_MASK 0x00008000
-#define PHY_ANALOG_BB2_OVERRIDE_SCFIR_CAP_GET(x) (((x) & 0x00008000) >> 15)
-#define PHY_ANALOG_BB2_OVERRIDE_SCFIR_CAP_SET(x) (((x) << 15) & 0x00008000)
-#define PHY_ANALOG_BB2_FNOTCH_MSB 19
-#define PHY_ANALOG_BB2_FNOTCH_LSB 16
-#define PHY_ANALOG_BB2_FNOTCH_MASK 0x000f0000
-#define PHY_ANALOG_BB2_FNOTCH_GET(x) (((x) & 0x000f0000) >> 16)
-#define PHY_ANALOG_BB2_FNOTCH_SET(x) (((x) << 16) & 0x000f0000)
-#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_MSB 20
-#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_LSB 20
-#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_MASK 0x00100000
-#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_GET(x) (((x) & 0x00100000) >> 20)
-#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_SET(x) (((x) << 20) & 0x00100000)
-#define PHY_ANALOG_BB2_FILTERFC_MSB 25
-#define PHY_ANALOG_BB2_FILTERFC_LSB 21
-#define PHY_ANALOG_BB2_FILTERFC_MASK 0x03e00000
-#define PHY_ANALOG_BB2_FILTERFC_GET(x) (((x) & 0x03e00000) >> 21)
-#define PHY_ANALOG_BB2_FILTERFC_SET(x) (((x) << 21) & 0x03e00000)
-#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_MSB 26
-#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_LSB 26
-#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_MASK 0x04000000
-#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_GET(x) (((x) & 0x04000000) >> 26)
-#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_SET(x) (((x) << 26) & 0x04000000)
-#define PHY_ANALOG_BB2_I2V2RXOUT_EN_MSB 27
-#define PHY_ANALOG_BB2_I2V2RXOUT_EN_LSB 27
-#define PHY_ANALOG_BB2_I2V2RXOUT_EN_MASK 0x08000000
-#define PHY_ANALOG_BB2_I2V2RXOUT_EN_GET(x) (((x) & 0x08000000) >> 27)
-#define PHY_ANALOG_BB2_I2V2RXOUT_EN_SET(x) (((x) << 27) & 0x08000000)
-#define PHY_ANALOG_BB2_BQ2RXOUT_EN_MSB 28
-#define PHY_ANALOG_BB2_BQ2RXOUT_EN_LSB 28
-#define PHY_ANALOG_BB2_BQ2RXOUT_EN_MASK 0x10000000
-#define PHY_ANALOG_BB2_BQ2RXOUT_EN_GET(x) (((x) & 0x10000000) >> 28)
-#define PHY_ANALOG_BB2_BQ2RXOUT_EN_SET(x) (((x) << 28) & 0x10000000)
-#define PHY_ANALOG_BB2_RXIN2I2V_EN_MSB 29
-#define PHY_ANALOG_BB2_RXIN2I2V_EN_LSB 29
-#define PHY_ANALOG_BB2_RXIN2I2V_EN_MASK 0x20000000
-#define PHY_ANALOG_BB2_RXIN2I2V_EN_GET(x) (((x) & 0x20000000) >> 29)
-#define PHY_ANALOG_BB2_RXIN2I2V_EN_SET(x) (((x) << 29) & 0x20000000)
-#define PHY_ANALOG_BB2_RXIN2BQ_EN_MSB 30
-#define PHY_ANALOG_BB2_RXIN2BQ_EN_LSB 30
-#define PHY_ANALOG_BB2_RXIN2BQ_EN_MASK 0x40000000
-#define PHY_ANALOG_BB2_RXIN2BQ_EN_GET(x) (((x) & 0x40000000) >> 30)
-#define PHY_ANALOG_BB2_RXIN2BQ_EN_SET(x) (((x) << 30) & 0x40000000)
-#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_MSB 31
-#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_LSB 31
-#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_MASK 0x80000000
-#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_GET(x) (((x) & 0x80000000) >> 31)
-#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_SET(x) (((x) << 31) & 0x80000000)
-
-/* macros for TOP1 */
-#define PHY_ANALOG_TOP1_ADDRESS 0x00000280
-#define PHY_ANALOG_TOP1_OFFSET 0x00000280
-#define PHY_ANALOG_TOP1_SEL_KVCO_MSB 1
-#define PHY_ANALOG_TOP1_SEL_KVCO_LSB 0
-#define PHY_ANALOG_TOP1_SEL_KVCO_MASK 0x00000003
-#define PHY_ANALOG_TOP1_SEL_KVCO_GET(x) (((x) & 0x00000003) >> 0)
-#define PHY_ANALOG_TOP1_SEL_KVCO_SET(x) (((x) << 0) & 0x00000003)
-#define PHY_ANALOG_TOP1_PLLATB_MSB 3
-#define PHY_ANALOG_TOP1_PLLATB_LSB 2
-#define PHY_ANALOG_TOP1_PLLATB_MASK 0x0000000c
-#define PHY_ANALOG_TOP1_PLLATB_GET(x) (((x) & 0x0000000c) >> 2)
-#define PHY_ANALOG_TOP1_PLLATB_SET(x) (((x) << 2) & 0x0000000c)
-#define PHY_ANALOG_TOP1_PLL_SVREG_MSB 4
-#define PHY_ANALOG_TOP1_PLL_SVREG_LSB 4
-#define PHY_ANALOG_TOP1_PLL_SVREG_MASK 0x00000010
-#define PHY_ANALOG_TOP1_PLL_SVREG_GET(x) (((x) & 0x00000010) >> 4)
-#define PHY_ANALOG_TOP1_PLL_SVREG_SET(x) (((x) << 4) & 0x00000010)
-#define PHY_ANALOG_TOP1_HI_FREQ_EN_MSB 5
-#define PHY_ANALOG_TOP1_HI_FREQ_EN_LSB 5
-#define PHY_ANALOG_TOP1_HI_FREQ_EN_MASK 0x00000020
-#define PHY_ANALOG_TOP1_HI_FREQ_EN_GET(x) (((x) & 0x00000020) >> 5)
-#define PHY_ANALOG_TOP1_HI_FREQ_EN_SET(x) (((x) << 5) & 0x00000020)
-#define PHY_ANALOG_TOP1_PWDPLL_MSB 6
-#define PHY_ANALOG_TOP1_PWDPLL_LSB 6
-#define PHY_ANALOG_TOP1_PWDPLL_MASK 0x00000040
-#define PHY_ANALOG_TOP1_PWDPLL_GET(x) (((x) & 0x00000040) >> 6)
-#define PHY_ANALOG_TOP1_PWDPLL_SET(x) (((x) << 6) & 0x00000040)
-#define PHY_ANALOG_TOP1_PWDEXTCLKBUF_MSB 7
-#define PHY_ANALOG_TOP1_PWDEXTCLKBUF_LSB 7
-#define PHY_ANALOG_TOP1_PWDEXTCLKBUF_MASK 0x00000080
-#define PHY_ANALOG_TOP1_PWDEXTCLKBUF_GET(x) (((x) & 0x00000080) >> 7)
-#define PHY_ANALOG_TOP1_PWDEXTCLKBUF_SET(x) (((x) << 7) & 0x00000080)
-#define PHY_ANALOG_TOP1_ADCPWD_PHASE_MSB 9
-#define PHY_ANALOG_TOP1_ADCPWD_PHASE_LSB 8
-#define PHY_ANALOG_TOP1_ADCPWD_PHASE_MASK 0x00000300
-#define PHY_ANALOG_TOP1_ADCPWD_PHASE_GET(x) (((x) & 0x00000300) >> 8)
-#define PHY_ANALOG_TOP1_ADCPWD_PHASE_SET(x) (((x) << 8) & 0x00000300)
-#define PHY_ANALOG_TOP1_ADCCLK_PHASE_MSB 11
-#define PHY_ANALOG_TOP1_ADCCLK_PHASE_LSB 10
-#define PHY_ANALOG_TOP1_ADCCLK_PHASE_MASK 0x00000c00
-#define PHY_ANALOG_TOP1_ADCCLK_PHASE_GET(x) (((x) & 0x00000c00) >> 10)
-#define PHY_ANALOG_TOP1_ADCCLK_PHASE_SET(x) (((x) << 10) & 0x00000c00)
-#define PHY_ANALOG_TOP1_DAC_CLK_SEL_MSB 13
-#define PHY_ANALOG_TOP1_DAC_CLK_SEL_LSB 12
-#define PHY_ANALOG_TOP1_DAC_CLK_SEL_MASK 0x00003000
-#define PHY_ANALOG_TOP1_DAC_CLK_SEL_GET(x) (((x) & 0x00003000) >> 12)
-#define PHY_ANALOG_TOP1_DAC_CLK_SEL_SET(x) (((x) << 12) & 0x00003000)
-#define PHY_ANALOG_TOP1_ADC_CLK_SEL_MSB 15
-#define PHY_ANALOG_TOP1_ADC_CLK_SEL_LSB 14
-#define PHY_ANALOG_TOP1_ADC_CLK_SEL_MASK 0x0000c000
-#define PHY_ANALOG_TOP1_ADC_CLK_SEL_GET(x) (((x) & 0x0000c000) >> 14)
-#define PHY_ANALOG_TOP1_ADC_CLK_SEL_SET(x) (((x) << 14) & 0x0000c000)
-#define PHY_ANALOG_TOP1_REFDIV_MSB 19
-#define PHY_ANALOG_TOP1_REFDIV_LSB 16
-#define PHY_ANALOG_TOP1_REFDIV_MASK 0x000f0000
-#define PHY_ANALOG_TOP1_REFDIV_GET(x) (((x) & 0x000f0000) >> 16)
-#define PHY_ANALOG_TOP1_REFDIV_SET(x) (((x) << 16) & 0x000f0000)
-#define PHY_ANALOG_TOP1_DIV_MSB 29
-#define PHY_ANALOG_TOP1_DIV_LSB 20
-#define PHY_ANALOG_TOP1_DIV_MASK 0x3ff00000
-#define PHY_ANALOG_TOP1_DIV_GET(x) (((x) & 0x3ff00000) >> 20)
-#define PHY_ANALOG_TOP1_DIV_SET(x) (((x) << 20) & 0x3ff00000)
-#define PHY_ANALOG_TOP1_PLLBYPASS_MSB 30
-#define PHY_ANALOG_TOP1_PLLBYPASS_LSB 30
-#define PHY_ANALOG_TOP1_PLLBYPASS_MASK 0x40000000
-#define PHY_ANALOG_TOP1_PLLBYPASS_GET(x) (((x) & 0x40000000) >> 30)
-#define PHY_ANALOG_TOP1_PLLBYPASS_SET(x) (((x) << 30) & 0x40000000)
-#define PHY_ANALOG_TOP1_CLKMOD_RSTB_MSB 31
-#define PHY_ANALOG_TOP1_CLKMOD_RSTB_LSB 31
-#define PHY_ANALOG_TOP1_CLKMOD_RSTB_MASK 0x80000000
-#define PHY_ANALOG_TOP1_CLKMOD_RSTB_GET(x) (((x) & 0x80000000) >> 31)
-#define PHY_ANALOG_TOP1_CLKMOD_RSTB_SET(x) (((x) << 31) & 0x80000000)
-
-/* macros for TOP2 */
-#define PHY_ANALOG_TOP2_ADDRESS 0x00000284
-#define PHY_ANALOG_TOP2_OFFSET 0x00000284
-#define PHY_ANALOG_TOP2_PLL_LOWLEAK_MSB 0
-#define PHY_ANALOG_TOP2_PLL_LOWLEAK_LSB 0
-#define PHY_ANALOG_TOP2_PLL_LOWLEAK_MASK 0x00000001
-#define PHY_ANALOG_TOP2_PLL_LOWLEAK_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_ANALOG_TOP2_PLL_LOWLEAK_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_ANALOG_TOP2_PLL_LEAK_MSB 4
-#define PHY_ANALOG_TOP2_PLL_LEAK_LSB 1
-#define PHY_ANALOG_TOP2_PLL_LEAK_MASK 0x0000001e
-#define PHY_ANALOG_TOP2_PLL_LEAK_GET(x) (((x) & 0x0000001e) >> 1)
-#define PHY_ANALOG_TOP2_PLL_LEAK_SET(x) (((x) << 1) & 0x0000001e)
-#define PHY_ANALOG_TOP2_PLLFRAC_MSB 19
-#define PHY_ANALOG_TOP2_PLLFRAC_LSB 5
-#define PHY_ANALOG_TOP2_PLLFRAC_MASK 0x000fffe0
-#define PHY_ANALOG_TOP2_PLLFRAC_GET(x) (((x) & 0x000fffe0) >> 5)
-#define PHY_ANALOG_TOP2_PLLFRAC_SET(x) (((x) << 5) & 0x000fffe0)
-#define PHY_ANALOG_TOP2_PWD_PLLSDM_MSB 20
-#define PHY_ANALOG_TOP2_PWD_PLLSDM_LSB 20
-#define PHY_ANALOG_TOP2_PWD_PLLSDM_MASK 0x00100000
-#define PHY_ANALOG_TOP2_PWD_PLLSDM_GET(x) (((x) & 0x00100000) >> 20)
-#define PHY_ANALOG_TOP2_PWD_PLLSDM_SET(x) (((x) << 20) & 0x00100000)
-#define PHY_ANALOG_TOP2_PLLICP_MSB 23
-#define PHY_ANALOG_TOP2_PLLICP_LSB 21
-#define PHY_ANALOG_TOP2_PLLICP_MASK 0x00e00000
-#define PHY_ANALOG_TOP2_PLLICP_GET(x) (((x) & 0x00e00000) >> 21)
-#define PHY_ANALOG_TOP2_PLLICP_SET(x) (((x) << 21) & 0x00e00000)
-#define PHY_ANALOG_TOP2_PLLFILTER_MSB 31
-#define PHY_ANALOG_TOP2_PLLFILTER_LSB 24
-#define PHY_ANALOG_TOP2_PLLFILTER_MASK 0xff000000
-#define PHY_ANALOG_TOP2_PLLFILTER_GET(x) (((x) & 0xff000000) >> 24)
-#define PHY_ANALOG_TOP2_PLLFILTER_SET(x) (((x) << 24) & 0xff000000)
-
-/* macros for TOP3 */
-#define PHY_ANALOG_TOP3_ADDRESS 0x00000288
-#define PHY_ANALOG_TOP3_OFFSET 0x00000288
-#define PHY_ANALOG_TOP3_INT2GND_MSB 0
-#define PHY_ANALOG_TOP3_INT2GND_LSB 0
-#define PHY_ANALOG_TOP3_INT2GND_MASK 0x00000001
-#define PHY_ANALOG_TOP3_INT2GND_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_ANALOG_TOP3_INT2GND_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_ANALOG_TOP3_PWDPALCLK_MSB 1
-#define PHY_ANALOG_TOP3_PWDPALCLK_LSB 1
-#define PHY_ANALOG_TOP3_PWDPALCLK_MASK 0x00000002
-#define PHY_ANALOG_TOP3_PWDPALCLK_GET(x) (((x) & 0x00000002) >> 1)
-#define PHY_ANALOG_TOP3_PWDPALCLK_SET(x) (((x) << 1) & 0x00000002)
-#define PHY_ANALOG_TOP3_PWDAGCCLK_MSB 2
-#define PHY_ANALOG_TOP3_PWDAGCCLK_LSB 2
-#define PHY_ANALOG_TOP3_PWDAGCCLK_MASK 0x00000004
-#define PHY_ANALOG_TOP3_PWDAGCCLK_GET(x) (((x) & 0x00000004) >> 2)
-#define PHY_ANALOG_TOP3_PWDAGCCLK_SET(x) (((x) << 2) & 0x00000004)
-#define PHY_ANALOG_TOP3_PWDV2I_MSB 3
-#define PHY_ANALOG_TOP3_PWDV2I_LSB 3
-#define PHY_ANALOG_TOP3_PWDV2I_MASK 0x00000008
-#define PHY_ANALOG_TOP3_PWDV2I_GET(x) (((x) & 0x00000008) >> 3)
-#define PHY_ANALOG_TOP3_PWDV2I_SET(x) (((x) << 3) & 0x00000008)
-#define PHY_ANALOG_TOP3_PWDBIAS_MSB 4
-#define PHY_ANALOG_TOP3_PWDBIAS_LSB 4
-#define PHY_ANALOG_TOP3_PWDBIAS_MASK 0x00000010
-#define PHY_ANALOG_TOP3_PWDBIAS_GET(x) (((x) & 0x00000010) >> 4)
-#define PHY_ANALOG_TOP3_PWDBIAS_SET(x) (((x) << 4) & 0x00000010)
-#define PHY_ANALOG_TOP3_PWDBG_MSB 5
-#define PHY_ANALOG_TOP3_PWDBG_LSB 5
-#define PHY_ANALOG_TOP3_PWDBG_MASK 0x00000020
-#define PHY_ANALOG_TOP3_PWDBG_GET(x) (((x) & 0x00000020) >> 5)
-#define PHY_ANALOG_TOP3_PWDBG_SET(x) (((x) << 5) & 0x00000020)
-#define PHY_ANALOG_TOP3_XTAL_SELVREG_MSB 6
-#define PHY_ANALOG_TOP3_XTAL_SELVREG_LSB 6
-#define PHY_ANALOG_TOP3_XTAL_SELVREG_MASK 0x00000040
-#define PHY_ANALOG_TOP3_XTAL_SELVREG_GET(x) (((x) & 0x00000040) >> 6)
-#define PHY_ANALOG_TOP3_XTAL_SELVREG_SET(x) (((x) << 6) & 0x00000040)
-#define PHY_ANALOG_TOP3_XTAL_PWDREG_MSB 7
-#define PHY_ANALOG_TOP3_XTAL_PWDREG_LSB 7
-#define PHY_ANALOG_TOP3_XTAL_PWDREG_MASK 0x00000080
-#define PHY_ANALOG_TOP3_XTAL_PWDREG_GET(x) (((x) & 0x00000080) >> 7)
-#define PHY_ANALOG_TOP3_XTAL_PWDREG_SET(x) (((x) << 7) & 0x00000080)
-#define PHY_ANALOG_TOP3_XTAL_PWDCLKIN_MSB 8
-#define PHY_ANALOG_TOP3_XTAL_PWDCLKIN_LSB 8
-#define PHY_ANALOG_TOP3_XTAL_PWDCLKIN_MASK 0x00000100
-#define PHY_ANALOG_TOP3_XTAL_PWDCLKIN_GET(x) (((x) & 0x00000100) >> 8)
-#define PHY_ANALOG_TOP3_XTAL_PWDCLKIN_SET(x) (((x) << 8) & 0x00000100)
-#define PHY_ANALOG_TOP3_XTAL_PWDCLKD_MSB 9
-#define PHY_ANALOG_TOP3_XTAL_PWDCLKD_LSB 9
-#define PHY_ANALOG_TOP3_XTAL_PWDCLKD_MASK 0x00000200
-#define PHY_ANALOG_TOP3_XTAL_PWDCLKD_GET(x) (((x) & 0x00000200) >> 9)
-#define PHY_ANALOG_TOP3_XTAL_PWDCLKD_SET(x) (((x) << 9) & 0x00000200)
-#define PHY_ANALOG_TOP3_XTAL_OSCON_MSB 10
-#define PHY_ANALOG_TOP3_XTAL_OSCON_LSB 10
-#define PHY_ANALOG_TOP3_XTAL_OSCON_MASK 0x00000400
-#define PHY_ANALOG_TOP3_XTAL_OSCON_GET(x) (((x) & 0x00000400) >> 10)
-#define PHY_ANALOG_TOP3_XTAL_OSCON_SET(x) (((x) << 10) & 0x00000400)
-#define PHY_ANALOG_TOP3_XTAL_NOTCXODET_MSB 11
-#define PHY_ANALOG_TOP3_XTAL_NOTCXODET_LSB 11
-#define PHY_ANALOG_TOP3_XTAL_NOTCXODET_MASK 0x00000800
-#define PHY_ANALOG_TOP3_XTAL_NOTCXODET_GET(x) (((x) & 0x00000800) >> 11)
-#define PHY_ANALOG_TOP3_XTAL_NOTCXODET_SET(x) (((x) << 11) & 0x00000800)
-#define PHY_ANALOG_TOP3_XTAL_LOCALBIAS_MSB 12
-#define PHY_ANALOG_TOP3_XTAL_LOCALBIAS_LSB 12
-#define PHY_ANALOG_TOP3_XTAL_LOCALBIAS_MASK 0x00001000
-#define PHY_ANALOG_TOP3_XTAL_LOCALBIAS_GET(x) (((x) & 0x00001000) >> 12)
-#define PHY_ANALOG_TOP3_XTAL_LOCALBIAS_SET(x) (((x) << 12) & 0x00001000)
-#define PHY_ANALOG_TOP3_XTAL_HIGHZ_MSB 13
-#define PHY_ANALOG_TOP3_XTAL_HIGHZ_LSB 13
-#define PHY_ANALOG_TOP3_XTAL_HIGHZ_MASK 0x00002000
-#define PHY_ANALOG_TOP3_XTAL_HIGHZ_GET(x) (((x) & 0x00002000) >> 13)
-#define PHY_ANALOG_TOP3_XTAL_HIGHZ_SET(x) (((x) << 13) & 0x00002000)
-#define PHY_ANALOG_TOP3_XTAL_DRVPNR_MSB 15
-#define PHY_ANALOG_TOP3_XTAL_DRVPNR_LSB 14
-#define PHY_ANALOG_TOP3_XTAL_DRVPNR_MASK 0x0000c000
-#define PHY_ANALOG_TOP3_XTAL_DRVPNR_GET(x) (((x) & 0x0000c000) >> 14)
-#define PHY_ANALOG_TOP3_XTAL_DRVPNR_SET(x) (((x) << 14) & 0x0000c000)
-#define PHY_ANALOG_TOP3_XTALCAPOUTDAC_MSB 22
-#define PHY_ANALOG_TOP3_XTALCAPOUTDAC_LSB 16
-#define PHY_ANALOG_TOP3_XTALCAPOUTDAC_MASK 0x007f0000
-#define PHY_ANALOG_TOP3_XTALCAPOUTDAC_GET(x) (((x) & 0x007f0000) >> 16)
-#define PHY_ANALOG_TOP3_XTALCAPOUTDAC_SET(x) (((x) << 16) & 0x007f0000)
-#define PHY_ANALOG_TOP3_XTAL_CAPINDAC_MSB 29
-#define PHY_ANALOG_TOP3_XTAL_CAPINDAC_LSB 23
-#define PHY_ANALOG_TOP3_XTAL_CAPINDAC_MASK 0x3f800000
-#define PHY_ANALOG_TOP3_XTAL_CAPINDAC_GET(x) (((x) & 0x3f800000) >> 23)
-#define PHY_ANALOG_TOP3_XTAL_CAPINDAC_SET(x) (((x) << 23) & 0x3f800000)
-#define PHY_ANALOG_TOP3_XTAL_BIAS2X_MSB 30
-#define PHY_ANALOG_TOP3_XTAL_BIAS2X_LSB 30
-#define PHY_ANALOG_TOP3_XTAL_BIAS2X_MASK 0x40000000
-#define PHY_ANALOG_TOP3_XTAL_BIAS2X_GET(x) (((x) & 0x40000000) >> 30)
-#define PHY_ANALOG_TOP3_XTAL_BIAS2X_SET(x) (((x) << 30) & 0x40000000)
-#define PHY_ANALOG_TOP3_TCXODET_MSB 31
-#define PHY_ANALOG_TOP3_TCXODET_LSB 31
-#define PHY_ANALOG_TOP3_TCXODET_MASK 0x80000000
-#define PHY_ANALOG_TOP3_TCXODET_GET(x) (((x) & 0x80000000) >> 31)
-
-/* macros for TOP4 */
-#define PHY_ANALOG_TOP4_ADDRESS 0x0000028c
-#define PHY_ANALOG_TOP4_OFFSET 0x0000028c
-#define PHY_ANALOG_TOP4_SPARE4_MSB 19
-#define PHY_ANALOG_TOP4_SPARE4_LSB 0
-#define PHY_ANALOG_TOP4_SPARE4_MASK 0x000fffff
-#define PHY_ANALOG_TOP4_SPARE4_GET(x) (((x) & 0x000fffff) >> 0)
-#define PHY_ANALOG_TOP4_SPARE4_SET(x) (((x) << 0) & 0x000fffff)
-#define PHY_ANALOG_TOP4_SEL_TEMPSENSOR_MSB 20
-#define PHY_ANALOG_TOP4_SEL_TEMPSENSOR_LSB 20
-#define PHY_ANALOG_TOP4_SEL_TEMPSENSOR_MASK 0x00100000
-#define PHY_ANALOG_TOP4_SEL_TEMPSENSOR_GET(x) (((x) & 0x00100000) >> 20)
-#define PHY_ANALOG_TOP4_SEL_TEMPSENSOR_SET(x) (((x) << 20) & 0x00100000)
-#define PHY_ANALOG_TOP4_ADCPWD_OVR_MSB 21
-#define PHY_ANALOG_TOP4_ADCPWD_OVR_LSB 21
-#define PHY_ANALOG_TOP4_ADCPWD_OVR_MASK 0x00200000
-#define PHY_ANALOG_TOP4_ADCPWD_OVR_GET(x) (((x) & 0x00200000) >> 21)
-#define PHY_ANALOG_TOP4_ADCPWD_OVR_SET(x) (((x) << 21) & 0x00200000)
-#define PHY_ANALOG_TOP4_ADCPWD_INT_MSB 22
-#define PHY_ANALOG_TOP4_ADCPWD_INT_LSB 22
-#define PHY_ANALOG_TOP4_ADCPWD_INT_MASK 0x00400000
-#define PHY_ANALOG_TOP4_ADCPWD_INT_GET(x) (((x) & 0x00400000) >> 22)
-#define PHY_ANALOG_TOP4_ADCPWD_INT_SET(x) (((x) << 22) & 0x00400000)
-#define PHY_ANALOG_TOP4_TESTIQ_OFF_MSB 23
-#define PHY_ANALOG_TOP4_TESTIQ_OFF_LSB 23
-#define PHY_ANALOG_TOP4_TESTIQ_OFF_MASK 0x00800000
-#define PHY_ANALOG_TOP4_TESTIQ_OFF_GET(x) (((x) & 0x00800000) >> 23)
-#define PHY_ANALOG_TOP4_TESTIQ_OFF_SET(x) (((x) << 23) & 0x00800000)
-#define PHY_ANALOG_TOP4_TESTIQ_BUFEN_MSB 24
-#define PHY_ANALOG_TOP4_TESTIQ_BUFEN_LSB 24
-#define PHY_ANALOG_TOP4_TESTIQ_BUFEN_MASK 0x01000000
-#define PHY_ANALOG_TOP4_TESTIQ_BUFEN_GET(x) (((x) & 0x01000000) >> 24)
-#define PHY_ANALOG_TOP4_TESTIQ_BUFEN_SET(x) (((x) << 24) & 0x01000000)
-#define PHY_ANALOG_TOP4_PAL_LOCKEDEN_MSB 25
-#define PHY_ANALOG_TOP4_PAL_LOCKEDEN_LSB 25
-#define PHY_ANALOG_TOP4_PAL_LOCKEDEN_MASK 0x02000000
-#define PHY_ANALOG_TOP4_PAL_LOCKEDEN_GET(x) (((x) & 0x02000000) >> 25)
-#define PHY_ANALOG_TOP4_PAL_LOCKEDEN_SET(x) (((x) << 25) & 0x02000000)
-#define PHY_ANALOG_TOP4_SYNTHDIGOUTEN_MSB 26
-#define PHY_ANALOG_TOP4_SYNTHDIGOUTEN_LSB 26
-#define PHY_ANALOG_TOP4_SYNTHDIGOUTEN_MASK 0x04000000
-#define PHY_ANALOG_TOP4_SYNTHDIGOUTEN_GET(x) (((x) & 0x04000000) >> 26)
-#define PHY_ANALOG_TOP4_SYNTHDIGOUTEN_SET(x) (((x) << 26) & 0x04000000)
-#define PHY_ANALOG_TOP4_ENBTCLK_MSB 27
-#define PHY_ANALOG_TOP4_ENBTCLK_LSB 27
-#define PHY_ANALOG_TOP4_ENBTCLK_MASK 0x08000000
-#define PHY_ANALOG_TOP4_ENBTCLK_GET(x) (((x) & 0x08000000) >> 27)
-#define PHY_ANALOG_TOP4_ENBTCLK_SET(x) (((x) << 27) & 0x08000000)
-#define PHY_ANALOG_TOP4_PAD2GND_MSB 28
-#define PHY_ANALOG_TOP4_PAD2GND_LSB 28
-#define PHY_ANALOG_TOP4_PAD2GND_MASK 0x10000000
-#define PHY_ANALOG_TOP4_PAD2GND_GET(x) (((x) & 0x10000000) >> 28)
-#define PHY_ANALOG_TOP4_PAD2GND_SET(x) (((x) << 28) & 0x10000000)
-#define PHY_ANALOG_TOP4_INTH2PAD_MSB 29
-#define PHY_ANALOG_TOP4_INTH2PAD_LSB 29
-#define PHY_ANALOG_TOP4_INTH2PAD_MASK 0x20000000
-#define PHY_ANALOG_TOP4_INTH2PAD_GET(x) (((x) & 0x20000000) >> 29)
-#define PHY_ANALOG_TOP4_INTH2PAD_SET(x) (((x) << 29) & 0x20000000)
-#define PHY_ANALOG_TOP4_INTH2GND_MSB 30
-#define PHY_ANALOG_TOP4_INTH2GND_LSB 30
-#define PHY_ANALOG_TOP4_INTH2GND_MASK 0x40000000
-#define PHY_ANALOG_TOP4_INTH2GND_GET(x) (((x) & 0x40000000) >> 30)
-#define PHY_ANALOG_TOP4_INTH2GND_SET(x) (((x) << 30) & 0x40000000)
-#define PHY_ANALOG_TOP4_INT2PAD_MSB 31
-#define PHY_ANALOG_TOP4_INT2PAD_LSB 31
-#define PHY_ANALOG_TOP4_INT2PAD_MASK 0x80000000
-#define PHY_ANALOG_TOP4_INT2PAD_GET(x) (((x) & 0x80000000) >> 31)
-#define PHY_ANALOG_TOP4_INT2PAD_SET(x) (((x) << 31) & 0x80000000)
-
-/* macros for rbist_cntrl */
-#define PHY_ANALOG_RBIST_CNTRL_ADDRESS 0x00000380
-#define PHY_ANALOG_RBIST_CNTRL_OFFSET 0x00000380
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_MSB 0
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_LSB 0
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_MASK 0x00000001
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_MSB 1
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_LSB 1
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_MASK 0x00000002
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_GET(x) (((x) & 0x00000002) >> 1)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_SET(x) (((x) << 1) & 0x00000002)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_MSB 2
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_LSB 2
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_MASK 0x00000004
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_GET(x) (((x) & 0x00000004) >> 2)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_SET(x) (((x) << 2) & 0x00000004)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_MSB 3
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_LSB 3
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_MASK 0x00000008
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_GET(x) (((x) & 0x00000008) >> 3)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_SET(x) (((x) << 3) & 0x00000008)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_MSB 4
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_LSB 4
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_MASK 0x00000010
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_GET(x) (((x) & 0x00000010) >> 4)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_SET(x) (((x) << 4) & 0x00000010)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_MSB 5
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_LSB 5
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_MASK 0x00000020
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_GET(x) (((x) & 0x00000020) >> 5)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_SET(x) (((x) << 5) & 0x00000020)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_MSB 6
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_LSB 6
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_MASK 0x00000040
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_GET(x) (((x) & 0x00000040) >> 6)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_SET(x) (((x) << 6) & 0x00000040)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_MSB 7
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_LSB 7
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_MASK 0x00000080
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_GET(x) (((x) & 0x00000080) >> 7)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_SET(x) (((x) << 7) & 0x00000080)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_MSB 8
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_LSB 8
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_MASK 0x00000100
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_GET(x) (((x) & 0x00000100) >> 8)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_SET(x) (((x) << 8) & 0x00000100)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_MSB 9
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_LSB 9
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_MASK 0x00000200
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_GET(x) (((x) & 0x00000200) >> 9)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_SET(x) (((x) << 9) & 0x00000200)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_MSB 10
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_LSB 10
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_MASK 0x00000400
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_GET(x) (((x) & 0x00000400) >> 10)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_SET(x) (((x) << 10) & 0x00000400)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_MSB 11
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_LSB 11
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_MASK 0x00000800
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_GET(x) (((x) & 0x00000800) >> 11)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_SET(x) (((x) << 11) & 0x00000800)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_MSB 12
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_LSB 12
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_MASK 0x00001000
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_GET(x) (((x) & 0x00001000) >> 12)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_SET(x) (((x) << 12) & 0x00001000)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_MSB 13
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_LSB 13
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_MASK 0x00002000
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_GET(x) (((x) & 0x00002000) >> 13)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_SET(x) (((x) << 13) & 0x00002000)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_MSB 14
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_LSB 14
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_MASK 0x00004000
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_GET(x) (((x) & 0x00004000) >> 14)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_SET(x) (((x) << 14) & 0x00004000)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_MSB 15
-#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_LSB 15
-#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_MASK 0x00008000
-#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_GET(x) (((x) & 0x00008000) >> 15)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_SET(x) (((x) << 15) & 0x00008000)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_MSB 16
-#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_LSB 16
-#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_MASK 0x00010000
-#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_GET(x) (((x) & 0x00010000) >> 16)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_SET(x) (((x) << 16) & 0x00010000)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_MSB 17
-#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_LSB 17
-#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_MASK 0x00020000
-#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_GET(x) (((x) & 0x00020000) >> 17)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_SET(x) (((x) << 17) & 0x00020000)
-
-/* macros for tx_dc_offset */
-#define PHY_ANALOG_TX_DC_OFFSET_ADDRESS 0x00000384
-#define PHY_ANALOG_TX_DC_OFFSET_OFFSET 0x00000384
-#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_MSB 10
-#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_LSB 0
-#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_MASK 0x000007ff
-#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_GET(x) (((x) & 0x000007ff) >> 0)
-#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_SET(x) (((x) << 0) & 0x000007ff)
-#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_MSB 26
-#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_LSB 16
-#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_MASK 0x07ff0000
-#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_GET(x) (((x) & 0x07ff0000) >> 16)
-#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_SET(x) (((x) << 16) & 0x07ff0000)
-
-/* macros for tx_tonegen0 */
-#define PHY_ANALOG_TX_TONEGEN0_ADDRESS 0x00000388
-#define PHY_ANALOG_TX_TONEGEN0_OFFSET 0x00000388
-#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_MSB 6
-#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_LSB 0
-#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_MASK 0x0000007f
-#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_GET(x) (((x) & 0x0000007f) >> 0)
-#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_SET(x) (((x) << 0) & 0x0000007f)
-#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_MSB 11
-#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_LSB 8
-#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_MASK 0x00000f00
-#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_GET(x) (((x) & 0x00000f00) >> 8)
-#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_SET(x) (((x) << 8) & 0x00000f00)
-#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_MSB 23
-#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_LSB 16
-#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_MASK 0x00ff0000
-#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_GET(x) (((x) & 0x00ff0000) >> 16)
-#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_SET(x) (((x) << 16) & 0x00ff0000)
-#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_MSB 30
-#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_LSB 24
-#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_MASK 0x7f000000
-#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_GET(x) (((x) & 0x7f000000) >> 24)
-#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_SET(x) (((x) << 24) & 0x7f000000)
-
-/* macros for tx_tonegen1 */
-#define PHY_ANALOG_TX_TONEGEN1_ADDRESS 0x0000038c
-#define PHY_ANALOG_TX_TONEGEN1_OFFSET 0x0000038c
-#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_MSB 6
-#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_LSB 0
-#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_MASK 0x0000007f
-#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_GET(x) (((x) & 0x0000007f) >> 0)
-#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_SET(x) (((x) << 0) & 0x0000007f)
-#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_MSB 11
-#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_LSB 8
-#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_MASK 0x00000f00
-#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_GET(x) (((x) & 0x00000f00) >> 8)
-#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_SET(x) (((x) << 8) & 0x00000f00)
-#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_MSB 23
-#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_LSB 16
-#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_MASK 0x00ff0000
-#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_GET(x) (((x) & 0x00ff0000) >> 16)
-#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_SET(x) (((x) << 16) & 0x00ff0000)
-#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_MSB 30
-#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_LSB 24
-#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_MASK 0x7f000000
-#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_GET(x) (((x) & 0x7f000000) >> 24)
-#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_SET(x) (((x) << 24) & 0x7f000000)
-
-/* macros for tx_lftonegen0 */
-#define PHY_ANALOG_TX_LFTONEGEN0_ADDRESS 0x00000390
-#define PHY_ANALOG_TX_LFTONEGEN0_OFFSET 0x00000390
-#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_MSB 6
-#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_LSB 0
-#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_MASK 0x0000007f
-#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_GET(x) (((x) & 0x0000007f) >> 0)
-#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_SET(x) (((x) << 0) & 0x0000007f)
-#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_MSB 11
-#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_LSB 8
-#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_MASK 0x00000f00
-#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_GET(x) (((x) & 0x00000f00) >> 8)
-#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_SET(x) (((x) << 8) & 0x00000f00)
-#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_MSB 23
-#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_LSB 16
-#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_MASK 0x00ff0000
-#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_GET(x) (((x) & 0x00ff0000) >> 16)
-#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_SET(x) (((x) << 16) & 0x00ff0000)
-#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_MSB 30
-#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_LSB 24
-#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_MASK 0x7f000000
-#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_GET(x) (((x) & 0x7f000000) >> 24)
-#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_SET(x) (((x) << 24) & 0x7f000000)
-
-/* macros for tx_linear_ramp_i */
-#define PHY_ANALOG_TX_LINEAR_RAMP_I_ADDRESS 0x00000394
-#define PHY_ANALOG_TX_LINEAR_RAMP_I_OFFSET 0x00000394
-#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_MSB 10
-#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_LSB 0
-#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_MASK 0x000007ff
-#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_GET(x) (((x) & 0x000007ff) >> 0)
-#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_SET(x) (((x) << 0) & 0x000007ff)
-#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_MSB 21
-#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_LSB 12
-#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_MASK 0x003ff000
-#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_GET(x) (((x) & 0x003ff000) >> 12)
-#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_SET(x) (((x) << 12) & 0x003ff000)
-#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_MSB 29
-#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_LSB 24
-#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_MASK 0x3f000000
-#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_GET(x) (((x) & 0x3f000000) >> 24)
-#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_SET(x) (((x) << 24) & 0x3f000000)
-
-/* macros for tx_linear_ramp_q */
-#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ADDRESS 0x00000398
-#define PHY_ANALOG_TX_LINEAR_RAMP_Q_OFFSET 0x00000398
-#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_MSB 10
-#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_LSB 0
-#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_MASK 0x000007ff
-#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_GET(x) (((x) & 0x000007ff) >> 0)
-#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_SET(x) (((x) << 0) & 0x000007ff)
-#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_MSB 21
-#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_LSB 12
-#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_MASK 0x003ff000
-#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_GET(x) (((x) & 0x003ff000) >> 12)
-#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_SET(x) (((x) << 12) & 0x003ff000)
-#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_MSB 29
-#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_LSB 24
-#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_MASK 0x3f000000
-#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_GET(x) (((x) & 0x3f000000) >> 24)
-#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_SET(x) (((x) << 24) & 0x3f000000)
-
-/* macros for tx_prbs_mag */
-#define PHY_ANALOG_TX_PRBS_MAG_ADDRESS 0x0000039c
-#define PHY_ANALOG_TX_PRBS_MAG_OFFSET 0x0000039c
-#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_MSB 9
-#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_LSB 0
-#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_MASK 0x000003ff
-#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_GET(x) (((x) & 0x000003ff) >> 0)
-#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_SET(x) (((x) << 0) & 0x000003ff)
-#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_MSB 25
-#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_LSB 16
-#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_MASK 0x03ff0000
-#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_GET(x) (((x) & 0x03ff0000) >> 16)
-#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_SET(x) (((x) << 16) & 0x03ff0000)
-
-/* macros for tx_prbs_seed_i */
-#define PHY_ANALOG_TX_PRBS_SEED_I_ADDRESS 0x000003a0
-#define PHY_ANALOG_TX_PRBS_SEED_I_OFFSET 0x000003a0
-#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_MSB 30
-#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_LSB 0
-#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_MASK 0x7fffffff
-#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_GET(x) (((x) & 0x7fffffff) >> 0)
-#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_SET(x) (((x) << 0) & 0x7fffffff)
-
-/* macros for tx_prbs_seed_q */
-#define PHY_ANALOG_TX_PRBS_SEED_Q_ADDRESS 0x000003a4
-#define PHY_ANALOG_TX_PRBS_SEED_Q_OFFSET 0x000003a4
-#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_MSB 30
-#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_LSB 0
-#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_MASK 0x7fffffff
-#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_GET(x) (((x) & 0x7fffffff) >> 0)
-#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_SET(x) (((x) << 0) & 0x7fffffff)
-
-/* macros for cmac_dc_cancel */
-#define PHY_ANALOG_CMAC_DC_CANCEL_ADDRESS 0x000003a8
-#define PHY_ANALOG_CMAC_DC_CANCEL_OFFSET 0x000003a8
-#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_MSB 9
-#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_LSB 0
-#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_MASK 0x000003ff
-#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_GET(x) (((x) & 0x000003ff) >> 0)
-#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_SET(x) (((x) << 0) & 0x000003ff)
-#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_MSB 25
-#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_LSB 16
-#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_MASK 0x03ff0000
-#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_GET(x) (((x) & 0x03ff0000) >> 16)
-#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_SET(x) (((x) << 16) & 0x03ff0000)
-
-/* macros for cmac_dc_offset */
-#define PHY_ANALOG_CMAC_DC_OFFSET_ADDRESS 0x000003ac
-#define PHY_ANALOG_CMAC_DC_OFFSET_OFFSET 0x000003ac
-#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_MSB 3
-#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_LSB 0
-#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_MASK 0x0000000f
-#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_GET(x) (((x) & 0x0000000f) >> 0)
-#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_SET(x) (((x) << 0) & 0x0000000f)
-
-/* macros for cmac_corr */
-#define PHY_ANALOG_CMAC_CORR_ADDRESS 0x000003b0
-#define PHY_ANALOG_CMAC_CORR_OFFSET 0x000003b0
-#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_MSB 4
-#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_LSB 0
-#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_MASK 0x0000001f
-#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_GET(x) (((x) & 0x0000001f) >> 0)
-#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_SET(x) (((x) << 0) & 0x0000001f)
-#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_MSB 13
-#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_LSB 8
-#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_MASK 0x00003f00
-#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_GET(x) (((x) & 0x00003f00) >> 8)
-#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_SET(x) (((x) << 8) & 0x00003f00)
-
-/* macros for cmac_power */
-#define PHY_ANALOG_CMAC_POWER_ADDRESS 0x000003b4
-#define PHY_ANALOG_CMAC_POWER_OFFSET 0x000003b4
-#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_MSB 3
-#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_LSB 0
-#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_MASK 0x0000000f
-#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_GET(x) (((x) & 0x0000000f) >> 0)
-#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_SET(x) (((x) << 0) & 0x0000000f)
-
-/* macros for cmac_cross_corr */
-#define PHY_ANALOG_CMAC_CROSS_CORR_ADDRESS 0x000003b8
-#define PHY_ANALOG_CMAC_CROSS_CORR_OFFSET 0x000003b8
-#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_MSB 3
-#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_LSB 0
-#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_MASK 0x0000000f
-#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_GET(x) (((x) & 0x0000000f) >> 0)
-#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_SET(x) (((x) << 0) & 0x0000000f)
-
-/* macros for cmac_i2q2 */
-#define PHY_ANALOG_CMAC_I2Q2_ADDRESS 0x000003bc
-#define PHY_ANALOG_CMAC_I2Q2_OFFSET 0x000003bc
-#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_MSB 3
-#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_LSB 0
-#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_MASK 0x0000000f
-#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_GET(x) (((x) & 0x0000000f) >> 0)
-#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_SET(x) (((x) << 0) & 0x0000000f)
-
-/* macros for cmac_power_hpf */
-#define PHY_ANALOG_CMAC_POWER_HPF_ADDRESS 0x000003c0
-#define PHY_ANALOG_CMAC_POWER_HPF_OFFSET 0x000003c0
-#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_MSB 3
-#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_LSB 0
-#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_MASK 0x0000000f
-#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_GET(x) (((x) & 0x0000000f) >> 0)
-#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_SET(x) (((x) << 0) & 0x0000000f)
-#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_MSB 7
-#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_LSB 4
-#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_MASK 0x000000f0
-#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_GET(x) (((x) & 0x000000f0) >> 4)
-#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_SET(x) (((x) << 4) & 0x000000f0)
-
-/* macros for rxdac_set1 */
-#define PHY_ANALOG_RXDAC_SET1_ADDRESS 0x000003c4
-#define PHY_ANALOG_RXDAC_SET1_OFFSET 0x000003c4
-#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_MSB 1
-#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_LSB 0
-#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_MASK 0x00000003
-#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_GET(x) (((x) & 0x00000003) >> 0)
-#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_SET(x) (((x) << 0) & 0x00000003)
-#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_MSB 4
-#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_LSB 4
-#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_MASK 0x00000010
-#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_GET(x) (((x) & 0x00000010) >> 4)
-#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_SET(x) (((x) << 4) & 0x00000010)
-#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_MSB 13
-#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_LSB 8
-#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_MASK 0x00003f00
-#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_GET(x) (((x) & 0x00003f00) >> 8)
-#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_SET(x) (((x) << 8) & 0x00003f00)
-#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_MSB 19
-#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_LSB 16
-#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_MASK 0x000f0000
-#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_GET(x) (((x) & 0x000f0000) >> 16)
-#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_SET(x) (((x) << 16) & 0x000f0000)
-
-/* macros for rxdac_set2 */
-#define PHY_ANALOG_RXDAC_SET2_ADDRESS 0x000003c8
-#define PHY_ANALOG_RXDAC_SET2_OFFSET 0x000003c8
-#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_MSB 4
-#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_LSB 0
-#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_MASK 0x0000001f
-#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_GET(x) (((x) & 0x0000001f) >> 0)
-#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_SET(x) (((x) << 0) & 0x0000001f)
-#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_MSB 12
-#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_LSB 8
-#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_MASK 0x00001f00
-#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_GET(x) (((x) & 0x00001f00) >> 8)
-#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_SET(x) (((x) << 8) & 0x00001f00)
-#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_MSB 20
-#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_LSB 16
-#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_MASK 0x001f0000
-#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_GET(x) (((x) & 0x001f0000) >> 16)
-#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_SET(x) (((x) << 16) & 0x001f0000)
-#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_MSB 28
-#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_LSB 24
-#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_MASK 0x1f000000
-#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_GET(x) (((x) & 0x1f000000) >> 24)
-#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_SET(x) (((x) << 24) & 0x1f000000)
-
-/* macros for rxdac_long_shift */
-#define PHY_ANALOG_RXDAC_LONG_SHIFT_ADDRESS 0x000003cc
-#define PHY_ANALOG_RXDAC_LONG_SHIFT_OFFSET 0x000003cc
-#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_MSB 4
-#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_LSB 0
-#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_MASK 0x0000001f
-#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_GET(x) (((x) & 0x0000001f) >> 0)
-#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_SET(x) (((x) << 0) & 0x0000001f)
-#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_MSB 12
-#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_LSB 8
-#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_MASK 0x00001f00
-#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_GET(x) (((x) & 0x00001f00) >> 8)
-#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_SET(x) (((x) << 8) & 0x00001f00)
-
-/* macros for cmac_results_i */
-#define PHY_ANALOG_CMAC_RESULTS_I_ADDRESS 0x000003d0
-#define PHY_ANALOG_CMAC_RESULTS_I_OFFSET 0x000003d0
-#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_MSB 31
-#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_LSB 0
-#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_MASK 0xffffffff
-#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for cmac_results_q */
-#define PHY_ANALOG_CMAC_RESULTS_Q_ADDRESS 0x000003d4
-#define PHY_ANALOG_CMAC_RESULTS_Q_OFFSET 0x000003d4
-#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_MSB 31
-#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_LSB 0
-#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_MASK 0xffffffff
-#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for PMU1 */
-#define PHY_ANALOG_PMU1_ADDRESS 0x00000740
-#define PHY_ANALOG_PMU1_OFFSET 0x00000740
-#define PHY_ANALOG_PMU1_SPARE_MSB 10
-#define PHY_ANALOG_PMU1_SPARE_LSB 0
-#define PHY_ANALOG_PMU1_SPARE_MASK 0x000007ff
-#define PHY_ANALOG_PMU1_SPARE_GET(x) (((x) & 0x000007ff) >> 0)
-#define PHY_ANALOG_PMU1_SPARE_SET(x) (((x) << 0) & 0x000007ff)
-#define PHY_ANALOG_PMU1_OTP_V25_PWD_MSB 11
-#define PHY_ANALOG_PMU1_OTP_V25_PWD_LSB 11
-#define PHY_ANALOG_PMU1_OTP_V25_PWD_MASK 0x00000800
-#define PHY_ANALOG_PMU1_OTP_V25_PWD_GET(x) (((x) & 0x00000800) >> 11)
-#define PHY_ANALOG_PMU1_OTP_V25_PWD_SET(x) (((x) << 11) & 0x00000800)
-#define PHY_ANALOG_PMU1_PAREGON_MAN_MSB 12
-#define PHY_ANALOG_PMU1_PAREGON_MAN_LSB 12
-#define PHY_ANALOG_PMU1_PAREGON_MAN_MASK 0x00001000
-#define PHY_ANALOG_PMU1_PAREGON_MAN_GET(x) (((x) & 0x00001000) >> 12)
-#define PHY_ANALOG_PMU1_PAREGON_MAN_SET(x) (((x) << 12) & 0x00001000)
-#define PHY_ANALOG_PMU1_OTPREGON_MAN_MSB 13
-#define PHY_ANALOG_PMU1_OTPREGON_MAN_LSB 13
-#define PHY_ANALOG_PMU1_OTPREGON_MAN_MASK 0x00002000
-#define PHY_ANALOG_PMU1_OTPREGON_MAN_GET(x) (((x) & 0x00002000) >> 13)
-#define PHY_ANALOG_PMU1_OTPREGON_MAN_SET(x) (((x) << 13) & 0x00002000)
-#define PHY_ANALOG_PMU1_DREGON_MAN_MSB 14
-#define PHY_ANALOG_PMU1_DREGON_MAN_LSB 14
-#define PHY_ANALOG_PMU1_DREGON_MAN_MASK 0x00004000
-#define PHY_ANALOG_PMU1_DREGON_MAN_GET(x) (((x) & 0x00004000) >> 14)
-#define PHY_ANALOG_PMU1_DREGON_MAN_SET(x) (((x) << 14) & 0x00004000)
-#define PHY_ANALOG_PMU1_DISCONTMODEEN_MSB 15
-#define PHY_ANALOG_PMU1_DISCONTMODEEN_LSB 15
-#define PHY_ANALOG_PMU1_DISCONTMODEEN_MASK 0x00008000
-#define PHY_ANALOG_PMU1_DISCONTMODEEN_GET(x) (((x) & 0x00008000) >> 15)
-#define PHY_ANALOG_PMU1_DISCONTMODEEN_SET(x) (((x) << 15) & 0x00008000)
-#define PHY_ANALOG_PMU1_SWREGON_MAN_MSB 16
-#define PHY_ANALOG_PMU1_SWREGON_MAN_LSB 16
-#define PHY_ANALOG_PMU1_SWREGON_MAN_MASK 0x00010000
-#define PHY_ANALOG_PMU1_SWREGON_MAN_GET(x) (((x) & 0x00010000) >> 16)
-#define PHY_ANALOG_PMU1_SWREGON_MAN_SET(x) (((x) << 16) & 0x00010000)
-#define PHY_ANALOG_PMU1_SWREG_FREQCUR_MSB 18
-#define PHY_ANALOG_PMU1_SWREG_FREQCUR_LSB 17
-#define PHY_ANALOG_PMU1_SWREG_FREQCUR_MASK 0x00060000
-#define PHY_ANALOG_PMU1_SWREG_FREQCUR_GET(x) (((x) & 0x00060000) >> 17)
-#define PHY_ANALOG_PMU1_SWREG_FREQCUR_SET(x) (((x) << 17) & 0x00060000)
-#define PHY_ANALOG_PMU1_SWREG_FREQCAP_MSB 21
-#define PHY_ANALOG_PMU1_SWREG_FREQCAP_LSB 19
-#define PHY_ANALOG_PMU1_SWREG_FREQCAP_MASK 0x00380000
-#define PHY_ANALOG_PMU1_SWREG_FREQCAP_GET(x) (((x) & 0x00380000) >> 19)
-#define PHY_ANALOG_PMU1_SWREG_FREQCAP_SET(x) (((x) << 19) & 0x00380000)
-#define PHY_ANALOG_PMU1_SWREG_LVLCTR_MSB 23
-#define PHY_ANALOG_PMU1_SWREG_LVLCTR_LSB 22
-#define PHY_ANALOG_PMU1_SWREG_LVLCTR_MASK 0x00c00000
-#define PHY_ANALOG_PMU1_SWREG_LVLCTR_GET(x) (((x) & 0x00c00000) >> 22)
-#define PHY_ANALOG_PMU1_SWREG_LVLCTR_SET(x) (((x) << 22) & 0x00c00000)
-#define PHY_ANALOG_PMU1_SREG_LVLCTR_MSB 25
-#define PHY_ANALOG_PMU1_SREG_LVLCTR_LSB 24
-#define PHY_ANALOG_PMU1_SREG_LVLCTR_MASK 0x03000000
-#define PHY_ANALOG_PMU1_SREG_LVLCTR_GET(x) (((x) & 0x03000000) >> 24)
-#define PHY_ANALOG_PMU1_SREG_LVLCTR_SET(x) (((x) << 24) & 0x03000000)
-#define PHY_ANALOG_PMU1_DREG_LVLCTR_MSB 27
-#define PHY_ANALOG_PMU1_DREG_LVLCTR_LSB 26
-#define PHY_ANALOG_PMU1_DREG_LVLCTR_MASK 0x0c000000
-#define PHY_ANALOG_PMU1_DREG_LVLCTR_GET(x) (((x) & 0x0c000000) >> 26)
-#define PHY_ANALOG_PMU1_DREG_LVLCTR_SET(x) (((x) << 26) & 0x0c000000)
-#define PHY_ANALOG_PMU1_PAREG_XPNP_MSB 28
-#define PHY_ANALOG_PMU1_PAREG_XPNP_LSB 28
-#define PHY_ANALOG_PMU1_PAREG_XPNP_MASK 0x10000000
-#define PHY_ANALOG_PMU1_PAREG_XPNP_GET(x) (((x) & 0x10000000) >> 28)
-#define PHY_ANALOG_PMU1_PAREG_XPNP_SET(x) (((x) << 28) & 0x10000000)
-#define PHY_ANALOG_PMU1_PAREG_LVLCTR_MSB 31
-#define PHY_ANALOG_PMU1_PAREG_LVLCTR_LSB 29
-#define PHY_ANALOG_PMU1_PAREG_LVLCTR_MASK 0xe0000000
-#define PHY_ANALOG_PMU1_PAREG_LVLCTR_GET(x) (((x) & 0xe0000000) >> 29)
-#define PHY_ANALOG_PMU1_PAREG_LVLCTR_SET(x) (((x) << 29) & 0xe0000000)
-
-/* macros for PMU2 */
-#define PHY_ANALOG_PMU2_ADDRESS 0x00000744
-#define PHY_ANALOG_PMU2_OFFSET 0x00000744
-#define PHY_ANALOG_PMU2_SPARE_MSB 7
-#define PHY_ANALOG_PMU2_SPARE_LSB 0
-#define PHY_ANALOG_PMU2_SPARE_MASK 0x000000ff
-#define PHY_ANALOG_PMU2_SPARE_GET(x) (((x) & 0x000000ff) >> 0)
-#define PHY_ANALOG_PMU2_SPARE_SET(x) (((x) << 0) & 0x000000ff)
-#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_MSB 8
-#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_LSB 8
-#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_MASK 0x00000100
-#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_GET(x) (((x) & 0x00000100) >> 8)
-#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_SET(x) (((x) << 8) & 0x00000100)
-#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_MSB 9
-#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_LSB 9
-#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_MASK 0x00000200
-#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_GET(x) (((x) & 0x00000200) >> 9)
-#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_SET(x) (((x) << 9) & 0x00000200)
-#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_MSB 10
-#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_LSB 10
-#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_MASK 0x00000400
-#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_GET(x) (((x) & 0x00000400) >> 10)
-#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_SET(x) (((x) << 10) & 0x00000400)
-#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_MSB 11
-#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_LSB 11
-#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_MASK 0x00000800
-#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_GET(x) (((x) & 0x00000800) >> 11)
-#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_SET(x) (((x) << 11) & 0x00000800)
-#define PHY_ANALOG_PMU2_PWD_LFO_MAN_MSB 12
-#define PHY_ANALOG_PMU2_PWD_LFO_MAN_LSB 12
-#define PHY_ANALOG_PMU2_PWD_LFO_MAN_MASK 0x00001000
-#define PHY_ANALOG_PMU2_PWD_LFO_MAN_GET(x) (((x) & 0x00001000) >> 12)
-#define PHY_ANALOG_PMU2_PWD_LFO_MAN_SET(x) (((x) << 12) & 0x00001000)
-#define PHY_ANALOG_PMU2_VBATT_LT_3P2_MSB 13
-#define PHY_ANALOG_PMU2_VBATT_LT_3P2_LSB 13
-#define PHY_ANALOG_PMU2_VBATT_LT_3P2_MASK 0x00002000
-#define PHY_ANALOG_PMU2_VBATT_LT_3P2_GET(x) (((x) & 0x00002000) >> 13)
-#define PHY_ANALOG_PMU2_VBATT_LT_3P2_SET(x) (((x) << 13) & 0x00002000)
-#define PHY_ANALOG_PMU2_VBATT_LT_2P8_MSB 14
-#define PHY_ANALOG_PMU2_VBATT_LT_2P8_LSB 14
-#define PHY_ANALOG_PMU2_VBATT_LT_2P8_MASK 0x00004000
-#define PHY_ANALOG_PMU2_VBATT_LT_2P8_GET(x) (((x) & 0x00004000) >> 14)
-#define PHY_ANALOG_PMU2_VBATT_LT_2P8_SET(x) (((x) << 14) & 0x00004000)
-#define PHY_ANALOG_PMU2_VBATT_GT_4P2_MSB 15
-#define PHY_ANALOG_PMU2_VBATT_GT_4P2_LSB 15
-#define PHY_ANALOG_PMU2_VBATT_GT_4P2_MASK 0x00008000
-#define PHY_ANALOG_PMU2_VBATT_GT_4P2_GET(x) (((x) & 0x00008000) >> 15)
-#define PHY_ANALOG_PMU2_VBATT_GT_4P2_SET(x) (((x) << 15) & 0x00008000)
-#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_MSB 16
-#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_LSB 16
-#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_MASK 0x00010000
-#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_GET(x) (((x) & 0x00010000) >> 16)
-#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_SET(x) (((x) << 16) & 0x00010000)
-#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_MSB 18
-#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_LSB 17
-#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_MASK 0x00060000
-#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_GET(x) (((x) & 0x00060000) >> 17)
-#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_SET(x) (((x) << 17) & 0x00060000)
-#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_MSB 19
-#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_LSB 19
-#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_MASK 0x00080000
-#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_GET(x) (((x) & 0x00080000) >> 19)
-#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_SET(x) (((x) << 19) & 0x00080000)
-#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_MSB 21
-#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_LSB 20
-#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_MASK 0x00300000
-#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_GET(x) (((x) & 0x00300000) >> 20)
-#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_SET(x) (((x) << 20) & 0x00300000)
-#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_MSB 22
-#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_LSB 22
-#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_MASK 0x00400000
-#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_GET(x) (((x) & 0x00400000) >> 22)
-#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_SET(x) (((x) << 22) & 0x00400000)
-#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_MSB 24
-#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_LSB 23
-#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_MASK 0x01800000
-#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_GET(x) (((x) & 0x01800000) >> 23)
-#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_SET(x) (((x) << 23) & 0x01800000)
-#define PHY_ANALOG_PMU2_SWREG2ATB_MSB 27
-#define PHY_ANALOG_PMU2_SWREG2ATB_LSB 25
-#define PHY_ANALOG_PMU2_SWREG2ATB_MASK 0x0e000000
-#define PHY_ANALOG_PMU2_SWREG2ATB_GET(x) (((x) & 0x0e000000) >> 25)
-#define PHY_ANALOG_PMU2_SWREG2ATB_SET(x) (((x) << 25) & 0x0e000000)
-#define PHY_ANALOG_PMU2_OTPREG2ATB_MSB 28
-#define PHY_ANALOG_PMU2_OTPREG2ATB_LSB 28
-#define PHY_ANALOG_PMU2_OTPREG2ATB_MASK 0x10000000
-#define PHY_ANALOG_PMU2_OTPREG2ATB_GET(x) (((x) & 0x10000000) >> 28)
-#define PHY_ANALOG_PMU2_OTPREG2ATB_SET(x) (((x) << 28) & 0x10000000)
-#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_MSB 30
-#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_LSB 29
-#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_MASK 0x60000000
-#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_GET(x) (((x) & 0x60000000) >> 29)
-#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_SET(x) (((x) << 29) & 0x60000000)
-#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_MSB 31
-#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_LSB 31
-#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_MASK 0x80000000
-#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_GET(x) (((x) & 0x80000000) >> 31)
-#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_SET(x) (((x) << 31) & 0x80000000)
-
-
-#ifndef __ASSEMBLER__
-
-typedef struct analog_intf_ares_reg_reg_s {
- volatile unsigned int RXRF_BIAS1; /* 0x0 - 0x4 */
- volatile unsigned int RXRF_BIAS2; /* 0x4 - 0x8 */
- volatile unsigned int RXRF_GAINSTAGES; /* 0x8 - 0xc */
- volatile unsigned int RXRF_AGC; /* 0xc - 0x10 */
- volatile char pad__0[0x30]; /* 0x10 - 0x40 */
- volatile unsigned int TXRF1; /* 0x40 - 0x44 */
- volatile unsigned int TXRF2; /* 0x44 - 0x48 */
- volatile unsigned int TXRF3; /* 0x48 - 0x4c */
- volatile unsigned int TXRF4; /* 0x4c - 0x50 */
- volatile unsigned int TXRF5; /* 0x50 - 0x54 */
- volatile unsigned int TXRF6; /* 0x54 - 0x58 */
- volatile unsigned int TXRF7; /* 0x58 - 0x5c */
- volatile unsigned int TXRF8; /* 0x5c - 0x60 */
- volatile unsigned int TXRF9; /* 0x60 - 0x64 */
- volatile unsigned int TXRF10; /* 0x64 - 0x68 */
- volatile unsigned int TXRF11; /* 0x68 - 0x6c */
- volatile unsigned int TXRF12; /* 0x6c - 0x70 */
- volatile char pad__1[0x10]; /* 0x70 - 0x80 */
- volatile unsigned int SYNTH1; /* 0x80 - 0x84 */
- volatile unsigned int SYNTH2; /* 0x84 - 0x88 */
- volatile unsigned int SYNTH3; /* 0x88 - 0x8c */
- volatile unsigned int SYNTH4; /* 0x8c - 0x90 */
- volatile unsigned int SYNTH5; /* 0x90 - 0x94 */
- volatile unsigned int SYNTH6; /* 0x94 - 0x98 */
- volatile unsigned int SYNTH7; /* 0x98 - 0x9c */
- volatile unsigned int SYNTH8; /* 0x9c - 0xa0 */
- volatile unsigned int SYNTH9; /* 0xa0 - 0xa4 */
- volatile unsigned int SYNTH10; /* 0xa4 - 0xa8 */
- volatile unsigned int SYNTH11; /* 0xa8 - 0xac */
- volatile unsigned int SYNTH12; /* 0xac - 0xb0 */
- volatile char pad__2[0x10]; /* 0xb0 - 0xc0 */
- volatile unsigned int BIAS1; /* 0xc0 - 0xc4 */
- volatile unsigned int BIAS2; /* 0xc4 - 0xc8 */
- volatile unsigned int BIAS3; /* 0xc8 - 0xcc */
- volatile unsigned int BIAS4; /* 0xcc - 0xd0 */
- volatile char pad__3[0x30]; /* 0xd0 - 0x100 */
- volatile unsigned int RXTX1; /* 0x100 - 0x104 */
- volatile unsigned int RXTX2; /* 0x104 - 0x108 */
- volatile unsigned int RXTX3; /* 0x108 - 0x10c */
- volatile char pad__4[0x34]; /* 0x10c - 0x140 */
- volatile unsigned int BB1; /* 0x140 - 0x144 */
- volatile unsigned int BB2; /* 0x144 - 0x148 */
- volatile char pad__5[0x138]; /* 0x148 - 0x280 */
- volatile unsigned int TOP1; /* 0x280 - 0x284 */
- volatile unsigned int TOP2; /* 0x284 - 0x288 */
- volatile unsigned int TOP3; /* 0x288 - 0x28c */
- volatile unsigned int TOP4; /* 0x28c - 0x290 */
- volatile char pad__6[0xf0]; /* 0x290 - 0x380 */
- volatile unsigned int rbist_cntrl; /* 0x380 - 0x384 */
- volatile unsigned int tx_dc_offset; /* 0x384 - 0x388 */
- volatile unsigned int tx_tonegen0; /* 0x388 - 0x38c */
- volatile unsigned int tx_tonegen1; /* 0x38c - 0x390 */
- volatile unsigned int tx_lftonegen0; /* 0x390 - 0x394 */
- volatile unsigned int tx_linear_ramp_i; /* 0x394 - 0x398 */
- volatile unsigned int tx_linear_ramp_q; /* 0x398 - 0x39c */
- volatile unsigned int tx_prbs_mag; /* 0x39c - 0x3a0 */
- volatile unsigned int tx_prbs_seed_i; /* 0x3a0 - 0x3a4 */
- volatile unsigned int tx_prbs_seed_q; /* 0x3a4 - 0x3a8 */
- volatile unsigned int cmac_dc_cancel; /* 0x3a8 - 0x3ac */
- volatile unsigned int cmac_dc_offset; /* 0x3ac - 0x3b0 */
- volatile unsigned int cmac_corr; /* 0x3b0 - 0x3b4 */
- volatile unsigned int cmac_power; /* 0x3b4 - 0x3b8 */
- volatile unsigned int cmac_cross_corr; /* 0x3b8 - 0x3bc */
- volatile unsigned int cmac_i2q2; /* 0x3bc - 0x3c0 */
- volatile unsigned int cmac_power_hpf; /* 0x3c0 - 0x3c4 */
- volatile unsigned int rxdac_set1; /* 0x3c4 - 0x3c8 */
- volatile unsigned int rxdac_set2; /* 0x3c8 - 0x3cc */
- volatile unsigned int rxdac_long_shift; /* 0x3cc - 0x3d0 */
- volatile unsigned int cmac_results_i; /* 0x3d0 - 0x3d4 */
- volatile unsigned int cmac_results_q; /* 0x3d4 - 0x3d8 */
- volatile char pad__7[0x368]; /* 0x3d8 - 0x740 */
- volatile unsigned int PMU1; /* 0x740 - 0x744 */
- volatile unsigned int PMU2; /* 0x744 - 0x748 */
-} analog_intf_ares_reg_reg_t;
-
-#endif /* __ASSEMBLER__ */
-
-#endif /* _ANALOG_INTF_ARES_REG_REG_H_ */
diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/analog_intf_athr_wlan_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/analog_intf_athr_wlan_reg.h
deleted file mode 100644
index 1c243fb..0000000
--- a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/analog_intf_athr_wlan_reg.h
+++ /dev/null
@@ -1,3674 +0,0 @@
-// ------------------------------------------------------------------
-// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
-//
-//
-// Permission to use, copy, modify, and/or distribute this software for any
-// purpose with or without fee is hereby granted, provided that the above
-// copyright notice and this permission notice appear in all copies.
-//
-// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-//
-//
-// ------------------------------------------------------------------
-//===================================================================
-// Author(s): ="Atheros"
-//===================================================================
-
-/* Copyright (C) 2009 Denali Software Inc. All rights reserved */
-/* THIS FILE IS AUTOMATICALLY GENERATED BY DENALI BLUEPRINT, DO NOT EDIT */
-
-
-#ifndef _ANALOG_INTF_ATHR_WLAN_REG_REG_H_
-#define _ANALOG_INTF_ATHR_WLAN_REG_REG_H_
-
-
-/* macros for RXRF_BIAS1 */
-#define PHY_ANALOG_RXRF_BIAS1_ADDRESS 0x00000000
-#define PHY_ANALOG_RXRF_BIAS1_OFFSET 0x00000000
-#define PHY_ANALOG_RXRF_BIAS1_SPARE_MSB 0
-#define PHY_ANALOG_RXRF_BIAS1_SPARE_LSB 0
-#define PHY_ANALOG_RXRF_BIAS1_SPARE_MASK 0x00000001
-#define PHY_ANALOG_RXRF_BIAS1_SPARE_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_ANALOG_RXRF_BIAS1_SPARE_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_MSB 3
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_LSB 1
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_MASK 0x0000000e
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_GET(x) (((x) & 0x0000000e) >> 1)
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25SPARE_SET(x) (((x) << 1) & 0x0000000e)
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_MSB 6
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_LSB 4
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_MASK 0x00000070
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_GET(x) (((x) & 0x00000070) >> 4)
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO18_SET(x) (((x) << 4) & 0x00000070)
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_MSB 9
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_LSB 7
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_MASK 0x00000380
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_GET(x) (((x) & 0x00000380) >> 7)
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25LO36_SET(x) (((x) << 7) & 0x00000380)
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_MSB 12
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_LSB 10
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_MASK 0x00001c00
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_GET(x) (((x) & 0x00001c00) >> 10)
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2_5GH_SET(x) (((x) << 10) & 0x00001c00)
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_MSB 15
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_LSB 13
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_MASK 0x0000e000
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_GET(x) (((x) & 0x0000e000) >> 13)
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR5GH_SET(x) (((x) << 13) & 0x0000e000)
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_MSB 18
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_LSB 16
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_MASK 0x00070000
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_GET(x) (((x) & 0x00070000) >> 16)
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25VGA5G_SET(x) (((x) << 16) & 0x00070000)
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_MSB 21
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_LSB 19
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_MASK 0x00380000
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_GET(x) (((x) & 0x00380000) >> 19)
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA5G_SET(x) (((x) << 19) & 0x00380000)
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_MSB 24
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_LSB 22
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_MASK 0x01c00000
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_GET(x) (((x) & 0x01c00000) >> 22)
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IR25LO24_SET(x) (((x) << 22) & 0x01c00000)
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_MSB 27
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_LSB 25
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_MASK 0x0e000000
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_GET(x) (((x) & 0x0e000000) >> 25)
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC25MXR2GH_SET(x) (((x) << 25) & 0x0e000000)
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_MSB 30
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_LSB 28
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_MASK 0x70000000
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_GET(x) (((x) & 0x70000000) >> 28)
-#define PHY_ANALOG_RXRF_BIAS1_PWD_IC75LNA2G_SET(x) (((x) << 28) & 0x70000000)
-#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_MSB 31
-#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_LSB 31
-#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_MASK 0x80000000
-#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_GET(x) (((x) & 0x80000000) >> 31)
-#define PHY_ANALOG_RXRF_BIAS1_PWD_BIAS_SET(x) (((x) << 31) & 0x80000000)
-
-/* macros for RXRF_BIAS2 */
-#define PHY_ANALOG_RXRF_BIAS2_ADDRESS 0x00000004
-#define PHY_ANALOG_RXRF_BIAS2_OFFSET 0x00000004
-#define PHY_ANALOG_RXRF_BIAS2_SPARE_MSB 0
-#define PHY_ANALOG_RXRF_BIAS2_SPARE_LSB 0
-#define PHY_ANALOG_RXRF_BIAS2_SPARE_MASK 0x00000001
-#define PHY_ANALOG_RXRF_BIAS2_SPARE_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_ANALOG_RXRF_BIAS2_SPARE_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_ANALOG_RXRF_BIAS2_PKEN_MSB 3
-#define PHY_ANALOG_RXRF_BIAS2_PKEN_LSB 1
-#define PHY_ANALOG_RXRF_BIAS2_PKEN_MASK 0x0000000e
-#define PHY_ANALOG_RXRF_BIAS2_PKEN_GET(x) (((x) & 0x0000000e) >> 1)
-#define PHY_ANALOG_RXRF_BIAS2_PKEN_SET(x) (((x) << 1) & 0x0000000e)
-#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_MSB 6
-#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_LSB 4
-#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_MASK 0x00000070
-#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_GET(x) (((x) & 0x00000070) >> 4)
-#define PHY_ANALOG_RXRF_BIAS2_VCMVALUE_SET(x) (((x) << 4) & 0x00000070)
-#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_MSB 7
-#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_LSB 7
-#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_MASK 0x00000080
-#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_GET(x) (((x) & 0x00000080) >> 7)
-#define PHY_ANALOG_RXRF_BIAS2_PWD_VCMBUF_SET(x) (((x) << 7) & 0x00000080)
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPAREH_MSB 10
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPAREH_LSB 8
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPAREH_MASK 0x00000700
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPAREH_GET(x) (((x) & 0x00000700) >> 8)
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPAREH_SET(x) (((x) << 8) & 0x00000700)
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPARE_MSB 13
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPARE_LSB 11
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPARE_MASK 0x00003800
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPARE_GET(x) (((x) & 0x00003800) >> 11)
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25SPARE_SET(x) (((x) << 11) & 0x00003800)
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25LNABUF_MSB 16
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25LNABUF_LSB 14
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25LNABUF_MASK 0x0001c000
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25LNABUF_GET(x) (((x) & 0x0001c000) >> 14)
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25LNABUF_SET(x) (((x) << 14) & 0x0001c000)
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGCH_MSB 19
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGCH_LSB 17
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGCH_MASK 0x000e0000
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGCH_GET(x) (((x) & 0x000e0000) >> 17)
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGCH_SET(x) (((x) << 17) & 0x000e0000)
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC_MSB 22
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC_LSB 20
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC_MASK 0x00700000
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC_GET(x) (((x) & 0x00700000) >> 20)
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25AGC_SET(x) (((x) << 20) & 0x00700000)
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC_MSB 25
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC_LSB 23
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC_MASK 0x03800000
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC_GET(x) (((x) & 0x03800000) >> 23)
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25AGC_SET(x) (((x) << 23) & 0x03800000)
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_MSB 28
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_LSB 26
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_MASK 0x1c000000
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_GET(x) (((x) & 0x1c000000) >> 26)
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IC25VCMBUF_SET(x) (((x) << 26) & 0x1c000000)
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_MSB 31
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_LSB 29
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_MASK 0xe0000000
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_GET(x) (((x) & 0xe0000000) >> 29)
-#define PHY_ANALOG_RXRF_BIAS2_PWD_IR25VCM_SET(x) (((x) << 29) & 0xe0000000)
-
-/* macros for RXRF_GAINSTAGES */
-#define PHY_ANALOG_RXRF_GAINSTAGES_ADDRESS 0x00000008
-#define PHY_ANALOG_RXRF_GAINSTAGES_OFFSET 0x00000008
-#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_MSB 0
-#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_LSB 0
-#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_MASK 0x00000001
-#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_ANALOG_RXRF_GAINSTAGES_SPARE_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_MSB 1
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_LSB 1
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_MASK 0x00000002
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_GET(x) (((x) & 0x00000002) >> 1)
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNAON_CALDC_SET(x) (((x) << 1) & 0x00000002)
-#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_MSB 3
-#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_LSB 2
-#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_MASK 0x0000000c
-#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_GET(x) (((x) & 0x0000000c) >> 2)
-#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_CAP_SET(x) (((x) << 2) & 0x0000000c)
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_MSB 5
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_LSB 4
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_MASK 0x00000030
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_GET(x) (((x) & 0x00000030) >> 4)
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_CAP_SET(x) (((x) << 4) & 0x00000030)
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_MSB 6
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_LSB 6
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_MASK 0x00000040
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_GET(x) (((x) & 0x00000040) >> 6)
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_SHORTINP_SET(x) (((x) << 6) & 0x00000040)
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_MSB 7
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_LSB 7
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_MASK 0x00000080
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_GET(x) (((x) & 0x00000080) >> 7)
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO5G_SET(x) (((x) << 7) & 0x00000080)
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_MSB 8
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_LSB 8
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_MASK 0x00000100
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_GET(x) (((x) & 0x00000100) >> 8)
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_VGA5G_SET(x) (((x) << 8) & 0x00000100)
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_MSB 9
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_LSB 9
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_MASK 0x00000200
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_GET(x) (((x) & 0x00000200) >> 9)
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR5G_SET(x) (((x) << 9) & 0x00000200)
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_MSB 10
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_LSB 10
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_MASK 0x00000400
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_GET(x) (((x) & 0x00000400) >> 10)
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA5G_SET(x) (((x) << 10) & 0x00000400)
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_MSB 12
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_LSB 11
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_MASK 0x00001800
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_GET(x) (((x) & 0x00001800) >> 11)
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_CAP_SET(x) (((x) << 11) & 0x00001800)
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_MSB 13
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_LSB 13
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_MASK 0x00002000
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_GET(x) (((x) & 0x00002000) >> 13)
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_SHORTINP_SET(x) (((x) << 13) & 0x00002000)
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_MSB 14
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_LSB 14
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_MASK 0x00004000
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_GET(x) (((x) & 0x00004000) >> 14)
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_LP_SET(x) (((x) << 14) & 0x00004000)
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_MSB 15
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_LSB 15
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_MASK 0x00008000
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_GET(x) (((x) & 0x00008000) >> 15)
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LO2G_SET(x) (((x) << 15) & 0x00008000)
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_MSB 16
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_LSB 16
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_MASK 0x00010000
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_GET(x) (((x) & 0x00010000) >> 16)
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_MXR2G_SET(x) (((x) << 16) & 0x00010000)
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_MSB 17
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_LSB 17
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_MASK 0x00020000
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_GET(x) (((x) & 0x00020000) >> 17)
-#define PHY_ANALOG_RXRF_GAINSTAGES_PWD_LNA2G_SET(x) (((x) << 17) & 0x00020000)
-#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_MSB 19
-#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_LSB 18
-#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_MASK 0x000c0000
-#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_GET(x) (((x) & 0x000c0000) >> 18)
-#define PHY_ANALOG_RXRF_GAINSTAGES_MXR5G_GAIN_OVR_SET(x) (((x) << 18) & 0x000c0000)
-#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_MSB 22
-#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_LSB 20
-#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_MASK 0x00700000
-#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_GET(x) (((x) & 0x00700000) >> 20)
-#define PHY_ANALOG_RXRF_GAINSTAGES_VGA5G_GAIN_OVR_SET(x) (((x) << 20) & 0x00700000)
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_MSB 25
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_LSB 23
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_MASK 0x03800000
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_GET(x) (((x) & 0x03800000) >> 23)
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA5G_GAIN_OVR_SET(x) (((x) << 23) & 0x03800000)
-#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_MSB 27
-#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_LSB 26
-#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_MASK 0x0c000000
-#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_GET(x) (((x) & 0x0c000000) >> 26)
-#define PHY_ANALOG_RXRF_GAINSTAGES_MXR2G_GAIN_OVR_SET(x) (((x) << 26) & 0x0c000000)
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_MSB 30
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_LSB 28
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_MASK 0x70000000
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_GET(x) (((x) & 0x70000000) >> 28)
-#define PHY_ANALOG_RXRF_GAINSTAGES_LNA2G_GAIN_OVR_SET(x) (((x) << 28) & 0x70000000)
-#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_MSB 31
-#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_LSB 31
-#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_MASK 0x80000000
-#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_GET(x) (((x) & 0x80000000) >> 31)
-#define PHY_ANALOG_RXRF_GAINSTAGES_RX_OVERRIDE_SET(x) (((x) << 31) & 0x80000000)
-
-/* macros for RXRF_AGC */
-#define PHY_ANALOG_RXRF_AGC_ADDRESS 0x0000000c
-#define PHY_ANALOG_RXRF_AGC_OFFSET 0x0000000c
-#define PHY_ANALOG_RXRF_AGC_RF5G_ON_DURING_CALPA_MSB 0
-#define PHY_ANALOG_RXRF_AGC_RF5G_ON_DURING_CALPA_LSB 0
-#define PHY_ANALOG_RXRF_AGC_RF5G_ON_DURING_CALPA_MASK 0x00000001
-#define PHY_ANALOG_RXRF_AGC_RF5G_ON_DURING_CALPA_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_ANALOG_RXRF_AGC_RF5G_ON_DURING_CALPA_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_ANALOG_RXRF_AGC_RF2G_ON_DURING_CALPA_MSB 1
-#define PHY_ANALOG_RXRF_AGC_RF2G_ON_DURING_CALPA_LSB 1
-#define PHY_ANALOG_RXRF_AGC_RF2G_ON_DURING_CALPA_MASK 0x00000002
-#define PHY_ANALOG_RXRF_AGC_RF2G_ON_DURING_CALPA_GET(x) (((x) & 0x00000002) >> 1)
-#define PHY_ANALOG_RXRF_AGC_RF2G_ON_DURING_CALPA_SET(x) (((x) << 1) & 0x00000002)
-#define PHY_ANALOG_RXRF_AGC_AGC_OUT_MSB 2
-#define PHY_ANALOG_RXRF_AGC_AGC_OUT_LSB 2
-#define PHY_ANALOG_RXRF_AGC_AGC_OUT_MASK 0x00000004
-#define PHY_ANALOG_RXRF_AGC_AGC_OUT_GET(x) (((x) & 0x00000004) >> 2)
-#define PHY_ANALOG_RXRF_AGC_LNABUFGAIN2X_MSB 3
-#define PHY_ANALOG_RXRF_AGC_LNABUFGAIN2X_LSB 3
-#define PHY_ANALOG_RXRF_AGC_LNABUFGAIN2X_MASK 0x00000008
-#define PHY_ANALOG_RXRF_AGC_LNABUFGAIN2X_GET(x) (((x) & 0x00000008) >> 3)
-#define PHY_ANALOG_RXRF_AGC_LNABUFGAIN2X_SET(x) (((x) << 3) & 0x00000008)
-#define PHY_ANALOG_RXRF_AGC_LNABUF_PWD_OVR_MSB 4
-#define PHY_ANALOG_RXRF_AGC_LNABUF_PWD_OVR_LSB 4
-#define PHY_ANALOG_RXRF_AGC_LNABUF_PWD_OVR_MASK 0x00000010
-#define PHY_ANALOG_RXRF_AGC_LNABUF_PWD_OVR_GET(x) (((x) & 0x00000010) >> 4)
-#define PHY_ANALOG_RXRF_AGC_LNABUF_PWD_OVR_SET(x) (((x) << 4) & 0x00000010)
-#define PHY_ANALOG_RXRF_AGC_PWD_LNABUF_MSB 5
-#define PHY_ANALOG_RXRF_AGC_PWD_LNABUF_LSB 5
-#define PHY_ANALOG_RXRF_AGC_PWD_LNABUF_MASK 0x00000020
-#define PHY_ANALOG_RXRF_AGC_PWD_LNABUF_GET(x) (((x) & 0x00000020) >> 5)
-#define PHY_ANALOG_RXRF_AGC_PWD_LNABUF_SET(x) (((x) << 5) & 0x00000020)
-#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_MSB 8
-#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_LSB 6
-#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_MASK 0x000001c0
-#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_GET(x) (((x) & 0x000001c0) >> 6)
-#define PHY_ANALOG_RXRF_AGC_AGC_FALL_CTRL_SET(x) (((x) << 6) & 0x000001c0)
-#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_MSB 14
-#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_LSB 9
-#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_MASK 0x00007e00
-#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_GET(x) (((x) & 0x00007e00) >> 9)
-#define PHY_ANALOG_RXRF_AGC_AGC5G_CALDAC_OVR_SET(x) (((x) << 9) & 0x00007e00)
-#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_MSB 18
-#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_LSB 15
-#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_MASK 0x00078000
-#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_GET(x) (((x) & 0x00078000) >> 15)
-#define PHY_ANALOG_RXRF_AGC_AGC5G_DBDAC_OVR_SET(x) (((x) << 15) & 0x00078000)
-#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_MSB 24
-#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_LSB 19
-#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_MASK 0x01f80000
-#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_GET(x) (((x) & 0x01f80000) >> 19)
-#define PHY_ANALOG_RXRF_AGC_AGC2G_CALDAC_OVR_SET(x) (((x) << 19) & 0x01f80000)
-#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_MSB 28
-#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_LSB 25
-#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_MASK 0x1e000000
-#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_GET(x) (((x) & 0x1e000000) >> 25)
-#define PHY_ANALOG_RXRF_AGC_AGC2G_DBDAC_OVR_SET(x) (((x) << 25) & 0x1e000000)
-#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_MSB 29
-#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_LSB 29
-#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_MASK 0x20000000
-#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_GET(x) (((x) & 0x20000000) >> 29)
-#define PHY_ANALOG_RXRF_AGC_AGC_CAL_OVR_SET(x) (((x) << 29) & 0x20000000)
-#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_MSB 30
-#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_LSB 30
-#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_MASK 0x40000000
-#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_GET(x) (((x) & 0x40000000) >> 30)
-#define PHY_ANALOG_RXRF_AGC_AGC_ON_OVR_SET(x) (((x) << 30) & 0x40000000)
-#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_MSB 31
-#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_LSB 31
-#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_MASK 0x80000000
-#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_GET(x) (((x) & 0x80000000) >> 31)
-#define PHY_ANALOG_RXRF_AGC_AGC_OVERRIDE_SET(x) (((x) << 31) & 0x80000000)
-
-/* macros for TXRF1 */
-#define PHY_ANALOG_TXRF1_ADDRESS 0x00000040
-#define PHY_ANALOG_TXRF1_OFFSET 0x00000040
-#define PHY_ANALOG_TXRF1_PDLOBUF5G_MSB 0
-#define PHY_ANALOG_TXRF1_PDLOBUF5G_LSB 0
-#define PHY_ANALOG_TXRF1_PDLOBUF5G_MASK 0x00000001
-#define PHY_ANALOG_TXRF1_PDLOBUF5G_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_ANALOG_TXRF1_PDLOBUF5G_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_ANALOG_TXRF1_PDLODIV5G_MSB 1
-#define PHY_ANALOG_TXRF1_PDLODIV5G_LSB 1
-#define PHY_ANALOG_TXRF1_PDLODIV5G_MASK 0x00000002
-#define PHY_ANALOG_TXRF1_PDLODIV5G_GET(x) (((x) & 0x00000002) >> 1)
-#define PHY_ANALOG_TXRF1_PDLODIV5G_SET(x) (((x) << 1) & 0x00000002)
-#define PHY_ANALOG_TXRF1_LOBUF5GFORCED_MSB 2
-#define PHY_ANALOG_TXRF1_LOBUF5GFORCED_LSB 2
-#define PHY_ANALOG_TXRF1_LOBUF5GFORCED_MASK 0x00000004
-#define PHY_ANALOG_TXRF1_LOBUF5GFORCED_GET(x) (((x) & 0x00000004) >> 2)
-#define PHY_ANALOG_TXRF1_LOBUF5GFORCED_SET(x) (((x) << 2) & 0x00000004)
-#define PHY_ANALOG_TXRF1_LODIV5GFORCED_MSB 3
-#define PHY_ANALOG_TXRF1_LODIV5GFORCED_LSB 3
-#define PHY_ANALOG_TXRF1_LODIV5GFORCED_MASK 0x00000008
-#define PHY_ANALOG_TXRF1_LODIV5GFORCED_GET(x) (((x) & 0x00000008) >> 3)
-#define PHY_ANALOG_TXRF1_LODIV5GFORCED_SET(x) (((x) << 3) & 0x00000008)
-#define PHY_ANALOG_TXRF1_PADRV2GN5G_MSB 7
-#define PHY_ANALOG_TXRF1_PADRV2GN5G_LSB 4
-#define PHY_ANALOG_TXRF1_PADRV2GN5G_MASK 0x000000f0
-#define PHY_ANALOG_TXRF1_PADRV2GN5G_GET(x) (((x) & 0x000000f0) >> 4)
-#define PHY_ANALOG_TXRF1_PADRV2GN5G_SET(x) (((x) << 4) & 0x000000f0)
-#define PHY_ANALOG_TXRF1_PADRV3GN5G_MSB 11
-#define PHY_ANALOG_TXRF1_PADRV3GN5G_LSB 8
-#define PHY_ANALOG_TXRF1_PADRV3GN5G_MASK 0x00000f00
-#define PHY_ANALOG_TXRF1_PADRV3GN5G_GET(x) (((x) & 0x00000f00) >> 8)
-#define PHY_ANALOG_TXRF1_PADRV3GN5G_SET(x) (((x) << 8) & 0x00000f00)
-#define PHY_ANALOG_TXRF1_PADRV4GN5G_MSB 15
-#define PHY_ANALOG_TXRF1_PADRV4GN5G_LSB 12
-#define PHY_ANALOG_TXRF1_PADRV4GN5G_MASK 0x0000f000
-#define PHY_ANALOG_TXRF1_PADRV4GN5G_GET(x) (((x) & 0x0000f000) >> 12)
-#define PHY_ANALOG_TXRF1_PADRV4GN5G_SET(x) (((x) << 12) & 0x0000f000)
-#define PHY_ANALOG_TXRF1_LOCALTXGAIN5G_MSB 16
-#define PHY_ANALOG_TXRF1_LOCALTXGAIN5G_LSB 16
-#define PHY_ANALOG_TXRF1_LOCALTXGAIN5G_MASK 0x00010000
-#define PHY_ANALOG_TXRF1_LOCALTXGAIN5G_GET(x) (((x) & 0x00010000) >> 16)
-#define PHY_ANALOG_TXRF1_LOCALTXGAIN5G_SET(x) (((x) << 16) & 0x00010000)
-#define PHY_ANALOG_TXRF1_PDOUT2G_MSB 17
-#define PHY_ANALOG_TXRF1_PDOUT2G_LSB 17
-#define PHY_ANALOG_TXRF1_PDOUT2G_MASK 0x00020000
-#define PHY_ANALOG_TXRF1_PDOUT2G_GET(x) (((x) & 0x00020000) >> 17)
-#define PHY_ANALOG_TXRF1_PDOUT2G_SET(x) (((x) << 17) & 0x00020000)
-#define PHY_ANALOG_TXRF1_PDDR2G_MSB 18
-#define PHY_ANALOG_TXRF1_PDDR2G_LSB 18
-#define PHY_ANALOG_TXRF1_PDDR2G_MASK 0x00040000
-#define PHY_ANALOG_TXRF1_PDDR2G_GET(x) (((x) & 0x00040000) >> 18)
-#define PHY_ANALOG_TXRF1_PDDR2G_SET(x) (((x) << 18) & 0x00040000)
-#define PHY_ANALOG_TXRF1_PDMXR2G_MSB 19
-#define PHY_ANALOG_TXRF1_PDMXR2G_LSB 19
-#define PHY_ANALOG_TXRF1_PDMXR2G_MASK 0x00080000
-#define PHY_ANALOG_TXRF1_PDMXR2G_GET(x) (((x) & 0x00080000) >> 19)
-#define PHY_ANALOG_TXRF1_PDMXR2G_SET(x) (((x) << 19) & 0x00080000)
-#define PHY_ANALOG_TXRF1_PDLOBUF2G_MSB 20
-#define PHY_ANALOG_TXRF1_PDLOBUF2G_LSB 20
-#define PHY_ANALOG_TXRF1_PDLOBUF2G_MASK 0x00100000
-#define PHY_ANALOG_TXRF1_PDLOBUF2G_GET(x) (((x) & 0x00100000) >> 20)
-#define PHY_ANALOG_TXRF1_PDLOBUF2G_SET(x) (((x) << 20) & 0x00100000)
-#define PHY_ANALOG_TXRF1_PDLODIV2G_MSB 21
-#define PHY_ANALOG_TXRF1_PDLODIV2G_LSB 21
-#define PHY_ANALOG_TXRF1_PDLODIV2G_MASK 0x00200000
-#define PHY_ANALOG_TXRF1_PDLODIV2G_GET(x) (((x) & 0x00200000) >> 21)
-#define PHY_ANALOG_TXRF1_PDLODIV2G_SET(x) (((x) << 21) & 0x00200000)
-#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_MSB 22
-#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_LSB 22
-#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_MASK 0x00400000
-#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_GET(x) (((x) & 0x00400000) >> 22)
-#define PHY_ANALOG_TXRF1_LOBUF2GFORCED_SET(x) (((x) << 22) & 0x00400000)
-#define PHY_ANALOG_TXRF1_LODIV2GFORCED_MSB 23
-#define PHY_ANALOG_TXRF1_LODIV2GFORCED_LSB 23
-#define PHY_ANALOG_TXRF1_LODIV2GFORCED_MASK 0x00800000
-#define PHY_ANALOG_TXRF1_LODIV2GFORCED_GET(x) (((x) & 0x00800000) >> 23)
-#define PHY_ANALOG_TXRF1_LODIV2GFORCED_SET(x) (((x) << 23) & 0x00800000)
-#define PHY_ANALOG_TXRF1_PADRVGN2G_MSB 30
-#define PHY_ANALOG_TXRF1_PADRVGN2G_LSB 24
-#define PHY_ANALOG_TXRF1_PADRVGN2G_MASK 0x7f000000
-#define PHY_ANALOG_TXRF1_PADRVGN2G_GET(x) (((x) & 0x7f000000) >> 24)
-#define PHY_ANALOG_TXRF1_PADRVGN2G_SET(x) (((x) << 24) & 0x7f000000)
-#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_MSB 31
-#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_LSB 31
-#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_MASK 0x80000000
-#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_GET(x) (((x) & 0x80000000) >> 31)
-#define PHY_ANALOG_TXRF1_LOCALTXGAIN2G_SET(x) (((x) << 31) & 0x80000000)
-
-/* macros for TXRF2 */
-#define PHY_ANALOG_TXRF2_ADDRESS 0x00000044
-#define PHY_ANALOG_TXRF2_OFFSET 0x00000044
-#define PHY_ANALOG_TXRF2_D3B5G_MSB 2
-#define PHY_ANALOG_TXRF2_D3B5G_LSB 0
-#define PHY_ANALOG_TXRF2_D3B5G_MASK 0x00000007
-#define PHY_ANALOG_TXRF2_D3B5G_GET(x) (((x) & 0x00000007) >> 0)
-#define PHY_ANALOG_TXRF2_D3B5G_SET(x) (((x) << 0) & 0x00000007)
-#define PHY_ANALOG_TXRF2_D4B5G_MSB 5
-#define PHY_ANALOG_TXRF2_D4B5G_LSB 3
-#define PHY_ANALOG_TXRF2_D4B5G_MASK 0x00000038
-#define PHY_ANALOG_TXRF2_D4B5G_GET(x) (((x) & 0x00000038) >> 3)
-#define PHY_ANALOG_TXRF2_D4B5G_SET(x) (((x) << 3) & 0x00000038)
-#define PHY_ANALOG_TXRF2_OCAS2G_MSB 8
-#define PHY_ANALOG_TXRF2_OCAS2G_LSB 6
-#define PHY_ANALOG_TXRF2_OCAS2G_MASK 0x000001c0
-#define PHY_ANALOG_TXRF2_OCAS2G_GET(x) (((x) & 0x000001c0) >> 6)
-#define PHY_ANALOG_TXRF2_OCAS2G_SET(x) (((x) << 6) & 0x000001c0)
-#define PHY_ANALOG_TXRF2_DCAS2G_MSB 11
-#define PHY_ANALOG_TXRF2_DCAS2G_LSB 9
-#define PHY_ANALOG_TXRF2_DCAS2G_MASK 0x00000e00
-#define PHY_ANALOG_TXRF2_DCAS2G_GET(x) (((x) & 0x00000e00) >> 9)
-#define PHY_ANALOG_TXRF2_DCAS2G_SET(x) (((x) << 9) & 0x00000e00)
-#define PHY_ANALOG_TXRF2_OB2G_PALOFF_MSB 14
-#define PHY_ANALOG_TXRF2_OB2G_PALOFF_LSB 12
-#define PHY_ANALOG_TXRF2_OB2G_PALOFF_MASK 0x00007000
-#define PHY_ANALOG_TXRF2_OB2G_PALOFF_GET(x) (((x) & 0x00007000) >> 12)
-#define PHY_ANALOG_TXRF2_OB2G_PALOFF_SET(x) (((x) << 12) & 0x00007000)
-#define PHY_ANALOG_TXRF2_OB2G_QAM_MSB 17
-#define PHY_ANALOG_TXRF2_OB2G_QAM_LSB 15
-#define PHY_ANALOG_TXRF2_OB2G_QAM_MASK 0x00038000
-#define PHY_ANALOG_TXRF2_OB2G_QAM_GET(x) (((x) & 0x00038000) >> 15)
-#define PHY_ANALOG_TXRF2_OB2G_QAM_SET(x) (((x) << 15) & 0x00038000)
-#define PHY_ANALOG_TXRF2_OB2G_PSK_MSB 20
-#define PHY_ANALOG_TXRF2_OB2G_PSK_LSB 18
-#define PHY_ANALOG_TXRF2_OB2G_PSK_MASK 0x001c0000
-#define PHY_ANALOG_TXRF2_OB2G_PSK_GET(x) (((x) & 0x001c0000) >> 18)
-#define PHY_ANALOG_TXRF2_OB2G_PSK_SET(x) (((x) << 18) & 0x001c0000)
-#define PHY_ANALOG_TXRF2_OB2G_CCK_MSB 23
-#define PHY_ANALOG_TXRF2_OB2G_CCK_LSB 21
-#define PHY_ANALOG_TXRF2_OB2G_CCK_MASK 0x00e00000
-#define PHY_ANALOG_TXRF2_OB2G_CCK_GET(x) (((x) & 0x00e00000) >> 21)
-#define PHY_ANALOG_TXRF2_OB2G_CCK_SET(x) (((x) << 21) & 0x00e00000)
-#define PHY_ANALOG_TXRF2_DB2G_MSB 26
-#define PHY_ANALOG_TXRF2_DB2G_LSB 24
-#define PHY_ANALOG_TXRF2_DB2G_MASK 0x07000000
-#define PHY_ANALOG_TXRF2_DB2G_GET(x) (((x) & 0x07000000) >> 24)
-#define PHY_ANALOG_TXRF2_DB2G_SET(x) (((x) << 24) & 0x07000000)
-#define PHY_ANALOG_TXRF2_PDOUT5G_MSB 30
-#define PHY_ANALOG_TXRF2_PDOUT5G_LSB 27
-#define PHY_ANALOG_TXRF2_PDOUT5G_MASK 0x78000000
-#define PHY_ANALOG_TXRF2_PDOUT5G_GET(x) (((x) & 0x78000000) >> 27)
-#define PHY_ANALOG_TXRF2_PDOUT5G_SET(x) (((x) << 27) & 0x78000000)
-#define PHY_ANALOG_TXRF2_PDMXR5G_MSB 31
-#define PHY_ANALOG_TXRF2_PDMXR5G_LSB 31
-#define PHY_ANALOG_TXRF2_PDMXR5G_MASK 0x80000000
-#define PHY_ANALOG_TXRF2_PDMXR5G_GET(x) (((x) & 0x80000000) >> 31)
-#define PHY_ANALOG_TXRF2_PDMXR5G_SET(x) (((x) << 31) & 0x80000000)
-
-/* macros for TXRF3 */
-#define PHY_ANALOG_TXRF3_ADDRESS 0x00000048
-#define PHY_ANALOG_TXRF3_OFFSET 0x00000048
-#define PHY_ANALOG_TXRF3_FILTR2G_MSB 1
-#define PHY_ANALOG_TXRF3_FILTR2G_LSB 0
-#define PHY_ANALOG_TXRF3_FILTR2G_MASK 0x00000003
-#define PHY_ANALOG_TXRF3_FILTR2G_GET(x) (((x) & 0x00000003) >> 0)
-#define PHY_ANALOG_TXRF3_FILTR2G_SET(x) (((x) << 0) & 0x00000003)
-#define PHY_ANALOG_TXRF3_PWDFB2_2G_MSB 2
-#define PHY_ANALOG_TXRF3_PWDFB2_2G_LSB 2
-#define PHY_ANALOG_TXRF3_PWDFB2_2G_MASK 0x00000004
-#define PHY_ANALOG_TXRF3_PWDFB2_2G_GET(x) (((x) & 0x00000004) >> 2)
-#define PHY_ANALOG_TXRF3_PWDFB2_2G_SET(x) (((x) << 2) & 0x00000004)
-#define PHY_ANALOG_TXRF3_PWDFB1_2G_MSB 3
-#define PHY_ANALOG_TXRF3_PWDFB1_2G_LSB 3
-#define PHY_ANALOG_TXRF3_PWDFB1_2G_MASK 0x00000008
-#define PHY_ANALOG_TXRF3_PWDFB1_2G_GET(x) (((x) & 0x00000008) >> 3)
-#define PHY_ANALOG_TXRF3_PWDFB1_2G_SET(x) (((x) << 3) & 0x00000008)
-#define PHY_ANALOG_TXRF3_PDFB2G_MSB 4
-#define PHY_ANALOG_TXRF3_PDFB2G_LSB 4
-#define PHY_ANALOG_TXRF3_PDFB2G_MASK 0x00000010
-#define PHY_ANALOG_TXRF3_PDFB2G_GET(x) (((x) & 0x00000010) >> 4)
-#define PHY_ANALOG_TXRF3_PDFB2G_SET(x) (((x) << 4) & 0x00000010)
-#define PHY_ANALOG_TXRF3_RDIV5G_MSB 6
-#define PHY_ANALOG_TXRF3_RDIV5G_LSB 5
-#define PHY_ANALOG_TXRF3_RDIV5G_MASK 0x00000060
-#define PHY_ANALOG_TXRF3_RDIV5G_GET(x) (((x) & 0x00000060) >> 5)
-#define PHY_ANALOG_TXRF3_RDIV5G_SET(x) (((x) << 5) & 0x00000060)
-#define PHY_ANALOG_TXRF3_CAPDIV5G_MSB 9
-#define PHY_ANALOG_TXRF3_CAPDIV5G_LSB 7
-#define PHY_ANALOG_TXRF3_CAPDIV5G_MASK 0x00000380
-#define PHY_ANALOG_TXRF3_CAPDIV5G_GET(x) (((x) & 0x00000380) >> 7)
-#define PHY_ANALOG_TXRF3_CAPDIV5G_SET(x) (((x) << 7) & 0x00000380)
-#define PHY_ANALOG_TXRF3_PDPREDIST5G_MSB 10
-#define PHY_ANALOG_TXRF3_PDPREDIST5G_LSB 10
-#define PHY_ANALOG_TXRF3_PDPREDIST5G_MASK 0x00000400
-#define PHY_ANALOG_TXRF3_PDPREDIST5G_GET(x) (((x) & 0x00000400) >> 10)
-#define PHY_ANALOG_TXRF3_PDPREDIST5G_SET(x) (((x) << 10) & 0x00000400)
-#define PHY_ANALOG_TXRF3_RDIV2G_MSB 12
-#define PHY_ANALOG_TXRF3_RDIV2G_LSB 11
-#define PHY_ANALOG_TXRF3_RDIV2G_MASK 0x00001800
-#define PHY_ANALOG_TXRF3_RDIV2G_GET(x) (((x) & 0x00001800) >> 11)
-#define PHY_ANALOG_TXRF3_RDIV2G_SET(x) (((x) << 11) & 0x00001800)
-#define PHY_ANALOG_TXRF3_PDPREDIST2G_MSB 13
-#define PHY_ANALOG_TXRF3_PDPREDIST2G_LSB 13
-#define PHY_ANALOG_TXRF3_PDPREDIST2G_MASK 0x00002000
-#define PHY_ANALOG_TXRF3_PDPREDIST2G_GET(x) (((x) & 0x00002000) >> 13)
-#define PHY_ANALOG_TXRF3_PDPREDIST2G_SET(x) (((x) << 13) & 0x00002000)
-#define PHY_ANALOG_TXRF3_OCAS5G_MSB 16
-#define PHY_ANALOG_TXRF3_OCAS5G_LSB 14
-#define PHY_ANALOG_TXRF3_OCAS5G_MASK 0x0001c000
-#define PHY_ANALOG_TXRF3_OCAS5G_GET(x) (((x) & 0x0001c000) >> 14)
-#define PHY_ANALOG_TXRF3_OCAS5G_SET(x) (((x) << 14) & 0x0001c000)
-#define PHY_ANALOG_TXRF3_D2CAS5G_MSB 19
-#define PHY_ANALOG_TXRF3_D2CAS5G_LSB 17
-#define PHY_ANALOG_TXRF3_D2CAS5G_MASK 0x000e0000
-#define PHY_ANALOG_TXRF3_D2CAS5G_GET(x) (((x) & 0x000e0000) >> 17)
-#define PHY_ANALOG_TXRF3_D2CAS5G_SET(x) (((x) << 17) & 0x000e0000)
-#define PHY_ANALOG_TXRF3_D3CAS5G_MSB 22
-#define PHY_ANALOG_TXRF3_D3CAS5G_LSB 20
-#define PHY_ANALOG_TXRF3_D3CAS5G_MASK 0x00700000
-#define PHY_ANALOG_TXRF3_D3CAS5G_GET(x) (((x) & 0x00700000) >> 20)
-#define PHY_ANALOG_TXRF3_D3CAS5G_SET(x) (((x) << 20) & 0x00700000)
-#define PHY_ANALOG_TXRF3_D4CAS5G_MSB 25
-#define PHY_ANALOG_TXRF3_D4CAS5G_LSB 23
-#define PHY_ANALOG_TXRF3_D4CAS5G_MASK 0x03800000
-#define PHY_ANALOG_TXRF3_D4CAS5G_GET(x) (((x) & 0x03800000) >> 23)
-#define PHY_ANALOG_TXRF3_D4CAS5G_SET(x) (((x) << 23) & 0x03800000)
-#define PHY_ANALOG_TXRF3_OB5G_MSB 28
-#define PHY_ANALOG_TXRF3_OB5G_LSB 26
-#define PHY_ANALOG_TXRF3_OB5G_MASK 0x1c000000
-#define PHY_ANALOG_TXRF3_OB5G_GET(x) (((x) & 0x1c000000) >> 26)
-#define PHY_ANALOG_TXRF3_OB5G_SET(x) (((x) << 26) & 0x1c000000)
-#define PHY_ANALOG_TXRF3_D2B5G_MSB 31
-#define PHY_ANALOG_TXRF3_D2B5G_LSB 29
-#define PHY_ANALOG_TXRF3_D2B5G_MASK 0xe0000000
-#define PHY_ANALOG_TXRF3_D2B5G_GET(x) (((x) & 0xe0000000) >> 29)
-#define PHY_ANALOG_TXRF3_D2B5G_SET(x) (((x) << 29) & 0xe0000000)
-
-/* macros for TXRF4 */
-#define PHY_ANALOG_TXRF4_ADDRESS 0x0000004c
-#define PHY_ANALOG_TXRF4_OFFSET 0x0000004c
-#define PHY_ANALOG_TXRF4_PK1B2G_CCK_MSB 1
-#define PHY_ANALOG_TXRF4_PK1B2G_CCK_LSB 0
-#define PHY_ANALOG_TXRF4_PK1B2G_CCK_MASK 0x00000003
-#define PHY_ANALOG_TXRF4_PK1B2G_CCK_GET(x) (((x) & 0x00000003) >> 0)
-#define PHY_ANALOG_TXRF4_PK1B2G_CCK_SET(x) (((x) << 0) & 0x00000003)
-#define PHY_ANALOG_TXRF4_MIOB2G_QAM_MSB 4
-#define PHY_ANALOG_TXRF4_MIOB2G_QAM_LSB 2
-#define PHY_ANALOG_TXRF4_MIOB2G_QAM_MASK 0x0000001c
-#define PHY_ANALOG_TXRF4_MIOB2G_QAM_GET(x) (((x) & 0x0000001c) >> 2)
-#define PHY_ANALOG_TXRF4_MIOB2G_QAM_SET(x) (((x) << 2) & 0x0000001c)
-#define PHY_ANALOG_TXRF4_MIOB2G_PSK_MSB 7
-#define PHY_ANALOG_TXRF4_MIOB2G_PSK_LSB 5
-#define PHY_ANALOG_TXRF4_MIOB2G_PSK_MASK 0x000000e0
-#define PHY_ANALOG_TXRF4_MIOB2G_PSK_GET(x) (((x) & 0x000000e0) >> 5)
-#define PHY_ANALOG_TXRF4_MIOB2G_PSK_SET(x) (((x) << 5) & 0x000000e0)
-#define PHY_ANALOG_TXRF4_MIOB2G_CCK_MSB 10
-#define PHY_ANALOG_TXRF4_MIOB2G_CCK_LSB 8
-#define PHY_ANALOG_TXRF4_MIOB2G_CCK_MASK 0x00000700
-#define PHY_ANALOG_TXRF4_MIOB2G_CCK_GET(x) (((x) & 0x00000700) >> 8)
-#define PHY_ANALOG_TXRF4_MIOB2G_CCK_SET(x) (((x) << 8) & 0x00000700)
-#define PHY_ANALOG_TXRF4_COMP2G_QAM_MSB 13
-#define PHY_ANALOG_TXRF4_COMP2G_QAM_LSB 11
-#define PHY_ANALOG_TXRF4_COMP2G_QAM_MASK 0x00003800
-#define PHY_ANALOG_TXRF4_COMP2G_QAM_GET(x) (((x) & 0x00003800) >> 11)
-#define PHY_ANALOG_TXRF4_COMP2G_QAM_SET(x) (((x) << 11) & 0x00003800)
-#define PHY_ANALOG_TXRF4_COMP2G_PSK_MSB 16
-#define PHY_ANALOG_TXRF4_COMP2G_PSK_LSB 14
-#define PHY_ANALOG_TXRF4_COMP2G_PSK_MASK 0x0001c000
-#define PHY_ANALOG_TXRF4_COMP2G_PSK_GET(x) (((x) & 0x0001c000) >> 14)
-#define PHY_ANALOG_TXRF4_COMP2G_PSK_SET(x) (((x) << 14) & 0x0001c000)
-#define PHY_ANALOG_TXRF4_COMP2G_CCK_MSB 19
-#define PHY_ANALOG_TXRF4_COMP2G_CCK_LSB 17
-#define PHY_ANALOG_TXRF4_COMP2G_CCK_MASK 0x000e0000
-#define PHY_ANALOG_TXRF4_COMP2G_CCK_GET(x) (((x) & 0x000e0000) >> 17)
-#define PHY_ANALOG_TXRF4_COMP2G_CCK_SET(x) (((x) << 17) & 0x000e0000)
-#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_MSB 22
-#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_LSB 20
-#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_MASK 0x00700000
-#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_GET(x) (((x) & 0x00700000) >> 20)
-#define PHY_ANALOG_TXRF4_AMP2B2G_QAM_SET(x) (((x) << 20) & 0x00700000)
-#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_MSB 25
-#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_LSB 23
-#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_MASK 0x03800000
-#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_GET(x) (((x) & 0x03800000) >> 23)
-#define PHY_ANALOG_TXRF4_AMP2B2G_PSK_SET(x) (((x) << 23) & 0x03800000)
-#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_MSB 28
-#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_LSB 26
-#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_MASK 0x1c000000
-#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_GET(x) (((x) & 0x1c000000) >> 26)
-#define PHY_ANALOG_TXRF4_AMP2B2G_CCK_SET(x) (((x) << 26) & 0x1c000000)
-#define PHY_ANALOG_TXRF4_AMP2CAS2G_MSB 31
-#define PHY_ANALOG_TXRF4_AMP2CAS2G_LSB 29
-#define PHY_ANALOG_TXRF4_AMP2CAS2G_MASK 0xe0000000
-#define PHY_ANALOG_TXRF4_AMP2CAS2G_GET(x) (((x) & 0xe0000000) >> 29)
-#define PHY_ANALOG_TXRF4_AMP2CAS2G_SET(x) (((x) << 29) & 0xe0000000)
-
-/* macros for TXRF5 */
-#define PHY_ANALOG_TXRF5_ADDRESS 0x00000050
-#define PHY_ANALOG_TXRF5_OFFSET 0x00000050
-#define PHY_ANALOG_TXRF5_SPARE5_MSB 0
-#define PHY_ANALOG_TXRF5_SPARE5_LSB 0
-#define PHY_ANALOG_TXRF5_SPARE5_MASK 0x00000001
-#define PHY_ANALOG_TXRF5_SPARE5_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_ANALOG_TXRF5_SPARE5_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_ANALOG_TXRF5_PAL_LOCKED_MSB 1
-#define PHY_ANALOG_TXRF5_PAL_LOCKED_LSB 1
-#define PHY_ANALOG_TXRF5_PAL_LOCKED_MASK 0x00000002
-#define PHY_ANALOG_TXRF5_PAL_LOCKED_GET(x) (((x) & 0x00000002) >> 1)
-#define PHY_ANALOG_TXRF5_FBHI2G_MSB 2
-#define PHY_ANALOG_TXRF5_FBHI2G_LSB 2
-#define PHY_ANALOG_TXRF5_FBHI2G_MASK 0x00000004
-#define PHY_ANALOG_TXRF5_FBHI2G_GET(x) (((x) & 0x00000004) >> 2)
-#define PHY_ANALOG_TXRF5_FBLO2G_MSB 3
-#define PHY_ANALOG_TXRF5_FBLO2G_LSB 3
-#define PHY_ANALOG_TXRF5_FBLO2G_MASK 0x00000008
-#define PHY_ANALOG_TXRF5_FBLO2G_GET(x) (((x) & 0x00000008) >> 3)
-#define PHY_ANALOG_TXRF5_NOPALGAIN2G_MSB 4
-#define PHY_ANALOG_TXRF5_NOPALGAIN2G_LSB 4
-#define PHY_ANALOG_TXRF5_NOPALGAIN2G_MASK 0x00000010
-#define PHY_ANALOG_TXRF5_NOPALGAIN2G_GET(x) (((x) & 0x00000010) >> 4)
-#define PHY_ANALOG_TXRF5_NOPALGAIN2G_SET(x) (((x) << 4) & 0x00000010)
-#define PHY_ANALOG_TXRF5_ENPACAL2G_MSB 5
-#define PHY_ANALOG_TXRF5_ENPACAL2G_LSB 5
-#define PHY_ANALOG_TXRF5_ENPACAL2G_MASK 0x00000020
-#define PHY_ANALOG_TXRF5_ENPACAL2G_GET(x) (((x) & 0x00000020) >> 5)
-#define PHY_ANALOG_TXRF5_ENPACAL2G_SET(x) (((x) << 5) & 0x00000020)
-#define PHY_ANALOG_TXRF5_OFFSET2G_MSB 12
-#define PHY_ANALOG_TXRF5_OFFSET2G_LSB 6
-#define PHY_ANALOG_TXRF5_OFFSET2G_MASK 0x00001fc0
-#define PHY_ANALOG_TXRF5_OFFSET2G_GET(x) (((x) & 0x00001fc0) >> 6)
-#define PHY_ANALOG_TXRF5_OFFSET2G_SET(x) (((x) << 6) & 0x00001fc0)
-#define PHY_ANALOG_TXRF5_ENOFFSETCAL2G_MSB 13
-#define PHY_ANALOG_TXRF5_ENOFFSETCAL2G_LSB 13
-#define PHY_ANALOG_TXRF5_ENOFFSETCAL2G_MASK 0x00002000
-#define PHY_ANALOG_TXRF5_ENOFFSETCAL2G_GET(x) (((x) & 0x00002000) >> 13)
-#define PHY_ANALOG_TXRF5_ENOFFSETCAL2G_SET(x) (((x) << 13) & 0x00002000)
-#define PHY_ANALOG_TXRF5_REFHI2G_MSB 16
-#define PHY_ANALOG_TXRF5_REFHI2G_LSB 14
-#define PHY_ANALOG_TXRF5_REFHI2G_MASK 0x0001c000
-#define PHY_ANALOG_TXRF5_REFHI2G_GET(x) (((x) & 0x0001c000) >> 14)
-#define PHY_ANALOG_TXRF5_REFHI2G_SET(x) (((x) << 14) & 0x0001c000)
-#define PHY_ANALOG_TXRF5_REFLO2G_MSB 19
-#define PHY_ANALOG_TXRF5_REFLO2G_LSB 17
-#define PHY_ANALOG_TXRF5_REFLO2G_MASK 0x000e0000
-#define PHY_ANALOG_TXRF5_REFLO2G_GET(x) (((x) & 0x000e0000) >> 17)
-#define PHY_ANALOG_TXRF5_REFLO2G_SET(x) (((x) << 17) & 0x000e0000)
-#define PHY_ANALOG_TXRF5_PALCLAMP2G_MSB 21
-#define PHY_ANALOG_TXRF5_PALCLAMP2G_LSB 20
-#define PHY_ANALOG_TXRF5_PALCLAMP2G_MASK 0x00300000
-#define PHY_ANALOG_TXRF5_PALCLAMP2G_GET(x) (((x) & 0x00300000) >> 20)
-#define PHY_ANALOG_TXRF5_PALCLAMP2G_SET(x) (((x) << 20) & 0x00300000)
-#define PHY_ANALOG_TXRF5_PK2B2G_QAM_MSB 23
-#define PHY_ANALOG_TXRF5_PK2B2G_QAM_LSB 22
-#define PHY_ANALOG_TXRF5_PK2B2G_QAM_MASK 0x00c00000
-#define PHY_ANALOG_TXRF5_PK2B2G_QAM_GET(x) (((x) & 0x00c00000) >> 22)
-#define PHY_ANALOG_TXRF5_PK2B2G_QAM_SET(x) (((x) << 22) & 0x00c00000)
-#define PHY_ANALOG_TXRF5_PK2B2G_PSK_MSB 25
-#define PHY_ANALOG_TXRF5_PK2B2G_PSK_LSB 24
-#define PHY_ANALOG_TXRF5_PK2B2G_PSK_MASK 0x03000000
-#define PHY_ANALOG_TXRF5_PK2B2G_PSK_GET(x) (((x) & 0x03000000) >> 24)
-#define PHY_ANALOG_TXRF5_PK2B2G_PSK_SET(x) (((x) << 24) & 0x03000000)
-#define PHY_ANALOG_TXRF5_PK2B2G_CCK_MSB 27
-#define PHY_ANALOG_TXRF5_PK2B2G_CCK_LSB 26
-#define PHY_ANALOG_TXRF5_PK2B2G_CCK_MASK 0x0c000000
-#define PHY_ANALOG_TXRF5_PK2B2G_CCK_GET(x) (((x) & 0x0c000000) >> 26)
-#define PHY_ANALOG_TXRF5_PK2B2G_CCK_SET(x) (((x) << 26) & 0x0c000000)
-#define PHY_ANALOG_TXRF5_PK1B2G_QAM_MSB 29
-#define PHY_ANALOG_TXRF5_PK1B2G_QAM_LSB 28
-#define PHY_ANALOG_TXRF5_PK1B2G_QAM_MASK 0x30000000
-#define PHY_ANALOG_TXRF5_PK1B2G_QAM_GET(x) (((x) & 0x30000000) >> 28)
-#define PHY_ANALOG_TXRF5_PK1B2G_QAM_SET(x) (((x) << 28) & 0x30000000)
-#define PHY_ANALOG_TXRF5_PK1B2G_PSK_MSB 31
-#define PHY_ANALOG_TXRF5_PK1B2G_PSK_LSB 30
-#define PHY_ANALOG_TXRF5_PK1B2G_PSK_MASK 0xc0000000
-#define PHY_ANALOG_TXRF5_PK1B2G_PSK_GET(x) (((x) & 0xc0000000) >> 30)
-#define PHY_ANALOG_TXRF5_PK1B2G_PSK_SET(x) (((x) << 30) & 0xc0000000)
-
-/* macros for TXRF6 */
-#define PHY_ANALOG_TXRF6_ADDRESS 0x00000054
-#define PHY_ANALOG_TXRF6_OFFSET 0x00000054
-#define PHY_ANALOG_TXRF6_PALCLKGATE2G_MSB 0
-#define PHY_ANALOG_TXRF6_PALCLKGATE2G_LSB 0
-#define PHY_ANALOG_TXRF6_PALCLKGATE2G_MASK 0x00000001
-#define PHY_ANALOG_TXRF6_PALCLKGATE2G_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_ANALOG_TXRF6_PALCLKGATE2G_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_ANALOG_TXRF6_PALFLUCTCOUNT2G_MSB 8
-#define PHY_ANALOG_TXRF6_PALFLUCTCOUNT2G_LSB 1
-#define PHY_ANALOG_TXRF6_PALFLUCTCOUNT2G_MASK 0x000001fe
-#define PHY_ANALOG_TXRF6_PALFLUCTCOUNT2G_GET(x) (((x) & 0x000001fe) >> 1)
-#define PHY_ANALOG_TXRF6_PALFLUCTCOUNT2G_SET(x) (((x) << 1) & 0x000001fe)
-#define PHY_ANALOG_TXRF6_PALFLUCTGAIN2G_MSB 10
-#define PHY_ANALOG_TXRF6_PALFLUCTGAIN2G_LSB 9
-#define PHY_ANALOG_TXRF6_PALFLUCTGAIN2G_MASK 0x00000600
-#define PHY_ANALOG_TXRF6_PALFLUCTGAIN2G_GET(x) (((x) & 0x00000600) >> 9)
-#define PHY_ANALOG_TXRF6_PALFLUCTGAIN2G_SET(x) (((x) << 9) & 0x00000600)
-#define PHY_ANALOG_TXRF6_PALNOFLUCT2G_MSB 11
-#define PHY_ANALOG_TXRF6_PALNOFLUCT2G_LSB 11
-#define PHY_ANALOG_TXRF6_PALNOFLUCT2G_MASK 0x00000800
-#define PHY_ANALOG_TXRF6_PALNOFLUCT2G_GET(x) (((x) & 0x00000800) >> 11)
-#define PHY_ANALOG_TXRF6_PALNOFLUCT2G_SET(x) (((x) << 11) & 0x00000800)
-#define PHY_ANALOG_TXRF6_GAINSTEP2G_MSB 14
-#define PHY_ANALOG_TXRF6_GAINSTEP2G_LSB 12
-#define PHY_ANALOG_TXRF6_GAINSTEP2G_MASK 0x00007000
-#define PHY_ANALOG_TXRF6_GAINSTEP2G_GET(x) (((x) & 0x00007000) >> 12)
-#define PHY_ANALOG_TXRF6_GAINSTEP2G_SET(x) (((x) << 12) & 0x00007000)
-#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_MSB 15
-#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_LSB 15
-#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_MASK 0x00008000
-#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_GET(x) (((x) & 0x00008000) >> 15)
-#define PHY_ANALOG_TXRF6_USE_GAIN_DELTA2G_SET(x) (((x) << 15) & 0x00008000)
-#define PHY_ANALOG_TXRF6_CAPDIV_I2G_MSB 19
-#define PHY_ANALOG_TXRF6_CAPDIV_I2G_LSB 16
-#define PHY_ANALOG_TXRF6_CAPDIV_I2G_MASK 0x000f0000
-#define PHY_ANALOG_TXRF6_CAPDIV_I2G_GET(x) (((x) & 0x000f0000) >> 16)
-#define PHY_ANALOG_TXRF6_CAPDIV_I2G_SET(x) (((x) << 16) & 0x000f0000)
-#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_MSB 23
-#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_LSB 20
-#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_MASK 0x00f00000
-#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_GET(x) (((x) & 0x00f00000) >> 20)
-#define PHY_ANALOG_TXRF6_PADRVGN_INDEX_I2G_SET(x) (((x) << 20) & 0x00f00000)
-#define PHY_ANALOG_TXRF6_VCMONDELAY2G_MSB 26
-#define PHY_ANALOG_TXRF6_VCMONDELAY2G_LSB 24
-#define PHY_ANALOG_TXRF6_VCMONDELAY2G_MASK 0x07000000
-#define PHY_ANALOG_TXRF6_VCMONDELAY2G_GET(x) (((x) & 0x07000000) >> 24)
-#define PHY_ANALOG_TXRF6_VCMONDELAY2G_SET(x) (((x) << 24) & 0x07000000)
-#define PHY_ANALOG_TXRF6_CAPDIV2G_MSB 30
-#define PHY_ANALOG_TXRF6_CAPDIV2G_LSB 27
-#define PHY_ANALOG_TXRF6_CAPDIV2G_MASK 0x78000000
-#define PHY_ANALOG_TXRF6_CAPDIV2G_GET(x) (((x) & 0x78000000) >> 27)
-#define PHY_ANALOG_TXRF6_CAPDIV2G_SET(x) (((x) << 27) & 0x78000000)
-#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_MSB 31
-#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_LSB 31
-#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_MASK 0x80000000
-#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_GET(x) (((x) & 0x80000000) >> 31)
-#define PHY_ANALOG_TXRF6_CAPDIV2GOVR_SET(x) (((x) << 31) & 0x80000000)
-
-/* macros for TXRF7 */
-#define PHY_ANALOG_TXRF7_ADDRESS 0x00000058
-#define PHY_ANALOG_TXRF7_OFFSET 0x00000058
-#define PHY_ANALOG_TXRF7_SPARE7_MSB 1
-#define PHY_ANALOG_TXRF7_SPARE7_LSB 0
-#define PHY_ANALOG_TXRF7_SPARE7_MASK 0x00000003
-#define PHY_ANALOG_TXRF7_SPARE7_GET(x) (((x) & 0x00000003) >> 0)
-#define PHY_ANALOG_TXRF7_SPARE7_SET(x) (((x) << 0) & 0x00000003)
-#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_MSB 7
-#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_LSB 2
-#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_MASK 0x000000fc
-#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_GET(x) (((x) & 0x000000fc) >> 2)
-#define PHY_ANALOG_TXRF7_PADRVGNTAB_4_SET(x) (((x) << 2) & 0x000000fc)
-#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_MSB 13
-#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_LSB 8
-#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_MASK 0x00003f00
-#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_GET(x) (((x) & 0x00003f00) >> 8)
-#define PHY_ANALOG_TXRF7_PADRVGNTAB_3_SET(x) (((x) << 8) & 0x00003f00)
-#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_MSB 19
-#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_LSB 14
-#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_MASK 0x000fc000
-#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_GET(x) (((x) & 0x000fc000) >> 14)
-#define PHY_ANALOG_TXRF7_PADRVGNTAB_2_SET(x) (((x) << 14) & 0x000fc000)
-#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_MSB 25
-#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_LSB 20
-#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_MASK 0x03f00000
-#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_GET(x) (((x) & 0x03f00000) >> 20)
-#define PHY_ANALOG_TXRF7_PADRVGNTAB_1_SET(x) (((x) << 20) & 0x03f00000)
-#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_MSB 31
-#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_LSB 26
-#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_MASK 0xfc000000
-#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_GET(x) (((x) & 0xfc000000) >> 26)
-#define PHY_ANALOG_TXRF7_PADRVGNTAB_0_SET(x) (((x) << 26) & 0xfc000000)
-
-/* macros for TXRF8 */
-#define PHY_ANALOG_TXRF8_ADDRESS 0x0000005c
-#define PHY_ANALOG_TXRF8_OFFSET 0x0000005c
-#define PHY_ANALOG_TXRF8_SPARE8_MSB 1
-#define PHY_ANALOG_TXRF8_SPARE8_LSB 0
-#define PHY_ANALOG_TXRF8_SPARE8_MASK 0x00000003
-#define PHY_ANALOG_TXRF8_SPARE8_GET(x) (((x) & 0x00000003) >> 0)
-#define PHY_ANALOG_TXRF8_SPARE8_SET(x) (((x) << 0) & 0x00000003)
-#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_MSB 7
-#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_LSB 2
-#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_MASK 0x000000fc
-#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_GET(x) (((x) & 0x000000fc) >> 2)
-#define PHY_ANALOG_TXRF8_PADRVGNTAB_9_SET(x) (((x) << 2) & 0x000000fc)
-#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_MSB 13
-#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_LSB 8
-#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_MASK 0x00003f00
-#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_GET(x) (((x) & 0x00003f00) >> 8)
-#define PHY_ANALOG_TXRF8_PADRVGNTAB_8_SET(x) (((x) << 8) & 0x00003f00)
-#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_MSB 19
-#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_LSB 14
-#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_MASK 0x000fc000
-#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_GET(x) (((x) & 0x000fc000) >> 14)
-#define PHY_ANALOG_TXRF8_PADRVGNTAB_7_SET(x) (((x) << 14) & 0x000fc000)
-#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_MSB 25
-#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_LSB 20
-#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_MASK 0x03f00000
-#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_GET(x) (((x) & 0x03f00000) >> 20)
-#define PHY_ANALOG_TXRF8_PADRVGNTAB_6_SET(x) (((x) << 20) & 0x03f00000)
-#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_MSB 31
-#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_LSB 26
-#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_MASK 0xfc000000
-#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_GET(x) (((x) & 0xfc000000) >> 26)
-#define PHY_ANALOG_TXRF8_PADRVGNTAB_5_SET(x) (((x) << 26) & 0xfc000000)
-
-/* macros for TXRF9 */
-#define PHY_ANALOG_TXRF9_ADDRESS 0x00000060
-#define PHY_ANALOG_TXRF9_OFFSET 0x00000060
-#define PHY_ANALOG_TXRF9_SPARE9_MSB 1
-#define PHY_ANALOG_TXRF9_SPARE9_LSB 0
-#define PHY_ANALOG_TXRF9_SPARE9_MASK 0x00000003
-#define PHY_ANALOG_TXRF9_SPARE9_GET(x) (((x) & 0x00000003) >> 0)
-#define PHY_ANALOG_TXRF9_SPARE9_SET(x) (((x) << 0) & 0x00000003)
-#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_MSB 7
-#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_LSB 2
-#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_MASK 0x000000fc
-#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_GET(x) (((x) & 0x000000fc) >> 2)
-#define PHY_ANALOG_TXRF9_PADRVGNTAB_14_SET(x) (((x) << 2) & 0x000000fc)
-#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_MSB 13
-#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_LSB 8
-#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_MASK 0x00003f00
-#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_GET(x) (((x) & 0x00003f00) >> 8)
-#define PHY_ANALOG_TXRF9_PADRVGNTAB_13_SET(x) (((x) << 8) & 0x00003f00)
-#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_MSB 19
-#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_LSB 14
-#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_MASK 0x000fc000
-#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_GET(x) (((x) & 0x000fc000) >> 14)
-#define PHY_ANALOG_TXRF9_PADRVGNTAB_12_SET(x) (((x) << 14) & 0x000fc000)
-#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_MSB 25
-#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_LSB 20
-#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_MASK 0x03f00000
-#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_GET(x) (((x) & 0x03f00000) >> 20)
-#define PHY_ANALOG_TXRF9_PADRVGNTAB_11_SET(x) (((x) << 20) & 0x03f00000)
-#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_MSB 31
-#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_LSB 26
-#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_MASK 0xfc000000
-#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_GET(x) (((x) & 0xfc000000) >> 26)
-#define PHY_ANALOG_TXRF9_PADRVGNTAB_10_SET(x) (((x) << 26) & 0xfc000000)
-
-/* macros for TXRF10 */
-#define PHY_ANALOG_TXRF10_ADDRESS 0x00000064
-#define PHY_ANALOG_TXRF10_OFFSET 0x00000064
-#define PHY_ANALOG_TXRF10_SPARE10_MSB 2
-#define PHY_ANALOG_TXRF10_SPARE10_LSB 0
-#define PHY_ANALOG_TXRF10_SPARE10_MASK 0x00000007
-#define PHY_ANALOG_TXRF10_SPARE10_GET(x) (((x) & 0x00000007) >> 0)
-#define PHY_ANALOG_TXRF10_SPARE10_SET(x) (((x) << 0) & 0x00000007)
-#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_MSB 3
-#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_LSB 3
-#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_MASK 0x00000008
-#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_GET(x) (((x) & 0x00000008) >> 3)
-#define PHY_ANALOG_TXRF10_PDOUT5G_3CALTX_SET(x) (((x) << 3) & 0x00000008)
-#define PHY_ANALOG_TXRF10_D3B5GCALTX_MSB 6
-#define PHY_ANALOG_TXRF10_D3B5GCALTX_LSB 4
-#define PHY_ANALOG_TXRF10_D3B5GCALTX_MASK 0x00000070
-#define PHY_ANALOG_TXRF10_D3B5GCALTX_GET(x) (((x) & 0x00000070) >> 4)
-#define PHY_ANALOG_TXRF10_D3B5GCALTX_SET(x) (((x) << 4) & 0x00000070)
-#define PHY_ANALOG_TXRF10_D4B5GCALTX_MSB 9
-#define PHY_ANALOG_TXRF10_D4B5GCALTX_LSB 7
-#define PHY_ANALOG_TXRF10_D4B5GCALTX_MASK 0x00000380
-#define PHY_ANALOG_TXRF10_D4B5GCALTX_GET(x) (((x) & 0x00000380) >> 7)
-#define PHY_ANALOG_TXRF10_D4B5GCALTX_SET(x) (((x) << 7) & 0x00000380)
-#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_MSB 16
-#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_LSB 10
-#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_MASK 0x0001fc00
-#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_GET(x) (((x) & 0x0001fc00) >> 10)
-#define PHY_ANALOG_TXRF10_PADRVGN2GCALTX_SET(x) (((x) << 10) & 0x0001fc00)
-#define PHY_ANALOG_TXRF10_DB2GCALTX_MSB 19
-#define PHY_ANALOG_TXRF10_DB2GCALTX_LSB 17
-#define PHY_ANALOG_TXRF10_DB2GCALTX_MASK 0x000e0000
-#define PHY_ANALOG_TXRF10_DB2GCALTX_GET(x) (((x) & 0x000e0000) >> 17)
-#define PHY_ANALOG_TXRF10_DB2GCALTX_SET(x) (((x) << 17) & 0x000e0000)
-#define PHY_ANALOG_TXRF10_CALTXSHIFT_MSB 20
-#define PHY_ANALOG_TXRF10_CALTXSHIFT_LSB 20
-#define PHY_ANALOG_TXRF10_CALTXSHIFT_MASK 0x00100000
-#define PHY_ANALOG_TXRF10_CALTXSHIFT_GET(x) (((x) & 0x00100000) >> 20)
-#define PHY_ANALOG_TXRF10_CALTXSHIFT_SET(x) (((x) << 20) & 0x00100000)
-#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_MSB 21
-#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_LSB 21
-#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_MASK 0x00200000
-#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_GET(x) (((x) & 0x00200000) >> 21)
-#define PHY_ANALOG_TXRF10_CALTXSHIFTOVR_SET(x) (((x) << 21) & 0x00200000)
-#define PHY_ANALOG_TXRF10_PADRVGN2G_SMOUT_MSB 27
-#define PHY_ANALOG_TXRF10_PADRVGN2G_SMOUT_LSB 22
-#define PHY_ANALOG_TXRF10_PADRVGN2G_SMOUT_MASK 0x0fc00000
-#define PHY_ANALOG_TXRF10_PADRVGN2G_SMOUT_GET(x) (((x) & 0x0fc00000) >> 22)
-#define PHY_ANALOG_TXRF10_PADRVGN_INDEX2G_SMOUT_MSB 31
-#define PHY_ANALOG_TXRF10_PADRVGN_INDEX2G_SMOUT_LSB 28
-#define PHY_ANALOG_TXRF10_PADRVGN_INDEX2G_SMOUT_MASK 0xf0000000
-#define PHY_ANALOG_TXRF10_PADRVGN_INDEX2G_SMOUT_GET(x) (((x) & 0xf0000000) >> 28)
-
-/* macros for TXRF11 */
-#define PHY_ANALOG_TXRF11_ADDRESS 0x00000068
-#define PHY_ANALOG_TXRF11_OFFSET 0x00000068
-#define PHY_ANALOG_TXRF11_SPARE11_MSB 1
-#define PHY_ANALOG_TXRF11_SPARE11_LSB 0
-#define PHY_ANALOG_TXRF11_SPARE11_MASK 0x00000003
-#define PHY_ANALOG_TXRF11_SPARE11_GET(x) (((x) & 0x00000003) >> 0)
-#define PHY_ANALOG_TXRF11_SPARE11_SET(x) (((x) << 0) & 0x00000003)
-#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_MSB 4
-#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_LSB 2
-#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_MASK 0x0000001c
-#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_GET(x) (((x) & 0x0000001c) >> 2)
-#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV5G_SET(x) (((x) << 2) & 0x0000001c)
-#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_MSB 7
-#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_LSB 5
-#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_MASK 0x000000e0
-#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_GET(x) (((x) & 0x000000e0) >> 5)
-#define PHY_ANALOG_TXRF11_PWD_IR25PA2G_SET(x) (((x) << 5) & 0x000000e0)
-#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_MSB 10
-#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_LSB 8
-#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_MASK 0x00000700
-#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_GET(x) (((x) & 0x00000700) >> 8)
-#define PHY_ANALOG_TXRF11_PWD_IR25MIXBIAS2G_SET(x) (((x) << 8) & 0x00000700)
-#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_MSB 13
-#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_LSB 11
-#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_MASK 0x00003800
-#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_GET(x) (((x) & 0x00003800) >> 11)
-#define PHY_ANALOG_TXRF11_PWD_IR25MIXDIV2G_SET(x) (((x) << 11) & 0x00003800)
-#define PHY_ANALOG_TXRF11_PWD_ICSPARE_MSB 16
-#define PHY_ANALOG_TXRF11_PWD_ICSPARE_LSB 14
-#define PHY_ANALOG_TXRF11_PWD_ICSPARE_MASK 0x0001c000
-#define PHY_ANALOG_TXRF11_PWD_ICSPARE_GET(x) (((x) & 0x0001c000) >> 14)
-#define PHY_ANALOG_TXRF11_PWD_ICSPARE_SET(x) (((x) << 14) & 0x0001c000)
-#define PHY_ANALOG_TXRF11_PWD_IC25TEMPSEN_MSB 19
-#define PHY_ANALOG_TXRF11_PWD_IC25TEMPSEN_LSB 17
-#define PHY_ANALOG_TXRF11_PWD_IC25TEMPSEN_MASK 0x000e0000
-#define PHY_ANALOG_TXRF11_PWD_IC25TEMPSEN_GET(x) (((x) & 0x000e0000) >> 17)
-#define PHY_ANALOG_TXRF11_PWD_IC25TEMPSEN_SET(x) (((x) << 17) & 0x000e0000)
-#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_MSB 22
-#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_LSB 20
-#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_MASK 0x00700000
-#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_GET(x) (((x) & 0x00700000) >> 20)
-#define PHY_ANALOG_TXRF11_PWD_IC25PA5G2_SET(x) (((x) << 20) & 0x00700000)
-#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_MSB 25
-#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_LSB 23
-#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_MASK 0x03800000
-#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_GET(x) (((x) & 0x03800000) >> 23)
-#define PHY_ANALOG_TXRF11_PWD_IC25PA5G1_SET(x) (((x) << 23) & 0x03800000)
-#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_MSB 28
-#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_LSB 26
-#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_MASK 0x1c000000
-#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_GET(x) (((x) & 0x1c000000) >> 26)
-#define PHY_ANALOG_TXRF11_PWD_IC25MIXBUF5G_SET(x) (((x) << 26) & 0x1c000000)
-#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_MSB 31
-#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_LSB 29
-#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_MASK 0xe0000000
-#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_GET(x) (((x) & 0xe0000000) >> 29)
-#define PHY_ANALOG_TXRF11_PWD_IC25PA2G_SET(x) (((x) << 29) & 0xe0000000)
-
-/* macros for TXRF12 */
-#define PHY_ANALOG_TXRF12_ADDRESS 0x0000006c
-#define PHY_ANALOG_TXRF12_OFFSET 0x0000006c
-#define PHY_ANALOG_TXRF12_SPARE12_2_MSB 7
-#define PHY_ANALOG_TXRF12_SPARE12_2_LSB 0
-#define PHY_ANALOG_TXRF12_SPARE12_2_MASK 0x000000ff
-#define PHY_ANALOG_TXRF12_SPARE12_2_GET(x) (((x) & 0x000000ff) >> 0)
-#define PHY_ANALOG_TXRF12_SPARE12_1_MSB 9
-#define PHY_ANALOG_TXRF12_SPARE12_1_LSB 8
-#define PHY_ANALOG_TXRF12_SPARE12_1_MASK 0x00000300
-#define PHY_ANALOG_TXRF12_SPARE12_1_GET(x) (((x) & 0x00000300) >> 8)
-#define PHY_ANALOG_TXRF12_SPARE12_1_SET(x) (((x) << 8) & 0x00000300)
-#define PHY_ANALOG_TXRF12_ATBSEL5G_MSB 13
-#define PHY_ANALOG_TXRF12_ATBSEL5G_LSB 10
-#define PHY_ANALOG_TXRF12_ATBSEL5G_MASK 0x00003c00
-#define PHY_ANALOG_TXRF12_ATBSEL5G_GET(x) (((x) & 0x00003c00) >> 10)
-#define PHY_ANALOG_TXRF12_ATBSEL5G_SET(x) (((x) << 10) & 0x00003c00)
-#define PHY_ANALOG_TXRF12_ATBSEL2G_MSB 16
-#define PHY_ANALOG_TXRF12_ATBSEL2G_LSB 14
-#define PHY_ANALOG_TXRF12_ATBSEL2G_MASK 0x0001c000
-#define PHY_ANALOG_TXRF12_ATBSEL2G_GET(x) (((x) & 0x0001c000) >> 14)
-#define PHY_ANALOG_TXRF12_ATBSEL2G_SET(x) (((x) << 14) & 0x0001c000)
-#define PHY_ANALOG_TXRF12_PWD_IRSPARE_MSB 19
-#define PHY_ANALOG_TXRF12_PWD_IRSPARE_LSB 17
-#define PHY_ANALOG_TXRF12_PWD_IRSPARE_MASK 0x000e0000
-#define PHY_ANALOG_TXRF12_PWD_IRSPARE_GET(x) (((x) & 0x000e0000) >> 17)
-#define PHY_ANALOG_TXRF12_PWD_IRSPARE_SET(x) (((x) << 17) & 0x000e0000)
-#define PHY_ANALOG_TXRF12_PWD_IR25TEMPSEN_MSB 22
-#define PHY_ANALOG_TXRF12_PWD_IR25TEMPSEN_LSB 20
-#define PHY_ANALOG_TXRF12_PWD_IR25TEMPSEN_MASK 0x00700000
-#define PHY_ANALOG_TXRF12_PWD_IR25TEMPSEN_GET(x) (((x) & 0x00700000) >> 20)
-#define PHY_ANALOG_TXRF12_PWD_IR25TEMPSEN_SET(x) (((x) << 20) & 0x00700000)
-#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_MSB 25
-#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_LSB 23
-#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_MASK 0x03800000
-#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_GET(x) (((x) & 0x03800000) >> 23)
-#define PHY_ANALOG_TXRF12_PWD_IR25PA5G2_SET(x) (((x) << 23) & 0x03800000)
-#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_MSB 28
-#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_LSB 26
-#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_MASK 0x1c000000
-#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_GET(x) (((x) & 0x1c000000) >> 26)
-#define PHY_ANALOG_TXRF12_PWD_IR25PA5G1_SET(x) (((x) << 26) & 0x1c000000)
-#define PHY_ANALOG_TXRF12_PWD_IR25MIXBIAS5G_MSB 31
-#define PHY_ANALOG_TXRF12_PWD_IR25MIXBIAS5G_LSB 29
-#define PHY_ANALOG_TXRF12_PWD_IR25MIXBIAS5G_MASK 0xe0000000
-#define PHY_ANALOG_TXRF12_PWD_IR25MIXBIAS5G_GET(x) (((x) & 0xe0000000) >> 29)
-#define PHY_ANALOG_TXRF12_PWD_IR25MIXBIAS5G_SET(x) (((x) << 29) & 0xe0000000)
-
-/* macros for SYNTH1 */
-#define PHY_ANALOG_SYNTH1_ADDRESS 0x00000080
-#define PHY_ANALOG_SYNTH1_OFFSET 0x00000080
-#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_MSB 2
-#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_LSB 0
-#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_MASK 0x00000007
-#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_GET(x) (((x) & 0x00000007) >> 0)
-#define PHY_ANALOG_SYNTH1_SEL_VCMONABUS_SET(x) (((x) << 0) & 0x00000007)
-#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_MSB 5
-#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_LSB 3
-#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_MASK 0x00000038
-#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_GET(x) (((x) & 0x00000038) >> 3)
-#define PHY_ANALOG_SYNTH1_SEL_VCOABUS_SET(x) (((x) << 3) & 0x00000038)
-#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_MSB 6
-#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_LSB 6
-#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_MASK 0x00000040
-#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_GET(x) (((x) & 0x00000040) >> 6)
-#define PHY_ANALOG_SYNTH1_MONITOR_SYNTHLOCKVCOK_SET(x) (((x) << 6) & 0x00000040)
-#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_MSB 7
-#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_LSB 7
-#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_MASK 0x00000080
-#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_GET(x) (((x) & 0x00000080) >> 7)
-#define PHY_ANALOG_SYNTH1_MONITOR_VC2LOW_SET(x) (((x) << 7) & 0x00000080)
-#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_MSB 8
-#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_LSB 8
-#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_MASK 0x00000100
-#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_GET(x) (((x) & 0x00000100) >> 8)
-#define PHY_ANALOG_SYNTH1_MONITOR_VC2HIGH_SET(x) (((x) << 8) & 0x00000100)
-#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_MSB 9
-#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_LSB 9
-#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_MASK 0x00000200
-#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_GET(x) (((x) & 0x00000200) >> 9)
-#define PHY_ANALOG_SYNTH1_MONITOR_FB_DIV2_SET(x) (((x) << 9) & 0x00000200)
-#define PHY_ANALOG_SYNTH1_MONITOR_REF_MSB 10
-#define PHY_ANALOG_SYNTH1_MONITOR_REF_LSB 10
-#define PHY_ANALOG_SYNTH1_MONITOR_REF_MASK 0x00000400
-#define PHY_ANALOG_SYNTH1_MONITOR_REF_GET(x) (((x) & 0x00000400) >> 10)
-#define PHY_ANALOG_SYNTH1_MONITOR_REF_SET(x) (((x) << 10) & 0x00000400)
-#define PHY_ANALOG_SYNTH1_MONITOR_FB_MSB 11
-#define PHY_ANALOG_SYNTH1_MONITOR_FB_LSB 11
-#define PHY_ANALOG_SYNTH1_MONITOR_FB_MASK 0x00000800
-#define PHY_ANALOG_SYNTH1_MONITOR_FB_GET(x) (((x) & 0x00000800) >> 11)
-#define PHY_ANALOG_SYNTH1_MONITOR_FB_SET(x) (((x) << 11) & 0x00000800)
-#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_MSB 12
-#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_LSB 12
-#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_MASK 0x00001000
-#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_GET(x) (((x) & 0x00001000) >> 12)
-#define PHY_ANALOG_SYNTH1_SEVENBITVCOCAP_SET(x) (((x) << 12) & 0x00001000)
-#define PHY_ANALOG_SYNTH1_PWUP_PD_MSB 15
-#define PHY_ANALOG_SYNTH1_PWUP_PD_LSB 13
-#define PHY_ANALOG_SYNTH1_PWUP_PD_MASK 0x0000e000
-#define PHY_ANALOG_SYNTH1_PWUP_PD_GET(x) (((x) & 0x0000e000) >> 13)
-#define PHY_ANALOG_SYNTH1_PWUP_PD_SET(x) (((x) << 13) & 0x0000e000)
-#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_MSB 16
-#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_LSB 16
-#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_MASK 0x00010000
-#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_GET(x) (((x) & 0x00010000) >> 16)
-#define PHY_ANALOG_SYNTH1_PWD_VCOBUF_SET(x) (((x) << 16) & 0x00010000)
-#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_MSB 18
-#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_LSB 17
-#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_MASK 0x00060000
-#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_GET(x) (((x) & 0x00060000) >> 17)
-#define PHY_ANALOG_SYNTH1_VCOBUFGAIN_SET(x) (((x) << 17) & 0x00060000)
-#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_MSB 20
-#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_LSB 19
-#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_MASK 0x00180000
-#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_GET(x) (((x) & 0x00180000) >> 19)
-#define PHY_ANALOG_SYNTH1_VCOREGLEVEL_SET(x) (((x) << 19) & 0x00180000)
-#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_MSB 21
-#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_LSB 21
-#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_MASK 0x00200000
-#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_GET(x) (((x) & 0x00200000) >> 21)
-#define PHY_ANALOG_SYNTH1_VCOREGBYPASS_SET(x) (((x) << 21) & 0x00200000)
-#define PHY_ANALOG_SYNTH1_PWUP_LOREF_MSB 22
-#define PHY_ANALOG_SYNTH1_PWUP_LOREF_LSB 22
-#define PHY_ANALOG_SYNTH1_PWUP_LOREF_MASK 0x00400000
-#define PHY_ANALOG_SYNTH1_PWUP_LOREF_GET(x) (((x) & 0x00400000) >> 22)
-#define PHY_ANALOG_SYNTH1_PWUP_LOREF_SET(x) (((x) << 22) & 0x00400000)
-#define PHY_ANALOG_SYNTH1_PWD_LOMIX_MSB 23
-#define PHY_ANALOG_SYNTH1_PWD_LOMIX_LSB 23
-#define PHY_ANALOG_SYNTH1_PWD_LOMIX_MASK 0x00800000
-#define PHY_ANALOG_SYNTH1_PWD_LOMIX_GET(x) (((x) & 0x00800000) >> 23)
-#define PHY_ANALOG_SYNTH1_PWD_LOMIX_SET(x) (((x) << 23) & 0x00800000)
-#define PHY_ANALOG_SYNTH1_PWD_LODIV_MSB 24
-#define PHY_ANALOG_SYNTH1_PWD_LODIV_LSB 24
-#define PHY_ANALOG_SYNTH1_PWD_LODIV_MASK 0x01000000
-#define PHY_ANALOG_SYNTH1_PWD_LODIV_GET(x) (((x) & 0x01000000) >> 24)
-#define PHY_ANALOG_SYNTH1_PWD_LODIV_SET(x) (((x) << 24) & 0x01000000)
-#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_MSB 25
-#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_LSB 25
-#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_MASK 0x02000000
-#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_GET(x) (((x) & 0x02000000) >> 25)
-#define PHY_ANALOG_SYNTH1_PWD_LOBUF5G_SET(x) (((x) << 25) & 0x02000000)
-#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_MSB 26
-#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_LSB 26
-#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_MASK 0x04000000
-#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_GET(x) (((x) & 0x04000000) >> 26)
-#define PHY_ANALOG_SYNTH1_PWD_LOBUF2G_SET(x) (((x) << 26) & 0x04000000)
-#define PHY_ANALOG_SYNTH1_PWD_PRESC_MSB 27
-#define PHY_ANALOG_SYNTH1_PWD_PRESC_LSB 27
-#define PHY_ANALOG_SYNTH1_PWD_PRESC_MASK 0x08000000
-#define PHY_ANALOG_SYNTH1_PWD_PRESC_GET(x) (((x) & 0x08000000) >> 27)
-#define PHY_ANALOG_SYNTH1_PWD_PRESC_SET(x) (((x) << 27) & 0x08000000)
-#define PHY_ANALOG_SYNTH1_PWD_VCO_MSB 28
-#define PHY_ANALOG_SYNTH1_PWD_VCO_LSB 28
-#define PHY_ANALOG_SYNTH1_PWD_VCO_MASK 0x10000000
-#define PHY_ANALOG_SYNTH1_PWD_VCO_GET(x) (((x) & 0x10000000) >> 28)
-#define PHY_ANALOG_SYNTH1_PWD_VCO_SET(x) (((x) << 28) & 0x10000000)
-#define PHY_ANALOG_SYNTH1_PWD_VCMON_MSB 29
-#define PHY_ANALOG_SYNTH1_PWD_VCMON_LSB 29
-#define PHY_ANALOG_SYNTH1_PWD_VCMON_MASK 0x20000000
-#define PHY_ANALOG_SYNTH1_PWD_VCMON_GET(x) (((x) & 0x20000000) >> 29)
-#define PHY_ANALOG_SYNTH1_PWD_VCMON_SET(x) (((x) << 29) & 0x20000000)
-#define PHY_ANALOG_SYNTH1_PWD_CP_MSB 30
-#define PHY_ANALOG_SYNTH1_PWD_CP_LSB 30
-#define PHY_ANALOG_SYNTH1_PWD_CP_MASK 0x40000000
-#define PHY_ANALOG_SYNTH1_PWD_CP_GET(x) (((x) & 0x40000000) >> 30)
-#define PHY_ANALOG_SYNTH1_PWD_CP_SET(x) (((x) << 30) & 0x40000000)
-#define PHY_ANALOG_SYNTH1_PWD_BIAS_MSB 31
-#define PHY_ANALOG_SYNTH1_PWD_BIAS_LSB 31
-#define PHY_ANALOG_SYNTH1_PWD_BIAS_MASK 0x80000000
-#define PHY_ANALOG_SYNTH1_PWD_BIAS_GET(x) (((x) & 0x80000000) >> 31)
-#define PHY_ANALOG_SYNTH1_PWD_BIAS_SET(x) (((x) << 31) & 0x80000000)
-
-/* macros for SYNTH2 */
-#define PHY_ANALOG_SYNTH2_ADDRESS 0x00000084
-#define PHY_ANALOG_SYNTH2_OFFSET 0x00000084
-#define PHY_ANALOG_SYNTH2_CAPRANGE3_MSB 3
-#define PHY_ANALOG_SYNTH2_CAPRANGE3_LSB 0
-#define PHY_ANALOG_SYNTH2_CAPRANGE3_MASK 0x0000000f
-#define PHY_ANALOG_SYNTH2_CAPRANGE3_GET(x) (((x) & 0x0000000f) >> 0)
-#define PHY_ANALOG_SYNTH2_CAPRANGE3_SET(x) (((x) << 0) & 0x0000000f)
-#define PHY_ANALOG_SYNTH2_CAPRANGE2_MSB 7
-#define PHY_ANALOG_SYNTH2_CAPRANGE2_LSB 4
-#define PHY_ANALOG_SYNTH2_CAPRANGE2_MASK 0x000000f0
-#define PHY_ANALOG_SYNTH2_CAPRANGE2_GET(x) (((x) & 0x000000f0) >> 4)
-#define PHY_ANALOG_SYNTH2_CAPRANGE2_SET(x) (((x) << 4) & 0x000000f0)
-#define PHY_ANALOG_SYNTH2_CAPRANGE1_MSB 11
-#define PHY_ANALOG_SYNTH2_CAPRANGE1_LSB 8
-#define PHY_ANALOG_SYNTH2_CAPRANGE1_MASK 0x00000f00
-#define PHY_ANALOG_SYNTH2_CAPRANGE1_GET(x) (((x) & 0x00000f00) >> 8)
-#define PHY_ANALOG_SYNTH2_CAPRANGE1_SET(x) (((x) << 8) & 0x00000f00)
-#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_INTN_MSB 15
-#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_INTN_LSB 12
-#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_INTN_MASK 0x0000f000
-#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_INTN_GET(x) (((x) & 0x0000f000) >> 12)
-#define PHY_ANALOG_SYNTH2_LOOPLEAKCUR_INTN_SET(x) (((x) << 12) & 0x0000f000)
-#define PHY_ANALOG_SYNTH2_CPLOWLK_INTN_MSB 16
-#define PHY_ANALOG_SYNTH2_CPLOWLK_INTN_LSB 16
-#define PHY_ANALOG_SYNTH2_CPLOWLK_INTN_MASK 0x00010000
-#define PHY_ANALOG_SYNTH2_CPLOWLK_INTN_GET(x) (((x) & 0x00010000) >> 16)
-#define PHY_ANALOG_SYNTH2_CPLOWLK_INTN_SET(x) (((x) << 16) & 0x00010000)
-#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_MSB 17
-#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_LSB 17
-#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_MASK 0x00020000
-#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_GET(x) (((x) & 0x00020000) >> 17)
-#define PHY_ANALOG_SYNTH2_CPSTEERING_EN_INTN_SET(x) (((x) << 17) & 0x00020000)
-#define PHY_ANALOG_SYNTH2_CPBIAS_INTN_MSB 19
-#define PHY_ANALOG_SYNTH2_CPBIAS_INTN_LSB 18
-#define PHY_ANALOG_SYNTH2_CPBIAS_INTN_MASK 0x000c0000
-#define PHY_ANALOG_SYNTH2_CPBIAS_INTN_GET(x) (((x) & 0x000c0000) >> 18)
-#define PHY_ANALOG_SYNTH2_CPBIAS_INTN_SET(x) (((x) << 18) & 0x000c0000)
-#define PHY_ANALOG_SYNTH2_VC_LOW_REF_MSB 22
-#define PHY_ANALOG_SYNTH2_VC_LOW_REF_LSB 20
-#define PHY_ANALOG_SYNTH2_VC_LOW_REF_MASK 0x00700000
-#define PHY_ANALOG_SYNTH2_VC_LOW_REF_GET(x) (((x) & 0x00700000) >> 20)
-#define PHY_ANALOG_SYNTH2_VC_LOW_REF_SET(x) (((x) << 20) & 0x00700000)
-#define PHY_ANALOG_SYNTH2_VC_MID_REF_MSB 25
-#define PHY_ANALOG_SYNTH2_VC_MID_REF_LSB 23
-#define PHY_ANALOG_SYNTH2_VC_MID_REF_MASK 0x03800000
-#define PHY_ANALOG_SYNTH2_VC_MID_REF_GET(x) (((x) & 0x03800000) >> 23)
-#define PHY_ANALOG_SYNTH2_VC_MID_REF_SET(x) (((x) << 23) & 0x03800000)
-#define PHY_ANALOG_SYNTH2_VC_HI_REF_MSB 28
-#define PHY_ANALOG_SYNTH2_VC_HI_REF_LSB 26
-#define PHY_ANALOG_SYNTH2_VC_HI_REF_MASK 0x1c000000
-#define PHY_ANALOG_SYNTH2_VC_HI_REF_GET(x) (((x) & 0x1c000000) >> 26)
-#define PHY_ANALOG_SYNTH2_VC_HI_REF_SET(x) (((x) << 26) & 0x1c000000)
-#define PHY_ANALOG_SYNTH2_VC_CAL_REF_MSB 31
-#define PHY_ANALOG_SYNTH2_VC_CAL_REF_LSB 29
-#define PHY_ANALOG_SYNTH2_VC_CAL_REF_MASK 0xe0000000
-#define PHY_ANALOG_SYNTH2_VC_CAL_REF_GET(x) (((x) & 0xe0000000) >> 29)
-#define PHY_ANALOG_SYNTH2_VC_CAL_REF_SET(x) (((x) << 29) & 0xe0000000)
-
-/* macros for SYNTH3 */
-#define PHY_ANALOG_SYNTH3_ADDRESS 0x00000088
-#define PHY_ANALOG_SYNTH3_OFFSET 0x00000088
-#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_MSB 5
-#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_LSB 0
-#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_MASK 0x0000003f
-#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_GET(x) (((x) & 0x0000003f) >> 0)
-#define PHY_ANALOG_SYNTH3_WAIT_VC_CHECK_SET(x) (((x) << 0) & 0x0000003f)
-#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_MSB 11
-#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_LSB 6
-#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_MASK 0x00000fc0
-#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_GET(x) (((x) & 0x00000fc0) >> 6)
-#define PHY_ANALOG_SYNTH3_WAIT_CAL_LIN_SET(x) (((x) << 6) & 0x00000fc0)
-#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_MSB 17
-#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_LSB 12
-#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_MASK 0x0003f000
-#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_GET(x) (((x) & 0x0003f000) >> 12)
-#define PHY_ANALOG_SYNTH3_WAIT_CAL_BIN_SET(x) (((x) << 12) & 0x0003f000)
-#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_MSB 23
-#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_LSB 18
-#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_MASK 0x00fc0000
-#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_GET(x) (((x) & 0x00fc0000) >> 18)
-#define PHY_ANALOG_SYNTH3_WAIT_PWRUP_SET(x) (((x) << 18) & 0x00fc0000)
-#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_MSB 29
-#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_LSB 24
-#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_MASK 0x3f000000
-#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_GET(x) (((x) & 0x3f000000) >> 24)
-#define PHY_ANALOG_SYNTH3_WAIT_SHORTR_PWRUP_SET(x) (((x) << 24) & 0x3f000000)
-#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_MSB 30
-#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_LSB 30
-#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_MASK 0x40000000
-#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_GET(x) (((x) & 0x40000000) >> 30)
-#define PHY_ANALOG_SYNTH3_SEL_CLK_DIV2_SET(x) (((x) << 30) & 0x40000000)
-#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_MSB 31
-#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_LSB 31
-#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_MASK 0x80000000
-#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_GET(x) (((x) & 0x80000000) >> 31)
-#define PHY_ANALOG_SYNTH3_DIS_CLK_XTAL_SET(x) (((x) << 31) & 0x80000000)
-
-/* macros for SYNTH4 */
-#define PHY_ANALOG_SYNTH4_ADDRESS 0x0000008c
-#define PHY_ANALOG_SYNTH4_OFFSET 0x0000008c
-#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_MSB 0
-#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_LSB 0
-#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_MASK 0x00000001
-#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_ANALOG_SYNTH4_PS_SINGLE_PULSE_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_MSB 1
-#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_LSB 1
-#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_MASK 0x00000002
-#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_GET(x) (((x) & 0x00000002) >> 1)
-#define PHY_ANALOG_SYNTH4_LONGSHIFTSEL_SET(x) (((x) << 1) & 0x00000002)
-#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_MSB 3
-#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_LSB 2
-#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_MASK 0x0000000c
-#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_GET(x) (((x) & 0x0000000c) >> 2)
-#define PHY_ANALOG_SYNTH4_LOBUF5GTUNE_OVR_SET(x) (((x) << 2) & 0x0000000c)
-#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_MSB 4
-#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_LSB 4
-#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_MASK 0x00000010
-#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_GET(x) (((x) & 0x00000010) >> 4)
-#define PHY_ANALOG_SYNTH4_FORCE_LOBUF5GTUNE_SET(x) (((x) << 4) & 0x00000010)
-#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_MSB 5
-#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_LSB 5
-#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_MASK 0x00000020
-#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_GET(x) (((x) & 0x00000020) >> 5)
-#define PHY_ANALOG_SYNTH4_PSCOUNT_FBSEL_SET(x) (((x) << 5) & 0x00000020)
-#define PHY_ANALOG_SYNTH4_SDM_DITHER1_MSB 7
-#define PHY_ANALOG_SYNTH4_SDM_DITHER1_LSB 6
-#define PHY_ANALOG_SYNTH4_SDM_DITHER1_MASK 0x000000c0
-#define PHY_ANALOG_SYNTH4_SDM_DITHER1_GET(x) (((x) & 0x000000c0) >> 6)
-#define PHY_ANALOG_SYNTH4_SDM_DITHER1_SET(x) (((x) << 6) & 0x000000c0)
-#define PHY_ANALOG_SYNTH4_SDM_MODE_MSB 8
-#define PHY_ANALOG_SYNTH4_SDM_MODE_LSB 8
-#define PHY_ANALOG_SYNTH4_SDM_MODE_MASK 0x00000100
-#define PHY_ANALOG_SYNTH4_SDM_MODE_GET(x) (((x) & 0x00000100) >> 8)
-#define PHY_ANALOG_SYNTH4_SDM_MODE_SET(x) (((x) << 8) & 0x00000100)
-#define PHY_ANALOG_SYNTH4_SDM_DISABLE_MSB 9
-#define PHY_ANALOG_SYNTH4_SDM_DISABLE_LSB 9
-#define PHY_ANALOG_SYNTH4_SDM_DISABLE_MASK 0x00000200
-#define PHY_ANALOG_SYNTH4_SDM_DISABLE_GET(x) (((x) & 0x00000200) >> 9)
-#define PHY_ANALOG_SYNTH4_SDM_DISABLE_SET(x) (((x) << 9) & 0x00000200)
-#define PHY_ANALOG_SYNTH4_RESET_PRESC_MSB 10
-#define PHY_ANALOG_SYNTH4_RESET_PRESC_LSB 10
-#define PHY_ANALOG_SYNTH4_RESET_PRESC_MASK 0x00000400
-#define PHY_ANALOG_SYNTH4_RESET_PRESC_GET(x) (((x) & 0x00000400) >> 10)
-#define PHY_ANALOG_SYNTH4_RESET_PRESC_SET(x) (((x) << 10) & 0x00000400)
-#define PHY_ANALOG_SYNTH4_PRESCSEL_MSB 12
-#define PHY_ANALOG_SYNTH4_PRESCSEL_LSB 11
-#define PHY_ANALOG_SYNTH4_PRESCSEL_MASK 0x00001800
-#define PHY_ANALOG_SYNTH4_PRESCSEL_GET(x) (((x) & 0x00001800) >> 11)
-#define PHY_ANALOG_SYNTH4_PRESCSEL_SET(x) (((x) << 11) & 0x00001800)
-#define PHY_ANALOG_SYNTH4_PFD_DISABLE_MSB 13
-#define PHY_ANALOG_SYNTH4_PFD_DISABLE_LSB 13
-#define PHY_ANALOG_SYNTH4_PFD_DISABLE_MASK 0x00002000
-#define PHY_ANALOG_SYNTH4_PFD_DISABLE_GET(x) (((x) & 0x00002000) >> 13)
-#define PHY_ANALOG_SYNTH4_PFD_DISABLE_SET(x) (((x) << 13) & 0x00002000)
-#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_MSB 14
-#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_LSB 14
-#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_MASK 0x00004000
-#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_GET(x) (((x) & 0x00004000) >> 14)
-#define PHY_ANALOG_SYNTH4_PFDDELAY_FRACN_SET(x) (((x) << 14) & 0x00004000)
-#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_MSB 15
-#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_LSB 15
-#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_MASK 0x00008000
-#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_GET(x) (((x) & 0x00008000) >> 15)
-#define PHY_ANALOG_SYNTH4_FORCE_LO_ON_SET(x) (((x) << 15) & 0x00008000)
-#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_MSB 16
-#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_LSB 16
-#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_MASK 0x00010000
-#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_GET(x) (((x) & 0x00010000) >> 16)
-#define PHY_ANALOG_SYNTH4_CLKXTAL_EDGE_SEL_SET(x) (((x) << 16) & 0x00010000)
-#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_MSB 17
-#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_LSB 17
-#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_MASK 0x00020000
-#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_GET(x) (((x) & 0x00020000) >> 17)
-#define PHY_ANALOG_SYNTH4_VCOCAPPULLUP_SET(x) (((x) << 17) & 0x00020000)
-#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_MSB 25
-#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_LSB 18
-#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_MASK 0x03fc0000
-#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_GET(x) (((x) & 0x03fc0000) >> 18)
-#define PHY_ANALOG_SYNTH4_VCOCAP_OVR_SET(x) (((x) << 18) & 0x03fc0000)
-#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_MSB 26
-#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_LSB 26
-#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_MASK 0x04000000
-#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_GET(x) (((x) & 0x04000000) >> 26)
-#define PHY_ANALOG_SYNTH4_FORCE_VCOCAP_SET(x) (((x) << 26) & 0x04000000)
-#define PHY_ANALOG_SYNTH4_FORCE_PINVC_MSB 27
-#define PHY_ANALOG_SYNTH4_FORCE_PINVC_LSB 27
-#define PHY_ANALOG_SYNTH4_FORCE_PINVC_MASK 0x08000000
-#define PHY_ANALOG_SYNTH4_FORCE_PINVC_GET(x) (((x) & 0x08000000) >> 27)
-#define PHY_ANALOG_SYNTH4_FORCE_PINVC_SET(x) (((x) << 27) & 0x08000000)
-#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_MSB 28
-#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_LSB 28
-#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_MASK 0x10000000
-#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_GET(x) (((x) & 0x10000000) >> 28)
-#define PHY_ANALOG_SYNTH4_SHORTR_UNTIL_LOCKED_SET(x) (((x) << 28) & 0x10000000)
-#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_MSB 29
-#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_LSB 29
-#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_MASK 0x20000000
-#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_GET(x) (((x) & 0x20000000) >> 29)
-#define PHY_ANALOG_SYNTH4_ALWAYS_SHORTR_SET(x) (((x) << 29) & 0x20000000)
-#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_MSB 30
-#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_LSB 30
-#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_MASK 0x40000000
-#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_GET(x) (((x) & 0x40000000) >> 30)
-#define PHY_ANALOG_SYNTH4_DIS_LOSTVC_SET(x) (((x) << 30) & 0x40000000)
-#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_MSB 31
-#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_LSB 31
-#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_MASK 0x80000000
-#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_GET(x) (((x) & 0x80000000) >> 31)
-#define PHY_ANALOG_SYNTH4_DIS_LIN_CAPSEARCH_SET(x) (((x) << 31) & 0x80000000)
-
-/* macros for SYNTH5 */
-#define PHY_ANALOG_SYNTH5_ADDRESS 0x00000090
-#define PHY_ANALOG_SYNTH5_OFFSET 0x00000090
-#define PHY_ANALOG_SYNTH5_VCOBIAS_MSB 1
-#define PHY_ANALOG_SYNTH5_VCOBIAS_LSB 0
-#define PHY_ANALOG_SYNTH5_VCOBIAS_MASK 0x00000003
-#define PHY_ANALOG_SYNTH5_VCOBIAS_GET(x) (((x) & 0x00000003) >> 0)
-#define PHY_ANALOG_SYNTH5_VCOBIAS_SET(x) (((x) << 0) & 0x00000003)
-#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_MSB 4
-#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_LSB 2
-#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_MASK 0x0000001c
-#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_GET(x) (((x) & 0x0000001c) >> 2)
-#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF5G50_SET(x) (((x) << 2) & 0x0000001c)
-#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_MSB 7
-#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_LSB 5
-#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_MASK 0x000000e0
-#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_GET(x) (((x) & 0x000000e0) >> 5)
-#define PHY_ANALOG_SYNTH5_PWDB_ICLOBUF2G50_SET(x) (((x) << 5) & 0x000000e0)
-#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_MSB 10
-#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_LSB 8
-#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_MASK 0x00000700
-#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_GET(x) (((x) & 0x00000700) >> 8)
-#define PHY_ANALOG_SYNTH5_PWDB_ICVCO25_SET(x) (((x) << 8) & 0x00000700)
-#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_MSB 13
-#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_LSB 11
-#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_MASK 0x00003800
-#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_GET(x) (((x) & 0x00003800) >> 11)
-#define PHY_ANALOG_SYNTH5_PWDB_ICVCOREG25_SET(x) (((x) << 11) & 0x00003800)
-#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_MSB 14
-#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_LSB 14
-#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_MASK 0x00004000
-#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_GET(x) (((x) & 0x00004000) >> 14)
-#define PHY_ANALOG_SYNTH5_PWDB_IRVCOREG50_SET(x) (((x) << 14) & 0x00004000)
-#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_MSB 17
-#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_LSB 15
-#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_MASK 0x00038000
-#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_GET(x) (((x) & 0x00038000) >> 15)
-#define PHY_ANALOG_SYNTH5_PWDB_ICLOMIX_SET(x) (((x) << 15) & 0x00038000)
-#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_MSB 20
-#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_LSB 18
-#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_MASK 0x001c0000
-#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_GET(x) (((x) & 0x001c0000) >> 18)
-#define PHY_ANALOG_SYNTH5_PWDB_ICLODIV50_SET(x) (((x) << 18) & 0x001c0000)
-#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_MSB 23
-#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_LSB 21
-#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_MASK 0x00e00000
-#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_GET(x) (((x) & 0x00e00000) >> 21)
-#define PHY_ANALOG_SYNTH5_PWDB_ICPRESC50_SET(x) (((x) << 21) & 0x00e00000)
-#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_MSB 26
-#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_LSB 24
-#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_MASK 0x07000000
-#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_GET(x) (((x) & 0x07000000) >> 24)
-#define PHY_ANALOG_SYNTH5_PWDB_IRVCMON25_SET(x) (((x) << 24) & 0x07000000)
-#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_MSB 29
-#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_LSB 27
-#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_MASK 0x38000000
-#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_GET(x) (((x) & 0x38000000) >> 27)
-#define PHY_ANALOG_SYNTH5_PWDB_IRPFDCP_SET(x) (((x) << 27) & 0x38000000)
-#define PHY_ANALOG_SYNTH5_SDM_DITHER2_MSB 31
-#define PHY_ANALOG_SYNTH5_SDM_DITHER2_LSB 30
-#define PHY_ANALOG_SYNTH5_SDM_DITHER2_MASK 0xc0000000
-#define PHY_ANALOG_SYNTH5_SDM_DITHER2_GET(x) (((x) & 0xc0000000) >> 30)
-#define PHY_ANALOG_SYNTH5_SDM_DITHER2_SET(x) (((x) << 30) & 0xc0000000)
-
-/* macros for SYNTH6 */
-#define PHY_ANALOG_SYNTH6_ADDRESS 0x00000094
-#define PHY_ANALOG_SYNTH6_OFFSET 0x00000094
-#define PHY_ANALOG_SYNTH6_LOBUF5GTUNE_MSB 1
-#define PHY_ANALOG_SYNTH6_LOBUF5GTUNE_LSB 0
-#define PHY_ANALOG_SYNTH6_LOBUF5GTUNE_MASK 0x00000003
-#define PHY_ANALOG_SYNTH6_LOBUF5GTUNE_GET(x) (((x) & 0x00000003) >> 0)
-#define PHY_ANALOG_SYNTH6_LOOP_IP_MSB 8
-#define PHY_ANALOG_SYNTH6_LOOP_IP_LSB 2
-#define PHY_ANALOG_SYNTH6_LOOP_IP_MASK 0x000001fc
-#define PHY_ANALOG_SYNTH6_LOOP_IP_GET(x) (((x) & 0x000001fc) >> 2)
-#define PHY_ANALOG_SYNTH6_VC2LOW_MSB 9
-#define PHY_ANALOG_SYNTH6_VC2LOW_LSB 9
-#define PHY_ANALOG_SYNTH6_VC2LOW_MASK 0x00000200
-#define PHY_ANALOG_SYNTH6_VC2LOW_GET(x) (((x) & 0x00000200) >> 9)
-#define PHY_ANALOG_SYNTH6_VC2HIGH_MSB 10
-#define PHY_ANALOG_SYNTH6_VC2HIGH_LSB 10
-#define PHY_ANALOG_SYNTH6_VC2HIGH_MASK 0x00000400
-#define PHY_ANALOG_SYNTH6_VC2HIGH_GET(x) (((x) & 0x00000400) >> 10)
-#define PHY_ANALOG_SYNTH6_RESET_SDM_B_MSB 11
-#define PHY_ANALOG_SYNTH6_RESET_SDM_B_LSB 11
-#define PHY_ANALOG_SYNTH6_RESET_SDM_B_MASK 0x00000800
-#define PHY_ANALOG_SYNTH6_RESET_SDM_B_GET(x) (((x) & 0x00000800) >> 11)
-#define PHY_ANALOG_SYNTH6_RESET_PSCOUNTERS_MSB 12
-#define PHY_ANALOG_SYNTH6_RESET_PSCOUNTERS_LSB 12
-#define PHY_ANALOG_SYNTH6_RESET_PSCOUNTERS_MASK 0x00001000
-#define PHY_ANALOG_SYNTH6_RESET_PSCOUNTERS_GET(x) (((x) & 0x00001000) >> 12)
-#define PHY_ANALOG_SYNTH6_RESET_PFD_MSB 13
-#define PHY_ANALOG_SYNTH6_RESET_PFD_LSB 13
-#define PHY_ANALOG_SYNTH6_RESET_PFD_MASK 0x00002000
-#define PHY_ANALOG_SYNTH6_RESET_PFD_GET(x) (((x) & 0x00002000) >> 13)
-#define PHY_ANALOG_SYNTH6_RESET_RFD_MSB 14
-#define PHY_ANALOG_SYNTH6_RESET_RFD_LSB 14
-#define PHY_ANALOG_SYNTH6_RESET_RFD_MASK 0x00004000
-#define PHY_ANALOG_SYNTH6_RESET_RFD_GET(x) (((x) & 0x00004000) >> 14)
-#define PHY_ANALOG_SYNTH6_SHORT_R_MSB 15
-#define PHY_ANALOG_SYNTH6_SHORT_R_LSB 15
-#define PHY_ANALOG_SYNTH6_SHORT_R_MASK 0x00008000
-#define PHY_ANALOG_SYNTH6_SHORT_R_GET(x) (((x) & 0x00008000) >> 15)
-#define PHY_ANALOG_SYNTH6_VCO_CAP_ST_MSB 23
-#define PHY_ANALOG_SYNTH6_VCO_CAP_ST_LSB 16
-#define PHY_ANALOG_SYNTH6_VCO_CAP_ST_MASK 0x00ff0000
-#define PHY_ANALOG_SYNTH6_VCO_CAP_ST_GET(x) (((x) & 0x00ff0000) >> 16)
-#define PHY_ANALOG_SYNTH6_PIN_VC_MSB 24
-#define PHY_ANALOG_SYNTH6_PIN_VC_LSB 24
-#define PHY_ANALOG_SYNTH6_PIN_VC_MASK 0x01000000
-#define PHY_ANALOG_SYNTH6_PIN_VC_GET(x) (((x) & 0x01000000) >> 24)
-#define PHY_ANALOG_SYNTH6_SYNTH_LOCK_VC_OK_MSB 25
-#define PHY_ANALOG_SYNTH6_SYNTH_LOCK_VC_OK_LSB 25
-#define PHY_ANALOG_SYNTH6_SYNTH_LOCK_VC_OK_MASK 0x02000000
-#define PHY_ANALOG_SYNTH6_SYNTH_LOCK_VC_OK_GET(x) (((x) & 0x02000000) >> 25)
-#define PHY_ANALOG_SYNTH6_CAP_SEARCH_MSB 26
-#define PHY_ANALOG_SYNTH6_CAP_SEARCH_LSB 26
-#define PHY_ANALOG_SYNTH6_CAP_SEARCH_MASK 0x04000000
-#define PHY_ANALOG_SYNTH6_CAP_SEARCH_GET(x) (((x) & 0x04000000) >> 26)
-#define PHY_ANALOG_SYNTH6_SYNTH_SM_STATE_MSB 30
-#define PHY_ANALOG_SYNTH6_SYNTH_SM_STATE_LSB 27
-#define PHY_ANALOG_SYNTH6_SYNTH_SM_STATE_MASK 0x78000000
-#define PHY_ANALOG_SYNTH6_SYNTH_SM_STATE_GET(x) (((x) & 0x78000000) >> 27)
-#define PHY_ANALOG_SYNTH6_SYNTH_ON_MSB 31
-#define PHY_ANALOG_SYNTH6_SYNTH_ON_LSB 31
-#define PHY_ANALOG_SYNTH6_SYNTH_ON_MASK 0x80000000
-#define PHY_ANALOG_SYNTH6_SYNTH_ON_GET(x) (((x) & 0x80000000) >> 31)
-
-/* macros for SYNTH7 */
-#define PHY_ANALOG_SYNTH7_ADDRESS 0x00000098
-#define PHY_ANALOG_SYNTH7_OFFSET 0x00000098
-#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_MSB 0
-#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_LSB 0
-#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_MASK 0x00000001
-#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_ANALOG_SYNTH7_OVRCHANDECODER_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_MSB 1
-#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_LSB 1
-#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_MASK 0x00000002
-#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_GET(x) (((x) & 0x00000002) >> 1)
-#define PHY_ANALOG_SYNTH7_FORCE_FRACLSB_SET(x) (((x) << 1) & 0x00000002)
-#define PHY_ANALOG_SYNTH7_CHANFRAC_MSB 18
-#define PHY_ANALOG_SYNTH7_CHANFRAC_LSB 2
-#define PHY_ANALOG_SYNTH7_CHANFRAC_MASK 0x0007fffc
-#define PHY_ANALOG_SYNTH7_CHANFRAC_GET(x) (((x) & 0x0007fffc) >> 2)
-#define PHY_ANALOG_SYNTH7_CHANFRAC_SET(x) (((x) << 2) & 0x0007fffc)
-#define PHY_ANALOG_SYNTH7_CHANSEL_MSB 27
-#define PHY_ANALOG_SYNTH7_CHANSEL_LSB 19
-#define PHY_ANALOG_SYNTH7_CHANSEL_MASK 0x0ff80000
-#define PHY_ANALOG_SYNTH7_CHANSEL_GET(x) (((x) & 0x0ff80000) >> 19)
-#define PHY_ANALOG_SYNTH7_CHANSEL_SET(x) (((x) << 19) & 0x0ff80000)
-#define PHY_ANALOG_SYNTH7_AMODEREFSEL_MSB 29
-#define PHY_ANALOG_SYNTH7_AMODEREFSEL_LSB 28
-#define PHY_ANALOG_SYNTH7_AMODEREFSEL_MASK 0x30000000
-#define PHY_ANALOG_SYNTH7_AMODEREFSEL_GET(x) (((x) & 0x30000000) >> 28)
-#define PHY_ANALOG_SYNTH7_AMODEREFSEL_SET(x) (((x) << 28) & 0x30000000)
-#define PHY_ANALOG_SYNTH7_FRACMODE_MSB 30
-#define PHY_ANALOG_SYNTH7_FRACMODE_LSB 30
-#define PHY_ANALOG_SYNTH7_FRACMODE_MASK 0x40000000
-#define PHY_ANALOG_SYNTH7_FRACMODE_GET(x) (((x) & 0x40000000) >> 30)
-#define PHY_ANALOG_SYNTH7_FRACMODE_SET(x) (((x) << 30) & 0x40000000)
-#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_MSB 31
-#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_LSB 31
-#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_MASK 0x80000000
-#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_GET(x) (((x) & 0x80000000) >> 31)
-#define PHY_ANALOG_SYNTH7_LOADSYNTHCHANNEL_SET(x) (((x) << 31) & 0x80000000)
-
-/* macros for SYNTH8 */
-#define PHY_ANALOG_SYNTH8_ADDRESS 0x0000009c
-#define PHY_ANALOG_SYNTH8_OFFSET 0x0000009c
-#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_MSB 0
-#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_LSB 0
-#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_MASK 0x00000001
-#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_ANALOG_SYNTH8_CPSTEERING_EN_FRACN_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_ANALOG_SYNTH8_LOOP_ICPB_MSB 7
-#define PHY_ANALOG_SYNTH8_LOOP_ICPB_LSB 1
-#define PHY_ANALOG_SYNTH8_LOOP_ICPB_MASK 0x000000fe
-#define PHY_ANALOG_SYNTH8_LOOP_ICPB_GET(x) (((x) & 0x000000fe) >> 1)
-#define PHY_ANALOG_SYNTH8_LOOP_ICPB_SET(x) (((x) << 1) & 0x000000fe)
-#define PHY_ANALOG_SYNTH8_LOOP_CSB_MSB 11
-#define PHY_ANALOG_SYNTH8_LOOP_CSB_LSB 8
-#define PHY_ANALOG_SYNTH8_LOOP_CSB_MASK 0x00000f00
-#define PHY_ANALOG_SYNTH8_LOOP_CSB_GET(x) (((x) & 0x00000f00) >> 8)
-#define PHY_ANALOG_SYNTH8_LOOP_CSB_SET(x) (((x) << 8) & 0x00000f00)
-#define PHY_ANALOG_SYNTH8_LOOP_RSB_MSB 16
-#define PHY_ANALOG_SYNTH8_LOOP_RSB_LSB 12
-#define PHY_ANALOG_SYNTH8_LOOP_RSB_MASK 0x0001f000
-#define PHY_ANALOG_SYNTH8_LOOP_RSB_GET(x) (((x) & 0x0001f000) >> 12)
-#define PHY_ANALOG_SYNTH8_LOOP_RSB_SET(x) (((x) << 12) & 0x0001f000)
-#define PHY_ANALOG_SYNTH8_LOOP_CPB_MSB 21
-#define PHY_ANALOG_SYNTH8_LOOP_CPB_LSB 17
-#define PHY_ANALOG_SYNTH8_LOOP_CPB_MASK 0x003e0000
-#define PHY_ANALOG_SYNTH8_LOOP_CPB_GET(x) (((x) & 0x003e0000) >> 17)
-#define PHY_ANALOG_SYNTH8_LOOP_CPB_SET(x) (((x) << 17) & 0x003e0000)
-#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_MSB 26
-#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_LSB 22
-#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_MASK 0x07c00000
-#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_GET(x) (((x) & 0x07c00000) >> 22)
-#define PHY_ANALOG_SYNTH8_LOOP_3RD_ORDER_RB_SET(x) (((x) << 22) & 0x07c00000)
-#define PHY_ANALOG_SYNTH8_REFDIVB_MSB 31
-#define PHY_ANALOG_SYNTH8_REFDIVB_LSB 27
-#define PHY_ANALOG_SYNTH8_REFDIVB_MASK 0xf8000000
-#define PHY_ANALOG_SYNTH8_REFDIVB_GET(x) (((x) & 0xf8000000) >> 27)
-#define PHY_ANALOG_SYNTH8_REFDIVB_SET(x) (((x) << 27) & 0xf8000000)
-
-/* macros for SYNTH9 */
-#define PHY_ANALOG_SYNTH9_ADDRESS 0x000000a0
-#define PHY_ANALOG_SYNTH9_OFFSET 0x000000a0
-#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_MSB 0
-#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_LSB 0
-#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_MASK 0x00000001
-#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_ANALOG_SYNTH9_PFDDELAY_INTN_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_MSB 3
-#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_LSB 1
-#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_MASK 0x0000000e
-#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_GET(x) (((x) & 0x0000000e) >> 1)
-#define PHY_ANALOG_SYNTH9_SLOPE_ICPA0_SET(x) (((x) << 1) & 0x0000000e)
-#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_MSB 7
-#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_LSB 4
-#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_MASK 0x000000f0
-#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_GET(x) (((x) & 0x000000f0) >> 4)
-#define PHY_ANALOG_SYNTH9_LOOP_ICPA0_SET(x) (((x) << 4) & 0x000000f0)
-#define PHY_ANALOG_SYNTH9_LOOP_CSA0_MSB 11
-#define PHY_ANALOG_SYNTH9_LOOP_CSA0_LSB 8
-#define PHY_ANALOG_SYNTH9_LOOP_CSA0_MASK 0x00000f00
-#define PHY_ANALOG_SYNTH9_LOOP_CSA0_GET(x) (((x) & 0x00000f00) >> 8)
-#define PHY_ANALOG_SYNTH9_LOOP_CSA0_SET(x) (((x) << 8) & 0x00000f00)
-#define PHY_ANALOG_SYNTH9_LOOP_RSA0_MSB 16
-#define PHY_ANALOG_SYNTH9_LOOP_RSA0_LSB 12
-#define PHY_ANALOG_SYNTH9_LOOP_RSA0_MASK 0x0001f000
-#define PHY_ANALOG_SYNTH9_LOOP_RSA0_GET(x) (((x) & 0x0001f000) >> 12)
-#define PHY_ANALOG_SYNTH9_LOOP_RSA0_SET(x) (((x) << 12) & 0x0001f000)
-#define PHY_ANALOG_SYNTH9_LOOP_CPA0_MSB 21
-#define PHY_ANALOG_SYNTH9_LOOP_CPA0_LSB 17
-#define PHY_ANALOG_SYNTH9_LOOP_CPA0_MASK 0x003e0000
-#define PHY_ANALOG_SYNTH9_LOOP_CPA0_GET(x) (((x) & 0x003e0000) >> 17)
-#define PHY_ANALOG_SYNTH9_LOOP_CPA0_SET(x) (((x) << 17) & 0x003e0000)
-#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_MSB 26
-#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_LSB 22
-#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_MASK 0x07c00000
-#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_GET(x) (((x) & 0x07c00000) >> 22)
-#define PHY_ANALOG_SYNTH9_LOOP_3RD_ORDER_RA_SET(x) (((x) << 22) & 0x07c00000)
-#define PHY_ANALOG_SYNTH9_REFDIVA_MSB 31
-#define PHY_ANALOG_SYNTH9_REFDIVA_LSB 27
-#define PHY_ANALOG_SYNTH9_REFDIVA_MASK 0xf8000000
-#define PHY_ANALOG_SYNTH9_REFDIVA_GET(x) (((x) & 0xf8000000) >> 27)
-#define PHY_ANALOG_SYNTH9_REFDIVA_SET(x) (((x) << 27) & 0xf8000000)
-
-/* macros for SYNTH10 */
-#define PHY_ANALOG_SYNTH10_ADDRESS 0x000000a4
-#define PHY_ANALOG_SYNTH10_OFFSET 0x000000a4
-#define PHY_ANALOG_SYNTH10_SPARE10A_MSB 1
-#define PHY_ANALOG_SYNTH10_SPARE10A_LSB 0
-#define PHY_ANALOG_SYNTH10_SPARE10A_MASK 0x00000003
-#define PHY_ANALOG_SYNTH10_SPARE10A_GET(x) (((x) & 0x00000003) >> 0)
-#define PHY_ANALOG_SYNTH10_SPARE10A_SET(x) (((x) << 0) & 0x00000003)
-#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_MSB 4
-#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_LSB 2
-#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_MASK 0x0000001c
-#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_GET(x) (((x) & 0x0000001c) >> 2)
-#define PHY_ANALOG_SYNTH10_PWDB_ICLOBIAS50_SET(x) (((x) << 2) & 0x0000001c)
-#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_MSB 7
-#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_LSB 5
-#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_MASK 0x000000e0
-#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_GET(x) (((x) & 0x000000e0) >> 5)
-#define PHY_ANALOG_SYNTH10_PWDB_IRSPARE25_SET(x) (((x) << 5) & 0x000000e0)
-#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_MSB 10
-#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_LSB 8
-#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_MASK 0x00000700
-#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_GET(x) (((x) & 0x00000700) >> 8)
-#define PHY_ANALOG_SYNTH10_PWDB_ICSPARE25_SET(x) (((x) << 8) & 0x00000700)
-#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_MSB 13
-#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_LSB 11
-#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_MASK 0x00003800
-#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_GET(x) (((x) & 0x00003800) >> 11)
-#define PHY_ANALOG_SYNTH10_SLOPE_ICPA1_SET(x) (((x) << 11) & 0x00003800)
-#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_MSB 17
-#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_LSB 14
-#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_MASK 0x0003c000
-#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_GET(x) (((x) & 0x0003c000) >> 14)
-#define PHY_ANALOG_SYNTH10_LOOP_ICPA1_SET(x) (((x) << 14) & 0x0003c000)
-#define PHY_ANALOG_SYNTH10_LOOP_CSA1_MSB 21
-#define PHY_ANALOG_SYNTH10_LOOP_CSA1_LSB 18
-#define PHY_ANALOG_SYNTH10_LOOP_CSA1_MASK 0x003c0000
-#define PHY_ANALOG_SYNTH10_LOOP_CSA1_GET(x) (((x) & 0x003c0000) >> 18)
-#define PHY_ANALOG_SYNTH10_LOOP_CSA1_SET(x) (((x) << 18) & 0x003c0000)
-#define PHY_ANALOG_SYNTH10_LOOP_RSA1_MSB 26
-#define PHY_ANALOG_SYNTH10_LOOP_RSA1_LSB 22
-#define PHY_ANALOG_SYNTH10_LOOP_RSA1_MASK 0x07c00000
-#define PHY_ANALOG_SYNTH10_LOOP_RSA1_GET(x) (((x) & 0x07c00000) >> 22)
-#define PHY_ANALOG_SYNTH10_LOOP_RSA1_SET(x) (((x) << 22) & 0x07c00000)
-#define PHY_ANALOG_SYNTH10_LOOP_CPA1_MSB 31
-#define PHY_ANALOG_SYNTH10_LOOP_CPA1_LSB 27
-#define PHY_ANALOG_SYNTH10_LOOP_CPA1_MASK 0xf8000000
-#define PHY_ANALOG_SYNTH10_LOOP_CPA1_GET(x) (((x) & 0xf8000000) >> 27)
-#define PHY_ANALOG_SYNTH10_LOOP_CPA1_SET(x) (((x) << 27) & 0xf8000000)
-
-/* macros for SYNTH11 */
-#define PHY_ANALOG_SYNTH11_ADDRESS 0x000000a8
-#define PHY_ANALOG_SYNTH11_OFFSET 0x000000a8
-#define PHY_ANALOG_SYNTH11_SPARE11A_MSB 4
-#define PHY_ANALOG_SYNTH11_SPARE11A_LSB 0
-#define PHY_ANALOG_SYNTH11_SPARE11A_MASK 0x0000001f
-#define PHY_ANALOG_SYNTH11_SPARE11A_GET(x) (((x) & 0x0000001f) >> 0)
-#define PHY_ANALOG_SYNTH11_SPARE11A_SET(x) (((x) << 0) & 0x0000001f)
-#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_MSB 5
-#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_LSB 5
-#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_MASK 0x00000020
-#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_GET(x) (((x) & 0x00000020) >> 5)
-#define PHY_ANALOG_SYNTH11_FORCE_LOBUF5G_ON_SET(x) (((x) << 5) & 0x00000020)
-#define PHY_ANALOG_SYNTH11_LOREFSEL_MSB 7
-#define PHY_ANALOG_SYNTH11_LOREFSEL_LSB 6
-#define PHY_ANALOG_SYNTH11_LOREFSEL_MASK 0x000000c0
-#define PHY_ANALOG_SYNTH11_LOREFSEL_GET(x) (((x) & 0x000000c0) >> 6)
-#define PHY_ANALOG_SYNTH11_LOREFSEL_SET(x) (((x) << 6) & 0x000000c0)
-#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_MSB 9
-#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_LSB 8
-#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_MASK 0x00000300
-#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_GET(x) (((x) & 0x00000300) >> 8)
-#define PHY_ANALOG_SYNTH11_LOBUF2GTUNE_SET(x) (((x) << 8) & 0x00000300)
-#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_MSB 10
-#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_LSB 10
-#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_MASK 0x00000400
-#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_GET(x) (((x) & 0x00000400) >> 10)
-#define PHY_ANALOG_SYNTH11_CPSTEERING_MODE_SET(x) (((x) << 10) & 0x00000400)
-#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_MSB 13
-#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_LSB 11
-#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_MASK 0x00003800
-#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_GET(x) (((x) & 0x00003800) >> 11)
-#define PHY_ANALOG_SYNTH11_SLOPE_ICPA2_SET(x) (((x) << 11) & 0x00003800)
-#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_MSB 17
-#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_LSB 14
-#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_MASK 0x0003c000
-#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_GET(x) (((x) & 0x0003c000) >> 14)
-#define PHY_ANALOG_SYNTH11_LOOP_ICPA2_SET(x) (((x) << 14) & 0x0003c000)
-#define PHY_ANALOG_SYNTH11_LOOP_CSA2_MSB 21
-#define PHY_ANALOG_SYNTH11_LOOP_CSA2_LSB 18
-#define PHY_ANALOG_SYNTH11_LOOP_CSA2_MASK 0x003c0000
-#define PHY_ANALOG_SYNTH11_LOOP_CSA2_GET(x) (((x) & 0x003c0000) >> 18)
-#define PHY_ANALOG_SYNTH11_LOOP_CSA2_SET(x) (((x) << 18) & 0x003c0000)
-#define PHY_ANALOG_SYNTH11_LOOP_RSA2_MSB 26
-#define PHY_ANALOG_SYNTH11_LOOP_RSA2_LSB 22
-#define PHY_ANALOG_SYNTH11_LOOP_RSA2_MASK 0x07c00000
-#define PHY_ANALOG_SYNTH11_LOOP_RSA2_GET(x) (((x) & 0x07c00000) >> 22)
-#define PHY_ANALOG_SYNTH11_LOOP_RSA2_SET(x) (((x) << 22) & 0x07c00000)
-#define PHY_ANALOG_SYNTH11_LOOP_CPA2_MSB 31
-#define PHY_ANALOG_SYNTH11_LOOP_CPA2_LSB 27
-#define PHY_ANALOG_SYNTH11_LOOP_CPA2_MASK 0xf8000000
-#define PHY_ANALOG_SYNTH11_LOOP_CPA2_GET(x) (((x) & 0xf8000000) >> 27)
-#define PHY_ANALOG_SYNTH11_LOOP_CPA2_SET(x) (((x) << 27) & 0xf8000000)
-
-/* macros for SYNTH12 */
-#define PHY_ANALOG_SYNTH12_ADDRESS 0x000000ac
-#define PHY_ANALOG_SYNTH12_OFFSET 0x000000ac
-#define PHY_ANALOG_SYNTH12_SPARE12A_MSB 9
-#define PHY_ANALOG_SYNTH12_SPARE12A_LSB 0
-#define PHY_ANALOG_SYNTH12_SPARE12A_MASK 0x000003ff
-#define PHY_ANALOG_SYNTH12_SPARE12A_GET(x) (((x) & 0x000003ff) >> 0)
-#define PHY_ANALOG_SYNTH12_SPARE12A_SET(x) (((x) << 0) & 0x000003ff)
-#define PHY_ANALOG_SYNTH12_LOOPLEAKCUR_FRACN_MSB 13
-#define PHY_ANALOG_SYNTH12_LOOPLEAKCUR_FRACN_LSB 10
-#define PHY_ANALOG_SYNTH12_LOOPLEAKCUR_FRACN_MASK 0x00003c00
-#define PHY_ANALOG_SYNTH12_LOOPLEAKCUR_FRACN_GET(x) (((x) & 0x00003c00) >> 10)
-#define PHY_ANALOG_SYNTH12_LOOPLEAKCUR_FRACN_SET(x) (((x) << 10) & 0x00003c00)
-#define PHY_ANALOG_SYNTH12_CPLOWLK_FRACN_MSB 14
-#define PHY_ANALOG_SYNTH12_CPLOWLK_FRACN_LSB 14
-#define PHY_ANALOG_SYNTH12_CPLOWLK_FRACN_MASK 0x00004000
-#define PHY_ANALOG_SYNTH12_CPLOWLK_FRACN_GET(x) (((x) & 0x00004000) >> 14)
-#define PHY_ANALOG_SYNTH12_CPLOWLK_FRACN_SET(x) (((x) << 14) & 0x00004000)
-#define PHY_ANALOG_SYNTH12_CPBIAS_FRACN_MSB 16
-#define PHY_ANALOG_SYNTH12_CPBIAS_FRACN_LSB 15
-#define PHY_ANALOG_SYNTH12_CPBIAS_FRACN_MASK 0x00018000
-#define PHY_ANALOG_SYNTH12_CPBIAS_FRACN_GET(x) (((x) & 0x00018000) >> 15)
-#define PHY_ANALOG_SYNTH12_CPBIAS_FRACN_SET(x) (((x) << 15) & 0x00018000)
-#define PHY_ANALOG_SYNTH12_SYNTHDIGOUTEN_MSB 17
-#define PHY_ANALOG_SYNTH12_SYNTHDIGOUTEN_LSB 17
-#define PHY_ANALOG_SYNTH12_SYNTHDIGOUTEN_MASK 0x00020000
-#define PHY_ANALOG_SYNTH12_SYNTHDIGOUTEN_GET(x) (((x) & 0x00020000) >> 17)
-#define PHY_ANALOG_SYNTH12_SYNTHDIGOUTEN_SET(x) (((x) << 17) & 0x00020000)
-#define PHY_ANALOG_SYNTH12_STRCONT_MSB 18
-#define PHY_ANALOG_SYNTH12_STRCONT_LSB 18
-#define PHY_ANALOG_SYNTH12_STRCONT_MASK 0x00040000
-#define PHY_ANALOG_SYNTH12_STRCONT_GET(x) (((x) & 0x00040000) >> 18)
-#define PHY_ANALOG_SYNTH12_STRCONT_SET(x) (((x) << 18) & 0x00040000)
-#define PHY_ANALOG_SYNTH12_VREFMUL3_MSB 22
-#define PHY_ANALOG_SYNTH12_VREFMUL3_LSB 19
-#define PHY_ANALOG_SYNTH12_VREFMUL3_MASK 0x00780000
-#define PHY_ANALOG_SYNTH12_VREFMUL3_GET(x) (((x) & 0x00780000) >> 19)
-#define PHY_ANALOG_SYNTH12_VREFMUL3_SET(x) (((x) << 19) & 0x00780000)
-#define PHY_ANALOG_SYNTH12_VREFMUL2_MSB 26
-#define PHY_ANALOG_SYNTH12_VREFMUL2_LSB 23
-#define PHY_ANALOG_SYNTH12_VREFMUL2_MASK 0x07800000
-#define PHY_ANALOG_SYNTH12_VREFMUL2_GET(x) (((x) & 0x07800000) >> 23)
-#define PHY_ANALOG_SYNTH12_VREFMUL2_SET(x) (((x) << 23) & 0x07800000)
-#define PHY_ANALOG_SYNTH12_VREFMUL1_MSB 30
-#define PHY_ANALOG_SYNTH12_VREFMUL1_LSB 27
-#define PHY_ANALOG_SYNTH12_VREFMUL1_MASK 0x78000000
-#define PHY_ANALOG_SYNTH12_VREFMUL1_GET(x) (((x) & 0x78000000) >> 27)
-#define PHY_ANALOG_SYNTH12_VREFMUL1_SET(x) (((x) << 27) & 0x78000000)
-#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_MSB 31
-#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_LSB 31
-#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_MASK 0x80000000
-#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_GET(x) (((x) & 0x80000000) >> 31)
-#define PHY_ANALOG_SYNTH12_CLK_DOUBLER_EN_SET(x) (((x) << 31) & 0x80000000)
-
-/* macros for SYNTH13 */
-#define PHY_ANALOG_SYNTH13_ADDRESS 0x000000b0
-#define PHY_ANALOG_SYNTH13_OFFSET 0x000000b0
-#define PHY_ANALOG_SYNTH13_SPARE13A_MSB 0
-#define PHY_ANALOG_SYNTH13_SPARE13A_LSB 0
-#define PHY_ANALOG_SYNTH13_SPARE13A_MASK 0x00000001
-#define PHY_ANALOG_SYNTH13_SPARE13A_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_ANALOG_SYNTH13_SPARE13A_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_ANALOG_SYNTH13_SLOPE_ICPA_FRACN_MSB 3
-#define PHY_ANALOG_SYNTH13_SLOPE_ICPA_FRACN_LSB 1
-#define PHY_ANALOG_SYNTH13_SLOPE_ICPA_FRACN_MASK 0x0000000e
-#define PHY_ANALOG_SYNTH13_SLOPE_ICPA_FRACN_GET(x) (((x) & 0x0000000e) >> 1)
-#define PHY_ANALOG_SYNTH13_SLOPE_ICPA_FRACN_SET(x) (((x) << 1) & 0x0000000e)
-#define PHY_ANALOG_SYNTH13_LOOP_ICPA_FRACN_MSB 7
-#define PHY_ANALOG_SYNTH13_LOOP_ICPA_FRACN_LSB 4
-#define PHY_ANALOG_SYNTH13_LOOP_ICPA_FRACN_MASK 0x000000f0
-#define PHY_ANALOG_SYNTH13_LOOP_ICPA_FRACN_GET(x) (((x) & 0x000000f0) >> 4)
-#define PHY_ANALOG_SYNTH13_LOOP_ICPA_FRACN_SET(x) (((x) << 4) & 0x000000f0)
-#define PHY_ANALOG_SYNTH13_LOOP_CSA_FRACN_MSB 11
-#define PHY_ANALOG_SYNTH13_LOOP_CSA_FRACN_LSB 8
-#define PHY_ANALOG_SYNTH13_LOOP_CSA_FRACN_MASK 0x00000f00
-#define PHY_ANALOG_SYNTH13_LOOP_CSA_FRACN_GET(x) (((x) & 0x00000f00) >> 8)
-#define PHY_ANALOG_SYNTH13_LOOP_CSA_FRACN_SET(x) (((x) << 8) & 0x00000f00)
-#define PHY_ANALOG_SYNTH13_LOOP_RSA_FRACN_MSB 16
-#define PHY_ANALOG_SYNTH13_LOOP_RSA_FRACN_LSB 12
-#define PHY_ANALOG_SYNTH13_LOOP_RSA_FRACN_MASK 0x0001f000
-#define PHY_ANALOG_SYNTH13_LOOP_RSA_FRACN_GET(x) (((x) & 0x0001f000) >> 12)
-#define PHY_ANALOG_SYNTH13_LOOP_RSA_FRACN_SET(x) (((x) << 12) & 0x0001f000)
-#define PHY_ANALOG_SYNTH13_LOOP_CPA_FRACN_MSB 21
-#define PHY_ANALOG_SYNTH13_LOOP_CPA_FRACN_LSB 17
-#define PHY_ANALOG_SYNTH13_LOOP_CPA_FRACN_MASK 0x003e0000
-#define PHY_ANALOG_SYNTH13_LOOP_CPA_FRACN_GET(x) (((x) & 0x003e0000) >> 17)
-#define PHY_ANALOG_SYNTH13_LOOP_CPA_FRACN_SET(x) (((x) << 17) & 0x003e0000)
-#define PHY_ANALOG_SYNTH13_LOOP_3RD_ORDER_RA_FRACN_MSB 26
-#define PHY_ANALOG_SYNTH13_LOOP_3RD_ORDER_RA_FRACN_LSB 22
-#define PHY_ANALOG_SYNTH13_LOOP_3RD_ORDER_RA_FRACN_MASK 0x07c00000
-#define PHY_ANALOG_SYNTH13_LOOP_3RD_ORDER_RA_FRACN_GET(x) (((x) & 0x07c00000) >> 22)
-#define PHY_ANALOG_SYNTH13_LOOP_3RD_ORDER_RA_FRACN_SET(x) (((x) << 22) & 0x07c00000)
-#define PHY_ANALOG_SYNTH13_REFDIVA_FRACN_MSB 31
-#define PHY_ANALOG_SYNTH13_REFDIVA_FRACN_LSB 27
-#define PHY_ANALOG_SYNTH13_REFDIVA_FRACN_MASK 0xf8000000
-#define PHY_ANALOG_SYNTH13_REFDIVA_FRACN_GET(x) (((x) & 0xf8000000) >> 27)
-#define PHY_ANALOG_SYNTH13_REFDIVA_FRACN_SET(x) (((x) << 27) & 0xf8000000)
-
-/* macros for SYNTH14 */
-#define PHY_ANALOG_SYNTH14_ADDRESS 0x000000b4
-#define PHY_ANALOG_SYNTH14_OFFSET 0x000000b4
-#define PHY_ANALOG_SYNTH14_SPARE14A_MSB 1
-#define PHY_ANALOG_SYNTH14_SPARE14A_LSB 0
-#define PHY_ANALOG_SYNTH14_SPARE14A_MASK 0x00000003
-#define PHY_ANALOG_SYNTH14_SPARE14A_GET(x) (((x) & 0x00000003) >> 0)
-#define PHY_ANALOG_SYNTH14_SPARE14A_SET(x) (((x) << 0) & 0x00000003)
-#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_3_MSB 3
-#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_3_LSB 2
-#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_3_MASK 0x0000000c
-#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_3_GET(x) (((x) & 0x0000000c) >> 2)
-#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_3_SET(x) (((x) << 2) & 0x0000000c)
-#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_3_MSB 5
-#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_3_LSB 4
-#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_3_MASK 0x00000030
-#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_3_GET(x) (((x) & 0x00000030) >> 4)
-#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_3_SET(x) (((x) << 4) & 0x00000030)
-#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_2_MSB 7
-#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_2_LSB 6
-#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_2_MASK 0x000000c0
-#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_2_GET(x) (((x) & 0x000000c0) >> 6)
-#define PHY_ANALOG_SYNTH14_LOBUF5GTUNE_2_SET(x) (((x) << 6) & 0x000000c0)
-#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_2_MSB 9
-#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_2_LSB 8
-#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_2_MASK 0x00000300
-#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_2_GET(x) (((x) & 0x00000300) >> 8)
-#define PHY_ANALOG_SYNTH14_LOBUF2GTUNE_2_SET(x) (((x) << 8) & 0x00000300)
-#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_3_MSB 10
-#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_3_LSB 10
-#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_3_MASK 0x00000400
-#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_3_GET(x) (((x) & 0x00000400) >> 10)
-#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_3_SET(x) (((x) << 10) & 0x00000400)
-#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_3_MSB 11
-#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_3_LSB 11
-#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_3_MASK 0x00000800
-#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_3_GET(x) (((x) & 0x00000800) >> 11)
-#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_3_SET(x) (((x) << 11) & 0x00000800)
-#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_2_MSB 12
-#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_2_LSB 12
-#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_2_MASK 0x00001000
-#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_2_GET(x) (((x) & 0x00001000) >> 12)
-#define PHY_ANALOG_SYNTH14_PWD_LOBUF5G_2_SET(x) (((x) << 12) & 0x00001000)
-#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_2_MSB 13
-#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_2_LSB 13
-#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_2_MASK 0x00002000
-#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_2_GET(x) (((x) & 0x00002000) >> 13)
-#define PHY_ANALOG_SYNTH14_PWD_LOBUF2G_2_SET(x) (((x) << 13) & 0x00002000)
-#define PHY_ANALOG_SYNTH14_PWUPLO23_PD_MSB 16
-#define PHY_ANALOG_SYNTH14_PWUPLO23_PD_LSB 14
-#define PHY_ANALOG_SYNTH14_PWUPLO23_PD_MASK 0x0001c000
-#define PHY_ANALOG_SYNTH14_PWUPLO23_PD_GET(x) (((x) & 0x0001c000) >> 14)
-#define PHY_ANALOG_SYNTH14_PWUPLO23_PD_SET(x) (((x) << 14) & 0x0001c000)
-#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_3_MSB 19
-#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_3_LSB 17
-#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_3_MASK 0x000e0000
-#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_3_GET(x) (((x) & 0x000e0000) >> 17)
-#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_3_SET(x) (((x) << 17) & 0x000e0000)
-#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_3_MSB 22
-#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_3_LSB 20
-#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_3_MASK 0x00700000
-#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_3_GET(x) (((x) & 0x00700000) >> 20)
-#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_3_SET(x) (((x) << 20) & 0x00700000)
-#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_2_MSB 25
-#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_2_LSB 23
-#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_2_MASK 0x03800000
-#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_2_GET(x) (((x) & 0x03800000) >> 23)
-#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF5G50_2_SET(x) (((x) << 23) & 0x03800000)
-#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_2_MSB 28
-#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_2_LSB 26
-#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_2_MASK 0x1c000000
-#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_2_GET(x) (((x) & 0x1c000000) >> 26)
-#define PHY_ANALOG_SYNTH14_PWDB_ICLOBUF2G50_2_SET(x) (((x) << 26) & 0x1c000000)
-#define PHY_ANALOG_SYNTH14_PWDB_ICLVLSHFT_MSB 31
-#define PHY_ANALOG_SYNTH14_PWDB_ICLVLSHFT_LSB 29
-#define PHY_ANALOG_SYNTH14_PWDB_ICLVLSHFT_MASK 0xe0000000
-#define PHY_ANALOG_SYNTH14_PWDB_ICLVLSHFT_GET(x) (((x) & 0xe0000000) >> 29)
-#define PHY_ANALOG_SYNTH14_PWDB_ICLVLSHFT_SET(x) (((x) << 29) & 0xe0000000)
-
-/* macros for BIAS1 */
-#define PHY_ANALOG_BIAS1_ADDRESS 0x000000c0
-#define PHY_ANALOG_BIAS1_OFFSET 0x000000c0
-#define PHY_ANALOG_BIAS1_SPARE1_MSB 6
-#define PHY_ANALOG_BIAS1_SPARE1_LSB 0
-#define PHY_ANALOG_BIAS1_SPARE1_MASK 0x0000007f
-#define PHY_ANALOG_BIAS1_SPARE1_GET(x) (((x) & 0x0000007f) >> 0)
-#define PHY_ANALOG_BIAS1_SPARE1_SET(x) (((x) << 0) & 0x0000007f)
-#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_MSB 9
-#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_LSB 7
-#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_MASK 0x00000380
-#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_GET(x) (((x) & 0x00000380) >> 7)
-#define PHY_ANALOG_BIAS1_PWD_IC25V2IQ_SET(x) (((x) << 7) & 0x00000380)
-#define PHY_ANALOG_BIAS1_PWD_IC25V2II_MSB 12
-#define PHY_ANALOG_BIAS1_PWD_IC25V2II_LSB 10
-#define PHY_ANALOG_BIAS1_PWD_IC25V2II_MASK 0x00001c00
-#define PHY_ANALOG_BIAS1_PWD_IC25V2II_GET(x) (((x) & 0x00001c00) >> 10)
-#define PHY_ANALOG_BIAS1_PWD_IC25V2II_SET(x) (((x) << 10) & 0x00001c00)
-#define PHY_ANALOG_BIAS1_PWD_IC25BB_MSB 15
-#define PHY_ANALOG_BIAS1_PWD_IC25BB_LSB 13
-#define PHY_ANALOG_BIAS1_PWD_IC25BB_MASK 0x0000e000
-#define PHY_ANALOG_BIAS1_PWD_IC25BB_GET(x) (((x) & 0x0000e000) >> 13)
-#define PHY_ANALOG_BIAS1_PWD_IC25BB_SET(x) (((x) << 13) & 0x0000e000)
-#define PHY_ANALOG_BIAS1_PWD_IC25DAC_MSB 18
-#define PHY_ANALOG_BIAS1_PWD_IC25DAC_LSB 16
-#define PHY_ANALOG_BIAS1_PWD_IC25DAC_MASK 0x00070000
-#define PHY_ANALOG_BIAS1_PWD_IC25DAC_GET(x) (((x) & 0x00070000) >> 16)
-#define PHY_ANALOG_BIAS1_PWD_IC25DAC_SET(x) (((x) << 16) & 0x00070000)
-#define PHY_ANALOG_BIAS1_PWD_IC25FIR_MSB 21
-#define PHY_ANALOG_BIAS1_PWD_IC25FIR_LSB 19
-#define PHY_ANALOG_BIAS1_PWD_IC25FIR_MASK 0x00380000
-#define PHY_ANALOG_BIAS1_PWD_IC25FIR_GET(x) (((x) & 0x00380000) >> 19)
-#define PHY_ANALOG_BIAS1_PWD_IC25FIR_SET(x) (((x) << 19) & 0x00380000)
-#define PHY_ANALOG_BIAS1_PWD_IC25ADC_MSB 24
-#define PHY_ANALOG_BIAS1_PWD_IC25ADC_LSB 22
-#define PHY_ANALOG_BIAS1_PWD_IC25ADC_MASK 0x01c00000
-#define PHY_ANALOG_BIAS1_PWD_IC25ADC_GET(x) (((x) & 0x01c00000) >> 22)
-#define PHY_ANALOG_BIAS1_PWD_IC25ADC_SET(x) (((x) << 22) & 0x01c00000)
-#define PHY_ANALOG_BIAS1_BIAS_SEL_MSB 31
-#define PHY_ANALOG_BIAS1_BIAS_SEL_LSB 25
-#define PHY_ANALOG_BIAS1_BIAS_SEL_MASK 0xfe000000
-#define PHY_ANALOG_BIAS1_BIAS_SEL_GET(x) (((x) & 0xfe000000) >> 25)
-#define PHY_ANALOG_BIAS1_BIAS_SEL_SET(x) (((x) << 25) & 0xfe000000)
-
-/* macros for BIAS2 */
-#define PHY_ANALOG_BIAS2_ADDRESS 0x000000c4
-#define PHY_ANALOG_BIAS2_OFFSET 0x000000c4
-#define PHY_ANALOG_BIAS2_SPARE2_MSB 4
-#define PHY_ANALOG_BIAS2_SPARE2_LSB 0
-#define PHY_ANALOG_BIAS2_SPARE2_MASK 0x0000001f
-#define PHY_ANALOG_BIAS2_SPARE2_GET(x) (((x) & 0x0000001f) >> 0)
-#define PHY_ANALOG_BIAS2_SPARE2_SET(x) (((x) << 0) & 0x0000001f)
-#define PHY_ANALOG_BIAS2_PWD_IC25XPA_MSB 7
-#define PHY_ANALOG_BIAS2_PWD_IC25XPA_LSB 5
-#define PHY_ANALOG_BIAS2_PWD_IC25XPA_MASK 0x000000e0
-#define PHY_ANALOG_BIAS2_PWD_IC25XPA_GET(x) (((x) & 0x000000e0) >> 5)
-#define PHY_ANALOG_BIAS2_PWD_IC25XPA_SET(x) (((x) << 5) & 0x000000e0)
-#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_MSB 10
-#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_LSB 8
-#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_MASK 0x00000700
-#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_GET(x) (((x) & 0x00000700) >> 8)
-#define PHY_ANALOG_BIAS2_PWD_IC25XTAL_SET(x) (((x) << 8) & 0x00000700)
-#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_MSB 13
-#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_LSB 11
-#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_MASK 0x00003800
-#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_GET(x) (((x) & 0x00003800) >> 11)
-#define PHY_ANALOG_BIAS2_PWD_IC25TXRF_SET(x) (((x) << 11) & 0x00003800)
-#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_MSB 16
-#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_LSB 14
-#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_MASK 0x0001c000
-#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_GET(x) (((x) & 0x0001c000) >> 14)
-#define PHY_ANALOG_BIAS2_PWD_IC25RXRF_SET(x) (((x) << 14) & 0x0001c000)
-#define PHY_ANALOG_BIAS2_PWD_IC25SYNTH_MSB 19
-#define PHY_ANALOG_BIAS2_PWD_IC25SYNTH_LSB 17
-#define PHY_ANALOG_BIAS2_PWD_IC25SYNTH_MASK 0x000e0000
-#define PHY_ANALOG_BIAS2_PWD_IC25SYNTH_GET(x) (((x) & 0x000e0000) >> 17)
-#define PHY_ANALOG_BIAS2_PWD_IC25SYNTH_SET(x) (((x) << 17) & 0x000e0000)
-#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_MSB 22
-#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_LSB 20
-#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_MASK 0x00700000
-#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_GET(x) (((x) & 0x00700000) >> 20)
-#define PHY_ANALOG_BIAS2_PWD_IC25PLLREG_SET(x) (((x) << 20) & 0x00700000)
-#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_MSB 25
-#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_LSB 23
-#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_MASK 0x03800000
-#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_GET(x) (((x) & 0x03800000) >> 23)
-#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP2_SET(x) (((x) << 23) & 0x03800000)
-#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_MSB 28
-#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_LSB 26
-#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_MASK 0x1c000000
-#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_GET(x) (((x) & 0x1c000000) >> 26)
-#define PHY_ANALOG_BIAS2_PWD_IC25PLLCP_SET(x) (((x) << 26) & 0x1c000000)
-#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_MSB 31
-#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_LSB 29
-#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_MASK 0xe0000000
-#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_GET(x) (((x) & 0xe0000000) >> 29)
-#define PHY_ANALOG_BIAS2_PWD_IC25PLLGM_SET(x) (((x) << 29) & 0xe0000000)
-
-/* macros for BIAS3 */
-#define PHY_ANALOG_BIAS3_ADDRESS 0x000000c8
-#define PHY_ANALOG_BIAS3_OFFSET 0x000000c8
-#define PHY_ANALOG_BIAS3_SPARE3_MSB 1
-#define PHY_ANALOG_BIAS3_SPARE3_LSB 0
-#define PHY_ANALOG_BIAS3_SPARE3_MASK 0x00000003
-#define PHY_ANALOG_BIAS3_SPARE3_GET(x) (((x) & 0x00000003) >> 0)
-#define PHY_ANALOG_BIAS3_SPARE3_SET(x) (((x) << 0) & 0x00000003)
-#define PHY_ANALOG_BIAS3_PWD_IR25SAR_MSB 4
-#define PHY_ANALOG_BIAS3_PWD_IR25SAR_LSB 2
-#define PHY_ANALOG_BIAS3_PWD_IR25SAR_MASK 0x0000001c
-#define PHY_ANALOG_BIAS3_PWD_IR25SAR_GET(x) (((x) & 0x0000001c) >> 2)
-#define PHY_ANALOG_BIAS3_PWD_IR25SAR_SET(x) (((x) << 2) & 0x0000001c)
-#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_MSB 7
-#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_LSB 5
-#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_MASK 0x000000e0
-#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_GET(x) (((x) & 0x000000e0) >> 5)
-#define PHY_ANALOG_BIAS3_PWD_IR25TXRF_SET(x) (((x) << 5) & 0x000000e0)
-#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_MSB 10
-#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_LSB 8
-#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_MASK 0x00000700
-#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_GET(x) (((x) & 0x00000700) >> 8)
-#define PHY_ANALOG_BIAS3_PWD_IR25RXRF_SET(x) (((x) << 8) & 0x00000700)
-#define PHY_ANALOG_BIAS3_PWD_IR25SYNTH_MSB 13
-#define PHY_ANALOG_BIAS3_PWD_IR25SYNTH_LSB 11
-#define PHY_ANALOG_BIAS3_PWD_IR25SYNTH_MASK 0x00003800
-#define PHY_ANALOG_BIAS3_PWD_IR25SYNTH_GET(x) (((x) & 0x00003800) >> 11)
-#define PHY_ANALOG_BIAS3_PWD_IR25SYNTH_SET(x) (((x) << 11) & 0x00003800)
-#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_MSB 16
-#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_LSB 14
-#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_MASK 0x0001c000
-#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_GET(x) (((x) & 0x0001c000) >> 14)
-#define PHY_ANALOG_BIAS3_PWD_IR25PLLREG_SET(x) (((x) << 14) & 0x0001c000)
-#define PHY_ANALOG_BIAS3_PWD_IR25BB_MSB 19
-#define PHY_ANALOG_BIAS3_PWD_IR25BB_LSB 17
-#define PHY_ANALOG_BIAS3_PWD_IR25BB_MASK 0x000e0000
-#define PHY_ANALOG_BIAS3_PWD_IR25BB_GET(x) (((x) & 0x000e0000) >> 17)
-#define PHY_ANALOG_BIAS3_PWD_IR25BB_SET(x) (((x) << 17) & 0x000e0000)
-#define PHY_ANALOG_BIAS3_PWD_IR50DAC_MSB 22
-#define PHY_ANALOG_BIAS3_PWD_IR50DAC_LSB 20
-#define PHY_ANALOG_BIAS3_PWD_IR50DAC_MASK 0x00700000
-#define PHY_ANALOG_BIAS3_PWD_IR50DAC_GET(x) (((x) & 0x00700000) >> 20)
-#define PHY_ANALOG_BIAS3_PWD_IR50DAC_SET(x) (((x) << 20) & 0x00700000)
-#define PHY_ANALOG_BIAS3_PWD_IR25DAC_MSB 25
-#define PHY_ANALOG_BIAS3_PWD_IR25DAC_LSB 23
-#define PHY_ANALOG_BIAS3_PWD_IR25DAC_MASK 0x03800000
-#define PHY_ANALOG_BIAS3_PWD_IR25DAC_GET(x) (((x) & 0x03800000) >> 23)
-#define PHY_ANALOG_BIAS3_PWD_IR25DAC_SET(x) (((x) << 23) & 0x03800000)
-#define PHY_ANALOG_BIAS3_PWD_IR25FIR_MSB 28
-#define PHY_ANALOG_BIAS3_PWD_IR25FIR_LSB 26
-#define PHY_ANALOG_BIAS3_PWD_IR25FIR_MASK 0x1c000000
-#define PHY_ANALOG_BIAS3_PWD_IR25FIR_GET(x) (((x) & 0x1c000000) >> 26)
-#define PHY_ANALOG_BIAS3_PWD_IR25FIR_SET(x) (((x) << 26) & 0x1c000000)
-#define PHY_ANALOG_BIAS3_PWD_IR50ADC_MSB 31
-#define PHY_ANALOG_BIAS3_PWD_IR50ADC_LSB 29
-#define PHY_ANALOG_BIAS3_PWD_IR50ADC_MASK 0xe0000000
-#define PHY_ANALOG_BIAS3_PWD_IR50ADC_GET(x) (((x) & 0xe0000000) >> 29)
-#define PHY_ANALOG_BIAS3_PWD_IR50ADC_SET(x) (((x) << 29) & 0xe0000000)
-
-/* macros for BIAS4 */
-#define PHY_ANALOG_BIAS4_ADDRESS 0x000000cc
-#define PHY_ANALOG_BIAS4_OFFSET 0x000000cc
-#define PHY_ANALOG_BIAS4_SPARE4_MSB 10
-#define PHY_ANALOG_BIAS4_SPARE4_LSB 0
-#define PHY_ANALOG_BIAS4_SPARE4_MASK 0x000007ff
-#define PHY_ANALOG_BIAS4_SPARE4_GET(x) (((x) & 0x000007ff) >> 0)
-#define PHY_ANALOG_BIAS4_SPARE4_SET(x) (((x) << 0) & 0x000007ff)
-#define PHY_ANALOG_BIAS4_PWD_IR25SPARED_MSB 13
-#define PHY_ANALOG_BIAS4_PWD_IR25SPARED_LSB 11
-#define PHY_ANALOG_BIAS4_PWD_IR25SPARED_MASK 0x00003800
-#define PHY_ANALOG_BIAS4_PWD_IR25SPARED_GET(x) (((x) & 0x00003800) >> 11)
-#define PHY_ANALOG_BIAS4_PWD_IR25SPARED_SET(x) (((x) << 11) & 0x00003800)
-#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_MSB 16
-#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_LSB 14
-#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_MASK 0x0001c000
-#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_GET(x) (((x) & 0x0001c000) >> 14)
-#define PHY_ANALOG_BIAS4_PWD_IR25SPAREC_SET(x) (((x) << 14) & 0x0001c000)
-#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_MSB 19
-#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_LSB 17
-#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_MASK 0x000e0000
-#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_GET(x) (((x) & 0x000e0000) >> 17)
-#define PHY_ANALOG_BIAS4_PWD_IR25SPAREB_SET(x) (((x) << 17) & 0x000e0000)
-#define PHY_ANALOG_BIAS4_PWD_IR25XPA_MSB 22
-#define PHY_ANALOG_BIAS4_PWD_IR25XPA_LSB 20
-#define PHY_ANALOG_BIAS4_PWD_IR25XPA_MASK 0x00700000
-#define PHY_ANALOG_BIAS4_PWD_IR25XPA_GET(x) (((x) & 0x00700000) >> 20)
-#define PHY_ANALOG_BIAS4_PWD_IR25XPA_SET(x) (((x) << 20) & 0x00700000)
-#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_MSB 25
-#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_LSB 23
-#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_MASK 0x03800000
-#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_GET(x) (((x) & 0x03800000) >> 23)
-#define PHY_ANALOG_BIAS4_PWD_IC25SPAREC_SET(x) (((x) << 23) & 0x03800000)
-#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_MSB 28
-#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_LSB 26
-#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_MASK 0x1c000000
-#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_GET(x) (((x) & 0x1c000000) >> 26)
-#define PHY_ANALOG_BIAS4_PWD_IC25SPAREB_SET(x) (((x) << 26) & 0x1c000000)
-#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_MSB 31
-#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_LSB 29
-#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_MASK 0xe0000000
-#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_GET(x) (((x) & 0xe0000000) >> 29)
-#define PHY_ANALOG_BIAS4_PWD_IC25SPAREA_SET(x) (((x) << 29) & 0xe0000000)
-
-/* macros for RXTX1 */
-#define PHY_ANALOG_RXTX1_ADDRESS 0x00000100
-#define PHY_ANALOG_RXTX1_OFFSET 0x00000100
-#define PHY_ANALOG_RXTX1_SCFIR_GAIN_MSB 0
-#define PHY_ANALOG_RXTX1_SCFIR_GAIN_LSB 0
-#define PHY_ANALOG_RXTX1_SCFIR_GAIN_MASK 0x00000001
-#define PHY_ANALOG_RXTX1_SCFIR_GAIN_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_ANALOG_RXTX1_SCFIR_GAIN_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_ANALOG_RXTX1_MANRXGAIN_MSB 1
-#define PHY_ANALOG_RXTX1_MANRXGAIN_LSB 1
-#define PHY_ANALOG_RXTX1_MANRXGAIN_MASK 0x00000002
-#define PHY_ANALOG_RXTX1_MANRXGAIN_GET(x) (((x) & 0x00000002) >> 1)
-#define PHY_ANALOG_RXTX1_MANRXGAIN_SET(x) (((x) << 1) & 0x00000002)
-#define PHY_ANALOG_RXTX1_AGC_DBDAC_MSB 5
-#define PHY_ANALOG_RXTX1_AGC_DBDAC_LSB 2
-#define PHY_ANALOG_RXTX1_AGC_DBDAC_MASK 0x0000003c
-#define PHY_ANALOG_RXTX1_AGC_DBDAC_GET(x) (((x) & 0x0000003c) >> 2)
-#define PHY_ANALOG_RXTX1_AGC_DBDAC_SET(x) (((x) << 2) & 0x0000003c)
-#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_MSB 6
-#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_LSB 6
-#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_MASK 0x00000040
-#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_GET(x) (((x) & 0x00000040) >> 6)
-#define PHY_ANALOG_RXTX1_OVR_AGC_DBDAC_SET(x) (((x) << 6) & 0x00000040)
-#define PHY_ANALOG_RXTX1_ENABLE_PAL_MSB 7
-#define PHY_ANALOG_RXTX1_ENABLE_PAL_LSB 7
-#define PHY_ANALOG_RXTX1_ENABLE_PAL_MASK 0x00000080
-#define PHY_ANALOG_RXTX1_ENABLE_PAL_GET(x) (((x) & 0x00000080) >> 7)
-#define PHY_ANALOG_RXTX1_ENABLE_PAL_SET(x) (((x) << 7) & 0x00000080)
-#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_MSB 8
-#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_LSB 8
-#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_MASK 0x00000100
-#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_GET(x) (((x) & 0x00000100) >> 8)
-#define PHY_ANALOG_RXTX1_ENABLE_PAL_OVR_SET(x) (((x) << 8) & 0x00000100)
-#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_MSB 11
-#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_LSB 9
-#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_MASK 0x00000e00
-#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_GET(x) (((x) & 0x00000e00) >> 9)
-#define PHY_ANALOG_RXTX1_TX1DB_BIQUAD_SET(x) (((x) << 9) & 0x00000e00)
-#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_MSB 13
-#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_LSB 12
-#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_MASK 0x00003000
-#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_GET(x) (((x) & 0x00003000) >> 12)
-#define PHY_ANALOG_RXTX1_TX6DB_BIQUAD_SET(x) (((x) << 12) & 0x00003000)
-#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_MSB 14
-#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_LSB 14
-#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_MASK 0x00004000
-#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_GET(x) (((x) & 0x00004000) >> 14)
-#define PHY_ANALOG_RXTX1_PADRVHALFGN2G_SET(x) (((x) << 14) & 0x00004000)
-#define PHY_ANALOG_RXTX1_PADRV2GN_MSB 18
-#define PHY_ANALOG_RXTX1_PADRV2GN_LSB 15
-#define PHY_ANALOG_RXTX1_PADRV2GN_MASK 0x00078000
-#define PHY_ANALOG_RXTX1_PADRV2GN_GET(x) (((x) & 0x00078000) >> 15)
-#define PHY_ANALOG_RXTX1_PADRV2GN_SET(x) (((x) << 15) & 0x00078000)
-#define PHY_ANALOG_RXTX1_PADRV3GN5G_MSB 22
-#define PHY_ANALOG_RXTX1_PADRV3GN5G_LSB 19
-#define PHY_ANALOG_RXTX1_PADRV3GN5G_MASK 0x00780000
-#define PHY_ANALOG_RXTX1_PADRV3GN5G_GET(x) (((x) & 0x00780000) >> 19)
-#define PHY_ANALOG_RXTX1_PADRV3GN5G_SET(x) (((x) << 19) & 0x00780000)
-#define PHY_ANALOG_RXTX1_PADRV4GN5G_MSB 26
-#define PHY_ANALOG_RXTX1_PADRV4GN5G_LSB 23
-#define PHY_ANALOG_RXTX1_PADRV4GN5G_MASK 0x07800000
-#define PHY_ANALOG_RXTX1_PADRV4GN5G_GET(x) (((x) & 0x07800000) >> 23)
-#define PHY_ANALOG_RXTX1_PADRV4GN5G_SET(x) (((x) << 23) & 0x07800000)
-#define PHY_ANALOG_RXTX1_TXBB_GC_MSB 30
-#define PHY_ANALOG_RXTX1_TXBB_GC_LSB 27
-#define PHY_ANALOG_RXTX1_TXBB_GC_MASK 0x78000000
-#define PHY_ANALOG_RXTX1_TXBB_GC_GET(x) (((x) & 0x78000000) >> 27)
-#define PHY_ANALOG_RXTX1_TXBB_GC_SET(x) (((x) << 27) & 0x78000000)
-#define PHY_ANALOG_RXTX1_MANTXGAIN_MSB 31
-#define PHY_ANALOG_RXTX1_MANTXGAIN_LSB 31
-#define PHY_ANALOG_RXTX1_MANTXGAIN_MASK 0x80000000
-#define PHY_ANALOG_RXTX1_MANTXGAIN_GET(x) (((x) & 0x80000000) >> 31)
-#define PHY_ANALOG_RXTX1_MANTXGAIN_SET(x) (((x) << 31) & 0x80000000)
-
-/* macros for RXTX2 */
-#define PHY_ANALOG_RXTX2_ADDRESS 0x00000104
-#define PHY_ANALOG_RXTX2_OFFSET 0x00000104
-#define PHY_ANALOG_RXTX2_BMODE_MSB 0
-#define PHY_ANALOG_RXTX2_BMODE_LSB 0
-#define PHY_ANALOG_RXTX2_BMODE_MASK 0x00000001
-#define PHY_ANALOG_RXTX2_BMODE_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_ANALOG_RXTX2_BMODE_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_ANALOG_RXTX2_BMODE_OVR_MSB 1
-#define PHY_ANALOG_RXTX2_BMODE_OVR_LSB 1
-#define PHY_ANALOG_RXTX2_BMODE_OVR_MASK 0x00000002
-#define PHY_ANALOG_RXTX2_BMODE_OVR_GET(x) (((x) & 0x00000002) >> 1)
-#define PHY_ANALOG_RXTX2_BMODE_OVR_SET(x) (((x) << 1) & 0x00000002)
-#define PHY_ANALOG_RXTX2_SYNTHON_MSB 2
-#define PHY_ANALOG_RXTX2_SYNTHON_LSB 2
-#define PHY_ANALOG_RXTX2_SYNTHON_MASK 0x00000004
-#define PHY_ANALOG_RXTX2_SYNTHON_GET(x) (((x) & 0x00000004) >> 2)
-#define PHY_ANALOG_RXTX2_SYNTHON_SET(x) (((x) << 2) & 0x00000004)
-#define PHY_ANALOG_RXTX2_SYNTHON_OVR_MSB 3
-#define PHY_ANALOG_RXTX2_SYNTHON_OVR_LSB 3
-#define PHY_ANALOG_RXTX2_SYNTHON_OVR_MASK 0x00000008
-#define PHY_ANALOG_RXTX2_SYNTHON_OVR_GET(x) (((x) & 0x00000008) >> 3)
-#define PHY_ANALOG_RXTX2_SYNTHON_OVR_SET(x) (((x) << 3) & 0x00000008)
-#define PHY_ANALOG_RXTX2_BW_ST_MSB 5
-#define PHY_ANALOG_RXTX2_BW_ST_LSB 4
-#define PHY_ANALOG_RXTX2_BW_ST_MASK 0x00000030
-#define PHY_ANALOG_RXTX2_BW_ST_GET(x) (((x) & 0x00000030) >> 4)
-#define PHY_ANALOG_RXTX2_BW_ST_SET(x) (((x) << 4) & 0x00000030)
-#define PHY_ANALOG_RXTX2_BW_ST_OVR_MSB 6
-#define PHY_ANALOG_RXTX2_BW_ST_OVR_LSB 6
-#define PHY_ANALOG_RXTX2_BW_ST_OVR_MASK 0x00000040
-#define PHY_ANALOG_RXTX2_BW_ST_OVR_GET(x) (((x) & 0x00000040) >> 6)
-#define PHY_ANALOG_RXTX2_BW_ST_OVR_SET(x) (((x) << 6) & 0x00000040)
-#define PHY_ANALOG_RXTX2_TXON_MSB 7
-#define PHY_ANALOG_RXTX2_TXON_LSB 7
-#define PHY_ANALOG_RXTX2_TXON_MASK 0x00000080
-#define PHY_ANALOG_RXTX2_TXON_GET(x) (((x) & 0x00000080) >> 7)
-#define PHY_ANALOG_RXTX2_TXON_SET(x) (((x) << 7) & 0x00000080)
-#define PHY_ANALOG_RXTX2_TXON_OVR_MSB 8
-#define PHY_ANALOG_RXTX2_TXON_OVR_LSB 8
-#define PHY_ANALOG_RXTX2_TXON_OVR_MASK 0x00000100
-#define PHY_ANALOG_RXTX2_TXON_OVR_GET(x) (((x) & 0x00000100) >> 8)
-#define PHY_ANALOG_RXTX2_TXON_OVR_SET(x) (((x) << 8) & 0x00000100)
-#define PHY_ANALOG_RXTX2_PAON_MSB 9
-#define PHY_ANALOG_RXTX2_PAON_LSB 9
-#define PHY_ANALOG_RXTX2_PAON_MASK 0x00000200
-#define PHY_ANALOG_RXTX2_PAON_GET(x) (((x) & 0x00000200) >> 9)
-#define PHY_ANALOG_RXTX2_PAON_SET(x) (((x) << 9) & 0x00000200)
-#define PHY_ANALOG_RXTX2_PAON_OVR_MSB 10
-#define PHY_ANALOG_RXTX2_PAON_OVR_LSB 10
-#define PHY_ANALOG_RXTX2_PAON_OVR_MASK 0x00000400
-#define PHY_ANALOG_RXTX2_PAON_OVR_GET(x) (((x) & 0x00000400) >> 10)
-#define PHY_ANALOG_RXTX2_PAON_OVR_SET(x) (((x) << 10) & 0x00000400)
-#define PHY_ANALOG_RXTX2_RXON_MSB 11
-#define PHY_ANALOG_RXTX2_RXON_LSB 11
-#define PHY_ANALOG_RXTX2_RXON_MASK 0x00000800
-#define PHY_ANALOG_RXTX2_RXON_GET(x) (((x) & 0x00000800) >> 11)
-#define PHY_ANALOG_RXTX2_RXON_SET(x) (((x) << 11) & 0x00000800)
-#define PHY_ANALOG_RXTX2_RXON_OVR_MSB 12
-#define PHY_ANALOG_RXTX2_RXON_OVR_LSB 12
-#define PHY_ANALOG_RXTX2_RXON_OVR_MASK 0x00001000
-#define PHY_ANALOG_RXTX2_RXON_OVR_GET(x) (((x) & 0x00001000) >> 12)
-#define PHY_ANALOG_RXTX2_RXON_OVR_SET(x) (((x) << 12) & 0x00001000)
-#define PHY_ANALOG_RXTX2_AGCON_MSB 13
-#define PHY_ANALOG_RXTX2_AGCON_LSB 13
-#define PHY_ANALOG_RXTX2_AGCON_MASK 0x00002000
-#define PHY_ANALOG_RXTX2_AGCON_GET(x) (((x) & 0x00002000) >> 13)
-#define PHY_ANALOG_RXTX2_AGCON_SET(x) (((x) << 13) & 0x00002000)
-#define PHY_ANALOG_RXTX2_AGCON_OVR_MSB 14
-#define PHY_ANALOG_RXTX2_AGCON_OVR_LSB 14
-#define PHY_ANALOG_RXTX2_AGCON_OVR_MASK 0x00004000
-#define PHY_ANALOG_RXTX2_AGCON_OVR_GET(x) (((x) & 0x00004000) >> 14)
-#define PHY_ANALOG_RXTX2_AGCON_OVR_SET(x) (((x) << 14) & 0x00004000)
-#define PHY_ANALOG_RXTX2_TXMOD_MSB 17
-#define PHY_ANALOG_RXTX2_TXMOD_LSB 15
-#define PHY_ANALOG_RXTX2_TXMOD_MASK 0x00038000
-#define PHY_ANALOG_RXTX2_TXMOD_GET(x) (((x) & 0x00038000) >> 15)
-#define PHY_ANALOG_RXTX2_TXMOD_SET(x) (((x) << 15) & 0x00038000)
-#define PHY_ANALOG_RXTX2_TXMOD_OVR_MSB 18
-#define PHY_ANALOG_RXTX2_TXMOD_OVR_LSB 18
-#define PHY_ANALOG_RXTX2_TXMOD_OVR_MASK 0x00040000
-#define PHY_ANALOG_RXTX2_TXMOD_OVR_GET(x) (((x) & 0x00040000) >> 18)
-#define PHY_ANALOG_RXTX2_TXMOD_OVR_SET(x) (((x) << 18) & 0x00040000)
-#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_MSB 21
-#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_LSB 19
-#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_MASK 0x00380000
-#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_GET(x) (((x) & 0x00380000) >> 19)
-#define PHY_ANALOG_RXTX2_RX1DB_BIQUAD_SET(x) (((x) << 19) & 0x00380000)
-#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_MSB 23
-#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_LSB 22
-#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_MASK 0x00c00000
-#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_GET(x) (((x) & 0x00c00000) >> 22)
-#define PHY_ANALOG_RXTX2_RX6DB_BIQUAD_SET(x) (((x) << 22) & 0x00c00000)
-#define PHY_ANALOG_RXTX2_MXRGAIN_MSB 25
-#define PHY_ANALOG_RXTX2_MXRGAIN_LSB 24
-#define PHY_ANALOG_RXTX2_MXRGAIN_MASK 0x03000000
-#define PHY_ANALOG_RXTX2_MXRGAIN_GET(x) (((x) & 0x03000000) >> 24)
-#define PHY_ANALOG_RXTX2_MXRGAIN_SET(x) (((x) << 24) & 0x03000000)
-#define PHY_ANALOG_RXTX2_VGAGAIN_MSB 28
-#define PHY_ANALOG_RXTX2_VGAGAIN_LSB 26
-#define PHY_ANALOG_RXTX2_VGAGAIN_MASK 0x1c000000
-#define PHY_ANALOG_RXTX2_VGAGAIN_GET(x) (((x) & 0x1c000000) >> 26)
-#define PHY_ANALOG_RXTX2_VGAGAIN_SET(x) (((x) << 26) & 0x1c000000)
-#define PHY_ANALOG_RXTX2_LNAGAIN_MSB 31
-#define PHY_ANALOG_RXTX2_LNAGAIN_LSB 29
-#define PHY_ANALOG_RXTX2_LNAGAIN_MASK 0xe0000000
-#define PHY_ANALOG_RXTX2_LNAGAIN_GET(x) (((x) & 0xe0000000) >> 29)
-#define PHY_ANALOG_RXTX2_LNAGAIN_SET(x) (((x) << 29) & 0xe0000000)
-
-/* macros for RXTX3 */
-#define PHY_ANALOG_RXTX3_ADDRESS 0x00000108
-#define PHY_ANALOG_RXTX3_OFFSET 0x00000108
-#define PHY_ANALOG_RXTX3_SPARE3_MSB 2
-#define PHY_ANALOG_RXTX3_SPARE3_LSB 0
-#define PHY_ANALOG_RXTX3_SPARE3_MASK 0x00000007
-#define PHY_ANALOG_RXTX3_SPARE3_GET(x) (((x) & 0x00000007) >> 0)
-#define PHY_ANALOG_RXTX3_SPARE3_SET(x) (((x) << 0) & 0x00000007)
-#define PHY_ANALOG_RXTX3_SPURON_MSB 3
-#define PHY_ANALOG_RXTX3_SPURON_LSB 3
-#define PHY_ANALOG_RXTX3_SPURON_MASK 0x00000008
-#define PHY_ANALOG_RXTX3_SPURON_GET(x) (((x) & 0x00000008) >> 3)
-#define PHY_ANALOG_RXTX3_SPURON_SET(x) (((x) << 3) & 0x00000008)
-#define PHY_ANALOG_RXTX3_PAL_LOCKEDEN_MSB 4
-#define PHY_ANALOG_RXTX3_PAL_LOCKEDEN_LSB 4
-#define PHY_ANALOG_RXTX3_PAL_LOCKEDEN_MASK 0x00000010
-#define PHY_ANALOG_RXTX3_PAL_LOCKEDEN_GET(x) (((x) & 0x00000010) >> 4)
-#define PHY_ANALOG_RXTX3_PAL_LOCKEDEN_SET(x) (((x) << 4) & 0x00000010)
-#define PHY_ANALOG_RXTX3_DACFULLSCALE_MSB 5
-#define PHY_ANALOG_RXTX3_DACFULLSCALE_LSB 5
-#define PHY_ANALOG_RXTX3_DACFULLSCALE_MASK 0x00000020
-#define PHY_ANALOG_RXTX3_DACFULLSCALE_GET(x) (((x) & 0x00000020) >> 5)
-#define PHY_ANALOG_RXTX3_DACFULLSCALE_SET(x) (((x) << 5) & 0x00000020)
-#define PHY_ANALOG_RXTX3_ADCSHORT_MSB 6
-#define PHY_ANALOG_RXTX3_ADCSHORT_LSB 6
-#define PHY_ANALOG_RXTX3_ADCSHORT_MASK 0x00000040
-#define PHY_ANALOG_RXTX3_ADCSHORT_GET(x) (((x) & 0x00000040) >> 6)
-#define PHY_ANALOG_RXTX3_ADCSHORT_SET(x) (((x) << 6) & 0x00000040)
-#define PHY_ANALOG_RXTX3_DACPWD_MSB 7
-#define PHY_ANALOG_RXTX3_DACPWD_LSB 7
-#define PHY_ANALOG_RXTX3_DACPWD_MASK 0x00000080
-#define PHY_ANALOG_RXTX3_DACPWD_GET(x) (((x) & 0x00000080) >> 7)
-#define PHY_ANALOG_RXTX3_DACPWD_SET(x) (((x) << 7) & 0x00000080)
-#define PHY_ANALOG_RXTX3_DACPWD_OVR_MSB 8
-#define PHY_ANALOG_RXTX3_DACPWD_OVR_LSB 8
-#define PHY_ANALOG_RXTX3_DACPWD_OVR_MASK 0x00000100
-#define PHY_ANALOG_RXTX3_DACPWD_OVR_GET(x) (((x) & 0x00000100) >> 8)
-#define PHY_ANALOG_RXTX3_DACPWD_OVR_SET(x) (((x) << 8) & 0x00000100)
-#define PHY_ANALOG_RXTX3_ADCPWD_MSB 9
-#define PHY_ANALOG_RXTX3_ADCPWD_LSB 9
-#define PHY_ANALOG_RXTX3_ADCPWD_MASK 0x00000200
-#define PHY_ANALOG_RXTX3_ADCPWD_GET(x) (((x) & 0x00000200) >> 9)
-#define PHY_ANALOG_RXTX3_ADCPWD_SET(x) (((x) << 9) & 0x00000200)
-#define PHY_ANALOG_RXTX3_ADCPWD_OVR_MSB 10
-#define PHY_ANALOG_RXTX3_ADCPWD_OVR_LSB 10
-#define PHY_ANALOG_RXTX3_ADCPWD_OVR_MASK 0x00000400
-#define PHY_ANALOG_RXTX3_ADCPWD_OVR_GET(x) (((x) & 0x00000400) >> 10)
-#define PHY_ANALOG_RXTX3_ADCPWD_OVR_SET(x) (((x) << 10) & 0x00000400)
-#define PHY_ANALOG_RXTX3_AGC_CALDAC_MSB 16
-#define PHY_ANALOG_RXTX3_AGC_CALDAC_LSB 11
-#define PHY_ANALOG_RXTX3_AGC_CALDAC_MASK 0x0001f800
-#define PHY_ANALOG_RXTX3_AGC_CALDAC_GET(x) (((x) & 0x0001f800) >> 11)
-#define PHY_ANALOG_RXTX3_AGC_CALDAC_SET(x) (((x) << 11) & 0x0001f800)
-#define PHY_ANALOG_RXTX3_AGC_CAL_MSB 17
-#define PHY_ANALOG_RXTX3_AGC_CAL_LSB 17
-#define PHY_ANALOG_RXTX3_AGC_CAL_MASK 0x00020000
-#define PHY_ANALOG_RXTX3_AGC_CAL_GET(x) (((x) & 0x00020000) >> 17)
-#define PHY_ANALOG_RXTX3_AGC_CAL_SET(x) (((x) << 17) & 0x00020000)
-#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_MSB 18
-#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_LSB 18
-#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_MASK 0x00040000
-#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_GET(x) (((x) & 0x00040000) >> 18)
-#define PHY_ANALOG_RXTX3_AGC_CAL_OVR_SET(x) (((x) << 18) & 0x00040000)
-#define PHY_ANALOG_RXTX3_LOFORCEDON_MSB 19
-#define PHY_ANALOG_RXTX3_LOFORCEDON_LSB 19
-#define PHY_ANALOG_RXTX3_LOFORCEDON_MASK 0x00080000
-#define PHY_ANALOG_RXTX3_LOFORCEDON_GET(x) (((x) & 0x00080000) >> 19)
-#define PHY_ANALOG_RXTX3_LOFORCEDON_SET(x) (((x) << 19) & 0x00080000)
-#define PHY_ANALOG_RXTX3_CALRESIDUE_MSB 20
-#define PHY_ANALOG_RXTX3_CALRESIDUE_LSB 20
-#define PHY_ANALOG_RXTX3_CALRESIDUE_MASK 0x00100000
-#define PHY_ANALOG_RXTX3_CALRESIDUE_GET(x) (((x) & 0x00100000) >> 20)
-#define PHY_ANALOG_RXTX3_CALRESIDUE_SET(x) (((x) << 20) & 0x00100000)
-#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_MSB 21
-#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_LSB 21
-#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_MASK 0x00200000
-#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_GET(x) (((x) & 0x00200000) >> 21)
-#define PHY_ANALOG_RXTX3_CALRESIDUE_OVR_SET(x) (((x) << 21) & 0x00200000)
-#define PHY_ANALOG_RXTX3_CALFC_MSB 22
-#define PHY_ANALOG_RXTX3_CALFC_LSB 22
-#define PHY_ANALOG_RXTX3_CALFC_MASK 0x00400000
-#define PHY_ANALOG_RXTX3_CALFC_GET(x) (((x) & 0x00400000) >> 22)
-#define PHY_ANALOG_RXTX3_CALFC_SET(x) (((x) << 22) & 0x00400000)
-#define PHY_ANALOG_RXTX3_CALFC_OVR_MSB 23
-#define PHY_ANALOG_RXTX3_CALFC_OVR_LSB 23
-#define PHY_ANALOG_RXTX3_CALFC_OVR_MASK 0x00800000
-#define PHY_ANALOG_RXTX3_CALFC_OVR_GET(x) (((x) & 0x00800000) >> 23)
-#define PHY_ANALOG_RXTX3_CALFC_OVR_SET(x) (((x) << 23) & 0x00800000)
-#define PHY_ANALOG_RXTX3_CALTX_MSB 24
-#define PHY_ANALOG_RXTX3_CALTX_LSB 24
-#define PHY_ANALOG_RXTX3_CALTX_MASK 0x01000000
-#define PHY_ANALOG_RXTX3_CALTX_GET(x) (((x) & 0x01000000) >> 24)
-#define PHY_ANALOG_RXTX3_CALTX_SET(x) (((x) << 24) & 0x01000000)
-#define PHY_ANALOG_RXTX3_CALTX_OVR_MSB 25
-#define PHY_ANALOG_RXTX3_CALTX_OVR_LSB 25
-#define PHY_ANALOG_RXTX3_CALTX_OVR_MASK 0x02000000
-#define PHY_ANALOG_RXTX3_CALTX_OVR_GET(x) (((x) & 0x02000000) >> 25)
-#define PHY_ANALOG_RXTX3_CALTX_OVR_SET(x) (((x) << 25) & 0x02000000)
-#define PHY_ANALOG_RXTX3_CALTXSHIFT_MSB 26
-#define PHY_ANALOG_RXTX3_CALTXSHIFT_LSB 26
-#define PHY_ANALOG_RXTX3_CALTXSHIFT_MASK 0x04000000
-#define PHY_ANALOG_RXTX3_CALTXSHIFT_GET(x) (((x) & 0x04000000) >> 26)
-#define PHY_ANALOG_RXTX3_CALTXSHIFT_SET(x) (((x) << 26) & 0x04000000)
-#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_MSB 27
-#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_LSB 27
-#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_MASK 0x08000000
-#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_GET(x) (((x) & 0x08000000) >> 27)
-#define PHY_ANALOG_RXTX3_CALTXSHIFT_OVR_SET(x) (((x) << 27) & 0x08000000)
-#define PHY_ANALOG_RXTX3_CALPA_MSB 28
-#define PHY_ANALOG_RXTX3_CALPA_LSB 28
-#define PHY_ANALOG_RXTX3_CALPA_MASK 0x10000000
-#define PHY_ANALOG_RXTX3_CALPA_GET(x) (((x) & 0x10000000) >> 28)
-#define PHY_ANALOG_RXTX3_CALPA_SET(x) (((x) << 28) & 0x10000000)
-#define PHY_ANALOG_RXTX3_CALPA_OVR_MSB 29
-#define PHY_ANALOG_RXTX3_CALPA_OVR_LSB 29
-#define PHY_ANALOG_RXTX3_CALPA_OVR_MASK 0x20000000
-#define PHY_ANALOG_RXTX3_CALPA_OVR_GET(x) (((x) & 0x20000000) >> 29)
-#define PHY_ANALOG_RXTX3_CALPA_OVR_SET(x) (((x) << 29) & 0x20000000)
-#define PHY_ANALOG_RXTX3_TURBOADC_MSB 30
-#define PHY_ANALOG_RXTX3_TURBOADC_LSB 30
-#define PHY_ANALOG_RXTX3_TURBOADC_MASK 0x40000000
-#define PHY_ANALOG_RXTX3_TURBOADC_GET(x) (((x) & 0x40000000) >> 30)
-#define PHY_ANALOG_RXTX3_TURBOADC_SET(x) (((x) << 30) & 0x40000000)
-#define PHY_ANALOG_RXTX3_TURBOADC_OVR_MSB 31
-#define PHY_ANALOG_RXTX3_TURBOADC_OVR_LSB 31
-#define PHY_ANALOG_RXTX3_TURBOADC_OVR_MASK 0x80000000
-#define PHY_ANALOG_RXTX3_TURBOADC_OVR_GET(x) (((x) & 0x80000000) >> 31)
-#define PHY_ANALOG_RXTX3_TURBOADC_OVR_SET(x) (((x) << 31) & 0x80000000)
-
-/* macros for BB1 */
-#define PHY_ANALOG_BB1_ADDRESS 0x00000140
-#define PHY_ANALOG_BB1_OFFSET 0x00000140
-#define PHY_ANALOG_BB1_I2V_CURR2X_MSB 0
-#define PHY_ANALOG_BB1_I2V_CURR2X_LSB 0
-#define PHY_ANALOG_BB1_I2V_CURR2X_MASK 0x00000001
-#define PHY_ANALOG_BB1_I2V_CURR2X_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_ANALOG_BB1_I2V_CURR2X_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_ANALOG_BB1_ENABLE_LOQ_MSB 1
-#define PHY_ANALOG_BB1_ENABLE_LOQ_LSB 1
-#define PHY_ANALOG_BB1_ENABLE_LOQ_MASK 0x00000002
-#define PHY_ANALOG_BB1_ENABLE_LOQ_GET(x) (((x) & 0x00000002) >> 1)
-#define PHY_ANALOG_BB1_ENABLE_LOQ_SET(x) (((x) << 1) & 0x00000002)
-#define PHY_ANALOG_BB1_FORCE_LOQ_MSB 2
-#define PHY_ANALOG_BB1_FORCE_LOQ_LSB 2
-#define PHY_ANALOG_BB1_FORCE_LOQ_MASK 0x00000004
-#define PHY_ANALOG_BB1_FORCE_LOQ_GET(x) (((x) & 0x00000004) >> 2)
-#define PHY_ANALOG_BB1_FORCE_LOQ_SET(x) (((x) << 2) & 0x00000004)
-#define PHY_ANALOG_BB1_ENABLE_NOTCH_MSB 3
-#define PHY_ANALOG_BB1_ENABLE_NOTCH_LSB 3
-#define PHY_ANALOG_BB1_ENABLE_NOTCH_MASK 0x00000008
-#define PHY_ANALOG_BB1_ENABLE_NOTCH_GET(x) (((x) & 0x00000008) >> 3)
-#define PHY_ANALOG_BB1_ENABLE_NOTCH_SET(x) (((x) << 3) & 0x00000008)
-#define PHY_ANALOG_BB1_FORCE_NOTCH_MSB 4
-#define PHY_ANALOG_BB1_FORCE_NOTCH_LSB 4
-#define PHY_ANALOG_BB1_FORCE_NOTCH_MASK 0x00000010
-#define PHY_ANALOG_BB1_FORCE_NOTCH_GET(x) (((x) & 0x00000010) >> 4)
-#define PHY_ANALOG_BB1_FORCE_NOTCH_SET(x) (((x) << 4) & 0x00000010)
-#define PHY_ANALOG_BB1_ENABLE_BIQUAD_MSB 5
-#define PHY_ANALOG_BB1_ENABLE_BIQUAD_LSB 5
-#define PHY_ANALOG_BB1_ENABLE_BIQUAD_MASK 0x00000020
-#define PHY_ANALOG_BB1_ENABLE_BIQUAD_GET(x) (((x) & 0x00000020) >> 5)
-#define PHY_ANALOG_BB1_ENABLE_BIQUAD_SET(x) (((x) << 5) & 0x00000020)
-#define PHY_ANALOG_BB1_FORCE_BIQUAD_MSB 6
-#define PHY_ANALOG_BB1_FORCE_BIQUAD_LSB 6
-#define PHY_ANALOG_BB1_FORCE_BIQUAD_MASK 0x00000040
-#define PHY_ANALOG_BB1_FORCE_BIQUAD_GET(x) (((x) & 0x00000040) >> 6)
-#define PHY_ANALOG_BB1_FORCE_BIQUAD_SET(x) (((x) << 6) & 0x00000040)
-#define PHY_ANALOG_BB1_ENABLE_OSDAC_MSB 7
-#define PHY_ANALOG_BB1_ENABLE_OSDAC_LSB 7
-#define PHY_ANALOG_BB1_ENABLE_OSDAC_MASK 0x00000080
-#define PHY_ANALOG_BB1_ENABLE_OSDAC_GET(x) (((x) & 0x00000080) >> 7)
-#define PHY_ANALOG_BB1_ENABLE_OSDAC_SET(x) (((x) << 7) & 0x00000080)
-#define PHY_ANALOG_BB1_FORCE_OSDAC_MSB 8
-#define PHY_ANALOG_BB1_FORCE_OSDAC_LSB 8
-#define PHY_ANALOG_BB1_FORCE_OSDAC_MASK 0x00000100
-#define PHY_ANALOG_BB1_FORCE_OSDAC_GET(x) (((x) & 0x00000100) >> 8)
-#define PHY_ANALOG_BB1_FORCE_OSDAC_SET(x) (((x) << 8) & 0x00000100)
-#define PHY_ANALOG_BB1_ENABLE_V2I_MSB 9
-#define PHY_ANALOG_BB1_ENABLE_V2I_LSB 9
-#define PHY_ANALOG_BB1_ENABLE_V2I_MASK 0x00000200
-#define PHY_ANALOG_BB1_ENABLE_V2I_GET(x) (((x) & 0x00000200) >> 9)
-#define PHY_ANALOG_BB1_ENABLE_V2I_SET(x) (((x) << 9) & 0x00000200)
-#define PHY_ANALOG_BB1_FORCE_V2I_MSB 10
-#define PHY_ANALOG_BB1_FORCE_V2I_LSB 10
-#define PHY_ANALOG_BB1_FORCE_V2I_MASK 0x00000400
-#define PHY_ANALOG_BB1_FORCE_V2I_GET(x) (((x) & 0x00000400) >> 10)
-#define PHY_ANALOG_BB1_FORCE_V2I_SET(x) (((x) << 10) & 0x00000400)
-#define PHY_ANALOG_BB1_ENABLE_I2V_MSB 11
-#define PHY_ANALOG_BB1_ENABLE_I2V_LSB 11
-#define PHY_ANALOG_BB1_ENABLE_I2V_MASK 0x00000800
-#define PHY_ANALOG_BB1_ENABLE_I2V_GET(x) (((x) & 0x00000800) >> 11)
-#define PHY_ANALOG_BB1_ENABLE_I2V_SET(x) (((x) << 11) & 0x00000800)
-#define PHY_ANALOG_BB1_FORCE_I2V_MSB 12
-#define PHY_ANALOG_BB1_FORCE_I2V_LSB 12
-#define PHY_ANALOG_BB1_FORCE_I2V_MASK 0x00001000
-#define PHY_ANALOG_BB1_FORCE_I2V_GET(x) (((x) & 0x00001000) >> 12)
-#define PHY_ANALOG_BB1_FORCE_I2V_SET(x) (((x) << 12) & 0x00001000)
-#define PHY_ANALOG_BB1_CMSEL_MSB 15
-#define PHY_ANALOG_BB1_CMSEL_LSB 13
-#define PHY_ANALOG_BB1_CMSEL_MASK 0x0000e000
-#define PHY_ANALOG_BB1_CMSEL_GET(x) (((x) & 0x0000e000) >> 13)
-#define PHY_ANALOG_BB1_CMSEL_SET(x) (((x) << 13) & 0x0000e000)
-#define PHY_ANALOG_BB1_ATBSEL_MSB 17
-#define PHY_ANALOG_BB1_ATBSEL_LSB 16
-#define PHY_ANALOG_BB1_ATBSEL_MASK 0x00030000
-#define PHY_ANALOG_BB1_ATBSEL_GET(x) (((x) & 0x00030000) >> 16)
-#define PHY_ANALOG_BB1_ATBSEL_SET(x) (((x) << 16) & 0x00030000)
-#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_MSB 18
-#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_LSB 18
-#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_MASK 0x00040000
-#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_GET(x) (((x) & 0x00040000) >> 18)
-#define PHY_ANALOG_BB1_PD_OSDAC_CALTX_CALPA_SET(x) (((x) << 18) & 0x00040000)
-#define PHY_ANALOG_BB1_OFSTCORRI2VQ_MSB 23
-#define PHY_ANALOG_BB1_OFSTCORRI2VQ_LSB 19
-#define PHY_ANALOG_BB1_OFSTCORRI2VQ_MASK 0x00f80000
-#define PHY_ANALOG_BB1_OFSTCORRI2VQ_GET(x) (((x) & 0x00f80000) >> 19)
-#define PHY_ANALOG_BB1_OFSTCORRI2VQ_SET(x) (((x) << 19) & 0x00f80000)
-#define PHY_ANALOG_BB1_OFSTCORRI2VI_MSB 28
-#define PHY_ANALOG_BB1_OFSTCORRI2VI_LSB 24
-#define PHY_ANALOG_BB1_OFSTCORRI2VI_MASK 0x1f000000
-#define PHY_ANALOG_BB1_OFSTCORRI2VI_GET(x) (((x) & 0x1f000000) >> 24)
-#define PHY_ANALOG_BB1_OFSTCORRI2VI_SET(x) (((x) << 24) & 0x1f000000)
-#define PHY_ANALOG_BB1_LOCALOFFSET_MSB 29
-#define PHY_ANALOG_BB1_LOCALOFFSET_LSB 29
-#define PHY_ANALOG_BB1_LOCALOFFSET_MASK 0x20000000
-#define PHY_ANALOG_BB1_LOCALOFFSET_GET(x) (((x) & 0x20000000) >> 29)
-#define PHY_ANALOG_BB1_LOCALOFFSET_SET(x) (((x) << 29) & 0x20000000)
-#define PHY_ANALOG_BB1_RANGE_OSDAC_MSB 31
-#define PHY_ANALOG_BB1_RANGE_OSDAC_LSB 30
-#define PHY_ANALOG_BB1_RANGE_OSDAC_MASK 0xc0000000
-#define PHY_ANALOG_BB1_RANGE_OSDAC_GET(x) (((x) & 0xc0000000) >> 30)
-#define PHY_ANALOG_BB1_RANGE_OSDAC_SET(x) (((x) << 30) & 0xc0000000)
-
-/* macros for BB2 */
-#define PHY_ANALOG_BB2_ADDRESS 0x00000144
-#define PHY_ANALOG_BB2_OFFSET 0x00000144
-#define PHY_ANALOG_BB2_SPARE_MSB 3
-#define PHY_ANALOG_BB2_SPARE_LSB 0
-#define PHY_ANALOG_BB2_SPARE_MASK 0x0000000f
-#define PHY_ANALOG_BB2_SPARE_GET(x) (((x) & 0x0000000f) >> 0)
-#define PHY_ANALOG_BB2_SPARE_SET(x) (((x) << 0) & 0x0000000f)
-#define PHY_ANALOG_BB2_MXR_HIGHGAINMASK_MSB 7
-#define PHY_ANALOG_BB2_MXR_HIGHGAINMASK_LSB 4
-#define PHY_ANALOG_BB2_MXR_HIGHGAINMASK_MASK 0x000000f0
-#define PHY_ANALOG_BB2_MXR_HIGHGAINMASK_GET(x) (((x) & 0x000000f0) >> 4)
-#define PHY_ANALOG_BB2_MXR_HIGHGAINMASK_SET(x) (((x) << 4) & 0x000000f0)
-#define PHY_ANALOG_BB2_SEL_TEST_MSB 9
-#define PHY_ANALOG_BB2_SEL_TEST_LSB 8
-#define PHY_ANALOG_BB2_SEL_TEST_MASK 0x00000300
-#define PHY_ANALOG_BB2_SEL_TEST_GET(x) (((x) & 0x00000300) >> 8)
-#define PHY_ANALOG_BB2_SEL_TEST_SET(x) (((x) << 8) & 0x00000300)
-#define PHY_ANALOG_BB2_RCFILTER_CAP_MSB 14
-#define PHY_ANALOG_BB2_RCFILTER_CAP_LSB 10
-#define PHY_ANALOG_BB2_RCFILTER_CAP_MASK 0x00007c00
-#define PHY_ANALOG_BB2_RCFILTER_CAP_GET(x) (((x) & 0x00007c00) >> 10)
-#define PHY_ANALOG_BB2_RCFILTER_CAP_SET(x) (((x) << 10) & 0x00007c00)
-#define PHY_ANALOG_BB2_OVERRIDE_RCFILTER_CAP_MSB 15
-#define PHY_ANALOG_BB2_OVERRIDE_RCFILTER_CAP_LSB 15
-#define PHY_ANALOG_BB2_OVERRIDE_RCFILTER_CAP_MASK 0x00008000
-#define PHY_ANALOG_BB2_OVERRIDE_RCFILTER_CAP_GET(x) (((x) & 0x00008000) >> 15)
-#define PHY_ANALOG_BB2_OVERRIDE_RCFILTER_CAP_SET(x) (((x) << 15) & 0x00008000)
-#define PHY_ANALOG_BB2_FNOTCH_MSB 19
-#define PHY_ANALOG_BB2_FNOTCH_LSB 16
-#define PHY_ANALOG_BB2_FNOTCH_MASK 0x000f0000
-#define PHY_ANALOG_BB2_FNOTCH_GET(x) (((x) & 0x000f0000) >> 16)
-#define PHY_ANALOG_BB2_FNOTCH_SET(x) (((x) << 16) & 0x000f0000)
-#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_MSB 20
-#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_LSB 20
-#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_MASK 0x00100000
-#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_GET(x) (((x) & 0x00100000) >> 20)
-#define PHY_ANALOG_BB2_OVERRIDE_FNOTCH_SET(x) (((x) << 20) & 0x00100000)
-#define PHY_ANALOG_BB2_FILTERFC_MSB 25
-#define PHY_ANALOG_BB2_FILTERFC_LSB 21
-#define PHY_ANALOG_BB2_FILTERFC_MASK 0x03e00000
-#define PHY_ANALOG_BB2_FILTERFC_GET(x) (((x) & 0x03e00000) >> 21)
-#define PHY_ANALOG_BB2_FILTERFC_SET(x) (((x) << 21) & 0x03e00000)
-#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_MSB 26
-#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_LSB 26
-#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_MASK 0x04000000
-#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_GET(x) (((x) & 0x04000000) >> 26)
-#define PHY_ANALOG_BB2_OVERRIDE_FILTERFC_SET(x) (((x) << 26) & 0x04000000)
-#define PHY_ANALOG_BB2_I2V2RXOUT_EN_MSB 27
-#define PHY_ANALOG_BB2_I2V2RXOUT_EN_LSB 27
-#define PHY_ANALOG_BB2_I2V2RXOUT_EN_MASK 0x08000000
-#define PHY_ANALOG_BB2_I2V2RXOUT_EN_GET(x) (((x) & 0x08000000) >> 27)
-#define PHY_ANALOG_BB2_I2V2RXOUT_EN_SET(x) (((x) << 27) & 0x08000000)
-#define PHY_ANALOG_BB2_BQ2RXOUT_EN_MSB 28
-#define PHY_ANALOG_BB2_BQ2RXOUT_EN_LSB 28
-#define PHY_ANALOG_BB2_BQ2RXOUT_EN_MASK 0x10000000
-#define PHY_ANALOG_BB2_BQ2RXOUT_EN_GET(x) (((x) & 0x10000000) >> 28)
-#define PHY_ANALOG_BB2_BQ2RXOUT_EN_SET(x) (((x) << 28) & 0x10000000)
-#define PHY_ANALOG_BB2_RXIN2I2V_EN_MSB 29
-#define PHY_ANALOG_BB2_RXIN2I2V_EN_LSB 29
-#define PHY_ANALOG_BB2_RXIN2I2V_EN_MASK 0x20000000
-#define PHY_ANALOG_BB2_RXIN2I2V_EN_GET(x) (((x) & 0x20000000) >> 29)
-#define PHY_ANALOG_BB2_RXIN2I2V_EN_SET(x) (((x) << 29) & 0x20000000)
-#define PHY_ANALOG_BB2_RXIN2BQ_EN_MSB 30
-#define PHY_ANALOG_BB2_RXIN2BQ_EN_LSB 30
-#define PHY_ANALOG_BB2_RXIN2BQ_EN_MASK 0x40000000
-#define PHY_ANALOG_BB2_RXIN2BQ_EN_GET(x) (((x) & 0x40000000) >> 30)
-#define PHY_ANALOG_BB2_RXIN2BQ_EN_SET(x) (((x) << 30) & 0x40000000)
-#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_MSB 31
-#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_LSB 31
-#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_MASK 0x80000000
-#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_GET(x) (((x) & 0x80000000) >> 31)
-#define PHY_ANALOG_BB2_SWITCH_OVERRIDE_SET(x) (((x) << 31) & 0x80000000)
-
-/* macros for BB3 */
-#define PHY_ANALOG_BB3_ADDRESS 0x00000148
-#define PHY_ANALOG_BB3_OFFSET 0x00000148
-#define PHY_ANALOG_BB3_SPARE_MSB 15
-#define PHY_ANALOG_BB3_SPARE_LSB 0
-#define PHY_ANALOG_BB3_SPARE_MASK 0x0000ffff
-#define PHY_ANALOG_BB3_SPARE_GET(x) (((x) & 0x0000ffff) >> 0)
-#define PHY_ANALOG_BB3_SPARE_SET(x) (((x) << 0) & 0x0000ffff)
-#define PHY_ANALOG_BB3_FILTERFC_MSB 20
-#define PHY_ANALOG_BB3_FILTERFC_LSB 16
-#define PHY_ANALOG_BB3_FILTERFC_MASK 0x001f0000
-#define PHY_ANALOG_BB3_FILTERFC_GET(x) (((x) & 0x001f0000) >> 16)
-#define PHY_ANALOG_BB3_OFSTCORRI2VQ_MSB 25
-#define PHY_ANALOG_BB3_OFSTCORRI2VQ_LSB 21
-#define PHY_ANALOG_BB3_OFSTCORRI2VQ_MASK 0x03e00000
-#define PHY_ANALOG_BB3_OFSTCORRI2VQ_GET(x) (((x) & 0x03e00000) >> 21)
-#define PHY_ANALOG_BB3_OFSTCORRI2VI_MSB 30
-#define PHY_ANALOG_BB3_OFSTCORRI2VI_LSB 26
-#define PHY_ANALOG_BB3_OFSTCORRI2VI_MASK 0x7c000000
-#define PHY_ANALOG_BB3_OFSTCORRI2VI_GET(x) (((x) & 0x7c000000) >> 26)
-#define PHY_ANALOG_BB3_EN_TXBBCONSTCUR_MSB 31
-#define PHY_ANALOG_BB3_EN_TXBBCONSTCUR_LSB 31
-#define PHY_ANALOG_BB3_EN_TXBBCONSTCUR_MASK 0x80000000
-#define PHY_ANALOG_BB3_EN_TXBBCONSTCUR_GET(x) (((x) & 0x80000000) >> 31)
-#define PHY_ANALOG_BB3_EN_TXBBCONSTCUR_SET(x) (((x) << 31) & 0x80000000)
-
-/* macros for PLLCLKMODA */
-#define PHY_ANALOG_PLLCLKMODA_ADDRESS 0x00000280
-#define PHY_ANALOG_PLLCLKMODA_OFFSET 0x00000280
-#define PHY_ANALOG_PLLCLKMODA_PWD_PLLSDM_MSB 0
-#define PHY_ANALOG_PLLCLKMODA_PWD_PLLSDM_LSB 0
-#define PHY_ANALOG_PLLCLKMODA_PWD_PLLSDM_MASK 0x00000001
-#define PHY_ANALOG_PLLCLKMODA_PWD_PLLSDM_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_ANALOG_PLLCLKMODA_PWD_PLLSDM_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_ANALOG_PLLCLKMODA_PWDPLL_MSB 1
-#define PHY_ANALOG_PLLCLKMODA_PWDPLL_LSB 1
-#define PHY_ANALOG_PLLCLKMODA_PWDPLL_MASK 0x00000002
-#define PHY_ANALOG_PLLCLKMODA_PWDPLL_GET(x) (((x) & 0x00000002) >> 1)
-#define PHY_ANALOG_PLLCLKMODA_PWDPLL_SET(x) (((x) << 1) & 0x00000002)
-#define PHY_ANALOG_PLLCLKMODA_PLLFRAC_MSB 16
-#define PHY_ANALOG_PLLCLKMODA_PLLFRAC_LSB 2
-#define PHY_ANALOG_PLLCLKMODA_PLLFRAC_MASK 0x0001fffc
-#define PHY_ANALOG_PLLCLKMODA_PLLFRAC_GET(x) (((x) & 0x0001fffc) >> 2)
-#define PHY_ANALOG_PLLCLKMODA_PLLFRAC_SET(x) (((x) << 2) & 0x0001fffc)
-#define PHY_ANALOG_PLLCLKMODA_REFDIV_MSB 20
-#define PHY_ANALOG_PLLCLKMODA_REFDIV_LSB 17
-#define PHY_ANALOG_PLLCLKMODA_REFDIV_MASK 0x001e0000
-#define PHY_ANALOG_PLLCLKMODA_REFDIV_GET(x) (((x) & 0x001e0000) >> 17)
-#define PHY_ANALOG_PLLCLKMODA_REFDIV_SET(x) (((x) << 17) & 0x001e0000)
-#define PHY_ANALOG_PLLCLKMODA_DIV_MSB 30
-#define PHY_ANALOG_PLLCLKMODA_DIV_LSB 21
-#define PHY_ANALOG_PLLCLKMODA_DIV_MASK 0x7fe00000
-#define PHY_ANALOG_PLLCLKMODA_DIV_GET(x) (((x) & 0x7fe00000) >> 21)
-#define PHY_ANALOG_PLLCLKMODA_DIV_SET(x) (((x) << 21) & 0x7fe00000)
-#define PHY_ANALOG_PLLCLKMODA_LOCAL_PLL_MSB 31
-#define PHY_ANALOG_PLLCLKMODA_LOCAL_PLL_LSB 31
-#define PHY_ANALOG_PLLCLKMODA_LOCAL_PLL_MASK 0x80000000
-#define PHY_ANALOG_PLLCLKMODA_LOCAL_PLL_GET(x) (((x) & 0x80000000) >> 31)
-#define PHY_ANALOG_PLLCLKMODA_LOCAL_PLL_SET(x) (((x) << 31) & 0x80000000)
-
-/* macros for PLLCLKMODA2 */
-#define PHY_ANALOG_PLLCLKMODA2_ADDRESS 0x00000284
-#define PHY_ANALOG_PLLCLKMODA2_OFFSET 0x00000284
-#define PHY_ANALOG_PLLCLKMODA2_SPARE_MSB 3
-#define PHY_ANALOG_PLLCLKMODA2_SPARE_LSB 0
-#define PHY_ANALOG_PLLCLKMODA2_SPARE_MASK 0x0000000f
-#define PHY_ANALOG_PLLCLKMODA2_SPARE_GET(x) (((x) & 0x0000000f) >> 0)
-#define PHY_ANALOG_PLLCLKMODA2_SPARE_SET(x) (((x) << 0) & 0x0000000f)
-#define PHY_ANALOG_PLLCLKMODA2_DACPWD_MSB 4
-#define PHY_ANALOG_PLLCLKMODA2_DACPWD_LSB 4
-#define PHY_ANALOG_PLLCLKMODA2_DACPWD_MASK 0x00000010
-#define PHY_ANALOG_PLLCLKMODA2_DACPWD_GET(x) (((x) & 0x00000010) >> 4)
-#define PHY_ANALOG_PLLCLKMODA2_DACPWD_SET(x) (((x) << 4) & 0x00000010)
-#define PHY_ANALOG_PLLCLKMODA2_ADCPWD_MSB 5
-#define PHY_ANALOG_PLLCLKMODA2_ADCPWD_LSB 5
-#define PHY_ANALOG_PLLCLKMODA2_ADCPWD_MASK 0x00000020
-#define PHY_ANALOG_PLLCLKMODA2_ADCPWD_GET(x) (((x) & 0x00000020) >> 5)
-#define PHY_ANALOG_PLLCLKMODA2_ADCPWD_SET(x) (((x) << 5) & 0x00000020)
-#define PHY_ANALOG_PLLCLKMODA2_LOCAL_ADDAC_MSB 6
-#define PHY_ANALOG_PLLCLKMODA2_LOCAL_ADDAC_LSB 6
-#define PHY_ANALOG_PLLCLKMODA2_LOCAL_ADDAC_MASK 0x00000040
-#define PHY_ANALOG_PLLCLKMODA2_LOCAL_ADDAC_GET(x) (((x) & 0x00000040) >> 6)
-#define PHY_ANALOG_PLLCLKMODA2_LOCAL_ADDAC_SET(x) (((x) << 6) & 0x00000040)
-#define PHY_ANALOG_PLLCLKMODA2_DAC_CLK_SEL_MSB 8
-#define PHY_ANALOG_PLLCLKMODA2_DAC_CLK_SEL_LSB 7
-#define PHY_ANALOG_PLLCLKMODA2_DAC_CLK_SEL_MASK 0x00000180
-#define PHY_ANALOG_PLLCLKMODA2_DAC_CLK_SEL_GET(x) (((x) & 0x00000180) >> 7)
-#define PHY_ANALOG_PLLCLKMODA2_DAC_CLK_SEL_SET(x) (((x) << 7) & 0x00000180)
-#define PHY_ANALOG_PLLCLKMODA2_ADC_CLK_SEL_MSB 12
-#define PHY_ANALOG_PLLCLKMODA2_ADC_CLK_SEL_LSB 9
-#define PHY_ANALOG_PLLCLKMODA2_ADC_CLK_SEL_MASK 0x00001e00
-#define PHY_ANALOG_PLLCLKMODA2_ADC_CLK_SEL_GET(x) (((x) & 0x00001e00) >> 9)
-#define PHY_ANALOG_PLLCLKMODA2_ADC_CLK_SEL_SET(x) (((x) << 9) & 0x00001e00)
-#define PHY_ANALOG_PLLCLKMODA2_LOCAL_CLKMODA_MSB 13
-#define PHY_ANALOG_PLLCLKMODA2_LOCAL_CLKMODA_LSB 13
-#define PHY_ANALOG_PLLCLKMODA2_LOCAL_CLKMODA_MASK 0x00002000
-#define PHY_ANALOG_PLLCLKMODA2_LOCAL_CLKMODA_GET(x) (((x) & 0x00002000) >> 13)
-#define PHY_ANALOG_PLLCLKMODA2_LOCAL_CLKMODA_SET(x) (((x) << 13) & 0x00002000)
-#define PHY_ANALOG_PLLCLKMODA2_PLLBYPASS_MSB 14
-#define PHY_ANALOG_PLLCLKMODA2_PLLBYPASS_LSB 14
-#define PHY_ANALOG_PLLCLKMODA2_PLLBYPASS_MASK 0x00004000
-#define PHY_ANALOG_PLLCLKMODA2_PLLBYPASS_GET(x) (((x) & 0x00004000) >> 14)
-#define PHY_ANALOG_PLLCLKMODA2_PLLBYPASS_SET(x) (((x) << 14) & 0x00004000)
-#define PHY_ANALOG_PLLCLKMODA2_LOCAL_PLLBYPASS_MSB 15
-#define PHY_ANALOG_PLLCLKMODA2_LOCAL_PLLBYPASS_LSB 15
-#define PHY_ANALOG_PLLCLKMODA2_LOCAL_PLLBYPASS_MASK 0x00008000
-#define PHY_ANALOG_PLLCLKMODA2_LOCAL_PLLBYPASS_GET(x) (((x) & 0x00008000) >> 15)
-#define PHY_ANALOG_PLLCLKMODA2_LOCAL_PLLBYPASS_SET(x) (((x) << 15) & 0x00008000)
-#define PHY_ANALOG_PLLCLKMODA2_PLLATB_MSB 17
-#define PHY_ANALOG_PLLCLKMODA2_PLLATB_LSB 16
-#define PHY_ANALOG_PLLCLKMODA2_PLLATB_MASK 0x00030000
-#define PHY_ANALOG_PLLCLKMODA2_PLLATB_GET(x) (((x) & 0x00030000) >> 16)
-#define PHY_ANALOG_PLLCLKMODA2_PLLATB_SET(x) (((x) << 16) & 0x00030000)
-#define PHY_ANALOG_PLLCLKMODA2_PLL_SVREG_MSB 18
-#define PHY_ANALOG_PLLCLKMODA2_PLL_SVREG_LSB 18
-#define PHY_ANALOG_PLLCLKMODA2_PLL_SVREG_MASK 0x00040000
-#define PHY_ANALOG_PLLCLKMODA2_PLL_SVREG_GET(x) (((x) & 0x00040000) >> 18)
-#define PHY_ANALOG_PLLCLKMODA2_PLL_SVREG_SET(x) (((x) << 18) & 0x00040000)
-#define PHY_ANALOG_PLLCLKMODA2_HI_FREQ_EN_MSB 19
-#define PHY_ANALOG_PLLCLKMODA2_HI_FREQ_EN_LSB 19
-#define PHY_ANALOG_PLLCLKMODA2_HI_FREQ_EN_MASK 0x00080000
-#define PHY_ANALOG_PLLCLKMODA2_HI_FREQ_EN_GET(x) (((x) & 0x00080000) >> 19)
-#define PHY_ANALOG_PLLCLKMODA2_HI_FREQ_EN_SET(x) (((x) << 19) & 0x00080000)
-#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_INT_L_MSB 20
-#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_INT_L_LSB 20
-#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_INT_L_MASK 0x00100000
-#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_INT_L_GET(x) (((x) & 0x00100000) >> 20)
-#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_INT_L_SET(x) (((x) << 20) & 0x00100000)
-#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_OVR_MSB 21
-#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_OVR_LSB 21
-#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_OVR_MASK 0x00200000
-#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_OVR_GET(x) (((x) & 0x00200000) >> 21)
-#define PHY_ANALOG_PLLCLKMODA2_RST_WARM_OVR_SET(x) (((x) << 21) & 0x00200000)
-#define PHY_ANALOG_PLLCLKMODA2_PLL_KVCO_MSB 23
-#define PHY_ANALOG_PLLCLKMODA2_PLL_KVCO_LSB 22
-#define PHY_ANALOG_PLLCLKMODA2_PLL_KVCO_MASK 0x00c00000
-#define PHY_ANALOG_PLLCLKMODA2_PLL_KVCO_GET(x) (((x) & 0x00c00000) >> 22)
-#define PHY_ANALOG_PLLCLKMODA2_PLL_KVCO_SET(x) (((x) << 22) & 0x00c00000)
-#define PHY_ANALOG_PLLCLKMODA2_PLLICP_MSB 26
-#define PHY_ANALOG_PLLCLKMODA2_PLLICP_LSB 24
-#define PHY_ANALOG_PLLCLKMODA2_PLLICP_MASK 0x07000000
-#define PHY_ANALOG_PLLCLKMODA2_PLLICP_GET(x) (((x) & 0x07000000) >> 24)
-#define PHY_ANALOG_PLLCLKMODA2_PLLICP_SET(x) (((x) << 24) & 0x07000000)
-#define PHY_ANALOG_PLLCLKMODA2_PLLFILTER_MSB 31
-#define PHY_ANALOG_PLLCLKMODA2_PLLFILTER_LSB 27
-#define PHY_ANALOG_PLLCLKMODA2_PLLFILTER_MASK 0xf8000000
-#define PHY_ANALOG_PLLCLKMODA2_PLLFILTER_GET(x) (((x) & 0xf8000000) >> 27)
-#define PHY_ANALOG_PLLCLKMODA2_PLLFILTER_SET(x) (((x) << 27) & 0xf8000000)
-
-/* macros for TOP */
-#define PHY_ANALOG_TOP_ADDRESS 0x00000288
-#define PHY_ANALOG_TOP_OFFSET 0x00000288
-#define PHY_ANALOG_TOP_SPARE_MSB 2
-#define PHY_ANALOG_TOP_SPARE_LSB 0
-#define PHY_ANALOG_TOP_SPARE_MASK 0x00000007
-#define PHY_ANALOG_TOP_SPARE_GET(x) (((x) & 0x00000007) >> 0)
-#define PHY_ANALOG_TOP_SPARE_SET(x) (((x) << 0) & 0x00000007)
-#define PHY_ANALOG_TOP_PWDBIAS_MSB 3
-#define PHY_ANALOG_TOP_PWDBIAS_LSB 3
-#define PHY_ANALOG_TOP_PWDBIAS_MASK 0x00000008
-#define PHY_ANALOG_TOP_PWDBIAS_GET(x) (((x) & 0x00000008) >> 3)
-#define PHY_ANALOG_TOP_PWDBIAS_SET(x) (((x) << 3) & 0x00000008)
-#define PHY_ANALOG_TOP_FLIP_XPABIAS_MSB 4
-#define PHY_ANALOG_TOP_FLIP_XPABIAS_LSB 4
-#define PHY_ANALOG_TOP_FLIP_XPABIAS_MASK 0x00000010
-#define PHY_ANALOG_TOP_FLIP_XPABIAS_GET(x) (((x) & 0x00000010) >> 4)
-#define PHY_ANALOG_TOP_FLIP_XPABIAS_SET(x) (((x) << 4) & 0x00000010)
-#define PHY_ANALOG_TOP_XPAON2_MSB 5
-#define PHY_ANALOG_TOP_XPAON2_LSB 5
-#define PHY_ANALOG_TOP_XPAON2_MASK 0x00000020
-#define PHY_ANALOG_TOP_XPAON2_GET(x) (((x) & 0x00000020) >> 5)
-#define PHY_ANALOG_TOP_XPAON2_SET(x) (((x) << 5) & 0x00000020)
-#define PHY_ANALOG_TOP_XPAON5_MSB 6
-#define PHY_ANALOG_TOP_XPAON5_LSB 6
-#define PHY_ANALOG_TOP_XPAON5_MASK 0x00000040
-#define PHY_ANALOG_TOP_XPAON5_GET(x) (((x) & 0x00000040) >> 6)
-#define PHY_ANALOG_TOP_XPAON5_SET(x) (((x) << 6) & 0x00000040)
-#define PHY_ANALOG_TOP_XPASHORT2GND_MSB 7
-#define PHY_ANALOG_TOP_XPASHORT2GND_LSB 7
-#define PHY_ANALOG_TOP_XPASHORT2GND_MASK 0x00000080
-#define PHY_ANALOG_TOP_XPASHORT2GND_GET(x) (((x) & 0x00000080) >> 7)
-#define PHY_ANALOG_TOP_XPASHORT2GND_SET(x) (((x) << 7) & 0x00000080)
-#define PHY_ANALOG_TOP_XPABIASLVL_MSB 11
-#define PHY_ANALOG_TOP_XPABIASLVL_LSB 8
-#define PHY_ANALOG_TOP_XPABIASLVL_MASK 0x00000f00
-#define PHY_ANALOG_TOP_XPABIASLVL_GET(x) (((x) & 0x00000f00) >> 8)
-#define PHY_ANALOG_TOP_XPABIASLVL_SET(x) (((x) << 8) & 0x00000f00)
-#define PHY_ANALOG_TOP_XPABIAS_EN_MSB 12
-#define PHY_ANALOG_TOP_XPABIAS_EN_LSB 12
-#define PHY_ANALOG_TOP_XPABIAS_EN_MASK 0x00001000
-#define PHY_ANALOG_TOP_XPABIAS_EN_GET(x) (((x) & 0x00001000) >> 12)
-#define PHY_ANALOG_TOP_XPABIAS_EN_SET(x) (((x) << 12) & 0x00001000)
-#define PHY_ANALOG_TOP_ATBSELECT_MSB 13
-#define PHY_ANALOG_TOP_ATBSELECT_LSB 13
-#define PHY_ANALOG_TOP_ATBSELECT_MASK 0x00002000
-#define PHY_ANALOG_TOP_ATBSELECT_GET(x) (((x) & 0x00002000) >> 13)
-#define PHY_ANALOG_TOP_ATBSELECT_SET(x) (((x) << 13) & 0x00002000)
-#define PHY_ANALOG_TOP_LOCAL_XPA_MSB 14
-#define PHY_ANALOG_TOP_LOCAL_XPA_LSB 14
-#define PHY_ANALOG_TOP_LOCAL_XPA_MASK 0x00004000
-#define PHY_ANALOG_TOP_LOCAL_XPA_GET(x) (((x) & 0x00004000) >> 14)
-#define PHY_ANALOG_TOP_LOCAL_XPA_SET(x) (((x) << 14) & 0x00004000)
-#define PHY_ANALOG_TOP_XPABIAS_BYPASS_MSB 15
-#define PHY_ANALOG_TOP_XPABIAS_BYPASS_LSB 15
-#define PHY_ANALOG_TOP_XPABIAS_BYPASS_MASK 0x00008000
-#define PHY_ANALOG_TOP_XPABIAS_BYPASS_GET(x) (((x) & 0x00008000) >> 15)
-#define PHY_ANALOG_TOP_XPABIAS_BYPASS_SET(x) (((x) << 15) & 0x00008000)
-#define PHY_ANALOG_TOP_TEST_PADQ_EN_MSB 16
-#define PHY_ANALOG_TOP_TEST_PADQ_EN_LSB 16
-#define PHY_ANALOG_TOP_TEST_PADQ_EN_MASK 0x00010000
-#define PHY_ANALOG_TOP_TEST_PADQ_EN_GET(x) (((x) & 0x00010000) >> 16)
-#define PHY_ANALOG_TOP_TEST_PADQ_EN_SET(x) (((x) << 16) & 0x00010000)
-#define PHY_ANALOG_TOP_TEST_PADI_EN_MSB 17
-#define PHY_ANALOG_TOP_TEST_PADI_EN_LSB 17
-#define PHY_ANALOG_TOP_TEST_PADI_EN_MASK 0x00020000
-#define PHY_ANALOG_TOP_TEST_PADI_EN_GET(x) (((x) & 0x00020000) >> 17)
-#define PHY_ANALOG_TOP_TEST_PADI_EN_SET(x) (((x) << 17) & 0x00020000)
-#define PHY_ANALOG_TOP_TESTIQ_RSEL_MSB 18
-#define PHY_ANALOG_TOP_TESTIQ_RSEL_LSB 18
-#define PHY_ANALOG_TOP_TESTIQ_RSEL_MASK 0x00040000
-#define PHY_ANALOG_TOP_TESTIQ_RSEL_GET(x) (((x) & 0x00040000) >> 18)
-#define PHY_ANALOG_TOP_TESTIQ_RSEL_SET(x) (((x) << 18) & 0x00040000)
-#define PHY_ANALOG_TOP_TESTIQ_BUFEN_MSB 19
-#define PHY_ANALOG_TOP_TESTIQ_BUFEN_LSB 19
-#define PHY_ANALOG_TOP_TESTIQ_BUFEN_MASK 0x00080000
-#define PHY_ANALOG_TOP_TESTIQ_BUFEN_GET(x) (((x) & 0x00080000) >> 19)
-#define PHY_ANALOG_TOP_TESTIQ_BUFEN_SET(x) (((x) << 19) & 0x00080000)
-#define PHY_ANALOG_TOP_PAD2GND_MSB 20
-#define PHY_ANALOG_TOP_PAD2GND_LSB 20
-#define PHY_ANALOG_TOP_PAD2GND_MASK 0x00100000
-#define PHY_ANALOG_TOP_PAD2GND_GET(x) (((x) & 0x00100000) >> 20)
-#define PHY_ANALOG_TOP_PAD2GND_SET(x) (((x) << 20) & 0x00100000)
-#define PHY_ANALOG_TOP_INTH2PAD_MSB 21
-#define PHY_ANALOG_TOP_INTH2PAD_LSB 21
-#define PHY_ANALOG_TOP_INTH2PAD_MASK 0x00200000
-#define PHY_ANALOG_TOP_INTH2PAD_GET(x) (((x) & 0x00200000) >> 21)
-#define PHY_ANALOG_TOP_INTH2PAD_SET(x) (((x) << 21) & 0x00200000)
-#define PHY_ANALOG_TOP_INTH2GND_MSB 22
-#define PHY_ANALOG_TOP_INTH2GND_LSB 22
-#define PHY_ANALOG_TOP_INTH2GND_MASK 0x00400000
-#define PHY_ANALOG_TOP_INTH2GND_GET(x) (((x) & 0x00400000) >> 22)
-#define PHY_ANALOG_TOP_INTH2GND_SET(x) (((x) << 22) & 0x00400000)
-#define PHY_ANALOG_TOP_INT2PAD_MSB 23
-#define PHY_ANALOG_TOP_INT2PAD_LSB 23
-#define PHY_ANALOG_TOP_INT2PAD_MASK 0x00800000
-#define PHY_ANALOG_TOP_INT2PAD_GET(x) (((x) & 0x00800000) >> 23)
-#define PHY_ANALOG_TOP_INT2PAD_SET(x) (((x) << 23) & 0x00800000)
-#define PHY_ANALOG_TOP_INT2GND_MSB 24
-#define PHY_ANALOG_TOP_INT2GND_LSB 24
-#define PHY_ANALOG_TOP_INT2GND_MASK 0x01000000
-#define PHY_ANALOG_TOP_INT2GND_GET(x) (((x) & 0x01000000) >> 24)
-#define PHY_ANALOG_TOP_INT2GND_SET(x) (((x) << 24) & 0x01000000)
-#define PHY_ANALOG_TOP_PWDPALCLK_MSB 25
-#define PHY_ANALOG_TOP_PWDPALCLK_LSB 25
-#define PHY_ANALOG_TOP_PWDPALCLK_MASK 0x02000000
-#define PHY_ANALOG_TOP_PWDPALCLK_GET(x) (((x) & 0x02000000) >> 25)
-#define PHY_ANALOG_TOP_PWDPALCLK_SET(x) (((x) << 25) & 0x02000000)
-#define PHY_ANALOG_TOP_INV_CLK320_ADC_MSB 26
-#define PHY_ANALOG_TOP_INV_CLK320_ADC_LSB 26
-#define PHY_ANALOG_TOP_INV_CLK320_ADC_MASK 0x04000000
-#define PHY_ANALOG_TOP_INV_CLK320_ADC_GET(x) (((x) & 0x04000000) >> 26)
-#define PHY_ANALOG_TOP_INV_CLK320_ADC_SET(x) (((x) << 26) & 0x04000000)
-#define PHY_ANALOG_TOP_FLIP_REFCLK40_MSB 27
-#define PHY_ANALOG_TOP_FLIP_REFCLK40_LSB 27
-#define PHY_ANALOG_TOP_FLIP_REFCLK40_MASK 0x08000000
-#define PHY_ANALOG_TOP_FLIP_REFCLK40_GET(x) (((x) & 0x08000000) >> 27)
-#define PHY_ANALOG_TOP_FLIP_REFCLK40_SET(x) (((x) << 27) & 0x08000000)
-#define PHY_ANALOG_TOP_FLIP_PLLCLK320_MSB 28
-#define PHY_ANALOG_TOP_FLIP_PLLCLK320_LSB 28
-#define PHY_ANALOG_TOP_FLIP_PLLCLK320_MASK 0x10000000
-#define PHY_ANALOG_TOP_FLIP_PLLCLK320_GET(x) (((x) & 0x10000000) >> 28)
-#define PHY_ANALOG_TOP_FLIP_PLLCLK320_SET(x) (((x) << 28) & 0x10000000)
-#define PHY_ANALOG_TOP_FLIP_PLLCLK160_MSB 29
-#define PHY_ANALOG_TOP_FLIP_PLLCLK160_LSB 29
-#define PHY_ANALOG_TOP_FLIP_PLLCLK160_MASK 0x20000000
-#define PHY_ANALOG_TOP_FLIP_PLLCLK160_GET(x) (((x) & 0x20000000) >> 29)
-#define PHY_ANALOG_TOP_FLIP_PLLCLK160_SET(x) (((x) << 29) & 0x20000000)
-#define PHY_ANALOG_TOP_CLK_SEL_MSB 31
-#define PHY_ANALOG_TOP_CLK_SEL_LSB 30
-#define PHY_ANALOG_TOP_CLK_SEL_MASK 0xc0000000
-#define PHY_ANALOG_TOP_CLK_SEL_GET(x) (((x) & 0xc0000000) >> 30)
-#define PHY_ANALOG_TOP_CLK_SEL_SET(x) (((x) << 30) & 0xc0000000)
-
-/* macros for THERM */
-#define PHY_ANALOG_THERM_ADDRESS 0x0000028c
-#define PHY_ANALOG_THERM_OFFSET 0x0000028c
-#define PHY_ANALOG_THERM_LOREG_LVL_MSB 2
-#define PHY_ANALOG_THERM_LOREG_LVL_LSB 0
-#define PHY_ANALOG_THERM_LOREG_LVL_MASK 0x00000007
-#define PHY_ANALOG_THERM_LOREG_LVL_GET(x) (((x) & 0x00000007) >> 0)
-#define PHY_ANALOG_THERM_LOREG_LVL_SET(x) (((x) << 0) & 0x00000007)
-#define PHY_ANALOG_THERM_RFREG_LVL_MSB 5
-#define PHY_ANALOG_THERM_RFREG_LVL_LSB 3
-#define PHY_ANALOG_THERM_RFREG_LVL_MASK 0x00000038
-#define PHY_ANALOG_THERM_RFREG_LVL_GET(x) (((x) & 0x00000038) >> 3)
-#define PHY_ANALOG_THERM_RFREG_LVL_SET(x) (((x) << 3) & 0x00000038)
-#define PHY_ANALOG_THERM_SAR_ADC_DONE_MSB 6
-#define PHY_ANALOG_THERM_SAR_ADC_DONE_LSB 6
-#define PHY_ANALOG_THERM_SAR_ADC_DONE_MASK 0x00000040
-#define PHY_ANALOG_THERM_SAR_ADC_DONE_GET(x) (((x) & 0x00000040) >> 6)
-#define PHY_ANALOG_THERM_SAR_ADC_OUT_MSB 14
-#define PHY_ANALOG_THERM_SAR_ADC_OUT_LSB 7
-#define PHY_ANALOG_THERM_SAR_ADC_OUT_MASK 0x00007f80
-#define PHY_ANALOG_THERM_SAR_ADC_OUT_GET(x) (((x) & 0x00007f80) >> 7)
-#define PHY_ANALOG_THERM_SAR_DACTEST_CODE_MSB 22
-#define PHY_ANALOG_THERM_SAR_DACTEST_CODE_LSB 15
-#define PHY_ANALOG_THERM_SAR_DACTEST_CODE_MASK 0x007f8000
-#define PHY_ANALOG_THERM_SAR_DACTEST_CODE_GET(x) (((x) & 0x007f8000) >> 15)
-#define PHY_ANALOG_THERM_SAR_DACTEST_CODE_SET(x) (((x) << 15) & 0x007f8000)
-#define PHY_ANALOG_THERM_SAR_DACTEST_EN_MSB 23
-#define PHY_ANALOG_THERM_SAR_DACTEST_EN_LSB 23
-#define PHY_ANALOG_THERM_SAR_DACTEST_EN_MASK 0x00800000
-#define PHY_ANALOG_THERM_SAR_DACTEST_EN_GET(x) (((x) & 0x00800000) >> 23)
-#define PHY_ANALOG_THERM_SAR_DACTEST_EN_SET(x) (((x) << 23) & 0x00800000)
-#define PHY_ANALOG_THERM_SAR_ADCCAL_EN_MSB 24
-#define PHY_ANALOG_THERM_SAR_ADCCAL_EN_LSB 24
-#define PHY_ANALOG_THERM_SAR_ADCCAL_EN_MASK 0x01000000
-#define PHY_ANALOG_THERM_SAR_ADCCAL_EN_GET(x) (((x) & 0x01000000) >> 24)
-#define PHY_ANALOG_THERM_SAR_ADCCAL_EN_SET(x) (((x) << 24) & 0x01000000)
-#define PHY_ANALOG_THERM_THERMSEL_MSB 26
-#define PHY_ANALOG_THERM_THERMSEL_LSB 25
-#define PHY_ANALOG_THERM_THERMSEL_MASK 0x06000000
-#define PHY_ANALOG_THERM_THERMSEL_GET(x) (((x) & 0x06000000) >> 25)
-#define PHY_ANALOG_THERM_THERMSEL_SET(x) (((x) << 25) & 0x06000000)
-#define PHY_ANALOG_THERM_SAR_SLOW_EN_MSB 27
-#define PHY_ANALOG_THERM_SAR_SLOW_EN_LSB 27
-#define PHY_ANALOG_THERM_SAR_SLOW_EN_MASK 0x08000000
-#define PHY_ANALOG_THERM_SAR_SLOW_EN_GET(x) (((x) & 0x08000000) >> 27)
-#define PHY_ANALOG_THERM_SAR_SLOW_EN_SET(x) (((x) << 27) & 0x08000000)
-#define PHY_ANALOG_THERM_THERMSTART_MSB 28
-#define PHY_ANALOG_THERM_THERMSTART_LSB 28
-#define PHY_ANALOG_THERM_THERMSTART_MASK 0x10000000
-#define PHY_ANALOG_THERM_THERMSTART_GET(x) (((x) & 0x10000000) >> 28)
-#define PHY_ANALOG_THERM_THERMSTART_SET(x) (((x) << 28) & 0x10000000)
-#define PHY_ANALOG_THERM_SAR_AUTOPWD_EN_MSB 29
-#define PHY_ANALOG_THERM_SAR_AUTOPWD_EN_LSB 29
-#define PHY_ANALOG_THERM_SAR_AUTOPWD_EN_MASK 0x20000000
-#define PHY_ANALOG_THERM_SAR_AUTOPWD_EN_GET(x) (((x) & 0x20000000) >> 29)
-#define PHY_ANALOG_THERM_SAR_AUTOPWD_EN_SET(x) (((x) << 29) & 0x20000000)
-#define PHY_ANALOG_THERM_THERMON_MSB 30
-#define PHY_ANALOG_THERM_THERMON_LSB 30
-#define PHY_ANALOG_THERM_THERMON_MASK 0x40000000
-#define PHY_ANALOG_THERM_THERMON_GET(x) (((x) & 0x40000000) >> 30)
-#define PHY_ANALOG_THERM_THERMON_SET(x) (((x) << 30) & 0x40000000)
-#define PHY_ANALOG_THERM_LOCAL_THERM_MSB 31
-#define PHY_ANALOG_THERM_LOCAL_THERM_LSB 31
-#define PHY_ANALOG_THERM_LOCAL_THERM_MASK 0x80000000
-#define PHY_ANALOG_THERM_LOCAL_THERM_GET(x) (((x) & 0x80000000) >> 31)
-#define PHY_ANALOG_THERM_LOCAL_THERM_SET(x) (((x) << 31) & 0x80000000)
-
-/* macros for XTAL */
-#define PHY_ANALOG_XTAL_ADDRESS 0x00000290
-#define PHY_ANALOG_XTAL_OFFSET 0x00000290
-#define PHY_ANALOG_XTAL_SPARE_MSB 5
-#define PHY_ANALOG_XTAL_SPARE_LSB 0
-#define PHY_ANALOG_XTAL_SPARE_MASK 0x0000003f
-#define PHY_ANALOG_XTAL_SPARE_GET(x) (((x) & 0x0000003f) >> 0)
-#define PHY_ANALOG_XTAL_SPARE_SET(x) (((x) << 0) & 0x0000003f)
-#define PHY_ANALOG_XTAL_XTAL_NOTCXODET_MSB 6
-#define PHY_ANALOG_XTAL_XTAL_NOTCXODET_LSB 6
-#define PHY_ANALOG_XTAL_XTAL_NOTCXODET_MASK 0x00000040
-#define PHY_ANALOG_XTAL_XTAL_NOTCXODET_GET(x) (((x) & 0x00000040) >> 6)
-#define PHY_ANALOG_XTAL_XTAL_NOTCXODET_SET(x) (((x) << 6) & 0x00000040)
-#define PHY_ANALOG_XTAL_LOCALBIAS2X_MSB 7
-#define PHY_ANALOG_XTAL_LOCALBIAS2X_LSB 7
-#define PHY_ANALOG_XTAL_LOCALBIAS2X_MASK 0x00000080
-#define PHY_ANALOG_XTAL_LOCALBIAS2X_GET(x) (((x) & 0x00000080) >> 7)
-#define PHY_ANALOG_XTAL_LOCALBIAS2X_SET(x) (((x) << 7) & 0x00000080)
-#define PHY_ANALOG_XTAL_LOCAL_XTAL_MSB 8
-#define PHY_ANALOG_XTAL_LOCAL_XTAL_LSB 8
-#define PHY_ANALOG_XTAL_LOCAL_XTAL_MASK 0x00000100
-#define PHY_ANALOG_XTAL_LOCAL_XTAL_GET(x) (((x) & 0x00000100) >> 8)
-#define PHY_ANALOG_XTAL_LOCAL_XTAL_SET(x) (((x) << 8) & 0x00000100)
-#define PHY_ANALOG_XTAL_XTAL_PWDCLKIN_MSB 9
-#define PHY_ANALOG_XTAL_XTAL_PWDCLKIN_LSB 9
-#define PHY_ANALOG_XTAL_XTAL_PWDCLKIN_MASK 0x00000200
-#define PHY_ANALOG_XTAL_XTAL_PWDCLKIN_GET(x) (((x) & 0x00000200) >> 9)
-#define PHY_ANALOG_XTAL_XTAL_PWDCLKIN_SET(x) (((x) << 9) & 0x00000200)
-#define PHY_ANALOG_XTAL_XTAL_OSCON_MSB 10
-#define PHY_ANALOG_XTAL_XTAL_OSCON_LSB 10
-#define PHY_ANALOG_XTAL_XTAL_OSCON_MASK 0x00000400
-#define PHY_ANALOG_XTAL_XTAL_OSCON_GET(x) (((x) & 0x00000400) >> 10)
-#define PHY_ANALOG_XTAL_XTAL_OSCON_SET(x) (((x) << 10) & 0x00000400)
-#define PHY_ANALOG_XTAL_XTAL_PWDCLKD_MSB 11
-#define PHY_ANALOG_XTAL_XTAL_PWDCLKD_LSB 11
-#define PHY_ANALOG_XTAL_XTAL_PWDCLKD_MASK 0x00000800
-#define PHY_ANALOG_XTAL_XTAL_PWDCLKD_GET(x) (((x) & 0x00000800) >> 11)
-#define PHY_ANALOG_XTAL_XTAL_PWDCLKD_SET(x) (((x) << 11) & 0x00000800)
-#define PHY_ANALOG_XTAL_XTAL_LOCALBIAS_MSB 12
-#define PHY_ANALOG_XTAL_XTAL_LOCALBIAS_LSB 12
-#define PHY_ANALOG_XTAL_XTAL_LOCALBIAS_MASK 0x00001000
-#define PHY_ANALOG_XTAL_XTAL_LOCALBIAS_GET(x) (((x) & 0x00001000) >> 12)
-#define PHY_ANALOG_XTAL_XTAL_LOCALBIAS_SET(x) (((x) << 12) & 0x00001000)
-#define PHY_ANALOG_XTAL_XTAL_SHRTXIN_MSB 13
-#define PHY_ANALOG_XTAL_XTAL_SHRTXIN_LSB 13
-#define PHY_ANALOG_XTAL_XTAL_SHRTXIN_MASK 0x00002000
-#define PHY_ANALOG_XTAL_XTAL_SHRTXIN_GET(x) (((x) & 0x00002000) >> 13)
-#define PHY_ANALOG_XTAL_XTAL_SHRTXIN_SET(x) (((x) << 13) & 0x00002000)
-#define PHY_ANALOG_XTAL_XTAL_DRVSTR_MSB 15
-#define PHY_ANALOG_XTAL_XTAL_DRVSTR_LSB 14
-#define PHY_ANALOG_XTAL_XTAL_DRVSTR_MASK 0x0000c000
-#define PHY_ANALOG_XTAL_XTAL_DRVSTR_GET(x) (((x) & 0x0000c000) >> 14)
-#define PHY_ANALOG_XTAL_XTAL_DRVSTR_SET(x) (((x) << 14) & 0x0000c000)
-#define PHY_ANALOG_XTAL_XTAL_CAPOUTDAC_MSB 22
-#define PHY_ANALOG_XTAL_XTAL_CAPOUTDAC_LSB 16
-#define PHY_ANALOG_XTAL_XTAL_CAPOUTDAC_MASK 0x007f0000
-#define PHY_ANALOG_XTAL_XTAL_CAPOUTDAC_GET(x) (((x) & 0x007f0000) >> 16)
-#define PHY_ANALOG_XTAL_XTAL_CAPOUTDAC_SET(x) (((x) << 16) & 0x007f0000)
-#define PHY_ANALOG_XTAL_XTAL_CAPINDAC_MSB 29
-#define PHY_ANALOG_XTAL_XTAL_CAPINDAC_LSB 23
-#define PHY_ANALOG_XTAL_XTAL_CAPINDAC_MASK 0x3f800000
-#define PHY_ANALOG_XTAL_XTAL_CAPINDAC_GET(x) (((x) & 0x3f800000) >> 23)
-#define PHY_ANALOG_XTAL_XTAL_CAPINDAC_SET(x) (((x) << 23) & 0x3f800000)
-#define PHY_ANALOG_XTAL_XTAL_BIAS2X_MSB 30
-#define PHY_ANALOG_XTAL_XTAL_BIAS2X_LSB 30
-#define PHY_ANALOG_XTAL_XTAL_BIAS2X_MASK 0x40000000
-#define PHY_ANALOG_XTAL_XTAL_BIAS2X_GET(x) (((x) & 0x40000000) >> 30)
-#define PHY_ANALOG_XTAL_XTAL_BIAS2X_SET(x) (((x) << 30) & 0x40000000)
-#define PHY_ANALOG_XTAL_TCXODET_MSB 31
-#define PHY_ANALOG_XTAL_TCXODET_LSB 31
-#define PHY_ANALOG_XTAL_TCXODET_MASK 0x80000000
-#define PHY_ANALOG_XTAL_TCXODET_GET(x) (((x) & 0x80000000) >> 31)
-
-/* macros for rbist_cntrl */
-#define PHY_ANALOG_RBIST_CNTRL_ADDRESS 0x00000380
-#define PHY_ANALOG_RBIST_CNTRL_OFFSET 0x00000380
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_MSB 0
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_LSB 0
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_MASK 0x00000001
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_DC_ENABLE_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_MSB 1
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_LSB 1
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_MASK 0x00000002
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_GET(x) (((x) & 0x00000002) >> 1)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE0_ENABLE_SET(x) (((x) << 1) & 0x00000002)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_MSB 2
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_LSB 2
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_MASK 0x00000004
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_GET(x) (((x) & 0x00000004) >> 2)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_TONE1_ENABLE_SET(x) (((x) << 2) & 0x00000004)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_MSB 3
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_LSB 3
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_MASK 0x00000008
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_GET(x) (((x) & 0x00000008) >> 3)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LFTONE0_ENABLE_SET(x) (((x) << 3) & 0x00000008)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_MSB 4
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_LSB 4
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_MASK 0x00000010
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_GET(x) (((x) & 0x00000010) >> 4)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_I_SET(x) (((x) << 4) & 0x00000010)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_MSB 5
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_LSB 5
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_MASK 0x00000020
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_GET(x) (((x) & 0x00000020) >> 5)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_LINRAMP_ENABLE_Q_SET(x) (((x) << 5) & 0x00000020)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_MSB 6
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_LSB 6
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_MASK 0x00000040
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_GET(x) (((x) & 0x00000040) >> 6)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_I_SET(x) (((x) << 6) & 0x00000040)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_MSB 7
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_LSB 7
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_MASK 0x00000080
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_GET(x) (((x) & 0x00000080) >> 7)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_TONEGEN_PRBS_ENABLE_Q_SET(x) (((x) << 7) & 0x00000080)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_MSB 8
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_LSB 8
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_MASK 0x00000100
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_GET(x) (((x) & 0x00000100) >> 8)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_WRITE_TO_CANCEL_SET(x) (((x) << 8) & 0x00000100)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_MSB 9
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_LSB 9
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_MASK 0x00000200
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_GET(x) (((x) & 0x00000200) >> 9)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_DC_ENABLE_SET(x) (((x) << 9) & 0x00000200)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_MSB 10
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_LSB 10
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_MASK 0x00000400
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_GET(x) (((x) & 0x00000400) >> 10)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_CORR_ENABLE_SET(x) (((x) << 10) & 0x00000400)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_MSB 11
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_LSB 11
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_MASK 0x00000800
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_GET(x) (((x) & 0x00000800) >> 11)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_ENABLE_SET(x) (((x) << 11) & 0x00000800)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_MSB 12
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_LSB 12
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_MASK 0x00001000
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_GET(x) (((x) & 0x00001000) >> 12)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_IQ_ENABLE_SET(x) (((x) << 12) & 0x00001000)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_MSB 13
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_LSB 13
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_MASK 0x00002000
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_GET(x) (((x) & 0x00002000) >> 13)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_I2Q2_ENABLE_SET(x) (((x) << 13) & 0x00002000)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_MSB 14
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_LSB 14
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_MASK 0x00004000
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_GET(x) (((x) & 0x00004000) >> 14)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_CMAC_POWER_HPF_ENABLE_SET(x) (((x) << 14) & 0x00004000)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_MSB 15
-#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_LSB 15
-#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_MASK 0x00008000
-#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_GET(x) (((x) & 0x00008000) >> 15)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_RXDAC_CALIBRATE_SET(x) (((x) << 15) & 0x00008000)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_MSB 16
-#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_LSB 16
-#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_MASK 0x00010000
-#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_GET(x) (((x) & 0x00010000) >> 16)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_RBIST_ENABLE_SET(x) (((x) << 16) & 0x00010000)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_MSB 17
-#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_LSB 17
-#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_MASK 0x00020000
-#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_GET(x) (((x) & 0x00020000) >> 17)
-#define PHY_ANALOG_RBIST_CNTRL_ATE_ADC_CLK_INVERT_SET(x) (((x) << 17) & 0x00020000)
-
-/* macros for tx_dc_offset */
-#define PHY_ANALOG_TX_DC_OFFSET_ADDRESS 0x00000384
-#define PHY_ANALOG_TX_DC_OFFSET_OFFSET 0x00000384
-#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_MSB 10
-#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_LSB 0
-#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_MASK 0x000007ff
-#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_GET(x) (((x) & 0x000007ff) >> 0)
-#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_I_SET(x) (((x) << 0) & 0x000007ff)
-#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_MSB 26
-#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_LSB 16
-#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_MASK 0x07ff0000
-#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_GET(x) (((x) & 0x07ff0000) >> 16)
-#define PHY_ANALOG_TX_DC_OFFSET_ATE_TONEGEN_DC_Q_SET(x) (((x) << 16) & 0x07ff0000)
-
-/* macros for tx_tonegen0 */
-#define PHY_ANALOG_TX_TONEGEN0_ADDRESS 0x00000388
-#define PHY_ANALOG_TX_TONEGEN0_OFFSET 0x00000388
-#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_MSB 6
-#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_LSB 0
-#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_MASK 0x0000007f
-#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_GET(x) (((x) & 0x0000007f) >> 0)
-#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_FREQ_SET(x) (((x) << 0) & 0x0000007f)
-#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_MSB 11
-#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_LSB 8
-#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_MASK 0x00000f00
-#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_GET(x) (((x) & 0x00000f00) >> 8)
-#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_EXP_SET(x) (((x) << 8) & 0x00000f00)
-#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_MSB 23
-#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_LSB 16
-#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_MASK 0x00ff0000
-#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_GET(x) (((x) & 0x00ff0000) >> 16)
-#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_A_MAN_SET(x) (((x) << 16) & 0x00ff0000)
-#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_MSB 30
-#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_LSB 24
-#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_MASK 0x7f000000
-#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_GET(x) (((x) & 0x7f000000) >> 24)
-#define PHY_ANALOG_TX_TONEGEN0_ATE_TONEGEN_TONE_TAU_K_SET(x) (((x) << 24) & 0x7f000000)
-
-/* macros for tx_tonegen1 */
-#define PHY_ANALOG_TX_TONEGEN1_ADDRESS 0x0000038c
-#define PHY_ANALOG_TX_TONEGEN1_OFFSET 0x0000038c
-#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_MSB 6
-#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_LSB 0
-#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_MASK 0x0000007f
-#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_GET(x) (((x) & 0x0000007f) >> 0)
-#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_FREQ_SET(x) (((x) << 0) & 0x0000007f)
-#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_MSB 11
-#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_LSB 8
-#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_MASK 0x00000f00
-#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_GET(x) (((x) & 0x00000f00) >> 8)
-#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_EXP_SET(x) (((x) << 8) & 0x00000f00)
-#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_MSB 23
-#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_LSB 16
-#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_MASK 0x00ff0000
-#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_GET(x) (((x) & 0x00ff0000) >> 16)
-#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_A_MAN_SET(x) (((x) << 16) & 0x00ff0000)
-#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_MSB 30
-#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_LSB 24
-#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_MASK 0x7f000000
-#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_GET(x) (((x) & 0x7f000000) >> 24)
-#define PHY_ANALOG_TX_TONEGEN1_ATE_TONEGEN_TONE_TAU_K_SET(x) (((x) << 24) & 0x7f000000)
-
-/* macros for tx_lftonegen0 */
-#define PHY_ANALOG_TX_LFTONEGEN0_ADDRESS 0x00000390
-#define PHY_ANALOG_TX_LFTONEGEN0_OFFSET 0x00000390
-#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_MSB 6
-#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_LSB 0
-#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_MASK 0x0000007f
-#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_GET(x) (((x) & 0x0000007f) >> 0)
-#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_FREQ_SET(x) (((x) << 0) & 0x0000007f)
-#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_MSB 11
-#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_LSB 8
-#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_MASK 0x00000f00
-#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_GET(x) (((x) & 0x00000f00) >> 8)
-#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_EXP_SET(x) (((x) << 8) & 0x00000f00)
-#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_MSB 23
-#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_LSB 16
-#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_MASK 0x00ff0000
-#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_GET(x) (((x) & 0x00ff0000) >> 16)
-#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_A_MAN_SET(x) (((x) << 16) & 0x00ff0000)
-#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_MSB 30
-#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_LSB 24
-#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_MASK 0x7f000000
-#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_GET(x) (((x) & 0x7f000000) >> 24)
-#define PHY_ANALOG_TX_LFTONEGEN0_ATE_TONEGEN_TONE_TAU_K_SET(x) (((x) << 24) & 0x7f000000)
-
-/* macros for tx_linear_ramp_i */
-#define PHY_ANALOG_TX_LINEAR_RAMP_I_ADDRESS 0x00000394
-#define PHY_ANALOG_TX_LINEAR_RAMP_I_OFFSET 0x00000394
-#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_MSB 10
-#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_LSB 0
-#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_MASK 0x000007ff
-#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_GET(x) (((x) & 0x000007ff) >> 0)
-#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_INIT_SET(x) (((x) << 0) & 0x000007ff)
-#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_MSB 21
-#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_LSB 12
-#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_MASK 0x003ff000
-#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_GET(x) (((x) & 0x003ff000) >> 12)
-#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_DWELL_SET(x) (((x) << 12) & 0x003ff000)
-#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_MSB 29
-#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_LSB 24
-#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_MASK 0x3f000000
-#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_GET(x) (((x) & 0x3f000000) >> 24)
-#define PHY_ANALOG_TX_LINEAR_RAMP_I_ATE_TONEGEN_LINRAMP_STEP_SET(x) (((x) << 24) & 0x3f000000)
-
-/* macros for tx_linear_ramp_q */
-#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ADDRESS 0x00000398
-#define PHY_ANALOG_TX_LINEAR_RAMP_Q_OFFSET 0x00000398
-#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_MSB 10
-#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_LSB 0
-#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_MASK 0x000007ff
-#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_GET(x) (((x) & 0x000007ff) >> 0)
-#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_INIT_SET(x) (((x) << 0) & 0x000007ff)
-#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_MSB 21
-#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_LSB 12
-#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_MASK 0x003ff000
-#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_GET(x) (((x) & 0x003ff000) >> 12)
-#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_DWELL_SET(x) (((x) << 12) & 0x003ff000)
-#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_MSB 29
-#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_LSB 24
-#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_MASK 0x3f000000
-#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_GET(x) (((x) & 0x3f000000) >> 24)
-#define PHY_ANALOG_TX_LINEAR_RAMP_Q_ATE_TONEGEN_LINRAMP_STEP_SET(x) (((x) << 24) & 0x3f000000)
-
-/* macros for tx_prbs_mag */
-#define PHY_ANALOG_TX_PRBS_MAG_ADDRESS 0x0000039c
-#define PHY_ANALOG_TX_PRBS_MAG_OFFSET 0x0000039c
-#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_MSB 9
-#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_LSB 0
-#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_MASK 0x000003ff
-#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_GET(x) (((x) & 0x000003ff) >> 0)
-#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_I_SET(x) (((x) << 0) & 0x000003ff)
-#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_MSB 25
-#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_LSB 16
-#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_MASK 0x03ff0000
-#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_GET(x) (((x) & 0x03ff0000) >> 16)
-#define PHY_ANALOG_TX_PRBS_MAG_ATE_TONEGEN_PRBS_MAGNITUDE_Q_SET(x) (((x) << 16) & 0x03ff0000)
-
-/* macros for tx_prbs_seed_i */
-#define PHY_ANALOG_TX_PRBS_SEED_I_ADDRESS 0x000003a0
-#define PHY_ANALOG_TX_PRBS_SEED_I_OFFSET 0x000003a0
-#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_MSB 30
-#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_LSB 0
-#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_MASK 0x7fffffff
-#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_GET(x) (((x) & 0x7fffffff) >> 0)
-#define PHY_ANALOG_TX_PRBS_SEED_I_ATE_TONEGEN_PRBS_SEED_SET(x) (((x) << 0) & 0x7fffffff)
-
-/* macros for tx_prbs_seed_q */
-#define PHY_ANALOG_TX_PRBS_SEED_Q_ADDRESS 0x000003a4
-#define PHY_ANALOG_TX_PRBS_SEED_Q_OFFSET 0x000003a4
-#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_MSB 30
-#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_LSB 0
-#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_MASK 0x7fffffff
-#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_GET(x) (((x) & 0x7fffffff) >> 0)
-#define PHY_ANALOG_TX_PRBS_SEED_Q_ATE_TONEGEN_PRBS_SEED_SET(x) (((x) << 0) & 0x7fffffff)
-
-/* macros for cmac_dc_cancel */
-#define PHY_ANALOG_CMAC_DC_CANCEL_ADDRESS 0x000003a8
-#define PHY_ANALOG_CMAC_DC_CANCEL_OFFSET 0x000003a8
-#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_MSB 9
-#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_LSB 0
-#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_MASK 0x000003ff
-#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_GET(x) (((x) & 0x000003ff) >> 0)
-#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_I_SET(x) (((x) << 0) & 0x000003ff)
-#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_MSB 25
-#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_LSB 16
-#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_MASK 0x03ff0000
-#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_GET(x) (((x) & 0x03ff0000) >> 16)
-#define PHY_ANALOG_CMAC_DC_CANCEL_ATE_CMAC_DC_CANCEL_Q_SET(x) (((x) << 16) & 0x03ff0000)
-
-/* macros for cmac_dc_offset */
-#define PHY_ANALOG_CMAC_DC_OFFSET_ADDRESS 0x000003ac
-#define PHY_ANALOG_CMAC_DC_OFFSET_OFFSET 0x000003ac
-#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_MSB 3
-#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_LSB 0
-#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_MASK 0x0000000f
-#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_GET(x) (((x) & 0x0000000f) >> 0)
-#define PHY_ANALOG_CMAC_DC_OFFSET_ATE_CMAC_DC_CYCLES_SET(x) (((x) << 0) & 0x0000000f)
-
-/* macros for cmac_corr */
-#define PHY_ANALOG_CMAC_CORR_ADDRESS 0x000003b0
-#define PHY_ANALOG_CMAC_CORR_OFFSET 0x000003b0
-#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_MSB 4
-#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_LSB 0
-#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_MASK 0x0000001f
-#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_GET(x) (((x) & 0x0000001f) >> 0)
-#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_CYCLES_SET(x) (((x) << 0) & 0x0000001f)
-#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_MSB 13
-#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_LSB 8
-#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_MASK 0x00003f00
-#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_GET(x) (((x) & 0x00003f00) >> 8)
-#define PHY_ANALOG_CMAC_CORR_ATE_CMAC_CORR_FREQ_SET(x) (((x) << 8) & 0x00003f00)
-
-/* macros for cmac_power */
-#define PHY_ANALOG_CMAC_POWER_ADDRESS 0x000003b4
-#define PHY_ANALOG_CMAC_POWER_OFFSET 0x000003b4
-#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_MSB 3
-#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_LSB 0
-#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_MASK 0x0000000f
-#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_GET(x) (((x) & 0x0000000f) >> 0)
-#define PHY_ANALOG_CMAC_POWER_ATE_CMAC_POWER_CYCLES_SET(x) (((x) << 0) & 0x0000000f)
-
-/* macros for cmac_cross_corr */
-#define PHY_ANALOG_CMAC_CROSS_CORR_ADDRESS 0x000003b8
-#define PHY_ANALOG_CMAC_CROSS_CORR_OFFSET 0x000003b8
-#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_MSB 3
-#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_LSB 0
-#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_MASK 0x0000000f
-#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_GET(x) (((x) & 0x0000000f) >> 0)
-#define PHY_ANALOG_CMAC_CROSS_CORR_ATE_CMAC_IQ_CYCLES_SET(x) (((x) << 0) & 0x0000000f)
-
-/* macros for cmac_i2q2 */
-#define PHY_ANALOG_CMAC_I2Q2_ADDRESS 0x000003bc
-#define PHY_ANALOG_CMAC_I2Q2_OFFSET 0x000003bc
-#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_MSB 3
-#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_LSB 0
-#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_MASK 0x0000000f
-#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_GET(x) (((x) & 0x0000000f) >> 0)
-#define PHY_ANALOG_CMAC_I2Q2_ATE_CMAC_I2Q2_CYCLES_SET(x) (((x) << 0) & 0x0000000f)
-
-/* macros for cmac_power_hpf */
-#define PHY_ANALOG_CMAC_POWER_HPF_ADDRESS 0x000003c0
-#define PHY_ANALOG_CMAC_POWER_HPF_OFFSET 0x000003c0
-#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_MSB 3
-#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_LSB 0
-#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_MASK 0x0000000f
-#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_GET(x) (((x) & 0x0000000f) >> 0)
-#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_CYCLES_SET(x) (((x) << 0) & 0x0000000f)
-#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_MSB 7
-#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_LSB 4
-#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_MASK 0x000000f0
-#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_GET(x) (((x) & 0x000000f0) >> 4)
-#define PHY_ANALOG_CMAC_POWER_HPF_ATE_CMAC_POWER_HPF_WAIT_SET(x) (((x) << 4) & 0x000000f0)
-
-/* macros for rxdac_set1 */
-#define PHY_ANALOG_RXDAC_SET1_ADDRESS 0x000003c4
-#define PHY_ANALOG_RXDAC_SET1_OFFSET 0x000003c4
-#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_MSB 1
-#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_LSB 0
-#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_MASK 0x00000003
-#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_GET(x) (((x) & 0x00000003) >> 0)
-#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_MUX_SET(x) (((x) << 0) & 0x00000003)
-#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_MSB 4
-#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_LSB 4
-#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_MASK 0x00000010
-#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_GET(x) (((x) & 0x00000010) >> 4)
-#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_HI_GAIN_SET(x) (((x) << 4) & 0x00000010)
-#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_MSB 13
-#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_LSB 8
-#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_MASK 0x00003f00
-#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_GET(x) (((x) & 0x00003f00) >> 8)
-#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_WAIT_SET(x) (((x) << 8) & 0x00003f00)
-#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_MSB 19
-#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_LSB 16
-#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_MASK 0x000f0000
-#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_GET(x) (((x) & 0x000f0000) >> 16)
-#define PHY_ANALOG_RXDAC_SET1_ATE_RXDAC_CAL_MEASURE_TIME_SET(x) (((x) << 16) & 0x000f0000)
-
-/* macros for rxdac_set2 */
-#define PHY_ANALOG_RXDAC_SET2_ADDRESS 0x000003c8
-#define PHY_ANALOG_RXDAC_SET2_OFFSET 0x000003c8
-#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_MSB 4
-#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_LSB 0
-#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_MASK 0x0000001f
-#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_GET(x) (((x) & 0x0000001f) >> 0)
-#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_HI_SET(x) (((x) << 0) & 0x0000001f)
-#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_MSB 12
-#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_LSB 8
-#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_MASK 0x00001f00
-#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_GET(x) (((x) & 0x00001f00) >> 8)
-#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_HI_SET(x) (((x) << 8) & 0x00001f00)
-#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_MSB 20
-#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_LSB 16
-#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_MASK 0x001f0000
-#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_GET(x) (((x) & 0x001f0000) >> 16)
-#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_I_LOW_SET(x) (((x) << 16) & 0x001f0000)
-#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_MSB 28
-#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_LSB 24
-#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_MASK 0x1f000000
-#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_GET(x) (((x) & 0x1f000000) >> 24)
-#define PHY_ANALOG_RXDAC_SET2_ATE_RXDAC_Q_LOW_SET(x) (((x) << 24) & 0x1f000000)
-
-/* macros for rxdac_long_shift */
-#define PHY_ANALOG_RXDAC_LONG_SHIFT_ADDRESS 0x000003cc
-#define PHY_ANALOG_RXDAC_LONG_SHIFT_OFFSET 0x000003cc
-#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_MSB 4
-#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_LSB 0
-#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_MASK 0x0000001f
-#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_GET(x) (((x) & 0x0000001f) >> 0)
-#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_I_STATIC_SET(x) (((x) << 0) & 0x0000001f)
-#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_MSB 12
-#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_LSB 8
-#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_MASK 0x00001f00
-#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_GET(x) (((x) & 0x00001f00) >> 8)
-#define PHY_ANALOG_RXDAC_LONG_SHIFT_ATE_RXDAC_Q_STATIC_SET(x) (((x) << 8) & 0x00001f00)
-
-/* macros for cmac_results_i */
-#define PHY_ANALOG_CMAC_RESULTS_I_ADDRESS 0x000003d0
-#define PHY_ANALOG_CMAC_RESULTS_I_OFFSET 0x000003d0
-#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_MSB 31
-#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_LSB 0
-#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_MASK 0xffffffff
-#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_ANALOG_CMAC_RESULTS_I_ATE_CMAC_RESULTS_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for cmac_results_q */
-#define PHY_ANALOG_CMAC_RESULTS_Q_ADDRESS 0x000003d4
-#define PHY_ANALOG_CMAC_RESULTS_Q_OFFSET 0x000003d4
-#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_MSB 31
-#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_LSB 0
-#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_MASK 0xffffffff
-#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_ANALOG_CMAC_RESULTS_Q_ATE_CMAC_RESULTS_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for PMU1 */
-#define PHY_ANALOG_PMU1_ADDRESS 0x00000740
-#define PHY_ANALOG_PMU1_OFFSET 0x00000740
-#define PHY_ANALOG_PMU1_SPARE_MSB 10
-#define PHY_ANALOG_PMU1_SPARE_LSB 0
-#define PHY_ANALOG_PMU1_SPARE_MASK 0x000007ff
-#define PHY_ANALOG_PMU1_SPARE_GET(x) (((x) & 0x000007ff) >> 0)
-#define PHY_ANALOG_PMU1_SPARE_SET(x) (((x) << 0) & 0x000007ff)
-#define PHY_ANALOG_PMU1_OTP_V25_PWD_MSB 11
-#define PHY_ANALOG_PMU1_OTP_V25_PWD_LSB 11
-#define PHY_ANALOG_PMU1_OTP_V25_PWD_MASK 0x00000800
-#define PHY_ANALOG_PMU1_OTP_V25_PWD_GET(x) (((x) & 0x00000800) >> 11)
-#define PHY_ANALOG_PMU1_OTP_V25_PWD_SET(x) (((x) << 11) & 0x00000800)
-#define PHY_ANALOG_PMU1_PAREGON_MAN_MSB 12
-#define PHY_ANALOG_PMU1_PAREGON_MAN_LSB 12
-#define PHY_ANALOG_PMU1_PAREGON_MAN_MASK 0x00001000
-#define PHY_ANALOG_PMU1_PAREGON_MAN_GET(x) (((x) & 0x00001000) >> 12)
-#define PHY_ANALOG_PMU1_PAREGON_MAN_SET(x) (((x) << 12) & 0x00001000)
-#define PHY_ANALOG_PMU1_OTPREGON_MAN_MSB 13
-#define PHY_ANALOG_PMU1_OTPREGON_MAN_LSB 13
-#define PHY_ANALOG_PMU1_OTPREGON_MAN_MASK 0x00002000
-#define PHY_ANALOG_PMU1_OTPREGON_MAN_GET(x) (((x) & 0x00002000) >> 13)
-#define PHY_ANALOG_PMU1_OTPREGON_MAN_SET(x) (((x) << 13) & 0x00002000)
-#define PHY_ANALOG_PMU1_DREGON_MAN_MSB 14
-#define PHY_ANALOG_PMU1_DREGON_MAN_LSB 14
-#define PHY_ANALOG_PMU1_DREGON_MAN_MASK 0x00004000
-#define PHY_ANALOG_PMU1_DREGON_MAN_GET(x) (((x) & 0x00004000) >> 14)
-#define PHY_ANALOG_PMU1_DREGON_MAN_SET(x) (((x) << 14) & 0x00004000)
-#define PHY_ANALOG_PMU1_DISCONTMODEEN_MSB 15
-#define PHY_ANALOG_PMU1_DISCONTMODEEN_LSB 15
-#define PHY_ANALOG_PMU1_DISCONTMODEEN_MASK 0x00008000
-#define PHY_ANALOG_PMU1_DISCONTMODEEN_GET(x) (((x) & 0x00008000) >> 15)
-#define PHY_ANALOG_PMU1_DISCONTMODEEN_SET(x) (((x) << 15) & 0x00008000)
-#define PHY_ANALOG_PMU1_SWREGON_MAN_MSB 16
-#define PHY_ANALOG_PMU1_SWREGON_MAN_LSB 16
-#define PHY_ANALOG_PMU1_SWREGON_MAN_MASK 0x00010000
-#define PHY_ANALOG_PMU1_SWREGON_MAN_GET(x) (((x) & 0x00010000) >> 16)
-#define PHY_ANALOG_PMU1_SWREGON_MAN_SET(x) (((x) << 16) & 0x00010000)
-#define PHY_ANALOG_PMU1_SWREG_FREQCUR_MSB 18
-#define PHY_ANALOG_PMU1_SWREG_FREQCUR_LSB 17
-#define PHY_ANALOG_PMU1_SWREG_FREQCUR_MASK 0x00060000
-#define PHY_ANALOG_PMU1_SWREG_FREQCUR_GET(x) (((x) & 0x00060000) >> 17)
-#define PHY_ANALOG_PMU1_SWREG_FREQCUR_SET(x) (((x) << 17) & 0x00060000)
-#define PHY_ANALOG_PMU1_SWREG_FREQCAP_MSB 21
-#define PHY_ANALOG_PMU1_SWREG_FREQCAP_LSB 19
-#define PHY_ANALOG_PMU1_SWREG_FREQCAP_MASK 0x00380000
-#define PHY_ANALOG_PMU1_SWREG_FREQCAP_GET(x) (((x) & 0x00380000) >> 19)
-#define PHY_ANALOG_PMU1_SWREG_FREQCAP_SET(x) (((x) << 19) & 0x00380000)
-#define PHY_ANALOG_PMU1_SWREG_LVLCTR_MSB 23
-#define PHY_ANALOG_PMU1_SWREG_LVLCTR_LSB 22
-#define PHY_ANALOG_PMU1_SWREG_LVLCTR_MASK 0x00c00000
-#define PHY_ANALOG_PMU1_SWREG_LVLCTR_GET(x) (((x) & 0x00c00000) >> 22)
-#define PHY_ANALOG_PMU1_SWREG_LVLCTR_SET(x) (((x) << 22) & 0x00c00000)
-#define PHY_ANALOG_PMU1_SREG_LVLCTR_MSB 25
-#define PHY_ANALOG_PMU1_SREG_LVLCTR_LSB 24
-#define PHY_ANALOG_PMU1_SREG_LVLCTR_MASK 0x03000000
-#define PHY_ANALOG_PMU1_SREG_LVLCTR_GET(x) (((x) & 0x03000000) >> 24)
-#define PHY_ANALOG_PMU1_SREG_LVLCTR_SET(x) (((x) << 24) & 0x03000000)
-#define PHY_ANALOG_PMU1_DREG_LVLCTR_MSB 27
-#define PHY_ANALOG_PMU1_DREG_LVLCTR_LSB 26
-#define PHY_ANALOG_PMU1_DREG_LVLCTR_MASK 0x0c000000
-#define PHY_ANALOG_PMU1_DREG_LVLCTR_GET(x) (((x) & 0x0c000000) >> 26)
-#define PHY_ANALOG_PMU1_DREG_LVLCTR_SET(x) (((x) << 26) & 0x0c000000)
-#define PHY_ANALOG_PMU1_PAREG_XPNP_MSB 28
-#define PHY_ANALOG_PMU1_PAREG_XPNP_LSB 28
-#define PHY_ANALOG_PMU1_PAREG_XPNP_MASK 0x10000000
-#define PHY_ANALOG_PMU1_PAREG_XPNP_GET(x) (((x) & 0x10000000) >> 28)
-#define PHY_ANALOG_PMU1_PAREG_XPNP_SET(x) (((x) << 28) & 0x10000000)
-#define PHY_ANALOG_PMU1_PAREG_LVLCTR_MSB 31
-#define PHY_ANALOG_PMU1_PAREG_LVLCTR_LSB 29
-#define PHY_ANALOG_PMU1_PAREG_LVLCTR_MASK 0xe0000000
-#define PHY_ANALOG_PMU1_PAREG_LVLCTR_GET(x) (((x) & 0xe0000000) >> 29)
-#define PHY_ANALOG_PMU1_PAREG_LVLCTR_SET(x) (((x) << 29) & 0xe0000000)
-
-/* macros for PMU2 */
-#define PHY_ANALOG_PMU2_ADDRESS 0x00000744
-#define PHY_ANALOG_PMU2_OFFSET 0x00000744
-#define PHY_ANALOG_PMU2_SPARE_MSB 7
-#define PHY_ANALOG_PMU2_SPARE_LSB 0
-#define PHY_ANALOG_PMU2_SPARE_MASK 0x000000ff
-#define PHY_ANALOG_PMU2_SPARE_GET(x) (((x) & 0x000000ff) >> 0)
-#define PHY_ANALOG_PMU2_SPARE_SET(x) (((x) << 0) & 0x000000ff)
-#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_MSB 8
-#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_LSB 8
-#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_MASK 0x00000100
-#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_GET(x) (((x) & 0x00000100) >> 8)
-#define PHY_ANALOG_PMU2_VBATT_1_3TOATB_SET(x) (((x) << 8) & 0x00000100)
-#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_MSB 9
-#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_LSB 9
-#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_MASK 0x00000200
-#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_GET(x) (((x) & 0x00000200) >> 9)
-#define PHY_ANALOG_PMU2_VBATT_1_2TOATB_SET(x) (((x) << 9) & 0x00000200)
-#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_MSB 10
-#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_LSB 10
-#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_MASK 0x00000400
-#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_GET(x) (((x) & 0x00000400) >> 10)
-#define PHY_ANALOG_PMU2_VBATT_2_3TOATB_SET(x) (((x) << 10) & 0x00000400)
-#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_MSB 11
-#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_LSB 11
-#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_MASK 0x00000800
-#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_GET(x) (((x) & 0x00000800) >> 11)
-#define PHY_ANALOG_PMU2_PWD_BANDGAP_MAN_SET(x) (((x) << 11) & 0x00000800)
-#define PHY_ANALOG_PMU2_PWD_LFO_MAN_MSB 12
-#define PHY_ANALOG_PMU2_PWD_LFO_MAN_LSB 12
-#define PHY_ANALOG_PMU2_PWD_LFO_MAN_MASK 0x00001000
-#define PHY_ANALOG_PMU2_PWD_LFO_MAN_GET(x) (((x) & 0x00001000) >> 12)
-#define PHY_ANALOG_PMU2_PWD_LFO_MAN_SET(x) (((x) << 12) & 0x00001000)
-#define PHY_ANALOG_PMU2_VBATT_LT_3P2_MSB 13
-#define PHY_ANALOG_PMU2_VBATT_LT_3P2_LSB 13
-#define PHY_ANALOG_PMU2_VBATT_LT_3P2_MASK 0x00002000
-#define PHY_ANALOG_PMU2_VBATT_LT_3P2_GET(x) (((x) & 0x00002000) >> 13)
-#define PHY_ANALOG_PMU2_VBATT_LT_3P2_SET(x) (((x) << 13) & 0x00002000)
-#define PHY_ANALOG_PMU2_VBATT_LT_2P8_MSB 14
-#define PHY_ANALOG_PMU2_VBATT_LT_2P8_LSB 14
-#define PHY_ANALOG_PMU2_VBATT_LT_2P8_MASK 0x00004000
-#define PHY_ANALOG_PMU2_VBATT_LT_2P8_GET(x) (((x) & 0x00004000) >> 14)
-#define PHY_ANALOG_PMU2_VBATT_LT_2P8_SET(x) (((x) << 14) & 0x00004000)
-#define PHY_ANALOG_PMU2_VBATT_GT_4P2_MSB 15
-#define PHY_ANALOG_PMU2_VBATT_GT_4P2_LSB 15
-#define PHY_ANALOG_PMU2_VBATT_GT_4P2_MASK 0x00008000
-#define PHY_ANALOG_PMU2_VBATT_GT_4P2_GET(x) (((x) & 0x00008000) >> 15)
-#define PHY_ANALOG_PMU2_VBATT_GT_4P2_SET(x) (((x) << 15) & 0x00008000)
-#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_MSB 16
-#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_LSB 16
-#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_MASK 0x00010000
-#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_GET(x) (((x) & 0x00010000) >> 16)
-#define PHY_ANALOG_PMU2_PMU_MAN_OVERRIDE_EN_SET(x) (((x) << 16) & 0x00010000)
-#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_MSB 18
-#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_LSB 17
-#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_MASK 0x00060000
-#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_GET(x) (((x) & 0x00060000) >> 17)
-#define PHY_ANALOG_PMU2_VBATT_GT_LVLCTR_SET(x) (((x) << 17) & 0x00060000)
-#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_MSB 19
-#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_LSB 19
-#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_MASK 0x00080000
-#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_GET(x) (((x) & 0x00080000) >> 19)
-#define PHY_ANALOG_PMU2_SWREGVSSL2ATB_SET(x) (((x) << 19) & 0x00080000)
-#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_MSB 21
-#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_LSB 20
-#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_MASK 0x00300000
-#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_GET(x) (((x) & 0x00300000) >> 20)
-#define PHY_ANALOG_PMU2_SWREGVSSL_LVLCTR_SET(x) (((x) << 20) & 0x00300000)
-#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_MSB 22
-#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_LSB 22
-#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_MASK 0x00400000
-#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_GET(x) (((x) & 0x00400000) >> 22)
-#define PHY_ANALOG_PMU2_SWREGVDDH2ATB_SET(x) (((x) << 22) & 0x00400000)
-#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_MSB 24
-#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_LSB 23
-#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_MASK 0x01800000
-#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_GET(x) (((x) & 0x01800000) >> 23)
-#define PHY_ANALOG_PMU2_SWREGVDDH_LVLCTR_SET(x) (((x) << 23) & 0x01800000)
-#define PHY_ANALOG_PMU2_SWREG2ATB_MSB 27
-#define PHY_ANALOG_PMU2_SWREG2ATB_LSB 25
-#define PHY_ANALOG_PMU2_SWREG2ATB_MASK 0x0e000000
-#define PHY_ANALOG_PMU2_SWREG2ATB_GET(x) (((x) & 0x0e000000) >> 25)
-#define PHY_ANALOG_PMU2_SWREG2ATB_SET(x) (((x) << 25) & 0x0e000000)
-#define PHY_ANALOG_PMU2_OTPREG2ATB_MSB 28
-#define PHY_ANALOG_PMU2_OTPREG2ATB_LSB 28
-#define PHY_ANALOG_PMU2_OTPREG2ATB_MASK 0x10000000
-#define PHY_ANALOG_PMU2_OTPREG2ATB_GET(x) (((x) & 0x10000000) >> 28)
-#define PHY_ANALOG_PMU2_OTPREG2ATB_SET(x) (((x) << 28) & 0x10000000)
-#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_MSB 30
-#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_LSB 29
-#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_MASK 0x60000000
-#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_GET(x) (((x) & 0x60000000) >> 29)
-#define PHY_ANALOG_PMU2_OTPREG_LVLCTR_SET(x) (((x) << 29) & 0x60000000)
-#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_MSB 31
-#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_LSB 31
-#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_MASK 0x80000000
-#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_GET(x) (((x) & 0x80000000) >> 31)
-#define PHY_ANALOG_PMU2_DREG_LVLCTR_MANOVR_EN_SET(x) (((x) << 31) & 0x80000000)
-
-
-#ifndef __ASSEMBLER__
-
-typedef struct analog_intf_athr_wlan_reg_reg_s {
- volatile unsigned int RXRF_BIAS1; /* 0x0 - 0x4 */
- volatile unsigned int RXRF_BIAS2; /* 0x4 - 0x8 */
- volatile unsigned int RXRF_GAINSTAGES; /* 0x8 - 0xc */
- volatile unsigned int RXRF_AGC; /* 0xc - 0x10 */
- volatile char pad__0[0x30]; /* 0x10 - 0x40 */
- volatile unsigned int TXRF1; /* 0x40 - 0x44 */
- volatile unsigned int TXRF2; /* 0x44 - 0x48 */
- volatile unsigned int TXRF3; /* 0x48 - 0x4c */
- volatile unsigned int TXRF4; /* 0x4c - 0x50 */
- volatile unsigned int TXRF5; /* 0x50 - 0x54 */
- volatile unsigned int TXRF6; /* 0x54 - 0x58 */
- volatile unsigned int TXRF7; /* 0x58 - 0x5c */
- volatile unsigned int TXRF8; /* 0x5c - 0x60 */
- volatile unsigned int TXRF9; /* 0x60 - 0x64 */
- volatile unsigned int TXRF10; /* 0x64 - 0x68 */
- volatile unsigned int TXRF11; /* 0x68 - 0x6c */
- volatile unsigned int TXRF12; /* 0x6c - 0x70 */
- volatile char pad__1[0x10]; /* 0x70 - 0x80 */
- volatile unsigned int SYNTH1; /* 0x80 - 0x84 */
- volatile unsigned int SYNTH2; /* 0x84 - 0x88 */
- volatile unsigned int SYNTH3; /* 0x88 - 0x8c */
- volatile unsigned int SYNTH4; /* 0x8c - 0x90 */
- volatile unsigned int SYNTH5; /* 0x90 - 0x94 */
- volatile unsigned int SYNTH6; /* 0x94 - 0x98 */
- volatile unsigned int SYNTH7; /* 0x98 - 0x9c */
- volatile unsigned int SYNTH8; /* 0x9c - 0xa0 */
- volatile unsigned int SYNTH9; /* 0xa0 - 0xa4 */
- volatile unsigned int SYNTH10; /* 0xa4 - 0xa8 */
- volatile unsigned int SYNTH11; /* 0xa8 - 0xac */
- volatile unsigned int SYNTH12; /* 0xac - 0xb0 */
- volatile unsigned int SYNTH13; /* 0xb0 - 0xb4 */
- volatile unsigned int SYNTH14; /* 0xb4 - 0xb8 */
- volatile char pad__2[0x8]; /* 0xb8 - 0xc0 */
- volatile unsigned int BIAS1; /* 0xc0 - 0xc4 */
- volatile unsigned int BIAS2; /* 0xc4 - 0xc8 */
- volatile unsigned int BIAS3; /* 0xc8 - 0xcc */
- volatile unsigned int BIAS4; /* 0xcc - 0xd0 */
- volatile char pad__3[0x30]; /* 0xd0 - 0x100 */
- volatile unsigned int RXTX1; /* 0x100 - 0x104 */
- volatile unsigned int RXTX2; /* 0x104 - 0x108 */
- volatile unsigned int RXTX3; /* 0x108 - 0x10c */
- volatile char pad__4[0x34]; /* 0x10c - 0x140 */
- volatile unsigned int BB1; /* 0x140 - 0x144 */
- volatile unsigned int BB2; /* 0x144 - 0x148 */
- volatile unsigned int BB3; /* 0x148 - 0x14c */
- volatile char pad__5[0x134]; /* 0x14c - 0x280 */
- volatile unsigned int PLLCLKMODA; /* 0x280 - 0x284 */
- volatile unsigned int PLLCLKMODA2; /* 0x284 - 0x288 */
- volatile unsigned int TOP; /* 0x288 - 0x28c */
- volatile unsigned int THERM; /* 0x28c - 0x290 */
- volatile unsigned int XTAL; /* 0x290 - 0x294 */
- volatile char pad__6[0xec]; /* 0x294 - 0x380 */
- volatile unsigned int rbist_cntrl; /* 0x380 - 0x384 */
- volatile unsigned int tx_dc_offset; /* 0x384 - 0x388 */
- volatile unsigned int tx_tonegen0; /* 0x388 - 0x38c */
- volatile unsigned int tx_tonegen1; /* 0x38c - 0x390 */
- volatile unsigned int tx_lftonegen0; /* 0x390 - 0x394 */
- volatile unsigned int tx_linear_ramp_i; /* 0x394 - 0x398 */
- volatile unsigned int tx_linear_ramp_q; /* 0x398 - 0x39c */
- volatile unsigned int tx_prbs_mag; /* 0x39c - 0x3a0 */
- volatile unsigned int tx_prbs_seed_i; /* 0x3a0 - 0x3a4 */
- volatile unsigned int tx_prbs_seed_q; /* 0x3a4 - 0x3a8 */
- volatile unsigned int cmac_dc_cancel; /* 0x3a8 - 0x3ac */
- volatile unsigned int cmac_dc_offset; /* 0x3ac - 0x3b0 */
- volatile unsigned int cmac_corr; /* 0x3b0 - 0x3b4 */
- volatile unsigned int cmac_power; /* 0x3b4 - 0x3b8 */
- volatile unsigned int cmac_cross_corr; /* 0x3b8 - 0x3bc */
- volatile unsigned int cmac_i2q2; /* 0x3bc - 0x3c0 */
- volatile unsigned int cmac_power_hpf; /* 0x3c0 - 0x3c4 */
- volatile unsigned int rxdac_set1; /* 0x3c4 - 0x3c8 */
- volatile unsigned int rxdac_set2; /* 0x3c8 - 0x3cc */
- volatile unsigned int rxdac_long_shift; /* 0x3cc - 0x3d0 */
- volatile unsigned int cmac_results_i; /* 0x3d0 - 0x3d4 */
- volatile unsigned int cmac_results_q; /* 0x3d4 - 0x3d8 */
- volatile char pad__7[0x368]; /* 0x3d8 - 0x740 */
- volatile unsigned int PMU1; /* 0x740 - 0x744 */
- volatile unsigned int PMU2; /* 0x744 - 0x748 */
-} analog_intf_athr_wlan_reg_reg_t;
-
-#endif /* __ASSEMBLER__ */
-
-#endif /* _ANALOG_INTF_ATHR_WLAN_REG_REG_H_ */
diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/analog_intf_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/analog_intf_reg.h
deleted file mode 100644
index 01b9eb5..0000000
--- a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/analog_intf_reg.h
+++ /dev/null
@@ -1,37 +0,0 @@
-// ------------------------------------------------------------------
-// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
-//
-//
-// Permission to use, copy, modify, and/or distribute this software for any
-// purpose with or without fee is hereby granted, provided that the above
-// copyright notice and this permission notice appear in all copies.
-//
-// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-//
-//
-// ------------------------------------------------------------------
-//===================================================================
-// Author(s): ="Atheros"
-//===================================================================
-
-
-#ifdef WLAN_HEADERS
-
-#include "analog_intf_athr_wlan_reg.h"
-
-
-#ifndef BT_HEADERS
-
-
-
-#endif
-#endif
-
-
-
diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/apb_map.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/apb_map.h
index e4d2d62..0068ca3 100644
--- a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/apb_map.h
+++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/apb_map.h
@@ -21,11 +21,8 @@
//===================================================================
-#ifdef WLAN_HEADERS
-
#include "apb_athr_wlan_map.h"
-
#ifndef BT_HEADERS
#define RTC_BASE_ADDRESS WLAN_RTC_BASE_ADDRESS
@@ -40,9 +37,4 @@
#define MAC_BASE_ADDRESS WLAN_MAC_BASE_ADDRESS
#define RDMA_BASE_ADDRESS WLAN_RDMA_BASE_ADDRESS
-
#endif
-#endif
-
-
-
diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/bb_lc_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/bb_lc_reg.h
deleted file mode 100644
index 2711929..0000000
--- a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/bb_lc_reg.h
+++ /dev/null
@@ -1,7076 +0,0 @@
-// ------------------------------------------------------------------
-// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
-//
-//
-// Permission to use, copy, modify, and/or distribute this software for any
-// purpose with or without fee is hereby granted, provided that the above
-// copyright notice and this permission notice appear in all copies.
-//
-// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-//
-//
-// ------------------------------------------------------------------
-//===================================================================
-// Author(s): ="Atheros"
-//===================================================================
-
-/* Copyright (C) 2009 Denali Software Inc. All rights reserved */
-/* THIS FILE IS AUTOMATICALLY GENERATED BY DENALI BLUEPRINT, DO NOT EDIT */
-
-
-#ifndef _BB_LC_REG_REG_H_
-#define _BB_LC_REG_REG_H_
-
-
-/* macros for BB_test_controls */
-#define PHY_BB_TEST_CONTROLS_ADDRESS 0x00009800
-#define PHY_BB_TEST_CONTROLS_OFFSET 0x00009800
-#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_SEL_MSB 3
-#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_SEL_LSB 0
-#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_SEL_MASK 0x0000000f
-#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_SEL_GET(x) (((x) & 0x0000000f) >> 0)
-#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_SEL_SET(x) (((x) << 0) & 0x0000000f)
-#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_MSB 4
-#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_LSB 4
-#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_MASK 0x00000010
-#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_GET(x) (((x) & 0x00000010) >> 4)
-#define PHY_BB_TEST_CONTROLS_CF_TSTTRIG_SET(x) (((x) << 4) & 0x00000010)
-#define PHY_BB_TEST_CONTROLS_CF_RFSHIFT_SEL_MSB 6
-#define PHY_BB_TEST_CONTROLS_CF_RFSHIFT_SEL_LSB 5
-#define PHY_BB_TEST_CONTROLS_CF_RFSHIFT_SEL_MASK 0x00000060
-#define PHY_BB_TEST_CONTROLS_CF_RFSHIFT_SEL_GET(x) (((x) & 0x00000060) >> 5)
-#define PHY_BB_TEST_CONTROLS_CF_RFSHIFT_SEL_SET(x) (((x) << 5) & 0x00000060)
-#define PHY_BB_TEST_CONTROLS_CARDBUS_MODE_MSB 9
-#define PHY_BB_TEST_CONTROLS_CARDBUS_MODE_LSB 8
-#define PHY_BB_TEST_CONTROLS_CARDBUS_MODE_MASK 0x00000300
-#define PHY_BB_TEST_CONTROLS_CARDBUS_MODE_GET(x) (((x) & 0x00000300) >> 8)
-#define PHY_BB_TEST_CONTROLS_CARDBUS_MODE_SET(x) (((x) << 8) & 0x00000300)
-#define PHY_BB_TEST_CONTROLS_CLKOUT_IS_CLK32_MSB 10
-#define PHY_BB_TEST_CONTROLS_CLKOUT_IS_CLK32_LSB 10
-#define PHY_BB_TEST_CONTROLS_CLKOUT_IS_CLK32_MASK 0x00000400
-#define PHY_BB_TEST_CONTROLS_CLKOUT_IS_CLK32_GET(x) (((x) & 0x00000400) >> 10)
-#define PHY_BB_TEST_CONTROLS_CLKOUT_IS_CLK32_SET(x) (((x) << 10) & 0x00000400)
-#define PHY_BB_TEST_CONTROLS_ENABLE_RFSILENT_BB_MSB 13
-#define PHY_BB_TEST_CONTROLS_ENABLE_RFSILENT_BB_LSB 13
-#define PHY_BB_TEST_CONTROLS_ENABLE_RFSILENT_BB_MASK 0x00002000
-#define PHY_BB_TEST_CONTROLS_ENABLE_RFSILENT_BB_GET(x) (((x) & 0x00002000) >> 13)
-#define PHY_BB_TEST_CONTROLS_ENABLE_RFSILENT_BB_SET(x) (((x) << 13) & 0x00002000)
-#define PHY_BB_TEST_CONTROLS_ENABLE_MINI_OBS_MSB 15
-#define PHY_BB_TEST_CONTROLS_ENABLE_MINI_OBS_LSB 15
-#define PHY_BB_TEST_CONTROLS_ENABLE_MINI_OBS_MASK 0x00008000
-#define PHY_BB_TEST_CONTROLS_ENABLE_MINI_OBS_GET(x) (((x) & 0x00008000) >> 15)
-#define PHY_BB_TEST_CONTROLS_ENABLE_MINI_OBS_SET(x) (((x) << 15) & 0x00008000)
-#define PHY_BB_TEST_CONTROLS_SLOW_CLK160_MSB 17
-#define PHY_BB_TEST_CONTROLS_SLOW_CLK160_LSB 17
-#define PHY_BB_TEST_CONTROLS_SLOW_CLK160_MASK 0x00020000
-#define PHY_BB_TEST_CONTROLS_SLOW_CLK160_GET(x) (((x) & 0x00020000) >> 17)
-#define PHY_BB_TEST_CONTROLS_SLOW_CLK160_SET(x) (((x) << 17) & 0x00020000)
-#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_3_MSB 18
-#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_3_LSB 18
-#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_3_MASK 0x00040000
-#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_3_GET(x) (((x) & 0x00040000) >> 18)
-#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_3_SET(x) (((x) << 18) & 0x00040000)
-#define PHY_BB_TEST_CONTROLS_CF_BBB_OBS_SEL_MSB 22
-#define PHY_BB_TEST_CONTROLS_CF_BBB_OBS_SEL_LSB 19
-#define PHY_BB_TEST_CONTROLS_CF_BBB_OBS_SEL_MASK 0x00780000
-#define PHY_BB_TEST_CONTROLS_CF_BBB_OBS_SEL_GET(x) (((x) & 0x00780000) >> 19)
-#define PHY_BB_TEST_CONTROLS_CF_BBB_OBS_SEL_SET(x) (((x) << 19) & 0x00780000)
-#define PHY_BB_TEST_CONTROLS_RX_OBS_SEL_5TH_BIT_MSB 23
-#define PHY_BB_TEST_CONTROLS_RX_OBS_SEL_5TH_BIT_LSB 23
-#define PHY_BB_TEST_CONTROLS_RX_OBS_SEL_5TH_BIT_MASK 0x00800000
-#define PHY_BB_TEST_CONTROLS_RX_OBS_SEL_5TH_BIT_GET(x) (((x) & 0x00800000) >> 23)
-#define PHY_BB_TEST_CONTROLS_RX_OBS_SEL_5TH_BIT_SET(x) (((x) << 23) & 0x00800000)
-#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_4_MSB 24
-#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_4_LSB 24
-#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_4_MASK 0x01000000
-#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_4_GET(x) (((x) & 0x01000000) >> 24)
-#define PHY_BB_TEST_CONTROLS_AGC_OBS_SEL_4_SET(x) (((x) << 24) & 0x01000000)
-#define PHY_BB_TEST_CONTROLS_FORCE_AGC_CLEAR_MSB 28
-#define PHY_BB_TEST_CONTROLS_FORCE_AGC_CLEAR_LSB 28
-#define PHY_BB_TEST_CONTROLS_FORCE_AGC_CLEAR_MASK 0x10000000
-#define PHY_BB_TEST_CONTROLS_FORCE_AGC_CLEAR_GET(x) (((x) & 0x10000000) >> 28)
-#define PHY_BB_TEST_CONTROLS_FORCE_AGC_CLEAR_SET(x) (((x) << 28) & 0x10000000)
-#define PHY_BB_TEST_CONTROLS_TSTDAC_OUT_SEL_MSB 31
-#define PHY_BB_TEST_CONTROLS_TSTDAC_OUT_SEL_LSB 30
-#define PHY_BB_TEST_CONTROLS_TSTDAC_OUT_SEL_MASK 0xc0000000
-#define PHY_BB_TEST_CONTROLS_TSTDAC_OUT_SEL_GET(x) (((x) & 0xc0000000) >> 30)
-#define PHY_BB_TEST_CONTROLS_TSTDAC_OUT_SEL_SET(x) (((x) << 30) & 0xc0000000)
-
-/* macros for BB_gen_controls */
-#define PHY_BB_GEN_CONTROLS_ADDRESS 0x00009804
-#define PHY_BB_GEN_CONTROLS_OFFSET 0x00009804
-#define PHY_BB_GEN_CONTROLS_TURBO_MSB 0
-#define PHY_BB_GEN_CONTROLS_TURBO_LSB 0
-#define PHY_BB_GEN_CONTROLS_TURBO_MASK 0x00000001
-#define PHY_BB_GEN_CONTROLS_TURBO_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_BB_GEN_CONTROLS_TURBO_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_BB_GEN_CONTROLS_CF_SHORT20_MSB 1
-#define PHY_BB_GEN_CONTROLS_CF_SHORT20_LSB 1
-#define PHY_BB_GEN_CONTROLS_CF_SHORT20_MASK 0x00000002
-#define PHY_BB_GEN_CONTROLS_CF_SHORT20_GET(x) (((x) & 0x00000002) >> 1)
-#define PHY_BB_GEN_CONTROLS_CF_SHORT20_SET(x) (((x) << 1) & 0x00000002)
-#define PHY_BB_GEN_CONTROLS_DYN_20_40_MSB 2
-#define PHY_BB_GEN_CONTROLS_DYN_20_40_LSB 2
-#define PHY_BB_GEN_CONTROLS_DYN_20_40_MASK 0x00000004
-#define PHY_BB_GEN_CONTROLS_DYN_20_40_GET(x) (((x) & 0x00000004) >> 2)
-#define PHY_BB_GEN_CONTROLS_DYN_20_40_SET(x) (((x) << 2) & 0x00000004)
-#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_ONLY_MSB 3
-#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_ONLY_LSB 3
-#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_ONLY_MASK 0x00000008
-#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_ONLY_GET(x) (((x) & 0x00000008) >> 3)
-#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_ONLY_SET(x) (((x) << 3) & 0x00000008)
-#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_CHN_MSB 4
-#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_CHN_LSB 4
-#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_CHN_MASK 0x00000010
-#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_CHN_GET(x) (((x) & 0x00000010) >> 4)
-#define PHY_BB_GEN_CONTROLS_DYN_20_40_PRI_CHN_SET(x) (((x) << 4) & 0x00000010)
-#define PHY_BB_GEN_CONTROLS_DYN_20_40_EXT_CHN_MSB 5
-#define PHY_BB_GEN_CONTROLS_DYN_20_40_EXT_CHN_LSB 5
-#define PHY_BB_GEN_CONTROLS_DYN_20_40_EXT_CHN_MASK 0x00000020
-#define PHY_BB_GEN_CONTROLS_DYN_20_40_EXT_CHN_GET(x) (((x) & 0x00000020) >> 5)
-#define PHY_BB_GEN_CONTROLS_DYN_20_40_EXT_CHN_SET(x) (((x) << 5) & 0x00000020)
-#define PHY_BB_GEN_CONTROLS_HT_ENABLE_MSB 6
-#define PHY_BB_GEN_CONTROLS_HT_ENABLE_LSB 6
-#define PHY_BB_GEN_CONTROLS_HT_ENABLE_MASK 0x00000040
-#define PHY_BB_GEN_CONTROLS_HT_ENABLE_GET(x) (((x) & 0x00000040) >> 6)
-#define PHY_BB_GEN_CONTROLS_HT_ENABLE_SET(x) (((x) << 6) & 0x00000040)
-#define PHY_BB_GEN_CONTROLS_ALLOW_SHORT_GI_MSB 7
-#define PHY_BB_GEN_CONTROLS_ALLOW_SHORT_GI_LSB 7
-#define PHY_BB_GEN_CONTROLS_ALLOW_SHORT_GI_MASK 0x00000080
-#define PHY_BB_GEN_CONTROLS_ALLOW_SHORT_GI_GET(x) (((x) & 0x00000080) >> 7)
-#define PHY_BB_GEN_CONTROLS_ALLOW_SHORT_GI_SET(x) (((x) << 7) & 0x00000080)
-#define PHY_BB_GEN_CONTROLS_CF_2_CHAINS_USE_WALSH_MSB 8
-#define PHY_BB_GEN_CONTROLS_CF_2_CHAINS_USE_WALSH_LSB 8
-#define PHY_BB_GEN_CONTROLS_CF_2_CHAINS_USE_WALSH_MASK 0x00000100
-#define PHY_BB_GEN_CONTROLS_CF_2_CHAINS_USE_WALSH_GET(x) (((x) & 0x00000100) >> 8)
-#define PHY_BB_GEN_CONTROLS_CF_2_CHAINS_USE_WALSH_SET(x) (((x) << 8) & 0x00000100)
-#define PHY_BB_GEN_CONTROLS_CF_SINGLE_HT_LTF1_MSB 9
-#define PHY_BB_GEN_CONTROLS_CF_SINGLE_HT_LTF1_LSB 9
-#define PHY_BB_GEN_CONTROLS_CF_SINGLE_HT_LTF1_MASK 0x00000200
-#define PHY_BB_GEN_CONTROLS_CF_SINGLE_HT_LTF1_GET(x) (((x) & 0x00000200) >> 9)
-#define PHY_BB_GEN_CONTROLS_CF_SINGLE_HT_LTF1_SET(x) (((x) << 9) & 0x00000200)
-#define PHY_BB_GEN_CONTROLS_GF_ENABLE_MSB 10
-#define PHY_BB_GEN_CONTROLS_GF_ENABLE_LSB 10
-#define PHY_BB_GEN_CONTROLS_GF_ENABLE_MASK 0x00000400
-#define PHY_BB_GEN_CONTROLS_GF_ENABLE_GET(x) (((x) & 0x00000400) >> 10)
-#define PHY_BB_GEN_CONTROLS_GF_ENABLE_SET(x) (((x) << 10) & 0x00000400)
-#define PHY_BB_GEN_CONTROLS_BYPASS_DAC_FIFO_N_MSB 11
-#define PHY_BB_GEN_CONTROLS_BYPASS_DAC_FIFO_N_LSB 11
-#define PHY_BB_GEN_CONTROLS_BYPASS_DAC_FIFO_N_MASK 0x00000800
-#define PHY_BB_GEN_CONTROLS_BYPASS_DAC_FIFO_N_GET(x) (((x) & 0x00000800) >> 11)
-#define PHY_BB_GEN_CONTROLS_BYPASS_DAC_FIFO_N_SET(x) (((x) << 11) & 0x00000800)
-
-/* macros for BB_test_controls_status */
-#define PHY_BB_TEST_CONTROLS_STATUS_ADDRESS 0x00009808
-#define PHY_BB_TEST_CONTROLS_STATUS_OFFSET 0x00009808
-#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTDAC_EN_MSB 0
-#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTDAC_EN_LSB 0
-#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTDAC_EN_MASK 0x00000001
-#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTDAC_EN_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTDAC_EN_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_IS_TSTDAC_MSB 1
-#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_IS_TSTDAC_LSB 1
-#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_IS_TSTDAC_MASK 0x00000002
-#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_IS_TSTDAC_GET(x) (((x) & 0x00000002) >> 1)
-#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_IS_TSTDAC_SET(x) (((x) << 1) & 0x00000002)
-#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_SEL_MSB 4
-#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_SEL_LSB 2
-#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_SEL_MASK 0x0000001c
-#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_SEL_GET(x) (((x) & 0x0000001c) >> 2)
-#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_SEL_SET(x) (((x) << 2) & 0x0000001c)
-#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_MUX_SEL_MSB 6
-#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_MUX_SEL_LSB 5
-#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_MUX_SEL_MASK 0x00000060
-#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_MUX_SEL_GET(x) (((x) & 0x00000060) >> 5)
-#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_OBS_MUX_SEL_SET(x) (((x) << 5) & 0x00000060)
-#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_ALTERNATE_MSB 7
-#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_ALTERNATE_LSB 7
-#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_ALTERNATE_MASK 0x00000080
-#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_ALTERNATE_GET(x) (((x) & 0x00000080) >> 7)
-#define PHY_BB_TEST_CONTROLS_STATUS_CF_TX_SRC_ALTERNATE_SET(x) (((x) << 7) & 0x00000080)
-#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTADC_EN_MSB 8
-#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTADC_EN_LSB 8
-#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTADC_EN_MASK 0x00000100
-#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTADC_EN_GET(x) (((x) & 0x00000100) >> 8)
-#define PHY_BB_TEST_CONTROLS_STATUS_CF_TSTADC_EN_SET(x) (((x) << 8) & 0x00000100)
-#define PHY_BB_TEST_CONTROLS_STATUS_CF_RX_SRC_IS_TSTADC_MSB 9
-#define PHY_BB_TEST_CONTROLS_STATUS_CF_RX_SRC_IS_TSTADC_LSB 9
-#define PHY_BB_TEST_CONTROLS_STATUS_CF_RX_SRC_IS_TSTADC_MASK 0x00000200
-#define PHY_BB_TEST_CONTROLS_STATUS_CF_RX_SRC_IS_TSTADC_GET(x) (((x) & 0x00000200) >> 9)
-#define PHY_BB_TEST_CONTROLS_STATUS_CF_RX_SRC_IS_TSTADC_SET(x) (((x) << 9) & 0x00000200)
-#define PHY_BB_TEST_CONTROLS_STATUS_RX_OBS_SEL_MSB 13
-#define PHY_BB_TEST_CONTROLS_STATUS_RX_OBS_SEL_LSB 10
-#define PHY_BB_TEST_CONTROLS_STATUS_RX_OBS_SEL_MASK 0x00003c00
-#define PHY_BB_TEST_CONTROLS_STATUS_RX_OBS_SEL_GET(x) (((x) & 0x00003c00) >> 10)
-#define PHY_BB_TEST_CONTROLS_STATUS_RX_OBS_SEL_SET(x) (((x) << 10) & 0x00003c00)
-#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_A2_WARM_RESET_MSB 14
-#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_A2_WARM_RESET_LSB 14
-#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_A2_WARM_RESET_MASK 0x00004000
-#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_A2_WARM_RESET_GET(x) (((x) & 0x00004000) >> 14)
-#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_A2_WARM_RESET_SET(x) (((x) << 14) & 0x00004000)
-#define PHY_BB_TEST_CONTROLS_STATUS_RESET_A2_MSB 15
-#define PHY_BB_TEST_CONTROLS_STATUS_RESET_A2_LSB 15
-#define PHY_BB_TEST_CONTROLS_STATUS_RESET_A2_MASK 0x00008000
-#define PHY_BB_TEST_CONTROLS_STATUS_RESET_A2_GET(x) (((x) & 0x00008000) >> 15)
-#define PHY_BB_TEST_CONTROLS_STATUS_RESET_A2_SET(x) (((x) << 15) & 0x00008000)
-#define PHY_BB_TEST_CONTROLS_STATUS_AGC_OBS_SEL_MSB 18
-#define PHY_BB_TEST_CONTROLS_STATUS_AGC_OBS_SEL_LSB 16
-#define PHY_BB_TEST_CONTROLS_STATUS_AGC_OBS_SEL_MASK 0x00070000
-#define PHY_BB_TEST_CONTROLS_STATUS_AGC_OBS_SEL_GET(x) (((x) & 0x00070000) >> 16)
-#define PHY_BB_TEST_CONTROLS_STATUS_AGC_OBS_SEL_SET(x) (((x) << 16) & 0x00070000)
-#define PHY_BB_TEST_CONTROLS_STATUS_CF_ENABLE_FFT_DUMP_MSB 19
-#define PHY_BB_TEST_CONTROLS_STATUS_CF_ENABLE_FFT_DUMP_LSB 19
-#define PHY_BB_TEST_CONTROLS_STATUS_CF_ENABLE_FFT_DUMP_MASK 0x00080000
-#define PHY_BB_TEST_CONTROLS_STATUS_CF_ENABLE_FFT_DUMP_GET(x) (((x) & 0x00080000) >> 19)
-#define PHY_BB_TEST_CONTROLS_STATUS_CF_ENABLE_FFT_DUMP_SET(x) (((x) << 19) & 0x00080000)
-#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_IN_MSB 23
-#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_IN_LSB 23
-#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_IN_MASK 0x00800000
-#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_IN_GET(x) (((x) & 0x00800000) >> 23)
-#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_IN_SET(x) (((x) << 23) & 0x00800000)
-#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_AGC_TO_A2_MSB 27
-#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_AGC_TO_A2_LSB 27
-#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_AGC_TO_A2_MASK 0x08000000
-#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_AGC_TO_A2_GET(x) (((x) & 0x08000000) >> 27)
-#define PHY_BB_TEST_CONTROLS_STATUS_DISABLE_AGC_TO_A2_SET(x) (((x) << 27) & 0x08000000)
-#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_EN_MSB 28
-#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_EN_LSB 28
-#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_EN_MASK 0x10000000
-#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_EN_GET(x) (((x) & 0x10000000) >> 28)
-#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_EN_SET(x) (((x) << 28) & 0x10000000)
-#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_SEL_MSB 30
-#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_SEL_LSB 29
-#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_SEL_MASK 0x60000000
-#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_SEL_GET(x) (((x) & 0x60000000) >> 29)
-#define PHY_BB_TEST_CONTROLS_STATUS_CF_DEBUGPORT_SEL_SET(x) (((x) << 29) & 0x60000000)
-
-/* macros for BB_timing_controls_1 */
-#define PHY_BB_TIMING_CONTROLS_1_ADDRESS 0x0000980c
-#define PHY_BB_TIMING_CONTROLS_1_OFFSET 0x0000980c
-#define PHY_BB_TIMING_CONTROLS_1_STE_THR_MSB 6
-#define PHY_BB_TIMING_CONTROLS_1_STE_THR_LSB 0
-#define PHY_BB_TIMING_CONTROLS_1_STE_THR_MASK 0x0000007f
-#define PHY_BB_TIMING_CONTROLS_1_STE_THR_GET(x) (((x) & 0x0000007f) >> 0)
-#define PHY_BB_TIMING_CONTROLS_1_STE_THR_SET(x) (((x) << 0) & 0x0000007f)
-#define PHY_BB_TIMING_CONTROLS_1_STE_TO_LONG1_MSB 12
-#define PHY_BB_TIMING_CONTROLS_1_STE_TO_LONG1_LSB 7
-#define PHY_BB_TIMING_CONTROLS_1_STE_TO_LONG1_MASK 0x00001f80
-#define PHY_BB_TIMING_CONTROLS_1_STE_TO_LONG1_GET(x) (((x) & 0x00001f80) >> 7)
-#define PHY_BB_TIMING_CONTROLS_1_STE_TO_LONG1_SET(x) (((x) << 7) & 0x00001f80)
-#define PHY_BB_TIMING_CONTROLS_1_TIMING_BACKOFF_MSB 16
-#define PHY_BB_TIMING_CONTROLS_1_TIMING_BACKOFF_LSB 13
-#define PHY_BB_TIMING_CONTROLS_1_TIMING_BACKOFF_MASK 0x0001e000
-#define PHY_BB_TIMING_CONTROLS_1_TIMING_BACKOFF_GET(x) (((x) & 0x0001e000) >> 13)
-#define PHY_BB_TIMING_CONTROLS_1_TIMING_BACKOFF_SET(x) (((x) << 13) & 0x0001e000)
-#define PHY_BB_TIMING_CONTROLS_1_ENABLE_HT_FINE_PPM_MSB 17
-#define PHY_BB_TIMING_CONTROLS_1_ENABLE_HT_FINE_PPM_LSB 17
-#define PHY_BB_TIMING_CONTROLS_1_ENABLE_HT_FINE_PPM_MASK 0x00020000
-#define PHY_BB_TIMING_CONTROLS_1_ENABLE_HT_FINE_PPM_GET(x) (((x) & 0x00020000) >> 17)
-#define PHY_BB_TIMING_CONTROLS_1_ENABLE_HT_FINE_PPM_SET(x) (((x) << 17) & 0x00020000)
-#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_STREAM_MSB 19
-#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_STREAM_LSB 18
-#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_STREAM_MASK 0x000c0000
-#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_STREAM_GET(x) (((x) & 0x000c0000) >> 18)
-#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_STREAM_SET(x) (((x) << 18) & 0x000c0000)
-#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_QAM_MSB 21
-#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_QAM_LSB 20
-#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_QAM_MASK 0x00300000
-#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_QAM_GET(x) (((x) & 0x00300000) >> 20)
-#define PHY_BB_TIMING_CONTROLS_1_HT_FINE_PPM_QAM_SET(x) (((x) << 20) & 0x00300000)
-#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_CHANFIL_MSB 22
-#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_CHANFIL_LSB 22
-#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_CHANFIL_MASK 0x00400000
-#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_CHANFIL_GET(x) (((x) & 0x00400000) >> 22)
-#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_CHANFIL_SET(x) (((x) << 22) & 0x00400000)
-#define PHY_BB_TIMING_CONTROLS_1_ENABLE_RX_STBC_MSB 23
-#define PHY_BB_TIMING_CONTROLS_1_ENABLE_RX_STBC_LSB 23
-#define PHY_BB_TIMING_CONTROLS_1_ENABLE_RX_STBC_MASK 0x00800000
-#define PHY_BB_TIMING_CONTROLS_1_ENABLE_RX_STBC_GET(x) (((x) & 0x00800000) >> 23)
-#define PHY_BB_TIMING_CONTROLS_1_ENABLE_RX_STBC_SET(x) (((x) << 23) & 0x00800000)
-#define PHY_BB_TIMING_CONTROLS_1_ENABLE_CHANNEL_FILTER_MSB 24
-#define PHY_BB_TIMING_CONTROLS_1_ENABLE_CHANNEL_FILTER_LSB 24
-#define PHY_BB_TIMING_CONTROLS_1_ENABLE_CHANNEL_FILTER_MASK 0x01000000
-#define PHY_BB_TIMING_CONTROLS_1_ENABLE_CHANNEL_FILTER_GET(x) (((x) & 0x01000000) >> 24)
-#define PHY_BB_TIMING_CONTROLS_1_ENABLE_CHANNEL_FILTER_SET(x) (((x) << 24) & 0x01000000)
-#define PHY_BB_TIMING_CONTROLS_1_FALSE_ALARM_MSB 26
-#define PHY_BB_TIMING_CONTROLS_1_FALSE_ALARM_LSB 25
-#define PHY_BB_TIMING_CONTROLS_1_FALSE_ALARM_MASK 0x06000000
-#define PHY_BB_TIMING_CONTROLS_1_FALSE_ALARM_GET(x) (((x) & 0x06000000) >> 25)
-#define PHY_BB_TIMING_CONTROLS_1_FALSE_ALARM_SET(x) (((x) << 25) & 0x06000000)
-#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_RESCALE_MSB 27
-#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_RESCALE_LSB 27
-#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_RESCALE_MASK 0x08000000
-#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_RESCALE_GET(x) (((x) & 0x08000000) >> 27)
-#define PHY_BB_TIMING_CONTROLS_1_ENABLE_LONG_RESCALE_SET(x) (((x) << 27) & 0x08000000)
-#define PHY_BB_TIMING_CONTROLS_1_TIMING_LEAK_ENABLE_MSB 28
-#define PHY_BB_TIMING_CONTROLS_1_TIMING_LEAK_ENABLE_LSB 28
-#define PHY_BB_TIMING_CONTROLS_1_TIMING_LEAK_ENABLE_MASK 0x10000000
-#define PHY_BB_TIMING_CONTROLS_1_TIMING_LEAK_ENABLE_GET(x) (((x) & 0x10000000) >> 28)
-#define PHY_BB_TIMING_CONTROLS_1_TIMING_LEAK_ENABLE_SET(x) (((x) << 28) & 0x10000000)
-#define PHY_BB_TIMING_CONTROLS_1_COARSE_PPM_SELECT_MSB 30
-#define PHY_BB_TIMING_CONTROLS_1_COARSE_PPM_SELECT_LSB 29
-#define PHY_BB_TIMING_CONTROLS_1_COARSE_PPM_SELECT_MASK 0x60000000
-#define PHY_BB_TIMING_CONTROLS_1_COARSE_PPM_SELECT_GET(x) (((x) & 0x60000000) >> 29)
-#define PHY_BB_TIMING_CONTROLS_1_COARSE_PPM_SELECT_SET(x) (((x) << 29) & 0x60000000)
-#define PHY_BB_TIMING_CONTROLS_1_FFT_SCALING_MSB 31
-#define PHY_BB_TIMING_CONTROLS_1_FFT_SCALING_LSB 31
-#define PHY_BB_TIMING_CONTROLS_1_FFT_SCALING_MASK 0x80000000
-#define PHY_BB_TIMING_CONTROLS_1_FFT_SCALING_GET(x) (((x) & 0x80000000) >> 31)
-#define PHY_BB_TIMING_CONTROLS_1_FFT_SCALING_SET(x) (((x) << 31) & 0x80000000)
-
-/* macros for BB_timing_controls_2 */
-#define PHY_BB_TIMING_CONTROLS_2_ADDRESS 0x00009810
-#define PHY_BB_TIMING_CONTROLS_2_OFFSET 0x00009810
-#define PHY_BB_TIMING_CONTROLS_2_FORCED_DELTA_PHI_SYMBOL_MSB 11
-#define PHY_BB_TIMING_CONTROLS_2_FORCED_DELTA_PHI_SYMBOL_LSB 0
-#define PHY_BB_TIMING_CONTROLS_2_FORCED_DELTA_PHI_SYMBOL_MASK 0x00000fff
-#define PHY_BB_TIMING_CONTROLS_2_FORCED_DELTA_PHI_SYMBOL_GET(x) (((x) & 0x00000fff) >> 0)
-#define PHY_BB_TIMING_CONTROLS_2_FORCED_DELTA_PHI_SYMBOL_SET(x) (((x) << 0) & 0x00000fff)
-#define PHY_BB_TIMING_CONTROLS_2_FORCE_DELTA_PHI_SYMBOL_MSB 12
-#define PHY_BB_TIMING_CONTROLS_2_FORCE_DELTA_PHI_SYMBOL_LSB 12
-#define PHY_BB_TIMING_CONTROLS_2_FORCE_DELTA_PHI_SYMBOL_MASK 0x00001000
-#define PHY_BB_TIMING_CONTROLS_2_FORCE_DELTA_PHI_SYMBOL_GET(x) (((x) & 0x00001000) >> 12)
-#define PHY_BB_TIMING_CONTROLS_2_FORCE_DELTA_PHI_SYMBOL_SET(x) (((x) << 12) & 0x00001000)
-#define PHY_BB_TIMING_CONTROLS_2_ENABLE_MAGNITUDE_TRACK_MSB 13
-#define PHY_BB_TIMING_CONTROLS_2_ENABLE_MAGNITUDE_TRACK_LSB 13
-#define PHY_BB_TIMING_CONTROLS_2_ENABLE_MAGNITUDE_TRACK_MASK 0x00002000
-#define PHY_BB_TIMING_CONTROLS_2_ENABLE_MAGNITUDE_TRACK_GET(x) (((x) & 0x00002000) >> 13)
-#define PHY_BB_TIMING_CONTROLS_2_ENABLE_MAGNITUDE_TRACK_SET(x) (((x) << 13) & 0x00002000)
-#define PHY_BB_TIMING_CONTROLS_2_ENABLE_SLOPE_FILTER_MSB 14
-#define PHY_BB_TIMING_CONTROLS_2_ENABLE_SLOPE_FILTER_LSB 14
-#define PHY_BB_TIMING_CONTROLS_2_ENABLE_SLOPE_FILTER_MASK 0x00004000
-#define PHY_BB_TIMING_CONTROLS_2_ENABLE_SLOPE_FILTER_GET(x) (((x) & 0x00004000) >> 14)
-#define PHY_BB_TIMING_CONTROLS_2_ENABLE_SLOPE_FILTER_SET(x) (((x) << 14) & 0x00004000)
-#define PHY_BB_TIMING_CONTROLS_2_ENABLE_OFFSET_FILTER_MSB 15
-#define PHY_BB_TIMING_CONTROLS_2_ENABLE_OFFSET_FILTER_LSB 15
-#define PHY_BB_TIMING_CONTROLS_2_ENABLE_OFFSET_FILTER_MASK 0x00008000
-#define PHY_BB_TIMING_CONTROLS_2_ENABLE_OFFSET_FILTER_GET(x) (((x) & 0x00008000) >> 15)
-#define PHY_BB_TIMING_CONTROLS_2_ENABLE_OFFSET_FILTER_SET(x) (((x) << 15) & 0x00008000)
-#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_DELTAF_THRES_MSB 22
-#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_DELTAF_THRES_LSB 16
-#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_DELTAF_THRES_MASK 0x007f0000
-#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_DELTAF_THRES_GET(x) (((x) & 0x007f0000) >> 16)
-#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_DELTAF_THRES_SET(x) (((x) << 16) & 0x007f0000)
-#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_TIM_CONST_MSB 26
-#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_TIM_CONST_LSB 24
-#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_TIM_CONST_MASK 0x07000000
-#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_TIM_CONST_GET(x) (((x) & 0x07000000) >> 24)
-#define PHY_BB_TIMING_CONTROLS_2_DC_OFF_TIM_CONST_SET(x) (((x) << 24) & 0x07000000)
-#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_MSB 27
-#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_LSB 27
-#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_MASK 0x08000000
-#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_GET(x) (((x) & 0x08000000) >> 27)
-#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_SET(x) (((x) << 27) & 0x08000000)
-#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_TRACK_MSB 28
-#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_TRACK_LSB 28
-#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_TRACK_MASK 0x10000000
-#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_TRACK_GET(x) (((x) & 0x10000000) >> 28)
-#define PHY_BB_TIMING_CONTROLS_2_ENABLE_DC_OFFSET_TRACK_SET(x) (((x) << 28) & 0x10000000)
-#define PHY_BB_TIMING_CONTROLS_2_ENABLE_WEIGHTING_MSB 29
-#define PHY_BB_TIMING_CONTROLS_2_ENABLE_WEIGHTING_LSB 29
-#define PHY_BB_TIMING_CONTROLS_2_ENABLE_WEIGHTING_MASK 0x20000000
-#define PHY_BB_TIMING_CONTROLS_2_ENABLE_WEIGHTING_GET(x) (((x) & 0x20000000) >> 29)
-#define PHY_BB_TIMING_CONTROLS_2_ENABLE_WEIGHTING_SET(x) (((x) << 29) & 0x20000000)
-#define PHY_BB_TIMING_CONTROLS_2_TRACEBACK128_MSB 30
-#define PHY_BB_TIMING_CONTROLS_2_TRACEBACK128_LSB 30
-#define PHY_BB_TIMING_CONTROLS_2_TRACEBACK128_MASK 0x40000000
-#define PHY_BB_TIMING_CONTROLS_2_TRACEBACK128_GET(x) (((x) & 0x40000000) >> 30)
-#define PHY_BB_TIMING_CONTROLS_2_TRACEBACK128_SET(x) (((x) << 30) & 0x40000000)
-#define PHY_BB_TIMING_CONTROLS_2_ENABLE_HT_FINE_TIMING_MSB 31
-#define PHY_BB_TIMING_CONTROLS_2_ENABLE_HT_FINE_TIMING_LSB 31
-#define PHY_BB_TIMING_CONTROLS_2_ENABLE_HT_FINE_TIMING_MASK 0x80000000
-#define PHY_BB_TIMING_CONTROLS_2_ENABLE_HT_FINE_TIMING_GET(x) (((x) & 0x80000000) >> 31)
-#define PHY_BB_TIMING_CONTROLS_2_ENABLE_HT_FINE_TIMING_SET(x) (((x) << 31) & 0x80000000)
-
-/* macros for BB_timing_controls_3 */
-#define PHY_BB_TIMING_CONTROLS_3_ADDRESS 0x00009814
-#define PHY_BB_TIMING_CONTROLS_3_OFFSET 0x00009814
-#define PHY_BB_TIMING_CONTROLS_3_PPM_RESCUE_INTERVAL_MSB 7
-#define PHY_BB_TIMING_CONTROLS_3_PPM_RESCUE_INTERVAL_LSB 0
-#define PHY_BB_TIMING_CONTROLS_3_PPM_RESCUE_INTERVAL_MASK 0x000000ff
-#define PHY_BB_TIMING_CONTROLS_3_PPM_RESCUE_INTERVAL_GET(x) (((x) & 0x000000ff) >> 0)
-#define PHY_BB_TIMING_CONTROLS_3_PPM_RESCUE_INTERVAL_SET(x) (((x) << 0) & 0x000000ff)
-#define PHY_BB_TIMING_CONTROLS_3_ENABLE_PPM_RESCUE_MSB 8
-#define PHY_BB_TIMING_CONTROLS_3_ENABLE_PPM_RESCUE_LSB 8
-#define PHY_BB_TIMING_CONTROLS_3_ENABLE_PPM_RESCUE_MASK 0x00000100
-#define PHY_BB_TIMING_CONTROLS_3_ENABLE_PPM_RESCUE_GET(x) (((x) & 0x00000100) >> 8)
-#define PHY_BB_TIMING_CONTROLS_3_ENABLE_PPM_RESCUE_SET(x) (((x) << 8) & 0x00000100)
-#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_PPM_MSB 9
-#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_PPM_LSB 9
-#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_PPM_MASK 0x00000200
-#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_PPM_GET(x) (((x) & 0x00000200) >> 9)
-#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_PPM_SET(x) (((x) << 9) & 0x00000200)
-#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_INTERP_MSB 10
-#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_INTERP_LSB 10
-#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_INTERP_MASK 0x00000400
-#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_INTERP_GET(x) (((x) & 0x00000400) >> 10)
-#define PHY_BB_TIMING_CONTROLS_3_ENABLE_FINE_INTERP_SET(x) (((x) << 10) & 0x00000400)
-#define PHY_BB_TIMING_CONTROLS_3_CONTINUOUS_PPM_RESCUE_MSB 11
-#define PHY_BB_TIMING_CONTROLS_3_CONTINUOUS_PPM_RESCUE_LSB 11
-#define PHY_BB_TIMING_CONTROLS_3_CONTINUOUS_PPM_RESCUE_MASK 0x00000800
-#define PHY_BB_TIMING_CONTROLS_3_CONTINUOUS_PPM_RESCUE_GET(x) (((x) & 0x00000800) >> 11)
-#define PHY_BB_TIMING_CONTROLS_3_CONTINUOUS_PPM_RESCUE_SET(x) (((x) << 11) & 0x00000800)
-#define PHY_BB_TIMING_CONTROLS_3_ENABLE_DF_CHANEST_MSB 12
-#define PHY_BB_TIMING_CONTROLS_3_ENABLE_DF_CHANEST_LSB 12
-#define PHY_BB_TIMING_CONTROLS_3_ENABLE_DF_CHANEST_MASK 0x00001000
-#define PHY_BB_TIMING_CONTROLS_3_ENABLE_DF_CHANEST_GET(x) (((x) & 0x00001000) >> 12)
-#define PHY_BB_TIMING_CONTROLS_3_ENABLE_DF_CHANEST_SET(x) (((x) << 12) & 0x00001000)
-#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_EXP_MSB 16
-#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_EXP_LSB 13
-#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_EXP_MASK 0x0001e000
-#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_EXP_GET(x) (((x) & 0x0001e000) >> 13)
-#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_EXP_SET(x) (((x) << 13) & 0x0001e000)
-#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_MAN_MSB 31
-#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_MAN_LSB 17
-#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_MAN_MASK 0xfffe0000
-#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_MAN_GET(x) (((x) & 0xfffe0000) >> 17)
-#define PHY_BB_TIMING_CONTROLS_3_DELTA_SLOPE_COEF_MAN_SET(x) (((x) << 17) & 0xfffe0000)
-
-/* macros for BB_D2_chip_id */
-#define PHY_BB_D2_CHIP_ID_ADDRESS 0x00009818
-#define PHY_BB_D2_CHIP_ID_OFFSET 0x00009818
-#define PHY_BB_D2_CHIP_ID_OLD_ID_MSB 7
-#define PHY_BB_D2_CHIP_ID_OLD_ID_LSB 0
-#define PHY_BB_D2_CHIP_ID_OLD_ID_MASK 0x000000ff
-#define PHY_BB_D2_CHIP_ID_OLD_ID_GET(x) (((x) & 0x000000ff) >> 0)
-#define PHY_BB_D2_CHIP_ID_ID_MSB 31
-#define PHY_BB_D2_CHIP_ID_ID_LSB 8
-#define PHY_BB_D2_CHIP_ID_ID_MASK 0xffffff00
-#define PHY_BB_D2_CHIP_ID_ID_GET(x) (((x) & 0xffffff00) >> 8)
-
-/* macros for BB_active */
-#define PHY_BB_ACTIVE_ADDRESS 0x0000981c
-#define PHY_BB_ACTIVE_OFFSET 0x0000981c
-#define PHY_BB_ACTIVE_CF_ACTIVE_MSB 0
-#define PHY_BB_ACTIVE_CF_ACTIVE_LSB 0
-#define PHY_BB_ACTIVE_CF_ACTIVE_MASK 0x00000001
-#define PHY_BB_ACTIVE_CF_ACTIVE_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_BB_ACTIVE_CF_ACTIVE_SET(x) (((x) << 0) & 0x00000001)
-
-/* macros for BB_tx_timing_1 */
-#define PHY_BB_TX_TIMING_1_ADDRESS 0x00009820
-#define PHY_BB_TX_TIMING_1_OFFSET 0x00009820
-#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_ADC_OFF_MSB 7
-#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_ADC_OFF_LSB 0
-#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_ADC_OFF_MASK 0x000000ff
-#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_ADC_OFF_GET(x) (((x) & 0x000000ff) >> 0)
-#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_ADC_OFF_SET(x) (((x) << 0) & 0x000000ff)
-#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_RX_OFF_MSB 15
-#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_RX_OFF_LSB 8
-#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_RX_OFF_MASK 0x0000ff00
-#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_RX_OFF_GET(x) (((x) & 0x0000ff00) >> 8)
-#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_RX_OFF_SET(x) (((x) << 8) & 0x0000ff00)
-#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_DAC_ON_MSB 23
-#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_DAC_ON_LSB 16
-#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_DAC_ON_MASK 0x00ff0000
-#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_DAC_ON_GET(x) (((x) & 0x00ff0000) >> 16)
-#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_DAC_ON_SET(x) (((x) << 16) & 0x00ff0000)
-#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_TX_ON_MSB 31
-#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_TX_ON_LSB 24
-#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_TX_ON_MASK 0xff000000
-#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_TX_ON_GET(x) (((x) & 0xff000000) >> 24)
-#define PHY_BB_TX_TIMING_1_TX_FRAME_TO_A2_TX_ON_SET(x) (((x) << 24) & 0xff000000)
-
-/* macros for BB_tx_timing_2 */
-#define PHY_BB_TX_TIMING_2_ADDRESS 0x00009824
-#define PHY_BB_TX_TIMING_2_OFFSET 0x00009824
-#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_TX_D_START_MSB 7
-#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_TX_D_START_LSB 0
-#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_TX_D_START_MASK 0x000000ff
-#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_TX_D_START_GET(x) (((x) & 0x000000ff) >> 0)
-#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_TX_D_START_SET(x) (((x) << 0) & 0x000000ff)
-#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_PA_ON_MSB 15
-#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_PA_ON_LSB 8
-#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_PA_ON_MASK 0x0000ff00
-#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_PA_ON_GET(x) (((x) & 0x0000ff00) >> 8)
-#define PHY_BB_TX_TIMING_2_TX_FRAME_TO_PA_ON_SET(x) (((x) << 8) & 0x0000ff00)
-#define PHY_BB_TX_TIMING_2_TX_END_TO_PA_OFF_MSB 23
-#define PHY_BB_TX_TIMING_2_TX_END_TO_PA_OFF_LSB 16
-#define PHY_BB_TX_TIMING_2_TX_END_TO_PA_OFF_MASK 0x00ff0000
-#define PHY_BB_TX_TIMING_2_TX_END_TO_PA_OFF_GET(x) (((x) & 0x00ff0000) >> 16)
-#define PHY_BB_TX_TIMING_2_TX_END_TO_PA_OFF_SET(x) (((x) << 16) & 0x00ff0000)
-#define PHY_BB_TX_TIMING_2_TX_END_TO_A2_TX_OFF_MSB 31
-#define PHY_BB_TX_TIMING_2_TX_END_TO_A2_TX_OFF_LSB 24
-#define PHY_BB_TX_TIMING_2_TX_END_TO_A2_TX_OFF_MASK 0xff000000
-#define PHY_BB_TX_TIMING_2_TX_END_TO_A2_TX_OFF_GET(x) (((x) & 0xff000000) >> 24)
-#define PHY_BB_TX_TIMING_2_TX_END_TO_A2_TX_OFF_SET(x) (((x) << 24) & 0xff000000)
-
-/* macros for BB_tx_timing_3 */
-#define PHY_BB_TX_TIMING_3_ADDRESS 0x00009828
-#define PHY_BB_TX_TIMING_3_OFFSET 0x00009828
-#define PHY_BB_TX_TIMING_3_TX_END_TO_DAC_OFF_MSB 7
-#define PHY_BB_TX_TIMING_3_TX_END_TO_DAC_OFF_LSB 0
-#define PHY_BB_TX_TIMING_3_TX_END_TO_DAC_OFF_MASK 0x000000ff
-#define PHY_BB_TX_TIMING_3_TX_END_TO_DAC_OFF_GET(x) (((x) & 0x000000ff) >> 0)
-#define PHY_BB_TX_TIMING_3_TX_END_TO_DAC_OFF_SET(x) (((x) << 0) & 0x000000ff)
-#define PHY_BB_TX_TIMING_3_TX_FRAME_TO_THERM_CHAIN_ON_MSB 15
-#define PHY_BB_TX_TIMING_3_TX_FRAME_TO_THERM_CHAIN_ON_LSB 8
-#define PHY_BB_TX_TIMING_3_TX_FRAME_TO_THERM_CHAIN_ON_MASK 0x0000ff00
-#define PHY_BB_TX_TIMING_3_TX_FRAME_TO_THERM_CHAIN_ON_GET(x) (((x) & 0x0000ff00) >> 8)
-#define PHY_BB_TX_TIMING_3_TX_FRAME_TO_THERM_CHAIN_ON_SET(x) (((x) << 8) & 0x0000ff00)
-#define PHY_BB_TX_TIMING_3_TX_END_TO_A2_RX_ON_MSB 23
-#define PHY_BB_TX_TIMING_3_TX_END_TO_A2_RX_ON_LSB 16
-#define PHY_BB_TX_TIMING_3_TX_END_TO_A2_RX_ON_MASK 0x00ff0000
-#define PHY_BB_TX_TIMING_3_TX_END_TO_A2_RX_ON_GET(x) (((x) & 0x00ff0000) >> 16)
-#define PHY_BB_TX_TIMING_3_TX_END_TO_A2_RX_ON_SET(x) (((x) << 16) & 0x00ff0000)
-#define PHY_BB_TX_TIMING_3_TX_END_TO_ADC_ON_MSB 31
-#define PHY_BB_TX_TIMING_3_TX_END_TO_ADC_ON_LSB 24
-#define PHY_BB_TX_TIMING_3_TX_END_TO_ADC_ON_MASK 0xff000000
-#define PHY_BB_TX_TIMING_3_TX_END_TO_ADC_ON_GET(x) (((x) & 0xff000000) >> 24)
-#define PHY_BB_TX_TIMING_3_TX_END_TO_ADC_ON_SET(x) (((x) << 24) & 0xff000000)
-
-/* macros for BB_addac_parallel_control */
-#define PHY_BB_ADDAC_PARALLEL_CONTROL_ADDRESS 0x0000982c
-#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFFSET 0x0000982c
-#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_DACLPMODE_MSB 12
-#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_DACLPMODE_LSB 12
-#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_DACLPMODE_MASK 0x00001000
-#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_DACLPMODE_GET(x) (((x) & 0x00001000) >> 12)
-#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_DACLPMODE_SET(x) (((x) << 12) & 0x00001000)
-#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDDAC_MSB 13
-#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDDAC_LSB 13
-#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDDAC_MASK 0x00002000
-#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDDAC_GET(x) (((x) & 0x00002000) >> 13)
-#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDDAC_SET(x) (((x) << 13) & 0x00002000)
-#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDADC_MSB 15
-#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDADC_LSB 15
-#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDADC_MASK 0x00008000
-#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDADC_GET(x) (((x) & 0x00008000) >> 15)
-#define PHY_BB_ADDAC_PARALLEL_CONTROL_OFF_PWDADC_SET(x) (((x) << 15) & 0x00008000)
-#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_DACLPMODE_MSB 28
-#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_DACLPMODE_LSB 28
-#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_DACLPMODE_MASK 0x10000000
-#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_DACLPMODE_GET(x) (((x) & 0x10000000) >> 28)
-#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_DACLPMODE_SET(x) (((x) << 28) & 0x10000000)
-#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDDAC_MSB 29
-#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDDAC_LSB 29
-#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDDAC_MASK 0x20000000
-#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDDAC_GET(x) (((x) & 0x20000000) >> 29)
-#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDDAC_SET(x) (((x) << 29) & 0x20000000)
-#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDADC_MSB 31
-#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDADC_LSB 31
-#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDADC_MASK 0x80000000
-#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDADC_GET(x) (((x) & 0x80000000) >> 31)
-#define PHY_BB_ADDAC_PARALLEL_CONTROL_ON_PWDADC_SET(x) (((x) << 31) & 0x80000000)
-
-/* macros for BB_xpa_timing_control */
-#define PHY_BB_XPA_TIMING_CONTROL_ADDRESS 0x00009834
-#define PHY_BB_XPA_TIMING_CONTROL_OFFSET 0x00009834
-#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAA_ON_MSB 7
-#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAA_ON_LSB 0
-#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAA_ON_MASK 0x000000ff
-#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAA_ON_GET(x) (((x) & 0x000000ff) >> 0)
-#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAA_ON_SET(x) (((x) << 0) & 0x000000ff)
-#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAB_ON_MSB 15
-#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAB_ON_LSB 8
-#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAB_ON_MASK 0x0000ff00
-#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAB_ON_GET(x) (((x) & 0x0000ff00) >> 8)
-#define PHY_BB_XPA_TIMING_CONTROL_TX_FRAME_TO_XPAB_ON_SET(x) (((x) << 8) & 0x0000ff00)
-#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAA_OFF_MSB 23
-#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAA_OFF_LSB 16
-#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAA_OFF_MASK 0x00ff0000
-#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAA_OFF_GET(x) (((x) & 0x00ff0000) >> 16)
-#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAA_OFF_SET(x) (((x) << 16) & 0x00ff0000)
-#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAB_OFF_MSB 31
-#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAB_OFF_LSB 24
-#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAB_OFF_MASK 0xff000000
-#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAB_OFF_GET(x) (((x) & 0xff000000) >> 24)
-#define PHY_BB_XPA_TIMING_CONTROL_TX_END_TO_XPAB_OFF_SET(x) (((x) << 24) & 0xff000000)
-
-/* macros for BB_misc_pa_control */
-#define PHY_BB_MISC_PA_CONTROL_ADDRESS 0x00009838
-#define PHY_BB_MISC_PA_CONTROL_OFFSET 0x00009838
-#define PHY_BB_MISC_PA_CONTROL_XPAA_ACTIVE_HIGH_MSB 0
-#define PHY_BB_MISC_PA_CONTROL_XPAA_ACTIVE_HIGH_LSB 0
-#define PHY_BB_MISC_PA_CONTROL_XPAA_ACTIVE_HIGH_MASK 0x00000001
-#define PHY_BB_MISC_PA_CONTROL_XPAA_ACTIVE_HIGH_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_BB_MISC_PA_CONTROL_XPAA_ACTIVE_HIGH_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_BB_MISC_PA_CONTROL_XPAB_ACTIVE_HIGH_MSB 1
-#define PHY_BB_MISC_PA_CONTROL_XPAB_ACTIVE_HIGH_LSB 1
-#define PHY_BB_MISC_PA_CONTROL_XPAB_ACTIVE_HIGH_MASK 0x00000002
-#define PHY_BB_MISC_PA_CONTROL_XPAB_ACTIVE_HIGH_GET(x) (((x) & 0x00000002) >> 1)
-#define PHY_BB_MISC_PA_CONTROL_XPAB_ACTIVE_HIGH_SET(x) (((x) << 1) & 0x00000002)
-#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAA_MSB 2
-#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAA_LSB 2
-#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAA_MASK 0x00000004
-#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAA_GET(x) (((x) & 0x00000004) >> 2)
-#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAA_SET(x) (((x) << 2) & 0x00000004)
-#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAB_MSB 3
-#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAB_LSB 3
-#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAB_MASK 0x00000008
-#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAB_GET(x) (((x) & 0x00000008) >> 3)
-#define PHY_BB_MISC_PA_CONTROL_ENABLE_XPAB_SET(x) (((x) << 3) & 0x00000008)
-
-/* macros for BB_tstdac_constant */
-#define PHY_BB_TSTDAC_CONSTANT_ADDRESS 0x0000983c
-#define PHY_BB_TSTDAC_CONSTANT_OFFSET 0x0000983c
-#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_I_MSB 10
-#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_I_LSB 0
-#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_I_MASK 0x000007ff
-#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_I_GET(x) (((x) & 0x000007ff) >> 0)
-#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_I_SET(x) (((x) << 0) & 0x000007ff)
-#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_Q_MSB 21
-#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_Q_LSB 11
-#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_Q_MASK 0x003ff800
-#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_Q_GET(x) (((x) & 0x003ff800) >> 11)
-#define PHY_BB_TSTDAC_CONSTANT_CF_TSTDAC_CONSTANT_Q_SET(x) (((x) << 11) & 0x003ff800)
-
-/* macros for BB_find_signal_low */
-#define PHY_BB_FIND_SIGNAL_LOW_ADDRESS 0x00009840
-#define PHY_BB_FIND_SIGNAL_LOW_OFFSET 0x00009840
-#define PHY_BB_FIND_SIGNAL_LOW_RELSTEP_LOW_MSB 5
-#define PHY_BB_FIND_SIGNAL_LOW_RELSTEP_LOW_LSB 0
-#define PHY_BB_FIND_SIGNAL_LOW_RELSTEP_LOW_MASK 0x0000003f
-#define PHY_BB_FIND_SIGNAL_LOW_RELSTEP_LOW_GET(x) (((x) & 0x0000003f) >> 0)
-#define PHY_BB_FIND_SIGNAL_LOW_RELSTEP_LOW_SET(x) (((x) << 0) & 0x0000003f)
-#define PHY_BB_FIND_SIGNAL_LOW_FIRSTEP_LOW_MSB 11
-#define PHY_BB_FIND_SIGNAL_LOW_FIRSTEP_LOW_LSB 6
-#define PHY_BB_FIND_SIGNAL_LOW_FIRSTEP_LOW_MASK 0x00000fc0
-#define PHY_BB_FIND_SIGNAL_LOW_FIRSTEP_LOW_GET(x) (((x) & 0x00000fc0) >> 6)
-#define PHY_BB_FIND_SIGNAL_LOW_FIRSTEP_LOW_SET(x) (((x) << 6) & 0x00000fc0)
-#define PHY_BB_FIND_SIGNAL_LOW_FIRPWR_LOW_MSB 19
-#define PHY_BB_FIND_SIGNAL_LOW_FIRPWR_LOW_LSB 12
-#define PHY_BB_FIND_SIGNAL_LOW_FIRPWR_LOW_MASK 0x000ff000
-#define PHY_BB_FIND_SIGNAL_LOW_FIRPWR_LOW_GET(x) (((x) & 0x000ff000) >> 12)
-#define PHY_BB_FIND_SIGNAL_LOW_FIRPWR_LOW_SET(x) (((x) << 12) & 0x000ff000)
-#define PHY_BB_FIND_SIGNAL_LOW_YCOK_MAX_LOW_MSB 23
-#define PHY_BB_FIND_SIGNAL_LOW_YCOK_MAX_LOW_LSB 20
-#define PHY_BB_FIND_SIGNAL_LOW_YCOK_MAX_LOW_MASK 0x00f00000
-#define PHY_BB_FIND_SIGNAL_LOW_YCOK_MAX_LOW_GET(x) (((x) & 0x00f00000) >> 20)
-#define PHY_BB_FIND_SIGNAL_LOW_YCOK_MAX_LOW_SET(x) (((x) << 20) & 0x00f00000)
-#define PHY_BB_FIND_SIGNAL_LOW_LONG_SC_THRESH_MSB 30
-#define PHY_BB_FIND_SIGNAL_LOW_LONG_SC_THRESH_LSB 24
-#define PHY_BB_FIND_SIGNAL_LOW_LONG_SC_THRESH_MASK 0x7f000000
-#define PHY_BB_FIND_SIGNAL_LOW_LONG_SC_THRESH_GET(x) (((x) & 0x7f000000) >> 24)
-#define PHY_BB_FIND_SIGNAL_LOW_LONG_SC_THRESH_SET(x) (((x) << 24) & 0x7f000000)
-
-/* macros for BB_settling_time */
-#define PHY_BB_SETTLING_TIME_ADDRESS 0x00009844
-#define PHY_BB_SETTLING_TIME_OFFSET 0x00009844
-#define PHY_BB_SETTLING_TIME_AGC_SETTLING_MSB 6
-#define PHY_BB_SETTLING_TIME_AGC_SETTLING_LSB 0
-#define PHY_BB_SETTLING_TIME_AGC_SETTLING_MASK 0x0000007f
-#define PHY_BB_SETTLING_TIME_AGC_SETTLING_GET(x) (((x) & 0x0000007f) >> 0)
-#define PHY_BB_SETTLING_TIME_AGC_SETTLING_SET(x) (((x) << 0) & 0x0000007f)
-#define PHY_BB_SETTLING_TIME_SWITCH_SETTLING_MSB 13
-#define PHY_BB_SETTLING_TIME_SWITCH_SETTLING_LSB 7
-#define PHY_BB_SETTLING_TIME_SWITCH_SETTLING_MASK 0x00003f80
-#define PHY_BB_SETTLING_TIME_SWITCH_SETTLING_GET(x) (((x) & 0x00003f80) >> 7)
-#define PHY_BB_SETTLING_TIME_SWITCH_SETTLING_SET(x) (((x) << 7) & 0x00003f80)
-#define PHY_BB_SETTLING_TIME_ADCSAT_THRL_MSB 19
-#define PHY_BB_SETTLING_TIME_ADCSAT_THRL_LSB 14
-#define PHY_BB_SETTLING_TIME_ADCSAT_THRL_MASK 0x000fc000
-#define PHY_BB_SETTLING_TIME_ADCSAT_THRL_GET(x) (((x) & 0x000fc000) >> 14)
-#define PHY_BB_SETTLING_TIME_ADCSAT_THRL_SET(x) (((x) << 14) & 0x000fc000)
-#define PHY_BB_SETTLING_TIME_ADCSAT_THRH_MSB 25
-#define PHY_BB_SETTLING_TIME_ADCSAT_THRH_LSB 20
-#define PHY_BB_SETTLING_TIME_ADCSAT_THRH_MASK 0x03f00000
-#define PHY_BB_SETTLING_TIME_ADCSAT_THRH_GET(x) (((x) & 0x03f00000) >> 20)
-#define PHY_BB_SETTLING_TIME_ADCSAT_THRH_SET(x) (((x) << 20) & 0x03f00000)
-#define PHY_BB_SETTLING_TIME_LBRESET_ADVANCE_MSB 29
-#define PHY_BB_SETTLING_TIME_LBRESET_ADVANCE_LSB 26
-#define PHY_BB_SETTLING_TIME_LBRESET_ADVANCE_MASK 0x3c000000
-#define PHY_BB_SETTLING_TIME_LBRESET_ADVANCE_GET(x) (((x) & 0x3c000000) >> 26)
-#define PHY_BB_SETTLING_TIME_LBRESET_ADVANCE_SET(x) (((x) << 26) & 0x3c000000)
-
-/* macros for BB_gain_force_max_gains_b0 */
-#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_ADDRESS 0x00009848
-#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_OFFSET 0x00009848
-#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN1_HYST_MARGIN_0_MSB 13
-#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN1_HYST_MARGIN_0_LSB 7
-#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN1_HYST_MARGIN_0_MASK 0x00003f80
-#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN1_HYST_MARGIN_0_GET(x) (((x) & 0x00003f80) >> 7)
-#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN1_HYST_MARGIN_0_SET(x) (((x) << 7) & 0x00003f80)
-#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN2_HYST_MARGIN_0_MSB 20
-#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN2_HYST_MARGIN_0_LSB 14
-#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN2_HYST_MARGIN_0_MASK 0x001fc000
-#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN2_HYST_MARGIN_0_GET(x) (((x) & 0x001fc000) >> 14)
-#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_XATTEN2_HYST_MARGIN_0_SET(x) (((x) << 14) & 0x001fc000)
-#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_GAIN_FORCE_MSB 21
-#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_GAIN_FORCE_LSB 21
-#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_GAIN_FORCE_MASK 0x00200000
-#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_GAIN_FORCE_GET(x) (((x) & 0x00200000) >> 21)
-#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_GAIN_FORCE_SET(x) (((x) << 21) & 0x00200000)
-#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_ENABLE_SHARED_RX_MSB 31
-#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_ENABLE_SHARED_RX_LSB 31
-#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_ENABLE_SHARED_RX_MASK 0x80000000
-#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_ENABLE_SHARED_RX_GET(x) (((x) & 0x80000000) >> 31)
-#define PHY_BB_GAIN_FORCE_MAX_GAINS_B0_ENABLE_SHARED_RX_SET(x) (((x) << 31) & 0x80000000)
-
-/* macros for BB_gains_min_offsets_b0 */
-#define PHY_BB_GAINS_MIN_OFFSETS_B0_ADDRESS 0x0000984c
-#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSET 0x0000984c
-#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC1_MSB 6
-#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC1_LSB 0
-#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC1_MASK 0x0000007f
-#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC1_GET(x) (((x) & 0x0000007f) >> 0)
-#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC1_SET(x) (((x) << 0) & 0x0000007f)
-#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC2_MSB 11
-#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC2_LSB 7
-#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC2_MASK 0x00000f80
-#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC2_GET(x) (((x) & 0x00000f80) >> 7)
-#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC2_SET(x) (((x) << 7) & 0x00000f80)
-#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC3_MSB 16
-#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC3_LSB 12
-#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC3_MASK 0x0001f000
-#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC3_GET(x) (((x) & 0x0001f000) >> 12)
-#define PHY_BB_GAINS_MIN_OFFSETS_B0_OFFSETC3_SET(x) (((x) << 12) & 0x0001f000)
-#define PHY_BB_GAINS_MIN_OFFSETS_B0_RF_GAIN_F_0_MSB 24
-#define PHY_BB_GAINS_MIN_OFFSETS_B0_RF_GAIN_F_0_LSB 17
-#define PHY_BB_GAINS_MIN_OFFSETS_B0_RF_GAIN_F_0_MASK 0x01fe0000
-#define PHY_BB_GAINS_MIN_OFFSETS_B0_RF_GAIN_F_0_GET(x) (((x) & 0x01fe0000) >> 17)
-#define PHY_BB_GAINS_MIN_OFFSETS_B0_RF_GAIN_F_0_SET(x) (((x) << 17) & 0x01fe0000)
-#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN1_SW_F_0_MSB 25
-#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN1_SW_F_0_LSB 25
-#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN1_SW_F_0_MASK 0x02000000
-#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN1_SW_F_0_GET(x) (((x) & 0x02000000) >> 25)
-#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN1_SW_F_0_SET(x) (((x) << 25) & 0x02000000)
-#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN2_SW_F_0_MSB 26
-#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN2_SW_F_0_LSB 26
-#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN2_SW_F_0_MASK 0x04000000
-#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN2_SW_F_0_GET(x) (((x) & 0x04000000) >> 26)
-#define PHY_BB_GAINS_MIN_OFFSETS_B0_XATTEN2_SW_F_0_SET(x) (((x) << 26) & 0x04000000)
-
-/* macros for BB_desired_sigsize */
-#define PHY_BB_DESIRED_SIGSIZE_ADDRESS 0x00009850
-#define PHY_BB_DESIRED_SIGSIZE_OFFSET 0x00009850
-#define PHY_BB_DESIRED_SIGSIZE_ADC_DESIRED_SIZE_MSB 7
-#define PHY_BB_DESIRED_SIGSIZE_ADC_DESIRED_SIZE_LSB 0
-#define PHY_BB_DESIRED_SIGSIZE_ADC_DESIRED_SIZE_MASK 0x000000ff
-#define PHY_BB_DESIRED_SIGSIZE_ADC_DESIRED_SIZE_GET(x) (((x) & 0x000000ff) >> 0)
-#define PHY_BB_DESIRED_SIGSIZE_ADC_DESIRED_SIZE_SET(x) (((x) << 0) & 0x000000ff)
-#define PHY_BB_DESIRED_SIGSIZE_TOTAL_DESIRED_MSB 27
-#define PHY_BB_DESIRED_SIGSIZE_TOTAL_DESIRED_LSB 20
-#define PHY_BB_DESIRED_SIGSIZE_TOTAL_DESIRED_MASK 0x0ff00000
-#define PHY_BB_DESIRED_SIGSIZE_TOTAL_DESIRED_GET(x) (((x) & 0x0ff00000) >> 20)
-#define PHY_BB_DESIRED_SIGSIZE_TOTAL_DESIRED_SET(x) (((x) << 20) & 0x0ff00000)
-#define PHY_BB_DESIRED_SIGSIZE_INIT_GC_COUNT_MAX_MSB 29
-#define PHY_BB_DESIRED_SIGSIZE_INIT_GC_COUNT_MAX_LSB 28
-#define PHY_BB_DESIRED_SIGSIZE_INIT_GC_COUNT_MAX_MASK 0x30000000
-#define PHY_BB_DESIRED_SIGSIZE_INIT_GC_COUNT_MAX_GET(x) (((x) & 0x30000000) >> 28)
-#define PHY_BB_DESIRED_SIGSIZE_INIT_GC_COUNT_MAX_SET(x) (((x) << 28) & 0x30000000)
-#define PHY_BB_DESIRED_SIGSIZE_REDUCE_INIT_GC_COUNT_MSB 30
-#define PHY_BB_DESIRED_SIGSIZE_REDUCE_INIT_GC_COUNT_LSB 30
-#define PHY_BB_DESIRED_SIGSIZE_REDUCE_INIT_GC_COUNT_MASK 0x40000000
-#define PHY_BB_DESIRED_SIGSIZE_REDUCE_INIT_GC_COUNT_GET(x) (((x) & 0x40000000) >> 30)
-#define PHY_BB_DESIRED_SIGSIZE_REDUCE_INIT_GC_COUNT_SET(x) (((x) << 30) & 0x40000000)
-#define PHY_BB_DESIRED_SIGSIZE_ENA_INIT_GAIN_MSB 31
-#define PHY_BB_DESIRED_SIGSIZE_ENA_INIT_GAIN_LSB 31
-#define PHY_BB_DESIRED_SIGSIZE_ENA_INIT_GAIN_MASK 0x80000000
-#define PHY_BB_DESIRED_SIGSIZE_ENA_INIT_GAIN_GET(x) (((x) & 0x80000000) >> 31)
-#define PHY_BB_DESIRED_SIGSIZE_ENA_INIT_GAIN_SET(x) (((x) << 31) & 0x80000000)
-
-/* macros for BB_timing_control_3a */
-#define PHY_BB_TIMING_CONTROL_3A_ADDRESS 0x00009854
-#define PHY_BB_TIMING_CONTROL_3A_OFFSET 0x00009854
-#define PHY_BB_TIMING_CONTROL_3A_STE_THR_HI_RSSI_MSB 6
-#define PHY_BB_TIMING_CONTROL_3A_STE_THR_HI_RSSI_LSB 0
-#define PHY_BB_TIMING_CONTROL_3A_STE_THR_HI_RSSI_MASK 0x0000007f
-#define PHY_BB_TIMING_CONTROL_3A_STE_THR_HI_RSSI_GET(x) (((x) & 0x0000007f) >> 0)
-#define PHY_BB_TIMING_CONTROL_3A_STE_THR_HI_RSSI_SET(x) (((x) << 0) & 0x0000007f)
-
-/* macros for BB_find_signal */
-#define PHY_BB_FIND_SIGNAL_ADDRESS 0x00009858
-#define PHY_BB_FIND_SIGNAL_OFFSET 0x00009858
-#define PHY_BB_FIND_SIGNAL_RELSTEP_MSB 5
-#define PHY_BB_FIND_SIGNAL_RELSTEP_LSB 0
-#define PHY_BB_FIND_SIGNAL_RELSTEP_MASK 0x0000003f
-#define PHY_BB_FIND_SIGNAL_RELSTEP_GET(x) (((x) & 0x0000003f) >> 0)
-#define PHY_BB_FIND_SIGNAL_RELSTEP_SET(x) (((x) << 0) & 0x0000003f)
-#define PHY_BB_FIND_SIGNAL_RELPWR_MSB 11
-#define PHY_BB_FIND_SIGNAL_RELPWR_LSB 6
-#define PHY_BB_FIND_SIGNAL_RELPWR_MASK 0x00000fc0
-#define PHY_BB_FIND_SIGNAL_RELPWR_GET(x) (((x) & 0x00000fc0) >> 6)
-#define PHY_BB_FIND_SIGNAL_RELPWR_SET(x) (((x) << 6) & 0x00000fc0)
-#define PHY_BB_FIND_SIGNAL_FIRSTEP_MSB 17
-#define PHY_BB_FIND_SIGNAL_FIRSTEP_LSB 12
-#define PHY_BB_FIND_SIGNAL_FIRSTEP_MASK 0x0003f000
-#define PHY_BB_FIND_SIGNAL_FIRSTEP_GET(x) (((x) & 0x0003f000) >> 12)
-#define PHY_BB_FIND_SIGNAL_FIRSTEP_SET(x) (((x) << 12) & 0x0003f000)
-#define PHY_BB_FIND_SIGNAL_FIRPWR_MSB 25
-#define PHY_BB_FIND_SIGNAL_FIRPWR_LSB 18
-#define PHY_BB_FIND_SIGNAL_FIRPWR_MASK 0x03fc0000
-#define PHY_BB_FIND_SIGNAL_FIRPWR_GET(x) (((x) & 0x03fc0000) >> 18)
-#define PHY_BB_FIND_SIGNAL_FIRPWR_SET(x) (((x) << 18) & 0x03fc0000)
-#define PHY_BB_FIND_SIGNAL_M1COUNT_MAX_MSB 31
-#define PHY_BB_FIND_SIGNAL_M1COUNT_MAX_LSB 26
-#define PHY_BB_FIND_SIGNAL_M1COUNT_MAX_MASK 0xfc000000
-#define PHY_BB_FIND_SIGNAL_M1COUNT_MAX_GET(x) (((x) & 0xfc000000) >> 26)
-#define PHY_BB_FIND_SIGNAL_M1COUNT_MAX_SET(x) (((x) << 26) & 0xfc000000)
-
-/* macros for BB_agc */
-#define PHY_BB_AGC_ADDRESS 0x0000985c
-#define PHY_BB_AGC_OFFSET 0x0000985c
-#define PHY_BB_AGC_COARSEPWR_CONST_MSB 6
-#define PHY_BB_AGC_COARSEPWR_CONST_LSB 0
-#define PHY_BB_AGC_COARSEPWR_CONST_MASK 0x0000007f
-#define PHY_BB_AGC_COARSEPWR_CONST_GET(x) (((x) & 0x0000007f) >> 0)
-#define PHY_BB_AGC_COARSEPWR_CONST_SET(x) (((x) << 0) & 0x0000007f)
-#define PHY_BB_AGC_COARSE_LOW_MSB 14
-#define PHY_BB_AGC_COARSE_LOW_LSB 7
-#define PHY_BB_AGC_COARSE_LOW_MASK 0x00007f80
-#define PHY_BB_AGC_COARSE_LOW_GET(x) (((x) & 0x00007f80) >> 7)
-#define PHY_BB_AGC_COARSE_LOW_SET(x) (((x) << 7) & 0x00007f80)
-#define PHY_BB_AGC_COARSE_HIGH_MSB 21
-#define PHY_BB_AGC_COARSE_HIGH_LSB 15
-#define PHY_BB_AGC_COARSE_HIGH_MASK 0x003f8000
-#define PHY_BB_AGC_COARSE_HIGH_GET(x) (((x) & 0x003f8000) >> 15)
-#define PHY_BB_AGC_COARSE_HIGH_SET(x) (((x) << 15) & 0x003f8000)
-#define PHY_BB_AGC_QUICK_DROP_MSB 29
-#define PHY_BB_AGC_QUICK_DROP_LSB 22
-#define PHY_BB_AGC_QUICK_DROP_MASK 0x3fc00000
-#define PHY_BB_AGC_QUICK_DROP_GET(x) (((x) & 0x3fc00000) >> 22)
-#define PHY_BB_AGC_QUICK_DROP_SET(x) (((x) << 22) & 0x3fc00000)
-#define PHY_BB_AGC_RSSI_OUT_SELECT_MSB 31
-#define PHY_BB_AGC_RSSI_OUT_SELECT_LSB 30
-#define PHY_BB_AGC_RSSI_OUT_SELECT_MASK 0xc0000000
-#define PHY_BB_AGC_RSSI_OUT_SELECT_GET(x) (((x) & 0xc0000000) >> 30)
-#define PHY_BB_AGC_RSSI_OUT_SELECT_SET(x) (((x) << 30) & 0xc0000000)
-
-/* macros for BB_agc_control */
-#define PHY_BB_AGC_CONTROL_ADDRESS 0x00009860
-#define PHY_BB_AGC_CONTROL_OFFSET 0x00009860
-#define PHY_BB_AGC_CONTROL_DO_CALIBRATE_MSB 0
-#define PHY_BB_AGC_CONTROL_DO_CALIBRATE_LSB 0
-#define PHY_BB_AGC_CONTROL_DO_CALIBRATE_MASK 0x00000001
-#define PHY_BB_AGC_CONTROL_DO_CALIBRATE_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_BB_AGC_CONTROL_DO_CALIBRATE_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_BB_AGC_CONTROL_DO_NOISEFLOOR_MSB 1
-#define PHY_BB_AGC_CONTROL_DO_NOISEFLOOR_LSB 1
-#define PHY_BB_AGC_CONTROL_DO_NOISEFLOOR_MASK 0x00000002
-#define PHY_BB_AGC_CONTROL_DO_NOISEFLOOR_GET(x) (((x) & 0x00000002) >> 1)
-#define PHY_BB_AGC_CONTROL_DO_NOISEFLOOR_SET(x) (((x) << 1) & 0x00000002)
-#define PHY_BB_AGC_CONTROL_MIN_NUM_GAIN_CHANGE_MSB 5
-#define PHY_BB_AGC_CONTROL_MIN_NUM_GAIN_CHANGE_LSB 3
-#define PHY_BB_AGC_CONTROL_MIN_NUM_GAIN_CHANGE_MASK 0x00000038
-#define PHY_BB_AGC_CONTROL_MIN_NUM_GAIN_CHANGE_GET(x) (((x) & 0x00000038) >> 3)
-#define PHY_BB_AGC_CONTROL_MIN_NUM_GAIN_CHANGE_SET(x) (((x) << 3) & 0x00000038)
-#define PHY_BB_AGC_CONTROL_YCOK_MAX_MSB 9
-#define PHY_BB_AGC_CONTROL_YCOK_MAX_LSB 6
-#define PHY_BB_AGC_CONTROL_YCOK_MAX_MASK 0x000003c0
-#define PHY_BB_AGC_CONTROL_YCOK_MAX_GET(x) (((x) & 0x000003c0) >> 6)
-#define PHY_BB_AGC_CONTROL_YCOK_MAX_SET(x) (((x) << 6) & 0x000003c0)
-#define PHY_BB_AGC_CONTROL_LEAKY_BUCKET_ENABLE_MSB 10
-#define PHY_BB_AGC_CONTROL_LEAKY_BUCKET_ENABLE_LSB 10
-#define PHY_BB_AGC_CONTROL_LEAKY_BUCKET_ENABLE_MASK 0x00000400
-#define PHY_BB_AGC_CONTROL_LEAKY_BUCKET_ENABLE_GET(x) (((x) & 0x00000400) >> 10)
-#define PHY_BB_AGC_CONTROL_LEAKY_BUCKET_ENABLE_SET(x) (((x) << 10) & 0x00000400)
-#define PHY_BB_AGC_CONTROL_CAL_ENABLE_MSB 11
-#define PHY_BB_AGC_CONTROL_CAL_ENABLE_LSB 11
-#define PHY_BB_AGC_CONTROL_CAL_ENABLE_MASK 0x00000800
-#define PHY_BB_AGC_CONTROL_CAL_ENABLE_GET(x) (((x) & 0x00000800) >> 11)
-#define PHY_BB_AGC_CONTROL_CAL_ENABLE_SET(x) (((x) << 11) & 0x00000800)
-#define PHY_BB_AGC_CONTROL_USE_TABLE_SEED_MSB 12
-#define PHY_BB_AGC_CONTROL_USE_TABLE_SEED_LSB 12
-#define PHY_BB_AGC_CONTROL_USE_TABLE_SEED_MASK 0x00001000
-#define PHY_BB_AGC_CONTROL_USE_TABLE_SEED_GET(x) (((x) & 0x00001000) >> 12)
-#define PHY_BB_AGC_CONTROL_USE_TABLE_SEED_SET(x) (((x) << 12) & 0x00001000)
-#define PHY_BB_AGC_CONTROL_AGC_UPDATE_TABLE_SEED_MSB 13
-#define PHY_BB_AGC_CONTROL_AGC_UPDATE_TABLE_SEED_LSB 13
-#define PHY_BB_AGC_CONTROL_AGC_UPDATE_TABLE_SEED_MASK 0x00002000
-#define PHY_BB_AGC_CONTROL_AGC_UPDATE_TABLE_SEED_GET(x) (((x) & 0x00002000) >> 13)
-#define PHY_BB_AGC_CONTROL_AGC_UPDATE_TABLE_SEED_SET(x) (((x) << 13) & 0x00002000)
-#define PHY_BB_AGC_CONTROL_ENABLE_NOISEFLOOR_MSB 15
-#define PHY_BB_AGC_CONTROL_ENABLE_NOISEFLOOR_LSB 15
-#define PHY_BB_AGC_CONTROL_ENABLE_NOISEFLOOR_MASK 0x00008000
-#define PHY_BB_AGC_CONTROL_ENABLE_NOISEFLOOR_GET(x) (((x) & 0x00008000) >> 15)
-#define PHY_BB_AGC_CONTROL_ENABLE_NOISEFLOOR_SET(x) (((x) << 15) & 0x00008000)
-#define PHY_BB_AGC_CONTROL_ENABLE_FLTR_CAL_MSB 16
-#define PHY_BB_AGC_CONTROL_ENABLE_FLTR_CAL_LSB 16
-#define PHY_BB_AGC_CONTROL_ENABLE_FLTR_CAL_MASK 0x00010000
-#define PHY_BB_AGC_CONTROL_ENABLE_FLTR_CAL_GET(x) (((x) & 0x00010000) >> 16)
-#define PHY_BB_AGC_CONTROL_ENABLE_FLTR_CAL_SET(x) (((x) << 16) & 0x00010000)
-#define PHY_BB_AGC_CONTROL_NO_UPDATE_NOISEFLOOR_MSB 17
-#define PHY_BB_AGC_CONTROL_NO_UPDATE_NOISEFLOOR_LSB 17
-#define PHY_BB_AGC_CONTROL_NO_UPDATE_NOISEFLOOR_MASK 0x00020000
-#define PHY_BB_AGC_CONTROL_NO_UPDATE_NOISEFLOOR_GET(x) (((x) & 0x00020000) >> 17)
-#define PHY_BB_AGC_CONTROL_NO_UPDATE_NOISEFLOOR_SET(x) (((x) << 17) & 0x00020000)
-#define PHY_BB_AGC_CONTROL_EXTEND_NF_PWR_MEAS_MSB 18
-#define PHY_BB_AGC_CONTROL_EXTEND_NF_PWR_MEAS_LSB 18
-#define PHY_BB_AGC_CONTROL_EXTEND_NF_PWR_MEAS_MASK 0x00040000
-#define PHY_BB_AGC_CONTROL_EXTEND_NF_PWR_MEAS_GET(x) (((x) & 0x00040000) >> 18)
-#define PHY_BB_AGC_CONTROL_EXTEND_NF_PWR_MEAS_SET(x) (((x) << 18) & 0x00040000)
-#define PHY_BB_AGC_CONTROL_CLC_SUCCESS_MSB 19
-#define PHY_BB_AGC_CONTROL_CLC_SUCCESS_LSB 19
-#define PHY_BB_AGC_CONTROL_CLC_SUCCESS_MASK 0x00080000
-#define PHY_BB_AGC_CONTROL_CLC_SUCCESS_GET(x) (((x) & 0x00080000) >> 19)
-#define PHY_BB_AGC_CONTROL_ENABLE_PKDET_CAL_MSB 20
-#define PHY_BB_AGC_CONTROL_ENABLE_PKDET_CAL_LSB 20
-#define PHY_BB_AGC_CONTROL_ENABLE_PKDET_CAL_MASK 0x00100000
-#define PHY_BB_AGC_CONTROL_ENABLE_PKDET_CAL_GET(x) (((x) & 0x00100000) >> 20)
-#define PHY_BB_AGC_CONTROL_ENABLE_PKDET_CAL_SET(x) (((x) << 20) & 0x00100000)
-
-/* macros for BB_cca_b0 */
-#define PHY_BB_CCA_B0_ADDRESS 0x00009864
-#define PHY_BB_CCA_B0_OFFSET 0x00009864
-#define PHY_BB_CCA_B0_CF_MAXCCAPWR_0_MSB 8
-#define PHY_BB_CCA_B0_CF_MAXCCAPWR_0_LSB 0
-#define PHY_BB_CCA_B0_CF_MAXCCAPWR_0_MASK 0x000001ff
-#define PHY_BB_CCA_B0_CF_MAXCCAPWR_0_GET(x) (((x) & 0x000001ff) >> 0)
-#define PHY_BB_CCA_B0_CF_MAXCCAPWR_0_SET(x) (((x) << 0) & 0x000001ff)
-#define PHY_BB_CCA_B0_CF_CCA_COUNT_MAXC_MSB 11
-#define PHY_BB_CCA_B0_CF_CCA_COUNT_MAXC_LSB 9
-#define PHY_BB_CCA_B0_CF_CCA_COUNT_MAXC_MASK 0x00000e00
-#define PHY_BB_CCA_B0_CF_CCA_COUNT_MAXC_GET(x) (((x) & 0x00000e00) >> 9)
-#define PHY_BB_CCA_B0_CF_CCA_COUNT_MAXC_SET(x) (((x) << 9) & 0x00000e00)
-#define PHY_BB_CCA_B0_CF_THRESH62_MSB 19
-#define PHY_BB_CCA_B0_CF_THRESH62_LSB 12
-#define PHY_BB_CCA_B0_CF_THRESH62_MASK 0x000ff000
-#define PHY_BB_CCA_B0_CF_THRESH62_GET(x) (((x) & 0x000ff000) >> 12)
-#define PHY_BB_CCA_B0_CF_THRESH62_SET(x) (((x) << 12) & 0x000ff000)
-#define PHY_BB_CCA_B0_MINCCAPWR_0_MSB 28
-#define PHY_BB_CCA_B0_MINCCAPWR_0_LSB 20
-#define PHY_BB_CCA_B0_MINCCAPWR_0_MASK 0x1ff00000
-#define PHY_BB_CCA_B0_MINCCAPWR_0_GET(x) (((x) & 0x1ff00000) >> 20)
-
-/* macros for BB_sfcorr */
-#define PHY_BB_SFCORR_ADDRESS 0x00009868
-#define PHY_BB_SFCORR_OFFSET 0x00009868
-#define PHY_BB_SFCORR_M2COUNT_THR_MSB 4
-#define PHY_BB_SFCORR_M2COUNT_THR_LSB 0
-#define PHY_BB_SFCORR_M2COUNT_THR_MASK 0x0000001f
-#define PHY_BB_SFCORR_M2COUNT_THR_GET(x) (((x) & 0x0000001f) >> 0)
-#define PHY_BB_SFCORR_M2COUNT_THR_SET(x) (((x) << 0) & 0x0000001f)
-#define PHY_BB_SFCORR_ADCSAT_THRESH_MSB 10
-#define PHY_BB_SFCORR_ADCSAT_THRESH_LSB 5
-#define PHY_BB_SFCORR_ADCSAT_THRESH_MASK 0x000007e0
-#define PHY_BB_SFCORR_ADCSAT_THRESH_GET(x) (((x) & 0x000007e0) >> 5)
-#define PHY_BB_SFCORR_ADCSAT_THRESH_SET(x) (((x) << 5) & 0x000007e0)
-#define PHY_BB_SFCORR_ADCSAT_ICOUNT_MSB 16
-#define PHY_BB_SFCORR_ADCSAT_ICOUNT_LSB 11
-#define PHY_BB_SFCORR_ADCSAT_ICOUNT_MASK 0x0001f800
-#define PHY_BB_SFCORR_ADCSAT_ICOUNT_GET(x) (((x) & 0x0001f800) >> 11)
-#define PHY_BB_SFCORR_ADCSAT_ICOUNT_SET(x) (((x) << 11) & 0x0001f800)
-#define PHY_BB_SFCORR_M1_THRES_MSB 23
-#define PHY_BB_SFCORR_M1_THRES_LSB 17
-#define PHY_BB_SFCORR_M1_THRES_MASK 0x00fe0000
-#define PHY_BB_SFCORR_M1_THRES_GET(x) (((x) & 0x00fe0000) >> 17)
-#define PHY_BB_SFCORR_M1_THRES_SET(x) (((x) << 17) & 0x00fe0000)
-#define PHY_BB_SFCORR_M2_THRES_MSB 30
-#define PHY_BB_SFCORR_M2_THRES_LSB 24
-#define PHY_BB_SFCORR_M2_THRES_MASK 0x7f000000
-#define PHY_BB_SFCORR_M2_THRES_GET(x) (((x) & 0x7f000000) >> 24)
-#define PHY_BB_SFCORR_M2_THRES_SET(x) (((x) << 24) & 0x7f000000)
-
-/* macros for BB_self_corr_low */
-#define PHY_BB_SELF_CORR_LOW_ADDRESS 0x0000986c
-#define PHY_BB_SELF_CORR_LOW_OFFSET 0x0000986c
-#define PHY_BB_SELF_CORR_LOW_USE_SELF_CORR_LOW_MSB 0
-#define PHY_BB_SELF_CORR_LOW_USE_SELF_CORR_LOW_LSB 0
-#define PHY_BB_SELF_CORR_LOW_USE_SELF_CORR_LOW_MASK 0x00000001
-#define PHY_BB_SELF_CORR_LOW_USE_SELF_CORR_LOW_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_BB_SELF_CORR_LOW_USE_SELF_CORR_LOW_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_BB_SELF_CORR_LOW_M1COUNT_MAX_LOW_MSB 7
-#define PHY_BB_SELF_CORR_LOW_M1COUNT_MAX_LOW_LSB 1
-#define PHY_BB_SELF_CORR_LOW_M1COUNT_MAX_LOW_MASK 0x000000fe
-#define PHY_BB_SELF_CORR_LOW_M1COUNT_MAX_LOW_GET(x) (((x) & 0x000000fe) >> 1)
-#define PHY_BB_SELF_CORR_LOW_M1COUNT_MAX_LOW_SET(x) (((x) << 1) & 0x000000fe)
-#define PHY_BB_SELF_CORR_LOW_M2COUNT_THR_LOW_MSB 13
-#define PHY_BB_SELF_CORR_LOW_M2COUNT_THR_LOW_LSB 8
-#define PHY_BB_SELF_CORR_LOW_M2COUNT_THR_LOW_MASK 0x00003f00
-#define PHY_BB_SELF_CORR_LOW_M2COUNT_THR_LOW_GET(x) (((x) & 0x00003f00) >> 8)
-#define PHY_BB_SELF_CORR_LOW_M2COUNT_THR_LOW_SET(x) (((x) << 8) & 0x00003f00)
-#define PHY_BB_SELF_CORR_LOW_M1_THRESH_LOW_MSB 20
-#define PHY_BB_SELF_CORR_LOW_M1_THRESH_LOW_LSB 14
-#define PHY_BB_SELF_CORR_LOW_M1_THRESH_LOW_MASK 0x001fc000
-#define PHY_BB_SELF_CORR_LOW_M1_THRESH_LOW_GET(x) (((x) & 0x001fc000) >> 14)
-#define PHY_BB_SELF_CORR_LOW_M1_THRESH_LOW_SET(x) (((x) << 14) & 0x001fc000)
-#define PHY_BB_SELF_CORR_LOW_M2_THRESH_LOW_MSB 27
-#define PHY_BB_SELF_CORR_LOW_M2_THRESH_LOW_LSB 21
-#define PHY_BB_SELF_CORR_LOW_M2_THRESH_LOW_MASK 0x0fe00000
-#define PHY_BB_SELF_CORR_LOW_M2_THRESH_LOW_GET(x) (((x) & 0x0fe00000) >> 21)
-#define PHY_BB_SELF_CORR_LOW_M2_THRESH_LOW_SET(x) (((x) << 21) & 0x0fe00000)
-
-/* macros for BB_synth_control */
-#define PHY_BB_SYNTH_CONTROL_ADDRESS 0x00009874
-#define PHY_BB_SYNTH_CONTROL_OFFSET 0x00009874
-#define PHY_BB_SYNTH_CONTROL_RFCHANFRAC_MSB 16
-#define PHY_BB_SYNTH_CONTROL_RFCHANFRAC_LSB 0
-#define PHY_BB_SYNTH_CONTROL_RFCHANFRAC_MASK 0x0001ffff
-#define PHY_BB_SYNTH_CONTROL_RFCHANFRAC_GET(x) (((x) & 0x0001ffff) >> 0)
-#define PHY_BB_SYNTH_CONTROL_RFCHANFRAC_SET(x) (((x) << 0) & 0x0001ffff)
-#define PHY_BB_SYNTH_CONTROL_RFCHANNEL_MSB 25
-#define PHY_BB_SYNTH_CONTROL_RFCHANNEL_LSB 17
-#define PHY_BB_SYNTH_CONTROL_RFCHANNEL_MASK 0x03fe0000
-#define PHY_BB_SYNTH_CONTROL_RFCHANNEL_GET(x) (((x) & 0x03fe0000) >> 17)
-#define PHY_BB_SYNTH_CONTROL_RFCHANNEL_SET(x) (((x) << 17) & 0x03fe0000)
-#define PHY_BB_SYNTH_CONTROL_RFAMODEREFSEL_MSB 27
-#define PHY_BB_SYNTH_CONTROL_RFAMODEREFSEL_LSB 26
-#define PHY_BB_SYNTH_CONTROL_RFAMODEREFSEL_MASK 0x0c000000
-#define PHY_BB_SYNTH_CONTROL_RFAMODEREFSEL_GET(x) (((x) & 0x0c000000) >> 26)
-#define PHY_BB_SYNTH_CONTROL_RFAMODEREFSEL_SET(x) (((x) << 26) & 0x0c000000)
-#define PHY_BB_SYNTH_CONTROL_RFFRACMODE_MSB 28
-#define PHY_BB_SYNTH_CONTROL_RFFRACMODE_LSB 28
-#define PHY_BB_SYNTH_CONTROL_RFFRACMODE_MASK 0x10000000
-#define PHY_BB_SYNTH_CONTROL_RFFRACMODE_GET(x) (((x) & 0x10000000) >> 28)
-#define PHY_BB_SYNTH_CONTROL_RFFRACMODE_SET(x) (((x) << 28) & 0x10000000)
-#define PHY_BB_SYNTH_CONTROL_RFBMODE_MSB 29
-#define PHY_BB_SYNTH_CONTROL_RFBMODE_LSB 29
-#define PHY_BB_SYNTH_CONTROL_RFBMODE_MASK 0x20000000
-#define PHY_BB_SYNTH_CONTROL_RFBMODE_GET(x) (((x) & 0x20000000) >> 29)
-#define PHY_BB_SYNTH_CONTROL_RFBMODE_SET(x) (((x) << 29) & 0x20000000)
-#define PHY_BB_SYNTH_CONTROL_RFSYNTH_CTRL_SSHIFT_MSB 30
-#define PHY_BB_SYNTH_CONTROL_RFSYNTH_CTRL_SSHIFT_LSB 30
-#define PHY_BB_SYNTH_CONTROL_RFSYNTH_CTRL_SSHIFT_MASK 0x40000000
-#define PHY_BB_SYNTH_CONTROL_RFSYNTH_CTRL_SSHIFT_GET(x) (((x) & 0x40000000) >> 30)
-#define PHY_BB_SYNTH_CONTROL_RFSYNTH_CTRL_SSHIFT_SET(x) (((x) << 30) & 0x40000000)
-
-/* macros for BB_addac_clk_select */
-#define PHY_BB_ADDAC_CLK_SELECT_ADDRESS 0x00009878
-#define PHY_BB_ADDAC_CLK_SELECT_OFFSET 0x00009878
-#define PHY_BB_ADDAC_CLK_SELECT_BB_DAC_CLK_SELECT_MSB 3
-#define PHY_BB_ADDAC_CLK_SELECT_BB_DAC_CLK_SELECT_LSB 2
-#define PHY_BB_ADDAC_CLK_SELECT_BB_DAC_CLK_SELECT_MASK 0x0000000c
-#define PHY_BB_ADDAC_CLK_SELECT_BB_DAC_CLK_SELECT_GET(x) (((x) & 0x0000000c) >> 2)
-#define PHY_BB_ADDAC_CLK_SELECT_BB_DAC_CLK_SELECT_SET(x) (((x) << 2) & 0x0000000c)
-#define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_MSB 5
-#define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_LSB 4
-#define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_MASK 0x00000030
-#define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_GET(x) (((x) & 0x00000030) >> 4)
-#define PHY_BB_ADDAC_CLK_SELECT_BB_ADC_CLK_SELECT_SET(x) (((x) << 4) & 0x00000030)
-
-/* macros for BB_pll_cntl */
-#define PHY_BB_PLL_CNTL_ADDRESS 0x0000987c
-#define PHY_BB_PLL_CNTL_OFFSET 0x0000987c
-#define PHY_BB_PLL_CNTL_BB_PLL_DIV_MSB 9
-#define PHY_BB_PLL_CNTL_BB_PLL_DIV_LSB 0
-#define PHY_BB_PLL_CNTL_BB_PLL_DIV_MASK 0x000003ff
-#define PHY_BB_PLL_CNTL_BB_PLL_DIV_GET(x) (((x) & 0x000003ff) >> 0)
-#define PHY_BB_PLL_CNTL_BB_PLL_DIV_SET(x) (((x) << 0) & 0x000003ff)
-#define PHY_BB_PLL_CNTL_BB_PLL_REFDIV_MSB 13
-#define PHY_BB_PLL_CNTL_BB_PLL_REFDIV_LSB 10
-#define PHY_BB_PLL_CNTL_BB_PLL_REFDIV_MASK 0x00003c00
-#define PHY_BB_PLL_CNTL_BB_PLL_REFDIV_GET(x) (((x) & 0x00003c00) >> 10)
-#define PHY_BB_PLL_CNTL_BB_PLL_REFDIV_SET(x) (((x) << 10) & 0x00003c00)
-#define PHY_BB_PLL_CNTL_BB_PLL_CLK_SEL_MSB 15
-#define PHY_BB_PLL_CNTL_BB_PLL_CLK_SEL_LSB 14
-#define PHY_BB_PLL_CNTL_BB_PLL_CLK_SEL_MASK 0x0000c000
-#define PHY_BB_PLL_CNTL_BB_PLL_CLK_SEL_GET(x) (((x) & 0x0000c000) >> 14)
-#define PHY_BB_PLL_CNTL_BB_PLL_CLK_SEL_SET(x) (((x) << 14) & 0x0000c000)
-#define PHY_BB_PLL_CNTL_BB_PLLBYPASS_MSB 16
-#define PHY_BB_PLL_CNTL_BB_PLLBYPASS_LSB 16
-#define PHY_BB_PLL_CNTL_BB_PLLBYPASS_MASK 0x00010000
-#define PHY_BB_PLL_CNTL_BB_PLLBYPASS_GET(x) (((x) & 0x00010000) >> 16)
-#define PHY_BB_PLL_CNTL_BB_PLLBYPASS_SET(x) (((x) << 16) & 0x00010000)
-#define PHY_BB_PLL_CNTL_BB_PLL_SETTLE_TIME_MSB 27
-#define PHY_BB_PLL_CNTL_BB_PLL_SETTLE_TIME_LSB 17
-#define PHY_BB_PLL_CNTL_BB_PLL_SETTLE_TIME_MASK 0x0ffe0000
-#define PHY_BB_PLL_CNTL_BB_PLL_SETTLE_TIME_GET(x) (((x) & 0x0ffe0000) >> 17)
-#define PHY_BB_PLL_CNTL_BB_PLL_SETTLE_TIME_SET(x) (((x) << 17) & 0x0ffe0000)
-
-/* macros for BB_vit_spur_mask_A */
-#define PHY_BB_VIT_SPUR_MASK_A_ADDRESS 0x00009900
-#define PHY_BB_VIT_SPUR_MASK_A_OFFSET 0x00009900
-#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_A_MSB 9
-#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_A_LSB 0
-#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_A_MASK 0x000003ff
-#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_A_GET(x) (((x) & 0x000003ff) >> 0)
-#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_A_SET(x) (((x) << 0) & 0x000003ff)
-#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_MSB 16
-#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_LSB 10
-#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_MASK 0x0001fc00
-#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_GET(x) (((x) & 0x0001fc00) >> 10)
-#define PHY_BB_VIT_SPUR_MASK_A_CF_PUNC_MASK_IDX_A_SET(x) (((x) << 10) & 0x0001fc00)
-
-/* macros for BB_vit_spur_mask_B */
-#define PHY_BB_VIT_SPUR_MASK_B_ADDRESS 0x00009904
-#define PHY_BB_VIT_SPUR_MASK_B_OFFSET 0x00009904
-#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_B_MSB 9
-#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_B_LSB 0
-#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_B_MASK 0x000003ff
-#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_B_GET(x) (((x) & 0x000003ff) >> 0)
-#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_B_SET(x) (((x) << 0) & 0x000003ff)
-#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_IDX_B_MSB 16
-#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_IDX_B_LSB 10
-#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_IDX_B_MASK 0x0001fc00
-#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_IDX_B_GET(x) (((x) & 0x0001fc00) >> 10)
-#define PHY_BB_VIT_SPUR_MASK_B_CF_PUNC_MASK_IDX_B_SET(x) (((x) << 10) & 0x0001fc00)
-
-/* macros for BB_pilot_spur_mask */
-#define PHY_BB_PILOT_SPUR_MASK_ADDRESS 0x00009908
-#define PHY_BB_PILOT_SPUR_MASK_OFFSET 0x00009908
-#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_A_MSB 4
-#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_A_LSB 0
-#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_A_MASK 0x0000001f
-#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_A_GET(x) (((x) & 0x0000001f) >> 0)
-#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_A_SET(x) (((x) << 0) & 0x0000001f)
-#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_MSB 11
-#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_LSB 5
-#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_MASK 0x00000fe0
-#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_GET(x) (((x) & 0x00000fe0) >> 5)
-#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_A_SET(x) (((x) << 5) & 0x00000fe0)
-#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_B_MSB 16
-#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_B_LSB 12
-#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_B_MASK 0x0001f000
-#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_B_GET(x) (((x) & 0x0001f000) >> 12)
-#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_B_SET(x) (((x) << 12) & 0x0001f000)
-#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B_MSB 23
-#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B_LSB 17
-#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B_MASK 0x00fe0000
-#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B_GET(x) (((x) & 0x00fe0000) >> 17)
-#define PHY_BB_PILOT_SPUR_MASK_CF_PILOT_MASK_IDX_B_SET(x) (((x) << 17) & 0x00fe0000)
-
-/* macros for BB_chan_spur_mask */
-#define PHY_BB_CHAN_SPUR_MASK_ADDRESS 0x0000990c
-#define PHY_BB_CHAN_SPUR_MASK_OFFSET 0x0000990c
-#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_A_MSB 4
-#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_A_LSB 0
-#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_A_MASK 0x0000001f
-#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_A_GET(x) (((x) & 0x0000001f) >> 0)
-#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_A_SET(x) (((x) << 0) & 0x0000001f)
-#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_MSB 11
-#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_LSB 5
-#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_MASK 0x00000fe0
-#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_GET(x) (((x) & 0x00000fe0) >> 5)
-#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_A_SET(x) (((x) << 5) & 0x00000fe0)
-#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_B_MSB 16
-#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_B_LSB 12
-#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_B_MASK 0x0001f000
-#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_B_GET(x) (((x) & 0x0001f000) >> 12)
-#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_B_SET(x) (((x) << 12) & 0x0001f000)
-#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B_MSB 23
-#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B_LSB 17
-#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B_MASK 0x00fe0000
-#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B_GET(x) (((x) & 0x00fe0000) >> 17)
-#define PHY_BB_CHAN_SPUR_MASK_CF_CHAN_MASK_IDX_B_SET(x) (((x) << 17) & 0x00fe0000)
-
-/* macros for BB_spectral_scan */
-#define PHY_BB_SPECTRAL_SCAN_ADDRESS 0x00009910
-#define PHY_BB_SPECTRAL_SCAN_OFFSET 0x00009910
-#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ENA_MSB 0
-#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ENA_LSB 0
-#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ENA_MASK 0x00000001
-#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ENA_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ENA_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ACTIVE_MSB 1
-#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ACTIVE_LSB 1
-#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ACTIVE_MASK 0x00000002
-#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ACTIVE_GET(x) (((x) & 0x00000002) >> 1)
-#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_ACTIVE_SET(x) (((x) << 1) & 0x00000002)
-#define PHY_BB_SPECTRAL_SCAN_DISABLE_RADAR_TCTL_RST_MSB 2
-#define PHY_BB_SPECTRAL_SCAN_DISABLE_RADAR_TCTL_RST_LSB 2
-#define PHY_BB_SPECTRAL_SCAN_DISABLE_RADAR_TCTL_RST_MASK 0x00000004
-#define PHY_BB_SPECTRAL_SCAN_DISABLE_RADAR_TCTL_RST_GET(x) (((x) & 0x00000004) >> 2)
-#define PHY_BB_SPECTRAL_SCAN_DISABLE_RADAR_TCTL_RST_SET(x) (((x) << 2) & 0x00000004)
-#define PHY_BB_SPECTRAL_SCAN_DISABLE_PULSE_COARSE_LOW_MSB 3
-#define PHY_BB_SPECTRAL_SCAN_DISABLE_PULSE_COARSE_LOW_LSB 3
-#define PHY_BB_SPECTRAL_SCAN_DISABLE_PULSE_COARSE_LOW_MASK 0x00000008
-#define PHY_BB_SPECTRAL_SCAN_DISABLE_PULSE_COARSE_LOW_GET(x) (((x) & 0x00000008) >> 3)
-#define PHY_BB_SPECTRAL_SCAN_DISABLE_PULSE_COARSE_LOW_SET(x) (((x) << 3) & 0x00000008)
-#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_FFT_PERIOD_MSB 7
-#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_FFT_PERIOD_LSB 4
-#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_FFT_PERIOD_MASK 0x000000f0
-#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_FFT_PERIOD_GET(x) (((x) & 0x000000f0) >> 4)
-#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_FFT_PERIOD_SET(x) (((x) << 4) & 0x000000f0)
-#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PERIOD_MSB 15
-#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PERIOD_LSB 8
-#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PERIOD_MASK 0x0000ff00
-#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PERIOD_GET(x) (((x) & 0x0000ff00) >> 8)
-#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PERIOD_SET(x) (((x) << 8) & 0x0000ff00)
-#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_COUNT_MSB 27
-#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_COUNT_LSB 16
-#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_COUNT_MASK 0x0fff0000
-#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_COUNT_GET(x) (((x) & 0x0fff0000) >> 16)
-#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_COUNT_SET(x) (((x) << 16) & 0x0fff0000)
-#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_SHORT_RPT_MSB 28
-#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_SHORT_RPT_LSB 28
-#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_SHORT_RPT_MASK 0x10000000
-#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_SHORT_RPT_GET(x) (((x) & 0x10000000) >> 28)
-#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_SHORT_RPT_SET(x) (((x) << 28) & 0x10000000)
-#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PRIORITY_MSB 29
-#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PRIORITY_LSB 29
-#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PRIORITY_MASK 0x20000000
-#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PRIORITY_GET(x) (((x) & 0x20000000) >> 29)
-#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_PRIORITY_SET(x) (((x) << 29) & 0x20000000)
-#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_USE_ERR5_MSB 30
-#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_USE_ERR5_LSB 30
-#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_USE_ERR5_MASK 0x40000000
-#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_USE_ERR5_GET(x) (((x) & 0x40000000) >> 30)
-#define PHY_BB_SPECTRAL_SCAN_SPECTRAL_SCAN_USE_ERR5_SET(x) (((x) << 30) & 0x40000000)
-
-/* macros for BB_analog_power_on_time */
-#define PHY_BB_ANALOG_POWER_ON_TIME_ADDRESS 0x00009914
-#define PHY_BB_ANALOG_POWER_ON_TIME_OFFSET 0x00009914
-#define PHY_BB_ANALOG_POWER_ON_TIME_ACTIVE_TO_RECEIVE_MSB 13
-#define PHY_BB_ANALOG_POWER_ON_TIME_ACTIVE_TO_RECEIVE_LSB 0
-#define PHY_BB_ANALOG_POWER_ON_TIME_ACTIVE_TO_RECEIVE_MASK 0x00003fff
-#define PHY_BB_ANALOG_POWER_ON_TIME_ACTIVE_TO_RECEIVE_GET(x) (((x) & 0x00003fff) >> 0)
-#define PHY_BB_ANALOG_POWER_ON_TIME_ACTIVE_TO_RECEIVE_SET(x) (((x) << 0) & 0x00003fff)
-
-/* macros for BB_search_start_delay */
-#define PHY_BB_SEARCH_START_DELAY_ADDRESS 0x00009918
-#define PHY_BB_SEARCH_START_DELAY_OFFSET 0x00009918
-#define PHY_BB_SEARCH_START_DELAY_SEARCH_START_DELAY_MSB 11
-#define PHY_BB_SEARCH_START_DELAY_SEARCH_START_DELAY_LSB 0
-#define PHY_BB_SEARCH_START_DELAY_SEARCH_START_DELAY_MASK 0x00000fff
-#define PHY_BB_SEARCH_START_DELAY_SEARCH_START_DELAY_GET(x) (((x) & 0x00000fff) >> 0)
-#define PHY_BB_SEARCH_START_DELAY_SEARCH_START_DELAY_SET(x) (((x) << 0) & 0x00000fff)
-#define PHY_BB_SEARCH_START_DELAY_ENABLE_FLT_SVD_MSB 12
-#define PHY_BB_SEARCH_START_DELAY_ENABLE_FLT_SVD_LSB 12
-#define PHY_BB_SEARCH_START_DELAY_ENABLE_FLT_SVD_MASK 0x00001000
-#define PHY_BB_SEARCH_START_DELAY_ENABLE_FLT_SVD_GET(x) (((x) & 0x00001000) >> 12)
-#define PHY_BB_SEARCH_START_DELAY_ENABLE_FLT_SVD_SET(x) (((x) << 12) & 0x00001000)
-#define PHY_BB_SEARCH_START_DELAY_ENABLE_SEND_CHAN_MSB 13
-#define PHY_BB_SEARCH_START_DELAY_ENABLE_SEND_CHAN_LSB 13
-#define PHY_BB_SEARCH_START_DELAY_ENABLE_SEND_CHAN_MASK 0x00002000
-#define PHY_BB_SEARCH_START_DELAY_ENABLE_SEND_CHAN_GET(x) (((x) & 0x00002000) >> 13)
-#define PHY_BB_SEARCH_START_DELAY_ENABLE_SEND_CHAN_SET(x) (((x) << 13) & 0x00002000)
-
-/* macros for BB_max_rx_length */
-#define PHY_BB_MAX_RX_LENGTH_ADDRESS 0x0000991c
-#define PHY_BB_MAX_RX_LENGTH_OFFSET 0x0000991c
-#define PHY_BB_MAX_RX_LENGTH_MAX_RX_LENGTH_MSB 11
-#define PHY_BB_MAX_RX_LENGTH_MAX_RX_LENGTH_LSB 0
-#define PHY_BB_MAX_RX_LENGTH_MAX_RX_LENGTH_MASK 0x00000fff
-#define PHY_BB_MAX_RX_LENGTH_MAX_RX_LENGTH_GET(x) (((x) & 0x00000fff) >> 0)
-#define PHY_BB_MAX_RX_LENGTH_MAX_RX_LENGTH_SET(x) (((x) << 0) & 0x00000fff)
-#define PHY_BB_MAX_RX_LENGTH_MAX_HT_LENGTH_MSB 29
-#define PHY_BB_MAX_RX_LENGTH_MAX_HT_LENGTH_LSB 12
-#define PHY_BB_MAX_RX_LENGTH_MAX_HT_LENGTH_MASK 0x3ffff000
-#define PHY_BB_MAX_RX_LENGTH_MAX_HT_LENGTH_GET(x) (((x) & 0x3ffff000) >> 12)
-#define PHY_BB_MAX_RX_LENGTH_MAX_HT_LENGTH_SET(x) (((x) << 12) & 0x3ffff000)
-
-/* macros for BB_timing_control_4 */
-#define PHY_BB_TIMING_CONTROL_4_ADDRESS 0x00009920
-#define PHY_BB_TIMING_CONTROL_4_OFFSET 0x00009920
-#define PHY_BB_TIMING_CONTROL_4_CAL_LG_COUNT_MAX_MSB 15
-#define PHY_BB_TIMING_CONTROL_4_CAL_LG_COUNT_MAX_LSB 12
-#define PHY_BB_TIMING_CONTROL_4_CAL_LG_COUNT_MAX_MASK 0x0000f000
-#define PHY_BB_TIMING_CONTROL_4_CAL_LG_COUNT_MAX_GET(x) (((x) & 0x0000f000) >> 12)
-#define PHY_BB_TIMING_CONTROL_4_CAL_LG_COUNT_MAX_SET(x) (((x) << 12) & 0x0000f000)
-#define PHY_BB_TIMING_CONTROL_4_DO_GAIN_DC_IQ_CAL_MSB 16
-#define PHY_BB_TIMING_CONTROL_4_DO_GAIN_DC_IQ_CAL_LSB 16
-#define PHY_BB_TIMING_CONTROL_4_DO_GAIN_DC_IQ_CAL_MASK 0x00010000
-#define PHY_BB_TIMING_CONTROL_4_DO_GAIN_DC_IQ_CAL_GET(x) (((x) & 0x00010000) >> 16)
-#define PHY_BB_TIMING_CONTROL_4_DO_GAIN_DC_IQ_CAL_SET(x) (((x) << 16) & 0x00010000)
-#define PHY_BB_TIMING_CONTROL_4_USE_PILOT_TRACK_DF_MSB 20
-#define PHY_BB_TIMING_CONTROL_4_USE_PILOT_TRACK_DF_LSB 17
-#define PHY_BB_TIMING_CONTROL_4_USE_PILOT_TRACK_DF_MASK 0x001e0000
-#define PHY_BB_TIMING_CONTROL_4_USE_PILOT_TRACK_DF_GET(x) (((x) & 0x001e0000) >> 17)
-#define PHY_BB_TIMING_CONTROL_4_USE_PILOT_TRACK_DF_SET(x) (((x) << 17) & 0x001e0000)
-#define PHY_BB_TIMING_CONTROL_4_EARLY_TRIGGER_THR_MSB 27
-#define PHY_BB_TIMING_CONTROL_4_EARLY_TRIGGER_THR_LSB 21
-#define PHY_BB_TIMING_CONTROL_4_EARLY_TRIGGER_THR_MASK 0x0fe00000
-#define PHY_BB_TIMING_CONTROL_4_EARLY_TRIGGER_THR_GET(x) (((x) & 0x0fe00000) >> 21)
-#define PHY_BB_TIMING_CONTROL_4_EARLY_TRIGGER_THR_SET(x) (((x) << 21) & 0x0fe00000)
-#define PHY_BB_TIMING_CONTROL_4_ENABLE_PILOT_MASK_MSB 28
-#define PHY_BB_TIMING_CONTROL_4_ENABLE_PILOT_MASK_LSB 28
-#define PHY_BB_TIMING_CONTROL_4_ENABLE_PILOT_MASK_MASK 0x10000000
-#define PHY_BB_TIMING_CONTROL_4_ENABLE_PILOT_MASK_GET(x) (((x) & 0x10000000) >> 28)
-#define PHY_BB_TIMING_CONTROL_4_ENABLE_PILOT_MASK_SET(x) (((x) << 28) & 0x10000000)
-#define PHY_BB_TIMING_CONTROL_4_ENABLE_CHAN_MASK_MSB 29
-#define PHY_BB_TIMING_CONTROL_4_ENABLE_CHAN_MASK_LSB 29
-#define PHY_BB_TIMING_CONTROL_4_ENABLE_CHAN_MASK_MASK 0x20000000
-#define PHY_BB_TIMING_CONTROL_4_ENABLE_CHAN_MASK_GET(x) (((x) & 0x20000000) >> 29)
-#define PHY_BB_TIMING_CONTROL_4_ENABLE_CHAN_MASK_SET(x) (((x) << 29) & 0x20000000)
-#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_FILTER_MSB 30
-#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_FILTER_LSB 30
-#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_FILTER_MASK 0x40000000
-#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_FILTER_GET(x) (((x) & 0x40000000) >> 30)
-#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_FILTER_SET(x) (((x) << 30) & 0x40000000)
-#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_RSSI_MSB 31
-#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_RSSI_LSB 31
-#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_RSSI_MASK 0x80000000
-#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_RSSI_GET(x) (((x) & 0x80000000) >> 31)
-#define PHY_BB_TIMING_CONTROL_4_ENABLE_SPUR_RSSI_SET(x) (((x) << 31) & 0x80000000)
-
-/* macros for BB_timing_control_5 */
-#define PHY_BB_TIMING_CONTROL_5_ADDRESS 0x00009924
-#define PHY_BB_TIMING_CONTROL_5_OFFSET 0x00009924
-#define PHY_BB_TIMING_CONTROL_5_ENABLE_CYCPWR_THR1_MSB 0
-#define PHY_BB_TIMING_CONTROL_5_ENABLE_CYCPWR_THR1_LSB 0
-#define PHY_BB_TIMING_CONTROL_5_ENABLE_CYCPWR_THR1_MASK 0x00000001
-#define PHY_BB_TIMING_CONTROL_5_ENABLE_CYCPWR_THR1_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_BB_TIMING_CONTROL_5_ENABLE_CYCPWR_THR1_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_BB_TIMING_CONTROL_5_CYCPWR_THR1_MSB 7
-#define PHY_BB_TIMING_CONTROL_5_CYCPWR_THR1_LSB 1
-#define PHY_BB_TIMING_CONTROL_5_CYCPWR_THR1_MASK 0x000000fe
-#define PHY_BB_TIMING_CONTROL_5_CYCPWR_THR1_GET(x) (((x) & 0x000000fe) >> 1)
-#define PHY_BB_TIMING_CONTROL_5_CYCPWR_THR1_SET(x) (((x) << 1) & 0x000000fe)
-#define PHY_BB_TIMING_CONTROL_5_ENABLE_RSSI_THR1A_MSB 15
-#define PHY_BB_TIMING_CONTROL_5_ENABLE_RSSI_THR1A_LSB 15
-#define PHY_BB_TIMING_CONTROL_5_ENABLE_RSSI_THR1A_MASK 0x00008000
-#define PHY_BB_TIMING_CONTROL_5_ENABLE_RSSI_THR1A_GET(x) (((x) & 0x00008000) >> 15)
-#define PHY_BB_TIMING_CONTROL_5_ENABLE_RSSI_THR1A_SET(x) (((x) << 15) & 0x00008000)
-#define PHY_BB_TIMING_CONTROL_5_RSSI_THR1A_MSB 22
-#define PHY_BB_TIMING_CONTROL_5_RSSI_THR1A_LSB 16
-#define PHY_BB_TIMING_CONTROL_5_RSSI_THR1A_MASK 0x007f0000
-#define PHY_BB_TIMING_CONTROL_5_RSSI_THR1A_GET(x) (((x) & 0x007f0000) >> 16)
-#define PHY_BB_TIMING_CONTROL_5_RSSI_THR1A_SET(x) (((x) << 16) & 0x007f0000)
-#define PHY_BB_TIMING_CONTROL_5_LONG_SC_THRESH_HI_RSSI_MSB 29
-#define PHY_BB_TIMING_CONTROL_5_LONG_SC_THRESH_HI_RSSI_LSB 23
-#define PHY_BB_TIMING_CONTROL_5_LONG_SC_THRESH_HI_RSSI_MASK 0x3f800000
-#define PHY_BB_TIMING_CONTROL_5_LONG_SC_THRESH_HI_RSSI_GET(x) (((x) & 0x3f800000) >> 23)
-#define PHY_BB_TIMING_CONTROL_5_LONG_SC_THRESH_HI_RSSI_SET(x) (((x) << 23) & 0x3f800000)
-#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_MSB 30
-#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_LSB 30
-#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_MASK 0x40000000
-#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_GET(x) (((x) & 0x40000000) >> 30)
-#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_SET(x) (((x) << 30) & 0x40000000)
-#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_EN_MSB 31
-#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_EN_LSB 31
-#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_EN_MASK 0x80000000
-#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_EN_GET(x) (((x) & 0x80000000) >> 31)
-#define PHY_BB_TIMING_CONTROL_5_FORCED_AGC_STR_PRI_EN_SET(x) (((x) << 31) & 0x80000000)
-
-/* macros for BB_phyonly_warm_reset */
-#define PHY_BB_PHYONLY_WARM_RESET_ADDRESS 0x00009928
-#define PHY_BB_PHYONLY_WARM_RESET_OFFSET 0x00009928
-#define PHY_BB_PHYONLY_WARM_RESET_PHYONLY_RST_WARM_L_MSB 0
-#define PHY_BB_PHYONLY_WARM_RESET_PHYONLY_RST_WARM_L_LSB 0
-#define PHY_BB_PHYONLY_WARM_RESET_PHYONLY_RST_WARM_L_MASK 0x00000001
-#define PHY_BB_PHYONLY_WARM_RESET_PHYONLY_RST_WARM_L_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_BB_PHYONLY_WARM_RESET_PHYONLY_RST_WARM_L_SET(x) (((x) << 0) & 0x00000001)
-
-/* macros for BB_phyonly_control */
-#define PHY_BB_PHYONLY_CONTROL_ADDRESS 0x0000992c
-#define PHY_BB_PHYONLY_CONTROL_OFFSET 0x0000992c
-#define PHY_BB_PHYONLY_CONTROL_RX_DRAIN_RATE_MSB 0
-#define PHY_BB_PHYONLY_CONTROL_RX_DRAIN_RATE_LSB 0
-#define PHY_BB_PHYONLY_CONTROL_RX_DRAIN_RATE_MASK 0x00000001
-#define PHY_BB_PHYONLY_CONTROL_RX_DRAIN_RATE_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_BB_PHYONLY_CONTROL_RX_DRAIN_RATE_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_BB_PHYONLY_CONTROL_LATE_TX_SIGNAL_SYMBOL_MSB 1
-#define PHY_BB_PHYONLY_CONTROL_LATE_TX_SIGNAL_SYMBOL_LSB 1
-#define PHY_BB_PHYONLY_CONTROL_LATE_TX_SIGNAL_SYMBOL_MASK 0x00000002
-#define PHY_BB_PHYONLY_CONTROL_LATE_TX_SIGNAL_SYMBOL_GET(x) (((x) & 0x00000002) >> 1)
-#define PHY_BB_PHYONLY_CONTROL_LATE_TX_SIGNAL_SYMBOL_SET(x) (((x) << 1) & 0x00000002)
-#define PHY_BB_PHYONLY_CONTROL_GENERATE_SCRAMBLER_MSB 2
-#define PHY_BB_PHYONLY_CONTROL_GENERATE_SCRAMBLER_LSB 2
-#define PHY_BB_PHYONLY_CONTROL_GENERATE_SCRAMBLER_MASK 0x00000004
-#define PHY_BB_PHYONLY_CONTROL_GENERATE_SCRAMBLER_GET(x) (((x) & 0x00000004) >> 2)
-#define PHY_BB_PHYONLY_CONTROL_GENERATE_SCRAMBLER_SET(x) (((x) << 2) & 0x00000004)
-#define PHY_BB_PHYONLY_CONTROL_TX_ANTENNA_SELECT_MSB 3
-#define PHY_BB_PHYONLY_CONTROL_TX_ANTENNA_SELECT_LSB 3
-#define PHY_BB_PHYONLY_CONTROL_TX_ANTENNA_SELECT_MASK 0x00000008
-#define PHY_BB_PHYONLY_CONTROL_TX_ANTENNA_SELECT_GET(x) (((x) & 0x00000008) >> 3)
-#define PHY_BB_PHYONLY_CONTROL_TX_ANTENNA_SELECT_SET(x) (((x) << 3) & 0x00000008)
-#define PHY_BB_PHYONLY_CONTROL_STATIC_TX_ANTENNA_MSB 4
-#define PHY_BB_PHYONLY_CONTROL_STATIC_TX_ANTENNA_LSB 4
-#define PHY_BB_PHYONLY_CONTROL_STATIC_TX_ANTENNA_MASK 0x00000010
-#define PHY_BB_PHYONLY_CONTROL_STATIC_TX_ANTENNA_GET(x) (((x) & 0x00000010) >> 4)
-#define PHY_BB_PHYONLY_CONTROL_STATIC_TX_ANTENNA_SET(x) (((x) << 4) & 0x00000010)
-#define PHY_BB_PHYONLY_CONTROL_RX_ANTENNA_SELECT_MSB 5
-#define PHY_BB_PHYONLY_CONTROL_RX_ANTENNA_SELECT_LSB 5
-#define PHY_BB_PHYONLY_CONTROL_RX_ANTENNA_SELECT_MASK 0x00000020
-#define PHY_BB_PHYONLY_CONTROL_RX_ANTENNA_SELECT_GET(x) (((x) & 0x00000020) >> 5)
-#define PHY_BB_PHYONLY_CONTROL_RX_ANTENNA_SELECT_SET(x) (((x) << 5) & 0x00000020)
-#define PHY_BB_PHYONLY_CONTROL_STATIC_RX_ANTENNA_MSB 6
-#define PHY_BB_PHYONLY_CONTROL_STATIC_RX_ANTENNA_LSB 6
-#define PHY_BB_PHYONLY_CONTROL_STATIC_RX_ANTENNA_MASK 0x00000040
-#define PHY_BB_PHYONLY_CONTROL_STATIC_RX_ANTENNA_GET(x) (((x) & 0x00000040) >> 6)
-#define PHY_BB_PHYONLY_CONTROL_STATIC_RX_ANTENNA_SET(x) (((x) << 6) & 0x00000040)
-#define PHY_BB_PHYONLY_CONTROL_EN_LOW_FREQ_SLEEP_MSB 7
-#define PHY_BB_PHYONLY_CONTROL_EN_LOW_FREQ_SLEEP_LSB 7
-#define PHY_BB_PHYONLY_CONTROL_EN_LOW_FREQ_SLEEP_MASK 0x00000080
-#define PHY_BB_PHYONLY_CONTROL_EN_LOW_FREQ_SLEEP_GET(x) (((x) & 0x00000080) >> 7)
-#define PHY_BB_PHYONLY_CONTROL_EN_LOW_FREQ_SLEEP_SET(x) (((x) << 7) & 0x00000080)
-
-/* macros for BB_powertx_rate1 */
-#define PHY_BB_POWERTX_RATE1_ADDRESS 0x00009934
-#define PHY_BB_POWERTX_RATE1_OFFSET 0x00009934
-#define PHY_BB_POWERTX_RATE1_POWERTX_0_MSB 5
-#define PHY_BB_POWERTX_RATE1_POWERTX_0_LSB 0
-#define PHY_BB_POWERTX_RATE1_POWERTX_0_MASK 0x0000003f
-#define PHY_BB_POWERTX_RATE1_POWERTX_0_GET(x) (((x) & 0x0000003f) >> 0)
-#define PHY_BB_POWERTX_RATE1_POWERTX_0_SET(x) (((x) << 0) & 0x0000003f)
-#define PHY_BB_POWERTX_RATE1_POWERTX_1_MSB 13
-#define PHY_BB_POWERTX_RATE1_POWERTX_1_LSB 8
-#define PHY_BB_POWERTX_RATE1_POWERTX_1_MASK 0x00003f00
-#define PHY_BB_POWERTX_RATE1_POWERTX_1_GET(x) (((x) & 0x00003f00) >> 8)
-#define PHY_BB_POWERTX_RATE1_POWERTX_1_SET(x) (((x) << 8) & 0x00003f00)
-#define PHY_BB_POWERTX_RATE1_POWERTX_2_MSB 21
-#define PHY_BB_POWERTX_RATE1_POWERTX_2_LSB 16
-#define PHY_BB_POWERTX_RATE1_POWERTX_2_MASK 0x003f0000
-#define PHY_BB_POWERTX_RATE1_POWERTX_2_GET(x) (((x) & 0x003f0000) >> 16)
-#define PHY_BB_POWERTX_RATE1_POWERTX_2_SET(x) (((x) << 16) & 0x003f0000)
-#define PHY_BB_POWERTX_RATE1_POWERTX_3_MSB 29
-#define PHY_BB_POWERTX_RATE1_POWERTX_3_LSB 24
-#define PHY_BB_POWERTX_RATE1_POWERTX_3_MASK 0x3f000000
-#define PHY_BB_POWERTX_RATE1_POWERTX_3_GET(x) (((x) & 0x3f000000) >> 24)
-#define PHY_BB_POWERTX_RATE1_POWERTX_3_SET(x) (((x) << 24) & 0x3f000000)
-
-/* macros for BB_powertx_rate2 */
-#define PHY_BB_POWERTX_RATE2_ADDRESS 0x00009938
-#define PHY_BB_POWERTX_RATE2_OFFSET 0x00009938
-#define PHY_BB_POWERTX_RATE2_POWERTX_4_MSB 5
-#define PHY_BB_POWERTX_RATE2_POWERTX_4_LSB 0
-#define PHY_BB_POWERTX_RATE2_POWERTX_4_MASK 0x0000003f
-#define PHY_BB_POWERTX_RATE2_POWERTX_4_GET(x) (((x) & 0x0000003f) >> 0)
-#define PHY_BB_POWERTX_RATE2_POWERTX_4_SET(x) (((x) << 0) & 0x0000003f)
-#define PHY_BB_POWERTX_RATE2_POWERTX_5_MSB 13
-#define PHY_BB_POWERTX_RATE2_POWERTX_5_LSB 8
-#define PHY_BB_POWERTX_RATE2_POWERTX_5_MASK 0x00003f00
-#define PHY_BB_POWERTX_RATE2_POWERTX_5_GET(x) (((x) & 0x00003f00) >> 8)
-#define PHY_BB_POWERTX_RATE2_POWERTX_5_SET(x) (((x) << 8) & 0x00003f00)
-#define PHY_BB_POWERTX_RATE2_POWERTX_6_MSB 21
-#define PHY_BB_POWERTX_RATE2_POWERTX_6_LSB 16
-#define PHY_BB_POWERTX_RATE2_POWERTX_6_MASK 0x003f0000
-#define PHY_BB_POWERTX_RATE2_POWERTX_6_GET(x) (((x) & 0x003f0000) >> 16)
-#define PHY_BB_POWERTX_RATE2_POWERTX_6_SET(x) (((x) << 16) & 0x003f0000)
-#define PHY_BB_POWERTX_RATE2_POWERTX_7_MSB 29
-#define PHY_BB_POWERTX_RATE2_POWERTX_7_LSB 24
-#define PHY_BB_POWERTX_RATE2_POWERTX_7_MASK 0x3f000000
-#define PHY_BB_POWERTX_RATE2_POWERTX_7_GET(x) (((x) & 0x3f000000) >> 24)
-#define PHY_BB_POWERTX_RATE2_POWERTX_7_SET(x) (((x) << 24) & 0x3f000000)
-
-/* macros for BB_powertx_max */
-#define PHY_BB_POWERTX_MAX_ADDRESS 0x0000993c
-#define PHY_BB_POWERTX_MAX_OFFSET 0x0000993c
-#define PHY_BB_POWERTX_MAX_USE_PER_PACKET_POWERTX_MAX_MSB 6
-#define PHY_BB_POWERTX_MAX_USE_PER_PACKET_POWERTX_MAX_LSB 6
-#define PHY_BB_POWERTX_MAX_USE_PER_PACKET_POWERTX_MAX_MASK 0x00000040
-#define PHY_BB_POWERTX_MAX_USE_PER_PACKET_POWERTX_MAX_GET(x) (((x) & 0x00000040) >> 6)
-#define PHY_BB_POWERTX_MAX_USE_PER_PACKET_POWERTX_MAX_SET(x) (((x) << 6) & 0x00000040)
-
-/* macros for BB_extension_radar */
-#define PHY_BB_EXTENSION_RADAR_ADDRESS 0x00009940
-#define PHY_BB_EXTENSION_RADAR_OFFSET 0x00009940
-#define PHY_BB_EXTENSION_RADAR_BLOCKER40_MAX_RADAR_MSB 13
-#define PHY_BB_EXTENSION_RADAR_BLOCKER40_MAX_RADAR_LSB 8
-#define PHY_BB_EXTENSION_RADAR_BLOCKER40_MAX_RADAR_MASK 0x00003f00
-#define PHY_BB_EXTENSION_RADAR_BLOCKER40_MAX_RADAR_GET(x) (((x) & 0x00003f00) >> 8)
-#define PHY_BB_EXTENSION_RADAR_BLOCKER40_MAX_RADAR_SET(x) (((x) << 8) & 0x00003f00)
-#define PHY_BB_EXTENSION_RADAR_ENABLE_EXT_RADAR_MSB 14
-#define PHY_BB_EXTENSION_RADAR_ENABLE_EXT_RADAR_LSB 14
-#define PHY_BB_EXTENSION_RADAR_ENABLE_EXT_RADAR_MASK 0x00004000
-#define PHY_BB_EXTENSION_RADAR_ENABLE_EXT_RADAR_GET(x) (((x) & 0x00004000) >> 14)
-#define PHY_BB_EXTENSION_RADAR_ENABLE_EXT_RADAR_SET(x) (((x) << 14) & 0x00004000)
-#define PHY_BB_EXTENSION_RADAR_RADAR_DC_PWR_THRESH_MSB 22
-#define PHY_BB_EXTENSION_RADAR_RADAR_DC_PWR_THRESH_LSB 15
-#define PHY_BB_EXTENSION_RADAR_RADAR_DC_PWR_THRESH_MASK 0x007f8000
-#define PHY_BB_EXTENSION_RADAR_RADAR_DC_PWR_THRESH_GET(x) (((x) & 0x007f8000) >> 15)
-#define PHY_BB_EXTENSION_RADAR_RADAR_DC_PWR_THRESH_SET(x) (((x) << 15) & 0x007f8000)
-#define PHY_BB_EXTENSION_RADAR_RADAR_LB_DC_CAP_MSB 30
-#define PHY_BB_EXTENSION_RADAR_RADAR_LB_DC_CAP_LSB 23
-#define PHY_BB_EXTENSION_RADAR_RADAR_LB_DC_CAP_MASK 0x7f800000
-#define PHY_BB_EXTENSION_RADAR_RADAR_LB_DC_CAP_GET(x) (((x) & 0x7f800000) >> 23)
-#define PHY_BB_EXTENSION_RADAR_RADAR_LB_DC_CAP_SET(x) (((x) << 23) & 0x7f800000)
-#define PHY_BB_EXTENSION_RADAR_DISABLE_ADCSAT_HOLD_MSB 31
-#define PHY_BB_EXTENSION_RADAR_DISABLE_ADCSAT_HOLD_LSB 31
-#define PHY_BB_EXTENSION_RADAR_DISABLE_ADCSAT_HOLD_MASK 0x80000000
-#define PHY_BB_EXTENSION_RADAR_DISABLE_ADCSAT_HOLD_GET(x) (((x) & 0x80000000) >> 31)
-#define PHY_BB_EXTENSION_RADAR_DISABLE_ADCSAT_HOLD_SET(x) (((x) << 31) & 0x80000000)
-
-/* macros for BB_frame_control */
-#define PHY_BB_FRAME_CONTROL_ADDRESS 0x00009944
-#define PHY_BB_FRAME_CONTROL_OFFSET 0x00009944
-#define PHY_BB_FRAME_CONTROL_CF_OVERLAP_WINDOW_MSB 1
-#define PHY_BB_FRAME_CONTROL_CF_OVERLAP_WINDOW_LSB 0
-#define PHY_BB_FRAME_CONTROL_CF_OVERLAP_WINDOW_MASK 0x00000003
-#define PHY_BB_FRAME_CONTROL_CF_OVERLAP_WINDOW_GET(x) (((x) & 0x00000003) >> 0)
-#define PHY_BB_FRAME_CONTROL_CF_OVERLAP_WINDOW_SET(x) (((x) << 0) & 0x00000003)
-#define PHY_BB_FRAME_CONTROL_CF_SCALE_SHORT_MSB 2
-#define PHY_BB_FRAME_CONTROL_CF_SCALE_SHORT_LSB 2
-#define PHY_BB_FRAME_CONTROL_CF_SCALE_SHORT_MASK 0x00000004
-#define PHY_BB_FRAME_CONTROL_CF_SCALE_SHORT_GET(x) (((x) & 0x00000004) >> 2)
-#define PHY_BB_FRAME_CONTROL_CF_SCALE_SHORT_SET(x) (((x) << 2) & 0x00000004)
-#define PHY_BB_FRAME_CONTROL_CF_TX_CLIP_MSB 5
-#define PHY_BB_FRAME_CONTROL_CF_TX_CLIP_LSB 3
-#define PHY_BB_FRAME_CONTROL_CF_TX_CLIP_MASK 0x00000038
-#define PHY_BB_FRAME_CONTROL_CF_TX_CLIP_GET(x) (((x) & 0x00000038) >> 3)
-#define PHY_BB_FRAME_CONTROL_CF_TX_CLIP_SET(x) (((x) << 3) & 0x00000038)
-#define PHY_BB_FRAME_CONTROL_CF_TX_DOUBLESAMP_DAC_MSB 7
-#define PHY_BB_FRAME_CONTROL_CF_TX_DOUBLESAMP_DAC_LSB 6
-#define PHY_BB_FRAME_CONTROL_CF_TX_DOUBLESAMP_DAC_MASK 0x000000c0
-#define PHY_BB_FRAME_CONTROL_CF_TX_DOUBLESAMP_DAC_GET(x) (((x) & 0x000000c0) >> 6)
-#define PHY_BB_FRAME_CONTROL_CF_TX_DOUBLESAMP_DAC_SET(x) (((x) << 6) & 0x000000c0)
-#define PHY_BB_FRAME_CONTROL_TX_END_ADJUST_MSB 15
-#define PHY_BB_FRAME_CONTROL_TX_END_ADJUST_LSB 8
-#define PHY_BB_FRAME_CONTROL_TX_END_ADJUST_MASK 0x0000ff00
-#define PHY_BB_FRAME_CONTROL_TX_END_ADJUST_GET(x) (((x) & 0x0000ff00) >> 8)
-#define PHY_BB_FRAME_CONTROL_TX_END_ADJUST_SET(x) (((x) << 8) & 0x0000ff00)
-#define PHY_BB_FRAME_CONTROL_PREPEND_CHAN_INFO_MSB 16
-#define PHY_BB_FRAME_CONTROL_PREPEND_CHAN_INFO_LSB 16
-#define PHY_BB_FRAME_CONTROL_PREPEND_CHAN_INFO_MASK 0x00010000
-#define PHY_BB_FRAME_CONTROL_PREPEND_CHAN_INFO_GET(x) (((x) & 0x00010000) >> 16)
-#define PHY_BB_FRAME_CONTROL_PREPEND_CHAN_INFO_SET(x) (((x) << 16) & 0x00010000)
-#define PHY_BB_FRAME_CONTROL_SHORT_HIGH_PAR_NORM_MSB 17
-#define PHY_BB_FRAME_CONTROL_SHORT_HIGH_PAR_NORM_LSB 17
-#define PHY_BB_FRAME_CONTROL_SHORT_HIGH_PAR_NORM_MASK 0x00020000
-#define PHY_BB_FRAME_CONTROL_SHORT_HIGH_PAR_NORM_GET(x) (((x) & 0x00020000) >> 17)
-#define PHY_BB_FRAME_CONTROL_SHORT_HIGH_PAR_NORM_SET(x) (((x) << 17) & 0x00020000)
-#define PHY_BB_FRAME_CONTROL_EN_ERR_GREEN_FIELD_MSB 18
-#define PHY_BB_FRAME_CONTROL_EN_ERR_GREEN_FIELD_LSB 18
-#define PHY_BB_FRAME_CONTROL_EN_ERR_GREEN_FIELD_MASK 0x00040000
-#define PHY_BB_FRAME_CONTROL_EN_ERR_GREEN_FIELD_GET(x) (((x) & 0x00040000) >> 18)
-#define PHY_BB_FRAME_CONTROL_EN_ERR_GREEN_FIELD_SET(x) (((x) << 18) & 0x00040000)
-#define PHY_BB_FRAME_CONTROL_EN_ERR_XR_POWER_RATIO_MSB 19
-#define PHY_BB_FRAME_CONTROL_EN_ERR_XR_POWER_RATIO_LSB 19
-#define PHY_BB_FRAME_CONTROL_EN_ERR_XR_POWER_RATIO_MASK 0x00080000
-#define PHY_BB_FRAME_CONTROL_EN_ERR_XR_POWER_RATIO_GET(x) (((x) & 0x00080000) >> 19)
-#define PHY_BB_FRAME_CONTROL_EN_ERR_XR_POWER_RATIO_SET(x) (((x) << 19) & 0x00080000)
-#define PHY_BB_FRAME_CONTROL_EN_ERR_OFDM_XCORR_MSB 20
-#define PHY_BB_FRAME_CONTROL_EN_ERR_OFDM_XCORR_LSB 20
-#define PHY_BB_FRAME_CONTROL_EN_ERR_OFDM_XCORR_MASK 0x00100000
-#define PHY_BB_FRAME_CONTROL_EN_ERR_OFDM_XCORR_GET(x) (((x) & 0x00100000) >> 20)
-#define PHY_BB_FRAME_CONTROL_EN_ERR_OFDM_XCORR_SET(x) (((x) << 20) & 0x00100000)
-#define PHY_BB_FRAME_CONTROL_EN_ERR_LONG_SC_THR_MSB 21
-#define PHY_BB_FRAME_CONTROL_EN_ERR_LONG_SC_THR_LSB 21
-#define PHY_BB_FRAME_CONTROL_EN_ERR_LONG_SC_THR_MASK 0x00200000
-#define PHY_BB_FRAME_CONTROL_EN_ERR_LONG_SC_THR_GET(x) (((x) & 0x00200000) >> 21)
-#define PHY_BB_FRAME_CONTROL_EN_ERR_LONG_SC_THR_SET(x) (((x) << 21) & 0x00200000)
-#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_LONG1_MSB 22
-#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_LONG1_LSB 22
-#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_LONG1_MASK 0x00400000
-#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_LONG1_GET(x) (((x) & 0x00400000) >> 22)
-#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_LONG1_SET(x) (((x) << 22) & 0x00400000)
-#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_EARLY_TRIG_MSB 23
-#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_EARLY_TRIG_LSB 23
-#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_EARLY_TRIG_MASK 0x00800000
-#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_EARLY_TRIG_GET(x) (((x) & 0x00800000) >> 23)
-#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_EARLY_TRIG_SET(x) (((x) << 23) & 0x00800000)
-#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_TIMEOUT_MSB 24
-#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_TIMEOUT_LSB 24
-#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_TIMEOUT_MASK 0x01000000
-#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_TIMEOUT_GET(x) (((x) & 0x01000000) >> 24)
-#define PHY_BB_FRAME_CONTROL_EN_ERR_TIM_TIMEOUT_SET(x) (((x) << 24) & 0x01000000)
-#define PHY_BB_FRAME_CONTROL_EN_ERR_SIGNAL_PARITY_MSB 25
-#define PHY_BB_FRAME_CONTROL_EN_ERR_SIGNAL_PARITY_LSB 25
-#define PHY_BB_FRAME_CONTROL_EN_ERR_SIGNAL_PARITY_MASK 0x02000000
-#define PHY_BB_FRAME_CONTROL_EN_ERR_SIGNAL_PARITY_GET(x) (((x) & 0x02000000) >> 25)
-#define PHY_BB_FRAME_CONTROL_EN_ERR_SIGNAL_PARITY_SET(x) (((x) << 25) & 0x02000000)
-#define PHY_BB_FRAME_CONTROL_EN_ERR_RATE_ILLEGAL_MSB 26
-#define PHY_BB_FRAME_CONTROL_EN_ERR_RATE_ILLEGAL_LSB 26
-#define PHY_BB_FRAME_CONTROL_EN_ERR_RATE_ILLEGAL_MASK 0x04000000
-#define PHY_BB_FRAME_CONTROL_EN_ERR_RATE_ILLEGAL_GET(x) (((x) & 0x04000000) >> 26)
-#define PHY_BB_FRAME_CONTROL_EN_ERR_RATE_ILLEGAL_SET(x) (((x) << 26) & 0x04000000)
-#define PHY_BB_FRAME_CONTROL_EN_ERR_LENGTH_ILLEGAL_MSB 27
-#define PHY_BB_FRAME_CONTROL_EN_ERR_LENGTH_ILLEGAL_LSB 27
-#define PHY_BB_FRAME_CONTROL_EN_ERR_LENGTH_ILLEGAL_MASK 0x08000000
-#define PHY_BB_FRAME_CONTROL_EN_ERR_LENGTH_ILLEGAL_GET(x) (((x) & 0x08000000) >> 27)
-#define PHY_BB_FRAME_CONTROL_EN_ERR_LENGTH_ILLEGAL_SET(x) (((x) << 27) & 0x08000000)
-#define PHY_BB_FRAME_CONTROL_EN_ERR_HT_SERVICE_MSB 28
-#define PHY_BB_FRAME_CONTROL_EN_ERR_HT_SERVICE_LSB 28
-#define PHY_BB_FRAME_CONTROL_EN_ERR_HT_SERVICE_MASK 0x10000000
-#define PHY_BB_FRAME_CONTROL_EN_ERR_HT_SERVICE_GET(x) (((x) & 0x10000000) >> 28)
-#define PHY_BB_FRAME_CONTROL_EN_ERR_HT_SERVICE_SET(x) (((x) << 28) & 0x10000000)
-#define PHY_BB_FRAME_CONTROL_EN_ERR_SERVICE_MSB 29
-#define PHY_BB_FRAME_CONTROL_EN_ERR_SERVICE_LSB 29
-#define PHY_BB_FRAME_CONTROL_EN_ERR_SERVICE_MASK 0x20000000
-#define PHY_BB_FRAME_CONTROL_EN_ERR_SERVICE_GET(x) (((x) & 0x20000000) >> 29)
-#define PHY_BB_FRAME_CONTROL_EN_ERR_SERVICE_SET(x) (((x) << 29) & 0x20000000)
-#define PHY_BB_FRAME_CONTROL_EN_ERR_TX_UNDERRUN_MSB 30
-#define PHY_BB_FRAME_CONTROL_EN_ERR_TX_UNDERRUN_LSB 30
-#define PHY_BB_FRAME_CONTROL_EN_ERR_TX_UNDERRUN_MASK 0x40000000
-#define PHY_BB_FRAME_CONTROL_EN_ERR_TX_UNDERRUN_GET(x) (((x) & 0x40000000) >> 30)
-#define PHY_BB_FRAME_CONTROL_EN_ERR_TX_UNDERRUN_SET(x) (((x) << 30) & 0x40000000)
-#define PHY_BB_FRAME_CONTROL_EN_ERR_RX_ABORT_MSB 31
-#define PHY_BB_FRAME_CONTROL_EN_ERR_RX_ABORT_LSB 31
-#define PHY_BB_FRAME_CONTROL_EN_ERR_RX_ABORT_MASK 0x80000000
-#define PHY_BB_FRAME_CONTROL_EN_ERR_RX_ABORT_GET(x) (((x) & 0x80000000) >> 31)
-#define PHY_BB_FRAME_CONTROL_EN_ERR_RX_ABORT_SET(x) (((x) << 31) & 0x80000000)
-
-/* macros for BB_timing_control_6 */
-#define PHY_BB_TIMING_CONTROL_6_ADDRESS 0x00009948
-#define PHY_BB_TIMING_CONTROL_6_OFFSET 0x00009948
-#define PHY_BB_TIMING_CONTROL_6_HI_RSSI_THRESH_MSB 7
-#define PHY_BB_TIMING_CONTROL_6_HI_RSSI_THRESH_LSB 0
-#define PHY_BB_TIMING_CONTROL_6_HI_RSSI_THRESH_MASK 0x000000ff
-#define PHY_BB_TIMING_CONTROL_6_HI_RSSI_THRESH_GET(x) (((x) & 0x000000ff) >> 0)
-#define PHY_BB_TIMING_CONTROL_6_HI_RSSI_THRESH_SET(x) (((x) << 0) & 0x000000ff)
-#define PHY_BB_TIMING_CONTROL_6_EARLY_TRIGGER_THR_HI_RSSI_MSB 14
-#define PHY_BB_TIMING_CONTROL_6_EARLY_TRIGGER_THR_HI_RSSI_LSB 8
-#define PHY_BB_TIMING_CONTROL_6_EARLY_TRIGGER_THR_HI_RSSI_MASK 0x00007f00
-#define PHY_BB_TIMING_CONTROL_6_EARLY_TRIGGER_THR_HI_RSSI_GET(x) (((x) & 0x00007f00) >> 8)
-#define PHY_BB_TIMING_CONTROL_6_EARLY_TRIGGER_THR_HI_RSSI_SET(x) (((x) << 8) & 0x00007f00)
-#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_MSB 20
-#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_LSB 15
-#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_MASK 0x001f8000
-#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_GET(x) (((x) & 0x001f8000) >> 15)
-#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_SET(x) (((x) << 15) & 0x001f8000)
-#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_HI_RSSI_MSB 27
-#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_HI_RSSI_LSB 21
-#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_HI_RSSI_MASK 0x0fe00000
-#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_HI_RSSI_GET(x) (((x) & 0x0fe00000) >> 21)
-#define PHY_BB_TIMING_CONTROL_6_OFDM_XCORR_THRESH_HI_RSSI_SET(x) (((x) << 21) & 0x0fe00000)
-#define PHY_BB_TIMING_CONTROL_6_LONG_MEDIUM_RATIO_THR_MSB 31
-#define PHY_BB_TIMING_CONTROL_6_LONG_MEDIUM_RATIO_THR_LSB 28
-#define PHY_BB_TIMING_CONTROL_6_LONG_MEDIUM_RATIO_THR_MASK 0xf0000000
-#define PHY_BB_TIMING_CONTROL_6_LONG_MEDIUM_RATIO_THR_GET(x) (((x) & 0xf0000000) >> 28)
-#define PHY_BB_TIMING_CONTROL_6_LONG_MEDIUM_RATIO_THR_SET(x) (((x) << 28) & 0xf0000000)
-
-/* macros for BB_spur_mask_controls */
-#define PHY_BB_SPUR_MASK_CONTROLS_ADDRESS 0x0000994c
-#define PHY_BB_SPUR_MASK_CONTROLS_OFFSET 0x0000994c
-#define PHY_BB_SPUR_MASK_CONTROLS_SPUR_RSSI_THRESH_MSB 7
-#define PHY_BB_SPUR_MASK_CONTROLS_SPUR_RSSI_THRESH_LSB 0
-#define PHY_BB_SPUR_MASK_CONTROLS_SPUR_RSSI_THRESH_MASK 0x000000ff
-#define PHY_BB_SPUR_MASK_CONTROLS_SPUR_RSSI_THRESH_GET(x) (((x) & 0x000000ff) >> 0)
-#define PHY_BB_SPUR_MASK_CONTROLS_SPUR_RSSI_THRESH_SET(x) (((x) << 0) & 0x000000ff)
-#define PHY_BB_SPUR_MASK_CONTROLS_EN_VIT_SPUR_RSSI_MSB 8
-#define PHY_BB_SPUR_MASK_CONTROLS_EN_VIT_SPUR_RSSI_LSB 8
-#define PHY_BB_SPUR_MASK_CONTROLS_EN_VIT_SPUR_RSSI_MASK 0x00000100
-#define PHY_BB_SPUR_MASK_CONTROLS_EN_VIT_SPUR_RSSI_GET(x) (((x) & 0x00000100) >> 8)
-#define PHY_BB_SPUR_MASK_CONTROLS_EN_VIT_SPUR_RSSI_SET(x) (((x) << 8) & 0x00000100)
-#define PHY_BB_SPUR_MASK_CONTROLS_ENABLE_MASK_PPM_MSB 17
-#define PHY_BB_SPUR_MASK_CONTROLS_ENABLE_MASK_PPM_LSB 17
-#define PHY_BB_SPUR_MASK_CONTROLS_ENABLE_MASK_PPM_MASK 0x00020000
-#define PHY_BB_SPUR_MASK_CONTROLS_ENABLE_MASK_PPM_GET(x) (((x) & 0x00020000) >> 17)
-#define PHY_BB_SPUR_MASK_CONTROLS_ENABLE_MASK_PPM_SET(x) (((x) << 17) & 0x00020000)
-#define PHY_BB_SPUR_MASK_CONTROLS_MASK_RATE_CNTL_MSB 25
-#define PHY_BB_SPUR_MASK_CONTROLS_MASK_RATE_CNTL_LSB 18
-#define PHY_BB_SPUR_MASK_CONTROLS_MASK_RATE_CNTL_MASK 0x03fc0000
-#define PHY_BB_SPUR_MASK_CONTROLS_MASK_RATE_CNTL_GET(x) (((x) & 0x03fc0000) >> 18)
-#define PHY_BB_SPUR_MASK_CONTROLS_MASK_RATE_CNTL_SET(x) (((x) << 18) & 0x03fc0000)
-
-/* macros for BB_rx_iq_corr_b0 */
-#define PHY_BB_RX_IQ_CORR_B0_ADDRESS 0x00009950
-#define PHY_BB_RX_IQ_CORR_B0_OFFSET 0x00009950
-#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_Q_COFF_0_MSB 6
-#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_Q_COFF_0_LSB 0
-#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_Q_COFF_0_MASK 0x0000007f
-#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_Q_COFF_0_GET(x) (((x) & 0x0000007f) >> 0)
-#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_Q_COFF_0_SET(x) (((x) << 0) & 0x0000007f)
-#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_I_COFF_0_MSB 13
-#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_I_COFF_0_LSB 7
-#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_I_COFF_0_MASK 0x00003f80
-#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_I_COFF_0_GET(x) (((x) & 0x00003f80) >> 7)
-#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_Q_I_COFF_0_SET(x) (((x) << 7) & 0x00003f80)
-#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_ENABLE_MSB 14
-#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_ENABLE_LSB 14
-#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_ENABLE_MASK 0x00004000
-#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_ENABLE_GET(x) (((x) & 0x00004000) >> 14)
-#define PHY_BB_RX_IQ_CORR_B0_RX_IQCORR_ENABLE_SET(x) (((x) << 14) & 0x00004000)
-#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_Q_COFF_0_MSB 21
-#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_Q_COFF_0_LSB 15
-#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_Q_COFF_0_MASK 0x003f8000
-#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_Q_COFF_0_GET(x) (((x) & 0x003f8000) >> 15)
-#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_Q_COFF_0_SET(x) (((x) << 15) & 0x003f8000)
-#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_I_COFF_0_MSB 28
-#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_I_COFF_0_LSB 22
-#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_I_COFF_0_MASK 0x1fc00000
-#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_I_COFF_0_GET(x) (((x) & 0x1fc00000) >> 22)
-#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_Q_I_COFF_0_SET(x) (((x) << 22) & 0x1fc00000)
-#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_ENABLE_MSB 29
-#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_ENABLE_LSB 29
-#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_ENABLE_MASK 0x20000000
-#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_ENABLE_GET(x) (((x) & 0x20000000) >> 29)
-#define PHY_BB_RX_IQ_CORR_B0_LOOPBACK_IQCORR_ENABLE_SET(x) (((x) << 29) & 0x20000000)
-
-/* macros for BB_radar_detection */
-#define PHY_BB_RADAR_DETECTION_ADDRESS 0x00009954
-#define PHY_BB_RADAR_DETECTION_OFFSET 0x00009954
-#define PHY_BB_RADAR_DETECTION_PULSE_DETECT_ENABLE_MSB 0
-#define PHY_BB_RADAR_DETECTION_PULSE_DETECT_ENABLE_LSB 0
-#define PHY_BB_RADAR_DETECTION_PULSE_DETECT_ENABLE_MASK 0x00000001
-#define PHY_BB_RADAR_DETECTION_PULSE_DETECT_ENABLE_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_BB_RADAR_DETECTION_PULSE_DETECT_ENABLE_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_BB_RADAR_DETECTION_PULSE_IN_BAND_THRESH_MSB 5
-#define PHY_BB_RADAR_DETECTION_PULSE_IN_BAND_THRESH_LSB 1
-#define PHY_BB_RADAR_DETECTION_PULSE_IN_BAND_THRESH_MASK 0x0000003e
-#define PHY_BB_RADAR_DETECTION_PULSE_IN_BAND_THRESH_GET(x) (((x) & 0x0000003e) >> 1)
-#define PHY_BB_RADAR_DETECTION_PULSE_IN_BAND_THRESH_SET(x) (((x) << 1) & 0x0000003e)
-#define PHY_BB_RADAR_DETECTION_PULSE_RSSI_THRESH_MSB 11
-#define PHY_BB_RADAR_DETECTION_PULSE_RSSI_THRESH_LSB 6
-#define PHY_BB_RADAR_DETECTION_PULSE_RSSI_THRESH_MASK 0x00000fc0
-#define PHY_BB_RADAR_DETECTION_PULSE_RSSI_THRESH_GET(x) (((x) & 0x00000fc0) >> 6)
-#define PHY_BB_RADAR_DETECTION_PULSE_RSSI_THRESH_SET(x) (((x) << 6) & 0x00000fc0)
-#define PHY_BB_RADAR_DETECTION_PULSE_HEIGHT_THRESH_MSB 17
-#define PHY_BB_RADAR_DETECTION_PULSE_HEIGHT_THRESH_LSB 12
-#define PHY_BB_RADAR_DETECTION_PULSE_HEIGHT_THRESH_MASK 0x0003f000
-#define PHY_BB_RADAR_DETECTION_PULSE_HEIGHT_THRESH_GET(x) (((x) & 0x0003f000) >> 12)
-#define PHY_BB_RADAR_DETECTION_PULSE_HEIGHT_THRESH_SET(x) (((x) << 12) & 0x0003f000)
-#define PHY_BB_RADAR_DETECTION_RADAR_RSSI_THRESH_MSB 23
-#define PHY_BB_RADAR_DETECTION_RADAR_RSSI_THRESH_LSB 18
-#define PHY_BB_RADAR_DETECTION_RADAR_RSSI_THRESH_MASK 0x00fc0000
-#define PHY_BB_RADAR_DETECTION_RADAR_RSSI_THRESH_GET(x) (((x) & 0x00fc0000) >> 18)
-#define PHY_BB_RADAR_DETECTION_RADAR_RSSI_THRESH_SET(x) (((x) << 18) & 0x00fc0000)
-#define PHY_BB_RADAR_DETECTION_RADAR_FIRPWR_THRESH_MSB 30
-#define PHY_BB_RADAR_DETECTION_RADAR_FIRPWR_THRESH_LSB 24
-#define PHY_BB_RADAR_DETECTION_RADAR_FIRPWR_THRESH_MASK 0x7f000000
-#define PHY_BB_RADAR_DETECTION_RADAR_FIRPWR_THRESH_GET(x) (((x) & 0x7f000000) >> 24)
-#define PHY_BB_RADAR_DETECTION_RADAR_FIRPWR_THRESH_SET(x) (((x) << 24) & 0x7f000000)
-#define PHY_BB_RADAR_DETECTION_ENABLE_RADAR_FFT_MSB 31
-#define PHY_BB_RADAR_DETECTION_ENABLE_RADAR_FFT_LSB 31
-#define PHY_BB_RADAR_DETECTION_ENABLE_RADAR_FFT_MASK 0x80000000
-#define PHY_BB_RADAR_DETECTION_ENABLE_RADAR_FFT_GET(x) (((x) & 0x80000000) >> 31)
-#define PHY_BB_RADAR_DETECTION_ENABLE_RADAR_FFT_SET(x) (((x) << 31) & 0x80000000)
-
-/* macros for BB_radar_detection_2 */
-#define PHY_BB_RADAR_DETECTION_2_ADDRESS 0x00009958
-#define PHY_BB_RADAR_DETECTION_2_OFFSET 0x00009958
-#define PHY_BB_RADAR_DETECTION_2_RADAR_LENGTH_MAX_MSB 7
-#define PHY_BB_RADAR_DETECTION_2_RADAR_LENGTH_MAX_LSB 0
-#define PHY_BB_RADAR_DETECTION_2_RADAR_LENGTH_MAX_MASK 0x000000ff
-#define PHY_BB_RADAR_DETECTION_2_RADAR_LENGTH_MAX_GET(x) (((x) & 0x000000ff) >> 0)
-#define PHY_BB_RADAR_DETECTION_2_RADAR_LENGTH_MAX_SET(x) (((x) << 0) & 0x000000ff)
-#define PHY_BB_RADAR_DETECTION_2_PULSE_RELSTEP_THRESH_MSB 12
-#define PHY_BB_RADAR_DETECTION_2_PULSE_RELSTEP_THRESH_LSB 8
-#define PHY_BB_RADAR_DETECTION_2_PULSE_RELSTEP_THRESH_MASK 0x00001f00
-#define PHY_BB_RADAR_DETECTION_2_PULSE_RELSTEP_THRESH_GET(x) (((x) & 0x00001f00) >> 8)
-#define PHY_BB_RADAR_DETECTION_2_PULSE_RELSTEP_THRESH_SET(x) (((x) << 8) & 0x00001f00)
-#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_RELSTEP_CHECK_MSB 13
-#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_RELSTEP_CHECK_LSB 13
-#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_RELSTEP_CHECK_MASK 0x00002000
-#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_RELSTEP_CHECK_GET(x) (((x) & 0x00002000) >> 13)
-#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_RELSTEP_CHECK_SET(x) (((x) << 13) & 0x00002000)
-#define PHY_BB_RADAR_DETECTION_2_ENABLE_MAX_RADAR_RSSI_MSB 14
-#define PHY_BB_RADAR_DETECTION_2_ENABLE_MAX_RADAR_RSSI_LSB 14
-#define PHY_BB_RADAR_DETECTION_2_ENABLE_MAX_RADAR_RSSI_MASK 0x00004000
-#define PHY_BB_RADAR_DETECTION_2_ENABLE_MAX_RADAR_RSSI_GET(x) (((x) & 0x00004000) >> 14)
-#define PHY_BB_RADAR_DETECTION_2_ENABLE_MAX_RADAR_RSSI_SET(x) (((x) << 14) & 0x00004000)
-#define PHY_BB_RADAR_DETECTION_2_ENABLE_BLOCK_RADAR_CHECK_MSB 15
-#define PHY_BB_RADAR_DETECTION_2_ENABLE_BLOCK_RADAR_CHECK_LSB 15
-#define PHY_BB_RADAR_DETECTION_2_ENABLE_BLOCK_RADAR_CHECK_MASK 0x00008000
-#define PHY_BB_RADAR_DETECTION_2_ENABLE_BLOCK_RADAR_CHECK_GET(x) (((x) & 0x00008000) >> 15)
-#define PHY_BB_RADAR_DETECTION_2_ENABLE_BLOCK_RADAR_CHECK_SET(x) (((x) << 15) & 0x00008000)
-#define PHY_BB_RADAR_DETECTION_2_RADAR_RELPWR_THRESH_MSB 21
-#define PHY_BB_RADAR_DETECTION_2_RADAR_RELPWR_THRESH_LSB 16
-#define PHY_BB_RADAR_DETECTION_2_RADAR_RELPWR_THRESH_MASK 0x003f0000
-#define PHY_BB_RADAR_DETECTION_2_RADAR_RELPWR_THRESH_GET(x) (((x) & 0x003f0000) >> 16)
-#define PHY_BB_RADAR_DETECTION_2_RADAR_RELPWR_THRESH_SET(x) (((x) << 16) & 0x003f0000)
-#define PHY_BB_RADAR_DETECTION_2_RADAR_USE_FIRPWR_128_MSB 22
-#define PHY_BB_RADAR_DETECTION_2_RADAR_USE_FIRPWR_128_LSB 22
-#define PHY_BB_RADAR_DETECTION_2_RADAR_USE_FIRPWR_128_MASK 0x00400000
-#define PHY_BB_RADAR_DETECTION_2_RADAR_USE_FIRPWR_128_GET(x) (((x) & 0x00400000) >> 22)
-#define PHY_BB_RADAR_DETECTION_2_RADAR_USE_FIRPWR_128_SET(x) (((x) << 22) & 0x00400000)
-#define PHY_BB_RADAR_DETECTION_2_ENABLE_RADAR_RELPWR_CHECK_MSB 23
-#define PHY_BB_RADAR_DETECTION_2_ENABLE_RADAR_RELPWR_CHECK_LSB 23
-#define PHY_BB_RADAR_DETECTION_2_ENABLE_RADAR_RELPWR_CHECK_MASK 0x00800000
-#define PHY_BB_RADAR_DETECTION_2_ENABLE_RADAR_RELPWR_CHECK_GET(x) (((x) & 0x00800000) >> 23)
-#define PHY_BB_RADAR_DETECTION_2_ENABLE_RADAR_RELPWR_CHECK_SET(x) (((x) << 23) & 0x00800000)
-#define PHY_BB_RADAR_DETECTION_2_CF_RADAR_BIN_THRESH_SEL_MSB 26
-#define PHY_BB_RADAR_DETECTION_2_CF_RADAR_BIN_THRESH_SEL_LSB 24
-#define PHY_BB_RADAR_DETECTION_2_CF_RADAR_BIN_THRESH_SEL_MASK 0x07000000
-#define PHY_BB_RADAR_DETECTION_2_CF_RADAR_BIN_THRESH_SEL_GET(x) (((x) & 0x07000000) >> 24)
-#define PHY_BB_RADAR_DETECTION_2_CF_RADAR_BIN_THRESH_SEL_SET(x) (((x) << 24) & 0x07000000)
-#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_GC_COUNT_CHECK_MSB 27
-#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_GC_COUNT_CHECK_LSB 27
-#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_GC_COUNT_CHECK_MASK 0x08000000
-#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_GC_COUNT_CHECK_GET(x) (((x) & 0x08000000) >> 27)
-#define PHY_BB_RADAR_DETECTION_2_ENABLE_PULSE_GC_COUNT_CHECK_SET(x) (((x) << 27) & 0x08000000)
-
-/* macros for BB_tx_phase_ramp_b0 */
-#define PHY_BB_TX_PHASE_RAMP_B0_ADDRESS 0x0000995c
-#define PHY_BB_TX_PHASE_RAMP_B0_OFFSET 0x0000995c
-#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ENABLE_0_MSB 0
-#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ENABLE_0_LSB 0
-#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ENABLE_0_MASK 0x00000001
-#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ENABLE_0_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ENABLE_0_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_BIAS_0_MSB 6
-#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_BIAS_0_LSB 1
-#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_BIAS_0_MASK 0x0000007e
-#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_BIAS_0_GET(x) (((x) & 0x0000007e) >> 1)
-#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_BIAS_0_SET(x) (((x) << 1) & 0x0000007e)
-#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_INIT_0_MSB 16
-#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_INIT_0_LSB 7
-#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_INIT_0_MASK 0x0001ff80
-#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_INIT_0_GET(x) (((x) & 0x0001ff80) >> 7)
-#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_INIT_0_SET(x) (((x) << 7) & 0x0001ff80)
-#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ALPHA_0_MSB 24
-#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ALPHA_0_LSB 17
-#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ALPHA_0_MASK 0x01fe0000
-#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ALPHA_0_GET(x) (((x) & 0x01fe0000) >> 17)
-#define PHY_BB_TX_PHASE_RAMP_B0_CF_PHASE_RAMP_ALPHA_0_SET(x) (((x) << 17) & 0x01fe0000)
-
-/* macros for BB_switch_table_chn_b0 */
-#define PHY_BB_SWITCH_TABLE_CHN_B0_ADDRESS 0x00009960
-#define PHY_BB_SWITCH_TABLE_CHN_B0_OFFSET 0x00009960
-#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_IDLE_0_MSB 1
-#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_IDLE_0_LSB 0
-#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_IDLE_0_MASK 0x00000003
-#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_IDLE_0_GET(x) (((x) & 0x00000003) >> 0)
-#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_IDLE_0_SET(x) (((x) << 0) & 0x00000003)
-#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_T_0_MSB 3
-#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_T_0_LSB 2
-#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_T_0_MASK 0x0000000c
-#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_T_0_GET(x) (((x) & 0x0000000c) >> 2)
-#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_T_0_SET(x) (((x) << 2) & 0x0000000c)
-#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_R_0_MSB 5
-#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_R_0_LSB 4
-#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_R_0_MASK 0x00000030
-#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_R_0_GET(x) (((x) & 0x00000030) >> 4)
-#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_R_0_SET(x) (((x) << 4) & 0x00000030)
-#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX1_0_MSB 7
-#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX1_0_LSB 6
-#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX1_0_MASK 0x000000c0
-#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX1_0_GET(x) (((x) & 0x000000c0) >> 6)
-#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX1_0_SET(x) (((x) << 6) & 0x000000c0)
-#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX12_0_MSB 9
-#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX12_0_LSB 8
-#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX12_0_MASK 0x00000300
-#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX12_0_GET(x) (((x) & 0x00000300) >> 8)
-#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_RX12_0_SET(x) (((x) << 8) & 0x00000300)
-#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_B_0_MSB 11
-#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_B_0_LSB 10
-#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_B_0_MASK 0x00000c00
-#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_B_0_GET(x) (((x) & 0x00000c00) >> 10)
-#define PHY_BB_SWITCH_TABLE_CHN_B0_SWITCH_TABLE_B_0_SET(x) (((x) << 10) & 0x00000c00)
-
-/* macros for BB_switch_table_com1 */
-#define PHY_BB_SWITCH_TABLE_COM1_ADDRESS 0x00009964
-#define PHY_BB_SWITCH_TABLE_COM1_OFFSET 0x00009964
-#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_IDLE_MSB 3
-#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_IDLE_LSB 0
-#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_IDLE_MASK 0x0000000f
-#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_IDLE_GET(x) (((x) & 0x0000000f) >> 0)
-#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_IDLE_SET(x) (((x) << 0) & 0x0000000f)
-#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T1_MSB 7
-#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T1_LSB 4
-#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T1_MASK 0x000000f0
-#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T1_GET(x) (((x) & 0x000000f0) >> 4)
-#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T1_SET(x) (((x) << 4) & 0x000000f0)
-#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T2_MSB 11
-#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T2_LSB 8
-#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T2_MASK 0x00000f00
-#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T2_GET(x) (((x) & 0x00000f00) >> 8)
-#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_T2_SET(x) (((x) << 8) & 0x00000f00)
-#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_B_MSB 15
-#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_B_LSB 12
-#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_B_MASK 0x0000f000
-#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_B_GET(x) (((x) & 0x0000f000) >> 12)
-#define PHY_BB_SWITCH_TABLE_COM1_SWITCH_TABLE_COM_B_SET(x) (((x) << 12) & 0x0000f000)
-
-/* macros for BB_cca_ctrl_2_b0 */
-#define PHY_BB_CCA_CTRL_2_B0_ADDRESS 0x00009968
-#define PHY_BB_CCA_CTRL_2_B0_OFFSET 0x00009968
-#define PHY_BB_CCA_CTRL_2_B0_MINCCAPWR_THR_0_MSB 8
-#define PHY_BB_CCA_CTRL_2_B0_MINCCAPWR_THR_0_LSB 0
-#define PHY_BB_CCA_CTRL_2_B0_MINCCAPWR_THR_0_MASK 0x000001ff
-#define PHY_BB_CCA_CTRL_2_B0_MINCCAPWR_THR_0_GET(x) (((x) & 0x000001ff) >> 0)
-#define PHY_BB_CCA_CTRL_2_B0_MINCCAPWR_THR_0_SET(x) (((x) << 0) & 0x000001ff)
-#define PHY_BB_CCA_CTRL_2_B0_ENABLE_MINCCAPWR_THR_MSB 9
-#define PHY_BB_CCA_CTRL_2_B0_ENABLE_MINCCAPWR_THR_LSB 9
-#define PHY_BB_CCA_CTRL_2_B0_ENABLE_MINCCAPWR_THR_MASK 0x00000200
-#define PHY_BB_CCA_CTRL_2_B0_ENABLE_MINCCAPWR_THR_GET(x) (((x) & 0x00000200) >> 9)
-#define PHY_BB_CCA_CTRL_2_B0_ENABLE_MINCCAPWR_THR_SET(x) (((x) << 9) & 0x00000200)
-#define PHY_BB_CCA_CTRL_2_B0_NF_GAIN_COMP_0_MSB 17
-#define PHY_BB_CCA_CTRL_2_B0_NF_GAIN_COMP_0_LSB 10
-#define PHY_BB_CCA_CTRL_2_B0_NF_GAIN_COMP_0_MASK 0x0003fc00
-#define PHY_BB_CCA_CTRL_2_B0_NF_GAIN_COMP_0_GET(x) (((x) & 0x0003fc00) >> 10)
-#define PHY_BB_CCA_CTRL_2_B0_NF_GAIN_COMP_0_SET(x) (((x) << 10) & 0x0003fc00)
-#define PHY_BB_CCA_CTRL_2_B0_THRESH62_MODE_MSB 18
-#define PHY_BB_CCA_CTRL_2_B0_THRESH62_MODE_LSB 18
-#define PHY_BB_CCA_CTRL_2_B0_THRESH62_MODE_MASK 0x00040000
-#define PHY_BB_CCA_CTRL_2_B0_THRESH62_MODE_GET(x) (((x) & 0x00040000) >> 18)
-#define PHY_BB_CCA_CTRL_2_B0_THRESH62_MODE_SET(x) (((x) << 18) & 0x00040000)
-
-/* macros for BB_switch_table_com2 */
-#define PHY_BB_SWITCH_TABLE_COM2_ADDRESS 0x0000996c
-#define PHY_BB_SWITCH_TABLE_COM2_OFFSET 0x0000996c
-#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL1_MSB 3
-#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL1_LSB 0
-#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL1_MASK 0x0000000f
-#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL1_GET(x) (((x) & 0x0000000f) >> 0)
-#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL1_SET(x) (((x) << 0) & 0x0000000f)
-#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL1_MSB 7
-#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL1_LSB 4
-#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL1_MASK 0x000000f0
-#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL1_GET(x) (((x) & 0x000000f0) >> 4)
-#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL1_SET(x) (((x) << 4) & 0x000000f0)
-#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL1_MSB 11
-#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL1_LSB 8
-#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL1_MASK 0x00000f00
-#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL1_GET(x) (((x) & 0x00000f00) >> 8)
-#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL1_SET(x) (((x) << 8) & 0x00000f00)
-#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL1_MSB 15
-#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL1_LSB 12
-#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL1_MASK 0x0000f000
-#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL1_GET(x) (((x) & 0x0000f000) >> 12)
-#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL1_SET(x) (((x) << 12) & 0x0000f000)
-#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL2_MSB 19
-#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL2_LSB 16
-#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL2_MASK 0x000f0000
-#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL2_GET(x) (((x) & 0x000f0000) >> 16)
-#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1NXAL2_SET(x) (((x) << 16) & 0x000f0000)
-#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL2_MSB 23
-#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL2_LSB 20
-#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL2_MASK 0x00f00000
-#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL2_GET(x) (((x) & 0x00f00000) >> 20)
-#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2NXAL2_SET(x) (((x) << 20) & 0x00f00000)
-#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL2_MSB 27
-#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL2_LSB 24
-#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL2_MASK 0x0f000000
-#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL2_GET(x) (((x) & 0x0f000000) >> 24)
-#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA1XAL2_SET(x) (((x) << 24) & 0x0f000000)
-#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL2_MSB 31
-#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL2_LSB 28
-#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL2_MASK 0xf0000000
-#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL2_GET(x) (((x) & 0xf0000000) >> 28)
-#define PHY_BB_SWITCH_TABLE_COM2_SWITCH_TABLE_COM_RA2XAL2_SET(x) (((x) << 28) & 0xf0000000)
-
-/* macros for BB_restart */
-#define PHY_BB_RESTART_ADDRESS 0x00009970
-#define PHY_BB_RESTART_OFFSET 0x00009970
-#define PHY_BB_RESTART_ENABLE_RESTART_MSB 0
-#define PHY_BB_RESTART_ENABLE_RESTART_LSB 0
-#define PHY_BB_RESTART_ENABLE_RESTART_MASK 0x00000001
-#define PHY_BB_RESTART_ENABLE_RESTART_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_BB_RESTART_ENABLE_RESTART_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_BB_RESTART_RESTART_LGFIRPWR_DELTA_MSB 5
-#define PHY_BB_RESTART_RESTART_LGFIRPWR_DELTA_LSB 1
-#define PHY_BB_RESTART_RESTART_LGFIRPWR_DELTA_MASK 0x0000003e
-#define PHY_BB_RESTART_RESTART_LGFIRPWR_DELTA_GET(x) (((x) & 0x0000003e) >> 1)
-#define PHY_BB_RESTART_RESTART_LGFIRPWR_DELTA_SET(x) (((x) << 1) & 0x0000003e)
-#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_MSB 6
-#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_LSB 6
-#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_MASK 0x00000040
-#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_GET(x) (((x) & 0x00000040) >> 6)
-#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_SET(x) (((x) << 6) & 0x00000040)
-#define PHY_BB_RESTART_PWRDROP_LGFIRPWR_DELTA_MSB 11
-#define PHY_BB_RESTART_PWRDROP_LGFIRPWR_DELTA_LSB 7
-#define PHY_BB_RESTART_PWRDROP_LGFIRPWR_DELTA_MASK 0x00000f80
-#define PHY_BB_RESTART_PWRDROP_LGFIRPWR_DELTA_GET(x) (((x) & 0x00000f80) >> 7)
-#define PHY_BB_RESTART_PWRDROP_LGFIRPWR_DELTA_SET(x) (((x) << 7) & 0x00000f80)
-#define PHY_BB_RESTART_OFDM_CCK_RSSI_BIAS_MSB 17
-#define PHY_BB_RESTART_OFDM_CCK_RSSI_BIAS_LSB 12
-#define PHY_BB_RESTART_OFDM_CCK_RSSI_BIAS_MASK 0x0003f000
-#define PHY_BB_RESTART_OFDM_CCK_RSSI_BIAS_GET(x) (((x) & 0x0003f000) >> 12)
-#define PHY_BB_RESTART_OFDM_CCK_RSSI_BIAS_SET(x) (((x) << 12) & 0x0003f000)
-#define PHY_BB_RESTART_ANT_FAST_DIV_GC_LIMIT_MSB 20
-#define PHY_BB_RESTART_ANT_FAST_DIV_GC_LIMIT_LSB 18
-#define PHY_BB_RESTART_ANT_FAST_DIV_GC_LIMIT_MASK 0x001c0000
-#define PHY_BB_RESTART_ANT_FAST_DIV_GC_LIMIT_GET(x) (((x) & 0x001c0000) >> 18)
-#define PHY_BB_RESTART_ANT_FAST_DIV_GC_LIMIT_SET(x) (((x) << 18) & 0x001c0000)
-#define PHY_BB_RESTART_ENABLE_ANT_FAST_DIV_M2FLAG_MSB 21
-#define PHY_BB_RESTART_ENABLE_ANT_FAST_DIV_M2FLAG_LSB 21
-#define PHY_BB_RESTART_ENABLE_ANT_FAST_DIV_M2FLAG_MASK 0x00200000
-#define PHY_BB_RESTART_ENABLE_ANT_FAST_DIV_M2FLAG_GET(x) (((x) & 0x00200000) >> 21)
-#define PHY_BB_RESTART_ENABLE_ANT_FAST_DIV_M2FLAG_SET(x) (((x) << 21) & 0x00200000)
-#define PHY_BB_RESTART_WEAK_RSSI_VOTE_THR_MSB 28
-#define PHY_BB_RESTART_WEAK_RSSI_VOTE_THR_LSB 22
-#define PHY_BB_RESTART_WEAK_RSSI_VOTE_THR_MASK 0x1fc00000
-#define PHY_BB_RESTART_WEAK_RSSI_VOTE_THR_GET(x) (((x) & 0x1fc00000) >> 22)
-#define PHY_BB_RESTART_WEAK_RSSI_VOTE_THR_SET(x) (((x) << 22) & 0x1fc00000)
-#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_CCK_MSB 29
-#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_CCK_LSB 29
-#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_CCK_MASK 0x20000000
-#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_CCK_GET(x) (((x) & 0x20000000) >> 29)
-#define PHY_BB_RESTART_ENABLE_PWR_DROP_ERR_CCK_SET(x) (((x) << 29) & 0x20000000)
-#define PHY_BB_RESTART_DISABLE_DC_RESTART_MSB 30
-#define PHY_BB_RESTART_DISABLE_DC_RESTART_LSB 30
-#define PHY_BB_RESTART_DISABLE_DC_RESTART_MASK 0x40000000
-#define PHY_BB_RESTART_DISABLE_DC_RESTART_GET(x) (((x) & 0x40000000) >> 30)
-#define PHY_BB_RESTART_DISABLE_DC_RESTART_SET(x) (((x) << 30) & 0x40000000)
-#define PHY_BB_RESTART_RESTART_MODE_BW40_MSB 31
-#define PHY_BB_RESTART_RESTART_MODE_BW40_LSB 31
-#define PHY_BB_RESTART_RESTART_MODE_BW40_MASK 0x80000000
-#define PHY_BB_RESTART_RESTART_MODE_BW40_GET(x) (((x) & 0x80000000) >> 31)
-#define PHY_BB_RESTART_RESTART_MODE_BW40_SET(x) (((x) << 31) & 0x80000000)
-
-/* macros for BB_scrambler_seed */
-#define PHY_BB_SCRAMBLER_SEED_ADDRESS 0x00009978
-#define PHY_BB_SCRAMBLER_SEED_OFFSET 0x00009978
-#define PHY_BB_SCRAMBLER_SEED_FIXED_SCRAMBLER_SEED_MSB 6
-#define PHY_BB_SCRAMBLER_SEED_FIXED_SCRAMBLER_SEED_LSB 0
-#define PHY_BB_SCRAMBLER_SEED_FIXED_SCRAMBLER_SEED_MASK 0x0000007f
-#define PHY_BB_SCRAMBLER_SEED_FIXED_SCRAMBLER_SEED_GET(x) (((x) & 0x0000007f) >> 0)
-#define PHY_BB_SCRAMBLER_SEED_FIXED_SCRAMBLER_SEED_SET(x) (((x) << 0) & 0x0000007f)
-
-/* macros for BB_rfbus_request */
-#define PHY_BB_RFBUS_REQUEST_ADDRESS 0x0000997c
-#define PHY_BB_RFBUS_REQUEST_OFFSET 0x0000997c
-#define PHY_BB_RFBUS_REQUEST_RFBUS_REQUEST_MSB 0
-#define PHY_BB_RFBUS_REQUEST_RFBUS_REQUEST_LSB 0
-#define PHY_BB_RFBUS_REQUEST_RFBUS_REQUEST_MASK 0x00000001
-#define PHY_BB_RFBUS_REQUEST_RFBUS_REQUEST_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_BB_RFBUS_REQUEST_RFBUS_REQUEST_SET(x) (((x) << 0) & 0x00000001)
-
-/* macros for BB_timing_control_11 */
-#define PHY_BB_TIMING_CONTROL_11_ADDRESS 0x000099a0
-#define PHY_BB_TIMING_CONTROL_11_OFFSET 0x000099a0
-#define PHY_BB_TIMING_CONTROL_11_SPUR_DELTA_PHASE_MSB 19
-#define PHY_BB_TIMING_CONTROL_11_SPUR_DELTA_PHASE_LSB 0
-#define PHY_BB_TIMING_CONTROL_11_SPUR_DELTA_PHASE_MASK 0x000fffff
-#define PHY_BB_TIMING_CONTROL_11_SPUR_DELTA_PHASE_GET(x) (((x) & 0x000fffff) >> 0)
-#define PHY_BB_TIMING_CONTROL_11_SPUR_DELTA_PHASE_SET(x) (((x) << 0) & 0x000fffff)
-#define PHY_BB_TIMING_CONTROL_11_SPUR_FREQ_SD_MSB 29
-#define PHY_BB_TIMING_CONTROL_11_SPUR_FREQ_SD_LSB 20
-#define PHY_BB_TIMING_CONTROL_11_SPUR_FREQ_SD_MASK 0x3ff00000
-#define PHY_BB_TIMING_CONTROL_11_SPUR_FREQ_SD_GET(x) (((x) & 0x3ff00000) >> 20)
-#define PHY_BB_TIMING_CONTROL_11_SPUR_FREQ_SD_SET(x) (((x) << 20) & 0x3ff00000)
-#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_AGC_MSB 30
-#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_AGC_LSB 30
-#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_AGC_MASK 0x40000000
-#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_AGC_GET(x) (((x) & 0x40000000) >> 30)
-#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_AGC_SET(x) (((x) << 30) & 0x40000000)
-#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_SELFCOR_MSB 31
-#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_SELFCOR_LSB 31
-#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_SELFCOR_MASK 0x80000000
-#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_SELFCOR_GET(x) (((x) & 0x80000000) >> 31)
-#define PHY_BB_TIMING_CONTROL_11_USE_SPUR_FILTER_IN_SELFCOR_SET(x) (((x) << 31) & 0x80000000)
-
-/* macros for BB_multichain_enable */
-#define PHY_BB_MULTICHAIN_ENABLE_ADDRESS 0x000099a4
-#define PHY_BB_MULTICHAIN_ENABLE_OFFSET 0x000099a4
-#define PHY_BB_MULTICHAIN_ENABLE_RX_CHAIN_MASK_MSB 2
-#define PHY_BB_MULTICHAIN_ENABLE_RX_CHAIN_MASK_LSB 0
-#define PHY_BB_MULTICHAIN_ENABLE_RX_CHAIN_MASK_MASK 0x00000007
-#define PHY_BB_MULTICHAIN_ENABLE_RX_CHAIN_MASK_GET(x) (((x) & 0x00000007) >> 0)
-#define PHY_BB_MULTICHAIN_ENABLE_RX_CHAIN_MASK_SET(x) (((x) << 0) & 0x00000007)
-
-/* macros for BB_multichain_control */
-#define PHY_BB_MULTICHAIN_CONTROL_ADDRESS 0x000099a8
-#define PHY_BB_MULTICHAIN_CONTROL_OFFSET 0x000099a8
-#define PHY_BB_MULTICHAIN_CONTROL_FORCE_ANALOG_GAIN_DIFF_MSB 0
-#define PHY_BB_MULTICHAIN_CONTROL_FORCE_ANALOG_GAIN_DIFF_LSB 0
-#define PHY_BB_MULTICHAIN_CONTROL_FORCE_ANALOG_GAIN_DIFF_MASK 0x00000001
-#define PHY_BB_MULTICHAIN_CONTROL_FORCE_ANALOG_GAIN_DIFF_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_BB_MULTICHAIN_CONTROL_FORCE_ANALOG_GAIN_DIFF_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_01_MSB 7
-#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_01_LSB 1
-#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_01_MASK 0x000000fe
-#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_01_GET(x) (((x) & 0x000000fe) >> 1)
-#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_01_SET(x) (((x) << 1) & 0x000000fe)
-#define PHY_BB_MULTICHAIN_CONTROL_SYNC_SYNTHON_MSB 8
-#define PHY_BB_MULTICHAIN_CONTROL_SYNC_SYNTHON_LSB 8
-#define PHY_BB_MULTICHAIN_CONTROL_SYNC_SYNTHON_MASK 0x00000100
-#define PHY_BB_MULTICHAIN_CONTROL_SYNC_SYNTHON_GET(x) (((x) & 0x00000100) >> 8)
-#define PHY_BB_MULTICHAIN_CONTROL_SYNC_SYNTHON_SET(x) (((x) << 8) & 0x00000100)
-#define PHY_BB_MULTICHAIN_CONTROL_USE_POSEDGE_REFCLK_MSB 9
-#define PHY_BB_MULTICHAIN_CONTROL_USE_POSEDGE_REFCLK_LSB 9
-#define PHY_BB_MULTICHAIN_CONTROL_USE_POSEDGE_REFCLK_MASK 0x00000200
-#define PHY_BB_MULTICHAIN_CONTROL_USE_POSEDGE_REFCLK_GET(x) (((x) & 0x00000200) >> 9)
-#define PHY_BB_MULTICHAIN_CONTROL_USE_POSEDGE_REFCLK_SET(x) (((x) << 9) & 0x00000200)
-#define PHY_BB_MULTICHAIN_CONTROL_CF_SHORT_SAT_MSB 20
-#define PHY_BB_MULTICHAIN_CONTROL_CF_SHORT_SAT_LSB 10
-#define PHY_BB_MULTICHAIN_CONTROL_CF_SHORT_SAT_MASK 0x001ffc00
-#define PHY_BB_MULTICHAIN_CONTROL_CF_SHORT_SAT_GET(x) (((x) & 0x001ffc00) >> 10)
-#define PHY_BB_MULTICHAIN_CONTROL_CF_SHORT_SAT_SET(x) (((x) << 10) & 0x001ffc00)
-#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_02_MSB 28
-#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_02_LSB 22
-#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_02_MASK 0x1fc00000
-#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_02_GET(x) (((x) & 0x1fc00000) >> 22)
-#define PHY_BB_MULTICHAIN_CONTROL_FORCED_GAIN_DIFF_02_SET(x) (((x) << 22) & 0x1fc00000)
-#define PHY_BB_MULTICHAIN_CONTROL_FORCE_SIGMA_ZERO_MSB 29
-#define PHY_BB_MULTICHAIN_CONTROL_FORCE_SIGMA_ZERO_LSB 29
-#define PHY_BB_MULTICHAIN_CONTROL_FORCE_SIGMA_ZERO_MASK 0x20000000
-#define PHY_BB_MULTICHAIN_CONTROL_FORCE_SIGMA_ZERO_GET(x) (((x) & 0x20000000) >> 29)
-#define PHY_BB_MULTICHAIN_CONTROL_FORCE_SIGMA_ZERO_SET(x) (((x) << 29) & 0x20000000)
-
-/* macros for BB_multichain_gain_ctrl */
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_ADDRESS 0x000099ac
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_OFFSET 0x000099ac
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_QUICKDROP_LOW_MSB 7
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_QUICKDROP_LOW_LSB 0
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_QUICKDROP_LOW_MASK 0x000000ff
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_QUICKDROP_LOW_GET(x) (((x) & 0x000000ff) >> 0)
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_QUICKDROP_LOW_SET(x) (((x) << 0) & 0x000000ff)
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_CHECK_STRONG_ANT_MSB 8
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_CHECK_STRONG_ANT_LSB 8
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_CHECK_STRONG_ANT_MASK 0x00000100
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_CHECK_STRONG_ANT_GET(x) (((x) & 0x00000100) >> 8)
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_CHECK_STRONG_ANT_SET(x) (((x) << 8) & 0x00000100)
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_FAST_DIV_BIAS_MSB 14
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_FAST_DIV_BIAS_LSB 9
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_FAST_DIV_BIAS_MASK 0x00007e00
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_FAST_DIV_BIAS_GET(x) (((x) & 0x00007e00) >> 9)
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_FAST_DIV_BIAS_SET(x) (((x) << 9) & 0x00007e00)
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_SNR_MSB 20
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_SNR_LSB 15
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_SNR_MASK 0x001f8000
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_SNR_GET(x) (((x) & 0x001f8000) >> 15)
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_SNR_SET(x) (((x) << 15) & 0x001f8000)
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_ENA_MSB 21
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_ENA_LSB 21
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_ENA_MASK 0x00200000
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_ENA_GET(x) (((x) & 0x00200000) >> 21)
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_ENA_SET(x) (((x) << 21) & 0x00200000)
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_MODE_MSB 22
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_MODE_LSB 22
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_MODE_MASK 0x00400000
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_MODE_GET(x) (((x) & 0x00400000) >> 22)
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_CAP_GAIN_RATIO_MODE_SET(x) (((x) << 22) & 0x00400000)
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_SW_RX_PROT_MSB 23
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_SW_RX_PROT_LSB 23
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_SW_RX_PROT_MASK 0x00800000
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_SW_RX_PROT_GET(x) (((x) & 0x00800000) >> 23)
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_SW_RX_PROT_SET(x) (((x) << 23) & 0x00800000)
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_DIV_LNADIV_MSB 24
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_DIV_LNADIV_LSB 24
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_DIV_LNADIV_MASK 0x01000000
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_DIV_LNADIV_GET(x) (((x) & 0x01000000) >> 24)
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_ENABLE_ANT_DIV_LNADIV_SET(x) (((x) << 24) & 0x01000000)
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_LNACONF_MSB 26
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_LNACONF_LSB 25
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_LNACONF_MASK 0x06000000
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_LNACONF_GET(x) (((x) & 0x06000000) >> 25)
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_LNACONF_SET(x) (((x) << 25) & 0x06000000)
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_LNACONF_MSB 28
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_LNACONF_LSB 27
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_LNACONF_MASK 0x18000000
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_LNACONF_GET(x) (((x) & 0x18000000) >> 27)
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_LNACONF_SET(x) (((x) << 27) & 0x18000000)
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_GAINTB_MSB 29
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_GAINTB_LSB 29
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_GAINTB_MASK 0x20000000
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_GAINTB_GET(x) (((x) & 0x20000000) >> 29)
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_ALT_GAINTB_SET(x) (((x) << 29) & 0x20000000)
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_GAINTB_MSB 30
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_GAINTB_LSB 30
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_GAINTB_MASK 0x40000000
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_GAINTB_GET(x) (((x) & 0x40000000) >> 30)
-#define PHY_BB_MULTICHAIN_GAIN_CTRL_ANT_DIV_MAIN_GAINTB_SET(x) (((x) << 30) & 0x40000000)
-
-/* macros for BB_adc_gain_dc_corr_b0 */
-#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADDRESS 0x000099b4
-#define PHY_BB_ADC_GAIN_DC_CORR_B0_OFFSET 0x000099b4
-#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_Q_COEFF_0_MSB 5
-#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_Q_COEFF_0_LSB 0
-#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_Q_COEFF_0_MASK 0x0000003f
-#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_Q_COEFF_0_GET(x) (((x) & 0x0000003f) >> 0)
-#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_Q_COEFF_0_SET(x) (((x) << 0) & 0x0000003f)
-#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_I_COEFF_0_MSB 11
-#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_I_COEFF_0_LSB 6
-#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_I_COEFF_0_MASK 0x00000fc0
-#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_I_COEFF_0_GET(x) (((x) & 0x00000fc0) >> 6)
-#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_I_COEFF_0_SET(x) (((x) << 6) & 0x00000fc0)
-#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_Q_COEFF_0_MSB 20
-#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_Q_COEFF_0_LSB 12
-#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_Q_COEFF_0_MASK 0x001ff000
-#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_Q_COEFF_0_GET(x) (((x) & 0x001ff000) >> 12)
-#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_Q_COEFF_0_SET(x) (((x) << 12) & 0x001ff000)
-#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_I_COEFF_0_MSB 29
-#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_I_COEFF_0_LSB 21
-#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_I_COEFF_0_MASK 0x3fe00000
-#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_I_COEFF_0_GET(x) (((x) & 0x3fe00000) >> 21)
-#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_I_COEFF_0_SET(x) (((x) << 21) & 0x3fe00000)
-#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_ENABLE_MSB 30
-#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_ENABLE_LSB 30
-#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_ENABLE_MASK 0x40000000
-#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_ENABLE_GET(x) (((x) & 0x40000000) >> 30)
-#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_GAIN_CORR_ENABLE_SET(x) (((x) << 30) & 0x40000000)
-#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_ENABLE_MSB 31
-#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_ENABLE_LSB 31
-#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_ENABLE_MASK 0x80000000
-#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_ENABLE_GET(x) (((x) & 0x80000000) >> 31)
-#define PHY_BB_ADC_GAIN_DC_CORR_B0_ADC_DC_CORR_ENABLE_SET(x) (((x) << 31) & 0x80000000)
-
-/* macros for BB_ext_chan_pwr_thr_1 */
-#define PHY_BB_EXT_CHAN_PWR_THR_1_ADDRESS 0x000099b8
-#define PHY_BB_EXT_CHAN_PWR_THR_1_OFFSET 0x000099b8
-#define PHY_BB_EXT_CHAN_PWR_THR_1_THRESH62_EXT_MSB 7
-#define PHY_BB_EXT_CHAN_PWR_THR_1_THRESH62_EXT_LSB 0
-#define PHY_BB_EXT_CHAN_PWR_THR_1_THRESH62_EXT_MASK 0x000000ff
-#define PHY_BB_EXT_CHAN_PWR_THR_1_THRESH62_EXT_GET(x) (((x) & 0x000000ff) >> 0)
-#define PHY_BB_EXT_CHAN_PWR_THR_1_THRESH62_EXT_SET(x) (((x) << 0) & 0x000000ff)
-#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_MINGAINIDX_MSB 15
-#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_MINGAINIDX_LSB 8
-#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_MINGAINIDX_MASK 0x0000ff00
-#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_MINGAINIDX_GET(x) (((x) & 0x0000ff00) >> 8)
-#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_MINGAINIDX_SET(x) (((x) << 8) & 0x0000ff00)
-#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTAGAINIDX_MSB 20
-#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTAGAINIDX_LSB 16
-#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTAGAINIDX_MASK 0x001f0000
-#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTAGAINIDX_GET(x) (((x) & 0x001f0000) >> 16)
-#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTAGAINIDX_SET(x) (((x) << 16) & 0x001f0000)
-#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTANF_MSB 26
-#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTANF_LSB 21
-#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTANF_MASK 0x07e00000
-#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTANF_GET(x) (((x) & 0x07e00000) >> 21)
-#define PHY_BB_EXT_CHAN_PWR_THR_1_ANT_DIV_ALT_ANT_DELTANF_SET(x) (((x) << 21) & 0x07e00000)
-
-/* macros for BB_ext_chan_pwr_thr_2_b0 */
-#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_ADDRESS 0x000099bc
-#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_OFFSET 0x000099bc
-#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CF_MAXCCAPWR_EXT_0_MSB 8
-#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CF_MAXCCAPWR_EXT_0_LSB 0
-#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CF_MAXCCAPWR_EXT_0_MASK 0x000001ff
-#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CF_MAXCCAPWR_EXT_0_GET(x) (((x) & 0x000001ff) >> 0)
-#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CF_MAXCCAPWR_EXT_0_SET(x) (((x) << 0) & 0x000001ff)
-#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CYCPWR_THR1_EXT_MSB 15
-#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CYCPWR_THR1_EXT_LSB 9
-#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CYCPWR_THR1_EXT_MASK 0x0000fe00
-#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CYCPWR_THR1_EXT_GET(x) (((x) & 0x0000fe00) >> 9)
-#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_CYCPWR_THR1_EXT_SET(x) (((x) << 9) & 0x0000fe00)
-#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_MINCCAPWR_EXT_0_MSB 24
-#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_MINCCAPWR_EXT_0_LSB 16
-#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_MINCCAPWR_EXT_0_MASK 0x01ff0000
-#define PHY_BB_EXT_CHAN_PWR_THR_2_B0_MINCCAPWR_EXT_0_GET(x) (((x) & 0x01ff0000) >> 16)
-
-/* macros for BB_ext_chan_scorr_thr */
-#define PHY_BB_EXT_CHAN_SCORR_THR_ADDRESS 0x000099c0
-#define PHY_BB_EXT_CHAN_SCORR_THR_OFFSET 0x000099c0
-#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_EXT_MSB 6
-#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_EXT_LSB 0
-#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_EXT_MASK 0x0000007f
-#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_EXT_GET(x) (((x) & 0x0000007f) >> 0)
-#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_EXT_SET(x) (((x) << 0) & 0x0000007f)
-#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_EXT_MSB 13
-#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_EXT_LSB 7
-#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_EXT_MASK 0x00003f80
-#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_EXT_GET(x) (((x) & 0x00003f80) >> 7)
-#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_EXT_SET(x) (((x) << 7) & 0x00003f80)
-#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_LOW_EXT_MSB 20
-#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_LOW_EXT_LSB 14
-#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_LOW_EXT_MASK 0x001fc000
-#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_LOW_EXT_GET(x) (((x) & 0x001fc000) >> 14)
-#define PHY_BB_EXT_CHAN_SCORR_THR_M1_THRES_LOW_EXT_SET(x) (((x) << 14) & 0x001fc000)
-#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_LOW_EXT_MSB 27
-#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_LOW_EXT_LSB 21
-#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_LOW_EXT_MASK 0x0fe00000
-#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_LOW_EXT_GET(x) (((x) & 0x0fe00000) >> 21)
-#define PHY_BB_EXT_CHAN_SCORR_THR_M2_THRES_LOW_EXT_SET(x) (((x) << 21) & 0x0fe00000)
-#define PHY_BB_EXT_CHAN_SCORR_THR_SPUR_SUBCHANNEL_SD_MSB 28
-#define PHY_BB_EXT_CHAN_SCORR_THR_SPUR_SUBCHANNEL_SD_LSB 28
-#define PHY_BB_EXT_CHAN_SCORR_THR_SPUR_SUBCHANNEL_SD_MASK 0x10000000
-#define PHY_BB_EXT_CHAN_SCORR_THR_SPUR_SUBCHANNEL_SD_GET(x) (((x) & 0x10000000) >> 28)
-#define PHY_BB_EXT_CHAN_SCORR_THR_SPUR_SUBCHANNEL_SD_SET(x) (((x) << 28) & 0x10000000)
-
-/* macros for BB_ext_chan_detect_win */
-#define PHY_BB_EXT_CHAN_DETECT_WIN_ADDRESS 0x000099c4
-#define PHY_BB_EXT_CHAN_DETECT_WIN_OFFSET 0x000099c4
-#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_MSB 3
-#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_LSB 0
-#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_MASK 0x0000000f
-#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_GET(x) (((x) & 0x0000000f) >> 0)
-#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_SET(x) (((x) << 0) & 0x0000000f)
-#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_LOW_MSB 7
-#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_LOW_LSB 4
-#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_LOW_MASK 0x000000f0
-#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_LOW_GET(x) (((x) & 0x000000f0) >> 4)
-#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_LOW_SET(x) (((x) << 4) & 0x000000f0)
-#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_CCK_MSB 12
-#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_CCK_LSB 8
-#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_CCK_MASK 0x00001f00
-#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_CCK_GET(x) (((x) & 0x00001f00) >> 8)
-#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_WEAK_CCK_SET(x) (((x) << 8) & 0x00001f00)
-#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_20H_COUNT_MSB 15
-#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_20H_COUNT_LSB 13
-#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_20H_COUNT_MASK 0x0000e000
-#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_20H_COUNT_GET(x) (((x) & 0x0000e000) >> 13)
-#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_20H_COUNT_SET(x) (((x) << 13) & 0x0000e000)
-#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_EXT_BLK_COUNT_MSB 18
-#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_EXT_BLK_COUNT_LSB 16
-#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_EXT_BLK_COUNT_MASK 0x00070000
-#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_EXT_BLK_COUNT_GET(x) (((x) & 0x00070000) >> 16)
-#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_EXT_BLK_COUNT_SET(x) (((x) << 16) & 0x00070000)
-#define PHY_BB_EXT_CHAN_DETECT_WIN_WEAK_SIG_THR_CCK_EXT_MSB 24
-#define PHY_BB_EXT_CHAN_DETECT_WIN_WEAK_SIG_THR_CCK_EXT_LSB 19
-#define PHY_BB_EXT_CHAN_DETECT_WIN_WEAK_SIG_THR_CCK_EXT_MASK 0x01f80000
-#define PHY_BB_EXT_CHAN_DETECT_WIN_WEAK_SIG_THR_CCK_EXT_GET(x) (((x) & 0x01f80000) >> 19)
-#define PHY_BB_EXT_CHAN_DETECT_WIN_WEAK_SIG_THR_CCK_EXT_SET(x) (((x) << 19) & 0x01f80000)
-#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_THRESH_MSB 28
-#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_THRESH_LSB 25
-#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_THRESH_MASK 0x1e000000
-#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_THRESH_GET(x) (((x) & 0x1e000000) >> 25)
-#define PHY_BB_EXT_CHAN_DETECT_WIN_DET_DIFF_WIN_THRESH_SET(x) (((x) << 25) & 0x1e000000)
-
-/* macros for BB_pwr_thr_20_40_det */
-#define PHY_BB_PWR_THR_20_40_DET_ADDRESS 0x000099c8
-#define PHY_BB_PWR_THR_20_40_DET_OFFSET 0x000099c8
-#define PHY_BB_PWR_THR_20_40_DET_PWRDIFF40_THRSTR_MSB 4
-#define PHY_BB_PWR_THR_20_40_DET_PWRDIFF40_THRSTR_LSB 0
-#define PHY_BB_PWR_THR_20_40_DET_PWRDIFF40_THRSTR_MASK 0x0000001f
-#define PHY_BB_PWR_THR_20_40_DET_PWRDIFF40_THRSTR_GET(x) (((x) & 0x0000001f) >> 0)
-#define PHY_BB_PWR_THR_20_40_DET_PWRDIFF40_THRSTR_SET(x) (((x) << 0) & 0x0000001f)
-#define PHY_BB_PWR_THR_20_40_DET_BLOCKER40_MAX_MSB 10
-#define PHY_BB_PWR_THR_20_40_DET_BLOCKER40_MAX_LSB 5
-#define PHY_BB_PWR_THR_20_40_DET_BLOCKER40_MAX_MASK 0x000007e0
-#define PHY_BB_PWR_THR_20_40_DET_BLOCKER40_MAX_GET(x) (((x) & 0x000007e0) >> 5)
-#define PHY_BB_PWR_THR_20_40_DET_BLOCKER40_MAX_SET(x) (((x) << 5) & 0x000007e0)
-#define PHY_BB_PWR_THR_20_40_DET_DET40_PWRSTEP_MAX_MSB 15
-#define PHY_BB_PWR_THR_20_40_DET_DET40_PWRSTEP_MAX_LSB 11
-#define PHY_BB_PWR_THR_20_40_DET_DET40_PWRSTEP_MAX_MASK 0x0000f800
-#define PHY_BB_PWR_THR_20_40_DET_DET40_PWRSTEP_MAX_GET(x) (((x) & 0x0000f800) >> 11)
-#define PHY_BB_PWR_THR_20_40_DET_DET40_PWRSTEP_MAX_SET(x) (((x) << 11) & 0x0000f800)
-#define PHY_BB_PWR_THR_20_40_DET_DET40_THR_SNR_MSB 23
-#define PHY_BB_PWR_THR_20_40_DET_DET40_THR_SNR_LSB 16
-#define PHY_BB_PWR_THR_20_40_DET_DET40_THR_SNR_MASK 0x00ff0000
-#define PHY_BB_PWR_THR_20_40_DET_DET40_THR_SNR_GET(x) (((x) & 0x00ff0000) >> 16)
-#define PHY_BB_PWR_THR_20_40_DET_DET40_THR_SNR_SET(x) (((x) << 16) & 0x00ff0000)
-#define PHY_BB_PWR_THR_20_40_DET_DET40_PRI_BIAS_MSB 28
-#define PHY_BB_PWR_THR_20_40_DET_DET40_PRI_BIAS_LSB 24
-#define PHY_BB_PWR_THR_20_40_DET_DET40_PRI_BIAS_MASK 0x1f000000
-#define PHY_BB_PWR_THR_20_40_DET_DET40_PRI_BIAS_GET(x) (((x) & 0x1f000000) >> 24)
-#define PHY_BB_PWR_THR_20_40_DET_DET40_PRI_BIAS_SET(x) (((x) << 24) & 0x1f000000)
-#define PHY_BB_PWR_THR_20_40_DET_PWRSTEP40_ENA_MSB 29
-#define PHY_BB_PWR_THR_20_40_DET_PWRSTEP40_ENA_LSB 29
-#define PHY_BB_PWR_THR_20_40_DET_PWRSTEP40_ENA_MASK 0x20000000
-#define PHY_BB_PWR_THR_20_40_DET_PWRSTEP40_ENA_GET(x) (((x) & 0x20000000) >> 29)
-#define PHY_BB_PWR_THR_20_40_DET_PWRSTEP40_ENA_SET(x) (((x) << 29) & 0x20000000)
-#define PHY_BB_PWR_THR_20_40_DET_LOWSNR40_ENA_MSB 30
-#define PHY_BB_PWR_THR_20_40_DET_LOWSNR40_ENA_LSB 30
-#define PHY_BB_PWR_THR_20_40_DET_LOWSNR40_ENA_MASK 0x40000000
-#define PHY_BB_PWR_THR_20_40_DET_LOWSNR40_ENA_GET(x) (((x) & 0x40000000) >> 30)
-#define PHY_BB_PWR_THR_20_40_DET_LOWSNR40_ENA_SET(x) (((x) << 30) & 0x40000000)
-
-/* macros for BB_short_gi_delta_slope */
-#define PHY_BB_SHORT_GI_DELTA_SLOPE_ADDRESS 0x000099d0
-#define PHY_BB_SHORT_GI_DELTA_SLOPE_OFFSET 0x000099d0
-#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_EXP_SHORT_GI_MSB 3
-#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_EXP_SHORT_GI_LSB 0
-#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_EXP_SHORT_GI_MASK 0x0000000f
-#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_EXP_SHORT_GI_GET(x) (((x) & 0x0000000f) >> 0)
-#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_EXP_SHORT_GI_SET(x) (((x) << 0) & 0x0000000f)
-#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_MAN_SHORT_GI_MSB 18
-#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_MAN_SHORT_GI_LSB 4
-#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_MAN_SHORT_GI_MASK 0x0007fff0
-#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_MAN_SHORT_GI_GET(x) (((x) & 0x0007fff0) >> 4)
-#define PHY_BB_SHORT_GI_DELTA_SLOPE_DELTA_SLOPE_COEF_MAN_SHORT_GI_SET(x) (((x) << 4) & 0x0007fff0)
-
-/* macros for BB_chaninfo_ctrl */
-#define PHY_BB_CHANINFO_CTRL_ADDRESS 0x000099dc
-#define PHY_BB_CHANINFO_CTRL_OFFSET 0x000099dc
-#define PHY_BB_CHANINFO_CTRL_CAPTURE_CHAN_INFO_MSB 0
-#define PHY_BB_CHANINFO_CTRL_CAPTURE_CHAN_INFO_LSB 0
-#define PHY_BB_CHANINFO_CTRL_CAPTURE_CHAN_INFO_MASK 0x00000001
-#define PHY_BB_CHANINFO_CTRL_CAPTURE_CHAN_INFO_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_BB_CHANINFO_CTRL_CAPTURE_CHAN_INFO_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_BB_CHANINFO_CTRL_DISABLE_CHANINFOMEM_MSB 1
-#define PHY_BB_CHANINFO_CTRL_DISABLE_CHANINFOMEM_LSB 1
-#define PHY_BB_CHANINFO_CTRL_DISABLE_CHANINFOMEM_MASK 0x00000002
-#define PHY_BB_CHANINFO_CTRL_DISABLE_CHANINFOMEM_GET(x) (((x) & 0x00000002) >> 1)
-#define PHY_BB_CHANINFO_CTRL_DISABLE_CHANINFOMEM_SET(x) (((x) << 1) & 0x00000002)
-
-/* macros for BB_heavy_clip_ctrl */
-#define PHY_BB_HEAVY_CLIP_CTRL_ADDRESS 0x000099e0
-#define PHY_BB_HEAVY_CLIP_CTRL_OFFSET 0x000099e0
-#define PHY_BB_HEAVY_CLIP_CTRL_CF_HEAVY_CLIP_ENABLE_MSB 8
-#define PHY_BB_HEAVY_CLIP_CTRL_CF_HEAVY_CLIP_ENABLE_LSB 0
-#define PHY_BB_HEAVY_CLIP_CTRL_CF_HEAVY_CLIP_ENABLE_MASK 0x000001ff
-#define PHY_BB_HEAVY_CLIP_CTRL_CF_HEAVY_CLIP_ENABLE_GET(x) (((x) & 0x000001ff) >> 0)
-#define PHY_BB_HEAVY_CLIP_CTRL_CF_HEAVY_CLIP_ENABLE_SET(x) (((x) << 0) & 0x000001ff)
-#define PHY_BB_HEAVY_CLIP_CTRL_PRE_EMP_HT40_ENABLE_MSB 9
-#define PHY_BB_HEAVY_CLIP_CTRL_PRE_EMP_HT40_ENABLE_LSB 9
-#define PHY_BB_HEAVY_CLIP_CTRL_PRE_EMP_HT40_ENABLE_MASK 0x00000200
-#define PHY_BB_HEAVY_CLIP_CTRL_PRE_EMP_HT40_ENABLE_GET(x) (((x) & 0x00000200) >> 9)
-#define PHY_BB_HEAVY_CLIP_CTRL_PRE_EMP_HT40_ENABLE_SET(x) (((x) << 9) & 0x00000200)
-
-/* macros for BB_heavy_clip_20 */
-#define PHY_BB_HEAVY_CLIP_20_ADDRESS 0x000099e4
-#define PHY_BB_HEAVY_CLIP_20_OFFSET 0x000099e4
-#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_0_MSB 7
-#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_0_LSB 0
-#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_0_MASK 0x000000ff
-#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_0_GET(x) (((x) & 0x000000ff) >> 0)
-#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_0_SET(x) (((x) << 0) & 0x000000ff)
-#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_1_MSB 15
-#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_1_LSB 8
-#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_1_MASK 0x0000ff00
-#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_1_GET(x) (((x) & 0x0000ff00) >> 8)
-#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_1_SET(x) (((x) << 8) & 0x0000ff00)
-#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_2_MSB 23
-#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_2_LSB 16
-#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_2_MASK 0x00ff0000
-#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_2_GET(x) (((x) & 0x00ff0000) >> 16)
-#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_2_SET(x) (((x) << 16) & 0x00ff0000)
-#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_3_MSB 31
-#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_3_LSB 24
-#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_3_MASK 0xff000000
-#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_3_GET(x) (((x) & 0xff000000) >> 24)
-#define PHY_BB_HEAVY_CLIP_20_HEAVY_CLIP_FACTOR_3_SET(x) (((x) << 24) & 0xff000000)
-
-/* macros for BB_heavy_clip_40 */
-#define PHY_BB_HEAVY_CLIP_40_ADDRESS 0x000099e8
-#define PHY_BB_HEAVY_CLIP_40_OFFSET 0x000099e8
-#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_4_MSB 7
-#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_4_LSB 0
-#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_4_MASK 0x000000ff
-#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_4_GET(x) (((x) & 0x000000ff) >> 0)
-#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_4_SET(x) (((x) << 0) & 0x000000ff)
-#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_5_MSB 15
-#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_5_LSB 8
-#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_5_MASK 0x0000ff00
-#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_5_GET(x) (((x) & 0x0000ff00) >> 8)
-#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_5_SET(x) (((x) << 8) & 0x0000ff00)
-#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_6_MSB 23
-#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_6_LSB 16
-#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_6_MASK 0x00ff0000
-#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_6_GET(x) (((x) & 0x00ff0000) >> 16)
-#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_6_SET(x) (((x) << 16) & 0x00ff0000)
-#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_7_MSB 31
-#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_7_LSB 24
-#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_7_MASK 0xff000000
-#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_7_GET(x) (((x) & 0xff000000) >> 24)
-#define PHY_BB_HEAVY_CLIP_40_HEAVY_CLIP_FACTOR_7_SET(x) (((x) << 24) & 0xff000000)
-
-/* macros for BB_rifs_srch */
-#define PHY_BB_RIFS_SRCH_ADDRESS 0x000099ec
-#define PHY_BB_RIFS_SRCH_OFFSET 0x000099ec
-#define PHY_BB_RIFS_SRCH_HEAVY_CLIP_FACTOR_XR_MSB 7
-#define PHY_BB_RIFS_SRCH_HEAVY_CLIP_FACTOR_XR_LSB 0
-#define PHY_BB_RIFS_SRCH_HEAVY_CLIP_FACTOR_XR_MASK 0x000000ff
-#define PHY_BB_RIFS_SRCH_HEAVY_CLIP_FACTOR_XR_GET(x) (((x) & 0x000000ff) >> 0)
-#define PHY_BB_RIFS_SRCH_HEAVY_CLIP_FACTOR_XR_SET(x) (((x) << 0) & 0x000000ff)
-#define PHY_BB_RIFS_SRCH_INIT_GAIN_DB_OFFSET_MSB 15
-#define PHY_BB_RIFS_SRCH_INIT_GAIN_DB_OFFSET_LSB 8
-#define PHY_BB_RIFS_SRCH_INIT_GAIN_DB_OFFSET_MASK 0x0000ff00
-#define PHY_BB_RIFS_SRCH_INIT_GAIN_DB_OFFSET_GET(x) (((x) & 0x0000ff00) >> 8)
-#define PHY_BB_RIFS_SRCH_INIT_GAIN_DB_OFFSET_SET(x) (((x) << 8) & 0x0000ff00)
-#define PHY_BB_RIFS_SRCH_RIFS_INIT_DELAY_MSB 25
-#define PHY_BB_RIFS_SRCH_RIFS_INIT_DELAY_LSB 16
-#define PHY_BB_RIFS_SRCH_RIFS_INIT_DELAY_MASK 0x03ff0000
-#define PHY_BB_RIFS_SRCH_RIFS_INIT_DELAY_GET(x) (((x) & 0x03ff0000) >> 16)
-#define PHY_BB_RIFS_SRCH_RIFS_INIT_DELAY_SET(x) (((x) << 16) & 0x03ff0000)
-#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_PWRLOW_GC_MSB 26
-#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_PWRLOW_GC_LSB 26
-#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_PWRLOW_GC_MASK 0x04000000
-#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_PWRLOW_GC_GET(x) (((x) & 0x04000000) >> 26)
-#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_PWRLOW_GC_SET(x) (((x) << 26) & 0x04000000)
-#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_CCK_DET_MSB 27
-#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_CCK_DET_LSB 27
-#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_CCK_DET_MASK 0x08000000
-#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_CCK_DET_GET(x) (((x) & 0x08000000) >> 27)
-#define PHY_BB_RIFS_SRCH_RIFS_DISABLE_CCK_DET_SET(x) (((x) << 27) & 0x08000000)
-
-/* macros for BB_iq_adc_cal_mode */
-#define PHY_BB_IQ_ADC_CAL_MODE_ADDRESS 0x000099f0
-#define PHY_BB_IQ_ADC_CAL_MODE_OFFSET 0x000099f0
-#define PHY_BB_IQ_ADC_CAL_MODE_GAIN_DC_IQ_CAL_MODE_MSB 1
-#define PHY_BB_IQ_ADC_CAL_MODE_GAIN_DC_IQ_CAL_MODE_LSB 0
-#define PHY_BB_IQ_ADC_CAL_MODE_GAIN_DC_IQ_CAL_MODE_MASK 0x00000003
-#define PHY_BB_IQ_ADC_CAL_MODE_GAIN_DC_IQ_CAL_MODE_GET(x) (((x) & 0x00000003) >> 0)
-#define PHY_BB_IQ_ADC_CAL_MODE_GAIN_DC_IQ_CAL_MODE_SET(x) (((x) << 0) & 0x00000003)
-#define PHY_BB_IQ_ADC_CAL_MODE_TEST_CALADCOFF_MSB 2
-#define PHY_BB_IQ_ADC_CAL_MODE_TEST_CALADCOFF_LSB 2
-#define PHY_BB_IQ_ADC_CAL_MODE_TEST_CALADCOFF_MASK 0x00000004
-#define PHY_BB_IQ_ADC_CAL_MODE_TEST_CALADCOFF_GET(x) (((x) & 0x00000004) >> 2)
-#define PHY_BB_IQ_ADC_CAL_MODE_TEST_CALADCOFF_SET(x) (((x) << 2) & 0x00000004)
-
-/* macros for BB_per_chain_csd */
-#define PHY_BB_PER_CHAIN_CSD_ADDRESS 0x000099fc
-#define PHY_BB_PER_CHAIN_CSD_OFFSET 0x000099fc
-#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_2CHAINS_MSB 4
-#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_2CHAINS_LSB 0
-#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_2CHAINS_MASK 0x0000001f
-#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_2CHAINS_GET(x) (((x) & 0x0000001f) >> 0)
-#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_2CHAINS_SET(x) (((x) << 0) & 0x0000001f)
-#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_3CHAINS_MSB 9
-#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_3CHAINS_LSB 5
-#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_3CHAINS_MASK 0x000003e0
-#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_3CHAINS_GET(x) (((x) & 0x000003e0) >> 5)
-#define PHY_BB_PER_CHAIN_CSD_CSD_CHN1_3CHAINS_SET(x) (((x) << 5) & 0x000003e0)
-#define PHY_BB_PER_CHAIN_CSD_CSD_CHN2_3CHAINS_MSB 14
-#define PHY_BB_PER_CHAIN_CSD_CSD_CHN2_3CHAINS_LSB 10
-#define PHY_BB_PER_CHAIN_CSD_CSD_CHN2_3CHAINS_MASK 0x00007c00
-#define PHY_BB_PER_CHAIN_CSD_CSD_CHN2_3CHAINS_GET(x) (((x) & 0x00007c00) >> 10)
-#define PHY_BB_PER_CHAIN_CSD_CSD_CHN2_3CHAINS_SET(x) (((x) << 10) & 0x00007c00)
-
-/* macros for BB_rx_ocgain */
-#define PHY_BB_RX_OCGAIN_ADDRESS 0x00009a00
-#define PHY_BB_RX_OCGAIN_OFFSET 0x00009a00
-#define PHY_BB_RX_OCGAIN_GAIN_ENTRY_MSB 31
-#define PHY_BB_RX_OCGAIN_GAIN_ENTRY_LSB 0
-#define PHY_BB_RX_OCGAIN_GAIN_ENTRY_MASK 0xffffffff
-#define PHY_BB_RX_OCGAIN_GAIN_ENTRY_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_crc */
-#define PHY_BB_TX_CRC_ADDRESS 0x00009c00
-#define PHY_BB_TX_CRC_OFFSET 0x00009c00
-#define PHY_BB_TX_CRC_TX_CRC_MSB 15
-#define PHY_BB_TX_CRC_TX_CRC_LSB 0
-#define PHY_BB_TX_CRC_TX_CRC_MASK 0x0000ffff
-#define PHY_BB_TX_CRC_TX_CRC_GET(x) (((x) & 0x0000ffff) >> 0)
-
-/* macros for BB_iq_adc_meas_0_b0 */
-#define PHY_BB_IQ_ADC_MEAS_0_B0_ADDRESS 0x00009c10
-#define PHY_BB_IQ_ADC_MEAS_0_B0_OFFSET 0x00009c10
-#define PHY_BB_IQ_ADC_MEAS_0_B0_GAIN_DC_IQ_CAL_MEAS_0_0_MSB 31
-#define PHY_BB_IQ_ADC_MEAS_0_B0_GAIN_DC_IQ_CAL_MEAS_0_0_LSB 0
-#define PHY_BB_IQ_ADC_MEAS_0_B0_GAIN_DC_IQ_CAL_MEAS_0_0_MASK 0xffffffff
-#define PHY_BB_IQ_ADC_MEAS_0_B0_GAIN_DC_IQ_CAL_MEAS_0_0_GET(x) (((x) & 0xffffffff) >> 0)
-
-/* macros for BB_iq_adc_meas_1_b0 */
-#define PHY_BB_IQ_ADC_MEAS_1_B0_ADDRESS 0x00009c14
-#define PHY_BB_IQ_ADC_MEAS_1_B0_OFFSET 0x00009c14
-#define PHY_BB_IQ_ADC_MEAS_1_B0_GAIN_DC_IQ_CAL_MEAS_1_0_MSB 31
-#define PHY_BB_IQ_ADC_MEAS_1_B0_GAIN_DC_IQ_CAL_MEAS_1_0_LSB 0
-#define PHY_BB_IQ_ADC_MEAS_1_B0_GAIN_DC_IQ_CAL_MEAS_1_0_MASK 0xffffffff
-#define PHY_BB_IQ_ADC_MEAS_1_B0_GAIN_DC_IQ_CAL_MEAS_1_0_GET(x) (((x) & 0xffffffff) >> 0)
-
-/* macros for BB_iq_adc_meas_2_b0 */
-#define PHY_BB_IQ_ADC_MEAS_2_B0_ADDRESS 0x00009c18
-#define PHY_BB_IQ_ADC_MEAS_2_B0_OFFSET 0x00009c18
-#define PHY_BB_IQ_ADC_MEAS_2_B0_GAIN_DC_IQ_CAL_MEAS_2_0_MSB 31
-#define PHY_BB_IQ_ADC_MEAS_2_B0_GAIN_DC_IQ_CAL_MEAS_2_0_LSB 0
-#define PHY_BB_IQ_ADC_MEAS_2_B0_GAIN_DC_IQ_CAL_MEAS_2_0_MASK 0xffffffff
-#define PHY_BB_IQ_ADC_MEAS_2_B0_GAIN_DC_IQ_CAL_MEAS_2_0_GET(x) (((x) & 0xffffffff) >> 0)
-
-/* macros for BB_iq_adc_meas_3_b0 */
-#define PHY_BB_IQ_ADC_MEAS_3_B0_ADDRESS 0x00009c1c
-#define PHY_BB_IQ_ADC_MEAS_3_B0_OFFSET 0x00009c1c
-#define PHY_BB_IQ_ADC_MEAS_3_B0_GAIN_DC_IQ_CAL_MEAS_3_0_MSB 31
-#define PHY_BB_IQ_ADC_MEAS_3_B0_GAIN_DC_IQ_CAL_MEAS_3_0_LSB 0
-#define PHY_BB_IQ_ADC_MEAS_3_B0_GAIN_DC_IQ_CAL_MEAS_3_0_MASK 0xffffffff
-#define PHY_BB_IQ_ADC_MEAS_3_B0_GAIN_DC_IQ_CAL_MEAS_3_0_GET(x) (((x) & 0xffffffff) >> 0)
-
-/* macros for BB_rfbus_grant */
-#define PHY_BB_RFBUS_GRANT_ADDRESS 0x00009c20
-#define PHY_BB_RFBUS_GRANT_OFFSET 0x00009c20
-#define PHY_BB_RFBUS_GRANT_RFBUS_GRANT_MSB 0
-#define PHY_BB_RFBUS_GRANT_RFBUS_GRANT_LSB 0
-#define PHY_BB_RFBUS_GRANT_RFBUS_GRANT_MASK 0x00000001
-#define PHY_BB_RFBUS_GRANT_RFBUS_GRANT_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_BB_RFBUS_GRANT_BT_ANT_MSB 1
-#define PHY_BB_RFBUS_GRANT_BT_ANT_LSB 1
-#define PHY_BB_RFBUS_GRANT_BT_ANT_MASK 0x00000002
-#define PHY_BB_RFBUS_GRANT_BT_ANT_GET(x) (((x) & 0x00000002) >> 1)
-
-/* macros for BB_tstadc */
-#define PHY_BB_TSTADC_ADDRESS 0x00009c24
-#define PHY_BB_TSTADC_OFFSET 0x00009c24
-#define PHY_BB_TSTADC_TSTADC_OUT_Q_MSB 9
-#define PHY_BB_TSTADC_TSTADC_OUT_Q_LSB 0
-#define PHY_BB_TSTADC_TSTADC_OUT_Q_MASK 0x000003ff
-#define PHY_BB_TSTADC_TSTADC_OUT_Q_GET(x) (((x) & 0x000003ff) >> 0)
-#define PHY_BB_TSTADC_TSTADC_OUT_I_MSB 19
-#define PHY_BB_TSTADC_TSTADC_OUT_I_LSB 10
-#define PHY_BB_TSTADC_TSTADC_OUT_I_MASK 0x000ffc00
-#define PHY_BB_TSTADC_TSTADC_OUT_I_GET(x) (((x) & 0x000ffc00) >> 10)
-
-/* macros for BB_tstdac */
-#define PHY_BB_TSTDAC_ADDRESS 0x00009c28
-#define PHY_BB_TSTDAC_OFFSET 0x00009c28
-#define PHY_BB_TSTDAC_TSTDAC_OUT_Q_MSB 9
-#define PHY_BB_TSTDAC_TSTDAC_OUT_Q_LSB 0
-#define PHY_BB_TSTDAC_TSTDAC_OUT_Q_MASK 0x000003ff
-#define PHY_BB_TSTDAC_TSTDAC_OUT_Q_GET(x) (((x) & 0x000003ff) >> 0)
-#define PHY_BB_TSTDAC_TSTDAC_OUT_I_MSB 19
-#define PHY_BB_TSTDAC_TSTDAC_OUT_I_LSB 10
-#define PHY_BB_TSTDAC_TSTDAC_OUT_I_MASK 0x000ffc00
-#define PHY_BB_TSTDAC_TSTDAC_OUT_I_GET(x) (((x) & 0x000ffc00) >> 10)
-
-/* macros for BB_illegal_tx_rate */
-#define PHY_BB_ILLEGAL_TX_RATE_ADDRESS 0x00009c30
-#define PHY_BB_ILLEGAL_TX_RATE_OFFSET 0x00009c30
-#define PHY_BB_ILLEGAL_TX_RATE_ILLEGAL_TX_RATE_MSB 0
-#define PHY_BB_ILLEGAL_TX_RATE_ILLEGAL_TX_RATE_LSB 0
-#define PHY_BB_ILLEGAL_TX_RATE_ILLEGAL_TX_RATE_MASK 0x00000001
-#define PHY_BB_ILLEGAL_TX_RATE_ILLEGAL_TX_RATE_GET(x) (((x) & 0x00000001) >> 0)
-
-/* macros for BB_spur_report_b0 */
-#define PHY_BB_SPUR_REPORT_B0_ADDRESS 0x00009c34
-#define PHY_BB_SPUR_REPORT_B0_OFFSET 0x00009c34
-#define PHY_BB_SPUR_REPORT_B0_SPUR_EST_I_0_MSB 7
-#define PHY_BB_SPUR_REPORT_B0_SPUR_EST_I_0_LSB 0
-#define PHY_BB_SPUR_REPORT_B0_SPUR_EST_I_0_MASK 0x000000ff
-#define PHY_BB_SPUR_REPORT_B0_SPUR_EST_I_0_GET(x) (((x) & 0x000000ff) >> 0)
-#define PHY_BB_SPUR_REPORT_B0_SPUR_EST_Q_0_MSB 15
-#define PHY_BB_SPUR_REPORT_B0_SPUR_EST_Q_0_LSB 8
-#define PHY_BB_SPUR_REPORT_B0_SPUR_EST_Q_0_MASK 0x0000ff00
-#define PHY_BB_SPUR_REPORT_B0_SPUR_EST_Q_0_GET(x) (((x) & 0x0000ff00) >> 8)
-#define PHY_BB_SPUR_REPORT_B0_POWER_WITH_SPUR_REMOVED_0_MSB 31
-#define PHY_BB_SPUR_REPORT_B0_POWER_WITH_SPUR_REMOVED_0_LSB 16
-#define PHY_BB_SPUR_REPORT_B0_POWER_WITH_SPUR_REMOVED_0_MASK 0xffff0000
-#define PHY_BB_SPUR_REPORT_B0_POWER_WITH_SPUR_REMOVED_0_GET(x) (((x) & 0xffff0000) >> 16)
-
-/* macros for BB_channel_status */
-#define PHY_BB_CHANNEL_STATUS_ADDRESS 0x00009c38
-#define PHY_BB_CHANNEL_STATUS_OFFSET 0x00009c38
-#define PHY_BB_CHANNEL_STATUS_BT_ACTIVE_MSB 0
-#define PHY_BB_CHANNEL_STATUS_BT_ACTIVE_LSB 0
-#define PHY_BB_CHANNEL_STATUS_BT_ACTIVE_MASK 0x00000001
-#define PHY_BB_CHANNEL_STATUS_BT_ACTIVE_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_RAW_MSB 1
-#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_RAW_LSB 1
-#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_RAW_MASK 0x00000002
-#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_RAW_GET(x) (((x) & 0x00000002) >> 1)
-#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_MAC_MSB 2
-#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_MAC_LSB 2
-#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_MAC_MASK 0x00000004
-#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_MAC_GET(x) (((x) & 0x00000004) >> 2)
-#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_PAD_MSB 3
-#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_PAD_LSB 3
-#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_PAD_MASK 0x00000008
-#define PHY_BB_CHANNEL_STATUS_RX_CLEAR_PAD_GET(x) (((x) & 0x00000008) >> 3)
-#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_0_MSB 5
-#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_0_LSB 4
-#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_0_MASK 0x00000030
-#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_0_GET(x) (((x) & 0x00000030) >> 4)
-#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_1_MSB 7
-#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_1_LSB 6
-#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_1_MASK 0x000000c0
-#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_1_GET(x) (((x) & 0x000000c0) >> 6)
-#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_2_MSB 9
-#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_2_LSB 8
-#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_2_MASK 0x00000300
-#define PHY_BB_CHANNEL_STATUS_BB_SW_OUT_2_GET(x) (((x) & 0x00000300) >> 8)
-#define PHY_BB_CHANNEL_STATUS_BB_SW_COM_OUT_MSB 13
-#define PHY_BB_CHANNEL_STATUS_BB_SW_COM_OUT_LSB 10
-#define PHY_BB_CHANNEL_STATUS_BB_SW_COM_OUT_MASK 0x00003c00
-#define PHY_BB_CHANNEL_STATUS_BB_SW_COM_OUT_GET(x) (((x) & 0x00003c00) >> 10)
-#define PHY_BB_CHANNEL_STATUS_ANT_DIV_CFG_USED_MSB 16
-#define PHY_BB_CHANNEL_STATUS_ANT_DIV_CFG_USED_LSB 14
-#define PHY_BB_CHANNEL_STATUS_ANT_DIV_CFG_USED_MASK 0x0001c000
-#define PHY_BB_CHANNEL_STATUS_ANT_DIV_CFG_USED_GET(x) (((x) & 0x0001c000) >> 14)
-
-/* macros for BB_rssi_b0 */
-#define PHY_BB_RSSI_B0_ADDRESS 0x00009c3c
-#define PHY_BB_RSSI_B0_OFFSET 0x00009c3c
-#define PHY_BB_RSSI_B0_RSSI_0_MSB 7
-#define PHY_BB_RSSI_B0_RSSI_0_LSB 0
-#define PHY_BB_RSSI_B0_RSSI_0_MASK 0x000000ff
-#define PHY_BB_RSSI_B0_RSSI_0_GET(x) (((x) & 0x000000ff) >> 0)
-#define PHY_BB_RSSI_B0_RSSI_EXT_0_MSB 15
-#define PHY_BB_RSSI_B0_RSSI_EXT_0_LSB 8
-#define PHY_BB_RSSI_B0_RSSI_EXT_0_MASK 0x0000ff00
-#define PHY_BB_RSSI_B0_RSSI_EXT_0_GET(x) (((x) & 0x0000ff00) >> 8)
-
-/* macros for BB_spur_est_cck_report_b0 */
-#define PHY_BB_SPUR_EST_CCK_REPORT_B0_ADDRESS 0x00009c40
-#define PHY_BB_SPUR_EST_CCK_REPORT_B0_OFFSET 0x00009c40
-#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_I_0_CCK_MSB 7
-#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_I_0_CCK_LSB 0
-#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_I_0_CCK_MASK 0x000000ff
-#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_I_0_CCK_GET(x) (((x) & 0x000000ff) >> 0)
-#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_Q_0_CCK_MSB 15
-#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_Q_0_CCK_LSB 8
-#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_Q_0_CCK_MASK 0x0000ff00
-#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_SD_Q_0_CCK_GET(x) (((x) & 0x0000ff00) >> 8)
-#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_I_0_CCK_MSB 23
-#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_I_0_CCK_LSB 16
-#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_I_0_CCK_MASK 0x00ff0000
-#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_I_0_CCK_GET(x) (((x) & 0x00ff0000) >> 16)
-#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_Q_0_CCK_MSB 31
-#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_Q_0_CCK_LSB 24
-#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_Q_0_CCK_MASK 0xff000000
-#define PHY_BB_SPUR_EST_CCK_REPORT_B0_SPUR_EST_Q_0_CCK_GET(x) (((x) & 0xff000000) >> 24)
-
-/* macros for BB_chan_info_noise_pwr */
-#define PHY_BB_CHAN_INFO_NOISE_PWR_ADDRESS 0x00009cac
-#define PHY_BB_CHAN_INFO_NOISE_PWR_OFFSET 0x00009cac
-#define PHY_BB_CHAN_INFO_NOISE_PWR_NOISE_POWER_MSB 11
-#define PHY_BB_CHAN_INFO_NOISE_PWR_NOISE_POWER_LSB 0
-#define PHY_BB_CHAN_INFO_NOISE_PWR_NOISE_POWER_MASK 0x00000fff
-#define PHY_BB_CHAN_INFO_NOISE_PWR_NOISE_POWER_GET(x) (((x) & 0x00000fff) >> 0)
-
-/* macros for BB_chan_info_gain_diff */
-#define PHY_BB_CHAN_INFO_GAIN_DIFF_ADDRESS 0x00009cb0
-#define PHY_BB_CHAN_INFO_GAIN_DIFF_OFFSET 0x00009cb0
-#define PHY_BB_CHAN_INFO_GAIN_DIFF_FINE_PPM_MSB 11
-#define PHY_BB_CHAN_INFO_GAIN_DIFF_FINE_PPM_LSB 0
-#define PHY_BB_CHAN_INFO_GAIN_DIFF_FINE_PPM_MASK 0x00000fff
-#define PHY_BB_CHAN_INFO_GAIN_DIFF_FINE_PPM_GET(x) (((x) & 0x00000fff) >> 0)
-
-/* macros for BB_chan_info_fine_timing */
-#define PHY_BB_CHAN_INFO_FINE_TIMING_ADDRESS 0x00009cb4
-#define PHY_BB_CHAN_INFO_FINE_TIMING_OFFSET 0x00009cb4
-#define PHY_BB_CHAN_INFO_FINE_TIMING_COARSE_PPM_MSB 11
-#define PHY_BB_CHAN_INFO_FINE_TIMING_COARSE_PPM_LSB 0
-#define PHY_BB_CHAN_INFO_FINE_TIMING_COARSE_PPM_MASK 0x00000fff
-#define PHY_BB_CHAN_INFO_FINE_TIMING_COARSE_PPM_GET(x) (((x) & 0x00000fff) >> 0)
-#define PHY_BB_CHAN_INFO_FINE_TIMING_FINE_TIMING_MSB 21
-#define PHY_BB_CHAN_INFO_FINE_TIMING_FINE_TIMING_LSB 12
-#define PHY_BB_CHAN_INFO_FINE_TIMING_FINE_TIMING_MASK 0x003ff000
-#define PHY_BB_CHAN_INFO_FINE_TIMING_FINE_TIMING_GET(x) (((x) & 0x003ff000) >> 12)
-
-/* macros for BB_chan_info_gain_b0 */
-#define PHY_BB_CHAN_INFO_GAIN_B0_ADDRESS 0x00009cb8
-#define PHY_BB_CHAN_INFO_GAIN_B0_OFFSET 0x00009cb8
-#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RSSI_0_MSB 7
-#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RSSI_0_LSB 0
-#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RSSI_0_MASK 0x000000ff
-#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RSSI_0_GET(x) (((x) & 0x000000ff) >> 0)
-#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RF_GAIN_0_MSB 15
-#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RF_GAIN_0_LSB 8
-#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RF_GAIN_0_MASK 0x0000ff00
-#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_RF_GAIN_0_GET(x) (((x) & 0x0000ff00) >> 8)
-#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN1_SW_0_MSB 16
-#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN1_SW_0_LSB 16
-#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN1_SW_0_MASK 0x00010000
-#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN1_SW_0_GET(x) (((x) & 0x00010000) >> 16)
-#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN2_SW_0_MSB 17
-#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN2_SW_0_LSB 17
-#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN2_SW_0_MASK 0x00020000
-#define PHY_BB_CHAN_INFO_GAIN_B0_CHAN_INFO_XATTEN2_SW_0_GET(x) (((x) & 0x00020000) >> 17)
-
-/* macros for BB_chan_info_chan_tab_b0 */
-#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_ADDRESS 0x00009cbc
-#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_OFFSET 0x00009cbc
-#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_0_MSB 5
-#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_0_LSB 0
-#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_0_MASK 0x0000003f
-#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_0_GET(x) (((x) & 0x0000003f) >> 0)
-#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_0_MSB 11
-#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_0_LSB 6
-#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_0_MASK 0x00000fc0
-#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_0_GET(x) (((x) & 0x00000fc0) >> 6)
-#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_0_MSB 15
-#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_0_LSB 12
-#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_0_MASK 0x0000f000
-#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_0_GET(x) (((x) & 0x0000f000) >> 12)
-#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_1_MSB 21
-#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_1_LSB 16
-#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_1_MASK 0x003f0000
-#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_Q_1_GET(x) (((x) & 0x003f0000) >> 16)
-#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_1_MSB 27
-#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_1_LSB 22
-#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_1_MASK 0x0fc00000
-#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_MAN_I_1_GET(x) (((x) & 0x0fc00000) >> 22)
-#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_1_MSB 31
-#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_1_LSB 28
-#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_1_MASK 0xf0000000
-#define PHY_BB_CHAN_INFO_CHAN_TAB_B0_EXP_1_GET(x) (((x) & 0xf0000000) >> 28)
-
-/* macros for BB_paprd_am2am_mask */
-#define PHY_BB_PAPRD_AM2AM_MASK_ADDRESS 0x00009de4
-#define PHY_BB_PAPRD_AM2AM_MASK_OFFSET 0x00009de4
-#define PHY_BB_PAPRD_AM2AM_MASK_PAPRD_AM2AM_MASK_MSB 24
-#define PHY_BB_PAPRD_AM2AM_MASK_PAPRD_AM2AM_MASK_LSB 0
-#define PHY_BB_PAPRD_AM2AM_MASK_PAPRD_AM2AM_MASK_MASK 0x01ffffff
-#define PHY_BB_PAPRD_AM2AM_MASK_PAPRD_AM2AM_MASK_GET(x) (((x) & 0x01ffffff) >> 0)
-#define PHY_BB_PAPRD_AM2AM_MASK_PAPRD_AM2AM_MASK_SET(x) (((x) << 0) & 0x01ffffff)
-
-/* macros for BB_paprd_am2pm_mask */
-#define PHY_BB_PAPRD_AM2PM_MASK_ADDRESS 0x00009de8
-#define PHY_BB_PAPRD_AM2PM_MASK_OFFSET 0x00009de8
-#define PHY_BB_PAPRD_AM2PM_MASK_PAPRD_AM2PM_MASK_MSB 24
-#define PHY_BB_PAPRD_AM2PM_MASK_PAPRD_AM2PM_MASK_LSB 0
-#define PHY_BB_PAPRD_AM2PM_MASK_PAPRD_AM2PM_MASK_MASK 0x01ffffff
-#define PHY_BB_PAPRD_AM2PM_MASK_PAPRD_AM2PM_MASK_GET(x) (((x) & 0x01ffffff) >> 0)
-#define PHY_BB_PAPRD_AM2PM_MASK_PAPRD_AM2PM_MASK_SET(x) (((x) << 0) & 0x01ffffff)
-
-/* macros for BB_paprd_ht40_mask */
-#define PHY_BB_PAPRD_HT40_MASK_ADDRESS 0x00009dec
-#define PHY_BB_PAPRD_HT40_MASK_OFFSET 0x00009dec
-#define PHY_BB_PAPRD_HT40_MASK_PAPRD_HT40_MASK_MSB 24
-#define PHY_BB_PAPRD_HT40_MASK_PAPRD_HT40_MASK_LSB 0
-#define PHY_BB_PAPRD_HT40_MASK_PAPRD_HT40_MASK_MASK 0x01ffffff
-#define PHY_BB_PAPRD_HT40_MASK_PAPRD_HT40_MASK_GET(x) (((x) & 0x01ffffff) >> 0)
-#define PHY_BB_PAPRD_HT40_MASK_PAPRD_HT40_MASK_SET(x) (((x) << 0) & 0x01ffffff)
-
-/* macros for BB_paprd_ctrl0 */
-#define PHY_BB_PAPRD_CTRL0_ADDRESS 0x00009df0
-#define PHY_BB_PAPRD_CTRL0_OFFSET 0x00009df0
-#define PHY_BB_PAPRD_CTRL0_PAPRD_ENABLE_MSB 0
-#define PHY_BB_PAPRD_CTRL0_PAPRD_ENABLE_LSB 0
-#define PHY_BB_PAPRD_CTRL0_PAPRD_ENABLE_MASK 0x00000001
-#define PHY_BB_PAPRD_CTRL0_PAPRD_ENABLE_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_BB_PAPRD_CTRL0_PAPRD_ENABLE_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_BB_PAPRD_CTRL0_PAPRD_ADAPTIVE_USE_SINGLE_TABLE_MSB 1
-#define PHY_BB_PAPRD_CTRL0_PAPRD_ADAPTIVE_USE_SINGLE_TABLE_LSB 1
-#define PHY_BB_PAPRD_CTRL0_PAPRD_ADAPTIVE_USE_SINGLE_TABLE_MASK 0x00000002
-#define PHY_BB_PAPRD_CTRL0_PAPRD_ADAPTIVE_USE_SINGLE_TABLE_GET(x) (((x) & 0x00000002) >> 1)
-#define PHY_BB_PAPRD_CTRL0_PAPRD_ADAPTIVE_USE_SINGLE_TABLE_SET(x) (((x) << 1) & 0x00000002)
-#define PHY_BB_PAPRD_CTRL0_PAPRD_VALID_GAIN_MSB 26
-#define PHY_BB_PAPRD_CTRL0_PAPRD_VALID_GAIN_LSB 2
-#define PHY_BB_PAPRD_CTRL0_PAPRD_VALID_GAIN_MASK 0x07fffffc
-#define PHY_BB_PAPRD_CTRL0_PAPRD_VALID_GAIN_GET(x) (((x) & 0x07fffffc) >> 2)
-#define PHY_BB_PAPRD_CTRL0_PAPRD_VALID_GAIN_SET(x) (((x) << 2) & 0x07fffffc)
-#define PHY_BB_PAPRD_CTRL0_PAPRD_MAG_THRSH_MSB 31
-#define PHY_BB_PAPRD_CTRL0_PAPRD_MAG_THRSH_LSB 27
-#define PHY_BB_PAPRD_CTRL0_PAPRD_MAG_THRSH_MASK 0xf8000000
-#define PHY_BB_PAPRD_CTRL0_PAPRD_MAG_THRSH_GET(x) (((x) & 0xf8000000) >> 27)
-#define PHY_BB_PAPRD_CTRL0_PAPRD_MAG_THRSH_SET(x) (((x) << 27) & 0xf8000000)
-
-/* macros for BB_paprd_ctrl1 */
-#define PHY_BB_PAPRD_CTRL1_ADDRESS 0x00009df4
-#define PHY_BB_PAPRD_CTRL1_OFFSET 0x00009df4
-#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_SCALING_ENABLE_MSB 0
-#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_SCALING_ENABLE_LSB 0
-#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_SCALING_ENABLE_MASK 0x00000001
-#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_SCALING_ENABLE_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_SCALING_ENABLE_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2AM_ENABLE_MSB 1
-#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2AM_ENABLE_LSB 1
-#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2AM_ENABLE_MASK 0x00000002
-#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2AM_ENABLE_GET(x) (((x) & 0x00000002) >> 1)
-#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2AM_ENABLE_SET(x) (((x) << 1) & 0x00000002)
-#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2PM_ENABLE_MSB 2
-#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2PM_ENABLE_LSB 2
-#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2PM_ENABLE_MASK 0x00000004
-#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2PM_ENABLE_GET(x) (((x) & 0x00000004) >> 2)
-#define PHY_BB_PAPRD_CTRL1_PAPRD_ADAPTIVE_AM2PM_ENABLE_SET(x) (((x) << 2) & 0x00000004)
-#define PHY_BB_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL_MSB 8
-#define PHY_BB_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL_LSB 3
-#define PHY_BB_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL_MASK 0x000001f8
-#define PHY_BB_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL_GET(x) (((x) & 0x000001f8) >> 3)
-#define PHY_BB_PAPRD_CTRL1_PAPRD_POWER_AT_AM2AM_CAL_SET(x) (((x) << 3) & 0x000001f8)
-#define PHY_BB_PAPRD_CTRL1_PA_GAIN_SCALE_FACTOR_MSB 16
-#define PHY_BB_PAPRD_CTRL1_PA_GAIN_SCALE_FACTOR_LSB 9
-#define PHY_BB_PAPRD_CTRL1_PA_GAIN_SCALE_FACTOR_MASK 0x0001fe00
-#define PHY_BB_PAPRD_CTRL1_PA_GAIN_SCALE_FACTOR_GET(x) (((x) & 0x0001fe00) >> 9)
-#define PHY_BB_PAPRD_CTRL1_PA_GAIN_SCALE_FACTOR_SET(x) (((x) << 9) & 0x0001fe00)
-#define PHY_BB_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACTOR_MSB 26
-#define PHY_BB_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACTOR_LSB 17
-#define PHY_BB_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACTOR_MASK 0x07fe0000
-#define PHY_BB_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACTOR_GET(x) (((x) & 0x07fe0000) >> 17)
-#define PHY_BB_PAPRD_CTRL1_PAPRD_MAG_SCALE_FACTOR_SET(x) (((x) << 17) & 0x07fe0000)
-#define PHY_BB_PAPRD_CTRL1_PAPRD_TRAINER_IANDQ_SEL_MSB 27
-#define PHY_BB_PAPRD_CTRL1_PAPRD_TRAINER_IANDQ_SEL_LSB 27
-#define PHY_BB_PAPRD_CTRL1_PAPRD_TRAINER_IANDQ_SEL_MASK 0x08000000
-#define PHY_BB_PAPRD_CTRL1_PAPRD_TRAINER_IANDQ_SEL_GET(x) (((x) & 0x08000000) >> 27)
-#define PHY_BB_PAPRD_CTRL1_PAPRD_TRAINER_IANDQ_SEL_SET(x) (((x) << 27) & 0x08000000)
-
-/* macros for BB_pa_gain123 */
-#define PHY_BB_PA_GAIN123_ADDRESS 0x00009df8
-#define PHY_BB_PA_GAIN123_OFFSET 0x00009df8
-#define PHY_BB_PA_GAIN123_PA_GAIN1_MSB 9
-#define PHY_BB_PA_GAIN123_PA_GAIN1_LSB 0
-#define PHY_BB_PA_GAIN123_PA_GAIN1_MASK 0x000003ff
-#define PHY_BB_PA_GAIN123_PA_GAIN1_GET(x) (((x) & 0x000003ff) >> 0)
-#define PHY_BB_PA_GAIN123_PA_GAIN1_SET(x) (((x) << 0) & 0x000003ff)
-#define PHY_BB_PA_GAIN123_PA_GAIN2_MSB 19
-#define PHY_BB_PA_GAIN123_PA_GAIN2_LSB 10
-#define PHY_BB_PA_GAIN123_PA_GAIN2_MASK 0x000ffc00
-#define PHY_BB_PA_GAIN123_PA_GAIN2_GET(x) (((x) & 0x000ffc00) >> 10)
-#define PHY_BB_PA_GAIN123_PA_GAIN2_SET(x) (((x) << 10) & 0x000ffc00)
-#define PHY_BB_PA_GAIN123_PA_GAIN3_MSB 29
-#define PHY_BB_PA_GAIN123_PA_GAIN3_LSB 20
-#define PHY_BB_PA_GAIN123_PA_GAIN3_MASK 0x3ff00000
-#define PHY_BB_PA_GAIN123_PA_GAIN3_GET(x) (((x) & 0x3ff00000) >> 20)
-#define PHY_BB_PA_GAIN123_PA_GAIN3_SET(x) (((x) << 20) & 0x3ff00000)
-
-/* macros for BB_pa_gain45 */
-#define PHY_BB_PA_GAIN45_ADDRESS 0x00009dfc
-#define PHY_BB_PA_GAIN45_OFFSET 0x00009dfc
-#define PHY_BB_PA_GAIN45_PA_GAIN4_MSB 9
-#define PHY_BB_PA_GAIN45_PA_GAIN4_LSB 0
-#define PHY_BB_PA_GAIN45_PA_GAIN4_MASK 0x000003ff
-#define PHY_BB_PA_GAIN45_PA_GAIN4_GET(x) (((x) & 0x000003ff) >> 0)
-#define PHY_BB_PA_GAIN45_PA_GAIN4_SET(x) (((x) << 0) & 0x000003ff)
-#define PHY_BB_PA_GAIN45_PA_GAIN5_MSB 19
-#define PHY_BB_PA_GAIN45_PA_GAIN5_LSB 10
-#define PHY_BB_PA_GAIN45_PA_GAIN5_MASK 0x000ffc00
-#define PHY_BB_PA_GAIN45_PA_GAIN5_GET(x) (((x) & 0x000ffc00) >> 10)
-#define PHY_BB_PA_GAIN45_PA_GAIN5_SET(x) (((x) << 10) & 0x000ffc00)
-#define PHY_BB_PA_GAIN45_PAPRD_ADAPTIVE_TABLE_VALID_MSB 24
-#define PHY_BB_PA_GAIN45_PAPRD_ADAPTIVE_TABLE_VALID_LSB 20
-#define PHY_BB_PA_GAIN45_PAPRD_ADAPTIVE_TABLE_VALID_MASK 0x01f00000
-#define PHY_BB_PA_GAIN45_PAPRD_ADAPTIVE_TABLE_VALID_GET(x) (((x) & 0x01f00000) >> 20)
-#define PHY_BB_PA_GAIN45_PAPRD_ADAPTIVE_TABLE_VALID_SET(x) (((x) << 20) & 0x01f00000)
-
-/* macros for BB_paprd_pre_post_scale_0 */
-#define PHY_BB_PAPRD_PRE_POST_SCALE_0_ADDRESS 0x00009e00
-#define PHY_BB_PAPRD_PRE_POST_SCALE_0_OFFSET 0x00009e00
-#define PHY_BB_PAPRD_PRE_POST_SCALE_0_PAPRD_PRE_POST_SCALING_0_MSB 17
-#define PHY_BB_PAPRD_PRE_POST_SCALE_0_PAPRD_PRE_POST_SCALING_0_LSB 0
-#define PHY_BB_PAPRD_PRE_POST_SCALE_0_PAPRD_PRE_POST_SCALING_0_MASK 0x0003ffff
-#define PHY_BB_PAPRD_PRE_POST_SCALE_0_PAPRD_PRE_POST_SCALING_0_GET(x) (((x) & 0x0003ffff) >> 0)
-#define PHY_BB_PAPRD_PRE_POST_SCALE_0_PAPRD_PRE_POST_SCALING_0_SET(x) (((x) << 0) & 0x0003ffff)
-
-/* macros for BB_paprd_pre_post_scale_1 */
-#define PHY_BB_PAPRD_PRE_POST_SCALE_1_ADDRESS 0x00009e04
-#define PHY_BB_PAPRD_PRE_POST_SCALE_1_OFFSET 0x00009e04
-#define PHY_BB_PAPRD_PRE_POST_SCALE_1_PAPRD_PRE_POST_SCALING_1_MSB 17
-#define PHY_BB_PAPRD_PRE_POST_SCALE_1_PAPRD_PRE_POST_SCALING_1_LSB 0
-#define PHY_BB_PAPRD_PRE_POST_SCALE_1_PAPRD_PRE_POST_SCALING_1_MASK 0x0003ffff
-#define PHY_BB_PAPRD_PRE_POST_SCALE_1_PAPRD_PRE_POST_SCALING_1_GET(x) (((x) & 0x0003ffff) >> 0)
-#define PHY_BB_PAPRD_PRE_POST_SCALE_1_PAPRD_PRE_POST_SCALING_1_SET(x) (((x) << 0) & 0x0003ffff)
-
-/* macros for BB_paprd_pre_post_scale_2 */
-#define PHY_BB_PAPRD_PRE_POST_SCALE_2_ADDRESS 0x00009e08
-#define PHY_BB_PAPRD_PRE_POST_SCALE_2_OFFSET 0x00009e08
-#define PHY_BB_PAPRD_PRE_POST_SCALE_2_PAPRD_PRE_POST_SCALING_2_MSB 17
-#define PHY_BB_PAPRD_PRE_POST_SCALE_2_PAPRD_PRE_POST_SCALING_2_LSB 0
-#define PHY_BB_PAPRD_PRE_POST_SCALE_2_PAPRD_PRE_POST_SCALING_2_MASK 0x0003ffff
-#define PHY_BB_PAPRD_PRE_POST_SCALE_2_PAPRD_PRE_POST_SCALING_2_GET(x) (((x) & 0x0003ffff) >> 0)
-#define PHY_BB_PAPRD_PRE_POST_SCALE_2_PAPRD_PRE_POST_SCALING_2_SET(x) (((x) << 0) & 0x0003ffff)
-
-/* macros for BB_paprd_pre_post_scale_3 */
-#define PHY_BB_PAPRD_PRE_POST_SCALE_3_ADDRESS 0x00009e0c
-#define PHY_BB_PAPRD_PRE_POST_SCALE_3_OFFSET 0x00009e0c
-#define PHY_BB_PAPRD_PRE_POST_SCALE_3_PAPRD_PRE_POST_SCALING_3_MSB 17
-#define PHY_BB_PAPRD_PRE_POST_SCALE_3_PAPRD_PRE_POST_SCALING_3_LSB 0
-#define PHY_BB_PAPRD_PRE_POST_SCALE_3_PAPRD_PRE_POST_SCALING_3_MASK 0x0003ffff
-#define PHY_BB_PAPRD_PRE_POST_SCALE_3_PAPRD_PRE_POST_SCALING_3_GET(x) (((x) & 0x0003ffff) >> 0)
-#define PHY_BB_PAPRD_PRE_POST_SCALE_3_PAPRD_PRE_POST_SCALING_3_SET(x) (((x) << 0) & 0x0003ffff)
-
-/* macros for BB_paprd_pre_post_scale_4 */
-#define PHY_BB_PAPRD_PRE_POST_SCALE_4_ADDRESS 0x00009e10
-#define PHY_BB_PAPRD_PRE_POST_SCALE_4_OFFSET 0x00009e10
-#define PHY_BB_PAPRD_PRE_POST_SCALE_4_PAPRD_PRE_POST_SCALING_4_MSB 17
-#define PHY_BB_PAPRD_PRE_POST_SCALE_4_PAPRD_PRE_POST_SCALING_4_LSB 0
-#define PHY_BB_PAPRD_PRE_POST_SCALE_4_PAPRD_PRE_POST_SCALING_4_MASK 0x0003ffff
-#define PHY_BB_PAPRD_PRE_POST_SCALE_4_PAPRD_PRE_POST_SCALING_4_GET(x) (((x) & 0x0003ffff) >> 0)
-#define PHY_BB_PAPRD_PRE_POST_SCALE_4_PAPRD_PRE_POST_SCALING_4_SET(x) (((x) << 0) & 0x0003ffff)
-
-/* macros for BB_paprd_pre_post_scale_5 */
-#define PHY_BB_PAPRD_PRE_POST_SCALE_5_ADDRESS 0x00009e14
-#define PHY_BB_PAPRD_PRE_POST_SCALE_5_OFFSET 0x00009e14
-#define PHY_BB_PAPRD_PRE_POST_SCALE_5_PAPRD_PRE_POST_SCALING_5_MSB 17
-#define PHY_BB_PAPRD_PRE_POST_SCALE_5_PAPRD_PRE_POST_SCALING_5_LSB 0
-#define PHY_BB_PAPRD_PRE_POST_SCALE_5_PAPRD_PRE_POST_SCALING_5_MASK 0x0003ffff
-#define PHY_BB_PAPRD_PRE_POST_SCALE_5_PAPRD_PRE_POST_SCALING_5_GET(x) (((x) & 0x0003ffff) >> 0)
-#define PHY_BB_PAPRD_PRE_POST_SCALE_5_PAPRD_PRE_POST_SCALING_5_SET(x) (((x) << 0) & 0x0003ffff)
-
-/* macros for BB_paprd_pre_post_scale_6 */
-#define PHY_BB_PAPRD_PRE_POST_SCALE_6_ADDRESS 0x00009e18
-#define PHY_BB_PAPRD_PRE_POST_SCALE_6_OFFSET 0x00009e18
-#define PHY_BB_PAPRD_PRE_POST_SCALE_6_PAPRD_PRE_POST_SCALING_6_MSB 17
-#define PHY_BB_PAPRD_PRE_POST_SCALE_6_PAPRD_PRE_POST_SCALING_6_LSB 0
-#define PHY_BB_PAPRD_PRE_POST_SCALE_6_PAPRD_PRE_POST_SCALING_6_MASK 0x0003ffff
-#define PHY_BB_PAPRD_PRE_POST_SCALE_6_PAPRD_PRE_POST_SCALING_6_GET(x) (((x) & 0x0003ffff) >> 0)
-#define PHY_BB_PAPRD_PRE_POST_SCALE_6_PAPRD_PRE_POST_SCALING_6_SET(x) (((x) << 0) & 0x0003ffff)
-
-/* macros for BB_paprd_pre_post_scale_7 */
-#define PHY_BB_PAPRD_PRE_POST_SCALE_7_ADDRESS 0x00009e1c
-#define PHY_BB_PAPRD_PRE_POST_SCALE_7_OFFSET 0x00009e1c
-#define PHY_BB_PAPRD_PRE_POST_SCALE_7_PAPRD_PRE_POST_SCALING_7_MSB 17
-#define PHY_BB_PAPRD_PRE_POST_SCALE_7_PAPRD_PRE_POST_SCALING_7_LSB 0
-#define PHY_BB_PAPRD_PRE_POST_SCALE_7_PAPRD_PRE_POST_SCALING_7_MASK 0x0003ffff
-#define PHY_BB_PAPRD_PRE_POST_SCALE_7_PAPRD_PRE_POST_SCALING_7_GET(x) (((x) & 0x0003ffff) >> 0)
-#define PHY_BB_PAPRD_PRE_POST_SCALE_7_PAPRD_PRE_POST_SCALING_7_SET(x) (((x) << 0) & 0x0003ffff)
-
-/* macros for BB_paprd_mem_tab */
-#define PHY_BB_PAPRD_MEM_TAB_ADDRESS 0x00009e20
-#define PHY_BB_PAPRD_MEM_TAB_OFFSET 0x00009e20
-#define PHY_BB_PAPRD_MEM_TAB_PAPRD_MEM_MSB 21
-#define PHY_BB_PAPRD_MEM_TAB_PAPRD_MEM_LSB 0
-#define PHY_BB_PAPRD_MEM_TAB_PAPRD_MEM_MASK 0x003fffff
-#define PHY_BB_PAPRD_MEM_TAB_PAPRD_MEM_GET(x) (((x) & 0x003fffff) >> 0)
-#define PHY_BB_PAPRD_MEM_TAB_PAPRD_MEM_SET(x) (((x) << 0) & 0x003fffff)
-
-/* macros for BB_peak_det_ctrl_1 */
-#define PHY_BB_PEAK_DET_CTRL_1_ADDRESS 0x0000a000
-#define PHY_BB_PEAK_DET_CTRL_1_OFFSET 0x0000a000
-#define PHY_BB_PEAK_DET_CTRL_1_USE_OC_GAIN_TABLE_MSB 0
-#define PHY_BB_PEAK_DET_CTRL_1_USE_OC_GAIN_TABLE_LSB 0
-#define PHY_BB_PEAK_DET_CTRL_1_USE_OC_GAIN_TABLE_MASK 0x00000001
-#define PHY_BB_PEAK_DET_CTRL_1_USE_OC_GAIN_TABLE_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_BB_PEAK_DET_CTRL_1_USE_OC_GAIN_TABLE_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_BB_PEAK_DET_CTRL_1_USE_PEAK_DET_MSB 1
-#define PHY_BB_PEAK_DET_CTRL_1_USE_PEAK_DET_LSB 1
-#define PHY_BB_PEAK_DET_CTRL_1_USE_PEAK_DET_MASK 0x00000002
-#define PHY_BB_PEAK_DET_CTRL_1_USE_PEAK_DET_GET(x) (((x) & 0x00000002) >> 1)
-#define PHY_BB_PEAK_DET_CTRL_1_USE_PEAK_DET_SET(x) (((x) << 1) & 0x00000002)
-#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_WIN_LEN_MSB 7
-#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_WIN_LEN_LSB 2
-#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_WIN_LEN_MASK 0x000000fc
-#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_WIN_LEN_GET(x) (((x) & 0x000000fc) >> 2)
-#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_WIN_LEN_SET(x) (((x) << 2) & 0x000000fc)
-#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_LOW_MSB 12
-#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_LOW_LSB 8
-#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_LOW_MASK 0x00001f00
-#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_LOW_GET(x) (((x) & 0x00001f00) >> 8)
-#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_LOW_SET(x) (((x) << 8) & 0x00001f00)
-#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_MED_MSB 17
-#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_MED_LSB 13
-#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_MED_MASK 0x0003e000
-#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_MED_GET(x) (((x) & 0x0003e000) >> 13)
-#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_MED_SET(x) (((x) << 13) & 0x0003e000)
-#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_HIGH_MSB 22
-#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_HIGH_LSB 18
-#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_HIGH_MASK 0x007c0000
-#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_HIGH_GET(x) (((x) & 0x007c0000) >> 18)
-#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_TALLY_THR_HIGH_SET(x) (((x) << 18) & 0x007c0000)
-#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_SETTLING_MSB 29
-#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_SETTLING_LSB 23
-#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_SETTLING_MASK 0x3f800000
-#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_SETTLING_GET(x) (((x) & 0x3f800000) >> 23)
-#define PHY_BB_PEAK_DET_CTRL_1_PEAK_DET_SETTLING_SET(x) (((x) << 23) & 0x3f800000)
-#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_CAL_MSB 30
-#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_CAL_LSB 30
-#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_CAL_MASK 0x40000000
-#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_CAL_GET(x) (((x) & 0x40000000) >> 30)
-#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_CAL_SET(x) (((x) << 30) & 0x40000000)
-#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_RX_MSB 31
-#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_RX_LSB 31
-#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_RX_MASK 0x80000000
-#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_RX_GET(x) (((x) & 0x80000000) >> 31)
-#define PHY_BB_PEAK_DET_CTRL_1_PWD_PKDET_DURING_RX_SET(x) (((x) << 31) & 0x80000000)
-
-/* macros for BB_peak_det_ctrl_2 */
-#define PHY_BB_PEAK_DET_CTRL_2_ADDRESS 0x0000a004
-#define PHY_BB_PEAK_DET_CTRL_2_OFFSET 0x0000a004
-#define PHY_BB_PEAK_DET_CTRL_2_RFSAT_2_ADD_RFGAIN_DEL_MSB 9
-#define PHY_BB_PEAK_DET_CTRL_2_RFSAT_2_ADD_RFGAIN_DEL_LSB 0
-#define PHY_BB_PEAK_DET_CTRL_2_RFSAT_2_ADD_RFGAIN_DEL_MASK 0x000003ff
-#define PHY_BB_PEAK_DET_CTRL_2_RFSAT_2_ADD_RFGAIN_DEL_GET(x) (((x) & 0x000003ff) >> 0)
-#define PHY_BB_PEAK_DET_CTRL_2_RFSAT_2_ADD_RFGAIN_DEL_SET(x) (((x) << 0) & 0x000003ff)
-#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_LOW_MSB 14
-#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_LOW_LSB 10
-#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_LOW_MASK 0x00007c00
-#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_LOW_GET(x) (((x) & 0x00007c00) >> 10)
-#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_LOW_SET(x) (((x) << 10) & 0x00007c00)
-#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_MED_MSB 19
-#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_MED_LSB 15
-#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_MED_MASK 0x000f8000
-#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_MED_GET(x) (((x) & 0x000f8000) >> 15)
-#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_MED_SET(x) (((x) << 15) & 0x000f8000)
-#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_HIGH_MSB 24
-#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_HIGH_LSB 20
-#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_HIGH_MASK 0x01f00000
-#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_HIGH_GET(x) (((x) & 0x01f00000) >> 20)
-#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_HIGH_SET(x) (((x) << 20) & 0x01f00000)
-#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_NON_MSB 29
-#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_NON_LSB 25
-#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_NON_MASK 0x3e000000
-#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_NON_GET(x) (((x) & 0x3e000000) >> 25)
-#define PHY_BB_PEAK_DET_CTRL_2_RF_GAIN_DROP_DB_NON_SET(x) (((x) << 25) & 0x3e000000)
-
-/* macros for BB_rx_gain_bounds_1 */
-#define PHY_BB_RX_GAIN_BOUNDS_1_ADDRESS 0x0000a008
-#define PHY_BB_RX_GAIN_BOUNDS_1_OFFSET 0x0000a008
-#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_MB_GAIN_MSB 7
-#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_MB_GAIN_LSB 0
-#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_MB_GAIN_MASK 0x000000ff
-#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_MB_GAIN_GET(x) (((x) & 0x000000ff) >> 0)
-#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_MB_GAIN_SET(x) (((x) << 0) & 0x000000ff)
-#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_REF_MSB 15
-#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_REF_LSB 8
-#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_REF_MASK 0x0000ff00
-#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_REF_GET(x) (((x) & 0x0000ff00) >> 8)
-#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_REF_SET(x) (((x) << 8) & 0x0000ff00)
-#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_MSB 23
-#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_LSB 16
-#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_MASK 0x00ff0000
-#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_GET(x) (((x) & 0x00ff0000) >> 16)
-#define PHY_BB_RX_GAIN_BOUNDS_1_RX_MAX_RF_GAIN_SET(x) (((x) << 16) & 0x00ff0000)
-#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_2G_MSB 24
-#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_2G_LSB 24
-#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_2G_MASK 0x01000000
-#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_2G_GET(x) (((x) & 0x01000000) >> 24)
-#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_2G_SET(x) (((x) << 24) & 0x01000000)
-#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_5G_MSB 25
-#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_5G_LSB 25
-#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_5G_MASK 0x02000000
-#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_5G_GET(x) (((x) & 0x02000000) >> 25)
-#define PHY_BB_RX_GAIN_BOUNDS_1_RX_OCGAIN_SEL_5G_SET(x) (((x) << 25) & 0x02000000)
-
-/* macros for BB_rx_gain_bounds_2 */
-#define PHY_BB_RX_GAIN_BOUNDS_2_ADDRESS 0x0000a00c
-#define PHY_BB_RX_GAIN_BOUNDS_2_OFFSET 0x0000a00c
-#define PHY_BB_RX_GAIN_BOUNDS_2_GC_RSSI_LOW_DB_MSB 7
-#define PHY_BB_RX_GAIN_BOUNDS_2_GC_RSSI_LOW_DB_LSB 0
-#define PHY_BB_RX_GAIN_BOUNDS_2_GC_RSSI_LOW_DB_MASK 0x000000ff
-#define PHY_BB_RX_GAIN_BOUNDS_2_GC_RSSI_LOW_DB_GET(x) (((x) & 0x000000ff) >> 0)
-#define PHY_BB_RX_GAIN_BOUNDS_2_GC_RSSI_LOW_DB_SET(x) (((x) << 0) & 0x000000ff)
-#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_REF_BASE_ADDR_MSB 15
-#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_REF_BASE_ADDR_LSB 8
-#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_REF_BASE_ADDR_MASK 0x0000ff00
-#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_REF_BASE_ADDR_GET(x) (((x) & 0x0000ff00) >> 8)
-#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_REF_BASE_ADDR_SET(x) (((x) << 8) & 0x0000ff00)
-#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_BASE_ADDR_MSB 23
-#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_BASE_ADDR_LSB 16
-#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_BASE_ADDR_MASK 0x00ff0000
-#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_BASE_ADDR_GET(x) (((x) & 0x00ff0000) >> 16)
-#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_BASE_ADDR_SET(x) (((x) << 16) & 0x00ff0000)
-#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_DIV_BASE_ADDR_MSB 31
-#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_DIV_BASE_ADDR_LSB 24
-#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_DIV_BASE_ADDR_MASK 0xff000000
-#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_DIV_BASE_ADDR_GET(x) (((x) & 0xff000000) >> 24)
-#define PHY_BB_RX_GAIN_BOUNDS_2_RF_GAIN_DIV_BASE_ADDR_SET(x) (((x) << 24) & 0xff000000)
-
-/* macros for BB_peak_det_cal_ctrl */
-#define PHY_BB_PEAK_DET_CAL_CTRL_ADDRESS 0x0000a010
-#define PHY_BB_PEAK_DET_CAL_CTRL_OFFSET 0x0000a010
-#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_WIN_THR_MSB 5
-#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_WIN_THR_LSB 0
-#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_WIN_THR_MASK 0x0000003f
-#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_WIN_THR_GET(x) (((x) & 0x0000003f) >> 0)
-#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_WIN_THR_SET(x) (((x) << 0) & 0x0000003f)
-#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_BIAS_MSB 11
-#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_BIAS_LSB 6
-#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_BIAS_MASK 0x00000fc0
-#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_BIAS_GET(x) (((x) & 0x00000fc0) >> 6)
-#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_BIAS_SET(x) (((x) << 6) & 0x00000fc0)
-#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_MEAS_TIME_SEL_MSB 13
-#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_MEAS_TIME_SEL_LSB 12
-#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_MEAS_TIME_SEL_MASK 0x00003000
-#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_MEAS_TIME_SEL_GET(x) (((x) & 0x00003000) >> 12)
-#define PHY_BB_PEAK_DET_CAL_CTRL_PKDET_CAL_MEAS_TIME_SEL_SET(x) (((x) << 12) & 0x00003000)
-
-/* macros for BB_agc_dig_dc_ctrl */
-#define PHY_BB_AGC_DIG_DC_CTRL_ADDRESS 0x0000a014
-#define PHY_BB_AGC_DIG_DC_CTRL_OFFSET 0x0000a014
-#define PHY_BB_AGC_DIG_DC_CTRL_USE_DIG_DC_MSB 0
-#define PHY_BB_AGC_DIG_DC_CTRL_USE_DIG_DC_LSB 0
-#define PHY_BB_AGC_DIG_DC_CTRL_USE_DIG_DC_MASK 0x00000001
-#define PHY_BB_AGC_DIG_DC_CTRL_USE_DIG_DC_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_BB_AGC_DIG_DC_CTRL_USE_DIG_DC_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_SCALE_BIAS_MSB 3
-#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_SCALE_BIAS_LSB 1
-#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_SCALE_BIAS_MASK 0x0000000e
-#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_SCALE_BIAS_GET(x) (((x) & 0x0000000e) >> 1)
-#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_SCALE_BIAS_SET(x) (((x) << 1) & 0x0000000e)
-#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_CORRECT_CAP_MSB 9
-#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_CORRECT_CAP_LSB 4
-#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_CORRECT_CAP_MASK 0x000003f0
-#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_CORRECT_CAP_GET(x) (((x) & 0x000003f0) >> 4)
-#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_CORRECT_CAP_SET(x) (((x) << 4) & 0x000003f0)
-#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_MIXER_SEL_MASK_MSB 31
-#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_MIXER_SEL_MASK_LSB 16
-#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_MIXER_SEL_MASK_MASK 0xffff0000
-#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_MIXER_SEL_MASK_GET(x) (((x) & 0xffff0000) >> 16)
-#define PHY_BB_AGC_DIG_DC_CTRL_DIG_DC_MIXER_SEL_MASK_SET(x) (((x) << 16) & 0xffff0000)
-
-/* macros for BB_agc_dig_dc_status_i_b0 */
-#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_ADDRESS 0x0000a018
-#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_OFFSET 0x0000a018
-#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C1_RES_I_0_MSB 8
-#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C1_RES_I_0_LSB 0
-#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C1_RES_I_0_MASK 0x000001ff
-#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C1_RES_I_0_GET(x) (((x) & 0x000001ff) >> 0)
-#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C2_RES_I_0_MSB 17
-#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C2_RES_I_0_LSB 9
-#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C2_RES_I_0_MASK 0x0003fe00
-#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C2_RES_I_0_GET(x) (((x) & 0x0003fe00) >> 9)
-#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C3_RES_I_0_MSB 26
-#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C3_RES_I_0_LSB 18
-#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C3_RES_I_0_MASK 0x07fc0000
-#define PHY_BB_AGC_DIG_DC_STATUS_I_B0_DIG_DC_C3_RES_I_0_GET(x) (((x) & 0x07fc0000) >> 18)
-
-/* macros for BB_agc_dig_dc_status_q_b0 */
-#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_ADDRESS 0x0000a01c
-#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_OFFSET 0x0000a01c
-#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C1_RES_Q_0_MSB 8
-#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C1_RES_Q_0_LSB 0
-#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C1_RES_Q_0_MASK 0x000001ff
-#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C1_RES_Q_0_GET(x) (((x) & 0x000001ff) >> 0)
-#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C2_RES_Q_0_MSB 17
-#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C2_RES_Q_0_LSB 9
-#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C2_RES_Q_0_MASK 0x0003fe00
-#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C2_RES_Q_0_GET(x) (((x) & 0x0003fe00) >> 9)
-#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C3_RES_Q_0_MSB 26
-#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C3_RES_Q_0_LSB 18
-#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C3_RES_Q_0_MASK 0x07fc0000
-#define PHY_BB_AGC_DIG_DC_STATUS_Q_B0_DIG_DC_C3_RES_Q_0_GET(x) (((x) & 0x07fc0000) >> 18)
-
-/* macros for BB_bbb_txfir_0 */
-#define PHY_BB_BBB_TXFIR_0_ADDRESS 0x0000a1f4
-#define PHY_BB_BBB_TXFIR_0_OFFSET 0x0000a1f4
-#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H0_MSB 3
-#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H0_LSB 0
-#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H0_MASK 0x0000000f
-#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H0_GET(x) (((x) & 0x0000000f) >> 0)
-#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H0_SET(x) (((x) << 0) & 0x0000000f)
-#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H1_MSB 11
-#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H1_LSB 8
-#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H1_MASK 0x00000f00
-#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H1_GET(x) (((x) & 0x00000f00) >> 8)
-#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H1_SET(x) (((x) << 8) & 0x00000f00)
-#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H2_MSB 20
-#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H2_LSB 16
-#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H2_MASK 0x001f0000
-#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H2_GET(x) (((x) & 0x001f0000) >> 16)
-#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H2_SET(x) (((x) << 16) & 0x001f0000)
-#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H3_MSB 28
-#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H3_LSB 24
-#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H3_MASK 0x1f000000
-#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H3_GET(x) (((x) & 0x1f000000) >> 24)
-#define PHY_BB_BBB_TXFIR_0_TXFIR_COEFF_H3_SET(x) (((x) << 24) & 0x1f000000)
-
-/* macros for BB_bbb_txfir_1 */
-#define PHY_BB_BBB_TXFIR_1_ADDRESS 0x0000a1f8
-#define PHY_BB_BBB_TXFIR_1_OFFSET 0x0000a1f8
-#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H4_MSB 5
-#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H4_LSB 0
-#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H4_MASK 0x0000003f
-#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H4_GET(x) (((x) & 0x0000003f) >> 0)
-#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H4_SET(x) (((x) << 0) & 0x0000003f)
-#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H5_MSB 13
-#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H5_LSB 8
-#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H5_MASK 0x00003f00
-#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H5_GET(x) (((x) & 0x00003f00) >> 8)
-#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H5_SET(x) (((x) << 8) & 0x00003f00)
-#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H6_MSB 22
-#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H6_LSB 16
-#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H6_MASK 0x007f0000
-#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H6_GET(x) (((x) & 0x007f0000) >> 16)
-#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H6_SET(x) (((x) << 16) & 0x007f0000)
-#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H7_MSB 30
-#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H7_LSB 24
-#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H7_MASK 0x7f000000
-#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H7_GET(x) (((x) & 0x7f000000) >> 24)
-#define PHY_BB_BBB_TXFIR_1_TXFIR_COEFF_H7_SET(x) (((x) << 24) & 0x7f000000)
-
-/* macros for BB_bbb_txfir_2 */
-#define PHY_BB_BBB_TXFIR_2_ADDRESS 0x0000a1fc
-#define PHY_BB_BBB_TXFIR_2_OFFSET 0x0000a1fc
-#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H8_MSB 7
-#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H8_LSB 0
-#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H8_MASK 0x000000ff
-#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H8_GET(x) (((x) & 0x000000ff) >> 0)
-#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H8_SET(x) (((x) << 0) & 0x000000ff)
-#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H9_MSB 15
-#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H9_LSB 8
-#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H9_MASK 0x0000ff00
-#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H9_GET(x) (((x) & 0x0000ff00) >> 8)
-#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H9_SET(x) (((x) << 8) & 0x0000ff00)
-#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H10_MSB 23
-#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H10_LSB 16
-#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H10_MASK 0x00ff0000
-#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H10_GET(x) (((x) & 0x00ff0000) >> 16)
-#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H10_SET(x) (((x) << 16) & 0x00ff0000)
-#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H11_MSB 31
-#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H11_LSB 24
-#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H11_MASK 0xff000000
-#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H11_GET(x) (((x) & 0xff000000) >> 24)
-#define PHY_BB_BBB_TXFIR_2_TXFIR_COEFF_H11_SET(x) (((x) << 24) & 0xff000000)
-
-/* macros for BB_modes_select */
-#define PHY_BB_MODES_SELECT_ADDRESS 0x0000a200
-#define PHY_BB_MODES_SELECT_OFFSET 0x0000a200
-#define PHY_BB_MODES_SELECT_CCK_MODE_MSB 0
-#define PHY_BB_MODES_SELECT_CCK_MODE_LSB 0
-#define PHY_BB_MODES_SELECT_CCK_MODE_MASK 0x00000001
-#define PHY_BB_MODES_SELECT_CCK_MODE_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_BB_MODES_SELECT_CCK_MODE_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_BB_MODES_SELECT_DYN_OFDM_CCK_MODE_MSB 2
-#define PHY_BB_MODES_SELECT_DYN_OFDM_CCK_MODE_LSB 2
-#define PHY_BB_MODES_SELECT_DYN_OFDM_CCK_MODE_MASK 0x00000004
-#define PHY_BB_MODES_SELECT_DYN_OFDM_CCK_MODE_GET(x) (((x) & 0x00000004) >> 2)
-#define PHY_BB_MODES_SELECT_DYN_OFDM_CCK_MODE_SET(x) (((x) << 2) & 0x00000004)
-#define PHY_BB_MODES_SELECT_HALF_RATE_MODE_MSB 5
-#define PHY_BB_MODES_SELECT_HALF_RATE_MODE_LSB 5
-#define PHY_BB_MODES_SELECT_HALF_RATE_MODE_MASK 0x00000020
-#define PHY_BB_MODES_SELECT_HALF_RATE_MODE_GET(x) (((x) & 0x00000020) >> 5)
-#define PHY_BB_MODES_SELECT_HALF_RATE_MODE_SET(x) (((x) << 5) & 0x00000020)
-#define PHY_BB_MODES_SELECT_QUARTER_RATE_MODE_MSB 6
-#define PHY_BB_MODES_SELECT_QUARTER_RATE_MODE_LSB 6
-#define PHY_BB_MODES_SELECT_QUARTER_RATE_MODE_MASK 0x00000040
-#define PHY_BB_MODES_SELECT_QUARTER_RATE_MODE_GET(x) (((x) & 0x00000040) >> 6)
-#define PHY_BB_MODES_SELECT_QUARTER_RATE_MODE_SET(x) (((x) << 6) & 0x00000040)
-#define PHY_BB_MODES_SELECT_MAC_CLK_MODE_MSB 7
-#define PHY_BB_MODES_SELECT_MAC_CLK_MODE_LSB 7
-#define PHY_BB_MODES_SELECT_MAC_CLK_MODE_MASK 0x00000080
-#define PHY_BB_MODES_SELECT_MAC_CLK_MODE_GET(x) (((x) & 0x00000080) >> 7)
-#define PHY_BB_MODES_SELECT_MAC_CLK_MODE_SET(x) (((x) << 7) & 0x00000080)
-#define PHY_BB_MODES_SELECT_DISABLE_DYN_CCK_DET_MSB 8
-#define PHY_BB_MODES_SELECT_DISABLE_DYN_CCK_DET_LSB 8
-#define PHY_BB_MODES_SELECT_DISABLE_DYN_CCK_DET_MASK 0x00000100
-#define PHY_BB_MODES_SELECT_DISABLE_DYN_CCK_DET_GET(x) (((x) & 0x00000100) >> 8)
-#define PHY_BB_MODES_SELECT_DISABLE_DYN_CCK_DET_SET(x) (((x) << 8) & 0x00000100)
-
-/* macros for BB_bbb_tx_ctrl */
-#define PHY_BB_BBB_TX_CTRL_ADDRESS 0x0000a204
-#define PHY_BB_BBB_TX_CTRL_OFFSET 0x0000a204
-#define PHY_BB_BBB_TX_CTRL_DISABLE_SCRAMBLER_MSB 0
-#define PHY_BB_BBB_TX_CTRL_DISABLE_SCRAMBLER_LSB 0
-#define PHY_BB_BBB_TX_CTRL_DISABLE_SCRAMBLER_MASK 0x00000001
-#define PHY_BB_BBB_TX_CTRL_DISABLE_SCRAMBLER_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_BB_BBB_TX_CTRL_DISABLE_SCRAMBLER_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_BB_BBB_TX_CTRL_USE_SCRAMBLER_SEED_MSB 1
-#define PHY_BB_BBB_TX_CTRL_USE_SCRAMBLER_SEED_LSB 1
-#define PHY_BB_BBB_TX_CTRL_USE_SCRAMBLER_SEED_MASK 0x00000002
-#define PHY_BB_BBB_TX_CTRL_USE_SCRAMBLER_SEED_GET(x) (((x) & 0x00000002) >> 1)
-#define PHY_BB_BBB_TX_CTRL_USE_SCRAMBLER_SEED_SET(x) (((x) << 1) & 0x00000002)
-#define PHY_BB_BBB_TX_CTRL_TX_DAC_SCALE_CCK_MSB 3
-#define PHY_BB_BBB_TX_CTRL_TX_DAC_SCALE_CCK_LSB 2
-#define PHY_BB_BBB_TX_CTRL_TX_DAC_SCALE_CCK_MASK 0x0000000c
-#define PHY_BB_BBB_TX_CTRL_TX_DAC_SCALE_CCK_GET(x) (((x) & 0x0000000c) >> 2)
-#define PHY_BB_BBB_TX_CTRL_TX_DAC_SCALE_CCK_SET(x) (((x) << 2) & 0x0000000c)
-#define PHY_BB_BBB_TX_CTRL_TXFIR_JAPAN_CCK_MSB 4
-#define PHY_BB_BBB_TX_CTRL_TXFIR_JAPAN_CCK_LSB 4
-#define PHY_BB_BBB_TX_CTRL_TXFIR_JAPAN_CCK_MASK 0x00000010
-#define PHY_BB_BBB_TX_CTRL_TXFIR_JAPAN_CCK_GET(x) (((x) & 0x00000010) >> 4)
-#define PHY_BB_BBB_TX_CTRL_TXFIR_JAPAN_CCK_SET(x) (((x) << 4) & 0x00000010)
-#define PHY_BB_BBB_TX_CTRL_ALLOW_1MBPS_SHORT_MSB 5
-#define PHY_BB_BBB_TX_CTRL_ALLOW_1MBPS_SHORT_LSB 5
-#define PHY_BB_BBB_TX_CTRL_ALLOW_1MBPS_SHORT_MASK 0x00000020
-#define PHY_BB_BBB_TX_CTRL_ALLOW_1MBPS_SHORT_GET(x) (((x) & 0x00000020) >> 5)
-#define PHY_BB_BBB_TX_CTRL_ALLOW_1MBPS_SHORT_SET(x) (((x) << 5) & 0x00000020)
-#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_1_MSB 8
-#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_1_LSB 6
-#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_1_MASK 0x000001c0
-#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_1_GET(x) (((x) & 0x000001c0) >> 6)
-#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_1_SET(x) (((x) << 6) & 0x000001c0)
-#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_2_MSB 11
-#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_2_LSB 9
-#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_2_MASK 0x00000e00
-#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_2_GET(x) (((x) & 0x00000e00) >> 9)
-#define PHY_BB_BBB_TX_CTRL_TX_CCK_DELAY_2_SET(x) (((x) << 9) & 0x00000e00)
-
-/* macros for BB_bbb_sig_detect */
-#define PHY_BB_BBB_SIG_DETECT_ADDRESS 0x0000a208
-#define PHY_BB_BBB_SIG_DETECT_OFFSET 0x0000a208
-#define PHY_BB_BBB_SIG_DETECT_WEAK_SIG_THR_CCK_MSB 5
-#define PHY_BB_BBB_SIG_DETECT_WEAK_SIG_THR_CCK_LSB 0
-#define PHY_BB_BBB_SIG_DETECT_WEAK_SIG_THR_CCK_MASK 0x0000003f
-#define PHY_BB_BBB_SIG_DETECT_WEAK_SIG_THR_CCK_GET(x) (((x) & 0x0000003f) >> 0)
-#define PHY_BB_BBB_SIG_DETECT_WEAK_SIG_THR_CCK_SET(x) (((x) << 0) & 0x0000003f)
-#define PHY_BB_BBB_SIG_DETECT_ANT_SWITCH_TIME_MSB 12
-#define PHY_BB_BBB_SIG_DETECT_ANT_SWITCH_TIME_LSB 6
-#define PHY_BB_BBB_SIG_DETECT_ANT_SWITCH_TIME_MASK 0x00001fc0
-#define PHY_BB_BBB_SIG_DETECT_ANT_SWITCH_TIME_GET(x) (((x) & 0x00001fc0) >> 6)
-#define PHY_BB_BBB_SIG_DETECT_ANT_SWITCH_TIME_SET(x) (((x) << 6) & 0x00001fc0)
-#define PHY_BB_BBB_SIG_DETECT_ENABLE_ANT_FAST_DIV_MSB 13
-#define PHY_BB_BBB_SIG_DETECT_ENABLE_ANT_FAST_DIV_LSB 13
-#define PHY_BB_BBB_SIG_DETECT_ENABLE_ANT_FAST_DIV_MASK 0x00002000
-#define PHY_BB_BBB_SIG_DETECT_ENABLE_ANT_FAST_DIV_GET(x) (((x) & 0x00002000) >> 13)
-#define PHY_BB_BBB_SIG_DETECT_ENABLE_ANT_FAST_DIV_SET(x) (((x) << 13) & 0x00002000)
-#define PHY_BB_BBB_SIG_DETECT_LB_ALPHA_128_CCK_MSB 14
-#define PHY_BB_BBB_SIG_DETECT_LB_ALPHA_128_CCK_LSB 14
-#define PHY_BB_BBB_SIG_DETECT_LB_ALPHA_128_CCK_MASK 0x00004000
-#define PHY_BB_BBB_SIG_DETECT_LB_ALPHA_128_CCK_GET(x) (((x) & 0x00004000) >> 14)
-#define PHY_BB_BBB_SIG_DETECT_LB_ALPHA_128_CCK_SET(x) (((x) << 14) & 0x00004000)
-#define PHY_BB_BBB_SIG_DETECT_LB_RX_ENABLE_CCK_MSB 15
-#define PHY_BB_BBB_SIG_DETECT_LB_RX_ENABLE_CCK_LSB 15
-#define PHY_BB_BBB_SIG_DETECT_LB_RX_ENABLE_CCK_MASK 0x00008000
-#define PHY_BB_BBB_SIG_DETECT_LB_RX_ENABLE_CCK_GET(x) (((x) & 0x00008000) >> 15)
-#define PHY_BB_BBB_SIG_DETECT_LB_RX_ENABLE_CCK_SET(x) (((x) << 15) & 0x00008000)
-#define PHY_BB_BBB_SIG_DETECT_CYC32_COARSE_DC_EST_CCK_MSB 16
-#define PHY_BB_BBB_SIG_DETECT_CYC32_COARSE_DC_EST_CCK_LSB 16
-#define PHY_BB_BBB_SIG_DETECT_CYC32_COARSE_DC_EST_CCK_MASK 0x00010000
-#define PHY_BB_BBB_SIG_DETECT_CYC32_COARSE_DC_EST_CCK_GET(x) (((x) & 0x00010000) >> 16)
-#define PHY_BB_BBB_SIG_DETECT_CYC32_COARSE_DC_EST_CCK_SET(x) (((x) << 16) & 0x00010000)
-#define PHY_BB_BBB_SIG_DETECT_CYC64_COARSE_DC_EST_CCK_MSB 17
-#define PHY_BB_BBB_SIG_DETECT_CYC64_COARSE_DC_EST_CCK_LSB 17
-#define PHY_BB_BBB_SIG_DETECT_CYC64_COARSE_DC_EST_CCK_MASK 0x00020000
-#define PHY_BB_BBB_SIG_DETECT_CYC64_COARSE_DC_EST_CCK_GET(x) (((x) & 0x00020000) >> 17)
-#define PHY_BB_BBB_SIG_DETECT_CYC64_COARSE_DC_EST_CCK_SET(x) (((x) << 17) & 0x00020000)
-#define PHY_BB_BBB_SIG_DETECT_ENABLE_COARSE_DC_CCK_MSB 18
-#define PHY_BB_BBB_SIG_DETECT_ENABLE_COARSE_DC_CCK_LSB 18
-#define PHY_BB_BBB_SIG_DETECT_ENABLE_COARSE_DC_CCK_MASK 0x00040000
-#define PHY_BB_BBB_SIG_DETECT_ENABLE_COARSE_DC_CCK_GET(x) (((x) & 0x00040000) >> 18)
-#define PHY_BB_BBB_SIG_DETECT_ENABLE_COARSE_DC_CCK_SET(x) (((x) << 18) & 0x00040000)
-#define PHY_BB_BBB_SIG_DETECT_CYC256_FINE_DC_EST_CCK_MSB 19
-#define PHY_BB_BBB_SIG_DETECT_CYC256_FINE_DC_EST_CCK_LSB 19
-#define PHY_BB_BBB_SIG_DETECT_CYC256_FINE_DC_EST_CCK_MASK 0x00080000
-#define PHY_BB_BBB_SIG_DETECT_CYC256_FINE_DC_EST_CCK_GET(x) (((x) & 0x00080000) >> 19)
-#define PHY_BB_BBB_SIG_DETECT_CYC256_FINE_DC_EST_CCK_SET(x) (((x) << 19) & 0x00080000)
-#define PHY_BB_BBB_SIG_DETECT_ENABLE_FINE_DC_CCK_MSB 20
-#define PHY_BB_BBB_SIG_DETECT_ENABLE_FINE_DC_CCK_LSB 20
-#define PHY_BB_BBB_SIG_DETECT_ENABLE_FINE_DC_CCK_MASK 0x00100000
-#define PHY_BB_BBB_SIG_DETECT_ENABLE_FINE_DC_CCK_GET(x) (((x) & 0x00100000) >> 20)
-#define PHY_BB_BBB_SIG_DETECT_ENABLE_FINE_DC_CCK_SET(x) (((x) << 20) & 0x00100000)
-#define PHY_BB_BBB_SIG_DETECT_DELAY_START_SYNC_CCK_MSB 21
-#define PHY_BB_BBB_SIG_DETECT_DELAY_START_SYNC_CCK_LSB 21
-#define PHY_BB_BBB_SIG_DETECT_DELAY_START_SYNC_CCK_MASK 0x00200000
-#define PHY_BB_BBB_SIG_DETECT_DELAY_START_SYNC_CCK_GET(x) (((x) & 0x00200000) >> 21)
-#define PHY_BB_BBB_SIG_DETECT_DELAY_START_SYNC_CCK_SET(x) (((x) << 21) & 0x00200000)
-#define PHY_BB_BBB_SIG_DETECT_USE_DC_EST_DURING_SRCH_MSB 22
-#define PHY_BB_BBB_SIG_DETECT_USE_DC_EST_DURING_SRCH_LSB 22
-#define PHY_BB_BBB_SIG_DETECT_USE_DC_EST_DURING_SRCH_MASK 0x00400000
-#define PHY_BB_BBB_SIG_DETECT_USE_DC_EST_DURING_SRCH_GET(x) (((x) & 0x00400000) >> 22)
-#define PHY_BB_BBB_SIG_DETECT_USE_DC_EST_DURING_SRCH_SET(x) (((x) << 22) & 0x00400000)
-#define PHY_BB_BBB_SIG_DETECT_ENABLE_BARKER_TWO_PHASE_MSB 31
-#define PHY_BB_BBB_SIG_DETECT_ENABLE_BARKER_TWO_PHASE_LSB 31
-#define PHY_BB_BBB_SIG_DETECT_ENABLE_BARKER_TWO_PHASE_MASK 0x80000000
-#define PHY_BB_BBB_SIG_DETECT_ENABLE_BARKER_TWO_PHASE_GET(x) (((x) & 0x80000000) >> 31)
-#define PHY_BB_BBB_SIG_DETECT_ENABLE_BARKER_TWO_PHASE_SET(x) (((x) << 31) & 0x80000000)
-
-/* macros for BB_ext_atten_switch_ctl_b0 */
-#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_ADDRESS 0x0000a20c
-#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_OFFSET 0x0000a20c
-#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_DB_0_MSB 5
-#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_DB_0_LSB 0
-#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_DB_0_MASK 0x0000003f
-#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_DB_0_GET(x) (((x) & 0x0000003f) >> 0)
-#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_DB_0_SET(x) (((x) << 0) & 0x0000003f)
-#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_DB_0_MSB 11
-#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_DB_0_LSB 6
-#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_DB_0_MASK 0x00000fc0
-#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_DB_0_GET(x) (((x) & 0x00000fc0) >> 6)
-#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_DB_0_SET(x) (((x) << 6) & 0x00000fc0)
-#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_MARGIN_0_MSB 16
-#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_MARGIN_0_LSB 12
-#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_MARGIN_0_MASK 0x0001f000
-#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_MARGIN_0_GET(x) (((x) & 0x0001f000) >> 12)
-#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN1_MARGIN_0_SET(x) (((x) << 12) & 0x0001f000)
-#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_MARGIN_0_MSB 21
-#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_MARGIN_0_LSB 17
-#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_MARGIN_0_MASK 0x003e0000
-#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_MARGIN_0_GET(x) (((x) & 0x003e0000) >> 17)
-#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B0_XATTEN2_MARGIN_0_SET(x) (((x) << 17) & 0x003e0000)
-
-/* macros for BB_bbb_rx_ctrl_1 */
-#define PHY_BB_BBB_RX_CTRL_1_ADDRESS 0x0000a210
-#define PHY_BB_BBB_RX_CTRL_1_OFFSET 0x0000a210
-#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_2_MSB 2
-#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_2_LSB 0
-#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_2_MASK 0x00000007
-#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_2_GET(x) (((x) & 0x00000007) >> 0)
-#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_2_SET(x) (((x) << 0) & 0x00000007)
-#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_MSB 7
-#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_LSB 3
-#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_MASK 0x000000f8
-#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_GET(x) (((x) & 0x000000f8) >> 3)
-#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_THRESHOLD_SET(x) (((x) << 3) & 0x000000f8)
-#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_N_SYNC_MSB 10
-#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_N_SYNC_LSB 8
-#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_N_SYNC_MASK 0x00000700
-#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_N_SYNC_GET(x) (((x) & 0x00000700) >> 8)
-#define PHY_BB_BBB_RX_CTRL_1_COARSE_TIM_N_SYNC_SET(x) (((x) << 8) & 0x00000700)
-#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_LONG_MSB 15
-#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_LONG_LSB 11
-#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_LONG_MASK 0x0000f800
-#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_LONG_GET(x) (((x) & 0x0000f800) >> 11)
-#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_LONG_SET(x) (((x) << 11) & 0x0000f800)
-#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_SHORT_MSB 20
-#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_SHORT_LSB 16
-#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_SHORT_MASK 0x001f0000
-#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_SHORT_GET(x) (((x) & 0x001f0000) >> 16)
-#define PHY_BB_BBB_RX_CTRL_1_MAX_BAL_SHORT_SET(x) (((x) << 16) & 0x001f0000)
-#define PHY_BB_BBB_RX_CTRL_1_RECON_LMS_STEP_MSB 23
-#define PHY_BB_BBB_RX_CTRL_1_RECON_LMS_STEP_LSB 21
-#define PHY_BB_BBB_RX_CTRL_1_RECON_LMS_STEP_MASK 0x00e00000
-#define PHY_BB_BBB_RX_CTRL_1_RECON_LMS_STEP_GET(x) (((x) & 0x00e00000) >> 21)
-#define PHY_BB_BBB_RX_CTRL_1_RECON_LMS_STEP_SET(x) (((x) << 21) & 0x00e00000)
-#define PHY_BB_BBB_RX_CTRL_1_SB_CHECK_WIN_MSB 30
-#define PHY_BB_BBB_RX_CTRL_1_SB_CHECK_WIN_LSB 24
-#define PHY_BB_BBB_RX_CTRL_1_SB_CHECK_WIN_MASK 0x7f000000
-#define PHY_BB_BBB_RX_CTRL_1_SB_CHECK_WIN_GET(x) (((x) & 0x7f000000) >> 24)
-#define PHY_BB_BBB_RX_CTRL_1_SB_CHECK_WIN_SET(x) (((x) << 24) & 0x7f000000)
-#define PHY_BB_BBB_RX_CTRL_1_EN_RX_ABORT_CCK_MSB 31
-#define PHY_BB_BBB_RX_CTRL_1_EN_RX_ABORT_CCK_LSB 31
-#define PHY_BB_BBB_RX_CTRL_1_EN_RX_ABORT_CCK_MASK 0x80000000
-#define PHY_BB_BBB_RX_CTRL_1_EN_RX_ABORT_CCK_GET(x) (((x) & 0x80000000) >> 31)
-#define PHY_BB_BBB_RX_CTRL_1_EN_RX_ABORT_CCK_SET(x) (((x) << 31) & 0x80000000)
-
-/* macros for BB_bbb_rx_ctrl_2 */
-#define PHY_BB_BBB_RX_CTRL_2_ADDRESS 0x0000a214
-#define PHY_BB_BBB_RX_CTRL_2_OFFSET 0x0000a214
-#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_N_AVG_LONG_MSB 5
-#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_N_AVG_LONG_LSB 0
-#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_N_AVG_LONG_MASK 0x0000003f
-#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_N_AVG_LONG_GET(x) (((x) & 0x0000003f) >> 0)
-#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_N_AVG_LONG_SET(x) (((x) << 0) & 0x0000003f)
-#define PHY_BB_BBB_RX_CTRL_2_CHAN_AVG_LONG_MSB 11
-#define PHY_BB_BBB_RX_CTRL_2_CHAN_AVG_LONG_LSB 6
-#define PHY_BB_BBB_RX_CTRL_2_CHAN_AVG_LONG_MASK 0x00000fc0
-#define PHY_BB_BBB_RX_CTRL_2_CHAN_AVG_LONG_GET(x) (((x) & 0x00000fc0) >> 6)
-#define PHY_BB_BBB_RX_CTRL_2_CHAN_AVG_LONG_SET(x) (((x) << 6) & 0x00000fc0)
-#define PHY_BB_BBB_RX_CTRL_2_COARSE_TIM_THRESHOLD_3_MSB 16
-#define PHY_BB_BBB_RX_CTRL_2_COARSE_TIM_THRESHOLD_3_LSB 12
-#define PHY_BB_BBB_RX_CTRL_2_COARSE_TIM_THRESHOLD_3_MASK 0x0001f000
-#define PHY_BB_BBB_RX_CTRL_2_COARSE_TIM_THRESHOLD_3_GET(x) (((x) & 0x0001f000) >> 12)
-#define PHY_BB_BBB_RX_CTRL_2_COARSE_TIM_THRESHOLD_3_SET(x) (((x) << 12) & 0x0001f000)
-#define PHY_BB_BBB_RX_CTRL_2_FREQ_TRACK_UPDATE_PERIOD_MSB 21
-#define PHY_BB_BBB_RX_CTRL_2_FREQ_TRACK_UPDATE_PERIOD_LSB 17
-#define PHY_BB_BBB_RX_CTRL_2_FREQ_TRACK_UPDATE_PERIOD_MASK 0x003e0000
-#define PHY_BB_BBB_RX_CTRL_2_FREQ_TRACK_UPDATE_PERIOD_GET(x) (((x) & 0x003e0000) >> 17)
-#define PHY_BB_BBB_RX_CTRL_2_FREQ_TRACK_UPDATE_PERIOD_SET(x) (((x) << 17) & 0x003e0000)
-#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_SCALING_PERIOD_MSB 25
-#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_SCALING_PERIOD_LSB 22
-#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_SCALING_PERIOD_MASK 0x03c00000
-#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_SCALING_PERIOD_GET(x) (((x) & 0x03c00000) >> 22)
-#define PHY_BB_BBB_RX_CTRL_2_FREQ_EST_SCALING_PERIOD_SET(x) (((x) << 22) & 0x03c00000)
-#define PHY_BB_BBB_RX_CTRL_2_LOOP_COEF_DPSK_C2_DATA_MSB 31
-#define PHY_BB_BBB_RX_CTRL_2_LOOP_COEF_DPSK_C2_DATA_LSB 26
-#define PHY_BB_BBB_RX_CTRL_2_LOOP_COEF_DPSK_C2_DATA_MASK 0xfc000000
-#define PHY_BB_BBB_RX_CTRL_2_LOOP_COEF_DPSK_C2_DATA_GET(x) (((x) & 0xfc000000) >> 26)
-#define PHY_BB_BBB_RX_CTRL_2_LOOP_COEF_DPSK_C2_DATA_SET(x) (((x) << 26) & 0xfc000000)
-
-/* macros for BB_bbb_rx_ctrl_3 */
-#define PHY_BB_BBB_RX_CTRL_3_ADDRESS 0x0000a218
-#define PHY_BB_BBB_RX_CTRL_3_OFFSET 0x0000a218
-#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_DPSK_MSB 7
-#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_DPSK_LSB 0
-#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_DPSK_MASK 0x000000ff
-#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_DPSK_GET(x) (((x) & 0x000000ff) >> 0)
-#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_DPSK_SET(x) (((x) << 0) & 0x000000ff)
-#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_CCK_MSB 15
-#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_CCK_LSB 8
-#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_CCK_MASK 0x0000ff00
-#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_CCK_GET(x) (((x) & 0x0000ff00) >> 8)
-#define PHY_BB_BBB_RX_CTRL_3_TIM_ADJUST_FREQ_CCK_SET(x) (((x) << 8) & 0x0000ff00)
-#define PHY_BB_BBB_RX_CTRL_3_TIMER_N_SFD_MSB 23
-#define PHY_BB_BBB_RX_CTRL_3_TIMER_N_SFD_LSB 16
-#define PHY_BB_BBB_RX_CTRL_3_TIMER_N_SFD_MASK 0x00ff0000
-#define PHY_BB_BBB_RX_CTRL_3_TIMER_N_SFD_GET(x) (((x) & 0x00ff0000) >> 16)
-#define PHY_BB_BBB_RX_CTRL_3_TIMER_N_SFD_SET(x) (((x) << 16) & 0x00ff0000)
-
-/* macros for BB_bbb_rx_ctrl_4 */
-#define PHY_BB_BBB_RX_CTRL_4_ADDRESS 0x0000a21c
-#define PHY_BB_BBB_RX_CTRL_4_OFFSET 0x0000a21c
-#define PHY_BB_BBB_RX_CTRL_4_TIMER_N_SYNC_MSB 3
-#define PHY_BB_BBB_RX_CTRL_4_TIMER_N_SYNC_LSB 0
-#define PHY_BB_BBB_RX_CTRL_4_TIMER_N_SYNC_MASK 0x0000000f
-#define PHY_BB_BBB_RX_CTRL_4_TIMER_N_SYNC_GET(x) (((x) & 0x0000000f) >> 0)
-#define PHY_BB_BBB_RX_CTRL_4_TIMER_N_SYNC_SET(x) (((x) << 0) & 0x0000000f)
-#define PHY_BB_BBB_RX_CTRL_4_TIM_ADJUST_TIMER_EXP_MSB 15
-#define PHY_BB_BBB_RX_CTRL_4_TIM_ADJUST_TIMER_EXP_LSB 4
-#define PHY_BB_BBB_RX_CTRL_4_TIM_ADJUST_TIMER_EXP_MASK 0x0000fff0
-#define PHY_BB_BBB_RX_CTRL_4_TIM_ADJUST_TIMER_EXP_GET(x) (((x) & 0x0000fff0) >> 4)
-#define PHY_BB_BBB_RX_CTRL_4_TIM_ADJUST_TIMER_EXP_SET(x) (((x) << 4) & 0x0000fff0)
-#define PHY_BB_BBB_RX_CTRL_4_FORCE_UNLOCKED_CLOCKS_MSB 16
-#define PHY_BB_BBB_RX_CTRL_4_FORCE_UNLOCKED_CLOCKS_LSB 16
-#define PHY_BB_BBB_RX_CTRL_4_FORCE_UNLOCKED_CLOCKS_MASK 0x00010000
-#define PHY_BB_BBB_RX_CTRL_4_FORCE_UNLOCKED_CLOCKS_GET(x) (((x) & 0x00010000) >> 16)
-#define PHY_BB_BBB_RX_CTRL_4_FORCE_UNLOCKED_CLOCKS_SET(x) (((x) << 16) & 0x00010000)
-#define PHY_BB_BBB_RX_CTRL_4_DYNAMIC_PREAM_SEL_MSB 17
-#define PHY_BB_BBB_RX_CTRL_4_DYNAMIC_PREAM_SEL_LSB 17
-#define PHY_BB_BBB_RX_CTRL_4_DYNAMIC_PREAM_SEL_MASK 0x00020000
-#define PHY_BB_BBB_RX_CTRL_4_DYNAMIC_PREAM_SEL_GET(x) (((x) & 0x00020000) >> 17)
-#define PHY_BB_BBB_RX_CTRL_4_DYNAMIC_PREAM_SEL_SET(x) (((x) << 17) & 0x00020000)
-#define PHY_BB_BBB_RX_CTRL_4_SHORT_PREAMBLE_MSB 18
-#define PHY_BB_BBB_RX_CTRL_4_SHORT_PREAMBLE_LSB 18
-#define PHY_BB_BBB_RX_CTRL_4_SHORT_PREAMBLE_MASK 0x00040000
-#define PHY_BB_BBB_RX_CTRL_4_SHORT_PREAMBLE_GET(x) (((x) & 0x00040000) >> 18)
-#define PHY_BB_BBB_RX_CTRL_4_SHORT_PREAMBLE_SET(x) (((x) << 18) & 0x00040000)
-#define PHY_BB_BBB_RX_CTRL_4_FREQ_EST_N_AVG_SHORT_MSB 24
-#define PHY_BB_BBB_RX_CTRL_4_FREQ_EST_N_AVG_SHORT_LSB 19
-#define PHY_BB_BBB_RX_CTRL_4_FREQ_EST_N_AVG_SHORT_MASK 0x01f80000
-#define PHY_BB_BBB_RX_CTRL_4_FREQ_EST_N_AVG_SHORT_GET(x) (((x) & 0x01f80000) >> 19)
-#define PHY_BB_BBB_RX_CTRL_4_FREQ_EST_N_AVG_SHORT_SET(x) (((x) << 19) & 0x01f80000)
-#define PHY_BB_BBB_RX_CTRL_4_CHAN_AVG_SHORT_MSB 30
-#define PHY_BB_BBB_RX_CTRL_4_CHAN_AVG_SHORT_LSB 25
-#define PHY_BB_BBB_RX_CTRL_4_CHAN_AVG_SHORT_MASK 0x7e000000
-#define PHY_BB_BBB_RX_CTRL_4_CHAN_AVG_SHORT_GET(x) (((x) & 0x7e000000) >> 25)
-#define PHY_BB_BBB_RX_CTRL_4_CHAN_AVG_SHORT_SET(x) (((x) << 25) & 0x7e000000)
-
-/* macros for BB_bbb_rx_ctrl_5 */
-#define PHY_BB_BBB_RX_CTRL_5_ADDRESS 0x0000a220
-#define PHY_BB_BBB_RX_CTRL_5_OFFSET 0x0000a220
-#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_DATA_MSB 4
-#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_DATA_LSB 0
-#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_DATA_MASK 0x0000001f
-#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_DATA_GET(x) (((x) & 0x0000001f) >> 0)
-#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_DATA_SET(x) (((x) << 0) & 0x0000001f)
-#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_HEAD_MSB 9
-#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_HEAD_LSB 5
-#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_HEAD_MASK 0x000003e0
-#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_HEAD_GET(x) (((x) & 0x000003e0) >> 5)
-#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C1_HEAD_SET(x) (((x) << 5) & 0x000003e0)
-#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C2_HEAD_MSB 15
-#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C2_HEAD_LSB 10
-#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C2_HEAD_MASK 0x0000fc00
-#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C2_HEAD_GET(x) (((x) & 0x0000fc00) >> 10)
-#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_DPSK_C2_HEAD_SET(x) (((x) << 10) & 0x0000fc00)
-#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C1_MSB 20
-#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C1_LSB 16
-#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C1_MASK 0x001f0000
-#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C1_GET(x) (((x) & 0x001f0000) >> 16)
-#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C1_SET(x) (((x) << 16) & 0x001f0000)
-#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C2_MSB 26
-#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C2_LSB 21
-#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C2_MASK 0x07e00000
-#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C2_GET(x) (((x) & 0x07e00000) >> 21)
-#define PHY_BB_BBB_RX_CTRL_5_LOOP_COEF_CCK_C2_SET(x) (((x) << 21) & 0x07e00000)
-
-/* macros for BB_bbb_rx_ctrl_6 */
-#define PHY_BB_BBB_RX_CTRL_6_ADDRESS 0x0000a224
-#define PHY_BB_BBB_RX_CTRL_6_OFFSET 0x0000a224
-#define PHY_BB_BBB_RX_CTRL_6_SYNC_START_DELAY_MSB 9
-#define PHY_BB_BBB_RX_CTRL_6_SYNC_START_DELAY_LSB 0
-#define PHY_BB_BBB_RX_CTRL_6_SYNC_START_DELAY_MASK 0x000003ff
-#define PHY_BB_BBB_RX_CTRL_6_SYNC_START_DELAY_GET(x) (((x) & 0x000003ff) >> 0)
-#define PHY_BB_BBB_RX_CTRL_6_SYNC_START_DELAY_SET(x) (((x) << 0) & 0x000003ff)
-#define PHY_BB_BBB_RX_CTRL_6_MAP_1S_TO_2S_MSB 10
-#define PHY_BB_BBB_RX_CTRL_6_MAP_1S_TO_2S_LSB 10
-#define PHY_BB_BBB_RX_CTRL_6_MAP_1S_TO_2S_MASK 0x00000400
-#define PHY_BB_BBB_RX_CTRL_6_MAP_1S_TO_2S_GET(x) (((x) & 0x00000400) >> 10)
-#define PHY_BB_BBB_RX_CTRL_6_MAP_1S_TO_2S_SET(x) (((x) << 10) & 0x00000400)
-#define PHY_BB_BBB_RX_CTRL_6_START_IIR_DELAY_MSB 20
-#define PHY_BB_BBB_RX_CTRL_6_START_IIR_DELAY_LSB 11
-#define PHY_BB_BBB_RX_CTRL_6_START_IIR_DELAY_MASK 0x001ff800
-#define PHY_BB_BBB_RX_CTRL_6_START_IIR_DELAY_GET(x) (((x) & 0x001ff800) >> 11)
-#define PHY_BB_BBB_RX_CTRL_6_START_IIR_DELAY_SET(x) (((x) << 11) & 0x001ff800)
-
-/* macros for BB_bbb_dagc_ctrl */
-#define PHY_BB_BBB_DAGC_CTRL_ADDRESS 0x0000a228
-#define PHY_BB_BBB_DAGC_CTRL_OFFSET 0x0000a228
-#define PHY_BB_BBB_DAGC_CTRL_ENABLE_DAGC_CCK_MSB 0
-#define PHY_BB_BBB_DAGC_CTRL_ENABLE_DAGC_CCK_LSB 0
-#define PHY_BB_BBB_DAGC_CTRL_ENABLE_DAGC_CCK_MASK 0x00000001
-#define PHY_BB_BBB_DAGC_CTRL_ENABLE_DAGC_CCK_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_BB_BBB_DAGC_CTRL_ENABLE_DAGC_CCK_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_BB_BBB_DAGC_CTRL_DAGC_TARGET_PWR_CCK_MSB 8
-#define PHY_BB_BBB_DAGC_CTRL_DAGC_TARGET_PWR_CCK_LSB 1
-#define PHY_BB_BBB_DAGC_CTRL_DAGC_TARGET_PWR_CCK_MASK 0x000001fe
-#define PHY_BB_BBB_DAGC_CTRL_DAGC_TARGET_PWR_CCK_GET(x) (((x) & 0x000001fe) >> 1)
-#define PHY_BB_BBB_DAGC_CTRL_DAGC_TARGET_PWR_CCK_SET(x) (((x) << 1) & 0x000001fe)
-#define PHY_BB_BBB_DAGC_CTRL_ENABLE_BARKER_RSSI_THR_MSB 9
-#define PHY_BB_BBB_DAGC_CTRL_ENABLE_BARKER_RSSI_THR_LSB 9
-#define PHY_BB_BBB_DAGC_CTRL_ENABLE_BARKER_RSSI_THR_MASK 0x00000200
-#define PHY_BB_BBB_DAGC_CTRL_ENABLE_BARKER_RSSI_THR_GET(x) (((x) & 0x00000200) >> 9)
-#define PHY_BB_BBB_DAGC_CTRL_ENABLE_BARKER_RSSI_THR_SET(x) (((x) << 9) & 0x00000200)
-#define PHY_BB_BBB_DAGC_CTRL_BARKER_RSSI_THR_MSB 16
-#define PHY_BB_BBB_DAGC_CTRL_BARKER_RSSI_THR_LSB 10
-#define PHY_BB_BBB_DAGC_CTRL_BARKER_RSSI_THR_MASK 0x0001fc00
-#define PHY_BB_BBB_DAGC_CTRL_BARKER_RSSI_THR_GET(x) (((x) & 0x0001fc00) >> 10)
-#define PHY_BB_BBB_DAGC_CTRL_BARKER_RSSI_THR_SET(x) (((x) << 10) & 0x0001fc00)
-#define PHY_BB_BBB_DAGC_CTRL_ENABLE_FIRSTEP_SEL_MSB 17
-#define PHY_BB_BBB_DAGC_CTRL_ENABLE_FIRSTEP_SEL_LSB 17
-#define PHY_BB_BBB_DAGC_CTRL_ENABLE_FIRSTEP_SEL_MASK 0x00020000
-#define PHY_BB_BBB_DAGC_CTRL_ENABLE_FIRSTEP_SEL_GET(x) (((x) & 0x00020000) >> 17)
-#define PHY_BB_BBB_DAGC_CTRL_ENABLE_FIRSTEP_SEL_SET(x) (((x) << 17) & 0x00020000)
-#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_2_MSB 23
-#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_2_LSB 18
-#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_2_MASK 0x00fc0000
-#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_2_GET(x) (((x) & 0x00fc0000) >> 18)
-#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_2_SET(x) (((x) << 18) & 0x00fc0000)
-#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_COUNT_LGMAX_MSB 27
-#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_COUNT_LGMAX_LSB 24
-#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_COUNT_LGMAX_MASK 0x0f000000
-#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_COUNT_LGMAX_GET(x) (((x) & 0x0f000000) >> 24)
-#define PHY_BB_BBB_DAGC_CTRL_FIRSTEP_COUNT_LGMAX_SET(x) (((x) << 24) & 0x0f000000)
-
-/* macros for BB_force_clken_cck */
-#define PHY_BB_FORCE_CLKEN_CCK_ADDRESS 0x0000a22c
-#define PHY_BB_FORCE_CLKEN_CCK_OFFSET 0x0000a22c
-#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE0_MSB 0
-#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE0_LSB 0
-#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE0_MASK 0x00000001
-#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE0_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE0_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE1_MSB 1
-#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE1_LSB 1
-#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE1_MASK 0x00000002
-#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE1_GET(x) (((x) & 0x00000002) >> 1)
-#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE1_SET(x) (((x) << 1) & 0x00000002)
-#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE2_MSB 2
-#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE2_LSB 2
-#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE2_MASK 0x00000004
-#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE2_GET(x) (((x) & 0x00000004) >> 2)
-#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE2_SET(x) (((x) << 2) & 0x00000004)
-#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE3_MSB 3
-#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE3_LSB 3
-#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE3_MASK 0x00000008
-#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE3_GET(x) (((x) & 0x00000008) >> 3)
-#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ENABLE3_SET(x) (((x) << 3) & 0x00000008)
-#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ALWAYS_MSB 4
-#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ALWAYS_LSB 4
-#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ALWAYS_MASK 0x00000010
-#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ALWAYS_GET(x) (((x) & 0x00000010) >> 4)
-#define PHY_BB_FORCE_CLKEN_CCK_FORCE_RX_ALWAYS_SET(x) (((x) << 4) & 0x00000010)
-#define PHY_BB_FORCE_CLKEN_CCK_FORCE_TXSM_CLKEN_MSB 5
-#define PHY_BB_FORCE_CLKEN_CCK_FORCE_TXSM_CLKEN_LSB 5
-#define PHY_BB_FORCE_CLKEN_CCK_FORCE_TXSM_CLKEN_MASK 0x00000020
-#define PHY_BB_FORCE_CLKEN_CCK_FORCE_TXSM_CLKEN_GET(x) (((x) & 0x00000020) >> 5)
-#define PHY_BB_FORCE_CLKEN_CCK_FORCE_TXSM_CLKEN_SET(x) (((x) << 5) & 0x00000020)
-
-/* macros for BB_rx_clear_delay */
-#define PHY_BB_RX_CLEAR_DELAY_ADDRESS 0x0000a230
-#define PHY_BB_RX_CLEAR_DELAY_OFFSET 0x0000a230
-#define PHY_BB_RX_CLEAR_DELAY_OFDM_XR_RX_CLEAR_DELAY_MSB 9
-#define PHY_BB_RX_CLEAR_DELAY_OFDM_XR_RX_CLEAR_DELAY_LSB 0
-#define PHY_BB_RX_CLEAR_DELAY_OFDM_XR_RX_CLEAR_DELAY_MASK 0x000003ff
-#define PHY_BB_RX_CLEAR_DELAY_OFDM_XR_RX_CLEAR_DELAY_GET(x) (((x) & 0x000003ff) >> 0)
-#define PHY_BB_RX_CLEAR_DELAY_OFDM_XR_RX_CLEAR_DELAY_SET(x) (((x) << 0) & 0x000003ff)
-
-/* macros for BB_powertx_rate3 */
-#define PHY_BB_POWERTX_RATE3_ADDRESS 0x0000a234
-#define PHY_BB_POWERTX_RATE3_OFFSET 0x0000a234
-#define PHY_BB_POWERTX_RATE3_POWERTX_1L_MSB 5
-#define PHY_BB_POWERTX_RATE3_POWERTX_1L_LSB 0
-#define PHY_BB_POWERTX_RATE3_POWERTX_1L_MASK 0x0000003f
-#define PHY_BB_POWERTX_RATE3_POWERTX_1L_GET(x) (((x) & 0x0000003f) >> 0)
-#define PHY_BB_POWERTX_RATE3_POWERTX_1L_SET(x) (((x) << 0) & 0x0000003f)
-#define PHY_BB_POWERTX_RATE3_POWERTX_2L_MSB 21
-#define PHY_BB_POWERTX_RATE3_POWERTX_2L_LSB 16
-#define PHY_BB_POWERTX_RATE3_POWERTX_2L_MASK 0x003f0000
-#define PHY_BB_POWERTX_RATE3_POWERTX_2L_GET(x) (((x) & 0x003f0000) >> 16)
-#define PHY_BB_POWERTX_RATE3_POWERTX_2L_SET(x) (((x) << 16) & 0x003f0000)
-#define PHY_BB_POWERTX_RATE3_POWERTX_2S_MSB 29
-#define PHY_BB_POWERTX_RATE3_POWERTX_2S_LSB 24
-#define PHY_BB_POWERTX_RATE3_POWERTX_2S_MASK 0x3f000000
-#define PHY_BB_POWERTX_RATE3_POWERTX_2S_GET(x) (((x) & 0x3f000000) >> 24)
-#define PHY_BB_POWERTX_RATE3_POWERTX_2S_SET(x) (((x) << 24) & 0x3f000000)
-
-/* macros for BB_powertx_rate4 */
-#define PHY_BB_POWERTX_RATE4_ADDRESS 0x0000a238
-#define PHY_BB_POWERTX_RATE4_OFFSET 0x0000a238
-#define PHY_BB_POWERTX_RATE4_POWERTX_55L_MSB 5
-#define PHY_BB_POWERTX_RATE4_POWERTX_55L_LSB 0
-#define PHY_BB_POWERTX_RATE4_POWERTX_55L_MASK 0x0000003f
-#define PHY_BB_POWERTX_RATE4_POWERTX_55L_GET(x) (((x) & 0x0000003f) >> 0)
-#define PHY_BB_POWERTX_RATE4_POWERTX_55L_SET(x) (((x) << 0) & 0x0000003f)
-#define PHY_BB_POWERTX_RATE4_POWERTX_55S_MSB 13
-#define PHY_BB_POWERTX_RATE4_POWERTX_55S_LSB 8
-#define PHY_BB_POWERTX_RATE4_POWERTX_55S_MASK 0x00003f00
-#define PHY_BB_POWERTX_RATE4_POWERTX_55S_GET(x) (((x) & 0x00003f00) >> 8)
-#define PHY_BB_POWERTX_RATE4_POWERTX_55S_SET(x) (((x) << 8) & 0x00003f00)
-#define PHY_BB_POWERTX_RATE4_POWERTX_11L_MSB 21
-#define PHY_BB_POWERTX_RATE4_POWERTX_11L_LSB 16
-#define PHY_BB_POWERTX_RATE4_POWERTX_11L_MASK 0x003f0000
-#define PHY_BB_POWERTX_RATE4_POWERTX_11L_GET(x) (((x) & 0x003f0000) >> 16)
-#define PHY_BB_POWERTX_RATE4_POWERTX_11L_SET(x) (((x) << 16) & 0x003f0000)
-#define PHY_BB_POWERTX_RATE4_POWERTX_11S_MSB 29
-#define PHY_BB_POWERTX_RATE4_POWERTX_11S_LSB 24
-#define PHY_BB_POWERTX_RATE4_POWERTX_11S_MASK 0x3f000000
-#define PHY_BB_POWERTX_RATE4_POWERTX_11S_GET(x) (((x) & 0x3f000000) >> 24)
-#define PHY_BB_POWERTX_RATE4_POWERTX_11S_SET(x) (((x) << 24) & 0x3f000000)
-
-/* macros for BB_cck_spur_mit */
-#define PHY_BB_CCK_SPUR_MIT_ADDRESS 0x0000a240
-#define PHY_BB_CCK_SPUR_MIT_OFFSET 0x0000a240
-#define PHY_BB_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_MSB 0
-#define PHY_BB_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_LSB 0
-#define PHY_BB_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_MASK 0x00000001
-#define PHY_BB_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_BB_CCK_SPUR_MIT_USE_CCK_SPUR_MIT_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_BB_CCK_SPUR_MIT_SPUR_RSSI_THR_MSB 8
-#define PHY_BB_CCK_SPUR_MIT_SPUR_RSSI_THR_LSB 1
-#define PHY_BB_CCK_SPUR_MIT_SPUR_RSSI_THR_MASK 0x000001fe
-#define PHY_BB_CCK_SPUR_MIT_SPUR_RSSI_THR_GET(x) (((x) & 0x000001fe) >> 1)
-#define PHY_BB_CCK_SPUR_MIT_SPUR_RSSI_THR_SET(x) (((x) << 1) & 0x000001fe)
-#define PHY_BB_CCK_SPUR_MIT_CCK_SPUR_FREQ_MSB 28
-#define PHY_BB_CCK_SPUR_MIT_CCK_SPUR_FREQ_LSB 9
-#define PHY_BB_CCK_SPUR_MIT_CCK_SPUR_FREQ_MASK 0x1ffffe00
-#define PHY_BB_CCK_SPUR_MIT_CCK_SPUR_FREQ_GET(x) (((x) & 0x1ffffe00) >> 9)
-#define PHY_BB_CCK_SPUR_MIT_CCK_SPUR_FREQ_SET(x) (((x) << 9) & 0x1ffffe00)
-#define PHY_BB_CCK_SPUR_MIT_SPUR_FILTER_TYPE_MSB 30
-#define PHY_BB_CCK_SPUR_MIT_SPUR_FILTER_TYPE_LSB 29
-#define PHY_BB_CCK_SPUR_MIT_SPUR_FILTER_TYPE_MASK 0x60000000
-#define PHY_BB_CCK_SPUR_MIT_SPUR_FILTER_TYPE_GET(x) (((x) & 0x60000000) >> 29)
-#define PHY_BB_CCK_SPUR_MIT_SPUR_FILTER_TYPE_SET(x) (((x) << 29) & 0x60000000)
-
-/* macros for BB_panic_watchdog_status */
-#define PHY_BB_PANIC_WATCHDOG_STATUS_ADDRESS 0x0000a244
-#define PHY_BB_PANIC_WATCHDOG_STATUS_OFFSET 0x0000a244
-#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_1_MSB 2
-#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_1_LSB 0
-#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_1_MASK 0x00000007
-#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_1_GET(x) (((x) & 0x00000007) >> 0)
-#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_1_SET(x) (((x) << 0) & 0x00000007)
-#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_DET_HANG_MSB 3
-#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_DET_HANG_LSB 3
-#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_DET_HANG_MASK 0x00000008
-#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_DET_HANG_GET(x) (((x) & 0x00000008) >> 3)
-#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_DET_HANG_SET(x) (((x) << 3) & 0x00000008)
-#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_2_MSB 7
-#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_2_LSB 4
-#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_2_MASK 0x000000f0
-#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_2_GET(x) (((x) & 0x000000f0) >> 4)
-#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_2_SET(x) (((x) << 4) & 0x000000f0)
-#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_3_MSB 11
-#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_3_LSB 8
-#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_3_MASK 0x00000f00
-#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_3_GET(x) (((x) & 0x00000f00) >> 8)
-#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_3_SET(x) (((x) << 8) & 0x00000f00)
-#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_4_MSB 15
-#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_4_LSB 12
-#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_4_MASK 0x0000f000
-#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_4_GET(x) (((x) & 0x0000f000) >> 12)
-#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_4_SET(x) (((x) << 12) & 0x0000f000)
-#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_5_MSB 19
-#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_5_LSB 16
-#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_5_MASK 0x000f0000
-#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_5_GET(x) (((x) & 0x000f0000) >> 16)
-#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_5_SET(x) (((x) << 16) & 0x000f0000)
-#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_6_MSB 23
-#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_6_LSB 20
-#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_6_MASK 0x00f00000
-#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_6_GET(x) (((x) & 0x00f00000) >> 20)
-#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_6_SET(x) (((x) << 20) & 0x00f00000)
-#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_7_MSB 27
-#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_7_LSB 24
-#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_7_MASK 0x0f000000
-#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_7_GET(x) (((x) & 0x0f000000) >> 24)
-#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_7_SET(x) (((x) << 24) & 0x0f000000)
-#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_8_MSB 31
-#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_8_LSB 28
-#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_8_MASK 0xf0000000
-#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_8_GET(x) (((x) & 0xf0000000) >> 28)
-#define PHY_BB_PANIC_WATCHDOG_STATUS_PANIC_WATCHDOG_STATUS_8_SET(x) (((x) << 28) & 0xf0000000)
-
-/* macros for BB_panic_watchdog_ctrl_1 */
-#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ADDRESS 0x0000a248
-#define PHY_BB_PANIC_WATCHDOG_CTRL_1_OFFSET 0x0000a248
-#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_NON_IDLE_MSB 0
-#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_NON_IDLE_LSB 0
-#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_NON_IDLE_MASK 0x00000001
-#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_NON_IDLE_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_NON_IDLE_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_IDLE_MSB 1
-#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_IDLE_LSB 1
-#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_IDLE_MASK 0x00000002
-#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_IDLE_GET(x) (((x) & 0x00000002) >> 1)
-#define PHY_BB_PANIC_WATCHDOG_CTRL_1_ENABLE_PANIC_WATCHDOG_IDLE_SET(x) (((x) << 1) & 0x00000002)
-#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_NON_IDLE_LIMIT_MSB 15
-#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_NON_IDLE_LIMIT_LSB 2
-#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_NON_IDLE_LIMIT_MASK 0x0000fffc
-#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_NON_IDLE_LIMIT_GET(x) (((x) & 0x0000fffc) >> 2)
-#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_NON_IDLE_LIMIT_SET(x) (((x) << 2) & 0x0000fffc)
-#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_IDLE_LIMIT_MSB 31
-#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_IDLE_LIMIT_LSB 16
-#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_IDLE_LIMIT_MASK 0xffff0000
-#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_IDLE_LIMIT_GET(x) (((x) & 0xffff0000) >> 16)
-#define PHY_BB_PANIC_WATCHDOG_CTRL_1_PANIC_WATCHDOG_IDLE_LIMIT_SET(x) (((x) << 16) & 0xffff0000)
-
-/* macros for BB_panic_watchdog_ctrl_2 */
-#define PHY_BB_PANIC_WATCHDOG_CTRL_2_ADDRESS 0x0000a24c
-#define PHY_BB_PANIC_WATCHDOG_CTRL_2_OFFSET 0x0000a24c
-#define PHY_BB_PANIC_WATCHDOG_CTRL_2_FORCE_FAST_ADC_CLK_MSB 0
-#define PHY_BB_PANIC_WATCHDOG_CTRL_2_FORCE_FAST_ADC_CLK_LSB 0
-#define PHY_BB_PANIC_WATCHDOG_CTRL_2_FORCE_FAST_ADC_CLK_MASK 0x00000001
-#define PHY_BB_PANIC_WATCHDOG_CTRL_2_FORCE_FAST_ADC_CLK_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_BB_PANIC_WATCHDOG_CTRL_2_FORCE_FAST_ADC_CLK_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_RESET_ENA_MSB 1
-#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_RESET_ENA_LSB 1
-#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_RESET_ENA_MASK 0x00000002
-#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_RESET_ENA_GET(x) (((x) & 0x00000002) >> 1)
-#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_RESET_ENA_SET(x) (((x) << 1) & 0x00000002)
-#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_IRQ_ENA_MSB 2
-#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_IRQ_ENA_LSB 2
-#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_IRQ_ENA_MASK 0x00000004
-#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_IRQ_ENA_GET(x) (((x) & 0x00000004) >> 2)
-#define PHY_BB_PANIC_WATCHDOG_CTRL_2_PANIC_WATCHDOG_IRQ_ENA_SET(x) (((x) << 2) & 0x00000004)
-
-/* macros for BB_iqcorr_ctrl_cck */
-#define PHY_BB_IQCORR_CTRL_CCK_ADDRESS 0x0000a250
-#define PHY_BB_IQCORR_CTRL_CCK_OFFSET 0x0000a250
-#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_Q_COFF_CCK_MSB 4
-#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_Q_COFF_CCK_LSB 0
-#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_Q_COFF_CCK_MASK 0x0000001f
-#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_Q_COFF_CCK_GET(x) (((x) & 0x0000001f) >> 0)
-#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_Q_COFF_CCK_SET(x) (((x) << 0) & 0x0000001f)
-#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_I_COFF_CCK_MSB 10
-#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_I_COFF_CCK_LSB 5
-#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_I_COFF_CCK_MASK 0x000007e0
-#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_I_COFF_CCK_GET(x) (((x) & 0x000007e0) >> 5)
-#define PHY_BB_IQCORR_CTRL_CCK_IQCORR_Q_I_COFF_CCK_SET(x) (((x) << 5) & 0x000007e0)
-#define PHY_BB_IQCORR_CTRL_CCK_ENABLE_IQCORR_CCK_MSB 11
-#define PHY_BB_IQCORR_CTRL_CCK_ENABLE_IQCORR_CCK_LSB 11
-#define PHY_BB_IQCORR_CTRL_CCK_ENABLE_IQCORR_CCK_MASK 0x00000800
-#define PHY_BB_IQCORR_CTRL_CCK_ENABLE_IQCORR_CCK_GET(x) (((x) & 0x00000800) >> 11)
-#define PHY_BB_IQCORR_CTRL_CCK_ENABLE_IQCORR_CCK_SET(x) (((x) << 11) & 0x00000800)
-#define PHY_BB_IQCORR_CTRL_CCK_RXCAL_MEAS_TIME_SEL_MSB 13
-#define PHY_BB_IQCORR_CTRL_CCK_RXCAL_MEAS_TIME_SEL_LSB 12
-#define PHY_BB_IQCORR_CTRL_CCK_RXCAL_MEAS_TIME_SEL_MASK 0x00003000
-#define PHY_BB_IQCORR_CTRL_CCK_RXCAL_MEAS_TIME_SEL_GET(x) (((x) & 0x00003000) >> 12)
-#define PHY_BB_IQCORR_CTRL_CCK_RXCAL_MEAS_TIME_SEL_SET(x) (((x) << 12) & 0x00003000)
-#define PHY_BB_IQCORR_CTRL_CCK_CLCAL_MEAS_TIME_SEL_MSB 15
-#define PHY_BB_IQCORR_CTRL_CCK_CLCAL_MEAS_TIME_SEL_LSB 14
-#define PHY_BB_IQCORR_CTRL_CCK_CLCAL_MEAS_TIME_SEL_MASK 0x0000c000
-#define PHY_BB_IQCORR_CTRL_CCK_CLCAL_MEAS_TIME_SEL_GET(x) (((x) & 0x0000c000) >> 14)
-#define PHY_BB_IQCORR_CTRL_CCK_CLCAL_MEAS_TIME_SEL_SET(x) (((x) << 14) & 0x0000c000)
-#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_INIT_RFGAIN_MSB 20
-#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_INIT_RFGAIN_LSB 16
-#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_INIT_RFGAIN_MASK 0x001f0000
-#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_INIT_RFGAIN_GET(x) (((x) & 0x001f0000) >> 16)
-#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_INIT_RFGAIN_SET(x) (((x) << 16) & 0x001f0000)
-#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_PAL_MODE_MSB 21
-#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_PAL_MODE_LSB 21
-#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_PAL_MODE_MASK 0x00200000
-#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_PAL_MODE_GET(x) (((x) & 0x00200000) >> 21)
-#define PHY_BB_IQCORR_CTRL_CCK_CF_CLC_PAL_MODE_SET(x) (((x) << 21) & 0x00200000)
-
-/* macros for BB_bluetooth_cntl */
-#define PHY_BB_BLUETOOTH_CNTL_ADDRESS 0x0000a254
-#define PHY_BB_BLUETOOTH_CNTL_OFFSET 0x0000a254
-#define PHY_BB_BLUETOOTH_CNTL_BT_BREAK_CCK_EN_MSB 0
-#define PHY_BB_BLUETOOTH_CNTL_BT_BREAK_CCK_EN_LSB 0
-#define PHY_BB_BLUETOOTH_CNTL_BT_BREAK_CCK_EN_MASK 0x00000001
-#define PHY_BB_BLUETOOTH_CNTL_BT_BREAK_CCK_EN_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_BB_BLUETOOTH_CNTL_BT_BREAK_CCK_EN_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_BB_BLUETOOTH_CNTL_BT_ANT_HALT_WLAN_MSB 1
-#define PHY_BB_BLUETOOTH_CNTL_BT_ANT_HALT_WLAN_LSB 1
-#define PHY_BB_BLUETOOTH_CNTL_BT_ANT_HALT_WLAN_MASK 0x00000002
-#define PHY_BB_BLUETOOTH_CNTL_BT_ANT_HALT_WLAN_GET(x) (((x) & 0x00000002) >> 1)
-#define PHY_BB_BLUETOOTH_CNTL_BT_ANT_HALT_WLAN_SET(x) (((x) << 1) & 0x00000002)
-
-/* macros for BB_tpc_1 */
-#define PHY_BB_TPC_1_ADDRESS 0x0000a258
-#define PHY_BB_TPC_1_OFFSET 0x0000a258
-#define PHY_BB_TPC_1_FORCE_DAC_GAIN_MSB 0
-#define PHY_BB_TPC_1_FORCE_DAC_GAIN_LSB 0
-#define PHY_BB_TPC_1_FORCE_DAC_GAIN_MASK 0x00000001
-#define PHY_BB_TPC_1_FORCE_DAC_GAIN_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_BB_TPC_1_FORCE_DAC_GAIN_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_BB_TPC_1_FORCED_DAC_GAIN_MSB 5
-#define PHY_BB_TPC_1_FORCED_DAC_GAIN_LSB 1
-#define PHY_BB_TPC_1_FORCED_DAC_GAIN_MASK 0x0000003e
-#define PHY_BB_TPC_1_FORCED_DAC_GAIN_GET(x) (((x) & 0x0000003e) >> 1)
-#define PHY_BB_TPC_1_FORCED_DAC_GAIN_SET(x) (((x) << 1) & 0x0000003e)
-#define PHY_BB_TPC_1_PD_DC_OFFSET_TARGET_MSB 13
-#define PHY_BB_TPC_1_PD_DC_OFFSET_TARGET_LSB 6
-#define PHY_BB_TPC_1_PD_DC_OFFSET_TARGET_MASK 0x00003fc0
-#define PHY_BB_TPC_1_PD_DC_OFFSET_TARGET_GET(x) (((x) & 0x00003fc0) >> 6)
-#define PHY_BB_TPC_1_PD_DC_OFFSET_TARGET_SET(x) (((x) << 6) & 0x00003fc0)
-#define PHY_BB_TPC_1_NUM_PD_GAIN_MSB 15
-#define PHY_BB_TPC_1_NUM_PD_GAIN_LSB 14
-#define PHY_BB_TPC_1_NUM_PD_GAIN_MASK 0x0000c000
-#define PHY_BB_TPC_1_NUM_PD_GAIN_GET(x) (((x) & 0x0000c000) >> 14)
-#define PHY_BB_TPC_1_NUM_PD_GAIN_SET(x) (((x) << 14) & 0x0000c000)
-#define PHY_BB_TPC_1_PD_GAIN_SETTING1_MSB 17
-#define PHY_BB_TPC_1_PD_GAIN_SETTING1_LSB 16
-#define PHY_BB_TPC_1_PD_GAIN_SETTING1_MASK 0x00030000
-#define PHY_BB_TPC_1_PD_GAIN_SETTING1_GET(x) (((x) & 0x00030000) >> 16)
-#define PHY_BB_TPC_1_PD_GAIN_SETTING1_SET(x) (((x) << 16) & 0x00030000)
-#define PHY_BB_TPC_1_PD_GAIN_SETTING2_MSB 19
-#define PHY_BB_TPC_1_PD_GAIN_SETTING2_LSB 18
-#define PHY_BB_TPC_1_PD_GAIN_SETTING2_MASK 0x000c0000
-#define PHY_BB_TPC_1_PD_GAIN_SETTING2_GET(x) (((x) & 0x000c0000) >> 18)
-#define PHY_BB_TPC_1_PD_GAIN_SETTING2_SET(x) (((x) << 18) & 0x000c0000)
-#define PHY_BB_TPC_1_PD_GAIN_SETTING3_MSB 21
-#define PHY_BB_TPC_1_PD_GAIN_SETTING3_LSB 20
-#define PHY_BB_TPC_1_PD_GAIN_SETTING3_MASK 0x00300000
-#define PHY_BB_TPC_1_PD_GAIN_SETTING3_GET(x) (((x) & 0x00300000) >> 20)
-#define PHY_BB_TPC_1_PD_GAIN_SETTING3_SET(x) (((x) << 20) & 0x00300000)
-#define PHY_BB_TPC_1_ENABLE_PD_CALIBRATE_MSB 22
-#define PHY_BB_TPC_1_ENABLE_PD_CALIBRATE_LSB 22
-#define PHY_BB_TPC_1_ENABLE_PD_CALIBRATE_MASK 0x00400000
-#define PHY_BB_TPC_1_ENABLE_PD_CALIBRATE_GET(x) (((x) & 0x00400000) >> 22)
-#define PHY_BB_TPC_1_ENABLE_PD_CALIBRATE_SET(x) (((x) << 22) & 0x00400000)
-#define PHY_BB_TPC_1_PD_CALIBRATE_WAIT_MSB 28
-#define PHY_BB_TPC_1_PD_CALIBRATE_WAIT_LSB 23
-#define PHY_BB_TPC_1_PD_CALIBRATE_WAIT_MASK 0x1f800000
-#define PHY_BB_TPC_1_PD_CALIBRATE_WAIT_GET(x) (((x) & 0x1f800000) >> 23)
-#define PHY_BB_TPC_1_PD_CALIBRATE_WAIT_SET(x) (((x) << 23) & 0x1f800000)
-#define PHY_BB_TPC_1_FORCE_PDADC_GAIN_MSB 29
-#define PHY_BB_TPC_1_FORCE_PDADC_GAIN_LSB 29
-#define PHY_BB_TPC_1_FORCE_PDADC_GAIN_MASK 0x20000000
-#define PHY_BB_TPC_1_FORCE_PDADC_GAIN_GET(x) (((x) & 0x20000000) >> 29)
-#define PHY_BB_TPC_1_FORCE_PDADC_GAIN_SET(x) (((x) << 29) & 0x20000000)
-#define PHY_BB_TPC_1_FORCED_PDADC_GAIN_MSB 31
-#define PHY_BB_TPC_1_FORCED_PDADC_GAIN_LSB 30
-#define PHY_BB_TPC_1_FORCED_PDADC_GAIN_MASK 0xc0000000
-#define PHY_BB_TPC_1_FORCED_PDADC_GAIN_GET(x) (((x) & 0xc0000000) >> 30)
-#define PHY_BB_TPC_1_FORCED_PDADC_GAIN_SET(x) (((x) << 30) & 0xc0000000)
-
-/* macros for BB_tpc_2 */
-#define PHY_BB_TPC_2_ADDRESS 0x0000a25c
-#define PHY_BB_TPC_2_OFFSET 0x0000a25c
-#define PHY_BB_TPC_2_TX_FRAME_TO_PDADC_ON_MSB 7
-#define PHY_BB_TPC_2_TX_FRAME_TO_PDADC_ON_LSB 0
-#define PHY_BB_TPC_2_TX_FRAME_TO_PDADC_ON_MASK 0x000000ff
-#define PHY_BB_TPC_2_TX_FRAME_TO_PDADC_ON_GET(x) (((x) & 0x000000ff) >> 0)
-#define PHY_BB_TPC_2_TX_FRAME_TO_PDADC_ON_SET(x) (((x) << 0) & 0x000000ff)
-#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_OFDM_MSB 15
-#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_OFDM_LSB 8
-#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_OFDM_MASK 0x0000ff00
-#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_OFDM_GET(x) (((x) & 0x0000ff00) >> 8)
-#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_OFDM_SET(x) (((x) << 8) & 0x0000ff00)
-#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_CCK_MSB 23
-#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_CCK_LSB 16
-#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_CCK_MASK 0x00ff0000
-#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_CCK_GET(x) (((x) & 0x00ff0000) >> 16)
-#define PHY_BB_TPC_2_TX_FRAME_TO_PD_ACC_CCK_SET(x) (((x) << 16) & 0x00ff0000)
-
-/* macros for BB_tpc_3 */
-#define PHY_BB_TPC_3_ADDRESS 0x0000a260
-#define PHY_BB_TPC_3_OFFSET 0x0000a260
-#define PHY_BB_TPC_3_TX_END_TO_PDADC_ON_MSB 7
-#define PHY_BB_TPC_3_TX_END_TO_PDADC_ON_LSB 0
-#define PHY_BB_TPC_3_TX_END_TO_PDADC_ON_MASK 0x000000ff
-#define PHY_BB_TPC_3_TX_END_TO_PDADC_ON_GET(x) (((x) & 0x000000ff) >> 0)
-#define PHY_BB_TPC_3_TX_END_TO_PDADC_ON_SET(x) (((x) << 0) & 0x000000ff)
-#define PHY_BB_TPC_3_TX_END_TO_PD_ACC_ON_MSB 15
-#define PHY_BB_TPC_3_TX_END_TO_PD_ACC_ON_LSB 8
-#define PHY_BB_TPC_3_TX_END_TO_PD_ACC_ON_MASK 0x0000ff00
-#define PHY_BB_TPC_3_TX_END_TO_PD_ACC_ON_GET(x) (((x) & 0x0000ff00) >> 8)
-#define PHY_BB_TPC_3_TX_END_TO_PD_ACC_ON_SET(x) (((x) << 8) & 0x0000ff00)
-#define PHY_BB_TPC_3_PD_ACC_WINDOW_DC_OFF_MSB 18
-#define PHY_BB_TPC_3_PD_ACC_WINDOW_DC_OFF_LSB 16
-#define PHY_BB_TPC_3_PD_ACC_WINDOW_DC_OFF_MASK 0x00070000
-#define PHY_BB_TPC_3_PD_ACC_WINDOW_DC_OFF_GET(x) (((x) & 0x00070000) >> 16)
-#define PHY_BB_TPC_3_PD_ACC_WINDOW_DC_OFF_SET(x) (((x) << 16) & 0x00070000)
-#define PHY_BB_TPC_3_PD_ACC_WINDOW_CAL_MSB 21
-#define PHY_BB_TPC_3_PD_ACC_WINDOW_CAL_LSB 19
-#define PHY_BB_TPC_3_PD_ACC_WINDOW_CAL_MASK 0x00380000
-#define PHY_BB_TPC_3_PD_ACC_WINDOW_CAL_GET(x) (((x) & 0x00380000) >> 19)
-#define PHY_BB_TPC_3_PD_ACC_WINDOW_CAL_SET(x) (((x) << 19) & 0x00380000)
-#define PHY_BB_TPC_3_PD_ACC_WINDOW_OFDM_MSB 24
-#define PHY_BB_TPC_3_PD_ACC_WINDOW_OFDM_LSB 22
-#define PHY_BB_TPC_3_PD_ACC_WINDOW_OFDM_MASK 0x01c00000
-#define PHY_BB_TPC_3_PD_ACC_WINDOW_OFDM_GET(x) (((x) & 0x01c00000) >> 22)
-#define PHY_BB_TPC_3_PD_ACC_WINDOW_OFDM_SET(x) (((x) << 22) & 0x01c00000)
-#define PHY_BB_TPC_3_PD_ACC_WINDOW_CCK_MSB 27
-#define PHY_BB_TPC_3_PD_ACC_WINDOW_CCK_LSB 25
-#define PHY_BB_TPC_3_PD_ACC_WINDOW_CCK_MASK 0x0e000000
-#define PHY_BB_TPC_3_PD_ACC_WINDOW_CCK_GET(x) (((x) & 0x0e000000) >> 25)
-#define PHY_BB_TPC_3_PD_ACC_WINDOW_CCK_SET(x) (((x) << 25) & 0x0e000000)
-#define PHY_BB_TPC_3_TPC_CLK_GATE_ENABLE_MSB 31
-#define PHY_BB_TPC_3_TPC_CLK_GATE_ENABLE_LSB 31
-#define PHY_BB_TPC_3_TPC_CLK_GATE_ENABLE_MASK 0x80000000
-#define PHY_BB_TPC_3_TPC_CLK_GATE_ENABLE_GET(x) (((x) & 0x80000000) >> 31)
-#define PHY_BB_TPC_3_TPC_CLK_GATE_ENABLE_SET(x) (((x) << 31) & 0x80000000)
-
-/* macros for BB_tpc_4_b0 */
-#define PHY_BB_TPC_4_B0_ADDRESS 0x0000a264
-#define PHY_BB_TPC_4_B0_OFFSET 0x0000a264
-#define PHY_BB_TPC_4_B0_PD_AVG_VALID_0_MSB 0
-#define PHY_BB_TPC_4_B0_PD_AVG_VALID_0_LSB 0
-#define PHY_BB_TPC_4_B0_PD_AVG_VALID_0_MASK 0x00000001
-#define PHY_BB_TPC_4_B0_PD_AVG_VALID_0_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_BB_TPC_4_B0_PD_AVG_OUT_0_MSB 8
-#define PHY_BB_TPC_4_B0_PD_AVG_OUT_0_LSB 1
-#define PHY_BB_TPC_4_B0_PD_AVG_OUT_0_MASK 0x000001fe
-#define PHY_BB_TPC_4_B0_PD_AVG_OUT_0_GET(x) (((x) & 0x000001fe) >> 1)
-#define PHY_BB_TPC_4_B0_DAC_GAIN_0_MSB 13
-#define PHY_BB_TPC_4_B0_DAC_GAIN_0_LSB 9
-#define PHY_BB_TPC_4_B0_DAC_GAIN_0_MASK 0x00003e00
-#define PHY_BB_TPC_4_B0_DAC_GAIN_0_GET(x) (((x) & 0x00003e00) >> 9)
-#define PHY_BB_TPC_4_B0_TX_GAIN_SETTING_0_MSB 19
-#define PHY_BB_TPC_4_B0_TX_GAIN_SETTING_0_LSB 14
-#define PHY_BB_TPC_4_B0_TX_GAIN_SETTING_0_MASK 0x000fc000
-#define PHY_BB_TPC_4_B0_TX_GAIN_SETTING_0_GET(x) (((x) & 0x000fc000) >> 14)
-#define PHY_BB_TPC_4_B0_RATE_SENT_0_MSB 24
-#define PHY_BB_TPC_4_B0_RATE_SENT_0_LSB 20
-#define PHY_BB_TPC_4_B0_RATE_SENT_0_MASK 0x01f00000
-#define PHY_BB_TPC_4_B0_RATE_SENT_0_GET(x) (((x) & 0x01f00000) >> 20)
-#define PHY_BB_TPC_4_B0_ERROR_EST_UPDATE_POWER_THRESH_MSB 30
-#define PHY_BB_TPC_4_B0_ERROR_EST_UPDATE_POWER_THRESH_LSB 25
-#define PHY_BB_TPC_4_B0_ERROR_EST_UPDATE_POWER_THRESH_MASK 0x7e000000
-#define PHY_BB_TPC_4_B0_ERROR_EST_UPDATE_POWER_THRESH_GET(x) (((x) & 0x7e000000) >> 25)
-#define PHY_BB_TPC_4_B0_ERROR_EST_UPDATE_POWER_THRESH_SET(x) (((x) << 25) & 0x7e000000)
-
-/* macros for BB_analog_swap */
-#define PHY_BB_ANALOG_SWAP_ADDRESS 0x0000a268
-#define PHY_BB_ANALOG_SWAP_OFFSET 0x0000a268
-#define PHY_BB_ANALOG_SWAP_ANALOG_RX_SWAP_CNTL_MSB 2
-#define PHY_BB_ANALOG_SWAP_ANALOG_RX_SWAP_CNTL_LSB 0
-#define PHY_BB_ANALOG_SWAP_ANALOG_RX_SWAP_CNTL_MASK 0x00000007
-#define PHY_BB_ANALOG_SWAP_ANALOG_RX_SWAP_CNTL_GET(x) (((x) & 0x00000007) >> 0)
-#define PHY_BB_ANALOG_SWAP_ANALOG_RX_SWAP_CNTL_SET(x) (((x) << 0) & 0x00000007)
-#define PHY_BB_ANALOG_SWAP_ANALOG_TX_SWAP_CNTL_MSB 5
-#define PHY_BB_ANALOG_SWAP_ANALOG_TX_SWAP_CNTL_LSB 3
-#define PHY_BB_ANALOG_SWAP_ANALOG_TX_SWAP_CNTL_MASK 0x00000038
-#define PHY_BB_ANALOG_SWAP_ANALOG_TX_SWAP_CNTL_GET(x) (((x) & 0x00000038) >> 3)
-#define PHY_BB_ANALOG_SWAP_ANALOG_TX_SWAP_CNTL_SET(x) (((x) << 3) & 0x00000038)
-#define PHY_BB_ANALOG_SWAP_SWAP_ALT_CHN_MSB 6
-#define PHY_BB_ANALOG_SWAP_SWAP_ALT_CHN_LSB 6
-#define PHY_BB_ANALOG_SWAP_SWAP_ALT_CHN_MASK 0x00000040
-#define PHY_BB_ANALOG_SWAP_SWAP_ALT_CHN_GET(x) (((x) & 0x00000040) >> 6)
-#define PHY_BB_ANALOG_SWAP_SWAP_ALT_CHN_SET(x) (((x) << 6) & 0x00000040)
-#define PHY_BB_ANALOG_SWAP_ANALOG_DC_DAC_POLARITY_MSB 7
-#define PHY_BB_ANALOG_SWAP_ANALOG_DC_DAC_POLARITY_LSB 7
-#define PHY_BB_ANALOG_SWAP_ANALOG_DC_DAC_POLARITY_MASK 0x00000080
-#define PHY_BB_ANALOG_SWAP_ANALOG_DC_DAC_POLARITY_GET(x) (((x) & 0x00000080) >> 7)
-#define PHY_BB_ANALOG_SWAP_ANALOG_DC_DAC_POLARITY_SET(x) (((x) << 7) & 0x00000080)
-#define PHY_BB_ANALOG_SWAP_ANALOG_PKDET_DAC_POLARITY_MSB 8
-#define PHY_BB_ANALOG_SWAP_ANALOG_PKDET_DAC_POLARITY_LSB 8
-#define PHY_BB_ANALOG_SWAP_ANALOG_PKDET_DAC_POLARITY_MASK 0x00000100
-#define PHY_BB_ANALOG_SWAP_ANALOG_PKDET_DAC_POLARITY_GET(x) (((x) & 0x00000100) >> 8)
-#define PHY_BB_ANALOG_SWAP_ANALOG_PKDET_DAC_POLARITY_SET(x) (((x) << 8) & 0x00000100)
-
-/* macros for BB_tpc_5_b0 */
-#define PHY_BB_TPC_5_B0_ADDRESS 0x0000a26c
-#define PHY_BB_TPC_5_B0_OFFSET 0x0000a26c
-#define PHY_BB_TPC_5_B0_PD_GAIN_OVERLAP_MSB 3
-#define PHY_BB_TPC_5_B0_PD_GAIN_OVERLAP_LSB 0
-#define PHY_BB_TPC_5_B0_PD_GAIN_OVERLAP_MASK 0x0000000f
-#define PHY_BB_TPC_5_B0_PD_GAIN_OVERLAP_GET(x) (((x) & 0x0000000f) >> 0)
-#define PHY_BB_TPC_5_B0_PD_GAIN_OVERLAP_SET(x) (((x) << 0) & 0x0000000f)
-#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_1_0_MSB 9
-#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_1_0_LSB 4
-#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_1_0_MASK 0x000003f0
-#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_1_0_GET(x) (((x) & 0x000003f0) >> 4)
-#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_1_0_SET(x) (((x) << 4) & 0x000003f0)
-#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_2_0_MSB 15
-#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_2_0_LSB 10
-#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_2_0_MASK 0x0000fc00
-#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_2_0_GET(x) (((x) & 0x0000fc00) >> 10)
-#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_2_0_SET(x) (((x) << 10) & 0x0000fc00)
-#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_3_0_MSB 21
-#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_3_0_LSB 16
-#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_3_0_MASK 0x003f0000
-#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_3_0_GET(x) (((x) & 0x003f0000) >> 16)
-#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_3_0_SET(x) (((x) << 16) & 0x003f0000)
-#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_4_0_MSB 27
-#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_4_0_LSB 22
-#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_4_0_MASK 0x0fc00000
-#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_4_0_GET(x) (((x) & 0x0fc00000) >> 22)
-#define PHY_BB_TPC_5_B0_PD_GAIN_BOUNDARY_4_0_SET(x) (((x) << 22) & 0x0fc00000)
-
-/* macros for BB_tpc_6_b0 */
-#define PHY_BB_TPC_6_B0_ADDRESS 0x0000a270
-#define PHY_BB_TPC_6_B0_OFFSET 0x0000a270
-#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_1_0_MSB 5
-#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_1_0_LSB 0
-#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_1_0_MASK 0x0000003f
-#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_1_0_GET(x) (((x) & 0x0000003f) >> 0)
-#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_1_0_SET(x) (((x) << 0) & 0x0000003f)
-#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_2_0_MSB 11
-#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_2_0_LSB 6
-#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_2_0_MASK 0x00000fc0
-#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_2_0_GET(x) (((x) & 0x00000fc0) >> 6)
-#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_2_0_SET(x) (((x) << 6) & 0x00000fc0)
-#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_3_0_MSB 17
-#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_3_0_LSB 12
-#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_3_0_MASK 0x0003f000
-#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_3_0_GET(x) (((x) & 0x0003f000) >> 12)
-#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_3_0_SET(x) (((x) << 12) & 0x0003f000)
-#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_4_0_MSB 23
-#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_4_0_LSB 18
-#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_4_0_MASK 0x00fc0000
-#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_4_0_GET(x) (((x) & 0x00fc0000) >> 18)
-#define PHY_BB_TPC_6_B0_PD_DAC_SETTING_4_0_SET(x) (((x) << 18) & 0x00fc0000)
-#define PHY_BB_TPC_6_B0_ERROR_EST_MODE_MSB 25
-#define PHY_BB_TPC_6_B0_ERROR_EST_MODE_LSB 24
-#define PHY_BB_TPC_6_B0_ERROR_EST_MODE_MASK 0x03000000
-#define PHY_BB_TPC_6_B0_ERROR_EST_MODE_GET(x) (((x) & 0x03000000) >> 24)
-#define PHY_BB_TPC_6_B0_ERROR_EST_MODE_SET(x) (((x) << 24) & 0x03000000)
-#define PHY_BB_TPC_6_B0_ERROR_EST_FILTER_COEFF_MSB 28
-#define PHY_BB_TPC_6_B0_ERROR_EST_FILTER_COEFF_LSB 26
-#define PHY_BB_TPC_6_B0_ERROR_EST_FILTER_COEFF_MASK 0x1c000000
-#define PHY_BB_TPC_6_B0_ERROR_EST_FILTER_COEFF_GET(x) (((x) & 0x1c000000) >> 26)
-#define PHY_BB_TPC_6_B0_ERROR_EST_FILTER_COEFF_SET(x) (((x) << 26) & 0x1c000000)
-
-/* macros for BB_tpc_7 */
-#define PHY_BB_TPC_7_ADDRESS 0x0000a274
-#define PHY_BB_TPC_7_OFFSET 0x0000a274
-#define PHY_BB_TPC_7_TX_GAIN_TABLE_MAX_MSB 5
-#define PHY_BB_TPC_7_TX_GAIN_TABLE_MAX_LSB 0
-#define PHY_BB_TPC_7_TX_GAIN_TABLE_MAX_MASK 0x0000003f
-#define PHY_BB_TPC_7_TX_GAIN_TABLE_MAX_GET(x) (((x) & 0x0000003f) >> 0)
-#define PHY_BB_TPC_7_TX_GAIN_TABLE_MAX_SET(x) (((x) << 0) & 0x0000003f)
-#define PHY_BB_TPC_7_INIT_TX_GAIN_SETTING_MSB 11
-#define PHY_BB_TPC_7_INIT_TX_GAIN_SETTING_LSB 6
-#define PHY_BB_TPC_7_INIT_TX_GAIN_SETTING_MASK 0x00000fc0
-#define PHY_BB_TPC_7_INIT_TX_GAIN_SETTING_GET(x) (((x) & 0x00000fc0) >> 6)
-#define PHY_BB_TPC_7_INIT_TX_GAIN_SETTING_SET(x) (((x) << 6) & 0x00000fc0)
-#define PHY_BB_TPC_7_EN_CL_GAIN_MOD_MSB 12
-#define PHY_BB_TPC_7_EN_CL_GAIN_MOD_LSB 12
-#define PHY_BB_TPC_7_EN_CL_GAIN_MOD_MASK 0x00001000
-#define PHY_BB_TPC_7_EN_CL_GAIN_MOD_GET(x) (((x) & 0x00001000) >> 12)
-#define PHY_BB_TPC_7_EN_CL_GAIN_MOD_SET(x) (((x) << 12) & 0x00001000)
-#define PHY_BB_TPC_7_USE_TX_PD_IN_XPA_MSB 13
-#define PHY_BB_TPC_7_USE_TX_PD_IN_XPA_LSB 13
-#define PHY_BB_TPC_7_USE_TX_PD_IN_XPA_MASK 0x00002000
-#define PHY_BB_TPC_7_USE_TX_PD_IN_XPA_GET(x) (((x) & 0x00002000) >> 13)
-#define PHY_BB_TPC_7_USE_TX_PD_IN_XPA_SET(x) (((x) << 13) & 0x00002000)
-#define PHY_BB_TPC_7_EXTEND_TX_FRAME_FOR_TPC_MSB 14
-#define PHY_BB_TPC_7_EXTEND_TX_FRAME_FOR_TPC_LSB 14
-#define PHY_BB_TPC_7_EXTEND_TX_FRAME_FOR_TPC_MASK 0x00004000
-#define PHY_BB_TPC_7_EXTEND_TX_FRAME_FOR_TPC_GET(x) (((x) & 0x00004000) >> 14)
-#define PHY_BB_TPC_7_EXTEND_TX_FRAME_FOR_TPC_SET(x) (((x) << 14) & 0x00004000)
-#define PHY_BB_TPC_7_USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET_MSB 15
-#define PHY_BB_TPC_7_USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET_LSB 15
-#define PHY_BB_TPC_7_USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET_MASK 0x00008000
-#define PHY_BB_TPC_7_USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET_GET(x) (((x) & 0x00008000) >> 15)
-#define PHY_BB_TPC_7_USE_INIT_TX_GAIN_SETTING_AFTER_WARM_RESET_SET(x) (((x) << 15) & 0x00008000)
-
-/* macros for BB_tpc_8 */
-#define PHY_BB_TPC_8_ADDRESS 0x0000a278
-#define PHY_BB_TPC_8_OFFSET 0x0000a278
-#define PHY_BB_TPC_8_DESIRED_SCALE_0_MSB 4
-#define PHY_BB_TPC_8_DESIRED_SCALE_0_LSB 0
-#define PHY_BB_TPC_8_DESIRED_SCALE_0_MASK 0x0000001f
-#define PHY_BB_TPC_8_DESIRED_SCALE_0_GET(x) (((x) & 0x0000001f) >> 0)
-#define PHY_BB_TPC_8_DESIRED_SCALE_0_SET(x) (((x) << 0) & 0x0000001f)
-#define PHY_BB_TPC_8_DESIRED_SCALE_1_MSB 9
-#define PHY_BB_TPC_8_DESIRED_SCALE_1_LSB 5
-#define PHY_BB_TPC_8_DESIRED_SCALE_1_MASK 0x000003e0
-#define PHY_BB_TPC_8_DESIRED_SCALE_1_GET(x) (((x) & 0x000003e0) >> 5)
-#define PHY_BB_TPC_8_DESIRED_SCALE_1_SET(x) (((x) << 5) & 0x000003e0)
-#define PHY_BB_TPC_8_DESIRED_SCALE_2_MSB 14
-#define PHY_BB_TPC_8_DESIRED_SCALE_2_LSB 10
-#define PHY_BB_TPC_8_DESIRED_SCALE_2_MASK 0x00007c00
-#define PHY_BB_TPC_8_DESIRED_SCALE_2_GET(x) (((x) & 0x00007c00) >> 10)
-#define PHY_BB_TPC_8_DESIRED_SCALE_2_SET(x) (((x) << 10) & 0x00007c00)
-#define PHY_BB_TPC_8_DESIRED_SCALE_3_MSB 19
-#define PHY_BB_TPC_8_DESIRED_SCALE_3_LSB 15
-#define PHY_BB_TPC_8_DESIRED_SCALE_3_MASK 0x000f8000
-#define PHY_BB_TPC_8_DESIRED_SCALE_3_GET(x) (((x) & 0x000f8000) >> 15)
-#define PHY_BB_TPC_8_DESIRED_SCALE_3_SET(x) (((x) << 15) & 0x000f8000)
-#define PHY_BB_TPC_8_DESIRED_SCALE_4_MSB 24
-#define PHY_BB_TPC_8_DESIRED_SCALE_4_LSB 20
-#define PHY_BB_TPC_8_DESIRED_SCALE_4_MASK 0x01f00000
-#define PHY_BB_TPC_8_DESIRED_SCALE_4_GET(x) (((x) & 0x01f00000) >> 20)
-#define PHY_BB_TPC_8_DESIRED_SCALE_4_SET(x) (((x) << 20) & 0x01f00000)
-#define PHY_BB_TPC_8_DESIRED_SCALE_5_MSB 29
-#define PHY_BB_TPC_8_DESIRED_SCALE_5_LSB 25
-#define PHY_BB_TPC_8_DESIRED_SCALE_5_MASK 0x3e000000
-#define PHY_BB_TPC_8_DESIRED_SCALE_5_GET(x) (((x) & 0x3e000000) >> 25)
-#define PHY_BB_TPC_8_DESIRED_SCALE_5_SET(x) (((x) << 25) & 0x3e000000)
-
-/* macros for BB_tpc_9 */
-#define PHY_BB_TPC_9_ADDRESS 0x0000a27c
-#define PHY_BB_TPC_9_OFFSET 0x0000a27c
-#define PHY_BB_TPC_9_DESIRED_SCALE_6_MSB 4
-#define PHY_BB_TPC_9_DESIRED_SCALE_6_LSB 0
-#define PHY_BB_TPC_9_DESIRED_SCALE_6_MASK 0x0000001f
-#define PHY_BB_TPC_9_DESIRED_SCALE_6_GET(x) (((x) & 0x0000001f) >> 0)
-#define PHY_BB_TPC_9_DESIRED_SCALE_6_SET(x) (((x) << 0) & 0x0000001f)
-#define PHY_BB_TPC_9_DESIRED_SCALE_7_MSB 9
-#define PHY_BB_TPC_9_DESIRED_SCALE_7_LSB 5
-#define PHY_BB_TPC_9_DESIRED_SCALE_7_MASK 0x000003e0
-#define PHY_BB_TPC_9_DESIRED_SCALE_7_GET(x) (((x) & 0x000003e0) >> 5)
-#define PHY_BB_TPC_9_DESIRED_SCALE_7_SET(x) (((x) << 5) & 0x000003e0)
-#define PHY_BB_TPC_9_DESIRED_SCALE_CCK_MSB 14
-#define PHY_BB_TPC_9_DESIRED_SCALE_CCK_LSB 10
-#define PHY_BB_TPC_9_DESIRED_SCALE_CCK_MASK 0x00007c00
-#define PHY_BB_TPC_9_DESIRED_SCALE_CCK_GET(x) (((x) & 0x00007c00) >> 10)
-#define PHY_BB_TPC_9_DESIRED_SCALE_CCK_SET(x) (((x) << 10) & 0x00007c00)
-#define PHY_BB_TPC_9_EN_PD_DC_OFFSET_THR_MSB 20
-#define PHY_BB_TPC_9_EN_PD_DC_OFFSET_THR_LSB 20
-#define PHY_BB_TPC_9_EN_PD_DC_OFFSET_THR_MASK 0x00100000
-#define PHY_BB_TPC_9_EN_PD_DC_OFFSET_THR_GET(x) (((x) & 0x00100000) >> 20)
-#define PHY_BB_TPC_9_EN_PD_DC_OFFSET_THR_SET(x) (((x) << 20) & 0x00100000)
-#define PHY_BB_TPC_9_PD_DC_OFFSET_THR_MSB 26
-#define PHY_BB_TPC_9_PD_DC_OFFSET_THR_LSB 21
-#define PHY_BB_TPC_9_PD_DC_OFFSET_THR_MASK 0x07e00000
-#define PHY_BB_TPC_9_PD_DC_OFFSET_THR_GET(x) (((x) & 0x07e00000) >> 21)
-#define PHY_BB_TPC_9_PD_DC_OFFSET_THR_SET(x) (((x) << 21) & 0x07e00000)
-#define PHY_BB_TPC_9_WAIT_CALTX_SETTLE_MSB 30
-#define PHY_BB_TPC_9_WAIT_CALTX_SETTLE_LSB 27
-#define PHY_BB_TPC_9_WAIT_CALTX_SETTLE_MASK 0x78000000
-#define PHY_BB_TPC_9_WAIT_CALTX_SETTLE_GET(x) (((x) & 0x78000000) >> 27)
-#define PHY_BB_TPC_9_WAIT_CALTX_SETTLE_SET(x) (((x) << 27) & 0x78000000)
-#define PHY_BB_TPC_9_DISABLE_PDADC_RESIDUAL_DC_REMOVAL_MSB 31
-#define PHY_BB_TPC_9_DISABLE_PDADC_RESIDUAL_DC_REMOVAL_LSB 31
-#define PHY_BB_TPC_9_DISABLE_PDADC_RESIDUAL_DC_REMOVAL_MASK 0x80000000
-#define PHY_BB_TPC_9_DISABLE_PDADC_RESIDUAL_DC_REMOVAL_GET(x) (((x) & 0x80000000) >> 31)
-#define PHY_BB_TPC_9_DISABLE_PDADC_RESIDUAL_DC_REMOVAL_SET(x) (((x) << 31) & 0x80000000)
-
-/* macros for BB_pdadc_tab_b0 */
-#define PHY_BB_PDADC_TAB_B0_ADDRESS 0x0000a280
-#define PHY_BB_PDADC_TAB_B0_OFFSET 0x0000a280
-#define PHY_BB_PDADC_TAB_B0_TAB_ENTRY_MSB 31
-#define PHY_BB_PDADC_TAB_B0_TAB_ENTRY_LSB 0
-#define PHY_BB_PDADC_TAB_B0_TAB_ENTRY_MASK 0xffffffff
-#define PHY_BB_PDADC_TAB_B0_TAB_ENTRY_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_cl_tab_b0 */
-#define PHY_BB_CL_TAB_B0_ADDRESS 0x0000a300
-#define PHY_BB_CL_TAB_B0_OFFSET 0x0000a300
-#define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_MSB 4
-#define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_LSB 0
-#define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_MASK 0x0000001f
-#define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_GET(x) (((x) & 0x0000001f) >> 0)
-#define PHY_BB_CL_TAB_B0_CL_GAIN_MOD_SET(x) (((x) << 0) & 0x0000001f)
-#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_MSB 15
-#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_LSB 5
-#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_MASK 0x0000ffe0
-#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_GET(x) (((x) & 0x0000ffe0) >> 5)
-#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_Q_SET(x) (((x) << 5) & 0x0000ffe0)
-#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_MSB 26
-#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_LSB 16
-#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_MASK 0x07ff0000
-#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_GET(x) (((x) & 0x07ff0000) >> 16)
-#define PHY_BB_CL_TAB_B0_CARR_LK_DC_ADD_I_SET(x) (((x) << 16) & 0x07ff0000)
-#define PHY_BB_CL_TAB_B0_BB_GAIN_MSB 30
-#define PHY_BB_CL_TAB_B0_BB_GAIN_LSB 27
-#define PHY_BB_CL_TAB_B0_BB_GAIN_MASK 0x78000000
-#define PHY_BB_CL_TAB_B0_BB_GAIN_GET(x) (((x) & 0x78000000) >> 27)
-#define PHY_BB_CL_TAB_B0_BB_GAIN_SET(x) (((x) << 27) & 0x78000000)
-
-/* macros for BB_cl_map_0_b0 */
-#define PHY_BB_CL_MAP_0_B0_ADDRESS 0x0000a340
-#define PHY_BB_CL_MAP_0_B0_OFFSET 0x0000a340
-#define PHY_BB_CL_MAP_0_B0_CL_MAP_0_MSB 31
-#define PHY_BB_CL_MAP_0_B0_CL_MAP_0_LSB 0
-#define PHY_BB_CL_MAP_0_B0_CL_MAP_0_MASK 0xffffffff
-#define PHY_BB_CL_MAP_0_B0_CL_MAP_0_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_CL_MAP_0_B0_CL_MAP_0_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_cl_map_1_b0 */
-#define PHY_BB_CL_MAP_1_B0_ADDRESS 0x0000a344
-#define PHY_BB_CL_MAP_1_B0_OFFSET 0x0000a344
-#define PHY_BB_CL_MAP_1_B0_CL_MAP_1_MSB 31
-#define PHY_BB_CL_MAP_1_B0_CL_MAP_1_LSB 0
-#define PHY_BB_CL_MAP_1_B0_CL_MAP_1_MASK 0xffffffff
-#define PHY_BB_CL_MAP_1_B0_CL_MAP_1_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_CL_MAP_1_B0_CL_MAP_1_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_cl_map_2_b0 */
-#define PHY_BB_CL_MAP_2_B0_ADDRESS 0x0000a348
-#define PHY_BB_CL_MAP_2_B0_OFFSET 0x0000a348
-#define PHY_BB_CL_MAP_2_B0_CL_MAP_2_MSB 31
-#define PHY_BB_CL_MAP_2_B0_CL_MAP_2_LSB 0
-#define PHY_BB_CL_MAP_2_B0_CL_MAP_2_MASK 0xffffffff
-#define PHY_BB_CL_MAP_2_B0_CL_MAP_2_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_CL_MAP_2_B0_CL_MAP_2_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_cl_map_3_b0 */
-#define PHY_BB_CL_MAP_3_B0_ADDRESS 0x0000a34c
-#define PHY_BB_CL_MAP_3_B0_OFFSET 0x0000a34c
-#define PHY_BB_CL_MAP_3_B0_CL_MAP_3_MSB 31
-#define PHY_BB_CL_MAP_3_B0_CL_MAP_3_LSB 0
-#define PHY_BB_CL_MAP_3_B0_CL_MAP_3_MASK 0xffffffff
-#define PHY_BB_CL_MAP_3_B0_CL_MAP_3_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_CL_MAP_3_B0_CL_MAP_3_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_cl_cal_ctrl */
-#define PHY_BB_CL_CAL_CTRL_ADDRESS 0x0000a358
-#define PHY_BB_CL_CAL_CTRL_OFFSET 0x0000a358
-#define PHY_BB_CL_CAL_CTRL_ENABLE_PARALLEL_CAL_MSB 0
-#define PHY_BB_CL_CAL_CTRL_ENABLE_PARALLEL_CAL_LSB 0
-#define PHY_BB_CL_CAL_CTRL_ENABLE_PARALLEL_CAL_MASK 0x00000001
-#define PHY_BB_CL_CAL_CTRL_ENABLE_PARALLEL_CAL_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_BB_CL_CAL_CTRL_ENABLE_PARALLEL_CAL_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_BB_CL_CAL_CTRL_ENABLE_CL_CALIBRATE_MSB 1
-#define PHY_BB_CL_CAL_CTRL_ENABLE_CL_CALIBRATE_LSB 1
-#define PHY_BB_CL_CAL_CTRL_ENABLE_CL_CALIBRATE_MASK 0x00000002
-#define PHY_BB_CL_CAL_CTRL_ENABLE_CL_CALIBRATE_GET(x) (((x) & 0x00000002) >> 1)
-#define PHY_BB_CL_CAL_CTRL_ENABLE_CL_CALIBRATE_SET(x) (((x) << 1) & 0x00000002)
-#define PHY_BB_CL_CAL_CTRL_CF_CLC_TEST_POINT_MSB 3
-#define PHY_BB_CL_CAL_CTRL_CF_CLC_TEST_POINT_LSB 2
-#define PHY_BB_CL_CAL_CTRL_CF_CLC_TEST_POINT_MASK 0x0000000c
-#define PHY_BB_CL_CAL_CTRL_CF_CLC_TEST_POINT_GET(x) (((x) & 0x0000000c) >> 2)
-#define PHY_BB_CL_CAL_CTRL_CF_CLC_TEST_POINT_SET(x) (((x) << 2) & 0x0000000c)
-#define PHY_BB_CL_CAL_CTRL_CF_CLC_FORCED_PAGAIN_MSB 7
-#define PHY_BB_CL_CAL_CTRL_CF_CLC_FORCED_PAGAIN_LSB 4
-#define PHY_BB_CL_CAL_CTRL_CF_CLC_FORCED_PAGAIN_MASK 0x000000f0
-#define PHY_BB_CL_CAL_CTRL_CF_CLC_FORCED_PAGAIN_GET(x) (((x) & 0x000000f0) >> 4)
-#define PHY_BB_CL_CAL_CTRL_CF_CLC_FORCED_PAGAIN_SET(x) (((x) << 4) & 0x000000f0)
-#define PHY_BB_CL_CAL_CTRL_CARR_LEAK_MAX_OFFSET_MSB 15
-#define PHY_BB_CL_CAL_CTRL_CARR_LEAK_MAX_OFFSET_LSB 8
-#define PHY_BB_CL_CAL_CTRL_CARR_LEAK_MAX_OFFSET_MASK 0x0000ff00
-#define PHY_BB_CL_CAL_CTRL_CARR_LEAK_MAX_OFFSET_GET(x) (((x) & 0x0000ff00) >> 8)
-#define PHY_BB_CL_CAL_CTRL_CARR_LEAK_MAX_OFFSET_SET(x) (((x) << 8) & 0x0000ff00)
-#define PHY_BB_CL_CAL_CTRL_CF_CLC_INIT_BBGAIN_MSB 21
-#define PHY_BB_CL_CAL_CTRL_CF_CLC_INIT_BBGAIN_LSB 16
-#define PHY_BB_CL_CAL_CTRL_CF_CLC_INIT_BBGAIN_MASK 0x003f0000
-#define PHY_BB_CL_CAL_CTRL_CF_CLC_INIT_BBGAIN_GET(x) (((x) & 0x003f0000) >> 16)
-#define PHY_BB_CL_CAL_CTRL_CF_CLC_INIT_BBGAIN_SET(x) (((x) << 16) & 0x003f0000)
-#define PHY_BB_CL_CAL_CTRL_CF_ADC_BOUND_MSB 29
-#define PHY_BB_CL_CAL_CTRL_CF_ADC_BOUND_LSB 22
-#define PHY_BB_CL_CAL_CTRL_CF_ADC_BOUND_MASK 0x3fc00000
-#define PHY_BB_CL_CAL_CTRL_CF_ADC_BOUND_GET(x) (((x) & 0x3fc00000) >> 22)
-#define PHY_BB_CL_CAL_CTRL_CF_ADC_BOUND_SET(x) (((x) << 22) & 0x3fc00000)
-#define PHY_BB_CL_CAL_CTRL_USE_DAC_CL_CORRECTION_MSB 30
-#define PHY_BB_CL_CAL_CTRL_USE_DAC_CL_CORRECTION_LSB 30
-#define PHY_BB_CL_CAL_CTRL_USE_DAC_CL_CORRECTION_MASK 0x40000000
-#define PHY_BB_CL_CAL_CTRL_USE_DAC_CL_CORRECTION_GET(x) (((x) & 0x40000000) >> 30)
-#define PHY_BB_CL_CAL_CTRL_USE_DAC_CL_CORRECTION_SET(x) (((x) << 30) & 0x40000000)
-#define PHY_BB_CL_CAL_CTRL_CL_MAP_HW_GEN_MSB 31
-#define PHY_BB_CL_CAL_CTRL_CL_MAP_HW_GEN_LSB 31
-#define PHY_BB_CL_CAL_CTRL_CL_MAP_HW_GEN_MASK 0x80000000
-#define PHY_BB_CL_CAL_CTRL_CL_MAP_HW_GEN_GET(x) (((x) & 0x80000000) >> 31)
-#define PHY_BB_CL_CAL_CTRL_CL_MAP_HW_GEN_SET(x) (((x) << 31) & 0x80000000)
-
-/* macros for BB_cl_map_pal_0_b0 */
-#define PHY_BB_CL_MAP_PAL_0_B0_ADDRESS 0x0000a35c
-#define PHY_BB_CL_MAP_PAL_0_B0_OFFSET 0x0000a35c
-#define PHY_BB_CL_MAP_PAL_0_B0_CL_MAP_0_MSB 31
-#define PHY_BB_CL_MAP_PAL_0_B0_CL_MAP_0_LSB 0
-#define PHY_BB_CL_MAP_PAL_0_B0_CL_MAP_0_MASK 0xffffffff
-#define PHY_BB_CL_MAP_PAL_0_B0_CL_MAP_0_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_CL_MAP_PAL_0_B0_CL_MAP_0_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_cl_map_pal_1_b0 */
-#define PHY_BB_CL_MAP_PAL_1_B0_ADDRESS 0x0000a360
-#define PHY_BB_CL_MAP_PAL_1_B0_OFFSET 0x0000a360
-#define PHY_BB_CL_MAP_PAL_1_B0_CL_MAP_1_MSB 31
-#define PHY_BB_CL_MAP_PAL_1_B0_CL_MAP_1_LSB 0
-#define PHY_BB_CL_MAP_PAL_1_B0_CL_MAP_1_MASK 0xffffffff
-#define PHY_BB_CL_MAP_PAL_1_B0_CL_MAP_1_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_CL_MAP_PAL_1_B0_CL_MAP_1_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_cl_map_pal_2_b0 */
-#define PHY_BB_CL_MAP_PAL_2_B0_ADDRESS 0x0000a364
-#define PHY_BB_CL_MAP_PAL_2_B0_OFFSET 0x0000a364
-#define PHY_BB_CL_MAP_PAL_2_B0_CL_MAP_2_MSB 31
-#define PHY_BB_CL_MAP_PAL_2_B0_CL_MAP_2_LSB 0
-#define PHY_BB_CL_MAP_PAL_2_B0_CL_MAP_2_MASK 0xffffffff
-#define PHY_BB_CL_MAP_PAL_2_B0_CL_MAP_2_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_CL_MAP_PAL_2_B0_CL_MAP_2_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_cl_map_pal_3_b0 */
-#define PHY_BB_CL_MAP_PAL_3_B0_ADDRESS 0x0000a368
-#define PHY_BB_CL_MAP_PAL_3_B0_OFFSET 0x0000a368
-#define PHY_BB_CL_MAP_PAL_3_B0_CL_MAP_3_MSB 31
-#define PHY_BB_CL_MAP_PAL_3_B0_CL_MAP_3_LSB 0
-#define PHY_BB_CL_MAP_PAL_3_B0_CL_MAP_3_MASK 0xffffffff
-#define PHY_BB_CL_MAP_PAL_3_B0_CL_MAP_3_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_CL_MAP_PAL_3_B0_CL_MAP_3_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_rifs */
-#define PHY_BB_RIFS_ADDRESS 0x0000a388
-#define PHY_BB_RIFS_OFFSET 0x0000a388
-#define PHY_BB_RIFS_DISABLE_FCC_FIX_MSB 25
-#define PHY_BB_RIFS_DISABLE_FCC_FIX_LSB 25
-#define PHY_BB_RIFS_DISABLE_FCC_FIX_MASK 0x02000000
-#define PHY_BB_RIFS_DISABLE_FCC_FIX_GET(x) (((x) & 0x02000000) >> 25)
-#define PHY_BB_RIFS_DISABLE_FCC_FIX_SET(x) (((x) << 25) & 0x02000000)
-#define PHY_BB_RIFS_ENABLE_RESET_TDOMAIN_MSB 26
-#define PHY_BB_RIFS_ENABLE_RESET_TDOMAIN_LSB 26
-#define PHY_BB_RIFS_ENABLE_RESET_TDOMAIN_MASK 0x04000000
-#define PHY_BB_RIFS_ENABLE_RESET_TDOMAIN_GET(x) (((x) & 0x04000000) >> 26)
-#define PHY_BB_RIFS_ENABLE_RESET_TDOMAIN_SET(x) (((x) << 26) & 0x04000000)
-#define PHY_BB_RIFS_DISABLE_FCC_FIX2_MSB 27
-#define PHY_BB_RIFS_DISABLE_FCC_FIX2_LSB 27
-#define PHY_BB_RIFS_DISABLE_FCC_FIX2_MASK 0x08000000
-#define PHY_BB_RIFS_DISABLE_FCC_FIX2_GET(x) (((x) & 0x08000000) >> 27)
-#define PHY_BB_RIFS_DISABLE_FCC_FIX2_SET(x) (((x) << 27) & 0x08000000)
-#define PHY_BB_RIFS_DISABLE_RIFS_CCK_FIX_MSB 28
-#define PHY_BB_RIFS_DISABLE_RIFS_CCK_FIX_LSB 28
-#define PHY_BB_RIFS_DISABLE_RIFS_CCK_FIX_MASK 0x10000000
-#define PHY_BB_RIFS_DISABLE_RIFS_CCK_FIX_GET(x) (((x) & 0x10000000) >> 28)
-#define PHY_BB_RIFS_DISABLE_RIFS_CCK_FIX_SET(x) (((x) << 28) & 0x10000000)
-#define PHY_BB_RIFS_DISABLE_ERROR_RESET_FIX_MSB 29
-#define PHY_BB_RIFS_DISABLE_ERROR_RESET_FIX_LSB 29
-#define PHY_BB_RIFS_DISABLE_ERROR_RESET_FIX_MASK 0x20000000
-#define PHY_BB_RIFS_DISABLE_ERROR_RESET_FIX_GET(x) (((x) & 0x20000000) >> 29)
-#define PHY_BB_RIFS_DISABLE_ERROR_RESET_FIX_SET(x) (((x) << 29) & 0x20000000)
-#define PHY_BB_RIFS_RADAR_USE_FDOMAIN_RESET_MSB 30
-#define PHY_BB_RIFS_RADAR_USE_FDOMAIN_RESET_LSB 30
-#define PHY_BB_RIFS_RADAR_USE_FDOMAIN_RESET_MASK 0x40000000
-#define PHY_BB_RIFS_RADAR_USE_FDOMAIN_RESET_GET(x) (((x) & 0x40000000) >> 30)
-#define PHY_BB_RIFS_RADAR_USE_FDOMAIN_RESET_SET(x) (((x) << 30) & 0x40000000)
-
-/* macros for BB_powertx_rate5 */
-#define PHY_BB_POWERTX_RATE5_ADDRESS 0x0000a38c
-#define PHY_BB_POWERTX_RATE5_OFFSET 0x0000a38c
-#define PHY_BB_POWERTX_RATE5_POWERTXHT20_0_MSB 5
-#define PHY_BB_POWERTX_RATE5_POWERTXHT20_0_LSB 0
-#define PHY_BB_POWERTX_RATE5_POWERTXHT20_0_MASK 0x0000003f
-#define PHY_BB_POWERTX_RATE5_POWERTXHT20_0_GET(x) (((x) & 0x0000003f) >> 0)
-#define PHY_BB_POWERTX_RATE5_POWERTXHT20_0_SET(x) (((x) << 0) & 0x0000003f)
-#define PHY_BB_POWERTX_RATE5_POWERTXHT20_1_MSB 13
-#define PHY_BB_POWERTX_RATE5_POWERTXHT20_1_LSB 8
-#define PHY_BB_POWERTX_RATE5_POWERTXHT20_1_MASK 0x00003f00
-#define PHY_BB_POWERTX_RATE5_POWERTXHT20_1_GET(x) (((x) & 0x00003f00) >> 8)
-#define PHY_BB_POWERTX_RATE5_POWERTXHT20_1_SET(x) (((x) << 8) & 0x00003f00)
-#define PHY_BB_POWERTX_RATE5_POWERTXHT20_2_MSB 21
-#define PHY_BB_POWERTX_RATE5_POWERTXHT20_2_LSB 16
-#define PHY_BB_POWERTX_RATE5_POWERTXHT20_2_MASK 0x003f0000
-#define PHY_BB_POWERTX_RATE5_POWERTXHT20_2_GET(x) (((x) & 0x003f0000) >> 16)
-#define PHY_BB_POWERTX_RATE5_POWERTXHT20_2_SET(x) (((x) << 16) & 0x003f0000)
-#define PHY_BB_POWERTX_RATE5_POWERTXHT20_3_MSB 29
-#define PHY_BB_POWERTX_RATE5_POWERTXHT20_3_LSB 24
-#define PHY_BB_POWERTX_RATE5_POWERTXHT20_3_MASK 0x3f000000
-#define PHY_BB_POWERTX_RATE5_POWERTXHT20_3_GET(x) (((x) & 0x3f000000) >> 24)
-#define PHY_BB_POWERTX_RATE5_POWERTXHT20_3_SET(x) (((x) << 24) & 0x3f000000)
-
-/* macros for BB_powertx_rate6 */
-#define PHY_BB_POWERTX_RATE6_ADDRESS 0x0000a390
-#define PHY_BB_POWERTX_RATE6_OFFSET 0x0000a390
-#define PHY_BB_POWERTX_RATE6_POWERTXHT20_4_MSB 5
-#define PHY_BB_POWERTX_RATE6_POWERTXHT20_4_LSB 0
-#define PHY_BB_POWERTX_RATE6_POWERTXHT20_4_MASK 0x0000003f
-#define PHY_BB_POWERTX_RATE6_POWERTXHT20_4_GET(x) (((x) & 0x0000003f) >> 0)
-#define PHY_BB_POWERTX_RATE6_POWERTXHT20_4_SET(x) (((x) << 0) & 0x0000003f)
-#define PHY_BB_POWERTX_RATE6_POWERTXHT20_5_MSB 13
-#define PHY_BB_POWERTX_RATE6_POWERTXHT20_5_LSB 8
-#define PHY_BB_POWERTX_RATE6_POWERTXHT20_5_MASK 0x00003f00
-#define PHY_BB_POWERTX_RATE6_POWERTXHT20_5_GET(x) (((x) & 0x00003f00) >> 8)
-#define PHY_BB_POWERTX_RATE6_POWERTXHT20_5_SET(x) (((x) << 8) & 0x00003f00)
-#define PHY_BB_POWERTX_RATE6_POWERTXHT20_6_MSB 21
-#define PHY_BB_POWERTX_RATE6_POWERTXHT20_6_LSB 16
-#define PHY_BB_POWERTX_RATE6_POWERTXHT20_6_MASK 0x003f0000
-#define PHY_BB_POWERTX_RATE6_POWERTXHT20_6_GET(x) (((x) & 0x003f0000) >> 16)
-#define PHY_BB_POWERTX_RATE6_POWERTXHT20_6_SET(x) (((x) << 16) & 0x003f0000)
-#define PHY_BB_POWERTX_RATE6_POWERTXHT20_7_MSB 29
-#define PHY_BB_POWERTX_RATE6_POWERTXHT20_7_LSB 24
-#define PHY_BB_POWERTX_RATE6_POWERTXHT20_7_MASK 0x3f000000
-#define PHY_BB_POWERTX_RATE6_POWERTXHT20_7_GET(x) (((x) & 0x3f000000) >> 24)
-#define PHY_BB_POWERTX_RATE6_POWERTXHT20_7_SET(x) (((x) << 24) & 0x3f000000)
-
-/* macros for BB_tpc_10 */
-#define PHY_BB_TPC_10_ADDRESS 0x0000a394
-#define PHY_BB_TPC_10_OFFSET 0x0000a394
-#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_0_MSB 4
-#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_0_LSB 0
-#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_0_MASK 0x0000001f
-#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_0_GET(x) (((x) & 0x0000001f) >> 0)
-#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_0_SET(x) (((x) << 0) & 0x0000001f)
-#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_1_MSB 9
-#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_1_LSB 5
-#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_1_MASK 0x000003e0
-#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_1_GET(x) (((x) & 0x000003e0) >> 5)
-#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_1_SET(x) (((x) << 5) & 0x000003e0)
-#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_2_MSB 14
-#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_2_LSB 10
-#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_2_MASK 0x00007c00
-#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_2_GET(x) (((x) & 0x00007c00) >> 10)
-#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_2_SET(x) (((x) << 10) & 0x00007c00)
-#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_3_MSB 19
-#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_3_LSB 15
-#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_3_MASK 0x000f8000
-#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_3_GET(x) (((x) & 0x000f8000) >> 15)
-#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_3_SET(x) (((x) << 15) & 0x000f8000)
-#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_4_MSB 24
-#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_4_LSB 20
-#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_4_MASK 0x01f00000
-#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_4_GET(x) (((x) & 0x01f00000) >> 20)
-#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_4_SET(x) (((x) << 20) & 0x01f00000)
-#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_5_MSB 29
-#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_5_LSB 25
-#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_5_MASK 0x3e000000
-#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_5_GET(x) (((x) & 0x3e000000) >> 25)
-#define PHY_BB_TPC_10_DESIRED_SCALE_HT20_5_SET(x) (((x) << 25) & 0x3e000000)
-
-/* macros for BB_tpc_11_b0 */
-#define PHY_BB_TPC_11_B0_ADDRESS 0x0000a398
-#define PHY_BB_TPC_11_B0_OFFSET 0x0000a398
-#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_6_MSB 4
-#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_6_LSB 0
-#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_6_MASK 0x0000001f
-#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_6_GET(x) (((x) & 0x0000001f) >> 0)
-#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_6_SET(x) (((x) << 0) & 0x0000001f)
-#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_7_MSB 9
-#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_7_LSB 5
-#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_7_MASK 0x000003e0
-#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_7_GET(x) (((x) & 0x000003e0) >> 5)
-#define PHY_BB_TPC_11_B0_DESIRED_SCALE_HT20_7_SET(x) (((x) << 5) & 0x000003e0)
-#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_MSB 23
-#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_LSB 16
-#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_MASK 0x00ff0000
-#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_GET(x) (((x) & 0x00ff0000) >> 16)
-#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_SET(x) (((x) << 16) & 0x00ff0000)
-#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_PAL_ON_MSB 31
-#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_PAL_ON_LSB 24
-#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_PAL_ON_MASK 0xff000000
-#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_PAL_ON_GET(x) (((x) & 0xff000000) >> 24)
-#define PHY_BB_TPC_11_B0_OLPC_GAIN_DELTA_0_PAL_ON_SET(x) (((x) << 24) & 0xff000000)
-
-/* macros for BB_cal_chain_mask */
-#define PHY_BB_CAL_CHAIN_MASK_ADDRESS 0x0000a39c
-#define PHY_BB_CAL_CHAIN_MASK_OFFSET 0x0000a39c
-#define PHY_BB_CAL_CHAIN_MASK_CAL_CHAIN_MASK_MSB 2
-#define PHY_BB_CAL_CHAIN_MASK_CAL_CHAIN_MASK_LSB 0
-#define PHY_BB_CAL_CHAIN_MASK_CAL_CHAIN_MASK_MASK 0x00000007
-#define PHY_BB_CAL_CHAIN_MASK_CAL_CHAIN_MASK_GET(x) (((x) & 0x00000007) >> 0)
-#define PHY_BB_CAL_CHAIN_MASK_CAL_CHAIN_MASK_SET(x) (((x) << 0) & 0x00000007)
-
-/* macros for BB_powertx_sub */
-#define PHY_BB_POWERTX_SUB_ADDRESS 0x0000a3bc
-#define PHY_BB_POWERTX_SUB_OFFSET 0x0000a3bc
-#define PHY_BB_POWERTX_SUB_POWERTX_SUB_FOR_2CHAIN_MSB 5
-#define PHY_BB_POWERTX_SUB_POWERTX_SUB_FOR_2CHAIN_LSB 0
-#define PHY_BB_POWERTX_SUB_POWERTX_SUB_FOR_2CHAIN_MASK 0x0000003f
-#define PHY_BB_POWERTX_SUB_POWERTX_SUB_FOR_2CHAIN_GET(x) (((x) & 0x0000003f) >> 0)
-#define PHY_BB_POWERTX_SUB_POWERTX_SUB_FOR_2CHAIN_SET(x) (((x) << 0) & 0x0000003f)
-
-/* macros for BB_powertx_rate7 */
-#define PHY_BB_POWERTX_RATE7_ADDRESS 0x0000a3c0
-#define PHY_BB_POWERTX_RATE7_OFFSET 0x0000a3c0
-#define PHY_BB_POWERTX_RATE7_POWERTXHT40_0_MSB 5
-#define PHY_BB_POWERTX_RATE7_POWERTXHT40_0_LSB 0
-#define PHY_BB_POWERTX_RATE7_POWERTXHT40_0_MASK 0x0000003f
-#define PHY_BB_POWERTX_RATE7_POWERTXHT40_0_GET(x) (((x) & 0x0000003f) >> 0)
-#define PHY_BB_POWERTX_RATE7_POWERTXHT40_0_SET(x) (((x) << 0) & 0x0000003f)
-#define PHY_BB_POWERTX_RATE7_POWERTXHT40_1_MSB 13
-#define PHY_BB_POWERTX_RATE7_POWERTXHT40_1_LSB 8
-#define PHY_BB_POWERTX_RATE7_POWERTXHT40_1_MASK 0x00003f00
-#define PHY_BB_POWERTX_RATE7_POWERTXHT40_1_GET(x) (((x) & 0x00003f00) >> 8)
-#define PHY_BB_POWERTX_RATE7_POWERTXHT40_1_SET(x) (((x) << 8) & 0x00003f00)
-#define PHY_BB_POWERTX_RATE7_POWERTXHT40_2_MSB 21
-#define PHY_BB_POWERTX_RATE7_POWERTXHT40_2_LSB 16
-#define PHY_BB_POWERTX_RATE7_POWERTXHT40_2_MASK 0x003f0000
-#define PHY_BB_POWERTX_RATE7_POWERTXHT40_2_GET(x) (((x) & 0x003f0000) >> 16)
-#define PHY_BB_POWERTX_RATE7_POWERTXHT40_2_SET(x) (((x) << 16) & 0x003f0000)
-#define PHY_BB_POWERTX_RATE7_POWERTXHT40_3_MSB 29
-#define PHY_BB_POWERTX_RATE7_POWERTXHT40_3_LSB 24
-#define PHY_BB_POWERTX_RATE7_POWERTXHT40_3_MASK 0x3f000000
-#define PHY_BB_POWERTX_RATE7_POWERTXHT40_3_GET(x) (((x) & 0x3f000000) >> 24)
-#define PHY_BB_POWERTX_RATE7_POWERTXHT40_3_SET(x) (((x) << 24) & 0x3f000000)
-
-/* macros for BB_powertx_rate8 */
-#define PHY_BB_POWERTX_RATE8_ADDRESS 0x0000a3c4
-#define PHY_BB_POWERTX_RATE8_OFFSET 0x0000a3c4
-#define PHY_BB_POWERTX_RATE8_POWERTXHT40_4_MSB 5
-#define PHY_BB_POWERTX_RATE8_POWERTXHT40_4_LSB 0
-#define PHY_BB_POWERTX_RATE8_POWERTXHT40_4_MASK 0x0000003f
-#define PHY_BB_POWERTX_RATE8_POWERTXHT40_4_GET(x) (((x) & 0x0000003f) >> 0)
-#define PHY_BB_POWERTX_RATE8_POWERTXHT40_4_SET(x) (((x) << 0) & 0x0000003f)
-#define PHY_BB_POWERTX_RATE8_POWERTXHT40_5_MSB 13
-#define PHY_BB_POWERTX_RATE8_POWERTXHT40_5_LSB 8
-#define PHY_BB_POWERTX_RATE8_POWERTXHT40_5_MASK 0x00003f00
-#define PHY_BB_POWERTX_RATE8_POWERTXHT40_5_GET(x) (((x) & 0x00003f00) >> 8)
-#define PHY_BB_POWERTX_RATE8_POWERTXHT40_5_SET(x) (((x) << 8) & 0x00003f00)
-#define PHY_BB_POWERTX_RATE8_POWERTXHT40_6_MSB 21
-#define PHY_BB_POWERTX_RATE8_POWERTXHT40_6_LSB 16
-#define PHY_BB_POWERTX_RATE8_POWERTXHT40_6_MASK 0x003f0000
-#define PHY_BB_POWERTX_RATE8_POWERTXHT40_6_GET(x) (((x) & 0x003f0000) >> 16)
-#define PHY_BB_POWERTX_RATE8_POWERTXHT40_6_SET(x) (((x) << 16) & 0x003f0000)
-#define PHY_BB_POWERTX_RATE8_POWERTXHT40_7_MSB 29
-#define PHY_BB_POWERTX_RATE8_POWERTXHT40_7_LSB 24
-#define PHY_BB_POWERTX_RATE8_POWERTXHT40_7_MASK 0x3f000000
-#define PHY_BB_POWERTX_RATE8_POWERTXHT40_7_GET(x) (((x) & 0x3f000000) >> 24)
-#define PHY_BB_POWERTX_RATE8_POWERTXHT40_7_SET(x) (((x) << 24) & 0x3f000000)
-
-/* macros for BB_powertx_rate9 */
-#define PHY_BB_POWERTX_RATE9_ADDRESS 0x0000a3c8
-#define PHY_BB_POWERTX_RATE9_OFFSET 0x0000a3c8
-#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_CCK_MSB 5
-#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_CCK_LSB 0
-#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_CCK_MASK 0x0000003f
-#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_CCK_GET(x) (((x) & 0x0000003f) >> 0)
-#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_CCK_SET(x) (((x) << 0) & 0x0000003f)
-#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_OFDM_MSB 13
-#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_OFDM_LSB 8
-#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_OFDM_MASK 0x00003f00
-#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_OFDM_GET(x) (((x) & 0x00003f00) >> 8)
-#define PHY_BB_POWERTX_RATE9_POWERTX_DUP40_OFDM_SET(x) (((x) << 8) & 0x00003f00)
-#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_CCK_MSB 21
-#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_CCK_LSB 16
-#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_CCK_MASK 0x003f0000
-#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_CCK_GET(x) (((x) & 0x003f0000) >> 16)
-#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_CCK_SET(x) (((x) << 16) & 0x003f0000)
-#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_OFDM_MSB 29
-#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_OFDM_LSB 24
-#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_OFDM_MASK 0x3f000000
-#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_OFDM_GET(x) (((x) & 0x3f000000) >> 24)
-#define PHY_BB_POWERTX_RATE9_POWERTX_EXT20_OFDM_SET(x) (((x) << 24) & 0x3f000000)
-
-/* macros for BB_powertx_rate10 */
-#define PHY_BB_POWERTX_RATE10_ADDRESS 0x0000a3cc
-#define PHY_BB_POWERTX_RATE10_OFFSET 0x0000a3cc
-#define PHY_BB_POWERTX_RATE10_POWERTXHT20_8_MSB 5
-#define PHY_BB_POWERTX_RATE10_POWERTXHT20_8_LSB 0
-#define PHY_BB_POWERTX_RATE10_POWERTXHT20_8_MASK 0x0000003f
-#define PHY_BB_POWERTX_RATE10_POWERTXHT20_8_GET(x) (((x) & 0x0000003f) >> 0)
-#define PHY_BB_POWERTX_RATE10_POWERTXHT20_8_SET(x) (((x) << 0) & 0x0000003f)
-#define PHY_BB_POWERTX_RATE10_POWERTXHT20_9_MSB 13
-#define PHY_BB_POWERTX_RATE10_POWERTXHT20_9_LSB 8
-#define PHY_BB_POWERTX_RATE10_POWERTXHT20_9_MASK 0x00003f00
-#define PHY_BB_POWERTX_RATE10_POWERTXHT20_9_GET(x) (((x) & 0x00003f00) >> 8)
-#define PHY_BB_POWERTX_RATE10_POWERTXHT20_9_SET(x) (((x) << 8) & 0x00003f00)
-#define PHY_BB_POWERTX_RATE10_POWERTXHT20_10_MSB 21
-#define PHY_BB_POWERTX_RATE10_POWERTXHT20_10_LSB 16
-#define PHY_BB_POWERTX_RATE10_POWERTXHT20_10_MASK 0x003f0000
-#define PHY_BB_POWERTX_RATE10_POWERTXHT20_10_GET(x) (((x) & 0x003f0000) >> 16)
-#define PHY_BB_POWERTX_RATE10_POWERTXHT20_10_SET(x) (((x) << 16) & 0x003f0000)
-#define PHY_BB_POWERTX_RATE10_POWERTXHT20_11_MSB 29
-#define PHY_BB_POWERTX_RATE10_POWERTXHT20_11_LSB 24
-#define PHY_BB_POWERTX_RATE10_POWERTXHT20_11_MASK 0x3f000000
-#define PHY_BB_POWERTX_RATE10_POWERTXHT20_11_GET(x) (((x) & 0x3f000000) >> 24)
-#define PHY_BB_POWERTX_RATE10_POWERTXHT20_11_SET(x) (((x) << 24) & 0x3f000000)
-
-/* macros for BB_powertx_rate11 */
-#define PHY_BB_POWERTX_RATE11_ADDRESS 0x0000a3d0
-#define PHY_BB_POWERTX_RATE11_OFFSET 0x0000a3d0
-#define PHY_BB_POWERTX_RATE11_POWERTXHT20_12_MSB 5
-#define PHY_BB_POWERTX_RATE11_POWERTXHT20_12_LSB 0
-#define PHY_BB_POWERTX_RATE11_POWERTXHT20_12_MASK 0x0000003f
-#define PHY_BB_POWERTX_RATE11_POWERTXHT20_12_GET(x) (((x) & 0x0000003f) >> 0)
-#define PHY_BB_POWERTX_RATE11_POWERTXHT20_12_SET(x) (((x) << 0) & 0x0000003f)
-#define PHY_BB_POWERTX_RATE11_POWERTXHT20_13_MSB 13
-#define PHY_BB_POWERTX_RATE11_POWERTXHT20_13_LSB 8
-#define PHY_BB_POWERTX_RATE11_POWERTXHT20_13_MASK 0x00003f00
-#define PHY_BB_POWERTX_RATE11_POWERTXHT20_13_GET(x) (((x) & 0x00003f00) >> 8)
-#define PHY_BB_POWERTX_RATE11_POWERTXHT20_13_SET(x) (((x) << 8) & 0x00003f00)
-#define PHY_BB_POWERTX_RATE11_POWERTXHT40_12_MSB 21
-#define PHY_BB_POWERTX_RATE11_POWERTXHT40_12_LSB 16
-#define PHY_BB_POWERTX_RATE11_POWERTXHT40_12_MASK 0x003f0000
-#define PHY_BB_POWERTX_RATE11_POWERTXHT40_12_GET(x) (((x) & 0x003f0000) >> 16)
-#define PHY_BB_POWERTX_RATE11_POWERTXHT40_12_SET(x) (((x) << 16) & 0x003f0000)
-#define PHY_BB_POWERTX_RATE11_POWERTXHT40_13_MSB 29
-#define PHY_BB_POWERTX_RATE11_POWERTXHT40_13_LSB 24
-#define PHY_BB_POWERTX_RATE11_POWERTXHT40_13_MASK 0x3f000000
-#define PHY_BB_POWERTX_RATE11_POWERTXHT40_13_GET(x) (((x) & 0x3f000000) >> 24)
-#define PHY_BB_POWERTX_RATE11_POWERTXHT40_13_SET(x) (((x) << 24) & 0x3f000000)
-
-/* macros for BB_powertx_rate12 */
-#define PHY_BB_POWERTX_RATE12_ADDRESS 0x0000a3d4
-#define PHY_BB_POWERTX_RATE12_OFFSET 0x0000a3d4
-#define PHY_BB_POWERTX_RATE12_POWERTXHT40_8_MSB 5
-#define PHY_BB_POWERTX_RATE12_POWERTXHT40_8_LSB 0
-#define PHY_BB_POWERTX_RATE12_POWERTXHT40_8_MASK 0x0000003f
-#define PHY_BB_POWERTX_RATE12_POWERTXHT40_8_GET(x) (((x) & 0x0000003f) >> 0)
-#define PHY_BB_POWERTX_RATE12_POWERTXHT40_8_SET(x) (((x) << 0) & 0x0000003f)
-#define PHY_BB_POWERTX_RATE12_POWERTXHT40_9_MSB 13
-#define PHY_BB_POWERTX_RATE12_POWERTXHT40_9_LSB 8
-#define PHY_BB_POWERTX_RATE12_POWERTXHT40_9_MASK 0x00003f00
-#define PHY_BB_POWERTX_RATE12_POWERTXHT40_9_GET(x) (((x) & 0x00003f00) >> 8)
-#define PHY_BB_POWERTX_RATE12_POWERTXHT40_9_SET(x) (((x) << 8) & 0x00003f00)
-#define PHY_BB_POWERTX_RATE12_POWERTXHT40_10_MSB 21
-#define PHY_BB_POWERTX_RATE12_POWERTXHT40_10_LSB 16
-#define PHY_BB_POWERTX_RATE12_POWERTXHT40_10_MASK 0x003f0000
-#define PHY_BB_POWERTX_RATE12_POWERTXHT40_10_GET(x) (((x) & 0x003f0000) >> 16)
-#define PHY_BB_POWERTX_RATE12_POWERTXHT40_10_SET(x) (((x) << 16) & 0x003f0000)
-#define PHY_BB_POWERTX_RATE12_POWERTXHT40_11_MSB 29
-#define PHY_BB_POWERTX_RATE12_POWERTXHT40_11_LSB 24
-#define PHY_BB_POWERTX_RATE12_POWERTXHT40_11_MASK 0x3f000000
-#define PHY_BB_POWERTX_RATE12_POWERTXHT40_11_GET(x) (((x) & 0x3f000000) >> 24)
-#define PHY_BB_POWERTX_RATE12_POWERTXHT40_11_SET(x) (((x) << 24) & 0x3f000000)
-
-/* macros for BB_force_analog */
-#define PHY_BB_FORCE_ANALOG_ADDRESS 0x0000a3d8
-#define PHY_BB_FORCE_ANALOG_OFFSET 0x0000a3d8
-#define PHY_BB_FORCE_ANALOG_FORCE_XPAON_MSB 0
-#define PHY_BB_FORCE_ANALOG_FORCE_XPAON_LSB 0
-#define PHY_BB_FORCE_ANALOG_FORCE_XPAON_MASK 0x00000001
-#define PHY_BB_FORCE_ANALOG_FORCE_XPAON_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_BB_FORCE_ANALOG_FORCE_XPAON_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_BB_FORCE_ANALOG_FORCED_XPAON_MSB 3
-#define PHY_BB_FORCE_ANALOG_FORCED_XPAON_LSB 1
-#define PHY_BB_FORCE_ANALOG_FORCED_XPAON_MASK 0x0000000e
-#define PHY_BB_FORCE_ANALOG_FORCED_XPAON_GET(x) (((x) & 0x0000000e) >> 1)
-#define PHY_BB_FORCE_ANALOG_FORCED_XPAON_SET(x) (((x) << 1) & 0x0000000e)
-#define PHY_BB_FORCE_ANALOG_FORCE_PDADC_PWD_MSB 4
-#define PHY_BB_FORCE_ANALOG_FORCE_PDADC_PWD_LSB 4
-#define PHY_BB_FORCE_ANALOG_FORCE_PDADC_PWD_MASK 0x00000010
-#define PHY_BB_FORCE_ANALOG_FORCE_PDADC_PWD_GET(x) (((x) & 0x00000010) >> 4)
-#define PHY_BB_FORCE_ANALOG_FORCE_PDADC_PWD_SET(x) (((x) << 4) & 0x00000010)
-#define PHY_BB_FORCE_ANALOG_FORCED_PDADC_PWD_MSB 7
-#define PHY_BB_FORCE_ANALOG_FORCED_PDADC_PWD_LSB 5
-#define PHY_BB_FORCE_ANALOG_FORCED_PDADC_PWD_MASK 0x000000e0
-#define PHY_BB_FORCE_ANALOG_FORCED_PDADC_PWD_GET(x) (((x) & 0x000000e0) >> 5)
-#define PHY_BB_FORCE_ANALOG_FORCED_PDADC_PWD_SET(x) (((x) << 5) & 0x000000e0)
-
-/* macros for BB_tpc_12 */
-#define PHY_BB_TPC_12_ADDRESS 0x0000a3dc
-#define PHY_BB_TPC_12_OFFSET 0x0000a3dc
-#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_0_MSB 4
-#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_0_LSB 0
-#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_0_MASK 0x0000001f
-#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_0_GET(x) (((x) & 0x0000001f) >> 0)
-#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_0_SET(x) (((x) << 0) & 0x0000001f)
-#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_1_MSB 9
-#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_1_LSB 5
-#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_1_MASK 0x000003e0
-#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_1_GET(x) (((x) & 0x000003e0) >> 5)
-#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_1_SET(x) (((x) << 5) & 0x000003e0)
-#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_2_MSB 14
-#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_2_LSB 10
-#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_2_MASK 0x00007c00
-#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_2_GET(x) (((x) & 0x00007c00) >> 10)
-#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_2_SET(x) (((x) << 10) & 0x00007c00)
-#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_3_MSB 19
-#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_3_LSB 15
-#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_3_MASK 0x000f8000
-#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_3_GET(x) (((x) & 0x000f8000) >> 15)
-#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_3_SET(x) (((x) << 15) & 0x000f8000)
-#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_4_MSB 24
-#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_4_LSB 20
-#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_4_MASK 0x01f00000
-#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_4_GET(x) (((x) & 0x01f00000) >> 20)
-#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_4_SET(x) (((x) << 20) & 0x01f00000)
-#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_5_MSB 29
-#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_5_LSB 25
-#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_5_MASK 0x3e000000
-#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_5_GET(x) (((x) & 0x3e000000) >> 25)
-#define PHY_BB_TPC_12_DESIRED_SCALE_HT40_5_SET(x) (((x) << 25) & 0x3e000000)
-
-/* macros for BB_tpc_13 */
-#define PHY_BB_TPC_13_ADDRESS 0x0000a3e0
-#define PHY_BB_TPC_13_OFFSET 0x0000a3e0
-#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_6_MSB 4
-#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_6_LSB 0
-#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_6_MASK 0x0000001f
-#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_6_GET(x) (((x) & 0x0000001f) >> 0)
-#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_6_SET(x) (((x) << 0) & 0x0000001f)
-#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_7_MSB 9
-#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_7_LSB 5
-#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_7_MASK 0x000003e0
-#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_7_GET(x) (((x) & 0x000003e0) >> 5)
-#define PHY_BB_TPC_13_DESIRED_SCALE_HT40_7_SET(x) (((x) << 5) & 0x000003e0)
-
-/* macros for BB_tpc_14 */
-#define PHY_BB_TPC_14_ADDRESS 0x0000a3e4
-#define PHY_BB_TPC_14_OFFSET 0x0000a3e4
-#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_8_MSB 4
-#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_8_LSB 0
-#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_8_MASK 0x0000001f
-#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_8_GET(x) (((x) & 0x0000001f) >> 0)
-#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_8_SET(x) (((x) << 0) & 0x0000001f)
-#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_9_MSB 9
-#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_9_LSB 5
-#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_9_MASK 0x000003e0
-#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_9_GET(x) (((x) & 0x000003e0) >> 5)
-#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_9_SET(x) (((x) << 5) & 0x000003e0)
-#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_10_MSB 14
-#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_10_LSB 10
-#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_10_MASK 0x00007c00
-#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_10_GET(x) (((x) & 0x00007c00) >> 10)
-#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_10_SET(x) (((x) << 10) & 0x00007c00)
-#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_11_MSB 19
-#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_11_LSB 15
-#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_11_MASK 0x000f8000
-#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_11_GET(x) (((x) & 0x000f8000) >> 15)
-#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_11_SET(x) (((x) << 15) & 0x000f8000)
-#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_12_MSB 24
-#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_12_LSB 20
-#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_12_MASK 0x01f00000
-#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_12_GET(x) (((x) & 0x01f00000) >> 20)
-#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_12_SET(x) (((x) << 20) & 0x01f00000)
-#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_13_MSB 29
-#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_13_LSB 25
-#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_13_MASK 0x3e000000
-#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_13_GET(x) (((x) & 0x3e000000) >> 25)
-#define PHY_BB_TPC_14_DESIRED_SCALE_HT20_13_SET(x) (((x) << 25) & 0x3e000000)
-
-/* macros for BB_tpc_15 */
-#define PHY_BB_TPC_15_ADDRESS 0x0000a3e8
-#define PHY_BB_TPC_15_OFFSET 0x0000a3e8
-#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_8_MSB 4
-#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_8_LSB 0
-#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_8_MASK 0x0000001f
-#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_8_GET(x) (((x) & 0x0000001f) >> 0)
-#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_8_SET(x) (((x) << 0) & 0x0000001f)
-#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_9_MSB 9
-#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_9_LSB 5
-#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_9_MASK 0x000003e0
-#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_9_GET(x) (((x) & 0x000003e0) >> 5)
-#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_9_SET(x) (((x) << 5) & 0x000003e0)
-#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_10_MSB 14
-#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_10_LSB 10
-#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_10_MASK 0x00007c00
-#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_10_GET(x) (((x) & 0x00007c00) >> 10)
-#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_10_SET(x) (((x) << 10) & 0x00007c00)
-#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_11_MSB 19
-#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_11_LSB 15
-#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_11_MASK 0x000f8000
-#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_11_GET(x) (((x) & 0x000f8000) >> 15)
-#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_11_SET(x) (((x) << 15) & 0x000f8000)
-#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_12_MSB 24
-#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_12_LSB 20
-#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_12_MASK 0x01f00000
-#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_12_GET(x) (((x) & 0x01f00000) >> 20)
-#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_12_SET(x) (((x) << 20) & 0x01f00000)
-#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_13_MSB 29
-#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_13_LSB 25
-#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_13_MASK 0x3e000000
-#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_13_GET(x) (((x) & 0x3e000000) >> 25)
-#define PHY_BB_TPC_15_DESIRED_SCALE_HT40_13_SET(x) (((x) << 25) & 0x3e000000)
-
-/* macros for BB_tpc_16 */
-#define PHY_BB_TPC_16_ADDRESS 0x0000a3ec
-#define PHY_BB_TPC_16_OFFSET 0x0000a3ec
-#define PHY_BB_TPC_16_PDADC_PAR_CORR_CCK_MSB 13
-#define PHY_BB_TPC_16_PDADC_PAR_CORR_CCK_LSB 8
-#define PHY_BB_TPC_16_PDADC_PAR_CORR_CCK_MASK 0x00003f00
-#define PHY_BB_TPC_16_PDADC_PAR_CORR_CCK_GET(x) (((x) & 0x00003f00) >> 8)
-#define PHY_BB_TPC_16_PDADC_PAR_CORR_CCK_SET(x) (((x) << 8) & 0x00003f00)
-#define PHY_BB_TPC_16_PDADC_PAR_CORR_OFDM_MSB 21
-#define PHY_BB_TPC_16_PDADC_PAR_CORR_OFDM_LSB 16
-#define PHY_BB_TPC_16_PDADC_PAR_CORR_OFDM_MASK 0x003f0000
-#define PHY_BB_TPC_16_PDADC_PAR_CORR_OFDM_GET(x) (((x) & 0x003f0000) >> 16)
-#define PHY_BB_TPC_16_PDADC_PAR_CORR_OFDM_SET(x) (((x) << 16) & 0x003f0000)
-#define PHY_BB_TPC_16_PDADC_PAR_CORR_HT40_MSB 29
-#define PHY_BB_TPC_16_PDADC_PAR_CORR_HT40_LSB 24
-#define PHY_BB_TPC_16_PDADC_PAR_CORR_HT40_MASK 0x3f000000
-#define PHY_BB_TPC_16_PDADC_PAR_CORR_HT40_GET(x) (((x) & 0x3f000000) >> 24)
-#define PHY_BB_TPC_16_PDADC_PAR_CORR_HT40_SET(x) (((x) << 24) & 0x3f000000)
-
-/* macros for BB_tpc_17 */
-#define PHY_BB_TPC_17_ADDRESS 0x0000a3f0
-#define PHY_BB_TPC_17_OFFSET 0x0000a3f0
-#define PHY_BB_TPC_17_ENABLE_PAL_MSB 0
-#define PHY_BB_TPC_17_ENABLE_PAL_LSB 0
-#define PHY_BB_TPC_17_ENABLE_PAL_MASK 0x00000001
-#define PHY_BB_TPC_17_ENABLE_PAL_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_BB_TPC_17_ENABLE_PAL_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_BB_TPC_17_ENABLE_PAL_CCK_MSB 1
-#define PHY_BB_TPC_17_ENABLE_PAL_CCK_LSB 1
-#define PHY_BB_TPC_17_ENABLE_PAL_CCK_MASK 0x00000002
-#define PHY_BB_TPC_17_ENABLE_PAL_CCK_GET(x) (((x) & 0x00000002) >> 1)
-#define PHY_BB_TPC_17_ENABLE_PAL_CCK_SET(x) (((x) << 1) & 0x00000002)
-#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_20_MSB 2
-#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_20_LSB 2
-#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_20_MASK 0x00000004
-#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_20_GET(x) (((x) & 0x00000004) >> 2)
-#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_20_SET(x) (((x) << 2) & 0x00000004)
-#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_40_MSB 3
-#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_40_LSB 3
-#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_40_MASK 0x00000008
-#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_40_GET(x) (((x) & 0x00000008) >> 3)
-#define PHY_BB_TPC_17_ENABLE_PAL_OFDM_40_SET(x) (((x) << 3) & 0x00000008)
-#define PHY_BB_TPC_17_PAL_POWER_THRESHOLD_MSB 9
-#define PHY_BB_TPC_17_PAL_POWER_THRESHOLD_LSB 4
-#define PHY_BB_TPC_17_PAL_POWER_THRESHOLD_MASK 0x000003f0
-#define PHY_BB_TPC_17_PAL_POWER_THRESHOLD_GET(x) (((x) & 0x000003f0) >> 4)
-#define PHY_BB_TPC_17_PAL_POWER_THRESHOLD_SET(x) (((x) << 4) & 0x000003f0)
-#define PHY_BB_TPC_17_FORCE_PAL_LOCKED_MSB 10
-#define PHY_BB_TPC_17_FORCE_PAL_LOCKED_LSB 10
-#define PHY_BB_TPC_17_FORCE_PAL_LOCKED_MASK 0x00000400
-#define PHY_BB_TPC_17_FORCE_PAL_LOCKED_GET(x) (((x) & 0x00000400) >> 10)
-#define PHY_BB_TPC_17_FORCE_PAL_LOCKED_SET(x) (((x) << 10) & 0x00000400)
-#define PHY_BB_TPC_17_INIT_TX_GAIN_SETTING_PAL_ON_MSB 16
-#define PHY_BB_TPC_17_INIT_TX_GAIN_SETTING_PAL_ON_LSB 11
-#define PHY_BB_TPC_17_INIT_TX_GAIN_SETTING_PAL_ON_MASK 0x0001f800
-#define PHY_BB_TPC_17_INIT_TX_GAIN_SETTING_PAL_ON_GET(x) (((x) & 0x0001f800) >> 11)
-#define PHY_BB_TPC_17_INIT_TX_GAIN_SETTING_PAL_ON_SET(x) (((x) << 11) & 0x0001f800)
-
-/* macros for BB_tpc_18 */
-#define PHY_BB_TPC_18_ADDRESS 0x0000a3f4
-#define PHY_BB_TPC_18_OFFSET 0x0000a3f4
-#define PHY_BB_TPC_18_THERM_CAL_VALUE_MSB 7
-#define PHY_BB_TPC_18_THERM_CAL_VALUE_LSB 0
-#define PHY_BB_TPC_18_THERM_CAL_VALUE_MASK 0x000000ff
-#define PHY_BB_TPC_18_THERM_CAL_VALUE_GET(x) (((x) & 0x000000ff) >> 0)
-#define PHY_BB_TPC_18_THERM_CAL_VALUE_SET(x) (((x) << 0) & 0x000000ff)
-#define PHY_BB_TPC_18_VOLT_CAL_VALUE_MSB 15
-#define PHY_BB_TPC_18_VOLT_CAL_VALUE_LSB 8
-#define PHY_BB_TPC_18_VOLT_CAL_VALUE_MASK 0x0000ff00
-#define PHY_BB_TPC_18_VOLT_CAL_VALUE_GET(x) (((x) & 0x0000ff00) >> 8)
-#define PHY_BB_TPC_18_VOLT_CAL_VALUE_SET(x) (((x) << 8) & 0x0000ff00)
-#define PHY_BB_TPC_18_USE_LEGACY_TPC_MSB 16
-#define PHY_BB_TPC_18_USE_LEGACY_TPC_LSB 16
-#define PHY_BB_TPC_18_USE_LEGACY_TPC_MASK 0x00010000
-#define PHY_BB_TPC_18_USE_LEGACY_TPC_GET(x) (((x) & 0x00010000) >> 16)
-#define PHY_BB_TPC_18_USE_LEGACY_TPC_SET(x) (((x) << 16) & 0x00010000)
-
-/* macros for BB_tpc_19 */
-#define PHY_BB_TPC_19_ADDRESS 0x0000a3f8
-#define PHY_BB_TPC_19_OFFSET 0x0000a3f8
-#define PHY_BB_TPC_19_ALPHA_THERM_MSB 7
-#define PHY_BB_TPC_19_ALPHA_THERM_LSB 0
-#define PHY_BB_TPC_19_ALPHA_THERM_MASK 0x000000ff
-#define PHY_BB_TPC_19_ALPHA_THERM_GET(x) (((x) & 0x000000ff) >> 0)
-#define PHY_BB_TPC_19_ALPHA_THERM_SET(x) (((x) << 0) & 0x000000ff)
-#define PHY_BB_TPC_19_ALPHA_THERM_PAL_ON_MSB 15
-#define PHY_BB_TPC_19_ALPHA_THERM_PAL_ON_LSB 8
-#define PHY_BB_TPC_19_ALPHA_THERM_PAL_ON_MASK 0x0000ff00
-#define PHY_BB_TPC_19_ALPHA_THERM_PAL_ON_GET(x) (((x) & 0x0000ff00) >> 8)
-#define PHY_BB_TPC_19_ALPHA_THERM_PAL_ON_SET(x) (((x) << 8) & 0x0000ff00)
-#define PHY_BB_TPC_19_ALPHA_VOLT_MSB 20
-#define PHY_BB_TPC_19_ALPHA_VOLT_LSB 16
-#define PHY_BB_TPC_19_ALPHA_VOLT_MASK 0x001f0000
-#define PHY_BB_TPC_19_ALPHA_VOLT_GET(x) (((x) & 0x001f0000) >> 16)
-#define PHY_BB_TPC_19_ALPHA_VOLT_SET(x) (((x) << 16) & 0x001f0000)
-#define PHY_BB_TPC_19_ALPHA_VOLT_PAL_ON_MSB 25
-#define PHY_BB_TPC_19_ALPHA_VOLT_PAL_ON_LSB 21
-#define PHY_BB_TPC_19_ALPHA_VOLT_PAL_ON_MASK 0x03e00000
-#define PHY_BB_TPC_19_ALPHA_VOLT_PAL_ON_GET(x) (((x) & 0x03e00000) >> 21)
-#define PHY_BB_TPC_19_ALPHA_VOLT_PAL_ON_SET(x) (((x) << 21) & 0x03e00000)
-
-/* macros for BB_tpc_20 */
-#define PHY_BB_TPC_20_ADDRESS 0x0000a3fc
-#define PHY_BB_TPC_20_OFFSET 0x0000a3fc
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_0_MSB 0
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_0_LSB 0
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_0_MASK 0x00000001
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_0_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_0_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_1_MSB 1
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_1_LSB 1
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_1_MASK 0x00000002
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_1_GET(x) (((x) & 0x00000002) >> 1)
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_1_SET(x) (((x) << 1) & 0x00000002)
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_2_MSB 2
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_2_LSB 2
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_2_MASK 0x00000004
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_2_GET(x) (((x) & 0x00000004) >> 2)
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_2_SET(x) (((x) << 2) & 0x00000004)
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_3_MSB 3
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_3_LSB 3
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_3_MASK 0x00000008
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_3_GET(x) (((x) & 0x00000008) >> 3)
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_3_SET(x) (((x) << 3) & 0x00000008)
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_4_MSB 4
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_4_LSB 4
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_4_MASK 0x00000010
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_4_GET(x) (((x) & 0x00000010) >> 4)
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_4_SET(x) (((x) << 4) & 0x00000010)
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_5_MSB 5
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_5_LSB 5
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_5_MASK 0x00000020
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_5_GET(x) (((x) & 0x00000020) >> 5)
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_5_SET(x) (((x) << 5) & 0x00000020)
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_6_MSB 6
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_6_LSB 6
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_6_MASK 0x00000040
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_6_GET(x) (((x) & 0x00000040) >> 6)
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_6_SET(x) (((x) << 6) & 0x00000040)
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_7_MSB 7
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_7_LSB 7
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_7_MASK 0x00000080
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_7_GET(x) (((x) & 0x00000080) >> 7)
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_7_SET(x) (((x) << 7) & 0x00000080)
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_8_MSB 8
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_8_LSB 8
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_8_MASK 0x00000100
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_8_GET(x) (((x) & 0x00000100) >> 8)
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_8_SET(x) (((x) << 8) & 0x00000100)
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_9_MSB 9
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_9_LSB 9
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_9_MASK 0x00000200
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_9_GET(x) (((x) & 0x00000200) >> 9)
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_9_SET(x) (((x) << 9) & 0x00000200)
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_10_MSB 10
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_10_LSB 10
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_10_MASK 0x00000400
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_10_GET(x) (((x) & 0x00000400) >> 10)
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_10_SET(x) (((x) << 10) & 0x00000400)
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_11_MSB 11
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_11_LSB 11
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_11_MASK 0x00000800
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_11_GET(x) (((x) & 0x00000800) >> 11)
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_11_SET(x) (((x) << 11) & 0x00000800)
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_12_MSB 12
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_12_LSB 12
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_12_MASK 0x00001000
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_12_GET(x) (((x) & 0x00001000) >> 12)
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_12_SET(x) (((x) << 12) & 0x00001000)
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_13_MSB 13
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_13_LSB 13
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_13_MASK 0x00002000
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_13_GET(x) (((x) & 0x00002000) >> 13)
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_13_SET(x) (((x) << 13) & 0x00002000)
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_14_MSB 14
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_14_LSB 14
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_14_MASK 0x00004000
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_14_GET(x) (((x) & 0x00004000) >> 14)
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_14_SET(x) (((x) << 14) & 0x00004000)
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_15_MSB 15
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_15_LSB 15
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_15_MASK 0x00008000
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_15_GET(x) (((x) & 0x00008000) >> 15)
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_15_SET(x) (((x) << 15) & 0x00008000)
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_16_MSB 16
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_16_LSB 16
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_16_MASK 0x00010000
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_16_GET(x) (((x) & 0x00010000) >> 16)
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_16_SET(x) (((x) << 16) & 0x00010000)
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_17_MSB 17
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_17_LSB 17
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_17_MASK 0x00020000
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_17_GET(x) (((x) & 0x00020000) >> 17)
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_17_SET(x) (((x) << 17) & 0x00020000)
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_18_MSB 18
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_18_LSB 18
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_18_MASK 0x00040000
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_18_GET(x) (((x) & 0x00040000) >> 18)
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_18_SET(x) (((x) << 18) & 0x00040000)
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_19_MSB 19
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_19_LSB 19
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_19_MASK 0x00080000
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_19_GET(x) (((x) & 0x00080000) >> 19)
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_19_SET(x) (((x) << 19) & 0x00080000)
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_20_MSB 20
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_20_LSB 20
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_20_MASK 0x00100000
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_20_GET(x) (((x) & 0x00100000) >> 20)
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_20_SET(x) (((x) << 20) & 0x00100000)
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_21_MSB 21
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_21_LSB 21
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_21_MASK 0x00200000
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_21_GET(x) (((x) & 0x00200000) >> 21)
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_21_SET(x) (((x) << 21) & 0x00200000)
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_22_MSB 22
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_22_LSB 22
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_22_MASK 0x00400000
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_22_GET(x) (((x) & 0x00400000) >> 22)
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_22_SET(x) (((x) << 22) & 0x00400000)
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_23_MSB 23
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_23_LSB 23
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_23_MASK 0x00800000
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_23_GET(x) (((x) & 0x00800000) >> 23)
-#define PHY_BB_TPC_20_ENABLE_PAL_MCS_23_SET(x) (((x) << 23) & 0x00800000)
-
-/* macros for BB_tx_gain_tab_1 */
-#define PHY_BB_TX_GAIN_TAB_1_ADDRESS 0x0000a400
-#define PHY_BB_TX_GAIN_TAB_1_OFFSET 0x0000a400
-#define PHY_BB_TX_GAIN_TAB_1_TG_TABLE1_MSB 31
-#define PHY_BB_TX_GAIN_TAB_1_TG_TABLE1_LSB 0
-#define PHY_BB_TX_GAIN_TAB_1_TG_TABLE1_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_1_TG_TABLE1_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_1_TG_TABLE1_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_2 */
-#define PHY_BB_TX_GAIN_TAB_2_ADDRESS 0x0000a404
-#define PHY_BB_TX_GAIN_TAB_2_OFFSET 0x0000a404
-#define PHY_BB_TX_GAIN_TAB_2_TG_TABLE2_MSB 31
-#define PHY_BB_TX_GAIN_TAB_2_TG_TABLE2_LSB 0
-#define PHY_BB_TX_GAIN_TAB_2_TG_TABLE2_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_2_TG_TABLE2_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_2_TG_TABLE2_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_3 */
-#define PHY_BB_TX_GAIN_TAB_3_ADDRESS 0x0000a408
-#define PHY_BB_TX_GAIN_TAB_3_OFFSET 0x0000a408
-#define PHY_BB_TX_GAIN_TAB_3_TG_TABLE3_MSB 31
-#define PHY_BB_TX_GAIN_TAB_3_TG_TABLE3_LSB 0
-#define PHY_BB_TX_GAIN_TAB_3_TG_TABLE3_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_3_TG_TABLE3_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_3_TG_TABLE3_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_4 */
-#define PHY_BB_TX_GAIN_TAB_4_ADDRESS 0x0000a40c
-#define PHY_BB_TX_GAIN_TAB_4_OFFSET 0x0000a40c
-#define PHY_BB_TX_GAIN_TAB_4_TG_TABLE4_MSB 31
-#define PHY_BB_TX_GAIN_TAB_4_TG_TABLE4_LSB 0
-#define PHY_BB_TX_GAIN_TAB_4_TG_TABLE4_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_4_TG_TABLE4_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_4_TG_TABLE4_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_5 */
-#define PHY_BB_TX_GAIN_TAB_5_ADDRESS 0x0000a410
-#define PHY_BB_TX_GAIN_TAB_5_OFFSET 0x0000a410
-#define PHY_BB_TX_GAIN_TAB_5_TG_TABLE5_MSB 31
-#define PHY_BB_TX_GAIN_TAB_5_TG_TABLE5_LSB 0
-#define PHY_BB_TX_GAIN_TAB_5_TG_TABLE5_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_5_TG_TABLE5_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_5_TG_TABLE5_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_6 */
-#define PHY_BB_TX_GAIN_TAB_6_ADDRESS 0x0000a414
-#define PHY_BB_TX_GAIN_TAB_6_OFFSET 0x0000a414
-#define PHY_BB_TX_GAIN_TAB_6_TG_TABLE6_MSB 31
-#define PHY_BB_TX_GAIN_TAB_6_TG_TABLE6_LSB 0
-#define PHY_BB_TX_GAIN_TAB_6_TG_TABLE6_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_6_TG_TABLE6_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_6_TG_TABLE6_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_7 */
-#define PHY_BB_TX_GAIN_TAB_7_ADDRESS 0x0000a418
-#define PHY_BB_TX_GAIN_TAB_7_OFFSET 0x0000a418
-#define PHY_BB_TX_GAIN_TAB_7_TG_TABLE7_MSB 31
-#define PHY_BB_TX_GAIN_TAB_7_TG_TABLE7_LSB 0
-#define PHY_BB_TX_GAIN_TAB_7_TG_TABLE7_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_7_TG_TABLE7_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_7_TG_TABLE7_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_8 */
-#define PHY_BB_TX_GAIN_TAB_8_ADDRESS 0x0000a41c
-#define PHY_BB_TX_GAIN_TAB_8_OFFSET 0x0000a41c
-#define PHY_BB_TX_GAIN_TAB_8_TG_TABLE8_MSB 31
-#define PHY_BB_TX_GAIN_TAB_8_TG_TABLE8_LSB 0
-#define PHY_BB_TX_GAIN_TAB_8_TG_TABLE8_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_8_TG_TABLE8_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_8_TG_TABLE8_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_9 */
-#define PHY_BB_TX_GAIN_TAB_9_ADDRESS 0x0000a420
-#define PHY_BB_TX_GAIN_TAB_9_OFFSET 0x0000a420
-#define PHY_BB_TX_GAIN_TAB_9_TG_TABLE9_MSB 31
-#define PHY_BB_TX_GAIN_TAB_9_TG_TABLE9_LSB 0
-#define PHY_BB_TX_GAIN_TAB_9_TG_TABLE9_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_9_TG_TABLE9_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_9_TG_TABLE9_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_10 */
-#define PHY_BB_TX_GAIN_TAB_10_ADDRESS 0x0000a424
-#define PHY_BB_TX_GAIN_TAB_10_OFFSET 0x0000a424
-#define PHY_BB_TX_GAIN_TAB_10_TG_TABLE10_MSB 31
-#define PHY_BB_TX_GAIN_TAB_10_TG_TABLE10_LSB 0
-#define PHY_BB_TX_GAIN_TAB_10_TG_TABLE10_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_10_TG_TABLE10_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_10_TG_TABLE10_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_11 */
-#define PHY_BB_TX_GAIN_TAB_11_ADDRESS 0x0000a428
-#define PHY_BB_TX_GAIN_TAB_11_OFFSET 0x0000a428
-#define PHY_BB_TX_GAIN_TAB_11_TG_TABLE11_MSB 31
-#define PHY_BB_TX_GAIN_TAB_11_TG_TABLE11_LSB 0
-#define PHY_BB_TX_GAIN_TAB_11_TG_TABLE11_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_11_TG_TABLE11_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_11_TG_TABLE11_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_12 */
-#define PHY_BB_TX_GAIN_TAB_12_ADDRESS 0x0000a42c
-#define PHY_BB_TX_GAIN_TAB_12_OFFSET 0x0000a42c
-#define PHY_BB_TX_GAIN_TAB_12_TG_TABLE12_MSB 31
-#define PHY_BB_TX_GAIN_TAB_12_TG_TABLE12_LSB 0
-#define PHY_BB_TX_GAIN_TAB_12_TG_TABLE12_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_12_TG_TABLE12_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_12_TG_TABLE12_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_13 */
-#define PHY_BB_TX_GAIN_TAB_13_ADDRESS 0x0000a430
-#define PHY_BB_TX_GAIN_TAB_13_OFFSET 0x0000a430
-#define PHY_BB_TX_GAIN_TAB_13_TG_TABLE13_MSB 31
-#define PHY_BB_TX_GAIN_TAB_13_TG_TABLE13_LSB 0
-#define PHY_BB_TX_GAIN_TAB_13_TG_TABLE13_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_13_TG_TABLE13_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_13_TG_TABLE13_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_14 */
-#define PHY_BB_TX_GAIN_TAB_14_ADDRESS 0x0000a434
-#define PHY_BB_TX_GAIN_TAB_14_OFFSET 0x0000a434
-#define PHY_BB_TX_GAIN_TAB_14_TG_TABLE14_MSB 31
-#define PHY_BB_TX_GAIN_TAB_14_TG_TABLE14_LSB 0
-#define PHY_BB_TX_GAIN_TAB_14_TG_TABLE14_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_14_TG_TABLE14_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_14_TG_TABLE14_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_15 */
-#define PHY_BB_TX_GAIN_TAB_15_ADDRESS 0x0000a438
-#define PHY_BB_TX_GAIN_TAB_15_OFFSET 0x0000a438
-#define PHY_BB_TX_GAIN_TAB_15_TG_TABLE15_MSB 31
-#define PHY_BB_TX_GAIN_TAB_15_TG_TABLE15_LSB 0
-#define PHY_BB_TX_GAIN_TAB_15_TG_TABLE15_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_15_TG_TABLE15_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_15_TG_TABLE15_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_16 */
-#define PHY_BB_TX_GAIN_TAB_16_ADDRESS 0x0000a43c
-#define PHY_BB_TX_GAIN_TAB_16_OFFSET 0x0000a43c
-#define PHY_BB_TX_GAIN_TAB_16_TG_TABLE16_MSB 31
-#define PHY_BB_TX_GAIN_TAB_16_TG_TABLE16_LSB 0
-#define PHY_BB_TX_GAIN_TAB_16_TG_TABLE16_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_16_TG_TABLE16_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_16_TG_TABLE16_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_17 */
-#define PHY_BB_TX_GAIN_TAB_17_ADDRESS 0x0000a440
-#define PHY_BB_TX_GAIN_TAB_17_OFFSET 0x0000a440
-#define PHY_BB_TX_GAIN_TAB_17_TG_TABLE17_MSB 31
-#define PHY_BB_TX_GAIN_TAB_17_TG_TABLE17_LSB 0
-#define PHY_BB_TX_GAIN_TAB_17_TG_TABLE17_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_17_TG_TABLE17_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_17_TG_TABLE17_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_18 */
-#define PHY_BB_TX_GAIN_TAB_18_ADDRESS 0x0000a444
-#define PHY_BB_TX_GAIN_TAB_18_OFFSET 0x0000a444
-#define PHY_BB_TX_GAIN_TAB_18_TG_TABLE18_MSB 31
-#define PHY_BB_TX_GAIN_TAB_18_TG_TABLE18_LSB 0
-#define PHY_BB_TX_GAIN_TAB_18_TG_TABLE18_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_18_TG_TABLE18_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_18_TG_TABLE18_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_19 */
-#define PHY_BB_TX_GAIN_TAB_19_ADDRESS 0x0000a448
-#define PHY_BB_TX_GAIN_TAB_19_OFFSET 0x0000a448
-#define PHY_BB_TX_GAIN_TAB_19_TG_TABLE19_MSB 31
-#define PHY_BB_TX_GAIN_TAB_19_TG_TABLE19_LSB 0
-#define PHY_BB_TX_GAIN_TAB_19_TG_TABLE19_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_19_TG_TABLE19_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_19_TG_TABLE19_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_20 */
-#define PHY_BB_TX_GAIN_TAB_20_ADDRESS 0x0000a44c
-#define PHY_BB_TX_GAIN_TAB_20_OFFSET 0x0000a44c
-#define PHY_BB_TX_GAIN_TAB_20_TG_TABLE20_MSB 31
-#define PHY_BB_TX_GAIN_TAB_20_TG_TABLE20_LSB 0
-#define PHY_BB_TX_GAIN_TAB_20_TG_TABLE20_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_20_TG_TABLE20_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_20_TG_TABLE20_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_21 */
-#define PHY_BB_TX_GAIN_TAB_21_ADDRESS 0x0000a450
-#define PHY_BB_TX_GAIN_TAB_21_OFFSET 0x0000a450
-#define PHY_BB_TX_GAIN_TAB_21_TG_TABLE21_MSB 31
-#define PHY_BB_TX_GAIN_TAB_21_TG_TABLE21_LSB 0
-#define PHY_BB_TX_GAIN_TAB_21_TG_TABLE21_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_21_TG_TABLE21_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_21_TG_TABLE21_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_22 */
-#define PHY_BB_TX_GAIN_TAB_22_ADDRESS 0x0000a454
-#define PHY_BB_TX_GAIN_TAB_22_OFFSET 0x0000a454
-#define PHY_BB_TX_GAIN_TAB_22_TG_TABLE22_MSB 31
-#define PHY_BB_TX_GAIN_TAB_22_TG_TABLE22_LSB 0
-#define PHY_BB_TX_GAIN_TAB_22_TG_TABLE22_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_22_TG_TABLE22_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_22_TG_TABLE22_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_23 */
-#define PHY_BB_TX_GAIN_TAB_23_ADDRESS 0x0000a458
-#define PHY_BB_TX_GAIN_TAB_23_OFFSET 0x0000a458
-#define PHY_BB_TX_GAIN_TAB_23_TG_TABLE23_MSB 31
-#define PHY_BB_TX_GAIN_TAB_23_TG_TABLE23_LSB 0
-#define PHY_BB_TX_GAIN_TAB_23_TG_TABLE23_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_23_TG_TABLE23_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_23_TG_TABLE23_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_24 */
-#define PHY_BB_TX_GAIN_TAB_24_ADDRESS 0x0000a45c
-#define PHY_BB_TX_GAIN_TAB_24_OFFSET 0x0000a45c
-#define PHY_BB_TX_GAIN_TAB_24_TG_TABLE24_MSB 31
-#define PHY_BB_TX_GAIN_TAB_24_TG_TABLE24_LSB 0
-#define PHY_BB_TX_GAIN_TAB_24_TG_TABLE24_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_24_TG_TABLE24_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_24_TG_TABLE24_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_25 */
-#define PHY_BB_TX_GAIN_TAB_25_ADDRESS 0x0000a460
-#define PHY_BB_TX_GAIN_TAB_25_OFFSET 0x0000a460
-#define PHY_BB_TX_GAIN_TAB_25_TG_TABLE25_MSB 31
-#define PHY_BB_TX_GAIN_TAB_25_TG_TABLE25_LSB 0
-#define PHY_BB_TX_GAIN_TAB_25_TG_TABLE25_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_25_TG_TABLE25_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_25_TG_TABLE25_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_26 */
-#define PHY_BB_TX_GAIN_TAB_26_ADDRESS 0x0000a464
-#define PHY_BB_TX_GAIN_TAB_26_OFFSET 0x0000a464
-#define PHY_BB_TX_GAIN_TAB_26_TG_TABLE26_MSB 31
-#define PHY_BB_TX_GAIN_TAB_26_TG_TABLE26_LSB 0
-#define PHY_BB_TX_GAIN_TAB_26_TG_TABLE26_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_26_TG_TABLE26_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_26_TG_TABLE26_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_27 */
-#define PHY_BB_TX_GAIN_TAB_27_ADDRESS 0x0000a468
-#define PHY_BB_TX_GAIN_TAB_27_OFFSET 0x0000a468
-#define PHY_BB_TX_GAIN_TAB_27_TG_TABLE27_MSB 31
-#define PHY_BB_TX_GAIN_TAB_27_TG_TABLE27_LSB 0
-#define PHY_BB_TX_GAIN_TAB_27_TG_TABLE27_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_27_TG_TABLE27_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_27_TG_TABLE27_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_28 */
-#define PHY_BB_TX_GAIN_TAB_28_ADDRESS 0x0000a46c
-#define PHY_BB_TX_GAIN_TAB_28_OFFSET 0x0000a46c
-#define PHY_BB_TX_GAIN_TAB_28_TG_TABLE28_MSB 31
-#define PHY_BB_TX_GAIN_TAB_28_TG_TABLE28_LSB 0
-#define PHY_BB_TX_GAIN_TAB_28_TG_TABLE28_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_28_TG_TABLE28_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_28_TG_TABLE28_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_29 */
-#define PHY_BB_TX_GAIN_TAB_29_ADDRESS 0x0000a470
-#define PHY_BB_TX_GAIN_TAB_29_OFFSET 0x0000a470
-#define PHY_BB_TX_GAIN_TAB_29_TG_TABLE29_MSB 31
-#define PHY_BB_TX_GAIN_TAB_29_TG_TABLE29_LSB 0
-#define PHY_BB_TX_GAIN_TAB_29_TG_TABLE29_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_29_TG_TABLE29_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_29_TG_TABLE29_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_30 */
-#define PHY_BB_TX_GAIN_TAB_30_ADDRESS 0x0000a474
-#define PHY_BB_TX_GAIN_TAB_30_OFFSET 0x0000a474
-#define PHY_BB_TX_GAIN_TAB_30_TG_TABLE30_MSB 31
-#define PHY_BB_TX_GAIN_TAB_30_TG_TABLE30_LSB 0
-#define PHY_BB_TX_GAIN_TAB_30_TG_TABLE30_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_30_TG_TABLE30_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_30_TG_TABLE30_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_31 */
-#define PHY_BB_TX_GAIN_TAB_31_ADDRESS 0x0000a478
-#define PHY_BB_TX_GAIN_TAB_31_OFFSET 0x0000a478
-#define PHY_BB_TX_GAIN_TAB_31_TG_TABLE31_MSB 31
-#define PHY_BB_TX_GAIN_TAB_31_TG_TABLE31_LSB 0
-#define PHY_BB_TX_GAIN_TAB_31_TG_TABLE31_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_31_TG_TABLE31_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_31_TG_TABLE31_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_32 */
-#define PHY_BB_TX_GAIN_TAB_32_ADDRESS 0x0000a47c
-#define PHY_BB_TX_GAIN_TAB_32_OFFSET 0x0000a47c
-#define PHY_BB_TX_GAIN_TAB_32_TG_TABLE32_MSB 31
-#define PHY_BB_TX_GAIN_TAB_32_TG_TABLE32_LSB 0
-#define PHY_BB_TX_GAIN_TAB_32_TG_TABLE32_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_32_TG_TABLE32_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_32_TG_TABLE32_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_pal_1 */
-#define PHY_BB_TX_GAIN_TAB_PAL_1_ADDRESS 0x0000a480
-#define PHY_BB_TX_GAIN_TAB_PAL_1_OFFSET 0x0000a480
-#define PHY_BB_TX_GAIN_TAB_PAL_1_TG_TABLE1_PAL_ON_MSB 31
-#define PHY_BB_TX_GAIN_TAB_PAL_1_TG_TABLE1_PAL_ON_LSB 0
-#define PHY_BB_TX_GAIN_TAB_PAL_1_TG_TABLE1_PAL_ON_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_PAL_1_TG_TABLE1_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_PAL_1_TG_TABLE1_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_pal_2 */
-#define PHY_BB_TX_GAIN_TAB_PAL_2_ADDRESS 0x0000a484
-#define PHY_BB_TX_GAIN_TAB_PAL_2_OFFSET 0x0000a484
-#define PHY_BB_TX_GAIN_TAB_PAL_2_TG_TABLE2_PAL_ON_MSB 31
-#define PHY_BB_TX_GAIN_TAB_PAL_2_TG_TABLE2_PAL_ON_LSB 0
-#define PHY_BB_TX_GAIN_TAB_PAL_2_TG_TABLE2_PAL_ON_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_PAL_2_TG_TABLE2_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_PAL_2_TG_TABLE2_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_pal_3 */
-#define PHY_BB_TX_GAIN_TAB_PAL_3_ADDRESS 0x0000a488
-#define PHY_BB_TX_GAIN_TAB_PAL_3_OFFSET 0x0000a488
-#define PHY_BB_TX_GAIN_TAB_PAL_3_TG_TABLE3_PAL_ON_MSB 31
-#define PHY_BB_TX_GAIN_TAB_PAL_3_TG_TABLE3_PAL_ON_LSB 0
-#define PHY_BB_TX_GAIN_TAB_PAL_3_TG_TABLE3_PAL_ON_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_PAL_3_TG_TABLE3_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_PAL_3_TG_TABLE3_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_pal_4 */
-#define PHY_BB_TX_GAIN_TAB_PAL_4_ADDRESS 0x0000a48c
-#define PHY_BB_TX_GAIN_TAB_PAL_4_OFFSET 0x0000a48c
-#define PHY_BB_TX_GAIN_TAB_PAL_4_TG_TABLE4_PAL_ON_MSB 31
-#define PHY_BB_TX_GAIN_TAB_PAL_4_TG_TABLE4_PAL_ON_LSB 0
-#define PHY_BB_TX_GAIN_TAB_PAL_4_TG_TABLE4_PAL_ON_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_PAL_4_TG_TABLE4_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_PAL_4_TG_TABLE4_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_pal_5 */
-#define PHY_BB_TX_GAIN_TAB_PAL_5_ADDRESS 0x0000a490
-#define PHY_BB_TX_GAIN_TAB_PAL_5_OFFSET 0x0000a490
-#define PHY_BB_TX_GAIN_TAB_PAL_5_TG_TABLE5_PAL_ON_MSB 31
-#define PHY_BB_TX_GAIN_TAB_PAL_5_TG_TABLE5_PAL_ON_LSB 0
-#define PHY_BB_TX_GAIN_TAB_PAL_5_TG_TABLE5_PAL_ON_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_PAL_5_TG_TABLE5_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_PAL_5_TG_TABLE5_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_pal_6 */
-#define PHY_BB_TX_GAIN_TAB_PAL_6_ADDRESS 0x0000a494
-#define PHY_BB_TX_GAIN_TAB_PAL_6_OFFSET 0x0000a494
-#define PHY_BB_TX_GAIN_TAB_PAL_6_TG_TABLE6_PAL_ON_MSB 31
-#define PHY_BB_TX_GAIN_TAB_PAL_6_TG_TABLE6_PAL_ON_LSB 0
-#define PHY_BB_TX_GAIN_TAB_PAL_6_TG_TABLE6_PAL_ON_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_PAL_6_TG_TABLE6_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_PAL_6_TG_TABLE6_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_pal_7 */
-#define PHY_BB_TX_GAIN_TAB_PAL_7_ADDRESS 0x0000a498
-#define PHY_BB_TX_GAIN_TAB_PAL_7_OFFSET 0x0000a498
-#define PHY_BB_TX_GAIN_TAB_PAL_7_TG_TABLE7_PAL_ON_MSB 31
-#define PHY_BB_TX_GAIN_TAB_PAL_7_TG_TABLE7_PAL_ON_LSB 0
-#define PHY_BB_TX_GAIN_TAB_PAL_7_TG_TABLE7_PAL_ON_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_PAL_7_TG_TABLE7_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_PAL_7_TG_TABLE7_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_pal_8 */
-#define PHY_BB_TX_GAIN_TAB_PAL_8_ADDRESS 0x0000a49c
-#define PHY_BB_TX_GAIN_TAB_PAL_8_OFFSET 0x0000a49c
-#define PHY_BB_TX_GAIN_TAB_PAL_8_TG_TABLE8_PAL_ON_MSB 31
-#define PHY_BB_TX_GAIN_TAB_PAL_8_TG_TABLE8_PAL_ON_LSB 0
-#define PHY_BB_TX_GAIN_TAB_PAL_8_TG_TABLE8_PAL_ON_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_PAL_8_TG_TABLE8_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_PAL_8_TG_TABLE8_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_pal_9 */
-#define PHY_BB_TX_GAIN_TAB_PAL_9_ADDRESS 0x0000a4a0
-#define PHY_BB_TX_GAIN_TAB_PAL_9_OFFSET 0x0000a4a0
-#define PHY_BB_TX_GAIN_TAB_PAL_9_TG_TABLE9_PAL_ON_MSB 31
-#define PHY_BB_TX_GAIN_TAB_PAL_9_TG_TABLE9_PAL_ON_LSB 0
-#define PHY_BB_TX_GAIN_TAB_PAL_9_TG_TABLE9_PAL_ON_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_PAL_9_TG_TABLE9_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_PAL_9_TG_TABLE9_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_pal_10 */
-#define PHY_BB_TX_GAIN_TAB_PAL_10_ADDRESS 0x0000a4a4
-#define PHY_BB_TX_GAIN_TAB_PAL_10_OFFSET 0x0000a4a4
-#define PHY_BB_TX_GAIN_TAB_PAL_10_TG_TABLE10_PAL_ON_MSB 31
-#define PHY_BB_TX_GAIN_TAB_PAL_10_TG_TABLE10_PAL_ON_LSB 0
-#define PHY_BB_TX_GAIN_TAB_PAL_10_TG_TABLE10_PAL_ON_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_PAL_10_TG_TABLE10_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_PAL_10_TG_TABLE10_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_pal_11 */
-#define PHY_BB_TX_GAIN_TAB_PAL_11_ADDRESS 0x0000a4a8
-#define PHY_BB_TX_GAIN_TAB_PAL_11_OFFSET 0x0000a4a8
-#define PHY_BB_TX_GAIN_TAB_PAL_11_TG_TABLE11_PAL_ON_MSB 31
-#define PHY_BB_TX_GAIN_TAB_PAL_11_TG_TABLE11_PAL_ON_LSB 0
-#define PHY_BB_TX_GAIN_TAB_PAL_11_TG_TABLE11_PAL_ON_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_PAL_11_TG_TABLE11_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_PAL_11_TG_TABLE11_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_pal_12 */
-#define PHY_BB_TX_GAIN_TAB_PAL_12_ADDRESS 0x0000a4ac
-#define PHY_BB_TX_GAIN_TAB_PAL_12_OFFSET 0x0000a4ac
-#define PHY_BB_TX_GAIN_TAB_PAL_12_TG_TABLE12_PAL_ON_MSB 31
-#define PHY_BB_TX_GAIN_TAB_PAL_12_TG_TABLE12_PAL_ON_LSB 0
-#define PHY_BB_TX_GAIN_TAB_PAL_12_TG_TABLE12_PAL_ON_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_PAL_12_TG_TABLE12_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_PAL_12_TG_TABLE12_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_pal_13 */
-#define PHY_BB_TX_GAIN_TAB_PAL_13_ADDRESS 0x0000a4b0
-#define PHY_BB_TX_GAIN_TAB_PAL_13_OFFSET 0x0000a4b0
-#define PHY_BB_TX_GAIN_TAB_PAL_13_TG_TABLE13_PAL_ON_MSB 31
-#define PHY_BB_TX_GAIN_TAB_PAL_13_TG_TABLE13_PAL_ON_LSB 0
-#define PHY_BB_TX_GAIN_TAB_PAL_13_TG_TABLE13_PAL_ON_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_PAL_13_TG_TABLE13_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_PAL_13_TG_TABLE13_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_pal_14 */
-#define PHY_BB_TX_GAIN_TAB_PAL_14_ADDRESS 0x0000a4b4
-#define PHY_BB_TX_GAIN_TAB_PAL_14_OFFSET 0x0000a4b4
-#define PHY_BB_TX_GAIN_TAB_PAL_14_TG_TABLE14_PAL_ON_MSB 31
-#define PHY_BB_TX_GAIN_TAB_PAL_14_TG_TABLE14_PAL_ON_LSB 0
-#define PHY_BB_TX_GAIN_TAB_PAL_14_TG_TABLE14_PAL_ON_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_PAL_14_TG_TABLE14_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_PAL_14_TG_TABLE14_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_pal_15 */
-#define PHY_BB_TX_GAIN_TAB_PAL_15_ADDRESS 0x0000a4b8
-#define PHY_BB_TX_GAIN_TAB_PAL_15_OFFSET 0x0000a4b8
-#define PHY_BB_TX_GAIN_TAB_PAL_15_TG_TABLE15_PAL_ON_MSB 31
-#define PHY_BB_TX_GAIN_TAB_PAL_15_TG_TABLE15_PAL_ON_LSB 0
-#define PHY_BB_TX_GAIN_TAB_PAL_15_TG_TABLE15_PAL_ON_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_PAL_15_TG_TABLE15_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_PAL_15_TG_TABLE15_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_pal_16 */
-#define PHY_BB_TX_GAIN_TAB_PAL_16_ADDRESS 0x0000a4bc
-#define PHY_BB_TX_GAIN_TAB_PAL_16_OFFSET 0x0000a4bc
-#define PHY_BB_TX_GAIN_TAB_PAL_16_TG_TABLE16_PAL_ON_MSB 31
-#define PHY_BB_TX_GAIN_TAB_PAL_16_TG_TABLE16_PAL_ON_LSB 0
-#define PHY_BB_TX_GAIN_TAB_PAL_16_TG_TABLE16_PAL_ON_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_PAL_16_TG_TABLE16_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_PAL_16_TG_TABLE16_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_pal_17 */
-#define PHY_BB_TX_GAIN_TAB_PAL_17_ADDRESS 0x0000a4c0
-#define PHY_BB_TX_GAIN_TAB_PAL_17_OFFSET 0x0000a4c0
-#define PHY_BB_TX_GAIN_TAB_PAL_17_TG_TABLE17_PAL_ON_MSB 31
-#define PHY_BB_TX_GAIN_TAB_PAL_17_TG_TABLE17_PAL_ON_LSB 0
-#define PHY_BB_TX_GAIN_TAB_PAL_17_TG_TABLE17_PAL_ON_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_PAL_17_TG_TABLE17_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_PAL_17_TG_TABLE17_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_pal_18 */
-#define PHY_BB_TX_GAIN_TAB_PAL_18_ADDRESS 0x0000a4c4
-#define PHY_BB_TX_GAIN_TAB_PAL_18_OFFSET 0x0000a4c4
-#define PHY_BB_TX_GAIN_TAB_PAL_18_TG_TABLE18_PAL_ON_MSB 31
-#define PHY_BB_TX_GAIN_TAB_PAL_18_TG_TABLE18_PAL_ON_LSB 0
-#define PHY_BB_TX_GAIN_TAB_PAL_18_TG_TABLE18_PAL_ON_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_PAL_18_TG_TABLE18_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_PAL_18_TG_TABLE18_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_pal_19 */
-#define PHY_BB_TX_GAIN_TAB_PAL_19_ADDRESS 0x0000a4c8
-#define PHY_BB_TX_GAIN_TAB_PAL_19_OFFSET 0x0000a4c8
-#define PHY_BB_TX_GAIN_TAB_PAL_19_TG_TABLE19_PAL_ON_MSB 31
-#define PHY_BB_TX_GAIN_TAB_PAL_19_TG_TABLE19_PAL_ON_LSB 0
-#define PHY_BB_TX_GAIN_TAB_PAL_19_TG_TABLE19_PAL_ON_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_PAL_19_TG_TABLE19_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_PAL_19_TG_TABLE19_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_pal_20 */
-#define PHY_BB_TX_GAIN_TAB_PAL_20_ADDRESS 0x0000a4cc
-#define PHY_BB_TX_GAIN_TAB_PAL_20_OFFSET 0x0000a4cc
-#define PHY_BB_TX_GAIN_TAB_PAL_20_TG_TABLE20_PAL_ON_MSB 31
-#define PHY_BB_TX_GAIN_TAB_PAL_20_TG_TABLE20_PAL_ON_LSB 0
-#define PHY_BB_TX_GAIN_TAB_PAL_20_TG_TABLE20_PAL_ON_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_PAL_20_TG_TABLE20_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_PAL_20_TG_TABLE20_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_pal_21 */
-#define PHY_BB_TX_GAIN_TAB_PAL_21_ADDRESS 0x0000a4d0
-#define PHY_BB_TX_GAIN_TAB_PAL_21_OFFSET 0x0000a4d0
-#define PHY_BB_TX_GAIN_TAB_PAL_21_TG_TABLE21_PAL_ON_MSB 31
-#define PHY_BB_TX_GAIN_TAB_PAL_21_TG_TABLE21_PAL_ON_LSB 0
-#define PHY_BB_TX_GAIN_TAB_PAL_21_TG_TABLE21_PAL_ON_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_PAL_21_TG_TABLE21_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_PAL_21_TG_TABLE21_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_pal_22 */
-#define PHY_BB_TX_GAIN_TAB_PAL_22_ADDRESS 0x0000a4d4
-#define PHY_BB_TX_GAIN_TAB_PAL_22_OFFSET 0x0000a4d4
-#define PHY_BB_TX_GAIN_TAB_PAL_22_TG_TABLE22_PAL_ON_MSB 31
-#define PHY_BB_TX_GAIN_TAB_PAL_22_TG_TABLE22_PAL_ON_LSB 0
-#define PHY_BB_TX_GAIN_TAB_PAL_22_TG_TABLE22_PAL_ON_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_PAL_22_TG_TABLE22_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_PAL_22_TG_TABLE22_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_pal_23 */
-#define PHY_BB_TX_GAIN_TAB_PAL_23_ADDRESS 0x0000a4d8
-#define PHY_BB_TX_GAIN_TAB_PAL_23_OFFSET 0x0000a4d8
-#define PHY_BB_TX_GAIN_TAB_PAL_23_TG_TABLE23_PAL_ON_MSB 31
-#define PHY_BB_TX_GAIN_TAB_PAL_23_TG_TABLE23_PAL_ON_LSB 0
-#define PHY_BB_TX_GAIN_TAB_PAL_23_TG_TABLE23_PAL_ON_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_PAL_23_TG_TABLE23_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_PAL_23_TG_TABLE23_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_pal_24 */
-#define PHY_BB_TX_GAIN_TAB_PAL_24_ADDRESS 0x0000a4dc
-#define PHY_BB_TX_GAIN_TAB_PAL_24_OFFSET 0x0000a4dc
-#define PHY_BB_TX_GAIN_TAB_PAL_24_TG_TABLE24_PAL_ON_MSB 31
-#define PHY_BB_TX_GAIN_TAB_PAL_24_TG_TABLE24_PAL_ON_LSB 0
-#define PHY_BB_TX_GAIN_TAB_PAL_24_TG_TABLE24_PAL_ON_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_PAL_24_TG_TABLE24_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_PAL_24_TG_TABLE24_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_pal_25 */
-#define PHY_BB_TX_GAIN_TAB_PAL_25_ADDRESS 0x0000a4e0
-#define PHY_BB_TX_GAIN_TAB_PAL_25_OFFSET 0x0000a4e0
-#define PHY_BB_TX_GAIN_TAB_PAL_25_TG_TABLE25_PAL_ON_MSB 31
-#define PHY_BB_TX_GAIN_TAB_PAL_25_TG_TABLE25_PAL_ON_LSB 0
-#define PHY_BB_TX_GAIN_TAB_PAL_25_TG_TABLE25_PAL_ON_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_PAL_25_TG_TABLE25_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_PAL_25_TG_TABLE25_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_pal_26 */
-#define PHY_BB_TX_GAIN_TAB_PAL_26_ADDRESS 0x0000a4e4
-#define PHY_BB_TX_GAIN_TAB_PAL_26_OFFSET 0x0000a4e4
-#define PHY_BB_TX_GAIN_TAB_PAL_26_TG_TABLE26_PAL_ON_MSB 31
-#define PHY_BB_TX_GAIN_TAB_PAL_26_TG_TABLE26_PAL_ON_LSB 0
-#define PHY_BB_TX_GAIN_TAB_PAL_26_TG_TABLE26_PAL_ON_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_PAL_26_TG_TABLE26_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_PAL_26_TG_TABLE26_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_pal_27 */
-#define PHY_BB_TX_GAIN_TAB_PAL_27_ADDRESS 0x0000a4e8
-#define PHY_BB_TX_GAIN_TAB_PAL_27_OFFSET 0x0000a4e8
-#define PHY_BB_TX_GAIN_TAB_PAL_27_TG_TABLE27_PAL_ON_MSB 31
-#define PHY_BB_TX_GAIN_TAB_PAL_27_TG_TABLE27_PAL_ON_LSB 0
-#define PHY_BB_TX_GAIN_TAB_PAL_27_TG_TABLE27_PAL_ON_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_PAL_27_TG_TABLE27_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_PAL_27_TG_TABLE27_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_pal_28 */
-#define PHY_BB_TX_GAIN_TAB_PAL_28_ADDRESS 0x0000a4ec
-#define PHY_BB_TX_GAIN_TAB_PAL_28_OFFSET 0x0000a4ec
-#define PHY_BB_TX_GAIN_TAB_PAL_28_TG_TABLE28_PAL_ON_MSB 31
-#define PHY_BB_TX_GAIN_TAB_PAL_28_TG_TABLE28_PAL_ON_LSB 0
-#define PHY_BB_TX_GAIN_TAB_PAL_28_TG_TABLE28_PAL_ON_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_PAL_28_TG_TABLE28_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_PAL_28_TG_TABLE28_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_pal_29 */
-#define PHY_BB_TX_GAIN_TAB_PAL_29_ADDRESS 0x0000a4f0
-#define PHY_BB_TX_GAIN_TAB_PAL_29_OFFSET 0x0000a4f0
-#define PHY_BB_TX_GAIN_TAB_PAL_29_TG_TABLE29_PAL_ON_MSB 31
-#define PHY_BB_TX_GAIN_TAB_PAL_29_TG_TABLE29_PAL_ON_LSB 0
-#define PHY_BB_TX_GAIN_TAB_PAL_29_TG_TABLE29_PAL_ON_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_PAL_29_TG_TABLE29_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_PAL_29_TG_TABLE29_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_pal_30 */
-#define PHY_BB_TX_GAIN_TAB_PAL_30_ADDRESS 0x0000a4f4
-#define PHY_BB_TX_GAIN_TAB_PAL_30_OFFSET 0x0000a4f4
-#define PHY_BB_TX_GAIN_TAB_PAL_30_TG_TABLE30_PAL_ON_MSB 31
-#define PHY_BB_TX_GAIN_TAB_PAL_30_TG_TABLE30_PAL_ON_LSB 0
-#define PHY_BB_TX_GAIN_TAB_PAL_30_TG_TABLE30_PAL_ON_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_PAL_30_TG_TABLE30_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_PAL_30_TG_TABLE30_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_pal_31 */
-#define PHY_BB_TX_GAIN_TAB_PAL_31_ADDRESS 0x0000a4f8
-#define PHY_BB_TX_GAIN_TAB_PAL_31_OFFSET 0x0000a4f8
-#define PHY_BB_TX_GAIN_TAB_PAL_31_TG_TABLE31_PAL_ON_MSB 31
-#define PHY_BB_TX_GAIN_TAB_PAL_31_TG_TABLE31_PAL_ON_LSB 0
-#define PHY_BB_TX_GAIN_TAB_PAL_31_TG_TABLE31_PAL_ON_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_PAL_31_TG_TABLE31_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_PAL_31_TG_TABLE31_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_tx_gain_tab_pal_32 */
-#define PHY_BB_TX_GAIN_TAB_PAL_32_ADDRESS 0x0000a4fc
-#define PHY_BB_TX_GAIN_TAB_PAL_32_OFFSET 0x0000a4fc
-#define PHY_BB_TX_GAIN_TAB_PAL_32_TG_TABLE32_PAL_ON_MSB 31
-#define PHY_BB_TX_GAIN_TAB_PAL_32_TG_TABLE32_PAL_ON_LSB 0
-#define PHY_BB_TX_GAIN_TAB_PAL_32_TG_TABLE32_PAL_ON_MASK 0xffffffff
-#define PHY_BB_TX_GAIN_TAB_PAL_32_TG_TABLE32_PAL_ON_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_TX_GAIN_TAB_PAL_32_TG_TABLE32_PAL_ON_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_caltx_gain_set_0 */
-#define PHY_BB_CALTX_GAIN_SET_0_ADDRESS 0x0000a518
-#define PHY_BB_CALTX_GAIN_SET_0_OFFSET 0x0000a518
-#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_0_MSB 13
-#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_0_LSB 0
-#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_0_MASK 0x00003fff
-#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_0_GET(x) (((x) & 0x00003fff) >> 0)
-#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_0_SET(x) (((x) << 0) & 0x00003fff)
-#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_1_MSB 27
-#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_1_LSB 14
-#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_1_MASK 0x0fffc000
-#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_1_GET(x) (((x) & 0x0fffc000) >> 14)
-#define PHY_BB_CALTX_GAIN_SET_0_CALTX_GAIN_SET_1_SET(x) (((x) << 14) & 0x0fffc000)
-
-/* macros for BB_caltx_gain_set_2 */
-#define PHY_BB_CALTX_GAIN_SET_2_ADDRESS 0x0000a51c
-#define PHY_BB_CALTX_GAIN_SET_2_OFFSET 0x0000a51c
-#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_2_MSB 13
-#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_2_LSB 0
-#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_2_MASK 0x00003fff
-#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_2_GET(x) (((x) & 0x00003fff) >> 0)
-#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_2_SET(x) (((x) << 0) & 0x00003fff)
-#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_3_MSB 27
-#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_3_LSB 14
-#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_3_MASK 0x0fffc000
-#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_3_GET(x) (((x) & 0x0fffc000) >> 14)
-#define PHY_BB_CALTX_GAIN_SET_2_CALTX_GAIN_SET_3_SET(x) (((x) << 14) & 0x0fffc000)
-
-/* macros for BB_caltx_gain_set_4 */
-#define PHY_BB_CALTX_GAIN_SET_4_ADDRESS 0x0000a520
-#define PHY_BB_CALTX_GAIN_SET_4_OFFSET 0x0000a520
-#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_4_MSB 13
-#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_4_LSB 0
-#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_4_MASK 0x00003fff
-#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_4_GET(x) (((x) & 0x00003fff) >> 0)
-#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_4_SET(x) (((x) << 0) & 0x00003fff)
-#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_5_MSB 27
-#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_5_LSB 14
-#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_5_MASK 0x0fffc000
-#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_5_GET(x) (((x) & 0x0fffc000) >> 14)
-#define PHY_BB_CALTX_GAIN_SET_4_CALTX_GAIN_SET_5_SET(x) (((x) << 14) & 0x0fffc000)
-
-/* macros for BB_caltx_gain_set_6 */
-#define PHY_BB_CALTX_GAIN_SET_6_ADDRESS 0x0000a524
-#define PHY_BB_CALTX_GAIN_SET_6_OFFSET 0x0000a524
-#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_6_MSB 13
-#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_6_LSB 0
-#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_6_MASK 0x00003fff
-#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_6_GET(x) (((x) & 0x00003fff) >> 0)
-#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_6_SET(x) (((x) << 0) & 0x00003fff)
-#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_7_MSB 27
-#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_7_LSB 14
-#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_7_MASK 0x0fffc000
-#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_7_GET(x) (((x) & 0x0fffc000) >> 14)
-#define PHY_BB_CALTX_GAIN_SET_6_CALTX_GAIN_SET_7_SET(x) (((x) << 14) & 0x0fffc000)
-
-/* macros for BB_caltx_gain_set_8 */
-#define PHY_BB_CALTX_GAIN_SET_8_ADDRESS 0x0000a528
-#define PHY_BB_CALTX_GAIN_SET_8_OFFSET 0x0000a528
-#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_8_MSB 13
-#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_8_LSB 0
-#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_8_MASK 0x00003fff
-#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_8_GET(x) (((x) & 0x00003fff) >> 0)
-#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_8_SET(x) (((x) << 0) & 0x00003fff)
-#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_9_MSB 27
-#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_9_LSB 14
-#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_9_MASK 0x0fffc000
-#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_9_GET(x) (((x) & 0x0fffc000) >> 14)
-#define PHY_BB_CALTX_GAIN_SET_8_CALTX_GAIN_SET_9_SET(x) (((x) << 14) & 0x0fffc000)
-
-/* macros for BB_caltx_gain_set_10 */
-#define PHY_BB_CALTX_GAIN_SET_10_ADDRESS 0x0000a52c
-#define PHY_BB_CALTX_GAIN_SET_10_OFFSET 0x0000a52c
-#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_10_MSB 13
-#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_10_LSB 0
-#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_10_MASK 0x00003fff
-#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_10_GET(x) (((x) & 0x00003fff) >> 0)
-#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_10_SET(x) (((x) << 0) & 0x00003fff)
-#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_11_MSB 27
-#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_11_LSB 14
-#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_11_MASK 0x0fffc000
-#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_11_GET(x) (((x) & 0x0fffc000) >> 14)
-#define PHY_BB_CALTX_GAIN_SET_10_CALTX_GAIN_SET_11_SET(x) (((x) << 14) & 0x0fffc000)
-
-/* macros for BB_caltx_gain_set_12 */
-#define PHY_BB_CALTX_GAIN_SET_12_ADDRESS 0x0000a530
-#define PHY_BB_CALTX_GAIN_SET_12_OFFSET 0x0000a530
-#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_12_MSB 13
-#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_12_LSB 0
-#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_12_MASK 0x00003fff
-#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_12_GET(x) (((x) & 0x00003fff) >> 0)
-#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_12_SET(x) (((x) << 0) & 0x00003fff)
-#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_13_MSB 27
-#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_13_LSB 14
-#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_13_MASK 0x0fffc000
-#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_13_GET(x) (((x) & 0x0fffc000) >> 14)
-#define PHY_BB_CALTX_GAIN_SET_12_CALTX_GAIN_SET_13_SET(x) (((x) << 14) & 0x0fffc000)
-
-/* macros for BB_caltx_gain_set_14 */
-#define PHY_BB_CALTX_GAIN_SET_14_ADDRESS 0x0000a534
-#define PHY_BB_CALTX_GAIN_SET_14_OFFSET 0x0000a534
-#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_14_MSB 13
-#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_14_LSB 0
-#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_14_MASK 0x00003fff
-#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_14_GET(x) (((x) & 0x00003fff) >> 0)
-#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_14_SET(x) (((x) << 0) & 0x00003fff)
-#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_15_MSB 27
-#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_15_LSB 14
-#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_15_MASK 0x0fffc000
-#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_15_GET(x) (((x) & 0x0fffc000) >> 14)
-#define PHY_BB_CALTX_GAIN_SET_14_CALTX_GAIN_SET_15_SET(x) (((x) << 14) & 0x0fffc000)
-
-/* macros for BB_caltx_gain_set_16 */
-#define PHY_BB_CALTX_GAIN_SET_16_ADDRESS 0x0000a538
-#define PHY_BB_CALTX_GAIN_SET_16_OFFSET 0x0000a538
-#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_16_MSB 13
-#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_16_LSB 0
-#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_16_MASK 0x00003fff
-#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_16_GET(x) (((x) & 0x00003fff) >> 0)
-#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_16_SET(x) (((x) << 0) & 0x00003fff)
-#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_17_MSB 27
-#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_17_LSB 14
-#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_17_MASK 0x0fffc000
-#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_17_GET(x) (((x) & 0x0fffc000) >> 14)
-#define PHY_BB_CALTX_GAIN_SET_16_CALTX_GAIN_SET_17_SET(x) (((x) << 14) & 0x0fffc000)
-
-/* macros for BB_caltx_gain_set_18 */
-#define PHY_BB_CALTX_GAIN_SET_18_ADDRESS 0x0000a53c
-#define PHY_BB_CALTX_GAIN_SET_18_OFFSET 0x0000a53c
-#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_18_MSB 13
-#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_18_LSB 0
-#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_18_MASK 0x00003fff
-#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_18_GET(x) (((x) & 0x00003fff) >> 0)
-#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_18_SET(x) (((x) << 0) & 0x00003fff)
-#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_19_MSB 27
-#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_19_LSB 14
-#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_19_MASK 0x0fffc000
-#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_19_GET(x) (((x) & 0x0fffc000) >> 14)
-#define PHY_BB_CALTX_GAIN_SET_18_CALTX_GAIN_SET_19_SET(x) (((x) << 14) & 0x0fffc000)
-
-/* macros for BB_caltx_gain_set_20 */
-#define PHY_BB_CALTX_GAIN_SET_20_ADDRESS 0x0000a540
-#define PHY_BB_CALTX_GAIN_SET_20_OFFSET 0x0000a540
-#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_20_MSB 13
-#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_20_LSB 0
-#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_20_MASK 0x00003fff
-#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_20_GET(x) (((x) & 0x00003fff) >> 0)
-#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_20_SET(x) (((x) << 0) & 0x00003fff)
-#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_21_MSB 27
-#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_21_LSB 14
-#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_21_MASK 0x0fffc000
-#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_21_GET(x) (((x) & 0x0fffc000) >> 14)
-#define PHY_BB_CALTX_GAIN_SET_20_CALTX_GAIN_SET_21_SET(x) (((x) << 14) & 0x0fffc000)
-
-/* macros for BB_caltx_gain_set_22 */
-#define PHY_BB_CALTX_GAIN_SET_22_ADDRESS 0x0000a544
-#define PHY_BB_CALTX_GAIN_SET_22_OFFSET 0x0000a544
-#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_22_MSB 13
-#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_22_LSB 0
-#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_22_MASK 0x00003fff
-#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_22_GET(x) (((x) & 0x00003fff) >> 0)
-#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_22_SET(x) (((x) << 0) & 0x00003fff)
-#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_23_MSB 27
-#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_23_LSB 14
-#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_23_MASK 0x0fffc000
-#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_23_GET(x) (((x) & 0x0fffc000) >> 14)
-#define PHY_BB_CALTX_GAIN_SET_22_CALTX_GAIN_SET_23_SET(x) (((x) << 14) & 0x0fffc000)
-
-/* macros for BB_caltx_gain_set_24 */
-#define PHY_BB_CALTX_GAIN_SET_24_ADDRESS 0x0000a548
-#define PHY_BB_CALTX_GAIN_SET_24_OFFSET 0x0000a548
-#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_24_MSB 13
-#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_24_LSB 0
-#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_24_MASK 0x00003fff
-#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_24_GET(x) (((x) & 0x00003fff) >> 0)
-#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_24_SET(x) (((x) << 0) & 0x00003fff)
-#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_25_MSB 27
-#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_25_LSB 14
-#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_25_MASK 0x0fffc000
-#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_25_GET(x) (((x) & 0x0fffc000) >> 14)
-#define PHY_BB_CALTX_GAIN_SET_24_CALTX_GAIN_SET_25_SET(x) (((x) << 14) & 0x0fffc000)
-
-/* macros for BB_caltx_gain_set_26 */
-#define PHY_BB_CALTX_GAIN_SET_26_ADDRESS 0x0000a54c
-#define PHY_BB_CALTX_GAIN_SET_26_OFFSET 0x0000a54c
-#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_26_MSB 13
-#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_26_LSB 0
-#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_26_MASK 0x00003fff
-#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_26_GET(x) (((x) & 0x00003fff) >> 0)
-#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_26_SET(x) (((x) << 0) & 0x00003fff)
-#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_27_MSB 27
-#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_27_LSB 14
-#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_27_MASK 0x0fffc000
-#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_27_GET(x) (((x) & 0x0fffc000) >> 14)
-#define PHY_BB_CALTX_GAIN_SET_26_CALTX_GAIN_SET_27_SET(x) (((x) << 14) & 0x0fffc000)
-
-/* macros for BB_caltx_gain_set_28 */
-#define PHY_BB_CALTX_GAIN_SET_28_ADDRESS 0x0000a550
-#define PHY_BB_CALTX_GAIN_SET_28_OFFSET 0x0000a550
-#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_28_MSB 13
-#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_28_LSB 0
-#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_28_MASK 0x00003fff
-#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_28_GET(x) (((x) & 0x00003fff) >> 0)
-#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_28_SET(x) (((x) << 0) & 0x00003fff)
-#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_29_MSB 27
-#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_29_LSB 14
-#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_29_MASK 0x0fffc000
-#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_29_GET(x) (((x) & 0x0fffc000) >> 14)
-#define PHY_BB_CALTX_GAIN_SET_28_CALTX_GAIN_SET_29_SET(x) (((x) << 14) & 0x0fffc000)
-
-/* macros for BB_caltx_gain_set_30 */
-#define PHY_BB_CALTX_GAIN_SET_30_ADDRESS 0x0000a554
-#define PHY_BB_CALTX_GAIN_SET_30_OFFSET 0x0000a554
-#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_30_MSB 13
-#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_30_LSB 0
-#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_30_MASK 0x00003fff
-#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_30_GET(x) (((x) & 0x00003fff) >> 0)
-#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_30_SET(x) (((x) << 0) & 0x00003fff)
-#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_31_MSB 27
-#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_31_LSB 14
-#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_31_MASK 0x0fffc000
-#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_31_GET(x) (((x) & 0x0fffc000) >> 14)
-#define PHY_BB_CALTX_GAIN_SET_30_CALTX_GAIN_SET_31_SET(x) (((x) << 14) & 0x0fffc000)
-
-/* macros for BB_txiqcal_meas_b0 */
-#define PHY_BB_TXIQCAL_MEAS_B0_ADDRESS 0x0000a558
-#define PHY_BB_TXIQCAL_MEAS_B0_OFFSET 0x0000a558
-#define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA0_0_MSB 11
-#define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA0_0_LSB 0
-#define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA0_0_MASK 0x00000fff
-#define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA0_0_GET(x) (((x) & 0x00000fff) >> 0)
-#define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA1_0_MSB 23
-#define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA1_0_LSB 12
-#define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA1_0_MASK 0x00fff000
-#define PHY_BB_TXIQCAL_MEAS_B0_TXIQC_MEAS_DATA1_0_GET(x) (((x) & 0x00fff000) >> 12)
-
-/* macros for BB_txiqcal_start */
-#define PHY_BB_TXIQCAL_START_ADDRESS 0x0000a6d8
-#define PHY_BB_TXIQCAL_START_OFFSET 0x0000a6d8
-#define PHY_BB_TXIQCAL_START_DO_TX_IQCAL_MSB 0
-#define PHY_BB_TXIQCAL_START_DO_TX_IQCAL_LSB 0
-#define PHY_BB_TXIQCAL_START_DO_TX_IQCAL_MASK 0x00000001
-#define PHY_BB_TXIQCAL_START_DO_TX_IQCAL_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_BB_TXIQCAL_START_DO_TX_IQCAL_SET(x) (((x) << 0) & 0x00000001)
-
-/* macros for BB_txiqcal_control_0 */
-#define PHY_BB_TXIQCAL_CONTROL_0_ADDRESS 0x0000a6dc
-#define PHY_BB_TXIQCAL_CONTROL_0_OFFSET 0x0000a6dc
-#define PHY_BB_TXIQCAL_CONTROL_0_IQC_TX_TABLE_SEL_MSB 0
-#define PHY_BB_TXIQCAL_CONTROL_0_IQC_TX_TABLE_SEL_LSB 0
-#define PHY_BB_TXIQCAL_CONTROL_0_IQC_TX_TABLE_SEL_MASK 0x00000001
-#define PHY_BB_TXIQCAL_CONTROL_0_IQC_TX_TABLE_SEL_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_BB_TXIQCAL_CONTROL_0_IQC_TX_TABLE_SEL_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_BB_TXIQCAL_CONTROL_0_BASE_TX_TONE_DB_MSB 6
-#define PHY_BB_TXIQCAL_CONTROL_0_BASE_TX_TONE_DB_LSB 1
-#define PHY_BB_TXIQCAL_CONTROL_0_BASE_TX_TONE_DB_MASK 0x0000007e
-#define PHY_BB_TXIQCAL_CONTROL_0_BASE_TX_TONE_DB_GET(x) (((x) & 0x0000007e) >> 1)
-#define PHY_BB_TXIQCAL_CONTROL_0_BASE_TX_TONE_DB_SET(x) (((x) << 1) & 0x0000007e)
-#define PHY_BB_TXIQCAL_CONTROL_0_MAX_TX_TONE_GAIN_MSB 12
-#define PHY_BB_TXIQCAL_CONTROL_0_MAX_TX_TONE_GAIN_LSB 7
-#define PHY_BB_TXIQCAL_CONTROL_0_MAX_TX_TONE_GAIN_MASK 0x00001f80
-#define PHY_BB_TXIQCAL_CONTROL_0_MAX_TX_TONE_GAIN_GET(x) (((x) & 0x00001f80) >> 7)
-#define PHY_BB_TXIQCAL_CONTROL_0_MAX_TX_TONE_GAIN_SET(x) (((x) << 7) & 0x00001f80)
-#define PHY_BB_TXIQCAL_CONTROL_0_MIN_TX_TONE_GAIN_MSB 18
-#define PHY_BB_TXIQCAL_CONTROL_0_MIN_TX_TONE_GAIN_LSB 13
-#define PHY_BB_TXIQCAL_CONTROL_0_MIN_TX_TONE_GAIN_MASK 0x0007e000
-#define PHY_BB_TXIQCAL_CONTROL_0_MIN_TX_TONE_GAIN_GET(x) (((x) & 0x0007e000) >> 13)
-#define PHY_BB_TXIQCAL_CONTROL_0_MIN_TX_TONE_GAIN_SET(x) (((x) << 13) & 0x0007e000)
-#define PHY_BB_TXIQCAL_CONTROL_0_CALTXSHIFT_DELAY_MSB 22
-#define PHY_BB_TXIQCAL_CONTROL_0_CALTXSHIFT_DELAY_LSB 19
-#define PHY_BB_TXIQCAL_CONTROL_0_CALTXSHIFT_DELAY_MASK 0x00780000
-#define PHY_BB_TXIQCAL_CONTROL_0_CALTXSHIFT_DELAY_GET(x) (((x) & 0x00780000) >> 19)
-#define PHY_BB_TXIQCAL_CONTROL_0_CALTXSHIFT_DELAY_SET(x) (((x) << 19) & 0x00780000)
-#define PHY_BB_TXIQCAL_CONTROL_0_LOOPBACK_DELAY_MSB 29
-#define PHY_BB_TXIQCAL_CONTROL_0_LOOPBACK_DELAY_LSB 23
-#define PHY_BB_TXIQCAL_CONTROL_0_LOOPBACK_DELAY_MASK 0x3f800000
-#define PHY_BB_TXIQCAL_CONTROL_0_LOOPBACK_DELAY_GET(x) (((x) & 0x3f800000) >> 23)
-#define PHY_BB_TXIQCAL_CONTROL_0_LOOPBACK_DELAY_SET(x) (((x) << 23) & 0x3f800000)
-
-/* macros for BB_txiqcal_control_1 */
-#define PHY_BB_TXIQCAL_CONTROL_1_ADDRESS 0x0000a6e0
-#define PHY_BB_TXIQCAL_CONTROL_1_OFFSET 0x0000a6e0
-#define PHY_BB_TXIQCAL_CONTROL_1_RX_INIT_GAIN_DB_MSB 5
-#define PHY_BB_TXIQCAL_CONTROL_1_RX_INIT_GAIN_DB_LSB 0
-#define PHY_BB_TXIQCAL_CONTROL_1_RX_INIT_GAIN_DB_MASK 0x0000003f
-#define PHY_BB_TXIQCAL_CONTROL_1_RX_INIT_GAIN_DB_GET(x) (((x) & 0x0000003f) >> 0)
-#define PHY_BB_TXIQCAL_CONTROL_1_RX_INIT_GAIN_DB_SET(x) (((x) << 0) & 0x0000003f)
-#define PHY_BB_TXIQCAL_CONTROL_1_MAX_RX_GAIN_DB_MSB 11
-#define PHY_BB_TXIQCAL_CONTROL_1_MAX_RX_GAIN_DB_LSB 6
-#define PHY_BB_TXIQCAL_CONTROL_1_MAX_RX_GAIN_DB_MASK 0x00000fc0
-#define PHY_BB_TXIQCAL_CONTROL_1_MAX_RX_GAIN_DB_GET(x) (((x) & 0x00000fc0) >> 6)
-#define PHY_BB_TXIQCAL_CONTROL_1_MAX_RX_GAIN_DB_SET(x) (((x) << 6) & 0x00000fc0)
-#define PHY_BB_TXIQCAL_CONTROL_1_MIN_RX_GAIN_DB_MSB 17
-#define PHY_BB_TXIQCAL_CONTROL_1_MIN_RX_GAIN_DB_LSB 12
-#define PHY_BB_TXIQCAL_CONTROL_1_MIN_RX_GAIN_DB_MASK 0x0003f000
-#define PHY_BB_TXIQCAL_CONTROL_1_MIN_RX_GAIN_DB_GET(x) (((x) & 0x0003f000) >> 12)
-#define PHY_BB_TXIQCAL_CONTROL_1_MIN_RX_GAIN_DB_SET(x) (((x) << 12) & 0x0003f000)
-#define PHY_BB_TXIQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_MSB 24
-#define PHY_BB_TXIQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_LSB 18
-#define PHY_BB_TXIQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_MASK 0x01fc0000
-#define PHY_BB_TXIQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_GET(x) (((x) & 0x01fc0000) >> 18)
-#define PHY_BB_TXIQCAL_CONTROL_1_IQCORR_I_Q_COFF_DELPT_SET(x) (((x) << 18) & 0x01fc0000)
-
-/* macros for BB_txiqcal_control_2 */
-#define PHY_BB_TXIQCAL_CONTROL_2_ADDRESS 0x0000a6e4
-#define PHY_BB_TXIQCAL_CONTROL_2_OFFSET 0x0000a6e4
-#define PHY_BB_TXIQCAL_CONTROL_2_IQC_FORCED_PAGAIN_MSB 3
-#define PHY_BB_TXIQCAL_CONTROL_2_IQC_FORCED_PAGAIN_LSB 0
-#define PHY_BB_TXIQCAL_CONTROL_2_IQC_FORCED_PAGAIN_MASK 0x0000000f
-#define PHY_BB_TXIQCAL_CONTROL_2_IQC_FORCED_PAGAIN_GET(x) (((x) & 0x0000000f) >> 0)
-#define PHY_BB_TXIQCAL_CONTROL_2_IQC_FORCED_PAGAIN_SET(x) (((x) << 0) & 0x0000000f)
-#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MIN_TX_GAIN_MSB 8
-#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MIN_TX_GAIN_LSB 4
-#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MIN_TX_GAIN_MASK 0x000001f0
-#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MIN_TX_GAIN_GET(x) (((x) & 0x000001f0) >> 4)
-#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MIN_TX_GAIN_SET(x) (((x) << 4) & 0x000001f0)
-#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MAX_TX_GAIN_MSB 13
-#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MAX_TX_GAIN_LSB 9
-#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MAX_TX_GAIN_MASK 0x00003e00
-#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MAX_TX_GAIN_GET(x) (((x) & 0x00003e00) >> 9)
-#define PHY_BB_TXIQCAL_CONTROL_2_IQCAL_MAX_TX_GAIN_SET(x) (((x) << 9) & 0x00003e00)
-
-/* macros for BB_txiqcal_control_3 */
-#define PHY_BB_TXIQCAL_CONTROL_3_ADDRESS 0x0000a6e8
-#define PHY_BB_TXIQCAL_CONTROL_3_OFFSET 0x0000a6e8
-#define PHY_BB_TXIQCAL_CONTROL_3_PWR_HIGH_DB_MSB 5
-#define PHY_BB_TXIQCAL_CONTROL_3_PWR_HIGH_DB_LSB 0
-#define PHY_BB_TXIQCAL_CONTROL_3_PWR_HIGH_DB_MASK 0x0000003f
-#define PHY_BB_TXIQCAL_CONTROL_3_PWR_HIGH_DB_GET(x) (((x) & 0x0000003f) >> 0)
-#define PHY_BB_TXIQCAL_CONTROL_3_PWR_HIGH_DB_SET(x) (((x) << 0) & 0x0000003f)
-#define PHY_BB_TXIQCAL_CONTROL_3_PWR_LOW_DB_MSB 11
-#define PHY_BB_TXIQCAL_CONTROL_3_PWR_LOW_DB_LSB 6
-#define PHY_BB_TXIQCAL_CONTROL_3_PWR_LOW_DB_MASK 0x00000fc0
-#define PHY_BB_TXIQCAL_CONTROL_3_PWR_LOW_DB_GET(x) (((x) & 0x00000fc0) >> 6)
-#define PHY_BB_TXIQCAL_CONTROL_3_PWR_LOW_DB_SET(x) (((x) << 6) & 0x00000fc0)
-#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_TONE_PHS_STEP_MSB 21
-#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_TONE_PHS_STEP_LSB 12
-#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_TONE_PHS_STEP_MASK 0x003ff000
-#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_TONE_PHS_STEP_GET(x) (((x) & 0x003ff000) >> 12)
-#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_TONE_PHS_STEP_SET(x) (((x) << 12) & 0x003ff000)
-#define PHY_BB_TXIQCAL_CONTROL_3_DC_EST_LEN_MSB 23
-#define PHY_BB_TXIQCAL_CONTROL_3_DC_EST_LEN_LSB 22
-#define PHY_BB_TXIQCAL_CONTROL_3_DC_EST_LEN_MASK 0x00c00000
-#define PHY_BB_TXIQCAL_CONTROL_3_DC_EST_LEN_GET(x) (((x) & 0x00c00000) >> 22)
-#define PHY_BB_TXIQCAL_CONTROL_3_DC_EST_LEN_SET(x) (((x) << 22) & 0x00c00000)
-#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_LEN_MSB 24
-#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_LEN_LSB 24
-#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_LEN_MASK 0x01000000
-#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_LEN_GET(x) (((x) & 0x01000000) >> 24)
-#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_LEN_SET(x) (((x) << 24) & 0x01000000)
-#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_SEL_MSB 26
-#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_SEL_LSB 25
-#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_SEL_MASK 0x06000000
-#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_SEL_GET(x) (((x) & 0x06000000) >> 25)
-#define PHY_BB_TXIQCAL_CONTROL_3_ADC_SAT_SEL_SET(x) (((x) << 25) & 0x06000000)
-#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_MEAS_LEN_MSB 28
-#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_MEAS_LEN_LSB 27
-#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_MEAS_LEN_MASK 0x18000000
-#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_MEAS_LEN_GET(x) (((x) & 0x18000000) >> 27)
-#define PHY_BB_TXIQCAL_CONTROL_3_IQCAL_MEAS_LEN_SET(x) (((x) << 27) & 0x18000000)
-#define PHY_BB_TXIQCAL_CONTROL_3_DESIRED_SIZE_DB_MSB 30
-#define PHY_BB_TXIQCAL_CONTROL_3_DESIRED_SIZE_DB_LSB 29
-#define PHY_BB_TXIQCAL_CONTROL_3_DESIRED_SIZE_DB_MASK 0x60000000
-#define PHY_BB_TXIQCAL_CONTROL_3_DESIRED_SIZE_DB_GET(x) (((x) & 0x60000000) >> 29)
-#define PHY_BB_TXIQCAL_CONTROL_3_DESIRED_SIZE_DB_SET(x) (((x) << 29) & 0x60000000)
-#define PHY_BB_TXIQCAL_CONTROL_3_TX_IQCORR_EN_MSB 31
-#define PHY_BB_TXIQCAL_CONTROL_3_TX_IQCORR_EN_LSB 31
-#define PHY_BB_TXIQCAL_CONTROL_3_TX_IQCORR_EN_MASK 0x80000000
-#define PHY_BB_TXIQCAL_CONTROL_3_TX_IQCORR_EN_GET(x) (((x) & 0x80000000) >> 31)
-#define PHY_BB_TXIQCAL_CONTROL_3_TX_IQCORR_EN_SET(x) (((x) << 31) & 0x80000000)
-
-/* macros for BB_txiq_corr_coeff_01_b0 */
-#define PHY_BB_TXIQ_CORR_COEFF_01_B0_ADDRESS 0x0000a6ec
-#define PHY_BB_TXIQ_CORR_COEFF_01_B0_OFFSET 0x0000a6ec
-#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_0_0_MSB 13
-#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_0_0_LSB 0
-#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_0_0_MASK 0x00003fff
-#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_0_0_GET(x) (((x) & 0x00003fff) >> 0)
-#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_0_0_SET(x) (((x) << 0) & 0x00003fff)
-#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_1_0_MSB 27
-#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_1_0_LSB 14
-#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_1_0_MASK 0x0fffc000
-#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_1_0_GET(x) (((x) & 0x0fffc000) >> 14)
-#define PHY_BB_TXIQ_CORR_COEFF_01_B0_IQC_COEFF_TABLE_1_0_SET(x) (((x) << 14) & 0x0fffc000)
-
-/* macros for BB_txiq_corr_coeff_23_b0 */
-#define PHY_BB_TXIQ_CORR_COEFF_23_B0_ADDRESS 0x0000a6f0
-#define PHY_BB_TXIQ_CORR_COEFF_23_B0_OFFSET 0x0000a6f0
-#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_2_0_MSB 13
-#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_2_0_LSB 0
-#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_2_0_MASK 0x00003fff
-#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_2_0_GET(x) (((x) & 0x00003fff) >> 0)
-#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_2_0_SET(x) (((x) << 0) & 0x00003fff)
-#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_3_0_MSB 27
-#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_3_0_LSB 14
-#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_3_0_MASK 0x0fffc000
-#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_3_0_GET(x) (((x) & 0x0fffc000) >> 14)
-#define PHY_BB_TXIQ_CORR_COEFF_23_B0_IQC_COEFF_TABLE_3_0_SET(x) (((x) << 14) & 0x0fffc000)
-
-/* macros for BB_txiq_corr_coeff_45_b0 */
-#define PHY_BB_TXIQ_CORR_COEFF_45_B0_ADDRESS 0x0000a6f4
-#define PHY_BB_TXIQ_CORR_COEFF_45_B0_OFFSET 0x0000a6f4
-#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_4_0_MSB 13
-#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_4_0_LSB 0
-#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_4_0_MASK 0x00003fff
-#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_4_0_GET(x) (((x) & 0x00003fff) >> 0)
-#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_4_0_SET(x) (((x) << 0) & 0x00003fff)
-#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_5_0_MSB 27
-#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_5_0_LSB 14
-#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_5_0_MASK 0x0fffc000
-#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_5_0_GET(x) (((x) & 0x0fffc000) >> 14)
-#define PHY_BB_TXIQ_CORR_COEFF_45_B0_IQC_COEFF_TABLE_5_0_SET(x) (((x) << 14) & 0x0fffc000)
-
-/* macros for BB_txiq_corr_coeff_67_b0 */
-#define PHY_BB_TXIQ_CORR_COEFF_67_B0_ADDRESS 0x0000a6f8
-#define PHY_BB_TXIQ_CORR_COEFF_67_B0_OFFSET 0x0000a6f8
-#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_6_0_MSB 13
-#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_6_0_LSB 0
-#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_6_0_MASK 0x00003fff
-#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_6_0_GET(x) (((x) & 0x00003fff) >> 0)
-#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_6_0_SET(x) (((x) << 0) & 0x00003fff)
-#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_7_0_MSB 27
-#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_7_0_LSB 14
-#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_7_0_MASK 0x0fffc000
-#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_7_0_GET(x) (((x) & 0x0fffc000) >> 14)
-#define PHY_BB_TXIQ_CORR_COEFF_67_B0_IQC_COEFF_TABLE_7_0_SET(x) (((x) << 14) & 0x0fffc000)
-
-/* macros for BB_txiq_corr_coeff_89_b0 */
-#define PHY_BB_TXIQ_CORR_COEFF_89_B0_ADDRESS 0x0000a6fc
-#define PHY_BB_TXIQ_CORR_COEFF_89_B0_OFFSET 0x0000a6fc
-#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_8_0_MSB 13
-#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_8_0_LSB 0
-#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_8_0_MASK 0x00003fff
-#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_8_0_GET(x) (((x) & 0x00003fff) >> 0)
-#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_8_0_SET(x) (((x) << 0) & 0x00003fff)
-#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_9_0_MSB 27
-#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_9_0_LSB 14
-#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_9_0_MASK 0x0fffc000
-#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_9_0_GET(x) (((x) & 0x0fffc000) >> 14)
-#define PHY_BB_TXIQ_CORR_COEFF_89_B0_IQC_COEFF_TABLE_9_0_SET(x) (((x) << 14) & 0x0fffc000)
-
-/* macros for BB_txiq_corr_coeff_ab_b0 */
-#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_ADDRESS 0x0000a700
-#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_OFFSET 0x0000a700
-#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_A_0_MSB 13
-#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_A_0_LSB 0
-#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_A_0_MASK 0x00003fff
-#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_A_0_GET(x) (((x) & 0x00003fff) >> 0)
-#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_A_0_SET(x) (((x) << 0) & 0x00003fff)
-#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_B_0_MSB 27
-#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_B_0_LSB 14
-#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_B_0_MASK 0x0fffc000
-#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_B_0_GET(x) (((x) & 0x0fffc000) >> 14)
-#define PHY_BB_TXIQ_CORR_COEFF_AB_B0_IQC_COEFF_TABLE_B_0_SET(x) (((x) << 14) & 0x0fffc000)
-
-/* macros for BB_txiq_corr_coeff_cd_b0 */
-#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_ADDRESS 0x0000a704
-#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_OFFSET 0x0000a704
-#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_C_0_MSB 13
-#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_C_0_LSB 0
-#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_C_0_MASK 0x00003fff
-#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_C_0_GET(x) (((x) & 0x00003fff) >> 0)
-#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_C_0_SET(x) (((x) << 0) & 0x00003fff)
-#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_D_0_MSB 27
-#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_D_0_LSB 14
-#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_D_0_MASK 0x0fffc000
-#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_D_0_GET(x) (((x) & 0x0fffc000) >> 14)
-#define PHY_BB_TXIQ_CORR_COEFF_CD_B0_IQC_COEFF_TABLE_D_0_SET(x) (((x) << 14) & 0x0fffc000)
-
-/* macros for BB_txiq_corr_coeff_ef_b0 */
-#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_ADDRESS 0x0000a708
-#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_OFFSET 0x0000a708
-#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_E_0_MSB 13
-#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_E_0_LSB 0
-#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_E_0_MASK 0x00003fff
-#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_E_0_GET(x) (((x) & 0x00003fff) >> 0)
-#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_E_0_SET(x) (((x) << 0) & 0x00003fff)
-#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_F_0_MSB 27
-#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_F_0_LSB 14
-#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_F_0_MASK 0x0fffc000
-#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_F_0_GET(x) (((x) & 0x0fffc000) >> 14)
-#define PHY_BB_TXIQ_CORR_COEFF_EF_B0_IQC_COEFF_TABLE_F_0_SET(x) (((x) << 14) & 0x0fffc000)
-
-/* macros for BB_cal_rxbb_gain_tbl_0 */
-#define PHY_BB_CAL_RXBB_GAIN_TBL_0_ADDRESS 0x0000a70c
-#define PHY_BB_CAL_RXBB_GAIN_TBL_0_OFFSET 0x0000a70c
-#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_0_MSB 5
-#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_0_LSB 0
-#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_0_MASK 0x0000003f
-#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_0_GET(x) (((x) & 0x0000003f) >> 0)
-#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_0_SET(x) (((x) << 0) & 0x0000003f)
-#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_1_MSB 11
-#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_1_LSB 6
-#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_1_MASK 0x00000fc0
-#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_1_GET(x) (((x) & 0x00000fc0) >> 6)
-#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_1_SET(x) (((x) << 6) & 0x00000fc0)
-#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_2_MSB 17
-#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_2_LSB 12
-#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_2_MASK 0x0003f000
-#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_2_GET(x) (((x) & 0x0003f000) >> 12)
-#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_2_SET(x) (((x) << 12) & 0x0003f000)
-#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_3_MSB 23
-#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_3_LSB 18
-#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_3_MASK 0x00fc0000
-#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_3_GET(x) (((x) & 0x00fc0000) >> 18)
-#define PHY_BB_CAL_RXBB_GAIN_TBL_0_TXCAL_RX_BB_GAIN_TABLE_3_SET(x) (((x) << 18) & 0x00fc0000)
-
-/* macros for BB_cal_rxbb_gain_tbl_4 */
-#define PHY_BB_CAL_RXBB_GAIN_TBL_4_ADDRESS 0x0000a710
-#define PHY_BB_CAL_RXBB_GAIN_TBL_4_OFFSET 0x0000a710
-#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_4_MSB 5
-#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_4_LSB 0
-#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_4_MASK 0x0000003f
-#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_4_GET(x) (((x) & 0x0000003f) >> 0)
-#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_4_SET(x) (((x) << 0) & 0x0000003f)
-#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_5_MSB 11
-#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_5_LSB 6
-#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_5_MASK 0x00000fc0
-#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_5_GET(x) (((x) & 0x00000fc0) >> 6)
-#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_5_SET(x) (((x) << 6) & 0x00000fc0)
-#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_6_MSB 17
-#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_6_LSB 12
-#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_6_MASK 0x0003f000
-#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_6_GET(x) (((x) & 0x0003f000) >> 12)
-#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_6_SET(x) (((x) << 12) & 0x0003f000)
-#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_7_MSB 23
-#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_7_LSB 18
-#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_7_MASK 0x00fc0000
-#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_7_GET(x) (((x) & 0x00fc0000) >> 18)
-#define PHY_BB_CAL_RXBB_GAIN_TBL_4_TXCAL_RX_BB_GAIN_TABLE_7_SET(x) (((x) << 18) & 0x00fc0000)
-
-/* macros for BB_cal_rxbb_gain_tbl_8 */
-#define PHY_BB_CAL_RXBB_GAIN_TBL_8_ADDRESS 0x0000a714
-#define PHY_BB_CAL_RXBB_GAIN_TBL_8_OFFSET 0x0000a714
-#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_8_MSB 5
-#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_8_LSB 0
-#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_8_MASK 0x0000003f
-#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_8_GET(x) (((x) & 0x0000003f) >> 0)
-#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_8_SET(x) (((x) << 0) & 0x0000003f)
-#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_9_MSB 11
-#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_9_LSB 6
-#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_9_MASK 0x00000fc0
-#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_9_GET(x) (((x) & 0x00000fc0) >> 6)
-#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_9_SET(x) (((x) << 6) & 0x00000fc0)
-#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_10_MSB 17
-#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_10_LSB 12
-#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_10_MASK 0x0003f000
-#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_10_GET(x) (((x) & 0x0003f000) >> 12)
-#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_10_SET(x) (((x) << 12) & 0x0003f000)
-#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_11_MSB 23
-#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_11_LSB 18
-#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_11_MASK 0x00fc0000
-#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_11_GET(x) (((x) & 0x00fc0000) >> 18)
-#define PHY_BB_CAL_RXBB_GAIN_TBL_8_TXCAL_RX_BB_GAIN_TABLE_11_SET(x) (((x) << 18) & 0x00fc0000)
-
-/* macros for BB_cal_rxbb_gain_tbl_12 */
-#define PHY_BB_CAL_RXBB_GAIN_TBL_12_ADDRESS 0x0000a718
-#define PHY_BB_CAL_RXBB_GAIN_TBL_12_OFFSET 0x0000a718
-#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_12_MSB 5
-#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_12_LSB 0
-#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_12_MASK 0x0000003f
-#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_12_GET(x) (((x) & 0x0000003f) >> 0)
-#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_12_SET(x) (((x) << 0) & 0x0000003f)
-#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_13_MSB 11
-#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_13_LSB 6
-#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_13_MASK 0x00000fc0
-#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_13_GET(x) (((x) & 0x00000fc0) >> 6)
-#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_13_SET(x) (((x) << 6) & 0x00000fc0)
-#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_14_MSB 17
-#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_14_LSB 12
-#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_14_MASK 0x0003f000
-#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_14_GET(x) (((x) & 0x0003f000) >> 12)
-#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_14_SET(x) (((x) << 12) & 0x0003f000)
-#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_15_MSB 23
-#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_15_LSB 18
-#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_15_MASK 0x00fc0000
-#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_15_GET(x) (((x) & 0x00fc0000) >> 18)
-#define PHY_BB_CAL_RXBB_GAIN_TBL_12_TXCAL_RX_BB_GAIN_TABLE_15_SET(x) (((x) << 18) & 0x00fc0000)
-
-/* macros for BB_cal_rxbb_gain_tbl_16 */
-#define PHY_BB_CAL_RXBB_GAIN_TBL_16_ADDRESS 0x0000a71c
-#define PHY_BB_CAL_RXBB_GAIN_TBL_16_OFFSET 0x0000a71c
-#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_16_MSB 5
-#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_16_LSB 0
-#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_16_MASK 0x0000003f
-#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_16_GET(x) (((x) & 0x0000003f) >> 0)
-#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_16_SET(x) (((x) << 0) & 0x0000003f)
-#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_17_MSB 11
-#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_17_LSB 6
-#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_17_MASK 0x00000fc0
-#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_17_GET(x) (((x) & 0x00000fc0) >> 6)
-#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_17_SET(x) (((x) << 6) & 0x00000fc0)
-#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_18_MSB 17
-#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_18_LSB 12
-#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_18_MASK 0x0003f000
-#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_18_GET(x) (((x) & 0x0003f000) >> 12)
-#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_18_SET(x) (((x) << 12) & 0x0003f000)
-#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_19_MSB 23
-#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_19_LSB 18
-#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_19_MASK 0x00fc0000
-#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_19_GET(x) (((x) & 0x00fc0000) >> 18)
-#define PHY_BB_CAL_RXBB_GAIN_TBL_16_TXCAL_RX_BB_GAIN_TABLE_19_SET(x) (((x) << 18) & 0x00fc0000)
-
-/* macros for BB_cal_rxbb_gain_tbl_20 */
-#define PHY_BB_CAL_RXBB_GAIN_TBL_20_ADDRESS 0x0000a720
-#define PHY_BB_CAL_RXBB_GAIN_TBL_20_OFFSET 0x0000a720
-#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_20_MSB 5
-#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_20_LSB 0
-#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_20_MASK 0x0000003f
-#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_20_GET(x) (((x) & 0x0000003f) >> 0)
-#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_20_SET(x) (((x) << 0) & 0x0000003f)
-#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_21_MSB 11
-#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_21_LSB 6
-#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_21_MASK 0x00000fc0
-#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_21_GET(x) (((x) & 0x00000fc0) >> 6)
-#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_21_SET(x) (((x) << 6) & 0x00000fc0)
-#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_22_MSB 17
-#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_22_LSB 12
-#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_22_MASK 0x0003f000
-#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_22_GET(x) (((x) & 0x0003f000) >> 12)
-#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_22_SET(x) (((x) << 12) & 0x0003f000)
-#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_23_MSB 23
-#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_23_LSB 18
-#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_23_MASK 0x00fc0000
-#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_23_GET(x) (((x) & 0x00fc0000) >> 18)
-#define PHY_BB_CAL_RXBB_GAIN_TBL_20_TXCAL_RX_BB_GAIN_TABLE_23_SET(x) (((x) << 18) & 0x00fc0000)
-
-/* macros for BB_cal_rxbb_gain_tbl_24 */
-#define PHY_BB_CAL_RXBB_GAIN_TBL_24_ADDRESS 0x0000a724
-#define PHY_BB_CAL_RXBB_GAIN_TBL_24_OFFSET 0x0000a724
-#define PHY_BB_CAL_RXBB_GAIN_TBL_24_TXCAL_RX_BB_GAIN_TABLE_24_MSB 5
-#define PHY_BB_CAL_RXBB_GAIN_TBL_24_TXCAL_RX_BB_GAIN_TABLE_24_LSB 0
-#define PHY_BB_CAL_RXBB_GAIN_TBL_24_TXCAL_RX_BB_GAIN_TABLE_24_MASK 0x0000003f
-#define PHY_BB_CAL_RXBB_GAIN_TBL_24_TXCAL_RX_BB_GAIN_TABLE_24_GET(x) (((x) & 0x0000003f) >> 0)
-#define PHY_BB_CAL_RXBB_GAIN_TBL_24_TXCAL_RX_BB_GAIN_TABLE_24_SET(x) (((x) << 0) & 0x0000003f)
-
-/* macros for BB_txiqcal_status_b0 */
-#define PHY_BB_TXIQCAL_STATUS_B0_ADDRESS 0x0000a728
-#define PHY_BB_TXIQCAL_STATUS_B0_OFFSET 0x0000a728
-#define PHY_BB_TXIQCAL_STATUS_B0_TXIQCAL_FAILED_0_MSB 0
-#define PHY_BB_TXIQCAL_STATUS_B0_TXIQCAL_FAILED_0_LSB 0
-#define PHY_BB_TXIQCAL_STATUS_B0_TXIQCAL_FAILED_0_MASK 0x00000001
-#define PHY_BB_TXIQCAL_STATUS_B0_TXIQCAL_FAILED_0_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_BB_TXIQCAL_STATUS_B0_CALIBRATED_GAINS_0_MSB 5
-#define PHY_BB_TXIQCAL_STATUS_B0_CALIBRATED_GAINS_0_LSB 1
-#define PHY_BB_TXIQCAL_STATUS_B0_CALIBRATED_GAINS_0_MASK 0x0000003e
-#define PHY_BB_TXIQCAL_STATUS_B0_CALIBRATED_GAINS_0_GET(x) (((x) & 0x0000003e) >> 1)
-#define PHY_BB_TXIQCAL_STATUS_B0_TONE_GAIN_USED_0_MSB 11
-#define PHY_BB_TXIQCAL_STATUS_B0_TONE_GAIN_USED_0_LSB 6
-#define PHY_BB_TXIQCAL_STATUS_B0_TONE_GAIN_USED_0_MASK 0x00000fc0
-#define PHY_BB_TXIQCAL_STATUS_B0_TONE_GAIN_USED_0_GET(x) (((x) & 0x00000fc0) >> 6)
-#define PHY_BB_TXIQCAL_STATUS_B0_RX_GAIN_USED_0_MSB 17
-#define PHY_BB_TXIQCAL_STATUS_B0_RX_GAIN_USED_0_LSB 12
-#define PHY_BB_TXIQCAL_STATUS_B0_RX_GAIN_USED_0_MASK 0x0003f000
-#define PHY_BB_TXIQCAL_STATUS_B0_RX_GAIN_USED_0_GET(x) (((x) & 0x0003f000) >> 12)
-#define PHY_BB_TXIQCAL_STATUS_B0_LAST_MEAS_ADDR_0_MSB 24
-#define PHY_BB_TXIQCAL_STATUS_B0_LAST_MEAS_ADDR_0_LSB 18
-#define PHY_BB_TXIQCAL_STATUS_B0_LAST_MEAS_ADDR_0_MASK 0x01fc0000
-#define PHY_BB_TXIQCAL_STATUS_B0_LAST_MEAS_ADDR_0_GET(x) (((x) & 0x01fc0000) >> 18)
-
-/* macros for BB_paprd_trainer_cntl1 */
-#define PHY_BB_PAPRD_TRAINER_CNTL1_ADDRESS 0x0000a72c
-#define PHY_BB_PAPRD_TRAINER_CNTL1_OFFSET 0x0000a72c
-#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TRAIN_ENABLE_MSB 0
-#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TRAIN_ENABLE_LSB 0
-#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TRAIN_ENABLE_MASK 0x00000001
-#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TRAIN_ENABLE_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TRAIN_ENABLE_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_MSB 7
-#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_LSB 1
-#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_MASK 0x000000fe
-#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_GET(x) (((x) & 0x000000fe) >> 1)
-#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_AGC2_SETTLING_SET(x) (((x) << 1) & 0x000000fe)
-#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_MSB 8
-#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_LSB 8
-#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_MASK 0x00000100
-#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_GET(x) (((x) & 0x00000100) >> 8)
-#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_IQCORR_ENABLE_SET(x) (((x) << 8) & 0x00000100)
-#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_MSB 9
-#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_LSB 9
-#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_MASK 0x00000200
-#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_GET(x) (((x) & 0x00000200) >> 9)
-#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_RX_BB_GAIN_FORCE_SET(x) (((x) << 9) & 0x00000200)
-#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_MSB 10
-#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_LSB 10
-#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_MASK 0x00000400
-#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_GET(x) (((x) & 0x00000400) >> 10)
-#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_TX_GAIN_FORCE_SET(x) (((x) << 10) & 0x00000400)
-#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE_MSB 11
-#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE_LSB 11
-#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE_MASK 0x00000800
-#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE_GET(x) (((x) & 0x00000800) >> 11)
-#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_ENABLE_SET(x) (((x) << 11) & 0x00000800)
-#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_MSB 18
-#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_LSB 12
-#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_MASK 0x0007f000
-#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_GET(x) (((x) & 0x0007f000) >> 12)
-#define PHY_BB_PAPRD_TRAINER_CNTL1_CF_PAPRD_LB_SKIP_SET(x) (((x) << 12) & 0x0007f000)
-
-/* macros for BB_paprd_trainer_cntl2 */
-#define PHY_BB_PAPRD_TRAINER_CNTL2_ADDRESS 0x0000a730
-#define PHY_BB_PAPRD_TRAINER_CNTL2_OFFSET 0x0000a730
-#define PHY_BB_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_MSB 31
-#define PHY_BB_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_LSB 0
-#define PHY_BB_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_MASK 0xffffffff
-#define PHY_BB_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_GET(x) (((x) & 0xffffffff) >> 0)
-#define PHY_BB_PAPRD_TRAINER_CNTL2_CF_PAPRD_INIT_RX_BB_GAIN_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_paprd_trainer_cntl3 */
-#define PHY_BB_PAPRD_TRAINER_CNTL3_ADDRESS 0x0000a734
-#define PHY_BB_PAPRD_TRAINER_CNTL3_OFFSET 0x0000a734
-#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_MSB 5
-#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_LSB 0
-#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_MASK 0x0000003f
-#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_GET(x) (((x) & 0x0000003f) >> 0)
-#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_ADC_DESIRED_SIZE_SET(x) (((x) << 0) & 0x0000003f)
-#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_MSB 11
-#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_LSB 6
-#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_MASK 0x00000fc0
-#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_GET(x) (((x) & 0x00000fc0) >> 6)
-#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_QUICK_DROP_SET(x) (((x) << 6) & 0x00000fc0)
-#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_MSB 16
-#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_LSB 12
-#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_MASK 0x0001f000
-#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_GET(x) (((x) & 0x0001f000) >> 12)
-#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_MIN_LOOPBACK_DEL_SET(x) (((x) << 12) & 0x0001f000)
-#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_MSB 19
-#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_LSB 17
-#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_MASK 0x000e0000
-#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_GET(x) (((x) & 0x000e0000) >> 17)
-#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_NUM_CORR_STAGES_SET(x) (((x) << 17) & 0x000e0000)
-#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_MSB 23
-#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_LSB 20
-#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_MASK 0x00f00000
-#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_GET(x) (((x) & 0x00f00000) >> 20)
-#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_COARSE_CORR_LEN_SET(x) (((x) << 20) & 0x00f00000)
-#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_MSB 27
-#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_LSB 24
-#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_MASK 0x0f000000
-#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_GET(x) (((x) & 0x0f000000) >> 24)
-#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_FINE_CORR_LEN_SET(x) (((x) << 24) & 0x0f000000)
-#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_MSB 28
-#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_LSB 28
-#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_MASK 0x10000000
-#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_GET(x) (((x) & 0x10000000) >> 28)
-#define PHY_BB_PAPRD_TRAINER_CNTL3_CF_PAPRD_BBTXMIX_DISABLE_SET(x) (((x) << 28) & 0x10000000)
-
-/* macros for BB_paprd_trainer_cntl4 */
-#define PHY_BB_PAPRD_TRAINER_CNTL4_ADDRESS 0x0000a738
-#define PHY_BB_PAPRD_TRAINER_CNTL4_OFFSET 0x0000a738
-#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_MSB 11
-#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_LSB 0
-#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_MASK 0x00000fff
-#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_GET(x) (((x) & 0x00000fff) >> 0)
-#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_MIN_CORR_SET(x) (((x) << 0) & 0x00000fff)
-#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_MSB 15
-#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_LSB 12
-#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_MASK 0x0000f000
-#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_GET(x) (((x) & 0x0000f000) >> 12)
-#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_SAFETY_DELTA_SET(x) (((x) << 12) & 0x0000f000)
-#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_MSB 25
-#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_LSB 16
-#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_MASK 0x03ff0000
-#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_GET(x) (((x) & 0x03ff0000) >> 16)
-#define PHY_BB_PAPRD_TRAINER_CNTL4_CF_PAPRD_NUM_TRAIN_SAMPLES_SET(x) (((x) << 16) & 0x03ff0000)
-
-/* macros for BB_paprd_trainer_stat1 */
-#define PHY_BB_PAPRD_TRAINER_STAT1_ADDRESS 0x0000a73c
-#define PHY_BB_PAPRD_TRAINER_STAT1_OFFSET 0x0000a73c
-#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_MSB 0
-#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_LSB 0
-#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_MASK 0x00000001
-#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_DONE_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE_MSB 1
-#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE_LSB 1
-#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE_MASK 0x00000002
-#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_INCOMPLETE_GET(x) (((x) & 0x00000002) >> 1)
-#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR_MSB 2
-#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR_LSB 2
-#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR_MASK 0x00000004
-#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_CORR_ERR_GET(x) (((x) & 0x00000004) >> 2)
-#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE_MSB 3
-#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE_LSB 3
-#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE_MASK 0x00000008
-#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_TRAIN_ACTIVE_GET(x) (((x) & 0x00000008) >> 3)
-#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX_MSB 8
-#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX_LSB 4
-#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX_MASK 0x000001f0
-#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_RX_GAIN_IDX_GET(x) (((x) & 0x000001f0) >> 4)
-#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR_MSB 16
-#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR_LSB 9
-#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR_MASK 0x0001fe00
-#define PHY_BB_PAPRD_TRAINER_STAT1_PAPRD_AGC2_PWR_GET(x) (((x) & 0x0001fe00) >> 9)
-
-/* macros for BB_paprd_trainer_stat2 */
-#define PHY_BB_PAPRD_TRAINER_STAT2_ADDRESS 0x0000a740
-#define PHY_BB_PAPRD_TRAINER_STAT2_OFFSET 0x0000a740
-#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL_MSB 15
-#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL_LSB 0
-#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL_MASK 0x0000ffff
-#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_VAL_GET(x) (((x) & 0x0000ffff) >> 0)
-#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX_MSB 20
-#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX_LSB 16
-#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX_MASK 0x001f0000
-#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_COARSE_IDX_GET(x) (((x) & 0x001f0000) >> 16)
-#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX_MSB 22
-#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX_LSB 21
-#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX_MASK 0x00600000
-#define PHY_BB_PAPRD_TRAINER_STAT2_PAPRD_FINE_IDX_GET(x) (((x) & 0x00600000) >> 21)
-
-/* macros for BB_paprd_trainer_stat3 */
-#define PHY_BB_PAPRD_TRAINER_STAT3_ADDRESS 0x0000a744
-#define PHY_BB_PAPRD_TRAINER_STAT3_OFFSET 0x0000a744
-#define PHY_BB_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT_MSB 19
-#define PHY_BB_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT_LSB 0
-#define PHY_BB_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT_MASK 0x000fffff
-#define PHY_BB_PAPRD_TRAINER_STAT3_PAPRD_TRAIN_SAMPLES_CNT_GET(x) (((x) & 0x000fffff) >> 0)
-
-/* macros for BB_fcal_1 */
-#define PHY_BB_FCAL_1_ADDRESS 0x0000a7d8
-#define PHY_BB_FCAL_1_OFFSET 0x0000a7d8
-#define PHY_BB_FCAL_1_FLC_PB_FSTEP_MSB 9
-#define PHY_BB_FCAL_1_FLC_PB_FSTEP_LSB 0
-#define PHY_BB_FCAL_1_FLC_PB_FSTEP_MASK 0x000003ff
-#define PHY_BB_FCAL_1_FLC_PB_FSTEP_GET(x) (((x) & 0x000003ff) >> 0)
-#define PHY_BB_FCAL_1_FLC_PB_FSTEP_SET(x) (((x) << 0) & 0x000003ff)
-#define PHY_BB_FCAL_1_FLC_SB_FSTEP_MSB 19
-#define PHY_BB_FCAL_1_FLC_SB_FSTEP_LSB 10
-#define PHY_BB_FCAL_1_FLC_SB_FSTEP_MASK 0x000ffc00
-#define PHY_BB_FCAL_1_FLC_SB_FSTEP_GET(x) (((x) & 0x000ffc00) >> 10)
-#define PHY_BB_FCAL_1_FLC_SB_FSTEP_SET(x) (((x) << 10) & 0x000ffc00)
-#define PHY_BB_FCAL_1_FLC_PB_ATTEN_MSB 24
-#define PHY_BB_FCAL_1_FLC_PB_ATTEN_LSB 20
-#define PHY_BB_FCAL_1_FLC_PB_ATTEN_MASK 0x01f00000
-#define PHY_BB_FCAL_1_FLC_PB_ATTEN_GET(x) (((x) & 0x01f00000) >> 20)
-#define PHY_BB_FCAL_1_FLC_PB_ATTEN_SET(x) (((x) << 20) & 0x01f00000)
-#define PHY_BB_FCAL_1_FLC_SB_ATTEN_MSB 29
-#define PHY_BB_FCAL_1_FLC_SB_ATTEN_LSB 25
-#define PHY_BB_FCAL_1_FLC_SB_ATTEN_MASK 0x3e000000
-#define PHY_BB_FCAL_1_FLC_SB_ATTEN_GET(x) (((x) & 0x3e000000) >> 25)
-#define PHY_BB_FCAL_1_FLC_SB_ATTEN_SET(x) (((x) << 25) & 0x3e000000)
-
-/* macros for BB_fcal_2_b0 */
-#define PHY_BB_FCAL_2_B0_ADDRESS 0x0000a7dc
-#define PHY_BB_FCAL_2_B0_OFFSET 0x0000a7dc
-#define PHY_BB_FCAL_2_B0_FLC_PWR_THRESH_MSB 2
-#define PHY_BB_FCAL_2_B0_FLC_PWR_THRESH_LSB 0
-#define PHY_BB_FCAL_2_B0_FLC_PWR_THRESH_MASK 0x00000007
-#define PHY_BB_FCAL_2_B0_FLC_PWR_THRESH_GET(x) (((x) & 0x00000007) >> 0)
-#define PHY_BB_FCAL_2_B0_FLC_PWR_THRESH_SET(x) (((x) << 0) & 0x00000007)
-#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_VAL_0_MSB 7
-#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_VAL_0_LSB 3
-#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_VAL_0_MASK 0x000000f8
-#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_VAL_0_GET(x) (((x) & 0x000000f8) >> 3)
-#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_VAL_0_SET(x) (((x) << 3) & 0x000000f8)
-#define PHY_BB_FCAL_2_B0_FLC_BBMISCGAIN_MSB 9
-#define PHY_BB_FCAL_2_B0_FLC_BBMISCGAIN_LSB 8
-#define PHY_BB_FCAL_2_B0_FLC_BBMISCGAIN_MASK 0x00000300
-#define PHY_BB_FCAL_2_B0_FLC_BBMISCGAIN_GET(x) (((x) & 0x00000300) >> 8)
-#define PHY_BB_FCAL_2_B0_FLC_BBMISCGAIN_SET(x) (((x) << 8) & 0x00000300)
-#define PHY_BB_FCAL_2_B0_FLC_BB1DBGAIN_MSB 12
-#define PHY_BB_FCAL_2_B0_FLC_BB1DBGAIN_LSB 10
-#define PHY_BB_FCAL_2_B0_FLC_BB1DBGAIN_MASK 0x00001c00
-#define PHY_BB_FCAL_2_B0_FLC_BB1DBGAIN_GET(x) (((x) & 0x00001c00) >> 10)
-#define PHY_BB_FCAL_2_B0_FLC_BB1DBGAIN_SET(x) (((x) << 10) & 0x00001c00)
-#define PHY_BB_FCAL_2_B0_FLC_BB6DBGAIN_MSB 14
-#define PHY_BB_FCAL_2_B0_FLC_BB6DBGAIN_LSB 13
-#define PHY_BB_FCAL_2_B0_FLC_BB6DBGAIN_MASK 0x00006000
-#define PHY_BB_FCAL_2_B0_FLC_BB6DBGAIN_GET(x) (((x) & 0x00006000) >> 13)
-#define PHY_BB_FCAL_2_B0_FLC_BB6DBGAIN_SET(x) (((x) << 13) & 0x00006000)
-#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_SET_MSB 15
-#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_SET_LSB 15
-#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_SET_MASK 0x00008000
-#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_SET_GET(x) (((x) & 0x00008000) >> 15)
-#define PHY_BB_FCAL_2_B0_FLC_SW_CAP_SET_SET(x) (((x) << 15) & 0x00008000)
-#define PHY_BB_FCAL_2_B0_FLC_MEAS_WIN_MSB 18
-#define PHY_BB_FCAL_2_B0_FLC_MEAS_WIN_LSB 16
-#define PHY_BB_FCAL_2_B0_FLC_MEAS_WIN_MASK 0x00070000
-#define PHY_BB_FCAL_2_B0_FLC_MEAS_WIN_GET(x) (((x) & 0x00070000) >> 16)
-#define PHY_BB_FCAL_2_B0_FLC_MEAS_WIN_SET(x) (((x) << 16) & 0x00070000)
-#define PHY_BB_FCAL_2_B0_FLC_CAP_VAL_STATUS_0_MSB 24
-#define PHY_BB_FCAL_2_B0_FLC_CAP_VAL_STATUS_0_LSB 20
-#define PHY_BB_FCAL_2_B0_FLC_CAP_VAL_STATUS_0_MASK 0x01f00000
-#define PHY_BB_FCAL_2_B0_FLC_CAP_VAL_STATUS_0_GET(x) (((x) & 0x01f00000) >> 20)
-
-/* macros for BB_radar_bw_filter */
-#define PHY_BB_RADAR_BW_FILTER_ADDRESS 0x0000a7e0
-#define PHY_BB_RADAR_BW_FILTER_OFFSET 0x0000a7e0
-#define PHY_BB_RADAR_BW_FILTER_RADAR_AVG_BW_CHECK_MSB 0
-#define PHY_BB_RADAR_BW_FILTER_RADAR_AVG_BW_CHECK_LSB 0
-#define PHY_BB_RADAR_BW_FILTER_RADAR_AVG_BW_CHECK_MASK 0x00000001
-#define PHY_BB_RADAR_BW_FILTER_RADAR_AVG_BW_CHECK_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_BB_RADAR_BW_FILTER_RADAR_AVG_BW_CHECK_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_SRC_SEL_MSB 1
-#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_SRC_SEL_LSB 1
-#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_SRC_SEL_MASK 0x00000002
-#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_SRC_SEL_GET(x) (((x) & 0x00000002) >> 1)
-#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_SRC_SEL_SET(x) (((x) << 1) & 0x00000002)
-#define PHY_BB_RADAR_BW_FILTER_RADAR_FIRPWR_SEL_MSB 3
-#define PHY_BB_RADAR_BW_FILTER_RADAR_FIRPWR_SEL_LSB 2
-#define PHY_BB_RADAR_BW_FILTER_RADAR_FIRPWR_SEL_MASK 0x0000000c
-#define PHY_BB_RADAR_BW_FILTER_RADAR_FIRPWR_SEL_GET(x) (((x) & 0x0000000c) >> 2)
-#define PHY_BB_RADAR_BW_FILTER_RADAR_FIRPWR_SEL_SET(x) (((x) << 2) & 0x0000000c)
-#define PHY_BB_RADAR_BW_FILTER_RADAR_PULSE_WIDTH_SEL_MSB 5
-#define PHY_BB_RADAR_BW_FILTER_RADAR_PULSE_WIDTH_SEL_LSB 4
-#define PHY_BB_RADAR_BW_FILTER_RADAR_PULSE_WIDTH_SEL_MASK 0x00000030
-#define PHY_BB_RADAR_BW_FILTER_RADAR_PULSE_WIDTH_SEL_GET(x) (((x) & 0x00000030) >> 4)
-#define PHY_BB_RADAR_BW_FILTER_RADAR_PULSE_WIDTH_SEL_SET(x) (((x) << 4) & 0x00000030)
-#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_FIRPWR_THRESH_MSB 14
-#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_FIRPWR_THRESH_LSB 8
-#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_FIRPWR_THRESH_MASK 0x00007f00
-#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_FIRPWR_THRESH_GET(x) (((x) & 0x00007f00) >> 8)
-#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_FIRPWR_THRESH_SET(x) (((x) << 8) & 0x00007f00)
-#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_PWR_BIAS_MSB 20
-#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_PWR_BIAS_LSB 15
-#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_PWR_BIAS_MASK 0x001f8000
-#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_PWR_BIAS_GET(x) (((x) & 0x001f8000) >> 15)
-#define PHY_BB_RADAR_BW_FILTER_RADAR_DC_PWR_BIAS_SET(x) (((x) << 15) & 0x001f8000)
-#define PHY_BB_RADAR_BW_FILTER_RADAR_BIN_MAX_BW_MSB 26
-#define PHY_BB_RADAR_BW_FILTER_RADAR_BIN_MAX_BW_LSB 21
-#define PHY_BB_RADAR_BW_FILTER_RADAR_BIN_MAX_BW_MASK 0x07e00000
-#define PHY_BB_RADAR_BW_FILTER_RADAR_BIN_MAX_BW_GET(x) (((x) & 0x07e00000) >> 21)
-#define PHY_BB_RADAR_BW_FILTER_RADAR_BIN_MAX_BW_SET(x) (((x) << 21) & 0x07e00000)
-
-/* macros for BB_dft_tone_ctrl_b0 */
-#define PHY_BB_DFT_TONE_CTRL_B0_ADDRESS 0x0000a7e4
-#define PHY_BB_DFT_TONE_CTRL_B0_OFFSET 0x0000a7e4
-#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_EN_0_MSB 0
-#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_EN_0_LSB 0
-#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_EN_0_MASK 0x00000001
-#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_EN_0_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_EN_0_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_AMP_SEL_0_MSB 3
-#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_AMP_SEL_0_LSB 2
-#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_AMP_SEL_0_MASK 0x0000000c
-#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_AMP_SEL_0_GET(x) (((x) & 0x0000000c) >> 2)
-#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_AMP_SEL_0_SET(x) (((x) << 2) & 0x0000000c)
-#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_FREQ_ANG_0_MSB 12
-#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_FREQ_ANG_0_LSB 4
-#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_FREQ_ANG_0_MASK 0x00001ff0
-#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_FREQ_ANG_0_GET(x) (((x) & 0x00001ff0) >> 4)
-#define PHY_BB_DFT_TONE_CTRL_B0_DFT_TONE_FREQ_ANG_0_SET(x) (((x) << 4) & 0x00001ff0)
-
-/* macros for BB_therm_adc_1 */
-#define PHY_BB_THERM_ADC_1_ADDRESS 0x0000a7e8
-#define PHY_BB_THERM_ADC_1_OFFSET 0x0000a7e8
-#define PHY_BB_THERM_ADC_1_INIT_THERM_SETTING_MSB 7
-#define PHY_BB_THERM_ADC_1_INIT_THERM_SETTING_LSB 0
-#define PHY_BB_THERM_ADC_1_INIT_THERM_SETTING_MASK 0x000000ff
-#define PHY_BB_THERM_ADC_1_INIT_THERM_SETTING_GET(x) (((x) & 0x000000ff) >> 0)
-#define PHY_BB_THERM_ADC_1_INIT_THERM_SETTING_SET(x) (((x) << 0) & 0x000000ff)
-#define PHY_BB_THERM_ADC_1_INIT_VOLT_SETTING_MSB 15
-#define PHY_BB_THERM_ADC_1_INIT_VOLT_SETTING_LSB 8
-#define PHY_BB_THERM_ADC_1_INIT_VOLT_SETTING_MASK 0x0000ff00
-#define PHY_BB_THERM_ADC_1_INIT_VOLT_SETTING_GET(x) (((x) & 0x0000ff00) >> 8)
-#define PHY_BB_THERM_ADC_1_INIT_VOLT_SETTING_SET(x) (((x) << 8) & 0x0000ff00)
-#define PHY_BB_THERM_ADC_1_INIT_ATB_SETTING_MSB 23
-#define PHY_BB_THERM_ADC_1_INIT_ATB_SETTING_LSB 16
-#define PHY_BB_THERM_ADC_1_INIT_ATB_SETTING_MASK 0x00ff0000
-#define PHY_BB_THERM_ADC_1_INIT_ATB_SETTING_GET(x) (((x) & 0x00ff0000) >> 16)
-#define PHY_BB_THERM_ADC_1_INIT_ATB_SETTING_SET(x) (((x) << 16) & 0x00ff0000)
-#define PHY_BB_THERM_ADC_1_SAMPLES_CNT_CODING_MSB 25
-#define PHY_BB_THERM_ADC_1_SAMPLES_CNT_CODING_LSB 24
-#define PHY_BB_THERM_ADC_1_SAMPLES_CNT_CODING_MASK 0x03000000
-#define PHY_BB_THERM_ADC_1_SAMPLES_CNT_CODING_GET(x) (((x) & 0x03000000) >> 24)
-#define PHY_BB_THERM_ADC_1_SAMPLES_CNT_CODING_SET(x) (((x) << 24) & 0x03000000)
-#define PHY_BB_THERM_ADC_1_USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET_MSB 26
-#define PHY_BB_THERM_ADC_1_USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET_LSB 26
-#define PHY_BB_THERM_ADC_1_USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET_MASK 0x04000000
-#define PHY_BB_THERM_ADC_1_USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET_GET(x) (((x) & 0x04000000) >> 26)
-#define PHY_BB_THERM_ADC_1_USE_INIT_THERM_VOLT_ATB_AFTER_WARM_RESET_SET(x) (((x) << 26) & 0x04000000)
-#define PHY_BB_THERM_ADC_1_FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS_MSB 27
-#define PHY_BB_THERM_ADC_1_FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS_LSB 27
-#define PHY_BB_THERM_ADC_1_FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS_MASK 0x08000000
-#define PHY_BB_THERM_ADC_1_FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS_GET(x) (((x) & 0x08000000) >> 27)
-#define PHY_BB_THERM_ADC_1_FORCE_THERM_VOLT_ATB_TO_INIT_SETTINGS_SET(x) (((x) << 27) & 0x08000000)
-
-/* macros for BB_therm_adc_2 */
-#define PHY_BB_THERM_ADC_2_ADDRESS 0x0000a7ec
-#define PHY_BB_THERM_ADC_2_OFFSET 0x0000a7ec
-#define PHY_BB_THERM_ADC_2_MEASURE_THERM_FREQ_MSB 11
-#define PHY_BB_THERM_ADC_2_MEASURE_THERM_FREQ_LSB 0
-#define PHY_BB_THERM_ADC_2_MEASURE_THERM_FREQ_MASK 0x00000fff
-#define PHY_BB_THERM_ADC_2_MEASURE_THERM_FREQ_GET(x) (((x) & 0x00000fff) >> 0)
-#define PHY_BB_THERM_ADC_2_MEASURE_THERM_FREQ_SET(x) (((x) << 0) & 0x00000fff)
-#define PHY_BB_THERM_ADC_2_MEASURE_VOLT_FREQ_MSB 21
-#define PHY_BB_THERM_ADC_2_MEASURE_VOLT_FREQ_LSB 12
-#define PHY_BB_THERM_ADC_2_MEASURE_VOLT_FREQ_MASK 0x003ff000
-#define PHY_BB_THERM_ADC_2_MEASURE_VOLT_FREQ_GET(x) (((x) & 0x003ff000) >> 12)
-#define PHY_BB_THERM_ADC_2_MEASURE_VOLT_FREQ_SET(x) (((x) << 12) & 0x003ff000)
-#define PHY_BB_THERM_ADC_2_MEASURE_ATB_FREQ_MSB 31
-#define PHY_BB_THERM_ADC_2_MEASURE_ATB_FREQ_LSB 22
-#define PHY_BB_THERM_ADC_2_MEASURE_ATB_FREQ_MASK 0xffc00000
-#define PHY_BB_THERM_ADC_2_MEASURE_ATB_FREQ_GET(x) (((x) & 0xffc00000) >> 22)
-#define PHY_BB_THERM_ADC_2_MEASURE_ATB_FREQ_SET(x) (((x) << 22) & 0xffc00000)
-
-/* macros for BB_therm_adc_3 */
-#define PHY_BB_THERM_ADC_3_ADDRESS 0x0000a7f0
-#define PHY_BB_THERM_ADC_3_OFFSET 0x0000a7f0
-#define PHY_BB_THERM_ADC_3_THERM_ADC_OFFSET_MSB 7
-#define PHY_BB_THERM_ADC_3_THERM_ADC_OFFSET_LSB 0
-#define PHY_BB_THERM_ADC_3_THERM_ADC_OFFSET_MASK 0x000000ff
-#define PHY_BB_THERM_ADC_3_THERM_ADC_OFFSET_GET(x) (((x) & 0x000000ff) >> 0)
-#define PHY_BB_THERM_ADC_3_THERM_ADC_OFFSET_SET(x) (((x) << 0) & 0x000000ff)
-#define PHY_BB_THERM_ADC_3_THERM_ADC_SCALED_GAIN_MSB 16
-#define PHY_BB_THERM_ADC_3_THERM_ADC_SCALED_GAIN_LSB 8
-#define PHY_BB_THERM_ADC_3_THERM_ADC_SCALED_GAIN_MASK 0x0001ff00
-#define PHY_BB_THERM_ADC_3_THERM_ADC_SCALED_GAIN_GET(x) (((x) & 0x0001ff00) >> 8)
-#define PHY_BB_THERM_ADC_3_THERM_ADC_SCALED_GAIN_SET(x) (((x) << 8) & 0x0001ff00)
-#define PHY_BB_THERM_ADC_3_ADC_INTERVAL_MSB 29
-#define PHY_BB_THERM_ADC_3_ADC_INTERVAL_LSB 17
-#define PHY_BB_THERM_ADC_3_ADC_INTERVAL_MASK 0x3ffe0000
-#define PHY_BB_THERM_ADC_3_ADC_INTERVAL_GET(x) (((x) & 0x3ffe0000) >> 17)
-#define PHY_BB_THERM_ADC_3_ADC_INTERVAL_SET(x) (((x) << 17) & 0x3ffe0000)
-
-/* macros for BB_therm_adc_4 */
-#define PHY_BB_THERM_ADC_4_ADDRESS 0x0000a7f4
-#define PHY_BB_THERM_ADC_4_OFFSET 0x0000a7f4
-#define PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE_MSB 7
-#define PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE_LSB 0
-#define PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE_MASK 0x000000ff
-#define PHY_BB_THERM_ADC_4_LATEST_THERM_VALUE_GET(x) (((x) & 0x000000ff) >> 0)
-#define PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE_MSB 15
-#define PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE_LSB 8
-#define PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE_MASK 0x0000ff00
-#define PHY_BB_THERM_ADC_4_LATEST_VOLT_VALUE_GET(x) (((x) & 0x0000ff00) >> 8)
-#define PHY_BB_THERM_ADC_4_LATEST_ATB_VALUE_MSB 23
-#define PHY_BB_THERM_ADC_4_LATEST_ATB_VALUE_LSB 16
-#define PHY_BB_THERM_ADC_4_LATEST_ATB_VALUE_MASK 0x00ff0000
-#define PHY_BB_THERM_ADC_4_LATEST_ATB_VALUE_GET(x) (((x) & 0x00ff0000) >> 16)
-
-/* macros for BB_tx_forced_gain */
-#define PHY_BB_TX_FORCED_GAIN_ADDRESS 0x0000a7f8
-#define PHY_BB_TX_FORCED_GAIN_OFFSET 0x0000a7f8
-#define PHY_BB_TX_FORCED_GAIN_FORCE_TX_GAIN_MSB 0
-#define PHY_BB_TX_FORCED_GAIN_FORCE_TX_GAIN_LSB 0
-#define PHY_BB_TX_FORCED_GAIN_FORCE_TX_GAIN_MASK 0x00000001
-#define PHY_BB_TX_FORCED_GAIN_FORCE_TX_GAIN_GET(x) (((x) & 0x00000001) >> 0)
-#define PHY_BB_TX_FORCED_GAIN_FORCE_TX_GAIN_SET(x) (((x) << 0) & 0x00000001)
-#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_MSB 3
-#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_LSB 1
-#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_MASK 0x0000000e
-#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_GET(x) (((x) & 0x0000000e) >> 1)
-#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB1DBGAIN_SET(x) (((x) << 1) & 0x0000000e)
-#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_MSB 5
-#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_LSB 4
-#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_MASK 0x00000030
-#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_GET(x) (((x) & 0x00000030) >> 4)
-#define PHY_BB_TX_FORCED_GAIN_FORCED_TXBB6DBGAIN_SET(x) (((x) << 4) & 0x00000030)
-#define PHY_BB_TX_FORCED_GAIN_FORCED_TXMXRGAIN_MSB 9
-#define PHY_BB_TX_FORCED_GAIN_FORCED_TXMXRGAIN_LSB 6
-#define PHY_BB_TX_FORCED_GAIN_FORCED_TXMXRGAIN_MASK 0x000003c0
-#define PHY_BB_TX_FORCED_GAIN_FORCED_TXMXRGAIN_GET(x) (((x) & 0x000003c0) >> 6)
-#define PHY_BB_TX_FORCED_GAIN_FORCED_TXMXRGAIN_SET(x) (((x) << 6) & 0x000003c0)
-#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNA_MSB 13
-#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNA_LSB 10
-#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNA_MASK 0x00003c00
-#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNA_GET(x) (((x) & 0x00003c00) >> 10)
-#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNA_SET(x) (((x) << 10) & 0x00003c00)
-#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNB_MSB 17
-#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNB_LSB 14
-#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNB_MASK 0x0003c000
-#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNB_GET(x) (((x) & 0x0003c000) >> 14)
-#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNB_SET(x) (((x) << 14) & 0x0003c000)
-#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNC_MSB 21
-#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNC_LSB 18
-#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNC_MASK 0x003c0000
-#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNC_GET(x) (((x) & 0x003c0000) >> 18)
-#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGNC_SET(x) (((x) << 18) & 0x003c0000)
-#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGND_MSB 23
-#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGND_LSB 22
-#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGND_MASK 0x00c00000
-#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGND_GET(x) (((x) & 0x00c00000) >> 22)
-#define PHY_BB_TX_FORCED_GAIN_FORCED_PADRVGND_SET(x) (((x) << 22) & 0x00c00000)
-#define PHY_BB_TX_FORCED_GAIN_FORCED_ENABLE_PAL_MSB 24
-#define PHY_BB_TX_FORCED_GAIN_FORCED_ENABLE_PAL_LSB 24
-#define PHY_BB_TX_FORCED_GAIN_FORCED_ENABLE_PAL_MASK 0x01000000
-#define PHY_BB_TX_FORCED_GAIN_FORCED_ENABLE_PAL_GET(x) (((x) & 0x01000000) >> 24)
-#define PHY_BB_TX_FORCED_GAIN_FORCED_ENABLE_PAL_SET(x) (((x) << 24) & 0x01000000)
-
-/* macros for BB_eco_ctrl */
-#define PHY_BB_ECO_CTRL_ADDRESS 0x0000a7fc
-#define PHY_BB_ECO_CTRL_OFFSET 0x0000a7fc
-#define PHY_BB_ECO_CTRL_ECO_CTRL_MSB 7
-#define PHY_BB_ECO_CTRL_ECO_CTRL_LSB 0
-#define PHY_BB_ECO_CTRL_ECO_CTRL_MASK 0x000000ff
-#define PHY_BB_ECO_CTRL_ECO_CTRL_GET(x) (((x) & 0x000000ff) >> 0)
-#define PHY_BB_ECO_CTRL_ECO_CTRL_SET(x) (((x) << 0) & 0x000000ff)
-
-/* macros for BB_gain_force_max_gains_b1 */
-#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_ADDRESS 0x0000a848
-#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_OFFSET 0x0000a848
-#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN1_HYST_MARGIN_1_MSB 13
-#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN1_HYST_MARGIN_1_LSB 7
-#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN1_HYST_MARGIN_1_MASK 0x00003f80
-#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN1_HYST_MARGIN_1_GET(x) (((x) & 0x00003f80) >> 7)
-#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN1_HYST_MARGIN_1_SET(x) (((x) << 7) & 0x00003f80)
-#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN2_HYST_MARGIN_1_MSB 20
-#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN2_HYST_MARGIN_1_LSB 14
-#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN2_HYST_MARGIN_1_MASK 0x001fc000
-#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN2_HYST_MARGIN_1_GET(x) (((x) & 0x001fc000) >> 14)
-#define PHY_BB_GAIN_FORCE_MAX_GAINS_B1_XATTEN2_HYST_MARGIN_1_SET(x) (((x) << 14) & 0x001fc000)
-
-/* macros for BB_gains_min_offsets_b1 */
-#define PHY_BB_GAINS_MIN_OFFSETS_B1_ADDRESS 0x0000a84c
-#define PHY_BB_GAINS_MIN_OFFSETS_B1_OFFSET 0x0000a84c
-#define PHY_BB_GAINS_MIN_OFFSETS_B1_RF_GAIN_F_1_MSB 24
-#define PHY_BB_GAINS_MIN_OFFSETS_B1_RF_GAIN_F_1_LSB 17
-#define PHY_BB_GAINS_MIN_OFFSETS_B1_RF_GAIN_F_1_MASK 0x01fe0000
-#define PHY_BB_GAINS_MIN_OFFSETS_B1_RF_GAIN_F_1_GET(x) (((x) & 0x01fe0000) >> 17)
-#define PHY_BB_GAINS_MIN_OFFSETS_B1_RF_GAIN_F_1_SET(x) (((x) << 17) & 0x01fe0000)
-#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN1_SW_F_1_MSB 25
-#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN1_SW_F_1_LSB 25
-#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN1_SW_F_1_MASK 0x02000000
-#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN1_SW_F_1_GET(x) (((x) & 0x02000000) >> 25)
-#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN1_SW_F_1_SET(x) (((x) << 25) & 0x02000000)
-#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN2_SW_F_1_MSB 26
-#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN2_SW_F_1_LSB 26
-#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN2_SW_F_1_MASK 0x04000000
-#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN2_SW_F_1_GET(x) (((x) & 0x04000000) >> 26)
-#define PHY_BB_GAINS_MIN_OFFSETS_B1_XATTEN2_SW_F_1_SET(x) (((x) << 26) & 0x04000000)
-
-/* macros for BB_rx_ocgain2 */
-#define PHY_BB_RX_OCGAIN2_ADDRESS 0x0000aa00
-#define PHY_BB_RX_OCGAIN2_OFFSET 0x0000aa00
-#define PHY_BB_RX_OCGAIN2_GAIN_ENTRY2_MSB 31
-#define PHY_BB_RX_OCGAIN2_GAIN_ENTRY2_LSB 0
-#define PHY_BB_RX_OCGAIN2_GAIN_ENTRY2_MASK 0xffffffff
-#define PHY_BB_RX_OCGAIN2_GAIN_ENTRY2_SET(x) (((x) << 0) & 0xffffffff)
-
-/* macros for BB_ext_atten_switch_ctl_b1 */
-#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_ADDRESS 0x0000b20c
-#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_OFFSET 0x0000b20c
-#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_DB_1_MSB 5
-#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_DB_1_LSB 0
-#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_DB_1_MASK 0x0000003f
-#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_DB_1_GET(x) (((x) & 0x0000003f) >> 0)
-#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_DB_1_SET(x) (((x) << 0) & 0x0000003f)
-#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_DB_1_MSB 11
-#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_DB_1_LSB 6
-#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_DB_1_MASK 0x00000fc0
-#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_DB_1_GET(x) (((x) & 0x00000fc0) >> 6)
-#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_DB_1_SET(x) (((x) << 6) & 0x00000fc0)
-#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_MARGIN_1_MSB 16
-#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_MARGIN_1_LSB 12
-#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_MARGIN_1_MASK 0x0001f000
-#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_MARGIN_1_GET(x) (((x) & 0x0001f000) >> 12)
-#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN1_MARGIN_1_SET(x) (((x) << 12) & 0x0001f000)
-#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_MARGIN_1_MSB 21
-#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_MARGIN_1_LSB 17
-#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_MARGIN_1_MASK 0x003e0000
-#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_MARGIN_1_GET(x) (((x) & 0x003e0000) >> 17)
-#define PHY_BB_EXT_ATTEN_SWITCH_CTL_B1_XATTEN2_MARGIN_1_SET(x) (((x) << 17) & 0x003e0000)
-
-
-#ifndef __ASSEMBLER__
-
-typedef struct bb_lc_reg_reg_s {
- volatile char pad__0[0x9800]; /* 0x0 - 0x9800 */
- volatile unsigned int BB_test_controls; /* 0x9800 - 0x9804 */
- volatile unsigned int BB_gen_controls; /* 0x9804 - 0x9808 */
- volatile unsigned int BB_test_controls_status; /* 0x9808 - 0x980c */
- volatile unsigned int BB_timing_controls_1; /* 0x980c - 0x9810 */
- volatile unsigned int BB_timing_controls_2; /* 0x9810 - 0x9814 */
- volatile unsigned int BB_timing_controls_3; /* 0x9814 - 0x9818 */
- volatile unsigned int BB_D2_chip_id; /* 0x9818 - 0x981c */
- volatile unsigned int BB_active; /* 0x981c - 0x9820 */
- volatile unsigned int BB_tx_timing_1; /* 0x9820 - 0x9824 */
- volatile unsigned int BB_tx_timing_2; /* 0x9824 - 0x9828 */
- volatile unsigned int BB_tx_timing_3; /* 0x9828 - 0x982c */
- volatile unsigned int BB_addac_parallel_control; /* 0x982c - 0x9830 */
- volatile char pad__1[0x4]; /* 0x9830 - 0x9834 */
- volatile unsigned int BB_xpa_timing_control; /* 0x9834 - 0x9838 */
- volatile unsigned int BB_misc_pa_control; /* 0x9838 - 0x983c */
- volatile unsigned int BB_tstdac_constant; /* 0x983c - 0x9840 */
- volatile unsigned int BB_find_signal_low; /* 0x9840 - 0x9844 */
- volatile unsigned int BB_settling_time; /* 0x9844 - 0x9848 */
- volatile unsigned int BB_gain_force_max_gains_b0; /* 0x9848 - 0x984c */
- volatile unsigned int BB_gains_min_offsets_b0; /* 0x984c - 0x9850 */
- volatile unsigned int BB_desired_sigsize; /* 0x9850 - 0x9854 */
- volatile unsigned int BB_timing_control_3a; /* 0x9854 - 0x9858 */
- volatile unsigned int BB_find_signal; /* 0x9858 - 0x985c */
- volatile unsigned int BB_agc; /* 0x985c - 0x9860 */
- volatile unsigned int BB_agc_control; /* 0x9860 - 0x9864 */
- volatile unsigned int BB_cca_b0; /* 0x9864 - 0x9868 */
- volatile unsigned int BB_sfcorr; /* 0x9868 - 0x986c */
- volatile unsigned int BB_self_corr_low; /* 0x986c - 0x9870 */
- volatile char pad__2[0x4]; /* 0x9870 - 0x9874 */
- volatile unsigned int BB_synth_control; /* 0x9874 - 0x9878 */
- volatile unsigned int BB_addac_clk_select; /* 0x9878 - 0x987c */
- volatile unsigned int BB_pll_cntl; /* 0x987c - 0x9880 */
- volatile char pad__3[0x80]; /* 0x9880 - 0x9900 */
- volatile unsigned int BB_vit_spur_mask_A; /* 0x9900 - 0x9904 */
- volatile unsigned int BB_vit_spur_mask_B; /* 0x9904 - 0x9908 */
- volatile unsigned int BB_pilot_spur_mask; /* 0x9908 - 0x990c */
- volatile unsigned int BB_chan_spur_mask; /* 0x990c - 0x9910 */
- volatile unsigned int BB_spectral_scan; /* 0x9910 - 0x9914 */
- volatile unsigned int BB_analog_power_on_time; /* 0x9914 - 0x9918 */
- volatile unsigned int BB_search_start_delay; /* 0x9918 - 0x991c */
- volatile unsigned int BB_max_rx_length; /* 0x991c - 0x9920 */
- volatile unsigned int BB_timing_control_4; /* 0x9920 - 0x9924 */
- volatile unsigned int BB_timing_control_5; /* 0x9924 - 0x9928 */
- volatile unsigned int BB_phyonly_warm_reset; /* 0x9928 - 0x992c */
- volatile unsigned int BB_phyonly_control; /* 0x992c - 0x9930 */
- volatile char pad__4[0x4]; /* 0x9930 - 0x9934 */
- volatile unsigned int BB_powertx_rate1; /* 0x9934 - 0x9938 */
- volatile unsigned int BB_powertx_rate2; /* 0x9938 - 0x993c */
- volatile unsigned int BB_powertx_max; /* 0x993c - 0x9940 */
- volatile unsigned int BB_extension_radar; /* 0x9940 - 0x9944 */
- volatile unsigned int BB_frame_control; /* 0x9944 - 0x9948 */
- volatile unsigned int BB_timing_control_6; /* 0x9948 - 0x994c */
- volatile unsigned int BB_spur_mask_controls; /* 0x994c - 0x9950 */
- volatile unsigned int BB_rx_iq_corr_b0; /* 0x9950 - 0x9954 */
- volatile unsigned int BB_radar_detection; /* 0x9954 - 0x9958 */
- volatile unsigned int BB_radar_detection_2; /* 0x9958 - 0x995c */
- volatile unsigned int BB_tx_phase_ramp_b0; /* 0x995c - 0x9960 */
- volatile unsigned int BB_switch_table_chn_b0; /* 0x9960 - 0x9964 */
- volatile unsigned int BB_switch_table_com1; /* 0x9964 - 0x9968 */
- volatile unsigned int BB_cca_ctrl_2_b0; /* 0x9968 - 0x996c */
- volatile unsigned int BB_switch_table_com2; /* 0x996c - 0x9970 */
- volatile unsigned int BB_restart; /* 0x9970 - 0x9974 */
- volatile char pad__5[0x4]; /* 0x9974 - 0x9978 */
- volatile unsigned int BB_scrambler_seed; /* 0x9978 - 0x997c */
- volatile unsigned int BB_rfbus_request; /* 0x997c - 0x9980 */
- volatile char pad__6[0x20]; /* 0x9980 - 0x99a0 */
- volatile unsigned int BB_timing_control_11; /* 0x99a0 - 0x99a4 */
- volatile unsigned int BB_multichain_enable; /* 0x99a4 - 0x99a8 */
- volatile unsigned int BB_multichain_control; /* 0x99a8 - 0x99ac */
- volatile unsigned int BB_multichain_gain_ctrl; /* 0x99ac - 0x99b0 */
- volatile char pad__7[0x4]; /* 0x99b0 - 0x99b4 */
- volatile unsigned int BB_adc_gain_dc_corr_b0; /* 0x99b4 - 0x99b8 */
- volatile unsigned int BB_ext_chan_pwr_thr_1; /* 0x99b8 - 0x99bc */
- volatile unsigned int BB_ext_chan_pwr_thr_2_b0; /* 0x99bc - 0x99c0 */
- volatile unsigned int BB_ext_chan_scorr_thr; /* 0x99c0 - 0x99c4 */
- volatile unsigned int BB_ext_chan_detect_win; /* 0x99c4 - 0x99c8 */
- volatile unsigned int BB_pwr_thr_20_40_det; /* 0x99c8 - 0x99cc */
- volatile char pad__8[0x4]; /* 0x99cc - 0x99d0 */
- volatile unsigned int BB_short_gi_delta_slope; /* 0x99d0 - 0x99d4 */
- volatile char pad__9[0x8]; /* 0x99d4 - 0x99dc */
- volatile unsigned int BB_chaninfo_ctrl; /* 0x99dc - 0x99e0 */
- volatile unsigned int BB_heavy_clip_ctrl; /* 0x99e0 - 0x99e4 */
- volatile unsigned int BB_heavy_clip_20; /* 0x99e4 - 0x99e8 */
- volatile unsigned int BB_heavy_clip_40; /* 0x99e8 - 0x99ec */
- volatile unsigned int BB_rifs_srch; /* 0x99ec - 0x99f0 */
- volatile unsigned int BB_iq_adc_cal_mode; /* 0x99f0 - 0x99f4 */
- volatile char pad__10[0x8]; /* 0x99f4 - 0x99fc */
- volatile unsigned int BB_per_chain_csd; /* 0x99fc - 0x9a00 */
- volatile unsigned int BB_rx_ocgain[128]; /* 0x9a00 - 0x9c00 */
- volatile unsigned int BB_tx_crc; /* 0x9c00 - 0x9c04 */
- volatile char pad__11[0xc]; /* 0x9c04 - 0x9c10 */
- volatile unsigned int BB_iq_adc_meas_0_b0; /* 0x9c10 - 0x9c14 */
- volatile unsigned int BB_iq_adc_meas_1_b0; /* 0x9c14 - 0x9c18 */
- volatile unsigned int BB_iq_adc_meas_2_b0; /* 0x9c18 - 0x9c1c */
- volatile unsigned int BB_iq_adc_meas_3_b0; /* 0x9c1c - 0x9c20 */
- volatile unsigned int BB_rfbus_grant; /* 0x9c20 - 0x9c24 */
- volatile unsigned int BB_tstadc; /* 0x9c24 - 0x9c28 */
- volatile unsigned int BB_tstdac; /* 0x9c28 - 0x9c2c */
- volatile char pad__12[0x4]; /* 0x9c2c - 0x9c30 */
- volatile unsigned int BB_illegal_tx_rate; /* 0x9c30 - 0x9c34 */
- volatile unsigned int BB_spur_report_b0; /* 0x9c34 - 0x9c38 */
- volatile unsigned int BB_channel_status; /* 0x9c38 - 0x9c3c */
- volatile unsigned int BB_rssi_b0; /* 0x9c3c - 0x9c40 */
- volatile unsigned int BB_spur_est_cck_report_b0; /* 0x9c40 - 0x9c44 */
- volatile char pad__13[0x68]; /* 0x9c44 - 0x9cac */
- volatile unsigned int BB_chan_info_noise_pwr; /* 0x9cac - 0x9cb0 */
- volatile unsigned int BB_chan_info_gain_diff; /* 0x9cb0 - 0x9cb4 */
- volatile unsigned int BB_chan_info_fine_timing; /* 0x9cb4 - 0x9cb8 */
- volatile unsigned int BB_chan_info_gain_b0; /* 0x9cb8 - 0x9cbc */
- volatile unsigned int BB_chan_info_chan_tab_b0[60]; /* 0x9cbc - 0x9dac */
- volatile char pad__14[0x38]; /* 0x9dac - 0x9de4 */
- volatile unsigned int BB_paprd_am2am_mask; /* 0x9de4 - 0x9de8 */
- volatile unsigned int BB_paprd_am2pm_mask; /* 0x9de8 - 0x9dec */
- volatile unsigned int BB_paprd_ht40_mask; /* 0x9dec - 0x9df0 */
- volatile unsigned int BB_paprd_ctrl0; /* 0x9df0 - 0x9df4 */
- volatile unsigned int BB_paprd_ctrl1; /* 0x9df4 - 0x9df8 */
- volatile unsigned int BB_pa_gain123; /* 0x9df8 - 0x9dfc */
- volatile unsigned int BB_pa_gain45; /* 0x9dfc - 0x9e00 */
- volatile unsigned int BB_paprd_pre_post_scale_0; /* 0x9e00 - 0x9e04 */
- volatile unsigned int BB_paprd_pre_post_scale_1; /* 0x9e04 - 0x9e08 */
- volatile unsigned int BB_paprd_pre_post_scale_2; /* 0x9e08 - 0x9e0c */
- volatile unsigned int BB_paprd_pre_post_scale_3; /* 0x9e0c - 0x9e10 */
- volatile unsigned int BB_paprd_pre_post_scale_4; /* 0x9e10 - 0x9e14 */
- volatile unsigned int BB_paprd_pre_post_scale_5; /* 0x9e14 - 0x9e18 */
- volatile unsigned int BB_paprd_pre_post_scale_6; /* 0x9e18 - 0x9e1c */
- volatile unsigned int BB_paprd_pre_post_scale_7; /* 0x9e1c - 0x9e20 */
- volatile unsigned int BB_paprd_mem_tab[120]; /* 0x9e20 - 0xa000 */
- volatile unsigned int BB_peak_det_ctrl_1; /* 0xa000 - 0xa004 */
- volatile unsigned int BB_peak_det_ctrl_2; /* 0xa004 - 0xa008 */
- volatile unsigned int BB_rx_gain_bounds_1; /* 0xa008 - 0xa00c */
- volatile unsigned int BB_rx_gain_bounds_2; /* 0xa00c - 0xa010 */
- volatile unsigned int BB_peak_det_cal_ctrl; /* 0xa010 - 0xa014 */
- volatile unsigned int BB_agc_dig_dc_ctrl; /* 0xa014 - 0xa018 */
- volatile unsigned int BB_agc_dig_dc_status_i_b0; /* 0xa018 - 0xa01c */
- volatile unsigned int BB_agc_dig_dc_status_q_b0; /* 0xa01c - 0xa020 */
- volatile char pad__15[0x1d4]; /* 0xa020 - 0xa1f4 */
- volatile unsigned int BB_bbb_txfir_0; /* 0xa1f4 - 0xa1f8 */
- volatile unsigned int BB_bbb_txfir_1; /* 0xa1f8 - 0xa1fc */
- volatile unsigned int BB_bbb_txfir_2; /* 0xa1fc - 0xa200 */
- volatile unsigned int BB_modes_select; /* 0xa200 - 0xa204 */
- volatile unsigned int BB_bbb_tx_ctrl; /* 0xa204 - 0xa208 */
- volatile unsigned int BB_bbb_sig_detect; /* 0xa208 - 0xa20c */
- volatile unsigned int BB_ext_atten_switch_ctl_b0; /* 0xa20c - 0xa210 */
- volatile unsigned int BB_bbb_rx_ctrl_1; /* 0xa210 - 0xa214 */
- volatile unsigned int BB_bbb_rx_ctrl_2; /* 0xa214 - 0xa218 */
- volatile unsigned int BB_bbb_rx_ctrl_3; /* 0xa218 - 0xa21c */
- volatile unsigned int BB_bbb_rx_ctrl_4; /* 0xa21c - 0xa220 */
- volatile unsigned int BB_bbb_rx_ctrl_5; /* 0xa220 - 0xa224 */
- volatile unsigned int BB_bbb_rx_ctrl_6; /* 0xa224 - 0xa228 */
- volatile unsigned int BB_bbb_dagc_ctrl; /* 0xa228 - 0xa22c */
- volatile unsigned int BB_force_clken_cck; /* 0xa22c - 0xa230 */
- volatile unsigned int BB_rx_clear_delay; /* 0xa230 - 0xa234 */
- volatile unsigned int BB_powertx_rate3; /* 0xa234 - 0xa238 */
- volatile unsigned int BB_powertx_rate4; /* 0xa238 - 0xa23c */
- volatile char pad__16[0x4]; /* 0xa23c - 0xa240 */
- volatile unsigned int BB_cck_spur_mit; /* 0xa240 - 0xa244 */
- volatile unsigned int BB_panic_watchdog_status; /* 0xa244 - 0xa248 */
- volatile unsigned int BB_panic_watchdog_ctrl_1; /* 0xa248 - 0xa24c */
- volatile unsigned int BB_panic_watchdog_ctrl_2; /* 0xa24c - 0xa250 */
- volatile unsigned int BB_iqcorr_ctrl_cck; /* 0xa250 - 0xa254 */
- volatile unsigned int BB_bluetooth_cntl; /* 0xa254 - 0xa258 */
- volatile unsigned int BB_tpc_1; /* 0xa258 - 0xa25c */
- volatile unsigned int BB_tpc_2; /* 0xa25c - 0xa260 */
- volatile unsigned int BB_tpc_3; /* 0xa260 - 0xa264 */
- volatile unsigned int BB_tpc_4_b0; /* 0xa264 - 0xa268 */
- volatile unsigned int BB_analog_swap; /* 0xa268 - 0xa26c */
- volatile unsigned int BB_tpc_5_b0; /* 0xa26c - 0xa270 */
- volatile unsigned int BB_tpc_6_b0; /* 0xa270 - 0xa274 */
- volatile unsigned int BB_tpc_7; /* 0xa274 - 0xa278 */
- volatile unsigned int BB_tpc_8; /* 0xa278 - 0xa27c */
- volatile unsigned int BB_tpc_9; /* 0xa27c - 0xa280 */
- volatile unsigned int BB_pdadc_tab_b0[32]; /* 0xa280 - 0xa300 */
- volatile unsigned int BB_cl_tab_b0[16]; /* 0xa300 - 0xa340 */
- volatile unsigned int BB_cl_map_0_b0; /* 0xa340 - 0xa344 */
- volatile unsigned int BB_cl_map_1_b0; /* 0xa344 - 0xa348 */
- volatile unsigned int BB_cl_map_2_b0; /* 0xa348 - 0xa34c */
- volatile unsigned int BB_cl_map_3_b0; /* 0xa34c - 0xa350 */
- volatile char pad__17[0x8]; /* 0xa350 - 0xa358 */
- volatile unsigned int BB_cl_cal_ctrl; /* 0xa358 - 0xa35c */
- volatile unsigned int BB_cl_map_pal_0_b0; /* 0xa35c - 0xa360 */
- volatile unsigned int BB_cl_map_pal_1_b0; /* 0xa360 - 0xa364 */
- volatile unsigned int BB_cl_map_pal_2_b0; /* 0xa364 - 0xa368 */
- volatile unsigned int BB_cl_map_pal_3_b0; /* 0xa368 - 0xa36c */
- volatile char pad__18[0x1c]; /* 0xa36c - 0xa388 */
- volatile unsigned int BB_rifs; /* 0xa388 - 0xa38c */
- volatile unsigned int BB_powertx_rate5; /* 0xa38c - 0xa390 */
- volatile unsigned int BB_powertx_rate6; /* 0xa390 - 0xa394 */
- volatile unsigned int BB_tpc_10; /* 0xa394 - 0xa398 */
- volatile unsigned int BB_tpc_11_b0; /* 0xa398 - 0xa39c */
- volatile unsigned int BB_cal_chain_mask; /* 0xa39c - 0xa3a0 */
- volatile char pad__19[0x1c]; /* 0xa3a0 - 0xa3bc */
- volatile unsigned int BB_powertx_sub; /* 0xa3bc - 0xa3c0 */
- volatile unsigned int BB_powertx_rate7; /* 0xa3c0 - 0xa3c4 */
- volatile unsigned int BB_powertx_rate8; /* 0xa3c4 - 0xa3c8 */
- volatile unsigned int BB_powertx_rate9; /* 0xa3c8 - 0xa3cc */
- volatile unsigned int BB_powertx_rate10; /* 0xa3cc - 0xa3d0 */
- volatile unsigned int BB_powertx_rate11; /* 0xa3d0 - 0xa3d4 */
- volatile unsigned int BB_powertx_rate12; /* 0xa3d4 - 0xa3d8 */
- volatile unsigned int BB_force_analog; /* 0xa3d8 - 0xa3dc */
- volatile unsigned int BB_tpc_12; /* 0xa3dc - 0xa3e0 */
- volatile unsigned int BB_tpc_13; /* 0xa3e0 - 0xa3e4 */
- volatile unsigned int BB_tpc_14; /* 0xa3e4 - 0xa3e8 */
- volatile unsigned int BB_tpc_15; /* 0xa3e8 - 0xa3ec */
- volatile unsigned int BB_tpc_16; /* 0xa3ec - 0xa3f0 */
- volatile unsigned int BB_tpc_17; /* 0xa3f0 - 0xa3f4 */
- volatile unsigned int BB_tpc_18; /* 0xa3f4 - 0xa3f8 */
- volatile unsigned int BB_tpc_19; /* 0xa3f8 - 0xa3fc */
- volatile unsigned int BB_tpc_20; /* 0xa3fc - 0xa400 */
- volatile unsigned int BB_tx_gain_tab_1; /* 0xa400 - 0xa404 */
- volatile unsigned int BB_tx_gain_tab_2; /* 0xa404 - 0xa408 */
- volatile unsigned int BB_tx_gain_tab_3; /* 0xa408 - 0xa40c */
- volatile unsigned int BB_tx_gain_tab_4; /* 0xa40c - 0xa410 */
- volatile unsigned int BB_tx_gain_tab_5; /* 0xa410 - 0xa414 */
- volatile unsigned int BB_tx_gain_tab_6; /* 0xa414 - 0xa418 */
- volatile unsigned int BB_tx_gain_tab_7; /* 0xa418 - 0xa41c */
- volatile unsigned int BB_tx_gain_tab_8; /* 0xa41c - 0xa420 */
- volatile unsigned int BB_tx_gain_tab_9; /* 0xa420 - 0xa424 */
- volatile unsigned int BB_tx_gain_tab_10; /* 0xa424 - 0xa428 */
- volatile unsigned int BB_tx_gain_tab_11; /* 0xa428 - 0xa42c */
- volatile unsigned int BB_tx_gain_tab_12; /* 0xa42c - 0xa430 */
- volatile unsigned int BB_tx_gain_tab_13; /* 0xa430 - 0xa434 */
- volatile unsigned int BB_tx_gain_tab_14; /* 0xa434 - 0xa438 */
- volatile unsigned int BB_tx_gain_tab_15; /* 0xa438 - 0xa43c */
- volatile unsigned int BB_tx_gain_tab_16; /* 0xa43c - 0xa440 */
- volatile unsigned int BB_tx_gain_tab_17; /* 0xa440 - 0xa444 */
- volatile unsigned int BB_tx_gain_tab_18; /* 0xa444 - 0xa448 */
- volatile unsigned int BB_tx_gain_tab_19; /* 0xa448 - 0xa44c */
- volatile unsigned int BB_tx_gain_tab_20; /* 0xa44c - 0xa450 */
- volatile unsigned int BB_tx_gain_tab_21; /* 0xa450 - 0xa454 */
- volatile unsigned int BB_tx_gain_tab_22; /* 0xa454 - 0xa458 */
- volatile unsigned int BB_tx_gain_tab_23; /* 0xa458 - 0xa45c */
- volatile unsigned int BB_tx_gain_tab_24; /* 0xa45c - 0xa460 */
- volatile unsigned int BB_tx_gain_tab_25; /* 0xa460 - 0xa464 */
- volatile unsigned int BB_tx_gain_tab_26; /* 0xa464 - 0xa468 */
- volatile unsigned int BB_tx_gain_tab_27; /* 0xa468 - 0xa46c */
- volatile unsigned int BB_tx_gain_tab_28; /* 0xa46c - 0xa470 */
- volatile unsigned int BB_tx_gain_tab_29; /* 0xa470 - 0xa474 */
- volatile unsigned int BB_tx_gain_tab_30; /* 0xa474 - 0xa478 */
- volatile unsigned int BB_tx_gain_tab_31; /* 0xa478 - 0xa47c */
- volatile unsigned int BB_tx_gain_tab_32; /* 0xa47c - 0xa480 */
- volatile unsigned int BB_tx_gain_tab_pal_1; /* 0xa480 - 0xa484 */
- volatile unsigned int BB_tx_gain_tab_pal_2; /* 0xa484 - 0xa488 */
- volatile unsigned int BB_tx_gain_tab_pal_3; /* 0xa488 - 0xa48c */
- volatile unsigned int BB_tx_gain_tab_pal_4; /* 0xa48c - 0xa490 */
- volatile unsigned int BB_tx_gain_tab_pal_5; /* 0xa490 - 0xa494 */
- volatile unsigned int BB_tx_gain_tab_pal_6; /* 0xa494 - 0xa498 */
- volatile unsigned int BB_tx_gain_tab_pal_7; /* 0xa498 - 0xa49c */
- volatile unsigned int BB_tx_gain_tab_pal_8; /* 0xa49c - 0xa4a0 */
- volatile unsigned int BB_tx_gain_tab_pal_9; /* 0xa4a0 - 0xa4a4 */
- volatile unsigned int BB_tx_gain_tab_pal_10; /* 0xa4a4 - 0xa4a8 */
- volatile unsigned int BB_tx_gain_tab_pal_11; /* 0xa4a8 - 0xa4ac */
- volatile unsigned int BB_tx_gain_tab_pal_12; /* 0xa4ac - 0xa4b0 */
- volatile unsigned int BB_tx_gain_tab_pal_13; /* 0xa4b0 - 0xa4b4 */
- volatile unsigned int BB_tx_gain_tab_pal_14; /* 0xa4b4 - 0xa4b8 */
- volatile unsigned int BB_tx_gain_tab_pal_15; /* 0xa4b8 - 0xa4bc */
- volatile unsigned int BB_tx_gain_tab_pal_16; /* 0xa4bc - 0xa4c0 */
- volatile unsigned int BB_tx_gain_tab_pal_17; /* 0xa4c0 - 0xa4c4 */
- volatile unsigned int BB_tx_gain_tab_pal_18; /* 0xa4c4 - 0xa4c8 */
- volatile unsigned int BB_tx_gain_tab_pal_19; /* 0xa4c8 - 0xa4cc */
- volatile unsigned int BB_tx_gain_tab_pal_20; /* 0xa4cc - 0xa4d0 */
- volatile unsigned int BB_tx_gain_tab_pal_21; /* 0xa4d0 - 0xa4d4 */
- volatile unsigned int BB_tx_gain_tab_pal_22; /* 0xa4d4 - 0xa4d8 */
- volatile unsigned int BB_tx_gain_tab_pal_23; /* 0xa4d8 - 0xa4dc */
- volatile unsigned int BB_tx_gain_tab_pal_24; /* 0xa4dc - 0xa4e0 */
- volatile unsigned int BB_tx_gain_tab_pal_25; /* 0xa4e0 - 0xa4e4 */
- volatile unsigned int BB_tx_gain_tab_pal_26; /* 0xa4e4 - 0xa4e8 */
- volatile unsigned int BB_tx_gain_tab_pal_27; /* 0xa4e8 - 0xa4ec */
- volatile unsigned int BB_tx_gain_tab_pal_28; /* 0xa4ec - 0xa4f0 */
- volatile unsigned int BB_tx_gain_tab_pal_29; /* 0xa4f0 - 0xa4f4 */
- volatile unsigned int BB_tx_gain_tab_pal_30; /* 0xa4f4 - 0xa4f8 */
- volatile unsigned int BB_tx_gain_tab_pal_31; /* 0xa4f8 - 0xa4fc */
- volatile unsigned int BB_tx_gain_tab_pal_32; /* 0xa4fc - 0xa500 */
- volatile char pad__20[0x18]; /* 0xa500 - 0xa518 */
- volatile unsigned int BB_caltx_gain_set_0; /* 0xa518 - 0xa51c */
- volatile unsigned int BB_caltx_gain_set_2; /* 0xa51c - 0xa520 */
- volatile unsigned int BB_caltx_gain_set_4; /* 0xa520 - 0xa524 */
- volatile unsigned int BB_caltx_gain_set_6; /* 0xa524 - 0xa528 */
- volatile unsigned int BB_caltx_gain_set_8; /* 0xa528 - 0xa52c */
- volatile unsigned int BB_caltx_gain_set_10; /* 0xa52c - 0xa530 */
- volatile unsigned int BB_caltx_gain_set_12; /* 0xa530 - 0xa534 */
- volatile unsigned int BB_caltx_gain_set_14; /* 0xa534 - 0xa538 */
- volatile unsigned int BB_caltx_gain_set_16; /* 0xa538 - 0xa53c */
- volatile unsigned int BB_caltx_gain_set_18; /* 0xa53c - 0xa540 */
- volatile unsigned int BB_caltx_gain_set_20; /* 0xa540 - 0xa544 */
- volatile unsigned int BB_caltx_gain_set_22; /* 0xa544 - 0xa548 */
- volatile unsigned int BB_caltx_gain_set_24; /* 0xa548 - 0xa54c */
- volatile unsigned int BB_caltx_gain_set_26; /* 0xa54c - 0xa550 */
- volatile unsigned int BB_caltx_gain_set_28; /* 0xa550 - 0xa554 */
- volatile unsigned int BB_caltx_gain_set_30; /* 0xa554 - 0xa558 */
- volatile unsigned int BB_txiqcal_meas_b0[96]; /* 0xa558 - 0xa6d8 */
- volatile unsigned int BB_txiqcal_start; /* 0xa6d8 - 0xa6dc */
- volatile unsigned int BB_txiqcal_control_0; /* 0xa6dc - 0xa6e0 */
- volatile unsigned int BB_txiqcal_control_1; /* 0xa6e0 - 0xa6e4 */
- volatile unsigned int BB_txiqcal_control_2; /* 0xa6e4 - 0xa6e8 */
- volatile unsigned int BB_txiqcal_control_3; /* 0xa6e8 - 0xa6ec */
- volatile unsigned int BB_txiq_corr_coeff_01_b0; /* 0xa6ec - 0xa6f0 */
- volatile unsigned int BB_txiq_corr_coeff_23_b0; /* 0xa6f0 - 0xa6f4 */
- volatile unsigned int BB_txiq_corr_coeff_45_b0; /* 0xa6f4 - 0xa6f8 */
- volatile unsigned int BB_txiq_corr_coeff_67_b0; /* 0xa6f8 - 0xa6fc */
- volatile unsigned int BB_txiq_corr_coeff_89_b0; /* 0xa6fc - 0xa700 */
- volatile unsigned int BB_txiq_corr_coeff_ab_b0; /* 0xa700 - 0xa704 */
- volatile unsigned int BB_txiq_corr_coeff_cd_b0; /* 0xa704 - 0xa708 */
- volatile unsigned int BB_txiq_corr_coeff_ef_b0; /* 0xa708 - 0xa70c */
- volatile unsigned int BB_cal_rxbb_gain_tbl_0; /* 0xa70c - 0xa710 */
- volatile unsigned int BB_cal_rxbb_gain_tbl_4; /* 0xa710 - 0xa714 */
- volatile unsigned int BB_cal_rxbb_gain_tbl_8; /* 0xa714 - 0xa718 */
- volatile unsigned int BB_cal_rxbb_gain_tbl_12; /* 0xa718 - 0xa71c */
- volatile unsigned int BB_cal_rxbb_gain_tbl_16; /* 0xa71c - 0xa720 */
- volatile unsigned int BB_cal_rxbb_gain_tbl_20; /* 0xa720 - 0xa724 */
- volatile unsigned int BB_cal_rxbb_gain_tbl_24; /* 0xa724 - 0xa728 */
- volatile unsigned int BB_txiqcal_status_b0; /* 0xa728 - 0xa72c */
- volatile unsigned int BB_paprd_trainer_cntl1; /* 0xa72c - 0xa730 */
- volatile unsigned int BB_paprd_trainer_cntl2; /* 0xa730 - 0xa734 */
- volatile unsigned int BB_paprd_trainer_cntl3; /* 0xa734 - 0xa738 */
- volatile unsigned int BB_paprd_trainer_cntl4; /* 0xa738 - 0xa73c */
- volatile unsigned int BB_paprd_trainer_stat1; /* 0xa73c - 0xa740 */
- volatile unsigned int BB_paprd_trainer_stat2; /* 0xa740 - 0xa744 */
- volatile unsigned int BB_paprd_trainer_stat3; /* 0xa744 - 0xa748 */
- volatile char pad__21[0x90]; /* 0xa748 - 0xa7d8 */
- volatile unsigned int BB_fcal_1; /* 0xa7d8 - 0xa7dc */
- volatile unsigned int BB_fcal_2_b0; /* 0xa7dc - 0xa7e0 */
- volatile unsigned int BB_radar_bw_filter; /* 0xa7e0 - 0xa7e4 */
- volatile unsigned int BB_dft_tone_ctrl_b0; /* 0xa7e4 - 0xa7e8 */
- volatile unsigned int BB_therm_adc_1; /* 0xa7e8 - 0xa7ec */
- volatile unsigned int BB_therm_adc_2; /* 0xa7ec - 0xa7f0 */
- volatile unsigned int BB_therm_adc_3; /* 0xa7f0 - 0xa7f4 */
- volatile unsigned int BB_therm_adc_4; /* 0xa7f4 - 0xa7f8 */
- volatile unsigned int BB_tx_forced_gain; /* 0xa7f8 - 0xa7fc */
- volatile unsigned int BB_eco_ctrl; /* 0xa7fc - 0xa800 */
- volatile char pad__22[0x48]; /* 0xa800 - 0xa848 */
- volatile unsigned int BB_gain_force_max_gains_b1; /* 0xa848 - 0xa84c */
- volatile unsigned int BB_gains_min_offsets_b1; /* 0xa84c - 0xa850 */
- volatile char pad__23[0x1b0]; /* 0xa850 - 0xaa00 */
- volatile unsigned int BB_rx_ocgain2[128]; /* 0xaa00 - 0xac00 */
- volatile char pad__24[0x60c]; /* 0xac00 - 0xb20c */
- volatile unsigned int BB_ext_atten_switch_ctl_b1; /* 0xb20c - 0xb210 */
-} bb_lc_reg_reg_t;
-
-#endif /* __ASSEMBLER__ */
-
-#endif /* _BB_LC_REG_REG_H_ */
diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/efuse_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/efuse_reg.h
deleted file mode 100644
index 12cadb3..0000000
--- a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/efuse_reg.h
+++ /dev/null
@@ -1,108 +0,0 @@
-// ------------------------------------------------------------------
-// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
-//
-//
-// Permission to use, copy, modify, and/or distribute this software for any
-// purpose with or without fee is hereby granted, provided that the above
-// copyright notice and this permission notice appear in all copies.
-//
-// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-//
-//
-// ------------------------------------------------------------------
-//===================================================================
-// Author(s): ="Atheros"
-//===================================================================
-
-
-#ifndef _EFUSE_REG_REG_H_
-#define _EFUSE_REG_REG_H_
-
-#define EFUSE_WR_ENABLE_REG_ADDRESS 0x00000000
-#define EFUSE_WR_ENABLE_REG_OFFSET 0x00000000
-#define EFUSE_WR_ENABLE_REG_V_MSB 0
-#define EFUSE_WR_ENABLE_REG_V_LSB 0
-#define EFUSE_WR_ENABLE_REG_V_MASK 0x00000001
-#define EFUSE_WR_ENABLE_REG_V_GET(x) (((x) & EFUSE_WR_ENABLE_REG_V_MASK) >> EFUSE_WR_ENABLE_REG_V_LSB)
-#define EFUSE_WR_ENABLE_REG_V_SET(x) (((x) << EFUSE_WR_ENABLE_REG_V_LSB) & EFUSE_WR_ENABLE_REG_V_MASK)
-
-#define EFUSE_INT_ENABLE_REG_ADDRESS 0x00000004
-#define EFUSE_INT_ENABLE_REG_OFFSET 0x00000004
-#define EFUSE_INT_ENABLE_REG_V_MSB 0
-#define EFUSE_INT_ENABLE_REG_V_LSB 0
-#define EFUSE_INT_ENABLE_REG_V_MASK 0x00000001
-#define EFUSE_INT_ENABLE_REG_V_GET(x) (((x) & EFUSE_INT_ENABLE_REG_V_MASK) >> EFUSE_INT_ENABLE_REG_V_LSB)
-#define EFUSE_INT_ENABLE_REG_V_SET(x) (((x) << EFUSE_INT_ENABLE_REG_V_LSB) & EFUSE_INT_ENABLE_REG_V_MASK)
-
-#define EFUSE_INT_STATUS_REG_ADDRESS 0x00000008
-#define EFUSE_INT_STATUS_REG_OFFSET 0x00000008
-#define EFUSE_INT_STATUS_REG_V_MSB 0
-#define EFUSE_INT_STATUS_REG_V_LSB 0
-#define EFUSE_INT_STATUS_REG_V_MASK 0x00000001
-#define EFUSE_INT_STATUS_REG_V_GET(x) (((x) & EFUSE_INT_STATUS_REG_V_MASK) >> EFUSE_INT_STATUS_REG_V_LSB)
-#define EFUSE_INT_STATUS_REG_V_SET(x) (((x) << EFUSE_INT_STATUS_REG_V_LSB) & EFUSE_INT_STATUS_REG_V_MASK)
-
-#define BITMASK_WR_REG_ADDRESS 0x0000000c
-#define BITMASK_WR_REG_OFFSET 0x0000000c
-#define BITMASK_WR_REG_V_MSB 31
-#define BITMASK_WR_REG_V_LSB 0
-#define BITMASK_WR_REG_V_MASK 0xffffffff
-#define BITMASK_WR_REG_V_GET(x) (((x) & BITMASK_WR_REG_V_MASK) >> BITMASK_WR_REG_V_LSB)
-#define BITMASK_WR_REG_V_SET(x) (((x) << BITMASK_WR_REG_V_LSB) & BITMASK_WR_REG_V_MASK)
-
-#define VDDQ_SETTLE_TIME_REG_ADDRESS 0x00000010
-#define VDDQ_SETTLE_TIME_REG_OFFSET 0x00000010
-#define VDDQ_SETTLE_TIME_REG_V_MSB 31
-#define VDDQ_SETTLE_TIME_REG_V_LSB 0
-#define VDDQ_SETTLE_TIME_REG_V_MASK 0xffffffff
-#define VDDQ_SETTLE_TIME_REG_V_GET(x) (((x) & VDDQ_SETTLE_TIME_REG_V_MASK) >> VDDQ_SETTLE_TIME_REG_V_LSB)
-#define VDDQ_SETTLE_TIME_REG_V_SET(x) (((x) << VDDQ_SETTLE_TIME_REG_V_LSB) & VDDQ_SETTLE_TIME_REG_V_MASK)
-
-#define RD_STROBE_PW_REG_ADDRESS 0x00000014
-#define RD_STROBE_PW_REG_OFFSET 0x00000014
-#define RD_STROBE_PW_REG_V_MSB 31
-#define RD_STROBE_PW_REG_V_LSB 0
-#define RD_STROBE_PW_REG_V_MASK 0xffffffff
-#define RD_STROBE_PW_REG_V_GET(x) (((x) & RD_STROBE_PW_REG_V_MASK) >> RD_STROBE_PW_REG_V_LSB)
-#define RD_STROBE_PW_REG_V_SET(x) (((x) << RD_STROBE_PW_REG_V_LSB) & RD_STROBE_PW_REG_V_MASK)
-
-#define PG_STROBE_PW_REG_ADDRESS 0x00000018
-#define PG_STROBE_PW_REG_OFFSET 0x00000018
-#define PG_STROBE_PW_REG_V_MSB 31
-#define PG_STROBE_PW_REG_V_LSB 0
-#define PG_STROBE_PW_REG_V_MASK 0xffffffff
-#define PG_STROBE_PW_REG_V_GET(x) (((x) & PG_STROBE_PW_REG_V_MASK) >> PG_STROBE_PW_REG_V_LSB)
-#define PG_STROBE_PW_REG_V_SET(x) (((x) << PG_STROBE_PW_REG_V_LSB) & PG_STROBE_PW_REG_V_MASK)
-
-#define EFUSE_INTF_ADDRESS 0x00000800
-#define EFUSE_INTF_OFFSET 0x00000800
-#define EFUSE_INTF_R_MSB 31
-#define EFUSE_INTF_R_LSB 0
-#define EFUSE_INTF_R_MASK 0xffffffff
-#define EFUSE_INTF_R_GET(x) (((x) & EFUSE_INTF_R_MASK) >> EFUSE_INTF_R_LSB)
-#define EFUSE_INTF_R_SET(x) (((x) << EFUSE_INTF_R_LSB) & EFUSE_INTF_R_MASK)
-
-
-#ifndef __ASSEMBLER__
-
-typedef struct efuse_reg_reg_s {
- volatile unsigned int efuse_wr_enable_reg;
- volatile unsigned int efuse_int_enable_reg;
- volatile unsigned int efuse_int_status_reg;
- volatile unsigned int bitmask_wr_reg;
- volatile unsigned int vddq_settle_time_reg;
- volatile unsigned int rd_strobe_pw_reg;
- volatile unsigned int pg_strobe_pw_reg;
- unsigned char pad0[2020]; /* pad to 0x800 */
- volatile unsigned int efuse_intf[512];
-} efuse_reg_reg_t;
-
-#endif /* __ASSEMBLER__ */
-
-#endif /* _EFUSE_REG_H_ */
diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/gpio_athr_wlan_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/gpio_athr_wlan_reg.h
deleted file mode 100644
index 1adee70..0000000
--- a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/gpio_athr_wlan_reg.h
+++ /dev/null
@@ -1,1253 +0,0 @@
-// ------------------------------------------------------------------
-// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
-//
-//
-// Permission to use, copy, modify, and/or distribute this software for any
-// purpose with or without fee is hereby granted, provided that the above
-// copyright notice and this permission notice appear in all copies.
-//
-// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-//
-//
-// ------------------------------------------------------------------
-//===================================================================
-// Author(s): ="Atheros"
-//===================================================================
-
-
-#ifndef _GPIO_ATHR_WLAN_REG_REG_H_
-#define _GPIO_ATHR_WLAN_REG_REG_H_
-
-#define WLAN_GPIO_OUT_ADDRESS 0x00000000
-#define WLAN_GPIO_OUT_OFFSET 0x00000000
-#define WLAN_GPIO_OUT_DATA_MSB 25
-#define WLAN_GPIO_OUT_DATA_LSB 0
-#define WLAN_GPIO_OUT_DATA_MASK 0x03ffffff
-#define WLAN_GPIO_OUT_DATA_GET(x) (((x) & WLAN_GPIO_OUT_DATA_MASK) >> WLAN_GPIO_OUT_DATA_LSB)
-#define WLAN_GPIO_OUT_DATA_SET(x) (((x) << WLAN_GPIO_OUT_DATA_LSB) & WLAN_GPIO_OUT_DATA_MASK)
-
-#define WLAN_GPIO_OUT_W1TS_ADDRESS 0x00000004
-#define WLAN_GPIO_OUT_W1TS_OFFSET 0x00000004
-#define WLAN_GPIO_OUT_W1TS_DATA_MSB 25
-#define WLAN_GPIO_OUT_W1TS_DATA_LSB 0
-#define WLAN_GPIO_OUT_W1TS_DATA_MASK 0x03ffffff
-#define WLAN_GPIO_OUT_W1TS_DATA_GET(x) (((x) & WLAN_GPIO_OUT_W1TS_DATA_MASK) >> WLAN_GPIO_OUT_W1TS_DATA_LSB)
-#define WLAN_GPIO_OUT_W1TS_DATA_SET(x) (((x) << WLAN_GPIO_OUT_W1TS_DATA_LSB) & WLAN_GPIO_OUT_W1TS_DATA_MASK)
-
-#define WLAN_GPIO_OUT_W1TC_ADDRESS 0x00000008
-#define WLAN_GPIO_OUT_W1TC_OFFSET 0x00000008
-#define WLAN_GPIO_OUT_W1TC_DATA_MSB 25
-#define WLAN_GPIO_OUT_W1TC_DATA_LSB 0
-#define WLAN_GPIO_OUT_W1TC_DATA_MASK 0x03ffffff
-#define WLAN_GPIO_OUT_W1TC_DATA_GET(x) (((x) & WLAN_GPIO_OUT_W1TC_DATA_MASK) >> WLAN_GPIO_OUT_W1TC_DATA_LSB)
-#define WLAN_GPIO_OUT_W1TC_DATA_SET(x) (((x) << WLAN_GPIO_OUT_W1TC_DATA_LSB) & WLAN_GPIO_OUT_W1TC_DATA_MASK)
-
-#define WLAN_GPIO_ENABLE_ADDRESS 0x0000000c
-#define WLAN_GPIO_ENABLE_OFFSET 0x0000000c
-#define WLAN_GPIO_ENABLE_DATA_MSB 25
-#define WLAN_GPIO_ENABLE_DATA_LSB 0
-#define WLAN_GPIO_ENABLE_DATA_MASK 0x03ffffff
-#define WLAN_GPIO_ENABLE_DATA_GET(x) (((x) & WLAN_GPIO_ENABLE_DATA_MASK) >> WLAN_GPIO_ENABLE_DATA_LSB)
-#define WLAN_GPIO_ENABLE_DATA_SET(x) (((x) << WLAN_GPIO_ENABLE_DATA_LSB) & WLAN_GPIO_ENABLE_DATA_MASK)
-
-#define WLAN_GPIO_ENABLE_W1TS_ADDRESS 0x00000010
-#define WLAN_GPIO_ENABLE_W1TS_OFFSET 0x00000010
-#define WLAN_GPIO_ENABLE_W1TS_DATA_MSB 25
-#define WLAN_GPIO_ENABLE_W1TS_DATA_LSB 0
-#define WLAN_GPIO_ENABLE_W1TS_DATA_MASK 0x03ffffff
-#define WLAN_GPIO_ENABLE_W1TS_DATA_GET(x) (((x) & WLAN_GPIO_ENABLE_W1TS_DATA_MASK) >> WLAN_GPIO_ENABLE_W1TS_DATA_LSB)
-#define WLAN_GPIO_ENABLE_W1TS_DATA_SET(x) (((x) << WLAN_GPIO_ENABLE_W1TS_DATA_LSB) & WLAN_GPIO_ENABLE_W1TS_DATA_MASK)
-
-#define WLAN_GPIO_ENABLE_W1TC_ADDRESS 0x00000014
-#define WLAN_GPIO_ENABLE_W1TC_OFFSET 0x00000014
-#define WLAN_GPIO_ENABLE_W1TC_DATA_MSB 25
-#define WLAN_GPIO_ENABLE_W1TC_DATA_LSB 0
-#define WLAN_GPIO_ENABLE_W1TC_DATA_MASK 0x03ffffff
-#define WLAN_GPIO_ENABLE_W1TC_DATA_GET(x) (((x) & WLAN_GPIO_ENABLE_W1TC_DATA_MASK) >> WLAN_GPIO_ENABLE_W1TC_DATA_LSB)
-#define WLAN_GPIO_ENABLE_W1TC_DATA_SET(x) (((x) << WLAN_GPIO_ENABLE_W1TC_DATA_LSB) & WLAN_GPIO_ENABLE_W1TC_DATA_MASK)
-
-#define WLAN_GPIO_IN_ADDRESS 0x00000018
-#define WLAN_GPIO_IN_OFFSET 0x00000018
-#define WLAN_GPIO_IN_DATA_MSB 25
-#define WLAN_GPIO_IN_DATA_LSB 0
-#define WLAN_GPIO_IN_DATA_MASK 0x03ffffff
-#define WLAN_GPIO_IN_DATA_GET(x) (((x) & WLAN_GPIO_IN_DATA_MASK) >> WLAN_GPIO_IN_DATA_LSB)
-#define WLAN_GPIO_IN_DATA_SET(x) (((x) << WLAN_GPIO_IN_DATA_LSB) & WLAN_GPIO_IN_DATA_MASK)
-
-#define WLAN_GPIO_STATUS_ADDRESS 0x0000001c
-#define WLAN_GPIO_STATUS_OFFSET 0x0000001c
-#define WLAN_GPIO_STATUS_INTERRUPT_MSB 25
-#define WLAN_GPIO_STATUS_INTERRUPT_LSB 0
-#define WLAN_GPIO_STATUS_INTERRUPT_MASK 0x03ffffff
-#define WLAN_GPIO_STATUS_INTERRUPT_GET(x) (((x) & WLAN_GPIO_STATUS_INTERRUPT_MASK) >> WLAN_GPIO_STATUS_INTERRUPT_LSB)
-#define WLAN_GPIO_STATUS_INTERRUPT_SET(x) (((x) << WLAN_GPIO_STATUS_INTERRUPT_LSB) & WLAN_GPIO_STATUS_INTERRUPT_MASK)
-
-#define WLAN_GPIO_STATUS_W1TS_ADDRESS 0x00000020
-#define WLAN_GPIO_STATUS_W1TS_OFFSET 0x00000020
-#define WLAN_GPIO_STATUS_W1TS_INTERRUPT_MSB 25
-#define WLAN_GPIO_STATUS_W1TS_INTERRUPT_LSB 0
-#define WLAN_GPIO_STATUS_W1TS_INTERRUPT_MASK 0x03ffffff
-#define WLAN_GPIO_STATUS_W1TS_INTERRUPT_GET(x) (((x) & WLAN_GPIO_STATUS_W1TS_INTERRUPT_MASK) >> WLAN_GPIO_STATUS_W1TS_INTERRUPT_LSB)
-#define WLAN_GPIO_STATUS_W1TS_INTERRUPT_SET(x) (((x) << WLAN_GPIO_STATUS_W1TS_INTERRUPT_LSB) & WLAN_GPIO_STATUS_W1TS_INTERRUPT_MASK)
-
-#define WLAN_GPIO_STATUS_W1TC_ADDRESS 0x00000024
-#define WLAN_GPIO_STATUS_W1TC_OFFSET 0x00000024
-#define WLAN_GPIO_STATUS_W1TC_INTERRUPT_MSB 25
-#define WLAN_GPIO_STATUS_W1TC_INTERRUPT_LSB 0
-#define WLAN_GPIO_STATUS_W1TC_INTERRUPT_MASK 0x03ffffff
-#define WLAN_GPIO_STATUS_W1TC_INTERRUPT_GET(x) (((x) & WLAN_GPIO_STATUS_W1TC_INTERRUPT_MASK) >> WLAN_GPIO_STATUS_W1TC_INTERRUPT_LSB)
-#define WLAN_GPIO_STATUS_W1TC_INTERRUPT_SET(x) (((x) << WLAN_GPIO_STATUS_W1TC_INTERRUPT_LSB) & WLAN_GPIO_STATUS_W1TC_INTERRUPT_MASK)
-
-#define WLAN_GPIO_PIN0_ADDRESS 0x00000028
-#define WLAN_GPIO_PIN0_OFFSET 0x00000028
-#define WLAN_GPIO_PIN0_CONFIG_MSB 13
-#define WLAN_GPIO_PIN0_CONFIG_LSB 11
-#define WLAN_GPIO_PIN0_CONFIG_MASK 0x00003800
-#define WLAN_GPIO_PIN0_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN0_CONFIG_MASK) >> WLAN_GPIO_PIN0_CONFIG_LSB)
-#define WLAN_GPIO_PIN0_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN0_CONFIG_LSB) & WLAN_GPIO_PIN0_CONFIG_MASK)
-#define WLAN_GPIO_PIN0_WAKEUP_ENABLE_MSB 10
-#define WLAN_GPIO_PIN0_WAKEUP_ENABLE_LSB 10
-#define WLAN_GPIO_PIN0_WAKEUP_ENABLE_MASK 0x00000400
-#define WLAN_GPIO_PIN0_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN0_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN0_WAKEUP_ENABLE_LSB)
-#define WLAN_GPIO_PIN0_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN0_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN0_WAKEUP_ENABLE_MASK)
-#define WLAN_GPIO_PIN0_INT_TYPE_MSB 9
-#define WLAN_GPIO_PIN0_INT_TYPE_LSB 7
-#define WLAN_GPIO_PIN0_INT_TYPE_MASK 0x00000380
-#define WLAN_GPIO_PIN0_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN0_INT_TYPE_MASK) >> WLAN_GPIO_PIN0_INT_TYPE_LSB)
-#define WLAN_GPIO_PIN0_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN0_INT_TYPE_LSB) & WLAN_GPIO_PIN0_INT_TYPE_MASK)
-#define WLAN_GPIO_PIN0_PAD_PULL_MSB 6
-#define WLAN_GPIO_PIN0_PAD_PULL_LSB 5
-#define WLAN_GPIO_PIN0_PAD_PULL_MASK 0x00000060
-#define WLAN_GPIO_PIN0_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN0_PAD_PULL_MASK) >> WLAN_GPIO_PIN0_PAD_PULL_LSB)
-#define WLAN_GPIO_PIN0_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN0_PAD_PULL_LSB) & WLAN_GPIO_PIN0_PAD_PULL_MASK)
-#define WLAN_GPIO_PIN0_PAD_STRENGTH_MSB 4
-#define WLAN_GPIO_PIN0_PAD_STRENGTH_LSB 3
-#define WLAN_GPIO_PIN0_PAD_STRENGTH_MASK 0x00000018
-#define WLAN_GPIO_PIN0_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN0_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN0_PAD_STRENGTH_LSB)
-#define WLAN_GPIO_PIN0_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN0_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN0_PAD_STRENGTH_MASK)
-#define WLAN_GPIO_PIN0_PAD_DRIVER_MSB 2
-#define WLAN_GPIO_PIN0_PAD_DRIVER_LSB 2
-#define WLAN_GPIO_PIN0_PAD_DRIVER_MASK 0x00000004
-#define WLAN_GPIO_PIN0_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN0_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN0_PAD_DRIVER_LSB)
-#define WLAN_GPIO_PIN0_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN0_PAD_DRIVER_LSB) & WLAN_GPIO_PIN0_PAD_DRIVER_MASK)
-#define WLAN_GPIO_PIN0_SOURCE_MSB 0
-#define WLAN_GPIO_PIN0_SOURCE_LSB 0
-#define WLAN_GPIO_PIN0_SOURCE_MASK 0x00000001
-#define WLAN_GPIO_PIN0_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN0_SOURCE_MASK) >> WLAN_GPIO_PIN0_SOURCE_LSB)
-#define WLAN_GPIO_PIN0_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN0_SOURCE_LSB) & WLAN_GPIO_PIN0_SOURCE_MASK)
-
-#define WLAN_GPIO_PIN1_ADDRESS 0x0000002c
-#define WLAN_GPIO_PIN1_OFFSET 0x0000002c
-#define WLAN_GPIO_PIN1_CONFIG_MSB 13
-#define WLAN_GPIO_PIN1_CONFIG_LSB 11
-#define WLAN_GPIO_PIN1_CONFIG_MASK 0x00003800
-#define WLAN_GPIO_PIN1_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN1_CONFIG_MASK) >> WLAN_GPIO_PIN1_CONFIG_LSB)
-#define WLAN_GPIO_PIN1_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN1_CONFIG_LSB) & WLAN_GPIO_PIN1_CONFIG_MASK)
-#define WLAN_GPIO_PIN1_WAKEUP_ENABLE_MSB 10
-#define WLAN_GPIO_PIN1_WAKEUP_ENABLE_LSB 10
-#define WLAN_GPIO_PIN1_WAKEUP_ENABLE_MASK 0x00000400
-#define WLAN_GPIO_PIN1_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN1_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN1_WAKEUP_ENABLE_LSB)
-#define WLAN_GPIO_PIN1_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN1_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN1_WAKEUP_ENABLE_MASK)
-#define WLAN_GPIO_PIN1_INT_TYPE_MSB 9
-#define WLAN_GPIO_PIN1_INT_TYPE_LSB 7
-#define WLAN_GPIO_PIN1_INT_TYPE_MASK 0x00000380
-#define WLAN_GPIO_PIN1_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN1_INT_TYPE_MASK) >> WLAN_GPIO_PIN1_INT_TYPE_LSB)
-#define WLAN_GPIO_PIN1_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN1_INT_TYPE_LSB) & WLAN_GPIO_PIN1_INT_TYPE_MASK)
-#define WLAN_GPIO_PIN1_PAD_PULL_MSB 6
-#define WLAN_GPIO_PIN1_PAD_PULL_LSB 5
-#define WLAN_GPIO_PIN1_PAD_PULL_MASK 0x00000060
-#define WLAN_GPIO_PIN1_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN1_PAD_PULL_MASK) >> WLAN_GPIO_PIN1_PAD_PULL_LSB)
-#define WLAN_GPIO_PIN1_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN1_PAD_PULL_LSB) & WLAN_GPIO_PIN1_PAD_PULL_MASK)
-#define WLAN_GPIO_PIN1_PAD_STRENGTH_MSB 4
-#define WLAN_GPIO_PIN1_PAD_STRENGTH_LSB 3
-#define WLAN_GPIO_PIN1_PAD_STRENGTH_MASK 0x00000018
-#define WLAN_GPIO_PIN1_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN1_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN1_PAD_STRENGTH_LSB)
-#define WLAN_GPIO_PIN1_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN1_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN1_PAD_STRENGTH_MASK)
-#define WLAN_GPIO_PIN1_PAD_DRIVER_MSB 2
-#define WLAN_GPIO_PIN1_PAD_DRIVER_LSB 2
-#define WLAN_GPIO_PIN1_PAD_DRIVER_MASK 0x00000004
-#define WLAN_GPIO_PIN1_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN1_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN1_PAD_DRIVER_LSB)
-#define WLAN_GPIO_PIN1_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN1_PAD_DRIVER_LSB) & WLAN_GPIO_PIN1_PAD_DRIVER_MASK)
-#define WLAN_GPIO_PIN1_SOURCE_MSB 0
-#define WLAN_GPIO_PIN1_SOURCE_LSB 0
-#define WLAN_GPIO_PIN1_SOURCE_MASK 0x00000001
-#define WLAN_GPIO_PIN1_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN1_SOURCE_MASK) >> WLAN_GPIO_PIN1_SOURCE_LSB)
-#define WLAN_GPIO_PIN1_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN1_SOURCE_LSB) & WLAN_GPIO_PIN1_SOURCE_MASK)
-
-#define WLAN_GPIO_PIN2_ADDRESS 0x00000030
-#define WLAN_GPIO_PIN2_OFFSET 0x00000030
-#define WLAN_GPIO_PIN2_CONFIG_MSB 13
-#define WLAN_GPIO_PIN2_CONFIG_LSB 11
-#define WLAN_GPIO_PIN2_CONFIG_MASK 0x00003800
-#define WLAN_GPIO_PIN2_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN2_CONFIG_MASK) >> WLAN_GPIO_PIN2_CONFIG_LSB)
-#define WLAN_GPIO_PIN2_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN2_CONFIG_LSB) & WLAN_GPIO_PIN2_CONFIG_MASK)
-#define WLAN_GPIO_PIN2_WAKEUP_ENABLE_MSB 10
-#define WLAN_GPIO_PIN2_WAKEUP_ENABLE_LSB 10
-#define WLAN_GPIO_PIN2_WAKEUP_ENABLE_MASK 0x00000400
-#define WLAN_GPIO_PIN2_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN2_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN2_WAKEUP_ENABLE_LSB)
-#define WLAN_GPIO_PIN2_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN2_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN2_WAKEUP_ENABLE_MASK)
-#define WLAN_GPIO_PIN2_INT_TYPE_MSB 9
-#define WLAN_GPIO_PIN2_INT_TYPE_LSB 7
-#define WLAN_GPIO_PIN2_INT_TYPE_MASK 0x00000380
-#define WLAN_GPIO_PIN2_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN2_INT_TYPE_MASK) >> WLAN_GPIO_PIN2_INT_TYPE_LSB)
-#define WLAN_GPIO_PIN2_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN2_INT_TYPE_LSB) & WLAN_GPIO_PIN2_INT_TYPE_MASK)
-#define WLAN_GPIO_PIN2_PAD_PULL_MSB 6
-#define WLAN_GPIO_PIN2_PAD_PULL_LSB 5
-#define WLAN_GPIO_PIN2_PAD_PULL_MASK 0x00000060
-#define WLAN_GPIO_PIN2_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN2_PAD_PULL_MASK) >> WLAN_GPIO_PIN2_PAD_PULL_LSB)
-#define WLAN_GPIO_PIN2_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN2_PAD_PULL_LSB) & WLAN_GPIO_PIN2_PAD_PULL_MASK)
-#define WLAN_GPIO_PIN2_PAD_STRENGTH_MSB 4
-#define WLAN_GPIO_PIN2_PAD_STRENGTH_LSB 3
-#define WLAN_GPIO_PIN2_PAD_STRENGTH_MASK 0x00000018
-#define WLAN_GPIO_PIN2_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN2_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN2_PAD_STRENGTH_LSB)
-#define WLAN_GPIO_PIN2_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN2_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN2_PAD_STRENGTH_MASK)
-#define WLAN_GPIO_PIN2_PAD_DRIVER_MSB 2
-#define WLAN_GPIO_PIN2_PAD_DRIVER_LSB 2
-#define WLAN_GPIO_PIN2_PAD_DRIVER_MASK 0x00000004
-#define WLAN_GPIO_PIN2_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN2_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN2_PAD_DRIVER_LSB)
-#define WLAN_GPIO_PIN2_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN2_PAD_DRIVER_LSB) & WLAN_GPIO_PIN2_PAD_DRIVER_MASK)
-#define WLAN_GPIO_PIN2_SOURCE_MSB 0
-#define WLAN_GPIO_PIN2_SOURCE_LSB 0
-#define WLAN_GPIO_PIN2_SOURCE_MASK 0x00000001
-#define WLAN_GPIO_PIN2_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN2_SOURCE_MASK) >> WLAN_GPIO_PIN2_SOURCE_LSB)
-#define WLAN_GPIO_PIN2_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN2_SOURCE_LSB) & WLAN_GPIO_PIN2_SOURCE_MASK)
-
-#define WLAN_GPIO_PIN3_ADDRESS 0x00000034
-#define WLAN_GPIO_PIN3_OFFSET 0x00000034
-#define WLAN_GPIO_PIN3_CONFIG_MSB 13
-#define WLAN_GPIO_PIN3_CONFIG_LSB 11
-#define WLAN_GPIO_PIN3_CONFIG_MASK 0x00003800
-#define WLAN_GPIO_PIN3_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN3_CONFIG_MASK) >> WLAN_GPIO_PIN3_CONFIG_LSB)
-#define WLAN_GPIO_PIN3_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN3_CONFIG_LSB) & WLAN_GPIO_PIN3_CONFIG_MASK)
-#define WLAN_GPIO_PIN3_WAKEUP_ENABLE_MSB 10
-#define WLAN_GPIO_PIN3_WAKEUP_ENABLE_LSB 10
-#define WLAN_GPIO_PIN3_WAKEUP_ENABLE_MASK 0x00000400
-#define WLAN_GPIO_PIN3_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN3_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN3_WAKEUP_ENABLE_LSB)
-#define WLAN_GPIO_PIN3_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN3_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN3_WAKEUP_ENABLE_MASK)
-#define WLAN_GPIO_PIN3_INT_TYPE_MSB 9
-#define WLAN_GPIO_PIN3_INT_TYPE_LSB 7
-#define WLAN_GPIO_PIN3_INT_TYPE_MASK 0x00000380
-#define WLAN_GPIO_PIN3_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN3_INT_TYPE_MASK) >> WLAN_GPIO_PIN3_INT_TYPE_LSB)
-#define WLAN_GPIO_PIN3_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN3_INT_TYPE_LSB) & WLAN_GPIO_PIN3_INT_TYPE_MASK)
-#define WLAN_GPIO_PIN3_PAD_PULL_MSB 6
-#define WLAN_GPIO_PIN3_PAD_PULL_LSB 5
-#define WLAN_GPIO_PIN3_PAD_PULL_MASK 0x00000060
-#define WLAN_GPIO_PIN3_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN3_PAD_PULL_MASK) >> WLAN_GPIO_PIN3_PAD_PULL_LSB)
-#define WLAN_GPIO_PIN3_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN3_PAD_PULL_LSB) & WLAN_GPIO_PIN3_PAD_PULL_MASK)
-#define WLAN_GPIO_PIN3_PAD_STRENGTH_MSB 4
-#define WLAN_GPIO_PIN3_PAD_STRENGTH_LSB 3
-#define WLAN_GPIO_PIN3_PAD_STRENGTH_MASK 0x00000018
-#define WLAN_GPIO_PIN3_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN3_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN3_PAD_STRENGTH_LSB)
-#define WLAN_GPIO_PIN3_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN3_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN3_PAD_STRENGTH_MASK)
-#define WLAN_GPIO_PIN3_PAD_DRIVER_MSB 2
-#define WLAN_GPIO_PIN3_PAD_DRIVER_LSB 2
-#define WLAN_GPIO_PIN3_PAD_DRIVER_MASK 0x00000004
-#define WLAN_GPIO_PIN3_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN3_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN3_PAD_DRIVER_LSB)
-#define WLAN_GPIO_PIN3_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN3_PAD_DRIVER_LSB) & WLAN_GPIO_PIN3_PAD_DRIVER_MASK)
-#define WLAN_GPIO_PIN3_SOURCE_MSB 0
-#define WLAN_GPIO_PIN3_SOURCE_LSB 0
-#define WLAN_GPIO_PIN3_SOURCE_MASK 0x00000001
-#define WLAN_GPIO_PIN3_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN3_SOURCE_MASK) >> WLAN_GPIO_PIN3_SOURCE_LSB)
-#define WLAN_GPIO_PIN3_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN3_SOURCE_LSB) & WLAN_GPIO_PIN3_SOURCE_MASK)
-
-#define WLAN_GPIO_PIN4_ADDRESS 0x00000038
-#define WLAN_GPIO_PIN4_OFFSET 0x00000038
-#define WLAN_GPIO_PIN4_CONFIG_MSB 13
-#define WLAN_GPIO_PIN4_CONFIG_LSB 11
-#define WLAN_GPIO_PIN4_CONFIG_MASK 0x00003800
-#define WLAN_GPIO_PIN4_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN4_CONFIG_MASK) >> WLAN_GPIO_PIN4_CONFIG_LSB)
-#define WLAN_GPIO_PIN4_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN4_CONFIG_LSB) & WLAN_GPIO_PIN4_CONFIG_MASK)
-#define WLAN_GPIO_PIN4_WAKEUP_ENABLE_MSB 10
-#define WLAN_GPIO_PIN4_WAKEUP_ENABLE_LSB 10
-#define WLAN_GPIO_PIN4_WAKEUP_ENABLE_MASK 0x00000400
-#define WLAN_GPIO_PIN4_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN4_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN4_WAKEUP_ENABLE_LSB)
-#define WLAN_GPIO_PIN4_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN4_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN4_WAKEUP_ENABLE_MASK)
-#define WLAN_GPIO_PIN4_INT_TYPE_MSB 9
-#define WLAN_GPIO_PIN4_INT_TYPE_LSB 7
-#define WLAN_GPIO_PIN4_INT_TYPE_MASK 0x00000380
-#define WLAN_GPIO_PIN4_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN4_INT_TYPE_MASK) >> WLAN_GPIO_PIN4_INT_TYPE_LSB)
-#define WLAN_GPIO_PIN4_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN4_INT_TYPE_LSB) & WLAN_GPIO_PIN4_INT_TYPE_MASK)
-#define WLAN_GPIO_PIN4_PAD_PULL_MSB 6
-#define WLAN_GPIO_PIN4_PAD_PULL_LSB 5
-#define WLAN_GPIO_PIN4_PAD_PULL_MASK 0x00000060
-#define WLAN_GPIO_PIN4_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN4_PAD_PULL_MASK) >> WLAN_GPIO_PIN4_PAD_PULL_LSB)
-#define WLAN_GPIO_PIN4_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN4_PAD_PULL_LSB) & WLAN_GPIO_PIN4_PAD_PULL_MASK)
-#define WLAN_GPIO_PIN4_PAD_STRENGTH_MSB 4
-#define WLAN_GPIO_PIN4_PAD_STRENGTH_LSB 3
-#define WLAN_GPIO_PIN4_PAD_STRENGTH_MASK 0x00000018
-#define WLAN_GPIO_PIN4_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN4_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN4_PAD_STRENGTH_LSB)
-#define WLAN_GPIO_PIN4_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN4_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN4_PAD_STRENGTH_MASK)
-#define WLAN_GPIO_PIN4_PAD_DRIVER_MSB 2
-#define WLAN_GPIO_PIN4_PAD_DRIVER_LSB 2
-#define WLAN_GPIO_PIN4_PAD_DRIVER_MASK 0x00000004
-#define WLAN_GPIO_PIN4_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN4_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN4_PAD_DRIVER_LSB)
-#define WLAN_GPIO_PIN4_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN4_PAD_DRIVER_LSB) & WLAN_GPIO_PIN4_PAD_DRIVER_MASK)
-#define WLAN_GPIO_PIN4_SOURCE_MSB 0
-#define WLAN_GPIO_PIN4_SOURCE_LSB 0
-#define WLAN_GPIO_PIN4_SOURCE_MASK 0x00000001
-#define WLAN_GPIO_PIN4_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN4_SOURCE_MASK) >> WLAN_GPIO_PIN4_SOURCE_LSB)
-#define WLAN_GPIO_PIN4_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN4_SOURCE_LSB) & WLAN_GPIO_PIN4_SOURCE_MASK)
-
-#define WLAN_GPIO_PIN5_ADDRESS 0x0000003c
-#define WLAN_GPIO_PIN5_OFFSET 0x0000003c
-#define WLAN_GPIO_PIN5_CONFIG_MSB 13
-#define WLAN_GPIO_PIN5_CONFIG_LSB 11
-#define WLAN_GPIO_PIN5_CONFIG_MASK 0x00003800
-#define WLAN_GPIO_PIN5_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN5_CONFIG_MASK) >> WLAN_GPIO_PIN5_CONFIG_LSB)
-#define WLAN_GPIO_PIN5_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN5_CONFIG_LSB) & WLAN_GPIO_PIN5_CONFIG_MASK)
-#define WLAN_GPIO_PIN5_WAKEUP_ENABLE_MSB 10
-#define WLAN_GPIO_PIN5_WAKEUP_ENABLE_LSB 10
-#define WLAN_GPIO_PIN5_WAKEUP_ENABLE_MASK 0x00000400
-#define WLAN_GPIO_PIN5_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN5_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN5_WAKEUP_ENABLE_LSB)
-#define WLAN_GPIO_PIN5_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN5_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN5_WAKEUP_ENABLE_MASK)
-#define WLAN_GPIO_PIN5_INT_TYPE_MSB 9
-#define WLAN_GPIO_PIN5_INT_TYPE_LSB 7
-#define WLAN_GPIO_PIN5_INT_TYPE_MASK 0x00000380
-#define WLAN_GPIO_PIN5_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN5_INT_TYPE_MASK) >> WLAN_GPIO_PIN5_INT_TYPE_LSB)
-#define WLAN_GPIO_PIN5_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN5_INT_TYPE_LSB) & WLAN_GPIO_PIN5_INT_TYPE_MASK)
-#define WLAN_GPIO_PIN5_PAD_PULL_MSB 6
-#define WLAN_GPIO_PIN5_PAD_PULL_LSB 5
-#define WLAN_GPIO_PIN5_PAD_PULL_MASK 0x00000060
-#define WLAN_GPIO_PIN5_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN5_PAD_PULL_MASK) >> WLAN_GPIO_PIN5_PAD_PULL_LSB)
-#define WLAN_GPIO_PIN5_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN5_PAD_PULL_LSB) & WLAN_GPIO_PIN5_PAD_PULL_MASK)
-#define WLAN_GPIO_PIN5_PAD_STRENGTH_MSB 4
-#define WLAN_GPIO_PIN5_PAD_STRENGTH_LSB 3
-#define WLAN_GPIO_PIN5_PAD_STRENGTH_MASK 0x00000018
-#define WLAN_GPIO_PIN5_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN5_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN5_PAD_STRENGTH_LSB)
-#define WLAN_GPIO_PIN5_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN5_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN5_PAD_STRENGTH_MASK)
-#define WLAN_GPIO_PIN5_PAD_DRIVER_MSB 2
-#define WLAN_GPIO_PIN5_PAD_DRIVER_LSB 2
-#define WLAN_GPIO_PIN5_PAD_DRIVER_MASK 0x00000004
-#define WLAN_GPIO_PIN5_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN5_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN5_PAD_DRIVER_LSB)
-#define WLAN_GPIO_PIN5_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN5_PAD_DRIVER_LSB) & WLAN_GPIO_PIN5_PAD_DRIVER_MASK)
-#define WLAN_GPIO_PIN5_SOURCE_MSB 0
-#define WLAN_GPIO_PIN5_SOURCE_LSB 0
-#define WLAN_GPIO_PIN5_SOURCE_MASK 0x00000001
-#define WLAN_GPIO_PIN5_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN5_SOURCE_MASK) >> WLAN_GPIO_PIN5_SOURCE_LSB)
-#define WLAN_GPIO_PIN5_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN5_SOURCE_LSB) & WLAN_GPIO_PIN5_SOURCE_MASK)
-
-#define WLAN_GPIO_PIN6_ADDRESS 0x00000040
-#define WLAN_GPIO_PIN6_OFFSET 0x00000040
-#define WLAN_GPIO_PIN6_CONFIG_MSB 13
-#define WLAN_GPIO_PIN6_CONFIG_LSB 11
-#define WLAN_GPIO_PIN6_CONFIG_MASK 0x00003800
-#define WLAN_GPIO_PIN6_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN6_CONFIG_MASK) >> WLAN_GPIO_PIN6_CONFIG_LSB)
-#define WLAN_GPIO_PIN6_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN6_CONFIG_LSB) & WLAN_GPIO_PIN6_CONFIG_MASK)
-#define WLAN_GPIO_PIN6_WAKEUP_ENABLE_MSB 10
-#define WLAN_GPIO_PIN6_WAKEUP_ENABLE_LSB 10
-#define WLAN_GPIO_PIN6_WAKEUP_ENABLE_MASK 0x00000400
-#define WLAN_GPIO_PIN6_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN6_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN6_WAKEUP_ENABLE_LSB)
-#define WLAN_GPIO_PIN6_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN6_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN6_WAKEUP_ENABLE_MASK)
-#define WLAN_GPIO_PIN6_INT_TYPE_MSB 9
-#define WLAN_GPIO_PIN6_INT_TYPE_LSB 7
-#define WLAN_GPIO_PIN6_INT_TYPE_MASK 0x00000380
-#define WLAN_GPIO_PIN6_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN6_INT_TYPE_MASK) >> WLAN_GPIO_PIN6_INT_TYPE_LSB)
-#define WLAN_GPIO_PIN6_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN6_INT_TYPE_LSB) & WLAN_GPIO_PIN6_INT_TYPE_MASK)
-#define WLAN_GPIO_PIN6_PAD_PULL_MSB 6
-#define WLAN_GPIO_PIN6_PAD_PULL_LSB 5
-#define WLAN_GPIO_PIN6_PAD_PULL_MASK 0x00000060
-#define WLAN_GPIO_PIN6_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN6_PAD_PULL_MASK) >> WLAN_GPIO_PIN6_PAD_PULL_LSB)
-#define WLAN_GPIO_PIN6_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN6_PAD_PULL_LSB) & WLAN_GPIO_PIN6_PAD_PULL_MASK)
-#define WLAN_GPIO_PIN6_PAD_STRENGTH_MSB 4
-#define WLAN_GPIO_PIN6_PAD_STRENGTH_LSB 3
-#define WLAN_GPIO_PIN6_PAD_STRENGTH_MASK 0x00000018
-#define WLAN_GPIO_PIN6_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN6_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN6_PAD_STRENGTH_LSB)
-#define WLAN_GPIO_PIN6_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN6_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN6_PAD_STRENGTH_MASK)
-#define WLAN_GPIO_PIN6_PAD_DRIVER_MSB 2
-#define WLAN_GPIO_PIN6_PAD_DRIVER_LSB 2
-#define WLAN_GPIO_PIN6_PAD_DRIVER_MASK 0x00000004
-#define WLAN_GPIO_PIN6_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN6_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN6_PAD_DRIVER_LSB)
-#define WLAN_GPIO_PIN6_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN6_PAD_DRIVER_LSB) & WLAN_GPIO_PIN6_PAD_DRIVER_MASK)
-#define WLAN_GPIO_PIN6_SOURCE_MSB 0
-#define WLAN_GPIO_PIN6_SOURCE_LSB 0
-#define WLAN_GPIO_PIN6_SOURCE_MASK 0x00000001
-#define WLAN_GPIO_PIN6_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN6_SOURCE_MASK) >> WLAN_GPIO_PIN6_SOURCE_LSB)
-#define WLAN_GPIO_PIN6_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN6_SOURCE_LSB) & WLAN_GPIO_PIN6_SOURCE_MASK)
-
-#define WLAN_GPIO_PIN7_ADDRESS 0x00000044
-#define WLAN_GPIO_PIN7_OFFSET 0x00000044
-#define WLAN_GPIO_PIN7_CONFIG_MSB 13
-#define WLAN_GPIO_PIN7_CONFIG_LSB 11
-#define WLAN_GPIO_PIN7_CONFIG_MASK 0x00003800
-#define WLAN_GPIO_PIN7_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN7_CONFIG_MASK) >> WLAN_GPIO_PIN7_CONFIG_LSB)
-#define WLAN_GPIO_PIN7_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN7_CONFIG_LSB) & WLAN_GPIO_PIN7_CONFIG_MASK)
-#define WLAN_GPIO_PIN7_WAKEUP_ENABLE_MSB 10
-#define WLAN_GPIO_PIN7_WAKEUP_ENABLE_LSB 10
-#define WLAN_GPIO_PIN7_WAKEUP_ENABLE_MASK 0x00000400
-#define WLAN_GPIO_PIN7_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN7_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN7_WAKEUP_ENABLE_LSB)
-#define WLAN_GPIO_PIN7_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN7_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN7_WAKEUP_ENABLE_MASK)
-#define WLAN_GPIO_PIN7_INT_TYPE_MSB 9
-#define WLAN_GPIO_PIN7_INT_TYPE_LSB 7
-#define WLAN_GPIO_PIN7_INT_TYPE_MASK 0x00000380
-#define WLAN_GPIO_PIN7_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN7_INT_TYPE_MASK) >> WLAN_GPIO_PIN7_INT_TYPE_LSB)
-#define WLAN_GPIO_PIN7_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN7_INT_TYPE_LSB) & WLAN_GPIO_PIN7_INT_TYPE_MASK)
-#define WLAN_GPIO_PIN7_PAD_PULL_MSB 6
-#define WLAN_GPIO_PIN7_PAD_PULL_LSB 5
-#define WLAN_GPIO_PIN7_PAD_PULL_MASK 0x00000060
-#define WLAN_GPIO_PIN7_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN7_PAD_PULL_MASK) >> WLAN_GPIO_PIN7_PAD_PULL_LSB)
-#define WLAN_GPIO_PIN7_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN7_PAD_PULL_LSB) & WLAN_GPIO_PIN7_PAD_PULL_MASK)
-#define WLAN_GPIO_PIN7_PAD_STRENGTH_MSB 4
-#define WLAN_GPIO_PIN7_PAD_STRENGTH_LSB 3
-#define WLAN_GPIO_PIN7_PAD_STRENGTH_MASK 0x00000018
-#define WLAN_GPIO_PIN7_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN7_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN7_PAD_STRENGTH_LSB)
-#define WLAN_GPIO_PIN7_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN7_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN7_PAD_STRENGTH_MASK)
-#define WLAN_GPIO_PIN7_PAD_DRIVER_MSB 2
-#define WLAN_GPIO_PIN7_PAD_DRIVER_LSB 2
-#define WLAN_GPIO_PIN7_PAD_DRIVER_MASK 0x00000004
-#define WLAN_GPIO_PIN7_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN7_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN7_PAD_DRIVER_LSB)
-#define WLAN_GPIO_PIN7_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN7_PAD_DRIVER_LSB) & WLAN_GPIO_PIN7_PAD_DRIVER_MASK)
-#define WLAN_GPIO_PIN7_SOURCE_MSB 0
-#define WLAN_GPIO_PIN7_SOURCE_LSB 0
-#define WLAN_GPIO_PIN7_SOURCE_MASK 0x00000001
-#define WLAN_GPIO_PIN7_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN7_SOURCE_MASK) >> WLAN_GPIO_PIN7_SOURCE_LSB)
-#define WLAN_GPIO_PIN7_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN7_SOURCE_LSB) & WLAN_GPIO_PIN7_SOURCE_MASK)
-
-#define WLAN_GPIO_PIN8_ADDRESS 0x00000048
-#define WLAN_GPIO_PIN8_OFFSET 0x00000048
-#define WLAN_GPIO_PIN8_CONFIG_MSB 13
-#define WLAN_GPIO_PIN8_CONFIG_LSB 11
-#define WLAN_GPIO_PIN8_CONFIG_MASK 0x00003800
-#define WLAN_GPIO_PIN8_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN8_CONFIG_MASK) >> WLAN_GPIO_PIN8_CONFIG_LSB)
-#define WLAN_GPIO_PIN8_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN8_CONFIG_LSB) & WLAN_GPIO_PIN8_CONFIG_MASK)
-#define WLAN_GPIO_PIN8_WAKEUP_ENABLE_MSB 10
-#define WLAN_GPIO_PIN8_WAKEUP_ENABLE_LSB 10
-#define WLAN_GPIO_PIN8_WAKEUP_ENABLE_MASK 0x00000400
-#define WLAN_GPIO_PIN8_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN8_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN8_WAKEUP_ENABLE_LSB)
-#define WLAN_GPIO_PIN8_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN8_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN8_WAKEUP_ENABLE_MASK)
-#define WLAN_GPIO_PIN8_INT_TYPE_MSB 9
-#define WLAN_GPIO_PIN8_INT_TYPE_LSB 7
-#define WLAN_GPIO_PIN8_INT_TYPE_MASK 0x00000380
-#define WLAN_GPIO_PIN8_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN8_INT_TYPE_MASK) >> WLAN_GPIO_PIN8_INT_TYPE_LSB)
-#define WLAN_GPIO_PIN8_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN8_INT_TYPE_LSB) & WLAN_GPIO_PIN8_INT_TYPE_MASK)
-#define WLAN_GPIO_PIN8_PAD_PULL_MSB 6
-#define WLAN_GPIO_PIN8_PAD_PULL_LSB 5
-#define WLAN_GPIO_PIN8_PAD_PULL_MASK 0x00000060
-#define WLAN_GPIO_PIN8_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN8_PAD_PULL_MASK) >> WLAN_GPIO_PIN8_PAD_PULL_LSB)
-#define WLAN_GPIO_PIN8_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN8_PAD_PULL_LSB) & WLAN_GPIO_PIN8_PAD_PULL_MASK)
-#define WLAN_GPIO_PIN8_PAD_STRENGTH_MSB 4
-#define WLAN_GPIO_PIN8_PAD_STRENGTH_LSB 3
-#define WLAN_GPIO_PIN8_PAD_STRENGTH_MASK 0x00000018
-#define WLAN_GPIO_PIN8_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN8_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN8_PAD_STRENGTH_LSB)
-#define WLAN_GPIO_PIN8_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN8_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN8_PAD_STRENGTH_MASK)
-#define WLAN_GPIO_PIN8_PAD_DRIVER_MSB 2
-#define WLAN_GPIO_PIN8_PAD_DRIVER_LSB 2
-#define WLAN_GPIO_PIN8_PAD_DRIVER_MASK 0x00000004
-#define WLAN_GPIO_PIN8_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN8_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN8_PAD_DRIVER_LSB)
-#define WLAN_GPIO_PIN8_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN8_PAD_DRIVER_LSB) & WLAN_GPIO_PIN8_PAD_DRIVER_MASK)
-#define WLAN_GPIO_PIN8_SOURCE_MSB 0
-#define WLAN_GPIO_PIN8_SOURCE_LSB 0
-#define WLAN_GPIO_PIN8_SOURCE_MASK 0x00000001
-#define WLAN_GPIO_PIN8_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN8_SOURCE_MASK) >> WLAN_GPIO_PIN8_SOURCE_LSB)
-#define WLAN_GPIO_PIN8_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN8_SOURCE_LSB) & WLAN_GPIO_PIN8_SOURCE_MASK)
-
-#define WLAN_GPIO_PIN9_ADDRESS 0x0000004c
-#define WLAN_GPIO_PIN9_OFFSET 0x0000004c
-#define WLAN_GPIO_PIN9_CONFIG_MSB 13
-#define WLAN_GPIO_PIN9_CONFIG_LSB 11
-#define WLAN_GPIO_PIN9_CONFIG_MASK 0x00003800
-#define WLAN_GPIO_PIN9_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN9_CONFIG_MASK) >> WLAN_GPIO_PIN9_CONFIG_LSB)
-#define WLAN_GPIO_PIN9_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN9_CONFIG_LSB) & WLAN_GPIO_PIN9_CONFIG_MASK)
-#define WLAN_GPIO_PIN9_WAKEUP_ENABLE_MSB 10
-#define WLAN_GPIO_PIN9_WAKEUP_ENABLE_LSB 10
-#define WLAN_GPIO_PIN9_WAKEUP_ENABLE_MASK 0x00000400
-#define WLAN_GPIO_PIN9_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN9_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN9_WAKEUP_ENABLE_LSB)
-#define WLAN_GPIO_PIN9_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN9_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN9_WAKEUP_ENABLE_MASK)
-#define WLAN_GPIO_PIN9_INT_TYPE_MSB 9
-#define WLAN_GPIO_PIN9_INT_TYPE_LSB 7
-#define WLAN_GPIO_PIN9_INT_TYPE_MASK 0x00000380
-#define WLAN_GPIO_PIN9_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN9_INT_TYPE_MASK) >> WLAN_GPIO_PIN9_INT_TYPE_LSB)
-#define WLAN_GPIO_PIN9_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN9_INT_TYPE_LSB) & WLAN_GPIO_PIN9_INT_TYPE_MASK)
-#define WLAN_GPIO_PIN9_PAD_PULL_MSB 6
-#define WLAN_GPIO_PIN9_PAD_PULL_LSB 5
-#define WLAN_GPIO_PIN9_PAD_PULL_MASK 0x00000060
-#define WLAN_GPIO_PIN9_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN9_PAD_PULL_MASK) >> WLAN_GPIO_PIN9_PAD_PULL_LSB)
-#define WLAN_GPIO_PIN9_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN9_PAD_PULL_LSB) & WLAN_GPIO_PIN9_PAD_PULL_MASK)
-#define WLAN_GPIO_PIN9_PAD_STRENGTH_MSB 4
-#define WLAN_GPIO_PIN9_PAD_STRENGTH_LSB 3
-#define WLAN_GPIO_PIN9_PAD_STRENGTH_MASK 0x00000018
-#define WLAN_GPIO_PIN9_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN9_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN9_PAD_STRENGTH_LSB)
-#define WLAN_GPIO_PIN9_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN9_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN9_PAD_STRENGTH_MASK)
-#define WLAN_GPIO_PIN9_PAD_DRIVER_MSB 2
-#define WLAN_GPIO_PIN9_PAD_DRIVER_LSB 2
-#define WLAN_GPIO_PIN9_PAD_DRIVER_MASK 0x00000004
-#define WLAN_GPIO_PIN9_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN9_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN9_PAD_DRIVER_LSB)
-#define WLAN_GPIO_PIN9_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN9_PAD_DRIVER_LSB) & WLAN_GPIO_PIN9_PAD_DRIVER_MASK)
-#define WLAN_GPIO_PIN9_SOURCE_MSB 0
-#define WLAN_GPIO_PIN9_SOURCE_LSB 0
-#define WLAN_GPIO_PIN9_SOURCE_MASK 0x00000001
-#define WLAN_GPIO_PIN9_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN9_SOURCE_MASK) >> WLAN_GPIO_PIN9_SOURCE_LSB)
-#define WLAN_GPIO_PIN9_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN9_SOURCE_LSB) & WLAN_GPIO_PIN9_SOURCE_MASK)
-
-#define WLAN_GPIO_PIN10_ADDRESS 0x00000050
-#define WLAN_GPIO_PIN10_OFFSET 0x00000050
-#define WLAN_GPIO_PIN10_CONFIG_MSB 13
-#define WLAN_GPIO_PIN10_CONFIG_LSB 11
-#define WLAN_GPIO_PIN10_CONFIG_MASK 0x00003800
-#define WLAN_GPIO_PIN10_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN10_CONFIG_MASK) >> WLAN_GPIO_PIN10_CONFIG_LSB)
-#define WLAN_GPIO_PIN10_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN10_CONFIG_LSB) & WLAN_GPIO_PIN10_CONFIG_MASK)
-#define WLAN_GPIO_PIN10_WAKEUP_ENABLE_MSB 10
-#define WLAN_GPIO_PIN10_WAKEUP_ENABLE_LSB 10
-#define WLAN_GPIO_PIN10_WAKEUP_ENABLE_MASK 0x00000400
-#define WLAN_GPIO_PIN10_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN10_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN10_WAKEUP_ENABLE_LSB)
-#define WLAN_GPIO_PIN10_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN10_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN10_WAKEUP_ENABLE_MASK)
-#define WLAN_GPIO_PIN10_INT_TYPE_MSB 9
-#define WLAN_GPIO_PIN10_INT_TYPE_LSB 7
-#define WLAN_GPIO_PIN10_INT_TYPE_MASK 0x00000380
-#define WLAN_GPIO_PIN10_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN10_INT_TYPE_MASK) >> WLAN_GPIO_PIN10_INT_TYPE_LSB)
-#define WLAN_GPIO_PIN10_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN10_INT_TYPE_LSB) & WLAN_GPIO_PIN10_INT_TYPE_MASK)
-#define WLAN_GPIO_PIN10_PAD_PULL_MSB 6
-#define WLAN_GPIO_PIN10_PAD_PULL_LSB 5
-#define WLAN_GPIO_PIN10_PAD_PULL_MASK 0x00000060
-#define WLAN_GPIO_PIN10_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN10_PAD_PULL_MASK) >> WLAN_GPIO_PIN10_PAD_PULL_LSB)
-#define WLAN_GPIO_PIN10_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN10_PAD_PULL_LSB) & WLAN_GPIO_PIN10_PAD_PULL_MASK)
-#define WLAN_GPIO_PIN10_PAD_STRENGTH_MSB 4
-#define WLAN_GPIO_PIN10_PAD_STRENGTH_LSB 3
-#define WLAN_GPIO_PIN10_PAD_STRENGTH_MASK 0x00000018
-#define WLAN_GPIO_PIN10_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN10_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN10_PAD_STRENGTH_LSB)
-#define WLAN_GPIO_PIN10_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN10_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN10_PAD_STRENGTH_MASK)
-#define WLAN_GPIO_PIN10_PAD_DRIVER_MSB 2
-#define WLAN_GPIO_PIN10_PAD_DRIVER_LSB 2
-#define WLAN_GPIO_PIN10_PAD_DRIVER_MASK 0x00000004
-#define WLAN_GPIO_PIN10_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN10_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN10_PAD_DRIVER_LSB)
-#define WLAN_GPIO_PIN10_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN10_PAD_DRIVER_LSB) & WLAN_GPIO_PIN10_PAD_DRIVER_MASK)
-#define WLAN_GPIO_PIN10_SOURCE_MSB 0
-#define WLAN_GPIO_PIN10_SOURCE_LSB 0
-#define WLAN_GPIO_PIN10_SOURCE_MASK 0x00000001
-#define WLAN_GPIO_PIN10_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN10_SOURCE_MASK) >> WLAN_GPIO_PIN10_SOURCE_LSB)
-#define WLAN_GPIO_PIN10_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN10_SOURCE_LSB) & WLAN_GPIO_PIN10_SOURCE_MASK)
-
-#define WLAN_GPIO_PIN11_ADDRESS 0x00000054
-#define WLAN_GPIO_PIN11_OFFSET 0x00000054
-#define WLAN_GPIO_PIN11_CONFIG_MSB 13
-#define WLAN_GPIO_PIN11_CONFIG_LSB 11
-#define WLAN_GPIO_PIN11_CONFIG_MASK 0x00003800
-#define WLAN_GPIO_PIN11_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN11_CONFIG_MASK) >> WLAN_GPIO_PIN11_CONFIG_LSB)
-#define WLAN_GPIO_PIN11_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN11_CONFIG_LSB) & WLAN_GPIO_PIN11_CONFIG_MASK)
-#define WLAN_GPIO_PIN11_WAKEUP_ENABLE_MSB 10
-#define WLAN_GPIO_PIN11_WAKEUP_ENABLE_LSB 10
-#define WLAN_GPIO_PIN11_WAKEUP_ENABLE_MASK 0x00000400
-#define WLAN_GPIO_PIN11_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN11_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN11_WAKEUP_ENABLE_LSB)
-#define WLAN_GPIO_PIN11_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN11_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN11_WAKEUP_ENABLE_MASK)
-#define WLAN_GPIO_PIN11_INT_TYPE_MSB 9
-#define WLAN_GPIO_PIN11_INT_TYPE_LSB 7
-#define WLAN_GPIO_PIN11_INT_TYPE_MASK 0x00000380
-#define WLAN_GPIO_PIN11_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN11_INT_TYPE_MASK) >> WLAN_GPIO_PIN11_INT_TYPE_LSB)
-#define WLAN_GPIO_PIN11_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN11_INT_TYPE_LSB) & WLAN_GPIO_PIN11_INT_TYPE_MASK)
-#define WLAN_GPIO_PIN11_PAD_PULL_MSB 6
-#define WLAN_GPIO_PIN11_PAD_PULL_LSB 5
-#define WLAN_GPIO_PIN11_PAD_PULL_MASK 0x00000060
-#define WLAN_GPIO_PIN11_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN11_PAD_PULL_MASK) >> WLAN_GPIO_PIN11_PAD_PULL_LSB)
-#define WLAN_GPIO_PIN11_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN11_PAD_PULL_LSB) & WLAN_GPIO_PIN11_PAD_PULL_MASK)
-#define WLAN_GPIO_PIN11_PAD_STRENGTH_MSB 4
-#define WLAN_GPIO_PIN11_PAD_STRENGTH_LSB 3
-#define WLAN_GPIO_PIN11_PAD_STRENGTH_MASK 0x00000018
-#define WLAN_GPIO_PIN11_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN11_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN11_PAD_STRENGTH_LSB)
-#define WLAN_GPIO_PIN11_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN11_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN11_PAD_STRENGTH_MASK)
-#define WLAN_GPIO_PIN11_PAD_DRIVER_MSB 2
-#define WLAN_GPIO_PIN11_PAD_DRIVER_LSB 2
-#define WLAN_GPIO_PIN11_PAD_DRIVER_MASK 0x00000004
-#define WLAN_GPIO_PIN11_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN11_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN11_PAD_DRIVER_LSB)
-#define WLAN_GPIO_PIN11_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN11_PAD_DRIVER_LSB) & WLAN_GPIO_PIN11_PAD_DRIVER_MASK)
-#define WLAN_GPIO_PIN11_SOURCE_MSB 0
-#define WLAN_GPIO_PIN11_SOURCE_LSB 0
-#define WLAN_GPIO_PIN11_SOURCE_MASK 0x00000001
-#define WLAN_GPIO_PIN11_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN11_SOURCE_MASK) >> WLAN_GPIO_PIN11_SOURCE_LSB)
-#define WLAN_GPIO_PIN11_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN11_SOURCE_LSB) & WLAN_GPIO_PIN11_SOURCE_MASK)
-
-#define WLAN_GPIO_PIN12_ADDRESS 0x00000058
-#define WLAN_GPIO_PIN12_OFFSET 0x00000058
-#define WLAN_GPIO_PIN12_CONFIG_MSB 13
-#define WLAN_GPIO_PIN12_CONFIG_LSB 11
-#define WLAN_GPIO_PIN12_CONFIG_MASK 0x00003800
-#define WLAN_GPIO_PIN12_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN12_CONFIG_MASK) >> WLAN_GPIO_PIN12_CONFIG_LSB)
-#define WLAN_GPIO_PIN12_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN12_CONFIG_LSB) & WLAN_GPIO_PIN12_CONFIG_MASK)
-#define WLAN_GPIO_PIN12_WAKEUP_ENABLE_MSB 10
-#define WLAN_GPIO_PIN12_WAKEUP_ENABLE_LSB 10
-#define WLAN_GPIO_PIN12_WAKEUP_ENABLE_MASK 0x00000400
-#define WLAN_GPIO_PIN12_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN12_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN12_WAKEUP_ENABLE_LSB)
-#define WLAN_GPIO_PIN12_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN12_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN12_WAKEUP_ENABLE_MASK)
-#define WLAN_GPIO_PIN12_INT_TYPE_MSB 9
-#define WLAN_GPIO_PIN12_INT_TYPE_LSB 7
-#define WLAN_GPIO_PIN12_INT_TYPE_MASK 0x00000380
-#define WLAN_GPIO_PIN12_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN12_INT_TYPE_MASK) >> WLAN_GPIO_PIN12_INT_TYPE_LSB)
-#define WLAN_GPIO_PIN12_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN12_INT_TYPE_LSB) & WLAN_GPIO_PIN12_INT_TYPE_MASK)
-#define WLAN_GPIO_PIN12_PAD_PULL_MSB 6
-#define WLAN_GPIO_PIN12_PAD_PULL_LSB 5
-#define WLAN_GPIO_PIN12_PAD_PULL_MASK 0x00000060
-#define WLAN_GPIO_PIN12_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN12_PAD_PULL_MASK) >> WLAN_GPIO_PIN12_PAD_PULL_LSB)
-#define WLAN_GPIO_PIN12_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN12_PAD_PULL_LSB) & WLAN_GPIO_PIN12_PAD_PULL_MASK)
-#define WLAN_GPIO_PIN12_PAD_STRENGTH_MSB 4
-#define WLAN_GPIO_PIN12_PAD_STRENGTH_LSB 3
-#define WLAN_GPIO_PIN12_PAD_STRENGTH_MASK 0x00000018
-#define WLAN_GPIO_PIN12_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN12_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN12_PAD_STRENGTH_LSB)
-#define WLAN_GPIO_PIN12_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN12_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN12_PAD_STRENGTH_MASK)
-#define WLAN_GPIO_PIN12_PAD_DRIVER_MSB 2
-#define WLAN_GPIO_PIN12_PAD_DRIVER_LSB 2
-#define WLAN_GPIO_PIN12_PAD_DRIVER_MASK 0x00000004
-#define WLAN_GPIO_PIN12_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN12_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN12_PAD_DRIVER_LSB)
-#define WLAN_GPIO_PIN12_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN12_PAD_DRIVER_LSB) & WLAN_GPIO_PIN12_PAD_DRIVER_MASK)
-#define WLAN_GPIO_PIN12_SOURCE_MSB 0
-#define WLAN_GPIO_PIN12_SOURCE_LSB 0
-#define WLAN_GPIO_PIN12_SOURCE_MASK 0x00000001
-#define WLAN_GPIO_PIN12_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN12_SOURCE_MASK) >> WLAN_GPIO_PIN12_SOURCE_LSB)
-#define WLAN_GPIO_PIN12_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN12_SOURCE_LSB) & WLAN_GPIO_PIN12_SOURCE_MASK)
-
-#define WLAN_GPIO_PIN13_ADDRESS 0x0000005c
-#define WLAN_GPIO_PIN13_OFFSET 0x0000005c
-#define WLAN_GPIO_PIN13_CONFIG_MSB 13
-#define WLAN_GPIO_PIN13_CONFIG_LSB 11
-#define WLAN_GPIO_PIN13_CONFIG_MASK 0x00003800
-#define WLAN_GPIO_PIN13_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN13_CONFIG_MASK) >> WLAN_GPIO_PIN13_CONFIG_LSB)
-#define WLAN_GPIO_PIN13_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN13_CONFIG_LSB) & WLAN_GPIO_PIN13_CONFIG_MASK)
-#define WLAN_GPIO_PIN13_WAKEUP_ENABLE_MSB 10
-#define WLAN_GPIO_PIN13_WAKEUP_ENABLE_LSB 10
-#define WLAN_GPIO_PIN13_WAKEUP_ENABLE_MASK 0x00000400
-#define WLAN_GPIO_PIN13_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN13_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN13_WAKEUP_ENABLE_LSB)
-#define WLAN_GPIO_PIN13_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN13_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN13_WAKEUP_ENABLE_MASK)
-#define WLAN_GPIO_PIN13_INT_TYPE_MSB 9
-#define WLAN_GPIO_PIN13_INT_TYPE_LSB 7
-#define WLAN_GPIO_PIN13_INT_TYPE_MASK 0x00000380
-#define WLAN_GPIO_PIN13_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN13_INT_TYPE_MASK) >> WLAN_GPIO_PIN13_INT_TYPE_LSB)
-#define WLAN_GPIO_PIN13_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN13_INT_TYPE_LSB) & WLAN_GPIO_PIN13_INT_TYPE_MASK)
-#define WLAN_GPIO_PIN13_PAD_PULL_MSB 6
-#define WLAN_GPIO_PIN13_PAD_PULL_LSB 5
-#define WLAN_GPIO_PIN13_PAD_PULL_MASK 0x00000060
-#define WLAN_GPIO_PIN13_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN13_PAD_PULL_MASK) >> WLAN_GPIO_PIN13_PAD_PULL_LSB)
-#define WLAN_GPIO_PIN13_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN13_PAD_PULL_LSB) & WLAN_GPIO_PIN13_PAD_PULL_MASK)
-#define WLAN_GPIO_PIN13_PAD_STRENGTH_MSB 4
-#define WLAN_GPIO_PIN13_PAD_STRENGTH_LSB 3
-#define WLAN_GPIO_PIN13_PAD_STRENGTH_MASK 0x00000018
-#define WLAN_GPIO_PIN13_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN13_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN13_PAD_STRENGTH_LSB)
-#define WLAN_GPIO_PIN13_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN13_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN13_PAD_STRENGTH_MASK)
-#define WLAN_GPIO_PIN13_PAD_DRIVER_MSB 2
-#define WLAN_GPIO_PIN13_PAD_DRIVER_LSB 2
-#define WLAN_GPIO_PIN13_PAD_DRIVER_MASK 0x00000004
-#define WLAN_GPIO_PIN13_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN13_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN13_PAD_DRIVER_LSB)
-#define WLAN_GPIO_PIN13_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN13_PAD_DRIVER_LSB) & WLAN_GPIO_PIN13_PAD_DRIVER_MASK)
-#define WLAN_GPIO_PIN13_SOURCE_MSB 0
-#define WLAN_GPIO_PIN13_SOURCE_LSB 0
-#define WLAN_GPIO_PIN13_SOURCE_MASK 0x00000001
-#define WLAN_GPIO_PIN13_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN13_SOURCE_MASK) >> WLAN_GPIO_PIN13_SOURCE_LSB)
-#define WLAN_GPIO_PIN13_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN13_SOURCE_LSB) & WLAN_GPIO_PIN13_SOURCE_MASK)
-
-#define WLAN_GPIO_PIN14_ADDRESS 0x00000060
-#define WLAN_GPIO_PIN14_OFFSET 0x00000060
-#define WLAN_GPIO_PIN14_CONFIG_MSB 13
-#define WLAN_GPIO_PIN14_CONFIG_LSB 11
-#define WLAN_GPIO_PIN14_CONFIG_MASK 0x00003800
-#define WLAN_GPIO_PIN14_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN14_CONFIG_MASK) >> WLAN_GPIO_PIN14_CONFIG_LSB)
-#define WLAN_GPIO_PIN14_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN14_CONFIG_LSB) & WLAN_GPIO_PIN14_CONFIG_MASK)
-#define WLAN_GPIO_PIN14_WAKEUP_ENABLE_MSB 10
-#define WLAN_GPIO_PIN14_WAKEUP_ENABLE_LSB 10
-#define WLAN_GPIO_PIN14_WAKEUP_ENABLE_MASK 0x00000400
-#define WLAN_GPIO_PIN14_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN14_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN14_WAKEUP_ENABLE_LSB)
-#define WLAN_GPIO_PIN14_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN14_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN14_WAKEUP_ENABLE_MASK)
-#define WLAN_GPIO_PIN14_INT_TYPE_MSB 9
-#define WLAN_GPIO_PIN14_INT_TYPE_LSB 7
-#define WLAN_GPIO_PIN14_INT_TYPE_MASK 0x00000380
-#define WLAN_GPIO_PIN14_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN14_INT_TYPE_MASK) >> WLAN_GPIO_PIN14_INT_TYPE_LSB)
-#define WLAN_GPIO_PIN14_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN14_INT_TYPE_LSB) & WLAN_GPIO_PIN14_INT_TYPE_MASK)
-#define WLAN_GPIO_PIN14_PAD_PULL_MSB 6
-#define WLAN_GPIO_PIN14_PAD_PULL_LSB 5
-#define WLAN_GPIO_PIN14_PAD_PULL_MASK 0x00000060
-#define WLAN_GPIO_PIN14_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN14_PAD_PULL_MASK) >> WLAN_GPIO_PIN14_PAD_PULL_LSB)
-#define WLAN_GPIO_PIN14_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN14_PAD_PULL_LSB) & WLAN_GPIO_PIN14_PAD_PULL_MASK)
-#define WLAN_GPIO_PIN14_PAD_STRENGTH_MSB 4
-#define WLAN_GPIO_PIN14_PAD_STRENGTH_LSB 3
-#define WLAN_GPIO_PIN14_PAD_STRENGTH_MASK 0x00000018
-#define WLAN_GPIO_PIN14_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN14_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN14_PAD_STRENGTH_LSB)
-#define WLAN_GPIO_PIN14_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN14_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN14_PAD_STRENGTH_MASK)
-#define WLAN_GPIO_PIN14_PAD_DRIVER_MSB 2
-#define WLAN_GPIO_PIN14_PAD_DRIVER_LSB 2
-#define WLAN_GPIO_PIN14_PAD_DRIVER_MASK 0x00000004
-#define WLAN_GPIO_PIN14_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN14_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN14_PAD_DRIVER_LSB)
-#define WLAN_GPIO_PIN14_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN14_PAD_DRIVER_LSB) & WLAN_GPIO_PIN14_PAD_DRIVER_MASK)
-#define WLAN_GPIO_PIN14_SOURCE_MSB 0
-#define WLAN_GPIO_PIN14_SOURCE_LSB 0
-#define WLAN_GPIO_PIN14_SOURCE_MASK 0x00000001
-#define WLAN_GPIO_PIN14_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN14_SOURCE_MASK) >> WLAN_GPIO_PIN14_SOURCE_LSB)
-#define WLAN_GPIO_PIN14_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN14_SOURCE_LSB) & WLAN_GPIO_PIN14_SOURCE_MASK)
-
-#define WLAN_GPIO_PIN15_ADDRESS 0x00000064
-#define WLAN_GPIO_PIN15_OFFSET 0x00000064
-#define WLAN_GPIO_PIN15_CONFIG_MSB 13
-#define WLAN_GPIO_PIN15_CONFIG_LSB 11
-#define WLAN_GPIO_PIN15_CONFIG_MASK 0x00003800
-#define WLAN_GPIO_PIN15_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN15_CONFIG_MASK) >> WLAN_GPIO_PIN15_CONFIG_LSB)
-#define WLAN_GPIO_PIN15_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN15_CONFIG_LSB) & WLAN_GPIO_PIN15_CONFIG_MASK)
-#define WLAN_GPIO_PIN15_WAKEUP_ENABLE_MSB 10
-#define WLAN_GPIO_PIN15_WAKEUP_ENABLE_LSB 10
-#define WLAN_GPIO_PIN15_WAKEUP_ENABLE_MASK 0x00000400
-#define WLAN_GPIO_PIN15_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN15_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN15_WAKEUP_ENABLE_LSB)
-#define WLAN_GPIO_PIN15_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN15_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN15_WAKEUP_ENABLE_MASK)
-#define WLAN_GPIO_PIN15_INT_TYPE_MSB 9
-#define WLAN_GPIO_PIN15_INT_TYPE_LSB 7
-#define WLAN_GPIO_PIN15_INT_TYPE_MASK 0x00000380
-#define WLAN_GPIO_PIN15_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN15_INT_TYPE_MASK) >> WLAN_GPIO_PIN15_INT_TYPE_LSB)
-#define WLAN_GPIO_PIN15_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN15_INT_TYPE_LSB) & WLAN_GPIO_PIN15_INT_TYPE_MASK)
-#define WLAN_GPIO_PIN15_PAD_PULL_MSB 6
-#define WLAN_GPIO_PIN15_PAD_PULL_LSB 5
-#define WLAN_GPIO_PIN15_PAD_PULL_MASK 0x00000060
-#define WLAN_GPIO_PIN15_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN15_PAD_PULL_MASK) >> WLAN_GPIO_PIN15_PAD_PULL_LSB)
-#define WLAN_GPIO_PIN15_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN15_PAD_PULL_LSB) & WLAN_GPIO_PIN15_PAD_PULL_MASK)
-#define WLAN_GPIO_PIN15_PAD_STRENGTH_MSB 4
-#define WLAN_GPIO_PIN15_PAD_STRENGTH_LSB 3
-#define WLAN_GPIO_PIN15_PAD_STRENGTH_MASK 0x00000018
-#define WLAN_GPIO_PIN15_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN15_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN15_PAD_STRENGTH_LSB)
-#define WLAN_GPIO_PIN15_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN15_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN15_PAD_STRENGTH_MASK)
-#define WLAN_GPIO_PIN15_PAD_DRIVER_MSB 2
-#define WLAN_GPIO_PIN15_PAD_DRIVER_LSB 2
-#define WLAN_GPIO_PIN15_PAD_DRIVER_MASK 0x00000004
-#define WLAN_GPIO_PIN15_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN15_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN15_PAD_DRIVER_LSB)
-#define WLAN_GPIO_PIN15_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN15_PAD_DRIVER_LSB) & WLAN_GPIO_PIN15_PAD_DRIVER_MASK)
-#define WLAN_GPIO_PIN15_SOURCE_MSB 0
-#define WLAN_GPIO_PIN15_SOURCE_LSB 0
-#define WLAN_GPIO_PIN15_SOURCE_MASK 0x00000001
-#define WLAN_GPIO_PIN15_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN15_SOURCE_MASK) >> WLAN_GPIO_PIN15_SOURCE_LSB)
-#define WLAN_GPIO_PIN15_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN15_SOURCE_LSB) & WLAN_GPIO_PIN15_SOURCE_MASK)
-
-#define WLAN_GPIO_PIN16_ADDRESS 0x00000068
-#define WLAN_GPIO_PIN16_OFFSET 0x00000068
-#define WLAN_GPIO_PIN16_CONFIG_MSB 13
-#define WLAN_GPIO_PIN16_CONFIG_LSB 11
-#define WLAN_GPIO_PIN16_CONFIG_MASK 0x00003800
-#define WLAN_GPIO_PIN16_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN16_CONFIG_MASK) >> WLAN_GPIO_PIN16_CONFIG_LSB)
-#define WLAN_GPIO_PIN16_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN16_CONFIG_LSB) & WLAN_GPIO_PIN16_CONFIG_MASK)
-#define WLAN_GPIO_PIN16_WAKEUP_ENABLE_MSB 10
-#define WLAN_GPIO_PIN16_WAKEUP_ENABLE_LSB 10
-#define WLAN_GPIO_PIN16_WAKEUP_ENABLE_MASK 0x00000400
-#define WLAN_GPIO_PIN16_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN16_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN16_WAKEUP_ENABLE_LSB)
-#define WLAN_GPIO_PIN16_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN16_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN16_WAKEUP_ENABLE_MASK)
-#define WLAN_GPIO_PIN16_INT_TYPE_MSB 9
-#define WLAN_GPIO_PIN16_INT_TYPE_LSB 7
-#define WLAN_GPIO_PIN16_INT_TYPE_MASK 0x00000380
-#define WLAN_GPIO_PIN16_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN16_INT_TYPE_MASK) >> WLAN_GPIO_PIN16_INT_TYPE_LSB)
-#define WLAN_GPIO_PIN16_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN16_INT_TYPE_LSB) & WLAN_GPIO_PIN16_INT_TYPE_MASK)
-#define WLAN_GPIO_PIN16_PAD_PULL_MSB 6
-#define WLAN_GPIO_PIN16_PAD_PULL_LSB 5
-#define WLAN_GPIO_PIN16_PAD_PULL_MASK 0x00000060
-#define WLAN_GPIO_PIN16_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN16_PAD_PULL_MASK) >> WLAN_GPIO_PIN16_PAD_PULL_LSB)
-#define WLAN_GPIO_PIN16_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN16_PAD_PULL_LSB) & WLAN_GPIO_PIN16_PAD_PULL_MASK)
-#define WLAN_GPIO_PIN16_PAD_STRENGTH_MSB 4
-#define WLAN_GPIO_PIN16_PAD_STRENGTH_LSB 3
-#define WLAN_GPIO_PIN16_PAD_STRENGTH_MASK 0x00000018
-#define WLAN_GPIO_PIN16_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN16_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN16_PAD_STRENGTH_LSB)
-#define WLAN_GPIO_PIN16_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN16_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN16_PAD_STRENGTH_MASK)
-#define WLAN_GPIO_PIN16_PAD_DRIVER_MSB 2
-#define WLAN_GPIO_PIN16_PAD_DRIVER_LSB 2
-#define WLAN_GPIO_PIN16_PAD_DRIVER_MASK 0x00000004
-#define WLAN_GPIO_PIN16_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN16_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN16_PAD_DRIVER_LSB)
-#define WLAN_GPIO_PIN16_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN16_PAD_DRIVER_LSB) & WLAN_GPIO_PIN16_PAD_DRIVER_MASK)
-#define WLAN_GPIO_PIN16_SOURCE_MSB 0
-#define WLAN_GPIO_PIN16_SOURCE_LSB 0
-#define WLAN_GPIO_PIN16_SOURCE_MASK 0x00000001
-#define WLAN_GPIO_PIN16_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN16_SOURCE_MASK) >> WLAN_GPIO_PIN16_SOURCE_LSB)
-#define WLAN_GPIO_PIN16_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN16_SOURCE_LSB) & WLAN_GPIO_PIN16_SOURCE_MASK)
-
-#define WLAN_GPIO_PIN17_ADDRESS 0x0000006c
-#define WLAN_GPIO_PIN17_OFFSET 0x0000006c
-#define WLAN_GPIO_PIN17_CONFIG_MSB 13
-#define WLAN_GPIO_PIN17_CONFIG_LSB 11
-#define WLAN_GPIO_PIN17_CONFIG_MASK 0x00003800
-#define WLAN_GPIO_PIN17_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN17_CONFIG_MASK) >> WLAN_GPIO_PIN17_CONFIG_LSB)
-#define WLAN_GPIO_PIN17_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN17_CONFIG_LSB) & WLAN_GPIO_PIN17_CONFIG_MASK)
-#define WLAN_GPIO_PIN17_WAKEUP_ENABLE_MSB 10
-#define WLAN_GPIO_PIN17_WAKEUP_ENABLE_LSB 10
-#define WLAN_GPIO_PIN17_WAKEUP_ENABLE_MASK 0x00000400
-#define WLAN_GPIO_PIN17_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN17_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN17_WAKEUP_ENABLE_LSB)
-#define WLAN_GPIO_PIN17_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN17_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN17_WAKEUP_ENABLE_MASK)
-#define WLAN_GPIO_PIN17_INT_TYPE_MSB 9
-#define WLAN_GPIO_PIN17_INT_TYPE_LSB 7
-#define WLAN_GPIO_PIN17_INT_TYPE_MASK 0x00000380
-#define WLAN_GPIO_PIN17_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN17_INT_TYPE_MASK) >> WLAN_GPIO_PIN17_INT_TYPE_LSB)
-#define WLAN_GPIO_PIN17_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN17_INT_TYPE_LSB) & WLAN_GPIO_PIN17_INT_TYPE_MASK)
-#define WLAN_GPIO_PIN17_PAD_PULL_MSB 6
-#define WLAN_GPIO_PIN17_PAD_PULL_LSB 5
-#define WLAN_GPIO_PIN17_PAD_PULL_MASK 0x00000060
-#define WLAN_GPIO_PIN17_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN17_PAD_PULL_MASK) >> WLAN_GPIO_PIN17_PAD_PULL_LSB)
-#define WLAN_GPIO_PIN17_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN17_PAD_PULL_LSB) & WLAN_GPIO_PIN17_PAD_PULL_MASK)
-#define WLAN_GPIO_PIN17_PAD_STRENGTH_MSB 4
-#define WLAN_GPIO_PIN17_PAD_STRENGTH_LSB 3
-#define WLAN_GPIO_PIN17_PAD_STRENGTH_MASK 0x00000018
-#define WLAN_GPIO_PIN17_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN17_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN17_PAD_STRENGTH_LSB)
-#define WLAN_GPIO_PIN17_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN17_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN17_PAD_STRENGTH_MASK)
-#define WLAN_GPIO_PIN17_PAD_DRIVER_MSB 2
-#define WLAN_GPIO_PIN17_PAD_DRIVER_LSB 2
-#define WLAN_GPIO_PIN17_PAD_DRIVER_MASK 0x00000004
-#define WLAN_GPIO_PIN17_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN17_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN17_PAD_DRIVER_LSB)
-#define WLAN_GPIO_PIN17_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN17_PAD_DRIVER_LSB) & WLAN_GPIO_PIN17_PAD_DRIVER_MASK)
-#define WLAN_GPIO_PIN17_SOURCE_MSB 0
-#define WLAN_GPIO_PIN17_SOURCE_LSB 0
-#define WLAN_GPIO_PIN17_SOURCE_MASK 0x00000001
-#define WLAN_GPIO_PIN17_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN17_SOURCE_MASK) >> WLAN_GPIO_PIN17_SOURCE_LSB)
-#define WLAN_GPIO_PIN17_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN17_SOURCE_LSB) & WLAN_GPIO_PIN17_SOURCE_MASK)
-
-#define WLAN_GPIO_PIN18_ADDRESS 0x00000070
-#define WLAN_GPIO_PIN18_OFFSET 0x00000070
-#define WLAN_GPIO_PIN18_CONFIG_MSB 13
-#define WLAN_GPIO_PIN18_CONFIG_LSB 11
-#define WLAN_GPIO_PIN18_CONFIG_MASK 0x00003800
-#define WLAN_GPIO_PIN18_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN18_CONFIG_MASK) >> WLAN_GPIO_PIN18_CONFIG_LSB)
-#define WLAN_GPIO_PIN18_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN18_CONFIG_LSB) & WLAN_GPIO_PIN18_CONFIG_MASK)
-#define WLAN_GPIO_PIN18_WAKEUP_ENABLE_MSB 10
-#define WLAN_GPIO_PIN18_WAKEUP_ENABLE_LSB 10
-#define WLAN_GPIO_PIN18_WAKEUP_ENABLE_MASK 0x00000400
-#define WLAN_GPIO_PIN18_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN18_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN18_WAKEUP_ENABLE_LSB)
-#define WLAN_GPIO_PIN18_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN18_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN18_WAKEUP_ENABLE_MASK)
-#define WLAN_GPIO_PIN18_INT_TYPE_MSB 9
-#define WLAN_GPIO_PIN18_INT_TYPE_LSB 7
-#define WLAN_GPIO_PIN18_INT_TYPE_MASK 0x00000380
-#define WLAN_GPIO_PIN18_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN18_INT_TYPE_MASK) >> WLAN_GPIO_PIN18_INT_TYPE_LSB)
-#define WLAN_GPIO_PIN18_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN18_INT_TYPE_LSB) & WLAN_GPIO_PIN18_INT_TYPE_MASK)
-#define WLAN_GPIO_PIN18_PAD_PULL_MSB 6
-#define WLAN_GPIO_PIN18_PAD_PULL_LSB 5
-#define WLAN_GPIO_PIN18_PAD_PULL_MASK 0x00000060
-#define WLAN_GPIO_PIN18_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN18_PAD_PULL_MASK) >> WLAN_GPIO_PIN18_PAD_PULL_LSB)
-#define WLAN_GPIO_PIN18_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN18_PAD_PULL_LSB) & WLAN_GPIO_PIN18_PAD_PULL_MASK)
-#define WLAN_GPIO_PIN18_PAD_STRENGTH_MSB 4
-#define WLAN_GPIO_PIN18_PAD_STRENGTH_LSB 3
-#define WLAN_GPIO_PIN18_PAD_STRENGTH_MASK 0x00000018
-#define WLAN_GPIO_PIN18_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN18_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN18_PAD_STRENGTH_LSB)
-#define WLAN_GPIO_PIN18_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN18_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN18_PAD_STRENGTH_MASK)
-#define WLAN_GPIO_PIN18_PAD_DRIVER_MSB 2
-#define WLAN_GPIO_PIN18_PAD_DRIVER_LSB 2
-#define WLAN_GPIO_PIN18_PAD_DRIVER_MASK 0x00000004
-#define WLAN_GPIO_PIN18_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN18_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN18_PAD_DRIVER_LSB)
-#define WLAN_GPIO_PIN18_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN18_PAD_DRIVER_LSB) & WLAN_GPIO_PIN18_PAD_DRIVER_MASK)
-#define WLAN_GPIO_PIN18_SOURCE_MSB 0
-#define WLAN_GPIO_PIN18_SOURCE_LSB 0
-#define WLAN_GPIO_PIN18_SOURCE_MASK 0x00000001
-#define WLAN_GPIO_PIN18_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN18_SOURCE_MASK) >> WLAN_GPIO_PIN18_SOURCE_LSB)
-#define WLAN_GPIO_PIN18_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN18_SOURCE_LSB) & WLAN_GPIO_PIN18_SOURCE_MASK)
-
-#define WLAN_GPIO_PIN19_ADDRESS 0x00000074
-#define WLAN_GPIO_PIN19_OFFSET 0x00000074
-#define WLAN_GPIO_PIN19_CONFIG_MSB 13
-#define WLAN_GPIO_PIN19_CONFIG_LSB 11
-#define WLAN_GPIO_PIN19_CONFIG_MASK 0x00003800
-#define WLAN_GPIO_PIN19_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN19_CONFIG_MASK) >> WLAN_GPIO_PIN19_CONFIG_LSB)
-#define WLAN_GPIO_PIN19_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN19_CONFIG_LSB) & WLAN_GPIO_PIN19_CONFIG_MASK)
-#define WLAN_GPIO_PIN19_WAKEUP_ENABLE_MSB 10
-#define WLAN_GPIO_PIN19_WAKEUP_ENABLE_LSB 10
-#define WLAN_GPIO_PIN19_WAKEUP_ENABLE_MASK 0x00000400
-#define WLAN_GPIO_PIN19_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN19_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN19_WAKEUP_ENABLE_LSB)
-#define WLAN_GPIO_PIN19_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN19_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN19_WAKEUP_ENABLE_MASK)
-#define WLAN_GPIO_PIN19_INT_TYPE_MSB 9
-#define WLAN_GPIO_PIN19_INT_TYPE_LSB 7
-#define WLAN_GPIO_PIN19_INT_TYPE_MASK 0x00000380
-#define WLAN_GPIO_PIN19_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN19_INT_TYPE_MASK) >> WLAN_GPIO_PIN19_INT_TYPE_LSB)
-#define WLAN_GPIO_PIN19_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN19_INT_TYPE_LSB) & WLAN_GPIO_PIN19_INT_TYPE_MASK)
-#define WLAN_GPIO_PIN19_PAD_PULL_MSB 6
-#define WLAN_GPIO_PIN19_PAD_PULL_LSB 5
-#define WLAN_GPIO_PIN19_PAD_PULL_MASK 0x00000060
-#define WLAN_GPIO_PIN19_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN19_PAD_PULL_MASK) >> WLAN_GPIO_PIN19_PAD_PULL_LSB)
-#define WLAN_GPIO_PIN19_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN19_PAD_PULL_LSB) & WLAN_GPIO_PIN19_PAD_PULL_MASK)
-#define WLAN_GPIO_PIN19_PAD_STRENGTH_MSB 4
-#define WLAN_GPIO_PIN19_PAD_STRENGTH_LSB 3
-#define WLAN_GPIO_PIN19_PAD_STRENGTH_MASK 0x00000018
-#define WLAN_GPIO_PIN19_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN19_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN19_PAD_STRENGTH_LSB)
-#define WLAN_GPIO_PIN19_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN19_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN19_PAD_STRENGTH_MASK)
-#define WLAN_GPIO_PIN19_PAD_DRIVER_MSB 2
-#define WLAN_GPIO_PIN19_PAD_DRIVER_LSB 2
-#define WLAN_GPIO_PIN19_PAD_DRIVER_MASK 0x00000004
-#define WLAN_GPIO_PIN19_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN19_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN19_PAD_DRIVER_LSB)
-#define WLAN_GPIO_PIN19_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN19_PAD_DRIVER_LSB) & WLAN_GPIO_PIN19_PAD_DRIVER_MASK)
-#define WLAN_GPIO_PIN19_SOURCE_MSB 0
-#define WLAN_GPIO_PIN19_SOURCE_LSB 0
-#define WLAN_GPIO_PIN19_SOURCE_MASK 0x00000001
-#define WLAN_GPIO_PIN19_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN19_SOURCE_MASK) >> WLAN_GPIO_PIN19_SOURCE_LSB)
-#define WLAN_GPIO_PIN19_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN19_SOURCE_LSB) & WLAN_GPIO_PIN19_SOURCE_MASK)
-
-#define WLAN_GPIO_PIN20_ADDRESS 0x00000078
-#define WLAN_GPIO_PIN20_OFFSET 0x00000078
-#define WLAN_GPIO_PIN20_CONFIG_MSB 13
-#define WLAN_GPIO_PIN20_CONFIG_LSB 11
-#define WLAN_GPIO_PIN20_CONFIG_MASK 0x00003800
-#define WLAN_GPIO_PIN20_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN20_CONFIG_MASK) >> WLAN_GPIO_PIN20_CONFIG_LSB)
-#define WLAN_GPIO_PIN20_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN20_CONFIG_LSB) & WLAN_GPIO_PIN20_CONFIG_MASK)
-#define WLAN_GPIO_PIN20_WAKEUP_ENABLE_MSB 10
-#define WLAN_GPIO_PIN20_WAKEUP_ENABLE_LSB 10
-#define WLAN_GPIO_PIN20_WAKEUP_ENABLE_MASK 0x00000400
-#define WLAN_GPIO_PIN20_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN20_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN20_WAKEUP_ENABLE_LSB)
-#define WLAN_GPIO_PIN20_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN20_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN20_WAKEUP_ENABLE_MASK)
-#define WLAN_GPIO_PIN20_INT_TYPE_MSB 9
-#define WLAN_GPIO_PIN20_INT_TYPE_LSB 7
-#define WLAN_GPIO_PIN20_INT_TYPE_MASK 0x00000380
-#define WLAN_GPIO_PIN20_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN20_INT_TYPE_MASK) >> WLAN_GPIO_PIN20_INT_TYPE_LSB)
-#define WLAN_GPIO_PIN20_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN20_INT_TYPE_LSB) & WLAN_GPIO_PIN20_INT_TYPE_MASK)
-#define WLAN_GPIO_PIN20_PAD_PULL_MSB 6
-#define WLAN_GPIO_PIN20_PAD_PULL_LSB 5
-#define WLAN_GPIO_PIN20_PAD_PULL_MASK 0x00000060
-#define WLAN_GPIO_PIN20_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN20_PAD_PULL_MASK) >> WLAN_GPIO_PIN20_PAD_PULL_LSB)
-#define WLAN_GPIO_PIN20_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN20_PAD_PULL_LSB) & WLAN_GPIO_PIN20_PAD_PULL_MASK)
-#define WLAN_GPIO_PIN20_PAD_STRENGTH_MSB 4
-#define WLAN_GPIO_PIN20_PAD_STRENGTH_LSB 3
-#define WLAN_GPIO_PIN20_PAD_STRENGTH_MASK 0x00000018
-#define WLAN_GPIO_PIN20_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN20_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN20_PAD_STRENGTH_LSB)
-#define WLAN_GPIO_PIN20_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN20_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN20_PAD_STRENGTH_MASK)
-#define WLAN_GPIO_PIN20_PAD_DRIVER_MSB 2
-#define WLAN_GPIO_PIN20_PAD_DRIVER_LSB 2
-#define WLAN_GPIO_PIN20_PAD_DRIVER_MASK 0x00000004
-#define WLAN_GPIO_PIN20_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN20_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN20_PAD_DRIVER_LSB)
-#define WLAN_GPIO_PIN20_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN20_PAD_DRIVER_LSB) & WLAN_GPIO_PIN20_PAD_DRIVER_MASK)
-#define WLAN_GPIO_PIN20_SOURCE_MSB 0
-#define WLAN_GPIO_PIN20_SOURCE_LSB 0
-#define WLAN_GPIO_PIN20_SOURCE_MASK 0x00000001
-#define WLAN_GPIO_PIN20_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN20_SOURCE_MASK) >> WLAN_GPIO_PIN20_SOURCE_LSB)
-#define WLAN_GPIO_PIN20_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN20_SOURCE_LSB) & WLAN_GPIO_PIN20_SOURCE_MASK)
-
-#define WLAN_GPIO_PIN21_ADDRESS 0x0000007c
-#define WLAN_GPIO_PIN21_OFFSET 0x0000007c
-#define WLAN_GPIO_PIN21_CONFIG_MSB 13
-#define WLAN_GPIO_PIN21_CONFIG_LSB 11
-#define WLAN_GPIO_PIN21_CONFIG_MASK 0x00003800
-#define WLAN_GPIO_PIN21_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN21_CONFIG_MASK) >> WLAN_GPIO_PIN21_CONFIG_LSB)
-#define WLAN_GPIO_PIN21_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN21_CONFIG_LSB) & WLAN_GPIO_PIN21_CONFIG_MASK)
-#define WLAN_GPIO_PIN21_WAKEUP_ENABLE_MSB 10
-#define WLAN_GPIO_PIN21_WAKEUP_ENABLE_LSB 10
-#define WLAN_GPIO_PIN21_WAKEUP_ENABLE_MASK 0x00000400
-#define WLAN_GPIO_PIN21_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN21_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN21_WAKEUP_ENABLE_LSB)
-#define WLAN_GPIO_PIN21_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN21_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN21_WAKEUP_ENABLE_MASK)
-#define WLAN_GPIO_PIN21_INT_TYPE_MSB 9
-#define WLAN_GPIO_PIN21_INT_TYPE_LSB 7
-#define WLAN_GPIO_PIN21_INT_TYPE_MASK 0x00000380
-#define WLAN_GPIO_PIN21_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN21_INT_TYPE_MASK) >> WLAN_GPIO_PIN21_INT_TYPE_LSB)
-#define WLAN_GPIO_PIN21_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN21_INT_TYPE_LSB) & WLAN_GPIO_PIN21_INT_TYPE_MASK)
-#define WLAN_GPIO_PIN21_PAD_PULL_MSB 6
-#define WLAN_GPIO_PIN21_PAD_PULL_LSB 5
-#define WLAN_GPIO_PIN21_PAD_PULL_MASK 0x00000060
-#define WLAN_GPIO_PIN21_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN21_PAD_PULL_MASK) >> WLAN_GPIO_PIN21_PAD_PULL_LSB)
-#define WLAN_GPIO_PIN21_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN21_PAD_PULL_LSB) & WLAN_GPIO_PIN21_PAD_PULL_MASK)
-#define WLAN_GPIO_PIN21_PAD_STRENGTH_MSB 4
-#define WLAN_GPIO_PIN21_PAD_STRENGTH_LSB 3
-#define WLAN_GPIO_PIN21_PAD_STRENGTH_MASK 0x00000018
-#define WLAN_GPIO_PIN21_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN21_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN21_PAD_STRENGTH_LSB)
-#define WLAN_GPIO_PIN21_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN21_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN21_PAD_STRENGTH_MASK)
-#define WLAN_GPIO_PIN21_PAD_DRIVER_MSB 2
-#define WLAN_GPIO_PIN21_PAD_DRIVER_LSB 2
-#define WLAN_GPIO_PIN21_PAD_DRIVER_MASK 0x00000004
-#define WLAN_GPIO_PIN21_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN21_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN21_PAD_DRIVER_LSB)
-#define WLAN_GPIO_PIN21_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN21_PAD_DRIVER_LSB) & WLAN_GPIO_PIN21_PAD_DRIVER_MASK)
-#define WLAN_GPIO_PIN21_SOURCE_MSB 0
-#define WLAN_GPIO_PIN21_SOURCE_LSB 0
-#define WLAN_GPIO_PIN21_SOURCE_MASK 0x00000001
-#define WLAN_GPIO_PIN21_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN21_SOURCE_MASK) >> WLAN_GPIO_PIN21_SOURCE_LSB)
-#define WLAN_GPIO_PIN21_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN21_SOURCE_LSB) & WLAN_GPIO_PIN21_SOURCE_MASK)
-
-#define WLAN_GPIO_PIN22_ADDRESS 0x00000080
-#define WLAN_GPIO_PIN22_OFFSET 0x00000080
-#define WLAN_GPIO_PIN22_CONFIG_MSB 13
-#define WLAN_GPIO_PIN22_CONFIG_LSB 11
-#define WLAN_GPIO_PIN22_CONFIG_MASK 0x00003800
-#define WLAN_GPIO_PIN22_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN22_CONFIG_MASK) >> WLAN_GPIO_PIN22_CONFIG_LSB)
-#define WLAN_GPIO_PIN22_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN22_CONFIG_LSB) & WLAN_GPIO_PIN22_CONFIG_MASK)
-#define WLAN_GPIO_PIN22_WAKEUP_ENABLE_MSB 10
-#define WLAN_GPIO_PIN22_WAKEUP_ENABLE_LSB 10
-#define WLAN_GPIO_PIN22_WAKEUP_ENABLE_MASK 0x00000400
-#define WLAN_GPIO_PIN22_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN22_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN22_WAKEUP_ENABLE_LSB)
-#define WLAN_GPIO_PIN22_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN22_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN22_WAKEUP_ENABLE_MASK)
-#define WLAN_GPIO_PIN22_INT_TYPE_MSB 9
-#define WLAN_GPIO_PIN22_INT_TYPE_LSB 7
-#define WLAN_GPIO_PIN22_INT_TYPE_MASK 0x00000380
-#define WLAN_GPIO_PIN22_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN22_INT_TYPE_MASK) >> WLAN_GPIO_PIN22_INT_TYPE_LSB)
-#define WLAN_GPIO_PIN22_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN22_INT_TYPE_LSB) & WLAN_GPIO_PIN22_INT_TYPE_MASK)
-#define WLAN_GPIO_PIN22_PAD_PULL_MSB 6
-#define WLAN_GPIO_PIN22_PAD_PULL_LSB 5
-#define WLAN_GPIO_PIN22_PAD_PULL_MASK 0x00000060
-#define WLAN_GPIO_PIN22_PAD_PULL_GET(x) (((x) & WLAN_GPIO_PIN22_PAD_PULL_MASK) >> WLAN_GPIO_PIN22_PAD_PULL_LSB)
-#define WLAN_GPIO_PIN22_PAD_PULL_SET(x) (((x) << WLAN_GPIO_PIN22_PAD_PULL_LSB) & WLAN_GPIO_PIN22_PAD_PULL_MASK)
-#define WLAN_GPIO_PIN22_PAD_STRENGTH_MSB 4
-#define WLAN_GPIO_PIN22_PAD_STRENGTH_LSB 3
-#define WLAN_GPIO_PIN22_PAD_STRENGTH_MASK 0x00000018
-#define WLAN_GPIO_PIN22_PAD_STRENGTH_GET(x) (((x) & WLAN_GPIO_PIN22_PAD_STRENGTH_MASK) >> WLAN_GPIO_PIN22_PAD_STRENGTH_LSB)
-#define WLAN_GPIO_PIN22_PAD_STRENGTH_SET(x) (((x) << WLAN_GPIO_PIN22_PAD_STRENGTH_LSB) & WLAN_GPIO_PIN22_PAD_STRENGTH_MASK)
-#define WLAN_GPIO_PIN22_PAD_DRIVER_MSB 2
-#define WLAN_GPIO_PIN22_PAD_DRIVER_LSB 2
-#define WLAN_GPIO_PIN22_PAD_DRIVER_MASK 0x00000004
-#define WLAN_GPIO_PIN22_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN22_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN22_PAD_DRIVER_LSB)
-#define WLAN_GPIO_PIN22_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN22_PAD_DRIVER_LSB) & WLAN_GPIO_PIN22_PAD_DRIVER_MASK)
-#define WLAN_GPIO_PIN22_SOURCE_MSB 0
-#define WLAN_GPIO_PIN22_SOURCE_LSB 0
-#define WLAN_GPIO_PIN22_SOURCE_MASK 0x00000001
-#define WLAN_GPIO_PIN22_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN22_SOURCE_MASK) >> WLAN_GPIO_PIN22_SOURCE_LSB)
-#define WLAN_GPIO_PIN22_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN22_SOURCE_LSB) & WLAN_GPIO_PIN22_SOURCE_MASK)
-
-#define WLAN_GPIO_PIN23_ADDRESS 0x00000084
-#define WLAN_GPIO_PIN23_OFFSET 0x00000084
-#define WLAN_GPIO_PIN23_CONFIG_MSB 13
-#define WLAN_GPIO_PIN23_CONFIG_LSB 11
-#define WLAN_GPIO_PIN23_CONFIG_MASK 0x00003800
-#define WLAN_GPIO_PIN23_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN23_CONFIG_MASK) >> WLAN_GPIO_PIN23_CONFIG_LSB)
-#define WLAN_GPIO_PIN23_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN23_CONFIG_LSB) & WLAN_GPIO_PIN23_CONFIG_MASK)
-#define WLAN_GPIO_PIN23_WAKEUP_ENABLE_MSB 10
-#define WLAN_GPIO_PIN23_WAKEUP_ENABLE_LSB 10
-#define WLAN_GPIO_PIN23_WAKEUP_ENABLE_MASK 0x00000400
-#define WLAN_GPIO_PIN23_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN23_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN23_WAKEUP_ENABLE_LSB)
-#define WLAN_GPIO_PIN23_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN23_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN23_WAKEUP_ENABLE_MASK)
-#define WLAN_GPIO_PIN23_INT_TYPE_MSB 9
-#define WLAN_GPIO_PIN23_INT_TYPE_LSB 7
-#define WLAN_GPIO_PIN23_INT_TYPE_MASK 0x00000380
-#define WLAN_GPIO_PIN23_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN23_INT_TYPE_MASK) >> WLAN_GPIO_PIN23_INT_TYPE_LSB)
-#define WLAN_GPIO_PIN23_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN23_INT_TYPE_LSB) & WLAN_GPIO_PIN23_INT_TYPE_MASK)
-#define WLAN_GPIO_PIN23_PAD_DRIVER_MSB 2
-#define WLAN_GPIO_PIN23_PAD_DRIVER_LSB 2
-#define WLAN_GPIO_PIN23_PAD_DRIVER_MASK 0x00000004
-#define WLAN_GPIO_PIN23_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN23_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN23_PAD_DRIVER_LSB)
-#define WLAN_GPIO_PIN23_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN23_PAD_DRIVER_LSB) & WLAN_GPIO_PIN23_PAD_DRIVER_MASK)
-#define WLAN_GPIO_PIN23_SOURCE_MSB 0
-#define WLAN_GPIO_PIN23_SOURCE_LSB 0
-#define WLAN_GPIO_PIN23_SOURCE_MASK 0x00000001
-#define WLAN_GPIO_PIN23_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN23_SOURCE_MASK) >> WLAN_GPIO_PIN23_SOURCE_LSB)
-#define WLAN_GPIO_PIN23_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN23_SOURCE_LSB) & WLAN_GPIO_PIN23_SOURCE_MASK)
-
-#define WLAN_GPIO_PIN24_ADDRESS 0x00000088
-#define WLAN_GPIO_PIN24_OFFSET 0x00000088
-#define WLAN_GPIO_PIN24_CONFIG_MSB 13
-#define WLAN_GPIO_PIN24_CONFIG_LSB 11
-#define WLAN_GPIO_PIN24_CONFIG_MASK 0x00003800
-#define WLAN_GPIO_PIN24_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN24_CONFIG_MASK) >> WLAN_GPIO_PIN24_CONFIG_LSB)
-#define WLAN_GPIO_PIN24_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN24_CONFIG_LSB) & WLAN_GPIO_PIN24_CONFIG_MASK)
-#define WLAN_GPIO_PIN24_WAKEUP_ENABLE_MSB 10
-#define WLAN_GPIO_PIN24_WAKEUP_ENABLE_LSB 10
-#define WLAN_GPIO_PIN24_WAKEUP_ENABLE_MASK 0x00000400
-#define WLAN_GPIO_PIN24_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN24_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN24_WAKEUP_ENABLE_LSB)
-#define WLAN_GPIO_PIN24_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN24_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN24_WAKEUP_ENABLE_MASK)
-#define WLAN_GPIO_PIN24_INT_TYPE_MSB 9
-#define WLAN_GPIO_PIN24_INT_TYPE_LSB 7
-#define WLAN_GPIO_PIN24_INT_TYPE_MASK 0x00000380
-#define WLAN_GPIO_PIN24_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN24_INT_TYPE_MASK) >> WLAN_GPIO_PIN24_INT_TYPE_LSB)
-#define WLAN_GPIO_PIN24_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN24_INT_TYPE_LSB) & WLAN_GPIO_PIN24_INT_TYPE_MASK)
-#define WLAN_GPIO_PIN24_PAD_DRIVER_MSB 2
-#define WLAN_GPIO_PIN24_PAD_DRIVER_LSB 2
-#define WLAN_GPIO_PIN24_PAD_DRIVER_MASK 0x00000004
-#define WLAN_GPIO_PIN24_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN24_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN24_PAD_DRIVER_LSB)
-#define WLAN_GPIO_PIN24_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN24_PAD_DRIVER_LSB) & WLAN_GPIO_PIN24_PAD_DRIVER_MASK)
-#define WLAN_GPIO_PIN24_SOURCE_MSB 0
-#define WLAN_GPIO_PIN24_SOURCE_LSB 0
-#define WLAN_GPIO_PIN24_SOURCE_MASK 0x00000001
-#define WLAN_GPIO_PIN24_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN24_SOURCE_MASK) >> WLAN_GPIO_PIN24_SOURCE_LSB)
-#define WLAN_GPIO_PIN24_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN24_SOURCE_LSB) & WLAN_GPIO_PIN24_SOURCE_MASK)
-
-#define WLAN_GPIO_PIN25_ADDRESS 0x0000008c
-#define WLAN_GPIO_PIN25_OFFSET 0x0000008c
-#define WLAN_GPIO_PIN25_CONFIG_MSB 13
-#define WLAN_GPIO_PIN25_CONFIG_LSB 11
-#define WLAN_GPIO_PIN25_CONFIG_MASK 0x00003800
-#define WLAN_GPIO_PIN25_CONFIG_GET(x) (((x) & WLAN_GPIO_PIN25_CONFIG_MASK) >> WLAN_GPIO_PIN25_CONFIG_LSB)
-#define WLAN_GPIO_PIN25_CONFIG_SET(x) (((x) << WLAN_GPIO_PIN25_CONFIG_LSB) & WLAN_GPIO_PIN25_CONFIG_MASK)
-#define WLAN_GPIO_PIN25_WAKEUP_ENABLE_MSB 10
-#define WLAN_GPIO_PIN25_WAKEUP_ENABLE_LSB 10
-#define WLAN_GPIO_PIN25_WAKEUP_ENABLE_MASK 0x00000400
-#define WLAN_GPIO_PIN25_WAKEUP_ENABLE_GET(x) (((x) & WLAN_GPIO_PIN25_WAKEUP_ENABLE_MASK) >> WLAN_GPIO_PIN25_WAKEUP_ENABLE_LSB)
-#define WLAN_GPIO_PIN25_WAKEUP_ENABLE_SET(x) (((x) << WLAN_GPIO_PIN25_WAKEUP_ENABLE_LSB) & WLAN_GPIO_PIN25_WAKEUP_ENABLE_MASK)
-#define WLAN_GPIO_PIN25_INT_TYPE_MSB 9
-#define WLAN_GPIO_PIN25_INT_TYPE_LSB 7
-#define WLAN_GPIO_PIN25_INT_TYPE_MASK 0x00000380
-#define WLAN_GPIO_PIN25_INT_TYPE_GET(x) (((x) & WLAN_GPIO_PIN25_INT_TYPE_MASK) >> WLAN_GPIO_PIN25_INT_TYPE_LSB)
-#define WLAN_GPIO_PIN25_INT_TYPE_SET(x) (((x) << WLAN_GPIO_PIN25_INT_TYPE_LSB) & WLAN_GPIO_PIN25_INT_TYPE_MASK)
-#define WLAN_GPIO_PIN25_PAD_DRIVER_MSB 2
-#define WLAN_GPIO_PIN25_PAD_DRIVER_LSB 2
-#define WLAN_GPIO_PIN25_PAD_DRIVER_MASK 0x00000004
-#define WLAN_GPIO_PIN25_PAD_DRIVER_GET(x) (((x) & WLAN_GPIO_PIN25_PAD_DRIVER_MASK) >> WLAN_GPIO_PIN25_PAD_DRIVER_LSB)
-#define WLAN_GPIO_PIN25_PAD_DRIVER_SET(x) (((x) << WLAN_GPIO_PIN25_PAD_DRIVER_LSB) & WLAN_GPIO_PIN25_PAD_DRIVER_MASK)
-#define WLAN_GPIO_PIN25_SOURCE_MSB 0
-#define WLAN_GPIO_PIN25_SOURCE_LSB 0
-#define WLAN_GPIO_PIN25_SOURCE_MASK 0x00000001
-#define WLAN_GPIO_PIN25_SOURCE_GET(x) (((x) & WLAN_GPIO_PIN25_SOURCE_MASK) >> WLAN_GPIO_PIN25_SOURCE_LSB)
-#define WLAN_GPIO_PIN25_SOURCE_SET(x) (((x) << WLAN_GPIO_PIN25_SOURCE_LSB) & WLAN_GPIO_PIN25_SOURCE_MASK)
-
-#define SDIO_ADDRESS 0x00000090
-#define SDIO_OFFSET 0x00000090
-#define SDIO_PINS_EN_MSB 0
-#define SDIO_PINS_EN_LSB 0
-#define SDIO_PINS_EN_MASK 0x00000001
-#define SDIO_PINS_EN_GET(x) (((x) & SDIO_PINS_EN_MASK) >> SDIO_PINS_EN_LSB)
-#define SDIO_PINS_EN_SET(x) (((x) << SDIO_PINS_EN_LSB) & SDIO_PINS_EN_MASK)
-
-#define FUNC_BUS_ADDRESS 0x00000094
-#define FUNC_BUS_OFFSET 0x00000094
-#define FUNC_BUS_GPIO_MODE_MSB 22
-#define FUNC_BUS_GPIO_MODE_LSB 22
-#define FUNC_BUS_GPIO_MODE_MASK 0x00400000
-#define FUNC_BUS_GPIO_MODE_GET(x) (((x) & FUNC_BUS_GPIO_MODE_MASK) >> FUNC_BUS_GPIO_MODE_LSB)
-#define FUNC_BUS_GPIO_MODE_SET(x) (((x) << FUNC_BUS_GPIO_MODE_LSB) & FUNC_BUS_GPIO_MODE_MASK)
-#define FUNC_BUS_OE_L_MSB 21
-#define FUNC_BUS_OE_L_LSB 0
-#define FUNC_BUS_OE_L_MASK 0x003fffff
-#define FUNC_BUS_OE_L_GET(x) (((x) & FUNC_BUS_OE_L_MASK) >> FUNC_BUS_OE_L_LSB)
-#define FUNC_BUS_OE_L_SET(x) (((x) << FUNC_BUS_OE_L_LSB) & FUNC_BUS_OE_L_MASK)
-
-#define WL_SOC_APB_ADDRESS 0x00000098
-#define WL_SOC_APB_OFFSET 0x00000098
-#define WL_SOC_APB_TOGGLE_MSB 0
-#define WL_SOC_APB_TOGGLE_LSB 0
-#define WL_SOC_APB_TOGGLE_MASK 0x00000001
-#define WL_SOC_APB_TOGGLE_GET(x) (((x) & WL_SOC_APB_TOGGLE_MASK) >> WL_SOC_APB_TOGGLE_LSB)
-#define WL_SOC_APB_TOGGLE_SET(x) (((x) << WL_SOC_APB_TOGGLE_LSB) & WL_SOC_APB_TOGGLE_MASK)
-
-#define WLAN_SIGMA_DELTA_ADDRESS 0x0000009c
-#define WLAN_SIGMA_DELTA_OFFSET 0x0000009c
-#define WLAN_SIGMA_DELTA_ENABLE_MSB 16
-#define WLAN_SIGMA_DELTA_ENABLE_LSB 16
-#define WLAN_SIGMA_DELTA_ENABLE_MASK 0x00010000
-#define WLAN_SIGMA_DELTA_ENABLE_GET(x) (((x) & WLAN_SIGMA_DELTA_ENABLE_MASK) >> WLAN_SIGMA_DELTA_ENABLE_LSB)
-#define WLAN_SIGMA_DELTA_ENABLE_SET(x) (((x) << WLAN_SIGMA_DELTA_ENABLE_LSB) & WLAN_SIGMA_DELTA_ENABLE_MASK)
-#define WLAN_SIGMA_DELTA_PRESCALAR_MSB 15
-#define WLAN_SIGMA_DELTA_PRESCALAR_LSB 8
-#define WLAN_SIGMA_DELTA_PRESCALAR_MASK 0x0000ff00
-#define WLAN_SIGMA_DELTA_PRESCALAR_GET(x) (((x) & WLAN_SIGMA_DELTA_PRESCALAR_MASK) >> WLAN_SIGMA_DELTA_PRESCALAR_LSB)
-#define WLAN_SIGMA_DELTA_PRESCALAR_SET(x) (((x) << WLAN_SIGMA_DELTA_PRESCALAR_LSB) & WLAN_SIGMA_DELTA_PRESCALAR_MASK)
-#define WLAN_SIGMA_DELTA_TARGET_MSB 7
-#define WLAN_SIGMA_DELTA_TARGET_LSB 0
-#define WLAN_SIGMA_DELTA_TARGET_MASK 0x000000ff
-#define WLAN_SIGMA_DELTA_TARGET_GET(x) (((x) & WLAN_SIGMA_DELTA_TARGET_MASK) >> WLAN_SIGMA_DELTA_TARGET_LSB)
-#define WLAN_SIGMA_DELTA_TARGET_SET(x) (((x) << WLAN_SIGMA_DELTA_TARGET_LSB) & WLAN_SIGMA_DELTA_TARGET_MASK)
-
-#define WL_BOOTSTRAP_ADDRESS 0x000000a0
-#define WL_BOOTSTRAP_OFFSET 0x000000a0
-#define WL_BOOTSTRAP_STATUS_MSB 22
-#define WL_BOOTSTRAP_STATUS_LSB 0
-#define WL_BOOTSTRAP_STATUS_MASK 0x007fffff
-#define WL_BOOTSTRAP_STATUS_GET(x) (((x) & WL_BOOTSTRAP_STATUS_MASK) >> WL_BOOTSTRAP_STATUS_LSB)
-#define WL_BOOTSTRAP_STATUS_SET(x) (((x) << WL_BOOTSTRAP_STATUS_LSB) & WL_BOOTSTRAP_STATUS_MASK)
-
-#define CLOCK_GPIO_ADDRESS 0x000000a4
-#define CLOCK_GPIO_OFFSET 0x000000a4
-#define CLOCK_GPIO_CLK_REQ_OUT_EN_MSB 2
-#define CLOCK_GPIO_CLK_REQ_OUT_EN_LSB 2
-#define CLOCK_GPIO_CLK_REQ_OUT_EN_MASK 0x00000004
-#define CLOCK_GPIO_CLK_REQ_OUT_EN_GET(x) (((x) & CLOCK_GPIO_CLK_REQ_OUT_EN_MASK) >> CLOCK_GPIO_CLK_REQ_OUT_EN_LSB)
-#define CLOCK_GPIO_CLK_REQ_OUT_EN_SET(x) (((x) << CLOCK_GPIO_CLK_REQ_OUT_EN_LSB) & CLOCK_GPIO_CLK_REQ_OUT_EN_MASK)
-#define CLOCK_GPIO_BT_CLK_REQ_EN_MSB 1
-#define CLOCK_GPIO_BT_CLK_REQ_EN_LSB 1
-#define CLOCK_GPIO_BT_CLK_REQ_EN_MASK 0x00000002
-#define CLOCK_GPIO_BT_CLK_REQ_EN_GET(x) (((x) & CLOCK_GPIO_BT_CLK_REQ_EN_MASK) >> CLOCK_GPIO_BT_CLK_REQ_EN_LSB)
-#define CLOCK_GPIO_BT_CLK_REQ_EN_SET(x) (((x) << CLOCK_GPIO_BT_CLK_REQ_EN_LSB) & CLOCK_GPIO_BT_CLK_REQ_EN_MASK)
-#define CLOCK_GPIO_BT_CLK_OUT_EN_MSB 0
-#define CLOCK_GPIO_BT_CLK_OUT_EN_LSB 0
-#define CLOCK_GPIO_BT_CLK_OUT_EN_MASK 0x00000001
-#define CLOCK_GPIO_BT_CLK_OUT_EN_GET(x) (((x) & CLOCK_GPIO_BT_CLK_OUT_EN_MASK) >> CLOCK_GPIO_BT_CLK_OUT_EN_LSB)
-#define CLOCK_GPIO_BT_CLK_OUT_EN_SET(x) (((x) << CLOCK_GPIO_BT_CLK_OUT_EN_LSB) & CLOCK_GPIO_BT_CLK_OUT_EN_MASK)
-
-#define WLAN_DEBUG_CONTROL_ADDRESS 0x000000a8
-#define WLAN_DEBUG_CONTROL_OFFSET 0x000000a8
-#define WLAN_DEBUG_CONTROL_ENABLE_MSB 0
-#define WLAN_DEBUG_CONTROL_ENABLE_LSB 0
-#define WLAN_DEBUG_CONTROL_ENABLE_MASK 0x00000001
-#define WLAN_DEBUG_CONTROL_ENABLE_GET(x) (((x) & WLAN_DEBUG_CONTROL_ENABLE_MASK) >> WLAN_DEBUG_CONTROL_ENABLE_LSB)
-#define WLAN_DEBUG_CONTROL_ENABLE_SET(x) (((x) << WLAN_DEBUG_CONTROL_ENABLE_LSB) & WLAN_DEBUG_CONTROL_ENABLE_MASK)
-
-#define WLAN_DEBUG_INPUT_SEL_ADDRESS 0x000000ac
-#define WLAN_DEBUG_INPUT_SEL_OFFSET 0x000000ac
-#define WLAN_DEBUG_INPUT_SEL_SHIFT_MSB 5
-#define WLAN_DEBUG_INPUT_SEL_SHIFT_LSB 4
-#define WLAN_DEBUG_INPUT_SEL_SHIFT_MASK 0x00000030
-#define WLAN_DEBUG_INPUT_SEL_SHIFT_GET(x) (((x) & WLAN_DEBUG_INPUT_SEL_SHIFT_MASK) >> WLAN_DEBUG_INPUT_SEL_SHIFT_LSB)
-#define WLAN_DEBUG_INPUT_SEL_SHIFT_SET(x) (((x) << WLAN_DEBUG_INPUT_SEL_SHIFT_LSB) & WLAN_DEBUG_INPUT_SEL_SHIFT_MASK)
-#define WLAN_DEBUG_INPUT_SEL_SRC_MSB 3
-#define WLAN_DEBUG_INPUT_SEL_SRC_LSB 0
-#define WLAN_DEBUG_INPUT_SEL_SRC_MASK 0x0000000f
-#define WLAN_DEBUG_INPUT_SEL_SRC_GET(x) (((x) & WLAN_DEBUG_INPUT_SEL_SRC_MASK) >> WLAN_DEBUG_INPUT_SEL_SRC_LSB)
-#define WLAN_DEBUG_INPUT_SEL_SRC_SET(x) (((x) << WLAN_DEBUG_INPUT_SEL_SRC_LSB) & WLAN_DEBUG_INPUT_SEL_SRC_MASK)
-
-#define WLAN_DEBUG_OUT_ADDRESS 0x000000b0
-#define WLAN_DEBUG_OUT_OFFSET 0x000000b0
-#define WLAN_DEBUG_OUT_DATA_MSB 17
-#define WLAN_DEBUG_OUT_DATA_LSB 0
-#define WLAN_DEBUG_OUT_DATA_MASK 0x0003ffff
-#define WLAN_DEBUG_OUT_DATA_GET(x) (((x) & WLAN_DEBUG_OUT_DATA_MASK) >> WLAN_DEBUG_OUT_DATA_LSB)
-#define WLAN_DEBUG_OUT_DATA_SET(x) (((x) << WLAN_DEBUG_OUT_DATA_LSB) & WLAN_DEBUG_OUT_DATA_MASK)
-
-#define WLAN_RESET_TUPLE_STATUS_ADDRESS 0x000000b4
-#define WLAN_RESET_TUPLE_STATUS_OFFSET 0x000000b4
-#define WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MSB 11
-#define WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB 8
-#define WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK 0x00000f00
-#define WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_GET(x) (((x) & WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK) >> WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB)
-#define WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_SET(x) (((x) << WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB) & WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK)
-#define WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MSB 7
-#define WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB 0
-#define WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK 0x000000ff
-#define WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_GET(x) (((x) & WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK) >> WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB)
-#define WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_SET(x) (((x) << WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB) & WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK)
-
-#define ANTENNA_SLEEP_CONTROL_ADDRESS 0x000000b8
-#define ANTENNA_SLEEP_CONTROL_OFFSET 0x000000b8
-#define ANTENNA_SLEEP_CONTROL_OVERRIDE_MSB 14
-#define ANTENNA_SLEEP_CONTROL_OVERRIDE_LSB 10
-#define ANTENNA_SLEEP_CONTROL_OVERRIDE_MASK 0x00007c00
-#define ANTENNA_SLEEP_CONTROL_OVERRIDE_GET(x) (((x) & ANTENNA_SLEEP_CONTROL_OVERRIDE_MASK) >> ANTENNA_SLEEP_CONTROL_OVERRIDE_LSB)
-#define ANTENNA_SLEEP_CONTROL_OVERRIDE_SET(x) (((x) << ANTENNA_SLEEP_CONTROL_OVERRIDE_LSB) & ANTENNA_SLEEP_CONTROL_OVERRIDE_MASK)
-#define ANTENNA_SLEEP_CONTROL_VALUE_MSB 9
-#define ANTENNA_SLEEP_CONTROL_VALUE_LSB 5
-#define ANTENNA_SLEEP_CONTROL_VALUE_MASK 0x000003e0
-#define ANTENNA_SLEEP_CONTROL_VALUE_GET(x) (((x) & ANTENNA_SLEEP_CONTROL_VALUE_MASK) >> ANTENNA_SLEEP_CONTROL_VALUE_LSB)
-#define ANTENNA_SLEEP_CONTROL_VALUE_SET(x) (((x) << ANTENNA_SLEEP_CONTROL_VALUE_LSB) & ANTENNA_SLEEP_CONTROL_VALUE_MASK)
-#define ANTENNA_SLEEP_CONTROL_ENABLE_MSB 4
-#define ANTENNA_SLEEP_CONTROL_ENABLE_LSB 0
-#define ANTENNA_SLEEP_CONTROL_ENABLE_MASK 0x0000001f
-#define ANTENNA_SLEEP_CONTROL_ENABLE_GET(x) (((x) & ANTENNA_SLEEP_CONTROL_ENABLE_MASK) >> ANTENNA_SLEEP_CONTROL_ENABLE_LSB)
-#define ANTENNA_SLEEP_CONTROL_ENABLE_SET(x) (((x) << ANTENNA_SLEEP_CONTROL_ENABLE_LSB) & ANTENNA_SLEEP_CONTROL_ENABLE_MASK)
-
-
-#ifndef __ASSEMBLER__
-
-typedef struct gpio_athr_wlan_reg_reg_s {
- volatile unsigned int wlan_gpio_out;
- volatile unsigned int wlan_gpio_out_w1ts;
- volatile unsigned int wlan_gpio_out_w1tc;
- volatile unsigned int wlan_gpio_enable;
- volatile unsigned int wlan_gpio_enable_w1ts;
- volatile unsigned int wlan_gpio_enable_w1tc;
- volatile unsigned int wlan_gpio_in;
- volatile unsigned int wlan_gpio_status;
- volatile unsigned int wlan_gpio_status_w1ts;
- volatile unsigned int wlan_gpio_status_w1tc;
- volatile unsigned int wlan_gpio_pin0;
- volatile unsigned int wlan_gpio_pin1;
- volatile unsigned int wlan_gpio_pin2;
- volatile unsigned int wlan_gpio_pin3;
- volatile unsigned int wlan_gpio_pin4;
- volatile unsigned int wlan_gpio_pin5;
- volatile unsigned int wlan_gpio_pin6;
- volatile unsigned int wlan_gpio_pin7;
- volatile unsigned int wlan_gpio_pin8;
- volatile unsigned int wlan_gpio_pin9;
- volatile unsigned int wlan_gpio_pin10;
- volatile unsigned int wlan_gpio_pin11;
- volatile unsigned int wlan_gpio_pin12;
- volatile unsigned int wlan_gpio_pin13;
- volatile unsigned int wlan_gpio_pin14;
- volatile unsigned int wlan_gpio_pin15;
- volatile unsigned int wlan_gpio_pin16;
- volatile unsigned int wlan_gpio_pin17;
- volatile unsigned int wlan_gpio_pin18;
- volatile unsigned int wlan_gpio_pin19;
- volatile unsigned int wlan_gpio_pin20;
- volatile unsigned int wlan_gpio_pin21;
- volatile unsigned int wlan_gpio_pin22;
- volatile unsigned int wlan_gpio_pin23;
- volatile unsigned int wlan_gpio_pin24;
- volatile unsigned int wlan_gpio_pin25;
- volatile unsigned int sdio;
- volatile unsigned int func_bus;
- volatile unsigned int wl_soc_apb;
- volatile unsigned int wlan_sigma_delta;
- volatile unsigned int wl_bootstrap;
- volatile unsigned int clock_gpio;
- volatile unsigned int wlan_debug_control;
- volatile unsigned int wlan_debug_input_sel;
- volatile unsigned int wlan_debug_out;
- volatile unsigned int wlan_reset_tuple_status;
- volatile unsigned int antenna_sleep_control;
-} gpio_athr_wlan_reg_reg_t;
-
-#endif /* __ASSEMBLER__ */
-
-#endif /* _GPIO_ATHR_WLAN_REG_H_ */
diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/gpio_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/gpio_reg.h
deleted file mode 100644
index b3e7126..0000000
--- a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/gpio_reg.h
+++ /dev/null
@@ -1,1094 +0,0 @@
-// ------------------------------------------------------------------
-// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
-//
-//
-// Permission to use, copy, modify, and/or distribute this software for any
-// purpose with or without fee is hereby granted, provided that the above
-// copyright notice and this permission notice appear in all copies.
-//
-// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-//
-//
-// ------------------------------------------------------------------
-//===================================================================
-// Author(s): ="Atheros"
-//===================================================================
-
-
-#ifdef WLAN_HEADERS
-
-#include "gpio_athr_wlan_reg.h"
-
-
-#ifndef BT_HEADERS
-
-#define GPIO_OUT_ADDRESS WLAN_GPIO_OUT_ADDRESS
-#define GPIO_OUT_OFFSET WLAN_GPIO_OUT_OFFSET
-#define GPIO_OUT_DATA_MSB WLAN_GPIO_OUT_DATA_MSB
-#define GPIO_OUT_DATA_LSB WLAN_GPIO_OUT_DATA_LSB
-#define GPIO_OUT_DATA_MASK WLAN_GPIO_OUT_DATA_MASK
-#define GPIO_OUT_DATA_GET(x) WLAN_GPIO_OUT_DATA_GET(x)
-#define GPIO_OUT_DATA_SET(x) WLAN_GPIO_OUT_DATA_SET(x)
-#define GPIO_OUT_W1TS_ADDRESS WLAN_GPIO_OUT_W1TS_ADDRESS
-#define GPIO_OUT_W1TS_OFFSET WLAN_GPIO_OUT_W1TS_OFFSET
-#define GPIO_OUT_W1TS_DATA_MSB WLAN_GPIO_OUT_W1TS_DATA_MSB
-#define GPIO_OUT_W1TS_DATA_LSB WLAN_GPIO_OUT_W1TS_DATA_LSB
-#define GPIO_OUT_W1TS_DATA_MASK WLAN_GPIO_OUT_W1TS_DATA_MASK
-#define GPIO_OUT_W1TS_DATA_GET(x) WLAN_GPIO_OUT_W1TS_DATA_GET(x)
-#define GPIO_OUT_W1TS_DATA_SET(x) WLAN_GPIO_OUT_W1TS_DATA_SET(x)
-#define GPIO_OUT_W1TC_ADDRESS WLAN_GPIO_OUT_W1TC_ADDRESS
-#define GPIO_OUT_W1TC_OFFSET WLAN_GPIO_OUT_W1TC_OFFSET
-#define GPIO_OUT_W1TC_DATA_MSB WLAN_GPIO_OUT_W1TC_DATA_MSB
-#define GPIO_OUT_W1TC_DATA_LSB WLAN_GPIO_OUT_W1TC_DATA_LSB
-#define GPIO_OUT_W1TC_DATA_MASK WLAN_GPIO_OUT_W1TC_DATA_MASK
-#define GPIO_OUT_W1TC_DATA_GET(x) WLAN_GPIO_OUT_W1TC_DATA_GET(x)
-#define GPIO_OUT_W1TC_DATA_SET(x) WLAN_GPIO_OUT_W1TC_DATA_SET(x)
-#define GPIO_ENABLE_ADDRESS WLAN_GPIO_ENABLE_ADDRESS
-#define GPIO_ENABLE_OFFSET WLAN_GPIO_ENABLE_OFFSET
-#define GPIO_ENABLE_DATA_MSB WLAN_GPIO_ENABLE_DATA_MSB
-#define GPIO_ENABLE_DATA_LSB WLAN_GPIO_ENABLE_DATA_LSB
-#define GPIO_ENABLE_DATA_MASK WLAN_GPIO_ENABLE_DATA_MASK
-#define GPIO_ENABLE_DATA_GET(x) WLAN_GPIO_ENABLE_DATA_GET(x)
-#define GPIO_ENABLE_DATA_SET(x) WLAN_GPIO_ENABLE_DATA_SET(x)
-#define GPIO_ENABLE_W1TS_ADDRESS WLAN_GPIO_ENABLE_W1TS_ADDRESS
-#define GPIO_ENABLE_W1TS_OFFSET WLAN_GPIO_ENABLE_W1TS_OFFSET
-#define GPIO_ENABLE_W1TS_DATA_MSB WLAN_GPIO_ENABLE_W1TS_DATA_MSB
-#define GPIO_ENABLE_W1TS_DATA_LSB WLAN_GPIO_ENABLE_W1TS_DATA_LSB
-#define GPIO_ENABLE_W1TS_DATA_MASK WLAN_GPIO_ENABLE_W1TS_DATA_MASK
-#define GPIO_ENABLE_W1TS_DATA_GET(x) WLAN_GPIO_ENABLE_W1TS_DATA_GET(x)
-#define GPIO_ENABLE_W1TS_DATA_SET(x) WLAN_GPIO_ENABLE_W1TS_DATA_SET(x)
-#define GPIO_ENABLE_W1TC_ADDRESS WLAN_GPIO_ENABLE_W1TC_ADDRESS
-#define GPIO_ENABLE_W1TC_OFFSET WLAN_GPIO_ENABLE_W1TC_OFFSET
-#define GPIO_ENABLE_W1TC_DATA_MSB WLAN_GPIO_ENABLE_W1TC_DATA_MSB
-#define GPIO_ENABLE_W1TC_DATA_LSB WLAN_GPIO_ENABLE_W1TC_DATA_LSB
-#define GPIO_ENABLE_W1TC_DATA_MASK WLAN_GPIO_ENABLE_W1TC_DATA_MASK
-#define GPIO_ENABLE_W1TC_DATA_GET(x) WLAN_GPIO_ENABLE_W1TC_DATA_GET(x)
-#define GPIO_ENABLE_W1TC_DATA_SET(x) WLAN_GPIO_ENABLE_W1TC_DATA_SET(x)
-#define GPIO_IN_ADDRESS WLAN_GPIO_IN_ADDRESS
-#define GPIO_IN_OFFSET WLAN_GPIO_IN_OFFSET
-#define GPIO_IN_DATA_MSB WLAN_GPIO_IN_DATA_MSB
-#define GPIO_IN_DATA_LSB WLAN_GPIO_IN_DATA_LSB
-#define GPIO_IN_DATA_MASK WLAN_GPIO_IN_DATA_MASK
-#define GPIO_IN_DATA_GET(x) WLAN_GPIO_IN_DATA_GET(x)
-#define GPIO_IN_DATA_SET(x) WLAN_GPIO_IN_DATA_SET(x)
-#define GPIO_STATUS_ADDRESS WLAN_GPIO_STATUS_ADDRESS
-#define GPIO_STATUS_OFFSET WLAN_GPIO_STATUS_OFFSET
-#define GPIO_STATUS_INTERRUPT_MSB WLAN_GPIO_STATUS_INTERRUPT_MSB
-#define GPIO_STATUS_INTERRUPT_LSB WLAN_GPIO_STATUS_INTERRUPT_LSB
-#define GPIO_STATUS_INTERRUPT_MASK WLAN_GPIO_STATUS_INTERRUPT_MASK
-#define GPIO_STATUS_INTERRUPT_GET(x) WLAN_GPIO_STATUS_INTERRUPT_GET(x)
-#define GPIO_STATUS_INTERRUPT_SET(x) WLAN_GPIO_STATUS_INTERRUPT_SET(x)
-#define GPIO_STATUS_W1TS_ADDRESS WLAN_GPIO_STATUS_W1TS_ADDRESS
-#define GPIO_STATUS_W1TS_OFFSET WLAN_GPIO_STATUS_W1TS_OFFSET
-#define GPIO_STATUS_W1TS_INTERRUPT_MSB WLAN_GPIO_STATUS_W1TS_INTERRUPT_MSB
-#define GPIO_STATUS_W1TS_INTERRUPT_LSB WLAN_GPIO_STATUS_W1TS_INTERRUPT_LSB
-#define GPIO_STATUS_W1TS_INTERRUPT_MASK WLAN_GPIO_STATUS_W1TS_INTERRUPT_MASK
-#define GPIO_STATUS_W1TS_INTERRUPT_GET(x) WLAN_GPIO_STATUS_W1TS_INTERRUPT_GET(x)
-#define GPIO_STATUS_W1TS_INTERRUPT_SET(x) WLAN_GPIO_STATUS_W1TS_INTERRUPT_SET(x)
-#define GPIO_STATUS_W1TC_ADDRESS WLAN_GPIO_STATUS_W1TC_ADDRESS
-#define GPIO_STATUS_W1TC_OFFSET WLAN_GPIO_STATUS_W1TC_OFFSET
-#define GPIO_STATUS_W1TC_INTERRUPT_MSB WLAN_GPIO_STATUS_W1TC_INTERRUPT_MSB
-#define GPIO_STATUS_W1TC_INTERRUPT_LSB WLAN_GPIO_STATUS_W1TC_INTERRUPT_LSB
-#define GPIO_STATUS_W1TC_INTERRUPT_MASK WLAN_GPIO_STATUS_W1TC_INTERRUPT_MASK
-#define GPIO_STATUS_W1TC_INTERRUPT_GET(x) WLAN_GPIO_STATUS_W1TC_INTERRUPT_GET(x)
-#define GPIO_STATUS_W1TC_INTERRUPT_SET(x) WLAN_GPIO_STATUS_W1TC_INTERRUPT_SET(x)
-#define GPIO_PIN0_ADDRESS WLAN_GPIO_PIN0_ADDRESS
-#define GPIO_PIN0_OFFSET WLAN_GPIO_PIN0_OFFSET
-#define GPIO_PIN0_CONFIG_MSB WLAN_GPIO_PIN0_CONFIG_MSB
-#define GPIO_PIN0_CONFIG_LSB WLAN_GPIO_PIN0_CONFIG_LSB
-#define GPIO_PIN0_CONFIG_MASK WLAN_GPIO_PIN0_CONFIG_MASK
-#define GPIO_PIN0_CONFIG_GET(x) WLAN_GPIO_PIN0_CONFIG_GET(x)
-#define GPIO_PIN0_CONFIG_SET(x) WLAN_GPIO_PIN0_CONFIG_SET(x)
-#define GPIO_PIN0_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN0_WAKEUP_ENABLE_MSB
-#define GPIO_PIN0_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN0_WAKEUP_ENABLE_LSB
-#define GPIO_PIN0_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN0_WAKEUP_ENABLE_MASK
-#define GPIO_PIN0_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN0_WAKEUP_ENABLE_GET(x)
-#define GPIO_PIN0_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN0_WAKEUP_ENABLE_SET(x)
-#define GPIO_PIN0_INT_TYPE_MSB WLAN_GPIO_PIN0_INT_TYPE_MSB
-#define GPIO_PIN0_INT_TYPE_LSB WLAN_GPIO_PIN0_INT_TYPE_LSB
-#define GPIO_PIN0_INT_TYPE_MASK WLAN_GPIO_PIN0_INT_TYPE_MASK
-#define GPIO_PIN0_INT_TYPE_GET(x) WLAN_GPIO_PIN0_INT_TYPE_GET(x)
-#define GPIO_PIN0_INT_TYPE_SET(x) WLAN_GPIO_PIN0_INT_TYPE_SET(x)
-#define GPIO_PIN0_PAD_PULL_MSB WLAN_GPIO_PIN0_PAD_PULL_MSB
-#define GPIO_PIN0_PAD_PULL_LSB WLAN_GPIO_PIN0_PAD_PULL_LSB
-#define GPIO_PIN0_PAD_PULL_MASK WLAN_GPIO_PIN0_PAD_PULL_MASK
-#define GPIO_PIN0_PAD_PULL_GET(x) WLAN_GPIO_PIN0_PAD_PULL_GET(x)
-#define GPIO_PIN0_PAD_PULL_SET(x) WLAN_GPIO_PIN0_PAD_PULL_SET(x)
-#define GPIO_PIN0_PAD_STRENGTH_MSB WLAN_GPIO_PIN0_PAD_STRENGTH_MSB
-#define GPIO_PIN0_PAD_STRENGTH_LSB WLAN_GPIO_PIN0_PAD_STRENGTH_LSB
-#define GPIO_PIN0_PAD_STRENGTH_MASK WLAN_GPIO_PIN0_PAD_STRENGTH_MASK
-#define GPIO_PIN0_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN0_PAD_STRENGTH_GET(x)
-#define GPIO_PIN0_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN0_PAD_STRENGTH_SET(x)
-#define GPIO_PIN0_PAD_DRIVER_MSB WLAN_GPIO_PIN0_PAD_DRIVER_MSB
-#define GPIO_PIN0_PAD_DRIVER_LSB WLAN_GPIO_PIN0_PAD_DRIVER_LSB
-#define GPIO_PIN0_PAD_DRIVER_MASK WLAN_GPIO_PIN0_PAD_DRIVER_MASK
-#define GPIO_PIN0_PAD_DRIVER_GET(x) WLAN_GPIO_PIN0_PAD_DRIVER_GET(x)
-#define GPIO_PIN0_PAD_DRIVER_SET(x) WLAN_GPIO_PIN0_PAD_DRIVER_SET(x)
-#define GPIO_PIN0_SOURCE_MSB WLAN_GPIO_PIN0_SOURCE_MSB
-#define GPIO_PIN0_SOURCE_LSB WLAN_GPIO_PIN0_SOURCE_LSB
-#define GPIO_PIN0_SOURCE_MASK WLAN_GPIO_PIN0_SOURCE_MASK
-#define GPIO_PIN0_SOURCE_GET(x) WLAN_GPIO_PIN0_SOURCE_GET(x)
-#define GPIO_PIN0_SOURCE_SET(x) WLAN_GPIO_PIN0_SOURCE_SET(x)
-#define GPIO_PIN1_ADDRESS WLAN_GPIO_PIN1_ADDRESS
-#define GPIO_PIN1_OFFSET WLAN_GPIO_PIN1_OFFSET
-#define GPIO_PIN1_CONFIG_MSB WLAN_GPIO_PIN1_CONFIG_MSB
-#define GPIO_PIN1_CONFIG_LSB WLAN_GPIO_PIN1_CONFIG_LSB
-#define GPIO_PIN1_CONFIG_MASK WLAN_GPIO_PIN1_CONFIG_MASK
-#define GPIO_PIN1_CONFIG_GET(x) WLAN_GPIO_PIN1_CONFIG_GET(x)
-#define GPIO_PIN1_CONFIG_SET(x) WLAN_GPIO_PIN1_CONFIG_SET(x)
-#define GPIO_PIN1_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN1_WAKEUP_ENABLE_MSB
-#define GPIO_PIN1_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN1_WAKEUP_ENABLE_LSB
-#define GPIO_PIN1_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN1_WAKEUP_ENABLE_MASK
-#define GPIO_PIN1_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN1_WAKEUP_ENABLE_GET(x)
-#define GPIO_PIN1_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN1_WAKEUP_ENABLE_SET(x)
-#define GPIO_PIN1_INT_TYPE_MSB WLAN_GPIO_PIN1_INT_TYPE_MSB
-#define GPIO_PIN1_INT_TYPE_LSB WLAN_GPIO_PIN1_INT_TYPE_LSB
-#define GPIO_PIN1_INT_TYPE_MASK WLAN_GPIO_PIN1_INT_TYPE_MASK
-#define GPIO_PIN1_INT_TYPE_GET(x) WLAN_GPIO_PIN1_INT_TYPE_GET(x)
-#define GPIO_PIN1_INT_TYPE_SET(x) WLAN_GPIO_PIN1_INT_TYPE_SET(x)
-#define GPIO_PIN1_PAD_PULL_MSB WLAN_GPIO_PIN1_PAD_PULL_MSB
-#define GPIO_PIN1_PAD_PULL_LSB WLAN_GPIO_PIN1_PAD_PULL_LSB
-#define GPIO_PIN1_PAD_PULL_MASK WLAN_GPIO_PIN1_PAD_PULL_MASK
-#define GPIO_PIN1_PAD_PULL_GET(x) WLAN_GPIO_PIN1_PAD_PULL_GET(x)
-#define GPIO_PIN1_PAD_PULL_SET(x) WLAN_GPIO_PIN1_PAD_PULL_SET(x)
-#define GPIO_PIN1_PAD_STRENGTH_MSB WLAN_GPIO_PIN1_PAD_STRENGTH_MSB
-#define GPIO_PIN1_PAD_STRENGTH_LSB WLAN_GPIO_PIN1_PAD_STRENGTH_LSB
-#define GPIO_PIN1_PAD_STRENGTH_MASK WLAN_GPIO_PIN1_PAD_STRENGTH_MASK
-#define GPIO_PIN1_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN1_PAD_STRENGTH_GET(x)
-#define GPIO_PIN1_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN1_PAD_STRENGTH_SET(x)
-#define GPIO_PIN1_PAD_DRIVER_MSB WLAN_GPIO_PIN1_PAD_DRIVER_MSB
-#define GPIO_PIN1_PAD_DRIVER_LSB WLAN_GPIO_PIN1_PAD_DRIVER_LSB
-#define GPIO_PIN1_PAD_DRIVER_MASK WLAN_GPIO_PIN1_PAD_DRIVER_MASK
-#define GPIO_PIN1_PAD_DRIVER_GET(x) WLAN_GPIO_PIN1_PAD_DRIVER_GET(x)
-#define GPIO_PIN1_PAD_DRIVER_SET(x) WLAN_GPIO_PIN1_PAD_DRIVER_SET(x)
-#define GPIO_PIN1_SOURCE_MSB WLAN_GPIO_PIN1_SOURCE_MSB
-#define GPIO_PIN1_SOURCE_LSB WLAN_GPIO_PIN1_SOURCE_LSB
-#define GPIO_PIN1_SOURCE_MASK WLAN_GPIO_PIN1_SOURCE_MASK
-#define GPIO_PIN1_SOURCE_GET(x) WLAN_GPIO_PIN1_SOURCE_GET(x)
-#define GPIO_PIN1_SOURCE_SET(x) WLAN_GPIO_PIN1_SOURCE_SET(x)
-#define GPIO_PIN2_ADDRESS WLAN_GPIO_PIN2_ADDRESS
-#define GPIO_PIN2_OFFSET WLAN_GPIO_PIN2_OFFSET
-#define GPIO_PIN2_CONFIG_MSB WLAN_GPIO_PIN2_CONFIG_MSB
-#define GPIO_PIN2_CONFIG_LSB WLAN_GPIO_PIN2_CONFIG_LSB
-#define GPIO_PIN2_CONFIG_MASK WLAN_GPIO_PIN2_CONFIG_MASK
-#define GPIO_PIN2_CONFIG_GET(x) WLAN_GPIO_PIN2_CONFIG_GET(x)
-#define GPIO_PIN2_CONFIG_SET(x) WLAN_GPIO_PIN2_CONFIG_SET(x)
-#define GPIO_PIN2_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN2_WAKEUP_ENABLE_MSB
-#define GPIO_PIN2_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN2_WAKEUP_ENABLE_LSB
-#define GPIO_PIN2_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN2_WAKEUP_ENABLE_MASK
-#define GPIO_PIN2_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN2_WAKEUP_ENABLE_GET(x)
-#define GPIO_PIN2_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN2_WAKEUP_ENABLE_SET(x)
-#define GPIO_PIN2_INT_TYPE_MSB WLAN_GPIO_PIN2_INT_TYPE_MSB
-#define GPIO_PIN2_INT_TYPE_LSB WLAN_GPIO_PIN2_INT_TYPE_LSB
-#define GPIO_PIN2_INT_TYPE_MASK WLAN_GPIO_PIN2_INT_TYPE_MASK
-#define GPIO_PIN2_INT_TYPE_GET(x) WLAN_GPIO_PIN2_INT_TYPE_GET(x)
-#define GPIO_PIN2_INT_TYPE_SET(x) WLAN_GPIO_PIN2_INT_TYPE_SET(x)
-#define GPIO_PIN2_PAD_PULL_MSB WLAN_GPIO_PIN2_PAD_PULL_MSB
-#define GPIO_PIN2_PAD_PULL_LSB WLAN_GPIO_PIN2_PAD_PULL_LSB
-#define GPIO_PIN2_PAD_PULL_MASK WLAN_GPIO_PIN2_PAD_PULL_MASK
-#define GPIO_PIN2_PAD_PULL_GET(x) WLAN_GPIO_PIN2_PAD_PULL_GET(x)
-#define GPIO_PIN2_PAD_PULL_SET(x) WLAN_GPIO_PIN2_PAD_PULL_SET(x)
-#define GPIO_PIN2_PAD_STRENGTH_MSB WLAN_GPIO_PIN2_PAD_STRENGTH_MSB
-#define GPIO_PIN2_PAD_STRENGTH_LSB WLAN_GPIO_PIN2_PAD_STRENGTH_LSB
-#define GPIO_PIN2_PAD_STRENGTH_MASK WLAN_GPIO_PIN2_PAD_STRENGTH_MASK
-#define GPIO_PIN2_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN2_PAD_STRENGTH_GET(x)
-#define GPIO_PIN2_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN2_PAD_STRENGTH_SET(x)
-#define GPIO_PIN2_PAD_DRIVER_MSB WLAN_GPIO_PIN2_PAD_DRIVER_MSB
-#define GPIO_PIN2_PAD_DRIVER_LSB WLAN_GPIO_PIN2_PAD_DRIVER_LSB
-#define GPIO_PIN2_PAD_DRIVER_MASK WLAN_GPIO_PIN2_PAD_DRIVER_MASK
-#define GPIO_PIN2_PAD_DRIVER_GET(x) WLAN_GPIO_PIN2_PAD_DRIVER_GET(x)
-#define GPIO_PIN2_PAD_DRIVER_SET(x) WLAN_GPIO_PIN2_PAD_DRIVER_SET(x)
-#define GPIO_PIN2_SOURCE_MSB WLAN_GPIO_PIN2_SOURCE_MSB
-#define GPIO_PIN2_SOURCE_LSB WLAN_GPIO_PIN2_SOURCE_LSB
-#define GPIO_PIN2_SOURCE_MASK WLAN_GPIO_PIN2_SOURCE_MASK
-#define GPIO_PIN2_SOURCE_GET(x) WLAN_GPIO_PIN2_SOURCE_GET(x)
-#define GPIO_PIN2_SOURCE_SET(x) WLAN_GPIO_PIN2_SOURCE_SET(x)
-#define GPIO_PIN3_ADDRESS WLAN_GPIO_PIN3_ADDRESS
-#define GPIO_PIN3_OFFSET WLAN_GPIO_PIN3_OFFSET
-#define GPIO_PIN3_CONFIG_MSB WLAN_GPIO_PIN3_CONFIG_MSB
-#define GPIO_PIN3_CONFIG_LSB WLAN_GPIO_PIN3_CONFIG_LSB
-#define GPIO_PIN3_CONFIG_MASK WLAN_GPIO_PIN3_CONFIG_MASK
-#define GPIO_PIN3_CONFIG_GET(x) WLAN_GPIO_PIN3_CONFIG_GET(x)
-#define GPIO_PIN3_CONFIG_SET(x) WLAN_GPIO_PIN3_CONFIG_SET(x)
-#define GPIO_PIN3_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN3_WAKEUP_ENABLE_MSB
-#define GPIO_PIN3_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN3_WAKEUP_ENABLE_LSB
-#define GPIO_PIN3_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN3_WAKEUP_ENABLE_MASK
-#define GPIO_PIN3_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN3_WAKEUP_ENABLE_GET(x)
-#define GPIO_PIN3_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN3_WAKEUP_ENABLE_SET(x)
-#define GPIO_PIN3_INT_TYPE_MSB WLAN_GPIO_PIN3_INT_TYPE_MSB
-#define GPIO_PIN3_INT_TYPE_LSB WLAN_GPIO_PIN3_INT_TYPE_LSB
-#define GPIO_PIN3_INT_TYPE_MASK WLAN_GPIO_PIN3_INT_TYPE_MASK
-#define GPIO_PIN3_INT_TYPE_GET(x) WLAN_GPIO_PIN3_INT_TYPE_GET(x)
-#define GPIO_PIN3_INT_TYPE_SET(x) WLAN_GPIO_PIN3_INT_TYPE_SET(x)
-#define GPIO_PIN3_PAD_PULL_MSB WLAN_GPIO_PIN3_PAD_PULL_MSB
-#define GPIO_PIN3_PAD_PULL_LSB WLAN_GPIO_PIN3_PAD_PULL_LSB
-#define GPIO_PIN3_PAD_PULL_MASK WLAN_GPIO_PIN3_PAD_PULL_MASK
-#define GPIO_PIN3_PAD_PULL_GET(x) WLAN_GPIO_PIN3_PAD_PULL_GET(x)
-#define GPIO_PIN3_PAD_PULL_SET(x) WLAN_GPIO_PIN3_PAD_PULL_SET(x)
-#define GPIO_PIN3_PAD_STRENGTH_MSB WLAN_GPIO_PIN3_PAD_STRENGTH_MSB
-#define GPIO_PIN3_PAD_STRENGTH_LSB WLAN_GPIO_PIN3_PAD_STRENGTH_LSB
-#define GPIO_PIN3_PAD_STRENGTH_MASK WLAN_GPIO_PIN3_PAD_STRENGTH_MASK
-#define GPIO_PIN3_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN3_PAD_STRENGTH_GET(x)
-#define GPIO_PIN3_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN3_PAD_STRENGTH_SET(x)
-#define GPIO_PIN3_PAD_DRIVER_MSB WLAN_GPIO_PIN3_PAD_DRIVER_MSB
-#define GPIO_PIN3_PAD_DRIVER_LSB WLAN_GPIO_PIN3_PAD_DRIVER_LSB
-#define GPIO_PIN3_PAD_DRIVER_MASK WLAN_GPIO_PIN3_PAD_DRIVER_MASK
-#define GPIO_PIN3_PAD_DRIVER_GET(x) WLAN_GPIO_PIN3_PAD_DRIVER_GET(x)
-#define GPIO_PIN3_PAD_DRIVER_SET(x) WLAN_GPIO_PIN3_PAD_DRIVER_SET(x)
-#define GPIO_PIN3_SOURCE_MSB WLAN_GPIO_PIN3_SOURCE_MSB
-#define GPIO_PIN3_SOURCE_LSB WLAN_GPIO_PIN3_SOURCE_LSB
-#define GPIO_PIN3_SOURCE_MASK WLAN_GPIO_PIN3_SOURCE_MASK
-#define GPIO_PIN3_SOURCE_GET(x) WLAN_GPIO_PIN3_SOURCE_GET(x)
-#define GPIO_PIN3_SOURCE_SET(x) WLAN_GPIO_PIN3_SOURCE_SET(x)
-#define GPIO_PIN4_ADDRESS WLAN_GPIO_PIN4_ADDRESS
-#define GPIO_PIN4_OFFSET WLAN_GPIO_PIN4_OFFSET
-#define GPIO_PIN4_CONFIG_MSB WLAN_GPIO_PIN4_CONFIG_MSB
-#define GPIO_PIN4_CONFIG_LSB WLAN_GPIO_PIN4_CONFIG_LSB
-#define GPIO_PIN4_CONFIG_MASK WLAN_GPIO_PIN4_CONFIG_MASK
-#define GPIO_PIN4_CONFIG_GET(x) WLAN_GPIO_PIN4_CONFIG_GET(x)
-#define GPIO_PIN4_CONFIG_SET(x) WLAN_GPIO_PIN4_CONFIG_SET(x)
-#define GPIO_PIN4_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN4_WAKEUP_ENABLE_MSB
-#define GPIO_PIN4_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN4_WAKEUP_ENABLE_LSB
-#define GPIO_PIN4_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN4_WAKEUP_ENABLE_MASK
-#define GPIO_PIN4_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN4_WAKEUP_ENABLE_GET(x)
-#define GPIO_PIN4_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN4_WAKEUP_ENABLE_SET(x)
-#define GPIO_PIN4_INT_TYPE_MSB WLAN_GPIO_PIN4_INT_TYPE_MSB
-#define GPIO_PIN4_INT_TYPE_LSB WLAN_GPIO_PIN4_INT_TYPE_LSB
-#define GPIO_PIN4_INT_TYPE_MASK WLAN_GPIO_PIN4_INT_TYPE_MASK
-#define GPIO_PIN4_INT_TYPE_GET(x) WLAN_GPIO_PIN4_INT_TYPE_GET(x)
-#define GPIO_PIN4_INT_TYPE_SET(x) WLAN_GPIO_PIN4_INT_TYPE_SET(x)
-#define GPIO_PIN4_PAD_PULL_MSB WLAN_GPIO_PIN4_PAD_PULL_MSB
-#define GPIO_PIN4_PAD_PULL_LSB WLAN_GPIO_PIN4_PAD_PULL_LSB
-#define GPIO_PIN4_PAD_PULL_MASK WLAN_GPIO_PIN4_PAD_PULL_MASK
-#define GPIO_PIN4_PAD_PULL_GET(x) WLAN_GPIO_PIN4_PAD_PULL_GET(x)
-#define GPIO_PIN4_PAD_PULL_SET(x) WLAN_GPIO_PIN4_PAD_PULL_SET(x)
-#define GPIO_PIN4_PAD_STRENGTH_MSB WLAN_GPIO_PIN4_PAD_STRENGTH_MSB
-#define GPIO_PIN4_PAD_STRENGTH_LSB WLAN_GPIO_PIN4_PAD_STRENGTH_LSB
-#define GPIO_PIN4_PAD_STRENGTH_MASK WLAN_GPIO_PIN4_PAD_STRENGTH_MASK
-#define GPIO_PIN4_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN4_PAD_STRENGTH_GET(x)
-#define GPIO_PIN4_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN4_PAD_STRENGTH_SET(x)
-#define GPIO_PIN4_PAD_DRIVER_MSB WLAN_GPIO_PIN4_PAD_DRIVER_MSB
-#define GPIO_PIN4_PAD_DRIVER_LSB WLAN_GPIO_PIN4_PAD_DRIVER_LSB
-#define GPIO_PIN4_PAD_DRIVER_MASK WLAN_GPIO_PIN4_PAD_DRIVER_MASK
-#define GPIO_PIN4_PAD_DRIVER_GET(x) WLAN_GPIO_PIN4_PAD_DRIVER_GET(x)
-#define GPIO_PIN4_PAD_DRIVER_SET(x) WLAN_GPIO_PIN4_PAD_DRIVER_SET(x)
-#define GPIO_PIN4_SOURCE_MSB WLAN_GPIO_PIN4_SOURCE_MSB
-#define GPIO_PIN4_SOURCE_LSB WLAN_GPIO_PIN4_SOURCE_LSB
-#define GPIO_PIN4_SOURCE_MASK WLAN_GPIO_PIN4_SOURCE_MASK
-#define GPIO_PIN4_SOURCE_GET(x) WLAN_GPIO_PIN4_SOURCE_GET(x)
-#define GPIO_PIN4_SOURCE_SET(x) WLAN_GPIO_PIN4_SOURCE_SET(x)
-#define GPIO_PIN5_ADDRESS WLAN_GPIO_PIN5_ADDRESS
-#define GPIO_PIN5_OFFSET WLAN_GPIO_PIN5_OFFSET
-#define GPIO_PIN5_CONFIG_MSB WLAN_GPIO_PIN5_CONFIG_MSB
-#define GPIO_PIN5_CONFIG_LSB WLAN_GPIO_PIN5_CONFIG_LSB
-#define GPIO_PIN5_CONFIG_MASK WLAN_GPIO_PIN5_CONFIG_MASK
-#define GPIO_PIN5_CONFIG_GET(x) WLAN_GPIO_PIN5_CONFIG_GET(x)
-#define GPIO_PIN5_CONFIG_SET(x) WLAN_GPIO_PIN5_CONFIG_SET(x)
-#define GPIO_PIN5_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN5_WAKEUP_ENABLE_MSB
-#define GPIO_PIN5_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN5_WAKEUP_ENABLE_LSB
-#define GPIO_PIN5_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN5_WAKEUP_ENABLE_MASK
-#define GPIO_PIN5_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN5_WAKEUP_ENABLE_GET(x)
-#define GPIO_PIN5_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN5_WAKEUP_ENABLE_SET(x)
-#define GPIO_PIN5_INT_TYPE_MSB WLAN_GPIO_PIN5_INT_TYPE_MSB
-#define GPIO_PIN5_INT_TYPE_LSB WLAN_GPIO_PIN5_INT_TYPE_LSB
-#define GPIO_PIN5_INT_TYPE_MASK WLAN_GPIO_PIN5_INT_TYPE_MASK
-#define GPIO_PIN5_INT_TYPE_GET(x) WLAN_GPIO_PIN5_INT_TYPE_GET(x)
-#define GPIO_PIN5_INT_TYPE_SET(x) WLAN_GPIO_PIN5_INT_TYPE_SET(x)
-#define GPIO_PIN5_PAD_PULL_MSB WLAN_GPIO_PIN5_PAD_PULL_MSB
-#define GPIO_PIN5_PAD_PULL_LSB WLAN_GPIO_PIN5_PAD_PULL_LSB
-#define GPIO_PIN5_PAD_PULL_MASK WLAN_GPIO_PIN5_PAD_PULL_MASK
-#define GPIO_PIN5_PAD_PULL_GET(x) WLAN_GPIO_PIN5_PAD_PULL_GET(x)
-#define GPIO_PIN5_PAD_PULL_SET(x) WLAN_GPIO_PIN5_PAD_PULL_SET(x)
-#define GPIO_PIN5_PAD_STRENGTH_MSB WLAN_GPIO_PIN5_PAD_STRENGTH_MSB
-#define GPIO_PIN5_PAD_STRENGTH_LSB WLAN_GPIO_PIN5_PAD_STRENGTH_LSB
-#define GPIO_PIN5_PAD_STRENGTH_MASK WLAN_GPIO_PIN5_PAD_STRENGTH_MASK
-#define GPIO_PIN5_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN5_PAD_STRENGTH_GET(x)
-#define GPIO_PIN5_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN5_PAD_STRENGTH_SET(x)
-#define GPIO_PIN5_PAD_DRIVER_MSB WLAN_GPIO_PIN5_PAD_DRIVER_MSB
-#define GPIO_PIN5_PAD_DRIVER_LSB WLAN_GPIO_PIN5_PAD_DRIVER_LSB
-#define GPIO_PIN5_PAD_DRIVER_MASK WLAN_GPIO_PIN5_PAD_DRIVER_MASK
-#define GPIO_PIN5_PAD_DRIVER_GET(x) WLAN_GPIO_PIN5_PAD_DRIVER_GET(x)
-#define GPIO_PIN5_PAD_DRIVER_SET(x) WLAN_GPIO_PIN5_PAD_DRIVER_SET(x)
-#define GPIO_PIN5_SOURCE_MSB WLAN_GPIO_PIN5_SOURCE_MSB
-#define GPIO_PIN5_SOURCE_LSB WLAN_GPIO_PIN5_SOURCE_LSB
-#define GPIO_PIN5_SOURCE_MASK WLAN_GPIO_PIN5_SOURCE_MASK
-#define GPIO_PIN5_SOURCE_GET(x) WLAN_GPIO_PIN5_SOURCE_GET(x)
-#define GPIO_PIN5_SOURCE_SET(x) WLAN_GPIO_PIN5_SOURCE_SET(x)
-#define GPIO_PIN6_ADDRESS WLAN_GPIO_PIN6_ADDRESS
-#define GPIO_PIN6_OFFSET WLAN_GPIO_PIN6_OFFSET
-#define GPIO_PIN6_CONFIG_MSB WLAN_GPIO_PIN6_CONFIG_MSB
-#define GPIO_PIN6_CONFIG_LSB WLAN_GPIO_PIN6_CONFIG_LSB
-#define GPIO_PIN6_CONFIG_MASK WLAN_GPIO_PIN6_CONFIG_MASK
-#define GPIO_PIN6_CONFIG_GET(x) WLAN_GPIO_PIN6_CONFIG_GET(x)
-#define GPIO_PIN6_CONFIG_SET(x) WLAN_GPIO_PIN6_CONFIG_SET(x)
-#define GPIO_PIN6_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN6_WAKEUP_ENABLE_MSB
-#define GPIO_PIN6_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN6_WAKEUP_ENABLE_LSB
-#define GPIO_PIN6_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN6_WAKEUP_ENABLE_MASK
-#define GPIO_PIN6_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN6_WAKEUP_ENABLE_GET(x)
-#define GPIO_PIN6_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN6_WAKEUP_ENABLE_SET(x)
-#define GPIO_PIN6_INT_TYPE_MSB WLAN_GPIO_PIN6_INT_TYPE_MSB
-#define GPIO_PIN6_INT_TYPE_LSB WLAN_GPIO_PIN6_INT_TYPE_LSB
-#define GPIO_PIN6_INT_TYPE_MASK WLAN_GPIO_PIN6_INT_TYPE_MASK
-#define GPIO_PIN6_INT_TYPE_GET(x) WLAN_GPIO_PIN6_INT_TYPE_GET(x)
-#define GPIO_PIN6_INT_TYPE_SET(x) WLAN_GPIO_PIN6_INT_TYPE_SET(x)
-#define GPIO_PIN6_PAD_PULL_MSB WLAN_GPIO_PIN6_PAD_PULL_MSB
-#define GPIO_PIN6_PAD_PULL_LSB WLAN_GPIO_PIN6_PAD_PULL_LSB
-#define GPIO_PIN6_PAD_PULL_MASK WLAN_GPIO_PIN6_PAD_PULL_MASK
-#define GPIO_PIN6_PAD_PULL_GET(x) WLAN_GPIO_PIN6_PAD_PULL_GET(x)
-#define GPIO_PIN6_PAD_PULL_SET(x) WLAN_GPIO_PIN6_PAD_PULL_SET(x)
-#define GPIO_PIN6_PAD_STRENGTH_MSB WLAN_GPIO_PIN6_PAD_STRENGTH_MSB
-#define GPIO_PIN6_PAD_STRENGTH_LSB WLAN_GPIO_PIN6_PAD_STRENGTH_LSB
-#define GPIO_PIN6_PAD_STRENGTH_MASK WLAN_GPIO_PIN6_PAD_STRENGTH_MASK
-#define GPIO_PIN6_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN6_PAD_STRENGTH_GET(x)
-#define GPIO_PIN6_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN6_PAD_STRENGTH_SET(x)
-#define GPIO_PIN6_PAD_DRIVER_MSB WLAN_GPIO_PIN6_PAD_DRIVER_MSB
-#define GPIO_PIN6_PAD_DRIVER_LSB WLAN_GPIO_PIN6_PAD_DRIVER_LSB
-#define GPIO_PIN6_PAD_DRIVER_MASK WLAN_GPIO_PIN6_PAD_DRIVER_MASK
-#define GPIO_PIN6_PAD_DRIVER_GET(x) WLAN_GPIO_PIN6_PAD_DRIVER_GET(x)
-#define GPIO_PIN6_PAD_DRIVER_SET(x) WLAN_GPIO_PIN6_PAD_DRIVER_SET(x)
-#define GPIO_PIN6_SOURCE_MSB WLAN_GPIO_PIN6_SOURCE_MSB
-#define GPIO_PIN6_SOURCE_LSB WLAN_GPIO_PIN6_SOURCE_LSB
-#define GPIO_PIN6_SOURCE_MASK WLAN_GPIO_PIN6_SOURCE_MASK
-#define GPIO_PIN6_SOURCE_GET(x) WLAN_GPIO_PIN6_SOURCE_GET(x)
-#define GPIO_PIN6_SOURCE_SET(x) WLAN_GPIO_PIN6_SOURCE_SET(x)
-#define GPIO_PIN7_ADDRESS WLAN_GPIO_PIN7_ADDRESS
-#define GPIO_PIN7_OFFSET WLAN_GPIO_PIN7_OFFSET
-#define GPIO_PIN7_CONFIG_MSB WLAN_GPIO_PIN7_CONFIG_MSB
-#define GPIO_PIN7_CONFIG_LSB WLAN_GPIO_PIN7_CONFIG_LSB
-#define GPIO_PIN7_CONFIG_MASK WLAN_GPIO_PIN7_CONFIG_MASK
-#define GPIO_PIN7_CONFIG_GET(x) WLAN_GPIO_PIN7_CONFIG_GET(x)
-#define GPIO_PIN7_CONFIG_SET(x) WLAN_GPIO_PIN7_CONFIG_SET(x)
-#define GPIO_PIN7_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN7_WAKEUP_ENABLE_MSB
-#define GPIO_PIN7_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN7_WAKEUP_ENABLE_LSB
-#define GPIO_PIN7_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN7_WAKEUP_ENABLE_MASK
-#define GPIO_PIN7_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN7_WAKEUP_ENABLE_GET(x)
-#define GPIO_PIN7_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN7_WAKEUP_ENABLE_SET(x)
-#define GPIO_PIN7_INT_TYPE_MSB WLAN_GPIO_PIN7_INT_TYPE_MSB
-#define GPIO_PIN7_INT_TYPE_LSB WLAN_GPIO_PIN7_INT_TYPE_LSB
-#define GPIO_PIN7_INT_TYPE_MASK WLAN_GPIO_PIN7_INT_TYPE_MASK
-#define GPIO_PIN7_INT_TYPE_GET(x) WLAN_GPIO_PIN7_INT_TYPE_GET(x)
-#define GPIO_PIN7_INT_TYPE_SET(x) WLAN_GPIO_PIN7_INT_TYPE_SET(x)
-#define GPIO_PIN7_PAD_PULL_MSB WLAN_GPIO_PIN7_PAD_PULL_MSB
-#define GPIO_PIN7_PAD_PULL_LSB WLAN_GPIO_PIN7_PAD_PULL_LSB
-#define GPIO_PIN7_PAD_PULL_MASK WLAN_GPIO_PIN7_PAD_PULL_MASK
-#define GPIO_PIN7_PAD_PULL_GET(x) WLAN_GPIO_PIN7_PAD_PULL_GET(x)
-#define GPIO_PIN7_PAD_PULL_SET(x) WLAN_GPIO_PIN7_PAD_PULL_SET(x)
-#define GPIO_PIN7_PAD_STRENGTH_MSB WLAN_GPIO_PIN7_PAD_STRENGTH_MSB
-#define GPIO_PIN7_PAD_STRENGTH_LSB WLAN_GPIO_PIN7_PAD_STRENGTH_LSB
-#define GPIO_PIN7_PAD_STRENGTH_MASK WLAN_GPIO_PIN7_PAD_STRENGTH_MASK
-#define GPIO_PIN7_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN7_PAD_STRENGTH_GET(x)
-#define GPIO_PIN7_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN7_PAD_STRENGTH_SET(x)
-#define GPIO_PIN7_PAD_DRIVER_MSB WLAN_GPIO_PIN7_PAD_DRIVER_MSB
-#define GPIO_PIN7_PAD_DRIVER_LSB WLAN_GPIO_PIN7_PAD_DRIVER_LSB
-#define GPIO_PIN7_PAD_DRIVER_MASK WLAN_GPIO_PIN7_PAD_DRIVER_MASK
-#define GPIO_PIN7_PAD_DRIVER_GET(x) WLAN_GPIO_PIN7_PAD_DRIVER_GET(x)
-#define GPIO_PIN7_PAD_DRIVER_SET(x) WLAN_GPIO_PIN7_PAD_DRIVER_SET(x)
-#define GPIO_PIN7_SOURCE_MSB WLAN_GPIO_PIN7_SOURCE_MSB
-#define GPIO_PIN7_SOURCE_LSB WLAN_GPIO_PIN7_SOURCE_LSB
-#define GPIO_PIN7_SOURCE_MASK WLAN_GPIO_PIN7_SOURCE_MASK
-#define GPIO_PIN7_SOURCE_GET(x) WLAN_GPIO_PIN7_SOURCE_GET(x)
-#define GPIO_PIN7_SOURCE_SET(x) WLAN_GPIO_PIN7_SOURCE_SET(x)
-#define GPIO_PIN8_ADDRESS WLAN_GPIO_PIN8_ADDRESS
-#define GPIO_PIN8_OFFSET WLAN_GPIO_PIN8_OFFSET
-#define GPIO_PIN8_CONFIG_MSB WLAN_GPIO_PIN8_CONFIG_MSB
-#define GPIO_PIN8_CONFIG_LSB WLAN_GPIO_PIN8_CONFIG_LSB
-#define GPIO_PIN8_CONFIG_MASK WLAN_GPIO_PIN8_CONFIG_MASK
-#define GPIO_PIN8_CONFIG_GET(x) WLAN_GPIO_PIN8_CONFIG_GET(x)
-#define GPIO_PIN8_CONFIG_SET(x) WLAN_GPIO_PIN8_CONFIG_SET(x)
-#define GPIO_PIN8_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN8_WAKEUP_ENABLE_MSB
-#define GPIO_PIN8_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN8_WAKEUP_ENABLE_LSB
-#define GPIO_PIN8_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN8_WAKEUP_ENABLE_MASK
-#define GPIO_PIN8_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN8_WAKEUP_ENABLE_GET(x)
-#define GPIO_PIN8_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN8_WAKEUP_ENABLE_SET(x)
-#define GPIO_PIN8_INT_TYPE_MSB WLAN_GPIO_PIN8_INT_TYPE_MSB
-#define GPIO_PIN8_INT_TYPE_LSB WLAN_GPIO_PIN8_INT_TYPE_LSB
-#define GPIO_PIN8_INT_TYPE_MASK WLAN_GPIO_PIN8_INT_TYPE_MASK
-#define GPIO_PIN8_INT_TYPE_GET(x) WLAN_GPIO_PIN8_INT_TYPE_GET(x)
-#define GPIO_PIN8_INT_TYPE_SET(x) WLAN_GPIO_PIN8_INT_TYPE_SET(x)
-#define GPIO_PIN8_PAD_PULL_MSB WLAN_GPIO_PIN8_PAD_PULL_MSB
-#define GPIO_PIN8_PAD_PULL_LSB WLAN_GPIO_PIN8_PAD_PULL_LSB
-#define GPIO_PIN8_PAD_PULL_MASK WLAN_GPIO_PIN8_PAD_PULL_MASK
-#define GPIO_PIN8_PAD_PULL_GET(x) WLAN_GPIO_PIN8_PAD_PULL_GET(x)
-#define GPIO_PIN8_PAD_PULL_SET(x) WLAN_GPIO_PIN8_PAD_PULL_SET(x)
-#define GPIO_PIN8_PAD_STRENGTH_MSB WLAN_GPIO_PIN8_PAD_STRENGTH_MSB
-#define GPIO_PIN8_PAD_STRENGTH_LSB WLAN_GPIO_PIN8_PAD_STRENGTH_LSB
-#define GPIO_PIN8_PAD_STRENGTH_MASK WLAN_GPIO_PIN8_PAD_STRENGTH_MASK
-#define GPIO_PIN8_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN8_PAD_STRENGTH_GET(x)
-#define GPIO_PIN8_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN8_PAD_STRENGTH_SET(x)
-#define GPIO_PIN8_PAD_DRIVER_MSB WLAN_GPIO_PIN8_PAD_DRIVER_MSB
-#define GPIO_PIN8_PAD_DRIVER_LSB WLAN_GPIO_PIN8_PAD_DRIVER_LSB
-#define GPIO_PIN8_PAD_DRIVER_MASK WLAN_GPIO_PIN8_PAD_DRIVER_MASK
-#define GPIO_PIN8_PAD_DRIVER_GET(x) WLAN_GPIO_PIN8_PAD_DRIVER_GET(x)
-#define GPIO_PIN8_PAD_DRIVER_SET(x) WLAN_GPIO_PIN8_PAD_DRIVER_SET(x)
-#define GPIO_PIN8_SOURCE_MSB WLAN_GPIO_PIN8_SOURCE_MSB
-#define GPIO_PIN8_SOURCE_LSB WLAN_GPIO_PIN8_SOURCE_LSB
-#define GPIO_PIN8_SOURCE_MASK WLAN_GPIO_PIN8_SOURCE_MASK
-#define GPIO_PIN8_SOURCE_GET(x) WLAN_GPIO_PIN8_SOURCE_GET(x)
-#define GPIO_PIN8_SOURCE_SET(x) WLAN_GPIO_PIN8_SOURCE_SET(x)
-#define GPIO_PIN9_ADDRESS WLAN_GPIO_PIN9_ADDRESS
-#define GPIO_PIN9_OFFSET WLAN_GPIO_PIN9_OFFSET
-#define GPIO_PIN9_CONFIG_MSB WLAN_GPIO_PIN9_CONFIG_MSB
-#define GPIO_PIN9_CONFIG_LSB WLAN_GPIO_PIN9_CONFIG_LSB
-#define GPIO_PIN9_CONFIG_MASK WLAN_GPIO_PIN9_CONFIG_MASK
-#define GPIO_PIN9_CONFIG_GET(x) WLAN_GPIO_PIN9_CONFIG_GET(x)
-#define GPIO_PIN9_CONFIG_SET(x) WLAN_GPIO_PIN9_CONFIG_SET(x)
-#define GPIO_PIN9_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN9_WAKEUP_ENABLE_MSB
-#define GPIO_PIN9_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN9_WAKEUP_ENABLE_LSB
-#define GPIO_PIN9_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN9_WAKEUP_ENABLE_MASK
-#define GPIO_PIN9_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN9_WAKEUP_ENABLE_GET(x)
-#define GPIO_PIN9_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN9_WAKEUP_ENABLE_SET(x)
-#define GPIO_PIN9_INT_TYPE_MSB WLAN_GPIO_PIN9_INT_TYPE_MSB
-#define GPIO_PIN9_INT_TYPE_LSB WLAN_GPIO_PIN9_INT_TYPE_LSB
-#define GPIO_PIN9_INT_TYPE_MASK WLAN_GPIO_PIN9_INT_TYPE_MASK
-#define GPIO_PIN9_INT_TYPE_GET(x) WLAN_GPIO_PIN9_INT_TYPE_GET(x)
-#define GPIO_PIN9_INT_TYPE_SET(x) WLAN_GPIO_PIN9_INT_TYPE_SET(x)
-#define GPIO_PIN9_PAD_PULL_MSB WLAN_GPIO_PIN9_PAD_PULL_MSB
-#define GPIO_PIN9_PAD_PULL_LSB WLAN_GPIO_PIN9_PAD_PULL_LSB
-#define GPIO_PIN9_PAD_PULL_MASK WLAN_GPIO_PIN9_PAD_PULL_MASK
-#define GPIO_PIN9_PAD_PULL_GET(x) WLAN_GPIO_PIN9_PAD_PULL_GET(x)
-#define GPIO_PIN9_PAD_PULL_SET(x) WLAN_GPIO_PIN9_PAD_PULL_SET(x)
-#define GPIO_PIN9_PAD_STRENGTH_MSB WLAN_GPIO_PIN9_PAD_STRENGTH_MSB
-#define GPIO_PIN9_PAD_STRENGTH_LSB WLAN_GPIO_PIN9_PAD_STRENGTH_LSB
-#define GPIO_PIN9_PAD_STRENGTH_MASK WLAN_GPIO_PIN9_PAD_STRENGTH_MASK
-#define GPIO_PIN9_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN9_PAD_STRENGTH_GET(x)
-#define GPIO_PIN9_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN9_PAD_STRENGTH_SET(x)
-#define GPIO_PIN9_PAD_DRIVER_MSB WLAN_GPIO_PIN9_PAD_DRIVER_MSB
-#define GPIO_PIN9_PAD_DRIVER_LSB WLAN_GPIO_PIN9_PAD_DRIVER_LSB
-#define GPIO_PIN9_PAD_DRIVER_MASK WLAN_GPIO_PIN9_PAD_DRIVER_MASK
-#define GPIO_PIN9_PAD_DRIVER_GET(x) WLAN_GPIO_PIN9_PAD_DRIVER_GET(x)
-#define GPIO_PIN9_PAD_DRIVER_SET(x) WLAN_GPIO_PIN9_PAD_DRIVER_SET(x)
-#define GPIO_PIN9_SOURCE_MSB WLAN_GPIO_PIN9_SOURCE_MSB
-#define GPIO_PIN9_SOURCE_LSB WLAN_GPIO_PIN9_SOURCE_LSB
-#define GPIO_PIN9_SOURCE_MASK WLAN_GPIO_PIN9_SOURCE_MASK
-#define GPIO_PIN9_SOURCE_GET(x) WLAN_GPIO_PIN9_SOURCE_GET(x)
-#define GPIO_PIN9_SOURCE_SET(x) WLAN_GPIO_PIN9_SOURCE_SET(x)
-#define GPIO_PIN10_ADDRESS WLAN_GPIO_PIN10_ADDRESS
-#define GPIO_PIN10_OFFSET WLAN_GPIO_PIN10_OFFSET
-#define GPIO_PIN10_CONFIG_MSB WLAN_GPIO_PIN10_CONFIG_MSB
-#define GPIO_PIN10_CONFIG_LSB WLAN_GPIO_PIN10_CONFIG_LSB
-#define GPIO_PIN10_CONFIG_MASK WLAN_GPIO_PIN10_CONFIG_MASK
-#define GPIO_PIN10_CONFIG_GET(x) WLAN_GPIO_PIN10_CONFIG_GET(x)
-#define GPIO_PIN10_CONFIG_SET(x) WLAN_GPIO_PIN10_CONFIG_SET(x)
-#define GPIO_PIN10_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN10_WAKEUP_ENABLE_MSB
-#define GPIO_PIN10_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN10_WAKEUP_ENABLE_LSB
-#define GPIO_PIN10_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN10_WAKEUP_ENABLE_MASK
-#define GPIO_PIN10_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN10_WAKEUP_ENABLE_GET(x)
-#define GPIO_PIN10_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN10_WAKEUP_ENABLE_SET(x)
-#define GPIO_PIN10_INT_TYPE_MSB WLAN_GPIO_PIN10_INT_TYPE_MSB
-#define GPIO_PIN10_INT_TYPE_LSB WLAN_GPIO_PIN10_INT_TYPE_LSB
-#define GPIO_PIN10_INT_TYPE_MASK WLAN_GPIO_PIN10_INT_TYPE_MASK
-#define GPIO_PIN10_INT_TYPE_GET(x) WLAN_GPIO_PIN10_INT_TYPE_GET(x)
-#define GPIO_PIN10_INT_TYPE_SET(x) WLAN_GPIO_PIN10_INT_TYPE_SET(x)
-#define GPIO_PIN10_PAD_PULL_MSB WLAN_GPIO_PIN10_PAD_PULL_MSB
-#define GPIO_PIN10_PAD_PULL_LSB WLAN_GPIO_PIN10_PAD_PULL_LSB
-#define GPIO_PIN10_PAD_PULL_MASK WLAN_GPIO_PIN10_PAD_PULL_MASK
-#define GPIO_PIN10_PAD_PULL_GET(x) WLAN_GPIO_PIN10_PAD_PULL_GET(x)
-#define GPIO_PIN10_PAD_PULL_SET(x) WLAN_GPIO_PIN10_PAD_PULL_SET(x)
-#define GPIO_PIN10_PAD_STRENGTH_MSB WLAN_GPIO_PIN10_PAD_STRENGTH_MSB
-#define GPIO_PIN10_PAD_STRENGTH_LSB WLAN_GPIO_PIN10_PAD_STRENGTH_LSB
-#define GPIO_PIN10_PAD_STRENGTH_MASK WLAN_GPIO_PIN10_PAD_STRENGTH_MASK
-#define GPIO_PIN10_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN10_PAD_STRENGTH_GET(x)
-#define GPIO_PIN10_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN10_PAD_STRENGTH_SET(x)
-#define GPIO_PIN10_PAD_DRIVER_MSB WLAN_GPIO_PIN10_PAD_DRIVER_MSB
-#define GPIO_PIN10_PAD_DRIVER_LSB WLAN_GPIO_PIN10_PAD_DRIVER_LSB
-#define GPIO_PIN10_PAD_DRIVER_MASK WLAN_GPIO_PIN10_PAD_DRIVER_MASK
-#define GPIO_PIN10_PAD_DRIVER_GET(x) WLAN_GPIO_PIN10_PAD_DRIVER_GET(x)
-#define GPIO_PIN10_PAD_DRIVER_SET(x) WLAN_GPIO_PIN10_PAD_DRIVER_SET(x)
-#define GPIO_PIN10_SOURCE_MSB WLAN_GPIO_PIN10_SOURCE_MSB
-#define GPIO_PIN10_SOURCE_LSB WLAN_GPIO_PIN10_SOURCE_LSB
-#define GPIO_PIN10_SOURCE_MASK WLAN_GPIO_PIN10_SOURCE_MASK
-#define GPIO_PIN10_SOURCE_GET(x) WLAN_GPIO_PIN10_SOURCE_GET(x)
-#define GPIO_PIN10_SOURCE_SET(x) WLAN_GPIO_PIN10_SOURCE_SET(x)
-#define GPIO_PIN11_ADDRESS WLAN_GPIO_PIN11_ADDRESS
-#define GPIO_PIN11_OFFSET WLAN_GPIO_PIN11_OFFSET
-#define GPIO_PIN11_CONFIG_MSB WLAN_GPIO_PIN11_CONFIG_MSB
-#define GPIO_PIN11_CONFIG_LSB WLAN_GPIO_PIN11_CONFIG_LSB
-#define GPIO_PIN11_CONFIG_MASK WLAN_GPIO_PIN11_CONFIG_MASK
-#define GPIO_PIN11_CONFIG_GET(x) WLAN_GPIO_PIN11_CONFIG_GET(x)
-#define GPIO_PIN11_CONFIG_SET(x) WLAN_GPIO_PIN11_CONFIG_SET(x)
-#define GPIO_PIN11_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN11_WAKEUP_ENABLE_MSB
-#define GPIO_PIN11_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN11_WAKEUP_ENABLE_LSB
-#define GPIO_PIN11_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN11_WAKEUP_ENABLE_MASK
-#define GPIO_PIN11_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN11_WAKEUP_ENABLE_GET(x)
-#define GPIO_PIN11_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN11_WAKEUP_ENABLE_SET(x)
-#define GPIO_PIN11_INT_TYPE_MSB WLAN_GPIO_PIN11_INT_TYPE_MSB
-#define GPIO_PIN11_INT_TYPE_LSB WLAN_GPIO_PIN11_INT_TYPE_LSB
-#define GPIO_PIN11_INT_TYPE_MASK WLAN_GPIO_PIN11_INT_TYPE_MASK
-#define GPIO_PIN11_INT_TYPE_GET(x) WLAN_GPIO_PIN11_INT_TYPE_GET(x)
-#define GPIO_PIN11_INT_TYPE_SET(x) WLAN_GPIO_PIN11_INT_TYPE_SET(x)
-#define GPIO_PIN11_PAD_PULL_MSB WLAN_GPIO_PIN11_PAD_PULL_MSB
-#define GPIO_PIN11_PAD_PULL_LSB WLAN_GPIO_PIN11_PAD_PULL_LSB
-#define GPIO_PIN11_PAD_PULL_MASK WLAN_GPIO_PIN11_PAD_PULL_MASK
-#define GPIO_PIN11_PAD_PULL_GET(x) WLAN_GPIO_PIN11_PAD_PULL_GET(x)
-#define GPIO_PIN11_PAD_PULL_SET(x) WLAN_GPIO_PIN11_PAD_PULL_SET(x)
-#define GPIO_PIN11_PAD_STRENGTH_MSB WLAN_GPIO_PIN11_PAD_STRENGTH_MSB
-#define GPIO_PIN11_PAD_STRENGTH_LSB WLAN_GPIO_PIN11_PAD_STRENGTH_LSB
-#define GPIO_PIN11_PAD_STRENGTH_MASK WLAN_GPIO_PIN11_PAD_STRENGTH_MASK
-#define GPIO_PIN11_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN11_PAD_STRENGTH_GET(x)
-#define GPIO_PIN11_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN11_PAD_STRENGTH_SET(x)
-#define GPIO_PIN11_PAD_DRIVER_MSB WLAN_GPIO_PIN11_PAD_DRIVER_MSB
-#define GPIO_PIN11_PAD_DRIVER_LSB WLAN_GPIO_PIN11_PAD_DRIVER_LSB
-#define GPIO_PIN11_PAD_DRIVER_MASK WLAN_GPIO_PIN11_PAD_DRIVER_MASK
-#define GPIO_PIN11_PAD_DRIVER_GET(x) WLAN_GPIO_PIN11_PAD_DRIVER_GET(x)
-#define GPIO_PIN11_PAD_DRIVER_SET(x) WLAN_GPIO_PIN11_PAD_DRIVER_SET(x)
-#define GPIO_PIN11_SOURCE_MSB WLAN_GPIO_PIN11_SOURCE_MSB
-#define GPIO_PIN11_SOURCE_LSB WLAN_GPIO_PIN11_SOURCE_LSB
-#define GPIO_PIN11_SOURCE_MASK WLAN_GPIO_PIN11_SOURCE_MASK
-#define GPIO_PIN11_SOURCE_GET(x) WLAN_GPIO_PIN11_SOURCE_GET(x)
-#define GPIO_PIN11_SOURCE_SET(x) WLAN_GPIO_PIN11_SOURCE_SET(x)
-#define GPIO_PIN12_ADDRESS WLAN_GPIO_PIN12_ADDRESS
-#define GPIO_PIN12_OFFSET WLAN_GPIO_PIN12_OFFSET
-#define GPIO_PIN12_CONFIG_MSB WLAN_GPIO_PIN12_CONFIG_MSB
-#define GPIO_PIN12_CONFIG_LSB WLAN_GPIO_PIN12_CONFIG_LSB
-#define GPIO_PIN12_CONFIG_MASK WLAN_GPIO_PIN12_CONFIG_MASK
-#define GPIO_PIN12_CONFIG_GET(x) WLAN_GPIO_PIN12_CONFIG_GET(x)
-#define GPIO_PIN12_CONFIG_SET(x) WLAN_GPIO_PIN12_CONFIG_SET(x)
-#define GPIO_PIN12_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN12_WAKEUP_ENABLE_MSB
-#define GPIO_PIN12_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN12_WAKEUP_ENABLE_LSB
-#define GPIO_PIN12_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN12_WAKEUP_ENABLE_MASK
-#define GPIO_PIN12_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN12_WAKEUP_ENABLE_GET(x)
-#define GPIO_PIN12_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN12_WAKEUP_ENABLE_SET(x)
-#define GPIO_PIN12_INT_TYPE_MSB WLAN_GPIO_PIN12_INT_TYPE_MSB
-#define GPIO_PIN12_INT_TYPE_LSB WLAN_GPIO_PIN12_INT_TYPE_LSB
-#define GPIO_PIN12_INT_TYPE_MASK WLAN_GPIO_PIN12_INT_TYPE_MASK
-#define GPIO_PIN12_INT_TYPE_GET(x) WLAN_GPIO_PIN12_INT_TYPE_GET(x)
-#define GPIO_PIN12_INT_TYPE_SET(x) WLAN_GPIO_PIN12_INT_TYPE_SET(x)
-#define GPIO_PIN12_PAD_PULL_MSB WLAN_GPIO_PIN12_PAD_PULL_MSB
-#define GPIO_PIN12_PAD_PULL_LSB WLAN_GPIO_PIN12_PAD_PULL_LSB
-#define GPIO_PIN12_PAD_PULL_MASK WLAN_GPIO_PIN12_PAD_PULL_MASK
-#define GPIO_PIN12_PAD_PULL_GET(x) WLAN_GPIO_PIN12_PAD_PULL_GET(x)
-#define GPIO_PIN12_PAD_PULL_SET(x) WLAN_GPIO_PIN12_PAD_PULL_SET(x)
-#define GPIO_PIN12_PAD_STRENGTH_MSB WLAN_GPIO_PIN12_PAD_STRENGTH_MSB
-#define GPIO_PIN12_PAD_STRENGTH_LSB WLAN_GPIO_PIN12_PAD_STRENGTH_LSB
-#define GPIO_PIN12_PAD_STRENGTH_MASK WLAN_GPIO_PIN12_PAD_STRENGTH_MASK
-#define GPIO_PIN12_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN12_PAD_STRENGTH_GET(x)
-#define GPIO_PIN12_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN12_PAD_STRENGTH_SET(x)
-#define GPIO_PIN12_PAD_DRIVER_MSB WLAN_GPIO_PIN12_PAD_DRIVER_MSB
-#define GPIO_PIN12_PAD_DRIVER_LSB WLAN_GPIO_PIN12_PAD_DRIVER_LSB
-#define GPIO_PIN12_PAD_DRIVER_MASK WLAN_GPIO_PIN12_PAD_DRIVER_MASK
-#define GPIO_PIN12_PAD_DRIVER_GET(x) WLAN_GPIO_PIN12_PAD_DRIVER_GET(x)
-#define GPIO_PIN12_PAD_DRIVER_SET(x) WLAN_GPIO_PIN12_PAD_DRIVER_SET(x)
-#define GPIO_PIN12_SOURCE_MSB WLAN_GPIO_PIN12_SOURCE_MSB
-#define GPIO_PIN12_SOURCE_LSB WLAN_GPIO_PIN12_SOURCE_LSB
-#define GPIO_PIN12_SOURCE_MASK WLAN_GPIO_PIN12_SOURCE_MASK
-#define GPIO_PIN12_SOURCE_GET(x) WLAN_GPIO_PIN12_SOURCE_GET(x)
-#define GPIO_PIN12_SOURCE_SET(x) WLAN_GPIO_PIN12_SOURCE_SET(x)
-#define GPIO_PIN13_ADDRESS WLAN_GPIO_PIN13_ADDRESS
-#define GPIO_PIN13_OFFSET WLAN_GPIO_PIN13_OFFSET
-#define GPIO_PIN13_CONFIG_MSB WLAN_GPIO_PIN13_CONFIG_MSB
-#define GPIO_PIN13_CONFIG_LSB WLAN_GPIO_PIN13_CONFIG_LSB
-#define GPIO_PIN13_CONFIG_MASK WLAN_GPIO_PIN13_CONFIG_MASK
-#define GPIO_PIN13_CONFIG_GET(x) WLAN_GPIO_PIN13_CONFIG_GET(x)
-#define GPIO_PIN13_CONFIG_SET(x) WLAN_GPIO_PIN13_CONFIG_SET(x)
-#define GPIO_PIN13_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN13_WAKEUP_ENABLE_MSB
-#define GPIO_PIN13_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN13_WAKEUP_ENABLE_LSB
-#define GPIO_PIN13_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN13_WAKEUP_ENABLE_MASK
-#define GPIO_PIN13_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN13_WAKEUP_ENABLE_GET(x)
-#define GPIO_PIN13_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN13_WAKEUP_ENABLE_SET(x)
-#define GPIO_PIN13_INT_TYPE_MSB WLAN_GPIO_PIN13_INT_TYPE_MSB
-#define GPIO_PIN13_INT_TYPE_LSB WLAN_GPIO_PIN13_INT_TYPE_LSB
-#define GPIO_PIN13_INT_TYPE_MASK WLAN_GPIO_PIN13_INT_TYPE_MASK
-#define GPIO_PIN13_INT_TYPE_GET(x) WLAN_GPIO_PIN13_INT_TYPE_GET(x)
-#define GPIO_PIN13_INT_TYPE_SET(x) WLAN_GPIO_PIN13_INT_TYPE_SET(x)
-#define GPIO_PIN13_PAD_PULL_MSB WLAN_GPIO_PIN13_PAD_PULL_MSB
-#define GPIO_PIN13_PAD_PULL_LSB WLAN_GPIO_PIN13_PAD_PULL_LSB
-#define GPIO_PIN13_PAD_PULL_MASK WLAN_GPIO_PIN13_PAD_PULL_MASK
-#define GPIO_PIN13_PAD_PULL_GET(x) WLAN_GPIO_PIN13_PAD_PULL_GET(x)
-#define GPIO_PIN13_PAD_PULL_SET(x) WLAN_GPIO_PIN13_PAD_PULL_SET(x)
-#define GPIO_PIN13_PAD_STRENGTH_MSB WLAN_GPIO_PIN13_PAD_STRENGTH_MSB
-#define GPIO_PIN13_PAD_STRENGTH_LSB WLAN_GPIO_PIN13_PAD_STRENGTH_LSB
-#define GPIO_PIN13_PAD_STRENGTH_MASK WLAN_GPIO_PIN13_PAD_STRENGTH_MASK
-#define GPIO_PIN13_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN13_PAD_STRENGTH_GET(x)
-#define GPIO_PIN13_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN13_PAD_STRENGTH_SET(x)
-#define GPIO_PIN13_PAD_DRIVER_MSB WLAN_GPIO_PIN13_PAD_DRIVER_MSB
-#define GPIO_PIN13_PAD_DRIVER_LSB WLAN_GPIO_PIN13_PAD_DRIVER_LSB
-#define GPIO_PIN13_PAD_DRIVER_MASK WLAN_GPIO_PIN13_PAD_DRIVER_MASK
-#define GPIO_PIN13_PAD_DRIVER_GET(x) WLAN_GPIO_PIN13_PAD_DRIVER_GET(x)
-#define GPIO_PIN13_PAD_DRIVER_SET(x) WLAN_GPIO_PIN13_PAD_DRIVER_SET(x)
-#define GPIO_PIN13_SOURCE_MSB WLAN_GPIO_PIN13_SOURCE_MSB
-#define GPIO_PIN13_SOURCE_LSB WLAN_GPIO_PIN13_SOURCE_LSB
-#define GPIO_PIN13_SOURCE_MASK WLAN_GPIO_PIN13_SOURCE_MASK
-#define GPIO_PIN13_SOURCE_GET(x) WLAN_GPIO_PIN13_SOURCE_GET(x)
-#define GPIO_PIN13_SOURCE_SET(x) WLAN_GPIO_PIN13_SOURCE_SET(x)
-#define GPIO_PIN14_ADDRESS WLAN_GPIO_PIN14_ADDRESS
-#define GPIO_PIN14_OFFSET WLAN_GPIO_PIN14_OFFSET
-#define GPIO_PIN14_CONFIG_MSB WLAN_GPIO_PIN14_CONFIG_MSB
-#define GPIO_PIN14_CONFIG_LSB WLAN_GPIO_PIN14_CONFIG_LSB
-#define GPIO_PIN14_CONFIG_MASK WLAN_GPIO_PIN14_CONFIG_MASK
-#define GPIO_PIN14_CONFIG_GET(x) WLAN_GPIO_PIN14_CONFIG_GET(x)
-#define GPIO_PIN14_CONFIG_SET(x) WLAN_GPIO_PIN14_CONFIG_SET(x)
-#define GPIO_PIN14_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN14_WAKEUP_ENABLE_MSB
-#define GPIO_PIN14_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN14_WAKEUP_ENABLE_LSB
-#define GPIO_PIN14_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN14_WAKEUP_ENABLE_MASK
-#define GPIO_PIN14_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN14_WAKEUP_ENABLE_GET(x)
-#define GPIO_PIN14_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN14_WAKEUP_ENABLE_SET(x)
-#define GPIO_PIN14_INT_TYPE_MSB WLAN_GPIO_PIN14_INT_TYPE_MSB
-#define GPIO_PIN14_INT_TYPE_LSB WLAN_GPIO_PIN14_INT_TYPE_LSB
-#define GPIO_PIN14_INT_TYPE_MASK WLAN_GPIO_PIN14_INT_TYPE_MASK
-#define GPIO_PIN14_INT_TYPE_GET(x) WLAN_GPIO_PIN14_INT_TYPE_GET(x)
-#define GPIO_PIN14_INT_TYPE_SET(x) WLAN_GPIO_PIN14_INT_TYPE_SET(x)
-#define GPIO_PIN14_PAD_PULL_MSB WLAN_GPIO_PIN14_PAD_PULL_MSB
-#define GPIO_PIN14_PAD_PULL_LSB WLAN_GPIO_PIN14_PAD_PULL_LSB
-#define GPIO_PIN14_PAD_PULL_MASK WLAN_GPIO_PIN14_PAD_PULL_MASK
-#define GPIO_PIN14_PAD_PULL_GET(x) WLAN_GPIO_PIN14_PAD_PULL_GET(x)
-#define GPIO_PIN14_PAD_PULL_SET(x) WLAN_GPIO_PIN14_PAD_PULL_SET(x)
-#define GPIO_PIN14_PAD_STRENGTH_MSB WLAN_GPIO_PIN14_PAD_STRENGTH_MSB
-#define GPIO_PIN14_PAD_STRENGTH_LSB WLAN_GPIO_PIN14_PAD_STRENGTH_LSB
-#define GPIO_PIN14_PAD_STRENGTH_MASK WLAN_GPIO_PIN14_PAD_STRENGTH_MASK
-#define GPIO_PIN14_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN14_PAD_STRENGTH_GET(x)
-#define GPIO_PIN14_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN14_PAD_STRENGTH_SET(x)
-#define GPIO_PIN14_PAD_DRIVER_MSB WLAN_GPIO_PIN14_PAD_DRIVER_MSB
-#define GPIO_PIN14_PAD_DRIVER_LSB WLAN_GPIO_PIN14_PAD_DRIVER_LSB
-#define GPIO_PIN14_PAD_DRIVER_MASK WLAN_GPIO_PIN14_PAD_DRIVER_MASK
-#define GPIO_PIN14_PAD_DRIVER_GET(x) WLAN_GPIO_PIN14_PAD_DRIVER_GET(x)
-#define GPIO_PIN14_PAD_DRIVER_SET(x) WLAN_GPIO_PIN14_PAD_DRIVER_SET(x)
-#define GPIO_PIN14_SOURCE_MSB WLAN_GPIO_PIN14_SOURCE_MSB
-#define GPIO_PIN14_SOURCE_LSB WLAN_GPIO_PIN14_SOURCE_LSB
-#define GPIO_PIN14_SOURCE_MASK WLAN_GPIO_PIN14_SOURCE_MASK
-#define GPIO_PIN14_SOURCE_GET(x) WLAN_GPIO_PIN14_SOURCE_GET(x)
-#define GPIO_PIN14_SOURCE_SET(x) WLAN_GPIO_PIN14_SOURCE_SET(x)
-#define GPIO_PIN15_ADDRESS WLAN_GPIO_PIN15_ADDRESS
-#define GPIO_PIN15_OFFSET WLAN_GPIO_PIN15_OFFSET
-#define GPIO_PIN15_CONFIG_MSB WLAN_GPIO_PIN15_CONFIG_MSB
-#define GPIO_PIN15_CONFIG_LSB WLAN_GPIO_PIN15_CONFIG_LSB
-#define GPIO_PIN15_CONFIG_MASK WLAN_GPIO_PIN15_CONFIG_MASK
-#define GPIO_PIN15_CONFIG_GET(x) WLAN_GPIO_PIN15_CONFIG_GET(x)
-#define GPIO_PIN15_CONFIG_SET(x) WLAN_GPIO_PIN15_CONFIG_SET(x)
-#define GPIO_PIN15_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN15_WAKEUP_ENABLE_MSB
-#define GPIO_PIN15_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN15_WAKEUP_ENABLE_LSB
-#define GPIO_PIN15_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN15_WAKEUP_ENABLE_MASK
-#define GPIO_PIN15_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN15_WAKEUP_ENABLE_GET(x)
-#define GPIO_PIN15_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN15_WAKEUP_ENABLE_SET(x)
-#define GPIO_PIN15_INT_TYPE_MSB WLAN_GPIO_PIN15_INT_TYPE_MSB
-#define GPIO_PIN15_INT_TYPE_LSB WLAN_GPIO_PIN15_INT_TYPE_LSB
-#define GPIO_PIN15_INT_TYPE_MASK WLAN_GPIO_PIN15_INT_TYPE_MASK
-#define GPIO_PIN15_INT_TYPE_GET(x) WLAN_GPIO_PIN15_INT_TYPE_GET(x)
-#define GPIO_PIN15_INT_TYPE_SET(x) WLAN_GPIO_PIN15_INT_TYPE_SET(x)
-#define GPIO_PIN15_PAD_PULL_MSB WLAN_GPIO_PIN15_PAD_PULL_MSB
-#define GPIO_PIN15_PAD_PULL_LSB WLAN_GPIO_PIN15_PAD_PULL_LSB
-#define GPIO_PIN15_PAD_PULL_MASK WLAN_GPIO_PIN15_PAD_PULL_MASK
-#define GPIO_PIN15_PAD_PULL_GET(x) WLAN_GPIO_PIN15_PAD_PULL_GET(x)
-#define GPIO_PIN15_PAD_PULL_SET(x) WLAN_GPIO_PIN15_PAD_PULL_SET(x)
-#define GPIO_PIN15_PAD_STRENGTH_MSB WLAN_GPIO_PIN15_PAD_STRENGTH_MSB
-#define GPIO_PIN15_PAD_STRENGTH_LSB WLAN_GPIO_PIN15_PAD_STRENGTH_LSB
-#define GPIO_PIN15_PAD_STRENGTH_MASK WLAN_GPIO_PIN15_PAD_STRENGTH_MASK
-#define GPIO_PIN15_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN15_PAD_STRENGTH_GET(x)
-#define GPIO_PIN15_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN15_PAD_STRENGTH_SET(x)
-#define GPIO_PIN15_PAD_DRIVER_MSB WLAN_GPIO_PIN15_PAD_DRIVER_MSB
-#define GPIO_PIN15_PAD_DRIVER_LSB WLAN_GPIO_PIN15_PAD_DRIVER_LSB
-#define GPIO_PIN15_PAD_DRIVER_MASK WLAN_GPIO_PIN15_PAD_DRIVER_MASK
-#define GPIO_PIN15_PAD_DRIVER_GET(x) WLAN_GPIO_PIN15_PAD_DRIVER_GET(x)
-#define GPIO_PIN15_PAD_DRIVER_SET(x) WLAN_GPIO_PIN15_PAD_DRIVER_SET(x)
-#define GPIO_PIN15_SOURCE_MSB WLAN_GPIO_PIN15_SOURCE_MSB
-#define GPIO_PIN15_SOURCE_LSB WLAN_GPIO_PIN15_SOURCE_LSB
-#define GPIO_PIN15_SOURCE_MASK WLAN_GPIO_PIN15_SOURCE_MASK
-#define GPIO_PIN15_SOURCE_GET(x) WLAN_GPIO_PIN15_SOURCE_GET(x)
-#define GPIO_PIN15_SOURCE_SET(x) WLAN_GPIO_PIN15_SOURCE_SET(x)
-#define GPIO_PIN16_ADDRESS WLAN_GPIO_PIN16_ADDRESS
-#define GPIO_PIN16_OFFSET WLAN_GPIO_PIN16_OFFSET
-#define GPIO_PIN16_CONFIG_MSB WLAN_GPIO_PIN16_CONFIG_MSB
-#define GPIO_PIN16_CONFIG_LSB WLAN_GPIO_PIN16_CONFIG_LSB
-#define GPIO_PIN16_CONFIG_MASK WLAN_GPIO_PIN16_CONFIG_MASK
-#define GPIO_PIN16_CONFIG_GET(x) WLAN_GPIO_PIN16_CONFIG_GET(x)
-#define GPIO_PIN16_CONFIG_SET(x) WLAN_GPIO_PIN16_CONFIG_SET(x)
-#define GPIO_PIN16_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN16_WAKEUP_ENABLE_MSB
-#define GPIO_PIN16_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN16_WAKEUP_ENABLE_LSB
-#define GPIO_PIN16_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN16_WAKEUP_ENABLE_MASK
-#define GPIO_PIN16_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN16_WAKEUP_ENABLE_GET(x)
-#define GPIO_PIN16_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN16_WAKEUP_ENABLE_SET(x)
-#define GPIO_PIN16_INT_TYPE_MSB WLAN_GPIO_PIN16_INT_TYPE_MSB
-#define GPIO_PIN16_INT_TYPE_LSB WLAN_GPIO_PIN16_INT_TYPE_LSB
-#define GPIO_PIN16_INT_TYPE_MASK WLAN_GPIO_PIN16_INT_TYPE_MASK
-#define GPIO_PIN16_INT_TYPE_GET(x) WLAN_GPIO_PIN16_INT_TYPE_GET(x)
-#define GPIO_PIN16_INT_TYPE_SET(x) WLAN_GPIO_PIN16_INT_TYPE_SET(x)
-#define GPIO_PIN16_PAD_PULL_MSB WLAN_GPIO_PIN16_PAD_PULL_MSB
-#define GPIO_PIN16_PAD_PULL_LSB WLAN_GPIO_PIN16_PAD_PULL_LSB
-#define GPIO_PIN16_PAD_PULL_MASK WLAN_GPIO_PIN16_PAD_PULL_MASK
-#define GPIO_PIN16_PAD_PULL_GET(x) WLAN_GPIO_PIN16_PAD_PULL_GET(x)
-#define GPIO_PIN16_PAD_PULL_SET(x) WLAN_GPIO_PIN16_PAD_PULL_SET(x)
-#define GPIO_PIN16_PAD_STRENGTH_MSB WLAN_GPIO_PIN16_PAD_STRENGTH_MSB
-#define GPIO_PIN16_PAD_STRENGTH_LSB WLAN_GPIO_PIN16_PAD_STRENGTH_LSB
-#define GPIO_PIN16_PAD_STRENGTH_MASK WLAN_GPIO_PIN16_PAD_STRENGTH_MASK
-#define GPIO_PIN16_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN16_PAD_STRENGTH_GET(x)
-#define GPIO_PIN16_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN16_PAD_STRENGTH_SET(x)
-#define GPIO_PIN16_PAD_DRIVER_MSB WLAN_GPIO_PIN16_PAD_DRIVER_MSB
-#define GPIO_PIN16_PAD_DRIVER_LSB WLAN_GPIO_PIN16_PAD_DRIVER_LSB
-#define GPIO_PIN16_PAD_DRIVER_MASK WLAN_GPIO_PIN16_PAD_DRIVER_MASK
-#define GPIO_PIN16_PAD_DRIVER_GET(x) WLAN_GPIO_PIN16_PAD_DRIVER_GET(x)
-#define GPIO_PIN16_PAD_DRIVER_SET(x) WLAN_GPIO_PIN16_PAD_DRIVER_SET(x)
-#define GPIO_PIN16_SOURCE_MSB WLAN_GPIO_PIN16_SOURCE_MSB
-#define GPIO_PIN16_SOURCE_LSB WLAN_GPIO_PIN16_SOURCE_LSB
-#define GPIO_PIN16_SOURCE_MASK WLAN_GPIO_PIN16_SOURCE_MASK
-#define GPIO_PIN16_SOURCE_GET(x) WLAN_GPIO_PIN16_SOURCE_GET(x)
-#define GPIO_PIN16_SOURCE_SET(x) WLAN_GPIO_PIN16_SOURCE_SET(x)
-#define GPIO_PIN17_ADDRESS WLAN_GPIO_PIN17_ADDRESS
-#define GPIO_PIN17_OFFSET WLAN_GPIO_PIN17_OFFSET
-#define GPIO_PIN17_CONFIG_MSB WLAN_GPIO_PIN17_CONFIG_MSB
-#define GPIO_PIN17_CONFIG_LSB WLAN_GPIO_PIN17_CONFIG_LSB
-#define GPIO_PIN17_CONFIG_MASK WLAN_GPIO_PIN17_CONFIG_MASK
-#define GPIO_PIN17_CONFIG_GET(x) WLAN_GPIO_PIN17_CONFIG_GET(x)
-#define GPIO_PIN17_CONFIG_SET(x) WLAN_GPIO_PIN17_CONFIG_SET(x)
-#define GPIO_PIN17_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN17_WAKEUP_ENABLE_MSB
-#define GPIO_PIN17_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN17_WAKEUP_ENABLE_LSB
-#define GPIO_PIN17_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN17_WAKEUP_ENABLE_MASK
-#define GPIO_PIN17_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN17_WAKEUP_ENABLE_GET(x)
-#define GPIO_PIN17_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN17_WAKEUP_ENABLE_SET(x)
-#define GPIO_PIN17_INT_TYPE_MSB WLAN_GPIO_PIN17_INT_TYPE_MSB
-#define GPIO_PIN17_INT_TYPE_LSB WLAN_GPIO_PIN17_INT_TYPE_LSB
-#define GPIO_PIN17_INT_TYPE_MASK WLAN_GPIO_PIN17_INT_TYPE_MASK
-#define GPIO_PIN17_INT_TYPE_GET(x) WLAN_GPIO_PIN17_INT_TYPE_GET(x)
-#define GPIO_PIN17_INT_TYPE_SET(x) WLAN_GPIO_PIN17_INT_TYPE_SET(x)
-#define GPIO_PIN17_PAD_PULL_MSB WLAN_GPIO_PIN17_PAD_PULL_MSB
-#define GPIO_PIN17_PAD_PULL_LSB WLAN_GPIO_PIN17_PAD_PULL_LSB
-#define GPIO_PIN17_PAD_PULL_MASK WLAN_GPIO_PIN17_PAD_PULL_MASK
-#define GPIO_PIN17_PAD_PULL_GET(x) WLAN_GPIO_PIN17_PAD_PULL_GET(x)
-#define GPIO_PIN17_PAD_PULL_SET(x) WLAN_GPIO_PIN17_PAD_PULL_SET(x)
-#define GPIO_PIN17_PAD_STRENGTH_MSB WLAN_GPIO_PIN17_PAD_STRENGTH_MSB
-#define GPIO_PIN17_PAD_STRENGTH_LSB WLAN_GPIO_PIN17_PAD_STRENGTH_LSB
-#define GPIO_PIN17_PAD_STRENGTH_MASK WLAN_GPIO_PIN17_PAD_STRENGTH_MASK
-#define GPIO_PIN17_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN17_PAD_STRENGTH_GET(x)
-#define GPIO_PIN17_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN17_PAD_STRENGTH_SET(x)
-#define GPIO_PIN17_PAD_DRIVER_MSB WLAN_GPIO_PIN17_PAD_DRIVER_MSB
-#define GPIO_PIN17_PAD_DRIVER_LSB WLAN_GPIO_PIN17_PAD_DRIVER_LSB
-#define GPIO_PIN17_PAD_DRIVER_MASK WLAN_GPIO_PIN17_PAD_DRIVER_MASK
-#define GPIO_PIN17_PAD_DRIVER_GET(x) WLAN_GPIO_PIN17_PAD_DRIVER_GET(x)
-#define GPIO_PIN17_PAD_DRIVER_SET(x) WLAN_GPIO_PIN17_PAD_DRIVER_SET(x)
-#define GPIO_PIN17_SOURCE_MSB WLAN_GPIO_PIN17_SOURCE_MSB
-#define GPIO_PIN17_SOURCE_LSB WLAN_GPIO_PIN17_SOURCE_LSB
-#define GPIO_PIN17_SOURCE_MASK WLAN_GPIO_PIN17_SOURCE_MASK
-#define GPIO_PIN17_SOURCE_GET(x) WLAN_GPIO_PIN17_SOURCE_GET(x)
-#define GPIO_PIN17_SOURCE_SET(x) WLAN_GPIO_PIN17_SOURCE_SET(x)
-#define GPIO_PIN18_ADDRESS WLAN_GPIO_PIN18_ADDRESS
-#define GPIO_PIN18_OFFSET WLAN_GPIO_PIN18_OFFSET
-#define GPIO_PIN18_CONFIG_MSB WLAN_GPIO_PIN18_CONFIG_MSB
-#define GPIO_PIN18_CONFIG_LSB WLAN_GPIO_PIN18_CONFIG_LSB
-#define GPIO_PIN18_CONFIG_MASK WLAN_GPIO_PIN18_CONFIG_MASK
-#define GPIO_PIN18_CONFIG_GET(x) WLAN_GPIO_PIN18_CONFIG_GET(x)
-#define GPIO_PIN18_CONFIG_SET(x) WLAN_GPIO_PIN18_CONFIG_SET(x)
-#define GPIO_PIN18_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN18_WAKEUP_ENABLE_MSB
-#define GPIO_PIN18_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN18_WAKEUP_ENABLE_LSB
-#define GPIO_PIN18_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN18_WAKEUP_ENABLE_MASK
-#define GPIO_PIN18_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN18_WAKEUP_ENABLE_GET(x)
-#define GPIO_PIN18_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN18_WAKEUP_ENABLE_SET(x)
-#define GPIO_PIN18_INT_TYPE_MSB WLAN_GPIO_PIN18_INT_TYPE_MSB
-#define GPIO_PIN18_INT_TYPE_LSB WLAN_GPIO_PIN18_INT_TYPE_LSB
-#define GPIO_PIN18_INT_TYPE_MASK WLAN_GPIO_PIN18_INT_TYPE_MASK
-#define GPIO_PIN18_INT_TYPE_GET(x) WLAN_GPIO_PIN18_INT_TYPE_GET(x)
-#define GPIO_PIN18_INT_TYPE_SET(x) WLAN_GPIO_PIN18_INT_TYPE_SET(x)
-#define GPIO_PIN18_PAD_PULL_MSB WLAN_GPIO_PIN18_PAD_PULL_MSB
-#define GPIO_PIN18_PAD_PULL_LSB WLAN_GPIO_PIN18_PAD_PULL_LSB
-#define GPIO_PIN18_PAD_PULL_MASK WLAN_GPIO_PIN18_PAD_PULL_MASK
-#define GPIO_PIN18_PAD_PULL_GET(x) WLAN_GPIO_PIN18_PAD_PULL_GET(x)
-#define GPIO_PIN18_PAD_PULL_SET(x) WLAN_GPIO_PIN18_PAD_PULL_SET(x)
-#define GPIO_PIN18_PAD_STRENGTH_MSB WLAN_GPIO_PIN18_PAD_STRENGTH_MSB
-#define GPIO_PIN18_PAD_STRENGTH_LSB WLAN_GPIO_PIN18_PAD_STRENGTH_LSB
-#define GPIO_PIN18_PAD_STRENGTH_MASK WLAN_GPIO_PIN18_PAD_STRENGTH_MASK
-#define GPIO_PIN18_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN18_PAD_STRENGTH_GET(x)
-#define GPIO_PIN18_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN18_PAD_STRENGTH_SET(x)
-#define GPIO_PIN18_PAD_DRIVER_MSB WLAN_GPIO_PIN18_PAD_DRIVER_MSB
-#define GPIO_PIN18_PAD_DRIVER_LSB WLAN_GPIO_PIN18_PAD_DRIVER_LSB
-#define GPIO_PIN18_PAD_DRIVER_MASK WLAN_GPIO_PIN18_PAD_DRIVER_MASK
-#define GPIO_PIN18_PAD_DRIVER_GET(x) WLAN_GPIO_PIN18_PAD_DRIVER_GET(x)
-#define GPIO_PIN18_PAD_DRIVER_SET(x) WLAN_GPIO_PIN18_PAD_DRIVER_SET(x)
-#define GPIO_PIN18_SOURCE_MSB WLAN_GPIO_PIN18_SOURCE_MSB
-#define GPIO_PIN18_SOURCE_LSB WLAN_GPIO_PIN18_SOURCE_LSB
-#define GPIO_PIN18_SOURCE_MASK WLAN_GPIO_PIN18_SOURCE_MASK
-#define GPIO_PIN18_SOURCE_GET(x) WLAN_GPIO_PIN18_SOURCE_GET(x)
-#define GPIO_PIN18_SOURCE_SET(x) WLAN_GPIO_PIN18_SOURCE_SET(x)
-#define GPIO_PIN19_ADDRESS WLAN_GPIO_PIN19_ADDRESS
-#define GPIO_PIN19_OFFSET WLAN_GPIO_PIN19_OFFSET
-#define GPIO_PIN19_CONFIG_MSB WLAN_GPIO_PIN19_CONFIG_MSB
-#define GPIO_PIN19_CONFIG_LSB WLAN_GPIO_PIN19_CONFIG_LSB
-#define GPIO_PIN19_CONFIG_MASK WLAN_GPIO_PIN19_CONFIG_MASK
-#define GPIO_PIN19_CONFIG_GET(x) WLAN_GPIO_PIN19_CONFIG_GET(x)
-#define GPIO_PIN19_CONFIG_SET(x) WLAN_GPIO_PIN19_CONFIG_SET(x)
-#define GPIO_PIN19_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN19_WAKEUP_ENABLE_MSB
-#define GPIO_PIN19_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN19_WAKEUP_ENABLE_LSB
-#define GPIO_PIN19_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN19_WAKEUP_ENABLE_MASK
-#define GPIO_PIN19_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN19_WAKEUP_ENABLE_GET(x)
-#define GPIO_PIN19_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN19_WAKEUP_ENABLE_SET(x)
-#define GPIO_PIN19_INT_TYPE_MSB WLAN_GPIO_PIN19_INT_TYPE_MSB
-#define GPIO_PIN19_INT_TYPE_LSB WLAN_GPIO_PIN19_INT_TYPE_LSB
-#define GPIO_PIN19_INT_TYPE_MASK WLAN_GPIO_PIN19_INT_TYPE_MASK
-#define GPIO_PIN19_INT_TYPE_GET(x) WLAN_GPIO_PIN19_INT_TYPE_GET(x)
-#define GPIO_PIN19_INT_TYPE_SET(x) WLAN_GPIO_PIN19_INT_TYPE_SET(x)
-#define GPIO_PIN19_PAD_PULL_MSB WLAN_GPIO_PIN19_PAD_PULL_MSB
-#define GPIO_PIN19_PAD_PULL_LSB WLAN_GPIO_PIN19_PAD_PULL_LSB
-#define GPIO_PIN19_PAD_PULL_MASK WLAN_GPIO_PIN19_PAD_PULL_MASK
-#define GPIO_PIN19_PAD_PULL_GET(x) WLAN_GPIO_PIN19_PAD_PULL_GET(x)
-#define GPIO_PIN19_PAD_PULL_SET(x) WLAN_GPIO_PIN19_PAD_PULL_SET(x)
-#define GPIO_PIN19_PAD_STRENGTH_MSB WLAN_GPIO_PIN19_PAD_STRENGTH_MSB
-#define GPIO_PIN19_PAD_STRENGTH_LSB WLAN_GPIO_PIN19_PAD_STRENGTH_LSB
-#define GPIO_PIN19_PAD_STRENGTH_MASK WLAN_GPIO_PIN19_PAD_STRENGTH_MASK
-#define GPIO_PIN19_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN19_PAD_STRENGTH_GET(x)
-#define GPIO_PIN19_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN19_PAD_STRENGTH_SET(x)
-#define GPIO_PIN19_PAD_DRIVER_MSB WLAN_GPIO_PIN19_PAD_DRIVER_MSB
-#define GPIO_PIN19_PAD_DRIVER_LSB WLAN_GPIO_PIN19_PAD_DRIVER_LSB
-#define GPIO_PIN19_PAD_DRIVER_MASK WLAN_GPIO_PIN19_PAD_DRIVER_MASK
-#define GPIO_PIN19_PAD_DRIVER_GET(x) WLAN_GPIO_PIN19_PAD_DRIVER_GET(x)
-#define GPIO_PIN19_PAD_DRIVER_SET(x) WLAN_GPIO_PIN19_PAD_DRIVER_SET(x)
-#define GPIO_PIN19_SOURCE_MSB WLAN_GPIO_PIN19_SOURCE_MSB
-#define GPIO_PIN19_SOURCE_LSB WLAN_GPIO_PIN19_SOURCE_LSB
-#define GPIO_PIN19_SOURCE_MASK WLAN_GPIO_PIN19_SOURCE_MASK
-#define GPIO_PIN19_SOURCE_GET(x) WLAN_GPIO_PIN19_SOURCE_GET(x)
-#define GPIO_PIN19_SOURCE_SET(x) WLAN_GPIO_PIN19_SOURCE_SET(x)
-#define GPIO_PIN20_ADDRESS WLAN_GPIO_PIN20_ADDRESS
-#define GPIO_PIN20_OFFSET WLAN_GPIO_PIN20_OFFSET
-#define GPIO_PIN20_CONFIG_MSB WLAN_GPIO_PIN20_CONFIG_MSB
-#define GPIO_PIN20_CONFIG_LSB WLAN_GPIO_PIN20_CONFIG_LSB
-#define GPIO_PIN20_CONFIG_MASK WLAN_GPIO_PIN20_CONFIG_MASK
-#define GPIO_PIN20_CONFIG_GET(x) WLAN_GPIO_PIN20_CONFIG_GET(x)
-#define GPIO_PIN20_CONFIG_SET(x) WLAN_GPIO_PIN20_CONFIG_SET(x)
-#define GPIO_PIN20_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN20_WAKEUP_ENABLE_MSB
-#define GPIO_PIN20_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN20_WAKEUP_ENABLE_LSB
-#define GPIO_PIN20_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN20_WAKEUP_ENABLE_MASK
-#define GPIO_PIN20_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN20_WAKEUP_ENABLE_GET(x)
-#define GPIO_PIN20_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN20_WAKEUP_ENABLE_SET(x)
-#define GPIO_PIN20_INT_TYPE_MSB WLAN_GPIO_PIN20_INT_TYPE_MSB
-#define GPIO_PIN20_INT_TYPE_LSB WLAN_GPIO_PIN20_INT_TYPE_LSB
-#define GPIO_PIN20_INT_TYPE_MASK WLAN_GPIO_PIN20_INT_TYPE_MASK
-#define GPIO_PIN20_INT_TYPE_GET(x) WLAN_GPIO_PIN20_INT_TYPE_GET(x)
-#define GPIO_PIN20_INT_TYPE_SET(x) WLAN_GPIO_PIN20_INT_TYPE_SET(x)
-#define GPIO_PIN20_PAD_PULL_MSB WLAN_GPIO_PIN20_PAD_PULL_MSB
-#define GPIO_PIN20_PAD_PULL_LSB WLAN_GPIO_PIN20_PAD_PULL_LSB
-#define GPIO_PIN20_PAD_PULL_MASK WLAN_GPIO_PIN20_PAD_PULL_MASK
-#define GPIO_PIN20_PAD_PULL_GET(x) WLAN_GPIO_PIN20_PAD_PULL_GET(x)
-#define GPIO_PIN20_PAD_PULL_SET(x) WLAN_GPIO_PIN20_PAD_PULL_SET(x)
-#define GPIO_PIN20_PAD_STRENGTH_MSB WLAN_GPIO_PIN20_PAD_STRENGTH_MSB
-#define GPIO_PIN20_PAD_STRENGTH_LSB WLAN_GPIO_PIN20_PAD_STRENGTH_LSB
-#define GPIO_PIN20_PAD_STRENGTH_MASK WLAN_GPIO_PIN20_PAD_STRENGTH_MASK
-#define GPIO_PIN20_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN20_PAD_STRENGTH_GET(x)
-#define GPIO_PIN20_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN20_PAD_STRENGTH_SET(x)
-#define GPIO_PIN20_PAD_DRIVER_MSB WLAN_GPIO_PIN20_PAD_DRIVER_MSB
-#define GPIO_PIN20_PAD_DRIVER_LSB WLAN_GPIO_PIN20_PAD_DRIVER_LSB
-#define GPIO_PIN20_PAD_DRIVER_MASK WLAN_GPIO_PIN20_PAD_DRIVER_MASK
-#define GPIO_PIN20_PAD_DRIVER_GET(x) WLAN_GPIO_PIN20_PAD_DRIVER_GET(x)
-#define GPIO_PIN20_PAD_DRIVER_SET(x) WLAN_GPIO_PIN20_PAD_DRIVER_SET(x)
-#define GPIO_PIN20_SOURCE_MSB WLAN_GPIO_PIN20_SOURCE_MSB
-#define GPIO_PIN20_SOURCE_LSB WLAN_GPIO_PIN20_SOURCE_LSB
-#define GPIO_PIN20_SOURCE_MASK WLAN_GPIO_PIN20_SOURCE_MASK
-#define GPIO_PIN20_SOURCE_GET(x) WLAN_GPIO_PIN20_SOURCE_GET(x)
-#define GPIO_PIN20_SOURCE_SET(x) WLAN_GPIO_PIN20_SOURCE_SET(x)
-#define GPIO_PIN21_ADDRESS WLAN_GPIO_PIN21_ADDRESS
-#define GPIO_PIN21_OFFSET WLAN_GPIO_PIN21_OFFSET
-#define GPIO_PIN21_CONFIG_MSB WLAN_GPIO_PIN21_CONFIG_MSB
-#define GPIO_PIN21_CONFIG_LSB WLAN_GPIO_PIN21_CONFIG_LSB
-#define GPIO_PIN21_CONFIG_MASK WLAN_GPIO_PIN21_CONFIG_MASK
-#define GPIO_PIN21_CONFIG_GET(x) WLAN_GPIO_PIN21_CONFIG_GET(x)
-#define GPIO_PIN21_CONFIG_SET(x) WLAN_GPIO_PIN21_CONFIG_SET(x)
-#define GPIO_PIN21_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN21_WAKEUP_ENABLE_MSB
-#define GPIO_PIN21_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN21_WAKEUP_ENABLE_LSB
-#define GPIO_PIN21_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN21_WAKEUP_ENABLE_MASK
-#define GPIO_PIN21_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN21_WAKEUP_ENABLE_GET(x)
-#define GPIO_PIN21_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN21_WAKEUP_ENABLE_SET(x)
-#define GPIO_PIN21_INT_TYPE_MSB WLAN_GPIO_PIN21_INT_TYPE_MSB
-#define GPIO_PIN21_INT_TYPE_LSB WLAN_GPIO_PIN21_INT_TYPE_LSB
-#define GPIO_PIN21_INT_TYPE_MASK WLAN_GPIO_PIN21_INT_TYPE_MASK
-#define GPIO_PIN21_INT_TYPE_GET(x) WLAN_GPIO_PIN21_INT_TYPE_GET(x)
-#define GPIO_PIN21_INT_TYPE_SET(x) WLAN_GPIO_PIN21_INT_TYPE_SET(x)
-#define GPIO_PIN21_PAD_PULL_MSB WLAN_GPIO_PIN21_PAD_PULL_MSB
-#define GPIO_PIN21_PAD_PULL_LSB WLAN_GPIO_PIN21_PAD_PULL_LSB
-#define GPIO_PIN21_PAD_PULL_MASK WLAN_GPIO_PIN21_PAD_PULL_MASK
-#define GPIO_PIN21_PAD_PULL_GET(x) WLAN_GPIO_PIN21_PAD_PULL_GET(x)
-#define GPIO_PIN21_PAD_PULL_SET(x) WLAN_GPIO_PIN21_PAD_PULL_SET(x)
-#define GPIO_PIN21_PAD_STRENGTH_MSB WLAN_GPIO_PIN21_PAD_STRENGTH_MSB
-#define GPIO_PIN21_PAD_STRENGTH_LSB WLAN_GPIO_PIN21_PAD_STRENGTH_LSB
-#define GPIO_PIN21_PAD_STRENGTH_MASK WLAN_GPIO_PIN21_PAD_STRENGTH_MASK
-#define GPIO_PIN21_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN21_PAD_STRENGTH_GET(x)
-#define GPIO_PIN21_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN21_PAD_STRENGTH_SET(x)
-#define GPIO_PIN21_PAD_DRIVER_MSB WLAN_GPIO_PIN21_PAD_DRIVER_MSB
-#define GPIO_PIN21_PAD_DRIVER_LSB WLAN_GPIO_PIN21_PAD_DRIVER_LSB
-#define GPIO_PIN21_PAD_DRIVER_MASK WLAN_GPIO_PIN21_PAD_DRIVER_MASK
-#define GPIO_PIN21_PAD_DRIVER_GET(x) WLAN_GPIO_PIN21_PAD_DRIVER_GET(x)
-#define GPIO_PIN21_PAD_DRIVER_SET(x) WLAN_GPIO_PIN21_PAD_DRIVER_SET(x)
-#define GPIO_PIN21_SOURCE_MSB WLAN_GPIO_PIN21_SOURCE_MSB
-#define GPIO_PIN21_SOURCE_LSB WLAN_GPIO_PIN21_SOURCE_LSB
-#define GPIO_PIN21_SOURCE_MASK WLAN_GPIO_PIN21_SOURCE_MASK
-#define GPIO_PIN21_SOURCE_GET(x) WLAN_GPIO_PIN21_SOURCE_GET(x)
-#define GPIO_PIN21_SOURCE_SET(x) WLAN_GPIO_PIN21_SOURCE_SET(x)
-#define GPIO_PIN22_ADDRESS WLAN_GPIO_PIN22_ADDRESS
-#define GPIO_PIN22_OFFSET WLAN_GPIO_PIN22_OFFSET
-#define GPIO_PIN22_CONFIG_MSB WLAN_GPIO_PIN22_CONFIG_MSB
-#define GPIO_PIN22_CONFIG_LSB WLAN_GPIO_PIN22_CONFIG_LSB
-#define GPIO_PIN22_CONFIG_MASK WLAN_GPIO_PIN22_CONFIG_MASK
-#define GPIO_PIN22_CONFIG_GET(x) WLAN_GPIO_PIN22_CONFIG_GET(x)
-#define GPIO_PIN22_CONFIG_SET(x) WLAN_GPIO_PIN22_CONFIG_SET(x)
-#define GPIO_PIN22_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN22_WAKEUP_ENABLE_MSB
-#define GPIO_PIN22_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN22_WAKEUP_ENABLE_LSB
-#define GPIO_PIN22_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN22_WAKEUP_ENABLE_MASK
-#define GPIO_PIN22_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN22_WAKEUP_ENABLE_GET(x)
-#define GPIO_PIN22_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN22_WAKEUP_ENABLE_SET(x)
-#define GPIO_PIN22_INT_TYPE_MSB WLAN_GPIO_PIN22_INT_TYPE_MSB
-#define GPIO_PIN22_INT_TYPE_LSB WLAN_GPIO_PIN22_INT_TYPE_LSB
-#define GPIO_PIN22_INT_TYPE_MASK WLAN_GPIO_PIN22_INT_TYPE_MASK
-#define GPIO_PIN22_INT_TYPE_GET(x) WLAN_GPIO_PIN22_INT_TYPE_GET(x)
-#define GPIO_PIN22_INT_TYPE_SET(x) WLAN_GPIO_PIN22_INT_TYPE_SET(x)
-#define GPIO_PIN22_PAD_PULL_MSB WLAN_GPIO_PIN22_PAD_PULL_MSB
-#define GPIO_PIN22_PAD_PULL_LSB WLAN_GPIO_PIN22_PAD_PULL_LSB
-#define GPIO_PIN22_PAD_PULL_MASK WLAN_GPIO_PIN22_PAD_PULL_MASK
-#define GPIO_PIN22_PAD_PULL_GET(x) WLAN_GPIO_PIN22_PAD_PULL_GET(x)
-#define GPIO_PIN22_PAD_PULL_SET(x) WLAN_GPIO_PIN22_PAD_PULL_SET(x)
-#define GPIO_PIN22_PAD_STRENGTH_MSB WLAN_GPIO_PIN22_PAD_STRENGTH_MSB
-#define GPIO_PIN22_PAD_STRENGTH_LSB WLAN_GPIO_PIN22_PAD_STRENGTH_LSB
-#define GPIO_PIN22_PAD_STRENGTH_MASK WLAN_GPIO_PIN22_PAD_STRENGTH_MASK
-#define GPIO_PIN22_PAD_STRENGTH_GET(x) WLAN_GPIO_PIN22_PAD_STRENGTH_GET(x)
-#define GPIO_PIN22_PAD_STRENGTH_SET(x) WLAN_GPIO_PIN22_PAD_STRENGTH_SET(x)
-#define GPIO_PIN22_PAD_DRIVER_MSB WLAN_GPIO_PIN22_PAD_DRIVER_MSB
-#define GPIO_PIN22_PAD_DRIVER_LSB WLAN_GPIO_PIN22_PAD_DRIVER_LSB
-#define GPIO_PIN22_PAD_DRIVER_MASK WLAN_GPIO_PIN22_PAD_DRIVER_MASK
-#define GPIO_PIN22_PAD_DRIVER_GET(x) WLAN_GPIO_PIN22_PAD_DRIVER_GET(x)
-#define GPIO_PIN22_PAD_DRIVER_SET(x) WLAN_GPIO_PIN22_PAD_DRIVER_SET(x)
-#define GPIO_PIN22_SOURCE_MSB WLAN_GPIO_PIN22_SOURCE_MSB
-#define GPIO_PIN22_SOURCE_LSB WLAN_GPIO_PIN22_SOURCE_LSB
-#define GPIO_PIN22_SOURCE_MASK WLAN_GPIO_PIN22_SOURCE_MASK
-#define GPIO_PIN22_SOURCE_GET(x) WLAN_GPIO_PIN22_SOURCE_GET(x)
-#define GPIO_PIN22_SOURCE_SET(x) WLAN_GPIO_PIN22_SOURCE_SET(x)
-#define GPIO_PIN23_ADDRESS WLAN_GPIO_PIN23_ADDRESS
-#define GPIO_PIN23_OFFSET WLAN_GPIO_PIN23_OFFSET
-#define GPIO_PIN23_CONFIG_MSB WLAN_GPIO_PIN23_CONFIG_MSB
-#define GPIO_PIN23_CONFIG_LSB WLAN_GPIO_PIN23_CONFIG_LSB
-#define GPIO_PIN23_CONFIG_MASK WLAN_GPIO_PIN23_CONFIG_MASK
-#define GPIO_PIN23_CONFIG_GET(x) WLAN_GPIO_PIN23_CONFIG_GET(x)
-#define GPIO_PIN23_CONFIG_SET(x) WLAN_GPIO_PIN23_CONFIG_SET(x)
-#define GPIO_PIN23_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN23_WAKEUP_ENABLE_MSB
-#define GPIO_PIN23_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN23_WAKEUP_ENABLE_LSB
-#define GPIO_PIN23_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN23_WAKEUP_ENABLE_MASK
-#define GPIO_PIN23_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN23_WAKEUP_ENABLE_GET(x)
-#define GPIO_PIN23_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN23_WAKEUP_ENABLE_SET(x)
-#define GPIO_PIN23_INT_TYPE_MSB WLAN_GPIO_PIN23_INT_TYPE_MSB
-#define GPIO_PIN23_INT_TYPE_LSB WLAN_GPIO_PIN23_INT_TYPE_LSB
-#define GPIO_PIN23_INT_TYPE_MASK WLAN_GPIO_PIN23_INT_TYPE_MASK
-#define GPIO_PIN23_INT_TYPE_GET(x) WLAN_GPIO_PIN23_INT_TYPE_GET(x)
-#define GPIO_PIN23_INT_TYPE_SET(x) WLAN_GPIO_PIN23_INT_TYPE_SET(x)
-#define GPIO_PIN23_PAD_DRIVER_MSB WLAN_GPIO_PIN23_PAD_DRIVER_MSB
-#define GPIO_PIN23_PAD_DRIVER_LSB WLAN_GPIO_PIN23_PAD_DRIVER_LSB
-#define GPIO_PIN23_PAD_DRIVER_MASK WLAN_GPIO_PIN23_PAD_DRIVER_MASK
-#define GPIO_PIN23_PAD_DRIVER_GET(x) WLAN_GPIO_PIN23_PAD_DRIVER_GET(x)
-#define GPIO_PIN23_PAD_DRIVER_SET(x) WLAN_GPIO_PIN23_PAD_DRIVER_SET(x)
-#define GPIO_PIN23_SOURCE_MSB WLAN_GPIO_PIN23_SOURCE_MSB
-#define GPIO_PIN23_SOURCE_LSB WLAN_GPIO_PIN23_SOURCE_LSB
-#define GPIO_PIN23_SOURCE_MASK WLAN_GPIO_PIN23_SOURCE_MASK
-#define GPIO_PIN23_SOURCE_GET(x) WLAN_GPIO_PIN23_SOURCE_GET(x)
-#define GPIO_PIN23_SOURCE_SET(x) WLAN_GPIO_PIN23_SOURCE_SET(x)
-#define GPIO_PIN24_ADDRESS WLAN_GPIO_PIN24_ADDRESS
-#define GPIO_PIN24_OFFSET WLAN_GPIO_PIN24_OFFSET
-#define GPIO_PIN24_CONFIG_MSB WLAN_GPIO_PIN24_CONFIG_MSB
-#define GPIO_PIN24_CONFIG_LSB WLAN_GPIO_PIN24_CONFIG_LSB
-#define GPIO_PIN24_CONFIG_MASK WLAN_GPIO_PIN24_CONFIG_MASK
-#define GPIO_PIN24_CONFIG_GET(x) WLAN_GPIO_PIN24_CONFIG_GET(x)
-#define GPIO_PIN24_CONFIG_SET(x) WLAN_GPIO_PIN24_CONFIG_SET(x)
-#define GPIO_PIN24_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN24_WAKEUP_ENABLE_MSB
-#define GPIO_PIN24_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN24_WAKEUP_ENABLE_LSB
-#define GPIO_PIN24_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN24_WAKEUP_ENABLE_MASK
-#define GPIO_PIN24_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN24_WAKEUP_ENABLE_GET(x)
-#define GPIO_PIN24_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN24_WAKEUP_ENABLE_SET(x)
-#define GPIO_PIN24_INT_TYPE_MSB WLAN_GPIO_PIN24_INT_TYPE_MSB
-#define GPIO_PIN24_INT_TYPE_LSB WLAN_GPIO_PIN24_INT_TYPE_LSB
-#define GPIO_PIN24_INT_TYPE_MASK WLAN_GPIO_PIN24_INT_TYPE_MASK
-#define GPIO_PIN24_INT_TYPE_GET(x) WLAN_GPIO_PIN24_INT_TYPE_GET(x)
-#define GPIO_PIN24_INT_TYPE_SET(x) WLAN_GPIO_PIN24_INT_TYPE_SET(x)
-#define GPIO_PIN24_PAD_DRIVER_MSB WLAN_GPIO_PIN24_PAD_DRIVER_MSB
-#define GPIO_PIN24_PAD_DRIVER_LSB WLAN_GPIO_PIN24_PAD_DRIVER_LSB
-#define GPIO_PIN24_PAD_DRIVER_MASK WLAN_GPIO_PIN24_PAD_DRIVER_MASK
-#define GPIO_PIN24_PAD_DRIVER_GET(x) WLAN_GPIO_PIN24_PAD_DRIVER_GET(x)
-#define GPIO_PIN24_PAD_DRIVER_SET(x) WLAN_GPIO_PIN24_PAD_DRIVER_SET(x)
-#define GPIO_PIN24_SOURCE_MSB WLAN_GPIO_PIN24_SOURCE_MSB
-#define GPIO_PIN24_SOURCE_LSB WLAN_GPIO_PIN24_SOURCE_LSB
-#define GPIO_PIN24_SOURCE_MASK WLAN_GPIO_PIN24_SOURCE_MASK
-#define GPIO_PIN24_SOURCE_GET(x) WLAN_GPIO_PIN24_SOURCE_GET(x)
-#define GPIO_PIN24_SOURCE_SET(x) WLAN_GPIO_PIN24_SOURCE_SET(x)
-#define GPIO_PIN25_ADDRESS WLAN_GPIO_PIN25_ADDRESS
-#define GPIO_PIN25_OFFSET WLAN_GPIO_PIN25_OFFSET
-#define GPIO_PIN25_CONFIG_MSB WLAN_GPIO_PIN25_CONFIG_MSB
-#define GPIO_PIN25_CONFIG_LSB WLAN_GPIO_PIN25_CONFIG_LSB
-#define GPIO_PIN25_CONFIG_MASK WLAN_GPIO_PIN25_CONFIG_MASK
-#define GPIO_PIN25_CONFIG_GET(x) WLAN_GPIO_PIN25_CONFIG_GET(x)
-#define GPIO_PIN25_CONFIG_SET(x) WLAN_GPIO_PIN25_CONFIG_SET(x)
-#define GPIO_PIN25_WAKEUP_ENABLE_MSB WLAN_GPIO_PIN25_WAKEUP_ENABLE_MSB
-#define GPIO_PIN25_WAKEUP_ENABLE_LSB WLAN_GPIO_PIN25_WAKEUP_ENABLE_LSB
-#define GPIO_PIN25_WAKEUP_ENABLE_MASK WLAN_GPIO_PIN25_WAKEUP_ENABLE_MASK
-#define GPIO_PIN25_WAKEUP_ENABLE_GET(x) WLAN_GPIO_PIN25_WAKEUP_ENABLE_GET(x)
-#define GPIO_PIN25_WAKEUP_ENABLE_SET(x) WLAN_GPIO_PIN25_WAKEUP_ENABLE_SET(x)
-#define GPIO_PIN25_INT_TYPE_MSB WLAN_GPIO_PIN25_INT_TYPE_MSB
-#define GPIO_PIN25_INT_TYPE_LSB WLAN_GPIO_PIN25_INT_TYPE_LSB
-#define GPIO_PIN25_INT_TYPE_MASK WLAN_GPIO_PIN25_INT_TYPE_MASK
-#define GPIO_PIN25_INT_TYPE_GET(x) WLAN_GPIO_PIN25_INT_TYPE_GET(x)
-#define GPIO_PIN25_INT_TYPE_SET(x) WLAN_GPIO_PIN25_INT_TYPE_SET(x)
-#define GPIO_PIN25_PAD_DRIVER_MSB WLAN_GPIO_PIN25_PAD_DRIVER_MSB
-#define GPIO_PIN25_PAD_DRIVER_LSB WLAN_GPIO_PIN25_PAD_DRIVER_LSB
-#define GPIO_PIN25_PAD_DRIVER_MASK WLAN_GPIO_PIN25_PAD_DRIVER_MASK
-#define GPIO_PIN25_PAD_DRIVER_GET(x) WLAN_GPIO_PIN25_PAD_DRIVER_GET(x)
-#define GPIO_PIN25_PAD_DRIVER_SET(x) WLAN_GPIO_PIN25_PAD_DRIVER_SET(x)
-#define GPIO_PIN25_SOURCE_MSB WLAN_GPIO_PIN25_SOURCE_MSB
-#define GPIO_PIN25_SOURCE_LSB WLAN_GPIO_PIN25_SOURCE_LSB
-#define GPIO_PIN25_SOURCE_MASK WLAN_GPIO_PIN25_SOURCE_MASK
-#define GPIO_PIN25_SOURCE_GET(x) WLAN_GPIO_PIN25_SOURCE_GET(x)
-#define GPIO_PIN25_SOURCE_SET(x) WLAN_GPIO_PIN25_SOURCE_SET(x)
-#define SIGMA_DELTA_ADDRESS WLAN_SIGMA_DELTA_ADDRESS
-#define SIGMA_DELTA_OFFSET WLAN_SIGMA_DELTA_OFFSET
-#define SIGMA_DELTA_ENABLE_MSB WLAN_SIGMA_DELTA_ENABLE_MSB
-#define SIGMA_DELTA_ENABLE_LSB WLAN_SIGMA_DELTA_ENABLE_LSB
-#define SIGMA_DELTA_ENABLE_MASK WLAN_SIGMA_DELTA_ENABLE_MASK
-#define SIGMA_DELTA_ENABLE_GET(x) WLAN_SIGMA_DELTA_ENABLE_GET(x)
-#define SIGMA_DELTA_ENABLE_SET(x) WLAN_SIGMA_DELTA_ENABLE_SET(x)
-#define SIGMA_DELTA_PRESCALAR_MSB WLAN_SIGMA_DELTA_PRESCALAR_MSB
-#define SIGMA_DELTA_PRESCALAR_LSB WLAN_SIGMA_DELTA_PRESCALAR_LSB
-#define SIGMA_DELTA_PRESCALAR_MASK WLAN_SIGMA_DELTA_PRESCALAR_MASK
-#define SIGMA_DELTA_PRESCALAR_GET(x) WLAN_SIGMA_DELTA_PRESCALAR_GET(x)
-#define SIGMA_DELTA_PRESCALAR_SET(x) WLAN_SIGMA_DELTA_PRESCALAR_SET(x)
-#define SIGMA_DELTA_TARGET_MSB WLAN_SIGMA_DELTA_TARGET_MSB
-#define SIGMA_DELTA_TARGET_LSB WLAN_SIGMA_DELTA_TARGET_LSB
-#define SIGMA_DELTA_TARGET_MASK WLAN_SIGMA_DELTA_TARGET_MASK
-#define SIGMA_DELTA_TARGET_GET(x) WLAN_SIGMA_DELTA_TARGET_GET(x)
-#define SIGMA_DELTA_TARGET_SET(x) WLAN_SIGMA_DELTA_TARGET_SET(x)
-#define DEBUG_CONTROL_ADDRESS WLAN_DEBUG_CONTROL_ADDRESS
-#define DEBUG_CONTROL_OFFSET WLAN_DEBUG_CONTROL_OFFSET
-#define DEBUG_CONTROL_ENABLE_MSB WLAN_DEBUG_CONTROL_ENABLE_MSB
-#define DEBUG_CONTROL_ENABLE_LSB WLAN_DEBUG_CONTROL_ENABLE_LSB
-#define DEBUG_CONTROL_ENABLE_MASK WLAN_DEBUG_CONTROL_ENABLE_MASK
-#define DEBUG_CONTROL_ENABLE_GET(x) WLAN_DEBUG_CONTROL_ENABLE_GET(x)
-#define DEBUG_CONTROL_ENABLE_SET(x) WLAN_DEBUG_CONTROL_ENABLE_SET(x)
-#define DEBUG_INPUT_SEL_ADDRESS WLAN_DEBUG_INPUT_SEL_ADDRESS
-#define DEBUG_INPUT_SEL_OFFSET WLAN_DEBUG_INPUT_SEL_OFFSET
-#define DEBUG_INPUT_SEL_SHIFT_MSB WLAN_DEBUG_INPUT_SEL_SHIFT_MSB
-#define DEBUG_INPUT_SEL_SHIFT_LSB WLAN_DEBUG_INPUT_SEL_SHIFT_LSB
-#define DEBUG_INPUT_SEL_SHIFT_MASK WLAN_DEBUG_INPUT_SEL_SHIFT_MASK
-#define DEBUG_INPUT_SEL_SHIFT_GET(x) WLAN_DEBUG_INPUT_SEL_SHIFT_GET(x)
-#define DEBUG_INPUT_SEL_SHIFT_SET(x) WLAN_DEBUG_INPUT_SEL_SHIFT_SET(x)
-#define DEBUG_INPUT_SEL_SRC_MSB WLAN_DEBUG_INPUT_SEL_SRC_MSB
-#define DEBUG_INPUT_SEL_SRC_LSB WLAN_DEBUG_INPUT_SEL_SRC_LSB
-#define DEBUG_INPUT_SEL_SRC_MASK WLAN_DEBUG_INPUT_SEL_SRC_MASK
-#define DEBUG_INPUT_SEL_SRC_GET(x) WLAN_DEBUG_INPUT_SEL_SRC_GET(x)
-#define DEBUG_INPUT_SEL_SRC_SET(x) WLAN_DEBUG_INPUT_SEL_SRC_SET(x)
-#define DEBUG_OUT_ADDRESS WLAN_DEBUG_OUT_ADDRESS
-#define DEBUG_OUT_OFFSET WLAN_DEBUG_OUT_OFFSET
-#define DEBUG_OUT_DATA_MSB WLAN_DEBUG_OUT_DATA_MSB
-#define DEBUG_OUT_DATA_LSB WLAN_DEBUG_OUT_DATA_LSB
-#define DEBUG_OUT_DATA_MASK WLAN_DEBUG_OUT_DATA_MASK
-#define DEBUG_OUT_DATA_GET(x) WLAN_DEBUG_OUT_DATA_GET(x)
-#define DEBUG_OUT_DATA_SET(x) WLAN_DEBUG_OUT_DATA_SET(x)
-#define RESET_TUPLE_STATUS_ADDRESS WLAN_RESET_TUPLE_STATUS_ADDRESS
-#define RESET_TUPLE_STATUS_OFFSET WLAN_RESET_TUPLE_STATUS_OFFSET
-#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MSB WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MSB
-#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_LSB
-#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_MASK
-#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_GET(x) WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_GET(x)
-#define RESET_TUPLE_STATUS_TEST_RESET_TUPLE_SET(x) WLAN_RESET_TUPLE_STATUS_TEST_RESET_TUPLE_SET(x)
-#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MSB WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MSB
-#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_LSB
-#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_MASK
-#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_GET(x) WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_GET(x)
-#define RESET_TUPLE_STATUS_PIN_RESET_TUPLE_SET(x) WLAN_RESET_TUPLE_STATUS_PIN_RESET_TUPLE_SET(x)
-
-
-#endif
-#endif
-
-
-
diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mac_dma_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mac_dma_reg.h
deleted file mode 100644
index f82f809..0000000
--- a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mac_dma_reg.h
+++ /dev/null
@@ -1,605 +0,0 @@
-// ------------------------------------------------------------------
-// Copyright (c) 2002-2010 Atheros Communications Inc.
-// All rights reserved.
-//
-//
-// Permission to use, copy, modify, and/or distribute this software for any
-// purpose with or without fee is hereby granted, provided that the above
-// copyright notice and this permission notice appear in all copies.
-//
-// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-//
-//
-// ------------------------------------------------------------------
-//===================================================================
-// Author(s): ="Atheros"
-//===================================================================
-
-
-/*****************************************************************************/
-/* AR6003 WLAN MAC DMA register definitions */
-/*****************************************************************************/
-
-#ifndef _AR6000_DMAREG_H_
-#define _AR6000_DMAREG_H_
-
-/*
- * Definitions for the Atheros AR6003 chipset.
- */
-
-/* DMA Control and Interrupt Registers */
-#define MAC_DMA_CR_ADDRESS 0x00000008 /* MAC control register */
-#define MAC_DMA_CR_RXE_MASK 0x00000004 /* Receive enable */
-#define MAC_DMA_CR_RXD_MASK 0x00000020 /* Receive disable */
-#define MAC_DMA_CR_SWI_MASK 0x00000040 /* One-shot software interrupt */
-
-#define MAC_DMA_RXDP_ADDRESS 0x0000000C /* MAC receive queue descriptor pointer */
-
-#define MAC_DMA_CFG_ADDRESS 0x00000014 /* MAC configuration and status register */
-#define MAC_DMA_CFG_SWTD_MASK 0x00000001 /* byteswap tx descriptor words */
-#define MAC_DMA_CFG_SWTB_MASK 0x00000002 /* byteswap tx data buffer words */
-#define MAC_DMA_CFG_SWRD_MASK 0x00000004 /* byteswap rx descriptor words */
-#define MAC_DMA_CFG_SWRB_MASK 0x00000008 /* byteswap rx data buffer words */
-#define MAC_DMA_CFG_SWRG_MASK 0x00000010 /* byteswap register access data words */
-#define MAC_DMA_CFG_AP_ADHOC_INDICATION_MASK 0x00000020 /* AP/adhoc indication (0-AP, 1-Adhoc) */
-#define MAC_DMA_CFG_PHOK_MASK 0x00000100 /* PHY OK status */
-#define MAC_DMA_CFG_CLK_GATE_DIS_MASK 0x00000400 /* Clock gating disable */
-
-#define MAC_DMA_MIRT_ADDRESS 0x00000020 /* Maximum rate threshold register */
-#define MAC_DMA_MIRT_THRESH_MASK 0x0000FFFF
-
-#define MAC_DMA_IER_ADDRESS 0x00000024 /* MAC Interrupt enable register */
-#define MAC_DMA_IER_ENABLE_MASK 0x00000001 /* Global interrupt enable */
-#define MAC_DMA_IER_DISABLE_MASK 0x00000000 /* Global interrupt disable */
-
-#define MAC_DMA_TIMT_ADDRESS 0x00000028 /* Transmit Interrupt Mitigation Threshold */
-#define MAC_DMA_TIMT_LAST_PACKER_THRESH_MASK 0x0000FFFF /* Last packet threshold mask */
-#define MAC_DMA_TIMT_FIRST_PACKER_THRESH_MASK 0xFFFF0000 /* First packet threshold mask */
-
-#define MAC_DMA_RIMT_ADDRESS 0x0000002C /* Receive Interrupt Mitigation Threshold */
-#define MAC_DMA_RIMT_LAST_PACKER_THRESH_MASK 0x0000FFFF /* Last packet threshold mask */
-#define MAC_DMA_RIMT_FIRST_PACKER_THRESH_MASK 0xFFFF0000 /* First packet threshold mask */
-
-#define MAC_DMA_TXCFG_ADDRESS 0x00000030 /* MAC tx DMA size config register */
-#define MAC_DMA_FTRIG_MASK 0x000003F0 /* Mask for Frame trigger level */
-#define MAC_DMA_FTRIG_LSB 4 /* Shift for Frame trigger level */
-#define MAC_DMA_FTRIG_IMMED 0x00000000 /* bytes in PCU TX FIFO before air */
-#define MAC_DMA_FTRIG_64B 0x00000010 /* default */
-#define MAC_DMA_FTRIG_128B 0x00000020
-#define MAC_DMA_FTRIG_192B 0x00000030
-#define MAC_DMA_FTRIG_256B 0x00000040 /* 5 bits total */
-#define MAC_DMA_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY_MASK 0x00000800
-
-#define MAC_DMA_RXCFG_ADDRESS 0x00000034 /* MAC rx DMA size config register */
-#define MAC_DMA_RXCFG_ZLFDMA_MASK 0x00000010 /* Enable DMA of zero-length frame */
-#define MAC_DMA_RXCFG_DMASIZE_4B 0x00000000 /* DMA size 4 bytes (TXCFG + RXCFG) */
-#define MAC_DMA_RXCFG_DMASIZE_8B 0x00000001 /* DMA size 8 bytes */
-#define MAC_DMA_RXCFG_DMASIZE_16B 0x00000002 /* DMA size 16 bytes */
-#define MAC_DMA_RXCFG_DMASIZE_32B 0x00000003 /* DMA size 32 bytes */
-#define MAC_DMA_RXCFG_DMASIZE_64B 0x00000004 /* DMA size 64 bytes */
-#define MAC_DMA_RXCFG_DMASIZE_128B 0x00000005 /* DMA size 128 bytes */
-#define MAC_DMA_RXCFG_DMASIZE_256B 0x00000006 /* DMA size 256 bytes */
-#define MAC_DMA_RXCFG_DMASIZE_512B 0x00000007 /* DMA size 512 bytes */
-
-#define MAC_DMA_MIBC_ADDRESS 0x00000040 /* MAC MIB control register */
-#define MAC_DMA_MIBC_COW_MASK 0x00000001 /* counter overflow warning */
-#define MAC_DMA_MIBC_FMC_MASK 0x00000002 /* freeze MIB counters */
-#define MAC_DMA_MIBC_CMC_MASK 0x00000004 /* clear MIB counters */
-#define MAC_DMA_MIBC_MCS_MASK 0x00000008 /* MIB counter strobe, increment all */
-
-#define MAC_DMA_TOPS_ADDRESS 0x00000044 /* MAC timeout prescale count */
-#define MAC_DMA_TOPS_MASK 0x0000FFFF /* Mask for timeout prescale */
-
-#define MAC_DMA_RXNPTO_ADDRESS 0x00000048 /* MAC no frame received timeout */
-#define MAC_DMA_RXNPTO_MASK 0x000003FF /* Mask for no frame received timeout */
-
-#define MAC_DMA_TXNPTO_ADDRESS 0x0000004C /* MAC no frame trasmitted timeout */
-#define MAC_DMA_TXNPTO_MASK 0x000003FF /* Mask for no frame transmitted timeout */
-#define MAC_DMA_TXNPTO_QCU_MASK 0x000FFC00 /* Mask indicating the set of QCUs */
- /* for which frame completions will cause */
- /* a reset of the no frame xmit'd timeout */
-
-#define MAC_DMA_RPGTO_ADDRESS 0x00000050 /* MAC receive frame gap timeout */
-#define MAC_DMA_RPGTO_MASK 0x000003FF /* Mask for receive frame gap timeout */
-
-#define MAC_DMA_RPCNT_ADDRESS 0x00000054 /* MAC receive frame count limit */
-#define MAC_DMA_RPCNT_MASK 0x0000001F /* Mask for receive frame count limit */
-
-#define MAC_DMA_MACMISC_ADDRESS 0x00000058 /* MAC miscellaneous control/status register */
-#define MAC_DMA_MACMISC_DMA_OBS_MASK 0x000001E0 /* Mask for DMA observation bus mux select */
-#define MAC_DMA_MACMISC_DMA_OBS_LSB 5 /* Shift for DMA observation bus mux select */
-#define MAC_DMA_MACMISC_MISC_OBS 0x00000E00 /* Mask for MISC observation bus mux select */
-#define MAC_DMA_MACMISC_MISC_OBS_LSB 9 /* Shift for MISC observation bus mux select */
-#define MAC_DMA_MACMISC_MAC_OBS_BUS_LSB 0x00007000 /* Mask for MAC observation bus mux select (lsb) */
-#define MAC_DMA_MACMISC_MAC_OBS_BUS_LSB_LSB 12 /* Shift for MAC observation bus mux select (lsb) */
-#define MAC_DMA_MACMISC_MAC_OBS_BUS_MSB 0x00038000 /* Mask for MAC observation bus mux select (msb) */
-#define MAC_DMA_MACMISC_MAC_OBS_BUS_MSB_LSB 15 /* Shift for MAC observation bus mux select (msb) */
-
-
-#define MAC_DMA_ISR_ADDRESS 0x00000080 /* MAC Primary interrupt status register */
-/*
- * Interrupt Status Registers
- *
- * Only the bits in the ISR_P register and the IMR_P registers
- * control whether the MAC's INTA# output is asserted. The bits in
- * the secondary interrupt status/mask registers control what bits
- * are set in the primary interrupt status register; however the
- * IMR_S* registers DO NOT determine whether INTA# is asserted.
- * That is INTA# is asserted only when the logical AND of ISR_P
- * and IMR_P is non-zero. The secondary interrupt mask/status
- * registers affect what bits are set in ISR_P but they do not
- * directly affect whether INTA# is asserted.
- */
-#define MAC_DMA_ISR_RXOK_MASK 0x00000001 /* At least one frame received sans errors */
-#define MAC_DMA_ISR_RXDESC_MASK 0x00000002 /* Receive interrupt request */
-#define MAC_DMA_ISR_RXERR_MASK 0x00000004 /* Receive error interrupt */
-#define MAC_DMA_ISR_RXNOPKT_MASK 0x00000008 /* No frame received within timeout clock */
-#define MAC_DMA_ISR_RXEOL_MASK 0x00000010 /* Received descriptor empty interrupt */
-#define MAC_DMA_ISR_RXORN_MASK 0x00000020 /* Receive FIFO overrun interrupt */
-#define MAC_DMA_ISR_TXOK_MASK 0x00000040 /* Transmit okay interrupt */
-#define MAC_DMA_ISR_TXDESC_MASK 0x00000080 /* Transmit interrupt request */
-#define MAC_DMA_ISR_TXERR_MASK 0x00000100 /* Transmit error interrupt */
-#define MAC_DMA_ISR_TXNOPKT_MASK 0x00000200 /* No frame transmitted interrupt */
-#define MAC_DMA_ISR_TXEOL_MASK 0x00000400 /* Transmit descriptor empty interrupt */
-#define MAC_DMA_ISR_TXURN_MASK 0x00000800 /* Transmit FIFO underrun interrupt */
-#define MAC_DMA_ISR_MIB_MASK 0x00001000 /* MIB interrupt - see MIBC */
-#define MAC_DMA_ISR_SWI_MASK 0x00002000 /* Software interrupt */
-#define MAC_DMA_ISR_RXPHY_MASK 0x00004000 /* PHY receive error interrupt */
-#define MAC_DMA_ISR_RXKCM_MASK 0x00008000 /* Key-cache miss interrupt */
-#define MAC_DMA_ISR_BRSSI_HI_MASK 0x00010000 /* Beacon rssi high threshold interrupt */
-#define MAC_DMA_ISR_BRSSI_LO_MASK 0x00020000 /* Beacon threshold interrupt */
-#define MAC_DMA_ISR_BMISS_MASK 0x00040000 /* Beacon missed interrupt */
-#define MAC_DMA_ISR_TXMINTR_MASK 0x00080000 /* Maximum transmit interrupt rate */
-#define MAC_DMA_ISR_BNR_MASK 0x00100000 /* Beacon not ready interrupt */
-#define MAC_DMA_ISR_HIUERR_MASK 0x00200000 /* An unexpected bus error has occurred */
-#define MAC_DMA_ISR_BCNMISC_MASK 0x00800000 /* 'or' of TIM, CABEND, DTIMSYNC, BCNTO */
-#define MAC_DMA_ISR_RXMINTR_MASK 0x01000000 /* Maximum receive interrupt rate */
-#define MAC_DMA_ISR_QCBROVF_MASK 0x02000000 /* QCU CBR overflow interrupt */
-#define MAC_DMA_ISR_QCBRURN_MASK 0x04000000 /* QCU CBR underrun interrupt */
-#define MAC_DMA_ISR_QTRIG_MASK 0x08000000 /* QCU scheduling trigger interrupt */
-#define MAC_DMA_ISR_TIMER_MASK 0x10000000 /* GENTMR interrupt */
-#define MAC_DMA_ISR_HCFTO_MASK 0x20000000 /* HCFTO interrupt */
-#define MAC_DMA_ISR_TXINTM_MASK 0x40000000 /* Transmit completion mitigation interrupt */
-#define MAC_DMA_ISR_RXINTM_MASK 0x80000000 /* Receive completion mitigation interrupt */
-
-#define MAC_DMA_ISR_S0_ADDRESS 0x00000084 /* MAC Secondary interrupt status register 0 */
-#define MAC_DMA_ISR_S0_QCU_TXOK_MASK 0x000003FF /* Mask for TXOK (QCU 0-9) */
-#define MAC_DMA_ISR_S0_QCU_TXOK_LSB 0
-#define MAC_DMA_ISR_S0_QCU_TXDESC_MASK 0x03FF0000 /* Mask for TXDESC (QCU 0-9) */
-#define MAC_DMA_ISR_S0_QCU_TXDESC_LSB 16
-
-#define MAC_DMA_ISR_S1_ADDRESS 0x00000088 /* MAC Secondary interrupt status register 1 */
-#define MAC_DMA_ISR_S1_QCU_TXERR_MASK 0x000003FF /* Mask for TXERR (QCU 0-9) */
-#define MAC_DMA_ISR_S1_QCU_TXERR_LSB 0
-#define MAC_DMA_ISR_S1_QCU_TXEOL_MASK 0x03FF0000 /* Mask for TXEOL (QCU 0-9) */
-#define MAC_DMA_ISR_S1_QCU_TXEOL_LSB 16
-
-#define MAC_DMA_ISR_S2_ADDRESS 0x0000008c /* MAC Secondary interrupt status register 2 */
-#define MAC_DMA_ISR_S2_QCU_TXURN_MASK 0x000003FF /* Mask for TXURN (QCU 0-9) */
-#define MAC_DMA_ISR_S2_QCU_TXURN_LSB 0 /* Shift for TXURN (QCU 0-9) */
-#define MAC_DMA_ISR_S2_RX_INT_MASK 0x00000800
-#define MAC_DMA_ISR_S2_WL_STOMPED_MASK 0x00001000
-#define MAC_DMA_ISR_S2_RX_PTR_BAD_MASK 0x00002000
-#define MAC_DMA_ISR_S2_BT_LOW_PRIORITY_RISING_MASK 0x00004000
-#define MAC_DMA_ISR_S2_BT_LOW_PRIORITY_FALLING_MASK 0x00008000
-#define MAC_DMA_ISR_S2_BB_PANIC_IRQ_MASK 0x00010000
-#define MAC_DMA_ISR_S2_BT_STOMPED_MASK 0x00020000
-#define MAC_DMA_ISR_S2_BT_ACTIVE_RISING_MASK 0x00040000
-#define MAC_DMA_ISR_S2_BT_ACTIVE_FALLING_MASK 0x00080000
-#define MAC_DMA_ISR_S2_BT_PRIORITY_RISING_MASK 0x00100000
-#define MAC_DMA_ISR_S2_BT_PRIORITY_FALLING_MASK 0x00200000
-#define MAC_DMA_ISR_S2_CST_MASK 0x00400000
-#define MAC_DMA_ISR_S2_GTT_MASK 0x00800000
-#define MAC_DMA_ISR_S2_TIM_MASK 0x01000000 /* TIM */
-#define MAC_DMA_ISR_S2_CABEND_MASK 0x02000000 /* CABEND */
-#define MAC_DMA_ISR_S2_DTIMSYNC_MASK 0x04000000 /* DTIMSYNC */
-#define MAC_DMA_ISR_S2_BCNTO_MASK 0x08000000 /* BCNTO */
-#define MAC_DMA_ISR_S2_CABTO_MASK 0x10000000 /* CABTO */
-#define MAC_DMA_ISR_S2_DTIM_MASK 0x20000000 /* DTIM */
-#define MAC_DMA_ISR_S2_TSFOOR_MASK 0x40000000 /* TSFOOR */
-
-#define MAC_DMA_ISR_S3_ADDRESS 0x00000090 /* MAC Secondary interrupt status register 3 */
-#define MAC_DMA_ISR_S3_QCU_QCBROVF_MASK 0x000003FF /* Mask for QCBROVF (QCU 0-9) */
-#define MAC_DMA_ISR_S3_QCU_QCBRURN_MASK 0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */
-
-#define MAC_DMA_ISR_S4_ADDRESS 0x00000094 /* MAC Secondary interrupt status register 4 */
-#define MAC_DMA_ISR_S4_QCU_QTRIG_MASK 0x000003FF /* Mask for QTRIG (QCU 0-9) */
-
-#define MAC_DMA_ISR_S5_ADDRESS 0x00000098 /* MAC Secondary interrupt status register 5 */
-#define MAC_DMA_ISR_S5_TBTT_TIMER_TRIGGER_MASK 0x00000001
-#define MAC_DMA_ISR_S5_DBA_TIMER_TRIGGER_MASK 0x00000002
-#define MAC_DMA_ISR_S5_SBA_TIMER_TRIGGER_MASK 0x00000004
-#define MAC_DMA_ISR_S5_HCF_TIMER_TRIGGER_MASK 0x00000008
-#define MAC_DMA_ISR_S5_TIM_TIMER_TRIGGER_MASK 0x00000010
-#define MAC_DMA_ISR_S5_DTIM_TIMER_TRIGGER_MASK 0x00000020
-#define MAC_DMA_ISR_S5_QUIET_TIMER_TRIGGER_MASK 0x00000040
-#define MAC_DMA_ISR_S5_NDP_TIMER_TRIGGER_MASK 0x00000080
-#define MAC_DMA_ISR_S5_GENERIC_TIMER2_TRIGGER_MASK 0x0000FF00
-#define MAC_DMA_ISR_S5_GENERIC_TIMER2_TRIGGER_LSB 8
-#define MAC_DMA_ISR_S5_GENERIC_TIMER2_TRIGGER(_i) (0x00000100 << (_i))
-#define MAC_DMA_ISR_S5_TIMER_OVERFLOW_MASK 0x00010000
-#define MAC_DMA_ISR_S5_DBA_TIMER_THRESHOLD_MASK 0x00020000
-#define MAC_DMA_ISR_S5_SBA_TIMER_THRESHOLD_MASK 0x00040000
-#define MAC_DMA_ISR_S5_HCF_TIMER_THRESHOLD_MASK 0x00080000
-#define MAC_DMA_ISR_S5_TIM_TIMER_THRESHOLD_MASK 0x00100000
-#define MAC_DMA_ISR_S5_DTIM_TIMER_THRESHOLD_MASK 0x00200000
-#define MAC_DMA_ISR_S5_QUIET_TIMER_THRESHOLD_MASK 0x00400000
-#define MAC_DMA_ISR_S5_NDP_TIMER_THRESHOLD_MASK 0x00800000
-#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD_MASK 0xFF000000
-#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD_LSB 24
-#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD(_i) (0x01000000 << (_i))
-
-#define MAC_DMA_IMR_ADDRESS 0x000000A0 /* MAC Primary interrupt mask register */
-/*
- * Interrupt Mask Registers
- *
- * Only the bits in the IMR control whether the MAC's INTA#
- * output will be asserted. The bits in the secondary interrupt
- * mask registers control what bits get set in the primary
- * interrupt status register; however the IMR_S* registers
- * DO NOT determine whether INTA# is asserted.
- */
-#define MAC_DMA_IMR_RXOK_MASK 0x00000001 /* At least one frame received sans errors */
-#define MAC_DMA_IMR_RXDESC_MASK 0x00000002 /* Receive interrupt request */
-#define MAC_DMA_IMR_RXERR_MASK 0x00000004 /* Receive error interrupt */
-#define MAC_DMA_IMR_RXNOPKT_MASK 0x00000008 /* No frame received within timeout clock */
-#define MAC_DMA_IMR_RXEOL_MASK 0x00000010 /* Received descriptor empty interrupt */
-#define MAC_DMA_IMR_RXORN_MASK 0x00000020 /* Receive FIFO overrun interrupt */
-#define MAC_DMA_IMR_TXOK_MASK 0x00000040 /* Transmit okay interrupt */
-#define MAC_DMA_IMR_TXDESC_MASK 0x00000080 /* Transmit interrupt request */
-#define MAC_DMA_IMR_TXERR_MASK 0x00000100 /* Transmit error interrupt */
-#define MAC_DMA_IMR_TXNOPKT_MASK 0x00000200 /* No frame transmitted interrupt */
-#define MAC_DMA_IMR_TXEOL_MASK 0x00000400 /* Transmit descriptor empty interrupt */
-#define MAC_DMA_IMR_TXURN_MASK 0x00000800 /* Transmit FIFO underrun interrupt */
-#define MAC_DMA_IMR_MIB_MASK 0x00001000 /* MIB interrupt - see MIBC */
-#define MAC_DMA_IMR_SWI_MASK 0x00002000 /* Software interrupt */
-#define MAC_DMA_IMR_RXPHY_MASK 0x00004000 /* PHY receive error interrupt */
-#define MAC_DMA_IMR_RXKCM_MASK 0x00008000 /* Key-cache miss interrupt */
-#define MAC_DMA_IMR_BRSSI_HI_MASK 0x00010000 /* Beacon rssi hi threshold interrupt */
-#define MAC_DMA_IMR_BRSSI_LO_MASK 0x00020000 /* Beacon rssi lo threshold interrupt */
-#define MAC_DMA_IMR_BMISS_MASK 0x00040000 /* Beacon missed interrupt */
-#define MAC_DMA_IMR_TXMINTR_MASK 0x00080000 /* Maximum transmit interrupt rate */
-#define MAC_DMA_IMR_BNR_MASK 0x00100000 /* BNR interrupt */
-#define MAC_DMA_IMR_HIUERR_MASK 0x00200000 /* An unexpected bus error has occurred */
-#define MAC_DMA_IMR_BCNMISC_MASK 0x00800000 /* Beacon Misc */
-#define MAC_DMA_IMR_RXMINTR_MASK 0x01000000 /* Maximum receive interrupt rate */
-#define MAC_DMA_IMR_QCBROVF_MASK 0x02000000 /* QCU CBR overflow interrupt */
-#define MAC_DMA_IMR_QCBRURN_MASK 0x04000000 /* QCU CBR underrun interrupt */
-#define MAC_DMA_IMR_QTRIG_MASK 0x08000000 /* QCU scheduling trigger interrupt */
-#define MAC_DMA_IMR_TIMER_MASK 0x10000000 /* GENTMR interrupt */
-#define MAC_DMA_IMR_HCFTO_MASK 0x20000000 /* HCFTO interrupt*/
-#define MAC_DMA_IMR_TXINTM_MASK 0x40000000 /* Transmit completion mitigation interrupt */
-#define MAC_DMA_IMR_RXINTM_MASK 0x80000000 /* Receive completion mitigation interrupt */
-
-#define MAC_DMA_IMR_S0_ADDRESS 0x000000A4 /* MAC Secondary interrupt mask register 0 */
-#define MAC_DMA_IMR_S0_QCU_TXOK_MASK 0x000003FF /* TXOK (QCU 0-9) */
-#define MAC_DMA_IMR_S0_QCU_TXOK_LSB 0
-#define MAC_DMA_IMR_S0_QCU_TXDESC_MASK 0x03FF0000 /* TXDESC (QCU 0-9) */
-#define MAC_DMA_IMR_S0_QCU_TXDESC_LSB 16
-
-#define MAC_DMA_IMR_S1_ADDRESS 0x000000A8 /* MAC Secondary interrupt mask register 1 */
-#define MAC_DMA_IMR_S1_QCU_TXERR_MASK 0x000003FF /* TXERR (QCU 0-9) */
-#define MAC_DMA_IMR_S1_QCU_TXERR_LSB 0
-#define MAC_DMA_IMR_S1_QCU_TXEOL_MASK 0x03FF0000 /* TXEOL (QCU 0-9) */
-#define MAC_DMA_IMR_S1_QCU_TXEOL_LSB 16
-
-#define MAC_DMA_IMR_S2_ADDRESS 0x000000AC /* MAC Secondary interrupt mask register 2 */
-#define MAC_DMA_IMR_S2_QCU_TXURN_MASK 0x000003FF /* Mask for TXURN (QCU 0-9) */
-#define MAC_DMA_IMR_S2_QCU_TXURN_LSB 0
-#define MAC_DMA_IMR_S2_RX_INT_MASK 0x00000800
-#define MAC_DMA_IMR_S2_WL_STOMPED_MASK 0x00001000
-#define MAC_DMA_IMR_S2_RX_PTR_BAD_MASK 0x00002000
-#define MAC_DMA_IMR_S2_BT_LOW_PRIORITY_RISING_MASK 0x00004000
-#define MAC_DMA_IMR_S2_BT_LOW_PRIORITY_FALLING_MASK 0x00008000
-#define MAC_DMA_IMR_S2_BB_PANIC_IRQ_MASK 0x00010000
-#define MAC_DMA_IMR_S2_BT_STOMPED_MASK 0x00020000
-#define MAC_DMA_IMR_S2_BT_ACTIVE_RISING_MASK 0x00040000
-#define MAC_DMA_IMR_S2_BT_ACTIVE_FALLING_MASK 0x00080000
-#define MAC_DMA_IMR_S2_BT_PRIORITY_RISING_MASK 0x00100000
-#define MAC_DMA_IMR_S2_BT_PRIORITY_FALLING_MASK 0x00200000
-#define MAC_DMA_IMR_S2_CST_MASK 0x00400000
-#define MAC_DMA_IMR_S2_GTT_MASK 0x00800000
-#define MAC_DMA_IMR_S2_TIM_MASK 0x01000000 /* TIM */
-#define MAC_DMA_IMR_S2_CABEND_MASK 0x02000000 /* CABEND */
-#define MAC_DMA_IMR_S2_DTIMSYNC_MASK 0x04000000 /* DTIMSYNC */
-#define MAC_DMA_IMR_S2_BCNTO_MASK 0x08000000 /* BCNTO */
-#define MAC_DMA_IMR_S2_CABTO_MASK 0x10000000 /* CABTO */
-#define MAC_DMA_IMR_S2_DTIM_MASK 0x20000000 /* DTIM */
-#define MAC_DMA_IMR_S2_TSFOOR_MASK 0x40000000 /* TSFOOR */
-
-#define MAC_DMA_IMR_S3_ADDRESS 0x000000B0 /* MAC Secondary interrupt mask register 3 */
-#define MAC_DMA_IMR_S3_QCU_QCBROVF_MASK 0x000003FF /* Mask for QCBROVF (QCU 0-9) */
-#define MAC_DMA_IMR_S3_QCU_QCBRURN_MASK 0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */
-#define MAC_DMA_IMR_S3_QCU_QCBRURN_LSB 16
-
-#define MAC_DMA_IMR_S4_ADDRESS 0x000000B4 /* MAC Secondary interrupt mask register 4 */
-#define MAC_DMA_IMR_S4_QCU_QTRIG_MASK 0x000003FF /* Mask for QTRIG (QCU 0-9) */
-
-#define MAC_DMA_IMR_S5_ADDRESS 0x000000B8 /* MAC Secondary interrupt mask register 5 */
-#define MAC_DMA_IMR_S5_TBTT_TIMER_TRIGGER_MASK 0x00000001
-#define MAC_DMA_IMR_S5_DBA_TIMER_TRIGGER_MASK 0x00000002
-#define MAC_DMA_IMR_S5_SBA_TIMER_TRIGGER_MASK 0x00000004
-#define MAC_DMA_IMR_S5_HCF_TIMER_TRIGGER_MASK 0x00000008
-#define MAC_DMA_IMR_S5_TIM_TIMER_TRIGGER_MASK 0x00000010
-#define MAC_DMA_IMR_S5_DTIM_TIMER_TRIGGER_MASK 0x00000020
-#define MAC_DMA_IMR_S5_QUIET_TIMER_TRIGGER_MASK 0x00000040
-#define MAC_DMA_IMR_S5_NDP_TIMER_TRIGGER_MASK 0x00000080
-#define MAC_DMA_IMR_S5_GENERIC_TIMER2_TRIGGER_MASK 0x0000FF00
-#define MAC_DMA_IMR_S5_GENERIC_TIMER2_TRIGGER_LSB 8
-#define MAC_DMA_IMR_S5_GENERIC_TIMER2_TRIGGER(_i) (0x100 << (_i))
-#define MAC_DMA_IMR_S5_TIMER_OVERFLOW_MASK 0x00010000
-#define MAC_DMA_IMR_S5_DBA_TIMER_THRESHOLD_MASK 0x00020000
-#define MAC_DMA_IMR_S5_SBA_TIMER_THRESHOLD_MASK 0x00040000
-#define MAC_DMA_IMR_S5_HCF_TIMER_THRESHOLD_MASK 0x00080000
-#define MAC_DMA_IMR_S5_TIM_TIMER_THRESHOLD_MASK 0x00100000
-#define MAC_DMA_IMR_S5_DTIM_TIMER_THRESHOLD_MASK 0x00200000
-#define MAC_DMA_IMR_S5_QUIET_TIMER_THRESHOLD_MASK 0000400000
-#define MAC_DMA_IMR_S5_NDP_TIMER_THRESHOLD_MASK 0x00800000
-#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD_MASK 0xFF000000
-#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD_LSB 24
-#define MAC_DMA_IMR_S5_GENERIC_TIMER2_THRESHOLD(_i) (0x01000000 << (_i))
-
-#define MAC_DMA_ISR_RAC_ADDRESS 0x000000C0 /* ISR read-and-clear access */
-
-/* Shadow copies with read-and-clear access */
-#define MAC_DMA_ISR_S0_S_ADDRESS 0x000000C4 /* ISR_S0 shadow copy */
-#define MAC_DMA_ISR_S1_S_ADDRESS 0x000000C8 /* ISR_S1 shadow copy */
-#define MAC_DMA_ISR_S2_S_ADDRESS 0x000000Cc /* ISR_S2 shadow copy */
-#define MAC_DMA_ISR_S3_S_ADDRESS 0x000000D0 /* ISR_S3 shadow copy */
-#define MAC_DMA_ISR_S4_S_ADDRESS 0x000000D4 /* ISR_S4 shadow copy */
-#define MAC_DMA_ISR_S5_S_ADDRESS 0x000000D8 /* ISR_S5 shadow copy */
-
-#define MAC_DMA_Q0_TXDP_ADDRESS 0x00000800 /* MAC Transmit Queue descriptor pointer */
-#define MAC_DMA_Q1_TXDP_ADDRESS 0x00000804 /* MAC Transmit Queue descriptor pointer */
-#define MAC_DMA_Q2_TXDP_ADDRESS 0x00000808 /* MAC Transmit Queue descriptor pointer */
-#define MAC_DMA_Q3_TXDP_ADDRESS 0x0000080C /* MAC Transmit Queue descriptor pointer */
-#define MAC_DMA_Q4_TXDP_ADDRESS 0x00000810 /* MAC Transmit Queue descriptor pointer */
-#define MAC_DMA_Q5_TXDP_ADDRESS 0x00000814 /* MAC Transmit Queue descriptor pointer */
-#define MAC_DMA_Q6_TXDP_ADDRESS 0x00000818 /* MAC Transmit Queue descriptor pointer */
-#define MAC_DMA_Q7_TXDP_ADDRESS 0x0000081C /* MAC Transmit Queue descriptor pointer */
-#define MAC_DMA_Q8_TXDP_ADDRESS 0x00000820 /* MAC Transmit Queue descriptor pointer */
-#define MAC_DMA_Q9_TXDP_ADDRESS 0x00000824 /* MAC Transmit Queue descriptor pointer */
-#define MAC_DMA_QTXDP_ADDRESS(_i) (MAC_DMA_Q0_TXDP_ADDRESS + ((_i)<<2))
-
-#define MAC_DMA_Q_TXE_ADDRESS 0x00000840 /* MAC Transmit Queue enable */
-#define MAC_DMA_Q_TXD_ADDRESS 0x00000880 /* MAC Transmit Queue disable */
-/* QCU registers */
-
-#define MAC_DMA_Q0_CBRCFG_ADDRESS 0x000008C0 /* MAC CBR configuration */
-#define MAC_DMA_Q1_CBRCFG_ADDRESS 0x000008C4 /* MAC CBR configuration */
-#define MAC_DMA_Q2_CBRCFG_ADDRESS 0x000008C8 /* MAC CBR configuration */
-#define MAC_DMA_Q3_CBRCFG_ADDRESS 0x000008CC /* MAC CBR configuration */
-#define MAC_DMA_Q4_CBRCFG_ADDRESS 0x000008D0 /* MAC CBR configuration */
-#define MAC_DMA_Q5_CBRCFG_ADDRESS 0x000008D4 /* MAC CBR configuration */
-#define MAC_DMA_Q6_CBRCFG_ADDRESS 0x000008D8 /* MAC CBR configuration */
-#define MAC_DMA_Q7_CBRCFG_ADDRESS 0x000008DC /* MAC CBR configuration */
-#define MAC_DMA_Q8_CBRCFG_ADDRESS 0x000008E0 /* MAC CBR configuration */
-#define MAC_DMA_Q9_CBRCFG_ADDRESS 0x000008E4 /* MAC CBR configuration */
-#define MAC_DMA_QCBRCFG_ADDRESS(_i) (MAC_DMA_Q0_CBRCFG_ADDRESS + ((_i)<<2))
-
-#define MAC_DMA_Q_CBRCFG_CBR_INTERVAL_MASK 0x00FFFFFF /* Mask for CBR interval (us) */
-#define MAC_DMA_Q_CBRCFG_CBR_INTERVAL_LSB 0 /* Shift for CBR interval */
-#define MAC_DMA_Q_CBRCFG_CBR_OVF_THRESH_MASK 0xFF000000 /* Mask for CBR overflow threshold */
-#define MAC_DMA_Q_CBRCFG_CBR_OVF_THRESH_LSB 24 /* Shift for CBR overflow thresh */
-
-
-#define MAC_DMA_Q0_RDYTIMECFG_ADDRESS 0x00000900 /* MAC ReadyTime configuration */
-#define MAC_DMA_Q1_RDYTIMECFG_ADDRESS 0x00000904 /* MAC ReadyTime configuration */
-#define MAC_DMA_Q2_RDYTIMECFG_ADDRESS 0x00000908 /* MAC ReadyTime configuration */
-#define MAC_DMA_Q3_RDYTIMECFG_ADDRESS 0x0000090C /* MAC ReadyTime configuration */
-#define MAC_DMA_Q4_RDYTIMECFG_ADDRESS 0x00000910 /* MAC ReadyTime configuration */
-#define MAC_DMA_Q5_RDYTIMECFG_ADDRESS 0x00000914 /* MAC ReadyTime configuration */
-#define MAC_DMA_Q6_RDYTIMECFG_ADDRESS 0x00000918 /* MAC ReadyTime configuration */
-#define MAC_DMA_Q7_RDYTIMECFG_ADDRESS 0x0000091C /* MAC ReadyTime configuration */
-#define MAC_DMA_Q8_RDYTIMECFG_ADDRESS 0x00000920 /* MAC ReadyTime configuration */
-#define MAC_DMA_Q9_RDYTIMECFG_ADDRESS 0x00000924 /* MAC ReadyTime configuration */
-#define MAC_DMA_QRDYTIMECFG_ADDRESS(_i) (MAC_DMA_Q0_RDYTIMECFG_ADDRESS + ((_i)<<2))
-
-#define MAC_DMA_Q_RDYTIMECFG_INT_MASK 0x00FFFFFF /* CBR interval (us) */
-#define MAC_DMA_Q_RDYTIMECFG_INT_LSB 0 /* Shift for ReadyTime Interval (us) */
-#define MAC_DMA_Q_RDYTIMECFG_ENA_MASK 0x01000000 /* CBR enable */
-
-#define MAC_DMA_Q_ONESHOTMAC_DMAM_SC_ADDRESS 0x00000940 /* MAC OneShotArm set control */
-#define MAC_DMA_Q_ONESHOTMAC_DMAM_CC_ADDRESS 0x00000980 /* MAC OneShotArm clear control */
-
-#define MAC_DMA_Q0_MISC_ADDRESS 0x000009C0 /* MAC Miscellaneous QCU settings */
-#define MAC_DMA_Q1_MISC_ADDRESS 0x000009C4 /* MAC Miscellaneous QCU settings */
-#define MAC_DMA_Q2_MISC_ADDRESS 0x000009C8 /* MAC Miscellaneous QCU settings */
-#define MAC_DMA_Q3_MISC_ADDRESS 0x000009CC /* MAC Miscellaneous QCU settings */
-#define MAC_DMA_Q4_MISC_ADDRESS 0x000009D0 /* MAC Miscellaneous QCU settings */
-#define MAC_DMA_Q5_MISC_ADDRESS 0x000009D4 /* MAC Miscellaneous QCU settings */
-#define MAC_DMA_Q6_MISC_ADDRESS 0x000009D8 /* MAC Miscellaneous QCU settings */
-#define MAC_DMA_Q7_MISC_ADDRESS 0x000009DC /* MAC Miscellaneous QCU settings */
-#define MAC_DMA_Q8_MISC_ADDRESS 0x000009E0 /* MAC Miscellaneous QCU settings */
-#define MAC_DMA_Q9_MISC_ADDRESS 0x000009E4 /* MAC Miscellaneous QCU settings */
-#define MAC_DMA_QMISC_ADDRESS(_i) (MAC_DMA_Q0_MISC_ADDRESS + ((_i)<<2))
-
-#define MAC_DMA_Q_MISC_FSP_MASK 0x0000000F /* Frame Scheduling Policy mask */
-#define MAC_DMA_Q_MISC_FSP_ASAP 0 /* ASAP */
-#define MAC_DMA_Q_MISC_FSP_CBR 1 /* CBR */
-#define MAC_DMA_Q_MISC_FSP_DBA_GATED 2 /* DMA Beacon Alert gated */
-#define MAC_DMA_Q_MISC_FSP_TIM_GATED 3 /* TIM gated */
-#define MAC_DMA_Q_MISC_FSP_BEACON_SENT_GATED 4 /* Beacon-sent-gated */
-#define MAC_DMA_Q_MISC_ONE_SHOT_EN_MASK 0x00000010 /* OneShot enable */
-#define MAC_DMA_Q_MISC_CBR_INCR_DIS1_MASK 0x00000020 /* Disable CBR expired counter incr
- (empty q) */
-#define MAC_DMA_Q_MISC_CBR_INCR_DIS0_MASK 0x00000040 /* Disable CBR expired counter incr
- (empty beacon q) */
-#define MAC_DMA_Q_MISC_BEACON_USE_MASK 0x00000080 /* Beacon use indication */
-#define MAC_DMA_Q_MISC_CBR_EXP_CNTR_LIMIT_MASK 0x00000100 /* CBR expired counter limit enable */
-#define MAC_DMA_Q_MISC_RDYTIME_EXP_POLICY_MASK 0x00000200 /* Enable TXE cleared on ReadyTime expired or VEOL */
-#define MAC_DMA_Q_MISC_RESET_CBR_EXP_CTR_MASK 0x00000400 /* Reset CBR expired counter */
-#define MAC_DMA_Q_MISC_DCU_EARLY_TERM_REQ_MASK 0x00000800 /* DCU frame early termination request control */
-
-#define MAC_DMA_Q0_STS_ADDRESS 0x00000A00 /* MAC Miscellaneous QCU status */
-#define MAC_DMA_Q1_STS_ADDRESS 0x00000A04 /* MAC Miscellaneous QCU status */
-#define MAC_DMA_Q2_STS_ADDRESS 0x00000A08 /* MAC Miscellaneous QCU status */
-#define MAC_DMA_Q3_STS_ADDRESS 0x00000A0C /* MAC Miscellaneous QCU status */
-#define MAC_DMA_Q4_STS_ADDRESS 0x00000A10 /* MAC Miscellaneous QCU status */
-#define MAC_DMA_Q5_STS_ADDRESS 0x00000A14 /* MAC Miscellaneous QCU status */
-#define MAC_DMA_Q6_STS_ADDRESS 0x00000A18 /* MAC Miscellaneous QCU status */
-#define MAC_DMA_Q7_STS_ADDRESS 0x00000A1C /* MAC Miscellaneous QCU status */
-#define MAC_DMA_Q8_STS_ADDRESS 0x00000A20 /* MAC Miscellaneous QCU status */
-#define MAC_DMA_Q9_STS_ADDRESS 0x00000A24 /* MAC Miscellaneous QCU status */
-#define MAC_DMA_QSTS_ADDRESS(_i) (MAC_DMA_Q0_STS_ADDRESS + ((_i)<<2))
-
-#define MAC_DMA_Q_STS_PEND_FR_CNT_MASK 0x00000003 /* Mask for Pending Frame Count */
-#define MAC_DMA_Q_STS_CBR_EXP_CNT_MASK 0x0000FF00 /* Mask for CBR expired counter */
-
-#define MAC_DMA_Q_RDYTIMESHDN_ADDRESS 0x00000A40 /* MAC ReadyTimeShutdown status */
-
-/* DCU registers */
-
-#define MAC_DMA_D0_QCUMASK_ADDRESS 0x00001000 /* MAC QCU Mask */
-#define MAC_DMA_D1_QCUMASK_ADDRESS 0x00001004 /* MAC QCU Mask */
-#define MAC_DMA_D2_QCUMASK_ADDRESS 0x00001008 /* MAC QCU Mask */
-#define MAC_DMA_D3_QCUMASK_ADDRESS 0x0000100C /* MAC QCU Mask */
-#define MAC_DMA_D4_QCUMASK_ADDRESS 0x00001010 /* MAC QCU Mask */
-#define MAC_DMA_D5_QCUMASK_ADDRESS 0x00001014 /* MAC QCU Mask */
-#define MAC_DMA_D6_QCUMASK_ADDRESS 0x00001018 /* MAC QCU Mask */
-#define MAC_DMA_D7_QCUMASK_ADDRESS 0x0000101C /* MAC QCU Mask */
-#define MAC_DMA_D8_QCUMASK_ADDRESS 0x00001020 /* MAC QCU Mask */
-#define MAC_DMA_D9_QCUMASK_ADDRESS 0x00001024 /* MAC QCU Mask */
-#define MAC_DMA_DQCUMASK_ADDRESS(_i) (MAC_DMA_D0_QCUMASK_ADDRESS + ((_i)<<2))
-
-#define MAC_DMA_D_QCUMASK_MASK 0x000003FF /* Mask for QCU Mask (QCU 0-9) */
-
-#define MAC_DMA_D_GBL_IFS_SIFS_ADDRESS 0x00001030 /* DCU global SIFS settings */
-
-
-#define MAC_DMA_D0_LCL_IFS_ADDRESS 0x00001040 /* MAC DCU-specific IFS settings */
-#define MAC_DMA_D1_LCL_IFS_ADDRESS 0x00001044 /* MAC DCU-specific IFS settings */
-#define MAC_DMA_D2_LCL_IFS_ADDRESS 0x00001048 /* MAC DCU-specific IFS settings */
-#define MAC_DMA_D3_LCL_IFS_ADDRESS 0x0000104C /* MAC DCU-specific IFS settings */
-#define MAC_DMA_D4_LCL_IFS_ADDRESS 0x00001050 /* MAC DCU-specific IFS settings */
-#define MAC_DMA_D5_LCL_IFS_ADDRESS 0x00001054 /* MAC DCU-specific IFS settings */
-#define MAC_DMA_D6_LCL_IFS_ADDRESS 0x00001058 /* MAC DCU-specific IFS settings */
-#define MAC_DMA_D7_LCL_IFS_ADDRESS 0x0000105C /* MAC DCU-specific IFS settings */
-#define MAC_DMA_D8_LCL_IFS_ADDRESS 0x00001060 /* MAC DCU-specific IFS settings */
-#define MAC_DMA_D9_LCL_IFS_ADDRESS 0x00001064 /* MAC DCU-specific IFS settings */
-#define MAC_DMA_DLCL_IFS_ADDRESS(_i) (MAC_DMA_D0_LCL_IFS_ADDRESS + ((_i)<<2))
-#define MAC_DMA_D_LCL_IFS_CWMIN_MASK 0x000003FF /* Mask for CW_MIN */
-#define MAC_DMA_D_LCL_IFS_CWMIN_LSB 0
-#define MAC_DMA_D_LCL_IFS_CWMAX_MASK 0x000FFC00 /* Mask for CW_MAX */
-#define MAC_DMA_D_LCL_IFS_CWMAX_LSB 10
-#define MAC_DMA_D_LCL_IFS_AIFS_MASK 0x0FF00000 /* Mask for AIFS */
-#define MAC_DMA_D_LCL_IFS_AIFS_LSB 20
-/*
- * Note: even though this field is 8 bits wide the
- * maximum supported AIFS value is 0xFc. Setting the AIFS value
- * to 0xFd 0xFe, or 0xFf will not work correctly and will cause
- * the DCU to hang.
- */
-#define MAC_DMA_D_GBL_IFS_SLOT_ADDRESS 0x00001070 /* DC global slot interval */
-
-#define MAC_DMA_D0_RETRY_LIMIT_ADDRESS 0x00001080 /* MAC Retry limits */
-#define MAC_DMA_D1_RETRY_LIMIT_ADDRESS 0x00001084 /* MAC Retry limits */
-#define MAC_DMA_D2_RETRY_LIMIT_ADDRESS 0x00001088 /* MAC Retry limits */
-#define MAC_DMA_D3_RETRY_LIMIT_ADDRESS 0x0000108C /* MAC Retry limits */
-#define MAC_DMA_D4_RETRY_LIMIT_ADDRESS 0x00001090 /* MAC Retry limits */
-#define MAC_DMA_D5_RETRY_LIMIT_ADDRESS 0x00001094 /* MAC Retry limits */
-#define MAC_DMA_D6_RETRY_LIMIT_ADDRESS 0x00001098 /* MAC Retry limits */
-#define MAC_DMA_D7_RETRY_LIMIT_ADDRESS 0x0000109C /* MAC Retry limits */
-#define MAC_DMA_D8_RETRY_LIMIT_ADDRESS 0x000010A0 /* MAC Retry limits */
-#define MAC_DMA_D9_RETRY_LIMIT_ADDRESS 0x000010A4 /* MAC Retry limits */
-#define MAC_DMA_DRETRY_LIMIT_ADDRESS(_i) (MAC_DMA_D0_RETRY_LIMIT_ADDRESS + ((_i)<<2))
-
-#define MAC_DMA_D_RETRY_LIMIT_FR_RTS_MASK 0x0000000F /* frame RTS failure limit */
-#define MAC_DMA_D_RETRY_LIMIT_FR_RTS_LSB 0
-#define MAC_DMA_D_RETRY_LIMIT_STA_RTS_MASK 0x00003F00 /* station RTS failure limit */
-#define MAC_DMA_D_RETRY_LIMIT_STA_RTS_LSB 8
-#define MAC_DMA_D_RETRY_LIMIT_STA_DATA_MASK 0x000FC000 /* station short retry limit */
-#define MAC_DMA_D_RETRY_LIMIT_STA_DATA_LSB 14
-
-#define MAC_DMA_D_GBL_IFS_EIFS_ADDRESS 0x000010B0 /* DCU global EIFS setting */
-
-#define MAC_DMA_D0_CHNTIME_ADDRESS 0x000010C0 /* MAC ChannelTime settings */
-#define MAC_DMA_D1_CHNTIME_ADDRESS 0x000010C4 /* MAC ChannelTime settings */
-#define MAC_DMA_D2_CHNTIME_ADDRESS 0x000010C8 /* MAC ChannelTime settings */
-#define MAC_DMA_D3_CHNTIME_ADDRESS 0x000010CC /* MAC ChannelTime settings */
-#define MAC_DMA_D4_CHNTIME_ADDRESS 0x000010D0 /* MAC ChannelTime settings */
-#define MAC_DMA_D5_CHNTIME_ADDRESS 0x000010D4 /* MAC ChannelTime settings */
-#define MAC_DMA_D6_CHNTIME_ADDRESS 0x000010D8 /* MAC ChannelTime settings */
-#define MAC_DMA_D7_CHNTIME_ADDRESS 0x000010DC /* MAC ChannelTime settings */
-#define MAC_DMA_D8_CHNTIME_ADDRESS 0x000010E0 /* MAC ChannelTime settings */
-#define MAC_DMA_D9_CHNTIME_ADDRESS 0x000010E4 /* MAC ChannelTime settings */
-#define MAC_DMA_DCHNTIME_ADDRESS(_i) (MAC_DMA_D0_CHNTIME_ADDRESS + ((_i)<<2))
-
-#define MAC_DMA_D_CHNTIME_DUR_MASK 0x000FFFFF /* ChannelTime duration (us) */
-#define MAC_DMA_D_CHNTIME_DUR_LSB 0 /* Shift for ChannelTime duration */
-#define MAC_DMA_D_CHNTIME_EN_MASK 0x00100000 /* ChannelTime enable */
-
-#define MAC_DMA_D_GBL_IFS_MISC_ADDRESS 0x000010f0 /* DCU global misc. IFS settings */
-#define MAC_DMA_D_GBL_IFS_MISC_LFSR_SLICE_SEL_MASK 0x00000007 /* LFSR slice select */
-#define MAC_DMA_D_GBL_IFS_MISC_TURBO_MODE_MASK 0x00000008 /* Turbo mode indication */
-#define MAC_DMA_D_GBL_IFS_MISC_DCU_ARBITER_DLY_MASK 0x00300000 /* DCU arbiter delay */
-#define MAC_DMA_D_GBL_IFS_IGNORE_BACKOFF_MASK 0x10000000
-
-#define MAC_DMA_D0_MISC_ADDRESS 0x00001100 /* MAC Miscellaneous DCU-specific settings */
-#define MAC_DMA_D1_MISC_ADDRESS 0x00001104 /* MAC Miscellaneous DCU-specific settings */
-#define MAC_DMA_D2_MISC_ADDRESS 0x00001108 /* MAC Miscellaneous DCU-specific settings */
-#define MAC_DMA_D3_MISC_ADDRESS 0x0000110C /* MAC Miscellaneous DCU-specific settings */
-#define MAC_DMA_D4_MISC_ADDRESS 0x00001110 /* MAC Miscellaneous DCU-specific settings */
-#define MAC_DMA_D5_MISC_ADDRESS 0x00001114 /* MAC Miscellaneous DCU-specific settings */
-#define MAC_DMA_D6_MISC_ADDRESS 0x00001118 /* MAC Miscellaneous DCU-specific settings */
-#define MAC_DMA_D7_MISC_ADDRESS 0x0000111C /* MAC Miscellaneous DCU-specific settings */
-#define MAC_DMA_D8_MISC_ADDRESS 0x00001120 /* MAC Miscellaneous DCU-specific settings */
-#define MAC_DMA_D9_MISC_ADDRESS 0x00001124 /* MAC Miscellaneous DCU-specific settings */
-#define MAC_DMA_DMISC_ADDRESS(_i) (MAC_DMA_D0_MISC_ADDRESS + ((_i)<<2))
-
-#define MAC_DMA_D0_EOL_ADDRESS 0x00001180
-#define MAC_DMA_D1_EOL_ADDRESS 0x00001184
-#define MAC_DMA_D2_EOL_ADDRESS 0x00001188
-#define MAC_DMA_D3_EOL_ADDRESS 0x0000118C
-#define MAC_DMA_D4_EOL_ADDRESS 0x00001190
-#define MAC_DMA_D5_EOL_ADDRESS 0x00001194
-#define MAC_DMA_D6_EOL_ADDRESS 0x00001198
-#define MAC_DMA_D7_EOL_ADDRESS 0x0000119C
-#define MAC_DMA_D8_EOL_ADDRESS 0x00001200
-#define MAC_DMA_D9_EOL_ADDRESS 0x00001204
-#define MAC_DMA_DEOL_ADDRESS(_i) (MAC_DMA_D0_EOL_ADDRESS + ((_i)<<2))
-
-#define MAC_DMA_D_MISC_BKOFF_THRESH_MASK 0x0000003F /* Backoff threshold */
-#define MAC_DMA_D_MISC_BACK_OFF_THRESH_LSB 0
-#define MAC_DMA_D_MISC_ETS_RTS_MASK 0x00000040 /* End of transmission series
- station RTS/data failure
- count reset policy */
-#define MAC_DMA_D_MISC_ETS_CW_MASK 0x00000080 /* End of transmission series
- CW reset policy */
-#define MAC_DMA_D_MISC_FRAG_WAIT_EN_MASK 0x00000100 /* Fragment Starvation Policy */
-
-#define MAC_DMA_D_MISC_FRAG_BKOFF_EN_MASK 0x00000200 /* Backoff during a frag burst */
-#define MAC_DMA_D_MISC_HCF_POLL_EN_MASK 0x00000800 /* HFC poll enable */
-#define MAC_DMA_D_MISC_BKOFF_PERSISTENCE_MASK 0x00001000 /* Backoff persistence factor
- setting */
-#define MAC_DMA_D_MISC_VIR_COL_HANDLING_MASK 0x0000C000 /* Mask for Virtual collision
- handling policy */
-#define MAC_DMA_D_MISC_VIR_COL_HANDLING_LSB 14
-#define MAC_DMA_D_MISC_VIR_COL_HANDLING_DEFAULT 0 /* Normal */
-#define MAC_DMA_D_MISC_VIR_COL_HANDLING_IGNORE 1 /* Ignore */
-#define MAC_DMA_D_MISC_BEACON_USE_MASK 0x00010000 /* Beacon use indication */
-#define MAC_DMA_D_MISC_ARB_LOCKOUT_CNTRL_MASK 0x00060000 /* Mask for DCU arbiter lockout control */
-#define MAC_DMA_D_MISC_ARB_LOCKOUT_CNTRL_LSB 17
-#define MAC_DMA_D_MISC_ARB_LOCKOUT_CNTRL_NONE 0 /* No lockout*/
-#define MAC_DMA_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR 1 /* Intra-frame*/
-#define MAC_DMA_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL 2 /* Global */
-#define MAC_DMA_D_MISC_ARB_LOCKOUT_IGNORE_MASK 0x00080000 /* DCU arbiter lockout ignore control */
-#define MAC_DMA_D_MISC_SEQ_NUM_INCR_DIS_MASK 0x00100000 /* Sequence number increment disable */
-#define MAC_DMA_D_MISC_POST_FR_BKOFF_DIS_MASK 0x00200000 /* Post-frame backoff disable */
-#define MAC_DMA_D_MISC_VIRT_COLL_POLICY_MASK 0x00400000 /* Virtual coll. handling policy */
-#define MAC_DMA_D_MISC_BLOWN_IFS_POLICY_MASK 0x00800000 /* Blown IFS handling policy */
-
-#define MAC_DMA_D_SEQNUM_ADDRESS 0x00001140 /* MAC Frame sequence number */
-
-
-
-#define MAC_DMA_D_FPCTL_ADDRESS 0x00001230 /* DCU frame prefetch settings */
-#define MAC_DMA_D_TXPSE_ADDRESS 0x00001270 /* DCU transmit pause control/status */
-
-#endif /* _AR6000_DMMAEG_H_ */
diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mac_pcu_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mac_pcu_reg.h
deleted file mode 100644
index 6ccb08c..0000000
--- a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mac_pcu_reg.h
+++ /dev/null
@@ -1,3065 +0,0 @@
-// ------------------------------------------------------------------
-// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
-//
-//
-// Permission to use, copy, modify, and/or distribute this software for any
-// purpose with or without fee is hereby granted, provided that the above
-// copyright notice and this permission notice appear in all copies.
-//
-// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-//
-//
-// ------------------------------------------------------------------
-//===================================================================
-// Author(s): ="Atheros"
-//===================================================================
-
-
-#ifndef _MAC_PCU_REG_H_
-#define _MAC_PCU_REG_H_
-
-#define MAC_PCU_STA_ADDR_L32_ADDRESS 0x00008000
-#define MAC_PCU_STA_ADDR_L32_OFFSET 0x00000000
-#define MAC_PCU_STA_ADDR_L32_ADDR_31_0_MSB 31
-#define MAC_PCU_STA_ADDR_L32_ADDR_31_0_LSB 0
-#define MAC_PCU_STA_ADDR_L32_ADDR_31_0_MASK 0xffffffff
-#define MAC_PCU_STA_ADDR_L32_ADDR_31_0_GET(x) (((x) & MAC_PCU_STA_ADDR_L32_ADDR_31_0_MASK) >> MAC_PCU_STA_ADDR_L32_ADDR_31_0_LSB)
-#define MAC_PCU_STA_ADDR_L32_ADDR_31_0_SET(x) (((x) << MAC_PCU_STA_ADDR_L32_ADDR_31_0_LSB) & MAC_PCU_STA_ADDR_L32_ADDR_31_0_MASK)
-
-#define MAC_PCU_STA_ADDR_U16_ADDRESS 0x00008004
-#define MAC_PCU_STA_ADDR_U16_OFFSET 0x00000004
-#define MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_MSB 31
-#define MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_LSB 31
-#define MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_MASK 0x80000000
-#define MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_MASK) >> MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_LSB)
-#define MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_LSB) & MAC_PCU_STA_ADDR_U16_ADHOC_MCAST_SEARCH_MASK)
-#define MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_MSB 30
-#define MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_LSB 30
-#define MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_MASK 0x40000000
-#define MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_MASK) >> MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_LSB)
-#define MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_LSB) & MAC_PCU_STA_ADDR_U16_CBCIV_ENDIAN_MASK)
-#define MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_MSB 29
-#define MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_LSB 29
-#define MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_MASK 0x20000000
-#define MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_MASK) >> MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_LSB)
-#define MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_LSB) & MAC_PCU_STA_ADDR_U16_PRESERVE_SEQNUM_MASK)
-#define MAC_PCU_STA_ADDR_U16_KSRCH_MODE_MSB 28
-#define MAC_PCU_STA_ADDR_U16_KSRCH_MODE_LSB 28
-#define MAC_PCU_STA_ADDR_U16_KSRCH_MODE_MASK 0x10000000
-#define MAC_PCU_STA_ADDR_U16_KSRCH_MODE_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_KSRCH_MODE_MASK) >> MAC_PCU_STA_ADDR_U16_KSRCH_MODE_LSB)
-#define MAC_PCU_STA_ADDR_U16_KSRCH_MODE_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_KSRCH_MODE_LSB) & MAC_PCU_STA_ADDR_U16_KSRCH_MODE_MASK)
-#define MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_MSB 27
-#define MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_LSB 27
-#define MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_MASK 0x08000000
-#define MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_MASK) >> MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_LSB)
-#define MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_LSB) & MAC_PCU_STA_ADDR_U16_CRPT_MIC_ENABLE_MASK)
-#define MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_MSB 26
-#define MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_LSB 26
-#define MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_MASK 0x04000000
-#define MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_MASK) >> MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_LSB)
-#define MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_LSB) & MAC_PCU_STA_ADDR_U16_SECTOR_SELF_GEN_MASK)
-#define MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_MSB 25
-#define MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_LSB 25
-#define MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_MASK 0x02000000
-#define MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_MASK) >> MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_LSB)
-#define MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_LSB) & MAC_PCU_STA_ADDR_U16_BASE_RATE_11B_MASK)
-#define MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_MSB 24
-#define MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_LSB 24
-#define MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_MASK 0x01000000
-#define MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_MASK) >> MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_LSB)
-#define MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_LSB) & MAC_PCU_STA_ADDR_U16_ACKCTS_6MB_MASK)
-#define MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_MSB 23
-#define MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_LSB 23
-#define MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_MASK 0x00800000
-#define MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_MASK) >> MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_LSB)
-#define MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_LSB) & MAC_PCU_STA_ADDR_U16_RTS_USE_DEF_MASK)
-#define MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_MSB 22
-#define MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_LSB 22
-#define MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_MASK 0x00400000
-#define MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_MASK) >> MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_LSB)
-#define MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_LSB) & MAC_PCU_STA_ADDR_U16_DEFANT_UPDATE_MASK)
-#define MAC_PCU_STA_ADDR_U16_USE_DEFANT_MSB 21
-#define MAC_PCU_STA_ADDR_U16_USE_DEFANT_LSB 21
-#define MAC_PCU_STA_ADDR_U16_USE_DEFANT_MASK 0x00200000
-#define MAC_PCU_STA_ADDR_U16_USE_DEFANT_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_USE_DEFANT_MASK) >> MAC_PCU_STA_ADDR_U16_USE_DEFANT_LSB)
-#define MAC_PCU_STA_ADDR_U16_USE_DEFANT_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_USE_DEFANT_LSB) & MAC_PCU_STA_ADDR_U16_USE_DEFANT_MASK)
-#define MAC_PCU_STA_ADDR_U16_PCF_MSB 20
-#define MAC_PCU_STA_ADDR_U16_PCF_LSB 20
-#define MAC_PCU_STA_ADDR_U16_PCF_MASK 0x00100000
-#define MAC_PCU_STA_ADDR_U16_PCF_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_PCF_MASK) >> MAC_PCU_STA_ADDR_U16_PCF_LSB)
-#define MAC_PCU_STA_ADDR_U16_PCF_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_PCF_LSB) & MAC_PCU_STA_ADDR_U16_PCF_MASK)
-#define MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_MSB 19
-#define MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_LSB 19
-#define MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_MASK 0x00080000
-#define MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_MASK) >> MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_LSB)
-#define MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_LSB) & MAC_PCU_STA_ADDR_U16_KEYSRCH_DIS_MASK)
-#define MAC_PCU_STA_ADDR_U16_PW_SAVE_MSB 18
-#define MAC_PCU_STA_ADDR_U16_PW_SAVE_LSB 18
-#define MAC_PCU_STA_ADDR_U16_PW_SAVE_MASK 0x00040000
-#define MAC_PCU_STA_ADDR_U16_PW_SAVE_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_PW_SAVE_MASK) >> MAC_PCU_STA_ADDR_U16_PW_SAVE_LSB)
-#define MAC_PCU_STA_ADDR_U16_PW_SAVE_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_PW_SAVE_LSB) & MAC_PCU_STA_ADDR_U16_PW_SAVE_MASK)
-#define MAC_PCU_STA_ADDR_U16_ADHOC_MSB 17
-#define MAC_PCU_STA_ADDR_U16_ADHOC_LSB 17
-#define MAC_PCU_STA_ADDR_U16_ADHOC_MASK 0x00020000
-#define MAC_PCU_STA_ADDR_U16_ADHOC_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_ADHOC_MASK) >> MAC_PCU_STA_ADDR_U16_ADHOC_LSB)
-#define MAC_PCU_STA_ADDR_U16_ADHOC_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_ADHOC_LSB) & MAC_PCU_STA_ADDR_U16_ADHOC_MASK)
-#define MAC_PCU_STA_ADDR_U16_STA_AP_MSB 16
-#define MAC_PCU_STA_ADDR_U16_STA_AP_LSB 16
-#define MAC_PCU_STA_ADDR_U16_STA_AP_MASK 0x00010000
-#define MAC_PCU_STA_ADDR_U16_STA_AP_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_STA_AP_MASK) >> MAC_PCU_STA_ADDR_U16_STA_AP_LSB)
-#define MAC_PCU_STA_ADDR_U16_STA_AP_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_STA_AP_LSB) & MAC_PCU_STA_ADDR_U16_STA_AP_MASK)
-#define MAC_PCU_STA_ADDR_U16_ADDR_47_32_MSB 15
-#define MAC_PCU_STA_ADDR_U16_ADDR_47_32_LSB 0
-#define MAC_PCU_STA_ADDR_U16_ADDR_47_32_MASK 0x0000ffff
-#define MAC_PCU_STA_ADDR_U16_ADDR_47_32_GET(x) (((x) & MAC_PCU_STA_ADDR_U16_ADDR_47_32_MASK) >> MAC_PCU_STA_ADDR_U16_ADDR_47_32_LSB)
-#define MAC_PCU_STA_ADDR_U16_ADDR_47_32_SET(x) (((x) << MAC_PCU_STA_ADDR_U16_ADDR_47_32_LSB) & MAC_PCU_STA_ADDR_U16_ADDR_47_32_MASK)
-
-#define MAC_PCU_BSSID_L32_ADDRESS 0x00008008
-#define MAC_PCU_BSSID_L32_OFFSET 0x00000008
-#define MAC_PCU_BSSID_L32_ADDR_MSB 31
-#define MAC_PCU_BSSID_L32_ADDR_LSB 0
-#define MAC_PCU_BSSID_L32_ADDR_MASK 0xffffffff
-#define MAC_PCU_BSSID_L32_ADDR_GET(x) (((x) & MAC_PCU_BSSID_L32_ADDR_MASK) >> MAC_PCU_BSSID_L32_ADDR_LSB)
-#define MAC_PCU_BSSID_L32_ADDR_SET(x) (((x) << MAC_PCU_BSSID_L32_ADDR_LSB) & MAC_PCU_BSSID_L32_ADDR_MASK)
-
-#define MAC_PCU_BSSID_U16_ADDRESS 0x0000800c
-#define MAC_PCU_BSSID_U16_OFFSET 0x0000000c
-#define MAC_PCU_BSSID_U16_AID_MSB 26
-#define MAC_PCU_BSSID_U16_AID_LSB 16
-#define MAC_PCU_BSSID_U16_AID_MASK 0x07ff0000
-#define MAC_PCU_BSSID_U16_AID_GET(x) (((x) & MAC_PCU_BSSID_U16_AID_MASK) >> MAC_PCU_BSSID_U16_AID_LSB)
-#define MAC_PCU_BSSID_U16_AID_SET(x) (((x) << MAC_PCU_BSSID_U16_AID_LSB) & MAC_PCU_BSSID_U16_AID_MASK)
-#define MAC_PCU_BSSID_U16_ADDR_MSB 15
-#define MAC_PCU_BSSID_U16_ADDR_LSB 0
-#define MAC_PCU_BSSID_U16_ADDR_MASK 0x0000ffff
-#define MAC_PCU_BSSID_U16_ADDR_GET(x) (((x) & MAC_PCU_BSSID_U16_ADDR_MASK) >> MAC_PCU_BSSID_U16_ADDR_LSB)
-#define MAC_PCU_BSSID_U16_ADDR_SET(x) (((x) << MAC_PCU_BSSID_U16_ADDR_LSB) & MAC_PCU_BSSID_U16_ADDR_MASK)
-
-#define MAC_PCU_BCN_RSSI_AVE_ADDRESS 0x00008010
-#define MAC_PCU_BCN_RSSI_AVE_OFFSET 0x00000010
-#define MAC_PCU_BCN_RSSI_AVE_VALUE_MSB 11
-#define MAC_PCU_BCN_RSSI_AVE_VALUE_LSB 0
-#define MAC_PCU_BCN_RSSI_AVE_VALUE_MASK 0x00000fff
-#define MAC_PCU_BCN_RSSI_AVE_VALUE_GET(x) (((x) & MAC_PCU_BCN_RSSI_AVE_VALUE_MASK) >> MAC_PCU_BCN_RSSI_AVE_VALUE_LSB)
-#define MAC_PCU_BCN_RSSI_AVE_VALUE_SET(x) (((x) << MAC_PCU_BCN_RSSI_AVE_VALUE_LSB) & MAC_PCU_BCN_RSSI_AVE_VALUE_MASK)
-
-#define MAC_PCU_ACK_CTS_TIMEOUT_ADDRESS 0x00008014
-#define MAC_PCU_ACK_CTS_TIMEOUT_OFFSET 0x00000014
-#define MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_MSB 29
-#define MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_LSB 16
-#define MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_MASK 0x3fff0000
-#define MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_GET(x) (((x) & MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_MASK) >> MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_LSB)
-#define MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_SET(x) (((x) << MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_LSB) & MAC_PCU_ACK_CTS_TIMEOUT_CTS_TIMEOUT_MASK)
-#define MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_MSB 13
-#define MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_LSB 0
-#define MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_MASK 0x00003fff
-#define MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_GET(x) (((x) & MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_MASK) >> MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_LSB)
-#define MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_SET(x) (((x) << MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_LSB) & MAC_PCU_ACK_CTS_TIMEOUT_ACK_TIMEOUT_MASK)
-
-#define MAC_PCU_BCN_RSSI_CTL_ADDRESS 0x00008018
-#define MAC_PCU_BCN_RSSI_CTL_OFFSET 0x00000018
-#define MAC_PCU_BCN_RSSI_CTL_RESET_MSB 29
-#define MAC_PCU_BCN_RSSI_CTL_RESET_LSB 29
-#define MAC_PCU_BCN_RSSI_CTL_RESET_MASK 0x20000000
-#define MAC_PCU_BCN_RSSI_CTL_RESET_GET(x) (((x) & MAC_PCU_BCN_RSSI_CTL_RESET_MASK) >> MAC_PCU_BCN_RSSI_CTL_RESET_LSB)
-#define MAC_PCU_BCN_RSSI_CTL_RESET_SET(x) (((x) << MAC_PCU_BCN_RSSI_CTL_RESET_LSB) & MAC_PCU_BCN_RSSI_CTL_RESET_MASK)
-#define MAC_PCU_BCN_RSSI_CTL_WEIGHT_MSB 28
-#define MAC_PCU_BCN_RSSI_CTL_WEIGHT_LSB 24
-#define MAC_PCU_BCN_RSSI_CTL_WEIGHT_MASK 0x1f000000
-#define MAC_PCU_BCN_RSSI_CTL_WEIGHT_GET(x) (((x) & MAC_PCU_BCN_RSSI_CTL_WEIGHT_MASK) >> MAC_PCU_BCN_RSSI_CTL_WEIGHT_LSB)
-#define MAC_PCU_BCN_RSSI_CTL_WEIGHT_SET(x) (((x) << MAC_PCU_BCN_RSSI_CTL_WEIGHT_LSB) & MAC_PCU_BCN_RSSI_CTL_WEIGHT_MASK)
-#define MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_MSB 23
-#define MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_LSB 16
-#define MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_MASK 0x00ff0000
-#define MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_GET(x) (((x) & MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_MASK) >> MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_LSB)
-#define MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_SET(x) (((x) << MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_LSB) & MAC_PCU_BCN_RSSI_CTL_RSSI_HIGH_THRESH_MASK)
-#define MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_MSB 15
-#define MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_LSB 8
-#define MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_MASK 0x0000ff00
-#define MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_GET(x) (((x) & MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_MASK) >> MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_LSB)
-#define MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_SET(x) (((x) << MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_LSB) & MAC_PCU_BCN_RSSI_CTL_MISS_THRESH_MASK)
-#define MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_MSB 7
-#define MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_LSB 0
-#define MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_MASK 0x000000ff
-#define MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_GET(x) (((x) & MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_MASK) >> MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_LSB)
-#define MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_SET(x) (((x) << MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_LSB) & MAC_PCU_BCN_RSSI_CTL_RSSI_LOW_THRESH_MASK)
-
-#define MAC_PCU_USEC_LATENCY_ADDRESS 0x0000801c
-#define MAC_PCU_USEC_LATENCY_OFFSET 0x0000001c
-#define MAC_PCU_USEC_LATENCY_RX_LATENCY_MSB 28
-#define MAC_PCU_USEC_LATENCY_RX_LATENCY_LSB 23
-#define MAC_PCU_USEC_LATENCY_RX_LATENCY_MASK 0x1f800000
-#define MAC_PCU_USEC_LATENCY_RX_LATENCY_GET(x) (((x) & MAC_PCU_USEC_LATENCY_RX_LATENCY_MASK) >> MAC_PCU_USEC_LATENCY_RX_LATENCY_LSB)
-#define MAC_PCU_USEC_LATENCY_RX_LATENCY_SET(x) (((x) << MAC_PCU_USEC_LATENCY_RX_LATENCY_LSB) & MAC_PCU_USEC_LATENCY_RX_LATENCY_MASK)
-#define MAC_PCU_USEC_LATENCY_TX_LATENCY_MSB 22
-#define MAC_PCU_USEC_LATENCY_TX_LATENCY_LSB 14
-#define MAC_PCU_USEC_LATENCY_TX_LATENCY_MASK 0x007fc000
-#define MAC_PCU_USEC_LATENCY_TX_LATENCY_GET(x) (((x) & MAC_PCU_USEC_LATENCY_TX_LATENCY_MASK) >> MAC_PCU_USEC_LATENCY_TX_LATENCY_LSB)
-#define MAC_PCU_USEC_LATENCY_TX_LATENCY_SET(x) (((x) << MAC_PCU_USEC_LATENCY_TX_LATENCY_LSB) & MAC_PCU_USEC_LATENCY_TX_LATENCY_MASK)
-#define MAC_PCU_USEC_LATENCY_USEC_MSB 7
-#define MAC_PCU_USEC_LATENCY_USEC_LSB 0
-#define MAC_PCU_USEC_LATENCY_USEC_MASK 0x000000ff
-#define MAC_PCU_USEC_LATENCY_USEC_GET(x) (((x) & MAC_PCU_USEC_LATENCY_USEC_MASK) >> MAC_PCU_USEC_LATENCY_USEC_LSB)
-#define MAC_PCU_USEC_LATENCY_USEC_SET(x) (((x) << MAC_PCU_USEC_LATENCY_USEC_LSB) & MAC_PCU_USEC_LATENCY_USEC_MASK)
-
-#define PCU_MAX_CFP_DUR_ADDRESS 0x00008020
-#define PCU_MAX_CFP_DUR_OFFSET 0x00000020
-#define PCU_MAX_CFP_DUR_VALUE_MSB 15
-#define PCU_MAX_CFP_DUR_VALUE_LSB 0
-#define PCU_MAX_CFP_DUR_VALUE_MASK 0x0000ffff
-#define PCU_MAX_CFP_DUR_VALUE_GET(x) (((x) & PCU_MAX_CFP_DUR_VALUE_MASK) >> PCU_MAX_CFP_DUR_VALUE_LSB)
-#define PCU_MAX_CFP_DUR_VALUE_SET(x) (((x) << PCU_MAX_CFP_DUR_VALUE_LSB) & PCU_MAX_CFP_DUR_VALUE_MASK)
-
-#define MAC_PCU_RX_FILTER_ADDRESS 0x00008024
-#define MAC_PCU_RX_FILTER_OFFSET 0x00000024
-#define MAC_PCU_RX_FILTER_GENERIC_FILTER_MSB 25
-#define MAC_PCU_RX_FILTER_GENERIC_FILTER_LSB 24
-#define MAC_PCU_RX_FILTER_GENERIC_FILTER_MASK 0x03000000
-#define MAC_PCU_RX_FILTER_GENERIC_FILTER_GET(x) (((x) & MAC_PCU_RX_FILTER_GENERIC_FILTER_MASK) >> MAC_PCU_RX_FILTER_GENERIC_FILTER_LSB)
-#define MAC_PCU_RX_FILTER_GENERIC_FILTER_SET(x) (((x) << MAC_PCU_RX_FILTER_GENERIC_FILTER_LSB) & MAC_PCU_RX_FILTER_GENERIC_FILTER_MASK)
-#define MAC_PCU_RX_FILTER_GENERIC_FTYPE_MSB 23
-#define MAC_PCU_RX_FILTER_GENERIC_FTYPE_LSB 18
-#define MAC_PCU_RX_FILTER_GENERIC_FTYPE_MASK 0x00fc0000
-#define MAC_PCU_RX_FILTER_GENERIC_FTYPE_GET(x) (((x) & MAC_PCU_RX_FILTER_GENERIC_FTYPE_MASK) >> MAC_PCU_RX_FILTER_GENERIC_FTYPE_LSB)
-#define MAC_PCU_RX_FILTER_GENERIC_FTYPE_SET(x) (((x) << MAC_PCU_RX_FILTER_GENERIC_FTYPE_LSB) & MAC_PCU_RX_FILTER_GENERIC_FTYPE_MASK)
-#define MAC_PCU_RX_FILTER_FROM_TO_DS_MSB 17
-#define MAC_PCU_RX_FILTER_FROM_TO_DS_LSB 17
-#define MAC_PCU_RX_FILTER_FROM_TO_DS_MASK 0x00020000
-#define MAC_PCU_RX_FILTER_FROM_TO_DS_GET(x) (((x) & MAC_PCU_RX_FILTER_FROM_TO_DS_MASK) >> MAC_PCU_RX_FILTER_FROM_TO_DS_LSB)
-#define MAC_PCU_RX_FILTER_FROM_TO_DS_SET(x) (((x) << MAC_PCU_RX_FILTER_FROM_TO_DS_LSB) & MAC_PCU_RX_FILTER_FROM_TO_DS_MASK)
-#define MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_MSB 16
-#define MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_LSB 16
-#define MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_MASK 0x00010000
-#define MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_GET(x) (((x) & MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_MASK) >> MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_LSB)
-#define MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_SET(x) (((x) << MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_LSB) & MAC_PCU_RX_FILTER_RST_DLMTR_CNT_DISABLE_MASK)
-#define MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_MSB 15
-#define MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_LSB 15
-#define MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_MASK 0x00008000
-#define MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_GET(x) (((x) & MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_MASK) >> MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_LSB)
-#define MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_SET(x) (((x) << MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_LSB) & MAC_PCU_RX_FILTER_MCAST_BCAST_ALL_MASK)
-#define MAC_PCU_RX_FILTER_PS_POLL_MSB 14
-#define MAC_PCU_RX_FILTER_PS_POLL_LSB 14
-#define MAC_PCU_RX_FILTER_PS_POLL_MASK 0x00004000
-#define MAC_PCU_RX_FILTER_PS_POLL_GET(x) (((x) & MAC_PCU_RX_FILTER_PS_POLL_MASK) >> MAC_PCU_RX_FILTER_PS_POLL_LSB)
-#define MAC_PCU_RX_FILTER_PS_POLL_SET(x) (((x) << MAC_PCU_RX_FILTER_PS_POLL_LSB) & MAC_PCU_RX_FILTER_PS_POLL_MASK)
-#define MAC_PCU_RX_FILTER_ASSUME_RADAR_MSB 13
-#define MAC_PCU_RX_FILTER_ASSUME_RADAR_LSB 13
-#define MAC_PCU_RX_FILTER_ASSUME_RADAR_MASK 0x00002000
-#define MAC_PCU_RX_FILTER_ASSUME_RADAR_GET(x) (((x) & MAC_PCU_RX_FILTER_ASSUME_RADAR_MASK) >> MAC_PCU_RX_FILTER_ASSUME_RADAR_LSB)
-#define MAC_PCU_RX_FILTER_ASSUME_RADAR_SET(x) (((x) << MAC_PCU_RX_FILTER_ASSUME_RADAR_LSB) & MAC_PCU_RX_FILTER_ASSUME_RADAR_MASK)
-#define MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_MSB 12
-#define MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_LSB 12
-#define MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_MASK 0x00001000
-#define MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_GET(x) (((x) & MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_MASK) >> MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_LSB)
-#define MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_SET(x) (((x) << MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_LSB) & MAC_PCU_RX_FILTER_UNCOMPRESSED_BA_BAR_MASK)
-#define MAC_PCU_RX_FILTER_COMPRESSED_BA_MSB 11
-#define MAC_PCU_RX_FILTER_COMPRESSED_BA_LSB 11
-#define MAC_PCU_RX_FILTER_COMPRESSED_BA_MASK 0x00000800
-#define MAC_PCU_RX_FILTER_COMPRESSED_BA_GET(x) (((x) & MAC_PCU_RX_FILTER_COMPRESSED_BA_MASK) >> MAC_PCU_RX_FILTER_COMPRESSED_BA_LSB)
-#define MAC_PCU_RX_FILTER_COMPRESSED_BA_SET(x) (((x) << MAC_PCU_RX_FILTER_COMPRESSED_BA_LSB) & MAC_PCU_RX_FILTER_COMPRESSED_BA_MASK)
-#define MAC_PCU_RX_FILTER_COMPRESSED_BAR_MSB 10
-#define MAC_PCU_RX_FILTER_COMPRESSED_BAR_LSB 10
-#define MAC_PCU_RX_FILTER_COMPRESSED_BAR_MASK 0x00000400
-#define MAC_PCU_RX_FILTER_COMPRESSED_BAR_GET(x) (((x) & MAC_PCU_RX_FILTER_COMPRESSED_BAR_MASK) >> MAC_PCU_RX_FILTER_COMPRESSED_BAR_LSB)
-#define MAC_PCU_RX_FILTER_COMPRESSED_BAR_SET(x) (((x) << MAC_PCU_RX_FILTER_COMPRESSED_BAR_LSB) & MAC_PCU_RX_FILTER_COMPRESSED_BAR_MASK)
-#define MAC_PCU_RX_FILTER_MY_BEACON_MSB 9
-#define MAC_PCU_RX_FILTER_MY_BEACON_LSB 9
-#define MAC_PCU_RX_FILTER_MY_BEACON_MASK 0x00000200
-#define MAC_PCU_RX_FILTER_MY_BEACON_GET(x) (((x) & MAC_PCU_RX_FILTER_MY_BEACON_MASK) >> MAC_PCU_RX_FILTER_MY_BEACON_LSB)
-#define MAC_PCU_RX_FILTER_MY_BEACON_SET(x) (((x) << MAC_PCU_RX_FILTER_MY_BEACON_LSB) & MAC_PCU_RX_FILTER_MY_BEACON_MASK)
-#define MAC_PCU_RX_FILTER_SYNC_FRAME_MSB 8
-#define MAC_PCU_RX_FILTER_SYNC_FRAME_LSB 8
-#define MAC_PCU_RX_FILTER_SYNC_FRAME_MASK 0x00000100
-#define MAC_PCU_RX_FILTER_SYNC_FRAME_GET(x) (((x) & MAC_PCU_RX_FILTER_SYNC_FRAME_MASK) >> MAC_PCU_RX_FILTER_SYNC_FRAME_LSB)
-#define MAC_PCU_RX_FILTER_SYNC_FRAME_SET(x) (((x) << MAC_PCU_RX_FILTER_SYNC_FRAME_LSB) & MAC_PCU_RX_FILTER_SYNC_FRAME_MASK)
-#define MAC_PCU_RX_FILTER_PROBE_REQ_MSB 7
-#define MAC_PCU_RX_FILTER_PROBE_REQ_LSB 7
-#define MAC_PCU_RX_FILTER_PROBE_REQ_MASK 0x00000080
-#define MAC_PCU_RX_FILTER_PROBE_REQ_GET(x) (((x) & MAC_PCU_RX_FILTER_PROBE_REQ_MASK) >> MAC_PCU_RX_FILTER_PROBE_REQ_LSB)
-#define MAC_PCU_RX_FILTER_PROBE_REQ_SET(x) (((x) << MAC_PCU_RX_FILTER_PROBE_REQ_LSB) & MAC_PCU_RX_FILTER_PROBE_REQ_MASK)
-#define MAC_PCU_RX_FILTER_XR_POLL_MSB 6
-#define MAC_PCU_RX_FILTER_XR_POLL_LSB 6
-#define MAC_PCU_RX_FILTER_XR_POLL_MASK 0x00000040
-#define MAC_PCU_RX_FILTER_XR_POLL_GET(x) (((x) & MAC_PCU_RX_FILTER_XR_POLL_MASK) >> MAC_PCU_RX_FILTER_XR_POLL_LSB)
-#define MAC_PCU_RX_FILTER_XR_POLL_SET(x) (((x) << MAC_PCU_RX_FILTER_XR_POLL_LSB) & MAC_PCU_RX_FILTER_XR_POLL_MASK)
-#define MAC_PCU_RX_FILTER_PROMISCUOUS_MSB 5
-#define MAC_PCU_RX_FILTER_PROMISCUOUS_LSB 5
-#define MAC_PCU_RX_FILTER_PROMISCUOUS_MASK 0x00000020
-#define MAC_PCU_RX_FILTER_PROMISCUOUS_GET(x) (((x) & MAC_PCU_RX_FILTER_PROMISCUOUS_MASK) >> MAC_PCU_RX_FILTER_PROMISCUOUS_LSB)
-#define MAC_PCU_RX_FILTER_PROMISCUOUS_SET(x) (((x) << MAC_PCU_RX_FILTER_PROMISCUOUS_LSB) & MAC_PCU_RX_FILTER_PROMISCUOUS_MASK)
-#define MAC_PCU_RX_FILTER_BEACON_MSB 4
-#define MAC_PCU_RX_FILTER_BEACON_LSB 4
-#define MAC_PCU_RX_FILTER_BEACON_MASK 0x00000010
-#define MAC_PCU_RX_FILTER_BEACON_GET(x) (((x) & MAC_PCU_RX_FILTER_BEACON_MASK) >> MAC_PCU_RX_FILTER_BEACON_LSB)
-#define MAC_PCU_RX_FILTER_BEACON_SET(x) (((x) << MAC_PCU_RX_FILTER_BEACON_LSB) & MAC_PCU_RX_FILTER_BEACON_MASK)
-#define MAC_PCU_RX_FILTER_CONTROL_MSB 3
-#define MAC_PCU_RX_FILTER_CONTROL_LSB 3
-#define MAC_PCU_RX_FILTER_CONTROL_MASK 0x00000008
-#define MAC_PCU_RX_FILTER_CONTROL_GET(x) (((x) & MAC_PCU_RX_FILTER_CONTROL_MASK) >> MAC_PCU_RX_FILTER_CONTROL_LSB)
-#define MAC_PCU_RX_FILTER_CONTROL_SET(x) (((x) << MAC_PCU_RX_FILTER_CONTROL_LSB) & MAC_PCU_RX_FILTER_CONTROL_MASK)
-#define MAC_PCU_RX_FILTER_BROADCAST_MSB 2
-#define MAC_PCU_RX_FILTER_BROADCAST_LSB 2
-#define MAC_PCU_RX_FILTER_BROADCAST_MASK 0x00000004
-#define MAC_PCU_RX_FILTER_BROADCAST_GET(x) (((x) & MAC_PCU_RX_FILTER_BROADCAST_MASK) >> MAC_PCU_RX_FILTER_BROADCAST_LSB)
-#define MAC_PCU_RX_FILTER_BROADCAST_SET(x) (((x) << MAC_PCU_RX_FILTER_BROADCAST_LSB) & MAC_PCU_RX_FILTER_BROADCAST_MASK)
-#define MAC_PCU_RX_FILTER_MULTICAST_MSB 1
-#define MAC_PCU_RX_FILTER_MULTICAST_LSB 1
-#define MAC_PCU_RX_FILTER_MULTICAST_MASK 0x00000002
-#define MAC_PCU_RX_FILTER_MULTICAST_GET(x) (((x) & MAC_PCU_RX_FILTER_MULTICAST_MASK) >> MAC_PCU_RX_FILTER_MULTICAST_LSB)
-#define MAC_PCU_RX_FILTER_MULTICAST_SET(x) (((x) << MAC_PCU_RX_FILTER_MULTICAST_LSB) & MAC_PCU_RX_FILTER_MULTICAST_MASK)
-#define MAC_PCU_RX_FILTER_UNICAST_MSB 0
-#define MAC_PCU_RX_FILTER_UNICAST_LSB 0
-#define MAC_PCU_RX_FILTER_UNICAST_MASK 0x00000001
-#define MAC_PCU_RX_FILTER_UNICAST_GET(x) (((x) & MAC_PCU_RX_FILTER_UNICAST_MASK) >> MAC_PCU_RX_FILTER_UNICAST_LSB)
-#define MAC_PCU_RX_FILTER_UNICAST_SET(x) (((x) << MAC_PCU_RX_FILTER_UNICAST_LSB) & MAC_PCU_RX_FILTER_UNICAST_MASK)
-
-#define MAC_PCU_MCAST_FILTER_L32_ADDRESS 0x00008028
-#define MAC_PCU_MCAST_FILTER_L32_OFFSET 0x00000028
-#define MAC_PCU_MCAST_FILTER_L32_VALUE_MSB 31
-#define MAC_PCU_MCAST_FILTER_L32_VALUE_LSB 0
-#define MAC_PCU_MCAST_FILTER_L32_VALUE_MASK 0xffffffff
-#define MAC_PCU_MCAST_FILTER_L32_VALUE_GET(x) (((x) & MAC_PCU_MCAST_FILTER_L32_VALUE_MASK) >> MAC_PCU_MCAST_FILTER_L32_VALUE_LSB)
-#define MAC_PCU_MCAST_FILTER_L32_VALUE_SET(x) (((x) << MAC_PCU_MCAST_FILTER_L32_VALUE_LSB) & MAC_PCU_MCAST_FILTER_L32_VALUE_MASK)
-
-#define MAC_PCU_MCAST_FILTER_U32_ADDRESS 0x0000802c
-#define MAC_PCU_MCAST_FILTER_U32_OFFSET 0x0000002c
-#define MAC_PCU_MCAST_FILTER_U32_VALUE_MSB 31
-#define MAC_PCU_MCAST_FILTER_U32_VALUE_LSB 0
-#define MAC_PCU_MCAST_FILTER_U32_VALUE_MASK 0xffffffff
-#define MAC_PCU_MCAST_FILTER_U32_VALUE_GET(x) (((x) & MAC_PCU_MCAST_FILTER_U32_VALUE_MASK) >> MAC_PCU_MCAST_FILTER_U32_VALUE_LSB)
-#define MAC_PCU_MCAST_FILTER_U32_VALUE_SET(x) (((x) << MAC_PCU_MCAST_FILTER_U32_VALUE_LSB) & MAC_PCU_MCAST_FILTER_U32_VALUE_MASK)
-
-#define MAC_PCU_DIAG_SW_ADDRESS 0x00008030
-#define MAC_PCU_DIAG_SW_OFFSET 0x00000030
-#define MAC_PCU_DIAG_SW_DEBUG_MODE_MSB 31
-#define MAC_PCU_DIAG_SW_DEBUG_MODE_LSB 30
-#define MAC_PCU_DIAG_SW_DEBUG_MODE_MASK 0xc0000000
-#define MAC_PCU_DIAG_SW_DEBUG_MODE_GET(x) (((x) & MAC_PCU_DIAG_SW_DEBUG_MODE_MASK) >> MAC_PCU_DIAG_SW_DEBUG_MODE_LSB)
-#define MAC_PCU_DIAG_SW_DEBUG_MODE_SET(x) (((x) << MAC_PCU_DIAG_SW_DEBUG_MODE_LSB) & MAC_PCU_DIAG_SW_DEBUG_MODE_MASK)
-#define MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_MSB 29
-#define MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_LSB 29
-#define MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_MASK 0x20000000
-#define MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_GET(x) (((x) & MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_MASK) >> MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_LSB)
-#define MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_SET(x) (((x) << MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_LSB) & MAC_PCU_DIAG_SW_RX_CLEAR_EXT_LOW_MASK)
-#define MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_MSB 28
-#define MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_LSB 28
-#define MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_MASK 0x10000000
-#define MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_GET(x) (((x) & MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_MASK) >> MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_LSB)
-#define MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_SET(x) (((x) << MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_LSB) & MAC_PCU_DIAG_SW_RX_CLEAR_CTL_LOW_MASK)
-#define MAC_PCU_DIAG_SW_OBS_SEL_2_MSB 27
-#define MAC_PCU_DIAG_SW_OBS_SEL_2_LSB 27
-#define MAC_PCU_DIAG_SW_OBS_SEL_2_MASK 0x08000000
-#define MAC_PCU_DIAG_SW_OBS_SEL_2_GET(x) (((x) & MAC_PCU_DIAG_SW_OBS_SEL_2_MASK) >> MAC_PCU_DIAG_SW_OBS_SEL_2_LSB)
-#define MAC_PCU_DIAG_SW_OBS_SEL_2_SET(x) (((x) << MAC_PCU_DIAG_SW_OBS_SEL_2_LSB) & MAC_PCU_DIAG_SW_OBS_SEL_2_MASK)
-#define MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_MSB 26
-#define MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_LSB 26
-#define MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_MASK 0x04000000
-#define MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_GET(x) (((x) & MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_MASK) >> MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_LSB)
-#define MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_SET(x) (((x) << MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_LSB) & MAC_PCU_DIAG_SW_SATURATE_CYCLE_CNT_MASK)
-#define MAC_PCU_DIAG_SW_FORCE_RX_ABORT_MSB 25
-#define MAC_PCU_DIAG_SW_FORCE_RX_ABORT_LSB 25
-#define MAC_PCU_DIAG_SW_FORCE_RX_ABORT_MASK 0x02000000
-#define MAC_PCU_DIAG_SW_FORCE_RX_ABORT_GET(x) (((x) & MAC_PCU_DIAG_SW_FORCE_RX_ABORT_MASK) >> MAC_PCU_DIAG_SW_FORCE_RX_ABORT_LSB)
-#define MAC_PCU_DIAG_SW_FORCE_RX_ABORT_SET(x) (((x) << MAC_PCU_DIAG_SW_FORCE_RX_ABORT_LSB) & MAC_PCU_DIAG_SW_FORCE_RX_ABORT_MASK)
-#define MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_MSB 24
-#define MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_LSB 24
-#define MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_MASK 0x01000000
-#define MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_GET(x) (((x) & MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_MASK) >> MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_LSB)
-#define MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_SET(x) (((x) << MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_LSB) & MAC_PCU_DIAG_SW_DUAL_CHAIN_CHAN_INFO_MASK)
-#define MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_MSB 23
-#define MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_LSB 23
-#define MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_MASK 0x00800000
-#define MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_GET(x) (((x) & MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_MASK) >> MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_LSB)
-#define MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_SET(x) (((x) << MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_LSB) & MAC_PCU_DIAG_SW_PHYERR_ENABLE_EIFS_CTL_MASK)
-#define MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_MSB 22
-#define MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_LSB 22
-#define MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_MASK 0x00400000
-#define MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_GET(x) (((x) & MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_MASK) >> MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_LSB)
-#define MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_SET(x) (((x) << MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_LSB) & MAC_PCU_DIAG_SW_CHAN_IDLE_HIGH_MASK)
-#define MAC_PCU_DIAG_SW_IGNORE_NAV_MSB 21
-#define MAC_PCU_DIAG_SW_IGNORE_NAV_LSB 21
-#define MAC_PCU_DIAG_SW_IGNORE_NAV_MASK 0x00200000
-#define MAC_PCU_DIAG_SW_IGNORE_NAV_GET(x) (((x) & MAC_PCU_DIAG_SW_IGNORE_NAV_MASK) >> MAC_PCU_DIAG_SW_IGNORE_NAV_LSB)
-#define MAC_PCU_DIAG_SW_IGNORE_NAV_SET(x) (((x) << MAC_PCU_DIAG_SW_IGNORE_NAV_LSB) & MAC_PCU_DIAG_SW_IGNORE_NAV_MASK)
-#define MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_MSB 20
-#define MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_LSB 20
-#define MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_MASK 0x00100000
-#define MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_GET(x) (((x) & MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_MASK) >> MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_LSB)
-#define MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_SET(x) (((x) << MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_LSB) & MAC_PCU_DIAG_SW_RX_CLEAR_HIGH_MASK)
-#define MAC_PCU_DIAG_SW_OBS_SEL_1_0_MSB 19
-#define MAC_PCU_DIAG_SW_OBS_SEL_1_0_LSB 18
-#define MAC_PCU_DIAG_SW_OBS_SEL_1_0_MASK 0x000c0000
-#define MAC_PCU_DIAG_SW_OBS_SEL_1_0_GET(x) (((x) & MAC_PCU_DIAG_SW_OBS_SEL_1_0_MASK) >> MAC_PCU_DIAG_SW_OBS_SEL_1_0_LSB)
-#define MAC_PCU_DIAG_SW_OBS_SEL_1_0_SET(x) (((x) << MAC_PCU_DIAG_SW_OBS_SEL_1_0_LSB) & MAC_PCU_DIAG_SW_OBS_SEL_1_0_MASK)
-#define MAC_PCU_DIAG_SW_ACCEPT_NON_V0_MSB 17
-#define MAC_PCU_DIAG_SW_ACCEPT_NON_V0_LSB 17
-#define MAC_PCU_DIAG_SW_ACCEPT_NON_V0_MASK 0x00020000
-#define MAC_PCU_DIAG_SW_ACCEPT_NON_V0_GET(x) (((x) & MAC_PCU_DIAG_SW_ACCEPT_NON_V0_MASK) >> MAC_PCU_DIAG_SW_ACCEPT_NON_V0_LSB)
-#define MAC_PCU_DIAG_SW_ACCEPT_NON_V0_SET(x) (((x) << MAC_PCU_DIAG_SW_ACCEPT_NON_V0_LSB) & MAC_PCU_DIAG_SW_ACCEPT_NON_V0_MASK)
-#define MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_MSB 8
-#define MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_LSB 8
-#define MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_MASK 0x00000100
-#define MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_GET(x) (((x) & MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_MASK) >> MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_LSB)
-#define MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_SET(x) (((x) << MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_LSB) & MAC_PCU_DIAG_SW_DUMP_CHAN_INFO_MASK)
-#define MAC_PCU_DIAG_SW_CORRUPT_FCS_MSB 7
-#define MAC_PCU_DIAG_SW_CORRUPT_FCS_LSB 7
-#define MAC_PCU_DIAG_SW_CORRUPT_FCS_MASK 0x00000080
-#define MAC_PCU_DIAG_SW_CORRUPT_FCS_GET(x) (((x) & MAC_PCU_DIAG_SW_CORRUPT_FCS_MASK) >> MAC_PCU_DIAG_SW_CORRUPT_FCS_LSB)
-#define MAC_PCU_DIAG_SW_CORRUPT_FCS_SET(x) (((x) << MAC_PCU_DIAG_SW_CORRUPT_FCS_LSB) & MAC_PCU_DIAG_SW_CORRUPT_FCS_MASK)
-#define MAC_PCU_DIAG_SW_LOOP_BACK_MSB 6
-#define MAC_PCU_DIAG_SW_LOOP_BACK_LSB 6
-#define MAC_PCU_DIAG_SW_LOOP_BACK_MASK 0x00000040
-#define MAC_PCU_DIAG_SW_LOOP_BACK_GET(x) (((x) & MAC_PCU_DIAG_SW_LOOP_BACK_MASK) >> MAC_PCU_DIAG_SW_LOOP_BACK_LSB)
-#define MAC_PCU_DIAG_SW_LOOP_BACK_SET(x) (((x) << MAC_PCU_DIAG_SW_LOOP_BACK_LSB) & MAC_PCU_DIAG_SW_LOOP_BACK_MASK)
-#define MAC_PCU_DIAG_SW_HALT_RX_MSB 5
-#define MAC_PCU_DIAG_SW_HALT_RX_LSB 5
-#define MAC_PCU_DIAG_SW_HALT_RX_MASK 0x00000020
-#define MAC_PCU_DIAG_SW_HALT_RX_GET(x) (((x) & MAC_PCU_DIAG_SW_HALT_RX_MASK) >> MAC_PCU_DIAG_SW_HALT_RX_LSB)
-#define MAC_PCU_DIAG_SW_HALT_RX_SET(x) (((x) << MAC_PCU_DIAG_SW_HALT_RX_LSB) & MAC_PCU_DIAG_SW_HALT_RX_MASK)
-#define MAC_PCU_DIAG_SW_NO_DECRYPT_MSB 4
-#define MAC_PCU_DIAG_SW_NO_DECRYPT_LSB 4
-#define MAC_PCU_DIAG_SW_NO_DECRYPT_MASK 0x00000010
-#define MAC_PCU_DIAG_SW_NO_DECRYPT_GET(x) (((x) & MAC_PCU_DIAG_SW_NO_DECRYPT_MASK) >> MAC_PCU_DIAG_SW_NO_DECRYPT_LSB)
-#define MAC_PCU_DIAG_SW_NO_DECRYPT_SET(x) (((x) << MAC_PCU_DIAG_SW_NO_DECRYPT_LSB) & MAC_PCU_DIAG_SW_NO_DECRYPT_MASK)
-#define MAC_PCU_DIAG_SW_NO_ENCRYPT_MSB 3
-#define MAC_PCU_DIAG_SW_NO_ENCRYPT_LSB 3
-#define MAC_PCU_DIAG_SW_NO_ENCRYPT_MASK 0x00000008
-#define MAC_PCU_DIAG_SW_NO_ENCRYPT_GET(x) (((x) & MAC_PCU_DIAG_SW_NO_ENCRYPT_MASK) >> MAC_PCU_DIAG_SW_NO_ENCRYPT_LSB)
-#define MAC_PCU_DIAG_SW_NO_ENCRYPT_SET(x) (((x) << MAC_PCU_DIAG_SW_NO_ENCRYPT_LSB) & MAC_PCU_DIAG_SW_NO_ENCRYPT_MASK)
-#define MAC_PCU_DIAG_SW_NO_CTS_MSB 2
-#define MAC_PCU_DIAG_SW_NO_CTS_LSB 2
-#define MAC_PCU_DIAG_SW_NO_CTS_MASK 0x00000004
-#define MAC_PCU_DIAG_SW_NO_CTS_GET(x) (((x) & MAC_PCU_DIAG_SW_NO_CTS_MASK) >> MAC_PCU_DIAG_SW_NO_CTS_LSB)
-#define MAC_PCU_DIAG_SW_NO_CTS_SET(x) (((x) << MAC_PCU_DIAG_SW_NO_CTS_LSB) & MAC_PCU_DIAG_SW_NO_CTS_MASK)
-#define MAC_PCU_DIAG_SW_NO_ACK_MSB 1
-#define MAC_PCU_DIAG_SW_NO_ACK_LSB 1
-#define MAC_PCU_DIAG_SW_NO_ACK_MASK 0x00000002
-#define MAC_PCU_DIAG_SW_NO_ACK_GET(x) (((x) & MAC_PCU_DIAG_SW_NO_ACK_MASK) >> MAC_PCU_DIAG_SW_NO_ACK_LSB)
-#define MAC_PCU_DIAG_SW_NO_ACK_SET(x) (((x) << MAC_PCU_DIAG_SW_NO_ACK_LSB) & MAC_PCU_DIAG_SW_NO_ACK_MASK)
-#define MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_MSB 0
-#define MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_LSB 0
-#define MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_MASK 0x00000001
-#define MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_GET(x) (((x) & MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_MASK) >> MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_LSB)
-#define MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_SET(x) (((x) << MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_LSB) & MAC_PCU_DIAG_SW_INVALID_KEY_NO_ACK_MASK)
-
-#define MAC_PCU_TST_ADDAC_ADDRESS 0x00008034
-#define MAC_PCU_TST_ADDAC_OFFSET 0x00000034
-#define MAC_PCU_TST_ADDAC_TEST_ARM_MSB 20
-#define MAC_PCU_TST_ADDAC_TEST_ARM_LSB 20
-#define MAC_PCU_TST_ADDAC_TEST_ARM_MASK 0x00100000
-#define MAC_PCU_TST_ADDAC_TEST_ARM_GET(x) (((x) & MAC_PCU_TST_ADDAC_TEST_ARM_MASK) >> MAC_PCU_TST_ADDAC_TEST_ARM_LSB)
-#define MAC_PCU_TST_ADDAC_TEST_ARM_SET(x) (((x) << MAC_PCU_TST_ADDAC_TEST_ARM_LSB) & MAC_PCU_TST_ADDAC_TEST_ARM_MASK)
-#define MAC_PCU_TST_ADDAC_TEST_CAPTURE_MSB 19
-#define MAC_PCU_TST_ADDAC_TEST_CAPTURE_LSB 19
-#define MAC_PCU_TST_ADDAC_TEST_CAPTURE_MASK 0x00080000
-#define MAC_PCU_TST_ADDAC_TEST_CAPTURE_GET(x) (((x) & MAC_PCU_TST_ADDAC_TEST_CAPTURE_MASK) >> MAC_PCU_TST_ADDAC_TEST_CAPTURE_LSB)
-#define MAC_PCU_TST_ADDAC_TEST_CAPTURE_SET(x) (((x) << MAC_PCU_TST_ADDAC_TEST_CAPTURE_LSB) & MAC_PCU_TST_ADDAC_TEST_CAPTURE_MASK)
-#define MAC_PCU_TST_ADDAC_CONT_TEST_MSB 18
-#define MAC_PCU_TST_ADDAC_CONT_TEST_LSB 18
-#define MAC_PCU_TST_ADDAC_CONT_TEST_MASK 0x00040000
-#define MAC_PCU_TST_ADDAC_CONT_TEST_GET(x) (((x) & MAC_PCU_TST_ADDAC_CONT_TEST_MASK) >> MAC_PCU_TST_ADDAC_CONT_TEST_LSB)
-#define MAC_PCU_TST_ADDAC_CONT_TEST_SET(x) (((x) << MAC_PCU_TST_ADDAC_CONT_TEST_LSB) & MAC_PCU_TST_ADDAC_CONT_TEST_MASK)
-#define MAC_PCU_TST_ADDAC_TRIG_POLARITY_MSB 17
-#define MAC_PCU_TST_ADDAC_TRIG_POLARITY_LSB 17
-#define MAC_PCU_TST_ADDAC_TRIG_POLARITY_MASK 0x00020000
-#define MAC_PCU_TST_ADDAC_TRIG_POLARITY_GET(x) (((x) & MAC_PCU_TST_ADDAC_TRIG_POLARITY_MASK) >> MAC_PCU_TST_ADDAC_TRIG_POLARITY_LSB)
-#define MAC_PCU_TST_ADDAC_TRIG_POLARITY_SET(x) (((x) << MAC_PCU_TST_ADDAC_TRIG_POLARITY_LSB) & MAC_PCU_TST_ADDAC_TRIG_POLARITY_MASK)
-#define MAC_PCU_TST_ADDAC_TRIG_SEL_MSB 16
-#define MAC_PCU_TST_ADDAC_TRIG_SEL_LSB 16
-#define MAC_PCU_TST_ADDAC_TRIG_SEL_MASK 0x00010000
-#define MAC_PCU_TST_ADDAC_TRIG_SEL_GET(x) (((x) & MAC_PCU_TST_ADDAC_TRIG_SEL_MASK) >> MAC_PCU_TST_ADDAC_TRIG_SEL_LSB)
-#define MAC_PCU_TST_ADDAC_TRIG_SEL_SET(x) (((x) << MAC_PCU_TST_ADDAC_TRIG_SEL_LSB) & MAC_PCU_TST_ADDAC_TRIG_SEL_MASK)
-#define MAC_PCU_TST_ADDAC_UPPER_8B_MSB 14
-#define MAC_PCU_TST_ADDAC_UPPER_8B_LSB 14
-#define MAC_PCU_TST_ADDAC_UPPER_8B_MASK 0x00004000
-#define MAC_PCU_TST_ADDAC_UPPER_8B_GET(x) (((x) & MAC_PCU_TST_ADDAC_UPPER_8B_MASK) >> MAC_PCU_TST_ADDAC_UPPER_8B_LSB)
-#define MAC_PCU_TST_ADDAC_UPPER_8B_SET(x) (((x) << MAC_PCU_TST_ADDAC_UPPER_8B_LSB) & MAC_PCU_TST_ADDAC_UPPER_8B_MASK)
-#define MAC_PCU_TST_ADDAC_LOOP_LEN_MSB 13
-#define MAC_PCU_TST_ADDAC_LOOP_LEN_LSB 3
-#define MAC_PCU_TST_ADDAC_LOOP_LEN_MASK 0x00003ff8
-#define MAC_PCU_TST_ADDAC_LOOP_LEN_GET(x) (((x) & MAC_PCU_TST_ADDAC_LOOP_LEN_MASK) >> MAC_PCU_TST_ADDAC_LOOP_LEN_LSB)
-#define MAC_PCU_TST_ADDAC_LOOP_LEN_SET(x) (((x) << MAC_PCU_TST_ADDAC_LOOP_LEN_LSB) & MAC_PCU_TST_ADDAC_LOOP_LEN_MASK)
-#define MAC_PCU_TST_ADDAC_LOOP_MSB 2
-#define MAC_PCU_TST_ADDAC_LOOP_LSB 2
-#define MAC_PCU_TST_ADDAC_LOOP_MASK 0x00000004
-#define MAC_PCU_TST_ADDAC_LOOP_GET(x) (((x) & MAC_PCU_TST_ADDAC_LOOP_MASK) >> MAC_PCU_TST_ADDAC_LOOP_LSB)
-#define MAC_PCU_TST_ADDAC_LOOP_SET(x) (((x) << MAC_PCU_TST_ADDAC_LOOP_LSB) & MAC_PCU_TST_ADDAC_LOOP_MASK)
-#define MAC_PCU_TST_ADDAC_TESTMODE_MSB 1
-#define MAC_PCU_TST_ADDAC_TESTMODE_LSB 1
-#define MAC_PCU_TST_ADDAC_TESTMODE_MASK 0x00000002
-#define MAC_PCU_TST_ADDAC_TESTMODE_GET(x) (((x) & MAC_PCU_TST_ADDAC_TESTMODE_MASK) >> MAC_PCU_TST_ADDAC_TESTMODE_LSB)
-#define MAC_PCU_TST_ADDAC_TESTMODE_SET(x) (((x) << MAC_PCU_TST_ADDAC_TESTMODE_LSB) & MAC_PCU_TST_ADDAC_TESTMODE_MASK)
-#define MAC_PCU_TST_ADDAC_CONT_TX_MSB 0
-#define MAC_PCU_TST_ADDAC_CONT_TX_LSB 0
-#define MAC_PCU_TST_ADDAC_CONT_TX_MASK 0x00000001
-#define MAC_PCU_TST_ADDAC_CONT_TX_GET(x) (((x) & MAC_PCU_TST_ADDAC_CONT_TX_MASK) >> MAC_PCU_TST_ADDAC_CONT_TX_LSB)
-#define MAC_PCU_TST_ADDAC_CONT_TX_SET(x) (((x) << MAC_PCU_TST_ADDAC_CONT_TX_LSB) & MAC_PCU_TST_ADDAC_CONT_TX_MASK)
-
-#define MAC_PCU_DEF_ANTENNA_ADDRESS 0x00008038
-#define MAC_PCU_DEF_ANTENNA_OFFSET 0x00000038
-#define MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_MSB 28
-#define MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_LSB 28
-#define MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_MASK 0x10000000
-#define MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_GET(x) (((x) & MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_MASK) >> MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_LSB)
-#define MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_SET(x) (((x) << MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_LSB) & MAC_PCU_DEF_ANTENNA_RX_LNA_CONFIG_SEL_MASK)
-#define MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_MSB 24
-#define MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_LSB 24
-#define MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_MASK 0x01000000
-#define MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_GET(x) (((x) & MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_MASK) >> MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_LSB)
-#define MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_SET(x) (((x) << MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_LSB) & MAC_PCU_DEF_ANTENNA_TX_DEF_ANT_SEL_MASK)
-#define MAC_PCU_DEF_ANTENNA_VALUE_MSB 23
-#define MAC_PCU_DEF_ANTENNA_VALUE_LSB 0
-#define MAC_PCU_DEF_ANTENNA_VALUE_MASK 0x00ffffff
-#define MAC_PCU_DEF_ANTENNA_VALUE_GET(x) (((x) & MAC_PCU_DEF_ANTENNA_VALUE_MASK) >> MAC_PCU_DEF_ANTENNA_VALUE_LSB)
-#define MAC_PCU_DEF_ANTENNA_VALUE_SET(x) (((x) << MAC_PCU_DEF_ANTENNA_VALUE_LSB) & MAC_PCU_DEF_ANTENNA_VALUE_MASK)
-
-#define MAC_PCU_AES_MUTE_MASK_0_ADDRESS 0x0000803c
-#define MAC_PCU_AES_MUTE_MASK_0_OFFSET 0x0000003c
-#define MAC_PCU_AES_MUTE_MASK_0_QOS_MSB 31
-#define MAC_PCU_AES_MUTE_MASK_0_QOS_LSB 16
-#define MAC_PCU_AES_MUTE_MASK_0_QOS_MASK 0xffff0000
-#define MAC_PCU_AES_MUTE_MASK_0_QOS_GET(x) (((x) & MAC_PCU_AES_MUTE_MASK_0_QOS_MASK) >> MAC_PCU_AES_MUTE_MASK_0_QOS_LSB)
-#define MAC_PCU_AES_MUTE_MASK_0_QOS_SET(x) (((x) << MAC_PCU_AES_MUTE_MASK_0_QOS_LSB) & MAC_PCU_AES_MUTE_MASK_0_QOS_MASK)
-#define MAC_PCU_AES_MUTE_MASK_0_FC_MSB 15
-#define MAC_PCU_AES_MUTE_MASK_0_FC_LSB 0
-#define MAC_PCU_AES_MUTE_MASK_0_FC_MASK 0x0000ffff
-#define MAC_PCU_AES_MUTE_MASK_0_FC_GET(x) (((x) & MAC_PCU_AES_MUTE_MASK_0_FC_MASK) >> MAC_PCU_AES_MUTE_MASK_0_FC_LSB)
-#define MAC_PCU_AES_MUTE_MASK_0_FC_SET(x) (((x) << MAC_PCU_AES_MUTE_MASK_0_FC_LSB) & MAC_PCU_AES_MUTE_MASK_0_FC_MASK)
-
-#define MAC_PCU_AES_MUTE_MASK_1_ADDRESS 0x00008040
-#define MAC_PCU_AES_MUTE_MASK_1_OFFSET 0x00000040
-#define MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_MSB 31
-#define MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_LSB 16
-#define MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_MASK 0xffff0000
-#define MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_GET(x) (((x) & MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_MASK) >> MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_LSB)
-#define MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_SET(x) (((x) << MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_LSB) & MAC_PCU_AES_MUTE_MASK_1_FC_MGMT_MASK)
-#define MAC_PCU_AES_MUTE_MASK_1_SEQ_MSB 15
-#define MAC_PCU_AES_MUTE_MASK_1_SEQ_LSB 0
-#define MAC_PCU_AES_MUTE_MASK_1_SEQ_MASK 0x0000ffff
-#define MAC_PCU_AES_MUTE_MASK_1_SEQ_GET(x) (((x) & MAC_PCU_AES_MUTE_MASK_1_SEQ_MASK) >> MAC_PCU_AES_MUTE_MASK_1_SEQ_LSB)
-#define MAC_PCU_AES_MUTE_MASK_1_SEQ_SET(x) (((x) << MAC_PCU_AES_MUTE_MASK_1_SEQ_LSB) & MAC_PCU_AES_MUTE_MASK_1_SEQ_MASK)
-
-#define MAC_PCU_GATED_CLKS_ADDRESS 0x00008044
-#define MAC_PCU_GATED_CLKS_OFFSET 0x00000044
-#define MAC_PCU_GATED_CLKS_GATED_REG_MSB 3
-#define MAC_PCU_GATED_CLKS_GATED_REG_LSB 3
-#define MAC_PCU_GATED_CLKS_GATED_REG_MASK 0x00000008
-#define MAC_PCU_GATED_CLKS_GATED_REG_GET(x) (((x) & MAC_PCU_GATED_CLKS_GATED_REG_MASK) >> MAC_PCU_GATED_CLKS_GATED_REG_LSB)
-#define MAC_PCU_GATED_CLKS_GATED_REG_SET(x) (((x) << MAC_PCU_GATED_CLKS_GATED_REG_LSB) & MAC_PCU_GATED_CLKS_GATED_REG_MASK)
-#define MAC_PCU_GATED_CLKS_GATED_RX_MSB 2
-#define MAC_PCU_GATED_CLKS_GATED_RX_LSB 2
-#define MAC_PCU_GATED_CLKS_GATED_RX_MASK 0x00000004
-#define MAC_PCU_GATED_CLKS_GATED_RX_GET(x) (((x) & MAC_PCU_GATED_CLKS_GATED_RX_MASK) >> MAC_PCU_GATED_CLKS_GATED_RX_LSB)
-#define MAC_PCU_GATED_CLKS_GATED_RX_SET(x) (((x) << MAC_PCU_GATED_CLKS_GATED_RX_LSB) & MAC_PCU_GATED_CLKS_GATED_RX_MASK)
-#define MAC_PCU_GATED_CLKS_GATED_TX_MSB 1
-#define MAC_PCU_GATED_CLKS_GATED_TX_LSB 1
-#define MAC_PCU_GATED_CLKS_GATED_TX_MASK 0x00000002
-#define MAC_PCU_GATED_CLKS_GATED_TX_GET(x) (((x) & MAC_PCU_GATED_CLKS_GATED_TX_MASK) >> MAC_PCU_GATED_CLKS_GATED_TX_LSB)
-#define MAC_PCU_GATED_CLKS_GATED_TX_SET(x) (((x) << MAC_PCU_GATED_CLKS_GATED_TX_LSB) & MAC_PCU_GATED_CLKS_GATED_TX_MASK)
-
-#define MAC_PCU_OBS_BUS_2_ADDRESS 0x00008048
-#define MAC_PCU_OBS_BUS_2_OFFSET 0x00000048
-#define MAC_PCU_OBS_BUS_2_VALUE_MSB 17
-#define MAC_PCU_OBS_BUS_2_VALUE_LSB 0
-#define MAC_PCU_OBS_BUS_2_VALUE_MASK 0x0003ffff
-#define MAC_PCU_OBS_BUS_2_VALUE_GET(x) (((x) & MAC_PCU_OBS_BUS_2_VALUE_MASK) >> MAC_PCU_OBS_BUS_2_VALUE_LSB)
-#define MAC_PCU_OBS_BUS_2_VALUE_SET(x) (((x) << MAC_PCU_OBS_BUS_2_VALUE_LSB) & MAC_PCU_OBS_BUS_2_VALUE_MASK)
-
-#define MAC_PCU_OBS_BUS_1_ADDRESS 0x0000804c
-#define MAC_PCU_OBS_BUS_1_OFFSET 0x0000004c
-#define MAC_PCU_OBS_BUS_1_TX_STATE_MSB 30
-#define MAC_PCU_OBS_BUS_1_TX_STATE_LSB 25
-#define MAC_PCU_OBS_BUS_1_TX_STATE_MASK 0x7e000000
-#define MAC_PCU_OBS_BUS_1_TX_STATE_GET(x) (((x) & MAC_PCU_OBS_BUS_1_TX_STATE_MASK) >> MAC_PCU_OBS_BUS_1_TX_STATE_LSB)
-#define MAC_PCU_OBS_BUS_1_TX_STATE_SET(x) (((x) << MAC_PCU_OBS_BUS_1_TX_STATE_LSB) & MAC_PCU_OBS_BUS_1_TX_STATE_MASK)
-#define MAC_PCU_OBS_BUS_1_RX_STATE_MSB 24
-#define MAC_PCU_OBS_BUS_1_RX_STATE_LSB 20
-#define MAC_PCU_OBS_BUS_1_RX_STATE_MASK 0x01f00000
-#define MAC_PCU_OBS_BUS_1_RX_STATE_GET(x) (((x) & MAC_PCU_OBS_BUS_1_RX_STATE_MASK) >> MAC_PCU_OBS_BUS_1_RX_STATE_LSB)
-#define MAC_PCU_OBS_BUS_1_RX_STATE_SET(x) (((x) << MAC_PCU_OBS_BUS_1_RX_STATE_LSB) & MAC_PCU_OBS_BUS_1_RX_STATE_MASK)
-#define MAC_PCU_OBS_BUS_1_WEP_STATE_MSB 17
-#define MAC_PCU_OBS_BUS_1_WEP_STATE_LSB 12
-#define MAC_PCU_OBS_BUS_1_WEP_STATE_MASK 0x0003f000
-#define MAC_PCU_OBS_BUS_1_WEP_STATE_GET(x) (((x) & MAC_PCU_OBS_BUS_1_WEP_STATE_MASK) >> MAC_PCU_OBS_BUS_1_WEP_STATE_LSB)
-#define MAC_PCU_OBS_BUS_1_WEP_STATE_SET(x) (((x) << MAC_PCU_OBS_BUS_1_WEP_STATE_LSB) & MAC_PCU_OBS_BUS_1_WEP_STATE_MASK)
-#define MAC_PCU_OBS_BUS_1_RX_CLEAR_MSB 11
-#define MAC_PCU_OBS_BUS_1_RX_CLEAR_LSB 11
-#define MAC_PCU_OBS_BUS_1_RX_CLEAR_MASK 0x00000800
-#define MAC_PCU_OBS_BUS_1_RX_CLEAR_GET(x) (((x) & MAC_PCU_OBS_BUS_1_RX_CLEAR_MASK) >> MAC_PCU_OBS_BUS_1_RX_CLEAR_LSB)
-#define MAC_PCU_OBS_BUS_1_RX_CLEAR_SET(x) (((x) << MAC_PCU_OBS_BUS_1_RX_CLEAR_LSB) & MAC_PCU_OBS_BUS_1_RX_CLEAR_MASK)
-#define MAC_PCU_OBS_BUS_1_RX_FRAME_MSB 10
-#define MAC_PCU_OBS_BUS_1_RX_FRAME_LSB 10
-#define MAC_PCU_OBS_BUS_1_RX_FRAME_MASK 0x00000400
-#define MAC_PCU_OBS_BUS_1_RX_FRAME_GET(x) (((x) & MAC_PCU_OBS_BUS_1_RX_FRAME_MASK) >> MAC_PCU_OBS_BUS_1_RX_FRAME_LSB)
-#define MAC_PCU_OBS_BUS_1_RX_FRAME_SET(x) (((x) << MAC_PCU_OBS_BUS_1_RX_FRAME_LSB) & MAC_PCU_OBS_BUS_1_RX_FRAME_MASK)
-#define MAC_PCU_OBS_BUS_1_TX_FRAME_MSB 9
-#define MAC_PCU_OBS_BUS_1_TX_FRAME_LSB 9
-#define MAC_PCU_OBS_BUS_1_TX_FRAME_MASK 0x00000200
-#define MAC_PCU_OBS_BUS_1_TX_FRAME_GET(x) (((x) & MAC_PCU_OBS_BUS_1_TX_FRAME_MASK) >> MAC_PCU_OBS_BUS_1_TX_FRAME_LSB)
-#define MAC_PCU_OBS_BUS_1_TX_FRAME_SET(x) (((x) << MAC_PCU_OBS_BUS_1_TX_FRAME_LSB) & MAC_PCU_OBS_BUS_1_TX_FRAME_MASK)
-#define MAC_PCU_OBS_BUS_1_TX_HOLD_MSB 8
-#define MAC_PCU_OBS_BUS_1_TX_HOLD_LSB 8
-#define MAC_PCU_OBS_BUS_1_TX_HOLD_MASK 0x00000100
-#define MAC_PCU_OBS_BUS_1_TX_HOLD_GET(x) (((x) & MAC_PCU_OBS_BUS_1_TX_HOLD_MASK) >> MAC_PCU_OBS_BUS_1_TX_HOLD_LSB)
-#define MAC_PCU_OBS_BUS_1_TX_HOLD_SET(x) (((x) << MAC_PCU_OBS_BUS_1_TX_HOLD_LSB) & MAC_PCU_OBS_BUS_1_TX_HOLD_MASK)
-#define MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_MSB 7
-#define MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_LSB 7
-#define MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_MASK 0x00000080
-#define MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_GET(x) (((x) & MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_MASK) >> MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_LSB)
-#define MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_SET(x) (((x) << MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_LSB) & MAC_PCU_OBS_BUS_1_PCU_CHANNEL_IDLE_MASK)
-#define MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_MSB 6
-#define MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_LSB 6
-#define MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_MASK 0x00000040
-#define MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_GET(x) (((x) & MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_MASK) >> MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_LSB)
-#define MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_SET(x) (((x) << MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_LSB) & MAC_PCU_OBS_BUS_1_TM_QUIET_TIME_MASK)
-#define MAC_PCU_OBS_BUS_1_TX_HCF_MSB 5
-#define MAC_PCU_OBS_BUS_1_TX_HCF_LSB 5
-#define MAC_PCU_OBS_BUS_1_TX_HCF_MASK 0x00000020
-#define MAC_PCU_OBS_BUS_1_TX_HCF_GET(x) (((x) & MAC_PCU_OBS_BUS_1_TX_HCF_MASK) >> MAC_PCU_OBS_BUS_1_TX_HCF_LSB)
-#define MAC_PCU_OBS_BUS_1_TX_HCF_SET(x) (((x) << MAC_PCU_OBS_BUS_1_TX_HCF_LSB) & MAC_PCU_OBS_BUS_1_TX_HCF_MASK)
-#define MAC_PCU_OBS_BUS_1_FILTER_PASS_MSB 4
-#define MAC_PCU_OBS_BUS_1_FILTER_PASS_LSB 4
-#define MAC_PCU_OBS_BUS_1_FILTER_PASS_MASK 0x00000010
-#define MAC_PCU_OBS_BUS_1_FILTER_PASS_GET(x) (((x) & MAC_PCU_OBS_BUS_1_FILTER_PASS_MASK) >> MAC_PCU_OBS_BUS_1_FILTER_PASS_LSB)
-#define MAC_PCU_OBS_BUS_1_FILTER_PASS_SET(x) (((x) << MAC_PCU_OBS_BUS_1_FILTER_PASS_LSB) & MAC_PCU_OBS_BUS_1_FILTER_PASS_MASK)
-#define MAC_PCU_OBS_BUS_1_RX_MY_BEACON_MSB 3
-#define MAC_PCU_OBS_BUS_1_RX_MY_BEACON_LSB 3
-#define MAC_PCU_OBS_BUS_1_RX_MY_BEACON_MASK 0x00000008
-#define MAC_PCU_OBS_BUS_1_RX_MY_BEACON_GET(x) (((x) & MAC_PCU_OBS_BUS_1_RX_MY_BEACON_MASK) >> MAC_PCU_OBS_BUS_1_RX_MY_BEACON_LSB)
-#define MAC_PCU_OBS_BUS_1_RX_MY_BEACON_SET(x) (((x) << MAC_PCU_OBS_BUS_1_RX_MY_BEACON_LSB) & MAC_PCU_OBS_BUS_1_RX_MY_BEACON_MASK)
-#define MAC_PCU_OBS_BUS_1_RX_WEP_MSB 2
-#define MAC_PCU_OBS_BUS_1_RX_WEP_LSB 2
-#define MAC_PCU_OBS_BUS_1_RX_WEP_MASK 0x00000004
-#define MAC_PCU_OBS_BUS_1_RX_WEP_GET(x) (((x) & MAC_PCU_OBS_BUS_1_RX_WEP_MASK) >> MAC_PCU_OBS_BUS_1_RX_WEP_LSB)
-#define MAC_PCU_OBS_BUS_1_RX_WEP_SET(x) (((x) << MAC_PCU_OBS_BUS_1_RX_WEP_LSB) & MAC_PCU_OBS_BUS_1_RX_WEP_MASK)
-#define MAC_PCU_OBS_BUS_1_PCU_RX_END_MSB 1
-#define MAC_PCU_OBS_BUS_1_PCU_RX_END_LSB 1
-#define MAC_PCU_OBS_BUS_1_PCU_RX_END_MASK 0x00000002
-#define MAC_PCU_OBS_BUS_1_PCU_RX_END_GET(x) (((x) & MAC_PCU_OBS_BUS_1_PCU_RX_END_MASK) >> MAC_PCU_OBS_BUS_1_PCU_RX_END_LSB)
-#define MAC_PCU_OBS_BUS_1_PCU_RX_END_SET(x) (((x) << MAC_PCU_OBS_BUS_1_PCU_RX_END_LSB) & MAC_PCU_OBS_BUS_1_PCU_RX_END_MASK)
-#define MAC_PCU_OBS_BUS_1_PCU_DIRECTED_MSB 0
-#define MAC_PCU_OBS_BUS_1_PCU_DIRECTED_LSB 0
-#define MAC_PCU_OBS_BUS_1_PCU_DIRECTED_MASK 0x00000001
-#define MAC_PCU_OBS_BUS_1_PCU_DIRECTED_GET(x) (((x) & MAC_PCU_OBS_BUS_1_PCU_DIRECTED_MASK) >> MAC_PCU_OBS_BUS_1_PCU_DIRECTED_LSB)
-#define MAC_PCU_OBS_BUS_1_PCU_DIRECTED_SET(x) (((x) << MAC_PCU_OBS_BUS_1_PCU_DIRECTED_LSB) & MAC_PCU_OBS_BUS_1_PCU_DIRECTED_MASK)
-
-#define MAC_PCU_DYM_MIMO_PWR_SAVE_ADDRESS 0x00008050
-#define MAC_PCU_DYM_MIMO_PWR_SAVE_OFFSET 0x00000050
-#define MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_MSB 10
-#define MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_LSB 8
-#define MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_MASK 0x00000700
-#define MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_GET(x) (((x) & MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_MASK) >> MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_LSB)
-#define MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_SET(x) (((x) << MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_LSB) & MAC_PCU_DYM_MIMO_PWR_SAVE_HI_PWR_CHAIN_MASK_MASK)
-#define MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_MSB 6
-#define MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_LSB 4
-#define MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_MASK 0x00000070
-#define MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_GET(x) (((x) & MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_MASK) >> MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_LSB)
-#define MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_SET(x) (((x) << MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_LSB) & MAC_PCU_DYM_MIMO_PWR_SAVE_LOW_PWR_CHAIN_MASK_MASK)
-#define MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_MSB 2
-#define MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_LSB 2
-#define MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_MASK 0x00000004
-#define MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_GET(x) (((x) & MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_MASK) >> MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_LSB)
-#define MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_SET(x) (((x) << MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_LSB) & MAC_PCU_DYM_MIMO_PWR_SAVE_SW_CHAIN_MASK_SEL_MASK)
-#define MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_MSB 1
-#define MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_LSB 1
-#define MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_MASK 0x00000002
-#define MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_GET(x) (((x) & MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_MASK) >> MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_LSB)
-#define MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_SET(x) (((x) << MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_LSB) & MAC_PCU_DYM_MIMO_PWR_SAVE_HW_CTRL_EN_MASK)
-#define MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_MSB 0
-#define MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_LSB 0
-#define MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_MASK 0x00000001
-#define MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_GET(x) (((x) & MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_MASK) >> MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_LSB)
-#define MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_SET(x) (((x) << MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_LSB) & MAC_PCU_DYM_MIMO_PWR_SAVE_USE_MAC_CTRL_MASK)
-
-#define MAC_PCU_LAST_BEACON_TSF_ADDRESS 0x00008054
-#define MAC_PCU_LAST_BEACON_TSF_OFFSET 0x00000054
-#define MAC_PCU_LAST_BEACON_TSF_VALUE_MSB 31
-#define MAC_PCU_LAST_BEACON_TSF_VALUE_LSB 0
-#define MAC_PCU_LAST_BEACON_TSF_VALUE_MASK 0xffffffff
-#define MAC_PCU_LAST_BEACON_TSF_VALUE_GET(x) (((x) & MAC_PCU_LAST_BEACON_TSF_VALUE_MASK) >> MAC_PCU_LAST_BEACON_TSF_VALUE_LSB)
-#define MAC_PCU_LAST_BEACON_TSF_VALUE_SET(x) (((x) << MAC_PCU_LAST_BEACON_TSF_VALUE_LSB) & MAC_PCU_LAST_BEACON_TSF_VALUE_MASK)
-
-#define MAC_PCU_NAV_ADDRESS 0x00008058
-#define MAC_PCU_NAV_OFFSET 0x00000058
-#define MAC_PCU_NAV_VALUE_MSB 25
-#define MAC_PCU_NAV_VALUE_LSB 0
-#define MAC_PCU_NAV_VALUE_MASK 0x03ffffff
-#define MAC_PCU_NAV_VALUE_GET(x) (((x) & MAC_PCU_NAV_VALUE_MASK) >> MAC_PCU_NAV_VALUE_LSB)
-#define MAC_PCU_NAV_VALUE_SET(x) (((x) << MAC_PCU_NAV_VALUE_LSB) & MAC_PCU_NAV_VALUE_MASK)
-
-#define MAC_PCU_RTS_SUCCESS_CNT_ADDRESS 0x0000805c
-#define MAC_PCU_RTS_SUCCESS_CNT_OFFSET 0x0000005c
-#define MAC_PCU_RTS_SUCCESS_CNT_VALUE_MSB 15
-#define MAC_PCU_RTS_SUCCESS_CNT_VALUE_LSB 0
-#define MAC_PCU_RTS_SUCCESS_CNT_VALUE_MASK 0x0000ffff
-#define MAC_PCU_RTS_SUCCESS_CNT_VALUE_GET(x) (((x) & MAC_PCU_RTS_SUCCESS_CNT_VALUE_MASK) >> MAC_PCU_RTS_SUCCESS_CNT_VALUE_LSB)
-#define MAC_PCU_RTS_SUCCESS_CNT_VALUE_SET(x) (((x) << MAC_PCU_RTS_SUCCESS_CNT_VALUE_LSB) & MAC_PCU_RTS_SUCCESS_CNT_VALUE_MASK)
-
-#define MAC_PCU_RTS_FAIL_CNT_ADDRESS 0x00008060
-#define MAC_PCU_RTS_FAIL_CNT_OFFSET 0x00000060
-#define MAC_PCU_RTS_FAIL_CNT_VALUE_MSB 15
-#define MAC_PCU_RTS_FAIL_CNT_VALUE_LSB 0
-#define MAC_PCU_RTS_FAIL_CNT_VALUE_MASK 0x0000ffff
-#define MAC_PCU_RTS_FAIL_CNT_VALUE_GET(x) (((x) & MAC_PCU_RTS_FAIL_CNT_VALUE_MASK) >> MAC_PCU_RTS_FAIL_CNT_VALUE_LSB)
-#define MAC_PCU_RTS_FAIL_CNT_VALUE_SET(x) (((x) << MAC_PCU_RTS_FAIL_CNT_VALUE_LSB) & MAC_PCU_RTS_FAIL_CNT_VALUE_MASK)
-
-#define MAC_PCU_ACK_FAIL_CNT_ADDRESS 0x00008064
-#define MAC_PCU_ACK_FAIL_CNT_OFFSET 0x00000064
-#define MAC_PCU_ACK_FAIL_CNT_VALUE_MSB 15
-#define MAC_PCU_ACK_FAIL_CNT_VALUE_LSB 0
-#define MAC_PCU_ACK_FAIL_CNT_VALUE_MASK 0x0000ffff
-#define MAC_PCU_ACK_FAIL_CNT_VALUE_GET(x) (((x) & MAC_PCU_ACK_FAIL_CNT_VALUE_MASK) >> MAC_PCU_ACK_FAIL_CNT_VALUE_LSB)
-#define MAC_PCU_ACK_FAIL_CNT_VALUE_SET(x) (((x) << MAC_PCU_ACK_FAIL_CNT_VALUE_LSB) & MAC_PCU_ACK_FAIL_CNT_VALUE_MASK)
-
-#define MAC_PCU_FCS_FAIL_CNT_ADDRESS 0x00008068
-#define MAC_PCU_FCS_FAIL_CNT_OFFSET 0x00000068
-#define MAC_PCU_FCS_FAIL_CNT_VALUE_MSB 15
-#define MAC_PCU_FCS_FAIL_CNT_VALUE_LSB 0
-#define MAC_PCU_FCS_FAIL_CNT_VALUE_MASK 0x0000ffff
-#define MAC_PCU_FCS_FAIL_CNT_VALUE_GET(x) (((x) & MAC_PCU_FCS_FAIL_CNT_VALUE_MASK) >> MAC_PCU_FCS_FAIL_CNT_VALUE_LSB)
-#define MAC_PCU_FCS_FAIL_CNT_VALUE_SET(x) (((x) << MAC_PCU_FCS_FAIL_CNT_VALUE_LSB) & MAC_PCU_FCS_FAIL_CNT_VALUE_MASK)
-
-#define MAC_PCU_BEACON_CNT_ADDRESS 0x0000806c
-#define MAC_PCU_BEACON_CNT_OFFSET 0x0000006c
-#define MAC_PCU_BEACON_CNT_VALUE_MSB 15
-#define MAC_PCU_BEACON_CNT_VALUE_LSB 0
-#define MAC_PCU_BEACON_CNT_VALUE_MASK 0x0000ffff
-#define MAC_PCU_BEACON_CNT_VALUE_GET(x) (((x) & MAC_PCU_BEACON_CNT_VALUE_MASK) >> MAC_PCU_BEACON_CNT_VALUE_LSB)
-#define MAC_PCU_BEACON_CNT_VALUE_SET(x) (((x) << MAC_PCU_BEACON_CNT_VALUE_LSB) & MAC_PCU_BEACON_CNT_VALUE_MASK)
-
-#define MAC_PCU_XRMODE_ADDRESS 0x00008070
-#define MAC_PCU_XRMODE_OFFSET 0x00000070
-#define MAC_PCU_XRMODE_FRAME_HOLD_MSB 31
-#define MAC_PCU_XRMODE_FRAME_HOLD_LSB 20
-#define MAC_PCU_XRMODE_FRAME_HOLD_MASK 0xfff00000
-#define MAC_PCU_XRMODE_FRAME_HOLD_GET(x) (((x) & MAC_PCU_XRMODE_FRAME_HOLD_MASK) >> MAC_PCU_XRMODE_FRAME_HOLD_LSB)
-#define MAC_PCU_XRMODE_FRAME_HOLD_SET(x) (((x) << MAC_PCU_XRMODE_FRAME_HOLD_LSB) & MAC_PCU_XRMODE_FRAME_HOLD_MASK)
-#define MAC_PCU_XRMODE_WAIT_FOR_POLL_MSB 7
-#define MAC_PCU_XRMODE_WAIT_FOR_POLL_LSB 7
-#define MAC_PCU_XRMODE_WAIT_FOR_POLL_MASK 0x00000080
-#define MAC_PCU_XRMODE_WAIT_FOR_POLL_GET(x) (((x) & MAC_PCU_XRMODE_WAIT_FOR_POLL_MASK) >> MAC_PCU_XRMODE_WAIT_FOR_POLL_LSB)
-#define MAC_PCU_XRMODE_WAIT_FOR_POLL_SET(x) (((x) << MAC_PCU_XRMODE_WAIT_FOR_POLL_LSB) & MAC_PCU_XRMODE_WAIT_FOR_POLL_MASK)
-#define MAC_PCU_XRMODE_POLL_TYPE_MSB 5
-#define MAC_PCU_XRMODE_POLL_TYPE_LSB 0
-#define MAC_PCU_XRMODE_POLL_TYPE_MASK 0x0000003f
-#define MAC_PCU_XRMODE_POLL_TYPE_GET(x) (((x) & MAC_PCU_XRMODE_POLL_TYPE_MASK) >> MAC_PCU_XRMODE_POLL_TYPE_LSB)
-#define MAC_PCU_XRMODE_POLL_TYPE_SET(x) (((x) << MAC_PCU_XRMODE_POLL_TYPE_LSB) & MAC_PCU_XRMODE_POLL_TYPE_MASK)
-
-#define MAC_PCU_XRDEL_ADDRESS 0x00008074
-#define MAC_PCU_XRDEL_OFFSET 0x00000074
-#define MAC_PCU_XRDEL_CHIRP_DATA_DELAY_MSB 31
-#define MAC_PCU_XRDEL_CHIRP_DATA_DELAY_LSB 16
-#define MAC_PCU_XRDEL_CHIRP_DATA_DELAY_MASK 0xffff0000
-#define MAC_PCU_XRDEL_CHIRP_DATA_DELAY_GET(x) (((x) & MAC_PCU_XRDEL_CHIRP_DATA_DELAY_MASK) >> MAC_PCU_XRDEL_CHIRP_DATA_DELAY_LSB)
-#define MAC_PCU_XRDEL_CHIRP_DATA_DELAY_SET(x) (((x) << MAC_PCU_XRDEL_CHIRP_DATA_DELAY_LSB) & MAC_PCU_XRDEL_CHIRP_DATA_DELAY_MASK)
-#define MAC_PCU_XRDEL_SLOT_DELAY_MSB 15
-#define MAC_PCU_XRDEL_SLOT_DELAY_LSB 0
-#define MAC_PCU_XRDEL_SLOT_DELAY_MASK 0x0000ffff
-#define MAC_PCU_XRDEL_SLOT_DELAY_GET(x) (((x) & MAC_PCU_XRDEL_SLOT_DELAY_MASK) >> MAC_PCU_XRDEL_SLOT_DELAY_LSB)
-#define MAC_PCU_XRDEL_SLOT_DELAY_SET(x) (((x) << MAC_PCU_XRDEL_SLOT_DELAY_LSB) & MAC_PCU_XRDEL_SLOT_DELAY_MASK)
-
-#define MAC_PCU_XRTO_ADDRESS 0x00008078
-#define MAC_PCU_XRTO_OFFSET 0x00000078
-#define MAC_PCU_XRTO_POLL_TIMEOUT_MSB 31
-#define MAC_PCU_XRTO_POLL_TIMEOUT_LSB 16
-#define MAC_PCU_XRTO_POLL_TIMEOUT_MASK 0xffff0000
-#define MAC_PCU_XRTO_POLL_TIMEOUT_GET(x) (((x) & MAC_PCU_XRTO_POLL_TIMEOUT_MASK) >> MAC_PCU_XRTO_POLL_TIMEOUT_LSB)
-#define MAC_PCU_XRTO_POLL_TIMEOUT_SET(x) (((x) << MAC_PCU_XRTO_POLL_TIMEOUT_LSB) & MAC_PCU_XRTO_POLL_TIMEOUT_MASK)
-#define MAC_PCU_XRTO_CHIRP_TIMEOUT_MSB 15
-#define MAC_PCU_XRTO_CHIRP_TIMEOUT_LSB 0
-#define MAC_PCU_XRTO_CHIRP_TIMEOUT_MASK 0x0000ffff
-#define MAC_PCU_XRTO_CHIRP_TIMEOUT_GET(x) (((x) & MAC_PCU_XRTO_CHIRP_TIMEOUT_MASK) >> MAC_PCU_XRTO_CHIRP_TIMEOUT_LSB)
-#define MAC_PCU_XRTO_CHIRP_TIMEOUT_SET(x) (((x) << MAC_PCU_XRTO_CHIRP_TIMEOUT_LSB) & MAC_PCU_XRTO_CHIRP_TIMEOUT_MASK)
-
-#define MAC_PCU_XRCRP_ADDRESS 0x0000807c
-#define MAC_PCU_XRCRP_OFFSET 0x0000007c
-#define MAC_PCU_XRCRP_CHIRP_GAP_MSB 31
-#define MAC_PCU_XRCRP_CHIRP_GAP_LSB 16
-#define MAC_PCU_XRCRP_CHIRP_GAP_MASK 0xffff0000
-#define MAC_PCU_XRCRP_CHIRP_GAP_GET(x) (((x) & MAC_PCU_XRCRP_CHIRP_GAP_MASK) >> MAC_PCU_XRCRP_CHIRP_GAP_LSB)
-#define MAC_PCU_XRCRP_CHIRP_GAP_SET(x) (((x) << MAC_PCU_XRCRP_CHIRP_GAP_LSB) & MAC_PCU_XRCRP_CHIRP_GAP_MASK)
-#define MAC_PCU_XRCRP_SEND_CHIRP_MSB 0
-#define MAC_PCU_XRCRP_SEND_CHIRP_LSB 0
-#define MAC_PCU_XRCRP_SEND_CHIRP_MASK 0x00000001
-#define MAC_PCU_XRCRP_SEND_CHIRP_GET(x) (((x) & MAC_PCU_XRCRP_SEND_CHIRP_MASK) >> MAC_PCU_XRCRP_SEND_CHIRP_LSB)
-#define MAC_PCU_XRCRP_SEND_CHIRP_SET(x) (((x) << MAC_PCU_XRCRP_SEND_CHIRP_LSB) & MAC_PCU_XRCRP_SEND_CHIRP_MASK)
-
-#define MAC_PCU_XRSTMP_ADDRESS 0x00008080
-#define MAC_PCU_XRSTMP_OFFSET 0x00000080
-#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_MSB 23
-#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_LSB 16
-#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_MASK 0x00ff0000
-#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_GET(x) (((x) & MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_MASK) >> MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_LSB)
-#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_SET(x) (((x) << MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_LSB) & MAC_PCU_XRSTMP_RX_ABORT_RSSI_THRESH_MASK)
-#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_MSB 15
-#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_LSB 8
-#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_MASK 0x0000ff00
-#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_GET(x) (((x) & MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_MASK) >> MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_LSB)
-#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_SET(x) (((x) << MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_LSB) & MAC_PCU_XRSTMP_TX_STOMP_RSSI_THRESH_MASK)
-#define MAC_PCU_XRSTMP_RX_ABORT_DATA_MSB 5
-#define MAC_PCU_XRSTMP_RX_ABORT_DATA_LSB 5
-#define MAC_PCU_XRSTMP_RX_ABORT_DATA_MASK 0x00000020
-#define MAC_PCU_XRSTMP_RX_ABORT_DATA_GET(x) (((x) & MAC_PCU_XRSTMP_RX_ABORT_DATA_MASK) >> MAC_PCU_XRSTMP_RX_ABORT_DATA_LSB)
-#define MAC_PCU_XRSTMP_RX_ABORT_DATA_SET(x) (((x) << MAC_PCU_XRSTMP_RX_ABORT_DATA_LSB) & MAC_PCU_XRSTMP_RX_ABORT_DATA_MASK)
-#define MAC_PCU_XRSTMP_TX_STOMP_DATA_MSB 4
-#define MAC_PCU_XRSTMP_TX_STOMP_DATA_LSB 4
-#define MAC_PCU_XRSTMP_TX_STOMP_DATA_MASK 0x00000010
-#define MAC_PCU_XRSTMP_TX_STOMP_DATA_GET(x) (((x) & MAC_PCU_XRSTMP_TX_STOMP_DATA_MASK) >> MAC_PCU_XRSTMP_TX_STOMP_DATA_LSB)
-#define MAC_PCU_XRSTMP_TX_STOMP_DATA_SET(x) (((x) << MAC_PCU_XRSTMP_TX_STOMP_DATA_LSB) & MAC_PCU_XRSTMP_TX_STOMP_DATA_MASK)
-#define MAC_PCU_XRSTMP_TX_STOMP_BSSID_MSB 3
-#define MAC_PCU_XRSTMP_TX_STOMP_BSSID_LSB 3
-#define MAC_PCU_XRSTMP_TX_STOMP_BSSID_MASK 0x00000008
-#define MAC_PCU_XRSTMP_TX_STOMP_BSSID_GET(x) (((x) & MAC_PCU_XRSTMP_TX_STOMP_BSSID_MASK) >> MAC_PCU_XRSTMP_TX_STOMP_BSSID_LSB)
-#define MAC_PCU_XRSTMP_TX_STOMP_BSSID_SET(x) (((x) << MAC_PCU_XRSTMP_TX_STOMP_BSSID_LSB) & MAC_PCU_XRSTMP_TX_STOMP_BSSID_MASK)
-#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_MSB 2
-#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_LSB 2
-#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_MASK 0x00000004
-#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_GET(x) (((x) & MAC_PCU_XRSTMP_TX_STOMP_RSSI_MASK) >> MAC_PCU_XRSTMP_TX_STOMP_RSSI_LSB)
-#define MAC_PCU_XRSTMP_TX_STOMP_RSSI_SET(x) (((x) << MAC_PCU_XRSTMP_TX_STOMP_RSSI_LSB) & MAC_PCU_XRSTMP_TX_STOMP_RSSI_MASK)
-#define MAC_PCU_XRSTMP_RX_ABORT_BSSID_MSB 1
-#define MAC_PCU_XRSTMP_RX_ABORT_BSSID_LSB 1
-#define MAC_PCU_XRSTMP_RX_ABORT_BSSID_MASK 0x00000002
-#define MAC_PCU_XRSTMP_RX_ABORT_BSSID_GET(x) (((x) & MAC_PCU_XRSTMP_RX_ABORT_BSSID_MASK) >> MAC_PCU_XRSTMP_RX_ABORT_BSSID_LSB)
-#define MAC_PCU_XRSTMP_RX_ABORT_BSSID_SET(x) (((x) << MAC_PCU_XRSTMP_RX_ABORT_BSSID_LSB) & MAC_PCU_XRSTMP_RX_ABORT_BSSID_MASK)
-#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_MSB 0
-#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_LSB 0
-#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_MASK 0x00000001
-#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_GET(x) (((x) & MAC_PCU_XRSTMP_RX_ABORT_RSSI_MASK) >> MAC_PCU_XRSTMP_RX_ABORT_RSSI_LSB)
-#define MAC_PCU_XRSTMP_RX_ABORT_RSSI_SET(x) (((x) << MAC_PCU_XRSTMP_RX_ABORT_RSSI_LSB) & MAC_PCU_XRSTMP_RX_ABORT_RSSI_MASK)
-
-#define MAC_PCU_ADDR1_MASK_L32_ADDRESS 0x00008084
-#define MAC_PCU_ADDR1_MASK_L32_OFFSET 0x00000084
-#define MAC_PCU_ADDR1_MASK_L32_VALUE_MSB 31
-#define MAC_PCU_ADDR1_MASK_L32_VALUE_LSB 0
-#define MAC_PCU_ADDR1_MASK_L32_VALUE_MASK 0xffffffff
-#define MAC_PCU_ADDR1_MASK_L32_VALUE_GET(x) (((x) & MAC_PCU_ADDR1_MASK_L32_VALUE_MASK) >> MAC_PCU_ADDR1_MASK_L32_VALUE_LSB)
-#define MAC_PCU_ADDR1_MASK_L32_VALUE_SET(x) (((x) << MAC_PCU_ADDR1_MASK_L32_VALUE_LSB) & MAC_PCU_ADDR1_MASK_L32_VALUE_MASK)
-
-#define MAC_PCU_ADDR1_MASK_U16_ADDRESS 0x00008088
-#define MAC_PCU_ADDR1_MASK_U16_OFFSET 0x00000088
-#define MAC_PCU_ADDR1_MASK_U16_VALUE_MSB 15
-#define MAC_PCU_ADDR1_MASK_U16_VALUE_LSB 0
-#define MAC_PCU_ADDR1_MASK_U16_VALUE_MASK 0x0000ffff
-#define MAC_PCU_ADDR1_MASK_U16_VALUE_GET(x) (((x) & MAC_PCU_ADDR1_MASK_U16_VALUE_MASK) >> MAC_PCU_ADDR1_MASK_U16_VALUE_LSB)
-#define MAC_PCU_ADDR1_MASK_U16_VALUE_SET(x) (((x) << MAC_PCU_ADDR1_MASK_U16_VALUE_LSB) & MAC_PCU_ADDR1_MASK_U16_VALUE_MASK)
-
-#define MAC_PCU_TPC_ADDRESS 0x0000808c
-#define MAC_PCU_TPC_OFFSET 0x0000008c
-#define MAC_PCU_TPC_CHIRP_PWR_MSB 21
-#define MAC_PCU_TPC_CHIRP_PWR_LSB 16
-#define MAC_PCU_TPC_CHIRP_PWR_MASK 0x003f0000
-#define MAC_PCU_TPC_CHIRP_PWR_GET(x) (((x) & MAC_PCU_TPC_CHIRP_PWR_MASK) >> MAC_PCU_TPC_CHIRP_PWR_LSB)
-#define MAC_PCU_TPC_CHIRP_PWR_SET(x) (((x) << MAC_PCU_TPC_CHIRP_PWR_LSB) & MAC_PCU_TPC_CHIRP_PWR_MASK)
-#define MAC_PCU_TPC_CTS_PWR_MSB 13
-#define MAC_PCU_TPC_CTS_PWR_LSB 8
-#define MAC_PCU_TPC_CTS_PWR_MASK 0x00003f00
-#define MAC_PCU_TPC_CTS_PWR_GET(x) (((x) & MAC_PCU_TPC_CTS_PWR_MASK) >> MAC_PCU_TPC_CTS_PWR_LSB)
-#define MAC_PCU_TPC_CTS_PWR_SET(x) (((x) << MAC_PCU_TPC_CTS_PWR_LSB) & MAC_PCU_TPC_CTS_PWR_MASK)
-#define MAC_PCU_TPC_ACK_PWR_MSB 5
-#define MAC_PCU_TPC_ACK_PWR_LSB 0
-#define MAC_PCU_TPC_ACK_PWR_MASK 0x0000003f
-#define MAC_PCU_TPC_ACK_PWR_GET(x) (((x) & MAC_PCU_TPC_ACK_PWR_MASK) >> MAC_PCU_TPC_ACK_PWR_LSB)
-#define MAC_PCU_TPC_ACK_PWR_SET(x) (((x) << MAC_PCU_TPC_ACK_PWR_LSB) & MAC_PCU_TPC_ACK_PWR_MASK)
-
-#define MAC_PCU_TX_FRAME_CNT_ADDRESS 0x00008090
-#define MAC_PCU_TX_FRAME_CNT_OFFSET 0x00000090
-#define MAC_PCU_TX_FRAME_CNT_VALUE_MSB 31
-#define MAC_PCU_TX_FRAME_CNT_VALUE_LSB 0
-#define MAC_PCU_TX_FRAME_CNT_VALUE_MASK 0xffffffff
-#define MAC_PCU_TX_FRAME_CNT_VALUE_GET(x) (((x) & MAC_PCU_TX_FRAME_CNT_VALUE_MASK) >> MAC_PCU_TX_FRAME_CNT_VALUE_LSB)
-#define MAC_PCU_TX_FRAME_CNT_VALUE_SET(x) (((x) << MAC_PCU_TX_FRAME_CNT_VALUE_LSB) & MAC_PCU_TX_FRAME_CNT_VALUE_MASK)
-
-#define MAC_PCU_RX_FRAME_CNT_ADDRESS 0x00008094
-#define MAC_PCU_RX_FRAME_CNT_OFFSET 0x00000094
-#define MAC_PCU_RX_FRAME_CNT_VALUE_MSB 31
-#define MAC_PCU_RX_FRAME_CNT_VALUE_LSB 0
-#define MAC_PCU_RX_FRAME_CNT_VALUE_MASK 0xffffffff
-#define MAC_PCU_RX_FRAME_CNT_VALUE_GET(x) (((x) & MAC_PCU_RX_FRAME_CNT_VALUE_MASK) >> MAC_PCU_RX_FRAME_CNT_VALUE_LSB)
-#define MAC_PCU_RX_FRAME_CNT_VALUE_SET(x) (((x) << MAC_PCU_RX_FRAME_CNT_VALUE_LSB) & MAC_PCU_RX_FRAME_CNT_VALUE_MASK)
-
-#define MAC_PCU_RX_CLEAR_CNT_ADDRESS 0x00008098
-#define MAC_PCU_RX_CLEAR_CNT_OFFSET 0x00000098
-#define MAC_PCU_RX_CLEAR_CNT_VALUE_MSB 31
-#define MAC_PCU_RX_CLEAR_CNT_VALUE_LSB 0
-#define MAC_PCU_RX_CLEAR_CNT_VALUE_MASK 0xffffffff
-#define MAC_PCU_RX_CLEAR_CNT_VALUE_GET(x) (((x) & MAC_PCU_RX_CLEAR_CNT_VALUE_MASK) >> MAC_PCU_RX_CLEAR_CNT_VALUE_LSB)
-#define MAC_PCU_RX_CLEAR_CNT_VALUE_SET(x) (((x) << MAC_PCU_RX_CLEAR_CNT_VALUE_LSB) & MAC_PCU_RX_CLEAR_CNT_VALUE_MASK)
-
-#define MAC_PCU_CYCLE_CNT_ADDRESS 0x0000809c
-#define MAC_PCU_CYCLE_CNT_OFFSET 0x0000009c
-#define MAC_PCU_CYCLE_CNT_VALUE_MSB 31
-#define MAC_PCU_CYCLE_CNT_VALUE_LSB 0
-#define MAC_PCU_CYCLE_CNT_VALUE_MASK 0xffffffff
-#define MAC_PCU_CYCLE_CNT_VALUE_GET(x) (((x) & MAC_PCU_CYCLE_CNT_VALUE_MASK) >> MAC_PCU_CYCLE_CNT_VALUE_LSB)
-#define MAC_PCU_CYCLE_CNT_VALUE_SET(x) (((x) << MAC_PCU_CYCLE_CNT_VALUE_LSB) & MAC_PCU_CYCLE_CNT_VALUE_MASK)
-
-#define MAC_PCU_QUIET_TIME_1_ADDRESS 0x000080a0
-#define MAC_PCU_QUIET_TIME_1_OFFSET 0x000000a0
-#define MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_MSB 17
-#define MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_LSB 17
-#define MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_MASK 0x00020000
-#define MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_GET(x) (((x) & MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_MASK) >> MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_LSB)
-#define MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_SET(x) (((x) << MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_LSB) & MAC_PCU_QUIET_TIME_1_ACK_CTS_ENABLE_MASK)
-
-#define MAC_PCU_QUIET_TIME_2_ADDRESS 0x000080a4
-#define MAC_PCU_QUIET_TIME_2_OFFSET 0x000000a4
-#define MAC_PCU_QUIET_TIME_2_DURATION_MSB 31
-#define MAC_PCU_QUIET_TIME_2_DURATION_LSB 16
-#define MAC_PCU_QUIET_TIME_2_DURATION_MASK 0xffff0000
-#define MAC_PCU_QUIET_TIME_2_DURATION_GET(x) (((x) & MAC_PCU_QUIET_TIME_2_DURATION_MASK) >> MAC_PCU_QUIET_TIME_2_DURATION_LSB)
-#define MAC_PCU_QUIET_TIME_2_DURATION_SET(x) (((x) << MAC_PCU_QUIET_TIME_2_DURATION_LSB) & MAC_PCU_QUIET_TIME_2_DURATION_MASK)
-
-#define MAC_PCU_QOS_NO_ACK_ADDRESS 0x000080a8
-#define MAC_PCU_QOS_NO_ACK_OFFSET 0x000000a8
-#define MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_MSB 8
-#define MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_LSB 7
-#define MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_MASK 0x00000180
-#define MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_GET(x) (((x) & MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_MASK) >> MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_LSB)
-#define MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_SET(x) (((x) << MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_LSB) & MAC_PCU_QOS_NO_ACK_BYTE_OFFSET_MASK)
-#define MAC_PCU_QOS_NO_ACK_BIT_OFFSET_MSB 6
-#define MAC_PCU_QOS_NO_ACK_BIT_OFFSET_LSB 4
-#define MAC_PCU_QOS_NO_ACK_BIT_OFFSET_MASK 0x00000070
-#define MAC_PCU_QOS_NO_ACK_BIT_OFFSET_GET(x) (((x) & MAC_PCU_QOS_NO_ACK_BIT_OFFSET_MASK) >> MAC_PCU_QOS_NO_ACK_BIT_OFFSET_LSB)
-#define MAC_PCU_QOS_NO_ACK_BIT_OFFSET_SET(x) (((x) << MAC_PCU_QOS_NO_ACK_BIT_OFFSET_LSB) & MAC_PCU_QOS_NO_ACK_BIT_OFFSET_MASK)
-#define MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_MSB 3
-#define MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_LSB 0
-#define MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_MASK 0x0000000f
-#define MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_GET(x) (((x) & MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_MASK) >> MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_LSB)
-#define MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_SET(x) (((x) << MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_LSB) & MAC_PCU_QOS_NO_ACK_TWO_BIT_VALUES_MASK)
-
-#define MAC_PCU_PHY_ERROR_MASK_ADDRESS 0x000080ac
-#define MAC_PCU_PHY_ERROR_MASK_OFFSET 0x000000ac
-#define MAC_PCU_PHY_ERROR_MASK_VALUE_MSB 31
-#define MAC_PCU_PHY_ERROR_MASK_VALUE_LSB 0
-#define MAC_PCU_PHY_ERROR_MASK_VALUE_MASK 0xffffffff
-#define MAC_PCU_PHY_ERROR_MASK_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERROR_MASK_VALUE_MASK) >> MAC_PCU_PHY_ERROR_MASK_VALUE_LSB)
-#define MAC_PCU_PHY_ERROR_MASK_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERROR_MASK_VALUE_LSB) & MAC_PCU_PHY_ERROR_MASK_VALUE_MASK)
-
-#define MAC_PCU_XRLAT_ADDRESS 0x000080b0
-#define MAC_PCU_XRLAT_OFFSET 0x000000b0
-#define MAC_PCU_XRLAT_VALUE_MSB 11
-#define MAC_PCU_XRLAT_VALUE_LSB 0
-#define MAC_PCU_XRLAT_VALUE_MASK 0x00000fff
-#define MAC_PCU_XRLAT_VALUE_GET(x) (((x) & MAC_PCU_XRLAT_VALUE_MASK) >> MAC_PCU_XRLAT_VALUE_LSB)
-#define MAC_PCU_XRLAT_VALUE_SET(x) (((x) << MAC_PCU_XRLAT_VALUE_LSB) & MAC_PCU_XRLAT_VALUE_MASK)
-
-#define MAC_PCU_RXBUF_ADDRESS 0x000080b4
-#define MAC_PCU_RXBUF_OFFSET 0x000000b4
-#define MAC_PCU_RXBUF_REG_RD_ENABLE_MSB 11
-#define MAC_PCU_RXBUF_REG_RD_ENABLE_LSB 11
-#define MAC_PCU_RXBUF_REG_RD_ENABLE_MASK 0x00000800
-#define MAC_PCU_RXBUF_REG_RD_ENABLE_GET(x) (((x) & MAC_PCU_RXBUF_REG_RD_ENABLE_MASK) >> MAC_PCU_RXBUF_REG_RD_ENABLE_LSB)
-#define MAC_PCU_RXBUF_REG_RD_ENABLE_SET(x) (((x) << MAC_PCU_RXBUF_REG_RD_ENABLE_LSB) & MAC_PCU_RXBUF_REG_RD_ENABLE_MASK)
-#define MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_MSB 10
-#define MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_LSB 0
-#define MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_MASK 0x000007ff
-#define MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_GET(x) (((x) & MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_MASK) >> MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_LSB)
-#define MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_SET(x) (((x) << MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_LSB) & MAC_PCU_RXBUF_HIGH_PRIORITY_THRSHD_MASK)
-
-#define MAC_PCU_MIC_QOS_CONTROL_ADDRESS 0x000080b8
-#define MAC_PCU_MIC_QOS_CONTROL_OFFSET 0x000000b8
-#define MAC_PCU_MIC_QOS_CONTROL_ENABLE_MSB 16
-#define MAC_PCU_MIC_QOS_CONTROL_ENABLE_LSB 16
-#define MAC_PCU_MIC_QOS_CONTROL_ENABLE_MASK 0x00010000
-#define MAC_PCU_MIC_QOS_CONTROL_ENABLE_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL_ENABLE_MASK) >> MAC_PCU_MIC_QOS_CONTROL_ENABLE_LSB)
-#define MAC_PCU_MIC_QOS_CONTROL_ENABLE_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTROL_ENABLE_LSB) & MAC_PCU_MIC_QOS_CONTROL_ENABLE_MASK)
-#define MAC_PCU_MIC_QOS_CONTROL_VALUE_7_MSB 15
-#define MAC_PCU_MIC_QOS_CONTROL_VALUE_7_LSB 14
-#define MAC_PCU_MIC_QOS_CONTROL_VALUE_7_MASK 0x0000c000
-#define MAC_PCU_MIC_QOS_CONTROL_VALUE_7_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_7_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_7_LSB)
-#define MAC_PCU_MIC_QOS_CONTROL_VALUE_7_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_7_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_7_MASK)
-#define MAC_PCU_MIC_QOS_CONTROL_VALUE_6_MSB 13
-#define MAC_PCU_MIC_QOS_CONTROL_VALUE_6_LSB 12
-#define MAC_PCU_MIC_QOS_CONTROL_VALUE_6_MASK 0x00003000
-#define MAC_PCU_MIC_QOS_CONTROL_VALUE_6_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_6_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_6_LSB)
-#define MAC_PCU_MIC_QOS_CONTROL_VALUE_6_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_6_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_6_MASK)
-#define MAC_PCU_MIC_QOS_CONTROL_VALUE_5_MSB 11
-#define MAC_PCU_MIC_QOS_CONTROL_VALUE_5_LSB 10
-#define MAC_PCU_MIC_QOS_CONTROL_VALUE_5_MASK 0x00000c00
-#define MAC_PCU_MIC_QOS_CONTROL_VALUE_5_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_5_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_5_LSB)
-#define MAC_PCU_MIC_QOS_CONTROL_VALUE_5_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_5_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_5_MASK)
-#define MAC_PCU_MIC_QOS_CONTROL_VALUE_4_MSB 9
-#define MAC_PCU_MIC_QOS_CONTROL_VALUE_4_LSB 8
-#define MAC_PCU_MIC_QOS_CONTROL_VALUE_4_MASK 0x00000300
-#define MAC_PCU_MIC_QOS_CONTROL_VALUE_4_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_4_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_4_LSB)
-#define MAC_PCU_MIC_QOS_CONTROL_VALUE_4_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_4_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_4_MASK)
-#define MAC_PCU_MIC_QOS_CONTROL_VALUE_3_MSB 7
-#define MAC_PCU_MIC_QOS_CONTROL_VALUE_3_LSB 6
-#define MAC_PCU_MIC_QOS_CONTROL_VALUE_3_MASK 0x000000c0
-#define MAC_PCU_MIC_QOS_CONTROL_VALUE_3_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_3_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_3_LSB)
-#define MAC_PCU_MIC_QOS_CONTROL_VALUE_3_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_3_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_3_MASK)
-#define MAC_PCU_MIC_QOS_CONTROL_VALUE_2_MSB 5
-#define MAC_PCU_MIC_QOS_CONTROL_VALUE_2_LSB 4
-#define MAC_PCU_MIC_QOS_CONTROL_VALUE_2_MASK 0x00000030
-#define MAC_PCU_MIC_QOS_CONTROL_VALUE_2_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_2_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_2_LSB)
-#define MAC_PCU_MIC_QOS_CONTROL_VALUE_2_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_2_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_2_MASK)
-#define MAC_PCU_MIC_QOS_CONTROL_VALUE_1_MSB 3
-#define MAC_PCU_MIC_QOS_CONTROL_VALUE_1_LSB 2
-#define MAC_PCU_MIC_QOS_CONTROL_VALUE_1_MASK 0x0000000c
-#define MAC_PCU_MIC_QOS_CONTROL_VALUE_1_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_1_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_1_LSB)
-#define MAC_PCU_MIC_QOS_CONTROL_VALUE_1_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_1_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_1_MASK)
-#define MAC_PCU_MIC_QOS_CONTROL_VALUE_0_MSB 1
-#define MAC_PCU_MIC_QOS_CONTROL_VALUE_0_LSB 0
-#define MAC_PCU_MIC_QOS_CONTROL_VALUE_0_MASK 0x00000003
-#define MAC_PCU_MIC_QOS_CONTROL_VALUE_0_GET(x) (((x) & MAC_PCU_MIC_QOS_CONTROL_VALUE_0_MASK) >> MAC_PCU_MIC_QOS_CONTROL_VALUE_0_LSB)
-#define MAC_PCU_MIC_QOS_CONTROL_VALUE_0_SET(x) (((x) << MAC_PCU_MIC_QOS_CONTROL_VALUE_0_LSB) & MAC_PCU_MIC_QOS_CONTROL_VALUE_0_MASK)
-
-#define MAC_PCU_MIC_QOS_SELECT_ADDRESS 0x000080bc
-#define MAC_PCU_MIC_QOS_SELECT_OFFSET 0x000000bc
-#define MAC_PCU_MIC_QOS_SELECT_VALUE_7_MSB 31
-#define MAC_PCU_MIC_QOS_SELECT_VALUE_7_LSB 28
-#define MAC_PCU_MIC_QOS_SELECT_VALUE_7_MASK 0xf0000000
-#define MAC_PCU_MIC_QOS_SELECT_VALUE_7_GET(x) (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_7_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_7_LSB)
-#define MAC_PCU_MIC_QOS_SELECT_VALUE_7_SET(x) (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_7_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_7_MASK)
-#define MAC_PCU_MIC_QOS_SELECT_VALUE_6_MSB 27
-#define MAC_PCU_MIC_QOS_SELECT_VALUE_6_LSB 24
-#define MAC_PCU_MIC_QOS_SELECT_VALUE_6_MASK 0x0f000000
-#define MAC_PCU_MIC_QOS_SELECT_VALUE_6_GET(x) (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_6_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_6_LSB)
-#define MAC_PCU_MIC_QOS_SELECT_VALUE_6_SET(x) (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_6_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_6_MASK)
-#define MAC_PCU_MIC_QOS_SELECT_VALUE_5_MSB 23
-#define MAC_PCU_MIC_QOS_SELECT_VALUE_5_LSB 20
-#define MAC_PCU_MIC_QOS_SELECT_VALUE_5_MASK 0x00f00000
-#define MAC_PCU_MIC_QOS_SELECT_VALUE_5_GET(x) (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_5_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_5_LSB)
-#define MAC_PCU_MIC_QOS_SELECT_VALUE_5_SET(x) (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_5_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_5_MASK)
-#define MAC_PCU_MIC_QOS_SELECT_VALUE_4_MSB 19
-#define MAC_PCU_MIC_QOS_SELECT_VALUE_4_LSB 16
-#define MAC_PCU_MIC_QOS_SELECT_VALUE_4_MASK 0x000f0000
-#define MAC_PCU_MIC_QOS_SELECT_VALUE_4_GET(x) (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_4_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_4_LSB)
-#define MAC_PCU_MIC_QOS_SELECT_VALUE_4_SET(x) (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_4_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_4_MASK)
-#define MAC_PCU_MIC_QOS_SELECT_VALUE_3_MSB 15
-#define MAC_PCU_MIC_QOS_SELECT_VALUE_3_LSB 12
-#define MAC_PCU_MIC_QOS_SELECT_VALUE_3_MASK 0x0000f000
-#define MAC_PCU_MIC_QOS_SELECT_VALUE_3_GET(x) (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_3_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_3_LSB)
-#define MAC_PCU_MIC_QOS_SELECT_VALUE_3_SET(x) (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_3_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_3_MASK)
-#define MAC_PCU_MIC_QOS_SELECT_VALUE_2_MSB 11
-#define MAC_PCU_MIC_QOS_SELECT_VALUE_2_LSB 8
-#define MAC_PCU_MIC_QOS_SELECT_VALUE_2_MASK 0x00000f00
-#define MAC_PCU_MIC_QOS_SELECT_VALUE_2_GET(x) (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_2_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_2_LSB)
-#define MAC_PCU_MIC_QOS_SELECT_VALUE_2_SET(x) (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_2_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_2_MASK)
-#define MAC_PCU_MIC_QOS_SELECT_VALUE_1_MSB 7
-#define MAC_PCU_MIC_QOS_SELECT_VALUE_1_LSB 4
-#define MAC_PCU_MIC_QOS_SELECT_VALUE_1_MASK 0x000000f0
-#define MAC_PCU_MIC_QOS_SELECT_VALUE_1_GET(x) (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_1_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_1_LSB)
-#define MAC_PCU_MIC_QOS_SELECT_VALUE_1_SET(x) (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_1_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_1_MASK)
-#define MAC_PCU_MIC_QOS_SELECT_VALUE_0_MSB 3
-#define MAC_PCU_MIC_QOS_SELECT_VALUE_0_LSB 0
-#define MAC_PCU_MIC_QOS_SELECT_VALUE_0_MASK 0x0000000f
-#define MAC_PCU_MIC_QOS_SELECT_VALUE_0_GET(x) (((x) & MAC_PCU_MIC_QOS_SELECT_VALUE_0_MASK) >> MAC_PCU_MIC_QOS_SELECT_VALUE_0_LSB)
-#define MAC_PCU_MIC_QOS_SELECT_VALUE_0_SET(x) (((x) << MAC_PCU_MIC_QOS_SELECT_VALUE_0_LSB) & MAC_PCU_MIC_QOS_SELECT_VALUE_0_MASK)
-
-#define MAC_PCU_MISC_MODE_ADDRESS 0x000080c0
-#define MAC_PCU_MISC_MODE_OFFSET 0x000000c0
-#define MAC_PCU_MISC_MODE_DEBUG_MODE_MSB 31
-#define MAC_PCU_MISC_MODE_DEBUG_MODE_LSB 30
-#define MAC_PCU_MISC_MODE_DEBUG_MODE_MASK 0xc0000000
-#define MAC_PCU_MISC_MODE_DEBUG_MODE_GET(x) (((x) & MAC_PCU_MISC_MODE_DEBUG_MODE_MASK) >> MAC_PCU_MISC_MODE_DEBUG_MODE_LSB)
-#define MAC_PCU_MISC_MODE_DEBUG_MODE_SET(x) (((x) << MAC_PCU_MISC_MODE_DEBUG_MODE_LSB) & MAC_PCU_MISC_MODE_DEBUG_MODE_MASK)
-#define MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_MSB 29
-#define MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_LSB 29
-#define MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_MASK 0x20000000
-#define MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_GET(x) (((x) & MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_MASK) >> MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_LSB)
-#define MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_SET(x) (((x) << MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_LSB) & MAC_PCU_MISC_MODE_USE_EOP_PTR_FOR_DMA_WR_MASK)
-#define MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_MSB 28
-#define MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_LSB 28
-#define MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_MASK 0x10000000
-#define MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_GET(x) (((x) & MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_MASK) >> MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_LSB)
-#define MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_SET(x) (((x) << MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_LSB) & MAC_PCU_MISC_MODE_ALWAYS_PERFORM_KEY_SEARCH_MASK)
-#define MAC_PCU_MISC_MODE_SEL_EVM_MSB 27
-#define MAC_PCU_MISC_MODE_SEL_EVM_LSB 27
-#define MAC_PCU_MISC_MODE_SEL_EVM_MASK 0x08000000
-#define MAC_PCU_MISC_MODE_SEL_EVM_GET(x) (((x) & MAC_PCU_MISC_MODE_SEL_EVM_MASK) >> MAC_PCU_MISC_MODE_SEL_EVM_LSB)
-#define MAC_PCU_MISC_MODE_SEL_EVM_SET(x) (((x) << MAC_PCU_MISC_MODE_SEL_EVM_LSB) & MAC_PCU_MISC_MODE_SEL_EVM_MASK)
-#define MAC_PCU_MISC_MODE_CLEAR_BA_VALID_MSB 26
-#define MAC_PCU_MISC_MODE_CLEAR_BA_VALID_LSB 26
-#define MAC_PCU_MISC_MODE_CLEAR_BA_VALID_MASK 0x04000000
-#define MAC_PCU_MISC_MODE_CLEAR_BA_VALID_GET(x) (((x) & MAC_PCU_MISC_MODE_CLEAR_BA_VALID_MASK) >> MAC_PCU_MISC_MODE_CLEAR_BA_VALID_LSB)
-#define MAC_PCU_MISC_MODE_CLEAR_BA_VALID_SET(x) (((x) << MAC_PCU_MISC_MODE_CLEAR_BA_VALID_LSB) & MAC_PCU_MISC_MODE_CLEAR_BA_VALID_MASK)
-#define MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_MSB 25
-#define MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_LSB 25
-#define MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_MASK 0x02000000
-#define MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_GET(x) (((x) & MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_MASK) >> MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_LSB)
-#define MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_SET(x) (((x) << MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_LSB) & MAC_PCU_MISC_MODE_CLEAR_FIRST_HCF_MASK)
-#define MAC_PCU_MISC_MODE_CLEAR_VMF_MSB 24
-#define MAC_PCU_MISC_MODE_CLEAR_VMF_LSB 24
-#define MAC_PCU_MISC_MODE_CLEAR_VMF_MASK 0x01000000
-#define MAC_PCU_MISC_MODE_CLEAR_VMF_GET(x) (((x) & MAC_PCU_MISC_MODE_CLEAR_VMF_MASK) >> MAC_PCU_MISC_MODE_CLEAR_VMF_LSB)
-#define MAC_PCU_MISC_MODE_CLEAR_VMF_SET(x) (((x) << MAC_PCU_MISC_MODE_CLEAR_VMF_LSB) & MAC_PCU_MISC_MODE_CLEAR_VMF_MASK)
-#define MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_MSB 23
-#define MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_LSB 23
-#define MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_MASK 0x00800000
-#define MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_MASK) >> MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_LSB)
-#define MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_SET(x) (((x) << MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_LSB) & MAC_PCU_MISC_MODE_RX_HCF_POLL_ENABLE_MASK)
-#define MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_MSB 22
-#define MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_LSB 22
-#define MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_MASK 0x00400000
-#define MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_GET(x) (((x) & MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_MASK) >> MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_LSB)
-#define MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_SET(x) (((x) << MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_LSB) & MAC_PCU_MISC_MODE_HCF_POLL_CANCELS_NAV_MASK)
-#define MAC_PCU_MISC_MODE_TBTT_PROTECT_MSB 21
-#define MAC_PCU_MISC_MODE_TBTT_PROTECT_LSB 21
-#define MAC_PCU_MISC_MODE_TBTT_PROTECT_MASK 0x00200000
-#define MAC_PCU_MISC_MODE_TBTT_PROTECT_GET(x) (((x) & MAC_PCU_MISC_MODE_TBTT_PROTECT_MASK) >> MAC_PCU_MISC_MODE_TBTT_PROTECT_LSB)
-#define MAC_PCU_MISC_MODE_TBTT_PROTECT_SET(x) (((x) << MAC_PCU_MISC_MODE_TBTT_PROTECT_LSB) & MAC_PCU_MISC_MODE_TBTT_PROTECT_MASK)
-#define MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_MSB 20
-#define MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_LSB 20
-#define MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_MASK 0x00100000
-#define MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_GET(x) (((x) & MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_MASK) >> MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_LSB)
-#define MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_SET(x) (((x) << MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_LSB) & MAC_PCU_MISC_MODE_BT_ANT_PREVENTS_RX_MASK)
-#define MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_MSB 18
-#define MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_LSB 18
-#define MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_MASK 0x00040000
-#define MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_GET(x) (((x) & MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_MASK) >> MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_LSB)
-#define MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_SET(x) (((x) << MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_LSB) & MAC_PCU_MISC_MODE_FORCE_QUIET_COLLISION_MASK)
-#define MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_MSB 14
-#define MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_LSB 14
-#define MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_MASK 0x00004000
-#define MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_GET(x) (((x) & MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_MASK) >> MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_LSB)
-#define MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_SET(x) (((x) << MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_LSB) & MAC_PCU_MISC_MODE_MISS_BEACON_IN_SLEEP_MASK)
-#define MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_MSB 12
-#define MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_LSB 12
-#define MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_MASK 0x00001000
-#define MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_MASK) >> MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_LSB)
-#define MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_SET(x) (((x) << MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_LSB) & MAC_PCU_MISC_MODE_TXOP_TBTT_LIMIT_ENABLE_MASK)
-#define MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_MSB 11
-#define MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_LSB 11
-#define MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_MASK 0x00000800
-#define MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_GET(x) (((x) & MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_MASK) >> MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_LSB)
-#define MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_SET(x) (((x) << MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_LSB) & MAC_PCU_MISC_MODE_KC_RX_ANT_UPDATE_MASK)
-#define MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_MSB 10
-#define MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_LSB 10
-#define MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_MASK 0x00000400
-#define MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_GET(x) (((x) & MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_MASK) >> MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_LSB)
-#define MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_SET(x) (((x) << MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_LSB) & MAC_PCU_MISC_MODE_DEBUG_MODE_SIFS_MASK)
-#define MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_MSB 9
-#define MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_LSB 9
-#define MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_MASK 0x00000200
-#define MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_GET(x) (((x) & MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_MASK) >> MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_LSB)
-#define MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_SET(x) (((x) << MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_LSB) & MAC_PCU_MISC_MODE_DEBUG_MODE_BA_BITMAP_MASK)
-#define MAC_PCU_MISC_MODE_CCK_SIFS_MODE_MSB 4
-#define MAC_PCU_MISC_MODE_CCK_SIFS_MODE_LSB 4
-#define MAC_PCU_MISC_MODE_CCK_SIFS_MODE_MASK 0x00000010
-#define MAC_PCU_MISC_MODE_CCK_SIFS_MODE_GET(x) (((x) & MAC_PCU_MISC_MODE_CCK_SIFS_MODE_MASK) >> MAC_PCU_MISC_MODE_CCK_SIFS_MODE_LSB)
-#define MAC_PCU_MISC_MODE_CCK_SIFS_MODE_SET(x) (((x) << MAC_PCU_MISC_MODE_CCK_SIFS_MODE_LSB) & MAC_PCU_MISC_MODE_CCK_SIFS_MODE_MASK)
-#define MAC_PCU_MISC_MODE_TX_ADD_TSF_MSB 3
-#define MAC_PCU_MISC_MODE_TX_ADD_TSF_LSB 3
-#define MAC_PCU_MISC_MODE_TX_ADD_TSF_MASK 0x00000008
-#define MAC_PCU_MISC_MODE_TX_ADD_TSF_GET(x) (((x) & MAC_PCU_MISC_MODE_TX_ADD_TSF_MASK) >> MAC_PCU_MISC_MODE_TX_ADD_TSF_LSB)
-#define MAC_PCU_MISC_MODE_TX_ADD_TSF_SET(x) (((x) << MAC_PCU_MISC_MODE_TX_ADD_TSF_LSB) & MAC_PCU_MISC_MODE_TX_ADD_TSF_MASK)
-#define MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_MSB 2
-#define MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_LSB 2
-#define MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_MASK 0x00000004
-#define MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_MASK) >> MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_LSB)
-#define MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_SET(x) (((x) << MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_LSB) & MAC_PCU_MISC_MODE_MIC_NEW_LOCATION_ENABLE_MASK)
-#define MAC_PCU_MISC_MODE_DEBUG_MODE_AD_MSB 1
-#define MAC_PCU_MISC_MODE_DEBUG_MODE_AD_LSB 1
-#define MAC_PCU_MISC_MODE_DEBUG_MODE_AD_MASK 0x00000002
-#define MAC_PCU_MISC_MODE_DEBUG_MODE_AD_GET(x) (((x) & MAC_PCU_MISC_MODE_DEBUG_MODE_AD_MASK) >> MAC_PCU_MISC_MODE_DEBUG_MODE_AD_LSB)
-#define MAC_PCU_MISC_MODE_DEBUG_MODE_AD_SET(x) (((x) << MAC_PCU_MISC_MODE_DEBUG_MODE_AD_LSB) & MAC_PCU_MISC_MODE_DEBUG_MODE_AD_MASK)
-#define MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_MSB 0
-#define MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_LSB 0
-#define MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_MASK 0x00000001
-#define MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_GET(x) (((x) & MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_MASK) >> MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_LSB)
-#define MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_SET(x) (((x) << MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_LSB) & MAC_PCU_MISC_MODE_BSSID_MATCH_FORCE_MASK)
-
-#define MAC_PCU_FILTER_OFDM_CNT_ADDRESS 0x000080c4
-#define MAC_PCU_FILTER_OFDM_CNT_OFFSET 0x000000c4
-#define MAC_PCU_FILTER_OFDM_CNT_VALUE_MSB 23
-#define MAC_PCU_FILTER_OFDM_CNT_VALUE_LSB 0
-#define MAC_PCU_FILTER_OFDM_CNT_VALUE_MASK 0x00ffffff
-#define MAC_PCU_FILTER_OFDM_CNT_VALUE_GET(x) (((x) & MAC_PCU_FILTER_OFDM_CNT_VALUE_MASK) >> MAC_PCU_FILTER_OFDM_CNT_VALUE_LSB)
-#define MAC_PCU_FILTER_OFDM_CNT_VALUE_SET(x) (((x) << MAC_PCU_FILTER_OFDM_CNT_VALUE_LSB) & MAC_PCU_FILTER_OFDM_CNT_VALUE_MASK)
-
-#define MAC_PCU_FILTER_CCK_CNT_ADDRESS 0x000080c8
-#define MAC_PCU_FILTER_CCK_CNT_OFFSET 0x000000c8
-#define MAC_PCU_FILTER_CCK_CNT_VALUE_MSB 23
-#define MAC_PCU_FILTER_CCK_CNT_VALUE_LSB 0
-#define MAC_PCU_FILTER_CCK_CNT_VALUE_MASK 0x00ffffff
-#define MAC_PCU_FILTER_CCK_CNT_VALUE_GET(x) (((x) & MAC_PCU_FILTER_CCK_CNT_VALUE_MASK) >> MAC_PCU_FILTER_CCK_CNT_VALUE_LSB)
-#define MAC_PCU_FILTER_CCK_CNT_VALUE_SET(x) (((x) << MAC_PCU_FILTER_CCK_CNT_VALUE_LSB) & MAC_PCU_FILTER_CCK_CNT_VALUE_MASK)
-
-#define MAC_PCU_PHY_ERR_CNT_1_ADDRESS 0x000080cc
-#define MAC_PCU_PHY_ERR_CNT_1_OFFSET 0x000000cc
-#define MAC_PCU_PHY_ERR_CNT_1_VALUE_MSB 23
-#define MAC_PCU_PHY_ERR_CNT_1_VALUE_LSB 0
-#define MAC_PCU_PHY_ERR_CNT_1_VALUE_MASK 0x00ffffff
-#define MAC_PCU_PHY_ERR_CNT_1_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_1_VALUE_MASK) >> MAC_PCU_PHY_ERR_CNT_1_VALUE_LSB)
-#define MAC_PCU_PHY_ERR_CNT_1_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_1_VALUE_LSB) & MAC_PCU_PHY_ERR_CNT_1_VALUE_MASK)
-
-#define MAC_PCU_PHY_ERR_CNT_1_MASK_ADDRESS 0x000080d0
-#define MAC_PCU_PHY_ERR_CNT_1_MASK_OFFSET 0x000000d0
-#define MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_MSB 31
-#define MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_LSB 0
-#define MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_MASK 0xffffffff
-#define MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_MASK) >> MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_LSB)
-#define MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_LSB) & MAC_PCU_PHY_ERR_CNT_1_MASK_VALUE_MASK)
-
-#define MAC_PCU_PHY_ERR_CNT_2_ADDRESS 0x000080d4
-#define MAC_PCU_PHY_ERR_CNT_2_OFFSET 0x000000d4
-#define MAC_PCU_PHY_ERR_CNT_2_VALUE_MSB 23
-#define MAC_PCU_PHY_ERR_CNT_2_VALUE_LSB 0
-#define MAC_PCU_PHY_ERR_CNT_2_VALUE_MASK 0x00ffffff
-#define MAC_PCU_PHY_ERR_CNT_2_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_2_VALUE_MASK) >> MAC_PCU_PHY_ERR_CNT_2_VALUE_LSB)
-#define MAC_PCU_PHY_ERR_CNT_2_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_2_VALUE_LSB) & MAC_PCU_PHY_ERR_CNT_2_VALUE_MASK)
-
-#define MAC_PCU_PHY_ERR_CNT_2_MASK_ADDRESS 0x000080d8
-#define MAC_PCU_PHY_ERR_CNT_2_MASK_OFFSET 0x000000d8
-#define MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_MSB 31
-#define MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_LSB 0
-#define MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_MASK 0xffffffff
-#define MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_MASK) >> MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_LSB)
-#define MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_LSB) & MAC_PCU_PHY_ERR_CNT_2_MASK_VALUE_MASK)
-
-#define MAC_PCU_TSF_THRESHOLD_ADDRESS 0x000080dc
-#define MAC_PCU_TSF_THRESHOLD_OFFSET 0x000000dc
-#define MAC_PCU_TSF_THRESHOLD_VALUE_MSB 15
-#define MAC_PCU_TSF_THRESHOLD_VALUE_LSB 0
-#define MAC_PCU_TSF_THRESHOLD_VALUE_MASK 0x0000ffff
-#define MAC_PCU_TSF_THRESHOLD_VALUE_GET(x) (((x) & MAC_PCU_TSF_THRESHOLD_VALUE_MASK) >> MAC_PCU_TSF_THRESHOLD_VALUE_LSB)
-#define MAC_PCU_TSF_THRESHOLD_VALUE_SET(x) (((x) << MAC_PCU_TSF_THRESHOLD_VALUE_LSB) & MAC_PCU_TSF_THRESHOLD_VALUE_MASK)
-
-#define MAC_PCU_PHY_ERROR_EIFS_MASK_ADDRESS 0x000080e0
-#define MAC_PCU_PHY_ERROR_EIFS_MASK_OFFSET 0x000000e0
-#define MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_MSB 31
-#define MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_LSB 0
-#define MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_MASK 0xffffffff
-#define MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_MASK) >> MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_LSB)
-#define MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_LSB) & MAC_PCU_PHY_ERROR_EIFS_MASK_VALUE_MASK)
-
-#define MAC_PCU_PHY_ERR_CNT_3_ADDRESS 0x000080e4
-#define MAC_PCU_PHY_ERR_CNT_3_OFFSET 0x000000e4
-#define MAC_PCU_PHY_ERR_CNT_3_VALUE_MSB 23
-#define MAC_PCU_PHY_ERR_CNT_3_VALUE_LSB 0
-#define MAC_PCU_PHY_ERR_CNT_3_VALUE_MASK 0x00ffffff
-#define MAC_PCU_PHY_ERR_CNT_3_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_3_VALUE_MASK) >> MAC_PCU_PHY_ERR_CNT_3_VALUE_LSB)
-#define MAC_PCU_PHY_ERR_CNT_3_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_3_VALUE_LSB) & MAC_PCU_PHY_ERR_CNT_3_VALUE_MASK)
-
-#define MAC_PCU_PHY_ERR_CNT_3_MASK_ADDRESS 0x000080e8
-#define MAC_PCU_PHY_ERR_CNT_3_MASK_OFFSET 0x000000e8
-#define MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_MSB 31
-#define MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_LSB 0
-#define MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_MASK 0xffffffff
-#define MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_MASK) >> MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_LSB)
-#define MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_LSB) & MAC_PCU_PHY_ERR_CNT_3_MASK_VALUE_MASK)
-
-#define MAC_PCU_BLUETOOTH_MODE_ADDRESS 0x000080ec
-#define MAC_PCU_BLUETOOTH_MODE_OFFSET 0x000000ec
-#define MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_MSB 31
-#define MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_LSB 24
-#define MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_MASK 0xff000000
-#define MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_MASK) >> MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_LSB)
-#define MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_LSB) & MAC_PCU_BLUETOOTH_MODE_FIRST_SLOT_TIME_MASK)
-#define MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_MSB 23
-#define MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_LSB 18
-#define MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_MASK 0x00fc0000
-#define MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_MASK) >> MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_LSB)
-#define MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_LSB) & MAC_PCU_BLUETOOTH_MODE_PRIORITY_TIME_MASK)
-#define MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_MSB 17
-#define MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_LSB 17
-#define MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_MASK 0x00020000
-#define MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_MASK) >> MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_LSB)
-#define MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_LSB) & MAC_PCU_BLUETOOTH_MODE_RX_CLEAR_POLARITY_MASK)
-#define MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_MSB 16
-#define MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_LSB 13
-#define MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_MASK 0x0001e000
-#define MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_MASK) >> MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_LSB)
-#define MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_LSB) & MAC_PCU_BLUETOOTH_MODE_QCU_THRESH_MASK)
-#define MAC_PCU_BLUETOOTH_MODE_QUIET_MSB 12
-#define MAC_PCU_BLUETOOTH_MODE_QUIET_LSB 12
-#define MAC_PCU_BLUETOOTH_MODE_QUIET_MASK 0x00001000
-#define MAC_PCU_BLUETOOTH_MODE_QUIET_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_QUIET_MASK) >> MAC_PCU_BLUETOOTH_MODE_QUIET_LSB)
-#define MAC_PCU_BLUETOOTH_MODE_QUIET_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_QUIET_LSB) & MAC_PCU_BLUETOOTH_MODE_QUIET_MASK)
-#define MAC_PCU_BLUETOOTH_MODE_MODE_MSB 11
-#define MAC_PCU_BLUETOOTH_MODE_MODE_LSB 10
-#define MAC_PCU_BLUETOOTH_MODE_MODE_MASK 0x00000c00
-#define MAC_PCU_BLUETOOTH_MODE_MODE_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_MODE_MASK) >> MAC_PCU_BLUETOOTH_MODE_MODE_LSB)
-#define MAC_PCU_BLUETOOTH_MODE_MODE_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_MODE_LSB) & MAC_PCU_BLUETOOTH_MODE_MODE_MASK)
-#define MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_MSB 9
-#define MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_LSB 9
-#define MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_MASK 0x00000200
-#define MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_MASK) >> MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_LSB)
-#define MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_LSB) & MAC_PCU_BLUETOOTH_MODE_TX_FRAME_EXTEND_MASK)
-#define MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_MSB 8
-#define MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_LSB 8
-#define MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_MASK 0x00000100
-#define MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_MASK) >> MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_LSB)
-#define MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_LSB) & MAC_PCU_BLUETOOTH_MODE_TX_STATE_EXTEND_MASK)
-#define MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_MSB 7
-#define MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_LSB 0
-#define MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_MASK 0x000000ff
-#define MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_MASK) >> MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_LSB)
-#define MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_LSB) & MAC_PCU_BLUETOOTH_MODE_TIME_EXTEND_MASK)
-
-#define MAC_PCU_BLUETOOTH_WEIGHTS_ADDRESS 0x000080f0
-#define MAC_PCU_BLUETOOTH_WEIGHTS_OFFSET 0x000000f0
-#define MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_MSB 31
-#define MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_LSB 16
-#define MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_MASK 0xffff0000
-#define MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_GET(x) (((x) & MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_MASK) >> MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_LSB)
-#define MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_SET(x) (((x) << MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_LSB) & MAC_PCU_BLUETOOTH_WEIGHTS_WL_WEIGHT_MASK)
-#define MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_MSB 15
-#define MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_LSB 0
-#define MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_MASK 0x0000ffff
-#define MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_GET(x) (((x) & MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_MASK) >> MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_LSB)
-#define MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_SET(x) (((x) << MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_LSB) & MAC_PCU_BLUETOOTH_WEIGHTS_BT_WEIGHT_MASK)
-
-#define MAC_PCU_BLUETOOTH_MODE2_ADDRESS 0x000080f4
-#define MAC_PCU_BLUETOOTH_MODE2_OFFSET 0x000000f4
-#define MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_MSB 31
-#define MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_LSB 31
-#define MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_MASK 0x80000000
-#define MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_MASK) >> MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_LSB)
-#define MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_LSB) & MAC_PCU_BLUETOOTH_MODE2_PHY_ERR_BT_COLL_ENABLE_MASK)
-#define MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_MSB 30
-#define MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_LSB 30
-#define MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_MASK 0x40000000
-#define MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_MASK) >> MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_LSB)
-#define MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_LSB) & MAC_PCU_BLUETOOTH_MODE2_INTERRUPT_ENABLE_MASK)
-#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_MSB 29
-#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_LSB 28
-#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_MASK 0x30000000
-#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_MASK) >> MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_LSB)
-#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_LSB) & MAC_PCU_BLUETOOTH_MODE2_TSF_BT_PRIORITY_CTRL_MASK)
-#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_MSB 27
-#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_LSB 26
-#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_MASK 0x0c000000
-#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_MASK) >> MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_LSB)
-#define MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_LSB) & MAC_PCU_BLUETOOTH_MODE2_TSF_BT_ACTIVE_CTRL_MASK)
-#define MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_MSB 25
-#define MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_LSB 25
-#define MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_MASK 0x02000000
-#define MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_MASK) >> MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_LSB)
-#define MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_LSB) & MAC_PCU_BLUETOOTH_MODE2_RS_DISCARD_EXTEND_MASK)
-#define MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_MSB 24
-#define MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_LSB 24
-#define MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_MASK 0x01000000
-#define MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_MASK) >> MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_LSB)
-#define MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_LSB) & MAC_PCU_BLUETOOTH_MODE2_WL_TXRX_SEPARATE_MASK)
-#define MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_MSB 23
-#define MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_LSB 22
-#define MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_MASK 0x00c00000
-#define MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_MASK) >> MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_LSB)
-#define MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_LSB) & MAC_PCU_BLUETOOTH_MODE2_WL_ACTIVE_MODE_MASK)
-#define MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_MSB 21
-#define MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_LSB 21
-#define MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_MASK 0x00200000
-#define MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_MASK) >> MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_LSB)
-#define MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_LSB) & MAC_PCU_BLUETOOTH_MODE2_QUIET_2_WIRE_MASK)
-#define MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_MSB 20
-#define MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_LSB 20
-#define MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_MASK 0x00100000
-#define MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_MASK) >> MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_LSB)
-#define MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_LSB) & MAC_PCU_BLUETOOTH_MODE2_DISABLE_BT_ANT_MASK)
-#define MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_MSB 19
-#define MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_LSB 19
-#define MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_MASK 0x00080000
-#define MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_MASK) >> MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_LSB)
-#define MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_LSB) & MAC_PCU_BLUETOOTH_MODE2_PROTECT_BT_AFTER_WAKEUP_MASK)
-#define MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_MSB 17
-#define MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_LSB 17
-#define MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_MASK 0x00020000
-#define MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_MASK) >> MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_LSB)
-#define MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_LSB) & MAC_PCU_BLUETOOTH_MODE2_SLEEP_ALLOW_BT_ACCESS_MASK)
-#define MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_MSB 16
-#define MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_LSB 16
-#define MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_MASK 0x00010000
-#define MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_MASK) >> MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_LSB)
-#define MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_LSB) & MAC_PCU_BLUETOOTH_MODE2_HOLD_RX_CLEAR_MASK)
-#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_MSB 15
-#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_LSB 8
-#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_MASK 0x0000ff00
-#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_MASK) >> MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_LSB)
-#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_LSB) & MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_CNT_MASK)
-#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_MSB 7
-#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_LSB 0
-#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_MASK 0x000000ff
-#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_MASK) >> MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_LSB)
-#define MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_LSB) & MAC_PCU_BLUETOOTH_MODE2_BCN_MISS_THRESH_MASK)
-
-#define MAC_PCU_TXSIFS_ADDRESS 0x000080f8
-#define MAC_PCU_TXSIFS_OFFSET 0x000000f8
-#define MAC_PCU_TXSIFS_ACK_SHIFT_MSB 14
-#define MAC_PCU_TXSIFS_ACK_SHIFT_LSB 12
-#define MAC_PCU_TXSIFS_ACK_SHIFT_MASK 0x00007000
-#define MAC_PCU_TXSIFS_ACK_SHIFT_GET(x) (((x) & MAC_PCU_TXSIFS_ACK_SHIFT_MASK) >> MAC_PCU_TXSIFS_ACK_SHIFT_LSB)
-#define MAC_PCU_TXSIFS_ACK_SHIFT_SET(x) (((x) << MAC_PCU_TXSIFS_ACK_SHIFT_LSB) & MAC_PCU_TXSIFS_ACK_SHIFT_MASK)
-#define MAC_PCU_TXSIFS_TX_LATENCY_MSB 11
-#define MAC_PCU_TXSIFS_TX_LATENCY_LSB 8
-#define MAC_PCU_TXSIFS_TX_LATENCY_MASK 0x00000f00
-#define MAC_PCU_TXSIFS_TX_LATENCY_GET(x) (((x) & MAC_PCU_TXSIFS_TX_LATENCY_MASK) >> MAC_PCU_TXSIFS_TX_LATENCY_LSB)
-#define MAC_PCU_TXSIFS_TX_LATENCY_SET(x) (((x) << MAC_PCU_TXSIFS_TX_LATENCY_LSB) & MAC_PCU_TXSIFS_TX_LATENCY_MASK)
-#define MAC_PCU_TXSIFS_SIFS_TIME_MSB 7
-#define MAC_PCU_TXSIFS_SIFS_TIME_LSB 0
-#define MAC_PCU_TXSIFS_SIFS_TIME_MASK 0x000000ff
-#define MAC_PCU_TXSIFS_SIFS_TIME_GET(x) (((x) & MAC_PCU_TXSIFS_SIFS_TIME_MASK) >> MAC_PCU_TXSIFS_SIFS_TIME_LSB)
-#define MAC_PCU_TXSIFS_SIFS_TIME_SET(x) (((x) << MAC_PCU_TXSIFS_SIFS_TIME_LSB) & MAC_PCU_TXSIFS_SIFS_TIME_MASK)
-
-#define MAC_PCU_TXOP_X_ADDRESS 0x000080fc
-#define MAC_PCU_TXOP_X_OFFSET 0x000000fc
-#define MAC_PCU_TXOP_X_VALUE_MSB 7
-#define MAC_PCU_TXOP_X_VALUE_LSB 0
-#define MAC_PCU_TXOP_X_VALUE_MASK 0x000000ff
-#define MAC_PCU_TXOP_X_VALUE_GET(x) (((x) & MAC_PCU_TXOP_X_VALUE_MASK) >> MAC_PCU_TXOP_X_VALUE_LSB)
-#define MAC_PCU_TXOP_X_VALUE_SET(x) (((x) << MAC_PCU_TXOP_X_VALUE_LSB) & MAC_PCU_TXOP_X_VALUE_MASK)
-
-#define MAC_PCU_TXOP_0_3_ADDRESS 0x00008100
-#define MAC_PCU_TXOP_0_3_OFFSET 0x00000100
-#define MAC_PCU_TXOP_0_3_VALUE_3_MSB 31
-#define MAC_PCU_TXOP_0_3_VALUE_3_LSB 24
-#define MAC_PCU_TXOP_0_3_VALUE_3_MASK 0xff000000
-#define MAC_PCU_TXOP_0_3_VALUE_3_GET(x) (((x) & MAC_PCU_TXOP_0_3_VALUE_3_MASK) >> MAC_PCU_TXOP_0_3_VALUE_3_LSB)
-#define MAC_PCU_TXOP_0_3_VALUE_3_SET(x) (((x) << MAC_PCU_TXOP_0_3_VALUE_3_LSB) & MAC_PCU_TXOP_0_3_VALUE_3_MASK)
-#define MAC_PCU_TXOP_0_3_VALUE_2_MSB 23
-#define MAC_PCU_TXOP_0_3_VALUE_2_LSB 16
-#define MAC_PCU_TXOP_0_3_VALUE_2_MASK 0x00ff0000
-#define MAC_PCU_TXOP_0_3_VALUE_2_GET(x) (((x) & MAC_PCU_TXOP_0_3_VALUE_2_MASK) >> MAC_PCU_TXOP_0_3_VALUE_2_LSB)
-#define MAC_PCU_TXOP_0_3_VALUE_2_SET(x) (((x) << MAC_PCU_TXOP_0_3_VALUE_2_LSB) & MAC_PCU_TXOP_0_3_VALUE_2_MASK)
-#define MAC_PCU_TXOP_0_3_VALUE_1_MSB 15
-#define MAC_PCU_TXOP_0_3_VALUE_1_LSB 8
-#define MAC_PCU_TXOP_0_3_VALUE_1_MASK 0x0000ff00
-#define MAC_PCU_TXOP_0_3_VALUE_1_GET(x) (((x) & MAC_PCU_TXOP_0_3_VALUE_1_MASK) >> MAC_PCU_TXOP_0_3_VALUE_1_LSB)
-#define MAC_PCU_TXOP_0_3_VALUE_1_SET(x) (((x) << MAC_PCU_TXOP_0_3_VALUE_1_LSB) & MAC_PCU_TXOP_0_3_VALUE_1_MASK)
-#define MAC_PCU_TXOP_0_3_VALUE_0_MSB 7
-#define MAC_PCU_TXOP_0_3_VALUE_0_LSB 0
-#define MAC_PCU_TXOP_0_3_VALUE_0_MASK 0x000000ff
-#define MAC_PCU_TXOP_0_3_VALUE_0_GET(x) (((x) & MAC_PCU_TXOP_0_3_VALUE_0_MASK) >> MAC_PCU_TXOP_0_3_VALUE_0_LSB)
-#define MAC_PCU_TXOP_0_3_VALUE_0_SET(x) (((x) << MAC_PCU_TXOP_0_3_VALUE_0_LSB) & MAC_PCU_TXOP_0_3_VALUE_0_MASK)
-
-#define MAC_PCU_TXOP_4_7_ADDRESS 0x00008104
-#define MAC_PCU_TXOP_4_7_OFFSET 0x00000104
-#define MAC_PCU_TXOP_4_7_VALUE_7_MSB 31
-#define MAC_PCU_TXOP_4_7_VALUE_7_LSB 24
-#define MAC_PCU_TXOP_4_7_VALUE_7_MASK 0xff000000
-#define MAC_PCU_TXOP_4_7_VALUE_7_GET(x) (((x) & MAC_PCU_TXOP_4_7_VALUE_7_MASK) >> MAC_PCU_TXOP_4_7_VALUE_7_LSB)
-#define MAC_PCU_TXOP_4_7_VALUE_7_SET(x) (((x) << MAC_PCU_TXOP_4_7_VALUE_7_LSB) & MAC_PCU_TXOP_4_7_VALUE_7_MASK)
-#define MAC_PCU_TXOP_4_7_VALUE_6_MSB 23
-#define MAC_PCU_TXOP_4_7_VALUE_6_LSB 16
-#define MAC_PCU_TXOP_4_7_VALUE_6_MASK 0x00ff0000
-#define MAC_PCU_TXOP_4_7_VALUE_6_GET(x) (((x) & MAC_PCU_TXOP_4_7_VALUE_6_MASK) >> MAC_PCU_TXOP_4_7_VALUE_6_LSB)
-#define MAC_PCU_TXOP_4_7_VALUE_6_SET(x) (((x) << MAC_PCU_TXOP_4_7_VALUE_6_LSB) & MAC_PCU_TXOP_4_7_VALUE_6_MASK)
-#define MAC_PCU_TXOP_4_7_VALUE_5_MSB 15
-#define MAC_PCU_TXOP_4_7_VALUE_5_LSB 8
-#define MAC_PCU_TXOP_4_7_VALUE_5_MASK 0x0000ff00
-#define MAC_PCU_TXOP_4_7_VALUE_5_GET(x) (((x) & MAC_PCU_TXOP_4_7_VALUE_5_MASK) >> MAC_PCU_TXOP_4_7_VALUE_5_LSB)
-#define MAC_PCU_TXOP_4_7_VALUE_5_SET(x) (((x) << MAC_PCU_TXOP_4_7_VALUE_5_LSB) & MAC_PCU_TXOP_4_7_VALUE_5_MASK)
-#define MAC_PCU_TXOP_4_7_VALUE_4_MSB 7
-#define MAC_PCU_TXOP_4_7_VALUE_4_LSB 0
-#define MAC_PCU_TXOP_4_7_VALUE_4_MASK 0x000000ff
-#define MAC_PCU_TXOP_4_7_VALUE_4_GET(x) (((x) & MAC_PCU_TXOP_4_7_VALUE_4_MASK) >> MAC_PCU_TXOP_4_7_VALUE_4_LSB)
-#define MAC_PCU_TXOP_4_7_VALUE_4_SET(x) (((x) << MAC_PCU_TXOP_4_7_VALUE_4_LSB) & MAC_PCU_TXOP_4_7_VALUE_4_MASK)
-
-#define MAC_PCU_TXOP_8_11_ADDRESS 0x00008108
-#define MAC_PCU_TXOP_8_11_OFFSET 0x00000108
-#define MAC_PCU_TXOP_8_11_VALUE_11_MSB 31
-#define MAC_PCU_TXOP_8_11_VALUE_11_LSB 24
-#define MAC_PCU_TXOP_8_11_VALUE_11_MASK 0xff000000
-#define MAC_PCU_TXOP_8_11_VALUE_11_GET(x) (((x) & MAC_PCU_TXOP_8_11_VALUE_11_MASK) >> MAC_PCU_TXOP_8_11_VALUE_11_LSB)
-#define MAC_PCU_TXOP_8_11_VALUE_11_SET(x) (((x) << MAC_PCU_TXOP_8_11_VALUE_11_LSB) & MAC_PCU_TXOP_8_11_VALUE_11_MASK)
-#define MAC_PCU_TXOP_8_11_VALUE_10_MSB 23
-#define MAC_PCU_TXOP_8_11_VALUE_10_LSB 16
-#define MAC_PCU_TXOP_8_11_VALUE_10_MASK 0x00ff0000
-#define MAC_PCU_TXOP_8_11_VALUE_10_GET(x) (((x) & MAC_PCU_TXOP_8_11_VALUE_10_MASK) >> MAC_PCU_TXOP_8_11_VALUE_10_LSB)
-#define MAC_PCU_TXOP_8_11_VALUE_10_SET(x) (((x) << MAC_PCU_TXOP_8_11_VALUE_10_LSB) & MAC_PCU_TXOP_8_11_VALUE_10_MASK)
-#define MAC_PCU_TXOP_8_11_VALUE_9_MSB 15
-#define MAC_PCU_TXOP_8_11_VALUE_9_LSB 8
-#define MAC_PCU_TXOP_8_11_VALUE_9_MASK 0x0000ff00
-#define MAC_PCU_TXOP_8_11_VALUE_9_GET(x) (((x) & MAC_PCU_TXOP_8_11_VALUE_9_MASK) >> MAC_PCU_TXOP_8_11_VALUE_9_LSB)
-#define MAC_PCU_TXOP_8_11_VALUE_9_SET(x) (((x) << MAC_PCU_TXOP_8_11_VALUE_9_LSB) & MAC_PCU_TXOP_8_11_VALUE_9_MASK)
-#define MAC_PCU_TXOP_8_11_VALUE_8_MSB 7
-#define MAC_PCU_TXOP_8_11_VALUE_8_LSB 0
-#define MAC_PCU_TXOP_8_11_VALUE_8_MASK 0x000000ff
-#define MAC_PCU_TXOP_8_11_VALUE_8_GET(x) (((x) & MAC_PCU_TXOP_8_11_VALUE_8_MASK) >> MAC_PCU_TXOP_8_11_VALUE_8_LSB)
-#define MAC_PCU_TXOP_8_11_VALUE_8_SET(x) (((x) << MAC_PCU_TXOP_8_11_VALUE_8_LSB) & MAC_PCU_TXOP_8_11_VALUE_8_MASK)
-
-#define MAC_PCU_TXOP_12_15_ADDRESS 0x0000810c
-#define MAC_PCU_TXOP_12_15_OFFSET 0x0000010c
-#define MAC_PCU_TXOP_12_15_VALUE_15_MSB 31
-#define MAC_PCU_TXOP_12_15_VALUE_15_LSB 24
-#define MAC_PCU_TXOP_12_15_VALUE_15_MASK 0xff000000
-#define MAC_PCU_TXOP_12_15_VALUE_15_GET(x) (((x) & MAC_PCU_TXOP_12_15_VALUE_15_MASK) >> MAC_PCU_TXOP_12_15_VALUE_15_LSB)
-#define MAC_PCU_TXOP_12_15_VALUE_15_SET(x) (((x) << MAC_PCU_TXOP_12_15_VALUE_15_LSB) & MAC_PCU_TXOP_12_15_VALUE_15_MASK)
-#define MAC_PCU_TXOP_12_15_VALUE_14_MSB 23
-#define MAC_PCU_TXOP_12_15_VALUE_14_LSB 16
-#define MAC_PCU_TXOP_12_15_VALUE_14_MASK 0x00ff0000
-#define MAC_PCU_TXOP_12_15_VALUE_14_GET(x) (((x) & MAC_PCU_TXOP_12_15_VALUE_14_MASK) >> MAC_PCU_TXOP_12_15_VALUE_14_LSB)
-#define MAC_PCU_TXOP_12_15_VALUE_14_SET(x) (((x) << MAC_PCU_TXOP_12_15_VALUE_14_LSB) & MAC_PCU_TXOP_12_15_VALUE_14_MASK)
-#define MAC_PCU_TXOP_12_15_VALUE_13_MSB 15
-#define MAC_PCU_TXOP_12_15_VALUE_13_LSB 8
-#define MAC_PCU_TXOP_12_15_VALUE_13_MASK 0x0000ff00
-#define MAC_PCU_TXOP_12_15_VALUE_13_GET(x) (((x) & MAC_PCU_TXOP_12_15_VALUE_13_MASK) >> MAC_PCU_TXOP_12_15_VALUE_13_LSB)
-#define MAC_PCU_TXOP_12_15_VALUE_13_SET(x) (((x) << MAC_PCU_TXOP_12_15_VALUE_13_LSB) & MAC_PCU_TXOP_12_15_VALUE_13_MASK)
-#define MAC_PCU_TXOP_12_15_VALUE_12_MSB 7
-#define MAC_PCU_TXOP_12_15_VALUE_12_LSB 0
-#define MAC_PCU_TXOP_12_15_VALUE_12_MASK 0x000000ff
-#define MAC_PCU_TXOP_12_15_VALUE_12_GET(x) (((x) & MAC_PCU_TXOP_12_15_VALUE_12_MASK) >> MAC_PCU_TXOP_12_15_VALUE_12_LSB)
-#define MAC_PCU_TXOP_12_15_VALUE_12_SET(x) (((x) << MAC_PCU_TXOP_12_15_VALUE_12_LSB) & MAC_PCU_TXOP_12_15_VALUE_12_MASK)
-
-#define MAC_PCU_LOGIC_ANALYZER_ADDRESS 0x00008110
-#define MAC_PCU_LOGIC_ANALYZER_OFFSET 0x00000110
-#define MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_MSB 31
-#define MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_LSB 18
-#define MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_MASK 0xfffc0000
-#define MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_MASK) >> MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_LSB)
-#define MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_LSB) & MAC_PCU_LOGIC_ANALYZER_DIAG_MODE_MASK)
-#define MAC_PCU_LOGIC_ANALYZER_INT_ADDR_MSB 17
-#define MAC_PCU_LOGIC_ANALYZER_INT_ADDR_LSB 8
-#define MAC_PCU_LOGIC_ANALYZER_INT_ADDR_MASK 0x0003ff00
-#define MAC_PCU_LOGIC_ANALYZER_INT_ADDR_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_INT_ADDR_MASK) >> MAC_PCU_LOGIC_ANALYZER_INT_ADDR_LSB)
-#define MAC_PCU_LOGIC_ANALYZER_INT_ADDR_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER_INT_ADDR_LSB) & MAC_PCU_LOGIC_ANALYZER_INT_ADDR_MASK)
-#define MAC_PCU_LOGIC_ANALYZER_QCU_SEL_MSB 7
-#define MAC_PCU_LOGIC_ANALYZER_QCU_SEL_LSB 4
-#define MAC_PCU_LOGIC_ANALYZER_QCU_SEL_MASK 0x000000f0
-#define MAC_PCU_LOGIC_ANALYZER_QCU_SEL_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_QCU_SEL_MASK) >> MAC_PCU_LOGIC_ANALYZER_QCU_SEL_LSB)
-#define MAC_PCU_LOGIC_ANALYZER_QCU_SEL_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER_QCU_SEL_LSB) & MAC_PCU_LOGIC_ANALYZER_QCU_SEL_MASK)
-#define MAC_PCU_LOGIC_ANALYZER_ENABLE_MSB 3
-#define MAC_PCU_LOGIC_ANALYZER_ENABLE_LSB 3
-#define MAC_PCU_LOGIC_ANALYZER_ENABLE_MASK 0x00000008
-#define MAC_PCU_LOGIC_ANALYZER_ENABLE_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_ENABLE_MASK) >> MAC_PCU_LOGIC_ANALYZER_ENABLE_LSB)
-#define MAC_PCU_LOGIC_ANALYZER_ENABLE_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER_ENABLE_LSB) & MAC_PCU_LOGIC_ANALYZER_ENABLE_MASK)
-#define MAC_PCU_LOGIC_ANALYZER_STATE_MSB 2
-#define MAC_PCU_LOGIC_ANALYZER_STATE_LSB 2
-#define MAC_PCU_LOGIC_ANALYZER_STATE_MASK 0x00000004
-#define MAC_PCU_LOGIC_ANALYZER_STATE_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_STATE_MASK) >> MAC_PCU_LOGIC_ANALYZER_STATE_LSB)
-#define MAC_PCU_LOGIC_ANALYZER_STATE_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER_STATE_LSB) & MAC_PCU_LOGIC_ANALYZER_STATE_MASK)
-#define MAC_PCU_LOGIC_ANALYZER_CLEAR_MSB 1
-#define MAC_PCU_LOGIC_ANALYZER_CLEAR_LSB 1
-#define MAC_PCU_LOGIC_ANALYZER_CLEAR_MASK 0x00000002
-#define MAC_PCU_LOGIC_ANALYZER_CLEAR_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_CLEAR_MASK) >> MAC_PCU_LOGIC_ANALYZER_CLEAR_LSB)
-#define MAC_PCU_LOGIC_ANALYZER_CLEAR_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER_CLEAR_LSB) & MAC_PCU_LOGIC_ANALYZER_CLEAR_MASK)
-#define MAC_PCU_LOGIC_ANALYZER_HOLD_MSB 0
-#define MAC_PCU_LOGIC_ANALYZER_HOLD_LSB 0
-#define MAC_PCU_LOGIC_ANALYZER_HOLD_MASK 0x00000001
-#define MAC_PCU_LOGIC_ANALYZER_HOLD_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_HOLD_MASK) >> MAC_PCU_LOGIC_ANALYZER_HOLD_LSB)
-#define MAC_PCU_LOGIC_ANALYZER_HOLD_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER_HOLD_LSB) & MAC_PCU_LOGIC_ANALYZER_HOLD_MASK)
-
-#define MAC_PCU_LOGIC_ANALYZER_32L_ADDRESS 0x00008114
-#define MAC_PCU_LOGIC_ANALYZER_32L_OFFSET 0x00000114
-#define MAC_PCU_LOGIC_ANALYZER_32L_MASK_MSB 31
-#define MAC_PCU_LOGIC_ANALYZER_32L_MASK_LSB 0
-#define MAC_PCU_LOGIC_ANALYZER_32L_MASK_MASK 0xffffffff
-#define MAC_PCU_LOGIC_ANALYZER_32L_MASK_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_32L_MASK_MASK) >> MAC_PCU_LOGIC_ANALYZER_32L_MASK_LSB)
-#define MAC_PCU_LOGIC_ANALYZER_32L_MASK_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER_32L_MASK_LSB) & MAC_PCU_LOGIC_ANALYZER_32L_MASK_MASK)
-
-#define MAC_PCU_LOGIC_ANALYZER_16U_ADDRESS 0x00008118
-#define MAC_PCU_LOGIC_ANALYZER_16U_OFFSET 0x00000118
-#define MAC_PCU_LOGIC_ANALYZER_16U_MASK_MSB 15
-#define MAC_PCU_LOGIC_ANALYZER_16U_MASK_LSB 0
-#define MAC_PCU_LOGIC_ANALYZER_16U_MASK_MASK 0x0000ffff
-#define MAC_PCU_LOGIC_ANALYZER_16U_MASK_GET(x) (((x) & MAC_PCU_LOGIC_ANALYZER_16U_MASK_MASK) >> MAC_PCU_LOGIC_ANALYZER_16U_MASK_LSB)
-#define MAC_PCU_LOGIC_ANALYZER_16U_MASK_SET(x) (((x) << MAC_PCU_LOGIC_ANALYZER_16U_MASK_LSB) & MAC_PCU_LOGIC_ANALYZER_16U_MASK_MASK)
-
-#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_ADDRESS 0x0000811c
-#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_OFFSET 0x0000011c
-#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_MSB 23
-#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_LSB 16
-#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_MASK 0x00ff0000
-#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_MASK) >> MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_LSB)
-#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_LSB) & MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK3_MASK)
-#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_MSB 15
-#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_LSB 8
-#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_MASK 0x0000ff00
-#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_MASK) >> MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_LSB)
-#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_LSB) & MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK2_MASK)
-#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_MSB 7
-#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_LSB 0
-#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_MASK 0x000000ff
-#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_GET(x) (((x) & MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_MASK) >> MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_LSB)
-#define MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_SET(x) (((x) << MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_LSB) & MAC_PCU_PHY_ERR_CNT_MASK_CONT_MASK1_MASK)
-
-#define MAC_PCU_AZIMUTH_MODE_ADDRESS 0x00008120
-#define MAC_PCU_AZIMUTH_MODE_OFFSET 0x00000120
-#define MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_MSB 7
-#define MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_LSB 7
-#define MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_MASK 0x00000080
-#define MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_MASK) >> MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_LSB)
-#define MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_LSB) & MAC_PCU_AZIMUTH_MODE_BA_USES_AD1_MASK)
-#define MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_MSB 6
-#define MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_LSB 6
-#define MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_MASK 0x00000040
-#define MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_MASK) >> MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_LSB)
-#define MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_LSB) & MAC_PCU_AZIMUTH_MODE_ACK_CTS_MATCH_TX_AD2_MASK)
-#define MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_MSB 5
-#define MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_LSB 5
-#define MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_MASK 0x00000020
-#define MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_MASK) >> MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_LSB)
-#define MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_LSB) & MAC_PCU_AZIMUTH_MODE_TX_DESC_EN_MASK)
-#define MAC_PCU_AZIMUTH_MODE_CLK_EN_MSB 4
-#define MAC_PCU_AZIMUTH_MODE_CLK_EN_LSB 4
-#define MAC_PCU_AZIMUTH_MODE_CLK_EN_MASK 0x00000010
-#define MAC_PCU_AZIMUTH_MODE_CLK_EN_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_CLK_EN_MASK) >> MAC_PCU_AZIMUTH_MODE_CLK_EN_LSB)
-#define MAC_PCU_AZIMUTH_MODE_CLK_EN_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE_CLK_EN_LSB) & MAC_PCU_AZIMUTH_MODE_CLK_EN_MASK)
-#define MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_MSB 3
-#define MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_LSB 3
-#define MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_MASK 0x00000008
-#define MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_MASK) >> MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_LSB)
-#define MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_LSB) & MAC_PCU_AZIMUTH_MODE_RX_TSF_STATUS_SEL_MASK)
-#define MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_MSB 2
-#define MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_LSB 2
-#define MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_MASK 0x00000004
-#define MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_MASK) >> MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_LSB)
-#define MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_LSB) & MAC_PCU_AZIMUTH_MODE_TX_TSF_STATUS_SEL_MASK)
-#define MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_MSB 1
-#define MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_LSB 1
-#define MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_MASK 0x00000002
-#define MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_MASK) >> MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_LSB)
-#define MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_LSB) & MAC_PCU_AZIMUTH_MODE_KEY_SEARCH_AD1_MASK)
-#define MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_MSB 0
-#define MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_LSB 0
-#define MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_MASK 0x00000001
-#define MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_GET(x) (((x) & MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_MASK) >> MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_LSB)
-#define MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_SET(x) (((x) << MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_LSB) & MAC_PCU_AZIMUTH_MODE_DISABLE_TSF_UPDATE_MASK)
-
-#define MAC_PCU_20_40_MODE_ADDRESS 0x00008124
-#define MAC_PCU_20_40_MODE_OFFSET 0x00000124
-#define MAC_PCU_20_40_MODE_PIFS_CYCLES_MSB 15
-#define MAC_PCU_20_40_MODE_PIFS_CYCLES_LSB 4
-#define MAC_PCU_20_40_MODE_PIFS_CYCLES_MASK 0x0000fff0
-#define MAC_PCU_20_40_MODE_PIFS_CYCLES_GET(x) (((x) & MAC_PCU_20_40_MODE_PIFS_CYCLES_MASK) >> MAC_PCU_20_40_MODE_PIFS_CYCLES_LSB)
-#define MAC_PCU_20_40_MODE_PIFS_CYCLES_SET(x) (((x) << MAC_PCU_20_40_MODE_PIFS_CYCLES_LSB) & MAC_PCU_20_40_MODE_PIFS_CYCLES_MASK)
-#define MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_MSB 3
-#define MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_LSB 3
-#define MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_MASK 0x00000008
-#define MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_GET(x) (((x) & MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_MASK) >> MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_LSB)
-#define MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_SET(x) (((x) << MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_LSB) & MAC_PCU_20_40_MODE_SWAMPED_FORCES_RX_CLEAR_CTL_IDLE_MASK)
-#define MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_MSB 2
-#define MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_LSB 2
-#define MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_MASK 0x00000004
-#define MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_GET(x) (((x) & MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_MASK) >> MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_LSB)
-#define MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_SET(x) (((x) << MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_LSB) & MAC_PCU_20_40_MODE_TX_HT20_ON_EXT_BUSY_MASK)
-#define MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_MSB 1
-#define MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_LSB 1
-#define MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_MASK 0x00000002
-#define MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_GET(x) (((x) & MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_MASK) >> MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_LSB)
-#define MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_SET(x) (((x) << MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_LSB) & MAC_PCU_20_40_MODE_EXT_PIFS_ENABLE_MASK)
-#define MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_MSB 0
-#define MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_LSB 0
-#define MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_MASK 0x00000001
-#define MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_GET(x) (((x) & MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_MASK) >> MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_LSB)
-#define MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_SET(x) (((x) << MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_LSB) & MAC_PCU_20_40_MODE_JOINED_RX_CLEAR_MASK)
-
-#define MAC_PCU_RX_CLEAR_DIFF_CNT_ADDRESS 0x00008128
-#define MAC_PCU_RX_CLEAR_DIFF_CNT_OFFSET 0x00000128
-#define MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_MSB 31
-#define MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_LSB 0
-#define MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_MASK 0xffffffff
-#define MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_GET(x) (((x) & MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_MASK) >> MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_LSB)
-#define MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_SET(x) (((x) << MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_LSB) & MAC_PCU_RX_CLEAR_DIFF_CNT_VALUE_MASK)
-
-#define MAC_PCU_SELF_GEN_ANTENNA_MASK_ADDRESS 0x0000812c
-#define MAC_PCU_SELF_GEN_ANTENNA_MASK_OFFSET 0x0000012c
-#define MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_MSB 2
-#define MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_LSB 0
-#define MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_MASK 0x00000007
-#define MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_GET(x) (((x) & MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_MASK) >> MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_LSB)
-#define MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_SET(x) (((x) << MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_LSB) & MAC_PCU_SELF_GEN_ANTENNA_MASK_VALUE_MASK)
-
-#define MAC_PCU_BA_BAR_CONTROL_ADDRESS 0x00008130
-#define MAC_PCU_BA_BAR_CONTROL_OFFSET 0x00000130
-#define MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_MSB 12
-#define MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_LSB 12
-#define MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_MASK 0x00001000
-#define MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_GET(x) (((x) & MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_MASK) >> MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_LSB)
-#define MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_SET(x) (((x) << MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_LSB) & MAC_PCU_BA_BAR_CONTROL_UPDATE_BA_BITMAP_QOS_NULL_MASK)
-#define MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_MSB 11
-#define MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_LSB 11
-#define MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_MASK 0x00000800
-#define MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_GET(x) (((x) & MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_MASK) >> MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_LSB)
-#define MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_SET(x) (((x) << MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_LSB) & MAC_PCU_BA_BAR_CONTROL_TX_BA_CLEAR_BA_VALID_MASK)
-#define MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_MSB 10
-#define MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_LSB 10
-#define MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_MASK 0x00000400
-#define MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_GET(x) (((x) & MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_MASK) >> MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_LSB)
-#define MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_SET(x) (((x) << MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_LSB) & MAC_PCU_BA_BAR_CONTROL_FORCE_NO_MATCH_MASK)
-#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_MSB 9
-#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_LSB 9
-#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_MASK 0x00000200
-#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_GET(x) (((x) & MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_MASK) >> MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_LSB)
-#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_SET(x) (((x) << MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_LSB) & MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_VALUE_MASK)
-#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_MSB 8
-#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_LSB 8
-#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_MASK 0x00000100
-#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_GET(x) (((x) & MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_MASK) >> MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_LSB)
-#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_SET(x) (((x) << MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_LSB) & MAC_PCU_BA_BAR_CONTROL_COMPRESSED_VALUE_MASK)
-#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_MSB 7
-#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_LSB 4
-#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_MASK 0x000000f0
-#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_GET(x) (((x) & MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_MASK) >> MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_LSB)
-#define MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_SET(x) (((x) << MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_LSB) & MAC_PCU_BA_BAR_CONTROL_ACK_POLICY_OFFSET_MASK)
-#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_MSB 3
-#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_LSB 0
-#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_MASK 0x0000000f
-#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_GET(x) (((x) & MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_MASK) >> MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_LSB)
-#define MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_SET(x) (((x) << MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_LSB) & MAC_PCU_BA_BAR_CONTROL_COMPRESSED_OFFSET_MASK)
-
-#define MAC_PCU_LEGACY_PLCP_SPOOF_ADDRESS 0x00008134
-#define MAC_PCU_LEGACY_PLCP_SPOOF_OFFSET 0x00000134
-#define MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_MSB 12
-#define MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_LSB 8
-#define MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_MASK 0x00001f00
-#define MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_GET(x) (((x) & MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_MASK) >> MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_LSB)
-#define MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_SET(x) (((x) << MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_LSB) & MAC_PCU_LEGACY_PLCP_SPOOF_MIN_LENGTH_MASK)
-#define MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_MSB 7
-#define MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_LSB 0
-#define MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_MASK 0x000000ff
-#define MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_GET(x) (((x) & MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_MASK) >> MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_LSB)
-#define MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_SET(x) (((x) << MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_LSB) & MAC_PCU_LEGACY_PLCP_SPOOF_EIFS_MINUS_DIFS_MASK)
-
-#define MAC_PCU_PHY_ERROR_MASK_CONT_ADDRESS 0x00008138
-#define MAC_PCU_PHY_ERROR_MASK_CONT_OFFSET 0x00000138
-#define MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_MSB 23
-#define MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_LSB 16
-#define MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_MASK 0x00ff0000
-#define MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_MASK) >> MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_LSB)
-#define MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_LSB) & MAC_PCU_PHY_ERROR_MASK_CONT_EIFS_VALUE_MASK)
-#define MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_MSB 7
-#define MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_LSB 0
-#define MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_MASK 0x000000ff
-#define MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_GET(x) (((x) & MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_MASK) >> MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_LSB)
-#define MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_SET(x) (((x) << MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_LSB) & MAC_PCU_PHY_ERROR_MASK_CONT_MASK_VALUE_MASK)
-
-#define MAC_PCU_TX_TIMER_ADDRESS 0x0000813c
-#define MAC_PCU_TX_TIMER_OFFSET 0x0000013c
-#define MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_MSB 25
-#define MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_LSB 25
-#define MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_MASK 0x02000000
-#define MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_GET(x) (((x) & MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_MASK) >> MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_LSB)
-#define MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_SET(x) (((x) << MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_LSB) & MAC_PCU_TX_TIMER_QUIET_TIMER_ENABLE_MASK)
-#define MAC_PCU_TX_TIMER_QUIET_TIMER_MSB 24
-#define MAC_PCU_TX_TIMER_QUIET_TIMER_LSB 20
-#define MAC_PCU_TX_TIMER_QUIET_TIMER_MASK 0x01f00000
-#define MAC_PCU_TX_TIMER_QUIET_TIMER_GET(x) (((x) & MAC_PCU_TX_TIMER_QUIET_TIMER_MASK) >> MAC_PCU_TX_TIMER_QUIET_TIMER_LSB)
-#define MAC_PCU_TX_TIMER_QUIET_TIMER_SET(x) (((x) << MAC_PCU_TX_TIMER_QUIET_TIMER_LSB) & MAC_PCU_TX_TIMER_QUIET_TIMER_MASK)
-#define MAC_PCU_TX_TIMER_RIFS_TIMER_MSB 19
-#define MAC_PCU_TX_TIMER_RIFS_TIMER_LSB 16
-#define MAC_PCU_TX_TIMER_RIFS_TIMER_MASK 0x000f0000
-#define MAC_PCU_TX_TIMER_RIFS_TIMER_GET(x) (((x) & MAC_PCU_TX_TIMER_RIFS_TIMER_MASK) >> MAC_PCU_TX_TIMER_RIFS_TIMER_LSB)
-#define MAC_PCU_TX_TIMER_RIFS_TIMER_SET(x) (((x) << MAC_PCU_TX_TIMER_RIFS_TIMER_LSB) & MAC_PCU_TX_TIMER_RIFS_TIMER_MASK)
-#define MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_MSB 15
-#define MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_LSB 15
-#define MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_MASK 0x00008000
-#define MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_GET(x) (((x) & MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_MASK) >> MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_LSB)
-#define MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_SET(x) (((x) << MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_LSB) & MAC_PCU_TX_TIMER_TX_TIMER_ENABLE_MASK)
-#define MAC_PCU_TX_TIMER_TX_TIMER_MSB 14
-#define MAC_PCU_TX_TIMER_TX_TIMER_LSB 0
-#define MAC_PCU_TX_TIMER_TX_TIMER_MASK 0x00007fff
-#define MAC_PCU_TX_TIMER_TX_TIMER_GET(x) (((x) & MAC_PCU_TX_TIMER_TX_TIMER_MASK) >> MAC_PCU_TX_TIMER_TX_TIMER_LSB)
-#define MAC_PCU_TX_TIMER_TX_TIMER_SET(x) (((x) << MAC_PCU_TX_TIMER_TX_TIMER_LSB) & MAC_PCU_TX_TIMER_TX_TIMER_MASK)
-
-#define MAC_PCU_TXBUF_CTRL_ADDRESS 0x00008140
-#define MAC_PCU_TXBUF_CTRL_OFFSET 0x00000140
-#define MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_MSB 16
-#define MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_LSB 16
-#define MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_MASK 0x00010000
-#define MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_GET(x) (((x) & MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_MASK) >> MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_LSB)
-#define MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_SET(x) (((x) << MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_LSB) & MAC_PCU_TXBUF_CTRL_TX_FIFO_WRAP_ENABLE_MASK)
-#define MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_MSB 11
-#define MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_LSB 0
-#define MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_MASK 0x00000fff
-#define MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_GET(x) (((x) & MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_MASK) >> MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_LSB)
-#define MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_SET(x) (((x) << MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_LSB) & MAC_PCU_TXBUF_CTRL_USABLE_ENTRIES_MASK)
-
-#define MAC_PCU_MISC_MODE2_ADDRESS 0x00008144
-#define MAC_PCU_MISC_MODE2_OFFSET 0x00000144
-#define MAC_PCU_MISC_MODE2_RESERVED_1_MSB 31
-#define MAC_PCU_MISC_MODE2_RESERVED_1_LSB 28
-#define MAC_PCU_MISC_MODE2_RESERVED_1_MASK 0xf0000000
-#define MAC_PCU_MISC_MODE2_RESERVED_1_GET(x) (((x) & MAC_PCU_MISC_MODE2_RESERVED_1_MASK) >> MAC_PCU_MISC_MODE2_RESERVED_1_LSB)
-#define MAC_PCU_MISC_MODE2_RESERVED_1_SET(x) (((x) << MAC_PCU_MISC_MODE2_RESERVED_1_LSB) & MAC_PCU_MISC_MODE2_RESERVED_1_MASK)
-#define MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_MSB 27
-#define MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_LSB 27
-#define MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_MASK 0x08000000
-#define MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_GET(x) (((x) & MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_MASK) >> MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_LSB)
-#define MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_SET(x) (((x) << MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_LSB) & MAC_PCU_MISC_MODE2_RCV_TIMESTAMP_FIX_MASK)
-#define MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_MSB 26
-#define MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_LSB 26
-#define MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_MASK 0x04000000
-#define MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_GET(x) (((x) & MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_MASK) >> MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_LSB)
-#define MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_SET(x) (((x) << MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_LSB) & MAC_PCU_MISC_MODE2_BEACON_FROM_TO_DS_MASK)
-#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_MSB 25
-#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_LSB 25
-#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_MASK 0x02000000
-#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_GET(x) (((x) & MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_MASK) >> MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_LSB)
-#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_SET(x) (((x) << MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_LSB) & MAC_PCU_MISC_MODE2_PM_FIELD_FOR_MGMT_MASK)
-#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_MSB 24
-#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_LSB 24
-#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_MASK 0x01000000
-#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_GET(x) (((x) & MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_MASK) >> MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_LSB)
-#define MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_SET(x) (((x) << MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_LSB) & MAC_PCU_MISC_MODE2_PM_FIELD_FOR_DAT_MASK)
-#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_MSB 23
-#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_LSB 23
-#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_MASK 0x00800000
-#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_GET(x) (((x) & MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_MASK) >> MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_LSB)
-#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_SET(x) (((x) << MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_LSB) & MAC_PCU_MISC_MODE2_IGNORE_TXOP_IF_ZERO_MASK)
-#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_MSB 22
-#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_LSB 22
-#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_MASK 0x00400000
-#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_GET(x) (((x) & MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_MASK) >> MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_LSB)
-#define MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_SET(x) (((x) << MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_LSB) & MAC_PCU_MISC_MODE2_IGNORE_TXOP_1ST_PKT_MASK)
-#define MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_MSB 21
-#define MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_LSB 21
-#define MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_MASK 0x00200000
-#define MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_GET(x) (((x) & MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_MASK) >> MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_LSB)
-#define MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_SET(x) (((x) << MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_LSB) & MAC_PCU_MISC_MODE2_CLEAR_MORE_FRAG_MASK)
-#define MAC_PCU_MISC_MODE2_BUG_28676_MSB 20
-#define MAC_PCU_MISC_MODE2_BUG_28676_LSB 20
-#define MAC_PCU_MISC_MODE2_BUG_28676_MASK 0x00100000
-#define MAC_PCU_MISC_MODE2_BUG_28676_GET(x) (((x) & MAC_PCU_MISC_MODE2_BUG_28676_MASK) >> MAC_PCU_MISC_MODE2_BUG_28676_LSB)
-#define MAC_PCU_MISC_MODE2_BUG_28676_SET(x) (((x) << MAC_PCU_MISC_MODE2_BUG_28676_LSB) & MAC_PCU_MISC_MODE2_BUG_28676_MASK)
-#define MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_MSB 19
-#define MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_LSB 19
-#define MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_MASK 0x00080000
-#define MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_GET(x) (((x) & MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_MASK) >> MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_LSB)
-#define MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_SET(x) (((x) << MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_LSB) & MAC_PCU_MISC_MODE2_DUR_ACCOUNT_BY_BA_MASK)
-#define MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_MSB 18
-#define MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_LSB 18
-#define MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_MASK 0x00040000
-#define MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_GET(x) (((x) & MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_MASK) >> MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_LSB)
-#define MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_SET(x) (((x) << MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_LSB) & MAC_PCU_MISC_MODE2_BC_MC_WAPI_MODE_MASK)
-#define MAC_PCU_MISC_MODE2_AGG_WEP_MSB 17
-#define MAC_PCU_MISC_MODE2_AGG_WEP_LSB 17
-#define MAC_PCU_MISC_MODE2_AGG_WEP_MASK 0x00020000
-#define MAC_PCU_MISC_MODE2_AGG_WEP_GET(x) (((x) & MAC_PCU_MISC_MODE2_AGG_WEP_MASK) >> MAC_PCU_MISC_MODE2_AGG_WEP_LSB)
-#define MAC_PCU_MISC_MODE2_AGG_WEP_SET(x) (((x) << MAC_PCU_MISC_MODE2_AGG_WEP_LSB) & MAC_PCU_MISC_MODE2_AGG_WEP_MASK)
-#define MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_MSB 16
-#define MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_LSB 16
-#define MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_MASK 0x00010000
-#define MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_GET(x) (((x) & MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_MASK) >> MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_LSB)
-#define MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_SET(x) (((x) << MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_LSB) & MAC_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION_MASK)
-#define MAC_PCU_MISC_MODE2_MGMT_QOS_MSB 15
-#define MAC_PCU_MISC_MODE2_MGMT_QOS_LSB 8
-#define MAC_PCU_MISC_MODE2_MGMT_QOS_MASK 0x0000ff00
-#define MAC_PCU_MISC_MODE2_MGMT_QOS_GET(x) (((x) & MAC_PCU_MISC_MODE2_MGMT_QOS_MASK) >> MAC_PCU_MISC_MODE2_MGMT_QOS_LSB)
-#define MAC_PCU_MISC_MODE2_MGMT_QOS_SET(x) (((x) << MAC_PCU_MISC_MODE2_MGMT_QOS_LSB) & MAC_PCU_MISC_MODE2_MGMT_QOS_MASK)
-#define MAC_PCU_MISC_MODE2_CFP_IGNORE_MSB 7
-#define MAC_PCU_MISC_MODE2_CFP_IGNORE_LSB 7
-#define MAC_PCU_MISC_MODE2_CFP_IGNORE_MASK 0x00000080
-#define MAC_PCU_MISC_MODE2_CFP_IGNORE_GET(x) (((x) & MAC_PCU_MISC_MODE2_CFP_IGNORE_MASK) >> MAC_PCU_MISC_MODE2_CFP_IGNORE_LSB)
-#define MAC_PCU_MISC_MODE2_CFP_IGNORE_SET(x) (((x) << MAC_PCU_MISC_MODE2_CFP_IGNORE_LSB) & MAC_PCU_MISC_MODE2_CFP_IGNORE_MASK)
-#define MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_MSB 6
-#define MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_LSB 6
-#define MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_MASK 0x00000040
-#define MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_MASK) >> MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_LSB)
-#define MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_SET(x) (((x) << MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_LSB) & MAC_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE_MASK)
-#define MAC_PCU_MISC_MODE2_RESERVED_2_MSB 5
-#define MAC_PCU_MISC_MODE2_RESERVED_2_LSB 5
-#define MAC_PCU_MISC_MODE2_RESERVED_2_MASK 0x00000020
-#define MAC_PCU_MISC_MODE2_RESERVED_2_GET(x) (((x) & MAC_PCU_MISC_MODE2_RESERVED_2_MASK) >> MAC_PCU_MISC_MODE2_RESERVED_2_LSB)
-#define MAC_PCU_MISC_MODE2_RESERVED_2_SET(x) (((x) << MAC_PCU_MISC_MODE2_RESERVED_2_LSB) & MAC_PCU_MISC_MODE2_RESERVED_2_MASK)
-#define MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_MSB 4
-#define MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_LSB 4
-#define MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_MASK 0x00000010
-#define MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_MASK) >> MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_LSB)
-#define MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_SET(x) (((x) << MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_LSB) & MAC_PCU_MISC_MODE2_BUG_58057_FIX_ENABLE_MASK)
-#define MAC_PCU_MISC_MODE2_RESERVED_0_MSB 3
-#define MAC_PCU_MISC_MODE2_RESERVED_0_LSB 3
-#define MAC_PCU_MISC_MODE2_RESERVED_0_MASK 0x00000008
-#define MAC_PCU_MISC_MODE2_RESERVED_0_GET(x) (((x) & MAC_PCU_MISC_MODE2_RESERVED_0_MASK) >> MAC_PCU_MISC_MODE2_RESERVED_0_LSB)
-#define MAC_PCU_MISC_MODE2_RESERVED_0_SET(x) (((x) << MAC_PCU_MISC_MODE2_RESERVED_0_LSB) & MAC_PCU_MISC_MODE2_RESERVED_0_MASK)
-#define MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_MSB 2
-#define MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_LSB 2
-#define MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_MASK 0x00000004
-#define MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_GET(x) (((x) & MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_MASK) >> MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_LSB)
-#define MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_SET(x) (((x) << MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_LSB) & MAC_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT_MASK)
-#define MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_MSB 1
-#define MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_LSB 1
-#define MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_MASK 0x00000002
-#define MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_MASK) >> MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_LSB)
-#define MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_SET(x) (((x) << MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_LSB) & MAC_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE_MASK)
-#define MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_MSB 0
-#define MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_LSB 0
-#define MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_MASK 0x00000001
-#define MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_GET(x) (((x) & MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_MASK) >> MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_LSB)
-#define MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_SET(x) (((x) << MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_LSB) & MAC_PCU_MISC_MODE2_BUG_21532_FIX_ENABLE_MASK)
-
-#define MAC_PCU_ALT_AES_MUTE_MASK_ADDRESS 0x00008148
-#define MAC_PCU_ALT_AES_MUTE_MASK_OFFSET 0x00000148
-#define MAC_PCU_ALT_AES_MUTE_MASK_QOS_MSB 31
-#define MAC_PCU_ALT_AES_MUTE_MASK_QOS_LSB 16
-#define MAC_PCU_ALT_AES_MUTE_MASK_QOS_MASK 0xffff0000
-#define MAC_PCU_ALT_AES_MUTE_MASK_QOS_GET(x) (((x) & MAC_PCU_ALT_AES_MUTE_MASK_QOS_MASK) >> MAC_PCU_ALT_AES_MUTE_MASK_QOS_LSB)
-#define MAC_PCU_ALT_AES_MUTE_MASK_QOS_SET(x) (((x) << MAC_PCU_ALT_AES_MUTE_MASK_QOS_LSB) & MAC_PCU_ALT_AES_MUTE_MASK_QOS_MASK)
-
-#define MAC_PCU_AZIMUTH_TIME_STAMP_ADDRESS 0x0000814c
-#define MAC_PCU_AZIMUTH_TIME_STAMP_OFFSET 0x0000014c
-#define MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_MSB 31
-#define MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_LSB 0
-#define MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_MASK 0xffffffff
-#define MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_GET(x) (((x) & MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_MASK) >> MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_LSB)
-#define MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_SET(x) (((x) << MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_LSB) & MAC_PCU_AZIMUTH_TIME_STAMP_VALUE_MASK)
-
-#define MAC_PCU_MAX_CFP_DUR_ADDRESS 0x00008150
-#define MAC_PCU_MAX_CFP_DUR_OFFSET 0x00000150
-#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_MSB 7
-#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_LSB 4
-#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_MASK 0x000000f0
-#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_GET(x) (((x) & MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_MASK) >> MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_LSB)
-#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_SET(x) (((x) << MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_LSB) & MAC_PCU_MAX_CFP_DUR_USEC_FRAC_DENOMINATOR_MASK)
-#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_MSB 3
-#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_LSB 0
-#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_MASK 0x0000000f
-#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_GET(x) (((x) & MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_MASK) >> MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_LSB)
-#define MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_SET(x) (((x) << MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_LSB) & MAC_PCU_MAX_CFP_DUR_USEC_FRAC_NUMERATOR_MASK)
-
-#define MAC_PCU_HCF_TIMEOUT_ADDRESS 0x00008154
-#define MAC_PCU_HCF_TIMEOUT_OFFSET 0x00000154
-#define MAC_PCU_HCF_TIMEOUT_VALUE_MSB 15
-#define MAC_PCU_HCF_TIMEOUT_VALUE_LSB 0
-#define MAC_PCU_HCF_TIMEOUT_VALUE_MASK 0x0000ffff
-#define MAC_PCU_HCF_TIMEOUT_VALUE_GET(x) (((x) & MAC_PCU_HCF_TIMEOUT_VALUE_MASK) >> MAC_PCU_HCF_TIMEOUT_VALUE_LSB)
-#define MAC_PCU_HCF_TIMEOUT_VALUE_SET(x) (((x) << MAC_PCU_HCF_TIMEOUT_VALUE_LSB) & MAC_PCU_HCF_TIMEOUT_VALUE_MASK)
-
-#define MAC_PCU_BLUETOOTH_WEIGHTS2_ADDRESS 0x00008158
-#define MAC_PCU_BLUETOOTH_WEIGHTS2_OFFSET 0x00000158
-#define MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_MSB 31
-#define MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_LSB 16
-#define MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_MASK 0xffff0000
-#define MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_GET(x) (((x) & MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_MASK) >> MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_LSB)
-#define MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_SET(x) (((x) << MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_LSB) & MAC_PCU_BLUETOOTH_WEIGHTS2_WL_WEIGHT_CONTD_MASK)
-
-#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_ADDRESS 0x0000815c
-#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_OFFSET 0x0000015c
-#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_MSB 31
-#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_LSB 0
-#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_MASK 0xffffffff
-#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_GET(x) (((x) & MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_MASK) >> MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_LSB)
-#define MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_SET(x) (((x) << MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_LSB) & MAC_PCU_BLUETOOTH_TSF_BT_ACTIVE_VALUE_MASK)
-
-#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_ADDRESS 0x00008160
-#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_OFFSET 0x00000160
-#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_MSB 31
-#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_LSB 0
-#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_MASK 0xffffffff
-#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_GET(x) (((x) & MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_MASK) >> MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_LSB)
-#define MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_SET(x) (((x) << MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_LSB) & MAC_PCU_BLUETOOTH_TSF_BT_PRIORITY_VALUE_MASK)
-
-#define MAC_PCU_BLUETOOTH_MODE3_ADDRESS 0x00008164
-#define MAC_PCU_BLUETOOTH_MODE3_OFFSET 0x00000164
-#define MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_MSB 31
-#define MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_LSB 28
-#define MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_MASK 0xf0000000
-#define MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_MASK) >> MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_LSB)
-#define MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_LSB) & MAC_PCU_BLUETOOTH_MODE3_BT_PRIORITY_EXTEND_THRES_MASK)
-#define MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_MSB 27
-#define MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_LSB 27
-#define MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_MASK 0x08000000
-#define MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_MASK) >> MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_LSB)
-#define MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_LSB) & MAC_PCU_BLUETOOTH_MODE3_BT_TX_ON_EN_MASK)
-#define MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_MSB 26
-#define MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_LSB 25
-#define MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_MASK 0x06000000
-#define MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_MASK) >> MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_LSB)
-#define MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_LSB) & MAC_PCU_BLUETOOTH_MODE3_SLOT_SLOP_MASK)
-#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_MSB 24
-#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_LSB 24
-#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_MASK 0x01000000
-#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_MASK) >> MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_LSB)
-#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_LSB) & MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_TOGGLE_WLA_EN_MASK)
-#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_MSB 23
-#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_LSB 23
-#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_MASK 0x00800000
-#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_MASK) >> MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_LSB)
-#define MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_LSB) & MAC_PCU_BLUETOOTH_MODE3_DYNAMIC_PRI_EN_MASK)
-#define MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_MSB 22
-#define MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_LSB 22
-#define MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_MASK 0x00400000
-#define MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_MASK) >> MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_LSB)
-#define MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_LSB) & MAC_PCU_BLUETOOTH_MODE3_RFGAIN_LOCK_SRC_MASK)
-#define MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_MSB 21
-#define MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_LSB 21
-#define MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_MASK 0x00200000
-#define MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_MASK) >> MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_LSB)
-#define MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_LSB) & MAC_PCU_BLUETOOTH_MODE3_WL_PRIORITY_OFFSET_EN_MASK)
-#define MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_MSB 20
-#define MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_LSB 20
-#define MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_MASK 0x00100000
-#define MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_MASK) >> MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_LSB)
-#define MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_LSB) & MAC_PCU_BLUETOOTH_MODE3_SHARED_RX_MASK)
-#define MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_MSB 19
-#define MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_LSB 16
-#define MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_MASK 0x000f0000
-#define MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_MASK) >> MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_LSB)
-#define MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_LSB) & MAC_PCU_BLUETOOTH_MODE3_ALLOW_CONCURRENT_ACCESS_MASK)
-#define MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_MSB 15
-#define MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_LSB 8
-#define MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_MASK 0x0000ff00
-#define MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_MASK) >> MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_LSB)
-#define MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_LSB) & MAC_PCU_BLUETOOTH_MODE3_WL_QC_TIME_MASK)
-#define MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_MSB 7
-#define MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_LSB 0
-#define MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_MASK 0x000000ff
-#define MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_MASK) >> MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_LSB)
-#define MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_LSB) & MAC_PCU_BLUETOOTH_MODE3_WL_ACTIVE_TIME_MASK)
-
-#define MAC_PCU_BLUETOOTH_MODE4_ADDRESS 0x00008168
-#define MAC_PCU_BLUETOOTH_MODE4_OFFSET 0x00000168
-#define MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_MSB 31
-#define MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_LSB 16
-#define MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_MASK 0xffff0000
-#define MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_MASK) >> MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_LSB)
-#define MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_LSB) & MAC_PCU_BLUETOOTH_MODE4_BT_PRIORITY_EXTEND_MASK)
-#define MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_MSB 15
-#define MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_LSB 0
-#define MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_MASK 0x0000ffff
-#define MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_GET(x) (((x) & MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_MASK) >> MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_LSB)
-#define MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_SET(x) (((x) << MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_LSB) & MAC_PCU_BLUETOOTH_MODE4_BT_ACTIVE_EXTEND_MASK)
-
-#define MAC_PCU_BT_BT_ADDRESS 0x00008200
-#define MAC_PCU_BT_BT_OFFSET 0x00000200
-#define MAC_PCU_BT_BT_WEIGHT_MSB 31
-#define MAC_PCU_BT_BT_WEIGHT_LSB 0
-#define MAC_PCU_BT_BT_WEIGHT_MASK 0xffffffff
-#define MAC_PCU_BT_BT_WEIGHT_GET(x) (((x) & MAC_PCU_BT_BT_WEIGHT_MASK) >> MAC_PCU_BT_BT_WEIGHT_LSB)
-#define MAC_PCU_BT_BT_WEIGHT_SET(x) (((x) << MAC_PCU_BT_BT_WEIGHT_LSB) & MAC_PCU_BT_BT_WEIGHT_MASK)
-
-#define MAC_PCU_BT_BT_ASYNC_ADDRESS 0x00008300
-#define MAC_PCU_BT_BT_ASYNC_OFFSET 0x00000300
-#define MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_MSB 15
-#define MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_LSB 12
-#define MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_MASK 0x0000f000
-#define MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_GET(x) (((x) & MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_MASK) >> MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_LSB)
-#define MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_SET(x) (((x) << MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_LSB) & MAC_PCU_BT_BT_ASYNC_RXLP_WEIGHT_MASK)
-#define MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_MSB 11
-#define MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_LSB 8
-#define MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_MASK 0x00000f00
-#define MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_GET(x) (((x) & MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_MASK) >> MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_LSB)
-#define MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_SET(x) (((x) << MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_LSB) & MAC_PCU_BT_BT_ASYNC_RXHP_WEIGHT_MASK)
-#define MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_MSB 7
-#define MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_LSB 4
-#define MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_MASK 0x000000f0
-#define MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_GET(x) (((x) & MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_MASK) >> MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_LSB)
-#define MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_SET(x) (((x) << MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_LSB) & MAC_PCU_BT_BT_ASYNC_TXLP_WEIGHT_MASK)
-#define MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_MSB 3
-#define MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_LSB 0
-#define MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_MASK 0x0000000f
-#define MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_GET(x) (((x) & MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_MASK) >> MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_LSB)
-#define MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_SET(x) (((x) << MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_LSB) & MAC_PCU_BT_BT_ASYNC_TXHP_WEIGHT_MASK)
-
-#define MAC_PCU_BT_WL_1_ADDRESS 0x00008304
-#define MAC_PCU_BT_WL_1_OFFSET 0x00000304
-#define MAC_PCU_BT_WL_1_WEIGHT_MSB 31
-#define MAC_PCU_BT_WL_1_WEIGHT_LSB 0
-#define MAC_PCU_BT_WL_1_WEIGHT_MASK 0xffffffff
-#define MAC_PCU_BT_WL_1_WEIGHT_GET(x) (((x) & MAC_PCU_BT_WL_1_WEIGHT_MASK) >> MAC_PCU_BT_WL_1_WEIGHT_LSB)
-#define MAC_PCU_BT_WL_1_WEIGHT_SET(x) (((x) << MAC_PCU_BT_WL_1_WEIGHT_LSB) & MAC_PCU_BT_WL_1_WEIGHT_MASK)
-
-#define MAC_PCU_BT_WL_2_ADDRESS 0x00008308
-#define MAC_PCU_BT_WL_2_OFFSET 0x00000308
-#define MAC_PCU_BT_WL_2_WEIGHT_MSB 31
-#define MAC_PCU_BT_WL_2_WEIGHT_LSB 0
-#define MAC_PCU_BT_WL_2_WEIGHT_MASK 0xffffffff
-#define MAC_PCU_BT_WL_2_WEIGHT_GET(x) (((x) & MAC_PCU_BT_WL_2_WEIGHT_MASK) >> MAC_PCU_BT_WL_2_WEIGHT_LSB)
-#define MAC_PCU_BT_WL_2_WEIGHT_SET(x) (((x) << MAC_PCU_BT_WL_2_WEIGHT_LSB) & MAC_PCU_BT_WL_2_WEIGHT_MASK)
-
-#define MAC_PCU_BT_WL_3_ADDRESS 0x0000830c
-#define MAC_PCU_BT_WL_3_OFFSET 0x0000030c
-#define MAC_PCU_BT_WL_3_WEIGHT_MSB 31
-#define MAC_PCU_BT_WL_3_WEIGHT_LSB 0
-#define MAC_PCU_BT_WL_3_WEIGHT_MASK 0xffffffff
-#define MAC_PCU_BT_WL_3_WEIGHT_GET(x) (((x) & MAC_PCU_BT_WL_3_WEIGHT_MASK) >> MAC_PCU_BT_WL_3_WEIGHT_LSB)
-#define MAC_PCU_BT_WL_3_WEIGHT_SET(x) (((x) << MAC_PCU_BT_WL_3_WEIGHT_LSB) & MAC_PCU_BT_WL_3_WEIGHT_MASK)
-
-#define MAC_PCU_BT_WL_4_ADDRESS 0x00008310
-#define MAC_PCU_BT_WL_4_OFFSET 0x00000310
-#define MAC_PCU_BT_WL_4_WEIGHT_MSB 31
-#define MAC_PCU_BT_WL_4_WEIGHT_LSB 0
-#define MAC_PCU_BT_WL_4_WEIGHT_MASK 0xffffffff
-#define MAC_PCU_BT_WL_4_WEIGHT_GET(x) (((x) & MAC_PCU_BT_WL_4_WEIGHT_MASK) >> MAC_PCU_BT_WL_4_WEIGHT_LSB)
-#define MAC_PCU_BT_WL_4_WEIGHT_SET(x) (((x) << MAC_PCU_BT_WL_4_WEIGHT_LSB) & MAC_PCU_BT_WL_4_WEIGHT_MASK)
-
-#define MAC_PCU_COEX_EPTA_ADDRESS 0x00008314
-#define MAC_PCU_COEX_EPTA_OFFSET 0x00000314
-#define MAC_PCU_COEX_EPTA_WT_IDX_MSB 12
-#define MAC_PCU_COEX_EPTA_WT_IDX_LSB 6
-#define MAC_PCU_COEX_EPTA_WT_IDX_MASK 0x00001fc0
-#define MAC_PCU_COEX_EPTA_WT_IDX_GET(x) (((x) & MAC_PCU_COEX_EPTA_WT_IDX_MASK) >> MAC_PCU_COEX_EPTA_WT_IDX_LSB)
-#define MAC_PCU_COEX_EPTA_WT_IDX_SET(x) (((x) << MAC_PCU_COEX_EPTA_WT_IDX_LSB) & MAC_PCU_COEX_EPTA_WT_IDX_MASK)
-#define MAC_PCU_COEX_EPTA_LINKID_MSB 5
-#define MAC_PCU_COEX_EPTA_LINKID_LSB 0
-#define MAC_PCU_COEX_EPTA_LINKID_MASK 0x0000003f
-#define MAC_PCU_COEX_EPTA_LINKID_GET(x) (((x) & MAC_PCU_COEX_EPTA_LINKID_MASK) >> MAC_PCU_COEX_EPTA_LINKID_LSB)
-#define MAC_PCU_COEX_EPTA_LINKID_SET(x) (((x) << MAC_PCU_COEX_EPTA_LINKID_LSB) & MAC_PCU_COEX_EPTA_LINKID_MASK)
-
-#define MAC_PCU_COEX_LNAMAXGAIN1_ADDRESS 0x00008318
-#define MAC_PCU_COEX_LNAMAXGAIN1_OFFSET 0x00000318
-#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_MSB 31
-#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_LSB 24
-#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_MASK 0xff000000
-#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_MASK) >> MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_LSB)
-#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_LSB) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN4_MASK)
-#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_MSB 23
-#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_LSB 16
-#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_MASK 0x00ff0000
-#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_MASK) >> MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_LSB)
-#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_LSB) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN3_MASK)
-#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_MSB 15
-#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_LSB 8
-#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_MASK 0x0000ff00
-#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_MASK) >> MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_LSB)
-#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_LSB) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN2_MASK)
-#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_MSB 7
-#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_LSB 0
-#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_MASK 0x000000ff
-#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_MASK) >> MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_LSB)
-#define MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_LSB) & MAC_PCU_COEX_LNAMAXGAIN1_MAXGAIN1_MASK)
-
-#define MAC_PCU_COEX_LNAMAXGAIN2_ADDRESS 0x0000831c
-#define MAC_PCU_COEX_LNAMAXGAIN2_OFFSET 0x0000031c
-#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_MSB 31
-#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_LSB 24
-#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_MASK 0xff000000
-#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_MASK) >> MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_LSB)
-#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_LSB) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN4_MASK)
-#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_MSB 23
-#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_LSB 16
-#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_MASK 0x00ff0000
-#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_MASK) >> MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_LSB)
-#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_LSB) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN3_MASK)
-#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_MSB 15
-#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_LSB 8
-#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_MASK 0x0000ff00
-#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_MASK) >> MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_LSB)
-#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_LSB) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN2_MASK)
-#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_MSB 7
-#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_LSB 0
-#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_MASK 0x000000ff
-#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_MASK) >> MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_LSB)
-#define MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_LSB) & MAC_PCU_COEX_LNAMAXGAIN2_MAXGAIN1_MASK)
-
-#define MAC_PCU_COEX_LNAMAXGAIN3_ADDRESS 0x00008320
-#define MAC_PCU_COEX_LNAMAXGAIN3_OFFSET 0x00000320
-#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_MSB 31
-#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_LSB 24
-#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_MASK 0xff000000
-#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_MASK) >> MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_LSB)
-#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_LSB) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN4_MASK)
-#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_MSB 23
-#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_LSB 16
-#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_MASK 0x00ff0000
-#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_MASK) >> MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_LSB)
-#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_LSB) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN3_MASK)
-#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_MSB 15
-#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_LSB 8
-#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_MASK 0x0000ff00
-#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_MASK) >> MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_LSB)
-#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_LSB) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN2_MASK)
-#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_MSB 7
-#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_LSB 0
-#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_MASK 0x000000ff
-#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_MASK) >> MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_LSB)
-#define MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_LSB) & MAC_PCU_COEX_LNAMAXGAIN3_MAXGAIN1_MASK)
-
-#define MAC_PCU_COEX_LNAMAXGAIN4_ADDRESS 0x00008324
-#define MAC_PCU_COEX_LNAMAXGAIN4_OFFSET 0x00000324
-#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_MSB 31
-#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_LSB 24
-#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_MASK 0xff000000
-#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_MASK) >> MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_LSB)
-#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_LSB) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN4_MASK)
-#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_MSB 23
-#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_LSB 16
-#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_MASK 0x00ff0000
-#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_MASK) >> MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_LSB)
-#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_LSB) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN3_MASK)
-#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_MSB 15
-#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_LSB 8
-#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_MASK 0x0000ff00
-#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_MASK) >> MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_LSB)
-#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_LSB) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN2_MASK)
-#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_MSB 7
-#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_LSB 0
-#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_MASK 0x000000ff
-#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_GET(x) (((x) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_MASK) >> MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_LSB)
-#define MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_SET(x) (((x) << MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_LSB) & MAC_PCU_COEX_LNAMAXGAIN4_MAXGAIN1_MASK)
-
-#define MAC_PCU_BASIC_RATE_SET0_ADDRESS 0x00008328
-#define MAC_PCU_BASIC_RATE_SET0_OFFSET 0x00000328
-#define MAC_PCU_BASIC_RATE_SET0_VALUE_MSB 29
-#define MAC_PCU_BASIC_RATE_SET0_VALUE_LSB 0
-#define MAC_PCU_BASIC_RATE_SET0_VALUE_MASK 0x3fffffff
-#define MAC_PCU_BASIC_RATE_SET0_VALUE_GET(x) (((x) & MAC_PCU_BASIC_RATE_SET0_VALUE_MASK) >> MAC_PCU_BASIC_RATE_SET0_VALUE_LSB)
-#define MAC_PCU_BASIC_RATE_SET0_VALUE_SET(x) (((x) << MAC_PCU_BASIC_RATE_SET0_VALUE_LSB) & MAC_PCU_BASIC_RATE_SET0_VALUE_MASK)
-
-#define MAC_PCU_BASIC_RATE_SET1_ADDRESS 0x0000832c
-#define MAC_PCU_BASIC_RATE_SET1_OFFSET 0x0000032c
-#define MAC_PCU_BASIC_RATE_SET1_VALUE_MSB 29
-#define MAC_PCU_BASIC_RATE_SET1_VALUE_LSB 0
-#define MAC_PCU_BASIC_RATE_SET1_VALUE_MASK 0x3fffffff
-#define MAC_PCU_BASIC_RATE_SET1_VALUE_GET(x) (((x) & MAC_PCU_BASIC_RATE_SET1_VALUE_MASK) >> MAC_PCU_BASIC_RATE_SET1_VALUE_LSB)
-#define MAC_PCU_BASIC_RATE_SET1_VALUE_SET(x) (((x) << MAC_PCU_BASIC_RATE_SET1_VALUE_LSB) & MAC_PCU_BASIC_RATE_SET1_VALUE_MASK)
-
-#define MAC_PCU_BASIC_RATE_SET2_ADDRESS 0x00008330
-#define MAC_PCU_BASIC_RATE_SET2_OFFSET 0x00000330
-#define MAC_PCU_BASIC_RATE_SET2_VALUE_MSB 29
-#define MAC_PCU_BASIC_RATE_SET2_VALUE_LSB 0
-#define MAC_PCU_BASIC_RATE_SET2_VALUE_MASK 0x3fffffff
-#define MAC_PCU_BASIC_RATE_SET2_VALUE_GET(x) (((x) & MAC_PCU_BASIC_RATE_SET2_VALUE_MASK) >> MAC_PCU_BASIC_RATE_SET2_VALUE_LSB)
-#define MAC_PCU_BASIC_RATE_SET2_VALUE_SET(x) (((x) << MAC_PCU_BASIC_RATE_SET2_VALUE_LSB) & MAC_PCU_BASIC_RATE_SET2_VALUE_MASK)
-
-#define MAC_PCU_BASIC_RATE_SET3_ADDRESS 0x00008334
-#define MAC_PCU_BASIC_RATE_SET3_OFFSET 0x00000334
-#define MAC_PCU_BASIC_RATE_SET3_VALUE_MSB 24
-#define MAC_PCU_BASIC_RATE_SET3_VALUE_LSB 0
-#define MAC_PCU_BASIC_RATE_SET3_VALUE_MASK 0x01ffffff
-#define MAC_PCU_BASIC_RATE_SET3_VALUE_GET(x) (((x) & MAC_PCU_BASIC_RATE_SET3_VALUE_MASK) >> MAC_PCU_BASIC_RATE_SET3_VALUE_LSB)
-#define MAC_PCU_BASIC_RATE_SET3_VALUE_SET(x) (((x) << MAC_PCU_BASIC_RATE_SET3_VALUE_LSB) & MAC_PCU_BASIC_RATE_SET3_VALUE_MASK)
-
-#define MAC_PCU_RX_INT_STATUS0_ADDRESS 0x00008338
-#define MAC_PCU_RX_INT_STATUS0_OFFSET 0x00000338
-#define MAC_PCU_RX_INT_STATUS0_DURATION_H_MSB 31
-#define MAC_PCU_RX_INT_STATUS0_DURATION_H_LSB 24
-#define MAC_PCU_RX_INT_STATUS0_DURATION_H_MASK 0xff000000
-#define MAC_PCU_RX_INT_STATUS0_DURATION_H_GET(x) (((x) & MAC_PCU_RX_INT_STATUS0_DURATION_H_MASK) >> MAC_PCU_RX_INT_STATUS0_DURATION_H_LSB)
-#define MAC_PCU_RX_INT_STATUS0_DURATION_H_SET(x) (((x) << MAC_PCU_RX_INT_STATUS0_DURATION_H_LSB) & MAC_PCU_RX_INT_STATUS0_DURATION_H_MASK)
-#define MAC_PCU_RX_INT_STATUS0_DURATION_L_MSB 23
-#define MAC_PCU_RX_INT_STATUS0_DURATION_L_LSB 16
-#define MAC_PCU_RX_INT_STATUS0_DURATION_L_MASK 0x00ff0000
-#define MAC_PCU_RX_INT_STATUS0_DURATION_L_GET(x) (((x) & MAC_PCU_RX_INT_STATUS0_DURATION_L_MASK) >> MAC_PCU_RX_INT_STATUS0_DURATION_L_LSB)
-#define MAC_PCU_RX_INT_STATUS0_DURATION_L_SET(x) (((x) << MAC_PCU_RX_INT_STATUS0_DURATION_L_LSB) & MAC_PCU_RX_INT_STATUS0_DURATION_L_MASK)
-#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_MSB 15
-#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_LSB 8
-#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_MASK 0x0000ff00
-#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_GET(x) (((x) & MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_MASK) >> MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_LSB)
-#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_SET(x) (((x) << MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_LSB) & MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_H_MASK)
-#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_MSB 7
-#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_LSB 0
-#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_MASK 0x000000ff
-#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_GET(x) (((x) & MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_MASK) >> MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_LSB)
-#define MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_SET(x) (((x) << MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_LSB) & MAC_PCU_RX_INT_STATUS0_FRAME_CONTROL_L_MASK)
-
-#define MAC_PCU_RX_INT_STATUS1_ADDRESS 0x0000833c
-#define MAC_PCU_RX_INT_STATUS1_OFFSET 0x0000033c
-#define MAC_PCU_RX_INT_STATUS1_VALUE_MSB 17
-#define MAC_PCU_RX_INT_STATUS1_VALUE_LSB 0
-#define MAC_PCU_RX_INT_STATUS1_VALUE_MASK 0x0003ffff
-#define MAC_PCU_RX_INT_STATUS1_VALUE_GET(x) (((x) & MAC_PCU_RX_INT_STATUS1_VALUE_MASK) >> MAC_PCU_RX_INT_STATUS1_VALUE_LSB)
-#define MAC_PCU_RX_INT_STATUS1_VALUE_SET(x) (((x) << MAC_PCU_RX_INT_STATUS1_VALUE_LSB) & MAC_PCU_RX_INT_STATUS1_VALUE_MASK)
-
-#define MAC_PCU_RX_INT_STATUS2_ADDRESS 0x00008340
-#define MAC_PCU_RX_INT_STATUS2_OFFSET 0x00000340
-#define MAC_PCU_RX_INT_STATUS2_VALUE_MSB 26
-#define MAC_PCU_RX_INT_STATUS2_VALUE_LSB 0
-#define MAC_PCU_RX_INT_STATUS2_VALUE_MASK 0x07ffffff
-#define MAC_PCU_RX_INT_STATUS2_VALUE_GET(x) (((x) & MAC_PCU_RX_INT_STATUS2_VALUE_MASK) >> MAC_PCU_RX_INT_STATUS2_VALUE_LSB)
-#define MAC_PCU_RX_INT_STATUS2_VALUE_SET(x) (((x) << MAC_PCU_RX_INT_STATUS2_VALUE_LSB) & MAC_PCU_RX_INT_STATUS2_VALUE_MASK)
-
-#define MAC_PCU_RX_INT_STATUS3_ADDRESS 0x00008344
-#define MAC_PCU_RX_INT_STATUS3_OFFSET 0x00000344
-#define MAC_PCU_RX_INT_STATUS3_VALUE_MSB 23
-#define MAC_PCU_RX_INT_STATUS3_VALUE_LSB 0
-#define MAC_PCU_RX_INT_STATUS3_VALUE_MASK 0x00ffffff
-#define MAC_PCU_RX_INT_STATUS3_VALUE_GET(x) (((x) & MAC_PCU_RX_INT_STATUS3_VALUE_MASK) >> MAC_PCU_RX_INT_STATUS3_VALUE_LSB)
-#define MAC_PCU_RX_INT_STATUS3_VALUE_SET(x) (((x) << MAC_PCU_RX_INT_STATUS3_VALUE_LSB) & MAC_PCU_RX_INT_STATUS3_VALUE_MASK)
-
-#define HT_HALF_GI_RATE1_ADDRESS 0x00008348
-#define HT_HALF_GI_RATE1_OFFSET 0x00000348
-#define HT_HALF_GI_RATE1_MCS3_MSB 31
-#define HT_HALF_GI_RATE1_MCS3_LSB 24
-#define HT_HALF_GI_RATE1_MCS3_MASK 0xff000000
-#define HT_HALF_GI_RATE1_MCS3_GET(x) (((x) & HT_HALF_GI_RATE1_MCS3_MASK) >> HT_HALF_GI_RATE1_MCS3_LSB)
-#define HT_HALF_GI_RATE1_MCS3_SET(x) (((x) << HT_HALF_GI_RATE1_MCS3_LSB) & HT_HALF_GI_RATE1_MCS3_MASK)
-#define HT_HALF_GI_RATE1_MCS2_MSB 23
-#define HT_HALF_GI_RATE1_MCS2_LSB 16
-#define HT_HALF_GI_RATE1_MCS2_MASK 0x00ff0000
-#define HT_HALF_GI_RATE1_MCS2_GET(x) (((x) & HT_HALF_GI_RATE1_MCS2_MASK) >> HT_HALF_GI_RATE1_MCS2_LSB)
-#define HT_HALF_GI_RATE1_MCS2_SET(x) (((x) << HT_HALF_GI_RATE1_MCS2_LSB) & HT_HALF_GI_RATE1_MCS2_MASK)
-#define HT_HALF_GI_RATE1_MCS1_MSB 15
-#define HT_HALF_GI_RATE1_MCS1_LSB 8
-#define HT_HALF_GI_RATE1_MCS1_MASK 0x0000ff00
-#define HT_HALF_GI_RATE1_MCS1_GET(x) (((x) & HT_HALF_GI_RATE1_MCS1_MASK) >> HT_HALF_GI_RATE1_MCS1_LSB)
-#define HT_HALF_GI_RATE1_MCS1_SET(x) (((x) << HT_HALF_GI_RATE1_MCS1_LSB) & HT_HALF_GI_RATE1_MCS1_MASK)
-#define HT_HALF_GI_RATE1_MCS0_MSB 7
-#define HT_HALF_GI_RATE1_MCS0_LSB 0
-#define HT_HALF_GI_RATE1_MCS0_MASK 0x000000ff
-#define HT_HALF_GI_RATE1_MCS0_GET(x) (((x) & HT_HALF_GI_RATE1_MCS0_MASK) >> HT_HALF_GI_RATE1_MCS0_LSB)
-#define HT_HALF_GI_RATE1_MCS0_SET(x) (((x) << HT_HALF_GI_RATE1_MCS0_LSB) & HT_HALF_GI_RATE1_MCS0_MASK)
-
-#define HT_HALF_GI_RATE2_ADDRESS 0x0000834c
-#define HT_HALF_GI_RATE2_OFFSET 0x0000034c
-#define HT_HALF_GI_RATE2_MCS7_MSB 31
-#define HT_HALF_GI_RATE2_MCS7_LSB 24
-#define HT_HALF_GI_RATE2_MCS7_MASK 0xff000000
-#define HT_HALF_GI_RATE2_MCS7_GET(x) (((x) & HT_HALF_GI_RATE2_MCS7_MASK) >> HT_HALF_GI_RATE2_MCS7_LSB)
-#define HT_HALF_GI_RATE2_MCS7_SET(x) (((x) << HT_HALF_GI_RATE2_MCS7_LSB) & HT_HALF_GI_RATE2_MCS7_MASK)
-#define HT_HALF_GI_RATE2_MCS6_MSB 23
-#define HT_HALF_GI_RATE2_MCS6_LSB 16
-#define HT_HALF_GI_RATE2_MCS6_MASK 0x00ff0000
-#define HT_HALF_GI_RATE2_MCS6_GET(x) (((x) & HT_HALF_GI_RATE2_MCS6_MASK) >> HT_HALF_GI_RATE2_MCS6_LSB)
-#define HT_HALF_GI_RATE2_MCS6_SET(x) (((x) << HT_HALF_GI_RATE2_MCS6_LSB) & HT_HALF_GI_RATE2_MCS6_MASK)
-#define HT_HALF_GI_RATE2_MCS5_MSB 15
-#define HT_HALF_GI_RATE2_MCS5_LSB 8
-#define HT_HALF_GI_RATE2_MCS5_MASK 0x0000ff00
-#define HT_HALF_GI_RATE2_MCS5_GET(x) (((x) & HT_HALF_GI_RATE2_MCS5_MASK) >> HT_HALF_GI_RATE2_MCS5_LSB)
-#define HT_HALF_GI_RATE2_MCS5_SET(x) (((x) << HT_HALF_GI_RATE2_MCS5_LSB) & HT_HALF_GI_RATE2_MCS5_MASK)
-#define HT_HALF_GI_RATE2_MCS4_MSB 7
-#define HT_HALF_GI_RATE2_MCS4_LSB 0
-#define HT_HALF_GI_RATE2_MCS4_MASK 0x000000ff
-#define HT_HALF_GI_RATE2_MCS4_GET(x) (((x) & HT_HALF_GI_RATE2_MCS4_MASK) >> HT_HALF_GI_RATE2_MCS4_LSB)
-#define HT_HALF_GI_RATE2_MCS4_SET(x) (((x) << HT_HALF_GI_RATE2_MCS4_LSB) & HT_HALF_GI_RATE2_MCS4_MASK)
-
-#define HT_FULL_GI_RATE1_ADDRESS 0x00008350
-#define HT_FULL_GI_RATE1_OFFSET 0x00000350
-#define HT_FULL_GI_RATE1_MCS3_MSB 31
-#define HT_FULL_GI_RATE1_MCS3_LSB 24
-#define HT_FULL_GI_RATE1_MCS3_MASK 0xff000000
-#define HT_FULL_GI_RATE1_MCS3_GET(x) (((x) & HT_FULL_GI_RATE1_MCS3_MASK) >> HT_FULL_GI_RATE1_MCS3_LSB)
-#define HT_FULL_GI_RATE1_MCS3_SET(x) (((x) << HT_FULL_GI_RATE1_MCS3_LSB) & HT_FULL_GI_RATE1_MCS3_MASK)
-#define HT_FULL_GI_RATE1_MCS2_MSB 23
-#define HT_FULL_GI_RATE1_MCS2_LSB 16
-#define HT_FULL_GI_RATE1_MCS2_MASK 0x00ff0000
-#define HT_FULL_GI_RATE1_MCS2_GET(x) (((x) & HT_FULL_GI_RATE1_MCS2_MASK) >> HT_FULL_GI_RATE1_MCS2_LSB)
-#define HT_FULL_GI_RATE1_MCS2_SET(x) (((x) << HT_FULL_GI_RATE1_MCS2_LSB) & HT_FULL_GI_RATE1_MCS2_MASK)
-#define HT_FULL_GI_RATE1_MCS1_MSB 15
-#define HT_FULL_GI_RATE1_MCS1_LSB 8
-#define HT_FULL_GI_RATE1_MCS1_MASK 0x0000ff00
-#define HT_FULL_GI_RATE1_MCS1_GET(x) (((x) & HT_FULL_GI_RATE1_MCS1_MASK) >> HT_FULL_GI_RATE1_MCS1_LSB)
-#define HT_FULL_GI_RATE1_MCS1_SET(x) (((x) << HT_FULL_GI_RATE1_MCS1_LSB) & HT_FULL_GI_RATE1_MCS1_MASK)
-#define HT_FULL_GI_RATE1_MCS0_MSB 7
-#define HT_FULL_GI_RATE1_MCS0_LSB 0
-#define HT_FULL_GI_RATE1_MCS0_MASK 0x000000ff
-#define HT_FULL_GI_RATE1_MCS0_GET(x) (((x) & HT_FULL_GI_RATE1_MCS0_MASK) >> HT_FULL_GI_RATE1_MCS0_LSB)
-#define HT_FULL_GI_RATE1_MCS0_SET(x) (((x) << HT_FULL_GI_RATE1_MCS0_LSB) & HT_FULL_GI_RATE1_MCS0_MASK)
-
-#define HT_FULL_GI_RATE2_ADDRESS 0x00008354
-#define HT_FULL_GI_RATE2_OFFSET 0x00000354
-#define HT_FULL_GI_RATE2_MCS7_MSB 31
-#define HT_FULL_GI_RATE2_MCS7_LSB 24
-#define HT_FULL_GI_RATE2_MCS7_MASK 0xff000000
-#define HT_FULL_GI_RATE2_MCS7_GET(x) (((x) & HT_FULL_GI_RATE2_MCS7_MASK) >> HT_FULL_GI_RATE2_MCS7_LSB)
-#define HT_FULL_GI_RATE2_MCS7_SET(x) (((x) << HT_FULL_GI_RATE2_MCS7_LSB) & HT_FULL_GI_RATE2_MCS7_MASK)
-#define HT_FULL_GI_RATE2_MCS6_MSB 23
-#define HT_FULL_GI_RATE2_MCS6_LSB 16
-#define HT_FULL_GI_RATE2_MCS6_MASK 0x00ff0000
-#define HT_FULL_GI_RATE2_MCS6_GET(x) (((x) & HT_FULL_GI_RATE2_MCS6_MASK) >> HT_FULL_GI_RATE2_MCS6_LSB)
-#define HT_FULL_GI_RATE2_MCS6_SET(x) (((x) << HT_FULL_GI_RATE2_MCS6_LSB) & HT_FULL_GI_RATE2_MCS6_MASK)
-#define HT_FULL_GI_RATE2_MCS5_MSB 15
-#define HT_FULL_GI_RATE2_MCS5_LSB 8
-#define HT_FULL_GI_RATE2_MCS5_MASK 0x0000ff00
-#define HT_FULL_GI_RATE2_MCS5_GET(x) (((x) & HT_FULL_GI_RATE2_MCS5_MASK) >> HT_FULL_GI_RATE2_MCS5_LSB)
-#define HT_FULL_GI_RATE2_MCS5_SET(x) (((x) << HT_FULL_GI_RATE2_MCS5_LSB) & HT_FULL_GI_RATE2_MCS5_MASK)
-#define HT_FULL_GI_RATE2_MCS4_MSB 7
-#define HT_FULL_GI_RATE2_MCS4_LSB 0
-#define HT_FULL_GI_RATE2_MCS4_MASK 0x000000ff
-#define HT_FULL_GI_RATE2_MCS4_GET(x) (((x) & HT_FULL_GI_RATE2_MCS4_MASK) >> HT_FULL_GI_RATE2_MCS4_LSB)
-#define HT_FULL_GI_RATE2_MCS4_SET(x) (((x) << HT_FULL_GI_RATE2_MCS4_LSB) & HT_FULL_GI_RATE2_MCS4_MASK)
-
-#define LEGACY_RATE1_ADDRESS 0x00008358
-#define LEGACY_RATE1_OFFSET 0x00000358
-#define LEGACY_RATE1_RATE12_MSB 29
-#define LEGACY_RATE1_RATE12_LSB 24
-#define LEGACY_RATE1_RATE12_MASK 0x3f000000
-#define LEGACY_RATE1_RATE12_GET(x) (((x) & LEGACY_RATE1_RATE12_MASK) >> LEGACY_RATE1_RATE12_LSB)
-#define LEGACY_RATE1_RATE12_SET(x) (((x) << LEGACY_RATE1_RATE12_LSB) & LEGACY_RATE1_RATE12_MASK)
-#define LEGACY_RATE1_RATE11_MSB 23
-#define LEGACY_RATE1_RATE11_LSB 18
-#define LEGACY_RATE1_RATE11_MASK 0x00fc0000
-#define LEGACY_RATE1_RATE11_GET(x) (((x) & LEGACY_RATE1_RATE11_MASK) >> LEGACY_RATE1_RATE11_LSB)
-#define LEGACY_RATE1_RATE11_SET(x) (((x) << LEGACY_RATE1_RATE11_LSB) & LEGACY_RATE1_RATE11_MASK)
-#define LEGACY_RATE1_RATE10_MSB 17
-#define LEGACY_RATE1_RATE10_LSB 12
-#define LEGACY_RATE1_RATE10_MASK 0x0003f000
-#define LEGACY_RATE1_RATE10_GET(x) (((x) & LEGACY_RATE1_RATE10_MASK) >> LEGACY_RATE1_RATE10_LSB)
-#define LEGACY_RATE1_RATE10_SET(x) (((x) << LEGACY_RATE1_RATE10_LSB) & LEGACY_RATE1_RATE10_MASK)
-#define LEGACY_RATE1_RATE9_MSB 11
-#define LEGACY_RATE1_RATE9_LSB 6
-#define LEGACY_RATE1_RATE9_MASK 0x00000fc0
-#define LEGACY_RATE1_RATE9_GET(x) (((x) & LEGACY_RATE1_RATE9_MASK) >> LEGACY_RATE1_RATE9_LSB)
-#define LEGACY_RATE1_RATE9_SET(x) (((x) << LEGACY_RATE1_RATE9_LSB) & LEGACY_RATE1_RATE9_MASK)
-#define LEGACY_RATE1_RATE8_MSB 5
-#define LEGACY_RATE1_RATE8_LSB 0
-#define LEGACY_RATE1_RATE8_MASK 0x0000003f
-#define LEGACY_RATE1_RATE8_GET(x) (((x) & LEGACY_RATE1_RATE8_MASK) >> LEGACY_RATE1_RATE8_LSB)
-#define LEGACY_RATE1_RATE8_SET(x) (((x) << LEGACY_RATE1_RATE8_LSB) & LEGACY_RATE1_RATE8_MASK)
-
-#define LEGACY_RATE2_ADDRESS 0x0000835c
-#define LEGACY_RATE2_OFFSET 0x0000035c
-#define LEGACY_RATE2_RATE25_MSB 29
-#define LEGACY_RATE2_RATE25_LSB 24
-#define LEGACY_RATE2_RATE25_MASK 0x3f000000
-#define LEGACY_RATE2_RATE25_GET(x) (((x) & LEGACY_RATE2_RATE25_MASK) >> LEGACY_RATE2_RATE25_LSB)
-#define LEGACY_RATE2_RATE25_SET(x) (((x) << LEGACY_RATE2_RATE25_LSB) & LEGACY_RATE2_RATE25_MASK)
-#define LEGACY_RATE2_RATE24_MSB 23
-#define LEGACY_RATE2_RATE24_LSB 18
-#define LEGACY_RATE2_RATE24_MASK 0x00fc0000
-#define LEGACY_RATE2_RATE24_GET(x) (((x) & LEGACY_RATE2_RATE24_MASK) >> LEGACY_RATE2_RATE24_LSB)
-#define LEGACY_RATE2_RATE24_SET(x) (((x) << LEGACY_RATE2_RATE24_LSB) & LEGACY_RATE2_RATE24_MASK)
-#define LEGACY_RATE2_RATE15_MSB 17
-#define LEGACY_RATE2_RATE15_LSB 12
-#define LEGACY_RATE2_RATE15_MASK 0x0003f000
-#define LEGACY_RATE2_RATE15_GET(x) (((x) & LEGACY_RATE2_RATE15_MASK) >> LEGACY_RATE2_RATE15_LSB)
-#define LEGACY_RATE2_RATE15_SET(x) (((x) << LEGACY_RATE2_RATE15_LSB) & LEGACY_RATE2_RATE15_MASK)
-#define LEGACY_RATE2_RATE14_MSB 11
-#define LEGACY_RATE2_RATE14_LSB 6
-#define LEGACY_RATE2_RATE14_MASK 0x00000fc0
-#define LEGACY_RATE2_RATE14_GET(x) (((x) & LEGACY_RATE2_RATE14_MASK) >> LEGACY_RATE2_RATE14_LSB)
-#define LEGACY_RATE2_RATE14_SET(x) (((x) << LEGACY_RATE2_RATE14_LSB) & LEGACY_RATE2_RATE14_MASK)
-#define LEGACY_RATE2_RATE13_MSB 5
-#define LEGACY_RATE2_RATE13_LSB 0
-#define LEGACY_RATE2_RATE13_MASK 0x0000003f
-#define LEGACY_RATE2_RATE13_GET(x) (((x) & LEGACY_RATE2_RATE13_MASK) >> LEGACY_RATE2_RATE13_LSB)
-#define LEGACY_RATE2_RATE13_SET(x) (((x) << LEGACY_RATE2_RATE13_LSB) & LEGACY_RATE2_RATE13_MASK)
-
-#define LEGACY_RATE3_ADDRESS 0x00008360
-#define LEGACY_RATE3_OFFSET 0x00000360
-#define LEGACY_RATE3_RATE30_MSB 29
-#define LEGACY_RATE3_RATE30_LSB 24
-#define LEGACY_RATE3_RATE30_MASK 0x3f000000
-#define LEGACY_RATE3_RATE30_GET(x) (((x) & LEGACY_RATE3_RATE30_MASK) >> LEGACY_RATE3_RATE30_LSB)
-#define LEGACY_RATE3_RATE30_SET(x) (((x) << LEGACY_RATE3_RATE30_LSB) & LEGACY_RATE3_RATE30_MASK)
-#define LEGACY_RATE3_RATE29_MSB 23
-#define LEGACY_RATE3_RATE29_LSB 18
-#define LEGACY_RATE3_RATE29_MASK 0x00fc0000
-#define LEGACY_RATE3_RATE29_GET(x) (((x) & LEGACY_RATE3_RATE29_MASK) >> LEGACY_RATE3_RATE29_LSB)
-#define LEGACY_RATE3_RATE29_SET(x) (((x) << LEGACY_RATE3_RATE29_LSB) & LEGACY_RATE3_RATE29_MASK)
-#define LEGACY_RATE3_RATE28_MSB 17
-#define LEGACY_RATE3_RATE28_LSB 12
-#define LEGACY_RATE3_RATE28_MASK 0x0003f000
-#define LEGACY_RATE3_RATE28_GET(x) (((x) & LEGACY_RATE3_RATE28_MASK) >> LEGACY_RATE3_RATE28_LSB)
-#define LEGACY_RATE3_RATE28_SET(x) (((x) << LEGACY_RATE3_RATE28_LSB) & LEGACY_RATE3_RATE28_MASK)
-#define LEGACY_RATE3_RATE27_MSB 11
-#define LEGACY_RATE3_RATE27_LSB 6
-#define LEGACY_RATE3_RATE27_MASK 0x00000fc0
-#define LEGACY_RATE3_RATE27_GET(x) (((x) & LEGACY_RATE3_RATE27_MASK) >> LEGACY_RATE3_RATE27_LSB)
-#define LEGACY_RATE3_RATE27_SET(x) (((x) << LEGACY_RATE3_RATE27_LSB) & LEGACY_RATE3_RATE27_MASK)
-#define LEGACY_RATE3_RATE26_MSB 5
-#define LEGACY_RATE3_RATE26_LSB 0
-#define LEGACY_RATE3_RATE26_MASK 0x0000003f
-#define LEGACY_RATE3_RATE26_GET(x) (((x) & LEGACY_RATE3_RATE26_MASK) >> LEGACY_RATE3_RATE26_LSB)
-#define LEGACY_RATE3_RATE26_SET(x) (((x) << LEGACY_RATE3_RATE26_LSB) & LEGACY_RATE3_RATE26_MASK)
-
-#define RX_INT_FILTER_ADDRESS 0x00008364
-#define RX_INT_FILTER_OFFSET 0x00000364
-#define RX_INT_FILTER_BEACON_MSB 17
-#define RX_INT_FILTER_BEACON_LSB 17
-#define RX_INT_FILTER_BEACON_MASK 0x00020000
-#define RX_INT_FILTER_BEACON_GET(x) (((x) & RX_INT_FILTER_BEACON_MASK) >> RX_INT_FILTER_BEACON_LSB)
-#define RX_INT_FILTER_BEACON_SET(x) (((x) << RX_INT_FILTER_BEACON_LSB) & RX_INT_FILTER_BEACON_MASK)
-#define RX_INT_FILTER_AMPDU_MSB 16
-#define RX_INT_FILTER_AMPDU_LSB 16
-#define RX_INT_FILTER_AMPDU_MASK 0x00010000
-#define RX_INT_FILTER_AMPDU_GET(x) (((x) & RX_INT_FILTER_AMPDU_MASK) >> RX_INT_FILTER_AMPDU_LSB)
-#define RX_INT_FILTER_AMPDU_SET(x) (((x) << RX_INT_FILTER_AMPDU_LSB) & RX_INT_FILTER_AMPDU_MASK)
-#define RX_INT_FILTER_EOSP_MSB 15
-#define RX_INT_FILTER_EOSP_LSB 15
-#define RX_INT_FILTER_EOSP_MASK 0x00008000
-#define RX_INT_FILTER_EOSP_GET(x) (((x) & RX_INT_FILTER_EOSP_MASK) >> RX_INT_FILTER_EOSP_LSB)
-#define RX_INT_FILTER_EOSP_SET(x) (((x) << RX_INT_FILTER_EOSP_LSB) & RX_INT_FILTER_EOSP_MASK)
-#define RX_INT_FILTER_LENGTH_LOW_MSB 14
-#define RX_INT_FILTER_LENGTH_LOW_LSB 14
-#define RX_INT_FILTER_LENGTH_LOW_MASK 0x00004000
-#define RX_INT_FILTER_LENGTH_LOW_GET(x) (((x) & RX_INT_FILTER_LENGTH_LOW_MASK) >> RX_INT_FILTER_LENGTH_LOW_LSB)
-#define RX_INT_FILTER_LENGTH_LOW_SET(x) (((x) << RX_INT_FILTER_LENGTH_LOW_LSB) & RX_INT_FILTER_LENGTH_LOW_MASK)
-#define RX_INT_FILTER_LENGTH_HIGH_MSB 13
-#define RX_INT_FILTER_LENGTH_HIGH_LSB 13
-#define RX_INT_FILTER_LENGTH_HIGH_MASK 0x00002000
-#define RX_INT_FILTER_LENGTH_HIGH_GET(x) (((x) & RX_INT_FILTER_LENGTH_HIGH_MASK) >> RX_INT_FILTER_LENGTH_HIGH_LSB)
-#define RX_INT_FILTER_LENGTH_HIGH_SET(x) (((x) << RX_INT_FILTER_LENGTH_HIGH_LSB) & RX_INT_FILTER_LENGTH_HIGH_MASK)
-#define RX_INT_FILTER_RSSI_MSB 12
-#define RX_INT_FILTER_RSSI_LSB 12
-#define RX_INT_FILTER_RSSI_MASK 0x00001000
-#define RX_INT_FILTER_RSSI_GET(x) (((x) & RX_INT_FILTER_RSSI_MASK) >> RX_INT_FILTER_RSSI_LSB)
-#define RX_INT_FILTER_RSSI_SET(x) (((x) << RX_INT_FILTER_RSSI_LSB) & RX_INT_FILTER_RSSI_MASK)
-#define RX_INT_FILTER_RATE_LOW_MSB 11
-#define RX_INT_FILTER_RATE_LOW_LSB 11
-#define RX_INT_FILTER_RATE_LOW_MASK 0x00000800
-#define RX_INT_FILTER_RATE_LOW_GET(x) (((x) & RX_INT_FILTER_RATE_LOW_MASK) >> RX_INT_FILTER_RATE_LOW_LSB)
-#define RX_INT_FILTER_RATE_LOW_SET(x) (((x) << RX_INT_FILTER_RATE_LOW_LSB) & RX_INT_FILTER_RATE_LOW_MASK)
-#define RX_INT_FILTER_RATE_HIGH_MSB 10
-#define RX_INT_FILTER_RATE_HIGH_LSB 10
-#define RX_INT_FILTER_RATE_HIGH_MASK 0x00000400
-#define RX_INT_FILTER_RATE_HIGH_GET(x) (((x) & RX_INT_FILTER_RATE_HIGH_MASK) >> RX_INT_FILTER_RATE_HIGH_LSB)
-#define RX_INT_FILTER_RATE_HIGH_SET(x) (((x) << RX_INT_FILTER_RATE_HIGH_LSB) & RX_INT_FILTER_RATE_HIGH_MASK)
-#define RX_INT_FILTER_MORE_FRAG_MSB 9
-#define RX_INT_FILTER_MORE_FRAG_LSB 9
-#define RX_INT_FILTER_MORE_FRAG_MASK 0x00000200
-#define RX_INT_FILTER_MORE_FRAG_GET(x) (((x) & RX_INT_FILTER_MORE_FRAG_MASK) >> RX_INT_FILTER_MORE_FRAG_LSB)
-#define RX_INT_FILTER_MORE_FRAG_SET(x) (((x) << RX_INT_FILTER_MORE_FRAG_LSB) & RX_INT_FILTER_MORE_FRAG_MASK)
-#define RX_INT_FILTER_MORE_DATA_MSB 8
-#define RX_INT_FILTER_MORE_DATA_LSB 8
-#define RX_INT_FILTER_MORE_DATA_MASK 0x00000100
-#define RX_INT_FILTER_MORE_DATA_GET(x) (((x) & RX_INT_FILTER_MORE_DATA_MASK) >> RX_INT_FILTER_MORE_DATA_LSB)
-#define RX_INT_FILTER_MORE_DATA_SET(x) (((x) << RX_INT_FILTER_MORE_DATA_LSB) & RX_INT_FILTER_MORE_DATA_MASK)
-#define RX_INT_FILTER_RETRY_MSB 7
-#define RX_INT_FILTER_RETRY_LSB 7
-#define RX_INT_FILTER_RETRY_MASK 0x00000080
-#define RX_INT_FILTER_RETRY_GET(x) (((x) & RX_INT_FILTER_RETRY_MASK) >> RX_INT_FILTER_RETRY_LSB)
-#define RX_INT_FILTER_RETRY_SET(x) (((x) << RX_INT_FILTER_RETRY_LSB) & RX_INT_FILTER_RETRY_MASK)
-#define RX_INT_FILTER_CTS_MSB 6
-#define RX_INT_FILTER_CTS_LSB 6
-#define RX_INT_FILTER_CTS_MASK 0x00000040
-#define RX_INT_FILTER_CTS_GET(x) (((x) & RX_INT_FILTER_CTS_MASK) >> RX_INT_FILTER_CTS_LSB)
-#define RX_INT_FILTER_CTS_SET(x) (((x) << RX_INT_FILTER_CTS_LSB) & RX_INT_FILTER_CTS_MASK)
-#define RX_INT_FILTER_ACK_MSB 5
-#define RX_INT_FILTER_ACK_LSB 5
-#define RX_INT_FILTER_ACK_MASK 0x00000020
-#define RX_INT_FILTER_ACK_GET(x) (((x) & RX_INT_FILTER_ACK_MASK) >> RX_INT_FILTER_ACK_LSB)
-#define RX_INT_FILTER_ACK_SET(x) (((x) << RX_INT_FILTER_ACK_LSB) & RX_INT_FILTER_ACK_MASK)
-#define RX_INT_FILTER_RTS_MSB 4
-#define RX_INT_FILTER_RTS_LSB 4
-#define RX_INT_FILTER_RTS_MASK 0x00000010
-#define RX_INT_FILTER_RTS_GET(x) (((x) & RX_INT_FILTER_RTS_MASK) >> RX_INT_FILTER_RTS_LSB)
-#define RX_INT_FILTER_RTS_SET(x) (((x) << RX_INT_FILTER_RTS_LSB) & RX_INT_FILTER_RTS_MASK)
-#define RX_INT_FILTER_MCAST_MSB 3
-#define RX_INT_FILTER_MCAST_LSB 3
-#define RX_INT_FILTER_MCAST_MASK 0x00000008
-#define RX_INT_FILTER_MCAST_GET(x) (((x) & RX_INT_FILTER_MCAST_MASK) >> RX_INT_FILTER_MCAST_LSB)
-#define RX_INT_FILTER_MCAST_SET(x) (((x) << RX_INT_FILTER_MCAST_LSB) & RX_INT_FILTER_MCAST_MASK)
-#define RX_INT_FILTER_BCAST_MSB 2
-#define RX_INT_FILTER_BCAST_LSB 2
-#define RX_INT_FILTER_BCAST_MASK 0x00000004
-#define RX_INT_FILTER_BCAST_GET(x) (((x) & RX_INT_FILTER_BCAST_MASK) >> RX_INT_FILTER_BCAST_LSB)
-#define RX_INT_FILTER_BCAST_SET(x) (((x) << RX_INT_FILTER_BCAST_LSB) & RX_INT_FILTER_BCAST_MASK)
-#define RX_INT_FILTER_DIRECTED_MSB 1
-#define RX_INT_FILTER_DIRECTED_LSB 1
-#define RX_INT_FILTER_DIRECTED_MASK 0x00000002
-#define RX_INT_FILTER_DIRECTED_GET(x) (((x) & RX_INT_FILTER_DIRECTED_MASK) >> RX_INT_FILTER_DIRECTED_LSB)
-#define RX_INT_FILTER_DIRECTED_SET(x) (((x) << RX_INT_FILTER_DIRECTED_LSB) & RX_INT_FILTER_DIRECTED_MASK)
-#define RX_INT_FILTER_ENABLE_MSB 0
-#define RX_INT_FILTER_ENABLE_LSB 0
-#define RX_INT_FILTER_ENABLE_MASK 0x00000001
-#define RX_INT_FILTER_ENABLE_GET(x) (((x) & RX_INT_FILTER_ENABLE_MASK) >> RX_INT_FILTER_ENABLE_LSB)
-#define RX_INT_FILTER_ENABLE_SET(x) (((x) << RX_INT_FILTER_ENABLE_LSB) & RX_INT_FILTER_ENABLE_MASK)
-
-#define RX_INT_OVERFLOW_ADDRESS 0x00008368
-#define RX_INT_OVERFLOW_OFFSET 0x00000368
-#define RX_INT_OVERFLOW_STATUS_MSB 0
-#define RX_INT_OVERFLOW_STATUS_LSB 0
-#define RX_INT_OVERFLOW_STATUS_MASK 0x00000001
-#define RX_INT_OVERFLOW_STATUS_GET(x) (((x) & RX_INT_OVERFLOW_STATUS_MASK) >> RX_INT_OVERFLOW_STATUS_LSB)
-#define RX_INT_OVERFLOW_STATUS_SET(x) (((x) << RX_INT_OVERFLOW_STATUS_LSB) & RX_INT_OVERFLOW_STATUS_MASK)
-
-#define RX_FILTER_THRESH_ADDRESS 0x0000836c
-#define RX_FILTER_THRESH_OFFSET 0x0000036c
-#define RX_FILTER_THRESH_RSSI_LOW_MSB 23
-#define RX_FILTER_THRESH_RSSI_LOW_LSB 16
-#define RX_FILTER_THRESH_RSSI_LOW_MASK 0x00ff0000
-#define RX_FILTER_THRESH_RSSI_LOW_GET(x) (((x) & RX_FILTER_THRESH_RSSI_LOW_MASK) >> RX_FILTER_THRESH_RSSI_LOW_LSB)
-#define RX_FILTER_THRESH_RSSI_LOW_SET(x) (((x) << RX_FILTER_THRESH_RSSI_LOW_LSB) & RX_FILTER_THRESH_RSSI_LOW_MASK)
-#define RX_FILTER_THRESH_RATE_LOW_MSB 15
-#define RX_FILTER_THRESH_RATE_LOW_LSB 8
-#define RX_FILTER_THRESH_RATE_LOW_MASK 0x0000ff00
-#define RX_FILTER_THRESH_RATE_LOW_GET(x) (((x) & RX_FILTER_THRESH_RATE_LOW_MASK) >> RX_FILTER_THRESH_RATE_LOW_LSB)
-#define RX_FILTER_THRESH_RATE_LOW_SET(x) (((x) << RX_FILTER_THRESH_RATE_LOW_LSB) & RX_FILTER_THRESH_RATE_LOW_MASK)
-#define RX_FILTER_THRESH_RATE_HIGH_MSB 7
-#define RX_FILTER_THRESH_RATE_HIGH_LSB 0
-#define RX_FILTER_THRESH_RATE_HIGH_MASK 0x000000ff
-#define RX_FILTER_THRESH_RATE_HIGH_GET(x) (((x) & RX_FILTER_THRESH_RATE_HIGH_MASK) >> RX_FILTER_THRESH_RATE_HIGH_LSB)
-#define RX_FILTER_THRESH_RATE_HIGH_SET(x) (((x) << RX_FILTER_THRESH_RATE_HIGH_LSB) & RX_FILTER_THRESH_RATE_HIGH_MASK)
-
-#define RX_FILTER_THRESH1_ADDRESS 0x00008370
-#define RX_FILTER_THRESH1_OFFSET 0x00000370
-#define RX_FILTER_THRESH1_LENGTH_LOW_MSB 23
-#define RX_FILTER_THRESH1_LENGTH_LOW_LSB 12
-#define RX_FILTER_THRESH1_LENGTH_LOW_MASK 0x00fff000
-#define RX_FILTER_THRESH1_LENGTH_LOW_GET(x) (((x) & RX_FILTER_THRESH1_LENGTH_LOW_MASK) >> RX_FILTER_THRESH1_LENGTH_LOW_LSB)
-#define RX_FILTER_THRESH1_LENGTH_LOW_SET(x) (((x) << RX_FILTER_THRESH1_LENGTH_LOW_LSB) & RX_FILTER_THRESH1_LENGTH_LOW_MASK)
-#define RX_FILTER_THRESH1_LENGTH_HIGH_MSB 11
-#define RX_FILTER_THRESH1_LENGTH_HIGH_LSB 0
-#define RX_FILTER_THRESH1_LENGTH_HIGH_MASK 0x00000fff
-#define RX_FILTER_THRESH1_LENGTH_HIGH_GET(x) (((x) & RX_FILTER_THRESH1_LENGTH_HIGH_MASK) >> RX_FILTER_THRESH1_LENGTH_HIGH_LSB)
-#define RX_FILTER_THRESH1_LENGTH_HIGH_SET(x) (((x) << RX_FILTER_THRESH1_LENGTH_HIGH_LSB) & RX_FILTER_THRESH1_LENGTH_HIGH_MASK)
-
-#define RX_PRIORITY_THRESH0_ADDRESS 0x00008374
-#define RX_PRIORITY_THRESH0_OFFSET 0x00000374
-#define RX_PRIORITY_THRESH0_RSSI_LOW_MSB 31
-#define RX_PRIORITY_THRESH0_RSSI_LOW_LSB 24
-#define RX_PRIORITY_THRESH0_RSSI_LOW_MASK 0xff000000
-#define RX_PRIORITY_THRESH0_RSSI_LOW_GET(x) (((x) & RX_PRIORITY_THRESH0_RSSI_LOW_MASK) >> RX_PRIORITY_THRESH0_RSSI_LOW_LSB)
-#define RX_PRIORITY_THRESH0_RSSI_LOW_SET(x) (((x) << RX_PRIORITY_THRESH0_RSSI_LOW_LSB) & RX_PRIORITY_THRESH0_RSSI_LOW_MASK)
-#define RX_PRIORITY_THRESH0_RSSI_HIGH_MSB 23
-#define RX_PRIORITY_THRESH0_RSSI_HIGH_LSB 16
-#define RX_PRIORITY_THRESH0_RSSI_HIGH_MASK 0x00ff0000
-#define RX_PRIORITY_THRESH0_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH0_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH0_RSSI_HIGH_LSB)
-#define RX_PRIORITY_THRESH0_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH0_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH0_RSSI_HIGH_MASK)
-#define RX_PRIORITY_THRESH0_RATE_LOW_MSB 15
-#define RX_PRIORITY_THRESH0_RATE_LOW_LSB 8
-#define RX_PRIORITY_THRESH0_RATE_LOW_MASK 0x0000ff00
-#define RX_PRIORITY_THRESH0_RATE_LOW_GET(x) (((x) & RX_PRIORITY_THRESH0_RATE_LOW_MASK) >> RX_PRIORITY_THRESH0_RATE_LOW_LSB)
-#define RX_PRIORITY_THRESH0_RATE_LOW_SET(x) (((x) << RX_PRIORITY_THRESH0_RATE_LOW_LSB) & RX_PRIORITY_THRESH0_RATE_LOW_MASK)
-#define RX_PRIORITY_THRESH0_RATE_HIGH_MSB 7
-#define RX_PRIORITY_THRESH0_RATE_HIGH_LSB 0
-#define RX_PRIORITY_THRESH0_RATE_HIGH_MASK 0x000000ff
-#define RX_PRIORITY_THRESH0_RATE_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH0_RATE_HIGH_MASK) >> RX_PRIORITY_THRESH0_RATE_HIGH_LSB)
-#define RX_PRIORITY_THRESH0_RATE_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH0_RATE_HIGH_LSB) & RX_PRIORITY_THRESH0_RATE_HIGH_MASK)
-
-#define RX_PRIORITY_THRESH1_ADDRESS 0x00008378
-#define RX_PRIORITY_THRESH1_OFFSET 0x00000378
-#define RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_MSB 31
-#define RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_LSB 24
-#define RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_MASK 0xff000000
-#define RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_LSB)
-#define RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH1_XCAST_RSSI_HIGH_MASK)
-#define RX_PRIORITY_THRESH1_LENGTH_LOW_MSB 23
-#define RX_PRIORITY_THRESH1_LENGTH_LOW_LSB 12
-#define RX_PRIORITY_THRESH1_LENGTH_LOW_MASK 0x00fff000
-#define RX_PRIORITY_THRESH1_LENGTH_LOW_GET(x) (((x) & RX_PRIORITY_THRESH1_LENGTH_LOW_MASK) >> RX_PRIORITY_THRESH1_LENGTH_LOW_LSB)
-#define RX_PRIORITY_THRESH1_LENGTH_LOW_SET(x) (((x) << RX_PRIORITY_THRESH1_LENGTH_LOW_LSB) & RX_PRIORITY_THRESH1_LENGTH_LOW_MASK)
-#define RX_PRIORITY_THRESH1_LENGTH_HIGH_MSB 11
-#define RX_PRIORITY_THRESH1_LENGTH_HIGH_LSB 0
-#define RX_PRIORITY_THRESH1_LENGTH_HIGH_MASK 0x00000fff
-#define RX_PRIORITY_THRESH1_LENGTH_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH1_LENGTH_HIGH_MASK) >> RX_PRIORITY_THRESH1_LENGTH_HIGH_LSB)
-#define RX_PRIORITY_THRESH1_LENGTH_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH1_LENGTH_HIGH_LSB) & RX_PRIORITY_THRESH1_LENGTH_HIGH_MASK)
-
-#define RX_PRIORITY_THRESH2_ADDRESS 0x0000837c
-#define RX_PRIORITY_THRESH2_OFFSET 0x0000037c
-#define RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_MSB 31
-#define RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_LSB 24
-#define RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_MASK 0xff000000
-#define RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_LSB)
-#define RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH2_NULL_RSSI_HIGH_MASK)
-#define RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_MSB 23
-#define RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_LSB 16
-#define RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_MASK 0x00ff0000
-#define RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_LSB)
-#define RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH2_BEACON_RSSI_HIGH_MASK)
-#define RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_MSB 15
-#define RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_LSB 8
-#define RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_MASK 0x0000ff00
-#define RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_LSB)
-#define RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH2_MGMT_RSSI_HIGH_MASK)
-#define RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_MSB 7
-#define RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_LSB 0
-#define RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_MASK 0x000000ff
-#define RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_LSB)
-#define RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH2_PRESP_RSSI_HIGH_MASK)
-
-#define RX_PRIORITY_THRESH3_ADDRESS 0x00008380
-#define RX_PRIORITY_THRESH3_OFFSET 0x00000380
-#define RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_MSB 15
-#define RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_LSB 8
-#define RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_MASK 0x0000ff00
-#define RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_LSB)
-#define RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH3_PS_POLL_RSSI_HIGH_MASK)
-#define RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_MSB 7
-#define RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_LSB 0
-#define RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_MASK 0x000000ff
-#define RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_MASK) >> RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_LSB)
-#define RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_LSB) & RX_PRIORITY_THRESH3_PREQ_RSSI_HIGH_MASK)
-
-#define RX_PRIORITY_OFFSET0_ADDRESS 0x00008384
-#define RX_PRIORITY_OFFSET0_OFFSET 0x00000384
-#define RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_MSB 29
-#define RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_LSB 24
-#define RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_MASK 0x3f000000
-#define RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_LSB)
-#define RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET0_XCAST_RSSI_HIGH_MASK)
-#define RX_PRIORITY_OFFSET0_RSSI_LOW_MSB 23
-#define RX_PRIORITY_OFFSET0_RSSI_LOW_LSB 18
-#define RX_PRIORITY_OFFSET0_RSSI_LOW_MASK 0x00fc0000
-#define RX_PRIORITY_OFFSET0_RSSI_LOW_GET(x) (((x) & RX_PRIORITY_OFFSET0_RSSI_LOW_MASK) >> RX_PRIORITY_OFFSET0_RSSI_LOW_LSB)
-#define RX_PRIORITY_OFFSET0_RSSI_LOW_SET(x) (((x) << RX_PRIORITY_OFFSET0_RSSI_LOW_LSB) & RX_PRIORITY_OFFSET0_RSSI_LOW_MASK)
-#define RX_PRIORITY_OFFSET0_RSSI_HIGH_MSB 17
-#define RX_PRIORITY_OFFSET0_RSSI_HIGH_LSB 12
-#define RX_PRIORITY_OFFSET0_RSSI_HIGH_MASK 0x0003f000
-#define RX_PRIORITY_OFFSET0_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET0_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET0_RSSI_HIGH_LSB)
-#define RX_PRIORITY_OFFSET0_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET0_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET0_RSSI_HIGH_MASK)
-#define RX_PRIORITY_OFFSET0_PHY_RATE_LOW_MSB 11
-#define RX_PRIORITY_OFFSET0_PHY_RATE_LOW_LSB 6
-#define RX_PRIORITY_OFFSET0_PHY_RATE_LOW_MASK 0x00000fc0
-#define RX_PRIORITY_OFFSET0_PHY_RATE_LOW_GET(x) (((x) & RX_PRIORITY_OFFSET0_PHY_RATE_LOW_MASK) >> RX_PRIORITY_OFFSET0_PHY_RATE_LOW_LSB)
-#define RX_PRIORITY_OFFSET0_PHY_RATE_LOW_SET(x) (((x) << RX_PRIORITY_OFFSET0_PHY_RATE_LOW_LSB) & RX_PRIORITY_OFFSET0_PHY_RATE_LOW_MASK)
-#define RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_MSB 5
-#define RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_LSB 0
-#define RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_MASK 0x0000003f
-#define RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_MASK) >> RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_LSB)
-#define RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_LSB) & RX_PRIORITY_OFFSET0_PHY_RATE_HIGH_MASK)
-
-#define RX_PRIORITY_OFFSET1_ADDRESS 0x00008388
-#define RX_PRIORITY_OFFSET1_OFFSET 0x00000388
-#define RX_PRIORITY_OFFSET1_RTS_MSB 29
-#define RX_PRIORITY_OFFSET1_RTS_LSB 24
-#define RX_PRIORITY_OFFSET1_RTS_MASK 0x3f000000
-#define RX_PRIORITY_OFFSET1_RTS_GET(x) (((x) & RX_PRIORITY_OFFSET1_RTS_MASK) >> RX_PRIORITY_OFFSET1_RTS_LSB)
-#define RX_PRIORITY_OFFSET1_RTS_SET(x) (((x) << RX_PRIORITY_OFFSET1_RTS_LSB) & RX_PRIORITY_OFFSET1_RTS_MASK)
-#define RX_PRIORITY_OFFSET1_RETX_MSB 23
-#define RX_PRIORITY_OFFSET1_RETX_LSB 18
-#define RX_PRIORITY_OFFSET1_RETX_MASK 0x00fc0000
-#define RX_PRIORITY_OFFSET1_RETX_GET(x) (((x) & RX_PRIORITY_OFFSET1_RETX_MASK) >> RX_PRIORITY_OFFSET1_RETX_LSB)
-#define RX_PRIORITY_OFFSET1_RETX_SET(x) (((x) << RX_PRIORITY_OFFSET1_RETX_LSB) & RX_PRIORITY_OFFSET1_RETX_MASK)
-#define RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_MSB 17
-#define RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_LSB 12
-#define RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_MASK 0x0003f000
-#define RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_LSB)
-#define RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET1_PRESP_RSSI_HIGH_MASK)
-#define RX_PRIORITY_OFFSET1_LENGTH_LOW_MSB 11
-#define RX_PRIORITY_OFFSET1_LENGTH_LOW_LSB 6
-#define RX_PRIORITY_OFFSET1_LENGTH_LOW_MASK 0x00000fc0
-#define RX_PRIORITY_OFFSET1_LENGTH_LOW_GET(x) (((x) & RX_PRIORITY_OFFSET1_LENGTH_LOW_MASK) >> RX_PRIORITY_OFFSET1_LENGTH_LOW_LSB)
-#define RX_PRIORITY_OFFSET1_LENGTH_LOW_SET(x) (((x) << RX_PRIORITY_OFFSET1_LENGTH_LOW_LSB) & RX_PRIORITY_OFFSET1_LENGTH_LOW_MASK)
-#define RX_PRIORITY_OFFSET1_LENGTH_HIGH_MSB 5
-#define RX_PRIORITY_OFFSET1_LENGTH_HIGH_LSB 0
-#define RX_PRIORITY_OFFSET1_LENGTH_HIGH_MASK 0x0000003f
-#define RX_PRIORITY_OFFSET1_LENGTH_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET1_LENGTH_HIGH_MASK) >> RX_PRIORITY_OFFSET1_LENGTH_HIGH_LSB)
-#define RX_PRIORITY_OFFSET1_LENGTH_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET1_LENGTH_HIGH_LSB) & RX_PRIORITY_OFFSET1_LENGTH_HIGH_MASK)
-
-#define RX_PRIORITY_OFFSET2_ADDRESS 0x0000838c
-#define RX_PRIORITY_OFFSET2_OFFSET 0x0000038c
-#define RX_PRIORITY_OFFSET2_BEACON_MSB 29
-#define RX_PRIORITY_OFFSET2_BEACON_LSB 24
-#define RX_PRIORITY_OFFSET2_BEACON_MASK 0x3f000000
-#define RX_PRIORITY_OFFSET2_BEACON_GET(x) (((x) & RX_PRIORITY_OFFSET2_BEACON_MASK) >> RX_PRIORITY_OFFSET2_BEACON_LSB)
-#define RX_PRIORITY_OFFSET2_BEACON_SET(x) (((x) << RX_PRIORITY_OFFSET2_BEACON_LSB) & RX_PRIORITY_OFFSET2_BEACON_MASK)
-#define RX_PRIORITY_OFFSET2_MGMT_MSB 23
-#define RX_PRIORITY_OFFSET2_MGMT_LSB 18
-#define RX_PRIORITY_OFFSET2_MGMT_MASK 0x00fc0000
-#define RX_PRIORITY_OFFSET2_MGMT_GET(x) (((x) & RX_PRIORITY_OFFSET2_MGMT_MASK) >> RX_PRIORITY_OFFSET2_MGMT_LSB)
-#define RX_PRIORITY_OFFSET2_MGMT_SET(x) (((x) << RX_PRIORITY_OFFSET2_MGMT_LSB) & RX_PRIORITY_OFFSET2_MGMT_MASK)
-#define RX_PRIORITY_OFFSET2_ATIM_MSB 17
-#define RX_PRIORITY_OFFSET2_ATIM_LSB 12
-#define RX_PRIORITY_OFFSET2_ATIM_MASK 0x0003f000
-#define RX_PRIORITY_OFFSET2_ATIM_GET(x) (((x) & RX_PRIORITY_OFFSET2_ATIM_MASK) >> RX_PRIORITY_OFFSET2_ATIM_LSB)
-#define RX_PRIORITY_OFFSET2_ATIM_SET(x) (((x) << RX_PRIORITY_OFFSET2_ATIM_LSB) & RX_PRIORITY_OFFSET2_ATIM_MASK)
-#define RX_PRIORITY_OFFSET2_PRESP_MSB 11
-#define RX_PRIORITY_OFFSET2_PRESP_LSB 6
-#define RX_PRIORITY_OFFSET2_PRESP_MASK 0x00000fc0
-#define RX_PRIORITY_OFFSET2_PRESP_GET(x) (((x) & RX_PRIORITY_OFFSET2_PRESP_MASK) >> RX_PRIORITY_OFFSET2_PRESP_LSB)
-#define RX_PRIORITY_OFFSET2_PRESP_SET(x) (((x) << RX_PRIORITY_OFFSET2_PRESP_LSB) & RX_PRIORITY_OFFSET2_PRESP_MASK)
-#define RX_PRIORITY_OFFSET2_XCAST_MSB 5
-#define RX_PRIORITY_OFFSET2_XCAST_LSB 0
-#define RX_PRIORITY_OFFSET2_XCAST_MASK 0x0000003f
-#define RX_PRIORITY_OFFSET2_XCAST_GET(x) (((x) & RX_PRIORITY_OFFSET2_XCAST_MASK) >> RX_PRIORITY_OFFSET2_XCAST_LSB)
-#define RX_PRIORITY_OFFSET2_XCAST_SET(x) (((x) << RX_PRIORITY_OFFSET2_XCAST_LSB) & RX_PRIORITY_OFFSET2_XCAST_MASK)
-
-#define RX_PRIORITY_OFFSET3_ADDRESS 0x00008390
-#define RX_PRIORITY_OFFSET3_OFFSET 0x00000390
-#define RX_PRIORITY_OFFSET3_PS_POLL_MSB 29
-#define RX_PRIORITY_OFFSET3_PS_POLL_LSB 24
-#define RX_PRIORITY_OFFSET3_PS_POLL_MASK 0x3f000000
-#define RX_PRIORITY_OFFSET3_PS_POLL_GET(x) (((x) & RX_PRIORITY_OFFSET3_PS_POLL_MASK) >> RX_PRIORITY_OFFSET3_PS_POLL_LSB)
-#define RX_PRIORITY_OFFSET3_PS_POLL_SET(x) (((x) << RX_PRIORITY_OFFSET3_PS_POLL_LSB) & RX_PRIORITY_OFFSET3_PS_POLL_MASK)
-#define RX_PRIORITY_OFFSET3_AMSDU_MSB 23
-#define RX_PRIORITY_OFFSET3_AMSDU_LSB 18
-#define RX_PRIORITY_OFFSET3_AMSDU_MASK 0x00fc0000
-#define RX_PRIORITY_OFFSET3_AMSDU_GET(x) (((x) & RX_PRIORITY_OFFSET3_AMSDU_MASK) >> RX_PRIORITY_OFFSET3_AMSDU_LSB)
-#define RX_PRIORITY_OFFSET3_AMSDU_SET(x) (((x) << RX_PRIORITY_OFFSET3_AMSDU_LSB) & RX_PRIORITY_OFFSET3_AMSDU_MASK)
-#define RX_PRIORITY_OFFSET3_AMPDU_MSB 17
-#define RX_PRIORITY_OFFSET3_AMPDU_LSB 12
-#define RX_PRIORITY_OFFSET3_AMPDU_MASK 0x0003f000
-#define RX_PRIORITY_OFFSET3_AMPDU_GET(x) (((x) & RX_PRIORITY_OFFSET3_AMPDU_MASK) >> RX_PRIORITY_OFFSET3_AMPDU_LSB)
-#define RX_PRIORITY_OFFSET3_AMPDU_SET(x) (((x) << RX_PRIORITY_OFFSET3_AMPDU_LSB) & RX_PRIORITY_OFFSET3_AMPDU_MASK)
-#define RX_PRIORITY_OFFSET3_EOSP_MSB 11
-#define RX_PRIORITY_OFFSET3_EOSP_LSB 6
-#define RX_PRIORITY_OFFSET3_EOSP_MASK 0x00000fc0
-#define RX_PRIORITY_OFFSET3_EOSP_GET(x) (((x) & RX_PRIORITY_OFFSET3_EOSP_MASK) >> RX_PRIORITY_OFFSET3_EOSP_LSB)
-#define RX_PRIORITY_OFFSET3_EOSP_SET(x) (((x) << RX_PRIORITY_OFFSET3_EOSP_LSB) & RX_PRIORITY_OFFSET3_EOSP_MASK)
-#define RX_PRIORITY_OFFSET3_MORE_MSB 5
-#define RX_PRIORITY_OFFSET3_MORE_LSB 0
-#define RX_PRIORITY_OFFSET3_MORE_MASK 0x0000003f
-#define RX_PRIORITY_OFFSET3_MORE_GET(x) (((x) & RX_PRIORITY_OFFSET3_MORE_MASK) >> RX_PRIORITY_OFFSET3_MORE_LSB)
-#define RX_PRIORITY_OFFSET3_MORE_SET(x) (((x) << RX_PRIORITY_OFFSET3_MORE_LSB) & RX_PRIORITY_OFFSET3_MORE_MASK)
-
-#define RX_PRIORITY_OFFSET4_ADDRESS 0x00008394
-#define RX_PRIORITY_OFFSET4_OFFSET 0x00000394
-#define RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_MSB 29
-#define RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_LSB 24
-#define RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_MASK 0x3f000000
-#define RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_LSB)
-#define RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET4_BEACON_RSSI_HIGH_MASK)
-#define RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_MSB 23
-#define RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_LSB 18
-#define RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_MASK 0x00fc0000
-#define RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_LSB)
-#define RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET4_MGMT_RSSI_HIGH_MASK)
-#define RX_PRIORITY_OFFSET4_BEACON_SSID_MSB 17
-#define RX_PRIORITY_OFFSET4_BEACON_SSID_LSB 12
-#define RX_PRIORITY_OFFSET4_BEACON_SSID_MASK 0x0003f000
-#define RX_PRIORITY_OFFSET4_BEACON_SSID_GET(x) (((x) & RX_PRIORITY_OFFSET4_BEACON_SSID_MASK) >> RX_PRIORITY_OFFSET4_BEACON_SSID_LSB)
-#define RX_PRIORITY_OFFSET4_BEACON_SSID_SET(x) (((x) << RX_PRIORITY_OFFSET4_BEACON_SSID_LSB) & RX_PRIORITY_OFFSET4_BEACON_SSID_MASK)
-#define RX_PRIORITY_OFFSET4_NULL_MSB 11
-#define RX_PRIORITY_OFFSET4_NULL_LSB 6
-#define RX_PRIORITY_OFFSET4_NULL_MASK 0x00000fc0
-#define RX_PRIORITY_OFFSET4_NULL_GET(x) (((x) & RX_PRIORITY_OFFSET4_NULL_MASK) >> RX_PRIORITY_OFFSET4_NULL_LSB)
-#define RX_PRIORITY_OFFSET4_NULL_SET(x) (((x) << RX_PRIORITY_OFFSET4_NULL_LSB) & RX_PRIORITY_OFFSET4_NULL_MASK)
-#define RX_PRIORITY_OFFSET4_PREQ_MSB 5
-#define RX_PRIORITY_OFFSET4_PREQ_LSB 0
-#define RX_PRIORITY_OFFSET4_PREQ_MASK 0x0000003f
-#define RX_PRIORITY_OFFSET4_PREQ_GET(x) (((x) & RX_PRIORITY_OFFSET4_PREQ_MASK) >> RX_PRIORITY_OFFSET4_PREQ_LSB)
-#define RX_PRIORITY_OFFSET4_PREQ_SET(x) (((x) << RX_PRIORITY_OFFSET4_PREQ_LSB) & RX_PRIORITY_OFFSET4_PREQ_MASK)
-
-#define RX_PRIORITY_OFFSET5_ADDRESS 0x00008398
-#define RX_PRIORITY_OFFSET5_OFFSET 0x00000398
-#define RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_MSB 17
-#define RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_LSB 12
-#define RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_MASK 0x0003f000
-#define RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_LSB)
-#define RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET5_PS_POLL_RSSI_HIGH_MASK)
-#define RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_MSB 11
-#define RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_LSB 6
-#define RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_MASK 0x00000fc0
-#define RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_LSB)
-#define RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET5_PREQ_RSSI_HIGH_MASK)
-#define RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_MSB 5
-#define RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_LSB 0
-#define RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_MASK 0x0000003f
-#define RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_GET(x) (((x) & RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_MASK) >> RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_LSB)
-#define RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_SET(x) (((x) << RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_LSB) & RX_PRIORITY_OFFSET5_NULL_RSSI_HIGH_MASK)
-
-#define MAC_PCU_BSSID2_L32_ADDRESS 0x0000839c
-#define MAC_PCU_BSSID2_L32_OFFSET 0x0000039c
-#define MAC_PCU_BSSID2_L32_ADDR_MSB 31
-#define MAC_PCU_BSSID2_L32_ADDR_LSB 0
-#define MAC_PCU_BSSID2_L32_ADDR_MASK 0xffffffff
-#define MAC_PCU_BSSID2_L32_ADDR_GET(x) (((x) & MAC_PCU_BSSID2_L32_ADDR_MASK) >> MAC_PCU_BSSID2_L32_ADDR_LSB)
-#define MAC_PCU_BSSID2_L32_ADDR_SET(x) (((x) << MAC_PCU_BSSID2_L32_ADDR_LSB) & MAC_PCU_BSSID2_L32_ADDR_MASK)
-
-#define MAC_PCU_BSSID2_U16_ADDRESS 0x000083a0
-#define MAC_PCU_BSSID2_U16_OFFSET 0x000003a0
-#define MAC_PCU_BSSID2_U16_ENABLE_MSB 16
-#define MAC_PCU_BSSID2_U16_ENABLE_LSB 16
-#define MAC_PCU_BSSID2_U16_ENABLE_MASK 0x00010000
-#define MAC_PCU_BSSID2_U16_ENABLE_GET(x) (((x) & MAC_PCU_BSSID2_U16_ENABLE_MASK) >> MAC_PCU_BSSID2_U16_ENABLE_LSB)
-#define MAC_PCU_BSSID2_U16_ENABLE_SET(x) (((x) << MAC_PCU_BSSID2_U16_ENABLE_LSB) & MAC_PCU_BSSID2_U16_ENABLE_MASK)
-#define MAC_PCU_BSSID2_U16_ADDR_MSB 15
-#define MAC_PCU_BSSID2_U16_ADDR_LSB 0
-#define MAC_PCU_BSSID2_U16_ADDR_MASK 0x0000ffff
-#define MAC_PCU_BSSID2_U16_ADDR_GET(x) (((x) & MAC_PCU_BSSID2_U16_ADDR_MASK) >> MAC_PCU_BSSID2_U16_ADDR_LSB)
-#define MAC_PCU_BSSID2_U16_ADDR_SET(x) (((x) << MAC_PCU_BSSID2_U16_ADDR_LSB) & MAC_PCU_BSSID2_U16_ADDR_MASK)
-
-#define MAC_PCU_TSF1_STATUS_L32_ADDRESS 0x000083a4
-#define MAC_PCU_TSF1_STATUS_L32_OFFSET 0x000003a4
-#define MAC_PCU_TSF1_STATUS_L32_VALUE_MSB 31
-#define MAC_PCU_TSF1_STATUS_L32_VALUE_LSB 0
-#define MAC_PCU_TSF1_STATUS_L32_VALUE_MASK 0xffffffff
-#define MAC_PCU_TSF1_STATUS_L32_VALUE_GET(x) (((x) & MAC_PCU_TSF1_STATUS_L32_VALUE_MASK) >> MAC_PCU_TSF1_STATUS_L32_VALUE_LSB)
-#define MAC_PCU_TSF1_STATUS_L32_VALUE_SET(x) (((x) << MAC_PCU_TSF1_STATUS_L32_VALUE_LSB) & MAC_PCU_TSF1_STATUS_L32_VALUE_MASK)
-
-#define MAC_PCU_TSF1_STATUS_U32_ADDRESS 0x000083a8
-#define MAC_PCU_TSF1_STATUS_U32_OFFSET 0x000003a8
-#define MAC_PCU_TSF1_STATUS_U32_VALUE_MSB 31
-#define MAC_PCU_TSF1_STATUS_U32_VALUE_LSB 0
-#define MAC_PCU_TSF1_STATUS_U32_VALUE_MASK 0xffffffff
-#define MAC_PCU_TSF1_STATUS_U32_VALUE_GET(x) (((x) & MAC_PCU_TSF1_STATUS_U32_VALUE_MASK) >> MAC_PCU_TSF1_STATUS_U32_VALUE_LSB)
-#define MAC_PCU_TSF1_STATUS_U32_VALUE_SET(x) (((x) << MAC_PCU_TSF1_STATUS_U32_VALUE_LSB) & MAC_PCU_TSF1_STATUS_U32_VALUE_MASK)
-
-#define MAC_PCU_TSF2_STATUS_L32_ADDRESS 0x000083ac
-#define MAC_PCU_TSF2_STATUS_L32_OFFSET 0x000003ac
-#define MAC_PCU_TSF2_STATUS_L32_VALUE_MSB 31
-#define MAC_PCU_TSF2_STATUS_L32_VALUE_LSB 0
-#define MAC_PCU_TSF2_STATUS_L32_VALUE_MASK 0xffffffff
-#define MAC_PCU_TSF2_STATUS_L32_VALUE_GET(x) (((x) & MAC_PCU_TSF2_STATUS_L32_VALUE_MASK) >> MAC_PCU_TSF2_STATUS_L32_VALUE_LSB)
-#define MAC_PCU_TSF2_STATUS_L32_VALUE_SET(x) (((x) << MAC_PCU_TSF2_STATUS_L32_VALUE_LSB) & MAC_PCU_TSF2_STATUS_L32_VALUE_MASK)
-
-#define MAC_PCU_TSF2_STATUS_U32_ADDRESS 0x000083b0
-#define MAC_PCU_TSF2_STATUS_U32_OFFSET 0x000003b0
-#define MAC_PCU_TSF2_STATUS_U32_VALUE_MSB 31
-#define MAC_PCU_TSF2_STATUS_U32_VALUE_LSB 0
-#define MAC_PCU_TSF2_STATUS_U32_VALUE_MASK 0xffffffff
-#define MAC_PCU_TSF2_STATUS_U32_VALUE_GET(x) (((x) & MAC_PCU_TSF2_STATUS_U32_VALUE_MASK) >> MAC_PCU_TSF2_STATUS_U32_VALUE_LSB)
-#define MAC_PCU_TSF2_STATUS_U32_VALUE_SET(x) (((x) << MAC_PCU_TSF2_STATUS_U32_VALUE_LSB) & MAC_PCU_TSF2_STATUS_U32_VALUE_MASK)
-
-#define MAC_PCU_TXBUF_BA_ADDRESS 0x00008400
-#define MAC_PCU_TXBUF_BA_OFFSET 0x00000400
-#define MAC_PCU_TXBUF_BA_DATA_MSB 31
-#define MAC_PCU_TXBUF_BA_DATA_LSB 0
-#define MAC_PCU_TXBUF_BA_DATA_MASK 0xffffffff
-#define MAC_PCU_TXBUF_BA_DATA_GET(x) (((x) & MAC_PCU_TXBUF_BA_DATA_MASK) >> MAC_PCU_TXBUF_BA_DATA_LSB)
-#define MAC_PCU_TXBUF_BA_DATA_SET(x) (((x) << MAC_PCU_TXBUF_BA_DATA_LSB) & MAC_PCU_TXBUF_BA_DATA_MASK)
-
-#define MAC_PCU_KEY_CACHE_1_ADDRESS 0x00008800
-#define MAC_PCU_KEY_CACHE_1_OFFSET 0x00000800
-#define MAC_PCU_KEY_CACHE_1_DATA_MSB 31
-#define MAC_PCU_KEY_CACHE_1_DATA_LSB 0
-#define MAC_PCU_KEY_CACHE_1_DATA_MASK 0xffffffff
-#define MAC_PCU_KEY_CACHE_1_DATA_GET(x) (((x) & MAC_PCU_KEY_CACHE_1_DATA_MASK) >> MAC_PCU_KEY_CACHE_1_DATA_LSB)
-#define MAC_PCU_KEY_CACHE_1_DATA_SET(x) (((x) << MAC_PCU_KEY_CACHE_1_DATA_LSB) & MAC_PCU_KEY_CACHE_1_DATA_MASK)
-
-#define MAC_PCU_BASEBAND_0_ADDRESS 0x00009800
-#define MAC_PCU_BASEBAND_0_OFFSET 0x00001800
-#define MAC_PCU_BASEBAND_0_DATA_MSB 31
-#define MAC_PCU_BASEBAND_0_DATA_LSB 0
-#define MAC_PCU_BASEBAND_0_DATA_MASK 0xffffffff
-#define MAC_PCU_BASEBAND_0_DATA_GET(x) (((x) & MAC_PCU_BASEBAND_0_DATA_MASK) >> MAC_PCU_BASEBAND_0_DATA_LSB)
-#define MAC_PCU_BASEBAND_0_DATA_SET(x) (((x) << MAC_PCU_BASEBAND_0_DATA_LSB) & MAC_PCU_BASEBAND_0_DATA_MASK)
-
-#define MAC_PCU_BASEBAND_1_ADDRESS 0x0000a000
-#define MAC_PCU_BASEBAND_1_OFFSET 0x00002000
-#define MAC_PCU_BASEBAND_1_DATA_MSB 31
-#define MAC_PCU_BASEBAND_1_DATA_LSB 0
-#define MAC_PCU_BASEBAND_1_DATA_MASK 0xffffffff
-#define MAC_PCU_BASEBAND_1_DATA_GET(x) (((x) & MAC_PCU_BASEBAND_1_DATA_MASK) >> MAC_PCU_BASEBAND_1_DATA_LSB)
-#define MAC_PCU_BASEBAND_1_DATA_SET(x) (((x) << MAC_PCU_BASEBAND_1_DATA_LSB) & MAC_PCU_BASEBAND_1_DATA_MASK)
-
-#define MAC_PCU_BASEBAND_2_ADDRESS 0x0000c000
-#define MAC_PCU_BASEBAND_2_OFFSET 0x00004000
-#define MAC_PCU_BASEBAND_2_DATA_MSB 31
-#define MAC_PCU_BASEBAND_2_DATA_LSB 0
-#define MAC_PCU_BASEBAND_2_DATA_MASK 0xffffffff
-#define MAC_PCU_BASEBAND_2_DATA_GET(x) (((x) & MAC_PCU_BASEBAND_2_DATA_MASK) >> MAC_PCU_BASEBAND_2_DATA_LSB)
-#define MAC_PCU_BASEBAND_2_DATA_SET(x) (((x) << MAC_PCU_BASEBAND_2_DATA_LSB) & MAC_PCU_BASEBAND_2_DATA_MASK)
-
-#define MAC_PCU_BASEBAND_3_ADDRESS 0x0000d000
-#define MAC_PCU_BASEBAND_3_OFFSET 0x00005000
-#define MAC_PCU_BASEBAND_3_DATA_MSB 31
-#define MAC_PCU_BASEBAND_3_DATA_LSB 0
-#define MAC_PCU_BASEBAND_3_DATA_MASK 0xffffffff
-#define MAC_PCU_BASEBAND_3_DATA_GET(x) (((x) & MAC_PCU_BASEBAND_3_DATA_MASK) >> MAC_PCU_BASEBAND_3_DATA_LSB)
-#define MAC_PCU_BASEBAND_3_DATA_SET(x) (((x) << MAC_PCU_BASEBAND_3_DATA_LSB) & MAC_PCU_BASEBAND_3_DATA_MASK)
-
-#define MAC_PCU_BUF_ADDRESS 0x0000e000
-#define MAC_PCU_BUF_OFFSET 0x00006000
-#define MAC_PCU_BUF_DATA_MSB 31
-#define MAC_PCU_BUF_DATA_LSB 0
-#define MAC_PCU_BUF_DATA_MASK 0xffffffff
-#define MAC_PCU_BUF_DATA_GET(x) (((x) & MAC_PCU_BUF_DATA_MASK) >> MAC_PCU_BUF_DATA_LSB)
-#define MAC_PCU_BUF_DATA_SET(x) (((x) << MAC_PCU_BUF_DATA_LSB) & MAC_PCU_BUF_DATA_MASK)
-
-
-#ifndef __ASSEMBLER__
-
-typedef struct mac_pcu_reg_s {
- volatile unsigned int mac_pcu_sta_addr_l32;
- volatile unsigned int mac_pcu_sta_addr_u16;
- volatile unsigned int mac_pcu_bssid_l32;
- volatile unsigned int mac_pcu_bssid_u16;
- volatile unsigned int mac_pcu_bcn_rssi_ave;
- volatile unsigned int mac_pcu_ack_cts_timeout;
- volatile unsigned int mac_pcu_bcn_rssi_ctl;
- volatile unsigned int mac_pcu_usec_latency;
- volatile unsigned int pcu_max_cfp_dur;
- volatile unsigned int mac_pcu_rx_filter;
- volatile unsigned int mac_pcu_mcast_filter_l32;
- volatile unsigned int mac_pcu_mcast_filter_u32;
- volatile unsigned int mac_pcu_diag_sw;
- volatile unsigned int mac_pcu_tst_addac;
- volatile unsigned int mac_pcu_def_antenna;
- volatile unsigned int mac_pcu_aes_mute_mask_0;
- volatile unsigned int mac_pcu_aes_mute_mask_1;
- volatile unsigned int mac_pcu_gated_clks;
- volatile unsigned int mac_pcu_obs_bus_2;
- volatile unsigned int mac_pcu_obs_bus_1;
- volatile unsigned int mac_pcu_dym_mimo_pwr_save;
- volatile unsigned int mac_pcu_last_beacon_tsf;
- volatile unsigned int mac_pcu_nav;
- volatile unsigned int mac_pcu_rts_success_cnt;
- volatile unsigned int mac_pcu_rts_fail_cnt;
- volatile unsigned int mac_pcu_ack_fail_cnt;
- volatile unsigned int mac_pcu_fcs_fail_cnt;
- volatile unsigned int mac_pcu_beacon_cnt;
- volatile unsigned int mac_pcu_xrmode;
- volatile unsigned int mac_pcu_xrdel;
- volatile unsigned int mac_pcu_xrto;
- volatile unsigned int mac_pcu_xrcrp;
- volatile unsigned int mac_pcu_xrstmp;
- volatile unsigned int mac_pcu_addr1_mask_l32;
- volatile unsigned int mac_pcu_addr1_mask_u16;
- volatile unsigned int mac_pcu_tpc;
- volatile unsigned int mac_pcu_tx_frame_cnt;
- volatile unsigned int mac_pcu_rx_frame_cnt;
- volatile unsigned int mac_pcu_rx_clear_cnt;
- volatile unsigned int mac_pcu_cycle_cnt;
- volatile unsigned int mac_pcu_quiet_time_1;
- volatile unsigned int mac_pcu_quiet_time_2;
- volatile unsigned int mac_pcu_qos_no_ack;
- volatile unsigned int mac_pcu_phy_error_mask;
- volatile unsigned int mac_pcu_xrlat;
- volatile unsigned int mac_pcu_rxbuf;
- volatile unsigned int mac_pcu_mic_qos_control;
- volatile unsigned int mac_pcu_mic_qos_select;
- volatile unsigned int mac_pcu_misc_mode;
- volatile unsigned int mac_pcu_filter_ofdm_cnt;
- volatile unsigned int mac_pcu_filter_cck_cnt;
- volatile unsigned int mac_pcu_phy_err_cnt_1;
- volatile unsigned int mac_pcu_phy_err_cnt_1_mask;
- volatile unsigned int mac_pcu_phy_err_cnt_2;
- volatile unsigned int mac_pcu_phy_err_cnt_2_mask;
- volatile unsigned int mac_pcu_tsf_threshold;
- volatile unsigned int mac_pcu_phy_error_eifs_mask;
- volatile unsigned int mac_pcu_phy_err_cnt_3;
- volatile unsigned int mac_pcu_phy_err_cnt_3_mask;
- volatile unsigned int mac_pcu_bluetooth_mode;
- volatile unsigned int mac_pcu_bluetooth_weights;
- volatile unsigned int mac_pcu_bluetooth_mode2;
- volatile unsigned int mac_pcu_txsifs;
- volatile unsigned int mac_pcu_txop_x;
- volatile unsigned int mac_pcu_txop_0_3;
- volatile unsigned int mac_pcu_txop_4_7;
- volatile unsigned int mac_pcu_txop_8_11;
- volatile unsigned int mac_pcu_txop_12_15;
- volatile unsigned int mac_pcu_logic_analyzer;
- volatile unsigned int mac_pcu_logic_analyzer_32l;
- volatile unsigned int mac_pcu_logic_analyzer_16u;
- volatile unsigned int mac_pcu_phy_err_cnt_mask_cont;
- volatile unsigned int mac_pcu_azimuth_mode;
- volatile unsigned int mac_pcu_20_40_mode;
- volatile unsigned int mac_pcu_rx_clear_diff_cnt;
- volatile unsigned int mac_pcu_self_gen_antenna_mask;
- volatile unsigned int mac_pcu_ba_bar_control;
- volatile unsigned int mac_pcu_legacy_plcp_spoof;
- volatile unsigned int mac_pcu_phy_error_mask_cont;
- volatile unsigned int mac_pcu_tx_timer;
- volatile unsigned int mac_pcu_txbuf_ctrl;
- volatile unsigned int mac_pcu_misc_mode2;
- volatile unsigned int mac_pcu_alt_aes_mute_mask;
- volatile unsigned int mac_pcu_azimuth_time_stamp;
- volatile unsigned int mac_pcu_max_cfp_dur;
- volatile unsigned int mac_pcu_hcf_timeout;
- volatile unsigned int mac_pcu_bluetooth_weights2;
- volatile unsigned int mac_pcu_bluetooth_tsf_bt_active;
- volatile unsigned int mac_pcu_bluetooth_tsf_bt_priority;
- volatile unsigned int mac_pcu_bluetooth_mode3;
- volatile unsigned int mac_pcu_bluetooth_mode4;
- unsigned char pad0[148]; /* pad to 0x200 */
- volatile unsigned int mac_pcu_bt_bt[64];
- volatile unsigned int mac_pcu_bt_bt_async;
- volatile unsigned int mac_pcu_bt_wl_1;
- volatile unsigned int mac_pcu_bt_wl_2;
- volatile unsigned int mac_pcu_bt_wl_3;
- volatile unsigned int mac_pcu_bt_wl_4;
- volatile unsigned int mac_pcu_coex_epta;
- volatile unsigned int mac_pcu_coex_lnamaxgain1;
- volatile unsigned int mac_pcu_coex_lnamaxgain2;
- volatile unsigned int mac_pcu_coex_lnamaxgain3;
- volatile unsigned int mac_pcu_coex_lnamaxgain4;
- volatile unsigned int mac_pcu_basic_rate_set0;
- volatile unsigned int mac_pcu_basic_rate_set1;
- volatile unsigned int mac_pcu_basic_rate_set2;
- volatile unsigned int mac_pcu_basic_rate_set3;
- volatile unsigned int mac_pcu_rx_int_status0;
- volatile unsigned int mac_pcu_rx_int_status1;
- volatile unsigned int mac_pcu_rx_int_status2;
- volatile unsigned int mac_pcu_rx_int_status3;
- volatile unsigned int ht_half_gi_rate1;
- volatile unsigned int ht_half_gi_rate2;
- volatile unsigned int ht_full_gi_rate1;
- volatile unsigned int ht_full_gi_rate2;
- volatile unsigned int legacy_rate1;
- volatile unsigned int legacy_rate2;
- volatile unsigned int legacy_rate3;
- volatile unsigned int rx_int_filter;
- volatile unsigned int rx_int_overflow;
- volatile unsigned int rx_filter_thresh;
- volatile unsigned int rx_filter_thresh1;
- volatile unsigned int rx_priority_thresh0;
- volatile unsigned int rx_priority_thresh1;
- volatile unsigned int rx_priority_thresh2;
- volatile unsigned int rx_priority_thresh3;
- volatile unsigned int rx_priority_offset0;
- volatile unsigned int rx_priority_offset1;
- volatile unsigned int rx_priority_offset2;
- volatile unsigned int rx_priority_offset3;
- volatile unsigned int rx_priority_offset4;
- volatile unsigned int rx_priority_offset5;
- volatile unsigned int mac_pcu_bssid2_l32;
- volatile unsigned int mac_pcu_bssid2_u16;
- volatile unsigned int mac_pcu_tsf1_status_l32;
- volatile unsigned int mac_pcu_tsf1_status_u32;
- volatile unsigned int mac_pcu_tsf2_status_l32;
- volatile unsigned int mac_pcu_tsf2_status_u32;
- unsigned char pad1[76]; /* pad to 0x400 */
- volatile unsigned int mac_pcu_txbuf_ba[64];
- unsigned char pad2[768]; /* pad to 0x800 */
- volatile unsigned int mac_pcu_key_cache_1[256];
- unsigned char pad3[3072]; /* pad to 0x1800 */
- volatile unsigned int mac_pcu_baseband_0[512];
- volatile unsigned int mac_pcu_baseband_1[2048];
- volatile unsigned int mac_pcu_baseband_2[1024];
- volatile unsigned int mac_pcu_baseband_3[1024];
- volatile unsigned int mac_pcu_buf[512];
-} mac_pcu_reg_t;
-
-#endif /* __ASSEMBLER__ */
-
-#endif /* _MAC_PCU_H_ */
diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mbox_host_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mbox_host_reg.h
index 3af5621..109f24e 100644
--- a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mbox_host_reg.h
+++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mbox_host_reg.h
@@ -21,17 +21,4 @@
//===================================================================
-#ifdef WLAN_HEADERS
-
#include "mbox_wlan_host_reg.h"
-
-
-#ifndef BT_HEADERS
-
-
-
-#endif
-#endif
-
-
-
diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mbox_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mbox_reg.h
index cc67585..72fa483 100644
--- a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mbox_reg.h
+++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mbox_reg.h
@@ -21,11 +21,8 @@
//===================================================================
-#ifdef WLAN_HEADERS
-
#include "mbox_wlan_reg.h"
-
#ifndef BT_HEADERS
#define MBOX_FIFO_ADDRESS WLAN_MBOX_FIFO_ADDRESS
@@ -552,9 +549,4 @@
#define HOST_IF_WINDOW_DATA_GET(x) WLAN_HOST_IF_WINDOW_DATA_GET(x)
#define HOST_IF_WINDOW_DATA_SET(x) WLAN_HOST_IF_WINDOW_DATA_SET(x)
-
#endif
-#endif
-
-
-
diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mbox_wlan_host_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mbox_wlan_host_reg.h
index 6085502..038d0d0 100644
--- a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mbox_wlan_host_reg.h
+++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mbox_wlan_host_reg.h
@@ -468,55 +468,4 @@
#define CIS_WINDOW_DATA_SET(x) (((x) << CIS_WINDOW_DATA_LSB) & CIS_WINDOW_DATA_MASK)
-#ifndef __ASSEMBLER__
-
-typedef struct mbox_wlan_host_reg_reg_s {
- unsigned char pad0[1024]; /* pad to 0x400 */
- volatile unsigned char host_int_status;
- volatile unsigned char cpu_int_status;
- volatile unsigned char error_int_status;
- volatile unsigned char counter_int_status;
- volatile unsigned char mbox_frame;
- volatile unsigned char rx_lookahead_valid;
- volatile unsigned char host_int_status2;
- volatile unsigned char gmbox_rx_avail;
- volatile unsigned char rx_lookahead0[4];
- volatile unsigned char rx_lookahead1[4];
- volatile unsigned char rx_lookahead2[4];
- volatile unsigned char rx_lookahead3[4];
- volatile unsigned char int_status_enable;
- volatile unsigned char cpu_int_status_enable;
- volatile unsigned char error_status_enable;
- volatile unsigned char counter_int_status_enable;
- unsigned char pad1[4]; /* pad to 0x420 */
- volatile unsigned char count[8];
- unsigned char pad2[24]; /* pad to 0x440 */
- volatile unsigned char count_dec[32];
- volatile unsigned char scratch[8];
- volatile unsigned char fifo_timeout;
- volatile unsigned char fifo_timeout_enable;
- volatile unsigned char disable_sleep;
- unsigned char pad3[5]; /* pad to 0x470 */
- volatile unsigned char local_bus;
- unsigned char pad4[1]; /* pad to 0x472 */
- volatile unsigned char int_wlan;
- unsigned char pad5[1]; /* pad to 0x474 */
- volatile unsigned char window_data[4];
- volatile unsigned char window_write_addr[4];
- volatile unsigned char window_read_addr[4];
- volatile unsigned char host_ctrl_spi_config;
- volatile unsigned char host_ctrl_spi_status;
- volatile unsigned char non_assoc_sleep_en;
- volatile unsigned char cpu_dbg_sel;
- volatile unsigned char cpu_dbg[4];
- volatile unsigned char int_status2_enable;
- unsigned char pad6[7]; /* pad to 0x490 */
- volatile unsigned char gmbox_rx_lookahead[8];
- volatile unsigned char gmbox_rx_lookahead_mux;
- unsigned char pad7[359]; /* pad to 0x600 */
- volatile unsigned char cis_window[512];
-} mbox_wlan_host_reg_reg_t;
-
-#endif /* __ASSEMBLER__ */
-
#endif /* _MBOX_WLAN_HOST_REG_H_ */
diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mbox_wlan_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mbox_wlan_reg.h
index e00270f..f5167b9 100644
--- a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mbox_wlan_reg.h
+++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/mbox_wlan_reg.h
@@ -586,53 +586,4 @@
#define WLAN_HOST_IF_WINDOW_DATA_GET(x) (((x) & WLAN_HOST_IF_WINDOW_DATA_MASK) >> WLAN_HOST_IF_WINDOW_DATA_LSB)
#define WLAN_HOST_IF_WINDOW_DATA_SET(x) (((x) << WLAN_HOST_IF_WINDOW_DATA_LSB) & WLAN_HOST_IF_WINDOW_DATA_MASK)
-
-#ifndef __ASSEMBLER__
-
-typedef struct mbox_wlan_reg_reg_s {
- volatile unsigned int wlan_mbox_fifo[4];
- volatile unsigned int wlan_mbox_fifo_status;
- volatile unsigned int wlan_mbox_dma_policy;
- volatile unsigned int wlan_mbox0_dma_rx_descriptor_base;
- volatile unsigned int wlan_mbox0_dma_rx_control;
- volatile unsigned int wlan_mbox0_dma_tx_descriptor_base;
- volatile unsigned int wlan_mbox0_dma_tx_control;
- volatile unsigned int wlan_mbox1_dma_rx_descriptor_base;
- volatile unsigned int wlan_mbox1_dma_rx_control;
- volatile unsigned int wlan_mbox1_dma_tx_descriptor_base;
- volatile unsigned int wlan_mbox1_dma_tx_control;
- volatile unsigned int wlan_mbox2_dma_rx_descriptor_base;
- volatile unsigned int wlan_mbox2_dma_rx_control;
- volatile unsigned int wlan_mbox2_dma_tx_descriptor_base;
- volatile unsigned int wlan_mbox2_dma_tx_control;
- volatile unsigned int wlan_mbox3_dma_rx_descriptor_base;
- volatile unsigned int wlan_mbox3_dma_rx_control;
- volatile unsigned int wlan_mbox3_dma_tx_descriptor_base;
- volatile unsigned int wlan_mbox3_dma_tx_control;
- volatile unsigned int wlan_mbox_int_status;
- volatile unsigned int wlan_mbox_int_enable;
- volatile unsigned int wlan_int_host;
- unsigned char pad0[28]; /* pad to 0x80 */
- volatile unsigned int wlan_local_count[8];
- volatile unsigned int wlan_count_inc[8];
- volatile unsigned int wlan_local_scratch[8];
- volatile unsigned int wlan_use_local_bus;
- volatile unsigned int wlan_sdio_config;
- volatile unsigned int wlan_mbox_debug;
- volatile unsigned int wlan_mbox_fifo_reset;
- volatile unsigned int wlan_mbox_txfifo_pop[4];
- volatile unsigned int wlan_mbox_rxfifo_pop[4];
- volatile unsigned int wlan_sdio_debug;
- volatile unsigned int wlan_gmbox0_dma_rx_descriptor_base;
- volatile unsigned int wlan_gmbox0_dma_rx_control;
- volatile unsigned int wlan_gmbox0_dma_tx_descriptor_base;
- volatile unsigned int wlan_gmbox0_dma_tx_control;
- volatile unsigned int wlan_gmbox_int_status;
- volatile unsigned int wlan_gmbox_int_enable;
- unsigned char pad1[7892]; /* pad to 0x2000 */
- volatile unsigned int wlan_host_if_window[2048];
-} mbox_wlan_reg_reg_t;
-
-#endif /* __ASSEMBLER__ */
-
#endif /* _MBOX_WLAN_REG_H_ */
diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/rdma_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/rdma_reg.h
deleted file mode 100644
index 56ffda5..0000000
--- a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/rdma_reg.h
+++ /dev/null
@@ -1,564 +0,0 @@
-// ------------------------------------------------------------------
-// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
-//
-//
-// Permission to use, copy, modify, and/or distribute this software for any
-// purpose with or without fee is hereby granted, provided that the above
-// copyright notice and this permission notice appear in all copies.
-//
-// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-//
-//
-// ------------------------------------------------------------------
-//===================================================================
-// Author(s): ="Atheros"
-//===================================================================
-
-
-#ifndef _RDMA_REG_REG_H_
-#define _RDMA_REG_REG_H_
-
-#define DMA_CONFIG_ADDRESS 0x00000000
-#define DMA_CONFIG_OFFSET 0x00000000
-#define DMA_CONFIG_WLBB_PWD_EN_MSB 4
-#define DMA_CONFIG_WLBB_PWD_EN_LSB 4
-#define DMA_CONFIG_WLBB_PWD_EN_MASK 0x00000010
-#define DMA_CONFIG_WLBB_PWD_EN_GET(x) (((x) & DMA_CONFIG_WLBB_PWD_EN_MASK) >> DMA_CONFIG_WLBB_PWD_EN_LSB)
-#define DMA_CONFIG_WLBB_PWD_EN_SET(x) (((x) << DMA_CONFIG_WLBB_PWD_EN_LSB) & DMA_CONFIG_WLBB_PWD_EN_MASK)
-#define DMA_CONFIG_WLMAC_PWD_EN_MSB 3
-#define DMA_CONFIG_WLMAC_PWD_EN_LSB 3
-#define DMA_CONFIG_WLMAC_PWD_EN_MASK 0x00000008
-#define DMA_CONFIG_WLMAC_PWD_EN_GET(x) (((x) & DMA_CONFIG_WLMAC_PWD_EN_MASK) >> DMA_CONFIG_WLMAC_PWD_EN_LSB)
-#define DMA_CONFIG_WLMAC_PWD_EN_SET(x) (((x) << DMA_CONFIG_WLMAC_PWD_EN_LSB) & DMA_CONFIG_WLMAC_PWD_EN_MASK)
-#define DMA_CONFIG_ENABLE_RETENTION_MSB 2
-#define DMA_CONFIG_ENABLE_RETENTION_LSB 2
-#define DMA_CONFIG_ENABLE_RETENTION_MASK 0x00000004
-#define DMA_CONFIG_ENABLE_RETENTION_GET(x) (((x) & DMA_CONFIG_ENABLE_RETENTION_MASK) >> DMA_CONFIG_ENABLE_RETENTION_LSB)
-#define DMA_CONFIG_ENABLE_RETENTION_SET(x) (((x) << DMA_CONFIG_ENABLE_RETENTION_LSB) & DMA_CONFIG_ENABLE_RETENTION_MASK)
-#define DMA_CONFIG_RTC_PRIORITY_MSB 1
-#define DMA_CONFIG_RTC_PRIORITY_LSB 1
-#define DMA_CONFIG_RTC_PRIORITY_MASK 0x00000002
-#define DMA_CONFIG_RTC_PRIORITY_GET(x) (((x) & DMA_CONFIG_RTC_PRIORITY_MASK) >> DMA_CONFIG_RTC_PRIORITY_LSB)
-#define DMA_CONFIG_RTC_PRIORITY_SET(x) (((x) << DMA_CONFIG_RTC_PRIORITY_LSB) & DMA_CONFIG_RTC_PRIORITY_MASK)
-#define DMA_CONFIG_DMA_TYPE_MSB 0
-#define DMA_CONFIG_DMA_TYPE_LSB 0
-#define DMA_CONFIG_DMA_TYPE_MASK 0x00000001
-#define DMA_CONFIG_DMA_TYPE_GET(x) (((x) & DMA_CONFIG_DMA_TYPE_MASK) >> DMA_CONFIG_DMA_TYPE_LSB)
-#define DMA_CONFIG_DMA_TYPE_SET(x) (((x) << DMA_CONFIG_DMA_TYPE_LSB) & DMA_CONFIG_DMA_TYPE_MASK)
-
-#define DMA_CONTROL_ADDRESS 0x00000004
-#define DMA_CONTROL_OFFSET 0x00000004
-#define DMA_CONTROL_START_MSB 1
-#define DMA_CONTROL_START_LSB 1
-#define DMA_CONTROL_START_MASK 0x00000002
-#define DMA_CONTROL_START_GET(x) (((x) & DMA_CONTROL_START_MASK) >> DMA_CONTROL_START_LSB)
-#define DMA_CONTROL_START_SET(x) (((x) << DMA_CONTROL_START_LSB) & DMA_CONTROL_START_MASK)
-#define DMA_CONTROL_STOP_MSB 0
-#define DMA_CONTROL_STOP_LSB 0
-#define DMA_CONTROL_STOP_MASK 0x00000001
-#define DMA_CONTROL_STOP_GET(x) (((x) & DMA_CONTROL_STOP_MASK) >> DMA_CONTROL_STOP_LSB)
-#define DMA_CONTROL_STOP_SET(x) (((x) << DMA_CONTROL_STOP_LSB) & DMA_CONTROL_STOP_MASK)
-
-#define DMA_SRC_ADDRESS 0x00000008
-#define DMA_SRC_OFFSET 0x00000008
-#define DMA_SRC_ADDR_MSB 31
-#define DMA_SRC_ADDR_LSB 2
-#define DMA_SRC_ADDR_MASK 0xfffffffc
-#define DMA_SRC_ADDR_GET(x) (((x) & DMA_SRC_ADDR_MASK) >> DMA_SRC_ADDR_LSB)
-#define DMA_SRC_ADDR_SET(x) (((x) << DMA_SRC_ADDR_LSB) & DMA_SRC_ADDR_MASK)
-
-#define DMA_DEST_ADDRESS 0x0000000c
-#define DMA_DEST_OFFSET 0x0000000c
-#define DMA_DEST_ADDR_MSB 31
-#define DMA_DEST_ADDR_LSB 2
-#define DMA_DEST_ADDR_MASK 0xfffffffc
-#define DMA_DEST_ADDR_GET(x) (((x) & DMA_DEST_ADDR_MASK) >> DMA_DEST_ADDR_LSB)
-#define DMA_DEST_ADDR_SET(x) (((x) << DMA_DEST_ADDR_LSB) & DMA_DEST_ADDR_MASK)
-
-#define DMA_LENGTH_ADDRESS 0x00000010
-#define DMA_LENGTH_OFFSET 0x00000010
-#define DMA_LENGTH_WORDS_MSB 11
-#define DMA_LENGTH_WORDS_LSB 0
-#define DMA_LENGTH_WORDS_MASK 0x00000fff
-#define DMA_LENGTH_WORDS_GET(x) (((x) & DMA_LENGTH_WORDS_MASK) >> DMA_LENGTH_WORDS_LSB)
-#define DMA_LENGTH_WORDS_SET(x) (((x) << DMA_LENGTH_WORDS_LSB) & DMA_LENGTH_WORDS_MASK)
-
-#define VMC_BASE_ADDRESS 0x00000014
-#define VMC_BASE_OFFSET 0x00000014
-#define VMC_BASE_ADDR_MSB 31
-#define VMC_BASE_ADDR_LSB 2
-#define VMC_BASE_ADDR_MASK 0xfffffffc
-#define VMC_BASE_ADDR_GET(x) (((x) & VMC_BASE_ADDR_MASK) >> VMC_BASE_ADDR_LSB)
-#define VMC_BASE_ADDR_SET(x) (((x) << VMC_BASE_ADDR_LSB) & VMC_BASE_ADDR_MASK)
-
-#define INDIRECT_REG_ADDRESS 0x00000018
-#define INDIRECT_REG_OFFSET 0x00000018
-#define INDIRECT_REG_ID_MSB 31
-#define INDIRECT_REG_ID_LSB 2
-#define INDIRECT_REG_ID_MASK 0xfffffffc
-#define INDIRECT_REG_ID_GET(x) (((x) & INDIRECT_REG_ID_MASK) >> INDIRECT_REG_ID_LSB)
-#define INDIRECT_REG_ID_SET(x) (((x) << INDIRECT_REG_ID_LSB) & INDIRECT_REG_ID_MASK)
-
-#define INDIRECT_RETURN_ADDRESS 0x0000001c
-#define INDIRECT_RETURN_OFFSET 0x0000001c
-#define INDIRECT_RETURN_ADDR_MSB 31
-#define INDIRECT_RETURN_ADDR_LSB 2
-#define INDIRECT_RETURN_ADDR_MASK 0xfffffffc
-#define INDIRECT_RETURN_ADDR_GET(x) (((x) & INDIRECT_RETURN_ADDR_MASK) >> INDIRECT_RETURN_ADDR_LSB)
-#define INDIRECT_RETURN_ADDR_SET(x) (((x) << INDIRECT_RETURN_ADDR_LSB) & INDIRECT_RETURN_ADDR_MASK)
-
-#define RDMA_REGION_0__ADDRESS 0x00000020
-#define RDMA_REGION_0__OFFSET 0x00000020
-#define RDMA_REGION_0__ADDR_MSB 31
-#define RDMA_REGION_0__ADDR_LSB 13
-#define RDMA_REGION_0__ADDR_MASK 0xffffe000
-#define RDMA_REGION_0__ADDR_GET(x) (((x) & RDMA_REGION_0__ADDR_MASK) >> RDMA_REGION_0__ADDR_LSB)
-#define RDMA_REGION_0__ADDR_SET(x) (((x) << RDMA_REGION_0__ADDR_LSB) & RDMA_REGION_0__ADDR_MASK)
-#define RDMA_REGION_0__LENGTH_MSB 12
-#define RDMA_REGION_0__LENGTH_LSB 2
-#define RDMA_REGION_0__LENGTH_MASK 0x00001ffc
-#define RDMA_REGION_0__LENGTH_GET(x) (((x) & RDMA_REGION_0__LENGTH_MASK) >> RDMA_REGION_0__LENGTH_LSB)
-#define RDMA_REGION_0__LENGTH_SET(x) (((x) << RDMA_REGION_0__LENGTH_LSB) & RDMA_REGION_0__LENGTH_MASK)
-#define RDMA_REGION_0__INDI_MSB 1
-#define RDMA_REGION_0__INDI_LSB 1
-#define RDMA_REGION_0__INDI_MASK 0x00000002
-#define RDMA_REGION_0__INDI_GET(x) (((x) & RDMA_REGION_0__INDI_MASK) >> RDMA_REGION_0__INDI_LSB)
-#define RDMA_REGION_0__INDI_SET(x) (((x) << RDMA_REGION_0__INDI_LSB) & RDMA_REGION_0__INDI_MASK)
-#define RDMA_REGION_0__NEXT_MSB 0
-#define RDMA_REGION_0__NEXT_LSB 0
-#define RDMA_REGION_0__NEXT_MASK 0x00000001
-#define RDMA_REGION_0__NEXT_GET(x) (((x) & RDMA_REGION_0__NEXT_MASK) >> RDMA_REGION_0__NEXT_LSB)
-#define RDMA_REGION_0__NEXT_SET(x) (((x) << RDMA_REGION_0__NEXT_LSB) & RDMA_REGION_0__NEXT_MASK)
-
-#define RDMA_REGION_1__ADDRESS 0x00000024
-#define RDMA_REGION_1__OFFSET 0x00000024
-#define RDMA_REGION_1__ADDR_MSB 31
-#define RDMA_REGION_1__ADDR_LSB 13
-#define RDMA_REGION_1__ADDR_MASK 0xffffe000
-#define RDMA_REGION_1__ADDR_GET(x) (((x) & RDMA_REGION_1__ADDR_MASK) >> RDMA_REGION_1__ADDR_LSB)
-#define RDMA_REGION_1__ADDR_SET(x) (((x) << RDMA_REGION_1__ADDR_LSB) & RDMA_REGION_1__ADDR_MASK)
-#define RDMA_REGION_1__LENGTH_MSB 12
-#define RDMA_REGION_1__LENGTH_LSB 2
-#define RDMA_REGION_1__LENGTH_MASK 0x00001ffc
-#define RDMA_REGION_1__LENGTH_GET(x) (((x) & RDMA_REGION_1__LENGTH_MASK) >> RDMA_REGION_1__LENGTH_LSB)
-#define RDMA_REGION_1__LENGTH_SET(x) (((x) << RDMA_REGION_1__LENGTH_LSB) & RDMA_REGION_1__LENGTH_MASK)
-#define RDMA_REGION_1__INDI_MSB 1
-#define RDMA_REGION_1__INDI_LSB 1
-#define RDMA_REGION_1__INDI_MASK 0x00000002
-#define RDMA_REGION_1__INDI_GET(x) (((x) & RDMA_REGION_1__INDI_MASK) >> RDMA_REGION_1__INDI_LSB)
-#define RDMA_REGION_1__INDI_SET(x) (((x) << RDMA_REGION_1__INDI_LSB) & RDMA_REGION_1__INDI_MASK)
-#define RDMA_REGION_1__NEXT_MSB 0
-#define RDMA_REGION_1__NEXT_LSB 0
-#define RDMA_REGION_1__NEXT_MASK 0x00000001
-#define RDMA_REGION_1__NEXT_GET(x) (((x) & RDMA_REGION_1__NEXT_MASK) >> RDMA_REGION_1__NEXT_LSB)
-#define RDMA_REGION_1__NEXT_SET(x) (((x) << RDMA_REGION_1__NEXT_LSB) & RDMA_REGION_1__NEXT_MASK)
-
-#define RDMA_REGION_2__ADDRESS 0x00000028
-#define RDMA_REGION_2__OFFSET 0x00000028
-#define RDMA_REGION_2__ADDR_MSB 31
-#define RDMA_REGION_2__ADDR_LSB 13
-#define RDMA_REGION_2__ADDR_MASK 0xffffe000
-#define RDMA_REGION_2__ADDR_GET(x) (((x) & RDMA_REGION_2__ADDR_MASK) >> RDMA_REGION_2__ADDR_LSB)
-#define RDMA_REGION_2__ADDR_SET(x) (((x) << RDMA_REGION_2__ADDR_LSB) & RDMA_REGION_2__ADDR_MASK)
-#define RDMA_REGION_2__LENGTH_MSB 12
-#define RDMA_REGION_2__LENGTH_LSB 2
-#define RDMA_REGION_2__LENGTH_MASK 0x00001ffc
-#define RDMA_REGION_2__LENGTH_GET(x) (((x) & RDMA_REGION_2__LENGTH_MASK) >> RDMA_REGION_2__LENGTH_LSB)
-#define RDMA_REGION_2__LENGTH_SET(x) (((x) << RDMA_REGION_2__LENGTH_LSB) & RDMA_REGION_2__LENGTH_MASK)
-#define RDMA_REGION_2__INDI_MSB 1
-#define RDMA_REGION_2__INDI_LSB 1
-#define RDMA_REGION_2__INDI_MASK 0x00000002
-#define RDMA_REGION_2__INDI_GET(x) (((x) & RDMA_REGION_2__INDI_MASK) >> RDMA_REGION_2__INDI_LSB)
-#define RDMA_REGION_2__INDI_SET(x) (((x) << RDMA_REGION_2__INDI_LSB) & RDMA_REGION_2__INDI_MASK)
-#define RDMA_REGION_2__NEXT_MSB 0
-#define RDMA_REGION_2__NEXT_LSB 0
-#define RDMA_REGION_2__NEXT_MASK 0x00000001
-#define RDMA_REGION_2__NEXT_GET(x) (((x) & RDMA_REGION_2__NEXT_MASK) >> RDMA_REGION_2__NEXT_LSB)
-#define RDMA_REGION_2__NEXT_SET(x) (((x) << RDMA_REGION_2__NEXT_LSB) & RDMA_REGION_2__NEXT_MASK)
-
-#define RDMA_REGION_3__ADDRESS 0x0000002c
-#define RDMA_REGION_3__OFFSET 0x0000002c
-#define RDMA_REGION_3__ADDR_MSB 31
-#define RDMA_REGION_3__ADDR_LSB 13
-#define RDMA_REGION_3__ADDR_MASK 0xffffe000
-#define RDMA_REGION_3__ADDR_GET(x) (((x) & RDMA_REGION_3__ADDR_MASK) >> RDMA_REGION_3__ADDR_LSB)
-#define RDMA_REGION_3__ADDR_SET(x) (((x) << RDMA_REGION_3__ADDR_LSB) & RDMA_REGION_3__ADDR_MASK)
-#define RDMA_REGION_3__LENGTH_MSB 12
-#define RDMA_REGION_3__LENGTH_LSB 2
-#define RDMA_REGION_3__LENGTH_MASK 0x00001ffc
-#define RDMA_REGION_3__LENGTH_GET(x) (((x) & RDMA_REGION_3__LENGTH_MASK) >> RDMA_REGION_3__LENGTH_LSB)
-#define RDMA_REGION_3__LENGTH_SET(x) (((x) << RDMA_REGION_3__LENGTH_LSB) & RDMA_REGION_3__LENGTH_MASK)
-#define RDMA_REGION_3__INDI_MSB 1
-#define RDMA_REGION_3__INDI_LSB 1
-#define RDMA_REGION_3__INDI_MASK 0x00000002
-#define RDMA_REGION_3__INDI_GET(x) (((x) & RDMA_REGION_3__INDI_MASK) >> RDMA_REGION_3__INDI_LSB)
-#define RDMA_REGION_3__INDI_SET(x) (((x) << RDMA_REGION_3__INDI_LSB) & RDMA_REGION_3__INDI_MASK)
-#define RDMA_REGION_3__NEXT_MSB 0
-#define RDMA_REGION_3__NEXT_LSB 0
-#define RDMA_REGION_3__NEXT_MASK 0x00000001
-#define RDMA_REGION_3__NEXT_GET(x) (((x) & RDMA_REGION_3__NEXT_MASK) >> RDMA_REGION_3__NEXT_LSB)
-#define RDMA_REGION_3__NEXT_SET(x) (((x) << RDMA_REGION_3__NEXT_LSB) & RDMA_REGION_3__NEXT_MASK)
-
-#define RDMA_REGION_4__ADDRESS 0x00000030
-#define RDMA_REGION_4__OFFSET 0x00000030
-#define RDMA_REGION_4__ADDR_MSB 31
-#define RDMA_REGION_4__ADDR_LSB 13
-#define RDMA_REGION_4__ADDR_MASK 0xffffe000
-#define RDMA_REGION_4__ADDR_GET(x) (((x) & RDMA_REGION_4__ADDR_MASK) >> RDMA_REGION_4__ADDR_LSB)
-#define RDMA_REGION_4__ADDR_SET(x) (((x) << RDMA_REGION_4__ADDR_LSB) & RDMA_REGION_4__ADDR_MASK)
-#define RDMA_REGION_4__LENGTH_MSB 12
-#define RDMA_REGION_4__LENGTH_LSB 2
-#define RDMA_REGION_4__LENGTH_MASK 0x00001ffc
-#define RDMA_REGION_4__LENGTH_GET(x) (((x) & RDMA_REGION_4__LENGTH_MASK) >> RDMA_REGION_4__LENGTH_LSB)
-#define RDMA_REGION_4__LENGTH_SET(x) (((x) << RDMA_REGION_4__LENGTH_LSB) & RDMA_REGION_4__LENGTH_MASK)
-#define RDMA_REGION_4__INDI_MSB 1
-#define RDMA_REGION_4__INDI_LSB 1
-#define RDMA_REGION_4__INDI_MASK 0x00000002
-#define RDMA_REGION_4__INDI_GET(x) (((x) & RDMA_REGION_4__INDI_MASK) >> RDMA_REGION_4__INDI_LSB)
-#define RDMA_REGION_4__INDI_SET(x) (((x) << RDMA_REGION_4__INDI_LSB) & RDMA_REGION_4__INDI_MASK)
-#define RDMA_REGION_4__NEXT_MSB 0
-#define RDMA_REGION_4__NEXT_LSB 0
-#define RDMA_REGION_4__NEXT_MASK 0x00000001
-#define RDMA_REGION_4__NEXT_GET(x) (((x) & RDMA_REGION_4__NEXT_MASK) >> RDMA_REGION_4__NEXT_LSB)
-#define RDMA_REGION_4__NEXT_SET(x) (((x) << RDMA_REGION_4__NEXT_LSB) & RDMA_REGION_4__NEXT_MASK)
-
-#define RDMA_REGION_5__ADDRESS 0x00000034
-#define RDMA_REGION_5__OFFSET 0x00000034
-#define RDMA_REGION_5__ADDR_MSB 31
-#define RDMA_REGION_5__ADDR_LSB 13
-#define RDMA_REGION_5__ADDR_MASK 0xffffe000
-#define RDMA_REGION_5__ADDR_GET(x) (((x) & RDMA_REGION_5__ADDR_MASK) >> RDMA_REGION_5__ADDR_LSB)
-#define RDMA_REGION_5__ADDR_SET(x) (((x) << RDMA_REGION_5__ADDR_LSB) & RDMA_REGION_5__ADDR_MASK)
-#define RDMA_REGION_5__LENGTH_MSB 12
-#define RDMA_REGION_5__LENGTH_LSB 2
-#define RDMA_REGION_5__LENGTH_MASK 0x00001ffc
-#define RDMA_REGION_5__LENGTH_GET(x) (((x) & RDMA_REGION_5__LENGTH_MASK) >> RDMA_REGION_5__LENGTH_LSB)
-#define RDMA_REGION_5__LENGTH_SET(x) (((x) << RDMA_REGION_5__LENGTH_LSB) & RDMA_REGION_5__LENGTH_MASK)
-#define RDMA_REGION_5__INDI_MSB 1
-#define RDMA_REGION_5__INDI_LSB 1
-#define RDMA_REGION_5__INDI_MASK 0x00000002
-#define RDMA_REGION_5__INDI_GET(x) (((x) & RDMA_REGION_5__INDI_MASK) >> RDMA_REGION_5__INDI_LSB)
-#define RDMA_REGION_5__INDI_SET(x) (((x) << RDMA_REGION_5__INDI_LSB) & RDMA_REGION_5__INDI_MASK)
-#define RDMA_REGION_5__NEXT_MSB 0
-#define RDMA_REGION_5__NEXT_LSB 0
-#define RDMA_REGION_5__NEXT_MASK 0x00000001
-#define RDMA_REGION_5__NEXT_GET(x) (((x) & RDMA_REGION_5__NEXT_MASK) >> RDMA_REGION_5__NEXT_LSB)
-#define RDMA_REGION_5__NEXT_SET(x) (((x) << RDMA_REGION_5__NEXT_LSB) & RDMA_REGION_5__NEXT_MASK)
-
-#define RDMA_REGION_6__ADDRESS 0x00000038
-#define RDMA_REGION_6__OFFSET 0x00000038
-#define RDMA_REGION_6__ADDR_MSB 31
-#define RDMA_REGION_6__ADDR_LSB 13
-#define RDMA_REGION_6__ADDR_MASK 0xffffe000
-#define RDMA_REGION_6__ADDR_GET(x) (((x) & RDMA_REGION_6__ADDR_MASK) >> RDMA_REGION_6__ADDR_LSB)
-#define RDMA_REGION_6__ADDR_SET(x) (((x) << RDMA_REGION_6__ADDR_LSB) & RDMA_REGION_6__ADDR_MASK)
-#define RDMA_REGION_6__LENGTH_MSB 12
-#define RDMA_REGION_6__LENGTH_LSB 2
-#define RDMA_REGION_6__LENGTH_MASK 0x00001ffc
-#define RDMA_REGION_6__LENGTH_GET(x) (((x) & RDMA_REGION_6__LENGTH_MASK) >> RDMA_REGION_6__LENGTH_LSB)
-#define RDMA_REGION_6__LENGTH_SET(x) (((x) << RDMA_REGION_6__LENGTH_LSB) & RDMA_REGION_6__LENGTH_MASK)
-#define RDMA_REGION_6__INDI_MSB 1
-#define RDMA_REGION_6__INDI_LSB 1
-#define RDMA_REGION_6__INDI_MASK 0x00000002
-#define RDMA_REGION_6__INDI_GET(x) (((x) & RDMA_REGION_6__INDI_MASK) >> RDMA_REGION_6__INDI_LSB)
-#define RDMA_REGION_6__INDI_SET(x) (((x) << RDMA_REGION_6__INDI_LSB) & RDMA_REGION_6__INDI_MASK)
-#define RDMA_REGION_6__NEXT_MSB 0
-#define RDMA_REGION_6__NEXT_LSB 0
-#define RDMA_REGION_6__NEXT_MASK 0x00000001
-#define RDMA_REGION_6__NEXT_GET(x) (((x) & RDMA_REGION_6__NEXT_MASK) >> RDMA_REGION_6__NEXT_LSB)
-#define RDMA_REGION_6__NEXT_SET(x) (((x) << RDMA_REGION_6__NEXT_LSB) & RDMA_REGION_6__NEXT_MASK)
-
-#define RDMA_REGION_7__ADDRESS 0x0000003c
-#define RDMA_REGION_7__OFFSET 0x0000003c
-#define RDMA_REGION_7__ADDR_MSB 31
-#define RDMA_REGION_7__ADDR_LSB 13
-#define RDMA_REGION_7__ADDR_MASK 0xffffe000
-#define RDMA_REGION_7__ADDR_GET(x) (((x) & RDMA_REGION_7__ADDR_MASK) >> RDMA_REGION_7__ADDR_LSB)
-#define RDMA_REGION_7__ADDR_SET(x) (((x) << RDMA_REGION_7__ADDR_LSB) & RDMA_REGION_7__ADDR_MASK)
-#define RDMA_REGION_7__LENGTH_MSB 12
-#define RDMA_REGION_7__LENGTH_LSB 2
-#define RDMA_REGION_7__LENGTH_MASK 0x00001ffc
-#define RDMA_REGION_7__LENGTH_GET(x) (((x) & RDMA_REGION_7__LENGTH_MASK) >> RDMA_REGION_7__LENGTH_LSB)
-#define RDMA_REGION_7__LENGTH_SET(x) (((x) << RDMA_REGION_7__LENGTH_LSB) & RDMA_REGION_7__LENGTH_MASK)
-#define RDMA_REGION_7__INDI_MSB 1
-#define RDMA_REGION_7__INDI_LSB 1
-#define RDMA_REGION_7__INDI_MASK 0x00000002
-#define RDMA_REGION_7__INDI_GET(x) (((x) & RDMA_REGION_7__INDI_MASK) >> RDMA_REGION_7__INDI_LSB)
-#define RDMA_REGION_7__INDI_SET(x) (((x) << RDMA_REGION_7__INDI_LSB) & RDMA_REGION_7__INDI_MASK)
-#define RDMA_REGION_7__NEXT_MSB 0
-#define RDMA_REGION_7__NEXT_LSB 0
-#define RDMA_REGION_7__NEXT_MASK 0x00000001
-#define RDMA_REGION_7__NEXT_GET(x) (((x) & RDMA_REGION_7__NEXT_MASK) >> RDMA_REGION_7__NEXT_LSB)
-#define RDMA_REGION_7__NEXT_SET(x) (((x) << RDMA_REGION_7__NEXT_LSB) & RDMA_REGION_7__NEXT_MASK)
-
-#define RDMA_REGION_8__ADDRESS 0x00000040
-#define RDMA_REGION_8__OFFSET 0x00000040
-#define RDMA_REGION_8__ADDR_MSB 31
-#define RDMA_REGION_8__ADDR_LSB 13
-#define RDMA_REGION_8__ADDR_MASK 0xffffe000
-#define RDMA_REGION_8__ADDR_GET(x) (((x) & RDMA_REGION_8__ADDR_MASK) >> RDMA_REGION_8__ADDR_LSB)
-#define RDMA_REGION_8__ADDR_SET(x) (((x) << RDMA_REGION_8__ADDR_LSB) & RDMA_REGION_8__ADDR_MASK)
-#define RDMA_REGION_8__LENGTH_MSB 12
-#define RDMA_REGION_8__LENGTH_LSB 2
-#define RDMA_REGION_8__LENGTH_MASK 0x00001ffc
-#define RDMA_REGION_8__LENGTH_GET(x) (((x) & RDMA_REGION_8__LENGTH_MASK) >> RDMA_REGION_8__LENGTH_LSB)
-#define RDMA_REGION_8__LENGTH_SET(x) (((x) << RDMA_REGION_8__LENGTH_LSB) & RDMA_REGION_8__LENGTH_MASK)
-#define RDMA_REGION_8__INDI_MSB 1
-#define RDMA_REGION_8__INDI_LSB 1
-#define RDMA_REGION_8__INDI_MASK 0x00000002
-#define RDMA_REGION_8__INDI_GET(x) (((x) & RDMA_REGION_8__INDI_MASK) >> RDMA_REGION_8__INDI_LSB)
-#define RDMA_REGION_8__INDI_SET(x) (((x) << RDMA_REGION_8__INDI_LSB) & RDMA_REGION_8__INDI_MASK)
-#define RDMA_REGION_8__NEXT_MSB 0
-#define RDMA_REGION_8__NEXT_LSB 0
-#define RDMA_REGION_8__NEXT_MASK 0x00000001
-#define RDMA_REGION_8__NEXT_GET(x) (((x) & RDMA_REGION_8__NEXT_MASK) >> RDMA_REGION_8__NEXT_LSB)
-#define RDMA_REGION_8__NEXT_SET(x) (((x) << RDMA_REGION_8__NEXT_LSB) & RDMA_REGION_8__NEXT_MASK)
-
-#define RDMA_REGION_9__ADDRESS 0x00000044
-#define RDMA_REGION_9__OFFSET 0x00000044
-#define RDMA_REGION_9__ADDR_MSB 31
-#define RDMA_REGION_9__ADDR_LSB 13
-#define RDMA_REGION_9__ADDR_MASK 0xffffe000
-#define RDMA_REGION_9__ADDR_GET(x) (((x) & RDMA_REGION_9__ADDR_MASK) >> RDMA_REGION_9__ADDR_LSB)
-#define RDMA_REGION_9__ADDR_SET(x) (((x) << RDMA_REGION_9__ADDR_LSB) & RDMA_REGION_9__ADDR_MASK)
-#define RDMA_REGION_9__LENGTH_MSB 12
-#define RDMA_REGION_9__LENGTH_LSB 2
-#define RDMA_REGION_9__LENGTH_MASK 0x00001ffc
-#define RDMA_REGION_9__LENGTH_GET(x) (((x) & RDMA_REGION_9__LENGTH_MASK) >> RDMA_REGION_9__LENGTH_LSB)
-#define RDMA_REGION_9__LENGTH_SET(x) (((x) << RDMA_REGION_9__LENGTH_LSB) & RDMA_REGION_9__LENGTH_MASK)
-#define RDMA_REGION_9__INDI_MSB 1
-#define RDMA_REGION_9__INDI_LSB 1
-#define RDMA_REGION_9__INDI_MASK 0x00000002
-#define RDMA_REGION_9__INDI_GET(x) (((x) & RDMA_REGION_9__INDI_MASK) >> RDMA_REGION_9__INDI_LSB)
-#define RDMA_REGION_9__INDI_SET(x) (((x) << RDMA_REGION_9__INDI_LSB) & RDMA_REGION_9__INDI_MASK)
-#define RDMA_REGION_9__NEXT_MSB 0
-#define RDMA_REGION_9__NEXT_LSB 0
-#define RDMA_REGION_9__NEXT_MASK 0x00000001
-#define RDMA_REGION_9__NEXT_GET(x) (((x) & RDMA_REGION_9__NEXT_MASK) >> RDMA_REGION_9__NEXT_LSB)
-#define RDMA_REGION_9__NEXT_SET(x) (((x) << RDMA_REGION_9__NEXT_LSB) & RDMA_REGION_9__NEXT_MASK)
-
-#define RDMA_REGION_10__ADDRESS 0x00000048
-#define RDMA_REGION_10__OFFSET 0x00000048
-#define RDMA_REGION_10__ADDR_MSB 31
-#define RDMA_REGION_10__ADDR_LSB 13
-#define RDMA_REGION_10__ADDR_MASK 0xffffe000
-#define RDMA_REGION_10__ADDR_GET(x) (((x) & RDMA_REGION_10__ADDR_MASK) >> RDMA_REGION_10__ADDR_LSB)
-#define RDMA_REGION_10__ADDR_SET(x) (((x) << RDMA_REGION_10__ADDR_LSB) & RDMA_REGION_10__ADDR_MASK)
-#define RDMA_REGION_10__LENGTH_MSB 12
-#define RDMA_REGION_10__LENGTH_LSB 2
-#define RDMA_REGION_10__LENGTH_MASK 0x00001ffc
-#define RDMA_REGION_10__LENGTH_GET(x) (((x) & RDMA_REGION_10__LENGTH_MASK) >> RDMA_REGION_10__LENGTH_LSB)
-#define RDMA_REGION_10__LENGTH_SET(x) (((x) << RDMA_REGION_10__LENGTH_LSB) & RDMA_REGION_10__LENGTH_MASK)
-#define RDMA_REGION_10__INDI_MSB 1
-#define RDMA_REGION_10__INDI_LSB 1
-#define RDMA_REGION_10__INDI_MASK 0x00000002
-#define RDMA_REGION_10__INDI_GET(x) (((x) & RDMA_REGION_10__INDI_MASK) >> RDMA_REGION_10__INDI_LSB)
-#define RDMA_REGION_10__INDI_SET(x) (((x) << RDMA_REGION_10__INDI_LSB) & RDMA_REGION_10__INDI_MASK)
-#define RDMA_REGION_10__NEXT_MSB 0
-#define RDMA_REGION_10__NEXT_LSB 0
-#define RDMA_REGION_10__NEXT_MASK 0x00000001
-#define RDMA_REGION_10__NEXT_GET(x) (((x) & RDMA_REGION_10__NEXT_MASK) >> RDMA_REGION_10__NEXT_LSB)
-#define RDMA_REGION_10__NEXT_SET(x) (((x) << RDMA_REGION_10__NEXT_LSB) & RDMA_REGION_10__NEXT_MASK)
-
-#define RDMA_REGION_11__ADDRESS 0x0000004c
-#define RDMA_REGION_11__OFFSET 0x0000004c
-#define RDMA_REGION_11__ADDR_MSB 31
-#define RDMA_REGION_11__ADDR_LSB 13
-#define RDMA_REGION_11__ADDR_MASK 0xffffe000
-#define RDMA_REGION_11__ADDR_GET(x) (((x) & RDMA_REGION_11__ADDR_MASK) >> RDMA_REGION_11__ADDR_LSB)
-#define RDMA_REGION_11__ADDR_SET(x) (((x) << RDMA_REGION_11__ADDR_LSB) & RDMA_REGION_11__ADDR_MASK)
-#define RDMA_REGION_11__LENGTH_MSB 12
-#define RDMA_REGION_11__LENGTH_LSB 2
-#define RDMA_REGION_11__LENGTH_MASK 0x00001ffc
-#define RDMA_REGION_11__LENGTH_GET(x) (((x) & RDMA_REGION_11__LENGTH_MASK) >> RDMA_REGION_11__LENGTH_LSB)
-#define RDMA_REGION_11__LENGTH_SET(x) (((x) << RDMA_REGION_11__LENGTH_LSB) & RDMA_REGION_11__LENGTH_MASK)
-#define RDMA_REGION_11__INDI_MSB 1
-#define RDMA_REGION_11__INDI_LSB 1
-#define RDMA_REGION_11__INDI_MASK 0x00000002
-#define RDMA_REGION_11__INDI_GET(x) (((x) & RDMA_REGION_11__INDI_MASK) >> RDMA_REGION_11__INDI_LSB)
-#define RDMA_REGION_11__INDI_SET(x) (((x) << RDMA_REGION_11__INDI_LSB) & RDMA_REGION_11__INDI_MASK)
-#define RDMA_REGION_11__NEXT_MSB 0
-#define RDMA_REGION_11__NEXT_LSB 0
-#define RDMA_REGION_11__NEXT_MASK 0x00000001
-#define RDMA_REGION_11__NEXT_GET(x) (((x) & RDMA_REGION_11__NEXT_MASK) >> RDMA_REGION_11__NEXT_LSB)
-#define RDMA_REGION_11__NEXT_SET(x) (((x) << RDMA_REGION_11__NEXT_LSB) & RDMA_REGION_11__NEXT_MASK)
-
-#define RDMA_REGION_12__ADDRESS 0x00000050
-#define RDMA_REGION_12__OFFSET 0x00000050
-#define RDMA_REGION_12__ADDR_MSB 31
-#define RDMA_REGION_12__ADDR_LSB 13
-#define RDMA_REGION_12__ADDR_MASK 0xffffe000
-#define RDMA_REGION_12__ADDR_GET(x) (((x) & RDMA_REGION_12__ADDR_MASK) >> RDMA_REGION_12__ADDR_LSB)
-#define RDMA_REGION_12__ADDR_SET(x) (((x) << RDMA_REGION_12__ADDR_LSB) & RDMA_REGION_12__ADDR_MASK)
-#define RDMA_REGION_12__LENGTH_MSB 12
-#define RDMA_REGION_12__LENGTH_LSB 2
-#define RDMA_REGION_12__LENGTH_MASK 0x00001ffc
-#define RDMA_REGION_12__LENGTH_GET(x) (((x) & RDMA_REGION_12__LENGTH_MASK) >> RDMA_REGION_12__LENGTH_LSB)
-#define RDMA_REGION_12__LENGTH_SET(x) (((x) << RDMA_REGION_12__LENGTH_LSB) & RDMA_REGION_12__LENGTH_MASK)
-#define RDMA_REGION_12__INDI_MSB 1
-#define RDMA_REGION_12__INDI_LSB 1
-#define RDMA_REGION_12__INDI_MASK 0x00000002
-#define RDMA_REGION_12__INDI_GET(x) (((x) & RDMA_REGION_12__INDI_MASK) >> RDMA_REGION_12__INDI_LSB)
-#define RDMA_REGION_12__INDI_SET(x) (((x) << RDMA_REGION_12__INDI_LSB) & RDMA_REGION_12__INDI_MASK)
-#define RDMA_REGION_12__NEXT_MSB 0
-#define RDMA_REGION_12__NEXT_LSB 0
-#define RDMA_REGION_12__NEXT_MASK 0x00000001
-#define RDMA_REGION_12__NEXT_GET(x) (((x) & RDMA_REGION_12__NEXT_MASK) >> RDMA_REGION_12__NEXT_LSB)
-#define RDMA_REGION_12__NEXT_SET(x) (((x) << RDMA_REGION_12__NEXT_LSB) & RDMA_REGION_12__NEXT_MASK)
-
-#define RDMA_REGION_13__ADDRESS 0x00000054
-#define RDMA_REGION_13__OFFSET 0x00000054
-#define RDMA_REGION_13__ADDR_MSB 31
-#define RDMA_REGION_13__ADDR_LSB 13
-#define RDMA_REGION_13__ADDR_MASK 0xffffe000
-#define RDMA_REGION_13__ADDR_GET(x) (((x) & RDMA_REGION_13__ADDR_MASK) >> RDMA_REGION_13__ADDR_LSB)
-#define RDMA_REGION_13__ADDR_SET(x) (((x) << RDMA_REGION_13__ADDR_LSB) & RDMA_REGION_13__ADDR_MASK)
-#define RDMA_REGION_13__LENGTH_MSB 12
-#define RDMA_REGION_13__LENGTH_LSB 2
-#define RDMA_REGION_13__LENGTH_MASK 0x00001ffc
-#define RDMA_REGION_13__LENGTH_GET(x) (((x) & RDMA_REGION_13__LENGTH_MASK) >> RDMA_REGION_13__LENGTH_LSB)
-#define RDMA_REGION_13__LENGTH_SET(x) (((x) << RDMA_REGION_13__LENGTH_LSB) & RDMA_REGION_13__LENGTH_MASK)
-#define RDMA_REGION_13__INDI_MSB 1
-#define RDMA_REGION_13__INDI_LSB 1
-#define RDMA_REGION_13__INDI_MASK 0x00000002
-#define RDMA_REGION_13__INDI_GET(x) (((x) & RDMA_REGION_13__INDI_MASK) >> RDMA_REGION_13__INDI_LSB)
-#define RDMA_REGION_13__INDI_SET(x) (((x) << RDMA_REGION_13__INDI_LSB) & RDMA_REGION_13__INDI_MASK)
-#define RDMA_REGION_13__NEXT_MSB 0
-#define RDMA_REGION_13__NEXT_LSB 0
-#define RDMA_REGION_13__NEXT_MASK 0x00000001
-#define RDMA_REGION_13__NEXT_GET(x) (((x) & RDMA_REGION_13__NEXT_MASK) >> RDMA_REGION_13__NEXT_LSB)
-#define RDMA_REGION_13__NEXT_SET(x) (((x) << RDMA_REGION_13__NEXT_LSB) & RDMA_REGION_13__NEXT_MASK)
-
-#define RDMA_REGION_14__ADDRESS 0x00000058
-#define RDMA_REGION_14__OFFSET 0x00000058
-#define RDMA_REGION_14__ADDR_MSB 31
-#define RDMA_REGION_14__ADDR_LSB 13
-#define RDMA_REGION_14__ADDR_MASK 0xffffe000
-#define RDMA_REGION_14__ADDR_GET(x) (((x) & RDMA_REGION_14__ADDR_MASK) >> RDMA_REGION_14__ADDR_LSB)
-#define RDMA_REGION_14__ADDR_SET(x) (((x) << RDMA_REGION_14__ADDR_LSB) & RDMA_REGION_14__ADDR_MASK)
-#define RDMA_REGION_14__LENGTH_MSB 12
-#define RDMA_REGION_14__LENGTH_LSB 2
-#define RDMA_REGION_14__LENGTH_MASK 0x00001ffc
-#define RDMA_REGION_14__LENGTH_GET(x) (((x) & RDMA_REGION_14__LENGTH_MASK) >> RDMA_REGION_14__LENGTH_LSB)
-#define RDMA_REGION_14__LENGTH_SET(x) (((x) << RDMA_REGION_14__LENGTH_LSB) & RDMA_REGION_14__LENGTH_MASK)
-#define RDMA_REGION_14__INDI_MSB 1
-#define RDMA_REGION_14__INDI_LSB 1
-#define RDMA_REGION_14__INDI_MASK 0x00000002
-#define RDMA_REGION_14__INDI_GET(x) (((x) & RDMA_REGION_14__INDI_MASK) >> RDMA_REGION_14__INDI_LSB)
-#define RDMA_REGION_14__INDI_SET(x) (((x) << RDMA_REGION_14__INDI_LSB) & RDMA_REGION_14__INDI_MASK)
-#define RDMA_REGION_14__NEXT_MSB 0
-#define RDMA_REGION_14__NEXT_LSB 0
-#define RDMA_REGION_14__NEXT_MASK 0x00000001
-#define RDMA_REGION_14__NEXT_GET(x) (((x) & RDMA_REGION_14__NEXT_MASK) >> RDMA_REGION_14__NEXT_LSB)
-#define RDMA_REGION_14__NEXT_SET(x) (((x) << RDMA_REGION_14__NEXT_LSB) & RDMA_REGION_14__NEXT_MASK)
-
-#define RDMA_REGION_15__ADDRESS 0x0000005c
-#define RDMA_REGION_15__OFFSET 0x0000005c
-#define RDMA_REGION_15__ADDR_MSB 31
-#define RDMA_REGION_15__ADDR_LSB 13
-#define RDMA_REGION_15__ADDR_MASK 0xffffe000
-#define RDMA_REGION_15__ADDR_GET(x) (((x) & RDMA_REGION_15__ADDR_MASK) >> RDMA_REGION_15__ADDR_LSB)
-#define RDMA_REGION_15__ADDR_SET(x) (((x) << RDMA_REGION_15__ADDR_LSB) & RDMA_REGION_15__ADDR_MASK)
-#define RDMA_REGION_15__LENGTH_MSB 12
-#define RDMA_REGION_15__LENGTH_LSB 2
-#define RDMA_REGION_15__LENGTH_MASK 0x00001ffc
-#define RDMA_REGION_15__LENGTH_GET(x) (((x) & RDMA_REGION_15__LENGTH_MASK) >> RDMA_REGION_15__LENGTH_LSB)
-#define RDMA_REGION_15__LENGTH_SET(x) (((x) << RDMA_REGION_15__LENGTH_LSB) & RDMA_REGION_15__LENGTH_MASK)
-#define RDMA_REGION_15__INDI_MSB 1
-#define RDMA_REGION_15__INDI_LSB 1
-#define RDMA_REGION_15__INDI_MASK 0x00000002
-#define RDMA_REGION_15__INDI_GET(x) (((x) & RDMA_REGION_15__INDI_MASK) >> RDMA_REGION_15__INDI_LSB)
-#define RDMA_REGION_15__INDI_SET(x) (((x) << RDMA_REGION_15__INDI_LSB) & RDMA_REGION_15__INDI_MASK)
-#define RDMA_REGION_15__NEXT_MSB 0
-#define RDMA_REGION_15__NEXT_LSB 0
-#define RDMA_REGION_15__NEXT_MASK 0x00000001
-#define RDMA_REGION_15__NEXT_GET(x) (((x) & RDMA_REGION_15__NEXT_MASK) >> RDMA_REGION_15__NEXT_LSB)
-#define RDMA_REGION_15__NEXT_SET(x) (((x) << RDMA_REGION_15__NEXT_LSB) & RDMA_REGION_15__NEXT_MASK)
-
-#define DMA_STATUS_ADDRESS 0x00000060
-#define DMA_STATUS_OFFSET 0x00000060
-#define DMA_STATUS_ERROR_CODE_MSB 14
-#define DMA_STATUS_ERROR_CODE_LSB 4
-#define DMA_STATUS_ERROR_CODE_MASK 0x00007ff0
-#define DMA_STATUS_ERROR_CODE_GET(x) (((x) & DMA_STATUS_ERROR_CODE_MASK) >> DMA_STATUS_ERROR_CODE_LSB)
-#define DMA_STATUS_ERROR_CODE_SET(x) (((x) << DMA_STATUS_ERROR_CODE_LSB) & DMA_STATUS_ERROR_CODE_MASK)
-#define DMA_STATUS_ERROR_MSB 3
-#define DMA_STATUS_ERROR_LSB 3
-#define DMA_STATUS_ERROR_MASK 0x00000008
-#define DMA_STATUS_ERROR_GET(x) (((x) & DMA_STATUS_ERROR_MASK) >> DMA_STATUS_ERROR_LSB)
-#define DMA_STATUS_ERROR_SET(x) (((x) << DMA_STATUS_ERROR_LSB) & DMA_STATUS_ERROR_MASK)
-#define DMA_STATUS_DONE_MSB 2
-#define DMA_STATUS_DONE_LSB 2
-#define DMA_STATUS_DONE_MASK 0x00000004
-#define DMA_STATUS_DONE_GET(x) (((x) & DMA_STATUS_DONE_MASK) >> DMA_STATUS_DONE_LSB)
-#define DMA_STATUS_DONE_SET(x) (((x) << DMA_STATUS_DONE_LSB) & DMA_STATUS_DONE_MASK)
-#define DMA_STATUS_STOPPED_MSB 1
-#define DMA_STATUS_STOPPED_LSB 1
-#define DMA_STATUS_STOPPED_MASK 0x00000002
-#define DMA_STATUS_STOPPED_GET(x) (((x) & DMA_STATUS_STOPPED_MASK) >> DMA_STATUS_STOPPED_LSB)
-#define DMA_STATUS_STOPPED_SET(x) (((x) << DMA_STATUS_STOPPED_LSB) & DMA_STATUS_STOPPED_MASK)
-#define DMA_STATUS_RUNNING_MSB 0
-#define DMA_STATUS_RUNNING_LSB 0
-#define DMA_STATUS_RUNNING_MASK 0x00000001
-#define DMA_STATUS_RUNNING_GET(x) (((x) & DMA_STATUS_RUNNING_MASK) >> DMA_STATUS_RUNNING_LSB)
-#define DMA_STATUS_RUNNING_SET(x) (((x) << DMA_STATUS_RUNNING_LSB) & DMA_STATUS_RUNNING_MASK)
-
-#define DMA_INT_EN_ADDRESS 0x00000064
-#define DMA_INT_EN_OFFSET 0x00000064
-#define DMA_INT_EN_ERROR_ENA_MSB 3
-#define DMA_INT_EN_ERROR_ENA_LSB 3
-#define DMA_INT_EN_ERROR_ENA_MASK 0x00000008
-#define DMA_INT_EN_ERROR_ENA_GET(x) (((x) & DMA_INT_EN_ERROR_ENA_MASK) >> DMA_INT_EN_ERROR_ENA_LSB)
-#define DMA_INT_EN_ERROR_ENA_SET(x) (((x) << DMA_INT_EN_ERROR_ENA_LSB) & DMA_INT_EN_ERROR_ENA_MASK)
-#define DMA_INT_EN_DONE_ENA_MSB 2
-#define DMA_INT_EN_DONE_ENA_LSB 2
-#define DMA_INT_EN_DONE_ENA_MASK 0x00000004
-#define DMA_INT_EN_DONE_ENA_GET(x) (((x) & DMA_INT_EN_DONE_ENA_MASK) >> DMA_INT_EN_DONE_ENA_LSB)
-#define DMA_INT_EN_DONE_ENA_SET(x) (((x) << DMA_INT_EN_DONE_ENA_LSB) & DMA_INT_EN_DONE_ENA_MASK)
-#define DMA_INT_EN_STOPPED_ENA_MSB 1
-#define DMA_INT_EN_STOPPED_ENA_LSB 1
-#define DMA_INT_EN_STOPPED_ENA_MASK 0x00000002
-#define DMA_INT_EN_STOPPED_ENA_GET(x) (((x) & DMA_INT_EN_STOPPED_ENA_MASK) >> DMA_INT_EN_STOPPED_ENA_LSB)
-#define DMA_INT_EN_STOPPED_ENA_SET(x) (((x) << DMA_INT_EN_STOPPED_ENA_LSB) & DMA_INT_EN_STOPPED_ENA_MASK)
-
-
-#ifndef __ASSEMBLER__
-
-typedef struct rdma_reg_reg_s {
- volatile unsigned int dma_config;
- volatile unsigned int dma_control;
- volatile unsigned int dma_src;
- volatile unsigned int dma_dest;
- volatile unsigned int dma_length;
- volatile unsigned int vmc_base;
- volatile unsigned int indirect_reg;
- volatile unsigned int indirect_return;
- volatile unsigned int rdma_region_0_;
- volatile unsigned int rdma_region_1_;
- volatile unsigned int rdma_region_2_;
- volatile unsigned int rdma_region_3_;
- volatile unsigned int rdma_region_4_;
- volatile unsigned int rdma_region_5_;
- volatile unsigned int rdma_region_6_;
- volatile unsigned int rdma_region_7_;
- volatile unsigned int rdma_region_8_;
- volatile unsigned int rdma_region_9_;
- volatile unsigned int rdma_region_10_;
- volatile unsigned int rdma_region_11_;
- volatile unsigned int rdma_region_12_;
- volatile unsigned int rdma_region_13_;
- volatile unsigned int rdma_region_14_;
- volatile unsigned int rdma_region_15_;
- volatile unsigned int dma_status;
- volatile unsigned int dma_int_en;
-} rdma_reg_reg_t;
-
-#endif /* __ASSEMBLER__ */
-
-#endif /* _RDMA_REG_H_ */
diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/rtc_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/rtc_reg.h
index 0855de5..fcafec8 100644
--- a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/rtc_reg.h
+++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/rtc_reg.h
@@ -21,11 +21,8 @@
//===================================================================
-#ifdef WLAN_HEADERS
-
#include "rtc_wlan_reg.h"
-
#ifndef BT_HEADERS
#define RESET_CONTROL_ADDRESS WLAN_RESET_CONTROL_ADDRESS
@@ -100,95 +97,6 @@
#define RESET_CONTROL_SI0_RST_MASK WLAN_RESET_CONTROL_SI0_RST_MASK
#define RESET_CONTROL_SI0_RST_GET(x) WLAN_RESET_CONTROL_SI0_RST_GET(x)
#define RESET_CONTROL_SI0_RST_SET(x) WLAN_RESET_CONTROL_SI0_RST_SET(x)
-#define XTAL_CONTROL_ADDRESS WLAN_XTAL_CONTROL_ADDRESS
-#define XTAL_CONTROL_OFFSET WLAN_XTAL_CONTROL_OFFSET
-#define XTAL_CONTROL_TCXO_MSB WLAN_XTAL_CONTROL_TCXO_MSB
-#define XTAL_CONTROL_TCXO_LSB WLAN_XTAL_CONTROL_TCXO_LSB
-#define XTAL_CONTROL_TCXO_MASK WLAN_XTAL_CONTROL_TCXO_MASK
-#define XTAL_CONTROL_TCXO_GET(x) WLAN_XTAL_CONTROL_TCXO_GET(x)
-#define XTAL_CONTROL_TCXO_SET(x) WLAN_XTAL_CONTROL_TCXO_SET(x)
-#define TCXO_DETECT_ADDRESS WLAN_TCXO_DETECT_ADDRESS
-#define TCXO_DETECT_OFFSET WLAN_TCXO_DETECT_OFFSET
-#define TCXO_DETECT_PRESENT_MSB WLAN_TCXO_DETECT_PRESENT_MSB
-#define TCXO_DETECT_PRESENT_LSB WLAN_TCXO_DETECT_PRESENT_LSB
-#define TCXO_DETECT_PRESENT_MASK WLAN_TCXO_DETECT_PRESENT_MASK
-#define TCXO_DETECT_PRESENT_GET(x) WLAN_TCXO_DETECT_PRESENT_GET(x)
-#define TCXO_DETECT_PRESENT_SET(x) WLAN_TCXO_DETECT_PRESENT_SET(x)
-#define XTAL_TEST_ADDRESS WLAN_XTAL_TEST_ADDRESS
-#define XTAL_TEST_OFFSET WLAN_XTAL_TEST_OFFSET
-#define XTAL_TEST_NOTCXODET_MSB WLAN_XTAL_TEST_NOTCXODET_MSB
-#define XTAL_TEST_NOTCXODET_LSB WLAN_XTAL_TEST_NOTCXODET_LSB
-#define XTAL_TEST_NOTCXODET_MASK WLAN_XTAL_TEST_NOTCXODET_MASK
-#define XTAL_TEST_NOTCXODET_GET(x) WLAN_XTAL_TEST_NOTCXODET_GET(x)
-#define XTAL_TEST_NOTCXODET_SET(x) WLAN_XTAL_TEST_NOTCXODET_SET(x)
-#define QUADRATURE_ADDRESS WLAN_QUADRATURE_ADDRESS
-#define QUADRATURE_OFFSET WLAN_QUADRATURE_OFFSET
-#define QUADRATURE_ADC_MSB WLAN_QUADRATURE_ADC_MSB
-#define QUADRATURE_ADC_LSB WLAN_QUADRATURE_ADC_LSB
-#define QUADRATURE_ADC_MASK WLAN_QUADRATURE_ADC_MASK
-#define QUADRATURE_ADC_GET(x) WLAN_QUADRATURE_ADC_GET(x)
-#define QUADRATURE_ADC_SET(x) WLAN_QUADRATURE_ADC_SET(x)
-#define QUADRATURE_SEL_MSB WLAN_QUADRATURE_SEL_MSB
-#define QUADRATURE_SEL_LSB WLAN_QUADRATURE_SEL_LSB
-#define QUADRATURE_SEL_MASK WLAN_QUADRATURE_SEL_MASK
-#define QUADRATURE_SEL_GET(x) WLAN_QUADRATURE_SEL_GET(x)
-#define QUADRATURE_SEL_SET(x) WLAN_QUADRATURE_SEL_SET(x)
-#define QUADRATURE_DAC_MSB WLAN_QUADRATURE_DAC_MSB
-#define QUADRATURE_DAC_LSB WLAN_QUADRATURE_DAC_LSB
-#define QUADRATURE_DAC_MASK WLAN_QUADRATURE_DAC_MASK
-#define QUADRATURE_DAC_GET(x) WLAN_QUADRATURE_DAC_GET(x)
-#define QUADRATURE_DAC_SET(x) WLAN_QUADRATURE_DAC_SET(x)
-#define PLL_CONTROL_ADDRESS WLAN_PLL_CONTROL_ADDRESS
-#define PLL_CONTROL_OFFSET WLAN_PLL_CONTROL_OFFSET
-#define PLL_CONTROL_DIG_TEST_CLK_MSB WLAN_PLL_CONTROL_DIG_TEST_CLK_MSB
-#define PLL_CONTROL_DIG_TEST_CLK_LSB WLAN_PLL_CONTROL_DIG_TEST_CLK_LSB
-#define PLL_CONTROL_DIG_TEST_CLK_MASK WLAN_PLL_CONTROL_DIG_TEST_CLK_MASK
-#define PLL_CONTROL_DIG_TEST_CLK_GET(x) WLAN_PLL_CONTROL_DIG_TEST_CLK_GET(x)
-#define PLL_CONTROL_DIG_TEST_CLK_SET(x) WLAN_PLL_CONTROL_DIG_TEST_CLK_SET(x)
-#define PLL_CONTROL_MAC_OVERRIDE_MSB WLAN_PLL_CONTROL_MAC_OVERRIDE_MSB
-#define PLL_CONTROL_MAC_OVERRIDE_LSB WLAN_PLL_CONTROL_MAC_OVERRIDE_LSB
-#define PLL_CONTROL_MAC_OVERRIDE_MASK WLAN_PLL_CONTROL_MAC_OVERRIDE_MASK
-#define PLL_CONTROL_MAC_OVERRIDE_GET(x) WLAN_PLL_CONTROL_MAC_OVERRIDE_GET(x)
-#define PLL_CONTROL_MAC_OVERRIDE_SET(x) WLAN_PLL_CONTROL_MAC_OVERRIDE_SET(x)
-#define PLL_CONTROL_NOPWD_MSB WLAN_PLL_CONTROL_NOPWD_MSB
-#define PLL_CONTROL_NOPWD_LSB WLAN_PLL_CONTROL_NOPWD_LSB
-#define PLL_CONTROL_NOPWD_MASK WLAN_PLL_CONTROL_NOPWD_MASK
-#define PLL_CONTROL_NOPWD_GET(x) WLAN_PLL_CONTROL_NOPWD_GET(x)
-#define PLL_CONTROL_NOPWD_SET(x) WLAN_PLL_CONTROL_NOPWD_SET(x)
-#define PLL_CONTROL_UPDATING_MSB WLAN_PLL_CONTROL_UPDATING_MSB
-#define PLL_CONTROL_UPDATING_LSB WLAN_PLL_CONTROL_UPDATING_LSB
-#define PLL_CONTROL_UPDATING_MASK WLAN_PLL_CONTROL_UPDATING_MASK
-#define PLL_CONTROL_UPDATING_GET(x) WLAN_PLL_CONTROL_UPDATING_GET(x)
-#define PLL_CONTROL_UPDATING_SET(x) WLAN_PLL_CONTROL_UPDATING_SET(x)
-#define PLL_CONTROL_BYPASS_MSB WLAN_PLL_CONTROL_BYPASS_MSB
-#define PLL_CONTROL_BYPASS_LSB WLAN_PLL_CONTROL_BYPASS_LSB
-#define PLL_CONTROL_BYPASS_MASK WLAN_PLL_CONTROL_BYPASS_MASK
-#define PLL_CONTROL_BYPASS_GET(x) WLAN_PLL_CONTROL_BYPASS_GET(x)
-#define PLL_CONTROL_BYPASS_SET(x) WLAN_PLL_CONTROL_BYPASS_SET(x)
-#define PLL_CONTROL_REFDIV_MSB WLAN_PLL_CONTROL_REFDIV_MSB
-#define PLL_CONTROL_REFDIV_LSB WLAN_PLL_CONTROL_REFDIV_LSB
-#define PLL_CONTROL_REFDIV_MASK WLAN_PLL_CONTROL_REFDIV_MASK
-#define PLL_CONTROL_REFDIV_GET(x) WLAN_PLL_CONTROL_REFDIV_GET(x)
-#define PLL_CONTROL_REFDIV_SET(x) WLAN_PLL_CONTROL_REFDIV_SET(x)
-#define PLL_CONTROL_DIV_MSB WLAN_PLL_CONTROL_DIV_MSB
-#define PLL_CONTROL_DIV_LSB WLAN_PLL_CONTROL_DIV_LSB
-#define PLL_CONTROL_DIV_MASK WLAN_PLL_CONTROL_DIV_MASK
-#define PLL_CONTROL_DIV_GET(x) WLAN_PLL_CONTROL_DIV_GET(x)
-#define PLL_CONTROL_DIV_SET(x) WLAN_PLL_CONTROL_DIV_SET(x)
-#define PLL_SETTLE_ADDRESS WLAN_PLL_SETTLE_ADDRESS
-#define PLL_SETTLE_OFFSET WLAN_PLL_SETTLE_OFFSET
-#define PLL_SETTLE_TIME_MSB WLAN_PLL_SETTLE_TIME_MSB
-#define PLL_SETTLE_TIME_LSB WLAN_PLL_SETTLE_TIME_LSB
-#define PLL_SETTLE_TIME_MASK WLAN_PLL_SETTLE_TIME_MASK
-#define PLL_SETTLE_TIME_GET(x) WLAN_PLL_SETTLE_TIME_GET(x)
-#define PLL_SETTLE_TIME_SET(x) WLAN_PLL_SETTLE_TIME_SET(x)
-#define XTAL_SETTLE_ADDRESS WLAN_XTAL_SETTLE_ADDRESS
-#define XTAL_SETTLE_OFFSET WLAN_XTAL_SETTLE_OFFSET
-#define XTAL_SETTLE_TIME_MSB WLAN_XTAL_SETTLE_TIME_MSB
-#define XTAL_SETTLE_TIME_LSB WLAN_XTAL_SETTLE_TIME_LSB
-#define XTAL_SETTLE_TIME_MASK WLAN_XTAL_SETTLE_TIME_MASK
-#define XTAL_SETTLE_TIME_GET(x) WLAN_XTAL_SETTLE_TIME_GET(x)
-#define XTAL_SETTLE_TIME_SET(x) WLAN_XTAL_SETTLE_TIME_SET(x)
#define CPU_CLOCK_ADDRESS WLAN_CPU_CLOCK_ADDRESS
#define CPU_CLOCK_OFFSET WLAN_CPU_CLOCK_OFFSET
#define CPU_CLOCK_STANDARD_MSB WLAN_CPU_CLOCK_STANDARD_MSB
@@ -215,510 +123,6 @@
#define CLOCK_CONTROL_SI0_CLK_MASK WLAN_CLOCK_CONTROL_SI0_CLK_MASK
#define CLOCK_CONTROL_SI0_CLK_GET(x) WLAN_CLOCK_CONTROL_SI0_CLK_GET(x)
#define CLOCK_CONTROL_SI0_CLK_SET(x) WLAN_CLOCK_CONTROL_SI0_CLK_SET(x)
-#define BIAS_OVERRIDE_ADDRESS WLAN_BIAS_OVERRIDE_ADDRESS
-#define BIAS_OVERRIDE_OFFSET WLAN_BIAS_OVERRIDE_OFFSET
-#define BIAS_OVERRIDE_ON_MSB WLAN_BIAS_OVERRIDE_ON_MSB
-#define BIAS_OVERRIDE_ON_LSB WLAN_BIAS_OVERRIDE_ON_LSB
-#define BIAS_OVERRIDE_ON_MASK WLAN_BIAS_OVERRIDE_ON_MASK
-#define BIAS_OVERRIDE_ON_GET(x) WLAN_BIAS_OVERRIDE_ON_GET(x)
-#define BIAS_OVERRIDE_ON_SET(x) WLAN_BIAS_OVERRIDE_ON_SET(x)
-#define WDT_CONTROL_ADDRESS WLAN_WDT_CONTROL_ADDRESS
-#define WDT_CONTROL_OFFSET WLAN_WDT_CONTROL_OFFSET
-#define WDT_CONTROL_ACTION_MSB WLAN_WDT_CONTROL_ACTION_MSB
-#define WDT_CONTROL_ACTION_LSB WLAN_WDT_CONTROL_ACTION_LSB
-#define WDT_CONTROL_ACTION_MASK WLAN_WDT_CONTROL_ACTION_MASK
-#define WDT_CONTROL_ACTION_GET(x) WLAN_WDT_CONTROL_ACTION_GET(x)
-#define WDT_CONTROL_ACTION_SET(x) WLAN_WDT_CONTROL_ACTION_SET(x)
-#define WDT_STATUS_ADDRESS WLAN_WDT_STATUS_ADDRESS
-#define WDT_STATUS_OFFSET WLAN_WDT_STATUS_OFFSET
-#define WDT_STATUS_INTERRUPT_MSB WLAN_WDT_STATUS_INTERRUPT_MSB
-#define WDT_STATUS_INTERRUPT_LSB WLAN_WDT_STATUS_INTERRUPT_LSB
-#define WDT_STATUS_INTERRUPT_MASK WLAN_WDT_STATUS_INTERRUPT_MASK
-#define WDT_STATUS_INTERRUPT_GET(x) WLAN_WDT_STATUS_INTERRUPT_GET(x)
-#define WDT_STATUS_INTERRUPT_SET(x) WLAN_WDT_STATUS_INTERRUPT_SET(x)
-#define WDT_ADDRESS WLAN_WDT_ADDRESS
-#define WDT_OFFSET WLAN_WDT_OFFSET
-#define WDT_TARGET_MSB WLAN_WDT_TARGET_MSB
-#define WDT_TARGET_LSB WLAN_WDT_TARGET_LSB
-#define WDT_TARGET_MASK WLAN_WDT_TARGET_MASK
-#define WDT_TARGET_GET(x) WLAN_WDT_TARGET_GET(x)
-#define WDT_TARGET_SET(x) WLAN_WDT_TARGET_SET(x)
-#define WDT_COUNT_ADDRESS WLAN_WDT_COUNT_ADDRESS
-#define WDT_COUNT_OFFSET WLAN_WDT_COUNT_OFFSET
-#define WDT_COUNT_VALUE_MSB WLAN_WDT_COUNT_VALUE_MSB
-#define WDT_COUNT_VALUE_LSB WLAN_WDT_COUNT_VALUE_LSB
-#define WDT_COUNT_VALUE_MASK WLAN_WDT_COUNT_VALUE_MASK
-#define WDT_COUNT_VALUE_GET(x) WLAN_WDT_COUNT_VALUE_GET(x)
-#define WDT_COUNT_VALUE_SET(x) WLAN_WDT_COUNT_VALUE_SET(x)
-#define WDT_RESET_ADDRESS WLAN_WDT_RESET_ADDRESS
-#define WDT_RESET_OFFSET WLAN_WDT_RESET_OFFSET
-#define WDT_RESET_VALUE_MSB WLAN_WDT_RESET_VALUE_MSB
-#define WDT_RESET_VALUE_LSB WLAN_WDT_RESET_VALUE_LSB
-#define WDT_RESET_VALUE_MASK WLAN_WDT_RESET_VALUE_MASK
-#define WDT_RESET_VALUE_GET(x) WLAN_WDT_RESET_VALUE_GET(x)
-#define WDT_RESET_VALUE_SET(x) WLAN_WDT_RESET_VALUE_SET(x)
-#define INT_STATUS_ADDRESS WLAN_INT_STATUS_ADDRESS
-#define INT_STATUS_OFFSET WLAN_INT_STATUS_OFFSET
-#define INT_STATUS_HCI_UART_MSB WLAN_INT_STATUS_HCI_UART_MSB
-#define INT_STATUS_HCI_UART_LSB WLAN_INT_STATUS_HCI_UART_LSB
-#define INT_STATUS_HCI_UART_MASK WLAN_INT_STATUS_HCI_UART_MASK
-#define INT_STATUS_HCI_UART_GET(x) WLAN_INT_STATUS_HCI_UART_GET(x)
-#define INT_STATUS_HCI_UART_SET(x) WLAN_INT_STATUS_HCI_UART_SET(x)
-#define INT_STATUS_THERM_MSB WLAN_INT_STATUS_THERM_MSB
-#define INT_STATUS_THERM_LSB WLAN_INT_STATUS_THERM_LSB
-#define INT_STATUS_THERM_MASK WLAN_INT_STATUS_THERM_MASK
-#define INT_STATUS_THERM_GET(x) WLAN_INT_STATUS_THERM_GET(x)
-#define INT_STATUS_THERM_SET(x) WLAN_INT_STATUS_THERM_SET(x)
-#define INT_STATUS_EFUSE_OVERWRITE_MSB WLAN_INT_STATUS_EFUSE_OVERWRITE_MSB
-#define INT_STATUS_EFUSE_OVERWRITE_LSB WLAN_INT_STATUS_EFUSE_OVERWRITE_LSB
-#define INT_STATUS_EFUSE_OVERWRITE_MASK WLAN_INT_STATUS_EFUSE_OVERWRITE_MASK
-#define INT_STATUS_EFUSE_OVERWRITE_GET(x) WLAN_INT_STATUS_EFUSE_OVERWRITE_GET(x)
-#define INT_STATUS_EFUSE_OVERWRITE_SET(x) WLAN_INT_STATUS_EFUSE_OVERWRITE_SET(x)
-#define INT_STATUS_UART_MBOX_MSB WLAN_INT_STATUS_UART_MBOX_MSB
-#define INT_STATUS_UART_MBOX_LSB WLAN_INT_STATUS_UART_MBOX_LSB
-#define INT_STATUS_UART_MBOX_MASK WLAN_INT_STATUS_UART_MBOX_MASK
-#define INT_STATUS_UART_MBOX_GET(x) WLAN_INT_STATUS_UART_MBOX_GET(x)
-#define INT_STATUS_UART_MBOX_SET(x) WLAN_INT_STATUS_UART_MBOX_SET(x)
-#define INT_STATUS_GENERIC_MBOX_MSB WLAN_INT_STATUS_GENERIC_MBOX_MSB
-#define INT_STATUS_GENERIC_MBOX_LSB WLAN_INT_STATUS_GENERIC_MBOX_LSB
-#define INT_STATUS_GENERIC_MBOX_MASK WLAN_INT_STATUS_GENERIC_MBOX_MASK
-#define INT_STATUS_GENERIC_MBOX_GET(x) WLAN_INT_STATUS_GENERIC_MBOX_GET(x)
-#define INT_STATUS_GENERIC_MBOX_SET(x) WLAN_INT_STATUS_GENERIC_MBOX_SET(x)
-#define INT_STATUS_RDMA_MSB WLAN_INT_STATUS_RDMA_MSB
-#define INT_STATUS_RDMA_LSB WLAN_INT_STATUS_RDMA_LSB
-#define INT_STATUS_RDMA_MASK WLAN_INT_STATUS_RDMA_MASK
-#define INT_STATUS_RDMA_GET(x) WLAN_INT_STATUS_RDMA_GET(x)
-#define INT_STATUS_RDMA_SET(x) WLAN_INT_STATUS_RDMA_SET(x)
-#define INT_STATUS_BTCOEX_MSB WLAN_INT_STATUS_BTCOEX_MSB
-#define INT_STATUS_BTCOEX_LSB WLAN_INT_STATUS_BTCOEX_LSB
-#define INT_STATUS_BTCOEX_MASK WLAN_INT_STATUS_BTCOEX_MASK
-#define INT_STATUS_BTCOEX_GET(x) WLAN_INT_STATUS_BTCOEX_GET(x)
-#define INT_STATUS_BTCOEX_SET(x) WLAN_INT_STATUS_BTCOEX_SET(x)
-#define INT_STATUS_RTC_POWER_MSB WLAN_INT_STATUS_RTC_POWER_MSB
-#define INT_STATUS_RTC_POWER_LSB WLAN_INT_STATUS_RTC_POWER_LSB
-#define INT_STATUS_RTC_POWER_MASK WLAN_INT_STATUS_RTC_POWER_MASK
-#define INT_STATUS_RTC_POWER_GET(x) WLAN_INT_STATUS_RTC_POWER_GET(x)
-#define INT_STATUS_RTC_POWER_SET(x) WLAN_INT_STATUS_RTC_POWER_SET(x)
-#define INT_STATUS_MAC_MSB WLAN_INT_STATUS_MAC_MSB
-#define INT_STATUS_MAC_LSB WLAN_INT_STATUS_MAC_LSB
-#define INT_STATUS_MAC_MASK WLAN_INT_STATUS_MAC_MASK
-#define INT_STATUS_MAC_GET(x) WLAN_INT_STATUS_MAC_GET(x)
-#define INT_STATUS_MAC_SET(x) WLAN_INT_STATUS_MAC_SET(x)
-#define INT_STATUS_MAILBOX_MSB WLAN_INT_STATUS_MAILBOX_MSB
-#define INT_STATUS_MAILBOX_LSB WLAN_INT_STATUS_MAILBOX_LSB
-#define INT_STATUS_MAILBOX_MASK WLAN_INT_STATUS_MAILBOX_MASK
-#define INT_STATUS_MAILBOX_GET(x) WLAN_INT_STATUS_MAILBOX_GET(x)
-#define INT_STATUS_MAILBOX_SET(x) WLAN_INT_STATUS_MAILBOX_SET(x)
-#define INT_STATUS_RTC_ALARM_MSB WLAN_INT_STATUS_RTC_ALARM_MSB
-#define INT_STATUS_RTC_ALARM_LSB WLAN_INT_STATUS_RTC_ALARM_LSB
-#define INT_STATUS_RTC_ALARM_MASK WLAN_INT_STATUS_RTC_ALARM_MASK
-#define INT_STATUS_RTC_ALARM_GET(x) WLAN_INT_STATUS_RTC_ALARM_GET(x)
-#define INT_STATUS_RTC_ALARM_SET(x) WLAN_INT_STATUS_RTC_ALARM_SET(x)
-#define INT_STATUS_HF_TIMER_MSB WLAN_INT_STATUS_HF_TIMER_MSB
-#define INT_STATUS_HF_TIMER_LSB WLAN_INT_STATUS_HF_TIMER_LSB
-#define INT_STATUS_HF_TIMER_MASK WLAN_INT_STATUS_HF_TIMER_MASK
-#define INT_STATUS_HF_TIMER_GET(x) WLAN_INT_STATUS_HF_TIMER_GET(x)
-#define INT_STATUS_HF_TIMER_SET(x) WLAN_INT_STATUS_HF_TIMER_SET(x)
-#define INT_STATUS_LF_TIMER3_MSB WLAN_INT_STATUS_LF_TIMER3_MSB
-#define INT_STATUS_LF_TIMER3_LSB WLAN_INT_STATUS_LF_TIMER3_LSB
-#define INT_STATUS_LF_TIMER3_MASK WLAN_INT_STATUS_LF_TIMER3_MASK
-#define INT_STATUS_LF_TIMER3_GET(x) WLAN_INT_STATUS_LF_TIMER3_GET(x)
-#define INT_STATUS_LF_TIMER3_SET(x) WLAN_INT_STATUS_LF_TIMER3_SET(x)
-#define INT_STATUS_LF_TIMER2_MSB WLAN_INT_STATUS_LF_TIMER2_MSB
-#define INT_STATUS_LF_TIMER2_LSB WLAN_INT_STATUS_LF_TIMER2_LSB
-#define INT_STATUS_LF_TIMER2_MASK WLAN_INT_STATUS_LF_TIMER2_MASK
-#define INT_STATUS_LF_TIMER2_GET(x) WLAN_INT_STATUS_LF_TIMER2_GET(x)
-#define INT_STATUS_LF_TIMER2_SET(x) WLAN_INT_STATUS_LF_TIMER2_SET(x)
-#define INT_STATUS_LF_TIMER1_MSB WLAN_INT_STATUS_LF_TIMER1_MSB
-#define INT_STATUS_LF_TIMER1_LSB WLAN_INT_STATUS_LF_TIMER1_LSB
-#define INT_STATUS_LF_TIMER1_MASK WLAN_INT_STATUS_LF_TIMER1_MASK
-#define INT_STATUS_LF_TIMER1_GET(x) WLAN_INT_STATUS_LF_TIMER1_GET(x)
-#define INT_STATUS_LF_TIMER1_SET(x) WLAN_INT_STATUS_LF_TIMER1_SET(x)
-#define INT_STATUS_LF_TIMER0_MSB WLAN_INT_STATUS_LF_TIMER0_MSB
-#define INT_STATUS_LF_TIMER0_LSB WLAN_INT_STATUS_LF_TIMER0_LSB
-#define INT_STATUS_LF_TIMER0_MASK WLAN_INT_STATUS_LF_TIMER0_MASK
-#define INT_STATUS_LF_TIMER0_GET(x) WLAN_INT_STATUS_LF_TIMER0_GET(x)
-#define INT_STATUS_LF_TIMER0_SET(x) WLAN_INT_STATUS_LF_TIMER0_SET(x)
-#define INT_STATUS_KEYPAD_MSB WLAN_INT_STATUS_KEYPAD_MSB
-#define INT_STATUS_KEYPAD_LSB WLAN_INT_STATUS_KEYPAD_LSB
-#define INT_STATUS_KEYPAD_MASK WLAN_INT_STATUS_KEYPAD_MASK
-#define INT_STATUS_KEYPAD_GET(x) WLAN_INT_STATUS_KEYPAD_GET(x)
-#define INT_STATUS_KEYPAD_SET(x) WLAN_INT_STATUS_KEYPAD_SET(x)
-#define INT_STATUS_SI_MSB WLAN_INT_STATUS_SI_MSB
-#define INT_STATUS_SI_LSB WLAN_INT_STATUS_SI_LSB
-#define INT_STATUS_SI_MASK WLAN_INT_STATUS_SI_MASK
-#define INT_STATUS_SI_GET(x) WLAN_INT_STATUS_SI_GET(x)
-#define INT_STATUS_SI_SET(x) WLAN_INT_STATUS_SI_SET(x)
-#define INT_STATUS_GPIO_MSB WLAN_INT_STATUS_GPIO_MSB
-#define INT_STATUS_GPIO_LSB WLAN_INT_STATUS_GPIO_LSB
-#define INT_STATUS_GPIO_MASK WLAN_INT_STATUS_GPIO_MASK
-#define INT_STATUS_GPIO_GET(x) WLAN_INT_STATUS_GPIO_GET(x)
-#define INT_STATUS_GPIO_SET(x) WLAN_INT_STATUS_GPIO_SET(x)
-#define INT_STATUS_UART_MSB WLAN_INT_STATUS_UART_MSB
-#define INT_STATUS_UART_LSB WLAN_INT_STATUS_UART_LSB
-#define INT_STATUS_UART_MASK WLAN_INT_STATUS_UART_MASK
-#define INT_STATUS_UART_GET(x) WLAN_INT_STATUS_UART_GET(x)
-#define INT_STATUS_UART_SET(x) WLAN_INT_STATUS_UART_SET(x)
-#define INT_STATUS_ERROR_MSB WLAN_INT_STATUS_ERROR_MSB
-#define INT_STATUS_ERROR_LSB WLAN_INT_STATUS_ERROR_LSB
-#define INT_STATUS_ERROR_MASK WLAN_INT_STATUS_ERROR_MASK
-#define INT_STATUS_ERROR_GET(x) WLAN_INT_STATUS_ERROR_GET(x)
-#define INT_STATUS_ERROR_SET(x) WLAN_INT_STATUS_ERROR_SET(x)
-#define INT_STATUS_WDT_INT_MSB WLAN_INT_STATUS_WDT_INT_MSB
-#define INT_STATUS_WDT_INT_LSB WLAN_INT_STATUS_WDT_INT_LSB
-#define INT_STATUS_WDT_INT_MASK WLAN_INT_STATUS_WDT_INT_MASK
-#define INT_STATUS_WDT_INT_GET(x) WLAN_INT_STATUS_WDT_INT_GET(x)
-#define INT_STATUS_WDT_INT_SET(x) WLAN_INT_STATUS_WDT_INT_SET(x)
-#define LF_TIMER0_ADDRESS WLAN_LF_TIMER0_ADDRESS
-#define LF_TIMER0_OFFSET WLAN_LF_TIMER0_OFFSET
-#define LF_TIMER0_TARGET_MSB WLAN_LF_TIMER0_TARGET_MSB
-#define LF_TIMER0_TARGET_LSB WLAN_LF_TIMER0_TARGET_LSB
-#define LF_TIMER0_TARGET_MASK WLAN_LF_TIMER0_TARGET_MASK
-#define LF_TIMER0_TARGET_GET(x) WLAN_LF_TIMER0_TARGET_GET(x)
-#define LF_TIMER0_TARGET_SET(x) WLAN_LF_TIMER0_TARGET_SET(x)
-#define LF_TIMER_COUNT0_ADDRESS WLAN_LF_TIMER_COUNT0_ADDRESS
-#define LF_TIMER_COUNT0_OFFSET WLAN_LF_TIMER_COUNT0_OFFSET
-#define LF_TIMER_COUNT0_VALUE_MSB WLAN_LF_TIMER_COUNT0_VALUE_MSB
-#define LF_TIMER_COUNT0_VALUE_LSB WLAN_LF_TIMER_COUNT0_VALUE_LSB
-#define LF_TIMER_COUNT0_VALUE_MASK WLAN_LF_TIMER_COUNT0_VALUE_MASK
-#define LF_TIMER_COUNT0_VALUE_GET(x) WLAN_LF_TIMER_COUNT0_VALUE_GET(x)
-#define LF_TIMER_COUNT0_VALUE_SET(x) WLAN_LF_TIMER_COUNT0_VALUE_SET(x)
-#define LF_TIMER_CONTROL0_ADDRESS WLAN_LF_TIMER_CONTROL0_ADDRESS
-#define LF_TIMER_CONTROL0_OFFSET WLAN_LF_TIMER_CONTROL0_OFFSET
-#define LF_TIMER_CONTROL0_ENABLE_MSB WLAN_LF_TIMER_CONTROL0_ENABLE_MSB
-#define LF_TIMER_CONTROL0_ENABLE_LSB WLAN_LF_TIMER_CONTROL0_ENABLE_LSB
-#define LF_TIMER_CONTROL0_ENABLE_MASK WLAN_LF_TIMER_CONTROL0_ENABLE_MASK
-#define LF_TIMER_CONTROL0_ENABLE_GET(x) WLAN_LF_TIMER_CONTROL0_ENABLE_GET(x)
-#define LF_TIMER_CONTROL0_ENABLE_SET(x) WLAN_LF_TIMER_CONTROL0_ENABLE_SET(x)
-#define LF_TIMER_CONTROL0_AUTO_RESTART_MSB WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_MSB
-#define LF_TIMER_CONTROL0_AUTO_RESTART_LSB WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_LSB
-#define LF_TIMER_CONTROL0_AUTO_RESTART_MASK WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_MASK
-#define LF_TIMER_CONTROL0_AUTO_RESTART_GET(x) WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_GET(x)
-#define LF_TIMER_CONTROL0_AUTO_RESTART_SET(x) WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_SET(x)
-#define LF_TIMER_CONTROL0_RESET_MSB WLAN_LF_TIMER_CONTROL0_RESET_MSB
-#define LF_TIMER_CONTROL0_RESET_LSB WLAN_LF_TIMER_CONTROL0_RESET_LSB
-#define LF_TIMER_CONTROL0_RESET_MASK WLAN_LF_TIMER_CONTROL0_RESET_MASK
-#define LF_TIMER_CONTROL0_RESET_GET(x) WLAN_LF_TIMER_CONTROL0_RESET_GET(x)
-#define LF_TIMER_CONTROL0_RESET_SET(x) WLAN_LF_TIMER_CONTROL0_RESET_SET(x)
-#define LF_TIMER_STATUS0_ADDRESS WLAN_LF_TIMER_STATUS0_ADDRESS
-#define LF_TIMER_STATUS0_OFFSET WLAN_LF_TIMER_STATUS0_OFFSET
-#define LF_TIMER_STATUS0_INTERRUPT_MSB WLAN_LF_TIMER_STATUS0_INTERRUPT_MSB
-#define LF_TIMER_STATUS0_INTERRUPT_LSB WLAN_LF_TIMER_STATUS0_INTERRUPT_LSB
-#define LF_TIMER_STATUS0_INTERRUPT_MASK WLAN_LF_TIMER_STATUS0_INTERRUPT_MASK
-#define LF_TIMER_STATUS0_INTERRUPT_GET(x) WLAN_LF_TIMER_STATUS0_INTERRUPT_GET(x)
-#define LF_TIMER_STATUS0_INTERRUPT_SET(x) WLAN_LF_TIMER_STATUS0_INTERRUPT_SET(x)
-#define LF_TIMER1_ADDRESS WLAN_LF_TIMER1_ADDRESS
-#define LF_TIMER1_OFFSET WLAN_LF_TIMER1_OFFSET
-#define LF_TIMER1_TARGET_MSB WLAN_LF_TIMER1_TARGET_MSB
-#define LF_TIMER1_TARGET_LSB WLAN_LF_TIMER1_TARGET_LSB
-#define LF_TIMER1_TARGET_MASK WLAN_LF_TIMER1_TARGET_MASK
-#define LF_TIMER1_TARGET_GET(x) WLAN_LF_TIMER1_TARGET_GET(x)
-#define LF_TIMER1_TARGET_SET(x) WLAN_LF_TIMER1_TARGET_SET(x)
-#define LF_TIMER_COUNT1_ADDRESS WLAN_LF_TIMER_COUNT1_ADDRESS
-#define LF_TIMER_COUNT1_OFFSET WLAN_LF_TIMER_COUNT1_OFFSET
-#define LF_TIMER_COUNT1_VALUE_MSB WLAN_LF_TIMER_COUNT1_VALUE_MSB
-#define LF_TIMER_COUNT1_VALUE_LSB WLAN_LF_TIMER_COUNT1_VALUE_LSB
-#define LF_TIMER_COUNT1_VALUE_MASK WLAN_LF_TIMER_COUNT1_VALUE_MASK
-#define LF_TIMER_COUNT1_VALUE_GET(x) WLAN_LF_TIMER_COUNT1_VALUE_GET(x)
-#define LF_TIMER_COUNT1_VALUE_SET(x) WLAN_LF_TIMER_COUNT1_VALUE_SET(x)
-#define LF_TIMER_CONTROL1_ADDRESS WLAN_LF_TIMER_CONTROL1_ADDRESS
-#define LF_TIMER_CONTROL1_OFFSET WLAN_LF_TIMER_CONTROL1_OFFSET
-#define LF_TIMER_CONTROL1_ENABLE_MSB WLAN_LF_TIMER_CONTROL1_ENABLE_MSB
-#define LF_TIMER_CONTROL1_ENABLE_LSB WLAN_LF_TIMER_CONTROL1_ENABLE_LSB
-#define LF_TIMER_CONTROL1_ENABLE_MASK WLAN_LF_TIMER_CONTROL1_ENABLE_MASK
-#define LF_TIMER_CONTROL1_ENABLE_GET(x) WLAN_LF_TIMER_CONTROL1_ENABLE_GET(x)
-#define LF_TIMER_CONTROL1_ENABLE_SET(x) WLAN_LF_TIMER_CONTROL1_ENABLE_SET(x)
-#define LF_TIMER_CONTROL1_AUTO_RESTART_MSB WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_MSB
-#define LF_TIMER_CONTROL1_AUTO_RESTART_LSB WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_LSB
-#define LF_TIMER_CONTROL1_AUTO_RESTART_MASK WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_MASK
-#define LF_TIMER_CONTROL1_AUTO_RESTART_GET(x) WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_GET(x)
-#define LF_TIMER_CONTROL1_AUTO_RESTART_SET(x) WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_SET(x)
-#define LF_TIMER_CONTROL1_RESET_MSB WLAN_LF_TIMER_CONTROL1_RESET_MSB
-#define LF_TIMER_CONTROL1_RESET_LSB WLAN_LF_TIMER_CONTROL1_RESET_LSB
-#define LF_TIMER_CONTROL1_RESET_MASK WLAN_LF_TIMER_CONTROL1_RESET_MASK
-#define LF_TIMER_CONTROL1_RESET_GET(x) WLAN_LF_TIMER_CONTROL1_RESET_GET(x)
-#define LF_TIMER_CONTROL1_RESET_SET(x) WLAN_LF_TIMER_CONTROL1_RESET_SET(x)
-#define LF_TIMER_STATUS1_ADDRESS WLAN_LF_TIMER_STATUS1_ADDRESS
-#define LF_TIMER_STATUS1_OFFSET WLAN_LF_TIMER_STATUS1_OFFSET
-#define LF_TIMER_STATUS1_INTERRUPT_MSB WLAN_LF_TIMER_STATUS1_INTERRUPT_MSB
-#define LF_TIMER_STATUS1_INTERRUPT_LSB WLAN_LF_TIMER_STATUS1_INTERRUPT_LSB
-#define LF_TIMER_STATUS1_INTERRUPT_MASK WLAN_LF_TIMER_STATUS1_INTERRUPT_MASK
-#define LF_TIMER_STATUS1_INTERRUPT_GET(x) WLAN_LF_TIMER_STATUS1_INTERRUPT_GET(x)
-#define LF_TIMER_STATUS1_INTERRUPT_SET(x) WLAN_LF_TIMER_STATUS1_INTERRUPT_SET(x)
-#define LF_TIMER2_ADDRESS WLAN_LF_TIMER2_ADDRESS
-#define LF_TIMER2_OFFSET WLAN_LF_TIMER2_OFFSET
-#define LF_TIMER2_TARGET_MSB WLAN_LF_TIMER2_TARGET_MSB
-#define LF_TIMER2_TARGET_LSB WLAN_LF_TIMER2_TARGET_LSB
-#define LF_TIMER2_TARGET_MASK WLAN_LF_TIMER2_TARGET_MASK
-#define LF_TIMER2_TARGET_GET(x) WLAN_LF_TIMER2_TARGET_GET(x)
-#define LF_TIMER2_TARGET_SET(x) WLAN_LF_TIMER2_TARGET_SET(x)
-#define LF_TIMER_COUNT2_ADDRESS WLAN_LF_TIMER_COUNT2_ADDRESS
-#define LF_TIMER_COUNT2_OFFSET WLAN_LF_TIMER_COUNT2_OFFSET
-#define LF_TIMER_COUNT2_VALUE_MSB WLAN_LF_TIMER_COUNT2_VALUE_MSB
-#define LF_TIMER_COUNT2_VALUE_LSB WLAN_LF_TIMER_COUNT2_VALUE_LSB
-#define LF_TIMER_COUNT2_VALUE_MASK WLAN_LF_TIMER_COUNT2_VALUE_MASK
-#define LF_TIMER_COUNT2_VALUE_GET(x) WLAN_LF_TIMER_COUNT2_VALUE_GET(x)
-#define LF_TIMER_COUNT2_VALUE_SET(x) WLAN_LF_TIMER_COUNT2_VALUE_SET(x)
-#define LF_TIMER_CONTROL2_ADDRESS WLAN_LF_TIMER_CONTROL2_ADDRESS
-#define LF_TIMER_CONTROL2_OFFSET WLAN_LF_TIMER_CONTROL2_OFFSET
-#define LF_TIMER_CONTROL2_ENABLE_MSB WLAN_LF_TIMER_CONTROL2_ENABLE_MSB
-#define LF_TIMER_CONTROL2_ENABLE_LSB WLAN_LF_TIMER_CONTROL2_ENABLE_LSB
-#define LF_TIMER_CONTROL2_ENABLE_MASK WLAN_LF_TIMER_CONTROL2_ENABLE_MASK
-#define LF_TIMER_CONTROL2_ENABLE_GET(x) WLAN_LF_TIMER_CONTROL2_ENABLE_GET(x)
-#define LF_TIMER_CONTROL2_ENABLE_SET(x) WLAN_LF_TIMER_CONTROL2_ENABLE_SET(x)
-#define LF_TIMER_CONTROL2_AUTO_RESTART_MSB WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_MSB
-#define LF_TIMER_CONTROL2_AUTO_RESTART_LSB WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_LSB
-#define LF_TIMER_CONTROL2_AUTO_RESTART_MASK WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_MASK
-#define LF_TIMER_CONTROL2_AUTO_RESTART_GET(x) WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_GET(x)
-#define LF_TIMER_CONTROL2_AUTO_RESTART_SET(x) WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_SET(x)
-#define LF_TIMER_CONTROL2_RESET_MSB WLAN_LF_TIMER_CONTROL2_RESET_MSB
-#define LF_TIMER_CONTROL2_RESET_LSB WLAN_LF_TIMER_CONTROL2_RESET_LSB
-#define LF_TIMER_CONTROL2_RESET_MASK WLAN_LF_TIMER_CONTROL2_RESET_MASK
-#define LF_TIMER_CONTROL2_RESET_GET(x) WLAN_LF_TIMER_CONTROL2_RESET_GET(x)
-#define LF_TIMER_CONTROL2_RESET_SET(x) WLAN_LF_TIMER_CONTROL2_RESET_SET(x)
-#define LF_TIMER_STATUS2_ADDRESS WLAN_LF_TIMER_STATUS2_ADDRESS
-#define LF_TIMER_STATUS2_OFFSET WLAN_LF_TIMER_STATUS2_OFFSET
-#define LF_TIMER_STATUS2_INTERRUPT_MSB WLAN_LF_TIMER_STATUS2_INTERRUPT_MSB
-#define LF_TIMER_STATUS2_INTERRUPT_LSB WLAN_LF_TIMER_STATUS2_INTERRUPT_LSB
-#define LF_TIMER_STATUS2_INTERRUPT_MASK WLAN_LF_TIMER_STATUS2_INTERRUPT_MASK
-#define LF_TIMER_STATUS2_INTERRUPT_GET(x) WLAN_LF_TIMER_STATUS2_INTERRUPT_GET(x)
-#define LF_TIMER_STATUS2_INTERRUPT_SET(x) WLAN_LF_TIMER_STATUS2_INTERRUPT_SET(x)
-#define LF_TIMER3_ADDRESS WLAN_LF_TIMER3_ADDRESS
-#define LF_TIMER3_OFFSET WLAN_LF_TIMER3_OFFSET
-#define LF_TIMER3_TARGET_MSB WLAN_LF_TIMER3_TARGET_MSB
-#define LF_TIMER3_TARGET_LSB WLAN_LF_TIMER3_TARGET_LSB
-#define LF_TIMER3_TARGET_MASK WLAN_LF_TIMER3_TARGET_MASK
-#define LF_TIMER3_TARGET_GET(x) WLAN_LF_TIMER3_TARGET_GET(x)
-#define LF_TIMER3_TARGET_SET(x) WLAN_LF_TIMER3_TARGET_SET(x)
-#define LF_TIMER_COUNT3_ADDRESS WLAN_LF_TIMER_COUNT3_ADDRESS
-#define LF_TIMER_COUNT3_OFFSET WLAN_LF_TIMER_COUNT3_OFFSET
-#define LF_TIMER_COUNT3_VALUE_MSB WLAN_LF_TIMER_COUNT3_VALUE_MSB
-#define LF_TIMER_COUNT3_VALUE_LSB WLAN_LF_TIMER_COUNT3_VALUE_LSB
-#define LF_TIMER_COUNT3_VALUE_MASK WLAN_LF_TIMER_COUNT3_VALUE_MASK
-#define LF_TIMER_COUNT3_VALUE_GET(x) WLAN_LF_TIMER_COUNT3_VALUE_GET(x)
-#define LF_TIMER_COUNT3_VALUE_SET(x) WLAN_LF_TIMER_COUNT3_VALUE_SET(x)
-#define LF_TIMER_CONTROL3_ADDRESS WLAN_LF_TIMER_CONTROL3_ADDRESS
-#define LF_TIMER_CONTROL3_OFFSET WLAN_LF_TIMER_CONTROL3_OFFSET
-#define LF_TIMER_CONTROL3_ENABLE_MSB WLAN_LF_TIMER_CONTROL3_ENABLE_MSB
-#define LF_TIMER_CONTROL3_ENABLE_LSB WLAN_LF_TIMER_CONTROL3_ENABLE_LSB
-#define LF_TIMER_CONTROL3_ENABLE_MASK WLAN_LF_TIMER_CONTROL3_ENABLE_MASK
-#define LF_TIMER_CONTROL3_ENABLE_GET(x) WLAN_LF_TIMER_CONTROL3_ENABLE_GET(x)
-#define LF_TIMER_CONTROL3_ENABLE_SET(x) WLAN_LF_TIMER_CONTROL3_ENABLE_SET(x)
-#define LF_TIMER_CONTROL3_AUTO_RESTART_MSB WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_MSB
-#define LF_TIMER_CONTROL3_AUTO_RESTART_LSB WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_LSB
-#define LF_TIMER_CONTROL3_AUTO_RESTART_MASK WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_MASK
-#define LF_TIMER_CONTROL3_AUTO_RESTART_GET(x) WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_GET(x)
-#define LF_TIMER_CONTROL3_AUTO_RESTART_SET(x) WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_SET(x)
-#define LF_TIMER_CONTROL3_RESET_MSB WLAN_LF_TIMER_CONTROL3_RESET_MSB
-#define LF_TIMER_CONTROL3_RESET_LSB WLAN_LF_TIMER_CONTROL3_RESET_LSB
-#define LF_TIMER_CONTROL3_RESET_MASK WLAN_LF_TIMER_CONTROL3_RESET_MASK
-#define LF_TIMER_CONTROL3_RESET_GET(x) WLAN_LF_TIMER_CONTROL3_RESET_GET(x)
-#define LF_TIMER_CONTROL3_RESET_SET(x) WLAN_LF_TIMER_CONTROL3_RESET_SET(x)
-#define LF_TIMER_STATUS3_ADDRESS WLAN_LF_TIMER_STATUS3_ADDRESS
-#define LF_TIMER_STATUS3_OFFSET WLAN_LF_TIMER_STATUS3_OFFSET
-#define LF_TIMER_STATUS3_INTERRUPT_MSB WLAN_LF_TIMER_STATUS3_INTERRUPT_MSB
-#define LF_TIMER_STATUS3_INTERRUPT_LSB WLAN_LF_TIMER_STATUS3_INTERRUPT_LSB
-#define LF_TIMER_STATUS3_INTERRUPT_MASK WLAN_LF_TIMER_STATUS3_INTERRUPT_MASK
-#define LF_TIMER_STATUS3_INTERRUPT_GET(x) WLAN_LF_TIMER_STATUS3_INTERRUPT_GET(x)
-#define LF_TIMER_STATUS3_INTERRUPT_SET(x) WLAN_LF_TIMER_STATUS3_INTERRUPT_SET(x)
-#define HF_TIMER_ADDRESS WLAN_HF_TIMER_ADDRESS
-#define HF_TIMER_OFFSET WLAN_HF_TIMER_OFFSET
-#define HF_TIMER_TARGET_MSB WLAN_HF_TIMER_TARGET_MSB
-#define HF_TIMER_TARGET_LSB WLAN_HF_TIMER_TARGET_LSB
-#define HF_TIMER_TARGET_MASK WLAN_HF_TIMER_TARGET_MASK
-#define HF_TIMER_TARGET_GET(x) WLAN_HF_TIMER_TARGET_GET(x)
-#define HF_TIMER_TARGET_SET(x) WLAN_HF_TIMER_TARGET_SET(x)
-#define HF_TIMER_COUNT_ADDRESS WLAN_HF_TIMER_COUNT_ADDRESS
-#define HF_TIMER_COUNT_OFFSET WLAN_HF_TIMER_COUNT_OFFSET
-#define HF_TIMER_COUNT_VALUE_MSB WLAN_HF_TIMER_COUNT_VALUE_MSB
-#define HF_TIMER_COUNT_VALUE_LSB WLAN_HF_TIMER_COUNT_VALUE_LSB
-#define HF_TIMER_COUNT_VALUE_MASK WLAN_HF_TIMER_COUNT_VALUE_MASK
-#define HF_TIMER_COUNT_VALUE_GET(x) WLAN_HF_TIMER_COUNT_VALUE_GET(x)
-#define HF_TIMER_COUNT_VALUE_SET(x) WLAN_HF_TIMER_COUNT_VALUE_SET(x)
-#define HF_LF_COUNT_ADDRESS WLAN_HF_LF_COUNT_ADDRESS
-#define HF_LF_COUNT_OFFSET WLAN_HF_LF_COUNT_OFFSET
-#define HF_LF_COUNT_VALUE_MSB WLAN_HF_LF_COUNT_VALUE_MSB
-#define HF_LF_COUNT_VALUE_LSB WLAN_HF_LF_COUNT_VALUE_LSB
-#define HF_LF_COUNT_VALUE_MASK WLAN_HF_LF_COUNT_VALUE_MASK
-#define HF_LF_COUNT_VALUE_GET(x) WLAN_HF_LF_COUNT_VALUE_GET(x)
-#define HF_LF_COUNT_VALUE_SET(x) WLAN_HF_LF_COUNT_VALUE_SET(x)
-#define HF_TIMER_CONTROL_ADDRESS WLAN_HF_TIMER_CONTROL_ADDRESS
-#define HF_TIMER_CONTROL_OFFSET WLAN_HF_TIMER_CONTROL_OFFSET
-#define HF_TIMER_CONTROL_ENABLE_MSB WLAN_HF_TIMER_CONTROL_ENABLE_MSB
-#define HF_TIMER_CONTROL_ENABLE_LSB WLAN_HF_TIMER_CONTROL_ENABLE_LSB
-#define HF_TIMER_CONTROL_ENABLE_MASK WLAN_HF_TIMER_CONTROL_ENABLE_MASK
-#define HF_TIMER_CONTROL_ENABLE_GET(x) WLAN_HF_TIMER_CONTROL_ENABLE_GET(x)
-#define HF_TIMER_CONTROL_ENABLE_SET(x) WLAN_HF_TIMER_CONTROL_ENABLE_SET(x)
-#define HF_TIMER_CONTROL_ON_MSB WLAN_HF_TIMER_CONTROL_ON_MSB
-#define HF_TIMER_CONTROL_ON_LSB WLAN_HF_TIMER_CONTROL_ON_LSB
-#define HF_TIMER_CONTROL_ON_MASK WLAN_HF_TIMER_CONTROL_ON_MASK
-#define HF_TIMER_CONTROL_ON_GET(x) WLAN_HF_TIMER_CONTROL_ON_GET(x)
-#define HF_TIMER_CONTROL_ON_SET(x) WLAN_HF_TIMER_CONTROL_ON_SET(x)
-#define HF_TIMER_CONTROL_AUTO_RESTART_MSB WLAN_HF_TIMER_CONTROL_AUTO_RESTART_MSB
-#define HF_TIMER_CONTROL_AUTO_RESTART_LSB WLAN_HF_TIMER_CONTROL_AUTO_RESTART_LSB
-#define HF_TIMER_CONTROL_AUTO_RESTART_MASK WLAN_HF_TIMER_CONTROL_AUTO_RESTART_MASK
-#define HF_TIMER_CONTROL_AUTO_RESTART_GET(x) WLAN_HF_TIMER_CONTROL_AUTO_RESTART_GET(x)
-#define HF_TIMER_CONTROL_AUTO_RESTART_SET(x) WLAN_HF_TIMER_CONTROL_AUTO_RESTART_SET(x)
-#define HF_TIMER_CONTROL_RESET_MSB WLAN_HF_TIMER_CONTROL_RESET_MSB
-#define HF_TIMER_CONTROL_RESET_LSB WLAN_HF_TIMER_CONTROL_RESET_LSB
-#define HF_TIMER_CONTROL_RESET_MASK WLAN_HF_TIMER_CONTROL_RESET_MASK
-#define HF_TIMER_CONTROL_RESET_GET(x) WLAN_HF_TIMER_CONTROL_RESET_GET(x)
-#define HF_TIMER_CONTROL_RESET_SET(x) WLAN_HF_TIMER_CONTROL_RESET_SET(x)
-#define HF_TIMER_STATUS_ADDRESS WLAN_HF_TIMER_STATUS_ADDRESS
-#define HF_TIMER_STATUS_OFFSET WLAN_HF_TIMER_STATUS_OFFSET
-#define HF_TIMER_STATUS_INTERRUPT_MSB WLAN_HF_TIMER_STATUS_INTERRUPT_MSB
-#define HF_TIMER_STATUS_INTERRUPT_LSB WLAN_HF_TIMER_STATUS_INTERRUPT_LSB
-#define HF_TIMER_STATUS_INTERRUPT_MASK WLAN_HF_TIMER_STATUS_INTERRUPT_MASK
-#define HF_TIMER_STATUS_INTERRUPT_GET(x) WLAN_HF_TIMER_STATUS_INTERRUPT_GET(x)
-#define HF_TIMER_STATUS_INTERRUPT_SET(x) WLAN_HF_TIMER_STATUS_INTERRUPT_SET(x)
-#define RTC_CONTROL_ADDRESS WLAN_RTC_CONTROL_ADDRESS
-#define RTC_CONTROL_OFFSET WLAN_RTC_CONTROL_OFFSET
-#define RTC_CONTROL_ENABLE_MSB WLAN_RTC_CONTROL_ENABLE_MSB
-#define RTC_CONTROL_ENABLE_LSB WLAN_RTC_CONTROL_ENABLE_LSB
-#define RTC_CONTROL_ENABLE_MASK WLAN_RTC_CONTROL_ENABLE_MASK
-#define RTC_CONTROL_ENABLE_GET(x) WLAN_RTC_CONTROL_ENABLE_GET(x)
-#define RTC_CONTROL_ENABLE_SET(x) WLAN_RTC_CONTROL_ENABLE_SET(x)
-#define RTC_CONTROL_LOAD_RTC_MSB WLAN_RTC_CONTROL_LOAD_RTC_MSB
-#define RTC_CONTROL_LOAD_RTC_LSB WLAN_RTC_CONTROL_LOAD_RTC_LSB
-#define RTC_CONTROL_LOAD_RTC_MASK WLAN_RTC_CONTROL_LOAD_RTC_MASK
-#define RTC_CONTROL_LOAD_RTC_GET(x) WLAN_RTC_CONTROL_LOAD_RTC_GET(x)
-#define RTC_CONTROL_LOAD_RTC_SET(x) WLAN_RTC_CONTROL_LOAD_RTC_SET(x)
-#define RTC_CONTROL_LOAD_ALARM_MSB WLAN_RTC_CONTROL_LOAD_ALARM_MSB
-#define RTC_CONTROL_LOAD_ALARM_LSB WLAN_RTC_CONTROL_LOAD_ALARM_LSB
-#define RTC_CONTROL_LOAD_ALARM_MASK WLAN_RTC_CONTROL_LOAD_ALARM_MASK
-#define RTC_CONTROL_LOAD_ALARM_GET(x) WLAN_RTC_CONTROL_LOAD_ALARM_GET(x)
-#define RTC_CONTROL_LOAD_ALARM_SET(x) WLAN_RTC_CONTROL_LOAD_ALARM_SET(x)
-#define RTC_TIME_ADDRESS WLAN_RTC_TIME_ADDRESS
-#define RTC_TIME_OFFSET WLAN_RTC_TIME_OFFSET
-#define RTC_TIME_WEEK_DAY_MSB WLAN_RTC_TIME_WEEK_DAY_MSB
-#define RTC_TIME_WEEK_DAY_LSB WLAN_RTC_TIME_WEEK_DAY_LSB
-#define RTC_TIME_WEEK_DAY_MASK WLAN_RTC_TIME_WEEK_DAY_MASK
-#define RTC_TIME_WEEK_DAY_GET(x) WLAN_RTC_TIME_WEEK_DAY_GET(x)
-#define RTC_TIME_WEEK_DAY_SET(x) WLAN_RTC_TIME_WEEK_DAY_SET(x)
-#define RTC_TIME_HOUR_MSB WLAN_RTC_TIME_HOUR_MSB
-#define RTC_TIME_HOUR_LSB WLAN_RTC_TIME_HOUR_LSB
-#define RTC_TIME_HOUR_MASK WLAN_RTC_TIME_HOUR_MASK
-#define RTC_TIME_HOUR_GET(x) WLAN_RTC_TIME_HOUR_GET(x)
-#define RTC_TIME_HOUR_SET(x) WLAN_RTC_TIME_HOUR_SET(x)
-#define RTC_TIME_MINUTE_MSB WLAN_RTC_TIME_MINUTE_MSB
-#define RTC_TIME_MINUTE_LSB WLAN_RTC_TIME_MINUTE_LSB
-#define RTC_TIME_MINUTE_MASK WLAN_RTC_TIME_MINUTE_MASK
-#define RTC_TIME_MINUTE_GET(x) WLAN_RTC_TIME_MINUTE_GET(x)
-#define RTC_TIME_MINUTE_SET(x) WLAN_RTC_TIME_MINUTE_SET(x)
-#define RTC_TIME_SECOND_MSB WLAN_RTC_TIME_SECOND_MSB
-#define RTC_TIME_SECOND_LSB WLAN_RTC_TIME_SECOND_LSB
-#define RTC_TIME_SECOND_MASK WLAN_RTC_TIME_SECOND_MASK
-#define RTC_TIME_SECOND_GET(x) WLAN_RTC_TIME_SECOND_GET(x)
-#define RTC_TIME_SECOND_SET(x) WLAN_RTC_TIME_SECOND_SET(x)
-#define RTC_DATE_ADDRESS WLAN_RTC_DATE_ADDRESS
-#define RTC_DATE_OFFSET WLAN_RTC_DATE_OFFSET
-#define RTC_DATE_YEAR_MSB WLAN_RTC_DATE_YEAR_MSB
-#define RTC_DATE_YEAR_LSB WLAN_RTC_DATE_YEAR_LSB
-#define RTC_DATE_YEAR_MASK WLAN_RTC_DATE_YEAR_MASK
-#define RTC_DATE_YEAR_GET(x) WLAN_RTC_DATE_YEAR_GET(x)
-#define RTC_DATE_YEAR_SET(x) WLAN_RTC_DATE_YEAR_SET(x)
-#define RTC_DATE_MONTH_MSB WLAN_RTC_DATE_MONTH_MSB
-#define RTC_DATE_MONTH_LSB WLAN_RTC_DATE_MONTH_LSB
-#define RTC_DATE_MONTH_MASK WLAN_RTC_DATE_MONTH_MASK
-#define RTC_DATE_MONTH_GET(x) WLAN_RTC_DATE_MONTH_GET(x)
-#define RTC_DATE_MONTH_SET(x) WLAN_RTC_DATE_MONTH_SET(x)
-#define RTC_DATE_MONTH_DAY_MSB WLAN_RTC_DATE_MONTH_DAY_MSB
-#define RTC_DATE_MONTH_DAY_LSB WLAN_RTC_DATE_MONTH_DAY_LSB
-#define RTC_DATE_MONTH_DAY_MASK WLAN_RTC_DATE_MONTH_DAY_MASK
-#define RTC_DATE_MONTH_DAY_GET(x) WLAN_RTC_DATE_MONTH_DAY_GET(x)
-#define RTC_DATE_MONTH_DAY_SET(x) WLAN_RTC_DATE_MONTH_DAY_SET(x)
-#define RTC_SET_TIME_ADDRESS WLAN_RTC_SET_TIME_ADDRESS
-#define RTC_SET_TIME_OFFSET WLAN_RTC_SET_TIME_OFFSET
-#define RTC_SET_TIME_WEEK_DAY_MSB WLAN_RTC_SET_TIME_WEEK_DAY_MSB
-#define RTC_SET_TIME_WEEK_DAY_LSB WLAN_RTC_SET_TIME_WEEK_DAY_LSB
-#define RTC_SET_TIME_WEEK_DAY_MASK WLAN_RTC_SET_TIME_WEEK_DAY_MASK
-#define RTC_SET_TIME_WEEK_DAY_GET(x) WLAN_RTC_SET_TIME_WEEK_DAY_GET(x)
-#define RTC_SET_TIME_WEEK_DAY_SET(x) WLAN_RTC_SET_TIME_WEEK_DAY_SET(x)
-#define RTC_SET_TIME_HOUR_MSB WLAN_RTC_SET_TIME_HOUR_MSB
-#define RTC_SET_TIME_HOUR_LSB WLAN_RTC_SET_TIME_HOUR_LSB
-#define RTC_SET_TIME_HOUR_MASK WLAN_RTC_SET_TIME_HOUR_MASK
-#define RTC_SET_TIME_HOUR_GET(x) WLAN_RTC_SET_TIME_HOUR_GET(x)
-#define RTC_SET_TIME_HOUR_SET(x) WLAN_RTC_SET_TIME_HOUR_SET(x)
-#define RTC_SET_TIME_MINUTE_MSB WLAN_RTC_SET_TIME_MINUTE_MSB
-#define RTC_SET_TIME_MINUTE_LSB WLAN_RTC_SET_TIME_MINUTE_LSB
-#define RTC_SET_TIME_MINUTE_MASK WLAN_RTC_SET_TIME_MINUTE_MASK
-#define RTC_SET_TIME_MINUTE_GET(x) WLAN_RTC_SET_TIME_MINUTE_GET(x)
-#define RTC_SET_TIME_MINUTE_SET(x) WLAN_RTC_SET_TIME_MINUTE_SET(x)
-#define RTC_SET_TIME_SECOND_MSB WLAN_RTC_SET_TIME_SECOND_MSB
-#define RTC_SET_TIME_SECOND_LSB WLAN_RTC_SET_TIME_SECOND_LSB
-#define RTC_SET_TIME_SECOND_MASK WLAN_RTC_SET_TIME_SECOND_MASK
-#define RTC_SET_TIME_SECOND_GET(x) WLAN_RTC_SET_TIME_SECOND_GET(x)
-#define RTC_SET_TIME_SECOND_SET(x) WLAN_RTC_SET_TIME_SECOND_SET(x)
-#define RTC_SET_DATE_ADDRESS WLAN_RTC_SET_DATE_ADDRESS
-#define RTC_SET_DATE_OFFSET WLAN_RTC_SET_DATE_OFFSET
-#define RTC_SET_DATE_YEAR_MSB WLAN_RTC_SET_DATE_YEAR_MSB
-#define RTC_SET_DATE_YEAR_LSB WLAN_RTC_SET_DATE_YEAR_LSB
-#define RTC_SET_DATE_YEAR_MASK WLAN_RTC_SET_DATE_YEAR_MASK
-#define RTC_SET_DATE_YEAR_GET(x) WLAN_RTC_SET_DATE_YEAR_GET(x)
-#define RTC_SET_DATE_YEAR_SET(x) WLAN_RTC_SET_DATE_YEAR_SET(x)
-#define RTC_SET_DATE_MONTH_MSB WLAN_RTC_SET_DATE_MONTH_MSB
-#define RTC_SET_DATE_MONTH_LSB WLAN_RTC_SET_DATE_MONTH_LSB
-#define RTC_SET_DATE_MONTH_MASK WLAN_RTC_SET_DATE_MONTH_MASK
-#define RTC_SET_DATE_MONTH_GET(x) WLAN_RTC_SET_DATE_MONTH_GET(x)
-#define RTC_SET_DATE_MONTH_SET(x) WLAN_RTC_SET_DATE_MONTH_SET(x)
-#define RTC_SET_DATE_MONTH_DAY_MSB WLAN_RTC_SET_DATE_MONTH_DAY_MSB
-#define RTC_SET_DATE_MONTH_DAY_LSB WLAN_RTC_SET_DATE_MONTH_DAY_LSB
-#define RTC_SET_DATE_MONTH_DAY_MASK WLAN_RTC_SET_DATE_MONTH_DAY_MASK
-#define RTC_SET_DATE_MONTH_DAY_GET(x) WLAN_RTC_SET_DATE_MONTH_DAY_GET(x)
-#define RTC_SET_DATE_MONTH_DAY_SET(x) WLAN_RTC_SET_DATE_MONTH_DAY_SET(x)
-#define RTC_SET_ALARM_ADDRESS WLAN_RTC_SET_ALARM_ADDRESS
-#define RTC_SET_ALARM_OFFSET WLAN_RTC_SET_ALARM_OFFSET
-#define RTC_SET_ALARM_HOUR_MSB WLAN_RTC_SET_ALARM_HOUR_MSB
-#define RTC_SET_ALARM_HOUR_LSB WLAN_RTC_SET_ALARM_HOUR_LSB
-#define RTC_SET_ALARM_HOUR_MASK WLAN_RTC_SET_ALARM_HOUR_MASK
-#define RTC_SET_ALARM_HOUR_GET(x) WLAN_RTC_SET_ALARM_HOUR_GET(x)
-#define RTC_SET_ALARM_HOUR_SET(x) WLAN_RTC_SET_ALARM_HOUR_SET(x)
-#define RTC_SET_ALARM_MINUTE_MSB WLAN_RTC_SET_ALARM_MINUTE_MSB
-#define RTC_SET_ALARM_MINUTE_LSB WLAN_RTC_SET_ALARM_MINUTE_LSB
-#define RTC_SET_ALARM_MINUTE_MASK WLAN_RTC_SET_ALARM_MINUTE_MASK
-#define RTC_SET_ALARM_MINUTE_GET(x) WLAN_RTC_SET_ALARM_MINUTE_GET(x)
-#define RTC_SET_ALARM_MINUTE_SET(x) WLAN_RTC_SET_ALARM_MINUTE_SET(x)
-#define RTC_SET_ALARM_SECOND_MSB WLAN_RTC_SET_ALARM_SECOND_MSB
-#define RTC_SET_ALARM_SECOND_LSB WLAN_RTC_SET_ALARM_SECOND_LSB
-#define RTC_SET_ALARM_SECOND_MASK WLAN_RTC_SET_ALARM_SECOND_MASK
-#define RTC_SET_ALARM_SECOND_GET(x) WLAN_RTC_SET_ALARM_SECOND_GET(x)
-#define RTC_SET_ALARM_SECOND_SET(x) WLAN_RTC_SET_ALARM_SECOND_SET(x)
-#define RTC_CONFIG_ADDRESS WLAN_RTC_CONFIG_ADDRESS
-#define RTC_CONFIG_OFFSET WLAN_RTC_CONFIG_OFFSET
-#define RTC_CONFIG_BCD_MSB WLAN_RTC_CONFIG_BCD_MSB
-#define RTC_CONFIG_BCD_LSB WLAN_RTC_CONFIG_BCD_LSB
-#define RTC_CONFIG_BCD_MASK WLAN_RTC_CONFIG_BCD_MASK
-#define RTC_CONFIG_BCD_GET(x) WLAN_RTC_CONFIG_BCD_GET(x)
-#define RTC_CONFIG_BCD_SET(x) WLAN_RTC_CONFIG_BCD_SET(x)
-#define RTC_CONFIG_TWELVE_HOUR_MSB WLAN_RTC_CONFIG_TWELVE_HOUR_MSB
-#define RTC_CONFIG_TWELVE_HOUR_LSB WLAN_RTC_CONFIG_TWELVE_HOUR_LSB
-#define RTC_CONFIG_TWELVE_HOUR_MASK WLAN_RTC_CONFIG_TWELVE_HOUR_MASK
-#define RTC_CONFIG_TWELVE_HOUR_GET(x) WLAN_RTC_CONFIG_TWELVE_HOUR_GET(x)
-#define RTC_CONFIG_TWELVE_HOUR_SET(x) WLAN_RTC_CONFIG_TWELVE_HOUR_SET(x)
-#define RTC_CONFIG_DSE_MSB WLAN_RTC_CONFIG_DSE_MSB
-#define RTC_CONFIG_DSE_LSB WLAN_RTC_CONFIG_DSE_LSB
-#define RTC_CONFIG_DSE_MASK WLAN_RTC_CONFIG_DSE_MASK
-#define RTC_CONFIG_DSE_GET(x) WLAN_RTC_CONFIG_DSE_GET(x)
-#define RTC_CONFIG_DSE_SET(x) WLAN_RTC_CONFIG_DSE_SET(x)
-#define RTC_ALARM_STATUS_ADDRESS WLAN_RTC_ALARM_STATUS_ADDRESS
-#define RTC_ALARM_STATUS_OFFSET WLAN_RTC_ALARM_STATUS_OFFSET
-#define RTC_ALARM_STATUS_ENABLE_MSB WLAN_RTC_ALARM_STATUS_ENABLE_MSB
-#define RTC_ALARM_STATUS_ENABLE_LSB WLAN_RTC_ALARM_STATUS_ENABLE_LSB
-#define RTC_ALARM_STATUS_ENABLE_MASK WLAN_RTC_ALARM_STATUS_ENABLE_MASK
-#define RTC_ALARM_STATUS_ENABLE_GET(x) WLAN_RTC_ALARM_STATUS_ENABLE_GET(x)
-#define RTC_ALARM_STATUS_ENABLE_SET(x) WLAN_RTC_ALARM_STATUS_ENABLE_SET(x)
-#define RTC_ALARM_STATUS_INTERRUPT_MSB WLAN_RTC_ALARM_STATUS_INTERRUPT_MSB
-#define RTC_ALARM_STATUS_INTERRUPT_LSB WLAN_RTC_ALARM_STATUS_INTERRUPT_LSB
-#define RTC_ALARM_STATUS_INTERRUPT_MASK WLAN_RTC_ALARM_STATUS_INTERRUPT_MASK
-#define RTC_ALARM_STATUS_INTERRUPT_GET(x) WLAN_RTC_ALARM_STATUS_INTERRUPT_GET(x)
-#define RTC_ALARM_STATUS_INTERRUPT_SET(x) WLAN_RTC_ALARM_STATUS_INTERRUPT_SET(x)
-#define UART_WAKEUP_ADDRESS WLAN_UART_WAKEUP_ADDRESS
-#define UART_WAKEUP_OFFSET WLAN_UART_WAKEUP_OFFSET
-#define UART_WAKEUP_ENABLE_MSB WLAN_UART_WAKEUP_ENABLE_MSB
-#define UART_WAKEUP_ENABLE_LSB WLAN_UART_WAKEUP_ENABLE_LSB
-#define UART_WAKEUP_ENABLE_MASK WLAN_UART_WAKEUP_ENABLE_MASK
-#define UART_WAKEUP_ENABLE_GET(x) WLAN_UART_WAKEUP_ENABLE_GET(x)
-#define UART_WAKEUP_ENABLE_SET(x) WLAN_UART_WAKEUP_ENABLE_SET(x)
#define RESET_CAUSE_ADDRESS WLAN_RESET_CAUSE_ADDRESS
#define RESET_CAUSE_OFFSET WLAN_RESET_CAUSE_OFFSET
#define RESET_CAUSE_LAST_MSB WLAN_RESET_CAUSE_LAST_MSB
@@ -753,49 +157,6 @@
#define SYSTEM_SLEEP_DISABLE_MASK WLAN_SYSTEM_SLEEP_DISABLE_MASK
#define SYSTEM_SLEEP_DISABLE_GET(x) WLAN_SYSTEM_SLEEP_DISABLE_GET(x)
#define SYSTEM_SLEEP_DISABLE_SET(x) WLAN_SYSTEM_SLEEP_DISABLE_SET(x)
-#define SDIO_WRAPPER_ADDRESS WLAN_SDIO_WRAPPER_ADDRESS
-#define SDIO_WRAPPER_OFFSET WLAN_SDIO_WRAPPER_OFFSET
-#define SDIO_WRAPPER_SLEEP_MSB WLAN_SDIO_WRAPPER_SLEEP_MSB
-#define SDIO_WRAPPER_SLEEP_LSB WLAN_SDIO_WRAPPER_SLEEP_LSB
-#define SDIO_WRAPPER_SLEEP_MASK WLAN_SDIO_WRAPPER_SLEEP_MASK
-#define SDIO_WRAPPER_SLEEP_GET(x) WLAN_SDIO_WRAPPER_SLEEP_GET(x)
-#define SDIO_WRAPPER_SLEEP_SET(x) WLAN_SDIO_WRAPPER_SLEEP_SET(x)
-#define SDIO_WRAPPER_WAKEUP_MSB WLAN_SDIO_WRAPPER_WAKEUP_MSB
-#define SDIO_WRAPPER_WAKEUP_LSB WLAN_SDIO_WRAPPER_WAKEUP_LSB
-#define SDIO_WRAPPER_WAKEUP_MASK WLAN_SDIO_WRAPPER_WAKEUP_MASK
-#define SDIO_WRAPPER_WAKEUP_GET(x) WLAN_SDIO_WRAPPER_WAKEUP_GET(x)
-#define SDIO_WRAPPER_WAKEUP_SET(x) WLAN_SDIO_WRAPPER_WAKEUP_SET(x)
-#define SDIO_WRAPPER_SOC_ON_MSB WLAN_SDIO_WRAPPER_SOC_ON_MSB
-#define SDIO_WRAPPER_SOC_ON_LSB WLAN_SDIO_WRAPPER_SOC_ON_LSB
-#define SDIO_WRAPPER_SOC_ON_MASK WLAN_SDIO_WRAPPER_SOC_ON_MASK
-#define SDIO_WRAPPER_SOC_ON_GET(x) WLAN_SDIO_WRAPPER_SOC_ON_GET(x)
-#define SDIO_WRAPPER_SOC_ON_SET(x) WLAN_SDIO_WRAPPER_SOC_ON_SET(x)
-#define SDIO_WRAPPER_ON_MSB WLAN_SDIO_WRAPPER_ON_MSB
-#define SDIO_WRAPPER_ON_LSB WLAN_SDIO_WRAPPER_ON_LSB
-#define SDIO_WRAPPER_ON_MASK WLAN_SDIO_WRAPPER_ON_MASK
-#define SDIO_WRAPPER_ON_GET(x) WLAN_SDIO_WRAPPER_ON_GET(x)
-#define SDIO_WRAPPER_ON_SET(x) WLAN_SDIO_WRAPPER_ON_SET(x)
-#define MAC_SLEEP_CONTROL_ADDRESS WLAN_MAC_SLEEP_CONTROL_ADDRESS
-#define MAC_SLEEP_CONTROL_OFFSET WLAN_MAC_SLEEP_CONTROL_OFFSET
-#define MAC_SLEEP_CONTROL_ENABLE_MSB WLAN_MAC_SLEEP_CONTROL_ENABLE_MSB
-#define MAC_SLEEP_CONTROL_ENABLE_LSB WLAN_MAC_SLEEP_CONTROL_ENABLE_LSB
-#define MAC_SLEEP_CONTROL_ENABLE_MASK WLAN_MAC_SLEEP_CONTROL_ENABLE_MASK
-#define MAC_SLEEP_CONTROL_ENABLE_GET(x) WLAN_MAC_SLEEP_CONTROL_ENABLE_GET(x)
-#define MAC_SLEEP_CONTROL_ENABLE_SET(x) WLAN_MAC_SLEEP_CONTROL_ENABLE_SET(x)
-#define KEEP_AWAKE_ADDRESS WLAN_KEEP_AWAKE_ADDRESS
-#define KEEP_AWAKE_OFFSET WLAN_KEEP_AWAKE_OFFSET
-#define KEEP_AWAKE_COUNT_MSB WLAN_KEEP_AWAKE_COUNT_MSB
-#define KEEP_AWAKE_COUNT_LSB WLAN_KEEP_AWAKE_COUNT_LSB
-#define KEEP_AWAKE_COUNT_MASK WLAN_KEEP_AWAKE_COUNT_MASK
-#define KEEP_AWAKE_COUNT_GET(x) WLAN_KEEP_AWAKE_COUNT_GET(x)
-#define KEEP_AWAKE_COUNT_SET(x) WLAN_KEEP_AWAKE_COUNT_SET(x)
-#define LPO_CAL_TIME_ADDRESS WLAN_LPO_CAL_TIME_ADDRESS
-#define LPO_CAL_TIME_OFFSET WLAN_LPO_CAL_TIME_OFFSET
-#define LPO_CAL_TIME_LENGTH_MSB WLAN_LPO_CAL_TIME_LENGTH_MSB
-#define LPO_CAL_TIME_LENGTH_LSB WLAN_LPO_CAL_TIME_LENGTH_LSB
-#define LPO_CAL_TIME_LENGTH_MASK WLAN_LPO_CAL_TIME_LENGTH_MASK
-#define LPO_CAL_TIME_LENGTH_GET(x) WLAN_LPO_CAL_TIME_LENGTH_GET(x)
-#define LPO_CAL_TIME_LENGTH_SET(x) WLAN_LPO_CAL_TIME_LENGTH_SET(x)
#define LPO_INIT_DIVIDEND_INT_ADDRESS WLAN_LPO_INIT_DIVIDEND_INT_ADDRESS
#define LPO_INIT_DIVIDEND_INT_OFFSET WLAN_LPO_INIT_DIVIDEND_INT_OFFSET
#define LPO_INIT_DIVIDEND_INT_VALUE_MSB WLAN_LPO_INIT_DIVIDEND_INT_VALUE_MSB
@@ -822,154 +183,5 @@
#define LPO_CAL_COUNT_MASK WLAN_LPO_CAL_COUNT_MASK
#define LPO_CAL_COUNT_GET(x) WLAN_LPO_CAL_COUNT_GET(x)
#define LPO_CAL_COUNT_SET(x) WLAN_LPO_CAL_COUNT_SET(x)
-#define LPO_CAL_TEST_CONTROL_ADDRESS WLAN_LPO_CAL_TEST_CONTROL_ADDRESS
-#define LPO_CAL_TEST_CONTROL_OFFSET WLAN_LPO_CAL_TEST_CONTROL_OFFSET
-#define LPO_CAL_TEST_CONTROL_ENABLE_MSB WLAN_LPO_CAL_TEST_CONTROL_ENABLE_MSB
-#define LPO_CAL_TEST_CONTROL_ENABLE_LSB WLAN_LPO_CAL_TEST_CONTROL_ENABLE_LSB
-#define LPO_CAL_TEST_CONTROL_ENABLE_MASK WLAN_LPO_CAL_TEST_CONTROL_ENABLE_MASK
-#define LPO_CAL_TEST_CONTROL_ENABLE_GET(x) WLAN_LPO_CAL_TEST_CONTROL_ENABLE_GET(x)
-#define LPO_CAL_TEST_CONTROL_ENABLE_SET(x) WLAN_LPO_CAL_TEST_CONTROL_ENABLE_SET(x)
-#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_MSB WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MSB
-#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB
-#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK
-#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_GET(x) WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_GET(x)
-#define LPO_CAL_TEST_CONTROL_RTC_CYCLES_SET(x) WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_SET(x)
-#define LPO_CAL_TEST_STATUS_ADDRESS WLAN_LPO_CAL_TEST_STATUS_ADDRESS
-#define LPO_CAL_TEST_STATUS_OFFSET WLAN_LPO_CAL_TEST_STATUS_OFFSET
-#define LPO_CAL_TEST_STATUS_READY_MSB WLAN_LPO_CAL_TEST_STATUS_READY_MSB
-#define LPO_CAL_TEST_STATUS_READY_LSB WLAN_LPO_CAL_TEST_STATUS_READY_LSB
-#define LPO_CAL_TEST_STATUS_READY_MASK WLAN_LPO_CAL_TEST_STATUS_READY_MASK
-#define LPO_CAL_TEST_STATUS_READY_GET(x) WLAN_LPO_CAL_TEST_STATUS_READY_GET(x)
-#define LPO_CAL_TEST_STATUS_READY_SET(x) WLAN_LPO_CAL_TEST_STATUS_READY_SET(x)
-#define LPO_CAL_TEST_STATUS_COUNT_MSB WLAN_LPO_CAL_TEST_STATUS_COUNT_MSB
-#define LPO_CAL_TEST_STATUS_COUNT_LSB WLAN_LPO_CAL_TEST_STATUS_COUNT_LSB
-#define LPO_CAL_TEST_STATUS_COUNT_MASK WLAN_LPO_CAL_TEST_STATUS_COUNT_MASK
-#define LPO_CAL_TEST_STATUS_COUNT_GET(x) WLAN_LPO_CAL_TEST_STATUS_COUNT_GET(x)
-#define LPO_CAL_TEST_STATUS_COUNT_SET(x) WLAN_LPO_CAL_TEST_STATUS_COUNT_SET(x)
-#define CHIP_ID_ADDRESS WLAN_CHIP_ID_ADDRESS
-#define CHIP_ID_OFFSET WLAN_CHIP_ID_OFFSET
-#define CHIP_ID_DEVICE_ID_MSB WLAN_CHIP_ID_DEVICE_ID_MSB
-#define CHIP_ID_DEVICE_ID_LSB WLAN_CHIP_ID_DEVICE_ID_LSB
-#define CHIP_ID_DEVICE_ID_MASK WLAN_CHIP_ID_DEVICE_ID_MASK
-#define CHIP_ID_DEVICE_ID_GET(x) WLAN_CHIP_ID_DEVICE_ID_GET(x)
-#define CHIP_ID_DEVICE_ID_SET(x) WLAN_CHIP_ID_DEVICE_ID_SET(x)
-#define CHIP_ID_CONFIG_ID_MSB WLAN_CHIP_ID_CONFIG_ID_MSB
-#define CHIP_ID_CONFIG_ID_LSB WLAN_CHIP_ID_CONFIG_ID_LSB
-#define CHIP_ID_CONFIG_ID_MASK WLAN_CHIP_ID_CONFIG_ID_MASK
-#define CHIP_ID_CONFIG_ID_GET(x) WLAN_CHIP_ID_CONFIG_ID_GET(x)
-#define CHIP_ID_CONFIG_ID_SET(x) WLAN_CHIP_ID_CONFIG_ID_SET(x)
-#define CHIP_ID_VERSION_ID_MSB WLAN_CHIP_ID_VERSION_ID_MSB
-#define CHIP_ID_VERSION_ID_LSB WLAN_CHIP_ID_VERSION_ID_LSB
-#define CHIP_ID_VERSION_ID_MASK WLAN_CHIP_ID_VERSION_ID_MASK
-#define CHIP_ID_VERSION_ID_GET(x) WLAN_CHIP_ID_VERSION_ID_GET(x)
-#define CHIP_ID_VERSION_ID_SET(x) WLAN_CHIP_ID_VERSION_ID_SET(x)
-#define DERIVED_RTC_CLK_ADDRESS WLAN_DERIVED_RTC_CLK_ADDRESS
-#define DERIVED_RTC_CLK_OFFSET WLAN_DERIVED_RTC_CLK_OFFSET
-#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MSB WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MSB
-#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB
-#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK
-#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_GET(x) WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_GET(x)
-#define DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_SET(x) WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_SET(x)
-#define DERIVED_RTC_CLK_EXTERNAL_DETECT_MSB WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_MSB
-#define DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB
-#define DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK
-#define DERIVED_RTC_CLK_EXTERNAL_DETECT_GET(x) WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_GET(x)
-#define DERIVED_RTC_CLK_EXTERNAL_DETECT_SET(x) WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_SET(x)
-#define DERIVED_RTC_CLK_FORCE_MSB WLAN_DERIVED_RTC_CLK_FORCE_MSB
-#define DERIVED_RTC_CLK_FORCE_LSB WLAN_DERIVED_RTC_CLK_FORCE_LSB
-#define DERIVED_RTC_CLK_FORCE_MASK WLAN_DERIVED_RTC_CLK_FORCE_MASK
-#define DERIVED_RTC_CLK_FORCE_GET(x) WLAN_DERIVED_RTC_CLK_FORCE_GET(x)
-#define DERIVED_RTC_CLK_FORCE_SET(x) WLAN_DERIVED_RTC_CLK_FORCE_SET(x)
-#define DERIVED_RTC_CLK_PERIOD_MSB WLAN_DERIVED_RTC_CLK_PERIOD_MSB
-#define DERIVED_RTC_CLK_PERIOD_LSB WLAN_DERIVED_RTC_CLK_PERIOD_LSB
-#define DERIVED_RTC_CLK_PERIOD_MASK WLAN_DERIVED_RTC_CLK_PERIOD_MASK
-#define DERIVED_RTC_CLK_PERIOD_GET(x) WLAN_DERIVED_RTC_CLK_PERIOD_GET(x)
-#define DERIVED_RTC_CLK_PERIOD_SET(x) WLAN_DERIVED_RTC_CLK_PERIOD_SET(x)
-#define POWER_REG_ADDRESS WLAN_POWER_REG_ADDRESS
-#define POWER_REG_OFFSET WLAN_POWER_REG_OFFSET
-#define POWER_REG_SLEEP_MAKE_N_BREAK_EN_MSB WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_MSB
-#define POWER_REG_SLEEP_MAKE_N_BREAK_EN_LSB WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_LSB
-#define POWER_REG_SLEEP_MAKE_N_BREAK_EN_MASK WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_MASK
-#define POWER_REG_SLEEP_MAKE_N_BREAK_EN_GET(x) WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_GET(x)
-#define POWER_REG_SLEEP_MAKE_N_BREAK_EN_SET(x) WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_SET(x)
-#define POWER_REG_DEBUG_EN_MSB WLAN_POWER_REG_DEBUG_EN_MSB
-#define POWER_REG_DEBUG_EN_LSB WLAN_POWER_REG_DEBUG_EN_LSB
-#define POWER_REG_DEBUG_EN_MASK WLAN_POWER_REG_DEBUG_EN_MASK
-#define POWER_REG_DEBUG_EN_GET(x) WLAN_POWER_REG_DEBUG_EN_GET(x)
-#define POWER_REG_DEBUG_EN_SET(x) WLAN_POWER_REG_DEBUG_EN_SET(x)
-#define POWER_REG_WLAN_BB_PWD_EN_MSB WLAN_POWER_REG_WLAN_BB_PWD_EN_MSB
-#define POWER_REG_WLAN_BB_PWD_EN_LSB WLAN_POWER_REG_WLAN_BB_PWD_EN_LSB
-#define POWER_REG_WLAN_BB_PWD_EN_MASK WLAN_POWER_REG_WLAN_BB_PWD_EN_MASK
-#define POWER_REG_WLAN_BB_PWD_EN_GET(x) WLAN_POWER_REG_WLAN_BB_PWD_EN_GET(x)
-#define POWER_REG_WLAN_BB_PWD_EN_SET(x) WLAN_POWER_REG_WLAN_BB_PWD_EN_SET(x)
-#define POWER_REG_WLAN_MAC_PWD_EN_MSB WLAN_POWER_REG_WLAN_MAC_PWD_EN_MSB
-#define POWER_REG_WLAN_MAC_PWD_EN_LSB WLAN_POWER_REG_WLAN_MAC_PWD_EN_LSB
-#define POWER_REG_WLAN_MAC_PWD_EN_MASK WLAN_POWER_REG_WLAN_MAC_PWD_EN_MASK
-#define POWER_REG_WLAN_MAC_PWD_EN_GET(x) WLAN_POWER_REG_WLAN_MAC_PWD_EN_GET(x)
-#define POWER_REG_WLAN_MAC_PWD_EN_SET(x) WLAN_POWER_REG_WLAN_MAC_PWD_EN_SET(x)
-#define POWER_REG_VLVL_MSB WLAN_POWER_REG_VLVL_MSB
-#define POWER_REG_VLVL_LSB WLAN_POWER_REG_VLVL_LSB
-#define POWER_REG_VLVL_MASK WLAN_POWER_REG_VLVL_MASK
-#define POWER_REG_VLVL_GET(x) WLAN_POWER_REG_VLVL_GET(x)
-#define POWER_REG_VLVL_SET(x) WLAN_POWER_REG_VLVL_SET(x)
-#define POWER_REG_CPU_INT_ENABLE_MSB WLAN_POWER_REG_CPU_INT_ENABLE_MSB
-#define POWER_REG_CPU_INT_ENABLE_LSB WLAN_POWER_REG_CPU_INT_ENABLE_LSB
-#define POWER_REG_CPU_INT_ENABLE_MASK WLAN_POWER_REG_CPU_INT_ENABLE_MASK
-#define POWER_REG_CPU_INT_ENABLE_GET(x) WLAN_POWER_REG_CPU_INT_ENABLE_GET(x)
-#define POWER_REG_CPU_INT_ENABLE_SET(x) WLAN_POWER_REG_CPU_INT_ENABLE_SET(x)
-#define POWER_REG_WLAN_ISO_DIS_MSB WLAN_POWER_REG_WLAN_ISO_DIS_MSB
-#define POWER_REG_WLAN_ISO_DIS_LSB WLAN_POWER_REG_WLAN_ISO_DIS_LSB
-#define POWER_REG_WLAN_ISO_DIS_MASK WLAN_POWER_REG_WLAN_ISO_DIS_MASK
-#define POWER_REG_WLAN_ISO_DIS_GET(x) WLAN_POWER_REG_WLAN_ISO_DIS_GET(x)
-#define POWER_REG_WLAN_ISO_DIS_SET(x) WLAN_POWER_REG_WLAN_ISO_DIS_SET(x)
-#define POWER_REG_WLAN_ISO_CNTL_MSB WLAN_POWER_REG_WLAN_ISO_CNTL_MSB
-#define POWER_REG_WLAN_ISO_CNTL_LSB WLAN_POWER_REG_WLAN_ISO_CNTL_LSB
-#define POWER_REG_WLAN_ISO_CNTL_MASK WLAN_POWER_REG_WLAN_ISO_CNTL_MASK
-#define POWER_REG_WLAN_ISO_CNTL_GET(x) WLAN_POWER_REG_WLAN_ISO_CNTL_GET(x)
-#define POWER_REG_WLAN_ISO_CNTL_SET(x) WLAN_POWER_REG_WLAN_ISO_CNTL_SET(x)
-#define POWER_REG_RADIO_PWD_EN_MSB WLAN_POWER_REG_RADIO_PWD_EN_MSB
-#define POWER_REG_RADIO_PWD_EN_LSB WLAN_POWER_REG_RADIO_PWD_EN_LSB
-#define POWER_REG_RADIO_PWD_EN_MASK WLAN_POWER_REG_RADIO_PWD_EN_MASK
-#define POWER_REG_RADIO_PWD_EN_GET(x) WLAN_POWER_REG_RADIO_PWD_EN_GET(x)
-#define POWER_REG_RADIO_PWD_EN_SET(x) WLAN_POWER_REG_RADIO_PWD_EN_SET(x)
-#define POWER_REG_SOC_ISO_EN_MSB WLAN_POWER_REG_SOC_ISO_EN_MSB
-#define POWER_REG_SOC_ISO_EN_LSB WLAN_POWER_REG_SOC_ISO_EN_LSB
-#define POWER_REG_SOC_ISO_EN_MASK WLAN_POWER_REG_SOC_ISO_EN_MASK
-#define POWER_REG_SOC_ISO_EN_GET(x) WLAN_POWER_REG_SOC_ISO_EN_GET(x)
-#define POWER_REG_SOC_ISO_EN_SET(x) WLAN_POWER_REG_SOC_ISO_EN_SET(x)
-#define POWER_REG_WLAN_ISO_EN_MSB WLAN_POWER_REG_WLAN_ISO_EN_MSB
-#define POWER_REG_WLAN_ISO_EN_LSB WLAN_POWER_REG_WLAN_ISO_EN_LSB
-#define POWER_REG_WLAN_ISO_EN_MASK WLAN_POWER_REG_WLAN_ISO_EN_MASK
-#define POWER_REG_WLAN_ISO_EN_GET(x) WLAN_POWER_REG_WLAN_ISO_EN_GET(x)
-#define POWER_REG_WLAN_ISO_EN_SET(x) WLAN_POWER_REG_WLAN_ISO_EN_SET(x)
-#define POWER_REG_WLAN_PWD_EN_MSB WLAN_POWER_REG_WLAN_PWD_EN_MSB
-#define POWER_REG_WLAN_PWD_EN_LSB WLAN_POWER_REG_WLAN_PWD_EN_LSB
-#define POWER_REG_WLAN_PWD_EN_MASK WLAN_POWER_REG_WLAN_PWD_EN_MASK
-#define POWER_REG_WLAN_PWD_EN_GET(x) WLAN_POWER_REG_WLAN_PWD_EN_GET(x)
-#define POWER_REG_WLAN_PWD_EN_SET(x) WLAN_POWER_REG_WLAN_PWD_EN_SET(x)
-#define POWER_REG_POWER_EN_MSB WLAN_POWER_REG_POWER_EN_MSB
-#define POWER_REG_POWER_EN_LSB WLAN_POWER_REG_POWER_EN_LSB
-#define POWER_REG_POWER_EN_MASK WLAN_POWER_REG_POWER_EN_MASK
-#define POWER_REG_POWER_EN_GET(x) WLAN_POWER_REG_POWER_EN_GET(x)
-#define POWER_REG_POWER_EN_SET(x) WLAN_POWER_REG_POWER_EN_SET(x)
-#define CORE_CLK_CTRL_ADDRESS WLAN_CORE_CLK_CTRL_ADDRESS
-#define CORE_CLK_CTRL_OFFSET WLAN_CORE_CLK_CTRL_OFFSET
-#define CORE_CLK_CTRL_DIV_MSB WLAN_CORE_CLK_CTRL_DIV_MSB
-#define CORE_CLK_CTRL_DIV_LSB WLAN_CORE_CLK_CTRL_DIV_LSB
-#define CORE_CLK_CTRL_DIV_MASK WLAN_CORE_CLK_CTRL_DIV_MASK
-#define CORE_CLK_CTRL_DIV_GET(x) WLAN_CORE_CLK_CTRL_DIV_GET(x)
-#define CORE_CLK_CTRL_DIV_SET(x) WLAN_CORE_CLK_CTRL_DIV_SET(x)
-#define GPIO_WAKEUP_CONTROL_ADDRESS WLAN_GPIO_WAKEUP_CONTROL_ADDRESS
-#define GPIO_WAKEUP_CONTROL_OFFSET WLAN_GPIO_WAKEUP_CONTROL_OFFSET
-#define GPIO_WAKEUP_CONTROL_ENABLE_MSB WLAN_GPIO_WAKEUP_CONTROL_ENABLE_MSB
-#define GPIO_WAKEUP_CONTROL_ENABLE_LSB WLAN_GPIO_WAKEUP_CONTROL_ENABLE_LSB
-#define GPIO_WAKEUP_CONTROL_ENABLE_MASK WLAN_GPIO_WAKEUP_CONTROL_ENABLE_MASK
-#define GPIO_WAKEUP_CONTROL_ENABLE_GET(x) WLAN_GPIO_WAKEUP_CONTROL_ENABLE_GET(x)
-#define GPIO_WAKEUP_CONTROL_ENABLE_SET(x) WLAN_GPIO_WAKEUP_CONTROL_ENABLE_SET(x)
-
#endif
-#endif
-
-
-
diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/rtc_wlan_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/rtc_wlan_reg.h
index abf8726..5c048ff 100644
--- a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/rtc_wlan_reg.h
+++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/rtc_wlan_reg.h
@@ -97,102 +97,6 @@
#define WLAN_RESET_CONTROL_SI0_RST_GET(x) (((x) & WLAN_RESET_CONTROL_SI0_RST_MASK) >> WLAN_RESET_CONTROL_SI0_RST_LSB)
#define WLAN_RESET_CONTROL_SI0_RST_SET(x) (((x) << WLAN_RESET_CONTROL_SI0_RST_LSB) & WLAN_RESET_CONTROL_SI0_RST_MASK)
-#define WLAN_XTAL_CONTROL_ADDRESS 0x00000004
-#define WLAN_XTAL_CONTROL_OFFSET 0x00000004
-#define WLAN_XTAL_CONTROL_TCXO_MSB 0
-#define WLAN_XTAL_CONTROL_TCXO_LSB 0
-#define WLAN_XTAL_CONTROL_TCXO_MASK 0x00000001
-#define WLAN_XTAL_CONTROL_TCXO_GET(x) (((x) & WLAN_XTAL_CONTROL_TCXO_MASK) >> WLAN_XTAL_CONTROL_TCXO_LSB)
-#define WLAN_XTAL_CONTROL_TCXO_SET(x) (((x) << WLAN_XTAL_CONTROL_TCXO_LSB) & WLAN_XTAL_CONTROL_TCXO_MASK)
-
-#define WLAN_TCXO_DETECT_ADDRESS 0x00000008
-#define WLAN_TCXO_DETECT_OFFSET 0x00000008
-#define WLAN_TCXO_DETECT_PRESENT_MSB 0
-#define WLAN_TCXO_DETECT_PRESENT_LSB 0
-#define WLAN_TCXO_DETECT_PRESENT_MASK 0x00000001
-#define WLAN_TCXO_DETECT_PRESENT_GET(x) (((x) & WLAN_TCXO_DETECT_PRESENT_MASK) >> WLAN_TCXO_DETECT_PRESENT_LSB)
-#define WLAN_TCXO_DETECT_PRESENT_SET(x) (((x) << WLAN_TCXO_DETECT_PRESENT_LSB) & WLAN_TCXO_DETECT_PRESENT_MASK)
-
-#define WLAN_XTAL_TEST_ADDRESS 0x0000000c
-#define WLAN_XTAL_TEST_OFFSET 0x0000000c
-#define WLAN_XTAL_TEST_NOTCXODET_MSB 0
-#define WLAN_XTAL_TEST_NOTCXODET_LSB 0
-#define WLAN_XTAL_TEST_NOTCXODET_MASK 0x00000001
-#define WLAN_XTAL_TEST_NOTCXODET_GET(x) (((x) & WLAN_XTAL_TEST_NOTCXODET_MASK) >> WLAN_XTAL_TEST_NOTCXODET_LSB)
-#define WLAN_XTAL_TEST_NOTCXODET_SET(x) (((x) << WLAN_XTAL_TEST_NOTCXODET_LSB) & WLAN_XTAL_TEST_NOTCXODET_MASK)
-
-#define WLAN_QUADRATURE_ADDRESS 0x00000010
-#define WLAN_QUADRATURE_OFFSET 0x00000010
-#define WLAN_QUADRATURE_ADC_MSB 7
-#define WLAN_QUADRATURE_ADC_LSB 4
-#define WLAN_QUADRATURE_ADC_MASK 0x000000f0
-#define WLAN_QUADRATURE_ADC_GET(x) (((x) & WLAN_QUADRATURE_ADC_MASK) >> WLAN_QUADRATURE_ADC_LSB)
-#define WLAN_QUADRATURE_ADC_SET(x) (((x) << WLAN_QUADRATURE_ADC_LSB) & WLAN_QUADRATURE_ADC_MASK)
-#define WLAN_QUADRATURE_SEL_MSB 2
-#define WLAN_QUADRATURE_SEL_LSB 2
-#define WLAN_QUADRATURE_SEL_MASK 0x00000004
-#define WLAN_QUADRATURE_SEL_GET(x) (((x) & WLAN_QUADRATURE_SEL_MASK) >> WLAN_QUADRATURE_SEL_LSB)
-#define WLAN_QUADRATURE_SEL_SET(x) (((x) << WLAN_QUADRATURE_SEL_LSB) & WLAN_QUADRATURE_SEL_MASK)
-#define WLAN_QUADRATURE_DAC_MSB 1
-#define WLAN_QUADRATURE_DAC_LSB 0
-#define WLAN_QUADRATURE_DAC_MASK 0x00000003
-#define WLAN_QUADRATURE_DAC_GET(x) (((x) & WLAN_QUADRATURE_DAC_MASK) >> WLAN_QUADRATURE_DAC_LSB)
-#define WLAN_QUADRATURE_DAC_SET(x) (((x) << WLAN_QUADRATURE_DAC_LSB) & WLAN_QUADRATURE_DAC_MASK)
-
-#define WLAN_PLL_CONTROL_ADDRESS 0x00000014
-#define WLAN_PLL_CONTROL_OFFSET 0x00000014
-#define WLAN_PLL_CONTROL_DIG_TEST_CLK_MSB 20
-#define WLAN_PLL_CONTROL_DIG_TEST_CLK_LSB 20
-#define WLAN_PLL_CONTROL_DIG_TEST_CLK_MASK 0x00100000
-#define WLAN_PLL_CONTROL_DIG_TEST_CLK_GET(x) (((x) & WLAN_PLL_CONTROL_DIG_TEST_CLK_MASK) >> WLAN_PLL_CONTROL_DIG_TEST_CLK_LSB)
-#define WLAN_PLL_CONTROL_DIG_TEST_CLK_SET(x) (((x) << WLAN_PLL_CONTROL_DIG_TEST_CLK_LSB) & WLAN_PLL_CONTROL_DIG_TEST_CLK_MASK)
-#define WLAN_PLL_CONTROL_MAC_OVERRIDE_MSB 19
-#define WLAN_PLL_CONTROL_MAC_OVERRIDE_LSB 19
-#define WLAN_PLL_CONTROL_MAC_OVERRIDE_MASK 0x00080000
-#define WLAN_PLL_CONTROL_MAC_OVERRIDE_GET(x) (((x) & WLAN_PLL_CONTROL_MAC_OVERRIDE_MASK) >> WLAN_PLL_CONTROL_MAC_OVERRIDE_LSB)
-#define WLAN_PLL_CONTROL_MAC_OVERRIDE_SET(x) (((x) << WLAN_PLL_CONTROL_MAC_OVERRIDE_LSB) & WLAN_PLL_CONTROL_MAC_OVERRIDE_MASK)
-#define WLAN_PLL_CONTROL_NOPWD_MSB 18
-#define WLAN_PLL_CONTROL_NOPWD_LSB 18
-#define WLAN_PLL_CONTROL_NOPWD_MASK 0x00040000
-#define WLAN_PLL_CONTROL_NOPWD_GET(x) (((x) & WLAN_PLL_CONTROL_NOPWD_MASK) >> WLAN_PLL_CONTROL_NOPWD_LSB)
-#define WLAN_PLL_CONTROL_NOPWD_SET(x) (((x) << WLAN_PLL_CONTROL_NOPWD_LSB) & WLAN_PLL_CONTROL_NOPWD_MASK)
-#define WLAN_PLL_CONTROL_UPDATING_MSB 17
-#define WLAN_PLL_CONTROL_UPDATING_LSB 17
-#define WLAN_PLL_CONTROL_UPDATING_MASK 0x00020000
-#define WLAN_PLL_CONTROL_UPDATING_GET(x) (((x) & WLAN_PLL_CONTROL_UPDATING_MASK) >> WLAN_PLL_CONTROL_UPDATING_LSB)
-#define WLAN_PLL_CONTROL_UPDATING_SET(x) (((x) << WLAN_PLL_CONTROL_UPDATING_LSB) & WLAN_PLL_CONTROL_UPDATING_MASK)
-#define WLAN_PLL_CONTROL_BYPASS_MSB 16
-#define WLAN_PLL_CONTROL_BYPASS_LSB 16
-#define WLAN_PLL_CONTROL_BYPASS_MASK 0x00010000
-#define WLAN_PLL_CONTROL_BYPASS_GET(x) (((x) & WLAN_PLL_CONTROL_BYPASS_MASK) >> WLAN_PLL_CONTROL_BYPASS_LSB)
-#define WLAN_PLL_CONTROL_BYPASS_SET(x) (((x) << WLAN_PLL_CONTROL_BYPASS_LSB) & WLAN_PLL_CONTROL_BYPASS_MASK)
-#define WLAN_PLL_CONTROL_REFDIV_MSB 15
-#define WLAN_PLL_CONTROL_REFDIV_LSB 12
-#define WLAN_PLL_CONTROL_REFDIV_MASK 0x0000f000
-#define WLAN_PLL_CONTROL_REFDIV_GET(x) (((x) & WLAN_PLL_CONTROL_REFDIV_MASK) >> WLAN_PLL_CONTROL_REFDIV_LSB)
-#define WLAN_PLL_CONTROL_REFDIV_SET(x) (((x) << WLAN_PLL_CONTROL_REFDIV_LSB) & WLAN_PLL_CONTROL_REFDIV_MASK)
-#define WLAN_PLL_CONTROL_DIV_MSB 9
-#define WLAN_PLL_CONTROL_DIV_LSB 0
-#define WLAN_PLL_CONTROL_DIV_MASK 0x000003ff
-#define WLAN_PLL_CONTROL_DIV_GET(x) (((x) & WLAN_PLL_CONTROL_DIV_MASK) >> WLAN_PLL_CONTROL_DIV_LSB)
-#define WLAN_PLL_CONTROL_DIV_SET(x) (((x) << WLAN_PLL_CONTROL_DIV_LSB) & WLAN_PLL_CONTROL_DIV_MASK)
-
-#define WLAN_PLL_SETTLE_ADDRESS 0x00000018
-#define WLAN_PLL_SETTLE_OFFSET 0x00000018
-#define WLAN_PLL_SETTLE_TIME_MSB 11
-#define WLAN_PLL_SETTLE_TIME_LSB 0
-#define WLAN_PLL_SETTLE_TIME_MASK 0x00000fff
-#define WLAN_PLL_SETTLE_TIME_GET(x) (((x) & WLAN_PLL_SETTLE_TIME_MASK) >> WLAN_PLL_SETTLE_TIME_LSB)
-#define WLAN_PLL_SETTLE_TIME_SET(x) (((x) << WLAN_PLL_SETTLE_TIME_LSB) & WLAN_PLL_SETTLE_TIME_MASK)
-
-#define WLAN_XTAL_SETTLE_ADDRESS 0x0000001c
-#define WLAN_XTAL_SETTLE_OFFSET 0x0000001c
-#define WLAN_XTAL_SETTLE_TIME_MSB 7
-#define WLAN_XTAL_SETTLE_TIME_LSB 0
-#define WLAN_XTAL_SETTLE_TIME_MASK 0x000000ff
-#define WLAN_XTAL_SETTLE_TIME_GET(x) (((x) & WLAN_XTAL_SETTLE_TIME_MASK) >> WLAN_XTAL_SETTLE_TIME_LSB)
-#define WLAN_XTAL_SETTLE_TIME_SET(x) (((x) << WLAN_XTAL_SETTLE_TIME_LSB) & WLAN_XTAL_SETTLE_TIME_MASK)
-
#define WLAN_CPU_CLOCK_ADDRESS 0x00000020
#define WLAN_CPU_CLOCK_OFFSET 0x00000020
#define WLAN_CPU_CLOCK_STANDARD_MSB 1
@@ -201,14 +105,6 @@
#define WLAN_CPU_CLOCK_STANDARD_GET(x) (((x) & WLAN_CPU_CLOCK_STANDARD_MASK) >> WLAN_CPU_CLOCK_STANDARD_LSB)
#define WLAN_CPU_CLOCK_STANDARD_SET(x) (((x) << WLAN_CPU_CLOCK_STANDARD_LSB) & WLAN_CPU_CLOCK_STANDARD_MASK)
-#define WLAN_CLOCK_OUT_ADDRESS 0x00000024
-#define WLAN_CLOCK_OUT_OFFSET 0x00000024
-#define WLAN_CLOCK_OUT_SELECT_MSB 3
-#define WLAN_CLOCK_OUT_SELECT_LSB 0
-#define WLAN_CLOCK_OUT_SELECT_MASK 0x0000000f
-#define WLAN_CLOCK_OUT_SELECT_GET(x) (((x) & WLAN_CLOCK_OUT_SELECT_MASK) >> WLAN_CLOCK_OUT_SELECT_LSB)
-#define WLAN_CLOCK_OUT_SELECT_SET(x) (((x) << WLAN_CLOCK_OUT_SELECT_LSB) & WLAN_CLOCK_OUT_SELECT_MASK)
-
#define WLAN_CLOCK_CONTROL_ADDRESS 0x00000028
#define WLAN_CLOCK_CONTROL_OFFSET 0x00000028
#define WLAN_CLOCK_CONTROL_LF_CLK32_MSB 2
@@ -222,555 +118,6 @@
#define WLAN_CLOCK_CONTROL_SI0_CLK_GET(x) (((x) & WLAN_CLOCK_CONTROL_SI0_CLK_MASK) >> WLAN_CLOCK_CONTROL_SI0_CLK_LSB)
#define WLAN_CLOCK_CONTROL_SI0_CLK_SET(x) (((x) << WLAN_CLOCK_CONTROL_SI0_CLK_LSB) & WLAN_CLOCK_CONTROL_SI0_CLK_MASK)
-#define WLAN_BIAS_OVERRIDE_ADDRESS 0x0000002c
-#define WLAN_BIAS_OVERRIDE_OFFSET 0x0000002c
-#define WLAN_BIAS_OVERRIDE_ON_MSB 0
-#define WLAN_BIAS_OVERRIDE_ON_LSB 0
-#define WLAN_BIAS_OVERRIDE_ON_MASK 0x00000001
-#define WLAN_BIAS_OVERRIDE_ON_GET(x) (((x) & WLAN_BIAS_OVERRIDE_ON_MASK) >> WLAN_BIAS_OVERRIDE_ON_LSB)
-#define WLAN_BIAS_OVERRIDE_ON_SET(x) (((x) << WLAN_BIAS_OVERRIDE_ON_LSB) & WLAN_BIAS_OVERRIDE_ON_MASK)
-
-#define WLAN_WDT_CONTROL_ADDRESS 0x00000030
-#define WLAN_WDT_CONTROL_OFFSET 0x00000030
-#define WLAN_WDT_CONTROL_ACTION_MSB 2
-#define WLAN_WDT_CONTROL_ACTION_LSB 0
-#define WLAN_WDT_CONTROL_ACTION_MASK 0x00000007
-#define WLAN_WDT_CONTROL_ACTION_GET(x) (((x) & WLAN_WDT_CONTROL_ACTION_MASK) >> WLAN_WDT_CONTROL_ACTION_LSB)
-#define WLAN_WDT_CONTROL_ACTION_SET(x) (((x) << WLAN_WDT_CONTROL_ACTION_LSB) & WLAN_WDT_CONTROL_ACTION_MASK)
-
-#define WLAN_WDT_STATUS_ADDRESS 0x00000034
-#define WLAN_WDT_STATUS_OFFSET 0x00000034
-#define WLAN_WDT_STATUS_INTERRUPT_MSB 0
-#define WLAN_WDT_STATUS_INTERRUPT_LSB 0
-#define WLAN_WDT_STATUS_INTERRUPT_MASK 0x00000001
-#define WLAN_WDT_STATUS_INTERRUPT_GET(x) (((x) & WLAN_WDT_STATUS_INTERRUPT_MASK) >> WLAN_WDT_STATUS_INTERRUPT_LSB)
-#define WLAN_WDT_STATUS_INTERRUPT_SET(x) (((x) << WLAN_WDT_STATUS_INTERRUPT_LSB) & WLAN_WDT_STATUS_INTERRUPT_MASK)
-
-#define WLAN_WDT_ADDRESS 0x00000038
-#define WLAN_WDT_OFFSET 0x00000038
-#define WLAN_WDT_TARGET_MSB 21
-#define WLAN_WDT_TARGET_LSB 0
-#define WLAN_WDT_TARGET_MASK 0x003fffff
-#define WLAN_WDT_TARGET_GET(x) (((x) & WLAN_WDT_TARGET_MASK) >> WLAN_WDT_TARGET_LSB)
-#define WLAN_WDT_TARGET_SET(x) (((x) << WLAN_WDT_TARGET_LSB) & WLAN_WDT_TARGET_MASK)
-
-#define WLAN_WDT_COUNT_ADDRESS 0x0000003c
-#define WLAN_WDT_COUNT_OFFSET 0x0000003c
-#define WLAN_WDT_COUNT_VALUE_MSB 21
-#define WLAN_WDT_COUNT_VALUE_LSB 0
-#define WLAN_WDT_COUNT_VALUE_MASK 0x003fffff
-#define WLAN_WDT_COUNT_VALUE_GET(x) (((x) & WLAN_WDT_COUNT_VALUE_MASK) >> WLAN_WDT_COUNT_VALUE_LSB)
-#define WLAN_WDT_COUNT_VALUE_SET(x) (((x) << WLAN_WDT_COUNT_VALUE_LSB) & WLAN_WDT_COUNT_VALUE_MASK)
-
-#define WLAN_WDT_RESET_ADDRESS 0x00000040
-#define WLAN_WDT_RESET_OFFSET 0x00000040
-#define WLAN_WDT_RESET_VALUE_MSB 0
-#define WLAN_WDT_RESET_VALUE_LSB 0
-#define WLAN_WDT_RESET_VALUE_MASK 0x00000001
-#define WLAN_WDT_RESET_VALUE_GET(x) (((x) & WLAN_WDT_RESET_VALUE_MASK) >> WLAN_WDT_RESET_VALUE_LSB)
-#define WLAN_WDT_RESET_VALUE_SET(x) (((x) << WLAN_WDT_RESET_VALUE_LSB) & WLAN_WDT_RESET_VALUE_MASK)
-
-#define WLAN_INT_STATUS_ADDRESS 0x00000044
-#define WLAN_INT_STATUS_OFFSET 0x00000044
-#define WLAN_INT_STATUS_HCI_UART_MSB 21
-#define WLAN_INT_STATUS_HCI_UART_LSB 21
-#define WLAN_INT_STATUS_HCI_UART_MASK 0x00200000
-#define WLAN_INT_STATUS_HCI_UART_GET(x) (((x) & WLAN_INT_STATUS_HCI_UART_MASK) >> WLAN_INT_STATUS_HCI_UART_LSB)
-#define WLAN_INT_STATUS_HCI_UART_SET(x) (((x) << WLAN_INT_STATUS_HCI_UART_LSB) & WLAN_INT_STATUS_HCI_UART_MASK)
-#define WLAN_INT_STATUS_THERM_MSB 20
-#define WLAN_INT_STATUS_THERM_LSB 20
-#define WLAN_INT_STATUS_THERM_MASK 0x00100000
-#define WLAN_INT_STATUS_THERM_GET(x) (((x) & WLAN_INT_STATUS_THERM_MASK) >> WLAN_INT_STATUS_THERM_LSB)
-#define WLAN_INT_STATUS_THERM_SET(x) (((x) << WLAN_INT_STATUS_THERM_LSB) & WLAN_INT_STATUS_THERM_MASK)
-#define WLAN_INT_STATUS_EFUSE_OVERWRITE_MSB 19
-#define WLAN_INT_STATUS_EFUSE_OVERWRITE_LSB 19
-#define WLAN_INT_STATUS_EFUSE_OVERWRITE_MASK 0x00080000
-#define WLAN_INT_STATUS_EFUSE_OVERWRITE_GET(x) (((x) & WLAN_INT_STATUS_EFUSE_OVERWRITE_MASK) >> WLAN_INT_STATUS_EFUSE_OVERWRITE_LSB)
-#define WLAN_INT_STATUS_EFUSE_OVERWRITE_SET(x) (((x) << WLAN_INT_STATUS_EFUSE_OVERWRITE_LSB) & WLAN_INT_STATUS_EFUSE_OVERWRITE_MASK)
-#define WLAN_INT_STATUS_UART_MBOX_MSB 18
-#define WLAN_INT_STATUS_UART_MBOX_LSB 18
-#define WLAN_INT_STATUS_UART_MBOX_MASK 0x00040000
-#define WLAN_INT_STATUS_UART_MBOX_GET(x) (((x) & WLAN_INT_STATUS_UART_MBOX_MASK) >> WLAN_INT_STATUS_UART_MBOX_LSB)
-#define WLAN_INT_STATUS_UART_MBOX_SET(x) (((x) << WLAN_INT_STATUS_UART_MBOX_LSB) & WLAN_INT_STATUS_UART_MBOX_MASK)
-#define WLAN_INT_STATUS_GENERIC_MBOX_MSB 17
-#define WLAN_INT_STATUS_GENERIC_MBOX_LSB 17
-#define WLAN_INT_STATUS_GENERIC_MBOX_MASK 0x00020000
-#define WLAN_INT_STATUS_GENERIC_MBOX_GET(x) (((x) & WLAN_INT_STATUS_GENERIC_MBOX_MASK) >> WLAN_INT_STATUS_GENERIC_MBOX_LSB)
-#define WLAN_INT_STATUS_GENERIC_MBOX_SET(x) (((x) << WLAN_INT_STATUS_GENERIC_MBOX_LSB) & WLAN_INT_STATUS_GENERIC_MBOX_MASK)
-#define WLAN_INT_STATUS_RDMA_MSB 16
-#define WLAN_INT_STATUS_RDMA_LSB 16
-#define WLAN_INT_STATUS_RDMA_MASK 0x00010000
-#define WLAN_INT_STATUS_RDMA_GET(x) (((x) & WLAN_INT_STATUS_RDMA_MASK) >> WLAN_INT_STATUS_RDMA_LSB)
-#define WLAN_INT_STATUS_RDMA_SET(x) (((x) << WLAN_INT_STATUS_RDMA_LSB) & WLAN_INT_STATUS_RDMA_MASK)
-#define WLAN_INT_STATUS_BTCOEX_MSB 15
-#define WLAN_INT_STATUS_BTCOEX_LSB 15
-#define WLAN_INT_STATUS_BTCOEX_MASK 0x00008000
-#define WLAN_INT_STATUS_BTCOEX_GET(x) (((x) & WLAN_INT_STATUS_BTCOEX_MASK) >> WLAN_INT_STATUS_BTCOEX_LSB)
-#define WLAN_INT_STATUS_BTCOEX_SET(x) (((x) << WLAN_INT_STATUS_BTCOEX_LSB) & WLAN_INT_STATUS_BTCOEX_MASK)
-#define WLAN_INT_STATUS_RTC_POWER_MSB 14
-#define WLAN_INT_STATUS_RTC_POWER_LSB 14
-#define WLAN_INT_STATUS_RTC_POWER_MASK 0x00004000
-#define WLAN_INT_STATUS_RTC_POWER_GET(x) (((x) & WLAN_INT_STATUS_RTC_POWER_MASK) >> WLAN_INT_STATUS_RTC_POWER_LSB)
-#define WLAN_INT_STATUS_RTC_POWER_SET(x) (((x) << WLAN_INT_STATUS_RTC_POWER_LSB) & WLAN_INT_STATUS_RTC_POWER_MASK)
-#define WLAN_INT_STATUS_MAC_MSB 13
-#define WLAN_INT_STATUS_MAC_LSB 13
-#define WLAN_INT_STATUS_MAC_MASK 0x00002000
-#define WLAN_INT_STATUS_MAC_GET(x) (((x) & WLAN_INT_STATUS_MAC_MASK) >> WLAN_INT_STATUS_MAC_LSB)
-#define WLAN_INT_STATUS_MAC_SET(x) (((x) << WLAN_INT_STATUS_MAC_LSB) & WLAN_INT_STATUS_MAC_MASK)
-#define WLAN_INT_STATUS_MAILBOX_MSB 12
-#define WLAN_INT_STATUS_MAILBOX_LSB 12
-#define WLAN_INT_STATUS_MAILBOX_MASK 0x00001000
-#define WLAN_INT_STATUS_MAILBOX_GET(x) (((x) & WLAN_INT_STATUS_MAILBOX_MASK) >> WLAN_INT_STATUS_MAILBOX_LSB)
-#define WLAN_INT_STATUS_MAILBOX_SET(x) (((x) << WLAN_INT_STATUS_MAILBOX_LSB) & WLAN_INT_STATUS_MAILBOX_MASK)
-#define WLAN_INT_STATUS_RTC_ALARM_MSB 11
-#define WLAN_INT_STATUS_RTC_ALARM_LSB 11
-#define WLAN_INT_STATUS_RTC_ALARM_MASK 0x00000800
-#define WLAN_INT_STATUS_RTC_ALARM_GET(x) (((x) & WLAN_INT_STATUS_RTC_ALARM_MASK) >> WLAN_INT_STATUS_RTC_ALARM_LSB)
-#define WLAN_INT_STATUS_RTC_ALARM_SET(x) (((x) << WLAN_INT_STATUS_RTC_ALARM_LSB) & WLAN_INT_STATUS_RTC_ALARM_MASK)
-#define WLAN_INT_STATUS_HF_TIMER_MSB 10
-#define WLAN_INT_STATUS_HF_TIMER_LSB 10
-#define WLAN_INT_STATUS_HF_TIMER_MASK 0x00000400
-#define WLAN_INT_STATUS_HF_TIMER_GET(x) (((x) & WLAN_INT_STATUS_HF_TIMER_MASK) >> WLAN_INT_STATUS_HF_TIMER_LSB)
-#define WLAN_INT_STATUS_HF_TIMER_SET(x) (((x) << WLAN_INT_STATUS_HF_TIMER_LSB) & WLAN_INT_STATUS_HF_TIMER_MASK)
-#define WLAN_INT_STATUS_LF_TIMER3_MSB 9
-#define WLAN_INT_STATUS_LF_TIMER3_LSB 9
-#define WLAN_INT_STATUS_LF_TIMER3_MASK 0x00000200
-#define WLAN_INT_STATUS_LF_TIMER3_GET(x) (((x) & WLAN_INT_STATUS_LF_TIMER3_MASK) >> WLAN_INT_STATUS_LF_TIMER3_LSB)
-#define WLAN_INT_STATUS_LF_TIMER3_SET(x) (((x) << WLAN_INT_STATUS_LF_TIMER3_LSB) & WLAN_INT_STATUS_LF_TIMER3_MASK)
-#define WLAN_INT_STATUS_LF_TIMER2_MSB 8
-#define WLAN_INT_STATUS_LF_TIMER2_LSB 8
-#define WLAN_INT_STATUS_LF_TIMER2_MASK 0x00000100
-#define WLAN_INT_STATUS_LF_TIMER2_GET(x) (((x) & WLAN_INT_STATUS_LF_TIMER2_MASK) >> WLAN_INT_STATUS_LF_TIMER2_LSB)
-#define WLAN_INT_STATUS_LF_TIMER2_SET(x) (((x) << WLAN_INT_STATUS_LF_TIMER2_LSB) & WLAN_INT_STATUS_LF_TIMER2_MASK)
-#define WLAN_INT_STATUS_LF_TIMER1_MSB 7
-#define WLAN_INT_STATUS_LF_TIMER1_LSB 7
-#define WLAN_INT_STATUS_LF_TIMER1_MASK 0x00000080
-#define WLAN_INT_STATUS_LF_TIMER1_GET(x) (((x) & WLAN_INT_STATUS_LF_TIMER1_MASK) >> WLAN_INT_STATUS_LF_TIMER1_LSB)
-#define WLAN_INT_STATUS_LF_TIMER1_SET(x) (((x) << WLAN_INT_STATUS_LF_TIMER1_LSB) & WLAN_INT_STATUS_LF_TIMER1_MASK)
-#define WLAN_INT_STATUS_LF_TIMER0_MSB 6
-#define WLAN_INT_STATUS_LF_TIMER0_LSB 6
-#define WLAN_INT_STATUS_LF_TIMER0_MASK 0x00000040
-#define WLAN_INT_STATUS_LF_TIMER0_GET(x) (((x) & WLAN_INT_STATUS_LF_TIMER0_MASK) >> WLAN_INT_STATUS_LF_TIMER0_LSB)
-#define WLAN_INT_STATUS_LF_TIMER0_SET(x) (((x) << WLAN_INT_STATUS_LF_TIMER0_LSB) & WLAN_INT_STATUS_LF_TIMER0_MASK)
-#define WLAN_INT_STATUS_KEYPAD_MSB 5
-#define WLAN_INT_STATUS_KEYPAD_LSB 5
-#define WLAN_INT_STATUS_KEYPAD_MASK 0x00000020
-#define WLAN_INT_STATUS_KEYPAD_GET(x) (((x) & WLAN_INT_STATUS_KEYPAD_MASK) >> WLAN_INT_STATUS_KEYPAD_LSB)
-#define WLAN_INT_STATUS_KEYPAD_SET(x) (((x) << WLAN_INT_STATUS_KEYPAD_LSB) & WLAN_INT_STATUS_KEYPAD_MASK)
-#define WLAN_INT_STATUS_SI_MSB 4
-#define WLAN_INT_STATUS_SI_LSB 4
-#define WLAN_INT_STATUS_SI_MASK 0x00000010
-#define WLAN_INT_STATUS_SI_GET(x) (((x) & WLAN_INT_STATUS_SI_MASK) >> WLAN_INT_STATUS_SI_LSB)
-#define WLAN_INT_STATUS_SI_SET(x) (((x) << WLAN_INT_STATUS_SI_LSB) & WLAN_INT_STATUS_SI_MASK)
-#define WLAN_INT_STATUS_GPIO_MSB 3
-#define WLAN_INT_STATUS_GPIO_LSB 3
-#define WLAN_INT_STATUS_GPIO_MASK 0x00000008
-#define WLAN_INT_STATUS_GPIO_GET(x) (((x) & WLAN_INT_STATUS_GPIO_MASK) >> WLAN_INT_STATUS_GPIO_LSB)
-#define WLAN_INT_STATUS_GPIO_SET(x) (((x) << WLAN_INT_STATUS_GPIO_LSB) & WLAN_INT_STATUS_GPIO_MASK)
-#define WLAN_INT_STATUS_UART_MSB 2
-#define WLAN_INT_STATUS_UART_LSB 2
-#define WLAN_INT_STATUS_UART_MASK 0x00000004
-#define WLAN_INT_STATUS_UART_GET(x) (((x) & WLAN_INT_STATUS_UART_MASK) >> WLAN_INT_STATUS_UART_LSB)
-#define WLAN_INT_STATUS_UART_SET(x) (((x) << WLAN_INT_STATUS_UART_LSB) & WLAN_INT_STATUS_UART_MASK)
-#define WLAN_INT_STATUS_ERROR_MSB 1
-#define WLAN_INT_STATUS_ERROR_LSB 1
-#define WLAN_INT_STATUS_ERROR_MASK 0x00000002
-#define WLAN_INT_STATUS_ERROR_GET(x) (((x) & WLAN_INT_STATUS_ERROR_MASK) >> WLAN_INT_STATUS_ERROR_LSB)
-#define WLAN_INT_STATUS_ERROR_SET(x) (((x) << WLAN_INT_STATUS_ERROR_LSB) & WLAN_INT_STATUS_ERROR_MASK)
-#define WLAN_INT_STATUS_WDT_INT_MSB 0
-#define WLAN_INT_STATUS_WDT_INT_LSB 0
-#define WLAN_INT_STATUS_WDT_INT_MASK 0x00000001
-#define WLAN_INT_STATUS_WDT_INT_GET(x) (((x) & WLAN_INT_STATUS_WDT_INT_MASK) >> WLAN_INT_STATUS_WDT_INT_LSB)
-#define WLAN_INT_STATUS_WDT_INT_SET(x) (((x) << WLAN_INT_STATUS_WDT_INT_LSB) & WLAN_INT_STATUS_WDT_INT_MASK)
-
-#define WLAN_LF_TIMER0_ADDRESS 0x00000048
-#define WLAN_LF_TIMER0_OFFSET 0x00000048
-#define WLAN_LF_TIMER0_TARGET_MSB 31
-#define WLAN_LF_TIMER0_TARGET_LSB 0
-#define WLAN_LF_TIMER0_TARGET_MASK 0xffffffff
-#define WLAN_LF_TIMER0_TARGET_GET(x) (((x) & WLAN_LF_TIMER0_TARGET_MASK) >> WLAN_LF_TIMER0_TARGET_LSB)
-#define WLAN_LF_TIMER0_TARGET_SET(x) (((x) << WLAN_LF_TIMER0_TARGET_LSB) & WLAN_LF_TIMER0_TARGET_MASK)
-
-#define WLAN_LF_TIMER_COUNT0_ADDRESS 0x0000004c
-#define WLAN_LF_TIMER_COUNT0_OFFSET 0x0000004c
-#define WLAN_LF_TIMER_COUNT0_VALUE_MSB 31
-#define WLAN_LF_TIMER_COUNT0_VALUE_LSB 0
-#define WLAN_LF_TIMER_COUNT0_VALUE_MASK 0xffffffff
-#define WLAN_LF_TIMER_COUNT0_VALUE_GET(x) (((x) & WLAN_LF_TIMER_COUNT0_VALUE_MASK) >> WLAN_LF_TIMER_COUNT0_VALUE_LSB)
-#define WLAN_LF_TIMER_COUNT0_VALUE_SET(x) (((x) << WLAN_LF_TIMER_COUNT0_VALUE_LSB) & WLAN_LF_TIMER_COUNT0_VALUE_MASK)
-
-#define WLAN_LF_TIMER_CONTROL0_ADDRESS 0x00000050
-#define WLAN_LF_TIMER_CONTROL0_OFFSET 0x00000050
-#define WLAN_LF_TIMER_CONTROL0_ENABLE_MSB 2
-#define WLAN_LF_TIMER_CONTROL0_ENABLE_LSB 2
-#define WLAN_LF_TIMER_CONTROL0_ENABLE_MASK 0x00000004
-#define WLAN_LF_TIMER_CONTROL0_ENABLE_GET(x) (((x) & WLAN_LF_TIMER_CONTROL0_ENABLE_MASK) >> WLAN_LF_TIMER_CONTROL0_ENABLE_LSB)
-#define WLAN_LF_TIMER_CONTROL0_ENABLE_SET(x) (((x) << WLAN_LF_TIMER_CONTROL0_ENABLE_LSB) & WLAN_LF_TIMER_CONTROL0_ENABLE_MASK)
-#define WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_MSB 1
-#define WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_LSB 1
-#define WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_MASK 0x00000002
-#define WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_GET(x) (((x) & WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_MASK) >> WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_LSB)
-#define WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_SET(x) (((x) << WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_LSB) & WLAN_LF_TIMER_CONTROL0_AUTO_RESTART_MASK)
-#define WLAN_LF_TIMER_CONTROL0_RESET_MSB 0
-#define WLAN_LF_TIMER_CONTROL0_RESET_LSB 0
-#define WLAN_LF_TIMER_CONTROL0_RESET_MASK 0x00000001
-#define WLAN_LF_TIMER_CONTROL0_RESET_GET(x) (((x) & WLAN_LF_TIMER_CONTROL0_RESET_MASK) >> WLAN_LF_TIMER_CONTROL0_RESET_LSB)
-#define WLAN_LF_TIMER_CONTROL0_RESET_SET(x) (((x) << WLAN_LF_TIMER_CONTROL0_RESET_LSB) & WLAN_LF_TIMER_CONTROL0_RESET_MASK)
-
-#define WLAN_LF_TIMER_STATUS0_ADDRESS 0x00000054
-#define WLAN_LF_TIMER_STATUS0_OFFSET 0x00000054
-#define WLAN_LF_TIMER_STATUS0_INTERRUPT_MSB 0
-#define WLAN_LF_TIMER_STATUS0_INTERRUPT_LSB 0
-#define WLAN_LF_TIMER_STATUS0_INTERRUPT_MASK 0x00000001
-#define WLAN_LF_TIMER_STATUS0_INTERRUPT_GET(x) (((x) & WLAN_LF_TIMER_STATUS0_INTERRUPT_MASK) >> WLAN_LF_TIMER_STATUS0_INTERRUPT_LSB)
-#define WLAN_LF_TIMER_STATUS0_INTERRUPT_SET(x) (((x) << WLAN_LF_TIMER_STATUS0_INTERRUPT_LSB) & WLAN_LF_TIMER_STATUS0_INTERRUPT_MASK)
-
-#define WLAN_LF_TIMER1_ADDRESS 0x00000058
-#define WLAN_LF_TIMER1_OFFSET 0x00000058
-#define WLAN_LF_TIMER1_TARGET_MSB 31
-#define WLAN_LF_TIMER1_TARGET_LSB 0
-#define WLAN_LF_TIMER1_TARGET_MASK 0xffffffff
-#define WLAN_LF_TIMER1_TARGET_GET(x) (((x) & WLAN_LF_TIMER1_TARGET_MASK) >> WLAN_LF_TIMER1_TARGET_LSB)
-#define WLAN_LF_TIMER1_TARGET_SET(x) (((x) << WLAN_LF_TIMER1_TARGET_LSB) & WLAN_LF_TIMER1_TARGET_MASK)
-
-#define WLAN_LF_TIMER_COUNT1_ADDRESS 0x0000005c
-#define WLAN_LF_TIMER_COUNT1_OFFSET 0x0000005c
-#define WLAN_LF_TIMER_COUNT1_VALUE_MSB 31
-#define WLAN_LF_TIMER_COUNT1_VALUE_LSB 0
-#define WLAN_LF_TIMER_COUNT1_VALUE_MASK 0xffffffff
-#define WLAN_LF_TIMER_COUNT1_VALUE_GET(x) (((x) & WLAN_LF_TIMER_COUNT1_VALUE_MASK) >> WLAN_LF_TIMER_COUNT1_VALUE_LSB)
-#define WLAN_LF_TIMER_COUNT1_VALUE_SET(x) (((x) << WLAN_LF_TIMER_COUNT1_VALUE_LSB) & WLAN_LF_TIMER_COUNT1_VALUE_MASK)
-
-#define WLAN_LF_TIMER_CONTROL1_ADDRESS 0x00000060
-#define WLAN_LF_TIMER_CONTROL1_OFFSET 0x00000060
-#define WLAN_LF_TIMER_CONTROL1_ENABLE_MSB 2
-#define WLAN_LF_TIMER_CONTROL1_ENABLE_LSB 2
-#define WLAN_LF_TIMER_CONTROL1_ENABLE_MASK 0x00000004
-#define WLAN_LF_TIMER_CONTROL1_ENABLE_GET(x) (((x) & WLAN_LF_TIMER_CONTROL1_ENABLE_MASK) >> WLAN_LF_TIMER_CONTROL1_ENABLE_LSB)
-#define WLAN_LF_TIMER_CONTROL1_ENABLE_SET(x) (((x) << WLAN_LF_TIMER_CONTROL1_ENABLE_LSB) & WLAN_LF_TIMER_CONTROL1_ENABLE_MASK)
-#define WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_MSB 1
-#define WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_LSB 1
-#define WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_MASK 0x00000002
-#define WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_GET(x) (((x) & WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_MASK) >> WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_LSB)
-#define WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_SET(x) (((x) << WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_LSB) & WLAN_LF_TIMER_CONTROL1_AUTO_RESTART_MASK)
-#define WLAN_LF_TIMER_CONTROL1_RESET_MSB 0
-#define WLAN_LF_TIMER_CONTROL1_RESET_LSB 0
-#define WLAN_LF_TIMER_CONTROL1_RESET_MASK 0x00000001
-#define WLAN_LF_TIMER_CONTROL1_RESET_GET(x) (((x) & WLAN_LF_TIMER_CONTROL1_RESET_MASK) >> WLAN_LF_TIMER_CONTROL1_RESET_LSB)
-#define WLAN_LF_TIMER_CONTROL1_RESET_SET(x) (((x) << WLAN_LF_TIMER_CONTROL1_RESET_LSB) & WLAN_LF_TIMER_CONTROL1_RESET_MASK)
-
-#define WLAN_LF_TIMER_STATUS1_ADDRESS 0x00000064
-#define WLAN_LF_TIMER_STATUS1_OFFSET 0x00000064
-#define WLAN_LF_TIMER_STATUS1_INTERRUPT_MSB 0
-#define WLAN_LF_TIMER_STATUS1_INTERRUPT_LSB 0
-#define WLAN_LF_TIMER_STATUS1_INTERRUPT_MASK 0x00000001
-#define WLAN_LF_TIMER_STATUS1_INTERRUPT_GET(x) (((x) & WLAN_LF_TIMER_STATUS1_INTERRUPT_MASK) >> WLAN_LF_TIMER_STATUS1_INTERRUPT_LSB)
-#define WLAN_LF_TIMER_STATUS1_INTERRUPT_SET(x) (((x) << WLAN_LF_TIMER_STATUS1_INTERRUPT_LSB) & WLAN_LF_TIMER_STATUS1_INTERRUPT_MASK)
-
-#define WLAN_LF_TIMER2_ADDRESS 0x00000068
-#define WLAN_LF_TIMER2_OFFSET 0x00000068
-#define WLAN_LF_TIMER2_TARGET_MSB 31
-#define WLAN_LF_TIMER2_TARGET_LSB 0
-#define WLAN_LF_TIMER2_TARGET_MASK 0xffffffff
-#define WLAN_LF_TIMER2_TARGET_GET(x) (((x) & WLAN_LF_TIMER2_TARGET_MASK) >> WLAN_LF_TIMER2_TARGET_LSB)
-#define WLAN_LF_TIMER2_TARGET_SET(x) (((x) << WLAN_LF_TIMER2_TARGET_LSB) & WLAN_LF_TIMER2_TARGET_MASK)
-
-#define WLAN_LF_TIMER_COUNT2_ADDRESS 0x0000006c
-#define WLAN_LF_TIMER_COUNT2_OFFSET 0x0000006c
-#define WLAN_LF_TIMER_COUNT2_VALUE_MSB 31
-#define WLAN_LF_TIMER_COUNT2_VALUE_LSB 0
-#define WLAN_LF_TIMER_COUNT2_VALUE_MASK 0xffffffff
-#define WLAN_LF_TIMER_COUNT2_VALUE_GET(x) (((x) & WLAN_LF_TIMER_COUNT2_VALUE_MASK) >> WLAN_LF_TIMER_COUNT2_VALUE_LSB)
-#define WLAN_LF_TIMER_COUNT2_VALUE_SET(x) (((x) << WLAN_LF_TIMER_COUNT2_VALUE_LSB) & WLAN_LF_TIMER_COUNT2_VALUE_MASK)
-
-#define WLAN_LF_TIMER_CONTROL2_ADDRESS 0x00000070
-#define WLAN_LF_TIMER_CONTROL2_OFFSET 0x00000070
-#define WLAN_LF_TIMER_CONTROL2_ENABLE_MSB 2
-#define WLAN_LF_TIMER_CONTROL2_ENABLE_LSB 2
-#define WLAN_LF_TIMER_CONTROL2_ENABLE_MASK 0x00000004
-#define WLAN_LF_TIMER_CONTROL2_ENABLE_GET(x) (((x) & WLAN_LF_TIMER_CONTROL2_ENABLE_MASK) >> WLAN_LF_TIMER_CONTROL2_ENABLE_LSB)
-#define WLAN_LF_TIMER_CONTROL2_ENABLE_SET(x) (((x) << WLAN_LF_TIMER_CONTROL2_ENABLE_LSB) & WLAN_LF_TIMER_CONTROL2_ENABLE_MASK)
-#define WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_MSB 1
-#define WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_LSB 1
-#define WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_MASK 0x00000002
-#define WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_GET(x) (((x) & WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_MASK) >> WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_LSB)
-#define WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_SET(x) (((x) << WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_LSB) & WLAN_LF_TIMER_CONTROL2_AUTO_RESTART_MASK)
-#define WLAN_LF_TIMER_CONTROL2_RESET_MSB 0
-#define WLAN_LF_TIMER_CONTROL2_RESET_LSB 0
-#define WLAN_LF_TIMER_CONTROL2_RESET_MASK 0x00000001
-#define WLAN_LF_TIMER_CONTROL2_RESET_GET(x) (((x) & WLAN_LF_TIMER_CONTROL2_RESET_MASK) >> WLAN_LF_TIMER_CONTROL2_RESET_LSB)
-#define WLAN_LF_TIMER_CONTROL2_RESET_SET(x) (((x) << WLAN_LF_TIMER_CONTROL2_RESET_LSB) & WLAN_LF_TIMER_CONTROL2_RESET_MASK)
-
-#define WLAN_LF_TIMER_STATUS2_ADDRESS 0x00000074
-#define WLAN_LF_TIMER_STATUS2_OFFSET 0x00000074
-#define WLAN_LF_TIMER_STATUS2_INTERRUPT_MSB 0
-#define WLAN_LF_TIMER_STATUS2_INTERRUPT_LSB 0
-#define WLAN_LF_TIMER_STATUS2_INTERRUPT_MASK 0x00000001
-#define WLAN_LF_TIMER_STATUS2_INTERRUPT_GET(x) (((x) & WLAN_LF_TIMER_STATUS2_INTERRUPT_MASK) >> WLAN_LF_TIMER_STATUS2_INTERRUPT_LSB)
-#define WLAN_LF_TIMER_STATUS2_INTERRUPT_SET(x) (((x) << WLAN_LF_TIMER_STATUS2_INTERRUPT_LSB) & WLAN_LF_TIMER_STATUS2_INTERRUPT_MASK)
-
-#define WLAN_LF_TIMER3_ADDRESS 0x00000078
-#define WLAN_LF_TIMER3_OFFSET 0x00000078
-#define WLAN_LF_TIMER3_TARGET_MSB 31
-#define WLAN_LF_TIMER3_TARGET_LSB 0
-#define WLAN_LF_TIMER3_TARGET_MASK 0xffffffff
-#define WLAN_LF_TIMER3_TARGET_GET(x) (((x) & WLAN_LF_TIMER3_TARGET_MASK) >> WLAN_LF_TIMER3_TARGET_LSB)
-#define WLAN_LF_TIMER3_TARGET_SET(x) (((x) << WLAN_LF_TIMER3_TARGET_LSB) & WLAN_LF_TIMER3_TARGET_MASK)
-
-#define WLAN_LF_TIMER_COUNT3_ADDRESS 0x0000007c
-#define WLAN_LF_TIMER_COUNT3_OFFSET 0x0000007c
-#define WLAN_LF_TIMER_COUNT3_VALUE_MSB 31
-#define WLAN_LF_TIMER_COUNT3_VALUE_LSB 0
-#define WLAN_LF_TIMER_COUNT3_VALUE_MASK 0xffffffff
-#define WLAN_LF_TIMER_COUNT3_VALUE_GET(x) (((x) & WLAN_LF_TIMER_COUNT3_VALUE_MASK) >> WLAN_LF_TIMER_COUNT3_VALUE_LSB)
-#define WLAN_LF_TIMER_COUNT3_VALUE_SET(x) (((x) << WLAN_LF_TIMER_COUNT3_VALUE_LSB) & WLAN_LF_TIMER_COUNT3_VALUE_MASK)
-
-#define WLAN_LF_TIMER_CONTROL3_ADDRESS 0x00000080
-#define WLAN_LF_TIMER_CONTROL3_OFFSET 0x00000080
-#define WLAN_LF_TIMER_CONTROL3_ENABLE_MSB 2
-#define WLAN_LF_TIMER_CONTROL3_ENABLE_LSB 2
-#define WLAN_LF_TIMER_CONTROL3_ENABLE_MASK 0x00000004
-#define WLAN_LF_TIMER_CONTROL3_ENABLE_GET(x) (((x) & WLAN_LF_TIMER_CONTROL3_ENABLE_MASK) >> WLAN_LF_TIMER_CONTROL3_ENABLE_LSB)
-#define WLAN_LF_TIMER_CONTROL3_ENABLE_SET(x) (((x) << WLAN_LF_TIMER_CONTROL3_ENABLE_LSB) & WLAN_LF_TIMER_CONTROL3_ENABLE_MASK)
-#define WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_MSB 1
-#define WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_LSB 1
-#define WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_MASK 0x00000002
-#define WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_GET(x) (((x) & WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_MASK) >> WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_LSB)
-#define WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_SET(x) (((x) << WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_LSB) & WLAN_LF_TIMER_CONTROL3_AUTO_RESTART_MASK)
-#define WLAN_LF_TIMER_CONTROL3_RESET_MSB 0
-#define WLAN_LF_TIMER_CONTROL3_RESET_LSB 0
-#define WLAN_LF_TIMER_CONTROL3_RESET_MASK 0x00000001
-#define WLAN_LF_TIMER_CONTROL3_RESET_GET(x) (((x) & WLAN_LF_TIMER_CONTROL3_RESET_MASK) >> WLAN_LF_TIMER_CONTROL3_RESET_LSB)
-#define WLAN_LF_TIMER_CONTROL3_RESET_SET(x) (((x) << WLAN_LF_TIMER_CONTROL3_RESET_LSB) & WLAN_LF_TIMER_CONTROL3_RESET_MASK)
-
-#define WLAN_LF_TIMER_STATUS3_ADDRESS 0x00000084
-#define WLAN_LF_TIMER_STATUS3_OFFSET 0x00000084
-#define WLAN_LF_TIMER_STATUS3_INTERRUPT_MSB 0
-#define WLAN_LF_TIMER_STATUS3_INTERRUPT_LSB 0
-#define WLAN_LF_TIMER_STATUS3_INTERRUPT_MASK 0x00000001
-#define WLAN_LF_TIMER_STATUS3_INTERRUPT_GET(x) (((x) & WLAN_LF_TIMER_STATUS3_INTERRUPT_MASK) >> WLAN_LF_TIMER_STATUS3_INTERRUPT_LSB)
-#define WLAN_LF_TIMER_STATUS3_INTERRUPT_SET(x) (((x) << WLAN_LF_TIMER_STATUS3_INTERRUPT_LSB) & WLAN_LF_TIMER_STATUS3_INTERRUPT_MASK)
-
-#define WLAN_HF_TIMER_ADDRESS 0x00000088
-#define WLAN_HF_TIMER_OFFSET 0x00000088
-#define WLAN_HF_TIMER_TARGET_MSB 31
-#define WLAN_HF_TIMER_TARGET_LSB 12
-#define WLAN_HF_TIMER_TARGET_MASK 0xfffff000
-#define WLAN_HF_TIMER_TARGET_GET(x) (((x) & WLAN_HF_TIMER_TARGET_MASK) >> WLAN_HF_TIMER_TARGET_LSB)
-#define WLAN_HF_TIMER_TARGET_SET(x) (((x) << WLAN_HF_TIMER_TARGET_LSB) & WLAN_HF_TIMER_TARGET_MASK)
-
-#define WLAN_HF_TIMER_COUNT_ADDRESS 0x0000008c
-#define WLAN_HF_TIMER_COUNT_OFFSET 0x0000008c
-#define WLAN_HF_TIMER_COUNT_VALUE_MSB 31
-#define WLAN_HF_TIMER_COUNT_VALUE_LSB 12
-#define WLAN_HF_TIMER_COUNT_VALUE_MASK 0xfffff000
-#define WLAN_HF_TIMER_COUNT_VALUE_GET(x) (((x) & WLAN_HF_TIMER_COUNT_VALUE_MASK) >> WLAN_HF_TIMER_COUNT_VALUE_LSB)
-#define WLAN_HF_TIMER_COUNT_VALUE_SET(x) (((x) << WLAN_HF_TIMER_COUNT_VALUE_LSB) & WLAN_HF_TIMER_COUNT_VALUE_MASK)
-
-#define WLAN_HF_LF_COUNT_ADDRESS 0x00000090
-#define WLAN_HF_LF_COUNT_OFFSET 0x00000090
-#define WLAN_HF_LF_COUNT_VALUE_MSB 31
-#define WLAN_HF_LF_COUNT_VALUE_LSB 0
-#define WLAN_HF_LF_COUNT_VALUE_MASK 0xffffffff
-#define WLAN_HF_LF_COUNT_VALUE_GET(x) (((x) & WLAN_HF_LF_COUNT_VALUE_MASK) >> WLAN_HF_LF_COUNT_VALUE_LSB)
-#define WLAN_HF_LF_COUNT_VALUE_SET(x) (((x) << WLAN_HF_LF_COUNT_VALUE_LSB) & WLAN_HF_LF_COUNT_VALUE_MASK)
-
-#define WLAN_HF_TIMER_CONTROL_ADDRESS 0x00000094
-#define WLAN_HF_TIMER_CONTROL_OFFSET 0x00000094
-#define WLAN_HF_TIMER_CONTROL_ENABLE_MSB 3
-#define WLAN_HF_TIMER_CONTROL_ENABLE_LSB 3
-#define WLAN_HF_TIMER_CONTROL_ENABLE_MASK 0x00000008
-#define WLAN_HF_TIMER_CONTROL_ENABLE_GET(x) (((x) & WLAN_HF_TIMER_CONTROL_ENABLE_MASK) >> WLAN_HF_TIMER_CONTROL_ENABLE_LSB)
-#define WLAN_HF_TIMER_CONTROL_ENABLE_SET(x) (((x) << WLAN_HF_TIMER_CONTROL_ENABLE_LSB) & WLAN_HF_TIMER_CONTROL_ENABLE_MASK)
-#define WLAN_HF_TIMER_CONTROL_ON_MSB 2
-#define WLAN_HF_TIMER_CONTROL_ON_LSB 2
-#define WLAN_HF_TIMER_CONTROL_ON_MASK 0x00000004
-#define WLAN_HF_TIMER_CONTROL_ON_GET(x) (((x) & WLAN_HF_TIMER_CONTROL_ON_MASK) >> WLAN_HF_TIMER_CONTROL_ON_LSB)
-#define WLAN_HF_TIMER_CONTROL_ON_SET(x) (((x) << WLAN_HF_TIMER_CONTROL_ON_LSB) & WLAN_HF_TIMER_CONTROL_ON_MASK)
-#define WLAN_HF_TIMER_CONTROL_AUTO_RESTART_MSB 1
-#define WLAN_HF_TIMER_CONTROL_AUTO_RESTART_LSB 1
-#define WLAN_HF_TIMER_CONTROL_AUTO_RESTART_MASK 0x00000002
-#define WLAN_HF_TIMER_CONTROL_AUTO_RESTART_GET(x) (((x) & WLAN_HF_TIMER_CONTROL_AUTO_RESTART_MASK) >> WLAN_HF_TIMER_CONTROL_AUTO_RESTART_LSB)
-#define WLAN_HF_TIMER_CONTROL_AUTO_RESTART_SET(x) (((x) << WLAN_HF_TIMER_CONTROL_AUTO_RESTART_LSB) & WLAN_HF_TIMER_CONTROL_AUTO_RESTART_MASK)
-#define WLAN_HF_TIMER_CONTROL_RESET_MSB 0
-#define WLAN_HF_TIMER_CONTROL_RESET_LSB 0
-#define WLAN_HF_TIMER_CONTROL_RESET_MASK 0x00000001
-#define WLAN_HF_TIMER_CONTROL_RESET_GET(x) (((x) & WLAN_HF_TIMER_CONTROL_RESET_MASK) >> WLAN_HF_TIMER_CONTROL_RESET_LSB)
-#define WLAN_HF_TIMER_CONTROL_RESET_SET(x) (((x) << WLAN_HF_TIMER_CONTROL_RESET_LSB) & WLAN_HF_TIMER_CONTROL_RESET_MASK)
-
-#define WLAN_HF_TIMER_STATUS_ADDRESS 0x00000098
-#define WLAN_HF_TIMER_STATUS_OFFSET 0x00000098
-#define WLAN_HF_TIMER_STATUS_INTERRUPT_MSB 0
-#define WLAN_HF_TIMER_STATUS_INTERRUPT_LSB 0
-#define WLAN_HF_TIMER_STATUS_INTERRUPT_MASK 0x00000001
-#define WLAN_HF_TIMER_STATUS_INTERRUPT_GET(x) (((x) & WLAN_HF_TIMER_STATUS_INTERRUPT_MASK) >> WLAN_HF_TIMER_STATUS_INTERRUPT_LSB)
-#define WLAN_HF_TIMER_STATUS_INTERRUPT_SET(x) (((x) << WLAN_HF_TIMER_STATUS_INTERRUPT_LSB) & WLAN_HF_TIMER_STATUS_INTERRUPT_MASK)
-
-#define WLAN_RTC_CONTROL_ADDRESS 0x0000009c
-#define WLAN_RTC_CONTROL_OFFSET 0x0000009c
-#define WLAN_RTC_CONTROL_ENABLE_MSB 2
-#define WLAN_RTC_CONTROL_ENABLE_LSB 2
-#define WLAN_RTC_CONTROL_ENABLE_MASK 0x00000004
-#define WLAN_RTC_CONTROL_ENABLE_GET(x) (((x) & WLAN_RTC_CONTROL_ENABLE_MASK) >> WLAN_RTC_CONTROL_ENABLE_LSB)
-#define WLAN_RTC_CONTROL_ENABLE_SET(x) (((x) << WLAN_RTC_CONTROL_ENABLE_LSB) & WLAN_RTC_CONTROL_ENABLE_MASK)
-#define WLAN_RTC_CONTROL_LOAD_RTC_MSB 1
-#define WLAN_RTC_CONTROL_LOAD_RTC_LSB 1
-#define WLAN_RTC_CONTROL_LOAD_RTC_MASK 0x00000002
-#define WLAN_RTC_CONTROL_LOAD_RTC_GET(x) (((x) & WLAN_RTC_CONTROL_LOAD_RTC_MASK) >> WLAN_RTC_CONTROL_LOAD_RTC_LSB)
-#define WLAN_RTC_CONTROL_LOAD_RTC_SET(x) (((x) << WLAN_RTC_CONTROL_LOAD_RTC_LSB) & WLAN_RTC_CONTROL_LOAD_RTC_MASK)
-#define WLAN_RTC_CONTROL_LOAD_ALARM_MSB 0
-#define WLAN_RTC_CONTROL_LOAD_ALARM_LSB 0
-#define WLAN_RTC_CONTROL_LOAD_ALARM_MASK 0x00000001
-#define WLAN_RTC_CONTROL_LOAD_ALARM_GET(x) (((x) & WLAN_RTC_CONTROL_LOAD_ALARM_MASK) >> WLAN_RTC_CONTROL_LOAD_ALARM_LSB)
-#define WLAN_RTC_CONTROL_LOAD_ALARM_SET(x) (((x) << WLAN_RTC_CONTROL_LOAD_ALARM_LSB) & WLAN_RTC_CONTROL_LOAD_ALARM_MASK)
-
-#define WLAN_RTC_TIME_ADDRESS 0x000000a0
-#define WLAN_RTC_TIME_OFFSET 0x000000a0
-#define WLAN_RTC_TIME_WEEK_DAY_MSB 26
-#define WLAN_RTC_TIME_WEEK_DAY_LSB 24
-#define WLAN_RTC_TIME_WEEK_DAY_MASK 0x07000000
-#define WLAN_RTC_TIME_WEEK_DAY_GET(x) (((x) & WLAN_RTC_TIME_WEEK_DAY_MASK) >> WLAN_RTC_TIME_WEEK_DAY_LSB)
-#define WLAN_RTC_TIME_WEEK_DAY_SET(x) (((x) << WLAN_RTC_TIME_WEEK_DAY_LSB) & WLAN_RTC_TIME_WEEK_DAY_MASK)
-#define WLAN_RTC_TIME_HOUR_MSB 21
-#define WLAN_RTC_TIME_HOUR_LSB 16
-#define WLAN_RTC_TIME_HOUR_MASK 0x003f0000
-#define WLAN_RTC_TIME_HOUR_GET(x) (((x) & WLAN_RTC_TIME_HOUR_MASK) >> WLAN_RTC_TIME_HOUR_LSB)
-#define WLAN_RTC_TIME_HOUR_SET(x) (((x) << WLAN_RTC_TIME_HOUR_LSB) & WLAN_RTC_TIME_HOUR_MASK)
-#define WLAN_RTC_TIME_MINUTE_MSB 14
-#define WLAN_RTC_TIME_MINUTE_LSB 8
-#define WLAN_RTC_TIME_MINUTE_MASK 0x00007f00
-#define WLAN_RTC_TIME_MINUTE_GET(x) (((x) & WLAN_RTC_TIME_MINUTE_MASK) >> WLAN_RTC_TIME_MINUTE_LSB)
-#define WLAN_RTC_TIME_MINUTE_SET(x) (((x) << WLAN_RTC_TIME_MINUTE_LSB) & WLAN_RTC_TIME_MINUTE_MASK)
-#define WLAN_RTC_TIME_SECOND_MSB 6
-#define WLAN_RTC_TIME_SECOND_LSB 0
-#define WLAN_RTC_TIME_SECOND_MASK 0x0000007f
-#define WLAN_RTC_TIME_SECOND_GET(x) (((x) & WLAN_RTC_TIME_SECOND_MASK) >> WLAN_RTC_TIME_SECOND_LSB)
-#define WLAN_RTC_TIME_SECOND_SET(x) (((x) << WLAN_RTC_TIME_SECOND_LSB) & WLAN_RTC_TIME_SECOND_MASK)
-
-#define WLAN_RTC_DATE_ADDRESS 0x000000a4
-#define WLAN_RTC_DATE_OFFSET 0x000000a4
-#define WLAN_RTC_DATE_YEAR_MSB 23
-#define WLAN_RTC_DATE_YEAR_LSB 16
-#define WLAN_RTC_DATE_YEAR_MASK 0x00ff0000
-#define WLAN_RTC_DATE_YEAR_GET(x) (((x) & WLAN_RTC_DATE_YEAR_MASK) >> WLAN_RTC_DATE_YEAR_LSB)
-#define WLAN_RTC_DATE_YEAR_SET(x) (((x) << WLAN_RTC_DATE_YEAR_LSB) & WLAN_RTC_DATE_YEAR_MASK)
-#define WLAN_RTC_DATE_MONTH_MSB 12
-#define WLAN_RTC_DATE_MONTH_LSB 8
-#define WLAN_RTC_DATE_MONTH_MASK 0x00001f00
-#define WLAN_RTC_DATE_MONTH_GET(x) (((x) & WLAN_RTC_DATE_MONTH_MASK) >> WLAN_RTC_DATE_MONTH_LSB)
-#define WLAN_RTC_DATE_MONTH_SET(x) (((x) << WLAN_RTC_DATE_MONTH_LSB) & WLAN_RTC_DATE_MONTH_MASK)
-#define WLAN_RTC_DATE_MONTH_DAY_MSB 5
-#define WLAN_RTC_DATE_MONTH_DAY_LSB 0
-#define WLAN_RTC_DATE_MONTH_DAY_MASK 0x0000003f
-#define WLAN_RTC_DATE_MONTH_DAY_GET(x) (((x) & WLAN_RTC_DATE_MONTH_DAY_MASK) >> WLAN_RTC_DATE_MONTH_DAY_LSB)
-#define WLAN_RTC_DATE_MONTH_DAY_SET(x) (((x) << WLAN_RTC_DATE_MONTH_DAY_LSB) & WLAN_RTC_DATE_MONTH_DAY_MASK)
-
-#define WLAN_RTC_SET_TIME_ADDRESS 0x000000a8
-#define WLAN_RTC_SET_TIME_OFFSET 0x000000a8
-#define WLAN_RTC_SET_TIME_WEEK_DAY_MSB 26
-#define WLAN_RTC_SET_TIME_WEEK_DAY_LSB 24
-#define WLAN_RTC_SET_TIME_WEEK_DAY_MASK 0x07000000
-#define WLAN_RTC_SET_TIME_WEEK_DAY_GET(x) (((x) & WLAN_RTC_SET_TIME_WEEK_DAY_MASK) >> WLAN_RTC_SET_TIME_WEEK_DAY_LSB)
-#define WLAN_RTC_SET_TIME_WEEK_DAY_SET(x) (((x) << WLAN_RTC_SET_TIME_WEEK_DAY_LSB) & WLAN_RTC_SET_TIME_WEEK_DAY_MASK)
-#define WLAN_RTC_SET_TIME_HOUR_MSB 21
-#define WLAN_RTC_SET_TIME_HOUR_LSB 16
-#define WLAN_RTC_SET_TIME_HOUR_MASK 0x003f0000
-#define WLAN_RTC_SET_TIME_HOUR_GET(x) (((x) & WLAN_RTC_SET_TIME_HOUR_MASK) >> WLAN_RTC_SET_TIME_HOUR_LSB)
-#define WLAN_RTC_SET_TIME_HOUR_SET(x) (((x) << WLAN_RTC_SET_TIME_HOUR_LSB) & WLAN_RTC_SET_TIME_HOUR_MASK)
-#define WLAN_RTC_SET_TIME_MINUTE_MSB 14
-#define WLAN_RTC_SET_TIME_MINUTE_LSB 8
-#define WLAN_RTC_SET_TIME_MINUTE_MASK 0x00007f00
-#define WLAN_RTC_SET_TIME_MINUTE_GET(x) (((x) & WLAN_RTC_SET_TIME_MINUTE_MASK) >> WLAN_RTC_SET_TIME_MINUTE_LSB)
-#define WLAN_RTC_SET_TIME_MINUTE_SET(x) (((x) << WLAN_RTC_SET_TIME_MINUTE_LSB) & WLAN_RTC_SET_TIME_MINUTE_MASK)
-#define WLAN_RTC_SET_TIME_SECOND_MSB 6
-#define WLAN_RTC_SET_TIME_SECOND_LSB 0
-#define WLAN_RTC_SET_TIME_SECOND_MASK 0x0000007f
-#define WLAN_RTC_SET_TIME_SECOND_GET(x) (((x) & WLAN_RTC_SET_TIME_SECOND_MASK) >> WLAN_RTC_SET_TIME_SECOND_LSB)
-#define WLAN_RTC_SET_TIME_SECOND_SET(x) (((x) << WLAN_RTC_SET_TIME_SECOND_LSB) & WLAN_RTC_SET_TIME_SECOND_MASK)
-
-#define WLAN_RTC_SET_DATE_ADDRESS 0x000000ac
-#define WLAN_RTC_SET_DATE_OFFSET 0x000000ac
-#define WLAN_RTC_SET_DATE_YEAR_MSB 23
-#define WLAN_RTC_SET_DATE_YEAR_LSB 16
-#define WLAN_RTC_SET_DATE_YEAR_MASK 0x00ff0000
-#define WLAN_RTC_SET_DATE_YEAR_GET(x) (((x) & WLAN_RTC_SET_DATE_YEAR_MASK) >> WLAN_RTC_SET_DATE_YEAR_LSB)
-#define WLAN_RTC_SET_DATE_YEAR_SET(x) (((x) << WLAN_RTC_SET_DATE_YEAR_LSB) & WLAN_RTC_SET_DATE_YEAR_MASK)
-#define WLAN_RTC_SET_DATE_MONTH_MSB 12
-#define WLAN_RTC_SET_DATE_MONTH_LSB 8
-#define WLAN_RTC_SET_DATE_MONTH_MASK 0x00001f00
-#define WLAN_RTC_SET_DATE_MONTH_GET(x) (((x) & WLAN_RTC_SET_DATE_MONTH_MASK) >> WLAN_RTC_SET_DATE_MONTH_LSB)
-#define WLAN_RTC_SET_DATE_MONTH_SET(x) (((x) << WLAN_RTC_SET_DATE_MONTH_LSB) & WLAN_RTC_SET_DATE_MONTH_MASK)
-#define WLAN_RTC_SET_DATE_MONTH_DAY_MSB 5
-#define WLAN_RTC_SET_DATE_MONTH_DAY_LSB 0
-#define WLAN_RTC_SET_DATE_MONTH_DAY_MASK 0x0000003f
-#define WLAN_RTC_SET_DATE_MONTH_DAY_GET(x) (((x) & WLAN_RTC_SET_DATE_MONTH_DAY_MASK) >> WLAN_RTC_SET_DATE_MONTH_DAY_LSB)
-#define WLAN_RTC_SET_DATE_MONTH_DAY_SET(x) (((x) << WLAN_RTC_SET_DATE_MONTH_DAY_LSB) & WLAN_RTC_SET_DATE_MONTH_DAY_MASK)
-
-#define WLAN_RTC_SET_ALARM_ADDRESS 0x000000b0
-#define WLAN_RTC_SET_ALARM_OFFSET 0x000000b0
-#define WLAN_RTC_SET_ALARM_HOUR_MSB 21
-#define WLAN_RTC_SET_ALARM_HOUR_LSB 16
-#define WLAN_RTC_SET_ALARM_HOUR_MASK 0x003f0000
-#define WLAN_RTC_SET_ALARM_HOUR_GET(x) (((x) & WLAN_RTC_SET_ALARM_HOUR_MASK) >> WLAN_RTC_SET_ALARM_HOUR_LSB)
-#define WLAN_RTC_SET_ALARM_HOUR_SET(x) (((x) << WLAN_RTC_SET_ALARM_HOUR_LSB) & WLAN_RTC_SET_ALARM_HOUR_MASK)
-#define WLAN_RTC_SET_ALARM_MINUTE_MSB 14
-#define WLAN_RTC_SET_ALARM_MINUTE_LSB 8
-#define WLAN_RTC_SET_ALARM_MINUTE_MASK 0x00007f00
-#define WLAN_RTC_SET_ALARM_MINUTE_GET(x) (((x) & WLAN_RTC_SET_ALARM_MINUTE_MASK) >> WLAN_RTC_SET_ALARM_MINUTE_LSB)
-#define WLAN_RTC_SET_ALARM_MINUTE_SET(x) (((x) << WLAN_RTC_SET_ALARM_MINUTE_LSB) & WLAN_RTC_SET_ALARM_MINUTE_MASK)
-#define WLAN_RTC_SET_ALARM_SECOND_MSB 6
-#define WLAN_RTC_SET_ALARM_SECOND_LSB 0
-#define WLAN_RTC_SET_ALARM_SECOND_MASK 0x0000007f
-#define WLAN_RTC_SET_ALARM_SECOND_GET(x) (((x) & WLAN_RTC_SET_ALARM_SECOND_MASK) >> WLAN_RTC_SET_ALARM_SECOND_LSB)
-#define WLAN_RTC_SET_ALARM_SECOND_SET(x) (((x) << WLAN_RTC_SET_ALARM_SECOND_LSB) & WLAN_RTC_SET_ALARM_SECOND_MASK)
-
-#define WLAN_RTC_CONFIG_ADDRESS 0x000000b4
-#define WLAN_RTC_CONFIG_OFFSET 0x000000b4
-#define WLAN_RTC_CONFIG_BCD_MSB 2
-#define WLAN_RTC_CONFIG_BCD_LSB 2
-#define WLAN_RTC_CONFIG_BCD_MASK 0x00000004
-#define WLAN_RTC_CONFIG_BCD_GET(x) (((x) & WLAN_RTC_CONFIG_BCD_MASK) >> WLAN_RTC_CONFIG_BCD_LSB)
-#define WLAN_RTC_CONFIG_BCD_SET(x) (((x) << WLAN_RTC_CONFIG_BCD_LSB) & WLAN_RTC_CONFIG_BCD_MASK)
-#define WLAN_RTC_CONFIG_TWELVE_HOUR_MSB 1
-#define WLAN_RTC_CONFIG_TWELVE_HOUR_LSB 1
-#define WLAN_RTC_CONFIG_TWELVE_HOUR_MASK 0x00000002
-#define WLAN_RTC_CONFIG_TWELVE_HOUR_GET(x) (((x) & WLAN_RTC_CONFIG_TWELVE_HOUR_MASK) >> WLAN_RTC_CONFIG_TWELVE_HOUR_LSB)
-#define WLAN_RTC_CONFIG_TWELVE_HOUR_SET(x) (((x) << WLAN_RTC_CONFIG_TWELVE_HOUR_LSB) & WLAN_RTC_CONFIG_TWELVE_HOUR_MASK)
-#define WLAN_RTC_CONFIG_DSE_MSB 0
-#define WLAN_RTC_CONFIG_DSE_LSB 0
-#define WLAN_RTC_CONFIG_DSE_MASK 0x00000001
-#define WLAN_RTC_CONFIG_DSE_GET(x) (((x) & WLAN_RTC_CONFIG_DSE_MASK) >> WLAN_RTC_CONFIG_DSE_LSB)
-#define WLAN_RTC_CONFIG_DSE_SET(x) (((x) << WLAN_RTC_CONFIG_DSE_LSB) & WLAN_RTC_CONFIG_DSE_MASK)
-
-#define WLAN_RTC_ALARM_STATUS_ADDRESS 0x000000b8
-#define WLAN_RTC_ALARM_STATUS_OFFSET 0x000000b8
-#define WLAN_RTC_ALARM_STATUS_ENABLE_MSB 1
-#define WLAN_RTC_ALARM_STATUS_ENABLE_LSB 1
-#define WLAN_RTC_ALARM_STATUS_ENABLE_MASK 0x00000002
-#define WLAN_RTC_ALARM_STATUS_ENABLE_GET(x) (((x) & WLAN_RTC_ALARM_STATUS_ENABLE_MASK) >> WLAN_RTC_ALARM_STATUS_ENABLE_LSB)
-#define WLAN_RTC_ALARM_STATUS_ENABLE_SET(x) (((x) << WLAN_RTC_ALARM_STATUS_ENABLE_LSB) & WLAN_RTC_ALARM_STATUS_ENABLE_MASK)
-#define WLAN_RTC_ALARM_STATUS_INTERRUPT_MSB 0
-#define WLAN_RTC_ALARM_STATUS_INTERRUPT_LSB 0
-#define WLAN_RTC_ALARM_STATUS_INTERRUPT_MASK 0x00000001
-#define WLAN_RTC_ALARM_STATUS_INTERRUPT_GET(x) (((x) & WLAN_RTC_ALARM_STATUS_INTERRUPT_MASK) >> WLAN_RTC_ALARM_STATUS_INTERRUPT_LSB)
-#define WLAN_RTC_ALARM_STATUS_INTERRUPT_SET(x) (((x) << WLAN_RTC_ALARM_STATUS_INTERRUPT_LSB) & WLAN_RTC_ALARM_STATUS_INTERRUPT_MASK)
-
-#define WLAN_UART_WAKEUP_ADDRESS 0x000000bc
-#define WLAN_UART_WAKEUP_OFFSET 0x000000bc
-#define WLAN_UART_WAKEUP_ENABLE_MSB 0
-#define WLAN_UART_WAKEUP_ENABLE_LSB 0
-#define WLAN_UART_WAKEUP_ENABLE_MASK 0x00000001
-#define WLAN_UART_WAKEUP_ENABLE_GET(x) (((x) & WLAN_UART_WAKEUP_ENABLE_MASK) >> WLAN_UART_WAKEUP_ENABLE_LSB)
-#define WLAN_UART_WAKEUP_ENABLE_SET(x) (((x) << WLAN_UART_WAKEUP_ENABLE_LSB) & WLAN_UART_WAKEUP_ENABLE_MASK)
-
-#define WLAN_RESET_CAUSE_ADDRESS 0x000000c0
-#define WLAN_RESET_CAUSE_OFFSET 0x000000c0
-#define WLAN_RESET_CAUSE_LAST_MSB 2
-#define WLAN_RESET_CAUSE_LAST_LSB 0
-#define WLAN_RESET_CAUSE_LAST_MASK 0x00000007
-#define WLAN_RESET_CAUSE_LAST_GET(x) (((x) & WLAN_RESET_CAUSE_LAST_MASK) >> WLAN_RESET_CAUSE_LAST_LSB)
-#define WLAN_RESET_CAUSE_LAST_SET(x) (((x) << WLAN_RESET_CAUSE_LAST_LSB) & WLAN_RESET_CAUSE_LAST_MASK)
-
#define WLAN_SYSTEM_SLEEP_ADDRESS 0x000000c4
#define WLAN_SYSTEM_SLEEP_OFFSET 0x000000c4
#define WLAN_SYSTEM_SLEEP_HOST_IF_MSB 4
@@ -799,69 +146,6 @@
#define WLAN_SYSTEM_SLEEP_DISABLE_GET(x) (((x) & WLAN_SYSTEM_SLEEP_DISABLE_MASK) >> WLAN_SYSTEM_SLEEP_DISABLE_LSB)
#define WLAN_SYSTEM_SLEEP_DISABLE_SET(x) (((x) << WLAN_SYSTEM_SLEEP_DISABLE_LSB) & WLAN_SYSTEM_SLEEP_DISABLE_MASK)
-#define WLAN_SDIO_WRAPPER_ADDRESS 0x000000c8
-#define WLAN_SDIO_WRAPPER_OFFSET 0x000000c8
-#define WLAN_SDIO_WRAPPER_SLEEP_MSB 3
-#define WLAN_SDIO_WRAPPER_SLEEP_LSB 3
-#define WLAN_SDIO_WRAPPER_SLEEP_MASK 0x00000008
-#define WLAN_SDIO_WRAPPER_SLEEP_GET(x) (((x) & WLAN_SDIO_WRAPPER_SLEEP_MASK) >> WLAN_SDIO_WRAPPER_SLEEP_LSB)
-#define WLAN_SDIO_WRAPPER_SLEEP_SET(x) (((x) << WLAN_SDIO_WRAPPER_SLEEP_LSB) & WLAN_SDIO_WRAPPER_SLEEP_MASK)
-#define WLAN_SDIO_WRAPPER_WAKEUP_MSB 2
-#define WLAN_SDIO_WRAPPER_WAKEUP_LSB 2
-#define WLAN_SDIO_WRAPPER_WAKEUP_MASK 0x00000004
-#define WLAN_SDIO_WRAPPER_WAKEUP_GET(x) (((x) & WLAN_SDIO_WRAPPER_WAKEUP_MASK) >> WLAN_SDIO_WRAPPER_WAKEUP_LSB)
-#define WLAN_SDIO_WRAPPER_WAKEUP_SET(x) (((x) << WLAN_SDIO_WRAPPER_WAKEUP_LSB) & WLAN_SDIO_WRAPPER_WAKEUP_MASK)
-#define WLAN_SDIO_WRAPPER_SOC_ON_MSB 1
-#define WLAN_SDIO_WRAPPER_SOC_ON_LSB 1
-#define WLAN_SDIO_WRAPPER_SOC_ON_MASK 0x00000002
-#define WLAN_SDIO_WRAPPER_SOC_ON_GET(x) (((x) & WLAN_SDIO_WRAPPER_SOC_ON_MASK) >> WLAN_SDIO_WRAPPER_SOC_ON_LSB)
-#define WLAN_SDIO_WRAPPER_SOC_ON_SET(x) (((x) << WLAN_SDIO_WRAPPER_SOC_ON_LSB) & WLAN_SDIO_WRAPPER_SOC_ON_MASK)
-#define WLAN_SDIO_WRAPPER_ON_MSB 0
-#define WLAN_SDIO_WRAPPER_ON_LSB 0
-#define WLAN_SDIO_WRAPPER_ON_MASK 0x00000001
-#define WLAN_SDIO_WRAPPER_ON_GET(x) (((x) & WLAN_SDIO_WRAPPER_ON_MASK) >> WLAN_SDIO_WRAPPER_ON_LSB)
-#define WLAN_SDIO_WRAPPER_ON_SET(x) (((x) << WLAN_SDIO_WRAPPER_ON_LSB) & WLAN_SDIO_WRAPPER_ON_MASK)
-
-#define WLAN_MAC_SLEEP_CONTROL_ADDRESS 0x000000cc
-#define WLAN_MAC_SLEEP_CONTROL_OFFSET 0x000000cc
-#define WLAN_MAC_SLEEP_CONTROL_ENABLE_MSB 1
-#define WLAN_MAC_SLEEP_CONTROL_ENABLE_LSB 0
-#define WLAN_MAC_SLEEP_CONTROL_ENABLE_MASK 0x00000003
-#define WLAN_MAC_SLEEP_CONTROL_ENABLE_GET(x) (((x) & WLAN_MAC_SLEEP_CONTROL_ENABLE_MASK) >> WLAN_MAC_SLEEP_CONTROL_ENABLE_LSB)
-#define WLAN_MAC_SLEEP_CONTROL_ENABLE_SET(x) (((x) << WLAN_MAC_SLEEP_CONTROL_ENABLE_LSB) & WLAN_MAC_SLEEP_CONTROL_ENABLE_MASK)
-
-#define WLAN_KEEP_AWAKE_ADDRESS 0x000000d0
-#define WLAN_KEEP_AWAKE_OFFSET 0x000000d0
-#define WLAN_KEEP_AWAKE_COUNT_MSB 7
-#define WLAN_KEEP_AWAKE_COUNT_LSB 0
-#define WLAN_KEEP_AWAKE_COUNT_MASK 0x000000ff
-#define WLAN_KEEP_AWAKE_COUNT_GET(x) (((x) & WLAN_KEEP_AWAKE_COUNT_MASK) >> WLAN_KEEP_AWAKE_COUNT_LSB)
-#define WLAN_KEEP_AWAKE_COUNT_SET(x) (((x) << WLAN_KEEP_AWAKE_COUNT_LSB) & WLAN_KEEP_AWAKE_COUNT_MASK)
-
-#define WLAN_LPO_CAL_TIME_ADDRESS 0x000000d4
-#define WLAN_LPO_CAL_TIME_OFFSET 0x000000d4
-#define WLAN_LPO_CAL_TIME_LENGTH_MSB 13
-#define WLAN_LPO_CAL_TIME_LENGTH_LSB 0
-#define WLAN_LPO_CAL_TIME_LENGTH_MASK 0x00003fff
-#define WLAN_LPO_CAL_TIME_LENGTH_GET(x) (((x) & WLAN_LPO_CAL_TIME_LENGTH_MASK) >> WLAN_LPO_CAL_TIME_LENGTH_LSB)
-#define WLAN_LPO_CAL_TIME_LENGTH_SET(x) (((x) << WLAN_LPO_CAL_TIME_LENGTH_LSB) & WLAN_LPO_CAL_TIME_LENGTH_MASK)
-
-#define WLAN_LPO_INIT_DIVIDEND_INT_ADDRESS 0x000000d8
-#define WLAN_LPO_INIT_DIVIDEND_INT_OFFSET 0x000000d8
-#define WLAN_LPO_INIT_DIVIDEND_INT_VALUE_MSB 23
-#define WLAN_LPO_INIT_DIVIDEND_INT_VALUE_LSB 0
-#define WLAN_LPO_INIT_DIVIDEND_INT_VALUE_MASK 0x00ffffff
-#define WLAN_LPO_INIT_DIVIDEND_INT_VALUE_GET(x) (((x) & WLAN_LPO_INIT_DIVIDEND_INT_VALUE_MASK) >> WLAN_LPO_INIT_DIVIDEND_INT_VALUE_LSB)
-#define WLAN_LPO_INIT_DIVIDEND_INT_VALUE_SET(x) (((x) << WLAN_LPO_INIT_DIVIDEND_INT_VALUE_LSB) & WLAN_LPO_INIT_DIVIDEND_INT_VALUE_MASK)
-
-#define WLAN_LPO_INIT_DIVIDEND_FRACTION_ADDRESS 0x000000dc
-#define WLAN_LPO_INIT_DIVIDEND_FRACTION_OFFSET 0x000000dc
-#define WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_MSB 10
-#define WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB 0
-#define WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK 0x000007ff
-#define WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_GET(x) (((x) & WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK) >> WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB)
-#define WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_SET(x) (((x) << WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_LSB) & WLAN_LPO_INIT_DIVIDEND_FRACTION_VALUE_MASK)
-
#define WLAN_LPO_CAL_ADDRESS 0x000000e0
#define WLAN_LPO_CAL_OFFSET 0x000000e0
#define WLAN_LPO_CAL_ENABLE_MSB 20
@@ -875,1191 +159,4 @@
#define WLAN_LPO_CAL_COUNT_GET(x) (((x) & WLAN_LPO_CAL_COUNT_MASK) >> WLAN_LPO_CAL_COUNT_LSB)
#define WLAN_LPO_CAL_COUNT_SET(x) (((x) << WLAN_LPO_CAL_COUNT_LSB) & WLAN_LPO_CAL_COUNT_MASK)
-#define WLAN_LPO_CAL_TEST_CONTROL_ADDRESS 0x000000e4
-#define WLAN_LPO_CAL_TEST_CONTROL_OFFSET 0x000000e4
-#define WLAN_LPO_CAL_TEST_CONTROL_ENABLE_MSB 5
-#define WLAN_LPO_CAL_TEST_CONTROL_ENABLE_LSB 5
-#define WLAN_LPO_CAL_TEST_CONTROL_ENABLE_MASK 0x00000020
-#define WLAN_LPO_CAL_TEST_CONTROL_ENABLE_GET(x) (((x) & WLAN_LPO_CAL_TEST_CONTROL_ENABLE_MASK) >> WLAN_LPO_CAL_TEST_CONTROL_ENABLE_LSB)
-#define WLAN_LPO_CAL_TEST_CONTROL_ENABLE_SET(x) (((x) << WLAN_LPO_CAL_TEST_CONTROL_ENABLE_LSB) & WLAN_LPO_CAL_TEST_CONTROL_ENABLE_MASK)
-#define WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MSB 4
-#define WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB 0
-#define WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK 0x0000001f
-#define WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_GET(x) (((x) & WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK) >> WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB)
-#define WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_SET(x) (((x) << WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_LSB) & WLAN_LPO_CAL_TEST_CONTROL_RTC_CYCLES_MASK)
-
-#define WLAN_LPO_CAL_TEST_STATUS_ADDRESS 0x000000e8
-#define WLAN_LPO_CAL_TEST_STATUS_OFFSET 0x000000e8
-#define WLAN_LPO_CAL_TEST_STATUS_READY_MSB 16
-#define WLAN_LPO_CAL_TEST_STATUS_READY_LSB 16
-#define WLAN_LPO_CAL_TEST_STATUS_READY_MASK 0x00010000
-#define WLAN_LPO_CAL_TEST_STATUS_READY_GET(x) (((x) & WLAN_LPO_CAL_TEST_STATUS_READY_MASK) >> WLAN_LPO_CAL_TEST_STATUS_READY_LSB)
-#define WLAN_LPO_CAL_TEST_STATUS_READY_SET(x) (((x) << WLAN_LPO_CAL_TEST_STATUS_READY_LSB) & WLAN_LPO_CAL_TEST_STATUS_READY_MASK)
-#define WLAN_LPO_CAL_TEST_STATUS_COUNT_MSB 15
-#define WLAN_LPO_CAL_TEST_STATUS_COUNT_LSB 0
-#define WLAN_LPO_CAL_TEST_STATUS_COUNT_MASK 0x0000ffff
-#define WLAN_LPO_CAL_TEST_STATUS_COUNT_GET(x) (((x) & WLAN_LPO_CAL_TEST_STATUS_COUNT_MASK) >> WLAN_LPO_CAL_TEST_STATUS_COUNT_LSB)
-#define WLAN_LPO_CAL_TEST_STATUS_COUNT_SET(x) (((x) << WLAN_LPO_CAL_TEST_STATUS_COUNT_LSB) & WLAN_LPO_CAL_TEST_STATUS_COUNT_MASK)
-
-#define WLAN_CHIP_ID_ADDRESS 0x000000ec
-#define WLAN_CHIP_ID_OFFSET 0x000000ec
-#define WLAN_CHIP_ID_DEVICE_ID_MSB 31
-#define WLAN_CHIP_ID_DEVICE_ID_LSB 16
-#define WLAN_CHIP_ID_DEVICE_ID_MASK 0xffff0000
-#define WLAN_CHIP_ID_DEVICE_ID_GET(x) (((x) & WLAN_CHIP_ID_DEVICE_ID_MASK) >> WLAN_CHIP_ID_DEVICE_ID_LSB)
-#define WLAN_CHIP_ID_DEVICE_ID_SET(x) (((x) << WLAN_CHIP_ID_DEVICE_ID_LSB) & WLAN_CHIP_ID_DEVICE_ID_MASK)
-#define WLAN_CHIP_ID_CONFIG_ID_MSB 15
-#define WLAN_CHIP_ID_CONFIG_ID_LSB 4
-#define WLAN_CHIP_ID_CONFIG_ID_MASK 0x0000fff0
-#define WLAN_CHIP_ID_CONFIG_ID_GET(x) (((x) & WLAN_CHIP_ID_CONFIG_ID_MASK) >> WLAN_CHIP_ID_CONFIG_ID_LSB)
-#define WLAN_CHIP_ID_CONFIG_ID_SET(x) (((x) << WLAN_CHIP_ID_CONFIG_ID_LSB) & WLAN_CHIP_ID_CONFIG_ID_MASK)
-#define WLAN_CHIP_ID_VERSION_ID_MSB 3
-#define WLAN_CHIP_ID_VERSION_ID_LSB 0
-#define WLAN_CHIP_ID_VERSION_ID_MASK 0x0000000f
-#define WLAN_CHIP_ID_VERSION_ID_GET(x) (((x) & WLAN_CHIP_ID_VERSION_ID_MASK) >> WLAN_CHIP_ID_VERSION_ID_LSB)
-#define WLAN_CHIP_ID_VERSION_ID_SET(x) (((x) << WLAN_CHIP_ID_VERSION_ID_LSB) & WLAN_CHIP_ID_VERSION_ID_MASK)
-
-#define WLAN_DERIVED_RTC_CLK_ADDRESS 0x000000f0
-#define WLAN_DERIVED_RTC_CLK_OFFSET 0x000000f0
-#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MSB 20
-#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB 20
-#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK 0x00100000
-#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_GET(x) (((x) & WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK) >> WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB)
-#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_SET(x) (((x) << WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_LSB) & WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_EN_MASK)
-#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_MSB 18
-#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB 18
-#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK 0x00040000
-#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_GET(x) (((x) & WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK) >> WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB)
-#define WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_SET(x) (((x) << WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_LSB) & WLAN_DERIVED_RTC_CLK_EXTERNAL_DETECT_MASK)
-#define WLAN_DERIVED_RTC_CLK_FORCE_MSB 17
-#define WLAN_DERIVED_RTC_CLK_FORCE_LSB 16
-#define WLAN_DERIVED_RTC_CLK_FORCE_MASK 0x00030000
-#define WLAN_DERIVED_RTC_CLK_FORCE_GET(x) (((x) & WLAN_DERIVED_RTC_CLK_FORCE_MASK) >> WLAN_DERIVED_RTC_CLK_FORCE_LSB)
-#define WLAN_DERIVED_RTC_CLK_FORCE_SET(x) (((x) << WLAN_DERIVED_RTC_CLK_FORCE_LSB) & WLAN_DERIVED_RTC_CLK_FORCE_MASK)
-#define WLAN_DERIVED_RTC_CLK_PERIOD_MSB 15
-#define WLAN_DERIVED_RTC_CLK_PERIOD_LSB 1
-#define WLAN_DERIVED_RTC_CLK_PERIOD_MASK 0x0000fffe
-#define WLAN_DERIVED_RTC_CLK_PERIOD_GET(x) (((x) & WLAN_DERIVED_RTC_CLK_PERIOD_MASK) >> WLAN_DERIVED_RTC_CLK_PERIOD_LSB)
-#define WLAN_DERIVED_RTC_CLK_PERIOD_SET(x) (((x) << WLAN_DERIVED_RTC_CLK_PERIOD_LSB) & WLAN_DERIVED_RTC_CLK_PERIOD_MASK)
-
-#define MAC_PCU_SLP32_MODE_ADDRESS 0x000000f4
-#define MAC_PCU_SLP32_MODE_OFFSET 0x000000f4
-#define MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_MSB 24
-#define MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_LSB 24
-#define MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_MASK 0x01000000
-#define MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_GET(x) (((x) & MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_MASK) >> MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_LSB)
-#define MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_SET(x) (((x) << MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_LSB) & MAC_PCU_SLP32_MODE_TSF2_WRITE_STATUS_MASK)
-#define MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_MSB 23
-#define MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_LSB 23
-#define MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_MASK 0x00800000
-#define MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_GET(x) (((x) & MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_MASK) >> MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_LSB)
-#define MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_SET(x) (((x) << MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_LSB) & MAC_PCU_SLP32_MODE_FORCE_BIAS_BLOCK_ON_MASK)
-#define MAC_PCU_SLP32_MODE_DISABLE_32KHZ_MSB 22
-#define MAC_PCU_SLP32_MODE_DISABLE_32KHZ_LSB 22
-#define MAC_PCU_SLP32_MODE_DISABLE_32KHZ_MASK 0x00400000
-#define MAC_PCU_SLP32_MODE_DISABLE_32KHZ_GET(x) (((x) & MAC_PCU_SLP32_MODE_DISABLE_32KHZ_MASK) >> MAC_PCU_SLP32_MODE_DISABLE_32KHZ_LSB)
-#define MAC_PCU_SLP32_MODE_DISABLE_32KHZ_SET(x) (((x) << MAC_PCU_SLP32_MODE_DISABLE_32KHZ_LSB) & MAC_PCU_SLP32_MODE_DISABLE_32KHZ_MASK)
-#define MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_MSB 21
-#define MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_LSB 21
-#define MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_MASK 0x00200000
-#define MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_GET(x) (((x) & MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_MASK) >> MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_LSB)
-#define MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_SET(x) (((x) << MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_LSB) & MAC_PCU_SLP32_MODE_TSF_WRITE_STATUS_MASK)
-#define MAC_PCU_SLP32_MODE_ENABLE_MSB 20
-#define MAC_PCU_SLP32_MODE_ENABLE_LSB 20
-#define MAC_PCU_SLP32_MODE_ENABLE_MASK 0x00100000
-#define MAC_PCU_SLP32_MODE_ENABLE_GET(x) (((x) & MAC_PCU_SLP32_MODE_ENABLE_MASK) >> MAC_PCU_SLP32_MODE_ENABLE_LSB)
-#define MAC_PCU_SLP32_MODE_ENABLE_SET(x) (((x) << MAC_PCU_SLP32_MODE_ENABLE_LSB) & MAC_PCU_SLP32_MODE_ENABLE_MASK)
-#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MSB 19
-#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB 0
-#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK 0x000fffff
-#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_GET(x) (((x) & MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK) >> MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB)
-#define MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_SET(x) (((x) << MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_LSB) & MAC_PCU_SLP32_MODE_HALF_CLK_LATENCY_MASK)
-
-#define MAC_PCU_SLP32_WAKE_ADDRESS 0x000000f8
-#define MAC_PCU_SLP32_WAKE_OFFSET 0x000000f8
-#define MAC_PCU_SLP32_WAKE_XTL_TIME_MSB 15
-#define MAC_PCU_SLP32_WAKE_XTL_TIME_LSB 0
-#define MAC_PCU_SLP32_WAKE_XTL_TIME_MASK 0x0000ffff
-#define MAC_PCU_SLP32_WAKE_XTL_TIME_GET(x) (((x) & MAC_PCU_SLP32_WAKE_XTL_TIME_MASK) >> MAC_PCU_SLP32_WAKE_XTL_TIME_LSB)
-#define MAC_PCU_SLP32_WAKE_XTL_TIME_SET(x) (((x) << MAC_PCU_SLP32_WAKE_XTL_TIME_LSB) & MAC_PCU_SLP32_WAKE_XTL_TIME_MASK)
-
-#define MAC_PCU_SLP32_INC_ADDRESS 0x000000fc
-#define MAC_PCU_SLP32_INC_OFFSET 0x000000fc
-#define MAC_PCU_SLP32_INC_TSF_INC_MSB 19
-#define MAC_PCU_SLP32_INC_TSF_INC_LSB 0
-#define MAC_PCU_SLP32_INC_TSF_INC_MASK 0x000fffff
-#define MAC_PCU_SLP32_INC_TSF_INC_GET(x) (((x) & MAC_PCU_SLP32_INC_TSF_INC_MASK) >> MAC_PCU_SLP32_INC_TSF_INC_LSB)
-#define MAC_PCU_SLP32_INC_TSF_INC_SET(x) (((x) << MAC_PCU_SLP32_INC_TSF_INC_LSB) & MAC_PCU_SLP32_INC_TSF_INC_MASK)
-
-#define MAC_PCU_SLP_MIB1_ADDRESS 0x00000100
-#define MAC_PCU_SLP_MIB1_OFFSET 0x00000100
-#define MAC_PCU_SLP_MIB1_SLEEP_CNT_MSB 31
-#define MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB 0
-#define MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK 0xffffffff
-#define MAC_PCU_SLP_MIB1_SLEEP_CNT_GET(x) (((x) & MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK) >> MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB)
-#define MAC_PCU_SLP_MIB1_SLEEP_CNT_SET(x) (((x) << MAC_PCU_SLP_MIB1_SLEEP_CNT_LSB) & MAC_PCU_SLP_MIB1_SLEEP_CNT_MASK)
-
-#define MAC_PCU_SLP_MIB2_ADDRESS 0x00000104
-#define MAC_PCU_SLP_MIB2_OFFSET 0x00000104
-#define MAC_PCU_SLP_MIB2_CYCLE_CNT_MSB 31
-#define MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB 0
-#define MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK 0xffffffff
-#define MAC_PCU_SLP_MIB2_CYCLE_CNT_GET(x) (((x) & MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK) >> MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB)
-#define MAC_PCU_SLP_MIB2_CYCLE_CNT_SET(x) (((x) << MAC_PCU_SLP_MIB2_CYCLE_CNT_LSB) & MAC_PCU_SLP_MIB2_CYCLE_CNT_MASK)
-
-#define MAC_PCU_SLP_MIB3_ADDRESS 0x00000108
-#define MAC_PCU_SLP_MIB3_OFFSET 0x00000108
-#define MAC_PCU_SLP_MIB3_PENDING_MSB 1
-#define MAC_PCU_SLP_MIB3_PENDING_LSB 1
-#define MAC_PCU_SLP_MIB3_PENDING_MASK 0x00000002
-#define MAC_PCU_SLP_MIB3_PENDING_GET(x) (((x) & MAC_PCU_SLP_MIB3_PENDING_MASK) >> MAC_PCU_SLP_MIB3_PENDING_LSB)
-#define MAC_PCU_SLP_MIB3_PENDING_SET(x) (((x) << MAC_PCU_SLP_MIB3_PENDING_LSB) & MAC_PCU_SLP_MIB3_PENDING_MASK)
-#define MAC_PCU_SLP_MIB3_CLR_CNT_MSB 0
-#define MAC_PCU_SLP_MIB3_CLR_CNT_LSB 0
-#define MAC_PCU_SLP_MIB3_CLR_CNT_MASK 0x00000001
-#define MAC_PCU_SLP_MIB3_CLR_CNT_GET(x) (((x) & MAC_PCU_SLP_MIB3_CLR_CNT_MASK) >> MAC_PCU_SLP_MIB3_CLR_CNT_LSB)
-#define MAC_PCU_SLP_MIB3_CLR_CNT_SET(x) (((x) << MAC_PCU_SLP_MIB3_CLR_CNT_LSB) & MAC_PCU_SLP_MIB3_CLR_CNT_MASK)
-
-#define WLAN_POWER_REG_ADDRESS 0x0000010c
-#define WLAN_POWER_REG_OFFSET 0x0000010c
-#define WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_MSB 15
-#define WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_LSB 15
-#define WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_MASK 0x00008000
-#define WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_GET(x) (((x) & WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_MASK) >> WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_LSB)
-#define WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_SET(x) (((x) << WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_LSB) & WLAN_POWER_REG_SLEEP_MAKE_N_BREAK_EN_MASK)
-#define WLAN_POWER_REG_DEBUG_EN_MSB 14
-#define WLAN_POWER_REG_DEBUG_EN_LSB 14
-#define WLAN_POWER_REG_DEBUG_EN_MASK 0x00004000
-#define WLAN_POWER_REG_DEBUG_EN_GET(x) (((x) & WLAN_POWER_REG_DEBUG_EN_MASK) >> WLAN_POWER_REG_DEBUG_EN_LSB)
-#define WLAN_POWER_REG_DEBUG_EN_SET(x) (((x) << WLAN_POWER_REG_DEBUG_EN_LSB) & WLAN_POWER_REG_DEBUG_EN_MASK)
-#define WLAN_POWER_REG_WLAN_BB_PWD_EN_MSB 13
-#define WLAN_POWER_REG_WLAN_BB_PWD_EN_LSB 13
-#define WLAN_POWER_REG_WLAN_BB_PWD_EN_MASK 0x00002000
-#define WLAN_POWER_REG_WLAN_BB_PWD_EN_GET(x) (((x) & WLAN_POWER_REG_WLAN_BB_PWD_EN_MASK) >> WLAN_POWER_REG_WLAN_BB_PWD_EN_LSB)
-#define WLAN_POWER_REG_WLAN_BB_PWD_EN_SET(x) (((x) << WLAN_POWER_REG_WLAN_BB_PWD_EN_LSB) & WLAN_POWER_REG_WLAN_BB_PWD_EN_MASK)
-#define WLAN_POWER_REG_WLAN_MAC_PWD_EN_MSB 12
-#define WLAN_POWER_REG_WLAN_MAC_PWD_EN_LSB 12
-#define WLAN_POWER_REG_WLAN_MAC_PWD_EN_MASK 0x00001000
-#define WLAN_POWER_REG_WLAN_MAC_PWD_EN_GET(x) (((x) & WLAN_POWER_REG_WLAN_MAC_PWD_EN_MASK) >> WLAN_POWER_REG_WLAN_MAC_PWD_EN_LSB)
-#define WLAN_POWER_REG_WLAN_MAC_PWD_EN_SET(x) (((x) << WLAN_POWER_REG_WLAN_MAC_PWD_EN_LSB) & WLAN_POWER_REG_WLAN_MAC_PWD_EN_MASK)
-#define WLAN_POWER_REG_VLVL_MSB 11
-#define WLAN_POWER_REG_VLVL_LSB 8
-#define WLAN_POWER_REG_VLVL_MASK 0x00000f00
-#define WLAN_POWER_REG_VLVL_GET(x) (((x) & WLAN_POWER_REG_VLVL_MASK) >> WLAN_POWER_REG_VLVL_LSB)
-#define WLAN_POWER_REG_VLVL_SET(x) (((x) << WLAN_POWER_REG_VLVL_LSB) & WLAN_POWER_REG_VLVL_MASK)
-#define WLAN_POWER_REG_CPU_INT_ENABLE_MSB 7
-#define WLAN_POWER_REG_CPU_INT_ENABLE_LSB 7
-#define WLAN_POWER_REG_CPU_INT_ENABLE_MASK 0x00000080
-#define WLAN_POWER_REG_CPU_INT_ENABLE_GET(x) (((x) & WLAN_POWER_REG_CPU_INT_ENABLE_MASK) >> WLAN_POWER_REG_CPU_INT_ENABLE_LSB)
-#define WLAN_POWER_REG_CPU_INT_ENABLE_SET(x) (((x) << WLAN_POWER_REG_CPU_INT_ENABLE_LSB) & WLAN_POWER_REG_CPU_INT_ENABLE_MASK)
-#define WLAN_POWER_REG_WLAN_ISO_DIS_MSB 6
-#define WLAN_POWER_REG_WLAN_ISO_DIS_LSB 6
-#define WLAN_POWER_REG_WLAN_ISO_DIS_MASK 0x00000040
-#define WLAN_POWER_REG_WLAN_ISO_DIS_GET(x) (((x) & WLAN_POWER_REG_WLAN_ISO_DIS_MASK) >> WLAN_POWER_REG_WLAN_ISO_DIS_LSB)
-#define WLAN_POWER_REG_WLAN_ISO_DIS_SET(x) (((x) << WLAN_POWER_REG_WLAN_ISO_DIS_LSB) & WLAN_POWER_REG_WLAN_ISO_DIS_MASK)
-#define WLAN_POWER_REG_WLAN_ISO_CNTL_MSB 5
-#define WLAN_POWER_REG_WLAN_ISO_CNTL_LSB 5
-#define WLAN_POWER_REG_WLAN_ISO_CNTL_MASK 0x00000020
-#define WLAN_POWER_REG_WLAN_ISO_CNTL_GET(x) (((x) & WLAN_POWER_REG_WLAN_ISO_CNTL_MASK) >> WLAN_POWER_REG_WLAN_ISO_CNTL_LSB)
-#define WLAN_POWER_REG_WLAN_ISO_CNTL_SET(x) (((x) << WLAN_POWER_REG_WLAN_ISO_CNTL_LSB) & WLAN_POWER_REG_WLAN_ISO_CNTL_MASK)
-#define WLAN_POWER_REG_RADIO_PWD_EN_MSB 4
-#define WLAN_POWER_REG_RADIO_PWD_EN_LSB 4
-#define WLAN_POWER_REG_RADIO_PWD_EN_MASK 0x00000010
-#define WLAN_POWER_REG_RADIO_PWD_EN_GET(x) (((x) & WLAN_POWER_REG_RADIO_PWD_EN_MASK) >> WLAN_POWER_REG_RADIO_PWD_EN_LSB)
-#define WLAN_POWER_REG_RADIO_PWD_EN_SET(x) (((x) << WLAN_POWER_REG_RADIO_PWD_EN_LSB) & WLAN_POWER_REG_RADIO_PWD_EN_MASK)
-#define WLAN_POWER_REG_SOC_ISO_EN_MSB 3
-#define WLAN_POWER_REG_SOC_ISO_EN_LSB 3
-#define WLAN_POWER_REG_SOC_ISO_EN_MASK 0x00000008
-#define WLAN_POWER_REG_SOC_ISO_EN_GET(x) (((x) & WLAN_POWER_REG_SOC_ISO_EN_MASK) >> WLAN_POWER_REG_SOC_ISO_EN_LSB)
-#define WLAN_POWER_REG_SOC_ISO_EN_SET(x) (((x) << WLAN_POWER_REG_SOC_ISO_EN_LSB) & WLAN_POWER_REG_SOC_ISO_EN_MASK)
-#define WLAN_POWER_REG_WLAN_ISO_EN_MSB 2
-#define WLAN_POWER_REG_WLAN_ISO_EN_LSB 2
-#define WLAN_POWER_REG_WLAN_ISO_EN_MASK 0x00000004
-#define WLAN_POWER_REG_WLAN_ISO_EN_GET(x) (((x) & WLAN_POWER_REG_WLAN_ISO_EN_MASK) >> WLAN_POWER_REG_WLAN_ISO_EN_LSB)
-#define WLAN_POWER_REG_WLAN_ISO_EN_SET(x) (((x) << WLAN_POWER_REG_WLAN_ISO_EN_LSB) & WLAN_POWER_REG_WLAN_ISO_EN_MASK)
-#define WLAN_POWER_REG_WLAN_PWD_EN_MSB 1
-#define WLAN_POWER_REG_WLAN_PWD_EN_LSB 1
-#define WLAN_POWER_REG_WLAN_PWD_EN_MASK 0x00000002
-#define WLAN_POWER_REG_WLAN_PWD_EN_GET(x) (((x) & WLAN_POWER_REG_WLAN_PWD_EN_MASK) >> WLAN_POWER_REG_WLAN_PWD_EN_LSB)
-#define WLAN_POWER_REG_WLAN_PWD_EN_SET(x) (((x) << WLAN_POWER_REG_WLAN_PWD_EN_LSB) & WLAN_POWER_REG_WLAN_PWD_EN_MASK)
-#define WLAN_POWER_REG_POWER_EN_MSB 0
-#define WLAN_POWER_REG_POWER_EN_LSB 0
-#define WLAN_POWER_REG_POWER_EN_MASK 0x00000001
-#define WLAN_POWER_REG_POWER_EN_GET(x) (((x) & WLAN_POWER_REG_POWER_EN_MASK) >> WLAN_POWER_REG_POWER_EN_LSB)
-#define WLAN_POWER_REG_POWER_EN_SET(x) (((x) << WLAN_POWER_REG_POWER_EN_LSB) & WLAN_POWER_REG_POWER_EN_MASK)
-
-#define WLAN_CORE_CLK_CTRL_ADDRESS 0x00000110
-#define WLAN_CORE_CLK_CTRL_OFFSET 0x00000110
-#define WLAN_CORE_CLK_CTRL_DIV_MSB 2
-#define WLAN_CORE_CLK_CTRL_DIV_LSB 0
-#define WLAN_CORE_CLK_CTRL_DIV_MASK 0x00000007
-#define WLAN_CORE_CLK_CTRL_DIV_GET(x) (((x) & WLAN_CORE_CLK_CTRL_DIV_MASK) >> WLAN_CORE_CLK_CTRL_DIV_LSB)
-#define WLAN_CORE_CLK_CTRL_DIV_SET(x) (((x) << WLAN_CORE_CLK_CTRL_DIV_LSB) & WLAN_CORE_CLK_CTRL_DIV_MASK)
-
-#define WLAN_GPIO_WAKEUP_CONTROL_ADDRESS 0x00000114
-#define WLAN_GPIO_WAKEUP_CONTROL_OFFSET 0x00000114
-#define WLAN_GPIO_WAKEUP_CONTROL_ENABLE_MSB 0
-#define WLAN_GPIO_WAKEUP_CONTROL_ENABLE_LSB 0
-#define WLAN_GPIO_WAKEUP_CONTROL_ENABLE_MASK 0x00000001
-#define WLAN_GPIO_WAKEUP_CONTROL_ENABLE_GET(x) (((x) & WLAN_GPIO_WAKEUP_CONTROL_ENABLE_MASK) >> WLAN_GPIO_WAKEUP_CONTROL_ENABLE_LSB)
-#define WLAN_GPIO_WAKEUP_CONTROL_ENABLE_SET(x) (((x) << WLAN_GPIO_WAKEUP_CONTROL_ENABLE_LSB) & WLAN_GPIO_WAKEUP_CONTROL_ENABLE_MASK)
-
-#define HT_ADDRESS 0x00000118
-#define HT_OFFSET 0x00000118
-#define HT_MODE_MSB 0
-#define HT_MODE_LSB 0
-#define HT_MODE_MASK 0x00000001
-#define HT_MODE_GET(x) (((x) & HT_MODE_MASK) >> HT_MODE_LSB)
-#define HT_MODE_SET(x) (((x) << HT_MODE_LSB) & HT_MODE_MASK)
-
-#define MAC_PCU_TSF_L32_ADDRESS 0x0000011c
-#define MAC_PCU_TSF_L32_OFFSET 0x0000011c
-#define MAC_PCU_TSF_L32_VALUE_MSB 31
-#define MAC_PCU_TSF_L32_VALUE_LSB 0
-#define MAC_PCU_TSF_L32_VALUE_MASK 0xffffffff
-#define MAC_PCU_TSF_L32_VALUE_GET(x) (((x) & MAC_PCU_TSF_L32_VALUE_MASK) >> MAC_PCU_TSF_L32_VALUE_LSB)
-#define MAC_PCU_TSF_L32_VALUE_SET(x) (((x) << MAC_PCU_TSF_L32_VALUE_LSB) & MAC_PCU_TSF_L32_VALUE_MASK)
-
-#define MAC_PCU_TSF_U32_ADDRESS 0x00000120
-#define MAC_PCU_TSF_U32_OFFSET 0x00000120
-#define MAC_PCU_TSF_U32_VALUE_MSB 31
-#define MAC_PCU_TSF_U32_VALUE_LSB 0
-#define MAC_PCU_TSF_U32_VALUE_MASK 0xffffffff
-#define MAC_PCU_TSF_U32_VALUE_GET(x) (((x) & MAC_PCU_TSF_U32_VALUE_MASK) >> MAC_PCU_TSF_U32_VALUE_LSB)
-#define MAC_PCU_TSF_U32_VALUE_SET(x) (((x) << MAC_PCU_TSF_U32_VALUE_LSB) & MAC_PCU_TSF_U32_VALUE_MASK)
-
-#define MAC_PCU_WBTIMER_ADDRESS 0x00000124
-#define MAC_PCU_WBTIMER_OFFSET 0x00000124
-#define MAC_PCU_WBTIMER_VALUE_MSB 31
-#define MAC_PCU_WBTIMER_VALUE_LSB 0
-#define MAC_PCU_WBTIMER_VALUE_MASK 0xffffffff
-#define MAC_PCU_WBTIMER_VALUE_GET(x) (((x) & MAC_PCU_WBTIMER_VALUE_MASK) >> MAC_PCU_WBTIMER_VALUE_LSB)
-#define MAC_PCU_WBTIMER_VALUE_SET(x) (((x) << MAC_PCU_WBTIMER_VALUE_LSB) & MAC_PCU_WBTIMER_VALUE_MASK)
-
-#define MAC_PCU_GENERIC_TIMERS_ADDRESS 0x00000140
-#define MAC_PCU_GENERIC_TIMERS_OFFSET 0x00000140
-#define MAC_PCU_GENERIC_TIMERS_DATA_MSB 31
-#define MAC_PCU_GENERIC_TIMERS_DATA_LSB 0
-#define MAC_PCU_GENERIC_TIMERS_DATA_MASK 0xffffffff
-#define MAC_PCU_GENERIC_TIMERS_DATA_GET(x) (((x) & MAC_PCU_GENERIC_TIMERS_DATA_MASK) >> MAC_PCU_GENERIC_TIMERS_DATA_LSB)
-#define MAC_PCU_GENERIC_TIMERS_DATA_SET(x) (((x) << MAC_PCU_GENERIC_TIMERS_DATA_LSB) & MAC_PCU_GENERIC_TIMERS_DATA_MASK)
-
-#define MAC_PCU_GENERIC_TIMERS_MODE_ADDRESS 0x00000180
-#define MAC_PCU_GENERIC_TIMERS_MODE_OFFSET 0x00000180
-#define MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_MSB 15
-#define MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_LSB 0
-#define MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_MASK 0x0000ffff
-#define MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_GET(x) (((x) & MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_MASK) >> MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_LSB)
-#define MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_SET(x) (((x) << MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_LSB) & MAC_PCU_GENERIC_TIMERS_MODE_ENABLE_MASK)
-
-#define MAC_PCU_GENERIC_TIMERS2_ADDRESS 0x000001c0
-#define MAC_PCU_GENERIC_TIMERS2_OFFSET 0x000001c0
-#define MAC_PCU_GENERIC_TIMERS2_DATA_MSB 31
-#define MAC_PCU_GENERIC_TIMERS2_DATA_LSB 0
-#define MAC_PCU_GENERIC_TIMERS2_DATA_MASK 0xffffffff
-#define MAC_PCU_GENERIC_TIMERS2_DATA_GET(x) (((x) & MAC_PCU_GENERIC_TIMERS2_DATA_MASK) >> MAC_PCU_GENERIC_TIMERS2_DATA_LSB)
-#define MAC_PCU_GENERIC_TIMERS2_DATA_SET(x) (((x) << MAC_PCU_GENERIC_TIMERS2_DATA_LSB) & MAC_PCU_GENERIC_TIMERS2_DATA_MASK)
-
-#define MAC_PCU_GENERIC_TIMERS_MODE2_ADDRESS 0x00000200
-#define MAC_PCU_GENERIC_TIMERS_MODE2_OFFSET 0x00000200
-#define MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_MSB 15
-#define MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_LSB 0
-#define MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_MASK 0x0000ffff
-#define MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_GET(x) (((x) & MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_MASK) >> MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_LSB)
-#define MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_SET(x) (((x) << MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_LSB) & MAC_PCU_GENERIC_TIMERS_MODE2_ENABLE_MASK)
-
-#define MAC_PCU_SLP1_ADDRESS 0x00000204
-#define MAC_PCU_SLP1_OFFSET 0x00000204
-#define MAC_PCU_SLP1_ASSUME_DTIM_MSB 19
-#define MAC_PCU_SLP1_ASSUME_DTIM_LSB 19
-#define MAC_PCU_SLP1_ASSUME_DTIM_MASK 0x00080000
-#define MAC_PCU_SLP1_ASSUME_DTIM_GET(x) (((x) & MAC_PCU_SLP1_ASSUME_DTIM_MASK) >> MAC_PCU_SLP1_ASSUME_DTIM_LSB)
-#define MAC_PCU_SLP1_ASSUME_DTIM_SET(x) (((x) << MAC_PCU_SLP1_ASSUME_DTIM_LSB) & MAC_PCU_SLP1_ASSUME_DTIM_MASK)
-#define MAC_PCU_SLP1_CAB_TIMEOUT_MSB 15
-#define MAC_PCU_SLP1_CAB_TIMEOUT_LSB 0
-#define MAC_PCU_SLP1_CAB_TIMEOUT_MASK 0x0000ffff
-#define MAC_PCU_SLP1_CAB_TIMEOUT_GET(x) (((x) & MAC_PCU_SLP1_CAB_TIMEOUT_MASK) >> MAC_PCU_SLP1_CAB_TIMEOUT_LSB)
-#define MAC_PCU_SLP1_CAB_TIMEOUT_SET(x) (((x) << MAC_PCU_SLP1_CAB_TIMEOUT_LSB) & MAC_PCU_SLP1_CAB_TIMEOUT_MASK)
-
-#define MAC_PCU_SLP2_ADDRESS 0x00000208
-#define MAC_PCU_SLP2_OFFSET 0x00000208
-#define MAC_PCU_SLP2_BEACON_TIMEOUT_MSB 15
-#define MAC_PCU_SLP2_BEACON_TIMEOUT_LSB 0
-#define MAC_PCU_SLP2_BEACON_TIMEOUT_MASK 0x0000ffff
-#define MAC_PCU_SLP2_BEACON_TIMEOUT_GET(x) (((x) & MAC_PCU_SLP2_BEACON_TIMEOUT_MASK) >> MAC_PCU_SLP2_BEACON_TIMEOUT_LSB)
-#define MAC_PCU_SLP2_BEACON_TIMEOUT_SET(x) (((x) << MAC_PCU_SLP2_BEACON_TIMEOUT_LSB) & MAC_PCU_SLP2_BEACON_TIMEOUT_MASK)
-
-#define MAC_PCU_RESET_TSF_ADDRESS 0x0000020c
-#define MAC_PCU_RESET_TSF_OFFSET 0x0000020c
-#define MAC_PCU_RESET_TSF_ONE_SHOT2_MSB 25
-#define MAC_PCU_RESET_TSF_ONE_SHOT2_LSB 25
-#define MAC_PCU_RESET_TSF_ONE_SHOT2_MASK 0x02000000
-#define MAC_PCU_RESET_TSF_ONE_SHOT2_GET(x) (((x) & MAC_PCU_RESET_TSF_ONE_SHOT2_MASK) >> MAC_PCU_RESET_TSF_ONE_SHOT2_LSB)
-#define MAC_PCU_RESET_TSF_ONE_SHOT2_SET(x) (((x) << MAC_PCU_RESET_TSF_ONE_SHOT2_LSB) & MAC_PCU_RESET_TSF_ONE_SHOT2_MASK)
-#define MAC_PCU_RESET_TSF_ONE_SHOT_MSB 24
-#define MAC_PCU_RESET_TSF_ONE_SHOT_LSB 24
-#define MAC_PCU_RESET_TSF_ONE_SHOT_MASK 0x01000000
-#define MAC_PCU_RESET_TSF_ONE_SHOT_GET(x) (((x) & MAC_PCU_RESET_TSF_ONE_SHOT_MASK) >> MAC_PCU_RESET_TSF_ONE_SHOT_LSB)
-#define MAC_PCU_RESET_TSF_ONE_SHOT_SET(x) (((x) << MAC_PCU_RESET_TSF_ONE_SHOT_LSB) & MAC_PCU_RESET_TSF_ONE_SHOT_MASK)
-
-#define MAC_PCU_TSF_ADD_PLL_ADDRESS 0x00000210
-#define MAC_PCU_TSF_ADD_PLL_OFFSET 0x00000210
-#define MAC_PCU_TSF_ADD_PLL_VALUE_MSB 7
-#define MAC_PCU_TSF_ADD_PLL_VALUE_LSB 0
-#define MAC_PCU_TSF_ADD_PLL_VALUE_MASK 0x000000ff
-#define MAC_PCU_TSF_ADD_PLL_VALUE_GET(x) (((x) & MAC_PCU_TSF_ADD_PLL_VALUE_MASK) >> MAC_PCU_TSF_ADD_PLL_VALUE_LSB)
-#define MAC_PCU_TSF_ADD_PLL_VALUE_SET(x) (((x) << MAC_PCU_TSF_ADD_PLL_VALUE_LSB) & MAC_PCU_TSF_ADD_PLL_VALUE_MASK)
-
-#define SLEEP_RETENTION_ADDRESS 0x00000214
-#define SLEEP_RETENTION_OFFSET 0x00000214
-#define SLEEP_RETENTION_TIME_MSB 9
-#define SLEEP_RETENTION_TIME_LSB 2
-#define SLEEP_RETENTION_TIME_MASK 0x000003fc
-#define SLEEP_RETENTION_TIME_GET(x) (((x) & SLEEP_RETENTION_TIME_MASK) >> SLEEP_RETENTION_TIME_LSB)
-#define SLEEP_RETENTION_TIME_SET(x) (((x) << SLEEP_RETENTION_TIME_LSB) & SLEEP_RETENTION_TIME_MASK)
-#define SLEEP_RETENTION_MODE_MSB 1
-#define SLEEP_RETENTION_MODE_LSB 1
-#define SLEEP_RETENTION_MODE_MASK 0x00000002
-#define SLEEP_RETENTION_MODE_GET(x) (((x) & SLEEP_RETENTION_MODE_MASK) >> SLEEP_RETENTION_MODE_LSB)
-#define SLEEP_RETENTION_MODE_SET(x) (((x) << SLEEP_RETENTION_MODE_LSB) & SLEEP_RETENTION_MODE_MASK)
-#define SLEEP_RETENTION_ENABLE_MSB 0
-#define SLEEP_RETENTION_ENABLE_LSB 0
-#define SLEEP_RETENTION_ENABLE_MASK 0x00000001
-#define SLEEP_RETENTION_ENABLE_GET(x) (((x) & SLEEP_RETENTION_ENABLE_MASK) >> SLEEP_RETENTION_ENABLE_LSB)
-#define SLEEP_RETENTION_ENABLE_SET(x) (((x) << SLEEP_RETENTION_ENABLE_LSB) & SLEEP_RETENTION_ENABLE_MASK)
-
-#define BTCOEXCTRL_ADDRESS 0x00000218
-#define BTCOEXCTRL_OFFSET 0x00000218
-#define BTCOEXCTRL_WBTIMER_ENABLE_MSB 26
-#define BTCOEXCTRL_WBTIMER_ENABLE_LSB 26
-#define BTCOEXCTRL_WBTIMER_ENABLE_MASK 0x04000000
-#define BTCOEXCTRL_WBTIMER_ENABLE_GET(x) (((x) & BTCOEXCTRL_WBTIMER_ENABLE_MASK) >> BTCOEXCTRL_WBTIMER_ENABLE_LSB)
-#define BTCOEXCTRL_WBTIMER_ENABLE_SET(x) (((x) << BTCOEXCTRL_WBTIMER_ENABLE_LSB) & BTCOEXCTRL_WBTIMER_ENABLE_MASK)
-#define BTCOEXCTRL_WBSYNC_ON_BEACON_MSB 25
-#define BTCOEXCTRL_WBSYNC_ON_BEACON_LSB 25
-#define BTCOEXCTRL_WBSYNC_ON_BEACON_MASK 0x02000000
-#define BTCOEXCTRL_WBSYNC_ON_BEACON_GET(x) (((x) & BTCOEXCTRL_WBSYNC_ON_BEACON_MASK) >> BTCOEXCTRL_WBSYNC_ON_BEACON_LSB)
-#define BTCOEXCTRL_WBSYNC_ON_BEACON_SET(x) (((x) << BTCOEXCTRL_WBSYNC_ON_BEACON_LSB) & BTCOEXCTRL_WBSYNC_ON_BEACON_MASK)
-#define BTCOEXCTRL_PTA_MODE_MSB 24
-#define BTCOEXCTRL_PTA_MODE_LSB 23
-#define BTCOEXCTRL_PTA_MODE_MASK 0x01800000
-#define BTCOEXCTRL_PTA_MODE_GET(x) (((x) & BTCOEXCTRL_PTA_MODE_MASK) >> BTCOEXCTRL_PTA_MODE_LSB)
-#define BTCOEXCTRL_PTA_MODE_SET(x) (((x) << BTCOEXCTRL_PTA_MODE_LSB) & BTCOEXCTRL_PTA_MODE_MASK)
-#define BTCOEXCTRL_FREQ_TIME_MSB 22
-#define BTCOEXCTRL_FREQ_TIME_LSB 18
-#define BTCOEXCTRL_FREQ_TIME_MASK 0x007c0000
-#define BTCOEXCTRL_FREQ_TIME_GET(x) (((x) & BTCOEXCTRL_FREQ_TIME_MASK) >> BTCOEXCTRL_FREQ_TIME_LSB)
-#define BTCOEXCTRL_FREQ_TIME_SET(x) (((x) << BTCOEXCTRL_FREQ_TIME_LSB) & BTCOEXCTRL_FREQ_TIME_MASK)
-#define BTCOEXCTRL_PRIORITY_TIME_MSB 17
-#define BTCOEXCTRL_PRIORITY_TIME_LSB 12
-#define BTCOEXCTRL_PRIORITY_TIME_MASK 0x0003f000
-#define BTCOEXCTRL_PRIORITY_TIME_GET(x) (((x) & BTCOEXCTRL_PRIORITY_TIME_MASK) >> BTCOEXCTRL_PRIORITY_TIME_LSB)
-#define BTCOEXCTRL_PRIORITY_TIME_SET(x) (((x) << BTCOEXCTRL_PRIORITY_TIME_LSB) & BTCOEXCTRL_PRIORITY_TIME_MASK)
-#define BTCOEXCTRL_SYNC_DET_EN_MSB 11
-#define BTCOEXCTRL_SYNC_DET_EN_LSB 11
-#define BTCOEXCTRL_SYNC_DET_EN_MASK 0x00000800
-#define BTCOEXCTRL_SYNC_DET_EN_GET(x) (((x) & BTCOEXCTRL_SYNC_DET_EN_MASK) >> BTCOEXCTRL_SYNC_DET_EN_LSB)
-#define BTCOEXCTRL_SYNC_DET_EN_SET(x) (((x) << BTCOEXCTRL_SYNC_DET_EN_LSB) & BTCOEXCTRL_SYNC_DET_EN_MASK)
-#define BTCOEXCTRL_IDLE_CNT_EN_MSB 10
-#define BTCOEXCTRL_IDLE_CNT_EN_LSB 10
-#define BTCOEXCTRL_IDLE_CNT_EN_MASK 0x00000400
-#define BTCOEXCTRL_IDLE_CNT_EN_GET(x) (((x) & BTCOEXCTRL_IDLE_CNT_EN_MASK) >> BTCOEXCTRL_IDLE_CNT_EN_LSB)
-#define BTCOEXCTRL_IDLE_CNT_EN_SET(x) (((x) << BTCOEXCTRL_IDLE_CNT_EN_LSB) & BTCOEXCTRL_IDLE_CNT_EN_MASK)
-#define BTCOEXCTRL_FRAME_CNT_EN_MSB 9
-#define BTCOEXCTRL_FRAME_CNT_EN_LSB 9
-#define BTCOEXCTRL_FRAME_CNT_EN_MASK 0x00000200
-#define BTCOEXCTRL_FRAME_CNT_EN_GET(x) (((x) & BTCOEXCTRL_FRAME_CNT_EN_MASK) >> BTCOEXCTRL_FRAME_CNT_EN_LSB)
-#define BTCOEXCTRL_FRAME_CNT_EN_SET(x) (((x) << BTCOEXCTRL_FRAME_CNT_EN_LSB) & BTCOEXCTRL_FRAME_CNT_EN_MASK)
-#define BTCOEXCTRL_CLK_CNT_EN_MSB 8
-#define BTCOEXCTRL_CLK_CNT_EN_LSB 8
-#define BTCOEXCTRL_CLK_CNT_EN_MASK 0x00000100
-#define BTCOEXCTRL_CLK_CNT_EN_GET(x) (((x) & BTCOEXCTRL_CLK_CNT_EN_MASK) >> BTCOEXCTRL_CLK_CNT_EN_LSB)
-#define BTCOEXCTRL_CLK_CNT_EN_SET(x) (((x) << BTCOEXCTRL_CLK_CNT_EN_LSB) & BTCOEXCTRL_CLK_CNT_EN_MASK)
-#define BTCOEXCTRL_GAP_MSB 7
-#define BTCOEXCTRL_GAP_LSB 0
-#define BTCOEXCTRL_GAP_MASK 0x000000ff
-#define BTCOEXCTRL_GAP_GET(x) (((x) & BTCOEXCTRL_GAP_MASK) >> BTCOEXCTRL_GAP_LSB)
-#define BTCOEXCTRL_GAP_SET(x) (((x) << BTCOEXCTRL_GAP_LSB) & BTCOEXCTRL_GAP_MASK)
-
-#define WBSYNC_PRIORITY1_ADDRESS 0x0000021c
-#define WBSYNC_PRIORITY1_OFFSET 0x0000021c
-#define WBSYNC_PRIORITY1_BITMAP_MSB 31
-#define WBSYNC_PRIORITY1_BITMAP_LSB 0
-#define WBSYNC_PRIORITY1_BITMAP_MASK 0xffffffff
-#define WBSYNC_PRIORITY1_BITMAP_GET(x) (((x) & WBSYNC_PRIORITY1_BITMAP_MASK) >> WBSYNC_PRIORITY1_BITMAP_LSB)
-#define WBSYNC_PRIORITY1_BITMAP_SET(x) (((x) << WBSYNC_PRIORITY1_BITMAP_LSB) & WBSYNC_PRIORITY1_BITMAP_MASK)
-
-#define WBSYNC_PRIORITY2_ADDRESS 0x00000220
-#define WBSYNC_PRIORITY2_OFFSET 0x00000220
-#define WBSYNC_PRIORITY2_BITMAP_MSB 31
-#define WBSYNC_PRIORITY2_BITMAP_LSB 0
-#define WBSYNC_PRIORITY2_BITMAP_MASK 0xffffffff
-#define WBSYNC_PRIORITY2_BITMAP_GET(x) (((x) & WBSYNC_PRIORITY2_BITMAP_MASK) >> WBSYNC_PRIORITY2_BITMAP_LSB)
-#define WBSYNC_PRIORITY2_BITMAP_SET(x) (((x) << WBSYNC_PRIORITY2_BITMAP_LSB) & WBSYNC_PRIORITY2_BITMAP_MASK)
-
-#define WBSYNC_PRIORITY3_ADDRESS 0x00000224
-#define WBSYNC_PRIORITY3_OFFSET 0x00000224
-#define WBSYNC_PRIORITY3_BITMAP_MSB 31
-#define WBSYNC_PRIORITY3_BITMAP_LSB 0
-#define WBSYNC_PRIORITY3_BITMAP_MASK 0xffffffff
-#define WBSYNC_PRIORITY3_BITMAP_GET(x) (((x) & WBSYNC_PRIORITY3_BITMAP_MASK) >> WBSYNC_PRIORITY3_BITMAP_LSB)
-#define WBSYNC_PRIORITY3_BITMAP_SET(x) (((x) << WBSYNC_PRIORITY3_BITMAP_LSB) & WBSYNC_PRIORITY3_BITMAP_MASK)
-
-#define BTCOEX0_ADDRESS 0x00000228
-#define BTCOEX0_OFFSET 0x00000228
-#define BTCOEX0_SYNC_DUR_MSB 7
-#define BTCOEX0_SYNC_DUR_LSB 0
-#define BTCOEX0_SYNC_DUR_MASK 0x000000ff
-#define BTCOEX0_SYNC_DUR_GET(x) (((x) & BTCOEX0_SYNC_DUR_MASK) >> BTCOEX0_SYNC_DUR_LSB)
-#define BTCOEX0_SYNC_DUR_SET(x) (((x) << BTCOEX0_SYNC_DUR_LSB) & BTCOEX0_SYNC_DUR_MASK)
-
-#define BTCOEX1_ADDRESS 0x0000022c
-#define BTCOEX1_OFFSET 0x0000022c
-#define BTCOEX1_CLK_THRES_MSB 20
-#define BTCOEX1_CLK_THRES_LSB 0
-#define BTCOEX1_CLK_THRES_MASK 0x001fffff
-#define BTCOEX1_CLK_THRES_GET(x) (((x) & BTCOEX1_CLK_THRES_MASK) >> BTCOEX1_CLK_THRES_LSB)
-#define BTCOEX1_CLK_THRES_SET(x) (((x) << BTCOEX1_CLK_THRES_LSB) & BTCOEX1_CLK_THRES_MASK)
-
-#define BTCOEX2_ADDRESS 0x00000230
-#define BTCOEX2_OFFSET 0x00000230
-#define BTCOEX2_FRAME_THRES_MSB 7
-#define BTCOEX2_FRAME_THRES_LSB 0
-#define BTCOEX2_FRAME_THRES_MASK 0x000000ff
-#define BTCOEX2_FRAME_THRES_GET(x) (((x) & BTCOEX2_FRAME_THRES_MASK) >> BTCOEX2_FRAME_THRES_LSB)
-#define BTCOEX2_FRAME_THRES_SET(x) (((x) << BTCOEX2_FRAME_THRES_LSB) & BTCOEX2_FRAME_THRES_MASK)
-
-#define BTCOEX3_ADDRESS 0x00000234
-#define BTCOEX3_OFFSET 0x00000234
-#define BTCOEX3_CLK_CNT_MSB 20
-#define BTCOEX3_CLK_CNT_LSB 0
-#define BTCOEX3_CLK_CNT_MASK 0x001fffff
-#define BTCOEX3_CLK_CNT_GET(x) (((x) & BTCOEX3_CLK_CNT_MASK) >> BTCOEX3_CLK_CNT_LSB)
-#define BTCOEX3_CLK_CNT_SET(x) (((x) << BTCOEX3_CLK_CNT_LSB) & BTCOEX3_CLK_CNT_MASK)
-
-#define BTCOEX4_ADDRESS 0x00000238
-#define BTCOEX4_OFFSET 0x00000238
-#define BTCOEX4_FRAME_CNT_MSB 7
-#define BTCOEX4_FRAME_CNT_LSB 0
-#define BTCOEX4_FRAME_CNT_MASK 0x000000ff
-#define BTCOEX4_FRAME_CNT_GET(x) (((x) & BTCOEX4_FRAME_CNT_MASK) >> BTCOEX4_FRAME_CNT_LSB)
-#define BTCOEX4_FRAME_CNT_SET(x) (((x) << BTCOEX4_FRAME_CNT_LSB) & BTCOEX4_FRAME_CNT_MASK)
-
-#define BTCOEX5_ADDRESS 0x0000023c
-#define BTCOEX5_OFFSET 0x0000023c
-#define BTCOEX5_IDLE_CNT_MSB 15
-#define BTCOEX5_IDLE_CNT_LSB 0
-#define BTCOEX5_IDLE_CNT_MASK 0x0000ffff
-#define BTCOEX5_IDLE_CNT_GET(x) (((x) & BTCOEX5_IDLE_CNT_MASK) >> BTCOEX5_IDLE_CNT_LSB)
-#define BTCOEX5_IDLE_CNT_SET(x) (((x) << BTCOEX5_IDLE_CNT_LSB) & BTCOEX5_IDLE_CNT_MASK)
-
-#define BTCOEX6_ADDRESS 0x00000240
-#define BTCOEX6_OFFSET 0x00000240
-#define BTCOEX6_IDLE_RESET_LVL_BITMAP_MSB 31
-#define BTCOEX6_IDLE_RESET_LVL_BITMAP_LSB 0
-#define BTCOEX6_IDLE_RESET_LVL_BITMAP_MASK 0xffffffff
-#define BTCOEX6_IDLE_RESET_LVL_BITMAP_GET(x) (((x) & BTCOEX6_IDLE_RESET_LVL_BITMAP_MASK) >> BTCOEX6_IDLE_RESET_LVL_BITMAP_LSB)
-#define BTCOEX6_IDLE_RESET_LVL_BITMAP_SET(x) (((x) << BTCOEX6_IDLE_RESET_LVL_BITMAP_LSB) & BTCOEX6_IDLE_RESET_LVL_BITMAP_MASK)
-
-#define LOCK_ADDRESS 0x00000244
-#define LOCK_OFFSET 0x00000244
-#define LOCK_TLOCK_SLAVE_MSB 31
-#define LOCK_TLOCK_SLAVE_LSB 24
-#define LOCK_TLOCK_SLAVE_MASK 0xff000000
-#define LOCK_TLOCK_SLAVE_GET(x) (((x) & LOCK_TLOCK_SLAVE_MASK) >> LOCK_TLOCK_SLAVE_LSB)
-#define LOCK_TLOCK_SLAVE_SET(x) (((x) << LOCK_TLOCK_SLAVE_LSB) & LOCK_TLOCK_SLAVE_MASK)
-#define LOCK_TUNLOCK_SLAVE_MSB 23
-#define LOCK_TUNLOCK_SLAVE_LSB 16
-#define LOCK_TUNLOCK_SLAVE_MASK 0x00ff0000
-#define LOCK_TUNLOCK_SLAVE_GET(x) (((x) & LOCK_TUNLOCK_SLAVE_MASK) >> LOCK_TUNLOCK_SLAVE_LSB)
-#define LOCK_TUNLOCK_SLAVE_SET(x) (((x) << LOCK_TUNLOCK_SLAVE_LSB) & LOCK_TUNLOCK_SLAVE_MASK)
-#define LOCK_TLOCK_MASTER_MSB 15
-#define LOCK_TLOCK_MASTER_LSB 8
-#define LOCK_TLOCK_MASTER_MASK 0x0000ff00
-#define LOCK_TLOCK_MASTER_GET(x) (((x) & LOCK_TLOCK_MASTER_MASK) >> LOCK_TLOCK_MASTER_LSB)
-#define LOCK_TLOCK_MASTER_SET(x) (((x) << LOCK_TLOCK_MASTER_LSB) & LOCK_TLOCK_MASTER_MASK)
-#define LOCK_TUNLOCK_MASTER_MSB 7
-#define LOCK_TUNLOCK_MASTER_LSB 0
-#define LOCK_TUNLOCK_MASTER_MASK 0x000000ff
-#define LOCK_TUNLOCK_MASTER_GET(x) (((x) & LOCK_TUNLOCK_MASTER_MASK) >> LOCK_TUNLOCK_MASTER_LSB)
-#define LOCK_TUNLOCK_MASTER_SET(x) (((x) << LOCK_TUNLOCK_MASTER_LSB) & LOCK_TUNLOCK_MASTER_MASK)
-
-#define NOLOCK_PRIORITY_ADDRESS 0x00000248
-#define NOLOCK_PRIORITY_OFFSET 0x00000248
-#define NOLOCK_PRIORITY_BITMAP_MSB 31
-#define NOLOCK_PRIORITY_BITMAP_LSB 0
-#define NOLOCK_PRIORITY_BITMAP_MASK 0xffffffff
-#define NOLOCK_PRIORITY_BITMAP_GET(x) (((x) & NOLOCK_PRIORITY_BITMAP_MASK) >> NOLOCK_PRIORITY_BITMAP_LSB)
-#define NOLOCK_PRIORITY_BITMAP_SET(x) (((x) << NOLOCK_PRIORITY_BITMAP_LSB) & NOLOCK_PRIORITY_BITMAP_MASK)
-
-#define WBSYNC_ADDRESS 0x0000024c
-#define WBSYNC_OFFSET 0x0000024c
-#define WBSYNC_BTCLOCK_MSB 31
-#define WBSYNC_BTCLOCK_LSB 0
-#define WBSYNC_BTCLOCK_MASK 0xffffffff
-#define WBSYNC_BTCLOCK_GET(x) (((x) & WBSYNC_BTCLOCK_MASK) >> WBSYNC_BTCLOCK_LSB)
-#define WBSYNC_BTCLOCK_SET(x) (((x) << WBSYNC_BTCLOCK_LSB) & WBSYNC_BTCLOCK_MASK)
-
-#define WBSYNC1_ADDRESS 0x00000250
-#define WBSYNC1_OFFSET 0x00000250
-#define WBSYNC1_BTCLOCK_MSB 31
-#define WBSYNC1_BTCLOCK_LSB 0
-#define WBSYNC1_BTCLOCK_MASK 0xffffffff
-#define WBSYNC1_BTCLOCK_GET(x) (((x) & WBSYNC1_BTCLOCK_MASK) >> WBSYNC1_BTCLOCK_LSB)
-#define WBSYNC1_BTCLOCK_SET(x) (((x) << WBSYNC1_BTCLOCK_LSB) & WBSYNC1_BTCLOCK_MASK)
-
-#define WBSYNC2_ADDRESS 0x00000254
-#define WBSYNC2_OFFSET 0x00000254
-#define WBSYNC2_BTCLOCK_MSB 31
-#define WBSYNC2_BTCLOCK_LSB 0
-#define WBSYNC2_BTCLOCK_MASK 0xffffffff
-#define WBSYNC2_BTCLOCK_GET(x) (((x) & WBSYNC2_BTCLOCK_MASK) >> WBSYNC2_BTCLOCK_LSB)
-#define WBSYNC2_BTCLOCK_SET(x) (((x) << WBSYNC2_BTCLOCK_LSB) & WBSYNC2_BTCLOCK_MASK)
-
-#define WBSYNC3_ADDRESS 0x00000258
-#define WBSYNC3_OFFSET 0x00000258
-#define WBSYNC3_BTCLOCK_MSB 31
-#define WBSYNC3_BTCLOCK_LSB 0
-#define WBSYNC3_BTCLOCK_MASK 0xffffffff
-#define WBSYNC3_BTCLOCK_GET(x) (((x) & WBSYNC3_BTCLOCK_MASK) >> WBSYNC3_BTCLOCK_LSB)
-#define WBSYNC3_BTCLOCK_SET(x) (((x) << WBSYNC3_BTCLOCK_LSB) & WBSYNC3_BTCLOCK_MASK)
-
-#define WB_TIMER_TARGET_ADDRESS 0x0000025c
-#define WB_TIMER_TARGET_OFFSET 0x0000025c
-#define WB_TIMER_TARGET_VALUE_MSB 31
-#define WB_TIMER_TARGET_VALUE_LSB 0
-#define WB_TIMER_TARGET_VALUE_MASK 0xffffffff
-#define WB_TIMER_TARGET_VALUE_GET(x) (((x) & WB_TIMER_TARGET_VALUE_MASK) >> WB_TIMER_TARGET_VALUE_LSB)
-#define WB_TIMER_TARGET_VALUE_SET(x) (((x) << WB_TIMER_TARGET_VALUE_LSB) & WB_TIMER_TARGET_VALUE_MASK)
-
-#define WB_TIMER_SLOP_ADDRESS 0x00000260
-#define WB_TIMER_SLOP_OFFSET 0x00000260
-#define WB_TIMER_SLOP_VALUE_MSB 9
-#define WB_TIMER_SLOP_VALUE_LSB 0
-#define WB_TIMER_SLOP_VALUE_MASK 0x000003ff
-#define WB_TIMER_SLOP_VALUE_GET(x) (((x) & WB_TIMER_SLOP_VALUE_MASK) >> WB_TIMER_SLOP_VALUE_LSB)
-#define WB_TIMER_SLOP_VALUE_SET(x) (((x) << WB_TIMER_SLOP_VALUE_LSB) & WB_TIMER_SLOP_VALUE_MASK)
-
-#define BTCOEX_INT_EN_ADDRESS 0x00000264
-#define BTCOEX_INT_EN_OFFSET 0x00000264
-#define BTCOEX_INT_EN_I2C_RECV_OVERFLOW_MSB 11
-#define BTCOEX_INT_EN_I2C_RECV_OVERFLOW_LSB 11
-#define BTCOEX_INT_EN_I2C_RECV_OVERFLOW_MASK 0x00000800
-#define BTCOEX_INT_EN_I2C_RECV_OVERFLOW_GET(x) (((x) & BTCOEX_INT_EN_I2C_RECV_OVERFLOW_MASK) >> BTCOEX_INT_EN_I2C_RECV_OVERFLOW_LSB)
-#define BTCOEX_INT_EN_I2C_RECV_OVERFLOW_SET(x) (((x) << BTCOEX_INT_EN_I2C_RECV_OVERFLOW_LSB) & BTCOEX_INT_EN_I2C_RECV_OVERFLOW_MASK)
-#define BTCOEX_INT_EN_I2C_TX_FAILED_MSB 10
-#define BTCOEX_INT_EN_I2C_TX_FAILED_LSB 10
-#define BTCOEX_INT_EN_I2C_TX_FAILED_MASK 0x00000400
-#define BTCOEX_INT_EN_I2C_TX_FAILED_GET(x) (((x) & BTCOEX_INT_EN_I2C_TX_FAILED_MASK) >> BTCOEX_INT_EN_I2C_TX_FAILED_LSB)
-#define BTCOEX_INT_EN_I2C_TX_FAILED_SET(x) (((x) << BTCOEX_INT_EN_I2C_TX_FAILED_LSB) & BTCOEX_INT_EN_I2C_TX_FAILED_MASK)
-#define BTCOEX_INT_EN_I2C_MESG_SENT_MSB 9
-#define BTCOEX_INT_EN_I2C_MESG_SENT_LSB 9
-#define BTCOEX_INT_EN_I2C_MESG_SENT_MASK 0x00000200
-#define BTCOEX_INT_EN_I2C_MESG_SENT_GET(x) (((x) & BTCOEX_INT_EN_I2C_MESG_SENT_MASK) >> BTCOEX_INT_EN_I2C_MESG_SENT_LSB)
-#define BTCOEX_INT_EN_I2C_MESG_SENT_SET(x) (((x) << BTCOEX_INT_EN_I2C_MESG_SENT_LSB) & BTCOEX_INT_EN_I2C_MESG_SENT_MASK)
-#define BTCOEX_INT_EN_ST_MESG_RECV_MSB 8
-#define BTCOEX_INT_EN_ST_MESG_RECV_LSB 8
-#define BTCOEX_INT_EN_ST_MESG_RECV_MASK 0x00000100
-#define BTCOEX_INT_EN_ST_MESG_RECV_GET(x) (((x) & BTCOEX_INT_EN_ST_MESG_RECV_MASK) >> BTCOEX_INT_EN_ST_MESG_RECV_LSB)
-#define BTCOEX_INT_EN_ST_MESG_RECV_SET(x) (((x) << BTCOEX_INT_EN_ST_MESG_RECV_LSB) & BTCOEX_INT_EN_ST_MESG_RECV_MASK)
-#define BTCOEX_INT_EN_WB_TIMER_MSB 7
-#define BTCOEX_INT_EN_WB_TIMER_LSB 7
-#define BTCOEX_INT_EN_WB_TIMER_MASK 0x00000080
-#define BTCOEX_INT_EN_WB_TIMER_GET(x) (((x) & BTCOEX_INT_EN_WB_TIMER_MASK) >> BTCOEX_INT_EN_WB_TIMER_LSB)
-#define BTCOEX_INT_EN_WB_TIMER_SET(x) (((x) << BTCOEX_INT_EN_WB_TIMER_LSB) & BTCOEX_INT_EN_WB_TIMER_MASK)
-#define BTCOEX_INT_EN_NOSYNC_MSB 4
-#define BTCOEX_INT_EN_NOSYNC_LSB 4
-#define BTCOEX_INT_EN_NOSYNC_MASK 0x00000010
-#define BTCOEX_INT_EN_NOSYNC_GET(x) (((x) & BTCOEX_INT_EN_NOSYNC_MASK) >> BTCOEX_INT_EN_NOSYNC_LSB)
-#define BTCOEX_INT_EN_NOSYNC_SET(x) (((x) << BTCOEX_INT_EN_NOSYNC_LSB) & BTCOEX_INT_EN_NOSYNC_MASK)
-#define BTCOEX_INT_EN_SYNC_MSB 3
-#define BTCOEX_INT_EN_SYNC_LSB 3
-#define BTCOEX_INT_EN_SYNC_MASK 0x00000008
-#define BTCOEX_INT_EN_SYNC_GET(x) (((x) & BTCOEX_INT_EN_SYNC_MASK) >> BTCOEX_INT_EN_SYNC_LSB)
-#define BTCOEX_INT_EN_SYNC_SET(x) (((x) << BTCOEX_INT_EN_SYNC_LSB) & BTCOEX_INT_EN_SYNC_MASK)
-#define BTCOEX_INT_EN_END_MSB 2
-#define BTCOEX_INT_EN_END_LSB 2
-#define BTCOEX_INT_EN_END_MASK 0x00000004
-#define BTCOEX_INT_EN_END_GET(x) (((x) & BTCOEX_INT_EN_END_MASK) >> BTCOEX_INT_EN_END_LSB)
-#define BTCOEX_INT_EN_END_SET(x) (((x) << BTCOEX_INT_EN_END_LSB) & BTCOEX_INT_EN_END_MASK)
-#define BTCOEX_INT_EN_FRAME_CNT_MSB 1
-#define BTCOEX_INT_EN_FRAME_CNT_LSB 1
-#define BTCOEX_INT_EN_FRAME_CNT_MASK 0x00000002
-#define BTCOEX_INT_EN_FRAME_CNT_GET(x) (((x) & BTCOEX_INT_EN_FRAME_CNT_MASK) >> BTCOEX_INT_EN_FRAME_CNT_LSB)
-#define BTCOEX_INT_EN_FRAME_CNT_SET(x) (((x) << BTCOEX_INT_EN_FRAME_CNT_LSB) & BTCOEX_INT_EN_FRAME_CNT_MASK)
-#define BTCOEX_INT_EN_CLK_CNT_MSB 0
-#define BTCOEX_INT_EN_CLK_CNT_LSB 0
-#define BTCOEX_INT_EN_CLK_CNT_MASK 0x00000001
-#define BTCOEX_INT_EN_CLK_CNT_GET(x) (((x) & BTCOEX_INT_EN_CLK_CNT_MASK) >> BTCOEX_INT_EN_CLK_CNT_LSB)
-#define BTCOEX_INT_EN_CLK_CNT_SET(x) (((x) << BTCOEX_INT_EN_CLK_CNT_LSB) & BTCOEX_INT_EN_CLK_CNT_MASK)
-
-#define BTCOEX_INT_STAT_ADDRESS 0x00000268
-#define BTCOEX_INT_STAT_OFFSET 0x00000268
-#define BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_MSB 11
-#define BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_LSB 11
-#define BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_MASK 0x00000800
-#define BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_GET(x) (((x) & BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_MASK) >> BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_LSB)
-#define BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_SET(x) (((x) << BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_LSB) & BTCOEX_INT_STAT_I2C_RECV_OVERFLOW_MASK)
-#define BTCOEX_INT_STAT_I2C_TX_FAILED_MSB 10
-#define BTCOEX_INT_STAT_I2C_TX_FAILED_LSB 10
-#define BTCOEX_INT_STAT_I2C_TX_FAILED_MASK 0x00000400
-#define BTCOEX_INT_STAT_I2C_TX_FAILED_GET(x) (((x) & BTCOEX_INT_STAT_I2C_TX_FAILED_MASK) >> BTCOEX_INT_STAT_I2C_TX_FAILED_LSB)
-#define BTCOEX_INT_STAT_I2C_TX_FAILED_SET(x) (((x) << BTCOEX_INT_STAT_I2C_TX_FAILED_LSB) & BTCOEX_INT_STAT_I2C_TX_FAILED_MASK)
-#define BTCOEX_INT_STAT_I2C_MESG_SENT_MSB 9
-#define BTCOEX_INT_STAT_I2C_MESG_SENT_LSB 9
-#define BTCOEX_INT_STAT_I2C_MESG_SENT_MASK 0x00000200
-#define BTCOEX_INT_STAT_I2C_MESG_SENT_GET(x) (((x) & BTCOEX_INT_STAT_I2C_MESG_SENT_MASK) >> BTCOEX_INT_STAT_I2C_MESG_SENT_LSB)
-#define BTCOEX_INT_STAT_I2C_MESG_SENT_SET(x) (((x) << BTCOEX_INT_STAT_I2C_MESG_SENT_LSB) & BTCOEX_INT_STAT_I2C_MESG_SENT_MASK)
-#define BTCOEX_INT_STAT_I2C_MESG_RECV_MSB 8
-#define BTCOEX_INT_STAT_I2C_MESG_RECV_LSB 8
-#define BTCOEX_INT_STAT_I2C_MESG_RECV_MASK 0x00000100
-#define BTCOEX_INT_STAT_I2C_MESG_RECV_GET(x) (((x) & BTCOEX_INT_STAT_I2C_MESG_RECV_MASK) >> BTCOEX_INT_STAT_I2C_MESG_RECV_LSB)
-#define BTCOEX_INT_STAT_I2C_MESG_RECV_SET(x) (((x) << BTCOEX_INT_STAT_I2C_MESG_RECV_LSB) & BTCOEX_INT_STAT_I2C_MESG_RECV_MASK)
-#define BTCOEX_INT_STAT_WB_TIMER_MSB 7
-#define BTCOEX_INT_STAT_WB_TIMER_LSB 7
-#define BTCOEX_INT_STAT_WB_TIMER_MASK 0x00000080
-#define BTCOEX_INT_STAT_WB_TIMER_GET(x) (((x) & BTCOEX_INT_STAT_WB_TIMER_MASK) >> BTCOEX_INT_STAT_WB_TIMER_LSB)
-#define BTCOEX_INT_STAT_WB_TIMER_SET(x) (((x) << BTCOEX_INT_STAT_WB_TIMER_LSB) & BTCOEX_INT_STAT_WB_TIMER_MASK)
-#define BTCOEX_INT_STAT_BTPRIORITY_STOMP_MSB 6
-#define BTCOEX_INT_STAT_BTPRIORITY_STOMP_LSB 6
-#define BTCOEX_INT_STAT_BTPRIORITY_STOMP_MASK 0x00000040
-#define BTCOEX_INT_STAT_BTPRIORITY_STOMP_GET(x) (((x) & BTCOEX_INT_STAT_BTPRIORITY_STOMP_MASK) >> BTCOEX_INT_STAT_BTPRIORITY_STOMP_LSB)
-#define BTCOEX_INT_STAT_BTPRIORITY_STOMP_SET(x) (((x) << BTCOEX_INT_STAT_BTPRIORITY_STOMP_LSB) & BTCOEX_INT_STAT_BTPRIORITY_STOMP_MASK)
-#define BTCOEX_INT_STAT_BTPRIORITY_MSB 5
-#define BTCOEX_INT_STAT_BTPRIORITY_LSB 5
-#define BTCOEX_INT_STAT_BTPRIORITY_MASK 0x00000020
-#define BTCOEX_INT_STAT_BTPRIORITY_GET(x) (((x) & BTCOEX_INT_STAT_BTPRIORITY_MASK) >> BTCOEX_INT_STAT_BTPRIORITY_LSB)
-#define BTCOEX_INT_STAT_BTPRIORITY_SET(x) (((x) << BTCOEX_INT_STAT_BTPRIORITY_LSB) & BTCOEX_INT_STAT_BTPRIORITY_MASK)
-#define BTCOEX_INT_STAT_NOSYNC_MSB 4
-#define BTCOEX_INT_STAT_NOSYNC_LSB 4
-#define BTCOEX_INT_STAT_NOSYNC_MASK 0x00000010
-#define BTCOEX_INT_STAT_NOSYNC_GET(x) (((x) & BTCOEX_INT_STAT_NOSYNC_MASK) >> BTCOEX_INT_STAT_NOSYNC_LSB)
-#define BTCOEX_INT_STAT_NOSYNC_SET(x) (((x) << BTCOEX_INT_STAT_NOSYNC_LSB) & BTCOEX_INT_STAT_NOSYNC_MASK)
-#define BTCOEX_INT_STAT_SYNC_MSB 3
-#define BTCOEX_INT_STAT_SYNC_LSB 3
-#define BTCOEX_INT_STAT_SYNC_MASK 0x00000008
-#define BTCOEX_INT_STAT_SYNC_GET(x) (((x) & BTCOEX_INT_STAT_SYNC_MASK) >> BTCOEX_INT_STAT_SYNC_LSB)
-#define BTCOEX_INT_STAT_SYNC_SET(x) (((x) << BTCOEX_INT_STAT_SYNC_LSB) & BTCOEX_INT_STAT_SYNC_MASK)
-#define BTCOEX_INT_STAT_END_MSB 2
-#define BTCOEX_INT_STAT_END_LSB 2
-#define BTCOEX_INT_STAT_END_MASK 0x00000004
-#define BTCOEX_INT_STAT_END_GET(x) (((x) & BTCOEX_INT_STAT_END_MASK) >> BTCOEX_INT_STAT_END_LSB)
-#define BTCOEX_INT_STAT_END_SET(x) (((x) << BTCOEX_INT_STAT_END_LSB) & BTCOEX_INT_STAT_END_MASK)
-#define BTCOEX_INT_STAT_FRAME_CNT_MSB 1
-#define BTCOEX_INT_STAT_FRAME_CNT_LSB 1
-#define BTCOEX_INT_STAT_FRAME_CNT_MASK 0x00000002
-#define BTCOEX_INT_STAT_FRAME_CNT_GET(x) (((x) & BTCOEX_INT_STAT_FRAME_CNT_MASK) >> BTCOEX_INT_STAT_FRAME_CNT_LSB)
-#define BTCOEX_INT_STAT_FRAME_CNT_SET(x) (((x) << BTCOEX_INT_STAT_FRAME_CNT_LSB) & BTCOEX_INT_STAT_FRAME_CNT_MASK)
-#define BTCOEX_INT_STAT_CLK_CNT_MSB 0
-#define BTCOEX_INT_STAT_CLK_CNT_LSB 0
-#define BTCOEX_INT_STAT_CLK_CNT_MASK 0x00000001
-#define BTCOEX_INT_STAT_CLK_CNT_GET(x) (((x) & BTCOEX_INT_STAT_CLK_CNT_MASK) >> BTCOEX_INT_STAT_CLK_CNT_LSB)
-#define BTCOEX_INT_STAT_CLK_CNT_SET(x) (((x) << BTCOEX_INT_STAT_CLK_CNT_LSB) & BTCOEX_INT_STAT_CLK_CNT_MASK)
-
-#define BTPRIORITY_INT_EN_ADDRESS 0x0000026c
-#define BTPRIORITY_INT_EN_OFFSET 0x0000026c
-#define BTPRIORITY_INT_EN_BITMAP_MSB 31
-#define BTPRIORITY_INT_EN_BITMAP_LSB 0
-#define BTPRIORITY_INT_EN_BITMAP_MASK 0xffffffff
-#define BTPRIORITY_INT_EN_BITMAP_GET(x) (((x) & BTPRIORITY_INT_EN_BITMAP_MASK) >> BTPRIORITY_INT_EN_BITMAP_LSB)
-#define BTPRIORITY_INT_EN_BITMAP_SET(x) (((x) << BTPRIORITY_INT_EN_BITMAP_LSB) & BTPRIORITY_INT_EN_BITMAP_MASK)
-
-#define BTPRIORITY_INT_STAT_ADDRESS 0x00000270
-#define BTPRIORITY_INT_STAT_OFFSET 0x00000270
-#define BTPRIORITY_INT_STAT_BITMAP_MSB 31
-#define BTPRIORITY_INT_STAT_BITMAP_LSB 0
-#define BTPRIORITY_INT_STAT_BITMAP_MASK 0xffffffff
-#define BTPRIORITY_INT_STAT_BITMAP_GET(x) (((x) & BTPRIORITY_INT_STAT_BITMAP_MASK) >> BTPRIORITY_INT_STAT_BITMAP_LSB)
-#define BTPRIORITY_INT_STAT_BITMAP_SET(x) (((x) << BTPRIORITY_INT_STAT_BITMAP_LSB) & BTPRIORITY_INT_STAT_BITMAP_MASK)
-
-#define BTPRIORITY_STOMP_INT_EN_ADDRESS 0x00000274
-#define BTPRIORITY_STOMP_INT_EN_OFFSET 0x00000274
-#define BTPRIORITY_STOMP_INT_EN_BITMAP_MSB 31
-#define BTPRIORITY_STOMP_INT_EN_BITMAP_LSB 0
-#define BTPRIORITY_STOMP_INT_EN_BITMAP_MASK 0xffffffff
-#define BTPRIORITY_STOMP_INT_EN_BITMAP_GET(x) (((x) & BTPRIORITY_STOMP_INT_EN_BITMAP_MASK) >> BTPRIORITY_STOMP_INT_EN_BITMAP_LSB)
-#define BTPRIORITY_STOMP_INT_EN_BITMAP_SET(x) (((x) << BTPRIORITY_STOMP_INT_EN_BITMAP_LSB) & BTPRIORITY_STOMP_INT_EN_BITMAP_MASK)
-
-#define BTPRIORITY_STOMP_INT_STAT_ADDRESS 0x00000278
-#define BTPRIORITY_STOMP_INT_STAT_OFFSET 0x00000278
-#define BTPRIORITY_STOMP_INT_STAT_BITMAP_MSB 31
-#define BTPRIORITY_STOMP_INT_STAT_BITMAP_LSB 0
-#define BTPRIORITY_STOMP_INT_STAT_BITMAP_MASK 0xffffffff
-#define BTPRIORITY_STOMP_INT_STAT_BITMAP_GET(x) (((x) & BTPRIORITY_STOMP_INT_STAT_BITMAP_MASK) >> BTPRIORITY_STOMP_INT_STAT_BITMAP_LSB)
-#define BTPRIORITY_STOMP_INT_STAT_BITMAP_SET(x) (((x) << BTPRIORITY_STOMP_INT_STAT_BITMAP_LSB) & BTPRIORITY_STOMP_INT_STAT_BITMAP_MASK)
-
-#define MAC_PCU_BMISS_TIMEOUT_ADDRESS 0x0000027c
-#define MAC_PCU_BMISS_TIMEOUT_OFFSET 0x0000027c
-#define MAC_PCU_BMISS_TIMEOUT_ENABLE_MSB 24
-#define MAC_PCU_BMISS_TIMEOUT_ENABLE_LSB 24
-#define MAC_PCU_BMISS_TIMEOUT_ENABLE_MASK 0x01000000
-#define MAC_PCU_BMISS_TIMEOUT_ENABLE_GET(x) (((x) & MAC_PCU_BMISS_TIMEOUT_ENABLE_MASK) >> MAC_PCU_BMISS_TIMEOUT_ENABLE_LSB)
-#define MAC_PCU_BMISS_TIMEOUT_ENABLE_SET(x) (((x) << MAC_PCU_BMISS_TIMEOUT_ENABLE_LSB) & MAC_PCU_BMISS_TIMEOUT_ENABLE_MASK)
-#define MAC_PCU_BMISS_TIMEOUT_VALUE_MSB 23
-#define MAC_PCU_BMISS_TIMEOUT_VALUE_LSB 0
-#define MAC_PCU_BMISS_TIMEOUT_VALUE_MASK 0x00ffffff
-#define MAC_PCU_BMISS_TIMEOUT_VALUE_GET(x) (((x) & MAC_PCU_BMISS_TIMEOUT_VALUE_MASK) >> MAC_PCU_BMISS_TIMEOUT_VALUE_LSB)
-#define MAC_PCU_BMISS_TIMEOUT_VALUE_SET(x) (((x) << MAC_PCU_BMISS_TIMEOUT_VALUE_LSB) & MAC_PCU_BMISS_TIMEOUT_VALUE_MASK)
-
-#define MAC_PCU_CAB_AWAKE_ADDRESS 0x00000280
-#define MAC_PCU_CAB_AWAKE_OFFSET 0x00000280
-#define MAC_PCU_CAB_AWAKE_ENABLE_MSB 16
-#define MAC_PCU_CAB_AWAKE_ENABLE_LSB 16
-#define MAC_PCU_CAB_AWAKE_ENABLE_MASK 0x00010000
-#define MAC_PCU_CAB_AWAKE_ENABLE_GET(x) (((x) & MAC_PCU_CAB_AWAKE_ENABLE_MASK) >> MAC_PCU_CAB_AWAKE_ENABLE_LSB)
-#define MAC_PCU_CAB_AWAKE_ENABLE_SET(x) (((x) << MAC_PCU_CAB_AWAKE_ENABLE_LSB) & MAC_PCU_CAB_AWAKE_ENABLE_MASK)
-#define MAC_PCU_CAB_AWAKE_DURATION_MSB 15
-#define MAC_PCU_CAB_AWAKE_DURATION_LSB 0
-#define MAC_PCU_CAB_AWAKE_DURATION_MASK 0x0000ffff
-#define MAC_PCU_CAB_AWAKE_DURATION_GET(x) (((x) & MAC_PCU_CAB_AWAKE_DURATION_MASK) >> MAC_PCU_CAB_AWAKE_DURATION_LSB)
-#define MAC_PCU_CAB_AWAKE_DURATION_SET(x) (((x) << MAC_PCU_CAB_AWAKE_DURATION_LSB) & MAC_PCU_CAB_AWAKE_DURATION_MASK)
-
-#define LP_PERF_COUNTER_ADDRESS 0x00000284
-#define LP_PERF_COUNTER_OFFSET 0x00000284
-#define LP_PERF_COUNTER_EN_MSB 0
-#define LP_PERF_COUNTER_EN_LSB 0
-#define LP_PERF_COUNTER_EN_MASK 0x00000001
-#define LP_PERF_COUNTER_EN_GET(x) (((x) & LP_PERF_COUNTER_EN_MASK) >> LP_PERF_COUNTER_EN_LSB)
-#define LP_PERF_COUNTER_EN_SET(x) (((x) << LP_PERF_COUNTER_EN_LSB) & LP_PERF_COUNTER_EN_MASK)
-
-#define LP_PERF_LIGHT_SLEEP_ADDRESS 0x00000288
-#define LP_PERF_LIGHT_SLEEP_OFFSET 0x00000288
-#define LP_PERF_LIGHT_SLEEP_CNT_MSB 31
-#define LP_PERF_LIGHT_SLEEP_CNT_LSB 0
-#define LP_PERF_LIGHT_SLEEP_CNT_MASK 0xffffffff
-#define LP_PERF_LIGHT_SLEEP_CNT_GET(x) (((x) & LP_PERF_LIGHT_SLEEP_CNT_MASK) >> LP_PERF_LIGHT_SLEEP_CNT_LSB)
-#define LP_PERF_LIGHT_SLEEP_CNT_SET(x) (((x) << LP_PERF_LIGHT_SLEEP_CNT_LSB) & LP_PERF_LIGHT_SLEEP_CNT_MASK)
-
-#define LP_PERF_DEEP_SLEEP_ADDRESS 0x0000028c
-#define LP_PERF_DEEP_SLEEP_OFFSET 0x0000028c
-#define LP_PERF_DEEP_SLEEP_CNT_MSB 31
-#define LP_PERF_DEEP_SLEEP_CNT_LSB 0
-#define LP_PERF_DEEP_SLEEP_CNT_MASK 0xffffffff
-#define LP_PERF_DEEP_SLEEP_CNT_GET(x) (((x) & LP_PERF_DEEP_SLEEP_CNT_MASK) >> LP_PERF_DEEP_SLEEP_CNT_LSB)
-#define LP_PERF_DEEP_SLEEP_CNT_SET(x) (((x) << LP_PERF_DEEP_SLEEP_CNT_LSB) & LP_PERF_DEEP_SLEEP_CNT_MASK)
-
-#define LP_PERF_ON_ADDRESS 0x00000290
-#define LP_PERF_ON_OFFSET 0x00000290
-#define LP_PERF_ON_CNT_MSB 31
-#define LP_PERF_ON_CNT_LSB 0
-#define LP_PERF_ON_CNT_MASK 0xffffffff
-#define LP_PERF_ON_CNT_GET(x) (((x) & LP_PERF_ON_CNT_MASK) >> LP_PERF_ON_CNT_LSB)
-#define LP_PERF_ON_CNT_SET(x) (((x) << LP_PERF_ON_CNT_LSB) & LP_PERF_ON_CNT_MASK)
-
-#define ST_64_BIT_ADDRESS 0x00000294
-#define ST_64_BIT_OFFSET 0x00000294
-#define ST_64_BIT_TIMEOUT_MSB 26
-#define ST_64_BIT_TIMEOUT_LSB 9
-#define ST_64_BIT_TIMEOUT_MASK 0x07fffe00
-#define ST_64_BIT_TIMEOUT_GET(x) (((x) & ST_64_BIT_TIMEOUT_MASK) >> ST_64_BIT_TIMEOUT_LSB)
-#define ST_64_BIT_TIMEOUT_SET(x) (((x) << ST_64_BIT_TIMEOUT_LSB) & ST_64_BIT_TIMEOUT_MASK)
-#define ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_MSB 8
-#define ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_LSB 8
-#define ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_MASK 0x00000100
-#define ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_GET(x) (((x) & ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_MASK) >> ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_LSB)
-#define ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_SET(x) (((x) << ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_LSB) & ST_64_BIT_REQ_ACK_NOT_PULLED_DOWN_MASK)
-#define ST_64_BIT_DRIVE_MODE_MSB 7
-#define ST_64_BIT_DRIVE_MODE_LSB 7
-#define ST_64_BIT_DRIVE_MODE_MASK 0x00000080
-#define ST_64_BIT_DRIVE_MODE_GET(x) (((x) & ST_64_BIT_DRIVE_MODE_MASK) >> ST_64_BIT_DRIVE_MODE_LSB)
-#define ST_64_BIT_DRIVE_MODE_SET(x) (((x) << ST_64_BIT_DRIVE_MODE_LSB) & ST_64_BIT_DRIVE_MODE_MASK)
-#define ST_64_BIT_CLOCK_GATE_MSB 6
-#define ST_64_BIT_CLOCK_GATE_LSB 6
-#define ST_64_BIT_CLOCK_GATE_MASK 0x00000040
-#define ST_64_BIT_CLOCK_GATE_GET(x) (((x) & ST_64_BIT_CLOCK_GATE_MASK) >> ST_64_BIT_CLOCK_GATE_LSB)
-#define ST_64_BIT_CLOCK_GATE_SET(x) (((x) << ST_64_BIT_CLOCK_GATE_LSB) & ST_64_BIT_CLOCK_GATE_MASK)
-#define ST_64_BIT_SOC_CLK_DIVIDE_RATIO_MSB 5
-#define ST_64_BIT_SOC_CLK_DIVIDE_RATIO_LSB 1
-#define ST_64_BIT_SOC_CLK_DIVIDE_RATIO_MASK 0x0000003e
-#define ST_64_BIT_SOC_CLK_DIVIDE_RATIO_GET(x) (((x) & ST_64_BIT_SOC_CLK_DIVIDE_RATIO_MASK) >> ST_64_BIT_SOC_CLK_DIVIDE_RATIO_LSB)
-#define ST_64_BIT_SOC_CLK_DIVIDE_RATIO_SET(x) (((x) << ST_64_BIT_SOC_CLK_DIVIDE_RATIO_LSB) & ST_64_BIT_SOC_CLK_DIVIDE_RATIO_MASK)
-#define ST_64_BIT_MODE_MSB 0
-#define ST_64_BIT_MODE_LSB 0
-#define ST_64_BIT_MODE_MASK 0x00000001
-#define ST_64_BIT_MODE_GET(x) (((x) & ST_64_BIT_MODE_MASK) >> ST_64_BIT_MODE_LSB)
-#define ST_64_BIT_MODE_SET(x) (((x) << ST_64_BIT_MODE_LSB) & ST_64_BIT_MODE_MASK)
-
-#define MESSAGE_WR_ADDRESS 0x00000298
-#define MESSAGE_WR_OFFSET 0x00000298
-#define MESSAGE_WR_TYPE_MSB 31
-#define MESSAGE_WR_TYPE_LSB 0
-#define MESSAGE_WR_TYPE_MASK 0xffffffff
-#define MESSAGE_WR_TYPE_GET(x) (((x) & MESSAGE_WR_TYPE_MASK) >> MESSAGE_WR_TYPE_LSB)
-#define MESSAGE_WR_TYPE_SET(x) (((x) << MESSAGE_WR_TYPE_LSB) & MESSAGE_WR_TYPE_MASK)
-
-#define MESSAGE_WR_P_ADDRESS 0x0000029c
-#define MESSAGE_WR_P_OFFSET 0x0000029c
-#define MESSAGE_WR_P_PARAMETER_MSB 31
-#define MESSAGE_WR_P_PARAMETER_LSB 0
-#define MESSAGE_WR_P_PARAMETER_MASK 0xffffffff
-#define MESSAGE_WR_P_PARAMETER_GET(x) (((x) & MESSAGE_WR_P_PARAMETER_MASK) >> MESSAGE_WR_P_PARAMETER_LSB)
-#define MESSAGE_WR_P_PARAMETER_SET(x) (((x) << MESSAGE_WR_P_PARAMETER_LSB) & MESSAGE_WR_P_PARAMETER_MASK)
-
-#define MESSAGE_RD_ADDRESS 0x000002a0
-#define MESSAGE_RD_OFFSET 0x000002a0
-#define MESSAGE_RD_TYPE_MSB 31
-#define MESSAGE_RD_TYPE_LSB 0
-#define MESSAGE_RD_TYPE_MASK 0xffffffff
-#define MESSAGE_RD_TYPE_GET(x) (((x) & MESSAGE_RD_TYPE_MASK) >> MESSAGE_RD_TYPE_LSB)
-#define MESSAGE_RD_TYPE_SET(x) (((x) << MESSAGE_RD_TYPE_LSB) & MESSAGE_RD_TYPE_MASK)
-
-#define MESSAGE_RD_P_ADDRESS 0x000002a4
-#define MESSAGE_RD_P_OFFSET 0x000002a4
-#define MESSAGE_RD_P_PARAMETER_MSB 31
-#define MESSAGE_RD_P_PARAMETER_LSB 0
-#define MESSAGE_RD_P_PARAMETER_MASK 0xffffffff
-#define MESSAGE_RD_P_PARAMETER_GET(x) (((x) & MESSAGE_RD_P_PARAMETER_MASK) >> MESSAGE_RD_P_PARAMETER_LSB)
-#define MESSAGE_RD_P_PARAMETER_SET(x) (((x) << MESSAGE_RD_P_PARAMETER_LSB) & MESSAGE_RD_P_PARAMETER_MASK)
-
-#define CHIP_MODE_ADDRESS 0x000002a8
-#define CHIP_MODE_OFFSET 0x000002a8
-#define CHIP_MODE_BIT_MSB 1
-#define CHIP_MODE_BIT_LSB 0
-#define CHIP_MODE_BIT_MASK 0x00000003
-#define CHIP_MODE_BIT_GET(x) (((x) & CHIP_MODE_BIT_MASK) >> CHIP_MODE_BIT_LSB)
-#define CHIP_MODE_BIT_SET(x) (((x) << CHIP_MODE_BIT_LSB) & CHIP_MODE_BIT_MASK)
-
-#define CLK_REQ_FALL_EDGE_ADDRESS 0x000002ac
-#define CLK_REQ_FALL_EDGE_OFFSET 0x000002ac
-#define CLK_REQ_FALL_EDGE_EN_MSB 31
-#define CLK_REQ_FALL_EDGE_EN_LSB 31
-#define CLK_REQ_FALL_EDGE_EN_MASK 0x80000000
-#define CLK_REQ_FALL_EDGE_EN_GET(x) (((x) & CLK_REQ_FALL_EDGE_EN_MASK) >> CLK_REQ_FALL_EDGE_EN_LSB)
-#define CLK_REQ_FALL_EDGE_EN_SET(x) (((x) << CLK_REQ_FALL_EDGE_EN_LSB) & CLK_REQ_FALL_EDGE_EN_MASK)
-#define CLK_REQ_FALL_EDGE_DELAY_MSB 7
-#define CLK_REQ_FALL_EDGE_DELAY_LSB 0
-#define CLK_REQ_FALL_EDGE_DELAY_MASK 0x000000ff
-#define CLK_REQ_FALL_EDGE_DELAY_GET(x) (((x) & CLK_REQ_FALL_EDGE_DELAY_MASK) >> CLK_REQ_FALL_EDGE_DELAY_LSB)
-#define CLK_REQ_FALL_EDGE_DELAY_SET(x) (((x) << CLK_REQ_FALL_EDGE_DELAY_LSB) & CLK_REQ_FALL_EDGE_DELAY_MASK)
-
-#define OTP_ADDRESS 0x000002b0
-#define OTP_OFFSET 0x000002b0
-#define OTP_LDO25_EN_MSB 1
-#define OTP_LDO25_EN_LSB 1
-#define OTP_LDO25_EN_MASK 0x00000002
-#define OTP_LDO25_EN_GET(x) (((x) & OTP_LDO25_EN_MASK) >> OTP_LDO25_EN_LSB)
-#define OTP_LDO25_EN_SET(x) (((x) << OTP_LDO25_EN_LSB) & OTP_LDO25_EN_MASK)
-#define OTP_VDD12_EN_MSB 0
-#define OTP_VDD12_EN_LSB 0
-#define OTP_VDD12_EN_MASK 0x00000001
-#define OTP_VDD12_EN_GET(x) (((x) & OTP_VDD12_EN_MASK) >> OTP_VDD12_EN_LSB)
-#define OTP_VDD12_EN_SET(x) (((x) << OTP_VDD12_EN_LSB) & OTP_VDD12_EN_MASK)
-
-#define OTP_STATUS_ADDRESS 0x000002b4
-#define OTP_STATUS_OFFSET 0x000002b4
-#define OTP_STATUS_LDO25_EN_READY_MSB 1
-#define OTP_STATUS_LDO25_EN_READY_LSB 1
-#define OTP_STATUS_LDO25_EN_READY_MASK 0x00000002
-#define OTP_STATUS_LDO25_EN_READY_GET(x) (((x) & OTP_STATUS_LDO25_EN_READY_MASK) >> OTP_STATUS_LDO25_EN_READY_LSB)
-#define OTP_STATUS_LDO25_EN_READY_SET(x) (((x) << OTP_STATUS_LDO25_EN_READY_LSB) & OTP_STATUS_LDO25_EN_READY_MASK)
-#define OTP_STATUS_VDD12_EN_READY_MSB 0
-#define OTP_STATUS_VDD12_EN_READY_LSB 0
-#define OTP_STATUS_VDD12_EN_READY_MASK 0x00000001
-#define OTP_STATUS_VDD12_EN_READY_GET(x) (((x) & OTP_STATUS_VDD12_EN_READY_MASK) >> OTP_STATUS_VDD12_EN_READY_LSB)
-#define OTP_STATUS_VDD12_EN_READY_SET(x) (((x) << OTP_STATUS_VDD12_EN_READY_LSB) & OTP_STATUS_VDD12_EN_READY_MASK)
-
-#define PMU_ADDRESS 0x000002b8
-#define PMU_OFFSET 0x000002b8
-#define PMU_REG_WAKEUP_TIME_SEL_MSB 1
-#define PMU_REG_WAKEUP_TIME_SEL_LSB 0
-#define PMU_REG_WAKEUP_TIME_SEL_MASK 0x00000003
-#define PMU_REG_WAKEUP_TIME_SEL_GET(x) (((x) & PMU_REG_WAKEUP_TIME_SEL_MASK) >> PMU_REG_WAKEUP_TIME_SEL_LSB)
-#define PMU_REG_WAKEUP_TIME_SEL_SET(x) (((x) << PMU_REG_WAKEUP_TIME_SEL_LSB) & PMU_REG_WAKEUP_TIME_SEL_MASK)
-
-#define PMU_CONFIG_ADDRESS 0x000002c0
-#define PMU_CONFIG_OFFSET 0x000002c0
-#define PMU_CONFIG_VALUE_MSB 15
-#define PMU_CONFIG_VALUE_LSB 0
-#define PMU_CONFIG_VALUE_MASK 0x0000ffff
-#define PMU_CONFIG_VALUE_GET(x) (((x) & PMU_CONFIG_VALUE_MASK) >> PMU_CONFIG_VALUE_LSB)
-#define PMU_CONFIG_VALUE_SET(x) (((x) << PMU_CONFIG_VALUE_LSB) & PMU_CONFIG_VALUE_MASK)
-
-#define PMU_BYPASS_ADDRESS 0x000002c8
-#define PMU_BYPASS_OFFSET 0x000002c8
-#define PMU_BYPASS_SWREG_MSB 2
-#define PMU_BYPASS_SWREG_LSB 2
-#define PMU_BYPASS_SWREG_MASK 0x00000004
-#define PMU_BYPASS_SWREG_GET(x) (((x) & PMU_BYPASS_SWREG_MASK) >> PMU_BYPASS_SWREG_LSB)
-#define PMU_BYPASS_SWREG_SET(x) (((x) << PMU_BYPASS_SWREG_LSB) & PMU_BYPASS_SWREG_MASK)
-#define PMU_BYPASS_DREG_MSB 1
-#define PMU_BYPASS_DREG_LSB 1
-#define PMU_BYPASS_DREG_MASK 0x00000002
-#define PMU_BYPASS_DREG_GET(x) (((x) & PMU_BYPASS_DREG_MASK) >> PMU_BYPASS_DREG_LSB)
-#define PMU_BYPASS_DREG_SET(x) (((x) << PMU_BYPASS_DREG_LSB) & PMU_BYPASS_DREG_MASK)
-#define PMU_BYPASS_PAREG_MSB 0
-#define PMU_BYPASS_PAREG_LSB 0
-#define PMU_BYPASS_PAREG_MASK 0x00000001
-#define PMU_BYPASS_PAREG_GET(x) (((x) & PMU_BYPASS_PAREG_MASK) >> PMU_BYPASS_PAREG_LSB)
-#define PMU_BYPASS_PAREG_SET(x) (((x) << PMU_BYPASS_PAREG_LSB) & PMU_BYPASS_PAREG_MASK)
-
-#define MAC_PCU_TSF2_L32_ADDRESS 0x000002cc
-#define MAC_PCU_TSF2_L32_OFFSET 0x000002cc
-#define MAC_PCU_TSF2_L32_VALUE_MSB 31
-#define MAC_PCU_TSF2_L32_VALUE_LSB 0
-#define MAC_PCU_TSF2_L32_VALUE_MASK 0xffffffff
-#define MAC_PCU_TSF2_L32_VALUE_GET(x) (((x) & MAC_PCU_TSF2_L32_VALUE_MASK) >> MAC_PCU_TSF2_L32_VALUE_LSB)
-#define MAC_PCU_TSF2_L32_VALUE_SET(x) (((x) << MAC_PCU_TSF2_L32_VALUE_LSB) & MAC_PCU_TSF2_L32_VALUE_MASK)
-
-#define MAC_PCU_TSF2_U32_ADDRESS 0x000002d0
-#define MAC_PCU_TSF2_U32_OFFSET 0x000002d0
-#define MAC_PCU_TSF2_U32_VALUE_MSB 31
-#define MAC_PCU_TSF2_U32_VALUE_LSB 0
-#define MAC_PCU_TSF2_U32_VALUE_MASK 0xffffffff
-#define MAC_PCU_TSF2_U32_VALUE_GET(x) (((x) & MAC_PCU_TSF2_U32_VALUE_MASK) >> MAC_PCU_TSF2_U32_VALUE_LSB)
-#define MAC_PCU_TSF2_U32_VALUE_SET(x) (((x) << MAC_PCU_TSF2_U32_VALUE_LSB) & MAC_PCU_TSF2_U32_VALUE_MASK)
-
-#define MAC_PCU_GENERIC_TIMERS_MODE3_ADDRESS 0x000002d4
-#define MAC_PCU_GENERIC_TIMERS_MODE3_OFFSET 0x000002d4
-#define MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_MSB 27
-#define MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_LSB 24
-#define MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_MASK 0x0f000000
-#define MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_GET(x) (((x) & MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_MASK) >> MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_LSB)
-#define MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_SET(x) (((x) << MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_LSB) & MAC_PCU_GENERIC_TIMERS_MODE3_OVERFLOW_INDEX_MASK)
-#define MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_MSB 19
-#define MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_LSB 0
-#define MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_MASK 0x000fffff
-#define MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_GET(x) (((x) & MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_MASK) >> MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_LSB)
-#define MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_SET(x) (((x) << MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_LSB) & MAC_PCU_GENERIC_TIMERS_MODE3_THRESH_MASK)
-
-#define MAC_PCU_DIRECT_CONNECT_ADDRESS 0x000002d8
-#define MAC_PCU_DIRECT_CONNECT_OFFSET 0x000002d8
-#define MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_MSB 2
-#define MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_LSB 2
-#define MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_MASK 0x00000004
-#define MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_GET(x) (((x) & MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_MASK) >> MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_LSB)
-#define MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_SET(x) (((x) << MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_LSB) & MAC_PCU_DIRECT_CONNECT_STA_TSF_1_2_SEL_MASK)
-#define MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_MSB 1
-#define MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_LSB 1
-#define MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_MASK 0x00000002
-#define MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_GET(x) (((x) & MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_MASK) >> MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_LSB)
-#define MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_SET(x) (((x) << MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_LSB) & MAC_PCU_DIRECT_CONNECT_AP_TSF_1_2_SEL_MASK)
-#define MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_MSB 0
-#define MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_LSB 0
-#define MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_MASK 0x00000001
-#define MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_GET(x) (((x) & MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_MASK) >> MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_LSB)
-#define MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_SET(x) (((x) << MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_LSB) & MAC_PCU_DIRECT_CONNECT_AP_STA_ENABLE_MASK)
-
-#define THERM_CTRL1_ADDRESS 0x000002dc
-#define THERM_CTRL1_OFFSET 0x000002dc
-#define THERM_CTRL1_BYPASS_MSB 16
-#define THERM_CTRL1_BYPASS_LSB 16
-#define THERM_CTRL1_BYPASS_MASK 0x00010000
-#define THERM_CTRL1_BYPASS_GET(x) (((x) & THERM_CTRL1_BYPASS_MASK) >> THERM_CTRL1_BYPASS_LSB)
-#define THERM_CTRL1_BYPASS_SET(x) (((x) << THERM_CTRL1_BYPASS_LSB) & THERM_CTRL1_BYPASS_MASK)
-#define THERM_CTRL1_WIDTH_ARBITOR_MSB 15
-#define THERM_CTRL1_WIDTH_ARBITOR_LSB 12
-#define THERM_CTRL1_WIDTH_ARBITOR_MASK 0x0000f000
-#define THERM_CTRL1_WIDTH_ARBITOR_GET(x) (((x) & THERM_CTRL1_WIDTH_ARBITOR_MASK) >> THERM_CTRL1_WIDTH_ARBITOR_LSB)
-#define THERM_CTRL1_WIDTH_ARBITOR_SET(x) (((x) << THERM_CTRL1_WIDTH_ARBITOR_LSB) & THERM_CTRL1_WIDTH_ARBITOR_MASK)
-#define THERM_CTRL1_WIDTH_MSB 11
-#define THERM_CTRL1_WIDTH_LSB 5
-#define THERM_CTRL1_WIDTH_MASK 0x00000fe0
-#define THERM_CTRL1_WIDTH_GET(x) (((x) & THERM_CTRL1_WIDTH_MASK) >> THERM_CTRL1_WIDTH_LSB)
-#define THERM_CTRL1_WIDTH_SET(x) (((x) << THERM_CTRL1_WIDTH_LSB) & THERM_CTRL1_WIDTH_MASK)
-#define THERM_CTRL1_TYPE_MSB 4
-#define THERM_CTRL1_TYPE_LSB 3
-#define THERM_CTRL1_TYPE_MASK 0x00000018
-#define THERM_CTRL1_TYPE_GET(x) (((x) & THERM_CTRL1_TYPE_MASK) >> THERM_CTRL1_TYPE_LSB)
-#define THERM_CTRL1_TYPE_SET(x) (((x) << THERM_CTRL1_TYPE_LSB) & THERM_CTRL1_TYPE_MASK)
-#define THERM_CTRL1_MEASURE_MSB 2
-#define THERM_CTRL1_MEASURE_LSB 2
-#define THERM_CTRL1_MEASURE_MASK 0x00000004
-#define THERM_CTRL1_MEASURE_GET(x) (((x) & THERM_CTRL1_MEASURE_MASK) >> THERM_CTRL1_MEASURE_LSB)
-#define THERM_CTRL1_MEASURE_SET(x) (((x) << THERM_CTRL1_MEASURE_LSB) & THERM_CTRL1_MEASURE_MASK)
-#define THERM_CTRL1_INT_EN_MSB 1
-#define THERM_CTRL1_INT_EN_LSB 1
-#define THERM_CTRL1_INT_EN_MASK 0x00000002
-#define THERM_CTRL1_INT_EN_GET(x) (((x) & THERM_CTRL1_INT_EN_MASK) >> THERM_CTRL1_INT_EN_LSB)
-#define THERM_CTRL1_INT_EN_SET(x) (((x) << THERM_CTRL1_INT_EN_LSB) & THERM_CTRL1_INT_EN_MASK)
-#define THERM_CTRL1_INT_STATUS_MSB 0
-#define THERM_CTRL1_INT_STATUS_LSB 0
-#define THERM_CTRL1_INT_STATUS_MASK 0x00000001
-#define THERM_CTRL1_INT_STATUS_GET(x) (((x) & THERM_CTRL1_INT_STATUS_MASK) >> THERM_CTRL1_INT_STATUS_LSB)
-#define THERM_CTRL1_INT_STATUS_SET(x) (((x) << THERM_CTRL1_INT_STATUS_LSB) & THERM_CTRL1_INT_STATUS_MASK)
-
-#define THERM_CTRL2_ADDRESS 0x000002e0
-#define THERM_CTRL2_OFFSET 0x000002e0
-#define THERM_CTRL2_ADC_OFF_MSB 25
-#define THERM_CTRL2_ADC_OFF_LSB 25
-#define THERM_CTRL2_ADC_OFF_MASK 0x02000000
-#define THERM_CTRL2_ADC_OFF_GET(x) (((x) & THERM_CTRL2_ADC_OFF_MASK) >> THERM_CTRL2_ADC_OFF_LSB)
-#define THERM_CTRL2_ADC_OFF_SET(x) (((x) << THERM_CTRL2_ADC_OFF_LSB) & THERM_CTRL2_ADC_OFF_MASK)
-#define THERM_CTRL2_ADC_ON_MSB 24
-#define THERM_CTRL2_ADC_ON_LSB 24
-#define THERM_CTRL2_ADC_ON_MASK 0x01000000
-#define THERM_CTRL2_ADC_ON_GET(x) (((x) & THERM_CTRL2_ADC_ON_MASK) >> THERM_CTRL2_ADC_ON_LSB)
-#define THERM_CTRL2_ADC_ON_SET(x) (((x) << THERM_CTRL2_ADC_ON_LSB) & THERM_CTRL2_ADC_ON_MASK)
-#define THERM_CTRL2_SAMPLE_MSB 23
-#define THERM_CTRL2_SAMPLE_LSB 16
-#define THERM_CTRL2_SAMPLE_MASK 0x00ff0000
-#define THERM_CTRL2_SAMPLE_GET(x) (((x) & THERM_CTRL2_SAMPLE_MASK) >> THERM_CTRL2_SAMPLE_LSB)
-#define THERM_CTRL2_SAMPLE_SET(x) (((x) << THERM_CTRL2_SAMPLE_LSB) & THERM_CTRL2_SAMPLE_MASK)
-#define THERM_CTRL2_HIGH_MSB 15
-#define THERM_CTRL2_HIGH_LSB 8
-#define THERM_CTRL2_HIGH_MASK 0x0000ff00
-#define THERM_CTRL2_HIGH_GET(x) (((x) & THERM_CTRL2_HIGH_MASK) >> THERM_CTRL2_HIGH_LSB)
-#define THERM_CTRL2_HIGH_SET(x) (((x) << THERM_CTRL2_HIGH_LSB) & THERM_CTRL2_HIGH_MASK)
-#define THERM_CTRL2_LOW_MSB 7
-#define THERM_CTRL2_LOW_LSB 0
-#define THERM_CTRL2_LOW_MASK 0x000000ff
-#define THERM_CTRL2_LOW_GET(x) (((x) & THERM_CTRL2_LOW_MASK) >> THERM_CTRL2_LOW_LSB)
-#define THERM_CTRL2_LOW_SET(x) (((x) << THERM_CTRL2_LOW_LSB) & THERM_CTRL2_LOW_MASK)
-
-#define THERM_CTRL3_ADDRESS 0x000002e4
-#define THERM_CTRL3_OFFSET 0x000002e4
-#define THERM_CTRL3_ADC_GAIN_MSB 16
-#define THERM_CTRL3_ADC_GAIN_LSB 8
-#define THERM_CTRL3_ADC_GAIN_MASK 0x0001ff00
-#define THERM_CTRL3_ADC_GAIN_GET(x) (((x) & THERM_CTRL3_ADC_GAIN_MASK) >> THERM_CTRL3_ADC_GAIN_LSB)
-#define THERM_CTRL3_ADC_GAIN_SET(x) (((x) << THERM_CTRL3_ADC_GAIN_LSB) & THERM_CTRL3_ADC_GAIN_MASK)
-#define THERM_CTRL3_ADC_OFFSET_MSB 7
-#define THERM_CTRL3_ADC_OFFSET_LSB 0
-#define THERM_CTRL3_ADC_OFFSET_MASK 0x000000ff
-#define THERM_CTRL3_ADC_OFFSET_GET(x) (((x) & THERM_CTRL3_ADC_OFFSET_MASK) >> THERM_CTRL3_ADC_OFFSET_LSB)
-#define THERM_CTRL3_ADC_OFFSET_SET(x) (((x) << THERM_CTRL3_ADC_OFFSET_LSB) & THERM_CTRL3_ADC_OFFSET_MASK)
-
-
-#ifndef __ASSEMBLER__
-
-typedef struct rtc_wlan_reg_reg_s {
- volatile unsigned int wlan_reset_control;
- volatile unsigned int wlan_xtal_control;
- volatile unsigned int wlan_tcxo_detect;
- volatile unsigned int wlan_xtal_test;
- volatile unsigned int wlan_quadrature;
- volatile unsigned int wlan_pll_control;
- volatile unsigned int wlan_pll_settle;
- volatile unsigned int wlan_xtal_settle;
- volatile unsigned int wlan_cpu_clock;
- volatile unsigned int wlan_clock_out;
- volatile unsigned int wlan_clock_control;
- volatile unsigned int wlan_bias_override;
- volatile unsigned int wlan_wdt_control;
- volatile unsigned int wlan_wdt_status;
- volatile unsigned int wlan_wdt;
- volatile unsigned int wlan_wdt_count;
- volatile unsigned int wlan_wdt_reset;
- volatile unsigned int wlan_int_status;
- volatile unsigned int wlan_lf_timer0;
- volatile unsigned int wlan_lf_timer_count0;
- volatile unsigned int wlan_lf_timer_control0;
- volatile unsigned int wlan_lf_timer_status0;
- volatile unsigned int wlan_lf_timer1;
- volatile unsigned int wlan_lf_timer_count1;
- volatile unsigned int wlan_lf_timer_control1;
- volatile unsigned int wlan_lf_timer_status1;
- volatile unsigned int wlan_lf_timer2;
- volatile unsigned int wlan_lf_timer_count2;
- volatile unsigned int wlan_lf_timer_control2;
- volatile unsigned int wlan_lf_timer_status2;
- volatile unsigned int wlan_lf_timer3;
- volatile unsigned int wlan_lf_timer_count3;
- volatile unsigned int wlan_lf_timer_control3;
- volatile unsigned int wlan_lf_timer_status3;
- volatile unsigned int wlan_hf_timer;
- volatile unsigned int wlan_hf_timer_count;
- volatile unsigned int wlan_hf_lf_count;
- volatile unsigned int wlan_hf_timer_control;
- volatile unsigned int wlan_hf_timer_status;
- volatile unsigned int wlan_rtc_control;
- volatile unsigned int wlan_rtc_time;
- volatile unsigned int wlan_rtc_date;
- volatile unsigned int wlan_rtc_set_time;
- volatile unsigned int wlan_rtc_set_date;
- volatile unsigned int wlan_rtc_set_alarm;
- volatile unsigned int wlan_rtc_config;
- volatile unsigned int wlan_rtc_alarm_status;
- volatile unsigned int wlan_uart_wakeup;
- volatile unsigned int wlan_reset_cause;
- volatile unsigned int wlan_system_sleep;
- volatile unsigned int wlan_sdio_wrapper;
- volatile unsigned int wlan_mac_sleep_control;
- volatile unsigned int wlan_keep_awake;
- volatile unsigned int wlan_lpo_cal_time;
- volatile unsigned int wlan_lpo_init_dividend_int;
- volatile unsigned int wlan_lpo_init_dividend_fraction;
- volatile unsigned int wlan_lpo_cal;
- volatile unsigned int wlan_lpo_cal_test_control;
- volatile unsigned int wlan_lpo_cal_test_status;
- volatile unsigned int wlan_chip_id;
- volatile unsigned int wlan_derived_rtc_clk;
- volatile unsigned int mac_pcu_slp32_mode;
- volatile unsigned int mac_pcu_slp32_wake;
- volatile unsigned int mac_pcu_slp32_inc;
- volatile unsigned int mac_pcu_slp_mib1;
- volatile unsigned int mac_pcu_slp_mib2;
- volatile unsigned int mac_pcu_slp_mib3;
- volatile unsigned int wlan_power_reg;
- volatile unsigned int wlan_core_clk_ctrl;
- volatile unsigned int wlan_gpio_wakeup_control;
- volatile unsigned int ht;
- volatile unsigned int mac_pcu_tsf_l32;
- volatile unsigned int mac_pcu_tsf_u32;
- volatile unsigned int mac_pcu_wbtimer;
- unsigned char pad0[24]; /* pad to 0x140 */
- volatile unsigned int mac_pcu_generic_timers[16];
- volatile unsigned int mac_pcu_generic_timers_mode;
- unsigned char pad1[60]; /* pad to 0x1c0 */
- volatile unsigned int mac_pcu_generic_timers2[16];
- volatile unsigned int mac_pcu_generic_timers_mode2;
- volatile unsigned int mac_pcu_slp1;
- volatile unsigned int mac_pcu_slp2;
- volatile unsigned int mac_pcu_reset_tsf;
- volatile unsigned int mac_pcu_tsf_add_pll;
- volatile unsigned int sleep_retention;
- volatile unsigned int btcoexctrl;
- volatile unsigned int wbsync_priority1;
- volatile unsigned int wbsync_priority2;
- volatile unsigned int wbsync_priority3;
- volatile unsigned int btcoex0;
- volatile unsigned int btcoex1;
- volatile unsigned int btcoex2;
- volatile unsigned int btcoex3;
- volatile unsigned int btcoex4;
- volatile unsigned int btcoex5;
- volatile unsigned int btcoex6;
- volatile unsigned int lock;
- volatile unsigned int nolock_priority;
- volatile unsigned int wbsync;
- volatile unsigned int wbsync1;
- volatile unsigned int wbsync2;
- volatile unsigned int wbsync3;
- volatile unsigned int wb_timer_target;
- volatile unsigned int wb_timer_slop;
- volatile unsigned int btcoex_int_en;
- volatile unsigned int btcoex_int_stat;
- volatile unsigned int btpriority_int_en;
- volatile unsigned int btpriority_int_stat;
- volatile unsigned int btpriority_stomp_int_en;
- volatile unsigned int btpriority_stomp_int_stat;
- volatile unsigned int mac_pcu_bmiss_timeout;
- volatile unsigned int mac_pcu_cab_awake;
- volatile unsigned int lp_perf_counter;
- volatile unsigned int lp_perf_light_sleep;
- volatile unsigned int lp_perf_deep_sleep;
- volatile unsigned int lp_perf_on;
- volatile unsigned int st_64_bit;
- volatile unsigned int message_wr;
- volatile unsigned int message_wr_p;
- volatile unsigned int message_rd;
- volatile unsigned int message_rd_p;
- volatile unsigned int chip_mode;
- volatile unsigned int clk_req_fall_edge;
- volatile unsigned int otp;
- volatile unsigned int otp_status;
- volatile unsigned int pmu;
- unsigned char pad2[4]; /* pad to 0x2c0 */
- volatile unsigned int pmu_config[2];
- volatile unsigned int pmu_bypass;
- volatile unsigned int mac_pcu_tsf2_l32;
- volatile unsigned int mac_pcu_tsf2_u32;
- volatile unsigned int mac_pcu_generic_timers_mode3;
- volatile unsigned int mac_pcu_direct_connect;
- volatile unsigned int therm_ctrl1;
- volatile unsigned int therm_ctrl2;
- volatile unsigned int therm_ctrl3;
-} rtc_wlan_reg_reg_t;
-
-#endif /* __ASSEMBLER__ */
-
#endif /* _RTC_WLAN_REG_H_ */
diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/si_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/si_reg.h
deleted file mode 100644
index 2cd2e3c..0000000
--- a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/si_reg.h
+++ /dev/null
@@ -1,209 +0,0 @@
-// ------------------------------------------------------------------
-// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
-//
-//
-// Permission to use, copy, modify, and/or distribute this software for any
-// purpose with or without fee is hereby granted, provided that the above
-// copyright notice and this permission notice appear in all copies.
-//
-// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-//
-//
-// ------------------------------------------------------------------
-//===================================================================
-// Author(s): ="Atheros"
-//===================================================================
-
-
-#ifndef _SI_REG_REG_H_
-#define _SI_REG_REG_H_
-
-#define SI_CONFIG_ADDRESS 0x00000000
-#define SI_CONFIG_OFFSET 0x00000000
-#define SI_CONFIG_ERR_INT_MSB 19
-#define SI_CONFIG_ERR_INT_LSB 19
-#define SI_CONFIG_ERR_INT_MASK 0x00080000
-#define SI_CONFIG_ERR_INT_GET(x) (((x) & SI_CONFIG_ERR_INT_MASK) >> SI_CONFIG_ERR_INT_LSB)
-#define SI_CONFIG_ERR_INT_SET(x) (((x) << SI_CONFIG_ERR_INT_LSB) & SI_CONFIG_ERR_INT_MASK)
-#define SI_CONFIG_BIDIR_OD_DATA_MSB 18
-#define SI_CONFIG_BIDIR_OD_DATA_LSB 18
-#define SI_CONFIG_BIDIR_OD_DATA_MASK 0x00040000
-#define SI_CONFIG_BIDIR_OD_DATA_GET(x) (((x) & SI_CONFIG_BIDIR_OD_DATA_MASK) >> SI_CONFIG_BIDIR_OD_DATA_LSB)
-#define SI_CONFIG_BIDIR_OD_DATA_SET(x) (((x) << SI_CONFIG_BIDIR_OD_DATA_LSB) & SI_CONFIG_BIDIR_OD_DATA_MASK)
-#define SI_CONFIG_I2C_MSB 16
-#define SI_CONFIG_I2C_LSB 16
-#define SI_CONFIG_I2C_MASK 0x00010000
-#define SI_CONFIG_I2C_GET(x) (((x) & SI_CONFIG_I2C_MASK) >> SI_CONFIG_I2C_LSB)
-#define SI_CONFIG_I2C_SET(x) (((x) << SI_CONFIG_I2C_LSB) & SI_CONFIG_I2C_MASK)
-#define SI_CONFIG_POS_SAMPLE_MSB 7
-#define SI_CONFIG_POS_SAMPLE_LSB 7
-#define SI_CONFIG_POS_SAMPLE_MASK 0x00000080
-#define SI_CONFIG_POS_SAMPLE_GET(x) (((x) & SI_CONFIG_POS_SAMPLE_MASK) >> SI_CONFIG_POS_SAMPLE_LSB)
-#define SI_CONFIG_POS_SAMPLE_SET(x) (((x) << SI_CONFIG_POS_SAMPLE_LSB) & SI_CONFIG_POS_SAMPLE_MASK)
-#define SI_CONFIG_POS_DRIVE_MSB 6
-#define SI_CONFIG_POS_DRIVE_LSB 6
-#define SI_CONFIG_POS_DRIVE_MASK 0x00000040
-#define SI_CONFIG_POS_DRIVE_GET(x) (((x) & SI_CONFIG_POS_DRIVE_MASK) >> SI_CONFIG_POS_DRIVE_LSB)
-#define SI_CONFIG_POS_DRIVE_SET(x) (((x) << SI_CONFIG_POS_DRIVE_LSB) & SI_CONFIG_POS_DRIVE_MASK)
-#define SI_CONFIG_INACTIVE_DATA_MSB 5
-#define SI_CONFIG_INACTIVE_DATA_LSB 5
-#define SI_CONFIG_INACTIVE_DATA_MASK 0x00000020
-#define SI_CONFIG_INACTIVE_DATA_GET(x) (((x) & SI_CONFIG_INACTIVE_DATA_MASK) >> SI_CONFIG_INACTIVE_DATA_LSB)
-#define SI_CONFIG_INACTIVE_DATA_SET(x) (((x) << SI_CONFIG_INACTIVE_DATA_LSB) & SI_CONFIG_INACTIVE_DATA_MASK)
-#define SI_CONFIG_INACTIVE_CLK_MSB 4
-#define SI_CONFIG_INACTIVE_CLK_LSB 4
-#define SI_CONFIG_INACTIVE_CLK_MASK 0x00000010
-#define SI_CONFIG_INACTIVE_CLK_GET(x) (((x) & SI_CONFIG_INACTIVE_CLK_MASK) >> SI_CONFIG_INACTIVE_CLK_LSB)
-#define SI_CONFIG_INACTIVE_CLK_SET(x) (((x) << SI_CONFIG_INACTIVE_CLK_LSB) & SI_CONFIG_INACTIVE_CLK_MASK)
-#define SI_CONFIG_DIVIDER_MSB 3
-#define SI_CONFIG_DIVIDER_LSB 0
-#define SI_CONFIG_DIVIDER_MASK 0x0000000f
-#define SI_CONFIG_DIVIDER_GET(x) (((x) & SI_CONFIG_DIVIDER_MASK) >> SI_CONFIG_DIVIDER_LSB)
-#define SI_CONFIG_DIVIDER_SET(x) (((x) << SI_CONFIG_DIVIDER_LSB) & SI_CONFIG_DIVIDER_MASK)
-
-#define SI_CS_ADDRESS 0x00000004
-#define SI_CS_OFFSET 0x00000004
-#define SI_CS_BIT_CNT_IN_LAST_BYTE_MSB 13
-#define SI_CS_BIT_CNT_IN_LAST_BYTE_LSB 11
-#define SI_CS_BIT_CNT_IN_LAST_BYTE_MASK 0x00003800
-#define SI_CS_BIT_CNT_IN_LAST_BYTE_GET(x) (((x) & SI_CS_BIT_CNT_IN_LAST_BYTE_MASK) >> SI_CS_BIT_CNT_IN_LAST_BYTE_LSB)
-#define SI_CS_BIT_CNT_IN_LAST_BYTE_SET(x) (((x) << SI_CS_BIT_CNT_IN_LAST_BYTE_LSB) & SI_CS_BIT_CNT_IN_LAST_BYTE_MASK)
-#define SI_CS_DONE_ERR_MSB 10
-#define SI_CS_DONE_ERR_LSB 10
-#define SI_CS_DONE_ERR_MASK 0x00000400
-#define SI_CS_DONE_ERR_GET(x) (((x) & SI_CS_DONE_ERR_MASK) >> SI_CS_DONE_ERR_LSB)
-#define SI_CS_DONE_ERR_SET(x) (((x) << SI_CS_DONE_ERR_LSB) & SI_CS_DONE_ERR_MASK)
-#define SI_CS_DONE_INT_MSB 9
-#define SI_CS_DONE_INT_LSB 9
-#define SI_CS_DONE_INT_MASK 0x00000200
-#define SI_CS_DONE_INT_GET(x) (((x) & SI_CS_DONE_INT_MASK) >> SI_CS_DONE_INT_LSB)
-#define SI_CS_DONE_INT_SET(x) (((x) << SI_CS_DONE_INT_LSB) & SI_CS_DONE_INT_MASK)
-#define SI_CS_START_MSB 8
-#define SI_CS_START_LSB 8
-#define SI_CS_START_MASK 0x00000100
-#define SI_CS_START_GET(x) (((x) & SI_CS_START_MASK) >> SI_CS_START_LSB)
-#define SI_CS_START_SET(x) (((x) << SI_CS_START_LSB) & SI_CS_START_MASK)
-#define SI_CS_RX_CNT_MSB 7
-#define SI_CS_RX_CNT_LSB 4
-#define SI_CS_RX_CNT_MASK 0x000000f0
-#define SI_CS_RX_CNT_GET(x) (((x) & SI_CS_RX_CNT_MASK) >> SI_CS_RX_CNT_LSB)
-#define SI_CS_RX_CNT_SET(x) (((x) << SI_CS_RX_CNT_LSB) & SI_CS_RX_CNT_MASK)
-#define SI_CS_TX_CNT_MSB 3
-#define SI_CS_TX_CNT_LSB 0
-#define SI_CS_TX_CNT_MASK 0x0000000f
-#define SI_CS_TX_CNT_GET(x) (((x) & SI_CS_TX_CNT_MASK) >> SI_CS_TX_CNT_LSB)
-#define SI_CS_TX_CNT_SET(x) (((x) << SI_CS_TX_CNT_LSB) & SI_CS_TX_CNT_MASK)
-
-#define SI_TX_DATA0_ADDRESS 0x00000008
-#define SI_TX_DATA0_OFFSET 0x00000008
-#define SI_TX_DATA0_DATA3_MSB 31
-#define SI_TX_DATA0_DATA3_LSB 24
-#define SI_TX_DATA0_DATA3_MASK 0xff000000
-#define SI_TX_DATA0_DATA3_GET(x) (((x) & SI_TX_DATA0_DATA3_MASK) >> SI_TX_DATA0_DATA3_LSB)
-#define SI_TX_DATA0_DATA3_SET(x) (((x) << SI_TX_DATA0_DATA3_LSB) & SI_TX_DATA0_DATA3_MASK)
-#define SI_TX_DATA0_DATA2_MSB 23
-#define SI_TX_DATA0_DATA2_LSB 16
-#define SI_TX_DATA0_DATA2_MASK 0x00ff0000
-#define SI_TX_DATA0_DATA2_GET(x) (((x) & SI_TX_DATA0_DATA2_MASK) >> SI_TX_DATA0_DATA2_LSB)
-#define SI_TX_DATA0_DATA2_SET(x) (((x) << SI_TX_DATA0_DATA2_LSB) & SI_TX_DATA0_DATA2_MASK)
-#define SI_TX_DATA0_DATA1_MSB 15
-#define SI_TX_DATA0_DATA1_LSB 8
-#define SI_TX_DATA0_DATA1_MASK 0x0000ff00
-#define SI_TX_DATA0_DATA1_GET(x) (((x) & SI_TX_DATA0_DATA1_MASK) >> SI_TX_DATA0_DATA1_LSB)
-#define SI_TX_DATA0_DATA1_SET(x) (((x) << SI_TX_DATA0_DATA1_LSB) & SI_TX_DATA0_DATA1_MASK)
-#define SI_TX_DATA0_DATA0_MSB 7
-#define SI_TX_DATA0_DATA0_LSB 0
-#define SI_TX_DATA0_DATA0_MASK 0x000000ff
-#define SI_TX_DATA0_DATA0_GET(x) (((x) & SI_TX_DATA0_DATA0_MASK) >> SI_TX_DATA0_DATA0_LSB)
-#define SI_TX_DATA0_DATA0_SET(x) (((x) << SI_TX_DATA0_DATA0_LSB) & SI_TX_DATA0_DATA0_MASK)
-
-#define SI_TX_DATA1_ADDRESS 0x0000000c
-#define SI_TX_DATA1_OFFSET 0x0000000c
-#define SI_TX_DATA1_DATA7_MSB 31
-#define SI_TX_DATA1_DATA7_LSB 24
-#define SI_TX_DATA1_DATA7_MASK 0xff000000
-#define SI_TX_DATA1_DATA7_GET(x) (((x) & SI_TX_DATA1_DATA7_MASK) >> SI_TX_DATA1_DATA7_LSB)
-#define SI_TX_DATA1_DATA7_SET(x) (((x) << SI_TX_DATA1_DATA7_LSB) & SI_TX_DATA1_DATA7_MASK)
-#define SI_TX_DATA1_DATA6_MSB 23
-#define SI_TX_DATA1_DATA6_LSB 16
-#define SI_TX_DATA1_DATA6_MASK 0x00ff0000
-#define SI_TX_DATA1_DATA6_GET(x) (((x) & SI_TX_DATA1_DATA6_MASK) >> SI_TX_DATA1_DATA6_LSB)
-#define SI_TX_DATA1_DATA6_SET(x) (((x) << SI_TX_DATA1_DATA6_LSB) & SI_TX_DATA1_DATA6_MASK)
-#define SI_TX_DATA1_DATA5_MSB 15
-#define SI_TX_DATA1_DATA5_LSB 8
-#define SI_TX_DATA1_DATA5_MASK 0x0000ff00
-#define SI_TX_DATA1_DATA5_GET(x) (((x) & SI_TX_DATA1_DATA5_MASK) >> SI_TX_DATA1_DATA5_LSB)
-#define SI_TX_DATA1_DATA5_SET(x) (((x) << SI_TX_DATA1_DATA5_LSB) & SI_TX_DATA1_DATA5_MASK)
-#define SI_TX_DATA1_DATA4_MSB 7
-#define SI_TX_DATA1_DATA4_LSB 0
-#define SI_TX_DATA1_DATA4_MASK 0x000000ff
-#define SI_TX_DATA1_DATA4_GET(x) (((x) & SI_TX_DATA1_DATA4_MASK) >> SI_TX_DATA1_DATA4_LSB)
-#define SI_TX_DATA1_DATA4_SET(x) (((x) << SI_TX_DATA1_DATA4_LSB) & SI_TX_DATA1_DATA4_MASK)
-
-#define SI_RX_DATA0_ADDRESS 0x00000010
-#define SI_RX_DATA0_OFFSET 0x00000010
-#define SI_RX_DATA0_DATA3_MSB 31
-#define SI_RX_DATA0_DATA3_LSB 24
-#define SI_RX_DATA0_DATA3_MASK 0xff000000
-#define SI_RX_DATA0_DATA3_GET(x) (((x) & SI_RX_DATA0_DATA3_MASK) >> SI_RX_DATA0_DATA3_LSB)
-#define SI_RX_DATA0_DATA3_SET(x) (((x) << SI_RX_DATA0_DATA3_LSB) & SI_RX_DATA0_DATA3_MASK)
-#define SI_RX_DATA0_DATA2_MSB 23
-#define SI_RX_DATA0_DATA2_LSB 16
-#define SI_RX_DATA0_DATA2_MASK 0x00ff0000
-#define SI_RX_DATA0_DATA2_GET(x) (((x) & SI_RX_DATA0_DATA2_MASK) >> SI_RX_DATA0_DATA2_LSB)
-#define SI_RX_DATA0_DATA2_SET(x) (((x) << SI_RX_DATA0_DATA2_LSB) & SI_RX_DATA0_DATA2_MASK)
-#define SI_RX_DATA0_DATA1_MSB 15
-#define SI_RX_DATA0_DATA1_LSB 8
-#define SI_RX_DATA0_DATA1_MASK 0x0000ff00
-#define SI_RX_DATA0_DATA1_GET(x) (((x) & SI_RX_DATA0_DATA1_MASK) >> SI_RX_DATA0_DATA1_LSB)
-#define SI_RX_DATA0_DATA1_SET(x) (((x) << SI_RX_DATA0_DATA1_LSB) & SI_RX_DATA0_DATA1_MASK)
-#define SI_RX_DATA0_DATA0_MSB 7
-#define SI_RX_DATA0_DATA0_LSB 0
-#define SI_RX_DATA0_DATA0_MASK 0x000000ff
-#define SI_RX_DATA0_DATA0_GET(x) (((x) & SI_RX_DATA0_DATA0_MASK) >> SI_RX_DATA0_DATA0_LSB)
-#define SI_RX_DATA0_DATA0_SET(x) (((x) << SI_RX_DATA0_DATA0_LSB) & SI_RX_DATA0_DATA0_MASK)
-
-#define SI_RX_DATA1_ADDRESS 0x00000014
-#define SI_RX_DATA1_OFFSET 0x00000014
-#define SI_RX_DATA1_DATA7_MSB 31
-#define SI_RX_DATA1_DATA7_LSB 24
-#define SI_RX_DATA1_DATA7_MASK 0xff000000
-#define SI_RX_DATA1_DATA7_GET(x) (((x) & SI_RX_DATA1_DATA7_MASK) >> SI_RX_DATA1_DATA7_LSB)
-#define SI_RX_DATA1_DATA7_SET(x) (((x) << SI_RX_DATA1_DATA7_LSB) & SI_RX_DATA1_DATA7_MASK)
-#define SI_RX_DATA1_DATA6_MSB 23
-#define SI_RX_DATA1_DATA6_LSB 16
-#define SI_RX_DATA1_DATA6_MASK 0x00ff0000
-#define SI_RX_DATA1_DATA6_GET(x) (((x) & SI_RX_DATA1_DATA6_MASK) >> SI_RX_DATA1_DATA6_LSB)
-#define SI_RX_DATA1_DATA6_SET(x) (((x) << SI_RX_DATA1_DATA6_LSB) & SI_RX_DATA1_DATA6_MASK)
-#define SI_RX_DATA1_DATA5_MSB 15
-#define SI_RX_DATA1_DATA5_LSB 8
-#define SI_RX_DATA1_DATA5_MASK 0x0000ff00
-#define SI_RX_DATA1_DATA5_GET(x) (((x) & SI_RX_DATA1_DATA5_MASK) >> SI_RX_DATA1_DATA5_LSB)
-#define SI_RX_DATA1_DATA5_SET(x) (((x) << SI_RX_DATA1_DATA5_LSB) & SI_RX_DATA1_DATA5_MASK)
-#define SI_RX_DATA1_DATA4_MSB 7
-#define SI_RX_DATA1_DATA4_LSB 0
-#define SI_RX_DATA1_DATA4_MASK 0x000000ff
-#define SI_RX_DATA1_DATA4_GET(x) (((x) & SI_RX_DATA1_DATA4_MASK) >> SI_RX_DATA1_DATA4_LSB)
-#define SI_RX_DATA1_DATA4_SET(x) (((x) << SI_RX_DATA1_DATA4_LSB) & SI_RX_DATA1_DATA4_MASK)
-
-
-#ifndef __ASSEMBLER__
-
-typedef struct si_reg_reg_s {
- volatile unsigned int si_config;
- volatile unsigned int si_cs;
- volatile unsigned int si_tx_data0;
- volatile unsigned int si_tx_data1;
- volatile unsigned int si_rx_data0;
- volatile unsigned int si_rx_data1;
-} si_reg_reg_t;
-
-#endif /* __ASSEMBLER__ */
-
-#endif /* _SI_REG_H_ */
diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/uart_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/uart_reg.h
index a8eccaf..302b20b 100644
--- a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/uart_reg.h
+++ b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/uart_reg.h
@@ -24,107 +24,6 @@
#ifndef _UART_REG_REG_H_
#define _UART_REG_REG_H_
-#define UART_DATA_ADDRESS 0x00000000
-#define UART_DATA_OFFSET 0x00000000
-#define UART_DATA_TX_CSR_MSB 9
-#define UART_DATA_TX_CSR_LSB 9
-#define UART_DATA_TX_CSR_MASK 0x00000200
-#define UART_DATA_TX_CSR_GET(x) (((x) & UART_DATA_TX_CSR_MASK) >> UART_DATA_TX_CSR_LSB)
-#define UART_DATA_TX_CSR_SET(x) (((x) << UART_DATA_TX_CSR_LSB) & UART_DATA_TX_CSR_MASK)
-#define UART_DATA_RX_CSR_MSB 8
-#define UART_DATA_RX_CSR_LSB 8
-#define UART_DATA_RX_CSR_MASK 0x00000100
-#define UART_DATA_RX_CSR_GET(x) (((x) & UART_DATA_RX_CSR_MASK) >> UART_DATA_RX_CSR_LSB)
-#define UART_DATA_RX_CSR_SET(x) (((x) << UART_DATA_RX_CSR_LSB) & UART_DATA_RX_CSR_MASK)
-#define UART_DATA_TXRX_DATA_MSB 7
-#define UART_DATA_TXRX_DATA_LSB 0
-#define UART_DATA_TXRX_DATA_MASK 0x000000ff
-#define UART_DATA_TXRX_DATA_GET(x) (((x) & UART_DATA_TXRX_DATA_MASK) >> UART_DATA_TXRX_DATA_LSB)
-#define UART_DATA_TXRX_DATA_SET(x) (((x) << UART_DATA_TXRX_DATA_LSB) & UART_DATA_TXRX_DATA_MASK)
-
-#define UART_CONTROL_ADDRESS 0x00000004
-#define UART_CONTROL_OFFSET 0x00000004
-#define UART_CONTROL_RX_BUSY_MSB 15
-#define UART_CONTROL_RX_BUSY_LSB 15
-#define UART_CONTROL_RX_BUSY_MASK 0x00008000
-#define UART_CONTROL_RX_BUSY_GET(x) (((x) & UART_CONTROL_RX_BUSY_MASK) >> UART_CONTROL_RX_BUSY_LSB)
-#define UART_CONTROL_RX_BUSY_SET(x) (((x) << UART_CONTROL_RX_BUSY_LSB) & UART_CONTROL_RX_BUSY_MASK)
-#define UART_CONTROL_TX_BUSY_MSB 14
-#define UART_CONTROL_TX_BUSY_LSB 14
-#define UART_CONTROL_TX_BUSY_MASK 0x00004000
-#define UART_CONTROL_TX_BUSY_GET(x) (((x) & UART_CONTROL_TX_BUSY_MASK) >> UART_CONTROL_TX_BUSY_LSB)
-#define UART_CONTROL_TX_BUSY_SET(x) (((x) << UART_CONTROL_TX_BUSY_LSB) & UART_CONTROL_TX_BUSY_MASK)
-#define UART_CONTROL_HOST_INT_ENABLE_MSB 13
-#define UART_CONTROL_HOST_INT_ENABLE_LSB 13
-#define UART_CONTROL_HOST_INT_ENABLE_MASK 0x00002000
-#define UART_CONTROL_HOST_INT_ENABLE_GET(x) (((x) & UART_CONTROL_HOST_INT_ENABLE_MASK) >> UART_CONTROL_HOST_INT_ENABLE_LSB)
-#define UART_CONTROL_HOST_INT_ENABLE_SET(x) (((x) << UART_CONTROL_HOST_INT_ENABLE_LSB) & UART_CONTROL_HOST_INT_ENABLE_MASK)
-#define UART_CONTROL_HOST_INT_MSB 12
-#define UART_CONTROL_HOST_INT_LSB 12
-#define UART_CONTROL_HOST_INT_MASK 0x00001000
-#define UART_CONTROL_HOST_INT_GET(x) (((x) & UART_CONTROL_HOST_INT_MASK) >> UART_CONTROL_HOST_INT_LSB)
-#define UART_CONTROL_HOST_INT_SET(x) (((x) << UART_CONTROL_HOST_INT_LSB) & UART_CONTROL_HOST_INT_MASK)
-#define UART_CONTROL_TX_BREAK_MSB 11
-#define UART_CONTROL_TX_BREAK_LSB 11
-#define UART_CONTROL_TX_BREAK_MASK 0x00000800
-#define UART_CONTROL_TX_BREAK_GET(x) (((x) & UART_CONTROL_TX_BREAK_MASK) >> UART_CONTROL_TX_BREAK_LSB)
-#define UART_CONTROL_TX_BREAK_SET(x) (((x) << UART_CONTROL_TX_BREAK_LSB) & UART_CONTROL_TX_BREAK_MASK)
-#define UART_CONTROL_RX_BREAK_MSB 10
-#define UART_CONTROL_RX_BREAK_LSB 10
-#define UART_CONTROL_RX_BREAK_MASK 0x00000400
-#define UART_CONTROL_RX_BREAK_GET(x) (((x) & UART_CONTROL_RX_BREAK_MASK) >> UART_CONTROL_RX_BREAK_LSB)
-#define UART_CONTROL_RX_BREAK_SET(x) (((x) << UART_CONTROL_RX_BREAK_LSB) & UART_CONTROL_RX_BREAK_MASK)
-#define UART_CONTROL_SERIAL_TX_READY_MSB 9
-#define UART_CONTROL_SERIAL_TX_READY_LSB 9
-#define UART_CONTROL_SERIAL_TX_READY_MASK 0x00000200
-#define UART_CONTROL_SERIAL_TX_READY_GET(x) (((x) & UART_CONTROL_SERIAL_TX_READY_MASK) >> UART_CONTROL_SERIAL_TX_READY_LSB)
-#define UART_CONTROL_SERIAL_TX_READY_SET(x) (((x) << UART_CONTROL_SERIAL_TX_READY_LSB) & UART_CONTROL_SERIAL_TX_READY_MASK)
-#define UART_CONTROL_TX_READY_ORIDE_MSB 8
-#define UART_CONTROL_TX_READY_ORIDE_LSB 8
-#define UART_CONTROL_TX_READY_ORIDE_MASK 0x00000100
-#define UART_CONTROL_TX_READY_ORIDE_GET(x) (((x) & UART_CONTROL_TX_READY_ORIDE_MASK) >> UART_CONTROL_TX_READY_ORIDE_LSB)
-#define UART_CONTROL_TX_READY_ORIDE_SET(x) (((x) << UART_CONTROL_TX_READY_ORIDE_LSB) & UART_CONTROL_TX_READY_ORIDE_MASK)
-#define UART_CONTROL_RX_READY_ORIDE_MSB 7
-#define UART_CONTROL_RX_READY_ORIDE_LSB 7
-#define UART_CONTROL_RX_READY_ORIDE_MASK 0x00000080
-#define UART_CONTROL_RX_READY_ORIDE_GET(x) (((x) & UART_CONTROL_RX_READY_ORIDE_MASK) >> UART_CONTROL_RX_READY_ORIDE_LSB)
-#define UART_CONTROL_RX_READY_ORIDE_SET(x) (((x) << UART_CONTROL_RX_READY_ORIDE_LSB) & UART_CONTROL_RX_READY_ORIDE_MASK)
-#define UART_CONTROL_DMA_ENABLE_MSB 6
-#define UART_CONTROL_DMA_ENABLE_LSB 6
-#define UART_CONTROL_DMA_ENABLE_MASK 0x00000040
-#define UART_CONTROL_DMA_ENABLE_GET(x) (((x) & UART_CONTROL_DMA_ENABLE_MASK) >> UART_CONTROL_DMA_ENABLE_LSB)
-#define UART_CONTROL_DMA_ENABLE_SET(x) (((x) << UART_CONTROL_DMA_ENABLE_LSB) & UART_CONTROL_DMA_ENABLE_MASK)
-#define UART_CONTROL_FLOW_ENABLE_MSB 5
-#define UART_CONTROL_FLOW_ENABLE_LSB 5
-#define UART_CONTROL_FLOW_ENABLE_MASK 0x00000020
-#define UART_CONTROL_FLOW_ENABLE_GET(x) (((x) & UART_CONTROL_FLOW_ENABLE_MASK) >> UART_CONTROL_FLOW_ENABLE_LSB)
-#define UART_CONTROL_FLOW_ENABLE_SET(x) (((x) << UART_CONTROL_FLOW_ENABLE_LSB) & UART_CONTROL_FLOW_ENABLE_MASK)
-#define UART_CONTROL_FLOW_INVERT_MSB 4
-#define UART_CONTROL_FLOW_INVERT_LSB 4
-#define UART_CONTROL_FLOW_INVERT_MASK 0x00000010
-#define UART_CONTROL_FLOW_INVERT_GET(x) (((x) & UART_CONTROL_FLOW_INVERT_MASK) >> UART_CONTROL_FLOW_INVERT_LSB)
-#define UART_CONTROL_FLOW_INVERT_SET(x) (((x) << UART_CONTROL_FLOW_INVERT_LSB) & UART_CONTROL_FLOW_INVERT_MASK)
-#define UART_CONTROL_IFC_ENABLE_MSB 3
-#define UART_CONTROL_IFC_ENABLE_LSB 3
-#define UART_CONTROL_IFC_ENABLE_MASK 0x00000008
-#define UART_CONTROL_IFC_ENABLE_GET(x) (((x) & UART_CONTROL_IFC_ENABLE_MASK) >> UART_CONTROL_IFC_ENABLE_LSB)
-#define UART_CONTROL_IFC_ENABLE_SET(x) (((x) << UART_CONTROL_IFC_ENABLE_LSB) & UART_CONTROL_IFC_ENABLE_MASK)
-#define UART_CONTROL_IFC_DCE_MSB 2
-#define UART_CONTROL_IFC_DCE_LSB 2
-#define UART_CONTROL_IFC_DCE_MASK 0x00000004
-#define UART_CONTROL_IFC_DCE_GET(x) (((x) & UART_CONTROL_IFC_DCE_MASK) >> UART_CONTROL_IFC_DCE_LSB)
-#define UART_CONTROL_IFC_DCE_SET(x) (((x) << UART_CONTROL_IFC_DCE_LSB) & UART_CONTROL_IFC_DCE_MASK)
-#define UART_CONTROL_PARITY_ENABLE_MSB 1
-#define UART_CONTROL_PARITY_ENABLE_LSB 1
-#define UART_CONTROL_PARITY_ENABLE_MASK 0x00000002
-#define UART_CONTROL_PARITY_ENABLE_GET(x) (((x) & UART_CONTROL_PARITY_ENABLE_MASK) >> UART_CONTROL_PARITY_ENABLE_LSB)
-#define UART_CONTROL_PARITY_ENABLE_SET(x) (((x) << UART_CONTROL_PARITY_ENABLE_LSB) & UART_CONTROL_PARITY_ENABLE_MASK)
-#define UART_CONTROL_PARITY_EVEN_MSB 0
-#define UART_CONTROL_PARITY_EVEN_LSB 0
-#define UART_CONTROL_PARITY_EVEN_MASK 0x00000001
-#define UART_CONTROL_PARITY_EVEN_GET(x) (((x) & UART_CONTROL_PARITY_EVEN_MASK) >> UART_CONTROL_PARITY_EVEN_LSB)
-#define UART_CONTROL_PARITY_EVEN_SET(x) (((x) << UART_CONTROL_PARITY_EVEN_LSB) & UART_CONTROL_PARITY_EVEN_MASK)
-
#define UART_CLKDIV_ADDRESS 0x00000008
#define UART_CLKDIV_OFFSET 0x00000008
#define UART_CLKDIV_CLK_SCALE_MSB 23
@@ -138,123 +37,4 @@
#define UART_CLKDIV_CLK_STEP_GET(x) (((x) & UART_CLKDIV_CLK_STEP_MASK) >> UART_CLKDIV_CLK_STEP_LSB)
#define UART_CLKDIV_CLK_STEP_SET(x) (((x) << UART_CLKDIV_CLK_STEP_LSB) & UART_CLKDIV_CLK_STEP_MASK)
-#define UART_INT_ADDRESS 0x0000000c
-#define UART_INT_OFFSET 0x0000000c
-#define UART_INT_TX_EMPTY_INT_MSB 9
-#define UART_INT_TX_EMPTY_INT_LSB 9
-#define UART_INT_TX_EMPTY_INT_MASK 0x00000200
-#define UART_INT_TX_EMPTY_INT_GET(x) (((x) & UART_INT_TX_EMPTY_INT_MASK) >> UART_INT_TX_EMPTY_INT_LSB)
-#define UART_INT_TX_EMPTY_INT_SET(x) (((x) << UART_INT_TX_EMPTY_INT_LSB) & UART_INT_TX_EMPTY_INT_MASK)
-#define UART_INT_RX_FULL_INT_MSB 8
-#define UART_INT_RX_FULL_INT_LSB 8
-#define UART_INT_RX_FULL_INT_MASK 0x00000100
-#define UART_INT_RX_FULL_INT_GET(x) (((x) & UART_INT_RX_FULL_INT_MASK) >> UART_INT_RX_FULL_INT_LSB)
-#define UART_INT_RX_FULL_INT_SET(x) (((x) << UART_INT_RX_FULL_INT_LSB) & UART_INT_RX_FULL_INT_MASK)
-#define UART_INT_RX_BREAK_OFF_INT_MSB 7
-#define UART_INT_RX_BREAK_OFF_INT_LSB 7
-#define UART_INT_RX_BREAK_OFF_INT_MASK 0x00000080
-#define UART_INT_RX_BREAK_OFF_INT_GET(x) (((x) & UART_INT_RX_BREAK_OFF_INT_MASK) >> UART_INT_RX_BREAK_OFF_INT_LSB)
-#define UART_INT_RX_BREAK_OFF_INT_SET(x) (((x) << UART_INT_RX_BREAK_OFF_INT_LSB) & UART_INT_RX_BREAK_OFF_INT_MASK)
-#define UART_INT_RX_BREAK_ON_INT_MSB 6
-#define UART_INT_RX_BREAK_ON_INT_LSB 6
-#define UART_INT_RX_BREAK_ON_INT_MASK 0x00000040
-#define UART_INT_RX_BREAK_ON_INT_GET(x) (((x) & UART_INT_RX_BREAK_ON_INT_MASK) >> UART_INT_RX_BREAK_ON_INT_LSB)
-#define UART_INT_RX_BREAK_ON_INT_SET(x) (((x) << UART_INT_RX_BREAK_ON_INT_LSB) & UART_INT_RX_BREAK_ON_INT_MASK)
-#define UART_INT_RX_PARITY_ERR_INT_MSB 5
-#define UART_INT_RX_PARITY_ERR_INT_LSB 5
-#define UART_INT_RX_PARITY_ERR_INT_MASK 0x00000020
-#define UART_INT_RX_PARITY_ERR_INT_GET(x) (((x) & UART_INT_RX_PARITY_ERR_INT_MASK) >> UART_INT_RX_PARITY_ERR_INT_LSB)
-#define UART_INT_RX_PARITY_ERR_INT_SET(x) (((x) << UART_INT_RX_PARITY_ERR_INT_LSB) & UART_INT_RX_PARITY_ERR_INT_MASK)
-#define UART_INT_TX_OFLOW_ERR_INT_MSB 4
-#define UART_INT_TX_OFLOW_ERR_INT_LSB 4
-#define UART_INT_TX_OFLOW_ERR_INT_MASK 0x00000010
-#define UART_INT_TX_OFLOW_ERR_INT_GET(x) (((x) & UART_INT_TX_OFLOW_ERR_INT_MASK) >> UART_INT_TX_OFLOW_ERR_INT_LSB)
-#define UART_INT_TX_OFLOW_ERR_INT_SET(x) (((x) << UART_INT_TX_OFLOW_ERR_INT_LSB) & UART_INT_TX_OFLOW_ERR_INT_MASK)
-#define UART_INT_RX_OFLOW_ERR_INT_MSB 3
-#define UART_INT_RX_OFLOW_ERR_INT_LSB 3
-#define UART_INT_RX_OFLOW_ERR_INT_MASK 0x00000008
-#define UART_INT_RX_OFLOW_ERR_INT_GET(x) (((x) & UART_INT_RX_OFLOW_ERR_INT_MASK) >> UART_INT_RX_OFLOW_ERR_INT_LSB)
-#define UART_INT_RX_OFLOW_ERR_INT_SET(x) (((x) << UART_INT_RX_OFLOW_ERR_INT_LSB) & UART_INT_RX_OFLOW_ERR_INT_MASK)
-#define UART_INT_RX_FRAMING_ERR_INT_MSB 2
-#define UART_INT_RX_FRAMING_ERR_INT_LSB 2
-#define UART_INT_RX_FRAMING_ERR_INT_MASK 0x00000004
-#define UART_INT_RX_FRAMING_ERR_INT_GET(x) (((x) & UART_INT_RX_FRAMING_ERR_INT_MASK) >> UART_INT_RX_FRAMING_ERR_INT_LSB)
-#define UART_INT_RX_FRAMING_ERR_INT_SET(x) (((x) << UART_INT_RX_FRAMING_ERR_INT_LSB) & UART_INT_RX_FRAMING_ERR_INT_MASK)
-#define UART_INT_TX_READY_INT_MSB 1
-#define UART_INT_TX_READY_INT_LSB 1
-#define UART_INT_TX_READY_INT_MASK 0x00000002
-#define UART_INT_TX_READY_INT_GET(x) (((x) & UART_INT_TX_READY_INT_MASK) >> UART_INT_TX_READY_INT_LSB)
-#define UART_INT_TX_READY_INT_SET(x) (((x) << UART_INT_TX_READY_INT_LSB) & UART_INT_TX_READY_INT_MASK)
-#define UART_INT_RX_VALID_INT_MSB 0
-#define UART_INT_RX_VALID_INT_LSB 0
-#define UART_INT_RX_VALID_INT_MASK 0x00000001
-#define UART_INT_RX_VALID_INT_GET(x) (((x) & UART_INT_RX_VALID_INT_MASK) >> UART_INT_RX_VALID_INT_LSB)
-#define UART_INT_RX_VALID_INT_SET(x) (((x) << UART_INT_RX_VALID_INT_LSB) & UART_INT_RX_VALID_INT_MASK)
-
-#define UART_INT_EN_ADDRESS 0x00000010
-#define UART_INT_EN_OFFSET 0x00000010
-#define UART_INT_EN_TX_EMPTY_INT_EN_MSB 9
-#define UART_INT_EN_TX_EMPTY_INT_EN_LSB 9
-#define UART_INT_EN_TX_EMPTY_INT_EN_MASK 0x00000200
-#define UART_INT_EN_TX_EMPTY_INT_EN_GET(x) (((x) & UART_INT_EN_TX_EMPTY_INT_EN_MASK) >> UART_INT_EN_TX_EMPTY_INT_EN_LSB)
-#define UART_INT_EN_TX_EMPTY_INT_EN_SET(x) (((x) << UART_INT_EN_TX_EMPTY_INT_EN_LSB) & UART_INT_EN_TX_EMPTY_INT_EN_MASK)
-#define UART_INT_EN_RX_FULL_INT_EN_MSB 8
-#define UART_INT_EN_RX_FULL_INT_EN_LSB 8
-#define UART_INT_EN_RX_FULL_INT_EN_MASK 0x00000100
-#define UART_INT_EN_RX_FULL_INT_EN_GET(x) (((x) & UART_INT_EN_RX_FULL_INT_EN_MASK) >> UART_INT_EN_RX_FULL_INT_EN_LSB)
-#define UART_INT_EN_RX_FULL_INT_EN_SET(x) (((x) << UART_INT_EN_RX_FULL_INT_EN_LSB) & UART_INT_EN_RX_FULL_INT_EN_MASK)
-#define UART_INT_EN_RX_BREAK_OFF_INT_EN_MSB 7
-#define UART_INT_EN_RX_BREAK_OFF_INT_EN_LSB 7
-#define UART_INT_EN_RX_BREAK_OFF_INT_EN_MASK 0x00000080
-#define UART_INT_EN_RX_BREAK_OFF_INT_EN_GET(x) (((x) & UART_INT_EN_RX_BREAK_OFF_INT_EN_MASK) >> UART_INT_EN_RX_BREAK_OFF_INT_EN_LSB)
-#define UART_INT_EN_RX_BREAK_OFF_INT_EN_SET(x) (((x) << UART_INT_EN_RX_BREAK_OFF_INT_EN_LSB) & UART_INT_EN_RX_BREAK_OFF_INT_EN_MASK)
-#define UART_INT_EN_RX_BREAK_ON_INT_EN_MSB 6
-#define UART_INT_EN_RX_BREAK_ON_INT_EN_LSB 6
-#define UART_INT_EN_RX_BREAK_ON_INT_EN_MASK 0x00000040
-#define UART_INT_EN_RX_BREAK_ON_INT_EN_GET(x) (((x) & UART_INT_EN_RX_BREAK_ON_INT_EN_MASK) >> UART_INT_EN_RX_BREAK_ON_INT_EN_LSB)
-#define UART_INT_EN_RX_BREAK_ON_INT_EN_SET(x) (((x) << UART_INT_EN_RX_BREAK_ON_INT_EN_LSB) & UART_INT_EN_RX_BREAK_ON_INT_EN_MASK)
-#define UART_INT_EN_RX_PARITY_ERR_INT_EN_MSB 5
-#define UART_INT_EN_RX_PARITY_ERR_INT_EN_LSB 5
-#define UART_INT_EN_RX_PARITY_ERR_INT_EN_MASK 0x00000020
-#define UART_INT_EN_RX_PARITY_ERR_INT_EN_GET(x) (((x) & UART_INT_EN_RX_PARITY_ERR_INT_EN_MASK) >> UART_INT_EN_RX_PARITY_ERR_INT_EN_LSB)
-#define UART_INT_EN_RX_PARITY_ERR_INT_EN_SET(x) (((x) << UART_INT_EN_RX_PARITY_ERR_INT_EN_LSB) & UART_INT_EN_RX_PARITY_ERR_INT_EN_MASK)
-#define UART_INT_EN_TX_OFLOW_ERR_INT_EN_MSB 4
-#define UART_INT_EN_TX_OFLOW_ERR_INT_EN_LSB 4
-#define UART_INT_EN_TX_OFLOW_ERR_INT_EN_MASK 0x00000010
-#define UART_INT_EN_TX_OFLOW_ERR_INT_EN_GET(x) (((x) & UART_INT_EN_TX_OFLOW_ERR_INT_EN_MASK) >> UART_INT_EN_TX_OFLOW_ERR_INT_EN_LSB)
-#define UART_INT_EN_TX_OFLOW_ERR_INT_EN_SET(x) (((x) << UART_INT_EN_TX_OFLOW_ERR_INT_EN_LSB) & UART_INT_EN_TX_OFLOW_ERR_INT_EN_MASK)
-#define UART_INT_EN_RX_OFLOW_ERR_INT_EN_MSB 3
-#define UART_INT_EN_RX_OFLOW_ERR_INT_EN_LSB 3
-#define UART_INT_EN_RX_OFLOW_ERR_INT_EN_MASK 0x00000008
-#define UART_INT_EN_RX_OFLOW_ERR_INT_EN_GET(x) (((x) & UART_INT_EN_RX_OFLOW_ERR_INT_EN_MASK) >> UART_INT_EN_RX_OFLOW_ERR_INT_EN_LSB)
-#define UART_INT_EN_RX_OFLOW_ERR_INT_EN_SET(x) (((x) << UART_INT_EN_RX_OFLOW_ERR_INT_EN_LSB) & UART_INT_EN_RX_OFLOW_ERR_INT_EN_MASK)
-#define UART_INT_EN_RX_FRAMING_ERR_INT_EN_MSB 2
-#define UART_INT_EN_RX_FRAMING_ERR_INT_EN_LSB 2
-#define UART_INT_EN_RX_FRAMING_ERR_INT_EN_MASK 0x00000004
-#define UART_INT_EN_RX_FRAMING_ERR_INT_EN_GET(x) (((x) & UART_INT_EN_RX_FRAMING_ERR_INT_EN_MASK) >> UART_INT_EN_RX_FRAMING_ERR_INT_EN_LSB)
-#define UART_INT_EN_RX_FRAMING_ERR_INT_EN_SET(x) (((x) << UART_INT_EN_RX_FRAMING_ERR_INT_EN_LSB) & UART_INT_EN_RX_FRAMING_ERR_INT_EN_MASK)
-#define UART_INT_EN_TX_READY_INT_EN_MSB 1
-#define UART_INT_EN_TX_READY_INT_EN_LSB 1
-#define UART_INT_EN_TX_READY_INT_EN_MASK 0x00000002
-#define UART_INT_EN_TX_READY_INT_EN_GET(x) (((x) & UART_INT_EN_TX_READY_INT_EN_MASK) >> UART_INT_EN_TX_READY_INT_EN_LSB)
-#define UART_INT_EN_TX_READY_INT_EN_SET(x) (((x) << UART_INT_EN_TX_READY_INT_EN_LSB) & UART_INT_EN_TX_READY_INT_EN_MASK)
-#define UART_INT_EN_RX_VALID_INT_EN_MSB 0
-#define UART_INT_EN_RX_VALID_INT_EN_LSB 0
-#define UART_INT_EN_RX_VALID_INT_EN_MASK 0x00000001
-#define UART_INT_EN_RX_VALID_INT_EN_GET(x) (((x) & UART_INT_EN_RX_VALID_INT_EN_MASK) >> UART_INT_EN_RX_VALID_INT_EN_LSB)
-#define UART_INT_EN_RX_VALID_INT_EN_SET(x) (((x) << UART_INT_EN_RX_VALID_INT_EN_LSB) & UART_INT_EN_RX_VALID_INT_EN_MASK)
-
-
-#ifndef __ASSEMBLER__
-
-typedef struct uart_reg_reg_s {
- volatile unsigned int uart_data;
- volatile unsigned int uart_control;
- volatile unsigned int uart_clkdiv;
- volatile unsigned int uart_int;
- volatile unsigned int uart_int_en;
-} uart_reg_reg_t;
-
-#endif /* __ASSEMBLER__ */
-
#endif /* _UART_REG_H_ */
diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/umbox_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/umbox_reg.h
deleted file mode 100644
index b233cbc..0000000
--- a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/umbox_reg.h
+++ /dev/null
@@ -1,37 +0,0 @@
-// ------------------------------------------------------------------
-// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
-//
-//
-// Permission to use, copy, modify, and/or distribute this software for any
-// purpose with or without fee is hereby granted, provided that the above
-// copyright notice and this permission notice appear in all copies.
-//
-// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-//
-//
-// ------------------------------------------------------------------
-//===================================================================
-// Author(s): ="Atheros"
-//===================================================================
-
-
-#ifdef WLAN_HEADERS
-
-#include "umbox_wlan_reg.h"
-
-
-#ifndef BT_HEADERS
-
-
-
-#endif
-#endif
-
-
-
diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/umbox_wlan_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/umbox_wlan_reg.h
deleted file mode 100644
index 4737a28..0000000
--- a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/umbox_wlan_reg.h
+++ /dev/null
@@ -1,322 +0,0 @@
-// ------------------------------------------------------------------
-// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
-//
-//
-// Permission to use, copy, modify, and/or distribute this software for any
-// purpose with or without fee is hereby granted, provided that the above
-// copyright notice and this permission notice appear in all copies.
-//
-// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-//
-//
-// ------------------------------------------------------------------
-//===================================================================
-// Author(s): ="Atheros"
-//===================================================================
-
-
-#ifndef _UMBOX_WLAN_REG_REG_H_
-#define _UMBOX_WLAN_REG_REG_H_
-
-#define UMBOX_FIFO_ADDRESS 0x00000000
-#define UMBOX_FIFO_OFFSET 0x00000000
-#define UMBOX_FIFO_DATA_MSB 8
-#define UMBOX_FIFO_DATA_LSB 0
-#define UMBOX_FIFO_DATA_MASK 0x000001ff
-#define UMBOX_FIFO_DATA_GET(x) (((x) & UMBOX_FIFO_DATA_MASK) >> UMBOX_FIFO_DATA_LSB)
-#define UMBOX_FIFO_DATA_SET(x) (((x) << UMBOX_FIFO_DATA_LSB) & UMBOX_FIFO_DATA_MASK)
-
-#define UMBOX_FIFO_STATUS_ADDRESS 0x00000008
-#define UMBOX_FIFO_STATUS_OFFSET 0x00000008
-#define UMBOX_FIFO_STATUS_TX_EMPTY_MSB 3
-#define UMBOX_FIFO_STATUS_TX_EMPTY_LSB 3
-#define UMBOX_FIFO_STATUS_TX_EMPTY_MASK 0x00000008
-#define UMBOX_FIFO_STATUS_TX_EMPTY_GET(x) (((x) & UMBOX_FIFO_STATUS_TX_EMPTY_MASK) >> UMBOX_FIFO_STATUS_TX_EMPTY_LSB)
-#define UMBOX_FIFO_STATUS_TX_EMPTY_SET(x) (((x) << UMBOX_FIFO_STATUS_TX_EMPTY_LSB) & UMBOX_FIFO_STATUS_TX_EMPTY_MASK)
-#define UMBOX_FIFO_STATUS_TX_FULL_MSB 2
-#define UMBOX_FIFO_STATUS_TX_FULL_LSB 2
-#define UMBOX_FIFO_STATUS_TX_FULL_MASK 0x00000004
-#define UMBOX_FIFO_STATUS_TX_FULL_GET(x) (((x) & UMBOX_FIFO_STATUS_TX_FULL_MASK) >> UMBOX_FIFO_STATUS_TX_FULL_LSB)
-#define UMBOX_FIFO_STATUS_TX_FULL_SET(x) (((x) << UMBOX_FIFO_STATUS_TX_FULL_LSB) & UMBOX_FIFO_STATUS_TX_FULL_MASK)
-#define UMBOX_FIFO_STATUS_RX_EMPTY_MSB 1
-#define UMBOX_FIFO_STATUS_RX_EMPTY_LSB 1
-#define UMBOX_FIFO_STATUS_RX_EMPTY_MASK 0x00000002
-#define UMBOX_FIFO_STATUS_RX_EMPTY_GET(x) (((x) & UMBOX_FIFO_STATUS_RX_EMPTY_MASK) >> UMBOX_FIFO_STATUS_RX_EMPTY_LSB)
-#define UMBOX_FIFO_STATUS_RX_EMPTY_SET(x) (((x) << UMBOX_FIFO_STATUS_RX_EMPTY_LSB) & UMBOX_FIFO_STATUS_RX_EMPTY_MASK)
-#define UMBOX_FIFO_STATUS_RX_FULL_MSB 0
-#define UMBOX_FIFO_STATUS_RX_FULL_LSB 0
-#define UMBOX_FIFO_STATUS_RX_FULL_MASK 0x00000001
-#define UMBOX_FIFO_STATUS_RX_FULL_GET(x) (((x) & UMBOX_FIFO_STATUS_RX_FULL_MASK) >> UMBOX_FIFO_STATUS_RX_FULL_LSB)
-#define UMBOX_FIFO_STATUS_RX_FULL_SET(x) (((x) << UMBOX_FIFO_STATUS_RX_FULL_LSB) & UMBOX_FIFO_STATUS_RX_FULL_MASK)
-
-#define UMBOX_DMA_POLICY_ADDRESS 0x0000000c
-#define UMBOX_DMA_POLICY_OFFSET 0x0000000c
-#define UMBOX_DMA_POLICY_TX_QUANTUM_MSB 3
-#define UMBOX_DMA_POLICY_TX_QUANTUM_LSB 3
-#define UMBOX_DMA_POLICY_TX_QUANTUM_MASK 0x00000008
-#define UMBOX_DMA_POLICY_TX_QUANTUM_GET(x) (((x) & UMBOX_DMA_POLICY_TX_QUANTUM_MASK) >> UMBOX_DMA_POLICY_TX_QUANTUM_LSB)
-#define UMBOX_DMA_POLICY_TX_QUANTUM_SET(x) (((x) << UMBOX_DMA_POLICY_TX_QUANTUM_LSB) & UMBOX_DMA_POLICY_TX_QUANTUM_MASK)
-#define UMBOX_DMA_POLICY_TX_ORDER_MSB 2
-#define UMBOX_DMA_POLICY_TX_ORDER_LSB 2
-#define UMBOX_DMA_POLICY_TX_ORDER_MASK 0x00000004
-#define UMBOX_DMA_POLICY_TX_ORDER_GET(x) (((x) & UMBOX_DMA_POLICY_TX_ORDER_MASK) >> UMBOX_DMA_POLICY_TX_ORDER_LSB)
-#define UMBOX_DMA_POLICY_TX_ORDER_SET(x) (((x) << UMBOX_DMA_POLICY_TX_ORDER_LSB) & UMBOX_DMA_POLICY_TX_ORDER_MASK)
-#define UMBOX_DMA_POLICY_RX_QUANTUM_MSB 1
-#define UMBOX_DMA_POLICY_RX_QUANTUM_LSB 1
-#define UMBOX_DMA_POLICY_RX_QUANTUM_MASK 0x00000002
-#define UMBOX_DMA_POLICY_RX_QUANTUM_GET(x) (((x) & UMBOX_DMA_POLICY_RX_QUANTUM_MASK) >> UMBOX_DMA_POLICY_RX_QUANTUM_LSB)
-#define UMBOX_DMA_POLICY_RX_QUANTUM_SET(x) (((x) << UMBOX_DMA_POLICY_RX_QUANTUM_LSB) & UMBOX_DMA_POLICY_RX_QUANTUM_MASK)
-#define UMBOX_DMA_POLICY_RX_ORDER_MSB 0
-#define UMBOX_DMA_POLICY_RX_ORDER_LSB 0
-#define UMBOX_DMA_POLICY_RX_ORDER_MASK 0x00000001
-#define UMBOX_DMA_POLICY_RX_ORDER_GET(x) (((x) & UMBOX_DMA_POLICY_RX_ORDER_MASK) >> UMBOX_DMA_POLICY_RX_ORDER_LSB)
-#define UMBOX_DMA_POLICY_RX_ORDER_SET(x) (((x) << UMBOX_DMA_POLICY_RX_ORDER_LSB) & UMBOX_DMA_POLICY_RX_ORDER_MASK)
-
-#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS 0x00000010
-#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_OFFSET 0x00000010
-#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MSB 27
-#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB 2
-#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
-#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK) >> UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB)
-#define UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_LSB) & UMBOX0_DMA_RX_DESCRIPTOR_BASE_ADDRESS_MASK)
-
-#define UMBOX0_DMA_RX_CONTROL_ADDRESS 0x00000014
-#define UMBOX0_DMA_RX_CONTROL_OFFSET 0x00000014
-#define UMBOX0_DMA_RX_CONTROL_RESUME_MSB 2
-#define UMBOX0_DMA_RX_CONTROL_RESUME_LSB 2
-#define UMBOX0_DMA_RX_CONTROL_RESUME_MASK 0x00000004
-#define UMBOX0_DMA_RX_CONTROL_RESUME_GET(x) (((x) & UMBOX0_DMA_RX_CONTROL_RESUME_MASK) >> UMBOX0_DMA_RX_CONTROL_RESUME_LSB)
-#define UMBOX0_DMA_RX_CONTROL_RESUME_SET(x) (((x) << UMBOX0_DMA_RX_CONTROL_RESUME_LSB) & UMBOX0_DMA_RX_CONTROL_RESUME_MASK)
-#define UMBOX0_DMA_RX_CONTROL_START_MSB 1
-#define UMBOX0_DMA_RX_CONTROL_START_LSB 1
-#define UMBOX0_DMA_RX_CONTROL_START_MASK 0x00000002
-#define UMBOX0_DMA_RX_CONTROL_START_GET(x) (((x) & UMBOX0_DMA_RX_CONTROL_START_MASK) >> UMBOX0_DMA_RX_CONTROL_START_LSB)
-#define UMBOX0_DMA_RX_CONTROL_START_SET(x) (((x) << UMBOX0_DMA_RX_CONTROL_START_LSB) & UMBOX0_DMA_RX_CONTROL_START_MASK)
-#define UMBOX0_DMA_RX_CONTROL_STOP_MSB 0
-#define UMBOX0_DMA_RX_CONTROL_STOP_LSB 0
-#define UMBOX0_DMA_RX_CONTROL_STOP_MASK 0x00000001
-#define UMBOX0_DMA_RX_CONTROL_STOP_GET(x) (((x) & UMBOX0_DMA_RX_CONTROL_STOP_MASK) >> UMBOX0_DMA_RX_CONTROL_STOP_LSB)
-#define UMBOX0_DMA_RX_CONTROL_STOP_SET(x) (((x) << UMBOX0_DMA_RX_CONTROL_STOP_LSB) & UMBOX0_DMA_RX_CONTROL_STOP_MASK)
-
-#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS 0x00000018
-#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_OFFSET 0x00000018
-#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MSB 27
-#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB 2
-#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK 0x0ffffffc
-#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_GET(x) (((x) & UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK) >> UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB)
-#define UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_SET(x) (((x) << UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_LSB) & UMBOX0_DMA_TX_DESCRIPTOR_BASE_ADDRESS_MASK)
-
-#define UMBOX0_DMA_TX_CONTROL_ADDRESS 0x0000001c
-#define UMBOX0_DMA_TX_CONTROL_OFFSET 0x0000001c
-#define UMBOX0_DMA_TX_CONTROL_RESUME_MSB 2
-#define UMBOX0_DMA_TX_CONTROL_RESUME_LSB 2
-#define UMBOX0_DMA_TX_CONTROL_RESUME_MASK 0x00000004
-#define UMBOX0_DMA_TX_CONTROL_RESUME_GET(x) (((x) & UMBOX0_DMA_TX_CONTROL_RESUME_MASK) >> UMBOX0_DMA_TX_CONTROL_RESUME_LSB)
-#define UMBOX0_DMA_TX_CONTROL_RESUME_SET(x) (((x) << UMBOX0_DMA_TX_CONTROL_RESUME_LSB) & UMBOX0_DMA_TX_CONTROL_RESUME_MASK)
-#define UMBOX0_DMA_TX_CONTROL_START_MSB 1
-#define UMBOX0_DMA_TX_CONTROL_START_LSB 1
-#define UMBOX0_DMA_TX_CONTROL_START_MASK 0x00000002
-#define UMBOX0_DMA_TX_CONTROL_START_GET(x) (((x) & UMBOX0_DMA_TX_CONTROL_START_MASK) >> UMBOX0_DMA_TX_CONTROL_START_LSB)
-#define UMBOX0_DMA_TX_CONTROL_START_SET(x) (((x) << UMBOX0_DMA_TX_CONTROL_START_LSB) & UMBOX0_DMA_TX_CONTROL_START_MASK)
-#define UMBOX0_DMA_TX_CONTROL_STOP_MSB 0
-#define UMBOX0_DMA_TX_CONTROL_STOP_LSB 0
-#define UMBOX0_DMA_TX_CONTROL_STOP_MASK 0x00000001
-#define UMBOX0_DMA_TX_CONTROL_STOP_GET(x) (((x) & UMBOX0_DMA_TX_CONTROL_STOP_MASK) >> UMBOX0_DMA_TX_CONTROL_STOP_LSB)
-#define UMBOX0_DMA_TX_CONTROL_STOP_SET(x) (((x) << UMBOX0_DMA_TX_CONTROL_STOP_LSB) & UMBOX0_DMA_TX_CONTROL_STOP_MASK)
-
-#define UMBOX_FIFO_TIMEOUT_ADDRESS 0x00000020
-#define UMBOX_FIFO_TIMEOUT_OFFSET 0x00000020
-#define UMBOX_FIFO_TIMEOUT_ENABLE_SET_MSB 8
-#define UMBOX_FIFO_TIMEOUT_ENABLE_SET_LSB 8
-#define UMBOX_FIFO_TIMEOUT_ENABLE_SET_MASK 0x00000100
-#define UMBOX_FIFO_TIMEOUT_ENABLE_SET_GET(x) (((x) & UMBOX_FIFO_TIMEOUT_ENABLE_SET_MASK) >> UMBOX_FIFO_TIMEOUT_ENABLE_SET_LSB)
-#define UMBOX_FIFO_TIMEOUT_ENABLE_SET_SET(x) (((x) << UMBOX_FIFO_TIMEOUT_ENABLE_SET_LSB) & UMBOX_FIFO_TIMEOUT_ENABLE_SET_MASK)
-#define UMBOX_FIFO_TIMEOUT_VALUE_MSB 7
-#define UMBOX_FIFO_TIMEOUT_VALUE_LSB 0
-#define UMBOX_FIFO_TIMEOUT_VALUE_MASK 0x000000ff
-#define UMBOX_FIFO_TIMEOUT_VALUE_GET(x) (((x) & UMBOX_FIFO_TIMEOUT_VALUE_MASK) >> UMBOX_FIFO_TIMEOUT_VALUE_LSB)
-#define UMBOX_FIFO_TIMEOUT_VALUE_SET(x) (((x) << UMBOX_FIFO_TIMEOUT_VALUE_LSB) & UMBOX_FIFO_TIMEOUT_VALUE_MASK)
-
-#define UMBOX_INT_STATUS_ADDRESS 0x00000024
-#define UMBOX_INT_STATUS_OFFSET 0x00000024
-#define UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_MSB 9
-#define UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_LSB 9
-#define UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_MASK 0x00000200
-#define UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_GET(x) (((x) & UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_MASK) >> UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_LSB)
-#define UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_SET(x) (((x) << UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_LSB) & UMBOX_INT_STATUS_HCI_FRAMER_UNDERFLOW_MASK)
-#define UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_MSB 8
-#define UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_LSB 8
-#define UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_MASK 0x00000100
-#define UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_GET(x) (((x) & UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_MASK) >> UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_LSB)
-#define UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_SET(x) (((x) << UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_LSB) & UMBOX_INT_STATUS_HCI_FRAMER_OVERFLOW_MASK)
-#define UMBOX_INT_STATUS_RX_DMA_COMPLETE_MSB 7
-#define UMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB 7
-#define UMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK 0x00000080
-#define UMBOX_INT_STATUS_RX_DMA_COMPLETE_GET(x) (((x) & UMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK) >> UMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB)
-#define UMBOX_INT_STATUS_RX_DMA_COMPLETE_SET(x) (((x) << UMBOX_INT_STATUS_RX_DMA_COMPLETE_LSB) & UMBOX_INT_STATUS_RX_DMA_COMPLETE_MASK)
-#define UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MSB 6
-#define UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB 6
-#define UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK 0x00000040
-#define UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_GET(x) (((x) & UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK) >> UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB)
-#define UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_SET(x) (((x) << UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_LSB) & UMBOX_INT_STATUS_TX_DMA_EOM_COMPLETE_MASK)
-#define UMBOX_INT_STATUS_TX_DMA_COMPLETE_MSB 5
-#define UMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB 5
-#define UMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK 0x00000020
-#define UMBOX_INT_STATUS_TX_DMA_COMPLETE_GET(x) (((x) & UMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK) >> UMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB)
-#define UMBOX_INT_STATUS_TX_DMA_COMPLETE_SET(x) (((x) << UMBOX_INT_STATUS_TX_DMA_COMPLETE_LSB) & UMBOX_INT_STATUS_TX_DMA_COMPLETE_MASK)
-#define UMBOX_INT_STATUS_HCI_SYNC_ERROR_MSB 4
-#define UMBOX_INT_STATUS_HCI_SYNC_ERROR_LSB 4
-#define UMBOX_INT_STATUS_HCI_SYNC_ERROR_MASK 0x00000010
-#define UMBOX_INT_STATUS_HCI_SYNC_ERROR_GET(x) (((x) & UMBOX_INT_STATUS_HCI_SYNC_ERROR_MASK) >> UMBOX_INT_STATUS_HCI_SYNC_ERROR_LSB)
-#define UMBOX_INT_STATUS_HCI_SYNC_ERROR_SET(x) (((x) << UMBOX_INT_STATUS_HCI_SYNC_ERROR_LSB) & UMBOX_INT_STATUS_HCI_SYNC_ERROR_MASK)
-#define UMBOX_INT_STATUS_TX_OVERFLOW_MSB 3
-#define UMBOX_INT_STATUS_TX_OVERFLOW_LSB 3
-#define UMBOX_INT_STATUS_TX_OVERFLOW_MASK 0x00000008
-#define UMBOX_INT_STATUS_TX_OVERFLOW_GET(x) (((x) & UMBOX_INT_STATUS_TX_OVERFLOW_MASK) >> UMBOX_INT_STATUS_TX_OVERFLOW_LSB)
-#define UMBOX_INT_STATUS_TX_OVERFLOW_SET(x) (((x) << UMBOX_INT_STATUS_TX_OVERFLOW_LSB) & UMBOX_INT_STATUS_TX_OVERFLOW_MASK)
-#define UMBOX_INT_STATUS_RX_UNDERFLOW_MSB 2
-#define UMBOX_INT_STATUS_RX_UNDERFLOW_LSB 2
-#define UMBOX_INT_STATUS_RX_UNDERFLOW_MASK 0x00000004
-#define UMBOX_INT_STATUS_RX_UNDERFLOW_GET(x) (((x) & UMBOX_INT_STATUS_RX_UNDERFLOW_MASK) >> UMBOX_INT_STATUS_RX_UNDERFLOW_LSB)
-#define UMBOX_INT_STATUS_RX_UNDERFLOW_SET(x) (((x) << UMBOX_INT_STATUS_RX_UNDERFLOW_LSB) & UMBOX_INT_STATUS_RX_UNDERFLOW_MASK)
-#define UMBOX_INT_STATUS_TX_NOT_EMPTY_MSB 1
-#define UMBOX_INT_STATUS_TX_NOT_EMPTY_LSB 1
-#define UMBOX_INT_STATUS_TX_NOT_EMPTY_MASK 0x00000002
-#define UMBOX_INT_STATUS_TX_NOT_EMPTY_GET(x) (((x) & UMBOX_INT_STATUS_TX_NOT_EMPTY_MASK) >> UMBOX_INT_STATUS_TX_NOT_EMPTY_LSB)
-#define UMBOX_INT_STATUS_TX_NOT_EMPTY_SET(x) (((x) << UMBOX_INT_STATUS_TX_NOT_EMPTY_LSB) & UMBOX_INT_STATUS_TX_NOT_EMPTY_MASK)
-#define UMBOX_INT_STATUS_RX_NOT_FULL_MSB 0
-#define UMBOX_INT_STATUS_RX_NOT_FULL_LSB 0
-#define UMBOX_INT_STATUS_RX_NOT_FULL_MASK 0x00000001
-#define UMBOX_INT_STATUS_RX_NOT_FULL_GET(x) (((x) & UMBOX_INT_STATUS_RX_NOT_FULL_MASK) >> UMBOX_INT_STATUS_RX_NOT_FULL_LSB)
-#define UMBOX_INT_STATUS_RX_NOT_FULL_SET(x) (((x) << UMBOX_INT_STATUS_RX_NOT_FULL_LSB) & UMBOX_INT_STATUS_RX_NOT_FULL_MASK)
-
-#define UMBOX_INT_ENABLE_ADDRESS 0x00000028
-#define UMBOX_INT_ENABLE_OFFSET 0x00000028
-#define UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_MSB 9
-#define UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_LSB 9
-#define UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_MASK 0x00000200
-#define UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_GET(x) (((x) & UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_MASK) >> UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_LSB)
-#define UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_SET(x) (((x) << UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_LSB) & UMBOX_INT_ENABLE_HCI_FRAMER_UNDERFLOW_MASK)
-#define UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_MSB 8
-#define UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_LSB 8
-#define UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_MASK 0x00000100
-#define UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_GET(x) (((x) & UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_MASK) >> UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_LSB)
-#define UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_SET(x) (((x) << UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_LSB) & UMBOX_INT_ENABLE_HCI_FRAMER_OVERFLOW_MASK)
-#define UMBOX_INT_ENABLE_RX_DMA_COMPLETE_MSB 7
-#define UMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB 7
-#define UMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK 0x00000080
-#define UMBOX_INT_ENABLE_RX_DMA_COMPLETE_GET(x) (((x) & UMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK) >> UMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB)
-#define UMBOX_INT_ENABLE_RX_DMA_COMPLETE_SET(x) (((x) << UMBOX_INT_ENABLE_RX_DMA_COMPLETE_LSB) & UMBOX_INT_ENABLE_RX_DMA_COMPLETE_MASK)
-#define UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MSB 6
-#define UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB 6
-#define UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK 0x00000040
-#define UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_GET(x) (((x) & UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK) >> UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB)
-#define UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_SET(x) (((x) << UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_LSB) & UMBOX_INT_ENABLE_TX_DMA_EOM_COMPLETE_MASK)
-#define UMBOX_INT_ENABLE_TX_DMA_COMPLETE_MSB 5
-#define UMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB 5
-#define UMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK 0x00000020
-#define UMBOX_INT_ENABLE_TX_DMA_COMPLETE_GET(x) (((x) & UMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK) >> UMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB)
-#define UMBOX_INT_ENABLE_TX_DMA_COMPLETE_SET(x) (((x) << UMBOX_INT_ENABLE_TX_DMA_COMPLETE_LSB) & UMBOX_INT_ENABLE_TX_DMA_COMPLETE_MASK)
-#define UMBOX_INT_ENABLE_HCI_SYNC_ERROR_MSB 4
-#define UMBOX_INT_ENABLE_HCI_SYNC_ERROR_LSB 4
-#define UMBOX_INT_ENABLE_HCI_SYNC_ERROR_MASK 0x00000010
-#define UMBOX_INT_ENABLE_HCI_SYNC_ERROR_GET(x) (((x) & UMBOX_INT_ENABLE_HCI_SYNC_ERROR_MASK) >> UMBOX_INT_ENABLE_HCI_SYNC_ERROR_LSB)
-#define UMBOX_INT_ENABLE_HCI_SYNC_ERROR_SET(x) (((x) << UMBOX_INT_ENABLE_HCI_SYNC_ERROR_LSB) & UMBOX_INT_ENABLE_HCI_SYNC_ERROR_MASK)
-#define UMBOX_INT_ENABLE_TX_OVERFLOW_MSB 3
-#define UMBOX_INT_ENABLE_TX_OVERFLOW_LSB 3
-#define UMBOX_INT_ENABLE_TX_OVERFLOW_MASK 0x00000008
-#define UMBOX_INT_ENABLE_TX_OVERFLOW_GET(x) (((x) & UMBOX_INT_ENABLE_TX_OVERFLOW_MASK) >> UMBOX_INT_ENABLE_TX_OVERFLOW_LSB)
-#define UMBOX_INT_ENABLE_TX_OVERFLOW_SET(x) (((x) << UMBOX_INT_ENABLE_TX_OVERFLOW_LSB) & UMBOX_INT_ENABLE_TX_OVERFLOW_MASK)
-#define UMBOX_INT_ENABLE_RX_UNDERFLOW_MSB 2
-#define UMBOX_INT_ENABLE_RX_UNDERFLOW_LSB 2
-#define UMBOX_INT_ENABLE_RX_UNDERFLOW_MASK 0x00000004
-#define UMBOX_INT_ENABLE_RX_UNDERFLOW_GET(x) (((x) & UMBOX_INT_ENABLE_RX_UNDERFLOW_MASK) >> UMBOX_INT_ENABLE_RX_UNDERFLOW_LSB)
-#define UMBOX_INT_ENABLE_RX_UNDERFLOW_SET(x) (((x) << UMBOX_INT_ENABLE_RX_UNDERFLOW_LSB) & UMBOX_INT_ENABLE_RX_UNDERFLOW_MASK)
-#define UMBOX_INT_ENABLE_TX_NOT_EMPTY_MSB 1
-#define UMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB 1
-#define UMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK 0x00000002
-#define UMBOX_INT_ENABLE_TX_NOT_EMPTY_GET(x) (((x) & UMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK) >> UMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB)
-#define UMBOX_INT_ENABLE_TX_NOT_EMPTY_SET(x) (((x) << UMBOX_INT_ENABLE_TX_NOT_EMPTY_LSB) & UMBOX_INT_ENABLE_TX_NOT_EMPTY_MASK)
-#define UMBOX_INT_ENABLE_RX_NOT_FULL_MSB 0
-#define UMBOX_INT_ENABLE_RX_NOT_FULL_LSB 0
-#define UMBOX_INT_ENABLE_RX_NOT_FULL_MASK 0x00000001
-#define UMBOX_INT_ENABLE_RX_NOT_FULL_GET(x) (((x) & UMBOX_INT_ENABLE_RX_NOT_FULL_MASK) >> UMBOX_INT_ENABLE_RX_NOT_FULL_LSB)
-#define UMBOX_INT_ENABLE_RX_NOT_FULL_SET(x) (((x) << UMBOX_INT_ENABLE_RX_NOT_FULL_LSB) & UMBOX_INT_ENABLE_RX_NOT_FULL_MASK)
-
-#define UMBOX_DEBUG_ADDRESS 0x0000002c
-#define UMBOX_DEBUG_OFFSET 0x0000002c
-#define UMBOX_DEBUG_SEL_MSB 2
-#define UMBOX_DEBUG_SEL_LSB 0
-#define UMBOX_DEBUG_SEL_MASK 0x00000007
-#define UMBOX_DEBUG_SEL_GET(x) (((x) & UMBOX_DEBUG_SEL_MASK) >> UMBOX_DEBUG_SEL_LSB)
-#define UMBOX_DEBUG_SEL_SET(x) (((x) << UMBOX_DEBUG_SEL_LSB) & UMBOX_DEBUG_SEL_MASK)
-
-#define UMBOX_FIFO_RESET_ADDRESS 0x00000030
-#define UMBOX_FIFO_RESET_OFFSET 0x00000030
-#define UMBOX_FIFO_RESET_INIT_MSB 0
-#define UMBOX_FIFO_RESET_INIT_LSB 0
-#define UMBOX_FIFO_RESET_INIT_MASK 0x00000001
-#define UMBOX_FIFO_RESET_INIT_GET(x) (((x) & UMBOX_FIFO_RESET_INIT_MASK) >> UMBOX_FIFO_RESET_INIT_LSB)
-#define UMBOX_FIFO_RESET_INIT_SET(x) (((x) << UMBOX_FIFO_RESET_INIT_LSB) & UMBOX_FIFO_RESET_INIT_MASK)
-
-#define UMBOX_HCI_FRAMER_ADDRESS 0x00000034
-#define UMBOX_HCI_FRAMER_OFFSET 0x00000034
-#define UMBOX_HCI_FRAMER_CRC_OVERRIDE_MSB 6
-#define UMBOX_HCI_FRAMER_CRC_OVERRIDE_LSB 6
-#define UMBOX_HCI_FRAMER_CRC_OVERRIDE_MASK 0x00000040
-#define UMBOX_HCI_FRAMER_CRC_OVERRIDE_GET(x) (((x) & UMBOX_HCI_FRAMER_CRC_OVERRIDE_MASK) >> UMBOX_HCI_FRAMER_CRC_OVERRIDE_LSB)
-#define UMBOX_HCI_FRAMER_CRC_OVERRIDE_SET(x) (((x) << UMBOX_HCI_FRAMER_CRC_OVERRIDE_LSB) & UMBOX_HCI_FRAMER_CRC_OVERRIDE_MASK)
-#define UMBOX_HCI_FRAMER_ENABLE_MSB 5
-#define UMBOX_HCI_FRAMER_ENABLE_LSB 5
-#define UMBOX_HCI_FRAMER_ENABLE_MASK 0x00000020
-#define UMBOX_HCI_FRAMER_ENABLE_GET(x) (((x) & UMBOX_HCI_FRAMER_ENABLE_MASK) >> UMBOX_HCI_FRAMER_ENABLE_LSB)
-#define UMBOX_HCI_FRAMER_ENABLE_SET(x) (((x) << UMBOX_HCI_FRAMER_ENABLE_LSB) & UMBOX_HCI_FRAMER_ENABLE_MASK)
-#define UMBOX_HCI_FRAMER_SYNC_ERROR_MSB 4
-#define UMBOX_HCI_FRAMER_SYNC_ERROR_LSB 4
-#define UMBOX_HCI_FRAMER_SYNC_ERROR_MASK 0x00000010
-#define UMBOX_HCI_FRAMER_SYNC_ERROR_GET(x) (((x) & UMBOX_HCI_FRAMER_SYNC_ERROR_MASK) >> UMBOX_HCI_FRAMER_SYNC_ERROR_LSB)
-#define UMBOX_HCI_FRAMER_SYNC_ERROR_SET(x) (((x) << UMBOX_HCI_FRAMER_SYNC_ERROR_LSB) & UMBOX_HCI_FRAMER_SYNC_ERROR_MASK)
-#define UMBOX_HCI_FRAMER_UNDERFLOW_MSB 3
-#define UMBOX_HCI_FRAMER_UNDERFLOW_LSB 3
-#define UMBOX_HCI_FRAMER_UNDERFLOW_MASK 0x00000008
-#define UMBOX_HCI_FRAMER_UNDERFLOW_GET(x) (((x) & UMBOX_HCI_FRAMER_UNDERFLOW_MASK) >> UMBOX_HCI_FRAMER_UNDERFLOW_LSB)
-#define UMBOX_HCI_FRAMER_UNDERFLOW_SET(x) (((x) << UMBOX_HCI_FRAMER_UNDERFLOW_LSB) & UMBOX_HCI_FRAMER_UNDERFLOW_MASK)
-#define UMBOX_HCI_FRAMER_OVERFLOW_MSB 2
-#define UMBOX_HCI_FRAMER_OVERFLOW_LSB 2
-#define UMBOX_HCI_FRAMER_OVERFLOW_MASK 0x00000004
-#define UMBOX_HCI_FRAMER_OVERFLOW_GET(x) (((x) & UMBOX_HCI_FRAMER_OVERFLOW_MASK) >> UMBOX_HCI_FRAMER_OVERFLOW_LSB)
-#define UMBOX_HCI_FRAMER_OVERFLOW_SET(x) (((x) << UMBOX_HCI_FRAMER_OVERFLOW_LSB) & UMBOX_HCI_FRAMER_OVERFLOW_MASK)
-#define UMBOX_HCI_FRAMER_CONFIG_MODE_MSB 1
-#define UMBOX_HCI_FRAMER_CONFIG_MODE_LSB 0
-#define UMBOX_HCI_FRAMER_CONFIG_MODE_MASK 0x00000003
-#define UMBOX_HCI_FRAMER_CONFIG_MODE_GET(x) (((x) & UMBOX_HCI_FRAMER_CONFIG_MODE_MASK) >> UMBOX_HCI_FRAMER_CONFIG_MODE_LSB)
-#define UMBOX_HCI_FRAMER_CONFIG_MODE_SET(x) (((x) << UMBOX_HCI_FRAMER_CONFIG_MODE_LSB) & UMBOX_HCI_FRAMER_CONFIG_MODE_MASK)
-
-
-#ifndef __ASSEMBLER__
-
-typedef struct umbox_wlan_reg_reg_s {
- volatile unsigned int umbox_fifo[2];
- volatile unsigned int umbox_fifo_status;
- volatile unsigned int umbox_dma_policy;
- volatile unsigned int umbox0_dma_rx_descriptor_base;
- volatile unsigned int umbox0_dma_rx_control;
- volatile unsigned int umbox0_dma_tx_descriptor_base;
- volatile unsigned int umbox0_dma_tx_control;
- volatile unsigned int umbox_fifo_timeout;
- volatile unsigned int umbox_int_status;
- volatile unsigned int umbox_int_enable;
- volatile unsigned int umbox_debug;
- volatile unsigned int umbox_fifo_reset;
- volatile unsigned int umbox_hci_framer;
-} umbox_wlan_reg_reg_t;
-
-#endif /* __ASSEMBLER__ */
-
-#endif /* _UMBOX_WLAN_REG_H_ */
diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/vmc_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/vmc_reg.h
deleted file mode 100644
index c3d8088..0000000
--- a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/vmc_reg.h
+++ /dev/null
@@ -1,167 +0,0 @@
-// ------------------------------------------------------------------
-// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
-//
-//
-// Permission to use, copy, modify, and/or distribute this software for any
-// purpose with or without fee is hereby granted, provided that the above
-// copyright notice and this permission notice appear in all copies.
-//
-// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-//
-//
-// ------------------------------------------------------------------
-//===================================================================
-// Author(s): ="Atheros"
-//===================================================================
-
-
-#ifdef WLAN_HEADERS
-
-#include "vmc_wlan_reg.h"
-
-
-#ifndef BT_HEADERS
-
-#define MC_BCAM_VALID_ADDRESS WLAN_MC_BCAM_VALID_ADDRESS
-#define MC_BCAM_VALID_OFFSET WLAN_MC_BCAM_VALID_OFFSET
-#define MC_BCAM_VALID_BIT_MSB WLAN_MC_BCAM_VALID_BIT_MSB
-#define MC_BCAM_VALID_BIT_LSB WLAN_MC_BCAM_VALID_BIT_LSB
-#define MC_BCAM_VALID_BIT_MASK WLAN_MC_BCAM_VALID_BIT_MASK
-#define MC_BCAM_VALID_BIT_GET(x) WLAN_MC_BCAM_VALID_BIT_GET(x)
-#define MC_BCAM_VALID_BIT_SET(x) WLAN_MC_BCAM_VALID_BIT_SET(x)
-#define MC_BCAM_COMPARE_ADDRESS WLAN_MC_BCAM_COMPARE_ADDRESS
-#define MC_BCAM_COMPARE_OFFSET WLAN_MC_BCAM_COMPARE_OFFSET
-#define MC_BCAM_COMPARE_KEY_MSB WLAN_MC_BCAM_COMPARE_KEY_MSB
-#define MC_BCAM_COMPARE_KEY_LSB WLAN_MC_BCAM_COMPARE_KEY_LSB
-#define MC_BCAM_COMPARE_KEY_MASK WLAN_MC_BCAM_COMPARE_KEY_MASK
-#define MC_BCAM_COMPARE_KEY_GET(x) WLAN_MC_BCAM_COMPARE_KEY_GET(x)
-#define MC_BCAM_COMPARE_KEY_SET(x) WLAN_MC_BCAM_COMPARE_KEY_SET(x)
-#define MC_BCAM_TARGET_ADDRESS WLAN_MC_BCAM_TARGET_ADDRESS
-#define MC_BCAM_TARGET_OFFSET WLAN_MC_BCAM_TARGET_OFFSET
-#define MC_BCAM_TARGET_INST_MSB WLAN_MC_BCAM_TARGET_INST_MSB
-#define MC_BCAM_TARGET_INST_LSB WLAN_MC_BCAM_TARGET_INST_LSB
-#define MC_BCAM_TARGET_INST_MASK WLAN_MC_BCAM_TARGET_INST_MASK
-#define MC_BCAM_TARGET_INST_GET(x) WLAN_MC_BCAM_TARGET_INST_GET(x)
-#define MC_BCAM_TARGET_INST_SET(x) WLAN_MC_BCAM_TARGET_INST_SET(x)
-#define APB_ADDR_ERROR_CONTROL_ADDRESS WLAN_APB_ADDR_ERROR_CONTROL_ADDRESS
-#define APB_ADDR_ERROR_CONTROL_OFFSET WLAN_APB_ADDR_ERROR_CONTROL_OFFSET
-#define APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MSB WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MSB
-#define APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB
-#define APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK
-#define APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_GET(x) WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_GET(x)
-#define APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_SET(x) WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_SET(x)
-#define APB_ADDR_ERROR_CONTROL_ENABLE_MSB WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_MSB
-#define APB_ADDR_ERROR_CONTROL_ENABLE_LSB WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_LSB
-#define APB_ADDR_ERROR_CONTROL_ENABLE_MASK WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_MASK
-#define APB_ADDR_ERROR_CONTROL_ENABLE_GET(x) WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_GET(x)
-#define APB_ADDR_ERROR_CONTROL_ENABLE_SET(x) WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_SET(x)
-#define APB_ADDR_ERROR_STATUS_ADDRESS WLAN_APB_ADDR_ERROR_STATUS_ADDRESS
-#define APB_ADDR_ERROR_STATUS_OFFSET WLAN_APB_ADDR_ERROR_STATUS_OFFSET
-#define APB_ADDR_ERROR_STATUS_WRITE_MSB WLAN_APB_ADDR_ERROR_STATUS_WRITE_MSB
-#define APB_ADDR_ERROR_STATUS_WRITE_LSB WLAN_APB_ADDR_ERROR_STATUS_WRITE_LSB
-#define APB_ADDR_ERROR_STATUS_WRITE_MASK WLAN_APB_ADDR_ERROR_STATUS_WRITE_MASK
-#define APB_ADDR_ERROR_STATUS_WRITE_GET(x) WLAN_APB_ADDR_ERROR_STATUS_WRITE_GET(x)
-#define APB_ADDR_ERROR_STATUS_WRITE_SET(x) WLAN_APB_ADDR_ERROR_STATUS_WRITE_SET(x)
-#define APB_ADDR_ERROR_STATUS_ADDRESS_MSB WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_MSB
-#define APB_ADDR_ERROR_STATUS_ADDRESS_LSB WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_LSB
-#define APB_ADDR_ERROR_STATUS_ADDRESS_MASK WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_MASK
-#define APB_ADDR_ERROR_STATUS_ADDRESS_GET(x) WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_GET(x)
-#define APB_ADDR_ERROR_STATUS_ADDRESS_SET(x) WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_SET(x)
-#define AHB_ADDR_ERROR_CONTROL_ADDRESS WLAN_AHB_ADDR_ERROR_CONTROL_ADDRESS
-#define AHB_ADDR_ERROR_CONTROL_OFFSET WLAN_AHB_ADDR_ERROR_CONTROL_OFFSET
-#define AHB_ADDR_ERROR_CONTROL_ENABLE_MSB WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_MSB
-#define AHB_ADDR_ERROR_CONTROL_ENABLE_LSB WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_LSB
-#define AHB_ADDR_ERROR_CONTROL_ENABLE_MASK WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_MASK
-#define AHB_ADDR_ERROR_CONTROL_ENABLE_GET(x) WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_GET(x)
-#define AHB_ADDR_ERROR_CONTROL_ENABLE_SET(x) WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_SET(x)
-#define AHB_ADDR_ERROR_STATUS_ADDRESS WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS
-#define AHB_ADDR_ERROR_STATUS_OFFSET WLAN_AHB_ADDR_ERROR_STATUS_OFFSET
-#define AHB_ADDR_ERROR_STATUS_MAC_MSB WLAN_AHB_ADDR_ERROR_STATUS_MAC_MSB
-#define AHB_ADDR_ERROR_STATUS_MAC_LSB WLAN_AHB_ADDR_ERROR_STATUS_MAC_LSB
-#define AHB_ADDR_ERROR_STATUS_MAC_MASK WLAN_AHB_ADDR_ERROR_STATUS_MAC_MASK
-#define AHB_ADDR_ERROR_STATUS_MAC_GET(x) WLAN_AHB_ADDR_ERROR_STATUS_MAC_GET(x)
-#define AHB_ADDR_ERROR_STATUS_MAC_SET(x) WLAN_AHB_ADDR_ERROR_STATUS_MAC_SET(x)
-#define AHB_ADDR_ERROR_STATUS_MBOX_MSB WLAN_AHB_ADDR_ERROR_STATUS_MBOX_MSB
-#define AHB_ADDR_ERROR_STATUS_MBOX_LSB WLAN_AHB_ADDR_ERROR_STATUS_MBOX_LSB
-#define AHB_ADDR_ERROR_STATUS_MBOX_MASK WLAN_AHB_ADDR_ERROR_STATUS_MBOX_MASK
-#define AHB_ADDR_ERROR_STATUS_MBOX_GET(x) WLAN_AHB_ADDR_ERROR_STATUS_MBOX_GET(x)
-#define AHB_ADDR_ERROR_STATUS_MBOX_SET(x) WLAN_AHB_ADDR_ERROR_STATUS_MBOX_SET(x)
-#define AHB_ADDR_ERROR_STATUS_ADDRESS_MSB WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_MSB
-#define AHB_ADDR_ERROR_STATUS_ADDRESS_LSB WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_LSB
-#define AHB_ADDR_ERROR_STATUS_ADDRESS_MASK WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_MASK
-#define AHB_ADDR_ERROR_STATUS_ADDRESS_GET(x) WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_GET(x)
-#define AHB_ADDR_ERROR_STATUS_ADDRESS_SET(x) WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_SET(x)
-#define BCAM_CONFLICT_ERROR_ADDRESS WLAN_BCAM_CONFLICT_ERROR_ADDRESS
-#define BCAM_CONFLICT_ERROR_OFFSET WLAN_BCAM_CONFLICT_ERROR_OFFSET
-#define BCAM_CONFLICT_ERROR_IPORT_FLAG_MSB WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_MSB
-#define BCAM_CONFLICT_ERROR_IPORT_FLAG_LSB WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_LSB
-#define BCAM_CONFLICT_ERROR_IPORT_FLAG_MASK WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_MASK
-#define BCAM_CONFLICT_ERROR_IPORT_FLAG_GET(x) WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_GET(x)
-#define BCAM_CONFLICT_ERROR_IPORT_FLAG_SET(x) WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_SET(x)
-#define BCAM_CONFLICT_ERROR_DPORT_FLAG_MSB WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_MSB
-#define BCAM_CONFLICT_ERROR_DPORT_FLAG_LSB WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_LSB
-#define BCAM_CONFLICT_ERROR_DPORT_FLAG_MASK WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_MASK
-#define BCAM_CONFLICT_ERROR_DPORT_FLAG_GET(x) WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_GET(x)
-#define BCAM_CONFLICT_ERROR_DPORT_FLAG_SET(x) WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_SET(x)
-#define CPU_PERF_CNT_ADDRESS WLAN_CPU_PERF_CNT_ADDRESS
-#define CPU_PERF_CNT_OFFSET WLAN_CPU_PERF_CNT_OFFSET
-#define CPU_PERF_CNT_EN_MSB WLAN_CPU_PERF_CNT_EN_MSB
-#define CPU_PERF_CNT_EN_LSB WLAN_CPU_PERF_CNT_EN_LSB
-#define CPU_PERF_CNT_EN_MASK WLAN_CPU_PERF_CNT_EN_MASK
-#define CPU_PERF_CNT_EN_GET(x) WLAN_CPU_PERF_CNT_EN_GET(x)
-#define CPU_PERF_CNT_EN_SET(x) WLAN_CPU_PERF_CNT_EN_SET(x)
-#define CPU_INST_FETCH_ADDRESS WLAN_CPU_INST_FETCH_ADDRESS
-#define CPU_INST_FETCH_OFFSET WLAN_CPU_INST_FETCH_OFFSET
-#define CPU_INST_FETCH_CNT_MSB WLAN_CPU_INST_FETCH_CNT_MSB
-#define CPU_INST_FETCH_CNT_LSB WLAN_CPU_INST_FETCH_CNT_LSB
-#define CPU_INST_FETCH_CNT_MASK WLAN_CPU_INST_FETCH_CNT_MASK
-#define CPU_INST_FETCH_CNT_GET(x) WLAN_CPU_INST_FETCH_CNT_GET(x)
-#define CPU_INST_FETCH_CNT_SET(x) WLAN_CPU_INST_FETCH_CNT_SET(x)
-#define CPU_DATA_FETCH_ADDRESS WLAN_CPU_DATA_FETCH_ADDRESS
-#define CPU_DATA_FETCH_OFFSET WLAN_CPU_DATA_FETCH_OFFSET
-#define CPU_DATA_FETCH_CNT_MSB WLAN_CPU_DATA_FETCH_CNT_MSB
-#define CPU_DATA_FETCH_CNT_LSB WLAN_CPU_DATA_FETCH_CNT_LSB
-#define CPU_DATA_FETCH_CNT_MASK WLAN_CPU_DATA_FETCH_CNT_MASK
-#define CPU_DATA_FETCH_CNT_GET(x) WLAN_CPU_DATA_FETCH_CNT_GET(x)
-#define CPU_DATA_FETCH_CNT_SET(x) WLAN_CPU_DATA_FETCH_CNT_SET(x)
-#define CPU_RAM1_CONFLICT_ADDRESS WLAN_CPU_RAM1_CONFLICT_ADDRESS
-#define CPU_RAM1_CONFLICT_OFFSET WLAN_CPU_RAM1_CONFLICT_OFFSET
-#define CPU_RAM1_CONFLICT_CNT_MSB WLAN_CPU_RAM1_CONFLICT_CNT_MSB
-#define CPU_RAM1_CONFLICT_CNT_LSB WLAN_CPU_RAM1_CONFLICT_CNT_LSB
-#define CPU_RAM1_CONFLICT_CNT_MASK WLAN_CPU_RAM1_CONFLICT_CNT_MASK
-#define CPU_RAM1_CONFLICT_CNT_GET(x) WLAN_CPU_RAM1_CONFLICT_CNT_GET(x)
-#define CPU_RAM1_CONFLICT_CNT_SET(x) WLAN_CPU_RAM1_CONFLICT_CNT_SET(x)
-#define CPU_RAM2_CONFLICT_ADDRESS WLAN_CPU_RAM2_CONFLICT_ADDRESS
-#define CPU_RAM2_CONFLICT_OFFSET WLAN_CPU_RAM2_CONFLICT_OFFSET
-#define CPU_RAM2_CONFLICT_CNT_MSB WLAN_CPU_RAM2_CONFLICT_CNT_MSB
-#define CPU_RAM2_CONFLICT_CNT_LSB WLAN_CPU_RAM2_CONFLICT_CNT_LSB
-#define CPU_RAM2_CONFLICT_CNT_MASK WLAN_CPU_RAM2_CONFLICT_CNT_MASK
-#define CPU_RAM2_CONFLICT_CNT_GET(x) WLAN_CPU_RAM2_CONFLICT_CNT_GET(x)
-#define CPU_RAM2_CONFLICT_CNT_SET(x) WLAN_CPU_RAM2_CONFLICT_CNT_SET(x)
-#define CPU_RAM3_CONFLICT_ADDRESS WLAN_CPU_RAM3_CONFLICT_ADDRESS
-#define CPU_RAM3_CONFLICT_OFFSET WLAN_CPU_RAM3_CONFLICT_OFFSET
-#define CPU_RAM3_CONFLICT_CNT_MSB WLAN_CPU_RAM3_CONFLICT_CNT_MSB
-#define CPU_RAM3_CONFLICT_CNT_LSB WLAN_CPU_RAM3_CONFLICT_CNT_LSB
-#define CPU_RAM3_CONFLICT_CNT_MASK WLAN_CPU_RAM3_CONFLICT_CNT_MASK
-#define CPU_RAM3_CONFLICT_CNT_GET(x) WLAN_CPU_RAM3_CONFLICT_CNT_GET(x)
-#define CPU_RAM3_CONFLICT_CNT_SET(x) WLAN_CPU_RAM3_CONFLICT_CNT_SET(x)
-#define CPU_RAM4_CONFLICT_ADDRESS WLAN_CPU_RAM4_CONFLICT_ADDRESS
-#define CPU_RAM4_CONFLICT_OFFSET WLAN_CPU_RAM4_CONFLICT_OFFSET
-#define CPU_RAM4_CONFLICT_CNT_MSB WLAN_CPU_RAM4_CONFLICT_CNT_MSB
-#define CPU_RAM4_CONFLICT_CNT_LSB WLAN_CPU_RAM4_CONFLICT_CNT_LSB
-#define CPU_RAM4_CONFLICT_CNT_MASK WLAN_CPU_RAM4_CONFLICT_CNT_MASK
-#define CPU_RAM4_CONFLICT_CNT_GET(x) WLAN_CPU_RAM4_CONFLICT_CNT_GET(x)
-#define CPU_RAM4_CONFLICT_CNT_SET(x) WLAN_CPU_RAM4_CONFLICT_CNT_SET(x)
-
-
-#endif
-#endif
-
-
-
diff --git a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/vmc_wlan_reg.h b/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/vmc_wlan_reg.h
deleted file mode 100644
index d28de39..0000000
--- a/drivers/staging/ath6kl/include/common/AR6002/hw4.0/hw/vmc_wlan_reg.h
+++ /dev/null
@@ -1,195 +0,0 @@
-// ------------------------------------------------------------------
-// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
-//
-//
-// Permission to use, copy, modify, and/or distribute this software for any
-// purpose with or without fee is hereby granted, provided that the above
-// copyright notice and this permission notice appear in all copies.
-//
-// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-//
-//
-// ------------------------------------------------------------------
-//===================================================================
-// Author(s): ="Atheros"
-//===================================================================
-
-
-#ifndef _VMC_WLAN_REG_REG_H_
-#define _VMC_WLAN_REG_REG_H_
-
-#define WLAN_MC_BCAM_VALID_ADDRESS 0x00000000
-#define WLAN_MC_BCAM_VALID_OFFSET 0x00000000
-#define WLAN_MC_BCAM_VALID_BIT_MSB 0
-#define WLAN_MC_BCAM_VALID_BIT_LSB 0
-#define WLAN_MC_BCAM_VALID_BIT_MASK 0x00000001
-#define WLAN_MC_BCAM_VALID_BIT_GET(x) (((x) & WLAN_MC_BCAM_VALID_BIT_MASK) >> WLAN_MC_BCAM_VALID_BIT_LSB)
-#define WLAN_MC_BCAM_VALID_BIT_SET(x) (((x) << WLAN_MC_BCAM_VALID_BIT_LSB) & WLAN_MC_BCAM_VALID_BIT_MASK)
-
-#define WLAN_MC_BCAM_COMPARE_ADDRESS 0x00000200
-#define WLAN_MC_BCAM_COMPARE_OFFSET 0x00000200
-#define WLAN_MC_BCAM_COMPARE_KEY_MSB 19
-#define WLAN_MC_BCAM_COMPARE_KEY_LSB 2
-#define WLAN_MC_BCAM_COMPARE_KEY_MASK 0x000ffffc
-#define WLAN_MC_BCAM_COMPARE_KEY_GET(x) (((x) & WLAN_MC_BCAM_COMPARE_KEY_MASK) >> WLAN_MC_BCAM_COMPARE_KEY_LSB)
-#define WLAN_MC_BCAM_COMPARE_KEY_SET(x) (((x) << WLAN_MC_BCAM_COMPARE_KEY_LSB) & WLAN_MC_BCAM_COMPARE_KEY_MASK)
-
-#define WLAN_MC_BCAM_TARGET_ADDRESS 0x00000400
-#define WLAN_MC_BCAM_TARGET_OFFSET 0x00000400
-#define WLAN_MC_BCAM_TARGET_INST_MSB 31
-#define WLAN_MC_BCAM_TARGET_INST_LSB 0
-#define WLAN_MC_BCAM_TARGET_INST_MASK 0xffffffff
-#define WLAN_MC_BCAM_TARGET_INST_GET(x) (((x) & WLAN_MC_BCAM_TARGET_INST_MASK) >> WLAN_MC_BCAM_TARGET_INST_LSB)
-#define WLAN_MC_BCAM_TARGET_INST_SET(x) (((x) << WLAN_MC_BCAM_TARGET_INST_LSB) & WLAN_MC_BCAM_TARGET_INST_MASK)
-
-#define WLAN_APB_ADDR_ERROR_CONTROL_ADDRESS 0x00000600
-#define WLAN_APB_ADDR_ERROR_CONTROL_OFFSET 0x00000600
-#define WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MSB 1
-#define WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB 1
-#define WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK 0x00000002
-#define WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_GET(x) (((x) & WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK) >> WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB)
-#define WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_SET(x) (((x) << WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_LSB) & WLAN_APB_ADDR_ERROR_CONTROL_QUAL_ENABLE_MASK)
-#define WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_MSB 0
-#define WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_LSB 0
-#define WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_MASK 0x00000001
-#define WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_GET(x) (((x) & WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_MASK) >> WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_LSB)
-#define WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_SET(x) (((x) << WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_LSB) & WLAN_APB_ADDR_ERROR_CONTROL_ENABLE_MASK)
-
-#define WLAN_APB_ADDR_ERROR_STATUS_ADDRESS 0x00000604
-#define WLAN_APB_ADDR_ERROR_STATUS_OFFSET 0x00000604
-#define WLAN_APB_ADDR_ERROR_STATUS_WRITE_MSB 25
-#define WLAN_APB_ADDR_ERROR_STATUS_WRITE_LSB 25
-#define WLAN_APB_ADDR_ERROR_STATUS_WRITE_MASK 0x02000000
-#define WLAN_APB_ADDR_ERROR_STATUS_WRITE_GET(x) (((x) & WLAN_APB_ADDR_ERROR_STATUS_WRITE_MASK) >> WLAN_APB_ADDR_ERROR_STATUS_WRITE_LSB)
-#define WLAN_APB_ADDR_ERROR_STATUS_WRITE_SET(x) (((x) << WLAN_APB_ADDR_ERROR_STATUS_WRITE_LSB) & WLAN_APB_ADDR_ERROR_STATUS_WRITE_MASK)
-#define WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_MSB 24
-#define WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_LSB 0
-#define WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_MASK 0x01ffffff
-#define WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_GET(x) (((x) & WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_MASK) >> WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_LSB)
-#define WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_SET(x) (((x) << WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_LSB) & WLAN_APB_ADDR_ERROR_STATUS_ADDRESS_MASK)
-
-#define WLAN_AHB_ADDR_ERROR_CONTROL_ADDRESS 0x00000608
-#define WLAN_AHB_ADDR_ERROR_CONTROL_OFFSET 0x00000608
-#define WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_MSB 0
-#define WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_LSB 0
-#define WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_MASK 0x00000001
-#define WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_GET(x) (((x) & WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_MASK) >> WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_LSB)
-#define WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_SET(x) (((x) << WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_LSB) & WLAN_AHB_ADDR_ERROR_CONTROL_ENABLE_MASK)
-
-#define WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS 0x0000060c
-#define WLAN_AHB_ADDR_ERROR_STATUS_OFFSET 0x0000060c
-#define WLAN_AHB_ADDR_ERROR_STATUS_MAC_MSB 31
-#define WLAN_AHB_ADDR_ERROR_STATUS_MAC_LSB 31
-#define WLAN_AHB_ADDR_ERROR_STATUS_MAC_MASK 0x80000000
-#define WLAN_AHB_ADDR_ERROR_STATUS_MAC_GET(x) (((x) & WLAN_AHB_ADDR_ERROR_STATUS_MAC_MASK) >> WLAN_AHB_ADDR_ERROR_STATUS_MAC_LSB)
-#define WLAN_AHB_ADDR_ERROR_STATUS_MAC_SET(x) (((x) << WLAN_AHB_ADDR_ERROR_STATUS_MAC_LSB) & WLAN_AHB_ADDR_ERROR_STATUS_MAC_MASK)
-#define WLAN_AHB_ADDR_ERROR_STATUS_MBOX_MSB 30
-#define WLAN_AHB_ADDR_ERROR_STATUS_MBOX_LSB 30
-#define WLAN_AHB_ADDR_ERROR_STATUS_MBOX_MASK 0x40000000
-#define WLAN_AHB_ADDR_ERROR_STATUS_MBOX_GET(x) (((x) & WLAN_AHB_ADDR_ERROR_STATUS_MBOX_MASK) >> WLAN_AHB_ADDR_ERROR_STATUS_MBOX_LSB)
-#define WLAN_AHB_ADDR_ERROR_STATUS_MBOX_SET(x) (((x) << WLAN_AHB_ADDR_ERROR_STATUS_MBOX_LSB) & WLAN_AHB_ADDR_ERROR_STATUS_MBOX_MASK)
-#define WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_MSB 23
-#define WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_LSB 0
-#define WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_MASK 0x00ffffff
-#define WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_GET(x) (((x) & WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_MASK) >> WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_LSB)
-#define WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_SET(x) (((x) << WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_LSB) & WLAN_AHB_ADDR_ERROR_STATUS_ADDRESS_MASK)
-
-#define WLAN_BCAM_CONFLICT_ERROR_ADDRESS 0x00000610
-#define WLAN_BCAM_CONFLICT_ERROR_OFFSET 0x00000610
-#define WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_MSB 1
-#define WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_LSB 1
-#define WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_MASK 0x00000002
-#define WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_GET(x) (((x) & WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_MASK) >> WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_LSB)
-#define WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_SET(x) (((x) << WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_LSB) & WLAN_BCAM_CONFLICT_ERROR_IPORT_FLAG_MASK)
-#define WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_MSB 0
-#define WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_LSB 0
-#define WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_MASK 0x00000001
-#define WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_GET(x) (((x) & WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_MASK) >> WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_LSB)
-#define WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_SET(x) (((x) << WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_LSB) & WLAN_BCAM_CONFLICT_ERROR_DPORT_FLAG_MASK)
-
-#define WLAN_CPU_PERF_CNT_ADDRESS 0x00000614
-#define WLAN_CPU_PERF_CNT_OFFSET 0x00000614
-#define WLAN_CPU_PERF_CNT_EN_MSB 0
-#define WLAN_CPU_PERF_CNT_EN_LSB 0
-#define WLAN_CPU_PERF_CNT_EN_MASK 0x00000001
-#define WLAN_CPU_PERF_CNT_EN_GET(x) (((x) & WLAN_CPU_PERF_CNT_EN_MASK) >> WLAN_CPU_PERF_CNT_EN_LSB)
-#define WLAN_CPU_PERF_CNT_EN_SET(x) (((x) << WLAN_CPU_PERF_CNT_EN_LSB) & WLAN_CPU_PERF_CNT_EN_MASK)
-
-#define WLAN_CPU_INST_FETCH_ADDRESS 0x00000618
-#define WLAN_CPU_INST_FETCH_OFFSET 0x00000618
-#define WLAN_CPU_INST_FETCH_CNT_MSB 31
-#define WLAN_CPU_INST_FETCH_CNT_LSB 0
-#define WLAN_CPU_INST_FETCH_CNT_MASK 0xffffffff
-#define WLAN_CPU_INST_FETCH_CNT_GET(x) (((x) & WLAN_CPU_INST_FETCH_CNT_MASK) >> WLAN_CPU_INST_FETCH_CNT_LSB)
-#define WLAN_CPU_INST_FETCH_CNT_SET(x) (((x) << WLAN_CPU_INST_FETCH_CNT_LSB) & WLAN_CPU_INST_FETCH_CNT_MASK)
-
-#define WLAN_CPU_DATA_FETCH_ADDRESS 0x0000061c
-#define WLAN_CPU_DATA_FETCH_OFFSET 0x0000061c
-#define WLAN_CPU_DATA_FETCH_CNT_MSB 31
-#define WLAN_CPU_DATA_FETCH_CNT_LSB 0
-#define WLAN_CPU_DATA_FETCH_CNT_MASK 0xffffffff
-#define WLAN_CPU_DATA_FETCH_CNT_GET(x) (((x) & WLAN_CPU_DATA_FETCH_CNT_MASK) >> WLAN_CPU_DATA_FETCH_CNT_LSB)
-#define WLAN_CPU_DATA_FETCH_CNT_SET(x) (((x) << WLAN_CPU_DATA_FETCH_CNT_LSB) & WLAN_CPU_DATA_FETCH_CNT_MASK)
-
-#define WLAN_CPU_RAM1_CONFLICT_ADDRESS 0x00000620
-#define WLAN_CPU_RAM1_CONFLICT_OFFSET 0x00000620
-#define WLAN_CPU_RAM1_CONFLICT_CNT_MSB 11
-#define WLAN_CPU_RAM1_CONFLICT_CNT_LSB 0
-#define WLAN_CPU_RAM1_CONFLICT_CNT_MASK 0x00000fff
-#define WLAN_CPU_RAM1_CONFLICT_CNT_GET(x) (((x) & WLAN_CPU_RAM1_CONFLICT_CNT_MASK) >> WLAN_CPU_RAM1_CONFLICT_CNT_LSB)
-#define WLAN_CPU_RAM1_CONFLICT_CNT_SET(x) (((x) << WLAN_CPU_RAM1_CONFLICT_CNT_LSB) & WLAN_CPU_RAM1_CONFLICT_CNT_MASK)
-
-#define WLAN_CPU_RAM2_CONFLICT_ADDRESS 0x00000624
-#define WLAN_CPU_RAM2_CONFLICT_OFFSET 0x00000624
-#define WLAN_CPU_RAM2_CONFLICT_CNT_MSB 11
-#define WLAN_CPU_RAM2_CONFLICT_CNT_LSB 0
-#define WLAN_CPU_RAM2_CONFLICT_CNT_MASK 0x00000fff
-#define WLAN_CPU_RAM2_CONFLICT_CNT_GET(x) (((x) & WLAN_CPU_RAM2_CONFLICT_CNT_MASK) >> WLAN_CPU_RAM2_CONFLICT_CNT_LSB)
-#define WLAN_CPU_RAM2_CONFLICT_CNT_SET(x) (((x) << WLAN_CPU_RAM2_CONFLICT_CNT_LSB) & WLAN_CPU_RAM2_CONFLICT_CNT_MASK)
-
-#define WLAN_CPU_RAM3_CONFLICT_ADDRESS 0x00000628
-#define WLAN_CPU_RAM3_CONFLICT_OFFSET 0x00000628
-#define WLAN_CPU_RAM3_CONFLICT_CNT_MSB 11
-#define WLAN_CPU_RAM3_CONFLICT_CNT_LSB 0
-#define WLAN_CPU_RAM3_CONFLICT_CNT_MASK 0x00000fff
-#define WLAN_CPU_RAM3_CONFLICT_CNT_GET(x) (((x) & WLAN_CPU_RAM3_CONFLICT_CNT_MASK) >> WLAN_CPU_RAM3_CONFLICT_CNT_LSB)
-#define WLAN_CPU_RAM3_CONFLICT_CNT_SET(x) (((x) << WLAN_CPU_RAM3_CONFLICT_CNT_LSB) & WLAN_CPU_RAM3_CONFLICT_CNT_MASK)
-
-#define WLAN_CPU_RAM4_CONFLICT_ADDRESS 0x0000062c
-#define WLAN_CPU_RAM4_CONFLICT_OFFSET 0x0000062c
-#define WLAN_CPU_RAM4_CONFLICT_CNT_MSB 11
-#define WLAN_CPU_RAM4_CONFLICT_CNT_LSB 0
-#define WLAN_CPU_RAM4_CONFLICT_CNT_MASK 0x00000fff
-#define WLAN_CPU_RAM4_CONFLICT_CNT_GET(x) (((x) & WLAN_CPU_RAM4_CONFLICT_CNT_MASK) >> WLAN_CPU_RAM4_CONFLICT_CNT_LSB)
-#define WLAN_CPU_RAM4_CONFLICT_CNT_SET(x) (((x) << WLAN_CPU_RAM4_CONFLICT_CNT_LSB) & WLAN_CPU_RAM4_CONFLICT_CNT_MASK)
-
-
-#ifndef __ASSEMBLER__
-
-typedef struct vmc_wlan_reg_reg_s {
- volatile unsigned int wlan_mc_bcam_valid[128];
- volatile unsigned int wlan_mc_bcam_compare[128];
- volatile unsigned int wlan_mc_bcam_target[128];
- volatile unsigned int wlan_apb_addr_error_control;
- volatile unsigned int wlan_apb_addr_error_status;
- volatile unsigned int wlan_ahb_addr_error_control;
- volatile unsigned int wlan_ahb_addr_error_status;
- volatile unsigned int wlan_bcam_conflict_error;
- volatile unsigned int wlan_cpu_perf_cnt;
- volatile unsigned int wlan_cpu_inst_fetch;
- volatile unsigned int wlan_cpu_data_fetch;
- volatile unsigned int wlan_cpu_ram1_conflict;
- volatile unsigned int wlan_cpu_ram2_conflict;
- volatile unsigned int wlan_cpu_ram3_conflict;
- volatile unsigned int wlan_cpu_ram4_conflict;
-} vmc_wlan_reg_reg_t;
-
-#endif /* __ASSEMBLER__ */
-
-#endif /* _VMC_WLAN_REG_H_ */
diff --git a/drivers/staging/ath6kl/include/common/a_hci.h b/drivers/staging/ath6kl/include/common/a_hci.h
deleted file mode 100644
index 379d652..0000000
--- a/drivers/staging/ath6kl/include/common/a_hci.h
+++ /dev/null
@@ -1,682 +0,0 @@
-//-
-// Copyright (c) 2009-2010 Atheros Communications Inc.
-// All rights reserved.
-//
-//
-// Permission to use, copy, modify, and/or distribute this software for any
-// purpose with or without fee is hereby granted, provided that the above
-// copyright notice and this permission notice appear in all copies.
-//
-// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-//
-//
-//
-//
-
-
-#ifndef __A_HCI_H__
-#define __A_HCI_H__
-
-#define HCI_CMD_OGF_MASK 0x3F
-#define HCI_CMD_OGF_SHIFT 10
-#define HCI_CMD_GET_OGF(opcode) ((opcode >> HCI_CMD_OGF_SHIFT) & HCI_CMD_OGF_MASK)
-
-#define HCI_CMD_OCF_MASK 0x3FF
-#define HCI_CMD_OCF_SHIFT 0
-#define HCI_CMD_GET_OCF(opcode) (((opcode) >> HCI_CMD_OCF_SHIFT) & HCI_CMD_OCF_MASK)
-
-#define HCI_FORM_OPCODE(ocf, ogf) ((ocf & HCI_CMD_OCF_MASK) << HCI_CMD_OCF_SHIFT | \
- (ogf & HCI_CMD_OGF_MASK) << HCI_CMD_OGF_SHIFT)
-
-
-/*======== HCI Opcode groups ===============*/
-#define OGF_NOP 0x00
-#define OGF_LINK_CONTROL 0x01
-#define OGF_LINK_POLICY 0x03
-#define OGF_INFO_PARAMS 0x04
-#define OGF_STATUS 0x05
-#define OGF_TESTING 0x06
-#define OGF_BLUETOOTH 0x3E
-#define OGF_VENDOR_DEBUG 0x3F
-
-
-
-#define OCF_NOP 0x00
-
-
-/*===== Link Control Commands Opcode===================*/
-#define OCF_HCI_Create_Physical_Link 0x35
-#define OCF_HCI_Accept_Physical_Link_Req 0x36
-#define OCF_HCI_Disconnect_Physical_Link 0x37
-#define OCF_HCI_Create_Logical_Link 0x38
-#define OCF_HCI_Accept_Logical_Link 0x39
-#define OCF_HCI_Disconnect_Logical_Link 0x3A
-#define OCF_HCI_Logical_Link_Cancel 0x3B
-#define OCF_HCI_Flow_Spec_Modify 0x3C
-
-
-
-/*===== Link Policy Commands Opcode====================*/
-#define OCF_HCI_Set_Event_Mask 0x01
-#define OCF_HCI_Reset 0x03
-#define OCF_HCI_Read_Conn_Accept_Timeout 0x15
-#define OCF_HCI_Write_Conn_Accept_Timeout 0x16
-#define OCF_HCI_Read_Link_Supervision_Timeout 0x36
-#define OCF_HCI_Write_Link_Supervision_Timeout 0x37
-#define OCF_HCI_Enhanced_Flush 0x5F
-#define OCF_HCI_Read_Logical_Link_Accept_Timeout 0x61
-#define OCF_HCI_Write_Logical_Link_Accept_Timeout 0x62
-#define OCF_HCI_Set_Event_Mask_Page_2 0x63
-#define OCF_HCI_Read_Location_Data 0x64
-#define OCF_HCI_Write_Location_Data 0x65
-#define OCF_HCI_Read_Flow_Control_Mode 0x66
-#define OCF_HCI_Write_Flow_Control_Mode 0x67
-#define OCF_HCI_Read_BE_Flush_Timeout 0x69
-#define OCF_HCI_Write_BE_Flush_Timeout 0x6A
-#define OCF_HCI_Short_Range_Mode 0x6B
-
-
-/*======== Info Commands Opcode========================*/
-#define OCF_HCI_Read_Local_Ver_Info 0x01
-#define OCF_HCI_Read_Local_Supported_Cmds 0x02
-#define OCF_HCI_Read_Data_Block_Size 0x0A
-/*======== Status Commands Opcode======================*/
-#define OCF_HCI_Read_Failed_Contact_Counter 0x01
-#define OCF_HCI_Reset_Failed_Contact_Counter 0x02
-#define OCF_HCI_Read_Link_Quality 0x03
-#define OCF_HCI_Read_RSSI 0x05
-#define OCF_HCI_Read_Local_AMP_Info 0x09
-#define OCF_HCI_Read_Local_AMP_ASSOC 0x0A
-#define OCF_HCI_Write_Remote_AMP_ASSOC 0x0B
-
-
-/*======= AMP_ASSOC Specific TLV tags =================*/
-#define AMP_ASSOC_MAC_ADDRESS_INFO_TYPE 0x1
-#define AMP_ASSOC_PREF_CHAN_LIST 0x2
-#define AMP_ASSOC_CONNECTED_CHAN 0x3
-#define AMP_ASSOC_PAL_CAPABILITIES 0x4
-#define AMP_ASSOC_PAL_VERSION 0x5
-
-
-/*========= PAL Events =================================*/
-#define PAL_COMMAND_COMPLETE_EVENT 0x0E
-#define PAL_COMMAND_STATUS_EVENT 0x0F
-#define PAL_HARDWARE_ERROR_EVENT 0x10
-#define PAL_FLUSH_OCCURRED_EVENT 0x11
-#define PAL_LOOPBACK_EVENT 0x19
-#define PAL_BUFFER_OVERFLOW_EVENT 0x1A
-#define PAL_QOS_VIOLATION_EVENT 0x1E
-#define PAL_ENHANCED_FLUSH_COMPLT_EVENT 0x39
-#define PAL_PHYSICAL_LINK_COMPL_EVENT 0x40
-#define PAL_CHANNEL_SELECT_EVENT 0x41
-#define PAL_DISCONNECT_PHYSICAL_LINK_EVENT 0x42
-#define PAL_PHY_LINK_EARLY_LOSS_WARNING_EVENT 0x43
-#define PAL_PHY_LINK_RECOVERY_EVENT 0x44
-#define PAL_LOGICAL_LINK_COMPL_EVENT 0x45
-#define PAL_DISCONNECT_LOGICAL_LINK_COMPL_EVENT 0x46
-#define PAL_FLOW_SPEC_MODIFY_COMPL_EVENT 0x47
-#define PAL_NUM_COMPL_DATA_BLOCK_EVENT 0x48
-#define PAL_SHORT_RANGE_MODE_CHANGE_COMPL_EVENT 0x4C
-#define PAL_AMP_STATUS_CHANGE_EVENT 0x4D
-/*======== End of PAL events definition =================*/
-
-
-/*======== Timeouts (not part of HCI cmd, but input to PAL engine) =========*/
-#define Timer_Conn_Accept_TO 0x01
-#define Timer_Link_Supervision_TO 0x02
-
-#define NUM_HCI_COMMAND_PKTS 0x1
-
-
-/*====== NOP Cmd ============================*/
-#define HCI_CMD_NOP HCI_FORM_OPCODE(OCF_NOP, OGF_NOP)
-
-
-/*===== Link Control Commands================*/
-#define HCI_Create_Physical_Link HCI_FORM_OPCODE(OCF_HCI_Create_Physical_Link, OGF_LINK_CONTROL)
-#define HCI_Accept_Physical_Link_Req HCI_FORM_OPCODE(OCF_HCI_Accept_Physical_Link_Req, OGF_LINK_CONTROL)
-#define HCI_Disconnect_Physical_Link HCI_FORM_OPCODE(OCF_HCI_Disconnect_Physical_Link, OGF_LINK_CONTROL)
-#define HCI_Create_Logical_Link HCI_FORM_OPCODE(OCF_HCI_Create_Logical_Link, OGF_LINK_CONTROL)
-#define HCI_Accept_Logical_Link HCI_FORM_OPCODE(OCF_HCI_Accept_Logical_Link, OGF_LINK_CONTROL)
-#define HCI_Disconnect_Logical_Link HCI_FORM_OPCODE(OCF_HCI_Disconnect_Logical_Link, OGF_LINK_CONTROL)
-#define HCI_Logical_Link_Cancel HCI_FORM_OPCODE(OCF_HCI_Logical_Link_Cancel, OGF_LINK_CONTROL)
-#define HCI_Flow_Spec_Modify HCI_FORM_OPCODE(OCF_HCI_Flow_Spec_Modify, OGF_LINK_CONTROL)
-
-
-/*===== Link Policy Commands ================*/
-#define HCI_Set_Event_Mask HCI_FORM_OPCODE(OCF_HCI_Set_Event_Mask, OGF_LINK_POLICY)
-#define HCI_Reset HCI_FORM_OPCODE(OCF_HCI_Reset, OGF_LINK_POLICY)
-#define HCI_Enhanced_Flush HCI_FORM_OPCODE(OCF_HCI_Enhanced_Flush, OGF_LINK_POLICY)
-#define HCI_Read_Conn_Accept_Timeout HCI_FORM_OPCODE(OCF_HCI_Read_Conn_Accept_Timeout, OGF_LINK_POLICY)
-#define HCI_Write_Conn_Accept_Timeout HCI_FORM_OPCODE(OCF_HCI_Write_Conn_Accept_Timeout, OGF_LINK_POLICY)
-#define HCI_Read_Logical_Link_Accept_Timeout HCI_FORM_OPCODE(OCF_HCI_Read_Logical_Link_Accept_Timeout, OGF_LINK_POLICY)
-#define HCI_Write_Logical_Link_Accept_Timeout HCI_FORM_OPCODE(OCF_HCI_Write_Logical_Link_Accept_Timeout, OGF_LINK_POLICY)
-#define HCI_Read_Link_Supervision_Timeout HCI_FORM_OPCODE(OCF_HCI_Read_Link_Supervision_Timeout, OGF_LINK_POLICY)
-#define HCI_Write_Link_Supervision_Timeout HCI_FORM_OPCODE(OCF_HCI_Write_Link_Supervision_Timeout, OGF_LINK_POLICY)
-#define HCI_Read_Location_Data HCI_FORM_OPCODE(OCF_HCI_Read_Location_Data, OGF_LINK_POLICY)
-#define HCI_Write_Location_Data HCI_FORM_OPCODE(OCF_HCI_Write_Location_Data, OGF_LINK_POLICY)
-#define HCI_Set_Event_Mask_Page_2 HCI_FORM_OPCODE(OCF_HCI_Set_Event_Mask_Page_2, OGF_LINK_POLICY)
-#define HCI_Read_Flow_Control_Mode HCI_FORM_OPCODE(OCF_HCI_Read_Flow_Control_Mode, OGF_LINK_POLICY)
-#define HCI_Write_Flow_Control_Mode HCI_FORM_OPCODE(OCF_HCI_Write_Flow_Control_Mode, OGF_LINK_POLICY)
-#define HCI_Write_BE_Flush_Timeout HCI_FORM_OPCODE(OCF_HCI_Write_BE_Flush_Timeout, OGF_LINK_POLICY)
-#define HCI_Read_BE_Flush_Timeout HCI_FORM_OPCODE(OCF_HCI_Read_BE_Flush_Timeout, OGF_LINK_POLICY)
-#define HCI_Short_Range_Mode HCI_FORM_OPCODE(OCF_HCI_Short_Range_Mode, OGF_LINK_POLICY)
-
-
-/*===== Info Commands =====================*/
-#define HCI_Read_Local_Ver_Info HCI_FORM_OPCODE(OCF_HCI_Read_Local_Ver_Info, OGF_INFO_PARAMS)
-#define HCI_Read_Local_Supported_Cmds HCI_FORM_OPCODE(OCF_HCI_Read_Local_Supported_Cmds, OGF_INFO_PARAMS)
-#define HCI_Read_Data_Block_Size HCI_FORM_OPCODE(OCF_HCI_Read_Data_Block_Size, OGF_INFO_PARAMS)
-
-/*===== Status Commands =====================*/
-#define HCI_Read_Link_Quality HCI_FORM_OPCODE(OCF_HCI_Read_Link_Quality, OGF_STATUS)
-#define HCI_Read_RSSI HCI_FORM_OPCODE(OCF_HCI_Read_RSSI, OGF_STATUS)
-#define HCI_Read_Local_AMP_Info HCI_FORM_OPCODE(OCF_HCI_Read_Local_AMP_Info, OGF_STATUS)
-#define HCI_Read_Local_AMP_ASSOC HCI_FORM_OPCODE(OCF_HCI_Read_Local_AMP_ASSOC, OGF_STATUS)
-#define HCI_Write_Remote_AMP_ASSOC HCI_FORM_OPCODE(OCF_HCI_Write_Remote_AMP_ASSOC, OGF_STATUS)
-
-/*====== End of cmd definitions =============*/
-
-
-
-/*===== Timeouts(private - can't come from HCI)=================*/
-#define Conn_Accept_TO HCI_FORM_OPCODE(Timer_Conn_Accept_TO, OGF_VENDOR_DEBUG)
-#define Link_Supervision_TO HCI_FORM_OPCODE(Timer_Link_Supervision_TO, OGF_VENDOR_DEBUG)
-
-/*----- PAL Constants (Sec 6 of Doc)------------------------*/
-#define Max80211_PAL_PDU_Size 1492
-#define Max80211_AMP_ASSOC_Len 672
-#define MinGUserPrio 4
-#define MaxGUserPrio 7
-#define BEUserPrio0 0
-#define BEUserPrio1 3
-#define Max80211BeaconPeriod 2000 /* in millisec */
-#define ShortRangeModePowerMax 4 /* dBm */
-
-/*------ PAL Protocol Identifiers (Sec5.1) ------------------*/
-typedef enum {
- ACL_DATA = 0x01,
- ACTIVITY_REPORT,
- SECURED_FRAMES,
- LINK_SUPERVISION_REQ,
- LINK_SUPERVISION_RESP,
-}PAL_PROTOCOL_IDENTIFIERS;
-
-#define HCI_CMD_HDR_SZ 3
-#define HCI_EVENT_HDR_SIZE 2
-#define MAX_EVT_PKT_SZ 255
-#define AMP_ASSOC_MAX_FRAG_SZ 248
-#define AMP_MAX_GUARANTEED_BW 20000
-
-#define DEFAULT_CONN_ACCPT_TO 5000
-#define DEFAULT_LL_ACCPT_TO 5000
-#define DEFAULT_LSTO 10000
-
-#define PACKET_BASED_FLOW_CONTROL_MODE 0x00
-#define DATA_BLK_BASED_FLOW_CONTROL_MODE 0x01
-
-#define SERVICE_TYPE_BEST_EFFORT 0x01
-#define SERVICE_TYPE_GUARANTEED 0x02
-
-#define MAC_ADDR_LEN 6
-#define LINK_KEY_LEN 32
-
-typedef enum {
- ACL_DATA_PB_1ST_NON_AUTOMATICALLY_FLUSHABLE = 0x00,
- ACL_DATA_PB_CONTINUING_FRAGMENT = 0x01,
- ACL_DATA_PB_1ST_AUTOMATICALLY_FLUSHABLE = 0x02,
- ACL_DATA_PB_COMPLETE_PDU = 0x03,
-} ACL_DATA_PB_FLAGS;
-#define ACL_DATA_PB_FLAGS_SHIFT 12
-
-typedef enum {
- ACL_DATA_BC_POINT_TO_POINT = 0x00,
-} ACL_DATA_BC_FLAGS;
-#define ACL_DATA_BC_FLAGS_SHIFT 14
-
-/* Command pkt */
-typedef struct hci_cmd_pkt_t {
- u16 opcode;
- u8 param_length;
- u8 params[255];
-} POSTPACK HCI_CMD_PKT;
-
-#define ACL_DATA_HDR_SIZE 4 /* hdl_and flags + data_len */
-/* Data pkt */
-typedef struct hci_acl_data_pkt_t {
- u16 hdl_and_flags;
- u16 data_len;
- u8 data[Max80211_PAL_PDU_Size];
-} POSTPACK HCI_ACL_DATA_PKT;
-
-/* Event pkt */
-typedef struct hci_event_pkt_t {
- u8 event_code;
- u8 param_len;
- u8 params[256];
-} POSTPACK HCI_EVENT_PKT;
-
-
-/*============== HCI Command definitions ======================= */
-typedef struct hci_cmd_phy_link_t {
- u16 opcode;
- u8 param_length;
- u8 phy_link_hdl;
- u8 link_key_len;
- u8 link_key_type;
- u8 link_key[LINK_KEY_LEN];
-} POSTPACK HCI_CMD_PHY_LINK;
-
-typedef struct hci_cmd_write_rem_amp_assoc_t {
- u16 opcode;
- u8 param_length;
- u8 phy_link_hdl;
- u16 len_so_far;
- u16 amp_assoc_remaining_len;
- u8 amp_assoc_frag[AMP_ASSOC_MAX_FRAG_SZ];
-} POSTPACK HCI_CMD_WRITE_REM_AMP_ASSOC;
-
-
-typedef struct hci_cmd_opcode_hdl_t {
- u16 opcode;
- u8 param_length;
- u16 hdl;
-} POSTPACK HCI_CMD_READ_LINK_QUAL,
- HCI_CMD_FLUSH,
- HCI_CMD_READ_LINK_SUPERVISION_TIMEOUT;
-
-typedef struct hci_cmd_read_local_amp_assoc_t {
- u16 opcode;
- u8 param_length;
- u8 phy_link_hdl;
- u16 len_so_far;
- u16 max_rem_amp_assoc_len;
-} POSTPACK HCI_CMD_READ_LOCAL_AMP_ASSOC;
-
-
-typedef struct hci_cmd_set_event_mask_t {
- u16 opcode;
- u8 param_length;
- u64 mask;
-}POSTPACK HCI_CMD_SET_EVT_MASK, HCI_CMD_SET_EVT_MASK_PG_2;
-
-
-typedef struct hci_cmd_enhanced_flush_t{
- u16 opcode;
- u8 param_length;
- u16 hdl;
- u8 type;
-} POSTPACK HCI_CMD_ENHANCED_FLUSH;
-
-
-typedef struct hci_cmd_write_timeout_t {
- u16 opcode;
- u8 param_length;
- u16 timeout;
-} POSTPACK HCI_CMD_WRITE_TIMEOUT;
-
-typedef struct hci_cmd_write_link_supervision_timeout_t {
- u16 opcode;
- u8 param_length;
- u16 hdl;
- u16 timeout;
-} POSTPACK HCI_CMD_WRITE_LINK_SUPERVISION_TIMEOUT;
-
-typedef struct hci_cmd_write_flow_control_t {
- u16 opcode;
- u8 param_length;
- u8 mode;
-} POSTPACK HCI_CMD_WRITE_FLOW_CONTROL;
-
-typedef struct location_data_cfg_t {
- u8 reg_domain_aware;
- u8 reg_domain[3];
- u8 reg_options;
-} POSTPACK LOCATION_DATA_CFG;
-
-typedef struct hci_cmd_write_location_data_t {
- u16 opcode;
- u8 param_length;
- LOCATION_DATA_CFG cfg;
-} POSTPACK HCI_CMD_WRITE_LOCATION_DATA;
-
-
-typedef struct flow_spec_t {
- u8 id;
- u8 service_type;
- u16 max_sdu;
- u32 sdu_inter_arrival_time;
- u32 access_latency;
- u32 flush_timeout;
-} POSTPACK FLOW_SPEC;
-
-
-typedef struct hci_cmd_create_logical_link_t {
- u16 opcode;
- u8 param_length;
- u8 phy_link_hdl;
- FLOW_SPEC tx_flow_spec;
- FLOW_SPEC rx_flow_spec;
-} POSTPACK HCI_CMD_CREATE_LOGICAL_LINK;
-
-typedef struct hci_cmd_flow_spec_modify_t {
- u16 opcode;
- u8 param_length;
- u16 hdl;
- FLOW_SPEC tx_flow_spec;
- FLOW_SPEC rx_flow_spec;
-} POSTPACK HCI_CMD_FLOW_SPEC_MODIFY;
-
-typedef struct hci_cmd_logical_link_cancel_t {
- u16 opcode;
- u8 param_length;
- u8 phy_link_hdl;
- u8 tx_flow_spec_id;
-} POSTPACK HCI_CMD_LOGICAL_LINK_CANCEL;
-
-typedef struct hci_cmd_disconnect_logical_link_t {
- u16 opcode;
- u8 param_length;
- u16 logical_link_hdl;
-} POSTPACK HCI_CMD_DISCONNECT_LOGICAL_LINK;
-
-typedef struct hci_cmd_disconnect_phy_link_t {
- u16 opcode;
- u8 param_length;
- u8 phy_link_hdl;
-} POSTPACK HCI_CMD_DISCONNECT_PHY_LINK;
-
-typedef struct hci_cmd_srm_t {
- u16 opcode;
- u8 param_length;
- u8 phy_link_hdl;
- u8 mode;
-} POSTPACK HCI_CMD_SHORT_RANGE_MODE;
-/*============== HCI Command definitions end ======================= */
-
-
-
-/*============== HCI Event definitions ============================= */
-
-/* Command complete event */
-typedef struct hci_event_cmd_complete_t {
- u8 event_code;
- u8 param_len;
- u8 num_hci_cmd_pkts;
- u16 opcode;
- u8 params[255];
-} POSTPACK HCI_EVENT_CMD_COMPLETE;
-
-
-/* Command status event */
-typedef struct hci_event_cmd_status_t {
- u8 event_code;
- u8 param_len;
- u8 status;
- u8 num_hci_cmd_pkts;
- u16 opcode;
-} POSTPACK HCI_EVENT_CMD_STATUS;
-
-/* Hardware Error event */
-typedef struct hci_event_hw_err_t {
- u8 event_code;
- u8 param_len;
- u8 hw_err_code;
-} POSTPACK HCI_EVENT_HW_ERR;
-
-/* Flush occurred event */
-/* Qos Violation event */
-typedef struct hci_event_handle_t {
- u8 event_code;
- u8 param_len;
- u16 handle;
-} POSTPACK HCI_EVENT_FLUSH_OCCRD,
- HCI_EVENT_QOS_VIOLATION;
-
-/* Loopback command event */
-typedef struct hci_loopback_cmd_t {
- u8 event_code;
- u8 param_len;
- u8 params[252];
-} POSTPACK HCI_EVENT_LOOPBACK_CMD;
-
-/* Data buffer overflow event */
-typedef struct hci_data_buf_overflow_t {
- u8 event_code;
- u8 param_len;
- u8 link_type;
-} POSTPACK HCI_EVENT_DATA_BUF_OVERFLOW;
-
-/* Enhanced Flush complete event */
-typedef struct hci_enhanced_flush_complt_t{
- u8 event_code;
- u8 param_len;
- u16 hdl;
-} POSTPACK HCI_EVENT_ENHANCED_FLUSH_COMPLT;
-
-/* Channel select event */
-typedef struct hci_event_chan_select_t {
- u8 event_code;
- u8 param_len;
- u8 phy_link_hdl;
-} POSTPACK HCI_EVENT_CHAN_SELECT;
-
-/* Physical Link Complete event */
-typedef struct hci_event_phy_link_complete_event_t {
- u8 event_code;
- u8 param_len;
- u8 status;
- u8 phy_link_hdl;
-} POSTPACK HCI_EVENT_PHY_LINK_COMPLETE;
-
-/* Logical Link complete event */
-typedef struct hci_event_logical_link_complete_event_t {
- u8 event_code;
- u8 param_len;
- u8 status;
- u16 logical_link_hdl;
- u8 phy_hdl;
- u8 tx_flow_id;
-} POSTPACK HCI_EVENT_LOGICAL_LINK_COMPLETE_EVENT;
-
-/* Disconnect Logical Link complete event */
-typedef struct hci_event_disconnect_logical_link_event_t {
- u8 event_code;
- u8 param_len;
- u8 status;
- u16 logical_link_hdl;
- u8 reason;
-} POSTPACK HCI_EVENT_DISCONNECT_LOGICAL_LINK_EVENT;
-
-/* Disconnect Physical Link complete event */
-typedef struct hci_event_disconnect_phy_link_complete_t {
- u8 event_code;
- u8 param_len;
- u8 status;
- u8 phy_link_hdl;
- u8 reason;
-} POSTPACK HCI_EVENT_DISCONNECT_PHY_LINK_COMPLETE;
-
-typedef struct hci_event_physical_link_loss_early_warning_t{
- u8 event_code;
- u8 param_len;
- u8 phy_hdl;
- u8 reason;
-} POSTPACK HCI_EVENT_PHY_LINK_LOSS_EARLY_WARNING;
-
-typedef struct hci_event_physical_link_recovery_t{
- u8 event_code;
- u8 param_len;
- u8 phy_hdl;
-} POSTPACK HCI_EVENT_PHY_LINK_RECOVERY;
-
-
-/* Flow spec modify complete event */
-/* Flush event */
-typedef struct hci_event_status_handle_t {
- u8 event_code;
- u8 param_len;
- u8 status;
- u16 handle;
-} POSTPACK HCI_EVENT_FLOW_SPEC_MODIFY,
- HCI_EVENT_FLUSH;
-
-
-/* Num of completed data blocks event */
-typedef struct hci_event_num_of_compl_data_blks_t {
- u8 event_code;
- u8 param_len;
- u16 num_data_blks;
- u8 num_handles;
- u8 params[255];
-} POSTPACK HCI_EVENT_NUM_COMPL_DATA_BLKS;
-
-/* Short range mode change complete event */
-typedef struct hci_srm_cmpl_t {
- u8 event_code;
- u8 param_len;
- u8 status;
- u8 phy_link;
- u8 state;
-} POSTPACK HCI_EVENT_SRM_COMPL;
-
-typedef struct hci_event_amp_status_change_t{
- u8 event_code;
- u8 param_len;
- u8 status;
- u8 amp_status;
-} POSTPACK HCI_EVENT_AMP_STATUS_CHANGE;
-
-/*============== Event definitions end =========================== */
-
-
-typedef struct local_amp_info_resp_t {
- u8 status;
- u8 amp_status;
- u32 total_bw; /* kbps */
- u32 max_guranteed_bw; /* kbps */
- u32 min_latency;
- u32 max_pdu_size;
- u8 amp_type;
- u16 pal_capabilities;
- u16 amp_assoc_len;
- u32 max_flush_timeout; /* in ms */
- u32 be_flush_timeout; /* in ms */
-} POSTPACK LOCAL_AMP_INFO;
-
-typedef struct amp_assoc_cmd_resp_t{
- u8 status;
- u8 phy_hdl;
- u16 amp_assoc_len;
- u8 amp_assoc_frag[AMP_ASSOC_MAX_FRAG_SZ];
-}POSTPACK AMP_ASSOC_CMD_RESP;
-
-
-enum PAL_HCI_CMD_STATUS {
- PAL_HCI_CMD_PROCESSED,
- PAL_HCI_CMD_IGNORED
-};
-
-
-/*============= HCI Error Codes =======================*/
-#define HCI_SUCCESS 0x00
-#define HCI_ERR_UNKNOW_CMD 0x01
-#define HCI_ERR_UNKNOWN_CONN_ID 0x02
-#define HCI_ERR_HW_FAILURE 0x03
-#define HCI_ERR_PAGE_TIMEOUT 0x04
-#define HCI_ERR_AUTH_FAILURE 0x05
-#define HCI_ERR_KEY_MISSING 0x06
-#define HCI_ERR_MEM_CAP_EXECED 0x07
-#define HCI_ERR_CON_TIMEOUT 0x08
-#define HCI_ERR_CON_LIMIT_EXECED 0x09
-#define HCI_ERR_ACL_CONN_ALRDY_EXISTS 0x0B
-#define HCI_ERR_COMMAND_DISALLOWED 0x0C
-#define HCI_ERR_CONN_REJ_BY_LIMIT_RES 0x0D
-#define HCI_ERR_CONN_REJ_BY_SEC 0x0E
-#define HCI_ERR_CONN_REJ_BY_BAD_ADDR 0x0F
-#define HCI_ERR_CONN_ACCPT_TIMEOUT 0x10
-#define HCI_ERR_UNSUPPORT_FEATURE 0x11
-#define HCI_ERR_INVALID_HCI_CMD_PARAMS 0x12
-#define HCI_ERR_REMOTE_USER_TERMINATE_CONN 0x13
-#define HCI_ERR_CON_TERM_BY_HOST 0x16
-#define HCI_ERR_UNSPECIFIED_ERROR 0x1F
-#define HCI_ERR_ENCRYPTION_MODE_NOT_SUPPORT 0x25
-#define HCI_ERR_REQUESTED_QOS_NOT_SUPPORT 0x27
-#define HCI_ERR_QOS_UNACCEPTABLE_PARM 0x2C
-#define HCI_ERR_QOS_REJECTED 0x2D
-#define HCI_ERR_CONN_REJ_NO_SUITABLE_CHAN 0x39
-
-/*============= HCI Error Codes End =======================*/
-
-
-/* Following are event return parameters.. part of HCI events
- */
-typedef struct timeout_read_t {
- u8 status;
- u16 timeout;
-}POSTPACK TIMEOUT_INFO;
-
-typedef struct link_supervision_timeout_read_t {
- u8 status;
- u16 hdl;
- u16 timeout;
-}POSTPACK LINK_SUPERVISION_TIMEOUT_INFO;
-
-typedef struct status_hdl_t {
- u8 status;
- u16 hdl;
-}POSTPACK INFO_STATUS_HDL;
-
-typedef struct write_remote_amp_assoc_t{
- u8 status;
- u8 hdl;
-}POSTPACK WRITE_REMOTE_AMP_ASSOC_INFO;
-
-typedef struct read_loc_info_t {
- u8 status;
- LOCATION_DATA_CFG loc;
-}POSTPACK READ_LOC_INFO;
-
-typedef struct read_flow_ctrl_mode_t {
- u8 status;
- u8 mode;
-}POSTPACK READ_FLWCTRL_INFO;
-
-typedef struct read_data_blk_size_t {
- u8 status;
- u16 max_acl_data_pkt_len;
- u16 data_block_len;
- u16 total_num_data_blks;
-}POSTPACK READ_DATA_BLK_SIZE_INFO;
-
-/* Read Link quality info */
-typedef struct link_qual_t {
- u8 status;
- u16 hdl;
- u8 link_qual;
-} POSTPACK READ_LINK_QUAL_INFO,
- READ_RSSI_INFO;
-
-typedef struct ll_cancel_resp_t {
- u8 status;
- u8 phy_link_hdl;
- u8 tx_flow_spec_id;
-} POSTPACK LL_CANCEL_RESP;
-
-typedef struct read_local_ver_info_t {
- u8 status;
- u8 hci_version;
- u16 hci_revision;
- u8 pal_version;
- u16 manf_name;
- u16 pal_sub_ver;
-} POSTPACK READ_LOCAL_VER_INFO;
-
-
-#endif /* __A_HCI_H__ */
diff --git a/drivers/staging/ath6kl/include/common/bmi_msg.h b/drivers/staging/ath6kl/include/common/bmi_msg.h
index e76624c..84e8db5 100644
--- a/drivers/staging/ath6kl/include/common/bmi_msg.h
+++ b/drivers/staging/ath6kl/include/common/bmi_msg.h
@@ -22,10 +22,6 @@
#ifndef __BMI_MSG_H__
#define __BMI_MSG_H__
-#ifndef ATH_TARGET
-#include "athstartpack.h"
-#endif
-
/*
* Bootloader Messaging Interface (BMI)
*
@@ -234,8 +230,4 @@
* Note: Not supported on all versions of ROM firmware.
*/
-#ifndef ATH_TARGET
-#include "athendpack.h"
-#endif
-
#endif /* __BMI_MSG_H__ */
diff --git a/drivers/staging/ath6kl/include/common/btcoexGpio.h b/drivers/staging/ath6kl/include/common/btcoexGpio.h
deleted file mode 100644
index 9d5a239..0000000
--- a/drivers/staging/ath6kl/include/common/btcoexGpio.h
+++ /dev/null
@@ -1,86 +0,0 @@
-// Copyright (c) 2010 Atheros Communications Inc.
-// All rights reserved.
-//
-//
-// Permission to use, copy, modify, and/or distribute this software for any
-// purpose with or without fee is hereby granted, provided that the above
-// copyright notice and this permission notice appear in all copies.
-//
-// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-//
-//
-
-#ifndef BTCOEX_GPIO_H_
-#define BTCOEX_GPIO_H_
-
-
-
-#ifdef FPGA
-#define GPIO_A (15)
-#define GPIO_B (16)
-#define GPIO_C (17)
-#define GPIO_D (18)
-#define GPIO_E (19)
-#define GPIO_F (21)
-#define GPIO_G (21)
-#else
-#define GPIO_A (0)
-#define GPIO_B (5)
-#define GPIO_C (6)
-#define GPIO_D (7)
-#define GPIO_E (7)
-#define GPIO_F (7)
-#define GPIO_G (7)
-#endif
-
-
-
-
-
-#define GPIO_DEBUG_WORD_1 (1<<GPIO_A)
-#define GPIO_DEBUG_WORD_2 (1<<GPIO_B)
-#define GPIO_DEBUG_WORD_3 ((1<<GPIO_B) | (1<<GPIO_A))
-#define GPIO_DEBUG_WORD_4 (1<<GPIO_C)
-#define GPIO_DEBUG_WORD_5 ((1<<GPIO_C) | (1<<GPIO_A))
-#define GPIO_DEBUG_WORD_6 ((1<<GPIO_C) | (1<<GPIO_B))
-#define GPIO_DEBUG_WORD_7 ((1<<GPIO_C) | (1<<GPIO_B) | (1<<GPIO_A))
-
-#define GPIO_DEBUG_WORD_8 (1<<GPIO_D)
-#define GPIO_DEBUG_WORD_9 ((1<<GPIO_D) | GPIO_DEBUG_WORD_1)
-#define GPIO_DEBUG_WORD_10 ((1<<GPIO_D) | GPIO_DEBUG_WORD_2)
-#define GPIO_DEBUG_WORD_11 ((1<<GPIO_D) | GPIO_DEBUG_WORD_3)
-#define GPIO_DEBUG_WORD_12 ((1<<GPIO_D) | GPIO_DEBUG_WORD_4)
-#define GPIO_DEBUG_WORD_13 ((1<<GPIO_D) | GPIO_DEBUG_WORD_5)
-#define GPIO_DEBUG_WORD_14 ((1<<GPIO_D) | GPIO_DEBUG_WORD_6)
-#define GPIO_DEBUG_WORD_15 ((1<<GPIO_D) | GPIO_DEBUG_WORD_7)
-
-#define GPIO_DEBUG_WORD_16 (1<<GPIO_E)
-#define GPIO_DEBUG_WORD_17 ((1<<GPIO_E) | GPIO_DEBUG_WORD_1)
-#define GPIO_DEBUG_WORD_18 ((1<<GPIO_E) | GPIO_DEBUG_WORD_2)
-#define GPIO_DEBUG_WORD_19 ((1<<GPIO_E) | GPIO_DEBUG_WORD_3)
-#define GPIO_DEBUG_WORD_20 ((1<<GPIO_E) | GPIO_DEBUG_WORD_4)
-#define GPIO_DEBUG_WORD_21 ((1<<GPIO_E) | GPIO_DEBUG_WORD_5)
-#define GPIO_DEBUG_WORD_22 ((1<<GPIO_E) | GPIO_DEBUG_WORD_6)
-#define GPIO_DEBUG_WORD_23 ((1<<GPIO_E) | GPIO_DEBUG_WORD_7)
-
-
-
-extern void btcoexDbgPulseWord(u32 gpioPinMask);
-extern void btcoexDbgPulse(u32 pin);
-
-#ifdef CONFIG_BTCOEX_ENABLE_GPIO_DEBUG
-#define BTCOEX_DBG_PULSE_WORD(gpioPinMask) (btcoexDbgPulseWord(gpioPinMask))
-#define BTCOEX_DBG_PULSE(pin) (btcoexDbgPulse(pin))
-#else
-#define BTCOEX_DBG_PULSE_WORD(gpioPinMask)
-#define BTCOEX_DBG_PULSE(pin)
-
-#endif
-#endif
-
diff --git a/drivers/staging/ath6kl/include/common/dbglog.h b/drivers/staging/ath6kl/include/common/dbglog.h
index b7a1230..5566e56 100644
--- a/drivers/staging/ath6kl/include/common/dbglog.h
+++ b/drivers/staging/ath6kl/include/common/dbglog.h
@@ -24,10 +24,6 @@
#ifndef _DBGLOG_H_
#define _DBGLOG_H_
-#ifndef ATH_TARGET
-#include "athstartpack.h"
-#endif
-
#ifdef __cplusplus
extern "C" {
#endif
@@ -127,8 +123,4 @@
}
#endif
-#ifndef ATH_TARGET
-#include "athendpack.h"
-#endif
-
#endif /* _DBGLOG_H_ */
diff --git a/drivers/staging/ath6kl/include/common/dset_internal.h b/drivers/staging/ath6kl/include/common/dset_internal.h
deleted file mode 100644
index 6947533..0000000
--- a/drivers/staging/ath6kl/include/common/dset_internal.h
+++ /dev/null
@@ -1,63 +0,0 @@
-//------------------------------------------------------------------------------
-// <copyright file="dset_internal.h" company="Atheros">
-// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
-//
-//
-// Permission to use, copy, modify, and/or distribute this software for any
-// purpose with or without fee is hereby granted, provided that the above
-// copyright notice and this permission notice appear in all copies.
-//
-// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-//
-//
-//------------------------------------------------------------------------------
-//==============================================================================
-// Author(s): ="Atheros"
-//==============================================================================
-
-
-#ifndef __DSET_INTERNAL_H__
-#define __DSET_INTERNAL_H__
-
-#ifndef ATH_TARGET
-#include "athstartpack.h"
-#endif
-
-/*
- * Internal dset definitions, common for DataSet layer.
- */
-
-#define DSET_TYPE_STANDARD 0
-#define DSET_TYPE_BPATCHED 1
-#define DSET_TYPE_COMPRESSED 2
-
-/* Dataset descriptor */
-
-typedef PREPACK struct dset_descriptor_s {
- struct dset_descriptor_s *next; /* List link. NULL only at the last
- descriptor */
- u16 id; /* Dset ID */
- u16 size; /* Dset size. */
- void *DataPtr; /* Pointer to raw data for standard
- DataSet or pointer to original
- dset_descriptor for patched
- DataSet */
- u32 data_type; /* DSET_TYPE_*, above */
-
- void *AuxPtr; /* Additional data that might
- needed for data_type. For
- example, pointer to patch
- Dataset descriptor for BPatch. */
-} POSTPACK dset_descriptor_t;
-
-#ifndef ATH_TARGET
-#include "athendpack.h"
-#endif
-
-#endif /* __DSET_INTERNAL_H__ */
diff --git a/drivers/staging/ath6kl/include/common/dsetid.h b/drivers/staging/ath6kl/include/common/dsetid.h
deleted file mode 100644
index 090e309..0000000
--- a/drivers/staging/ath6kl/include/common/dsetid.h
+++ /dev/null
@@ -1,134 +0,0 @@
-//------------------------------------------------------------------------------
-// <copyright file="dsetid.h" company="Atheros">
-// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
-//
-//
-// Permission to use, copy, modify, and/or distribute this software for any
-// purpose with or without fee is hereby granted, provided that the above
-// copyright notice and this permission notice appear in all copies.
-//
-// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-//
-//
-//------------------------------------------------------------------------------
-//==============================================================================
-// Author(s): ="Atheros"
-//==============================================================================
-
-
-#ifndef __DSETID_H__
-#define __DSETID_H__
-
-#ifndef ATH_TARGET
-#include "athstartpack.h"
-#endif
-
-/* Well-known DataSet IDs */
-#define DSETID_UNUSED 0x00000000
-#define DSETID_BOARD_DATA 0x00000001 /* Cal and board data */
-#define DSETID_REGDB 0x00000002 /* Regulatory Database */
-#define DSETID_POWER_CONTROL 0x00000003 /* TX Pwr Lim & Ant Gain */
-#define DSETID_USER_CONFIG 0x00000004 /* User Configuration */
-
-#define DSETID_ANALOG_CONTROL_DATA_START 0x00000005
-#define DSETID_ANALOG_CONTROL_DATA_END 0x00000025
-/*
- * Get DSETID for various reference clock speeds.
- * For each speed there are three DataSets that correspond
- * to the three columns of bank6 data (addr, 11a, 11b/g).
- * This macro returns the dsetid of the first of those
- * three DataSets.
- */
-#define ANALOG_CONTROL_DATA_DSETID(refclk) \
- (DSETID_ANALOG_CONTROL_DATA_START + 3*refclk)
-
-/*
- * There are TWO STARTUP_PATCH DataSets.
- * DSETID_STARTUP_PATCH is historical, and was applied before BMI on
- * earlier systems. On AR6002, it is applied after BMI, just like
- * DSETID_STARTUP_PATCH2.
- */
-#define DSETID_STARTUP_PATCH 0x00000026
-#define DSETID_GPIO_CONFIG_PATCH 0x00000027
-#define DSETID_WLANREGS 0x00000028 /* override wlan regs */
-#define DSETID_STARTUP_PATCH2 0x00000029
-
-#define DSETID_WOW_CONFIG 0x00000090 /* WoW Configuration */
-
-/* Add WHAL_INI_DATA_ID to DSETID_INI_DATA for a specific WHAL INI table. */
-#define DSETID_INI_DATA 0x00000100
-/* Reserved for WHAL INI Tables: 0x100..0x11f */
-#define DSETID_INI_DATA_END 0x0000011f
-
-#define DSETID_VENDOR_START 0x00010000 /* Vendor-defined DataSets */
-
-#define DSETID_INDEX_END 0xfffffffe /* Reserved to indicate the
- end of a memory-based
- DataSet Index */
-#define DSETID_INDEX_FREE 0xffffffff /* An unused index entry */
-
-/*
- * PATCH DataSet format:
- * A list of patches, terminated by a patch with
- * address=PATCH_END.
- *
- * This allows for patches to be stored in flash.
- */
-PREPACK struct patch_s {
- u32 *address;
- u32 data;
-} POSTPACK ;
-
-/*
- * Skip some patches. Can be used to erase a single patch in a
- * patch DataSet without having to re-write the DataSet. May
- * also be used to embed information for use by subsequent
- * patch code. The "data" in a PATCH_SKIP tells how many
- * bytes of length "patch_s" to skip.
- */
-#define PATCH_SKIP ((u32 *)0x00000000)
-
-/*
- * Execute code at the address specified by "data".
- * The address of the patch structure is passed as
- * the one parameter.
- */
-#define PATCH_CODE_ABS ((u32 *)0x00000001)
-
-/*
- * Same as PATCH_CODE_ABS, but treat "data" as an
- * offset from the start of the patch word.
- */
-#define PATCH_CODE_REL ((u32 *)0x00000002)
-
-/* Mark the end of this patch DataSet. */
-#define PATCH_END ((u32 *)0xffffffff)
-
-/*
- * A DataSet which contains a Binary Patch to some other DataSet
- * uses the original dsetid with the DSETID_BPATCH_FLAG bit set.
- * Such a BPatch DataSet consists of BPatch metadata followed by
- * the bdiff bytes. BPatch metadata consists of a single 32-bit
- * word that contains the size of the BPatched final image.
- *
- * To create a suitable bdiff DataSet, use bdiff in host/tools/bdiff
- * to create "diffs":
- * bdiff -q -O -nooldmd5 -nonewmd5 -d ORIGfile NEWfile diffs
- * Then add BPatch metadata to the start of "diffs".
- *
- * NB: There are some implementation-induced restrictions
- * on which DataSets can be BPatched.
- */
-#define DSETID_BPATCH_FLAG 0x80000000
-
-#ifndef ATH_TARGET
-#include "athendpack.h"
-#endif
-
-#endif /* __DSETID_H__ */
diff --git a/drivers/staging/ath6kl/include/common/epping_test.h b/drivers/staging/ath6kl/include/common/epping_test.h
index 7027fac..9eb5fdf 100644
--- a/drivers/staging/ath6kl/include/common/epping_test.h
+++ b/drivers/staging/ath6kl/include/common/epping_test.h
@@ -25,10 +25,6 @@
#ifndef EPPING_TEST_H_
#define EPPING_TEST_H_
-#ifndef ATH_TARGET
-#include "athstartpack.h"
-#endif
-
/* alignment to 4-bytes */
#define EPPING_ALIGNMENT_PAD (((sizeof(struct htc_frame_hdr) + 3) & (~0x3)) - sizeof(struct htc_frame_hdr))
@@ -112,9 +108,4 @@
#define HCI_TRANSPORT_STREAM_NUM 16 /* this number is higher than the define WMM AC classes so we
can use this to distinguish packets */
-#ifndef ATH_TARGET
-#include "athendpack.h"
-#endif
-
-
#endif /*EPPING_TEST_H_*/
diff --git a/drivers/staging/ath6kl/include/common/gmboxif.h b/drivers/staging/ath6kl/include/common/gmboxif.h
index dd9afbd..ea11c14 100644
--- a/drivers/staging/ath6kl/include/common/gmboxif.h
+++ b/drivers/staging/ath6kl/include/common/gmboxif.h
@@ -23,10 +23,6 @@
#ifndef __GMBOXIF_H__
#define __GMBOXIF_H__
-#ifndef ATH_TARGET
-#include "athstartpack.h"
-#endif
-
/* GMBOX interface definitions */
#define AR6K_GMBOX_CREDIT_COUNTER 1 /* we use credit counter 1 to track credits */
@@ -70,9 +66,5 @@
#define MBOX_SIG_HCI_BRIDGE_PWR_SAV_OFF 4
-#ifndef ATH_TARGET
-#include "athendpack.h"
-#endif
-
#endif /* __GMBOXIF_H__ */
diff --git a/drivers/staging/ath6kl/include/common/gpio.h b/drivers/staging/ath6kl/include/common/gpio.h
deleted file mode 100644
index f723066..0000000
--- a/drivers/staging/ath6kl/include/common/gpio.h
+++ /dev/null
@@ -1,45 +0,0 @@
-//------------------------------------------------------------------------------
-// Copyright (c) 2005-2010 Atheros Corporation. All rights reserved.
-//
-//
-// Permission to use, copy, modify, and/or distribute this software for any
-// purpose with or without fee is hereby granted, provided that the above
-// copyright notice and this permission notice appear in all copies.
-//
-// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-//
-//
-//
-// Author(s): ="Atheros"
-//------------------------------------------------------------------------------
-
-#define AR6001_GPIO_PIN_COUNT 18
-#define AR6002_GPIO_PIN_COUNT 18
-#define AR6003_GPIO_PIN_COUNT 28
-
-/*
- * Possible values for WMIX_GPIO_SET_REGISTER_CMDID.
- * NB: These match hardware order, so that addresses can
- * easily be computed.
- */
-#define GPIO_ID_OUT 0x00000000
-#define GPIO_ID_OUT_W1TS 0x00000001
-#define GPIO_ID_OUT_W1TC 0x00000002
-#define GPIO_ID_ENABLE 0x00000003
-#define GPIO_ID_ENABLE_W1TS 0x00000004
-#define GPIO_ID_ENABLE_W1TC 0x00000005
-#define GPIO_ID_IN 0x00000006
-#define GPIO_ID_STATUS 0x00000007
-#define GPIO_ID_STATUS_W1TS 0x00000008
-#define GPIO_ID_STATUS_W1TC 0x00000009
-#define GPIO_ID_PIN0 0x0000000a
-#define GPIO_ID_PIN(n) (GPIO_ID_PIN0+(n))
-
-#define GPIO_LAST_REGISTER_ID GPIO_ID_PIN(17)
-#define GPIO_ID_NONE 0xffffffff
diff --git a/drivers/staging/ath6kl/include/common/gpio_reg.h b/drivers/staging/ath6kl/include/common/gpio_reg.h
new file mode 100644
index 0000000..f9d425d
--- /dev/null
+++ b/drivers/staging/ath6kl/include/common/gpio_reg.h
@@ -0,0 +1,9 @@
+#ifndef _GPIO_REG_REG_H_
+#define _GPIO_REG_REG_H_
+
+#define GPIO_PIN10_ADDRESS 0x00000050
+#define GPIO_PIN11_ADDRESS 0x00000054
+#define GPIO_PIN12_ADDRESS 0x00000058
+#define GPIO_PIN13_ADDRESS 0x0000005c
+
+#endif /* _GPIO_REG_H_ */
diff --git a/drivers/staging/ath6kl/include/common/htc.h b/drivers/staging/ath6kl/include/common/htc.h
index b9d4495..85cbfa8 100644
--- a/drivers/staging/ath6kl/include/common/htc.h
+++ b/drivers/staging/ath6kl/include/common/htc.h
@@ -24,10 +24,6 @@
#ifndef __HTC_H__
#define __HTC_H__
-#ifndef ATH_TARGET
-#include "athstartpack.h"
-#endif
-
#define A_OFFSETOF(type,field) (unsigned long)(&(((type *)NULL)->field))
#define ASSEMBLE_UNALIGNED_UINT16(p,highbyte,lowbyte) \
@@ -227,10 +223,5 @@
u8 LookAhead[4]; /* 4 byte lookahead */
} POSTPACK HTC_BUNDLED_LOOKAHEAD_REPORT;
-#ifndef ATH_TARGET
-#include "athendpack.h"
-#endif
-
-
#endif /* __HTC_H__ */
diff --git a/drivers/staging/ath6kl/include/common/ini_dset.h b/drivers/staging/ath6kl/include/common/ini_dset.h
deleted file mode 100644
index a9e05fa..0000000
--- a/drivers/staging/ath6kl/include/common/ini_dset.h
+++ /dev/null
@@ -1,82 +0,0 @@
-//------------------------------------------------------------------------------
-// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
-//
-//
-// Permission to use, copy, modify, and/or distribute this software for any
-// purpose with or without fee is hereby granted, provided that the above
-// copyright notice and this permission notice appear in all copies.
-//
-// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-//
-//
-//
-// Author(s): ="Atheros"
-//------------------------------------------------------------------------------
-
-#ifndef _INI_DSET_H_
-#define _INI_DSET_H_
-
-/*
- * Each of these represents a WHAL INI table, which consists
- * of an "address column" followed by 1 or more "value columns".
- *
- * Software uses the base WHAL_INI_DATA_ID+column to access a
- * DataSet that holds a particular column of data.
- */
-typedef enum {
-#if defined(AR6002_REV4) || defined(AR6003)
-/* Add these definitions for compatibility */
-#define WHAL_INI_DATA_ID_BB_RFGAIN_LNA1 WHAL_INI_DATA_ID_BB_RFGAIN
-#define WHAL_INI_DATA_ID_BB_RFGAIN_LNA2 WHAL_INI_DATA_ID_BB_RFGAIN
- WHAL_INI_DATA_ID_NULL =0,
- WHAL_INI_DATA_ID_MODE_SPECIFIC =1, /* 2,3,4,5 */
- WHAL_INI_DATA_ID_COMMON =6, /* 7 */
- WHAL_INI_DATA_ID_BB_RFGAIN =8, /* 9,10 */
-#ifdef FPGA
- WHAL_INI_DATA_ID_ANALOG_BANK0 =11, /* 12 */
- WHAL_INI_DATA_ID_ANALOG_BANK1 =13, /* 14 */
- WHAL_INI_DATA_ID_ANALOG_BANK2 =15, /* 16 */
- WHAL_INI_DATA_ID_ANALOG_BANK3 =17, /* 18, 19 */
- WHAL_INI_DATA_ID_ANALOG_BANK6 =20, /* 21,22 */
- WHAL_INI_DATA_ID_ANALOG_BANK7 =23, /* 24 */
- WHAL_INI_DATA_ID_ADDAC =25, /* 26 */
-#else
- WHAL_INI_DATA_ID_ANALOG_COMMON =11, /* 12 */
- WHAL_INI_DATA_ID_ANALOG_MODE_SPECIFIC=13, /* 14,15 */
- WHAL_INI_DATA_ID_ANALOG_BANK6 =16, /* 17,18 */
- WHAL_INI_DATA_ID_MODE_OVERRIDES =19, /* 20,21,22,23 */
- WHAL_INI_DATA_ID_COMMON_OVERRIDES =24, /* 25 */
- WHAL_INI_DATA_ID_ANALOG_OVERRIDES =26, /* 27,28 */
-#endif /* FPGA */
-#else
- WHAL_INI_DATA_ID_NULL =0,
- WHAL_INI_DATA_ID_MODE_SPECIFIC =1, /* 2,3 */
- WHAL_INI_DATA_ID_COMMON =4, /* 5 */
- WHAL_INI_DATA_ID_BB_RFGAIN =6, /* 7,8 */
-#define WHAL_INI_DATA_ID_BB_RFGAIN_LNA1 WHAL_INI_DATA_ID_BB_RFGAIN
- WHAL_INI_DATA_ID_ANALOG_BANK1 =9, /* 10 */
- WHAL_INI_DATA_ID_ANALOG_BANK2 =11, /* 12 */
- WHAL_INI_DATA_ID_ANALOG_BANK3 =13, /* 14, 15 */
- WHAL_INI_DATA_ID_ANALOG_BANK6 =16, /* 17, 18 */
- WHAL_INI_DATA_ID_ANALOG_BANK7 =19, /* 20 */
- WHAL_INI_DATA_ID_MODE_OVERRIDES =21, /* 22,23 */
- WHAL_INI_DATA_ID_COMMON_OVERRIDES =24, /* 25 */
- WHAL_INI_DATA_ID_ANALOG_OVERRIDES =26, /* 27,28 */
- WHAL_INI_DATA_ID_BB_RFGAIN_LNA2 =29, /* 30,31 */
-#endif
- WHAL_INI_DATA_ID_MAX =31
-} WHAL_INI_DATA_ID;
-
-typedef PREPACK struct {
- u16 freqIndex; // 1 - A mode 2 - B or G mode 0 - common
- u16 offset;
- u32 newValue;
-} POSTPACK INI_DSET_REG_OVERRIDE;
-
-#endif
diff --git a/drivers/staging/ath6kl/include/common/regDb.h b/drivers/staging/ath6kl/include/common/regDb.h
deleted file mode 100644
index f8245f1..0000000
--- a/drivers/staging/ath6kl/include/common/regDb.h
+++ /dev/null
@@ -1,29 +0,0 @@
-//------------------------------------------------------------------------------
-// Copyright (c) 2005-2010 Atheros Corporation. All rights reserved.
-//
-//
-// Permission to use, copy, modify, and/or distribute this software for any
-// purpose with or without fee is hereby granted, provided that the above
-// copyright notice and this permission notice appear in all copies.
-//
-// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-//
-//
-//------------------------------------------------------------------------------
-//==============================================================================
-// Author(s): ="Atheros"
-//==============================================================================
-
-#ifndef __REG_DB_H__
-#define __REG_DB_H__
-
-#include "./regulatory/reg_dbschema.h"
-#include "./regulatory/reg_dbvalues.h"
-
-#endif /* __REG_DB_H__ */
diff --git a/drivers/staging/ath6kl/include/common/regdump.h b/drivers/staging/ath6kl/include/common/regdump.h
deleted file mode 100644
index aa64821..0000000
--- a/drivers/staging/ath6kl/include/common/regdump.h
+++ /dev/null
@@ -1,59 +0,0 @@
-//------------------------------------------------------------------------------
-// <copyright file="regdump.h" company="Atheros">
-// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
-//
-//
-// Permission to use, copy, modify, and/or distribute this software for any
-// purpose with or without fee is hereby granted, provided that the above
-// copyright notice and this permission notice appear in all copies.
-//
-// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-//
-//
-//------------------------------------------------------------------------------
-//==============================================================================
-// Author(s): ="Atheros"
-//==============================================================================
-
-#ifndef __REGDUMP_H__
-#define __REGDUMP_H__
-
-#ifndef ATH_TARGET
-#include "athstartpack.h"
-#endif
-
-#if defined(AR6001)
-#include "AR6001/AR6001_regdump.h"
-#endif
-#if defined(AR6002)
-#include "AR6002/AR6002_regdump.h"
-#endif
-
-#if !defined(__ASSEMBLER__)
-/*
- * Target CPU state at the time of failure is reflected
- * in a register dump, which the Host can fetch through
- * the diagnostic window.
- */
-PREPACK struct register_dump_s {
- u32 target_id; /* Target ID */
- u32 assline; /* Line number (if assertion failure) */
- u32 pc; /* Program Counter at time of exception */
- u32 badvaddr; /* Virtual address causing exception */
- CPU_exception_frame_t exc_frame; /* CPU-specific exception info */
-
- /* Could copy top of stack here, too.... */
-} POSTPACK;
-#endif /* __ASSEMBLER__ */
-
-#ifndef ATH_TARGET
-#include "athendpack.h"
-#endif
-
-#endif /* __REGDUMP_H__ */
diff --git a/drivers/staging/ath6kl/include/common/regulatory/reg_dbschema.h b/drivers/staging/ath6kl/include/common/regulatory/reg_dbschema.h
deleted file mode 100644
index 4904040..0000000
--- a/drivers/staging/ath6kl/include/common/regulatory/reg_dbschema.h
+++ /dev/null
@@ -1,237 +0,0 @@
-//------------------------------------------------------------------------------
-// Copyright (c) 2005-2010 Atheros Corporation. All rights reserved.
-//
-//
-// Permission to use, copy, modify, and/or distribute this software for any
-// purpose with or without fee is hereby granted, provided that the above
-// copyright notice and this permission notice appear in all copies.
-//
-// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-//
-//
-//------------------------------------------------------------------------------
-//==============================================================================
-// Author(s): ="Atheros"
-//==============================================================================
-
-#ifndef __REG_DBSCHEMA_H__
-#define __REG_DBSCHEMA_H__
-
-/*
- * This file describes the regulatory DB schema, which is common between the
- * 'generator' and 'parser'. The 'generator' runs on a host(typically a x86
- * Linux) and spits outs two binary files, which follow the DB file
- * format(described below). The resultant output "regulatoryData_AG.bin"
- * is binary file which has information regarding A and G regulatory
- * information, while the "regulatoryData_G.bin" consists of G-ONLY regulatory
- * information. This binary file is parsed in the target for extracting
- * regulatory information.
- *
- * The DB values used to populate the regulatory DB are defined in
- * reg_dbvalues.h
- *
- */
-
-/* Binary data file - Representation of Regulatory DB*/
-#define REG_DATA_FILE_AG "./regulatoryData_AG.bin"
-#define REG_DATA_FILE_G "./regulatoryData_G.bin"
-
-
-/* Table tags used to encode different tables in the database */
-enum data_tags_t{
- REG_DMN_PAIR_MAPPING_TAG = 0,
- REG_COUNTRY_CODE_TO_ENUM_RD_TAG,
- REG_DMN_FREQ_BAND_regDmn5GhzFreq_TAG,
- REG_DMN_FREQ_BAND_regDmn2Ghz11_BG_Freq_TAG,
- REG_DOMAIN_TAG,
- MAX_DB_TABLE_TAGS
- };
-
-
-
-/*
- ****************************************************************************
- * Regulatory DB file format :
- * 4-bytes : "RGDB" (Magic Key)
- * 4-bytes : version (Default is 5379(my extn))
- * 4-bytes : length of file
- * dbType(4)
- * TAG(4)
- * Entries(1)entrySize(1)searchType(1)reserved[3]tableSize(2)"0xdeadbeef"(4)struct_data....
- * TAG(4)
- * Entries(1)entrySize(1)searchType(1)reserved[3]tableSize(2)"0xdeadbeef"(4)struct_data....
- * TAG(4)
- * Entries(1)entrySize(1)searchType(1)reserved[3]tableSize(2)"0xdeadbeef"(4)struct_data....
- * ...
- * ...
- ****************************************************************************
- *
- */
-
-/*
- * Length of the file would be filled in when the file is created and
- * it would include the header size.
- */
-
-#define REG_DB_KEY "RGDB" /* Should be EXACTLY 4-bytes */
-#define REG_DB_VER 7802 /* Between 0-9999 */
-/* REG_DB_VER history in reverse chronological order:
- * 7802: 78 (ASCII code of N) + 02 (minor version number) - updated 10/21/09
- * 7801: 78 (ASCII code of N) + 01 (minor version number, increment on further changes)
- * 1178: '11N' = 11 + ASCII code of N(78)
- * 5379: initial version, no 11N support
- */
-#define MAGIC_KEY_OFFSET 0
-#define VERSION_OFFSET 4
-#define FILE_SZ_OFFSET 8
-#define DB_TYPE_OFFSET 12
-
-#define MAGIC_KEY_SZ 4
-#define VERSION_SZ 4
-#define FILE_SZ_SZ 4
-#define DB_TYPE_SZ 4
-#define DB_TAG_SZ 4
-
-#define REGDB_GET_MAGICKEY(x) ((char *)x + MAGIC_KEY_OFFSET)
-#define REGDB_GET_VERSION(x) ((char *)x + VERSION_OFFSET)
-#define REGDB_GET_FILESIZE(x) *((unsigned int *)((char *)x + FILE_SZ_OFFSET))
-#define REGDB_GET_DBTYPE(x) *((char *)x + DB_TYPE_OFFSET)
-
-#define REGDB_SET_FILESIZE(x, sz_) *((unsigned int *)((char *)x + FILE_SZ_OFFSET)) = (sz_)
-#define REGDB_IS_EOF(cur, begin) ( REGDB_GET_FILESIZE(begin) > ((cur) - (begin)) )
-
-
-/* A Table can be search based on key as a parameter or accessed directly
- * by giving its index in to the table.
- */
-enum searchType {
- KEY_BASED_TABLE_SEARCH = 1,
- INDEX_BASED_TABLE_ACCESS
- };
-
-
-/* Data is organised as different tables. There is a Master table, which
- * holds information regarding all the tables. It does not have any
- * knowledge about the attributes of the table it is holding
- * but has external view of the same(for ex, how many entries, record size,
- * how to search the table, total table size and reference to the data
- * instance of table).
- */
-typedef PREPACK struct dbMasterTable_t { /* Hold ptrs to Table data structures */
- u8 numOfEntries;
- char entrySize; /* Entry size per table row */
- char searchType; /* Index based access or key based */
- char reserved[3]; /* for alignment */
- u16 tableSize; /* Size of this table */
- char *dataPtr; /* Ptr to the actual Table */
-} POSTPACK dbMasterTable; /* Master table - table of tables */
-
-
-/* used to get the number of rows in a table */
-#define REGDB_NUM_OF_ROWS(a) (sizeof (a) / sizeof (a[0]))
-
-/*
- * Used to set the RegDomain bitmask which chooses which frequency
- * band specs are used.
- */
-
-#define BMLEN 2 /* Use 2 32-bit uint for channel bitmask */
-#define BMZERO {0,0} /* BMLEN zeros */
-
-#define BM(_fa, _fb, _fc, _fd, _fe, _ff, _fg, _fh) \
- {((((_fa >= 0) && (_fa < 32)) ? (((u32) 1) << _fa) : 0) | \
- (((_fb >= 0) && (_fb < 32)) ? (((u32) 1) << _fb) : 0) | \
- (((_fc >= 0) && (_fc < 32)) ? (((u32) 1) << _fc) : 0) | \
- (((_fd >= 0) && (_fd < 32)) ? (((u32) 1) << _fd) : 0) | \
- (((_fe >= 0) && (_fe < 32)) ? (((u32) 1) << _fe) : 0) | \
- (((_ff >= 0) && (_ff < 32)) ? (((u32) 1) << _ff) : 0) | \
- (((_fg >= 0) && (_fg < 32)) ? (((u32) 1) << _fg) : 0) | \
- (((_fh >= 0) && (_fh < 32)) ? (((u32) 1) << _fh) : 0)), \
- ((((_fa > 31) && (_fa < 64)) ? (((u32) 1) << (_fa - 32)) : 0) | \
- (((_fb > 31) && (_fb < 64)) ? (((u32) 1) << (_fb - 32)) : 0) | \
- (((_fc > 31) && (_fc < 64)) ? (((u32) 1) << (_fc - 32)) : 0) | \
- (((_fd > 31) && (_fd < 64)) ? (((u32) 1) << (_fd - 32)) : 0) | \
- (((_fe > 31) && (_fe < 64)) ? (((u32) 1) << (_fe - 32)) : 0) | \
- (((_ff > 31) && (_ff < 64)) ? (((u32) 1) << (_ff - 32)) : 0) | \
- (((_fg > 31) && (_fg < 64)) ? (((u32) 1) << (_fg - 32)) : 0) | \
- (((_fh > 31) && (_fh < 64)) ? (((u32) 1) << (_fh - 32)) : 0))}
-
-
-/*
- * THE following table is the mapping of regdomain pairs specified by
- * a regdomain value to the individual unitary reg domains
- */
-
-typedef PREPACK struct reg_dmn_pair_mapping {
- u16 regDmnEnum; /* 16 bit reg domain pair */
- u16 regDmn5GHz; /* 5GHz reg domain */
- u16 regDmn2GHz; /* 2GHz reg domain */
- u8 flags5GHz; /* Requirements flags (AdHoc disallow etc) */
- u8 flags2GHz; /* Requirements flags (AdHoc disallow etc) */
- u32 pscanMask; /* Passive Scan flags which can override unitary domain passive scan
- flags. This value is used as a mask on the unitary flags*/
-} POSTPACK REG_DMN_PAIR_MAPPING;
-
-#define OFDM_YES (1 << 0)
-#define OFDM_NO (0 << 0)
-#define MCS_HT20_YES (1 << 1)
-#define MCS_HT20_NO (0 << 1)
-#define MCS_HT40_A_YES (1 << 2)
-#define MCS_HT40_A_NO (0 << 2)
-#define MCS_HT40_G_YES (1 << 3)
-#define MCS_HT40_G_NO (0 << 3)
-
-typedef PREPACK struct {
- u16 countryCode;
- u16 regDmnEnum;
- char isoName[3];
- char allowMode; /* what mode is allowed - bit 0: OFDM; bit 1: MCS_HT20; bit 2: MCS_HT40_A; bit 3: MCS_HT40_G */
-} POSTPACK COUNTRY_CODE_TO_ENUM_RD;
-
-/* lower 16 bits of ht40ChanMask */
-#define NO_FREQ_HT40 0x0 /* no freq is HT40 capable */
-#define F1_TO_F4_HT40 0xF /* freq 1 to 4 in the block is ht40 capable */
-#define F2_TO_F3_HT40 0x6 /* freq 2 to 3 in the block is ht40 capable */
-#define F1_TO_F10_HT40 0x3FF /* freq 1 to 10 in the block is ht40 capable */
-#define F3_TO_F11_HT40 0x7FC /* freq 3 to 11 in the block is ht40 capable */
-#define F3_TO_F9_HT40 0x1FC /* freq 3 to 9 in the block is ht40 capable */
-#define F1_TO_F8_HT40 0xFF /* freq 1 to 8 in the block is ht40 capable */
-#define F1_TO_F4_F9_TO_F10_HT40 0x30F /* freq 1 to 4, 9 to 10 in the block is ht40 capable */
-
-/* upper 16 bits of ht40ChanMask */
-#define FREQ_HALF_RATE 0x10000
-#define FREQ_QUARTER_RATE 0x20000
-
-typedef PREPACK struct RegDmnFreqBand {
- u16 lowChannel; /* Low channel center in MHz */
- u16 highChannel; /* High Channel center in MHz */
- u8 power; /* Max power (dBm) for channel range */
- u8 channelSep; /* Channel separation within the band */
- u8 useDfs; /* Use DFS in the RegDomain if corresponding bit is set */
- u8 mode; /* Mode of operation */
- u32 usePassScan; /* Use Passive Scan in the RegDomain if corresponding bit is set */
- u32 ht40ChanMask; /* lower 16 bits: indicate which frequencies in the block is HT40 capable
- upper 16 bits: what rate (half/quarter) the channel is */
-} POSTPACK REG_DMN_FREQ_BAND;
-
-
-
-typedef PREPACK struct regDomain {
- u16 regDmnEnum; /* value from EnumRd table */
- u8 rdCTL;
- u8 maxAntGain;
- u8 dfsMask; /* DFS bitmask for 5Ghz tables */
- u8 flags; /* Requirement flags (AdHoc disallow etc) */
- u16 reserved; /* for alignment */
- u32 pscan; /* Bitmask for passive scan */
- u32 chan11a[BMLEN]; /* 64 bit bitmask for channel/band selection */
- u32 chan11bg[BMLEN];/* 64 bit bitmask for channel/band selection */
-} POSTPACK REG_DOMAIN;
-
-#endif /* __REG_DBSCHEMA_H__ */
diff --git a/drivers/staging/ath6kl/include/common/regulatory/reg_dbvalues.h b/drivers/staging/ath6kl/include/common/regulatory/reg_dbvalues.h
deleted file mode 100644
index 278f903..0000000
--- a/drivers/staging/ath6kl/include/common/regulatory/reg_dbvalues.h
+++ /dev/null
@@ -1,504 +0,0 @@
-//------------------------------------------------------------------------------
-// Copyright (c) 2005-2010 Atheros Corporation. All rights reserved.
-//
-//
-// Permission to use, copy, modify, and/or distribute this software for any
-// purpose with or without fee is hereby granted, provided that the above
-// copyright notice and this permission notice appear in all copies.
-//
-// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-//
-//
-//------------------------------------------------------------------------------
-//==============================================================================
-// Author(s): ="Atheros"
-//==============================================================================
-
-
-#ifndef __REG_DBVALUE_H__
-#define __REG_DBVALUE_H__
-
-/*
- * Numbering from ISO 3166
- */
-enum CountryCode {
- CTRY_ALBANIA = 8, /* Albania */
- CTRY_ALGERIA = 12, /* Algeria */
- CTRY_ARGENTINA = 32, /* Argentina */
- CTRY_ARMENIA = 51, /* Armenia */
- CTRY_ARUBA = 533, /* Aruba */
- CTRY_AUSTRALIA = 36, /* Australia (for STA) */
- CTRY_AUSTRALIA_AP = 5000, /* Australia (for AP) */
- CTRY_AUSTRIA = 40, /* Austria */
- CTRY_AZERBAIJAN = 31, /* Azerbaijan */
- CTRY_BAHRAIN = 48, /* Bahrain */
- CTRY_BANGLADESH = 50, /* Bangladesh */
- CTRY_BARBADOS = 52, /* Barbados */
- CTRY_BELARUS = 112, /* Belarus */
- CTRY_BELGIUM = 56, /* Belgium */
- CTRY_BELIZE = 84, /* Belize */
- CTRY_BOLIVIA = 68, /* Bolivia */
- CTRY_BOSNIA_HERZEGOWANIA = 70, /* Bosnia & Herzegowania */
- CTRY_BRAZIL = 76, /* Brazil */
- CTRY_BRUNEI_DARUSSALAM = 96, /* Brunei Darussalam */
- CTRY_BULGARIA = 100, /* Bulgaria */
- CTRY_CAMBODIA = 116, /* Cambodia */
- CTRY_CANADA = 124, /* Canada (for STA) */
- CTRY_CANADA_AP = 5001, /* Canada (for AP) */
- CTRY_CHILE = 152, /* Chile */
- CTRY_CHINA = 156, /* People's Republic of China */
- CTRY_COLOMBIA = 170, /* Colombia */
- CTRY_COSTA_RICA = 188, /* Costa Rica */
- CTRY_CROATIA = 191, /* Croatia */
- CTRY_CYPRUS = 196,
- CTRY_CZECH = 203, /* Czech Republic */
- CTRY_DENMARK = 208, /* Denmark */
- CTRY_DOMINICAN_REPUBLIC = 214, /* Dominican Republic */
- CTRY_ECUADOR = 218, /* Ecuador */
- CTRY_EGYPT = 818, /* Egypt */
- CTRY_EL_SALVADOR = 222, /* El Salvador */
- CTRY_ESTONIA = 233, /* Estonia */
- CTRY_FAEROE_ISLANDS = 234, /* Faeroe Islands */
- CTRY_FINLAND = 246, /* Finland */
- CTRY_FRANCE = 250, /* France */
- CTRY_FRANCE2 = 255, /* France2 */
- CTRY_GEORGIA = 268, /* Georgia */
- CTRY_GERMANY = 276, /* Germany */
- CTRY_GREECE = 300, /* Greece */
- CTRY_GREENLAND = 304, /* Greenland */
- CTRY_GRENADA = 308, /* Grenada */
- CTRY_GUAM = 316, /* Guam */
- CTRY_GUATEMALA = 320, /* Guatemala */
- CTRY_HAITI = 332, /* Haiti */
- CTRY_HONDURAS = 340, /* Honduras */
- CTRY_HONG_KONG = 344, /* Hong Kong S.A.R., P.R.C. */
- CTRY_HUNGARY = 348, /* Hungary */
- CTRY_ICELAND = 352, /* Iceland */
- CTRY_INDIA = 356, /* India */
- CTRY_INDONESIA = 360, /* Indonesia */
- CTRY_IRAN = 364, /* Iran */
- CTRY_IRAQ = 368, /* Iraq */
- CTRY_IRELAND = 372, /* Ireland */
- CTRY_ISRAEL = 376, /* Israel */
- CTRY_ITALY = 380, /* Italy */
- CTRY_JAMAICA = 388, /* Jamaica */
- CTRY_JAPAN = 392, /* Japan */
- CTRY_JAPAN1 = 393, /* Japan (JP1) */
- CTRY_JAPAN2 = 394, /* Japan (JP0) */
- CTRY_JAPAN3 = 395, /* Japan (JP1-1) */
- CTRY_JAPAN4 = 396, /* Japan (JE1) */
- CTRY_JAPAN5 = 397, /* Japan (JE2) */
- CTRY_JAPAN6 = 399, /* Japan (JP6) */
- CTRY_JORDAN = 400, /* Jordan */
- CTRY_KAZAKHSTAN = 398, /* Kazakhstan */
- CTRY_KENYA = 404, /* Kenya */
- CTRY_KOREA_NORTH = 408, /* North Korea */
- CTRY_KOREA_ROC = 410, /* South Korea (for STA) */
- CTRY_KOREA_ROC2 = 411, /* South Korea */
- CTRY_KOREA_ROC3 = 412, /* South Korea (for AP) */
- CTRY_KUWAIT = 414, /* Kuwait */
- CTRY_LATVIA = 428, /* Latvia */
- CTRY_LEBANON = 422, /* Lebanon */
- CTRY_LIBYA = 434, /* Libya */
- CTRY_LIECHTENSTEIN = 438, /* Liechtenstein */
- CTRY_LITHUANIA = 440, /* Lithuania */
- CTRY_LUXEMBOURG = 442, /* Luxembourg */
- CTRY_MACAU = 446, /* Macau */
- CTRY_MACEDONIA = 807, /* the Former Yugoslav Republic of Macedonia */
- CTRY_MALAYSIA = 458, /* Malaysia */
- CTRY_MALTA = 470, /* Malta */
- CTRY_MEXICO = 484, /* Mexico */
- CTRY_MONACO = 492, /* Principality of Monaco */
- CTRY_MOROCCO = 504, /* Morocco */
- CTRY_NEPAL = 524, /* Nepal */
- CTRY_NETHERLANDS = 528, /* Netherlands */
- CTRY_NETHERLAND_ANTILLES = 530, /* Netherlands-Antilles */
- CTRY_NEW_ZEALAND = 554, /* New Zealand */
- CTRY_NICARAGUA = 558, /* Nicaragua */
- CTRY_NORWAY = 578, /* Norway */
- CTRY_OMAN = 512, /* Oman */
- CTRY_PAKISTAN = 586, /* Islamic Republic of Pakistan */
- CTRY_PANAMA = 591, /* Panama */
- CTRY_PARAGUAY = 600, /* Paraguay */
- CTRY_PERU = 604, /* Peru */
- CTRY_PHILIPPINES = 608, /* Republic of the Philippines */
- CTRY_POLAND = 616, /* Poland */
- CTRY_PORTUGAL = 620, /* Portugal */
- CTRY_PUERTO_RICO = 630, /* Puerto Rico */
- CTRY_QATAR = 634, /* Qatar */
- CTRY_ROMANIA = 642, /* Romania */
- CTRY_RUSSIA = 643, /* Russia */
- CTRY_SAUDI_ARABIA = 682, /* Saudi Arabia */
- CTRY_MONTENEGRO = 891, /* Montenegro */
- CTRY_SINGAPORE = 702, /* Singapore */
- CTRY_SLOVAKIA = 703, /* Slovak Republic */
- CTRY_SLOVENIA = 705, /* Slovenia */
- CTRY_SOUTH_AFRICA = 710, /* South Africa */
- CTRY_SPAIN = 724, /* Spain */
- CTRY_SRILANKA = 144, /* Sri Lanka */
- CTRY_SWEDEN = 752, /* Sweden */
- CTRY_SWITZERLAND = 756, /* Switzerland */
- CTRY_SYRIA = 760, /* Syria */
- CTRY_TAIWAN = 158, /* Taiwan */
- CTRY_THAILAND = 764, /* Thailand */
- CTRY_TRINIDAD_Y_TOBAGO = 780, /* Trinidad y Tobago */
- CTRY_TUNISIA = 788, /* Tunisia */
- CTRY_TURKEY = 792, /* Turkey */
- CTRY_UAE = 784, /* U.A.E. */
- CTRY_UKRAINE = 804, /* Ukraine */
- CTRY_UNITED_KINGDOM = 826, /* United Kingdom */
- CTRY_UNITED_STATES = 840, /* United States (for STA) */
- CTRY_UNITED_STATES_AP = 841, /* United States (for AP) */
- CTRY_UNITED_STATES_PS = 842, /* United States - public safety */
- CTRY_URUGUAY = 858, /* Uruguay */
- CTRY_UZBEKISTAN = 860, /* Uzbekistan */
- CTRY_VENEZUELA = 862, /* Venezuela */
- CTRY_VIET_NAM = 704, /* Viet Nam */
- CTRY_YEMEN = 887, /* Yemen */
- CTRY_ZIMBABWE = 716 /* Zimbabwe */
-};
-
-#define CTRY_DEBUG 0
-#define CTRY_DEFAULT 0x1ff
-
-/*
- * The following regulatory domain definitions are
- * found in the EEPROM. Each regulatory domain
- * can operate in either a 5GHz or 2.4GHz wireless mode or
- * both 5GHz and 2.4GHz wireless modes.
- * In general, the value holds no special
- * meaning and is used to decode into either specific
- * 2.4GHz or 5GHz wireless mode for that particular
- * regulatory domain.
- *
- * Enumerated Regulatory Domain Information 8 bit values indicate that
- * the regdomain is really a pair of unitary regdomains. 12 bit values
- * are the real unitary regdomains and are the only ones which have the
- * frequency bitmasks and flags set.
- */
-
-enum EnumRd {
- NO_ENUMRD = 0x00,
- NULL1_WORLD = 0x03, /* For 11b-only countries (no 11a allowed) */
- NULL1_ETSIB = 0x07, /* Israel */
- NULL1_ETSIC = 0x08,
-
- FCC1_FCCA = 0x10, /* USA */
- FCC1_WORLD = 0x11, /* Hong Kong */
- FCC2_FCCA = 0x20, /* Canada */
- FCC2_WORLD = 0x21, /* Australia & HK */
- FCC2_ETSIC = 0x22,
- FCC3_FCCA = 0x3A, /* USA & Canada w/5470 band, 11h, DFS enabled */
- FCC3_WORLD = 0x3B, /* USA & Canada w/5470 band, 11h, DFS enabled */
- FCC4_FCCA = 0x12, /* FCC public safety plus UNII bands */
- FCC5_FCCA = 0x13, /* US with no DFS */
- FCC5_WORLD = 0x16, /* US with no DFS */
- FCC6_FCCA = 0x14, /* Same as FCC2_FCCA but with 5600-5650MHz channels disabled for US & Canada APs */
- FCC6_WORLD = 0x23, /* Same as FCC2_FCCA but with 5600-5650MHz channels disabled for Australia APs */
-
- ETSI1_WORLD = 0x37,
-
- ETSI2_WORLD = 0x35, /* Hungary & others */
- ETSI3_WORLD = 0x36, /* France & others */
- ETSI4_WORLD = 0x30,
- ETSI4_ETSIC = 0x38,
- ETSI5_WORLD = 0x39,
- ETSI6_WORLD = 0x34, /* Bulgaria */
- ETSI_RESERVED = 0x33, /* Reserved (Do not used) */
- FRANCE_RES = 0x31, /* Legacy France for OEM */
-
- APL6_WORLD = 0x5B, /* Singapore */
- APL4_WORLD = 0x42, /* Singapore */
- APL3_FCCA = 0x50,
- APL_RESERVED = 0x44, /* Reserved (Do not used) */
- APL2_WORLD = 0x45, /* Korea */
- APL2_APLC = 0x46,
- APL3_WORLD = 0x47,
- APL2_APLD = 0x49, /* Korea with 2.3G channels */
- APL2_FCCA = 0x4D, /* Specific Mobile Customer */
- APL1_WORLD = 0x52, /* Latin America */
- APL1_FCCA = 0x53,
- APL1_ETSIC = 0x55,
- APL2_ETSIC = 0x56, /* Venezuela */
- APL5_WORLD = 0x58, /* Chile */
- APL7_FCCA = 0x5C,
- APL8_WORLD = 0x5D,
- APL9_WORLD = 0x5E,
- APL10_WORLD = 0x5F, /* Korea 5GHz for STA */
-
-
- MKK5_MKKA = 0x99, /* This is a temporary value. MG and DQ have to give official one */
- MKK5_FCCA = 0x9A, /* This is a temporary value. MG and DQ have to give official one */
- MKK5_MKKC = 0x88,
- MKK11_MKKA = 0xD4,
- MKK11_FCCA = 0xD5,
- MKK11_MKKC = 0xD7,
-
- /*
- * World mode SKUs
- */
- WOR0_WORLD = 0x60, /* World0 (WO0 SKU) */
- WOR1_WORLD = 0x61, /* World1 (WO1 SKU) */
- WOR2_WORLD = 0x62, /* World2 (WO2 SKU) */
- WOR3_WORLD = 0x63, /* World3 (WO3 SKU) */
- WOR4_WORLD = 0x64, /* World4 (WO4 SKU) */
- WOR5_ETSIC = 0x65, /* World5 (WO5 SKU) */
-
- WOR01_WORLD = 0x66, /* World0-1 (WW0-1 SKU) */
- WOR02_WORLD = 0x67, /* World0-2 (WW0-2 SKU) */
- EU1_WORLD = 0x68, /* Same as World0-2 (WW0-2 SKU), except active scan ch1-13. No ch14 */
-
- WOR9_WORLD = 0x69, /* World9 (WO9 SKU) */
- WORA_WORLD = 0x6A, /* WorldA (WOA SKU) */
- WORB_WORLD = 0x6B, /* WorldB (WOA SKU) */
- WORC_WORLD = 0x6C, /* WorldC (WOA SKU) */
-
- /*
- * Regulator domains ending in a number (e.g. APL1,
- * MK1, ETSI4, etc) apply to 5GHz channel and power
- * information. Regulator domains ending in a letter
- * (e.g. APLA, FCCA, etc) apply to 2.4GHz channel and
- * power information.
- */
- APL1 = 0x0150, /* LAT & Asia */
- APL2 = 0x0250, /* LAT & Asia */
- APL3 = 0x0350, /* Taiwan */
- APL4 = 0x0450, /* Jordan */
- APL5 = 0x0550, /* Chile */
- APL6 = 0x0650, /* Singapore */
- APL7 = 0x0750, /* Taiwan */
- APL8 = 0x0850, /* Malaysia */
- APL9 = 0x0950, /* Korea */
- APL10 = 0x1050, /* Korea 5GHz */
-
- ETSI1 = 0x0130, /* Europe & others */
- ETSI2 = 0x0230, /* Europe & others */
- ETSI3 = 0x0330, /* Europe & others */
- ETSI4 = 0x0430, /* Europe & others */
- ETSI5 = 0x0530, /* Europe & others */
- ETSI6 = 0x0630, /* Europe & others */
- ETSIB = 0x0B30, /* Israel */
- ETSIC = 0x0C30, /* Latin America */
-
- FCC1 = 0x0110, /* US & others */
- FCC2 = 0x0120, /* Canada, Australia & New Zealand */
- FCC3 = 0x0160, /* US w/new middle band & DFS */
- FCC4 = 0x0165,
- FCC5 = 0x0180,
- FCC6 = 0x0610,
- FCCA = 0x0A10,
-
- APLD = 0x0D50, /* South Korea */
-
- MKK1 = 0x0140, /* Japan */
- MKK2 = 0x0240, /* Japan Extended */
- MKK3 = 0x0340, /* Japan new 5GHz */
- MKK4 = 0x0440, /* Japan new 5GHz */
- MKK5 = 0x0540, /* Japan new 5GHz */
- MKK6 = 0x0640, /* Japan new 5GHz */
- MKK7 = 0x0740, /* Japan new 5GHz */
- MKK8 = 0x0840, /* Japan new 5GHz */
- MKK9 = 0x0940, /* Japan new 5GHz */
- MKK10 = 0x1040, /* Japan new 5GHz */
- MKK11 = 0x1140, /* Japan new 5GHz */
- MKK12 = 0x1240, /* Japan new 5GHz */
-
- MKKA = 0x0A40, /* Japan */
- MKKC = 0x0A50,
-
- NULL1 = 0x0198,
- WORLD = 0x0199,
- DEBUG_REG_DMN = 0x01ff,
- UNINIT_REG_DMN = 0x0fff,
-};
-
-enum { /* conformance test limits */
- FCC = 0x10,
- MKK = 0x40,
- ETSI = 0x30,
- NO_CTL = 0xff,
- CTL_11B = 1,
- CTL_11G = 2
-};
-
-
-/*
- * The following are flags for different requirements per reg domain.
- * These requirements are either inhereted from the reg domain pair or
- * from the unitary reg domain if the reg domain pair flags value is
- * 0
- */
-
-enum {
- NO_REQ = 0x00,
- DISALLOW_ADHOC_11A = 0x01,
- ADHOC_PER_11D = 0x02,
- ADHOC_NO_11A = 0x04,
- DISALLOW_ADHOC_11G = 0x08
-};
-
-
-
-
-/*
- * The following describe the bit masks for different passive scan
- * capability/requirements per regdomain.
- */
-#define NO_PSCAN 0x00000000
-#define PSCAN_FCC 0x00000001
-#define PSCAN_ETSI 0x00000002
-#define PSCAN_MKK 0x00000004
-#define PSCAN_ETSIB 0x00000008
-#define PSCAN_ETSIC 0x00000010
-#define PSCAN_WWR 0x00000020
-#define PSCAN_DEFER 0xFFFFFFFF
-
-/* Bit masks for DFS per regdomain */
-
-enum {
- NO_DFS = 0x00,
- DFS_FCC3 = 0x01,
- DFS_ETSI = 0x02,
- DFS_MKK = 0x04
-};
-
-
-#define DEF_REGDMN FCC1_FCCA
-
-/*
- * The following table is the master list for all different freqeuncy
- * bands with the complete matrix of all possible flags and settings
- * for each band if it is used in ANY reg domain.
- *
- * The table of frequency bands is indexed by a bitmask. The ordering
- * must be consistent with the enum below. When adding a new
- * frequency band, be sure to match the location in the enum with the
- * comments
- */
-
-/*
- * These frequency values are as per channel tags and regulatory domain
- * info. Please update them as database is updated.
- */
-#define A_FREQ_MIN 4920
-#define A_FREQ_MAX 5825
-
-#define A_CHAN0_FREQ 5000
-#define A_CHAN_MAX ((A_FREQ_MAX - A_CHAN0_FREQ)/5)
-
-#define BG_FREQ_MIN 2412
-#define BG_FREQ_MAX 2484
-
-#define BG_CHAN0_FREQ 2407
-#define BG_CHAN_MIN ((BG_FREQ_MIN - BG_CHAN0_FREQ)/5)
-#define BG_CHAN_MAX 14 /* corresponding to 2484 MHz */
-
-#define A_20MHZ_BAND_FREQ_MAX 5000
-
-
-/*
- * 5GHz 11A channel tags
- */
-
-enum {
- F1_4920_4980,
- F1_5040_5080,
-
- F1_5120_5240,
-
- F1_5180_5240,
- F2_5180_5240,
- F3_5180_5240,
- F4_5180_5240,
- F5_5180_5240,
- F6_5180_5240,
- F7_5180_5240,
-
- F1_5260_5280,
-
- F1_5260_5320,
- F2_5260_5320,
- F3_5260_5320,
- F4_5260_5320,
- F5_5260_5320,
- F6_5260_5320,
-
- F1_5260_5700,
-
- F1_5280_5320,
-
- F1_5500_5620,
-
- F1_5500_5700,
- F2_5500_5700,
- F3_5500_5700,
- F4_5500_5700,
- F5_5500_5700,
- F6_5500_5700,
- F7_5500_5700,
-
- F1_5745_5805,
- F2_5745_5805,
-
- F1_5745_5825,
- F2_5745_5825,
- F3_5745_5825,
- F4_5745_5825,
- F5_5745_5825,
- F6_5745_5825,
-
- W1_4920_4980,
- W1_5040_5080,
- W1_5170_5230,
- W1_5180_5240,
- W1_5260_5320,
- W1_5745_5825,
- W1_5500_5700,
-};
-
-
-/* 2.4 GHz table - for 11b and 11g info */
-enum {
- BG1_2312_2372,
- BG2_2312_2372,
-
- BG1_2412_2472,
- BG2_2412_2472,
- BG3_2412_2472,
- BG4_2412_2472,
-
- BG1_2412_2462,
- BG2_2412_2462,
-
- BG1_2432_2442,
-
- BG1_2457_2472,
-
- BG1_2467_2472,
-
- BG1_2484_2484, /* No G */
- BG2_2484_2484, /* No G */
-
- BG1_2512_2732,
-
- WBG1_2312_2372,
- WBG1_2412_2412,
- WBG1_2417_2432,
- WBG1_2437_2442,
- WBG1_2447_2457,
- WBG1_2462_2462,
- WBG1_2467_2467,
- WBG2_2467_2467,
- WBG1_2472_2472,
- WBG2_2472_2472,
- WBG1_2484_2484, /* No G */
- WBG2_2484_2484, /* No G */
-};
-
-#endif /* __REG_DBVALUE_H__ */
diff --git a/drivers/staging/ath6kl/include/common/targaddrs.h b/drivers/staging/ath6kl/include/common/targaddrs.h
index 794ae21..c866cef 100644
--- a/drivers/staging/ath6kl/include/common/targaddrs.h
+++ b/drivers/staging/ath6kl/include/common/targaddrs.h
@@ -22,10 +22,6 @@
#ifndef __TARGADDRS_H__
#define __TARGADDRS_H__
-#ifndef ATH_TARGET
-#include "athstartpack.h"
-#endif
-
#if defined(AR6002)
#include "AR6002/addrs.h"
#endif
@@ -91,15 +87,7 @@
/* Pointer to debug logging header */
u32 hi_dbglog_hdr; /* 0x08 */
- /* Indicates whether or not flash is present on Target.
- * NB: flash_is_present indicator is here not just
- * because it might be of interest to the Host; but
- * also because it's set early on by Target's startup
- * asm code and we need it to have a special RAM address
- * so that it doesn't get reinitialized with the rest
- * of data.
- */
- u32 hi_flash_is_present; /* 0x0c */
+ u32 hi_unused1; /* 0x0c */
/*
* General-purpose flag bits, similar to AR6000_OPTION_* flags.
@@ -113,7 +101,7 @@
*/
u32 hi_serial_enable; /* 0x14 */
- /* Start address of Flash DataSet index, if any */
+ /* Start address of DataSet index, if any */
u32 hi_dset_list_head; /* 0x18 */
/* Override Target application start address */
@@ -171,35 +159,179 @@
u32 hi_hci_uart_support_pins; /* 0xa4 */
/* NOTE: byte [0] = RESET pin (bit 7 is polarity), bytes[1]..bytes[3] are for future use */
u32 hi_hci_uart_pwr_mgmt_params; /* 0xa8 */
- /* 0xa8 - [0]: 1 = enable, 0 = disable
- * [1]: 0 = UART FC active low, 1 = UART FC active high
- * 0xa9 - [7:0]: wakeup timeout in ms
- * 0xaa, 0xab - [15:0]: idle timeout in ms
- */
- /* Pointer to extended board Data */
- u32 hi_board_ext_data; /* 0xac */
- u32 hi_board_ext_data_initialized; /* 0xb0 */
+ /*
+ * 0xa8 - [1]: 0 = UART FC active low, 1 = UART FC active high
+ * [31:16]: wakeup timeout in ms
+ */
+
+ /* Pointer to extended board data */
+ u32 hi_board_ext_data; /* 0xac */
+ u32 hi_board_ext_data_config; /* 0xb0 */
+
+ /*
+ * Bit [0] : valid
+ * Bit[31:16: size
+ */
+ /*
+ * hi_reset_flag is used to do some stuff when target reset.
+ * such as restore app_start after warm reset or
+ * preserve host Interest area, or preserve ROM data, literals etc.
+ */
+ u32 hi_reset_flag; /* 0xb4 */
+ /* indicate hi_reset_flag is valid */
+ u32 hi_reset_flag_valid; /* 0xb8 */
+ u32 hi_hci_uart_pwr_mgmt_params_ext; /* 0xbc */
+ /*
+ * 0xbc - [31:0]: idle timeout in ms
+ */
+ /* ACS flags */
+ u32 hi_acs_flags; /* 0xc0 */
+ u32 hi_console_flags; /* 0xc4 */
+ u32 hi_nvram_state; /* 0xc8 */
+ u32 hi_option_flag2; /* 0xcc */
+
+ /* If non-zero, override values sent to Host in WMI_READY event. */
+ u32 hi_sw_version_override; /* 0xd0 */
+ u32 hi_abi_version_override; /* 0xd4 */
+
+ /*
+ * Percentage of high priority RX traffic to total expected RX traffic -
+ * applicable only to ar6004
+ */
+ u32 hi_hp_rx_traffic_ratio; /* 0xd8 */
+
+ /* test applications flags */
+ u32 hi_test_apps_related ; /* 0xdc */
+ /* location of test script */
+ u32 hi_ota_testscript; /* 0xe0 */
+ /* location of CAL data */
+ u32 hi_cal_data; /* 0xe4 */
+ /* Number of packet log buffers */
+ u32 hi_pktlog_num_buffers; /* 0xe8 */
+
} POSTPACK;
/* Bits defined in hi_option_flag */
#define HI_OPTION_TIMER_WAR 0x01 /* Enable timer workaround */
#define HI_OPTION_BMI_CRED_LIMIT 0x02 /* Limit BMI command credits */
#define HI_OPTION_RELAY_DOT11_HDR 0x04 /* Relay Dot11 hdr to/from host */
-#define HI_OPTION_FW_MODE_LSB 0x08 /* low bit of MODE (see below) */
-#define HI_OPTION_FW_MODE_MSB 0x10 /* high bit of MODE (see below) */
-#define HI_OPTION_ENABLE_PROFILE 0x20 /* Enable CPU profiling */
-#define HI_OPTION_DISABLE_DBGLOG 0x40 /* Disable debug logging */
-#define HI_OPTION_SKIP_ERA_TRACKING 0x80 /* Skip Era Tracking */
-#define HI_OPTION_PAPRD_DISABLE 0x100 /* Disable PAPRD (debug) */
+/* MAC addr method 0-locally administred 1-globally unique addrs */
+#define HI_OPTION_MAC_ADDR_METHOD 0x08
+#define HI_OPTION_FW_BRIDGE 0x10 /* Firmware Bridging */
+#define HI_OPTION_ENABLE_PROFILE 0x20 /* Enable CPU profiling */
+#define HI_OPTION_DISABLE_DBGLOG 0x40 /* Disable debug logging */
+#define HI_OPTION_SKIP_ERA_TRACKING 0x80 /* Skip Era Tracking */
+#define HI_OPTION_PAPRD_DISABLE 0x100 /* Disable PAPRD (debug) */
+#define HI_OPTION_NUM_DEV_LSB 0x200
+#define HI_OPTION_NUM_DEV_MSB 0x800
+#define HI_OPTION_DEV_MODE_LSB 0x1000
+#define HI_OPTION_DEV_MODE_MSB 0x8000000
+/* Disable LowFreq Timer Stabilization */
+#define HI_OPTION_NO_LFT_STBL 0x10000000
+#define HI_OPTION_SKIP_REG_SCAN 0x20000000 /* Skip regulatory scan */
+/* Do regulatory scan during init beforesending WMI ready event to host */
+#define HI_OPTION_INIT_REG_SCAN 0x40000000
+#define HI_OPTION_SKIP_MEMMAP 0x80000000 /* REV6: Do not adjust memory
+ map */
+
+/* hi_option_flag2 options */
+#define HI_OPTION_OFFLOAD_AMSDU 0x01
+#define HI_OPTION_DFS_SUPPORT 0x02 /* Enable DFS support */
+
+#define HI_OPTION_MAC_ADDR_METHOD_SHIFT 3
/* 2 bits of hi_option_flag are used to represent 3 modes */
#define HI_OPTION_FW_MODE_IBSS 0x0 /* IBSS Mode */
#define HI_OPTION_FW_MODE_BSS_STA 0x1 /* STA Mode */
#define HI_OPTION_FW_MODE_AP 0x2 /* AP Mode */
-/* Fw Mode Mask */
-#define HI_OPTION_FW_MODE_MASK 0x3
-#define HI_OPTION_FW_MODE_SHIFT 0x3
+/* 2 bits of hi_option flag are usedto represent 4 submodes */
+#define HI_OPTION_FW_SUBMODE_NONE 0x0 /* Normal mode */
+#define HI_OPTION_FW_SUBMODE_P2PDEV 0x1 /* p2p device mode */
+#define HI_OPTION_FW_SUBMODE_P2PCLIENT 0x2 /* p2p client mode */
+#define HI_OPTION_FW_SUBMODE_P2PGO 0x3 /* p2p go mode */
+
+/* Num dev Mask */
+#define HI_OPTION_NUM_DEV_MASK 0x7
+#define HI_OPTION_NUM_DEV_SHIFT 0x9
+
+/* firmware bridging */
+#define HI_OPTION_FW_BRIDGE_SHIFT 0x04
+
+/* Fw Mode/SubMode Mask
+|------------------------------------------------------------------------------|
+| SUB | SUB | SUB | SUB | | | |
+| MODE[3] | MODE[2] | MODE[1] | MODE[0] | MODE[3] | MODE[2] | MODE[1] | MODE[0|
+| (2) | (2) | (2) | (2) | (2) | (2) | (2) | (2)
+|------------------------------------------------------------------------------|
+*/
+#define HI_OPTION_FW_MODE_BITS 0x2
+#define HI_OPTION_FW_MODE_MASK 0x3
+#define HI_OPTION_FW_MODE_SHIFT 0xC
+#define HI_OPTION_ALL_FW_MODE_MASK 0xFF
+
+#define HI_OPTION_FW_SUBMODE_BITS 0x2
+#define HI_OPTION_FW_SUBMODE_MASK 0x3
+#define HI_OPTION_FW_SUBMODE_SHIFT 0x14
+#define HI_OPTION_ALL_FW_SUBMODE_MASK 0xFF00
+#define HI_OPTION_ALL_FW_SUBMODE_SHIFT 0x8
+
+/* hi_reset_flag */
+
+/* preserve App Start address */
+#define HI_RESET_FLAG_PRESERVE_APP_START 0x01
+/* preserve host interest */
+#define HI_RESET_FLAG_PRESERVE_HOST_INTEREST 0x02
+#define HI_RESET_FLAG_PRESERVE_ROMDATA 0x04 /* preserve ROM data */
+#define HI_RESET_FLAG_PRESERVE_NVRAM_STATE 0x08
+#define HI_RESET_FLAG_PRESERVE_BOOT_INFO 0x10
+
+#define HI_RESET_FLAG_IS_VALID 0x12345678 /* indicate the reset flag is
+valid */
+
+#define ON_RESET_FLAGS_VALID() \
+ (HOST_INTEREST->hi_reset_flag_valid == HI_RESET_FLAG_IS_VALID)
+
+#define RESET_FLAGS_VALIDATE() \
+ (HOST_INTEREST->hi_reset_flag_valid = HI_RESET_FLAG_IS_VALID)
+
+#define RESET_FLAGS_INVALIDATE() \
+ (HOST_INTEREST->hi_reset_flag_valid = 0)
+
+#define ON_RESET_PRESERVE_APP_START() \
+ (HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_APP_START)
+
+#define ON_RESET_PRESERVE_NVRAM_STATE() \
+ (HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_NVRAM_STATE)
+
+#define ON_RESET_PRESERVE_HOST_INTEREST() \
+ (HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_HOST_INTEREST)
+
+#define ON_RESET_PRESERVE_ROMDATA() \
+ (HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_ROMDATA)
+
+#define ON_RESET_PRESERVE_BOOT_INFO() \
+ (HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_BOOT_INFO)
+
+#define HI_ACS_FLAGS_ENABLED (1 << 0) /* ACS is enabled */
+#define HI_ACS_FLAGS_USE_WWAN (1 << 1) /* Use physical WWAN device */
+#define HI_ACS_FLAGS_TEST_VAP (1 << 2) /* Use test VAP */
+
+/* CONSOLE FLAGS
+ *
+ * Bit Range Meaning
+ * --------- --------------------------------
+ * 2..0 UART ID (0 = Default)
+ * 3 Baud Select (0 = 9600, 1 = 115200)
+ * 30..4 Reserved
+ * 31 Enable Console
+ *
+ */
+
+#define HI_CONSOLE_FLAGS_ENABLE (1 << 31)
+#define HI_CONSOLE_FLAGS_UART_MASK (0x7)
+#define HI_CONSOLE_FLAGS_UART_SHIFT 0
+#define HI_CONSOLE_FLAGS_BAUD_SELECT (1 << 3)
/*
* Intended for use by Host software, this macro returns the Target RAM
@@ -212,34 +344,52 @@
#define AR6003_HOST_INTEREST_ITEM_ADDRESS(item) \
(u32)((unsigned long)&((((struct host_interest_s *)(AR6003_HOST_INTEREST_ADDRESS))->item)))
+#define AR6004_HOST_INTEREST_ITEM_ADDRESS(item) \
+ ((u32)&((((struct host_interest_s *)(AR6004_HOST_INTEREST_ADDRESS))->item)))
+
+
#define HOST_INTEREST_DBGLOG_IS_ENABLED() \
(!(HOST_INTEREST->hi_option_flag & HI_OPTION_DISABLE_DBGLOG))
+#define HOST_INTEREST_PKTLOG_IS_ENABLED() \
+ ((HOST_INTEREST->hi_pktlog_num_buffers))
+
+
#define HOST_INTEREST_PROFILE_IS_ENABLED() \
(HOST_INTEREST->hi_option_flag & HI_OPTION_ENABLE_PROFILE)
+#define LF_TIMER_STABILIZATION_IS_ENABLED() \
+ (!(HOST_INTEREST->hi_option_flag & HI_OPTION_NO_LFT_STBL))
+
+#define IS_AMSDU_OFFLAOD_ENABLED() \
+ ((HOST_INTEREST->hi_option_flag2 & HI_OPTION_OFFLOAD_AMSDU))
+
+#define HOST_INTEREST_DFS_IS_ENABLED() \
+ ((HOST_INTEREST->hi_option_flag2 & HI_OPTION_DFS_SUPPORT))
+
/* Convert a Target virtual address into a Target physical address */
#define AR6002_VTOP(vaddr) ((vaddr) & 0x001fffff)
#define AR6003_VTOP(vaddr) ((vaddr) & 0x001fffff)
#define TARG_VTOP(TargetType, vaddr) \
(((TargetType) == TARGET_TYPE_AR6002) ? AR6002_VTOP(vaddr) : AR6003_VTOP(vaddr))
-/* override REV2 ROM's app start address */
-#define AR6002_REV2_APP_START_OVERRIDE 0x911A00
-#define AR6003_REV1_APP_START_OVERRIDE 0x944c00
-#define AR6003_REV1_OTP_DATA_ADDRESS 0x542800
-#define AR6003_REV2_APP_START_OVERRIDE 0x945000
-#define AR6003_REV2_OTP_DATA_ADDRESS 0x543800
-#define AR6003_BOARD_EXT_DATA_ADDRESS 0x57E600
+#define AR6003_REV2_APP_START_OVERRIDE 0x944C00
+#define AR6003_REV2_APP_LOAD_ADDRESS 0x543180
+#define AR6003_REV2_BOARD_EXT_DATA_ADDRESS 0x57E500
+#define AR6003_REV2_DATASET_PATCH_ADDRESS 0x57e884
+#define AR6003_REV2_RAM_RESERVE_SIZE 6912
+#define AR6003_REV3_APP_START_OVERRIDE 0x945d00
+#define AR6003_REV3_APP_LOAD_ADDRESS 0x545000
+#define AR6003_REV3_BOARD_EXT_DATA_ADDRESS 0x542330
+#define AR6003_REV3_DATASET_PATCH_ADDRESS 0x57FF74
+#define AR6003_REV3_RAM_RESERVE_SIZE 512
+
+#define AR6003_BOARD_EXT_DATA_ADDRESS 0x57E600
/* # of u32 entries in targregs, used by DIAG_FETCH_TARG_REGS */
#define AR6003_FETCH_TARG_REGS_COUNT 64
#endif /* !__ASSEMBLER__ */
-#ifndef ATH_TARGET
-#include "athendpack.h"
-#endif
-
#endif /* __TARGADDRS_H__ */
diff --git a/drivers/staging/ath6kl/include/common/wlan_dset.h b/drivers/staging/ath6kl/include/common/wlan_dset.h
deleted file mode 100644
index e775b25..0000000
--- a/drivers/staging/ath6kl/include/common/wlan_dset.h
+++ /dev/null
@@ -1,33 +0,0 @@
-//------------------------------------------------------------------------------
-// Copyright (c) 2007-2010 Atheros Corporation. All rights reserved.
-//
-//
-// Permission to use, copy, modify, and/or distribute this software for any
-// purpose with or without fee is hereby granted, provided that the above
-// copyright notice and this permission notice appear in all copies.
-//
-// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-//
-//
-//------------------------------------------------------------------------------
-//==============================================================================
-// Author(s): ="Atheros"
-//==============================================================================
-
-#ifndef __WLAN_DSET_H__
-#define __WLAN_DSET_H__
-
-typedef PREPACK struct wow_config_dset {
-
- u8 valid_dset;
- u8 gpio_enable;
- u16 gpio_pin;
-} POSTPACK WOW_CONFIG_DSET;
-
-#endif
diff --git a/drivers/staging/ath6kl/include/common/wmi.h b/drivers/staging/ath6kl/include/common/wmi.h
index 4e63434..d9687443 100644
--- a/drivers/staging/ath6kl/include/common/wmi.h
+++ b/drivers/staging/ath6kl/include/common/wmi.h
@@ -34,10 +34,6 @@
#ifndef _WMI_H_
#define _WMI_H_
-#ifndef ATH_TARGET
-#include "athstartpack.h"
-#endif
-
#include "wmix.h"
#include "wlan_defs.h"
@@ -118,7 +114,7 @@
typedef enum {
WMI_DATA_HDR_DATA_TYPE_802_3 = 0,
WMI_DATA_HDR_DATA_TYPE_802_11,
- WMI_DATA_HDR_DATA_TYPE_ACL,
+ WMI_DATA_HDR_DATA_TYPE_ACL, /* used to be used for the PAL */
} WMI_DATA_HDR_DATA_TYPE;
#define WMI_DATA_HDR_DATA_TYPE_MASK 0x3
@@ -159,6 +155,16 @@
#define WMI_DATA_HDR_GET_META(h) (((h)->info2 >> WMI_DATA_HDR_META_SHIFT) & WMI_DATA_HDR_META_MASK)
#define WMI_DATA_HDR_SET_META(h, _v) ((h)->info2 = ((h)->info2 & ~(WMI_DATA_HDR_META_MASK << WMI_DATA_HDR_META_SHIFT)) | ((_v) << WMI_DATA_HDR_META_SHIFT))
+/* Macros for operating on WMI_DATA_HDR (info3) field */
+#define WMI_DATA_HDR_DEVID_MASK 0xF
+#define WMI_DATA_HDR_DEVID_SHIFT 0
+#define GET_DEVID(_v) ((_v) & WMI_DATA_HDR_DEVID_MASK)
+
+#define WMI_DATA_HDR_GET_DEVID(h) \
+ (((h)->info3 >> WMI_DATA_HDR_DEVID_SHIFT) & WMI_DATA_HDR_DEVID_MASK)
+#define WMI_DATA_HDR_SET_DEVID(h, _v) \
+ ((h)->info3 = ((h)->info3 & ~(WMI_DATA_HDR_DEVID_MASK << WMI_DATA_HDR_DEVID_SHIFT)) | (GET_DEVID(_v) << WMI_DATA_HDR_DEVID_SHIFT))
+
typedef PREPACK struct {
s8 rssi;
u8 info; /* usage of 'info' field(8-bit):
@@ -175,7 +181,7 @@
* b12 - A-MSDU?
* b15:b13 - META_DATA_VERSION 0 - 7
*/
- u16 reserved;
+ u16 info3;
} POSTPACK WMI_DATA_HDR;
/*
@@ -259,6 +265,17 @@
#define WMI_GET_DEVICE_ID(info1) ((info1) & 0xF)
+/* Macros for operating on WMI_CMD_HDR (info1) field */
+#define WMI_CMD_HDR_DEVID_MASK 0xF
+#define WMI_CMD_HDR_DEVID_SHIFT 0
+#define GET_CMD_DEVID(_v) ((_v) & WMI_CMD_HDR_DEVID_MASK)
+
+#define WMI_CMD_HDR_GET_DEVID(h) \
+ (((h)->info1 >> WMI_CMD_HDR_DEVID_SHIFT) & WMI_CMD_HDR_DEVID_MASK)
+#define WMI_CMD_HDR_SET_DEVID(h, _v) \
+ ((h)->info1 = ((h)->info1 & \
+ ~(WMI_CMD_HDR_DEVID_MASK << WMI_CMD_HDR_DEVID_SHIFT)) | \
+ (GET_CMD_DEVID(_v) << WMI_CMD_HDR_DEVID_SHIFT))
/*
* Control Path
@@ -433,13 +450,47 @@
WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMDID,
WMI_GET_BTCOEX_STATS_CMDID,
WMI_GET_BTCOEX_CONFIG_CMDID,
- WMI_GET_PMK_CMDID,
- WMI_SET_PASSPHRASE_CMDID,
- WMI_ENABLE_WAC_CMDID,
- WMI_WAC_SCAN_REPLY_CMDID,
- WMI_WAC_CTRL_REQ_CMDID,
- WMI_SET_DIV_PARAMS_CMDID,
- WMI_SET_EXCESS_TX_RETRY_THRES_CMDID,
+
+ WMI_SET_DFS_ENABLE_CMDID, /* F034 */
+ WMI_SET_DFS_MINRSSITHRESH_CMDID,
+ WMI_SET_DFS_MAXPULSEDUR_CMDID,
+ WMI_DFS_RADAR_DETECTED_CMDID,
+
+ /* P2P CMDS */
+ WMI_P2P_SET_CONFIG_CMDID, /* F038 */
+ WMI_WPS_SET_CONFIG_CMDID,
+ WMI_SET_REQ_DEV_ATTR_CMDID,
+ WMI_P2P_FIND_CMDID,
+ WMI_P2P_STOP_FIND_CMDID,
+ WMI_P2P_GO_NEG_START_CMDID,
+ WMI_P2P_LISTEN_CMDID,
+
+ WMI_CONFIG_TX_MAC_RULES_CMDID, /* F040 */
+ WMI_SET_PROMISCUOUS_MODE_CMDID,
+ WMI_RX_FRAME_FILTER_CMDID,
+ WMI_SET_CHANNEL_CMDID,
+
+ /* WAC commands */
+ WMI_ENABLE_WAC_CMDID,
+ WMI_WAC_SCAN_REPLY_CMDID,
+ WMI_WAC_CTRL_REQ_CMDID,
+ WMI_SET_DIV_PARAMS_CMDID,
+
+ WMI_GET_PMK_CMDID,
+ WMI_SET_PASSPHRASE_CMDID,
+ WMI_SEND_ASSOC_RES_CMDID,
+ WMI_SET_ASSOC_REQ_RELAY_CMDID,
+ WMI_GET_RFKILL_MODE_CMDID,
+
+ /* ACS command, consists of sub-commands */
+ WMI_ACS_CTRL_CMDID,
+
+ /* Ultra low power store / recall commands */
+ WMI_STORERECALL_CONFIGURE_CMDID,
+ WMI_STORERECALL_RECALL_CMDID,
+ WMI_STORERECALL_HOST_READY_CMDID,
+ WMI_FORCE_TARGET_ASSERT_CMDID,
+ WMI_SET_EXCESS_TX_RETRY_THRES_CMDID,
} WMI_COMMAND_ID;
/*
@@ -470,6 +521,11 @@
LEAP_AUTH = 0x04, /* different from IEEE_AUTH_MODE definitions */
} DOT11_AUTH_MODE;
+enum {
+ AUTH_IDLE,
+ AUTH_OPEN_IN_PROGRESS,
+};
+
typedef enum {
NONE_AUTH = 0x01,
WPA_AUTH = 0x02,
@@ -560,7 +616,7 @@
* WMI_SET_EXCESS_TX_RETRY_THRES_CMDID
*/
typedef PREPACK struct {
- A_UINT32 threshold;
+ u32 threshold;
} POSTPACK WMI_SET_EXCESS_TX_RETRY_THRES_CMD;
/*
@@ -1969,12 +2025,47 @@
#endif
WMI_REPORT_BTCOEX_STATS_EVENTID,
WMI_REPORT_BTCOEX_CONFIG_EVENTID,
- WMI_ACM_REJECT_EVENTID,
- WMI_THIN_RESERVED_START_EVENTID = 0x8000,
- /* Events in this range are reserved for thinmode
- * See wmi_thin.h for actual definitions */
- WMI_THIN_RESERVED_END_EVENTID = 0x8fff,
+ WMI_GET_PMK_EVENTID,
+ /* DFS Events */
+ WMI_DFS_HOST_ATTACH_EVENTID,
+ WMI_DFS_HOST_INIT_EVENTID,
+ WMI_DFS_RESET_DELAYLINES_EVENTID,
+ WMI_DFS_RESET_RADARQ_EVENTID,
+ WMI_DFS_RESET_AR_EVENTID,
+ WMI_DFS_RESET_ARQ_EVENTID,
+ WMI_DFS_SET_DUR_MULTIPLIER_EVENTID,
+ WMI_DFS_SET_BANGRADAR_EVENTID,
+ WMI_DFS_SET_DEBUGLEVEL_EVENTID,
+ WMI_DFS_PHYERR_EVENTID,
+ /* CCX Evants */
+ WMI_CCX_RM_STATUS_EVENTID,
+
+ /* P2P Events */
+ WMI_P2P_GO_NEG_RESULT_EVENTID,
+
+ WMI_WAC_SCAN_DONE_EVENTID,
+ WMI_WAC_REPORT_BSS_EVENTID,
+ WMI_WAC_START_WPS_EVENTID,
+ WMI_WAC_CTRL_REQ_REPLY_EVENTID,
+
+ /* RFKILL Events */
+ WMI_RFKILL_STATE_CHANGE_EVENTID,
+ WMI_RFKILL_GET_MODE_CMD_EVENTID,
+ WMI_THIN_RESERVED_START_EVENTID = 0x8000,
+
+ /*
+ * Events in this range are reserved for thinmode
+ * See wmi_thin.h for actual definitions
+ */
+ WMI_THIN_RESERVED_END_EVENTID = 0x8fff,
+
+ WMI_SET_CHANNEL_EVENTID,
+ WMI_ASSOC_REQ_EVENTID,
+
+ /* generic ACS event */
+ WMI_ACS_EVENTID,
+ WMI_REPORT_WMM_PARAMS_EVENTID
} WMI_EVENT_ID;
@@ -3122,10 +3213,6 @@
* End of AP mode definitions
*/
-#ifndef ATH_TARGET
-#include "athendpack.h"
-#endif
-
#ifdef __cplusplus
}
#endif
diff --git a/drivers/staging/ath6kl/include/common/wmi_thin.h b/drivers/staging/ath6kl/include/common/wmi_thin.h
deleted file mode 100644
index 0a8364c..0000000
--- a/drivers/staging/ath6kl/include/common/wmi_thin.h
+++ /dev/null
@@ -1,347 +0,0 @@
-//------------------------------------------------------------------------------
-// <copyright file="wmi_thin.h" company="Atheros">
-// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
-//
-//
-// Permission to use, copy, modify, and/or distribute this software for any
-// purpose with or without fee is hereby granted, provided that the above
-// copyright notice and this permission notice appear in all copies.
-//
-// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-//
-//
-//------------------------------------------------------------------------------
-//==============================================================================
-// Author(s): ="Atheros"
-//==============================================================================
-
-/*
- * This file contains the definitions of the WMI protocol specified in the
- * Wireless Module Interface (WMI). It includes definitions of all the
- * commands and events. Commands are messages from the host to the WM.
- * Events and Replies are messages from the WM to the host.
- *
- * Ownership of correctness in regards to WMI commands
- * belongs to the host driver and the WM is not required to validate
- * parameters for value, proper range, or any other checking.
- *
- */
-
-#ifndef _WMI_THIN_H_
-#define _WMI_THIN_H_
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-typedef enum {
- WMI_THIN_CONFIG_CMDID = 0x8000, // WMI_THIN_RESERVED_START
- WMI_THIN_SET_MIB_CMDID,
- WMI_THIN_GET_MIB_CMDID,
- WMI_THIN_JOIN_CMDID,
- /* add new CMDID's here */
- WMI_THIN_RESERVED_END_CMDID = 0x8fff // WMI_THIN_RESERVED_END
-} WMI_THIN_COMMAND_ID;
-
-typedef enum{
- TEMPLATE_FRM_FIRST = 0,
- TEMPLATE_FRM_PROBE_REQ =TEMPLATE_FRM_FIRST,
- TEMPLATE_FRM_BEACON,
- TEMPLATE_FRM_PROBE_RESP,
- TEMPLATE_FRM_NULL,
- TEMPLATE_FRM_QOS_NULL,
- TEMPLATE_FRM_PSPOLL,
- TEMPLATE_FRM_MAX
-}WMI_TEMPLATE_FRM_TYPE;
-
-/* TEMPLATE_FRM_LEN... represent the maximum allowable
- * data lengths (bytes) for each frame type */
-#define TEMPLATE_FRM_LEN_PROBE_REQ (256) /* Symbian dictates a minimum of 256 for these 3 frame types */
-#define TEMPLATE_FRM_LEN_BEACON (256)
-#define TEMPLATE_FRM_LEN_PROBE_RESP (256)
-#define TEMPLATE_FRM_LEN_NULL (32)
-#define TEMPLATE_FRM_LEN_QOS_NULL (32)
-#define TEMPLATE_FRM_LEN_PSPOLL (32)
-#define TEMPLATE_FRM_LEN_SUM (TEMPLATE_FRM_LEN_PROBE_REQ + TEMPLATE_FRM_LEN_BEACON + TEMPLATE_FRM_LEN_PROBE_RESP + \
- TEMPLATE_FRM_LEN_NULL + TEMPLATE_FRM_LEN_QOS_NULL + TEMPLATE_FRM_LEN_PSPOLL)
-
-
-/* MAC Header Build Rules */
-/* These values allow the host to configure the
- * target code that is responsible for constructing
- * the MAC header. In cases where the MAC header
- * is provided by the host framework, the target
- * has a diminished responsibility over what fields
- * it must write. This will vary from framework to framework.
- * Symbian requires different behavior from MAC80211 which
- * requires different behavior from MS Native Wifi. */
-#define WMI_WRT_VER_TYPE 0x00000001
-#define WMI_WRT_DURATION 0x00000002
-#define WMI_WRT_DIRECTION 0x00000004
-#define WMI_WRT_POWER 0x00000008
-#define WMI_WRT_WEP 0x00000010
-#define WMI_WRT_MORE 0x00000020
-#define WMI_WRT_BSSID 0x00000040
-#define WMI_WRT_QOS 0x00000080
-#define WMI_WRT_SEQNO 0x00000100
-#define WMI_GUARD_TX 0x00000200 /* prevents TX ops that are not allowed for a current state */
-#define WMI_WRT_DEFAULT_CONFIG (WMI_WRT_VER_TYPE | WMI_WRT_DURATION | WMI_WRT_DIRECTION | \
- WMI_WRT_POWER | WMI_WRT_MORE | WMI_WRT_WEP | WMI_WRT_BSSID | \
- WMI_WRT_QOS | WMI_WRT_SEQNO | WMI_GUARD_TX)
-
-/* WMI_THIN_CONFIG_TXCOMPLETE -- Used to configure the params and content for
- * TX Complete messages the will come from the Target. these messages are
- * disabled by default but can be enabled using this structure and the
- * WMI_THIN_CONFIG_CMDID. */
-typedef PREPACK struct {
- u8 version; /* the versioned type of messages to use or 0 to disable */
- u8 countThreshold; /* msg count threshold triggering a tx complete message */
- u16 timeThreshold; /* timeout interval in MSEC triggering a tx complete message */
-} POSTPACK WMI_THIN_CONFIG_TXCOMPLETE;
-
-/* WMI_THIN_CONFIG_DECRYPT_ERR -- Used to configure behavior for received frames
- * that have decryption errors. The default behavior is to discard the frame
- * without notification. Alternately, the MAC Header is forwarded to the host
- * with the failed status. */
-typedef PREPACK struct {
- u8 enable; /* 1 == send decrypt errors to the host, 0 == don't */
- u8 reserved[3]; /* align padding */
-} POSTPACK WMI_THIN_CONFIG_DECRYPT_ERR;
-
-/* WMI_THIN_CONFIG_TX_MAC_RULES -- Used to configure behavior for transmitted
- * frames that require partial MAC header construction. These rules
- * are used by the target to indicate which fields need to be written. */
-typedef PREPACK struct {
- u32 rules; /* combination of WMI_WRT_... values */
-} POSTPACK WMI_THIN_CONFIG_TX_MAC_RULES;
-
-/* WMI_THIN_CONFIG_RX_FILTER_RULES -- Used to configure behavior for received
- * frames as to which frames should get forwarded to the host and which
- * should get processed internally. */
-typedef PREPACK struct {
- u32 rules; /* combination of WMI_FILT_... values */
-} POSTPACK WMI_THIN_CONFIG_RX_FILTER_RULES;
-
-/* WMI_THIN_CONFIG_CMD -- Used to contain some combination of the above
- * WMI_THIN_CONFIG_... structures. The actual combination is indicated
- * by the value of cfgField. Each bit in this field corresponds to
- * one of the above structures. */
-typedef PREPACK struct {
-#define WMI_THIN_CFG_TXCOMP 0x00000001
-#define WMI_THIN_CFG_DECRYPT 0x00000002
-#define WMI_THIN_CFG_MAC_RULES 0x00000004
-#define WMI_THIN_CFG_FILTER_RULES 0x00000008
- u32 cfgField; /* combination of WMI_THIN_CFG_... describes contents of config command */
- u16 length; /* length in bytes of appended sub-commands */
- u8 reserved[2]; /* align padding */
-} POSTPACK WMI_THIN_CONFIG_CMD;
-
-/* MIB Access Identifiers tailored for Symbian. */
-enum {
- MIB_ID_STA_MAC = 1, // [READONLY]
- MIB_ID_RX_LIFE_TIME, // [NOT IMPLEMENTED]
- MIB_ID_SLOT_TIME, // [READ/WRITE]
- MIB_ID_RTS_THRESHOLD, // [READ/WRITE]
- MIB_ID_CTS_TO_SELF, // [READ/WRITE]
- MIB_ID_TEMPLATE_FRAME, // [WRITE ONLY]
- MIB_ID_RXFRAME_FILTER, // [READ/WRITE]
- MIB_ID_BEACON_FILTER_TABLE, // [WRITE ONLY]
- MIB_ID_BEACON_FILTER, // [READ/WRITE]
- MIB_ID_BEACON_LOST_COUNT, // [WRITE ONLY]
- MIB_ID_RSSI_THRESHOLD, // [WRITE ONLY]
- MIB_ID_HT_CAP, // [NOT IMPLEMENTED]
- MIB_ID_HT_OP, // [NOT IMPLEMENTED]
- MIB_ID_HT_2ND_BEACON, // [NOT IMPLEMENTED]
- MIB_ID_HT_BLOCK_ACK, // [NOT IMPLEMENTED]
- MIB_ID_PREAMBLE, // [READ/WRITE]
- /*MIB_ID_GROUP_ADDR_TABLE,*/
- /*MIB_ID_WEP_DEFAULT_KEY_ID */
- /*MIB_ID_TX_POWER */
- /*MIB_ID_ARP_IP_TABLE */
- /*MIB_ID_SLEEP_MODE */
- /*MIB_ID_WAKE_INTERVAL*/
- /*MIB_ID_STAT_TABLE*/
- /*MIB_ID_IBSS_PWR_SAVE*/
- /*MIB_ID_COUNTERS_TABLE*/
- /*MIB_ID_ETHERTYPE_FILTER*/
- /*MIB_ID_BC_UDP_FILTER*/
-
-};
-
-typedef PREPACK struct {
- u8 addr[ATH_MAC_LEN];
-} POSTPACK WMI_THIN_MIB_STA_MAC;
-
-typedef PREPACK struct {
- u32 time; // units == msec
-} POSTPACK WMI_THIN_MIB_RX_LIFE_TIME;
-
-typedef PREPACK struct {
- u8 enable; //1 = on, 0 = off
-} POSTPACK WMI_THIN_MIB_CTS_TO_SELF;
-
-typedef PREPACK struct {
- u32 time; // units == usec
-} POSTPACK WMI_THIN_MIB_SLOT_TIME;
-
-typedef PREPACK struct {
- u16 length; //units == bytes
-} POSTPACK WMI_THIN_MIB_RTS_THRESHOLD;
-
-typedef PREPACK struct {
- u8 type; // type of frame
- u8 rate; // tx rate to be used (one of WMI_BIT_RATE)
- u16 length; // num bytes following this structure as the template data
-} POSTPACK WMI_THIN_MIB_TEMPLATE_FRAME;
-
-typedef PREPACK struct {
-#define FRAME_FILTER_PROMISCUOUS 0x00000001
-#define FRAME_FILTER_BSSID 0x00000002
- u32 filterMask;
-} POSTPACK WMI_THIN_MIB_RXFRAME_FILTER;
-
-
-#define IE_FILTER_TREATMENT_CHANGE 1
-#define IE_FILTER_TREATMENT_APPEAR 2
-
-typedef PREPACK struct {
- u8 ie;
- u8 treatment;
-} POSTPACK WMI_THIN_MIB_BEACON_FILTER_TABLE;
-
-typedef PREPACK struct {
- u8 ie;
- u8 treatment;
- u8 oui[3];
- u8 type;
- u16 version;
-} POSTPACK WMI_THIN_MIB_BEACON_FILTER_TABLE_OUI;
-
-typedef PREPACK struct {
- u16 numElements;
- u8 entrySize; // sizeof(WMI_THIN_MIB_BEACON_FILTER_TABLE) on host cpu may be 2 may be 4
- u8 reserved;
-} POSTPACK WMI_THIN_MIB_BEACON_FILTER_TABLE_HEADER;
-
-typedef PREPACK struct {
- u32 count; /* num beacons between deliveries */
- u8 enable;
- u8 reserved[3];
-} POSTPACK WMI_THIN_MIB_BEACON_FILTER;
-
-typedef PREPACK struct {
- u32 count; /* num consec lost beacons after which send event */
-} POSTPACK WMI_THIN_MIB_BEACON_LOST_COUNT;
-
-typedef PREPACK struct {
- u8 rssi; /* the low threshold which can trigger an event warning */
- u8 tolerance; /* the range above and below the threshold to prevent event flooding to the host. */
- u8 count; /* the sample count of consecutive frames necessary to trigger an event. */
- u8 reserved[1]; /* padding */
-} POSTPACK WMI_THIN_MIB_RSSI_THRESHOLD;
-
-
-typedef PREPACK struct {
- u32 cap;
- u32 rxRateField;
- u32 beamForming;
- u8 addr[ATH_MAC_LEN];
- u8 enable;
- u8 stbc;
- u8 maxAMPDU;
- u8 msduSpacing;
- u8 mcsFeedback;
- u8 antennaSelCap;
-} POSTPACK WMI_THIN_MIB_HT_CAP;
-
-typedef PREPACK struct {
- u32 infoField;
- u32 basicRateField;
- u8 protection;
- u8 secondChanneloffset;
- u8 channelWidth;
- u8 reserved;
-} POSTPACK WMI_THIN_MIB_HT_OP;
-
-typedef PREPACK struct {
-#define SECOND_BEACON_PRIMARY 1
-#define SECOND_BEACON_EITHER 2
-#define SECOND_BEACON_SECONDARY 3
- u8 cfg;
- u8 reserved[3]; /* padding */
-} POSTPACK WMI_THIN_MIB_HT_2ND_BEACON;
-
-typedef PREPACK struct {
- u8 txTIDField;
- u8 rxTIDField;
- u8 reserved[2]; /* padding */
-} POSTPACK WMI_THIN_MIB_HT_BLOCK_ACK;
-
-typedef PREPACK struct {
- u8 enableLong; // 1 == long preamble, 0 == short preamble
- u8 reserved[3];
-} POSTPACK WMI_THIN_MIB_PREAMBLE;
-
-typedef PREPACK struct {
- u16 length; /* the length in bytes of the appended MIB data */
- u8 mibID; /* the ID of the MIB element being set */
- u8 reserved; /* align padding */
-} POSTPACK WMI_THIN_SET_MIB_CMD;
-
-typedef PREPACK struct {
- u8 mibID; /* the ID of the MIB element being set */
- u8 reserved[3]; /* align padding */
-} POSTPACK WMI_THIN_GET_MIB_CMD;
-
-typedef PREPACK struct {
- u32 basicRateMask; /* bit mask of basic rates */
- u32 beaconIntval; /* TUs */
- u16 atimWindow; /* TUs */
- u16 channel; /* frequency in Mhz */
- u8 networkType; /* INFRA_NETWORK | ADHOC_NETWORK */
- u8 ssidLength; /* 0 - 32 */
- u8 probe; /* != 0 : issue probe req at start */
- u8 reserved; /* alignment */
- u8 ssid[WMI_MAX_SSID_LEN];
- u8 bssid[ATH_MAC_LEN];
-} POSTPACK WMI_THIN_JOIN_CMD;
-
-typedef PREPACK struct {
- u16 dtim; /* dtim interval in num beacons */
- u16 aid; /* 80211 AID from Assoc resp */
-} POSTPACK WMI_THIN_POST_ASSOC_CMD;
-
-typedef enum {
- WMI_THIN_EVENTID_RESERVED_START = 0x8000,
- WMI_THIN_GET_MIB_EVENTID,
- WMI_THIN_JOIN_EVENTID,
-
- /* Add new THIN EVENTID's here */
- WMI_THIN_EVENTID_RESERVED_END = 0x8fff
-} WMI_THIN_EVENT_ID;
-
-/* Possible values for WMI_THIN_JOIN_EVENT.result */
-typedef enum {
- WMI_THIN_JOIN_RES_SUCCESS = 0, // device has joined the network
- WMI_THIN_JOIN_RES_FAIL, // device failed for unspecified reason
- WMI_THIN_JOIN_RES_TIMEOUT, // device failed due to no beacon rx in time limit
- WMI_THIN_JOIN_RES_BAD_PARAM, // device failed due to bad cmd param.
-}WMI_THIN_JOIN_RESULT;
-
-typedef PREPACK struct {
- u8 result; /* the result of the join cmd. one of WMI_THIN_JOIN_RESULT */
- u8 reserved[3]; /* alignment */
-} POSTPACK WMI_THIN_JOIN_EVENT;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _WMI_THIN_H_ */
diff --git a/drivers/staging/ath6kl/include/common/wmix.h b/drivers/staging/ath6kl/include/common/wmix.h
index 36acba6..9435eab 100644
--- a/drivers/staging/ath6kl/include/common/wmix.h
+++ b/drivers/staging/ath6kl/include/common/wmix.h
@@ -40,10 +40,6 @@
extern "C" {
#endif
-#ifndef ATH_TARGET
-#include "athstartpack.h"
-#endif
-
#include "dbglog.h"
/*
@@ -148,7 +144,6 @@
* All masks are 18-bit masks with bit N operating on GPIO pin N.
*/
-#include "gpio.h"
/*
* Set GPIO pin output state.
@@ -268,9 +263,6 @@
u32 count;
} POSTPACK WMIX_PROF_COUNT_EVENT;
-#ifndef ATH_TARGET
-#include "athendpack.h"
-#endif
#ifdef __cplusplus
}
diff --git a/drivers/staging/ath6kl/include/common_drv.h b/drivers/staging/ath6kl/include/common_drv.h
index b606334..34db299 100644
--- a/drivers/staging/ath6kl/include/common_drv.h
+++ b/drivers/staging/ath6kl/include/common_drv.h
@@ -81,10 +81,6 @@
u32 MboxIsrYieldValue,
u8 HtcControlBuffers);
-int ar6000_prepare_target(struct hif_device *hifDevice,
- u32 TargetType,
- u32 TargetVersion);
-
int ar6000_set_hci_bridge_flags(struct hif_device *hifDevice,
u32 TargetType,
u32 Flags);
diff --git a/drivers/staging/ath6kl/include/gpio_api.h b/drivers/staging/ath6kl/include/gpio_api.h
deleted file mode 100644
index 6b4c547..0000000
--- a/drivers/staging/ath6kl/include/gpio_api.h
+++ /dev/null
@@ -1,59 +0,0 @@
-//------------------------------------------------------------------------------
-// <copyright file="gpio_api.h" company="Atheros">
-// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
-//
-//
-// Permission to use, copy, modify, and/or distribute this software for any
-// purpose with or without fee is hereby granted, provided that the above
-// copyright notice and this permission notice appear in all copies.
-//
-// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-//
-//
-//------------------------------------------------------------------------------
-//==============================================================================
-// Host-side General Purpose I/O API.
-//
-// Author(s): ="Atheros"
-//==============================================================================
-#ifndef _GPIO_API_H_
-#define _GPIO_API_H_
-
-/*
- * Send a command to the Target in order to change output on GPIO pins.
- */
-int wmi_gpio_output_set(struct wmi_t *wmip,
- u32 set_mask,
- u32 clear_mask,
- u32 enable_mask,
- u32 disable_mask);
-
-/*
- * Send a command to the Target requesting input state of GPIO pins.
- */
-int wmi_gpio_input_get(struct wmi_t *wmip);
-
-/*
- * Send a command to the Target to change the value of a GPIO register.
- */
-int wmi_gpio_register_set(struct wmi_t *wmip,
- u32 gpioreg_id,
- u32 value);
-
-/*
- * Send a command to the Target to fetch the value of a GPIO register.
- */
-int wmi_gpio_register_get(struct wmi_t *wmip, u32 gpioreg_id);
-
-/*
- * Send a command to the Target, acknowledging some GPIO interrupts.
- */
-int wmi_gpio_intr_ack(struct wmi_t *wmip, u32 ack_mask);
-
-#endif /* _GPIO_API_H_ */
diff --git a/drivers/staging/ath6kl/include/hif.h b/drivers/staging/ath6kl/include/hif.h
index 83650d5..24200e7 100644
--- a/drivers/staging/ath6kl/include/hif.h
+++ b/drivers/staging/ath6kl/include/hif.h
@@ -32,7 +32,6 @@
/* Header files */
#include "a_config.h"
#include "athdefs.h"
-#include "a_types.h"
#include "a_osapi.h"
#include "dl_list.h"
@@ -148,7 +147,7 @@
*
* HIF_DEVICE_GET_MBOX_BLOCK_SIZE
* input : none
- * output : array of 4 A_UINT32s
+ * output : array of 4 u32s
* notes: block size is returned for each mailbox (4)
*
* HIF_DEVICE_GET_MBOX_ADDR
diff --git a/drivers/staging/ath6kl/include/target_reg_table.h b/drivers/staging/ath6kl/include/target_reg_table.h
deleted file mode 100644
index e2225d5..0000000
--- a/drivers/staging/ath6kl/include/target_reg_table.h
+++ /dev/null
@@ -1,244 +0,0 @@
-//------------------------------------------------------------------------------
-// <copyright file="target_reg_table.h" company="Atheros">
-// Copyright (c) 2004-2010 Atheros Corporation. All rights reserved.
-//
-//
-// Permission to use, copy, modify, and/or distribute this software for any
-// purpose with or without fee is hereby granted, provided that the above
-// copyright notice and this permission notice appear in all copies.
-//
-// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-//
-//
-//------------------------------------------------------------------------------
-//==============================================================================
-// Target register table macros and structure definitions
-//
-// Author(s): ="Atheros"
-//==============================================================================
-
-#ifndef TARGET_REG_TABLE_H_
-#define TARGET_REG_TABLE_H_
-
-#include "targaddrs.h"
-
-/*** WARNING : Add to the end of the TABLE! do not change the order ****/
-typedef struct targetdef_s {
- u32 d_RTC_BASE_ADDRESS;
- u32 d_SYSTEM_SLEEP_OFFSET;
- u32 d_SYSTEM_SLEEP_DISABLE_LSB;
- u32 d_SYSTEM_SLEEP_DISABLE_MASK;
- u32 d_CLOCK_CONTROL_OFFSET;
- u32 d_CLOCK_CONTROL_SI0_CLK_MASK;
- u32 d_RESET_CONTROL_OFFSET;
- u32 d_RESET_CONTROL_SI0_RST_MASK;
- u32 d_GPIO_BASE_ADDRESS;
- u32 d_GPIO_PIN0_OFFSET;
- u32 d_GPIO_PIN1_OFFSET;
- u32 d_GPIO_PIN0_CONFIG_MASK;
- u32 d_GPIO_PIN1_CONFIG_MASK;
- u32 d_SI_CONFIG_BIDIR_OD_DATA_LSB;
- u32 d_SI_CONFIG_BIDIR_OD_DATA_MASK;
- u32 d_SI_CONFIG_I2C_LSB;
- u32 d_SI_CONFIG_I2C_MASK;
- u32 d_SI_CONFIG_POS_SAMPLE_LSB;
- u32 d_SI_CONFIG_POS_SAMPLE_MASK;
- u32 d_SI_CONFIG_INACTIVE_CLK_LSB;
- u32 d_SI_CONFIG_INACTIVE_CLK_MASK;
- u32 d_SI_CONFIG_INACTIVE_DATA_LSB;
- u32 d_SI_CONFIG_INACTIVE_DATA_MASK;
- u32 d_SI_CONFIG_DIVIDER_LSB;
- u32 d_SI_CONFIG_DIVIDER_MASK;
- u32 d_SI_BASE_ADDRESS;
- u32 d_SI_CONFIG_OFFSET;
- u32 d_SI_TX_DATA0_OFFSET;
- u32 d_SI_TX_DATA1_OFFSET;
- u32 d_SI_RX_DATA0_OFFSET;
- u32 d_SI_RX_DATA1_OFFSET;
- u32 d_SI_CS_OFFSET;
- u32 d_SI_CS_DONE_ERR_MASK;
- u32 d_SI_CS_DONE_INT_MASK;
- u32 d_SI_CS_START_LSB;
- u32 d_SI_CS_START_MASK;
- u32 d_SI_CS_RX_CNT_LSB;
- u32 d_SI_CS_RX_CNT_MASK;
- u32 d_SI_CS_TX_CNT_LSB;
- u32 d_SI_CS_TX_CNT_MASK;
- u32 d_BOARD_DATA_SZ;
- u32 d_BOARD_EXT_DATA_SZ;
-} TARGET_REGISTER_TABLE;
-
-#define BOARD_DATA_SZ_MAX 2048
-
-#if defined(MY_TARGET_DEF) /* { */
-
-#ifdef ATH_REG_TABLE_DIRECT_ASSIGN
-
-static struct targetdef_s my_target_def = {
- RTC_BASE_ADDRESS,
- SYSTEM_SLEEP_OFFSET,
- SYSTEM_SLEEP_DISABLE_LSB,
- SYSTEM_SLEEP_DISABLE_MASK,
- CLOCK_CONTROL_OFFSET,
- CLOCK_CONTROL_SI0_CLK_MASK,
- RESET_CONTROL_OFFSET,
- RESET_CONTROL_SI0_RST_MASK,
- GPIO_BASE_ADDRESS,
- GPIO_PIN0_OFFSET,
- GPIO_PIN0_CONFIG_MASK,
- GPIO_PIN1_OFFSET,
- GPIO_PIN1_CONFIG_MASK,
- SI_CONFIG_BIDIR_OD_DATA_LSB,
- SI_CONFIG_BIDIR_OD_DATA_MASK,
- SI_CONFIG_I2C_LSB,
- SI_CONFIG_I2C_MASK,
- SI_CONFIG_POS_SAMPLE_LSB,
- SI_CONFIG_POS_SAMPLE_MASK,
- SI_CONFIG_INACTIVE_CLK_LSB,
- SI_CONFIG_INACTIVE_CLK_MASK,
- SI_CONFIG_INACTIVE_DATA_LSB,
- SI_CONFIG_INACTIVE_DATA_MASK,
- SI_CONFIG_DIVIDER_LSB,
- SI_CONFIG_DIVIDER_MASK,
- SI_BASE_ADDRESS,
- SI_CONFIG_OFFSET,
- SI_TX_DATA0_OFFSET,
- SI_TX_DATA1_OFFSET,
- SI_RX_DATA0_OFFSET,
- SI_RX_DATA1_OFFSET,
- SI_CS_OFFSET,
- SI_CS_DONE_ERR_MASK,
- SI_CS_DONE_INT_MASK,
- SI_CS_START_LSB,
- SI_CS_START_MASK,
- SI_CS_RX_CNT_LSB,
- SI_CS_RX_CNT_MASK,
- SI_CS_TX_CNT_LSB,
- SI_CS_TX_CNT_MASK,
- MY_TARGET_BOARD_DATA_SZ,
- MY_TARGET_BOARD_EXT_DATA_SZ,
-};
-
-#else
-
-static struct targetdef_s my_target_def = {
- .d_RTC_BASE_ADDRESS = RTC_BASE_ADDRESS,
- .d_SYSTEM_SLEEP_OFFSET = SYSTEM_SLEEP_OFFSET,
- .d_SYSTEM_SLEEP_DISABLE_LSB = SYSTEM_SLEEP_DISABLE_LSB,
- .d_SYSTEM_SLEEP_DISABLE_MASK = SYSTEM_SLEEP_DISABLE_MASK,
- .d_CLOCK_CONTROL_OFFSET = CLOCK_CONTROL_OFFSET,
- .d_CLOCK_CONTROL_SI0_CLK_MASK = CLOCK_CONTROL_SI0_CLK_MASK,
- .d_RESET_CONTROL_OFFSET = RESET_CONTROL_OFFSET,
- .d_RESET_CONTROL_SI0_RST_MASK = RESET_CONTROL_SI0_RST_MASK,
- .d_GPIO_BASE_ADDRESS = GPIO_BASE_ADDRESS,
- .d_GPIO_PIN0_OFFSET = GPIO_PIN0_OFFSET,
- .d_GPIO_PIN0_CONFIG_MASK = GPIO_PIN0_CONFIG_MASK,
- .d_GPIO_PIN1_OFFSET = GPIO_PIN1_OFFSET,
- .d_GPIO_PIN1_CONFIG_MASK = GPIO_PIN1_CONFIG_MASK,
- .d_SI_CONFIG_BIDIR_OD_DATA_LSB = SI_CONFIG_BIDIR_OD_DATA_LSB,
- .d_SI_CONFIG_BIDIR_OD_DATA_MASK = SI_CONFIG_BIDIR_OD_DATA_MASK,
- .d_SI_CONFIG_I2C_LSB = SI_CONFIG_I2C_LSB,
- .d_SI_CONFIG_I2C_MASK = SI_CONFIG_I2C_MASK,
- .d_SI_CONFIG_POS_SAMPLE_LSB = SI_CONFIG_POS_SAMPLE_LSB,
- .d_SI_CONFIG_POS_SAMPLE_MASK = SI_CONFIG_POS_SAMPLE_MASK,
- .d_SI_CONFIG_INACTIVE_CLK_LSB = SI_CONFIG_INACTIVE_CLK_LSB,
- .d_SI_CONFIG_INACTIVE_CLK_MASK = SI_CONFIG_INACTIVE_CLK_MASK,
- .d_SI_CONFIG_INACTIVE_DATA_LSB = SI_CONFIG_INACTIVE_DATA_LSB,
- .d_SI_CONFIG_INACTIVE_DATA_MASK = SI_CONFIG_INACTIVE_DATA_MASK,
- .d_SI_CONFIG_DIVIDER_LSB = SI_CONFIG_DIVIDER_LSB,
- .d_SI_CONFIG_DIVIDER_MASK = SI_CONFIG_DIVIDER_MASK,
- .d_SI_BASE_ADDRESS = SI_BASE_ADDRESS,
- .d_SI_CONFIG_OFFSET = SI_CONFIG_OFFSET,
- .d_SI_TX_DATA0_OFFSET = SI_TX_DATA0_OFFSET,
- .d_SI_TX_DATA1_OFFSET = SI_TX_DATA1_OFFSET,
- .d_SI_RX_DATA0_OFFSET = SI_RX_DATA0_OFFSET,
- .d_SI_RX_DATA1_OFFSET = SI_RX_DATA1_OFFSET,
- .d_SI_CS_OFFSET = SI_CS_OFFSET,
- .d_SI_CS_DONE_ERR_MASK = SI_CS_DONE_ERR_MASK,
- .d_SI_CS_DONE_INT_MASK = SI_CS_DONE_INT_MASK,
- .d_SI_CS_START_LSB = SI_CS_START_LSB,
- .d_SI_CS_START_MASK = SI_CS_START_MASK,
- .d_SI_CS_RX_CNT_LSB = SI_CS_RX_CNT_LSB,
- .d_SI_CS_RX_CNT_MASK = SI_CS_RX_CNT_MASK,
- .d_SI_CS_TX_CNT_LSB = SI_CS_TX_CNT_LSB,
- .d_SI_CS_TX_CNT_MASK = SI_CS_TX_CNT_MASK,
- .d_BOARD_DATA_SZ = MY_TARGET_BOARD_DATA_SZ,
- .d_BOARD_EXT_DATA_SZ = MY_TARGET_BOARD_EXT_DATA_SZ,
-};
-
-#endif
-
-#if MY_TARGET_BOARD_DATA_SZ > BOARD_DATA_SZ_MAX
-#error "BOARD_DATA_SZ_MAX is too small"
-#endif
-
-struct targetdef_s *MY_TARGET_DEF = &my_target_def;
-
-#else /* } { */
-
-#define RTC_BASE_ADDRESS (targetdef->d_RTC_BASE_ADDRESS)
-#define SYSTEM_SLEEP_OFFSET (targetdef->d_SYSTEM_SLEEP_OFFSET)
-#define SYSTEM_SLEEP_DISABLE_LSB (targetdef->d_SYSTEM_SLEEP_DISABLE_LSB)
-#define SYSTEM_SLEEP_DISABLE_MASK (targetdef->d_SYSTEM_SLEEP_DISABLE_MASK)
-#define CLOCK_CONTROL_OFFSET (targetdef->d_CLOCK_CONTROL_OFFSET)
-#define CLOCK_CONTROL_SI0_CLK_MASK (targetdef->d_CLOCK_CONTROL_SI0_CLK_MASK)
-#define RESET_CONTROL_OFFSET (targetdef->d_RESET_CONTROL_OFFSET)
-#define RESET_CONTROL_SI0_RST_MASK (targetdef->d_RESET_CONTROL_SI0_RST_MASK)
-#define GPIO_BASE_ADDRESS (targetdef->d_GPIO_BASE_ADDRESS)
-#define GPIO_PIN0_OFFSET (targetdef->d_GPIO_PIN0_OFFSET)
-#define GPIO_PIN0_CONFIG_MASK (targetdef->d_GPIO_PIN0_CONFIG_MASK)
-#define GPIO_PIN1_OFFSET (targetdef->d_GPIO_PIN1_OFFSET)
-#define GPIO_PIN1_CONFIG_MASK (targetdef->d_GPIO_PIN1_CONFIG_MASK)
-#define SI_CONFIG_BIDIR_OD_DATA_LSB (targetdef->d_SI_CONFIG_BIDIR_OD_DATA_LSB)
-#define SI_CONFIG_BIDIR_OD_DATA_MASK (targetdef->d_SI_CONFIG_BIDIR_OD_DATA_MASK)
-#define SI_CONFIG_I2C_LSB (targetdef->d_SI_CONFIG_I2C_LSB)
-#define SI_CONFIG_I2C_MASK (targetdef->d_SI_CONFIG_I2C_MASK)
-#define SI_CONFIG_POS_SAMPLE_LSB (targetdef->d_SI_CONFIG_POS_SAMPLE_LSB)
-#define SI_CONFIG_POS_SAMPLE_MASK (targetdef->d_SI_CONFIG_POS_SAMPLE_MASK)
-#define SI_CONFIG_INACTIVE_CLK_LSB (targetdef->d_SI_CONFIG_INACTIVE_CLK_LSB)
-#define SI_CONFIG_INACTIVE_CLK_MASK (targetdef->d_SI_CONFIG_INACTIVE_CLK_MASK)
-#define SI_CONFIG_INACTIVE_DATA_LSB (targetdef->d_SI_CONFIG_INACTIVE_DATA_LSB)
-#define SI_CONFIG_INACTIVE_DATA_MASK (targetdef->d_SI_CONFIG_INACTIVE_DATA_MASK)
-#define SI_CONFIG_DIVIDER_LSB (targetdef->d_SI_CONFIG_DIVIDER_LSB)
-#define SI_CONFIG_DIVIDER_MASK (targetdef->d_SI_CONFIG_DIVIDER_MASK)
-#define SI_BASE_ADDRESS (targetdef->d_SI_BASE_ADDRESS)
-#define SI_CONFIG_OFFSET (targetdef->d_SI_CONFIG_OFFSET)
-#define SI_TX_DATA0_OFFSET (targetdef->d_SI_TX_DATA0_OFFSET)
-#define SI_TX_DATA1_OFFSET (targetdef->d_SI_TX_DATA1_OFFSET)
-#define SI_RX_DATA0_OFFSET (targetdef->d_SI_RX_DATA0_OFFSET)
-#define SI_RX_DATA1_OFFSET (targetdef->d_SI_RX_DATA1_OFFSET)
-#define SI_CS_OFFSET (targetdef->d_SI_CS_OFFSET)
-#define SI_CS_DONE_ERR_MASK (targetdef->d_SI_CS_DONE_ERR_MASK)
-#define SI_CS_DONE_INT_MASK (targetdef->d_SI_CS_DONE_INT_MASK)
-#define SI_CS_START_LSB (targetdef->d_SI_CS_START_LSB)
-#define SI_CS_START_MASK (targetdef->d_SI_CS_START_MASK)
-#define SI_CS_RX_CNT_LSB (targetdef->d_SI_CS_RX_CNT_LSB)
-#define SI_CS_RX_CNT_MASK (targetdef->d_SI_CS_RX_CNT_MASK)
-#define SI_CS_TX_CNT_LSB (targetdef->d_SI_CS_TX_CNT_LSB)
-#define SI_CS_TX_CNT_MASK (targetdef->d_SI_CS_TX_CNT_MASK)
-#define EEPROM_SZ (targetdef->d_BOARD_DATA_SZ)
-#define EEPROM_EXT_SZ (targetdef->d_BOARD_EXT_DATA_SZ)
-
-/* SET macros */
-#define SYSTEM_SLEEP_DISABLE_SET(x) (((x) << SYSTEM_SLEEP_DISABLE_LSB) & SYSTEM_SLEEP_DISABLE_MASK)
-#define SI_CONFIG_BIDIR_OD_DATA_SET(x) (((x) << SI_CONFIG_BIDIR_OD_DATA_LSB) & SI_CONFIG_BIDIR_OD_DATA_MASK)
-#define SI_CONFIG_I2C_SET(x) (((x) << SI_CONFIG_I2C_LSB) & SI_CONFIG_I2C_MASK)
-#define SI_CONFIG_POS_SAMPLE_SET(x) (((x) << SI_CONFIG_POS_SAMPLE_LSB) & SI_CONFIG_POS_SAMPLE_MASK)
-#define SI_CONFIG_INACTIVE_CLK_SET(x) (((x) << SI_CONFIG_INACTIVE_CLK_LSB) & SI_CONFIG_INACTIVE_CLK_MASK)
-#define SI_CONFIG_INACTIVE_DATA_SET(x) (((x) << SI_CONFIG_INACTIVE_DATA_LSB) & SI_CONFIG_INACTIVE_DATA_MASK)
-#define SI_CONFIG_DIVIDER_SET(x) (((x) << SI_CONFIG_DIVIDER_LSB) & SI_CONFIG_DIVIDER_MASK)
-#define SI_CS_START_SET(x) (((x) << SI_CS_START_LSB) & SI_CS_START_MASK)
-#define SI_CS_RX_CNT_SET(x) (((x) << SI_CS_RX_CNT_LSB) & SI_CS_RX_CNT_MASK)
-#define SI_CS_TX_CNT_SET(x) (((x) << SI_CS_TX_CNT_LSB) & SI_CS_TX_CNT_MASK)
-
-#endif /* } */
-
-#endif /*TARGET_REG_TABLE_H_*/
-
-
diff --git a/drivers/staging/ath6kl/miscdrv/ar3kconfig.c b/drivers/staging/ath6kl/miscdrv/ar3kconfig.c
index 4f18f43..e0ea218 100644
--- a/drivers/staging/ath6kl/miscdrv/ar3kconfig.c
+++ b/drivers/staging/ath6kl/miscdrv/ar3kconfig.c
@@ -24,7 +24,6 @@
#include "a_config.h"
#include "athdefs.h"
-#include "a_types.h"
#include "a_osapi.h"
#define ATH_MODULE_NAME misc
#include "a_debug.h"
@@ -78,7 +77,7 @@
} while (false);
if (pPacket != NULL) {
- A_FREE(pPacket);
+ kfree(pPacket);
}
return status;
@@ -116,7 +115,7 @@
} while (false);
if (pRecvPacket != NULL) {
- A_FREE(pRecvPacket);
+ kfree(pRecvPacket);
}
return status;
@@ -203,7 +202,7 @@
} while (false);
if (pBuffer != NULL) {
- A_FREE(pBuffer);
+ kfree(pBuffer);
}
return status;
@@ -268,7 +267,7 @@
} while (false);
if (pBufferToFree != NULL) {
- A_FREE(pBufferToFree);
+ kfree(pBufferToFree);
}
return status;
@@ -304,7 +303,7 @@
}
if (pBufferToFree != NULL) {
- A_FREE(pBufferToFree);
+ kfree(pBufferToFree);
}
return status;
@@ -328,7 +327,7 @@
}
if (pBufferToFree != NULL) {
- A_FREE(pBufferToFree);
+ kfree(pBufferToFree);
}
return status;
@@ -382,7 +381,7 @@
&pEvent,
&pBufferToFree);
if (pBufferToFree != NULL) {
- A_FREE(pBufferToFree);
+ kfree(pBufferToFree);
}
if (status) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("HostWakeup Config Failed! \n"));
@@ -397,7 +396,7 @@
&pEvent,
&pBufferToFree);
if (pBufferToFree != NULL) {
- A_FREE(pBufferToFree);
+ kfree(pBufferToFree);
}
if (status) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Target Wakeup Config Failed! \n"));
@@ -412,7 +411,7 @@
&pEvent,
&pBufferToFree);
if (pBufferToFree != NULL) {
- A_FREE(pBufferToFree);
+ kfree(pBufferToFree);
}
if (status) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("HostWakeup Enable Failed! \n"));
@@ -427,7 +426,7 @@
&pEvent,
&pBufferToFree);
if (pBufferToFree != NULL) {
- A_FREE(pBufferToFree);
+ kfree(pBufferToFree);
}
if (status) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Target Wakeup Enable Failed! \n"));
@@ -442,7 +441,7 @@
&pEvent,
&pBufferToFree);
if (pBufferToFree != NULL) {
- A_FREE(pBufferToFree);
+ kfree(pBufferToFree);
}
if (status) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Sleep Enable Failed! \n"));
diff --git a/drivers/staging/ath6kl/miscdrv/ar3kps/ar3kpsconfig.c b/drivers/staging/ath6kl/miscdrv/ar3kps/ar3kpsconfig.c
index 8393efe..282ceac 100644
--- a/drivers/staging/ath6kl/miscdrv/ar3kps/ar3kpsconfig.c
+++ b/drivers/staging/ath6kl/miscdrv/ar3kps/ar3kpsconfig.c
@@ -222,7 +222,7 @@
A_RELEASE_FIRMWARE(firmware);
/* Parse the PS buffer to a global variable */
status = AthDoParsePS(buffer,len);
- A_FREE(buffer);
+ kfree(buffer);
} else {
A_RELEASE_FIRMWARE(firmware);
}
@@ -256,7 +256,7 @@
A_RELEASE_FIRMWARE(firmware);
/* parse and store the Patch file contents to a global variables */
status = AthDoParsePatch(buffer,len);
- A_FREE(buffer);
+ kfree(buffer);
} else {
A_RELEASE_FIRMWARE(firmware);
}
@@ -283,7 +283,7 @@
&bufferToFree) == 0) {
if(ReadPSEvent(event) == 0) { /* Exit if the status is success */
if(bufferToFree != NULL) {
- A_FREE(bufferToFree);
+ kfree(bufferToFree);
}
#ifndef HCI_TRANSPORT_SDIO
@@ -295,7 +295,7 @@
goto complete;
}
if(bufferToFree != NULL) {
- A_FREE(bufferToFree);
+ kfree(bufferToFree);
}
} else {
status = 0;
@@ -312,13 +312,13 @@
&bufferToFree) == 0) {
if(ReadPSEvent(event) != 0) { /* Exit if the status is success */
if(bufferToFree != NULL) {
- A_FREE(bufferToFree);
+ kfree(bufferToFree);
}
status = 1;
goto complete;
}
if(bufferToFree != NULL) {
- A_FREE(bufferToFree);
+ kfree(bufferToFree);
}
} else {
status = 0;
@@ -376,10 +376,10 @@
AthFreeCommandList(&HciCmdList,numCmds);
}
if(path) {
- A_FREE(path);
+ kfree(path);
}
if(config_path) {
- A_FREE(config_path);
+ kfree(config_path);
}
return status;
}
@@ -511,7 +511,7 @@
}
if(bufferToFree != NULL) {
- A_FREE(bufferToFree);
+ kfree(bufferToFree);
}
return result;
@@ -527,7 +527,7 @@
}
if(bufferToFree != NULL) {
- A_FREE(bufferToFree);
+ kfree(bufferToFree);
}
return result;
}
@@ -564,7 +564,7 @@
}
if(bufferToFree != NULL) {
- A_FREE(bufferToFree);
+ kfree(bufferToFree);
}
return result;
}
diff --git a/drivers/staging/ath6kl/miscdrv/ar3kps/ar3kpsparser.c b/drivers/staging/ath6kl/miscdrv/ar3kps/ar3kpsparser.c
index 94a0939..c01c0cb 100644
--- a/drivers/staging/ath6kl/miscdrv/ar3kps/ar3kpsparser.c
+++ b/drivers/staging/ath6kl/miscdrv/ar3kps/ar3kpsparser.c
@@ -362,7 +362,7 @@
{
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("error\n"));
if(Buffer != NULL) {
- A_FREE(Buffer);
+ kfree(Buffer);
}
return A_ERROR;
}
@@ -401,7 +401,7 @@
if(uGetInputDataFormat(pCharLine, &stPS_DataFormat)) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("uGetInputDataFormat fail\n"));
if(Buffer != NULL) {
- A_FREE(Buffer);
+ kfree(Buffer);
}
return A_ERROR;
}
@@ -422,7 +422,7 @@
if(uGetInputDataFormat(pCharLine, &stPS_DataFormat)) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("uGetInputDataFormat fail \n"));
if(Buffer != NULL) {
- A_FREE(Buffer);
+ kfree(Buffer);
}
return A_ERROR;
}
@@ -433,7 +433,7 @@
if (ByteCount > LINE_SIZE_MAX/2)
{
if(Buffer != NULL) {
- A_FREE(Buffer);
+ kfree(Buffer);
}
return A_ERROR;
}
@@ -449,7 +449,7 @@
if(uGetInputDataFormat(pCharLine,&stPS_DataFormat)) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("uGetInputDataFormat Fail\n"));
if(Buffer != NULL) {
- A_FREE(Buffer);
+ kfree(Buffer);
}
return A_ERROR;
}
@@ -510,7 +510,7 @@
{
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("\n Buffer over flow PS File too big!!!"));
if(Buffer != NULL) {
- A_FREE(Buffer);
+ kfree(Buffer);
}
return A_ERROR;
//Sleep (3000);
@@ -524,7 +524,7 @@
default:
{
if(Buffer != NULL) {
- A_FREE(Buffer);
+ kfree(Buffer);
}
return A_ERROR;
}
@@ -541,13 +541,13 @@
{
if(Buffer != NULL) {
- A_FREE(Buffer);
+ kfree(Buffer);
}
return A_ERROR;
}
if(Buffer != NULL) {
- A_FREE(Buffer);
+ kfree(Buffer);
}
return 0;
@@ -609,7 +609,7 @@
/* Handle case when the number of patch buffer is more than the 20K */
if(MAX_NUM_PATCH_ENTRY == Patch_Count) {
for(i = 0; i < Patch_Count; i++) {
- A_FREE(RamPatch[i].Data);
+ kfree(RamPatch[i].Data);
}
return A_ERROR;
}
@@ -812,13 +812,13 @@
for(count = 0; count < Patch_Count; count++) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Freeing Patch Buffer %d \r\n",count));
- A_FREE(RamPatch[Patch_Count].Data);
+ kfree(RamPatch[Patch_Count].Data);
}
for(count = 0; count < Tag_Count; count++) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Freeing PS Buffer %d \r\n",count));
- A_FREE(PsTagEntry[count].TagData);
+ kfree(PsTagEntry[count].TagData);
}
/*
@@ -962,8 +962,8 @@
return A_ERROR;
}
for(i = 0; i < numPackets;i++) {
- A_FREE((*HciPacketList)[i].Hcipacket);
+ kfree((*HciPacketList)[i].Hcipacket);
}
- A_FREE(*HciPacketList);
+ kfree(*HciPacketList);
return 0;
}
diff --git a/drivers/staging/ath6kl/miscdrv/ar3kps/ar3kpsparser.h b/drivers/staging/ath6kl/miscdrv/ar3kps/ar3kpsparser.h
index 9378efc..4e0f2f7 100644
--- a/drivers/staging/ath6kl/miscdrv/ar3kps/ar3kpsparser.h
+++ b/drivers/staging/ath6kl/miscdrv/ar3kps/ar3kpsparser.h
@@ -33,7 +33,6 @@
#include "athdefs.h"
#ifdef HCI_TRANSPORT_SDIO
#include "a_config.h"
-#include "a_types.h"
#include "a_osapi.h"
#define ATH_MODULE_NAME misc
#include "a_debug.h"
@@ -60,11 +59,6 @@
#ifndef A_MALLOC
#define A_MALLOC(size) kmalloc((size),GFP_KERNEL)
#endif /* A_MALLOC */
-
-
-#ifndef A_FREE
-#define A_FREE(addr) kfree((addr))
-#endif /* A_MALLOC */
#endif /* HCI_TRANSPORT_UART */
/* String manipulation APIs */
diff --git a/drivers/staging/ath6kl/miscdrv/common_drv.c b/drivers/staging/ath6kl/miscdrv/common_drv.c
index a23a524..1ce539a 100644
--- a/drivers/staging/ath6kl/miscdrv/common_drv.c
+++ b/drivers/staging/ath6kl/miscdrv/common_drv.c
@@ -23,15 +23,12 @@
#include "a_config.h"
#include "athdefs.h"
-#include "a_types.h"
-#include "AR6002/hw2.0/hw/mbox_host_reg.h"
-#include "AR6002/hw2.0/hw/apb_map.h"
-#include "AR6002/hw2.0/hw/si_reg.h"
-#include "AR6002/hw2.0/hw/gpio_reg.h"
-#include "AR6002/hw2.0/hw/rtc_reg.h"
-#include "AR6002/hw2.0/hw/vmc_reg.h"
-#include "AR6002/hw2.0/hw/mbox_reg.h"
+#include "hw/mbox_host_reg.h"
+#include "gpio_reg.h"
+#include "hw/rtc_reg.h"
+#include "hw/mbox_reg.h"
+#include "hw/apb_map.h"
#include "a_osapi.h"
#include "targaddrs.h"
@@ -683,119 +680,6 @@
return status;
}
-
-static int prepare_ar6002(struct hif_device *hifDevice, u32 TargetVersion)
-{
- int status = 0;
-
- /* placeholder */
-
- return status;
-}
-
-static int prepare_ar6003(struct hif_device *hifDevice, u32 TargetVersion)
-{
- int status = 0;
-
- /* placeholder */
-
- return status;
-}
-
-/* this function assumes the caller has already initialized the BMI APIs */
-int ar6000_prepare_target(struct hif_device *hifDevice,
- u32 TargetType,
- u32 TargetVersion)
-{
- if (TargetType == TARGET_TYPE_AR6002) {
- /* do any preparations for AR6002 devices */
- return prepare_ar6002(hifDevice,TargetVersion);
- } else if (TargetType == TARGET_TYPE_AR6003) {
- return prepare_ar6003(hifDevice,TargetVersion);
- }
-
- return 0;
-}
-
-#if defined(CONFIG_AR6002_REV1_FORCE_HOST)
-/*
- * Call this function just before the call to BMIInit
- * in order to force* AR6002 rev 1.x firmware to detect a Host.
- * THIS IS FOR USE ONLY WITH AR6002 REV 1.x.
- * TBDXXX: Remove this function when REV 1.x is desupported.
- */
-int
-ar6002_REV1_reset_force_host (struct hif_device *hifDevice)
-{
- s32 i;
- struct forceROM_s {
- u32 addr;
- u32 data;
- };
- struct forceROM_s *ForceROM;
- s32 szForceROM;
- int status = 0;
- u32 address;
- u32 data;
-
- /* Force AR6002 REV1.x to recognize Host presence.
- *
- * Note: Use RAM at 0x52df80..0x52dfa0 with ROM Remap entry 0
- * so that this workaround functions with AR6002.war1.sh. We
- * could fold that entire workaround into this one, but it's not
- * worth the effort at this point. This workaround cannot be
- * merged into the other workaround because this must be done
- * before BMI.
- */
-
- static struct forceROM_s ForceROM_NEW[] = {
- {0x52df80, 0x20f31c07},
- {0x52df84, 0x92374420},
- {0x52df88, 0x1d120c03},
- {0x52df8c, 0xff8216f0},
- {0x52df90, 0xf01d120c},
- {0x52df94, 0x81004136},
- {0x52df98, 0xbc9100bd},
- {0x52df9c, 0x00bba100},
-
- {0x00008000|MC_TCAM_TARGET_ADDRESS, 0x0012dfe0}, /* Use remap entry 0 */
- {0x00008000|MC_TCAM_COMPARE_ADDRESS, 0x000e2380},
- {0x00008000|MC_TCAM_MASK_ADDRESS, 0x00000000},
- {0x00008000|MC_TCAM_VALID_ADDRESS, 0x00000001},
-
- {0x00018000|(LOCAL_COUNT_ADDRESS+0x10), 0}, /* clear BMI credit counter */
-
- {0x00004000|AR6002_RESET_CONTROL_ADDRESS, RESET_CONTROL_WARM_RST_MASK},
- };
-
- address = 0x004ed4b0; /* REV1 target software ID is stored here */
- status = ar6000_ReadRegDiag(hifDevice, &address, &data);
- if (status || (data != AR6002_VERSION_REV1)) {
- return A_ERROR; /* Not AR6002 REV1 */
- }
-
- ForceROM = ForceROM_NEW;
- szForceROM = sizeof(ForceROM_NEW)/sizeof(*ForceROM);
-
- ATH_DEBUG_PRINTF (DBG_MISC_DRV, ATH_DEBUG_TRC, ("Force Target to recognize Host....\n"));
- for (i = 0; i < szForceROM; i++)
- {
- if (ar6000_WriteRegDiag(hifDevice,
- &ForceROM[i].addr,
- &ForceROM[i].data) != 0)
- {
- ATH_DEBUG_PRINTF (DBG_MISC_DRV, ATH_DEBUG_TRC, ("Cannot force Target to recognize Host!\n"));
- return A_ERROR;
- }
- }
-
- A_MDELAY(1000);
-
- return 0;
-}
-
-#endif /* CONFIG_AR6002_REV1_FORCE_HOST */
-
void DebugDumpBytes(u8 *buffer, u16 length, char *pDescription)
{
char stream[60];
diff --git a/drivers/staging/ath6kl/miscdrv/credit_dist.c b/drivers/staging/ath6kl/miscdrv/credit_dist.c
index 33fa020..c777e98 100644
--- a/drivers/staging/ath6kl/miscdrv/credit_dist.c
+++ b/drivers/staging/ath6kl/miscdrv/credit_dist.c
@@ -23,7 +23,6 @@
#include "a_config.h"
#include "athdefs.h"
-#include "a_types.h"
#include "a_osapi.h"
#define ATH_MODULE_NAME misc
#include "a_debug.h"
diff --git a/drivers/staging/ath6kl/os/linux/ar6000_android.c b/drivers/staging/ath6kl/os/linux/ar6000_android.c
deleted file mode 100644
index 4aa75ee..0000000
--- a/drivers/staging/ath6kl/os/linux/ar6000_android.c
+++ /dev/null
@@ -1,388 +0,0 @@
-//------------------------------------------------------------------------------
-// Copyright (c) 2004-2010 Atheros Communications Inc.
-// All rights reserved.
-//
-//
-//
-// Permission to use, copy, modify, and/or distribute this software for any
-// purpose with or without fee is hereby granted, provided that the above
-// copyright notice and this permission notice appear in all copies.
-//
-// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-//
-//
-//
-// Author(s): ="Atheros"
-//------------------------------------------------------------------------------
-#include "ar6000_drv.h"
-#include "htc.h"
-#include <linux/vmalloc.h>
-#include <linux/fs.h>
-
-#ifdef CONFIG_HAS_EARLYSUSPEND
-#include <linux/earlysuspend.h>
-#endif
-
-bool enable_mmc_host_detect_change = false;
-static void ar6000_enable_mmchost_detect_change(int enable);
-
-
-char fwpath[256] = "/system/wifi";
-int wowledon;
-unsigned int enablelogcat;
-
-extern int bmienable;
-extern struct net_device *ar6000_devices[];
-extern char ifname[];
-
-const char def_ifname[] = "wlan0";
-module_param_string(fwpath, fwpath, sizeof(fwpath), 0644);
-module_param(enablelogcat, uint, 0644);
-module_param(wowledon, int, 0644);
-
-#ifdef CONFIG_HAS_EARLYSUSPEND
-static int screen_is_off;
-static struct early_suspend ar6k_early_suspend;
-#endif
-
-static int (*ar6000_avail_ev_p)(void *, void *);
-
-#if defined(CONFIG_ANDROID_LOGGER) && (!defined(CONFIG_MMC_MSM))
-int logger_write(const enum logidx index,
- const unsigned char prio,
- const char __kernel * const tag,
- const char __kernel * const fmt,
- ...)
-{
- int ret = 0;
- va_list vargs;
- struct file *filp = (struct file *)-ENOENT;
- mm_segment_t oldfs;
- struct iovec vec[3];
- int tag_bytes = strlen(tag) + 1, msg_bytes;
- char *msg;
- va_start(vargs, fmt);
- msg = kvasprintf(GFP_ATOMIC, fmt, vargs);
- va_end(vargs);
- if (!msg)
- return -ENOMEM;
- if (in_interrupt()) {
- /* we have no choice since aio_write may be blocked */
- printk(KERN_ALERT "%s", msg);
- goto out_free_message;
- }
- msg_bytes = strlen(msg) + 1;
- if (msg_bytes <= 1) /* empty message? */
- goto out_free_message; /* don't bother, then */
- if ((msg_bytes + tag_bytes + 1) > 2048) {
- ret = -E2BIG;
- goto out_free_message;
- }
-
- vec[0].iov_base = (unsigned char *) &prio;
- vec[0].iov_len = 1;
- vec[1].iov_base = (void *) tag;
- vec[1].iov_len = strlen(tag) + 1;
- vec[2].iov_base = (void *) msg;
- vec[2].iov_len = strlen(msg) + 1;
-
- oldfs = get_fs();
- set_fs(KERNEL_DS);
- do {
- filp = filp_open("/dev/log/main", O_WRONLY, S_IRUSR);
- if (IS_ERR(filp) || !filp->f_op) {
- AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: filp_open /dev/log/main error\n", __FUNCTION__));
- ret = -ENOENT;
- break;
- }
-
- if (filp->f_op->aio_write) {
- int nr_segs = sizeof(vec) / sizeof(vec[0]);
- int len = vec[0].iov_len + vec[1].iov_len + vec[2].iov_len;
- struct kiocb kiocb;
- init_sync_kiocb(&kiocb, filp);
- kiocb.ki_pos = 0;
- kiocb.ki_left = len;
- kiocb.ki_nbytes = len;
- ret = filp->f_op->aio_write(&kiocb, vec, nr_segs, kiocb.ki_pos);
- }
-
- } while (0);
-
- if (!IS_ERR(filp)) {
- filp_close(filp, NULL);
- }
- set_fs(oldfs);
-out_free_message:
- kfree(msg);
- return ret;
-}
-#endif
-
-int android_logger_lv(void *module, int mask)
-{
- switch (mask) {
- case ATH_DEBUG_ERR:
- return 6;
- case ATH_DEBUG_INFO:
- return 4;
- case ATH_DEBUG_WARN:
- return 5;
- case ATH_DEBUG_TRC:
- return 3;
- default:
-#ifdef DEBUG
- if (!module) {
- return 3;
- } else if (module == &GET_ATH_MODULE_DEBUG_VAR_NAME(driver)) {
- return (mask <=ATH_DEBUG_MAKE_MODULE_MASK(3)) ? 3 : 2;
- } else if (module == &GET_ATH_MODULE_DEBUG_VAR_NAME(htc)) {
- return 2;
- } else {
- return 3;
- }
-#else
- return 3; /* DEBUG */
-#endif
- }
-}
-
-static int android_readwrite_file(const char *filename, char *rbuf, const char *wbuf, size_t length)
-{
- int ret = 0;
- struct file *filp = (struct file *)-ENOENT;
- mm_segment_t oldfs;
- oldfs = get_fs();
- set_fs(KERNEL_DS);
- do {
- int mode = (wbuf) ? O_RDWR : O_RDONLY;
- filp = filp_open(filename, mode, S_IRUSR);
- if (IS_ERR(filp) || !filp->f_op) {
- AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: file %s filp_open error\n", __FUNCTION__, filename));
- ret = -ENOENT;
- break;
- }
-
- if (length==0) {
- /* Read the length of the file only */
- struct inode *inode;
-
- inode = GET_INODE_FROM_FILEP(filp);
- if (!inode) {
- AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Get inode from %s failed\n", __FUNCTION__, filename));
- ret = -ENOENT;
- break;
- }
- ret = i_size_read(inode->i_mapping->host);
- break;
- }
-
- if (wbuf) {
- if ( (ret=filp->f_op->write(filp, wbuf, length, &filp->f_pos)) < 0) {
- AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Write %u bytes to file %s error %d\n", __FUNCTION__,
- length, filename, ret));
- break;
- }
- } else {
- if ( (ret=filp->f_op->read(filp, rbuf, length, &filp->f_pos)) < 0) {
- AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Read %u bytes from file %s error %d\n", __FUNCTION__,
- length, filename, ret));
- break;
- }
- }
- } while (0);
-
- if (!IS_ERR(filp)) {
- filp_close(filp, NULL);
- }
- set_fs(oldfs);
-
- return ret;
-}
-
-int android_request_firmware(const struct firmware **firmware_p, const char *name,
- struct device *device)
-{
- int ret = 0;
- struct firmware *firmware;
- char filename[256];
- const char *raw_filename = name;
- *firmware_p = firmware = kzalloc(sizeof(*firmware), GFP_KERNEL);
- if (!firmware)
- return -ENOMEM;
- sprintf(filename, "%s/%s", fwpath, raw_filename);
- do {
- size_t length, bufsize, bmisize;
-
- if ( (ret=android_readwrite_file(filename, NULL, NULL, 0)) < 0) {
- break;
- } else {
- length = ret;
- }
-
- bufsize = ALIGN(length, PAGE_SIZE);
- bmisize = A_ROUND_UP(length, 4);
- bufsize = max(bmisize, bufsize);
- firmware->data = vmalloc(bufsize);
- firmware->size = length;
- if (!firmware->data) {
- AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s: Cannot allocate buffer for firmware\n", __FUNCTION__));
- ret = -ENOMEM;
- break;
- }
-
- if ( (ret=android_readwrite_file(filename, (char*)firmware->data, NULL, length)) != length) {
- AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s: file read error, ret %d request %d\n", __FUNCTION__, ret, length));
- ret = -1;
- break;
- }
-
- } while (0);
-
- if (ret<0) {
- if (firmware) {
- if (firmware->data)
- vfree(firmware->data);
- kfree(firmware);
- }
- *firmware_p = NULL;
- } else {
- ret = 0;
- }
- return ret;
-}
-
-void android_release_firmware(const struct firmware *firmware)
-{
- if (firmware) {
- if (firmware->data)
- vfree(firmware->data);
- kfree(firmware);
- }
-}
-
-static int ar6000_android_avail_ev(void *context, void *hif_handle)
-{
- int ret;
- ar6000_enable_mmchost_detect_change(0);
- ret = ar6000_avail_ev_p(context, hif_handle);
- return ret;
-}
-
-/* Useful for qualcom platform to detect our wlan card for mmc stack */
-static void ar6000_enable_mmchost_detect_change(int enable)
-{
-#ifdef CONFIG_MMC_MSM
-#define MMC_MSM_DEV "msm_sdcc.1"
- char buf[3];
- int length;
-
- if (!enable_mmc_host_detect_change) {
- return;
- }
- length = snprintf(buf, sizeof(buf), "%d\n", enable ? 1 : 0);
- if (android_readwrite_file("/sys/devices/platform/" MMC_MSM_DEV "/detect_change",
- NULL, buf, length) < 0) {
- /* fall back to polling */
- android_readwrite_file("/sys/devices/platform/" MMC_MSM_DEV "/polling", NULL, buf, length);
- }
-#endif
-}
-
-#ifdef CONFIG_HAS_EARLYSUSPEND
-static void android_early_suspend(struct early_suspend *h)
-{
- screen_is_off = 1;
-}
-
-static void android_late_resume(struct early_suspend *h)
-{
- screen_is_off = 0;
-}
-#endif
-
-void android_module_init(OSDRV_CALLBACKS *osdrvCallbacks)
-{
- bmienable = 1;
- if (ifname[0] == '\0')
- strcpy(ifname, def_ifname);
-#ifdef CONFIG_HAS_EARLYSUSPEND
- ar6k_early_suspend.suspend = android_early_suspend;
- ar6k_early_suspend.resume = android_late_resume;
- ar6k_early_suspend.level = EARLY_SUSPEND_LEVEL_BLANK_SCREEN;
- register_early_suspend(&ar6k_early_suspend);
-#endif
-
- ar6000_avail_ev_p = osdrvCallbacks->deviceInsertedHandler;
- osdrvCallbacks->deviceInsertedHandler = ar6000_android_avail_ev;
-
- ar6000_enable_mmchost_detect_change(1);
-}
-
-void android_module_exit(void)
-{
-#ifdef CONFIG_HAS_EARLYSUSPEND
- unregister_early_suspend(&ar6k_early_suspend);
-#endif
- ar6000_enable_mmchost_detect_change(1);
-}
-
-#ifdef CONFIG_PM
-void android_ar6k_check_wow_status(struct ar6_softc *ar, struct sk_buff *skb, bool isEvent)
-{
- if (
-#ifdef CONFIG_HAS_EARLYSUSPEND
- screen_is_off &&
-#endif
- skb && ar->arConnected) {
- bool needWake = false;
- if (isEvent) {
- if (A_NETBUF_LEN(skb) >= sizeof(u16)) {
- u16 cmd = *(const u16 *)A_NETBUF_DATA(skb);
- switch (cmd) {
- case WMI_CONNECT_EVENTID:
- case WMI_DISCONNECT_EVENTID:
- needWake = true;
- break;
- default:
- /* dont wake lock the system for other event */
- break;
- }
- }
- } else if (A_NETBUF_LEN(skb) >= sizeof(ATH_MAC_HDR)) {
- ATH_MAC_HDR *datap = (ATH_MAC_HDR *)A_NETBUF_DATA(skb);
- if (!IEEE80211_IS_MULTICAST(datap->dstMac)) {
- switch (A_BE2CPU16(datap->typeOrLen)) {
- case 0x0800: /* IP */
- case 0x888e: /* EAPOL */
- case 0x88c7: /* RSN_PREAUTH */
- case 0x88b4: /* WAPI */
- needWake = true;
- break;
- case 0x0806: /* ARP is not important to hold wake lock */
- default:
- break;
- }
- }
- }
- if (needWake) {
- /* keep host wake up if there is any event and packate coming in*/
- if (wowledon) {
- char buf[32];
- int len = sprintf(buf, "on");
- android_readwrite_file("/sys/power/state", NULL, buf, len);
-
- len = sprintf(buf, "%d", 127);
- android_readwrite_file("/sys/class/leds/lcd-backlight/brightness",
- NULL, buf,len);
- }
- }
- }
-}
-#endif /* CONFIG_PM */
diff --git a/drivers/staging/ath6kl/os/linux/ar6000_drv.c b/drivers/staging/ath6kl/os/linux/ar6000_drv.c
index 97d6ce6..48dd9e3 100644
--- a/drivers/staging/ath6kl/os/linux/ar6000_drv.c
+++ b/drivers/staging/ath6kl/os/linux/ar6000_drv.c
@@ -27,9 +27,7 @@
*/
#include "ar6000_drv.h"
-#ifdef ATH6K_CONFIG_CFG80211
#include "cfg80211.h"
-#endif /* ATH6K_CONFIG_CFG80211 */
#include "htc.h"
#include "wmi_filter_linux.h"
#include "epping_test.h"
@@ -118,7 +116,6 @@
#endif
unsigned int processDot11Hdr = 0;
-int bmienable = BMIENABLE_DEFAULT;
char ifname[IFNAMSIZ] = {0,};
@@ -134,6 +131,8 @@
unsigned int enableuartprint = ENABLEUARTPRINT_DEFAULT;
unsigned int logWmiRawMsgs = 0;
unsigned int enabletimerwar = 0;
+unsigned int num_device = 1;
+unsigned int regscanmode;
unsigned int fwmode = 1;
unsigned int mbox_yield_limit = 99;
unsigned int enablerssicompensation = 0;
@@ -148,7 +147,6 @@
unsigned int nohifscattersupport = NOHIFSCATTERSUPPORT_DEFAULT;
unsigned int setuphci = SETUPHCI_DEFAULT;
-unsigned int setuphcipal = SETUPHCIPAL_DEFAULT;
unsigned int loghci = 0;
unsigned int setupbtdev = SETUPBTDEV_DEFAULT;
#ifndef EXPORT_HCI_BRIDGE_INTERFACE
@@ -156,15 +154,14 @@
unsigned int hciuartscale = HCIUARTSCALE_DEFAULT;
unsigned int hciuartstep = HCIUARTSTEP_DEFAULT;
#endif
-#ifdef CONFIG_CHECKSUM_OFFLOAD
unsigned int csumOffload=0;
unsigned int csumOffloadTest=0;
-#endif
unsigned int eppingtest=0;
+unsigned int mac_addr_method;
+unsigned int firmware_bridge;
module_param_string(ifname, ifname, sizeof(ifname), 0644);
module_param(wlaninitmode, int, 0644);
-module_param(bmienable, int, 0644);
module_param(bypasswmi, bool, 0644);
module_param(debuglevel, uint, 0644);
module_param(tspecCompliance, int, 0644);
@@ -182,9 +179,7 @@
module_param(allow_trace_signal, int, 0644);
module_param(enablerssicompensation, uint, 0644);
module_param(processDot11Hdr, uint, 0644);
-#ifdef CONFIG_CHECKSUM_OFFLOAD
module_param(csumOffload, uint, 0644);
-#endif
#ifdef CONFIG_HOST_TCMD_SUPPORT
module_param(testmode, uint, 0644);
#endif
@@ -192,7 +187,6 @@
module_param(nohifscattersupport, uint, 0644);
module_param(panic_on_assert, uint, 0644);
module_param(setuphci, uint, 0644);
-module_param(setuphcipal, uint, 0644);
module_param(loghci, uint, 0644);
module_param(setupbtdev, uint, 0644);
#ifndef EXPORT_HCI_BRIDGE_INTERFACE
@@ -288,20 +282,11 @@
static void ar6000_detect_error(unsigned long ptr);
static void ar6000_set_multicast_list(struct net_device *dev);
static struct net_device_stats *ar6000_get_stats(struct net_device *dev);
-static struct iw_statistics *ar6000_get_iwstats(struct net_device * dev);
static void disconnect_timer_handler(unsigned long ptr);
void read_rssi_compensation_param(struct ar6_softc *ar);
- /* for android builds we call external APIs that handle firmware download and configuration */
-#ifdef ANDROID_ENV
-/* !!!! Interim android support to make it easier to patch the default driver for
- * android use. You must define an external source file ar6000_android.c that handles the following
- * APIs */
-extern void android_module_init(OSDRV_CALLBACKS *osdrvCallbacks);
-extern void android_module_exit(void);
-#endif
/*
* HTC service connection handlers
*/
@@ -321,9 +306,7 @@
static HTC_SEND_FULL_ACTION ar6000_tx_queue_full(void *Context, struct htc_packet *pPacket);
-#ifdef ATH_AR6K_11N_SUPPORT
static void ar6000_alloc_netbufs(A_NETBUF_QUEUE_T *q, u16 num);
-#endif
static void ar6000_deliver_frames_to_nw_stack(void * dev, void *osbuf);
//static void ar6000_deliver_frames_to_bt_stack(void * dev, void *osbuf);
@@ -346,8 +329,6 @@
static int
ar6000_sysfs_bmi_init(struct ar6_softc *ar);
-/* HCI PAL callback function declarations */
-int ar6k_setup_hci_pal(struct ar6_softc *ar);
void ar6k_cleanup_hci_pal(struct ar6_softc *ar);
static void
@@ -362,16 +343,13 @@
struct net_device *ar6000_devices[MAX_AR6000];
static int is_netdev_registered;
-extern struct iw_handler_def ath_iw_handler_def;
DECLARE_WAIT_QUEUE_HEAD(arEvent);
static void ar6000_cookie_init(struct ar6_softc *ar);
static void ar6000_cookie_cleanup(struct ar6_softc *ar);
static void ar6000_free_cookie(struct ar6_softc *ar, struct ar_cookie * cookie);
static struct ar_cookie *ar6000_alloc_cookie(struct ar6_softc *ar);
-#ifdef USER_KEYS
static int ar6000_reinstall_keys(struct ar6_softc *ar,u8 key_op_ctrl);
-#endif
#ifdef CONFIG_AP_VIRTUAL_ADAPTER_SUPPORT
struct net_device *arApNetDev;
@@ -389,7 +367,6 @@
.ndo_open = ar6000_open,
.ndo_stop = ar6000_close,
.ndo_get_stats = ar6000_get_stats,
- .ndo_do_ioctl = ar6000_ioctl,
.ndo_start_xmit = ar6000_data_tx,
.ndo_set_multicast_list = ar6000_set_multicast_list,
};
@@ -612,7 +589,6 @@
send = dbglog_get_debug_fragment(&buffer[sent], length - sent,
MAX_WIRELESS_EVENT_SIZE);
while (send) {
- ar6000_send_event_to_app(ar, WMIX_DBGLOG_EVENTID, (u8 *)&buffer[sent], send);
sent += send;
send = dbglog_get_debug_fragment(&buffer[sent], length - sent,
MAX_WIRELESS_EVENT_SIZE);
@@ -631,7 +607,7 @@
ar6000_init_module(void)
{
static int probed = 0;
- int status;
+ int r;
OSDRV_CALLBACKS osdrvCallbacks;
a_module_debug_support_init();
@@ -664,12 +640,6 @@
osdrvCallbacks.devicePowerChangeHandler = ar6000_power_change_ev;
#endif
- ar6000_pm_init();
-
-#ifdef ANDROID_ENV
- android_module_init(&osdrvCallbacks);
-#endif
-
#ifdef DEBUG
/* Set the debug flags if specified at load time */
if(debugflags != 0)
@@ -687,13 +657,9 @@
memset(&aptcTR, 0, sizeof(APTC_TRAFFIC_RECORD));
#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
-#ifdef CONFIG_HOST_GPIO_SUPPORT
- ar6000_gpio_init();
-#endif /* CONFIG_HOST_GPIO_SUPPORT */
-
- status = HIFInit(&osdrvCallbacks);
- if (status)
- return -ENODEV;
+ r = HIFInit(&osdrvCallbacks);
+ if (r)
+ return r;
return 0;
}
@@ -723,12 +689,6 @@
a_module_debug_support_cleanup();
- ar6000_pm_exit();
-
-#ifdef ANDROID_ENV
- android_module_exit();
-#endif
-
AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("ar6000_cleanup: success\n"));
}
@@ -769,7 +729,6 @@
}
#endif /* ADAPTIVE_POWER_THROUGHPUT_CONTROL */
-#ifdef ATH_AR6K_11N_SUPPORT
static void
ar6000_alloc_netbufs(A_NETBUF_QUEUE_T *q, u16 num)
{
@@ -788,7 +747,6 @@
A_PRINTF("%s(), allocation of netbuf failed", __func__);
}
}
-#endif
static struct bin_attribute bmi_attr = {
.attr = {.name = "bmi", .mode = 0600},
@@ -894,8 +852,6 @@
} \
} while(0)
-#ifdef INIT_MODE_DRV_ENABLED
-
#ifdef SOFTMAC_FILE_USED
#define AR6002_MAC_ADDRESS_OFFSET 0x0A
#define AR6003_MAC_ADDRESS_OFFSET 0x16
@@ -982,7 +938,7 @@
}
source = "softmac file";
}
- A_FREE(macbuf);
+ kfree(macbuf);
}
A_RELEASE_FIRMWARE(softmac_entry);
}
@@ -1005,6 +961,8 @@
filename = AR6003_REV1_OTP_FILE;
} else if (ar->arVersion.target_ver == AR6003_REV2_VERSION) {
filename = AR6003_REV2_OTP_FILE;
+ } else if (ar->arVersion.target_ver == AR6003_REV3_VERSION) {
+ filename = AR6003_REV3_OTP_FILE;
} else {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unknown firmware revision: %d\n", ar->arVersion.target_ver));
return A_ERROR;
@@ -1016,6 +974,8 @@
filename = AR6003_REV1_FIRMWARE_FILE;
} else if (ar->arVersion.target_ver == AR6003_REV2_VERSION) {
filename = AR6003_REV2_FIRMWARE_FILE;
+ } else if (ar->arVersion.target_ver == AR6003_REV3_VERSION) {
+ filename = AR6003_REV3_FIRMWARE_FILE;
} else {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unknown firmware revision: %d\n", ar->arVersion.target_ver));
return A_ERROR;
@@ -1027,6 +987,8 @@
filename = AR6003_REV1_EPPING_FIRMWARE_FILE;
} else if (ar->arVersion.target_ver == AR6003_REV2_VERSION) {
filename = AR6003_REV2_EPPING_FIRMWARE_FILE;
+ } else if (ar->arVersion.target_ver == AR6003_REV3_VERSION) {
+ filename = AR6003_REV3_EPPING_FIRMWARE_FILE;
} else {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("eppingtest : unsupported firmware revision: %d\n",
ar->arVersion.target_ver));
@@ -1041,6 +1003,8 @@
filename = AR6003_REV1_TCMD_FIRMWARE_FILE;
} else if (ar->arVersion.target_ver == AR6003_REV2_VERSION) {
filename = AR6003_REV2_TCMD_FIRMWARE_FILE;
+ } else if (ar->arVersion.target_ver == AR6003_REV3_VERSION) {
+ filename = AR6003_REV3_TCMD_FIRMWARE_FILE;
} else {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unknown firmware revision: %d\n", ar->arVersion.target_ver));
return A_ERROR;
@@ -1068,6 +1032,8 @@
filename = AR6003_REV1_PATCH_FILE;
} else if (ar->arVersion.target_ver == AR6003_REV2_VERSION) {
filename = AR6003_REV2_PATCH_FILE;
+ } else if (ar->arVersion.target_ver == AR6003_REV3_VERSION) {
+ filename = AR6003_REV3_PATCH_FILE;
} else {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unknown firmware revision: %d\n", ar->arVersion.target_ver));
return A_ERROR;
@@ -1079,6 +1045,8 @@
filename = AR6003_REV1_BOARD_DATA_FILE;
} else if (ar->arVersion.target_ver == AR6003_REV2_VERSION) {
filename = AR6003_REV2_BOARD_DATA_FILE;
+ } else if (ar->arVersion.target_ver == AR6003_REV3_VERSION) {
+ filename = AR6003_REV3_BOARD_DATA_FILE;
} else {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unknown firmware revision: %d\n", ar->arVersion.target_ver));
return A_ERROR;
@@ -1133,8 +1101,10 @@
}
/* Record the fact that extended board Data IS initialized */
- param = 1;
- bmifn(BMIWriteMemory(ar->arHifDevice, HOST_INTEREST_ITEM_ADDRESS(ar, hi_board_ext_data_initialized), (u8 *)¶m, 4));
+ param = (board_ext_data_size << 16) | 1;
+ bmifn(BMIWriteMemory(ar->arHifDevice,
+ HOST_INTEREST_ITEM_ADDRESS(ar, hi_board_ext_data_config),
+ (unsigned char *)¶m, 4));
}
fw_entry_size = board_data_size;
}
@@ -1153,7 +1123,6 @@
A_RELEASE_FIRMWARE(fw_entry);
return 0;
}
-#endif /* INIT_MODE_DRV_ENABLED */
int
ar6000_update_bdaddr(struct ar6_softc *ar)
@@ -1200,7 +1169,6 @@
}
A_RELEASE_FIRMWARE(fw_entry);
-#ifdef INIT_MODE_DRV_ENABLED
} else {
/* The config is contained within the driver itself */
int status;
@@ -1293,7 +1261,9 @@
bmifn(BMIWriteMemory(ar->arHifDevice, HOST_INTEREST_ITEM_ADDRESS(ar, hi_board_data_initialized), (u8 *)¶m, 4));
/* Transfer One time Programmable data */
- AR6K_DATA_DOWNLOAD_ADDRESS(address, ar->arVersion.target_ver);
+ AR6K_APP_LOAD_ADDRESS(address, ar->arVersion.target_ver);
+ if (ar->arVersion.target_ver == AR6003_REV3_VERSION)
+ address = 0x1234;
status = ar6000_transfer_bin_file(ar, AR6K_OTP_FILE, address, true);
if (status == 0) {
/* Execute the OTP code */
@@ -1309,7 +1279,9 @@
}
/* Download Target firmware */
- AR6K_DATA_DOWNLOAD_ADDRESS(address, ar->arVersion.target_ver);
+ AR6K_APP_LOAD_ADDRESS(address, ar->arVersion.target_ver);
+ if (ar->arVersion.target_ver == AR6003_REV3_VERSION)
+ address = 0x1234;
if ((ar6000_transfer_bin_file(ar, AR6K_FIRMWARE_FILE, address, true)) != 0) {
return A_ERROR;
}
@@ -1318,25 +1290,16 @@
AR6K_APP_START_OVERRIDE_ADDRESS(address, ar->arVersion.target_ver);
bmifn(BMISetAppStart(ar->arHifDevice, address));
- /* Apply the patches */
- AR6K_PATCH_DOWNLOAD_ADDRESS(address, ar->arVersion.target_ver);
- if ((ar6000_transfer_bin_file(ar, AR6K_PATCH_FILE, address, false)) != 0) {
- return A_ERROR;
- }
-
- param = address;
- bmifn(BMIWriteMemory(ar->arHifDevice, HOST_INTEREST_ITEM_ADDRESS(ar, hi_dset_list_head), (u8 *)¶m, 4));
-
- if (ar->arTargetType == TARGET_TYPE_AR6003) {
- if (ar->arVersion.target_ver == AR6003_REV1_VERSION) {
- /* Reserve 5.5K of RAM */
- param = 5632;
- } else { /* AR6003_REV2_VERSION */
- /* Reserve 6.5K of RAM */
- param = 6656;
- }
- bmifn(BMIWriteMemory(ar->arHifDevice, HOST_INTEREST_ITEM_ADDRESS(ar, hi_end_RAM_reserve_sz), (u8 *)¶m, 4));
- }
+ if(ar->arTargetType == TARGET_TYPE_AR6003) {
+ AR6K_DATASET_PATCH_ADDRESS(address, ar->arVersion.target_ver);
+ if ((ar6000_transfer_bin_file(ar, AR6K_PATCH_FILE,
+ address, false)) != 0)
+ return A_ERROR;
+ param = address;
+ bmifn(BMIWriteMemory(ar->arHifDevice,
+ HOST_INTEREST_ITEM_ADDRESS(ar, hi_dset_list_head),
+ (unsigned char *)¶m, 4));
+ }
/* Restore system sleep */
address = RTC_BASE_ADDRESS + SYSTEM_SLEEP_ADDRESS;
@@ -1390,8 +1353,6 @@
msleep(1000);
}
#endif /* HTC_RAW_INTERFACE */
-
-#endif /* INIT_MODE_DRV_ENABLED */
}
return 0;
@@ -1470,7 +1431,11 @@
return A_ERROR;
}
+ param |= (num_device << HI_OPTION_NUM_DEV_SHIFT);
param |= (fwmode << HI_OPTION_FW_MODE_SHIFT);
+ param |= (mac_addr_method << HI_OPTION_MAC_ADDR_METHOD_SHIFT);
+ param |= (firmware_bridge << HI_OPTION_FW_BRIDGE_SHIFT);
+
if (BMIWriteMemory(ar->arHifDevice,
HOST_INTEREST_ITEM_ADDRESS(ar, hi_option_flag),
@@ -1518,18 +1483,34 @@
* It is difficult to patch the firmware boot code,
* but possible in theory.
*/
- if (ar->arTargetType == TARGET_TYPE_AR6003) {
- param = AR6003_BOARD_EXT_DATA_ADDRESS;
- if (BMIWriteMemory(ar->arHifDevice,
- HOST_INTEREST_ITEM_ADDRESS(ar, hi_board_ext_data),
- (u8 *)¶m,
- 4) != 0)
- {
- AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BMIWriteMemory for hi_board_ext_data failed \n"));
- return A_ERROR;
- }
- }
+ if (ar->arTargetType == TARGET_TYPE_AR6003) {
+ u32 ramReservedSz;
+ if (ar->arVersion.target_ver == AR6003_REV2_VERSION) {
+ param = AR6003_REV2_BOARD_EXT_DATA_ADDRESS;
+ ramReservedSz = AR6003_REV2_RAM_RESERVE_SIZE;
+ } else {
+ param = AR6003_REV3_BOARD_EXT_DATA_ADDRESS;
+ ramReservedSz = AR6003_REV3_RAM_RESERVE_SIZE;
+ }
+ if (BMIWriteMemory(ar->arHifDevice,
+ HOST_INTEREST_ITEM_ADDRESS(ar, hi_board_ext_data),
+ (u8 *)¶m, 4) != 0) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ ("BMIWriteMemory for "
+ "hi_board_ext_data failed\n"));
+ return A_ERROR;
+ }
+ if (BMIWriteMemory(ar->arHifDevice,
+ HOST_INTEREST_ITEM_ADDRESS(ar,
+ hi_end_RAM_reserve_sz),
+ (u8 *)&ramReservedSz, 4) != 0) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR ,
+ ("BMIWriteMemory for "
+ "hi_end_RAM_reserve_sz failed\n"));
+ return A_ERROR;
+ }
+ }
/* since BMIInit is called in the driver layer, we have to set the block
* size here for the target */
@@ -1555,9 +1536,6 @@
{
dev->netdev_ops = &ar6000_netdev_ops;
dev->watchdog_timeo = AR6000_TX_TIMEOUT;
- dev->wireless_handlers = &ath_iw_handler_def;
-
- ath_iw_handler_def.get_wireless_stats = ar6000_get_iwstats; /*Displayed via proc fs */
/*
* We need the OS to provide us with more headroom in order to
@@ -1575,10 +1553,6 @@
strcpy(dev->name, name);
}
-#ifdef SET_MODULE_OWNER
- SET_MODULE_OWNER(dev);
-#endif
-
#ifdef CONFIG_CHECKSUM_OFFLOAD
if(csumOffload){
dev->features |= NETIF_F_IP_CSUM; /*advertise kernel capability to do TCP/UDP CSUM offload for IPV4*/
@@ -1588,6 +1562,52 @@
return;
}
+static int __ath6kl_init_netdev(struct net_device *dev)
+{
+ int r;
+
+ rtnl_lock();
+ r = ar6000_init(dev);
+ rtnl_unlock();
+
+ if (r) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000_avail: ar6000_init\n"));
+ return r;
+ }
+
+ return 0;
+}
+
+#ifdef HTC_RAW_INTERFACE
+static int ath6kl_init_netdev_wmi(struct net_device *dev)
+{
+ if (!eppingtest && bypasswmi)
+ return 0;
+
+ return __ath6kl_init_netdev(dev);
+}
+#else
+static int ath6kl_init_netdev_wmi(struct net_device *dev)
+{
+ return __ath6kl_init_netdev(dev);
+}
+#endif
+
+static int ath6kl_init_netdev(struct ar6_softc *ar)
+{
+ int r;
+
+ r = ar6000_sysfs_bmi_get_config(ar, wlaninitmode);
+ if (r) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ ("ar6000_avail: "
+ "ar6000_sysfs_bmi_get_config failed\n"));
+ return r;
+ }
+
+ return ath6kl_init_netdev_wmi(ar->arNetDev);
+}
+
/*
* HTC Event handlers
*/
@@ -1600,10 +1620,8 @@
struct ar6_softc *ar;
int device_index = 0;
struct htc_init_info htcInfo;
-#ifdef ATH6K_CONFIG_CFG80211
struct wireless_dev *wdev;
-#endif /* ATH6K_CONFIG_CFG80211 */
- int init_status = 0;
+ int r = 0;
struct hif_device_os_device_info osDevInfo;
memset(&osDevInfo, 0, sizeof(osDevInfo));
@@ -1630,22 +1648,12 @@
/* we use another local "i" variable below. */
device_index = i;
-#ifdef ATH6K_CONFIG_CFG80211
wdev = ar6k_cfg80211_init(osDevInfo.pOSDevice);
if (IS_ERR(wdev)) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: ar6k_cfg80211_init failed\n", __func__));
return A_ERROR;
}
ar_netif = wdev_priv(wdev);
-#else
- dev = alloc_etherdev(sizeof(struct ar6_softc));
- if (dev == NULL) {
- AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000_available: can't alloc etherdev\n"));
- return A_ERROR;
- }
- ether_setup(dev);
- ar_netif = ar6k_priv(dev);
-#endif /* ATH6K_CONFIG_CFG80211 */
if (ar_netif == NULL) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: Can't allocate ar6k priv memory\n", __func__));
@@ -1655,7 +1663,6 @@
A_MEMZERO(ar_netif, sizeof(struct ar6_softc));
ar = (struct ar6_softc *)ar_netif;
-#ifdef ATH6K_CONFIG_CFG80211
ar->wdev = wdev;
wdev->iftype = NL80211_IFTYPE_STATION;
@@ -1671,15 +1678,10 @@
wdev->netdev = dev;
ar->arNetworkType = INFRA_NETWORK;
ar->smeState = SME_DISCONNECTED;
-#endif /* ATH6K_CONFIG_CFG80211 */
+ ar->arAutoAuthStage = AUTH_IDLE;
init_netdev(dev, ifname);
-#ifdef SET_NETDEV_DEV
- if (ar_netif) {
- SET_NETDEV_DEV(dev, osDevInfo.pOSDevice);
- }
-#endif
ar->arNetDev = dev;
ar->arHifDevice = hif_handle;
@@ -1719,35 +1721,23 @@
BMIInit();
- if (bmienable) {
- ar6000_sysfs_bmi_init(ar);
- }
+ ar6000_sysfs_bmi_init(ar);
{
struct bmi_target_info targ_info;
- if (BMIGetTargetInfo(ar->arHifDevice, &targ_info) != 0) {
- init_status = A_ERROR;
+ r = BMIGetTargetInfo(ar->arHifDevice, &targ_info);
+ if (r)
goto avail_ev_failed;
- }
ar->arVersion.target_ver = targ_info.target_ver;
ar->arTargetType = targ_info.target_type;
-
- /* do any target-specific preparation that can be done through BMI */
- if (ar6000_prepare_target(ar->arHifDevice,
- targ_info.target_type,
- targ_info.target_ver) != 0) {
- init_status = A_ERROR;
- goto avail_ev_failed;
- }
-
+ wdev->wiphy->hw_version = targ_info.target_ver;
}
- if (ar6000_configure_target(ar) != 0) {
- init_status = A_ERROR;
+ r = ar6000_configure_target(ar);
+ if (r)
goto avail_ev_failed;
- }
A_MEMZERO(&htcInfo,sizeof(htcInfo));
htcInfo.pContext = ar;
@@ -1755,8 +1745,8 @@
ar->arHtcTarget = HTCCreate(ar->arHifDevice,&htcInfo);
- if (ar->arHtcTarget == NULL) {
- init_status = A_ERROR;
+ if (!ar->arHtcTarget) {
+ r = -ENOMEM;
goto avail_ev_failed;
}
@@ -1767,22 +1757,19 @@
#endif
-#ifdef CONFIG_CHECKSUM_OFFLOAD
if(csumOffload){
/*if external frame work is also needed, change and use an extended rxMetaVerion*/
ar->rxMetaVersion=WMI_META_VERSION_2;
}
-#endif
-#ifdef ATH_AR6K_11N_SUPPORT
- if((ar->aggr_cntxt = aggr_init(ar6000_alloc_netbufs)) == NULL) {
+ ar->aggr_cntxt = aggr_init(ar6000_alloc_netbufs);
+ if (!ar->aggr_cntxt) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s() Failed to initialize aggr.\n", __func__));
- init_status = A_ERROR;
+ r = -ENOMEM;
goto avail_ev_failed;
}
aggr_register_rx_dispatcher(ar->aggr_cntxt, (void *)dev, ar6000_deliver_frames_to_nw_stack);
-#endif
HIFClaimDevice(ar->arHifDevice, ar);
@@ -1791,46 +1778,20 @@
/* when the module is unloaded. */
ar6000_devices[device_index] = dev;
- /* Don't install the init function if BMI is requested */
- if (!bmienable) {
- ar6000_netdev_ops.ndo_init = ar6000_init;
- } else {
- AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("BMI enabled: %d\n", wlaninitmode));
- if ((wlaninitmode == WLAN_INIT_MODE_UDEV) ||
- (wlaninitmode == WLAN_INIT_MODE_DRV))
- {
- int status = 0;
- do {
- if ((status = ar6000_sysfs_bmi_get_config(ar, wlaninitmode)) != 0)
- {
- AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000_avail: ar6000_sysfs_bmi_get_config failed\n"));
- break;
- }
-#ifdef HTC_RAW_INTERFACE
- if (!eppingtest && bypasswmi) {
- break; /* Don't call ar6000_init for ART */
- }
-#endif
- rtnl_lock();
- status = (ar6000_init(dev)==0) ? 0 : A_ERROR;
- rtnl_unlock();
- if (status) {
- AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000_avail: ar6000_init\n"));
- }
- } while (false);
-
- if (status) {
- init_status = status;
- goto avail_ev_failed;
- }
- }
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("BMI enabled: %d\n", wlaninitmode));
+ if ((wlaninitmode == WLAN_INIT_MODE_UDEV) ||
+ (wlaninitmode == WLAN_INIT_MODE_DRV)) {
+ r = ath6kl_init_netdev(ar);
+ if (r)
+ goto avail_ev_failed;
}
/* This runs the init function if registered */
- if (register_netdev(dev)) {
+ r = register_netdev(dev);
+ if (r) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000_avail: register_netdev failed\n"));
ar6000_destroy(dev, 0);
- return A_ERROR;
+ return r;
}
is_netdev_registered = 1;
@@ -1843,13 +1804,10 @@
(unsigned long)ar));
avail_ev_failed :
- if (init_status) {
- if (bmienable) {
- ar6000_sysfs_bmi_deinit(ar);
- }
- }
+ if (r)
+ ar6000_sysfs_bmi_deinit(ar);
- return init_status;
+ return r;
}
static void ar6000_target_failure(void *Instance, int Status)
@@ -1880,9 +1838,6 @@
sip = true;
errEvent.errorVal = WMI_TARGET_COM_ERR |
WMI_TARGET_FATAL_ERR;
- ar6000_send_event_to_app(ar, WMI_ERROR_REPORT_EVENTID,
- (u8 *)&errEvent,
- sizeof(WMI_TARGET_ERROR_REPORT_EVENT));
}
}
}
@@ -1980,10 +1935,8 @@
ar6000_disconnect_event(ar, DISCONNECT_CMD, ar->arBssid, 0, NULL, 0);
}
}
-#ifdef USER_KEYS
ar->user_savedkeys_stat = USER_SAVEDKEYS_STAT_INIT;
ar->user_key_ctrl = 0;
-#endif
}
AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("%s(): WMI stopped\n", __func__));
@@ -2025,15 +1978,6 @@
if (setuphci)
ar6000_cleanup_hci(ar);
#endif
-#ifdef EXPORT_HCI_PAL_INTERFACE
- if (setuphcipal && (NULL != ar6kHciPalCallbacks_g.cleanupTransport)) {
- ar6kHciPalCallbacks_g.cleanupTransport(ar);
- }
-#else
- /* cleanup hci pal driver data structures */
- if(setuphcipal)
- ar6k_cleanup_hci_pal(ar);
-#endif
AR_DEBUG_PRINTF(ATH_DEBUG_INFO,(" Shutting down HTC .... \n"));
/* stop HTC */
HTCStop(ar->arHtcTarget);
@@ -2094,9 +2038,6 @@
if (ar->arWlanPowerState != WLAN_POWER_STATE_CUT_PWR) {
/* only stop endpoint if we are not stop it in suspend_ev */
ar6000_stop_endpoint(dev, false, true);
- } else {
- /* clear up the platform power state before rmmod */
- plat_setup_power(1,0);
}
ar->arWlanState = WLAN_DISABLED;
@@ -2110,9 +2051,7 @@
HIFReleaseDevice(ar->arHifDevice);
HIFShutDownDevice(ar->arHifDevice);
}
-#ifdef ATH_AR6K_11N_SUPPORT
aggr_module_destroy(ar->aggr_cntxt);
-#endif
/* Done with cookies */
ar6000_cookie_cleanup(ar);
@@ -2120,9 +2059,7 @@
/* cleanup any allocated AMSDU buffers */
ar6000_cleanup_amsdu_rxbufs(ar);
- if (bmienable) {
- ar6000_sysfs_bmi_deinit(ar);
- }
+ ar6000_sysfs_bmi_deinit(ar);
/* Cleanup BMI */
BMICleanup();
@@ -2134,7 +2071,7 @@
#ifdef HTC_RAW_INTERFACE
if (ar->arRawHtc) {
- A_FREE(ar->arRawHtc);
+ kfree(ar->arRawHtc);
ar->arRawHtc = NULL;
}
#endif
@@ -2145,9 +2082,7 @@
}
free_netdev(dev);
-#ifdef ATH6K_CONFIG_CFG80211
ar6k_cfg80211_deinit(ar);
-#endif /* ATH6K_CONFIG_CFG80211 */
#ifdef CONFIG_AP_VIRTUL_ADAPTER_SUPPORT
ar6000_remove_ap_interface();
@@ -2187,9 +2122,6 @@
ar->arHBChallengeResp.seqNum = 0;
errEvent.errorVal = WMI_TARGET_COM_ERR | WMI_TARGET_FATAL_ERR;
AR6000_SPIN_UNLOCK(&ar->arLock, 0);
- ar6000_send_event_to_app(ar, WMI_ERROR_REPORT_EVENTID,
- (u8 *)&errEvent,
- sizeof(WMI_TARGET_ERROR_REPORT_EVENT));
return;
}
@@ -2295,11 +2227,9 @@
spin_lock_irqsave(&ar->arLock, flags);
-#ifdef ATH6K_CONFIG_CFG80211
if(ar->arWlanState == WLAN_DISABLED) {
ar->arWlanState = WLAN_ENABLED;
}
-#endif /* ATH6K_CONFIG_CFG80211 */
if( ar->arConnected || bypasswmi) {
netif_carrier_on(dev);
@@ -2316,12 +2246,9 @@
static int
ar6000_close(struct net_device *dev)
{
-#ifdef ATH6K_CONFIG_CFG80211
struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
-#endif /* ATH6K_CONFIG_CFG80211 */
netif_stop_queue(dev);
-#ifdef ATH6K_CONFIG_CFG80211
ar6000_disconnect(ar);
if(ar->arWmiReady == true) {
@@ -2332,7 +2259,6 @@
ar->arWlanState = WLAN_DISABLED;
}
ar6k_cfg80211_scanComplete_event(ar, A_ECANCELED);
-#endif /* ATH6K_CONFIG_CFG80211 */
return 0;
}
@@ -2422,16 +2348,52 @@
return(arEndpoint2Ac(ar, ep ));
}
+#if defined(CONFIG_ATH6KL_ENABLE_COEXISTENCE)
+static int ath6kl_config_btcoex_params(struct ar6_softc *ar)
+{
+ int r;
+ WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMD sbcb_cmd;
+ WMI_SET_BTCOEX_FE_ANT_CMD sbfa_cmd;
+
+ /* Configure the type of BT collocated with WLAN */
+ memset(&sbcb_cmd, 0, sizeof(WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMD));
+ sbcb_cmd.btcoexCoLocatedBTdev = ATH6KL_BT_DEV;
+
+ r = wmi_set_btcoex_colocated_bt_dev_cmd(ar->arWmi, &sbcb_cmd);
+
+ if (r) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ ("Unable to set collocated BT type\n"));
+ return r;
+ }
+
+ /* Configure the type of BT collocated with WLAN */
+ memset(&sbfa_cmd, 0, sizeof(WMI_SET_BTCOEX_FE_ANT_CMD));
+
+ sbfa_cmd.btcoexFeAntType = ATH6KL_BT_ANTENNA;
+
+ r = wmi_set_btcoex_fe_ant_cmd(ar->arWmi, &sbfa_cmd);
+ if (r) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ ("Unable to set fornt end antenna configuration\n"));
+ return r;
+ }
+
+ return 0;
+}
+#else
+static int ath6kl_config_btcoex_params(struct ar6_softc *ar)
+{
+ return 0;
+}
+#endif /* CONFIG_ATH6KL_ENABLE_COEXISTENCE */
+
/*
* This function applies WLAN specific configuration defined in wlan_config.h
*/
int ar6000_target_config_wlan_params(struct ar6_softc *ar)
{
int status = 0;
-#if defined(INIT_MODE_DRV_ENABLED) && defined(ENABLE_COEXISTENCE)
- WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMD sbcb_cmd;
- WMI_SET_BTCOEX_FE_ANT_CMD sbfa_cmd;
-#endif /* INIT_MODE_DRV_ENABLED && ENABLE_COEXISTENCE */
#ifdef CONFIG_HOST_TCMD_SUPPORT
if (ar->arTargetMode != AR6000_WLAN_MODE) {
@@ -2449,39 +2411,9 @@
status = A_ERROR;
}
-#if defined(INIT_MODE_DRV_ENABLED) && defined(ENABLE_COEXISTENCE)
- /* Configure the type of BT collocated with WLAN */
- memset(&sbcb_cmd, 0, sizeof(WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMD));
-#ifdef CONFIG_AR600x_BT_QCOM
- sbcb_cmd.btcoexCoLocatedBTdev = 1;
-#elif defined(CONFIG_AR600x_BT_CSR)
- sbcb_cmd.btcoexCoLocatedBTdev = 2;
-#elif defined(CONFIG_AR600x_BT_AR3001)
- sbcb_cmd.btcoexCoLocatedBTdev = 3;
-#else
-#error Unsupported Bluetooth Type
-#endif /* Collocated Bluetooth Type */
-
- if ((wmi_set_btcoex_colocated_bt_dev_cmd(ar->arWmi, &sbcb_cmd)) != 0) {
- AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Unable to set collocated BT type\n"));
- status = A_ERROR;
- }
-
- /* Configure the type of BT collocated with WLAN */
- memset(&sbfa_cmd, 0, sizeof(WMI_SET_BTCOEX_FE_ANT_CMD));
-#ifdef CONFIG_AR600x_DUAL_ANTENNA
- sbfa_cmd.btcoexFeAntType = 2;
-#elif defined(CONFIG_AR600x_SINGLE_ANTENNA)
- sbfa_cmd.btcoexFeAntType = 1;
-#else
-#error Unsupported Front-End Antenna Configuration
-#endif /* AR600x Front-End Antenna Configuration */
-
- if ((wmi_set_btcoex_fe_ant_cmd(ar->arWmi, &sbfa_cmd)) != 0) {
- AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Unable to set fornt end antenna configuration\n"));
- status = A_ERROR;
- }
-#endif /* INIT_MODE_DRV_ENABLED && ENABLE_COEXISTENCE */
+ status = ath6kl_config_btcoex_params(ar);
+ if (status)
+ return status;
#if WLAN_CONFIG_IGNORE_POWER_SAVE_FAIL_EVENT_DURING_SCAN
if ((wmi_pmparams_cmd(ar->arWmi, 0, 1, 0, 0, 1, IGNORE_POWER_SAVE_FAIL_EVENT_DURING_SCAN)) != 0) {
@@ -2736,13 +2668,6 @@
status = ar6000_setup_hci(ar);
}
#endif
-#ifdef EXPORT_HCI_PAL_INTERFACE
- if (setuphcipal && (NULL != ar6kHciPalCallbacks_g.setupTransport))
- status = ar6kHciPalCallbacks_g.setupTransport(ar);
-#else
- if(setuphcipal)
- status = ar6k_setup_hci_pal(ar);
-#endif
} while (false);
@@ -2751,6 +2676,38 @@
goto ar6000_init_done;
}
+ if (regscanmode) {
+ u32 param;
+
+ if (BMIReadMemory(ar->arHifDevice,
+ HOST_INTEREST_ITEM_ADDRESS(ar,
+ hi_option_flag),
+ (u8 *)¶m,
+ 4) != 0) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ ("BMIReadMemory forsetting "
+ "regscanmode failed\n"));
+ return A_ERROR;
+ }
+
+ if (regscanmode == 1)
+ param |= HI_OPTION_SKIP_REG_SCAN;
+ else if (regscanmode == 2)
+ param |= HI_OPTION_INIT_REG_SCAN;
+
+ if (BMIWriteMemory(ar->arHifDevice,
+ HOST_INTEREST_ITEM_ADDRESS(ar,
+ hi_option_flag),
+ (u8 *)¶m,
+ 4) != 0) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
+ ("BMIWriteMemory forsetting "
+ "regscanmode failed\n"));
+ return A_ERROR;
+ }
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("Regulatory scan mode set\n"));
+ }
+
/*
* give our connected endpoints some buffers
*/
@@ -3095,7 +3052,6 @@
}
if (ar->arWmiEnabled) {
-#ifdef CONFIG_CHECKSUM_OFFLOAD
u8 csumStart=0;
u8 csumDest=0;
u8 csum=skb->ip_summed;
@@ -3104,7 +3060,6 @@
sizeof(ATH_LLC_SNAP_HDR));
csumDest=skb->csum_offset+csumStart;
}
-#endif
if (A_NETBUF_HEADROOM(skb) < dev->hard_header_len - LINUX_HACK_FUDGE_FACTOR) {
struct sk_buff *newbuf;
@@ -3135,7 +3090,6 @@
break;
}
}
-#ifdef CONFIG_CHECKSUM_OFFLOAD
if(csumOffload && (csum ==CHECKSUM_PARTIAL)){
WMI_TX_META_V2 metaV2;
metaV2.csumStart =csumStart;
@@ -3149,7 +3103,6 @@
}
else
-#endif
{
if (wmi_data_hdr_add(ar->arWmi, skb, DATA_MSGTYPE, bMoreData, dot11Hdr,0,NULL) != 0) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000_data_tx - wmi_data_hdr_add failed\n"));
@@ -3704,8 +3657,23 @@
WMI_DATA_HDR *dhdr = (WMI_DATA_HDR *)A_NETBUF_DATA(skb);
bool is_amsdu;
u8 tid;
- bool is_acl_data_frame;
- is_acl_data_frame = WMI_DATA_HDR_GET_DATA_TYPE(dhdr) == WMI_DATA_HDR_DATA_TYPE_ACL;
+
+ /*
+ * This check can be removed if after a while we do not
+ * see the warning. For now we leave it to ensure
+ * we drop these frames accordingly in case the
+ * target generates them for some reason. These
+ * were used for an internal PAL but that's not
+ * used or supported anymore. These frames should
+ * not come up from the target.
+ */
+ if (WARN_ON(WMI_DATA_HDR_GET_DATA_TYPE(dhdr) ==
+ WMI_DATA_HDR_DATA_TYPE_ACL)) {
+ AR6000_STAT_INC(ar, rx_errors);
+ A_NETBUF_FREE(skb);
+ return;
+ }
+
#ifdef CONFIG_PM
ar6000_check_wow_status(ar, NULL, false);
#endif /* CONFIG_PM */
@@ -3727,7 +3695,7 @@
* ACL data frames don't follow ethernet frame bounds for
* min length
*/
- if (ar->arNetworkType != AP_NETWORK && !is_acl_data_frame &&
+ if (ar->arNetworkType != AP_NETWORK &&
((pPacket->ActualLength < minHdrLen) ||
(pPacket->ActualLength > AR6000_MAX_RX_MESSAGE_SIZE)))
{
@@ -3767,11 +3735,9 @@
case WMI_META_VERSION_1:
offset += sizeof(WMI_RX_META_V1);
break;
-#ifdef CONFIG_CHECKSUM_OFFLOAD
case WMI_META_VERSION_2:
offset += sizeof(WMI_RX_META_V2);
break;
-#endif
default:
break;
}
@@ -3841,7 +3807,6 @@
A_NETBUF_PULL((void*)skb, sizeof(WMI_RX_META_V1));
break;
}
-#ifdef CONFIG_CHECKSUM_OFFLOAD
case WMI_META_VERSION_2:
{
WMI_RX_META_V2 *pMeta = (WMI_RX_META_V2 *)A_NETBUF_DATA(skb);
@@ -3852,7 +3817,6 @@
A_NETBUF_PULL((void*)skb, sizeof(WMI_RX_META_V2));
break;
}
-#endif
default:
break;
}
@@ -3862,7 +3826,7 @@
/* NWF: print the 802.11 hdr bytes */
if(containsDot11Hdr) {
status = wmi_dot11_hdr_remove(ar->arWmi,skb);
- } else if(!is_amsdu && !is_acl_data_frame) {
+ } else if(!is_amsdu) {
status = wmi_dot3_2_dix(skb);
}
@@ -3872,16 +3836,6 @@
goto rx_done;
}
- if (is_acl_data_frame) {
- A_NETBUF_PUSH(skb, sizeof(int));
- *((short *)A_NETBUF_DATA(skb)) = WMI_ACL_DATA_EVENTID;
- /* send the data packet to PAL driver */
- if(ar6k_pal_config_g.fpar6k_pal_recv_pkt) {
- if((*ar6k_pal_config_g.fpar6k_pal_recv_pkt)(ar->hcipal_info, skb) == true)
- goto rx_done;
- }
- }
-
if ((ar->arNetDev->flags & IFF_UP) == IFF_UP) {
if (ar->arNetworkType == AP_NETWORK) {
struct sk_buff *skb1 = NULL;
@@ -3915,9 +3869,7 @@
}
}
}
-#ifdef ATH_AR6K_11N_SUPPORT
aggr_process_recv_frm(ar->aggr_cntxt, tid, seq_no, is_amsdu, (void **)&skb);
-#endif
ar6000_deliver_frames_to_nw_stack((void *) ar->arNetDev, (void *)skb);
}
}
@@ -4146,93 +4098,6 @@
return &ar->arNetStats;
}
-static struct iw_statistics *
-ar6000_get_iwstats(struct net_device * dev)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
- TARGET_STATS *pStats = &ar->arTargetStats;
- struct iw_statistics * pIwStats = &ar->arIwStats;
- int rtnllocked;
-
- if (ar->bIsDestroyProgress || ar->arWmiReady == false || ar->arWlanState == WLAN_DISABLED)
- {
- pIwStats->status = 0;
- pIwStats->qual.qual = 0;
- pIwStats->qual.level =0;
- pIwStats->qual.noise = 0;
- pIwStats->discard.code =0;
- pIwStats->discard.retries=0;
- pIwStats->miss.beacon =0;
- return pIwStats;
- }
-
- /*
- * The in_atomic function is used to determine if the scheduling is
- * allowed in the current context or not. This was introduced in 2.6
- * From what I have read on the differences between 2.4 and 2.6, the
- * 2.4 kernel did not support preemption and so this check might not
- * be required for 2.4 kernels.
- */
- if (in_atomic())
- {
- wmi_get_stats_cmd(ar->arWmi);
-
- pIwStats->status = 1 ;
- pIwStats->qual.qual = pStats->cs_aveBeacon_rssi - 161;
- pIwStats->qual.level =pStats->cs_aveBeacon_rssi; /* noise is -95 dBm */
- pIwStats->qual.noise = pStats->noise_floor_calibation;
- pIwStats->discard.code = pStats->rx_decrypt_err;
- pIwStats->discard.retries = pStats->tx_retry_cnt;
- pIwStats->miss.beacon = pStats->cs_bmiss_cnt;
- return pIwStats;
- }
-
- dev_hold(dev);
- rtnllocked = rtnl_is_locked();
- if (rtnllocked) {
- rtnl_unlock();
- }
- pIwStats->status = 0;
-
- if (down_interruptible(&ar->arSem)) {
- goto err_exit;
- }
-
- do {
-
- if (ar->bIsDestroyProgress || ar->arWlanState == WLAN_DISABLED) {
- break;
- }
-
- ar->statsUpdatePending = true;
-
- if(wmi_get_stats_cmd(ar->arWmi) != 0) {
- break;
- }
-
- wait_event_interruptible_timeout(arEvent, ar->statsUpdatePending == false, wmitimeout * HZ);
- if (signal_pending(current)) {
- AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000 : WMI get stats timeout \n"));
- break;
- }
- pIwStats->status = 1 ;
- pIwStats->qual.qual = pStats->cs_aveBeacon_rssi - 161;
- pIwStats->qual.level =pStats->cs_aveBeacon_rssi; /* noise is -95 dBm */
- pIwStats->qual.noise = pStats->noise_floor_calibation;
- pIwStats->discard.code = pStats->rx_decrypt_err;
- pIwStats->discard.retries = pStats->tx_retry_cnt;
- pIwStats->miss.beacon = pStats->cs_bmiss_cnt;
- } while (0);
- up(&ar->arSem);
-
-err_exit:
- if (rtnllocked) {
- rtnl_lock();
- }
- dev_put(dev);
- return pIwStats;
-}
-
void
ar6000_ready_event(void *devt, u8 *datap, u8 phyCap, u32 sw_ver, u32 abi_ver)
{
@@ -4254,6 +4119,29 @@
wake_up(&arEvent);
}
+void ar6000_install_static_wep_keys(struct ar6_softc *ar)
+{
+ u8 index;
+ u8 keyUsage;
+
+ for (index = WMI_MIN_KEY_INDEX; index <= WMI_MAX_KEY_INDEX; index++) {
+ if (ar->arWepKeyList[index].arKeyLen) {
+ keyUsage = GROUP_USAGE;
+ if (index == ar->arDefTxKeyIndex) {
+ keyUsage |= TX_USAGE;
+ }
+ wmi_addKey_cmd(ar->arWmi,
+ index,
+ WEP_CRYPT,
+ keyUsage,
+ ar->arWepKeyList[index].arKeyLen,
+ NULL,
+ ar->arWepKeyList[index].arKey, KEY_OP_INIT_VAL, NULL,
+ NO_SYNC_WMIFLAG);
+ }
+ }
+}
+
void
add_new_sta(struct ar6_softc *ar, u8 *mac, u16 aid, u8 *wpaie,
u8 ielen, u8 keymgmt, u8 ucipher, u8 auth)
@@ -4344,7 +4232,7 @@
default:
A_PRINTF("AUTH: Unknown\n");
break;
- };
+ }
switch (listenInterval&0xFF) {
case WPA_PSK_AUTH:
A_PRINTF("KeyMgmt: WPA-PSK\n");
@@ -4355,7 +4243,7 @@
default:
A_PRINTF("KeyMgmt: NONE\n");
break;
- };
+ }
switch (beaconInterval) {
case AES_CRYPT:
A_PRINTF("Cipher: AES\n");
@@ -4374,7 +4262,7 @@
default:
A_PRINTF("Cipher: NONE\n");
break;
- };
+ }
add_new_sta(ar, bssid, channel /*aid*/,
assocInfo /* WPA IE */, assocRespLen /* IE len */,
@@ -4392,13 +4280,11 @@
return;
}
-#ifdef ATH6K_CONFIG_CFG80211
ar6k_cfg80211_connect_event(ar, channel, bssid,
listenInterval, beaconInterval,
networkType, beaconIeLen,
assocReqLen, assocRespLen,
assocInfo);
-#endif /* ATH6K_CONFIG_CFG80211 */
memcpy(ar->arBssid, bssid, sizeof(ar->arBssid));
ar->arBssChannel = channel;
@@ -4495,7 +4381,6 @@
wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf);
}
-#ifdef USER_KEYS
if (ar->user_savedkeys_stat == USER_SAVEDKEYS_STAT_RUN &&
ar->user_saved_keys.keyOk == true)
{
@@ -4508,30 +4393,9 @@
}
ar6000_reinstall_keys(ar, key_op_ctrl);
}
-#endif /* USER_KEYS */
netif_wake_queue(ar->arNetDev);
- /* For CFG80211 the key configuration and the default key comes in after connect so no point in plumbing invalid keys */
-#ifndef ATH6K_CONFIG_CFG80211
- if ((networkType & ADHOC_NETWORK) &&
- (OPEN_AUTH == ar->arDot11AuthMode) &&
- (NONE_AUTH == ar->arAuthMode) &&
- (WEP_CRYPT == ar->arPairwiseCrypto))
- {
- if (!ar->arConnected) {
- wmi_addKey_cmd(ar->arWmi,
- ar->arDefTxKeyIndex,
- WEP_CRYPT,
- GROUP_USAGE | TX_USAGE,
- ar->arWepKeyList[ar->arDefTxKeyIndex].arKeyLen,
- NULL,
- ar->arWepKeyList[ar->arDefTxKeyIndex].arKey, KEY_OP_INIT_VAL, NULL,
- NO_SYNC_WMIFLAG);
- }
- }
-#endif /* ATH6K_CONFIG_CFG80211 */
-
/* Update connect & link status atomically */
spin_lock_irqsave(&ar->arLock, flags);
ar->arConnected = true;
@@ -4661,11 +4525,9 @@
return;
}
-#ifdef ATH6K_CONFIG_CFG80211
ar6k_cfg80211_disconnect_event(ar, reason, bssid,
assocRespLen, assocInfo,
protocolReasonStatus);
-#endif /* ATH6K_CONFIG_CFG80211 */
/* Send disconnect event to supplicant */
A_MEMZERO(&wrqu, sizeof(wrqu));
@@ -4751,13 +4613,11 @@
reconnect_flag = 0;
}
-#ifdef USER_KEYS
if (reason != CSERV_DISCONNECT)
{
ar->user_savedkeys_stat = USER_SAVEDKEYS_STAT_INIT;
ar->user_key_ctrl = 0;
}
-#endif /* USER_KEYS */
netif_stop_queue(ar->arNetDev);
A_MEMZERO(ar->arBssid, sizeof(ar->arBssid));
@@ -4774,7 +4634,6 @@
ar->arRegCode = regCode;
}
-#ifdef ATH_AR6K_11N_SUPPORT
void
ar6000_aggr_rcv_addba_req_evt(struct ar6_softc *ar, WMI_ADDBA_REQ_EVENT *evt)
{
@@ -4796,7 +4655,6 @@
{
aggr_recv_delba_req_evt(ar->aggr_cntxt, evt->tid);
}
-#endif
void register_pal_cb(ar6k_pal_config_t *palConfig_p)
{
@@ -4828,12 +4686,6 @@
buf += sizeof(int);
memcpy(buf, cmd->buf, cmd->evt_buf_sz);
- if(ar6k_pal_config_g.fpar6k_pal_recv_pkt)
- {
- /* pass the cmd packet to PAL driver */
- if((*ar6k_pal_config_g.fpar6k_pal_recv_pkt)(ar->hcipal_info, osbuf) == true)
- return;
- }
ar6000_deliver_frames_to_nw_stack(ar->arNetDev, osbuf);
if(loghci) {
A_PRINTF_LOG("HCI Event From PAL <-- \n");
@@ -4883,7 +4735,7 @@
memcpy(pmkcand->bssid.sa_data, info->bssid, ATH_MAC_LEN);
wrqu.data.length = sizeof(struct iw_pmkid_cand);
wireless_send_event(ar->arNetDev, IWEVPMKIDCAND, &wrqu, (char *)pmkcand);
- A_FREE(pmkcand);
+ kfree(pmkcand);
#else /* WIRELESS_EXT >= 18 */
snprintf(buf, sizeof(buf), "%s%2.2x%2.2x%2.2x%2.2x%2.2x%2.2x%2.2x%2.2x",
tag,
@@ -4918,9 +4770,7 @@
tag, s->mac[0],s->mac[1],s->mac[2],s->mac[3],s->mac[4],s->mac[5]);
} else {
-#ifdef ATH6K_CONFIG_CFG80211
ar6k_cfg80211_tkip_micerr_event(ar, keyid, ismcast);
-#endif /* ATH6K_CONFIG_CFG80211 */
A_PRINTF("AR6000 TKIP MIC error received for keyid %d %scast\n",
keyid & 0x3, ismcast ? "multi": "uni");
@@ -4937,9 +4787,7 @@
ar6000_scanComplete_event(struct ar6_softc *ar, int status)
{
-#ifdef ATH6K_CONFIG_CFG80211
ar6k_cfg80211_scanComplete_event(ar, status);
-#endif /* ATH6K_CONFIG_CFG80211 */
if (!ar->arUserBssFilter) {
wmi_bssfilter_cmd(ar->arWmi, NONE_BSS_FILTER, 0);
@@ -5097,19 +4945,13 @@
userRssiThold.rssi = rssi;
A_PRINTF("rssi Threshold range = %d tag = %d rssi = %d\n", newThreshold,
userRssiThold.tag, userRssiThold.rssi);
-
- ar6000_send_event_to_app(ar, WMI_RSSI_THRESHOLD_EVENTID,(u8 *)&userRssiThold, sizeof(USER_RSSI_THOLD));
}
void
ar6000_hbChallengeResp_event(struct ar6_softc *ar, u32 cookie, u32 source)
{
- if (source == APP_HB_CHALLENGE) {
- /* Report it to the app in case it wants a positive acknowledgement */
- ar6000_send_event_to_app(ar, WMIX_HB_CHALLENGE_RESP_EVENTID,
- (u8 *)&cookie, sizeof(cookie));
- } else {
+ if (source != APP_HB_CHALLENGE) {
/* This would ignore the replys that come in after their due time */
if (cookie == ar->arHBChallengeResp.seqNum) {
ar->arHBChallengeResp.outstanding = false;
@@ -5562,100 +5404,6 @@
return cookie;
}
-#ifdef SEND_EVENT_TO_APP
-/*
- * This function is used to send event which come from taget to
- * the application. The buf which send to application is include
- * the event ID and event content.
- */
-#define EVENT_ID_LEN 2
-void ar6000_send_event_to_app(struct ar6_softc *ar, u16 eventId,
- u8 *datap, int len)
-{
-
-#if (WIRELESS_EXT >= 15)
-
-/* note: IWEVCUSTOM only exists in wireless extensions after version 15 */
-
- char *buf;
- u16 size;
- union iwreq_data wrqu;
-
- size = len + EVENT_ID_LEN;
-
- if (size > IW_CUSTOM_MAX) {
- AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("WMI event ID : 0x%4.4X, len = %d too big for IWEVCUSTOM (max=%d) \n",
- eventId, size, IW_CUSTOM_MAX));
- return;
- }
-
- buf = A_MALLOC_NOWAIT(size);
- if (NULL == buf){
- AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s: failed to allocate %d bytes\n", __func__, size));
- return;
- }
-
- A_MEMZERO(buf, size);
- memcpy(buf, &eventId, EVENT_ID_LEN);
- memcpy(buf+EVENT_ID_LEN, datap, len);
-
- //AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("event ID = %d,len = %d\n",*(u16 *)buf, size));
- A_MEMZERO(&wrqu, sizeof(wrqu));
- wrqu.data.length = size;
- wireless_send_event(ar->arNetDev, IWEVCUSTOM, &wrqu, buf);
- A_FREE(buf);
-#endif
-
-
-}
-
-/*
- * This function is used to send events larger than 256 bytes
- * to the application. The buf which is sent to application
- * includes the event ID and event content.
- */
-void ar6000_send_generic_event_to_app(struct ar6_softc *ar, u16 eventId,
- u8 *datap, int len)
-{
-
-#if (WIRELESS_EXT >= 18)
-
-/* IWEVGENIE exists in wireless extensions version 18 onwards */
-
- char *buf;
- u16 size;
- union iwreq_data wrqu;
-
- size = len + EVENT_ID_LEN;
-
- if (size > IW_GENERIC_IE_MAX) {
- AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("WMI event ID : 0x%4.4X, len = %d too big for IWEVGENIE (max=%d) \n",
- eventId, size, IW_GENERIC_IE_MAX));
- return;
- }
-
- buf = A_MALLOC_NOWAIT(size);
- if (NULL == buf){
- AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("%s: failed to allocate %d bytes\n", __func__, size));
- return;
- }
-
- A_MEMZERO(buf, size);
- memcpy(buf, &eventId, EVENT_ID_LEN);
- memcpy(buf+EVENT_ID_LEN, datap, len);
-
- A_MEMZERO(&wrqu, sizeof(wrqu));
- wrqu.data.length = size;
- wireless_send_event(ar->arNetDev, IWEVGENIE, &wrqu, buf);
-
- A_FREE(buf);
-
-#endif /* (WIRELESS_EXT >= 18) */
-
-}
-#endif /* SEND_EVENT_TO_APP */
-
-
void
ar6000_tx_retry_err_event(void *devt)
{
@@ -5666,13 +5414,9 @@
ar6000_snrThresholdEvent_rx(void *devt, WMI_SNR_THRESHOLD_VAL newThreshold, u8 snr)
{
WMI_SNR_THRESHOLD_EVENT event;
- struct ar6_softc *ar = (struct ar6_softc *)devt;
event.range = newThreshold;
event.snr = snr;
-
- ar6000_send_event_to_app(ar, WMI_SNR_THRESHOLD_EVENTID, (u8 *)&event,
- sizeof(WMI_SNR_THRESHOLD_EVENT));
}
void
@@ -5999,9 +5743,7 @@
}
#endif
-#ifdef USER_KEYS
static int
-
ar6000_reinstall_keys(struct ar6_softc *ar, u8 key_op_ctrl)
{
int status = 0;
@@ -6046,7 +5788,6 @@
return status;
}
-#endif /* USER_KEYS */
void
diff --git a/drivers/staging/ath6kl/os/linux/ar6000_pm.c b/drivers/staging/ath6kl/os/linux/ar6000_pm.c
index 1a90424..1e0ace8 100644
--- a/drivers/staging/ath6kl/os/linux/ar6000_pm.c
+++ b/drivers/staging/ath6kl/os/linux/ar6000_pm.c
@@ -36,9 +36,6 @@
extern unsigned int wmitimeout;
extern wait_queue_head_t arEvent;
-#ifdef ANDROID_ENV
-extern void android_ar6k_check_wow_status(struct ar6_softc *ar, struct sk_buff *skb, bool isEvent);
-#endif
#undef ATH_MODULE_NAME
#define ATH_MODULE_NAME pm
#define ATH_DEBUG_PM ATH_DEBUG_MAKE_MODULE_MASK(0)
@@ -283,10 +280,6 @@
/* Wow resume from irq interrupt */
AR_DEBUG_PRINTF(ATH_DEBUG_PM, ("%s: WoW resume from irq thread status %d\n", __func__, ar->arWlanPowerState));
ar6000_wow_resume(ar);
- } else {
-#ifdef ANDROID_ENV
- android_ar6k_check_wow_status(ar, skb, isEvent);
-#endif
}
}
@@ -309,37 +302,6 @@
return status;
}
-static int ar6000_pm_probe(struct platform_device *pdev)
-{
- plat_setup_power(1,1);
- return 0;
-}
-
-static int ar6000_pm_remove(struct platform_device *pdev)
-{
- plat_setup_power(0,1);
- return 0;
-}
-
-static int ar6000_pm_suspend(struct platform_device *pdev, pm_message_t state)
-{
- return 0;
-}
-
-static int ar6000_pm_resume(struct platform_device *pdev)
-{
- return 0;
-}
-
-static struct platform_driver ar6000_pm_device = {
- .probe = ar6000_pm_probe,
- .remove = ar6000_pm_remove,
- .suspend = ar6000_pm_suspend,
- .resume = ar6000_pm_resume,
- .driver = {
- .name = "wlan_ar6000_pm",
- },
-};
#endif /* CONFIG_PM */
int
@@ -359,8 +321,6 @@
break;
}
- plat_setup_power(1,0);
-
/* Change the state to ON */
ar->arWlanPowerState = WLAN_POWER_STATE_ON;
@@ -373,17 +333,6 @@
sizeof(HIF_DEVICE_POWER_CHANGE_TYPE));
if (status == A_PENDING) {
-#ifdef ANDROID_ENV
- /* Wait for WMI ready event */
- u32 timeleft = wait_event_interruptible_timeout(arEvent,
- (ar->arWmiReady == true), wmitimeout * HZ);
- if (!timeleft || signal_pending(current)) {
- AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000 : Failed to get wmi ready \n"));
- status = A_ERROR;
- break;
- }
-#endif
- status = 0;
} else if (status == 0) {
ar6000_restart_endpoint(ar->arNetDev);
status = 0;
@@ -403,8 +352,6 @@
&config,
sizeof(HIF_DEVICE_POWER_CHANGE_TYPE));
- plat_setup_power(0,0);
-
ar->arWlanPowerState = WLAN_POWER_STATE_CUT_PWR;
}
} while (0);
@@ -642,8 +589,6 @@
}
if (pSleepEvent) {
AR_DEBUG_PRINTF(ATH_DEBUG_PM, ("SENT WLAN Sleep Event %d\n", wmiSleepEvent.sleepState));
- ar6000_send_event_to_app(ar, WMI_REPORT_SLEEP_STATE_EVENTID, (u8 *)pSleepEvent,
- sizeof(WMI_REPORT_SLEEP_STATE_EVENTID));
}
}
up(&ar->arSem);
@@ -679,25 +624,3 @@
status = ar6000_update_wlan_pwr_state(ar, state, false);
return status;
}
-
-void ar6000_pm_init()
-{
- A_REGISTER_MODULE_DEBUG_INFO(pm);
-#ifdef CONFIG_PM
- /*
- * Register ar6000_pm_device into system.
- * We should also add platform_device into the first item of array
- * of devices[] in file arch/xxx/mach-xxx/board-xxxx.c
- */
- if (platform_driver_register(&ar6000_pm_device)) {
- AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("ar6000: fail to register the power control driver.\n"));
- }
-#endif /* CONFIG_PM */
-}
-
-void ar6000_pm_exit()
-{
-#ifdef CONFIG_PM
- platform_driver_unregister(&ar6000_pm_device);
-#endif /* CONFIG_PM */
-}
diff --git a/drivers/staging/ath6kl/os/linux/ar6k_pal.c b/drivers/staging/ath6kl/os/linux/ar6k_pal.c
deleted file mode 100644
index 1f7179a..0000000
--- a/drivers/staging/ath6kl/os/linux/ar6k_pal.c
+++ /dev/null
@@ -1,479 +0,0 @@
-//------------------------------------------------------------------------------
-// Copyright (c) 2004-2010 Atheros Communications Inc.
-// All rights reserved.
-//
-//
-//
-// Permission to use, copy, modify, and/or distribute this software for any
-// purpose with or without fee is hereby granted, provided that the above
-// copyright notice and this permission notice appear in all copies.
-//
-// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-//
-//
-//
-// Author(s): ="Atheros"
-//------------------------------------------------------------------------------
-
-#include "ar6000_drv.h"
-#ifdef AR6K_ENABLE_HCI_PAL
-#include <net/bluetooth/bluetooth.h>
-#include <net/bluetooth/hci_core.h>
-#include <ar6k_pal.h>
-
-extern unsigned int setupbtdev;
-#define bt_check_bit(val, bit) (val & bit)
-#define bt_set_bit(val, bit) (val |= bit)
-#define bt_clear_bit(val, bit) (val &= ~bit)
-
-/* export ATH_AR6K_DEBUG_HCI_PAL=yes in host/localmake.linux.inc
- * to enable debug information */
-#ifdef HCIPAL_DEBUG
-#define PRIN_LOG(format, args...) printk(KERN_ALERT "%s:%d - %s Msg:" format "\n",__FUNCTION__, __LINE__, __FILE__, ## args)
-#else
-#define PRIN_LOG(format, args...)
-#endif
-
-/**********************************
- * HCI PAL private info structure
- *********************************/
-typedef struct ar6k_hci_pal_info_s{
-
- unsigned long ulFlags;
-#define HCI_NORMAL_MODE (1)
-#define HCI_REGISTERED (1<<1)
- struct hci_dev *hdev; /* BT Stack HCI dev */
- struct ar6_softc *ar;
-
-}ar6k_hci_pal_info_t;
-
-/*** BT Stack Entrypoints *******/
-/***************************************
- * bt_open - open a handle to the device
- ***************************************/
-static int bt_open(struct hci_dev *hdev)
-{
- PRIN_LOG("HCI PAL: bt_open - enter - x\n");
- set_bit(HCI_RUNNING, &hdev->flags);
- set_bit(HCI_UP, &hdev->flags);
- set_bit(HCI_INIT, &hdev->flags);
- return 0;
-}
-
-/***************************************
- * bt_close - close handle to the device
- ***************************************/
-static int bt_close(struct hci_dev *hdev)
-{
- PRIN_LOG("HCI PAL: bt_close - enter\n");
- clear_bit(HCI_RUNNING, &hdev->flags);
- return 0;
-}
-
-/*****************************
- * bt_ioctl - ioctl processing
- *****************************/
-static int bt_ioctl(struct hci_dev *hdev, unsigned int cmd, unsigned long arg)
-{
- PRIN_LOG("HCI PAL: bt_ioctl - enter\n");
- return -ENOIOCTLCMD;
-}
-
-/**************************************
- * bt_flush - flush outstanding packets
- **************************************/
-static int bt_flush(struct hci_dev *hdev)
-{
- PRIN_LOG("HCI PAL: bt_flush - enter\n");
- return 0;
-}
-
-/***************
- * bt_destruct
- ***************/
-static void bt_destruct(struct hci_dev *hdev)
-{
- PRIN_LOG("HCI PAL: bt_destruct - enter\n");
- /* nothing to do here */
-}
-
-/****************************************************
- * Invoked from bluetooth stack via hdev->send()
- * to send the packet out via ar6k to PAL firmware.
- *
- * For HCI command packet wmi_send_hci_cmd() is invoked.
- * wmi_send_hci_cmd adds WMI_CMD_HDR and sends the packet
- * to PAL firmware.
- *
- * For HCI ACL data packet wmi_data_hdr_add is invoked
- * to add WMI_DATA_HDR to the packet. ar6000_acl_data_tx
- * is then invoked to send the packet to PAL firmware.
- ******************************************************/
-static int btpal_send_frame(struct sk_buff *skb)
-{
- struct hci_dev *hdev = (struct hci_dev *)skb->dev;
- HCI_TRANSPORT_PACKET_TYPE type;
- ar6k_hci_pal_info_t *pHciPalInfo;
- int status = 0;
- struct sk_buff *txSkb = NULL;
- struct ar6_softc *ar;
-
- if (!hdev) {
- PRIN_LOG("HCI PAL: btpal_send_frame - no device\n");
- return -ENODEV;
- }
-
- if (!test_bit(HCI_RUNNING, &hdev->flags)) {
- PRIN_LOG("HCI PAL: btpal_send_frame - not open\n");
- return -EBUSY;
- }
-
- pHciPalInfo = (ar6k_hci_pal_info_t *)hdev->driver_data;
- A_ASSERT(pHciPalInfo != NULL);
- ar = pHciPalInfo->ar;
-
- PRIN_LOG("+btpal_send_frame type: %d \n",bt_cb(skb)->pkt_type);
- type = HCI_COMMAND_TYPE;
-
- switch (bt_cb(skb)->pkt_type) {
- case HCI_COMMAND_PKT:
- type = HCI_COMMAND_TYPE;
- hdev->stat.cmd_tx++;
- break;
-
- case HCI_ACLDATA_PKT:
- type = HCI_ACL_TYPE;
- hdev->stat.acl_tx++;
- break;
-
- case HCI_SCODATA_PKT:
- /* we don't support SCO over the pal */
- kfree_skb(skb);
- return 0;
- default:
- A_ASSERT(false);
- kfree_skb(skb);
- return 0;
- }
-
- if (AR_DEBUG_LVL_CHECK(ATH_DEBUG_HCI_DUMP)) {
- A_PRINTF(">>> Send HCI %s packet len: %d\n",
- (type == HCI_COMMAND_TYPE) ? "COMMAND" : "ACL",
- skb->len);
- if (type == HCI_COMMAND_TYPE) {
- PRIN_LOG(" HCI Command: OGF:0x%X OCF:0x%X \r\n",
- HCI_GET_OP_CODE(skb-data) >> 10, HCI_GET_OP_CODE(skb-data) & 0x3FF);
- }
- AR_DEBUG_PRINTBUF(skb->data,skb->len,"BT HCI SEND Packet Dump");
- }
-
- do {
- if(type == HCI_COMMAND_TYPE)
- {
- PRIN_LOG("HCI command");
-
- if (ar->arWmiReady == false)
- {
- PRIN_LOG("WMI not ready ");
- break;
- }
-
- if (wmi_send_hci_cmd(ar->arWmi, skb->data, skb->len) != 0)
- {
- PRIN_LOG("send hci cmd error");
- break;
- }
- }
- else if(type == HCI_ACL_TYPE)
- {
- void *osbuf;
-
- PRIN_LOG("ACL data");
- if (ar->arWmiReady == false)
- {
- PRIN_LOG("WMI not ready");
- break;
- }
-
- /* need to add WMI header so allocate a skb with more space */
- txSkb = bt_skb_alloc(TX_PACKET_RSV_OFFSET + WMI_MAX_TX_META_SZ +
- sizeof(WMI_DATA_HDR) + skb->len,
- GFP_ATOMIC);
-
- if (txSkb == NULL) {
- status = A_NO_MEMORY;
- PRIN_LOG("No memory");
- break;
- }
-
- bt_cb(txSkb)->pkt_type = bt_cb(skb)->pkt_type;
- txSkb->dev = (void *)pHciPalInfo->hdev;
- skb_reserve(txSkb, TX_PACKET_RSV_OFFSET + WMI_MAX_TX_META_SZ + sizeof(WMI_DATA_HDR));
- memcpy(txSkb->data, skb->data, skb->len);
- skb_put(txSkb,skb->len);
- /* Add WMI packet type */
- osbuf = (void *)txSkb;
-
- if (wmi_data_hdr_add(ar->arWmi, osbuf, DATA_MSGTYPE, 0, WMI_DATA_HDR_DATA_TYPE_ACL,0,NULL) != 0) {
- PRIN_LOG("XIOCTL_ACL_DATA - wmi_data_hdr_add failed\n");
- } else {
- /* Send data buffer over HTC */
- PRIN_LOG("acl data tx");
- ar6000_acl_data_tx(osbuf, ar->arNetDev);
- }
- txSkb = NULL;
- }
- } while (false);
-
- if (txSkb != NULL) {
- PRIN_LOG("Free skb");
- kfree_skb(txSkb);
- }
- kfree_skb(skb);
- return 0;
-}
-
-
-/***********************************************
- * Unregister HCI device and free HCI device info
- ***********************************************/
-static void bt_cleanup_hci_pal(ar6k_hci_pal_info_t *pHciPalInfo)
-{
- int err;
-
- if (bt_check_bit(pHciPalInfo->ulFlags, HCI_REGISTERED)) {
- bt_clear_bit(pHciPalInfo->ulFlags, HCI_REGISTERED);
- clear_bit(HCI_RUNNING, &pHciPalInfo->hdev->flags);
- clear_bit(HCI_UP, &pHciPalInfo->hdev->flags);
- clear_bit(HCI_INIT, &pHciPalInfo->hdev->flags);
- A_ASSERT(pHciPalInfo->hdev != NULL);
- /* unregister */
- PRIN_LOG("Unregister PAL device");
- if ((err = hci_unregister_dev(pHciPalInfo->hdev)) < 0) {
- PRIN_LOG("HCI PAL: failed to unregister with bluetooth %d\n",err);
- }
- }
-
- kfree(pHciPalInfo->hdev);
- pHciPalInfo->hdev = NULL;
-}
-
-/*********************************************************
- * Allocate HCI device and store in PAL private info structure.
- *********************************************************/
-static int bt_setup_hci_pal(ar6k_hci_pal_info_t *pHciPalInfo)
-{
- int status = 0;
- struct hci_dev *pHciDev = NULL;
-
- if (!setupbtdev) {
- return 0;
- }
-
- do {
- /* allocate a BT HCI struct for this device */
- pHciDev = hci_alloc_dev();
- if (NULL == pHciDev) {
- PRIN_LOG("HCI PAL driver - failed to allocate BT HCI struct \n");
- status = A_NO_MEMORY;
- break;
- }
-
- /* save the device, we'll register this later */
- pHciPalInfo->hdev = pHciDev;
- SET_HCI_BUS_TYPE(pHciDev, HCI_VIRTUAL, HCI_80211);
- pHciDev->driver_data = pHciPalInfo;
- pHciDev->open = bt_open;
- pHciDev->close = bt_close;
- pHciDev->send = btpal_send_frame;
- pHciDev->ioctl = bt_ioctl;
- pHciDev->flush = bt_flush;
- pHciDev->destruct = bt_destruct;
- pHciDev->owner = THIS_MODULE;
- /* driver is running in normal BT mode */
- PRIN_LOG("Normal mode enabled");
- bt_set_bit(pHciPalInfo->ulFlags, HCI_NORMAL_MODE);
-
- } while (false);
-
- if (status) {
- bt_cleanup_hci_pal(pHciPalInfo);
- }
- return status;
-}
-
-/**********************************************
- * Cleanup HCI device and free HCI PAL private info
- *********************************************/
-void ar6k_cleanup_hci_pal(void *ar_p)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar_p;
- ar6k_hci_pal_info_t *pHciPalInfo = (ar6k_hci_pal_info_t *)ar->hcipal_info;
-
- if (pHciPalInfo != NULL) {
- bt_cleanup_hci_pal(pHciPalInfo);
- A_FREE(pHciPalInfo);
- ar->hcipal_info = NULL;
- }
-}
-
-/****************************
- * Register HCI device
- ****************************/
-static bool ar6k_pal_transport_ready(void *pHciPal)
-{
- ar6k_hci_pal_info_t *pHciPalInfo = (ar6k_hci_pal_info_t *)pHciPal;
-
- PRIN_LOG("HCI device transport ready");
- if(pHciPalInfo == NULL)
- return false;
-
- if (hci_register_dev(pHciPalInfo->hdev) < 0) {
- PRIN_LOG("Can't register HCI device");
- hci_free_dev(pHciPalInfo->hdev);
- return false;
- }
- PRIN_LOG("HCI device registered");
- pHciPalInfo->ulFlags |= HCI_REGISTERED;
- return true;
-}
-
-/**************************************************
- * Called from ar6k driver when command or ACL data
- * packet is received. Pass the packet to bluetooth
- * stack via hci_recv_frame.
- **************************************************/
-bool ar6k_pal_recv_pkt(void *pHciPal, void *osbuf)
-{
- struct sk_buff *skb = (struct sk_buff *)osbuf;
- ar6k_hci_pal_info_t *pHciPalInfo;
- bool success = false;
- u8 btType = 0;
- pHciPalInfo = (ar6k_hci_pal_info_t *)pHciPal;
-
- do {
-
- /* if normal mode is not enabled pass on to the stack
- * by returning failure */
- if(!(pHciPalInfo->ulFlags & HCI_NORMAL_MODE))
- {
- PRIN_LOG("Normal mode not enabled");
- break;
- }
-
- if (!test_bit(HCI_RUNNING, &pHciPalInfo->hdev->flags)) {
- PRIN_LOG("HCI PAL: HCI - not running\n");
- break;
- }
-
- if(*((short *)A_NETBUF_DATA(skb)) == WMI_ACL_DATA_EVENTID)
- btType = HCI_ACLDATA_PKT;
- else
- btType = HCI_EVENT_PKT;
- /* pull 4 bytes which contains WMI packet type */
- A_NETBUF_PULL(skb, sizeof(int));
- bt_cb(skb)->pkt_type = btType;
- skb->dev = (void *)pHciPalInfo->hdev;
-
- /* pass the received event packet up the stack */
- if (hci_recv_frame(skb) != 0) {
- PRIN_LOG("HCI PAL: hci_recv_frame failed \n");
- break;
- } else {
- PRIN_LOG("HCI PAL: Indicated RCV of type:%d, Length:%d \n",HCI_EVENT_PKT, skb->len);
- }
- PRIN_LOG("hci recv success");
- success = true;
- }while(false);
- return success;
-}
-
-/**********************************************************
- * HCI PAL init function called from ar6k when it is loaded..
- * Allocates PAL private info, stores the same in ar6k private info.
- * Registers a HCI device.
- * Registers packet receive callback function with ar6k
- **********************************************************/
-int ar6k_setup_hci_pal(void *ar_p)
-{
- int status = 0;
- ar6k_hci_pal_info_t *pHciPalInfo;
- ar6k_pal_config_t ar6k_pal_config;
- struct ar6_softc *ar = (struct ar6_softc *)ar_p;
-
- do {
-
- pHciPalInfo = (ar6k_hci_pal_info_t *)A_MALLOC(sizeof(ar6k_hci_pal_info_t));
-
- if (NULL == pHciPalInfo) {
- status = A_NO_MEMORY;
- break;
- }
-
- A_MEMZERO(pHciPalInfo, sizeof(ar6k_hci_pal_info_t));
- ar->hcipal_info = pHciPalInfo;
- pHciPalInfo->ar = ar;
-
- status = bt_setup_hci_pal(pHciPalInfo);
- if (status) {
- break;
- }
-
- if(bt_check_bit(pHciPalInfo->ulFlags, HCI_NORMAL_MODE))
- PRIN_LOG("HCI PAL: running in normal mode... \n");
- else
- PRIN_LOG("HCI PAL: running in test mode... \n");
-
- ar6k_pal_config.fpar6k_pal_recv_pkt = ar6k_pal_recv_pkt;
- register_pal_cb(&ar6k_pal_config);
- ar6k_pal_transport_ready(ar->hcipal_info);
- } while (false);
-
- if (status) {
- ar6k_cleanup_hci_pal(ar);
- }
- return status;
-}
-#else /* AR6K_ENABLE_HCI_PAL */
-int ar6k_setup_hci_pal(void *ar_p)
-{
- return 0;
-}
-void ar6k_cleanup_hci_pal(void *ar_p)
-{
-}
-#endif /* AR6K_ENABLE_HCI_PAL */
-
-#ifdef EXPORT_HCI_PAL_INTERFACE
-/*****************************************************
- * Register init and callback function with ar6k
- * when PAL driver is a separate kernel module.
- ****************************************************/
-int ar6k_register_hci_pal(struct hci_transport_callbacks *hciTransCallbacks);
-static int __init pal_init_module(void)
-{
- struct hci_transport_callbacks hciTransCallbacks;
-
- hciTransCallbacks.setupTransport = ar6k_setup_hci_pal;
- hciTransCallbacks.cleanupTransport = ar6k_cleanup_hci_pal;
-
- if(ar6k_register_hci_pal(&hciTransCallbacks) != 0)
- return -ENODEV;
-
- return 0;
-}
-
-static void __exit pal_cleanup_module(void)
-{
-}
-
-module_init(pal_init_module);
-module_exit(pal_cleanup_module);
-MODULE_LICENSE("Dual BSD/GPL");
-#endif
diff --git a/drivers/staging/ath6kl/os/linux/cfg80211.c b/drivers/staging/ath6kl/os/linux/cfg80211.c
index 5bda24e..77dfb40 100644
--- a/drivers/staging/ath6kl/os/linux/cfg80211.c
+++ b/drivers/staging/ath6kl/os/linux/cfg80211.c
@@ -172,6 +172,12 @@
case NL80211_AUTHTYPE_NETWORK_EAP:
ar->arDot11AuthMode = LEAP_AUTH;
break;
+
+ case NL80211_AUTHTYPE_AUTOMATIC:
+ ar->arDot11AuthMode = OPEN_AUTH;
+ ar->arAutoAuthStage = AUTH_OPEN_IN_PROGRESS;
+ break;
+
default:
ar->arDot11AuthMode = OPEN_AUTH;
AR_DEBUG_PRINTF(ATH_DEBUG_INFO,
@@ -460,6 +466,8 @@
assocReqLen -= assocReqIeOffset;
assocRespLen -= assocRespIeOffset;
+ ar->arAutoAuthStage = AUTH_IDLE;
+
if((ADHOC_NETWORK & networkType)) {
if(NL80211_IFTYPE_ADHOC != ar->wdev->iftype) {
AR_DEBUG_PRINTF(ATH_DEBUG_INFO,
@@ -487,75 +495,84 @@
((ADHOC_NETWORK & networkType) ? WLAN_CAPABILITY_IBSS : WLAN_CAPABILITY_ESS),
((ADHOC_NETWORK & networkType) ? WLAN_CAPABILITY_IBSS : WLAN_CAPABILITY_ESS));
- if(!bss) {
- if (ADHOC_NETWORK & networkType) {
+ /*
+ * Earlier we were updating the cfg about bss by making a beacon frame
+ * only if the entry for bss is not there. This can have some issue if
+ * ROAM event is generated and a heavy traffic is ongoing. The ROAM
+ * event is handled through a work queue and by the time it really gets
+ * handled, BSS would have been aged out. So it is better to update the
+ * cfg about BSS irrespective of its entry being present right now or
+ * not.
+ */
+
+ if (ADHOC_NETWORK & networkType) {
/* construct 802.11 mgmt beacon */
if(ptr_ie_buf) {
- *ptr_ie_buf++ = WLAN_EID_SSID;
- *ptr_ie_buf++ = ar->arSsidLen;
- memcpy(ptr_ie_buf, ar->arSsid, ar->arSsidLen);
- ptr_ie_buf +=ar->arSsidLen;
+ *ptr_ie_buf++ = WLAN_EID_SSID;
+ *ptr_ie_buf++ = ar->arSsidLen;
+ memcpy(ptr_ie_buf, ar->arSsid, ar->arSsidLen);
+ ptr_ie_buf +=ar->arSsidLen;
- *ptr_ie_buf++ = WLAN_EID_IBSS_PARAMS;
- *ptr_ie_buf++ = 2; /* length */
- *ptr_ie_buf++ = 0; /* ATIM window */
- *ptr_ie_buf++ = 0; /* ATIM window */
+ *ptr_ie_buf++ = WLAN_EID_IBSS_PARAMS;
+ *ptr_ie_buf++ = 2; /* length */
+ *ptr_ie_buf++ = 0; /* ATIM window */
+ *ptr_ie_buf++ = 0; /* ATIM window */
- /* TODO: update ibss params and include supported rates,
- * DS param set, extened support rates, wmm. */
+ /* TODO: update ibss params and include supported rates,
+ * DS param set, extened support rates, wmm. */
- ie_buf_len = ptr_ie_buf - ie_buf;
+ ie_buf_len = ptr_ie_buf - ie_buf;
}
capability |= IEEE80211_CAPINFO_IBSS;
if(WEP_CRYPT == ar->arPairwiseCrypto) {
- capability |= IEEE80211_CAPINFO_PRIVACY;
+ capability |= IEEE80211_CAPINFO_PRIVACY;
}
memcpy(source_mac, ar->arNetDev->dev_addr, ATH_MAC_LEN);
ptr_ie_buf = ie_buf;
- } else {
+ } else {
capability = *(u16 *)(&assocInfo[beaconIeLen]);
memcpy(source_mac, bssid, ATH_MAC_LEN);
ptr_ie_buf = assocReqIe;
ie_buf_len = assocReqLen;
- }
+ }
- size = offsetof(struct ieee80211_mgmt, u)
- + sizeof(mgmt->u.beacon)
- + ie_buf_len;
+ size = offsetof(struct ieee80211_mgmt, u)
+ + sizeof(mgmt->u.beacon)
+ + ie_buf_len;
- ieeemgmtbuf = A_MALLOC_NOWAIT(size);
- if(!ieeemgmtbuf) {
+ ieeemgmtbuf = A_MALLOC_NOWAIT(size);
+ if(!ieeemgmtbuf) {
AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
("%s: ieeeMgmtbuf alloc error\n", __func__));
+ cfg80211_put_bss(bss);
return;
- }
-
- A_MEMZERO(ieeemgmtbuf, size);
- mgmt = (struct ieee80211_mgmt *)ieeemgmtbuf;
- mgmt->frame_control = (IEEE80211_FTYPE_MGMT | IEEE80211_STYPE_BEACON);
- memcpy(mgmt->da, bcast_mac, ATH_MAC_LEN);
- memcpy(mgmt->sa, source_mac, ATH_MAC_LEN);
- memcpy(mgmt->bssid, bssid, ATH_MAC_LEN);
- mgmt->u.beacon.beacon_int = beaconInterval;
- mgmt->u.beacon.capab_info = capability;
- memcpy(mgmt->u.beacon.variable, ptr_ie_buf, ie_buf_len);
-
- ibss_channel = ieee80211_get_channel(ar->wdev->wiphy, (int)channel);
-
- AR_DEBUG_PRINTF(ATH_DEBUG_INFO,
- ("%s: inform bss with bssid %pM channel %d beaconInterval %d "
- "capability 0x%x\n", __func__, mgmt->bssid,
- ibss_channel->hw_value, beaconInterval, capability));
-
- bss = cfg80211_inform_bss_frame(ar->wdev->wiphy,
- ibss_channel, mgmt,
- le16_to_cpu(size),
- signal, GFP_KERNEL);
- A_FREE(ieeemgmtbuf);
- cfg80211_put_bss(bss);
}
+ A_MEMZERO(ieeemgmtbuf, size);
+ mgmt = (struct ieee80211_mgmt *)ieeemgmtbuf;
+ mgmt->frame_control = (IEEE80211_FTYPE_MGMT | IEEE80211_STYPE_BEACON);
+ memcpy(mgmt->da, bcast_mac, ATH_MAC_LEN);
+ memcpy(mgmt->sa, source_mac, ATH_MAC_LEN);
+ memcpy(mgmt->bssid, bssid, ATH_MAC_LEN);
+ mgmt->u.beacon.beacon_int = beaconInterval;
+ mgmt->u.beacon.capab_info = capability;
+ memcpy(mgmt->u.beacon.variable, ptr_ie_buf, ie_buf_len);
+
+ ibss_channel = ieee80211_get_channel(ar->wdev->wiphy, (int)channel);
+
+ AR_DEBUG_PRINTF(ATH_DEBUG_INFO,
+ ("%s: inform bss with bssid %pM channel %d beaconInterval %d "
+ "capability 0x%x\n", __func__, mgmt->bssid,
+ ibss_channel->hw_value, beaconInterval, capability));
+
+ bss = cfg80211_inform_bss_frame(ar->wdev->wiphy,
+ ibss_channel, mgmt,
+ le16_to_cpu(size),
+ signal, GFP_KERNEL);
+ kfree(ieeemgmtbuf);
+ cfg80211_put_bss(bss);
+
if((ADHOC_NETWORK & networkType)) {
cfg80211_ibss_joined(ar->arNetDev, bssid, GFP_KERNEL);
return;
@@ -625,8 +642,14 @@
u8 *assocInfo, u16 protocolReasonStatus)
{
+ u16 status;
+
AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: reason=%u\n", __func__, reason));
+ if (ar->scan_request) {
+ cfg80211_scan_done(ar->scan_request, true);
+ ar->scan_request = NULL;
+ }
if((ADHOC_NETWORK & ar->arNetworkType)) {
if(NL80211_IFTYPE_ADHOC != ar->wdev->iftype) {
AR_DEBUG_PRINTF(ATH_DEBUG_INFO,
@@ -651,23 +674,70 @@
/* connect cmd failed */
wmi_disconnect_cmd(ar->arWmi);
} else if (reason == DISCONNECT_CMD) {
- /* connection loss due to disconnect cmd or low rssi */
- ar->arConnectPending = false;
- if (ar->smeState == SME_CONNECTING) {
- cfg80211_connect_result(ar->arNetDev, bssid,
- NULL, 0,
- NULL, 0,
- WLAN_STATUS_UNSPECIFIED_FAILURE,
- GFP_KERNEL);
- } else {
- cfg80211_disconnected(ar->arNetDev, reason, NULL, 0, GFP_KERNEL);
- }
- ar->smeState = SME_DISCONNECTED;
- }
+ if (ar->arAutoAuthStage) {
+ /*
+ * If the current auth algorithm is open try shared
+ * and make autoAuthStage idle. We do not make it
+ * leap for now being.
+ */
+ if (ar->arDot11AuthMode == OPEN_AUTH) {
+ struct ar_key *key = NULL;
+ key = &ar->keys[ar->arDefTxKeyIndex];
+ if (down_interruptible(&ar->arSem)) {
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("%s: busy, couldn't get access\n", __func__));
+ return;
+ }
+
+
+ ar->arDot11AuthMode = SHARED_AUTH;
+ ar->arAutoAuthStage = AUTH_IDLE;
+
+ wmi_addKey_cmd(ar->arWmi, ar->arDefTxKeyIndex,
+ ar->arPairwiseCrypto,
+ GROUP_USAGE | TX_USAGE,
+ key->key_len,
+ NULL,
+ key->key, KEY_OP_INIT_VAL, NULL,
+ NO_SYNC_WMIFLAG);
+
+ status = wmi_connect_cmd(ar->arWmi,
+ ar->arNetworkType,
+ ar->arDot11AuthMode,
+ ar->arAuthMode,
+ ar->arPairwiseCrypto,
+ ar->arPairwiseCryptoLen,
+ ar->arGroupCrypto,
+ ar->arGroupCryptoLen,
+ ar->arSsidLen,
+ ar->arSsid,
+ ar->arReqBssid,
+ ar->arChannelHint,
+ ar->arConnectCtrlFlags);
+ up(&ar->arSem);
+
+ } else if (ar->arDot11AuthMode == SHARED_AUTH) {
+ /* should not reach here */
+ }
+ } else {
+ ar->arConnectPending = false;
+ if (ar->smeState == SME_CONNECTING) {
+ cfg80211_connect_result(ar->arNetDev, bssid,
+ NULL, 0,
+ NULL, 0,
+ WLAN_STATUS_UNSPECIFIED_FAILURE,
+ GFP_KERNEL);
+ } else {
+ cfg80211_disconnected(ar->arNetDev,
+ reason,
+ NULL, 0,
+ GFP_KERNEL);
+ }
+ ar->smeState = SME_DISCONNECTED;
+ }
+ }
} else {
- if (reason != DISCONNECT_CMD) {
- wmi_disconnect_cmd(ar->arWmi);
- }
+ if (reason != DISCONNECT_CMD)
+ wmi_disconnect_cmd(ar->arWmi);
}
}
@@ -729,7 +799,7 @@
le16_to_cpu(size),
signal, GFP_KERNEL);
- A_FREE (ieeemgmtbuf);
+ kfree (ieeemgmtbuf);
}
static int
@@ -1205,10 +1275,10 @@
if(pmgmt) {
AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: Max Perf\n", __func__));
- pwrMode.powerMode = MAX_PERF_POWER;
+ pwrMode.powerMode = REC_POWER;
} else {
AR_DEBUG_PRINTF(ATH_DEBUG_INFO, ("%s: Rec Power\n", __func__));
- pwrMode.powerMode = REC_POWER;
+ pwrMode.powerMode = MAX_PERF_POWER;
}
if(wmi_powermode_cmd(ar->arWmi, pwrMode.powerMode) != 0) {
@@ -1391,6 +1461,151 @@
WLAN_CIPHER_SUITE_CCMP,
};
+bool is_rate_legacy(s32 rate)
+{
+ static const s32 legacy[] = { 1000, 2000, 5500, 11000,
+ 6000, 9000, 12000, 18000, 24000,
+ 36000, 48000, 54000 };
+ u8 i;
+
+ for (i = 0; i < ARRAY_SIZE(legacy); i++) {
+ if (rate == legacy[i])
+ return true;
+ }
+
+ return false;
+}
+
+bool is_rate_ht20(s32 rate, u8 *mcs, bool *sgi)
+{
+ static const s32 ht20[] = { 6500, 13000, 19500, 26000, 39000,
+ 52000, 58500, 65000, 72200 };
+ u8 i;
+
+ for (i = 0; i < ARRAY_SIZE(ht20); i++) {
+ if (rate == ht20[i]) {
+ if (i == ARRAY_SIZE(ht20) - 1)
+ /* last rate uses sgi */
+ *sgi = true;
+ else
+ *sgi = false;
+
+ *mcs = i;
+ return true;
+ }
+ }
+ return false;
+}
+
+bool is_rate_ht40(s32 rate, u8 *mcs, bool *sgi)
+{
+ static const s32 ht40[] = { 13500, 27000, 40500, 54000,
+ 81000, 108000, 121500, 135000,
+ 150000 };
+ u8 i;
+
+ for (i = 0; i < ARRAY_SIZE(ht40); i++) {
+ if (rate == ht40[i]) {
+ if (i == ARRAY_SIZE(ht40) - 1)
+ /* last rate uses sgi */
+ *sgi = true;
+ else
+ *sgi = false;
+
+ *mcs = i;
+ return true;
+ }
+ }
+
+ return false;
+}
+
+static int ar6k_get_station(struct wiphy *wiphy, struct net_device *dev,
+ u8 *mac, struct station_info *sinfo)
+{
+ struct ar6_softc *ar = ar6k_priv(dev);
+ long left;
+ bool sgi;
+ s32 rate;
+ int ret;
+ u8 mcs;
+
+ if (memcmp(mac, ar->arBssid, ETH_ALEN) != 0)
+ return -ENOENT;
+
+ if (down_interruptible(&ar->arSem))
+ return -EBUSY;
+
+ ar->statsUpdatePending = true;
+
+ ret = wmi_get_stats_cmd(ar->arWmi);
+
+ if (ret != 0) {
+ up(&ar->arSem);
+ return -EIO;
+ }
+
+ left = wait_event_interruptible_timeout(arEvent,
+ ar->statsUpdatePending == false,
+ wmitimeout * HZ);
+
+ up(&ar->arSem);
+
+ if (left == 0)
+ return -ETIMEDOUT;
+ else if (left < 0)
+ return left;
+
+ if (ar->arTargetStats.rx_bytes) {
+ sinfo->rx_bytes = ar->arTargetStats.rx_bytes;
+ sinfo->filled |= STATION_INFO_RX_BYTES;
+ sinfo->rx_packets = ar->arTargetStats.rx_packets;
+ sinfo->filled |= STATION_INFO_RX_PACKETS;
+ }
+
+ if (ar->arTargetStats.tx_bytes) {
+ sinfo->tx_bytes = ar->arTargetStats.tx_bytes;
+ sinfo->filled |= STATION_INFO_TX_BYTES;
+ sinfo->tx_packets = ar->arTargetStats.tx_packets;
+ sinfo->filled |= STATION_INFO_TX_PACKETS;
+ }
+
+ sinfo->signal = ar->arTargetStats.cs_rssi;
+ sinfo->filled |= STATION_INFO_SIGNAL;
+
+ rate = ar->arTargetStats.tx_unicast_rate;
+
+ if (is_rate_legacy(rate)) {
+ sinfo->txrate.legacy = rate / 100;
+ } else if (is_rate_ht20(rate, &mcs, &sgi)) {
+ if (sgi) {
+ sinfo->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
+ sinfo->txrate.mcs = mcs - 1;
+ } else {
+ sinfo->txrate.mcs = mcs;
+ }
+
+ sinfo->txrate.flags |= RATE_INFO_FLAGS_MCS;
+ } else if (is_rate_ht40(rate, &mcs, &sgi)) {
+ if (sgi) {
+ sinfo->txrate.flags |= RATE_INFO_FLAGS_SHORT_GI;
+ sinfo->txrate.mcs = mcs - 1;
+ } else {
+ sinfo->txrate.mcs = mcs;
+ }
+
+ sinfo->txrate.flags |= RATE_INFO_FLAGS_40_MHZ_WIDTH;
+ sinfo->txrate.flags |= RATE_INFO_FLAGS_MCS;
+ } else {
+ WARN(1, "invalid rate: %d", rate);
+ return 0;
+ }
+
+ sinfo->filled |= STATION_INFO_TX_BITRATE;
+
+ return 0;
+}
+
static struct
cfg80211_ops ar6k_cfg80211_ops = {
.change_virtual_intf = ar6k_cfg80211_change_iface,
@@ -1411,6 +1626,7 @@
.set_power_mgmt = ar6k_cfg80211_set_power_mgmt,
.join_ibss = ar6k_cfg80211_join_ibss,
.leave_ibss = ar6k_cfg80211_leave_ibss,
+ .get_station = ar6k_get_station,
};
struct wireless_dev *
diff --git a/drivers/staging/ath6kl/os/linux/eeprom.c b/drivers/staging/ath6kl/os/linux/eeprom.c
deleted file mode 100644
index 4cff9da..0000000
--- a/drivers/staging/ath6kl/os/linux/eeprom.c
+++ /dev/null
@@ -1,574 +0,0 @@
-//------------------------------------------------------------------------------
-// Copyright (c) 2004-2010 Atheros Communications Inc.
-// All rights reserved.
-//
-//
-//
-// Permission to use, copy, modify, and/or distribute this software for any
-// purpose with or without fee is hereby granted, provided that the above
-// copyright notice and this permission notice appear in all copies.
-//
-// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-//
-//
-//
-// Author(s): ="Atheros"
-//------------------------------------------------------------------------------
-
-
-#include "ar6000_drv.h"
-#include "htc.h"
-#include <linux/fs.h>
-
-#include "AR6002/hw2.0/hw/gpio_reg.h"
-#include "AR6002/hw2.0/hw/si_reg.h"
-
-//
-// defines
-//
-
-#define MAX_FILENAME 1023
-#define EEPROM_WAIT_LIMIT 16
-
-#define HOST_INTEREST_ITEM_ADDRESS(item) \
- (AR6002_HOST_INTEREST_ITEM_ADDRESS(item))
-
-#define EEPROM_SZ 768
-
-/* soft mac */
-#define ATH_MAC_LEN 6
-#define ATH_SOFT_MAC_TMP_BUF_LEN 64
-unsigned char mac_addr[ATH_MAC_LEN];
-unsigned char soft_mac_tmp_buf[ATH_SOFT_MAC_TMP_BUF_LEN];
-char *p_mac = NULL;
-/* soft mac */
-
-//
-// static variables
-//
-
-static u8 eeprom_data[EEPROM_SZ];
-static u32 sys_sleep_reg;
-static struct hif_device *p_bmi_device;
-
-//
-// Functions
-//
-
-/* soft mac */
-static int
-wmic_ether_aton(const char *orig, u8 *eth)
-{
- const char *bufp;
- int i;
-
- i = 0;
- for(bufp = orig; *bufp != '\0'; ++bufp) {
- unsigned int val;
- int h, l;
-
- h = hex_to_bin(*bufp++);
-
- if (h < 0) {
- printk("%s: MAC value is invalid\n", __FUNCTION__);
- break;
- }
-
- l = hex_to_bin(*bufp++);
- if (l < 0) {
- printk("%s: MAC value is invalid\n", __FUNCTION__);
- break;
- }
-
- val = (h << 4) | l;
-
- eth[i] = (unsigned char) (val & 0377);
- if(++i == ATH_MAC_LEN) {
- /* That's it. Any trailing junk? */
- if (*bufp != '\0') {
- return 0;
- }
- return 1;
- }
- if (*bufp != ':')
- break;
- }
- return 0;
-}
-
-static void
-update_mac(unsigned char *eeprom, int size, unsigned char *macaddr)
-{
- int i;
- u16 *ptr = (u16 *)(eeprom+4);
- u16 checksum = 0;
-
- memcpy(eeprom+10,macaddr,6);
-
- *ptr = 0;
- ptr = (u16 *)eeprom;
-
- for (i=0; i<size; i+=2) {
- checksum ^= *ptr++;
- }
- checksum = ~checksum;
-
- ptr = (u16 *)(eeprom+4);
- *ptr = checksum;
- return;
-}
-/* soft mac */
-
-/* Read a Target register and return its value. */
-inline void
-BMI_read_reg(u32 address, u32 *pvalue)
-{
- BMIReadSOCRegister(p_bmi_device, address, pvalue);
-}
-
-/* Write a value to a Target register. */
-inline void
-BMI_write_reg(u32 address, u32 value)
-{
- BMIWriteSOCRegister(p_bmi_device, address, value);
-}
-
-/* Read Target memory word and return its value. */
-inline void
-BMI_read_mem(u32 address, u32 *pvalue)
-{
- BMIReadMemory(p_bmi_device, address, (u8*)(pvalue), 4);
-}
-
-/* Write a word to a Target memory. */
-inline void
-BMI_write_mem(u32 address, u8 *p_data, u32 sz)
-{
- BMIWriteMemory(p_bmi_device, address, (u8*)(p_data), sz);
-}
-
-/*
- * Enable and configure the Target's Serial Interface
- * so we can access the EEPROM.
- */
-static void
-enable_SI(struct hif_device *p_device)
-{
- u32 regval;
-
- printk("%s\n", __FUNCTION__);
-
- p_bmi_device = p_device;
-
- BMI_read_reg(RTC_BASE_ADDRESS+SYSTEM_SLEEP_OFFSET, &sys_sleep_reg);
- BMI_write_reg(RTC_BASE_ADDRESS+SYSTEM_SLEEP_OFFSET, SYSTEM_SLEEP_DISABLE_SET(1)); //disable system sleep temporarily
-
- BMI_read_reg(RTC_BASE_ADDRESS+CLOCK_CONTROL_OFFSET, ®val);
- regval &= ~CLOCK_CONTROL_SI0_CLK_MASK;
- BMI_write_reg(RTC_BASE_ADDRESS+CLOCK_CONTROL_OFFSET, regval);
-
- BMI_read_reg(RTC_BASE_ADDRESS+RESET_CONTROL_OFFSET, ®val);
- regval &= ~RESET_CONTROL_SI0_RST_MASK;
- BMI_write_reg(RTC_BASE_ADDRESS+RESET_CONTROL_OFFSET, regval);
-
-
- BMI_read_reg(GPIO_BASE_ADDRESS+GPIO_PIN0_OFFSET, ®val);
- regval &= ~GPIO_PIN0_CONFIG_MASK;
- BMI_write_reg(GPIO_BASE_ADDRESS+GPIO_PIN0_OFFSET, regval);
-
- BMI_read_reg(GPIO_BASE_ADDRESS+GPIO_PIN1_OFFSET, ®val);
- regval &= ~GPIO_PIN1_CONFIG_MASK;
- BMI_write_reg(GPIO_BASE_ADDRESS+GPIO_PIN1_OFFSET, regval);
-
- /* SI_CONFIG = 0x500a6; */
- regval = SI_CONFIG_BIDIR_OD_DATA_SET(1) |
- SI_CONFIG_I2C_SET(1) |
- SI_CONFIG_POS_SAMPLE_SET(1) |
- SI_CONFIG_INACTIVE_CLK_SET(1) |
- SI_CONFIG_INACTIVE_DATA_SET(1) |
- SI_CONFIG_DIVIDER_SET(6);
- BMI_write_reg(SI_BASE_ADDRESS+SI_CONFIG_OFFSET, regval);
-
-}
-
-static void
-disable_SI(void)
-{
- u32 regval;
-
- printk("%s\n", __FUNCTION__);
-
- BMI_write_reg(RTC_BASE_ADDRESS+RESET_CONTROL_OFFSET, RESET_CONTROL_SI0_RST_MASK);
- BMI_read_reg(RTC_BASE_ADDRESS+CLOCK_CONTROL_OFFSET, ®val);
- regval |= CLOCK_CONTROL_SI0_CLK_MASK;
- BMI_write_reg(RTC_BASE_ADDRESS+CLOCK_CONTROL_OFFSET, regval);//Gate SI0 clock
- BMI_write_reg(RTC_BASE_ADDRESS+SYSTEM_SLEEP_OFFSET, sys_sleep_reg); //restore system sleep setting
-}
-
-/*
- * Tell the Target to start an 8-byte read from EEPROM,
- * putting the results in Target RX_DATA registers.
- */
-static void
-request_8byte_read(int offset)
-{
- u32 regval;
-
-// printk("%s: request_8byte_read from offset 0x%x\n", __FUNCTION__, offset);
-
-
- /* SI_TX_DATA0 = read from offset */
- regval =(0xa1<<16)|
- ((offset & 0xff)<<8) |
- (0xa0 | ((offset & 0xff00)>>7));
-
- BMI_write_reg(SI_BASE_ADDRESS+SI_TX_DATA0_OFFSET, regval);
-
- regval = SI_CS_START_SET(1) |
- SI_CS_RX_CNT_SET(8) |
- SI_CS_TX_CNT_SET(3);
- BMI_write_reg(SI_BASE_ADDRESS+SI_CS_OFFSET, regval);
-}
-
-/*
- * Tell the Target to start a 4-byte write to EEPROM,
- * writing values from Target TX_DATA registers.
- */
-static void
-request_4byte_write(int offset, u32 data)
-{
- u32 regval;
-
- printk("%s: request_4byte_write (0x%x) to offset 0x%x\n", __FUNCTION__, data, offset);
-
- /* SI_TX_DATA0 = write data to offset */
- regval = ((data & 0xffff) <<16) |
- ((offset & 0xff)<<8) |
- (0xa0 | ((offset & 0xff00)>>7));
- BMI_write_reg(SI_BASE_ADDRESS+SI_TX_DATA0_OFFSET, regval);
-
- regval = data >> 16;
- BMI_write_reg(SI_BASE_ADDRESS+SI_TX_DATA1_OFFSET, regval);
-
- regval = SI_CS_START_SET(1) |
- SI_CS_RX_CNT_SET(0) |
- SI_CS_TX_CNT_SET(6);
- BMI_write_reg(SI_BASE_ADDRESS+SI_CS_OFFSET, regval);
-}
-
-/*
- * Check whether or not an EEPROM request that was started
- * earlier has completed yet.
- */
-static bool
-request_in_progress(void)
-{
- u32 regval;
-
- /* Wait for DONE_INT in SI_CS */
- BMI_read_reg(SI_BASE_ADDRESS+SI_CS_OFFSET, ®val);
-
-// printk("%s: request in progress SI_CS=0x%x\n", __FUNCTION__, regval);
- if (regval & SI_CS_DONE_ERR_MASK) {
- printk("%s: EEPROM signaled ERROR (0x%x)\n", __FUNCTION__, regval);
- }
-
- return (!(regval & SI_CS_DONE_INT_MASK));
-}
-
-/*
- * try to detect the type of EEPROM,16bit address or 8bit address
- */
-
-static void eeprom_type_detect(void)
-{
- u32 regval;
- u8 i = 0;
-
- request_8byte_read(0x100);
- /* Wait for DONE_INT in SI_CS */
- do{
- BMI_read_reg(SI_BASE_ADDRESS+SI_CS_OFFSET, ®val);
- if (regval & SI_CS_DONE_ERR_MASK) {
- printk("%s: ERROR : address type was wrongly set\n", __FUNCTION__);
- break;
- }
- if (i++ == EEPROM_WAIT_LIMIT) {
- printk("%s: EEPROM not responding\n", __FUNCTION__);
- }
- } while(!(regval & SI_CS_DONE_INT_MASK));
-}
-
-/*
- * Extract the results of a completed EEPROM Read request
- * and return them to the caller.
- */
-inline void
-read_8byte_results(u32 *data)
-{
- /* Read SI_RX_DATA0 and SI_RX_DATA1 */
- BMI_read_reg(SI_BASE_ADDRESS+SI_RX_DATA0_OFFSET, &data[0]);
- BMI_read_reg(SI_BASE_ADDRESS+SI_RX_DATA1_OFFSET, &data[1]);
-}
-
-
-/*
- * Wait for a previously started command to complete.
- * Timeout if the command is takes "too long".
- */
-static void
-wait_for_eeprom_completion(void)
-{
- int i=0;
-
- while (request_in_progress()) {
- if (i++ == EEPROM_WAIT_LIMIT) {
- printk("%s: EEPROM not responding\n", __FUNCTION__);
- }
- }
-}
-
-/*
- * High-level function which starts an 8-byte read,
- * waits for it to complete, and returns the result.
- */
-static void
-fetch_8bytes(int offset, u32 *data)
-{
- request_8byte_read(offset);
- wait_for_eeprom_completion();
- read_8byte_results(data);
-
- /* Clear any pending intr */
- BMI_write_reg(SI_BASE_ADDRESS+SI_CS_OFFSET, SI_CS_DONE_INT_MASK);
-}
-
-/*
- * High-level function which starts a 4-byte write,
- * and waits for it to complete.
- */
-inline void
-commit_4bytes(int offset, u32 data)
-{
- request_4byte_write(offset, data);
- wait_for_eeprom_completion();
-}
-/* ATHENV */
-#ifdef ANDROID_ENV
-void eeprom_ar6000_transfer(struct hif_device *device, char *fake_file, char *p_mac)
-{
- u32 first_word;
- u32 board_data_addr;
- int i;
-
- printk("%s: Enter\n", __FUNCTION__);
-
- enable_SI(device);
- eeprom_type_detect();
-
- if (fake_file) {
- /*
- * Transfer from file to Target RAM.
- * Fetch source data from file.
- */
- mm_segment_t oldfs;
- struct file *filp;
- struct inode *inode = NULL;
- int length;
-
- /* open file */
- oldfs = get_fs();
- set_fs(KERNEL_DS);
- filp = filp_open(fake_file, O_RDONLY, S_IRUSR);
-
- if (IS_ERR(filp)) {
- printk("%s: file %s filp_open error\n", __FUNCTION__, fake_file);
- set_fs(oldfs);
- return;
- }
-
- if (!filp->f_op) {
- printk("%s: File Operation Method Error\n", __FUNCTION__);
- filp_close(filp, NULL);
- set_fs(oldfs);
- return;
- }
-
- inode = GET_INODE_FROM_FILEP(filep);
- if (!inode) {
- printk("%s: Get inode from filp failed\n", __FUNCTION__);
- filp_close(filp, NULL);
- set_fs(oldfs);
- return;
- }
-
- printk("%s file offset opsition: %xh\n", __FUNCTION__, (unsigned)filp->f_pos);
-
- /* file's size */
- length = i_size_read(inode->i_mapping->host);
- printk("%s: length=%d\n", __FUNCTION__, length);
- if (length != EEPROM_SZ) {
- printk("%s: The file's size is not as expected\n", __FUNCTION__);
- filp_close(filp, NULL);
- set_fs(oldfs);
- return;
- }
-
- /* read data */
- if (filp->f_op->read(filp, eeprom_data, length, &filp->f_pos) != length) {
- printk("%s: file read error\n", __FUNCTION__);
- filp_close(filp, NULL);
- set_fs(oldfs);
- return;
- }
-
- /* read data out successfully */
- filp_close(filp, NULL);
- set_fs(oldfs);
- } else {
- /*
- * Read from EEPROM to file OR transfer from EEPROM to Target RAM.
- * Fetch EEPROM_SZ Bytes of Board Data, 8 bytes at a time.
- */
-
- fetch_8bytes(0, (u32 *)(&eeprom_data[0]));
-
- /* Check the first word of EEPROM for validity */
- first_word = *((u32 *)eeprom_data);
-
- if ((first_word == 0) || (first_word == 0xffffffff)) {
- printk("Did not find EEPROM with valid Board Data.\n");
- }
-
- for (i=8; i<EEPROM_SZ; i+=8) {
- fetch_8bytes(i, (u32 *)(&eeprom_data[i]));
- }
- }
-
- /* soft mac */
- if (p_mac) {
-
- mm_segment_t oldfs;
- struct file *filp;
- struct inode *inode = NULL;
- int length;
-
- /* open file */
- oldfs = get_fs();
- set_fs(KERNEL_DS);
- filp = filp_open(p_mac, O_RDONLY, S_IRUSR);
-
- printk("%s try to open file %s\n", __FUNCTION__, p_mac);
-
- if (IS_ERR(filp)) {
- printk("%s: file %s filp_open error\n", __FUNCTION__, p_mac);
- set_fs(oldfs);
- return;
- }
-
- if (!filp->f_op) {
- printk("%s: File Operation Method Error\n", __FUNCTION__);
- filp_close(filp, NULL);
- set_fs(oldfs);
- return;
- }
-
- inode = GET_INODE_FROM_FILEP(filep);
- if (!inode) {
- printk("%s: Get inode from filp failed\n", __FUNCTION__);
- filp_close(filp, NULL);
- set_fs(oldfs);
- return;
- }
-
- printk("%s file offset opsition: %xh\n", __FUNCTION__, (unsigned)filp->f_pos);
-
- /* file's size */
- length = i_size_read(inode->i_mapping->host);
- printk("%s: length=%d\n", __FUNCTION__, length);
- if (length > ATH_SOFT_MAC_TMP_BUF_LEN) {
- printk("%s: MAC file's size is not as expected\n", __FUNCTION__);
- filp_close(filp, NULL);
- set_fs(oldfs);
- return;
- }
-
- /* read data */
- if (filp->f_op->read(filp, soft_mac_tmp_buf, length, &filp->f_pos) != length) {
- printk("%s: file read error\n", __FUNCTION__);
- filp_close(filp, NULL);
- set_fs(oldfs);
- return;
- }
-
-#if 0
- /* the data we just read */
- printk("%s: mac address from the file:\n", __FUNCTION__);
- for (i = 0; i < length; i++)
- printk("[%c(0x%x)],", soft_mac_tmp_buf[i], soft_mac_tmp_buf[i]);
- printk("\n");
-#endif
-
- /* read data out successfully */
- filp_close(filp, NULL);
- set_fs(oldfs);
-
- /* convert mac address */
- if (!wmic_ether_aton(soft_mac_tmp_buf, mac_addr)) {
- printk("%s: convert mac value fail\n", __FUNCTION__);
- return;
- }
-
-#if 0
- /* the converted mac address */
- printk("%s: the converted mac value\n", __FUNCTION__);
- for (i = 0; i < ATH_MAC_LEN; i++)
- printk("[0x%x],", mac_addr[i]);
- printk("\n");
-#endif
- }
- /* soft mac */
-
- /* Determine where in Target RAM to write Board Data */
- BMI_read_mem( HOST_INTEREST_ITEM_ADDRESS(hi_board_data), &board_data_addr);
- if (board_data_addr == 0) {
- printk("hi_board_data is zero\n");
- }
-
- /* soft mac */
-#if 1
- /* Update MAC address in RAM */
- if (p_mac) {
- update_mac(eeprom_data, EEPROM_SZ, mac_addr);
- }
-#endif
-#if 0
- /* mac address in eeprom array */
- printk("%s: mac values in eeprom array\n", __FUNCTION__);
- for (i = 10; i < 10 + 6; i++)
- printk("[0x%x],", eeprom_data[i]);
- printk("\n");
-#endif
- /* soft mac */
-
- /* Write EEPROM data to Target RAM */
- BMI_write_mem(board_data_addr, ((u8 *)eeprom_data), EEPROM_SZ);
-
- /* Record the fact that Board Data IS initialized */
- {
- u32 one = 1;
- BMI_write_mem(HOST_INTEREST_ITEM_ADDRESS(hi_board_data_initialized),
- (u8 *)&one, sizeof(u32));
- }
-
- disable_SI();
-}
-#endif
-/* ATHENV */
-
diff --git a/drivers/staging/ath6kl/os/linux/export_hci_transport.c b/drivers/staging/ath6kl/os/linux/export_hci_transport.c
index 442a286..430998e 100644
--- a/drivers/staging/ath6kl/os/linux/export_hci_transport.c
+++ b/drivers/staging/ath6kl/os/linux/export_hci_transport.c
@@ -23,7 +23,6 @@
//==============================================================================
#include <a_config.h>
#include <athdefs.h>
-#include "a_types.h"
#include "a_osapi.h"
#include "htc_api.h"
#include "a_drv.h"
diff --git a/drivers/staging/ath6kl/os/linux/hci_bridge.c b/drivers/staging/ath6kl/os/linux/hci_bridge.c
index 39e5798..6087edc 100644
--- a/drivers/staging/ath6kl/os/linux/hci_bridge.c
+++ b/drivers/staging/ath6kl/os/linux/hci_bridge.c
@@ -26,7 +26,6 @@
#include <linux/etherdevice.h>
#include <a_config.h>
#include <athdefs.h>
-#include "a_types.h"
#include "a_osapi.h"
#include "htc_api.h"
#include "wmi.h"
@@ -582,11 +581,11 @@
}
if (pHcidevInfo->pHTCStructAlloc != NULL) {
- A_FREE(pHcidevInfo->pHTCStructAlloc);
+ kfree(pHcidevInfo->pHTCStructAlloc);
pHcidevInfo->pHTCStructAlloc = NULL;
}
- A_FREE(pHcidevInfo);
+ kfree(pHcidevInfo);
#ifndef EXPORT_HCI_BRIDGE_INTERFACE
ar->hcidev_info = NULL;
#endif
diff --git a/drivers/staging/ath6kl/os/linux/include/ar6000_drv.h b/drivers/staging/ath6kl/os/linux/include/ar6000_drv.h
index 89fd80a..22453b0 100644
--- a/drivers/staging/ath6kl/os/linux/include/ar6000_drv.h
+++ b/drivers/staging/ath6kl/os/linux/include/ar6000_drv.h
@@ -33,15 +33,12 @@
#include <linux/if_arp.h>
#include <linux/ip.h>
#include <linux/wireless.h>
-#ifdef ATH6K_CONFIG_CFG80211
#include <net/cfg80211.h>
-#endif /* ATH6K_CONFIG_CFG80211 */
#include <linux/module.h>
#include <asm/io.h>
#include <a_config.h>
#include <athdefs.h>
-#include "a_types.h"
#include "a_osapi.h"
#include "htc_api.h"
#include "wmi.h"
@@ -51,8 +48,6 @@
#include <ieee80211_ioctl.h>
#include <wlan_api.h>
#include <wmi_api.h>
-#include "gpio_api.h"
-#include "gpio.h"
#include "pkt_log.h"
#include "aggr_recv_api.h"
#include <host_version.h>
@@ -76,7 +71,7 @@
#include "hw/apb_map.h"
#include "hw/rtc_reg.h"
#include "hw/mbox_reg.h"
-#include "hw/gpio_reg.h"
+#include "gpio_reg.h"
#define ATH_DEBUG_DBG_LOG ATH_DEBUG_MAKE_MODULE_MASK(0)
#define ATH_DEBUG_WLAN_CONNECT ATH_DEBUG_MAKE_MODULE_MASK(1)
@@ -94,8 +89,6 @@
#endif
-#ifdef USER_KEYS
-
#define USER_SAVEDKEYS_STAT_INIT 0
#define USER_SAVEDKEYS_STAT_RUN 1
@@ -106,7 +99,6 @@
CRYPTO_TYPE keyType;
bool keyOk;
};
-#endif
#define DBG_INFO 0x00000001
#define DBG_ERROR 0x00000002
@@ -215,35 +207,42 @@
#define SETUPHCI_DEFAULT 0
#endif /* SETUPHCI_ENABLED */
-#ifdef SETUPHCIPAL_ENABLED
-#define SETUPHCIPAL_DEFAULT 1
-#else
-#define SETUPHCIPAL_DEFAULT 0
-#endif /* SETUPHCIPAL_ENABLED */
-
#ifdef SETUPBTDEV_ENABLED
#define SETUPBTDEV_DEFAULT 1
#else
#define SETUPBTDEV_DEFAULT 0
#endif /* SETUPBTDEV_ENABLED */
-#ifdef BMIENABLE_SET
-#define BMIENABLE_DEFAULT 1
-#else
-#define BMIENABLE_DEFAULT 0
-#endif /* BMIENABLE_SET */
-
#ifdef ENABLEUARTPRINT_SET
#define ENABLEUARTPRINT_DEFAULT 1
#else
#define ENABLEUARTPRINT_DEFAULT 0
#endif /* ENABLEARTPRINT_SET */
-#ifdef ATH6K_CONFIG_HIF_VIRTUAL_SCATTER
+#ifdef ATH6KL_CONFIG_HIF_VIRTUAL_SCATTER
#define NOHIFSCATTERSUPPORT_DEFAULT 1
-#else /* ATH6K_CONFIG_HIF_VIRTUAL_SCATTER */
+#else /* ATH6KL_CONFIG_HIF_VIRTUAL_SCATTER */
#define NOHIFSCATTERSUPPORT_DEFAULT 0
-#endif /* ATH6K_CONFIG_HIF_VIRTUAL_SCATTER */
+#endif /* ATH6KL_CONFIG_HIF_VIRTUAL_SCATTER */
+
+
+#if defined(CONFIG_ATH6KL_ENABLE_COEXISTENCE)
+
+#ifdef CONFIG_AR600x_BT_QCOM
+#define ATH6KL_BT_DEV 1
+#elif defined(CONFIG_AR600x_BT_CSR)
+#define ATH6KL_BT_DEV 2
+#else
+#define ATH6KL_BT_DEV 3
+#endif
+
+#ifdef CONFIG_AR600x_DUAL_ANTENNA
+#define ATH6KL_BT_ANTENNA 2
+#else
+#define ATH6KL_BT_ANTENNA 1
+#endif
+
+#endif /* CONFIG_ATH6KL_ENABLE_COEXISTENCE */
#ifdef AR600x_BT_AR3001
#define AR3KHCIBAUD_DEFAULT 3000000
@@ -255,11 +254,7 @@
#define HCIUARTSTEP_DEFAULT 0
#endif /* AR600x_BT_AR3001 */
-#ifdef INIT_MODE_DRV_ENABLED
#define WLAN_INIT_MODE_DEFAULT WLAN_INIT_MODE_DRV
-#else
-#define WLAN_INIT_MODE_DEFAULT WLAN_INIT_MODE_USR
-#endif /* INIT_MODE_DRV_ENABLED */
#define AR6K_PATCH_DOWNLOAD_ADDRESS(_param, _ver) do { \
if ((_ver) == AR6003_REV1_VERSION) { \
@@ -283,15 +278,37 @@
} \
} while (0)
+#define AR6K_DATASET_PATCH_ADDRESS(_param, _ver) do { \
+ if ((_ver) == AR6003_REV2_VERSION) { \
+ (_param) = AR6003_REV2_DATASET_PATCH_ADDRESS; \
+ } else if ((_ver) == AR6003_REV3_VERSION) { \
+ (_param) = AR6003_REV3_DATASET_PATCH_ADDRESS; \
+ } else { \
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unknown Version: %d\n", _ver)); \
+ A_ASSERT(0); \
+ } \
+} while (0)
+
+#define AR6K_APP_LOAD_ADDRESS(_param, _ver) do { \
+ if ((_ver) == AR6003_REV2_VERSION) { \
+ (_param) = AR6003_REV2_APP_LOAD_ADDRESS; \
+ } else if ((_ver) == AR6003_REV3_VERSION) { \
+ (_param) = AR6003_REV3_APP_LOAD_ADDRESS; \
+ } else { \
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unknown Version: %d\n", _ver)); \
+ A_ASSERT(0); \
+ } \
+} while (0)
+
#define AR6K_APP_START_OVERRIDE_ADDRESS(_param, _ver) do { \
- if ((_ver) == AR6003_REV1_VERSION) { \
- (_param) = AR6003_REV1_APP_START_OVERRIDE; \
- } else if ((_ver) == AR6003_REV2_VERSION) { \
- (_param) = AR6003_REV2_APP_START_OVERRIDE; \
- } else { \
- AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unknown Version: %d\n", _ver)); \
- A_ASSERT(0); \
- } \
+ if ((_ver) == AR6003_REV2_VERSION) { \
+ (_param) = AR6003_REV2_APP_START_OVERRIDE; \
+ } else if ((_ver) == AR6003_REV3_VERSION) { \
+ (_param) = AR6003_REV3_APP_START_OVERRIDE; \
+ } else { \
+ AR_DEBUG_PRINTF(ATH_DEBUG_ERR, ("Unknown Version: %d\n", _ver)); \
+ A_ASSERT(0); \
+ } \
} while (0)
/* AR6003 1.0 definitions */
@@ -304,11 +321,11 @@
#define AR6003_REV1_ART_FIRMWARE_FILE "ath6k/AR6003/hw1.0/device.bin"
#define AR6003_REV1_PATCH_FILE "ath6k/AR6003/hw1.0/data.patch.bin"
#define AR6003_REV1_EPPING_FIRMWARE_FILE "ath6k/AR6003/hw1.0/endpointping.bin"
-#ifdef AR600x_SD31_XXX
+#ifdef CONFIG_AR600x_SD31_XXX
#define AR6003_REV1_BOARD_DATA_FILE "ath6k/AR6003/hw1.0/bdata.SD31.bin"
-#elif defined(AR600x_SD32_XXX)
+#elif defined(CONFIG_AR600x_SD32_XXX)
#define AR6003_REV1_BOARD_DATA_FILE "ath6k/AR6003/hw1.0/bdata.SD32.bin"
-#elif defined(AR600x_WB31_XXX)
+#elif defined(CONFIG_AR600x_WB31_XXX)
#define AR6003_REV1_BOARD_DATA_FILE "ath6k/AR6003/hw1.0/bdata.WB31.bin"
#else
#define AR6003_REV1_BOARD_DATA_FILE "ath6k/AR6003/hw1.0/bdata.CUSTOM.bin"
@@ -324,16 +341,35 @@
#define AR6003_REV2_ART_FIRMWARE_FILE "ath6k/AR6003/hw2.0/device.bin"
#define AR6003_REV2_PATCH_FILE "ath6k/AR6003/hw2.0/data.patch.bin"
#define AR6003_REV2_EPPING_FIRMWARE_FILE "ath6k/AR6003/hw2.0/endpointping.bin"
-#ifdef AR600x_SD31_XXX
+#ifdef CONFIG_AR600x_SD31_XXX
#define AR6003_REV2_BOARD_DATA_FILE "ath6k/AR6003/hw2.0/bdata.SD31.bin"
-#elif defined(AR600x_SD32_XXX)
+#elif defined(CONFIG_AR600x_SD32_XXX)
#define AR6003_REV2_BOARD_DATA_FILE "ath6k/AR6003/hw2.0/bdata.SD32.bin"
-#elif defined(AR600x_WB31_XXX)
+#elif defined(CONFIG_AR600x_WB31_XXX)
#define AR6003_REV2_BOARD_DATA_FILE "ath6k/AR6003/hw2.0/bdata.WB31.bin"
#else
#define AR6003_REV2_BOARD_DATA_FILE "ath6k/AR6003/hw2.0/bdata.CUSTOM.bin"
#endif /* Board Data File */
+/* AR6003 3.0 definitions */
+#define AR6003_REV3_VERSION 0x30000582
+#define AR6003_REV3_OTP_FILE "ath6k/AR6003/hw2.1.1/otp.bin"
+#define AR6003_REV3_FIRMWARE_FILE "ath6k/AR6003/hw2.1.1/athwlan.bin"
+#define AR6003_REV3_TCMD_FIRMWARE_FILE "ath6k/AR6003/hw2.1.1/athtcmd_ram.bin"
+#define AR6003_REV3_ART_FIRMWARE_FILE "ath6k/AR6003/hw2.1.1/device.bin"
+#define AR6003_REV3_PATCH_FILE "ath6k/AR6003/hw2.1.1/data.patch.bin"
+#define AR6003_REV3_EPPING_FIRMWARE_FILE "ath6k/AR6003/hw2.1.1/endpointping.bin"
+#ifdef CONFIG_AR600x_SD31_XXX
+#define AR6003_REV3_BOARD_DATA_FILE "ath6k/AR6003/hw2.1.1/bdata.SD31.bin"
+#elif defined(CONFIG_AR600x_SD32_XXX)
+#define AR6003_REV3_BOARD_DATA_FILE "ath6k/AR6003/hw2.1.1/bdata.SD32.bin"
+#elif defined(CONFIG_AR600x_WB31_XXX)
+#define AR6003_REV3_BOARD_DATA_FILE "ath6k/AR6003/hw2.1.1/bdata.WB31.bin"
+#else
+#define AR6003_REV3_BOARD_DATA_FILE "ath6k/AR6003/hw2.1.1/bdata.CUSTOM.bin"
+#endif /* Board Data File */
+
+
/* Power states */
enum {
WLAN_PWR_CTRL_UP = 0,
@@ -385,7 +421,6 @@
u8 arKey[64];
} ;
-#ifdef ATH6K_CONFIG_CFG80211
struct ar_key {
u8 key[WLAN_MAX_KEY_LEN];
u8 key_len;
@@ -399,8 +434,6 @@
SME_CONNECTING,
SME_CONNECTED
};
-#endif /* ATH6K_CONFIG_CFG80211 */
-
struct ar_node_mapping {
u8 macAddress[6];
@@ -557,11 +590,9 @@
u32 log_cnt;
u32 dbglog_init_done;
u32 arConnectCtrlFlags;
-#ifdef USER_KEYS
s32 user_savedkeys_stat;
u32 user_key_ctrl;
struct USER_SAVEDKEYS user_saved_keys;
-#endif
USER_RSSI_THOLD rssi_map[12];
u8 arUserBssFilter;
u16 ap_profile_flag; /* AP mode */
@@ -577,7 +608,6 @@
#ifndef EXPORT_HCI_BRIDGE_INTERFACE
void *hcidev_info;
#endif
- void *hcipal_info;
WMI_AP_MODE_STAT arAPStats;
u8 ap_hidden_ssid;
u8 ap_country_code[3];
@@ -597,12 +627,10 @@
WMI_BTCOEX_STATS_EVENT arBtcoexStats;
s32 (*exitCallback)(void *config); /* generic callback at AR6K exit */
struct hif_device_os_device_info osDevInfo;
-#ifdef ATH6K_CONFIG_CFG80211
struct wireless_dev *wdev;
struct cfg80211_scan_request *scan_request;
struct ar_key keys[WMI_MAX_KEY_INDEX + 1];
u32 smeState;
-#endif /* ATH6K_CONFIG_CFG80211 */
u16 arWlanPowerState;
bool arWlanOff;
#ifdef CONFIG_PM
@@ -622,6 +650,7 @@
#ifdef CONFIG_AP_VIRTUAL_ADAPTER_SUPPORT
void *arApDev;
#endif
+ u8 arAutoAuthStage;
};
#ifdef CONFIG_AP_VIRTUAL_ADAPTER_SUPPORT
@@ -632,30 +661,10 @@
};
#endif /* CONFIG_AP_VIRTUAL_ADAPTER_SUPPORT */
-#ifdef ATH6K_CONFIG_CFG80211
static inline void *ar6k_priv(struct net_device *dev)
{
return (wdev_priv(dev->ieee80211_ptr));
}
-#else
-#ifdef CONFIG_AP_VIRTUAL_ADAPTER_SUPPORT
-static inline void *ar6k_priv(struct net_device *dev)
-{
- extern struct net_device *arApNetDev;
-
- if (arApNetDev == dev) {
- /* return arDev saved in virtual interface context */
- struct ar_virtual_interface *arVirDev;
- arVirDev = netdev_priv(dev);
- return arVirDev->arDev;
- } else {
- return netdev_priv(dev);
- }
-}
-#else
-#define ar6k_priv netdev_priv
-#endif /* CONFIG_AP_VIRTUAL_ADAPTER_SUPPORT */
-#endif /* ATH6K_CONFIG_CFG80211 */
#define SET_HCI_BUS_TYPE(pHciDev, __bus, __type) do { \
(pHciDev)->bus = (__bus); \
@@ -701,9 +710,6 @@
spin_unlock_bh(lock); \
} while (0)
-int ar6000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
-int ar6000_ioctl_dispatcher(struct net_device *dev, struct ifreq *rq, int cmd);
-void ar6000_gpio_init(void);
void ar6000_init_profile_info(struct ar6_softc *ar);
void ar6000_install_static_wep_keys(struct ar6_softc *ar);
int ar6000_init(struct net_device *dev);
diff --git a/drivers/staging/ath6kl/os/linux/include/ar6xapi_linux.h b/drivers/staging/ath6kl/os/linux/include/ar6xapi_linux.h
index 1acfb9c..184dbdb 100644
--- a/drivers/staging/ath6kl/os/linux/include/ar6xapi_linux.h
+++ b/drivers/staging/ath6kl/os/linux/include/ar6xapi_linux.h
@@ -83,11 +83,6 @@
void ar6000_dbglog_init_done(struct ar6_softc *ar);
-#ifdef SEND_EVENT_TO_APP
-void ar6000_send_event_to_app(struct ar6_softc *ar, u16 eventId, u8 *datap, int len);
-void ar6000_send_generic_event_to_app(struct ar6_softc *ar, u16 eventId, u8 *datap, int len);
-#endif
-
#ifdef CONFIG_HOST_TCMD_SUPPORT
void ar6000_tcmd_rx_report_event(void *devt, u8 *results, int len);
#endif
@@ -183,9 +178,6 @@
void ar6000_check_wow_status(struct ar6_softc *ar, struct sk_buff *skb, bool isEvent);
#endif
-void ar6000_pm_init(void);
-void ar6000_pm_exit(void);
-
#ifdef CONFIG_AP_VIRTUAL_ADAPTER_SUPPORT
int ar6000_add_ap_interface(struct ar6_softc *ar, char *ifname);
int ar6000_remove_ap_interface(struct ar6_softc *ar);
diff --git a/drivers/staging/ath6kl/os/linux/include/athdrv_linux.h b/drivers/staging/ath6kl/os/linux/include/athdrv_linux.h
index 66817c2..3d5f01d 100644
--- a/drivers/staging/ath6kl/os/linux/include/athdrv_linux.h
+++ b/drivers/staging/ath6kl/os/linux/include/athdrv_linux.h
@@ -620,7 +620,6 @@
*/
#define AR6000_XIOCTL_WMI_SET_TXOP 57
-#ifdef USER_KEYS
/*
* arguments:
* UINT32 cmd (AR6000_XIOCTL_USER_SETKEYS)
@@ -628,7 +627,6 @@
* uses struct ar6000_user_setkeys_info
*/
#define AR6000_XIOCTL_USER_SETKEYS 58
-#endif /* USER_KEYS */
#define AR6000_XIOCTL_WMI_SET_KEEPALIVE 59
/*
@@ -942,7 +940,7 @@
#define AR6000_XIOCTL_HCI_CMD 132
-#define AR6000_XIOCTL_ACL_DATA 133
+#define AR6000_XIOCTL_ACL_DATA 133 /* used to be used for PAL */
#define AR6000_XIOCTL_WLAN_CONN_PRECEDENCE 134
diff --git a/drivers/staging/ath6kl/os/linux/include/athtypes_linux.h b/drivers/staging/ath6kl/os/linux/include/athtypes_linux.h
deleted file mode 100644
index 8cb5632..0000000
--- a/drivers/staging/ath6kl/os/linux/include/athtypes_linux.h
+++ /dev/null
@@ -1,51 +0,0 @@
-//------------------------------------------------------------------------------
-//
-// This file contains the definitions of the basic atheros data types.
-// It is used to map the data types in atheros files to a platform specific
-// type.
-// Copyright (c) 2004-2010 Atheros Communications Inc.
-// All rights reserved.
-//
-//
-//
-// Permission to use, copy, modify, and/or distribute this software for any
-// purpose with or without fee is hereby granted, provided that the above
-// copyright notice and this permission notice appear in all copies.
-//
-// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-//
-//
-//
-// Author(s): ="Atheros"
-//------------------------------------------------------------------------------
-
-#ifndef _ATHTYPES_LINUX_H_
-#define _ATHTYPES_LINUX_H_
-
-#ifdef __KERNEL__
-#include <linux/types.h>
-#else
-#include <sys/types.h>
-#endif
-
-typedef int8_t A_INT8;
-typedef int16_t A_INT16;
-typedef int32_t A_INT32;
-typedef int64_t A_INT64;
-
-typedef u_int8_t A_UINT8;
-typedef u_int16_t A_UINT16;
-typedef u_int32_t A_UINT32;
-typedef u_int64_t A_UINT64;
-
-typedef char A_CHAR;
-typedef unsigned long A_ATH_TIMER;
-
-
-#endif /* _ATHTYPES_LINUX_H_ */
diff --git a/drivers/staging/ath6kl/os/linux/include/config_linux.h b/drivers/staging/ath6kl/os/linux/include/config_linux.h
index 50f53d3..d4030e2 100644
--- a/drivers/staging/ath6kl/os/linux/include/config_linux.h
+++ b/drivers/staging/ath6kl/os/linux/include/config_linux.h
@@ -31,13 +31,6 @@
#include <linux/version.h>
/*
- * Host-side GPIO support is optional.
- * If run-time access to GPIO pins is not required, then
- * this should be changed to #undef.
- */
-#define CONFIG_HOST_GPIO_SUPPORT
-
-/*
* Host side Test Command support
*/
#define CONFIG_HOST_TCMD_SUPPORT
diff --git a/drivers/staging/ath6kl/os/linux/include/osapi_linux.h b/drivers/staging/ath6kl/os/linux/include/osapi_linux.h
index 53b500c..07078b4 100644
--- a/drivers/staging/ath6kl/os/linux/include/osapi_linux.h
+++ b/drivers/staging/ath6kl/os/linux/include/osapi_linux.h
@@ -79,33 +79,10 @@
#define A_MEMZERO(addr, len) memset(addr, 0, len)
#define A_MALLOC(size) kmalloc((size), GFP_KERNEL)
#define A_MALLOC_NOWAIT(size) kmalloc((size), GFP_ATOMIC)
-#define A_FREE(addr) kfree(addr)
-#if defined(ANDROID_ENV) && defined(CONFIG_ANDROID_LOGGER)
-extern unsigned int enablelogcat;
-extern int android_logger_lv(void* module, int mask);
-enum logidx { LOG_MAIN_IDX = 0 };
-extern int logger_write(const enum logidx idx,
- const unsigned char prio,
- const char __kernel * const tag,
- const char __kernel * const fmt,
- ...);
-#define A_ANDROID_PRINTF(mask, module, tags, args...) do { \
- if (enablelogcat) \
- logger_write(LOG_MAIN_IDX, android_logger_lv(module, mask), tags, args); \
- else \
- printk(KERN_ALERT args); \
-} while (0)
-#ifdef DEBUG
-#define A_LOGGER_MODULE_NAME(x) #x
-#define A_LOGGER(mask, mod, args...) \
- A_ANDROID_PRINTF(mask, &GET_ATH_MODULE_DEBUG_VAR_NAME(mod), "ar6k_" A_LOGGER_MODULE_NAME(mod), args);
-#endif
-#define A_PRINTF(args...) A_ANDROID_PRINTF(ATH_DEBUG_INFO, NULL, "ar6k_driver", args)
-#else
#define A_LOGGER(mask, mod, args...) printk(KERN_ALERT args)
#define A_PRINTF(args...) printk(KERN_ALERT args)
-#endif /* ANDROID */
+
#define A_PRINTF_LOG(args...) printk(args)
#define A_SPRINTF(buf, args...) sprintf (buf, args)
@@ -211,17 +188,8 @@
#define A_ASSERT(expr)
#endif /* DEBUG */
-#ifdef ANDROID_ENV
-struct firmware;
-int android_request_firmware(const struct firmware **firmware_p, const char *filename,
- struct device *device);
-void android_release_firmware(const struct firmware *firmware);
-#define A_REQUEST_FIRMWARE(_ppf, _pfile, _dev) android_request_firmware(_ppf, _pfile, _dev)
-#define A_RELEASE_FIRMWARE(_pf) android_release_firmware(_pf)
-#else
#define A_REQUEST_FIRMWARE(_ppf, _pfile, _dev) request_firmware(_ppf, _pfile, _dev)
#define A_RELEASE_FIRMWARE(_pf) release_firmware(_pf)
-#endif
/*
* Initialization of the network buffer subsystem
@@ -364,19 +332,8 @@
#define A_MEMZERO(addr, len) memset((addr), 0, (len))
#define A_MALLOC(size) malloc(size)
-#define A_FREE(addr) free(addr)
-#ifdef ANDROID
-#ifndef err
-#include <errno.h>
-#define err(_s, args...) do { \
- fprintf(stderr, "%s: line %d ", __FILE__, __LINE__); \
- fprintf(stderr, args); fprintf(stderr, ": %d\n", errno); \
- exit(_s); } while (0)
-#endif
-#else
#include <err.h>
-#endif
#endif /* __KERNEL__ */
diff --git a/drivers/staging/ath6kl/os/linux/include/wlan_config.h b/drivers/staging/ath6kl/os/linux/include/wlan_config.h
index 2de5cef..c1fe0c6 100644
--- a/drivers/staging/ath6kl/os/linux/include/wlan_config.h
+++ b/drivers/staging/ath6kl/os/linux/include/wlan_config.h
@@ -56,11 +56,7 @@
* If the firmware successly roams within the disconnect timeout
* it sends a new connect event
*/
-#ifdef ANDROID_ENV
-#define WLAN_CONFIG_DISCONNECT_TIMEOUT 3
-#else
#define WLAN_CONFIG_DISCONNECT_TIMEOUT 10
-#endif /* ANDROID_ENV */
/*
* This configuration item disables 11n support.
@@ -109,10 +105,4 @@
*/
#define WLAN_CONFIG_DISABLE_TX_BURSTING 0
-/*
- * Platform specific function to power ON/OFF AR6000
- * and enable/disable SDIO card detection
- */
-#define plat_setup_power(on, detect)
-
#endif /* _HOST_WLAN_CONFIG_H_ */
diff --git a/drivers/staging/ath6kl/os/linux/include/wmi_filter_linux.h b/drivers/staging/ath6kl/os/linux/include/wmi_filter_linux.h
index d172625..1eb6f82 100644
--- a/drivers/staging/ath6kl/os/linux/include/wmi_filter_linux.h
+++ b/drivers/staging/ath6kl/os/linux/include/wmi_filter_linux.h
@@ -266,7 +266,7 @@
(0xFF), /* AR6000_XIOCTL_DELE_AGGR 130 */
(0xFF), /* AR6000_XIOCTL_FETCH_TARGET_REGS 131 */
(0xFF), /* AR6000_XIOCTL_HCI_CMD 132 */
-(0xFF), /* AR6000_XIOCTL_ACL_DATA 133 */
+(0xFF), /* AR6000_XIOCTL_ACL_DATA(used to be used for PAL) 133 */
(0xFF), /* AR6000_XIOCTL_WLAN_CONN_PRECEDENCE 134 */
(AP_NETWORK), /* AR6000_XIOCTL_AP_SET_11BG_RATESET 135 */
(0xFF),
diff --git a/drivers/staging/ath6kl/os/linux/ioctl.c b/drivers/staging/ath6kl/os/linux/ioctl.c
deleted file mode 100644
index 0daa201..0000000
--- a/drivers/staging/ath6kl/os/linux/ioctl.c
+++ /dev/null
@@ -1,4767 +0,0 @@
-//------------------------------------------------------------------------------
-// Copyright (c) 2004-2010 Atheros Communications Inc.
-// All rights reserved.
-//
-//
-//
-// Permission to use, copy, modify, and/or distribute this software for any
-// purpose with or without fee is hereby granted, provided that the above
-// copyright notice and this permission notice appear in all copies.
-//
-// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-//
-//
-//
-// Author(s): ="Atheros"
-//------------------------------------------------------------------------------
-
-#include "ar6000_drv.h"
-#include "ieee80211_ioctl.h"
-#include "ar6kap_common.h"
-#include "targaddrs.h"
-#include "a_hci.h"
-#include "wlan_config.h"
-
-extern int enablerssicompensation;
-u32 tcmdRxFreq;
-extern unsigned int wmitimeout;
-extern A_WAITQUEUE_HEAD arEvent;
-extern int tspecCompliance;
-extern int bmienable;
-extern int loghci;
-
-static int
-ar6000_ioctl_get_roam_tbl(struct net_device *dev, struct ifreq *rq)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
-
- if (ar->arWmiReady == false) {
- return -EIO;
- }
-
- if(wmi_get_roam_tbl_cmd(ar->arWmi) != 0) {
- return -EIO;
- }
-
- return 0;
-}
-
-static int
-ar6000_ioctl_get_roam_data(struct net_device *dev, struct ifreq *rq)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
-
- if (ar->arWmiReady == false) {
- return -EIO;
- }
-
-
- /* currently assume only roam times are required */
- if(wmi_get_roam_data_cmd(ar->arWmi, ROAM_DATA_TIME) != 0) {
- return -EIO;
- }
-
-
- return 0;
-}
-
-static int
-ar6000_ioctl_set_roam_ctrl(struct net_device *dev, char *userdata)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
- WMI_SET_ROAM_CTRL_CMD cmd;
- u8 size = sizeof(cmd);
-
- if (ar->arWmiReady == false) {
- return -EIO;
- }
-
-
- if (copy_from_user(&cmd, userdata, size)) {
- return -EFAULT;
- }
-
- if (cmd.roamCtrlType == WMI_SET_HOST_BIAS) {
- if (cmd.info.bssBiasInfo.numBss > 1) {
- size += (cmd.info.bssBiasInfo.numBss - 1) * sizeof(WMI_BSS_BIAS);
- }
- }
-
- if (copy_from_user(&cmd, userdata, size)) {
- return -EFAULT;
- }
-
- if(wmi_set_roam_ctrl_cmd(ar->arWmi, &cmd, size) != 0) {
- return -EIO;
- }
-
- return 0;
-}
-
-static int
-ar6000_ioctl_set_powersave_timers(struct net_device *dev, char *userdata)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
- WMI_POWERSAVE_TIMERS_POLICY_CMD cmd;
- u8 size = sizeof(cmd);
-
- if (ar->arWmiReady == false) {
- return -EIO;
- }
-
- if (copy_from_user(&cmd, userdata, size)) {
- return -EFAULT;
- }
-
- if (copy_from_user(&cmd, userdata, size)) {
- return -EFAULT;
- }
-
- if(wmi_set_powersave_timers_cmd(ar->arWmi, &cmd, size) != 0) {
- return -EIO;
- }
-
- return 0;
-}
-
-static int
-ar6000_ioctl_set_qos_supp(struct net_device *dev, struct ifreq *rq)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
- WMI_SET_QOS_SUPP_CMD cmd;
- int ret;
-
- if ((dev->flags & IFF_UP) != IFF_UP) {
- return -EIO;
- }
- if (ar->arWmiReady == false) {
- return -EIO;
- }
-
- if (copy_from_user(&cmd, (char *)((unsigned int*)rq->ifr_data + 1),
- sizeof(cmd)))
- {
- return -EFAULT;
- }
-
- ret = wmi_set_qos_supp_cmd(ar->arWmi, cmd.status);
-
- switch (ret) {
- case 0:
- return 0;
- case A_EBUSY :
- return -EBUSY;
- case A_NO_MEMORY:
- return -ENOMEM;
- case A_EINVAL:
- default:
- return -EFAULT;
- }
-}
-
-static int
-ar6000_ioctl_set_wmm(struct net_device *dev, struct ifreq *rq)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
- WMI_SET_WMM_CMD cmd;
- int ret;
-
- if ((dev->flags & IFF_UP) != IFF_UP) {
- return -EIO;
- }
- if (ar->arWmiReady == false) {
- return -EIO;
- }
-
- if (copy_from_user(&cmd, (char *)((unsigned int*)rq->ifr_data + 1),
- sizeof(cmd)))
- {
- return -EFAULT;
- }
-
- if (cmd.status == WMI_WMM_ENABLED) {
- ar->arWmmEnabled = true;
- } else {
- ar->arWmmEnabled = false;
- }
-
- ret = wmi_set_wmm_cmd(ar->arWmi, cmd.status);
-
- switch (ret) {
- case 0:
- return 0;
- case A_EBUSY :
- return -EBUSY;
- case A_NO_MEMORY:
- return -ENOMEM;
- case A_EINVAL:
- default:
- return -EFAULT;
- }
-}
-
-static int
-ar6000_ioctl_set_txop(struct net_device *dev, struct ifreq *rq)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
- WMI_SET_WMM_TXOP_CMD cmd;
- int ret;
-
- if ((dev->flags & IFF_UP) != IFF_UP) {
- return -EIO;
- }
- if (ar->arWmiReady == false) {
- return -EIO;
- }
-
- if (copy_from_user(&cmd, (char *)((unsigned int*)rq->ifr_data + 1),
- sizeof(cmd)))
- {
- return -EFAULT;
- }
-
- ret = wmi_set_wmm_txop(ar->arWmi, cmd.txopEnable);
-
- switch (ret) {
- case 0:
- return 0;
- case A_EBUSY :
- return -EBUSY;
- case A_NO_MEMORY:
- return -ENOMEM;
- case A_EINVAL:
- default:
- return -EFAULT;
- }
-}
-
-static int
-ar6000_ioctl_get_rd(struct net_device *dev, struct ifreq *rq)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
- int ret = 0;
-
- if ((dev->flags & IFF_UP) != IFF_UP || ar->arWmiReady == false) {
- return -EIO;
- }
-
- if(copy_to_user((char *)((unsigned int*)rq->ifr_data + 1),
- &ar->arRegCode, sizeof(ar->arRegCode)))
- ret = -EFAULT;
-
- return ret;
-}
-
-static int
-ar6000_ioctl_set_country(struct net_device *dev, struct ifreq *rq)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
- WMI_AP_SET_COUNTRY_CMD cmd;
- int ret;
-
- if ((dev->flags & IFF_UP) != IFF_UP) {
- return -EIO;
- }
- if (ar->arWmiReady == false) {
- return -EIO;
- }
-
- if (copy_from_user(&cmd, (char *)((unsigned int*)rq->ifr_data + 1),
- sizeof(cmd)))
- {
- return -EFAULT;
- }
-
- ar->ap_profile_flag = 1; /* There is a change in profile */
-
- ret = wmi_set_country(ar->arWmi, cmd.countryCode);
- memcpy(ar->ap_country_code, cmd.countryCode, 3);
-
- switch (ret) {
- case 0:
- return 0;
- case A_EBUSY :
- return -EBUSY;
- case A_NO_MEMORY:
- return -ENOMEM;
- case A_EINVAL:
- default:
- return -EFAULT;
- }
-}
-
-
-/* Get power mode command */
-static int
-ar6000_ioctl_get_power_mode(struct net_device *dev, struct ifreq *rq)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
- WMI_POWER_MODE_CMD power_mode;
- int ret = 0;
-
- if (ar->arWmiReady == false) {
- return -EIO;
- }
-
- power_mode.powerMode = wmi_get_power_mode_cmd(ar->arWmi);
- if (copy_to_user(rq->ifr_data, &power_mode, sizeof(WMI_POWER_MODE_CMD))) {
- ret = -EFAULT;
- }
-
- return ret;
-}
-
-
-static int
-ar6000_ioctl_set_channelParams(struct net_device *dev, struct ifreq *rq)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
- WMI_CHANNEL_PARAMS_CMD cmd, *cmdp;
- int ret = 0;
-
- if (ar->arWmiReady == false) {
- return -EIO;
- }
-
-
- if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
- return -EFAULT;
- }
-
- if( (ar->arNextMode == AP_NETWORK) && (cmd.numChannels || cmd.scanParam) ) {
- A_PRINTF("ERROR: Only wmode is allowed in AP mode\n");
- return -EIO;
- }
-
- if (cmd.numChannels > 1) {
- cmdp = A_MALLOC(130);
- if (copy_from_user(cmdp, rq->ifr_data,
- sizeof (*cmdp) +
- ((cmd.numChannels - 1) * sizeof(u16))))
- {
- kfree(cmdp);
- return -EFAULT;
- }
- } else {
- cmdp = &cmd;
- }
-
- if ((ar->arPhyCapability == WMI_11G_CAPABILITY) &&
- ((cmdp->phyMode == WMI_11A_MODE) || (cmdp->phyMode == WMI_11AG_MODE)))
- {
- ret = -EINVAL;
- }
-
- if (!ret &&
- (wmi_set_channelParams_cmd(ar->arWmi, cmdp->scanParam, cmdp->phyMode,
- cmdp->numChannels, cmdp->channelList)
- != 0))
- {
- ret = -EIO;
- }
-
- if (cmd.numChannels > 1) {
- kfree(cmdp);
- }
-
- ar->ap_wmode = cmdp->phyMode;
- /* Set the profile change flag to allow a commit cmd */
- ar->ap_profile_flag = 1;
-
- return ret;
-}
-
-
-static int
-ar6000_ioctl_set_snr_threshold(struct net_device *dev, struct ifreq *rq)
-{
-
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
- WMI_SNR_THRESHOLD_PARAMS_CMD cmd;
- int ret = 0;
-
- if (ar->arWmiReady == false) {
- return -EIO;
- }
-
- if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
- return -EFAULT;
- }
-
- if( wmi_set_snr_threshold_params(ar->arWmi, &cmd) != 0 ) {
- ret = -EIO;
- }
-
- return ret;
-}
-
-static int
-ar6000_ioctl_set_rssi_threshold(struct net_device *dev, struct ifreq *rq)
-{
-#define SWAP_THOLD(thold1, thold2) do { \
- USER_RSSI_THOLD tmpThold; \
- tmpThold.tag = thold1.tag; \
- tmpThold.rssi = thold1.rssi; \
- thold1.tag = thold2.tag; \
- thold1.rssi = thold2.rssi; \
- thold2.tag = tmpThold.tag; \
- thold2.rssi = tmpThold.rssi; \
-} while (0)
-
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
- WMI_RSSI_THRESHOLD_PARAMS_CMD cmd;
- USER_RSSI_PARAMS rssiParams;
- s32 i, j;
- int ret = 0;
-
- if (ar->arWmiReady == false) {
- return -EIO;
- }
-
- if (copy_from_user((char *)&rssiParams, (char *)((unsigned int *)rq->ifr_data + 1), sizeof(USER_RSSI_PARAMS))) {
- return -EFAULT;
- }
- cmd.weight = rssiParams.weight;
- cmd.pollTime = rssiParams.pollTime;
-
- memcpy(ar->rssi_map, &rssiParams.tholds, sizeof(ar->rssi_map));
- /*
- * only 6 elements, so use bubble sorting, in ascending order
- */
- for (i = 5; i > 0; i--) {
- for (j = 0; j < i; j++) { /* above tholds */
- if (ar->rssi_map[j+1].rssi < ar->rssi_map[j].rssi) {
- SWAP_THOLD(ar->rssi_map[j+1], ar->rssi_map[j]);
- } else if (ar->rssi_map[j+1].rssi == ar->rssi_map[j].rssi) {
- return -EFAULT;
- }
- }
- }
- for (i = 11; i > 6; i--) {
- for (j = 6; j < i; j++) { /* below tholds */
- if (ar->rssi_map[j+1].rssi < ar->rssi_map[j].rssi) {
- SWAP_THOLD(ar->rssi_map[j+1], ar->rssi_map[j]);
- } else if (ar->rssi_map[j+1].rssi == ar->rssi_map[j].rssi) {
- return -EFAULT;
- }
- }
- }
-
-#ifdef DEBUG
- for (i = 0; i < 12; i++) {
- AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("thold[%d].tag: %d, thold[%d].rssi: %d \n",
- i, ar->rssi_map[i].tag, i, ar->rssi_map[i].rssi));
- }
-#endif
-
- if (enablerssicompensation) {
- for (i = 0; i < 6; i++)
- ar->rssi_map[i].rssi = rssi_compensation_reverse_calc(ar, ar->rssi_map[i].rssi, true);
- for (i = 6; i < 12; i++)
- ar->rssi_map[i].rssi = rssi_compensation_reverse_calc(ar, ar->rssi_map[i].rssi, false);
- }
-
- cmd.thresholdAbove1_Val = ar->rssi_map[0].rssi;
- cmd.thresholdAbove2_Val = ar->rssi_map[1].rssi;
- cmd.thresholdAbove3_Val = ar->rssi_map[2].rssi;
- cmd.thresholdAbove4_Val = ar->rssi_map[3].rssi;
- cmd.thresholdAbove5_Val = ar->rssi_map[4].rssi;
- cmd.thresholdAbove6_Val = ar->rssi_map[5].rssi;
- cmd.thresholdBelow1_Val = ar->rssi_map[6].rssi;
- cmd.thresholdBelow2_Val = ar->rssi_map[7].rssi;
- cmd.thresholdBelow3_Val = ar->rssi_map[8].rssi;
- cmd.thresholdBelow4_Val = ar->rssi_map[9].rssi;
- cmd.thresholdBelow5_Val = ar->rssi_map[10].rssi;
- cmd.thresholdBelow6_Val = ar->rssi_map[11].rssi;
-
- if( wmi_set_rssi_threshold_params(ar->arWmi, &cmd) != 0 ) {
- ret = -EIO;
- }
-
- return ret;
-}
-
-static int
-ar6000_ioctl_set_lq_threshold(struct net_device *dev, struct ifreq *rq)
-{
-
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
- WMI_LQ_THRESHOLD_PARAMS_CMD cmd;
- int ret = 0;
-
- if (ar->arWmiReady == false) {
- return -EIO;
- }
-
- if (copy_from_user(&cmd, (char *)((unsigned int *)rq->ifr_data + 1), sizeof(cmd))) {
- return -EFAULT;
- }
-
- if( wmi_set_lq_threshold_params(ar->arWmi, &cmd) != 0 ) {
- ret = -EIO;
- }
-
- return ret;
-}
-
-
-static int
-ar6000_ioctl_set_probedSsid(struct net_device *dev, struct ifreq *rq)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
- WMI_PROBED_SSID_CMD cmd;
- int ret = 0;
-
- if (ar->arWmiReady == false) {
- return -EIO;
- }
-
- if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
- return -EFAULT;
- }
-
- if (wmi_probedSsid_cmd(ar->arWmi, cmd.entryIndex, cmd.flag, cmd.ssidLength,
- cmd.ssid) != 0)
- {
- ret = -EIO;
- }
-
- return ret;
-}
-
-static int
-ar6000_ioctl_set_badAp(struct net_device *dev, struct ifreq *rq)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
- WMI_ADD_BAD_AP_CMD cmd;
- int ret = 0;
-
- if (ar->arWmiReady == false) {
- return -EIO;
- }
-
-
- if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
- return -EFAULT;
- }
-
- if (cmd.badApIndex > WMI_MAX_BAD_AP_INDEX) {
- return -EIO;
- }
-
- if (memcmp(cmd.bssid, null_mac, AR6000_ETH_ADDR_LEN) == 0) {
- /*
- * This is a delete badAP.
- */
- if (wmi_deleteBadAp_cmd(ar->arWmi, cmd.badApIndex) != 0) {
- ret = -EIO;
- }
- } else {
- if (wmi_addBadAp_cmd(ar->arWmi, cmd.badApIndex, cmd.bssid) != 0) {
- ret = -EIO;
- }
- }
-
- return ret;
-}
-
-static int
-ar6000_ioctl_create_qos(struct net_device *dev, struct ifreq *rq)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
- WMI_CREATE_PSTREAM_CMD cmd;
- int ret;
-
- if (ar->arWmiReady == false) {
- return -EIO;
- }
-
-
- if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
- return -EFAULT;
- }
-
- ret = wmi_verify_tspec_params(&cmd, tspecCompliance);
- if (ret == 0)
- ret = wmi_create_pstream_cmd(ar->arWmi, &cmd);
-
- switch (ret) {
- case 0:
- return 0;
- case A_EBUSY :
- return -EBUSY;
- case A_NO_MEMORY:
- return -ENOMEM;
- case A_EINVAL:
- default:
- return -EFAULT;
- }
-}
-
-static int
-ar6000_ioctl_delete_qos(struct net_device *dev, struct ifreq *rq)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
- WMI_DELETE_PSTREAM_CMD cmd;
- int ret = 0;
-
- if (ar->arWmiReady == false) {
- return -EIO;
- }
-
- if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
- return -EFAULT;
- }
-
- ret = wmi_delete_pstream_cmd(ar->arWmi, cmd.trafficClass, cmd.tsid);
-
- switch (ret) {
- case 0:
- return 0;
- case A_EBUSY :
- return -EBUSY;
- case A_NO_MEMORY:
- return -ENOMEM;
- case A_EINVAL:
- default:
- return -EFAULT;
- }
-}
-
-static int
-ar6000_ioctl_get_qos_queue(struct net_device *dev, struct ifreq *rq)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
- struct ar6000_queuereq qreq;
- int ret = 0;
-
- if (ar->arWmiReady == false) {
- return -EIO;
- }
-
- if( copy_from_user(&qreq, rq->ifr_data,
- sizeof(struct ar6000_queuereq)))
- return -EFAULT;
-
- qreq.activeTsids = wmi_get_mapped_qos_queue(ar->arWmi, qreq.trafficClass);
-
- if (copy_to_user(rq->ifr_data, &qreq,
- sizeof(struct ar6000_queuereq)))
- {
- ret = -EFAULT;
- }
-
- return ret;
-}
-
-#ifdef CONFIG_HOST_TCMD_SUPPORT
-static int
-ar6000_ioctl_tcmd_get_rx_report(struct net_device *dev,
- struct ifreq *rq, u8 *data, u32 len)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
- u32 buf[4+TCMD_MAX_RATES];
- int ret = 0;
-
- if (ar->bIsDestroyProgress) {
- return -EBUSY;
- }
-
- if (ar->arWmiReady == false) {
- return -EIO;
- }
-
- if (down_interruptible(&ar->arSem)) {
- return -ERESTARTSYS;
- }
-
- if (ar->bIsDestroyProgress) {
- up(&ar->arSem);
- return -EBUSY;
- }
-
- ar->tcmdRxReport = 0;
- if (wmi_test_cmd(ar->arWmi, data, len) != 0) {
- up(&ar->arSem);
- return -EIO;
- }
-
- wait_event_interruptible_timeout(arEvent, ar->tcmdRxReport != 0, wmitimeout * HZ);
-
- if (signal_pending(current)) {
- ret = -EINTR;
- }
-
- buf[0] = ar->tcmdRxTotalPkt;
- buf[1] = ar->tcmdRxRssi;
- buf[2] = ar->tcmdRxcrcErrPkt;
- buf[3] = ar->tcmdRxsecErrPkt;
- memcpy(((u8 *)buf)+(4*sizeof(u32)), ar->tcmdRateCnt, sizeof(ar->tcmdRateCnt));
- memcpy(((u8 *)buf)+(4*sizeof(u32))+(TCMD_MAX_RATES *sizeof(u16)), ar->tcmdRateCntShortGuard, sizeof(ar->tcmdRateCntShortGuard));
-
- if (!ret && copy_to_user(rq->ifr_data, buf, sizeof(buf))) {
- ret = -EFAULT;
- }
-
- up(&ar->arSem);
-
- return ret;
-}
-
-void
-ar6000_tcmd_rx_report_event(void *devt, u8 *results, int len)
-{
- struct ar6_softc *ar = (struct ar6_softc *)devt;
- TCMD_CONT_RX * rx_rep = (TCMD_CONT_RX *)results;
-
- if (enablerssicompensation) {
- rx_rep->u.report.rssiInDBm = rssi_compensation_calc_tcmd(tcmdRxFreq, rx_rep->u.report.rssiInDBm,rx_rep->u.report.totalPkt);
- }
-
-
- ar->tcmdRxTotalPkt = rx_rep->u.report.totalPkt;
- ar->tcmdRxRssi = rx_rep->u.report.rssiInDBm;
- ar->tcmdRxcrcErrPkt = rx_rep->u.report.crcErrPkt;
- ar->tcmdRxsecErrPkt = rx_rep->u.report.secErrPkt;
- ar->tcmdRxReport = 1;
- A_MEMZERO(ar->tcmdRateCnt, sizeof(ar->tcmdRateCnt));
- A_MEMZERO(ar->tcmdRateCntShortGuard, sizeof(ar->tcmdRateCntShortGuard));
- memcpy(ar->tcmdRateCnt, rx_rep->u.report.rateCnt, sizeof(ar->tcmdRateCnt));
- memcpy(ar->tcmdRateCntShortGuard, rx_rep->u.report.rateCntShortGuard, sizeof(ar->tcmdRateCntShortGuard));
-
- wake_up(&arEvent);
-}
-#endif /* CONFIG_HOST_TCMD_SUPPORT*/
-
-static int
-ar6000_ioctl_set_error_report_bitmask(struct net_device *dev, struct ifreq *rq)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
- WMI_TARGET_ERROR_REPORT_BITMASK cmd;
- int ret = 0;
-
- if (ar->arWmiReady == false) {
- return -EIO;
- }
-
- if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
- return -EFAULT;
- }
-
- ret = wmi_set_error_report_bitmask(ar->arWmi, cmd.bitmask);
-
- return (ret==0 ? ret : -EINVAL);
-}
-
-static int
-ar6000_clear_target_stats(struct net_device *dev)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
- TARGET_STATS *pStats = &ar->arTargetStats;
- int ret = 0;
-
- if (ar->arWmiReady == false) {
- return -EIO;
- }
- AR6000_SPIN_LOCK(&ar->arLock, 0);
- A_MEMZERO(pStats, sizeof(TARGET_STATS));
- AR6000_SPIN_UNLOCK(&ar->arLock, 0);
- return ret;
-}
-
-static int
-ar6000_ioctl_get_target_stats(struct net_device *dev, struct ifreq *rq)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
- TARGET_STATS_CMD cmd;
- TARGET_STATS *pStats = &ar->arTargetStats;
- int ret = 0;
-
- if (ar->bIsDestroyProgress) {
- return -EBUSY;
- }
- if (ar->arWmiReady == false) {
- return -EIO;
- }
- if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
- return -EFAULT;
- }
- if (down_interruptible(&ar->arSem)) {
- return -ERESTARTSYS;
- }
- if (ar->bIsDestroyProgress) {
- up(&ar->arSem);
- return -EBUSY;
- }
-
- ar->statsUpdatePending = true;
-
- if(wmi_get_stats_cmd(ar->arWmi) != 0) {
- up(&ar->arSem);
- return -EIO;
- }
-
- wait_event_interruptible_timeout(arEvent, ar->statsUpdatePending == false, wmitimeout * HZ);
-
- if (signal_pending(current)) {
- ret = -EINTR;
- }
-
- if (!ret && copy_to_user(rq->ifr_data, pStats, sizeof(*pStats))) {
- ret = -EFAULT;
- }
-
- if (cmd.clearStats == 1) {
- ret = ar6000_clear_target_stats(dev);
- }
-
- up(&ar->arSem);
-
- return ret;
-}
-
-static int
-ar6000_ioctl_get_ap_stats(struct net_device *dev, struct ifreq *rq)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
- u32 action; /* Allocating only the desired space on the frame. Declaring is as a WMI_AP_MODE_STAT variable results in exceeding the compiler imposed limit on the maximum frame size */
- WMI_AP_MODE_STAT *pStats = &ar->arAPStats;
- int ret = 0;
-
- if (ar->arWmiReady == false) {
- return -EIO;
- }
- if (copy_from_user(&action, (char *)((unsigned int*)rq->ifr_data + 1),
- sizeof(u32)))
- {
- return -EFAULT;
- }
- if (action == AP_CLEAR_STATS) {
- u8 i;
- AR6000_SPIN_LOCK(&ar->arLock, 0);
- for(i = 0; i < AP_MAX_NUM_STA; i++) {
- pStats->sta[i].tx_bytes = 0;
- pStats->sta[i].tx_pkts = 0;
- pStats->sta[i].tx_error = 0;
- pStats->sta[i].tx_discard = 0;
- pStats->sta[i].rx_bytes = 0;
- pStats->sta[i].rx_pkts = 0;
- pStats->sta[i].rx_error = 0;
- pStats->sta[i].rx_discard = 0;
- }
- AR6000_SPIN_UNLOCK(&ar->arLock, 0);
- return ret;
- }
-
- if (down_interruptible(&ar->arSem)) {
- return -ERESTARTSYS;
- }
-
- ar->statsUpdatePending = true;
-
- if(wmi_get_stats_cmd(ar->arWmi) != 0) {
- up(&ar->arSem);
- return -EIO;
- }
-
- wait_event_interruptible_timeout(arEvent, ar->statsUpdatePending == false, wmitimeout * HZ);
-
- if (signal_pending(current)) {
- ret = -EINTR;
- }
-
- if (!ret && copy_to_user(rq->ifr_data, pStats, sizeof(*pStats))) {
- ret = -EFAULT;
- }
-
- up(&ar->arSem);
-
- return ret;
-}
-
-static int
-ar6000_ioctl_set_access_params(struct net_device *dev, struct ifreq *rq)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
- WMI_SET_ACCESS_PARAMS_CMD cmd;
- int ret = 0;
-
- if (ar->arWmiReady == false) {
- return -EIO;
- }
-
- if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
- return -EFAULT;
- }
-
- if (wmi_set_access_params_cmd(ar->arWmi, cmd.ac, cmd.txop, cmd.eCWmin, cmd.eCWmax,
- cmd.aifsn) == 0)
- {
- ret = 0;
- } else {
- ret = -EINVAL;
- }
-
- return (ret);
-}
-
-static int
-ar6000_ioctl_set_disconnect_timeout(struct net_device *dev, struct ifreq *rq)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
- WMI_DISC_TIMEOUT_CMD cmd;
- int ret = 0;
-
- if (ar->arWmiReady == false) {
- return -EIO;
- }
-
- if (copy_from_user(&cmd, rq->ifr_data, sizeof(cmd))) {
- return -EFAULT;
- }
-
- if (wmi_disctimeout_cmd(ar->arWmi, cmd.disconnectTimeout) == 0)
- {
- ret = 0;
- } else {
- ret = -EINVAL;
- }
-
- return (ret);
-}
-
-static int
-ar6000_xioctl_set_voice_pkt_size(struct net_device *dev, char *userdata)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
- WMI_SET_VOICE_PKT_SIZE_CMD cmd;
- int ret = 0;
-
- if (ar->arWmiReady == false) {
- return -EIO;
- }
-
- if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
- return -EFAULT;
- }
-
- if (wmi_set_voice_pkt_size_cmd(ar->arWmi, cmd.voicePktSize) == 0)
- {
- ret = 0;
- } else {
- ret = -EINVAL;
- }
-
-
- return (ret);
-}
-
-static int
-ar6000_xioctl_set_max_sp_len(struct net_device *dev, char *userdata)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
- WMI_SET_MAX_SP_LEN_CMD cmd;
- int ret = 0;
-
- if (ar->arWmiReady == false) {
- return -EIO;
- }
-
- if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
- return -EFAULT;
- }
-
- if (wmi_set_max_sp_len_cmd(ar->arWmi, cmd.maxSPLen) == 0)
- {
- ret = 0;
- } else {
- ret = -EINVAL;
- }
-
- return (ret);
-}
-
-
-static int
-ar6000_xioctl_set_bt_status_cmd(struct net_device *dev, char *userdata)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
- WMI_SET_BT_STATUS_CMD cmd;
- int ret = 0;
-
- if (ar->arWmiReady == false) {
- return -EIO;
- }
-
- if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
- return -EFAULT;
- }
-
- if (wmi_set_bt_status_cmd(ar->arWmi, cmd.streamType, cmd.status) == 0)
- {
- ret = 0;
- } else {
- ret = -EINVAL;
- }
-
- return (ret);
-}
-
-static int
-ar6000_xioctl_set_bt_params_cmd(struct net_device *dev, char *userdata)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
- WMI_SET_BT_PARAMS_CMD cmd;
- int ret = 0;
-
- if (ar->arWmiReady == false) {
- return -EIO;
- }
-
- if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
- return -EFAULT;
- }
-
- if (wmi_set_bt_params_cmd(ar->arWmi, &cmd) == 0)
- {
- ret = 0;
- } else {
- ret = -EINVAL;
- }
-
- return (ret);
-}
-
-static int
-ar6000_xioctl_set_btcoex_fe_ant_cmd(struct net_device * dev, char *userdata)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
- WMI_SET_BTCOEX_FE_ANT_CMD cmd;
- int ret = 0;
-
- if (ar->arWmiReady == false) {
- return -EIO;
- }
- if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
- return -EFAULT;
- }
-
- if (wmi_set_btcoex_fe_ant_cmd(ar->arWmi, &cmd) == 0)
- {
- ret = 0;
- } else {
- ret = -EINVAL;
- }
-
- return(ret);
-}
-
-static int
-ar6000_xioctl_set_btcoex_colocated_bt_dev_cmd(struct net_device * dev, char *userdata)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
- WMI_SET_BTCOEX_COLOCATED_BT_DEV_CMD cmd;
- int ret = 0;
-
- if (ar->arWmiReady == false) {
- return -EIO;
- }
-
- if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
- return -EFAULT;
- }
-
- if (wmi_set_btcoex_colocated_bt_dev_cmd(ar->arWmi, &cmd) == 0)
- {
- ret = 0;
- } else {
- ret = -EINVAL;
- }
-
- return(ret);
-}
-
-static int
-ar6000_xioctl_set_btcoex_btinquiry_page_config_cmd(struct net_device * dev, char *userdata)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
- WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG_CMD cmd;
- int ret = 0;
-
- if (ar->arWmiReady == false) {
- return -EIO;
- }
-
- if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
- return -EFAULT;
- }
-
- if (wmi_set_btcoex_btinquiry_page_config_cmd(ar->arWmi, &cmd) == 0)
- {
- ret = 0;
- } else {
- ret = -EINVAL;
- }
-
- return(ret);
-}
-
-static int
-ar6000_xioctl_set_btcoex_sco_config_cmd(struct net_device * dev, char *userdata)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
- WMI_SET_BTCOEX_SCO_CONFIG_CMD cmd;
- int ret = 0;
-
- if (ar->arWmiReady == false) {
- return -EIO;
- }
-
- if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
- return -EFAULT;
- }
-
- if (wmi_set_btcoex_sco_config_cmd(ar->arWmi, &cmd) == 0)
- {
- ret = 0;
- } else {
- ret = -EINVAL;
- }
-
- return(ret);
-}
-
-static int
-ar6000_xioctl_set_btcoex_a2dp_config_cmd(struct net_device * dev,
- char *userdata)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
- WMI_SET_BTCOEX_A2DP_CONFIG_CMD cmd;
- int ret = 0;
-
- if (ar->arWmiReady == false) {
- return -EIO;
- }
-
- if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
- return -EFAULT;
- }
-
- if (wmi_set_btcoex_a2dp_config_cmd(ar->arWmi, &cmd) == 0)
- {
- ret = 0;
- } else {
- ret = -EINVAL;
- }
-
- return(ret);
-}
-
-static int
-ar6000_xioctl_set_btcoex_aclcoex_config_cmd(struct net_device * dev, char *userdata)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
- WMI_SET_BTCOEX_ACLCOEX_CONFIG_CMD cmd;
- int ret = 0;
-
- if (ar->arWmiReady == false) {
- return -EIO;
- }
-
- if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
- return -EFAULT;
- }
-
- if (wmi_set_btcoex_aclcoex_config_cmd(ar->arWmi, &cmd) == 0)
- {
- ret = 0;
- } else {
- ret = -EINVAL;
- }
-
- return(ret);
-}
-
-static int
-ar60000_xioctl_set_btcoex_debug_cmd(struct net_device * dev, char *userdata)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
- WMI_SET_BTCOEX_DEBUG_CMD cmd;
- int ret = 0;
-
- if (ar->arWmiReady == false) {
- return -EIO;
- }
-
- if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
- return -EFAULT;
- }
-
- if (wmi_set_btcoex_debug_cmd(ar->arWmi, &cmd) == 0)
- {
- ret = 0;
- } else {
- ret = -EINVAL;
- }
-
- return(ret);
-}
-
-static int
-ar6000_xioctl_set_btcoex_bt_operating_status_cmd(struct net_device * dev, char *userdata)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
- WMI_SET_BTCOEX_BT_OPERATING_STATUS_CMD cmd;
- int ret = 0;
-
- if (ar->arWmiReady == false) {
- return -EIO;
- }
-
- if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
- return -EFAULT;
- }
-
- if (wmi_set_btcoex_bt_operating_status_cmd(ar->arWmi, &cmd) == 0)
- {
- ret = 0;
- } else {
- ret = -EINVAL;
- }
- return(ret);
-}
-
-static int
-ar6000_xioctl_get_btcoex_config_cmd(struct net_device * dev, char *userdata,
- struct ifreq *rq)
-{
-
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
- AR6000_BTCOEX_CONFIG btcoexConfig;
- WMI_BTCOEX_CONFIG_EVENT *pbtcoexConfigEv = &ar->arBtcoexConfig;
-
- int ret = 0;
-
- if (ar->bIsDestroyProgress) {
- return -EBUSY;
- }
- if (ar->arWmiReady == false) {
- return -EIO;
- }
- if (copy_from_user(&btcoexConfig.configCmd, userdata, sizeof(AR6000_BTCOEX_CONFIG))) {
- return -EFAULT;
- }
- if (down_interruptible(&ar->arSem)) {
- return -ERESTARTSYS;
- }
-
- if (wmi_get_btcoex_config_cmd(ar->arWmi, (WMI_GET_BTCOEX_CONFIG_CMD *)&btcoexConfig.configCmd) != 0)
- {
- up(&ar->arSem);
- return -EIO;
- }
-
- ar->statsUpdatePending = true;
-
- wait_event_interruptible_timeout(arEvent, ar->statsUpdatePending == false, wmitimeout * HZ);
-
- if (signal_pending(current)) {
- ret = -EINTR;
- }
-
- if (!ret && copy_to_user(btcoexConfig.configEvent, pbtcoexConfigEv, sizeof(WMI_BTCOEX_CONFIG_EVENT))) {
- ret = -EFAULT;
- }
- up(&ar->arSem);
- return ret;
-}
-
-static int
-ar6000_xioctl_get_btcoex_stats_cmd(struct net_device * dev, char *userdata, struct ifreq *rq)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
- AR6000_BTCOEX_STATS btcoexStats;
- WMI_BTCOEX_STATS_EVENT *pbtcoexStats = &ar->arBtcoexStats;
- int ret = 0;
-
- if (ar->bIsDestroyProgress) {
- return -EBUSY;
- }
- if (ar->arWmiReady == false) {
- return -EIO;
- }
-
- if (down_interruptible(&ar->arSem)) {
- return -ERESTARTSYS;
- }
-
- if (copy_from_user(&btcoexStats.statsEvent, userdata, sizeof(AR6000_BTCOEX_CONFIG))) {
- return -EFAULT;
- }
-
- if (wmi_get_btcoex_stats_cmd(ar->arWmi) != 0)
- {
- up(&ar->arSem);
- return -EIO;
- }
-
- ar->statsUpdatePending = true;
-
- wait_event_interruptible_timeout(arEvent, ar->statsUpdatePending == false, wmitimeout * HZ);
-
- if (signal_pending(current)) {
- ret = -EINTR;
- }
-
- if (!ret && copy_to_user(btcoexStats.statsEvent, pbtcoexStats, sizeof(WMI_BTCOEX_STATS_EVENT))) {
- ret = -EFAULT;
- }
-
-
- up(&ar->arSem);
-
- return(ret);
-}
-
-static int
-ar6000_xioctl_set_excess_tx_retry_thres_cmd(struct net_device * dev, char * userdata)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
- WMI_SET_EXCESS_TX_RETRY_THRES_CMD cmd;
- int ret = 0;
-
- if (ar->arWmiReady == false) {
- return -EIO;
- }
-
- if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
- return -EFAULT;
- }
-
- if (wmi_set_excess_tx_retry_thres_cmd(ar->arWmi, &cmd) != 0)
- {
- ret = -EINVAL;
- }
- return(ret);
-}
-
-#ifdef CONFIG_HOST_GPIO_SUPPORT
-struct ar6000_gpio_intr_wait_cmd_s gpio_intr_results;
-/* gpio_reg_results and gpio_data_available are protected by arSem */
-static struct ar6000_gpio_register_cmd_s gpio_reg_results;
-static bool gpio_data_available; /* Requested GPIO data available */
-static bool gpio_intr_available; /* GPIO interrupt info available */
-static bool gpio_ack_received; /* GPIO ack was received */
-
-/* Host-side initialization for General Purpose I/O support */
-void ar6000_gpio_init(void)
-{
- gpio_intr_available = false;
- gpio_data_available = false;
- gpio_ack_received = false;
-}
-
-/*
- * Called when a GPIO interrupt is received from the Target.
- * intr_values shows which GPIO pins have interrupted.
- * input_values shows a recent value of GPIO pins.
- */
-void
-ar6000_gpio_intr_rx(u32 intr_mask, u32 input_values)
-{
- gpio_intr_results.intr_mask = intr_mask;
- gpio_intr_results.input_values = input_values;
- *((volatile bool *)&gpio_intr_available) = true;
- wake_up(&arEvent);
-}
-
-/*
- * This is called when a response is received from the Target
- * for a previous or ar6000_gpio_input_get or ar6000_gpio_register_get
- * call.
- */
-void
-ar6000_gpio_data_rx(u32 reg_id, u32 value)
-{
- gpio_reg_results.gpioreg_id = reg_id;
- gpio_reg_results.value = value;
- *((volatile bool *)&gpio_data_available) = true;
- wake_up(&arEvent);
-}
-
-/*
- * This is called when an acknowledgement is received from the Target
- * for a previous or ar6000_gpio_output_set or ar6000_gpio_register_set
- * call.
- */
-void
-ar6000_gpio_ack_rx(void)
-{
- gpio_ack_received = true;
- wake_up(&arEvent);
-}
-
-int
-ar6000_gpio_output_set(struct net_device *dev,
- u32 set_mask,
- u32 clear_mask,
- u32 enable_mask,
- u32 disable_mask)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
-
- gpio_ack_received = false;
- return wmi_gpio_output_set(ar->arWmi,
- set_mask, clear_mask, enable_mask, disable_mask);
-}
-
-static int
-ar6000_gpio_input_get(struct net_device *dev)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
-
- *((volatile bool *)&gpio_data_available) = false;
- return wmi_gpio_input_get(ar->arWmi);
-}
-
-static int
-ar6000_gpio_register_set(struct net_device *dev,
- u32 gpioreg_id,
- u32 value)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
-
- gpio_ack_received = false;
- return wmi_gpio_register_set(ar->arWmi, gpioreg_id, value);
-}
-
-static int
-ar6000_gpio_register_get(struct net_device *dev,
- u32 gpioreg_id)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
-
- *((volatile bool *)&gpio_data_available) = false;
- return wmi_gpio_register_get(ar->arWmi, gpioreg_id);
-}
-
-static int
-ar6000_gpio_intr_ack(struct net_device *dev,
- u32 ack_mask)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
-
- gpio_intr_available = false;
- return wmi_gpio_intr_ack(ar->arWmi, ack_mask);
-}
-#endif /* CONFIG_HOST_GPIO_SUPPORT */
-
-#if defined(CONFIG_TARGET_PROFILE_SUPPORT)
-static struct prof_count_s prof_count_results;
-static bool prof_count_available; /* Requested GPIO data available */
-
-static int
-prof_count_get(struct net_device *dev)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
-
- *((volatile bool *)&prof_count_available) = false;
- return wmi_prof_count_get_cmd(ar->arWmi);
-}
-
-/*
- * This is called when a response is received from the Target
- * for a previous prof_count_get call.
- */
-void
-prof_count_rx(u32 addr, u32 count)
-{
- prof_count_results.addr = addr;
- prof_count_results.count = count;
- *((volatile bool *)&prof_count_available) = true;
- wake_up(&arEvent);
-}
-#endif /* CONFIG_TARGET_PROFILE_SUPPORT */
-
-
-static int
-ar6000_create_acl_data_osbuf(struct net_device *dev, u8 *userdata, void **p_osbuf)
-{
- void *osbuf = NULL;
- u8 tmp_space[8];
- HCI_ACL_DATA_PKT *acl;
- u8 hdr_size, *datap=NULL;
- int ret = 0;
-
- /* ACL is in data path. There is a need to create pool
- * mechanism for allocating and freeing NETBUFs - ToDo later.
- */
-
- *p_osbuf = NULL;
- acl = (HCI_ACL_DATA_PKT *)tmp_space;
- hdr_size = sizeof(acl->hdl_and_flags) + sizeof(acl->data_len);
-
- do {
- if (a_copy_from_user(acl, userdata, hdr_size)) {
- ret = A_EFAULT;
- break;
- }
-
- osbuf = A_NETBUF_ALLOC(hdr_size + acl->data_len);
- if (osbuf == NULL) {
- ret = A_NO_MEMORY;
- break;
- }
- A_NETBUF_PUT(osbuf, hdr_size + acl->data_len);
- datap = (u8 *)A_NETBUF_DATA(osbuf);
-
- /* Real copy to osbuf */
- acl = (HCI_ACL_DATA_PKT *)(datap);
- memcpy(acl, tmp_space, hdr_size);
- if (a_copy_from_user(acl->data, userdata + hdr_size, acl->data_len)) {
- ret = A_EFAULT;
- break;
- }
- } while(false);
-
- if (ret == 0) {
- *p_osbuf = osbuf;
- } else {
- A_NETBUF_FREE(osbuf);
- }
- return ret;
-}
-
-
-
-int
-ar6000_ioctl_ap_setparam(struct ar6_softc *ar, int param, int value)
-{
- int ret=0;
-
- switch(param) {
- case IEEE80211_PARAM_WPA:
- switch (value) {
- case WPA_MODE_WPA1:
- ar->arAuthMode = WPA_AUTH;
- break;
- case WPA_MODE_WPA2:
- ar->arAuthMode = WPA2_AUTH;
- break;
- case WPA_MODE_AUTO:
- ar->arAuthMode = WPA_AUTH | WPA2_AUTH;
- break;
- case WPA_MODE_NONE:
- ar->arAuthMode = NONE_AUTH;
- break;
- }
- break;
- case IEEE80211_PARAM_AUTHMODE:
- if(value == IEEE80211_AUTH_WPA_PSK) {
- if (WPA_AUTH == ar->arAuthMode) {
- ar->arAuthMode = WPA_PSK_AUTH;
- } else if (WPA2_AUTH == ar->arAuthMode) {
- ar->arAuthMode = WPA2_PSK_AUTH;
- } else if ((WPA_AUTH | WPA2_AUTH) == ar->arAuthMode) {
- ar->arAuthMode = WPA_PSK_AUTH | WPA2_PSK_AUTH;
- } else {
- AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Error - Setting PSK "\
- "mode when WPA param was set to %d\n",
- ar->arAuthMode));
- ret = -EIO;
- }
- }
- break;
- case IEEE80211_PARAM_UCASTCIPHER:
- ar->arPairwiseCrypto = 0;
- if(value & (1<<IEEE80211_CIPHER_AES_CCM)) {
- ar->arPairwiseCrypto |= AES_CRYPT;
- }
- if(value & (1<<IEEE80211_CIPHER_TKIP)) {
- ar->arPairwiseCrypto |= TKIP_CRYPT;
- }
- if(!ar->arPairwiseCrypto) {
- AR_DEBUG_PRINTF(ATH_DEBUG_ERR,
- ("Error - Invalid cipher in WPA \n"));
- ret = -EIO;
- }
- break;
- case IEEE80211_PARAM_PRIVACY:
- if(value == 0) {
- ar->arDot11AuthMode = OPEN_AUTH;
- ar->arAuthMode = NONE_AUTH;
- ar->arPairwiseCrypto = NONE_CRYPT;
- ar->arPairwiseCryptoLen = 0;
- ar->arGroupCrypto = NONE_CRYPT;
- ar->arGroupCryptoLen = 0;
- }
- break;
-#ifdef WAPI_ENABLE
- case IEEE80211_PARAM_WAPI:
- A_PRINTF("WAPI Policy: %d\n", value);
- ar->arDot11AuthMode = OPEN_AUTH;
- ar->arAuthMode = NONE_AUTH;
- if(value & 0x1) {
- ar->arPairwiseCrypto = WAPI_CRYPT;
- ar->arGroupCrypto = WAPI_CRYPT;
- } else {
- ar->arPairwiseCrypto = NONE_CRYPT;
- ar->arGroupCrypto = NONE_CRYPT;
- }
- break;
-#endif
- }
- return ret;
-}
-
-int
-ar6000_ioctl_setparam(struct ar6_softc *ar, int param, int value)
-{
- bool profChanged = false;
- int ret=0;
-
- if(ar->arNextMode == AP_NETWORK) {
- ar->ap_profile_flag = 1; /* There is a change in profile */
- switch (param) {
- case IEEE80211_PARAM_WPA:
- case IEEE80211_PARAM_AUTHMODE:
- case IEEE80211_PARAM_UCASTCIPHER:
- case IEEE80211_PARAM_PRIVACY:
- case IEEE80211_PARAM_WAPI:
- ret = ar6000_ioctl_ap_setparam(ar, param, value);
- return ret;
- }
- }
-
- switch (param) {
- case IEEE80211_PARAM_WPA:
- switch (value) {
- case WPA_MODE_WPA1:
- ar->arAuthMode = WPA_AUTH;
- profChanged = true;
- break;
- case WPA_MODE_WPA2:
- ar->arAuthMode = WPA2_AUTH;
- profChanged = true;
- break;
- case WPA_MODE_NONE:
- ar->arAuthMode = NONE_AUTH;
- profChanged = true;
- break;
- }
- break;
- case IEEE80211_PARAM_AUTHMODE:
- switch(value) {
- case IEEE80211_AUTH_WPA_PSK:
- if (WPA_AUTH == ar->arAuthMode) {
- ar->arAuthMode = WPA_PSK_AUTH;
- profChanged = true;
- } else if (WPA2_AUTH == ar->arAuthMode) {
- ar->arAuthMode = WPA2_PSK_AUTH;
- profChanged = true;
- } else {
- AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("Error - Setting PSK "\
- "mode when WPA param was set to %d\n",
- ar->arAuthMode));
- ret = -EIO;
- }
- break;
- case IEEE80211_AUTH_WPA_CCKM:
- if (WPA2_AUTH == ar->arAuthMode) {
- ar->arAuthMode = WPA2_AUTH_CCKM;
- } else {
- ar->arAuthMode = WPA_AUTH_CCKM;
- }
- break;
- default:
- break;
- }
- break;
- case IEEE80211_PARAM_UCASTCIPHER:
- switch (value) {
- case IEEE80211_CIPHER_AES_CCM:
- ar->arPairwiseCrypto = AES_CRYPT;
- profChanged = true;
- break;
- case IEEE80211_CIPHER_TKIP:
- ar->arPairwiseCrypto = TKIP_CRYPT;
- profChanged = true;
- break;
- case IEEE80211_CIPHER_WEP:
- ar->arPairwiseCrypto = WEP_CRYPT;
- profChanged = true;
- break;
- case IEEE80211_CIPHER_NONE:
- ar->arPairwiseCrypto = NONE_CRYPT;
- profChanged = true;
- break;
- }
- break;
- case IEEE80211_PARAM_UCASTKEYLEN:
- if (!IEEE80211_IS_VALID_WEP_CIPHER_LEN(value)) {
- ret = -EIO;
- } else {
- ar->arPairwiseCryptoLen = value;
- }
- break;
- case IEEE80211_PARAM_MCASTCIPHER:
- switch (value) {
- case IEEE80211_CIPHER_AES_CCM:
- ar->arGroupCrypto = AES_CRYPT;
- profChanged = true;
- break;
- case IEEE80211_CIPHER_TKIP:
- ar->arGroupCrypto = TKIP_CRYPT;
- profChanged = true;
- break;
- case IEEE80211_CIPHER_WEP:
- ar->arGroupCrypto = WEP_CRYPT;
- profChanged = true;
- break;
- case IEEE80211_CIPHER_NONE:
- ar->arGroupCrypto = NONE_CRYPT;
- profChanged = true;
- break;
- }
- break;
- case IEEE80211_PARAM_MCASTKEYLEN:
- if (!IEEE80211_IS_VALID_WEP_CIPHER_LEN(value)) {
- ret = -EIO;
- } else {
- ar->arGroupCryptoLen = value;
- }
- break;
- case IEEE80211_PARAM_COUNTERMEASURES:
- if (ar->arWmiReady == false) {
- return -EIO;
- }
- wmi_set_tkip_countermeasures_cmd(ar->arWmi, value);
- break;
- default:
- break;
- }
- if ((ar->arNextMode != AP_NETWORK) && (profChanged == true)) {
- /*
- * profile has changed. Erase ssid to signal change
- */
- A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
- }
-
- return ret;
-}
-
-int
-ar6000_ioctl_setkey(struct ar6_softc *ar, struct ieee80211req_key *ik)
-{
- KEY_USAGE keyUsage;
- int status;
- CRYPTO_TYPE keyType = NONE_CRYPT;
-
-#ifdef USER_KEYS
- ar->user_saved_keys.keyOk = false;
-#endif
- if ( (0 == memcmp(ik->ik_macaddr, null_mac, IEEE80211_ADDR_LEN)) ||
- (0 == memcmp(ik->ik_macaddr, bcast_mac, IEEE80211_ADDR_LEN)) ) {
- keyUsage = GROUP_USAGE;
- if(ar->arNextMode == AP_NETWORK) {
- memcpy(&ar->ap_mode_bkey, ik,
- sizeof(struct ieee80211req_key));
-#ifdef WAPI_ENABLE
- if(ar->arPairwiseCrypto == WAPI_CRYPT) {
- return ap_set_wapi_key(ar, ik);
- }
-#endif
- }
-#ifdef USER_KEYS
- memcpy(&ar->user_saved_keys.bcast_ik, ik,
- sizeof(struct ieee80211req_key));
-#endif
- } else {
- keyUsage = PAIRWISE_USAGE;
-#ifdef USER_KEYS
- memcpy(&ar->user_saved_keys.ucast_ik, ik,
- sizeof(struct ieee80211req_key));
-#endif
-#ifdef WAPI_ENABLE
- if(ar->arNextMode == AP_NETWORK) {
- if(ar->arPairwiseCrypto == WAPI_CRYPT) {
- return ap_set_wapi_key(ar, ik);
- }
- }
-#endif
- }
-
- switch (ik->ik_type) {
- case IEEE80211_CIPHER_WEP:
- keyType = WEP_CRYPT;
- break;
- case IEEE80211_CIPHER_TKIP:
- keyType = TKIP_CRYPT;
- break;
- case IEEE80211_CIPHER_AES_CCM:
- keyType = AES_CRYPT;
- break;
- default:
- break;
- }
-#ifdef USER_KEYS
- ar->user_saved_keys.keyType = keyType;
-#endif
- if (IEEE80211_CIPHER_CCKM_KRK != ik->ik_type) {
- if (NONE_CRYPT == keyType) {
- return -EIO;
- }
-
- if ((WEP_CRYPT == keyType)&&(!ar->arConnected)) {
- int index = ik->ik_keyix;
-
- if (!IEEE80211_IS_VALID_WEP_CIPHER_LEN(ik->ik_keylen)) {
- return -EIO;
- }
-
- A_MEMZERO(ar->arWepKeyList[index].arKey,
- sizeof(ar->arWepKeyList[index].arKey));
- memcpy(ar->arWepKeyList[index].arKey, ik->ik_keydata, ik->ik_keylen);
- ar->arWepKeyList[index].arKeyLen = ik->ik_keylen;
-
- if(ik->ik_flags & IEEE80211_KEY_DEFAULT){
- ar->arDefTxKeyIndex = index;
- }
-
- return 0;
- }
-
- if (((WPA_PSK_AUTH == ar->arAuthMode) || (WPA2_PSK_AUTH == ar->arAuthMode)) &&
- (GROUP_USAGE & keyUsage))
- {
- A_UNTIMEOUT(&ar->disconnect_timer);
- }
-
- status = wmi_addKey_cmd(ar->arWmi, ik->ik_keyix, keyType, keyUsage,
- ik->ik_keylen, (u8 *)&ik->ik_keyrsc,
- ik->ik_keydata, KEY_OP_INIT_VAL, ik->ik_macaddr,
- SYNC_BOTH_WMIFLAG);
-
- if (status) {
- return -EIO;
- }
- } else {
- status = wmi_add_krk_cmd(ar->arWmi, ik->ik_keydata);
- }
-
-#ifdef USER_KEYS
- ar->user_saved_keys.keyOk = true;
-#endif
-
- return 0;
-}
-
-int ar6000_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
- struct hif_device *hifDevice = ar->arHifDevice;
- int ret = 0, param;
- unsigned int address = 0;
- unsigned int length = 0;
- unsigned char *buffer;
- char *userdata;
- u32 connectCtrlFlags;
-
-
- WMI_SET_AKMP_PARAMS_CMD akmpParams;
- WMI_SET_PMKID_LIST_CMD pmkidInfo;
-
- WMI_SET_HT_CAP_CMD htCap;
- WMI_SET_HT_OP_CMD htOp;
-
- /*
- * ioctl operations may have to wait for the Target, so we cannot hold rtnl.
- * Prevent the device from disappearing under us and release the lock during
- * the ioctl operation.
- */
- dev_hold(dev);
- rtnl_unlock();
-
- if (cmd == AR6000_IOCTL_EXTENDED) {
- /*
- * This allows for many more wireless ioctls than would otherwise
- * be available. Applications embed the actual ioctl command in
- * the first word of the parameter block, and use the command
- * AR6000_IOCTL_EXTENDED_CMD on the ioctl call.
- */
- if (get_user(cmd, (int *)rq->ifr_data)) {
- ret = -EFAULT;
- goto ioctl_done;
- }
- userdata = (char *)(((unsigned int *)rq->ifr_data)+1);
- if(is_xioctl_allowed(ar->arNextMode, cmd) != 0) {
- A_PRINTF("xioctl: cmd=%d not allowed in this mode\n",cmd);
- ret = -EOPNOTSUPP;
- goto ioctl_done;
- }
- } else {
- int ret = is_iwioctl_allowed(ar->arNextMode, cmd);
- if(ret == A_ENOTSUP) {
- A_PRINTF("iwioctl: cmd=0x%x not allowed in this mode\n", cmd);
- ret = -EOPNOTSUPP;
- goto ioctl_done;
- } else if (ret == A_ERROR) {
- /* It is not our ioctl (out of range ioctl) */
- ret = -EOPNOTSUPP;
- goto ioctl_done;
- }
- userdata = (char *)rq->ifr_data;
- }
-
- if ((ar->arWlanState == WLAN_DISABLED) &&
- ((cmd != AR6000_XIOCTRL_WMI_SET_WLAN_STATE) &&
- (cmd != AR6000_XIOCTL_GET_WLAN_SLEEP_STATE) &&
- (cmd != AR6000_XIOCTL_DIAG_READ) &&
- (cmd != AR6000_XIOCTL_DIAG_WRITE) &&
- (cmd != AR6000_XIOCTL_SET_BT_HW_POWER_STATE) &&
- (cmd != AR6000_XIOCTL_GET_BT_HW_POWER_STATE) &&
- (cmd != AR6000_XIOCTL_ADD_AP_INTERFACE) &&
- (cmd != AR6000_XIOCTL_REMOVE_AP_INTERFACE) &&
- (cmd != AR6000_IOCTL_WMI_GETREV)))
- {
- ret = -EIO;
- goto ioctl_done;
- }
-
- ret = 0;
- switch(cmd)
- {
- case IEEE80211_IOCTL_SETPARAM:
- {
- int param, value;
- int *ptr = (int *)rq->ifr_ifru.ifru_newname;
- if (ar->arWmiReady == false) {
- ret = -EIO;
- } else {
- param = *ptr++;
- value = *ptr;
- ret = ar6000_ioctl_setparam(ar,param,value);
- }
- break;
- }
- case IEEE80211_IOCTL_SETKEY:
- {
- struct ieee80211req_key keydata;
- if (ar->arWmiReady == false) {
- ret = -EIO;
- } else if (copy_from_user(&keydata, userdata,
- sizeof(struct ieee80211req_key))) {
- ret = -EFAULT;
- } else {
- ar6000_ioctl_setkey(ar, &keydata);
- }
- break;
- }
- case IEEE80211_IOCTL_DELKEY:
- case IEEE80211_IOCTL_SETOPTIE:
- {
- //ret = -EIO;
- break;
- }
- case IEEE80211_IOCTL_SETMLME:
- {
- struct ieee80211req_mlme mlme;
- if (ar->arWmiReady == false) {
- ret = -EIO;
- } else if (copy_from_user(&mlme, userdata,
- sizeof(struct ieee80211req_mlme))) {
- ret = -EFAULT;
- } else {
- switch (mlme.im_op) {
- case IEEE80211_MLME_AUTHORIZE:
- A_PRINTF("setmlme AUTHORIZE %02X:%02X\n",
- mlme.im_macaddr[4], mlme.im_macaddr[5]);
- break;
- case IEEE80211_MLME_UNAUTHORIZE:
- A_PRINTF("setmlme UNAUTHORIZE %02X:%02X\n",
- mlme.im_macaddr[4], mlme.im_macaddr[5]);
- break;
- case IEEE80211_MLME_DEAUTH:
- A_PRINTF("setmlme DEAUTH %02X:%02X\n",
- mlme.im_macaddr[4], mlme.im_macaddr[5]);
- //remove_sta(ar, mlme.im_macaddr);
- break;
- case IEEE80211_MLME_DISASSOC:
- A_PRINTF("setmlme DISASSOC %02X:%02X\n",
- mlme.im_macaddr[4], mlme.im_macaddr[5]);
- //remove_sta(ar, mlme.im_macaddr);
- break;
- default:
- ret = 0;
- goto ioctl_done;
- }
-
- wmi_ap_set_mlme(ar->arWmi, mlme.im_op, mlme.im_macaddr,
- mlme.im_reason);
- }
- break;
- }
- case IEEE80211_IOCTL_ADDPMKID:
- {
- struct ieee80211req_addpmkid req;
- if (ar->arWmiReady == false) {
- ret = -EIO;
- } else if (copy_from_user(&req, userdata, sizeof(struct ieee80211req_addpmkid))) {
- ret = -EFAULT;
- } else {
- int status;
-
- AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("Add pmkid for %2.2x:%2.2x:%2.2x:%2.2x:%2.2x:%2.2x en=%d\n",
- req.pi_bssid[0], req.pi_bssid[1], req.pi_bssid[2],
- req.pi_bssid[3], req.pi_bssid[4], req.pi_bssid[5],
- req.pi_enable));
-
- status = wmi_setPmkid_cmd(ar->arWmi, req.pi_bssid, req.pi_pmkid,
- req.pi_enable);
-
- if (status) {
- ret = -EIO;
- goto ioctl_done;
- }
- }
- break;
- }
-#ifdef CONFIG_HOST_TCMD_SUPPORT
- case AR6000_XIOCTL_TCMD_CONT_TX:
- {
- TCMD_CONT_TX txCmd;
-
- if ((ar->tcmdPm == TCMD_PM_SLEEP) ||
- (ar->tcmdPm == TCMD_PM_DEEPSLEEP))
- {
- A_PRINTF("Can NOT send tx tcmd when target is asleep! \n");
- ret = -EFAULT;
- goto ioctl_done;
- }
-
- if(copy_from_user(&txCmd, userdata, sizeof(TCMD_CONT_TX))) {
- ret = -EFAULT;
- goto ioctl_done;
- } else {
- wmi_test_cmd(ar->arWmi,(u8 *)&txCmd, sizeof(TCMD_CONT_TX));
- }
- }
- break;
- case AR6000_XIOCTL_TCMD_CONT_RX:
- {
- TCMD_CONT_RX rxCmd;
-
- if ((ar->tcmdPm == TCMD_PM_SLEEP) ||
- (ar->tcmdPm == TCMD_PM_DEEPSLEEP))
- {
- A_PRINTF("Can NOT send rx tcmd when target is asleep! \n");
- ret = -EFAULT;
- goto ioctl_done;
- }
- if(copy_from_user(&rxCmd, userdata, sizeof(TCMD_CONT_RX))) {
- ret = -EFAULT;
- goto ioctl_done;
- }
-
- switch(rxCmd.act)
- {
- case TCMD_CONT_RX_PROMIS:
- case TCMD_CONT_RX_FILTER:
- case TCMD_CONT_RX_SETMAC:
- case TCMD_CONT_RX_SET_ANT_SWITCH_TABLE:
- wmi_test_cmd(ar->arWmi,(u8 *)&rxCmd,
- sizeof(TCMD_CONT_RX));
- tcmdRxFreq = rxCmd.u.para.freq;
- break;
- case TCMD_CONT_RX_REPORT:
- ar6000_ioctl_tcmd_get_rx_report(dev, rq,
- (u8 *)&rxCmd, sizeof(TCMD_CONT_RX));
- break;
- default:
- A_PRINTF("Unknown Cont Rx mode: %d\n",rxCmd.act);
- ret = -EINVAL;
- goto ioctl_done;
- }
- }
- break;
- case AR6000_XIOCTL_TCMD_PM:
- {
- TCMD_PM pmCmd;
-
- if(copy_from_user(&pmCmd, userdata, sizeof(TCMD_PM))) {
- ret = -EFAULT;
- goto ioctl_done;
- }
- ar->tcmdPm = pmCmd.mode;
- wmi_test_cmd(ar->arWmi, (u8 *)&pmCmd, sizeof(TCMD_PM));
- }
- break;
-#endif /* CONFIG_HOST_TCMD_SUPPORT */
-
- case AR6000_XIOCTL_BMI_DONE:
- if(bmienable)
- {
- rtnl_lock(); /* ar6000_init expects to be called holding rtnl lock */
- ret = ar6000_init(dev);
- rtnl_unlock();
- }
- else
- {
- ret = BMIDone(hifDevice);
- }
- break;
-
- case AR6000_XIOCTL_BMI_READ_MEMORY:
- if (get_user(address, (unsigned int *)userdata) ||
- get_user(length, (unsigned int *)userdata + 1)) {
- ret = -EFAULT;
- break;
- }
-
- AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("Read Memory (address: 0x%x, length: %d)\n",
- address, length));
- if ((buffer = (unsigned char *)A_MALLOC(length)) != NULL) {
- A_MEMZERO(buffer, length);
- ret = BMIReadMemory(hifDevice, address, buffer, length);
- if (copy_to_user(rq->ifr_data, buffer, length)) {
- ret = -EFAULT;
- }
- A_FREE(buffer);
- } else {
- ret = -ENOMEM;
- }
- break;
-
- case AR6000_XIOCTL_BMI_WRITE_MEMORY:
- if (get_user(address, (unsigned int *)userdata) ||
- get_user(length, (unsigned int *)userdata + 1)) {
- ret = -EFAULT;
- break;
- }
- AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("Write Memory (address: 0x%x, length: %d)\n",
- address, length));
- if ((buffer = (unsigned char *)A_MALLOC(length)) != NULL) {
- A_MEMZERO(buffer, length);
- if (copy_from_user(buffer, &userdata[sizeof(address) +
- sizeof(length)], length))
- {
- ret = -EFAULT;
- } else {
- ret = BMIWriteMemory(hifDevice, address, buffer, length);
- }
- A_FREE(buffer);
- } else {
- ret = -ENOMEM;
- }
- break;
-
- case AR6000_XIOCTL_BMI_TEST:
- AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("No longer supported\n"));
- ret = -EOPNOTSUPP;
- break;
-
- case AR6000_XIOCTL_BMI_EXECUTE:
- if (get_user(address, (unsigned int *)userdata) ||
- get_user(param, (unsigned int *)userdata + 1)) {
- ret = -EFAULT;
- break;
- }
- AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("Execute (address: 0x%x, param: %d)\n",
- address, param));
- ret = BMIExecute(hifDevice, address, (u32 *)¶m);
- /* return value */
- if (put_user(param, (unsigned int *)rq->ifr_data)) {
- ret = -EFAULT;
- break;
- }
- break;
-
- case AR6000_XIOCTL_BMI_SET_APP_START:
- if (get_user(address, (unsigned int *)userdata)) {
- ret = -EFAULT;
- break;
- }
- AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("Set App Start (address: 0x%x)\n", address));
- ret = BMISetAppStart(hifDevice, address);
- break;
-
- case AR6000_XIOCTL_BMI_READ_SOC_REGISTER:
- if (get_user(address, (unsigned int *)userdata)) {
- ret = -EFAULT;
- break;
- }
- ret = BMIReadSOCRegister(hifDevice, address, (u32 *)¶m);
- /* return value */
- if (put_user(param, (unsigned int *)rq->ifr_data)) {
- ret = -EFAULT;
- break;
- }
- break;
-
- case AR6000_XIOCTL_BMI_WRITE_SOC_REGISTER:
- if (get_user(address, (unsigned int *)userdata) ||
- get_user(param, (unsigned int *)userdata + 1)) {
- ret = -EFAULT;
- break;
- }
- ret = BMIWriteSOCRegister(hifDevice, address, param);
- break;
-
-#ifdef HTC_RAW_INTERFACE
- case AR6000_XIOCTL_HTC_RAW_OPEN:
- ret = 0;
- if (!arRawIfEnabled(ar)) {
- /* make sure block size is set in case the target was reset since last
- * BMI phase (i.e. flashup downloads) */
- ret = ar6000_set_htc_params(ar->arHifDevice,
- ar->arTargetType,
- 0, /* use default yield */
- 0 /* use default number of HTC ctrl buffers */
- );
- if (ret) {
- break;
- }
- /* Terminate the BMI phase */
- ret = BMIDone(hifDevice);
- if (ret == 0) {
- ret = ar6000_htc_raw_open(ar);
- }
- }
- break;
-
- case AR6000_XIOCTL_HTC_RAW_CLOSE:
- if (arRawIfEnabled(ar)) {
- ret = ar6000_htc_raw_close(ar);
- arRawIfEnabled(ar) = false;
- } else {
- ret = A_ERROR;
- }
- break;
-
- case AR6000_XIOCTL_HTC_RAW_READ:
- if (arRawIfEnabled(ar)) {
- unsigned int streamID;
- if (get_user(streamID, (unsigned int *)userdata) ||
- get_user(length, (unsigned int *)userdata + 1)) {
- ret = -EFAULT;
- break;
- }
- buffer = (unsigned char*)rq->ifr_data + sizeof(length);
- ret = ar6000_htc_raw_read(ar, (HTC_RAW_STREAM_ID)streamID,
- (char*)buffer, length);
- if (put_user(ret, (unsigned int *)rq->ifr_data)) {
- ret = -EFAULT;
- break;
- }
- } else {
- ret = A_ERROR;
- }
- break;
-
- case AR6000_XIOCTL_HTC_RAW_WRITE:
- if (arRawIfEnabled(ar)) {
- unsigned int streamID;
- if (get_user(streamID, (unsigned int *)userdata) ||
- get_user(length, (unsigned int *)userdata + 1)) {
- ret = -EFAULT;
- break;
- }
- buffer = (unsigned char*)userdata + sizeof(streamID) + sizeof(length);
- ret = ar6000_htc_raw_write(ar, (HTC_RAW_STREAM_ID)streamID,
- (char*)buffer, length);
- if (put_user(ret, (unsigned int *)rq->ifr_data)) {
- ret = -EFAULT;
- break;
- }
- } else {
- ret = A_ERROR;
- }
- break;
-#endif /* HTC_RAW_INTERFACE */
-
- case AR6000_XIOCTL_BMI_LZ_STREAM_START:
- if (get_user(address, (unsigned int *)userdata)) {
- ret = -EFAULT;
- break;
- }
- AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("Start Compressed Stream (address: 0x%x)\n", address));
- ret = BMILZStreamStart(hifDevice, address);
- break;
-
- case AR6000_XIOCTL_BMI_LZ_DATA:
- if (get_user(length, (unsigned int *)userdata)) {
- ret = -EFAULT;
- break;
- }
- AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("Send Compressed Data (length: %d)\n", length));
- if ((buffer = (unsigned char *)A_MALLOC(length)) != NULL) {
- A_MEMZERO(buffer, length);
- if (copy_from_user(buffer, &userdata[sizeof(length)], length))
- {
- ret = -EFAULT;
- } else {
- ret = BMILZData(hifDevice, buffer, length);
- }
- A_FREE(buffer);
- } else {
- ret = -ENOMEM;
- }
- break;
-
-#if defined(CONFIG_TARGET_PROFILE_SUPPORT)
- /*
- * Optional support for Target-side profiling.
- * Not needed in production.
- */
-
- /* Configure Target-side profiling */
- case AR6000_XIOCTL_PROF_CFG:
- {
- u32 period;
- u32 nbins;
- if (get_user(period, (unsigned int *)userdata) ||
- get_user(nbins, (unsigned int *)userdata + 1)) {
- ret = -EFAULT;
- break;
- }
-
- if (wmi_prof_cfg_cmd(ar->arWmi, period, nbins) != 0) {
- ret = -EIO;
- }
-
- break;
- }
-
- /* Start a profiling bucket/bin at the specified address */
- case AR6000_XIOCTL_PROF_ADDR_SET:
- {
- u32 addr;
- if (get_user(addr, (unsigned int *)userdata)) {
- ret = -EFAULT;
- break;
- }
-
- if (wmi_prof_addr_set_cmd(ar->arWmi, addr) != 0) {
- ret = -EIO;
- }
-
- break;
- }
-
- /* START Target-side profiling */
- case AR6000_XIOCTL_PROF_START:
- wmi_prof_start_cmd(ar->arWmi);
- break;
-
- /* STOP Target-side profiling */
- case AR6000_XIOCTL_PROF_STOP:
- wmi_prof_stop_cmd(ar->arWmi);
- break;
- case AR6000_XIOCTL_PROF_COUNT_GET:
- {
- if (ar->bIsDestroyProgress) {
- ret = -EBUSY;
- goto ioctl_done;
- }
- if (ar->arWmiReady == false) {
- ret = -EIO;
- goto ioctl_done;
- }
- if (down_interruptible(&ar->arSem)) {
- ret = -ERESTARTSYS;
- goto ioctl_done;
- }
- if (ar->bIsDestroyProgress) {
- up(&ar->arSem);
- ret = -EBUSY;
- goto ioctl_done;
- }
-
- prof_count_available = false;
- ret = prof_count_get(dev);
- if (ret != 0) {
- up(&ar->arSem);
- ret = -EIO;
- goto ioctl_done;
- }
-
- /* Wait for Target to respond. */
- wait_event_interruptible(arEvent, prof_count_available);
- if (signal_pending(current)) {
- ret = -EINTR;
- } else {
- if (copy_to_user(userdata, &prof_count_results,
- sizeof(prof_count_results)))
- {
- ret = -EFAULT;
- }
- }
- up(&ar->arSem);
- break;
- }
-#endif /* CONFIG_TARGET_PROFILE_SUPPORT */
-
- case AR6000_IOCTL_WMI_GETREV:
- {
- if (copy_to_user(rq->ifr_data, &ar->arVersion,
- sizeof(ar->arVersion)))
- {
- ret = -EFAULT;
- }
- break;
- }
- case AR6000_IOCTL_WMI_SETPWR:
- {
- WMI_POWER_MODE_CMD pwrModeCmd;
-
- if (ar->arWmiReady == false) {
- ret = -EIO;
- } else if (copy_from_user(&pwrModeCmd, userdata,
- sizeof(pwrModeCmd)))
- {
- ret = -EFAULT;
- } else {
- if (wmi_powermode_cmd(ar->arWmi, pwrModeCmd.powerMode)
- != 0)
- {
- ret = -EIO;
- }
- }
- break;
- }
- case AR6000_IOCTL_WMI_SET_IBSS_PM_CAPS:
- {
- WMI_IBSS_PM_CAPS_CMD ibssPmCaps;
-
- if (ar->arWmiReady == false) {
- ret = -EIO;
- } else if (copy_from_user(&ibssPmCaps, userdata,
- sizeof(ibssPmCaps)))
- {
- ret = -EFAULT;
- } else {
- if (wmi_ibsspmcaps_cmd(ar->arWmi, ibssPmCaps.power_saving, ibssPmCaps.ttl,
- ibssPmCaps.atim_windows, ibssPmCaps.timeout_value) != 0)
- {
- ret = -EIO;
- }
- AR6000_SPIN_LOCK(&ar->arLock, 0);
- ar->arIbssPsEnable = ibssPmCaps.power_saving;
- AR6000_SPIN_UNLOCK(&ar->arLock, 0);
- }
- break;
- }
- case AR6000_XIOCTL_WMI_SET_AP_PS:
- {
- WMI_AP_PS_CMD apPsCmd;
-
- if (ar->arWmiReady == false) {
- ret = -EIO;
- } else if (copy_from_user(&apPsCmd, userdata,
- sizeof(apPsCmd)))
- {
- ret = -EFAULT;
- } else {
- if (wmi_apps_cmd(ar->arWmi, apPsCmd.psType, apPsCmd.idle_time,
- apPsCmd.ps_period, apPsCmd.sleep_period) != 0)
- {
- ret = -EIO;
- }
- }
- break;
- }
- case AR6000_IOCTL_WMI_SET_PMPARAMS:
- {
- WMI_POWER_PARAMS_CMD pmParams;
-
- if (ar->arWmiReady == false) {
- ret = -EIO;
- } else if (copy_from_user(&pmParams, userdata,
- sizeof(pmParams)))
- {
- ret = -EFAULT;
- } else {
- if (wmi_pmparams_cmd(ar->arWmi, pmParams.idle_period,
- pmParams.pspoll_number,
- pmParams.dtim_policy,
- pmParams.tx_wakeup_policy,
- pmParams.num_tx_to_wakeup,
-#if WLAN_CONFIG_IGNORE_POWER_SAVE_FAIL_EVENT_DURING_SCAN
- IGNORE_POWER_SAVE_FAIL_EVENT_DURING_SCAN
-#else
- SEND_POWER_SAVE_FAIL_EVENT_ALWAYS
-#endif
- ) != 0)
- {
- ret = -EIO;
- }
- }
- break;
- }
- case AR6000_IOCTL_WMI_SETSCAN:
- {
- if (ar->arWmiReady == false) {
- ret = -EIO;
- } else if (copy_from_user(&ar->scParams, userdata,
- sizeof(ar->scParams)))
- {
- ret = -EFAULT;
- } else {
- if (CAN_SCAN_IN_CONNECT(ar->scParams.scanCtrlFlags)) {
- ar->arSkipScan = false;
- } else {
- ar->arSkipScan = true;
- }
-
- if (wmi_scanparams_cmd(ar->arWmi, ar->scParams.fg_start_period,
- ar->scParams.fg_end_period,
- ar->scParams.bg_period,
- ar->scParams.minact_chdwell_time,
- ar->scParams.maxact_chdwell_time,
- ar->scParams.pas_chdwell_time,
- ar->scParams.shortScanRatio,
- ar->scParams.scanCtrlFlags,
- ar->scParams.max_dfsch_act_time,
- ar->scParams.maxact_scan_per_ssid) != 0)
- {
- ret = -EIO;
- }
- }
- break;
- }
- case AR6000_IOCTL_WMI_SETLISTENINT:
- {
- WMI_LISTEN_INT_CMD listenCmd;
-
- if (ar->arWmiReady == false) {
- ret = -EIO;
- } else if (copy_from_user(&listenCmd, userdata,
- sizeof(listenCmd)))
- {
- ret = -EFAULT;
- } else {
- if (wmi_listeninterval_cmd(ar->arWmi, listenCmd.listenInterval, listenCmd.numBeacons) != 0) {
- ret = -EIO;
- } else {
- AR6000_SPIN_LOCK(&ar->arLock, 0);
- ar->arListenIntervalT = listenCmd.listenInterval;
- ar->arListenIntervalB = listenCmd.numBeacons;
- AR6000_SPIN_UNLOCK(&ar->arLock, 0);
- }
-
- }
- break;
- }
- case AR6000_IOCTL_WMI_SET_BMISS_TIME:
- {
- WMI_BMISS_TIME_CMD bmissCmd;
-
- if (ar->arWmiReady == false) {
- ret = -EIO;
- } else if (copy_from_user(&bmissCmd, userdata,
- sizeof(bmissCmd)))
- {
- ret = -EFAULT;
- } else {
- if (wmi_bmisstime_cmd(ar->arWmi, bmissCmd.bmissTime, bmissCmd.numBeacons) != 0) {
- ret = -EIO;
- }
- }
- break;
- }
- case AR6000_IOCTL_WMI_SETBSSFILTER:
- {
- WMI_BSS_FILTER_CMD filt;
-
- if (ar->arWmiReady == false) {
- ret = -EIO;
- } else if (copy_from_user(&filt, userdata,
- sizeof(filt)))
- {
- ret = -EFAULT;
- } else {
- if (wmi_bssfilter_cmd(ar->arWmi, filt.bssFilter, filt.ieMask)
- != 0) {
- ret = -EIO;
- } else {
- ar->arUserBssFilter = filt.bssFilter;
- }
- }
- break;
- }
-
- case AR6000_IOCTL_WMI_SET_SNRTHRESHOLD:
- {
- ret = ar6000_ioctl_set_snr_threshold(dev, rq);
- break;
- }
- case AR6000_XIOCTL_WMI_SET_RSSITHRESHOLD:
- {
- ret = ar6000_ioctl_set_rssi_threshold(dev, rq);
- break;
- }
- case AR6000_XIOCTL_WMI_CLR_RSSISNR:
- {
- if (ar->arWmiReady == false) {
- ret = -EIO;
- }
- ret = wmi_clr_rssi_snr(ar->arWmi);
- break;
- }
- case AR6000_XIOCTL_WMI_SET_LQTHRESHOLD:
- {
- ret = ar6000_ioctl_set_lq_threshold(dev, rq);
- break;
- }
- case AR6000_XIOCTL_WMI_SET_LPREAMBLE:
- {
- WMI_SET_LPREAMBLE_CMD setLpreambleCmd;
-
- if (ar->arWmiReady == false) {
- ret = -EIO;
- } else if (copy_from_user(&setLpreambleCmd, userdata,
- sizeof(setLpreambleCmd)))
- {
- ret = -EFAULT;
- } else {
- if (wmi_set_lpreamble_cmd(ar->arWmi, setLpreambleCmd.status,
-#if WLAN_CONFIG_DONOT_IGNORE_BARKER_IN_ERP
- WMI_DONOT_IGNORE_BARKER_IN_ERP
-#else
- WMI_IGNORE_BARKER_IN_ERP
-#endif
- ) != 0)
- {
- ret = -EIO;
- }
- }
-
- break;
- }
- case AR6000_XIOCTL_WMI_SET_RTS:
- {
- WMI_SET_RTS_CMD rtsCmd;
- if (ar->arWmiReady == false) {
- ret = -EIO;
- } else if (copy_from_user(&rtsCmd, userdata,
- sizeof(rtsCmd)))
- {
- ret = -EFAULT;
- } else {
- ar->arRTS = rtsCmd.threshold;
- if (wmi_set_rts_cmd(ar->arWmi, rtsCmd.threshold)
- != 0)
- {
- ret = -EIO;
- }
- }
-
- break;
- }
- case AR6000_XIOCTL_WMI_SET_WMM:
- {
- ret = ar6000_ioctl_set_wmm(dev, rq);
- break;
- }
- case AR6000_XIOCTL_WMI_SET_QOS_SUPP:
- {
- ret = ar6000_ioctl_set_qos_supp(dev, rq);
- break;
- }
- case AR6000_XIOCTL_WMI_SET_TXOP:
- {
- ret = ar6000_ioctl_set_txop(dev, rq);
- break;
- }
- case AR6000_XIOCTL_WMI_GET_RD:
- {
- ret = ar6000_ioctl_get_rd(dev, rq);
- break;
- }
- case AR6000_IOCTL_WMI_SET_CHANNELPARAMS:
- {
- ret = ar6000_ioctl_set_channelParams(dev, rq);
- break;
- }
- case AR6000_IOCTL_WMI_SET_PROBEDSSID:
- {
- ret = ar6000_ioctl_set_probedSsid(dev, rq);
- break;
- }
- case AR6000_IOCTL_WMI_SET_BADAP:
- {
- ret = ar6000_ioctl_set_badAp(dev, rq);
- break;
- }
- case AR6000_IOCTL_WMI_CREATE_QOS:
- {
- ret = ar6000_ioctl_create_qos(dev, rq);
- break;
- }
- case AR6000_IOCTL_WMI_DELETE_QOS:
- {
- ret = ar6000_ioctl_delete_qos(dev, rq);
- break;
- }
- case AR6000_IOCTL_WMI_GET_QOS_QUEUE:
- {
- ret = ar6000_ioctl_get_qos_queue(dev, rq);
- break;
- }
- case AR6000_IOCTL_WMI_GET_TARGET_STATS:
- {
- ret = ar6000_ioctl_get_target_stats(dev, rq);
- break;
- }
- case AR6000_IOCTL_WMI_SET_ERROR_REPORT_BITMASK:
- {
- ret = ar6000_ioctl_set_error_report_bitmask(dev, rq);
- break;
- }
- case AR6000_IOCTL_WMI_SET_ASSOC_INFO:
- {
- WMI_SET_ASSOC_INFO_CMD cmd;
- u8 assocInfo[WMI_MAX_ASSOC_INFO_LEN];
-
- if (ar->arWmiReady == false) {
- ret = -EIO;
- break;
- }
-
- if (get_user(cmd.ieType, userdata)) {
- ret = -EFAULT;
- break;
- }
- if (cmd.ieType >= WMI_MAX_ASSOC_INFO_TYPE) {
- ret = -EIO;
- break;
- }
-
- if (get_user(cmd.bufferSize, userdata + 1) ||
- (cmd.bufferSize > WMI_MAX_ASSOC_INFO_LEN) ||
- copy_from_user(assocInfo, userdata + 2, cmd.bufferSize)) {
- ret = -EFAULT;
- break;
- }
- if (wmi_associnfo_cmd(ar->arWmi, cmd.ieType,
- cmd.bufferSize, assocInfo) != 0) {
- ret = -EIO;
- break;
- }
- break;
- }
- case AR6000_IOCTL_WMI_SET_ACCESS_PARAMS:
- {
- ret = ar6000_ioctl_set_access_params(dev, rq);
- break;
- }
- case AR6000_IOCTL_WMI_SET_DISC_TIMEOUT:
- {
- ret = ar6000_ioctl_set_disconnect_timeout(dev, rq);
- break;
- }
- case AR6000_XIOCTL_FORCE_TARGET_RESET:
- {
- if (ar->arHtcTarget)
- {
-// HTCForceReset(htcTarget);
- }
- else
- {
- AR_DEBUG_PRINTF(ATH_DEBUG_WARN,("ar6000_ioctl cannot attempt reset.\n"));
- }
- break;
- }
- case AR6000_XIOCTL_TARGET_INFO:
- case AR6000_XIOCTL_CHECK_TARGET_READY: /* backwards compatibility */
- {
- /* If we made it to here, then the Target exists and is ready. */
-
- if (cmd == AR6000_XIOCTL_TARGET_INFO) {
- if (copy_to_user((u32 *)rq->ifr_data, &ar->arVersion.target_ver,
- sizeof(ar->arVersion.target_ver)))
- {
- ret = -EFAULT;
- }
- if (copy_to_user(((u32 *)rq->ifr_data)+1, &ar->arTargetType,
- sizeof(ar->arTargetType)))
- {
- ret = -EFAULT;
- }
- }
- break;
- }
- case AR6000_XIOCTL_WMI_SET_HB_CHALLENGE_RESP_PARAMS:
- {
- WMI_SET_HB_CHALLENGE_RESP_PARAMS_CMD hbparam;
-
- if (copy_from_user(&hbparam, userdata, sizeof(hbparam)))
- {
- ret = -EFAULT;
- } else {
- AR6000_SPIN_LOCK(&ar->arLock, 0);
- /* Start a cyclic timer with the parameters provided. */
- if (hbparam.frequency) {
- ar->arHBChallengeResp.frequency = hbparam.frequency;
- }
- if (hbparam.threshold) {
- ar->arHBChallengeResp.missThres = hbparam.threshold;
- }
-
- /* Delete the pending timer and start a new one */
- if (timer_pending(&ar->arHBChallengeResp.timer)) {
- A_UNTIMEOUT(&ar->arHBChallengeResp.timer);
- }
- A_TIMEOUT_MS(&ar->arHBChallengeResp.timer, ar->arHBChallengeResp.frequency * 1000, 0);
- AR6000_SPIN_UNLOCK(&ar->arLock, 0);
- }
- break;
- }
- case AR6000_XIOCTL_WMI_GET_HB_CHALLENGE_RESP:
- {
- u32 cookie;
-
- if (copy_from_user(&cookie, userdata, sizeof(cookie))) {
- ret = -EFAULT;
- goto ioctl_done;
- }
-
- /* Send the challenge on the control channel */
- if (wmi_get_challenge_resp_cmd(ar->arWmi, cookie, APP_HB_CHALLENGE) != 0) {
- ret = -EIO;
- goto ioctl_done;
- }
- break;
- }
-#ifdef USER_KEYS
- case AR6000_XIOCTL_USER_SETKEYS:
- {
-
- ar->user_savedkeys_stat = USER_SAVEDKEYS_STAT_RUN;
-
- if (copy_from_user(&ar->user_key_ctrl, userdata,
- sizeof(ar->user_key_ctrl)))
- {
- ret = -EFAULT;
- goto ioctl_done;
- }
-
- A_PRINTF("ar6000 USER set key %x\n", ar->user_key_ctrl);
- break;
- }
-#endif /* USER_KEYS */
-
-#ifdef CONFIG_HOST_GPIO_SUPPORT
- case AR6000_XIOCTL_GPIO_OUTPUT_SET:
- {
- struct ar6000_gpio_output_set_cmd_s gpio_output_set_cmd;
-
- if (ar->bIsDestroyProgress) {
- ret = -EBUSY;
- goto ioctl_done;
- }
- if (ar->arWmiReady == false) {
- ret = -EIO;
- goto ioctl_done;
- }
- if (down_interruptible(&ar->arSem)) {
- ret = -ERESTARTSYS;
- goto ioctl_done;
- }
- if (ar->bIsDestroyProgress) {
- up(&ar->arSem);
- ret = -EBUSY;
- goto ioctl_done;
- }
-
- if (copy_from_user(&gpio_output_set_cmd, userdata,
- sizeof(gpio_output_set_cmd)))
- {
- ret = -EFAULT;
- } else {
- ret = ar6000_gpio_output_set(dev,
- gpio_output_set_cmd.set_mask,
- gpio_output_set_cmd.clear_mask,
- gpio_output_set_cmd.enable_mask,
- gpio_output_set_cmd.disable_mask);
- if (ret != 0) {
- ret = -EIO;
- }
- }
- up(&ar->arSem);
- break;
- }
- case AR6000_XIOCTL_GPIO_INPUT_GET:
- {
- if (ar->bIsDestroyProgress) {
- ret = -EBUSY;
- goto ioctl_done;
- }
- if (ar->arWmiReady == false) {
- ret = -EIO;
- goto ioctl_done;
- }
- if (down_interruptible(&ar->arSem)) {
- ret = -ERESTARTSYS;
- goto ioctl_done;
- }
- if (ar->bIsDestroyProgress) {
- up(&ar->arSem);
- ret = -EBUSY;
- goto ioctl_done;
- }
-
- ret = ar6000_gpio_input_get(dev);
- if (ret != 0) {
- up(&ar->arSem);
- ret = -EIO;
- goto ioctl_done;
- }
-
- /* Wait for Target to respond. */
- wait_event_interruptible(arEvent, gpio_data_available);
- if (signal_pending(current)) {
- ret = -EINTR;
- } else {
- A_ASSERT(gpio_reg_results.gpioreg_id == GPIO_ID_NONE);
-
- if (copy_to_user(userdata, &gpio_reg_results.value,
- sizeof(gpio_reg_results.value)))
- {
- ret = -EFAULT;
- }
- }
- up(&ar->arSem);
- break;
- }
- case AR6000_XIOCTL_GPIO_REGISTER_SET:
- {
- struct ar6000_gpio_register_cmd_s gpio_register_cmd;
-
- if (ar->bIsDestroyProgress) {
- ret = -EBUSY;
- goto ioctl_done;
- }
- if (ar->arWmiReady == false) {
- ret = -EIO;
- goto ioctl_done;
- }
- if (down_interruptible(&ar->arSem)) {
- ret = -ERESTARTSYS;
- goto ioctl_done;
- }
- if (ar->bIsDestroyProgress) {
- up(&ar->arSem);
- ret = -EBUSY;
- goto ioctl_done;
- }
-
- if (copy_from_user(&gpio_register_cmd, userdata,
- sizeof(gpio_register_cmd)))
- {
- ret = -EFAULT;
- } else {
- ret = ar6000_gpio_register_set(dev,
- gpio_register_cmd.gpioreg_id,
- gpio_register_cmd.value);
- if (ret != 0) {
- ret = -EIO;
- }
-
- /* Wait for acknowledgement from Target */
- wait_event_interruptible(arEvent, gpio_ack_received);
- if (signal_pending(current)) {
- ret = -EINTR;
- }
- }
- up(&ar->arSem);
- break;
- }
- case AR6000_XIOCTL_GPIO_REGISTER_GET:
- {
- struct ar6000_gpio_register_cmd_s gpio_register_cmd;
-
- if (ar->bIsDestroyProgress) {
- ret = -EBUSY;
- goto ioctl_done;
- }
- if (ar->arWmiReady == false) {
- ret = -EIO;
- goto ioctl_done;
- }
- if (down_interruptible(&ar->arSem)) {
- ret = -ERESTARTSYS;
- goto ioctl_done;
- }
- if (ar->bIsDestroyProgress) {
- up(&ar->arSem);
- ret = -EBUSY;
- goto ioctl_done;
- }
-
- if (copy_from_user(&gpio_register_cmd, userdata,
- sizeof(gpio_register_cmd)))
- {
- ret = -EFAULT;
- } else {
- ret = ar6000_gpio_register_get(dev, gpio_register_cmd.gpioreg_id);
- if (ret != 0) {
- up(&ar->arSem);
- ret = -EIO;
- goto ioctl_done;
- }
-
- /* Wait for Target to respond. */
- wait_event_interruptible(arEvent, gpio_data_available);
- if (signal_pending(current)) {
- ret = -EINTR;
- } else {
- A_ASSERT(gpio_register_cmd.gpioreg_id == gpio_reg_results.gpioreg_id);
- if (copy_to_user(userdata, &gpio_reg_results,
- sizeof(gpio_reg_results)))
- {
- ret = -EFAULT;
- }
- }
- }
- up(&ar->arSem);
- break;
- }
- case AR6000_XIOCTL_GPIO_INTR_ACK:
- {
- struct ar6000_gpio_intr_ack_cmd_s gpio_intr_ack_cmd;
-
- if (ar->bIsDestroyProgress) {
- ret = -EBUSY;
- goto ioctl_done;
- }
- if (ar->arWmiReady == false) {
- ret = -EIO;
- goto ioctl_done;
- }
- if (down_interruptible(&ar->arSem)) {
- ret = -ERESTARTSYS;
- goto ioctl_done;
- }
- if (ar->bIsDestroyProgress) {
- up(&ar->arSem);
- ret = -EBUSY;
- goto ioctl_done;
- }
-
- if (copy_from_user(&gpio_intr_ack_cmd, userdata,
- sizeof(gpio_intr_ack_cmd)))
- {
- ret = -EFAULT;
- } else {
- ret = ar6000_gpio_intr_ack(dev, gpio_intr_ack_cmd.ack_mask);
- if (ret != 0) {
- ret = -EIO;
- }
- }
- up(&ar->arSem);
- break;
- }
- case AR6000_XIOCTL_GPIO_INTR_WAIT:
- {
- /* Wait for Target to report an interrupt. */
- wait_event_interruptible(arEvent, gpio_intr_available);
-
- if (signal_pending(current)) {
- ret = -EINTR;
- } else {
- if (copy_to_user(userdata, &gpio_intr_results,
- sizeof(gpio_intr_results)))
- {
- ret = -EFAULT;
- }
- }
- break;
- }
-#endif /* CONFIG_HOST_GPIO_SUPPORT */
-
- case AR6000_XIOCTL_DBGLOG_CFG_MODULE:
- {
- struct ar6000_dbglog_module_config_s config;
-
- if (copy_from_user(&config, userdata, sizeof(config))) {
- ret = -EFAULT;
- goto ioctl_done;
- }
-
- /* Send the challenge on the control channel */
- if (wmi_config_debug_module_cmd(ar->arWmi, config.mmask,
- config.tsr, config.rep,
- config.size, config.valid) != 0)
- {
- ret = -EIO;
- goto ioctl_done;
- }
- break;
- }
-
- case AR6000_XIOCTL_DBGLOG_GET_DEBUG_LOGS:
- {
- /* Send the challenge on the control channel */
- if (ar6000_dbglog_get_debug_logs(ar) != 0)
- {
- ret = -EIO;
- goto ioctl_done;
- }
- break;
- }
-
- case AR6000_XIOCTL_SET_ADHOC_BSSID:
- {
- WMI_SET_ADHOC_BSSID_CMD adhocBssid;
-
- if (ar->arWmiReady == false) {
- ret = -EIO;
- } else if (copy_from_user(&adhocBssid, userdata,
- sizeof(adhocBssid)))
- {
- ret = -EFAULT;
- } else if (memcmp(adhocBssid.bssid, bcast_mac,
- AR6000_ETH_ADDR_LEN) == 0)
- {
- ret = -EFAULT;
- } else {
-
- memcpy(ar->arReqBssid, adhocBssid.bssid, sizeof(ar->arReqBssid));
- }
- break;
- }
-
- case AR6000_XIOCTL_SET_OPT_MODE:
- {
- WMI_SET_OPT_MODE_CMD optModeCmd;
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
-
- if (ar->arWmiReady == false) {
- ret = -EIO;
- } else if (copy_from_user(&optModeCmd, userdata,
- sizeof(optModeCmd)))
- {
- ret = -EFAULT;
- } else if (ar->arConnected && optModeCmd.optMode == SPECIAL_ON) {
- ret = -EFAULT;
-
- } else if (wmi_set_opt_mode_cmd(ar->arWmi, optModeCmd.optMode)
- != 0)
- {
- ret = -EIO;
- }
- break;
- }
-
- case AR6000_XIOCTL_OPT_SEND_FRAME:
- {
- WMI_OPT_TX_FRAME_CMD optTxFrmCmd;
- u8 data[MAX_OPT_DATA_LEN];
-
- if (ar->arWmiReady == false) {
- ret = -EIO;
- break;
- }
-
- if (copy_from_user(&optTxFrmCmd, userdata, sizeof(optTxFrmCmd))) {
- ret = -EFAULT;
- break;
- }
-
- if (optTxFrmCmd.optIEDataLen > MAX_OPT_DATA_LEN) {
- ret = -EINVAL;
- break;
- }
-
- if (copy_from_user(data, userdata+sizeof(WMI_OPT_TX_FRAME_CMD) - 1,
- optTxFrmCmd.optIEDataLen)) {
- ret = -EFAULT;
- break;
- }
-
- ret = wmi_opt_tx_frame_cmd(ar->arWmi,
- optTxFrmCmd.frmType,
- optTxFrmCmd.dstAddr,
- optTxFrmCmd.bssid,
- optTxFrmCmd.optIEDataLen,
- data);
- break;
- }
- case AR6000_XIOCTL_WMI_SETRETRYLIMITS:
- {
- WMI_SET_RETRY_LIMITS_CMD setRetryParams;
-
- if (ar->arWmiReady == false) {
- ret = -EIO;
- } else if (copy_from_user(&setRetryParams, userdata,
- sizeof(setRetryParams)))
- {
- ret = -EFAULT;
- } else {
- if (wmi_set_retry_limits_cmd(ar->arWmi, setRetryParams.frameType,
- setRetryParams.trafficClass,
- setRetryParams.maxRetries,
- setRetryParams.enableNotify) != 0)
- {
- ret = -EIO;
- }
- AR6000_SPIN_LOCK(&ar->arLock, 0);
- ar->arMaxRetries = setRetryParams.maxRetries;
- AR6000_SPIN_UNLOCK(&ar->arLock, 0);
- }
- break;
- }
-
- case AR6000_XIOCTL_SET_BEACON_INTVAL:
- {
- WMI_BEACON_INT_CMD bIntvlCmd;
-
- if (ar->arWmiReady == false) {
- ret = -EIO;
- } else if (copy_from_user(&bIntvlCmd, userdata,
- sizeof(bIntvlCmd)))
- {
- ret = -EFAULT;
- } else if (wmi_set_adhoc_bconIntvl_cmd(ar->arWmi, bIntvlCmd.beaconInterval)
- != 0)
- {
- ret = -EIO;
- }
- if(ret == 0) {
- ar->ap_beacon_interval = bIntvlCmd.beaconInterval;
- ar->ap_profile_flag = 1; /* There is a change in profile */
- }
- break;
- }
- case IEEE80211_IOCTL_SETAUTHALG:
- {
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
- struct ieee80211req_authalg req;
-
- if (ar->arWmiReady == false) {
- ret = -EIO;
- } else if (copy_from_user(&req, userdata,
- sizeof(struct ieee80211req_authalg)))
- {
- ret = -EFAULT;
- } else {
- if (req.auth_alg & AUTH_ALG_OPEN_SYSTEM) {
- ar->arDot11AuthMode |= OPEN_AUTH;
- ar->arPairwiseCrypto = NONE_CRYPT;
- ar->arGroupCrypto = NONE_CRYPT;
- }
- if (req.auth_alg & AUTH_ALG_SHARED_KEY) {
- ar->arDot11AuthMode |= SHARED_AUTH;
- ar->arPairwiseCrypto = WEP_CRYPT;
- ar->arGroupCrypto = WEP_CRYPT;
- ar->arAuthMode = NONE_AUTH;
- }
- if (req.auth_alg == AUTH_ALG_LEAP) {
- ar->arDot11AuthMode = LEAP_AUTH;
- }
- }
- break;
- }
-
- case AR6000_XIOCTL_SET_VOICE_PKT_SIZE:
- ret = ar6000_xioctl_set_voice_pkt_size(dev, userdata);
- break;
-
- case AR6000_XIOCTL_SET_MAX_SP:
- ret = ar6000_xioctl_set_max_sp_len(dev, userdata);
- break;
-
- case AR6000_XIOCTL_WMI_GET_ROAM_TBL:
- ret = ar6000_ioctl_get_roam_tbl(dev, rq);
- break;
- case AR6000_XIOCTL_WMI_SET_ROAM_CTRL:
- ret = ar6000_ioctl_set_roam_ctrl(dev, userdata);
- break;
- case AR6000_XIOCTRL_WMI_SET_POWERSAVE_TIMERS:
- ret = ar6000_ioctl_set_powersave_timers(dev, userdata);
- break;
- case AR6000_XIOCTRL_WMI_GET_POWER_MODE:
- ret = ar6000_ioctl_get_power_mode(dev, rq);
- break;
- case AR6000_XIOCTRL_WMI_SET_WLAN_STATE:
- {
- AR6000_WLAN_STATE state;
- if (get_user(state, (unsigned int *)userdata))
- ret = -EFAULT;
- else if (ar6000_set_wlan_state(ar, state) != 0)
- ret = -EIO;
- break;
- }
- case AR6000_XIOCTL_WMI_GET_ROAM_DATA:
- ret = ar6000_ioctl_get_roam_data(dev, rq);
- break;
-
- case AR6000_XIOCTL_WMI_SET_BT_STATUS:
- ret = ar6000_xioctl_set_bt_status_cmd(dev, userdata);
- break;
-
- case AR6000_XIOCTL_WMI_SET_BT_PARAMS:
- ret = ar6000_xioctl_set_bt_params_cmd(dev, userdata);
- break;
-
- case AR6000_XIOCTL_WMI_SET_BTCOEX_FE_ANT:
- ret = ar6000_xioctl_set_btcoex_fe_ant_cmd(dev, userdata);
- break;
-
- case AR6000_XIOCTL_WMI_SET_BTCOEX_COLOCATED_BT_DEV:
- ret = ar6000_xioctl_set_btcoex_colocated_bt_dev_cmd(dev, userdata);
- break;
-
- case AR6000_XIOCTL_WMI_SET_BTCOEX_BTINQUIRY_PAGE_CONFIG:
- ret = ar6000_xioctl_set_btcoex_btinquiry_page_config_cmd(dev, userdata);
- break;
-
- case AR6000_XIOCTL_WMI_SET_BTCOEX_SCO_CONFIG:
- ret = ar6000_xioctl_set_btcoex_sco_config_cmd( dev, userdata);
- break;
-
- case AR6000_XIOCTL_WMI_SET_BTCOEX_A2DP_CONFIG:
- ret = ar6000_xioctl_set_btcoex_a2dp_config_cmd(dev, userdata);
- break;
-
- case AR6000_XIOCTL_WMI_SET_BTCOEX_ACLCOEX_CONFIG:
- ret = ar6000_xioctl_set_btcoex_aclcoex_config_cmd(dev, userdata);
- break;
-
- case AR6000_XIOCTL_WMI_SET_BTCOEX_DEBUG:
- ret = ar60000_xioctl_set_btcoex_debug_cmd(dev, userdata);
- break;
-
- case AR6000_XIOCTL_WMI_SET_BT_OPERATING_STATUS:
- ret = ar6000_xioctl_set_btcoex_bt_operating_status_cmd(dev, userdata);
- break;
-
- case AR6000_XIOCTL_WMI_GET_BTCOEX_CONFIG:
- ret = ar6000_xioctl_get_btcoex_config_cmd(dev, userdata, rq);
- break;
-
- case AR6000_XIOCTL_WMI_GET_BTCOEX_STATS:
- ret = ar6000_xioctl_get_btcoex_stats_cmd(dev, userdata, rq);
- break;
-
- case AR6000_XIOCTL_WMI_STARTSCAN:
- {
- WMI_START_SCAN_CMD setStartScanCmd, *cmdp;
-
- if (ar->arWmiReady == false) {
- ret = -EIO;
- } else if (copy_from_user(&setStartScanCmd, userdata,
- sizeof(setStartScanCmd)))
- {
- ret = -EFAULT;
- } else {
- if (setStartScanCmd.numChannels > 1) {
- cmdp = A_MALLOC(130);
- if (copy_from_user(cmdp, userdata,
- sizeof (*cmdp) +
- ((setStartScanCmd.numChannels - 1) *
- sizeof(u16))))
- {
- kfree(cmdp);
- ret = -EFAULT;
- goto ioctl_done;
- }
- } else {
- cmdp = &setStartScanCmd;
- }
-
- if (wmi_startscan_cmd(ar->arWmi, cmdp->scanType,
- cmdp->forceFgScan,
- cmdp->isLegacy,
- cmdp->homeDwellTime,
- cmdp->forceScanInterval,
- cmdp->numChannels,
- cmdp->channelList) != 0)
- {
- ret = -EIO;
- }
- }
- break;
- }
- case AR6000_XIOCTL_WMI_SETFIXRATES:
- {
- WMI_FIX_RATES_CMD setFixRatesCmd;
- int returnStatus;
-
- if (ar->arWmiReady == false) {
- ret = -EIO;
- } else if (copy_from_user(&setFixRatesCmd, userdata,
- sizeof(setFixRatesCmd)))
- {
- ret = -EFAULT;
- } else {
- returnStatus = wmi_set_fixrates_cmd(ar->arWmi, setFixRatesCmd.fixRateMask);
- if (returnStatus == A_EINVAL) {
- ret = -EINVAL;
- } else if(returnStatus != 0) {
- ret = -EIO;
- } else {
- ar->ap_profile_flag = 1; /* There is a change in profile */
- }
- }
- break;
- }
-
- case AR6000_XIOCTL_WMI_GETFIXRATES:
- {
- WMI_FIX_RATES_CMD getFixRatesCmd;
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
- int ret = 0;
-
- if (ar->bIsDestroyProgress) {
- ret = -EBUSY;
- goto ioctl_done;
- }
- if (ar->arWmiReady == false) {
- ret = -EIO;
- goto ioctl_done;
- }
-
- if (down_interruptible(&ar->arSem)) {
- ret = -ERESTARTSYS;
- goto ioctl_done;
- }
- if (ar->bIsDestroyProgress) {
- up(&ar->arSem);
- ret = -EBUSY;
- goto ioctl_done;
- }
- /* Used copy_from_user/copy_to_user to access user space data */
- if (copy_from_user(&getFixRatesCmd, userdata, sizeof(getFixRatesCmd))) {
- ret = -EFAULT;
- } else {
- ar->arRateMask = 0xFFFFFFFF;
-
- if (wmi_get_ratemask_cmd(ar->arWmi) != 0) {
- up(&ar->arSem);
- ret = -EIO;
- goto ioctl_done;
- }
-
- wait_event_interruptible_timeout(arEvent, ar->arRateMask != 0xFFFFFFFF, wmitimeout * HZ);
-
- if (signal_pending(current)) {
- ret = -EINTR;
- }
-
- if (!ret) {
- getFixRatesCmd.fixRateMask = ar->arRateMask;
- }
-
- if(copy_to_user(userdata, &getFixRatesCmd, sizeof(getFixRatesCmd))) {
- ret = -EFAULT;
- }
-
- up(&ar->arSem);
- }
- break;
- }
- case AR6000_XIOCTL_WMI_SET_AUTHMODE:
- {
- WMI_SET_AUTH_MODE_CMD setAuthMode;
-
- if (ar->arWmiReady == false) {
- ret = -EIO;
- } else if (copy_from_user(&setAuthMode, userdata,
- sizeof(setAuthMode)))
- {
- ret = -EFAULT;
- } else {
- if (wmi_set_authmode_cmd(ar->arWmi, setAuthMode.mode) != 0)
- {
- ret = -EIO;
- }
- }
- break;
- }
- case AR6000_XIOCTL_WMI_SET_REASSOCMODE:
- {
- WMI_SET_REASSOC_MODE_CMD setReassocMode;
-
- if (ar->arWmiReady == false) {
- ret = -EIO;
- } else if (copy_from_user(&setReassocMode, userdata,
- sizeof(setReassocMode)))
- {
- ret = -EFAULT;
- } else {
- if (wmi_set_reassocmode_cmd(ar->arWmi, setReassocMode.mode) != 0)
- {
- ret = -EIO;
- }
- }
- break;
- }
- case AR6000_XIOCTL_DIAG_READ:
- {
- u32 addr, data;
- if (get_user(addr, (unsigned int *)userdata)) {
- ret = -EFAULT;
- break;
- }
- addr = TARG_VTOP(ar->arTargetType, addr);
- if (ar6000_ReadRegDiag(ar->arHifDevice, &addr, &data) != 0) {
- ret = -EIO;
- }
- if (put_user(data, (unsigned int *)userdata + 1)) {
- ret = -EFAULT;
- break;
- }
- break;
- }
- case AR6000_XIOCTL_DIAG_WRITE:
- {
- u32 addr, data;
- if (get_user(addr, (unsigned int *)userdata) ||
- get_user(data, (unsigned int *)userdata + 1)) {
- ret = -EFAULT;
- break;
- }
- addr = TARG_VTOP(ar->arTargetType, addr);
- if (ar6000_WriteRegDiag(ar->arHifDevice, &addr, &data) != 0) {
- ret = -EIO;
- }
- break;
- }
- case AR6000_XIOCTL_WMI_SET_KEEPALIVE:
- {
- WMI_SET_KEEPALIVE_CMD setKeepAlive;
- if (ar->arWmiReady == false) {
- ret = -EIO;
- goto ioctl_done;
- } else if (copy_from_user(&setKeepAlive, userdata,
- sizeof(setKeepAlive))){
- ret = -EFAULT;
- } else {
- if (wmi_set_keepalive_cmd(ar->arWmi, setKeepAlive.keepaliveInterval) != 0) {
- ret = -EIO;
- }
- }
- break;
- }
- case AR6000_XIOCTL_WMI_SET_PARAMS:
- {
- WMI_SET_PARAMS_CMD cmd;
- if (ar->arWmiReady == false) {
- ret = -EIO;
- goto ioctl_done;
- } else if (copy_from_user(&cmd, userdata,
- sizeof(cmd))){
- ret = -EFAULT;
- } else if (copy_from_user(&cmd, userdata,
- sizeof(cmd) + cmd.length))
- {
- ret = -EFAULT;
- } else {
- if (wmi_set_params_cmd(ar->arWmi, cmd.opcode, cmd.length, cmd.buffer) != 0) {
- ret = -EIO;
- }
- }
- break;
- }
- case AR6000_XIOCTL_WMI_SET_MCAST_FILTER:
- {
- WMI_SET_MCAST_FILTER_CMD cmd;
- if (ar->arWmiReady == false) {
- ret = -EIO;
- goto ioctl_done;
- } else if (copy_from_user(&cmd, userdata,
- sizeof(cmd))){
- ret = -EFAULT;
- } else {
- if (wmi_set_mcast_filter_cmd(ar->arWmi, cmd.multicast_mac[0],
- cmd.multicast_mac[1],
- cmd.multicast_mac[2],
- cmd.multicast_mac[3]) != 0) {
- ret = -EIO;
- }
- }
- break;
- }
- case AR6000_XIOCTL_WMI_DEL_MCAST_FILTER:
- {
- WMI_SET_MCAST_FILTER_CMD cmd;
- if (ar->arWmiReady == false) {
- ret = -EIO;
- goto ioctl_done;
- } else if (copy_from_user(&cmd, userdata,
- sizeof(cmd))){
- ret = -EFAULT;
- } else {
- if (wmi_del_mcast_filter_cmd(ar->arWmi, cmd.multicast_mac[0],
- cmd.multicast_mac[1],
- cmd.multicast_mac[2],
- cmd.multicast_mac[3]) != 0) {
- ret = -EIO;
- }
- }
- break;
- }
- case AR6000_XIOCTL_WMI_MCAST_FILTER:
- {
- WMI_MCAST_FILTER_CMD cmd;
- if (ar->arWmiReady == false) {
- ret = -EIO;
- goto ioctl_done;
- } else if (copy_from_user(&cmd, userdata,
- sizeof(cmd))){
- ret = -EFAULT;
- } else {
- if (wmi_mcast_filter_cmd(ar->arWmi, cmd.enable) != 0) {
- ret = -EIO;
- }
- }
- break;
- }
- case AR6000_XIOCTL_WMI_GET_KEEPALIVE:
- {
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
- WMI_GET_KEEPALIVE_CMD getKeepAlive;
- int ret = 0;
- if (ar->bIsDestroyProgress) {
- ret =-EBUSY;
- goto ioctl_done;
- }
- if (ar->arWmiReady == false) {
- ret = -EIO;
- goto ioctl_done;
- }
- if (down_interruptible(&ar->arSem)) {
- ret = -ERESTARTSYS;
- goto ioctl_done;
- }
- if (ar->bIsDestroyProgress) {
- up(&ar->arSem);
- ret = -EBUSY;
- goto ioctl_done;
- }
- if (copy_from_user(&getKeepAlive, userdata,sizeof(getKeepAlive))) {
- ret = -EFAULT;
- } else {
- getKeepAlive.keepaliveInterval = wmi_get_keepalive_cmd(ar->arWmi);
- ar->arKeepaliveConfigured = 0xFF;
- if (wmi_get_keepalive_configured(ar->arWmi) != 0){
- up(&ar->arSem);
- ret = -EIO;
- goto ioctl_done;
- }
- wait_event_interruptible_timeout(arEvent, ar->arKeepaliveConfigured != 0xFF, wmitimeout * HZ);
- if (signal_pending(current)) {
- ret = -EINTR;
- }
-
- if (!ret) {
- getKeepAlive.configured = ar->arKeepaliveConfigured;
- }
- if (copy_to_user(userdata, &getKeepAlive, sizeof(getKeepAlive))) {
- ret = -EFAULT;
- }
- up(&ar->arSem);
- }
- break;
- }
- case AR6000_XIOCTL_WMI_SET_APPIE:
- {
- WMI_SET_APPIE_CMD appIEcmd;
- u8 appIeInfo[IEEE80211_APPIE_FRAME_MAX_LEN];
- u32 fType,ieLen;
-
- if (ar->arWmiReady == false) {
- ret = -EIO;
- goto ioctl_done;
- }
- if (get_user(fType, (u32 *)userdata)) {
- ret = -EFAULT;
- break;
- }
- appIEcmd.mgmtFrmType = fType;
- if (appIEcmd.mgmtFrmType >= IEEE80211_APPIE_NUM_OF_FRAME) {
- ret = -EIO;
- } else {
- if (get_user(ieLen, (u32 *)(userdata + 4))) {
- ret = -EFAULT;
- break;
- }
- appIEcmd.ieLen = ieLen;
- A_PRINTF("WPSIE: Type-%d, Len-%d\n",appIEcmd.mgmtFrmType, appIEcmd.ieLen);
- if (appIEcmd.ieLen > IEEE80211_APPIE_FRAME_MAX_LEN) {
- ret = -EIO;
- break;
- }
- if (copy_from_user(appIeInfo, userdata + 8, appIEcmd.ieLen)) {
- ret = -EFAULT;
- } else {
- if (wmi_set_appie_cmd(ar->arWmi, appIEcmd.mgmtFrmType,
- appIEcmd.ieLen, appIeInfo) != 0)
- {
- ret = -EIO;
- }
- }
- }
- break;
- }
- case AR6000_XIOCTL_WMI_SET_MGMT_FRM_RX_FILTER:
- {
- WMI_BSS_FILTER_CMD cmd;
- u32 filterType;
-
- if (copy_from_user(&filterType, userdata, sizeof(u32)))
- {
- ret = -EFAULT;
- goto ioctl_done;
- }
- if (filterType & (IEEE80211_FILTER_TYPE_BEACON |
- IEEE80211_FILTER_TYPE_PROBE_RESP))
- {
- cmd.bssFilter = ALL_BSS_FILTER;
- } else {
- cmd.bssFilter = NONE_BSS_FILTER;
- }
- if (wmi_bssfilter_cmd(ar->arWmi, cmd.bssFilter, 0) != 0) {
- ret = -EIO;
- } else {
- ar->arUserBssFilter = cmd.bssFilter;
- }
-
- AR6000_SPIN_LOCK(&ar->arLock, 0);
- ar->arMgmtFilter = filterType;
- AR6000_SPIN_UNLOCK(&ar->arLock, 0);
- break;
- }
- case AR6000_XIOCTL_WMI_SET_WSC_STATUS:
- {
- u32 wsc_status;
-
- if (ar->arWmiReady == false) {
- ret = -EIO;
- goto ioctl_done;
- } else if (copy_from_user(&wsc_status, userdata, sizeof(u32)))
- {
- ret = -EFAULT;
- goto ioctl_done;
- }
- if (wmi_set_wsc_status_cmd(ar->arWmi, wsc_status) != 0) {
- ret = -EIO;
- }
- break;
- }
- case AR6000_XIOCTL_BMI_ROMPATCH_INSTALL:
- {
- u32 ROM_addr;
- u32 RAM_addr;
- u32 nbytes;
- u32 do_activate;
- u32 rompatch_id;
-
- if (get_user(ROM_addr, (u32 *)userdata) ||
- get_user(RAM_addr, (u32 *)userdata + 1) ||
- get_user(nbytes, (u32 *)userdata + 2) ||
- get_user(do_activate, (u32 *)userdata + 3)) {
- ret = -EFAULT;
- break;
- }
- AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("Install rompatch from ROM: 0x%x to RAM: 0x%x length: %d\n",
- ROM_addr, RAM_addr, nbytes));
- ret = BMIrompatchInstall(hifDevice, ROM_addr, RAM_addr,
- nbytes, do_activate, &rompatch_id);
- if (ret == 0) {
- /* return value */
- if (put_user(rompatch_id, (unsigned int *)rq->ifr_data)) {
- ret = -EFAULT;
- break;
- }
- }
- break;
- }
-
- case AR6000_XIOCTL_BMI_ROMPATCH_UNINSTALL:
- {
- u32 rompatch_id;
-
- if (get_user(rompatch_id, (u32 *)userdata)) {
- ret = -EFAULT;
- break;
- }
- AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("UNinstall rompatch_id %d\n", rompatch_id));
- ret = BMIrompatchUninstall(hifDevice, rompatch_id);
- break;
- }
-
- case AR6000_XIOCTL_BMI_ROMPATCH_ACTIVATE:
- case AR6000_XIOCTL_BMI_ROMPATCH_DEACTIVATE:
- {
- u32 rompatch_count;
-
- if (get_user(rompatch_count, (u32 *)userdata)) {
- ret = -EFAULT;
- break;
- }
- AR_DEBUG_PRINTF(ATH_DEBUG_INFO,("Change rompatch activation count=%d\n", rompatch_count));
- length = sizeof(u32) * rompatch_count;
- if ((buffer = (unsigned char *)A_MALLOC(length)) != NULL) {
- A_MEMZERO(buffer, length);
- if (copy_from_user(buffer, &userdata[sizeof(rompatch_count)], length))
- {
- ret = -EFAULT;
- } else {
- if (cmd == AR6000_XIOCTL_BMI_ROMPATCH_ACTIVATE) {
- ret = BMIrompatchActivate(hifDevice, rompatch_count, (u32 *)buffer);
- } else {
- ret = BMIrompatchDeactivate(hifDevice, rompatch_count, (u32 *)buffer);
- }
- }
- A_FREE(buffer);
- } else {
- ret = -ENOMEM;
- }
-
- break;
- }
- case AR6000_XIOCTL_SET_IP:
- {
- WMI_SET_IP_CMD setIP;
-
- if (ar->arWmiReady == false) {
- ret = -EIO;
- } else if (copy_from_user(&setIP, userdata,
- sizeof(setIP)))
- {
- ret = -EFAULT;
- } else {
- if (wmi_set_ip_cmd(ar->arWmi,
- &setIP) != 0)
- {
- ret = -EIO;
- }
- }
- break;
- }
-
- case AR6000_XIOCTL_WMI_SET_HOST_SLEEP_MODE:
- {
- WMI_SET_HOST_SLEEP_MODE_CMD setHostSleepMode;
-
- if (ar->arWmiReady == false) {
- ret = -EIO;
- } else if (copy_from_user(&setHostSleepMode, userdata,
- sizeof(setHostSleepMode)))
- {
- ret = -EFAULT;
- } else {
- if (wmi_set_host_sleep_mode_cmd(ar->arWmi,
- &setHostSleepMode) != 0)
- {
- ret = -EIO;
- }
- }
- break;
- }
- case AR6000_XIOCTL_WMI_SET_WOW_MODE:
- {
- WMI_SET_WOW_MODE_CMD setWowMode;
-
- if (ar->arWmiReady == false) {
- ret = -EIO;
- } else if (copy_from_user(&setWowMode, userdata,
- sizeof(setWowMode)))
- {
- ret = -EFAULT;
- } else {
- if (wmi_set_wow_mode_cmd(ar->arWmi,
- &setWowMode) != 0)
- {
- ret = -EIO;
- }
- }
- break;
- }
- case AR6000_XIOCTL_WMI_GET_WOW_LIST:
- {
- WMI_GET_WOW_LIST_CMD getWowList;
-
- if (ar->arWmiReady == false) {
- ret = -EIO;
- } else if (copy_from_user(&getWowList, userdata,
- sizeof(getWowList)))
- {
- ret = -EFAULT;
- } else {
- if (wmi_get_wow_list_cmd(ar->arWmi,
- &getWowList) != 0)
- {
- ret = -EIO;
- }
- }
- break;
- }
- case AR6000_XIOCTL_WMI_ADD_WOW_PATTERN:
- {
-#define WOW_PATTERN_SIZE 64
-#define WOW_MASK_SIZE 64
-
- WMI_ADD_WOW_PATTERN_CMD cmd;
- u8 mask_data[WOW_PATTERN_SIZE]={0};
- u8 pattern_data[WOW_PATTERN_SIZE]={0};
-
- do {
- if (ar->arWmiReady == false) {
- ret = -EIO;
- break;
- }
- if(copy_from_user(&cmd, userdata,
- sizeof(WMI_ADD_WOW_PATTERN_CMD)))
- {
- ret = -EFAULT;
- break;
- }
- if (copy_from_user(pattern_data,
- userdata + 3,
- cmd.filter_size))
- {
- ret = -EFAULT;
- break;
- }
- if (copy_from_user(mask_data,
- (userdata + 3 + cmd.filter_size),
- cmd.filter_size))
- {
- ret = -EFAULT;
- break;
- }
- if (wmi_add_wow_pattern_cmd(ar->arWmi,
- &cmd, pattern_data, mask_data, cmd.filter_size) != 0)
- {
- ret = -EIO;
- }
- } while(false);
-#undef WOW_PATTERN_SIZE
-#undef WOW_MASK_SIZE
- break;
- }
- case AR6000_XIOCTL_WMI_DEL_WOW_PATTERN:
- {
- WMI_DEL_WOW_PATTERN_CMD delWowPattern;
-
- if (ar->arWmiReady == false) {
- ret = -EIO;
- } else if (copy_from_user(&delWowPattern, userdata,
- sizeof(delWowPattern)))
- {
- ret = -EFAULT;
- } else {
- if (wmi_del_wow_pattern_cmd(ar->arWmi,
- &delWowPattern) != 0)
- {
- ret = -EIO;
- }
- }
- break;
- }
- case AR6000_XIOCTL_DUMP_HTC_CREDIT_STATE:
- if (ar->arHtcTarget != NULL) {
-#ifdef ATH_DEBUG_MODULE
- HTCDumpCreditStates(ar->arHtcTarget);
-#endif /* ATH_DEBUG_MODULE */
-#ifdef HTC_EP_STAT_PROFILING
- {
- struct htc_endpoint_stats stats;
- int i;
-
- for (i = 0; i < 5; i++) {
- if (HTCGetEndpointStatistics(ar->arHtcTarget,
- i,
- HTC_EP_STAT_SAMPLE_AND_CLEAR,
- &stats)) {
- A_PRINTF(KERN_ALERT"------- Profiling Endpoint : %d \n", i);
- A_PRINTF(KERN_ALERT"TxCreditLowIndications : %d \n", stats.TxCreditLowIndications);
- A_PRINTF(KERN_ALERT"TxIssued : %d \n", stats.TxIssued);
- A_PRINTF(KERN_ALERT"TxDropped: %d \n", stats.TxDropped);
- A_PRINTF(KERN_ALERT"TxPacketsBundled : %d \n", stats.TxPacketsBundled);
- A_PRINTF(KERN_ALERT"TxBundles : %d \n", stats.TxBundles);
- A_PRINTF(KERN_ALERT"TxCreditRpts : %d \n", stats.TxCreditRpts);
- A_PRINTF(KERN_ALERT"TxCreditsRptsFromRx : %d \n", stats.TxCreditRptsFromRx);
- A_PRINTF(KERN_ALERT"TxCreditsRptsFromOther : %d \n", stats.TxCreditRptsFromOther);
- A_PRINTF(KERN_ALERT"TxCreditsRptsFromEp0 : %d \n", stats.TxCreditRptsFromEp0);
- A_PRINTF(KERN_ALERT"TxCreditsFromRx : %d \n", stats.TxCreditsFromRx);
- A_PRINTF(KERN_ALERT"TxCreditsFromOther : %d \n", stats.TxCreditsFromOther);
- A_PRINTF(KERN_ALERT"TxCreditsFromEp0 : %d \n", stats.TxCreditsFromEp0);
- A_PRINTF(KERN_ALERT"TxCreditsConsummed : %d \n", stats.TxCreditsConsummed);
- A_PRINTF(KERN_ALERT"TxCreditsReturned : %d \n", stats.TxCreditsReturned);
- A_PRINTF(KERN_ALERT"RxReceived : %d \n", stats.RxReceived);
- A_PRINTF(KERN_ALERT"RxPacketsBundled : %d \n", stats.RxPacketsBundled);
- A_PRINTF(KERN_ALERT"RxLookAheads : %d \n", stats.RxLookAheads);
- A_PRINTF(KERN_ALERT"RxBundleLookAheads : %d \n", stats.RxBundleLookAheads);
- A_PRINTF(KERN_ALERT"RxBundleIndFromHdr : %d \n", stats.RxBundleIndFromHdr);
- A_PRINTF(KERN_ALERT"RxAllocThreshHit : %d \n", stats.RxAllocThreshHit);
- A_PRINTF(KERN_ALERT"RxAllocThreshBytes : %d \n", stats.RxAllocThreshBytes);
- A_PRINTF(KERN_ALERT"---- \n");
-
- }
- }
- }
-#endif
- }
- break;
- case AR6000_XIOCTL_TRAFFIC_ACTIVITY_CHANGE:
- if (ar->arHtcTarget != NULL) {
- struct ar6000_traffic_activity_change data;
-
- if (copy_from_user(&data, userdata, sizeof(data)))
- {
- ret = -EFAULT;
- goto ioctl_done;
- }
- /* note, this is used for testing (mbox ping testing), indicate activity
- * change using the stream ID as the traffic class */
- ar6000_indicate_tx_activity(ar,
- (u8)data.StreamID,
- data.Active ? true : false);
- }
- break;
- case AR6000_XIOCTL_WMI_SET_CONNECT_CTRL_FLAGS:
- if (ar->arWmiReady == false) {
- ret = -EIO;
- } else if (copy_from_user(&connectCtrlFlags, userdata,
- sizeof(connectCtrlFlags)))
- {
- ret = -EFAULT;
- } else {
- ar->arConnectCtrlFlags = connectCtrlFlags;
- }
- break;
- case AR6000_XIOCTL_WMI_SET_AKMP_PARAMS:
- if (ar->arWmiReady == false) {
- ret = -EIO;
- } else if (copy_from_user(&akmpParams, userdata,
- sizeof(WMI_SET_AKMP_PARAMS_CMD)))
- {
- ret = -EFAULT;
- } else {
- if (wmi_set_akmp_params_cmd(ar->arWmi, &akmpParams) != 0) {
- ret = -EIO;
- }
- }
- break;
- case AR6000_XIOCTL_WMI_SET_PMKID_LIST:
- if (ar->arWmiReady == false) {
- ret = -EIO;
- } else {
- if (copy_from_user(&pmkidInfo.numPMKID, userdata,
- sizeof(pmkidInfo.numPMKID)))
- {
- ret = -EFAULT;
- break;
- }
- if (copy_from_user(&pmkidInfo.pmkidList,
- userdata + sizeof(pmkidInfo.numPMKID),
- pmkidInfo.numPMKID * sizeof(WMI_PMKID)))
- {
- ret = -EFAULT;
- break;
- }
- if (wmi_set_pmkid_list_cmd(ar->arWmi, &pmkidInfo) != 0) {
- ret = -EIO;
- }
- }
- break;
- case AR6000_XIOCTL_WMI_GET_PMKID_LIST:
- if (ar->arWmiReady == false) {
- ret = -EIO;
- } else {
- if (wmi_get_pmkid_list_cmd(ar->arWmi) != 0) {
- ret = -EIO;
- }
- }
- break;
- case AR6000_XIOCTL_WMI_ABORT_SCAN:
- if (ar->arWmiReady == false) {
- ret = -EIO;
- }
- ret = wmi_abort_scan_cmd(ar->arWmi);
- break;
- case AR6000_XIOCTL_AP_HIDDEN_SSID:
- {
- u8 hidden_ssid;
- if (ar->arWmiReady == false) {
- ret = -EIO;
- } else if (copy_from_user(&hidden_ssid, userdata, sizeof(hidden_ssid))) {
- ret = -EFAULT;
- } else {
- wmi_ap_set_hidden_ssid(ar->arWmi, hidden_ssid);
- ar->ap_hidden_ssid = hidden_ssid;
- ar->ap_profile_flag = 1; /* There is a change in profile */
- }
- break;
- }
- case AR6000_XIOCTL_AP_GET_STA_LIST:
- {
- if (ar->arWmiReady == false) {
- ret = -EIO;
- } else {
- u8 i;
- ap_get_sta_t temp;
- A_MEMZERO(&temp, sizeof(temp));
- for(i=0;i<AP_MAX_NUM_STA;i++) {
- memcpy(temp.sta[i].mac, ar->sta_list[i].mac, ATH_MAC_LEN);
- temp.sta[i].aid = ar->sta_list[i].aid;
- temp.sta[i].keymgmt = ar->sta_list[i].keymgmt;
- temp.sta[i].ucipher = ar->sta_list[i].ucipher;
- temp.sta[i].auth = ar->sta_list[i].auth;
- }
- if(copy_to_user((ap_get_sta_t *)rq->ifr_data, &temp,
- sizeof(ar->sta_list))) {
- ret = -EFAULT;
- }
- }
- break;
- }
- case AR6000_XIOCTL_AP_SET_NUM_STA:
- {
- u8 num_sta;
- if (ar->arWmiReady == false) {
- ret = -EIO;
- } else if (copy_from_user(&num_sta, userdata, sizeof(num_sta))) {
- ret = -EFAULT;
- } else if(num_sta > AP_MAX_NUM_STA) {
- /* value out of range */
- ret = -EINVAL;
- } else {
- wmi_ap_set_num_sta(ar->arWmi, num_sta);
- }
- break;
- }
- case AR6000_XIOCTL_AP_SET_ACL_POLICY:
- {
- u8 policy;
- if (ar->arWmiReady == false) {
- ret = -EIO;
- } else if (copy_from_user(&policy, userdata, sizeof(policy))) {
- ret = -EFAULT;
- } else if(policy == ar->g_acl.policy) {
- /* No change in policy */
- } else {
- if(!(policy & AP_ACL_RETAIN_LIST_MASK)) {
- /* clear ACL list */
- memset(&ar->g_acl,0,sizeof(WMI_AP_ACL));
- }
- ar->g_acl.policy = policy;
- wmi_ap_set_acl_policy(ar->arWmi, policy);
- }
- break;
- }
- case AR6000_XIOCTL_AP_SET_ACL_MAC:
- {
- WMI_AP_ACL_MAC_CMD acl;
- if (ar->arWmiReady == false) {
- ret = -EIO;
- } else if (copy_from_user(&acl, userdata, sizeof(acl))) {
- ret = -EFAULT;
- } else {
- if(acl_add_del_mac(&ar->g_acl, &acl)) {
- wmi_ap_acl_mac_list(ar->arWmi, &acl);
- } else {
- A_PRINTF("ACL list error\n");
- ret = -EIO;
- }
- }
- break;
- }
- case AR6000_XIOCTL_AP_GET_ACL_LIST:
- {
- if (ar->arWmiReady == false) {
- ret = -EIO;
- } else if(copy_to_user((WMI_AP_ACL *)rq->ifr_data, &ar->g_acl,
- sizeof(WMI_AP_ACL))) {
- ret = -EFAULT;
- }
- break;
- }
- case AR6000_XIOCTL_AP_COMMIT_CONFIG:
- {
- ret = ar6000_ap_mode_profile_commit(ar);
- break;
- }
- case IEEE80211_IOCTL_GETWPAIE:
- {
- struct ieee80211req_wpaie wpaie;
- if (ar->arWmiReady == false) {
- ret = -EIO;
- } else if (copy_from_user(&wpaie, userdata, sizeof(wpaie))) {
- ret = -EFAULT;
- } else if (ar6000_ap_mode_get_wpa_ie(ar, &wpaie)) {
- ret = -EFAULT;
- } else if(copy_to_user(userdata, &wpaie, sizeof(wpaie))) {
- ret = -EFAULT;
- }
- break;
- }
- case AR6000_XIOCTL_AP_CONN_INACT_TIME:
- {
- u32 period;
- if (ar->arWmiReady == false) {
- ret = -EIO;
- } else if (copy_from_user(&period, userdata, sizeof(period))) {
- ret = -EFAULT;
- } else {
- wmi_ap_conn_inact_time(ar->arWmi, period);
- }
- break;
- }
- case AR6000_XIOCTL_AP_PROT_SCAN_TIME:
- {
- WMI_AP_PROT_SCAN_TIME_CMD bgscan;
- if (ar->arWmiReady == false) {
- ret = -EIO;
- } else if (copy_from_user(&bgscan, userdata, sizeof(bgscan))) {
- ret = -EFAULT;
- } else {
- wmi_ap_bgscan_time(ar->arWmi, bgscan.period_min, bgscan.dwell_ms);
- }
- break;
- }
- case AR6000_XIOCTL_AP_SET_COUNTRY:
- {
- ret = ar6000_ioctl_set_country(dev, rq);
- break;
- }
- case AR6000_XIOCTL_AP_SET_DTIM:
- {
- WMI_AP_SET_DTIM_CMD d;
- if (ar->arWmiReady == false) {
- ret = -EIO;
- } else if (copy_from_user(&d, userdata, sizeof(d))) {
- ret = -EFAULT;
- } else {
- if(d.dtim > 0 && d.dtim < 11) {
- ar->ap_dtim_period = d.dtim;
- wmi_ap_set_dtim(ar->arWmi, d.dtim);
- ar->ap_profile_flag = 1; /* There is a change in profile */
- } else {
- A_PRINTF("DTIM out of range. Valid range is [1-10]\n");
- ret = -EIO;
- }
- }
- break;
- }
- case AR6000_XIOCTL_WMI_TARGET_EVENT_REPORT:
- {
- WMI_SET_TARGET_EVENT_REPORT_CMD evtCfgCmd;
-
- if (ar->arWmiReady == false) {
- ret = -EIO;
- }
- if (copy_from_user(&evtCfgCmd, userdata,
- sizeof(evtCfgCmd))) {
- ret = -EFAULT;
- break;
- }
- ret = wmi_set_target_event_report_cmd(ar->arWmi, &evtCfgCmd);
- break;
- }
- case AR6000_XIOCTL_AP_INTRA_BSS_COMM:
- {
- u8 intra=0;
- if (ar->arWmiReady == false) {
- ret = -EIO;
- } else if (copy_from_user(&intra, userdata, sizeof(intra))) {
- ret = -EFAULT;
- } else {
- ar->intra_bss = (intra?1:0);
- }
- break;
- }
- case AR6000_XIOCTL_DUMP_MODULE_DEBUG_INFO:
- {
- struct drv_debug_module_s moduleinfo;
-
- if (copy_from_user(&moduleinfo, userdata, sizeof(moduleinfo))) {
- ret = -EFAULT;
- break;
- }
-
- a_dump_module_debug_info_by_name(moduleinfo.modulename);
- ret = 0;
- break;
- }
- case AR6000_XIOCTL_MODULE_DEBUG_SET_MASK:
- {
- struct drv_debug_module_s moduleinfo;
-
- if (copy_from_user(&moduleinfo, userdata, sizeof(moduleinfo))) {
- ret = -EFAULT;
- break;
- }
-
- if (a_set_module_mask(moduleinfo.modulename, moduleinfo.mask)) {
- ret = -EFAULT;
- }
-
- break;
- }
- case AR6000_XIOCTL_MODULE_DEBUG_GET_MASK:
- {
- struct drv_debug_module_s moduleinfo;
-
- if (copy_from_user(&moduleinfo, userdata, sizeof(moduleinfo))) {
- ret = -EFAULT;
- break;
- }
-
- if (a_get_module_mask(moduleinfo.modulename, &moduleinfo.mask)) {
- ret = -EFAULT;
- break;
- }
-
- if (copy_to_user(userdata, &moduleinfo, sizeof(moduleinfo))) {
- ret = -EFAULT;
- break;
- }
-
- break;
- }
-#ifdef ATH_AR6K_11N_SUPPORT
- case AR6000_XIOCTL_DUMP_RCV_AGGR_STATS:
- {
- PACKET_LOG *copy_of_pkt_log;
-
- aggr_dump_stats(ar->aggr_cntxt, ©_of_pkt_log);
- if (copy_to_user(rq->ifr_data, copy_of_pkt_log, sizeof(PACKET_LOG))) {
- ret = -EFAULT;
- }
- break;
- }
- case AR6000_XIOCTL_SETUP_AGGR:
- {
- WMI_ADDBA_REQ_CMD cmd;
-
- if (ar->arWmiReady == false) {
- ret = -EIO;
- } else if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
- ret = -EFAULT;
- } else {
- wmi_setup_aggr_cmd(ar->arWmi, cmd.tid);
- }
- }
- break;
-
- case AR6000_XIOCTL_DELE_AGGR:
- {
- WMI_DELBA_REQ_CMD cmd;
-
- if (ar->arWmiReady == false) {
- ret = -EIO;
- } else if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
- ret = -EFAULT;
- } else {
- wmi_delete_aggr_cmd(ar->arWmi, cmd.tid, cmd.is_sender_initiator);
- }
- }
- break;
-
- case AR6000_XIOCTL_ALLOW_AGGR:
- {
- WMI_ALLOW_AGGR_CMD cmd;
-
- if (ar->arWmiReady == false) {
- ret = -EIO;
- } else if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
- ret = -EFAULT;
- } else {
- wmi_allow_aggr_cmd(ar->arWmi, cmd.tx_allow_aggr, cmd.rx_allow_aggr);
- }
- }
- break;
-
- case AR6000_XIOCTL_SET_HT_CAP:
- {
- if (ar->arWmiReady == false) {
- ret = -EIO;
- } else if (copy_from_user(&htCap, userdata,
- sizeof(htCap)))
- {
- ret = -EFAULT;
- } else {
-
- if (wmi_set_ht_cap_cmd(ar->arWmi, &htCap) != 0)
- {
- ret = -EIO;
- }
- }
- break;
- }
- case AR6000_XIOCTL_SET_HT_OP:
- {
- if (ar->arWmiReady == false) {
- ret = -EIO;
- } else if (copy_from_user(&htOp, userdata,
- sizeof(htOp)))
- {
- ret = -EFAULT;
- } else {
-
- if (wmi_set_ht_op_cmd(ar->arWmi, htOp.sta_chan_width) != 0)
- {
- ret = -EIO;
- }
- }
- break;
- }
-#endif
- case AR6000_XIOCTL_ACL_DATA:
- {
- void *osbuf = NULL;
- if (ar->arWmiReady == false) {
- ret = -EIO;
- } else if (ar6000_create_acl_data_osbuf(dev, (u8 *)userdata, &osbuf) != 0) {
- ret = -EIO;
- } else {
- if (wmi_data_hdr_add(ar->arWmi, osbuf, DATA_MSGTYPE, 0, WMI_DATA_HDR_DATA_TYPE_ACL,0,NULL) != 0) {
- AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("XIOCTL_ACL_DATA - wmi_data_hdr_add failed\n"));
- } else {
- /* Send data buffer over HTC */
- ar6000_acl_data_tx(osbuf, ar->arNetDev);
- }
- }
- break;
- }
- case AR6000_XIOCTL_HCI_CMD:
- {
- char tmp_buf[512];
- s8 i;
- WMI_HCI_CMD *cmd = (WMI_HCI_CMD *)tmp_buf;
- u8 size;
-
- size = sizeof(cmd->cmd_buf_sz);
- if (ar->arWmiReady == false) {
- ret = -EIO;
- } else if (copy_from_user(cmd, userdata, size)) {
- ret = -EFAULT;
- } else if(copy_from_user(cmd->buf, userdata + size, cmd->cmd_buf_sz)) {
- ret = -EFAULT;
- } else {
- if (wmi_send_hci_cmd(ar->arWmi, cmd->buf, cmd->cmd_buf_sz) != 0) {
- ret = -EIO;
- }else if(loghci) {
- A_PRINTF_LOG("HCI Command To PAL --> \n");
- for(i = 0; i < cmd->cmd_buf_sz; i++) {
- A_PRINTF_LOG("0x%02x ",cmd->buf[i]);
- if((i % 10) == 0) {
- A_PRINTF_LOG("\n");
- }
- }
- A_PRINTF_LOG("\n");
- A_PRINTF_LOG("==================================\n");
- }
- }
- break;
- }
- case AR6000_XIOCTL_WLAN_CONN_PRECEDENCE:
- {
- WMI_SET_BT_WLAN_CONN_PRECEDENCE cmd;
- if (ar->arWmiReady == false) {
- ret = -EIO;
- } else if (copy_from_user(&cmd, userdata, sizeof(cmd))) {
- ret = -EFAULT;
- } else {
- if (cmd.precedence == BT_WLAN_CONN_PRECDENCE_WLAN ||
- cmd.precedence == BT_WLAN_CONN_PRECDENCE_PAL) {
- if ( wmi_set_wlan_conn_precedence_cmd(ar->arWmi, cmd.precedence) != 0) {
- ret = -EIO;
- }
- } else {
- ret = -EINVAL;
- }
- }
- break;
- }
- case AR6000_XIOCTL_AP_GET_STAT:
- {
- ret = ar6000_ioctl_get_ap_stats(dev, rq);
- break;
- }
- case AR6000_XIOCTL_SET_TX_SELECT_RATES:
- {
- WMI_SET_TX_SELECT_RATES_CMD masks;
-
- if (ar->arWmiReady == false) {
- ret = -EIO;
- } else if (copy_from_user(&masks, userdata,
- sizeof(masks)))
- {
- ret = -EFAULT;
- } else {
-
- if (wmi_set_tx_select_rates_cmd(ar->arWmi, masks.rateMasks) != 0)
- {
- ret = -EIO;
- }
- }
- break;
- }
- case AR6000_XIOCTL_AP_GET_HIDDEN_SSID:
- {
- WMI_AP_HIDDEN_SSID_CMD ssid;
- ssid.hidden_ssid = ar->ap_hidden_ssid;
-
- if (ar->arWmiReady == false) {
- ret = -EIO;
- } else if(copy_to_user((WMI_AP_HIDDEN_SSID_CMD *)rq->ifr_data,
- &ssid, sizeof(WMI_AP_HIDDEN_SSID_CMD))) {
- ret = -EFAULT;
- }
- break;
- }
- case AR6000_XIOCTL_AP_GET_COUNTRY:
- {
- WMI_AP_SET_COUNTRY_CMD cty;
- memcpy(cty.countryCode, ar->ap_country_code, 3);
-
- if (ar->arWmiReady == false) {
- ret = -EIO;
- } else if(copy_to_user((WMI_AP_SET_COUNTRY_CMD *)rq->ifr_data,
- &cty, sizeof(WMI_AP_SET_COUNTRY_CMD))) {
- ret = -EFAULT;
- }
- break;
- }
- case AR6000_XIOCTL_AP_GET_WMODE:
- {
- if (ar->arWmiReady == false) {
- ret = -EIO;
- } else if(copy_to_user((u8 *)rq->ifr_data,
- &ar->ap_wmode, sizeof(u8))) {
- ret = -EFAULT;
- }
- break;
- }
- case AR6000_XIOCTL_AP_GET_DTIM:
- {
- WMI_AP_SET_DTIM_CMD dtim;
- dtim.dtim = ar->ap_dtim_period;
-
- if (ar->arWmiReady == false) {
- ret = -EIO;
- } else if(copy_to_user((WMI_AP_SET_DTIM_CMD *)rq->ifr_data,
- &dtim, sizeof(WMI_AP_SET_DTIM_CMD))) {
- ret = -EFAULT;
- }
- break;
- }
- case AR6000_XIOCTL_AP_GET_BINTVL:
- {
- WMI_BEACON_INT_CMD bi;
- bi.beaconInterval = ar->ap_beacon_interval;
-
- if (ar->arWmiReady == false) {
- ret = -EIO;
- } else if(copy_to_user((WMI_BEACON_INT_CMD *)rq->ifr_data,
- &bi, sizeof(WMI_BEACON_INT_CMD))) {
- ret = -EFAULT;
- }
- break;
- }
- case AR6000_XIOCTL_AP_GET_RTS:
- {
- WMI_SET_RTS_CMD rts;
- rts.threshold = ar->arRTS;
-
- if (ar->arWmiReady == false) {
- ret = -EIO;
- } else if(copy_to_user((WMI_SET_RTS_CMD *)rq->ifr_data,
- &rts, sizeof(WMI_SET_RTS_CMD))) {
- ret = -EFAULT;
- }
- break;
- }
- case AR6000_XIOCTL_FETCH_TARGET_REGS:
- {
- u32 targregs[AR6003_FETCH_TARG_REGS_COUNT];
-
- if (ar->arTargetType == TARGET_TYPE_AR6003) {
- ar6k_FetchTargetRegs(hifDevice, targregs);
- if (copy_to_user((u32 *)rq->ifr_data, &targregs, sizeof(targregs)))
- {
- ret = -EFAULT;
- }
- } else {
- ret = -EOPNOTSUPP;
- }
- break;
- }
- case AR6000_XIOCTL_AP_SET_11BG_RATESET:
- {
- WMI_AP_SET_11BG_RATESET_CMD rate;
- if (ar->arWmiReady == false) {
- ret = -EIO;
- } else if (copy_from_user(&rate, userdata, sizeof(rate))) {
- ret = -EFAULT;
- } else {
- wmi_ap_set_rateset(ar->arWmi, rate.rateset);
- }
- break;
- }
- case AR6000_XIOCTL_GET_WLAN_SLEEP_STATE:
- {
- WMI_REPORT_SLEEP_STATE_EVENT wmiSleepEvent ;
-
- if (ar->arWlanState == WLAN_ENABLED) {
- wmiSleepEvent.sleepState = WMI_REPORT_SLEEP_STATUS_IS_AWAKE;
- } else {
- wmiSleepEvent.sleepState = WMI_REPORT_SLEEP_STATUS_IS_DEEP_SLEEP;
- }
- rq->ifr_ifru.ifru_ivalue = ar->arWlanState; /* return value */
-
- ar6000_send_event_to_app(ar, WMI_REPORT_SLEEP_STATE_EVENTID, (u8 *)&wmiSleepEvent,
- sizeof(WMI_REPORT_SLEEP_STATE_EVENTID));
- break;
- }
-#ifdef CONFIG_PM
- case AR6000_XIOCTL_SET_BT_HW_POWER_STATE:
- {
- unsigned int state;
- if (get_user(state, (unsigned int *)userdata)) {
- ret = -EFAULT;
- break;
- }
- if (ar6000_set_bt_hw_state(ar, state)!= 0) {
- ret = -EIO;
- }
- }
- break;
- case AR6000_XIOCTL_GET_BT_HW_POWER_STATE:
- rq->ifr_ifru.ifru_ivalue = !ar->arBTOff; /* return value */
- break;
-#endif
-
- case AR6000_XIOCTL_WMI_SET_TX_SGI_PARAM:
- {
- WMI_SET_TX_SGI_PARAM_CMD SGICmd;
-
- if (ar->arWmiReady == false) {
- ret = -EIO;
- } else if (copy_from_user(&SGICmd, userdata,
- sizeof(SGICmd))){
- ret = -EFAULT;
- } else{
- if (wmi_SGI_cmd(ar->arWmi, SGICmd.sgiMask, SGICmd.sgiPERThreshold) != 0) {
- ret = -EIO;
- }
-
- }
- break;
- }
-
- case AR6000_XIOCTL_ADD_AP_INTERFACE:
-#ifdef CONFIG_AP_VIRTUAL_ADAPTER_SUPPORT
- {
- char ap_ifname[IFNAMSIZ] = {0,};
- if (copy_from_user(ap_ifname, userdata, IFNAMSIZ)) {
- ret = -EFAULT;
- } else {
- if (ar6000_add_ap_interface(ar, ap_ifname) != 0) {
- ret = -EIO;
- }
- }
- }
-#else
- ret = -EOPNOTSUPP;
-#endif
- break;
- case AR6000_XIOCTL_REMOVE_AP_INTERFACE:
-#ifdef CONFIG_AP_VIRTUAL_ADAPTER_SUPPORT
- if (ar6000_remove_ap_interface(ar) != 0) {
- ret = -EIO;
- }
-#else
- ret = -EOPNOTSUPP;
-#endif
- break;
-
- case AR6000_XIOCTL_WMI_SET_EXCESS_TX_RETRY_THRES:
- {
- ret = ar6000_xioctl_set_excess_tx_retry_thres_cmd(dev, userdata);
- break;
- }
-
- default:
- ret = -EOPNOTSUPP;
- }
-
-ioctl_done:
- rtnl_lock(); /* restore rtnl state */
- dev_put(dev);
-
- return ret;
-}
-
-u8 mac_cmp_wild(u8 *mac, u8 *new_mac, u8 wild, u8 new_wild)
-{
- u8 i;
-
- for(i=0;i<ATH_MAC_LEN;i++) {
- if((wild & 1<<i) && (new_wild & 1<<i)) continue;
- if(mac[i] != new_mac[i]) return 1;
- }
- if((memcmp(new_mac, null_mac, 6)==0) && new_wild &&
- (wild != new_wild)) {
- return 1;
- }
-
- return 0;
-}
-
-u8 acl_add_del_mac(WMI_AP_ACL *a, WMI_AP_ACL_MAC_CMD *acl)
-{
- s8 already_avail=-1, free_slot=-1, i;
-
- /* To check whether this mac is already there in our list */
- for(i=AP_ACL_SIZE-1;i>=0;i--)
- {
- if(mac_cmp_wild(a->acl_mac[i], acl->mac, a->wildcard[i],
- acl->wildcard)==0)
- already_avail = i;
-
- if(!((1 << i) & a->index))
- free_slot = i;
- }
-
- if(acl->action == ADD_MAC_ADDR)
- {
- /* Dont add mac if it is already available */
- if((already_avail >= 0) || (free_slot == -1))
- return 0;
-
- memcpy(a->acl_mac[free_slot], acl->mac, ATH_MAC_LEN);
- a->index = a->index | (1 << free_slot);
- acl->index = free_slot;
- a->wildcard[free_slot] = acl->wildcard;
- return 1;
- }
- else if(acl->action == DEL_MAC_ADDR)
- {
- if(acl->index > AP_ACL_SIZE)
- return 0;
-
- if(!(a->index & (1 << acl->index)))
- return 0;
-
- A_MEMZERO(a->acl_mac[acl->index],ATH_MAC_LEN);
- a->index = a->index & ~(1 << acl->index);
- a->wildcard[acl->index] = 0;
- return 1;
- }
-
- return 0;
-}
diff --git a/drivers/staging/ath6kl/os/linux/netbuf.c b/drivers/staging/ath6kl/os/linux/netbuf.c
index a9c96b3..963a2fb 100644
--- a/drivers/staging/ath6kl/os/linux/netbuf.c
+++ b/drivers/staging/ath6kl/os/linux/netbuf.c
@@ -22,7 +22,6 @@
//------------------------------------------------------------------------------
#include <a_config.h>
#include "athdefs.h"
-#include "a_types.h"
#include "a_osapi.h"
#include "htc_packet.h"
diff --git a/drivers/staging/ath6kl/os/linux/wireless_ext.c b/drivers/staging/ath6kl/os/linux/wireless_ext.c
deleted file mode 100644
index 4b77943..0000000
--- a/drivers/staging/ath6kl/os/linux/wireless_ext.c
+++ /dev/null
@@ -1,2723 +0,0 @@
-//------------------------------------------------------------------------------
-// Copyright (c) 2004-2010 Atheros Communications Inc.
-// All rights reserved.
-//
-//
-//
-// Permission to use, copy, modify, and/or distribute this software for any
-// purpose with or without fee is hereby granted, provided that the above
-// copyright notice and this permission notice appear in all copies.
-//
-// THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-// WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-// MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-// ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-// WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-// ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-// OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
-//
-//
-//
-// Author(s): ="Atheros"
-//------------------------------------------------------------------------------
-
-#include "ar6000_drv.h"
-
-#define IWE_STREAM_ADD_EVENT(p1, p2, p3, p4, p5) \
- iwe_stream_add_event((p1), (p2), (p3), (p4), (p5))
-
-#define IWE_STREAM_ADD_POINT(p1, p2, p3, p4, p5) \
- iwe_stream_add_point((p1), (p2), (p3), (p4), (p5))
-
-#define IWE_STREAM_ADD_VALUE(p1, p2, p3, p4, p5, p6) \
- iwe_stream_add_value((p1), (p2), (p3), (p4), (p5), (p6))
-
-static void ar6000_set_quality(struct iw_quality *iq, s8 rssi);
-extern unsigned int wmitimeout;
-extern A_WAITQUEUE_HEAD arEvent;
-
-#if WIRELESS_EXT > 14
-/*
- * Encode a WPA or RSN information element as a custom
- * element using the hostap format.
- */
-static u_int
-encode_ie(void *buf, size_t bufsize,
- const u_int8_t *ie, size_t ielen,
- const char *leader, size_t leader_len)
-{
- u_int8_t *p;
- int i;
-
- if (bufsize < leader_len)
- return 0;
- p = buf;
- memcpy(p, leader, leader_len);
- bufsize -= leader_len;
- p += leader_len;
- for (i = 0; i < ielen && bufsize > 2; i++)
- {
- p += sprintf((char*)p, "%02x", ie[i]);
- bufsize -= 2;
- }
- return (i == ielen ? p - (u_int8_t *)buf : 0);
-}
-#endif /* WIRELESS_EXT > 14 */
-
-static u8 get_bss_phy_capability(bss_t *bss)
-{
- u8 capability = 0;
- struct ieee80211_common_ie *cie = &bss->ni_cie;
-#define CHAN_IS_11A(x) (!((x >= 2412) && (x <= 2484)))
- if (CHAN_IS_11A(cie->ie_chan)) {
- if (cie->ie_htcap) {
- capability = WMI_11NA_CAPABILITY;
- } else {
- capability = WMI_11A_CAPABILITY;
- }
- } else if ((cie->ie_erp) || (cie->ie_xrates)) {
- if (cie->ie_htcap) {
- capability = WMI_11NG_CAPABILITY;
- } else {
- capability = WMI_11G_CAPABILITY;
- }
- }
- return capability;
-}
-
-void
-ar6000_scan_node(void *arg, bss_t *ni)
-{
- struct iw_event iwe;
-#if WIRELESS_EXT > 14
- char buf[256];
-#endif
- struct ar_giwscan_param *param;
- char *current_ev;
- char *end_buf;
- struct ieee80211_common_ie *cie;
- char *current_val;
- s32 j;
- u32 rate_len, data_len = 0;
-
- param = (struct ar_giwscan_param *)arg;
-
- current_ev = param->current_ev;
- end_buf = param->end_buf;
-
- cie = &ni->ni_cie;
-
- if ((end_buf - current_ev) > IW_EV_ADDR_LEN)
- {
- A_MEMZERO(&iwe, sizeof(iwe));
- iwe.cmd = SIOCGIWAP;
- iwe.u.ap_addr.sa_family = ARPHRD_ETHER;
- memcpy(iwe.u.ap_addr.sa_data, ni->ni_macaddr, 6);
- current_ev = IWE_STREAM_ADD_EVENT(param->info, current_ev, end_buf,
- &iwe, IW_EV_ADDR_LEN);
- }
- param->bytes_needed += IW_EV_ADDR_LEN;
-
- data_len = cie->ie_ssid[1] + IW_EV_POINT_LEN;
- if ((end_buf - current_ev) > data_len)
- {
- A_MEMZERO(&iwe, sizeof(iwe));
- iwe.cmd = SIOCGIWESSID;
- iwe.u.data.flags = 1;
- iwe.u.data.length = cie->ie_ssid[1];
- current_ev = IWE_STREAM_ADD_POINT(param->info, current_ev, end_buf,
- &iwe, (char*)&cie->ie_ssid[2]);
- }
- param->bytes_needed += data_len;
-
- if (cie->ie_capInfo & (IEEE80211_CAPINFO_ESS|IEEE80211_CAPINFO_IBSS)) {
- if ((end_buf - current_ev) > IW_EV_UINT_LEN)
- {
- A_MEMZERO(&iwe, sizeof(iwe));
- iwe.cmd = SIOCGIWMODE;
- iwe.u.mode = cie->ie_capInfo & IEEE80211_CAPINFO_ESS ?
- IW_MODE_MASTER : IW_MODE_ADHOC;
- current_ev = IWE_STREAM_ADD_EVENT(param->info, current_ev, end_buf,
- &iwe, IW_EV_UINT_LEN);
- }
- param->bytes_needed += IW_EV_UINT_LEN;
- }
-
- if ((end_buf - current_ev) > IW_EV_FREQ_LEN)
- {
- A_MEMZERO(&iwe, sizeof(iwe));
- iwe.cmd = SIOCGIWFREQ;
- iwe.u.freq.m = cie->ie_chan * 100000;
- iwe.u.freq.e = 1;
- current_ev = IWE_STREAM_ADD_EVENT(param->info, current_ev, end_buf,
- &iwe, IW_EV_FREQ_LEN);
- }
- param->bytes_needed += IW_EV_FREQ_LEN;
-
- if ((end_buf - current_ev) > IW_EV_QUAL_LEN)
- {
- A_MEMZERO(&iwe, sizeof(iwe));
- iwe.cmd = IWEVQUAL;
- ar6000_set_quality(&iwe.u.qual, ni->ni_snr);
- current_ev = IWE_STREAM_ADD_EVENT(param->info, current_ev, end_buf,
- &iwe, IW_EV_QUAL_LEN);
- }
- param->bytes_needed += IW_EV_QUAL_LEN;
-
- if ((end_buf - current_ev) > IW_EV_POINT_LEN)
- {
- A_MEMZERO(&iwe, sizeof(iwe));
- iwe.cmd = SIOCGIWENCODE;
- if (cie->ie_capInfo & IEEE80211_CAPINFO_PRIVACY) {
- iwe.u.data.flags = IW_ENCODE_ENABLED | IW_ENCODE_NOKEY;
- } else {
- iwe.u.data.flags = IW_ENCODE_DISABLED;
- }
- iwe.u.data.length = 0;
- current_ev = IWE_STREAM_ADD_POINT(param->info, current_ev, end_buf,
- &iwe, "");
- }
- param->bytes_needed += IW_EV_POINT_LEN;
-
- /* supported bit rate */
- A_MEMZERO(&iwe, sizeof(iwe));
- iwe.cmd = SIOCGIWRATE;
- iwe.u.bitrate.fixed = 0;
- iwe.u.bitrate.disabled = 0;
- iwe.u.bitrate.value = 0;
- current_val = current_ev + IW_EV_LCP_LEN;
- param->bytes_needed += IW_EV_LCP_LEN;
-
- if (cie->ie_rates != NULL) {
- rate_len = cie->ie_rates[1];
- data_len = (rate_len * (IW_EV_PARAM_LEN - IW_EV_LCP_LEN));
- if ((end_buf - current_ev) > data_len)
- {
- for (j = 0; j < rate_len; j++) {
- unsigned char val;
- val = cie->ie_rates[2 + j];
- iwe.u.bitrate.value =
- (val >= 0x80)? ((val - 0x80) * 500000): (val * 500000);
- current_val = IWE_STREAM_ADD_VALUE(param->info, current_ev,
- current_val, end_buf,
- &iwe, IW_EV_PARAM_LEN);
- }
- }
- param->bytes_needed += data_len;
- }
-
- if (cie->ie_xrates != NULL) {
- rate_len = cie->ie_xrates[1];
- data_len = (rate_len * (IW_EV_PARAM_LEN - IW_EV_LCP_LEN));
- if ((end_buf - current_ev) > data_len)
- {
- for (j = 0; j < rate_len; j++) {
- unsigned char val;
- val = cie->ie_xrates[2 + j];
- iwe.u.bitrate.value =
- (val >= 0x80)? ((val - 0x80) * 500000): (val * 500000);
- current_val = IWE_STREAM_ADD_VALUE(param->info, current_ev,
- current_val, end_buf,
- &iwe, IW_EV_PARAM_LEN);
- }
- }
- param->bytes_needed += data_len;
- }
- /* remove fixed header if no rates were added */
- if ((current_val - current_ev) > IW_EV_LCP_LEN)
- current_ev = current_val;
-
-#if WIRELESS_EXT >= 18
- /* IE */
- if (cie->ie_wpa != NULL) {
- data_len = cie->ie_wpa[1] + 2 + IW_EV_POINT_LEN;
- if ((end_buf - current_ev) > data_len)
- {
- A_MEMZERO(&iwe, sizeof(iwe));
- iwe.cmd = IWEVGENIE;
- iwe.u.data.length = cie->ie_wpa[1] + 2;
- current_ev = IWE_STREAM_ADD_POINT(param->info, current_ev, end_buf,
- &iwe, (char*)cie->ie_wpa);
- }
- param->bytes_needed += data_len;
- }
-
- if (cie->ie_rsn != NULL && cie->ie_rsn[0] == IEEE80211_ELEMID_RSN) {
- data_len = cie->ie_rsn[1] + 2 + IW_EV_POINT_LEN;
- if ((end_buf - current_ev) > data_len)
- {
- A_MEMZERO(&iwe, sizeof(iwe));
- iwe.cmd = IWEVGENIE;
- iwe.u.data.length = cie->ie_rsn[1] + 2;
- current_ev = IWE_STREAM_ADD_POINT(param->info, current_ev, end_buf,
- &iwe, (char*)cie->ie_rsn);
- }
- param->bytes_needed += data_len;
- }
-
-#endif /* WIRELESS_EXT >= 18 */
-
- if ((end_buf - current_ev) > IW_EV_CHAR_LEN)
- {
- /* protocol */
- A_MEMZERO(&iwe, sizeof(iwe));
- iwe.cmd = SIOCGIWNAME;
- switch (get_bss_phy_capability(ni)) {
- case WMI_11A_CAPABILITY:
- snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11a");
- break;
- case WMI_11G_CAPABILITY:
- snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11g");
- break;
- case WMI_11NA_CAPABILITY:
- snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11na");
- break;
- case WMI_11NG_CAPABILITY:
- snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11ng");
- break;
- default:
- snprintf(iwe.u.name, IFNAMSIZ, "IEEE 802.11b");
- break;
- }
- current_ev = IWE_STREAM_ADD_EVENT(param->info, current_ev, end_buf,
- &iwe, IW_EV_CHAR_LEN);
- }
- param->bytes_needed += IW_EV_CHAR_LEN;
-
-#if WIRELESS_EXT > 14
- A_MEMZERO(&iwe, sizeof(iwe));
- iwe.cmd = IWEVCUSTOM;
- iwe.u.data.length = snprintf(buf, sizeof(buf), "bcn_int=%d", cie->ie_beaconInt);
- data_len = iwe.u.data.length + IW_EV_POINT_LEN;
- if ((end_buf - current_ev) > data_len)
- {
- current_ev = IWE_STREAM_ADD_POINT(param->info, current_ev, end_buf,
- &iwe, buf);
- }
- param->bytes_needed += data_len;
-
-#if WIRELESS_EXT < 18
- if (cie->ie_wpa != NULL) {
- static const char wpa_leader[] = "wpa_ie=";
- data_len = (sizeof(wpa_leader) - 1) + ((cie->ie_wpa[1]+2) * 2) + IW_EV_POINT_LEN;
- if ((end_buf - current_ev) > data_len)
- {
- A_MEMZERO(&iwe, sizeof(iwe));
- iwe.cmd = IWEVCUSTOM;
- iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_wpa,
- cie->ie_wpa[1]+2,
- wpa_leader, sizeof(wpa_leader)-1);
-
- if (iwe.u.data.length != 0) {
- current_ev = IWE_STREAM_ADD_POINT(param->info, current_ev,
- end_buf, &iwe, buf);
- }
- }
- param->bytes_needed += data_len;
- }
-
- if (cie->ie_rsn != NULL && cie->ie_rsn[0] == IEEE80211_ELEMID_RSN) {
- static const char rsn_leader[] = "rsn_ie=";
- data_len = (sizeof(rsn_leader) - 1) + ((cie->ie_rsn[1]+2) * 2) + IW_EV_POINT_LEN;
- if ((end_buf - current_ev) > data_len)
- {
- A_MEMZERO(&iwe, sizeof(iwe));
- iwe.cmd = IWEVCUSTOM;
- iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_rsn,
- cie->ie_rsn[1]+2,
- rsn_leader, sizeof(rsn_leader)-1);
-
- if (iwe.u.data.length != 0) {
- current_ev = IWE_STREAM_ADD_POINT(param->info, current_ev,
- end_buf, &iwe, buf);
- }
- }
- param->bytes_needed += data_len;
- }
-#endif /* WIRELESS_EXT < 18 */
-
- if (cie->ie_wmm != NULL) {
- static const char wmm_leader[] = "wmm_ie=";
- data_len = (sizeof(wmm_leader) - 1) + ((cie->ie_wmm[1]+2) * 2) + IW_EV_POINT_LEN;
- if ((end_buf - current_ev) > data_len)
- {
- A_MEMZERO(&iwe, sizeof(iwe));
- iwe.cmd = IWEVCUSTOM;
- iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_wmm,
- cie->ie_wmm[1]+2,
- wmm_leader, sizeof(wmm_leader)-1);
- if (iwe.u.data.length != 0) {
- current_ev = IWE_STREAM_ADD_POINT(param->info, current_ev,
- end_buf, &iwe, buf);
- }
- }
- param->bytes_needed += data_len;
- }
-
- if (cie->ie_ath != NULL) {
- static const char ath_leader[] = "ath_ie=";
- data_len = (sizeof(ath_leader) - 1) + ((cie->ie_ath[1]+2) * 2) + IW_EV_POINT_LEN;
- if ((end_buf - current_ev) > data_len)
- {
- A_MEMZERO(&iwe, sizeof(iwe));
- iwe.cmd = IWEVCUSTOM;
- iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_ath,
- cie->ie_ath[1]+2,
- ath_leader, sizeof(ath_leader)-1);
- if (iwe.u.data.length != 0) {
- current_ev = IWE_STREAM_ADD_POINT(param->info, current_ev,
- end_buf, &iwe, buf);
- }
- }
- param->bytes_needed += data_len;
- }
-
-#ifdef WAPI_ENABLE
- if (cie->ie_wapi != NULL) {
- static const char wapi_leader[] = "wapi_ie=";
- data_len = (sizeof(wapi_leader) - 1) + ((cie->ie_wapi[1] + 2) * 2) + IW_EV_POINT_LEN;
- if ((end_buf - current_ev) > data_len) {
- A_MEMZERO(&iwe, sizeof(iwe));
- iwe.cmd = IWEVCUSTOM;
- iwe.u.data.length = encode_ie(buf, sizeof(buf), cie->ie_wapi,
- cie->ie_wapi[1] + 2,
- wapi_leader, sizeof(wapi_leader) - 1);
- if (iwe.u.data.length != 0) {
- current_ev = IWE_STREAM_ADD_POINT(param->info, current_ev,
- end_buf, &iwe, buf);
- }
- }
- param->bytes_needed += data_len;
- }
-#endif /* WAPI_ENABLE */
-
-#endif /* WIRELESS_EXT > 14 */
-
-#if WIRELESS_EXT >= 18
- if (cie->ie_wsc != NULL) {
- data_len = (cie->ie_wsc[1] + 2) + IW_EV_POINT_LEN;
- if ((end_buf - current_ev) > data_len)
- {
- A_MEMZERO(&iwe, sizeof(iwe));
- iwe.cmd = IWEVGENIE;
- iwe.u.data.length = cie->ie_wsc[1] + 2;
- current_ev = IWE_STREAM_ADD_POINT(param->info, current_ev, end_buf,
- &iwe, (char*)cie->ie_wsc);
- }
- param->bytes_needed += data_len;
- }
-#endif /* WIRELESS_EXT >= 18 */
-
- param->current_ev = current_ev;
-}
-
-int
-ar6000_ioctl_giwscan(struct net_device *dev,
- struct iw_request_info *info,
- struct iw_point *data, char *extra)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
- struct ar_giwscan_param param;
-
- if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != 0) {
- A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
- return -EOPNOTSUPP;
- }
-
- if (ar->arWlanState == WLAN_DISABLED) {
- return -EIO;
- }
-
- if (ar->arWmiReady == false) {
- return -EIO;
- }
-
- param.current_ev = extra;
- param.end_buf = extra + data->length;
- param.bytes_needed = 0;
- param.info = info;
-
- /* Translate data to WE format */
- wmi_iterate_nodes(ar->arWmi, ar6000_scan_node, ¶m);
-
- /* check if bytes needed is greater than bytes consumed */
- if (param.bytes_needed > (param.current_ev - extra))
- {
- /* Request one byte more than needed, because when "data->length" equals bytes_needed,
- it is not possible to add the last event data as all iwe_stream_add_xxxxx() functions
- checks whether (cur_ptr + ev_len) < end_ptr, due to this one more retry would happen*/
- data->length = param.bytes_needed + 1;
-
- return -E2BIG;
- }
-
- return 0;
-}
-
-extern int reconnect_flag;
-/* SIOCSIWESSID */
-static int
-ar6000_ioctl_siwessid(struct net_device *dev,
- struct iw_request_info *info,
- struct iw_point *data, char *ssid)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
- int status;
- u8 arNetworkType;
- u8 prevMode = ar->arNetworkType;
-
- if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != 0) {
- A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
- return -EOPNOTSUPP;
- }
-
- if (ar->bIsDestroyProgress) {
- return -EBUSY;
- }
-
- if (ar->arWlanState == WLAN_DISABLED) {
- return -EIO;
- }
-
- if (ar->arWmiReady == false) {
- return -EIO;
- }
-
-#if defined(WIRELESS_EXT)
- if (WIRELESS_EXT >= 20) {
- data->length += 1;
- }
-#endif
-
- /*
- * iwconfig passes a null terminated string with length including this
- * so we need to account for this
- */
- if (data->flags && (!data->length || (data->length == 1) ||
- ((data->length - 1) > sizeof(ar->arSsid))))
- {
- /*
- * ssid is invalid
- */
- return -EINVAL;
- }
-
- if (ar->arNextMode == AP_NETWORK) {
- /* SSID change for AP network - Will take effect on commit */
- if(memcmp(ar->arSsid,ssid,32) != 0) {
- ar->arSsidLen = data->length - 1;
- memcpy(ar->arSsid, ssid, ar->arSsidLen);
- ar->ap_profile_flag = 1; /* There is a change in profile */
- }
- return 0;
- } else if(ar->arNetworkType == AP_NETWORK) {
- u8 ctr;
- struct sk_buff *skb;
-
- /* We are switching from AP to STA | IBSS mode, cleanup the AP state */
- for (ctr=0; ctr < AP_MAX_NUM_STA; ctr++) {
- remove_sta(ar, ar->sta_list[ctr].mac, 0);
- }
- A_MUTEX_LOCK(&ar->mcastpsqLock);
- while (!A_NETBUF_QUEUE_EMPTY(&ar->mcastpsq)) {
- skb = A_NETBUF_DEQUEUE(&ar->mcastpsq);
- A_NETBUF_FREE(skb);
- }
- A_MUTEX_UNLOCK(&ar->mcastpsqLock);
- }
-
- /* Added for bug 25178, return an IOCTL error instead of target returning
- Illegal parameter error when either the BSSID or channel is missing
- and we cannot scan during connect.
- */
- if (data->flags) {
- if (ar->arSkipScan == true &&
- (ar->arChannelHint == 0 ||
- (!ar->arReqBssid[0] && !ar->arReqBssid[1] && !ar->arReqBssid[2] &&
- !ar->arReqBssid[3] && !ar->arReqBssid[4] && !ar->arReqBssid[5])))
- {
- return -EINVAL;
- }
- }
-
- if (down_interruptible(&ar->arSem)) {
- return -ERESTARTSYS;
- }
-
- if (ar->bIsDestroyProgress || ar->arWlanState == WLAN_DISABLED) {
- up(&ar->arSem);
- return -EBUSY;
- }
-
- if (ar->arTxPending[wmi_get_control_ep(ar->arWmi)]) {
- /*
- * sleep until the command queue drains
- */
- wait_event_interruptible_timeout(arEvent,
- ar->arTxPending[wmi_get_control_ep(ar->arWmi)] == 0, wmitimeout * HZ);
- if (signal_pending(current)) {
- return -EINTR;
- }
- }
-
- if (!data->flags) {
- arNetworkType = ar->arNetworkType;
-#ifdef ATH6K_CONFIG_CFG80211
- if (ar->arConnected) {
-#endif /* ATH6K_CONFIG_CFG80211 */
- ar6000_init_profile_info(ar);
-#ifdef ATH6K_CONFIG_CFG80211
- }
-#endif /* ATH6K_CONFIG_CFG80211 */
- ar->arNetworkType = arNetworkType;
- }
-
- /* Update the arNetworkType */
- ar->arNetworkType = ar->arNextMode;
-
- if ((prevMode != AP_NETWORK) &&
- ((ar->arSsidLen) ||
- ((ar->arSsidLen == 0) && (ar->arConnected || ar->arConnectPending)) ||
- (!data->flags)))
- {
- if ((!data->flags) ||
- (memcmp(ar->arSsid, ssid, ar->arSsidLen) != 0) ||
- (ar->arSsidLen != (data->length - 1)))
- {
- /*
- * SSID set previously or essid off has been issued.
- *
- * Disconnect Command is issued in two cases after wmi is ready
- * (1) ssid is different from the previous setting
- * (2) essid off has been issued
- *
- */
- if (ar->arWmiReady == true) {
- reconnect_flag = 0;
- status = wmi_setPmkid_cmd(ar->arWmi, ar->arBssid, NULL, 0);
- ar6000_disconnect(ar);
- A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
- ar->arSsidLen = 0;
- if (ar->arSkipScan == false) {
- A_MEMZERO(ar->arReqBssid, sizeof(ar->arReqBssid));
- }
- if (!data->flags) {
- up(&ar->arSem);
- return 0;
- }
- } else {
- up(&ar->arSem);
- }
- }
- else
- {
- /*
- * SSID is same, so we assume profile hasn't changed.
- * If the interface is up and wmi is ready, we issue
- * a reconnect cmd. Issue a reconnect only we are already
- * connected.
- */
- if((ar->arConnected == true) && (ar->arWmiReady == true))
- {
- reconnect_flag = true;
- status = wmi_reconnect_cmd(ar->arWmi,ar->arReqBssid,
- ar->arChannelHint);
- up(&ar->arSem);
- if (status) {
- return -EIO;
- }
- return 0;
- }
- else{
- /*
- * Dont return if connect is pending.
- */
- if(!(ar->arConnectPending)) {
- up(&ar->arSem);
- return 0;
- }
- }
- }
- }
-
- ar->arSsidLen = data->length - 1;
- memcpy(ar->arSsid, ssid, ar->arSsidLen);
-
- if (ar6000_connect_to_ap(ar)!= 0) {
- up(&ar->arSem);
- return -EIO;
- }else{
- up(&ar->arSem);
- }
- return 0;
-}
-
-/* SIOCGIWESSID */
-static int
-ar6000_ioctl_giwessid(struct net_device *dev,
- struct iw_request_info *info,
- struct iw_point *data, char *essid)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
-
- if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != 0) {
- A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
- return -EOPNOTSUPP;
- }
-
- if (ar->arWlanState == WLAN_DISABLED) {
- return -EIO;
- }
-
- if (!ar->arSsidLen) {
- return -EINVAL;
- }
-
- data->flags = 1;
- data->length = ar->arSsidLen;
- memcpy(essid, ar->arSsid, ar->arSsidLen);
-
- return 0;
-}
-
-
-void ar6000_install_static_wep_keys(struct ar6_softc *ar)
-{
- u8 index;
- u8 keyUsage;
-
- for (index = WMI_MIN_KEY_INDEX; index <= WMI_MAX_KEY_INDEX; index++) {
- if (ar->arWepKeyList[index].arKeyLen) {
- keyUsage = GROUP_USAGE;
- if (index == ar->arDefTxKeyIndex) {
- keyUsage |= TX_USAGE;
- }
- wmi_addKey_cmd(ar->arWmi,
- index,
- WEP_CRYPT,
- keyUsage,
- ar->arWepKeyList[index].arKeyLen,
- NULL,
- ar->arWepKeyList[index].arKey, KEY_OP_INIT_VAL, NULL,
- NO_SYNC_WMIFLAG);
- }
- }
-}
-
-/*
- * SIOCSIWRATE
- */
-int
-ar6000_ioctl_siwrate(struct net_device *dev,
- struct iw_request_info *info,
- struct iw_param *rrq, char *extra)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
- u32 kbps;
- s8 rate_idx;
-
- if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != 0) {
- A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
- return -EOPNOTSUPP;
- }
-
- if (rrq->fixed) {
- kbps = rrq->value / 1000; /* rrq->value is in bps */
- } else {
- kbps = -1; /* -1 indicates auto rate */
- }
- if(kbps != -1 && wmi_validate_bitrate(ar->arWmi, kbps, &rate_idx) != 0)
- {
- AR_DEBUG_PRINTF(ATH_DEBUG_ERR,("BitRate is not Valid %d\n", kbps));
- return -EINVAL;
- }
- ar->arBitRate = kbps;
- if(ar->arWmiReady == true)
- {
- if (wmi_set_bitrate_cmd(ar->arWmi, kbps, -1, -1) != 0) {
- return -EINVAL;
- }
- }
- return 0;
-}
-
-/*
- * SIOCGIWRATE
- */
-int
-ar6000_ioctl_giwrate(struct net_device *dev,
- struct iw_request_info *info,
- struct iw_param *rrq, char *extra)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
- int ret = 0;
-
- if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != 0) {
- A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
- return -EOPNOTSUPP;
- }
-
- if (ar->bIsDestroyProgress) {
- return -EBUSY;
- }
-
- if (ar->arWlanState == WLAN_DISABLED) {
- return -EIO;
- }
-
- if ((ar->arNextMode != AP_NETWORK && !ar->arConnected) || ar->arWmiReady == false) {
- rrq->value = 1000 * 1000;
- return 0;
- }
-
- if (down_interruptible(&ar->arSem)) {
- return -ERESTARTSYS;
- }
-
- if (ar->bIsDestroyProgress || ar->arWlanState == WLAN_DISABLED) {
- up(&ar->arSem);
- return -EBUSY;
- }
-
- ar->arBitRate = 0xFFFF;
- if (wmi_get_bitrate_cmd(ar->arWmi) != 0) {
- up(&ar->arSem);
- return -EIO;
- }
- wait_event_interruptible_timeout(arEvent, ar->arBitRate != 0xFFFF, wmitimeout * HZ);
- if (signal_pending(current)) {
- ret = -EINTR;
- }
- /* If the interface is down or wmi is not ready or the target is not
- connected - return the value stored in the device structure */
- if (!ret) {
- if (ar->arBitRate == -1) {
- rrq->fixed = true;
- rrq->value = 0;
- } else {
- rrq->value = ar->arBitRate * 1000;
- }
- }
-
- up(&ar->arSem);
-
- return ret;
-}
-
-/*
- * SIOCSIWTXPOW
- */
-static int
-ar6000_ioctl_siwtxpow(struct net_device *dev,
- struct iw_request_info *info,
- struct iw_param *rrq, char *extra)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
- u8 dbM;
-
- if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != 0) {
- A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
- return -EOPNOTSUPP;
- }
-
- if (ar->arWlanState == WLAN_DISABLED) {
- return -EIO;
- }
-
- if (rrq->disabled) {
- return -EOPNOTSUPP;
- }
-
- if (rrq->fixed) {
- if (rrq->flags != IW_TXPOW_DBM) {
- return -EOPNOTSUPP;
- }
- ar->arTxPwr= dbM = rrq->value;
- ar->arTxPwrSet = true;
- } else {
- ar->arTxPwr = dbM = 0;
- ar->arTxPwrSet = false;
- }
- if(ar->arWmiReady == true)
- {
- AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_TX,("Set tx pwr cmd %d dbM\n", dbM));
- wmi_set_txPwr_cmd(ar->arWmi, dbM);
- }
- return 0;
-}
-
-/*
- * SIOCGIWTXPOW
- */
-int
-ar6000_ioctl_giwtxpow(struct net_device *dev,
- struct iw_request_info *info,
- struct iw_param *rrq, char *extra)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
- int ret = 0;
-
- if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != 0) {
- A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
- return -EOPNOTSUPP;
- }
-
- if (ar->bIsDestroyProgress) {
- return -EBUSY;
- }
-
- if (ar->arWlanState == WLAN_DISABLED) {
- return -EIO;
- }
-
- if (down_interruptible(&ar->arSem)) {
- return -ERESTARTSYS;
- }
-
- if (ar->bIsDestroyProgress) {
- up(&ar->arSem);
- return -EBUSY;
- }
-
- if((ar->arWmiReady == true) && (ar->arConnected == true))
- {
- ar->arTxPwr = 0;
-
- if (wmi_get_txPwr_cmd(ar->arWmi) != 0) {
- up(&ar->arSem);
- return -EIO;
- }
-
- wait_event_interruptible_timeout(arEvent, ar->arTxPwr != 0, wmitimeout * HZ);
-
- if (signal_pending(current)) {
- ret = -EINTR;
- }
- }
- /* If the interace is down or wmi is not ready or target is not connected
- then return value stored in the device structure */
-
- if (!ret) {
- if (ar->arTxPwrSet == true) {
- rrq->fixed = true;
- }
- rrq->value = ar->arTxPwr;
- rrq->flags = IW_TXPOW_DBM;
- //
- // IWLIST need this flag to get TxPower
- //
- rrq->disabled = 0;
- }
-
- up(&ar->arSem);
-
- return ret;
-}
-
-/*
- * SIOCSIWRETRY
- * since iwconfig only provides us with one max retry value, we use it
- * to apply to data frames of the BE traffic class.
- */
-static int
-ar6000_ioctl_siwretry(struct net_device *dev,
- struct iw_request_info *info,
- struct iw_param *rrq, char *extra)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
-
- if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != 0) {
- A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
- return -EOPNOTSUPP;
- }
-
- if (ar->arWlanState == WLAN_DISABLED) {
- return -EIO;
- }
-
- if (rrq->disabled) {
- return -EOPNOTSUPP;
- }
-
- if ((rrq->flags & IW_RETRY_TYPE) != IW_RETRY_LIMIT) {
- return -EOPNOTSUPP;
- }
-
- if ( !(rrq->value >= WMI_MIN_RETRIES) || !(rrq->value <= WMI_MAX_RETRIES)) {
- return - EINVAL;
- }
- if(ar->arWmiReady == true)
- {
- if (wmi_set_retry_limits_cmd(ar->arWmi, DATA_FRAMETYPE, WMM_AC_BE,
- rrq->value, 0) != 0){
- return -EINVAL;
- }
- }
- ar->arMaxRetries = rrq->value;
- return 0;
-}
-
-/*
- * SIOCGIWRETRY
- */
-static int
-ar6000_ioctl_giwretry(struct net_device *dev,
- struct iw_request_info *info,
- struct iw_param *rrq, char *extra)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
-
- if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != 0) {
- A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
- return -EOPNOTSUPP;
- }
-
- if (ar->arWlanState == WLAN_DISABLED) {
- return -EIO;
- }
-
- rrq->disabled = 0;
- switch (rrq->flags & IW_RETRY_TYPE) {
- case IW_RETRY_LIFETIME:
- return -EOPNOTSUPP;
- break;
- case IW_RETRY_LIMIT:
- rrq->flags = IW_RETRY_LIMIT;
- switch (rrq->flags & IW_RETRY_MODIFIER) {
- case IW_RETRY_MIN:
- rrq->flags |= IW_RETRY_MIN;
- rrq->value = WMI_MIN_RETRIES;
- break;
- case IW_RETRY_MAX:
- rrq->flags |= IW_RETRY_MAX;
- rrq->value = ar->arMaxRetries;
- break;
- }
- break;
- }
- return 0;
-}
-
-/*
- * SIOCSIWENCODE
- */
-static int
-ar6000_ioctl_siwencode(struct net_device *dev,
- struct iw_request_info *info,
- struct iw_point *erq, char *keybuf)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
- int index;
- s32 auth = 0;
-
- if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != 0) {
- A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
- return -EOPNOTSUPP;
- }
-
- if(ar->arNextMode != AP_NETWORK) {
- /*
- * Static WEP Keys should be configured before setting the SSID
- */
- if (ar->arSsid[0] && erq->length) {
- return -EIO;
- }
- }
-
- if (ar->arWlanState == WLAN_DISABLED) {
- return -EIO;
- }
-
- index = erq->flags & IW_ENCODE_INDEX;
-
- if (index && (((index - 1) < WMI_MIN_KEY_INDEX) ||
- ((index - 1) > WMI_MAX_KEY_INDEX)))
- {
- return -EIO;
- }
-
- if (erq->flags & IW_ENCODE_DISABLED) {
- /*
- * Encryption disabled
- */
- if (index) {
- /*
- * If key index was specified then clear the specified key
- */
- index--;
- A_MEMZERO(ar->arWepKeyList[index].arKey,
- sizeof(ar->arWepKeyList[index].arKey));
- ar->arWepKeyList[index].arKeyLen = 0;
- }
- ar->arDot11AuthMode = OPEN_AUTH;
- ar->arPairwiseCrypto = NONE_CRYPT;
- ar->arGroupCrypto = NONE_CRYPT;
- ar->arAuthMode = NONE_AUTH;
- } else {
- /*
- * Enabling WEP encryption
- */
- if (index) {
- index--; /* keyindex is off base 1 in iwconfig */
- }
-
- if (erq->flags & IW_ENCODE_OPEN) {
- auth |= OPEN_AUTH;
- ar->arDefTxKeyIndex = index;
- }
- if (erq->flags & IW_ENCODE_RESTRICTED) {
- auth |= SHARED_AUTH;
- }
-
- if (!auth) {
- auth = OPEN_AUTH;
- }
-
- if (erq->length) {
- if (!IEEE80211_IS_VALID_WEP_CIPHER_LEN(erq->length)) {
- return -EIO;
- }
-
- A_MEMZERO(ar->arWepKeyList[index].arKey,
- sizeof(ar->arWepKeyList[index].arKey));
- memcpy(ar->arWepKeyList[index].arKey, keybuf, erq->length);
- ar->arWepKeyList[index].arKeyLen = erq->length;
- ar->arDot11AuthMode = auth;
- } else {
- if (ar->arWepKeyList[index].arKeyLen == 0) {
- return -EIO;
- }
- ar->arDefTxKeyIndex = index;
-
- if(ar->arSsidLen && ar->arWepKeyList[index].arKeyLen) {
- wmi_addKey_cmd(ar->arWmi,
- index,
- WEP_CRYPT,
- GROUP_USAGE | TX_USAGE,
- ar->arWepKeyList[index].arKeyLen,
- NULL,
- ar->arWepKeyList[index].arKey, KEY_OP_INIT_VAL, NULL,
- NO_SYNC_WMIFLAG);
- }
- }
-
- ar->arPairwiseCrypto = WEP_CRYPT;
- ar->arGroupCrypto = WEP_CRYPT;
- ar->arAuthMode = NONE_AUTH;
- }
-
- if(ar->arNextMode != AP_NETWORK) {
- /*
- * profile has changed. Erase ssid to signal change
- */
- A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
- ar->arSsidLen = 0;
- }
- ar->ap_profile_flag = 1; /* There is a change in profile */
- return 0;
-}
-
-static int
-ar6000_ioctl_giwencode(struct net_device *dev,
- struct iw_request_info *info,
- struct iw_point *erq, char *key)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
- u8 keyIndex;
- struct ar_wep_key *wk;
-
- if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != 0) {
- A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
- return -EOPNOTSUPP;
- }
-
- if (ar->arWlanState == WLAN_DISABLED) {
- return -EIO;
- }
-
- if (ar->arPairwiseCrypto == NONE_CRYPT) {
- erq->length = 0;
- erq->flags = IW_ENCODE_DISABLED;
- } else {
- if (ar->arPairwiseCrypto == WEP_CRYPT) {
- /* get the keyIndex */
- keyIndex = erq->flags & IW_ENCODE_INDEX;
- if (0 == keyIndex) {
- keyIndex = ar->arDefTxKeyIndex;
- } else if ((keyIndex - 1 < WMI_MIN_KEY_INDEX) ||
- (keyIndex - 1 > WMI_MAX_KEY_INDEX))
- {
- keyIndex = WMI_MIN_KEY_INDEX;
- } else {
- keyIndex--;
- }
- erq->flags = keyIndex + 1;
- erq->flags &= ~IW_ENCODE_DISABLED;
- wk = &ar->arWepKeyList[keyIndex];
- if (erq->length > wk->arKeyLen) {
- erq->length = wk->arKeyLen;
- }
- if (wk->arKeyLen) {
- memcpy(key, wk->arKey, erq->length);
- }
- } else {
- erq->flags &= ~IW_ENCODE_DISABLED;
- if (ar->user_saved_keys.keyOk) {
- erq->length = ar->user_saved_keys.ucast_ik.ik_keylen;
- if (erq->length) {
- memcpy(key, ar->user_saved_keys.ucast_ik.ik_keydata, erq->length);
- }
- } else {
- erq->length = 1; // not really printing any key but let iwconfig know enc is on
- }
- }
-
- if (ar->arDot11AuthMode & OPEN_AUTH) {
- erq->flags |= IW_ENCODE_OPEN;
- }
- if (ar->arDot11AuthMode & SHARED_AUTH) {
- erq->flags |= IW_ENCODE_RESTRICTED;
- }
- }
-
- return 0;
-}
-
-#if WIRELESS_EXT >= 18
-/*
- * SIOCSIWGENIE
- */
-static int
-ar6000_ioctl_siwgenie(struct net_device *dev,
- struct iw_request_info *info,
- struct iw_point *erq, char *extra)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
-
-#ifdef WAPI_ENABLE
- u8 *ie = erq->pointer;
- u8 ie_type = ie[0];
- u16 ie_length = erq->length;
- u8 wapi_ie[128];
-#endif
-
- if (ar->arWmiReady == false) {
- return -EIO;
- }
-#ifdef WAPI_ENABLE
- if (ie_type == IEEE80211_ELEMID_WAPI) {
- if (ie_length > 0) {
- if (copy_from_user(wapi_ie, ie, ie_length)) {
- return -EIO;
- }
- }
- wmi_set_appie_cmd(ar->arWmi, WMI_FRAME_ASSOC_REQ, ie_length, wapi_ie);
- } else if (ie_length == 0) {
- wmi_set_appie_cmd(ar->arWmi, WMI_FRAME_ASSOC_REQ, ie_length, wapi_ie);
- }
-#endif
- return 0;
-}
-
-
-/*
- * SIOCGIWGENIE
- */
-static int
-ar6000_ioctl_giwgenie(struct net_device *dev,
- struct iw_request_info *info,
- struct iw_point *erq, char *extra)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
-
- if (ar->arWmiReady == false) {
- return -EIO;
- }
- erq->length = 0;
- erq->flags = 0;
-
- return 0;
-}
-
-/*
- * SIOCSIWAUTH
- */
-static int
-ar6000_ioctl_siwauth(struct net_device *dev,
- struct iw_request_info *info,
- struct iw_param *data, char *extra)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
-
- bool profChanged;
- u16 param;
- s32 ret;
- s32 value;
-
- if (ar->arWmiReady == false) {
- return -EIO;
- }
-
- if (ar->arWlanState == WLAN_DISABLED) {
- return -EIO;
- }
-
- param = data->flags & IW_AUTH_INDEX;
- value = data->value;
- profChanged = true;
- ret = 0;
-
- switch (param) {
- case IW_AUTH_WPA_VERSION:
- if (value & IW_AUTH_WPA_VERSION_DISABLED) {
- ar->arAuthMode = NONE_AUTH;
- } else if (value & IW_AUTH_WPA_VERSION_WPA) {
- ar->arAuthMode = WPA_AUTH;
- } else if (value & IW_AUTH_WPA_VERSION_WPA2) {
- ar->arAuthMode = WPA2_AUTH;
- } else {
- ret = -1;
- profChanged = false;
- }
- break;
- case IW_AUTH_CIPHER_PAIRWISE:
- if (value & IW_AUTH_CIPHER_NONE) {
- ar->arPairwiseCrypto = NONE_CRYPT;
- ar->arPairwiseCryptoLen = 0;
- } else if (value & IW_AUTH_CIPHER_WEP40) {
- ar->arPairwiseCrypto = WEP_CRYPT;
- ar->arPairwiseCryptoLen = 5;
- } else if (value & IW_AUTH_CIPHER_TKIP) {
- ar->arPairwiseCrypto = TKIP_CRYPT;
- ar->arPairwiseCryptoLen = 0;
- } else if (value & IW_AUTH_CIPHER_CCMP) {
- ar->arPairwiseCrypto = AES_CRYPT;
- ar->arPairwiseCryptoLen = 0;
- } else if (value & IW_AUTH_CIPHER_WEP104) {
- ar->arPairwiseCrypto = WEP_CRYPT;
- ar->arPairwiseCryptoLen = 13;
- } else {
- ret = -1;
- profChanged = false;
- }
- break;
- case IW_AUTH_CIPHER_GROUP:
- if (value & IW_AUTH_CIPHER_NONE) {
- ar->arGroupCrypto = NONE_CRYPT;
- ar->arGroupCryptoLen = 0;
- } else if (value & IW_AUTH_CIPHER_WEP40) {
- ar->arGroupCrypto = WEP_CRYPT;
- ar->arGroupCryptoLen = 5;
- } else if (value & IW_AUTH_CIPHER_TKIP) {
- ar->arGroupCrypto = TKIP_CRYPT;
- ar->arGroupCryptoLen = 0;
- } else if (value & IW_AUTH_CIPHER_CCMP) {
- ar->arGroupCrypto = AES_CRYPT;
- ar->arGroupCryptoLen = 0;
- } else if (value & IW_AUTH_CIPHER_WEP104) {
- ar->arGroupCrypto = WEP_CRYPT;
- ar->arGroupCryptoLen = 13;
- } else {
- ret = -1;
- profChanged = false;
- }
- break;
- case IW_AUTH_KEY_MGMT:
- if (value & IW_AUTH_KEY_MGMT_PSK) {
- if (WPA_AUTH == ar->arAuthMode) {
- ar->arAuthMode = WPA_PSK_AUTH;
- } else if (WPA2_AUTH == ar->arAuthMode) {
- ar->arAuthMode = WPA2_PSK_AUTH;
- } else {
- ret = -1;
- }
- } else if (!(value & IW_AUTH_KEY_MGMT_802_1X)) {
- ar->arAuthMode = NONE_AUTH;
- }
- break;
- case IW_AUTH_TKIP_COUNTERMEASURES:
- wmi_set_tkip_countermeasures_cmd(ar->arWmi, value);
- profChanged = false;
- break;
- case IW_AUTH_DROP_UNENCRYPTED:
- profChanged = false;
- break;
- case IW_AUTH_80211_AUTH_ALG:
- ar->arDot11AuthMode = 0;
- if (value & IW_AUTH_ALG_OPEN_SYSTEM) {
- ar->arDot11AuthMode |= OPEN_AUTH;
- }
- if (value & IW_AUTH_ALG_SHARED_KEY) {
- ar->arDot11AuthMode |= SHARED_AUTH;
- }
- if (value & IW_AUTH_ALG_LEAP) {
- ar->arDot11AuthMode = LEAP_AUTH;
- }
- if(ar->arDot11AuthMode == 0) {
- ret = -1;
- profChanged = false;
- }
- break;
- case IW_AUTH_WPA_ENABLED:
- if (!value) {
- ar->arAuthMode = NONE_AUTH;
- /* when the supplicant is stopped, it calls this
- * handler with value=0. The followings need to be
- * reset if the STA were to connect again
- * without security
- */
- ar->arDot11AuthMode = OPEN_AUTH;
- ar->arPairwiseCrypto = NONE_CRYPT;
- ar->arPairwiseCryptoLen = 0;
- ar->arGroupCrypto = NONE_CRYPT;
- ar->arGroupCryptoLen = 0;
- }
- break;
- case IW_AUTH_RX_UNENCRYPTED_EAPOL:
- profChanged = false;
- break;
- case IW_AUTH_ROAMING_CONTROL:
- profChanged = false;
- break;
- case IW_AUTH_PRIVACY_INVOKED:
- if (!value) {
- ar->arPairwiseCrypto = NONE_CRYPT;
- ar->arPairwiseCryptoLen = 0;
- ar->arGroupCrypto = NONE_CRYPT;
- ar->arGroupCryptoLen = 0;
- }
- break;
-#ifdef WAPI_ENABLE
- case IW_AUTH_WAPI_ENABLED:
- ar->arWapiEnable = value;
- break;
-#endif
- default:
- ret = -1;
- profChanged = false;
- break;
- }
-
- if (profChanged == true) {
- /*
- * profile has changed. Erase ssid to signal change
- */
- A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
- ar->arSsidLen = 0;
- }
-
- return ret;
-}
-
-
-/*
- * SIOCGIWAUTH
- */
-static int
-ar6000_ioctl_giwauth(struct net_device *dev,
- struct iw_request_info *info,
- struct iw_param *data, char *extra)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
- u16 param;
- s32 ret;
-
- if (ar->arWmiReady == false) {
- return -EIO;
- }
-
- if (ar->arWlanState == WLAN_DISABLED) {
- return -EIO;
- }
-
- param = data->flags & IW_AUTH_INDEX;
- ret = 0;
- data->value = 0;
-
-
- switch (param) {
- case IW_AUTH_WPA_VERSION:
- if (ar->arAuthMode == NONE_AUTH) {
- data->value |= IW_AUTH_WPA_VERSION_DISABLED;
- } else if (ar->arAuthMode == WPA_AUTH) {
- data->value |= IW_AUTH_WPA_VERSION_WPA;
- } else if (ar->arAuthMode == WPA2_AUTH) {
- data->value |= IW_AUTH_WPA_VERSION_WPA2;
- } else {
- ret = -1;
- }
- break;
- case IW_AUTH_CIPHER_PAIRWISE:
- if (ar->arPairwiseCrypto == NONE_CRYPT) {
- data->value |= IW_AUTH_CIPHER_NONE;
- } else if (ar->arPairwiseCrypto == WEP_CRYPT) {
- if (ar->arPairwiseCryptoLen == 13) {
- data->value |= IW_AUTH_CIPHER_WEP104;
- } else {
- data->value |= IW_AUTH_CIPHER_WEP40;
- }
- } else if (ar->arPairwiseCrypto == TKIP_CRYPT) {
- data->value |= IW_AUTH_CIPHER_TKIP;
- } else if (ar->arPairwiseCrypto == AES_CRYPT) {
- data->value |= IW_AUTH_CIPHER_CCMP;
- } else {
- ret = -1;
- }
- break;
- case IW_AUTH_CIPHER_GROUP:
- if (ar->arGroupCrypto == NONE_CRYPT) {
- data->value |= IW_AUTH_CIPHER_NONE;
- } else if (ar->arGroupCrypto == WEP_CRYPT) {
- if (ar->arGroupCryptoLen == 13) {
- data->value |= IW_AUTH_CIPHER_WEP104;
- } else {
- data->value |= IW_AUTH_CIPHER_WEP40;
- }
- } else if (ar->arGroupCrypto == TKIP_CRYPT) {
- data->value |= IW_AUTH_CIPHER_TKIP;
- } else if (ar->arGroupCrypto == AES_CRYPT) {
- data->value |= IW_AUTH_CIPHER_CCMP;
- } else {
- ret = -1;
- }
- break;
- case IW_AUTH_KEY_MGMT:
- if ((ar->arAuthMode == WPA_PSK_AUTH) ||
- (ar->arAuthMode == WPA2_PSK_AUTH)) {
- data->value |= IW_AUTH_KEY_MGMT_PSK;
- } else if ((ar->arAuthMode == WPA_AUTH) ||
- (ar->arAuthMode == WPA2_AUTH)) {
- data->value |= IW_AUTH_KEY_MGMT_802_1X;
- }
- break;
- case IW_AUTH_TKIP_COUNTERMEASURES:
- // TODO. Save countermeassure enable/disable
- data->value = 0;
- break;
- case IW_AUTH_DROP_UNENCRYPTED:
- break;
- case IW_AUTH_80211_AUTH_ALG:
- if (ar->arDot11AuthMode == OPEN_AUTH) {
- data->value |= IW_AUTH_ALG_OPEN_SYSTEM;
- } else if (ar->arDot11AuthMode == SHARED_AUTH) {
- data->value |= IW_AUTH_ALG_SHARED_KEY;
- } else if (ar->arDot11AuthMode == LEAP_AUTH) {
- data->value |= IW_AUTH_ALG_LEAP;
- } else {
- ret = -1;
- }
- break;
- case IW_AUTH_WPA_ENABLED:
- if (ar->arAuthMode == NONE_AUTH) {
- data->value = 0;
- } else {
- data->value = 1;
- }
- break;
- case IW_AUTH_RX_UNENCRYPTED_EAPOL:
- break;
- case IW_AUTH_ROAMING_CONTROL:
- break;
- case IW_AUTH_PRIVACY_INVOKED:
- if (ar->arPairwiseCrypto == NONE_CRYPT) {
- data->value = 0;
- } else {
- data->value = 1;
- }
- break;
-#ifdef WAPI_ENABLE
- case IW_AUTH_WAPI_ENABLED:
- data->value = ar->arWapiEnable;
- break;
-#endif
- default:
- ret = -1;
- break;
- }
-
- return 0;
-}
-
-/*
- * SIOCSIWPMKSA
- */
-static int
-ar6000_ioctl_siwpmksa(struct net_device *dev,
- struct iw_request_info *info,
- struct iw_point *data, char *extra)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
- s32 ret;
- int status;
- struct iw_pmksa *pmksa;
-
- pmksa = (struct iw_pmksa *)extra;
-
- if (ar->arWmiReady == false) {
- return -EIO;
- }
-
- ret = 0;
- status = 0;
-
- switch (pmksa->cmd) {
- case IW_PMKSA_ADD:
- status = wmi_setPmkid_cmd(ar->arWmi, (u8 *)pmksa->bssid.sa_data, pmksa->pmkid, true);
- break;
- case IW_PMKSA_REMOVE:
- status = wmi_setPmkid_cmd(ar->arWmi, (u8 *)pmksa->bssid.sa_data, pmksa->pmkid, false);
- break;
- case IW_PMKSA_FLUSH:
- if (ar->arConnected == true) {
- status = wmi_setPmkid_cmd(ar->arWmi, ar->arBssid, NULL, 0);
- }
- break;
- default:
- ret=-1;
- break;
- }
- if (status) {
- ret = -1;
- }
-
- return ret;
-}
-
-#ifdef WAPI_ENABLE
-
-#define PN_INIT 0x5c365c36
-
-static int ar6000_set_wapi_key(struct net_device *dev,
- struct iw_request_info *info,
- struct iw_point *erq, char *extra)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
- struct iw_encode_ext *ext = (struct iw_encode_ext *)extra;
- KEY_USAGE keyUsage = 0;
- s32 keyLen;
- u8 *keyData;
- s32 index;
- u32 *PN;
- s32 i;
- int status;
- u8 wapiKeyRsc[16];
- CRYPTO_TYPE keyType = WAPI_CRYPT;
- const u8 broadcastMac[] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};
-
- index = erq->flags & IW_ENCODE_INDEX;
- if (index && (((index - 1) < WMI_MIN_KEY_INDEX) ||
- ((index - 1) > WMI_MAX_KEY_INDEX))) {
- return -EIO;
- }
-
- index--;
- if (index < 0 || index > 4) {
- return -EIO;
- }
- keyData = (u8 *)(ext + 1);
- keyLen = erq->length - sizeof(struct iw_encode_ext);
- memcpy(wapiKeyRsc, ext->tx_seq, sizeof(wapiKeyRsc));
-
- if (memcmp(ext->addr.sa_data, broadcastMac, sizeof(broadcastMac)) == 0) {
- keyUsage |= GROUP_USAGE;
- PN = (u32 *)wapiKeyRsc;
- for (i = 0; i < 4; i++) {
- PN[i] = PN_INIT;
- }
- } else {
- keyUsage |= PAIRWISE_USAGE;
- }
- status = wmi_addKey_cmd(ar->arWmi,
- index,
- keyType,
- keyUsage,
- keyLen,
- wapiKeyRsc,
- keyData,
- KEY_OP_INIT_WAPIPN,
- NULL,
- SYNC_BEFORE_WMIFLAG);
- if (0 != status) {
- return -EIO;
- }
- return 0;
-}
-
-#endif
-
-/*
- * SIOCSIWENCODEEXT
- */
-static int
-ar6000_ioctl_siwencodeext(struct net_device *dev,
- struct iw_request_info *info,
- struct iw_point *erq, char *extra)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
- s32 index;
- struct iw_encode_ext *ext;
- KEY_USAGE keyUsage;
- s32 keyLen;
- u8 *keyData;
- u8 keyRsc[8];
- int status;
- CRYPTO_TYPE keyType;
-#ifdef USER_KEYS
- struct ieee80211req_key ik;
-#endif /* USER_KEYS */
-
- if (ar->arWlanState == WLAN_DISABLED) {
- return -EIO;
- }
-
-#ifdef USER_KEYS
- ar->user_saved_keys.keyOk = false;
-#endif /* USER_KEYS */
-
- index = erq->flags & IW_ENCODE_INDEX;
-
- if (index && (((index - 1) < WMI_MIN_KEY_INDEX) ||
- ((index - 1) > WMI_MAX_KEY_INDEX)))
- {
- return -EIO;
- }
-
- ext = (struct iw_encode_ext *)extra;
- if (erq->flags & IW_ENCODE_DISABLED) {
- /*
- * Encryption disabled
- */
- if (index) {
- /*
- * If key index was specified then clear the specified key
- */
- index--;
- A_MEMZERO(ar->arWepKeyList[index].arKey,
- sizeof(ar->arWepKeyList[index].arKey));
- ar->arWepKeyList[index].arKeyLen = 0;
- }
- } else {
- /*
- * Enabling WEP encryption
- */
- if (index) {
- index--; /* keyindex is off base 1 in iwconfig */
- }
-
- keyUsage = 0;
- keyLen = erq->length - sizeof(struct iw_encode_ext);
-
- if (ext->ext_flags & IW_ENCODE_EXT_SET_TX_KEY) {
- keyUsage = TX_USAGE;
- ar->arDefTxKeyIndex = index;
- // Just setting the key index
- if (keyLen == 0) {
- return 0;
- }
- }
-
- if (keyLen <= 0) {
- return -EIO;
- }
-
- /* key follows iw_encode_ext */
- keyData = (u8 *)(ext + 1);
-
- switch (ext->alg) {
- case IW_ENCODE_ALG_WEP:
- keyType = WEP_CRYPT;
-#ifdef USER_KEYS
- ik.ik_type = IEEE80211_CIPHER_WEP;
-#endif /* USER_KEYS */
- if (!IEEE80211_IS_VALID_WEP_CIPHER_LEN(keyLen)) {
- return -EIO;
- }
-
- /* Check whether it is static wep. */
- if (!ar->arConnected) {
- A_MEMZERO(ar->arWepKeyList[index].arKey,
- sizeof(ar->arWepKeyList[index].arKey));
- memcpy(ar->arWepKeyList[index].arKey, keyData, keyLen);
- ar->arWepKeyList[index].arKeyLen = keyLen;
-
- return 0;
- }
- break;
- case IW_ENCODE_ALG_TKIP:
- keyType = TKIP_CRYPT;
-#ifdef USER_KEYS
- ik.ik_type = IEEE80211_CIPHER_TKIP;
-#endif /* USER_KEYS */
- break;
- case IW_ENCODE_ALG_CCMP:
- keyType = AES_CRYPT;
-#ifdef USER_KEYS
- ik.ik_type = IEEE80211_CIPHER_AES_CCM;
-#endif /* USER_KEYS */
- break;
-#ifdef WAPI_ENABLE
- case IW_ENCODE_ALG_SM4:
- if (ar->arWapiEnable) {
- return ar6000_set_wapi_key(dev, info, erq, extra);
- } else {
- return -EIO;
- }
-#endif
- case IW_ENCODE_ALG_PMK:
- ar->arConnectCtrlFlags |= CONNECT_DO_WPA_OFFLOAD;
- return wmi_set_pmk_cmd(ar->arWmi, keyData);
- default:
- return -EIO;
- }
-
-
- if (ext->ext_flags & IW_ENCODE_EXT_GROUP_KEY) {
- keyUsage |= GROUP_USAGE;
- } else {
- keyUsage |= PAIRWISE_USAGE;
- }
-
- if (ext->ext_flags & IW_ENCODE_EXT_RX_SEQ_VALID) {
- memcpy(keyRsc, ext->rx_seq, sizeof(keyRsc));
- } else {
- A_MEMZERO(keyRsc, sizeof(keyRsc));
- }
-
- if (((WPA_PSK_AUTH == ar->arAuthMode) || (WPA2_PSK_AUTH == ar->arAuthMode)) &&
- (GROUP_USAGE & keyUsage))
- {
- A_UNTIMEOUT(&ar->disconnect_timer);
- }
-
- status = wmi_addKey_cmd(ar->arWmi, index, keyType, keyUsage,
- keyLen, keyRsc,
- keyData, KEY_OP_INIT_VAL,
- (u8 *)ext->addr.sa_data,
- SYNC_BOTH_WMIFLAG);
- if (status) {
- return -EIO;
- }
-
-#ifdef USER_KEYS
- ik.ik_keyix = index;
- ik.ik_keylen = keyLen;
- memcpy(ik.ik_keydata, keyData, keyLen);
- memcpy(&ik.ik_keyrsc, keyRsc, sizeof(keyRsc));
- memcpy(ik.ik_macaddr, ext->addr.sa_data, ETH_ALEN);
- if (ext->ext_flags & IW_ENCODE_EXT_GROUP_KEY) {
- memcpy(&ar->user_saved_keys.bcast_ik, &ik,
- sizeof(struct ieee80211req_key));
- } else {
- memcpy(&ar->user_saved_keys.ucast_ik, &ik,
- sizeof(struct ieee80211req_key));
- }
- ar->user_saved_keys.keyOk = true;
-#endif /* USER_KEYS */
- }
-
-
- return 0;
-}
-
-/*
- * SIOCGIWENCODEEXT
- */
-static int
-ar6000_ioctl_giwencodeext(struct net_device *dev,
- struct iw_request_info *info,
- struct iw_point *erq, char *extra)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
-
- if (ar->arWlanState == WLAN_DISABLED) {
- return -EIO;
- }
-
- if (ar->arPairwiseCrypto == NONE_CRYPT) {
- erq->length = 0;
- erq->flags = IW_ENCODE_DISABLED;
- } else {
- erq->length = 0;
- }
-
- return 0;
-}
-#endif // WIRELESS_EXT >= 18
-
-#if WIRELESS_EXT > 20
-static int ar6000_ioctl_siwpower(struct net_device *dev,
- struct iw_request_info *info,
- union iwreq_data *wrqu, char *extra)
-{
-#ifndef ATH6K_CONFIG_OTA_MODE
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
- WMI_POWER_MODE power_mode;
-
- if (ar->arWmiReady == false) {
- return -EIO;
- }
-
- if (ar->arWlanState == WLAN_DISABLED) {
- return -EIO;
- }
-
- if (wrqu->power.disabled)
- power_mode = MAX_PERF_POWER;
- else
- power_mode = REC_POWER;
-
- if (wmi_powermode_cmd(ar->arWmi, power_mode) < 0)
- return -EIO;
-#endif
- return 0;
-}
-
-static int ar6000_ioctl_giwpower(struct net_device *dev,
- struct iw_request_info *info,
- union iwreq_data *wrqu, char *extra)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
- WMI_POWER_MODE power_mode;
-
- if (ar->arWmiReady == false) {
- return -EIO;
- }
-
- if (ar->arWlanState == WLAN_DISABLED) {
- return -EIO;
- }
-
- power_mode = wmi_get_power_mode_cmd(ar->arWmi);
-
- if (power_mode == MAX_PERF_POWER)
- wrqu->power.disabled = 1;
- else
- wrqu->power.disabled = 0;
-
- return 0;
-}
-#endif // WIRELESS_EXT > 20
-
-/*
- * SIOCGIWNAME
- */
-int
-ar6000_ioctl_giwname(struct net_device *dev,
- struct iw_request_info *info,
- char *name, char *extra)
-{
- u8 capability;
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
-
- if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != 0) {
- A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
- return -EOPNOTSUPP;
- }
-
- if (ar->arWlanState == WLAN_DISABLED) {
- return -EIO;
- }
-
- capability = ar->arPhyCapability;
- if(ar->arNetworkType == INFRA_NETWORK && ar->arConnected) {
- bss_t *bss = wmi_find_node(ar->arWmi, ar->arBssid);
- if (bss) {
- capability = get_bss_phy_capability(bss);
- wmi_node_return(ar->arWmi, bss);
- }
- }
- switch (capability) {
- case (WMI_11A_CAPABILITY):
- strncpy(name, "AR6000 802.11a", IFNAMSIZ);
- break;
- case (WMI_11G_CAPABILITY):
- strncpy(name, "AR6000 802.11g", IFNAMSIZ);
- break;
- case (WMI_11AG_CAPABILITY):
- strncpy(name, "AR6000 802.11ag", IFNAMSIZ);
- break;
- case (WMI_11NA_CAPABILITY):
- strncpy(name, "AR6000 802.11na", IFNAMSIZ);
- break;
- case (WMI_11NG_CAPABILITY):
- strncpy(name, "AR6000 802.11ng", IFNAMSIZ);
- break;
- case (WMI_11NAG_CAPABILITY):
- strncpy(name, "AR6000 802.11nag", IFNAMSIZ);
- break;
- default:
- strncpy(name, "AR6000 802.11b", IFNAMSIZ);
- break;
- }
-
- return 0;
-}
-
-/*
- * SIOCSIWFREQ
- */
-int
-ar6000_ioctl_siwfreq(struct net_device *dev,
- struct iw_request_info *info,
- struct iw_freq *freq, char *extra)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
-
- if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != 0) {
- A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
- return -EOPNOTSUPP;
- }
-
- if (ar->arWlanState == WLAN_DISABLED) {
- return -EIO;
- }
-
- /*
- * We support limiting the channels via wmiconfig.
- *
- * We use this command to configure the channel hint for the connect cmd
- * so it is possible the target will end up connecting to a different
- * channel.
- */
- if (freq->e > 1) {
- return -EINVAL;
- } else if (freq->e == 1) {
- ar->arChannelHint = freq->m / 100000;
- } else {
- if(freq->m) {
- ar->arChannelHint = wlan_ieee2freq(freq->m);
- } else {
- /* Auto Channel Selection */
- ar->arChannelHint = 0;
- }
- }
-
- ar->ap_profile_flag = 1; /* There is a change in profile */
-
- A_PRINTF("channel hint set to %d\n", ar->arChannelHint);
- return 0;
-}
-
-/*
- * SIOCGIWFREQ
- */
-int
-ar6000_ioctl_giwfreq(struct net_device *dev,
- struct iw_request_info *info,
- struct iw_freq *freq, char *extra)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
-
- if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != 0) {
- A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
- return -EOPNOTSUPP;
- }
-
- if (ar->arWlanState == WLAN_DISABLED) {
- return -EIO;
- }
-
- if (ar->arNetworkType == AP_NETWORK) {
- if(ar->arChannelHint) {
- freq->m = ar->arChannelHint * 100000;
- } else if(ar->arACS) {
- freq->m = ar->arACS * 100000;
- } else {
- return -EINVAL;
- }
- } else {
- if (ar->arConnected != true) {
- return -EINVAL;
- } else {
- freq->m = ar->arBssChannel * 100000;
- }
- }
-
- freq->e = 1;
-
- return 0;
-}
-
-/*
- * SIOCSIWMODE
- */
-int
-ar6000_ioctl_siwmode(struct net_device *dev,
- struct iw_request_info *info,
- __u32 *mode, char *extra)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
-
- if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != 0) {
- A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
- return -EOPNOTSUPP;
- }
-
- if (ar->arWlanState == WLAN_DISABLED) {
- return -EIO;
- }
-
- /*
- * clear SSID during mode switch in connected state
- */
- if(!(ar->arNetworkType == (((*mode) == IW_MODE_INFRA) ? INFRA_NETWORK : ADHOC_NETWORK)) && (ar->arConnected == true) ){
- A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
- ar->arSsidLen = 0;
- }
-
- switch (*mode) {
- case IW_MODE_INFRA:
- ar->arNextMode = INFRA_NETWORK;
- break;
- case IW_MODE_ADHOC:
- ar->arNextMode = ADHOC_NETWORK;
- break;
- case IW_MODE_MASTER:
- ar->arNextMode = AP_NETWORK;
- break;
- default:
- return -EINVAL;
- }
-
- /* clear all shared parameters between AP and STA|IBSS modes when we
- * switch between them. Switch between STA & IBSS modes does'nt clear
- * the shared profile. This is as per the original design for switching
- * between STA & IBSS.
- */
- if (ar->arNetworkType == AP_NETWORK || ar->arNextMode == AP_NETWORK) {
- ar->arDot11AuthMode = OPEN_AUTH;
- ar->arAuthMode = NONE_AUTH;
- ar->arPairwiseCrypto = NONE_CRYPT;
- ar->arPairwiseCryptoLen = 0;
- ar->arGroupCrypto = NONE_CRYPT;
- ar->arGroupCryptoLen = 0;
- ar->arChannelHint = 0;
- ar->arBssChannel = 0;
- A_MEMZERO(ar->arBssid, sizeof(ar->arBssid));
- A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
- ar->arSsidLen = 0;
- }
-
- /* SSID has to be cleared to trigger a profile change while switching
- * between STA & IBSS modes having the same SSID
- */
- if (ar->arNetworkType != ar->arNextMode) {
- A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
- ar->arSsidLen = 0;
- }
-
- return 0;
-}
-
-/*
- * SIOCGIWMODE
- */
-int
-ar6000_ioctl_giwmode(struct net_device *dev,
- struct iw_request_info *info,
- __u32 *mode, char *extra)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
-
- if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != 0) {
- A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
- return -EOPNOTSUPP;
- }
-
- if (ar->arWlanState == WLAN_DISABLED) {
- return -EIO;
- }
-
- switch (ar->arNetworkType) {
- case INFRA_NETWORK:
- *mode = IW_MODE_INFRA;
- break;
- case ADHOC_NETWORK:
- *mode = IW_MODE_ADHOC;
- break;
- case AP_NETWORK:
- *mode = IW_MODE_MASTER;
- break;
- default:
- return -EIO;
- }
- return 0;
-}
-
-/*
- * SIOCSIWSENS
- */
-int
-ar6000_ioctl_siwsens(struct net_device *dev,
- struct iw_request_info *info,
- struct iw_param *sens, char *extra)
-{
- return 0;
-}
-
-/*
- * SIOCGIWSENS
- */
-int
-ar6000_ioctl_giwsens(struct net_device *dev,
- struct iw_request_info *info,
- struct iw_param *sens, char *extra)
-{
- sens->value = 0;
- sens->fixed = 1;
-
- return 0;
-}
-
-/*
- * SIOCGIWRANGE
- */
-int
-ar6000_ioctl_giwrange(struct net_device *dev,
- struct iw_request_info *info,
- struct iw_point *data, char *extra)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
- struct iw_range *range = (struct iw_range *) extra;
- int i, ret = 0;
-
- if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != 0) {
- A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
- return -EOPNOTSUPP;
- }
-
- if (ar->bIsDestroyProgress) {
- return -EBUSY;
- }
-
- if (ar->arWmiReady == false) {
- return -EIO;
- }
-
- if (down_interruptible(&ar->arSem)) {
- return -ERESTARTSYS;
- }
-
- if (ar->bIsDestroyProgress) {
- up(&ar->arSem);
- return -EBUSY;
- }
-
- ar->arNumChannels = -1;
- A_MEMZERO(ar->arChannelList, sizeof (ar->arChannelList));
-
- if (wmi_get_channelList_cmd(ar->arWmi) != 0) {
- up(&ar->arSem);
- return -EIO;
- }
-
- wait_event_interruptible_timeout(arEvent, ar->arNumChannels != -1, wmitimeout * HZ);
-
- if (signal_pending(current)) {
- up(&ar->arSem);
- return -EINTR;
- }
-
- data->length = sizeof(struct iw_range);
- A_MEMZERO(range, sizeof(struct iw_range));
-
- range->txpower_capa = 0;
-
- range->min_pmp = 1 * 1024;
- range->max_pmp = 65535 * 1024;
- range->min_pmt = 1 * 1024;
- range->max_pmt = 1000 * 1024;
- range->pmp_flags = IW_POWER_PERIOD;
- range->pmt_flags = IW_POWER_TIMEOUT;
- range->pm_capa = 0;
-
- range->we_version_compiled = WIRELESS_EXT;
- range->we_version_source = 13;
-
- range->retry_capa = IW_RETRY_LIMIT;
- range->retry_flags = IW_RETRY_LIMIT;
- range->min_retry = 0;
- range->max_retry = 255;
-
- range->num_frequency = range->num_channels = ar->arNumChannels;
- for (i = 0; i < ar->arNumChannels; i++) {
- range->freq[i].i = wlan_freq2ieee(ar->arChannelList[i]);
- range->freq[i].m = ar->arChannelList[i] * 100000;
- range->freq[i].e = 1;
- /*
- * Linux supports max of 32 channels, bail out once you
- * reach the max.
- */
- if (i == IW_MAX_FREQUENCIES) {
- break;
- }
- }
-
- /* Max quality is max field value minus noise floor */
- range->max_qual.qual = 0xff - 161;
-
- /*
- * In order to use dBm measurements, 'level' must be lower
- * than any possible measurement (see iw_print_stats() in
- * wireless tools). It's unclear how this is meant to be
- * done, but setting zero in these values forces dBm and
- * the actual numbers are not used.
- */
- range->max_qual.level = 0;
- range->max_qual.noise = 0;
-
- range->sensitivity = 3;
-
- range->max_encoding_tokens = 4;
- /* XXX query driver to find out supported key sizes */
- range->num_encoding_sizes = 3;
- range->encoding_size[0] = 5; /* 40-bit */
- range->encoding_size[1] = 13; /* 104-bit */
- range->encoding_size[2] = 16; /* 128-bit */
-
- range->num_bitrates = 0;
-
- /* estimated maximum TCP throughput values (bps) */
- range->throughput = 22000000;
-
- range->min_rts = 0;
- range->max_rts = 2347;
- range->min_frag = 256;
- range->max_frag = 2346;
-
- up(&ar->arSem);
-
- return ret;
-}
-
-
-/*
- * SIOCSIWAP
- * This ioctl is used to set the desired bssid for the connect command.
- */
-int
-ar6000_ioctl_siwap(struct net_device *dev,
- struct iw_request_info *info,
- struct sockaddr *ap_addr, char *extra)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
-
- if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != 0) {
- A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
- return -EOPNOTSUPP;
- }
-
- if (ar->arWlanState == WLAN_DISABLED) {
- return -EIO;
- }
-
- if (ap_addr->sa_family != ARPHRD_ETHER) {
- return -EIO;
- }
-
- if (memcmp(&ap_addr->sa_data, bcast_mac, AR6000_ETH_ADDR_LEN) == 0) {
- A_MEMZERO(ar->arReqBssid, sizeof(ar->arReqBssid));
- } else {
- memcpy(ar->arReqBssid, &ap_addr->sa_data, sizeof(ar->arReqBssid));
- }
-
- return 0;
-}
-
-/*
- * SIOCGIWAP
- */
-int
-ar6000_ioctl_giwap(struct net_device *dev,
- struct iw_request_info *info,
- struct sockaddr *ap_addr, char *extra)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
-
- if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != 0) {
- A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
- return -EOPNOTSUPP;
- }
-
- if (ar->arWlanState == WLAN_DISABLED) {
- return -EIO;
- }
-
- if (ar->arNetworkType == AP_NETWORK) {
- memcpy(&ap_addr->sa_data, dev->dev_addr, ATH_MAC_LEN);
- ap_addr->sa_family = ARPHRD_ETHER;
- return 0;
- }
-
- if (ar->arConnected != true) {
- return -EINVAL;
- }
-
- memcpy(&ap_addr->sa_data, ar->arBssid, sizeof(ar->arBssid));
- ap_addr->sa_family = ARPHRD_ETHER;
-
- return 0;
-}
-
-#if (WIRELESS_EXT >= 18)
-/*
- * SIOCSIWMLME
- */
-int
-ar6000_ioctl_siwmlme(struct net_device *dev,
- struct iw_request_info *info,
- struct iw_point *data, char *extra)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
-
- if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != 0) {
- A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
- return -EOPNOTSUPP;
- }
-
- if (ar->bIsDestroyProgress) {
- return -EBUSY;
- }
-
- if (ar->arWlanState == WLAN_DISABLED) {
- return -EIO;
- }
-
- if (ar->arWmiReady == false) {
- return -EIO;
- }
-
- if (down_interruptible(&ar->arSem)) {
- return -ERESTARTSYS;
- }
-
- if (data->pointer && data->length == sizeof(struct iw_mlme)) {
-
- u8 arNetworkType;
- struct iw_mlme mlme;
-
- if (copy_from_user(&mlme, data->pointer, sizeof(struct iw_mlme)))
- return -EIO;
-
- switch (mlme.cmd) {
-
- case IW_MLME_DEAUTH:
- /* fall through */
- case IW_MLME_DISASSOC:
- if ((ar->arConnected != true) ||
- (memcmp(ar->arBssid, mlme.addr.sa_data, 6) != 0)) {
-
- up(&ar->arSem);
- return -EINVAL;
- }
- wmi_setPmkid_cmd(ar->arWmi, ar->arBssid, NULL, 0);
- arNetworkType = ar->arNetworkType;
- ar6000_init_profile_info(ar);
- ar->arNetworkType = arNetworkType;
- reconnect_flag = 0;
- ar6000_disconnect(ar);
- A_MEMZERO(ar->arSsid, sizeof(ar->arSsid));
- ar->arSsidLen = 0;
- if (ar->arSkipScan == false) {
- A_MEMZERO(ar->arReqBssid, sizeof(ar->arReqBssid));
- }
- break;
-
- case IW_MLME_AUTH:
- /* fall through */
- case IW_MLME_ASSOC:
- /* fall through */
- default:
- up(&ar->arSem);
- return -EOPNOTSUPP;
- }
- }
-
- up(&ar->arSem);
- return 0;
-}
-#endif /* WIRELESS_EXT >= 18 */
-
-/*
- * SIOCGIWAPLIST
- */
-int
-ar6000_ioctl_iwaplist(struct net_device *dev,
- struct iw_request_info *info,
- struct iw_point *data, char *extra)
-{
- return -EIO; /* for now */
-}
-
-/*
- * SIOCSIWSCAN
- */
-int
-ar6000_ioctl_siwscan(struct net_device *dev,
- struct iw_request_info *info,
- struct iw_point *data, char *extra)
-{
-#define ACT_DWELLTIME_DEFAULT 105
-#define HOME_TXDRAIN_TIME 100
-#define SCAN_INT HOME_TXDRAIN_TIME + ACT_DWELLTIME_DEFAULT
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
- int ret = 0;
-
- if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != 0) {
- A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
- return -EOPNOTSUPP;
- }
-
- if (ar->arWmiReady == false) {
- return -EIO;
- }
-
- if (ar->arWlanState == WLAN_DISABLED) {
- return -EIO;
- }
-
- /* If scan is issued in the middle of ongoing scan or connect,
- dont issue another one */
- if ( ar->scan_triggered > 0 ) {
- ++ar->scan_triggered;
- if (ar->scan_triggered < 5) {
- return 0;
- } else {
- AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_SCAN,("Scan request is triggered over 5 times. Not scan complete event\n"));
- }
- }
-
- if (!ar->arUserBssFilter) {
- if (wmi_bssfilter_cmd(ar->arWmi, ALL_BSS_FILTER, 0) != 0) {
- return -EIO;
- }
- }
-
- if (ar->arConnected) {
- if (wmi_get_stats_cmd(ar->arWmi) != 0) {
- return -EIO;
- }
- }
-
-#ifdef ANDROID_ENV
-#if WIRELESS_EXT >= 18
- if (data->pointer && (data->length == sizeof(struct iw_scan_req)))
- {
- if ((data->flags & IW_SCAN_THIS_ESSID) == IW_SCAN_THIS_ESSID)
- {
- struct iw_scan_req req;
- if (copy_from_user(&req, data->pointer, sizeof(struct iw_scan_req)))
- return -EIO;
- if (wmi_probedSsid_cmd(ar->arWmi, 1, SPECIFIC_SSID_FLAG, req.essid_len, req.essid) != 0)
- return -EIO;
- ar->scanSpecificSsid = true;
- }
- else
- {
- if (ar->scanSpecificSsid) {
- if (wmi_probedSsid_cmd(ar->arWmi, 1, DISABLE_SSID_FLAG, 0, NULL) != 0)
- return -EIO;
- ar->scanSpecificSsid = false;
- }
- }
- }
- else
- {
- if (ar->scanSpecificSsid) {
- if (wmi_probedSsid_cmd(ar->arWmi, 1, DISABLE_SSID_FLAG, 0, NULL) != 0)
- return -EIO;
- ar->scanSpecificSsid = false;
- }
- }
-#endif
-#endif /* ANDROID_ENV */
-
- if (wmi_startscan_cmd(ar->arWmi, WMI_LONG_SCAN, false, false, \
- 0, 0, 0, NULL) != 0) {
- ret = -EIO;
- }
-
- if (ret == 0) {
- ar->scan_triggered = 1;
- }
-
- return ret;
-#undef ACT_DWELLTIME_DEFAULT
-#undef HOME_TXDRAIN_TIME
-#undef SCAN_INT
-}
-
-
-/*
- * Units are in db above the noise floor. That means the
- * rssi values reported in the tx/rx descriptors in the
- * driver are the SNR expressed in db.
- *
- * If you assume that the noise floor is -95, which is an
- * excellent assumption 99.5 % of the time, then you can
- * derive the absolute signal level (i.e. -95 + rssi).
- * There are some other slight factors to take into account
- * depending on whether the rssi measurement is from 11b,
- * 11g, or 11a. These differences are at most 2db and
- * can be documented.
- *
- * NB: various calculations are based on the orinoco/wavelan
- * drivers for compatibility
- */
-static void
-ar6000_set_quality(struct iw_quality *iq, s8 rssi)
-{
- if (rssi < 0) {
- iq->qual = 0;
- } else {
- iq->qual = rssi;
- }
-
- /* NB: max is 94 because noise is hardcoded to 161 */
- if (iq->qual > 94)
- iq->qual = 94;
-
- iq->noise = 161; /* -95dBm */
- iq->level = iq->noise + iq->qual;
- iq->updated = 7;
-}
-
-
-int
-ar6000_ioctl_siwcommit(struct net_device *dev,
- struct iw_request_info *info,
- struct iw_point *data, char *extra)
-{
- struct ar6_softc *ar = (struct ar6_softc *)ar6k_priv(dev);
-
- if (is_iwioctl_allowed(ar->arNextMode, info->cmd) != 0) {
- A_PRINTF("wext_ioctl: cmd=0x%x not allowed in this mode\n", info->cmd);
- return -EOPNOTSUPP;
- }
-
- if (ar->arWmiReady == false) {
- return -EIO;
- }
-
- if (ar->arWlanState == WLAN_DISABLED) {
- return -EIO;
- }
-
- AR_DEBUG_PRINTF(ATH_DEBUG_WLAN_CONNECT,("AP: SSID %s freq %d authmode %d dot11 auth %d"\
- " PW crypto %d GRP crypto %d\n",
- ar->arSsid, ar->arChannelHint,
- ar->arAuthMode, ar->arDot11AuthMode,
- ar->arPairwiseCrypto, ar->arGroupCrypto));
-
- ar6000_ap_mode_profile_commit(ar);
-
- /* if there is a profile switch from STA|IBSS mode to AP mode,
- * update the host driver association state for the STA|IBSS mode.
- */
- if (ar->arNetworkType != AP_NETWORK && ar->arNextMode == AP_NETWORK) {
- /* Stop getting pkts from upper stack */
- netif_stop_queue(ar->arNetDev);
- A_MEMZERO(ar->arBssid, sizeof(ar->arBssid));
- ar->arBssChannel = 0;
- ar->arBeaconInterval = 0;
-
- /* Flush the Tx queues */
- ar6000_TxDataCleanup(ar);
-
- /* Start getting pkts from upper stack */
- netif_wake_queue(ar->arNetDev);
- }
-
- return 0;
-}
-
-#define W_PROTO(_x) wait_ ## _x
-#define WAIT_HANDLER_IMPL(_x, type) \
-int wait_ ## _x (struct net_device *dev, struct iw_request_info *info, type wrqu, char *extra) {\
- int ret; \
- dev_hold(dev); \
- rtnl_unlock(); \
- ret = _x(dev, info, wrqu, extra); \
- rtnl_lock(); \
- dev_put(dev); \
- return ret;\
-}
-
-WAIT_HANDLER_IMPL(ar6000_ioctl_siwessid, struct iw_point *)
-WAIT_HANDLER_IMPL(ar6000_ioctl_giwrate, struct iw_param *)
-WAIT_HANDLER_IMPL(ar6000_ioctl_giwtxpow, struct iw_param *)
-WAIT_HANDLER_IMPL(ar6000_ioctl_giwrange, struct iw_point*)
-
-/* Structures to export the Wireless Handlers */
-static const iw_handler ath_handlers[] = {
- (iw_handler) ar6000_ioctl_siwcommit, /* SIOCSIWCOMMIT */
- (iw_handler) ar6000_ioctl_giwname, /* SIOCGIWNAME */
- (iw_handler) NULL, /* SIOCSIWNWID */
- (iw_handler) NULL, /* SIOCGIWNWID */
- (iw_handler) ar6000_ioctl_siwfreq, /* SIOCSIWFREQ */
- (iw_handler) ar6000_ioctl_giwfreq, /* SIOCGIWFREQ */
- (iw_handler) ar6000_ioctl_siwmode, /* SIOCSIWMODE */
- (iw_handler) ar6000_ioctl_giwmode, /* SIOCGIWMODE */
- (iw_handler) ar6000_ioctl_siwsens, /* SIOCSIWSENS */
- (iw_handler) ar6000_ioctl_giwsens, /* SIOCGIWSENS */
- (iw_handler) NULL /* not _used */, /* SIOCSIWRANGE */
- (iw_handler) W_PROTO(ar6000_ioctl_giwrange),/* SIOCGIWRANGE */
- (iw_handler) NULL /* not used */, /* SIOCSIWPRIV */
- (iw_handler) NULL /* kernel code */, /* SIOCGIWPRIV */
- (iw_handler) NULL /* not used */, /* SIOCSIWSTATS */
- (iw_handler) NULL /* kernel code */, /* SIOCGIWSTATS */
- (iw_handler) NULL, /* SIOCSIWSPY */
- (iw_handler) NULL, /* SIOCGIWSPY */
- (iw_handler) NULL, /* SIOCSIWTHRSPY */
- (iw_handler) NULL, /* SIOCGIWTHRSPY */
- (iw_handler) ar6000_ioctl_siwap, /* SIOCSIWAP */
- (iw_handler) ar6000_ioctl_giwap, /* SIOCGIWAP */
-#if (WIRELESS_EXT >= 18)
- (iw_handler) ar6000_ioctl_siwmlme, /* SIOCSIWMLME */
-#else
- (iw_handler) NULL, /* -- hole -- */
-#endif /* WIRELESS_EXT >= 18 */
- (iw_handler) ar6000_ioctl_iwaplist, /* SIOCGIWAPLIST */
- (iw_handler) ar6000_ioctl_siwscan, /* SIOCSIWSCAN */
- (iw_handler) ar6000_ioctl_giwscan, /* SIOCGIWSCAN */
- (iw_handler) W_PROTO(ar6000_ioctl_siwessid),/* SIOCSIWESSID */
- (iw_handler) ar6000_ioctl_giwessid, /* SIOCGIWESSID */
- (iw_handler) NULL, /* SIOCSIWNICKN */
- (iw_handler) NULL, /* SIOCGIWNICKN */
- (iw_handler) NULL, /* -- hole -- */
- (iw_handler) NULL, /* -- hole -- */
- (iw_handler) ar6000_ioctl_siwrate, /* SIOCSIWRATE */
- (iw_handler) W_PROTO(ar6000_ioctl_giwrate), /* SIOCGIWRATE */
- (iw_handler) NULL, /* SIOCSIWRTS */
- (iw_handler) NULL, /* SIOCGIWRTS */
- (iw_handler) NULL, /* SIOCSIWFRAG */
- (iw_handler) NULL, /* SIOCGIWFRAG */
- (iw_handler) ar6000_ioctl_siwtxpow, /* SIOCSIWTXPOW */
- (iw_handler) W_PROTO(ar6000_ioctl_giwtxpow),/* SIOCGIWTXPOW */
- (iw_handler) ar6000_ioctl_siwretry, /* SIOCSIWRETRY */
- (iw_handler) ar6000_ioctl_giwretry, /* SIOCGIWRETRY */
- (iw_handler) ar6000_ioctl_siwencode, /* SIOCSIWENCODE */
- (iw_handler) ar6000_ioctl_giwencode, /* SIOCGIWENCODE */
-#if WIRELESS_EXT > 20
- (iw_handler) ar6000_ioctl_siwpower, /* SIOCSIWPOWER */
- (iw_handler) ar6000_ioctl_giwpower, /* SIOCGIWPOWER */
-#endif // WIRELESS_EXT > 20
-#if WIRELESS_EXT >= 18
- (iw_handler) NULL, /* -- hole -- */
- (iw_handler) NULL, /* -- hole -- */
- (iw_handler) ar6000_ioctl_siwgenie, /* SIOCSIWGENIE */
- (iw_handler) ar6000_ioctl_giwgenie, /* SIOCGIWGENIE */
- (iw_handler) ar6000_ioctl_siwauth, /* SIOCSIWAUTH */
- (iw_handler) ar6000_ioctl_giwauth, /* SIOCGIWAUTH */
- (iw_handler) ar6000_ioctl_siwencodeext, /* SIOCSIWENCODEEXT */
- (iw_handler) ar6000_ioctl_giwencodeext, /* SIOCGIWENCODEEXT */
- (iw_handler) ar6000_ioctl_siwpmksa, /* SIOCSIWPMKSA */
-#endif // WIRELESS_EXT >= 18
-};
-
-struct iw_handler_def ath_iw_handler_def = {
- .standard = (iw_handler *)ath_handlers,
- .num_standard = ARRAY_SIZE(ath_handlers),
- .private = NULL,
- .num_private = 0,
-};
diff --git a/drivers/staging/ath6kl/reorder/rcv_aggr.c b/drivers/staging/ath6kl/reorder/rcv_aggr.c
index 094b227..9b1509e 100644
--- a/drivers/staging/ath6kl/reorder/rcv_aggr.c
+++ b/drivers/staging/ath6kl/reorder/rcv_aggr.c
@@ -21,11 +21,8 @@
*
*/
-#ifdef ATH_AR6K_11N_SUPPORT
-
#include <a_config.h>
#include <athdefs.h>
-#include <a_types.h>
#include <a_osapi.h>
#include <a_debug.h>
#include "pkt_log.h"
@@ -40,7 +37,7 @@
aggr_slice_amsdu(struct aggr_info *p_aggr, struct rxtid *rxtid, void **osbuf);
static void
-aggr_timeout(A_ATH_TIMER arg);
+aggr_timeout(unsigned long arg);
static void
aggr_deque_frms(struct aggr_info *p_aggr, u8 tid, u16 seq_no, u8 order);
@@ -123,7 +120,7 @@
rxtid->hold_q_sz = 0;
if(rxtid->hold_q) {
- A_FREE(rxtid->hold_q);
+ kfree(rxtid->hold_q);
rxtid->hold_q = NULL;
}
@@ -154,7 +151,7 @@
A_NETBUF_FREE(rxtid->hold_q[k].osbuf);
}
}
- A_FREE(rxtid->hold_q);
+ kfree(rxtid->hold_q);
}
/* Free the dispatch q contents*/
while(A_NETBUF_QUEUE_SIZE(&rxtid->q)) {
@@ -168,7 +165,7 @@
while(A_NETBUF_QUEUE_SIZE(&p_aggr->freeQ)) {
A_NETBUF_FREE(A_NETBUF_DEQUEUE(&p_aggr->freeQ));
}
- A_FREE(p_aggr);
+ kfree(p_aggr);
}
A_PRINTF("out aggr_module_destroy\n");
}
@@ -573,7 +570,7 @@
static void
-aggr_timeout(A_ATH_TIMER arg)
+aggr_timeout(unsigned long arg)
{
u8 i,j;
struct aggr_info *p_aggr = (struct aggr_info *)arg;
@@ -662,5 +659,3 @@
A_PRINTF("================================================\n\n");
}
-
-#endif /* ATH_AR6K_11N_SUPPORT */
diff --git a/drivers/staging/ath6kl/wlan/include/ieee80211.h b/drivers/staging/ath6kl/wlan/include/ieee80211.h
index 532ab0e..cf47d06 100644
--- a/drivers/staging/ath6kl/wlan/include/ieee80211.h
+++ b/drivers/staging/ath6kl/wlan/include/ieee80211.h
@@ -23,8 +23,6 @@
#ifndef _NET80211_IEEE80211_H_
#define _NET80211_IEEE80211_H_
-#include "athstartpack.h"
-
/*
* 802.11 protocol definitions.
*/
@@ -396,6 +394,4 @@
#define IEEE80211_PS_MAX_QUEUE 50 /*Maximum no of buffers that can be queues for PS*/
-#include "athendpack.h"
-
#endif /* _NET80211_IEEE80211_H_ */
diff --git a/drivers/staging/ath6kl/wlan/src/wlan_node.c b/drivers/staging/ath6kl/wlan/src/wlan_node.c
index 1a3ac7d..0fe5f4b 100644
--- a/drivers/staging/ath6kl/wlan/src/wlan_node.c
+++ b/drivers/staging/ath6kl/wlan/src/wlan_node.c
@@ -24,7 +24,6 @@
//==============================================================================
#include <a_config.h>
#include <athdefs.h>
-#include <a_types.h>
#include <a_osapi.h>
#define ATH_MODULE_NAME wlan
#include <a_debug.h>
@@ -54,7 +53,7 @@
#endif
#ifdef THREAD_X
-static void wlan_node_timeout(A_ATH_TIMER arg);
+static void wlan_node_timeout(unsigned long arg);
#endif
static bss_t * _ieee80211_find_node (struct ieee80211_node_table *nt,
@@ -72,7 +71,7 @@
{
ni->ni_buf = A_MALLOC_NOWAIT(wh_size);
if (ni->ni_buf == NULL) {
- A_FREE(ni);
+ kfree(ni);
ni = NULL;
return ni;
}
@@ -104,9 +103,9 @@
wlan_node_free(bss_t *ni)
{
if (ni->ni_buf != NULL) {
- A_FREE(ni->ni_buf);
+ kfree(ni->ni_buf);
}
- A_FREE(ni);
+ kfree(ni);
}
void
@@ -375,7 +374,7 @@
#ifdef THREAD_X
static void
-wlan_node_timeout (A_ATH_TIMER arg)
+wlan_node_timeout (unsigned long arg)
{
struct ieee80211_node_table *nt = (struct ieee80211_node_table *)arg;
bss_t *bss, *nextBss;
diff --git a/drivers/staging/ath6kl/wlan/src/wlan_recv_beacon.c b/drivers/staging/ath6kl/wlan/src/wlan_recv_beacon.c
index 9ebfecf..07b8313 100644
--- a/drivers/staging/ath6kl/wlan/src/wlan_recv_beacon.c
+++ b/drivers/staging/ath6kl/wlan/src/wlan_recv_beacon.c
@@ -25,7 +25,6 @@
#include "a_config.h"
#include "athdefs.h"
-#include "a_types.h"
#include "a_osapi.h"
#include <wmi.h>
#include <ieee80211.h>
diff --git a/drivers/staging/ath6kl/wlan/src/wlan_utils.c b/drivers/staging/ath6kl/wlan/src/wlan_utils.c
index fd05e39..bc91599 100644
--- a/drivers/staging/ath6kl/wlan/src/wlan_utils.c
+++ b/drivers/staging/ath6kl/wlan/src/wlan_utils.c
@@ -24,7 +24,6 @@
//==============================================================================
#include <a_config.h>
#include <athdefs.h>
-#include <a_types.h>
#include <a_osapi.h>
/*
diff --git a/drivers/staging/ath6kl/wmi/wmi.c b/drivers/staging/ath6kl/wmi/wmi.c
index a00bf0a..4a17f99 100644
--- a/drivers/staging/ath6kl/wmi/wmi.c
+++ b/drivers/staging/ath6kl/wmi/wmi.c
@@ -25,7 +25,6 @@
#include <a_config.h>
#include <athdefs.h>
-#include <a_types.h>
#include <a_osapi.h>
#include "htc.h"
#include "htc_api.h"
@@ -35,7 +34,6 @@
#include <ieee80211.h>
#include <ieee80211_node.h>
#include "dset_api.h"
-#include "gpio_api.h"
#include "wmi_host.h"
#include "a_drv.h"
#include "a_drv_api.h"
@@ -129,14 +127,6 @@
static int
wmi_set_params_event_rx(struct wmi_t *wmip, u8 *datap, u32 len);
-static int
-wmi_acm_reject_event_rx(struct wmi_t *wmip, u8 *datap, u32 len);
-
-#ifdef CONFIG_HOST_GPIO_SUPPORT
-static int wmi_gpio_intr_rx(struct wmi_t *wmip, u8 *datap, int len);
-static int wmi_gpio_data_rx(struct wmi_t *wmip, u8 *datap, int len);
-static int wmi_gpio_ack_rx(struct wmi_t *wmip, u8 *datap, int len);
-#endif /* CONFIG_HOST_GPIO_SUPPORT */
#ifdef CONFIG_HOST_TCMD_SUPPORT
static int
@@ -187,13 +177,11 @@
static int wmi_peer_node_event_rx (struct wmi_t *wmip, u8 *datap,
int len);
-#ifdef ATH_AR6K_11N_SUPPORT
static int wmi_addba_req_event_rx(struct wmi_t *, u8 *, int);
static int wmi_addba_resp_event_rx(struct wmi_t *, u8 *, int);
static int wmi_delba_req_event_rx(struct wmi_t *, u8 *, int);
static int wmi_btcoex_config_event_rx(struct wmi_t *wmip, u8 *datap, int len);
static int wmi_btcoex_stats_event_rx(struct wmi_t *wmip, u8 *datap, int len);
-#endif
static int wmi_hci_event_rx(struct wmi_t *, u8 *, int);
#ifdef WAPI_ENABLE
@@ -273,8 +261,6 @@
WMM_AC_VO,
};
-#include "athstartpack.h"
-
/* This stuff is used when we want a simple layer-3 visibility */
typedef PREPACK struct _iphdr {
u8 ip_ver_hdrlen; /* version and hdr length */
@@ -292,8 +278,6 @@
u8 ip_dst[4];
} POSTPACK iphdr;
-#include "athendpack.h"
-
static s16 rssi_event_value = 0;
static s16 snr_event_value = 0;
@@ -381,7 +365,7 @@
A_MUTEX_DELETE(&wmip->wmi_lock);
#endif
}
- A_FREE(wmip);
+ kfree(wmip);
}
}
@@ -475,7 +459,6 @@
*pVersion = WMI_META_VERSION_1;
return (0);
}
-#ifdef CONFIG_CHECKSUM_OFFLOAD
case WMI_META_VERSION_2:
{
WMI_TX_META_V2 *pV2 ;
@@ -487,7 +470,6 @@
memcpy(pV2,(WMI_TX_META_V2 *)pTxMetaS,sizeof(WMI_TX_META_V2));
return (0);
}
-#endif
default:
return (0);
}
@@ -525,7 +507,8 @@
}
WMI_DATA_HDR_SET_META(dtHdr, metaVersion);
- //dtHdr->rssi = 0;
+
+ dtHdr->info3 = 0;
return (0);
}
@@ -865,17 +848,6 @@
status = wmi_dset_data_req_rx(wmip, datap, len);
break;
#endif /* CONFIG_HOST_DSET_SUPPORT */
-#ifdef CONFIG_HOST_GPIO_SUPPORT
- case (WMIX_GPIO_INTR_EVENTID):
- wmi_gpio_intr_rx(wmip, datap, len);
- break;
- case (WMIX_GPIO_DATA_EVENTID):
- wmi_gpio_data_rx(wmip, datap, len);
- break;
- case (WMIX_GPIO_ACK_EVENTID):
- wmi_gpio_ack_rx(wmip, datap, len);
- break;
-#endif /* CONFIG_HOST_GPIO_SUPPORT */
case (WMIX_HB_CHALLENGE_RESP_EVENTID):
wmi_hbChallengeResp_rx(wmip, datap, len);
break;
@@ -967,23 +939,19 @@
case (WMI_READY_EVENTID):
A_DPRINTF(DBG_WMI, (DBGFMT "WMI_READY_EVENTID\n", DBGARG));
status = wmi_ready_event_rx(wmip, datap, len);
- A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
A_WMI_DBGLOG_INIT_DONE(wmip->wmi_devt);
break;
case (WMI_CONNECT_EVENTID):
A_DPRINTF(DBG_WMI, (DBGFMT "WMI_CONNECT_EVENTID\n", DBGARG));
status = wmi_connect_event_rx(wmip, datap, len);
- A_WMI_SEND_GENERIC_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
break;
case (WMI_DISCONNECT_EVENTID):
A_DPRINTF(DBG_WMI, (DBGFMT "WMI_DISCONNECT_EVENTID\n", DBGARG));
status = wmi_disconnect_event_rx(wmip, datap, len);
- A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
break;
case (WMI_PEER_NODE_EVENTID):
A_DPRINTF (DBG_WMI, (DBGFMT "WMI_PEER_NODE_EVENTID\n", DBGARG));
status = wmi_peer_node_event_rx(wmip, datap, len);
- A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
break;
case (WMI_TKIP_MICERR_EVENTID):
A_DPRINTF(DBG_WMI, (DBGFMT "WMI_TKIP_MICERR_EVENTID\n", DBGARG));
@@ -1014,7 +982,6 @@
memcpy(bih->bssid, bih2.bssid, ATH_MAC_LEN);
status = wmi_bssInfo_event_rx(wmip, datap, len);
- A_WMI_SEND_GENERIC_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
}
break;
case (WMI_REGDOMAIN_EVENTID):
@@ -1024,13 +991,6 @@
case (WMI_PSTREAM_TIMEOUT_EVENTID):
A_DPRINTF(DBG_WMI, (DBGFMT "WMI_PSTREAM_TIMEOUT_EVENTID\n", DBGARG));
status = wmi_pstream_timeout_event_rx(wmip, datap, len);
- /* pstreams are fatpipe abstractions that get implicitly created.
- * User apps only deal with thinstreams. creation of a thinstream
- * by the user or data traffic flow in an AC triggers implicit
- * pstream creation. Do we need to send this event to App..?
- * no harm in sending it.
- */
- A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
break;
case (WMI_NEIGHBOR_REPORT_EVENTID):
A_DPRINTF(DBG_WMI, (DBGFMT "WMI_NEIGHBOR_REPORT_EVENTID\n", DBGARG));
@@ -1039,7 +999,6 @@
case (WMI_SCAN_COMPLETE_EVENTID):
A_DPRINTF(DBG_WMI, (DBGFMT "WMI_SCAN_COMPLETE_EVENTID\n", DBGARG));
status = wmi_scanComplete_rx(wmip, datap, len);
- A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
break;
case (WMI_CMDERROR_EVENTID):
A_DPRINTF(DBG_WMI, (DBGFMT "WMI_CMDERROR_EVENTID\n", DBGARG));
@@ -1056,7 +1015,6 @@
case (WMI_ERROR_REPORT_EVENTID):
A_DPRINTF(DBG_WMI, (DBGFMT "WMI_ERROR_REPORT_EVENTID\n", DBGARG));
status = wmi_reportErrorEvent_rx(wmip, datap, len);
- A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
break;
case (WMI_OPT_RX_FRAME_EVENTID):
A_DPRINTF(DBG_WMI, (DBGFMT "WMI_OPT_RX_FRAME_EVENTID\n", DBGARG));
@@ -1095,7 +1053,6 @@
case (WMI_TX_RETRY_ERR_EVENTID):
A_DPRINTF(DBG_WMI, (DBGFMT "WMI_TX_RETRY_ERR_EVENTID\n", DBGARG));
status = wmi_txRetryErrEvent_rx(wmip, datap, len);
- A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
break;
case (WMI_SNR_THRESHOLD_EVENTID):
A_DPRINTF(DBG_WMI, (DBGFMT "WMI_SNR_THRESHOLD_EVENTID\n", DBGARG));
@@ -1104,7 +1061,6 @@
case (WMI_LQ_THRESHOLD_EVENTID):
A_DPRINTF(DBG_WMI, (DBGFMT "WMI_LQ_THRESHOLD_EVENTID\n", DBGARG));
status = wmi_lqThresholdEvent_rx(wmip, datap, len);
- A_WMI_SEND_EVENT_TO_APP(wmip->wmi_devt, id, datap, len);
break;
case (WMI_APLIST_EVENTID):
AR_DEBUG_PRINTF(ATH_DEBUG_WMI, ("Received APLIST Event\n"));
@@ -1133,11 +1089,6 @@
A_DPRINTF(DBG_WMI, (DBGFMT "WMI_SET_PARAMS_REPLY Event\n", DBGARG));
status = wmi_set_params_event_rx(wmip, datap, len);
break;
- case (WMI_ACM_REJECT_EVENTID):
- A_DPRINTF(DBG_WMI, (DBGFMT "WMI_SET_PARAMS_REPLY Event\n", DBGARG));
- status = wmi_acm_reject_event_rx(wmip, datap, len);
- break;
-#ifdef ATH_AR6K_11N_SUPPORT
case (WMI_ADDBA_REQ_EVENTID):
status = wmi_addba_req_event_rx(wmip, datap, len);
break;
@@ -1155,7 +1106,6 @@
A_DPRINTF(DBG_WMI, (DBGFMT "WMI_BTCOEX_STATS_EVENTID", DBGARG));
status = wmi_btcoex_stats_event_rx(wmip, datap, len);
break;
-#endif
case (WMI_TX_COMPLETE_EVENTID):
{
int index;
@@ -1208,7 +1158,7 @@
/* Send a "simple" extended wmi command -- one with no arguments.
Enabling this command only if GPIO or profiling support is enabled.
This is to suppress warnings on some platforms */
-#if defined(CONFIG_HOST_GPIO_SUPPORT) || defined(CONFIG_TARGET_PROFILE_SUPPORT)
+#if defined(CONFIG_TARGET_PROFILE_SUPPORT)
static int
wmi_simple_cmd_xtnd(struct wmi_t *wmip, WMIX_COMMAND_ID cmdid)
{
@@ -2298,46 +2248,6 @@
return 0;
}
-#ifdef CONFIG_HOST_GPIO_SUPPORT
-static int
-wmi_gpio_intr_rx(struct wmi_t *wmip, u8 *datap, int len)
-{
- WMIX_GPIO_INTR_EVENT *gpio_intr = (WMIX_GPIO_INTR_EVENT *)datap;
-
- A_DPRINTF(DBG_WMI,
- (DBGFMT "Enter - intrmask=0x%x input=0x%x.\n", DBGARG,
- gpio_intr->intr_mask, gpio_intr->input_values));
-
- A_WMI_GPIO_INTR_RX(gpio_intr->intr_mask, gpio_intr->input_values);
-
- return 0;
-}
-
-static int
-wmi_gpio_data_rx(struct wmi_t *wmip, u8 *datap, int len)
-{
- WMIX_GPIO_DATA_EVENT *gpio_data = (WMIX_GPIO_DATA_EVENT *)datap;
-
- A_DPRINTF(DBG_WMI,
- (DBGFMT "Enter - reg=%d value=0x%x\n", DBGARG,
- gpio_data->reg_id, gpio_data->value));
-
- A_WMI_GPIO_DATA_RX(gpio_data->reg_id, gpio_data->value);
-
- return 0;
-}
-
-static int
-wmi_gpio_ack_rx(struct wmi_t *wmip, u8 *datap, int len)
-{
- A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
-
- A_WMI_GPIO_ACK_RX();
-
- return 0;
-}
-#endif /* CONFIG_HOST_GPIO_SUPPORT */
-
/*
* Called to send a wmi command. Command specific data is already built
* on osbuf and current osbuf->data points to it.
@@ -3075,6 +2985,7 @@
dtHdr->info =
(SYNC_MSGTYPE & WMI_DATA_HDR_MSG_TYPE_MASK) << WMI_DATA_HDR_MSG_TYPE_SHIFT;
+ dtHdr->info3 = 0;
A_DPRINTF(DBG_WMI, (DBGFMT "Enter - eid %d\n", DBGARG, eid));
return (A_WMI_CONTROL_TX(wmip->wmi_devt, osbuf, eid));
@@ -4282,132 +4193,6 @@
NO_SYNC_WMIFLAG));
}
-#ifdef CONFIG_HOST_GPIO_SUPPORT
-/* Send a command to Target to change GPIO output pins. */
-int
-wmi_gpio_output_set(struct wmi_t *wmip,
- u32 set_mask,
- u32 clear_mask,
- u32 enable_mask,
- u32 disable_mask)
-{
- void *osbuf;
- WMIX_GPIO_OUTPUT_SET_CMD *output_set;
- int size;
-
- size = sizeof(*output_set);
-
- A_DPRINTF(DBG_WMI,
- (DBGFMT "Enter - set=0x%x clear=0x%x enb=0x%x dis=0x%x\n", DBGARG,
- set_mask, clear_mask, enable_mask, disable_mask));
-
- osbuf = A_NETBUF_ALLOC(size);
- if (osbuf == NULL) {
- return A_NO_MEMORY;
- }
- A_NETBUF_PUT(osbuf, size);
- output_set = (WMIX_GPIO_OUTPUT_SET_CMD *)(A_NETBUF_DATA(osbuf));
-
- output_set->set_mask = set_mask;
- output_set->clear_mask = clear_mask;
- output_set->enable_mask = enable_mask;
- output_set->disable_mask = disable_mask;
-
- return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_GPIO_OUTPUT_SET_CMDID,
- NO_SYNC_WMIFLAG));
-}
-
-/* Send a command to the Target requesting state of the GPIO input pins */
-int
-wmi_gpio_input_get(struct wmi_t *wmip)
-{
- A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
-
- return wmi_simple_cmd_xtnd(wmip, WMIX_GPIO_INPUT_GET_CMDID);
-}
-
-/* Send a command to the Target that changes the value of a GPIO register. */
-int
-wmi_gpio_register_set(struct wmi_t *wmip,
- u32 gpioreg_id,
- u32 value)
-{
- void *osbuf;
- WMIX_GPIO_REGISTER_SET_CMD *register_set;
- int size;
-
- size = sizeof(*register_set);
-
- A_DPRINTF(DBG_WMI,
- (DBGFMT "Enter - reg=%d value=0x%x\n", DBGARG, gpioreg_id, value));
-
- osbuf = A_NETBUF_ALLOC(size);
- if (osbuf == NULL) {
- return A_NO_MEMORY;
- }
- A_NETBUF_PUT(osbuf, size);
- register_set = (WMIX_GPIO_REGISTER_SET_CMD *)(A_NETBUF_DATA(osbuf));
-
- register_set->gpioreg_id = gpioreg_id;
- register_set->value = value;
-
- return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_GPIO_REGISTER_SET_CMDID,
- NO_SYNC_WMIFLAG));
-}
-
-/* Send a command to the Target to fetch the value of a GPIO register. */
-int
-wmi_gpio_register_get(struct wmi_t *wmip,
- u32 gpioreg_id)
-{
- void *osbuf;
- WMIX_GPIO_REGISTER_GET_CMD *register_get;
- int size;
-
- size = sizeof(*register_get);
-
- A_DPRINTF(DBG_WMI, (DBGFMT "Enter - reg=%d\n", DBGARG, gpioreg_id));
-
- osbuf = A_NETBUF_ALLOC(size);
- if (osbuf == NULL) {
- return A_NO_MEMORY;
- }
- A_NETBUF_PUT(osbuf, size);
- register_get = (WMIX_GPIO_REGISTER_GET_CMD *)(A_NETBUF_DATA(osbuf));
-
- register_get->gpioreg_id = gpioreg_id;
-
- return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_GPIO_REGISTER_GET_CMDID,
- NO_SYNC_WMIFLAG));
-}
-
-/* Send a command to the Target acknowledging some GPIO interrupts. */
-int
-wmi_gpio_intr_ack(struct wmi_t *wmip,
- u32 ack_mask)
-{
- void *osbuf;
- WMIX_GPIO_INTR_ACK_CMD *intr_ack;
- int size;
-
- size = sizeof(*intr_ack);
-
- A_DPRINTF(DBG_WMI, (DBGFMT "Enter ack_mask=0x%x\n", DBGARG, ack_mask));
-
- osbuf = A_NETBUF_ALLOC(size);
- if (osbuf == NULL) {
- return A_NO_MEMORY;
- }
- A_NETBUF_PUT(osbuf, size);
- intr_ack = (WMIX_GPIO_INTR_ACK_CMD *)(A_NETBUF_DATA(osbuf));
-
- intr_ack->ack_mask = ack_mask;
-
- return (wmi_cmd_send_xtnd(wmip, osbuf, WMIX_GPIO_INTR_ACK_CMDID,
- NO_SYNC_WMIFLAG));
-}
-#endif /* CONFIG_HOST_GPIO_SUPPORT */
-
int
wmi_set_access_params_cmd(struct wmi_t *wmip, u8 ac, u16 txop, u8 eCWmin,
u8 eCWmax, u8 aifsn)
@@ -4683,8 +4468,6 @@
A_DPRINTF(DBG_WMI, (DBGFMT "Enter\n", DBGARG));
- A_WMI_TCMD_RX_REPORT_EVENT(wmip->wmi_devt, datap, len);
-
return 0;
}
@@ -5500,19 +5283,6 @@
}
-
-static int
-wmi_acm_reject_event_rx(struct wmi_t *wmip, u8 *datap, u32 len)
-{
- WMI_ACM_REJECT_EVENT *ev;
-
- ev = (WMI_ACM_REJECT_EVENT *)datap;
- wmip->wmi_traffic_class = ev->trafficClass;
- printk("ACM REJECT %d\n",wmip->wmi_traffic_class);
- return 0;
-}
-
-
#ifdef CONFIG_HOST_DSET_SUPPORT
int
wmi_dset_data_reply(struct wmi_t *wmip,
@@ -5877,7 +5647,7 @@
ar6000_scan_indication (wmip->wmi_devt, pAr6kScanIndEvent, size);
- A_FREE(pAr6kScanIndEvent);
+ kfree(pAr6kScanIndEvent);
}
#endif
@@ -5995,7 +5765,6 @@
return 0;
}
-#ifdef ATH_AR6K_11N_SUPPORT
static int
wmi_addba_req_event_rx(struct wmi_t *wmip, u8 *datap, int len)
{
@@ -6048,7 +5817,6 @@
return 0;
}
-#endif
static int
wmi_hci_event_rx(struct wmi_t *wmip, u8 *datap, int len)
@@ -6372,7 +6140,6 @@
return (wmi_cmd_send(wmip, osbuf, WMI_AP_SET_11BG_RATESET_CMDID, NO_SYNC_WMIFLAG));
}
-#ifdef ATH_AR6K_11N_SUPPORT
int
wmi_set_ht_cap_cmd(struct wmi_t *wmip, WMI_SET_HT_CAP_CMD *cmd)
{
@@ -6418,7 +6185,6 @@
return (wmi_cmd_send(wmip, osbuf, WMI_SET_HT_OP_CMDID,
NO_SYNC_WMIFLAG));
}
-#endif
int
wmi_set_tx_select_rates_cmd(struct wmi_t *wmip, u32 *pMaskArray)
@@ -6460,7 +6226,6 @@
return (wmi_cmd_send(wmip, osbuf, WMI_HCI_CMD_CMDID, NO_SYNC_WMIFLAG));
}
-#ifdef ATH_AR6K_11N_SUPPORT
int
wmi_allow_aggr_cmd(struct wmi_t *wmip, u16 tx_tidmask, u16 rx_tidmask)
{
@@ -6520,7 +6285,6 @@
/* Delete the local aggr state, on host */
return (wmi_cmd_send(wmip, osbuf, WMI_DELBA_REQ_CMDID, NO_SYNC_WMIFLAG));
}
-#endif
int
wmi_set_rx_frame_format_cmd(struct wmi_t *wmip, u8 rxMetaVersion,
diff --git a/drivers/staging/brcm80211/Kconfig b/drivers/staging/brcm80211/Kconfig
index b6f8635..f4cf9b2 100644
--- a/drivers/staging/brcm80211/Kconfig
+++ b/drivers/staging/brcm80211/Kconfig
@@ -1,21 +1,26 @@
-menuconfig BRCM80211
- tristate "Broadcom IEEE802.11n WLAN drivers"
- depends on WLAN
+config BRCMUTIL
+ tristate
+ default n
config BRCMSMAC
- bool "Broadcom IEEE802.11n PCIe SoftMAC WLAN driver"
+ tristate "Broadcom IEEE802.11n PCIe SoftMAC WLAN driver"
+ default n
depends on PCI
- depends on BRCM80211 && MAC80211
+ depends on WLAN && MAC80211
+ select BRCMUTIL
select FW_LOADER
+ select CRC_CCITT
---help---
This module adds support for PCIe wireless adapters based on Broadcom
IEEE802.11n SoftMAC chipsets. If you choose to build a module, it'll
be called brcmsmac.ko.
config BRCMFMAC
- bool "Broadcom IEEE802.11n embedded FullMAC WLAN driver"
+ tristate "Broadcom IEEE802.11n embedded FullMAC WLAN driver"
+ default n
depends on MMC
- depends on BRCM80211 && CFG80211
+ depends on WLAN && CFG80211
+ select BRCMUTIL
select FW_LOADER
select WIRELESS_EXT
select WEXT_PRIV
@@ -28,6 +33,6 @@
config BRCMDBG
bool "Broadcom driver debug functions"
default n
- depends on BRCM80211
+ depends on BRCMSMAC || BRCMFMAC
---help---
Selecting this enables additional code for debug purposes.
diff --git a/drivers/staging/brcm80211/Makefile b/drivers/staging/brcm80211/Makefile
index c064cdf..e7b3f27 100644
--- a/drivers/staging/brcm80211/Makefile
+++ b/drivers/staging/brcm80211/Makefile
@@ -19,5 +19,6 @@
subdir-ccflags-y := -DBCMDMA32
subdir-ccflags-$(CONFIG_BRCMDBG) += -DBCMDBG -DBCMDBG_ASSERT
+obj-$(CONFIG_BRCMUTIL) += util/
obj-$(CONFIG_BRCMFMAC) += brcmfmac/
obj-$(CONFIG_BRCMSMAC) += brcmsmac/
diff --git a/drivers/staging/brcm80211/README b/drivers/staging/brcm80211/README
index f8facb0..8ad5586 100644
--- a/drivers/staging/brcm80211/README
+++ b/drivers/staging/brcm80211/README
@@ -1,90 +1,64 @@
-Broadcom Mac80211 driver
+Broadcom brcmsmac (mac80211-based softmac PCIe) and brcmfmac (SDIO) drivers.
-This is a driver in progress. It has features still to be implemented well as
-bugs in current code.
+Completely open source host drivers, no binary object files.
+
+Support for the following chips:
+===============================
+
+ brcmsmac (PCIe)
+ Name Device ID
+ BCM4313 0x4727
+ BCM43224 0x4353
+ BCM43225 0x4357
+
+ brcmfmac (SDIO)
+ Name
+ BCM4329
+
+Both brcmsmac and brcmfmac drivers require firmware files that need to be
+separately downloaded.
+
+Firmware
+======================
+Firmware is available from the Linux firmware repository at:
+
+ git://git.kernel.org/pub/scm/linux/kernel/git/dwmw2/linux-firmware.git
+ http://git.kernel.org/?p=linux/kernel/git/dwmw2/linux-firmware.git
+ https://git.kernel.org/?p=linux/kernel/git/dwmw2/linux-firmware.git
-What's here and not here
-=======================
-- Completely open source host driver, no binary object files
-- Features Broadcom's OneDriver architecture (single source base for
- supported chips and architectures)
-- On-chip firmware loaded using standard request_firmware()
-- Support for BCM43224, BCM43225, BCM4313 (PCIe NIC)
-- Framework for supporting new chips, including mac80211-aware embedded chips
-- Does not support older PCI/PCIe chips with SSB backplane
-- Driver includes BMAC interface for transparent dongle support
-- Uses minstrel_ht rate algorithm
-- HW based encryption not enabled yet
-
-
-What's done
-==========
-- Integration with mac80211 stack
-- A-MPDU single & dual stream rates
-- BCM43224: Dualband, Dual stream, 20MHz channels
- Throughput (in chamber): ~85-90 Mbits/sec (in both 2.4 & 5 GHz bands)
-- BCM43225: 2.4 GHz, Dual Stream, 20MHz channels
- Throughput (in chamber): ~85-90 Mbits/sec
-- BCM4313: 2.4 GHz, Single Stream
- Throughput (in chamber): ~40 Mbits/sec
-
-
-Things To Be Done
-=================
-See the TODO file
+===============================================================
+Broadcom brcmsmac driver
+===============================================================
+- Support for both 32 and 64 bit Linux kernels
Firmware installation
======================
-Firmware is available from the Linux firmware repository at:
-
- git://git.kernel.org/pub/scm/linux/kernel/git/dwmw2/linux-firmware.git
- http://git.kernel.org/?p=linux/kernel/git/dwmw2/linux-firmware.git
- https://git.kernel.org/?p=linux/kernel/git/dwmw2/linux-firmware.git
-
-For all chips, copy brcm/bcm43xx-0.fw and brcm/bcm43xx_hdr-0.fw to
-/lib/firmware/brcm (or wherever firmware is normally installed on your system).
-
-Currently supported chips
-==============
-PCI
-Name Device ID
-BCM4313 0x4727
-BCM43224 0x4353
-BCM43225 0x4357
+Copy brcm/bcm43xx-0.fw and brcm/bcm43xx_hdr-0.fw to
+/lib/firmware/brcm (or wherever firmware is normally installed
+on your system).
-Bugs/Problems
-==============
-- Driver can get confused while scanning during high throughput, can cause
- burping, hanging, and possible crashing.
-- Occasional hangs & burps with BCM43224 on 2.4 GHz with dual stream rates.
-- Occasional crashes with BCM43224 on multicore machines.
+===============================================================
+Broadcom brcmfmac driver
+===============================================================
+- Support for 32 bit Linux kernel, 64 bit untested
-Note on Regulatory Implementation
-================================
-This generation of chips contain additional regulatory support independent of
-the driver. The devices use a single worldwide regulatory domain, with channels
-12-14 (2.4 GHz band) and channels 52-64 and 100-140 (5 GHz band) restricted to
-passive operation. Transmission on those channels is suppressed until
-appropriate other traffic is observed on those channels.
-
-Within the driver, we use the fictitious country code "X2" to represent this
-worldwide regulatory domain. There is currently no interface to configure a
-different domain.
-
-The driver reads the SROM country code from the chip and hands it up to
-mac80211 as the regulatory hint, however this information is otherwise unused
-with the driver.
+Firmware installation
+======================
+Copy brcm/bcm4329-fullmac-4.bin and brcm/bcm4329-fullmac-4.txt
+to /lib/firmware/brcm (or wherever firmware is normally installed on your
+system).
Contact Info:
=============
Brett Rudley brudley@broadcom.com
Henry Ptasinski henryp@broadcom.com
-Dowan Kim dowan@broadcom.com
+Dowan Kim dowan@broadcom.com
Roland Vossen rvossen@broadcom.com
Arend van Spriel arend@broadcom.com
+For more info, refer to: http://linuxwireless.org/en/users/Drivers/brcm80211
diff --git a/drivers/staging/brcm80211/TODO b/drivers/staging/brcm80211/TODO
index 24ebadb..e9c1393 100644
--- a/drivers/staging/brcm80211/TODO
+++ b/drivers/staging/brcm80211/TODO
@@ -1,51 +1,15 @@
-To Do List for Broadcom Mac80211 driver
-
-Features to be added
-=====================
-- 40 MHz channels
-- Power Save
-- AP
-- IBSS
-- HW-based encryption
-- LED support
-- RFKILL
-- Debugfs and debugability
-
-Code cleanup
-============
-- Use proper kernel coding standards
-- Remove overlap with system header files. (ie much of include/proto/*.h should
- be removed)
-- Purge unused variables/data structs/functions BUT keep code related to
- features that are being added (ie AP mode, 40 Mhz channels, IBSS etc).
-- Replace proprietary utility functions with public kernel versions.
+To Do List for Broadcom Mac80211 driver before getting in mainline
Bugs
====
-- Various occasional asserts/hangs
-- Scanning during data transfer sometimes causes major slowdowns. Sometimes
- revcovers when scan is done, other times not.
-- Mac80211 API not completely implemented (ie ops_bss_info_changed,
- ops_get_stats, etc)
+- Oops on AMPDU traffic, to be solved by new ucode (currently under test)
-Other
-=====
-- wlc_mac80211.[ch], wl_mac80211.[ch] and linux_osl.c all need to be refactored
- and combined.
-- Merge files that are partially duplicated between the softmac and fullmac
- drivers
+brcmfmac and brcmsmac
+=====================
+- ASSERTS not allowed in mainline, replace by warning + error handling
+- Replace printk and WL_ERROR() with proper routines
+
+brcmfmac
+=====================
- Replace driver's proprietary ssb interface with generic kernel ssb module
- (only used when compiling for SDIO).
-- PCI and SDIO support are currently #ifdef'ed exclusive of each other, which
- leads to a separate wl.ko for each. This should be changed to runtime
- handling of different interfaces so that a single binary driver can be built.
-- Add support for new chips (obviously an ongoing item).
-
-Contact
-=====
-Brett Rudley <brudley@broadcom.com>
-Henry Ptasinski <henryp@broadcom.com>
-Dowan Kim <dowan@broadcom.com>
-Roland Vossen <rvossen@broadcom.com>
-Arend van Spriel <arend@broadcom.com>
-
+- Build and test on 64 bit linux kernel
diff --git a/drivers/staging/brcm80211/brcmfmac/Makefile b/drivers/staging/brcm80211/brcmfmac/Makefile
index ac5a7d4..c5ec562 100644
--- a/drivers/staging/brcm80211/brcmfmac/Makefile
+++ b/drivers/staging/brcm80211/brcmfmac/Makefile
@@ -36,8 +36,7 @@
ccflags-y += \
-Idrivers/staging/brcm80211/brcmfmac \
- -Idrivers/staging/brcm80211/include \
- -Idrivers/staging/brcm80211/util
+ -Idrivers/staging/brcm80211/include
DHDOFILES = \
wl_cfg80211.o \
@@ -51,13 +50,7 @@
bcmsdh.o \
bcmsdh_linux.o \
bcmsdh_sdmmc.o \
- bcmsdh_sdmmc_linux.o \
- aiutils.o \
- siutils.o \
- sbutils.o \
- bcmutils.o \
- bcmwifi.o \
- hndpmu.o
+ bcmsdh_sdmmc_linux.o
-obj-m += brcmfmac.o
+obj-$(CONFIG_BRCMFMAC) += brcmfmac.o
brcmfmac-objs += $(DHDOFILES)
diff --git a/drivers/staging/brcm80211/brcmfmac/README b/drivers/staging/brcm80211/brcmfmac/README
index be29e42..139597f 100644
--- a/drivers/staging/brcm80211/brcmfmac/README
+++ b/drivers/staging/brcm80211/brcmfmac/README
@@ -1,37 +1,2 @@
-Broadcom fullmac driver
-This is production driver.
-
-What's here
-===========
-- Completely open source host driver, no binary object files
-- Features Broadcom's OneDriver architecture (single source base for
- supported chips and architectures)
-- On-chip firmware loaded using standard request_firmware()
-- Support for BCM4329(SDIO)
-
-What's done
-==========
-- Integration with cfg80211 stack
-- Most of Mac functionality is performed in dongle
-- A-MPDU single stream rates
-- BCM4329: Dualband, Single stream, 20MHz channels
-
-Firmware installation
-======================
-Firmware is available from the Linux firmware repository at:
-
- git://git.kernel.org/pub/scm/linux/kernel/git/dwmw2/linux-firmware.git
- http://git.kernel.org/?p=linux/kernel/git/dwmw2/linux-firmware.git
- https://git.kernel.org/?p=linux/kernel/git/dwmw2/linux-firmware.git
-
-For 4329 chip, copy brcm/bcm4329-fullmac-4.bin and brcm/bcm4329-fullmac-4.txt
-to /lib/firmware/brcm (or wherever firmware is normally installed on your
-system).
-
-Contact Info:
-=============
-Brett Rudley brudley@broadcom.com
-Henry Ptasinski henryp@broadcom.com
-Nohee Ko noheek@broadcom.com
diff --git a/drivers/staging/brcm80211/brcmfmac/bcmchip.h b/drivers/staging/brcm80211/brcmfmac/bcmchip.h
new file mode 100644
index 0000000..c0d4c3b
--- /dev/null
+++ b/drivers/staging/brcm80211/brcmfmac/bcmchip.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2011 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _bcmchip_h_
+#define _bcmchip_h_
+
+/* Core reg address translation */
+#define CORE_CC_REG(base, field) (base + offsetof(chipcregs_t, field))
+#define CORE_BUS_REG(base, field) (base + offsetof(sdpcmd_regs_t, field))
+#define CORE_SB(base, field) \
+ (base + SBCONFIGOFF + offsetof(sbconfig_t, field))
+
+/* bcm4329 */
+/* SDIO device core, ID 0x829 */
+#define BCM4329_CORE_BUS_BASE 0x18011000
+/* internal memory core, ID 0x80e */
+#define BCM4329_CORE_SOCRAM_BASE 0x18003000
+/* ARM Cortex M3 core, ID 0x82a */
+#define BCM4329_CORE_ARM_BASE 0x18002000
+#define BCM4329_RAMSIZE 0x48000
+
+#endif /* _bcmchip_h_ */
diff --git a/drivers/staging/brcm80211/brcmfmac/bcmsdh.c b/drivers/staging/brcm80211/brcmfmac/bcmsdh.c
index 473f57d..3750fcf 100644
--- a/drivers/staging/brcm80211/brcmfmac/bcmsdh.c
+++ b/drivers/staging/brcm80211/brcmfmac/bcmsdh.c
@@ -17,11 +17,11 @@
#include <linux/types.h>
#include <linux/netdevice.h>
+#include <linux/pci_ids.h>
#include <bcmdefs.h>
#include <bcmdevs.h>
#include <bcmutils.h>
#include <hndsoc.h>
-#include <siutils.h>
#include <bcmsdh.h> /* BRCM API for SDIO
clients (such as wl, dhd) */
@@ -29,6 +29,8 @@
#include <sbsdio.h> /* BRCM sdio device core */
#include <sdio.h> /* sdio spec */
+#include "dngl_stats.h"
+#include "dhd.h"
#define SDIOH_API_ACCESS_RETRY_LIMIT 2
const uint bcmsdh_msglevel = BCMSDH_ERROR_VAL;
@@ -126,7 +128,7 @@
ASSERT(bcmsdh);
status = sdioh_interrupt_set(bcmsdh->sdioh, true);
- return SDIOH_API_SUCCESS(status) ? 0 : BCME_ERROR;
+ return SDIOH_API_SUCCESS(status) ? 0 : -EIO;
}
int bcmsdh_intr_disable(void *sdh)
@@ -136,7 +138,7 @@
ASSERT(bcmsdh);
status = sdioh_interrupt_set(bcmsdh->sdioh, false);
- return SDIOH_API_SUCCESS(status) ? 0 : BCME_ERROR;
+ return SDIOH_API_SUCCESS(status) ? 0 : -EIO;
}
int bcmsdh_intr_reg(void *sdh, bcmsdh_cb_fn_t fn, void *argh)
@@ -146,7 +148,7 @@
ASSERT(bcmsdh);
status = sdioh_interrupt_register(bcmsdh->sdioh, fn, argh);
- return SDIOH_API_SUCCESS(status) ? 0 : BCME_ERROR;
+ return SDIOH_API_SUCCESS(status) ? 0 : -EIO;
}
int bcmsdh_intr_dereg(void *sdh)
@@ -156,7 +158,7 @@
ASSERT(bcmsdh);
status = sdioh_interrupt_deregister(bcmsdh->sdioh);
- return SDIOH_API_SUCCESS(status) ? 0 : BCME_ERROR;
+ return SDIOH_API_SUCCESS(status) ? 0 : -EIO;
}
#if defined(DHD_DEBUG)
@@ -174,7 +176,7 @@
ASSERT(sdh);
/* don't support yet */
- return BCME_UNSUPPORTED;
+ return -ENOTSUPP;
}
u8 bcmsdh_cfg_read(void *sdh, uint fnc_num, u32 addr, int *err)
@@ -204,7 +206,7 @@
&& (retry++ < SDIOH_API_ACCESS_RETRY_LIMIT));
#endif
if (err)
- *err = (SDIOH_API_SUCCESS(status) ? 0 : BCME_SDIO_ERROR);
+ *err = (SDIOH_API_SUCCESS(status) ? 0 : -EIO);
BCMSDH_INFO(("%s:fun = %d, addr = 0x%x, u8data = 0x%x\n",
__func__, fnc_num, addr, data));
@@ -239,7 +241,7 @@
&& (retry++ < SDIOH_API_ACCESS_RETRY_LIMIT));
#endif
if (err)
- *err = SDIOH_API_SUCCESS(status) ? 0 : BCME_SDIO_ERROR;
+ *err = SDIOH_API_SUCCESS(status) ? 0 : -EIO;
BCMSDH_INFO(("%s:fun = %d, addr = 0x%x, u8data = 0x%x\n",
__func__, fnc_num, addr, data));
@@ -261,7 +263,7 @@
fnc_num, addr, &data, 4);
if (err)
- *err = (SDIOH_API_SUCCESS(status) ? 0 : BCME_SDIO_ERROR);
+ *err = (SDIOH_API_SUCCESS(status) ? 0 : -EIO);
BCMSDH_INFO(("%s:fun = %d, addr = 0x%x, u32data = 0x%x\n",
__func__, fnc_num, addr, data));
@@ -286,7 +288,7 @@
SDIOH_WRITE, fnc_num, addr, &data, 4);
if (err)
- *err = (SDIOH_API_SUCCESS(status) ? 0 : BCME_SDIO_ERROR);
+ *err = (SDIOH_API_SUCCESS(status) ? 0 : -EIO);
BCMSDH_INFO(("%s:fun = %d, addr = 0x%x, u32data = 0x%x\n",
__func__, fnc_num, addr, data));
@@ -317,7 +319,7 @@
tmp_buf = kmalloc(length, GFP_ATOMIC);
if (tmp_buf == NULL) {
BCMSDH_ERROR(("%s: out of memory\n", __func__));
- return BCME_NOMEM;
+ return -ENOMEM;
}
memcpy(tmp_buf, cis, length);
for (tmp_ptr = tmp_buf, ptr = cis; ptr < (cis + length - 4);
@@ -329,7 +331,7 @@
kfree(tmp_buf);
}
- return SDIOH_API_SUCCESS(status) ? 0 : BCME_ERROR;
+ return SDIOH_API_SUCCESS(status) ? 0 : -EIO;
}
static int bcmsdhsdio_set_sbaddr_window(void *sdh, u32 address)
@@ -467,7 +469,7 @@
/* Async not implemented yet */
ASSERT(!(flags & SDIO_REQ_ASYNC));
if (flags & SDIO_REQ_ASYNC)
- return BCME_UNSUPPORTED;
+ return -ENOTSUPP;
if (bar0 != bcmsdh->sbwad) {
err = bcmsdhsdio_set_sbaddr_window(bcmsdh, bar0);
@@ -488,7 +490,7 @@
SDIOH_READ, fn, addr, width, nbytes, buf,
pkt);
- return SDIOH_API_SUCCESS(status) ? 0 : BCME_SDIO_ERROR;
+ return SDIOH_API_SUCCESS(status) ? 0 : -EIO;
}
int
@@ -512,7 +514,7 @@
/* Async not implemented yet */
ASSERT(!(flags & SDIO_REQ_ASYNC));
if (flags & SDIO_REQ_ASYNC)
- return BCME_UNSUPPORTED;
+ return -ENOTSUPP;
if (bar0 != bcmsdh->sbwad) {
err = bcmsdhsdio_set_sbaddr_window(bcmsdh, bar0);
@@ -533,7 +535,7 @@
SDIOH_WRITE, fn, addr, width, nbytes, buf,
pkt);
- return SDIOH_API_SUCCESS(status) ? 0 : BCME_ERROR;
+ return SDIOH_API_SUCCESS(status) ? 0 : -EIO;
}
int bcmsdh_rwdata(void *sdh, uint rw, u32 addr, u8 *buf, uint nbytes)
@@ -553,7 +555,7 @@
(rw ? SDIOH_WRITE : SDIOH_READ), SDIO_FUNC_1,
addr, 4, nbytes, buf, NULL);
- return SDIOH_API_SUCCESS(status) ? 0 : BCME_ERROR;
+ return SDIOH_API_SUCCESS(status) ? 0 : -EIO;
}
int bcmsdh_abort(void *sdh, uint fn)
@@ -580,7 +582,7 @@
int bcmsdh_query_device(void *sdh)
{
bcmsdh_info_t *bcmsdh = (bcmsdh_info_t *) sdh;
- bcmsdh->vendevid = (VENDOR_BROADCOM << 16) | 0;
+ bcmsdh->vendevid = (PCI_VENDOR_ID_BROADCOM << 16) | 0;
return bcmsdh->vendevid;
}
diff --git a/drivers/staging/brcm80211/brcmfmac/bcmsdh_linux.c b/drivers/staging/brcm80211/brcmfmac/bcmsdh_linux.c
index ac5bbc8..465f623 100644
--- a/drivers/staging/brcm80211/brcmfmac/bcmsdh_linux.c
+++ b/drivers/staging/brcm80211/brcmfmac/bcmsdh_linux.c
@@ -43,6 +43,9 @@
#include <linux/platform_device.h>
#endif /* CONFIG_MACH_SANDGATE2G */
+#include "dngl_stats.h"
+#include "dhd.h"
+
/**
* SDIO Host Controller info
*/
@@ -87,11 +90,11 @@
return true;
/* Check for BRCM 27XX Standard host controller */
- if (device == BCM27XX_SDIOH_ID && vendor == VENDOR_BROADCOM)
+ if (device == BCM27XX_SDIOH_ID && vendor == PCI_VENDOR_ID_BROADCOM)
return true;
/* Check for BRCM Standard host controller */
- if (device == SDIOH_FPGA_ID && vendor == VENDOR_BROADCOM)
+ if (device == SDIOH_FPGA_ID && vendor == PCI_VENDOR_ID_BROADCOM)
return true;
/* Check for TI PCIxx21 Standard host controller */
@@ -111,8 +114,7 @@
#endif /* BCMSDIOH_STD */
#ifdef BCMSDIOH_SPI
/* This is the PciSpiHost. */
- if (device == SPIH_FPGA_ID && vendor == VENDOR_BROADCOM) {
- WL_NONE("Found PCI SPI Host Controller\n");
+ if (device == SPIH_FPGA_ID && vendor == PCI_VENDOR_ID_BROADCOM) {
return true;
}
#endif /* BCMSDIOH_SPI */
diff --git a/drivers/staging/brcm80211/brcmfmac/bcmsdh_sdmmc.c b/drivers/staging/brcm80211/brcmfmac/bcmsdh_sdmmc.c
index 71c3571..c0ffbd3 100644
--- a/drivers/staging/brcm80211/brcmfmac/bcmsdh_sdmmc.c
+++ b/drivers/staging/brcm80211/brcmfmac/bcmsdh_sdmmc.c
@@ -26,14 +26,11 @@
#include <linux/mmc/core.h>
#include <linux/mmc/sdio_func.h>
#include <linux/mmc/sdio_ids.h>
+#include <linux/suspend.h>
#include <dngl_stats.h>
#include <dhd.h>
-#if defined(CONFIG_PM_SLEEP)
-#include <linux/suspend.h>
-extern volatile bool dhd_mmc_suspend;
-#endif
#include "bcmsdh_sdmmc.h"
extern int sdio_function_init(void);
@@ -68,6 +65,13 @@
int sdioh_sdmmc_card_regread(sdioh_info_t *sd, int func, u32 regaddr,
int regsize, u32 *data);
+void sdioh_sdio_set_host_pm_flags(int flag)
+{
+ if (sdio_set_host_pm_flags(gInstance->func[1], flag))
+ printk(KERN_ERR "%s: Failed to set pm_flags 0x%08x\n",\
+ __func__, (unsigned int)flag);
+}
+
static int sdioh_sdmmc_card_enablefuncs(sdioh_info_t *sd)
{
int err_ret;
@@ -416,7 +420,7 @@
vi = bcm_iovar_lookup(sdioh_iovars, name);
if (vi == NULL) {
- bcmerror = BCME_UNSUPPORTED;
+ bcmerror = -ENOTSUPP;
goto exit;
}
@@ -465,7 +469,7 @@
case IOV_GVAL(IOV_BLOCKSIZE):
if ((u32) int_val > si->num_funcs) {
- bcmerror = BCME_BADARG;
+ bcmerror = -EINVAL;
break;
}
int_val = (s32) si->client_block_size[int_val];
@@ -479,7 +483,7 @@
uint maxsize;
if (func > si->num_funcs) {
- bcmerror = BCME_BADARG;
+ bcmerror = -EINVAL;
break;
}
@@ -497,7 +501,7 @@
maxsize = 0;
}
if (blksize > maxsize) {
- bcmerror = BCME_BADARG;
+ bcmerror = -EINVAL;
break;
}
if (!blksize)
@@ -600,7 +604,7 @@
|| sd_ptr->offset > SD_MaxCurCap) {
sd_err(("%s: bad offset 0x%x\n", __func__,
sd_ptr->offset));
- bcmerror = BCME_BADARG;
+ bcmerror = -EINVAL;
break;
}
@@ -630,7 +634,7 @@
|| sd_ptr->offset > SD_MaxCurCap) {
sd_err(("%s: bad offset 0x%x\n", __func__,
sd_ptr->offset));
- bcmerror = BCME_BADARG;
+ bcmerror = -EINVAL;
break;
}
@@ -649,7 +653,7 @@
if (sdioh_cfg_read
(si, sd_ptr->func, sd_ptr->offset, &data)) {
- bcmerror = BCME_SDIO_ERROR;
+ bcmerror = -EIO;
break;
}
@@ -665,14 +669,14 @@
if (sdioh_cfg_write
(si, sd_ptr->func, sd_ptr->offset, &data)) {
- bcmerror = BCME_SDIO_ERROR;
+ bcmerror = -EIO;
break;
}
break;
}
default:
- bcmerror = BCME_UNSUPPORTED;
+ bcmerror = -ENOTSUPP;
break;
}
exit:
@@ -1006,17 +1010,16 @@
/*
* This function takes a buffer or packet, and fixes everything up
- * so that in the
- * end, a DMA-able packet is created.
+ * so that in the end, a DMA-able packet is created.
*
* A buffer does not have an associated packet pointer,
* and may or may not be aligned.
* A packet may consist of a single packet, or a packet chain.
- * If it is a packet chain,
- * then all the packets in the chain must be properly aligned.
- * If the packet data is not
- * aligned, then there may only be one packet, and in this case,
- * it is copied to a new
+ * If it is a packet chain, then all the packets in the chain
+ * must be properly aligned.
+ *
+ * If the packet data is not aligned, then there may only be
+ * one packet, and in this case, it is copied to a new
* aligned packet.
*
*/
@@ -1036,9 +1039,9 @@
if (pkt == NULL) {
sd_data(("%s: Creating new %s Packet, len=%d\n",
__func__, write ? "TX" : "RX", buflen_u));
- mypkt = pkt_buf_get_skb(buflen_u);
+ mypkt = bcm_pkt_buf_get_skb(buflen_u);
if (!mypkt) {
- sd_err(("%s: pkt_buf_get_skb failed: len %d\n",
+ sd_err(("%s: bcm_pkt_buf_get_skb failed: len %d\n",
__func__, buflen_u));
return SDIOH_API_RC_FAIL;
}
@@ -1054,7 +1057,7 @@
if (!write)
memcpy(buffer, mypkt->data, buflen_u);
- pkt_buf_free_skb(mypkt);
+ bcm_pkt_buf_free_skb(mypkt);
} else if (((u32) (pkt->data) & DMA_ALIGN_MASK) != 0) {
/* Case 2: We have a packet, but it is unaligned. */
@@ -1063,9 +1066,9 @@
sd_data(("%s: Creating aligned %s Packet, len=%d\n",
__func__, write ? "TX" : "RX", pkt->len));
- mypkt = pkt_buf_get_skb(pkt->len);
+ mypkt = bcm_pkt_buf_get_skb(pkt->len);
if (!mypkt) {
- sd_err(("%s: pkt_buf_get_skb failed: len %d\n",
+ sd_err(("%s: bcm_pkt_buf_get_skb failed: len %d\n",
__func__, pkt->len));
return SDIOH_API_RC_FAIL;
}
@@ -1081,7 +1084,7 @@
if (!write)
memcpy(pkt->data, mypkt->data, mypkt->len);
- pkt_buf_free_skb(mypkt);
+ bcm_pkt_buf_free_skb(mypkt);
} else { /* case 3: We have a packet and
it is aligned. */
sd_data(("%s: Aligned %s Packet, direct DMA\n",
diff --git a/drivers/staging/brcm80211/brcmfmac/bcmsdh_sdmmc_linux.c b/drivers/staging/brcm80211/brcmfmac/bcmsdh_sdmmc_linux.c
index d738d4d..2792a4d 100644
--- a/drivers/staging/brcm80211/brcmfmac/bcmsdh_sdmmc_linux.c
+++ b/drivers/staging/brcm80211/brcmfmac/bcmsdh_sdmmc_linux.c
@@ -27,6 +27,9 @@
#include <linux/mmc/sdio_func.h>
#include <linux/mmc/sdio_ids.h>
+#include "dngl_stats.h"
+#include "dhd.h"
+
#if !defined(SDIO_VENDOR_ID_BROADCOM)
#define SDIO_VENDOR_ID_BROADCOM 0x02d0
#endif /* !defined(SDIO_VENDOR_ID_BROADCOM) */
@@ -151,11 +154,11 @@
sdos = kmalloc(sizeof(struct sdos_info), GFP_ATOMIC);
sd->sdos_info = (void *)sdos;
if (sdos == NULL)
- return BCME_NOMEM;
+ return -ENOMEM;
sdos->sd = sd;
spin_lock_init(&sdos->lock);
- return BCME_OK;
+ return 0;
}
void sdioh_sdmmc_osfree(sdioh_info_t *sd)
diff --git a/drivers/staging/brcm80211/brcmfmac/bcmutils.c b/drivers/staging/brcm80211/brcmfmac/bcmutils.c
deleted file mode 100644
index 8e1296a..0000000
--- a/drivers/staging/brcm80211/brcmfmac/bcmutils.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../util/bcmutils.c"
diff --git a/drivers/staging/brcm80211/brcmfmac/bcmwifi.c b/drivers/staging/brcm80211/brcmfmac/bcmwifi.c
deleted file mode 100644
index 9fe988c..0000000
--- a/drivers/staging/brcm80211/brcmfmac/bcmwifi.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../util/bcmwifi.c"
diff --git a/drivers/staging/brcm80211/brcmfmac/dhd.h b/drivers/staging/brcm80211/brcmfmac/dhd.h
index 60cf782..a726b49 100644
--- a/drivers/staging/brcm80211/brcmfmac/dhd.h
+++ b/drivers/staging/brcm80211/brcmfmac/dhd.h
@@ -31,6 +31,7 @@
#include <linux/random.h>
#include <linux/spinlock.h>
#include <linux/ethtool.h>
+#include <linux/suspend.h>
#include <asm/uaccess.h>
#include <asm/unaligned.h>
/* The kernel threading is sdio-specific */
@@ -122,19 +123,22 @@
} dhd_pub_t;
#if defined(CONFIG_PM_SLEEP)
-
+extern atomic_t dhd_mmc_suspend;
#define DHD_PM_RESUME_WAIT_INIT(a) DECLARE_WAIT_QUEUE_HEAD(a);
-#define _DHD_PM_RESUME_WAIT(a, b) do {\
- int retry = 0; \
- while (dhd_mmc_suspend && retry++ != b) { \
- wait_event_timeout(a, false, HZ/100); \
- } \
- } while (0)
+#define _DHD_PM_RESUME_WAIT(a, b) do { \
+ int retry = 0; \
+ while (atomic_read(&dhd_mmc_suspend) && retry++ != b) { \
+ wait_event_timeout(a, false, HZ/100); \
+ } \
+ } while (0)
#define DHD_PM_RESUME_WAIT(a) _DHD_PM_RESUME_WAIT(a, 30)
#define DHD_PM_RESUME_WAIT_FOREVER(a) _DHD_PM_RESUME_WAIT(a, ~0)
#define DHD_PM_RESUME_RETURN_ERROR(a) \
- do { if (dhd_mmc_suspend) return a; } while (0)
-#define DHD_PM_RESUME_RETURN do { if (dhd_mmc_suspend) return; } while (0)
+ do { if (atomic_read(&dhd_mmc_suspend)) return a; } while (0)
+#define DHD_PM_RESUME_RETURN do { \
+ if (atomic_read(&dhd_mmc_suspend)) \
+ return; \
+ } while (0)
#define DHD_SPINWAIT_SLEEP_INIT(a) DECLARE_WAIT_QUEUE_HEAD(a);
#define SPINWAIT_SLEEP(a, exp, us) do { \
@@ -397,4 +401,14 @@
extern void dhd_wait_for_event(dhd_pub_t *dhd, bool * lockvar);
extern void dhd_wait_event_wakeup(dhd_pub_t *dhd);
+extern u32 g_assert_type;
+
+#ifdef BCMDBG
+#define ASSERT(exp) \
+ do { if (!(exp)) osl_assert(#exp, __FILE__, __LINE__); } while (0)
+extern void osl_assert(char *exp, char *file, int line);
+#else
+#define ASSERT(exp) do {} while (0)
+#endif /* defined(BCMDBG) */
+
#endif /* _dhd_h_ */
diff --git a/drivers/staging/brcm80211/brcmfmac/dhd_cdc.c b/drivers/staging/brcm80211/brcmfmac/dhd_cdc.c
index 39a4d00..ba5a5cb 100644
--- a/drivers/staging/brcm80211/brcmfmac/dhd_cdc.c
+++ b/drivers/staging/brcm80211/brcmfmac/dhd_cdc.c
@@ -111,7 +111,7 @@
/* Respond "bcmerror" and "bcmerrorstr" with local cache */
if (cmd == WLC_GET_VAR && buf) {
if (!strcmp((char *)buf, "bcmerrorstr")) {
- strncpy((char *)buf, bcmerrorstr(dhd->dongle_error),
+ strncpy((char *)buf, "bcm_error",
BCME_STRLEN);
goto done;
} else if (!strcmp((char *)buf, "bcmerror")) {
@@ -253,9 +253,9 @@
"lastcmd=0x%x (%lu)\n",
ioc->cmd, (unsigned long)ioc->cmd, prot->lastcmd,
(unsigned long)prot->lastcmd));
- if ((ioc->cmd == WLC_SET_VAR) || (ioc->cmd == WLC_GET_VAR)) {
+ if ((ioc->cmd == WLC_SET_VAR) || (ioc->cmd == WLC_GET_VAR))
DHD_TRACE(("iovar cmd=%s\n", (char *)buf));
- }
+
goto done;
}
@@ -309,7 +309,7 @@
dhd_prot_iovar_op(dhd_pub_t *dhdp, const char *name,
void *params, int plen, void *arg, int len, bool set)
{
- return BCME_UNSUPPORTED;
+ return -ENOTSUPP;
}
void dhd_prot_dump(dhd_pub_t *dhdp, struct bcmstrbuf *strbuf)
@@ -357,7 +357,7 @@
if (pktbuf->len < BDC_HEADER_LEN) {
DHD_ERROR(("%s: rx data too short (%d < %d)\n", __func__,
pktbuf->len, BDC_HEADER_LEN));
- return BCME_ERROR;
+ return -EBADE;
}
h = (struct bdc_header *)(pktbuf->data);
@@ -366,14 +366,14 @@
if (*ifidx >= DHD_MAX_IFS) {
DHD_ERROR(("%s: rx data ifnum out of range (%d)\n",
__func__, *ifidx));
- return BCME_ERROR;
+ return -EBADE;
}
if (((h->flags & BDC_FLAG_VER_MASK) >> BDC_FLAG_VER_SHIFT) !=
BDC_PROTO_VER) {
DHD_ERROR(("%s: non-BDC packet received, flags 0x%x\n",
dhd_ifname(dhd, *ifidx), h->flags));
- return BCME_ERROR;
+ return -EBADE;
}
if (h->flags & BDC_FLAG_SUM_GOOD) {
@@ -416,7 +416,7 @@
fail:
kfree(cdc);
- return BCME_NOMEM;
+ return -ENOMEM;
}
/* ~NOTE~ What if another thread is waiting on the semaphore? Holding it? */
diff --git a/drivers/staging/brcm80211/brcmfmac/dhd_common.c b/drivers/staging/brcm80211/brcmfmac/dhd_common.c
index aa171f6..0bfb93c 100644
--- a/drivers/staging/brcm80211/brcmfmac/dhd_common.c
+++ b/drivers/staging/brcm80211/brcmfmac/dhd_common.c
@@ -189,7 +189,7 @@
/* Add any bus info */
dhd_bus_dump(dhdp, strbuf);
- return !strbuf->size ? BCME_BUFTOOSHORT : 0;
+ return !strbuf->size ? -EOVERFLOW : 0;
}
static int
@@ -225,7 +225,7 @@
break;
case IOV_GVAL(IOV_BCMERRORSTR):
- strncpy((char *)arg, bcmerrorstr(dhd_pub->bcmerror),
+ strncpy((char *)arg, "bcm_error",
BCME_STRLEN);
((char *)arg)[BCME_STRLEN - 1] = 0x00;
break;
@@ -242,7 +242,7 @@
case IOV_SVAL(IOV_WDTICK):
if (!dhd_pub->up) {
- bcmerror = BCME_NOTUP;
+ bcmerror = -ENOLINK;
break;
}
dhd_os_wd_timer(dhd_pub, (uint) int_val);
@@ -289,7 +289,7 @@
case IOV_SVAL(IOV_IOCTLTIMEOUT):{
if (int_val <= 0)
- bcmerror = BCME_BADARG;
+ bcmerror = -EINVAL;
else
dhd_os_set_ioctl_resp_timeout((unsigned int)
int_val);
@@ -297,7 +297,7 @@
}
default:
- bcmerror = BCME_UNSUPPORTED;
+ bcmerror = -ENOTSUPP;
break;
}
@@ -316,7 +316,7 @@
* exceeding total queue length
*/
if (!pktq_pfull(q, prec) && !pktq_full(q)) {
- pktq_penq(q, prec, pkt);
+ bcm_pktq_penq(q, prec, pkt);
return true;
}
@@ -324,7 +324,7 @@
if (pktq_pfull(q, prec))
eprec = prec;
else if (pktq_full(q)) {
- p = pktq_peek_tail(q, &eprec);
+ p = bcm_pktq_peek_tail(q, &eprec);
ASSERT(p);
if (eprec > prec)
return false;
@@ -338,21 +338,21 @@
if (eprec == prec && !discard_oldest)
return false; /* refuse newer (incoming) packet */
/* Evict packet according to discard policy */
- p = discard_oldest ? pktq_pdeq(q, eprec) : pktq_pdeq_tail(q,
- eprec);
+ p = discard_oldest ? bcm_pktq_pdeq(q, eprec) :
+ bcm_pktq_pdeq_tail(q, eprec);
if (p == NULL) {
- DHD_ERROR(("%s: pktq_penq() failed, oldest %d.",
+ DHD_ERROR(("%s: bcm_pktq_penq() failed, oldest %d.",
__func__, discard_oldest));
ASSERT(p);
}
- pkt_buf_free_skb(p);
+ bcm_pkt_buf_free_skb(p);
}
/* Enqueue */
- p = pktq_penq(q, prec, pkt);
+ p = bcm_pktq_penq(q, prec, pkt);
if (p == NULL) {
- DHD_ERROR(("%s: pktq_penq() failed.", __func__));
+ DHD_ERROR(("%s: bcm_pktq_penq() failed.", __func__));
ASSERT(p);
}
@@ -381,7 +381,7 @@
vi = bcm_iovar_lookup(dhd_iovars, name);
if (vi == NULL) {
- bcmerror = BCME_UNSUPPORTED;
+ bcmerror = -ENOTSUPP;
goto exit;
}
@@ -420,19 +420,19 @@
DHD_TRACE(("%s: Enter\n", __func__));
if (!buf)
- return BCME_BADARG;
+ return -EINVAL;
switch (ioc->cmd) {
case DHD_GET_MAGIC:
if (buflen < sizeof(int))
- bcmerror = BCME_BUFTOOSHORT;
+ bcmerror = -EOVERFLOW;
else
*(int *)buf = DHD_IOCTL_MAGIC;
break;
case DHD_GET_VERSION:
if (buflen < sizeof(int))
- bcmerror = -BCME_BUFTOOSHORT;
+ bcmerror = -EOVERFLOW;
else
*(int *)buf = DHD_IOCTL_VERSION;
break;
@@ -448,7 +448,7 @@
;
if (*arg) {
- bcmerror = BCME_BUFTOOSHORT;
+ bcmerror = -EOVERFLOW;
break;
}
@@ -464,7 +464,7 @@
bcmerror =
dhd_iovar_op(dhd_pub, buf, NULL, 0, arg,
arglen, IOV_SET);
- if (bcmerror != BCME_UNSUPPORTED)
+ if (bcmerror != -ENOTSUPP)
break;
/* not in generic table, try protocol module */
@@ -476,7 +476,7 @@
bcmerror = dhd_prot_iovar_op(dhd_pub, buf,
NULL, 0, arg,
arglen, IOV_SET);
- if (bcmerror != BCME_UNSUPPORTED)
+ if (bcmerror != -ENOTSUPP)
break;
/* if still not found, try bus module */
@@ -493,7 +493,7 @@
}
default:
- bcmerror = BCME_UNSUPPORTED;
+ bcmerror = -ENOTSUPP;
}
return bcmerror;
@@ -586,6 +586,8 @@
}
DHD_EVENT(("EVENT: %s, event ID = %d\n", event_name, event_type));
+ DHD_EVENT(("flags 0x%04x, status %d, reason %d, auth_type %d MAC %s\n",
+ flags, status, reason, auth_type, eabuf));
if (flags & WLC_EVENT_MSG_LINK)
link = true;
@@ -815,14 +817,14 @@
if (memcmp(BRCM_OUI, &pvt_data->bcm_hdr.oui[0], DOT11_OUI_LEN)) {
DHD_ERROR(("%s: mismatched OUI, bailing\n", __func__));
- return BCME_ERROR;
+ return -EBADE;
}
/* BRCM event pkt may be unaligned - use xxx_ua to load user_subtype. */
if (get_unaligned_be16(&pvt_data->bcm_hdr.usr_subtype) !=
BCMILCP_BCM_SUBTYPE_EVENT) {
DHD_ERROR(("%s: mismatched subtype, bailing\n", __func__));
- return BCME_ERROR;
+ return -EBADE;
}
*data_ptr = &pvt_data[1];
@@ -902,7 +904,7 @@
wl_show_host_event(event, event_data);
#endif /* SHOW_EVENTS */
- return BCME_OK;
+ return 0;
}
/* Convert user's input in hex pattern to byte-size mask */
diff --git a/drivers/staging/brcm80211/brcmfmac/dhd_linux.c b/drivers/staging/brcm80211/brcmfmac/dhd_linux.c
index dd03757..f356c56 100644
--- a/drivers/staging/brcm80211/brcmfmac/dhd_linux.c
+++ b/drivers/staging/brcm80211/brcmfmac/dhd_linux.c
@@ -166,7 +166,7 @@
#if defined(CONFIG_PM_SLEEP)
#include <linux/suspend.h>
-volatile bool dhd_mmc_suspend = false;
+atomic_t dhd_mmc_suspend;
DECLARE_WAIT_QUEUE_HEAD(dhd_dpc_wait);
#endif /* defined(CONFIG_PM_SLEEP) */
@@ -325,7 +325,7 @@
uint dhd_radio_up = 1;
/* Network inteface name */
-char iface_name[IFNAMSIZ];
+char iface_name[IFNAMSIZ] = "wlan";
module_param_string(iface_name, iface_name, IFNAMSIZ, 0);
/* The following are specific to the SDIO dongle */
@@ -385,10 +385,6 @@
#define DHD_COMPILED
#endif
-#if defined(CONFIG_WIRELESS_EXT)
-struct iw_statistics *dhd_get_wireless_stats(struct net_device *dev);
-#endif /* defined(CONFIG_WIRELESS_EXT) */
-
static void dhd_dpc(unsigned long data);
/* forward decl */
extern int dhd_wait_pend8021x(struct net_device *dev);
@@ -411,11 +407,11 @@
switch (action) {
case PM_HIBERNATION_PREPARE:
case PM_SUSPEND_PREPARE:
- dhd_mmc_suspend = true;
+ atomic_set(&dhd_mmc_suspend, true);
return NOTIFY_OK;
case PM_POST_HIBERNATION:
case PM_POST_SUSPEND:
- dhd_mmc_suspend = false;
+ atomic_set(&dhd_mmc_suspend, false);
return NOTIFY_OK;
}
return 0;
@@ -1619,51 +1615,6 @@
return 0;
}
-static s16 linuxbcmerrormap[] = { 0, /* 0 */
- -EINVAL, /* BCME_ERROR */
- -EINVAL, /* BCME_BADARG */
- -EINVAL, /* BCME_BADOPTION */
- -EINVAL, /* BCME_NOTUP */
- -EINVAL, /* BCME_NOTDOWN */
- -EINVAL, /* BCME_NOTAP */
- -EINVAL, /* BCME_NOTSTA */
- -EINVAL, /* BCME_BADKEYIDX */
- -EINVAL, /* BCME_RADIOOFF */
- -EINVAL, /* BCME_NOTBANDLOCKED */
- -EINVAL, /* BCME_NOCLK */
- -EINVAL, /* BCME_BADRATESET */
- -EINVAL, /* BCME_BADBAND */
- -E2BIG, /* BCME_BUFTOOSHORT */
- -E2BIG, /* BCME_BUFTOOLONG */
- -EBUSY, /* BCME_BUSY */
- -EINVAL, /* BCME_NOTASSOCIATED */
- -EINVAL, /* BCME_BADSSIDLEN */
- -EINVAL, /* BCME_OUTOFRANGECHAN */
- -EINVAL, /* BCME_BADCHAN */
- -EFAULT, /* BCME_BADADDR */
- -ENOMEM, /* BCME_NORESOURCE */
- -EOPNOTSUPP, /* BCME_UNSUPPORTED */
- -EMSGSIZE, /* BCME_BADLENGTH */
- -EINVAL, /* BCME_NOTREADY */
- -EPERM, /* BCME_NOTPERMITTED */
- -ENOMEM, /* BCME_NOMEM */
- -EINVAL, /* BCME_ASSOCIATED */
- -ERANGE, /* BCME_RANGE */
- -EINVAL, /* BCME_NOTFOUND */
- -EINVAL, /* BCME_WME_NOT_ENABLED */
- -EINVAL, /* BCME_TSPEC_NOTFOUND */
- -EINVAL, /* BCME_ACM_NOTSUPPORTED */
- -EINVAL, /* BCME_NOT_WME_ASSOCIATION */
- -EIO, /* BCME_SDIO_ERROR */
- -ENODEV, /* BCME_DONGLE_DOWN */
- -EINVAL, /* BCME_VERSION */
- -EIO, /* BCME_TXFAIL */
- -EIO, /* BCME_RXFAIL */
- -EINVAL, /* BCME_NODEVICE */
- -EINVAL, /* BCME_NMODE_DISABLED */
- -ENODATA, /* BCME_NONRESIDENT */
-};
-
static int dhd_ioctl_entry(struct net_device *net, struct ifreq *ifr, int cmd)
{
dhd_info_t *dhd = *(dhd_info_t **) netdev_priv(net);
@@ -1699,7 +1650,7 @@
/* Copy the ioc control structure part of ioctl request */
if (copy_from_user(&ioc, ifr->ifr_data, sizeof(wl_ioctl_t))) {
- bcmerror = -BCME_BADADDR;
+ bcmerror = -EINVAL;
goto done;
}
@@ -1715,11 +1666,11 @@
{
buf = kmalloc(buflen, GFP_ATOMIC);
if (!buf) {
- bcmerror = -BCME_NOMEM;
+ bcmerror = -ENOMEM;
goto done;
}
if (copy_from_user(buf, ioc.buf, buflen)) {
- bcmerror = -BCME_BADADDR;
+ bcmerror = -EINVAL;
goto done;
}
}
@@ -1728,12 +1679,12 @@
/* To differentiate between wl and dhd read 4 more byes */
if ((copy_from_user(&driver, (char *)ifr->ifr_data + sizeof(wl_ioctl_t),
sizeof(uint)) != 0)) {
- bcmerror = -BCME_BADADDR;
+ bcmerror = -EINVAL;
goto done;
}
if (!capable(CAP_NET_ADMIN)) {
- bcmerror = -BCME_EPERM;
+ bcmerror = -EPERM;
goto done;
}
@@ -1748,12 +1699,12 @@
/* send to dongle (must be up, and wl) */
if ((dhd->pub.busstate != DHD_BUS_DATA)) {
DHD_ERROR(("%s DONGLE_DOWN,__func__\n", __func__));
- bcmerror = BCME_DONGLE_DOWN;
+ bcmerror = -EIO;
goto done;
}
if (!dhd->pub.iswl) {
- bcmerror = BCME_DONGLE_DOWN;
+ bcmerror = -EIO;
goto done;
}
@@ -1781,10 +1732,8 @@
if (bcmerror > 0)
bcmerror = 0;
- else if (bcmerror < BCME_LAST)
- bcmerror = BCME_ERROR;
- return linuxbcmerrormap[-bcmerror];
+ return bcmerror;
}
static int dhd_stop(struct net_device *net)
@@ -1997,7 +1946,6 @@
strcpy(fw_path, wl_cfg80211_get_fwname());
strcpy(nv_path, wl_cfg80211_get_nvramname());
}
- wl_cfg80211_dbg_level(DBG_CFG80211_GET());
}
/* Set up the watchdog timer */
@@ -2062,7 +2010,9 @@
g_bus = bus;
#endif
#if defined(CONFIG_PM_SLEEP)
- register_pm_notifier(&dhd_sleep_pm_notifier);
+ atomic_set(&dhd_mmc_suspend, false);
+ if (!IS_CFG80211_FAVORITE())
+ register_pm_notifier(&dhd_sleep_pm_notifier);
#endif /* defined(CONFIG_PM_SLEEP) */
/* && defined(DHD_GPL) */
/* Init lock suspend to prevent kernel going to suspend */
@@ -2252,18 +2202,6 @@
net->hard_header_len = ETH_HLEN + dhd->pub.hdrlen;
net->ethtool_ops = &dhd_ethtool_ops;
-#if defined(CONFIG_WIRELESS_EXT)
- if (!IS_CFG80211_FAVORITE()) {
-#if WIRELESS_EXT < 19
- net->get_wireless_stats = dhd_get_wireless_stats;
-#endif /* WIRELESS_EXT < 19 */
-#if WIRELESS_EXT > 12
- net->wireless_handlers =
- (struct iw_handler_def *)&wl_iw_handler_def;
-#endif /* WIRELESS_EXT > 12 */
- }
-#endif /* defined(CONFIG_WIRELESS_EXT) */
-
dhd->pub.rxsz = net->mtu + net->hard_header_len + dhd->pub.hdrlen;
memcpy(net->dev_addr, temp_addr, ETH_ALEN);
@@ -2280,7 +2218,7 @@
fail:
net->netdev_ops = NULL;
- return BCME_ERROR;
+ return -EBADE;
}
void dhd_bus_detach(dhd_pub_t *dhdp)
@@ -2368,7 +2306,8 @@
wl_cfg80211_detach();
#if defined(CONFIG_PM_SLEEP)
- unregister_pm_notifier(&dhd_sleep_pm_notifier);
+ if (!IS_CFG80211_FAVORITE())
+ unregister_pm_notifier(&dhd_sleep_pm_notifier);
#endif /* defined(CONFIG_PM_SLEEP) */
/* && defined(DHD_GPL) */
free_netdev(ifp->net);
@@ -2670,21 +2609,6 @@
dhd_os_sdunlock(pub);
}
-#if defined(CONFIG_WIRELESS_EXT)
-struct iw_statistics *dhd_get_wireless_stats(struct net_device *dev)
-{
- int res = 0;
- dhd_info_t *dhd = *(dhd_info_t **) netdev_priv(dev);
-
- res = wl_iw_get_wireless_stats(dev, &dhd->iw.wstats);
-
- if (res == 0)
- return &dhd->iw.wstats;
- else
- return NULL;
-}
-#endif /* defined(CONFIG_WIRELESS_EXT) */
-
static int
dhd_wl_host_event(dhd_info_t *dhd, int *ifidx, void *pktdata,
wl_event_msg_t *event, void **data)
@@ -2694,7 +2618,7 @@
ASSERT(dhd != NULL);
bcmerror = wl_host_event(dhd, ifidx, pktdata, event, data);
- if (bcmerror != BCME_OK)
+ if (bcmerror != 0)
return bcmerror;
#if defined(CONFIG_WIRELESS_EXT)
@@ -2894,6 +2818,13 @@
return pend;
}
+void wl_os_wd_timer(struct net_device *ndev, uint wdtick)
+{
+ dhd_info_t *dhd = *(dhd_info_t **)netdev_priv(ndev);
+
+ dhd_os_wd_timer(&dhd->pub, wdtick);
+}
+
#ifdef DHD_DEBUG
int write_to_file(dhd_pub_t *dhd, u8 *buf, int size)
{
diff --git a/drivers/staging/brcm80211/brcmfmac/dhd_sdio.c b/drivers/staging/brcm80211/brcmfmac/dhd_sdio.c
index 464f52a..a71c6f8 100644
--- a/drivers/staging/brcm80211/brcmfmac/dhd_sdio.c
+++ b/drivers/staging/brcm80211/brcmfmac/dhd_sdio.c
@@ -15,8 +15,11 @@
*/
#include <linux/types.h>
-#include <bcmdefs.h>
+#include <linux/kernel.h>
+#include <linux/printk.h>
+#include <linux/pci_ids.h>
#include <linux/netdevice.h>
+#include <bcmdefs.h>
#include <bcmsdh.h>
#ifdef BCMEMBEDIMAGE
@@ -27,8 +30,6 @@
#include <bcmutils.h>
#include <bcmdevs.h>
-#include <siutils.h>
-#include <hndpmu.h>
#include <hndsoc.h>
#ifdef DHD_DEBUG
#include <hndrte_armtrap.h>
@@ -51,7 +52,7 @@
#include <dhd_dbg.h>
#include <dhdioctl.h>
#include <sdiovar.h>
-#include <siutils_priv.h>
+#include <bcmchip.h>
#ifndef DHDSDIO_MEM_DUMP_FNAME
#define DHDSDIO_MEM_DUMP_FNAME "mem_dump"
@@ -136,12 +137,6 @@
/* Flags for SDH calls */
#define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
-/* Packet free applicable unconditionally for sdio and sdspi. Conditional if
- * bufpool was present for gspi bus.
- */
-#define PKTFREE2() if ((bus->bus != SPI_BUS) || bus->usebufpool) \
- pkt_buf_free_skb(pkt);
-
/*
* Conversion of 802.1D priority to precedence level
*/
@@ -165,12 +160,28 @@
} dhd_console_t;
#endif /* DHD_DEBUG */
+/* misc chip info needed by some of the routines */
+struct chip_info {
+ u32 chip;
+ u32 chiprev;
+ u32 cccorebase;
+ u32 ccrev;
+ u32 cccaps;
+ u32 buscorebase;
+ u32 buscorerev;
+ u32 buscoretype;
+ u32 ramcorebase;
+ u32 armcorebase;
+ u32 pmurev;
+ u32 ramsize;
+};
+
/* Private data for SDIO bus interaction */
typedef struct dhd_bus {
dhd_pub_t *dhd;
bcmsdh_info_t *sdh; /* Handle for BCMSDH calls */
- si_t *sih; /* Handle for SI calls */
+ struct chip_info *ci; /* Chip info struct */
char *vars; /* Variables (from CIS and/or other) */
uint varsz; /* Size of variables buffer */
u32 sbaddr; /* Current SB window pointer (-1, invalid) */
@@ -421,8 +432,6 @@
#define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE)
-#define GSPI_PR55150_BAILOUT
-
#ifdef SDTEST
static void dhdsdio_testrcv(dhd_bus_t *bus, void *pkt, uint seq);
static void dhdsdio_sdtest_set(dhd_bus_t *bus, bool start);
@@ -447,10 +456,6 @@
static uint process_nvram_vars(char *varbuf, uint len);
static void dhd_dongle_setmemsize(struct dhd_bus *bus, int mem_size);
-static int dhd_bcmsdh_recv_buf(dhd_bus_t *bus, u32 addr, uint fn,
- uint flags, u8 *buf, uint nbytes,
- struct sk_buff *pkt, bcmsdh_cmplt_fn_t complete,
- void *handle);
static int dhd_bcmsdh_send_buf(dhd_bus_t *bus, u32 addr, uint fn,
uint flags, u8 *buf, uint nbytes,
struct sk_buff *pkt, bcmsdh_cmplt_fn_t complete,
@@ -464,6 +469,23 @@
#ifdef BCMEMBEDIMAGE
static int dhdsdio_download_code_array(struct dhd_bus *bus);
#endif
+static void dhdsdio_chip_disablecore(bcmsdh_info_t *sdh, u32 corebase);
+static int dhdsdio_chip_attach(struct dhd_bus *bus, void *regs);
+static void dhdsdio_chip_resetcore(bcmsdh_info_t *sdh, u32 corebase);
+static void dhdsdio_sdiod_drive_strength_init(struct dhd_bus *bus,
+ u32 drivestrength);
+static void dhdsdio_chip_detach(struct dhd_bus *bus);
+
+/* Packet free applicable unconditionally for sdio and sdspi.
+ * Conditional if bufpool was present for gspi bus.
+ */
+static void dhdsdio_pktfree2(dhd_bus_t *bus, struct sk_buff *pkt)
+{
+ dhd_os_sdlock_rxq(bus->dhd);
+ if ((bus->bus != SPI_BUS) || bus->usebufpool)
+ bcm_pkt_buf_free_skb(pkt);
+ dhd_os_sdunlock_rxq(bus->dhd);
+}
static void dhd_dongle_setmemsize(struct dhd_bus *bus, int mem_size)
{
@@ -511,8 +533,8 @@
clkreq =
bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
- if ((bus->sih->chip == BCM4329_CHIP_ID)
- && (bus->sih->chiprev == 0))
+ if ((bus->ci->chip == BCM4329_CHIP_ID)
+ && (bus->ci->chiprev == 0))
clkreq |= SBSDIO_FORCE_ALP;
bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
@@ -520,11 +542,11 @@
if (err) {
DHD_ERROR(("%s: HT Avail request error: %d\n",
__func__, err));
- return BCME_ERROR;
+ return -EBADE;
}
- if (pendok && ((bus->sih->buscoretype == PCMCIA_CORE_ID)
- && (bus->sih->buscorerev == 9))) {
+ if (pendok && ((bus->ci->buscoretype == PCMCIA_CORE_ID)
+ && (bus->ci->buscorerev == 9))) {
u32 dummy, retries;
R_SDREG(dummy, &bus->regs->clockctlstatus, retries);
}
@@ -536,7 +558,7 @@
if (err) {
DHD_ERROR(("%s: HT Avail read error: %d\n",
__func__, err));
- return BCME_ERROR;
+ return -EBADE;
}
/* Go to pending and await interrupt if appropriate */
@@ -548,7 +570,7 @@
if (err) {
DHD_ERROR(("%s: Devctl error setting CA: %d\n",
__func__, err));
- return BCME_ERROR;
+ return -EBADE;
}
devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
@@ -557,7 +579,7 @@
DHD_INFO(("CLKCTL: set PENDING\n"));
bus->clkstate = CLK_PENDING;
- return BCME_OK;
+ return 0;
} else if (bus->clkstate == CLK_PENDING) {
/* Cancel CA-only interrupt filter */
devctl =
@@ -581,12 +603,12 @@
if (err) {
DHD_ERROR(("%s: HT Avail request error: %d\n",
__func__, err));
- return BCME_ERROR;
+ return -EBADE;
}
if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
DHD_ERROR(("%s: HT Avail timeout (%d): clkctl 0x%02x\n",
__func__, PMU_MAX_TRANSITION_DLY, clkctl));
- return BCME_ERROR;
+ return -EBADE;
}
/* Mark clock available */
@@ -630,10 +652,10 @@
if (err) {
DHD_ERROR(("%s: Failed access turning clock off: %d\n",
__func__, err));
- return BCME_ERROR;
+ return -EBADE;
}
}
- return BCME_OK;
+ return 0;
}
/* Change idle/active SD state */
@@ -653,7 +675,7 @@
if (err) {
DHD_ERROR(("%s: error enabling sd_clock: %d\n",
__func__, err));
- return BCME_ERROR;
+ return -EBADE;
}
iovalue = bus->sd_mode;
@@ -662,7 +684,7 @@
if (err) {
DHD_ERROR(("%s: error changing sd_mode: %d\n",
__func__, err));
- return BCME_ERROR;
+ return -EBADE;
}
} else if (bus->idleclock != DHD_IDLE_ACTIVE) {
/* Restore clock speed */
@@ -672,7 +694,7 @@
if (err) {
DHD_ERROR(("%s: error restoring sd_divisor: %d\n",
__func__, err));
- return BCME_ERROR;
+ return -EBADE;
}
}
bus->clkstate = CLK_SDONLY;
@@ -681,7 +703,7 @@
if ((bus->sd_divisor == -1) || (bus->sd_mode == -1)) {
DHD_TRACE(("%s: can't idle clock, divisor %d mode %d\n",
__func__, bus->sd_divisor, bus->sd_mode));
- return BCME_ERROR;
+ return -EBADE;
}
if (bus->idleclock == DHD_IDLE_STOP) {
if (sd1idle) {
@@ -694,7 +716,7 @@
if (err) {
DHD_ERROR(("%s: error changing sd_clock: %d\n",
__func__, err));
- return BCME_ERROR;
+ return -EBADE;
}
}
@@ -704,7 +726,7 @@
if (err) {
DHD_ERROR(("%s: error disabling sd_clock: %d\n",
__func__, err));
- return BCME_ERROR;
+ return -EBADE;
}
} else if (bus->idleclock != DHD_IDLE_ACTIVE) {
/* Set divisor to idle value */
@@ -714,13 +736,13 @@
if (err) {
DHD_ERROR(("%s: error changing sd_divisor: %d\n",
__func__, err));
- return BCME_ERROR;
+ return -EBADE;
}
}
bus->clkstate = CLK_NONE;
}
- return BCME_OK;
+ return 0;
}
/* Transition SD and backplane clock readiness */
@@ -738,7 +760,7 @@
dhd_os_wd_timer(bus->dhd, dhd_watchdog_ms);
bus->activity = true;
}
- return BCME_OK;
+ return 0;
}
switch (target) {
@@ -777,7 +799,7 @@
DHD_INFO(("dhdsdio_clkctl: %d -> %d\n", oldstate, bus->clkstate));
#endif /* DHD_DEBUG */
- return BCME_OK;
+ return 0;
}
int dhdsdio_bussleep(dhd_bus_t *bus, bool sleep)
@@ -792,13 +814,13 @@
/* Done if we're already in the requested state */
if (sleep == bus->sleeping)
- return BCME_OK;
+ return 0;
/* Going to sleep: set the alarm and turn off the lights... */
if (sleep) {
/* Don't sleep if something is pending */
if (bus->dpc_sched || bus->rxskip || pktq_len(&bus->txq))
- return BCME_BUSY;
+ return -EBUSY;
/* Disable SDIO interrupts (no longer interested) */
bcmsdh_intr_disable(bus->sdh);
@@ -818,8 +840,8 @@
SBSDIO_FORCE_HW_CLKREQ_OFF, NULL);
/* Isolate the bus */
- if (bus->sih->chip != BCM4329_CHIP_ID
- && bus->sih->chip != BCM4319_CHIP_ID) {
+ if (bus->ci->chip != BCM4329_CHIP_ID
+ && bus->ci->chip != BCM4319_CHIP_ID) {
bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL,
SBSDIO_DEVCTL_PADS_ISO, NULL);
}
@@ -835,8 +857,8 @@
/* Force pad isolation off if possible
(in case power never toggled) */
- if ((bus->sih->buscoretype == PCMCIA_CORE_ID)
- && (bus->sih->buscorerev >= 10))
+ if ((bus->ci->buscoretype == PCMCIA_CORE_ID)
+ && (bus->ci->buscorerev >= 10))
bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_DEVICE_CTL, 0,
NULL);
@@ -864,7 +886,7 @@
}
}
- return BCME_OK;
+ return 0;
}
#if defined(OOB_INTR_ONLY)
@@ -922,7 +944,7 @@
sdh = bus->sdh;
if (bus->dhd->dongle_reset) {
- ret = BCME_NOTREADY;
+ ret = -EPERM;
goto done;
}
@@ -935,19 +957,19 @@
DHD_INFO(("%s: insufficient headroom %d for %d pad\n",
__func__, skb_headroom(pkt), pad));
bus->dhd->tx_realloc++;
- new = pkt_buf_get_skb(pkt->len + DHD_SDALIGN);
+ new = bcm_pkt_buf_get_skb(pkt->len + DHD_SDALIGN);
if (!new) {
DHD_ERROR(("%s: couldn't allocate new %d-byte "
"packet\n",
__func__, pkt->len + DHD_SDALIGN));
- ret = BCME_NOMEM;
+ ret = -ENOMEM;
goto done;
}
PKTALIGN(new, pkt->len, DHD_SDALIGN);
memcpy(new->data, pkt->data, pkt->len);
if (free_pkt)
- pkt_buf_free_skb(pkt);
+ bcm_pkt_buf_free_skb(pkt);
/* free the pkt if canned one is not used */
free_pkt = true;
pkt = new;
@@ -983,9 +1005,12 @@
if (DHD_BYTES_ON() &&
(((DHD_CTL_ON() && (chan == SDPCM_CONTROL_CHANNEL)) ||
(DHD_DATA_ON() && (chan != SDPCM_CONTROL_CHANNEL))))) {
- prhex("Tx Frame", frame, len);
+ printk(KERN_DEBUG "Tx Frame:\n");
+ print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, frame, len);
} else if (DHD_HDRS_ON()) {
- prhex("TxHdr", frame, min_t(u16, len, 16));
+ printk(KERN_DEBUG "TxHdr:\n");
+ print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
+ frame, min_t(u16, len, 16));
}
#endif
@@ -1019,7 +1044,7 @@
dhd_bcmsdh_send_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
F2SYNC, frame, len, pkt, NULL, NULL);
bus->f2txdata++;
- ASSERT(ret != BCME_PENDING);
+ ASSERT(ret != -BCME_PENDING);
if (ret < 0) {
/* On failure, abort the command
@@ -1061,14 +1086,14 @@
dhd_os_sdlock(bus->dhd);
if (free_pkt)
- pkt_buf_free_skb(pkt);
+ bcm_pkt_buf_free_skb(pkt);
return ret;
}
int dhd_bus_txdata(struct dhd_bus *bus, struct sk_buff *pkt)
{
- int ret = BCME_ERROR;
+ int ret = -EBADE;
uint datalen, prec;
DHD_TRACE(("%s: Enter\n", __func__));
@@ -1110,11 +1135,11 @@
if (dhd_prec_enq(bus->dhd, &bus->txq, pkt, prec) == false) {
skb_pull(pkt, SDPCM_HDRLEN);
dhd_txcomplete(bus->dhd, pkt, false);
- pkt_buf_free_skb(pkt);
+ bcm_pkt_buf_free_skb(pkt);
DHD_ERROR(("%s: out of bus->txq !!!\n", __func__));
- ret = BCME_NORESOURCE;
+ ret = -ENOSR;
} else {
- ret = BCME_OK;
+ ret = 0;
}
dhd_os_sdunlock_txq(bus->dhd);
@@ -1183,7 +1208,7 @@
/* Send frames until the limit or some other event */
for (cnt = 0; (cnt < maxframes) && DATAOK(bus); cnt++) {
dhd_os_sdlock_txq(bus->dhd);
- pkt = pktq_mdeq(&bus->txq, tx_prec_map, &prec_out);
+ pkt = bcm_pktq_mdeq(&bus->txq, tx_prec_map, &prec_out);
if (pkt == NULL) {
dhd_os_sdunlock_txq(bus->dhd);
break;
@@ -1313,10 +1338,15 @@
if (ret == -1) {
#ifdef DHD_DEBUG
- if (DHD_BYTES_ON() && DHD_CTL_ON())
- prhex("Tx Frame", frame, len);
- else if (DHD_HDRS_ON())
- prhex("TxHdr", frame, min_t(u16, len, 16));
+ if (DHD_BYTES_ON() && DHD_CTL_ON()) {
+ printk(KERN_DEBUG "Tx Frame:\n");
+ print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
+ frame, len);
+ } else if (DHD_HDRS_ON()) {
+ printk(KERN_DEBUG "TxHdr:\n");
+ print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
+ frame, min_t(u16, len, 16));
+ }
#endif
do {
@@ -1326,7 +1356,7 @@
SDIO_FUNC_2, F2SYNC, frame, len,
NULL, NULL, NULL);
- ASSERT(ret != BCME_PENDING);
+ ASSERT(ret != -BCME_PENDING);
if (ret < 0) {
/* On failure, abort the command and
@@ -1669,7 +1699,7 @@
memcpy(&pktgen, arg, sizeof(pktgen));
if (pktgen.version != DHD_PKTGEN_VERSION)
- return BCME_BADARG;
+ return -EINVAL;
oldcnt = bus->pktgen_count;
oldmode = bus->pktgen_mode;
@@ -1778,7 +1808,7 @@
if (addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff)) {
DHD_ERROR(("%s: address (0x%08x) of sdpcm_shared invalid\n",
__func__, addr));
- return BCME_ERROR;
+ return -EBADE;
}
/* Read hndrte_shared structure */
@@ -1801,10 +1831,10 @@
"is different than sdpcm_shared version %d in dongle\n",
__func__, SDPCM_SHARED_VERSION,
sh->flags & SDPCM_SHARED_VERSION_MASK));
- return BCME_ERROR;
+ return -EBADE;
}
- return BCME_OK;
+ return 0;
}
static int dhdsdio_checkdied(dhd_bus_t *bus, u8 *data, uint size)
@@ -1830,7 +1860,7 @@
if (mbuffer == NULL) {
DHD_ERROR(("%s: kmalloc(%d) failed\n", __func__,
msize));
- bcmerror = BCME_NOMEM;
+ bcmerror = -ENOMEM;
goto done;
}
}
@@ -1838,7 +1868,7 @@
str = kmalloc(maxstrlen, GFP_ATOMIC);
if (str == NULL) {
DHD_ERROR(("%s: kmalloc(%d) failed\n", __func__, maxstrlen));
- bcmerror = BCME_NOMEM;
+ bcmerror = -ENOMEM;
goto done;
}
@@ -2007,19 +2037,19 @@
c->bufsize = le32_to_cpu(c->log.buf_size);
c->buf = kmalloc(c->bufsize, GFP_ATOMIC);
if (c->buf == NULL)
- return BCME_NOMEM;
+ return -ENOMEM;
}
idx = le32_to_cpu(c->log.idx);
/* Protect against corrupt value */
if (idx > c->bufsize)
- return BCME_ERROR;
+ return -EBADE;
/* Skip reading the console buffer if the index pointer
has not moved */
if (idx == c->last)
- return BCME_OK;
+ return 0;
/* Read the console buffer */
addr = le32_to_cpu(c->log.buf);
@@ -2057,23 +2087,23 @@
}
break2:
- return BCME_OK;
+ return 0;
}
#endif /* DHD_DEBUG */
int dhdsdio_downloadvars(dhd_bus_t *bus, void *arg, int len)
{
- int bcmerror = BCME_OK;
+ int bcmerror = 0;
DHD_TRACE(("%s: Enter\n", __func__));
/* Basic sanity checks */
if (bus->dhd->up) {
- bcmerror = BCME_NOTDOWN;
+ bcmerror = -EISCONN;
goto err;
}
if (!len) {
- bcmerror = BCME_BUFTOOSHORT;
+ bcmerror = -EOVERFLOW;
goto err;
}
@@ -2083,7 +2113,7 @@
bus->vars = kmalloc(len, GFP_ATOMIC);
bus->varsz = bus->vars ? len : 0;
if (bus->vars == NULL) {
- bcmerror = BCME_NOMEM;
+ bcmerror = -ENOMEM;
goto err;
}
@@ -2122,7 +2152,7 @@
/* Check if dongle is in reset. If so, only allow DEVRESET iovars */
if (bus->dhd->dongle_reset && !(actionid == IOV_SVAL(IOV_DEVRESET) ||
actionid == IOV_GVAL(IOV_DEVRESET))) {
- bcmerror = BCME_NOTREADY;
+ bcmerror = -EPERM;
goto exit;
}
@@ -2182,7 +2212,7 @@
case IOV_SVAL(IOV_IDLETIME):
if ((int_val < 0) && (int_val != DHD_IDLE_IMMEDIATE))
- bcmerror = BCME_BADARG;
+ bcmerror = -EINVAL;
else
bus->idletime = int_val;
break;
@@ -2228,7 +2258,7 @@
"0x%08x size %d dsize %d\n",
__func__, (set ? "set" : "get"),
address, size, dsize));
- bcmerror = BCME_BADARG;
+ bcmerror = -EINVAL;
break;
}
@@ -2243,7 +2273,7 @@
DHD_ERROR(("%s: ramsize 0x%08x doesn't have %d "
"bytes at 0x%08x\n",
__func__, bus->orig_ramsize, size, address));
- bcmerror = BCME_BADARG;
+ bcmerror = -EINVAL;
break;
}
@@ -2271,7 +2301,7 @@
case IOV_SVAL(IOV_SDIOD_DRIVE):
dhd_sdiod_drive_strength = int_val;
- si_sdiod_drive_strength_init(bus->sih,
+ dhdsdio_sdiod_drive_strength_init(bus,
dhd_sdiod_drive_strength);
break;
@@ -2301,7 +2331,7 @@
case IOV_SVAL(IOV_SDRXCHAIN):
if (bool_val && !bus->sd_rxchain)
- bcmerror = BCME_UNSUPPORTED;
+ bcmerror = -ENOTSUPP;
else
bus->use_rxchain = bool_val;
break;
@@ -2324,7 +2354,7 @@
if (bus->varsz < (uint) len)
memcpy(arg, bus->vars, bus->varsz);
else
- bcmerror = BCME_BUFTOOSHORT;
+ bcmerror = -EOVERFLOW;
break;
#endif /* DHD_DEBUG */
@@ -2340,7 +2370,7 @@
size = sd_ptr->func;
int_val = (s32) bcmsdh_reg_read(bus->sdh, addr, size);
if (bcmsdh_regfail(bus->sdh))
- bcmerror = BCME_SDIO_ERROR;
+ bcmerror = -EIO;
memcpy(arg, &int_val, sizeof(s32));
break;
}
@@ -2356,7 +2386,7 @@
size = sd_ptr->func;
bcmsdh_reg_write(bus->sdh, addr, size, sd_ptr->value);
if (bcmsdh_regfail(bus->sdh))
- bcmerror = BCME_SDIO_ERROR;
+ bcmerror = -EIO;
break;
}
@@ -2373,7 +2403,7 @@
size = sdreg.func;
int_val = (s32) bcmsdh_reg_read(bus->sdh, addr, size);
if (bcmsdh_regfail(bus->sdh))
- bcmerror = BCME_SDIO_ERROR;
+ bcmerror = -EIO;
memcpy(arg, &int_val, sizeof(s32));
break;
}
@@ -2389,7 +2419,7 @@
size = sdreg.func;
bcmsdh_reg_write(bus->sdh, addr, size, sdreg.value);
if (bcmsdh_regfail(bus->sdh))
- bcmerror = BCME_SDIO_ERROR;
+ bcmerror = -EIO;
break;
}
@@ -2488,7 +2518,7 @@
break;
default:
- bcmerror = BCME_UNSUPPORTED;
+ bcmerror = -ENOTSUPP;
break;
}
@@ -2525,7 +2555,7 @@
if (bus->vars) {
vbuffer = kzalloc(varsize, GFP_ATOMIC);
if (!vbuffer)
- return BCME_NOMEM;
+ return -ENOMEM;
memcpy(vbuffer, bus->vars, bus->varsz);
@@ -2537,7 +2567,7 @@
DHD_INFO(("Compare NVRAM dl & ul; varsize=%d\n", varsize));
nvram_ularray = kmalloc(varsize, GFP_ATOMIC);
if (!nvram_ularray)
- return BCME_NOMEM;
+ return -ENOMEM;
/* Upload image to verify downloaded contents. */
memset(nvram_ularray, 0xaa, varsize);
@@ -2596,42 +2626,18 @@
static int dhdsdio_download_state(dhd_bus_t *bus, bool enter)
{
uint retries;
+ u32 regdata;
int bcmerror = 0;
/* To enter download state, disable ARM and reset SOCRAM.
* To exit download state, simply reset ARM (default is RAM boot).
*/
if (enter) {
-
bus->alp_only = true;
- if (!(si_setcore(bus->sih, ARM7S_CORE_ID, 0)) &&
- !(si_setcore(bus->sih, ARMCM3_CORE_ID, 0))) {
- DHD_ERROR(("%s: Failed to find ARM core!\n", __func__));
- bcmerror = BCME_ERROR;
- goto fail;
- }
+ dhdsdio_chip_disablecore(bus->sdh, bus->ci->armcorebase);
- si_core_disable(bus->sih, 0);
- if (bcmsdh_regfail(bus->sdh)) {
- bcmerror = BCME_SDIO_ERROR;
- goto fail;
- }
-
- if (!(si_setcore(bus->sih, SOCRAM_CORE_ID, 0))) {
- DHD_ERROR(("%s: Failed to find SOCRAM core!\n",
- __func__));
- bcmerror = BCME_ERROR;
- goto fail;
- }
-
- si_core_reset(bus->sih, 0, 0);
- if (bcmsdh_regfail(bus->sdh)) {
- DHD_ERROR(("%s: Failure trying reset SOCRAM core?\n",
- __func__));
- bcmerror = BCME_SDIO_ERROR;
- goto fail;
- }
+ dhdsdio_chip_resetcore(bus->sdh, bus->ci->ramcorebase);
/* Clear the top bit of memory */
if (bus->ramsize) {
@@ -2640,17 +2646,14 @@
(u8 *)&zeros, 4);
}
} else {
- if (!(si_setcore(bus->sih, SOCRAM_CORE_ID, 0))) {
- DHD_ERROR(("%s: Failed to find SOCRAM core!\n",
- __func__));
- bcmerror = BCME_ERROR;
- goto fail;
- }
-
- if (!si_iscoreup(bus->sih)) {
+ regdata = bcmsdh_reg_read(bus->sdh,
+ CORE_SB(bus->ci->ramcorebase, sbtmstatelow), 4);
+ regdata &= (SBTML_RESET | SBTML_REJ_MASK |
+ (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
+ if ((SICF_CLOCK_EN << SBTML_SICF_SHIFT) != regdata) {
DHD_ERROR(("%s: SOCRAM core is down after reset?\n",
__func__));
- bcmerror = BCME_ERROR;
+ bcmerror = -EBADE;
goto fail;
}
@@ -2660,41 +2663,16 @@
bcmerror = 0;
}
- if (!si_setcore(bus->sih, PCMCIA_CORE_ID, 0) &&
- !si_setcore(bus->sih, SDIOD_CORE_ID, 0)) {
- DHD_ERROR(("%s: Can't change back to SDIO core?\n",
- __func__));
- bcmerror = BCME_ERROR;
- goto fail;
- }
W_SDREG(0xFFFFFFFF, &bus->regs->intstatus, retries);
- if (!(si_setcore(bus->sih, ARM7S_CORE_ID, 0)) &&
- !(si_setcore(bus->sih, ARMCM3_CORE_ID, 0))) {
- DHD_ERROR(("%s: Failed to find ARM core!\n", __func__));
- bcmerror = BCME_ERROR;
- goto fail;
- }
-
- si_core_reset(bus->sih, 0, 0);
- if (bcmsdh_regfail(bus->sdh)) {
- DHD_ERROR(("%s: Failure trying to reset ARM core?\n",
- __func__));
- bcmerror = BCME_SDIO_ERROR;
- goto fail;
- }
+ dhdsdio_chip_resetcore(bus->sdh, bus->ci->armcorebase);
/* Allow HT Clock now that the ARM is running. */
bus->alp_only = false;
bus->dhd->busstate = DHD_BUS_LOAD;
}
-
fail:
- /* Always return to SDIOD core */
- if (!si_setcore(bus->sih, PCMCIA_CORE_ID, 0))
- si_setcore(bus->sih, SDIOD_CORE_ID, 0);
-
return bcmerror;
}
@@ -2739,7 +2717,7 @@
if (set && strcmp(name, "sd_divisor") == 0) {
if (bcmsdh_iovar_op(bus->sdh, "sd_divisor", NULL, 0,
&bus->sd_divisor, sizeof(s32),
- false) != BCME_OK) {
+ false) != 0) {
bus->sd_divisor = -1;
DHD_ERROR(("%s: fail on %s get\n", __func__,
name));
@@ -2752,7 +2730,7 @@
if (set && strcmp(name, "sd_mode") == 0) {
if (bcmsdh_iovar_op(bus->sdh, "sd_mode", NULL, 0,
&bus->sd_mode, sizeof(s32),
- false) != BCME_OK) {
+ false) != 0) {
bus->sd_mode = -1;
DHD_ERROR(("%s: fail on %s get\n", __func__,
name));
@@ -2767,7 +2745,7 @@
if (bcmsdh_iovar_op
(bus->sdh, "sd_blocksize", &fnum, sizeof(s32),
&bus->blocksize, sizeof(s32),
- false) != BCME_OK) {
+ false) != 0) {
bus->blocksize = 0;
DHD_ERROR(("%s: fail on %s get\n", __func__,
"sd_blocksize"));
@@ -2867,14 +2845,14 @@
dhdsdio_clkctl(bus, CLK_SDONLY, false);
/* Clear the data packet queues */
- pktq_flush(&bus->txq, true);
+ bcm_pktq_flush(&bus->txq, true, NULL, NULL);
/* Clear any held glomming stuff */
if (bus->glomd)
- pkt_buf_free_skb(bus->glomd);
+ bcm_pkt_buf_free_skb(bus->glomd);
if (bus->glom)
- pkt_buf_free_skb(bus->glom);
+ bcm_pkt_buf_free_skb(bus->glom);
bus->glom = bus->glomd = NULL;
@@ -2948,14 +2926,11 @@
/* If F2 successfully enabled, set core and enable interrupts */
if (ready == enable) {
- /* Make sure we're talking to the core. */
- bus->regs = si_setcore(bus->sih, PCMCIA_CORE_ID, 0);
- if (!(bus->regs))
- bus->regs = si_setcore(bus->sih, SDIOD_CORE_ID, 0);
-
/* Set up the interrupt mask and enable interrupts */
bus->hostintmask = HOSTINTMASK;
- W_SDREG(bus->hostintmask, &bus->regs->hostintmask, retries);
+ W_SDREG(bus->hostintmask,
+ (unsigned int *)CORE_BUS_REG(bus->ci->buscorebase,
+ hostintmask), retries);
bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_WATERMARK,
(u8) watermark, &err);
@@ -3134,12 +3109,11 @@
}
/* Read remainder of frame body into the rxctl buffer */
- sdret =
- dhd_bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2, F2SYNC,
- (bus->rxctl + firstread), rdlen, NULL, NULL,
- NULL);
+ sdret = bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
+ F2SYNC, (bus->rxctl + firstread), rdlen,
+ NULL, NULL, NULL);
bus->f2rxdata++;
- ASSERT(sdret != BCME_PENDING);
+ ASSERT(sdret != -BCME_PENDING);
/* Control frame failures need retransmission */
if (sdret < 0) {
@@ -3153,8 +3127,10 @@
gotpkt:
#ifdef DHD_DEBUG
- if (DHD_BYTES_ON() && DHD_CTL_ON())
- prhex("RxCtrl", bus->rxctl, len);
+ if (DHD_BYTES_ON() && DHD_CTL_ON()) {
+ printk(KERN_DEBUG "RxCtrl:\n");
+ print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, bus->rxctl, len);
+ }
#endif
/* Point to valid data and indicate its length */
@@ -3228,10 +3204,11 @@
}
/* Allocate/chain packet for next subframe */
- pnext = pkt_buf_get_skb(sublen + DHD_SDALIGN);
+ pnext = bcm_pkt_buf_get_skb(sublen + DHD_SDALIGN);
if (pnext == NULL) {
- DHD_ERROR(("%s: pkt_buf_get_skb failed, num %d len %d\n",
- __func__, num, sublen));
+ DHD_ERROR(("%s: bcm_pkt_buf_get_skb failed, "
+ "num %d len %d\n", __func__,
+ num, sublen));
break;
}
ASSERT(!(pnext->prev));
@@ -3264,13 +3241,13 @@
pfirst = pnext = NULL;
} else {
if (pfirst)
- pkt_buf_free_skb(pfirst);
+ bcm_pkt_buf_free_skb(pfirst);
bus->glom = NULL;
num = 0;
}
/* Done with descriptor packet */
- pkt_buf_free_skb(bus->glomd);
+ bcm_pkt_buf_free_skb(bus->glomd);
bus->glomd = NULL;
bus->nextlen = 0;
@@ -3291,27 +3268,23 @@
}
pfirst = bus->glom;
- dlen = (u16) pkttotlen(pfirst);
+ dlen = (u16) bcm_pkttotlen(pfirst);
/* Do an SDIO read for the superframe. Configurable iovar to
* read directly into the chained packet, or allocate a large
* packet and and copy into the chain.
*/
if (usechain) {
- errcode = dhd_bcmsdh_recv_buf(bus,
- bcmsdh_cur_sbwad
- (bus->sdh), SDIO_FUNC_2,
- F2SYNC,
- (u8 *) pfirst->data,
- dlen, pfirst, NULL, NULL);
+ errcode = bcmsdh_recv_buf(bus,
+ bcmsdh_cur_sbwad(bus->sdh), SDIO_FUNC_2,
+ F2SYNC, (u8 *) pfirst->data, dlen,
+ pfirst, NULL, NULL);
} else if (bus->dataptr) {
- errcode = dhd_bcmsdh_recv_buf(bus,
- bcmsdh_cur_sbwad
- (bus->sdh), SDIO_FUNC_2,
- F2SYNC, bus->dataptr,
- dlen, NULL, NULL, NULL);
- sublen =
- (u16) pktfrombuf(pfirst, 0, dlen,
+ errcode = bcmsdh_recv_buf(bus,
+ bcmsdh_cur_sbwad(bus->sdh), SDIO_FUNC_2,
+ F2SYNC, bus->dataptr, dlen,
+ NULL, NULL, NULL);
+ sublen = (u16) bcm_pktfrombuf(pfirst, 0, dlen,
bus->dataptr);
if (sublen != dlen) {
DHD_ERROR(("%s: FAILED TO COPY, dlen %d sublen %d\n",
@@ -3325,7 +3298,7 @@
errcode = -1;
}
bus->f2rxdata++;
- ASSERT(errcode != BCME_PENDING);
+ ASSERT(errcode != -BCME_PENDING);
/* On failure, kill the superframe, allow a couple retries */
if (errcode < 0) {
@@ -3339,7 +3312,7 @@
bus->glomerr = 0;
dhdsdio_rxfail(bus, true, false);
dhd_os_sdlock_rxq(bus->dhd);
- pkt_buf_free_skb(bus->glom);
+ bcm_pkt_buf_free_skb(bus->glom);
dhd_os_sdunlock_rxq(bus->dhd);
bus->rxglomfail++;
bus->glom = NULL;
@@ -3348,8 +3321,9 @@
}
#ifdef DHD_DEBUG
if (DHD_GLOM_ON()) {
- prhex("SUPERFRAME", pfirst->data,
- min_t(int, pfirst->len, 48));
+ printk(KERN_DEBUG "SUPERFRAME:\n");
+ print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
+ pfirst->data, min_t(int, pfirst->len, 48));
}
#endif
@@ -3430,8 +3404,11 @@
chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
#ifdef DHD_DEBUG
- if (DHD_GLOM_ON())
- prhex("subframe", dptr, 32);
+ if (DHD_GLOM_ON()) {
+ printk(KERN_DEBUG "subframe:\n");
+ print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
+ dptr, 32);
+ }
#endif
if ((u16)~(sublen ^ check)) {
@@ -3468,7 +3445,7 @@
bus->glomerr = 0;
dhdsdio_rxfail(bus, true, false);
dhd_os_sdlock_rxq(bus->dhd);
- pkt_buf_free_skb(bus->glom);
+ bcm_pkt_buf_free_skb(bus->glom);
dhd_os_sdunlock_rxq(bus->dhd);
bus->rxglomfail++;
bus->glom = NULL;
@@ -3508,15 +3485,18 @@
rxseq = seq;
}
#ifdef DHD_DEBUG
- if (DHD_BYTES_ON() && DHD_DATA_ON())
- prhex("Rx Subframe Data", dptr, dlen);
+ if (DHD_BYTES_ON() && DHD_DATA_ON()) {
+ printk(KERN_DEBUG "Rx Subframe Data:\n");
+ print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
+ dptr, dlen);
+ }
#endif
__skb_trim(pfirst, sublen);
skb_pull(pfirst, doff);
if (pfirst->len == 0) {
- pkt_buf_free_skb(pfirst);
+ bcm_pkt_buf_free_skb(pfirst);
if (plast) {
plast->next = pnext;
} else {
@@ -3529,7 +3509,7 @@
DHD_ERROR(("%s: rx protocol error\n",
__func__));
bus->dhd->rx_errors++;
- pkt_buf_free_skb(pfirst);
+ bcm_pkt_buf_free_skb(pfirst);
if (plast) {
plast->next = pnext;
} else {
@@ -3552,8 +3532,9 @@
__func__, num, pfirst, pfirst->data,
pfirst->len, pfirst->next,
pfirst->prev));
- prhex("", (u8 *) pfirst->data,
- min_t(int, pfirst->len, 32));
+ print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
+ pfirst->data,
+ min_t(int, pfirst->len, 32));
}
#endif /* DHD_DEBUG */
}
@@ -3578,7 +3559,6 @@
u16 len, check; /* Extracted hardware header fields */
u8 chan, seq, doff; /* Extracted software header fields */
u8 fcbits; /* Extracted fcbits from software header */
- u8 delta;
struct sk_buff *pkt; /* Packet for event or data frames */
u16 pad; /* Number of pad bytes to read */
@@ -3667,7 +3647,7 @@
*/
/* Allocate a packet buffer */
dhd_os_sdlock_rxq(bus->dhd);
- pkt = pkt_buf_get_skb(rdlen + DHD_SDALIGN);
+ pkt = bcm_pkt_buf_get_skb(rdlen + DHD_SDALIGN);
if (!pkt) {
if (bus->bus == SPI_BUS) {
bus->usebufpool = false;
@@ -3684,16 +3664,13 @@
ASSERT(bus->rxctl >= bus->rxbuf);
rxbuf = bus->rxctl;
/* Read the entire frame */
- sdret = dhd_bcmsdh_recv_buf(bus,
- bcmsdh_cur_sbwad
- (sdh),
- SDIO_FUNC_2,
- F2SYNC,
- rxbuf,
- rdlen, NULL,
- NULL, NULL);
+ sdret = bcmsdh_recv_buf(bus,
+ bcmsdh_cur_sbwad(sdh),
+ SDIO_FUNC_2, F2SYNC,
+ rxbuf, rdlen,
+ NULL, NULL, NULL);
bus->f2rxdata++;
- ASSERT(sdret != BCME_PENDING);
+ ASSERT(sdret != -BCME_PENDING);
/* Control frame failures need
retransmission */
@@ -3713,8 +3690,11 @@
} else {
/* Give up on data,
request rtx of events */
- DHD_ERROR(("%s (nextlen): pkt_buf_get_skb failed: len %d rdlen %d " "expected rxseq %d\n",
- __func__, len, rdlen, rxseq));
+ DHD_ERROR(("%s (nextlen): "
+ "bcm_pkt_buf_get_skb failed:"
+ " len %d rdlen %d expected"
+ " rxseq %d\n", __func__,
+ len, rdlen, rxseq));
/* Just go try again w/normal
header read */
dhd_os_sdunlock_rxq(bus->dhd);
@@ -3728,19 +3708,18 @@
PKTALIGN(pkt, rdlen, DHD_SDALIGN);
rxbuf = (u8 *) (pkt->data);
/* Read the entire frame */
- sdret =
- dhd_bcmsdh_recv_buf(bus,
+ sdret = bcmsdh_recv_buf(bus,
bcmsdh_cur_sbwad(sdh),
SDIO_FUNC_2, F2SYNC,
- rxbuf, rdlen, pkt, NULL,
- NULL);
+ rxbuf, rdlen,
+ pkt, NULL, NULL);
bus->f2rxdata++;
- ASSERT(sdret != BCME_PENDING);
+ ASSERT(sdret != -BCME_PENDING);
if (sdret < 0) {
DHD_ERROR(("%s (nextlen): read %d bytes failed: %d\n",
__func__, rdlen, sdret));
- pkt_buf_free_skb(pkt);
+ bcm_pkt_buf_free_skb(pkt);
bus->dhd->rx_errors++;
dhd_os_sdunlock_rxq(bus->dhd);
/* Force retry w/normal header read.
@@ -3767,23 +3746,19 @@
if (!(len | check)) {
DHD_INFO(("%s (nextlen): read zeros in HW "
"header???\n", __func__));
- dhd_os_sdlock_rxq(bus->dhd);
- PKTFREE2();
- dhd_os_sdunlock_rxq(bus->dhd);
- GSPI_PR55150_BAILOUT;
+ dhdsdio_pktfree2(bus, pkt);
continue;
}
/* Validate check bytes */
if ((u16)~(len ^ check)) {
- DHD_ERROR(("%s (nextlen): HW hdr error: nextlen/len/check" " 0x%04x/0x%04x/0x%04x\n",
+ DHD_ERROR(("%s (nextlen): HW hdr error:"
+ " nextlen/len/check"
+ " 0x%04x/0x%04x/0x%04x\n",
__func__, nextlen, len, check));
- dhd_os_sdlock_rxq(bus->dhd);
- PKTFREE2();
- dhd_os_sdunlock_rxq(bus->dhd);
bus->rx_badhdr++;
dhdsdio_rxfail(bus, false, false);
- GSPI_PR55150_BAILOUT;
+ dhdsdio_pktfree2(bus, pkt);
continue;
}
@@ -3791,10 +3766,7 @@
if (len < SDPCM_HDRLEN) {
DHD_ERROR(("%s (nextlen): HW hdr length "
"invalid: %d\n", __func__, len));
- dhd_os_sdlock_rxq(bus->dhd);
- PKTFREE2();
- dhd_os_sdunlock_rxq(bus->dhd);
- GSPI_PR55150_BAILOUT;
+ dhdsdio_pktfree2(bus, pkt);
continue;
}
@@ -3803,31 +3775,25 @@
if (len_consistent) {
/* Mismatch, force retry w/normal
header (may be >4K) */
- DHD_ERROR(("%s (nextlen): mismatch, nextlen %d len %d rnd %d; " "expected rxseq %d\n",
+ DHD_ERROR(("%s (nextlen): mismatch, "
+ "nextlen %d len %d rnd %d; "
+ "expected rxseq %d\n",
__func__, nextlen,
len, roundup(len, 16), rxseq));
- dhd_os_sdlock_rxq(bus->dhd);
- PKTFREE2();
- dhd_os_sdunlock_rxq(bus->dhd);
- dhdsdio_rxfail(bus, true,
- (bus->bus ==
- SPI_BUS) ? false : true);
- GSPI_PR55150_BAILOUT;
+ dhdsdio_rxfail(bus, true, (bus->bus != SPI_BUS));
+ dhdsdio_pktfree2(bus, pkt);
continue;
}
/* Extract software header fields */
- chan =
- SDPCM_PACKET_CHANNEL(&bus->rxhdr
- [SDPCM_FRAMETAG_LEN]);
- seq =
- SDPCM_PACKET_SEQUENCE(&bus->rxhdr
- [SDPCM_FRAMETAG_LEN]);
- doff =
- SDPCM_DOFFSET_VALUE(&bus->rxhdr
- [SDPCM_FRAMETAG_LEN]);
- txmax =
- SDPCM_WINDOW_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
+ chan = SDPCM_PACKET_CHANNEL(
+ &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
+ seq = SDPCM_PACKET_SEQUENCE(
+ &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
+ doff = SDPCM_DOFFSET_VALUE(
+ &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
+ txmax = SDPCM_WINDOW_VALUE(
+ &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
bus->nextlen =
bus->rxhdr[SDPCM_FRAMETAG_LEN +
@@ -3839,21 +3805,18 @@
}
bus->dhd->rx_readahead_cnt++;
+
/* Handle Flow Control */
- fcbits =
- SDPCM_FCMASK_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
+ fcbits = SDPCM_FCMASK_VALUE(
+ &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
- delta = 0;
- if (~bus->flowcontrol & fcbits) {
- bus->fc_xoff++;
- delta = 1;
- }
- if (bus->flowcontrol & ~fcbits) {
- bus->fc_xon++;
- delta = 1;
- }
+ if (bus->flowcontrol != fcbits) {
+ if (~bus->flowcontrol & fcbits)
+ bus->fc_xoff++;
- if (delta) {
+ if (bus->flowcontrol & ~fcbits)
+ bus->fc_xon++;
+
bus->fc_rcvd++;
bus->flowcontrol = fcbits;
}
@@ -3876,33 +3839,30 @@
bus->tx_max = txmax;
#ifdef DHD_DEBUG
- if (DHD_BYTES_ON() && DHD_DATA_ON())
- prhex("Rx Data", rxbuf, len);
- else if (DHD_HDRS_ON())
- prhex("RxHdr", bus->rxhdr, SDPCM_HDRLEN);
+ if (DHD_BYTES_ON() && DHD_DATA_ON()) {
+ printk(KERN_DEBUG "Rx Data:\n");
+ print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
+ rxbuf, len);
+ } else if (DHD_HDRS_ON()) {
+ printk(KERN_DEBUG "RxHdr:\n");
+ print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
+ bus->rxhdr, SDPCM_HDRLEN);
+ }
#endif
if (chan == SDPCM_CONTROL_CHANNEL) {
if (bus->bus == SPI_BUS) {
dhdsdio_read_control(bus, rxbuf, len,
doff);
- if (bus->usebufpool) {
- dhd_os_sdlock_rxq(bus->dhd);
- pkt_buf_free_skb(pkt);
- dhd_os_sdunlock_rxq(bus->dhd);
- }
- continue;
} else {
DHD_ERROR(("%s (nextlen): readahead on control" " packet %d?\n",
__func__, seq));
/* Force retry w/normal header read */
bus->nextlen = 0;
dhdsdio_rxfail(bus, false, true);
- dhd_os_sdlock_rxq(bus->dhd);
- PKTFREE2();
- dhd_os_sdunlock_rxq(bus->dhd);
- continue;
}
+ dhdsdio_pktfree2(bus, pkt);
+ continue;
}
if ((bus->bus == SPI_BUS) && !bus->usebufpool) {
@@ -3915,11 +3875,8 @@
if ((doff < SDPCM_HDRLEN) || (doff > len)) {
DHD_ERROR(("%s (nextlen): bad data offset %d: HW len %d min %d\n",
__func__, doff, len, SDPCM_HDRLEN));
- dhd_os_sdlock_rxq(bus->dhd);
- PKTFREE2();
- dhd_os_sdunlock_rxq(bus->dhd);
- ASSERT(0);
dhdsdio_rxfail(bus, false, false);
+ dhdsdio_pktfree2(bus, pkt);
continue;
}
@@ -3931,12 +3888,11 @@
break;
/* Read frame header (hardware and software) */
- sdret =
- dhd_bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
- F2SYNC, bus->rxhdr, firstread, NULL,
- NULL, NULL);
+ sdret = bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh),
+ SDIO_FUNC_2, F2SYNC, bus->rxhdr, firstread,
+ NULL, NULL, NULL);
bus->f2rxhdrs++;
- ASSERT(sdret != BCME_PENDING);
+ ASSERT(sdret != -BCME_PENDING);
if (sdret < 0) {
DHD_ERROR(("%s: RXHEADER FAILED: %d\n", __func__,
@@ -3946,8 +3902,11 @@
continue;
}
#ifdef DHD_DEBUG
- if (DHD_BYTES_ON() || DHD_HDRS_ON())
- prhex("RxHdr", bus->rxhdr, SDPCM_HDRLEN);
+ if (DHD_BYTES_ON() || DHD_HDRS_ON()) {
+ printk(KERN_DEBUG "RxHdr:\n");
+ print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
+ bus->rxhdr, SDPCM_HDRLEN);
+ }
#endif
/* Extract hardware header fields */
@@ -4006,17 +3965,13 @@
/* Handle Flow Control */
fcbits = SDPCM_FCMASK_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
- delta = 0;
- if (~bus->flowcontrol & fcbits) {
- bus->fc_xoff++;
- delta = 1;
- }
- if (bus->flowcontrol & ~fcbits) {
- bus->fc_xon++;
- delta = 1;
- }
+ if (bus->flowcontrol != fcbits) {
+ if (~bus->flowcontrol & fcbits)
+ bus->fc_xoff++;
- if (delta) {
+ if (bus->flowcontrol & ~fcbits)
+ bus->fc_xon++;
+
bus->fc_rcvd++;
bus->flowcontrol = fcbits;
}
@@ -4077,11 +4032,11 @@
}
dhd_os_sdlock_rxq(bus->dhd);
- pkt = pkt_buf_get_skb(rdlen + firstread + DHD_SDALIGN);
+ pkt = bcm_pkt_buf_get_skb(rdlen + firstread + DHD_SDALIGN);
if (!pkt) {
/* Give up on data, request rtx of events */
- DHD_ERROR(("%s: pkt_buf_get_skb failed: rdlen %d chan %d\n",
- __func__, rdlen, chan));
+ DHD_ERROR(("%s: bcm_pkt_buf_get_skb failed: rdlen %d "
+ "chan %d\n", __func__, rdlen, chan));
bus->dhd->rx_dropped++;
dhd_os_sdunlock_rxq(bus->dhd);
dhdsdio_rxfail(bus, false, RETRYCHAN(chan));
@@ -4097,12 +4052,11 @@
PKTALIGN(pkt, rdlen, DHD_SDALIGN);
/* Read the remaining frame data */
- sdret =
- dhd_bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
+ sdret = bcmsdh_recv_buf(bus, bcmsdh_cur_sbwad(sdh), SDIO_FUNC_2,
F2SYNC, ((u8 *) (pkt->data)), rdlen,
pkt, NULL, NULL);
bus->f2rxdata++;
- ASSERT(sdret != BCME_PENDING);
+ ASSERT(sdret != -BCME_PENDING);
if (sdret < 0) {
DHD_ERROR(("%s: read %d %s bytes failed: %d\n",
@@ -4113,7 +4067,7 @@
? "data" : "test")),
sdret));
dhd_os_sdlock_rxq(bus->dhd);
- pkt_buf_free_skb(pkt);
+ bcm_pkt_buf_free_skb(pkt);
dhd_os_sdunlock_rxq(bus->dhd);
bus->dhd->rx_errors++;
dhdsdio_rxfail(bus, true, RETRYCHAN(chan));
@@ -4125,8 +4079,11 @@
memcpy(pkt->data, bus->rxhdr, firstread);
#ifdef DHD_DEBUG
- if (DHD_BYTES_ON() && DHD_DATA_ON())
- prhex("Rx Data", pkt->data, len);
+ if (DHD_BYTES_ON() && DHD_DATA_ON()) {
+ printk(KERN_DEBUG "Rx Data:\n");
+ print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
+ pkt->data, len);
+ }
#endif
deliver:
@@ -4137,7 +4094,10 @@
__func__, len));
#ifdef DHD_DEBUG
if (DHD_GLOM_ON()) {
- prhex("Glom Data", pkt->data, len);
+ printk(KERN_DEBUG "Glom Data:\n");
+ print_hex_dump_bytes("",
+ DUMP_PREFIX_OFFSET,
+ pkt->data, len);
}
#endif
__skb_trim(pkt, len);
@@ -4166,13 +4126,13 @@
if (pkt->len == 0) {
dhd_os_sdlock_rxq(bus->dhd);
- pkt_buf_free_skb(pkt);
+ bcm_pkt_buf_free_skb(pkt);
dhd_os_sdunlock_rxq(bus->dhd);
continue;
} else if (dhd_prot_hdrpull(bus->dhd, &ifidx, pkt) != 0) {
DHD_ERROR(("%s: rx protocol error\n", __func__));
dhd_os_sdlock_rxq(bus->dhd);
- pkt_buf_free_skb(pkt);
+ bcm_pkt_buf_free_skb(pkt);
dhd_os_sdunlock_rxq(bus->dhd);
bus->dhd->rx_errors++;
continue;
@@ -4245,16 +4205,16 @@
/*
* Flow Control has been moved into the RX headers and this out of band
- * method isn't used any more. Leae this here for possibly
- * remaining backward
- * compatible with older dongles
+ * method isn't used any more.
+ * remaining backward compatible with older dongles.
*/
if (hmb_data & HMB_DATA_FC) {
- fcbits =
- (hmb_data & HMB_DATA_FCDATA_MASK) >> HMB_DATA_FCDATA_SHIFT;
+ fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >>
+ HMB_DATA_FCDATA_SHIFT;
if (fcbits & ~bus->flowcontrol)
bus->fc_xoff++;
+
if (bus->flowcontrol & ~fcbits)
bus->fc_xon++;
@@ -4454,7 +4414,7 @@
F2SYNC, (u8 *) bus->ctrl_frame_buf,
(u32) bus->ctrl_frame_len, NULL,
NULL, NULL);
- ASSERT(ret != BCME_PENDING);
+ ASSERT(ret != -BCME_PENDING);
if (ret < 0) {
/* On failure, abort the command and
@@ -4493,7 +4453,7 @@
}
/* Send queued frames (limit 1 if rx may still be pending) */
else if ((bus->clkstate == CLK_AVAIL) && !bus->fcstate &&
- pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit
+ bcm_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit
&& DATAOK(bus)) {
framecnt = rxdone ? txlimit : min(txlimit, dhd_txminmax);
framecnt = dhdsdio_sendfromq(bus, framecnt);
@@ -4514,7 +4474,7 @@
"I_CHIPACTIVE interrupt\n", __func__));
resched = true;
} else if (bus->intstatus || bus->ipend ||
- (!bus->fcstate && pktq_mlen(&bus->txq, ~bus->flowcontrol) &&
+ (!bus->fcstate && bcm_pktq_mlen(&bus->txq, ~bus->flowcontrol) &&
DATAOK(bus)) || PKT_AVAILABLE()) {
resched = true;
}
@@ -4648,11 +4608,12 @@
/* Allocate an appropriate-sized packet */
len = bus->pktgen_len;
- pkt = pkt_buf_get_skb(
+ pkt = bcm_pkt_buf_get_skb(
(len + SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + DHD_SDALIGN),
true);
if (!pkt) {
- DHD_ERROR(("%s: pkt_buf_get_skb failed!\n", __func__));
+ DHD_ERROR(("%s: bcm_pkt_buf_get_skb failed!\n",
+ __func__));
break;
}
PKTALIGN(pkt, (len + SDPCM_HDRLEN + SDPCM_TEST_HDRLEN),
@@ -4679,7 +4640,7 @@
default:
DHD_ERROR(("Unrecognized pktgen mode %d\n",
bus->pktgen_mode));
- pkt_buf_free_skb(pkt, true);
+ bcm_pkt_buf_free_skb(pkt, true);
bus->pktgen_count = 0;
return;
}
@@ -4697,8 +4658,9 @@
#ifdef DHD_DEBUG
if (DHD_BYTES_ON() && DHD_DATA_ON()) {
data = (u8 *) (pkt->data) + SDPCM_HDRLEN;
- prhex("dhdsdio_pktgen: Tx Data", data,
- pkt->len - SDPCM_HDRLEN);
+ printk(KERN_DEBUG "dhdsdio_pktgen: Tx Data:\n");
+ print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, data,
+ pkt->len - SDPCM_HDRLEN);
}
#endif
@@ -4727,10 +4689,10 @@
u8 *data;
/* Allocate the packet */
- pkt = pkt_buf_get_skb(SDPCM_HDRLEN + SDPCM_TEST_HDRLEN + DHD_SDALIGN,
- true);
+ pkt = bcm_pkt_buf_get_skb(SDPCM_HDRLEN + SDPCM_TEST_HDRLEN +
+ DHD_SDALIGN, true);
if (!pkt) {
- DHD_ERROR(("%s: pkt_buf_get_skb failed!\n", __func__));
+ DHD_ERROR(("%s: bcm_pkt_buf_get_skb failed!\n", __func__));
return;
}
PKTALIGN(pkt, (SDPCM_HDRLEN + SDPCM_TEST_HDRLEN), DHD_SDALIGN);
@@ -4762,7 +4724,7 @@
if (pktlen < SDPCM_TEST_HDRLEN) {
DHD_ERROR(("dhdsdio_restrcv: toss runt frame, pktlen %d\n",
pktlen));
- pkt_buf_free_skb(pkt, false);
+ bcm_pkt_buf_free_skb(pkt, false);
return;
}
@@ -4780,7 +4742,7 @@
DHD_ERROR(("dhdsdio_testrcv: frame length mismatch, "
"pktlen %d seq %d" " cmd %d extra %d len %d\n",
pktlen, seq, cmd, extra, len));
- pkt_buf_free_skb(pkt, false);
+ bcm_pkt_buf_free_skb(pkt, false);
return;
}
}
@@ -4795,14 +4757,14 @@
bus->pktgen_sent++;
} else {
bus->pktgen_fail++;
- pkt_buf_free_skb(pkt, false);
+ bcm_pkt_buf_free_skb(pkt, false);
}
bus->pktgen_rcvd++;
break;
case SDPCM_TEST_ECHORSP:
if (bus->ext_loop) {
- pkt_buf_free_skb(pkt, false);
+ bcm_pkt_buf_free_skb(pkt, false);
bus->pktgen_rcvd++;
break;
}
@@ -4815,12 +4777,12 @@
break;
}
}
- pkt_buf_free_skb(pkt, false);
+ bcm_pkt_buf_free_skb(pkt, false);
bus->pktgen_rcvd++;
break;
case SDPCM_TEST_DISCARD:
- pkt_buf_free_skb(pkt, false);
+ bcm_pkt_buf_free_skb(pkt, false);
bus->pktgen_rcvd++;
break;
@@ -4830,7 +4792,7 @@
DHD_INFO(("dhdsdio_testrcv: unsupported or unknown command, "
"pktlen %d seq %d" " cmd %d extra %d len %d\n",
pktlen, seq, cmd, extra, len));
- pkt_buf_free_skb(pkt, false);
+ bcm_pkt_buf_free_skb(pkt, false);
break;
}
@@ -4952,7 +4914,7 @@
/* Address could be zero if CONSOLE := 0 in dongle Makefile */
if (bus->console_addr == 0)
- return BCME_UNSUPPORTED;
+ return -ENOTSUPP;
/* Exclusive bus access */
dhd_os_sdlock(bus->dhd);
@@ -4960,7 +4922,7 @@
/* Don't allow input if dongle is in reset */
if (bus->dhd->dongle_reset) {
dhd_os_sdunlock(bus->dhd);
- return BCME_NOTREADY;
+ return -EPERM;
}
/* Request clock to allow SDIO accesses */
@@ -4991,7 +4953,7 @@
/* Bump dongle by sending an empty event pkt.
* sdpcm_sendup (RX) checks for virtual console input.
*/
- pkt = pkt_buf_get_skb(4 + SDPCM_RESERVE);
+ pkt = bcm_pkt_buf_get_skb(4 + SDPCM_RESERVE);
if ((pkt != NULL) && bus->clkstate == CLK_AVAIL)
dhdsdio_txpkt(bus, pkt, SDPCM_EVENT_CHANNEL, true);
@@ -5089,7 +5051,7 @@
/* Check the Vendor ID */
switch (venid) {
case 0x0000:
- case VENDOR_BROADCOM:
+ case PCI_VENDOR_ID_BROADCOM:
break;
default:
DHD_ERROR(("%s: unknown vendor: 0x%04x\n", __func__, venid));
@@ -5179,7 +5141,7 @@
/* if firmware path present try to download and bring up bus */
ret = dhd_bus_start(bus->dhd);
if (ret != 0) {
- if (ret == BCME_NOTUP) {
+ if (ret == -ENOLINK) {
DHD_ERROR(("%s: dongle is not responding\n", __func__));
goto fail;
}
@@ -5215,7 +5177,10 @@
#endif /* DHD_DEBUG */
- /* Force PLL off until si_attach() programs PLL control regs */
+ /*
+ * Force PLL off until dhdsdio_chip_attach()
+ * programs PLL control regs
+ */
bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
DHD_INIT_CLKCTL1, &err);
@@ -5281,34 +5246,26 @@
}
#endif /* DHD_DEBUG */
- /* si_attach() will provide an SI handle and scan the backplane */
- bus->sih = si_attach((uint) devid, regsva, DHD_BUS, sdh,
- &bus->vars, &bus->varsz);
- if (!(bus->sih)) {
- DHD_ERROR(("%s: si_attach failed!\n", __func__));
+ if (dhdsdio_chip_attach(bus, regsva)) {
+ DHD_ERROR(("%s: dhdsdio_chip_attach failed!\n", __func__));
goto fail;
}
- bcmsdh_chipinfo(sdh, bus->sih->chip, bus->sih->chiprev);
+ bcmsdh_chipinfo(sdh, bus->ci->chip, bus->ci->chiprev);
- if (!dhdsdio_chipmatch((u16) bus->sih->chip)) {
+ if (!dhdsdio_chipmatch((u16) bus->ci->chip)) {
DHD_ERROR(("%s: unsupported chip: 0x%04x\n",
- __func__, bus->sih->chip));
+ __func__, bus->ci->chip));
goto fail;
}
- si_sdiod_drive_strength_init(bus->sih, dhd_sdiod_drive_strength);
+ dhdsdio_sdiod_drive_strength_init(bus, dhd_sdiod_drive_strength);
/* Get info on the ARM and SOCRAM cores... */
if (!DHD_NOPMU(bus)) {
- if ((si_setcore(bus->sih, ARM7S_CORE_ID, 0)) ||
- (si_setcore(bus->sih, ARMCM3_CORE_ID, 0))) {
- bus->armrev = si_corerev(bus->sih);
- } else {
- DHD_ERROR(("%s: failed to find ARM core!\n", __func__));
- goto fail;
- }
- bus->orig_ramsize = si_socram_size(bus->sih);
+ bus->armrev = SBCOREREV(bcmsdh_reg_read(bus->sdh,
+ CORE_SB(bus->ci->armcorebase, sbidhigh), 4));
+ bus->orig_ramsize = bus->ci->ramsize;
if (!(bus->orig_ramsize)) {
DHD_ERROR(("%s: failed to find SOCRAM memory!\n",
__func__));
@@ -5322,22 +5279,12 @@
bus->ramsize, bus->orig_ramsize));
}
- /* ...but normally deal with the SDPCMDEV core */
- bus->regs = si_setcore(bus->sih, PCMCIA_CORE_ID, 0);
- if (!bus->regs) {
- bus->regs = si_setcore(bus->sih, SDIOD_CORE_ID, 0);
- if (!bus->regs) {
- DHD_ERROR(("%s: failed to find SDIODEV core!\n",
- __func__));
- goto fail;
- }
- }
- bus->sdpcmrev = si_corerev(bus->sih);
+ bus->regs = (void *)bus->ci->buscorebase;
/* Set core control so an SDIO reset does a backplane reset */
OR_REG(&bus->regs->corecontrol, CC_BPRESEN);
- pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN);
+ bcm_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN);
/* Locate an appropriately-aligned portion of hdrbuf */
bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0], DHD_SDALIGN);
@@ -5425,7 +5372,7 @@
/* Query the SD clock speed */
if (bcmsdh_iovar_op(sdh, "sd_divisor", NULL, 0,
&bus->sd_divisor, sizeof(s32),
- false) != BCME_OK) {
+ false) != 0) {
DHD_ERROR(("%s: fail on %s get\n", __func__, "sd_divisor"));
bus->sd_divisor = -1;
} else {
@@ -5435,7 +5382,7 @@
/* Query the SD bus mode */
if (bcmsdh_iovar_op(sdh, "sd_mode", NULL, 0,
- &bus->sd_mode, sizeof(s32), false) != BCME_OK) {
+ &bus->sd_mode, sizeof(s32), false) != 0) {
DHD_ERROR(("%s: fail on %s get\n", __func__, "sd_mode"));
bus->sd_mode = -1;
} else {
@@ -5446,7 +5393,7 @@
/* Query the F2 block size, set roundup accordingly */
fnum = 2;
if (bcmsdh_iovar_op(sdh, "sd_blocksize", &fnum, sizeof(s32),
- &bus->blocksize, sizeof(s32), false) != BCME_OK) {
+ &bus->blocksize, sizeof(s32), false) != 0) {
bus->blocksize = 0;
DHD_ERROR(("%s: fail on %s get\n", __func__, "sd_blocksize"));
} else {
@@ -5459,7 +5406,7 @@
default to use if supported */
if (bcmsdh_iovar_op(sdh, "sd_rxchain", NULL, 0,
&bus->sd_rxchain, sizeof(s32),
- false) != BCME_OK) {
+ false) != 0) {
bus->sd_rxchain = false;
} else {
DHD_INFO(("%s: bus module (through bcmsdh API) %s chaining\n",
@@ -5509,10 +5456,8 @@
bcmsdh_intr_dereg(bus->sdh);
if (bus->dhd) {
-
- dhdsdio_release_dongle(bus);
-
dhd_detach(bus->dhd);
+ dhdsdio_release_dongle(bus);
bus->dhd = NULL;
}
@@ -5548,13 +5493,10 @@
if (bus->dhd && bus->dhd->dongle_reset)
return;
- if (bus->sih) {
+ if (bus->ci) {
dhdsdio_clkctl(bus, CLK_AVAIL, false);
-#if !defined(BCMLXSDMMC)
- si_watchdog(bus->sih, 4);
-#endif /* !defined(BCMLXSDMMC) */
dhdsdio_clkctl(bus, CLK_NONE, false);
- si_detach(bus->sih);
+ dhdsdio_chip_detach(bus);
if (bus->vars && bus->varsz)
kfree(bus->vars);
bus->vars = NULL;
@@ -5642,7 +5584,7 @@
ularray = kmalloc(bus->ramsize, GFP_ATOMIC);
if (!ularray) {
- bcmerror = BCME_NOMEM;
+ bcmerror = -ENOMEM;
goto err;
}
/* Upload image to verify downloaded contents. */
@@ -5865,7 +5807,7 @@
} else {
DHD_ERROR(("%s: error reading nvram file: %d\n",
__func__, len));
- bcmerror = BCME_SDIO_ERROR;
+ bcmerror = -EIO;
}
err:
@@ -5954,19 +5896,6 @@
return bcmerror;
}
-static int
-dhd_bcmsdh_recv_buf(dhd_bus_t *bus, u32 addr, uint fn, uint flags,
- u8 *buf, uint nbytes, struct sk_buff *pkt,
- bcmsdh_cmplt_fn_t complete, void *handle)
-{
- int status;
-
- /* 4329: GSPI check */
- status =
- bcmsdh_recv_buf(bus->sdh, addr, fn, flags, buf, nbytes, pkt,
- complete, handle);
- return status;
-}
static int
dhd_bcmsdh_send_buf(dhd_bus_t *bus, u32 addr, uint fn, uint flags,
@@ -5980,8 +5909,8 @@
uint dhd_bus_chip(struct dhd_bus *bus)
{
- ASSERT(bus->sih != NULL);
- return bus->sih->chip;
+ ASSERT(bus->ci != NULL);
+ return bus->ci->chip;
}
void *dhd_bus_pub(struct dhd_bus *bus)
@@ -6023,7 +5952,7 @@
DHD_TRACE(("%s: WLAN OFF DONE\n", __func__));
/* App can now remove power from device */
} else
- bcmerror = BCME_SDIO_ERROR;
+ bcmerror = -EIO;
} else {
/* App must have restored power to device before calling */
@@ -6058,15 +5987,404 @@
DHD_TRACE(("%s: WLAN ON DONE\n",
__func__));
} else
- bcmerror = BCME_SDIO_ERROR;
+ bcmerror = -EIO;
} else
- bcmerror = BCME_SDIO_ERROR;
+ bcmerror = -EIO;
} else {
- bcmerror = BCME_NOTDOWN;
+ bcmerror = -EISCONN;
DHD_ERROR(("%s: Set DEVRESET=false invoked when device "
"is on\n", __func__));
- bcmerror = BCME_SDIO_ERROR;
+ bcmerror = -EIO;
}
}
return bcmerror;
}
+
+static int
+dhdsdio_chip_recognition(bcmsdh_info_t *sdh, struct chip_info *ci, void *regs)
+{
+ u32 regdata;
+
+ /*
+ * Get CC core rev
+ * Chipid is assume to be at offset 0 from regs arg
+ * For different chiptypes or old sdio hosts w/o chipcommon,
+ * other ways of recognition should be added here.
+ */
+ ci->cccorebase = (u32)regs;
+ regdata = bcmsdh_reg_read(sdh, CORE_CC_REG(ci->cccorebase, chipid), 4);
+ ci->chip = regdata & CID_ID_MASK;
+ ci->chiprev = (regdata & CID_REV_MASK) >> CID_REV_SHIFT;
+
+ DHD_INFO(("%s: chipid=0x%x chiprev=%d\n",
+ __func__, ci->chip, ci->chiprev));
+
+ /* Address of cores for new chips should be added here */
+ switch (ci->chip) {
+ case BCM4329_CHIP_ID:
+ ci->buscorebase = BCM4329_CORE_BUS_BASE;
+ ci->ramcorebase = BCM4329_CORE_SOCRAM_BASE;
+ ci->armcorebase = BCM4329_CORE_ARM_BASE;
+ ci->ramsize = BCM4329_RAMSIZE;
+ break;
+ default:
+ DHD_ERROR(("%s: chipid 0x%x is not supported\n",
+ __func__, ci->chip));
+ return -ENODEV;
+ }
+
+ regdata = bcmsdh_reg_read(sdh,
+ CORE_SB(ci->cccorebase, sbidhigh), 4);
+ ci->ccrev = SBCOREREV(regdata);
+
+ regdata = bcmsdh_reg_read(sdh,
+ CORE_CC_REG(ci->cccorebase, pmucapabilities), 4);
+ ci->pmurev = regdata & PCAP_REV_MASK;
+
+ regdata = bcmsdh_reg_read(sdh, CORE_SB(ci->buscorebase, sbidhigh), 4);
+ ci->buscorerev = SBCOREREV(regdata);
+ ci->buscoretype = (regdata & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT;
+
+ DHD_INFO(("%s: ccrev=%d, pmurev=%d, buscore rev/type=%d/0x%x\n",
+ __func__, ci->ccrev, ci->pmurev,
+ ci->buscorerev, ci->buscoretype));
+
+ /* get chipcommon capabilites */
+ ci->cccaps = bcmsdh_reg_read(sdh,
+ CORE_CC_REG(ci->cccorebase, capabilities), 4);
+
+ return 0;
+}
+
+static void
+dhdsdio_chip_disablecore(bcmsdh_info_t *sdh, u32 corebase)
+{
+ u32 regdata;
+
+ regdata = bcmsdh_reg_read(sdh,
+ CORE_SB(corebase, sbtmstatelow), 4);
+ if (regdata & SBTML_RESET)
+ return;
+
+ regdata = bcmsdh_reg_read(sdh,
+ CORE_SB(corebase, sbtmstatelow), 4);
+ if ((regdata & (SICF_CLOCK_EN << SBTML_SICF_SHIFT)) != 0) {
+ /*
+ * set target reject and spin until busy is clear
+ * (preserve core-specific bits)
+ */
+ regdata = bcmsdh_reg_read(sdh,
+ CORE_SB(corebase, sbtmstatelow), 4);
+ bcmsdh_reg_write(sdh, CORE_SB(corebase, sbtmstatelow), 4,
+ regdata | SBTML_REJ);
+
+ regdata = bcmsdh_reg_read(sdh,
+ CORE_SB(corebase, sbtmstatelow), 4);
+ udelay(1);
+ SPINWAIT((bcmsdh_reg_read(sdh,
+ CORE_SB(corebase, sbtmstatehigh), 4) &
+ SBTMH_BUSY), 100000);
+
+ regdata = bcmsdh_reg_read(sdh,
+ CORE_SB(corebase, sbtmstatehigh), 4);
+ if (regdata & SBTMH_BUSY)
+ DHD_ERROR(("%s: ARM core still busy\n", __func__));
+
+ regdata = bcmsdh_reg_read(sdh,
+ CORE_SB(corebase, sbidlow), 4);
+ if (regdata & SBIDL_INIT) {
+ regdata = bcmsdh_reg_read(sdh,
+ CORE_SB(corebase, sbimstate), 4) |
+ SBIM_RJ;
+ bcmsdh_reg_write(sdh,
+ CORE_SB(corebase, sbimstate), 4,
+ regdata);
+ regdata = bcmsdh_reg_read(sdh,
+ CORE_SB(corebase, sbimstate), 4);
+ udelay(1);
+ SPINWAIT((bcmsdh_reg_read(sdh,
+ CORE_SB(corebase, sbimstate), 4) &
+ SBIM_BY), 100000);
+ }
+
+ /* set reset and reject while enabling the clocks */
+ bcmsdh_reg_write(sdh,
+ CORE_SB(corebase, sbtmstatelow), 4,
+ (((SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
+ SBTML_REJ | SBTML_RESET));
+ regdata = bcmsdh_reg_read(sdh,
+ CORE_SB(corebase, sbtmstatelow), 4);
+ udelay(10);
+
+ /* clear the initiator reject bit */
+ regdata = bcmsdh_reg_read(sdh,
+ CORE_SB(corebase, sbidlow), 4);
+ if (regdata & SBIDL_INIT) {
+ regdata = bcmsdh_reg_read(sdh,
+ CORE_SB(corebase, sbimstate), 4) &
+ ~SBIM_RJ;
+ bcmsdh_reg_write(sdh,
+ CORE_SB(corebase, sbimstate), 4,
+ regdata);
+ }
+ }
+
+ /* leave reset and reject asserted */
+ bcmsdh_reg_write(sdh, CORE_SB(corebase, sbtmstatelow), 4,
+ (SBTML_REJ | SBTML_RESET));
+ udelay(1);
+}
+
+static int
+dhdsdio_chip_attach(struct dhd_bus *bus, void *regs)
+{
+ struct chip_info *ci;
+ int err;
+ u8 clkval, clkset;
+
+ DHD_TRACE(("%s: Enter\n", __func__));
+
+ /* alloc chip_info_t */
+ ci = kmalloc(sizeof(struct chip_info), GFP_ATOMIC);
+ if (NULL == ci) {
+ DHD_ERROR(("%s: malloc failed!\n", __func__));
+ return -ENOMEM;
+ }
+
+ memset((unsigned char *)ci, 0, sizeof(struct chip_info));
+
+ /* bus/core/clk setup for register access */
+ /* Try forcing SDIO core to do ALPAvail request only */
+ clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ;
+ bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
+ clkset, &err);
+ if (err) {
+ DHD_ERROR(("%s: error writing for HT off\n", __func__));
+ goto fail;
+ }
+
+ /* If register supported, wait for ALPAvail and then force ALP */
+ /* This may take up to 15 milliseconds */
+ clkval = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1,
+ SBSDIO_FUNC1_CHIPCLKCSR, NULL);
+ if ((clkval & ~SBSDIO_AVBITS) == clkset) {
+ SPINWAIT(((clkval =
+ bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1,
+ SBSDIO_FUNC1_CHIPCLKCSR,
+ NULL)),
+ !SBSDIO_ALPAV(clkval)),
+ PMU_MAX_TRANSITION_DLY);
+ if (!SBSDIO_ALPAV(clkval)) {
+ DHD_ERROR(("%s: timeout on ALPAV wait, clkval 0x%02x\n",
+ __func__, clkval));
+ err = -EBUSY;
+ goto fail;
+ }
+ clkset = SBSDIO_FORCE_HW_CLKREQ_OFF |
+ SBSDIO_FORCE_ALP;
+ bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1,
+ SBSDIO_FUNC1_CHIPCLKCSR,
+ clkset, &err);
+ udelay(65);
+ } else {
+ DHD_ERROR(("%s: ChipClkCSR access: wrote 0x%02x read 0x%02x\n",
+ __func__, clkset, clkval));
+ err = -EACCES;
+ goto fail;
+ }
+
+ /* Also, disable the extra SDIO pull-ups */
+ bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SDIOPULLUP, 0,
+ NULL);
+
+ err = dhdsdio_chip_recognition(bus->sdh, ci, regs);
+ if (err)
+ goto fail;
+
+ /*
+ * Make sure any on-chip ARM is off (in case strapping is wrong),
+ * or downloaded code was already running.
+ */
+ dhdsdio_chip_disablecore(bus->sdh, ci->armcorebase);
+
+ bcmsdh_reg_write(bus->sdh,
+ CORE_CC_REG(ci->cccorebase, gpiopullup), 4, 0);
+ bcmsdh_reg_write(bus->sdh,
+ CORE_CC_REG(ci->cccorebase, gpiopulldown), 4, 0);
+
+ /* Disable F2 to clear any intermediate frame state on the dongle */
+ bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_0, SDIOD_CCCR_IOEN,
+ SDIO_FUNC_ENABLE_1, NULL);
+
+ /* WAR: cmd52 backplane read so core HW will drop ALPReq */
+ clkval = bcmsdh_cfg_read(bus->sdh, SDIO_FUNC_1,
+ 0, NULL);
+
+ /* Done with backplane-dependent accesses, can drop clock... */
+ bcmsdh_cfg_write(bus->sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR, 0,
+ NULL);
+
+ bus->ci = ci;
+ return 0;
+fail:
+ bus->ci = NULL;
+ kfree(ci);
+ return err;
+}
+
+static void
+dhdsdio_chip_resetcore(bcmsdh_info_t *sdh, u32 corebase)
+{
+ u32 regdata;
+
+ /*
+ * Must do the disable sequence first to work for
+ * arbitrary current core state.
+ */
+ dhdsdio_chip_disablecore(sdh, corebase);
+
+ /*
+ * Now do the initialization sequence.
+ * set reset while enabling the clock and
+ * forcing them on throughout the core
+ */
+ bcmsdh_reg_write(sdh, CORE_SB(corebase, sbtmstatelow), 4,
+ ((SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
+ SBTML_RESET);
+ udelay(1);
+
+ regdata = bcmsdh_reg_read(sdh, CORE_SB(corebase, sbtmstatehigh), 4);
+ if (regdata & SBTMH_SERR)
+ bcmsdh_reg_write(sdh, CORE_SB(corebase, sbtmstatehigh), 4, 0);
+
+ regdata = bcmsdh_reg_read(sdh, CORE_SB(corebase, sbimstate), 4);
+ if (regdata & (SBIM_IBE | SBIM_TO))
+ bcmsdh_reg_write(sdh, CORE_SB(corebase, sbimstate), 4,
+ regdata & ~(SBIM_IBE | SBIM_TO));
+
+ /* clear reset and allow it to propagate throughout the core */
+ bcmsdh_reg_write(sdh, CORE_SB(corebase, sbtmstatelow), 4,
+ (SICF_FGC << SBTML_SICF_SHIFT) |
+ (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
+ udelay(1);
+
+ /* leave clock enabled */
+ bcmsdh_reg_write(sdh, CORE_SB(corebase, sbtmstatelow), 4,
+ (SICF_CLOCK_EN << SBTML_SICF_SHIFT));
+ udelay(1);
+}
+
+/* SDIO Pad drive strength to select value mappings */
+struct sdiod_drive_str {
+ u8 strength; /* Pad Drive Strength in mA */
+ u8 sel; /* Chip-specific select value */
+};
+
+/* SDIO Drive Strength to sel value table for PMU Rev 1 */
+static const struct sdiod_drive_str sdiod_drive_strength_tab1[] = {
+ {
+ 4, 0x2}, {
+ 2, 0x3}, {
+ 1, 0x0}, {
+ 0, 0x0}
+ };
+
+/* SDIO Drive Strength to sel value table for PMU Rev 2, 3 */
+static const struct sdiod_drive_str sdiod_drive_strength_tab2[] = {
+ {
+ 12, 0x7}, {
+ 10, 0x6}, {
+ 8, 0x5}, {
+ 6, 0x4}, {
+ 4, 0x2}, {
+ 2, 0x1}, {
+ 0, 0x0}
+ };
+
+/* SDIO Drive Strength to sel value table for PMU Rev 8 (1.8V) */
+static const struct sdiod_drive_str sdiod_drive_strength_tab3[] = {
+ {
+ 32, 0x7}, {
+ 26, 0x6}, {
+ 22, 0x5}, {
+ 16, 0x4}, {
+ 12, 0x3}, {
+ 8, 0x2}, {
+ 4, 0x1}, {
+ 0, 0x0}
+ };
+
+#define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu))
+
+static void
+dhdsdio_sdiod_drive_strength_init(struct dhd_bus *bus, u32 drivestrength) {
+ struct sdiod_drive_str *str_tab = NULL;
+ u32 str_mask = 0;
+ u32 str_shift = 0;
+ char chn[8];
+
+ if (!(bus->ci->cccaps & CC_CAP_PMU))
+ return;
+
+ switch (SDIOD_DRVSTR_KEY(bus->ci->chip, bus->ci->pmurev)) {
+ case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 1):
+ str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab1;
+ str_mask = 0x30000000;
+ str_shift = 28;
+ break;
+ case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 2):
+ case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 3):
+ str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab2;
+ str_mask = 0x00003800;
+ str_shift = 11;
+ break;
+ case SDIOD_DRVSTR_KEY(BCM4336_CHIP_ID, 8):
+ str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab3;
+ str_mask = 0x00003800;
+ str_shift = 11;
+ break;
+ default:
+ DHD_ERROR(("No SDIO Drive strength init"
+ "done for chip %s rev %d pmurev %d\n",
+ bcm_chipname(bus->ci->chip, chn, 8),
+ bus->ci->chiprev, bus->ci->pmurev));
+ break;
+ }
+
+ if (str_tab != NULL) {
+ u32 drivestrength_sel = 0;
+ u32 cc_data_temp;
+ int i;
+
+ for (i = 0; str_tab[i].strength != 0; i++) {
+ if (drivestrength >= str_tab[i].strength) {
+ drivestrength_sel = str_tab[i].sel;
+ break;
+ }
+ }
+
+ bcmsdh_reg_write(bus->sdh,
+ CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr),
+ 4, 1);
+ cc_data_temp = bcmsdh_reg_read(bus->sdh,
+ CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr), 4);
+ cc_data_temp &= ~str_mask;
+ drivestrength_sel <<= str_shift;
+ cc_data_temp |= drivestrength_sel;
+ bcmsdh_reg_write(bus->sdh,
+ CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr),
+ 4, cc_data_temp);
+
+ DHD_INFO(("SDIO: %dmA drive strength selected, set to 0x%08x\n",
+ drivestrength, cc_data_temp));
+ }
+}
+
+static void
+dhdsdio_chip_detach(struct dhd_bus *bus)
+{
+ DHD_TRACE(("%s: Enter\n", __func__));
+
+ kfree(bus->ci);
+ bus->ci = NULL;
+}
diff --git a/drivers/staging/brcm80211/brcmfmac/hndpmu.c b/drivers/staging/brcm80211/brcmfmac/hndpmu.c
deleted file mode 100644
index e841da6..0000000
--- a/drivers/staging/brcm80211/brcmfmac/hndpmu.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../util/hndpmu.c"
diff --git a/drivers/staging/brcm80211/brcmfmac/sbutils.c b/drivers/staging/brcm80211/brcmfmac/sbutils.c
deleted file mode 100644
index 64496b8..0000000
--- a/drivers/staging/brcm80211/brcmfmac/sbutils.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../util/sbutils.c"
diff --git a/drivers/staging/brcm80211/brcmfmac/siutils.c b/drivers/staging/brcm80211/brcmfmac/siutils.c
deleted file mode 100644
index f428e99..0000000
--- a/drivers/staging/brcm80211/brcmfmac/siutils.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../util/siutils.c"
diff --git a/drivers/staging/brcm80211/brcmfmac/wl_cfg80211.c b/drivers/staging/brcm80211/brcmfmac/wl_cfg80211.c
index 7aaf99c..1827b0b 100644
--- a/drivers/staging/brcm80211/brcmfmac/wl_cfg80211.c
+++ b/drivers/staging/brcm80211/brcmfmac/wl_cfg80211.c
@@ -39,11 +39,13 @@
#include <linux/firmware.h>
#include <wl_cfg80211.h>
+void sdioh_sdio_set_host_pm_flags(int flag);
+
static struct sdio_func *cfg80211_sdio_func;
static struct wl_dev *wl_cfg80211_dev;
static const u8 ether_bcast[ETH_ALEN] = {255, 255, 255, 255, 255, 255};
-u32 wl_dbg_level = WL_DBG_ERR | WL_DBG_INFO;
+u32 wl_dbg_level = WL_DBG_ERR;
#define WL_4329_FW_FILE "brcm/bcm4329-fullmac-4.bin"
#define WL_4329_NVRAM_FILE "brcm/bcm4329-fullmac-4.txt"
@@ -180,41 +182,34 @@
** cfg80211 connect utilites
*/
static s32 wl_set_wpa_version(struct net_device *dev,
- struct cfg80211_connect_params *sme);
+ struct cfg80211_connect_params *sme);
static s32 wl_set_auth_type(struct net_device *dev,
- struct cfg80211_connect_params *sme);
+ struct cfg80211_connect_params *sme);
static s32 wl_set_set_cipher(struct net_device *dev,
- struct cfg80211_connect_params *sme);
+ struct cfg80211_connect_params *sme);
static s32 wl_set_key_mgmt(struct net_device *dev,
- struct cfg80211_connect_params *sme);
+ struct cfg80211_connect_params *sme);
static s32 wl_set_set_sharedkey(struct net_device *dev,
- struct cfg80211_connect_params *sme);
+ struct cfg80211_connect_params *sme);
static s32 wl_get_assoc_ies(struct wl_priv *wl);
+static void wl_clear_assoc_ies(struct wl_priv *wl);
static void wl_ch_to_chanspec(int ch,
struct wl_join_params *join_params, size_t *join_params_size);
/*
** information element utilities
*/
-static void wl_rst_ie(struct wl_priv *wl);
static __used s32 wl_add_ie(struct wl_priv *wl, u8 t, u8 l, u8 *v);
-static s32 wl_mrg_ie(struct wl_priv *wl, u8 *ie_stream, u16 ie_size);
-static s32 wl_cp_ie(struct wl_priv *wl, u8 *dst, u16 dst_size);
-static u32 wl_get_ielen(struct wl_priv *wl);
-
static s32 wl_mode_to_nl80211_iftype(s32 mode);
-
static struct wireless_dev *wl_alloc_wdev(s32 sizeof_iface,
- struct device *dev);
+ struct device *dev);
static void wl_free_wdev(struct wl_priv *wl);
-
static s32 wl_inform_bss(struct wl_priv *wl);
static s32 wl_inform_single_bss(struct wl_priv *wl, struct wl_bss_info *bi);
static s32 wl_update_bss_info(struct wl_priv *wl);
-
static s32 wl_add_keyext(struct wiphy *wiphy, struct net_device *dev,
- u8 key_idx, const u8 *mac_addr,
- struct key_params *params);
+ u8 key_idx, const u8 *mac_addr,
+ struct key_params *params);
/*
** key indianess swap utilities
@@ -240,7 +235,6 @@
** ibss mode utilities
*/
static bool wl_is_ibssmode(struct wl_priv *wl);
-static bool wl_is_ibssstarter(struct wl_priv *wl);
/*
** dongle up/down , default configuration utilities
@@ -248,7 +242,6 @@
static bool wl_is_linkdown(struct wl_priv *wl, const wl_event_msg_t *e);
static bool wl_is_linkup(struct wl_priv *wl, const wl_event_msg_t *e);
static bool wl_is_nonetwork(struct wl_priv *wl, const wl_event_msg_t *e);
-static void wl_link_up(struct wl_priv *wl);
static void wl_link_down(struct wl_priv *wl);
static s32 wl_dongle_mode(struct net_device *ndev, s32 iftype);
static s32 __wl_cfg80211_up(struct wl_priv *wl);
@@ -266,18 +259,19 @@
static s32 wl_dongle_power(struct net_device *ndev, u32 power_mode);
static s32 wl_dongle_glom(struct net_device *ndev, u32 glom,
u32 dongle_align);
-static s32 wl_dongle_roam(struct net_device *ndev, u32 roamvar,
- u32 bcn_timeout);
-static s32 wl_dongle_eventmsg(struct net_device *ndev);
-static s32 wl_dongle_scantime(struct net_device *ndev, s32 scan_assoc_time,
- s32 scan_unassoc_time);
static s32 wl_dongle_offload(struct net_device *ndev, s32 arpoe,
s32 arp_ol);
static s32 wl_pattern_atoh(s8 *src, s8 *dst);
static s32 wl_dongle_filter(struct net_device *ndev, u32 filter_mode);
static s32 wl_update_wiphybands(struct wl_priv *wl);
#endif /* !EMBEDDED_PLATFORM */
+
+static s32 wl_dongle_eventmsg(struct net_device *ndev);
+static s32 wl_dongle_scantime(struct net_device *ndev, s32 scan_assoc_time,
+ s32 scan_unassoc_time, s32 scan_passive_time);
static s32 wl_config_dongle(struct wl_priv *wl, bool need_lock);
+static s32 wl_dongle_roam(struct net_device *ndev, u32 roamvar,
+ u32 bcn_timeout);
/*
** iscan handler
@@ -352,30 +346,6 @@
} while (0)
extern int dhd_wait_pend8021x(struct net_device *dev);
-
-#if (WL_DBG_LEVEL > 0)
-#define WL_DBG_ESTR_MAX 32
-static s8 wl_dbg_estr[][WL_DBG_ESTR_MAX] = {
- "SET_SSID", "JOIN", "START", "AUTH", "AUTH_IND",
- "DEAUTH", "DEAUTH_IND", "ASSOC", "ASSOC_IND", "REASSOC",
- "REASSOC_IND", "DISASSOC", "DISASSOC_IND", "QUIET_START", "QUIET_END",
- "BEACON_RX", "LINK", "MIC_ERROR", "NDIS_LINK", "ROAM",
- "TXFAIL", "PMKID_CACHE", "RETROGRADE_TSF", "PRUNE", "AUTOAUTH",
- "EAPOL_MSG", "SCAN_COMPLETE", "ADDTS_IND", "DELTS_IND", "BCNSENT_IND",
- "BCNRX_MSG", "BCNLOST_MSG", "ROAM_PREP", "PFN_NET_FOUND",
- "PFN_NET_LOST",
- "RESET_COMPLETE", "JOIN_START", "ROAM_START", "ASSOC_START",
- "IBSS_ASSOC",
- "RADIO", "PSM_WATCHDOG",
- "PROBREQ_MSG",
- "SCAN_CONFIRM_IND", "PSK_SUP", "COUNTRY_CODE_CHANGED",
- "EXCEEDED_MEDIUM_TIME", "ICV_ERROR",
- "UNICAST_DECODE_ERROR", "MULTICAST_DECODE_ERROR", "TRACE",
- "IF",
- "RSSI", "PFN_SCAN_COMPLETE", "ACTION_FRAME", "ACTION_FRAME_COMPLETE",
-};
-#endif /* WL_DBG_LEVEL */
-
#define CHAN2G(_channel, _freq, _flags) { \
.band = IEEE80211_BAND_2GHZ, \
.center_freq = (_freq), \
@@ -604,10 +574,11 @@
struct wl_priv *wl = wiphy_to_wl(wiphy);
struct wireless_dev *wdev;
s32 infra = 0;
- s32 ap = 0;
s32 err = 0;
+ WL_TRACE("Enter\n");
CHECK_SYS_UP();
+
switch (type) {
case NL80211_IFTYPE_MONITOR:
case NL80211_IFTYPE_WDS:
@@ -616,32 +587,34 @@
return -EOPNOTSUPP;
case NL80211_IFTYPE_ADHOC:
wl->conf->mode = WL_MODE_IBSS;
+ infra = 0;
break;
case NL80211_IFTYPE_STATION:
wl->conf->mode = WL_MODE_BSS;
infra = 1;
break;
default:
- return -EINVAL;
+ err = -EINVAL;
+ goto done;
}
+
infra = cpu_to_le32(infra);
- ap = cpu_to_le32(ap);
- wdev = ndev->ieee80211_ptr;
- wdev->iftype = type;
- WL_DBG("%s : ap (%d), infra (%d)\n", ndev->name, ap, infra);
err = wl_dev_ioctl(ndev, WLC_SET_INFRA, &infra, sizeof(infra));
if (unlikely(err)) {
WL_ERR("WLC_SET_INFRA error (%d)\n", err);
- return err;
- }
- err = wl_dev_ioctl(ndev, WLC_SET_AP, &ap, sizeof(ap));
- if (unlikely(err)) {
- WL_ERR("WLC_SET_AP error (%d)\n", err);
- return err;
+ err = -EAGAIN;
+ } else {
+ wdev = ndev->ieee80211_ptr;
+ wdev->iftype = type;
}
- /* -EINPROGRESS: Call commit handler */
- return -EINPROGRESS;
+ WL_INFO("IF Type = %s\n",
+ (wl->conf->mode == WL_MODE_IBSS) ? "Adhoc" : "Infra");
+
+done:
+ WL_TRACE("Exit\n");
+
+ return err;
}
static void wl_iscan_prep(struct wl_scan_params *params, struct wlc_ssid *ssid)
@@ -740,7 +713,7 @@
err = wl_dev_ioctl(wl_to_ndev(wl), WLC_SET_PASSIVE_SCAN,
&passive_scan, sizeof(passive_scan));
if (unlikely(err)) {
- WL_DBG("error (%d)\n", err);
+ WL_ERR("error (%d)\n", err);
return err;
}
wl_set_mpc(ndev, 0);
@@ -774,26 +747,25 @@
(int)wl->status);
return -EAGAIN;
}
+ if (test_bit(WL_STATUS_CONNECTING, &wl->status)) {
+ WL_ERR("Connecting : status (%d)\n",
+ (int)wl->status);
+ return -EAGAIN;
+ }
iscan_req = false;
spec_scan = false;
- if (request) { /* scan bss */
+ if (request) {
+ /* scan bss */
ssids = request->ssids;
- if (wl->iscan_on && (!ssids || !ssids->ssid_len)) { /* for
- * specific scan,
- * ssids->ssid_len has
- * non-zero(ssid string)
- * length.
- * Otherwise this is 0.
- * we do not iscan for
- * specific scan request
- */
+ if (wl->iscan_on && (!ssids || !ssids->ssid_len))
iscan_req = true;
- }
- } else { /* scan in ibss */
+ } else {
+ /* scan in ibss */
/* we don't do iscan in ibss */
ssids = this_ssid;
}
+
wl->scan_request = request;
set_bit(WL_STATUS_SCANNING, &wl->status);
if (iscan_req) {
@@ -803,7 +775,7 @@
else
goto scan_out;
} else {
- WL_DBG("ssid \"%s\", ssid_len (%d)\n",
+ WL_SCAN("ssid \"%s\", ssid_len (%d)\n",
ssids->ssid, ssids->ssid_len);
memset(&sr->ssid, 0, sizeof(sr->ssid));
sr->ssid.SSID_len =
@@ -811,13 +783,11 @@
if (sr->ssid.SSID_len) {
memcpy(sr->ssid.SSID, ssids->ssid, sr->ssid.SSID_len);
sr->ssid.SSID_len = cpu_to_le32(sr->ssid.SSID_len);
- WL_DBG("Specific scan ssid=\"%s\" len=%d\n",
- sr->ssid.SSID, sr->ssid.SSID_len);
spec_scan = true;
} else {
- WL_DBG("Broadcast scan\n");
+ WL_SCAN("Broadcast scan\n");
}
- WL_DBG("sr->ssid.SSID_len (%d)\n", sr->ssid.SSID_len);
+
passive_scan = wl->active_scan ? 0 : 1;
err = wl_dev_ioctl(ndev, WLC_SET_PASSIVE_SCAN,
&passive_scan, sizeof(passive_scan));
@@ -854,13 +824,15 @@
{
s32 err = 0;
- CHECK_SYS_UP();
- err = __wl_cfg80211_scan(wiphy, ndev, request, NULL);
- if (unlikely(err)) {
- WL_DBG("scan error (%d)\n", err);
- return err;
- }
+ WL_TRACE("Enter\n");
+ CHECK_SYS_UP();
+
+ err = __wl_cfg80211_scan(wiphy, ndev, request, NULL);
+ if (unlikely(err))
+ WL_ERR("scan error (%d)\n", err);
+
+ WL_TRACE("Exit\n");
return err;
}
@@ -875,9 +847,8 @@
BUG_ON(!len);
err = wl_dev_ioctl(dev, WLC_SET_VAR, buf, len);
- if (unlikely(err)) {
+ if (unlikely(err))
WL_ERR("error (%d)\n", err);
- }
return err;
}
@@ -898,9 +869,9 @@
sizeof(var.buf));
BUG_ON(!len);
err = wl_dev_ioctl(dev, WLC_GET_VAR, &var, len);
- if (unlikely(err)) {
+ if (unlikely(err))
WL_ERR("error (%d)\n", err);
- }
+
*retval = le32_to_cpu(var.val);
return err;
@@ -911,10 +882,9 @@
s32 err = 0;
err = wl_dev_intvar_set(dev, "rtsthresh", rts_threshold);
- if (unlikely(err)) {
+ if (unlikely(err))
WL_ERR("Error (%d)\n", err);
- return err;
- }
+
return err;
}
@@ -923,10 +893,9 @@
s32 err = 0;
err = wl_dev_intvar_set(dev, "fragthresh", frag_threshold);
- if (unlikely(err)) {
+ if (unlikely(err))
WL_ERR("Error (%d)\n", err);
- return err;
- }
+
return err;
}
@@ -950,37 +919,40 @@
struct net_device *ndev = wl_to_ndev(wl);
s32 err = 0;
+ WL_TRACE("Enter\n");
CHECK_SYS_UP();
+
if (changed & WIPHY_PARAM_RTS_THRESHOLD &&
(wl->conf->rts_threshold != wiphy->rts_threshold)) {
wl->conf->rts_threshold = wiphy->rts_threshold;
err = wl_set_rts(ndev, wl->conf->rts_threshold);
if (!err)
- return err;
+ goto done;
}
if (changed & WIPHY_PARAM_FRAG_THRESHOLD &&
(wl->conf->frag_threshold != wiphy->frag_threshold)) {
wl->conf->frag_threshold = wiphy->frag_threshold;
err = wl_set_frag(ndev, wl->conf->frag_threshold);
if (!err)
- return err;
+ goto done;
}
if (changed & WIPHY_PARAM_RETRY_LONG
&& (wl->conf->retry_long != wiphy->retry_long)) {
wl->conf->retry_long = wiphy->retry_long;
err = wl_set_retry(ndev, wl->conf->retry_long, true);
if (!err)
- return err;
+ goto done;
}
if (changed & WIPHY_PARAM_RETRY_SHORT
&& (wl->conf->retry_short != wiphy->retry_short)) {
wl->conf->retry_short = wiphy->retry_short;
err = wl_set_retry(ndev, wl->conf->retry_short, false);
- if (!err) {
- return err;
- }
+ if (!err)
+ goto done;
}
+done:
+ WL_TRACE("Exit\n");
return err;
}
@@ -989,68 +961,139 @@
struct cfg80211_ibss_params *params)
{
struct wl_priv *wl = wiphy_to_wl(wiphy);
- struct cfg80211_bss *bss;
- struct ieee80211_channel *chan;
struct wl_join_params join_params;
- struct cfg80211_ssid ssid;
- s32 scan_retry = 0;
+ size_t join_params_size = 0;
s32 err = 0;
+ s32 wsec = 0;
+ s32 bcnprd;
+ WL_TRACE("Enter\n");
CHECK_SYS_UP();
- if (params->bssid) {
- WL_ERR("Invalid bssid\n");
+
+ if (params->ssid)
+ WL_CONN("SSID: %s\n", params->ssid);
+ else {
+ WL_CONN("SSID: NULL, Not supported\n");
return -EOPNOTSUPP;
}
- bss = cfg80211_get_ibss(wiphy, NULL, params->ssid, params->ssid_len);
- if (!bss) {
- memcpy(ssid.ssid, params->ssid, params->ssid_len);
- ssid.ssid_len = params->ssid_len;
- do {
- if (unlikely
- (__wl_cfg80211_scan(wiphy, dev, NULL, &ssid) ==
- -EBUSY)) {
- wl_delay(150);
- } else {
- break;
- }
- } while (++scan_retry < WL_SCAN_RETRY_MAX);
- rtnl_unlock(); /* to allow scan_inform to paropagate
- to cfg80211 plane */
- schedule_timeout_interruptible(4 * HZ); /* wait 4 secons
- till scan done.... */
- rtnl_lock();
- bss = cfg80211_get_ibss(wiphy, NULL,
- params->ssid, params->ssid_len);
- }
- if (bss) {
- wl->ibss_starter = false;
- WL_DBG("Found IBSS\n");
- } else {
- wl->ibss_starter = true;
- }
- chan = params->channel;
- if (chan)
- wl->channel = ieee80211_frequency_to_channel(chan->center_freq);
- /*
- ** Join with specific BSSID and cached SSID
- ** If SSID is zero join based on BSSID only
- */
- memset(&join_params, 0, sizeof(join_params));
- memcpy((void *)join_params.ssid.SSID, (void *)params->ssid,
- params->ssid_len);
- join_params.ssid.SSID_len = cpu_to_le32(params->ssid_len);
- if (params->bssid)
- memcpy(&join_params.params.bssid, params->bssid,
- ETH_ALEN);
- else
- memset(&join_params.params.bssid, 0, ETH_ALEN);
- err = wl_dev_ioctl(dev, WLC_SET_SSID, &join_params,
- sizeof(join_params));
+ if (params->bssid)
+ WL_CONN("BSSID: %02X %02X %02X %02X %02X %02X\n",
+ params->bssid[0], params->bssid[1], params->bssid[2],
+ params->bssid[3], params->bssid[4], params->bssid[5]);
+ else
+ WL_CONN("No BSSID specified\n");
+
+ if (params->channel)
+ WL_CONN("channel: %d\n", params->channel->center_freq);
+ else
+ WL_CONN("no channel specified\n");
+
+ if (params->channel_fixed)
+ WL_CONN("fixed channel required\n");
+ else
+ WL_CONN("no fixed channel required\n");
+
+ if (params->ie && params->ie_len)
+ WL_CONN("ie len: %d\n", params->ie_len);
+ else
+ WL_CONN("no ie specified\n");
+
+ if (params->beacon_interval)
+ WL_CONN("beacon interval: %d\n", params->beacon_interval);
+ else
+ WL_CONN("no beacon interval specified\n");
+
+ if (params->basic_rates)
+ WL_CONN("basic rates: %08X\n", params->basic_rates);
+ else
+ WL_CONN("no basic rates specified\n");
+
+ if (params->privacy)
+ WL_CONN("privacy required\n");
+ else
+ WL_CONN("no privacy required\n");
+
+ /* Configure Privacy for starter */
+ if (params->privacy)
+ wsec |= WEP_ENABLED;
+
+ err = wl_dev_intvar_set(dev, "wsec", wsec);
if (unlikely(err)) {
- WL_ERR("Error (%d)\n", err);
- return err;
+ WL_ERR("wsec failed (%d)\n", err);
+ goto done;
}
+
+ /* Configure Beacon Interval for starter */
+ if (params->beacon_interval)
+ bcnprd = cpu_to_le32(params->beacon_interval);
+ else
+ bcnprd = cpu_to_le32(100);
+
+ err = wl_dev_ioctl(dev, WLC_SET_BCNPRD, &bcnprd, sizeof(bcnprd));
+ if (unlikely(err)) {
+ WL_ERR("WLC_SET_BCNPRD failed (%d)\n", err);
+ goto done;
+ }
+
+ /* Configure required join parameter */
+ memset(&join_params, 0, sizeof(wl_join_params_t));
+
+ /* SSID */
+ join_params.ssid.SSID_len =
+ (params->ssid_len > 32) ? 32 : params->ssid_len;
+ memcpy(join_params.ssid.SSID, params->ssid, join_params.ssid.SSID_len);
+ join_params.ssid.SSID_len = cpu_to_le32(join_params.ssid.SSID_len);
+ join_params_size = sizeof(join_params.ssid);
+ wl_update_prof(wl, NULL, &join_params.ssid, WL_PROF_SSID);
+
+ /* BSSID */
+ if (params->bssid) {
+ memcpy(join_params.params.bssid, params->bssid, ETH_ALEN);
+ join_params_size =
+ sizeof(join_params.ssid) + WL_ASSOC_PARAMS_FIXED_SIZE;
+ } else {
+ memcpy(join_params.params.bssid, ether_bcast, ETH_ALEN);
+ }
+ wl_update_prof(wl, NULL, &join_params.params.bssid, WL_PROF_BSSID);
+
+ /* Channel */
+ if (params->channel) {
+ u32 target_channel;
+
+ wl->channel =
+ ieee80211_frequency_to_channel(
+ params->channel->center_freq);
+ if (params->channel_fixed) {
+ /* adding chanspec */
+ wl_ch_to_chanspec(wl->channel,
+ &join_params, &join_params_size);
+ }
+
+ /* set channel for starter */
+ target_channel = cpu_to_le32(wl->channel);
+ err = wl_dev_ioctl(dev, WLC_SET_CHANNEL,
+ &target_channel, sizeof(target_channel));
+ if (unlikely(err)) {
+ WL_ERR("WLC_SET_CHANNEL failed (%d)\n", err);
+ goto done;
+ }
+ } else
+ wl->channel = 0;
+
+ wl->ibss_starter = false;
+
+
+ err = wl_dev_ioctl(dev, WLC_SET_SSID, &join_params, join_params_size);
+ if (unlikely(err)) {
+ WL_ERR("WLC_SET_SSID failed (%d)\n", err);
+ goto done;
+ }
+
+ set_bit(WL_STATUS_CONNECTING, &wl->status);
+
+done:
+ WL_TRACE("Exit\n");
return err;
}
@@ -1059,9 +1102,13 @@
struct wl_priv *wl = wiphy_to_wl(wiphy);
s32 err = 0;
+ WL_TRACE("Enter\n");
CHECK_SYS_UP();
+
wl_link_down(wl);
+ WL_TRACE("Exit\n");
+
return err;
}
@@ -1079,7 +1126,7 @@
val = WPA2_AUTH_PSK | WPA2_AUTH_UNSPECIFIED;
else
val = WPA_AUTH_DISABLED;
- WL_DBG("setting wpa_auth to 0x%0x\n", val);
+ WL_CONN("setting wpa_auth to 0x%0x\n", val);
err = wl_dev_intvar_set(dev, "wpa_auth", val);
if (unlikely(err)) {
WL_ERR("set wpa_auth failed (%d)\n", err);
@@ -1101,18 +1148,18 @@
switch (sme->auth_type) {
case NL80211_AUTHTYPE_OPEN_SYSTEM:
val = 0;
- WL_DBG("open system\n");
+ WL_CONN("open system\n");
break;
case NL80211_AUTHTYPE_SHARED_KEY:
val = 1;
- WL_DBG("shared key\n");
+ WL_CONN("shared key\n");
break;
case NL80211_AUTHTYPE_AUTOMATIC:
val = 2;
- WL_DBG("automatic\n");
+ WL_CONN("automatic\n");
break;
case NL80211_AUTHTYPE_NETWORK_EAP:
- WL_DBG("network eap\n");
+ WL_CONN("network eap\n");
default:
val = 2;
WL_ERR("invalid auth type (%d)\n", sme->auth_type);
@@ -1181,7 +1228,7 @@
}
}
- WL_DBG("pval (%d) gval (%d)\n", pval, gval);
+ WL_CONN("pval (%d) gval (%d)\n", pval, gval);
err = wl_dev_intvar_set(dev, "wsec", pval | gval);
if (unlikely(err)) {
WL_ERR("error (%d)\n", err);
@@ -1237,7 +1284,7 @@
}
}
- WL_DBG("setting wpa_auth to %d\n", val);
+ WL_CONN("setting wpa_auth to %d\n", val);
err = wl_dev_intvar_set(dev, "wpa_auth", val);
if (unlikely(err)) {
WL_ERR("could not set wpa_auth (%d)\n", err);
@@ -1260,10 +1307,10 @@
s32 val;
s32 err = 0;
- WL_DBG("key len (%d)\n", sme->key_len);
+ WL_CONN("key len (%d)\n", sme->key_len);
if (sme->key_len) {
sec = wl_read_prof(wl, WL_PROF_SEC);
- WL_DBG("wpa_versions 0x%x cipher_pairwise 0x%x\n",
+ WL_CONN("wpa_versions 0x%x cipher_pairwise 0x%x\n",
sec->wpa_versions, sec->cipher_pairwise);
if (!
(sec->wpa_versions & (NL80211_WPA_VERSION_1 |
@@ -1292,9 +1339,9 @@
return -EINVAL;
}
/* Set the new key/index */
- WL_DBG("key length (%d) key index (%d) algo (%d)\n",
+ WL_CONN("key length (%d) key index (%d) algo (%d)\n",
key.len, key.index, key.algo);
- WL_DBG("key \"%s\"\n", key.data);
+ WL_CONN("key \"%s\"\n", key.data);
swap_key_from_BE(&key);
err = wl_dev_ioctl(dev, WLC_SET_KEY, &key,
sizeof(key));
@@ -1303,7 +1350,7 @@
return err;
}
if (sec->auth_type == NL80211_AUTHTYPE_OPEN_SYSTEM) {
- WL_DBG("set auth_type to shared key\n");
+ WL_CONN("set auth_type to shared key\n");
val = 1; /* shared key */
err = wl_dev_intvar_set(dev, "auth", val);
if (unlikely(err)) {
@@ -1327,17 +1374,24 @@
s32 err = 0;
+ WL_TRACE("Enter\n");
CHECK_SYS_UP();
+
if (unlikely(!sme->ssid)) {
WL_ERR("Invalid ssid\n");
return -EOPNOTSUPP;
}
+
if (chan) {
- wl->channel = ieee80211_frequency_to_channel(chan->center_freq);
- WL_DBG("channel (%d), center_req (%d)\n",
- wl->channel, chan->center_freq);
- }
- WL_DBG("ie (%p), ie_len (%zd)\n", sme->ie, sme->ie_len);
+ wl->channel =
+ ieee80211_frequency_to_channel(chan->center_freq);
+ WL_CONN("channel (%d), center_req (%d)\n",
+ wl->channel, chan->center_freq);
+ } else
+ wl->channel = 0;
+
+ WL_INFO("ie (%p), ie_len (%zd)\n", sme->ie, sme->ie_len);
+
err = wl_set_wpa_version(dev, sme);
if (unlikely(err))
return err;
@@ -1370,15 +1424,18 @@
memcpy(&join_params.ssid.SSID, sme->ssid, join_params.ssid.SSID_len);
join_params.ssid.SSID_len = cpu_to_le32(join_params.ssid.SSID_len);
wl_update_prof(wl, NULL, &join_params.ssid, WL_PROF_SSID);
- memcpy(join_params.params.bssid, ether_bcast, ETH_ALEN);
- wl_ch_to_chanspec(wl->channel, &join_params, &join_params_size);
- WL_DBG("join_param_size %zu\n", join_params_size);
+ if (sme->bssid)
+ memcpy(join_params.params.bssid, sme->bssid, ETH_ALEN);
+ else
+ memcpy(join_params.params.bssid, ether_bcast, ETH_ALEN);
if (join_params.ssid.SSID_len < IEEE80211_MAX_SSID_LEN) {
- WL_DBG("ssid \"%s\", len (%d)\n",
+ WL_CONN("ssid \"%s\", len (%d)\n",
join_params.ssid.SSID, join_params.ssid.SSID_len);
}
+
+ wl_ch_to_chanspec(wl->channel, &join_params, &join_params_size);
err = wl_dev_ioctl(dev, WLC_SET_SSID, &join_params, join_params_size);
if (unlikely(err)) {
WL_ERR("error (%d)\n", err);
@@ -1386,6 +1443,7 @@
}
set_bit(WL_STATUS_CONNECTING, &wl->status);
+ WL_TRACE("Exit\n");
return err;
}
@@ -1395,24 +1453,24 @@
{
struct wl_priv *wl = wiphy_to_wl(wiphy);
scb_val_t scbval;
- bool act = false;
s32 err = 0;
- WL_DBG("Reason %d\n", reason_code);
+ WL_TRACE("Enter. Reason code = %d\n", reason_code);
CHECK_SYS_UP();
- act = *(bool *) wl_read_prof(wl, WL_PROF_ACT);
- if (likely(act)) {
- scbval.val = reason_code;
- memcpy(&scbval.ea, &wl->bssid, ETH_ALEN);
- scbval.val = cpu_to_le32(scbval.val);
- err = wl_dev_ioctl(dev, WLC_DISASSOC, &scbval,
- sizeof(scb_val_t));
- if (unlikely(err)) {
- WL_ERR("error (%d)\n", err);
- return err;
- }
- }
+ clear_bit(WL_STATUS_CONNECTED, &wl->status);
+
+ scbval.val = reason_code;
+ memcpy(&scbval.ea, wl_read_prof(wl, WL_PROF_BSSID), ETH_ALEN);
+ scbval.val = cpu_to_le32(scbval.val);
+ err = wl_dev_ioctl(dev, WLC_DISASSOC, &scbval,
+ sizeof(scb_val_t));
+ if (unlikely(err))
+ WL_ERR("error (%d)\n", err);
+
+ wl->link_up = false;
+
+ WL_TRACE("Exit\n");
return err;
}
@@ -1427,20 +1485,24 @@
s32 err = 0;
s32 disable = 0;
+ WL_TRACE("Enter\n");
CHECK_SYS_UP();
+
switch (type) {
case NL80211_TX_POWER_AUTOMATIC:
break;
case NL80211_TX_POWER_LIMITED:
if (dbm < 0) {
WL_ERR("TX_POWER_LIMITED - dbm is negative\n");
- return -EINVAL;
+ err = -EINVAL;
+ goto done;
}
break;
case NL80211_TX_POWER_FIXED:
if (dbm < 0) {
WL_ERR("TX_POWER_FIXED - dbm is negative\n");
- return -EINVAL;
+ err = -EINVAL;
+ goto done;
}
break;
}
@@ -1448,10 +1510,8 @@
disable = WL_RADIO_SW_DISABLE << 16;
disable = cpu_to_le32(disable);
err = wl_dev_ioctl(ndev, WLC_SET_RADIO, &disable, sizeof(disable));
- if (unlikely(err)) {
+ if (unlikely(err))
WL_ERR("WLC_SET_RADIO error (%d)\n", err);
- return err;
- }
if (dbm > 0xffff)
txpwrmw = 0xffff;
@@ -1459,12 +1519,12 @@
txpwrmw = (u16) dbm;
err = wl_dev_intvar_set(ndev, "qtxpower",
(s32) (bcm_mw_to_qdbm(txpwrmw)));
- if (unlikely(err)) {
+ if (unlikely(err))
WL_ERR("qtxpower error (%d)\n", err);
- return err;
- }
wl->conf->tx_power = dbm;
+done:
+ WL_TRACE("Exit\n");
return err;
}
@@ -1476,15 +1536,20 @@
u8 result;
s32 err = 0;
+ WL_TRACE("Enter\n");
CHECK_SYS_UP();
+
err = wl_dev_intvar_get(ndev, "qtxpower", &txpwrdbm);
if (unlikely(err)) {
WL_ERR("error (%d)\n", err);
- return err;
+ goto done;
}
+
result = (u8) (txpwrdbm & ~WL_TXPWR_OVERRIDE);
*dbm = (s32) bcm_qdbm_to_mw(result);
+done:
+ WL_TRACE("Exit\n");
return err;
}
@@ -1496,14 +1561,16 @@
s32 wsec;
s32 err = 0;
- WL_DBG("key index (%d)\n", key_idx);
+ WL_TRACE("Enter\n");
+ WL_CONN("key index (%d)\n", key_idx);
CHECK_SYS_UP();
err = wl_dev_ioctl(dev, WLC_GET_WSEC, &wsec, sizeof(wsec));
if (unlikely(err)) {
WL_ERR("WLC_GET_WSEC error (%d)\n", err);
- return err;
+ goto done;
}
+
wsec = le32_to_cpu(wsec);
if (wsec & WEP_ENABLED) {
/* Just select a new current key */
@@ -1511,10 +1578,11 @@
index = cpu_to_le32(index);
err = wl_dev_ioctl(dev, WLC_SET_KEY_PRIMARY, &index,
sizeof(index));
- if (unlikely(err)) {
+ if (unlikely(err))
WL_ERR("error (%d)\n", err);
- }
}
+done:
+ WL_TRACE("Exit\n");
return err;
}
@@ -1547,7 +1615,7 @@
return -EINVAL;
}
- WL_DBG("Setting the key index %d\n", key.index);
+ WL_CONN("Setting the key index %d\n", key.index);
memcpy(key.data, params->key, key.len);
if (params->cipher == WLAN_CIPHER_SUITE_TKIP) {
@@ -1571,23 +1639,23 @@
switch (params->cipher) {
case WLAN_CIPHER_SUITE_WEP40:
key.algo = CRYPTO_ALGO_WEP1;
- WL_DBG("WLAN_CIPHER_SUITE_WEP40\n");
+ WL_CONN("WLAN_CIPHER_SUITE_WEP40\n");
break;
case WLAN_CIPHER_SUITE_WEP104:
key.algo = CRYPTO_ALGO_WEP128;
- WL_DBG("WLAN_CIPHER_SUITE_WEP104\n");
+ WL_CONN("WLAN_CIPHER_SUITE_WEP104\n");
break;
case WLAN_CIPHER_SUITE_TKIP:
key.algo = CRYPTO_ALGO_TKIP;
- WL_DBG("WLAN_CIPHER_SUITE_TKIP\n");
+ WL_CONN("WLAN_CIPHER_SUITE_TKIP\n");
break;
case WLAN_CIPHER_SUITE_AES_CMAC:
key.algo = CRYPTO_ALGO_AES_CCM;
- WL_DBG("WLAN_CIPHER_SUITE_AES_CMAC\n");
+ WL_CONN("WLAN_CIPHER_SUITE_AES_CMAC\n");
break;
case WLAN_CIPHER_SUITE_CCMP:
key.algo = CRYPTO_ALGO_AES_CCM;
- WL_DBG("WLAN_CIPHER_SUITE_CCMP\n");
+ WL_CONN("WLAN_CIPHER_SUITE_CCMP\n");
break;
default:
WL_ERR("Invalid cipher (0x%x)\n", params->cipher);
@@ -1614,12 +1682,16 @@
s32 val;
s32 wsec;
s32 err = 0;
+ u8 keybuf[8];
- WL_DBG("key index (%d)\n", key_idx);
+ WL_TRACE("Enter\n");
+ WL_CONN("key index (%d)\n", key_idx);
CHECK_SYS_UP();
- if (mac_addr)
+ if (mac_addr) {
+ WL_TRACE("Exit");
return wl_add_keyext(wiphy, dev, key_idx, mac_addr, params);
+ }
memset(&key, 0, sizeof(key));
key.len = (u32) params->key_len;
@@ -1627,7 +1699,8 @@
if (unlikely(key.len > sizeof(key.data))) {
WL_ERR("Too long key length (%u)\n", key.len);
- return -EINVAL;
+ err = -EINVAL;
+ goto done;
}
memcpy(key.data, params->key, key.len);
@@ -1635,27 +1708,31 @@
switch (params->cipher) {
case WLAN_CIPHER_SUITE_WEP40:
key.algo = CRYPTO_ALGO_WEP1;
- WL_DBG("WLAN_CIPHER_SUITE_WEP40\n");
+ WL_CONN("WLAN_CIPHER_SUITE_WEP40\n");
break;
case WLAN_CIPHER_SUITE_WEP104:
key.algo = CRYPTO_ALGO_WEP128;
- WL_DBG("WLAN_CIPHER_SUITE_WEP104\n");
+ WL_CONN("WLAN_CIPHER_SUITE_WEP104\n");
break;
case WLAN_CIPHER_SUITE_TKIP:
+ memcpy(keybuf, &key.data[24], sizeof(keybuf));
+ memcpy(&key.data[24], &key.data[16], sizeof(keybuf));
+ memcpy(&key.data[16], keybuf, sizeof(keybuf));
key.algo = CRYPTO_ALGO_TKIP;
- WL_DBG("WLAN_CIPHER_SUITE_TKIP\n");
+ WL_CONN("WLAN_CIPHER_SUITE_TKIP\n");
break;
case WLAN_CIPHER_SUITE_AES_CMAC:
key.algo = CRYPTO_ALGO_AES_CCM;
- WL_DBG("WLAN_CIPHER_SUITE_AES_CMAC\n");
+ WL_CONN("WLAN_CIPHER_SUITE_AES_CMAC\n");
break;
case WLAN_CIPHER_SUITE_CCMP:
key.algo = CRYPTO_ALGO_AES_CCM;
- WL_DBG("WLAN_CIPHER_SUITE_CCMP\n");
+ WL_CONN("WLAN_CIPHER_SUITE_CCMP\n");
break;
default:
WL_ERR("Invalid cipher (0x%x)\n", params->cipher);
- return -EINVAL;
+ err = -EINVAL;
+ goto done;
}
/* Set the new key/index */
@@ -1663,30 +1740,30 @@
err = wl_dev_ioctl(dev, WLC_SET_KEY, &key, sizeof(key));
if (unlikely(err)) {
WL_ERR("WLC_SET_KEY error (%d)\n", err);
- return err;
+ goto done;
}
val = WEP_ENABLED;
err = wl_dev_intvar_get(dev, "wsec", &wsec);
if (unlikely(err)) {
WL_ERR("get wsec error (%d)\n", err);
- return err;
+ goto done;
}
wsec &= ~(WEP_ENABLED);
wsec |= val;
err = wl_dev_intvar_set(dev, "wsec", wsec);
if (unlikely(err)) {
WL_ERR("set wsec error (%d)\n", err);
- return err;
+ goto done;
}
val = 1; /* assume shared key. otherwise 0 */
val = cpu_to_le32(val);
err = wl_dev_ioctl(dev, WLC_SET_AUTH, &val, sizeof(val));
- if (unlikely(err)) {
+ if (unlikely(err))
WL_ERR("WLC_SET_AUTH error (%d)\n", err);
- return err;
- }
+done:
+ WL_TRACE("Exit\n");
return err;
}
@@ -1699,6 +1776,7 @@
s32 val;
s32 wsec;
+ WL_TRACE("Enter\n");
CHECK_SYS_UP();
memset(&key, 0, sizeof(key));
@@ -1706,34 +1784,39 @@
key.flags = WL_PRIMARY_KEY;
key.algo = CRYPTO_ALGO_OFF;
- WL_DBG("key index (%d)\n", key_idx);
+ WL_CONN("key index (%d)\n", key_idx);
/* Set the new key/index */
swap_key_from_BE(&key);
err = wl_dev_ioctl(dev, WLC_SET_KEY, &key, sizeof(key));
if (unlikely(err)) {
if (err == -EINVAL) {
- if (key.index >= DOT11_MAX_DEFAULT_KEYS) {
+ if (key.index >= DOT11_MAX_DEFAULT_KEYS)
/* we ignore this key index in this case */
- WL_DBG("invalid key index (%d)\n", key_idx);
- }
- } else {
+ WL_ERR("invalid key index (%d)\n", key_idx);
+ } else
WL_ERR("WLC_SET_KEY error (%d)\n", err);
- }
- return err;
+
+ /* Ignore this error, may happen during DISASSOC */
+ err = -EAGAIN;
+ goto done;
}
val = 0;
err = wl_dev_intvar_get(dev, "wsec", &wsec);
if (unlikely(err)) {
WL_ERR("get wsec error (%d)\n", err);
- return err;
+ /* Ignore this error, may happen during DISASSOC */
+ err = -EAGAIN;
+ goto done;
}
wsec &= ~(WEP_ENABLED);
wsec |= val;
err = wl_dev_intvar_set(dev, "wsec", wsec);
if (unlikely(err)) {
WL_ERR("set wsec error (%d)\n", err);
- return err;
+ /* Ignore this error, may happen during DISASSOC */
+ err = -EAGAIN;
+ goto done;
}
val = 0; /* assume open key. otherwise 1 */
@@ -1741,8 +1824,11 @@
err = wl_dev_ioctl(dev, WLC_SET_AUTH, &val, sizeof(val));
if (unlikely(err)) {
WL_ERR("WLC_SET_AUTH error (%d)\n", err);
- return err;
+ /* Ignore this error, may happen during DISASSOC */
+ err = -EAGAIN;
}
+done:
+ WL_TRACE("Exit\n");
return err;
}
@@ -1758,7 +1844,8 @@
s32 wsec;
s32 err = 0;
- WL_DBG("key index (%d)\n", key_idx);
+ WL_TRACE("Enter\n");
+ WL_CONN("key index (%d)\n", key_idx);
CHECK_SYS_UP();
memset(&key, 0, sizeof(key));
@@ -1771,7 +1858,9 @@
err = wl_dev_ioctl(dev, WLC_GET_WSEC, &wsec, sizeof(wsec));
if (unlikely(err)) {
WL_ERR("WLC_GET_WSEC error (%d)\n", err);
- return err;
+ /* Ignore this error, may happen during DISASSOC */
+ err = -EAGAIN;
+ goto done;
}
wsec = le32_to_cpu(wsec);
switch (wsec) {
@@ -1779,26 +1868,29 @@
sec = wl_read_prof(wl, WL_PROF_SEC);
if (sec->cipher_pairwise & WLAN_CIPHER_SUITE_WEP40) {
params.cipher = WLAN_CIPHER_SUITE_WEP40;
- WL_DBG("WLAN_CIPHER_SUITE_WEP40\n");
+ WL_CONN("WLAN_CIPHER_SUITE_WEP40\n");
} else if (sec->cipher_pairwise & WLAN_CIPHER_SUITE_WEP104) {
params.cipher = WLAN_CIPHER_SUITE_WEP104;
- WL_DBG("WLAN_CIPHER_SUITE_WEP104\n");
+ WL_CONN("WLAN_CIPHER_SUITE_WEP104\n");
}
break;
case TKIP_ENABLED:
params.cipher = WLAN_CIPHER_SUITE_TKIP;
- WL_DBG("WLAN_CIPHER_SUITE_TKIP\n");
+ WL_CONN("WLAN_CIPHER_SUITE_TKIP\n");
break;
case AES_ENABLED:
params.cipher = WLAN_CIPHER_SUITE_AES_CMAC;
- WL_DBG("WLAN_CIPHER_SUITE_AES_CMAC\n");
+ WL_CONN("WLAN_CIPHER_SUITE_AES_CMAC\n");
break;
default:
WL_ERR("Invalid algo (0x%x)\n", wsec);
- return -EINVAL;
+ err = -EINVAL;
+ goto done;
}
-
callback(cookie, ¶ms);
+
+done:
+ WL_TRACE("Exit\n");
return err;
}
@@ -1807,6 +1899,7 @@
struct net_device *dev, u8 key_idx)
{
WL_INFO("Not supported\n");
+
CHECK_SYS_UP();
return -EOPNOTSUPP;
}
@@ -1820,12 +1913,20 @@
int rssi;
s32 rate;
s32 err = 0;
+ u8 *bssid = wl_read_prof(wl, WL_PROF_BSSID);
+ WL_TRACE("Enter\n");
CHECK_SYS_UP();
+
if (unlikely
- (memcmp(mac, wl_read_prof(wl, WL_PROF_BSSID), ETH_ALEN))) {
- WL_ERR("Wrong Mac address\n");
- return -ENOENT;
+ (memcmp(mac, bssid, ETH_ALEN))) {
+ WL_ERR("Wrong Mac address cfg_mac-%X:%X:%X:%X:%X:%X"
+ "wl_bssid-%X:%X:%X:%X:%X:%X\n",
+ mac[0], mac[1], mac[2], mac[3], mac[4], mac[5],
+ bssid[0], bssid[1], bssid[2], bssid[3],
+ bssid[4], bssid[5]);
+ err = -ENOENT;
+ goto done;
}
/* Report the current tx rate */
@@ -1836,7 +1937,7 @@
rate = le32_to_cpu(rate);
sinfo->filled |= STATION_INFO_TX_BITRATE;
sinfo->txrate.legacy = rate * 5;
- WL_DBG("Rate %d Mbps\n", rate / 2);
+ WL_CONN("Rate %d Mbps\n", rate / 2);
}
if (test_bit(WL_STATUS_CONNECTED, &wl->status)) {
@@ -1845,14 +1946,15 @@
sizeof(scb_val_t));
if (unlikely(err)) {
WL_ERR("Could not get rssi (%d)\n", err);
- return err;
}
rssi = le32_to_cpu(scb_val.val);
sinfo->filled |= STATION_INFO_SIGNAL;
sinfo->signal = rssi;
- WL_DBG("RSSI %d dBm\n", rssi);
+ WL_CONN("RSSI %d dBm\n", rssi);
}
+done:
+ WL_TRACE("Exit\n");
return err;
}
@@ -1863,18 +1965,21 @@
s32 pm;
s32 err = 0;
+ WL_TRACE("Enter\n");
CHECK_SYS_UP();
+
pm = enabled ? PM_FAST : PM_OFF;
pm = cpu_to_le32(pm);
- WL_DBG("power save %s\n", (pm ? "enabled" : "disabled"));
+ WL_INFO("power save %s\n", (pm ? "enabled" : "disabled"));
+
err = wl_dev_ioctl(dev, WLC_SET_PM, &pm, sizeof(pm));
if (unlikely(err)) {
if (err == -ENODEV)
- WL_DBG("net_device is not ready yet\n");
+ WL_ERR("net_device is not ready yet\n");
else
WL_ERR("error (%d)\n", err);
- return err;
}
+ WL_TRACE("Exit\n");
return err;
}
@@ -1918,14 +2023,16 @@
u32 legacy;
s32 err = 0;
+ WL_TRACE("Enter\n");
CHECK_SYS_UP();
+
/* addr param is always NULL. ignore it */
/* Get current rateset */
err = wl_dev_ioctl(dev, WLC_GET_CURR_RATESET, &rateset,
sizeof(rateset));
if (unlikely(err)) {
WL_ERR("could not get current rateset (%d)\n", err);
- return err;
+ goto done;
}
rateset.count = le32_to_cpu(rateset.count);
@@ -1936,15 +2043,14 @@
val = wl_g_rates[legacy - 1].bitrate * 100000;
- if (val < rateset.count) {
+ if (val < rateset.count)
/* Select rate by rateset index */
rate = rateset.rates[val] & 0x7f;
- } else {
+ else
/* Specified rate in bps */
rate = val / 500000;
- }
- WL_DBG("rate %d mbps\n", rate / 2);
+ WL_CONN("rate %d mbps\n", rate / 2);
/*
*
@@ -1955,40 +2061,105 @@
err_a = wl_dev_intvar_set(dev, "a_rate", rate);
if (unlikely(err_bg && err_a)) {
WL_ERR("could not set fixed rate (%d) (%d)\n", err_bg, err_a);
- return err_bg | err_a;
+ err = err_bg | err_a;
}
+done:
+ WL_TRACE("Exit\n");
return err;
}
static s32 wl_cfg80211_resume(struct wiphy *wiphy)
{
- s32 err = 0;
+ struct wl_priv *wl = wiphy_to_wl(wiphy);
+ struct net_device *ndev = wl_to_ndev(wl);
- CHECK_SYS_UP();
- wl_invoke_iscan(wiphy_to_wl(wiphy));
+ /*
+ * Check for WL_STATUS_READY before any function call which
+ * could result is bus access. Don't block the resume for
+ * any driver error conditions
+ */
+ WL_TRACE("Enter\n");
- return err;
+#if defined(CONFIG_PM_SLEEP)
+ atomic_set(&dhd_mmc_suspend, false);
+#endif /* defined(CONFIG_PM_SLEEP) */
+
+ if (test_bit(WL_STATUS_READY, &wl->status)) {
+ /* Turn on Watchdog timer */
+ wl_os_wd_timer(ndev, dhd_watchdog_ms);
+ wl_invoke_iscan(wiphy_to_wl(wiphy));
+ }
+
+ WL_TRACE("Exit\n");
+ return 0;
}
static s32 wl_cfg80211_suspend(struct wiphy *wiphy)
{
struct wl_priv *wl = wiphy_to_wl(wiphy);
struct net_device *ndev = wl_to_ndev(wl);
- s32 err = 0;
+
+ WL_TRACE("Enter\n");
+
+ /*
+ * Check for WL_STATUS_READY before any function call which
+ * could result is bus access. Don't block the suspend for
+ * any driver error conditions
+ */
+
+ /*
+ * While going to suspend if associated with AP disassociate
+ * from AP to save power while system is in suspended state
+ */
+ if (test_bit(WL_STATUS_CONNECTED, &wl->status) &&
+ test_bit(WL_STATUS_READY, &wl->status)) {
+ WL_INFO("Disassociating from AP"
+ " while entering suspend state\n");
+ wl_link_down(wl);
+
+ /*
+ * Make sure WPA_Supplicant receives all the event
+ * generated due to DISASSOC call to the fw to keep
+ * the state fw and WPA_Supplicant state consistent
+ */
+ rtnl_unlock();
+ wl_delay(500);
+ rtnl_lock();
+ }
set_bit(WL_STATUS_SCAN_ABORTING, &wl->status);
- wl_term_iscan(wl);
+ if (test_bit(WL_STATUS_READY, &wl->status))
+ wl_term_iscan(wl);
+
if (wl->scan_request) {
- cfg80211_scan_done(wl->scan_request, true); /* true means
- abort */
- wl_set_mpc(ndev, 1);
+ /* Indidate scan abort to cfg80211 layer */
+ WL_INFO("Terminating scan in progress\n");
+ cfg80211_scan_done(wl->scan_request, true);
wl->scan_request = NULL;
}
clear_bit(WL_STATUS_SCANNING, &wl->status);
clear_bit(WL_STATUS_SCAN_ABORTING, &wl->status);
+ clear_bit(WL_STATUS_CONNECTING, &wl->status);
+ clear_bit(WL_STATUS_CONNECTED, &wl->status);
- return err;
+ /* Inform SDIO stack not to switch off power to the chip */
+ sdioh_sdio_set_host_pm_flags(MMC_PM_KEEP_POWER);
+
+ /* Turn off watchdog timer */
+ if (test_bit(WL_STATUS_READY, &wl->status)) {
+ WL_INFO("Terminate watchdog timer and enable MPC\n");
+ wl_set_mpc(ndev, 1);
+ wl_os_wd_timer(ndev, 0);
+ }
+
+#if defined(CONFIG_PM_SLEEP)
+ atomic_set(&dhd_mmc_suspend, true);
+#endif /* defined(CONFIG_PM_SLEEP) */
+
+ WL_TRACE("Exit\n");
+
+ return 0;
}
static __used s32
@@ -1997,18 +2168,17 @@
{
int i, j;
- WL_DBG("No of elements %d\n", pmk_list->pmkids.npmkid);
+ WL_CONN("No of elements %d\n", pmk_list->pmkids.npmkid);
for (i = 0; i < pmk_list->pmkids.npmkid; i++) {
- WL_DBG("PMKID[%d]: %pM =\n", i,
+ WL_CONN("PMKID[%d]: %pM =\n", i,
&pmk_list->pmkids.pmkid[i].BSSID);
- for (j = 0; j < WLAN_PMKID_LEN; j++) {
- WL_DBG("%02x\n", pmk_list->pmkids.pmkid[i].PMKID[j]);
- }
+ for (j = 0; j < WLAN_PMKID_LEN; j++)
+ WL_CONN("%02x\n", pmk_list->pmkids.pmkid[i].PMKID[j]);
}
- if (likely(!err)) {
- err = wl_dev_bufvar_set(dev, "pmkid_info", (char *)pmk_list,
+
+ if (likely(!err))
+ wl_dev_bufvar_set(dev, "pmkid_info", (char *)pmk_list,
sizeof(*pmk_list));
- }
return err;
}
@@ -2021,7 +2191,9 @@
s32 err = 0;
int i;
+ WL_TRACE("Enter\n");
CHECK_SYS_UP();
+
for (i = 0; i < wl->pmk_list->pmkids.npmkid; i++)
if (!memcmp(pmksa->bssid, &wl->pmk_list->pmkids.pmkid[i].BSSID,
ETH_ALEN))
@@ -2033,19 +2205,19 @@
WLAN_PMKID_LEN);
if (i == wl->pmk_list->pmkids.npmkid)
wl->pmk_list->pmkids.npmkid++;
- } else {
+ } else
err = -EINVAL;
- }
- WL_DBG("set_pmksa,IW_PMKSA_ADD - PMKID: %pM =\n",
+
+ WL_CONN("set_pmksa,IW_PMKSA_ADD - PMKID: %pM =\n",
&wl->pmk_list->pmkids.pmkid[wl->pmk_list->pmkids.npmkid].BSSID);
- for (i = 0; i < WLAN_PMKID_LEN; i++) {
- WL_DBG("%02x\n",
+ for (i = 0; i < WLAN_PMKID_LEN; i++)
+ WL_CONN("%02x\n",
wl->pmk_list->pmkids.pmkid[wl->pmk_list->pmkids.npmkid].
PMKID[i]);
- }
err = wl_update_pmklist(dev, wl->pmk_list, err);
+ WL_TRACE("Exit\n");
return err;
}
@@ -2058,15 +2230,15 @@
s32 err = 0;
int i;
+ WL_TRACE("Enter\n");
CHECK_SYS_UP();
memcpy(&pmkid.pmkid[0].BSSID, pmksa->bssid, ETH_ALEN);
memcpy(&pmkid.pmkid[0].PMKID, pmksa->pmkid, WLAN_PMKID_LEN);
- WL_DBG("del_pmksa,IW_PMKSA_REMOVE - PMKID: %pM =\n",
+ WL_CONN("del_pmksa,IW_PMKSA_REMOVE - PMKID: %pM =\n",
&pmkid.pmkid[0].BSSID);
- for (i = 0; i < WLAN_PMKID_LEN; i++) {
- WL_DBG("%02x\n", pmkid.pmkid[0].PMKID[i]);
- }
+ for (i = 0; i < WLAN_PMKID_LEN; i++)
+ WL_CONN("%02x\n", pmkid.pmkid[0].PMKID[i]);
for (i = 0; i < wl->pmk_list->pmkids.npmkid; i++)
if (!memcmp
@@ -2086,12 +2258,12 @@
WLAN_PMKID_LEN);
}
wl->pmk_list->pmkids.npmkid--;
- } else {
+ } else
err = -EINVAL;
- }
err = wl_update_pmklist(dev, wl->pmk_list, err);
+ WL_TRACE("Exit\n");
return err;
}
@@ -2102,9 +2274,13 @@
struct wl_priv *wl = wiphy_to_wl(wiphy);
s32 err = 0;
+ WL_TRACE("Enter\n");
CHECK_SYS_UP();
+
memset(wl->pmk_list, 0, sizeof(*wl->pmk_list));
err = wl_update_pmklist(dev, wl->pmk_list, err);
+
+ WL_TRACE("Exit\n");
return err;
}
@@ -2235,7 +2411,7 @@
bss_list->version);
return -EOPNOTSUPP;
}
- WL_DBG("scanned AP count (%d)\n", bss_list->count);
+ WL_SCAN("scanned AP count (%d)\n", bss_list->count);
bi = next_bss(bss_list, bi);
for_each_bss(bss_list, bi, i) {
err = wl_inform_single_bss(wl, bi);
@@ -2245,89 +2421,137 @@
return err;
}
+
static s32 wl_inform_single_bss(struct wl_priv *wl, struct wl_bss_info *bi)
{
struct wiphy *wiphy = wl_to_wiphy(wl);
- struct ieee80211_mgmt *mgmt;
- struct ieee80211_channel *channel;
+ struct ieee80211_channel *notify_channel;
+ struct cfg80211_bss *bss;
struct ieee80211_supported_band *band;
- struct wl_cfg80211_bss_info *notif_bss_info;
- struct wl_scan_req *sr = wl_to_sr(wl);
- struct beacon_proberesp *beacon_proberesp;
- s32 mgmt_type;
- u32 signal;
- u32 freq;
s32 err = 0;
+ u16 channel;
+ u32 freq;
+ u64 notify_timestamp;
+ u16 notify_capability;
+ u16 notify_interval;
+ u8 *notify_ie;
+ size_t notify_ielen;
+ s32 notify_signal;
if (unlikely(le32_to_cpu(bi->length) > WL_BSS_INFO_MAX)) {
- WL_DBG("Beacon is larger than buffer. Discarding\n");
- return err;
+ WL_ERR("Bss info is larger than buffer. Discarding\n");
+ return 0;
}
- notif_bss_info =
- kzalloc(sizeof(*notif_bss_info) + sizeof(*mgmt) - sizeof(u8) +
- WL_BSS_INFO_MAX, GFP_KERNEL);
- if (unlikely(!notif_bss_info)) {
- WL_ERR("notif_bss_info alloc failed\n");
- return -ENOMEM;
- }
- mgmt = (struct ieee80211_mgmt *)notif_bss_info->frame_buf;
- notif_bss_info->channel =
- bi->ctl_ch ? bi->ctl_ch : CHSPEC_CHANNEL(bi->chanspec);
- if (notif_bss_info->channel <= CH_MAX_2G_CHANNEL)
+ channel = bi->ctl_ch ? bi->ctl_ch :
+ CHSPEC_CHANNEL(le16_to_cpu(bi->chanspec));
+
+ if (channel <= CH_MAX_2G_CHANNEL)
band = wiphy->bands[IEEE80211_BAND_2GHZ];
else
band = wiphy->bands[IEEE80211_BAND_5GHZ];
- notif_bss_info->rssi = bi->RSSI;
- memcpy(mgmt->bssid, &bi->BSSID, ETH_ALEN);
- mgmt_type = wl->active_scan ?
- IEEE80211_STYPE_PROBE_RESP : IEEE80211_STYPE_BEACON;
- if (!memcmp(bi->SSID, sr->ssid.SSID, bi->SSID_len)) {
- mgmt->frame_control = cpu_to_le16(IEEE80211_FTYPE_MGMT |
- mgmt_type);
- }
- beacon_proberesp = wl->active_scan ?
- (struct beacon_proberesp *)&mgmt->u.probe_resp :
- (struct beacon_proberesp *)&mgmt->u.beacon;
- beacon_proberesp->timestamp = 0;
- beacon_proberesp->beacon_int = cpu_to_le16(bi->beacon_period);
- beacon_proberesp->capab_info = cpu_to_le16(bi->capability);
- wl_rst_ie(wl);
- /*
- * wl_add_ie is not necessary because it can only add duplicated
- * SSID, rate information to frame_buf
- */
- /*
- * wl_add_ie(wl, WLAN_EID_SSID, bi->SSID_len, bi->SSID);
- * wl_add_ie(wl, WLAN_EID_SUPP_RATES, bi->rateset.count,
- * bi->rateset.rates);
- */
- wl_mrg_ie(wl, ((u8 *) bi) + bi->ie_offset, bi->ie_length);
- wl_cp_ie(wl, beacon_proberesp->variable, WL_BSS_INFO_MAX -
- offsetof(struct wl_cfg80211_bss_info, frame_buf));
- notif_bss_info->frame_len =
- offsetof(struct ieee80211_mgmt,
- u.beacon.variable) + wl_get_ielen(wl);
- freq = ieee80211_channel_to_frequency(notif_bss_info->channel,
- band->band);
- channel = ieee80211_get_channel(wiphy, freq);
+ freq = ieee80211_channel_to_frequency(channel, band->band);
+ notify_channel = ieee80211_get_channel(wiphy, freq);
- WL_DBG("SSID : \"%s\", rssi %d, channel %d, capability : 0x04%x, bssid %pM\n",
- bi->SSID,
- notif_bss_info->rssi, notif_bss_info->channel,
- mgmt->u.beacon.capab_info, &bi->BSSID);
+ notify_timestamp = jiffies_to_msecs(jiffies)*1000; /* uSec */
+ notify_capability = le16_to_cpu(bi->capability);
+ notify_interval = le16_to_cpu(bi->beacon_period);
+ notify_ie = (u8 *)bi + le16_to_cpu(bi->ie_offset);
+ notify_ielen = le16_to_cpu(bi->ie_length);
+ notify_signal = (s16)le16_to_cpu(bi->RSSI) * 100;
- signal = notif_bss_info->rssi * 100;
- if (unlikely(!cfg80211_inform_bss_frame(wiphy, channel, mgmt,
- le16_to_cpu
- (notif_bss_info->frame_len),
- signal, GFP_KERNEL))) {
+ WL_CONN("bssid: %2.2X:%2.2X:%2.2X:%2.2X:%2.2X:%2.2X\n",
+ bi->BSSID[0], bi->BSSID[1], bi->BSSID[2],
+ bi->BSSID[3], bi->BSSID[4], bi->BSSID[5]);
+ WL_CONN("Channel: %d(%d)\n", channel, freq);
+ WL_CONN("Capability: %X\n", notify_capability);
+ WL_CONN("Beacon interval: %d\n", notify_interval);
+ WL_CONN("Signal: %d\n", notify_signal);
+ WL_CONN("notify_timestamp: %#018llx\n", notify_timestamp);
+
+ bss = cfg80211_inform_bss(wiphy, notify_channel, (const u8 *)bi->BSSID,
+ notify_timestamp, notify_capability, notify_interval, notify_ie,
+ notify_ielen, notify_signal, GFP_KERNEL);
+
+ if (unlikely(!bss)) {
WL_ERR("cfg80211_inform_bss_frame error\n");
- kfree(notif_bss_info);
return -EINVAL;
}
- kfree(notif_bss_info);
+
+ return err;
+}
+
+static s32
+wl_inform_ibss(struct wl_priv *wl, struct net_device *dev, const u8 *bssid)
+{
+ struct wiphy *wiphy = wl_to_wiphy(wl);
+ struct ieee80211_channel *notify_channel;
+ struct wl_bss_info *bi = NULL;
+ struct ieee80211_supported_band *band;
+ u8 *buf = NULL;
+ s32 err = 0;
+ u16 channel;
+ u32 freq;
+ u64 notify_timestamp;
+ u16 notify_capability;
+ u16 notify_interval;
+ u8 *notify_ie;
+ size_t notify_ielen;
+ s32 notify_signal;
+
+ WL_TRACE("Enter\n");
+
+ buf = kzalloc(WL_BSS_INFO_MAX, GFP_KERNEL);
+ if (buf == NULL) {
+ WL_ERR("kzalloc() failed\n");
+ err = -ENOMEM;
+ goto CleanUp;
+ }
+
+ *(u32 *)buf = cpu_to_le32(WL_BSS_INFO_MAX);
+
+ err = wl_dev_ioctl(dev, WLC_GET_BSS_INFO, buf, WL_BSS_INFO_MAX);
+ if (unlikely(err)) {
+ WL_ERR("WLC_GET_BSS_INFO failed: %d\n", err);
+ goto CleanUp;
+ }
+
+ bi = (wl_bss_info_t *)(buf + 4);
+
+ channel = bi->ctl_ch ? bi->ctl_ch :
+ CHSPEC_CHANNEL(le16_to_cpu(bi->chanspec));
+
+ if (channel <= CH_MAX_2G_CHANNEL)
+ band = wiphy->bands[IEEE80211_BAND_2GHZ];
+ else
+ band = wiphy->bands[IEEE80211_BAND_5GHZ];
+
+ freq = ieee80211_channel_to_frequency(channel, band->band);
+ notify_channel = ieee80211_get_channel(wiphy, freq);
+
+ notify_timestamp = jiffies_to_msecs(jiffies)*1000; /* uSec */
+ notify_capability = le16_to_cpu(bi->capability);
+ notify_interval = le16_to_cpu(bi->beacon_period);
+ notify_ie = (u8 *)bi + le16_to_cpu(bi->ie_offset);
+ notify_ielen = le16_to_cpu(bi->ie_length);
+ notify_signal = (s16)le16_to_cpu(bi->RSSI) * 100;
+
+ WL_CONN("channel: %d(%d)\n", channel, freq);
+ WL_CONN("capability: %X\n", notify_capability);
+ WL_CONN("beacon interval: %d\n", notify_interval);
+ WL_CONN("signal: %d\n", notify_signal);
+ WL_CONN("notify_timestamp: %#018llx\n", notify_timestamp);
+
+ cfg80211_inform_bss(wiphy, notify_channel, bssid,
+ notify_timestamp, notify_capability, notify_interval,
+ notify_ie, notify_ielen, notify_signal, GFP_KERNEL);
+
+CleanUp:
+
+ kfree(buf);
+
+ WL_TRACE("Exit\n");
return err;
}
@@ -2335,17 +2559,12 @@
static bool wl_is_linkup(struct wl_priv *wl, const wl_event_msg_t *e)
{
u32 event = be32_to_cpu(e->event_type);
- u16 flags = be16_to_cpu(e->flags);
+ u32 status = be32_to_cpu(e->status);
- if (event == WLC_E_LINK) {
- if (flags & WLC_EVENT_MSG_LINK) {
- if (wl_is_ibssmode(wl)) {
- if (wl_is_ibssstarter(wl)) {
- }
- } else {
- return true;
- }
- }
+ if (event == WLC_E_SET_SSID && status == WLC_E_STATUS_SUCCESS) {
+ WL_CONN("Processing set ssid\n");
+ wl->link_up = true;
+ return true;
}
return false;
@@ -2356,13 +2575,10 @@
u32 event = be32_to_cpu(e->event_type);
u16 flags = be16_to_cpu(e->flags);
- if (event == WLC_E_DEAUTH_IND || event == WLC_E_DISASSOC_IND) {
+ if (event == WLC_E_LINK && (!(flags & WLC_EVENT_MSG_LINK))) {
+ WL_CONN("Processing link down\n");
return true;
- } else if (event == WLC_E_LINK) {
- if (!(flags & WLC_EVENT_MSG_LINK))
- return true;
}
-
return false;
}
@@ -2370,10 +2586,17 @@
{
u32 event = be32_to_cpu(e->event_type);
u32 status = be32_to_cpu(e->status);
+ u16 flags = be16_to_cpu(e->flags);
- if (event == WLC_E_SET_SSID || event == WLC_E_LINK) {
- if (status == WLC_E_STATUS_NO_NETWORKS)
- return true;
+ if (event == WLC_E_LINK && status == WLC_E_STATUS_NO_NETWORKS) {
+ WL_CONN("Processing Link %s & no network found\n",
+ flags & WLC_EVENT_MSG_LINK ? "up" : "down");
+ return true;
+ }
+
+ if (event == WLC_E_SET_SSID && status != WLC_E_STATUS_SUCCESS) {
+ WL_CONN("Processing connecting & no network found\n");
+ return true;
}
return false;
@@ -2383,30 +2606,39 @@
wl_notify_connect_status(struct wl_priv *wl, struct net_device *ndev,
const wl_event_msg_t *e, void *data)
{
- bool act;
s32 err = 0;
if (wl_is_linkup(wl, e)) {
- wl_link_up(wl);
+ WL_CONN("Linkup\n");
if (wl_is_ibssmode(wl)) {
- cfg80211_ibss_joined(ndev, (s8 *)&e->addr,
- GFP_KERNEL);
- WL_DBG("joined in IBSS network\n");
- } else {
+ wl_update_prof(wl, NULL, (void *)e->addr,
+ WL_PROF_BSSID);
+ wl_inform_ibss(wl, ndev, e->addr);
+ cfg80211_ibss_joined(ndev, e->addr, GFP_KERNEL);
+ clear_bit(WL_STATUS_CONNECTING, &wl->status);
+ set_bit(WL_STATUS_CONNECTED, &wl->status);
+ } else
wl_bss_connect_done(wl, ndev, e, data, true);
- WL_DBG("joined in BSS network \"%s\"\n",
- ((struct wlc_ssid *)
- wl_read_prof(wl, WL_PROF_SSID))->SSID);
- }
- act = true;
- wl_update_prof(wl, e, &act, WL_PROF_ACT);
} else if (wl_is_linkdown(wl, e)) {
- cfg80211_disconnected(ndev, 0, NULL, 0, GFP_KERNEL);
- clear_bit(WL_STATUS_CONNECTED, &wl->status);
- wl_link_down(wl);
+ WL_CONN("Linkdown\n");
+ if (wl_is_ibssmode(wl)) {
+ if (test_and_clear_bit(WL_STATUS_CONNECTED,
+ &wl->status))
+ wl_link_down(wl);
+ } else {
+ if (test_and_clear_bit(WL_STATUS_CONNECTED,
+ &wl->status)) {
+ cfg80211_disconnected(ndev, 0, NULL, 0,
+ GFP_KERNEL);
+ wl_link_down(wl);
+ }
+ }
wl_init_prof(wl->profile);
} else if (wl_is_nonetwork(wl, e)) {
- wl_bss_connect_done(wl, ndev, e, data, false);
+ if (wl_is_ibssmode(wl))
+ clear_bit(WL_STATUS_CONNECTING, &wl->status);
+ else
+ wl_bss_connect_done(wl, ndev, e, data, false);
}
return err;
@@ -2416,12 +2648,16 @@
wl_notify_roaming_status(struct wl_priv *wl, struct net_device *ndev,
const wl_event_msg_t *e, void *data)
{
- bool act;
s32 err = 0;
+ u32 event = be32_to_cpu(e->event_type);
+ u32 status = be32_to_cpu(e->status);
- wl_bss_roaming_done(wl, ndev, e, data);
- act = true;
- wl_update_prof(wl, e, &act, WL_PROF_ACT);
+ if (event == WLC_E_ROAM && status == WLC_E_STATUS_SUCCESS) {
+ if (test_bit(WL_STATUS_CONNECTED, &wl->status))
+ wl_bss_roaming_done(wl, ndev, e, data);
+ else
+ wl_bss_connect_done(wl, ndev, e, data, true);
+ }
return err;
}
@@ -2468,6 +2704,8 @@
u32 resp_len;
s32 err = 0;
+ wl_clear_assoc_ies(wl);
+
err = wl_dev_bufvar_get(ndev, "assoc_info", wl->extra_buf,
WL_ASSOC_INFO_MAX);
if (unlikely(err)) {
@@ -2505,12 +2743,25 @@
conn_info->resp_ie_len = 0;
conn_info->resp_ie = NULL;
}
- WL_DBG("req len (%d) resp len (%d)\n",
+ WL_CONN("req len (%d) resp len (%d)\n",
conn_info->req_ie_len, conn_info->resp_ie_len);
return err;
}
+static void wl_clear_assoc_ies(struct wl_priv *wl)
+{
+ struct wl_connect_info *conn_info = wl_to_conn(wl);
+
+ kfree(conn_info->req_ie);
+ conn_info->req_ie = NULL;
+ conn_info->req_ie_len = 0;
+ kfree(conn_info->resp_ie);
+ conn_info->resp_ie = NULL;
+ conn_info->resp_ie_len = 0;
+}
+
+
static void wl_ch_to_chanspec(int ch, struct wl_join_params *join_params,
size_t *join_params_size)
{
@@ -2520,7 +2771,7 @@
join_params->params.chanspec_num = 1;
join_params->params.chanspec_list[0] = ch;
- if (join_params->params.chanspec_list[0])
+ if (join_params->params.chanspec_list[0] <= CH_MAX_2G_CHANNEL)
chanspec |= WL_CHANSPEC_BAND_2G;
else
chanspec |= WL_CHANSPEC_BAND_5G;
@@ -2539,14 +2790,14 @@
join_params->params.chanspec_num =
cpu_to_le32(join_params->params.chanspec_num);
- WL_DBG("join_params->params.chanspec_list[0]= %#X, channel %d, chanspec %#X\n",
+ WL_CONN("join_params->params.chanspec_list[0]= %#X,"
+ "channel %d, chanspec %#X\n",
join_params->params.chanspec_list[0], ch, chanspec);
}
}
static s32 wl_update_bss_info(struct wl_priv *wl)
{
- struct cfg80211_bss *bss;
struct wl_bss_info *bi;
struct wlc_ssid *ssid;
struct bcm_tlv *tim;
@@ -2556,67 +2807,52 @@
u8 *ie;
s32 err = 0;
+ WL_TRACE("Enter\n");
if (wl_is_ibssmode(wl))
return err;
ssid = (struct wlc_ssid *)wl_read_prof(wl, WL_PROF_SSID);
- bss =
- cfg80211_get_bss(wl_to_wiphy(wl), NULL, (s8 *)&wl->bssid,
- ssid->SSID, ssid->SSID_len, WLAN_CAPABILITY_ESS,
- WLAN_CAPABILITY_ESS);
- rtnl_lock();
- if (unlikely(!bss)) {
- WL_DBG("Could not find the AP\n");
- *(u32 *) wl->extra_buf = cpu_to_le32(WL_EXTRA_BUF_MAX);
- err = wl_dev_ioctl(wl_to_ndev(wl), WLC_GET_BSS_INFO,
- wl->extra_buf, WL_EXTRA_BUF_MAX);
- if (unlikely(err)) {
- WL_ERR("Could not get bss info %d\n", err);
- goto update_bss_info_out;
- }
- bi = (struct wl_bss_info *)(wl->extra_buf + 4);
- if (unlikely(memcmp(&bi->BSSID, &wl->bssid, ETH_ALEN))) {
- err = -EIO;
- goto update_bss_info_out;
- }
- err = wl_inform_single_bss(wl, bi);
- if (unlikely(err))
- goto update_bss_info_out;
-
- ie = ((u8 *)bi) + bi->ie_offset;
- ie_len = bi->ie_length;
- beacon_interval = cpu_to_le16(bi->beacon_period);
- } else {
- WL_DBG("Found the AP in the list - BSSID %pM\n", bss->bssid);
- ie = bss->information_elements;
- ie_len = bss->len_information_elements;
- beacon_interval = bss->beacon_interval;
- cfg80211_put_bss(bss);
+ *(u32 *)wl->extra_buf = cpu_to_le32(WL_EXTRA_BUF_MAX);
+ err = wl_dev_ioctl(wl_to_ndev(wl), WLC_GET_BSS_INFO,
+ wl->extra_buf, WL_EXTRA_BUF_MAX);
+ if (unlikely(err)) {
+ WL_ERR("Could not get bss info %d\n", err);
+ goto update_bss_info_out;
}
+ bi = (struct wl_bss_info *)(wl->extra_buf + 4);
+ err = wl_inform_single_bss(wl, bi);
+ if (unlikely(err))
+ goto update_bss_info_out;
+
+ ie = ((u8 *)bi) + bi->ie_offset;
+ ie_len = bi->ie_length;
+ beacon_interval = cpu_to_le16(bi->beacon_period);
+
tim = bcm_parse_tlvs(ie, ie_len, WLAN_EID_TIM);
- if (tim) {
+ if (tim)
dtim_period = tim->data[1];
- } else {
+ else {
/*
* active scan was done so we could not get dtim
* information out of probe response.
* so we speficially query dtim information to dongle.
*/
- err = wl_dev_ioctl(wl_to_ndev(wl), WLC_GET_DTIMPRD,
- &dtim_period, sizeof(dtim_period));
+ u32 var;
+ err = wl_dev_intvar_get(wl_to_ndev(wl), "dtim_assoc", &var);
if (unlikely(err)) {
- WL_ERR("WLC_GET_DTIMPRD error (%d)\n", err);
+ WL_ERR("wl dtim_assoc failed (%d)\n", err);
goto update_bss_info_out;
}
+ dtim_period = (u8)var;
}
wl_update_prof(wl, NULL, &beacon_interval, WL_PROF_BEACONINT);
wl_update_prof(wl, NULL, &dtim_period, WL_PROF_DTIMPERIOD);
update_bss_info_out:
- rtnl_unlock();
+ WL_TRACE("Exit");
return err;
}
@@ -2627,17 +2863,20 @@
struct wl_connect_info *conn_info = wl_to_conn(wl);
s32 err = 0;
+ WL_TRACE("Enter\n");
+
wl_get_assoc_ies(wl);
- memcpy(&wl->bssid, &e->addr, ETH_ALEN);
+ wl_update_prof(wl, NULL, &e->addr, WL_PROF_BSSID);
wl_update_bss_info(wl);
+
cfg80211_roamed(ndev, NULL,
- (u8 *)&wl->bssid,
+ (u8 *)wl_read_prof(wl, WL_PROF_BSSID),
conn_info->req_ie, conn_info->req_ie_len,
conn_info->resp_ie, conn_info->resp_ie_len, GFP_KERNEL);
- WL_DBG("Report roaming result\n");
+ WL_CONN("Report roaming result\n");
set_bit(WL_STATUS_CONNECTED, &wl->status);
-
+ WL_TRACE("Exit\n");
return err;
}
@@ -2648,30 +2887,28 @@
struct wl_connect_info *conn_info = wl_to_conn(wl);
s32 err = 0;
- wl_get_assoc_ies(wl);
- memcpy(&wl->bssid, &e->addr, ETH_ALEN);
- wl_update_bss_info(wl);
+ WL_TRACE("Enter\n");
+
if (test_and_clear_bit(WL_STATUS_CONNECTING, &wl->status)) {
+ if (completed) {
+ wl_get_assoc_ies(wl);
+ wl_update_prof(wl, NULL, &e->addr, WL_PROF_BSSID);
+ wl_update_bss_info(wl);
+ }
cfg80211_connect_result(ndev,
- (u8 *)&wl->bssid,
+ (u8 *)wl_read_prof(wl, WL_PROF_BSSID),
conn_info->req_ie,
conn_info->req_ie_len,
conn_info->resp_ie,
conn_info->resp_ie_len,
completed ? WLAN_STATUS_SUCCESS : WLAN_STATUS_AUTH_TIMEOUT,
GFP_KERNEL);
- WL_DBG("Report connect result - connection %s\n",
- completed ? "succeeded" : "failed");
- } else {
- cfg80211_roamed(ndev, NULL,
- (u8 *)&wl->bssid,
- conn_info->req_ie, conn_info->req_ie_len,
- conn_info->resp_ie, conn_info->resp_ie_len,
- GFP_KERNEL);
- WL_DBG("Report roaming result\n");
+ if (completed)
+ set_bit(WL_STATUS_CONNECTED, &wl->status);
+ WL_CONN("Report connect result - connection %s\n",
+ completed ? "succeeded" : "failed");
}
- set_bit(WL_STATUS_CONNECTED, &wl->status);
-
+ WL_TRACE("Exit\n");
return err;
}
@@ -2703,37 +2940,45 @@
struct wl_scan_results *bss_list;
u32 len = WL_SCAN_BUF_MAX;
s32 err = 0;
+ bool scan_abort = false;
- if (wl->iscan_on && wl->iscan_kickstart)
+ WL_TRACE("Enter\n");
+
+ if (wl->iscan_on && wl->iscan_kickstart) {
+ WL_TRACE("Exit\n");
return wl_wakeup_iscan(wl_to_iscan(wl));
+ }
if (unlikely(!test_and_clear_bit(WL_STATUS_SCANNING, &wl->status))) {
WL_ERR("Scan complete while device not scanning\n");
- return -EINVAL;
+ scan_abort = true;
+ err = -EINVAL;
+ goto scan_done_out;
}
- if (unlikely(!wl->scan_request)) {
- }
- rtnl_lock();
+
err = wl_dev_ioctl(ndev, WLC_GET_CHANNEL, &channel_inform,
sizeof(channel_inform));
if (unlikely(err)) {
WL_ERR("scan busy (%d)\n", err);
+ scan_abort = true;
goto scan_done_out;
}
channel_inform.scan_channel = le32_to_cpu(channel_inform.scan_channel);
if (unlikely(channel_inform.scan_channel)) {
- WL_DBG("channel_inform.scan_channel (%d)\n",
+ WL_CONN("channel_inform.scan_channel (%d)\n",
channel_inform.scan_channel);
}
wl->bss_list = wl->scan_results;
bss_list = wl->bss_list;
memset(bss_list, 0, len);
bss_list->buflen = cpu_to_le32(len);
+
err = wl_dev_ioctl(ndev, WLC_SCAN_RESULTS, bss_list, len);
if (unlikely(err)) {
WL_ERR("%s Scan_results error (%d)\n", ndev->name, err);
err = -EINVAL;
+ scan_abort = true;
goto scan_done_out;
}
bss_list->buflen = le32_to_cpu(bss_list->buflen);
@@ -2741,16 +2986,21 @@
bss_list->count = le32_to_cpu(bss_list->count);
err = wl_inform_bss(wl);
- if (err)
+ if (err) {
+ scan_abort = true;
goto scan_done_out;
+ }
scan_done_out:
if (wl->scan_request) {
- cfg80211_scan_done(wl->scan_request, false);
+ WL_SCAN("calling cfg80211_scan_done\n");
+ cfg80211_scan_done(wl->scan_request, scan_abort);
wl_set_mpc(ndev, 1);
wl->scan_request = NULL;
}
- rtnl_unlock();
+
+ WL_TRACE("Exit\n");
+
return err;
}
@@ -2773,12 +3023,7 @@
{
memset(el, 0, sizeof(*el));
el->handler[WLC_E_SCAN_COMPLETE] = wl_notify_scan_status;
- el->handler[WLC_E_JOIN] = wl_notify_connect_status;
el->handler[WLC_E_LINK] = wl_notify_connect_status;
- el->handler[WLC_E_DEAUTH_IND] = wl_notify_connect_status;
- el->handler[WLC_E_DISASSOC_IND] = wl_notify_connect_status;
- el->handler[WLC_E_ASSOC_IND] = wl_notify_connect_status;
- el->handler[WLC_E_REASSOC_IND] = wl_notify_connect_status;
el->handler[WLC_E_ROAM] = wl_notify_roaming_status;
el->handler[WLC_E_MIC_ERROR] = wl_notify_mic_status;
el->handler[WLC_E_SET_SSID] = wl_notify_connect_status;
@@ -2912,6 +3157,8 @@
return;
}
if (likely(wl->scan_request)) {
+ WL_SCAN("ISCAN Completed scan: %s\n",
+ aborted ? "Aborted" : "Done");
cfg80211_scan_done(wl->scan_request, aborted);
wl_set_mpc(ndev, 1);
wl->scan_request = NULL;
@@ -2922,7 +3169,7 @@
static s32 wl_wakeup_iscan(struct wl_iscan_ctrl *iscan)
{
if (likely(iscan->state != WL_ISCAN_STATE_IDLE)) {
- WL_DBG("wake up iscan\n");
+ WL_SCAN("wake up iscan\n");
up(&iscan->sync);
return 0;
}
@@ -2958,8 +3205,8 @@
results->buflen = le32_to_cpu(results->buflen);
results->version = le32_to_cpu(results->version);
results->count = le32_to_cpu(results->count);
- WL_DBG("results->count = %d\n", results->count);
- WL_DBG("results->buflen = %d\n", results->buflen);
+ WL_SCAN("results->count = %d\n", results->count);
+ WL_SCAN("results->buflen = %d\n", results->buflen);
*status = le32_to_cpu(list_buf->status);
*bss_list = results;
@@ -3053,7 +3300,7 @@
del_timer_sync(&iscan->timer);
iscan->timer_on = 0;
}
- WL_DBG("%s was terminated\n", __func__);
+ WL_SCAN("ISCAN thread terminated\n");
return 0;
}
@@ -3064,7 +3311,7 @@
if (iscan) {
iscan->timer_on = 0;
- WL_DBG("timer expired\n");
+ WL_SCAN("timer expired\n");
wl_wakeup_iscan(iscan);
}
}
@@ -3191,7 +3438,7 @@
WL_ERR("wl_cfg80211_dev is invalid\n");
return -ENOMEM;
}
- WL_DBG("func %p\n", wl_cfg80211_get_sdio_func());
+ WL_INFO("func %p\n", wl_cfg80211_get_sdio_func());
wdev = wl_alloc_wdev(sizeof(struct wl_iface), &wl_cfg80211_get_sdio_func()->dev);
if (IS_ERR(wdev))
return -ENOMEM;
@@ -3211,7 +3458,6 @@
goto cfg80211_attach_out;
}
wl_set_drvdata(wl_cfg80211_dev, ci);
- set_bit(WL_STATUS_READY, &wl->status);
return err;
@@ -3255,16 +3501,16 @@
WL_ERR("event queue empty...\n");
BUG();
}
- WL_DBG("event type (%d)\n", e->etype);
+ WL_INFO("event type (%d)\n", e->etype);
if (wl->el.handler[e->etype]) {
wl->el.handler[e->etype] (wl, wl_to_ndev(wl), &e->emsg,
e->edata);
} else {
- WL_DBG("Unknown Event (%d): ignoring\n", e->etype);
+ WL_INFO("Unknown Event (%d): ignoring\n", e->etype);
}
wl_put_event(e);
}
- WL_DBG("%s was terminated\n", __func__);
+ WL_INFO("was terminated\n");
return 0;
}
@@ -3273,11 +3519,7 @@
{
u32 event_type = be32_to_cpu(e->event_type);
struct wl_priv *wl = ndev_to_wl(ndev);
-#if (WL_DBG_LEVEL > 0)
- s8 *estr = (event_type <= sizeof(wl_dbg_estr) / WL_DBG_ESTR_MAX - 1) ?
- wl_dbg_estr[event_type] : (s8 *) "Unknown";
-#endif /* (WL_DBG_LEVEL > 0) */
- WL_DBG("event_type (%d):" "WLC_E_" "%s\n", event_type, estr);
+
if (likely(!wl_enq_event(wl, event_type, e, data)))
wl_wakeup_event(wl);
}
@@ -3370,7 +3612,6 @@
static s32 wl_dongle_mode(struct net_device *ndev, s32 iftype)
{
s32 infra = 0;
- s32 ap = 0;
s32 err = 0;
switch (iftype) {
@@ -3381,6 +3622,7 @@
err = -EINVAL;
return err;
case NL80211_IFTYPE_ADHOC:
+ infra = 0;
break;
case NL80211_IFTYPE_STATION:
infra = 1;
@@ -3391,20 +3633,13 @@
return err;
}
infra = cpu_to_le32(infra);
- ap = cpu_to_le32(ap);
- WL_DBG("%s ap (%d), infra (%d)\n", ndev->name, ap, infra);
err = wl_dev_ioctl(ndev, WLC_SET_INFRA, &infra, sizeof(infra));
if (unlikely(err)) {
WL_ERR("WLC_SET_INFRA error (%d)\n", err);
return err;
}
- err = wl_dev_ioctl(ndev, WLC_SET_AP, &ap, sizeof(ap));
- if (unlikely(err)) {
- WL_ERR("WLC_SET_AP error (%d)\n", err);
- return err;
- }
- return -EINPROGRESS;
+ return 0;
}
#ifndef EMBEDDED_PLATFORM
@@ -3465,116 +3700,6 @@
}
static s32
-wl_dongle_roam(struct net_device *ndev, u32 roamvar, u32 bcn_timeout)
-{
- s8 iovbuf[WL_EVENTING_MASK_LEN + 12]; /* Room for "event_msgs" +
- '\0' + bitvec */
- s32 err = 0;
-
- /* Setup timeout if Beacons are lost and roam is
- off to report link down */
- if (roamvar) {
- bcm_mkiovar("bcn_timeout", (char *)&bcn_timeout, 4, iovbuf,
- sizeof(iovbuf));
- err = wl_dev_ioctl(ndev, WLC_SET_VAR, iovbuf, sizeof(iovbuf));
- if (unlikely(err)) {
- WL_ERR("bcn_timeout error (%d)\n", err);
- goto dongle_rom_out;
- }
- }
- /* Enable/Disable built-in roaming to allow supplicant
- to take care of roaming */
- bcm_mkiovar("roam_off", (char *)&roamvar, 4, iovbuf, sizeof(iovbuf));
- err = wl_dev_ioctl(ndev, WLC_SET_VAR, iovbuf, sizeof(iovbuf));
- if (unlikely(err)) {
- WL_ERR("roam_off error (%d)\n", err);
- goto dongle_rom_out;
- }
-dongle_rom_out:
- return err;
-}
-
-static s32 wl_dongle_eventmsg(struct net_device *ndev)
-{
-
- s8 iovbuf[WL_EVENTING_MASK_LEN + 12]; /* Room for "event_msgs" +
- '\0' + bitvec */
- s8 eventmask[WL_EVENTING_MASK_LEN];
- s32 err = 0;
-
- /* Setup event_msgs */
- bcm_mkiovar("event_msgs", eventmask, WL_EVENTING_MASK_LEN, iovbuf,
- sizeof(iovbuf));
- err = wl_dev_ioctl(ndev, WLC_GET_VAR, iovbuf, sizeof(iovbuf));
- if (unlikely(err)) {
- WL_ERR("Get event_msgs error (%d)\n", err);
- goto dongle_eventmsg_out;
- }
- memcpy(eventmask, iovbuf, WL_EVENTING_MASK_LEN);
-
- setbit(eventmask, WLC_E_SET_SSID);
- setbit(eventmask, WLC_E_PRUNE);
- setbit(eventmask, WLC_E_AUTH);
- setbit(eventmask, WLC_E_REASSOC);
- setbit(eventmask, WLC_E_REASSOC_IND);
- setbit(eventmask, WLC_E_DEAUTH_IND);
- setbit(eventmask, WLC_E_DISASSOC_IND);
- setbit(eventmask, WLC_E_DISASSOC);
- setbit(eventmask, WLC_E_JOIN);
- setbit(eventmask, WLC_E_ASSOC_IND);
- setbit(eventmask, WLC_E_PSK_SUP);
- setbit(eventmask, WLC_E_LINK);
- setbit(eventmask, WLC_E_NDIS_LINK);
- setbit(eventmask, WLC_E_MIC_ERROR);
- setbit(eventmask, WLC_E_PMKID_CACHE);
- setbit(eventmask, WLC_E_TXFAIL);
- setbit(eventmask, WLC_E_JOIN_START);
- setbit(eventmask, WLC_E_SCAN_COMPLETE);
-
- bcm_mkiovar("event_msgs", eventmask, WL_EVENTING_MASK_LEN, iovbuf,
- sizeof(iovbuf));
- err = wl_dev_ioctl(ndev, WLC_SET_VAR, iovbuf, sizeof(iovbuf));
- if (unlikely(err)) {
- WL_ERR("Set event_msgs error (%d)\n", err);
- goto dongle_eventmsg_out;
- }
-
-dongle_eventmsg_out:
- return err;
-}
-
-static s32
-wl_dongle_scantime(struct net_device *ndev, s32 scan_assoc_time,
- s32 scan_unassoc_time)
-{
- s32 err = 0;
-
- err = wl_dev_ioctl(ndev, WLC_SET_SCAN_CHANNEL_TIME, &scan_assoc_time,
- sizeof(scan_assoc_time));
- if (err) {
- if (err == -EOPNOTSUPP) {
- WL_INFO("Scan assoc time is not supported\n");
- } else {
- WL_ERR("Scan assoc time error (%d)\n", err);
- }
- goto dongle_scantime_out;
- }
- err = wl_dev_ioctl(ndev, WLC_SET_SCAN_UNASSOC_TIME, &scan_unassoc_time,
- sizeof(scan_unassoc_time));
- if (err) {
- if (err == -EOPNOTSUPP) {
- WL_INFO("Scan unassoc time is not supported\n");
- } else {
- WL_ERR("Scan unassoc time error (%d)\n", err);
- }
- goto dongle_scantime_out;
- }
-
-dongle_scantime_out:
- return err;
-}
-
-static s32
wl_dongle_offload(struct net_device *ndev, s32 arpoe, s32 arp_ol)
{
s8 iovbuf[WL_EVENTING_MASK_LEN + 12]; /* Room for "event_msgs" +
@@ -3722,6 +3847,154 @@
}
#endif /* !EMBEDDED_PLATFORM */
+static s32 wl_dongle_eventmsg(struct net_device *ndev)
+{
+ s8 iovbuf[WL_EVENTING_MASK_LEN + 12]; /* Room for "event_msgs" +
+ '\0' + bitvec */
+ s8 eventmask[WL_EVENTING_MASK_LEN];
+ s32 err = 0;
+
+ WL_TRACE("Enter\n");
+
+ /* Setup event_msgs */
+ bcm_mkiovar("event_msgs", eventmask, WL_EVENTING_MASK_LEN, iovbuf,
+ sizeof(iovbuf));
+ err = wl_dev_ioctl(ndev, WLC_GET_VAR, iovbuf, sizeof(iovbuf));
+ if (unlikely(err)) {
+ WL_ERR("Get event_msgs error (%d)\n", err);
+ goto dongle_eventmsg_out;
+ }
+ memcpy(eventmask, iovbuf, WL_EVENTING_MASK_LEN);
+
+ setbit(eventmask, WLC_E_SET_SSID);
+ setbit(eventmask, WLC_E_ROAM);
+ setbit(eventmask, WLC_E_PRUNE);
+ setbit(eventmask, WLC_E_AUTH);
+ setbit(eventmask, WLC_E_REASSOC);
+ setbit(eventmask, WLC_E_REASSOC_IND);
+ setbit(eventmask, WLC_E_DEAUTH_IND);
+ setbit(eventmask, WLC_E_DISASSOC_IND);
+ setbit(eventmask, WLC_E_DISASSOC);
+ setbit(eventmask, WLC_E_JOIN);
+ setbit(eventmask, WLC_E_ASSOC_IND);
+ setbit(eventmask, WLC_E_PSK_SUP);
+ setbit(eventmask, WLC_E_LINK);
+ setbit(eventmask, WLC_E_NDIS_LINK);
+ setbit(eventmask, WLC_E_MIC_ERROR);
+ setbit(eventmask, WLC_E_PMKID_CACHE);
+ setbit(eventmask, WLC_E_TXFAIL);
+ setbit(eventmask, WLC_E_JOIN_START);
+ setbit(eventmask, WLC_E_SCAN_COMPLETE);
+
+ bcm_mkiovar("event_msgs", eventmask, WL_EVENTING_MASK_LEN, iovbuf,
+ sizeof(iovbuf));
+ err = wl_dev_ioctl(ndev, WLC_SET_VAR, iovbuf, sizeof(iovbuf));
+ if (unlikely(err)) {
+ WL_ERR("Set event_msgs error (%d)\n", err);
+ goto dongle_eventmsg_out;
+ }
+
+dongle_eventmsg_out:
+ WL_TRACE("Exit\n");
+ return err;
+}
+
+static s32
+wl_dongle_roam(struct net_device *ndev, u32 roamvar, u32 bcn_timeout)
+{
+ s8 iovbuf[32];
+ s32 roamtrigger[2];
+ s32 roam_delta[2];
+ s32 err = 0;
+
+ /*
+ * Setup timeout if Beacons are lost and roam is
+ * off to report link down
+ */
+ if (roamvar) {
+ bcm_mkiovar("bcn_timeout", (char *)&bcn_timeout,
+ sizeof(bcn_timeout), iovbuf, sizeof(iovbuf));
+ err = wl_dev_ioctl(ndev, WLC_SET_VAR, iovbuf, sizeof(iovbuf));
+ if (unlikely(err)) {
+ WL_ERR("bcn_timeout error (%d)\n", err);
+ goto dongle_rom_out;
+ }
+ }
+
+ /*
+ * Enable/Disable built-in roaming to allow supplicant
+ * to take care of roaming
+ */
+ WL_INFO("Internal Roaming = %s\n", roamvar ? "Off" : "On");
+ bcm_mkiovar("roam_off", (char *)&roamvar,
+ sizeof(roamvar), iovbuf, sizeof(iovbuf));
+ err = wl_dev_ioctl(ndev, WLC_SET_VAR, iovbuf, sizeof(iovbuf));
+ if (unlikely(err)) {
+ WL_ERR("roam_off error (%d)\n", err);
+ goto dongle_rom_out;
+ }
+
+ roamtrigger[0] = WL_ROAM_TRIGGER_LEVEL;
+ roamtrigger[1] = WLC_BAND_ALL;
+ err = wl_dev_ioctl(ndev, WLC_SET_ROAM_TRIGGER,
+ (void *)roamtrigger, sizeof(roamtrigger));
+ if (unlikely(err)) {
+ WL_ERR("WLC_SET_ROAM_TRIGGER error (%d)\n", err);
+ goto dongle_rom_out;
+ }
+
+ roam_delta[0] = WL_ROAM_DELTA;
+ roam_delta[1] = WLC_BAND_ALL;
+ err = wl_dev_ioctl(ndev, WLC_SET_ROAM_DELTA,
+ (void *)roam_delta, sizeof(roam_delta));
+ if (unlikely(err)) {
+ WL_ERR("WLC_SET_ROAM_DELTA error (%d)\n", err);
+ goto dongle_rom_out;
+ }
+
+dongle_rom_out:
+ return err;
+}
+
+static s32
+wl_dongle_scantime(struct net_device *ndev, s32 scan_assoc_time,
+ s32 scan_unassoc_time, s32 scan_passive_time)
+{
+ s32 err = 0;
+
+ err = wl_dev_ioctl(ndev, WLC_SET_SCAN_CHANNEL_TIME, &scan_assoc_time,
+ sizeof(scan_assoc_time));
+ if (err) {
+ if (err == -EOPNOTSUPP)
+ WL_INFO("Scan assoc time is not supported\n");
+ else
+ WL_ERR("Scan assoc time error (%d)\n", err);
+ goto dongle_scantime_out;
+ }
+ err = wl_dev_ioctl(ndev, WLC_SET_SCAN_UNASSOC_TIME, &scan_unassoc_time,
+ sizeof(scan_unassoc_time));
+ if (err) {
+ if (err == -EOPNOTSUPP)
+ WL_INFO("Scan unassoc time is not supported\n");
+ else
+ WL_ERR("Scan unassoc time error (%d)\n", err);
+ goto dongle_scantime_out;
+ }
+
+ err = wl_dev_ioctl(ndev, WLC_SET_SCAN_PASSIVE_TIME, &scan_passive_time,
+ sizeof(scan_passive_time));
+ if (err) {
+ if (err == -EOPNOTSUPP)
+ WL_INFO("Scan passive time is not supported\n");
+ else
+ WL_ERR("Scan passive time error (%d)\n", err);
+ goto dongle_scantime_out;
+ }
+
+dongle_scantime_out:
+ return err;
+}
+
s32 wl_config_dongle(struct wl_priv *wl, bool need_lock)
{
#ifndef DHD_SDALIGN
@@ -3752,18 +4025,20 @@
err = wl_dongle_glom(ndev, 0, DHD_SDALIGN);
if (unlikely(err))
goto default_conf_out;
- err = wl_dongle_roam(ndev, (wl->roam_on ? 0 : 1), 3);
- if (unlikely(err))
- goto default_conf_out;
+
+ wl_dongle_offload(ndev, 1, 0xf);
+ wl_dongle_filter(ndev, 1);
+#endif /* !EMBEDDED_PLATFORM */
+
+ wl_dongle_scantime(ndev, WL_SCAN_CHANNEL_TIME,
+ WL_SCAN_UNASSOC_TIME, WL_SCAN_PASSIVE_TIME);
+
err = wl_dongle_eventmsg(ndev);
if (unlikely(err))
goto default_conf_out;
-
- wl_dongle_scantime(ndev, 40, 80);
- wl_dongle_offload(ndev, 1, 0xf);
- wl_dongle_filter(ndev, 1);
-#endif /* !EMBEDDED_PLATFORM */
-
+ err = wl_dongle_roam(ndev, (wl->roam_on ? 0 : 1), WL_BEACON_TIMEOUT);
+ if (unlikely(err))
+ goto default_conf_out;
err = wl_dongle_mode(ndev, wdev->iftype);
if (unlikely(err && err != -EINPROGRESS))
goto default_conf_out;
@@ -3798,7 +4073,7 @@
}
phy = ((char *)&phy_list)[1];
- WL_DBG("%c phy\n", phy);
+ WL_INFO("%c phy\n", phy);
if (phy == 'n' || phy == 'a') {
wiphy = wl_to_wiphy(wl);
wiphy->bands[IEEE80211_BAND_5GHZ] = &__wl_band_5ghz_n;
@@ -3811,6 +4086,8 @@
{
s32 err = 0;
+ set_bit(WL_STATUS_READY, &wl->status);
+
wl_debugfs_add_netdev_params(wl);
err = wl_config_dongle(wl, false);
@@ -3818,41 +4095,29 @@
return err;
wl_invoke_iscan(wl);
- set_bit(WL_STATUS_READY, &wl->status);
+
return err;
}
static s32 __wl_cfg80211_down(struct wl_priv *wl)
{
- s32 err = 0;
-
- /* Check if cfg80211 interface is already down */
- if (!test_bit(WL_STATUS_READY, &wl->status))
- return err; /* it is even not ready */
-
set_bit(WL_STATUS_SCAN_ABORTING, &wl->status);
wl_term_iscan(wl);
if (wl->scan_request) {
- cfg80211_scan_done(wl->scan_request, true); /* true
- means abort */
- /* wl_set_mpc(wl_to_ndev(wl), 1); */ /* BUG
- * this operation cannot help
- * but here because sdio
- * is already down through
- * rmmod process.
- * Need to figure out how to
- * address this issue
- */
+ cfg80211_scan_done(wl->scan_request, true);
+ /* May need to perform this to cover rmmod */
+ /* wl_set_mpc(wl_to_ndev(wl), 1); */
wl->scan_request = NULL;
}
clear_bit(WL_STATUS_READY, &wl->status);
clear_bit(WL_STATUS_SCANNING, &wl->status);
clear_bit(WL_STATUS_SCAN_ABORTING, &wl->status);
+ clear_bit(WL_STATUS_CONNECTING, &wl->status);
clear_bit(WL_STATUS_CONNECTED, &wl->status);
wl_debugfs_remove_netdev(wl);
- return err;
+ return 0;
}
s32 wl_cfg80211_up(void)
@@ -3897,8 +4162,6 @@
switch (item) {
case WL_PROF_SEC:
return &wl->profile->sec;
- case WL_PROF_ACT:
- return &wl->profile->active;
case WL_PROF_BSSID:
return &wl->profile->bssid;
case WL_PROF_SSID:
@@ -3932,9 +4195,6 @@
case WL_PROF_SEC:
memcpy(&wl->profile->sec, data, sizeof(wl->profile->sec));
break;
- case WL_PROF_ACT:
- wl->profile->active = *(bool *)data;
- break;
case WL_PROF_BEACONINT:
wl->profile->beacon_interval = *(u16 *)data;
break;
@@ -3950,34 +4210,11 @@
return err;
}
-void wl_cfg80211_dbg_level(u32 level)
-{
- /*
- * prohibit to change debug level
- * by insmod parameter.
- * eventually debug level will be configured
- * in compile time by using CONFIG_XXX
- */
- /* wl_dbg_level = level; */
-}
-
static bool wl_is_ibssmode(struct wl_priv *wl)
{
return wl->conf->mode == WL_MODE_IBSS;
}
-static bool wl_is_ibssstarter(struct wl_priv *wl)
-{
- return wl->ibss_starter;
-}
-
-static void wl_rst_ie(struct wl_priv *wl)
-{
- struct wl_ie *ie = wl_to_ie(wl);
-
- ie->offset = 0;
-}
-
static __used s32 wl_add_ie(struct wl_priv *wl, u8 t, u8 l, u8 *v)
{
struct wl_ie *ie = wl_to_ie(wl);
@@ -3995,58 +4232,24 @@
return err;
}
-static s32 wl_mrg_ie(struct wl_priv *wl, u8 *ie_stream, u16 ie_size)
-{
- struct wl_ie *ie = wl_to_ie(wl);
- s32 err = 0;
-
- if (unlikely(ie->offset + ie_size > WL_TLV_INFO_MAX)) {
- WL_ERR("ei_stream crosses buffer boundary\n");
- return -ENOSPC;
- }
- memcpy(&ie->buf[ie->offset], ie_stream, ie_size);
- ie->offset += ie_size;
-
- return err;
-}
-
-static s32 wl_cp_ie(struct wl_priv *wl, u8 *dst, u16 dst_size)
-{
- struct wl_ie *ie = wl_to_ie(wl);
- s32 err = 0;
-
- if (unlikely(ie->offset > dst_size)) {
- WL_ERR("dst_size is not enough\n");
- return -ENOSPC;
- }
- memcpy(dst, &ie->buf[0], ie->offset);
-
- return err;
-}
-
-static u32 wl_get_ielen(struct wl_priv *wl)
-{
- struct wl_ie *ie = wl_to_ie(wl);
-
- return ie->offset;
-}
-
-static void wl_link_up(struct wl_priv *wl)
-{
- wl->link_up = true;
-}
static void wl_link_down(struct wl_priv *wl)
{
- struct wl_connect_info *conn_info = wl_to_conn(wl);
+ struct net_device *dev = NULL;
+ s32 err = 0;
- wl->link_up = false;
- kfree(conn_info->req_ie);
- conn_info->req_ie = NULL;
- conn_info->req_ie_len = 0;
- kfree(conn_info->resp_ie);
- conn_info->resp_ie = NULL;
- conn_info->resp_ie_len = 0;
+ WL_TRACE("Enter\n");
+ clear_bit(WL_STATUS_CONNECTED, &wl->status);
+
+ if (wl->link_up) {
+ dev = wl_to_ndev(wl);
+ WL_INFO("Call WLC_DISASSOC to stop excess roaming\n ");
+ err = wl_dev_ioctl(dev, WLC_DISASSOC, NULL, 0);
+ if (unlikely(err))
+ WL_ERR("WLC_DISASSOC failed (%d)\n", err);
+ wl->link_up = false;
+ }
+ WL_TRACE("Exit\n");
}
static void wl_lock_eq(struct wl_priv *wl)
@@ -4116,7 +4319,7 @@
const struct firmware *fw_entry = NULL;
s32 err = 0;
- WL_DBG("file name : \"%s\"\n", file_name);
+ WL_INFO("file name : \"%s\"\n", file_name);
wl = WL_PRIV_GET();
if (!test_bit(WL_FW_LOADING_DONE, &wl->fw->status)) {
@@ -4129,7 +4332,7 @@
set_bit(WL_FW_LOADING_DONE, &wl->fw->status);
fw_entry = wl->fw->fw_entry;
if (fw_entry) {
- WL_DBG("fw size (%zd), data (%p)\n",
+ WL_INFO("fw size (%zd), data (%p)\n",
fw_entry->size, fw_entry->data);
}
} else if (!test_bit(WL_NVRAM_LOADING_DONE, &wl->fw->status)) {
@@ -4142,11 +4345,11 @@
set_bit(WL_NVRAM_LOADING_DONE, &wl->fw->status);
fw_entry = wl->fw->fw_entry;
if (fw_entry) {
- WL_DBG("nvram size (%zd), data (%p)\n",
+ WL_INFO("nvram size (%zd), data (%p)\n",
fw_entry->size, fw_entry->data);
}
} else {
- WL_DBG("Downloading already done. Nothing to do more\n");
+ WL_INFO("Downloading already done. Nothing to do more\n");
err = -EPERM;
}
@@ -4179,13 +4382,16 @@
static void wl_set_mpc(struct net_device *ndev, int mpc)
{
s32 err = 0;
+ struct wl_priv *wl = ndev_to_wl(ndev);
- err = wl_dev_intvar_set(ndev, "mpc", mpc);
- if (unlikely(err)) {
- WL_ERR("fail to set mpc\n");
- return;
+ if (test_bit(WL_STATUS_READY, &wl->status)) {
+ err = wl_dev_intvar_set(ndev, "mpc", mpc);
+ if (unlikely(err)) {
+ WL_ERR("fail to set mpc\n");
+ return;
+ }
+ WL_INFO("MPC : %d\n", mpc);
}
- WL_DBG("MPC : %d\n", mpc);
}
static int wl_debugfs_add_netdev_params(struct wl_priv *wl)
diff --git a/drivers/staging/brcm80211/brcmfmac/wl_cfg80211.h b/drivers/staging/brcm80211/brcmfmac/wl_cfg80211.h
index 5112160..996033c 100644
--- a/drivers/staging/brcm80211/brcmfmac/wl_cfg80211.h
+++ b/drivers/staging/brcm80211/brcmfmac/wl_cfg80211.h
@@ -28,45 +28,73 @@
struct wl_security;
struct wl_ibss;
-#define WL_DBG_NONE 0
-#define WL_DBG_DBG (1 << 2)
-#define WL_DBG_INFO (1 << 1)
-#define WL_DBG_ERR (1 << 0)
-#define WL_DBG_MASK ((WL_DBG_DBG | WL_DBG_INFO | WL_DBG_ERR) << 1)
+#define WL_DBG_NONE 0
+#define WL_DBG_CONN (1 << 5)
+#define WL_DBG_SCAN (1 << 4)
+#define WL_DBG_TRACE (1 << 3)
+#define WL_DBG_INFO (1 << 1)
+#define WL_DBG_ERR (1 << 0)
+#define WL_DBG_MASK ((WL_DBG_INFO | WL_DBG_ERR | WL_DBG_TRACE) | \
+ (WL_DBG_SCAN) | (WL_DBG_CONN))
-#define WL_DBG_LEVEL 1 /* 0 invalidates all debug messages.
- default is 1 */
#define WL_ERR(fmt, args...) \
do { \
if (wl_dbg_level & WL_DBG_ERR) { \
if (net_ratelimit()) { \
printk(KERN_ERR "ERROR @%s : " fmt, \
- __func__, ##args); \
+ __func__, ##args); \
} \
} \
} while (0)
+#if (defined BCMDBG)
#define WL_INFO(fmt, args...) \
do { \
if (wl_dbg_level & WL_DBG_INFO) { \
if (net_ratelimit()) { \
printk(KERN_ERR "INFO @%s : " fmt, \
- __func__, ##args); \
+ __func__, ##args); \
} \
} \
} while (0)
-#if (WL_DBG_LEVEL > 0)
-#define WL_DBG(fmt, args...) \
+#define WL_TRACE(fmt, args...) \
do { \
- if (wl_dbg_level & WL_DBG_DBG) { \
- printk(KERN_ERR "DEBUG @%s :" fmt, \
- __func__, ##args); \
+ if (wl_dbg_level & WL_DBG_TRACE) { \
+ if (net_ratelimit()) { \
+ printk(KERN_ERR "TRACE @%s : " fmt, \
+ __func__, ##args); \
+ } \
} \
} while (0)
-#else /* !(WL_DBG_LEVEL > 0) */
-#define WL_DBG(fmt, args...) noprintk(fmt, ##args)
-#endif /* (WL_DBG_LEVEL > 0) */
+
+#define WL_SCAN(fmt, args...) \
+do { \
+ if (wl_dbg_level & WL_DBG_SCAN) { \
+ if (net_ratelimit()) { \
+ printk(KERN_ERR "SCAN @%s : " fmt, \
+ __func__, ##args); \
+ } \
+ } \
+} while (0)
+
+#define WL_CONN(fmt, args...) \
+do { \
+ if (wl_dbg_level & WL_DBG_CONN) { \
+ if (net_ratelimit()) { \
+ printk(KERN_ERR "CONN @%s : " fmt, \
+ __func__, ##args); \
+ } \
+ } \
+} while (0)
+
+#else /* (defined BCMDBG) */
+#define WL_INFO(fmt, args...)
+#define WL_TRACE(fmt, args...)
+#define WL_SCAN(fmt, args...)
+#define WL_CONN(fmt, args...)
+#endif /* (defined BCMDBG) */
+
#define WL_SCAN_RETRY_MAX 3 /* used for ibss scan */
#define WL_NUM_SCAN_MAX 1
@@ -95,6 +123,14 @@
*/
#define WL_FILE_NAME_MAX 256
+#define WL_ROAM_TRIGGER_LEVEL -75
+#define WL_ROAM_DELTA 20
+#define WL_BEACON_TIMEOUT 3
+
+#define WL_SCAN_CHANNEL_TIME 40
+#define WL_SCAN_UNASSOC_TIME 40
+#define WL_SCAN_PASSIVE_TIME 120
+
/* dongle status */
enum wl_status {
WL_STATUS_READY,
@@ -227,7 +263,6 @@
struct wl_security sec;
struct wl_ibss ibss;
s32 band;
- bool active;
};
/* dongle iscan event loop */
@@ -298,7 +333,6 @@
cfg80211 layer */
struct wl_ie ie; /* information element object for
internal purpose */
- u8 bssid[ETH_ALEN]; /* bssid of currently engaged network */
struct semaphore event_sync; /* for synchronization of main event
thread */
struct wl_profile *profile; /* holding dongle profile */
@@ -375,5 +409,6 @@
the dongle */
extern s8 *wl_cfg80211_get_nvramname(void); /* get nvram name for
the dongle */
+extern void wl_os_wd_timer(struct net_device *ndev, uint wdtick);
#endif /* _wl_cfg80211_h_ */
diff --git a/drivers/staging/brcm80211/brcmfmac/wl_iw.c b/drivers/staging/brcm80211/brcmfmac/wl_iw.c
index b49957f..929ceaf 100644
--- a/drivers/staging/brcm80211/brcmfmac/wl_iw.c
+++ b/drivers/staging/brcm80211/brcmfmac/wl_iw.c
@@ -69,8 +69,6 @@
#define MAX_WLIW_IOCTL_LEN 1024
#ifdef CONFIG_WIRELESS_EXT
-
-extern struct iw_statistics *dhd_get_wireless_stats(struct net_device *dev);
extern int dhd_wait_pend8021x(struct net_device *dev);
#endif
@@ -119,6 +117,9 @@
static const u8 ether_bcast[ETH_ALEN] = {255, 255, 255, 255, 255, 255};
+/* Global ASSERT type flag */
+u32 g_assert_type;
+
static void wl_iw_timerfunc(unsigned long data);
static void wl_iw_set_event_mask(struct net_device *dev);
static int wl_iw_iscan(iscan_info_t *iscan, wlc_ssid_t *ssid, u16 action);
@@ -372,7 +373,7 @@
if (fwrq->m > 4000 && fwrq->m < 5000)
sf = WF_CHAN_FACTOR_4_G;
- chan = wf_mhz2channel(fwrq->m, sf);
+ chan = bcm_mhz2channel(fwrq->m, sf);
}
chan = cpu_to_le32(chan);
@@ -495,9 +496,7 @@
list = (wl_u32_list_t *) channels;
dwrq->length = sizeof(struct iw_range);
- memset(range, 0, sizeof(range));
-
- range->min_nwid = range->max_nwid = 0;
+ memset(range, 0, sizeof(*range));
list->count = cpu_to_le32(MAXCHANNEL);
error = dev_wlc_ioctl(dev, WLC_GET_VALID_CHANNELS, channels,
@@ -3131,7 +3130,7 @@
.private_args = 0,
#if WIRELESS_EXT >= 19
- .get_wireless_stats = dhd_get_wireless_stats,
+ .get_wireless_stats = NULL,
#endif
};
#endif /* WIRELESS_EXT > 12 */
@@ -3548,103 +3547,6 @@
#endif /* WIRELESS_EXT > 13 */
}
-int
-wl_iw_get_wireless_stats(struct net_device *dev, struct iw_statistics *wstats)
-{
- int res = 0;
- struct wl_cnt cnt;
- int phy_noise;
- int rssi;
- scb_val_t scb_val;
-
- phy_noise = 0;
- res = dev_wlc_ioctl(dev, WLC_GET_PHY_NOISE, &phy_noise,
- sizeof(phy_noise));
- if (res)
- goto done;
-
- phy_noise = le32_to_cpu(phy_noise);
- WL_TRACE("wl_iw_get_wireless_stats phy noise=%d\n", phy_noise);
-
- memset(&scb_val, 0, sizeof(scb_val_t));
- res = dev_wlc_ioctl(dev, WLC_GET_RSSI, &scb_val, sizeof(scb_val_t));
- if (res)
- goto done;
-
- rssi = le32_to_cpu(scb_val.val);
- WL_TRACE("wl_iw_get_wireless_stats rssi=%d\n", rssi);
- if (rssi <= WL_IW_RSSI_NO_SIGNAL)
- wstats->qual.qual = 0;
- else if (rssi <= WL_IW_RSSI_VERY_LOW)
- wstats->qual.qual = 1;
- else if (rssi <= WL_IW_RSSI_LOW)
- wstats->qual.qual = 2;
- else if (rssi <= WL_IW_RSSI_GOOD)
- wstats->qual.qual = 3;
- else if (rssi <= WL_IW_RSSI_VERY_GOOD)
- wstats->qual.qual = 4;
- else
- wstats->qual.qual = 5;
-
- wstats->qual.level = 0x100 + rssi;
- wstats->qual.noise = 0x100 + phy_noise;
-#if WIRELESS_EXT > 18
- wstats->qual.updated |= (IW_QUAL_ALL_UPDATED | IW_QUAL_DBM);
-#else
- wstats->qual.updated |= 7;
-#endif
-
-#if WIRELESS_EXT > 11
- WL_TRACE("wl_iw_get_wireless_stats counters=%zu\n",
- sizeof(struct wl_cnt));
-
- memset(&cnt, 0, sizeof(struct wl_cnt));
- res =
- dev_wlc_bufvar_get(dev, "counters", (char *)&cnt,
- sizeof(struct wl_cnt));
- if (res) {
- WL_ERROR("wl_iw_get_wireless_stats counters failed error=%d\n",
- res);
- goto done;
- }
-
- cnt.version = le16_to_cpu(cnt.version);
- if (cnt.version != WL_CNT_T_VERSION) {
- WL_TRACE("\tIncorrect counter version: expected %d; got %d\n",
- WL_CNT_T_VERSION, cnt.version);
- goto done;
- }
-
- wstats->discard.nwid = 0;
- wstats->discard.code = le32_to_cpu(cnt.rxundec);
- wstats->discard.fragment = le32_to_cpu(cnt.rxfragerr);
- wstats->discard.retries = le32_to_cpu(cnt.txfail);
- wstats->discard.misc = le32_to_cpu(cnt.rxrunt) +
- le32_to_cpu(cnt.rxgiant);
- wstats->miss.beacon = 0;
-
- WL_TRACE("wl_iw_get_wireless_stats counters txframe=%d txbyte=%d\n",
- le32_to_cpu(cnt.txframe), le32_to_cpu(cnt.txbyte));
- WL_TRACE("wl_iw_get_wireless_stats counters rxfrmtoolong=%d\n",
- le32_to_cpu(cnt.rxfrmtoolong));
- WL_TRACE("wl_iw_get_wireless_stats counters rxbadplcp=%d\n",
- le32_to_cpu(cnt.rxbadplcp));
- WL_TRACE("wl_iw_get_wireless_stats counters rxundec=%d\n",
- le32_to_cpu(cnt.rxundec));
- WL_TRACE("wl_iw_get_wireless_stats counters rxfragerr=%d\n",
- le32_to_cpu(cnt.rxfragerr));
- WL_TRACE("wl_iw_get_wireless_stats counters txfail=%d\n",
- le32_to_cpu(cnt.txfail));
- WL_TRACE("wl_iw_get_wireless_stats counters rxrunt=%d\n",
- le32_to_cpu(cnt.rxrunt));
- WL_TRACE("wl_iw_get_wireless_stats counters rxgiant=%d\n",
- le32_to_cpu(cnt.rxgiant));
-#endif /* WIRELESS_EXT > 11 */
-
-done:
- return res;
-}
-
int wl_iw_attach(struct net_device *dev, void *dhdp)
{
int params_size;
@@ -3672,8 +3574,10 @@
return -ENOMEM;
iscan->iscan_ex_params_p = kmalloc(params_size, GFP_KERNEL);
- if (!iscan->iscan_ex_params_p)
+ if (!iscan->iscan_ex_params_p) {
+ kfree(iscan);
return -ENOMEM;
+ }
iscan->iscan_ex_param_size = params_size;
iscan->sysioc_tsk = NULL;
@@ -3742,3 +3646,50 @@
g_scan = NULL;
}
+
+#if defined(BCMDBG)
+void osl_assert(char *exp, char *file, int line)
+{
+ char tempbuf[256];
+ char *basename;
+
+ basename = strrchr(file, '/');
+ /* skip the '/' */
+ if (basename)
+ basename++;
+
+ if (!basename)
+ basename = file;
+
+ snprintf(tempbuf, 256,
+ "assertion \"%s\" failed: file \"%s\", line %d\n", exp,
+ basename, line);
+
+ /*
+ * Print assert message and give it time to
+ * be written to /var/log/messages
+ */
+ if (!in_interrupt()) {
+ const int delay = 3;
+ printk(KERN_ERR "%s", tempbuf);
+ printk(KERN_ERR "panic in %d seconds\n", delay);
+ set_current_state(TASK_INTERRUPTIBLE);
+ schedule_timeout(delay * HZ);
+ }
+
+ switch (g_assert_type) {
+ case 0:
+ panic(KERN_ERR "%s", tempbuf);
+ break;
+ case 1:
+ printk(KERN_ERR "%s", tempbuf);
+ BUG();
+ break;
+ case 2:
+ printk(KERN_ERR "%s", tempbuf);
+ break;
+ default:
+ break;
+ }
+}
+#endif /* defined(BCMDBG) */
diff --git a/drivers/staging/brcm80211/brcmsmac/Makefile b/drivers/staging/brcm80211/brcmsmac/Makefile
index c4aafe5..8d75fe1 100644
--- a/drivers/staging/brcm80211/brcmsmac/Makefile
+++ b/drivers/staging/brcm80211/brcmsmac/Makefile
@@ -25,7 +25,6 @@
-DBCMNVRAMR \
-Idrivers/staging/brcm80211/brcmsmac \
-Idrivers/staging/brcm80211/brcmsmac/phy \
- -Idrivers/staging/brcm80211/util \
-Idrivers/staging/brcm80211/include
BRCMSMAC_OFILES := \
@@ -38,26 +37,23 @@
wlc_channel.o \
wlc_main.o \
wlc_phy_shim.o \
+ wlc_pmu.o \
wlc_rate.o \
wlc_stf.o \
+ aiutils.o \
phy/wlc_phy_cmn.o \
phy/wlc_phy_lcn.o \
phy/wlc_phy_n.o \
phy/wlc_phytbl_lcn.o \
phy/wlc_phytbl_n.o \
- ../util/aiutils.o \
- ../util/siutils.o \
- ../util/bcmutils.o \
- ../util/bcmwifi.o \
- ../util/bcmotp.o \
- ../util/bcmsrom.o \
- ../util/hnddma.o \
- ../util/hndpmu.o \
- ../util/nicpci.o \
- ../util/qmath.o \
- ../util/nvram/nvram_ro.o
+ phy/wlc_phy_qmath.o \
+ bcmotp.o \
+ bcmsrom.o \
+ hnddma.o \
+ nicpci.o \
+ nvram.o
MODULEPFX := brcmsmac
-obj-m += $(MODULEPFX).o
+obj-$(CONFIG_BRCMSMAC) += $(MODULEPFX).o
$(MODULEPFX)-objs = $(BRCMSMAC_OFILES)
diff --git a/drivers/staging/brcm80211/brcmsmac/aiutils.c b/drivers/staging/brcm80211/brcmsmac/aiutils.c
new file mode 100644
index 0000000..a61185f
--- /dev/null
+++ b/drivers/staging/brcm80211/brcmsmac/aiutils.c
@@ -0,0 +1,2054 @@
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <bcmdefs.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <bcmutils.h>
+#include <aiutils.h>
+#include <hndsoc.h>
+#include <sbchipc.h>
+#include <pcicfg.h>
+#include <bcmdevs.h>
+
+/* ********** from siutils.c *********** */
+#include <pci_core.h>
+#include <pcie_core.h>
+#include <nicpci.h>
+#include <bcmnvram.h>
+#include <bcmsrom.h>
+#include <wlc_pmu.h>
+
+#define BCM47162_DMP() ((sih->chip == BCM47162_CHIP_ID) && \
+ (sih->chiprev == 0) && \
+ (sii->coreid[sii->curidx] == MIPS74K_CORE_ID))
+
+/* EROM parsing */
+
+static u32
+get_erom_ent(si_t *sih, u32 **eromptr, u32 mask, u32 match)
+{
+ u32 ent;
+ uint inv = 0, nom = 0;
+
+ while (true) {
+ ent = R_REG(*eromptr);
+ (*eromptr)++;
+
+ if (mask == 0)
+ break;
+
+ if ((ent & ER_VALID) == 0) {
+ inv++;
+ continue;
+ }
+
+ if (ent == (ER_END | ER_VALID))
+ break;
+
+ if ((ent & mask) == match)
+ break;
+
+ nom++;
+ }
+
+ SI_VMSG(("%s: Returning ent 0x%08x\n", __func__, ent));
+ if (inv + nom) {
+ SI_VMSG((" after %d invalid and %d non-matching entries\n",
+ inv, nom));
+ }
+ return ent;
+}
+
+static u32
+get_asd(si_t *sih, u32 **eromptr, uint sp, uint ad, uint st,
+ u32 *addrl, u32 *addrh, u32 *sizel, u32 *sizeh)
+{
+ u32 asd, sz, szd;
+
+ asd = get_erom_ent(sih, eromptr, ER_VALID, ER_VALID);
+ if (((asd & ER_TAG1) != ER_ADD) ||
+ (((asd & AD_SP_MASK) >> AD_SP_SHIFT) != sp) ||
+ ((asd & AD_ST_MASK) != st)) {
+ /* This is not what we want, "push" it back */
+ (*eromptr)--;
+ return 0;
+ }
+ *addrl = asd & AD_ADDR_MASK;
+ if (asd & AD_AG32)
+ *addrh = get_erom_ent(sih, eromptr, 0, 0);
+ else
+ *addrh = 0;
+ *sizeh = 0;
+ sz = asd & AD_SZ_MASK;
+ if (sz == AD_SZ_SZD) {
+ szd = get_erom_ent(sih, eromptr, 0, 0);
+ *sizel = szd & SD_SZ_MASK;
+ if (szd & SD_SG32)
+ *sizeh = get_erom_ent(sih, eromptr, 0, 0);
+ } else
+ *sizel = AD_SZ_BASE << (sz >> AD_SZ_SHIFT);
+
+ SI_VMSG((" SP %d, ad %d: st = %d, 0x%08x_0x%08x @ 0x%08x_0x%08x\n",
+ sp, ad, st, *sizeh, *sizel, *addrh, *addrl));
+
+ return asd;
+}
+
+static void ai_hwfixup(si_info_t *sii)
+{
+}
+
+/* parse the enumeration rom to identify all cores */
+void ai_scan(si_t *sih, void *regs, uint devid)
+{
+ si_info_t *sii = SI_INFO(sih);
+ chipcregs_t *cc = (chipcregs_t *) regs;
+ u32 erombase, *eromptr, *eromlim;
+
+ erombase = R_REG(&cc->eromptr);
+
+ switch (sih->bustype) {
+ case SI_BUS:
+ eromptr = (u32 *) REG_MAP(erombase, SI_CORE_SIZE);
+ break;
+
+ case PCI_BUS:
+ /* Set wrappers address */
+ sii->curwrap = (void *)((unsigned long)regs + SI_CORE_SIZE);
+
+ /* Now point the window at the erom */
+ pci_write_config_dword(sii->pbus, PCI_BAR0_WIN, erombase);
+ eromptr = regs;
+ break;
+
+ case SPI_BUS:
+ case SDIO_BUS:
+ eromptr = (u32 *)(unsigned long)erombase;
+ break;
+
+ default:
+ SI_ERROR(("Don't know how to do AXI enumertion on bus %d\n",
+ sih->bustype));
+ return;
+ }
+ eromlim = eromptr + (ER_REMAPCONTROL / sizeof(u32));
+
+ SI_VMSG(("ai_scan: regs = 0x%p, erombase = 0x%08x, eromptr = 0x%p, eromlim = 0x%p\n", regs, erombase, eromptr, eromlim));
+ while (eromptr < eromlim) {
+ u32 cia, cib, cid, mfg, crev, nmw, nsw, nmp, nsp;
+ u32 mpd, asd, addrl, addrh, sizel, sizeh;
+ u32 *base;
+ uint i, j, idx;
+ bool br;
+
+ br = false;
+
+ /* Grok a component */
+ cia = get_erom_ent(sih, &eromptr, ER_TAG, ER_CI);
+ if (cia == (ER_END | ER_VALID)) {
+ SI_VMSG(("Found END of erom after %d cores\n",
+ sii->numcores));
+ ai_hwfixup(sii);
+ return;
+ }
+ base = eromptr - 1;
+ cib = get_erom_ent(sih, &eromptr, 0, 0);
+
+ if ((cib & ER_TAG) != ER_CI) {
+ SI_ERROR(("CIA not followed by CIB\n"));
+ goto error;
+ }
+
+ cid = (cia & CIA_CID_MASK) >> CIA_CID_SHIFT;
+ mfg = (cia & CIA_MFG_MASK) >> CIA_MFG_SHIFT;
+ crev = (cib & CIB_REV_MASK) >> CIB_REV_SHIFT;
+ nmw = (cib & CIB_NMW_MASK) >> CIB_NMW_SHIFT;
+ nsw = (cib & CIB_NSW_MASK) >> CIB_NSW_SHIFT;
+ nmp = (cib & CIB_NMP_MASK) >> CIB_NMP_SHIFT;
+ nsp = (cib & CIB_NSP_MASK) >> CIB_NSP_SHIFT;
+
+ SI_VMSG(("Found component 0x%04x/0x%04x rev %d at erom addr 0x%p, with nmw = %d, " "nsw = %d, nmp = %d & nsp = %d\n", mfg, cid, crev, base, nmw, nsw, nmp, nsp));
+
+ if (((mfg == MFGID_ARM) && (cid == DEF_AI_COMP)) || (nsp == 0))
+ continue;
+ if ((nmw + nsw == 0)) {
+ /* A component which is not a core */
+ if (cid == OOB_ROUTER_CORE_ID) {
+ asd = get_asd(sih, &eromptr, 0, 0, AD_ST_SLAVE,
+ &addrl, &addrh, &sizel, &sizeh);
+ if (asd != 0) {
+ sii->oob_router = addrl;
+ }
+ }
+ continue;
+ }
+
+ idx = sii->numcores;
+/* sii->eromptr[idx] = base; */
+ sii->cia[idx] = cia;
+ sii->cib[idx] = cib;
+ sii->coreid[idx] = cid;
+
+ for (i = 0; i < nmp; i++) {
+ mpd = get_erom_ent(sih, &eromptr, ER_VALID, ER_VALID);
+ if ((mpd & ER_TAG) != ER_MP) {
+ SI_ERROR(("Not enough MP entries for component 0x%x\n", cid));
+ goto error;
+ }
+ SI_VMSG((" Master port %d, mp: %d id: %d\n", i,
+ (mpd & MPD_MP_MASK) >> MPD_MP_SHIFT,
+ (mpd & MPD_MUI_MASK) >> MPD_MUI_SHIFT));
+ }
+
+ /* First Slave Address Descriptor should be port 0:
+ * the main register space for the core
+ */
+ asd =
+ get_asd(sih, &eromptr, 0, 0, AD_ST_SLAVE, &addrl, &addrh,
+ &sizel, &sizeh);
+ if (asd == 0) {
+ /* Try again to see if it is a bridge */
+ asd =
+ get_asd(sih, &eromptr, 0, 0, AD_ST_BRIDGE, &addrl,
+ &addrh, &sizel, &sizeh);
+ if (asd != 0)
+ br = true;
+ else if ((addrh != 0) || (sizeh != 0)
+ || (sizel != SI_CORE_SIZE)) {
+ SI_ERROR(("First Slave ASD for core 0x%04x malformed " "(0x%08x)\n", cid, asd));
+ goto error;
+ }
+ }
+ sii->coresba[idx] = addrl;
+ sii->coresba_size[idx] = sizel;
+ /* Get any more ASDs in port 0 */
+ j = 1;
+ do {
+ asd =
+ get_asd(sih, &eromptr, 0, j, AD_ST_SLAVE, &addrl,
+ &addrh, &sizel, &sizeh);
+ if ((asd != 0) && (j == 1) && (sizel == SI_CORE_SIZE)) {
+ sii->coresba2[idx] = addrl;
+ sii->coresba2_size[idx] = sizel;
+ }
+ j++;
+ } while (asd != 0);
+
+ /* Go through the ASDs for other slave ports */
+ for (i = 1; i < nsp; i++) {
+ j = 0;
+ do {
+ asd =
+ get_asd(sih, &eromptr, i, j++, AD_ST_SLAVE,
+ &addrl, &addrh, &sizel, &sizeh);
+ } while (asd != 0);
+ if (j == 0) {
+ SI_ERROR((" SP %d has no address descriptors\n",
+ i));
+ goto error;
+ }
+ }
+
+ /* Now get master wrappers */
+ for (i = 0; i < nmw; i++) {
+ asd =
+ get_asd(sih, &eromptr, i, 0, AD_ST_MWRAP, &addrl,
+ &addrh, &sizel, &sizeh);
+ if (asd == 0) {
+ SI_ERROR(("Missing descriptor for MW %d\n", i));
+ goto error;
+ }
+ if ((sizeh != 0) || (sizel != SI_CORE_SIZE)) {
+ SI_ERROR(("Master wrapper %d is not 4KB\n", i));
+ goto error;
+ }
+ if (i == 0)
+ sii->wrapba[idx] = addrl;
+ }
+
+ /* And finally slave wrappers */
+ for (i = 0; i < nsw; i++) {
+ uint fwp = (nsp == 1) ? 0 : 1;
+ asd =
+ get_asd(sih, &eromptr, fwp + i, 0, AD_ST_SWRAP,
+ &addrl, &addrh, &sizel, &sizeh);
+ if (asd == 0) {
+ SI_ERROR(("Missing descriptor for SW %d\n", i));
+ goto error;
+ }
+ if ((sizeh != 0) || (sizel != SI_CORE_SIZE)) {
+ SI_ERROR(("Slave wrapper %d is not 4KB\n", i));
+ goto error;
+ }
+ if ((nmw == 0) && (i == 0))
+ sii->wrapba[idx] = addrl;
+ }
+
+ /* Don't record bridges */
+ if (br)
+ continue;
+
+ /* Done with core */
+ sii->numcores++;
+ }
+
+ SI_ERROR(("Reached end of erom without finding END"));
+
+ error:
+ sii->numcores = 0;
+ return;
+}
+
+/* This function changes the logical "focus" to the indicated core.
+ * Return the current core's virtual address.
+ */
+void *ai_setcoreidx(si_t *sih, uint coreidx)
+{
+ si_info_t *sii = SI_INFO(sih);
+ u32 addr = sii->coresba[coreidx];
+ u32 wrap = sii->wrapba[coreidx];
+ void *regs;
+
+ if (coreidx >= sii->numcores)
+ return NULL;
+
+ switch (sih->bustype) {
+ case SI_BUS:
+ /* map new one */
+ if (!sii->regs[coreidx]) {
+ sii->regs[coreidx] = REG_MAP(addr, SI_CORE_SIZE);
+ }
+ sii->curmap = regs = sii->regs[coreidx];
+ if (!sii->wrappers[coreidx]) {
+ sii->wrappers[coreidx] = REG_MAP(wrap, SI_CORE_SIZE);
+ }
+ sii->curwrap = sii->wrappers[coreidx];
+ break;
+
+ case PCI_BUS:
+ /* point bar0 window */
+ pci_write_config_dword(sii->pbus, PCI_BAR0_WIN, addr);
+ regs = sii->curmap;
+ /* point bar0 2nd 4KB window */
+ pci_write_config_dword(sii->pbus, PCI_BAR0_WIN2, wrap);
+ break;
+
+ case SPI_BUS:
+ case SDIO_BUS:
+ sii->curmap = regs = (void *)(unsigned long)addr;
+ sii->curwrap = (void *)(unsigned long)wrap;
+ break;
+
+ default:
+ regs = NULL;
+ break;
+ }
+
+ sii->curmap = regs;
+ sii->curidx = coreidx;
+
+ return regs;
+}
+
+/* Return the number of address spaces in current core */
+int ai_numaddrspaces(si_t *sih)
+{
+ return 2;
+}
+
+/* Return the address of the nth address space in the current core */
+u32 ai_addrspace(si_t *sih, uint asidx)
+{
+ si_info_t *sii;
+ uint cidx;
+
+ sii = SI_INFO(sih);
+ cidx = sii->curidx;
+
+ if (asidx == 0)
+ return sii->coresba[cidx];
+ else if (asidx == 1)
+ return sii->coresba2[cidx];
+ else {
+ SI_ERROR(("%s: Need to parse the erom again to find addr space %d\n", __func__, asidx));
+ return 0;
+ }
+}
+
+/* Return the size of the nth address space in the current core */
+u32 ai_addrspacesize(si_t *sih, uint asidx)
+{
+ si_info_t *sii;
+ uint cidx;
+
+ sii = SI_INFO(sih);
+ cidx = sii->curidx;
+
+ if (asidx == 0)
+ return sii->coresba_size[cidx];
+ else if (asidx == 1)
+ return sii->coresba2_size[cidx];
+ else {
+ SI_ERROR(("%s: Need to parse the erom again to find addr space %d\n", __func__, asidx));
+ return 0;
+ }
+}
+
+uint ai_flag(si_t *sih)
+{
+ si_info_t *sii;
+ aidmp_t *ai;
+
+ sii = SI_INFO(sih);
+ if (BCM47162_DMP()) {
+ SI_ERROR(("%s: Attempting to read MIPS DMP registers on 47162a0", __func__));
+ return sii->curidx;
+ }
+ ai = sii->curwrap;
+
+ return R_REG(&ai->oobselouta30) & 0x1f;
+}
+
+void ai_setint(si_t *sih, int siflag)
+{
+}
+
+uint ai_corevendor(si_t *sih)
+{
+ si_info_t *sii;
+ u32 cia;
+
+ sii = SI_INFO(sih);
+ cia = sii->cia[sii->curidx];
+ return (cia & CIA_MFG_MASK) >> CIA_MFG_SHIFT;
+}
+
+uint ai_corerev(si_t *sih)
+{
+ si_info_t *sii;
+ u32 cib;
+
+ sii = SI_INFO(sih);
+ cib = sii->cib[sii->curidx];
+ return (cib & CIB_REV_MASK) >> CIB_REV_SHIFT;
+}
+
+bool ai_iscoreup(si_t *sih)
+{
+ si_info_t *sii;
+ aidmp_t *ai;
+
+ sii = SI_INFO(sih);
+ ai = sii->curwrap;
+
+ return (((R_REG(&ai->ioctrl) & (SICF_FGC | SICF_CLOCK_EN)) ==
+ SICF_CLOCK_EN)
+ && ((R_REG(&ai->resetctrl) & AIRC_RESET) == 0));
+}
+
+void ai_core_cflags_wo(si_t *sih, u32 mask, u32 val)
+{
+ si_info_t *sii;
+ aidmp_t *ai;
+ u32 w;
+
+ sii = SI_INFO(sih);
+
+ if (BCM47162_DMP()) {
+ SI_ERROR(("%s: Accessing MIPS DMP register (ioctrl) on 47162a0",
+ __func__));
+ return;
+ }
+
+ ai = sii->curwrap;
+
+ if (mask || val) {
+ w = ((R_REG(&ai->ioctrl) & ~mask) | val);
+ W_REG(&ai->ioctrl, w);
+ }
+}
+
+u32 ai_core_cflags(si_t *sih, u32 mask, u32 val)
+{
+ si_info_t *sii;
+ aidmp_t *ai;
+ u32 w;
+
+ sii = SI_INFO(sih);
+ if (BCM47162_DMP()) {
+ SI_ERROR(("%s: Accessing MIPS DMP register (ioctrl) on 47162a0",
+ __func__));
+ return 0;
+ }
+
+ ai = sii->curwrap;
+
+ if (mask || val) {
+ w = ((R_REG(&ai->ioctrl) & ~mask) | val);
+ W_REG(&ai->ioctrl, w);
+ }
+
+ return R_REG(&ai->ioctrl);
+}
+
+u32 ai_core_sflags(si_t *sih, u32 mask, u32 val)
+{
+ si_info_t *sii;
+ aidmp_t *ai;
+ u32 w;
+
+ sii = SI_INFO(sih);
+ if (BCM47162_DMP()) {
+ SI_ERROR(("%s: Accessing MIPS DMP register (iostatus) on 47162a0", __func__));
+ return 0;
+ }
+
+ ai = sii->curwrap;
+
+ if (mask || val) {
+ w = ((R_REG(&ai->iostatus) & ~mask) | val);
+ W_REG(&ai->iostatus, w);
+ }
+
+ return R_REG(&ai->iostatus);
+}
+
+/* *************** from siutils.c ************** */
+/* local prototypes */
+static si_info_t *ai_doattach(si_info_t *sii, uint devid, void *regs,
+ uint bustype, void *sdh, char **vars,
+ uint *varsz);
+static bool ai_buscore_prep(si_info_t *sii, uint bustype, uint devid,
+ void *sdh);
+static bool ai_buscore_setup(si_info_t *sii, chipcregs_t *cc, uint bustype,
+ u32 savewin, uint *origidx, void *regs);
+static void ai_nvram_process(si_info_t *sii, char *pvars);
+
+/* dev path concatenation util */
+static char *ai_devpathvar(si_t *sih, char *var, int len, const char *name);
+static bool _ai_clkctl_cc(si_info_t *sii, uint mode);
+static bool ai_ispcie(si_info_t *sii);
+
+/* global variable to indicate reservation/release of gpio's */
+static u32 ai_gpioreservation;
+
+/*
+ * Allocate a si handle.
+ * devid - pci device id (used to determine chip#)
+ * osh - opaque OS handle
+ * regs - virtual address of initial core registers
+ * bustype - pci/sb/sdio/etc
+ * vars - pointer to a pointer area for "environment" variables
+ * varsz - pointer to int to return the size of the vars
+ */
+si_t *ai_attach(uint devid, void *regs, uint bustype,
+ void *sdh, char **vars, uint *varsz)
+{
+ si_info_t *sii;
+
+ /* alloc si_info_t */
+ sii = kmalloc(sizeof(si_info_t), GFP_ATOMIC);
+ if (sii == NULL) {
+ SI_ERROR(("si_attach: malloc failed!\n"));
+ return NULL;
+ }
+
+ if (ai_doattach(sii, devid, regs, bustype, sdh, vars, varsz) ==
+ NULL) {
+ kfree(sii);
+ return NULL;
+ }
+ sii->vars = vars ? *vars : NULL;
+ sii->varsz = varsz ? *varsz : 0;
+
+ return (si_t *) sii;
+}
+
+/* global kernel resource */
+static si_info_t ksii;
+
+static bool ai_buscore_prep(si_info_t *sii, uint bustype, uint devid,
+ void *sdh)
+{
+ /* kludge to enable the clock on the 4306 which lacks a slowclock */
+ if (bustype == PCI_BUS && !ai_ispcie(sii))
+ ai_clkctl_xtal(&sii->pub, XTAL | PLL, ON);
+ return true;
+}
+
+static bool ai_buscore_setup(si_info_t *sii, chipcregs_t *cc, uint bustype,
+ u32 savewin, uint *origidx, void *regs)
+{
+ bool pci, pcie;
+ uint i;
+ uint pciidx, pcieidx, pcirev, pcierev;
+
+ cc = ai_setcoreidx(&sii->pub, SI_CC_IDX);
+
+ /* get chipcommon rev */
+ sii->pub.ccrev = (int)ai_corerev(&sii->pub);
+
+ /* get chipcommon chipstatus */
+ if (sii->pub.ccrev >= 11)
+ sii->pub.chipst = R_REG(&cc->chipstatus);
+
+ /* get chipcommon capabilites */
+ sii->pub.cccaps = R_REG(&cc->capabilities);
+ /* get chipcommon extended capabilities */
+
+ if (sii->pub.ccrev >= 35)
+ sii->pub.cccaps_ext = R_REG(&cc->capabilities_ext);
+
+ /* get pmu rev and caps */
+ if (sii->pub.cccaps & CC_CAP_PMU) {
+ sii->pub.pmucaps = R_REG(&cc->pmucapabilities);
+ sii->pub.pmurev = sii->pub.pmucaps & PCAP_REV_MASK;
+ }
+
+ /* figure out bus/orignal core idx */
+ sii->pub.buscoretype = NODEV_CORE_ID;
+ sii->pub.buscorerev = NOREV;
+ sii->pub.buscoreidx = BADIDX;
+
+ pci = pcie = false;
+ pcirev = pcierev = NOREV;
+ pciidx = pcieidx = BADIDX;
+
+ for (i = 0; i < sii->numcores; i++) {
+ uint cid, crev;
+
+ ai_setcoreidx(&sii->pub, i);
+ cid = ai_coreid(&sii->pub);
+ crev = ai_corerev(&sii->pub);
+
+ /* Display cores found */
+ SI_VMSG(("CORE[%d]: id 0x%x rev %d base 0x%x regs 0x%p\n",
+ i, cid, crev, sii->coresba[i], sii->regs[i]));
+
+ if (bustype == PCI_BUS) {
+ if (cid == PCI_CORE_ID) {
+ pciidx = i;
+ pcirev = crev;
+ pci = true;
+ } else if (cid == PCIE_CORE_ID) {
+ pcieidx = i;
+ pcierev = crev;
+ pcie = true;
+ }
+ }
+
+ /* find the core idx before entering this func. */
+ if ((savewin && (savewin == sii->coresba[i])) ||
+ (regs == sii->regs[i]))
+ *origidx = i;
+ }
+
+ if (pci && pcie) {
+ if (ai_ispcie(sii))
+ pci = false;
+ else
+ pcie = false;
+ }
+ if (pci) {
+ sii->pub.buscoretype = PCI_CORE_ID;
+ sii->pub.buscorerev = pcirev;
+ sii->pub.buscoreidx = pciidx;
+ } else if (pcie) {
+ sii->pub.buscoretype = PCIE_CORE_ID;
+ sii->pub.buscorerev = pcierev;
+ sii->pub.buscoreidx = pcieidx;
+ }
+
+ SI_VMSG(("Buscore id/type/rev %d/0x%x/%d\n", sii->pub.buscoreidx,
+ sii->pub.buscoretype, sii->pub.buscorerev));
+
+ /* fixup necessary chip/core configurations */
+ if (sii->pub.bustype == PCI_BUS) {
+ if (SI_FAST(sii)) {
+ if (!sii->pch) {
+ sii->pch = (void *)pcicore_init(
+ &sii->pub, sii->pbus,
+ (void *)PCIEREGS(sii));
+ if (sii->pch == NULL)
+ return false;
+ }
+ }
+ if (ai_pci_fixcfg(&sii->pub)) {
+ SI_ERROR(("si_doattach: si_pci_fixcfg failed\n"));
+ return false;
+ }
+ }
+
+ /* return to the original core */
+ ai_setcoreidx(&sii->pub, *origidx);
+
+ return true;
+}
+
+static __used void ai_nvram_process(si_info_t *sii, char *pvars)
+{
+ uint w = 0;
+
+ /* get boardtype and boardrev */
+ switch (sii->pub.bustype) {
+ case PCI_BUS:
+ /* do a pci config read to get subsystem id and subvendor id */
+ pci_read_config_dword(sii->pbus, PCI_SUBSYSTEM_VENDOR_ID, &w);
+ /* Let nvram variables override subsystem Vend/ID */
+ sii->pub.boardvendor = (u16)ai_getdevpathintvar(&sii->pub,
+ "boardvendor");
+ if (sii->pub.boardvendor == 0)
+ sii->pub.boardvendor = w & 0xffff;
+ else
+ SI_ERROR(("Overriding boardvendor: 0x%x instead of "
+ "0x%x\n", sii->pub.boardvendor, w & 0xffff));
+ sii->pub.boardtype = (u16)ai_getdevpathintvar(&sii->pub,
+ "boardtype");
+ if (sii->pub.boardtype == 0)
+ sii->pub.boardtype = (w >> 16) & 0xffff;
+ else
+ SI_ERROR(("Overriding boardtype: 0x%x instead of 0x%x\n"
+ , sii->pub.boardtype, (w >> 16) & 0xffff));
+ break;
+
+ sii->pub.boardvendor = getintvar(pvars, "manfid");
+ sii->pub.boardtype = getintvar(pvars, "prodid");
+ break;
+
+ case SI_BUS:
+ case JTAG_BUS:
+ sii->pub.boardvendor = PCI_VENDOR_ID_BROADCOM;
+ sii->pub.boardtype = getintvar(pvars, "prodid");
+ if (pvars == NULL || (sii->pub.boardtype == 0)) {
+ sii->pub.boardtype = getintvar(NULL, "boardtype");
+ if (sii->pub.boardtype == 0)
+ sii->pub.boardtype = 0xffff;
+ }
+ break;
+ }
+
+ if (sii->pub.boardtype == 0) {
+ SI_ERROR(("si_doattach: unknown board type\n"));
+ }
+
+ sii->pub.boardflags = getintvar(pvars, "boardflags");
+}
+
+static si_info_t *ai_doattach(si_info_t *sii, uint devid,
+ void *regs, uint bustype, void *pbus,
+ char **vars, uint *varsz)
+{
+ struct si_pub *sih = &sii->pub;
+ u32 w, savewin;
+ chipcregs_t *cc;
+ char *pvars = NULL;
+ uint socitype;
+ uint origidx;
+
+ memset((unsigned char *) sii, 0, sizeof(si_info_t));
+
+ savewin = 0;
+
+ sih->buscoreidx = BADIDX;
+
+ sii->curmap = regs;
+ sii->pbus = pbus;
+
+ /* check to see if we are a si core mimic'ing a pci core */
+ if (bustype == PCI_BUS) {
+ pci_read_config_dword(sii->pbus, PCI_SPROM_CONTROL, &w);
+ if (w == 0xffffffff) {
+ SI_ERROR(("%s: incoming bus is PCI but it's a lie, "
+ " switching to SI devid:0x%x\n",
+ __func__, devid));
+ bustype = SI_BUS;
+ }
+ }
+
+ /* find Chipcommon address */
+ if (bustype == PCI_BUS) {
+ pci_read_config_dword(sii->pbus, PCI_BAR0_WIN, &savewin);
+ if (!GOODCOREADDR(savewin, SI_ENUM_BASE))
+ savewin = SI_ENUM_BASE;
+ pci_write_config_dword(sii->pbus, PCI_BAR0_WIN,
+ SI_ENUM_BASE);
+ cc = (chipcregs_t *) regs;
+ } else {
+ cc = (chipcregs_t *) REG_MAP(SI_ENUM_BASE, SI_CORE_SIZE);
+ }
+
+ sih->bustype = bustype;
+
+ /* bus/core/clk setup for register access */
+ if (!ai_buscore_prep(sii, bustype, devid, pbus)) {
+ SI_ERROR(("si_doattach: si_core_clk_prep failed %d\n",
+ bustype));
+ return NULL;
+ }
+
+ /*
+ * ChipID recognition.
+ * We assume we can read chipid at offset 0 from the regs arg.
+ * If we add other chiptypes (or if we need to support old sdio
+ * hosts w/o chipcommon), some way of recognizing them needs to
+ * be added here.
+ */
+ w = R_REG(&cc->chipid);
+ socitype = (w & CID_TYPE_MASK) >> CID_TYPE_SHIFT;
+ /* Might as wll fill in chip id rev & pkg */
+ sih->chip = w & CID_ID_MASK;
+ sih->chiprev = (w & CID_REV_MASK) >> CID_REV_SHIFT;
+ sih->chippkg = (w & CID_PKG_MASK) >> CID_PKG_SHIFT;
+
+ sih->issim = IS_SIM(sih->chippkg);
+
+ /* scan for cores */
+ if (socitype == SOCI_AI) {
+ SI_MSG(("Found chip type AI (0x%08x)\n", w));
+ /* pass chipc address instead of original core base */
+ ai_scan(&sii->pub, (void *)cc, devid);
+ } else {
+ SI_ERROR(("Found chip of unknown type (0x%08x)\n", w));
+ return NULL;
+ }
+ /* no cores found, bail out */
+ if (sii->numcores == 0) {
+ SI_ERROR(("si_doattach: could not find any cores\n"));
+ return NULL;
+ }
+ /* bus/core/clk setup */
+ origidx = SI_CC_IDX;
+ if (!ai_buscore_setup(sii, cc, bustype, savewin, &origidx, regs)) {
+ SI_ERROR(("si_doattach: si_buscore_setup failed\n"));
+ goto exit;
+ }
+
+ /* assume current core is CC */
+ if ((sii->pub.ccrev == 0x25)
+ &&
+ ((sih->chip == BCM43236_CHIP_ID
+ || sih->chip == BCM43235_CHIP_ID
+ || sih->chip == BCM43238_CHIP_ID)
+ && (sii->pub.chiprev <= 2))) {
+
+ if ((cc->chipstatus & CST43236_BP_CLK) != 0) {
+ uint clkdiv;
+ clkdiv = R_REG(&cc->clkdiv);
+ /* otp_clk_div is even number, 120/14 < 9mhz */
+ clkdiv = (clkdiv & ~CLKD_OTP) | (14 << CLKD_OTP_SHIFT);
+ W_REG(&cc->clkdiv, clkdiv);
+ SI_ERROR(("%s: set clkdiv to %x\n", __func__, clkdiv));
+ }
+ udelay(10);
+ }
+
+ /* Init nvram from flash if it exists */
+ nvram_init();
+
+ /* Init nvram from sprom/otp if they exist */
+ if (srom_var_init
+ (&sii->pub, bustype, regs, vars, varsz)) {
+ SI_ERROR(("si_doattach: srom_var_init failed: bad srom\n"));
+ goto exit;
+ }
+ pvars = vars ? *vars : NULL;
+ ai_nvram_process(sii, pvars);
+
+ /* === NVRAM, clock is ready === */
+ cc = (chipcregs_t *) ai_setcore(sih, CC_CORE_ID, 0);
+ W_REG(&cc->gpiopullup, 0);
+ W_REG(&cc->gpiopulldown, 0);
+ ai_setcoreidx(sih, origidx);
+
+ /* PMU specific initializations */
+ if (PMUCTL_ENAB(sih)) {
+ u32 xtalfreq;
+ si_pmu_init(sih);
+ si_pmu_chip_init(sih);
+ xtalfreq = getintvar(pvars, "xtalfreq");
+ /* If xtalfreq var not available, try to measure it */
+ if (xtalfreq == 0)
+ xtalfreq = si_pmu_measure_alpclk(sih);
+ si_pmu_pll_init(sih, xtalfreq);
+ si_pmu_res_init(sih);
+ si_pmu_swreg_init(sih);
+ }
+
+ /* setup the GPIO based LED powersave register */
+ w = getintvar(pvars, "leddc");
+ if (w == 0)
+ w = DEFAULT_GPIOTIMERVAL;
+ ai_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, gpiotimerval), ~0, w);
+
+ if (PCIE(sii)) {
+ pcicore_attach(sii->pch, pvars, SI_DOATTACH);
+ }
+
+ if ((sih->chip == BCM43224_CHIP_ID) ||
+ (sih->chip == BCM43421_CHIP_ID)) {
+ /*
+ * enable 12 mA drive strenth for 43224 and
+ * set chipControl register bit 15
+ */
+ if (sih->chiprev == 0) {
+ SI_MSG(("Applying 43224A0 WARs\n"));
+ ai_corereg(sih, SI_CC_IDX,
+ offsetof(chipcregs_t, chipcontrol),
+ CCTRL43224_GPIO_TOGGLE,
+ CCTRL43224_GPIO_TOGGLE);
+ si_pmu_chipcontrol(sih, 0, CCTRL_43224A0_12MA_LED_DRIVE,
+ CCTRL_43224A0_12MA_LED_DRIVE);
+ }
+ if (sih->chiprev >= 1) {
+ SI_MSG(("Applying 43224B0+ WARs\n"));
+ si_pmu_chipcontrol(sih, 0, CCTRL_43224B0_12MA_LED_DRIVE,
+ CCTRL_43224B0_12MA_LED_DRIVE);
+ }
+ }
+
+ if (sih->chip == BCM4313_CHIP_ID) {
+ /*
+ * enable 12 mA drive strenth for 4313 and
+ * set chipControl register bit 1
+ */
+ SI_MSG(("Applying 4313 WARs\n"));
+ si_pmu_chipcontrol(sih, 0, CCTRL_4313_12MA_LED_DRIVE,
+ CCTRL_4313_12MA_LED_DRIVE);
+ }
+
+ if (sih->chip == BCM4331_CHIP_ID) {
+ /* Enable Ext PA lines depending on chip package option */
+ ai_chipcontrl_epa4331(sih, true);
+ }
+
+ return sii;
+ exit:
+ if (sih->bustype == PCI_BUS) {
+ if (sii->pch)
+ pcicore_deinit(sii->pch);
+ sii->pch = NULL;
+ }
+
+ return NULL;
+}
+
+/* may be called with core in reset */
+void ai_detach(si_t *sih)
+{
+ si_info_t *sii;
+ uint idx;
+
+ struct si_pub *si_local = NULL;
+ bcopy(&sih, &si_local, sizeof(si_t **));
+
+ sii = SI_INFO(sih);
+
+ if (sii == NULL)
+ return;
+
+ if (sih->bustype == SI_BUS)
+ for (idx = 0; idx < SI_MAXCORES; idx++)
+ if (sii->regs[idx]) {
+ iounmap(sii->regs[idx]);
+ sii->regs[idx] = NULL;
+ }
+
+ nvram_exit(); /* free up nvram buffers */
+
+ if (sih->bustype == PCI_BUS) {
+ if (sii->pch)
+ pcicore_deinit(sii->pch);
+ sii->pch = NULL;
+ }
+
+ if (sii != &ksii)
+ kfree(sii);
+}
+
+/* register driver interrupt disabling and restoring callback functions */
+void
+ai_register_intr_callback(si_t *sih, void *intrsoff_fn, void *intrsrestore_fn,
+ void *intrsenabled_fn, void *intr_arg)
+{
+ si_info_t *sii;
+
+ sii = SI_INFO(sih);
+ sii->intr_arg = intr_arg;
+ sii->intrsoff_fn = (si_intrsoff_t) intrsoff_fn;
+ sii->intrsrestore_fn = (si_intrsrestore_t) intrsrestore_fn;
+ sii->intrsenabled_fn = (si_intrsenabled_t) intrsenabled_fn;
+ /* save current core id. when this function called, the current core
+ * must be the core which provides driver functions(il, et, wl, etc.)
+ */
+ sii->dev_coreid = sii->coreid[sii->curidx];
+}
+
+void ai_deregister_intr_callback(si_t *sih)
+{
+ si_info_t *sii;
+
+ sii = SI_INFO(sih);
+ sii->intrsoff_fn = NULL;
+}
+
+uint ai_coreid(si_t *sih)
+{
+ si_info_t *sii;
+
+ sii = SI_INFO(sih);
+ return sii->coreid[sii->curidx];
+}
+
+uint ai_coreidx(si_t *sih)
+{
+ si_info_t *sii;
+
+ sii = SI_INFO(sih);
+ return sii->curidx;
+}
+
+bool ai_backplane64(si_t *sih)
+{
+ return (sih->cccaps & CC_CAP_BKPLN64) != 0;
+}
+
+/* return index of coreid or BADIDX if not found */
+uint ai_findcoreidx(si_t *sih, uint coreid, uint coreunit)
+{
+ si_info_t *sii;
+ uint found;
+ uint i;
+
+ sii = SI_INFO(sih);
+
+ found = 0;
+
+ for (i = 0; i < sii->numcores; i++)
+ if (sii->coreid[i] == coreid) {
+ if (found == coreunit)
+ return i;
+ found++;
+ }
+
+ return BADIDX;
+}
+
+/*
+ * This function changes logical "focus" to the indicated core;
+ * must be called with interrupts off.
+ * Moreover, callers should keep interrupts off during switching
+ * out of and back to d11 core.
+ */
+void *ai_setcore(si_t *sih, uint coreid, uint coreunit)
+{
+ uint idx;
+
+ idx = ai_findcoreidx(sih, coreid, coreunit);
+ if (!GOODIDX(idx))
+ return NULL;
+
+ return ai_setcoreidx(sih, idx);
+}
+
+/* Turn off interrupt as required by ai_setcore, before switch core */
+void *ai_switch_core(si_t *sih, uint coreid, uint *origidx, uint *intr_val)
+{
+ void *cc;
+ si_info_t *sii;
+
+ sii = SI_INFO(sih);
+
+ if (SI_FAST(sii)) {
+ /* Overloading the origidx variable to remember the coreid,
+ * this works because the core ids cannot be confused with
+ * core indices.
+ */
+ *origidx = coreid;
+ if (coreid == CC_CORE_ID)
+ return (void *)CCREGS_FAST(sii);
+ else if (coreid == sih->buscoretype)
+ return (void *)PCIEREGS(sii);
+ }
+ INTR_OFF(sii, *intr_val);
+ *origidx = sii->curidx;
+ cc = ai_setcore(sih, coreid, 0);
+ return cc;
+}
+
+/* restore coreidx and restore interrupt */
+void ai_restore_core(si_t *sih, uint coreid, uint intr_val)
+{
+ si_info_t *sii;
+
+ sii = SI_INFO(sih);
+ if (SI_FAST(sii)
+ && ((coreid == CC_CORE_ID) || (coreid == sih->buscoretype)))
+ return;
+
+ ai_setcoreidx(sih, coreid);
+ INTR_RESTORE(sii, intr_val);
+}
+
+void ai_write_wrapperreg(si_t *sih, u32 offset, u32 val)
+{
+ si_info_t *sii = SI_INFO(sih);
+ u32 *w = (u32 *) sii->curwrap;
+ W_REG(w + (offset / 4), val);
+ return;
+}
+
+/*
+ * Switch to 'coreidx', issue a single arbitrary 32bit register mask&set
+ * operation, switch back to the original core, and return the new value.
+ *
+ * When using the silicon backplane, no fiddling with interrupts or core
+ * switches is needed.
+ *
+ * Also, when using pci/pcie, we can optimize away the core switching for pci
+ * registers and (on newer pci cores) chipcommon registers.
+ */
+uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)
+{
+ uint origidx = 0;
+ u32 *r = NULL;
+ uint w;
+ uint intr_val = 0;
+ bool fast = false;
+ si_info_t *sii;
+
+ sii = SI_INFO(sih);
+
+ if (coreidx >= SI_MAXCORES)
+ return 0;
+
+ if (sih->bustype == SI_BUS) {
+ /* If internal bus, we can always get at everything */
+ fast = true;
+ /* map if does not exist */
+ if (!sii->regs[coreidx]) {
+ sii->regs[coreidx] = REG_MAP(sii->coresba[coreidx],
+ SI_CORE_SIZE);
+ }
+ r = (u32 *) ((unsigned char *) sii->regs[coreidx] + regoff);
+ } else if (sih->bustype == PCI_BUS) {
+ /*
+ * If pci/pcie, we can get at pci/pcie regs
+ * and on newer cores to chipc
+ */
+ if ((sii->coreid[coreidx] == CC_CORE_ID) && SI_FAST(sii)) {
+ /* Chipc registers are mapped at 12KB */
+
+ fast = true;
+ r = (u32 *) ((char *)sii->curmap +
+ PCI_16KB0_CCREGS_OFFSET + regoff);
+ } else if (sii->pub.buscoreidx == coreidx) {
+ /*
+ * pci registers are at either in the last 2KB of
+ * an 8KB window or, in pcie and pci rev 13 at 8KB
+ */
+ fast = true;
+ if (SI_FAST(sii))
+ r = (u32 *) ((char *)sii->curmap +
+ PCI_16KB0_PCIREGS_OFFSET +
+ regoff);
+ else
+ r = (u32 *) ((char *)sii->curmap +
+ ((regoff >= SBCONFIGOFF) ?
+ PCI_BAR0_PCISBR_OFFSET :
+ PCI_BAR0_PCIREGS_OFFSET) +
+ regoff);
+ }
+ }
+
+ if (!fast) {
+ INTR_OFF(sii, intr_val);
+
+ /* save current core index */
+ origidx = ai_coreidx(&sii->pub);
+
+ /* switch core */
+ r = (u32 *) ((unsigned char *) ai_setcoreidx(&sii->pub, coreidx)
+ + regoff);
+ }
+
+ /* mask and set */
+ if (mask || val) {
+ w = (R_REG(r) & ~mask) | val;
+ W_REG(r, w);
+ }
+
+ /* readback */
+ w = R_REG(r);
+
+ if (!fast) {
+ /* restore core index */
+ if (origidx != coreidx)
+ ai_setcoreidx(&sii->pub, origidx);
+
+ INTR_RESTORE(sii, intr_val);
+ }
+
+ return w;
+}
+
+void ai_core_disable(si_t *sih, u32 bits)
+{
+ si_info_t *sii;
+ u32 dummy;
+ aidmp_t *ai;
+
+ sii = SI_INFO(sih);
+
+ ai = sii->curwrap;
+
+ /* if core is already in reset, just return */
+ if (R_REG(&ai->resetctrl) & AIRC_RESET)
+ return;
+
+ W_REG(&ai->ioctrl, bits);
+ dummy = R_REG(&ai->ioctrl);
+ udelay(10);
+
+ W_REG(&ai->resetctrl, AIRC_RESET);
+ udelay(1);
+}
+
+/* reset and re-enable a core
+ * inputs:
+ * bits - core specific bits that are set during and after reset sequence
+ * resetbits - core specific bits that are set only during reset sequence
+ */
+void ai_core_reset(si_t *sih, u32 bits, u32 resetbits)
+{
+ si_info_t *sii;
+ aidmp_t *ai;
+ u32 dummy;
+
+ sii = SI_INFO(sih);
+ ai = sii->curwrap;
+
+ /*
+ * Must do the disable sequence first to work
+ * for arbitrary current core state.
+ */
+ ai_core_disable(sih, (bits | resetbits));
+
+ /*
+ * Now do the initialization sequence.
+ */
+ W_REG(&ai->ioctrl, (bits | SICF_FGC | SICF_CLOCK_EN));
+ dummy = R_REG(&ai->ioctrl);
+ W_REG(&ai->resetctrl, 0);
+ udelay(1);
+
+ W_REG(&ai->ioctrl, (bits | SICF_CLOCK_EN));
+ dummy = R_REG(&ai->ioctrl);
+ udelay(1);
+}
+
+/* return the slow clock source - LPO, XTAL, or PCI */
+static uint ai_slowclk_src(si_info_t *sii)
+{
+ chipcregs_t *cc;
+ u32 val;
+
+ if (sii->pub.ccrev < 6) {
+ if (sii->pub.bustype == PCI_BUS) {
+ pci_read_config_dword(sii->pbus, PCI_GPIO_OUT,
+ &val);
+ if (val & PCI_CFG_GPIO_SCS)
+ return SCC_SS_PCI;
+ }
+ return SCC_SS_XTAL;
+ } else if (sii->pub.ccrev < 10) {
+ cc = (chipcregs_t *) ai_setcoreidx(&sii->pub, sii->curidx);
+ return R_REG(&cc->slow_clk_ctl) & SCC_SS_MASK;
+ } else /* Insta-clock */
+ return SCC_SS_XTAL;
+}
+
+/*
+* return the ILP (slowclock) min or max frequency
+* precondition: we've established the chip has dynamic clk control
+*/
+static uint ai_slowclk_freq(si_info_t *sii, bool max_freq, chipcregs_t *cc)
+{
+ u32 slowclk;
+ uint div;
+
+ slowclk = ai_slowclk_src(sii);
+ if (sii->pub.ccrev < 6) {
+ if (slowclk == SCC_SS_PCI)
+ return max_freq ? (PCIMAXFREQ / 64)
+ : (PCIMINFREQ / 64);
+ else
+ return max_freq ? (XTALMAXFREQ / 32)
+ : (XTALMINFREQ / 32);
+ } else if (sii->pub.ccrev < 10) {
+ div = 4 *
+ (((R_REG(&cc->slow_clk_ctl) & SCC_CD_MASK) >>
+ SCC_CD_SHIFT) + 1);
+ if (slowclk == SCC_SS_LPO)
+ return max_freq ? LPOMAXFREQ : LPOMINFREQ;
+ else if (slowclk == SCC_SS_XTAL)
+ return max_freq ? (XTALMAXFREQ / div)
+ : (XTALMINFREQ / div);
+ else if (slowclk == SCC_SS_PCI)
+ return max_freq ? (PCIMAXFREQ / div)
+ : (PCIMINFREQ / div);
+ } else {
+ /* Chipc rev 10 is InstaClock */
+ div = R_REG(&cc->system_clk_ctl) >> SYCC_CD_SHIFT;
+ div = 4 * (div + 1);
+ return max_freq ? XTALMAXFREQ : (XTALMINFREQ / div);
+ }
+ return 0;
+}
+
+static void ai_clkctl_setdelay(si_info_t *sii, void *chipcregs)
+{
+ chipcregs_t *cc = (chipcregs_t *) chipcregs;
+ uint slowmaxfreq, pll_delay, slowclk;
+ uint pll_on_delay, fref_sel_delay;
+
+ pll_delay = PLL_DELAY;
+
+ /*
+ * If the slow clock is not sourced by the xtal then
+ * add the xtal_on_delay since the xtal will also be
+ * powered down by dynamic clk control logic.
+ */
+
+ slowclk = ai_slowclk_src(sii);
+ if (slowclk != SCC_SS_XTAL)
+ pll_delay += XTAL_ON_DELAY;
+
+ /* Starting with 4318 it is ILP that is used for the delays */
+ slowmaxfreq =
+ ai_slowclk_freq(sii, (sii->pub.ccrev >= 10) ? false : true, cc);
+
+ pll_on_delay = ((slowmaxfreq * pll_delay) + 999999) / 1000000;
+ fref_sel_delay = ((slowmaxfreq * FREF_DELAY) + 999999) / 1000000;
+
+ W_REG(&cc->pll_on_delay, pll_on_delay);
+ W_REG(&cc->fref_sel_delay, fref_sel_delay);
+}
+
+/* initialize power control delay registers */
+void ai_clkctl_init(si_t *sih)
+{
+ si_info_t *sii;
+ uint origidx = 0;
+ chipcregs_t *cc;
+ bool fast;
+
+ if (!CCCTL_ENAB(sih))
+ return;
+
+ sii = SI_INFO(sih);
+ fast = SI_FAST(sii);
+ if (!fast) {
+ origidx = sii->curidx;
+ cc = (chipcregs_t *) ai_setcore(sih, CC_CORE_ID, 0);
+ if (cc == NULL)
+ return;
+ } else {
+ cc = (chipcregs_t *) CCREGS_FAST(sii);
+ if (cc == NULL)
+ return;
+ }
+
+ /* set all Instaclk chip ILP to 1 MHz */
+ if (sih->ccrev >= 10)
+ SET_REG(&cc->system_clk_ctl, SYCC_CD_MASK,
+ (ILP_DIV_1MHZ << SYCC_CD_SHIFT));
+
+ ai_clkctl_setdelay(sii, (void *)cc);
+
+ if (!fast)
+ ai_setcoreidx(sih, origidx);
+}
+
+/*
+ * return the value suitable for writing to the
+ * dot11 core FAST_PWRUP_DELAY register
+ */
+u16 ai_clkctl_fast_pwrup_delay(si_t *sih)
+{
+ si_info_t *sii;
+ uint origidx = 0;
+ chipcregs_t *cc;
+ uint slowminfreq;
+ u16 fpdelay;
+ uint intr_val = 0;
+ bool fast;
+
+ sii = SI_INFO(sih);
+ if (PMUCTL_ENAB(sih)) {
+ INTR_OFF(sii, intr_val);
+ fpdelay = si_pmu_fast_pwrup_delay(sih);
+ INTR_RESTORE(sii, intr_val);
+ return fpdelay;
+ }
+
+ if (!CCCTL_ENAB(sih))
+ return 0;
+
+ fast = SI_FAST(sii);
+ fpdelay = 0;
+ if (!fast) {
+ origidx = sii->curidx;
+ INTR_OFF(sii, intr_val);
+ cc = (chipcregs_t *) ai_setcore(sih, CC_CORE_ID, 0);
+ if (cc == NULL)
+ goto done;
+ } else {
+ cc = (chipcregs_t *) CCREGS_FAST(sii);
+ if (cc == NULL)
+ goto done;
+ }
+
+ slowminfreq = ai_slowclk_freq(sii, false, cc);
+ fpdelay = (((R_REG(&cc->pll_on_delay) + 2) * 1000000) +
+ (slowminfreq - 1)) / slowminfreq;
+
+ done:
+ if (!fast) {
+ ai_setcoreidx(sih, origidx);
+ INTR_RESTORE(sii, intr_val);
+ }
+ return fpdelay;
+}
+
+/* turn primary xtal and/or pll off/on */
+int ai_clkctl_xtal(si_t *sih, uint what, bool on)
+{
+ si_info_t *sii;
+ u32 in, out, outen;
+
+ sii = SI_INFO(sih);
+
+ switch (sih->bustype) {
+
+ case PCI_BUS:
+ /* pcie core doesn't have any mapping to control the xtal pu */
+ if (PCIE(sii))
+ return -1;
+
+ pci_read_config_dword(sii->pbus, PCI_GPIO_IN, &in);
+ pci_read_config_dword(sii->pbus, PCI_GPIO_OUT, &out);
+ pci_read_config_dword(sii->pbus, PCI_GPIO_OUTEN, &outen);
+
+ /*
+ * Avoid glitching the clock if GPRS is already using it.
+ * We can't actually read the state of the PLLPD so we infer it
+ * by the value of XTAL_PU which *is* readable via gpioin.
+ */
+ if (on && (in & PCI_CFG_GPIO_XTAL))
+ return 0;
+
+ if (what & XTAL)
+ outen |= PCI_CFG_GPIO_XTAL;
+ if (what & PLL)
+ outen |= PCI_CFG_GPIO_PLL;
+
+ if (on) {
+ /* turn primary xtal on */
+ if (what & XTAL) {
+ out |= PCI_CFG_GPIO_XTAL;
+ if (what & PLL)
+ out |= PCI_CFG_GPIO_PLL;
+ pci_write_config_dword(sii->pbus,
+ PCI_GPIO_OUT, out);
+ pci_write_config_dword(sii->pbus,
+ PCI_GPIO_OUTEN, outen);
+ udelay(XTAL_ON_DELAY);
+ }
+
+ /* turn pll on */
+ if (what & PLL) {
+ out &= ~PCI_CFG_GPIO_PLL;
+ pci_write_config_dword(sii->pbus,
+ PCI_GPIO_OUT, out);
+ mdelay(2);
+ }
+ } else {
+ if (what & XTAL)
+ out &= ~PCI_CFG_GPIO_XTAL;
+ if (what & PLL)
+ out |= PCI_CFG_GPIO_PLL;
+ pci_write_config_dword(sii->pbus,
+ PCI_GPIO_OUT, out);
+ pci_write_config_dword(sii->pbus,
+ PCI_GPIO_OUTEN, outen);
+ }
+
+ default:
+ return -1;
+ }
+
+ return 0;
+}
+
+/*
+ * clock control policy function throught chipcommon
+ *
+ * set dynamic clk control mode (forceslow, forcefast, dynamic)
+ * returns true if we are forcing fast clock
+ * this is a wrapper over the next internal function
+ * to allow flexible policy settings for outside caller
+ */
+bool ai_clkctl_cc(si_t *sih, uint mode)
+{
+ si_info_t *sii;
+
+ sii = SI_INFO(sih);
+
+ /* chipcommon cores prior to rev6 don't support dynamic clock control */
+ if (sih->ccrev < 6)
+ return false;
+
+ if (PCI_FORCEHT(sii))
+ return mode == CLK_FAST;
+
+ return _ai_clkctl_cc(sii, mode);
+}
+
+/* clk control mechanism through chipcommon, no policy checking */
+static bool _ai_clkctl_cc(si_info_t *sii, uint mode)
+{
+ uint origidx = 0;
+ chipcregs_t *cc;
+ u32 scc;
+ uint intr_val = 0;
+ bool fast = SI_FAST(sii);
+
+ /* chipcommon cores prior to rev6 don't support dynamic clock control */
+ if (sii->pub.ccrev < 6)
+ return false;
+
+ if (!fast) {
+ INTR_OFF(sii, intr_val);
+ origidx = sii->curidx;
+
+ if ((sii->pub.bustype == SI_BUS) &&
+ ai_setcore(&sii->pub, MIPS33_CORE_ID, 0) &&
+ (ai_corerev(&sii->pub) <= 7) && (sii->pub.ccrev >= 10))
+ goto done;
+
+ cc = (chipcregs_t *) ai_setcore(&sii->pub, CC_CORE_ID, 0);
+ } else {
+ cc = (chipcregs_t *) CCREGS_FAST(sii);
+ if (cc == NULL)
+ goto done;
+ }
+
+ if (!CCCTL_ENAB(&sii->pub) && (sii->pub.ccrev < 20))
+ goto done;
+
+ switch (mode) {
+ case CLK_FAST: /* FORCEHT, fast (pll) clock */
+ if (sii->pub.ccrev < 10) {
+ /*
+ * don't forget to force xtal back
+ * on before we clear SCC_DYN_XTAL..
+ */
+ ai_clkctl_xtal(&sii->pub, XTAL, ON);
+ SET_REG(&cc->slow_clk_ctl,
+ (SCC_XC | SCC_FS | SCC_IP), SCC_IP);
+ } else if (sii->pub.ccrev < 20) {
+ OR_REG(&cc->system_clk_ctl, SYCC_HR);
+ } else {
+ OR_REG(&cc->clk_ctl_st, CCS_FORCEHT);
+ }
+
+ /* wait for the PLL */
+ if (PMUCTL_ENAB(&sii->pub)) {
+ u32 htavail = CCS_HTAVAIL;
+ SPINWAIT(((R_REG(&cc->clk_ctl_st) & htavail)
+ == 0), PMU_MAX_TRANSITION_DLY);
+ } else {
+ udelay(PLL_DELAY);
+ }
+ break;
+
+ case CLK_DYNAMIC: /* enable dynamic clock control */
+ if (sii->pub.ccrev < 10) {
+ scc = R_REG(&cc->slow_clk_ctl);
+ scc &= ~(SCC_FS | SCC_IP | SCC_XC);
+ if ((scc & SCC_SS_MASK) != SCC_SS_XTAL)
+ scc |= SCC_XC;
+ W_REG(&cc->slow_clk_ctl, scc);
+
+ /*
+ * for dynamic control, we have to
+ * release our xtal_pu "force on"
+ */
+ if (scc & SCC_XC)
+ ai_clkctl_xtal(&sii->pub, XTAL, OFF);
+ } else if (sii->pub.ccrev < 20) {
+ /* Instaclock */
+ AND_REG(&cc->system_clk_ctl, ~SYCC_HR);
+ } else {
+ AND_REG(&cc->clk_ctl_st, ~CCS_FORCEHT);
+ }
+ break;
+
+ default:
+ break;
+ }
+
+ done:
+ if (!fast) {
+ ai_setcoreidx(&sii->pub, origidx);
+ INTR_RESTORE(sii, intr_val);
+ }
+ return mode == CLK_FAST;
+}
+
+/* Build device path. Support SI, PCI, and JTAG for now. */
+int ai_devpath(si_t *sih, char *path, int size)
+{
+ int slen;
+
+ if (!path || size <= 0)
+ return -1;
+
+ switch (sih->bustype) {
+ case SI_BUS:
+ case JTAG_BUS:
+ slen = snprintf(path, (size_t) size, "sb/%u/", ai_coreidx(sih));
+ break;
+ case PCI_BUS:
+ slen = snprintf(path, (size_t) size, "pci/%u/%u/",
+ ((struct pci_dev *)((SI_INFO(sih))->pbus))->bus->number,
+ PCI_SLOT(
+ ((struct pci_dev *)((SI_INFO(sih))->pbus))->devfn));
+ break;
+
+ default:
+ slen = -1;
+ break;
+ }
+
+ if (slen < 0 || slen >= size) {
+ path[0] = '\0';
+ return -1;
+ }
+
+ return 0;
+}
+
+/* Get a variable, but only if it has a devpath prefix */
+char *ai_getdevpathvar(si_t *sih, const char *name)
+{
+ char varname[SI_DEVPATH_BUFSZ + 32];
+
+ ai_devpathvar(sih, varname, sizeof(varname), name);
+
+ return getvar(NULL, varname);
+}
+
+/* Get a variable, but only if it has a devpath prefix */
+int ai_getdevpathintvar(si_t *sih, const char *name)
+{
+#if defined(BCMBUSTYPE) && (BCMBUSTYPE == SI_BUS)
+ return getintvar(NULL, name);
+#else
+ char varname[SI_DEVPATH_BUFSZ + 32];
+
+ ai_devpathvar(sih, varname, sizeof(varname), name);
+
+ return getintvar(NULL, varname);
+#endif
+}
+
+char *ai_getnvramflvar(si_t *sih, const char *name)
+{
+ return getvar(NULL, name);
+}
+
+/* Concatenate the dev path with a varname into the given 'var' buffer
+ * and return the 'var' pointer. Nothing is done to the arguments if
+ * len == 0 or var is NULL, var is still returned. On overflow, the
+ * first char will be set to '\0'.
+ */
+static char *ai_devpathvar(si_t *sih, char *var, int len, const char *name)
+{
+ uint path_len;
+
+ if (!var || len <= 0)
+ return var;
+
+ if (ai_devpath(sih, var, len) == 0) {
+ path_len = strlen(var);
+
+ if (strlen(name) + 1 > (uint) (len - path_len))
+ var[0] = '\0';
+ else
+ strncpy(var + path_len, name, len - path_len - 1);
+ }
+
+ return var;
+}
+
+/* return true if PCIE capability exists in the pci config space */
+static __used bool ai_ispcie(si_info_t *sii)
+{
+ u8 cap_ptr;
+
+ if (sii->pub.bustype != PCI_BUS)
+ return false;
+
+ cap_ptr =
+ pcicore_find_pci_capability(sii->pbus, PCI_CAP_ID_EXP, NULL,
+ NULL);
+ if (!cap_ptr)
+ return false;
+
+ return true;
+}
+
+bool ai_pci_war16165(si_t *sih)
+{
+ si_info_t *sii;
+
+ sii = SI_INFO(sih);
+
+ return PCI(sii) && (sih->buscorerev <= 10);
+}
+
+void ai_pci_up(si_t *sih)
+{
+ si_info_t *sii;
+
+ sii = SI_INFO(sih);
+
+ /* if not pci bus, we're done */
+ if (sih->bustype != PCI_BUS)
+ return;
+
+ if (PCI_FORCEHT(sii))
+ _ai_clkctl_cc(sii, CLK_FAST);
+
+ if (PCIE(sii))
+ pcicore_up(sii->pch, SI_PCIUP);
+
+}
+
+/* Unconfigure and/or apply various WARs when system is going to sleep mode */
+void ai_pci_sleep(si_t *sih)
+{
+ si_info_t *sii;
+
+ sii = SI_INFO(sih);
+
+ pcicore_sleep(sii->pch);
+}
+
+/* Unconfigure and/or apply various WARs when going down */
+void ai_pci_down(si_t *sih)
+{
+ si_info_t *sii;
+
+ sii = SI_INFO(sih);
+
+ /* if not pci bus, we're done */
+ if (sih->bustype != PCI_BUS)
+ return;
+
+ /* release FORCEHT since chip is going to "down" state */
+ if (PCI_FORCEHT(sii))
+ _ai_clkctl_cc(sii, CLK_DYNAMIC);
+
+ pcicore_down(sii->pch, SI_PCIDOWN);
+}
+
+/*
+ * Configure the pci core for pci client (NIC) action
+ * coremask is the bitvec of cores by index to be enabled.
+ */
+void ai_pci_setup(si_t *sih, uint coremask)
+{
+ si_info_t *sii;
+ struct sbpciregs *pciregs = NULL;
+ u32 siflag = 0, w;
+ uint idx = 0;
+
+ sii = SI_INFO(sih);
+
+ if (sii->pub.bustype != PCI_BUS)
+ return;
+
+ if (PCI(sii)) {
+ /* get current core index */
+ idx = sii->curidx;
+
+ /* we interrupt on this backplane flag number */
+ siflag = ai_flag(sih);
+
+ /* switch over to pci core */
+ pciregs = ai_setcoreidx(sih, sii->pub.buscoreidx);
+ }
+
+ /*
+ * Enable sb->pci interrupts. Assume
+ * PCI rev 2.3 support was added in pci core rev 6 and things changed..
+ */
+ if (PCIE(sii) || (PCI(sii) && ((sii->pub.buscorerev) >= 6))) {
+ /* pci config write to set this core bit in PCIIntMask */
+ pci_read_config_dword(sii->pbus, PCI_INT_MASK, &w);
+ w |= (coremask << PCI_SBIM_SHIFT);
+ pci_write_config_dword(sii->pbus, PCI_INT_MASK, w);
+ } else {
+ /* set sbintvec bit for our flag number */
+ ai_setint(sih, siflag);
+ }
+
+ if (PCI(sii)) {
+ OR_REG(&pciregs->sbtopci2,
+ (SBTOPCI_PREF | SBTOPCI_BURST));
+ if (sii->pub.buscorerev >= 11) {
+ OR_REG(&pciregs->sbtopci2,
+ SBTOPCI_RC_READMULTI);
+ w = R_REG(&pciregs->clkrun);
+ W_REG(&pciregs->clkrun,
+ (w | PCI_CLKRUN_DSBL));
+ w = R_REG(&pciregs->clkrun);
+ }
+
+ /* switch back to previous core */
+ ai_setcoreidx(sih, idx);
+ }
+}
+
+/*
+ * Fixup SROMless PCI device's configuration.
+ * The current core may be changed upon return.
+ */
+int ai_pci_fixcfg(si_t *sih)
+{
+ uint origidx, pciidx;
+ struct sbpciregs *pciregs = NULL;
+ sbpcieregs_t *pcieregs = NULL;
+ void *regs = NULL;
+ u16 val16, *reg16 = NULL;
+
+ si_info_t *sii = SI_INFO(sih);
+
+ /* Fixup PI in SROM shadow area to enable the correct PCI core access */
+ /* save the current index */
+ origidx = ai_coreidx(&sii->pub);
+
+ /* check 'pi' is correct and fix it if not */
+ if (sii->pub.buscoretype == PCIE_CORE_ID) {
+ pcieregs = ai_setcore(&sii->pub, PCIE_CORE_ID, 0);
+ regs = pcieregs;
+ reg16 = &pcieregs->sprom[SRSH_PI_OFFSET];
+ } else if (sii->pub.buscoretype == PCI_CORE_ID) {
+ pciregs = ai_setcore(&sii->pub, PCI_CORE_ID, 0);
+ regs = pciregs;
+ reg16 = &pciregs->sprom[SRSH_PI_OFFSET];
+ }
+ pciidx = ai_coreidx(&sii->pub);
+ val16 = R_REG(reg16);
+ if (((val16 & SRSH_PI_MASK) >> SRSH_PI_SHIFT) != (u16) pciidx) {
+ val16 =
+ (u16) (pciidx << SRSH_PI_SHIFT) | (val16 &
+ ~SRSH_PI_MASK);
+ W_REG(reg16, val16);
+ }
+
+ /* restore the original index */
+ ai_setcoreidx(&sii->pub, origidx);
+
+ pcicore_hwup(sii->pch);
+ return 0;
+}
+
+/* mask&set gpiocontrol bits */
+u32 ai_gpiocontrol(si_t *sih, u32 mask, u32 val, u8 priority)
+{
+ uint regoff;
+
+ regoff = 0;
+
+ /* gpios could be shared on router platforms
+ * ignore reservation if it's high priority (e.g., test apps)
+ */
+ if ((priority != GPIO_HI_PRIORITY) &&
+ (sih->bustype == SI_BUS) && (val || mask)) {
+ mask = priority ? (ai_gpioreservation & mask) :
+ ((ai_gpioreservation | mask) & ~(ai_gpioreservation));
+ val &= mask;
+ }
+
+ regoff = offsetof(chipcregs_t, gpiocontrol);
+ return ai_corereg(sih, SI_CC_IDX, regoff, mask, val);
+}
+
+void ai_chipcontrl_epa4331(si_t *sih, bool on)
+{
+ si_info_t *sii;
+ chipcregs_t *cc;
+ uint origidx;
+ u32 val;
+
+ sii = SI_INFO(sih);
+ origidx = ai_coreidx(sih);
+
+ cc = (chipcregs_t *) ai_setcore(sih, CC_CORE_ID, 0);
+
+ val = R_REG(&cc->chipcontrol);
+
+ if (on) {
+ if (sih->chippkg == 9 || sih->chippkg == 0xb) {
+ /* Ext PA Controls for 4331 12x9 Package */
+ W_REG(&cc->chipcontrol, val |
+ (CCTRL4331_EXTPA_EN |
+ CCTRL4331_EXTPA_ON_GPIO2_5));
+ } else {
+ /* Ext PA Controls for 4331 12x12 Package */
+ W_REG(&cc->chipcontrol,
+ val | (CCTRL4331_EXTPA_EN));
+ }
+ } else {
+ val &= ~(CCTRL4331_EXTPA_EN | CCTRL4331_EXTPA_ON_GPIO2_5);
+ W_REG(&cc->chipcontrol, val);
+ }
+
+ ai_setcoreidx(sih, origidx);
+}
+
+/* Enable BT-COEX & Ex-PA for 4313 */
+void ai_epa_4313war(si_t *sih)
+{
+ si_info_t *sii;
+ chipcregs_t *cc;
+ uint origidx;
+
+ sii = SI_INFO(sih);
+ origidx = ai_coreidx(sih);
+
+ cc = (chipcregs_t *) ai_setcore(sih, CC_CORE_ID, 0);
+
+ /* EPA Fix */
+ W_REG(&cc->gpiocontrol,
+ R_REG(&cc->gpiocontrol) | GPIO_CTRL_EPA_EN_MASK);
+
+ ai_setcoreidx(sih, origidx);
+}
+
+/* check if the device is removed */
+bool ai_deviceremoved(si_t *sih)
+{
+ u32 w;
+ si_info_t *sii;
+
+ sii = SI_INFO(sih);
+
+ switch (sih->bustype) {
+ case PCI_BUS:
+ pci_read_config_dword(sii->pbus, PCI_VENDOR_ID, &w);
+ if ((w & 0xFFFF) != PCI_VENDOR_ID_BROADCOM)
+ return true;
+ break;
+ }
+ return false;
+}
+
+bool ai_is_sprom_available(si_t *sih)
+{
+ if (sih->ccrev >= 31) {
+ si_info_t *sii;
+ uint origidx;
+ chipcregs_t *cc;
+ u32 sromctrl;
+
+ if ((sih->cccaps & CC_CAP_SROM) == 0)
+ return false;
+
+ sii = SI_INFO(sih);
+ origidx = sii->curidx;
+ cc = ai_setcoreidx(sih, SI_CC_IDX);
+ sromctrl = R_REG(&cc->sromcontrol);
+ ai_setcoreidx(sih, origidx);
+ return sromctrl & SRC_PRESENT;
+ }
+
+ switch (sih->chip) {
+ case BCM4329_CHIP_ID:
+ return (sih->chipst & CST4329_SPROM_SEL) != 0;
+ case BCM4319_CHIP_ID:
+ return (sih->chipst & CST4319_SPROM_SEL) != 0;
+ case BCM4336_CHIP_ID:
+ return (sih->chipst & CST4336_SPROM_PRESENT) != 0;
+ case BCM4330_CHIP_ID:
+ return (sih->chipst & CST4330_SPROM_PRESENT) != 0;
+ case BCM4313_CHIP_ID:
+ return (sih->chipst & CST4313_SPROM_PRESENT) != 0;
+ case BCM4331_CHIP_ID:
+ return (sih->chipst & CST4331_SPROM_PRESENT) != 0;
+ default:
+ return true;
+ }
+}
+
+bool ai_is_otp_disabled(si_t *sih)
+{
+ switch (sih->chip) {
+ case BCM4329_CHIP_ID:
+ return (sih->chipst & CST4329_SPROM_OTP_SEL_MASK) ==
+ CST4329_OTP_PWRDN;
+ case BCM4319_CHIP_ID:
+ return (sih->chipst & CST4319_SPROM_OTP_SEL_MASK) ==
+ CST4319_OTP_PWRDN;
+ case BCM4336_CHIP_ID:
+ return (sih->chipst & CST4336_OTP_PRESENT) == 0;
+ case BCM4330_CHIP_ID:
+ return (sih->chipst & CST4330_OTP_PRESENT) == 0;
+ case BCM4313_CHIP_ID:
+ return (sih->chipst & CST4313_OTP_PRESENT) == 0;
+ /* These chips always have their OTP on */
+ case BCM43224_CHIP_ID:
+ case BCM43225_CHIP_ID:
+ case BCM43421_CHIP_ID:
+ case BCM43235_CHIP_ID:
+ case BCM43236_CHIP_ID:
+ case BCM43238_CHIP_ID:
+ case BCM4331_CHIP_ID:
+ default:
+ return false;
+ }
+}
+
+bool ai_is_otp_powered(si_t *sih)
+{
+ if (PMUCTL_ENAB(sih))
+ return si_pmu_is_otp_powered(sih);
+ return true;
+}
+
+void ai_otp_power(si_t *sih, bool on)
+{
+ if (PMUCTL_ENAB(sih))
+ si_pmu_otp_power(sih, on);
+ udelay(1000);
+}
diff --git a/drivers/staging/brcm80211/brcmsmac/aiutils.h b/drivers/staging/brcm80211/brcmsmac/aiutils.h
new file mode 100644
index 0000000..b98099e
--- /dev/null
+++ b/drivers/staging/brcm80211/brcmsmac/aiutils.h
@@ -0,0 +1,546 @@
+/*
+ * Copyright (c) 2011 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _aiutils_h_
+#define _aiutils_h_
+
+/* cpp contortions to concatenate w/arg prescan */
+#ifndef PAD
+#define _PADLINE(line) pad ## line
+#define _XSTR(line) _PADLINE(line)
+#define PAD _XSTR(__LINE__)
+#endif
+
+/* Include the soci specific files */
+#include <aidmp.h>
+
+/*
+ * SOC Interconnect Address Map.
+ * All regions may not exist on all chips.
+ */
+/* Physical SDRAM */
+#define SI_SDRAM_BASE 0x00000000
+/* Host Mode sb2pcitranslation0 (64 MB) */
+#define SI_PCI_MEM 0x08000000
+#define SI_PCI_MEM_SZ (64 * 1024 * 1024)
+/* Host Mode sb2pcitranslation1 (64 MB) */
+#define SI_PCI_CFG 0x0c000000
+/* Byteswapped Physical SDRAM */
+#define SI_SDRAM_SWAPPED 0x10000000
+/* Region 2 for sdram (512 MB) */
+#define SI_SDRAM_R2 0x80000000
+
+#ifdef SI_ENUM_BASE_VARIABLE
+#define SI_ENUM_BASE (sii->pub.si_enum_base)
+#else
+#define SI_ENUM_BASE 0x18000000 /* Enumeration space base */
+#endif /* SI_ENUM_BASE_VARIABLE */
+
+/* Wrapper space base */
+#define SI_WRAP_BASE 0x18100000
+/* each core gets 4Kbytes for registers */
+#define SI_CORE_SIZE 0x1000
+/*
+ * Max cores (this is arbitrary, for software
+ * convenience and could be changed if we
+ * make any larger chips
+ */
+#define SI_MAXCORES 16
+
+/* On-chip RAM on chips that also have DDR */
+#define SI_FASTRAM 0x19000000
+#define SI_FASTRAM_SWAPPED 0x19800000
+
+/* Flash Region 2 (region 1 shadowed here) */
+#define SI_FLASH2 0x1c000000
+/* Size of Flash Region 2 */
+#define SI_FLASH2_SZ 0x02000000
+/* ARM Cortex-M3 ROM */
+#define SI_ARMCM3_ROM 0x1e000000
+/* MIPS Flash Region 1 */
+#define SI_FLASH1 0x1fc00000
+/* MIPS Size of Flash Region 1 */
+#define SI_FLASH1_SZ 0x00400000
+/* ARM7TDMI-S ROM */
+#define SI_ARM7S_ROM 0x20000000
+/* ARM Cortex-M3 SRAM Region 2 */
+#define SI_ARMCM3_SRAM2 0x60000000
+/* ARM7TDMI-S SRAM Region 2 */
+#define SI_ARM7S_SRAM2 0x80000000
+/* ARM Flash Region 1 */
+#define SI_ARM_FLASH1 0xffff0000
+/* ARM Size of Flash Region 1 */
+#define SI_ARM_FLASH1_SZ 0x00010000
+
+/* Client Mode sb2pcitranslation2 (1 GB) */
+#define SI_PCI_DMA 0x40000000
+/* Client Mode sb2pcitranslation2 (1 GB) */
+#define SI_PCI_DMA2 0x80000000
+/* Client Mode sb2pcitranslation2 size in bytes */
+#define SI_PCI_DMA_SZ 0x40000000
+/* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), low 32 bits */
+#define SI_PCIE_DMA_L32 0x00000000
+/* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), high 32 bits */
+#define SI_PCIE_DMA_H32 0x80000000
+
+/* core codes */
+#define NODEV_CORE_ID 0x700 /* Invalid coreid */
+#define CC_CORE_ID 0x800 /* chipcommon core */
+#define ILINE20_CORE_ID 0x801 /* iline20 core */
+#define SRAM_CORE_ID 0x802 /* sram core */
+#define SDRAM_CORE_ID 0x803 /* sdram core */
+#define PCI_CORE_ID 0x804 /* pci core */
+#define MIPS_CORE_ID 0x805 /* mips core */
+#define ENET_CORE_ID 0x806 /* enet mac core */
+#define CODEC_CORE_ID 0x807 /* v90 codec core */
+#define USB_CORE_ID 0x808 /* usb 1.1 host/device core */
+#define ADSL_CORE_ID 0x809 /* ADSL core */
+#define ILINE100_CORE_ID 0x80a /* iline100 core */
+#define IPSEC_CORE_ID 0x80b /* ipsec core */
+#define UTOPIA_CORE_ID 0x80c /* utopia core */
+#define PCMCIA_CORE_ID 0x80d /* pcmcia core */
+#define SOCRAM_CORE_ID 0x80e /* internal memory core */
+#define MEMC_CORE_ID 0x80f /* memc sdram core */
+#define OFDM_CORE_ID 0x810 /* OFDM phy core */
+#define EXTIF_CORE_ID 0x811 /* external interface core */
+#define D11_CORE_ID 0x812 /* 802.11 MAC core */
+#define APHY_CORE_ID 0x813 /* 802.11a phy core */
+#define BPHY_CORE_ID 0x814 /* 802.11b phy core */
+#define GPHY_CORE_ID 0x815 /* 802.11g phy core */
+#define MIPS33_CORE_ID 0x816 /* mips3302 core */
+#define USB11H_CORE_ID 0x817 /* usb 1.1 host core */
+#define USB11D_CORE_ID 0x818 /* usb 1.1 device core */
+#define USB20H_CORE_ID 0x819 /* usb 2.0 host core */
+#define USB20D_CORE_ID 0x81a /* usb 2.0 device core */
+#define SDIOH_CORE_ID 0x81b /* sdio host core */
+#define ROBO_CORE_ID 0x81c /* roboswitch core */
+#define ATA100_CORE_ID 0x81d /* parallel ATA core */
+#define SATAXOR_CORE_ID 0x81e /* serial ATA & XOR DMA core */
+#define GIGETH_CORE_ID 0x81f /* gigabit ethernet core */
+#define PCIE_CORE_ID 0x820 /* pci express core */
+#define NPHY_CORE_ID 0x821 /* 802.11n 2x2 phy core */
+#define SRAMC_CORE_ID 0x822 /* SRAM controller core */
+#define MINIMAC_CORE_ID 0x823 /* MINI MAC/phy core */
+#define ARM11_CORE_ID 0x824 /* ARM 1176 core */
+#define ARM7S_CORE_ID 0x825 /* ARM7tdmi-s core */
+#define LPPHY_CORE_ID 0x826 /* 802.11a/b/g phy core */
+#define PMU_CORE_ID 0x827 /* PMU core */
+#define SSNPHY_CORE_ID 0x828 /* 802.11n single-stream phy core */
+#define SDIOD_CORE_ID 0x829 /* SDIO device core */
+#define ARMCM3_CORE_ID 0x82a /* ARM Cortex M3 core */
+#define HTPHY_CORE_ID 0x82b /* 802.11n 4x4 phy core */
+#define MIPS74K_CORE_ID 0x82c /* mips 74k core */
+#define GMAC_CORE_ID 0x82d /* Gigabit MAC core */
+#define DMEMC_CORE_ID 0x82e /* DDR1/2 memory controller core */
+#define PCIERC_CORE_ID 0x82f /* PCIE Root Complex core */
+#define OCP_CORE_ID 0x830 /* OCP2OCP bridge core */
+#define SC_CORE_ID 0x831 /* shared common core */
+#define AHB_CORE_ID 0x832 /* OCP2AHB bridge core */
+#define SPIH_CORE_ID 0x833 /* SPI host core */
+#define I2S_CORE_ID 0x834 /* I2S core */
+#define DMEMS_CORE_ID 0x835 /* SDR/DDR1 memory controller core */
+#define DEF_SHIM_COMP 0x837 /* SHIM component in ubus/6362 */
+#define OOB_ROUTER_CORE_ID 0x367 /* OOB router core ID */
+#define DEF_AI_COMP 0xfff /* Default component, in ai chips it
+ * maps all unused address ranges
+ */
+
+/* There are TWO constants on all HND chips: SI_ENUM_BASE above,
+ * and chipcommon being the first core:
+ */
+#define SI_CC_IDX 0
+
+/* SOC Interconnect types (aka chip types) */
+#define SOCI_AI 1
+
+/* Common core control flags */
+#define SICF_BIST_EN 0x8000
+#define SICF_PME_EN 0x4000
+#define SICF_CORE_BITS 0x3ffc
+#define SICF_FGC 0x0002
+#define SICF_CLOCK_EN 0x0001
+
+/* Common core status flags */
+#define SISF_BIST_DONE 0x8000
+#define SISF_BIST_ERROR 0x4000
+#define SISF_GATED_CLK 0x2000
+#define SISF_DMA64 0x1000
+#define SISF_CORE_BITS 0x0fff
+
+/* A register that is common to all cores to
+ * communicate w/PMU regarding clock control.
+ */
+#define SI_CLK_CTL_ST 0x1e0 /* clock control and status */
+
+/* clk_ctl_st register */
+#define CCS_FORCEALP 0x00000001 /* force ALP request */
+#define CCS_FORCEHT 0x00000002 /* force HT request */
+#define CCS_FORCEILP 0x00000004 /* force ILP request */
+#define CCS_ALPAREQ 0x00000008 /* ALP Avail Request */
+#define CCS_HTAREQ 0x00000010 /* HT Avail Request */
+#define CCS_FORCEHWREQOFF 0x00000020 /* Force HW Clock Request Off */
+#define CCS_ERSRC_REQ_MASK 0x00000700 /* external resource requests */
+#define CCS_ERSRC_REQ_SHIFT 8
+#define CCS_ALPAVAIL 0x00010000 /* ALP is available */
+#define CCS_HTAVAIL 0x00020000 /* HT is available */
+#define CCS_BP_ON_APL 0x00040000 /* RO: running on ALP clock */
+#define CCS_BP_ON_HT 0x00080000 /* RO: running on HT clock */
+#define CCS_ERSRC_STS_MASK 0x07000000 /* external resource status */
+#define CCS_ERSRC_STS_SHIFT 24
+
+/* HT avail in chipc and pcmcia on 4328a0 */
+#define CCS0_HTAVAIL 0x00010000
+/* ALP avail in chipc and pcmcia on 4328a0 */
+#define CCS0_ALPAVAIL 0x00020000
+
+/* Not really related to SOC Interconnect, but a couple of software
+ * conventions for the use the flash space:
+ */
+
+/* Minumum amount of flash we support */
+#define FLASH_MIN 0x00020000 /* Minimum flash size */
+
+/* A boot/binary may have an embedded block that describes its size */
+#define BISZ_OFFSET 0x3e0 /* At this offset into the binary */
+#define BISZ_MAGIC 0x4249535a /* Marked with value: 'BISZ' */
+#define BISZ_MAGIC_IDX 0 /* Word 0: magic */
+#define BISZ_TXTST_IDX 1 /* 1: text start */
+#define BISZ_TXTEND_IDX 2 /* 2: text end */
+#define BISZ_DATAST_IDX 3 /* 3: data start */
+#define BISZ_DATAEND_IDX 4 /* 4: data end */
+#define BISZ_BSSST_IDX 5 /* 5: bss start */
+#define BISZ_BSSEND_IDX 6 /* 6: bss end */
+#define BISZ_SIZE 7 /* descriptor size in 32-bit integers */
+
+#define SI_INFO(sih) (si_info_t *)sih
+
+#define GOODCOREADDR(x, b) \
+ (((x) >= (b)) && ((x) < ((b) + SI_MAXCORES * SI_CORE_SIZE)) && \
+ IS_ALIGNED((x), SI_CORE_SIZE))
+#define GOODREGS(regs) \
+ ((regs) != NULL && IS_ALIGNED((unsigned long)(regs), SI_CORE_SIZE))
+#define BADCOREADDR 0
+#define GOODIDX(idx) (((uint)idx) < SI_MAXCORES)
+#define NOREV -1 /* Invalid rev */
+
+/* Newer chips can access PCI/PCIE and CC core without requiring to change
+ * PCI BAR0 WIN
+ */
+#define SI_FAST(si) (((si)->pub.buscoretype == PCIE_CORE_ID) || \
+ (((si)->pub.buscoretype == PCI_CORE_ID) && \
+ (si)->pub.buscorerev >= 13))
+
+#define PCIEREGS(si) (((char *)((si)->curmap) + PCI_16KB0_PCIREGS_OFFSET))
+#define CCREGS_FAST(si) (((char *)((si)->curmap) + PCI_16KB0_CCREGS_OFFSET))
+
+/*
+ * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts
+ * before after core switching to avoid invalid register accesss inside ISR.
+ */
+#define INTR_OFF(si, intr_val) \
+ if ((si)->intrsoff_fn && \
+ (si)->coreid[(si)->curidx] == (si)->dev_coreid) \
+ intr_val = (*(si)->intrsoff_fn)((si)->intr_arg)
+#define INTR_RESTORE(si, intr_val) \
+ if ((si)->intrsrestore_fn && \
+ (si)->coreid[(si)->curidx] == (si)->dev_coreid) \
+ (*(si)->intrsrestore_fn)((si)->intr_arg, intr_val)
+
+/* dynamic clock control defines */
+#define LPOMINFREQ 25000 /* low power oscillator min */
+#define LPOMAXFREQ 43000 /* low power oscillator max */
+#define XTALMINFREQ 19800000 /* 20 MHz - 1% */
+#define XTALMAXFREQ 20200000 /* 20 MHz + 1% */
+#define PCIMINFREQ 25000000 /* 25 MHz */
+#define PCIMAXFREQ 34000000 /* 33 MHz + fudge */
+
+#define ILP_DIV_5MHZ 0 /* ILP = 5 MHz */
+#define ILP_DIV_1MHZ 4 /* ILP = 1 MHz */
+
+#define PCI(si) (((si)->pub.bustype == PCI_BUS) && \
+ ((si)->pub.buscoretype == PCI_CORE_ID))
+#define PCIE(si) (((si)->pub.bustype == PCI_BUS) && \
+ ((si)->pub.buscoretype == PCIE_CORE_ID))
+#define PCI_FORCEHT(si) \
+ (PCIE(si) && (si->pub.chip == BCM4716_CHIP_ID))
+
+/* GPIO Based LED powersave defines */
+#define DEFAULT_GPIO_ONTIME 10 /* Default: 10% on */
+#define DEFAULT_GPIO_OFFTIME 90 /* Default: 10% on */
+
+#ifndef DEFAULT_GPIOTIMERVAL
+#define DEFAULT_GPIOTIMERVAL \
+ ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME)
+#endif
+
+/*
+ * Data structure to export all chip specific common variables
+ * public (read-only) portion of aiutils handle returned by si_attach()
+ */
+struct si_pub {
+ uint bustype; /* SI_BUS, PCI_BUS */
+ uint buscoretype; /* PCI_CORE_ID, PCIE_CORE_ID, PCMCIA_CORE_ID */
+ uint buscorerev; /* buscore rev */
+ uint buscoreidx; /* buscore index */
+ int ccrev; /* chip common core rev */
+ u32 cccaps; /* chip common capabilities */
+ u32 cccaps_ext; /* chip common capabilities extension */
+ int pmurev; /* pmu core rev */
+ u32 pmucaps; /* pmu capabilities */
+ uint boardtype; /* board type */
+ uint boardvendor; /* board vendor */
+ uint boardflags; /* board flags */
+ uint boardflags2; /* board flags2 */
+ uint chip; /* chip number */
+ uint chiprev; /* chip revision */
+ uint chippkg; /* chip package option */
+ u32 chipst; /* chip status */
+ bool issim; /* chip is in simulation or emulation */
+ uint socirev; /* SOC interconnect rev */
+ bool pci_pr32414;
+
+};
+
+/*
+ * for HIGH_ONLY driver, the si_t must be writable to allow states sync from
+ * BMAC to HIGH driver for monolithic driver, it is readonly to prevent accident
+ * change
+ */
+typedef const struct si_pub si_t;
+
+/*
+ * Many of the routines below take an 'sih' handle as their first arg.
+ * Allocate this by calling si_attach(). Free it by calling si_detach().
+ * At any one time, the sih is logically focused on one particular si core
+ * (the "current core").
+ * Use si_setcore() or si_setcoreidx() to change the association to another core
+ */
+
+#define BADIDX (SI_MAXCORES + 1)
+
+/* clkctl xtal what flags */
+#define XTAL 0x1 /* primary crystal oscillator (2050) */
+#define PLL 0x2 /* main chip pll */
+
+/* clkctl clk mode */
+#define CLK_FAST 0 /* force fast (pll) clock */
+#define CLK_DYNAMIC 2 /* enable dynamic clock control */
+
+/* GPIO usage priorities */
+#define GPIO_DRV_PRIORITY 0 /* Driver */
+#define GPIO_APP_PRIORITY 1 /* Application */
+#define GPIO_HI_PRIORITY 2 /* Highest priority. Ignore GPIO
+ * reservation
+ */
+
+/* GPIO pull up/down */
+#define GPIO_PULLUP 0
+#define GPIO_PULLDN 1
+
+/* GPIO event regtype */
+#define GPIO_REGEVT 0 /* GPIO register event */
+#define GPIO_REGEVT_INTMSK 1 /* GPIO register event int mask */
+#define GPIO_REGEVT_INTPOL 2 /* GPIO register event int polarity */
+
+/* device path */
+#define SI_DEVPATH_BUFSZ 16 /* min buffer size in bytes */
+
+/* SI routine enumeration: to be used by update function with multiple hooks */
+#define SI_DOATTACH 1
+#define SI_PCIDOWN 2
+#define SI_PCIUP 3
+
+#define ISSIM_ENAB(sih) 0
+
+/* PMU clock/power control */
+#if defined(BCMPMUCTL)
+#define PMUCTL_ENAB(sih) (BCMPMUCTL)
+#else
+#define PMUCTL_ENAB(sih) ((sih)->cccaps & CC_CAP_PMU)
+#endif
+
+/* chipcommon clock/power control (exclusive with PMU's) */
+#if defined(BCMPMUCTL) && BCMPMUCTL
+#define CCCTL_ENAB(sih) (0)
+#define CCPLL_ENAB(sih) (0)
+#else
+#define CCCTL_ENAB(sih) ((sih)->cccaps & CC_CAP_PWR_CTL)
+#define CCPLL_ENAB(sih) ((sih)->cccaps & CC_CAP_PLL_MASK)
+#endif
+
+typedef void (*gpio_handler_t) (u32 stat, void *arg);
+
+/* External PA enable mask */
+#define GPIO_CTRL_EPA_EN_MASK 0x40
+
+#define SI_ERROR(args)
+
+#ifdef BCMDBG
+#define SI_MSG(args) printk args
+#else
+#define SI_MSG(args)
+#endif /* BCMDBG */
+
+/* Define SI_VMSG to printf for verbose debugging, but don't check it in */
+#define SI_VMSG(args)
+
+#define IS_SIM(chippkg) \
+ ((chippkg == HDLSIM_PKG_ID) || (chippkg == HWSIM_PKG_ID))
+
+typedef u32(*si_intrsoff_t) (void *intr_arg);
+typedef void (*si_intrsrestore_t) (void *intr_arg, u32 arg);
+typedef bool(*si_intrsenabled_t) (void *intr_arg);
+
+typedef struct gpioh_item {
+ void *arg;
+ bool level;
+ gpio_handler_t handler;
+ u32 event;
+ struct gpioh_item *next;
+} gpioh_item_t;
+
+/* misc si info needed by some of the routines */
+typedef struct si_info {
+ struct si_pub pub; /* back plane public state (must be first) */
+ void *pbus; /* handle to bus (pci/sdio/..) */
+ uint dev_coreid; /* the core provides driver functions */
+ void *intr_arg; /* interrupt callback function arg */
+ si_intrsoff_t intrsoff_fn; /* turns chip interrupts off */
+ si_intrsrestore_t intrsrestore_fn; /* restore chip interrupts */
+ si_intrsenabled_t intrsenabled_fn; /* check if interrupts are enabled */
+
+ void *pch; /* PCI/E core handle */
+
+ gpioh_item_t *gpioh_head; /* GPIO event handlers list */
+
+ bool memseg; /* flag to toggle MEM_SEG register */
+
+ char *vars;
+ uint varsz;
+
+ void *curmap; /* current regs va */
+ void *regs[SI_MAXCORES]; /* other regs va */
+
+ uint curidx; /* current core index */
+ uint numcores; /* # discovered cores */
+ uint coreid[SI_MAXCORES]; /* id of each core */
+ u32 coresba[SI_MAXCORES]; /* backplane address of each core */
+ void *regs2[SI_MAXCORES]; /* 2nd virtual address per core (usbh20) */
+ u32 coresba2[SI_MAXCORES]; /* 2nd phys address per core (usbh20) */
+ u32 coresba_size[SI_MAXCORES]; /* backplane address space size */
+ u32 coresba2_size[SI_MAXCORES]; /* second address space size */
+
+ void *curwrap; /* current wrapper va */
+ void *wrappers[SI_MAXCORES]; /* other cores wrapper va */
+ u32 wrapba[SI_MAXCORES]; /* address of controlling wrapper */
+
+ u32 cia[SI_MAXCORES]; /* erom cia entry for each core */
+ u32 cib[SI_MAXCORES]; /* erom cia entry for each core */
+ u32 oob_router; /* oob router registers for axi */
+} si_info_t;
+
+/* AMBA Interconnect exported externs */
+extern void ai_scan(si_t *sih, void *regs, uint devid);
+
+extern uint ai_flag(si_t *sih);
+extern void ai_setint(si_t *sih, int siflag);
+extern uint ai_coreidx(si_t *sih);
+extern uint ai_corevendor(si_t *sih);
+extern uint ai_corerev(si_t *sih);
+extern bool ai_iscoreup(si_t *sih);
+extern void *ai_setcoreidx(si_t *sih, uint coreidx);
+extern u32 ai_core_cflags(si_t *sih, u32 mask, u32 val);
+extern void ai_core_cflags_wo(si_t *sih, u32 mask, u32 val);
+extern u32 ai_core_sflags(si_t *sih, u32 mask, u32 val);
+extern uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask,
+ uint val);
+extern void ai_core_reset(si_t *sih, u32 bits, u32 resetbits);
+extern void ai_core_disable(si_t *sih, u32 bits);
+extern int ai_numaddrspaces(si_t *sih);
+extern u32 ai_addrspace(si_t *sih, uint asidx);
+extern u32 ai_addrspacesize(si_t *sih, uint asidx);
+extern void ai_write_wrap_reg(si_t *sih, u32 offset, u32 val);
+
+/* === exported functions === */
+extern si_t *ai_attach(uint pcidev, void *regs, uint bustype,
+ void *sdh, char **vars, uint *varsz);
+
+extern void ai_detach(si_t *sih);
+extern bool ai_pci_war16165(si_t *sih);
+
+extern uint ai_coreid(si_t *sih);
+extern uint ai_corerev(si_t *sih);
+extern uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask,
+ uint val);
+extern void ai_write_wrapperreg(si_t *sih, u32 offset, u32 val);
+extern u32 ai_core_cflags(si_t *sih, u32 mask, u32 val);
+extern u32 ai_core_sflags(si_t *sih, u32 mask, u32 val);
+extern bool ai_iscoreup(si_t *sih);
+extern uint ai_findcoreidx(si_t *sih, uint coreid, uint coreunit);
+extern void *ai_setcoreidx(si_t *sih, uint coreidx);
+extern void *ai_setcore(si_t *sih, uint coreid, uint coreunit);
+extern void *ai_switch_core(si_t *sih, uint coreid, uint *origidx,
+ uint *intr_val);
+extern void ai_restore_core(si_t *sih, uint coreid, uint intr_val);
+extern void ai_core_reset(si_t *sih, u32 bits, u32 resetbits);
+extern void ai_core_disable(si_t *sih, u32 bits);
+extern u32 ai_alp_clock(si_t *sih);
+extern u32 ai_ilp_clock(si_t *sih);
+extern void ai_pci_setup(si_t *sih, uint coremask);
+extern void ai_setint(si_t *sih, int siflag);
+extern bool ai_backplane64(si_t *sih);
+extern void ai_register_intr_callback(si_t *sih, void *intrsoff_fn,
+ void *intrsrestore_fn,
+ void *intrsenabled_fn, void *intr_arg);
+extern void ai_deregister_intr_callback(si_t *sih);
+extern void ai_clkctl_init(si_t *sih);
+extern u16 ai_clkctl_fast_pwrup_delay(si_t *sih);
+extern bool ai_clkctl_cc(si_t *sih, uint mode);
+extern int ai_clkctl_xtal(si_t *sih, uint what, bool on);
+extern bool ai_deviceremoved(si_t *sih);
+extern u32 ai_gpiocontrol(si_t *sih, u32 mask, u32 val,
+ u8 priority);
+
+/* OTP status */
+extern bool ai_is_otp_disabled(si_t *sih);
+extern bool ai_is_otp_powered(si_t *sih);
+extern void ai_otp_power(si_t *sih, bool on);
+
+/* SPROM availability */
+extern bool ai_is_sprom_available(si_t *sih);
+
+/*
+ * Build device path. Path size must be >= SI_DEVPATH_BUFSZ.
+ * The returned path is NULL terminated and has trailing '/'.
+ * Return 0 on success, nonzero otherwise.
+ */
+extern int ai_devpath(si_t *sih, char *path, int size);
+/* Read variable with prepending the devpath to the name */
+extern char *ai_getdevpathvar(si_t *sih, const char *name);
+extern int ai_getdevpathintvar(si_t *sih, const char *name);
+
+extern void ai_pci_sleep(si_t *sih);
+extern void ai_pci_down(si_t *sih);
+extern void ai_pci_up(si_t *sih);
+extern int ai_pci_fixcfg(si_t *sih);
+
+extern void ai_chipcontrl_epa4331(si_t *sih, bool on);
+/* Enable Ex-PA for 4313 */
+extern void ai_epa_4313war(si_t *sih);
+
+char *ai_getnvramflvar(si_t *sih, const char *name);
+
+#endif /* _aiutils_h_ */
diff --git a/drivers/staging/brcm80211/brcmsmac/bcmotp.c b/drivers/staging/brcm80211/brcmsmac/bcmotp.c
new file mode 100644
index 0000000..d09628b
--- /dev/null
+++ b/drivers/staging/brcm80211/brcmsmac/bcmotp.c
@@ -0,0 +1,936 @@
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/delay.h>
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <linux/crc-ccitt.h>
+
+#include <bcmdefs.h>
+#include <bcmdevs.h>
+#include <bcmutils.h>
+#include <aiutils.h>
+#include <hndsoc.h>
+#include <sbchipc.h>
+#include <bcmotp.h>
+
+/*
+ * There are two different OTP controllers so far:
+ * 1. new IPX OTP controller: chipc 21, >=23
+ * 2. older HND OTP controller: chipc 12, 17, 22
+ *
+ * Define BCMHNDOTP to include support for the HND OTP controller.
+ * Define BCMIPXOTP to include support for the IPX OTP controller.
+ *
+ * NOTE 1: More than one may be defined
+ * NOTE 2: If none are defined, the default is to include them all.
+ */
+
+#if !defined(BCMHNDOTP) && !defined(BCMIPXOTP)
+#define BCMHNDOTP 1
+#define BCMIPXOTP 1
+#endif
+
+#define OTPTYPE_HND(ccrev) ((ccrev) < 21 || (ccrev) == 22)
+#define OTPTYPE_IPX(ccrev) ((ccrev) == 21 || (ccrev) >= 23)
+
+#define OTPP_TRIES 10000000 /* # of tries for OTPP */
+
+#ifdef BCMIPXOTP
+#define MAXNUMRDES 9 /* Maximum OTP redundancy entries */
+#endif
+
+/* OTP common function type */
+typedef int (*otp_status_t) (void *oh);
+typedef int (*otp_size_t) (void *oh);
+typedef void *(*otp_init_t) (si_t *sih);
+typedef u16(*otp_read_bit_t) (void *oh, chipcregs_t *cc, uint off);
+typedef int (*otp_read_region_t) (si_t *sih, int region, u16 *data,
+ uint *wlen);
+typedef int (*otp_nvread_t) (void *oh, char *data, uint *len);
+
+/* OTP function struct */
+typedef struct otp_fn_s {
+ otp_size_t size;
+ otp_read_bit_t read_bit;
+ otp_init_t init;
+ otp_read_region_t read_region;
+ otp_nvread_t nvread;
+ otp_status_t status;
+} otp_fn_t;
+
+typedef struct {
+ uint ccrev; /* chipc revision */
+ otp_fn_t *fn; /* OTP functions */
+ si_t *sih; /* Saved sb handle */
+
+#ifdef BCMIPXOTP
+ /* IPX OTP section */
+ u16 wsize; /* Size of otp in words */
+ u16 rows; /* Geometry */
+ u16 cols; /* Geometry */
+ u32 status; /* Flag bits (lock/prog/rv).
+ * (Reflected only when OTP is power cycled)
+ */
+ u16 hwbase; /* hardware subregion offset */
+ u16 hwlim; /* hardware subregion boundary */
+ u16 swbase; /* software subregion offset */
+ u16 swlim; /* software subregion boundary */
+ u16 fbase; /* fuse subregion offset */
+ u16 flim; /* fuse subregion boundary */
+ int otpgu_base; /* offset to General Use Region */
+#endif /* BCMIPXOTP */
+
+#ifdef BCMHNDOTP
+ /* HND OTP section */
+ uint size; /* Size of otp in bytes */
+ uint hwprot; /* Hardware protection bits */
+ uint signvalid; /* Signature valid bits */
+ int boundary; /* hw/sw boundary */
+#endif /* BCMHNDOTP */
+} otpinfo_t;
+
+static otpinfo_t otpinfo;
+
+/*
+ * IPX OTP Code
+ *
+ * Exported functions:
+ * ipxotp_status()
+ * ipxotp_size()
+ * ipxotp_init()
+ * ipxotp_read_bit()
+ * ipxotp_read_region()
+ * ipxotp_nvread()
+ *
+ */
+
+#ifdef BCMIPXOTP
+
+#define HWSW_RGN(rgn) (((rgn) == OTP_HW_RGN) ? "h/w" : "s/w")
+
+/* OTP layout */
+/* CC revs 21, 24 and 27 OTP General Use Region word offset */
+#define REVA4_OTPGU_BASE 12
+
+/* CC revs 23, 25, 26, 28 and above OTP General Use Region word offset */
+#define REVB8_OTPGU_BASE 20
+
+/* CC rev 36 OTP General Use Region word offset */
+#define REV36_OTPGU_BASE 12
+
+/* Subregion word offsets in General Use region */
+#define OTPGU_HSB_OFF 0
+#define OTPGU_SFB_OFF 1
+#define OTPGU_CI_OFF 2
+#define OTPGU_P_OFF 3
+#define OTPGU_SROM_OFF 4
+
+/* Flag bit offsets in General Use region */
+#define OTPGU_HWP_OFF 60
+#define OTPGU_SWP_OFF 61
+#define OTPGU_CIP_OFF 62
+#define OTPGU_FUSEP_OFF 63
+#define OTPGU_CIP_MSK 0x4000
+#define OTPGU_P_MSK 0xf000
+#define OTPGU_P_SHIFT (OTPGU_HWP_OFF % 16)
+
+/* OTP Size */
+#define OTP_SZ_FU_324 ((roundup(324, 8))/8) /* 324 bits */
+#define OTP_SZ_FU_288 (288/8) /* 288 bits */
+#define OTP_SZ_FU_216 (216/8) /* 216 bits */
+#define OTP_SZ_FU_72 (72/8) /* 72 bits */
+#define OTP_SZ_CHECKSUM (16/8) /* 16 bits */
+#define OTP4315_SWREG_SZ 178 /* 178 bytes */
+#define OTP_SZ_FU_144 (144/8) /* 144 bits */
+
+static int ipxotp_status(void *oh)
+{
+ otpinfo_t *oi = (otpinfo_t *) oh;
+ return (int)(oi->status);
+}
+
+/* Return size in bytes */
+static int ipxotp_size(void *oh)
+{
+ otpinfo_t *oi = (otpinfo_t *) oh;
+ return (int)oi->wsize * 2;
+}
+
+static u16 ipxotp_otpr(void *oh, chipcregs_t *cc, uint wn)
+{
+ otpinfo_t *oi;
+
+ oi = (otpinfo_t *) oh;
+
+ return R_REG(&cc->sromotp[wn]);
+}
+
+static u16 ipxotp_read_bit(void *oh, chipcregs_t *cc, uint off)
+{
+ otpinfo_t *oi = (otpinfo_t *) oh;
+ uint k, row, col;
+ u32 otpp, st;
+
+ row = off / oi->cols;
+ col = off % oi->cols;
+
+ otpp = OTPP_START_BUSY |
+ ((OTPPOC_READ << OTPP_OC_SHIFT) & OTPP_OC_MASK) |
+ ((row << OTPP_ROW_SHIFT) & OTPP_ROW_MASK) |
+ ((col << OTPP_COL_SHIFT) & OTPP_COL_MASK);
+ W_REG(&cc->otpprog, otpp);
+
+ for (k = 0;
+ ((st = R_REG(&cc->otpprog)) & OTPP_START_BUSY)
+ && (k < OTPP_TRIES); k++)
+ ;
+ if (k >= OTPP_TRIES) {
+ return 0xffff;
+ }
+ if (st & OTPP_READERR) {
+ return 0xffff;
+ }
+ st = (st & OTPP_VALUE_MASK) >> OTPP_VALUE_SHIFT;
+
+ return (int)st;
+}
+
+/* Calculate max HW/SW region byte size by subtracting fuse region and checksum size,
+ * osizew is oi->wsize (OTP size - GU size) in words
+ */
+static int ipxotp_max_rgnsz(si_t *sih, int osizew)
+{
+ int ret = 0;
+
+ switch (sih->chip) {
+ case BCM43224_CHIP_ID:
+ case BCM43225_CHIP_ID:
+ ret = osizew * 2 - OTP_SZ_FU_72 - OTP_SZ_CHECKSUM;
+ break;
+ case BCM4313_CHIP_ID:
+ ret = osizew * 2 - OTP_SZ_FU_72 - OTP_SZ_CHECKSUM;
+ break;
+ default:
+ break; /* Don't know about this chip */
+ }
+
+ return ret;
+}
+
+static void _ipxotp_init(otpinfo_t *oi, chipcregs_t *cc)
+{
+ uint k;
+ u32 otpp, st;
+
+ /* record word offset of General Use Region for various chipcommon revs */
+ if (oi->sih->ccrev == 21 || oi->sih->ccrev == 24
+ || oi->sih->ccrev == 27) {
+ oi->otpgu_base = REVA4_OTPGU_BASE;
+ } else if (oi->sih->ccrev == 36) {
+ /* OTP size greater than equal to 2KB (128 words), otpgu_base is similar to rev23 */
+ if (oi->wsize >= 128)
+ oi->otpgu_base = REVB8_OTPGU_BASE;
+ else
+ oi->otpgu_base = REV36_OTPGU_BASE;
+ } else if (oi->sih->ccrev == 23 || oi->sih->ccrev >= 25) {
+ oi->otpgu_base = REVB8_OTPGU_BASE;
+ }
+
+ /* First issue an init command so the status is up to date */
+ otpp =
+ OTPP_START_BUSY | ((OTPPOC_INIT << OTPP_OC_SHIFT) & OTPP_OC_MASK);
+
+ W_REG(&cc->otpprog, otpp);
+ for (k = 0;
+ ((st = R_REG(&cc->otpprog)) & OTPP_START_BUSY)
+ && (k < OTPP_TRIES); k++)
+ ;
+ if (k >= OTPP_TRIES) {
+ return;
+ }
+
+ /* Read OTP lock bits and subregion programmed indication bits */
+ oi->status = R_REG(&cc->otpstatus);
+
+ if ((oi->sih->chip == BCM43224_CHIP_ID)
+ || (oi->sih->chip == BCM43225_CHIP_ID)) {
+ u32 p_bits;
+ p_bits =
+ (ipxotp_otpr(oi, cc, oi->otpgu_base + OTPGU_P_OFF) &
+ OTPGU_P_MSK)
+ >> OTPGU_P_SHIFT;
+ oi->status |= (p_bits << OTPS_GUP_SHIFT);
+ }
+
+ /*
+ * h/w region base and fuse region limit are fixed to the top and
+ * the bottom of the general use region. Everything else can be flexible.
+ */
+ oi->hwbase = oi->otpgu_base + OTPGU_SROM_OFF;
+ oi->hwlim = oi->wsize;
+ if (oi->status & OTPS_GUP_HW) {
+ oi->hwlim =
+ ipxotp_otpr(oi, cc, oi->otpgu_base + OTPGU_HSB_OFF) / 16;
+ oi->swbase = oi->hwlim;
+ } else
+ oi->swbase = oi->hwbase;
+
+ /* subtract fuse and checksum from beginning */
+ oi->swlim = ipxotp_max_rgnsz(oi->sih, oi->wsize) / 2;
+
+ if (oi->status & OTPS_GUP_SW) {
+ oi->swlim =
+ ipxotp_otpr(oi, cc, oi->otpgu_base + OTPGU_SFB_OFF) / 16;
+ oi->fbase = oi->swlim;
+ } else
+ oi->fbase = oi->swbase;
+
+ oi->flim = oi->wsize;
+}
+
+static void *ipxotp_init(si_t *sih)
+{
+ uint idx;
+ chipcregs_t *cc;
+ otpinfo_t *oi;
+
+ /* Make sure we're running IPX OTP */
+ if (!OTPTYPE_IPX(sih->ccrev))
+ return NULL;
+
+ /* Make sure OTP is not disabled */
+ if (ai_is_otp_disabled(sih))
+ return NULL;
+
+ /* Make sure OTP is powered up */
+ if (!ai_is_otp_powered(sih))
+ return NULL;
+
+ oi = &otpinfo;
+
+ /* Check for otp size */
+ switch ((sih->cccaps & CC_CAP_OTPSIZE) >> CC_CAP_OTPSIZE_SHIFT) {
+ case 0:
+ /* Nothing there */
+ return NULL;
+ case 1: /* 32x64 */
+ oi->rows = 32;
+ oi->cols = 64;
+ oi->wsize = 128;
+ break;
+ case 2: /* 64x64 */
+ oi->rows = 64;
+ oi->cols = 64;
+ oi->wsize = 256;
+ break;
+ case 5: /* 96x64 */
+ oi->rows = 96;
+ oi->cols = 64;
+ oi->wsize = 384;
+ break;
+ case 7: /* 16x64 *//* 1024 bits */
+ oi->rows = 16;
+ oi->cols = 64;
+ oi->wsize = 64;
+ break;
+ default:
+ /* Don't know the geometry */
+ return NULL;
+ }
+
+ /* Retrieve OTP region info */
+ idx = ai_coreidx(sih);
+ cc = ai_setcoreidx(sih, SI_CC_IDX);
+
+ _ipxotp_init(oi, cc);
+
+ ai_setcoreidx(sih, idx);
+
+ return (void *)oi;
+}
+
+static int ipxotp_read_region(void *oh, int region, u16 *data, uint *wlen)
+{
+ otpinfo_t *oi = (otpinfo_t *) oh;
+ uint idx;
+ chipcregs_t *cc;
+ uint base, i, sz;
+
+ /* Validate region selection */
+ switch (region) {
+ case OTP_HW_RGN:
+ sz = (uint) oi->hwlim - oi->hwbase;
+ if (!(oi->status & OTPS_GUP_HW)) {
+ *wlen = sz;
+ return -ENODATA;
+ }
+ if (*wlen < sz) {
+ *wlen = sz;
+ return -EOVERFLOW;
+ }
+ base = oi->hwbase;
+ break;
+ case OTP_SW_RGN:
+ sz = ((uint) oi->swlim - oi->swbase);
+ if (!(oi->status & OTPS_GUP_SW)) {
+ *wlen = sz;
+ return -ENODATA;
+ }
+ if (*wlen < sz) {
+ *wlen = sz;
+ return -EOVERFLOW;
+ }
+ base = oi->swbase;
+ break;
+ case OTP_CI_RGN:
+ sz = OTPGU_CI_SZ;
+ if (!(oi->status & OTPS_GUP_CI)) {
+ *wlen = sz;
+ return -ENODATA;
+ }
+ if (*wlen < sz) {
+ *wlen = sz;
+ return -EOVERFLOW;
+ }
+ base = oi->otpgu_base + OTPGU_CI_OFF;
+ break;
+ case OTP_FUSE_RGN:
+ sz = (uint) oi->flim - oi->fbase;
+ if (!(oi->status & OTPS_GUP_FUSE)) {
+ *wlen = sz;
+ return -ENODATA;
+ }
+ if (*wlen < sz) {
+ *wlen = sz;
+ return -EOVERFLOW;
+ }
+ base = oi->fbase;
+ break;
+ case OTP_ALL_RGN:
+ sz = ((uint) oi->flim - oi->hwbase);
+ if (!(oi->status & (OTPS_GUP_HW | OTPS_GUP_SW))) {
+ *wlen = sz;
+ return -ENODATA;
+ }
+ if (*wlen < sz) {
+ *wlen = sz;
+ return -EOVERFLOW;
+ }
+ base = oi->hwbase;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ idx = ai_coreidx(oi->sih);
+ cc = ai_setcoreidx(oi->sih, SI_CC_IDX);
+
+ /* Read the data */
+ for (i = 0; i < sz; i++)
+ data[i] = ipxotp_otpr(oh, cc, base + i);
+
+ ai_setcoreidx(oi->sih, idx);
+ *wlen = sz;
+ return 0;
+}
+
+static int ipxotp_nvread(void *oh, char *data, uint *len)
+{
+ return -ENOTSUPP;
+}
+
+static otp_fn_t ipxotp_fn = {
+ (otp_size_t) ipxotp_size,
+ (otp_read_bit_t) ipxotp_read_bit,
+
+ (otp_init_t) ipxotp_init,
+ (otp_read_region_t) ipxotp_read_region,
+ (otp_nvread_t) ipxotp_nvread,
+
+ (otp_status_t) ipxotp_status
+};
+
+#endif /* BCMIPXOTP */
+
+/*
+ * HND OTP Code
+ *
+ * Exported functions:
+ * hndotp_status()
+ * hndotp_size()
+ * hndotp_init()
+ * hndotp_read_bit()
+ * hndotp_read_region()
+ * hndotp_nvread()
+ *
+ */
+
+#ifdef BCMHNDOTP
+
+/* Fields in otpstatus */
+#define OTPS_PROGFAIL 0x80000000
+#define OTPS_PROTECT 0x00000007
+#define OTPS_HW_PROTECT 0x00000001
+#define OTPS_SW_PROTECT 0x00000002
+#define OTPS_CID_PROTECT 0x00000004
+#define OTPS_RCEV_MSK 0x00003f00
+#define OTPS_RCEV_SHIFT 8
+
+/* Fields in the otpcontrol register */
+#define OTPC_RECWAIT 0xff000000
+#define OTPC_PROGWAIT 0x00ffff00
+#define OTPC_PRW_SHIFT 8
+#define OTPC_MAXFAIL 0x00000038
+#define OTPC_VSEL 0x00000006
+#define OTPC_SELVL 0x00000001
+
+/* OTP regions (Word offsets from otp size) */
+#define OTP_SWLIM_OFF (-4)
+#define OTP_CIDBASE_OFF 0
+#define OTP_CIDLIM_OFF 4
+
+/* Predefined OTP words (Word offset from otp size) */
+#define OTP_BOUNDARY_OFF (-4)
+#define OTP_HWSIGN_OFF (-3)
+#define OTP_SWSIGN_OFF (-2)
+#define OTP_CIDSIGN_OFF (-1)
+#define OTP_CID_OFF 0
+#define OTP_PKG_OFF 1
+#define OTP_FID_OFF 2
+#define OTP_RSV_OFF 3
+#define OTP_LIM_OFF 4
+#define OTP_RD_OFF 4 /* Redundancy row starts here */
+#define OTP_RC0_OFF 28 /* Redundancy control word 1 */
+#define OTP_RC1_OFF 32 /* Redundancy control word 2 */
+#define OTP_RC_LIM_OFF 36 /* Redundancy control word end */
+
+#define OTP_HW_REGION OTPS_HW_PROTECT
+#define OTP_SW_REGION OTPS_SW_PROTECT
+#define OTP_CID_REGION OTPS_CID_PROTECT
+
+#if OTP_HW_REGION != OTP_HW_RGN
+#error "incompatible OTP_HW_RGN"
+#endif
+#if OTP_SW_REGION != OTP_SW_RGN
+#error "incompatible OTP_SW_RGN"
+#endif
+#if OTP_CID_REGION != OTP_CI_RGN
+#error "incompatible OTP_CI_RGN"
+#endif
+
+/* Redundancy entry definitions */
+#define OTP_RCE_ROW_SZ 6
+#define OTP_RCE_SIGN_MASK 0x7fff
+#define OTP_RCE_ROW_MASK 0x3f
+#define OTP_RCE_BITS 21
+#define OTP_RCE_SIGN_SZ 15
+#define OTP_RCE_BIT0 1
+
+#define OTP_WPR 4
+#define OTP_SIGNATURE 0x578a
+#define OTP_MAGIC 0x4e56
+
+static int hndotp_status(void *oh)
+{
+ otpinfo_t *oi = (otpinfo_t *) oh;
+ return (int)(oi->hwprot | oi->signvalid);
+}
+
+static int hndotp_size(void *oh)
+{
+ otpinfo_t *oi = (otpinfo_t *) oh;
+ return (int)(oi->size);
+}
+
+static u16 hndotp_otpr(void *oh, chipcregs_t *cc, uint wn)
+{
+ volatile u16 *ptr;
+
+ ptr = (volatile u16 *)((volatile char *)cc + CC_SROM_OTP);
+ return R_REG(&ptr[wn]);
+}
+
+static u16 hndotp_otproff(void *oh, chipcregs_t *cc, int woff)
+{
+ otpinfo_t *oi = (otpinfo_t *) oh;
+ volatile u16 *ptr;
+
+ ptr = (volatile u16 *)((volatile char *)cc + CC_SROM_OTP);
+
+ return R_REG(&ptr[(oi->size / 2) + woff]);
+}
+
+static u16 hndotp_read_bit(void *oh, chipcregs_t *cc, uint idx)
+{
+ uint k, row, col;
+ u32 otpp, st;
+
+ row = idx / 65;
+ col = idx % 65;
+
+ otpp = OTPP_START_BUSY | OTPP_READ |
+ ((row << OTPP_ROW_SHIFT) & OTPP_ROW_MASK) | (col & OTPP_COL_MASK);
+
+ W_REG(&cc->otpprog, otpp);
+ st = R_REG(&cc->otpprog);
+ for (k = 0;
+ ((st & OTPP_START_BUSY) == OTPP_START_BUSY) && (k < OTPP_TRIES);
+ k++)
+ st = R_REG(&cc->otpprog);
+
+ if (k >= OTPP_TRIES) {
+ return 0xffff;
+ }
+ if (st & OTPP_READERR) {
+ return 0xffff;
+ }
+ st = (st & OTPP_VALUE_MASK) >> OTPP_VALUE_SHIFT;
+ return (u16) st;
+}
+
+static void *hndotp_init(si_t *sih)
+{
+ uint idx;
+ chipcregs_t *cc;
+ otpinfo_t *oi;
+ u32 cap = 0, clkdiv, otpdiv = 0;
+ void *ret = NULL;
+
+ oi = &otpinfo;
+
+ idx = ai_coreidx(sih);
+
+ /* Check for otp */
+ cc = ai_setcoreidx(sih, SI_CC_IDX);
+ if (cc != NULL) {
+ cap = R_REG(&cc->capabilities);
+ if ((cap & CC_CAP_OTPSIZE) == 0) {
+ /* Nothing there */
+ goto out;
+ }
+
+ if (!((oi->ccrev == 12) || (oi->ccrev == 17)
+ || (oi->ccrev == 22)))
+ return NULL;
+
+ /* Read the OTP byte size. chipcommon rev >= 18 has RCE so the size is
+ * 8 row (64 bytes) smaller
+ */
+ oi->size =
+ 1 << (((cap & CC_CAP_OTPSIZE) >> CC_CAP_OTPSIZE_SHIFT)
+ + CC_CAP_OTPSIZE_BASE);
+ if (oi->ccrev >= 18)
+ oi->size -= ((OTP_RC0_OFF - OTP_BOUNDARY_OFF) * 2);
+
+ oi->hwprot = (int)(R_REG(&cc->otpstatus) & OTPS_PROTECT);
+ oi->boundary = -1;
+
+ /* Check the region signature */
+ if (hndotp_otproff(oi, cc, OTP_HWSIGN_OFF) == OTP_SIGNATURE) {
+ oi->signvalid |= OTP_HW_REGION;
+ oi->boundary = hndotp_otproff(oi, cc, OTP_BOUNDARY_OFF);
+ }
+
+ if (hndotp_otproff(oi, cc, OTP_SWSIGN_OFF) == OTP_SIGNATURE)
+ oi->signvalid |= OTP_SW_REGION;
+
+ if (hndotp_otproff(oi, cc, OTP_CIDSIGN_OFF) == OTP_SIGNATURE)
+ oi->signvalid |= OTP_CID_REGION;
+
+ /* Set OTP clkdiv for stability */
+ if (oi->ccrev == 22)
+ otpdiv = 12;
+
+ if (otpdiv) {
+ clkdiv = R_REG(&cc->clkdiv);
+ clkdiv =
+ (clkdiv & ~CLKD_OTP) | (otpdiv << CLKD_OTP_SHIFT);
+ W_REG(&cc->clkdiv, clkdiv);
+ }
+ udelay(10);
+
+ ret = (void *)oi;
+ }
+
+ out: /* All done */
+ ai_setcoreidx(sih, idx);
+
+ return ret;
+}
+
+static int hndotp_read_region(void *oh, int region, u16 *data, uint *wlen)
+{
+ otpinfo_t *oi = (otpinfo_t *) oh;
+ u32 idx, st;
+ chipcregs_t *cc;
+ int i;
+
+
+ if (region != OTP_HW_REGION) {
+ /*
+ * Only support HW region
+ * (no active chips use HND OTP SW region)
+ * */
+ return -ENOTSUPP;
+ }
+
+ /* Region empty? */
+ st = oi->hwprot | oi->signvalid;
+ if ((st & region) == 0)
+ return -ENODATA;
+
+ *wlen =
+ ((int)*wlen < oi->boundary / 2) ? *wlen : (uint) oi->boundary / 2;
+
+ idx = ai_coreidx(oi->sih);
+ cc = ai_setcoreidx(oi->sih, SI_CC_IDX);
+
+ for (i = 0; i < (int)*wlen; i++)
+ data[i] = hndotp_otpr(oh, cc, i);
+
+ ai_setcoreidx(oi->sih, idx);
+
+ return 0;
+}
+
+static int hndotp_nvread(void *oh, char *data, uint *len)
+{
+ int rc = 0;
+ otpinfo_t *oi = (otpinfo_t *) oh;
+ u32 base, bound, lim = 0, st;
+ int i, chunk, gchunks, tsz = 0;
+ u32 idx;
+ chipcregs_t *cc;
+ uint offset;
+ u16 *rawotp = NULL;
+
+ /* save the orig core */
+ idx = ai_coreidx(oi->sih);
+ cc = ai_setcoreidx(oi->sih, SI_CC_IDX);
+
+ st = hndotp_status(oh);
+ if (!(st & (OTP_HW_REGION | OTP_SW_REGION))) {
+ rc = -1;
+ goto out;
+ }
+
+ /* Read the whole otp so we can easily manipulate it */
+ lim = hndotp_size(oh);
+ rawotp = kmalloc(lim, GFP_ATOMIC);
+ if (rawotp == NULL) {
+ rc = -2;
+ goto out;
+ }
+ for (i = 0; i < (int)(lim / 2); i++)
+ rawotp[i] = hndotp_otpr(oh, cc, i);
+
+ if ((st & OTP_HW_REGION) == 0) {
+ /* This could be a programming failure in the first
+ * chunk followed by one or more good chunks
+ */
+ for (i = 0; i < (int)(lim / 2); i++)
+ if (rawotp[i] == OTP_MAGIC)
+ break;
+
+ if (i < (int)(lim / 2)) {
+ base = i;
+ bound = (i * 2) + rawotp[i + 1];
+ } else {
+ rc = -3;
+ goto out;
+ }
+ } else {
+ bound = rawotp[(lim / 2) + OTP_BOUNDARY_OFF];
+
+ /* There are two cases: 1) The whole otp is used as nvram
+ * and 2) There is a hardware header followed by nvram.
+ */
+ if (rawotp[0] == OTP_MAGIC) {
+ base = 0;
+ } else
+ base = bound;
+ }
+
+ /* Find and copy the data */
+
+ chunk = 0;
+ gchunks = 0;
+ i = base / 2;
+ offset = 0;
+ while ((i < (int)(lim / 2)) && (rawotp[i] == OTP_MAGIC)) {
+ int dsz, rsz = rawotp[i + 1];
+
+ if (((i * 2) + rsz) >= (int)lim) {
+ /* Bad length, try to find another chunk anyway */
+ rsz = 6;
+ }
+ if (crc_ccitt(CRC16_INIT_VALUE, (u8 *) &rawotp[i], rsz) ==
+ CRC16_GOOD_VALUE) {
+ /* Good crc, copy the vars */
+ gchunks++;
+ dsz = rsz - 6;
+ tsz += dsz;
+ if (offset + dsz >= *len) {
+ goto out;
+ }
+ memcpy(&data[offset], &rawotp[i + 2], dsz);
+ offset += dsz;
+ /* Remove extra null characters at the end */
+ while (offset > 1 &&
+ data[offset - 1] == 0 && data[offset - 2] == 0)
+ offset--;
+ i += rsz / 2;
+ } else {
+ /* bad length or crc didn't check, try to find the next set */
+ if (rawotp[i + (rsz / 2)] == OTP_MAGIC) {
+ /* Assume length is good */
+ i += rsz / 2;
+ } else {
+ while (++i < (int)(lim / 2))
+ if (rawotp[i] == OTP_MAGIC)
+ break;
+ }
+ }
+ chunk++;
+ }
+
+ *len = offset;
+
+ out:
+ kfree(rawotp);
+ ai_setcoreidx(oi->sih, idx);
+
+ return rc;
+}
+
+static otp_fn_t hndotp_fn = {
+ (otp_size_t) hndotp_size,
+ (otp_read_bit_t) hndotp_read_bit,
+
+ (otp_init_t) hndotp_init,
+ (otp_read_region_t) hndotp_read_region,
+ (otp_nvread_t) hndotp_nvread,
+
+ (otp_status_t) hndotp_status
+};
+
+#endif /* BCMHNDOTP */
+
+/*
+ * Common Code: Compiled for IPX / HND / AUTO
+ * otp_status()
+ * otp_size()
+ * otp_read_bit()
+ * otp_init()
+ * otp_read_region()
+ * otp_nvread()
+ */
+
+int otp_status(void *oh)
+{
+ otpinfo_t *oi = (otpinfo_t *) oh;
+
+ return oi->fn->status(oh);
+}
+
+int otp_size(void *oh)
+{
+ otpinfo_t *oi = (otpinfo_t *) oh;
+
+ return oi->fn->size(oh);
+}
+
+u16 otp_read_bit(void *oh, uint offset)
+{
+ otpinfo_t *oi = (otpinfo_t *) oh;
+ uint idx = ai_coreidx(oi->sih);
+ chipcregs_t *cc = ai_setcoreidx(oi->sih, SI_CC_IDX);
+ u16 readBit = (u16) oi->fn->read_bit(oh, cc, offset);
+ ai_setcoreidx(oi->sih, idx);
+ return readBit;
+}
+
+void *otp_init(si_t *sih)
+{
+ otpinfo_t *oi;
+ void *ret = NULL;
+
+ oi = &otpinfo;
+ memset(oi, 0, sizeof(otpinfo_t));
+
+ oi->ccrev = sih->ccrev;
+
+#ifdef BCMIPXOTP
+ if (OTPTYPE_IPX(oi->ccrev))
+ oi->fn = &ipxotp_fn;
+#endif
+
+#ifdef BCMHNDOTP
+ if (OTPTYPE_HND(oi->ccrev))
+ oi->fn = &hndotp_fn;
+#endif
+
+ if (oi->fn == NULL) {
+ return NULL;
+ }
+
+ oi->sih = sih;
+
+ ret = (oi->fn->init) (sih);
+
+ return ret;
+}
+
+int
+otp_read_region(si_t *sih, int region, u16 *data,
+ uint *wlen) {
+ bool wasup = false;
+ void *oh;
+ int err = 0;
+
+ wasup = ai_is_otp_powered(sih);
+ if (!wasup)
+ ai_otp_power(sih, true);
+
+ if (!ai_is_otp_powered(sih) || ai_is_otp_disabled(sih)) {
+ err = -EPERM;
+ goto out;
+ }
+
+ oh = otp_init(sih);
+ if (oh == NULL) {
+ err = -EBADE;
+ goto out;
+ }
+
+ err = (((otpinfo_t *) oh)->fn->read_region) (oh, region, data, wlen);
+
+ out:
+ if (!wasup)
+ ai_otp_power(sih, false);
+
+ return err;
+}
+
+int otp_nvread(void *oh, char *data, uint *len)
+{
+ otpinfo_t *oi = (otpinfo_t *) oh;
+
+ return oi->fn->nvread(oh, data, len);
+}
diff --git a/drivers/staging/brcm80211/brcmsmac/bcmsrom.c b/drivers/staging/brcm80211/brcmsmac/bcmsrom.c
new file mode 100644
index 0000000..bbfc642
--- /dev/null
+++ b/drivers/staging/brcm80211/brcmsmac/bcmsrom.c
@@ -0,0 +1,714 @@
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/etherdevice.h>
+#include <bcmdefs.h>
+#include <linux/module.h>
+#include <linux/pci.h>
+#include <stdarg.h>
+#include <bcmutils.h>
+#include <hndsoc.h>
+#include <sbchipc.h>
+#include <bcmdevs.h>
+#include <pcicfg.h>
+#include <aiutils.h>
+#include <bcmsrom.h>
+#include <bcmsrom_tbl.h>
+
+#include <bcmnvram.h>
+#include <bcmotp.h>
+
+#define SROM_OFFSET(sih) ((sih->ccrev > 31) ? \
+ (((sih->cccaps & CC_CAP_SROM) == 0) ? NULL : \
+ ((u8 *)curmap + PCI_16KB0_CCREGS_OFFSET + CC_SROM_OTP)) : \
+ ((u8 *)curmap + PCI_BAR0_SPROM_OFFSET))
+
+#if defined(BCMDBG)
+#define WRITE_ENABLE_DELAY 500 /* 500 ms after write enable/disable toggle */
+#define WRITE_WORD_DELAY 20 /* 20 ms between each word write */
+#endif
+
+typedef struct varbuf {
+ char *base; /* pointer to buffer base */
+ char *buf; /* pointer to current position */
+ unsigned int size; /* current (residual) size in bytes */
+} varbuf_t;
+extern char *_vars;
+extern uint _varsz;
+
+static int initvars_srom_si(si_t *sih, void *curmap, char **vars, uint *count);
+static void _initvars_srom_pci(u8 sromrev, u16 *srom, uint off, varbuf_t *b);
+static int initvars_srom_pci(si_t *sih, void *curmap, char **vars, uint *count);
+static int initvars_flash_si(si_t *sih, char **vars, uint *count);
+static int sprom_read_pci(si_t *sih, u16 *sprom,
+ uint wordoff, u16 *buf, uint nwords, bool check_crc);
+#if defined(BCMNVRAMR)
+static int otp_read_pci(si_t *sih, u16 *buf, uint bufsz);
+#endif
+static u16 srom_cc_cmd(si_t *sih, void *ccregs, u32 cmd,
+ uint wordoff, u16 data);
+
+static int initvars_table(char *start, char *end,
+ char **vars, uint *count);
+static int initvars_flash(si_t *sih, char **vp,
+ uint len);
+
+/* Initialization of varbuf structure */
+static void varbuf_init(varbuf_t *b, char *buf, uint size)
+{
+ b->size = size;
+ b->base = b->buf = buf;
+}
+
+/* append a null terminated var=value string */
+static int varbuf_append(varbuf_t *b, const char *fmt, ...)
+{
+ va_list ap;
+ int r;
+ size_t len;
+ char *s;
+
+ if (b->size < 2)
+ return 0;
+
+ va_start(ap, fmt);
+ r = vsnprintf(b->buf, b->size, fmt, ap);
+ va_end(ap);
+
+ /* C99 snprintf behavior returns r >= size on overflow,
+ * others return -1 on overflow.
+ * All return -1 on format error.
+ * We need to leave room for 2 null terminations, one for the current var
+ * string, and one for final null of the var table. So check that the
+ * strlen written, r, leaves room for 2 chars.
+ */
+ if ((r == -1) || (r > (int)(b->size - 2))) {
+ b->size = 0;
+ return 0;
+ }
+
+ /* Remove any earlier occurrence of the same variable */
+ s = strchr(b->buf, '=');
+ if (s != NULL) {
+ len = (size_t) (s - b->buf);
+ for (s = b->base; s < b->buf;) {
+ if ((memcmp(s, b->buf, len) == 0) && s[len] == '=') {
+ len = strlen(s) + 1;
+ memmove(s, (s + len),
+ ((b->buf + r + 1) - (s + len)));
+ b->buf -= len;
+ b->size += (unsigned int)len;
+ break;
+ }
+
+ while (*s++)
+ ;
+ }
+ }
+
+ /* skip over this string's null termination */
+ r++;
+ b->size -= r;
+ b->buf += r;
+
+ return r;
+}
+
+/*
+ * Initialize local vars from the right source for this platform.
+ * Return 0 on success, nonzero on error.
+ */
+int srom_var_init(si_t *sih, uint bustype, void *curmap,
+ char **vars, uint *count)
+{
+ uint len;
+
+ len = 0;
+
+ if (vars == NULL || count == NULL)
+ return 0;
+
+ *vars = NULL;
+ *count = 0;
+
+ switch (bustype) {
+ case SI_BUS:
+ case JTAG_BUS:
+ return initvars_srom_si(sih, curmap, vars, count);
+
+ case PCI_BUS:
+ if (curmap == NULL)
+ return -1;
+
+ return initvars_srom_pci(sih, curmap, vars, count);
+
+ default:
+ break;
+ }
+ return -1;
+}
+
+/* In chips with chipcommon rev 32 and later, the srom is in chipcommon,
+ * not in the bus cores.
+ */
+static u16
+srom_cc_cmd(si_t *sih, void *ccregs, u32 cmd,
+ uint wordoff, u16 data)
+{
+ chipcregs_t *cc = (chipcregs_t *) ccregs;
+ uint wait_cnt = 1000;
+
+ if ((cmd == SRC_OP_READ) || (cmd == SRC_OP_WRITE)) {
+ W_REG(&cc->sromaddress, wordoff * 2);
+ if (cmd == SRC_OP_WRITE)
+ W_REG(&cc->sromdata, data);
+ }
+
+ W_REG(&cc->sromcontrol, SRC_START | cmd);
+
+ while (wait_cnt--) {
+ if ((R_REG(&cc->sromcontrol) & SRC_BUSY) == 0)
+ break;
+ }
+
+ if (!wait_cnt) {
+ return 0xffff;
+ }
+ if (cmd == SRC_OP_READ)
+ return (u16) R_REG(&cc->sromdata);
+ else
+ return 0xffff;
+}
+
+static inline void ltoh16_buf(u16 *buf, unsigned int size)
+{
+ for (size /= 2; size; size--)
+ *(buf + size) = le16_to_cpu(*(buf + size));
+}
+
+static inline void htol16_buf(u16 *buf, unsigned int size)
+{
+ for (size /= 2; size; size--)
+ *(buf + size) = cpu_to_le16(*(buf + size));
+}
+
+/*
+ * Read in and validate sprom.
+ * Return 0 on success, nonzero on error.
+ */
+static int
+sprom_read_pci(si_t *sih, u16 *sprom, uint wordoff,
+ u16 *buf, uint nwords, bool check_crc)
+{
+ int err = 0;
+ uint i;
+ void *ccregs = NULL;
+
+ /* read the sprom */
+ for (i = 0; i < nwords; i++) {
+
+ if (sih->ccrev > 31 && ISSIM_ENAB(sih)) {
+ /* use indirect since direct is too slow on QT */
+ if ((sih->cccaps & CC_CAP_SROM) == 0)
+ return 1;
+
+ ccregs = (void *)((u8 *) sprom - CC_SROM_OTP);
+ buf[i] =
+ srom_cc_cmd(sih, ccregs, SRC_OP_READ,
+ wordoff + i, 0);
+
+ } else {
+ if (ISSIM_ENAB(sih))
+ buf[i] = R_REG(&sprom[wordoff + i]);
+
+ buf[i] = R_REG(&sprom[wordoff + i]);
+ }
+
+ }
+
+ /* bypass crc checking for simulation to allow srom hack */
+ if (ISSIM_ENAB(sih))
+ return err;
+
+ if (check_crc) {
+
+ if (buf[0] == 0xffff) {
+ /* The hardware thinks that an srom that starts with 0xffff
+ * is blank, regardless of the rest of the content, so declare
+ * it bad.
+ */
+ return 1;
+ }
+
+ /* fixup the endianness so crc8 will pass */
+ htol16_buf(buf, nwords * 2);
+ if (bcm_crc8((u8 *) buf, nwords * 2, CRC8_INIT_VALUE) !=
+ CRC8_GOOD_VALUE) {
+ /* DBG only pci always read srom4 first, then srom8/9 */
+ err = 1;
+ }
+ /* now correct the endianness of the byte array */
+ ltoh16_buf(buf, nwords * 2);
+ }
+ return err;
+}
+
+#if defined(BCMNVRAMR)
+static int otp_read_pci(si_t *sih, u16 *buf, uint bufsz)
+{
+ u8 *otp;
+ uint sz = OTP_SZ_MAX / 2; /* size in words */
+ int err = 0;
+
+ otp = kzalloc(OTP_SZ_MAX, GFP_ATOMIC);
+ if (otp == NULL) {
+ return -EBADE;
+ }
+
+ err = otp_read_region(sih, OTP_HW_RGN, (u16 *) otp, &sz);
+
+ memcpy(buf, otp, bufsz);
+
+ kfree(otp);
+
+ /* Check CRC */
+ if (buf[0] == 0xffff) {
+ /* The hardware thinks that an srom that starts with 0xffff
+ * is blank, regardless of the rest of the content, so declare
+ * it bad.
+ */
+ return 1;
+ }
+
+ /* fixup the endianness so crc8 will pass */
+ htol16_buf(buf, bufsz);
+ if (bcm_crc8((u8 *) buf, SROM4_WORDS * 2, CRC8_INIT_VALUE) !=
+ CRC8_GOOD_VALUE) {
+ err = 1;
+ }
+ /* now correct the endianness of the byte array */
+ ltoh16_buf(buf, bufsz);
+
+ return err;
+}
+#endif /* defined(BCMNVRAMR) */
+/*
+* Create variable table from memory.
+* Return 0 on success, nonzero on error.
+*/
+static int initvars_table(char *start, char *end,
+ char **vars, uint *count)
+{
+ int c = (int)(end - start);
+
+ /* do it only when there is more than just the null string */
+ if (c > 1) {
+ char *vp = kmalloc(c, GFP_ATOMIC);
+ if (!vp)
+ return -ENOMEM;
+ memcpy(vp, start, c);
+ *vars = vp;
+ *count = c;
+ } else {
+ *vars = NULL;
+ *count = 0;
+ }
+
+ return 0;
+}
+
+/*
+ * Find variables with <devpath> from flash. 'base' points to the beginning
+ * of the table upon enter and to the end of the table upon exit when success.
+ * Return 0 on success, nonzero on error.
+ */
+static int initvars_flash(si_t *sih, char **base, uint len)
+{
+ char *vp = *base;
+ char *flash;
+ int err;
+ char *s;
+ uint l, dl, copy_len;
+ char devpath[SI_DEVPATH_BUFSZ];
+
+ /* allocate memory and read in flash */
+ flash = kmalloc(NVRAM_SPACE, GFP_ATOMIC);
+ if (!flash)
+ return -ENOMEM;
+ err = nvram_getall(flash, NVRAM_SPACE);
+ if (err)
+ goto exit;
+
+ ai_devpath(sih, devpath, sizeof(devpath));
+
+ /* grab vars with the <devpath> prefix in name */
+ dl = strlen(devpath);
+ for (s = flash; s && *s; s += l + 1) {
+ l = strlen(s);
+
+ /* skip non-matching variable */
+ if (strncmp(s, devpath, dl))
+ continue;
+
+ /* is there enough room to copy? */
+ copy_len = l - dl + 1;
+ if (len < copy_len) {
+ err = -EOVERFLOW;
+ goto exit;
+ }
+
+ /* no prefix, just the name=value */
+ strncpy(vp, &s[dl], copy_len);
+ vp += copy_len;
+ len -= copy_len;
+ }
+
+ /* add null string as terminator */
+ if (len < 1) {
+ err = -EOVERFLOW;
+ goto exit;
+ }
+ *vp++ = '\0';
+
+ *base = vp;
+
+ exit: kfree(flash);
+ return err;
+}
+
+/*
+ * Initialize nonvolatile variable table from flash.
+ * Return 0 on success, nonzero on error.
+ */
+static int initvars_flash_si(si_t *sih, char **vars, uint *count)
+{
+ char *vp, *base;
+ int err;
+
+ base = vp = kmalloc(MAXSZ_NVRAM_VARS, GFP_ATOMIC);
+ if (!vp)
+ return -ENOMEM;
+
+ err = initvars_flash(sih, &vp, MAXSZ_NVRAM_VARS);
+ if (err == 0)
+ err = initvars_table(base, vp, vars, count);
+
+ kfree(base);
+
+ return err;
+}
+
+/* Parse SROM and create name=value pairs. 'srom' points to
+ * the SROM word array. 'off' specifies the offset of the
+ * first word 'srom' points to, which should be either 0 or
+ * SROM3_SWRG_OFF (full SROM or software region).
+ */
+
+static uint mask_shift(u16 mask)
+{
+ uint i;
+ for (i = 0; i < (sizeof(mask) << 3); i++) {
+ if (mask & (1 << i))
+ return i;
+ }
+ return 0;
+}
+
+static uint mask_width(u16 mask)
+{
+ int i;
+ for (i = (sizeof(mask) << 3) - 1; i >= 0; i--) {
+ if (mask & (1 << i))
+ return (uint) (i - mask_shift(mask) + 1);
+ }
+ return 0;
+}
+
+static void _initvars_srom_pci(u8 sromrev, u16 *srom, uint off, varbuf_t *b)
+{
+ u16 w;
+ u32 val;
+ const sromvar_t *srv;
+ uint width;
+ uint flags;
+ u32 sr = (1 << sromrev);
+
+ varbuf_append(b, "sromrev=%d", sromrev);
+
+ for (srv = pci_sromvars; srv->name != NULL; srv++) {
+ const char *name;
+
+ if ((srv->revmask & sr) == 0)
+ continue;
+
+ if (srv->off < off)
+ continue;
+
+ flags = srv->flags;
+ name = srv->name;
+
+ /* This entry is for mfgc only. Don't generate param for it, */
+ if (flags & SRFL_NOVAR)
+ continue;
+
+ if (flags & SRFL_ETHADDR) {
+ u8 ea[ETH_ALEN];
+
+ ea[0] = (srom[srv->off - off] >> 8) & 0xff;
+ ea[1] = srom[srv->off - off] & 0xff;
+ ea[2] = (srom[srv->off + 1 - off] >> 8) & 0xff;
+ ea[3] = srom[srv->off + 1 - off] & 0xff;
+ ea[4] = (srom[srv->off + 2 - off] >> 8) & 0xff;
+ ea[5] = srom[srv->off + 2 - off] & 0xff;
+
+ varbuf_append(b, "%s=%pM", name, ea);
+ } else {
+ w = srom[srv->off - off];
+ val = (w & srv->mask) >> mask_shift(srv->mask);
+ width = mask_width(srv->mask);
+
+ while (srv->flags & SRFL_MORE) {
+ srv++;
+ if (srv->off == 0 || srv->off < off)
+ continue;
+
+ w = srom[srv->off - off];
+ val +=
+ ((w & srv->mask) >> mask_shift(srv->
+ mask)) <<
+ width;
+ width += mask_width(srv->mask);
+ }
+
+ if ((flags & SRFL_NOFFS)
+ && ((int)val == (1 << width) - 1))
+ continue;
+
+ if (flags & SRFL_CCODE) {
+ if (val == 0)
+ varbuf_append(b, "ccode=");
+ else
+ varbuf_append(b, "ccode=%c%c",
+ (val >> 8), (val & 0xff));
+ }
+ /* LED Powersave duty cycle has to be scaled:
+ *(oncount >> 24) (offcount >> 8)
+ */
+ else if (flags & SRFL_LEDDC) {
+ u32 w32 = (((val >> 8) & 0xff) << 24) | /* oncount */
+ (((val & 0xff)) << 8); /* offcount */
+ varbuf_append(b, "leddc=%d", w32);
+ } else if (flags & SRFL_PRHEX)
+ varbuf_append(b, "%s=0x%x", name, val);
+ else if ((flags & SRFL_PRSIGN)
+ && (val & (1 << (width - 1))))
+ varbuf_append(b, "%s=%d", name,
+ (int)(val | (~0 << width)));
+ else
+ varbuf_append(b, "%s=%u", name, val);
+ }
+ }
+
+ if (sromrev >= 4) {
+ /* Do per-path variables */
+ uint p, pb, psz;
+
+ if (sromrev >= 8) {
+ pb = SROM8_PATH0;
+ psz = SROM8_PATH1 - SROM8_PATH0;
+ } else {
+ pb = SROM4_PATH0;
+ psz = SROM4_PATH1 - SROM4_PATH0;
+ }
+
+ for (p = 0; p < MAX_PATH_SROM; p++) {
+ for (srv = perpath_pci_sromvars; srv->name != NULL;
+ srv++) {
+ if ((srv->revmask & sr) == 0)
+ continue;
+
+ if (pb + srv->off < off)
+ continue;
+
+ /* This entry is for mfgc only. Don't generate param for it, */
+ if (srv->flags & SRFL_NOVAR)
+ continue;
+
+ w = srom[pb + srv->off - off];
+ val = (w & srv->mask) >> mask_shift(srv->mask);
+ width = mask_width(srv->mask);
+
+ /* Cheating: no per-path var is more than 1 word */
+
+ if ((srv->flags & SRFL_NOFFS)
+ && ((int)val == (1 << width) - 1))
+ continue;
+
+ if (srv->flags & SRFL_PRHEX)
+ varbuf_append(b, "%s%d=0x%x", srv->name,
+ p, val);
+ else
+ varbuf_append(b, "%s%d=%d", srv->name,
+ p, val);
+ }
+ pb += psz;
+ }
+ }
+}
+
+/*
+ * Initialize nonvolatile variable table from sprom.
+ * Return 0 on success, nonzero on error.
+ */
+static int initvars_srom_pci(si_t *sih, void *curmap, char **vars, uint *count)
+{
+ u16 *srom, *sromwindow;
+ u8 sromrev = 0;
+ u32 sr;
+ varbuf_t b;
+ char *vp, *base = NULL;
+ bool flash = false;
+ int err = 0;
+
+ /*
+ * Apply CRC over SROM content regardless SROM is present or not,
+ * and use variable <devpath>sromrev's existence in flash to decide
+ * if we should return an error when CRC fails or read SROM variables
+ * from flash.
+ */
+ srom = kmalloc(SROM_MAX, GFP_ATOMIC);
+ if (!srom)
+ return -2;
+
+ sromwindow = (u16 *) SROM_OFFSET(sih);
+ if (ai_is_sprom_available(sih)) {
+ err =
+ sprom_read_pci(sih, sromwindow, 0, srom, SROM_WORDS,
+ true);
+
+ if ((srom[SROM4_SIGN] == SROM4_SIGNATURE) ||
+ (((sih->buscoretype == PCIE_CORE_ID)
+ && (sih->buscorerev >= 6))
+ || ((sih->buscoretype == PCI_CORE_ID)
+ && (sih->buscorerev >= 0xe)))) {
+ /* sromrev >= 4, read more */
+ err =
+ sprom_read_pci(sih, sromwindow, 0, srom,
+ SROM4_WORDS, true);
+ sromrev = srom[SROM4_CRCREV] & 0xff;
+ } else if (err == 0) {
+ /* srom is good and is rev < 4 */
+ /* top word of sprom contains version and crc8 */
+ sromrev = srom[SROM_CRCREV] & 0xff;
+ /* bcm4401 sroms misprogrammed */
+ if (sromrev == 0x10)
+ sromrev = 1;
+ }
+ }
+#if defined(BCMNVRAMR)
+ /* Use OTP if SPROM not available */
+ else {
+ err = otp_read_pci(sih, srom, SROM_MAX);
+ if (err == 0)
+ /* OTP only contain SROM rev8/rev9 for now */
+ sromrev = srom[SROM4_CRCREV] & 0xff;
+ else
+ err = 1;
+ }
+#else
+ else
+ err = 1;
+#endif
+
+ /*
+ * We want internal/wltest driver to come up with default
+ * sromvars so we can program a blank SPROM/OTP.
+ */
+ if (err) {
+ char *value;
+ u32 val;
+ val = 0;
+
+ value = ai_getdevpathvar(sih, "sromrev");
+ if (value) {
+ sromrev = (u8) simple_strtoul(value, NULL, 0);
+ flash = true;
+ goto varscont;
+ }
+
+ value = ai_getnvramflvar(sih, "sromrev");
+ if (value) {
+ err = 0;
+ goto errout;
+ }
+
+ {
+ err = -1;
+ goto errout;
+ }
+ }
+
+ varscont:
+ /* Bitmask for the sromrev */
+ sr = 1 << sromrev;
+
+ /* srom version check: Current valid versions: 1, 2, 3, 4, 5, 8, 9 */
+ if ((sr & 0x33e) == 0) {
+ err = -2;
+ goto errout;
+ }
+
+ base = vp = kmalloc(MAXSZ_NVRAM_VARS, GFP_ATOMIC);
+ if (!vp) {
+ err = -2;
+ goto errout;
+ }
+
+ /* read variables from flash */
+ if (flash) {
+ err = initvars_flash(sih, &vp, MAXSZ_NVRAM_VARS);
+ if (err)
+ goto errout;
+ goto varsdone;
+ }
+
+ varbuf_init(&b, base, MAXSZ_NVRAM_VARS);
+
+ /* parse SROM into name=value pairs. */
+ _initvars_srom_pci(sromrev, srom, 0, &b);
+
+ /* final nullbyte terminator */
+ vp = b.buf;
+ *vp++ = '\0';
+
+ varsdone:
+ err = initvars_table(base, vp, vars, count);
+
+ errout:
+ if (base)
+ kfree(base);
+
+ kfree(srom);
+ return err;
+}
+
+
+static int initvars_srom_si(si_t *sih, void *curmap, char **vars, uint *varsz)
+{
+ /* Search flash nvram section for srom variables */
+ return initvars_flash_si(sih, vars, varsz);
+}
diff --git a/drivers/staging/brcm80211/brcmsmac/bcmsrom_tbl.h b/drivers/staging/brcm80211/brcmsmac/bcmsrom_tbl.h
new file mode 100644
index 0000000..f4b3e61
--- /dev/null
+++ b/drivers/staging/brcm80211/brcmsmac/bcmsrom_tbl.h
@@ -0,0 +1,513 @@
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef _bcmsrom_tbl_h_
+#define _bcmsrom_tbl_h_
+
+#include "wlioctl.h"
+
+typedef struct {
+ const char *name;
+ u32 revmask;
+ u32 flags;
+ u16 off;
+ u16 mask;
+} sromvar_t;
+
+#define SRFL_MORE 1 /* value continues as described by the next entry */
+#define SRFL_NOFFS 2 /* value bits can't be all one's */
+#define SRFL_PRHEX 4 /* value is in hexdecimal format */
+#define SRFL_PRSIGN 8 /* value is in signed decimal format */
+#define SRFL_CCODE 0x10 /* value is in country code format */
+#define SRFL_ETHADDR 0x20 /* value is an Ethernet address */
+#define SRFL_LEDDC 0x40 /* value is an LED duty cycle */
+#define SRFL_NOVAR 0x80 /* do not generate a nvram param, entry is for mfgc */
+
+/* Assumptions:
+ * - Ethernet address spans across 3 consective words
+ *
+ * Table rules:
+ * - Add multiple entries next to each other if a value spans across multiple words
+ * (even multiple fields in the same word) with each entry except the last having
+ * it's SRFL_MORE bit set.
+ * - Ethernet address entry does not follow above rule and must not have SRFL_MORE
+ * bit set. Its SRFL_ETHADDR bit implies it takes multiple words.
+ * - The last entry's name field must be NULL to indicate the end of the table. Other
+ * entries must have non-NULL name.
+ */
+
+static const sromvar_t pci_sromvars[] = {
+ {"devid", 0xffffff00, SRFL_PRHEX | SRFL_NOVAR, PCI_F0DEVID, 0xffff},
+ {"boardrev", 0x0000000e, SRFL_PRHEX, SROM_AABREV, SROM_BR_MASK},
+ {"boardrev", 0x000000f0, SRFL_PRHEX, SROM4_BREV, 0xffff},
+ {"boardrev", 0xffffff00, SRFL_PRHEX, SROM8_BREV, 0xffff},
+ {"boardflags", 0x00000002, SRFL_PRHEX, SROM_BFL, 0xffff},
+ {"boardflags", 0x00000004, SRFL_PRHEX | SRFL_MORE, SROM_BFL, 0xffff},
+ {"", 0, 0, SROM_BFL2, 0xffff},
+ {"boardflags", 0x00000008, SRFL_PRHEX | SRFL_MORE, SROM_BFL, 0xffff},
+ {"", 0, 0, SROM3_BFL2, 0xffff},
+ {"boardflags", 0x00000010, SRFL_PRHEX | SRFL_MORE, SROM4_BFL0, 0xffff},
+ {"", 0, 0, SROM4_BFL1, 0xffff},
+ {"boardflags", 0x000000e0, SRFL_PRHEX | SRFL_MORE, SROM5_BFL0, 0xffff},
+ {"", 0, 0, SROM5_BFL1, 0xffff},
+ {"boardflags", 0xffffff00, SRFL_PRHEX | SRFL_MORE, SROM8_BFL0, 0xffff},
+ {"", 0, 0, SROM8_BFL1, 0xffff},
+ {"boardflags2", 0x00000010, SRFL_PRHEX | SRFL_MORE, SROM4_BFL2, 0xffff},
+ {"", 0, 0, SROM4_BFL3, 0xffff},
+ {"boardflags2", 0x000000e0, SRFL_PRHEX | SRFL_MORE, SROM5_BFL2, 0xffff},
+ {"", 0, 0, SROM5_BFL3, 0xffff},
+ {"boardflags2", 0xffffff00, SRFL_PRHEX | SRFL_MORE, SROM8_BFL2, 0xffff},
+ {"", 0, 0, SROM8_BFL3, 0xffff},
+ {"boardtype", 0xfffffffc, SRFL_PRHEX, SROM_SSID, 0xffff},
+ {"boardnum", 0x00000006, 0, SROM_MACLO_IL0, 0xffff},
+ {"boardnum", 0x00000008, 0, SROM3_MACLO, 0xffff},
+ {"boardnum", 0x00000010, 0, SROM4_MACLO, 0xffff},
+ {"boardnum", 0x000000e0, 0, SROM5_MACLO, 0xffff},
+ {"boardnum", 0xffffff00, 0, SROM8_MACLO, 0xffff},
+ {"cc", 0x00000002, 0, SROM_AABREV, SROM_CC_MASK},
+ {"regrev", 0x00000008, 0, SROM_OPO, 0xff00},
+ {"regrev", 0x00000010, 0, SROM4_REGREV, 0x00ff},
+ {"regrev", 0x000000e0, 0, SROM5_REGREV, 0x00ff},
+ {"regrev", 0xffffff00, 0, SROM8_REGREV, 0x00ff},
+ {"ledbh0", 0x0000000e, SRFL_NOFFS, SROM_LEDBH10, 0x00ff},
+ {"ledbh1", 0x0000000e, SRFL_NOFFS, SROM_LEDBH10, 0xff00},
+ {"ledbh2", 0x0000000e, SRFL_NOFFS, SROM_LEDBH32, 0x00ff},
+ {"ledbh3", 0x0000000e, SRFL_NOFFS, SROM_LEDBH32, 0xff00},
+ {"ledbh0", 0x00000010, SRFL_NOFFS, SROM4_LEDBH10, 0x00ff},
+ {"ledbh1", 0x00000010, SRFL_NOFFS, SROM4_LEDBH10, 0xff00},
+ {"ledbh2", 0x00000010, SRFL_NOFFS, SROM4_LEDBH32, 0x00ff},
+ {"ledbh3", 0x00000010, SRFL_NOFFS, SROM4_LEDBH32, 0xff00},
+ {"ledbh0", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH10, 0x00ff},
+ {"ledbh1", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH10, 0xff00},
+ {"ledbh2", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH32, 0x00ff},
+ {"ledbh3", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH32, 0xff00},
+ {"ledbh0", 0xffffff00, SRFL_NOFFS, SROM8_LEDBH10, 0x00ff},
+ {"ledbh1", 0xffffff00, SRFL_NOFFS, SROM8_LEDBH10, 0xff00},
+ {"ledbh2", 0xffffff00, SRFL_NOFFS, SROM8_LEDBH32, 0x00ff},
+ {"ledbh3", 0xffffff00, SRFL_NOFFS, SROM8_LEDBH32, 0xff00},
+ {"pa0b0", 0x0000000e, SRFL_PRHEX, SROM_WL0PAB0, 0xffff},
+ {"pa0b1", 0x0000000e, SRFL_PRHEX, SROM_WL0PAB1, 0xffff},
+ {"pa0b2", 0x0000000e, SRFL_PRHEX, SROM_WL0PAB2, 0xffff},
+ {"pa0itssit", 0x0000000e, 0, SROM_ITT, 0x00ff},
+ {"pa0maxpwr", 0x0000000e, 0, SROM_WL10MAXP, 0x00ff},
+ {"pa0b0", 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB0, 0xffff},
+ {"pa0b1", 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB1, 0xffff},
+ {"pa0b2", 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB2, 0xffff},
+ {"pa0itssit", 0xffffff00, 0, SROM8_W0_ITTMAXP, 0xff00},
+ {"pa0maxpwr", 0xffffff00, 0, SROM8_W0_ITTMAXP, 0x00ff},
+ {"opo", 0x0000000c, 0, SROM_OPO, 0x00ff},
+ {"opo", 0xffffff00, 0, SROM8_2G_OFDMPO, 0x00ff},
+ {"aa2g", 0x0000000e, 0, SROM_AABREV, SROM_AA0_MASK},
+ {"aa2g", 0x000000f0, 0, SROM4_AA, 0x00ff},
+ {"aa2g", 0xffffff00, 0, SROM8_AA, 0x00ff},
+ {"aa5g", 0x0000000e, 0, SROM_AABREV, SROM_AA1_MASK},
+ {"aa5g", 0x000000f0, 0, SROM4_AA, 0xff00},
+ {"aa5g", 0xffffff00, 0, SROM8_AA, 0xff00},
+ {"ag0", 0x0000000e, 0, SROM_AG10, 0x00ff},
+ {"ag1", 0x0000000e, 0, SROM_AG10, 0xff00},
+ {"ag0", 0x000000f0, 0, SROM4_AG10, 0x00ff},
+ {"ag1", 0x000000f0, 0, SROM4_AG10, 0xff00},
+ {"ag2", 0x000000f0, 0, SROM4_AG32, 0x00ff},
+ {"ag3", 0x000000f0, 0, SROM4_AG32, 0xff00},
+ {"ag0", 0xffffff00, 0, SROM8_AG10, 0x00ff},
+ {"ag1", 0xffffff00, 0, SROM8_AG10, 0xff00},
+ {"ag2", 0xffffff00, 0, SROM8_AG32, 0x00ff},
+ {"ag3", 0xffffff00, 0, SROM8_AG32, 0xff00},
+ {"pa1b0", 0x0000000e, SRFL_PRHEX, SROM_WL1PAB0, 0xffff},
+ {"pa1b1", 0x0000000e, SRFL_PRHEX, SROM_WL1PAB1, 0xffff},
+ {"pa1b2", 0x0000000e, SRFL_PRHEX, SROM_WL1PAB2, 0xffff},
+ {"pa1lob0", 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB0, 0xffff},
+ {"pa1lob1", 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB1, 0xffff},
+ {"pa1lob2", 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB2, 0xffff},
+ {"pa1hib0", 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB0, 0xffff},
+ {"pa1hib1", 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB1, 0xffff},
+ {"pa1hib2", 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB2, 0xffff},
+ {"pa1itssit", 0x0000000e, 0, SROM_ITT, 0xff00},
+ {"pa1maxpwr", 0x0000000e, 0, SROM_WL10MAXP, 0xff00},
+ {"pa1lomaxpwr", 0x0000000c, 0, SROM_WL1LHMAXP, 0xff00},
+ {"pa1himaxpwr", 0x0000000c, 0, SROM_WL1LHMAXP, 0x00ff},
+ {"pa1b0", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0, 0xffff},
+ {"pa1b1", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1, 0xffff},
+ {"pa1b2", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2, 0xffff},
+ {"pa1lob0", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0_LC, 0xffff},
+ {"pa1lob1", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1_LC, 0xffff},
+ {"pa1lob2", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2_LC, 0xffff},
+ {"pa1hib0", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0_HC, 0xffff},
+ {"pa1hib1", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1_HC, 0xffff},
+ {"pa1hib2", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2_HC, 0xffff},
+ {"pa1itssit", 0xffffff00, 0, SROM8_W1_ITTMAXP, 0xff00},
+ {"pa1maxpwr", 0xffffff00, 0, SROM8_W1_ITTMAXP, 0x00ff},
+ {"pa1lomaxpwr", 0xffffff00, 0, SROM8_W1_MAXP_LCHC, 0xff00},
+ {"pa1himaxpwr", 0xffffff00, 0, SROM8_W1_MAXP_LCHC, 0x00ff},
+ {"bxa2g", 0x00000008, 0, SROM_BXARSSI2G, 0x1800},
+ {"rssisav2g", 0x00000008, 0, SROM_BXARSSI2G, 0x0700},
+ {"rssismc2g", 0x00000008, 0, SROM_BXARSSI2G, 0x00f0},
+ {"rssismf2g", 0x00000008, 0, SROM_BXARSSI2G, 0x000f},
+ {"bxa2g", 0xffffff00, 0, SROM8_BXARSSI2G, 0x1800},
+ {"rssisav2g", 0xffffff00, 0, SROM8_BXARSSI2G, 0x0700},
+ {"rssismc2g", 0xffffff00, 0, SROM8_BXARSSI2G, 0x00f0},
+ {"rssismf2g", 0xffffff00, 0, SROM8_BXARSSI2G, 0x000f},
+ {"bxa5g", 0x00000008, 0, SROM_BXARSSI5G, 0x1800},
+ {"rssisav5g", 0x00000008, 0, SROM_BXARSSI5G, 0x0700},
+ {"rssismc5g", 0x00000008, 0, SROM_BXARSSI5G, 0x00f0},
+ {"rssismf5g", 0x00000008, 0, SROM_BXARSSI5G, 0x000f},
+ {"bxa5g", 0xffffff00, 0, SROM8_BXARSSI5G, 0x1800},
+ {"rssisav5g", 0xffffff00, 0, SROM8_BXARSSI5G, 0x0700},
+ {"rssismc5g", 0xffffff00, 0, SROM8_BXARSSI5G, 0x00f0},
+ {"rssismf5g", 0xffffff00, 0, SROM8_BXARSSI5G, 0x000f},
+ {"tri2g", 0x00000008, 0, SROM_TRI52G, 0x00ff},
+ {"tri5g", 0x00000008, 0, SROM_TRI52G, 0xff00},
+ {"tri5gl", 0x00000008, 0, SROM_TRI5GHL, 0x00ff},
+ {"tri5gh", 0x00000008, 0, SROM_TRI5GHL, 0xff00},
+ {"tri2g", 0xffffff00, 0, SROM8_TRI52G, 0x00ff},
+ {"tri5g", 0xffffff00, 0, SROM8_TRI52G, 0xff00},
+ {"tri5gl", 0xffffff00, 0, SROM8_TRI5GHL, 0x00ff},
+ {"tri5gh", 0xffffff00, 0, SROM8_TRI5GHL, 0xff00},
+ {"rxpo2g", 0x00000008, SRFL_PRSIGN, SROM_RXPO52G, 0x00ff},
+ {"rxpo5g", 0x00000008, SRFL_PRSIGN, SROM_RXPO52G, 0xff00},
+ {"rxpo2g", 0xffffff00, SRFL_PRSIGN, SROM8_RXPO52G, 0x00ff},
+ {"rxpo5g", 0xffffff00, SRFL_PRSIGN, SROM8_RXPO52G, 0xff00},
+ {"txchain", 0x000000f0, SRFL_NOFFS, SROM4_TXRXC, SROM4_TXCHAIN_MASK},
+ {"rxchain", 0x000000f0, SRFL_NOFFS, SROM4_TXRXC, SROM4_RXCHAIN_MASK},
+ {"antswitch", 0x000000f0, SRFL_NOFFS, SROM4_TXRXC, SROM4_SWITCH_MASK},
+ {"txchain", 0xffffff00, SRFL_NOFFS, SROM8_TXRXC, SROM4_TXCHAIN_MASK},
+ {"rxchain", 0xffffff00, SRFL_NOFFS, SROM8_TXRXC, SROM4_RXCHAIN_MASK},
+ {"antswitch", 0xffffff00, SRFL_NOFFS, SROM8_TXRXC, SROM4_SWITCH_MASK},
+ {"tssipos2g", 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_TSSIPOS_MASK},
+ {"extpagain2g", 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_EXTPA_GAIN_MASK},
+ {"pdetrange2g", 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_PDET_RANGE_MASK},
+ {"triso2g", 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_TR_ISO_MASK},
+ {"antswctl2g", 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_ANTSWLUT_MASK},
+ {"tssipos5g", 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_TSSIPOS_MASK},
+ {"extpagain5g", 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_EXTPA_GAIN_MASK},
+ {"pdetrange5g", 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_PDET_RANGE_MASK},
+ {"triso5g", 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_TR_ISO_MASK},
+ {"antswctl5g", 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_ANTSWLUT_MASK},
+ {"tempthresh", 0xffffff00, 0, SROM8_THERMAL, 0xff00},
+ {"tempoffset", 0xffffff00, 0, SROM8_THERMAL, 0x00ff},
+ {"txpid2ga0", 0x000000f0, 0, SROM4_TXPID2G, 0x00ff},
+ {"txpid2ga1", 0x000000f0, 0, SROM4_TXPID2G, 0xff00},
+ {"txpid2ga2", 0x000000f0, 0, SROM4_TXPID2G + 1, 0x00ff},
+ {"txpid2ga3", 0x000000f0, 0, SROM4_TXPID2G + 1, 0xff00},
+ {"txpid5ga0", 0x000000f0, 0, SROM4_TXPID5G, 0x00ff},
+ {"txpid5ga1", 0x000000f0, 0, SROM4_TXPID5G, 0xff00},
+ {"txpid5ga2", 0x000000f0, 0, SROM4_TXPID5G + 1, 0x00ff},
+ {"txpid5ga3", 0x000000f0, 0, SROM4_TXPID5G + 1, 0xff00},
+ {"txpid5gla0", 0x000000f0, 0, SROM4_TXPID5GL, 0x00ff},
+ {"txpid5gla1", 0x000000f0, 0, SROM4_TXPID5GL, 0xff00},
+ {"txpid5gla2", 0x000000f0, 0, SROM4_TXPID5GL + 1, 0x00ff},
+ {"txpid5gla3", 0x000000f0, 0, SROM4_TXPID5GL + 1, 0xff00},
+ {"txpid5gha0", 0x000000f0, 0, SROM4_TXPID5GH, 0x00ff},
+ {"txpid5gha1", 0x000000f0, 0, SROM4_TXPID5GH, 0xff00},
+ {"txpid5gha2", 0x000000f0, 0, SROM4_TXPID5GH + 1, 0x00ff},
+ {"txpid5gha3", 0x000000f0, 0, SROM4_TXPID5GH + 1, 0xff00},
+
+ {"ccode", 0x0000000f, SRFL_CCODE, SROM_CCODE, 0xffff},
+ {"ccode", 0x00000010, SRFL_CCODE, SROM4_CCODE, 0xffff},
+ {"ccode", 0x000000e0, SRFL_CCODE, SROM5_CCODE, 0xffff},
+ {"ccode", 0xffffff00, SRFL_CCODE, SROM8_CCODE, 0xffff},
+ {"macaddr", 0xffffff00, SRFL_ETHADDR, SROM8_MACHI, 0xffff},
+ {"macaddr", 0x000000e0, SRFL_ETHADDR, SROM5_MACHI, 0xffff},
+ {"macaddr", 0x00000010, SRFL_ETHADDR, SROM4_MACHI, 0xffff},
+ {"macaddr", 0x00000008, SRFL_ETHADDR, SROM3_MACHI, 0xffff},
+ {"il0macaddr", 0x00000007, SRFL_ETHADDR, SROM_MACHI_IL0, 0xffff},
+ {"et1macaddr", 0x00000007, SRFL_ETHADDR, SROM_MACHI_ET1, 0xffff},
+ {"leddc", 0xffffff00, SRFL_NOFFS | SRFL_LEDDC, SROM8_LEDDC, 0xffff},
+ {"leddc", 0x000000e0, SRFL_NOFFS | SRFL_LEDDC, SROM5_LEDDC, 0xffff},
+ {"leddc", 0x00000010, SRFL_NOFFS | SRFL_LEDDC, SROM4_LEDDC, 0xffff},
+ {"leddc", 0x00000008, SRFL_NOFFS | SRFL_LEDDC, SROM3_LEDDC, 0xffff},
+ {"rawtempsense", 0xffffff00, SRFL_PRHEX, SROM8_MPWR_RAWTS, 0x01ff},
+ {"measpower", 0xffffff00, SRFL_PRHEX, SROM8_MPWR_RAWTS, 0xfe00},
+ {"tempsense_slope", 0xffffff00, SRFL_PRHEX, SROM8_TS_SLP_OPT_CORRX,
+ 0x00ff},
+ {"tempcorrx", 0xffffff00, SRFL_PRHEX, SROM8_TS_SLP_OPT_CORRX, 0xfc00},
+ {"tempsense_option", 0xffffff00, SRFL_PRHEX, SROM8_TS_SLP_OPT_CORRX,
+ 0x0300},
+ {"freqoffset_corr", 0xffffff00, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP,
+ 0x000f},
+ {"iqcal_swp_dis", 0xffffff00, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP, 0x0010},
+ {"hw_iqcal_en", 0xffffff00, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP, 0x0020},
+ {"phycal_tempdelta", 0xffffff00, 0, SROM8_PHYCAL_TEMPDELTA, 0x00ff},
+
+ {"cck2gpo", 0x000000f0, 0, SROM4_2G_CCKPO, 0xffff},
+ {"cck2gpo", 0x00000100, 0, SROM8_2G_CCKPO, 0xffff},
+ {"ofdm2gpo", 0x000000f0, SRFL_MORE, SROM4_2G_OFDMPO, 0xffff},
+ {"", 0, 0, SROM4_2G_OFDMPO + 1, 0xffff},
+ {"ofdm5gpo", 0x000000f0, SRFL_MORE, SROM4_5G_OFDMPO, 0xffff},
+ {"", 0, 0, SROM4_5G_OFDMPO + 1, 0xffff},
+ {"ofdm5glpo", 0x000000f0, SRFL_MORE, SROM4_5GL_OFDMPO, 0xffff},
+ {"", 0, 0, SROM4_5GL_OFDMPO + 1, 0xffff},
+ {"ofdm5ghpo", 0x000000f0, SRFL_MORE, SROM4_5GH_OFDMPO, 0xffff},
+ {"", 0, 0, SROM4_5GH_OFDMPO + 1, 0xffff},
+ {"ofdm2gpo", 0x00000100, SRFL_MORE, SROM8_2G_OFDMPO, 0xffff},
+ {"", 0, 0, SROM8_2G_OFDMPO + 1, 0xffff},
+ {"ofdm5gpo", 0x00000100, SRFL_MORE, SROM8_5G_OFDMPO, 0xffff},
+ {"", 0, 0, SROM8_5G_OFDMPO + 1, 0xffff},
+ {"ofdm5glpo", 0x00000100, SRFL_MORE, SROM8_5GL_OFDMPO, 0xffff},
+ {"", 0, 0, SROM8_5GL_OFDMPO + 1, 0xffff},
+ {"ofdm5ghpo", 0x00000100, SRFL_MORE, SROM8_5GH_OFDMPO, 0xffff},
+ {"", 0, 0, SROM8_5GH_OFDMPO + 1, 0xffff},
+ {"mcs2gpo0", 0x000000f0, 0, SROM4_2G_MCSPO, 0xffff},
+ {"mcs2gpo1", 0x000000f0, 0, SROM4_2G_MCSPO + 1, 0xffff},
+ {"mcs2gpo2", 0x000000f0, 0, SROM4_2G_MCSPO + 2, 0xffff},
+ {"mcs2gpo3", 0x000000f0, 0, SROM4_2G_MCSPO + 3, 0xffff},
+ {"mcs2gpo4", 0x000000f0, 0, SROM4_2G_MCSPO + 4, 0xffff},
+ {"mcs2gpo5", 0x000000f0, 0, SROM4_2G_MCSPO + 5, 0xffff},
+ {"mcs2gpo6", 0x000000f0, 0, SROM4_2G_MCSPO + 6, 0xffff},
+ {"mcs2gpo7", 0x000000f0, 0, SROM4_2G_MCSPO + 7, 0xffff},
+ {"mcs5gpo0", 0x000000f0, 0, SROM4_5G_MCSPO, 0xffff},
+ {"mcs5gpo1", 0x000000f0, 0, SROM4_5G_MCSPO + 1, 0xffff},
+ {"mcs5gpo2", 0x000000f0, 0, SROM4_5G_MCSPO + 2, 0xffff},
+ {"mcs5gpo3", 0x000000f0, 0, SROM4_5G_MCSPO + 3, 0xffff},
+ {"mcs5gpo4", 0x000000f0, 0, SROM4_5G_MCSPO + 4, 0xffff},
+ {"mcs5gpo5", 0x000000f0, 0, SROM4_5G_MCSPO + 5, 0xffff},
+ {"mcs5gpo6", 0x000000f0, 0, SROM4_5G_MCSPO + 6, 0xffff},
+ {"mcs5gpo7", 0x000000f0, 0, SROM4_5G_MCSPO + 7, 0xffff},
+ {"mcs5glpo0", 0x000000f0, 0, SROM4_5GL_MCSPO, 0xffff},
+ {"mcs5glpo1", 0x000000f0, 0, SROM4_5GL_MCSPO + 1, 0xffff},
+ {"mcs5glpo2", 0x000000f0, 0, SROM4_5GL_MCSPO + 2, 0xffff},
+ {"mcs5glpo3", 0x000000f0, 0, SROM4_5GL_MCSPO + 3, 0xffff},
+ {"mcs5glpo4", 0x000000f0, 0, SROM4_5GL_MCSPO + 4, 0xffff},
+ {"mcs5glpo5", 0x000000f0, 0, SROM4_5GL_MCSPO + 5, 0xffff},
+ {"mcs5glpo6", 0x000000f0, 0, SROM4_5GL_MCSPO + 6, 0xffff},
+ {"mcs5glpo7", 0x000000f0, 0, SROM4_5GL_MCSPO + 7, 0xffff},
+ {"mcs5ghpo0", 0x000000f0, 0, SROM4_5GH_MCSPO, 0xffff},
+ {"mcs5ghpo1", 0x000000f0, 0, SROM4_5GH_MCSPO + 1, 0xffff},
+ {"mcs5ghpo2", 0x000000f0, 0, SROM4_5GH_MCSPO + 2, 0xffff},
+ {"mcs5ghpo3", 0x000000f0, 0, SROM4_5GH_MCSPO + 3, 0xffff},
+ {"mcs5ghpo4", 0x000000f0, 0, SROM4_5GH_MCSPO + 4, 0xffff},
+ {"mcs5ghpo5", 0x000000f0, 0, SROM4_5GH_MCSPO + 5, 0xffff},
+ {"mcs5ghpo6", 0x000000f0, 0, SROM4_5GH_MCSPO + 6, 0xffff},
+ {"mcs5ghpo7", 0x000000f0, 0, SROM4_5GH_MCSPO + 7, 0xffff},
+ {"mcs2gpo0", 0x00000100, 0, SROM8_2G_MCSPO, 0xffff},
+ {"mcs2gpo1", 0x00000100, 0, SROM8_2G_MCSPO + 1, 0xffff},
+ {"mcs2gpo2", 0x00000100, 0, SROM8_2G_MCSPO + 2, 0xffff},
+ {"mcs2gpo3", 0x00000100, 0, SROM8_2G_MCSPO + 3, 0xffff},
+ {"mcs2gpo4", 0x00000100, 0, SROM8_2G_MCSPO + 4, 0xffff},
+ {"mcs2gpo5", 0x00000100, 0, SROM8_2G_MCSPO + 5, 0xffff},
+ {"mcs2gpo6", 0x00000100, 0, SROM8_2G_MCSPO + 6, 0xffff},
+ {"mcs2gpo7", 0x00000100, 0, SROM8_2G_MCSPO + 7, 0xffff},
+ {"mcs5gpo0", 0x00000100, 0, SROM8_5G_MCSPO, 0xffff},
+ {"mcs5gpo1", 0x00000100, 0, SROM8_5G_MCSPO + 1, 0xffff},
+ {"mcs5gpo2", 0x00000100, 0, SROM8_5G_MCSPO + 2, 0xffff},
+ {"mcs5gpo3", 0x00000100, 0, SROM8_5G_MCSPO + 3, 0xffff},
+ {"mcs5gpo4", 0x00000100, 0, SROM8_5G_MCSPO + 4, 0xffff},
+ {"mcs5gpo5", 0x00000100, 0, SROM8_5G_MCSPO + 5, 0xffff},
+ {"mcs5gpo6", 0x00000100, 0, SROM8_5G_MCSPO + 6, 0xffff},
+ {"mcs5gpo7", 0x00000100, 0, SROM8_5G_MCSPO + 7, 0xffff},
+ {"mcs5glpo0", 0x00000100, 0, SROM8_5GL_MCSPO, 0xffff},
+ {"mcs5glpo1", 0x00000100, 0, SROM8_5GL_MCSPO + 1, 0xffff},
+ {"mcs5glpo2", 0x00000100, 0, SROM8_5GL_MCSPO + 2, 0xffff},
+ {"mcs5glpo3", 0x00000100, 0, SROM8_5GL_MCSPO + 3, 0xffff},
+ {"mcs5glpo4", 0x00000100, 0, SROM8_5GL_MCSPO + 4, 0xffff},
+ {"mcs5glpo5", 0x00000100, 0, SROM8_5GL_MCSPO + 5, 0xffff},
+ {"mcs5glpo6", 0x00000100, 0, SROM8_5GL_MCSPO + 6, 0xffff},
+ {"mcs5glpo7", 0x00000100, 0, SROM8_5GL_MCSPO + 7, 0xffff},
+ {"mcs5ghpo0", 0x00000100, 0, SROM8_5GH_MCSPO, 0xffff},
+ {"mcs5ghpo1", 0x00000100, 0, SROM8_5GH_MCSPO + 1, 0xffff},
+ {"mcs5ghpo2", 0x00000100, 0, SROM8_5GH_MCSPO + 2, 0xffff},
+ {"mcs5ghpo3", 0x00000100, 0, SROM8_5GH_MCSPO + 3, 0xffff},
+ {"mcs5ghpo4", 0x00000100, 0, SROM8_5GH_MCSPO + 4, 0xffff},
+ {"mcs5ghpo5", 0x00000100, 0, SROM8_5GH_MCSPO + 5, 0xffff},
+ {"mcs5ghpo6", 0x00000100, 0, SROM8_5GH_MCSPO + 6, 0xffff},
+ {"mcs5ghpo7", 0x00000100, 0, SROM8_5GH_MCSPO + 7, 0xffff},
+ {"cddpo", 0x000000f0, 0, SROM4_CDDPO, 0xffff},
+ {"stbcpo", 0x000000f0, 0, SROM4_STBCPO, 0xffff},
+ {"bw40po", 0x000000f0, 0, SROM4_BW40PO, 0xffff},
+ {"bwduppo", 0x000000f0, 0, SROM4_BWDUPPO, 0xffff},
+ {"cddpo", 0x00000100, 0, SROM8_CDDPO, 0xffff},
+ {"stbcpo", 0x00000100, 0, SROM8_STBCPO, 0xffff},
+ {"bw40po", 0x00000100, 0, SROM8_BW40PO, 0xffff},
+ {"bwduppo", 0x00000100, 0, SROM8_BWDUPPO, 0xffff},
+
+ /* power per rate from sromrev 9 */
+ {"cckbw202gpo", 0xfffffe00, 0, SROM9_2GPO_CCKBW20, 0xffff},
+ {"cckbw20ul2gpo", 0xfffffe00, 0, SROM9_2GPO_CCKBW20UL, 0xffff},
+ {"legofdmbw202gpo", 0xfffffe00, SRFL_MORE, SROM9_2GPO_LOFDMBW20,
+ 0xffff},
+ {"", 0, 0, SROM9_2GPO_LOFDMBW20 + 1, 0xffff},
+ {"legofdmbw20ul2gpo", 0xfffffe00, SRFL_MORE, SROM9_2GPO_LOFDMBW20UL,
+ 0xffff},
+ {"", 0, 0, SROM9_2GPO_LOFDMBW20UL + 1, 0xffff},
+ {"legofdmbw205glpo", 0xfffffe00, SRFL_MORE, SROM9_5GLPO_LOFDMBW20,
+ 0xffff},
+ {"", 0, 0, SROM9_5GLPO_LOFDMBW20 + 1, 0xffff},
+ {"legofdmbw20ul5glpo", 0xfffffe00, SRFL_MORE, SROM9_5GLPO_LOFDMBW20UL,
+ 0xffff},
+ {"", 0, 0, SROM9_5GLPO_LOFDMBW20UL + 1, 0xffff},
+ {"legofdmbw205gmpo", 0xfffffe00, SRFL_MORE, SROM9_5GMPO_LOFDMBW20,
+ 0xffff},
+ {"", 0, 0, SROM9_5GMPO_LOFDMBW20 + 1, 0xffff},
+ {"legofdmbw20ul5gmpo", 0xfffffe00, SRFL_MORE, SROM9_5GMPO_LOFDMBW20UL,
+ 0xffff},
+ {"", 0, 0, SROM9_5GMPO_LOFDMBW20UL + 1, 0xffff},
+ {"legofdmbw205ghpo", 0xfffffe00, SRFL_MORE, SROM9_5GHPO_LOFDMBW20,
+ 0xffff},
+ {"", 0, 0, SROM9_5GHPO_LOFDMBW20 + 1, 0xffff},
+ {"legofdmbw20ul5ghpo", 0xfffffe00, SRFL_MORE, SROM9_5GHPO_LOFDMBW20UL,
+ 0xffff},
+ {"", 0, 0, SROM9_5GHPO_LOFDMBW20UL + 1, 0xffff},
+ {"mcsbw202gpo", 0xfffffe00, SRFL_MORE, SROM9_2GPO_MCSBW20, 0xffff},
+ {"", 0, 0, SROM9_2GPO_MCSBW20 + 1, 0xffff},
+ {"mcsbw20ul2gpo", 0xfffffe00, SRFL_MORE, SROM9_2GPO_MCSBW20UL, 0xffff},
+ {"", 0, 0, SROM9_2GPO_MCSBW20UL + 1, 0xffff},
+ {"mcsbw402gpo", 0xfffffe00, SRFL_MORE, SROM9_2GPO_MCSBW40, 0xffff},
+ {"", 0, 0, SROM9_2GPO_MCSBW40 + 1, 0xffff},
+ {"mcsbw205glpo", 0xfffffe00, SRFL_MORE, SROM9_5GLPO_MCSBW20, 0xffff},
+ {"", 0, 0, SROM9_5GLPO_MCSBW20 + 1, 0xffff},
+ {"mcsbw20ul5glpo", 0xfffffe00, SRFL_MORE, SROM9_5GLPO_MCSBW20UL,
+ 0xffff},
+ {"", 0, 0, SROM9_5GLPO_MCSBW20UL + 1, 0xffff},
+ {"mcsbw405glpo", 0xfffffe00, SRFL_MORE, SROM9_5GLPO_MCSBW40, 0xffff},
+ {"", 0, 0, SROM9_5GLPO_MCSBW40 + 1, 0xffff},
+ {"mcsbw205gmpo", 0xfffffe00, SRFL_MORE, SROM9_5GMPO_MCSBW20, 0xffff},
+ {"", 0, 0, SROM9_5GMPO_MCSBW20 + 1, 0xffff},
+ {"mcsbw20ul5gmpo", 0xfffffe00, SRFL_MORE, SROM9_5GMPO_MCSBW20UL,
+ 0xffff},
+ {"", 0, 0, SROM9_5GMPO_MCSBW20UL + 1, 0xffff},
+ {"mcsbw405gmpo", 0xfffffe00, SRFL_MORE, SROM9_5GMPO_MCSBW40, 0xffff},
+ {"", 0, 0, SROM9_5GMPO_MCSBW40 + 1, 0xffff},
+ {"mcsbw205ghpo", 0xfffffe00, SRFL_MORE, SROM9_5GHPO_MCSBW20, 0xffff},
+ {"", 0, 0, SROM9_5GHPO_MCSBW20 + 1, 0xffff},
+ {"mcsbw20ul5ghpo", 0xfffffe00, SRFL_MORE, SROM9_5GHPO_MCSBW20UL,
+ 0xffff},
+ {"", 0, 0, SROM9_5GHPO_MCSBW20UL + 1, 0xffff},
+ {"mcsbw405ghpo", 0xfffffe00, SRFL_MORE, SROM9_5GHPO_MCSBW40, 0xffff},
+ {"", 0, 0, SROM9_5GHPO_MCSBW40 + 1, 0xffff},
+ {"mcs32po", 0xfffffe00, 0, SROM9_PO_MCS32, 0xffff},
+ {"legofdm40duppo", 0xfffffe00, 0, SROM9_PO_LOFDM40DUP, 0xffff},
+
+ {NULL, 0, 0, 0, 0}
+};
+
+static const sromvar_t perpath_pci_sromvars[] = {
+ {"maxp2ga", 0x000000f0, 0, SROM4_2G_ITT_MAXP, 0x00ff},
+ {"itt2ga", 0x000000f0, 0, SROM4_2G_ITT_MAXP, 0xff00},
+ {"itt5ga", 0x000000f0, 0, SROM4_5G_ITT_MAXP, 0xff00},
+ {"pa2gw0a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA, 0xffff},
+ {"pa2gw1a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 1, 0xffff},
+ {"pa2gw2a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 2, 0xffff},
+ {"pa2gw3a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 3, 0xffff},
+ {"maxp5ga", 0x000000f0, 0, SROM4_5G_ITT_MAXP, 0x00ff},
+ {"maxp5gha", 0x000000f0, 0, SROM4_5GLH_MAXP, 0x00ff},
+ {"maxp5gla", 0x000000f0, 0, SROM4_5GLH_MAXP, 0xff00},
+ {"pa5gw0a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA, 0xffff},
+ {"pa5gw1a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 1, 0xffff},
+ {"pa5gw2a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 2, 0xffff},
+ {"pa5gw3a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 3, 0xffff},
+ {"pa5glw0a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA, 0xffff},
+ {"pa5glw1a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 1, 0xffff},
+ {"pa5glw2a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 2, 0xffff},
+ {"pa5glw3a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 3, 0xffff},
+ {"pa5ghw0a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA, 0xffff},
+ {"pa5ghw1a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 1, 0xffff},
+ {"pa5ghw2a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 2, 0xffff},
+ {"pa5ghw3a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 3, 0xffff},
+ {"maxp2ga", 0xffffff00, 0, SROM8_2G_ITT_MAXP, 0x00ff},
+ {"itt2ga", 0xffffff00, 0, SROM8_2G_ITT_MAXP, 0xff00},
+ {"itt5ga", 0xffffff00, 0, SROM8_5G_ITT_MAXP, 0xff00},
+ {"pa2gw0a", 0xffffff00, SRFL_PRHEX, SROM8_2G_PA, 0xffff},
+ {"pa2gw1a", 0xffffff00, SRFL_PRHEX, SROM8_2G_PA + 1, 0xffff},
+ {"pa2gw2a", 0xffffff00, SRFL_PRHEX, SROM8_2G_PA + 2, 0xffff},
+ {"maxp5ga", 0xffffff00, 0, SROM8_5G_ITT_MAXP, 0x00ff},
+ {"maxp5gha", 0xffffff00, 0, SROM8_5GLH_MAXP, 0x00ff},
+ {"maxp5gla", 0xffffff00, 0, SROM8_5GLH_MAXP, 0xff00},
+ {"pa5gw0a", 0xffffff00, SRFL_PRHEX, SROM8_5G_PA, 0xffff},
+ {"pa5gw1a", 0xffffff00, SRFL_PRHEX, SROM8_5G_PA + 1, 0xffff},
+ {"pa5gw2a", 0xffffff00, SRFL_PRHEX, SROM8_5G_PA + 2, 0xffff},
+ {"pa5glw0a", 0xffffff00, SRFL_PRHEX, SROM8_5GL_PA, 0xffff},
+ {"pa5glw1a", 0xffffff00, SRFL_PRHEX, SROM8_5GL_PA + 1, 0xffff},
+ {"pa5glw2a", 0xffffff00, SRFL_PRHEX, SROM8_5GL_PA + 2, 0xffff},
+ {"pa5ghw0a", 0xffffff00, SRFL_PRHEX, SROM8_5GH_PA, 0xffff},
+ {"pa5ghw1a", 0xffffff00, SRFL_PRHEX, SROM8_5GH_PA + 1, 0xffff},
+ {"pa5ghw2a", 0xffffff00, SRFL_PRHEX, SROM8_5GH_PA + 2, 0xffff},
+ {NULL, 0, 0, 0, 0}
+};
+
+#if !(defined(PHY_TYPE_N) && defined(PHY_TYPE_LP))
+#define PHY_TYPE_N 4 /* N-Phy value */
+#define PHY_TYPE_LP 5 /* LP-Phy value */
+#endif /* !(defined(PHY_TYPE_N) && defined(PHY_TYPE_LP)) */
+#if !defined(PHY_TYPE_NULL)
+#define PHY_TYPE_NULL 0xf /* Invalid Phy value */
+#endif /* !defined(PHY_TYPE_NULL) */
+
+typedef struct {
+ u16 phy_type;
+ u16 bandrange;
+ u16 chain;
+ const char *vars;
+} pavars_t;
+
+static const pavars_t pavars[] = {
+ /* NPHY */
+ {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_2G, 0, "pa2gw0a0 pa2gw1a0 pa2gw2a0"},
+ {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_2G, 1, "pa2gw0a1 pa2gw1a1 pa2gw2a1"},
+ {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GL, 0,
+ "pa5glw0a0 pa5glw1a0 pa5glw2a0"},
+ {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GL, 1,
+ "pa5glw0a1 pa5glw1a1 pa5glw2a1"},
+ {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GM, 0, "pa5gw0a0 pa5gw1a0 pa5gw2a0"},
+ {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GM, 1, "pa5gw0a1 pa5gw1a1 pa5gw2a1"},
+ {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GH, 0,
+ "pa5ghw0a0 pa5ghw1a0 pa5ghw2a0"},
+ {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GH, 1,
+ "pa5ghw0a1 pa5ghw1a1 pa5ghw2a1"},
+ /* LPPHY */
+ {PHY_TYPE_LP, WL_CHAN_FREQ_RANGE_2G, 0, "pa0b0 pa0b1 pa0b2"},
+ {PHY_TYPE_LP, WL_CHAN_FREQ_RANGE_5GL, 0, "pa1lob0 pa1lob1 pa1lob2"},
+ {PHY_TYPE_LP, WL_CHAN_FREQ_RANGE_5GM, 0, "pa1b0 pa1b1 pa1b2"},
+ {PHY_TYPE_LP, WL_CHAN_FREQ_RANGE_5GH, 0, "pa1hib0 pa1hib1 pa1hib2"},
+ {PHY_TYPE_NULL, 0, 0, ""}
+};
+
+typedef struct {
+ u16 phy_type;
+ u16 bandrange;
+ const char *vars;
+} povars_t;
+
+static const povars_t povars[] = {
+ /* NPHY */
+ {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_2G,
+ "mcs2gpo0 mcs2gpo1 mcs2gpo2 mcs2gpo3 "
+ "mcs2gpo4 mcs2gpo5 mcs2gpo6 mcs2gpo7"},
+ {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GL,
+ "mcs5glpo0 mcs5glpo1 mcs5glpo2 mcs5glpo3 "
+ "mcs5glpo4 mcs5glpo5 mcs5glpo6 mcs5glpo7"},
+ {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GM,
+ "mcs5gpo0 mcs5gpo1 mcs5gpo2 mcs5gpo3 "
+ "mcs5gpo4 mcs5gpo5 mcs5gpo6 mcs5gpo7"},
+ {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GH,
+ "mcs5ghpo0 mcs5ghpo1 mcs5ghpo2 mcs5ghpo3 "
+ "mcs5ghpo4 mcs5ghpo5 mcs5ghpo6 mcs5ghpo7"},
+ {PHY_TYPE_NULL, 0, ""}
+};
+
+typedef struct {
+ u8 tag; /* Broadcom subtag name */
+ u8 len; /* Length field of the tuple, note that it includes the
+ * subtag name (1 byte): 1 + tuple content length
+ */
+ const char *params;
+} cis_tuple_t;
+
+#define OTP_RAW (0xff - 1) /* Reserved tuple number for wrvar Raw input */
+#define OTP_VERS_1 (0xff - 2) /* CISTPL_VERS_1 */
+#define OTP_MANFID (0xff - 3) /* CISTPL_MANFID */
+#define OTP_RAW1 (0xff - 4) /* Like RAW, but comes first */
+
+#endif /* _bcmsrom_tbl_h_ */
diff --git a/drivers/staging/brcm80211/brcmsmac/d11.h b/drivers/staging/brcm80211/brcmsmac/d11.h
index a9d182f..d91e418 100644
--- a/drivers/staging/brcm80211/brcmsmac/d11.h
+++ b/drivers/staging/brcm80211/brcmsmac/d11.h
@@ -17,6 +17,8 @@
#ifndef _D11_H
#define _D11_H
+#include <sbconfig.h>
+
#ifndef WL_RSSI_ANT_MAX
#define WL_RSSI_ANT_MAX 4 /* max possible rx antennas */
#elif WL_RSSI_ANT_MAX != 4
diff --git a/drivers/staging/brcm80211/brcmsmac/hnddma.c b/drivers/staging/brcm80211/brcmsmac/hnddma.c
new file mode 100644
index 0000000..f607315
--- /dev/null
+++ b/drivers/staging/brcm80211/brcmsmac/hnddma.c
@@ -0,0 +1,1756 @@
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/kernel.h>
+#include <linux/string.h>
+#include <linux/netdevice.h>
+#include <linux/pci.h>
+#include <bcmdefs.h>
+#include <bcmdevs.h>
+#include <hndsoc.h>
+#include <bcmutils.h>
+#include <aiutils.h>
+
+#include <sbhnddma.h>
+#include <hnddma.h>
+
+#if defined(__mips__)
+#include <asm/addrspace.h>
+#endif
+
+#ifdef BRCM_FULLMAC
+#error "hnddma.c shouldn't be needed for FULLMAC"
+#endif
+
+/* debug/trace */
+#ifdef BCMDBG
+#define DMA_ERROR(args) \
+ do { \
+ if (!(*di->msg_level & 1)) \
+ ; \
+ else \
+ printk args; \
+ } while (0)
+#define DMA_TRACE(args) \
+ do { \
+ if (!(*di->msg_level & 2)) \
+ ; \
+ else \
+ printk args; \
+ } while (0)
+#else
+#define DMA_ERROR(args)
+#define DMA_TRACE(args)
+#endif /* BCMDBG */
+
+#define DMA_NONE(args)
+
+#define d64txregs dregs.d64_u.txregs_64
+#define d64rxregs dregs.d64_u.rxregs_64
+#define txd64 dregs.d64_u.txd_64
+#define rxd64 dregs.d64_u.rxd_64
+
+/* default dma message level (if input msg_level pointer is null in dma_attach()) */
+static uint dma_msg_level;
+
+#define MAXNAMEL 8 /* 8 char names */
+
+#define DI_INFO(dmah) ((dma_info_t *)dmah)
+
+#define R_SM(r) (*(r))
+#define W_SM(r, v) (*(r) = (v))
+
+/* dma engine software state */
+typedef struct dma_info {
+ struct hnddma_pub hnddma; /* exported structure */
+ uint *msg_level; /* message level pointer */
+ char name[MAXNAMEL]; /* callers name for diag msgs */
+
+ void *pbus; /* bus handle */
+
+ bool dma64; /* this dma engine is operating in 64-bit mode */
+ bool addrext; /* this dma engine supports DmaExtendedAddrChanges */
+
+ union {
+ struct {
+ dma64regs_t *txregs_64; /* 64-bit dma tx engine registers */
+ dma64regs_t *rxregs_64; /* 64-bit dma rx engine registers */
+ dma64dd_t *txd_64; /* pointer to dma64 tx descriptor ring */
+ dma64dd_t *rxd_64; /* pointer to dma64 rx descriptor ring */
+ } d64_u;
+ } dregs;
+
+ u16 dmadesc_align; /* alignment requirement for dma descriptors */
+
+ u16 ntxd; /* # tx descriptors tunable */
+ u16 txin; /* index of next descriptor to reclaim */
+ u16 txout; /* index of next descriptor to post */
+ void **txp; /* pointer to parallel array of pointers to packets */
+ hnddma_seg_map_t *txp_dmah; /* DMA MAP meta-data handle */
+ dmaaddr_t txdpa; /* Aligned physical address of descriptor ring */
+ dmaaddr_t txdpaorig; /* Original physical address of descriptor ring */
+ u16 txdalign; /* #bytes added to alloc'd mem to align txd */
+ u32 txdalloc; /* #bytes allocated for the ring */
+ u32 xmtptrbase; /* When using unaligned descriptors, the ptr register
+ * is not just an index, it needs all 13 bits to be
+ * an offset from the addr register.
+ */
+
+ u16 nrxd; /* # rx descriptors tunable */
+ u16 rxin; /* index of next descriptor to reclaim */
+ u16 rxout; /* index of next descriptor to post */
+ void **rxp; /* pointer to parallel array of pointers to packets */
+ hnddma_seg_map_t *rxp_dmah; /* DMA MAP meta-data handle */
+ dmaaddr_t rxdpa; /* Aligned physical address of descriptor ring */
+ dmaaddr_t rxdpaorig; /* Original physical address of descriptor ring */
+ u16 rxdalign; /* #bytes added to alloc'd mem to align rxd */
+ u32 rxdalloc; /* #bytes allocated for the ring */
+ u32 rcvptrbase; /* Base for ptr reg when using unaligned descriptors */
+
+ /* tunables */
+ unsigned int rxbufsize; /* rx buffer size in bytes,
+ * not including the extra headroom
+ */
+ uint rxextrahdrroom; /* extra rx headroom, reverseved to assist upper stack
+ * e.g. some rx pkt buffers will be bridged to tx side
+ * without byte copying. The extra headroom needs to be
+ * large enough to fit txheader needs.
+ * Some dongle driver may not need it.
+ */
+ uint nrxpost; /* # rx buffers to keep posted */
+ unsigned int rxoffset; /* rxcontrol offset */
+ uint ddoffsetlow; /* add to get dma address of descriptor ring, low 32 bits */
+ uint ddoffsethigh; /* high 32 bits */
+ uint dataoffsetlow; /* add to get dma address of data buffer, low 32 bits */
+ uint dataoffsethigh; /* high 32 bits */
+ bool aligndesc_4k; /* descriptor base need to be aligned or not */
+} dma_info_t;
+
+/* DMA Scatter-gather list is supported. Note this is limited to TX direction only */
+#ifdef BCMDMASGLISTOSL
+#define DMASGLIST_ENAB true
+#else
+#define DMASGLIST_ENAB false
+#endif /* BCMDMASGLISTOSL */
+
+/* descriptor bumping macros */
+#define XXD(x, n) ((x) & ((n) - 1)) /* faster than %, but n must be power of 2 */
+#define TXD(x) XXD((x), di->ntxd)
+#define RXD(x) XXD((x), di->nrxd)
+#define NEXTTXD(i) TXD((i) + 1)
+#define PREVTXD(i) TXD((i) - 1)
+#define NEXTRXD(i) RXD((i) + 1)
+#define PREVRXD(i) RXD((i) - 1)
+
+#define NTXDACTIVE(h, t) TXD((t) - (h))
+#define NRXDACTIVE(h, t) RXD((t) - (h))
+
+/* macros to convert between byte offsets and indexes */
+#define B2I(bytes, type) ((bytes) / sizeof(type))
+#define I2B(index, type) ((index) * sizeof(type))
+
+#define PCI32ADDR_HIGH 0xc0000000 /* address[31:30] */
+#define PCI32ADDR_HIGH_SHIFT 30 /* address[31:30] */
+
+#define PCI64ADDR_HIGH 0x80000000 /* address[63] */
+#define PCI64ADDR_HIGH_SHIFT 31 /* address[63] */
+
+/* Common prototypes */
+static bool _dma_isaddrext(dma_info_t *di);
+static bool _dma_descriptor_align(dma_info_t *di);
+static bool _dma_alloc(dma_info_t *di, uint direction);
+static void _dma_detach(dma_info_t *di);
+static void _dma_ddtable_init(dma_info_t *di, uint direction, dmaaddr_t pa);
+static void _dma_rxinit(dma_info_t *di);
+static void *_dma_rx(dma_info_t *di);
+static bool _dma_rxfill(dma_info_t *di);
+static void _dma_rxreclaim(dma_info_t *di);
+static void _dma_rxenable(dma_info_t *di);
+static void *_dma_getnextrxp(dma_info_t *di, bool forceall);
+static void _dma_rx_param_get(dma_info_t *di, u16 *rxoffset,
+ u16 *rxbufsize);
+
+static void _dma_txblock(dma_info_t *di);
+static void _dma_txunblock(dma_info_t *di);
+static uint _dma_txactive(dma_info_t *di);
+static uint _dma_rxactive(dma_info_t *di);
+static uint _dma_txpending(dma_info_t *di);
+static uint _dma_txcommitted(dma_info_t *di);
+
+static void *_dma_peeknexttxp(dma_info_t *di);
+static void *_dma_peeknextrxp(dma_info_t *di);
+static unsigned long _dma_getvar(dma_info_t *di, const char *name);
+static void _dma_counterreset(dma_info_t *di);
+static void _dma_fifoloopbackenable(dma_info_t *di);
+static uint _dma_ctrlflags(dma_info_t *di, uint mask, uint flags);
+static u8 dma_align_sizetobits(uint size);
+static void *dma_ringalloc(dma_info_t *di, u32 boundary, uint size,
+ u16 *alignbits, uint *alloced,
+ dmaaddr_t *descpa);
+
+/* Prototypes for 64-bit routines */
+static bool dma64_alloc(dma_info_t *di, uint direction);
+static bool dma64_txreset(dma_info_t *di);
+static bool dma64_rxreset(dma_info_t *di);
+static bool dma64_txsuspendedidle(dma_info_t *di);
+static int dma64_txfast(dma_info_t *di, struct sk_buff *p0, bool commit);
+static int dma64_txunframed(dma_info_t *di, void *p0, uint len, bool commit);
+static void *dma64_getpos(dma_info_t *di, bool direction);
+static void *dma64_getnexttxp(dma_info_t *di, txd_range_t range);
+static void *dma64_getnextrxp(dma_info_t *di, bool forceall);
+static void dma64_txrotate(dma_info_t *di);
+
+static bool dma64_rxidle(dma_info_t *di);
+static void dma64_txinit(dma_info_t *di);
+static bool dma64_txenabled(dma_info_t *di);
+static void dma64_txsuspend(dma_info_t *di);
+static void dma64_txresume(dma_info_t *di);
+static bool dma64_txsuspended(dma_info_t *di);
+static void dma64_txreclaim(dma_info_t *di, txd_range_t range);
+static bool dma64_txstopped(dma_info_t *di);
+static bool dma64_rxstopped(dma_info_t *di);
+static bool dma64_rxenabled(dma_info_t *di);
+static bool _dma64_addrext(dma64regs_t *dma64regs);
+
+static inline u32 parity32(u32 data);
+
+const di_fcn_t dma64proc = {
+ (di_detach_t) _dma_detach,
+ (di_txinit_t) dma64_txinit,
+ (di_txreset_t) dma64_txreset,
+ (di_txenabled_t) dma64_txenabled,
+ (di_txsuspend_t) dma64_txsuspend,
+ (di_txresume_t) dma64_txresume,
+ (di_txsuspended_t) dma64_txsuspended,
+ (di_txsuspendedidle_t) dma64_txsuspendedidle,
+ (di_txfast_t) dma64_txfast,
+ (di_txunframed_t) dma64_txunframed,
+ (di_getpos_t) dma64_getpos,
+ (di_txstopped_t) dma64_txstopped,
+ (di_txreclaim_t) dma64_txreclaim,
+ (di_getnexttxp_t) dma64_getnexttxp,
+ (di_peeknexttxp_t) _dma_peeknexttxp,
+ (di_txblock_t) _dma_txblock,
+ (di_txunblock_t) _dma_txunblock,
+ (di_txactive_t) _dma_txactive,
+ (di_txrotate_t) dma64_txrotate,
+
+ (di_rxinit_t) _dma_rxinit,
+ (di_rxreset_t) dma64_rxreset,
+ (di_rxidle_t) dma64_rxidle,
+ (di_rxstopped_t) dma64_rxstopped,
+ (di_rxenable_t) _dma_rxenable,
+ (di_rxenabled_t) dma64_rxenabled,
+ (di_rx_t) _dma_rx,
+ (di_rxfill_t) _dma_rxfill,
+ (di_rxreclaim_t) _dma_rxreclaim,
+ (di_getnextrxp_t) _dma_getnextrxp,
+ (di_peeknextrxp_t) _dma_peeknextrxp,
+ (di_rxparam_get_t) _dma_rx_param_get,
+
+ (di_fifoloopbackenable_t) _dma_fifoloopbackenable,
+ (di_getvar_t) _dma_getvar,
+ (di_counterreset_t) _dma_counterreset,
+ (di_ctrlflags_t) _dma_ctrlflags,
+ NULL,
+ NULL,
+ NULL,
+ (di_rxactive_t) _dma_rxactive,
+ (di_txpending_t) _dma_txpending,
+ (di_txcommitted_t) _dma_txcommitted,
+ 39
+};
+
+struct hnddma_pub *dma_attach(char *name, si_t *sih,
+ void *dmaregstx, void *dmaregsrx, uint ntxd,
+ uint nrxd, uint rxbufsize, int rxextheadroom,
+ uint nrxpost, uint rxoffset, uint *msg_level)
+{
+ dma_info_t *di;
+ uint size;
+
+ /* allocate private info structure */
+ di = kzalloc(sizeof(dma_info_t), GFP_ATOMIC);
+ if (di == NULL) {
+#ifdef BCMDBG
+ printk(KERN_ERR "dma_attach: out of memory\n");
+#endif
+ return NULL;
+ }
+
+ di->msg_level = msg_level ? msg_level : &dma_msg_level;
+
+
+ di->dma64 = ((ai_core_sflags(sih, 0, 0) & SISF_DMA64) == SISF_DMA64);
+
+ /* init dma reg pointer */
+ di->d64txregs = (dma64regs_t *) dmaregstx;
+ di->d64rxregs = (dma64regs_t *) dmaregsrx;
+ di->hnddma.di_fn = (const di_fcn_t *)&dma64proc;
+
+ /* Default flags (which can be changed by the driver calling dma_ctrlflags
+ * before enable): For backwards compatibility both Rx Overflow Continue
+ * and Parity are DISABLED.
+ * supports it.
+ */
+ di->hnddma.di_fn->ctrlflags(&di->hnddma, DMA_CTRL_ROC | DMA_CTRL_PEN,
+ 0);
+
+ DMA_TRACE(("%s: dma_attach: %s flags 0x%x ntxd %d nrxd %d "
+ "rxbufsize %d rxextheadroom %d nrxpost %d rxoffset %d "
+ "dmaregstx %p dmaregsrx %p\n", name, "DMA64",
+ di->hnddma.dmactrlflags, ntxd, nrxd, rxbufsize,
+ rxextheadroom, nrxpost, rxoffset, dmaregstx, dmaregsrx));
+
+ /* make a private copy of our callers name */
+ strncpy(di->name, name, MAXNAMEL);
+ di->name[MAXNAMEL - 1] = '\0';
+
+ di->pbus = ((struct si_info *)sih)->pbus;
+
+ /* save tunables */
+ di->ntxd = (u16) ntxd;
+ di->nrxd = (u16) nrxd;
+
+ /* the actual dma size doesn't include the extra headroom */
+ di->rxextrahdrroom =
+ (rxextheadroom == -1) ? BCMEXTRAHDROOM : rxextheadroom;
+ if (rxbufsize > BCMEXTRAHDROOM)
+ di->rxbufsize = (u16) (rxbufsize - di->rxextrahdrroom);
+ else
+ di->rxbufsize = (u16) rxbufsize;
+
+ di->nrxpost = (u16) nrxpost;
+ di->rxoffset = (u8) rxoffset;
+
+ /*
+ * figure out the DMA physical address offset for dd and data
+ * PCI/PCIE: they map silicon backplace address to zero based memory, need offset
+ * Other bus: use zero
+ * SI_BUS BIGENDIAN kludge: use sdram swapped region for data buffer, not descriptor
+ */
+ di->ddoffsetlow = 0;
+ di->dataoffsetlow = 0;
+ /* for pci bus, add offset */
+ if (sih->bustype == PCI_BUS) {
+ /* pcie with DMA64 */
+ di->ddoffsetlow = 0;
+ di->ddoffsethigh = SI_PCIE_DMA_H32;
+ di->dataoffsetlow = di->ddoffsetlow;
+ di->dataoffsethigh = di->ddoffsethigh;
+ }
+#if defined(__mips__) && defined(IL_BIGENDIAN)
+ di->dataoffsetlow = di->dataoffsetlow + SI_SDRAM_SWAPPED;
+#endif /* defined(__mips__) && defined(IL_BIGENDIAN) */
+ /* WAR64450 : DMACtl.Addr ext fields are not supported in SDIOD core. */
+ if ((ai_coreid(sih) == SDIOD_CORE_ID)
+ && ((ai_corerev(sih) > 0) && (ai_corerev(sih) <= 2)))
+ di->addrext = 0;
+ else if ((ai_coreid(sih) == I2S_CORE_ID) &&
+ ((ai_corerev(sih) == 0) || (ai_corerev(sih) == 1)))
+ di->addrext = 0;
+ else
+ di->addrext = _dma_isaddrext(di);
+
+ /* does the descriptors need to be aligned and if yes, on 4K/8K or not */
+ di->aligndesc_4k = _dma_descriptor_align(di);
+ if (di->aligndesc_4k) {
+ di->dmadesc_align = D64RINGALIGN_BITS;
+ if ((ntxd < D64MAXDD / 2) && (nrxd < D64MAXDD / 2)) {
+ /* for smaller dd table, HW relax alignment reqmnt */
+ di->dmadesc_align = D64RINGALIGN_BITS - 1;
+ }
+ } else
+ di->dmadesc_align = 4; /* 16 byte alignment */
+
+ DMA_NONE(("DMA descriptor align_needed %d, align %d\n",
+ di->aligndesc_4k, di->dmadesc_align));
+
+ /* allocate tx packet pointer vector */
+ if (ntxd) {
+ size = ntxd * sizeof(void *);
+ di->txp = kzalloc(size, GFP_ATOMIC);
+ if (di->txp == NULL) {
+ DMA_ERROR(("%s: dma_attach: out of tx memory\n", di->name));
+ goto fail;
+ }
+ }
+
+ /* allocate rx packet pointer vector */
+ if (nrxd) {
+ size = nrxd * sizeof(void *);
+ di->rxp = kzalloc(size, GFP_ATOMIC);
+ if (di->rxp == NULL) {
+ DMA_ERROR(("%s: dma_attach: out of rx memory\n", di->name));
+ goto fail;
+ }
+ }
+
+ /* allocate transmit descriptor ring, only need ntxd descriptors but it must be aligned */
+ if (ntxd) {
+ if (!_dma_alloc(di, DMA_TX))
+ goto fail;
+ }
+
+ /* allocate receive descriptor ring, only need nrxd descriptors but it must be aligned */
+ if (nrxd) {
+ if (!_dma_alloc(di, DMA_RX))
+ goto fail;
+ }
+
+ if ((di->ddoffsetlow != 0) && !di->addrext) {
+ if (PHYSADDRLO(di->txdpa) > SI_PCI_DMA_SZ) {
+ DMA_ERROR(("%s: dma_attach: txdpa 0x%x: addrext not supported\n", di->name, (u32) PHYSADDRLO(di->txdpa)));
+ goto fail;
+ }
+ if (PHYSADDRLO(di->rxdpa) > SI_PCI_DMA_SZ) {
+ DMA_ERROR(("%s: dma_attach: rxdpa 0x%x: addrext not supported\n", di->name, (u32) PHYSADDRLO(di->rxdpa)));
+ goto fail;
+ }
+ }
+
+ DMA_TRACE(("ddoffsetlow 0x%x ddoffsethigh 0x%x dataoffsetlow 0x%x dataoffsethigh " "0x%x addrext %d\n", di->ddoffsetlow, di->ddoffsethigh, di->dataoffsetlow, di->dataoffsethigh, di->addrext));
+
+ /* allocate DMA mapping vectors */
+ if (DMASGLIST_ENAB) {
+ if (ntxd) {
+ size = ntxd * sizeof(hnddma_seg_map_t);
+ di->txp_dmah = kzalloc(size, GFP_ATOMIC);
+ if (di->txp_dmah == NULL)
+ goto fail;
+ }
+
+ if (nrxd) {
+ size = nrxd * sizeof(hnddma_seg_map_t);
+ di->rxp_dmah = kzalloc(size, GFP_ATOMIC);
+ if (di->rxp_dmah == NULL)
+ goto fail;
+ }
+ }
+
+ return (struct hnddma_pub *) di;
+
+ fail:
+ _dma_detach(di);
+ return NULL;
+}
+
+/* Check for odd number of 1's */
+static inline u32 parity32(u32 data)
+{
+ data ^= data >> 16;
+ data ^= data >> 8;
+ data ^= data >> 4;
+ data ^= data >> 2;
+ data ^= data >> 1;
+
+ return data & 1;
+}
+
+#define DMA64_DD_PARITY(dd) parity32((dd)->addrlow ^ (dd)->addrhigh ^ (dd)->ctrl1 ^ (dd)->ctrl2)
+
+static inline void
+dma64_dd_upd(dma_info_t *di, dma64dd_t *ddring, dmaaddr_t pa, uint outidx,
+ u32 *flags, u32 bufcount)
+{
+ u32 ctrl2 = bufcount & D64_CTRL2_BC_MASK;
+
+ /* PCI bus with big(>1G) physical address, use address extension */
+#if defined(__mips__) && defined(IL_BIGENDIAN)
+ if ((di->dataoffsetlow == SI_SDRAM_SWAPPED)
+ || !(PHYSADDRLO(pa) & PCI32ADDR_HIGH)) {
+#else
+ if ((di->dataoffsetlow == 0) || !(PHYSADDRLO(pa) & PCI32ADDR_HIGH)) {
+#endif /* defined(__mips__) && defined(IL_BIGENDIAN) */
+
+ W_SM(&ddring[outidx].addrlow,
+ BUS_SWAP32(PHYSADDRLO(pa) + di->dataoffsetlow));
+ W_SM(&ddring[outidx].addrhigh,
+ BUS_SWAP32(PHYSADDRHI(pa) + di->dataoffsethigh));
+ W_SM(&ddring[outidx].ctrl1, BUS_SWAP32(*flags));
+ W_SM(&ddring[outidx].ctrl2, BUS_SWAP32(ctrl2));
+ } else {
+ /* address extension for 32-bit PCI */
+ u32 ae;
+
+ ae = (PHYSADDRLO(pa) & PCI32ADDR_HIGH) >> PCI32ADDR_HIGH_SHIFT;
+ PHYSADDRLO(pa) &= ~PCI32ADDR_HIGH;
+
+ ctrl2 |= (ae << D64_CTRL2_AE_SHIFT) & D64_CTRL2_AE;
+ W_SM(&ddring[outidx].addrlow,
+ BUS_SWAP32(PHYSADDRLO(pa) + di->dataoffsetlow));
+ W_SM(&ddring[outidx].addrhigh,
+ BUS_SWAP32(0 + di->dataoffsethigh));
+ W_SM(&ddring[outidx].ctrl1, BUS_SWAP32(*flags));
+ W_SM(&ddring[outidx].ctrl2, BUS_SWAP32(ctrl2));
+ }
+ if (di->hnddma.dmactrlflags & DMA_CTRL_PEN) {
+ if (DMA64_DD_PARITY(&ddring[outidx])) {
+ W_SM(&ddring[outidx].ctrl2,
+ BUS_SWAP32(ctrl2 | D64_CTRL2_PARITY));
+ }
+ }
+}
+
+static bool _dma_alloc(dma_info_t *di, uint direction)
+{
+ return dma64_alloc(di, direction);
+}
+
+void *dma_alloc_consistent(struct pci_dev *pdev, uint size, u16 align_bits,
+ uint *alloced, unsigned long *pap)
+{
+ if (align_bits) {
+ u16 align = (1 << align_bits);
+ if (!IS_ALIGNED(PAGE_SIZE, align))
+ size += align;
+ *alloced = size;
+ }
+ return pci_alloc_consistent(pdev, size, (dma_addr_t *) pap);
+}
+
+/* !! may be called with core in reset */
+static void _dma_detach(dma_info_t *di)
+{
+
+ DMA_TRACE(("%s: dma_detach\n", di->name));
+
+ /* free dma descriptor rings */
+ if (di->txd64)
+ pci_free_consistent(di->pbus, di->txdalloc,
+ ((s8 *)di->txd64 - di->txdalign),
+ (di->txdpaorig));
+ if (di->rxd64)
+ pci_free_consistent(di->pbus, di->rxdalloc,
+ ((s8 *)di->rxd64 - di->rxdalign),
+ (di->rxdpaorig));
+
+ /* free packet pointer vectors */
+ kfree(di->txp);
+ kfree(di->rxp);
+
+ /* free tx packet DMA handles */
+ kfree(di->txp_dmah);
+
+ /* free rx packet DMA handles */
+ kfree(di->rxp_dmah);
+
+ /* free our private info structure */
+ kfree(di);
+
+}
+
+static bool _dma_descriptor_align(dma_info_t *di)
+{
+ u32 addrl;
+
+ /* Check to see if the descriptors need to be aligned on 4K/8K or not */
+ if (di->d64txregs != NULL) {
+ W_REG(&di->d64txregs->addrlow, 0xff0);
+ addrl = R_REG(&di->d64txregs->addrlow);
+ if (addrl != 0)
+ return false;
+ } else if (di->d64rxregs != NULL) {
+ W_REG(&di->d64rxregs->addrlow, 0xff0);
+ addrl = R_REG(&di->d64rxregs->addrlow);
+ if (addrl != 0)
+ return false;
+ }
+ return true;
+}
+
+/* return true if this dma engine supports DmaExtendedAddrChanges, otherwise false */
+static bool _dma_isaddrext(dma_info_t *di)
+{
+ /* DMA64 supports full 32- or 64-bit operation. AE is always valid */
+
+ /* not all tx or rx channel are available */
+ if (di->d64txregs != NULL) {
+ if (!_dma64_addrext(di->d64txregs)) {
+ DMA_ERROR(("%s: _dma_isaddrext: DMA64 tx doesn't have "
+ "AE set\n", di->name));
+ }
+ return true;
+ } else if (di->d64rxregs != NULL) {
+ if (!_dma64_addrext(di->d64rxregs)) {
+ DMA_ERROR(("%s: _dma_isaddrext: DMA64 rx doesn't have "
+ "AE set\n", di->name));
+ }
+ return true;
+ }
+ return false;
+}
+
+/* initialize descriptor table base address */
+static void _dma_ddtable_init(dma_info_t *di, uint direction, dmaaddr_t pa)
+{
+ if (!di->aligndesc_4k) {
+ if (direction == DMA_TX)
+ di->xmtptrbase = PHYSADDRLO(pa);
+ else
+ di->rcvptrbase = PHYSADDRLO(pa);
+ }
+
+ if ((di->ddoffsetlow == 0)
+ || !(PHYSADDRLO(pa) & PCI32ADDR_HIGH)) {
+ if (direction == DMA_TX) {
+ W_REG(&di->d64txregs->addrlow,
+ (PHYSADDRLO(pa) + di->ddoffsetlow));
+ W_REG(&di->d64txregs->addrhigh,
+ (PHYSADDRHI(pa) + di->ddoffsethigh));
+ } else {
+ W_REG(&di->d64rxregs->addrlow,
+ (PHYSADDRLO(pa) + di->ddoffsetlow));
+ W_REG(&di->d64rxregs->addrhigh,
+ (PHYSADDRHI(pa) + di->ddoffsethigh));
+ }
+ } else {
+ /* DMA64 32bits address extension */
+ u32 ae;
+
+ /* shift the high bit(s) from pa to ae */
+ ae = (PHYSADDRLO(pa) & PCI32ADDR_HIGH) >>
+ PCI32ADDR_HIGH_SHIFT;
+ PHYSADDRLO(pa) &= ~PCI32ADDR_HIGH;
+
+ if (direction == DMA_TX) {
+ W_REG(&di->d64txregs->addrlow,
+ (PHYSADDRLO(pa) + di->ddoffsetlow));
+ W_REG(&di->d64txregs->addrhigh,
+ di->ddoffsethigh);
+ SET_REG(&di->d64txregs->control,
+ D64_XC_AE, (ae << D64_XC_AE_SHIFT));
+ } else {
+ W_REG(&di->d64rxregs->addrlow,
+ (PHYSADDRLO(pa) + di->ddoffsetlow));
+ W_REG(&di->d64rxregs->addrhigh,
+ di->ddoffsethigh);
+ SET_REG(&di->d64rxregs->control,
+ D64_RC_AE, (ae << D64_RC_AE_SHIFT));
+ }
+ }
+}
+
+static void _dma_fifoloopbackenable(dma_info_t *di)
+{
+ DMA_TRACE(("%s: dma_fifoloopbackenable\n", di->name));
+
+ OR_REG(&di->d64txregs->control, D64_XC_LE);
+}
+
+static void _dma_rxinit(dma_info_t *di)
+{
+ DMA_TRACE(("%s: dma_rxinit\n", di->name));
+
+ if (di->nrxd == 0)
+ return;
+
+ di->rxin = di->rxout = 0;
+
+ /* clear rx descriptor ring */
+ memset((void *)di->rxd64, '\0',
+ (di->nrxd * sizeof(dma64dd_t)));
+
+ /* DMA engine with out alignment requirement requires table to be inited
+ * before enabling the engine
+ */
+ if (!di->aligndesc_4k)
+ _dma_ddtable_init(di, DMA_RX, di->rxdpa);
+
+ _dma_rxenable(di);
+
+ if (di->aligndesc_4k)
+ _dma_ddtable_init(di, DMA_RX, di->rxdpa);
+}
+
+static void _dma_rxenable(dma_info_t *di)
+{
+ uint dmactrlflags = di->hnddma.dmactrlflags;
+ u32 control;
+
+ DMA_TRACE(("%s: dma_rxenable\n", di->name));
+
+ control =
+ (R_REG(&di->d64rxregs->control) & D64_RC_AE) |
+ D64_RC_RE;
+
+ if ((dmactrlflags & DMA_CTRL_PEN) == 0)
+ control |= D64_RC_PD;
+
+ if (dmactrlflags & DMA_CTRL_ROC)
+ control |= D64_RC_OC;
+
+ W_REG(&di->d64rxregs->control,
+ ((di->rxoffset << D64_RC_RO_SHIFT) | control));
+}
+
+static void
+_dma_rx_param_get(dma_info_t *di, u16 *rxoffset, u16 *rxbufsize)
+{
+ /* the normal values fit into 16 bits */
+ *rxoffset = (u16) di->rxoffset;
+ *rxbufsize = (u16) di->rxbufsize;
+}
+
+/* !! rx entry routine
+ * returns a pointer to the next frame received, or NULL if there are no more
+ * if DMA_CTRL_RXMULTI is defined, DMA scattering(multiple buffers) is supported
+ * with pkts chain
+ * otherwise, it's treated as giant pkt and will be tossed.
+ * The DMA scattering starts with normal DMA header, followed by first buffer data.
+ * After it reaches the max size of buffer, the data continues in next DMA descriptor
+ * buffer WITHOUT DMA header
+ */
+static void *_dma_rx(dma_info_t *di)
+{
+ struct sk_buff *p, *head, *tail;
+ uint len;
+ uint pkt_len;
+ int resid = 0;
+
+ next_frame:
+ head = _dma_getnextrxp(di, false);
+ if (head == NULL)
+ return NULL;
+
+ len = le16_to_cpu(*(u16 *) (head->data));
+ DMA_TRACE(("%s: dma_rx len %d\n", di->name, len));
+ dma_spin_for_len(len, head);
+
+ /* set actual length */
+ pkt_len = min((di->rxoffset + len), di->rxbufsize);
+ __skb_trim(head, pkt_len);
+ resid = len - (di->rxbufsize - di->rxoffset);
+
+ /* check for single or multi-buffer rx */
+ if (resid > 0) {
+ tail = head;
+ while ((resid > 0) && (p = _dma_getnextrxp(di, false))) {
+ tail->next = p;
+ pkt_len = min(resid, (int)di->rxbufsize);
+ __skb_trim(p, pkt_len);
+
+ tail = p;
+ resid -= di->rxbufsize;
+ }
+
+#ifdef BCMDBG
+ if (resid > 0) {
+ uint cur;
+ cur =
+ B2I(((R_REG(&di->d64rxregs->status0) &
+ D64_RS0_CD_MASK) -
+ di->rcvptrbase) & D64_RS0_CD_MASK,
+ dma64dd_t);
+ DMA_ERROR(("_dma_rx, rxin %d rxout %d, hw_curr %d\n",
+ di->rxin, di->rxout, cur));
+ }
+#endif /* BCMDBG */
+
+ if ((di->hnddma.dmactrlflags & DMA_CTRL_RXMULTI) == 0) {
+ DMA_ERROR(("%s: dma_rx: bad frame length (%d)\n",
+ di->name, len));
+ bcm_pkt_buf_free_skb(head);
+ di->hnddma.rxgiants++;
+ goto next_frame;
+ }
+ }
+
+ return head;
+}
+
+/* post receive buffers
+ * return false is refill failed completely and ring is empty
+ * this will stall the rx dma and user might want to call rxfill again asap
+ * This unlikely happens on memory-rich NIC, but often on memory-constrained dongle
+ */
+static bool _dma_rxfill(dma_info_t *di)
+{
+ struct sk_buff *p;
+ u16 rxin, rxout;
+ u32 flags = 0;
+ uint n;
+ uint i;
+ dmaaddr_t pa;
+ uint extra_offset = 0;
+ bool ring_empty;
+
+ ring_empty = false;
+
+ /*
+ * Determine how many receive buffers we're lacking
+ * from the full complement, allocate, initialize,
+ * and post them, then update the chip rx lastdscr.
+ */
+
+ rxin = di->rxin;
+ rxout = di->rxout;
+
+ n = di->nrxpost - NRXDACTIVE(rxin, rxout);
+
+ DMA_TRACE(("%s: dma_rxfill: post %d\n", di->name, n));
+
+ if (di->rxbufsize > BCMEXTRAHDROOM)
+ extra_offset = di->rxextrahdrroom;
+
+ for (i = 0; i < n; i++) {
+ /* the di->rxbufsize doesn't include the extra headroom, we need to add it to the
+ size to be allocated
+ */
+
+ p = bcm_pkt_buf_get_skb(di->rxbufsize + extra_offset);
+
+ if (p == NULL) {
+ DMA_ERROR(("%s: dma_rxfill: out of rxbufs\n",
+ di->name));
+ if (i == 0 && dma64_rxidle(di)) {
+ DMA_ERROR(("%s: rxfill64: ring is empty !\n",
+ di->name));
+ ring_empty = true;
+ }
+ di->hnddma.rxnobuf++;
+ break;
+ }
+ /* reserve an extra headroom, if applicable */
+ if (extra_offset)
+ skb_pull(p, extra_offset);
+
+ /* Do a cached write instead of uncached write since DMA_MAP
+ * will flush the cache.
+ */
+ *(u32 *) (p->data) = 0;
+
+ if (DMASGLIST_ENAB)
+ memset(&di->rxp_dmah[rxout], 0,
+ sizeof(hnddma_seg_map_t));
+
+ pa = pci_map_single(di->pbus, p->data,
+ di->rxbufsize, PCI_DMA_FROMDEVICE);
+
+ /* save the free packet pointer */
+ di->rxp[rxout] = p;
+
+ /* reset flags for each descriptor */
+ flags = 0;
+ if (rxout == (di->nrxd - 1))
+ flags = D64_CTRL1_EOT;
+
+ dma64_dd_upd(di, di->rxd64, pa, rxout, &flags,
+ di->rxbufsize);
+ rxout = NEXTRXD(rxout);
+ }
+
+ di->rxout = rxout;
+
+ /* update the chip lastdscr pointer */
+ W_REG(&di->d64rxregs->ptr,
+ di->rcvptrbase + I2B(rxout, dma64dd_t));
+
+ return ring_empty;
+}
+
+/* like getnexttxp but no reclaim */
+static void *_dma_peeknexttxp(dma_info_t *di)
+{
+ uint end, i;
+
+ if (di->ntxd == 0)
+ return NULL;
+
+ end =
+ B2I(((R_REG(&di->d64txregs->status0) &
+ D64_XS0_CD_MASK) - di->xmtptrbase) & D64_XS0_CD_MASK,
+ dma64dd_t);
+
+ for (i = di->txin; i != end; i = NEXTTXD(i))
+ if (di->txp[i])
+ return di->txp[i];
+
+ return NULL;
+}
+
+/* like getnextrxp but not take off the ring */
+static void *_dma_peeknextrxp(dma_info_t *di)
+{
+ uint end, i;
+
+ if (di->nrxd == 0)
+ return NULL;
+
+ end =
+ B2I(((R_REG(&di->d64rxregs->status0) &
+ D64_RS0_CD_MASK) - di->rcvptrbase) & D64_RS0_CD_MASK,
+ dma64dd_t);
+
+ for (i = di->rxin; i != end; i = NEXTRXD(i))
+ if (di->rxp[i])
+ return di->rxp[i];
+
+ return NULL;
+}
+
+static void _dma_rxreclaim(dma_info_t *di)
+{
+ void *p;
+
+ DMA_TRACE(("%s: dma_rxreclaim\n", di->name));
+
+ while ((p = _dma_getnextrxp(di, true)))
+ bcm_pkt_buf_free_skb(p);
+}
+
+static void *_dma_getnextrxp(dma_info_t *di, bool forceall)
+{
+ if (di->nrxd == 0)
+ return NULL;
+
+ return dma64_getnextrxp(di, forceall);
+}
+
+static void _dma_txblock(dma_info_t *di)
+{
+ di->hnddma.txavail = 0;
+}
+
+static void _dma_txunblock(dma_info_t *di)
+{
+ di->hnddma.txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
+}
+
+static uint _dma_txactive(dma_info_t *di)
+{
+ return NTXDACTIVE(di->txin, di->txout);
+}
+
+static uint _dma_txpending(dma_info_t *di)
+{
+ uint curr;
+
+ curr =
+ B2I(((R_REG(&di->d64txregs->status0) &
+ D64_XS0_CD_MASK) - di->xmtptrbase) & D64_XS0_CD_MASK,
+ dma64dd_t);
+
+ return NTXDACTIVE(curr, di->txout);
+}
+
+static uint _dma_txcommitted(dma_info_t *di)
+{
+ uint ptr;
+ uint txin = di->txin;
+
+ if (txin == di->txout)
+ return 0;
+
+ ptr = B2I(R_REG(&di->d64txregs->ptr), dma64dd_t);
+
+ return NTXDACTIVE(di->txin, ptr);
+}
+
+static uint _dma_rxactive(dma_info_t *di)
+{
+ return NRXDACTIVE(di->rxin, di->rxout);
+}
+
+static void _dma_counterreset(dma_info_t *di)
+{
+ /* reset all software counter */
+ di->hnddma.rxgiants = 0;
+ di->hnddma.rxnobuf = 0;
+ di->hnddma.txnobuf = 0;
+}
+
+static uint _dma_ctrlflags(dma_info_t *di, uint mask, uint flags)
+{
+ uint dmactrlflags = di->hnddma.dmactrlflags;
+
+ if (di == NULL) {
+ DMA_ERROR(("%s: _dma_ctrlflags: NULL dma handle\n", di->name));
+ return 0;
+ }
+
+ dmactrlflags &= ~mask;
+ dmactrlflags |= flags;
+
+ /* If trying to enable parity, check if parity is actually supported */
+ if (dmactrlflags & DMA_CTRL_PEN) {
+ u32 control;
+
+ control = R_REG(&di->d64txregs->control);
+ W_REG(&di->d64txregs->control,
+ control | D64_XC_PD);
+ if (R_REG(&di->d64txregs->control) & D64_XC_PD) {
+ /* We *can* disable it so it is supported,
+ * restore control register
+ */
+ W_REG(&di->d64txregs->control,
+ control);
+ } else {
+ /* Not supported, don't allow it to be enabled */
+ dmactrlflags &= ~DMA_CTRL_PEN;
+ }
+ }
+
+ di->hnddma.dmactrlflags = dmactrlflags;
+
+ return dmactrlflags;
+}
+
+/* get the address of the var in order to change later */
+static unsigned long _dma_getvar(dma_info_t *di, const char *name)
+{
+ if (!strcmp(name, "&txavail"))
+ return (unsigned long)&(di->hnddma.txavail);
+ return 0;
+}
+
+static
+u8 dma_align_sizetobits(uint size)
+{
+ u8 bitpos = 0;
+ while (size >>= 1) {
+ bitpos++;
+ }
+ return bitpos;
+}
+
+/* This function ensures that the DMA descriptor ring will not get allocated
+ * across Page boundary. If the allocation is done across the page boundary
+ * at the first time, then it is freed and the allocation is done at
+ * descriptor ring size aligned location. This will ensure that the ring will
+ * not cross page boundary
+ */
+static void *dma_ringalloc(dma_info_t *di, u32 boundary, uint size,
+ u16 *alignbits, uint *alloced,
+ dmaaddr_t *descpa)
+{
+ void *va;
+ u32 desc_strtaddr;
+ u32 alignbytes = 1 << *alignbits;
+
+ va = dma_alloc_consistent(di->pbus, size, *alignbits, alloced, descpa);
+
+ if (NULL == va)
+ return NULL;
+
+ desc_strtaddr = (u32) roundup((unsigned long)va, alignbytes);
+ if (((desc_strtaddr + size - 1) & boundary) != (desc_strtaddr
+ & boundary)) {
+ *alignbits = dma_align_sizetobits(size);
+ pci_free_consistent(di->pbus, size, va, *descpa);
+ va = dma_alloc_consistent(di->pbus, size, *alignbits,
+ alloced, descpa);
+ }
+ return va;
+}
+
+/* 64-bit DMA functions */
+
+static void dma64_txinit(dma_info_t *di)
+{
+ u32 control = D64_XC_XE;
+
+ DMA_TRACE(("%s: dma_txinit\n", di->name));
+
+ if (di->ntxd == 0)
+ return;
+
+ di->txin = di->txout = 0;
+ di->hnddma.txavail = di->ntxd - 1;
+
+ /* clear tx descriptor ring */
+ memset((void *)di->txd64, '\0', (di->ntxd * sizeof(dma64dd_t)));
+
+ /* DMA engine with out alignment requirement requires table to be inited
+ * before enabling the engine
+ */
+ if (!di->aligndesc_4k)
+ _dma_ddtable_init(di, DMA_TX, di->txdpa);
+
+ if ((di->hnddma.dmactrlflags & DMA_CTRL_PEN) == 0)
+ control |= D64_XC_PD;
+ OR_REG(&di->d64txregs->control, control);
+
+ /* DMA engine with alignment requirement requires table to be inited
+ * before enabling the engine
+ */
+ if (di->aligndesc_4k)
+ _dma_ddtable_init(di, DMA_TX, di->txdpa);
+}
+
+static bool dma64_txenabled(dma_info_t *di)
+{
+ u32 xc;
+
+ /* If the chip is dead, it is not enabled :-) */
+ xc = R_REG(&di->d64txregs->control);
+ return (xc != 0xffffffff) && (xc & D64_XC_XE);
+}
+
+static void dma64_txsuspend(dma_info_t *di)
+{
+ DMA_TRACE(("%s: dma_txsuspend\n", di->name));
+
+ if (di->ntxd == 0)
+ return;
+
+ OR_REG(&di->d64txregs->control, D64_XC_SE);
+}
+
+static void dma64_txresume(dma_info_t *di)
+{
+ DMA_TRACE(("%s: dma_txresume\n", di->name));
+
+ if (di->ntxd == 0)
+ return;
+
+ AND_REG(&di->d64txregs->control, ~D64_XC_SE);
+}
+
+static bool dma64_txsuspended(dma_info_t *di)
+{
+ return (di->ntxd == 0) ||
+ ((R_REG(&di->d64txregs->control) & D64_XC_SE) ==
+ D64_XC_SE);
+}
+
+static void dma64_txreclaim(dma_info_t *di, txd_range_t range)
+{
+ void *p;
+
+ DMA_TRACE(("%s: dma_txreclaim %s\n", di->name,
+ (range == HNDDMA_RANGE_ALL) ? "all" :
+ ((range ==
+ HNDDMA_RANGE_TRANSMITTED) ? "transmitted" :
+ "transferred")));
+
+ if (di->txin == di->txout)
+ return;
+
+ while ((p = dma64_getnexttxp(di, range))) {
+ /* For unframed data, we don't have any packets to free */
+ if (!(di->hnddma.dmactrlflags & DMA_CTRL_UNFRAMED))
+ bcm_pkt_buf_free_skb(p);
+ }
+}
+
+static bool dma64_txstopped(dma_info_t *di)
+{
+ return ((R_REG(&di->d64txregs->status0) & D64_XS0_XS_MASK) ==
+ D64_XS0_XS_STOPPED);
+}
+
+static bool dma64_rxstopped(dma_info_t *di)
+{
+ return ((R_REG(&di->d64rxregs->status0) & D64_RS0_RS_MASK) ==
+ D64_RS0_RS_STOPPED);
+}
+
+static bool dma64_alloc(dma_info_t *di, uint direction)
+{
+ u16 size;
+ uint ddlen;
+ void *va;
+ uint alloced = 0;
+ u16 align;
+ u16 align_bits;
+
+ ddlen = sizeof(dma64dd_t);
+
+ size = (direction == DMA_TX) ? (di->ntxd * ddlen) : (di->nrxd * ddlen);
+ align_bits = di->dmadesc_align;
+ align = (1 << align_bits);
+
+ if (direction == DMA_TX) {
+ va = dma_ringalloc(di, D64RINGALIGN, size, &align_bits,
+ &alloced, &di->txdpaorig);
+ if (va == NULL) {
+ DMA_ERROR(("%s: dma64_alloc: DMA_ALLOC_CONSISTENT(ntxd) failed\n", di->name));
+ return false;
+ }
+ align = (1 << align_bits);
+ di->txd64 = (dma64dd_t *) roundup((unsigned long)va, align);
+ di->txdalign = (uint) ((s8 *)di->txd64 - (s8 *) va);
+ PHYSADDRLOSET(di->txdpa,
+ PHYSADDRLO(di->txdpaorig) + di->txdalign);
+ PHYSADDRHISET(di->txdpa, PHYSADDRHI(di->txdpaorig));
+ di->txdalloc = alloced;
+ } else {
+ va = dma_ringalloc(di, D64RINGALIGN, size, &align_bits,
+ &alloced, &di->rxdpaorig);
+ if (va == NULL) {
+ DMA_ERROR(("%s: dma64_alloc: DMA_ALLOC_CONSISTENT(nrxd) failed\n", di->name));
+ return false;
+ }
+ align = (1 << align_bits);
+ di->rxd64 = (dma64dd_t *) roundup((unsigned long)va, align);
+ di->rxdalign = (uint) ((s8 *)di->rxd64 - (s8 *) va);
+ PHYSADDRLOSET(di->rxdpa,
+ PHYSADDRLO(di->rxdpaorig) + di->rxdalign);
+ PHYSADDRHISET(di->rxdpa, PHYSADDRHI(di->rxdpaorig));
+ di->rxdalloc = alloced;
+ }
+
+ return true;
+}
+
+static bool dma64_txreset(dma_info_t *di)
+{
+ u32 status;
+
+ if (di->ntxd == 0)
+ return true;
+
+ /* suspend tx DMA first */
+ W_REG(&di->d64txregs->control, D64_XC_SE);
+ SPINWAIT(((status =
+ (R_REG(&di->d64txregs->status0) & D64_XS0_XS_MASK))
+ != D64_XS0_XS_DISABLED) && (status != D64_XS0_XS_IDLE)
+ && (status != D64_XS0_XS_STOPPED), 10000);
+
+ W_REG(&di->d64txregs->control, 0);
+ SPINWAIT(((status =
+ (R_REG(&di->d64txregs->status0) & D64_XS0_XS_MASK))
+ != D64_XS0_XS_DISABLED), 10000);
+
+ /* wait for the last transaction to complete */
+ udelay(300);
+
+ return status == D64_XS0_XS_DISABLED;
+}
+
+static bool dma64_rxidle(dma_info_t *di)
+{
+ DMA_TRACE(("%s: dma_rxidle\n", di->name));
+
+ if (di->nrxd == 0)
+ return true;
+
+ return ((R_REG(&di->d64rxregs->status0) & D64_RS0_CD_MASK) ==
+ (R_REG(&di->d64rxregs->ptr) & D64_RS0_CD_MASK));
+}
+
+static bool dma64_rxreset(dma_info_t *di)
+{
+ u32 status;
+
+ if (di->nrxd == 0)
+ return true;
+
+ W_REG(&di->d64rxregs->control, 0);
+ SPINWAIT(((status =
+ (R_REG(&di->d64rxregs->status0) & D64_RS0_RS_MASK))
+ != D64_RS0_RS_DISABLED), 10000);
+
+ return status == D64_RS0_RS_DISABLED;
+}
+
+static bool dma64_rxenabled(dma_info_t *di)
+{
+ u32 rc;
+
+ rc = R_REG(&di->d64rxregs->control);
+ return (rc != 0xffffffff) && (rc & D64_RC_RE);
+}
+
+static bool dma64_txsuspendedidle(dma_info_t *di)
+{
+
+ if (di->ntxd == 0)
+ return true;
+
+ if (!(R_REG(&di->d64txregs->control) & D64_XC_SE))
+ return 0;
+
+ if ((R_REG(&di->d64txregs->status0) & D64_XS0_XS_MASK) ==
+ D64_XS0_XS_IDLE)
+ return 1;
+
+ return 0;
+}
+
+/* Useful when sending unframed data. This allows us to get a progress report from the DMA.
+ * We return a pointer to the beginning of the DATA buffer of the current descriptor.
+ * If DMA is idle, we return NULL.
+ */
+static void *dma64_getpos(dma_info_t *di, bool direction)
+{
+ void *va;
+ bool idle;
+ u32 cd_offset;
+
+ if (direction == DMA_TX) {
+ cd_offset =
+ R_REG(&di->d64txregs->status0) & D64_XS0_CD_MASK;
+ idle = !NTXDACTIVE(di->txin, di->txout);
+ va = di->txp[B2I(cd_offset, dma64dd_t)];
+ } else {
+ cd_offset =
+ R_REG(&di->d64rxregs->status0) & D64_XS0_CD_MASK;
+ idle = !NRXDACTIVE(di->rxin, di->rxout);
+ va = di->rxp[B2I(cd_offset, dma64dd_t)];
+ }
+
+ /* If DMA is IDLE, return NULL */
+ if (idle) {
+ DMA_TRACE(("%s: DMA idle, return NULL\n", __func__));
+ va = NULL;
+ }
+
+ return va;
+}
+
+/* TX of unframed data
+ *
+ * Adds a DMA ring descriptor for the data pointed to by "buf".
+ * This is for DMA of a buffer of data and is unlike other hnddma TX functions
+ * that take a pointer to a "packet"
+ * Each call to this is results in a single descriptor being added for "len" bytes of
+ * data starting at "buf", it doesn't handle chained buffers.
+ */
+static int dma64_txunframed(dma_info_t *di, void *buf, uint len, bool commit)
+{
+ u16 txout;
+ u32 flags = 0;
+ dmaaddr_t pa; /* phys addr */
+
+ txout = di->txout;
+
+ /* return nonzero if out of tx descriptors */
+ if (NEXTTXD(txout) == di->txin)
+ goto outoftxd;
+
+ if (len == 0)
+ return 0;
+
+ pa = pci_map_single(di->pbus, buf, len, PCI_DMA_TODEVICE);
+
+ flags = (D64_CTRL1_SOF | D64_CTRL1_IOC | D64_CTRL1_EOF);
+
+ if (txout == (di->ntxd - 1))
+ flags |= D64_CTRL1_EOT;
+
+ dma64_dd_upd(di, di->txd64, pa, txout, &flags, len);
+
+ /* save the buffer pointer - used by dma_getpos */
+ di->txp[txout] = buf;
+
+ txout = NEXTTXD(txout);
+ /* bump the tx descriptor index */
+ di->txout = txout;
+
+ /* kick the chip */
+ if (commit) {
+ W_REG(&di->d64txregs->ptr,
+ di->xmtptrbase + I2B(txout, dma64dd_t));
+ }
+
+ /* tx flow control */
+ di->hnddma.txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
+
+ return 0;
+
+ outoftxd:
+ DMA_ERROR(("%s: %s: out of txds !!!\n", di->name, __func__));
+ di->hnddma.txavail = 0;
+ di->hnddma.txnobuf++;
+ return -1;
+}
+
+/* !! tx entry routine
+ * WARNING: call must check the return value for error.
+ * the error(toss frames) could be fatal and cause many subsequent hard to debug problems
+ */
+static int dma64_txfast(dma_info_t *di, struct sk_buff *p0,
+ bool commit)
+{
+ struct sk_buff *p, *next;
+ unsigned char *data;
+ uint len;
+ u16 txout;
+ u32 flags = 0;
+ dmaaddr_t pa;
+
+ DMA_TRACE(("%s: dma_txfast\n", di->name));
+
+ txout = di->txout;
+
+ /*
+ * Walk the chain of packet buffers
+ * allocating and initializing transmit descriptor entries.
+ */
+ for (p = p0; p; p = next) {
+ uint nsegs, j;
+ hnddma_seg_map_t *map;
+
+ data = p->data;
+ len = p->len;
+ next = p->next;
+
+ /* return nonzero if out of tx descriptors */
+ if (NEXTTXD(txout) == di->txin)
+ goto outoftxd;
+
+ if (len == 0)
+ continue;
+
+ /* get physical address of buffer start */
+ if (DMASGLIST_ENAB)
+ memset(&di->txp_dmah[txout], 0,
+ sizeof(hnddma_seg_map_t));
+
+ pa = pci_map_single(di->pbus, data, len, PCI_DMA_TODEVICE);
+
+ if (DMASGLIST_ENAB) {
+ map = &di->txp_dmah[txout];
+
+ /* See if all the segments can be accounted for */
+ if (map->nsegs >
+ (uint) (di->ntxd - NTXDACTIVE(di->txin, di->txout) -
+ 1))
+ goto outoftxd;
+
+ nsegs = map->nsegs;
+ } else
+ nsegs = 1;
+
+ for (j = 1; j <= nsegs; j++) {
+ flags = 0;
+ if (p == p0 && j == 1)
+ flags |= D64_CTRL1_SOF;
+
+ /* With a DMA segment list, Descriptor table is filled
+ * using the segment list instead of looping over
+ * buffers in multi-chain DMA. Therefore, EOF for SGLIST is when
+ * end of segment list is reached.
+ */
+ if ((!DMASGLIST_ENAB && next == NULL) ||
+ (DMASGLIST_ENAB && j == nsegs))
+ flags |= (D64_CTRL1_IOC | D64_CTRL1_EOF);
+ if (txout == (di->ntxd - 1))
+ flags |= D64_CTRL1_EOT;
+
+ if (DMASGLIST_ENAB) {
+ len = map->segs[j - 1].length;
+ pa = map->segs[j - 1].addr;
+ }
+ dma64_dd_upd(di, di->txd64, pa, txout, &flags, len);
+
+ txout = NEXTTXD(txout);
+ }
+
+ /* See above. No need to loop over individual buffers */
+ if (DMASGLIST_ENAB)
+ break;
+ }
+
+ /* if last txd eof not set, fix it */
+ if (!(flags & D64_CTRL1_EOF))
+ W_SM(&di->txd64[PREVTXD(txout)].ctrl1,
+ BUS_SWAP32(flags | D64_CTRL1_IOC | D64_CTRL1_EOF));
+
+ /* save the packet */
+ di->txp[PREVTXD(txout)] = p0;
+
+ /* bump the tx descriptor index */
+ di->txout = txout;
+
+ /* kick the chip */
+ if (commit)
+ W_REG(&di->d64txregs->ptr,
+ di->xmtptrbase + I2B(txout, dma64dd_t));
+
+ /* tx flow control */
+ di->hnddma.txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
+
+ return 0;
+
+ outoftxd:
+ DMA_ERROR(("%s: dma_txfast: out of txds !!!\n", di->name));
+ bcm_pkt_buf_free_skb(p0);
+ di->hnddma.txavail = 0;
+ di->hnddma.txnobuf++;
+ return -1;
+}
+
+/*
+ * Reclaim next completed txd (txds if using chained buffers) in the range
+ * specified and return associated packet.
+ * If range is HNDDMA_RANGE_TRANSMITTED, reclaim descriptors that have be
+ * transmitted as noted by the hardware "CurrDescr" pointer.
+ * If range is HNDDMA_RANGE_TRANSFERED, reclaim descriptors that have be
+ * transferred by the DMA as noted by the hardware "ActiveDescr" pointer.
+ * If range is HNDDMA_RANGE_ALL, reclaim all txd(s) posted to the ring and
+ * return associated packet regardless of the value of hardware pointers.
+ */
+static void *dma64_getnexttxp(dma_info_t *di, txd_range_t range)
+{
+ u16 start, end, i;
+ u16 active_desc;
+ void *txp;
+
+ DMA_TRACE(("%s: dma_getnexttxp %s\n", di->name,
+ (range == HNDDMA_RANGE_ALL) ? "all" :
+ ((range ==
+ HNDDMA_RANGE_TRANSMITTED) ? "transmitted" :
+ "transferred")));
+
+ if (di->ntxd == 0)
+ return NULL;
+
+ txp = NULL;
+
+ start = di->txin;
+ if (range == HNDDMA_RANGE_ALL)
+ end = di->txout;
+ else {
+ dma64regs_t *dregs = di->d64txregs;
+
+ end =
+ (u16) (B2I
+ (((R_REG(&dregs->status0) &
+ D64_XS0_CD_MASK) -
+ di->xmtptrbase) & D64_XS0_CD_MASK, dma64dd_t));
+
+ if (range == HNDDMA_RANGE_TRANSFERED) {
+ active_desc =
+ (u16) (R_REG(&dregs->status1) &
+ D64_XS1_AD_MASK);
+ active_desc =
+ (active_desc - di->xmtptrbase) & D64_XS0_CD_MASK;
+ active_desc = B2I(active_desc, dma64dd_t);
+ if (end != active_desc)
+ end = PREVTXD(active_desc);
+ }
+ }
+
+ if ((start == 0) && (end > di->txout))
+ goto bogus;
+
+ for (i = start; i != end && !txp; i = NEXTTXD(i)) {
+ dmaaddr_t pa;
+ hnddma_seg_map_t *map = NULL;
+ uint size, j, nsegs;
+
+ PHYSADDRLOSET(pa,
+ (BUS_SWAP32(R_SM(&di->txd64[i].addrlow)) -
+ di->dataoffsetlow));
+ PHYSADDRHISET(pa,
+ (BUS_SWAP32(R_SM(&di->txd64[i].addrhigh)) -
+ di->dataoffsethigh));
+
+ if (DMASGLIST_ENAB) {
+ map = &di->txp_dmah[i];
+ size = map->origsize;
+ nsegs = map->nsegs;
+ } else {
+ size =
+ (BUS_SWAP32(R_SM(&di->txd64[i].ctrl2)) &
+ D64_CTRL2_BC_MASK);
+ nsegs = 1;
+ }
+
+ for (j = nsegs; j > 0; j--) {
+ W_SM(&di->txd64[i].addrlow, 0xdeadbeef);
+ W_SM(&di->txd64[i].addrhigh, 0xdeadbeef);
+
+ txp = di->txp[i];
+ di->txp[i] = NULL;
+ if (j > 1)
+ i = NEXTTXD(i);
+ }
+
+ pci_unmap_single(di->pbus, pa, size, PCI_DMA_TODEVICE);
+ }
+
+ di->txin = i;
+
+ /* tx flow control */
+ di->hnddma.txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
+
+ return txp;
+
+ bogus:
+ DMA_NONE(("dma_getnexttxp: bogus curr: start %d end %d txout %d force %d\n", start, end, di->txout, forceall));
+ return NULL;
+}
+
+static void *dma64_getnextrxp(dma_info_t *di, bool forceall)
+{
+ uint i, curr;
+ void *rxp;
+ dmaaddr_t pa;
+
+ i = di->rxin;
+
+ /* return if no packets posted */
+ if (i == di->rxout)
+ return NULL;
+
+ curr =
+ B2I(((R_REG(&di->d64rxregs->status0) & D64_RS0_CD_MASK) -
+ di->rcvptrbase) & D64_RS0_CD_MASK, dma64dd_t);
+
+ /* ignore curr if forceall */
+ if (!forceall && (i == curr))
+ return NULL;
+
+ /* get the packet pointer that corresponds to the rx descriptor */
+ rxp = di->rxp[i];
+ di->rxp[i] = NULL;
+
+ PHYSADDRLOSET(pa,
+ (BUS_SWAP32(R_SM(&di->rxd64[i].addrlow)) -
+ di->dataoffsetlow));
+ PHYSADDRHISET(pa,
+ (BUS_SWAP32(R_SM(&di->rxd64[i].addrhigh)) -
+ di->dataoffsethigh));
+
+ /* clear this packet from the descriptor ring */
+ pci_unmap_single(di->pbus, pa, di->rxbufsize, PCI_DMA_FROMDEVICE);
+
+ W_SM(&di->rxd64[i].addrlow, 0xdeadbeef);
+ W_SM(&di->rxd64[i].addrhigh, 0xdeadbeef);
+
+ di->rxin = NEXTRXD(i);
+
+ return rxp;
+}
+
+static bool _dma64_addrext(dma64regs_t *dma64regs)
+{
+ u32 w;
+ OR_REG(&dma64regs->control, D64_XC_AE);
+ w = R_REG(&dma64regs->control);
+ AND_REG(&dma64regs->control, ~D64_XC_AE);
+ return (w & D64_XC_AE) == D64_XC_AE;
+}
+
+/*
+ * Rotate all active tx dma ring entries "forward" by (ActiveDescriptor - txin).
+ */
+static void dma64_txrotate(dma_info_t *di)
+{
+ u16 ad;
+ uint nactive;
+ uint rot;
+ u16 old, new;
+ u32 w;
+ u16 first, last;
+
+ nactive = _dma_txactive(di);
+ ad = (u16) (B2I
+ ((((R_REG(&di->d64txregs->status1) &
+ D64_XS1_AD_MASK)
+ - di->xmtptrbase) & D64_XS1_AD_MASK), dma64dd_t));
+ rot = TXD(ad - di->txin);
+
+ /* full-ring case is a lot harder - don't worry about this */
+ if (rot >= (di->ntxd - nactive)) {
+ DMA_ERROR(("%s: dma_txrotate: ring full - punt\n", di->name));
+ return;
+ }
+
+ first = di->txin;
+ last = PREVTXD(di->txout);
+
+ /* move entries starting at last and moving backwards to first */
+ for (old = last; old != PREVTXD(first); old = PREVTXD(old)) {
+ new = TXD(old + rot);
+
+ /*
+ * Move the tx dma descriptor.
+ * EOT is set only in the last entry in the ring.
+ */
+ w = BUS_SWAP32(R_SM(&di->txd64[old].ctrl1)) & ~D64_CTRL1_EOT;
+ if (new == (di->ntxd - 1))
+ w |= D64_CTRL1_EOT;
+ W_SM(&di->txd64[new].ctrl1, BUS_SWAP32(w));
+
+ w = BUS_SWAP32(R_SM(&di->txd64[old].ctrl2));
+ W_SM(&di->txd64[new].ctrl2, BUS_SWAP32(w));
+
+ W_SM(&di->txd64[new].addrlow, R_SM(&di->txd64[old].addrlow));
+ W_SM(&di->txd64[new].addrhigh, R_SM(&di->txd64[old].addrhigh));
+
+ /* zap the old tx dma descriptor address field */
+ W_SM(&di->txd64[old].addrlow, BUS_SWAP32(0xdeadbeef));
+ W_SM(&di->txd64[old].addrhigh, BUS_SWAP32(0xdeadbeef));
+
+ /* move the corresponding txp[] entry */
+ di->txp[new] = di->txp[old];
+
+ /* Move the map */
+ if (DMASGLIST_ENAB) {
+ memcpy(&di->txp_dmah[new], &di->txp_dmah[old],
+ sizeof(hnddma_seg_map_t));
+ memset(&di->txp_dmah[old], 0, sizeof(hnddma_seg_map_t));
+ }
+
+ di->txp[old] = NULL;
+ }
+
+ /* update txin and txout */
+ di->txin = ad;
+ di->txout = TXD(di->txout + rot);
+ di->hnddma.txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
+
+ /* kick the chip */
+ W_REG(&di->d64txregs->ptr,
+ di->xmtptrbase + I2B(di->txout, dma64dd_t));
+}
+
+uint dma_addrwidth(si_t *sih, void *dmaregs)
+{
+ /* Perform 64-bit checks only if we want to advertise 64-bit (> 32bit) capability) */
+ /* DMA engine is 64-bit capable */
+ if ((ai_core_sflags(sih, 0, 0) & SISF_DMA64) == SISF_DMA64) {
+ /* backplane are 64-bit capable */
+ if (ai_backplane64(sih))
+ /* If bus is System Backplane or PCIE then we can access 64-bits */
+ if ((sih->bustype == SI_BUS) ||
+ ((sih->bustype == PCI_BUS) &&
+ (sih->buscoretype == PCIE_CORE_ID)))
+ return DMADDRWIDTH_64;
+ }
+ /* DMA hardware not supported by this driver*/
+ return DMADDRWIDTH_64;
+}
+
+/*
+ * Mac80211 initiated actions sometimes require packets in the DMA queue to be
+ * modified. The modified portion of the packet is not under control of the DMA
+ * engine. This function calls a caller-supplied function for each packet in
+ * the caller specified dma chain.
+ */
+void dma_walk_packets(struct hnddma_pub *dmah, void (*callback_fnc)
+ (void *pkt, void *arg_a), void *arg_a)
+{
+ dma_info_t *di = (dma_info_t *) dmah;
+ uint i = di->txin;
+ uint end = di->txout;
+ struct sk_buff *skb;
+ struct ieee80211_tx_info *tx_info;
+
+ while (i != end) {
+ skb = (struct sk_buff *)di->txp[i];
+ if (skb != NULL) {
+ tx_info = (struct ieee80211_tx_info *)skb->cb;
+ (callback_fnc)(tx_info, arg_a);
+ }
+ i = NEXTTXD(i);
+ }
+}
diff --git a/drivers/staging/brcm80211/brcmsmac/nicpci.c b/drivers/staging/brcm80211/brcmsmac/nicpci.c
new file mode 100644
index 0000000..18b844a
--- /dev/null
+++ b/drivers/staging/brcm80211/brcmsmac/nicpci.c
@@ -0,0 +1,836 @@
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/delay.h>
+#include <linux/string.h>
+#include <linux/pci.h>
+#include <bcmdefs.h>
+#include <bcmutils.h>
+#include <bcmnvram.h>
+#include <aiutils.h>
+#include <hndsoc.h>
+#include <bcmdevs.h>
+#include <sbchipc.h>
+#include <pci_core.h>
+#include <pcie_core.h>
+#include <nicpci.h>
+#include <pcicfg.h>
+
+typedef struct {
+ union {
+ sbpcieregs_t *pcieregs;
+ struct sbpciregs *pciregs;
+ } regs; /* Memory mapped register to the core */
+
+ si_t *sih; /* System interconnect handle */
+ struct pci_dev *dev;
+ u8 pciecap_lcreg_offset; /* PCIE capability LCreg offset in the config space */
+ bool pcie_pr42767;
+ u8 pcie_polarity;
+ u8 pcie_war_aspm_ovr; /* Override ASPM/Clkreq settings */
+
+ u8 pmecap_offset; /* PM Capability offset in the config space */
+ bool pmecap; /* Capable of generating PME */
+} pcicore_info_t;
+
+/* debug/trace */
+#define PCI_ERROR(args)
+#define PCIE_PUB(sih) \
+ (((sih)->bustype == PCI_BUS) && ((sih)->buscoretype == PCIE_CORE_ID))
+
+/* routines to access mdio slave device registers */
+static bool pcie_mdiosetblock(pcicore_info_t *pi, uint blk);
+static int pcie_mdioop(pcicore_info_t *pi, uint physmedia, uint regaddr,
+ bool write, uint *val);
+static int pcie_mdiowrite(pcicore_info_t *pi, uint physmedia, uint readdr,
+ uint val);
+static int pcie_mdioread(pcicore_info_t *pi, uint physmedia, uint readdr,
+ uint *ret_val);
+
+static void pcie_extendL1timer(pcicore_info_t *pi, bool extend);
+static void pcie_clkreq_upd(pcicore_info_t *pi, uint state);
+
+static void pcie_war_aspm_clkreq(pcicore_info_t *pi);
+static void pcie_war_serdes(pcicore_info_t *pi);
+static void pcie_war_noplldown(pcicore_info_t *pi);
+static void pcie_war_polarity(pcicore_info_t *pi);
+static void pcie_war_pci_setup(pcicore_info_t *pi);
+
+static bool pcicore_pmecap(pcicore_info_t *pi);
+
+#define PCIE_ASPM(sih) ((PCIE_PUB(sih)) && (((sih)->buscorerev >= 3) && ((sih)->buscorerev <= 5)))
+
+
+/* delay needed between the mdio control/ mdiodata register data access */
+#define PR28829_DELAY() udelay(10)
+
+/* Initialize the PCI core. It's caller's responsibility to make sure that this is done
+ * only once
+ */
+void *pcicore_init(si_t *sih, void *pdev, void *regs)
+{
+ pcicore_info_t *pi;
+
+ /* alloc pcicore_info_t */
+ pi = kzalloc(sizeof(pcicore_info_t), GFP_ATOMIC);
+ if (pi == NULL) {
+ PCI_ERROR(("pci_attach: malloc failed!\n"));
+ return NULL;
+ }
+
+ pi->sih = sih;
+ pi->dev = pdev;
+
+ if (sih->buscoretype == PCIE_CORE_ID) {
+ u8 cap_ptr;
+ pi->regs.pcieregs = (sbpcieregs_t *) regs;
+ cap_ptr = pcicore_find_pci_capability(pi->dev, PCI_CAP_ID_EXP,
+ NULL, NULL);
+ pi->pciecap_lcreg_offset = cap_ptr + PCIE_CAP_LINKCTRL_OFFSET;
+ } else
+ pi->regs.pciregs = (struct sbpciregs *) regs;
+
+ return pi;
+}
+
+void pcicore_deinit(void *pch)
+{
+ pcicore_info_t *pi = (pcicore_info_t *) pch;
+
+ if (pi == NULL)
+ return;
+ kfree(pi);
+}
+
+/* return cap_offset if requested capability exists in the PCI config space */
+/* Note that it's caller's responsibility to make sure it's a pci bus */
+u8
+pcicore_find_pci_capability(void *dev, u8 req_cap_id,
+ unsigned char *buf, u32 *buflen)
+{
+ u8 cap_id;
+ u8 cap_ptr = 0;
+ u32 bufsize;
+ u8 byte_val;
+
+ /* check for Header type 0 */
+ pci_read_config_byte(dev, PCI_HEADER_TYPE, &byte_val);
+ if ((byte_val & 0x7f) != PCI_HEADER_TYPE_NORMAL)
+ goto end;
+
+ /* check if the capability pointer field exists */
+ pci_read_config_byte(dev, PCI_STATUS, &byte_val);
+ if (!(byte_val & PCI_STATUS_CAP_LIST))
+ goto end;
+
+ pci_read_config_byte(dev, PCI_CAPABILITY_LIST, &cap_ptr);
+ /* check if the capability pointer is 0x00 */
+ if (cap_ptr == 0x00)
+ goto end;
+
+ /* loop thr'u the capability list and see if the pcie capabilty exists */
+
+ pci_read_config_byte(dev, cap_ptr, &cap_id);
+
+ while (cap_id != req_cap_id) {
+ pci_read_config_byte(dev, cap_ptr + 1, &cap_ptr);
+ if (cap_ptr == 0x00)
+ break;
+ pci_read_config_byte(dev, cap_ptr, &cap_id);
+ }
+ if (cap_id != req_cap_id) {
+ goto end;
+ }
+ /* found the caller requested capability */
+ if ((buf != NULL) && (buflen != NULL)) {
+ u8 cap_data;
+
+ bufsize = *buflen;
+ if (!bufsize)
+ goto end;
+ *buflen = 0;
+ /* copy the cpability data excluding cap ID and next ptr */
+ cap_data = cap_ptr + 2;
+ if ((bufsize + cap_data) > PCI_SZPCR)
+ bufsize = PCI_SZPCR - cap_data;
+ *buflen = bufsize;
+ while (bufsize--) {
+ pci_read_config_byte(dev, cap_data, buf);
+ cap_data++;
+ buf++;
+ }
+ }
+ end:
+ return cap_ptr;
+}
+
+/* ***** Register Access API */
+uint
+pcie_readreg(sbpcieregs_t *pcieregs, uint addrtype,
+ uint offset)
+{
+ uint retval = 0xFFFFFFFF;
+
+ switch (addrtype) {
+ case PCIE_CONFIGREGS:
+ W_REG((&pcieregs->configaddr), offset);
+ (void)R_REG((&pcieregs->configaddr));
+ retval = R_REG(&(pcieregs->configdata));
+ break;
+ case PCIE_PCIEREGS:
+ W_REG(&(pcieregs->pcieindaddr), offset);
+ (void)R_REG((&pcieregs->pcieindaddr));
+ retval = R_REG(&(pcieregs->pcieinddata));
+ break;
+ default:
+ break;
+ }
+
+ return retval;
+}
+
+uint
+pcie_writereg(sbpcieregs_t *pcieregs, uint addrtype,
+ uint offset, uint val)
+{
+ switch (addrtype) {
+ case PCIE_CONFIGREGS:
+ W_REG((&pcieregs->configaddr), offset);
+ W_REG((&pcieregs->configdata), val);
+ break;
+ case PCIE_PCIEREGS:
+ W_REG((&pcieregs->pcieindaddr), offset);
+ W_REG((&pcieregs->pcieinddata), val);
+ break;
+ default:
+ break;
+ }
+ return 0;
+}
+
+static bool pcie_mdiosetblock(pcicore_info_t *pi, uint blk)
+{
+ sbpcieregs_t *pcieregs = pi->regs.pcieregs;
+ uint mdiodata, i = 0;
+ uint pcie_serdes_spinwait = 200;
+
+ mdiodata =
+ MDIODATA_START | MDIODATA_WRITE | (MDIODATA_DEV_ADDR <<
+ MDIODATA_DEVADDR_SHF) |
+ (MDIODATA_BLK_ADDR << MDIODATA_REGADDR_SHF) | MDIODATA_TA | (blk <<
+ 4);
+ W_REG(&pcieregs->mdiodata, mdiodata);
+
+ PR28829_DELAY();
+ /* retry till the transaction is complete */
+ while (i < pcie_serdes_spinwait) {
+ if (R_REG(&(pcieregs->mdiocontrol)) &
+ MDIOCTL_ACCESS_DONE) {
+ break;
+ }
+ udelay(1000);
+ i++;
+ }
+
+ if (i >= pcie_serdes_spinwait) {
+ PCI_ERROR(("pcie_mdiosetblock: timed out\n"));
+ return false;
+ }
+
+ return true;
+}
+
+static int
+pcie_mdioop(pcicore_info_t *pi, uint physmedia, uint regaddr, bool write,
+ uint *val)
+{
+ sbpcieregs_t *pcieregs = pi->regs.pcieregs;
+ uint mdiodata;
+ uint i = 0;
+ uint pcie_serdes_spinwait = 10;
+
+ /* enable mdio access to SERDES */
+ W_REG((&pcieregs->mdiocontrol),
+ MDIOCTL_PREAM_EN | MDIOCTL_DIVISOR_VAL);
+
+ if (pi->sih->buscorerev >= 10) {
+ /* new serdes is slower in rw, using two layers of reg address mapping */
+ if (!pcie_mdiosetblock(pi, physmedia))
+ return 1;
+ mdiodata = (MDIODATA_DEV_ADDR << MDIODATA_DEVADDR_SHF) |
+ (regaddr << MDIODATA_REGADDR_SHF);
+ pcie_serdes_spinwait *= 20;
+ } else {
+ mdiodata = (physmedia << MDIODATA_DEVADDR_SHF_OLD) |
+ (regaddr << MDIODATA_REGADDR_SHF_OLD);
+ }
+
+ if (!write)
+ mdiodata |= (MDIODATA_START | MDIODATA_READ | MDIODATA_TA);
+ else
+ mdiodata |=
+ (MDIODATA_START | MDIODATA_WRITE | MDIODATA_TA | *val);
+
+ W_REG(&pcieregs->mdiodata, mdiodata);
+
+ PR28829_DELAY();
+
+ /* retry till the transaction is complete */
+ while (i < pcie_serdes_spinwait) {
+ if (R_REG(&(pcieregs->mdiocontrol)) &
+ MDIOCTL_ACCESS_DONE) {
+ if (!write) {
+ PR28829_DELAY();
+ *val =
+ (R_REG(&(pcieregs->mdiodata)) &
+ MDIODATA_MASK);
+ }
+ /* Disable mdio access to SERDES */
+ W_REG((&pcieregs->mdiocontrol), 0);
+ return 0;
+ }
+ udelay(1000);
+ i++;
+ }
+
+ PCI_ERROR(("pcie_mdioop: timed out op: %d\n", write));
+ /* Disable mdio access to SERDES */
+ W_REG((&pcieregs->mdiocontrol), 0);
+ return 1;
+}
+
+/* use the mdio interface to read from mdio slaves */
+static int
+pcie_mdioread(pcicore_info_t *pi, uint physmedia, uint regaddr, uint *regval)
+{
+ return pcie_mdioop(pi, physmedia, regaddr, false, regval);
+}
+
+/* use the mdio interface to write to mdio slaves */
+static int
+pcie_mdiowrite(pcicore_info_t *pi, uint physmedia, uint regaddr, uint val)
+{
+ return pcie_mdioop(pi, physmedia, regaddr, true, &val);
+}
+
+/* ***** Support functions ***** */
+u8 pcie_clkreq(void *pch, u32 mask, u32 val)
+{
+ pcicore_info_t *pi = (pcicore_info_t *) pch;
+ u32 reg_val;
+ u8 offset;
+
+ offset = pi->pciecap_lcreg_offset;
+ if (!offset)
+ return 0;
+
+ pci_read_config_dword(pi->dev, offset, ®_val);
+ /* set operation */
+ if (mask) {
+ if (val)
+ reg_val |= PCIE_CLKREQ_ENAB;
+ else
+ reg_val &= ~PCIE_CLKREQ_ENAB;
+ pci_write_config_dword(pi->dev, offset, reg_val);
+ pci_read_config_dword(pi->dev, offset, ®_val);
+ }
+ if (reg_val & PCIE_CLKREQ_ENAB)
+ return 1;
+ else
+ return 0;
+}
+
+static void pcie_extendL1timer(pcicore_info_t *pi, bool extend)
+{
+ u32 w;
+ si_t *sih = pi->sih;
+ sbpcieregs_t *pcieregs = pi->regs.pcieregs;
+
+ if (!PCIE_PUB(sih) || sih->buscorerev < 7)
+ return;
+
+ w = pcie_readreg(pcieregs, PCIE_PCIEREGS, PCIE_DLLP_PMTHRESHREG);
+ if (extend)
+ w |= PCIE_ASPMTIMER_EXTEND;
+ else
+ w &= ~PCIE_ASPMTIMER_EXTEND;
+ pcie_writereg(pcieregs, PCIE_PCIEREGS, PCIE_DLLP_PMTHRESHREG, w);
+ w = pcie_readreg(pcieregs, PCIE_PCIEREGS, PCIE_DLLP_PMTHRESHREG);
+}
+
+/* centralized clkreq control policy */
+static void pcie_clkreq_upd(pcicore_info_t *pi, uint state)
+{
+ si_t *sih = pi->sih;
+
+ switch (state) {
+ case SI_DOATTACH:
+ if (PCIE_ASPM(sih))
+ pcie_clkreq((void *)pi, 1, 0);
+ break;
+ case SI_PCIDOWN:
+ if (sih->buscorerev == 6) { /* turn on serdes PLL down */
+ ai_corereg(sih, SI_CC_IDX,
+ offsetof(chipcregs_t, chipcontrol_addr), ~0,
+ 0);
+ ai_corereg(sih, SI_CC_IDX,
+ offsetof(chipcregs_t, chipcontrol_data),
+ ~0x40, 0);
+ } else if (pi->pcie_pr42767) {
+ pcie_clkreq((void *)pi, 1, 1);
+ }
+ break;
+ case SI_PCIUP:
+ if (sih->buscorerev == 6) { /* turn off serdes PLL down */
+ ai_corereg(sih, SI_CC_IDX,
+ offsetof(chipcregs_t, chipcontrol_addr), ~0,
+ 0);
+ ai_corereg(sih, SI_CC_IDX,
+ offsetof(chipcregs_t, chipcontrol_data),
+ ~0x40, 0x40);
+ } else if (PCIE_ASPM(sih)) { /* disable clkreq */
+ pcie_clkreq((void *)pi, 1, 0);
+ }
+ break;
+ default:
+ break;
+ }
+}
+
+/* ***** PCI core WARs ***** */
+/* Done only once at attach time */
+static void pcie_war_polarity(pcicore_info_t *pi)
+{
+ u32 w;
+
+ if (pi->pcie_polarity != 0)
+ return;
+
+ w = pcie_readreg(pi->regs.pcieregs, PCIE_PCIEREGS,
+ PCIE_PLP_STATUSREG);
+
+ /* Detect the current polarity at attach and force that polarity and
+ * disable changing the polarity
+ */
+ if ((w & PCIE_PLP_POLARITYINV_STAT) == 0)
+ pi->pcie_polarity = (SERDES_RX_CTRL_FORCE);
+ else
+ pi->pcie_polarity =
+ (SERDES_RX_CTRL_FORCE | SERDES_RX_CTRL_POLARITY);
+}
+
+/* enable ASPM and CLKREQ if srom doesn't have it */
+/* Needs to happen when update to shadow SROM is needed
+ * : Coming out of 'standby'/'hibernate'
+ * : If pcie_war_aspm_ovr state changed
+ */
+static void pcie_war_aspm_clkreq(pcicore_info_t *pi)
+{
+ sbpcieregs_t *pcieregs = pi->regs.pcieregs;
+ si_t *sih = pi->sih;
+ u16 val16, *reg16;
+ u32 w;
+
+ if (!PCIE_ASPM(sih))
+ return;
+
+ /* bypass this on QT or VSIM */
+ if (!ISSIM_ENAB(sih)) {
+
+ reg16 = &pcieregs->sprom[SRSH_ASPM_OFFSET];
+ val16 = R_REG(reg16);
+
+ val16 &= ~SRSH_ASPM_ENB;
+ if (pi->pcie_war_aspm_ovr == PCIE_ASPM_ENAB)
+ val16 |= SRSH_ASPM_ENB;
+ else if (pi->pcie_war_aspm_ovr == PCIE_ASPM_L1_ENAB)
+ val16 |= SRSH_ASPM_L1_ENB;
+ else if (pi->pcie_war_aspm_ovr == PCIE_ASPM_L0s_ENAB)
+ val16 |= SRSH_ASPM_L0s_ENB;
+
+ W_REG(reg16, val16);
+
+ pci_read_config_dword(pi->dev, pi->pciecap_lcreg_offset,
+ &w);
+ w &= ~PCIE_ASPM_ENAB;
+ w |= pi->pcie_war_aspm_ovr;
+ pci_write_config_dword(pi->dev,
+ pi->pciecap_lcreg_offset, w);
+ }
+
+ reg16 = &pcieregs->sprom[SRSH_CLKREQ_OFFSET_REV5];
+ val16 = R_REG(reg16);
+
+ if (pi->pcie_war_aspm_ovr != PCIE_ASPM_DISAB) {
+ val16 |= SRSH_CLKREQ_ENB;
+ pi->pcie_pr42767 = true;
+ } else
+ val16 &= ~SRSH_CLKREQ_ENB;
+
+ W_REG(reg16, val16);
+}
+
+/* Apply the polarity determined at the start */
+/* Needs to happen when coming out of 'standby'/'hibernate' */
+static void pcie_war_serdes(pcicore_info_t *pi)
+{
+ u32 w = 0;
+
+ if (pi->pcie_polarity != 0)
+ pcie_mdiowrite(pi, MDIODATA_DEV_RX, SERDES_RX_CTRL,
+ pi->pcie_polarity);
+
+ pcie_mdioread(pi, MDIODATA_DEV_PLL, SERDES_PLL_CTRL, &w);
+ if (w & PLL_CTRL_FREQDET_EN) {
+ w &= ~PLL_CTRL_FREQDET_EN;
+ pcie_mdiowrite(pi, MDIODATA_DEV_PLL, SERDES_PLL_CTRL, w);
+ }
+}
+
+/* Fix MISC config to allow coming out of L2/L3-Ready state w/o PRST */
+/* Needs to happen when coming out of 'standby'/'hibernate' */
+static void pcie_misc_config_fixup(pcicore_info_t *pi)
+{
+ sbpcieregs_t *pcieregs = pi->regs.pcieregs;
+ u16 val16, *reg16;
+
+ reg16 = &pcieregs->sprom[SRSH_PCIE_MISC_CONFIG];
+ val16 = R_REG(reg16);
+
+ if ((val16 & SRSH_L23READY_EXIT_NOPERST) == 0) {
+ val16 |= SRSH_L23READY_EXIT_NOPERST;
+ W_REG(reg16, val16);
+ }
+}
+
+/* quick hack for testing */
+/* Needs to happen when coming out of 'standby'/'hibernate' */
+static void pcie_war_noplldown(pcicore_info_t *pi)
+{
+ sbpcieregs_t *pcieregs = pi->regs.pcieregs;
+ u16 *reg16;
+
+ /* turn off serdes PLL down */
+ ai_corereg(pi->sih, SI_CC_IDX, offsetof(chipcregs_t, chipcontrol),
+ CHIPCTRL_4321_PLL_DOWN, CHIPCTRL_4321_PLL_DOWN);
+
+ /* clear srom shadow backdoor */
+ reg16 = &pcieregs->sprom[SRSH_BD_OFFSET];
+ W_REG(reg16, 0);
+}
+
+/* Needs to happen when coming out of 'standby'/'hibernate' */
+static void pcie_war_pci_setup(pcicore_info_t *pi)
+{
+ si_t *sih = pi->sih;
+ sbpcieregs_t *pcieregs = pi->regs.pcieregs;
+ u32 w;
+
+ if ((sih->buscorerev == 0) || (sih->buscorerev == 1)) {
+ w = pcie_readreg(pcieregs, PCIE_PCIEREGS,
+ PCIE_TLP_WORKAROUNDSREG);
+ w |= 0x8;
+ pcie_writereg(pcieregs, PCIE_PCIEREGS,
+ PCIE_TLP_WORKAROUNDSREG, w);
+ }
+
+ if (sih->buscorerev == 1) {
+ w = pcie_readreg(pcieregs, PCIE_PCIEREGS, PCIE_DLLP_LCREG);
+ w |= (0x40);
+ pcie_writereg(pcieregs, PCIE_PCIEREGS, PCIE_DLLP_LCREG, w);
+ }
+
+ if (sih->buscorerev == 0) {
+ pcie_mdiowrite(pi, MDIODATA_DEV_RX, SERDES_RX_TIMER1, 0x8128);
+ pcie_mdiowrite(pi, MDIODATA_DEV_RX, SERDES_RX_CDR, 0x0100);
+ pcie_mdiowrite(pi, MDIODATA_DEV_RX, SERDES_RX_CDRBW, 0x1466);
+ } else if (PCIE_ASPM(sih)) {
+ /* Change the L1 threshold for better performance */
+ w = pcie_readreg(pcieregs, PCIE_PCIEREGS,
+ PCIE_DLLP_PMTHRESHREG);
+ w &= ~(PCIE_L1THRESHOLDTIME_MASK);
+ w |= (PCIE_L1THRESHOLD_WARVAL << PCIE_L1THRESHOLDTIME_SHIFT);
+ pcie_writereg(pcieregs, PCIE_PCIEREGS,
+ PCIE_DLLP_PMTHRESHREG, w);
+
+ pcie_war_serdes(pi);
+
+ pcie_war_aspm_clkreq(pi);
+ } else if (pi->sih->buscorerev == 7)
+ pcie_war_noplldown(pi);
+
+ /* Note that the fix is actually in the SROM, that's why this is open-ended */
+ if (pi->sih->buscorerev >= 6)
+ pcie_misc_config_fixup(pi);
+}
+
+void pcie_war_ovr_aspm_update(void *pch, u8 aspm)
+{
+ pcicore_info_t *pi = (pcicore_info_t *) pch;
+
+ if (!PCIE_ASPM(pi->sih))
+ return;
+
+ /* Validate */
+ if (aspm > PCIE_ASPM_ENAB)
+ return;
+
+ pi->pcie_war_aspm_ovr = aspm;
+
+ /* Update the current state */
+ pcie_war_aspm_clkreq(pi);
+}
+
+/* ***** Functions called during driver state changes ***** */
+void pcicore_attach(void *pch, char *pvars, int state)
+{
+ pcicore_info_t *pi = (pcicore_info_t *) pch;
+ si_t *sih = pi->sih;
+
+ /* Determine if this board needs override */
+ if (PCIE_ASPM(sih)) {
+ if ((u32) getintvar(pvars, "boardflags2") & BFL2_PCIEWAR_OVR) {
+ pi->pcie_war_aspm_ovr = PCIE_ASPM_DISAB;
+ } else {
+ pi->pcie_war_aspm_ovr = PCIE_ASPM_ENAB;
+ }
+ }
+
+ /* These need to happen in this order only */
+ pcie_war_polarity(pi);
+
+ pcie_war_serdes(pi);
+
+ pcie_war_aspm_clkreq(pi);
+
+ pcie_clkreq_upd(pi, state);
+
+}
+
+void pcicore_hwup(void *pch)
+{
+ pcicore_info_t *pi = (pcicore_info_t *) pch;
+
+ if (!pi || !PCIE_PUB(pi->sih))
+ return;
+
+ pcie_war_pci_setup(pi);
+}
+
+void pcicore_up(void *pch, int state)
+{
+ pcicore_info_t *pi = (pcicore_info_t *) pch;
+
+ if (!pi || !PCIE_PUB(pi->sih))
+ return;
+
+ /* Restore L1 timer for better performance */
+ pcie_extendL1timer(pi, true);
+
+ pcie_clkreq_upd(pi, state);
+}
+
+/* When the device is going to enter D3 state (or the system is going to enter S3/S4 states */
+void pcicore_sleep(void *pch)
+{
+ pcicore_info_t *pi = (pcicore_info_t *) pch;
+ u32 w;
+
+ if (!pi || !PCIE_ASPM(pi->sih))
+ return;
+
+ pci_read_config_dword(pi->dev, pi->pciecap_lcreg_offset, &w);
+ w &= ~PCIE_CAP_LCREG_ASPML1;
+ pci_write_config_dword(pi->dev, pi->pciecap_lcreg_offset, w);
+
+ pi->pcie_pr42767 = false;
+}
+
+void pcicore_down(void *pch, int state)
+{
+ pcicore_info_t *pi = (pcicore_info_t *) pch;
+
+ if (!pi || !PCIE_PUB(pi->sih))
+ return;
+
+ pcie_clkreq_upd(pi, state);
+
+ /* Reduce L1 timer for better power savings */
+ pcie_extendL1timer(pi, false);
+}
+
+/* ***** Wake-on-wireless-LAN (WOWL) support functions ***** */
+/* Just uses PCI config accesses to find out, when needed before sb_attach is done */
+bool pcicore_pmecap_fast(void *pch)
+{
+ pcicore_info_t *pi = (pcicore_info_t *) pch;
+ u8 cap_ptr;
+ u32 pmecap;
+
+ cap_ptr = pcicore_find_pci_capability(pi->dev, PCI_CAP_ID_PM, NULL,
+ NULL);
+
+ if (!cap_ptr)
+ return false;
+
+ pci_read_config_dword(pi->dev, cap_ptr, &pmecap);
+
+ return (pmecap & (PCI_PM_CAP_PME_MASK << 16)) != 0;
+}
+
+/* return true if PM capability exists in the pci config space
+ * Uses and caches the information using core handle
+ */
+static bool pcicore_pmecap(pcicore_info_t *pi)
+{
+ u8 cap_ptr;
+ u32 pmecap;
+
+ if (!pi->pmecap_offset) {
+ cap_ptr = pcicore_find_pci_capability(pi->dev,
+ PCI_CAP_ID_PM,
+ NULL, NULL);
+ if (!cap_ptr)
+ return false;
+
+ pi->pmecap_offset = cap_ptr;
+
+ pci_read_config_dword(pi->dev, pi->pmecap_offset,
+ &pmecap);
+
+ /* At least one state can generate PME */
+ pi->pmecap = (pmecap & (PCI_PM_CAP_PME_MASK << 16)) != 0;
+ }
+
+ return pi->pmecap;
+}
+
+/* Enable PME generation */
+void pcicore_pmeen(void *pch)
+{
+ pcicore_info_t *pi = (pcicore_info_t *) pch;
+ u32 w;
+
+ /* if not pmecapable return */
+ if (!pcicore_pmecap(pi))
+ return;
+
+ pci_read_config_dword(pi->dev, pi->pmecap_offset + PCI_PM_CTRL,
+ &w);
+ w |= (PCI_PM_CTRL_PME_ENABLE);
+ pci_write_config_dword(pi->dev,
+ pi->pmecap_offset + PCI_PM_CTRL, w);
+}
+
+/*
+ * Return true if PME status set
+ */
+bool pcicore_pmestat(void *pch)
+{
+ pcicore_info_t *pi = (pcicore_info_t *) pch;
+ u32 w;
+
+ if (!pcicore_pmecap(pi))
+ return false;
+
+ pci_read_config_dword(pi->dev, pi->pmecap_offset + PCI_PM_CTRL,
+ &w);
+
+ return (w & PCI_PM_CTRL_PME_STATUS) == PCI_PM_CTRL_PME_STATUS;
+}
+
+/* Disable PME generation, clear the PME status bit if set
+ */
+void pcicore_pmeclr(void *pch)
+{
+ pcicore_info_t *pi = (pcicore_info_t *) pch;
+ u32 w;
+
+ if (!pcicore_pmecap(pi))
+ return;
+
+ pci_read_config_dword(pi->dev, pi->pmecap_offset + PCI_PM_CTRL,
+ &w);
+
+ PCI_ERROR(("pcicore_pci_pmeclr PMECSR : 0x%x\n", w));
+
+ /* PMESTAT is cleared by writing 1 to it */
+ w &= ~(PCI_PM_CTRL_PME_ENABLE);
+
+ pci_write_config_dword(pi->dev,
+ pi->pmecap_offset + PCI_PM_CTRL, w);
+}
+
+u32 pcie_lcreg(void *pch, u32 mask, u32 val)
+{
+ pcicore_info_t *pi = (pcicore_info_t *) pch;
+ u8 offset;
+ u32 tmpval;
+
+ offset = pi->pciecap_lcreg_offset;
+ if (!offset)
+ return 0;
+
+ /* set operation */
+ if (mask)
+ pci_write_config_dword(pi->dev, offset, val);
+
+ pci_read_config_dword(pi->dev, offset, &tmpval);
+ return tmpval;
+}
+
+u32
+pcicore_pciereg(void *pch, u32 offset, u32 mask, u32 val, uint type)
+{
+ u32 reg_val = 0;
+ pcicore_info_t *pi = (pcicore_info_t *) pch;
+ sbpcieregs_t *pcieregs = pi->regs.pcieregs;
+
+ if (mask) {
+ PCI_ERROR(("PCIEREG: 0x%x writeval 0x%x\n", offset, val));
+ pcie_writereg(pcieregs, type, offset, val);
+ }
+
+ /* Should not read register 0x154 */
+ if (pi->sih->buscorerev <= 5 && offset == PCIE_DLLP_PCIE11
+ && type == PCIE_PCIEREGS)
+ return reg_val;
+
+ reg_val = pcie_readreg(pcieregs, type, offset);
+ PCI_ERROR(("PCIEREG: 0x%x readval is 0x%x\n", offset, reg_val));
+
+ return reg_val;
+}
+
+u32
+pcicore_pcieserdesreg(void *pch, u32 mdioslave, u32 offset, u32 mask,
+ u32 val)
+{
+ u32 reg_val = 0;
+ pcicore_info_t *pi = (pcicore_info_t *) pch;
+
+ if (mask) {
+ PCI_ERROR(("PCIEMDIOREG: 0x%x writeval 0x%x\n", offset, val));
+ pcie_mdiowrite(pi, mdioslave, offset, val);
+ }
+
+ if (pcie_mdioread(pi, mdioslave, offset, ®_val))
+ reg_val = 0xFFFFFFFF;
+ PCI_ERROR(("PCIEMDIOREG: dev 0x%x offset 0x%x read 0x%x\n", mdioslave,
+ offset, reg_val));
+
+ return reg_val;
+}
diff --git a/drivers/staging/brcm80211/brcmsmac/nvram.c b/drivers/staging/brcm80211/brcmsmac/nvram.c
new file mode 100644
index 0000000..085ec0b
--- /dev/null
+++ b/drivers/staging/brcm80211/brcmsmac/nvram.c
@@ -0,0 +1,215 @@
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/slab.h>
+#include <linux/string.h>
+#include <bcmdefs.h>
+#include <bcmutils.h>
+#include <bcmnvram.h>
+#include <sbchipc.h>
+#include <bcmdevs.h>
+#include <hndsoc.h>
+
+#define NVR_MSG(x)
+
+typedef struct _vars {
+ struct _vars *next;
+ int bufsz; /* allocated size */
+ int size; /* actual vars size */
+ char *vars;
+} vars_t;
+
+#define VARS_T_OH sizeof(vars_t)
+
+static vars_t *vars;
+
+#define NVRAM_FILE 1
+
+static char *findvar(char *vars, char *lim, const char *name);
+
+int nvram_init(void)
+{
+
+ /* Make sure we read nvram in flash just once before freeing the memory */
+ if (vars != NULL) {
+ NVR_MSG(("nvram_init: called again without calling nvram_exit()\n"));
+ return 0;
+ }
+ return 0;
+}
+
+int nvram_append(char *varlst, uint varsz)
+{
+ uint bufsz = VARS_T_OH;
+ vars_t *new;
+
+ new = kmalloc(bufsz, GFP_ATOMIC);
+ if (new == NULL)
+ return -ENOMEM;
+
+ new->vars = varlst;
+ new->bufsz = bufsz;
+ new->size = varsz;
+ new->next = vars;
+ vars = new;
+
+ return 0;
+}
+
+void nvram_exit(void)
+{
+ vars_t *this, *next;
+
+ this = vars;
+ if (this)
+ kfree(this->vars);
+
+ while (this) {
+ next = this->next;
+ kfree(this);
+ this = next;
+ }
+ vars = NULL;
+}
+
+static char *findvar(char *vars, char *lim, const char *name)
+{
+ char *s;
+ int len;
+
+ len = strlen(name);
+
+ for (s = vars; (s < lim) && *s;) {
+ if ((memcmp(s, name, len) == 0) && (s[len] == '='))
+ return &s[len + 1];
+
+ while (*s++)
+ ;
+ }
+
+ return NULL;
+}
+
+/*
+ * Search the name=value vars for a specific one and return its value.
+ * Returns NULL if not found.
+ */
+char *getvar(char *vars, const char *name)
+{
+ char *s;
+ int len;
+
+ if (!name)
+ return NULL;
+
+ len = strlen(name);
+ if (len == 0)
+ return NULL;
+
+ /* first look in vars[] */
+ for (s = vars; s && *s;) {
+ if ((memcmp(s, name, len) == 0) && (s[len] == '='))
+ return &s[len + 1];
+
+ while (*s++)
+ ;
+ }
+ /* then query nvram */
+ return nvram_get(name);
+}
+
+/*
+ * Search the vars for a specific one and return its value as
+ * an integer. Returns 0 if not found.
+ */
+int getintvar(char *vars, const char *name)
+{
+ char *val;
+
+ val = getvar(vars, name);
+ if (val == NULL)
+ return 0;
+
+ return simple_strtoul(val, NULL, 0);
+}
+
+char *nvram_get(const char *name)
+{
+ char *v = NULL;
+ vars_t *cur;
+
+ for (cur = vars; cur; cur = cur->next) {
+ v = findvar(cur->vars, cur->vars + cur->size, name);
+ if (v)
+ break;
+ }
+
+ return v;
+}
+
+int nvram_set(const char *name, const char *value)
+{
+ return 0;
+}
+
+int nvram_unset(const char *name)
+{
+ return 0;
+}
+
+int nvram_reset(void)
+{
+ return 0;
+}
+
+int nvram_commit(void)
+{
+ return 0;
+}
+
+int nvram_getall(char *buf, int count)
+{
+ int len, resid = count;
+ vars_t *this;
+
+ this = vars;
+ while (this) {
+ char *from, *lim, *to;
+ int acc;
+
+ from = this->vars;
+ lim = (char *)(this->vars + this->size);
+ to = buf;
+ acc = 0;
+ while ((from < lim) && (*from)) {
+ len = strlen(from) + 1;
+ if (resid < (acc + len))
+ return -EOVERFLOW;
+ memcpy(to, from, len);
+ acc += len;
+ from += len;
+ to += len;
+ }
+
+ resid -= acc;
+ buf += acc;
+ this = this->next;
+ }
+ if (resid < 1)
+ return -EOVERFLOW;
+ *buf = '\0';
+ return 0;
+}
diff --git a/drivers/staging/brcm80211/brcmsmac/phy/wlc_phy_cmn.c b/drivers/staging/brcm80211/brcmsmac/phy/wlc_phy_cmn.c
index 8f75af2..6cba4df 100644
--- a/drivers/staging/brcm80211/brcmsmac/phy/wlc_phy_cmn.c
+++ b/drivers/staging/brcm80211/brcmsmac/phy/wlc_phy_cmn.c
@@ -18,10 +18,12 @@
#include <linux/kernel.h>
#include <linux/string.h>
-#include <bcmdefs.h>
+#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/pci.h>
+
+#include <bcmdefs.h>
#include <bcmnvram.h>
#include <sbchipc.h>
#include <bcmdevs.h>
@@ -155,8 +157,6 @@
char *s;
int len;
- ASSERT(pi->vars != (char *)&pi->vars);
-
if (!name)
return NULL;
@@ -241,7 +241,7 @@
break;
default:
- ASSERT(VALID_PHYTYPE(pi->pubpi.phy_type));
+ break;
}
if ((D11REV_GE(pi->sh->corerev, 24)) ||
@@ -391,16 +391,6 @@
W_REG(&pi->regs->phychannel, val);
}
-#if defined(BCMDBG)
-static bool wlc_phy_war41476(phy_info_t *pi)
-{
- u32 mc = R_REG(&pi->regs->maccontrol);
-
- return ((mc & MCTL_EN_MAC) == 0)
- || ((mc & MCTL_PHYLOCK) == MCTL_PHYLOCK);
-}
-#endif
-
u16 read_phy_reg(phy_info_t *pi, u16 addr)
{
d11regs_t *regs;
@@ -412,10 +402,6 @@
(void)R_REG(®s->phyregaddr);
#endif
- ASSERT(!
- (D11REV_IS(pi->sh->corerev, 11)
- || D11REV_IS(pi->sh->corerev, 12)) || wlc_phy_war41476(pi));
-
pi->phy_wreg = 0;
return R_REG(®s->phyregdata);
}
@@ -455,10 +441,6 @@
(void)R_REG(®s->phyregaddr);
#endif
- ASSERT(!
- (D11REV_IS(pi->sh->corerev, 11)
- || D11REV_IS(pi->sh->corerev, 12)) || wlc_phy_war41476(pi));
-
W_REG(®s->phyregdata, (R_REG(®s->phyregdata) & val));
pi->phy_wreg = 0;
}
@@ -474,10 +456,6 @@
(void)R_REG(®s->phyregaddr);
#endif
- ASSERT(!
- (D11REV_IS(pi->sh->corerev, 11)
- || D11REV_IS(pi->sh->corerev, 12)) || wlc_phy_war41476(pi));
-
W_REG(®s->phyregdata, (R_REG(®s->phyregdata) | val));
pi->phy_wreg = 0;
}
@@ -493,10 +471,6 @@
(void)R_REG(®s->phyregaddr);
#endif
- ASSERT(!
- (D11REV_IS(pi->sh->corerev, 11)
- || D11REV_IS(pi->sh->corerev, 12)) || wlc_phy_war41476(pi));
-
W_REG(®s->phyregdata,
((R_REG(®s->phyregdata) & ~mask) | (val & mask)));
pi->phy_wreg = 0;
@@ -579,14 +553,12 @@
void wlc_phy_shared_detach(shared_phy_t *phy_sh)
{
if (phy_sh) {
- if (phy_sh->phy_head) {
- ASSERT(!phy_sh->phy_head);
- }
kfree(phy_sh);
}
}
-wlc_phy_t *wlc_phy_attach(shared_phy_t *sh, void *regs, int bandtype, char *vars)
+wlc_phy_t *wlc_phy_attach(shared_phy_t *sh, void *regs, int bandtype,
+ char *vars, struct wiphy *wiphy)
{
phy_info_t *pi;
u32 sflags = 0;
@@ -596,7 +568,7 @@
if (D11REV_IS(sh->corerev, 4))
sflags = SISF_2G_PHY | SISF_5G_PHY;
else
- sflags = si_core_sflags(sh->sih, 0, 0);
+ sflags = ai_core_sflags(sh->sih, 0, 0);
if (BAND_5G(bandtype)) {
if ((sflags & (SISF_5G_PHY | SISF_DB_PHY)) == 0) {
@@ -616,6 +588,7 @@
if (pi == NULL) {
return NULL;
}
+ pi->wiphy = wiphy;
pi->regs = (d11regs_t *) regs;
pi->sh = sh;
pi->phy_init_por = true;
@@ -781,8 +754,6 @@
pi->sh->phy_head = pi->next;
else if (pi->sh->phy_head->next == pi)
pi->sh->phy_head->next = NULL;
- else
- ASSERT(0);
if (pi->pi_fptr.detach)
(pi->pi_fptr.detach) (pi);
@@ -894,7 +865,6 @@
phy_bw_clkbits = SICF_BW40;
break;
default:
- ASSERT(0);
break;
}
}
@@ -962,24 +932,20 @@
pi->radio_chanspec = chanspec;
mc = R_REG(&pi->regs->maccontrol);
- if ((mc & MCTL_EN_MAC) != 0) {
- ASSERT((const char *)
- "wlc_phy_init: Called with the MAC running!" == NULL);
- }
-
- ASSERT(pi != NULL);
+ if (WARN(mc & MCTL_EN_MAC, "HW error MAC running on init"))
+ return;
if (!(pi->measure_hold & PHY_HOLD_FOR_SCAN)) {
pi->measure_hold |= PHY_HOLD_FOR_NOT_ASSOC;
}
- if (D11REV_GE(pi->sh->corerev, 5))
- ASSERT(si_core_sflags(pi->sh->sih, 0, 0) & SISF_FCLKA);
+ if (WARN(!(ai_core_sflags(pi->sh->sih, 0, 0) & SISF_FCLKA),
+ "HW error SISF_FCLKA\n"))
+ return;
phy_init = pi->pi_fptr.init;
if (phy_init == NULL) {
- ASSERT(phy_init != NULL);
return;
}
@@ -1013,7 +979,9 @@
phy_info_t *pi = (phy_info_t *) pih;
initfn_t cal_init = NULL;
- ASSERT((R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC) == 0);
+ if (WARN((R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC) != 0,
+ "HW error: MAC enabled during phy cal\n"))
+ return;
if (!pi->initialized) {
cal_init = pi->pi_fptr.calinit;
@@ -1029,8 +997,6 @@
phy_info_t *pi = (phy_info_t *) pih;
int callbacks = 0;
- ASSERT(pi->phytest_on == false);
-
if (pi->phycal_timer
&& !wlapi_del_timer(pi->sh->physhim, pi->phycal_timer))
callbacks++;
@@ -1070,8 +1036,6 @@
void wlc_phy_table_data_write(phy_info_t *pi, uint width, u32 val)
{
- ASSERT((width == 8) || (width == 16) || (width == 32));
-
if ((pi->sh->chip == BCM43224_CHIP_ID ||
pi->sh->chip == BCM43421_CHIP_ID) &&
(pi->sh->chiprev == 1) &&
@@ -1105,8 +1069,6 @@
const u16 *ptbl_16b = (const u16 *)ptbl_info->tbl_ptr;
const u32 *ptbl_32b = (const u32 *)ptbl_info->tbl_ptr;
- ASSERT((tbl_width == 8) || (tbl_width == 16) || (tbl_width == 32));
-
write_phy_reg(pi, tblAddr, (tbl_id << 10) | tbl_offset);
for (idx = 0; idx < ptbl_info->tbl_len; idx++) {
@@ -1148,8 +1110,6 @@
u16 *ptbl_16b = (u16 *)ptbl_info->tbl_ptr;
u32 *ptbl_32b = (u32 *)ptbl_info->tbl_ptr;
- ASSERT((tbl_width == 8) || (tbl_width == 16) || (tbl_width == 32));
-
write_phy_reg(pi, tblAddr, (tbl_id << 10) | tbl_offset);
for (idx = 0; idx < ptbl_info->tbl_len; idx++) {
@@ -1243,8 +1203,6 @@
};
u32 *dummypkt;
- ASSERT((R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC) == 0);
-
dummypkt = (u32 *) (ofdm ? ofdmpkt : cckpkt);
wlapi_bmac_write_template_ram(pi->sh->physhim, 0, DUMMY_PKT_LEN,
dummypkt);
@@ -1258,7 +1216,6 @@
W_REG(®s->txe_phyctl, (ofdm ? 1 : 0) | PHY_TXC_ANT_0);
if (ISNPHY(pi) || ISLCNPHY(pi)) {
- ASSERT(ofdm);
W_REG(®s->txe_phyctl1, 0x1A02);
}
@@ -1317,7 +1274,6 @@
void wlc_phy_hold_upd(wlc_phy_t *pih, mbool id, bool set)
{
phy_info_t *pi = (phy_info_t *) pih;
- ASSERT(id);
if (set) {
mboolset(pi->measure_hold, id);
@@ -1439,8 +1395,6 @@
u16 m_cur_channel;
chansetfn_t chanspec_set = NULL;
- ASSERT(!wf_chspec_malformed(chanspec));
-
m_cur_channel = CHSPEC_CHANNEL(chanspec);
if (CHSPEC_IS5G(chanspec))
m_cur_channel |= D11_CURCHANNEL_5G;
@@ -1480,8 +1434,7 @@
range = wlc_phy_get_chan_freq_range_nphy(pi, channel);
} else if (ISLCNPHY(pi)) {
range = wlc_phy_chanspec_freq2bandrange_lpssn(freq);
- } else
- ASSERT(0);
+ }
return range;
}
@@ -1511,8 +1464,6 @@
uint i;
uint channel;
- ASSERT((band == WLC_BAND_2G) || (band == WLC_BAND_5G));
-
memset(channels, 0, sizeof(chanvec_t));
for (i = 0; i < ARRAY_SIZE(chan_info_all); i++) {
@@ -1535,8 +1486,6 @@
uint channel;
chanspec_t chspec;
- ASSERT((band == WLC_BAND_2G) || (band == WLC_BAND_5G));
-
for (i = 0; i < ARRAY_SIZE(chan_info_all); i++) {
channel = chan_info_all[i].chan;
@@ -1572,8 +1521,6 @@
return chspec;
}
- ASSERT(0);
-
return (chanspec_t) INVCHANSPEC;
}
@@ -1581,7 +1528,6 @@
{
phy_info_t *pi = (phy_info_t *) ppi;
- ASSERT(qdbm != NULL);
*qdbm = pi->tx_user_target[0];
if (override != NULL)
*override = pi->txpwroverride;
@@ -1703,7 +1649,6 @@
break;
}
}
- ASSERT(i < ARRAY_SIZE(chan_info_all));
if (pi->hwtxpwr) {
*max_pwr = pi->hwtxpwr[i];
@@ -2134,7 +2079,6 @@
{
int j;
if (ISNPHY(pi)) {
- ASSERT(0);
return;
}
@@ -2466,8 +2410,6 @@
mod_phy_reg(pi, 0x410, (0x1 << 1), 0x00 << 1);
mod_phy_reg(pi, 0x410, (0x1 << 0), (u16) val << 0);
}
- } else {
- ASSERT(0);
}
if (!suspend)
@@ -2483,7 +2425,6 @@
u8 i;
memset((u8 *) cmplx_pwr_dbm, 0, sizeof(cmplx_pwr_dbm));
- ASSERT(pi->pubpi.phy_corenum <= PHY_CORE_MAX);
wlc_phy_compute_dB(cmplx_pwr, cmplx_pwr_dbm, pi->pubpi.phy_corenum);
for (i = 0; i < pi->pubpi.phy_corenum; i++) {
@@ -2529,7 +2470,6 @@
break;
default:
- ASSERT(0);
break;
}
@@ -2678,7 +2618,6 @@
s8 noise_dbm = PHY_NOISE_FIXED_VAL_NPHY;
u8 idx, core;
- ASSERT(pi->pubpi.phy_corenum <= PHY_CORE_MAX);
memset((u8 *) cmplx_pwr, 0, sizeof(cmplx_pwr));
memset((u8 *) noise_dbm_ant, 0, sizeof(noise_dbm_ant));
@@ -2760,8 +2699,6 @@
channel = jssi_aux & D11_CURCHANNEL_MAX;
noise_dbm = wlc_phy_noise_read_shmem(pi);
- } else {
- ASSERT(0);
}
wlc_phy_noise_cb(pi, channel, noise_dbm);
@@ -2811,25 +2748,20 @@
void wlc_phy_compute_dB(u32 *cmplx_pwr, s8 *p_cmplx_pwr_dB, u8 core)
{
- u8 shift_ct, lsb, msb, secondmsb, i;
+ u8 msb, secondmsb, i;
u32 tmp;
for (i = 0; i < core; i++) {
+ secondmsb = 0;
tmp = cmplx_pwr[i];
- shift_ct = msb = secondmsb = 0;
- while (tmp != 0) {
- tmp = tmp >> 1;
- shift_ct++;
- lsb = (u8) (tmp & 1);
- if (lsb == 1)
- msb = shift_ct;
- }
- secondmsb = (u8) ((cmplx_pwr[i] >> (msb - 1)) & 1);
+ msb = fls(tmp);
+ if (msb)
+ secondmsb = (u8) ((tmp >> (--msb - 1)) & 1);
p_cmplx_pwr_dB[i] = (s8) (3 * msb + 2 * secondmsb);
}
}
-void BCMFASTPATH wlc_phy_rssi_compute(wlc_phy_t *pih, void *ctx)
+void wlc_phy_rssi_compute(wlc_phy_t *pih, void *ctx)
{
wlc_d11rxhdr_t *wlc_rxhdr = (wlc_d11rxhdr_t *) ctx;
d11rxhdr_t *rxh = &wlc_rxhdr->rxhdr;
@@ -2871,10 +2803,7 @@
rssi -= 256;
} else if (radioid == BCM2055_ID || radioid == BCM2056_ID
|| radioid == BCM2057_ID) {
- ASSERT(ISNPHY(pi));
rssi = wlc_phy_rssi_compute_nphy(pi, wlc_rxhdr);
- } else {
- ASSERT((const char *)"Unknown radio" == NULL);
}
end:
@@ -2900,9 +2829,6 @@
wlc_lcnphy_deaf_mode(pi, true);
else if (ISNPHY(pi))
wlc_nphy_deaf_mode(pi, true);
- else {
- ASSERT(0);
- }
}
void wlc_phy_watchdog(wlc_phy_t *pih)
@@ -3163,13 +3089,9 @@
} else if (pi->nphy_perical == PHY_PERICAL_SPHASE)
wlc_phy_cal_perical_nphy_run(pi,
PHY_PERICAL_AUTO);
- else {
- ASSERT(0);
- }
}
break;
default:
- ASSERT(0);
break;
}
}
@@ -3192,25 +3114,6 @@
return nbits;
}
-u32 wlc_phy_sqrt_int(u32 value)
-{
- u32 root = 0, shift = 0;
-
- for (shift = 0; shift < 32; shift += 2) {
- if (((0x40000000 >> shift) + root) <= value) {
- value -= ((0x40000000 >> shift) + root);
- root = (root >> 1) | (0x40000000 >> shift);
- } else {
- root = root >> 1;
- }
- }
-
- if (root < value)
- ++root;
-
- return root;
-}
-
void wlc_phy_stf_chain_init(wlc_phy_t *pih, u8 txchain, u8 rxchain)
{
phy_info_t *pi = (phy_info_t *) pih;
@@ -3311,12 +3214,12 @@
mod_phy_reg(pi, 0x44c, (0x1 << 2), (1) << 2);
}
- si_corereg(pi->sh->sih, SI_CC_IDX,
+ ai_corereg(pi->sh->sih, SI_CC_IDX,
offsetof(chipcregs_t, gpiocontrol), ~0x0,
0x0);
- si_corereg(pi->sh->sih, SI_CC_IDX,
+ ai_corereg(pi->sh->sih, SI_CC_IDX,
offsetof(chipcregs_t, gpioout), 0x40, 0x40);
- si_corereg(pi->sh->sih, SI_CC_IDX,
+ ai_corereg(pi->sh->sih, SI_CC_IDX,
offsetof(chipcregs_t, gpioouten), 0x40,
0x40);
} else {
@@ -3324,11 +3227,11 @@
mod_phy_reg(pi, 0x44d, (0x1 << 2), (0) << 2);
- si_corereg(pi->sh->sih, SI_CC_IDX,
+ ai_corereg(pi->sh->sih, SI_CC_IDX,
offsetof(chipcregs_t, gpioout), 0x40, 0x00);
- si_corereg(pi->sh->sih, SI_CC_IDX,
+ ai_corereg(pi->sh->sih, SI_CC_IDX,
offsetof(chipcregs_t, gpioouten), 0x40, 0x0);
- si_corereg(pi->sh->sih, SI_CC_IDX,
+ ai_corereg(pi->sh->sih, SI_CC_IDX,
offsetof(chipcregs_t, gpiocontrol), ~0x0,
0x40);
}
@@ -3387,33 +3290,6 @@
*ofdmoffset = 0;
}
-u32 wlc_phy_qdiv_roundup(u32 dividend, u32 divisor, u8 precision)
-{
- u32 quotient, remainder, roundup, rbit;
-
- ASSERT(divisor);
-
- quotient = dividend / divisor;
- remainder = dividend % divisor;
- rbit = divisor & 1;
- roundup = (divisor >> 1) + rbit;
-
- while (precision--) {
- quotient <<= 1;
- if (remainder >= roundup) {
- quotient++;
- remainder = ((remainder - roundup) << 1) + rbit;
- } else {
- remainder <<= 1;
- }
- }
-
- if (remainder >= roundup)
- quotient++;
-
- return quotient;
-}
-
s8 wlc_phy_upd_rssi_offset(phy_info_t *pi, s8 rssi, chanspec_t chanspec)
{
diff --git a/drivers/staging/brcm80211/brcmsmac/phy/wlc_phy_hal.h b/drivers/staging/brcm80211/brcmsmac/phy/wlc_phy_hal.h
index bf962d5..8939153 100644
--- a/drivers/staging/brcm80211/brcmsmac/phy/wlc_phy_hal.h
+++ b/drivers/staging/brcm80211/brcmsmac/phy/wlc_phy_hal.h
@@ -18,9 +18,10 @@
#define _wlc_phy_h_
#include <wlioctl.h>
-#include <siutils.h>
+#include <aiutils.h>
#include <d11.h>
#include <wlc_phy_shim.h>
+#include <net/mac80211.h> /* struct wiphy */
#define IDCODE_VER_MASK 0x0000000f
#define IDCODE_VER_SHIFT 0
@@ -149,7 +150,7 @@
extern shared_phy_t *wlc_phy_shared_attach(shared_phy_params_t *shp);
extern void wlc_phy_shared_detach(shared_phy_t *phy_sh);
extern wlc_phy_t *wlc_phy_attach(shared_phy_t *sh, void *regs, int bandtype,
- char *vars);
+ char *vars, struct wiphy *wiphy);
extern void wlc_phy_detach(wlc_phy_t *ppi);
extern bool wlc_phy_get_phyversion(wlc_phy_t *pih, u16 *phytype,
diff --git a/drivers/staging/brcm80211/brcmsmac/phy/wlc_phy_int.h b/drivers/staging/brcm80211/brcmsmac/phy/wlc_phy_int.h
index 6e12a95..10cbf52 100644
--- a/drivers/staging/brcm80211/brcmsmac/phy/wlc_phy_int.h
+++ b/drivers/staging/brcm80211/brcmsmac/phy/wlc_phy_int.h
@@ -936,6 +936,7 @@
u8 phycal_tempdelta;
u32 mcs20_po;
u32 mcs40_po;
+ struct wiphy *wiphy;
};
typedef s32 fixed;
@@ -1024,7 +1025,6 @@
extern void wlc_phy_cordic(fixed theta, cs32 *val);
extern u8 wlc_phy_nbits(s32 value);
-extern u32 wlc_phy_sqrt_int(u32 value);
extern void wlc_phy_compute_dB(u32 *cmplx_pwr, s8 *p_dB, u8 core);
extern uint wlc_phy_init_radio_regs_allbands(phy_info_t *pi,
@@ -1093,8 +1093,6 @@
extern void wlc_2064_vco_cal(phy_info_t *pi);
extern void wlc_phy_txpower_recalc_target(phy_info_t *pi);
-extern u32 wlc_phy_qdiv_roundup(u32 dividend, u32 divisor,
- u8 precision);
#define LCNPHY_TBL_ID_PAPDCOMPDELTATBL 0x18
#define LCNPHY_TX_POWER_TABLE_SIZE 128
diff --git a/drivers/staging/brcm80211/brcmsmac/phy/wlc_phy_lcn.c b/drivers/staging/brcm80211/brcmsmac/phy/wlc_phy_lcn.c
index a5a7bb8..b8864c5 100644
--- a/drivers/staging/brcm80211/brcmsmac/phy/wlc_phy_lcn.c
+++ b/drivers/staging/brcm80211/brcmsmac/phy/wlc_phy_lcn.c
@@ -19,18 +19,19 @@
#include <linux/bitops.h>
#include <linux/delay.h>
#include <wlc_cfg.h>
-#include <qmath.h>
#include <linux/pci.h>
-#include <siutils.h>
-#include <hndpmu.h>
+#include <aiutils.h>
+#include <wlc_pmu.h>
+#include <bcmnvram.h>
#include <bcmdevs.h>
#include <sbhnddma.h>
-#include <wlc_phy_radio.h>
-#include <wlc_phy_int.h>
-#include <wlc_phy_lcn.h>
-#include <wlc_phytbl_lcn.h>
+#include "wlc_phy_radio.h"
+#include "wlc_phy_int.h"
+#include "wlc_phy_qmath.h"
+#include "wlc_phy_lcn.h"
+#include "wlc_phytbl_lcn.h"
#define PLL_2064_NDIV 90
#define PLL_2064_LOW_END_VCO 3000
@@ -1081,8 +1082,6 @@
{
u32 quotient, remainder, roundup, rbit;
- ASSERT(divisor);
-
quotient = dividend / divisor;
remainder = dividend % divisor;
rbit = divisor & 1;
@@ -1780,11 +1779,6 @@
s8 index;
phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
- ASSERT((LCNPHY_TX_PWR_CTRL_OFF == mode) ||
- (LCNPHY_TX_PWR_CTRL_SW == mode) ||
- (LCNPHY_TX_PWR_CTRL_HW == mode) ||
- (LCNPHY_TX_PWR_CTRL_TEMPBASED == mode));
-
mode = wlc_lcnphy_set_tx_pwr_ctrl_mode(pi, mode);
old_mode = wlc_lcnphy_set_tx_pwr_ctrl_mode(pi, old_mode);
@@ -1904,16 +1898,14 @@
break;
case LCNPHY_CAL_RECAL:
- ASSERT(pi_lcn->lcnphy_cal_results.txiqlocal_bestcoeffs_valid);
-
start_coeffs = syst_coeffs;
-
cal_cmds = commands_recal;
n_cal_cmds = ARRAY_SIZE(commands_recal);
command_nums = command_nums_recal;
break;
+
default:
- ASSERT(false);
+ break;
}
wlc_lcnphy_common_write_table(pi, LCNPHY_TBL_ID_IQLOCAL,
@@ -2460,8 +2452,6 @@
lcnphy_txgains_t gains;
phy_info_lcnphy_t *pi_lcn = pi->u.pi_lcnphy;
- ASSERT(index <= LCNPHY_MAX_TX_POWER_INDEX);
-
pi_lcn->lcnphy_tx_power_idx_override = (s8) index;
pi_lcn->lcnphy_current_index = (u8) index;
@@ -2760,7 +2750,6 @@
do {
bw = phy_bw * 1000 * k;
num_samps = bw / ABS(f_kHz);
- ASSERT(num_samps <= ARRAY_SIZE(data_buf));
k++;
} while ((num_samps * (u32) (ABS(f_kHz))) != bw);
} else
@@ -3255,7 +3244,7 @@
}
b /= temp;
b -= a * a;
- b = (s32) wlc_phy_sqrt_int((u32) b);
+ b = (s32) int_sqrt((unsigned long) b);
b -= (1 << 10);
a0_new = (u16) (a & 0x3ff);
b0_new = (u16) (b & 0x3ff);
@@ -3298,8 +3287,6 @@
return false;
}
if (module == 2) {
- ASSERT(iqcomp_sz);
-
while (iqcomp_sz--) {
if (iqcomp[iqcomp_sz].chan ==
CHSPEC_CHANNEL(pi->radio_chanspec)) {
@@ -3313,7 +3300,6 @@
break;
}
}
- ASSERT(result);
goto cal_done;
}
@@ -3584,9 +3570,6 @@
if (wlc_lcnphy_tempsense_based_pwr_ctrl_enabled(pi))
wlc_lcnphy_tx_power_adjustment((wlc_phy_t *) pi);
break;
- default:
- ASSERT(0);
- break;
}
}
@@ -5071,9 +5054,7 @@
pi->hwpwrctrl_capable = true;
}
- pi->xtalfreq = si_alp_clock(pi->sh->sih);
- ASSERT(0 == (pi->xtalfreq % 1000));
-
+ pi->xtalfreq = si_pmu_alp_clock(pi->sh->sih);
pi_lcn->lcnphy_papd_rxGnCtrl_init = 0;
pi->pi_fptr.init = wlc_phy_init_lcnphy;
@@ -5293,9 +5274,7 @@
}
}
- if (filt_index == -1) {
- ASSERT(false);
- } else {
+ if (filt_index != -1) {
for (j = 0; j < LCNPHY_NUM_DIG_FILT_COEFFS; j++) {
write_phy_reg(pi, addr[j],
LCNPHY_txdigfiltcoeffs_cck
@@ -5310,9 +5289,7 @@
}
}
- if (filt_index == -1) {
- ASSERT(false);
- } else {
+ if (filt_index != -1) {
for (j = 0; j < LCNPHY_NUM_DIG_FILT_COEFFS; j++) {
write_phy_reg(pi, addr_ofdm[j],
LCNPHY_txdigfiltcoeffs_ofdm
diff --git a/drivers/staging/brcm80211/brcmsmac/phy/wlc_phy_n.c b/drivers/staging/brcm80211/brcmsmac/phy/wlc_phy_n.c
index 7947c60..7127509 100644
--- a/drivers/staging/brcm80211/brcmsmac/phy/wlc_phy_n.c
+++ b/drivers/staging/brcm80211/brcmsmac/phy/wlc_phy_n.c
@@ -20,9 +20,9 @@
#include <wlc_cfg.h>
#include <linux/delay.h>
#include <linux/pci.h>
-#include <siutils.h>
+#include <aiutils.h>
#include <sbchipc.h>
-#include <hndpmu.h>
+#include <wlc_pmu.h>
#include <bcmdevs.h>
#include <sbhnddma.h>
@@ -14218,8 +14218,6 @@
{
u16 addr, val;
- ASSERT(ISNPHY(pi));
-
val = 0x1e1f;
for (addr = (NPHY_TO_BPHY_OFF + BPHY_RSSI_LUT);
addr <= (NPHY_TO_BPHY_OFF + BPHY_RSSI_LUT_END); addr++) {
@@ -14367,8 +14365,6 @@
break;
default:
-
- ASSERT(0);
break;
}
@@ -14401,8 +14397,6 @@
[idx]);
break;
default:
-
- ASSERT(0);
break;
}
} else {
@@ -14550,7 +14544,7 @@
(pi->sh->chippkg == BCM4718_PKG_ID))) {
if ((pi->sh->boardflags & BFL_EXTLNA) &&
(CHSPEC_IS2G(pi->radio_chanspec))) {
- si_corereg(pi->sh->sih, SI_CC_IDX,
+ ai_corereg(pi->sh->sih, SI_CC_IDX,
offsetof(chipcregs_t, chipcontrol), 0x40,
0x40);
}
@@ -14564,17 +14558,15 @@
if ((pi->nphy_gband_spurwar2_en) && CHSPEC_IS2G(pi->radio_chanspec) &&
CHSPEC_IS40(pi->radio_chanspec)) {
- regs = (d11regs_t *) si_switch_core(pi->sh->sih, D11_CORE_ID,
+ regs = (d11regs_t *) ai_switch_core(pi->sh->sih, D11_CORE_ID,
&origidx, &intr_val);
- ASSERT(regs != NULL);
-
d11_clk_ctl_st = R_REG(®s->clk_ctl_st);
AND_REG(®s->clk_ctl_st,
~(CCS_FORCEHT | CCS_HTAREQ));
W_REG(®s->clk_ctl_st, d11_clk_ctl_st);
- si_restore_core(pi->sh->sih, origidx, intr_val);
+ ai_restore_core(pi->sh->sih, origidx, intr_val);
}
pi->use_int_tx_iqlo_cal_nphy =
@@ -14783,10 +14775,7 @@
rfpwr_offset = (s16)
nphy_papd_padgain_dlt_2g_2057rev7
[pad_gn];
- } else {
- ASSERT(0);
}
-
} else {
if ((pi->pubpi.radiorev == 3) ||
(pi->pubpi.radiorev == 4) ||
@@ -14800,8 +14789,6 @@
rfpwr_offset = (s16)
nphy_papd_pgagain_dlt_5g_2057rev7
[pga_gn];
- } else {
- ASSERT(0);
}
}
wlc_phy_table_write_nphy(pi,
@@ -14905,10 +14892,10 @@
}
if (wlc_phy_cal_txiqlo_nphy
- (pi, target_gain, true, false) == BCME_OK) {
+ (pi, target_gain, true, false) == 0) {
if (wlc_phy_cal_rxiq_nphy
(pi, target_gain, 2,
- false) == BCME_OK) {
+ false) == 0) {
wlc_phy_savecal_nphy(pi);
}
@@ -14963,8 +14950,6 @@
{
u16 val;
- ASSERT(0 == (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
-
wlapi_bmac_phyclk_fgc(pi->sh->physhim, ON);
val = read_phy_reg(pi, 0x01);
@@ -16130,8 +16115,6 @@
0x18, 16, bcm_adc_vmid);
wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 4,
0x1c, 16, bcm_adc_gain);
- } else {
- ASSERT(0);
}
write_radio_reg(pi,
@@ -17418,8 +17401,10 @@
SPINWAIT(((read_radio_reg(pi, RADIO_2055_CAL_COUNTER_OUT2) &
RADIO_2055_RCAL_DONE) != RADIO_2055_RCAL_DONE), 2000);
- ASSERT((read_radio_reg(pi, RADIO_2055_CAL_COUNTER_OUT2) &
- RADIO_2055_RCAL_DONE) == RADIO_2055_RCAL_DONE);
+ if (WARN((read_radio_reg(pi, RADIO_2055_CAL_COUNTER_OUT2) &
+ RADIO_2055_RCAL_DONE) != RADIO_2055_RCAL_DONE,
+ "HW error: radio calibration1\n"))
+ return;
and_radio_reg(pi, RADIO_2055_CAL_LPO_CNTRL,
~(RADIO_2055_CAL_LPO_ENABLE));
@@ -17510,7 +17495,6 @@
break;
default:
- ASSERT(0);
break;
}
}
@@ -17571,7 +17555,6 @@
regs_2057_ptr = regs_2057_rev5v1;
} else {
- ASSERT(0);
break;
}
@@ -17586,11 +17569,8 @@
break;
default:
- ASSERT(0);
break;
}
- } else {
- ASSERT(0);
}
wlc_phy_init_radio_regs_allbands(pi, regs_2057_ptr);
@@ -17708,7 +17688,6 @@
}
if (i >= tbl_len) {
- ASSERT(i < tbl_len);
goto fail;
}
if (pi->pubpi.radiorev == 5) {
@@ -17765,7 +17744,6 @@
}
if (i >= tbl_len) {
- ASSERT(i < tbl_len);
goto fail;
}
*t1 = &chan_info_tbl_p_1[i];
@@ -17777,7 +17755,6 @@
break;
if (i >= ARRAY_SIZE(chan_info_nphy_2055)) {
- ASSERT(i < ARRAY_SIZE(chan_info_nphy_2055));
goto fail;
}
*t3 = &chan_info_nphy_2055[i];
@@ -18276,7 +18253,9 @@
udelay(100);
}
- ASSERT(i < MAX_205x_RCAL_WAITLOOPS);
+ if (WARN(i == MAX_205x_RCAL_WAITLOOPS,
+ "HW error: radio calib2"))
+ return 0;
mod_radio_reg(pi, RADIO_2057_RCAL_CONFIG, 0x2, 0x0);
@@ -18325,7 +18304,9 @@
udelay(100);
}
- ASSERT(i < MAX_205x_RCAL_WAITLOOPS);
+ if (WARN(i == MAX_205x_RCAL_WAITLOOPS,
+ "HW error: radio calib3"))
+ return 0;
write_radio_reg(pi, RADIO_2056_SYN_RCAL_MASTER | RADIO_2056_SYN,
0x1);
@@ -18572,8 +18553,6 @@
udelay(500);
}
- ASSERT(rccal_valid & 0x2);
-
write_radio_reg(pi, RADIO_2057_RCCAL_START_R1_Q1_P1, 0x15);
rccal_valid = 0;
@@ -18596,8 +18575,6 @@
udelay(500);
}
- ASSERT(rccal_valid & 0x2);
-
write_radio_reg(pi, RADIO_2057_RCCAL_START_R1_Q1_P1, 0x15);
rccal_valid = 0;
@@ -18621,7 +18598,8 @@
udelay(500);
}
- ASSERT(rccal_valid & 0x2);
+ if (WARN(!(rccal_valid & 0x2), "HW error: radio calib4"))
+ return 0;
write_radio_reg(pi, RADIO_2057_RCCAL_START_R1_Q1_P1, 0x15);
@@ -19585,8 +19563,6 @@
1, 0x08, 16, &v2);
wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_ANTSWCTRLLUT,
1, 0x0C, 16, &v3);
- } else {
- ASSERT(0);
}
if (pi->srom_fem5g.antswctrllut == 0) {
@@ -19598,15 +19574,13 @@
1, 0x18, 16, &v2);
wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_ANTSWCTRLLUT,
1, 0x1C, 16, &v3);
- } else {
- ASSERT(0);
}
} else {
write_phy_reg(pi, 0xc8, 0x0);
write_phy_reg(pi, 0xc9, 0x0);
- si_gpiocontrol(pi->sh->sih, mask, mask, GPIO_DRV_PRIORITY);
+ ai_gpiocontrol(pi->sh->sih, mask, mask, GPIO_DRV_PRIORITY);
mc = R_REG(&pi->regs->maccontrol);
mc &= ~MCTL_GPOUT_SEL_MASK;
@@ -19703,8 +19677,7 @@
or_phy_reg(pi, 0xa3, trigger_mask);
SPINWAIT((read_phy_reg(pi, 0xa4) & status_mask), 200000);
write_phy_reg(pi, 0xa1, orig_RfseqCoreActv);
-
- ASSERT((read_phy_reg(pi, 0xa4) & status_mask) == 0);
+ WARN(read_phy_reg(pi, 0xa4) & status_mask, "HW error in rf");
}
static void
@@ -19718,8 +19691,6 @@
3) ? NPHY_REV3_RFSEQ_CMD_END : NPHY_RFSEQ_CMD_END;
u8 end_dly = 1;
- ASSERT(len <= 16);
-
if (pi->phyhang_avoid)
wlc_phy_stay_in_carriersearch_nphy(pi, true);
@@ -21467,7 +21438,7 @@
wlc_phy_resetcca_nphy(pi);
}
-int BCMFASTPATH
+int
wlc_phy_rssi_compute_nphy(phy_info_t *pi, wlc_d11rxhdr_t *wlc_rxh)
{
d11rxhdr_t *rxh = &wlc_rxh->rxhdr;
@@ -21503,8 +21474,6 @@
rxpwr = (rxpwr0 < rxpwr1) ? rxpwr0 : rxpwr1;
else if (pi->sh->rssi_mode == RSSI_ANT_MERGE_AVG)
rxpwr = (rxpwr0 + rxpwr1) >> 1;
- else
- ASSERT(0);
return rxpwr;
}
@@ -21588,8 +21557,9 @@
SPINWAIT(((read_phy_reg(pi, 0x78) & val)
!= 0), 10000);
- ASSERT((read_phy_reg(pi, 0x78) & val) ==
- 0);
+ if (WARN(read_phy_reg(pi, 0x78) & val,
+ "HW error: override failed"))
+ return;
mask = (0x1 << 0);
val = 0 << 0;
@@ -22233,8 +22203,6 @@
static void wlc_phy_restore_rssical_nphy(phy_info_t *pi)
{
- ASSERT(NREV_GE(pi->pubpi.phy_rev, 3));
-
if (CHSPEC_IS2G(pi->radio_chanspec)) {
if (pi->nphy_rssical_chanspec_2G == 0)
return;
@@ -22399,13 +22367,13 @@
num_samps =
wlc_phy_gen_load_samples_nphy(pi, f_kHz, max_val, dac_test_mode);
if (num_samps == 0) {
- return BCME_ERROR;
+ return -EBADE;
}
wlc_phy_runsamples_nphy(pi, num_samps, loops, wait, iqmode,
dac_test_mode, modify_bbmult);
- return BCME_OK;
+ return 0;
}
static void
@@ -22775,8 +22743,6 @@
}
}
- ASSERT(idx != -1);
-
params->txgm = tbl_iqcal_gainparams_nphy[band_idx][k][1];
params->pga = tbl_iqcal_gainparams_nphy[band_idx][k][2];
params->pad = tbl_iqcal_gainparams_nphy[band_idx][k][3];
@@ -23855,8 +23821,6 @@
if (PHY_MUTED(pi))
return;
- ASSERT(pi->nphy_perical != PHY_PERICAL_DISABLE);
-
if (caltype == PHY_PERICAL_AUTO)
fullcal = (pi->radio_chanspec != pi->nphy_txiqlocal_chanspec);
else if (caltype == PHY_PERICAL_PARTIAL)
@@ -23913,7 +23877,7 @@
target_gain = pi->nphy_cal_target_gain;
}
- if (BCME_OK ==
+ if (0 ==
wlc_phy_cal_txiqlo_nphy(pi, target_gain, fullcal, mphase)) {
if (PHY_IPA(pi))
wlc_phy_a4(pi, true);
@@ -23925,7 +23889,7 @@
wlapi_suspend_mac_and_wait(pi->sh->physhim);
wlc_phyreg_enter((wlc_phy_t *) pi);
- if (BCME_OK == wlc_phy_cal_rxiq_nphy(pi, target_gain,
+ if (0 == wlc_phy_cal_rxiq_nphy(pi, target_gain,
(pi->
first_cal_after_assoc
|| (pi->
@@ -23955,8 +23919,6 @@
wlc_phy_radio205x_vcocal_nphy(pi);
}
} else {
- ASSERT(pi->nphy_perical >= PHY_PERICAL_MPHASE);
-
switch (pi->mphase_cal_phase_id) {
case MPHASE_CAL_STATE_INIT:
pi->nphy_perical_last = pi->sh->now;
@@ -23980,7 +23942,7 @@
if (wlc_phy_cal_txiqlo_nphy
(pi, pi->nphy_cal_target_gain, fullcal,
- true) != BCME_OK) {
+ true) != 0) {
wlc_phy_cal_perical_mphase_reset(pi);
break;
@@ -24012,7 +23974,7 @@
(pi->first_cal_after_assoc ||
(pi->cal_type_override ==
PHY_PERICAL_FULL)) ? 2 : 0,
- false) == BCME_OK) {
+ false) == 0) {
wlc_phy_savecal_nphy(pi);
}
@@ -24052,7 +24014,6 @@
break;
default:
- ASSERT(0);
wlc_phy_cal_perical_mphase_reset(pi);
break;
}
@@ -24116,7 +24077,7 @@
void *tbl_ptr;
bool ladder_updated[2];
u8 mphase_cal_lastphase = 0;
- int bcmerror = BCME_OK;
+ int bcmerror = 0;
bool phyhang_avoid_state = false;
u16 tbl_tx_iqlo_cal_loft_ladder_20[] = {
@@ -24242,13 +24203,13 @@
if (pi->mphase_cal_phase_id > MPHASE_CAL_STATE_TXPHASE0) {
wlc_phy_runsamples_nphy(pi, phy_bw * 8, 0xffff, 0, 1, 0, false);
- bcmerror = BCME_OK;
+ bcmerror = 0;
} else {
bcmerror =
wlc_phy_tx_tone_nphy(pi, tone_freq, max_val, 1, 0, false);
}
- if (bcmerror == BCME_OK) {
+ if (bcmerror == 0) {
if (pi->mphase_cal_phase_id > MPHASE_CAL_STATE_TXPHASE0) {
tbl_ptr = pi->mphase_txcal_bestcoeffs;
@@ -24361,7 +24322,9 @@
SPINWAIT(((read_phy_reg(pi, 0xc0) & 0xc000) != 0),
20000);
- ASSERT((read_phy_reg(pi, 0xc0) & 0xc000) == 0);
+ if (WARN(read_phy_reg(pi, 0xc0) & 0xc000,
+ "HW error: txiq calib"))
+ return -EIO;
wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_IQLOCAL,
tbl_len, 96, 16, tbl_buf);
@@ -24468,8 +24431,6 @@
{
u16 tbl_buf[7];
- ASSERT(NREV_LT(pi->pubpi.phy_rev, 2));
-
if ((pi->nphy_txiqlocal_chanspec == pi->radio_chanspec) &&
(pi->nphy_txiqlocal_coeffsvalid)) {
wlc_phy_table_read_nphy(pi, NPHY_TBL_ID_IQLOCAL,
@@ -24544,10 +24505,11 @@
SPINWAIT(((read_phy_reg(pi, 0x129) & NPHY_IqestCmd_iqstart) != 0),
10000);
- ASSERT((read_phy_reg(pi, 0x129) & NPHY_IqestCmd_iqstart) == 0);
+ if (WARN(read_phy_reg(pi, 0x129) & NPHY_IqestCmd_iqstart,
+ "HW error: rxiq est"))
+ return;
if ((read_phy_reg(pi, 0x129) & NPHY_IqestCmd_iqstart) == 0) {
- ASSERT(pi->pubpi.phy_corenum <= PHY_CORE_MAX);
for (core = 0; core < pi->pubpi.phy_corenum; core++) {
est[core].i_pwr =
(read_phy_reg(pi, NPHY_IqestipwrAccHi(core)) << 16)
@@ -24572,7 +24534,7 @@
u32 ii = 0, qq = 0;
s16 iq_nbits, qq_nbits, brsh, arsh;
s32 a, b, temp;
- int bcmerror = BCME_OK;
+ int bcmerror = 0;
uint cal_retry = 0;
if (core_mask == 0x0)
@@ -24602,7 +24564,7 @@
}
if ((ii + qq) < NPHY_MIN_RXIQ_PWR) {
- bcmerror = BCME_ERROR;
+ bcmerror = -EBADE;
break;
}
@@ -24614,14 +24576,14 @@
a = (-(iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
temp = (s32) (ii >> arsh);
if (temp == 0) {
- bcmerror = BCME_ERROR;
+ bcmerror = -EBADE;
break;
}
} else {
a = (-(iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
temp = (s32) (ii << -arsh);
if (temp == 0) {
- bcmerror = BCME_ERROR;
+ bcmerror = -EBADE;
break;
}
}
@@ -24633,20 +24595,20 @@
b = (qq << (31 - qq_nbits));
temp = (s32) (ii >> brsh);
if (temp == 0) {
- bcmerror = BCME_ERROR;
+ bcmerror = -EBADE;
break;
}
} else {
b = (qq << (31 - qq_nbits));
temp = (s32) (ii << -brsh);
if (temp == 0) {
- bcmerror = BCME_ERROR;
+ bcmerror = -EBADE;
break;
}
}
b /= temp;
b -= a * a;
- b = (s32) wlc_phy_sqrt_int((u32) b);
+ b = (s32) int_sqrt((unsigned long) b);
b -= (1 << 10);
if ((curr_core == PHY_CORE_0) && (core_mask & 0x1)) {
@@ -24671,7 +24633,7 @@
}
}
- if (bcmerror != BCME_OK) {
+ if (bcmerror != 0) {
printk("%s: Failed, cnt = %d\n", __func__, cal_retry);
if (cal_retry < CAL_RETRY_CNT) {
@@ -25451,7 +25413,7 @@
break;
default:
- ASSERT(0);
+ break;
}
if ((curr_gaintbl_index < 0) ||
@@ -25916,7 +25878,7 @@
wlc_phy_stay_in_carriersearch_nphy(pi, false);
- return BCME_OK;
+ return 0;
}
static int
@@ -25941,7 +25903,7 @@
u16 cal_gain[2];
nphy_iqcal_params_t cal_params[2];
u8 phy_bw;
- int bcmerror = BCME_OK;
+ int bcmerror = 0;
bool first_playtone = true;
wlc_phy_stay_in_carriersearch_nphy(pi, true);
@@ -26091,7 +26053,7 @@
0, 0, 0, true);
}
- if (bcmerror == BCME_OK) {
+ if (bcmerror == 0) {
if (gain_pass < 3) {
wlc_phy_rx_iq_est_nphy(pi, est,
@@ -26114,7 +26076,7 @@
wlc_phy_stopplayback_nphy(pi);
}
- if (bcmerror != BCME_OK)
+ if (bcmerror != 0)
break;
}
@@ -26130,7 +26092,7 @@
0xa7, orig_AfectrlCore);
write_phy_reg(pi, 0xa2, orig_RfseqCoreActv);
- if (bcmerror != BCME_OK)
+ if (bcmerror != 0)
break;
}
@@ -26270,8 +26232,6 @@
tx_pwrctrl_tbl =
nphy_tpc_txgain_ipa_2g_2057rev7;
- } else {
- ASSERT(0);
}
} else if (NREV_IS(pi->pubpi.phy_rev, 6)) {
@@ -26303,8 +26263,6 @@
tx_pwrctrl_tbl =
nphy_tpc_txgain_ipa_5g_2057rev7;
- } else {
- ASSERT(0);
}
} else {
@@ -26347,8 +26305,6 @@
|| (pi->pubpi.radiorev == 6)) {
mixgain = 0x00;
- } else {
- ASSERT(0);
}
} else {
@@ -26361,8 +26317,6 @@
|| (pi->pubpi.radiorev == 8)) {
mixgain = 0x0;
- } else {
- ASSERT(0);
}
}
@@ -26464,8 +26418,6 @@
WRITE_RADIO_REG3(pi, RADIO_2057, TX, core,
TXRXCOUPLE_2G_ATTEN, 0xf0);
- } else {
- ASSERT(0);
}
WRITE_RADIO_REG3(pi, RADIO_2057, TX, off_core,
@@ -26724,8 +26676,6 @@
u32 *buf, *src, *dst, sz;
sz = end - start + 1;
- ASSERT(end > start);
- ASSERT(end < NPHY_PAPD_EPS_TBL_SIZE);
buf = kmalloc(2 * sizeof(u32) * NPHY_PAPD_EPS_TBL_SIZE, GFP_ATOMIC);
if (NULL == buf) {
@@ -26787,8 +26737,6 @@
phy_a7 = (core == PHY_CORE_0) ? 1 : 0;
- ASSERT((cal_mode == CAL_FULL) || (cal_mode == CAL_GCTRL)
- || (cal_mode == CAL_SOFT));
phy_a6 = ((cal_mode == CAL_GCTRL)
|| (cal_mode == CAL_SOFT)) ? true : false;
@@ -27333,8 +27281,6 @@
nphy_papd_cal_gain_index
[phy_b5], phy_b5);
- } else {
- ASSERT(0);
}
phy_b1[phy_b5].gains.pad[phy_b5] =
@@ -27417,8 +27363,6 @@
-(nphy_papd_padgain_dlt_2g_2057rev7
[phy_b8]
+ 1) / 2;
- } else {
- ASSERT(0);
}
} else {
phy_b7 = phy_b1[phy_b5].gains.pga[phy_b5];
@@ -27435,8 +27379,6 @@
-(nphy_papd_pgagain_dlt_5g_2057rev7
[phy_b7]
+ 1) / 2;
- } else {
- ASSERT(0);
}
phy_b10 = -9;
@@ -27536,8 +27478,6 @@
u8 txpi[2], chan_freq_range;
s32 rfpwr_offset;
- ASSERT(pi->nphy_txpwrctrl == PHY_TPC_HW_OFF);
-
if (pi->phyhang_avoid)
wlc_phy_stay_in_carriersearch_nphy(pi, true);
@@ -29179,7 +29119,6 @@
*max_pwr = pi->tx_srom_max_rate_5g_hi[txp_rate_idx];
break;
default:
- ASSERT(0);
*max_pwr = pi->tx_srom_max_rate_2g[txp_rate_idx];
break;
}
@@ -29191,8 +29130,6 @@
{
u16 clip_off[] = { 0xffff, 0xffff };
- ASSERT(0 == (R_REG(&pi->regs->maccontrol) & MCTL_EN_MAC));
-
if (enable) {
if (pi->nphy_deaf_count == 0) {
pi->classifier_state =
@@ -29207,8 +29144,6 @@
wlc_phy_resetcca_nphy(pi);
} else {
- ASSERT(pi->nphy_deaf_count > 0);
-
pi->nphy_deaf_count--;
if (pi->nphy_deaf_count == 0) {
diff --git a/drivers/staging/brcm80211/brcmsmac/phy/wlc_phy_qmath.c b/drivers/staging/brcm80211/brcmsmac/phy/wlc_phy_qmath.c
new file mode 100644
index 0000000..c98176f
--- /dev/null
+++ b/drivers/staging/brcm80211/brcmsmac/phy/wlc_phy_qmath.c
@@ -0,0 +1,296 @@
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#include <linux/types.h>
+
+#include "wlc_phy_qmath.h"
+
+/*
+Description: This function make 16 bit unsigned multiplication. To fit the output into
+16 bits the 32 bit multiplication result is right shifted by 16 bits.
+*/
+u16 qm_mulu16(u16 op1, u16 op2)
+{
+ return (u16) (((u32) op1 * (u32) op2) >> 16);
+}
+
+/*
+Description: This function make 16 bit multiplication and return the result in 16 bits.
+To fit the multiplication result into 16 bits the multiplication result is right shifted by
+15 bits. Right shifting 15 bits instead of 16 bits is done to remove the extra sign bit formed
+due to the multiplication.
+When both the 16bit inputs are 0x8000 then the output is saturated to 0x7fffffff.
+*/
+s16 qm_muls16(s16 op1, s16 op2)
+{
+ s32 result;
+ if (op1 == (s16) 0x8000 && op2 == (s16) 0x8000) {
+ result = 0x7fffffff;
+ } else {
+ result = ((s32) (op1) * (s32) (op2));
+ }
+ return (s16) (result >> 15);
+}
+
+/*
+Description: This function add two 32 bit numbers and return the 32bit result.
+If the result overflow 32 bits, the output will be saturated to 32bits.
+*/
+s32 qm_add32(s32 op1, s32 op2)
+{
+ s32 result;
+ result = op1 + op2;
+ if (op1 < 0 && op2 < 0 && result > 0) {
+ result = 0x80000000;
+ } else if (op1 > 0 && op2 > 0 && result < 0) {
+ result = 0x7fffffff;
+ }
+ return result;
+}
+
+/*
+Description: This function add two 16 bit numbers and return the 16bit result.
+If the result overflow 16 bits, the output will be saturated to 16bits.
+*/
+s16 qm_add16(s16 op1, s16 op2)
+{
+ s16 result;
+ s32 temp = (s32) op1 + (s32) op2;
+ if (temp > (s32) 0x7fff) {
+ result = (s16) 0x7fff;
+ } else if (temp < (s32) 0xffff8000) {
+ result = (s16) 0xffff8000;
+ } else {
+ result = (s16) temp;
+ }
+ return result;
+}
+
+/*
+Description: This function make 16 bit subtraction and return the 16bit result.
+If the result overflow 16 bits, the output will be saturated to 16bits.
+*/
+s16 qm_sub16(s16 op1, s16 op2)
+{
+ s16 result;
+ s32 temp = (s32) op1 - (s32) op2;
+ if (temp > (s32) 0x7fff) {
+ result = (s16) 0x7fff;
+ } else if (temp < (s32) 0xffff8000) {
+ result = (s16) 0xffff8000;
+ } else {
+ result = (s16) temp;
+ }
+ return result;
+}
+
+/*
+Description: This function make a 32 bit saturated left shift when the specified shift
+is +ve. This function will make a 32 bit right shift when the specified shift is -ve.
+This function return the result after shifting operation.
+*/
+s32 qm_shl32(s32 op, int shift)
+{
+ int i;
+ s32 result;
+ result = op;
+ if (shift > 31)
+ shift = 31;
+ else if (shift < -31)
+ shift = -31;
+ if (shift >= 0) {
+ for (i = 0; i < shift; i++) {
+ result = qm_add32(result, result);
+ }
+ } else {
+ result = result >> (-shift);
+ }
+ return result;
+}
+
+/*
+Description: This function make a 16 bit saturated left shift when the specified shift
+is +ve. This function will make a 16 bit right shift when the specified shift is -ve.
+This function return the result after shifting operation.
+*/
+s16 qm_shl16(s16 op, int shift)
+{
+ int i;
+ s16 result;
+ result = op;
+ if (shift > 15)
+ shift = 15;
+ else if (shift < -15)
+ shift = -15;
+ if (shift > 0) {
+ for (i = 0; i < shift; i++) {
+ result = qm_add16(result, result);
+ }
+ } else {
+ result = result >> (-shift);
+ }
+ return result;
+}
+
+/*
+Description: This function make a 16 bit right shift when shift is +ve.
+This function make a 16 bit saturated left shift when shift is -ve. This function
+return the result of the shift operation.
+*/
+s16 qm_shr16(s16 op, int shift)
+{
+ return qm_shl16(op, -shift);
+}
+
+/*
+Description: This function return the number of redundant sign bits in a 32 bit number.
+Example: qm_norm32(0x00000080) = 23
+*/
+s16 qm_norm32(s32 op)
+{
+ u16 u16extraSignBits;
+ if (op == 0) {
+ return 31;
+ } else {
+ u16extraSignBits = 0;
+ while ((op >> 31) == (op >> 30)) {
+ u16extraSignBits++;
+ op = op << 1;
+ }
+ }
+ return u16extraSignBits;
+}
+
+/* This table is log2(1+(i/32)) where i=[0:1:31], in q.15 format */
+static const s16 log_table[] = {
+ 0,
+ 1455,
+ 2866,
+ 4236,
+ 5568,
+ 6863,
+ 8124,
+ 9352,
+ 10549,
+ 11716,
+ 12855,
+ 13968,
+ 15055,
+ 16117,
+ 17156,
+ 18173,
+ 19168,
+ 20143,
+ 21098,
+ 22034,
+ 22952,
+ 23852,
+ 24736,
+ 25604,
+ 26455,
+ 27292,
+ 28114,
+ 28922,
+ 29717,
+ 30498,
+ 31267,
+ 32024
+};
+
+#define LOG_TABLE_SIZE 32 /* log_table size */
+#define LOG2_LOG_TABLE_SIZE 5 /* log2(log_table size) */
+#define Q_LOG_TABLE 15 /* qformat of log_table */
+#define LOG10_2 19728 /* log10(2) in q.16 */
+
+/*
+Description:
+This routine takes the input number N and its q format qN and compute
+the log10(N). This routine first normalizes the input no N. Then N is in mag*(2^x) format.
+mag is any number in the range 2^30-(2^31 - 1). Then log2(mag * 2^x) = log2(mag) + x is computed.
+From that log10(mag * 2^x) = log2(mag * 2^x) * log10(2) is computed.
+This routine looks the log2 value in the table considering LOG2_LOG_TABLE_SIZE+1 MSBs.
+As the MSB is always 1, only next LOG2_OF_LOG_TABLE_SIZE MSBs are used for table lookup.
+Next 16 MSBs are used for interpolation.
+Inputs:
+N - number to which log10 has to be found.
+qN - q format of N
+log10N - address where log10(N) will be written.
+qLog10N - address where log10N qformat will be written.
+Note/Problem:
+For accurate results input should be in normalized or near normalized form.
+*/
+void qm_log10(s32 N, s16 qN, s16 *log10N, s16 *qLog10N)
+{
+ s16 s16norm, s16tableIndex, s16errorApproximation;
+ u16 u16offset;
+ s32 s32log;
+
+ /* normalize the N. */
+ s16norm = qm_norm32(N);
+ N = N << s16norm;
+
+ /* The qformat of N after normalization.
+ * -30 is added to treat the no as between 1.0 to 2.0
+ * i.e. after adding the -30 to the qformat the decimal point will be
+ * just rigtht of the MSB. (i.e. after sign bit and 1st MSB). i.e.
+ * at the right side of 30th bit.
+ */
+ qN = qN + s16norm - 30;
+
+ /* take the table index as the LOG2_OF_LOG_TABLE_SIZE bits right of the MSB */
+ s16tableIndex = (s16) (N >> (32 - (2 + LOG2_LOG_TABLE_SIZE)));
+
+ /* remove the MSB. the MSB is always 1 after normalization. */
+ s16tableIndex =
+ s16tableIndex & (s16) ((1 << LOG2_LOG_TABLE_SIZE) - 1);
+
+ /* remove the (1+LOG2_OF_LOG_TABLE_SIZE) MSBs in the N. */
+ N = N & ((1 << (32 - (2 + LOG2_LOG_TABLE_SIZE))) - 1);
+
+ /* take the offset as the 16 MSBS after table index.
+ */
+ u16offset = (u16) (N >> (32 - (2 + LOG2_LOG_TABLE_SIZE + 16)));
+
+ /* look the log value in the table. */
+ s32log = log_table[s16tableIndex]; /* q.15 format */
+
+ /* interpolate using the offset. */
+ s16errorApproximation = (s16) qm_mulu16(u16offset, (u16) (log_table[s16tableIndex + 1] - log_table[s16tableIndex])); /* q.15 */
+
+ s32log = qm_add16((s16) s32log, s16errorApproximation); /* q.15 format */
+
+ /* adjust for the qformat of the N as
+ * log2(mag * 2^x) = log2(mag) + x
+ */
+ s32log = qm_add32(s32log, ((s32) -qN) << 15); /* q.15 format */
+
+ /* normalize the result. */
+ s16norm = qm_norm32(s32log);
+
+ /* bring all the important bits into lower 16 bits */
+ s32log = qm_shl32(s32log, s16norm - 16); /* q.15+s16norm-16 format */
+
+ /* compute the log10(N) by multiplying log2(N) with log10(2).
+ * as log10(mag * 2^x) = log2(mag * 2^x) * log10(2)
+ * log10N in q.15+s16norm-16+1 (LOG10_2 is in q.16)
+ */
+ *log10N = qm_muls16((s16) s32log, (s16) LOG10_2);
+
+ /* write the q format of the result. */
+ *qLog10N = 15 + s16norm - 16 + 1;
+
+ return;
+}
diff --git a/drivers/staging/brcm80211/brcmsmac/phy/wlc_phy_qmath.h b/drivers/staging/brcm80211/brcmsmac/phy/wlc_phy_qmath.h
new file mode 100644
index 0000000..3dcee1c
--- /dev/null
+++ b/drivers/staging/brcm80211/brcmsmac/phy/wlc_phy_qmath.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+#ifndef __QMATH_H__
+#define __QMATH_H__
+
+u16 qm_mulu16(u16 op1, u16 op2);
+
+s16 qm_muls16(s16 op1, s16 op2);
+
+s32 qm_add32(s32 op1, s32 op2);
+
+s16 qm_add16(s16 op1, s16 op2);
+
+s16 qm_sub16(s16 op1, s16 op2);
+
+s32 qm_shl32(s32 op, int shift);
+
+s16 qm_shl16(s16 op, int shift);
+
+s16 qm_shr16(s16 op, int shift);
+
+s16 qm_norm32(s32 op);
+
+void qm_log10(s32 N, s16 qN, s16 *log10N, s16 *qLog10N);
+
+#endif /* #ifndef __QMATH_H__ */
diff --git a/drivers/staging/brcm80211/brcmsmac/wl_dbg.h b/drivers/staging/brcm80211/brcmsmac/wl_dbg.h
index 54af257..5582de3 100644
--- a/drivers/staging/brcm80211/brcmsmac/wl_dbg.h
+++ b/drivers/staging/brcm80211/brcmsmac/wl_dbg.h
@@ -17,25 +17,19 @@
#ifndef _wl_dbg_h_
#define _wl_dbg_h_
+#include <linux/device.h> /* dev_err() */
+
/* wl_msg_level is a bit vector with defs in wlioctl.h */
extern u32 wl_msg_level;
-#define WL_NONE(fmt, args...) no_printk(fmt, ##args)
-
-#define WL_PRINT(level, fmt, args...) \
+#define BCMMSG(dev, fmt, args...) \
do { \
- if (wl_msg_level & level) \
- printk(fmt, ##args); \
+ if (wl_msg_level & WL_TRACE_VAL) \
+ wiphy_err(dev, "%s: " fmt, __func__, ##args); \
} while (0)
#ifdef BCMDBG
-#define WL_ERROR(fmt, args...) WL_PRINT(WL_ERROR_VAL, fmt, ##args)
-#define WL_TRACE(fmt, args...) WL_PRINT(WL_TRACE_VAL, fmt, ##args)
-#define WL_AMPDU(fmt, args...) WL_PRINT(WL_AMPDU_VAL, fmt, ##args)
-#define WL_FFPLD(fmt, args...) WL_PRINT(WL_FFPLD_VAL, fmt, ##args)
-
-#define WL_ERROR_ON() (wl_msg_level & WL_ERROR_VAL)
/* Extra message control for AMPDU debugging */
#define WL_AMPDU_UPDN_VAL 0x00000001 /* Config up/down related */
@@ -78,12 +72,6 @@
#else /* BCMDBG */
-#define WL_ERROR(fmt, args...) no_printk(fmt, ##args)
-#define WL_TRACE(fmt, args...) no_printk(fmt, ##args)
-#define WL_AMPDU(fmt, args...) no_printk(fmt, ##args)
-#define WL_FFPLD(fmt, args...) no_printk(fmt, ##args)
-
-#define WL_ERROR_ON() 0
#define WL_AMPDU_UPDN(fmt, args...) no_printk(fmt, ##args)
#define WL_AMPDU_RX(fmt, args...) no_printk(fmt, ##args)
@@ -99,4 +87,6 @@
#endif /* BCMDBG */
+#define WL_ERROR_ON() (wl_msg_level & WL_ERROR_VAL)
+
#endif /* _wl_dbg_h_ */
diff --git a/drivers/staging/brcm80211/brcmsmac/wl_export.h b/drivers/staging/brcm80211/brcmsmac/wl_export.h
index 9ff760f..0fe0b24 100644
--- a/drivers/staging/brcm80211/brcmsmac/wl_export.h
+++ b/drivers/staging/brcm80211/brcmsmac/wl_export.h
@@ -42,5 +42,6 @@
extern void wl_add_timer(struct wl_info *wl, struct wl_timer *timer, uint ms,
int periodic);
extern bool wl_del_timer(struct wl_info *wl, struct wl_timer *timer);
+extern void wl_msleep(struct wl_info *wl, uint ms);
#endif /* _wl_export_h_ */
diff --git a/drivers/staging/brcm80211/brcmsmac/wl_mac80211.c b/drivers/staging/brcm80211/brcmsmac/wl_mac80211.c
index c1b07ae..6c6236c 100644
--- a/drivers/staging/brcm80211/brcmsmac/wl_mac80211.c
+++ b/drivers/staging/brcm80211/brcmsmac/wl_mac80211.c
@@ -30,6 +30,7 @@
#include <bcmdefs.h>
#include <bcmwifi.h>
#include <bcmutils.h>
+#include <bcmnvram.h>
#include <pcicfg.h>
#include <wlioctl.h>
#include <sbhnddma.h>
@@ -48,6 +49,8 @@
#include "wl_ucode.h"
#include "wl_mac80211.h"
+#define N_TX_QUEUES 4 /* #tx queues on mac80211<->driver interface */
+
static void wl_timer(unsigned long data);
static void _wl_timer(struct wl_timer *t);
@@ -81,6 +84,7 @@
const struct pci_device_id *ent);
static void wl_remove(struct pci_dev *pdev);
static void wl_free(struct wl_info *wl);
+static void wl_set_basic_rate(struct wl_rateset *rs, u16 rate, bool is_br);
MODULE_AUTHOR("Broadcom Corporation");
MODULE_DESCRIPTION("Broadcom 802.11n wireless LAN driver.");
@@ -129,7 +133,6 @@
static void wl_ops_set_tsf(struct ieee80211_hw *hw, u64 tsf);
static int wl_ops_get_stats(struct ieee80211_hw *hw,
struct ieee80211_low_level_stats *stats);
-static int wl_ops_set_rts_threshold(struct ieee80211_hw *hw, u32 value);
static void wl_ops_sta_notify(struct ieee80211_hw *hw,
struct ieee80211_vif *vif,
enum sta_notify_cmd cmd,
@@ -147,6 +150,7 @@
struct ieee80211_sta *sta, u16 tid, u16 *ssn,
u8 buf_size);
static void wl_ops_rfkill_poll(struct ieee80211_hw *hw);
+static void wl_ops_flush(struct ieee80211_hw *hw, bool drop);
static void wl_ops_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
{
@@ -154,7 +158,7 @@
WL_LOCK(wl);
if (!wl->pub->up) {
- WL_ERROR("ops->tx called while down\n");
+ wiphy_err(wl->wiphy, "ops->tx called while down\n");
kfree_skb(skb);
goto done;
}
@@ -169,7 +173,6 @@
bool blocked;
/*
struct ieee80211_channel *curchan = hw->conf.channel;
- WL_NONE("%s : Initial channel: %d\n", __func__, curchan->hw_value);
*/
ieee80211_wake_queues(hw);
@@ -184,10 +187,6 @@
static void wl_ops_stop(struct ieee80211_hw *hw)
{
-#ifdef BRCMDBG
- struct wl_info *wl = hw->priv;
- ASSERT(wl);
-#endif /*BRCMDBG*/
ieee80211_stop_queues(hw);
}
@@ -203,8 +202,8 @@
vif->type != NL80211_IFTYPE_STATION &&
vif->type != NL80211_IFTYPE_WDS &&
vif->type != NL80211_IFTYPE_ADHOC) {
- WL_ERROR("%s: Attempt to add type %d, only STA for now\n",
- __func__, vif->type);
+ wiphy_err(hw->wiphy, "%s: Attempt to add type %d, only"
+ " STA for now\n", __func__, vif->type);
return -EOPNOTSUPP;
}
@@ -214,7 +213,8 @@
WL_UNLOCK(wl);
if (err != 0) {
- WL_ERROR("%s: wl_up() returned %d\n", __func__, err);
+ wiphy_err(hw->wiphy, "%s: wl_up() returned %d\n", __func__,
+ err);
}
return err;
}
@@ -249,7 +249,8 @@
break;
case NL80211_CHAN_HT40MINUS:
case NL80211_CHAN_HT40PLUS:
- WL_ERROR("%s: Need to implement 40 Mhz Channels!\n", __func__);
+ wiphy_err(hw->wiphy,
+ "%s: Need to implement 40 Mhz Channels!\n", __func__);
err = 1;
break;
}
@@ -265,39 +266,41 @@
struct wl_info *wl = HW_TO_WL(hw);
int err = 0;
int new_int;
+ struct wiphy *wiphy = hw->wiphy;
WL_LOCK(wl);
if (changed & IEEE80211_CONF_CHANGE_LISTEN_INTERVAL) {
if (wlc_iovar_setint
(wl->wlc, "bcn_li_bcn", conf->listen_interval)) {
- WL_ERROR("%s: Error setting listen_interval\n",
- __func__);
+ wiphy_err(wiphy, "%s: Error setting listen_interval\n",
+ __func__);
err = -EIO;
goto config_out;
}
wlc_iovar_getint(wl->wlc, "bcn_li_bcn", &new_int);
- ASSERT(new_int == conf->listen_interval);
}
if (changed & IEEE80211_CONF_CHANGE_MONITOR)
- WL_ERROR("%s: change monitor mode: %s (implement)\n", __func__,
- conf->flags & IEEE80211_CONF_MONITOR ?
- "true" : "false");
+ wiphy_err(wiphy, "%s: change monitor mode: %s (implement)\n",
+ __func__, conf->flags & IEEE80211_CONF_MONITOR ?
+ "true" : "false");
if (changed & IEEE80211_CONF_CHANGE_PS)
- WL_ERROR("%s: change power-save mode: %s (implement)\n",
- __func__, conf->flags & IEEE80211_CONF_PS ?
- "true" : "false");
+ wiphy_err(wiphy, "%s: change power-save mode: %s (implement)\n",
+ __func__, conf->flags & IEEE80211_CONF_PS ?
+ "true" : "false");
if (changed & IEEE80211_CONF_CHANGE_POWER) {
if (wlc_iovar_setint
(wl->wlc, "qtxpower", conf->power_level * 4)) {
- WL_ERROR("%s: Error setting power_level\n", __func__);
+ wiphy_err(wiphy, "%s: Error setting power_level\n",
+ __func__);
err = -EIO;
goto config_out;
}
wlc_iovar_getint(wl->wlc, "qtxpower", &new_int);
if (new_int != (conf->power_level * 4))
- WL_ERROR("%s: Power level req != actual, %d %d\n",
- __func__, conf->power_level * 4, new_int);
+ wiphy_err(wiphy, "%s: Power level req != actual, %d %d"
+ "\n", __func__, conf->power_level * 4,
+ new_int);
}
if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
err = ieee_set_channel(hw, conf->channel, conf->channel_type);
@@ -306,13 +309,13 @@
if (wlc_set
(wl->wlc, WLC_SET_SRL,
conf->short_frame_max_tx_count) < 0) {
- WL_ERROR("%s: Error setting srl\n", __func__);
+ wiphy_err(wiphy, "%s: Error setting srl\n", __func__);
err = -EIO;
goto config_out;
}
if (wlc_set(wl->wlc, WLC_SET_LRL, conf->long_frame_max_tx_count)
< 0) {
- WL_ERROR("%s: Error setting lrl\n", __func__);
+ wiphy_err(wiphy, "%s: Error setting lrl\n", __func__);
err = -EIO;
goto config_out;
}
@@ -329,25 +332,18 @@
struct ieee80211_bss_conf *info, u32 changed)
{
struct wl_info *wl = HW_TO_WL(hw);
+ struct wiphy *wiphy = hw->wiphy;
int val;
if (changed & BSS_CHANGED_ASSOC) {
/* association status changed (associated/disassociated)
* also implies a change in the AID.
*/
- WL_ERROR("%s: %s: %sassociated\n", KBUILD_MODNAME, __func__,
- info->assoc ? "" : "dis");
+ wiphy_err(wiphy, "%s: %s: %sassociated\n", KBUILD_MODNAME,
+ __func__, info->assoc ? "" : "dis");
+ WL_LOCK(wl);
wlc_associate_upd(wl->wlc, info->assoc);
- }
- if (changed & BSS_CHANGED_ERP_CTS_PROT) {
- /* CTS protection changed */
- WL_ERROR("%s: use_cts_prot: %s (implement)\n", __func__,
- info->use_cts_prot ? "true" : "false");
- }
- if (changed & BSS_CHANGED_ERP_PREAMBLE) {
- /* preamble changed */
- WL_ERROR("%s: short preamble: %s (implement)\n", __func__,
- info->use_short_preamble ? "true" : "false");
+ WL_UNLOCK(wl);
}
if (changed & BSS_CHANGED_ERP_SLOT) {
/* slot timing changed */
@@ -363,29 +359,57 @@
if (changed & BSS_CHANGED_HT) {
/* 802.11n parameters changed */
u16 mode = info->ht_operation_mode;
- WL_NONE("%s: HT mode: 0x%04X\n", __func__, mode);
+
+ WL_LOCK(wl);
wlc_protection_upd(wl->wlc, WLC_PROT_N_CFG,
mode & IEEE80211_HT_OP_MODE_PROTECTION);
wlc_protection_upd(wl->wlc, WLC_PROT_N_NONGF,
mode & IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
wlc_protection_upd(wl->wlc, WLC_PROT_N_OBSS,
mode & IEEE80211_HT_OP_MODE_NON_HT_STA_PRSNT);
+ WL_UNLOCK(wl);
}
if (changed & BSS_CHANGED_BASIC_RATES) {
- /* Basic rateset changed */
- WL_ERROR("%s: Need to change Basic Rates: 0x%x (implement)\n",
- __func__, (u32) info->basic_rates);
+ struct ieee80211_supported_band *bi;
+ u32 br_mask, i;
+ u16 rate;
+ struct wl_rateset rs;
+ int error;
+
+ /* retrieve the current rates */
+ WL_LOCK(wl);
+ error = wlc_ioctl(wl->wlc, WLC_GET_CURR_RATESET,
+ &rs, sizeof(rs), NULL);
+ WL_UNLOCK(wl);
+ if (error) {
+ wiphy_err(wiphy, "%s: retrieve rateset failed: %d\n",
+ __func__, error);
+ return;
+ }
+ br_mask = info->basic_rates;
+ bi = hw->wiphy->bands[wlc_get_curband(wl->wlc)];
+ for (i = 0; i < bi->n_bitrates; i++) {
+ /* convert to internal rate value */
+ rate = (bi->bitrates[i].bitrate << 1) / 10;
+
+ /* set/clear basic rate flag */
+ wl_set_basic_rate(&rs, rate, br_mask & 1);
+ br_mask >>= 1;
+ }
+
+ /* update the rate set */
+ WL_LOCK(wl);
+ wlc_ioctl(wl->wlc, WLC_SET_RATESET, &rs, sizeof(rs), NULL);
+ WL_UNLOCK(wl);
}
if (changed & BSS_CHANGED_BEACON_INT) {
/* Beacon interval changed */
- WL_NONE("%s: Beacon Interval: %d\n",
- __func__, info->beacon_int);
+ WL_LOCK(wl);
wlc_set(wl->wlc, WLC_SET_BCNPRD, info->beacon_int);
+ WL_UNLOCK(wl);
}
if (changed & BSS_CHANGED_BSSID) {
/* BSSID changed, for whatever reason (IBSS and managed mode) */
- WL_NONE("%s: new BSSID: aid %d bss:%pM\n", __func__,
- info->aid, info->bssid);
WL_LOCK(wl);
wlc_set_addrmatch(wl->wlc, RCM_BSSID_OFFSET,
info->bssid);
@@ -393,41 +417,42 @@
}
if (changed & BSS_CHANGED_BEACON) {
/* Beacon data changed, retrieve new beacon (beaconing modes) */
- WL_ERROR("%s: beacon changed\n", __func__);
+ wiphy_err(wiphy, "%s: beacon changed\n", __func__);
}
if (changed & BSS_CHANGED_BEACON_ENABLED) {
/* Beaconing should be enabled/disabled (beaconing modes) */
- WL_ERROR("%s: Beacon enabled: %s\n", __func__,
- info->enable_beacon ? "true" : "false");
+ wiphy_err(wiphy, "%s: Beacon enabled: %s\n", __func__,
+ info->enable_beacon ? "true" : "false");
}
if (changed & BSS_CHANGED_CQM) {
/* Connection quality monitor config changed */
- WL_ERROR("%s: cqm change: threshold %d, hys %d (implement)\n",
- __func__, info->cqm_rssi_thold, info->cqm_rssi_hyst);
+ wiphy_err(wiphy, "%s: cqm change: threshold %d, hys %d "
+ " (implement)\n", __func__, info->cqm_rssi_thold,
+ info->cqm_rssi_hyst);
}
if (changed & BSS_CHANGED_IBSS) {
/* IBSS join status changed */
- WL_ERROR("%s: IBSS joined: %s (implement)\n", __func__,
- info->ibss_joined ? "true" : "false");
+ wiphy_err(wiphy, "%s: IBSS joined: %s (implement)\n", __func__,
+ info->ibss_joined ? "true" : "false");
}
if (changed & BSS_CHANGED_ARP_FILTER) {
/* Hardware ARP filter address list or state changed */
- WL_ERROR("%s: arp filtering: enabled %s, count %d (implement)\n",
- __func__, info->arp_filter_enabled ? "true" : "false",
- info->arp_addr_cnt);
+ wiphy_err(wiphy, "%s: arp filtering: enabled %s, count %d"
+ " (implement)\n", __func__, info->arp_filter_enabled ?
+ "true" : "false", info->arp_addr_cnt);
}
if (changed & BSS_CHANGED_QOS) {
/*
* QoS for this association was enabled/disabled.
* Note that it is only ever disabled for station mode.
*/
- WL_ERROR("%s: qos enabled: %s (implement)\n", __func__,
- info->qos ? "true" : "false");
+ wiphy_err(wiphy, "%s: qos enabled: %s (implement)\n", __func__,
+ info->qos ? "true" : "false");
}
if (changed & BSS_CHANGED_IDLE) {
/* Idle changed for this BSS/interface */
- WL_ERROR("%s: BSS idle: %s (implement)\n", __func__,
- info->idle ? "true" : "false");
+ wiphy_err(wiphy, "%s: BSS idle: %s (implement)\n", __func__,
+ info->idle ? "true" : "false");
}
return;
}
@@ -438,23 +463,23 @@
unsigned int *total_flags, u64 multicast)
{
struct wl_info *wl = hw->priv;
+ struct wiphy *wiphy = hw->wiphy;
changed_flags &= MAC_FILTERS;
*total_flags &= MAC_FILTERS;
if (changed_flags & FIF_PROMISC_IN_BSS)
- WL_ERROR("FIF_PROMISC_IN_BSS\n");
+ wiphy_err(wiphy, "FIF_PROMISC_IN_BSS\n");
if (changed_flags & FIF_ALLMULTI)
- WL_ERROR("FIF_ALLMULTI\n");
+ wiphy_err(wiphy, "FIF_ALLMULTI\n");
if (changed_flags & FIF_FCSFAIL)
- WL_ERROR("FIF_FCSFAIL\n");
+ wiphy_err(wiphy, "FIF_FCSFAIL\n");
if (changed_flags & FIF_PLCPFAIL)
- WL_ERROR("FIF_PLCPFAIL\n");
+ wiphy_err(wiphy, "FIF_PLCPFAIL\n");
if (changed_flags & FIF_CONTROL)
- WL_ERROR("FIF_CONTROL\n");
+ wiphy_err(wiphy, "FIF_CONTROL\n");
if (changed_flags & FIF_OTHER_BSS)
- WL_ERROR("FIF_OTHER_BSS\n");
+ wiphy_err(wiphy, "FIF_OTHER_BSS\n");
if (changed_flags & FIF_BCN_PRBRESP_PROMISC) {
- WL_NONE("FIF_BCN_PRBRESP_PROMISC\n");
WL_LOCK(wl);
if (*total_flags & FIF_BCN_PRBRESP_PROMISC) {
wl->pub->mac80211_state |= MAC80211_PROMISC_BCNS;
@@ -471,14 +496,12 @@
static int
wl_ops_set_tim(struct ieee80211_hw *hw, struct ieee80211_sta *sta, bool set)
{
- WL_NONE("%s: Enter\n", __func__);
return 0;
}
static void wl_ops_sw_scan_start(struct ieee80211_hw *hw)
{
struct wl_info *wl = hw->priv;
- WL_NONE("Scan Start\n");
WL_LOCK(wl);
wlc_scan_start(wl->wlc);
WL_UNLOCK(wl);
@@ -488,7 +511,6 @@
static void wl_ops_sw_scan_complete(struct ieee80211_hw *hw)
{
struct wl_info *wl = hw->priv;
- WL_NONE("Scan Complete\n");
WL_LOCK(wl);
wlc_scan_stop(wl->wlc);
WL_UNLOCK(wl);
@@ -497,7 +519,7 @@
static void wl_ops_set_tsf(struct ieee80211_hw *hw, u64 tsf)
{
- WL_ERROR("%s: Enter\n", __func__);
+ wiphy_err(hw->wiphy, "%s: Enter\n", __func__);
return;
}
@@ -510,20 +532,10 @@
WL_LOCK(wl);
cnt = wl->pub->_cnt;
- stats->dot11ACKFailureCount = cnt->txnoack;
- stats->dot11RTSFailureCount = cnt->txnocts;
- stats->dot11FCSErrorCount = cnt->rxcrc;
- stats->dot11RTSSuccessCount = cnt->txrts;
- WL_UNLOCK(wl);
- return 0;
-}
-
-static int wl_ops_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
-{
- struct wl_info *wl = hw->priv;
-
- WL_LOCK(wl);
- wlc_iovar_setint(wl->wlc, "rtsthresh", value & 0xFFFF);
+ stats->dot11ACKFailureCount = 0;
+ stats->dot11RTSFailureCount = 0;
+ stats->dot11FCSErrorCount = 0;
+ stats->dot11RTSSuccessCount = 0;
WL_UNLOCK(wl);
return 0;
}
@@ -532,10 +544,10 @@
wl_ops_sta_notify(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
enum sta_notify_cmd cmd, struct ieee80211_sta *sta)
{
- WL_NONE("%s: Enter\n", __func__);
switch (cmd) {
default:
- WL_ERROR("%s: Unknown cmd = %d\n", __func__, cmd);
+ wiphy_err(hw->wiphy, "%s: Unknown cmd = %d\n", __func__,
+ cmd);
break;
}
return;
@@ -547,12 +559,8 @@
{
struct wl_info *wl = hw->priv;
- WL_NONE("%s: Enter (WME config)\n", __func__);
- WL_NONE("queue %d, txop %d, cwmin %d, cwmax %d, aifs %d\n", queue,
- params->txop, params->cw_min, params->cw_max, params->aifs);
-
WL_LOCK(wl);
- wlc_wme_setparams(wl->wlc, queue, (void *)params, true);
+ wlc_wme_setparams(wl->wlc, queue, params, true);
WL_UNLOCK(wl);
return 0;
@@ -560,7 +568,7 @@
static u64 wl_ops_get_tsf(struct ieee80211_hw *hw)
{
- WL_ERROR("%s: Enter\n", __func__);
+ wiphy_err(hw->wiphy, "%s: Enter\n", __func__);
return 0;
}
@@ -585,7 +593,7 @@
wl->pub->global_ampdu = &(scb->scb_ampdu);
wl->pub->global_ampdu->scb = scb;
wl->pub->global_ampdu->max_pdu = 16;
- pktq_init(&scb->scb_ampdu.txq, AMPDU_MAX_SCB_TID,
+ bcm_pktq_init(&scb->scb_ampdu.txq, AMPDU_MAX_SCB_TID,
AMPDU_MAX_SCB_TID * PKTQ_LEN_DEFAULT);
sta->ht_cap.ht_supported = true;
@@ -603,7 +611,6 @@
wl_ops_sta_remove(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
struct ieee80211_sta *sta)
{
- WL_NONE("%s: Enter\n", __func__);
return 0;
}
@@ -614,27 +621,25 @@
struct ieee80211_sta *sta, u16 tid, u16 *ssn,
u8 buf_size)
{
-#if defined(BCMDBG)
struct scb *scb = (struct scb *)sta->drv_priv;
-#endif
struct wl_info *wl = hw->priv;
int status;
- ASSERT(scb->magic == SCB_MAGIC);
+ if (WARN_ON(scb->magic != SCB_MAGIC))
+ return -EIDRM;
switch (action) {
case IEEE80211_AMPDU_RX_START:
- WL_NONE("%s: action = IEEE80211_AMPDU_RX_START\n", __func__);
break;
case IEEE80211_AMPDU_RX_STOP:
- WL_NONE("%s: action = IEEE80211_AMPDU_RX_STOP\n", __func__);
break;
case IEEE80211_AMPDU_TX_START:
WL_LOCK(wl);
status = wlc_aggregatable(wl->wlc, tid);
WL_UNLOCK(wl);
if (!status) {
- /* WL_ERROR("START: tid %d is not agg' able, return FAILURE to stack\n", tid); */
- return -1;
+ wiphy_err(wl->wiphy, "START: tid %d is not agg\'able\n",
+ tid);
+ return -EINVAL;
}
/* XXX: Use the starting sequence number provided ... */
*ssn = 0;
@@ -650,11 +655,10 @@
case IEEE80211_AMPDU_TX_OPERATIONAL:
/* Not sure what to do here */
/* Power save wakeup */
- WL_NONE("%s: action = IEEE80211_AMPDU_TX_OPERATIONAL\n",
- __func__);
break;
default:
- WL_ERROR("%s: Invalid command, ignoring\n", __func__);
+ wiphy_err(wl->wiphy, "%s: Invalid command, ignoring\n",
+ __func__);
}
return 0;
@@ -669,10 +673,21 @@
blocked = wlc_check_radio_disabled(wl->wlc);
WL_UNLOCK(wl);
- WL_NONE("wl: rfkill_poll: %d\n", blocked);
wiphy_rfkill_set_hw_state(wl->pub->ieee_hw->wiphy, blocked);
}
+static void wl_ops_flush(struct ieee80211_hw *hw, bool drop)
+{
+ struct wl_info *wl = HW_TO_WL(hw);
+
+ no_printk("%s: drop = %s\n", __func__, drop ? "true" : "false");
+
+ /* wait for packet queue and dma fifos to run empty */
+ WL_LOCK(wl);
+ wlc_wait_for_tx_completion(wl->wlc, drop);
+ WL_UNLOCK(wl);
+}
+
static const struct ieee80211_ops wl_ops = {
.tx = wl_ops_tx,
.start = wl_ops_start,
@@ -687,7 +702,6 @@
.sw_scan_complete = wl_ops_sw_scan_complete,
.set_tsf = wl_ops_set_tsf,
.get_stats = wl_ops_get_stats,
- .set_rts_threshold = wl_ops_set_rts_threshold,
.sta_notify = wl_ops_sta_notify,
.conf_tx = wl_ops_conf_tx,
.get_tsf = wl_ops_get_tsf,
@@ -695,6 +709,7 @@
.sta_remove = wl_ops_sta_remove,
.ampdu_action = wl_ops_ampdu_action,
.rfkill_poll = wl_ops_rfkill_poll,
+ .flush = wl_ops_flush,
};
/*
@@ -702,8 +717,6 @@
*/
static int wl_set_hint(struct wl_info *wl, char *abbrev)
{
- WL_NONE("%s: Sending country code %c%c to MAC80211\n",
- __func__, abbrev[0], abbrev[1]);
return regulatory_hint(wl->pub->ieee_hw->wiphy, abbrev);
}
@@ -724,7 +737,7 @@
static struct wl_info *wl_attach(u16 vendor, u16 device, unsigned long regs,
uint bustype, void *btparam, uint irq)
{
- struct wl_info *wl;
+ struct wl_info *wl = NULL;
int unit, err;
unsigned long base_addr;
@@ -735,14 +748,16 @@
err = 0;
if (unit < 0) {
- WL_ERROR("wl%d: unit number overflow, exiting\n", unit);
return NULL;
}
/* allocate private info */
hw = pci_get_drvdata(btparam); /* btparam == pdev */
- wl = hw->priv;
- ASSERT(wl);
+ if (hw != NULL)
+ wl = hw->priv;
+ if (WARN_ON(hw == NULL) || WARN_ON(wl == NULL))
+ return NULL;
+ wl->wiphy = hw->wiphy;
atomic_set(&wl->callbacks, 0);
@@ -759,13 +774,13 @@
/* Do nothing */
} else {
bustype = PCI_BUS;
- WL_TRACE("force to PCI\n");
+ BCMMSG(wl->wiphy, "force to PCI\n");
}
wl->bcm_bustype = bustype;
wl->regsva = ioremap_nocache(base_addr, PCI_BAR0_WINSZ);
if (wl->regsva == NULL) {
- WL_ERROR("wl%d: ioremap() failed\n", unit);
+ wiphy_err(wl->wiphy, "wl%d: ioremap() failed\n", unit);
goto fail;
}
spin_lock_init(&wl->lock);
@@ -773,11 +788,11 @@
/* prepare ucode */
if (wl_request_fw(wl, (struct pci_dev *)btparam) < 0) {
- WL_ERROR("%s: Failed to find firmware usually in %s\n",
- KBUILD_MODNAME, "/lib/firmware/brcm");
+ wiphy_err(wl->wiphy, "%s: Failed to find firmware usually in "
+ "%s\n", KBUILD_MODNAME, "/lib/firmware/brcm");
wl_release_fw(wl);
wl_remove((struct pci_dev *)btparam);
- goto fail1;
+ return NULL;
}
/* common load-time initialization */
@@ -785,24 +800,22 @@
wl->regsva, wl->bcm_bustype, btparam, &err);
wl_release_fw(wl);
if (!wl->wlc) {
- WL_ERROR("%s: wlc_attach() failed with code %d\n",
- KBUILD_MODNAME, err);
+ wiphy_err(wl->wiphy, "%s: wlc_attach() failed with code %d\n",
+ KBUILD_MODNAME, err);
goto fail;
}
wl->pub = wlc_pub(wl->wlc);
wl->pub->ieee_hw = hw;
- ASSERT(wl->pub->ieee_hw);
- ASSERT(wl->pub->ieee_hw->priv == wl);
-
if (wlc_iovar_setint(wl->wlc, "mpc", 0)) {
- WL_ERROR("wl%d: Error setting MPC variable to 0\n", unit);
+ wiphy_err(wl->wiphy, "wl%d: Error setting MPC variable to 0\n",
+ unit);
}
/* register our interrupt handler */
if (request_irq(irq, wl_isr, IRQF_SHARED, KBUILD_MODNAME, wl)) {
- WL_ERROR("wl%d: request_irq() failed\n", unit);
+ wiphy_err(wl->wiphy, "wl%d: request_irq() failed\n", unit);
goto fail;
}
wl->irq = irq;
@@ -812,18 +825,20 @@
NULL);
if (ieee_hw_init(hw)) {
- WL_ERROR("wl%d: %s: ieee_hw_init failed!\n", unit, __func__);
+ wiphy_err(wl->wiphy, "wl%d: %s: ieee_hw_init failed!\n", unit,
+ __func__);
goto fail;
}
memcpy(perm, &wl->pub->cur_etheraddr, ETH_ALEN);
- ASSERT(is_valid_ether_addr(perm));
+ if (WARN_ON(!is_valid_ether_addr(perm)))
+ goto fail;
SET_IEEE80211_PERM_ADDR(hw, perm);
err = ieee80211_register_hw(hw);
if (err) {
- WL_ERROR("%s: ieee80211_register_hw failed, status %d\n",
- __func__, err);
+ wiphy_err(wl->wiphy, "%s: ieee80211_register_hw failed, status"
+ "%d\n", __func__, err);
}
if (wl->pub->srom_ccode[0])
@@ -831,8 +846,8 @@
else
err = wl_set_hint(wl, "US");
if (err) {
- WL_ERROR("%s: regulatory_hint failed, status %d\n",
- __func__, err);
+ wiphy_err(wl->wiphy, "%s: regulatory_hint failed, status %d\n",
+ __func__, err);
}
wl_found++;
@@ -840,7 +855,6 @@
fail:
wl_free(wl);
-fail1:
return NULL;
}
@@ -1027,9 +1041,8 @@
hw->wiphy->bands[IEEE80211_BAND_5GHZ] = NULL;
if (wlc_get(wl->wlc, WLC_GET_PHYLIST, (int *)&phy_list) < 0) {
- WL_ERROR("Phy list failed\n");
+ wiphy_err(hw->wiphy, "Phy list failed\n");
}
- WL_NONE("%s: phylist = %c\n", __func__, phy_list[0]);
if (phy_list[0] == 'n' || phy_list[0] == 'c') {
if (phy_list[0] == 'c') {
@@ -1039,8 +1052,7 @@
}
hw->wiphy->bands[IEEE80211_BAND_2GHZ] = &wl_band_2GHz_nphy;
} else {
- BUG();
- return -1;
+ return -EPERM;
}
/* Assume all bands use the same phy. True for 11n devices. */
@@ -1050,12 +1062,9 @@
hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
&wl_band_5GHz_nphy;
} else {
- return -1;
+ return -EPERM;
}
}
-
- WL_NONE("%s: 2ghz = %d, 5ghz = %d\n", __func__, 1, has_5g);
-
return 0;
}
@@ -1070,8 +1079,7 @@
| IEEE80211_HW_AMPDU_AGGREGATION;
hw->extra_tx_headroom = wlc_get_header_len();
- /* FIXME: should get this from wlc->machwcap */
- hw->queues = 4;
+ hw->queues = N_TX_QUEUES;
/* FIXME: this doesn't seem to be used properly in minstrel_ht.
* mac80211/status.c:ieee80211_tx_status() checks this value,
* but mac80211/rc80211_minstrel_ht.c:minstrel_ht_get_rate()
@@ -1104,11 +1112,9 @@
struct ieee80211_hw *hw;
u32 val;
- ASSERT(pdev);
-
- WL_TRACE("%s: bus %d slot %d func %d irq %d\n",
- __func__, pdev->bus->number, PCI_SLOT(pdev->devfn),
- PCI_FUNC(pdev->devfn), pdev->irq);
+ dev_info(&pdev->dev, "bus %d slot %d func %d irq %d\n",
+ pdev->bus->number, PCI_SLOT(pdev->devfn),
+ PCI_FUNC(pdev->devfn), pdev->irq);
if ((pdev->vendor != PCI_VENDOR_ID_BROADCOM) ||
(((pdev->device & 0xff00) != 0x4300) &&
@@ -1118,9 +1124,9 @@
rc = pci_enable_device(pdev);
if (rc) {
- WL_ERROR("%s: Cannot enable device %d-%d_%d\n",
- __func__, pdev->bus->number, PCI_SLOT(pdev->devfn),
- PCI_FUNC(pdev->devfn));
+ pr_err("%s: Cannot enable device %d-%d_%d\n",
+ __func__, pdev->bus->number, PCI_SLOT(pdev->devfn),
+ PCI_FUNC(pdev->devfn));
return -ENODEV;
}
pci_set_master(pdev);
@@ -1131,9 +1137,8 @@
hw = ieee80211_alloc_hw(sizeof(struct wl_info), &wl_ops);
if (!hw) {
- WL_ERROR("%s: ieee80211_alloc_hw failed\n", __func__);
- rc = -ENOMEM;
- goto err_1;
+ pr_err("%s: ieee80211_alloc_hw failed\n", __func__);
+ return -ENOMEM;
}
SET_IEEE80211_DEV(hw, &pdev->dev);
@@ -1146,14 +1151,11 @@
PCI_BUS, pdev, pdev->irq);
if (!wl) {
- WL_ERROR("%s: %s: wl_attach failed!\n",
- KBUILD_MODNAME, __func__);
+ pr_err("%s: %s: wl_attach failed!\n", KBUILD_MODNAME,
+ __func__);
return -ENODEV;
}
return 0;
- err_1:
- WL_ERROR("%s: err_1: Major hoarkage\n", __func__);
- return 0;
}
static int wl_suspend(struct pci_dev *pdev, pm_message_t state)
@@ -1161,12 +1163,11 @@
struct wl_info *wl;
struct ieee80211_hw *hw;
- WL_TRACE("wl: wl_suspend\n");
-
hw = pci_get_drvdata(pdev);
wl = HW_TO_WL(hw);
if (!wl) {
- WL_ERROR("wl: wl_suspend: pci_get_drvdata failed\n");
+ wiphy_err(wl->wiphy,
+ "wl_suspend: pci_get_drvdata failed\n");
return -ENODEV;
}
@@ -1187,11 +1188,11 @@
int err = 0;
u32 val;
- WL_TRACE("wl: wl_resume\n");
hw = pci_get_drvdata(pdev);
wl = HW_TO_WL(hw);
if (!wl) {
- WL_ERROR("wl: wl_resume: pci_get_drvdata failed\n");
+ wiphy_err(wl->wiphy,
+ "wl: wl_resume: pci_get_drvdata failed\n");
return -ENODEV;
}
@@ -1231,7 +1232,7 @@
hw = pci_get_drvdata(pdev);
wl = HW_TO_WL(hw);
if (!wl) {
- WL_ERROR("wl: wl_remove: pci_get_drvdata failed\n");
+ pr_err("wl: wl_remove: pci_get_drvdata failed\n");
return;
}
@@ -1239,7 +1240,7 @@
status = wlc_chipmatch(pdev->vendor, pdev->device);
WL_UNLOCK(wl);
if (!status) {
- WL_ERROR("wl: wl_remove: wlc_chipmatch failed\n");
+ wiphy_err(wl->wiphy, "wl: wl_remove: wlc_chipmatch failed\n");
return;
}
if (wl->wlc) {
@@ -1249,7 +1250,6 @@
WL_LOCK(wl);
wl_down(wl);
WL_UNLOCK(wl);
- WL_NONE("%s: Down\n", __func__);
}
pci_disable_device(pdev);
@@ -1342,7 +1342,6 @@
{
struct wl_timer *t, *next;
- ASSERT(wl);
/* free ucode data */
if (wl->fw.fw_cnt)
wl_ucode_data_free();
@@ -1389,13 +1388,30 @@
wl->regsva = NULL;
}
+/* flags the given rate in rateset as requested */
+static void wl_set_basic_rate(struct wl_rateset *rs, u16 rate, bool is_br)
+{
+ u32 i;
+
+ for (i = 0; i < rs->count; i++) {
+ if (rate != (rs->rates[i] & 0x7f))
+ continue;
+
+ if (is_br)
+ rs->rates[i] |= WLC_RATE_FLAG;
+ else
+ rs->rates[i] &= WLC_RATE_MASK;
+ return;
+ }
+}
+
/*
* precondition: perimeter lock has been acquired
*/
void wl_txflowcontrol(struct wl_info *wl, struct wl_if *wlif, bool state,
int prio)
{
- WL_ERROR("Shouldn't be here %s\n", __func__);
+ wiphy_err(wl->wiphy, "Shouldn't be here %s\n", __func__);
}
/*
@@ -1403,8 +1419,7 @@
*/
void wl_init(struct wl_info *wl)
{
- WL_TRACE("wl%d: wl_init\n", wl->pub->unit);
-
+ BCMMSG(WL_TO_HW(wl)->wiphy, "wl%d\n", wl->pub->unit);
wl_reset(wl);
wlc_init(wl->wlc);
@@ -1415,8 +1430,7 @@
*/
uint wl_reset(struct wl_info *wl)
{
- WL_TRACE("wl%d: wl_reset\n", wl->pub->unit);
-
+ BCMMSG(WL_TO_HW(wl)->wiphy, "wl%d\n", wl->pub->unit);
wlc_reset(wl->wlc);
/* dpc will not be rescheduled */
@@ -1429,7 +1443,7 @@
* These are interrupt on/off entry points. Disable interrupts
* during interrupt state transition.
*/
-void BCMFASTPATH wl_intrson(struct wl_info *wl)
+void wl_intrson(struct wl_info *wl)
{
unsigned long flags;
@@ -1446,7 +1460,7 @@
return true;
}
-u32 BCMFASTPATH wl_intrsoff(struct wl_info *wl)
+u32 wl_intrsoff(struct wl_info *wl)
{
unsigned long flags;
u32 status;
@@ -1503,7 +1517,7 @@
WL_LOCK(wl);
}
-static irqreturn_t BCMFASTPATH wl_isr(int irq, void *dev_id)
+static irqreturn_t wl_isr(int irq, void *dev_id)
{
struct wl_info *wl;
bool ours, wantdpc;
@@ -1521,7 +1535,6 @@
/* ...and call the second level interrupt handler */
/* schedule dpc */
- ASSERT(wl->resched == false);
tasklet_schedule(&wl->tasklet);
}
}
@@ -1531,7 +1544,7 @@
return IRQ_RETVAL(ours);
}
-static void BCMFASTPATH wl_dpc(unsigned long data)
+static void wl_dpc(unsigned long data)
{
struct wl_info *wl;
@@ -1613,7 +1626,8 @@
t = kzalloc(sizeof(struct wl_timer), GFP_ATOMIC);
if (!t) {
- WL_ERROR("wl%d: wl_init_timer: out of memory\n", wl->pub->unit);
+ wiphy_err(wl->wiphy, "wl%d: wl_init_timer: out of memory\n",
+ wl->pub->unit);
return 0;
}
@@ -1644,12 +1658,10 @@
{
#ifdef BCMDBG
if (t->set) {
- WL_ERROR("%s: Already set. Name: %s, per %d\n",
- __func__, t->name, periodic);
+ wiphy_err(wl->wiphy, "%s: Already set. Name: %s, per %d\n",
+ __func__, t->name, periodic);
}
#endif
- ASSERT(!t->set);
-
t->ms = ms;
t->periodic = (bool) periodic;
t->set = true;
@@ -1719,37 +1731,6 @@
*/
static int wl_linux_watchdog(void *ctx)
{
- struct wl_info *wl = (struct wl_info *) ctx;
- struct wl_cnt *cnt;
- struct net_device_stats *stats = NULL;
- uint id;
- /* refresh stats */
- if (wl->pub->up) {
- ASSERT(wl->stats_id < 2);
-
- cnt = wl->pub->_cnt;
- id = 1 - wl->stats_id;
- stats = &wl->stats_watchdog[id];
- stats->rx_packets = cnt->rxframe;
- stats->tx_packets = cnt->txframe;
- stats->rx_bytes = cnt->rxbyte;
- stats->tx_bytes = cnt->txbyte;
- stats->rx_errors = cnt->rxerror;
- stats->tx_errors = cnt->txerror;
- stats->collisions = 0;
-
- stats->rx_length_errors = 0;
- stats->rx_over_errors = cnt->rxoflo;
- stats->rx_crc_errors = cnt->rxcrc;
- stats->rx_frame_errors = 0;
- stats->rx_fifo_errors = cnt->rxoflo;
- stats->rx_missed_errors = 0;
-
- stats->tx_fifo_errors = cnt->txuflo;
-
- wl->stats_id = id;
- }
-
return 0;
}
@@ -1780,8 +1761,8 @@
pdata = wl->fw.fw_bin[i]->data + hdr->offset;
*pbuf = kmalloc(hdr->len, GFP_ATOMIC);
if (*pbuf == NULL) {
- WL_ERROR("fail to alloc %d bytes\n",
- hdr->len);
+ wiphy_err(wl->wiphy, "fail to alloc %d"
+ " bytes\n", hdr->len);
goto fail;
}
memcpy(*pbuf, pdata, hdr->len);
@@ -1789,10 +1770,11 @@
}
}
}
- WL_ERROR("ERROR: ucode buf tag:%d can not be found!\n", idx);
+ wiphy_err(wl->wiphy, "ERROR: ucode buf tag:%d can not be found!\n",
+ idx);
*pbuf = NULL;
fail:
- return BCME_NOTFOUND;
+ return -ENODATA;
}
/*
@@ -1810,14 +1792,18 @@
entry++, hdr++) {
if (hdr->idx == idx) {
pdata = wl->fw.fw_bin[i]->data + hdr->offset;
- ASSERT(hdr->len == 4);
+ if (hdr->len != 4) {
+ wiphy_err(wl->wiphy,
+ "ERROR: fw hdr len\n");
+ return -ENOMSG;
+ }
*data = *((u32 *) pdata);
return 0;
}
}
}
- WL_ERROR("ERROR: ucode tag:%d can not be found!\n", idx);
- return -1;
+ wiphy_err(wl->wiphy, "ERROR: ucode tag:%d can not be found!\n", idx);
+ return -ENOMSG;
}
/*
@@ -1837,26 +1823,22 @@
break;
sprintf(fw_name, "%s-%d.fw", wl_firmwares[i],
UCODE_LOADER_API_VER);
- WL_NONE("request fw %s\n", fw_name);
status = request_firmware(&wl->fw.fw_bin[i], fw_name, device);
if (status) {
- WL_ERROR("%s: fail to load firmware %s\n",
- KBUILD_MODNAME, fw_name);
+ wiphy_err(wl->wiphy, "%s: fail to load firmware %s\n",
+ KBUILD_MODNAME, fw_name);
return status;
}
- WL_NONE("request fw %s\n", fw_name);
sprintf(fw_name, "%s_hdr-%d.fw", wl_firmwares[i],
UCODE_LOADER_API_VER);
status = request_firmware(&wl->fw.fw_hdr[i], fw_name, device);
if (status) {
- WL_ERROR("%s: fail to load firmware %s\n",
- KBUILD_MODNAME, fw_name);
+ wiphy_err(wl->wiphy, "%s: fail to load firmware %s\n",
+ KBUILD_MODNAME, fw_name);
return status;
}
wl->fw.hdr_num_entries[i] =
wl->fw.fw_hdr[i]->size / (sizeof(struct wl_fw_hdr));
- WL_NONE("request fw %s find: %d entries\n",
- fw_name, wl->fw.hdr_num_entries[i]);
}
wl->fw.fw_cnt = i;
return wl_ucode_data_init(wl);
@@ -1904,16 +1886,17 @@
if (fw == NULL && fw_hdr == NULL) {
break;
} else if (fw == NULL || fw_hdr == NULL) {
- WL_ERROR("%s: invalid bin/hdr fw\n", __func__);
+ wiphy_err(wl->wiphy, "%s: invalid bin/hdr fw\n",
+ __func__);
rc = -EBADF;
} else if (fw_hdr->size % sizeof(struct wl_fw_hdr)) {
- WL_ERROR("%s: non integral fw hdr file size %zu/%zu\n",
- __func__, fw_hdr->size,
- sizeof(struct wl_fw_hdr));
+ wiphy_err(wl->wiphy, "%s: non integral fw hdr file "
+ "size %zu/%zu\n", __func__, fw_hdr->size,
+ sizeof(struct wl_fw_hdr));
rc = -EBADF;
} else if (fw->size < MIN_FW_SIZE || fw->size > MAX_FW_SIZE) {
- WL_ERROR("%s: out of bounds fw file size %zu\n",
- __func__, fw->size);
+ wiphy_err(wl->wiphy, "%s: out of bounds fw file size "
+ "%zu\n", __func__, fw->size);
rc = -EBADF;
} else {
/* check if ucode section overruns firmware image */
@@ -1922,15 +1905,17 @@
!rc; entry++, ucode_hdr++) {
if (ucode_hdr->offset + ucode_hdr->len >
fw->size) {
- WL_ERROR("%s: conflicting bin/hdr\n",
- __func__);
+ wiphy_err(wl->wiphy,
+ "%s: conflicting bin/hdr\n",
+ __func__);
rc = -EBADF;
}
}
}
}
if (rc == 0 && wl->fw.fw_cnt != i) {
- WL_ERROR("%s: invalid fw_cnt=%d\n", __func__, wl->fw.fw_cnt);
+ wiphy_err(wl->wiphy, "%s: invalid fw_cnt=%d\n", __func__,
+ wl->fw.fw_cnt);
rc = -EBADF;
}
return rc;
@@ -1943,8 +1928,6 @@
{
bool blocked = wlc_check_radio_disabled(wl->wlc);
- WL_NONE("%s: update hw state: blocked=%s\n", __func__,
- blocked ? "true" : "false");
WL_UNLOCK(wl);
wiphy_rfkill_set_hw_state(wl->pub->ieee_hw->wiphy, blocked);
if (blocked)
@@ -1952,3 +1935,13 @@
WL_LOCK(wl);
return blocked;
}
+
+/*
+ * precondition: perimeter lock has been acquired
+ */
+void wl_msleep(struct wl_info *wl, uint ms)
+{
+ WL_UNLOCK(wl);
+ msleep(ms);
+ WL_LOCK(wl);
+}
diff --git a/drivers/staging/brcm80211/brcmsmac/wl_mac80211.h b/drivers/staging/brcm80211/brcmsmac/wl_mac80211.h
index f3198cc..e703d8b 100644
--- a/drivers/staging/brcm80211/brcmsmac/wl_mac80211.h
+++ b/drivers/staging/brcm80211/brcmsmac/wl_mac80211.h
@@ -67,11 +67,8 @@
#ifdef LINUXSTA_PS
u32 pci_psstate[16]; /* pci ps-state save/restore */
#endif
- /* RPC, handle, lock, txq, workitem */
- uint stats_id; /* the current set of stats */
- /* ping-pong stats counters updated by Linux watchdog */
- struct net_device_stats stats_watchdog[2];
struct wl_firmware fw;
+ struct wiphy *wiphy;
};
#define WL_LOCK(wl) spin_lock_bh(&(wl)->lock)
diff --git a/drivers/staging/brcm80211/brcmsmac/wlc_alloc.c b/drivers/staging/brcm80211/brcmsmac/wlc_alloc.c
index e928fa1..82c64cd 100644
--- a/drivers/staging/brcm80211/brcmsmac/wlc_alloc.c
+++ b/drivers/staging/brcm80211/brcmsmac/wlc_alloc.c
@@ -18,7 +18,7 @@
#include <bcmdefs.h>
#include <bcmutils.h>
-#include <siutils.h>
+#include <aiutils.h>
#include <wlioctl.h>
#include <sbhnddma.h>
@@ -43,17 +43,7 @@
static void wlc_pub_mfree(struct wlc_pub *pub);
static void wlc_tunables_init(wlc_tunables_t *tunables, uint devid);
-void *wlc_calloc(uint unit, uint size)
-{
- void *item;
-
- item = kzalloc(size, GFP_ATOMIC);
- if (item == NULL)
- WL_ERROR("wl%d: %s: out of memory\n", unit, __func__);
- return item;
-}
-
-void wlc_tunables_init(wlc_tunables_t *tunables, uint devid)
+static void wlc_tunables_init(wlc_tunables_t *tunables, uint devid)
{
tunables->ntxd = NTXD;
tunables->nrxd = NRXD;
@@ -75,14 +65,13 @@
{
struct wlc_pub *pub;
- pub = wlc_calloc(unit, sizeof(struct wlc_pub));
+ pub = kzalloc(sizeof(struct wlc_pub), GFP_ATOMIC);
if (pub == NULL) {
*err = 1001;
goto fail;
}
- pub->tunables = wlc_calloc(unit,
- sizeof(wlc_tunables_t));
+ pub->tunables = kzalloc(sizeof(wlc_tunables_t), GFP_ATOMIC);
if (pub->tunables == NULL) {
*err = 1028;
goto fail;
@@ -91,12 +80,7 @@
/* need to init the tunables now */
wlc_tunables_init(pub->tunables, devid);
- pub->_cnt = wlc_calloc(unit, sizeof(struct wl_cnt));
- if (pub->_cnt == NULL)
- goto fail;
-
- pub->multicast = (u8 *)wlc_calloc(unit,
- (ETH_ALEN * MAXMULTILIST));
+ pub->multicast = kzalloc(ETH_ALEN * MAXMULTILIST, GFP_ATOMIC);
if (pub->multicast == NULL) {
*err = 1003;
goto fail;
@@ -115,7 +99,6 @@
return;
kfree(pub->multicast);
- kfree(pub->_cnt);
kfree(pub->tunables);
kfree(pub);
}
@@ -124,12 +107,11 @@
{
struct wlc_bsscfg *cfg;
- cfg = (struct wlc_bsscfg *) wlc_calloc(unit, sizeof(struct wlc_bsscfg));
+ cfg = kzalloc(sizeof(struct wlc_bsscfg), GFP_ATOMIC);
if (cfg == NULL)
goto fail;
- cfg->current_bss = (wlc_bss_info_t *)wlc_calloc(unit,
- sizeof(wlc_bss_info_t));
+ cfg->current_bss = kzalloc(sizeof(wlc_bss_info_t), GFP_ATOMIC);
if (cfg->current_bss == NULL)
goto fail;
@@ -150,7 +132,8 @@
kfree(cfg);
}
-void wlc_bsscfg_ID_assign(struct wlc_info *wlc, struct wlc_bsscfg *bsscfg)
+static void wlc_bsscfg_ID_assign(struct wlc_info *wlc,
+ struct wlc_bsscfg *bsscfg)
{
bsscfg->ID = wlc->next_bsscfg_ID;
wlc->next_bsscfg_ID++;
@@ -163,7 +146,7 @@
{
struct wlc_info *wlc;
- wlc = (struct wlc_info *) wlc_calloc(unit, sizeof(struct wlc_info));
+ wlc = kzalloc(sizeof(struct wlc_info), GFP_ATOMIC);
if (wlc == NULL) {
*err = 1002;
goto fail;
@@ -181,16 +164,15 @@
/* allocate struct wlc_hw_info state structure */
- wlc->hw = (struct wlc_hw_info *)wlc_calloc(unit,
- sizeof(struct wlc_hw_info));
+ wlc->hw = kzalloc(sizeof(struct wlc_hw_info), GFP_ATOMIC);
if (wlc->hw == NULL) {
*err = 1005;
goto fail;
}
wlc->hw->wlc = wlc;
- wlc->hw->bandstate[0] = wlc_calloc(unit,
- (sizeof(struct wlc_hwband) * MAXBANDS));
+ wlc->hw->bandstate[0] =
+ kzalloc(sizeof(struct wlc_hwband) * MAXBANDS, GFP_ATOMIC);
if (wlc->hw->bandstate[0] == NULL) {
*err = 1006;
goto fail;
@@ -204,15 +186,14 @@
}
}
- wlc->modulecb = wlc_calloc(unit,
- sizeof(struct modulecb) * WLC_MAXMODULES);
+ wlc->modulecb =
+ kzalloc(sizeof(struct modulecb) * WLC_MAXMODULES, GFP_ATOMIC);
if (wlc->modulecb == NULL) {
*err = 1009;
goto fail;
}
- wlc->default_bss = (wlc_bss_info_t *)wlc_calloc(unit,
- sizeof(wlc_bss_info_t));
+ wlc->default_bss = kzalloc(sizeof(wlc_bss_info_t), GFP_ATOMIC);
if (wlc->default_bss == NULL) {
*err = 1010;
goto fail;
@@ -225,15 +206,16 @@
}
wlc_bsscfg_ID_assign(wlc, wlc->cfg);
- wlc->pkt_callback = wlc_calloc(unit,
- (sizeof(struct pkt_cb) * (wlc->pub->tunables->maxpktcb + 1)));
+ wlc->pkt_callback = kzalloc(sizeof(struct pkt_cb) *
+ (wlc->pub->tunables->maxpktcb + 1),
+ GFP_ATOMIC);
if (wlc->pkt_callback == NULL) {
*err = 1013;
goto fail;
}
- wlc->wsec_def_keys[0] = (wsec_key_t *)wlc_calloc(unit,
- (sizeof(wsec_key_t) * WLC_DEFAULT_KEYS));
+ wlc->wsec_def_keys[0] =
+ kzalloc(sizeof(wsec_key_t) * WLC_DEFAULT_KEYS, GFP_ATOMIC);
if (wlc->wsec_def_keys[0] == NULL) {
*err = 1015;
goto fail;
@@ -246,21 +228,20 @@
}
}
- wlc->protection = wlc_calloc(unit,
- sizeof(struct wlc_protection));
+ wlc->protection = kzalloc(sizeof(struct wlc_protection), GFP_ATOMIC);
if (wlc->protection == NULL) {
*err = 1016;
goto fail;
}
- wlc->stf = wlc_calloc(unit, sizeof(struct wlc_stf));
+ wlc->stf = kzalloc(sizeof(struct wlc_stf), GFP_ATOMIC);
if (wlc->stf == NULL) {
*err = 1017;
goto fail;
}
- wlc->bandstate[0] = (struct wlcband *)wlc_calloc(unit,
- (sizeof(struct wlcband)*MAXBANDS));
+ wlc->bandstate[0] =
+ kzalloc(sizeof(struct wlcband)*MAXBANDS, GFP_ATOMIC);
if (wlc->bandstate[0] == NULL) {
*err = 1025;
goto fail;
@@ -274,15 +255,14 @@
}
}
- wlc->corestate = (struct wlccore *)wlc_calloc(unit,
- sizeof(struct wlccore));
+ wlc->corestate = kzalloc(sizeof(struct wlccore), GFP_ATOMIC);
if (wlc->corestate == NULL) {
*err = 1026;
goto fail;
}
wlc->corestate->macstat_snapshot =
- (macstat_t *)wlc_calloc(unit, sizeof(macstat_t));
+ kzalloc(sizeof(macstat_t), GFP_ATOMIC);
if (wlc->corestate->macstat_snapshot == NULL) {
*err = 1027;
goto fail;
diff --git a/drivers/staging/brcm80211/brcmsmac/wlc_alloc.h b/drivers/staging/brcm80211/brcmsmac/wlc_alloc.h
index 1fb7430..95f951e 100644
--- a/drivers/staging/brcm80211/brcmsmac/wlc_alloc.h
+++ b/drivers/staging/brcm80211/brcmsmac/wlc_alloc.h
@@ -14,7 +14,5 @@
* CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*/
-extern void *wlc_calloc(uint unit, uint size);
-
extern struct wlc_info *wlc_attach_malloc(uint unit, uint *err, uint devid);
extern void wlc_detach_mfree(struct wlc_info *wlc);
diff --git a/drivers/staging/brcm80211/brcmsmac/wlc_ampdu.c b/drivers/staging/brcm80211/brcmsmac/wlc_ampdu.c
index f008659..85ad700 100644
--- a/drivers/staging/brcm80211/brcmsmac/wlc_ampdu.c
+++ b/drivers/staging/brcm80211/brcmsmac/wlc_ampdu.c
@@ -18,7 +18,7 @@
#include <bcmdefs.h>
#include <bcmutils.h>
-#include <siutils.h>
+#include <aiutils.h>
#include <wlioctl.h>
#include <sbhnddma.h>
#include <hnddma.h>
@@ -38,12 +38,6 @@
#include "wlc_main.h"
#include "wlc_ampdu.h"
-/*
- * Disable AMPDU statistics counters for now
- */
-#define WLCNTINCR(a)
-#define WLCNTADD(a, b)
-
#define AMPDU_MAX_MPDU 32 /* max number of mpdus in an ampdu */
#define AMPDU_NUM_MPDU_LEGACY 16 /* max number of mpdus in an ampdu to a legacy */
#define AMPDU_TX_BA_MAX_WSIZE 64 /* max Tx ba window size (in pdu) */
@@ -76,16 +70,6 @@
AMPDU_DELIMITER_LEN + 3\
+ DOT11_A4_HDR_LEN + DOT11_QOS_LEN + DOT11_IV_MAX_LEN)
-#ifdef BCMDBG
-u32 wl_ampdu_dbg =
- WL_AMPDU_UPDN_VAL |
- WL_AMPDU_ERR_VAL |
- WL_AMPDU_TX_VAL |
- WL_AMPDU_RX_VAL |
- WL_AMPDU_CTL_VAL |
- WL_AMPDU_HW_VAL | WL_AMPDU_HWTXS_VAL | WL_AMPDU_HWDBG_VAL;
-#endif
-
/* structure to hold tx fifo information and pre-loading state
* counters specific to tx underflows of ampdus
* some counters might be redundant with the ones in wlc or ampdu structures.
@@ -130,6 +114,12 @@
};
+/* used for flushing ampdu packets */
+struct cb_del_ampdu_pars {
+ struct ieee80211_sta *sta;
+ u16 tid;
+};
+
#define AMPDU_CLEANUPFLAG_RX (0x1)
#define AMPDU_CLEANUPFLAG_TX (0x2)
@@ -143,9 +133,6 @@
static scb_ampdu_tid_ini_t *wlc_ampdu_init_tid_ini(struct ampdu_info *ampdu,
scb_ampdu_t *scb_ampdu,
u8 tid, bool override);
-static void ampdu_cleanup_tid_ini(struct ampdu_info *ampdu,
- scb_ampdu_t *scb_ampdu,
- u8 tid, bool force);
static void ampdu_update_max_txlen(struct ampdu_info *ampdu, u8 dur);
static void scb_ampdu_update_config(struct ampdu_info *ampdu, struct scb *scb);
static void scb_ampdu_update_config_all(struct ampdu_info *ampdu);
@@ -164,17 +151,10 @@
struct ampdu_info *ampdu;
int i;
- /* some code depends on packed structures */
- ASSERT(DOT11_MAXNUMFRAGS == NBITS(u16));
- ASSERT(ISPOWEROF2(AMPDU_TX_BA_MAX_WSIZE));
- ASSERT(ISPOWEROF2(AMPDU_RX_BA_MAX_WSIZE));
- ASSERT(wlc->pub->tunables->ampdunummpdu <= AMPDU_MAX_MPDU);
- ASSERT(wlc->pub->tunables->ampdunummpdu > 0);
-
ampdu = kzalloc(sizeof(struct ampdu_info), GFP_ATOMIC);
if (!ampdu) {
- WL_ERROR("wl%d: wlc_ampdu_attach: out of mem\n",
- wlc->pub->unit);
+ wiphy_err(wlc->wiphy, "wl%d: wlc_ampdu_attach: out of mem\n",
+ wlc->pub->unit);
return NULL;
}
ampdu->wlc = wlc;
@@ -237,27 +217,6 @@
kfree(ampdu);
}
-void scb_ampdu_cleanup(struct ampdu_info *ampdu, struct scb *scb)
-{
- scb_ampdu_t *scb_ampdu = SCB_AMPDU_CUBBY(ampdu, scb);
- u8 tid;
-
- WL_AMPDU_UPDN("scb_ampdu_cleanup: enter\n");
- ASSERT(scb_ampdu);
-
- for (tid = 0; tid < AMPDU_MAX_SCB_TID; tid++) {
- ampdu_cleanup_tid_ini(ampdu, scb_ampdu, tid, false);
- }
-}
-
-/* reset the ampdu state machine so that it can gracefully handle packets that were
- * freed from the dma and tx queues during reinit
- */
-void wlc_ampdu_reset(struct ampdu_info *ampdu)
-{
- WL_NONE("%s: Entering\n", __func__);
-}
-
static void scb_ampdu_update_config(struct ampdu_info *ampdu, struct scb *scb)
{
scb_ampdu_t *scb_ampdu = SCB_AMPDU_CUBBY(ampdu, scb);
@@ -284,11 +243,9 @@
scb_ampdu->release = min(scb_ampdu->release,
ampdu->fifo_tb[TX_AC_BE_FIFO].
mcs2ampdu_table[FFPLD_MAX_MCS]);
-
- ASSERT(scb_ampdu->release);
}
-void scb_ampdu_update_config_all(struct ampdu_info *ampdu)
+static void scb_ampdu_update_config_all(struct ampdu_info *ampdu)
{
scb_ampdu_update_config(ampdu, ampdu->wlc->pub->global_scb);
}
@@ -336,7 +293,7 @@
M_UCODE_MACSTAT + offsetof(macstat_t, txfunfl[fid]));
new_txunfl = (u16) (cur_txunfl - fifo->prev_txfunfl);
if (new_txunfl == 0) {
- WL_FFPLD("check_txunfl : TX status FRAG set but no tx underflows\n");
+ BCMMSG(wlc->wiphy, "TX status FRAG set but no tx underflows\n");
return -1;
}
fifo->prev_txfunfl = cur_txunfl;
@@ -346,7 +303,6 @@
/* check if fifo is big enough */
if (wlc_xmtfifo_sz_get(wlc, fid, &xmtfifo_sz)) {
- WL_FFPLD("check_txunfl : get xmtfifo_sz failed\n");
return -1;
}
@@ -360,8 +316,8 @@
if (fifo->accum_txfunfl < 10)
return 0;
- WL_FFPLD("ampdu_count %d tx_underflows %d\n",
- current_ampdu_cnt, fifo->accum_txfunfl);
+ BCMMSG(wlc->wiphy, "ampdu_count %d tx_underflows %d\n",
+ current_ampdu_cnt, fifo->accum_txfunfl);
/*
compute the current ratio of tx unfl per ampdu.
@@ -388,7 +344,6 @@
*/
if (fifo->ampdu_pld_size >= max_mpdu * FFPLD_MPDU_SIZE) {
- WL_FFPLD(("tx fifo pld : max ampdu fits in fifo\n)"));
fifo->accum_txfunfl = 0;
return 0;
}
@@ -406,7 +361,7 @@
/*
compute a new dma xfer rate for max_mpdu @ max mcs.
This is the minimum dma rate that
- can achieve no unferflow condition for the current mpdu size.
+ can achieve no underflow condition for the current mpdu size.
*/
/* note : we divide/multiply by 100 to avoid integer overflows */
fifo->dmaxferrate =
@@ -414,8 +369,9 @@
(max_mpdu * FFPLD_MPDU_SIZE - fifo->ampdu_pld_size))
/ (max_mpdu * FFPLD_MPDU_SIZE)) * 100;
- WL_FFPLD("DMA estimated transfer rate %d; pre-load size %d\n",
- fifo->dmaxferrate, fifo->ampdu_pld_size);
+ BCMMSG(wlc->wiphy, "DMA estimated transfer rate %d; "
+ "pre-load size %d\n",
+ fifo->dmaxferrate, fifo->ampdu_pld_size);
} else {
/* decrease ampdu size */
@@ -469,7 +425,7 @@
}
}
-static void BCMFASTPATH
+static void
wlc_ampdu_agg(struct ampdu_info *ampdu, struct scb *scb, struct sk_buff *p,
uint prec)
{
@@ -487,7 +443,7 @@
return;
}
-int BCMFASTPATH
+int
wlc_sendampdu(struct ampdu_info *ampdu, struct wlc_txq_info *qi,
struct sk_buff **pdu, int prec)
{
@@ -521,35 +477,31 @@
bool fbr_iscck;
struct ieee80211_tx_info *tx_info;
u16 qlen;
+ struct wiphy *wiphy;
wlc = ampdu->wlc;
+ wiphy = wlc->wiphy;
p = *pdu;
- ASSERT(p);
-
tid = (u8) (p->priority);
- ASSERT(tid < AMPDU_MAX_SCB_TID);
f = ampdu->fifo_tb + prio2fifo[tid];
scb = wlc->pub->global_scb;
- ASSERT(scb->magic == SCB_MAGIC);
-
scb_ampdu = SCB_AMPDU_CUBBY(ampdu, scb);
- ASSERT(scb_ampdu);
ini = &scb_ampdu->ini[tid];
/* Let pressure continue to build ... */
qlen = pktq_plen(&qi->q, prec);
if (ini->tx_in_transit > 0 && qlen < scb_ampdu->max_pdu) {
- return BCME_BUSY;
+ return -EBUSY;
}
wlc_ampdu_agg(ampdu, scb, p, tid);
if (wlc->block_datafifo) {
- WL_ERROR("%s: Fifo blocked\n", __func__);
- return BCME_BUSY;
+ wiphy_err(wiphy, "%s: Fifo blocked\n", __func__);
+ return -EBUSY;
}
rr_retry_limit = ampdu->rr_retry_limit_tid[tid];
ampdu_len = 0;
@@ -563,32 +515,29 @@
if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
err = wlc_prep_pdu(wlc, p, &fifo);
} else {
- WL_ERROR("%s: AMPDU flag is off!\n", __func__);
+ wiphy_err(wiphy, "%s: AMPDU flag is off!\n", __func__);
*pdu = NULL;
err = 0;
break;
}
if (err) {
- if (err == BCME_BUSY) {
- WL_ERROR("wl%d: wlc_sendampdu: prep_xdu retry; seq 0x%x\n",
- wlc->pub->unit, seq);
- WLCNTINCR(ampdu->cnt->sduretry);
+ if (err == -EBUSY) {
+ wiphy_err(wiphy, "wl%d: wlc_sendampdu: "
+ "prep_xdu retry; seq 0x%x\n",
+ wlc->pub->unit, seq);
*pdu = p;
break;
}
/* error in the packet; reject it */
- WL_AMPDU_ERR("wl%d: wlc_sendampdu: prep_xdu rejected; seq 0x%x\n",
- wlc->pub->unit, seq);
- WLCNTINCR(ampdu->cnt->sdurejected);
-
+ wiphy_err(wiphy, "wl%d: wlc_sendampdu: prep_xdu "
+ "rejected; seq 0x%x\n", wlc->pub->unit, seq);
*pdu = NULL;
break;
}
/* pkt is good to be aggregated */
- ASSERT(tx_info->flags & IEEE80211_TX_CTL_AMPDU);
txh = (d11txh_t *) p->data;
plcp = (u8 *) (txh + 1);
h = (struct ieee80211_hdr *)(plcp + D11_PHY_HDR_LEN);
@@ -599,7 +548,6 @@
mcl = le16_to_cpu(txh->MacTxControlLow);
mcl &= ~TXC_AMPDU_MASK;
fbr_iscck = !(le16_to_cpu(txh->XtraFrameTypes) & 0x3);
- ASSERT(!fbr_iscck);
txh->PreloadSize = 0; /* always default to 0 */
/* Handle retry limits */
@@ -607,7 +555,6 @@
txrate[0].count++;
rr = true;
fbr = false;
- ASSERT(!fbr);
} else {
fbr = true;
rr = false;
@@ -622,8 +569,8 @@
ndelim = txh->RTSPLCPFallback[AMPDU_FBR_NULL_DELIM];
seg_cnt += 1;
- WL_AMPDU_TX("wl%d: wlc_sendampdu: mpdu %d plcp_len %d\n",
- wlc->pub->unit, count, len);
+ BCMMSG(wlc->wiphy, "wl%d: mpdu %d plcp_len %d\n",
+ wlc->pub->unit, count, len);
/*
* aggregateable mpdu. For ucode/hw agg,
@@ -651,10 +598,11 @@
len = roundup(len, 4);
ampdu_len += (len + (ndelim + 1) * AMPDU_DELIMITER_LEN);
- dma_len += (u16) pkttotlen(p);
+ dma_len += (u16) bcm_pkttotlen(p);
- WL_AMPDU_TX("wl%d: wlc_sendampdu: ampdu_len %d seg_cnt %d null delim %d\n",
- wlc->pub->unit, ampdu_len, seg_cnt, ndelim);
+ BCMMSG(wlc->wiphy, "wl%d: ampdu_len %d"
+ " seg_cnt %d null delim %d\n",
+ wlc->pub->unit, ampdu_len, seg_cnt, ndelim);
txh->MacTxControlLow = cpu_to_le16(mcl);
@@ -679,15 +627,14 @@
is40 = (plcp0 & MIMO_PLCP_40MHZ) ? 1 : 0;
sgi = PLCP3_ISSGI(plcp3) ? 1 : 0;
mcs = plcp0 & ~MIMO_PLCP_40MHZ;
- ASSERT(mcs < MCS_TABLE_SIZE);
maxlen =
min(scb_ampdu->max_rxlen,
ampdu->max_txlen[mcs][is40][sgi]);
- WL_NONE("sendampdu: sgi %d, is40 %d, mcs %d\n",
- sgi, is40, mcs);
-
- maxlen = 64 * 1024; /* XXX Fix me to honor real max_rxlen */
+ /* XXX Fix me to honor real max_rxlen */
+ /* can fix this as soon as ampdu_action() in mac80211.h
+ * gets extra u8buf_size par */
+ maxlen = 64 * 1024;
if (is40)
mimo_ctlchbw =
@@ -728,14 +675,13 @@
/* test whether to add more */
if ((MCS_RATE(mcs, true, false) >= f->dmaxferrate) &&
(count == f->mcs2ampdu_table[mcs])) {
- WL_AMPDU_ERR("wl%d: PR 37644: stopping ampdu at %d for mcs %d\n",
- wlc->pub->unit, count, mcs);
+ BCMMSG(wlc->wiphy, "wl%d: PR 37644: stopping"
+ " ampdu at %d for mcs %d\n",
+ wlc->pub->unit, count, mcs);
break;
}
if (count == scb_ampdu->max_pdu) {
- WL_NONE("Stop taking from q, reached %d deep\n",
- scb_ampdu->max_pdu);
break;
}
@@ -748,26 +694,24 @@
((u8) (p->priority) == tid)) {
plen =
- pkttotlen(p) + AMPDU_MAX_MPDU_OVERHEAD;
+ bcm_pkttotlen(p) + AMPDU_MAX_MPDU_OVERHEAD;
plen = max(scb_ampdu->min_len, plen);
if ((plen + ampdu_len) > maxlen) {
p = NULL;
- WL_ERROR("%s: Bogus plen #1\n",
- __func__);
- ASSERT(3 == 4);
+ wiphy_err(wiphy, "%s: Bogus plen #1\n",
+ __func__);
continue;
}
/* check if there are enough descriptors available */
if (TXAVAIL(wlc, fifo) <= (seg_cnt + 1)) {
- WL_ERROR("%s: No fifo space !!!!!!\n",
- __func__);
+ wiphy_err(wiphy, "%s: No fifo space "
+ "!!\n", __func__);
p = NULL;
continue;
}
- p = pktq_pdeq(&qi->q, prec);
- ASSERT(p);
+ p = bcm_pktq_pdeq(&qi->q, prec);
} else {
p = NULL;
}
@@ -777,8 +721,6 @@
ini->tx_in_transit += count;
if (count) {
- WLCNTADD(ampdu->cnt->txmpdu, count);
-
/* patch up the last txh */
txh = (d11txh_t *) pkt[count - 1]->data;
mcl = le16_to_cpu(txh->MacTxControlLow);
@@ -861,22 +803,20 @@
/* set flag and plcp for fallback rate */
if (fbr) {
- WLCNTADD(ampdu->cnt->txfbr_mpdu, count);
- WLCNTINCR(ampdu->cnt->txfbr_ampdu);
mch |= TXC_AMPDU_FBR;
txh->MacTxControlHigh = cpu_to_le16(mch);
WLC_SET_MIMO_PLCP_AMPDU(plcp);
WLC_SET_MIMO_PLCP_AMPDU(txh->FragPLCPFallback);
}
- WL_AMPDU_TX("wl%d: wlc_sendampdu: count %d ampdu_len %d\n",
- wlc->pub->unit, count, ampdu_len);
+ BCMMSG(wlc->wiphy, "wl%d: count %d ampdu_len %d\n",
+ wlc->pub->unit, count, ampdu_len);
/* inform rate_sel if it this is a rate probe pkt */
frameid = le16_to_cpu(txh->TxFrameID);
if (frameid & TXFID_RATE_PROBE_MASK) {
- WL_ERROR("%s: XXX what to do with TXFID_RATE_PROBE_MASK!?\n",
- __func__);
+ wiphy_err(wiphy, "%s: XXX what to do with "
+ "TXFID_RATE_PROBE_MASK!?\n", __func__);
}
for (i = 0; i < count; i++)
wlc_txfifo(wlc, fifo, pkt[i], i == (count - 1),
@@ -887,7 +827,7 @@
return err;
}
-void BCMFASTPATH
+void
wlc_ampdu_dotxstatus(struct ampdu_info *ampdu, struct scb *scb,
struct sk_buff *p, tx_status_t *txs)
{
@@ -898,8 +838,6 @@
struct ieee80211_tx_info *tx_info;
tx_info = IEEE80211_SKB_CB(p);
- ASSERT(tx_info->flags & IEEE80211_TX_CTL_AMPDU);
- ASSERT(txs->status & TX_STATUS_AMPDU);
/* BMAC_NOTE: For the split driver, second level txstatus comes later
* So if the ACK was received then wait for the second level else just
@@ -913,22 +851,16 @@
udelay(1);
status_delay++;
if (status_delay > 10) {
- ASSERT(status_delay <= 10);
- return;
+ return; /* error condition */
}
}
- ASSERT(!(s1 & TX_STATUS_INTERMEDIATE));
- ASSERT(s1 & TX_STATUS_AMPDU);
s2 = R_REG(&wlc->regs->frmtxstatus2);
}
if (likely(scb)) {
- ASSERT(scb->magic == SCB_MAGIC);
scb_ampdu = SCB_AMPDU_CUBBY(ampdu, scb);
- ASSERT(scb_ampdu);
ini = SCB_AMPDU_INI(scb_ampdu, p->priority);
- ASSERT(ini->scb == scb);
wlc_ampdu_dotxstatus_complete(ampdu, scb, p, txs, s1, s2);
} else {
/* loop through all pkts and free */
@@ -939,21 +871,19 @@
tx_info = IEEE80211_SKB_CB(p);
txh = (d11txh_t *) p->data;
mcl = le16_to_cpu(txh->MacTxControlLow);
- ASSERT(tx_info->flags & IEEE80211_TX_CTL_AMPDU);
- pkt_buf_free_skb(p);
+ bcm_pkt_buf_free_skb(p);
/* break out if last packet of ampdu */
if (((mcl & TXC_AMPDU_MASK) >> TXC_AMPDU_SHIFT) ==
TXC_AMPDU_LAST)
break;
p = GETNEXTTXP(wlc, queue);
- ASSERT(p != NULL);
}
wlc_txfifo_complete(wlc, queue, ampdu->txpkt_weight);
}
wlc_ampdu_txflowcontrol(wlc, scb_ampdu, ini);
}
-void
+static void
rate_status(struct wlc_info *wlc, struct ieee80211_tx_info *tx_info,
tx_status_t *txs, u8 mcs)
{
@@ -969,7 +899,7 @@
#define SHORTNAME "AMPDU status"
-static void BCMFASTPATH
+static void
wlc_ampdu_dotxstatus_complete(struct ampdu_info *ampdu, struct scb *scb,
struct sk_buff *p, tx_status_t *txs,
u32 s1, u32 s2)
@@ -991,30 +921,21 @@
u8 antselid = 0;
u8 retry_limit, rr_retry_limit;
struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(p);
+ struct wiphy *wiphy = wlc->wiphy;
#ifdef BCMDBG
u8 hole[AMPDU_MAX_MPDU];
memset(hole, 0, sizeof(hole));
#endif
- ASSERT(tx_info->flags & IEEE80211_TX_CTL_AMPDU);
- ASSERT(txs->status & TX_STATUS_AMPDU);
-
scb_ampdu = SCB_AMPDU_CUBBY(ampdu, scb);
- ASSERT(scb_ampdu);
-
tid = (u8) (p->priority);
ini = SCB_AMPDU_INI(scb_ampdu, tid);
retry_limit = ampdu->retry_limit_tid[tid];
rr_retry_limit = ampdu->rr_retry_limit_tid[tid];
-
- ASSERT(ini->scb == scb);
-
memset(bitmap, 0, sizeof(bitmap));
queue = txs->frameid & TXFID_QUEUE_MASK;
- ASSERT(queue < AC_COUNT);
-
supr_status = txs->status & TX_STATUS_SUPR_MASK;
if (txs->status & TX_STATUS_ACK_RCV) {
@@ -1022,13 +943,13 @@
update_rate = false;
}
- ASSERT(txs->status & TX_STATUS_INTERMEDIATE);
+ WARN_ON(!(txs->status & TX_STATUS_INTERMEDIATE));
start_seq = txs->sequence >> SEQNUM_SHIFT;
bitmap[0] = (txs->status & TX_STATUS_BA_BMAP03_MASK) >>
TX_STATUS_BA_BMAP03_SHIFT;
- ASSERT(!(s1 & TX_STATUS_INTERMEDIATE));
- ASSERT(s1 & TX_STATUS_AMPDU);
+ WARN_ON(s1 & TX_STATUS_INTERMEDIATE);
+ WARN_ON(!(s1 & TX_STATUS_AMPDU));
bitmap[0] |=
(s1 & TX_STATUS_BA_BMAP47_MASK) <<
@@ -1044,30 +965,24 @@
ba_recd = true;
} else {
- WLCNTINCR(ampdu->cnt->noba);
if (supr_status) {
update_rate = false;
if (supr_status == TX_STATUS_SUPR_BADCH) {
- WL_ERROR("%s: Pkt tx suppressed, illegal channel possibly %d\n",
- __func__,
- CHSPEC_CHANNEL(wlc->default_bss->chanspec));
+ wiphy_err(wiphy, "%s: Pkt tx suppressed, "
+ "illegal channel possibly %d\n",
+ __func__, CHSPEC_CHANNEL(
+ wlc->default_bss->chanspec));
} else {
- if (supr_status == TX_STATUS_SUPR_FRAG)
- WL_NONE("%s: AMPDU frag err\n",
- __func__);
- else
- WL_ERROR("%s: wlc_ampdu_dotxstatus: supr_status 0x%x\n",
+ if (supr_status != TX_STATUS_SUPR_FRAG)
+ wiphy_err(wiphy, "%s: wlc_ampdu_dotx"
+ "status:supr_status 0x%x\n",
__func__, supr_status);
}
/* no need to retry for badch; will fail again */
if (supr_status == TX_STATUS_SUPR_BADCH ||
supr_status == TX_STATUS_SUPR_EXPTIME) {
retry = false;
- wlc->pub->_cnt->txchanrej++;
} else if (supr_status == TX_STATUS_SUPR_EXPTIME) {
-
- wlc->pub->_cnt->txexptime++;
-
/* TX underflow : try tuning pre-loading or ampdu size */
} else if (supr_status == TX_STATUS_SUPR_FRAG) {
/* if there were underflows, but pre-loading is not active,
@@ -1080,12 +995,12 @@
}
} else if (txs->phyerr) {
update_rate = false;
- wlc->pub->_cnt->txphyerr++;
- WL_ERROR("wl%d: wlc_ampdu_dotxstatus: tx phy error (0x%x)\n",
- wlc->pub->unit, txs->phyerr);
+ wiphy_err(wiphy, "wl%d: wlc_ampdu_dotxstatus: tx phy "
+ "error (0x%x)\n", wlc->pub->unit,
+ txs->phyerr);
if (WL_ERROR_ON()) {
- prpkt("txpkt (AMPDU)", p);
+ bcm_prpkt("txpkt (AMPDU)", p);
wlc_print_txdesc((d11txh_t *) p->data);
}
wlc_print_txstatus(txs);
@@ -1095,7 +1010,6 @@
/* loop through all pkts and retry if not acked */
while (p) {
tx_info = IEEE80211_SKB_CB(p);
- ASSERT(tx_info->flags & IEEE80211_TX_CTL_AMPDU);
txh = (d11txh_t *) p->data;
mcl = le16_to_cpu(txh->MacTxControlLow);
plcp = (u8 *) (txh + 1);
@@ -1111,11 +1025,10 @@
ack_recd = false;
if (ba_recd) {
bindex = MODSUB_POW2(seq, start_seq, SEQNUM_MAX);
-
- WL_AMPDU_TX("%s: tid %d seq is %d, start_seq is %d, bindex is %d set %d, index %d\n",
- __func__, tid, seq, start_seq, bindex,
- isset(bitmap, bindex), index);
-
+ BCMMSG(wlc->wiphy, "tid %d seq %d,"
+ " start_seq %d, bindex %d set %d, index %d\n",
+ tid, seq, start_seq, bindex,
+ isset(bitmap, bindex), index);
/* if acked then clear bit and free packet */
if ((bindex < AMPDU_TX_BA_MAX_WSIZE)
&& isset(bitmap, bindex)) {
@@ -1123,21 +1036,12 @@
ini->txretry[index] = 0;
/* ampdu_ack_len: number of acked aggregated frames */
- /* ampdu_ack_map: block ack bit map for the aggregation */
/* ampdu_len: number of aggregated frames */
rate_status(wlc, tx_info, txs, mcs);
tx_info->flags |= IEEE80211_TX_STAT_ACK;
tx_info->flags |= IEEE80211_TX_STAT_AMPDU;
-
- /* XXX TODO: Make these accurate. */
tx_info->status.ampdu_ack_len =
- (txs->
- status & TX_STATUS_FRM_RTX_MASK) >>
- TX_STATUS_FRM_RTX_SHIFT;
- tx_info->status.ampdu_len =
- (txs->
- status & TX_STATUS_FRM_RTX_MASK) >>
- TX_STATUS_FRM_RTX_SHIFT;
+ tx_info->status.ampdu_len = 1;
skb_pull(p, D11_PHY_HDR_LEN);
skb_pull(p, D11_TXH_LEN);
@@ -1163,12 +1067,15 @@
/* Retry timeout */
ini->tx_in_transit--;
ieee80211_tx_info_clear_status(tx_info);
+ tx_info->status.ampdu_ack_len = 0;
+ tx_info->status.ampdu_len = 1;
tx_info->flags |=
IEEE80211_TX_STAT_AMPDU_NO_BACK;
skb_pull(p, D11_PHY_HDR_LEN);
skb_pull(p, D11_TXH_LEN);
- WL_ERROR("%s: BA Timeout, seq %d, in_transit %d\n",
- SHORTNAME, seq, ini->tx_in_transit);
+ wiphy_err(wiphy, "%s: BA Timeout, seq %d, in_"
+ "transit %d\n", SHORTNAME, seq,
+ ini->tx_in_transit);
ieee80211_tx_status_irqsafe(wlc->pub->ieee_hw,
p);
}
@@ -1181,12 +1088,8 @@
break;
p = GETNEXTTXP(wlc, queue);
- if (p == NULL) {
- ASSERT(p);
- break;
- }
}
- wlc_send_q(wlc, wlc->active_queue);
+ wlc_send_q(wlc);
/* update rate state */
antselid = wlc_antsel_antsel2id(wlc->asi, mimoantsel);
@@ -1194,28 +1097,6 @@
wlc_txfifo_complete(wlc, queue, ampdu->txpkt_weight);
}
-static void
-ampdu_cleanup_tid_ini(struct ampdu_info *ampdu, scb_ampdu_t *scb_ampdu, u8 tid,
- bool force)
-{
- scb_ampdu_tid_ini_t *ini;
- ini = SCB_AMPDU_INI(scb_ampdu, tid);
- if (!ini)
- return;
-
- WL_AMPDU_CTL("wl%d: ampdu_cleanup_tid_ini: tid %d\n",
- ampdu->wlc->pub->unit, tid);
-
- if (ini->tx_in_transit && !force)
- return;
-
- scb_ampdu = SCB_AMPDU_CUBBY(ampdu, ini->scb);
- ASSERT(ini == &scb_ampdu->ini[ini->tid]);
-
- /* free all buffered tx packets */
- pktq_pflush(&scb_ampdu->txq, ini->tid, true, NULL, 0);
-}
-
/* initialize the initiator code for tid */
static scb_ampdu_tid_ini_t *wlc_ampdu_init_tid_ini(struct ampdu_info *ampdu,
scb_ampdu_t *scb_ampdu,
@@ -1223,14 +1104,10 @@
{
scb_ampdu_tid_ini_t *ini;
- ASSERT(scb_ampdu);
- ASSERT(scb_ampdu->scb);
- ASSERT(SCB_AMPDU(scb_ampdu->scb));
- ASSERT(tid < AMPDU_MAX_SCB_TID);
-
/* check for per-tid control of ampdu */
if (!ampdu->ini_enable[tid]) {
- WL_ERROR("%s: Rejecting tid %d\n", __func__, tid);
+ wiphy_err(ampdu->wlc->wiphy, "%s: Rejecting tid %d\n",
+ __func__, tid);
return NULL;
}
@@ -1238,8 +1115,6 @@
ini->tid = tid;
ini->scb = scb_ampdu->scb;
ini->magic = INI_MAGIC;
- WLCNTINCR(ampdu->cnt->txaddbareq);
-
return ini;
}
@@ -1251,14 +1126,14 @@
if (on) {
if (!N_ENAB(wlc->pub)) {
- WL_AMPDU_ERR("wl%d: driver not nmode enabled\n",
- wlc->pub->unit);
- return BCME_UNSUPPORTED;
+ wiphy_err(ampdu->wlc->wiphy, "wl%d: driver not "
+ "nmode enabled\n", wlc->pub->unit);
+ return -ENOTSUPP;
}
if (!wlc_ampdu_cap(ampdu)) {
- WL_AMPDU_ERR("wl%d: device not ampdu capable\n",
- wlc->pub->unit);
- return BCME_UNSUPPORTED;
+ wiphy_err(ampdu->wlc->wiphy, "wl%d: device not "
+ "ampdu capable\n", wlc->pub->unit);
+ return -ENOTSUPP;
}
wlc->pub->_ampdu = on;
}
@@ -1295,43 +1170,6 @@
}
}
-u8 BCMFASTPATH
-wlc_ampdu_null_delim_cnt(struct ampdu_info *ampdu, struct scb *scb,
- ratespec_t rspec, int phylen)
-{
- scb_ampdu_t *scb_ampdu;
- int bytes, cnt, tmp;
- u8 tx_density;
-
- ASSERT(scb);
- ASSERT(SCB_AMPDU(scb));
-
- scb_ampdu = SCB_AMPDU_CUBBY(ampdu, scb);
- ASSERT(scb_ampdu);
-
- if (scb_ampdu->mpdu_density == 0)
- return 0;
-
- /* RSPEC2RATE is in kbps units ==> ~RSPEC2RATE/2^13 is in bytes/usec
- density x is in 2^(x-4) usec
- ==> # of bytes needed for req density = rate/2^(17-x)
- ==> # of null delimiters = ceil(ceil(rate/2^(17-x)) - phylen)/4)
- */
-
- tx_density = scb_ampdu->mpdu_density;
-
- ASSERT(tx_density <= AMPDU_MAX_MPDU_DENSITY);
- tmp = 1 << (17 - tx_density);
- bytes = CEIL(RSPEC2RATE(rspec), tmp);
-
- if (bytes > phylen) {
- cnt = CEIL(bytes - phylen, AMPDU_DELIMITER_LEN);
- ASSERT(cnt <= 255);
- return (u8) cnt;
- } else
- return 0;
-}
-
void wlc_ampdu_macaddr_upd(struct wlc_info *wlc)
{
char template[T_RAM_ACCESS_SZ * 2];
@@ -1363,17 +1201,11 @@
}
}
-struct cb_del_ampdu_pars {
- struct ieee80211_sta *sta;
- u16 tid;
-};
-
/*
* callback function that helps flushing ampdu packets from a priority queue
*/
-static bool cb_del_ampdu_pkt(void *p, int arg_a)
+static bool cb_del_ampdu_pkt(struct sk_buff *mpdu, void *arg_a)
{
- struct sk_buff *mpdu = (struct sk_buff *)p;
struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(mpdu);
struct cb_del_ampdu_pars *ampdu_pars =
(struct cb_del_ampdu_pars *)arg_a;
@@ -1406,7 +1238,7 @@
void wlc_ampdu_flush(struct wlc_info *wlc,
struct ieee80211_sta *sta, u16 tid)
{
- struct wlc_txq_info *qi = wlc->active_queue;
+ struct wlc_txq_info *qi = wlc->pkt_queue;
struct pktq *pq = &qi->q;
int prec;
struct cb_del_ampdu_pars ampdu_pars;
@@ -1414,8 +1246,8 @@
ampdu_pars.sta = sta;
ampdu_pars.tid = tid;
for (prec = 0; prec < pq->num_prec; prec++) {
- pktq_pflush(pq, prec, true, cb_del_ampdu_pkt,
- (int)&du_pars);
+ bcm_pktq_pflush(pq, prec, true, cb_del_ampdu_pkt,
+ (void *)&du_pars);
}
wlc_inval_dma_pkts(wlc->hw, sta, dma_cb_fn_ampdu);
}
diff --git a/drivers/staging/brcm80211/brcmsmac/wlc_ampdu.h b/drivers/staging/brcm80211/brcmsmac/wlc_ampdu.h
index 17e9ebc..63d403b 100644
--- a/drivers/staging/brcm80211/brcmsmac/wlc_ampdu.h
+++ b/drivers/staging/brcm80211/brcmsmac/wlc_ampdu.h
@@ -23,10 +23,7 @@
struct sk_buff **aggp, int prec);
extern void wlc_ampdu_dotxstatus(struct ampdu_info *ampdu, struct scb *scb,
struct sk_buff *p, tx_status_t *txs);
-extern void wlc_ampdu_reset(struct ampdu_info *ampdu);
extern void wlc_ampdu_macaddr_upd(struct wlc_info *wlc);
extern void wlc_ampdu_shm_upd(struct ampdu_info *ampdu);
-extern u8 wlc_ampdu_null_delim_cnt(struct ampdu_info *ampdu, struct scb *scb,
- ratespec_t rspec, int phylen);
#endif /* _wlc_ampdu_h_ */
diff --git a/drivers/staging/brcm80211/brcmsmac/wlc_antsel.c b/drivers/staging/brcm80211/brcmsmac/wlc_antsel.c
index 85a73a9..111ef32 100644
--- a/drivers/staging/brcm80211/brcmsmac/wlc_antsel.c
+++ b/drivers/staging/brcm80211/brcmsmac/wlc_antsel.c
@@ -22,7 +22,8 @@
#include <bcmdefs.h>
#include <bcmutils.h>
-#include <siutils.h>
+#include <bcmnvram.h>
+#include <aiutils.h>
#include <bcmdevs.h>
#include <sbhnddma.h>
#include <wlioctl.h>
@@ -98,8 +99,8 @@
asi = kzalloc(sizeof(struct antsel_info), GFP_ATOMIC);
if (!asi) {
- WL_ERROR("wl%d: wlc_antsel_attach: out of mem\n",
- wlc->pub->unit);
+ wiphy_err(wlc->wiphy, "wl%d: wlc_antsel_attach: out of mem\n",
+ wlc->pub->unit);
return NULL;
}
@@ -128,8 +129,8 @@
asi->antsel_avail = false;
} else {
asi->antsel_avail = false;
- WL_ERROR("wlc_antsel_attach: 2o3 board cfg invalid\n");
- ASSERT(0);
+ wiphy_err(wlc->wiphy, "wlc_antsel_attach: 2o3 "
+ "board cfg invalid\n");
}
break;
default:
@@ -200,7 +201,7 @@
}
}
-void BCMFASTPATH
+void
wlc_antsel_antcfg_get(struct antsel_info *asi, bool usedef, bool sel,
u8 antselid, u8 fbantselid, u8 *antcfg,
u8 *fbantcfg)
@@ -297,8 +298,6 @@
u8 ant_cfg;
u16 mimo_antsel;
- ASSERT(asi->antsel_type != ANTSEL_NA);
-
/* 1) Update TX antconfig for all frames that are not unicast data
* (aka default TX)
*/
diff --git a/drivers/staging/brcm80211/brcmsmac/wlc_bmac.c b/drivers/staging/brcm80211/brcmsmac/wlc_bmac.c
index 4b6e181..4534926 100644
--- a/drivers/staging/brcm80211/brcmsmac/wlc_bmac.c
+++ b/drivers/staging/brcm80211/brcmsmac/wlc_bmac.c
@@ -25,19 +25,20 @@
#include <bcmdefs.h>
#include <bcmdevs.h>
#include <bcmwifi.h>
-#include <siutils.h>
+#include <aiutils.h>
#include <bcmsrom.h>
#include <bcmotp.h>
#include <bcmutils.h>
+#include <bcmnvram.h>
#include <wlioctl.h>
#include <sbconfig.h>
#include <sbchipc.h>
#include <pcicfg.h>
#include <sbhnddma.h>
#include <hnddma.h>
-#include <hndpmu.h>
#include "wlc_types.h"
+#include "wlc_pmu.h"
#include "d11.h"
#include "wlc_cfg.h"
#include "wlc_rate.h"
@@ -200,6 +201,8 @@
static void WLBANDINITFN(wlc_ucode_bsinit) (struct wlc_hw_info *wlc_hw)
{
+ struct wiphy *wiphy = wlc_hw->wlc->wiphy;
+
/* init microcode host flags */
wlc_write_mhf(wlc_hw, wlc_hw->band->mhfs);
@@ -208,20 +211,21 @@
if (WLCISNPHY(wlc_hw->band)) {
wlc_write_inits(wlc_hw, d11n0bsinitvals16);
} else {
- WL_ERROR("%s: wl%d: unsupported phy in corerev %d\n",
- __func__, wlc_hw->unit, wlc_hw->corerev);
+ wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
+ " %d\n", __func__, wlc_hw->unit,
+ wlc_hw->corerev);
}
} else {
if (D11REV_IS(wlc_hw->corerev, 24)) {
if (WLCISLCNPHY(wlc_hw->band)) {
wlc_write_inits(wlc_hw, d11lcn0bsinitvals24);
} else
- WL_ERROR("%s: wl%d: unsupported phy in corerev %d\n",
- __func__, wlc_hw->unit,
- wlc_hw->corerev);
+ wiphy_err(wiphy, "%s: wl%d: unsupported phy in"
+ " core rev %d\n", __func__,
+ wlc_hw->unit, wlc_hw->corerev);
} else {
- WL_ERROR("%s: wl%d: unsupported corerev %d\n",
- __func__, wlc_hw->unit, wlc_hw->corerev);
+ wiphy_err(wiphy, "%s: wl%d: unsupported corerev %d\n",
+ __func__, wlc_hw->unit, wlc_hw->corerev);
}
}
}
@@ -232,12 +236,9 @@
struct wlc_hw_info *wlc_hw = wlc->hw;
u32 macintmask;
- WL_TRACE("wl%d: wlc_setband_inact\n", wlc_hw->unit);
+ BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
- ASSERT(bandunit != wlc_hw->band->bandunit);
- ASSERT(si_iscoreup(wlc_hw->sih));
- ASSERT((R_REG(&wlc_hw->regs->maccontrol) & MCTL_EN_MAC) ==
- 0);
+ WARN_ON((R_REG(&wlc_hw->regs->maccontrol) & MCTL_EN_MAC) != 0);
/* disable interrupts */
macintmask = wl_intrsoff(wlc->wl);
@@ -245,8 +246,6 @@
/* radio off */
wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
- ASSERT(wlc_hw->clk);
-
wlc_bmac_core_phy_clk(wlc_hw, OFF);
wlc_setxband(wlc_hw, bandunit);
@@ -259,7 +258,7 @@
* Return true if more frames need to be processed. false otherwise.
* Param 'bound' indicates max. # frames to process before break out.
*/
-static bool BCMFASTPATH
+static bool
wlc_bmac_recv(struct wlc_hw_info *wlc_hw, uint fifo, bool bound)
{
struct sk_buff *p;
@@ -267,10 +266,9 @@
struct sk_buff *tail = NULL;
uint n = 0;
uint bound_limit = bound ? wlc_hw->wlc->pub->tunables->rxbnd : -1;
- u32 tsf_h, tsf_l;
wlc_d11rxhdr_t *wlc_rxhdr = NULL;
- WL_TRACE("wl%d: %s\n", wlc_hw->unit, __func__);
+ BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
/* gather received frames */
while ((p = dma_rx(wlc_hw->di[fifo]))) {
@@ -286,9 +284,6 @@
break;
}
- /* get the TSF REG reading */
- wlc_bmac_read_tsf(wlc_hw, &tsf_l, &tsf_h);
-
/* post more rbufs */
dma_rxfill(wlc_hw->di[fifo]);
@@ -297,9 +292,7 @@
head = head->prev;
p->prev = NULL;
- /* record the tsf_l in wlc_rxd11hdr */
wlc_rxhdr = (wlc_d11rxhdr_t *) p->data;
- wlc_rxhdr->tsf_l = cpu_to_le32(tsf_l);
/* compute the RSSI from d11rxhdr and record it in wlc_rxd11hr */
wlc_phy_rssi_compute(wlc_hw->band->pi, wlc_rxhdr);
@@ -314,15 +307,17 @@
* Return true if another dpc needs to be re-scheduled. false otherwise.
* Param 'bounded' indicates if applicable loops should be bounded.
*/
-bool BCMFASTPATH wlc_dpc(struct wlc_info *wlc, bool bounded)
+bool wlc_dpc(struct wlc_info *wlc, bool bounded)
{
u32 macintstatus;
struct wlc_hw_info *wlc_hw = wlc->hw;
d11regs_t *regs = wlc_hw->regs;
bool fatal = false;
+ struct wiphy *wiphy = wlc->wiphy;
if (DEVICEREMOVED(wlc)) {
- WL_ERROR("wl%d: %s: dead chip\n", wlc_hw->unit, __func__);
+ wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
+ __func__);
wl_down(wlc->wl);
return false;
}
@@ -331,13 +326,10 @@
macintstatus = wlc->macintstatus;
wlc->macintstatus = 0;
- WL_TRACE("wl%d: wlc_dpc: macintstatus 0x%x\n",
- wlc_hw->unit, macintstatus);
+ BCMMSG(wlc->wiphy, "wl%d: macintstatus 0x%x\n",
+ wlc_hw->unit, macintstatus);
- if (macintstatus & MI_PRQ) {
- /* Process probe request FIFO */
- ASSERT(0 && "PRQ Interrupt in non-MBSS");
- }
+ WARN_ON(macintstatus & MI_PRQ); /* PRQ Interrupt in non-MBSS */
/* BCN template is available */
/* ZZZ: Use AP_ACTIVE ? */
@@ -355,7 +347,7 @@
if (wlc_bmac_txstatus(wlc->hw, bounded, &fatal))
wlc->macintstatus |= MI_TFS;
if (fatal) {
- WL_ERROR("MI_TFS: fatal\n");
+ wiphy_err(wiphy, "MI_TFS: fatal\n");
goto fatal;
}
}
@@ -365,17 +357,11 @@
/* ATIM window end */
if (macintstatus & MI_ATIMWINEND) {
- WL_TRACE("wlc_isr: end of ATIM window\n");
-
+ BCMMSG(wlc->wiphy, "end of ATIM window\n");
OR_REG(®s->maccommand, wlc->qvalid);
wlc->qvalid = 0;
}
- /* phy tx error */
- if (macintstatus & MI_PHYTXERR) {
- wlc->pub->_cnt->txphyerr++;
- }
-
/* received data or control frame, MI_DMAINT is indication of RX_FIFO interrupt */
if (macintstatus & MI_DMAINT) {
if (wlc_bmac_recv(wlc_hw, RX_FIFO, bounded)) {
@@ -386,7 +372,7 @@
/* TX FIFO suspend/flush completion */
if (macintstatus & MI_TXSTOP) {
if (wlc_bmac_tx_fifo_suspended(wlc_hw, TX_DATA_FIFO)) {
- /* WL_ERROR("dpc: fifo_suspend_comlete\n"); */
+ /* wiphy_err(wiphy, "dpc: fifo_suspend_comlete\n"); */
}
}
@@ -396,15 +382,12 @@
}
if (macintstatus & MI_GP0) {
- WL_ERROR("wl%d: PSM microcode watchdog fired at %d (seconds). Resetting.\n",
- wlc_hw->unit, wlc_hw->now);
+ wiphy_err(wiphy, "wl%d: PSM microcode watchdog fired at %d "
+ "(seconds). Resetting.\n", wlc_hw->unit, wlc_hw->now);
printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n",
__func__, wlc_hw->sih->chip,
wlc_hw->sih->chiprev);
-
- wlc->pub->_cnt->psmwds++;
-
/* big hammer */
wl_init(wlc->wl);
}
@@ -415,20 +398,14 @@
}
if (macintstatus & MI_RFDISABLE) {
- WL_TRACE("wl%d: BMAC Detected a change on the RF Disable Input\n", wlc_hw->unit);
-
- wlc->pub->_cnt->rfdisable++;
+ BCMMSG(wlc->wiphy, "wl%d: BMAC Detected a change on the"
+ " RF Disable Input\n", wlc_hw->unit);
wl_rfkill_set_hw_state(wlc->wl);
}
/* send any enq'd tx packets. Just makes sure to jump start tx */
- if (!pktq_empty(&wlc->active_queue->q))
- wlc_send_q(wlc, wlc->active_queue);
-
- ASSERT(wlc_ps_check(wlc));
-
- /* make sure the bound indication and the implementation are in sync */
- ASSERT(bounded == true || wlc->macintstatus == 0);
+ if (!pktq_empty(&wlc->pkt_queue->q))
+ wlc_send_q(wlc);
/* it isn't done and needs to be resched if macintstatus is non-zero */
return wlc->macintstatus != 0;
@@ -444,7 +421,7 @@
struct wlc_info *wlc = (struct wlc_info *) arg;
struct wlc_hw_info *wlc_hw = wlc->hw;
- WL_TRACE("wl%d: wlc_bmac_watchdog\n", wlc_hw->unit);
+ BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
if (!wlc_hw->up)
return;
@@ -467,8 +444,7 @@
{
uint bandunit;
- WL_TRACE("wl%d: wlc_bmac_set_chanspec 0x%x\n",
- wlc_hw->unit, chanspec);
+ BCMMSG(wlc_hw->wlc->wiphy, "wl%d: 0x%x\n", wlc_hw->unit, chanspec);
wlc_hw->chanspec = chanspec;
@@ -522,6 +498,7 @@
struct wlc_hw_info *wlc_hw = wlc->hw;
uint unit = wlc_hw->unit;
wlc_tunables_t *tune = wlc->pub->tunables;
+ struct wiphy *wiphy = wlc->wiphy;
/* name and offsets for dma_attach */
snprintf(name, sizeof(name), "wl%d", unit);
@@ -537,8 +514,8 @@
dma_addrwidth(wlc_hw->sih, DMAREG(wlc_hw, DMA_TX, 0));
if (!wl_alloc_dma_resources(wlc_hw->wlc->wl, addrwidth)) {
- WL_ERROR("wl%d: wlc_attach: alloc_dma_resources failed\n",
- unit);
+ wiphy_err(wiphy, "wl%d: wlc_attach: alloc_dma_"
+ "resources failed\n", unit);
return false;
}
@@ -547,8 +524,6 @@
* TX: TX_AC_BK_FIFO (TX AC Background data packets)
* RX: RX_FIFO (RX data packets)
*/
- ASSERT(TX_AC_BK_FIFO == 0);
- ASSERT(RX_FIFO == 0);
wlc_hw->di[0] = dma_attach(name, wlc_hw->sih,
(wme ? DMAREG(wlc_hw, DMA_TX, 0) :
NULL), DMAREG(wlc_hw, DMA_RX, 0),
@@ -563,8 +538,6 @@
* (legacy) TX_DATA_FIFO (TX data packets)
* RX: UNUSED
*/
- ASSERT(TX_AC_BE_FIFO == 1);
- ASSERT(TX_DATA_FIFO == 1);
wlc_hw->di[1] = dma_attach(name, wlc_hw->sih,
DMAREG(wlc_hw, DMA_TX, 1), NULL,
tune->ntxd, 0, 0, -1, 0, 0,
@@ -576,7 +549,6 @@
* TX: TX_AC_VI_FIFO (TX AC Video data packets)
* RX: UNUSED
*/
- ASSERT(TX_AC_VI_FIFO == 2);
wlc_hw->di[2] = dma_attach(name, wlc_hw->sih,
DMAREG(wlc_hw, DMA_TX, 2), NULL,
tune->ntxd, 0, 0, -1, 0, 0,
@@ -587,8 +559,6 @@
* TX: TX_AC_VO_FIFO (TX AC Voice data packets)
* (legacy) TX_CTL_FIFO (TX control & mgmt packets)
*/
- ASSERT(TX_AC_VO_FIFO == 3);
- ASSERT(TX_CTL_FIFO == 3);
wlc_hw->di[3] = dma_attach(name, wlc_hw->sih,
DMAREG(wlc_hw, DMA_TX, 3),
NULL, tune->ntxd, 0, 0, -1,
@@ -597,7 +567,8 @@
/* Cleaner to leave this as if with AP defined */
if (dma_attach_err) {
- WL_ERROR("wl%d: wlc_attach: dma_attach failed\n", unit);
+ wiphy_err(wiphy, "wl%d: wlc_attach: dma_attach failed"
+ "\n", unit);
return false;
}
@@ -644,11 +615,10 @@
uint j;
bool wme = false;
shared_phy_params_t sha_params;
+ struct wiphy *wiphy = wlc->wiphy;
- WL_TRACE("wl%d: wlc_bmac_attach: vendor 0x%x device 0x%x\n",
- unit, vendor, device);
-
- ASSERT(sizeof(wlc_d11rxhdr_t) <= WL_HWRXOFF);
+ BCMMSG(wlc->wiphy, "wl%d: vendor 0x%x device 0x%x\n", unit, vendor,
+ device);
wme = true;
@@ -666,10 +636,11 @@
* Also initialize software state that depends on the particular hardware
* we are running.
*/
- wlc_hw->sih = si_attach((uint) device, regsva, bustype, btparam,
+ wlc_hw->sih = ai_attach((uint) device, regsva, bustype, btparam,
&wlc_hw->vars, &wlc_hw->vars_size);
if (wlc_hw->sih == NULL) {
- WL_ERROR("wl%d: wlc_bmac_attach: si_attach failed\n", unit);
+ wiphy_err(wiphy, "wl%d: wlc_bmac_attach: si_attach failed\n",
+ unit);
err = 11;
goto fail;
}
@@ -689,21 +660,23 @@
var = getvar(vars, "vendid");
if (var) {
vendor = (u16) simple_strtoul(var, NULL, 0);
- WL_ERROR("Overriding vendor id = 0x%x\n", vendor);
+ wiphy_err(wiphy, "Overriding vendor id = 0x%x\n",
+ vendor);
}
var = getvar(vars, "devid");
if (var) {
u16 devid = (u16) simple_strtoul(var, NULL, 0);
if (devid != 0xffff) {
device = devid;
- WL_ERROR("Overriding device id = 0x%x\n",
- device);
+ wiphy_err(wiphy, "Overriding device id = 0x%x"
+ "\n", device);
}
}
/* verify again the device is supported */
if (!wlc_chipmatch(vendor, device)) {
- WL_ERROR("wl%d: wlc_bmac_attach: Unsupported vendor/device (0x%x/0x%x)\n",
+ wiphy_err(wiphy, "wl%d: wlc_bmac_attach: Unsupported "
+ "vendor/device (0x%x/0x%x)\n",
unit, vendor, device);
err = 12;
goto fail;
@@ -714,8 +687,8 @@
wlc_hw->deviceid = device;
/* set bar0 window to point at D11 core */
- wlc_hw->regs = (d11regs_t *) si_setcore(wlc_hw->sih, D11_CORE_ID, 0);
- wlc_hw->corerev = si_corerev(wlc_hw->sih);
+ wlc_hw->regs = (d11regs_t *) ai_setcore(wlc_hw->sih, D11_CORE_ID, 0);
+ wlc_hw->corerev = ai_corerev(wlc_hw->sih);
regs = wlc_hw->regs;
@@ -728,7 +701,7 @@
}
/* initialize power control registers */
- si_clkctl_init(wlc_hw->sih);
+ ai_clkctl_init(wlc_hw->sih);
/* request fastclock and force fastclock for the rest of attach
* bring the d11 core out of reset.
@@ -739,8 +712,8 @@
wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
if (!wlc_bmac_validate_chip_access(wlc_hw)) {
- WL_ERROR("wl%d: wlc_bmac_attach: validate_chip_access failed\n",
- unit);
+ wiphy_err(wiphy, "wl%d: wlc_bmac_attach: validate_chip_access "
+ "failed\n", unit);
err = 14;
goto fail;
}
@@ -752,7 +725,8 @@
j = BOARDREV_PROMOTED;
wlc_hw->boardrev = (u16) j;
if (!wlc_validboardtype(wlc_hw)) {
- WL_ERROR("wl%d: wlc_bmac_attach: Unsupported Broadcom board type (0x%x)" " or revision level (0x%x)\n",
+ wiphy_err(wiphy, "wl%d: wlc_bmac_attach: Unsupported Broadcom "
+ "board type (0x%x)" " or revision level (0x%x)\n",
unit, wlc_hw->sih->boardtype, wlc_hw->boardrev);
err = 15;
goto fail;
@@ -765,7 +739,7 @@
wlc_bmac_pllreq(wlc_hw, true, WLC_PLLREQ_SHARED);
if ((wlc_hw->sih->bustype == PCI_BUS)
- && (si_pci_war16165(wlc_hw->sih)))
+ && (ai_pci_war16165(wlc_hw->sih)))
wlc->war16165 = true;
/* check device id(srom, nvram etc.) to set bands */
@@ -794,8 +768,8 @@
wlc_hw->physhim = wlc_phy_shim_attach(wlc_hw, wlc->wl, wlc);
if (wlc_hw->physhim == NULL) {
- WL_ERROR("wl%d: wlc_bmac_attach: wlc_phy_shim_attach failed\n",
- unit);
+ wiphy_err(wiphy, "wl%d: wlc_bmac_attach: wlc_phy_shim_attach "
+ "failed\n", unit);
err = 25;
goto fail;
}
@@ -844,23 +818,22 @@
wlc_hw->band->bandtype = j ? WLC_BAND_5G : WLC_BAND_2G;
wlc->band->bandunit = j;
wlc->band->bandtype = j ? WLC_BAND_5G : WLC_BAND_2G;
- wlc->core->coreidx = si_coreidx(wlc_hw->sih);
+ wlc->core->coreidx = ai_coreidx(wlc_hw->sih);
wlc_hw->machwcap = R_REG(®s->machwcap);
wlc_hw->machwcap_backup = wlc_hw->machwcap;
/* init tx fifo size */
- ASSERT((wlc_hw->corerev - XMTFIFOTBL_STARTREV) <
- ARRAY_SIZE(xmtfifo_sz));
wlc_hw->xmtfifo_sz =
xmtfifo_sz[(wlc_hw->corerev - XMTFIFOTBL_STARTREV)];
/* Get a phy for this band */
wlc_hw->band->pi = wlc_phy_attach(wlc_hw->phy_sh,
- (void *)regs, wlc_bmac_bandtype(wlc_hw), vars);
+ (void *)regs, wlc_bmac_bandtype(wlc_hw), vars,
+ wlc->wiphy);
if (wlc_hw->band->pi == NULL) {
- WL_ERROR("wl%d: wlc_bmac_attach: wlc_phy_attach failed\n",
- unit);
+ wiphy_err(wiphy, "wl%d: wlc_bmac_attach: wlc_phy_"
+ "attach failed\n", unit);
err = 17;
goto fail;
}
@@ -890,9 +863,9 @@
goto bad_phy;
} else {
bad_phy:
- WL_ERROR("wl%d: wlc_bmac_attach: unsupported phy type/rev (%d/%d)\n",
- unit,
- wlc_hw->band->phytype, wlc_hw->band->phyrev);
+ wiphy_err(wiphy, "wl%d: wlc_bmac_attach: unsupported "
+ "phy type/rev (%d/%d)\n", unit,
+ wlc_hw->band->phytype, wlc_hw->band->phyrev);
err = 18;
goto fail;
}
@@ -925,10 +898,10 @@
/* Match driver "down" state */
if (wlc_hw->sih->bustype == PCI_BUS)
- si_pci_down(wlc_hw->sih);
+ ai_pci_down(wlc_hw->sih);
/* register sb interrupt callback functions */
- si_register_intr_callback(wlc_hw->sih, (void *)wlc_wlintrsoff,
+ ai_register_intr_callback(wlc_hw->sih, (void *)wlc_wlintrsoff,
(void *)wlc_wlintrsrestore, NULL, wlc);
/* turn off pll and xtal to match driver "down" state */
@@ -947,27 +920,30 @@
/* init etheraddr state variables */
macaddr = wlc_get_macaddr(wlc_hw);
if (macaddr == NULL) {
- WL_ERROR("wl%d: wlc_bmac_attach: macaddr not found\n", unit);
+ wiphy_err(wiphy, "wl%d: wlc_bmac_attach: macaddr not found\n",
+ unit);
err = 21;
goto fail;
}
bcm_ether_atoe(macaddr, wlc_hw->etheraddr);
if (is_broadcast_ether_addr(wlc_hw->etheraddr) ||
is_zero_ether_addr(wlc_hw->etheraddr)) {
- WL_ERROR("wl%d: wlc_bmac_attach: bad macaddr %s\n",
- unit, macaddr);
+ wiphy_err(wiphy, "wl%d: wlc_bmac_attach: bad macaddr %s\n",
+ unit, macaddr);
err = 22;
goto fail;
}
- WL_TRACE("%s:: deviceid 0x%x nbands %d board 0x%x macaddr: %s\n",
- __func__, wlc_hw->deviceid, wlc_hw->_nbands,
+ BCMMSG(wlc->wiphy,
+ "deviceid 0x%x nbands %d board 0x%x macaddr: %s\n",
+ wlc_hw->deviceid, wlc_hw->_nbands,
wlc_hw->sih->boardtype, macaddr);
return err;
fail:
- WL_ERROR("wl%d: wlc_bmac_attach: failed with err %d\n", unit, err);
+ wiphy_err(wiphy, "wl%d: wlc_bmac_attach: failed with err %d\n", unit,
+ err);
return err;
}
@@ -1011,10 +987,10 @@
/* detach interrupt sync mechanism since interrupt is disabled and per-port
* interrupt object may has been freed. this must be done before sb core switch
*/
- si_deregister_intr_callback(wlc_hw->sih);
+ ai_deregister_intr_callback(wlc_hw->sih);
if (wlc_hw->sih->bustype == PCI_BUS)
- si_pci_sleep(wlc_hw->sih);
+ ai_pci_sleep(wlc_hw->sih);
}
wlc_bmac_detach_dmapio(wlc_hw);
@@ -1039,7 +1015,7 @@
wlc_hw->vars = NULL;
if (wlc_hw->sih) {
- si_detach(wlc_hw->sih);
+ ai_detach(wlc_hw->sih);
wlc_hw->sih = NULL;
}
@@ -1049,9 +1025,7 @@
void wlc_bmac_reset(struct wlc_hw_info *wlc_hw)
{
- WL_TRACE("wl%d: wlc_bmac_reset\n", wlc_hw->unit);
-
- wlc_hw->wlc->pub->_cnt->reset++;
+ BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
/* reset the core */
if (!DEVICEREMOVED(wlc_hw->wlc))
@@ -1070,7 +1044,7 @@
bool fastclk;
struct wlc_info *wlc = wlc_hw->wlc;
- WL_TRACE("wl%d: wlc_bmac_init\n", wlc_hw->unit);
+ BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
/* request FAST clock if not on */
fastclk = wlc_hw->forcefastclk;
@@ -1119,16 +1093,14 @@
{
uint coremask;
- WL_TRACE("wl%d: %s:\n", wlc_hw->unit, __func__);
-
- ASSERT(wlc_hw->wlc->pub->hw_up && wlc_hw->wlc->macintmask == 0);
+ BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
/*
* Enable pll and xtal, initialize the power control registers,
* and force fastclock for the remainder of wlc_up().
*/
wlc_bmac_xtal(wlc_hw, ON);
- si_clkctl_init(wlc_hw->sih);
+ ai_clkctl_init(wlc_hw->sih);
wlc_clkctl_clk(wlc_hw, CLK_FAST);
/*
@@ -1138,9 +1110,7 @@
coremask = (1 << wlc_hw->wlc->core->coreidx);
if (wlc_hw->sih->bustype == PCI_BUS)
- si_pci_setup(wlc_hw->sih, coremask);
-
- ASSERT(si_coreid(wlc_hw->sih) == D11_CORE_ID);
+ ai_pci_setup(wlc_hw->sih, coremask);
/*
* Need to read the hwradio status here to cover the case where the system
@@ -1149,13 +1119,13 @@
if (wlc_bmac_radio_read_hwdisabled(wlc_hw)) {
/* put SB PCI in down state again */
if (wlc_hw->sih->bustype == PCI_BUS)
- si_pci_down(wlc_hw->sih);
+ ai_pci_down(wlc_hw->sih);
wlc_bmac_xtal(wlc_hw, OFF);
- return BCME_RADIOOFF;
+ return -ENOMEDIUM;
}
if (wlc_hw->sih->bustype == PCI_BUS)
- si_pci_up(wlc_hw->sih);
+ ai_pci_up(wlc_hw->sih);
/* reset the d11 core */
wlc_bmac_corereset(wlc_hw, WLC_USE_COREFLAGS);
@@ -1165,14 +1135,13 @@
int wlc_bmac_up_finish(struct wlc_hw_info *wlc_hw)
{
- WL_TRACE("wl%d: %s:\n", wlc_hw->unit, __func__);
+ BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
wlc_hw->up = true;
wlc_phy_hw_state_upd(wlc_hw->band->pi, true);
/* FULLY enable dynamic power control and d11 core interrupt */
wlc_clkctl_clk(wlc_hw, CLK_DYNAMIC);
- ASSERT(wlc_hw->wlc->macintmask == 0);
wl_intrson(wlc_hw->wlc->wl);
return 0;
}
@@ -1182,7 +1151,7 @@
bool dev_gone;
uint callbacks = 0;
- WL_TRACE("wl%d: %s:\n", wlc_hw->unit, __func__);
+ BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
if (!wlc_hw->up)
return callbacks;
@@ -1210,7 +1179,7 @@
uint callbacks = 0;
bool dev_gone;
- WL_TRACE("wl%d: %s:\n", wlc_hw->unit, __func__);
+ BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
if (!wlc_hw->up)
return callbacks;
@@ -1230,7 +1199,7 @@
} else {
/* Reset and disable the core */
- if (si_iscoreup(wlc_hw->sih)) {
+ if (ai_iscoreup(wlc_hw->sih)) {
if (R_REG(&wlc_hw->regs->maccontrol) &
MCTL_EN_MAC)
wlc_suspend_mac_and_wait(wlc_hw->wlc);
@@ -1241,7 +1210,7 @@
/* turn off primary xtal and pll */
if (!wlc_hw->noreset) {
if (wlc_hw->sih->bustype == PCI_BUS)
- si_pci_down(wlc_hw->sih);
+ ai_pci_down(wlc_hw->sih);
wlc_bmac_xtal(wlc_hw, OFF);
}
}
@@ -1257,8 +1226,6 @@
/* wait until ucode is no longer asleep */
SPINWAIT((wlc_bmac_read_shm(wlc_hw, M_UCODE_DBGST) ==
DBGST_ASLEEP), wlc_hw->wlc->fastpwrup_dly);
-
- ASSERT(wlc_bmac_read_shm(wlc_hw, M_UCODE_DBGST) != DBGST_ASLEEP);
}
void wlc_bmac_hw_etheraddr(struct wlc_hw_info *wlc_hw, u8 *ea)
@@ -1292,9 +1259,9 @@
(&wlc_hw->regs->
clk_ctl_st) & CCS_HTAVAIL) == 0),
PMU_MAX_TRANSITION_DLY);
- ASSERT(R_REG
- (&wlc_hw->regs->
- clk_ctl_st) & CCS_HTAVAIL);
+ WARN_ON(!(R_REG
+ (&wlc_hw->regs->
+ clk_ctl_st) & CCS_HTAVAIL));
} else {
if ((wlc_hw->sih->pmurev == 0) &&
(R_REG
@@ -1316,11 +1283,12 @@
* then use FCA to verify mac is running fast clock
*/
- wlc_hw->forcefastclk = si_clkctl_cc(wlc_hw->sih, mode);
+ wlc_hw->forcefastclk = ai_clkctl_cc(wlc_hw->sih, mode);
/* check fast clock is available (if core is not in reset) */
if (wlc_hw->forcefastclk && wlc_hw->clk)
- ASSERT(si_core_sflags(wlc_hw->sih, 0, 0) & SISF_FCLKA);
+ WARN_ON(!(ai_core_sflags(wlc_hw->sih, 0, 0) &
+ SISF_FCLKA));
/* keep the ucode wake bit on if forcefastclk is on
* since we do not want ucode to put us back to slow clock
@@ -1382,9 +1350,8 @@
};
struct wlc_hwband *band;
- ASSERT((val & ~mask) == 0);
- ASSERT(idx < MHFMAX);
- ASSERT(ARRAY_SIZE(addr) == MHFMAX);
+ if ((val & ~mask) || idx >= MHFMAX)
+ return; /* error condition */
switch (bands) {
/* Current band only or all bands,
@@ -1401,8 +1368,7 @@
band = wlc_hw->bandstate[BAND_2G_INDEX];
break;
default:
- ASSERT(0);
- band = NULL;
+ band = NULL; /* error condition */
}
if (band) {
@@ -1429,8 +1395,9 @@
u16 wlc_bmac_mhf_get(struct wlc_hw_info *wlc_hw, u8 idx, int bands)
{
struct wlc_hwband *band;
- ASSERT(idx < MHFMAX);
+ if (idx >= MHFMAX)
+ return 0; /* error condition */
switch (bands) {
case WLC_BAND_AUTO:
band = wlc_hw->band;
@@ -1442,8 +1409,7 @@
band = wlc_hw->bandstate[BAND_2G_INDEX];
break;
default:
- ASSERT(0);
- band = NULL;
+ band = NULL; /* error condition */
}
if (!band)
@@ -1460,8 +1426,6 @@
M_HOST_FLAGS5
};
- ASSERT(ARRAY_SIZE(addr) == MHFMAX);
-
for (idx = 0; idx < MHFMAX; idx++) {
wlc_bmac_write_shm(wlc_hw, addr[idx], mhfs[idx]);
}
@@ -1486,8 +1450,8 @@
u32 maccontrol;
u32 new_maccontrol;
- ASSERT((val & ~mask) == 0);
-
+ if (val & ~mask)
+ return; /* error condition */
maccontrol = wlc_hw->maccontrol;
new_maccontrol = (maccontrol & ~mask) | val;
@@ -1522,8 +1486,6 @@
void wlc_ucode_wake_override_set(struct wlc_hw_info *wlc_hw, u32 override_bit)
{
- ASSERT((wlc_hw->wake_override & override_bit) == 0);
-
if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE)) {
mboolset(wlc_hw->wake_override, override_bit);
return;
@@ -1539,8 +1501,6 @@
void wlc_ucode_wake_override_clear(struct wlc_hw_info *wlc_hw, u32 override_bit)
{
- ASSERT(wlc_hw->wake_override & override_bit);
-
mboolclr(wlc_hw->wake_override, override_bit);
if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE))
@@ -1591,33 +1551,6 @@
}
/*
- * Write a MAC address to the rcmta structure
- */
-void
-wlc_bmac_set_rcmta(struct wlc_hw_info *wlc_hw, int idx,
- const u8 *addr)
-{
- d11regs_t *regs = wlc_hw->regs;
- volatile u16 *objdata16 = (volatile u16 *)®s->objdata;
- u32 mac_hm;
- u16 mac_l;
-
- WL_TRACE("wl%d: %s\n", wlc_hw->unit, __func__);
-
- mac_hm =
- (addr[3] << 24) | (addr[2] << 16) |
- (addr[1] << 8) | addr[0];
- mac_l = (addr[5] << 8) | addr[4];
-
- W_REG(®s->objaddr, (OBJADDR_RCMTA_SEL | (idx * 2)));
- (void)R_REG(®s->objaddr);
- W_REG(®s->objdata, mac_hm);
- W_REG(®s->objaddr, (OBJADDR_RCMTA_SEL | ((idx * 2) + 1)));
- (void)R_REG(®s->objaddr);
- W_REG(objdata16, mac_l);
-}
-
-/*
* Write a MAC address to the given match reg offset in the RXE match engine.
*/
void
@@ -1629,9 +1562,8 @@
u16 mac_m;
u16 mac_h;
- WL_TRACE("wl%d: wlc_bmac_set_addrmatch\n", wlc_hw->unit);
-
- ASSERT(match_reg_offset < RCM_SIZE);
+ BCMMSG(wlc_hw->wlc->wiphy, "wl%d: wlc_bmac_set_addrmatch\n",
+ wlc_hw->unit);
regs = wlc_hw->regs;
mac_l = addr[0] | (addr[1] << 8);
@@ -1653,17 +1585,9 @@
d11regs_t *regs;
u32 word;
bool be_bit;
-#ifdef IL_BIGENDIAN
- volatile u16 *dptr = NULL;
-#endif /* IL_BIGENDIAN */
- WL_TRACE("wl%d: wlc_bmac_write_template_ram\n", wlc_hw->unit);
+ BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
regs = wlc_hw->regs;
-
- ASSERT(IS_ALIGNED(offset, sizeof(u32)));
- ASSERT(IS_ALIGNED(len, sizeof(u32)));
- ASSERT((offset & ~0xffff) == 0);
-
W_REG(®s->tplatewrptr, offset);
/* if MCTL_BIGEND bit set in mac control register,
@@ -1716,8 +1640,6 @@
wlc_phy_bw_state_set(wlc_hw->band->pi, bw);
- ASSERT(wlc_hw->clk);
-
wlc_bmac_phy_reset(wlc_hw);
wlc_phy_init(wlc_hw->band->pi, wlc_phy_chanspec_get(wlc_hw->band->pi));
@@ -1734,7 +1656,6 @@
wlc_bmac_write_template_ram(wlc_hw, T_BCN0_TPL_BASE, (len + 3) & ~3,
bcn);
/* write beacon length to SCR */
- ASSERT(len < 65536);
wlc_bmac_write_shm(wlc_hw, M_BCN0_FRM_BYTESZ, (u16) len);
/* mark beacon0 valid */
OR_REG(®s->maccommand, MCMD_BCN0VLD);
@@ -1748,7 +1669,6 @@
wlc_bmac_write_template_ram(wlc_hw, T_BCN1_TPL_BASE, (len + 3) & ~3,
bcn);
/* write beacon length to SCR */
- ASSERT(len < 65536);
wlc_bmac_write_shm(wlc_hw, M_BCN1_FRM_BYTESZ, (u16) len);
/* mark beacon1 valid */
OR_REG(®s->maccommand, MCMD_BCN1VLD);
@@ -1772,8 +1692,6 @@
else if (!
(R_REG(®s->maccommand) & MCMD_BCN1VLD))
wlc_write_hw_bcntemplate1(wlc_hw, bcn, len);
- else /* one template should always have been available */
- ASSERT(0);
}
}
@@ -1800,15 +1718,8 @@
{
struct wlc_hw_info *wlc_hw = wlc->hw;
- WL_TRACE("wl%d: wlc_bmac_bsinit: bandunit %d\n",
- wlc_hw->unit, wlc_hw->band->bandunit);
-
- /* sanity check */
- if (PHY_TYPE(R_REG(&wlc_hw->regs->phyversion)) !=
- PHY_TYPE_LCNXN)
- ASSERT((uint)
- PHY_TYPE(R_REG(&wlc_hw->regs->phyversion))
- == wlc_hw->band->phytype);
+ BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
+ wlc_hw->band->bandunit);
wlc_ucode_bsinit(wlc_hw);
@@ -1837,23 +1748,23 @@
static void wlc_bmac_core_phy_clk(struct wlc_hw_info *wlc_hw, bool clk)
{
- WL_TRACE("wl%d: wlc_bmac_core_phy_clk: clk %d\n", wlc_hw->unit, clk);
+ BCMMSG(wlc_hw->wlc->wiphy, "wl%d: clk %d\n", wlc_hw->unit, clk);
wlc_hw->phyclk = clk;
if (OFF == clk) { /* clear gmode bit, put phy into reset */
- si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC | SICF_GMODE),
+ ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC | SICF_GMODE),
(SICF_PRST | SICF_FGC));
udelay(1);
- si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_PRST);
+ ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_PRST);
udelay(1);
} else { /* take phy out of reset */
- si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_FGC);
+ ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_FGC), SICF_FGC);
udelay(1);
- si_core_cflags(wlc_hw->sih, (SICF_FGC), 0);
+ ai_core_cflags(wlc_hw->sih, (SICF_FGC), 0);
udelay(1);
}
@@ -1862,18 +1773,18 @@
/* Perform a soft reset of the PHY PLL */
void wlc_bmac_core_phypll_reset(struct wlc_hw_info *wlc_hw)
{
- WL_TRACE("wl%d: wlc_bmac_core_phypll_reset\n", wlc_hw->unit);
+ BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
- si_corereg(wlc_hw->sih, SI_CC_IDX,
+ ai_corereg(wlc_hw->sih, SI_CC_IDX,
offsetof(chipcregs_t, chipcontrol_addr), ~0, 0);
udelay(1);
- si_corereg(wlc_hw->sih, SI_CC_IDX,
+ ai_corereg(wlc_hw->sih, SI_CC_IDX,
offsetof(chipcregs_t, chipcontrol_data), 0x4, 0);
udelay(1);
- si_corereg(wlc_hw->sih, SI_CC_IDX,
+ ai_corereg(wlc_hw->sih, SI_CC_IDX,
offsetof(chipcregs_t, chipcontrol_data), 0x4, 4);
udelay(1);
- si_corereg(wlc_hw->sih, SI_CC_IDX,
+ ai_corereg(wlc_hw->sih, SI_CC_IDX,
offsetof(chipcregs_t, chipcontrol_data), 0x4, 0);
udelay(1);
}
@@ -1888,18 +1799,18 @@
return;
if (ON == clk)
- si_core_cflags(wlc_hw->sih, SICF_FGC, SICF_FGC);
+ ai_core_cflags(wlc_hw->sih, SICF_FGC, SICF_FGC);
else
- si_core_cflags(wlc_hw->sih, SICF_FGC, 0);
+ ai_core_cflags(wlc_hw->sih, SICF_FGC, 0);
}
void wlc_bmac_macphyclk_set(struct wlc_hw_info *wlc_hw, bool clk)
{
if (ON == clk)
- si_core_cflags(wlc_hw->sih, SICF_MPCLKE, SICF_MPCLKE);
+ ai_core_cflags(wlc_hw->sih, SICF_MPCLKE, SICF_MPCLKE);
else
- si_core_cflags(wlc_hw->sih, SICF_MPCLKE, 0);
+ ai_core_cflags(wlc_hw->sih, SICF_MPCLKE, 0);
}
void wlc_bmac_phy_reset(struct wlc_hw_info *wlc_hw)
@@ -1908,7 +1819,7 @@
u32 phy_bw_clkbits;
bool phy_in_reset = false;
- WL_TRACE("wl%d: wlc_bmac_phy_reset\n", wlc_hw->unit);
+ BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
if (pih == NULL)
return;
@@ -1919,7 +1830,7 @@
if (WLCISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3) &&
NREV_LE(wlc_hw->band->phyrev, 4)) {
/* Set the PHY bandwidth */
- si_core_cflags(wlc_hw->sih, SICF_BWMASK, phy_bw_clkbits);
+ ai_core_cflags(wlc_hw->sih, SICF_BWMASK, phy_bw_clkbits);
udelay(1);
@@ -1927,12 +1838,12 @@
wlc_bmac_core_phypll_reset(wlc_hw);
/* reset the PHY */
- si_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_PCLKE),
+ ai_core_cflags(wlc_hw->sih, (SICF_PRST | SICF_PCLKE),
(SICF_PRST | SICF_PCLKE));
phy_in_reset = true;
} else {
- si_core_cflags(wlc_hw->sih,
+ ai_core_cflags(wlc_hw->sih,
(SICF_PRST | SICF_PCLKE | SICF_BWMASK),
(SICF_PRST | SICF_PCLKE | phy_bw_clkbits));
}
@@ -1951,13 +1862,9 @@
struct wlc_info *wlc = wlc_hw->wlc;
u32 macintmask;
- ASSERT(NBANDS_HW(wlc_hw) > 1);
- ASSERT(bandunit != wlc_hw->band->bandunit);
-
/* Enable the d11 core before accessing it */
- if (!si_iscoreup(wlc_hw->sih)) {
- si_core_reset(wlc_hw->sih, 0, 0);
- ASSERT(si_iscoreup(wlc_hw->sih));
+ if (!ai_iscoreup(wlc_hw->sih)) {
+ ai_core_reset(wlc_hw->sih, 0, 0);
wlc_mctrl_reset(wlc_hw);
}
@@ -1983,14 +1890,14 @@
wl_intrsrestore(wlc->wl, macintmask);
/* ucode should still be suspended.. */
- ASSERT((R_REG(&wlc_hw->regs->maccontrol) & MCTL_EN_MAC) ==
- 0);
+ WARN_ON((R_REG(&wlc_hw->regs->maccontrol) & MCTL_EN_MAC) != 0);
}
/* low-level band switch utility routine */
void WLBANDINITFN(wlc_setxband) (struct wlc_hw_info *wlc_hw, uint bandunit)
{
- WL_TRACE("wl%d: wlc_setxband: bandunit %d\n", wlc_hw->unit, bandunit);
+ BCMMSG(wlc_hw->wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
+ bandunit);
wlc_hw->band = wlc_hw->bandstate[bandunit];
@@ -1999,7 +1906,7 @@
/* set gmode core flag */
if (wlc_hw->sbclk && !wlc_hw->noreset) {
- si_core_cflags(wlc_hw->sih, SICF_GMODE,
+ ai_core_cflags(wlc_hw->sih, SICF_GMODE,
((bandunit == 0) ? SICF_GMODE : 0));
}
}
@@ -2009,7 +1916,8 @@
/* reject unsupported corerev */
if (!VALID_COREREV(wlc_hw->corerev)) {
- WL_ERROR("unsupported core rev %d\n", wlc_hw->corerev);
+ wiphy_err(wlc_hw->wlc->wiphy, "unsupported core rev %d\n",
+ wlc_hw->corerev);
return false;
}
@@ -2034,7 +1942,7 @@
goodboard = false;
}
- if (wlc_hw->sih->boardvendor != VENDOR_BROADCOM)
+ if (wlc_hw->sih->boardvendor != PCI_VENDOR_ID_BROADCOM)
return goodboard;
return goodboard;
@@ -2057,8 +1965,8 @@
macaddr = getvar(wlc_hw->vars, varname);
if (macaddr == NULL) {
- WL_ERROR("wl%d: wlc_get_macaddr: macaddr getvar(%s) not found\n",
- wlc_hw->unit, varname);
+ wiphy_err(wlc_hw->wlc->wiphy, "wl%d: wlc_get_macaddr: macaddr "
+ "getvar(%s) not found\n", wlc_hw->unit, varname);
}
return macaddr;
@@ -2094,9 +2002,9 @@
(wlc_hw->sih->chip == BCM43225_CHIP_ID) ||
(wlc_hw->sih->chip == BCM43421_CHIP_ID))
wlc_hw->regs =
- (d11regs_t *) si_setcore(wlc_hw->sih, D11_CORE_ID,
+ (d11regs_t *) ai_setcore(wlc_hw->sih, D11_CORE_ID,
0);
- si_core_reset(wlc_hw->sih, flags, resetbits);
+ ai_core_reset(wlc_hw->sih, flags, resetbits);
wlc_mctrl_reset(wlc_hw);
}
@@ -2104,7 +2012,7 @@
/* put core back into reset */
if (!clk)
- si_core_disable(wlc_hw->sih, 0);
+ ai_core_disable(wlc_hw->sih, 0);
if (!xtal)
wlc_bmac_xtal(wlc_hw, OFF);
@@ -2118,25 +2026,25 @@
if (wlc_hw->wlc->pub->hw_up)
return;
- WL_TRACE("wl%d: %s:\n", wlc_hw->unit, __func__);
+ BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
/*
* Enable pll and xtal, initialize the power control registers,
* and force fastclock for the remainder of wlc_up().
*/
wlc_bmac_xtal(wlc_hw, ON);
- si_clkctl_init(wlc_hw->sih);
+ ai_clkctl_init(wlc_hw->sih);
wlc_clkctl_clk(wlc_hw, CLK_FAST);
if (wlc_hw->sih->bustype == PCI_BUS) {
- si_pci_fixcfg(wlc_hw->sih);
+ ai_pci_fixcfg(wlc_hw->sih);
/* AI chip doesn't restore bar0win2 on hibernation/resume, need sw fixup */
if ((wlc_hw->sih->chip == BCM43224_CHIP_ID) ||
(wlc_hw->sih->chip == BCM43225_CHIP_ID) ||
(wlc_hw->sih->chip == BCM43421_CHIP_ID))
wlc_hw->regs =
- (d11regs_t *) si_setcore(wlc_hw->sih, D11_CORE_ID,
+ (d11regs_t *) ai_setcore(wlc_hw->sih, D11_CORE_ID,
0);
}
@@ -2151,7 +2059,7 @@
if (!
(wlc_hw->boardrev >= 0x1250
&& (wlc_hw->boardflags & BFL_FEM_BT)))
- si_epa_4313war(wlc_hw->sih);
+ ai_epa_4313war(wlc_hw->sih);
}
}
@@ -2179,7 +2087,7 @@
if (flags == WLC_USE_COREFLAGS)
flags = (wlc_hw->band->pi ? wlc_hw->band->core_flags : 0);
- WL_TRACE("wl%d: %s\n", wlc_hw->unit, __func__);
+ BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
regs = wlc_hw->regs;
@@ -2189,17 +2097,19 @@
wlc_clkctl_clk(wlc_hw, CLK_FAST);
/* reset the dma engines except first time thru */
- if (si_iscoreup(wlc_hw->sih)) {
+ if (ai_iscoreup(wlc_hw->sih)) {
for (i = 0; i < NFIFO; i++)
if ((wlc_hw->di[i]) && (!dma_txreset(wlc_hw->di[i]))) {
- WL_ERROR("wl%d: %s: dma_txreset[%d]: cannot stop dma\n",
- wlc_hw->unit, __func__, i);
+ wiphy_err(wlc_hw->wlc->wiphy, "wl%d: %s: "
+ "dma_txreset[%d]: cannot stop dma\n",
+ wlc_hw->unit, __func__, i);
}
if ((wlc_hw->di[RX_FIFO])
&& (!wlc_dma_rxreset(wlc_hw, RX_FIFO))) {
- WL_ERROR("wl%d: %s: dma_rxreset[%d]: cannot stop dma\n",
- wlc_hw->unit, __func__, RX_FIFO);
+ wiphy_err(wlc_hw->wlc->wiphy, "wl%d: %s: dma_rxreset"
+ "[%d]: cannot stop dma\n",
+ wlc_hw->unit, __func__, RX_FIFO);
}
}
/* if noreset, just stop the psm and return */
@@ -2224,7 +2134,7 @@
* with other driver like mips/arm since they may touch chipcommon as well.
*/
wlc_hw->clk = false;
- si_core_reset(wlc_hw->sih, flags, resetbits);
+ ai_core_reset(wlc_hw->sih, flags, resetbits);
wlc_hw->clk = true;
if (wlc_hw->band && wlc_hw->band->pi)
wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, true);
@@ -2315,10 +2225,11 @@
bool fifosz_fixup = false;
int err = 0;
u16 buf[NFIFO];
+ struct wiphy *wiphy = wlc->wiphy;
regs = wlc_hw->regs;
- WL_TRACE("wl%d: wlc_coreinit\n", wlc_hw->unit);
+ BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
/* reset PSM */
wlc_bmac_mctrl(wlc_hw, ~0, (MCTL_IHR_EN | MCTL_PSM_JMP_0 | MCTL_WAKE));
@@ -2338,29 +2249,31 @@
SPINWAIT(((R_REG(®s->macintstatus) & MI_MACSSPNDD) == 0),
1000 * 1000);
if ((R_REG(®s->macintstatus) & MI_MACSSPNDD) == 0)
- WL_ERROR("wl%d: wlc_coreinit: ucode did not self-suspend!\n",
- wlc_hw->unit);
+ wiphy_err(wiphy, "wl%d: wlc_coreinit: ucode did not self-"
+ "suspend!\n", wlc_hw->unit);
wlc_gpio_init(wlc);
- sflags = si_core_sflags(wlc_hw->sih, 0, 0);
+ sflags = ai_core_sflags(wlc_hw->sih, 0, 0);
if (D11REV_IS(wlc_hw->corerev, 23)) {
if (WLCISNPHY(wlc_hw->band))
wlc_write_inits(wlc_hw, d11n0initvals16);
else
- WL_ERROR("%s: wl%d: unsupported phy in corerev %d\n",
- __func__, wlc_hw->unit, wlc_hw->corerev);
+ wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
+ " %d\n", __func__, wlc_hw->unit,
+ wlc_hw->corerev);
} else if (D11REV_IS(wlc_hw->corerev, 24)) {
if (WLCISLCNPHY(wlc_hw->band)) {
wlc_write_inits(wlc_hw, d11lcn0initvals24);
} else {
- WL_ERROR("%s: wl%d: unsupported phy in corerev %d\n",
- __func__, wlc_hw->unit, wlc_hw->corerev);
+ wiphy_err(wiphy, "%s: wl%d: unsupported phy in corerev"
+ " %d\n", __func__, wlc_hw->unit,
+ wlc_hw->corerev);
}
} else {
- WL_ERROR("%s: wl%d: unsupported corerev %d\n",
- __func__, wlc_hw->unit, wlc_hw->corerev);
+ wiphy_err(wiphy, "%s: wl%d: unsupported corerev %d\n",
+ __func__, wlc_hw->unit, wlc_hw->corerev);
}
/* For old ucode, txfifo sizes needs to be modified(increased) */
@@ -2402,13 +2315,13 @@
err = -1;
}
if (err != 0) {
- WL_ERROR("wlc_coreinit: txfifo mismatch: ucode size %d driver size %d index %d\n",
- buf[i], wlc_hw->xmtfifo_sz[i], i);
- ASSERT(0);
+ wiphy_err(wiphy, "wlc_coreinit: txfifo mismatch: ucode size %d"
+ " driver size %d index %d\n", buf[i],
+ wlc_hw->xmtfifo_sz[i], i);
}
/* make sure we can still talk to the mac */
- ASSERT(R_REG(®s->maccontrol) != 0xffffffff);
+ WARN_ON(R_REG(®s->maccontrol) == 0xffffffff);
/* band-specific inits done by wlc_bsinit() */
@@ -2437,7 +2350,7 @@
wlc_bmac_macphyclk_set(wlc_hw, ON);
/* program dynamic clock control fast powerup delay register */
- wlc->fastpwrup_dly = si_clkctl_fast_pwrup_delay(wlc_hw->sih);
+ wlc->fastpwrup_dly = ai_clkctl_fast_pwrup_delay(wlc_hw->sih);
W_REG(®s->scc_fastpwrup_dly, wlc->fastpwrup_dly);
/* tell the ucode the corerev */
@@ -2554,7 +2467,6 @@
wlc_phy_antsel_init(wlc_hw->band->pi, false);
} else if (wlc_hw->antsel_type == ANTSEL_2x4) {
- ASSERT((gm & BOARD_GPIO_12) == 0);
gm |= gc |= (BOARD_GPIO_12 | BOARD_GPIO_13);
/*
* The board itself is powered by these GPIOs
@@ -2581,7 +2493,7 @@
gm |= gc |= BOARD_GPIO_PACTRL;
/* apply to gpiocontrol register */
- si_gpiocontrol(wlc_hw->sih, gm, gc, GPIO_DRV_PRIORITY);
+ ai_gpiocontrol(wlc_hw->sih, gm, gc, GPIO_DRV_PRIORITY);
}
static void wlc_ucode_download(struct wlc_hw_info *wlc_hw)
@@ -2598,16 +2510,18 @@
bcm43xx_16_mimosz);
wlc_hw->ucode_loaded = true;
} else
- WL_ERROR("%s: wl%d: unsupported phy in corerev %d\n",
- __func__, wlc_hw->unit, wlc_hw->corerev);
+ wiphy_err(wlc->wiphy, "%s: wl%d: unsupported phy in "
+ "corerev %d\n",
+ __func__, wlc_hw->unit, wlc_hw->corerev);
} else if (D11REV_IS(wlc_hw->corerev, 24)) {
if (WLCISLCNPHY(wlc_hw->band)) {
wlc_ucode_write(wlc_hw, bcm43xx_24_lcn,
bcm43xx_24_lcnsz);
wlc_hw->ucode_loaded = true;
} else {
- WL_ERROR("%s: wl%d: unsupported phy in corerev %d\n",
- __func__, wlc_hw->unit, wlc_hw->corerev);
+ wiphy_err(wlc->wiphy, "%s: wl%d: unsupported phy in "
+ "corerev %d\n",
+ __func__, wlc_hw->unit, wlc_hw->corerev);
}
}
}
@@ -2618,9 +2532,7 @@
uint i;
uint count;
- WL_TRACE("wl%d: wlc_ucode_write\n", wlc_hw->unit);
-
- ASSERT(IS_ALIGNED(nbytes, sizeof(u32)));
+ BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
count = (nbytes / sizeof(u32));
@@ -2636,13 +2548,11 @@
int i;
volatile u8 *base;
- WL_TRACE("wl%d: wlc_write_inits\n", wlc_hw->unit);
+ BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
base = (volatile u8 *)wlc_hw->regs;
for (i = 0; inits[i].addr != 0xffff; i++) {
- ASSERT((inits[i].size == 2) || (inits[i].size == 4));
-
if (inits[i].size == 2)
W_REG((u16 *)(base + inits[i].addr),
inits[i].value);
@@ -2700,6 +2610,7 @@
uint unit;
uint intstatus, idx;
d11regs_t *regs = wlc_hw->regs;
+ struct wiphy *wiphy = wlc_hw->wlc->wiphy;
unit = wlc_hw->unit;
@@ -2710,46 +2621,41 @@
if (!intstatus)
continue;
- WL_TRACE("wl%d: wlc_bmac_fifoerrors: intstatus%d 0x%x\n",
- unit, idx, intstatus);
+ BCMMSG(wlc_hw->wlc->wiphy, "wl%d: intstatus%d 0x%x\n",
+ unit, idx, intstatus);
if (intstatus & I_RO) {
- WL_ERROR("wl%d: fifo %d: receive fifo overflow\n",
- unit, idx);
- wlc_hw->wlc->pub->_cnt->rxoflo++;
+ wiphy_err(wiphy, "wl%d: fifo %d: receive fifo "
+ "overflow\n", unit, idx);
fatal = true;
}
if (intstatus & I_PC) {
- WL_ERROR("wl%d: fifo %d: descriptor error\n",
+ wiphy_err(wiphy, "wl%d: fifo %d: descriptor error\n",
unit, idx);
- wlc_hw->wlc->pub->_cnt->dmade++;
fatal = true;
}
if (intstatus & I_PD) {
- WL_ERROR("wl%d: fifo %d: data error\n", unit, idx);
- wlc_hw->wlc->pub->_cnt->dmada++;
+ wiphy_err(wiphy, "wl%d: fifo %d: data error\n", unit,
+ idx);
fatal = true;
}
if (intstatus & I_DE) {
- WL_ERROR("wl%d: fifo %d: descriptor protocol error\n",
- unit, idx);
- wlc_hw->wlc->pub->_cnt->dmape++;
+ wiphy_err(wiphy, "wl%d: fifo %d: descriptor protocol "
+ "error\n", unit, idx);
fatal = true;
}
if (intstatus & I_RU) {
- WL_ERROR("wl%d: fifo %d: receive descriptor underflow\n",
- idx, unit);
- wlc_hw->wlc->pub->_cnt->rxuflo[idx]++;
+ wiphy_err(wiphy, "wl%d: fifo %d: receive descriptor "
+ "underflow\n", idx, unit);
}
if (intstatus & I_XU) {
- WL_ERROR("wl%d: fifo %d: transmit fifo underflow\n",
- idx, unit);
- wlc_hw->wlc->pub->_cnt->txuflo++;
+ wiphy_err(wiphy, "wl%d: fifo %d: transmit fifo "
+ "underflow\n", idx, unit);
fatal = true;
}
@@ -2765,7 +2671,6 @@
void wlc_intrson(struct wlc_info *wlc)
{
struct wlc_hw_info *wlc_hw = wlc->hw;
- ASSERT(wlc->defmacintmask);
wlc->macintmask = wlc->defmacintmask;
W_REG(&wlc_hw->regs->macintmask, wlc->macintmask);
}
@@ -2859,7 +2764,7 @@
int wlc_bmac_xmtfifo_sz_get(struct wlc_hw_info *wlc_hw, uint fifo, uint *blocks)
{
if (fifo >= NFIFO)
- return BCME_RANGE;
+ return -EINVAL;
*blocks = wlc_hw->xmtfifo_sz[fifo];
@@ -2962,7 +2867,8 @@
/* macintstatus includes a DMA interrupt summary bit */
macintstatus = R_REG(®s->macintstatus);
- WL_TRACE("wl%d: macintstatus: 0x%x\n", wlc_hw->unit, macintstatus);
+ BCMMSG(wlc->wiphy, "wl%d: macintstatus: 0x%x\n", wlc_hw->unit,
+ macintstatus);
/* detect cardbus removed, in power down(suspend) and in reset */
if (DEVICEREMOVED(wlc))
@@ -3013,8 +2919,6 @@
{
u32 macintstatus;
- ASSERT(wlc->macintstatus != 0);
-
/* read and clear macintstatus and intstatus registers */
macintstatus = wlc_intstatus(wlc, false);
@@ -3034,7 +2938,7 @@
* *wantdpc will be set to true if further wlc_dpc() processing is required,
* false otherwise.
*/
-bool BCMFASTPATH wlc_isr(struct wlc_info *wlc, bool *wantdpc)
+bool wlc_isr(struct wlc_info *wlc, bool *wantdpc)
{
struct wlc_hw_info *wlc_hw = wlc->hw;
u32 macintstatus;
@@ -3048,7 +2952,8 @@
macintstatus = wlc_intstatus(wlc, true);
if (macintstatus == 0xffffffff)
- WL_ERROR("DEVICEREMOVED detected in the ISR code path\n");
+ wiphy_err(wlc->wiphy, "DEVICEREMOVED detected in the ISR code"
+ " path\n");
/* it is not for us */
if (macintstatus == 0)
@@ -3057,14 +2962,13 @@
*wantdpc = true;
/* save interrupt status bits */
- ASSERT(wlc->macintstatus == 0);
wlc->macintstatus = macintstatus;
return true;
}
-static bool BCMFASTPATH
+static bool
wlc_bmac_dotxstatus(struct wlc_hw_info *wlc_hw, tx_status_t *txs, u32 s2)
{
/* discard intermediate indications for ucode with one legitimate case:
@@ -3083,7 +2987,7 @@
/* process tx completion events in BMAC
* Return true if more tx status need to be processed. false otherwise.
*/
-static bool BCMFASTPATH
+static bool
wlc_bmac_txstatus(struct wlc_hw_info *wlc_hw, bool bound, bool *fatal)
{
bool morepending = false;
@@ -3098,7 +3002,7 @@
*/
uint max_tx_num = bound ? wlc->pub->tunables->txsbnd : -1;
- WL_TRACE("wl%d: wlc_bmac_txstatus\n", wlc_hw->unit);
+ BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
txs = &txstatus;
regs = wlc_hw->regs;
@@ -3106,9 +3010,8 @@
&& (s1 = R_REG(®s->frmtxstatus)) & TXS_V) {
if (s1 == 0xffffffff) {
- WL_ERROR("wl%d: %s: dead chip\n",
+ wiphy_err(wlc->wiphy, "wl%d: %s: dead chip\n",
wlc_hw->unit, __func__);
- ASSERT(s1 != 0xffffffff);
return morepending;
}
@@ -3133,8 +3036,8 @@
if (n >= max_tx_num)
morepending = true;
- if (!pktq_empty(&wlc->active_queue->q))
- wlc_send_q(wlc, wlc->active_queue);
+ if (!pktq_empty(&wlc->pkt_queue->q))
+ wlc_send_q(wlc);
return morepending;
}
@@ -3144,9 +3047,10 @@
struct wlc_hw_info *wlc_hw = wlc->hw;
d11regs_t *regs = wlc_hw->regs;
u32 mc, mi;
+ struct wiphy *wiphy = wlc->wiphy;
- WL_TRACE("wl%d: wlc_suspend_mac_and_wait: bandunit %d\n",
- wlc_hw->unit, wlc_hw->band->bandunit);
+ BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
+ wlc_hw->band->bandunit);
/*
* Track overlapping suspend requests
@@ -3161,21 +3065,23 @@
mc = R_REG(®s->maccontrol);
if (mc == 0xffffffff) {
- WL_ERROR("wl%d: %s: dead chip\n", wlc_hw->unit, __func__);
+ wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
+ __func__);
wl_down(wlc->wl);
return;
}
- ASSERT(!(mc & MCTL_PSM_JMP_0));
- ASSERT(mc & MCTL_PSM_RUN);
- ASSERT(mc & MCTL_EN_MAC);
+ WARN_ON(mc & MCTL_PSM_JMP_0);
+ WARN_ON(!(mc & MCTL_PSM_RUN));
+ WARN_ON(!(mc & MCTL_EN_MAC));
mi = R_REG(®s->macintstatus);
if (mi == 0xffffffff) {
- WL_ERROR("wl%d: %s: dead chip\n", wlc_hw->unit, __func__);
+ wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
+ __func__);
wl_down(wlc->wl);
return;
}
- ASSERT(!(mi & MI_MACSSPNDD));
+ WARN_ON(mi & MI_MACSSPNDD);
wlc_bmac_mctrl(wlc_hw, MCTL_EN_MAC, 0);
@@ -3183,24 +3089,26 @@
WLC_MAX_MAC_SUSPEND);
if (!(R_REG(®s->macintstatus) & MI_MACSSPNDD)) {
- WL_ERROR("wl%d: wlc_suspend_mac_and_wait: waited %d uS and MI_MACSSPNDD is still not on.\n",
- wlc_hw->unit, WLC_MAX_MAC_SUSPEND);
- WL_ERROR("wl%d: psmdebug 0x%08x, phydebug 0x%08x, psm_brc 0x%04x\n",
- wlc_hw->unit,
- R_REG(®s->psmdebug),
- R_REG(®s->phydebug),
- R_REG(®s->psm_brc));
+ wiphy_err(wiphy, "wl%d: wlc_suspend_mac_and_wait: waited %d uS"
+ " and MI_MACSSPNDD is still not on.\n",
+ wlc_hw->unit, WLC_MAX_MAC_SUSPEND);
+ wiphy_err(wiphy, "wl%d: psmdebug 0x%08x, phydebug 0x%08x, "
+ "psm_brc 0x%04x\n", wlc_hw->unit,
+ R_REG(®s->psmdebug),
+ R_REG(®s->phydebug),
+ R_REG(®s->psm_brc));
}
mc = R_REG(®s->maccontrol);
if (mc == 0xffffffff) {
- WL_ERROR("wl%d: %s: dead chip\n", wlc_hw->unit, __func__);
+ wiphy_err(wiphy, "wl%d: %s: dead chip\n", wlc_hw->unit,
+ __func__);
wl_down(wlc->wl);
return;
}
- ASSERT(!(mc & MCTL_PSM_JMP_0));
- ASSERT(mc & MCTL_PSM_RUN);
- ASSERT(!(mc & MCTL_EN_MAC));
+ WARN_ON(mc & MCTL_PSM_JMP_0);
+ WARN_ON(!(mc & MCTL_PSM_RUN));
+ WARN_ON(mc & MCTL_EN_MAC);
}
void wlc_enable_mac(struct wlc_info *wlc)
@@ -3209,32 +3117,31 @@
d11regs_t *regs = wlc_hw->regs;
u32 mc, mi;
- WL_TRACE("wl%d: wlc_enable_mac: bandunit %d\n",
- wlc_hw->unit, wlc->band->bandunit);
+ BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n", wlc_hw->unit,
+ wlc->band->bandunit);
/*
* Track overlapping suspend requests
*/
- ASSERT(wlc_hw->mac_suspend_depth > 0);
wlc_hw->mac_suspend_depth--;
if (wlc_hw->mac_suspend_depth > 0)
return;
mc = R_REG(®s->maccontrol);
- ASSERT(!(mc & MCTL_PSM_JMP_0));
- ASSERT(!(mc & MCTL_EN_MAC));
- ASSERT(mc & MCTL_PSM_RUN);
+ WARN_ON(mc & MCTL_PSM_JMP_0);
+ WARN_ON(mc & MCTL_EN_MAC);
+ WARN_ON(!(mc & MCTL_PSM_RUN));
wlc_bmac_mctrl(wlc_hw, MCTL_EN_MAC, MCTL_EN_MAC);
W_REG(®s->macintstatus, MI_MACSSPNDD);
mc = R_REG(®s->maccontrol);
- ASSERT(!(mc & MCTL_PSM_JMP_0));
- ASSERT(mc & MCTL_EN_MAC);
- ASSERT(mc & MCTL_PSM_RUN);
+ WARN_ON(mc & MCTL_PSM_JMP_0);
+ WARN_ON(!(mc & MCTL_EN_MAC));
+ WARN_ON(!(mc & MCTL_PSM_RUN));
mi = R_REG(®s->macintstatus);
- ASSERT(!(mi & MI_MACSSPNDD));
+ WARN_ON(mi & MI_MACSSPNDD);
wlc_ucode_wake_override_clear(wlc_hw, WLC_WAKE_OVERRIDE_MACSUSPEND);
}
@@ -3314,7 +3221,7 @@
wlc_upd_ofdm_pctl1_table(wlc_hw);
}
-void BCMFASTPATH
+void
wlc_bmac_read_tsf(struct wlc_hw_info *wlc_hw, u32 *tsf_l_ptr,
u32 *tsf_h_ptr)
{
@@ -3331,8 +3238,9 @@
{
d11regs_t *regs;
u32 w, val;
+ struct wiphy *wiphy = wlc_hw->wlc->wiphy;
- WL_TRACE("wl%d: validate_chip_access\n", wlc_hw->unit);
+ BCMMSG(wiphy, "wl%d\n", wlc_hw->unit);
regs = wlc_hw->regs;
@@ -3351,8 +3259,8 @@
(void)R_REG(®s->objaddr);
val = R_REG(®s->objdata);
if (val != (u32) 0xaa5555aa) {
- WL_ERROR("wl%d: validate_chip_access: SHM = 0x%x, expected 0xaa5555aa\n",
- wlc_hw->unit, val);
+ wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
+ "expected 0xaa5555aa\n", wlc_hw->unit, val);
return false;
}
@@ -3364,8 +3272,8 @@
(void)R_REG(®s->objaddr);
val = R_REG(®s->objdata);
if (val != (u32) 0x55aaaa55) {
- WL_ERROR("wl%d: validate_chip_access: SHM = 0x%x, expected 0x55aaaa55\n",
- wlc_hw->unit, val);
+ wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
+ "expected 0x55aaaa55\n", wlc_hw->unit, val);
return false;
}
@@ -3379,10 +3287,10 @@
w = R_REG(®s->maccontrol);
if ((w != (MCTL_IHR_EN | MCTL_WAKE)) &&
(w != (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE))) {
- WL_ERROR("wl%d: validate_chip_access: maccontrol = 0x%x, expected 0x%x or 0x%x\n",
- wlc_hw->unit, w,
- (MCTL_IHR_EN | MCTL_WAKE),
- (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE));
+ wiphy_err(wiphy, "wl%d: validate_chip_access: maccontrol = "
+ "0x%x, expected 0x%x or 0x%x\n", wlc_hw->unit, w,
+ (MCTL_IHR_EN | MCTL_WAKE),
+ (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE));
return false;
}
@@ -3396,7 +3304,7 @@
d11regs_t *regs;
u32 tmp;
- WL_TRACE("wl%d: wlc_bmac_core_phypll_ctl\n", wlc_hw->unit);
+ BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
tmp = 0;
regs = wlc_hw->regs;
@@ -3413,9 +3321,8 @@
tmp = R_REG(®s->clk_ctl_st);
if ((tmp & (CCS_ERSRC_AVAIL_HT)) !=
(CCS_ERSRC_AVAIL_HT)) {
- WL_ERROR("%s: turn on PHY PLL failed\n",
- __func__);
- ASSERT(0);
+ wiphy_err(wlc_hw->wlc->wiphy, "%s: turn on PHY"
+ " PLL failed\n", __func__);
}
} else {
OR_REG(®s->clk_ctl_st,
@@ -3431,9 +3338,8 @@
(CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
!=
(CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL)) {
- WL_ERROR("%s: turn on PHY PLL failed\n",
- __func__);
- ASSERT(0);
+ wiphy_err(wlc_hw->wlc->wiphy, "%s: turn on "
+ "PHY PLL failed\n", __func__);
}
}
} else {
@@ -3449,9 +3355,7 @@
{
bool dev_gone;
- WL_TRACE("wl%d: %s\n", wlc_hw->unit, __func__);
-
- ASSERT(!wlc_hw->up);
+ BCMMSG(wlc_hw->wlc->wiphy, "wl%d\n", wlc_hw->unit);
dev_gone = DEVICEREMOVED(wlc_hw->wlc);
@@ -3477,24 +3381,24 @@
/* remove gpio controls */
if (wlc_hw->ucode_dbgsel)
- si_gpiocontrol(wlc_hw->sih, ~0, 0, GPIO_DRV_PRIORITY);
+ ai_gpiocontrol(wlc_hw->sih, ~0, 0, GPIO_DRV_PRIORITY);
wlc_hw->clk = false;
- si_core_disable(wlc_hw->sih, 0);
+ ai_core_disable(wlc_hw->sih, 0);
wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
}
/* power both the pll and external oscillator on/off */
static void wlc_bmac_xtal(struct wlc_hw_info *wlc_hw, bool want)
{
- WL_TRACE("wl%d: wlc_bmac_xtal: want %d\n", wlc_hw->unit, want);
+ BCMMSG(wlc_hw->wlc->wiphy, "wl%d: want %d\n", wlc_hw->unit, want);
/* dont power down if plldown is false or we must poll hw radio disable */
if (!want && wlc_hw->pllreq)
return;
if (wlc_hw->sih)
- si_clkctl_xtal(wlc_hw->sih, XTAL | PLL, want);
+ ai_clkctl_xtal(wlc_hw->sih, XTAL | PLL, want);
wlc_hw->sbclk = want;
if (!wlc_hw->sbclk) {
@@ -3516,8 +3420,7 @@
if (wlc_hw->di[i]) {
dma_txreclaim(wlc_hw->di[i], HNDDMA_RANGE_ALL);
TXPKTPENDCLR(wlc, i);
- WL_TRACE("wlc_flushqueues: pktpend fifo %d cleared\n",
- i);
+ BCMMSG(wlc->wiphy, "pktpend fifo %d clrd\n", i);
}
/* free any posted rx packets */
@@ -3534,26 +3437,6 @@
wlc_bmac_write_objmem(wlc_hw, offset, v, OBJADDR_SHM_SEL);
}
-/* Set a range of shared memory to a value.
- * SHM 'offset' needs to be an even address and
- * Buffer length 'len' must be an even number of bytes
- */
-void wlc_bmac_set_shm(struct wlc_hw_info *wlc_hw, uint offset, u16 v, int len)
-{
- int i;
-
- /* offset and len need to be even */
- ASSERT((offset & 1) == 0);
- ASSERT((len & 1) == 0);
-
- if (len <= 0)
- return;
-
- for (i = 0; i < len; i += 2) {
- wlc_bmac_write_objmem(wlc_hw, offset + i, v, OBJADDR_SHM_SEL);
- }
-}
-
static u16
wlc_bmac_read_objmem(struct wlc_hw_info *wlc_hw, uint offset, u32 sel)
{
@@ -3562,8 +3445,6 @@
volatile u16 *objdata_hi = objdata_lo + 1;
u16 v;
- ASSERT((offset & 1) == 0);
-
W_REG(®s->objaddr, sel | (offset >> 2));
(void)R_REG(®s->objaddr);
if (offset & 2) {
@@ -3582,8 +3463,6 @@
volatile u16 *objdata_lo = (volatile u16 *)®s->objdata;
volatile u16 *objdata_hi = objdata_lo + 1;
- ASSERT((offset & 1) == 0);
-
W_REG(®s->objaddr, sel | (offset >> 2));
(void)R_REG(®s->objaddr);
if (offset & 2) {
@@ -3606,11 +3485,7 @@
const u8 *p = (const u8 *)buf;
int i;
- /* offset and len need to be even */
- ASSERT((offset & 1) == 0);
- ASSERT((len & 1) == 0);
-
- if (len <= 0)
+ if (len <= 0 || (offset & 1) || (len & 1))
return;
for (i = 0; i < len; i += 2) {
@@ -3632,11 +3507,7 @@
u8 *p = (u8 *) buf;
int i;
- /* offset and len need to be even */
- ASSERT((offset & 1) == 0);
- ASSERT((len & 1) == 0);
-
- if (len <= 0)
+ if (len <= 0 || (offset & 1) || (len & 1))
return;
for (i = 0; i < len; i += 2) {
@@ -3648,8 +3519,8 @@
void wlc_bmac_copyfrom_vars(struct wlc_hw_info *wlc_hw, char **buf, uint *len)
{
- WL_TRACE("wlc_bmac_copyfrom_vars, nvram vars totlen=%d\n",
- wlc_hw->vars_size);
+ BCMMSG(wlc_hw->wlc->wiphy, "nvram vars totlen=%d\n",
+ wlc_hw->vars_size);
*buf = wlc_hw->vars;
*len = wlc_hw->vars_size;
@@ -3673,15 +3544,8 @@
}
}
-void wlc_bmac_set_noreset(struct wlc_hw_info *wlc_hw, bool noreset_flag)
-{
- wlc_hw->noreset = noreset_flag;
-}
-
void wlc_bmac_pllreq(struct wlc_hw_info *wlc_hw, bool set, mbool req_bit)
{
- ASSERT(req_bit);
-
if (set) {
if (mboolisset(wlc_hw->pllreq, req_bit))
return;
@@ -3709,12 +3573,6 @@
return;
}
-/* this will be true for all ai chips */
-bool wlc_bmac_taclear(struct wlc_hw_info *wlc_hw, bool ta_ok)
-{
- return true;
-}
-
u16 wlc_bmac_rate_shm_offset(struct wlc_hw_info *wlc_hw, u8 rate)
{
u16 table_ptr;
@@ -3730,7 +3588,7 @@
/* for a given rate, the LS-nibble of the PLCP SIGNAL field is
* the index into the rate table.
*/
- phy_rate = rate_info[rate] & RATE_MASK;
+ phy_rate = rate_info[rate] & WLC_RATE_MASK;
index = phy_rate & 0xf;
/* Find the SHM pointer to the rate table entry by looking in the
diff --git a/drivers/staging/brcm80211/brcmsmac/wlc_bmac.h b/drivers/staging/brcm80211/brcmsmac/wlc_bmac.h
index 9c2c658..a5dccc2 100644
--- a/drivers/staging/brcm80211/brcmsmac/wlc_bmac.h
+++ b/drivers/staging/brcm80211/brcmsmac/wlc_bmac.h
@@ -130,8 +130,6 @@
wlc_bmac_state_t *state);
extern void wlc_bmac_write_shm(struct wlc_hw_info *wlc_hw, uint offset, u16 v);
extern u16 wlc_bmac_read_shm(struct wlc_hw_info *wlc_hw, uint offset);
-extern void wlc_bmac_set_shm(struct wlc_hw_info *wlc_hw, uint offset, u16 v,
- int len);
extern void wlc_bmac_write_template_ram(struct wlc_hw_info *wlc_hw, int offset,
int len, void *buf);
extern void wlc_bmac_copyfrom_vars(struct wlc_hw_info *wlc_hw, char **buf,
@@ -151,8 +149,6 @@
extern void wlc_ucode_wake_override_clear(struct wlc_hw_info *wlc_hw,
u32 override_bit);
-extern void wlc_bmac_set_rcmta(struct wlc_hw_info *wlc_hw, int idx,
- const u8 *addr);
extern void wlc_bmac_set_addrmatch(struct wlc_hw_info *wlc_hw,
int match_reg_offset,
const u8 *addr);
@@ -163,7 +159,6 @@
u32 *tsf_h_ptr);
extern void wlc_bmac_set_cwmin(struct wlc_hw_info *wlc_hw, u16 newmin);
extern void wlc_bmac_set_cwmax(struct wlc_hw_info *wlc_hw, u16 newmax);
-extern void wlc_bmac_set_noreset(struct wlc_hw_info *wlc, bool noreset_flag);
extern void wlc_bmac_retrylimit_upd(struct wlc_hw_info *wlc_hw, u16 SRL,
u16 LRL);
@@ -176,7 +171,6 @@
extern void wlc_bmac_bw_set(struct wlc_hw_info *wlc_hw, u16 bw);
extern void wlc_bmac_pllreq(struct wlc_hw_info *wlc_hw, bool set,
mbool req_bit);
-extern bool wlc_bmac_taclear(struct wlc_hw_info *wlc_hw, bool ta_ok);
extern void wlc_bmac_hw_up(struct wlc_hw_info *wlc_hw);
extern u16 wlc_bmac_rate_shm_offset(struct wlc_hw_info *wlc_hw, u8 rate);
extern void wlc_bmac_antsel_set(struct wlc_hw_info *wlc_hw, u32 antsel_avail);
diff --git a/drivers/staging/brcm80211/brcmsmac/wlc_bsscfg.h b/drivers/staging/brcm80211/brcmsmac/wlc_bsscfg.h
index bbcff4f..2572541 100644
--- a/drivers/staging/brcm80211/brcmsmac/wlc_bsscfg.h
+++ b/drivers/staging/brcm80211/brcmsmac/wlc_bsscfg.h
@@ -122,9 +122,6 @@
#define HWBCN_ENAB(cfg) (((cfg)->flags & WLC_BSSCFG_HW_BCN) != 0)
#define HWPRB_ENAB(cfg) (((cfg)->flags & WLC_BSSCFG_HW_PRB) != 0)
-extern void wlc_bsscfg_ID_assign(struct wlc_info *wlc,
- struct wlc_bsscfg *bsscfg);
-
/* Extend N_ENAB to per-BSS */
#define BSS_N_ENAB(wlc, cfg) \
(N_ENAB((wlc)->pub) && !((cfg)->flags & WLC_BSSCFG_11N_DISABLE))
diff --git a/drivers/staging/brcm80211/brcmsmac/wlc_channel.c b/drivers/staging/brcm80211/brcmsmac/wlc_channel.c
index 96161c0..a3a2bf9 100644
--- a/drivers/staging/brcm80211/brcmsmac/wlc_channel.c
+++ b/drivers/staging/brcm80211/brcmsmac/wlc_channel.c
@@ -21,7 +21,8 @@
#include <bcmdefs.h>
#include <bcmutils.h>
-#include <siutils.h>
+#include <bcmnvram.h>
+#include <aiutils.h>
#include <sbhnddma.h>
#include <wlioctl.h>
@@ -106,7 +107,8 @@
*txpwr,
u8
local_constraint_qdbm);
-void wlc_locale_add_channels(chanvec_t *target, const chanvec_t *channels);
+static void wlc_locale_add_channels(chanvec_t *target,
+ const chanvec_t *channels);
static const locale_mimo_info_t *wlc_get_mimo_2g(u8 locale_idx);
static const locale_mimo_info_t *wlc_get_mimo_5g(u8 locale_idx);
@@ -396,7 +398,8 @@
&locale_5g_HIGH4
};
-void wlc_locale_add_channels(chanvec_t *target, const chanvec_t *channels)
+static void wlc_locale_add_channels(chanvec_t *target,
+ const chanvec_t *channels)
{
u8 i;
for (i = 0; i < sizeof(chanvec_t); i++) {
@@ -594,10 +597,7 @@
static const locale_info_t *wlc_get_locale_2g(u8 locale_idx)
{
if (locale_idx >= ARRAY_SIZE(g_locale_2g_table)) {
- WL_ERROR("%s: locale 2g index size out of range %d\n",
- __func__, locale_idx);
- ASSERT(locale_idx < ARRAY_SIZE(g_locale_2g_table));
- return NULL;
+ return NULL; /* error condition */
}
return g_locale_2g_table[locale_idx];
}
@@ -605,29 +605,22 @@
static const locale_info_t *wlc_get_locale_5g(u8 locale_idx)
{
if (locale_idx >= ARRAY_SIZE(g_locale_5g_table)) {
- WL_ERROR("%s: locale 5g index size out of range %d\n",
- __func__, locale_idx);
- ASSERT(locale_idx < ARRAY_SIZE(g_locale_5g_table));
- return NULL;
+ return NULL; /* error condition */
}
return g_locale_5g_table[locale_idx];
}
-const locale_mimo_info_t *wlc_get_mimo_2g(u8 locale_idx)
+static const locale_mimo_info_t *wlc_get_mimo_2g(u8 locale_idx)
{
if (locale_idx >= ARRAY_SIZE(g_mimo_2g_table)) {
- WL_ERROR("%s: mimo 2g index size out of range %d\n",
- __func__, locale_idx);
return NULL;
}
return g_mimo_2g_table[locale_idx];
}
-const locale_mimo_info_t *wlc_get_mimo_5g(u8 locale_idx)
+static const locale_mimo_info_t *wlc_get_mimo_5g(u8 locale_idx)
{
if (locale_idx >= ARRAY_SIZE(g_mimo_5g_table)) {
- WL_ERROR("%s: mimo 5g index size out of range %d\n",
- __func__, locale_idx);
return NULL;
}
return g_mimo_5g_table[locale_idx];
@@ -641,11 +634,12 @@
struct wlc_pub *pub = wlc->pub;
char *ccode;
- WL_TRACE("wl%d: wlc_channel_mgr_attach\n", wlc->pub->unit);
+ BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
wlc_cm = kzalloc(sizeof(wlc_cm_info_t), GFP_ATOMIC);
if (wlc_cm == NULL) {
- WL_ERROR("wl%d: %s: out of memory", pub->unit, __func__);
+ wiphy_err(wlc->wiphy, "wl%d: %s: out of memory", pub->unit,
+ __func__);
return NULL;
}
wlc_cm->pub = pub;
@@ -656,9 +650,6 @@
ccode = getvar(wlc->pub->vars, "ccode");
if (ccode) {
strncpy(wlc->pub->srom_ccode, ccode, WLC_CNTRY_BUF_SZ - 1);
- WL_NONE("%s: SROM country code is %c%c\n",
- __func__,
- wlc->pub->srom_ccode[0], wlc->pub->srom_ccode[1]);
}
/* internal country information which must match regulatory constraints in firmware */
@@ -666,8 +657,6 @@
strncpy(country_abbrev, "X2", sizeof(country_abbrev) - 1);
country = wlc_country_lookup(wlc, country_abbrev);
- ASSERT(country != NULL);
-
/* save default country for exiting 11d regulatory mode */
strncpy(wlc->country_default, country_abbrev, WLC_CNTRY_BUF_SZ - 1);
@@ -708,10 +697,6 @@
char mapped_ccode[WLC_CNTRY_BUF_SZ];
uint mapped_regrev;
- WL_NONE("%s: (country_abbrev \"%s\", ccode \"%s\", regrev %d) SPROM \"%s\"/%u\n",
- __func__, country_abbrev, ccode, regrev,
- wlc_cm->srom_ccode, wlc_cm->srom_regrev);
-
/* if regrev is -1, lookup the mapped country code,
* otherwise use the ccode and regrev directly
*/
@@ -722,14 +707,13 @@
&mapped_regrev);
} else {
/* find the matching built-in country definition */
- ASSERT(0);
country = wlc_country_lookup_direct(ccode, regrev);
strncpy(mapped_ccode, ccode, WLC_CNTRY_BUF_SZ);
mapped_regrev = regrev;
}
if (country == NULL)
- return BCME_BADARG;
+ return -EINVAL;
/* set the driver state for the country */
wlc_set_country_common(wlc_cm, country_abbrev, mapped_ccode,
@@ -752,8 +736,6 @@
struct wlc_info *wlc = wlc_cm->wlc;
char prev_country_abbrev[WLC_CNTRY_BUF_SZ];
- ASSERT(country != NULL);
-
/* save current country state */
wlc_cm->country = country;
@@ -821,8 +803,8 @@
/* check for currently supported ccode size */
if (strlen(ccode) > (WLC_CNTRY_BUF_SZ - 1)) {
- WL_ERROR("wl%d: %s: ccode \"%s\" too long for match\n",
- wlc->pub->unit, __func__, ccode);
+ wiphy_err(wlc->wiphy, "wl%d: %s: ccode \"%s\" too long for "
+ "match\n", wlc->pub->unit, __func__, ccode);
return NULL;
}
@@ -837,8 +819,7 @@
if (!strcmp(srom_ccode, ccode)) {
*mapped_regrev = srom_regrev;
mapped = 0;
- WL_ERROR("srom_code == ccode %s\n", __func__);
- ASSERT(0);
+ wiphy_err(wlc->wiphy, "srom_code == ccode %s\n", __func__);
} else {
mapped =
wlc_country_aggregate_map(wlc_cm, ccode, mapped_ccode,
@@ -851,7 +832,6 @@
/* if there is not an exact rev match, default to rev zero */
if (country == NULL && *mapped_regrev != 0) {
*mapped_regrev = 0;
- ASSERT(0);
country =
wlc_country_lookup_direct(mapped_ccode, *mapped_regrev);
}
@@ -888,9 +868,6 @@
return &cntry_locales[i].country;
}
}
-
- WL_ERROR("%s: Returning NULL\n", __func__);
- ASSERT(0);
return NULL;
}
@@ -911,12 +888,10 @@
li = BAND_5G(band->bandtype) ?
wlc_get_locale_5g(country->locale_5G) :
wlc_get_locale_2g(country->locale_2G);
- ASSERT(li);
wlc_cm->bandstate[band->bandunit].locale_flags = li->flags;
li_mimo = BAND_5G(band->bandtype) ?
wlc_get_mimo_5g(country->locale_mimo_5G) :
wlc_get_mimo_2g(country->locale_mimo_2G);
- ASSERT(li_mimo);
/* merge the mimo non-mimo locale flags */
wlc_cm->bandstate[band->bandunit].locale_flags |=
@@ -968,9 +943,10 @@
if (chan == INVCHANNEL) {
/* country/locale with no valid channels, set the radio disable bit */
mboolset(wlc->pub->radio_disabled, WL_RADIO_COUNTRY_DISABLE);
- WL_ERROR("wl%d: %s: no valid channel for \"%s\" nbands %d bandlocked %d\n",
- wlc->pub->unit, __func__,
- wlc_cm->country_abbrev, NBANDS(wlc), wlc->bandlocked);
+ wiphy_err(wlc->wiphy, "wl%d: %s: no valid channel for \"%s\" "
+ "nbands %d bandlocked %d\n", wlc->pub->unit,
+ __func__, wlc_cm->country_abbrev, NBANDS(wlc),
+ wlc->bandlocked);
} else
if (mboolisset(wlc->pub->radio_disabled,
WL_RADIO_COUNTRY_DISABLE)) {
@@ -1520,10 +1496,9 @@
u8 channel = CHSPEC_CHANNEL(chspec);
/* check the chanspec */
- if (wf_chspec_malformed(chspec)) {
- WL_ERROR("wl%d: malformed chanspec 0x%x\n",
- wlc->pub->unit, chspec);
- ASSERT(0);
+ if (bcm_chspec_malformed(chspec)) {
+ wiphy_err(wlc->wiphy, "wl%d: malformed chanspec 0x%x\n",
+ wlc->pub->unit, chspec);
return false;
}
diff --git a/drivers/staging/brcm80211/brcmsmac/wlc_key.h b/drivers/staging/brcm80211/brcmsmac/wlc_key.h
index 50a4e38..cab10c7 100644
--- a/drivers/staging/brcm80211/brcmsmac/wlc_key.h
+++ b/drivers/staging/brcm80211/brcmsmac/wlc_key.h
@@ -115,7 +115,7 @@
#define WSEC_IBSS_PEER_GROUP_KEY (1 << 7) /* Flag: group key for a IBSS PEER */
#define WSEC_ICV_ERROR (1 << 8) /* Provoke deliberate ICV error */
-#define wlc_key_insert(a, b, c, d, e, f, g, h, i, j) (BCME_ERROR)
+#define wlc_key_insert(a, b, c, d, e, f, g, h, i, j) (-EBADE)
#define wlc_key_update(a, b, c) do {} while (0)
#define wlc_key_remove(a, b, c) do {} while (0)
#define wlc_key_remove_all(a, b) do {} while (0)
@@ -126,12 +126,12 @@
#define wlc_key_hw_init(a, b, c) do {} while (0)
#define wlc_key_hw_wowl_init(a, b, c, d) do {} while (0)
#define wlc_key_sw_wowl_update(a, b, c, d, e) do {} while (0)
-#define wlc_key_sw_wowl_create(a, b, c) (BCME_ERROR)
+#define wlc_key_sw_wowl_create(a, b, c) (-EBADE)
#define wlc_key_iv_update(a, b, c, d, e) do {(void)e; } while (0)
#define wlc_key_iv_init(a, b, c) do {} while (0)
-#define wlc_key_set_error(a, b, c) (BCME_ERROR)
-#define wlc_key_dump_hw(a, b) (BCME_ERROR)
-#define wlc_key_dump_sw(a, b) (BCME_ERROR)
+#define wlc_key_set_error(a, b, c) (-EBADE)
+#define wlc_key_dump_hw(a, b) (-EBADE)
+#define wlc_key_dump_sw(a, b) (-EBADE)
#define wlc_key_defkeyflag(a) (0)
#define wlc_rcmta_add_bssid(a, b) do {} while (0)
#define wlc_rcmta_del_bssid(a, b) do {} while (0)
diff --git a/drivers/staging/brcm80211/brcmsmac/wlc_main.c b/drivers/staging/brcm80211/brcmsmac/wlc_main.c
index ab7ab85..4b4a31e 100644
--- a/drivers/staging/brcm80211/brcmsmac/wlc_main.c
+++ b/drivers/staging/brcm80211/brcmsmac/wlc_main.c
@@ -16,20 +16,22 @@
#include <linux/kernel.h>
#include <linux/ctype.h>
#include <linux/etherdevice.h>
+#include <linux/pci_ids.h>
#include <net/mac80211.h>
#include <bcmdefs.h>
#include <bcmdevs.h>
#include <bcmutils.h>
#include <bcmwifi.h>
-#include <siutils.h>
+#include <bcmnvram.h>
+#include <aiutils.h>
#include <pcicfg.h>
#include <bcmsrom.h>
#include <wlioctl.h>
#include <sbhnddma.h>
#include <hnddma.h>
-#include <hndpmu.h>
+#include "wlc_pmu.h"
#include "d11.h"
#include "wlc_types.h"
#include "wlc_cfg.h"
@@ -51,12 +53,7 @@
#include "wlc_alloc.h"
#include "wl_dbg.h"
-/*
- * Disable statistics counting for WME
- */
-#define WLCNTSET(a, b)
-#define WLCNTINCR(a)
-#define WLCNTADD(a, b)
+#include "wl_mac80211.h"
/*
* WPA(2) definitions
@@ -242,7 +239,7 @@
#define WLC_REPLAY_CNTRS_VALUE WPA_CAP_16_REPLAY_CNTRS
/* local prototypes */
-static u16 BCMFASTPATH wlc_d11hdrs_mac80211(struct wlc_info *wlc,
+static u16 wlc_d11hdrs_mac80211(struct wlc_info *wlc,
struct ieee80211_hw *hw,
struct sk_buff *p,
struct scb *scb, uint frag,
@@ -250,8 +247,6 @@
uint next_frag_len,
wsec_key_t *key,
ratespec_t rspec_override);
-
-static void wlc_ctrupd_cache(u16 cur_stat, u16 *macstat_snapshot, u32 *macstat);
static void wlc_bss_default_init(struct wlc_info *wlc);
static void wlc_ucode_mac_upd(struct wlc_info *wlc);
static ratespec_t mac80211_wlc_set_nrate(struct wlc_info *wlc,
@@ -273,13 +268,13 @@
struct wlc_txq_info *qi,
bool on, int prio);
static void wlc_txflowcontrol_reset(struct wlc_info *wlc);
-static u16 wlc_compute_airtime(struct wlc_info *wlc, ratespec_t rspec,
- uint length);
-static void wlc_compute_cck_plcp(ratespec_t rate, uint length, u8 *plcp);
+static void wlc_compute_cck_plcp(struct wlc_info *wlc, ratespec_t rate,
+ uint length, u8 *plcp);
static void wlc_compute_ofdm_plcp(ratespec_t rate, uint length, u8 *plcp);
static void wlc_compute_mimo_plcp(ratespec_t rate, uint length, u8 *plcp);
static u16 wlc_compute_frame_dur(struct wlc_info *wlc, ratespec_t rate,
u8 preamble_type, uint next_frag_len);
+static u64 wlc_recover_tsf64(struct wlc_info *wlc, struct wlc_d11rxhdr *rxh);
static void wlc_recvctl(struct wlc_info *wlc,
d11rxhdr_t *rxh, struct sk_buff *p);
static uint wlc_calc_frame_len(struct wlc_info *wlc, ratespec_t rate,
@@ -320,35 +315,6 @@
static int _wlc_ioctl(struct wlc_info *wlc, int cmd, void *arg, int len,
struct wlc_if *wlcif);
-#if defined(BCMDBG)
-void wlc_get_rcmta(struct wlc_info *wlc, int idx, u8 *addr)
-{
- d11regs_t *regs = wlc->regs;
- u32 v32;
-
- WL_TRACE("wl%d: %s\n", WLCWLUNIT(wlc), __func__);
-
- W_REG(®s->objaddr, (OBJADDR_RCMTA_SEL | (idx * 2)));
- (void)R_REG(®s->objaddr);
- v32 = R_REG(®s->objdata);
- addr[0] = (u8) v32;
- addr[1] = (u8) (v32 >> 8);
- addr[2] = (u8) (v32 >> 16);
- addr[3] = (u8) (v32 >> 24);
- W_REG(®s->objaddr, (OBJADDR_RCMTA_SEL | ((idx * 2) + 1)));
- (void)R_REG(®s->objaddr);
- v32 = R_REG(®s->objdata);
- addr[4] = (u8) v32;
- addr[5] = (u8) (v32 >> 8);
-}
-#endif /* defined(BCMDBG) */
-
-/* keep the chip awake if needed */
-bool wlc_stay_awake(struct wlc_info *wlc)
-{
- return true;
-}
-
/* conditions under which the PM bit should be set in outgoing frames and STAY_AWAKE is meaningful
*/
bool wlc_ps_allowed(struct wlc_info *wlc)
@@ -380,7 +346,7 @@
void wlc_reset(struct wlc_info *wlc)
{
- WL_TRACE("wl%d: wlc_reset\n", wlc->pub->unit);
+ BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
wlc->check_for_unaligned_tbtt = false;
@@ -392,14 +358,14 @@
sizeof(macstat_t));
wlc_bmac_reset(wlc->hw);
- wlc_ampdu_reset(wlc->ampdu);
wlc->txretried = 0;
}
void wlc_fatal_error(struct wlc_info *wlc)
{
- WL_ERROR("wl%d: fatal error, reinitializing\n", wlc->pub->unit);
+ wiphy_err(wlc->wiphy, "wl%d: fatal error, reinitializing\n",
+ wlc->pub->unit);
wl_init(wlc->wl);
}
@@ -414,11 +380,6 @@
1 | WL_CHANSPEC_BW_20 | WL_CHANSPEC_CTL_SB_NONE |
WL_CHANSPEC_BAND_2G;
- /* make sure the channel is on the supported band if we are band-restricted */
- if (wlc->bandlocked || NBANDS(wlc) == 1) {
- ASSERT(CHSPEC_WLCBANDUNIT(chanspec) == wlc->band->bandunit);
- }
- ASSERT(wlc_valid_chanspec_db(wlc->cmi, chanspec));
return chanspec;
}
@@ -440,7 +401,7 @@
struct wlc_bsscfg *bsscfg;
bool mute = false;
- WL_TRACE("wl%d: wlc_init\n", wlc->pub->unit);
+ BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
regs = wlc->regs;
@@ -463,7 +424,6 @@
wlc_bcn_li_upd(wlc);
wlc->bcn_wait_prd =
(u8) (wlc_bmac_read_shm(wlc->hw, M_NOSLPZNATDTIM) >> 10);
- ASSERT(wlc->bcn_wait_prd > 0);
/* the world is new again, so is our reported rate */
wlc_reprate_init(wlc);
@@ -524,7 +484,7 @@
/* Enable EDCF mode (while the MAC is suspended) */
if (EDCF_ENAB(wlc->pub)) {
OR_REG(®s->ifs_ctl, IFS_USEEDCF);
- wlc_edcf_setparams(wlc->cfg, false);
+ wlc_edcf_setparams(wlc, false);
}
/* Init precedence maps for empty FIFOs */
@@ -559,7 +519,6 @@
if (WLC_WME_RETRY_SHORT_GET(wlc, 0) == 0) { /* Uninitialized; read from HW */
int ac;
- ASSERT(wlc->clk);
for (ac = 0; ac < AC_COUNT; ac++) {
wlc->wme_retries[ac] =
wlc_read_shm(wlc, M_AC_TXLMT_ADDR(ac));
@@ -604,82 +563,27 @@
wlc_mctrl(wlc, MCTL_PROMISC | MCTL_KEEPCONTROL, promisc_bits);
}
-/* check if hps and wake states of sw and hw are in sync */
-bool wlc_ps_check(struct wlc_info *wlc)
-{
- bool res = true;
- bool hps, wake;
- bool wake_ok;
-
- if (!AP_ACTIVE(wlc)) {
- u32 tmp;
- tmp = R_REG(&wlc->regs->maccontrol);
-
- /*
- * If deviceremoved is detected, then don't take any action as
- * this can be called in any context. Assume that caller will
- * take care of the condition. This is just to avoid assert
- */
- if (tmp == 0xffffffff) {
- WL_ERROR("wl%d: %s: dead chip\n",
- wlc->pub->unit, __func__);
- return DEVICEREMOVED(wlc);
- }
-
- hps = PS_ALLOWED(wlc);
-
- if (hps != ((tmp & MCTL_HPS) != 0)) {
- int idx;
- struct wlc_bsscfg *cfg;
- WL_ERROR("wl%d: hps not sync, sw %d, maccontrol 0x%x\n",
- wlc->pub->unit, hps, tmp);
- FOREACH_BSS(wlc, idx, cfg) {
- if (!BSSCFG_STA(cfg))
- continue;
- }
-
- res = false;
- }
- /* For a monolithic build the wake check can be exact since it looks at wake
- * override bits. The MCTL_WAKE bit should match the 'wake' value.
- */
- wake = STAY_AWAKE(wlc) || wlc->hw->wake_override;
- wake_ok = (wake == ((tmp & MCTL_WAKE) != 0));
- if (hps && !wake_ok) {
- WL_ERROR("wl%d: wake not sync, sw %d maccontrol 0x%x\n",
- wlc->pub->unit, wake, tmp);
- res = false;
- }
- }
- ASSERT(res);
- return res;
-}
-
/* push sw hps and wake state through hardware */
void wlc_set_ps_ctrl(struct wlc_info *wlc)
{
u32 v1, v2;
- bool hps, wake;
+ bool hps;
bool awake_before;
hps = PS_ALLOWED(wlc);
- wake = hps ? (STAY_AWAKE(wlc)) : true;
- WL_TRACE("wl%d: wlc_set_ps_ctrl: hps %d wake %d\n",
- wlc->pub->unit, hps, wake);
+ BCMMSG(wlc->wiphy, "wl%d: hps %d\n", wlc->pub->unit, hps);
v1 = R_REG(&wlc->regs->maccontrol);
- v2 = 0;
+ v2 = MCTL_WAKE;
if (hps)
v2 |= MCTL_HPS;
- if (wake)
- v2 |= MCTL_WAKE;
wlc_mctrl(wlc, MCTL_WAKE | MCTL_HPS, v2);
awake_before = ((v1 & MCTL_WAKE) || ((v1 & MCTL_HPS) == 0));
- if (wake && !awake_before)
+ if (!awake_before)
wlc_bmac_wait_for_wake(wlc->hw);
}
@@ -730,8 +634,6 @@
int idx;
struct wlc_bsscfg *cfg;
- ASSERT(wlc->band->gmode);
-
/* use the override if it is set */
if (wlc->shortslot_override != WLC_SHORTSLOT_AUTO)
shortslot = (wlc->shortslot_override == WLC_SHORTSLOT_ON);
@@ -762,8 +664,8 @@
local = WLC_TXPWR_MAX;
if (wlc->pub->associated &&
- (wf_chspec_ctlchan(wlc->chanspec) ==
- wf_chspec_ctlchan(wlc->home_chanspec))) {
+ (bcm_chspec_ctlchan(wlc->chanspec) ==
+ bcm_chspec_ctlchan(wlc->home_chanspec))) {
/* get the local power constraint if we are on the AP's
* channel [802.11h, 7.3.2.13]
@@ -826,9 +728,8 @@
chanspec_t old_chanspec = wlc->chanspec;
if (!wlc_valid_chanspec_db(wlc->cmi, chanspec)) {
- WL_ERROR("wl%d: %s: Bad channel %d\n",
- wlc->pub->unit, __func__, CHSPEC_CHANNEL(chanspec));
- ASSERT(wlc_valid_chanspec_db(wlc->cmi, chanspec));
+ wiphy_err(wlc->wiphy, "wl%d: %s: Bad channel %d\n",
+ wlc->pub->unit, __func__, CHSPEC_CHANNEL(chanspec));
return;
}
@@ -838,9 +739,10 @@
if (wlc->band->bandunit != bandunit || wlc->bandinit_pending) {
switchband = true;
if (wlc->bandlocked) {
- WL_ERROR("wl%d: %s: chspec %d band is locked!\n",
- wlc->pub->unit, __func__,
- CHSPEC_CHANNEL(chanspec));
+ wiphy_err(wlc->wiphy, "wl%d: %s: chspec %d "
+ "band is locked!\n",
+ wlc->pub->unit, __func__,
+ CHSPEC_CHANNEL(chanspec));
return;
}
/* BMAC_NOTE: should the setband call come after the wlc_bmac_chanspec() ?
@@ -852,8 +754,6 @@
}
}
- ASSERT(N_ENAB(wlc->pub) || !CHSPEC_IS40(chanspec));
-
/* sync up phy/radio chanspec */
wlc_set_phy_chanspec(wlc, chanspec);
@@ -887,7 +787,7 @@
if (len == sizeof(tx_power_legacy_t))
old_power = (tx_power_legacy_t *) pwr;
else if (len < sizeof(tx_power_t))
- return BCME_BUFTOOSHORT;
+ return -EOVERFLOW;
memset(&power, 0, sizeof(tx_power_t));
@@ -1098,10 +998,10 @@
uint i;
/* Use the lowest basic rate */
- lowest_basic_rspec = rs->rates[0] & RATE_MASK;
+ lowest_basic_rspec = rs->rates[0] & WLC_RATE_MASK;
for (i = 0; i < rs->count; i++) {
if (rs->rates[i] & WLC_RATE_FLAG) {
- lowest_basic_rspec = rs->rates[i] & RATE_MASK;
+ lowest_basic_rspec = rs->rates[i] & WLC_RATE_MASK;
break;
}
}
@@ -1141,7 +1041,7 @@
*/
void wlc_protection_upd(struct wlc_info *wlc, uint idx, int val)
{
- WL_TRACE("wlc_protection_upd: idx %d, val %d\n", idx, val);
+ BCMMSG(wlc->wiphy, "idx %d, val %d\n", idx, val);
switch (idx) {
case WLC_PROT_G_SPEC:
@@ -1179,7 +1079,6 @@
break;
default:
- ASSERT(0);
break;
}
@@ -1252,14 +1151,12 @@
uint parkband;
uint i, band_order[2];
- WL_TRACE("wl%d: wlc_bandinit_ordered\n", wlc->pub->unit);
+ BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
/*
* We might have been bandlocked during down and the chip power-cycled (hibernate).
* figure out the right band to park on
*/
if (wlc->bandlocked || NBANDS(wlc) == 1) {
- ASSERT(CHSPEC_WLCBANDUNIT(chanspec) == wlc->band->bandunit);
-
parkband = wlc->band->bandunit; /* updated in wlc_bandlock() */
band_order[0] = band_order[1] = parkband;
} else {
@@ -1281,7 +1178,7 @@
/* fill in hw_rate */
wlc_rateset_filter(&default_rateset, &wlc->band->hw_rateset,
- false, WLC_RATES_CCK_OFDM, RATE_MASK,
+ false, WLC_RATES_CCK_OFDM, WLC_RATE_MASK,
(bool) N_ENAB(wlc->pub));
/* init basic rate lookup */
@@ -1295,7 +1192,7 @@
/* band-specific init */
static void WLBANDINITFN(wlc_bsinit) (struct wlc_info *wlc)
{
- WL_TRACE("wl%d: wlc_bsinit: bandunit %d\n",
+ BCMMSG(wlc->wiphy, "wl%d: bandunit %d\n",
wlc->pub->unit, wlc->band->bandunit);
/* write ucode ACK/CTS rate table */
@@ -1315,10 +1212,6 @@
int idx;
struct wlc_bsscfg *cfg;
- ASSERT(NBANDS(wlc) > 1);
- ASSERT(!wlc->bandlocked);
- ASSERT(bandunit != wlc->band->bandunit || wlc->bandinit_pending);
-
wlc->band = wlc->bandstate[bandunit];
if (!wlc->pub->up)
@@ -1355,41 +1248,28 @@
cpu_to_le16(EDCF_AC_VO_TXOP_STA)}
}
};
-
- ASSERT(sizeof(*pe) == WME_PARAM_IE_LEN);
memcpy(pe, &stadef, sizeof(*pe));
}
-void wlc_wme_setparams(struct wlc_info *wlc, u16 aci, void *arg, bool suspend)
+void wlc_wme_setparams(struct wlc_info *wlc, u16 aci,
+ const struct ieee80211_tx_queue_params *params,
+ bool suspend)
{
int i;
shm_acparams_t acp_shm;
u16 *shm_entry;
- struct ieee80211_tx_queue_params *params = arg;
-
- ASSERT(wlc);
/* Only apply params if the core is out of reset and has clocks */
if (!wlc->clk) {
- WL_ERROR("wl%d: %s : no-clock\n", wlc->pub->unit, __func__);
+ wiphy_err(wlc->wiphy, "wl%d: %s : no-clock\n", wlc->pub->unit,
+ __func__);
return;
}
- /*
- * AP uses AC params from wme_param_ie_ap.
- * AP advertises AC params from wme_param_ie.
- * STA uses AC params from wme_param_ie.
- */
-
wlc->wme_admctl = 0;
do {
memset((char *)&acp_shm, 0, sizeof(shm_acparams_t));
- /* find out which ac this set of params applies to */
- ASSERT(aci < AC_COUNT);
- /* set the admission control policy for this AC */
- /* wlc->wme_admctl |= 1 << aci; *//* should be set ?? seems like off by default */
-
/* fill in shm ac params struct */
acp_shm.txop = le16_to_cpu(params->txop);
/* convert from units of 32us to us for ucode */
@@ -1403,8 +1283,8 @@
if (acp_shm.aifs < EDCF_AIFSN_MIN
|| acp_shm.aifs > EDCF_AIFSN_MAX) {
- WL_ERROR("wl%d: wlc_edcf_setparams: bad aifs %d\n",
- wlc->pub->unit, acp_shm.aifs);
+ wiphy_err(wlc->wiphy, "wl%d: wlc_edcf_setparams: bad "
+ "aifs %d\n", wlc->pub->unit, acp_shm.aifs);
continue;
}
@@ -1439,20 +1319,14 @@
}
-void wlc_edcf_setparams(struct wlc_bsscfg *cfg, bool suspend)
+void wlc_edcf_setparams(struct wlc_info *wlc, bool suspend)
{
- struct wlc_info *wlc = cfg->wlc;
- uint aci, i, j;
+ u16 aci;
+ int i_ac;
edcf_acparam_t *edcf_acp;
- shm_acparams_t acp_shm;
- u16 *shm_entry;
- ASSERT(cfg);
- ASSERT(wlc);
-
- /* Only apply params if the core is out of reset and has clocks */
- if (!wlc->clk)
- return;
+ struct ieee80211_tx_queue_params txq_pars;
+ struct ieee80211_tx_queue_params *params = &txq_pars;
/*
* AP uses AC params from wme_param_ie_ap.
@@ -1462,59 +1336,24 @@
edcf_acp = (edcf_acparam_t *) &wlc->wme_param_ie.acparam[0];
- wlc->wme_admctl = 0;
-
- for (i = 0; i < AC_COUNT; i++, edcf_acp++) {
- memset((char *)&acp_shm, 0, sizeof(shm_acparams_t));
+ for (i_ac = 0; i_ac < AC_COUNT; i_ac++, edcf_acp++) {
/* find out which ac this set of params applies to */
aci = (edcf_acp->ACI & EDCF_ACI_MASK) >> EDCF_ACI_SHIFT;
- ASSERT(aci < AC_COUNT);
/* set the admission control policy for this AC */
if (edcf_acp->ACI & EDCF_ACM_MASK) {
wlc->wme_admctl |= 1 << aci;
}
/* fill in shm ac params struct */
- acp_shm.txop = le16_to_cpu(edcf_acp->TXOP);
- /* convert from units of 32us to us for ucode */
- wlc->edcf_txop[aci] = acp_shm.txop =
- EDCF_TXOP2USEC(acp_shm.txop);
- acp_shm.aifs = (edcf_acp->ACI & EDCF_AIFSN_MASK);
-
- if (aci == AC_VI && acp_shm.txop == 0
- && acp_shm.aifs < EDCF_AIFSN_MAX)
- acp_shm.aifs++;
-
- if (acp_shm.aifs < EDCF_AIFSN_MIN
- || acp_shm.aifs > EDCF_AIFSN_MAX) {
- WL_ERROR("wl%d: wlc_edcf_setparams: bad aifs %d\n",
- wlc->pub->unit, acp_shm.aifs);
- continue;
- }
+ params->txop = edcf_acp->TXOP;
+ params->aifs = edcf_acp->ACI;
/* CWmin = 2^(ECWmin) - 1 */
- acp_shm.cwmin = EDCF_ECW2CW(edcf_acp->ECW & EDCF_ECWMIN_MASK);
+ params->cw_min = EDCF_ECW2CW(edcf_acp->ECW & EDCF_ECWMIN_MASK);
/* CWmax = 2^(ECWmax) - 1 */
- acp_shm.cwmax = EDCF_ECW2CW((edcf_acp->ECW & EDCF_ECWMAX_MASK)
+ params->cw_max = EDCF_ECW2CW((edcf_acp->ECW & EDCF_ECWMAX_MASK)
>> EDCF_ECWMAX_SHIFT);
- acp_shm.cwcur = acp_shm.cwmin;
- acp_shm.bslots =
- R_REG(&wlc->regs->tsf_random) & acp_shm.cwcur;
- acp_shm.reggap = acp_shm.bslots + acp_shm.aifs;
- /* Indicate the new params to the ucode */
- acp_shm.status = wlc_read_shm(wlc, (M_EDCF_QINFO +
- wme_shmemacindex(aci) *
- M_EDCF_QLEN +
- M_EDCF_STATUS_OFF));
- acp_shm.status |= WME_STATUS_NEWAC;
-
- /* Fill in shm acparam table */
- shm_entry = (u16 *) &acp_shm;
- for (j = 0; j < (int)sizeof(shm_acparams_t); j += 2)
- wlc_write_shm(wlc,
- M_EDCF_QINFO +
- wme_shmemacindex(aci) * M_EDCF_QLEN + j,
- *shm_entry++);
+ wlc_wme_setparams(wlc, aci, params, suspend);
}
if (suspend)
@@ -1535,14 +1374,16 @@
wlc->wdtimer = wl_init_timer(wlc->wl, wlc_watchdog_by_timer,
wlc, "watchdog");
if (!wlc->wdtimer) {
- WL_ERROR("wl%d: wl_init_timer for wdtimer failed\n", unit);
+ wiphy_err(wlc->wiphy, "wl%d: wl_init_timer for wdtimer "
+ "failed\n", unit);
goto fail;
}
wlc->radio_timer = wl_init_timer(wlc->wl, wlc_radio_timer,
wlc, "radio");
if (!wlc->radio_timer) {
- WL_ERROR("wl%d: wl_init_timer for radio_timer failed\n", unit);
+ wiphy_err(wlc->wiphy, "wl%d: wl_init_timer for radio_timer "
+ "failed\n", unit);
goto fail;
}
@@ -1689,20 +1530,23 @@
wlc->asi = wlc_antsel_attach(wlc);
if (wlc->asi == NULL) {
- WL_ERROR("wl%d: wlc_attach: wlc_antsel_attach failed\n", unit);
+ wiphy_err(wlc->wiphy, "wl%d: wlc_attach: wlc_antsel_attach "
+ "failed\n", unit);
err = 44;
goto fail;
}
wlc->ampdu = wlc_ampdu_attach(wlc);
if (wlc->ampdu == NULL) {
- WL_ERROR("wl%d: wlc_attach: wlc_ampdu_attach failed\n", unit);
+ wiphy_err(wlc->wiphy, "wl%d: wlc_attach: wlc_ampdu_attach "
+ "failed\n", unit);
err = 50;
goto fail;
}
if ((wlc_stf_attach(wlc) != 0)) {
- WL_ERROR("wl%d: wlc_attach: wlc_stf_attach failed\n", unit);
+ wiphy_err(wlc->wiphy, "wl%d: wlc_attach: wlc_stf_attach "
+ "failed\n", unit);
err = 68;
goto fail;
}
@@ -1720,56 +1564,21 @@
/*
* The common driver entry routine. Error codes should be unique
*/
-void *wlc_attach(void *wl, u16 vendor, u16 device, uint unit, bool piomode,
- void *regsva, uint bustype, void *btparam, uint *perr)
+void *wlc_attach(struct wl_info *wl, u16 vendor, u16 device, uint unit,
+ bool piomode, void *regsva, uint bustype, void *btparam,
+ uint *perr)
{
struct wlc_info *wlc;
uint err = 0;
uint j;
struct wlc_pub *pub;
- struct wlc_txq_info *qi;
uint n_disabled;
- WL_NONE("wl%d: %s: vendor 0x%x device 0x%x\n",
- unit, __func__, vendor, device);
-
- ASSERT(WSEC_MAX_RCMTA_KEYS <= WSEC_MAX_KEYS);
- ASSERT(WSEC_MAX_DEFAULT_KEYS == WLC_DEFAULT_KEYS);
-
- /* some code depends on packed structures */
- ASSERT(sizeof(struct ethhdr) == ETH_HLEN);
- ASSERT(sizeof(d11regs_t) == SI_CORE_SIZE);
- ASSERT(sizeof(ofdm_phy_hdr_t) == D11_PHY_HDR_LEN);
- ASSERT(sizeof(cck_phy_hdr_t) == D11_PHY_HDR_LEN);
- ASSERT(sizeof(d11txh_t) == D11_TXH_LEN);
- ASSERT(sizeof(d11rxhdr_t) == RXHDR_LEN);
- ASSERT(sizeof(struct ieee80211_hdr) == DOT11_A4_HDR_LEN);
- ASSERT(sizeof(struct ieee80211_rts) == DOT11_RTS_LEN);
- ASSERT(sizeof(tx_status_t) == TXSTATUS_LEN);
- ASSERT(sizeof(struct ieee80211_ht_cap) == HT_CAP_IE_LEN);
-#ifdef BRCM_FULLMAC
- ASSERT(offsetof(wl_scan_params_t, channel_list) ==
- WL_SCAN_PARAMS_FIXED_SIZE);
-#endif
- ASSERT(IS_ALIGNED(offsetof(wsec_key_t, data), sizeof(u32)));
- ASSERT(ISPOWEROF2(MA_WINDOW_SZ));
-
- ASSERT(sizeof(wlc_d11rxhdr_t) <= WL_HWRXOFF);
-
- /*
- * Number of replay counters value used in WPA IE must match # rxivs
- * supported in wsec_key_t struct. See 802.11i/D3.0 sect. 7.3.2.17
- * 'RSN Information Element' figure 8 for this mapping.
- */
- ASSERT((WPA_CAP_16_REPLAY_CNTRS == WLC_REPLAY_CNTRS_VALUE
- && 16 == WLC_NUMRXIVS)
- || (WPA_CAP_4_REPLAY_CNTRS == WLC_REPLAY_CNTRS_VALUE
- && 4 == WLC_NUMRXIVS));
-
/* allocate struct wlc_info state and its substructures */
wlc = (struct wlc_info *) wlc_attach_malloc(unit, &err, device);
if (wlc == NULL)
goto fail;
+ wlc->wiphy = wl->wiphy;
pub = wlc->pub;
#if defined(BCMDBG)
@@ -1892,7 +1701,7 @@
/* fill in hw_rateset (used early by WLC_SET_RATESET) */
wlc_rateset_filter(&wlc->band->defrateset,
&wlc->band->hw_rateset, false,
- WLC_RATES_CCK_OFDM, RATE_MASK,
+ WLC_RATES_CCK_OFDM, WLC_RATE_MASK,
(bool) N_ENAB(wlc->pub));
}
@@ -1905,7 +1714,8 @@
goto fail;
if (!wlc_timers_init(wlc, unit)) {
- WL_ERROR("wl%d: %s: wlc_init_timer failed\n", unit, __func__);
+ wiphy_err(wl->wiphy, "wl%d: %s: wlc_init_timer failed\n", unit,
+ __func__);
err = 32;
goto fail;
}
@@ -1913,8 +1723,8 @@
/* depend on rateset, gmode */
wlc->cmi = wlc_channel_mgr_attach(wlc);
if (!wlc->cmi) {
- WL_ERROR("wl%d: %s: wlc_channel_mgr_attach failed\n",
- unit, __func__);
+ wiphy_err(wl->wiphy, "wl%d: %s: wlc_channel_mgr_attach failed"
+ "\n", unit, __func__);
err = 33;
goto fail;
}
@@ -1927,26 +1737,19 @@
*/
/* allocate our initial queue */
- qi = wlc_txq_alloc(wlc);
- if (qi == NULL) {
- WL_ERROR("wl%d: %s: failed to malloc tx queue\n",
- unit, __func__);
+ wlc->pkt_queue = wlc_txq_alloc(wlc);
+ if (wlc->pkt_queue == NULL) {
+ wiphy_err(wl->wiphy, "wl%d: %s: failed to malloc tx queue\n",
+ unit, __func__);
err = 100;
goto fail;
}
- wlc->active_queue = qi;
wlc->bsscfg[0] = wlc->cfg;
wlc->cfg->_idx = 0;
wlc->cfg->wlc = wlc;
pub->txmaxpkts = MAXTXPKTS;
- pub->_cnt->version = WL_CNT_T_VERSION;
- pub->_cnt->length = sizeof(struct wl_cnt);
-
- WLCNTSET(pub->_wme_cnt->version, WL_WME_CNT_VERSION);
- WLCNTSET(pub->_wme_cnt->length, sizeof(wl_wme_cnt_t));
-
wlc_wme_initparams_sta(wlc, &wlc->wme_param_ie);
wlc->mimoft = FT_HT;
@@ -2014,7 +1817,8 @@
return (void *)wlc;
fail:
- WL_ERROR("wl%d: %s: failed with err %d\n", unit, __func__, err);
+ wiphy_err(wl->wiphy, "wl%d: %s: failed with err %d\n",
+ unit, __func__, err);
if (wlc)
wlc_detach(wlc);
@@ -2032,8 +1836,8 @@
/* default antenna gain for srom rev 1 is 2 dBm (8 qdbm) */
wlc->band->antgain = 8;
} else if (wlc->band->antgain == -1) {
- WL_ERROR("wl%d: %s: Invalid antennas available in srom, using 2dB\n",
- unit, __func__);
+ wiphy_err(wlc->wiphy, "wl%d: %s: Invalid antennas available in"
+ " srom, using 2dB\n", unit, __func__);
wlc->band->antgain = 8;
} else {
s8 gain, fract;
@@ -2072,8 +1876,8 @@
aa = (s8) getintvar(vars,
(BAND_5G(bandtype) ? "aa1" : "aa0"));
if ((aa < 1) || (aa > 15)) {
- WL_ERROR("wl%d: %s: Invalid antennas available in srom (0x%x), using 3\n",
- unit, __func__, aa);
+ wiphy_err(wlc->wiphy, "wl%d: %s: Invalid antennas available in"
+ " srom (0x%x), using 3\n", unit, __func__, aa);
aa = 3;
}
@@ -2134,15 +1938,12 @@
*/
uint wlc_detach(struct wlc_info *wlc)
{
- uint i;
uint callbacks = 0;
if (wlc == NULL)
return 0;
- WL_TRACE("wl%d: %s\n", wlc->pub->unit, __func__);
-
- ASSERT(!wlc->pub->up);
+ BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
callbacks += wlc_bmac_detach(wlc);
@@ -2182,13 +1983,6 @@
while (wlc->tx_queues != NULL)
wlc_txq_free(wlc, wlc->tx_queues);
- /*
- * consistency check: wlc_module_register/wlc_module_unregister calls
- * should match therefore nothing should be left here.
- */
- for (i = 0; i < WLC_MAXMODULES; i++)
- ASSERT(wlc->modulecb[i].name[0] == '\0');
-
wlc_detach_mfree(wlc);
return callbacks;
}
@@ -2300,8 +2094,6 @@
/* maintain LED behavior in down state */
static void wlc_down_led_upd(struct wlc_info *wlc)
{
- ASSERT(!wlc->pub->up);
-
/* maintain LEDs while in down state, turn on sbclk if not available yet */
/* turn on sbclk if necessary */
if (!AP_ENAB(wlc->pub)) {
@@ -2349,7 +2141,8 @@
struct wlc_info *wlc = (struct wlc_info *) arg;
if (DEVICEREMOVED(wlc)) {
- WL_ERROR("wl%d: %s: dead chip\n", wlc->pub->unit, __func__);
+ wiphy_err(wlc->wiphy, "wl%d: %s: dead chip\n", wlc->pub->unit,
+ __func__);
wl_down(wlc->wl);
return;
}
@@ -2358,8 +2151,6 @@
if (wlc->mpc_offcnt < WLC_MPC_MAX_DELAYCNT)
wlc->mpc_offcnt++;
- /* validate all the reasons driver could be down and running this radio_timer */
- ASSERT(wlc->pub->radio_disabled || wlc->down_override);
wlc_radio_hwdisable_upd(wlc);
wlc_radio_upd(wlc);
}
@@ -2381,56 +2172,11 @@
if (!wlc->radio_monitor)
return true;
- ASSERT((wlc->pub->wlfeatureflag & WL_SWFL_NOHWRADIO) !=
- WL_SWFL_NOHWRADIO);
-
wlc->radio_monitor = false;
wlc_pllreq(wlc, false, WLC_PLLREQ_RADIO_MON);
return wl_del_timer(wlc->wl, wlc->radio_timer);
}
-/* bring the driver down, but don't reset hardware */
-void wlc_out(struct wlc_info *wlc)
-{
- wlc_bmac_set_noreset(wlc->hw, true);
- wlc_radio_upd(wlc);
- wl_down(wlc->wl);
- wlc_bmac_set_noreset(wlc->hw, false);
-
- /* core clk is true in BMAC driver due to noreset, need to mirror it in HIGH */
- wlc->clk = true;
-
- /* This will make sure that when 'up' is done
- * after 'out' it'll restore hardware (especially gpios)
- */
- wlc->pub->hw_up = false;
-}
-
-#if defined(BCMDBG)
-/* Verify the sanity of wlc->tx_prec_map. This can be done only by making sure that
- * if there is no packet pending for the FIFO, then the corresponding prec bits should be set
- * in prec_map. Of course, ignore this rule when block_datafifo is set
- */
-static bool wlc_tx_prec_map_verify(struct wlc_info *wlc)
-{
- /* For non-WME, both fifos have overlapping prec_map. So it's an error only if both
- * fail the check.
- */
- if (!EDCF_ENAB(wlc->pub)) {
- if (!(WLC_TX_FIFO_CHECK(wlc, TX_DATA_FIFO) ||
- WLC_TX_FIFO_CHECK(wlc, TX_CTL_FIFO)))
- return false;
- else
- return true;
- }
-
- return WLC_TX_FIFO_CHECK(wlc, TX_AC_BK_FIFO)
- && WLC_TX_FIFO_CHECK(wlc, TX_AC_BE_FIFO)
- && WLC_TX_FIFO_CHECK(wlc, TX_AC_VI_FIFO)
- && WLC_TX_FIFO_CHECK(wlc, TX_AC_VO_FIFO);
-}
-#endif /* BCMDBG */
-
static void wlc_watchdog_by_timer(void *arg)
{
struct wlc_info *wlc = (struct wlc_info *) arg;
@@ -2450,13 +2196,14 @@
int i;
struct wlc_bsscfg *cfg;
- WL_TRACE("wl%d: wlc_watchdog\n", wlc->pub->unit);
+ BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
if (!wlc->pub->up)
return;
if (DEVICEREMOVED(wlc)) {
- WL_ERROR("wl%d: %s: dead chip\n", wlc->pub->unit, __func__);
+ wiphy_err(wlc->wiphy, "wl%d: %s: dead chip\n", wlc->pub->unit,
+ __func__);
wl_down(wlc->wl);
return;
}
@@ -2480,9 +2227,6 @@
/* radio sync: sw/hw/mpc --> radio_disable/radio_enable */
wlc_radio_hwdisable_upd(wlc);
wlc_radio_upd(wlc);
- /* if ismpc, driver should be in down state if up/down is allowed */
- if (wlc->mpc && wlc_ismpc(wlc))
- ASSERT(!wlc->pub->up);
/* if radio is disable, driver may be down, quit here */
if (wlc->pub->radio_disabled)
return;
@@ -2515,23 +2259,16 @@
wlc->tempsense_lasttime = wlc->pub->now;
wlc_tempsense_upd(wlc);
}
- /* BMAC_NOTE: for HIGH_ONLY driver, this seems being called after RPC bus failed */
- ASSERT(wlc_bmac_taclear(wlc->hw, true));
-
- /* Verify that tx_prec_map and fifos are in sync to avoid lock ups */
- ASSERT(wlc_tx_prec_map_verify(wlc));
-
- ASSERT(wlc_ps_check(wlc));
}
/* make interface operational */
int wlc_up(struct wlc_info *wlc)
{
- WL_TRACE("wl%d: %s:\n", wlc->pub->unit, __func__);
+ BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
/* HW is turned off so don't try to access it */
if (wlc->pub->hw_off || DEVICEREMOVED(wlc))
- return BCME_RADIOOFF;
+ return -ENOMEDIUM;
if (!wlc->pub->hw_up) {
wlc_bmac_hw_up(wlc->hw);
@@ -2556,11 +2293,11 @@
* if radio is disabled, abort up, lower power, start radio timer and return 0(for NDIS)
* don't call radio_update to avoid looping wlc_up.
*
- * wlc_bmac_up_prep() returns either 0 or BCME_RADIOOFF only
+ * wlc_bmac_up_prep() returns either 0 or -BCME_RADIOOFF only
*/
if (!wlc->pub->radio_disabled) {
int status = wlc_bmac_up_prep(wlc->hw);
- if (status == BCME_RADIOOFF) {
+ if (status == -ENOMEDIUM) {
if (!mboolisset
(wlc->pub->radio_disabled, WL_RADIO_HW_DISABLE)) {
int idx;
@@ -2572,12 +2309,13 @@
if (!BSSCFG_STA(bsscfg)
|| !bsscfg->enable || !bsscfg->BSS)
continue;
- WL_ERROR("wl%d.%d: wlc_up: rfdisable -> " "wlc_bsscfg_disable()\n",
- wlc->pub->unit, idx);
+ wiphy_err(wlc->wiphy, "wl%d.%d: wlc_up"
+ ": rfdisable -> "
+ "wlc_bsscfg_disable()\n",
+ wlc->pub->unit, idx);
}
}
- } else
- ASSERT(!status);
+ }
}
if (wlc->pub->radio_disabled) {
@@ -2621,7 +2359,6 @@
wlc_wme_retries_write(wlc);
/* start one second watchdog timer */
- ASSERT(!wlc->WDarmed);
wl_add_timer(wlc->wl, wlc->wdtimer, TIMER_INTERVAL_WATCHDOG, true);
wlc->WDarmed = true;
@@ -2673,12 +2410,12 @@
bool dev_gone = false;
struct wlc_txq_info *qi;
- WL_TRACE("wl%d: %s:\n", wlc->pub->unit, __func__);
+ BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
/* check if we are already in the going down path */
if (wlc->going_down) {
- WL_ERROR("wl%d: %s: Driver going down so return\n",
- wlc->pub->unit, __func__);
+ wiphy_err(wlc->wiphy, "wl%d: %s: Driver going down so return"
+ "\n", wlc->pub->unit, __func__);
return 0;
}
if (!wlc->pub->up)
@@ -2707,9 +2444,6 @@
/* cancel all other timers */
callbacks += wlc_down_del_timer(wlc);
- /* interrupt must have been blocked */
- ASSERT((wlc->macintmask == 0) || !wlc->pub->up);
-
wlc->pub->up = false;
wlc_phy_mute_upd(wlc->band->pi, false, PHY_MUTE_ALL);
@@ -2719,8 +2453,7 @@
/* flush tx queues */
for (qi = wlc->tx_queues; qi != NULL; qi = qi->next) {
- pktq_flush(&qi->q, true, NULL, 0);
- ASSERT(pktq_empty(&qi->q));
+ bcm_pktq_flush(&qi->q, true, NULL, NULL);
}
callbacks += wlc_bmac_down_finish(wlc->hw);
@@ -2728,13 +2461,6 @@
/* wlc_bmac_down_finish has done wlc_coredisable(). so clk is off */
wlc->clk = false;
-#ifdef BCMDBG
- /* Since all the packets should have been freed,
- * all callbacks should have been called
- */
- for (i = 1; i <= wlc->pub->tunables->maxpktcb; i++)
- ASSERT(wlc->pkt_callback[i].fn == NULL);
-#endif
wlc->going_down = false;
return callbacks;
}
@@ -2761,7 +2487,7 @@
* Gmode is not GMODE_LEGACY_B
*/
if (N_ENAB(wlc->pub) && gmode == GMODE_LEGACY_B)
- return BCME_UNSUPPORTED;
+ return -ENOTSUPP;
/* verify that we are dealing with 2G band and grab the band pointer */
if (wlc->band->bandtype == WLC_BAND_2G)
@@ -2770,12 +2496,12 @@
(wlc->bandstate[OTHERBANDUNIT(wlc)]->bandtype == WLC_BAND_2G))
band = wlc->bandstate[OTHERBANDUNIT(wlc)];
else
- return BCME_BADBAND;
+ return -EINVAL;
/* Legacy or bust when no OFDM is supported by regulatory */
if ((wlc_channel_locale_flags_in_band(wlc->cmi, band->bandunit) &
WLC_NO_OFDM) && (gmode != GMODE_LEGACY_B))
- return BCME_RANGE;
+ return -EINVAL;
/* update configuration value */
if (config == true)
@@ -2823,9 +2549,9 @@
default:
/* Error */
- WL_ERROR("wl%d: %s: invalid gmode %d\n",
- wlc->pub->unit, __func__, gmode);
- return BCME_UNSUPPORTED;
+ wiphy_err(wlc->wiphy, "wl%d: %s: invalid gmode %d\n",
+ wlc->pub->unit, __func__, gmode);
+ return -ENOTSUPP;
}
/*
@@ -2904,11 +2630,11 @@
case WL_11N_2x2:
case WL_11N_3x3:
if (!(WLC_PHY_11N_CAP(wlc->band)))
- err = BCME_BADBAND;
+ err = -EINVAL;
break;
default:
- err = BCME_RANGE;
+ err = -EINVAL;
break;
}
@@ -2921,7 +2647,6 @@
int err;
err = wlc_nmode_validate(wlc, nmode);
- ASSERT(err == 0);
if (err)
return err;
@@ -2950,7 +2675,6 @@
nmode = WL_11N_2x2;
case WL_11N_2x2:
case WL_11N_3x3:
- ASSERT(WLC_PHY_11N_CAP(wlc->band));
/* force GMODE_AUTO if NMODE is ON */
wlc_set_gmode(wlc, GMODE_AUTO, true);
if (nmode == WL_11N_3x3)
@@ -2967,7 +2691,6 @@
break;
default:
- ASSERT(0);
break;
}
@@ -2983,7 +2706,7 @@
/* check for bad count value */
if ((rs.count == 0) || (rs.count > WLC_NUMRATES))
- return BCME_BADRATESET;
+ return -EINVAL;
/* try the current band */
bandunit = wlc->band->bandunit;
@@ -3005,7 +2728,7 @@
goto good;
}
- return BCME_ERROR;
+ return -EBADE;
good:
/* apply new rateset */
@@ -3067,8 +2790,8 @@
wlc_bss_info_t *current_bss;
/* update bsscfg pointer */
- bsscfg = NULL; /* XXX: Hack bsscfg to be size one and use this globally */
- current_bss = NULL;
+ bsscfg = wlc->cfg;
+ current_bss = bsscfg->current_bss;
/* initialize the following to get rid of compiler warning */
nextscb = NULL;
@@ -3078,13 +2801,12 @@
/* If the device is turned off, then it's not "removed" */
if (!wlc->pub->hw_off && DEVICEREMOVED(wlc)) {
- WL_ERROR("wl%d: %s: dead chip\n", wlc->pub->unit, __func__);
+ wiphy_err(wlc->wiphy, "wl%d: %s: dead chip\n", wlc->pub->unit,
+ __func__);
wl_down(wlc->wl);
- return BCME_ERROR;
+ return -EBADE;
}
- ASSERT(!(wlc->pub->hw_off && wlc->pub->up));
-
/* default argument is generic integer */
pval = arg ? (int *)arg:NULL;
@@ -3096,11 +2818,6 @@
/* bool conversion to avoid duplication below */
bool_val = val != 0;
-
- if (cmd != WLC_SET_CHANNEL)
- WL_NONE("WLC_IOCTL: cmd %d val 0x%x (%d) len %d\n",
- cmd, (uint)val, val, len);
-
bcmerror = 0;
regs = wlc->regs;
@@ -3118,9 +2835,10 @@
default:
if ((arg == NULL) || (len <= 0)) {
- WL_ERROR("wl%d: %s: Command %d needs arguments\n",
- wlc->pub->unit, __func__, cmd);
- bcmerror = BCME_BADARG;
+ wiphy_err(wlc->wiphy, "wl%d: %s: Command %d needs "
+ "arguments\n",
+ wlc->pub->unit, __func__, cmd);
+ bcmerror = -EINVAL;
goto done;
}
}
@@ -3144,7 +2862,10 @@
case WLC_GET_CHANNEL:{
channel_info_t *ci = (channel_info_t *) arg;
- ASSERT(len > (int)sizeof(ci));
+ if (len <= (int)sizeof(ci)) {
+ bcmerror = EOVERFLOW;
+ goto done;
+ }
ci->hw_channel =
CHSPEC_CHANNEL(WLC_BAND_PI_RADIO_CHANSPEC);
@@ -3159,12 +2880,12 @@
chanspec_t chspec = CH20MHZ_CHSPEC(val);
if (val < 0 || val > MAXCHANNEL) {
- bcmerror = BCME_OUTOFRANGECHAN;
+ bcmerror = -EINVAL;
break;
}
if (!wlc_valid_chanspec_db(wlc->cmi, chspec)) {
- bcmerror = BCME_BADCHAN;
+ bcmerror = -EINVAL;
break;
}
@@ -3191,7 +2912,7 @@
#if defined(BCMDBG)
case WLC_GET_UCFLAGS:
if (!wlc->pub->up) {
- bcmerror = BCME_NOTUP;
+ bcmerror = -ENOLINK;
break;
}
@@ -3206,7 +2927,7 @@
break;
if (val >= MHFMAX) {
- bcmerror = BCME_RANGE;
+ bcmerror = -EINVAL;
break;
}
@@ -3215,7 +2936,7 @@
case WLC_SET_UCFLAGS:
if (!wlc->pub->up) {
- bcmerror = BCME_NOTUP;
+ bcmerror = -ENOLINK;
break;
}
@@ -3231,7 +2952,7 @@
i = (u16) val;
if (i >= MHFMAX) {
- bcmerror = BCME_RANGE;
+ bcmerror = -EINVAL;
break;
}
@@ -3253,7 +2974,7 @@
break;
if (val & 1) {
- bcmerror = BCME_BADADDR;
+ bcmerror = -EINVAL;
break;
}
@@ -3274,7 +2995,7 @@
break;
if (val & 1) {
- bcmerror = BCME_BADADDR;
+ bcmerror = -EINVAL;
break;
}
@@ -3288,7 +3009,7 @@
band = WLC_BAND_AUTO;
if (len < (int)(sizeof(rw_reg_t) - sizeof(uint))) {
- bcmerror = BCME_BUFTOOSHORT;
+ bcmerror = -EOVERFLOW;
break;
}
@@ -3301,7 +3022,7 @@
break;
if ((r->byteoff + r->size) > sizeof(d11regs_t)) {
- bcmerror = BCME_BADADDR;
+ bcmerror = -EINVAL;
break;
}
if (r->size == sizeof(u32))
@@ -3313,7 +3034,7 @@
R_REG((u16 *)((unsigned char *)(unsigned long)regs +
r->byteoff));
else
- bcmerror = BCME_BADADDR;
+ bcmerror = -EINVAL;
break;
case WLC_W_REG:
@@ -3322,7 +3043,7 @@
band = WLC_BAND_AUTO;
if (len < (int)(sizeof(rw_reg_t) - sizeof(uint))) {
- bcmerror = BCME_BUFTOOSHORT;
+ bcmerror = -EOVERFLOW;
break;
}
@@ -3335,7 +3056,7 @@
break;
if (r->byteoff + r->size > sizeof(d11regs_t)) {
- bcmerror = BCME_BADADDR;
+ bcmerror = -EINVAL;
break;
}
if (r->size == sizeof(u32))
@@ -3345,7 +3066,7 @@
W_REG((u16 *)((unsigned char *)(unsigned long) regs +
r->byteoff), r->val);
else
- bcmerror = BCME_BADADDR;
+ bcmerror = -EINVAL;
break;
#endif /* BCMDBG */
@@ -3393,7 +3114,7 @@
case WLC_SET_ANTDIV:
/* values are -1=driver default, 0=force0, 1=force1, 2=start1, 3=start0 */
if ((val < -1) || (val > 3)) {
- bcmerror = BCME_RANGE;
+ bcmerror = -EINVAL;
break;
}
@@ -3408,13 +3129,13 @@
u16 rxstatus;
if (!wlc->pub->up) {
- bcmerror = BCME_NOTUP;
+ bcmerror = -ENOLINK;
break;
}
rxstatus = R_REG(&wlc->regs->phyrxstatus0);
if (rxstatus == 0xdead || rxstatus == (u16) -1) {
- bcmerror = BCME_ERROR;
+ bcmerror = -EBADE;
break;
}
*pval = (rxstatus & PRXS0_RXANT_UPSUBBAND) ? 1 : 0;
@@ -3424,7 +3145,7 @@
#if defined(BCMDBG)
case WLC_GET_UCANTDIV:
if (!wlc->clk) {
- bcmerror = BCME_NOCLK;
+ bcmerror = -EIO;
break;
}
@@ -3435,13 +3156,13 @@
case WLC_SET_UCANTDIV:{
if (!wlc->pub->up) {
- bcmerror = BCME_NOTUP;
+ bcmerror = -ENOLINK;
break;
}
/* if multiband, band must be locked */
if (IS_MBAND_UNLOCKED(wlc)) {
- bcmerror = BCME_NOTBANDLOCKED;
+ bcmerror = -ENOMEDIUM;
break;
}
@@ -3467,7 +3188,7 @@
}
wlc_wme_retries_write(wlc);
} else
- bcmerror = BCME_RANGE;
+ bcmerror = -EINVAL;
break;
case WLC_GET_LRL:
@@ -3486,7 +3207,7 @@
}
wlc_wme_retries_write(wlc);
} else
- bcmerror = BCME_RANGE;
+ bcmerror = -EINVAL;
break;
case WLC_GET_CWMIN:
@@ -3495,14 +3216,14 @@
case WLC_SET_CWMIN:
if (!wlc->clk) {
- bcmerror = BCME_NOCLK;
+ bcmerror = -EIO;
break;
}
if (val >= 1 && val <= 255) {
wlc_set_cwmin(wlc, (u16) val);
} else
- bcmerror = BCME_RANGE;
+ bcmerror = -EINVAL;
break;
case WLC_GET_CWMAX:
@@ -3511,14 +3232,14 @@
case WLC_SET_CWMAX:
if (!wlc->clk) {
- bcmerror = BCME_NOCLK;
+ bcmerror = -EIO;
break;
}
if (val >= 255 && val <= 2047) {
wlc_set_cwmax(wlc, (u16) val);
} else
- bcmerror = BCME_RANGE;
+ bcmerror = -EINVAL;
break;
case WLC_GET_RADIO: /* use mask if don't want to expose some internal bits */
@@ -3539,9 +3260,9 @@
if ((radiomask == 0) || (radiomask & ~validbits)
|| (radioval & ~validbits)
|| ((radioval & ~radiomask) != 0)) {
- WL_ERROR("SET_RADIO with wrong bits 0x%x\n",
- val);
- bcmerror = BCME_RANGE;
+ wiphy_err(wlc->wiphy, "SET_RADIO with wrong "
+ "bits 0x%x\n", val);
+ bcmerror = -EINVAL;
break;
}
@@ -3566,7 +3287,7 @@
wsec_key_t *src_key = wlc->wsec_keys[val];
if (len < (int)sizeof(key)) {
- bcmerror = BCME_BUFTOOSHORT;
+ bcmerror = -EOVERFLOW;
break;
}
@@ -3586,7 +3307,7 @@
memcpy(arg, &key, sizeof(key));
} else
- bcmerror = BCME_BADKEYIDX;
+ bcmerror = -EINVAL;
break;
#endif /* defined(BCMDBG) */
@@ -3600,7 +3321,7 @@
wsec_key_t *key;
if (len < DOT11_WPA_KEY_RSC_LEN) {
- bcmerror = BCME_BUFTOOSHORT;
+ bcmerror = -EOVERFLOW;
break;
}
@@ -3637,7 +3358,7 @@
memcpy(arg, seq, sizeof(seq));
} else {
- bcmerror = BCME_BADKEYIDX;
+ bcmerror = -EINVAL;
}
break;
}
@@ -3646,13 +3367,13 @@
wl_rateset_t *ret_rs = (wl_rateset_t *) arg;
wlc_rateset_t *rs;
- if (bsscfg->associated)
+ if (wlc->pub->associated)
rs = ¤t_bss->rateset;
else
rs = &wlc->default_bss->rateset;
if (len < (int)(rs->count + sizeof(rs->count))) {
- bcmerror = BCME_BUFTOOSHORT;
+ bcmerror = -EOVERFLOW;
break;
}
@@ -3670,7 +3391,7 @@
wlc_default_rateset(wlc, (wlc_rateset_t *) &rs);
if (len < (int)(rs.count + sizeof(rs.count))) {
- bcmerror = BCME_BUFTOOSHORT;
+ bcmerror = -EOVERFLOW;
break;
}
@@ -3685,12 +3406,12 @@
wl_rateset_t *in_rs = (wl_rateset_t *) arg;
if (len < (int)(in_rs->count + sizeof(in_rs->count))) {
- bcmerror = BCME_BUFTOOSHORT;
+ bcmerror = -EOVERFLOW;
break;
}
if (in_rs->count > WLC_NUMRATES) {
- bcmerror = BCME_BUFTOOLONG;
+ bcmerror = -ENOBUFS;
break;
}
@@ -3733,7 +3454,7 @@
&& val <= DOT11_MAX_BEACON_PERIOD) {
wlc->default_bss->beacon_period = (u16) val;
} else
- bcmerror = BCME_RANGE;
+ bcmerror = -EINVAL;
break;
case WLC_GET_DTIMPRD:
@@ -3749,7 +3470,7 @@
&& val <= DOT11_MAX_DTIM_PERIOD) {
wlc->default_bss->dtim_period = (u8) val;
} else
- bcmerror = BCME_RANGE;
+ bcmerror = -EINVAL;
break;
#ifdef SUPPORT_PS
@@ -3765,7 +3486,7 @@
/* Change watchdog driver to align watchdog with tbtt if possible */
wlc_watchdog_upd(wlc, PS_ALLOWED(wlc));
} else
- bcmerror = BCME_ERROR;
+ bcmerror = -EBADE;
break;
#endif /* SUPPORT_PS */
@@ -3773,7 +3494,7 @@
#ifdef BCMDBG
case WLC_GET_WAKE:
if (AP_ENAB(wlc->pub)) {
- bcmerror = BCME_NOTSTA;
+ bcmerror = -BCME_NOTSTA;
break;
}
*pval = wlc->wake;
@@ -3781,7 +3502,7 @@
case WLC_SET_WAKE:
if (AP_ENAB(wlc->pub)) {
- bcmerror = BCME_NOTSTA;
+ bcmerror = -BCME_NOTSTA;
break;
}
@@ -3816,24 +3537,6 @@
wlc->default_bss->atim_window = (u32) val;
break;
- case WLC_GET_PKTCNTS:{
- get_pktcnt_t *pktcnt = (get_pktcnt_t *) pval;
- wlc_statsupd(wlc);
- pktcnt->rx_good_pkt = wlc->pub->_cnt->rxframe;
- pktcnt->rx_bad_pkt = wlc->pub->_cnt->rxerror;
- pktcnt->tx_good_pkt =
- wlc->pub->_cnt->txfrmsnt;
- pktcnt->tx_bad_pkt =
- wlc->pub->_cnt->txerror +
- wlc->pub->_cnt->txfail;
- if (len >= (int)sizeof(get_pktcnt_t)) {
- /* Be backward compatible - only if buffer is large enough */
- pktcnt->rx_ocast_good_pkt =
- wlc->pub->_cnt->rxmfrmocast;
- }
- break;
- }
-
#ifdef SUPPORT_HWKEY
case WLC_GET_WSEC:
bcmerror =
@@ -3876,7 +3579,7 @@
{
unsigned char *cp = arg;
if (len < 3) {
- bcmerror = BCME_BUFTOOSHORT;
+ bcmerror = -EOVERFLOW;
break;
}
@@ -3902,7 +3605,7 @@
case WLC_SET_SHORTSLOT_OVERRIDE:
if ((val != WLC_SHORTSLOT_AUTO) &&
(val != WLC_SHORTSLOT_OFF) && (val != WLC_SHORTSLOT_ON)) {
- bcmerror = BCME_RANGE;
+ bcmerror = -EINVAL;
break;
}
@@ -3959,7 +3662,7 @@
if (!wlc->pub->associated)
bcmerror = wlc_set_gmode(wlc, (u8) val, true);
else {
- bcmerror = BCME_ASSOCIATED;
+ bcmerror = -EISCONN;
break;
}
break;
@@ -3976,7 +3679,7 @@
if ((val != WLC_PROTECTION_CTL_OFF) &&
(val != WLC_PROTECTION_CTL_LOCAL) &&
(val != WLC_PROTECTION_CTL_OVERLAP)) {
- bcmerror = BCME_RANGE;
+ bcmerror = -EINVAL;
break;
}
@@ -3995,7 +3698,7 @@
case WLC_SET_GMODE_PROTECTION_OVERRIDE:
if ((val != WLC_PROTECTION_AUTO) &&
(val != WLC_PROTECTION_OFF) && (val != WLC_PROTECTION_ON)) {
- bcmerror = BCME_RANGE;
+ bcmerror = -EINVAL;
break;
}
@@ -4008,14 +3711,14 @@
/* copyin */
if (len < (int)sizeof(wlc_rateset_t)) {
- bcmerror = BCME_BUFTOOSHORT;
+ bcmerror = -EOVERFLOW;
break;
}
memcpy(&rs, arg, sizeof(wlc_rateset_t));
/* check for bad count value */
if (rs.count > WLC_NUMRATES) {
- bcmerror = BCME_BADRATESET; /* invalid rateset */
+ bcmerror = -EINVAL;
break;
}
@@ -4023,7 +3726,8 @@
if (!(wlc->band->gmode ||
((NBANDS(wlc) > 1)
&& wlc->bandstate[OTHERBANDUNIT(wlc)]->gmode))) {
- bcmerror = BCME_BADBAND; /* gmode only command when not in gmode */
+ /* gmode only command when not in gmode */
+ bcmerror = -EINVAL;
break;
}
@@ -4034,15 +3738,19 @@
break;
}
- /* validate rateset by comparing pre and post sorted against 11g hw rates */
- wlc_rateset_filter(&rs, &new, false, WLC_RATES_CCK_OFDM,
- RATE_MASK, BSS_N_ENAB(wlc, bsscfg));
+ /*
+ * validate rateset by comparing pre and
+ * post sorted against 11g hw rates
+ */
+ wlc_rateset_filter(&rs, &new, false,
+ WLC_RATES_CCK_OFDM, WLC_RATE_MASK,
+ BSS_N_ENAB(wlc, bsscfg));
wlc_rate_hwrs_filter_sort_validate(&new,
&cck_ofdm_rates,
false,
wlc->stf->txstreams);
if (rs.count != new.count) {
- bcmerror = BCME_BADRATESET; /* invalid rateset */
+ bcmerror = -EINVAL;
break;
}
@@ -4064,11 +3772,12 @@
if (!(wlc->band->gmode ||
((NBANDS(wlc) > 1)
&& wlc->bandstate[OTHERBANDUNIT(wlc)]->gmode))) {
- bcmerror = BCME_BADBAND; /* gmode only command when not in gmode */
+ /* gmode only command when not in gmode */
+ bcmerror = -EINVAL;
break;
}
if (len < (int)sizeof(wlc_rateset_t)) {
- bcmerror = BCME_BUFTOOSHORT;
+ bcmerror = -EOVERFLOW;
break;
}
memcpy(arg, &wlc->sup_rates_override, sizeof(wlc_rateset_t));
@@ -4081,11 +3790,11 @@
case WLC_SET_PRB_RESP_TIMEOUT:
if (wlc->pub->up) {
- bcmerror = BCME_NOTDOWN;
+ bcmerror = -EISCONN;
break;
}
if (val < 0 || val >= 0xFFFF) {
- bcmerror = BCME_RANGE; /* bad value */
+ bcmerror = -EINVAL; /* bad value */
break;
}
wlc->prb_resp_timeout = (u16) val;
@@ -4099,7 +3808,7 @@
if (key != NULL) {
*pval = key->id == val ? true : false;
} else {
- bcmerror = BCME_BADKEYIDX;
+ bcmerror = -EINVAL;
}
break;
}
@@ -4107,7 +3816,7 @@
case WLC_SET_KEY_PRIMARY:{
wsec_key_t *key, *old_key;
- bcmerror = BCME_BADKEYIDX;
+ bcmerror = -EINVAL;
/* treat the 'val' parm as the key id */
for (i = 0; i < WSEC_MAX_DEFAULT_KEYS; i++) {
@@ -4119,7 +3828,7 @@
~WSEC_PRIMARY_KEY;
key->flags |= WSEC_PRIMARY_KEY;
bsscfg->wsec_index = i;
- bcmerror = BCME_OK;
+ bcmerror = 0;
}
}
break;
@@ -4141,7 +3850,7 @@
;
if (i == (uint) len) {
- bcmerror = BCME_BUFTOOSHORT;
+ bcmerror = -EOVERFLOW;
break;
}
i++; /* include the null in the string length */
@@ -4162,37 +3871,25 @@
}
case WLC_SET_WSEC_PMK:
- bcmerror = BCME_UNSUPPORTED;
+ bcmerror = -ENOTSUPP;
break;
#if defined(BCMDBG)
case WLC_CURRENT_PWR:
if (!wlc->pub->up)
- bcmerror = BCME_NOTUP;
+ bcmerror = -ENOLINK;
else
bcmerror = wlc_get_current_txpwr(wlc, arg, len);
break;
#endif
case WLC_LAST:
- WL_ERROR("%s: WLC_LAST\n", __func__);
+ wiphy_err(wlc->wiphy, "%s: WLC_LAST\n", __func__);
}
done:
- if (bcmerror) {
- if (VALID_BCMERROR(bcmerror))
- wlc->pub->bcmerror = bcmerror;
- else {
- bcmerror = 0;
- }
-
- }
- /* BMAC_NOTE: for HIGH_ONLY driver, this seems being called after RPC bus failed */
- /* In hw_off condition, IOCTLs that reach here are deemed safe but taclear would
- * certainly result in getting -1 for register reads. So skip ta_clear altogether
- */
- if (!(wlc->pub->hw_off))
- ASSERT(wlc_bmac_taclear(wlc->hw, ta_ok) || !ta_ok);
+ if (bcmerror)
+ wlc->pub->bcmerror = bcmerror;
return bcmerror;
}
@@ -4203,30 +3900,20 @@
{
/* if band is specified, it must be the current band */
if ((band != WLC_BAND_AUTO) && (band != (uint) wlc->band->bandtype))
- return BCME_BADBAND;
+ return -EINVAL;
/* if multiband and band is not specified, band must be locked */
if ((band == WLC_BAND_AUTO) && IS_MBAND_UNLOCKED(wlc))
- return BCME_NOTBANDLOCKED;
+ return -ENOMEDIUM;
/* must have core clocks */
if (!wlc->clk)
- return BCME_NOCLK;
+ return -EIO;
return 0;
}
#endif /* defined(BCMDBG) */
-#if defined(BCMDBG)
-/* For some ioctls, make sure that the pi pointer matches the current phy */
-int wlc_iocpichk(struct wlc_info *wlc, uint phytype)
-{
- if (wlc->band->phytype != phytype)
- return BCME_BADBAND;
- return 0;
-}
-#endif
-
/* Look up the given var name in the given table */
static const bcm_iovar_t *wlc_iovar_lookup(const bcm_iovar_t *table,
const char *name)
@@ -4241,8 +3928,6 @@
else
lookup_name = name;
- ASSERT(table != NULL);
-
for (vi = table; vi->name; vi++) {
if (!strcmp(vi->name, lookup_name))
return vi;
@@ -4266,21 +3951,6 @@
IOV_SET, NULL);
}
-/* simplified s8 get interface for common WLC_GET_VAR ioctl handler */
-int wlc_iovar_gets8(struct wlc_info *wlc, const char *name, s8 *arg)
-{
- int iovar_int;
- int err;
-
- err =
- wlc_iovar_op(wlc, name, NULL, 0, &iovar_int, sizeof(iovar_int),
- IOV_GET, NULL);
- if (!err)
- *arg = (s8) iovar_int;
-
- return err;
-}
-
/*
* register iovar table, watchdog and down handlers.
* calling function must keep 'iovars' until wlc_module_unregister is called.
@@ -4293,9 +3963,6 @@
struct wlc_info *wlc = (struct wlc_info *) pub->wlc;
int i;
- ASSERT(name != NULL);
- ASSERT(i_fn != NULL || w_fn != NULL || d_fn != NULL);
-
/* find an empty entry and just add, no duplication check! */
for (i = 0; i < WLC_MAXMODULES; i++) {
if (wlc->modulecb[i].name[0] == '\0') {
@@ -4310,9 +3977,7 @@
}
}
- /* it is time to increase the capacity */
- ASSERT(i < WLC_MAXMODULES);
- return BCME_NORESOURCE;
+ return -ENOSR;
}
/* unregister module callbacks */
@@ -4322,9 +3987,7 @@
int i;
if (wlc == NULL)
- return BCME_NOTFOUND;
-
- ASSERT(name != NULL);
+ return -ENODATA;
for (i = 0; i < WLC_MAXMODULES; i++) {
if (!strcmp(wlc->modulecb[i].name, name) &&
@@ -4335,7 +3998,7 @@
}
/* table not found! */
- return BCME_NOTFOUND;
+ return -ENODATA;
}
/* Write WME tunable parameters for retransmit/max rate from wlc struct to ucode */
@@ -4371,23 +4034,11 @@
u32 actionid;
int i;
- ASSERT(name != NULL);
-
- ASSERT(len >= 0);
-
- /* Get MUST have return space */
- ASSERT(set || (arg && len));
-
- ASSERT(!(wlc->pub->hw_off && wlc->pub->up));
-
- /* Set does NOT take qualifiers */
- ASSERT(!set || (!params && !p_len));
-
if (!set && (len == sizeof(int)) &&
!(IS_ALIGNED((unsigned long)(arg), (uint) sizeof(int)))) {
- WL_ERROR("wl%d: %s unaligned get ptr for %s\n",
- wlc->pub->unit, __func__, name);
- ASSERT(0);
+ wiphy_err(wlc->wiphy, "wl%d: %s unaligned get ptr for %s\n",
+ wlc->pub->unit, __func__, name);
+ return -ENOTSUPP;
}
/* find the given iovar name */
@@ -4400,8 +4051,7 @@
}
/* iovar name not found */
if (i >= WLC_MAXMODULES) {
- err = BCME_UNSUPPORTED;
- goto exit;
+ return -ENOTSUPP;
}
/* set up 'params' pointer in case this is a set command so that
@@ -4426,8 +4076,6 @@
err = wlc->modulecb[i].iovar_fn(wlc->modulecb[i].hdl, vi, actionid,
name, params, p_len, arg, len, val_size,
wlcif);
-
- exit:
return err;
}
@@ -4443,22 +4091,22 @@
if (set) {
if (((vi->flags & IOVF_SET_DOWN) && wlc->pub->up) ||
((vi->flags & IOVF_SET_UP) && !wlc->pub->up)) {
- err = (wlc->pub->up ? BCME_NOTDOWN : BCME_NOTUP);
+ err = (wlc->pub->up ? -EISCONN : -ENOLINK);
} else if ((vi->flags & IOVF_SET_BAND)
&& IS_MBAND_UNLOCKED(wlc)) {
- err = BCME_NOTBANDLOCKED;
+ err = -ENOMEDIUM;
} else if ((vi->flags & IOVF_SET_CLK) && !wlc->clk) {
- err = BCME_NOCLK;
+ err = -EIO;
}
} else {
if (((vi->flags & IOVF_GET_DOWN) && wlc->pub->up) ||
((vi->flags & IOVF_GET_UP) && !wlc->pub->up)) {
- err = (wlc->pub->up ? BCME_NOTDOWN : BCME_NOTUP);
+ err = (wlc->pub->up ? -EISCONN : -ENOLINK);
} else if ((vi->flags & IOVF_GET_BAND)
&& IS_MBAND_UNLOCKED(wlc)) {
- err = BCME_NOTBANDLOCKED;
+ err = -ENOMEDIUM;
} else if ((vi->flags & IOVF_GET_CLK) && !wlc->clk) {
- err = BCME_NOCLK;
+ err = -EIO;
}
}
@@ -4513,7 +4161,7 @@
bool bool_val2;
wlc_bss_info_t *current_bss;
- WL_TRACE("wl%d: %s\n", wlc->pub->unit, __func__);
+ BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
bsscfg = NULL;
current_bss = NULL;
@@ -4537,8 +4185,7 @@
bool_val = (int_val != 0) ? true : false;
bool_val2 = (int_val2 != 0) ? true : false;
- WL_TRACE("wl%d: %s: id %d\n",
- wlc->pub->unit, __func__, IOV_ID(actionid));
+ BCMMSG(wlc->wiphy, "wl%d: id %d\n", wlc->pub->unit, IOV_ID(actionid));
/* Do the actual parameter implementation */
switch (actionid) {
case IOV_SVAL(IOV_RTSTHRESH):
@@ -4551,7 +4198,7 @@
err = wlc_phy_txpower_get(wlc->band->pi, &qdbm,
&override);
- if (err != BCME_OK)
+ if (err != 0)
return err;
/* Return qdbm units */
@@ -4599,8 +4246,9 @@
break;
default:
- WL_ERROR("wl%d: %s: unsupported\n", wlc->pub->unit, __func__);
- err = BCME_UNSUPPORTED;
+ wiphy_err(wlc->wiphy, "wl%d: %s: unsupported\n",
+ wlc->pub->unit, __func__);
+ err = -ENOTSUPP;
break;
}
@@ -4635,7 +4283,7 @@
/* Signed values are checked against max_val and min_val */
if ((s32) val < (s32) min_val
|| (s32) val > (s32) max_val)
- err = BCME_RANGE;
+ err = -EINVAL;
break;
case IOVT_UINT32:
@@ -4649,7 +4297,7 @@
if (vi->flags & IOVF_NTRL)
min_val = 1;
if ((val < min_val) || (val > max_val))
- err = BCME_RANGE;
+ err = -EINVAL;
break;
}
@@ -4708,24 +4356,6 @@
#endif /* defined(BCMDBG) */
}
-static void
-wlc_ctrupd_cache(u16 cur_stat, u16 *macstat_snapshot, u32 *macstat)
-{
- u16 v;
- u16 delta;
-
- v = le16_to_cpu(cur_stat);
- delta = (u16)(v - *macstat_snapshot);
-
- if (delta != 0) {
- *macstat += delta;
- *macstat_snapshot = v;
- }
-}
-
-#define MACSTATUPD(name) \
- wlc_ctrupd_cache(macstats.name, &wlc->core->macstat_snapshot->name, &wlc->pub->_cnt->name)
-
void wlc_statsupd(struct wlc_info *wlc)
{
int i;
@@ -4753,68 +4383,12 @@
wlc_bmac_copyfrom_shm(wlc->hw, M_UCODE_MACSTAT,
&macstats, sizeof(macstat_t));
- /* update mac stats */
- MACSTATUPD(txallfrm);
- MACSTATUPD(txrtsfrm);
- MACSTATUPD(txctsfrm);
- MACSTATUPD(txackfrm);
- MACSTATUPD(txdnlfrm);
- MACSTATUPD(txbcnfrm);
- for (i = 0; i < NFIFO; i++)
- MACSTATUPD(txfunfl[i]);
- MACSTATUPD(txtplunfl);
- MACSTATUPD(txphyerr);
- MACSTATUPD(rxfrmtoolong);
- MACSTATUPD(rxfrmtooshrt);
- MACSTATUPD(rxinvmachdr);
- MACSTATUPD(rxbadfcs);
- MACSTATUPD(rxbadplcp);
- MACSTATUPD(rxcrsglitch);
- MACSTATUPD(rxstrt);
- MACSTATUPD(rxdfrmucastmbss);
- MACSTATUPD(rxmfrmucastmbss);
- MACSTATUPD(rxcfrmucast);
- MACSTATUPD(rxrtsucast);
- MACSTATUPD(rxctsucast);
- MACSTATUPD(rxackucast);
- MACSTATUPD(rxdfrmocast);
- MACSTATUPD(rxmfrmocast);
- MACSTATUPD(rxcfrmocast);
- MACSTATUPD(rxrtsocast);
- MACSTATUPD(rxctsocast);
- MACSTATUPD(rxdfrmmcast);
- MACSTATUPD(rxmfrmmcast);
- MACSTATUPD(rxcfrmmcast);
- MACSTATUPD(rxbeaconmbss);
- MACSTATUPD(rxdfrmucastobss);
- MACSTATUPD(rxbeaconobss);
- MACSTATUPD(rxrsptmout);
- MACSTATUPD(bcntxcancl);
- MACSTATUPD(rxf0ovfl);
- MACSTATUPD(rxf1ovfl);
- MACSTATUPD(rxf2ovfl);
- MACSTATUPD(txsfovfl);
- MACSTATUPD(pmqovfl);
- MACSTATUPD(rxcgprqfrm);
- MACSTATUPD(rxcgprsqovfl);
- MACSTATUPD(txcgprsfail);
- MACSTATUPD(txcgprssuc);
- MACSTATUPD(prs_timeout);
- MACSTATUPD(rxnack);
- MACSTATUPD(frmscons);
- MACSTATUPD(txnack);
- MACSTATUPD(txglitch_nack);
- MACSTATUPD(txburst);
- MACSTATUPD(phywatchdog);
- MACSTATUPD(pktengrxducast);
- MACSTATUPD(pktengrxdmcast);
-
#ifdef BCMDBG
/* check for rx fifo 0 overflow */
delta = (u16) (wlc->core->macstat_snapshot->rxf0ovfl - rxf0ovfl);
if (delta)
- WL_ERROR("wl%d: %u rx fifo 0 overflows!\n",
- wlc->pub->unit, delta);
+ wiphy_err(wlc->wiphy, "wl%d: %u rx fifo 0 overflows!\n",
+ wlc->pub->unit, delta);
/* check for tx fifo underflows */
for (i = 0; i < NFIFO; i++) {
@@ -4822,57 +4396,23 @@
(u16) (wlc->core->macstat_snapshot->txfunfl[i] -
txfunfl[i]);
if (delta)
- WL_ERROR("wl%d: %u tx fifo %d underflows!\n",
- wlc->pub->unit, delta, i);
+ wiphy_err(wlc->wiphy, "wl%d: %u tx fifo %d underflows!"
+ "\n", wlc->pub->unit, delta, i);
}
#endif /* BCMDBG */
- /* dot11 counter update */
-
- WLCNTSET(wlc->pub->_cnt->txrts,
- (wlc->pub->_cnt->rxctsucast -
- wlc->pub->_cnt->d11cnt_txrts_off));
- WLCNTSET(wlc->pub->_cnt->rxcrc,
- (wlc->pub->_cnt->rxbadfcs - wlc->pub->_cnt->d11cnt_rxcrc_off));
- WLCNTSET(wlc->pub->_cnt->txnocts,
- ((wlc->pub->_cnt->txrtsfrm - wlc->pub->_cnt->rxctsucast) -
- wlc->pub->_cnt->d11cnt_txnocts_off));
-
/* merge counters from dma module */
for (i = 0; i < NFIFO; i++) {
if (wlc->hw->di[i]) {
- WLCNTADD(wlc->pub->_cnt->txnobuf,
- (wlc->hw->di[i])->txnobuf);
- WLCNTADD(wlc->pub->_cnt->rxnobuf,
- (wlc->hw->di[i])->rxnobuf);
- WLCNTADD(wlc->pub->_cnt->rxgiant,
- (wlc->hw->di[i])->rxgiants);
dma_counterreset(wlc->hw->di[i]);
}
}
-
- /*
- * Aggregate transmit and receive errors that probably resulted
- * in the loss of a frame are computed on the fly.
- */
- WLCNTSET(wlc->pub->_cnt->txerror,
- wlc->pub->_cnt->txnobuf + wlc->pub->_cnt->txnoassoc +
- wlc->pub->_cnt->txuflo + wlc->pub->_cnt->txrunt +
- wlc->pub->_cnt->dmade + wlc->pub->_cnt->dmada +
- wlc->pub->_cnt->dmape);
- WLCNTSET(wlc->pub->_cnt->rxerror,
- wlc->pub->_cnt->rxoflo + wlc->pub->_cnt->rxnobuf +
- wlc->pub->_cnt->rxfragerr + wlc->pub->_cnt->rxrunt +
- wlc->pub->_cnt->rxgiant + wlc->pub->_cnt->rxnoscb +
- wlc->pub->_cnt->rxbadsrcmac);
- for (i = 0; i < NFIFO; i++)
- wlc->pub->_cnt->rxerror += wlc->pub->_cnt->rxuflo[i];
}
bool wlc_chipmatch(u16 vendor, u16 device)
{
- if (vendor != VENDOR_BROADCOM) {
- WL_ERROR("wlc_chipmatch: unknown vendor id %04x\n", vendor);
+ if (vendor != PCI_VENDOR_ID_BROADCOM) {
+ pr_err("wlc_chipmatch: unknown vendor id %04x\n", vendor);
return false;
}
@@ -4884,7 +4424,7 @@
if ((device == BCM43236_D11N_ID) || (device == BCM43236_D11N2G_ID))
return true;
- WL_ERROR("wlc_chipmatch: unknown device id %04x\n", device);
+ pr_err("wlc_chipmatch: unknown device id %04x\n", device);
return false;
}
@@ -4923,7 +4463,9 @@
char hexbuf[256];
/* add plcp header along with txh descriptor */
- prhex("Raw TxDesc + plcp header", (unsigned char *) txh, sizeof(d11txh_t) + 48);
+ printk(KERN_DEBUG "Raw TxDesc + plcp header:\n");
+ print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
+ txh, sizeof(d11txh_t) + 48);
printk(KERN_DEBUG "TxCtlLow: %04x ", mtcl);
printk(KERN_DEBUG "TxCtlHigh: %04x ", mtch);
@@ -4994,7 +4536,8 @@
{0, NULL}
};
- prhex("Raw RxDesc", (unsigned char *) rxh, sizeof(d11rxhdr_t));
+ printk(KERN_DEBUG "Raw RxDesc:\n");
+ print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, rxh, sizeof(d11rxhdr_t));
bcm_format_flags(macstat_flags, macstatus1, flagstr, 64);
@@ -5033,8 +4576,6 @@
}
}
*p = '\0';
- ASSERT(p < endp);
-
return (int)(p - buf);
}
#endif /* defined(BCMDBG) */
@@ -5055,13 +4596,13 @@
*
* Returns true if packet consumed (queued), false if not.
*/
-bool BCMFASTPATH
+bool
wlc_prec_enq(struct wlc_info *wlc, struct pktq *q, void *pkt, int prec)
{
return wlc_prec_enq_head(wlc, q, pkt, prec, false);
}
-bool BCMFASTPATH
+bool
wlc_prec_enq_head(struct wlc_info *wlc, struct pktq *q, struct sk_buff *pkt,
int prec, bool head)
{
@@ -5072,11 +4613,10 @@
if (pktq_pfull(q, prec))
eprec = prec;
else if (pktq_full(q)) {
- p = pktq_peek_tail(q, &eprec);
- ASSERT(p != NULL);
+ p = bcm_pktq_peek_tail(q, &eprec);
if (eprec > prec) {
- WL_ERROR("%s: Failing: eprec %d > prec %d\n",
- __func__, eprec, prec);
+ wiphy_err(wlc->wiphy, "%s: Failing: eprec %d > prec %d"
+ "\n", __func__, eprec, prec);
return false;
}
}
@@ -5085,69 +4625,51 @@
if (eprec >= 0) {
bool discard_oldest;
- /* Detect queueing to unconfigured precedence */
- ASSERT(!pktq_pempty(q, eprec));
-
discard_oldest = AC_BITMAP_TST(wlc->wme_dp, eprec);
/* Refuse newer packet unless configured to discard oldest */
if (eprec == prec && !discard_oldest) {
- WL_ERROR("%s: No where to go, prec == %d\n",
- __func__, prec);
+ wiphy_err(wlc->wiphy, "%s: No where to go, prec == %d"
+ "\n", __func__, prec);
return false;
}
/* Evict packet according to discard policy */
- p = discard_oldest ? pktq_pdeq(q, eprec) : pktq_pdeq_tail(q,
- eprec);
- ASSERT(p != NULL);
-
- /* Increment wme stats */
- if (WME_ENAB(wlc->pub)) {
- WLCNTINCR(wlc->pub->_wme_cnt->
- tx_failed[WME_PRIO2AC(p->priority)].packets);
- WLCNTADD(wlc->pub->_wme_cnt->
- tx_failed[WME_PRIO2AC(p->priority)].bytes,
- pkttotlen(p));
- }
- pkt_buf_free_skb(p);
- wlc->pub->_cnt->txnobuf++;
+ p = discard_oldest ? bcm_pktq_pdeq(q, eprec) :
+ bcm_pktq_pdeq_tail(q, eprec);
+ bcm_pkt_buf_free_skb(p);
}
/* Enqueue */
if (head)
- p = pktq_penq_head(q, prec, pkt);
+ p = bcm_pktq_penq_head(q, prec, pkt);
else
- p = pktq_penq(q, prec, pkt);
- ASSERT(p != NULL);
+ p = bcm_pktq_penq(q, prec, pkt);
return true;
}
-void BCMFASTPATH wlc_txq_enq(void *ctx, struct scb *scb, struct sk_buff *sdu,
+void wlc_txq_enq(void *ctx, struct scb *scb, struct sk_buff *sdu,
uint prec)
{
struct wlc_info *wlc = (struct wlc_info *) ctx;
- struct wlc_txq_info *qi = wlc->active_queue; /* Check me */
+ struct wlc_txq_info *qi = wlc->pkt_queue; /* Check me */
struct pktq *q = &qi->q;
int prio;
prio = sdu->priority;
- ASSERT(pktq_max(q) >= wlc->pub->tunables->datahiwat);
-
if (!wlc_prec_enq(wlc, q, sdu, prec)) {
if (!EDCF_ENAB(wlc->pub)
|| (wlc->pub->wlfeatureflag & WL_SWFL_FLOWCONTROL))
- WL_ERROR("wl%d: wlc_txq_enq: txq overflow\n",
- wlc->pub->unit);
+ wiphy_err(wlc->wiphy, "wl%d: wlc_txq_enq: txq overflow"
+ "\n", wlc->pub->unit);
/*
* XXX we might hit this condtion in case
* packet flooding from mac80211 stack
*/
- pkt_buf_free_skb(sdu);
- wlc->pub->_cnt->txnobuf++;
+ bcm_pkt_buf_free_skb(sdu);
}
/* Check if flow control needs to be turned on after enqueuing the packet
@@ -5167,7 +4689,7 @@
}
}
-bool BCMFASTPATH
+bool
wlc_sendpkt_mac80211(struct wlc_info *wlc, struct sk_buff *sdu,
struct ieee80211_hw *hw)
{
@@ -5177,43 +4699,30 @@
struct scb *scb = &global_scb;
struct ieee80211_hdr *d11_header = (struct ieee80211_hdr *)(sdu->data);
- ASSERT(sdu);
-
/* 802.11 standard requires management traffic to go at highest priority */
prio = ieee80211_is_data(d11_header->frame_control) ? sdu->priority :
MAXPRIO;
fifo = prio2fifo[prio];
-
- ASSERT((uint) skb_headroom(sdu) >= TXOFF);
- ASSERT(!(sdu->next));
- ASSERT(!(sdu->prev));
- ASSERT(fifo < NFIFO);
-
pkt = sdu;
if (unlikely
(wlc_d11hdrs_mac80211(wlc, hw, pkt, scb, 0, 1, fifo, 0, NULL, 0)))
return -EINVAL;
wlc_txq_enq(wlc, scb, pkt, WLC_PRIO_TO_PREC(prio));
- wlc_send_q(wlc, wlc->active_queue);
-
- wlc->pub->_cnt->ieee_tx++;
+ wlc_send_q(wlc);
return 0;
}
-void BCMFASTPATH wlc_send_q(struct wlc_info *wlc, struct wlc_txq_info *qi)
+void wlc_send_q(struct wlc_info *wlc)
{
struct sk_buff *pkt[DOT11_MAXNUMFRAGS];
int prec;
u16 prec_map;
int err = 0, i, count;
uint fifo;
+ struct wlc_txq_info *qi = wlc->pkt_queue;
struct pktq *q = &qi->q;
struct ieee80211_tx_info *tx_info;
- /* only do work for the active queue */
- if (qi != wlc->active_queue)
- return;
-
if (in_send_q)
return;
else
@@ -5224,7 +4733,7 @@
/* Send all the enq'd pkts that we can.
* Dequeue packets with precedence with empty HW fifo only
*/
- while (prec_map && (pkt[0] = pktq_mdeq(q, prec_map, &prec))) {
+ while (prec_map && (pkt[0] = bcm_pktq_mdeq(q, prec_map, &prec))) {
tx_info = IEEE80211_SKB_CB(pkt[0]);
if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
err = wlc_sendampdu(wlc->ampdu, qi, pkt, prec);
@@ -5238,8 +4747,8 @@
}
}
- if (err == BCME_BUSY) {
- pktq_penq_head(q, prec, pkt[0]);
+ if (err == -EBUSY) {
+ bcm_pktq_penq_head(q, prec, pkt[0]);
/* If send failed due to any other reason than a change in
* HW FIFO condition, quit. Otherwise, read the new prec_map!
*/
@@ -5290,14 +4799,13 @@
return frameid;
}
-void BCMFASTPATH
+void
wlc_txfifo(struct wlc_info *wlc, uint fifo, struct sk_buff *p, bool commit,
s8 txpktpend)
{
u16 frameid = INVALIDFID;
d11txh_t *txh;
- ASSERT(fifo < NFIFO);
txh = (d11txh_t *) (p->data);
/* When a BC/MC frame is being committed to the BCMC fifo via DMA (NOT PIO), update
@@ -5317,7 +4825,7 @@
*/
if (commit) {
TXPKTPENDINC(wlc, fifo, txpktpend);
- WL_TRACE("wlc_txfifo, pktpend inc %d to %d\n",
+ BCMMSG(wlc->wiphy, "pktpend inc %d to %d\n",
txpktpend, TXPKTPENDGET(wlc, fifo));
}
@@ -5326,57 +4834,11 @@
BCMCFID(wlc, frameid);
if (dma_txfast(wlc->hw->di[fifo], p, commit) < 0) {
- WL_ERROR("wlc_txfifo: fatal, toss frames !!!\n");
+ wiphy_err(wlc->wiphy, "wlc_txfifo: fatal, toss frames !!!\n");
}
}
-static u16
-wlc_compute_airtime(struct wlc_info *wlc, ratespec_t rspec, uint length)
-{
- u16 usec = 0;
- uint mac_rate = RSPEC2RATE(rspec);
- uint nsyms;
-
- if (IS_MCS(rspec)) {
- /* not supported yet */
- ASSERT(0);
- } else if (IS_OFDM(rspec)) {
- /* nsyms = Ceiling(Nbits / (Nbits/sym))
- *
- * Nbits = length * 8
- * Nbits/sym = Mbps * 4 = mac_rate * 2
- */
- nsyms = CEIL((length * 8), (mac_rate * 2));
-
- /* usec = symbols * usec/symbol */
- usec = (u16) (nsyms * APHY_SYMBOL_TIME);
- return usec;
- } else {
- switch (mac_rate) {
- case WLC_RATE_1M:
- usec = length << 3;
- break;
- case WLC_RATE_2M:
- usec = length << 2;
- break;
- case WLC_RATE_5M5:
- usec = (length << 4) / 11;
- break;
- case WLC_RATE_11M:
- usec = (length << 3) / 11;
- break;
- default:
- WL_ERROR("wl%d: wlc_compute_airtime: unsupported rspec 0x%x\n",
- wlc->pub->unit, rspec);
- ASSERT((const char *)"Bad phy_rate" == NULL);
- break;
- }
- }
-
- return usec;
-}
-
-void BCMFASTPATH
+void
wlc_compute_plcp(struct wlc_info *wlc, ratespec_t rspec, uint length, u8 *plcp)
{
if (IS_MCS(rspec)) {
@@ -5384,7 +4846,7 @@
} else if (IS_OFDM(rspec)) {
wlc_compute_ofdm_plcp(rspec, length, plcp);
} else {
- wlc_compute_cck_plcp(rspec, length, plcp);
+ wlc_compute_cck_plcp(wlc, rspec, length, plcp);
}
return;
}
@@ -5393,7 +4855,6 @@
static void wlc_compute_mimo_plcp(ratespec_t rspec, uint length, u8 *plcp)
{
u8 mcs = (u8) (rspec & RSPEC_RATE_MASK);
- ASSERT(IS_MCS(rspec));
plcp[0] = mcs;
if (RSPEC_IS40MHZ(rspec) || (mcs == 32))
plcp[0] |= MIMO_PLCP_40MHZ;
@@ -5405,19 +4866,15 @@
}
/* Rate: 802.11 rate code, length: PSDU length in octets */
-static void BCMFASTPATH
+static void
wlc_compute_ofdm_plcp(ratespec_t rspec, u32 length, u8 *plcp)
{
u8 rate_signal;
u32 tmp = 0;
int rate = RSPEC2RATE(rspec);
- ASSERT(IS_OFDM(rspec));
-
/* encode rate per 802.11a-1999 sec 17.3.4.1, with lsb transmitted first */
- rate_signal = rate_info[rate] & RATE_MASK;
- ASSERT(rate_signal != 0);
-
+ rate_signal = rate_info[rate] & WLC_RATE_MASK;
memset(plcp, 0, D11_PHY_HDR_LEN);
D11A_PHY_HDR_SRATE((ofdm_phy_hdr_t *) plcp, rate_signal);
@@ -5436,7 +4893,8 @@
* Broken out for PRQ.
*/
-static void wlc_cck_plcp_set(int rate_500, uint length, u8 *plcp)
+static void wlc_cck_plcp_set(struct wlc_info *wlc, int rate_500, uint length,
+ u8 *plcp)
{
u16 usec = 0;
u8 le = 0;
@@ -5463,7 +4921,8 @@
break;
default:
- WL_ERROR("wlc_cck_plcp_set: unsupported rate %d\n", rate_500);
+ wiphy_err(wlc->wiphy, "wlc_cck_plcp_set: unsupported rate %d"
+ "\n", rate_500);
rate_500 = WLC_RATE_1M;
usec = length << 3;
break;
@@ -5481,13 +4940,12 @@
}
/* Rate: 802.11 rate code, length: PSDU length in octets */
-static void wlc_compute_cck_plcp(ratespec_t rspec, uint length, u8 *plcp)
+static void wlc_compute_cck_plcp(struct wlc_info *wlc, ratespec_t rspec,
+ uint length, u8 *plcp)
{
int rate = RSPEC2RATE(rspec);
- ASSERT(IS_CCK(rspec));
-
- wlc_cck_plcp_set(rate, length, plcp);
+ wlc_cck_plcp_set(wlc, rate, length, plcp);
}
/* wlc_compute_frame_dur()
@@ -5500,7 +4958,7 @@
* next_frag_len next MPDU length in bytes
* preamble_type use short/GF or long/MM PLCP header
*/
-static u16 BCMFASTPATH
+static u16
wlc_compute_frame_dur(struct wlc_info *wlc, ratespec_t rate, u8 preamble_type,
uint next_frag_len)
{
@@ -5534,7 +4992,7 @@
* rate next MPDU rate in unit of 500kbps
* frame_len next MPDU frame length in bytes
*/
-u16 BCMFASTPATH
+u16
wlc_compute_rtscts_dur(struct wlc_info *wlc, bool cts_only, ratespec_t rts_rate,
ratespec_t frame_rate, u8 rts_preamble_type,
u8 frame_preamble_type, uint frame_len, bool ba)
@@ -5566,33 +5024,7 @@
return dur;
}
-static bool wlc_phy_rspec_check(struct wlc_info *wlc, u16 bw, ratespec_t rspec)
-{
- if (IS_MCS(rspec)) {
- uint mcs = rspec & RSPEC_RATE_MASK;
-
- if (mcs < 8) {
- ASSERT(RSPEC_STF(rspec) < PHY_TXC1_MODE_SDM);
- } else if ((mcs >= 8) && (mcs <= 23)) {
- ASSERT(RSPEC_STF(rspec) == PHY_TXC1_MODE_SDM);
- } else if (mcs == 32) {
- ASSERT(RSPEC_STF(rspec) < PHY_TXC1_MODE_SDM);
- ASSERT(bw == PHY_TXC1_BW_40MHZ_DUP);
- }
- } else if (IS_OFDM(rspec)) {
- ASSERT(RSPEC_STF(rspec) < PHY_TXC1_MODE_STBC);
- } else {
- ASSERT(IS_CCK(rspec));
-
- ASSERT((bw == PHY_TXC1_BW_20MHZ)
- || (bw == PHY_TXC1_BW_20MHZ_UP));
- ASSERT(RSPEC_STF(rspec) == PHY_TXC1_MODE_SISO);
- }
-
- return true;
-}
-
-u16 BCMFASTPATH wlc_phytxctl1_calc(struct wlc_info *wlc, ratespec_t rspec)
+u16 wlc_phytxctl1_calc(struct wlc_info *wlc, ratespec_t rspec)
{
u16 phyctl1 = 0;
u16 bw;
@@ -5603,12 +5035,10 @@
bw = RSPEC_GET_BW(rspec);
/* 10Mhz is not supported yet */
if (bw < PHY_TXC1_BW_20MHZ) {
- WL_ERROR("wlc_phytxctl1_calc: bw %d is not supported yet, set to 20L\n",
- bw);
+ wiphy_err(wlc->wiphy, "wlc_phytxctl1_calc: bw %d is "
+ "not supported yet, set to 20L\n", bw);
bw = PHY_TXC1_BW_20MHZ;
}
-
- wlc_phy_rspec_check(wlc, bw, rspec);
}
if (IS_MCS(rspec)) {
@@ -5629,8 +5059,8 @@
/* get the phyctl byte from rate phycfg table */
phycfg = wlc_rate_legacy_phyctl(RSPEC2RATE(rspec));
if (phycfg == -1) {
- WL_ERROR("wlc_phytxctl1_calc: wrong legacy OFDM/CCK rate\n");
- ASSERT(0);
+ wiphy_err(wlc->wiphy, "wlc_phytxctl1_calc: wrong "
+ "legacy OFDM/CCK rate\n");
phycfg = 0;
}
/* set the upper byte of phyctl1 */
@@ -5638,18 +5068,10 @@
(bw | (phycfg << 8) |
(RSPEC_STF(rspec) << PHY_TXC1_MODE_SHIFT));
}
-
-#ifdef BCMDBG
- /* phy clock must support 40Mhz if tx descriptor uses it */
- if ((phyctl1 & PHY_TXC1_BW_MASK) >= PHY_TXC1_BW_40MHZ) {
- ASSERT(CHSPEC_WLC_BW(wlc->chanspec) == WLC_40_MHZ);
- ASSERT(wlc->chanspec == wlc_phy_chanspec_get(wlc->band->pi));
- }
-#endif /* BCMDBG */
return phyctl1;
}
-ratespec_t BCMFASTPATH
+ratespec_t
wlc_rspec_to_rts_rspec(struct wlc_info *wlc, ratespec_t rspec, bool use_rspec,
u16 mimo_ctlchbw)
{
@@ -5705,7 +5127,7 @@
* headroom == D11_PHY_HDR_LEN + D11_TXH_LEN (D11_TXH_LEN is now 104 bytes)
*
*/
-static u16 BCMFASTPATH
+static u16
wlc_d11hdrs_mac80211(struct wlc_info *wlc, struct ieee80211_hw *hw,
struct sk_buff *p, struct scb *scb, uint frag,
uint nfrags, uint queue, uint next_frag_len,
@@ -5744,14 +5166,12 @@
u16 mimo_txbw;
u8 mimo_preamble_type;
- ASSERT(queue < NFIFO);
-
/* locate 802.11 MAC header */
h = (struct ieee80211_hdr *)(p->data);
qos = ieee80211_is_data_qos(h->frame_control);
/* compute length of frame in bytes for use in PLCP computations */
- len = pkttotlen(p);
+ len = bcm_pkttotlen(p);
phylen = len + FCS_LEN;
/* If WEP enabled, add room in phylen for the additional bytes of
@@ -5765,7 +5185,6 @@
/* Get tx_info */
tx_info = IEEE80211_SKB_CB(p);
- ASSERT(tx_info);
/* add PLCP */
plcp = skb_push(p, D11_PHY_HDR_LEN);
@@ -5777,10 +5196,9 @@
/* setup frameid */
if (tx_info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
/* non-AP STA should never use BCMC queue */
- ASSERT(queue != TX_BCMC_FIFO);
if (queue == TX_BCMC_FIFO) {
- WL_ERROR("wl%d: %s: ASSERT queue == TX_BCMC!\n",
- WLCWLUNIT(wlc), __func__);
+ wiphy_err(wlc->wiphy, "wl%d: %s: ASSERT queue == "
+ "TX_BCMC!\n", WLCWLUNIT(wlc), __func__);
frameid = bcmc_fid_generate(wlc, NULL, txh);
} else {
/* Increment the counter for first fragment */
@@ -5803,13 +5221,9 @@
if (SCB_PS(scb) || ieee80211_is_beacon(h->frame_control))
mcl |= TXC_IGNOREPMQ;
- ASSERT(hw->max_rates <= IEEE80211_TX_MAX_RATES);
- ASSERT(hw->max_rates == 2);
-
txrate[0] = tx_info->control.rates;
txrate[1] = txrate[0] + 1;
- ASSERT(txrate[0]->idx >= 0);
/* if rate control algorithm didn't give us a fallback rate, use the primary rate */
if (txrate[1]->idx < 0) {
txrate[1] = txrate[0];
@@ -5819,7 +5233,6 @@
is_mcs[k] =
txrate[k]->flags & IEEE80211_TX_RC_MCS ? true : false;
if (!is_mcs[k]) {
- ASSERT(!(tx_info->flags & IEEE80211_TX_CTL_AMPDU));
if ((txrate[k]->idx >= 0)
&& (txrate[k]->idx <
hw->wiphy->bands[tx_info->band]->n_bitrates)) {
@@ -5831,10 +5244,6 @@
flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ?
true : false;
} else {
- ASSERT((txrate[k]->idx >= 0) &&
- (txrate[k]->idx <
- hw->wiphy->bands[tx_info->band]->
- n_bitrates));
rate_val[k] = WLC_RATE_1M;
}
} else {
@@ -5857,7 +5266,6 @@
/* (1) RATE: determine and validate primary rate and fallback rates */
if (!RSPEC_ACTIVE(rspec[k])) {
- ASSERT(RSPEC_ACTIVE(rspec[k]));
rspec[k] = WLC_RATE_1M;
} else {
if (!is_multicast_ether_addr(h->addr1)) {
@@ -5885,7 +5293,6 @@
&& WLC_STF_SS_STBC_TX(wlc, scb)) {
u8 stc;
- ASSERT(WLC_STBC_CAP_PHY(wlc));
stc = 1; /* Nss for single stream is always 1 */
rspec[k] |=
(PHY_TXC1_MODE_STBC <<
@@ -5918,7 +5325,6 @@
if (wlc->ofdm_40txbw != AUTO)
mimo_txbw = wlc->ofdm_40txbw;
} else {
- ASSERT(IS_CCK(rspec[k]));
if (wlc->cck_40txbw != AUTO)
mimo_txbw = wlc->cck_40txbw;
}
@@ -5957,9 +5363,9 @@
if ((txrate[k]->flags & IEEE80211_TX_RC_MCS)
&& (!IS_MCS(rspec[k]))) {
- WL_ERROR("wl%d: %s: IEEE80211_TX_RC_MCS != IS_MCS(rspec)\n",
- WLCWLUNIT(wlc), __func__);
- ASSERT(0 && "Rate mismatch");
+ wiphy_err(wlc->wiphy, "wl%d: %s: IEEE80211_TX_"
+ "RC_MCS != IS_MCS(rspec)\n",
+ WLCWLUNIT(wlc), __func__);
}
if (IS_MCS(rspec[k])) {
@@ -5973,22 +5379,15 @@
}
}
- /* mimo bw field MUST now be valid in the rspec (it affects duration calculations) */
- ASSERT(VALID_RATE_DBG(wlc, rspec[0]));
-
/* should be better conditionalized */
if (!IS_MCS(rspec[0])
&& (tx_info->control.rates[0].
flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE))
preamble_type[k] = WLC_SHORT_PREAMBLE;
-
- ASSERT(!IS_MCS(rspec[0])
- || WLC_IS_MIMO_PREAMBLE(preamble_type[k]));
}
} else {
for (k = 0; k < hw->max_rates; k++) {
/* Set ctrlchbw as 20Mhz */
- ASSERT(!IS_MCS(rspec[k]));
rspec[k] &= ~RSPEC_BW_MASK;
rspec[k] |= (PHY_TXC1_BW_20MHZ << RSPEC_BW_SHIFT);
@@ -6080,8 +5479,6 @@
/* Set fallback rate preamble type */
if ((preamble_type[1] == WLC_SHORT_PREAMBLE) ||
(preamble_type[1] == WLC_GF_PREAMBLE)) {
- ASSERT((preamble_type[1] == WLC_GF_PREAMBLE) ||
- (!IS_MCS(rspec[1])));
if (RSPEC2RATE(rspec[1]) != WLC_RATE_1M)
mch |= TXC_PREAMBLE_DATA_FB_SHORT;
}
@@ -6146,7 +5543,6 @@
}
/* RTS PLCP header */
- ASSERT(IS_ALIGNED((unsigned long)txh->RTSPhyHeader, sizeof(u16)));
rts_plcp = txh->RTSPhyHeader;
if (use_cts)
rts_phylen = DOT11_CTS_LEN + FCS_LEN;
@@ -6229,11 +5625,8 @@
phyctl = FRAMETYPE(rspec[0], wlc->mimoft);
if ((preamble_type[0] == WLC_SHORT_PREAMBLE) ||
(preamble_type[0] == WLC_GF_PREAMBLE)) {
- ASSERT((preamble_type[0] == WLC_GF_PREAMBLE)
- || !IS_MCS(rspec[0]));
if (RSPEC2RATE(rspec[0]) != WLC_RATE_1M)
phyctl |= PHY_TXC_SHORT_HDR;
- wlc->pub->_cnt->txprshort++;
}
/* phytxant is properly bit shifted */
@@ -6274,21 +5667,10 @@
}
}
- if (IS_MCS(rspec[0]))
- ASSERT(IS_MCS(rspec[1]));
-
- ASSERT(!IS_MCS(rspec[0]) ||
- ((preamble_type[0] == WLC_MM_PREAMBLE) == (txh->MModeLen != 0)));
- ASSERT(!IS_MCS(rspec[1]) ||
- ((preamble_type[1] == WLC_MM_PREAMBLE) ==
- (txh->MModeFbrLen != 0)));
-
ac = skb_get_queue_mapping(p);
if (SCB_WME(scb) && qos && wlc->edcf_txop[ac]) {
uint frag_dur, dur, dur_fallback;
- ASSERT(!is_multicast_ether_addr(h->addr1));
-
/* WME: Update TXOP threshold */
if ((!(tx_info->flags & IEEE80211_TX_CTL_AMPDU)) && (frag == 0)) {
frag_dur =
@@ -6359,16 +5741,18 @@
}
}
} else
- WL_ERROR("wl%d: %s txop invalid for rate %d\n",
- wlc->pub->unit, fifo_names[queue],
- RSPEC2RATE(rspec[0]));
+ wiphy_err(wlc->wiphy, "wl%d: %s txop invalid "
+ "for rate %d\n",
+ wlc->pub->unit, fifo_names[queue],
+ RSPEC2RATE(rspec[0]));
if (dur > wlc->edcf_txop[ac])
- WL_ERROR("wl%d: %s: %s txop exceeded phylen %d/%d dur %d/%d\n",
- wlc->pub->unit, __func__,
- fifo_names[queue],
- phylen, wlc->fragthresh[queue],
- dur, wlc->edcf_txop[ac]);
+ wiphy_err(wlc->wiphy, "wl%d: %s: %s txop "
+ "exceeded phylen %d/%d dur %d/%d\n",
+ wlc->pub->unit, __func__,
+ fifo_names[queue],
+ phylen, wlc->fragthresh[queue],
+ dur, wlc->edcf_txop[ac]);
}
}
@@ -6379,8 +5763,6 @@
{
struct wlc_bsscfg *cfg = wlc->cfg;
- wlc->pub->_cnt->tbtt++;
-
if (BSSCFG_STA(cfg)) {
/* run watchdog here if the watchdog timer is not armed */
if (WLC_WATCHDOG_TBTT(wlc)) {
@@ -6410,127 +5792,6 @@
}
}
-/* GP timer is a freerunning 32 bit counter, decrements at 1 us rate */
-void wlc_hwtimer_gptimer_set(struct wlc_info *wlc, uint us)
-{
- W_REG(&wlc->regs->gptimer, us);
-}
-
-void wlc_hwtimer_gptimer_abort(struct wlc_info *wlc)
-{
- W_REG(&wlc->regs->gptimer, 0);
-}
-
-static void wlc_hwtimer_gptimer_cb(struct wlc_info *wlc)
-{
- /* when interrupt is generated, the counter is loaded with last value
- * written and continue to decrement. So it has to be cleaned first
- */
- W_REG(&wlc->regs->gptimer, 0);
-}
-
-/*
- * This fn has all the high level dpc processing from wlc_dpc.
- * POLICY: no macinstatus change, no bounding loop.
- * All dpc bounding should be handled in BMAC dpc, like txstatus and rxint
- */
-void wlc_high_dpc(struct wlc_info *wlc, u32 macintstatus)
-{
- d11regs_t *regs = wlc->regs;
-#ifdef BCMDBG
- char flagstr[128];
- static const bcm_bit_desc_t int_flags[] = {
- {MI_MACSSPNDD, "MACSSPNDD"},
- {MI_BCNTPL, "BCNTPL"},
- {MI_TBTT, "TBTT"},
- {MI_BCNSUCCESS, "BCNSUCCESS"},
- {MI_BCNCANCLD, "BCNCANCLD"},
- {MI_ATIMWINEND, "ATIMWINEND"},
- {MI_PMQ, "PMQ"},
- {MI_NSPECGEN_0, "NSPECGEN_0"},
- {MI_NSPECGEN_1, "NSPECGEN_1"},
- {MI_MACTXERR, "MACTXERR"},
- {MI_NSPECGEN_3, "NSPECGEN_3"},
- {MI_PHYTXERR, "PHYTXERR"},
- {MI_PME, "PME"},
- {MI_GP0, "GP0"},
- {MI_GP1, "GP1"},
- {MI_DMAINT, "DMAINT"},
- {MI_TXSTOP, "TXSTOP"},
- {MI_CCA, "CCA"},
- {MI_BG_NOISE, "BG_NOISE"},
- {MI_DTIM_TBTT, "DTIM_TBTT"},
- {MI_PRQ, "PRQ"},
- {MI_PWRUP, "PWRUP"},
- {MI_RFDISABLE, "RFDISABLE"},
- {MI_TFS, "TFS"},
- {MI_PHYCHANGED, "PHYCHANGED"},
- {MI_TO, "TO"},
- {0, NULL}
- };
-
- if (macintstatus & ~(MI_TBTT | MI_TXSTOP)) {
- bcm_format_flags(int_flags, macintstatus, flagstr,
- sizeof(flagstr));
- WL_TRACE("wl%d: macintstatus 0x%x %s\n",
- wlc->pub->unit, macintstatus, flagstr);
- }
-#endif /* BCMDBG */
-
- if (macintstatus & MI_PRQ) {
- /* Process probe request FIFO */
- ASSERT(0 && "PRQ Interrupt in non-MBSS");
- }
-
- /* TBTT indication */
- /* ucode only gives either TBTT or DTIM_TBTT, not both */
- if (macintstatus & (MI_TBTT | MI_DTIM_TBTT))
- wlc_tbtt(wlc, regs);
-
- if (macintstatus & MI_GP0) {
- WL_ERROR("wl%d: PSM microcode watchdog fired at %d (seconds). Resetting.\n",
- wlc->pub->unit, wlc->pub->now);
-
- printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n",
- __func__, wlc->pub->sih->chip,
- wlc->pub->sih->chiprev);
-
- wlc->pub->_cnt->psmwds++;
-
- /* big hammer */
- wl_init(wlc->wl);
- }
-
- /* gptimer timeout */
- if (macintstatus & MI_TO) {
- wlc_hwtimer_gptimer_cb(wlc);
- }
-
- if (macintstatus & MI_RFDISABLE) {
- WL_ERROR("wl%d: MAC Detected a change on the RF Disable Input 0x%x\n",
- wlc->pub->unit,
- R_REG(®s->phydebug) & PDBG_RFD);
- /* delay the cleanup to wl_down in IBSS case */
- if ((R_REG(®s->phydebug) & PDBG_RFD)) {
- int idx;
- struct wlc_bsscfg *bsscfg;
- FOREACH_BSS(wlc, idx, bsscfg) {
- if (!BSSCFG_STA(bsscfg) || !bsscfg->enable
- || !bsscfg->BSS)
- continue;
- WL_ERROR("wl%d: wlc_dpc: rfdisable -> wlc_bsscfg_disable()\n",
- wlc->pub->unit);
- }
- }
- }
-
- /* send any enq'd tx packets. Just makes sure to jump start tx */
- if (!pktq_empty(&wlc->active_queue->q))
- wlc_send_q(wlc, wlc->active_queue);
-
- ASSERT(wlc_ps_check(wlc));
-}
-
static void wlc_war16165(struct wlc_info *wlc, bool tx)
{
if (tx) {
@@ -6546,7 +5807,7 @@
/* process an individual tx_status_t */
/* WLC_HIGH_API */
-bool BCMFASTPATH
+bool
wlc_dotxstatus(struct wlc_info *wlc, tx_status_t *txs, u32 frm_tx2)
{
struct sk_buff *p;
@@ -6572,16 +5833,12 @@
*/
if (!(txs->status & TX_STATUS_AMPDU)
&& (txs->status & TX_STATUS_INTERMEDIATE)) {
- WLCNTADD(wlc->pub->_cnt->txnoack,
- ((txs->
- status & TX_STATUS_FRM_RTX_MASK) >>
- TX_STATUS_FRM_RTX_SHIFT));
- WL_ERROR("%s: INTERMEDIATE but not AMPDU\n", __func__);
+ wiphy_err(wlc->wiphy, "%s: INTERMEDIATE but not AMPDU\n",
+ __func__);
return false;
}
queue = txs->frameid & TXFID_QUEUE_MASK;
- ASSERT(queue < NFIFO);
if (queue >= NFIFO) {
p = NULL;
goto fatal;
@@ -6598,41 +5855,31 @@
if (txs->phyerr) {
if (WL_ERROR_ON()) {
- WL_ERROR("phyerr 0x%x, rate 0x%x\n",
- txs->phyerr, txh->MainRates);
+ wiphy_err(wlc->wiphy, "phyerr 0x%x, rate 0x%x\n",
+ txs->phyerr, txh->MainRates);
wlc_print_txdesc(txh);
}
wlc_print_txstatus(txs);
}
- ASSERT(txs->frameid == cpu_to_le16(txh->TxFrameID));
if (txs->frameid != cpu_to_le16(txh->TxFrameID))
goto fatal;
-
tx_info = IEEE80211_SKB_CB(p);
h = (struct ieee80211_hdr *)((u8 *) (txh + 1) + D11_PHY_HDR_LEN);
if (tx_info->control.sta)
scb = (struct scb *)tx_info->control.sta->drv_priv;
- if (N_ENAB(wlc->pub)) {
- u8 *plcp = (u8 *) (txh + 1);
- if (PLCP3_ISSGI(plcp[3]))
- wlc->pub->_cnt->txmpdu_sgi++;
- if (PLCP3_ISSTBC(plcp[3]))
- wlc->pub->_cnt->txmpdu_stbc++;
- }
-
if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
- ASSERT((mcl & TXC_AMPDU_MASK) != TXC_AMPDU_NONE);
wlc_ampdu_dotxstatus(wlc->ampdu, scb, p, txs);
return false;
}
supr_status = txs->status & TX_STATUS_SUPR_MASK;
if (supr_status == TX_STATUS_SUPR_BADCH)
- WL_NONE("%s: Pkt tx suppressed, possibly channel %d\n",
- __func__, CHSPEC_CHANNEL(wlc->default_bss->chanspec));
+ BCMMSG(wlc->wiphy,
+ "%s: Pkt tx suppressed, possibly channel %d\n",
+ __func__, CHSPEC_CHANNEL(wlc->default_bss->chanspec));
tx_rts = cpu_to_le16(txh->MacTxControlLow) & TXC_SENDRTS;
tx_frame_count =
@@ -6643,7 +5890,7 @@
lastframe = !ieee80211_has_morefrags(h->frame_control);
if (!lastframe) {
- WL_ERROR("Not last frame!\n");
+ wiphy_err(wlc->wiphy, "Not last frame!\n");
} else {
u16 sfbl, lfbl;
ieee80211_tx_info_clear_status(tx_info);
@@ -6679,7 +5926,7 @@
tx_info->flags |= IEEE80211_TX_STAT_ACK;
}
- totlen = pkttotlen(p);
+ totlen = bcm_pkttotlen(p);
free_pdu = true;
wlc_txfifo_complete(wlc, queue, 1);
@@ -6692,33 +5939,30 @@
skb_pull(p, D11_PHY_HDR_LEN);
skb_pull(p, D11_TXH_LEN);
ieee80211_tx_status_irqsafe(wlc->pub->ieee_hw, p);
- wlc->pub->_cnt->ieee_tx_status++;
} else {
- WL_ERROR("%s: Not last frame => not calling tx_status\n",
- __func__);
+ wiphy_err(wlc->wiphy, "%s: Not last frame => not calling "
+ "tx_status\n", __func__);
}
return false;
fatal:
- ASSERT(0);
if (p)
- pkt_buf_free_skb(p);
+ bcm_pkt_buf_free_skb(p);
return true;
}
-void BCMFASTPATH
+void
wlc_txfifo_complete(struct wlc_info *wlc, uint fifo, s8 txpktpend)
{
TXPKTPENDDEC(wlc, fifo, txpktpend);
- WL_TRACE("wlc_txfifo_complete, pktpend dec %d to %d\n",
- txpktpend, TXPKTPENDGET(wlc, fifo));
+ BCMMSG(wlc->wiphy, "pktpend dec %d to %d\n", txpktpend,
+ TXPKTPENDGET(wlc, fifo));
/* There is more room; mark precedences related to this FIFO sendable */
WLC_TX_FIFO_ENAB(wlc, fifo);
- ASSERT(TXPKTPENDGET(wlc, fifo) >= 0);
if (!TXPKTPENDTOT(wlc)) {
if (wlc->block_datafifo & DATA_BLOCK_TX_SUPR)
@@ -6735,84 +5979,6 @@
/* figure out which bsscfg is being worked on... */
}
-/* Given the beacon interval in kus, and a 64 bit TSF in us,
- * return the offset (in us) of the TSF from the last TBTT
- */
-u32 wlc_calc_tbtt_offset(u32 bp, u32 tsf_h, u32 tsf_l)
-{
- u32 k, btklo, btkhi, offset;
-
- /* TBTT is always an even multiple of the beacon_interval,
- * so the TBTT less than or equal to the beacon timestamp is
- * the beacon timestamp minus the beacon timestamp modulo
- * the beacon interval.
- *
- * TBTT = BT - (BT % BIu)
- * = (BTk - (BTk % BP)) * 2^10
- *
- * BT = beacon timestamp (usec, 64bits)
- * BTk = beacon timestamp (Kusec, 54bits)
- * BP = beacon interval (Kusec, 16bits)
- * BIu = BP * 2^10 = beacon interval (usec, 26bits)
- *
- * To keep the calculations in u32s, the modulo operation
- * on the high part of BT needs to be done in parts using the
- * relations:
- * X*Y mod Z = ((X mod Z) * (Y mod Z)) mod Z
- * and
- * (X + Y) mod Z = ((X mod Z) + (Y mod Z)) mod Z
- *
- * So, if BTk[n] = u16 n [0,3] of BTk.
- * BTk % BP = SUM((BTk[n] * 2^16n) % BP , 0<=n<4) % BP
- * and the SUM term can be broken down:
- * (BTk[n] * 2^16n) % BP
- * (BTk[n] * (2^16n % BP)) % BP
- *
- * Create a set of power of 2 mod BP constants:
- * K[n] = 2^(16n) % BP
- * = (K[n-1] * 2^16) % BP
- * K[2] = 2^32 % BP = ((2^16 % BP) * 2^16) % BP
- *
- * BTk % BP = BTk[0-1] % BP +
- * (BTk[2] * K[2]) % BP +
- * (BTk[3] * K[3]) % BP
- *
- * Since K[n] < 2^16 and BTk[n] is < 2^16, then BTk[n] * K[n] < 2^32
- */
-
- /* BTk = BT >> 10, btklo = BTk[0-3], bkthi = BTk[4-6] */
- btklo = (tsf_h << 22) | (tsf_l >> 10);
- btkhi = tsf_h >> 10;
-
- /* offset = BTk % BP */
- offset = btklo % bp;
-
- /* K[2] = ((2^16 % BP) * 2^16) % BP */
- k = (u32) (1 << 16) % bp;
- k = (u32) (k * 1 << 16) % (u32) bp;
-
- /* offset += (BTk[2] * K[2]) % BP */
- offset += ((btkhi & 0xffff) * k) % bp;
-
- /* BTk[3] */
- btkhi = btkhi >> 16;
-
- /* k[3] = (K[2] * 2^16) % BP */
- k = (k << 16) % bp;
-
- /* offset += (BTk[3] * K[3]) % BP */
- offset += ((btkhi & 0xffff) * k) % bp;
-
- offset = offset % bp;
-
- /* convert offset from kus to us by shifting up 10 bits and
- * add in the low 10 bits of tsf that we ignored
- */
- offset = (offset << 10) + (tsf_l & 0x3FF);
-
- return offset;
-}
-
/* Update beacon listen interval in shared memory */
void wlc_bcn_li_upd(struct wlc_info *wlc)
{
@@ -6827,25 +5993,56 @@
(wlc->bcn_li_dtim << 8) | wlc->bcn_li_bcn);
}
+/*
+ * recover 64bit TSF value from the 16bit TSF value in the rx header
+ * given the assumption that the TSF passed in header is within 65ms
+ * of the current tsf.
+ *
+ * 6 5 4 4 3 2 1
+ * 3.......6.......8.......0.......2.......4.......6.......8......0
+ * |<---------- tsf_h ----------->||<--- tsf_l -->||<-RxTSFTime ->|
+ *
+ * The RxTSFTime are the lowest 16 bits and provided by the ucode. The
+ * tsf_l is filled in by wlc_bmac_recv, which is done earlier in the
+ * receive call sequence after rx interrupt. Only the higher 16 bits
+ * are used. Finally, the tsf_h is read from the tsf register.
+ */
+static u64 wlc_recover_tsf64(struct wlc_info *wlc, struct wlc_d11rxhdr *rxh)
+{
+ u32 tsf_h, tsf_l;
+ u16 rx_tsf_0_15, rx_tsf_16_31;
+
+ wlc_bmac_read_tsf(wlc->hw, &tsf_l, &tsf_h);
+
+ rx_tsf_16_31 = (u16)(tsf_l >> 16);
+ rx_tsf_0_15 = rxh->rxhdr.RxTSFTime;
+
+ /*
+ * a greater tsf time indicates the low 16 bits of
+ * tsf_l wrapped, so decrement the high 16 bits.
+ */
+ if ((u16)tsf_l < rx_tsf_0_15) {
+ rx_tsf_16_31 -= 1;
+ if (rx_tsf_16_31 == 0xffff)
+ tsf_h -= 1;
+ }
+
+ return ((u64)tsf_h << 32) | (((u32)rx_tsf_16_31 << 16) + rx_tsf_0_15);
+}
+
static void
prep_mac80211_status(struct wlc_info *wlc, d11rxhdr_t *rxh, struct sk_buff *p,
struct ieee80211_rx_status *rx_status)
{
- u32 tsf_l, tsf_h;
wlc_d11rxhdr_t *wlc_rxh = (wlc_d11rxhdr_t *) rxh;
int preamble;
int channel;
ratespec_t rspec;
unsigned char *plcp;
-#if 0
- /* Clearly, this is bogus -- reading the TSF now is wrong */
- wlc_read_tsf(wlc, &tsf_l, &tsf_h); /* mactime */
- rx_status->mactime = tsf_h;
- rx_status->mactime <<= 32;
- rx_status->mactime |= tsf_l;
- rx_status->flag |= RX_FLAG_MACTIME_MPDU; /* clearly wrong */
-#endif
+ /* fill in TSF and flag its presence */
+ rx_status->mactime = wlc_recover_tsf64(wlc, wlc_rxh);
+ rx_status->flag |= RX_FLAG_MACTIME_MPDU;
channel = WLC_CHAN_CHANNEL(rxh->RxChan);
@@ -6912,7 +6109,7 @@
rx_status->rate_idx = 11;
break;
default:
- WL_ERROR("%s: Unknown rate\n", __func__);
+ wiphy_err(wlc->wiphy, "%s: Unknown rate\n", __func__);
}
/* Determine short preamble and rate_idx */
@@ -6923,7 +6120,8 @@
} else if (IS_OFDM(rspec)) {
rx_status->flag |= RX_FLAG_SHORTPRE;
} else {
- WL_ERROR("%s: Unknown modulation\n", __func__);
+ wiphy_err(wlc->wiphy, "%s: Unknown modulation\n",
+ __func__);
}
}
@@ -6932,11 +6130,13 @@
if (rxh->RxStatus1 & RXS_DECERR) {
rx_status->flag |= RX_FLAG_FAILED_PLCP_CRC;
- WL_ERROR("%s: RX_FLAG_FAILED_PLCP_CRC\n", __func__);
+ wiphy_err(wlc->wiphy, "%s: RX_FLAG_FAILED_PLCP_CRC\n",
+ __func__);
}
if (rxh->RxStatus1 & RXS_FCSERR) {
rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
- WL_ERROR("%s: RX_FLAG_FAILED_FCS_CRC\n", __func__);
+ wiphy_err(wlc->wiphy, "%s: RX_FLAG_FAILED_FCS_CRC\n",
+ __func__);
}
}
@@ -6945,14 +6145,6 @@
{
int len_mpdu;
struct ieee80211_rx_status rx_status;
-#if defined(BCMDBG)
- struct sk_buff *skb = p;
-#endif /* BCMDBG */
- /* Todo:
- * Cache plcp for first MPDU of AMPD and use chacched version for INTERMEDIATE.
- * Test for INTERMEDIATE like so:
- * if (!(plcp[0] | plcp[1] | plcp[2]))
- */
memset(&rx_status, 0, sizeof(rx_status));
prep_mac80211_status(wlc, rxh, p, &rx_status);
@@ -6962,48 +6154,25 @@
skb_pull(p, D11_PHY_HDR_LEN);
__skb_trim(p, len_mpdu);
- ASSERT(!(p->next));
- ASSERT(!(p->prev));
-
- ASSERT(IS_ALIGNED((unsigned long)skb->data, 2));
-
memcpy(IEEE80211_SKB_RXCB(p), &rx_status, sizeof(rx_status));
ieee80211_rx_irqsafe(wlc->pub->ieee_hw, p);
-
- wlc->pub->_cnt->ieee_rx++;
return;
}
-void wlc_bss_list_free(struct wlc_info *wlc, struct wlc_bss_list *bss_list)
-{
- uint index;
-
- if (!bss_list) {
- WL_ERROR("%s: Attempting to free NULL list\n", __func__);
- return;
- }
- /* inspect all BSS descriptor */
- for (index = 0; index < bss_list->count; index++) {
- kfree(bss_list->ptrs[index]);
- bss_list->ptrs[index] = NULL;
- }
- bss_list->count = 0;
-}
-
/* Process received frames */
/*
* Return true if more frames need to be processed. false otherwise.
* Param 'bound' indicates max. # frames to process before break out.
*/
/* WLC_HIGH_API */
-void BCMFASTPATH wlc_recv(struct wlc_info *wlc, struct sk_buff *p)
+void wlc_recv(struct wlc_info *wlc, struct sk_buff *p)
{
d11rxhdr_t *rxh;
struct ieee80211_hdr *h;
uint len;
bool is_amsdu;
- WL_TRACE("wl%d: wlc_recv\n", wlc->pub->unit);
+ BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
/* frame starts with rxhdr */
rxh = (d11rxhdr_t *) (p->data);
@@ -7027,9 +6196,8 @@
/* MAC inserts 2 pad bytes for a4 headers or QoS or A-MSDU subframes */
if (rxh->RxStatus1 & RXS_PBPRES) {
if (p->len < 2) {
- wlc->pub->_cnt->rxrunt++;
- WL_ERROR("wl%d: wlc_recv: rcvd runt of len %d\n",
- wlc->pub->unit, p->len);
+ wiphy_err(wlc->wiphy, "wl%d: wlc_recv: rcvd runt of "
+ "len %d\n", wlc->pub->unit, p->len);
goto toss;
}
skb_pull(p, 2);
@@ -7040,17 +6208,17 @@
if (rxh->RxStatus1 & RXS_FCSERR) {
if (wlc->pub->mac80211_state & MAC80211_PROMISC_BCNS) {
- WL_ERROR("FCSERR while scanning******* - tossing\n");
+ wiphy_err(wlc->wiphy, "FCSERR while scanning******* -"
+ " tossing\n");
goto toss;
} else {
- WL_ERROR("RCSERR!!!\n");
+ wiphy_err(wlc->wiphy, "RCSERR!!!\n");
goto toss;
}
}
/* check received pkt has at least frame control field */
if (len < D11_PHY_HDR_LEN + sizeof(h->frame_control)) {
- wlc->pub->_cnt->rxrunt++;
goto toss;
}
@@ -7064,13 +6232,12 @@
ieee80211_is_mgmt(h->frame_control)) {
if ((is_zero_ether_addr(h->addr2) ||
is_multicast_ether_addr(h->addr2))) {
- WL_ERROR("wl%d: %s: dropping a frame with "
- "invalid src mac address, a2: %pM\n",
+ wiphy_err(wlc->wiphy, "wl%d: %s: dropping a "
+ "frame with invalid src mac address,"
+ " a2: %pM\n",
wlc->pub->unit, __func__, h->addr2);
- wlc->pub->_cnt->rxbadsrcmac++;
goto toss;
}
- wlc->pub->_cnt->rxfrag++;
}
}
@@ -7085,7 +6252,7 @@
return;
toss:
- pkt_buf_free_skb(p);
+ bcm_pkt_buf_free_skb(p);
}
/* calculate frame duration for Mixed-mode L-SIG spoofing, return
@@ -7094,12 +6261,12 @@
* Formula given by HT PHY Spec v 1.13
* len = 3(nsyms + nstream + 3) - 3
*/
-u16 BCMFASTPATH
+u16
wlc_calc_lsig_len(struct wlc_info *wlc, ratespec_t ratespec, uint mac_len)
{
uint nsyms, len = 0, kNdps;
- WL_TRACE("wl%d: wlc_calc_lsig_len: rate %d, len%d\n",
+ BCMMSG(wlc->wiphy, "wl%d: rate %d, len%d\n",
wlc->pub->unit, RSPEC2RATE(ratespec), mac_len);
if (IS_MCS(ratespec)) {
@@ -7107,7 +6274,6 @@
/* MCS_TXS(mcs) returns num tx streams - 1 */
int tot_streams = (MCS_TXS(mcs) + 1) + RSPEC_STC(ratespec);
- ASSERT(WLC_PHY_11N_CAP(wlc->band));
/* the payload duration calculation matches that of regular ofdm */
/* 1000Ndbps = kbps * 4 */
kNdps =
@@ -7135,7 +6301,7 @@
}
/* calculate frame duration of a given rate and length, return time in usec unit */
-uint BCMFASTPATH
+uint
wlc_calc_frame_time(struct wlc_info *wlc, ratespec_t ratespec, u8 preamble_type,
uint mac_len)
{
@@ -7143,19 +6309,17 @@
uint rate = RSPEC2RATE(ratespec);
if (rate == 0) {
- ASSERT(0);
- WL_ERROR("wl%d: WAR: using rate of 1 mbps\n", wlc->pub->unit);
+ wiphy_err(wlc->wiphy, "wl%d: WAR: using rate of 1 mbps\n",
+ wlc->pub->unit);
rate = WLC_RATE_1M;
}
- WL_TRACE("wl%d: wlc_calc_frame_time: rspec 0x%x, preamble_type %d, len%d\n",
+ BCMMSG(wlc->wiphy, "wl%d: rspec 0x%x, preamble_type %d, len%d\n",
wlc->pub->unit, ratespec, preamble_type, mac_len);
if (IS_MCS(ratespec)) {
uint mcs = ratespec & RSPEC_RATE_MASK;
int tot_streams = MCS_TXS(mcs) + RSPEC_STC(ratespec);
- ASSERT(WLC_PHY_11N_CAP(wlc->band));
- ASSERT(WLC_IS_MIMO_PREAMBLE(preamble_type));
dur = PREN_PREAMBLE + (tot_streams * PREN_PREAMBLE_EXT);
if (preamble_type == WLC_MM_PREAMBLE)
@@ -7213,13 +6377,12 @@
uint nsyms, mac_len, Ndps, kNdps;
uint rate = RSPEC2RATE(ratespec);
- WL_TRACE("wl%d: wlc_calc_frame_len: rspec 0x%x, preamble_type %d, dur %d\n",
+ BCMMSG(wlc->wiphy, "wl%d: rspec 0x%x, preamble_type %d, dur %d\n",
wlc->pub->unit, ratespec, preamble_type, dur);
if (IS_MCS(ratespec)) {
uint mcs = ratespec & RSPEC_RATE_MASK;
int tot_streams = MCS_TXS(mcs) + RSPEC_STC(ratespec);
- ASSERT(WLC_PHY_11N_CAP(wlc->band));
dur -= PREN_PREAMBLE + (tot_streams * PREN_PREAMBLE_EXT);
/* payload calculation matches that of regular ofdm */
if (BAND_2G(wlc->band->bandtype))
@@ -7256,33 +6419,29 @@
static uint
wlc_calc_ba_time(struct wlc_info *wlc, ratespec_t rspec, u8 preamble_type)
{
- WL_TRACE("wl%d: wlc_calc_ba_time: rspec 0x%x, preamble_type %d\n",
- wlc->pub->unit, rspec, preamble_type);
+ BCMMSG(wlc->wiphy, "wl%d: rspec 0x%x, "
+ "preamble_type %d\n", wlc->pub->unit, rspec, preamble_type);
/* Spec 9.6: ack rate is the highest rate in BSSBasicRateSet that is less than
* or equal to the rate of the immediately previous frame in the FES
*/
rspec = WLC_BASIC_RATE(wlc, rspec);
- ASSERT(VALID_RATE_DBG(wlc, rspec));
-
/* BA len == 32 == 16(ctl hdr) + 4(ba len) + 8(bitmap) + 4(fcs) */
return wlc_calc_frame_time(wlc, rspec, preamble_type,
(DOT11_BA_LEN + DOT11_BA_BITMAP_LEN +
FCS_LEN));
}
-static uint BCMFASTPATH
+static uint
wlc_calc_ack_time(struct wlc_info *wlc, ratespec_t rspec, u8 preamble_type)
{
uint dur = 0;
- WL_TRACE("wl%d: wlc_calc_ack_time: rspec 0x%x, preamble_type %d\n",
- wlc->pub->unit, rspec, preamble_type);
+ BCMMSG(wlc->wiphy, "wl%d: rspec 0x%x, preamble_type %d\n",
+ wlc->pub->unit, rspec, preamble_type);
/* Spec 9.6: ack rate is the highest rate in BSSBasicRateSet that is less than
* or equal to the rate of the immediately previous frame in the FES
*/
rspec = WLC_BASIC_RATE(wlc, rspec);
- ASSERT(VALID_RATE_DBG(wlc, rspec));
-
/* ACK frame len == 14 == 2(fc) + 2(dur) + 6(ra) + 4(fcs) */
dur =
wlc_calc_frame_time(wlc, rspec, preamble_type,
@@ -7293,8 +6452,8 @@
static uint
wlc_calc_cts_time(struct wlc_info *wlc, ratespec_t rspec, u8 preamble_type)
{
- WL_TRACE("wl%d: wlc_calc_cts_time: ratespec 0x%x, preamble_type %d\n",
- wlc->pub->unit, rspec, preamble_type);
+ BCMMSG(wlc->wiphy, "wl%d: ratespec 0x%x, preamble_type %d\n",
+ wlc->pub->unit, rspec, preamble_type);
return wlc_calc_ack_time(wlc, rspec, preamble_type);
}
@@ -7320,11 +6479,12 @@
continue;
/* mask off basic bit */
- rate = (rateset->rates[i] & RATE_MASK);
+ rate = (rateset->rates[i] & WLC_RATE_MASK);
if (rate > WLC_MAXRATE) {
- WL_ERROR("wlc_rate_lookup_init: invalid rate 0x%X in rate set\n",
- rateset->rates[i]);
+ wiphy_err(wlc->wiphy, "wlc_rate_lookup_init: invalid "
+ "rate 0x%X in rate set\n",
+ rateset->rates[i]);
continue;
}
@@ -7347,7 +6507,6 @@
for (i = 0; i < wlc->band->hw_rateset.count; i++) {
rate = wlc->band->hw_rateset.rates[i];
- ASSERT(rate <= WLC_MAXRATE);
if (br[rate] != 0) {
/* This rate is a basic rate.
@@ -7406,8 +6565,8 @@
* for a given rate, the LS-nibble of the PLCP SIGNAL field is
* the index into the rate table.
*/
- phy_rate = rate_info[rate] & RATE_MASK;
- basic_phy_rate = rate_info[basic_rate] & RATE_MASK;
+ phy_rate = rate_info[rate] & WLC_RATE_MASK;
+ basic_phy_rate = rate_info[basic_rate] & WLC_RATE_MASK;
index = phy_rate & 0xf;
basic_index = basic_phy_rate & 0xf;
@@ -7447,14 +6606,13 @@
uint i;
rs_dflt = wlc_rateset_get_hwrs(wlc);
- ASSERT(rs_dflt != NULL);
wlc_rateset_copy(rs_dflt, &rs);
wlc_rateset_mcs_upd(&rs, wlc->stf->txstreams);
/* walk the phy rate table and update SHM basic rate lookup table */
for (i = 0; i < rs.count; i++) {
- rate = rs.rates[i] & RATE_MASK;
+ rate = rs.rates[i] & WLC_RATE_MASK;
/* for a given rate WLC_BASIC_RATE returns the rate at
* which a response ACK/CTS should be sent.
@@ -7464,7 +6622,7 @@
/* This should only happen if we are using a
* restricted rateset.
*/
- basic_rate = rs.rates[0] & RATE_MASK;
+ basic_rate = rs.rates[0] & WLC_RATE_MASK;
}
wlc_write_rate_shm(wlc, rate, basic_rate);
@@ -7503,8 +6661,8 @@
return true;
error:
if (verbose) {
- WL_ERROR("wl%d: wlc_valid_rate: rate spec 0x%x not in hw_rateset\n",
- wlc->pub->unit, rspec);
+ wiphy_err(wlc->wiphy, "wl%d: wlc_valid_rate: rate spec 0x%x "
+ "not in hw_rateset\n", wlc->pub->unit, rspec);
}
return false;
@@ -7526,7 +6684,6 @@
else
band->mimo_cap_40 = false;
} else {
- ASSERT(band->bandtype == WLC_BAND_2G);
if (bwcap == WLC_N_BW_40ALL)
band->mimo_cap_40 = true;
else
@@ -7550,14 +6707,13 @@
sifs = SIFS(wlc->band);
rs_dflt = wlc_rateset_get_hwrs(wlc);
- ASSERT(rs_dflt != NULL);
wlc_rateset_copy(rs_dflt, &rs);
wlc_rateset_mcs_upd(&rs, wlc->stf->txstreams);
/* walk the phy rate table and update MAC core SHM basic rate table entries */
for (i = 0; i < rs.count; i++) {
- rate = rs.rates[i] & RATE_MASK;
+ rate = rs.rates[i] & WLC_RATE_MASK;
entry_ptr = wlc_rate_shm_offset(wlc, rate);
@@ -7579,41 +6735,6 @@
}
}
-u16
-wlc_compute_bcntsfoff(struct wlc_info *wlc, ratespec_t rspec,
- bool short_preamble, bool phydelay)
-{
- uint bcntsfoff = 0;
-
- if (IS_MCS(rspec)) {
- WL_ERROR("wl%d: recd beacon with mcs rate; rspec 0x%x\n",
- wlc->pub->unit, rspec);
- } else if (IS_OFDM(rspec)) {
- /* tx delay from MAC through phy to air (2.1 usec) +
- * phy header time (preamble + PLCP SIGNAL == 20 usec) +
- * PLCP SERVICE + MAC header time (SERVICE + FC + DUR + A1 + A2 + A3 + SEQ == 26
- * bytes at beacon rate)
- */
- bcntsfoff += phydelay ? D11A_PHY_TX_DELAY : 0;
- bcntsfoff += APHY_PREAMBLE_TIME + APHY_SIGNAL_TIME;
- bcntsfoff +=
- wlc_compute_airtime(wlc, rspec,
- APHY_SERVICE_NBITS / 8 +
- DOT11_MAC_HDR_LEN);
- } else {
- /* tx delay from MAC through phy to air (3.4 usec) +
- * phy header time (long preamble + PLCP == 192 usec) +
- * MAC header time (FC + DUR + A1 + A2 + A3 + SEQ == 24 bytes at beacon rate)
- */
- bcntsfoff += phydelay ? D11B_PHY_TX_DELAY : 0;
- bcntsfoff +=
- short_preamble ? D11B_PHY_SPREHDR_TIME :
- D11B_PHY_LPREHDR_TIME;
- bcntsfoff += wlc_compute_airtime(wlc, rspec, DOT11_MAC_HDR_LEN);
- }
- return (u16) (bcntsfoff);
-}
-
/* Max buffering needed for beacon template/prb resp template is 142 bytes.
*
* PLCP header is 6 bytes.
@@ -7635,10 +6756,6 @@
struct ieee80211_mgmt *h;
int hdr_len, body_len;
- ASSERT(*len >= 142);
- ASSERT(type == IEEE80211_STYPE_BEACON ||
- type == IEEE80211_STYPE_PROBE_RESP);
-
if (MBSS_BCN_ENAB(cfg) && type == IEEE80211_STYPE_BEACON)
hdr_len = DOT11_MAC_HDR_LEN;
else
@@ -7730,12 +6847,6 @@
wlc->bcn_rspec =
wlc_lowest_basic_rspec(wlc, &cfg->current_bss->rateset);
- ASSERT(wlc_valid_rate
- (wlc, wlc->bcn_rspec,
- CHSPEC_IS2G(cfg->current_bss->
- chanspec) ? WLC_BAND_2G : WLC_BAND_5G,
- true));
-
/* update the template and ucode shm */
wlc_bcn_prb_template(wlc, IEEE80211_STYPE_BEACON,
wlc->bcn_rspec, cfg, bcn, &len);
@@ -7825,7 +6936,7 @@
if (suspend)
wlc_enable_mac(wlc);
} else { /* Generating probe resp in sw; update local template */
- ASSERT(0 && "No software probe response support without MBSS");
+ /* error: No software probe response support without MBSS */
}
}
@@ -7837,11 +6948,8 @@
struct ieee80211_hdr *h;
struct scb *scb;
- ASSERT(pdu);
txh = (d11txh_t *) (pdu->data);
- ASSERT(txh);
h = (struct ieee80211_hdr *)((u8 *) (txh + 1) + D11_PHY_HDR_LEN);
- ASSERT(h);
/* get the pkt queue info. This was put at wlc_sendctl or wlc_send for PDU */
fifo = le16_to_cpu(txh->TxFrameID) & TXFID_QUEUE_MASK;
@@ -7854,12 +6962,8 @@
if (TXAVAIL(wlc, fifo) < MAX_DMA_SEGS) {
/* Mark precedences related to this FIFO, unsendable */
WLC_TX_FIFO_CLEAR(wlc, fifo);
- return BCME_BUSY;
+ return -EBUSY;
}
-
- if (!ieee80211_is_data(txh->MacFrameControl))
- wlc->pub->_cnt->txctl++;
-
return 0;
}
@@ -7889,7 +6993,7 @@
wlc_rev_info_t *rinfo = (wlc_rev_info_t *) buf;
if (len < WL_REV_INFO_LEGACY_LENGTH)
- return BCME_BUFTOOSHORT;
+ return -EOVERFLOW;
rinfo->vendorid = wlc->vendorid;
rinfo->deviceid = wlc->deviceid;
@@ -7915,13 +7019,13 @@
rinfo->chippkg = wlc->pub->sih->chippkg;
}
- return BCME_OK;
+ return 0;
}
void wlc_default_rateset(struct wlc_info *wlc, wlc_rateset_t *rs)
{
wlc_rateset_default(rs, NULL, wlc->band->phytype, wlc->band->bandtype,
- false, RATE_MASK_FULL, (bool) N_ENAB(wlc->pub),
+ false, WLC_RATE_MASK_FULL, (bool) N_ENAB(wlc->pub),
CHSPEC_WLC_BW(wlc->default_bss->chanspec),
wlc->stf->txstreams);
}
@@ -7943,8 +7047,6 @@
* starting from the 2G channels
*/
chanspec = CH20MHZ_CHSPEC(1);
- ASSERT(chanspec != INVCHANSPEC);
-
wlc->home_chanspec = bi->chanspec = chanspec;
/* find the band of our default channel */
@@ -7954,24 +7056,13 @@
/* init bss rates to the band specific default rate set */
wlc_rateset_default(&bi->rateset, NULL, band->phytype, band->bandtype,
- false, RATE_MASK_FULL, (bool) N_ENAB(wlc->pub),
+ false, WLC_RATE_MASK_FULL, (bool) N_ENAB(wlc->pub),
CHSPEC_WLC_BW(chanspec), wlc->stf->txstreams);
if (N_ENAB(wlc->pub))
bi->flags |= WLC_BSS_HT;
}
-void
-wlc_uint64_sub(u32 *a_high, u32 *a_low, u32 b_high, u32 b_low)
-{
- if (b_low > *a_low) {
- /* low half needs a carry */
- b_high += 1;
- }
- *a_low -= b_low;
- *a_high -= b_high;
-}
-
static ratespec_t
mac80211_wlc_set_nrate(struct wlc_info *wlc, struct wlcband *cur_band,
u32 int_val)
@@ -7993,9 +7084,9 @@
if (N_ENAB(wlc->pub) && ismcs) {
/* mcs only allowed when nmode */
if (stf > PHY_TXC1_MODE_SDM) {
- WL_ERROR("wl%d: %s: Invalid stf\n",
+ wiphy_err(wlc->wiphy, "wl%d: %s: Invalid stf\n",
WLCWLUNIT(wlc), __func__);
- bcmerror = BCME_RANGE;
+ bcmerror = -EINVAL;
goto done;
}
@@ -8004,17 +7095,18 @@
if (!CHSPEC_IS40(wlc->home_chanspec) ||
((stf != PHY_TXC1_MODE_SISO)
&& (stf != PHY_TXC1_MODE_CDD))) {
- WL_ERROR("wl%d: %s: Invalid mcs 32\n",
- WLCWLUNIT(wlc), __func__);
- bcmerror = BCME_RANGE;
+ wiphy_err(wlc->wiphy, "wl%d: %s: Invalid mcs "
+ "32\n", WLCWLUNIT(wlc), __func__);
+ bcmerror = -EINVAL;
goto done;
}
/* mcs > 7 must use stf SDM */
} else if (rate > HIGHEST_SINGLE_STREAM_MCS) {
/* mcs > 7 must use stf SDM */
if (stf != PHY_TXC1_MODE_SDM) {
- WL_TRACE("wl%d: %s: enabling SDM mode for mcs %d\n",
- WLCWLUNIT(wlc), __func__, rate);
+ BCMMSG(wlc->wiphy, "wl%d: enabling "
+ "SDM mode for mcs %d\n",
+ WLCWLUNIT(wlc), rate);
stf = PHY_TXC1_MODE_SDM;
}
} else {
@@ -8022,38 +7114,38 @@
if ((stf > PHY_TXC1_MODE_STBC) ||
(!WLC_STBC_CAP_PHY(wlc)
&& (stf == PHY_TXC1_MODE_STBC))) {
- WL_ERROR("wl%d: %s: Invalid STBC\n",
- WLCWLUNIT(wlc), __func__);
- bcmerror = BCME_RANGE;
+ wiphy_err(wlc->wiphy, "wl%d: %s: Invalid STBC"
+ "\n", WLCWLUNIT(wlc), __func__);
+ bcmerror = -EINVAL;
goto done;
}
}
} else if (IS_OFDM(rate)) {
if ((stf != PHY_TXC1_MODE_CDD) && (stf != PHY_TXC1_MODE_SISO)) {
- WL_ERROR("wl%d: %s: Invalid OFDM\n",
- WLCWLUNIT(wlc), __func__);
- bcmerror = BCME_RANGE;
+ wiphy_err(wlc->wiphy, "wl%d: %s: Invalid OFDM\n",
+ WLCWLUNIT(wlc), __func__);
+ bcmerror = -EINVAL;
goto done;
}
} else if (IS_CCK(rate)) {
if ((cur_band->bandtype != WLC_BAND_2G)
|| (stf != PHY_TXC1_MODE_SISO)) {
- WL_ERROR("wl%d: %s: Invalid CCK\n",
- WLCWLUNIT(wlc), __func__);
- bcmerror = BCME_RANGE;
+ wiphy_err(wlc->wiphy, "wl%d: %s: Invalid CCK\n",
+ WLCWLUNIT(wlc), __func__);
+ bcmerror = -EINVAL;
goto done;
}
} else {
- WL_ERROR("wl%d: %s: Unknown rate type\n",
- WLCWLUNIT(wlc), __func__);
- bcmerror = BCME_RANGE;
+ wiphy_err(wlc->wiphy, "wl%d: %s: Unknown rate type\n",
+ WLCWLUNIT(wlc), __func__);
+ bcmerror = -EINVAL;
goto done;
}
/* make sure multiple antennae are available for non-siso rates */
if ((stf != PHY_TXC1_MODE_SISO) && (wlc->stf->txstreams == 1)) {
- WL_ERROR("wl%d: %s: SISO antenna but !SISO request\n",
- WLCWLUNIT(wlc), __func__);
- bcmerror = BCME_RANGE;
+ wiphy_err(wlc->wiphy, "wl%d: %s: SISO antenna but !SISO "
+ "request\n", WLCWLUNIT(wlc), __func__);
+ bcmerror = -EINVAL;
goto done;
}
@@ -8082,8 +7174,7 @@
}
return rspec;
- done:
- WL_ERROR("Hoark\n");
+done:
return rate;
}
@@ -8097,8 +7188,9 @@
isOFDM ? M_TX_IDLE_BUSY_RATIO_X_16_OFDM :
M_TX_IDLE_BUSY_RATIO_X_16_CCK;
if (duty_cycle > 100 || duty_cycle < 0) {
- WL_ERROR("wl%d: duty cycle value off limit\n", wlc->pub->unit);
- return BCME_RANGE;
+ wiphy_err(wlc->wiphy, "wl%d: duty cycle value off limit\n",
+ wlc->pub->unit);
+ return -EINVAL;
}
if (duty_cycle)
idle_busy_ratio_x_16 = (100 - duty_cycle) * 16 / duty_cycle;
@@ -8111,7 +7203,7 @@
else
wlc->tx_duty_cycle_cck = (u16) duty_cycle;
- return BCME_OK;
+ return 0;
}
/* Read a single u16 from shared memory.
@@ -8130,22 +7222,6 @@
wlc_bmac_write_shm(wlc->hw, offset, v);
}
-/* Set a range of shared memory to a value.
- * SHM 'offset' needs to be an even address and
- * Range length 'len' must be an even number of bytes
- */
-void wlc_set_shm(struct wlc_info *wlc, uint offset, u16 v, int len)
-{
- /* offset and len need to be even */
- ASSERT((offset & 1) == 0);
- ASSERT((len & 1) == 0);
-
- if (len <= 0)
- return;
-
- wlc_bmac_set_shm(wlc->hw, offset, v, len);
-}
-
/* Copy a buffer to shared memory.
* SHM 'offset' needs to be an even address and
* Buffer length 'len' must be an even number of bytes
@@ -8153,52 +7229,24 @@
void wlc_copyto_shm(struct wlc_info *wlc, uint offset, const void *buf, int len)
{
/* offset and len need to be even */
- ASSERT((offset & 1) == 0);
- ASSERT((len & 1) == 0);
-
- if (len <= 0)
+ if (len <= 0 || (offset & 1) || (len & 1))
return;
+
wlc_bmac_copyto_objmem(wlc->hw, offset, buf, len, OBJADDR_SHM_SEL);
}
-/* Copy from shared memory to a buffer.
- * SHM 'offset' needs to be an even address and
- * Buffer length 'len' must be an even number of bytes
- */
-void wlc_copyfrom_shm(struct wlc_info *wlc, uint offset, void *buf, int len)
-{
- /* offset and len need to be even */
- ASSERT((offset & 1) == 0);
- ASSERT((len & 1) == 0);
-
- if (len <= 0)
- return;
-
- wlc_bmac_copyfrom_objmem(wlc->hw, offset, buf, len, OBJADDR_SHM_SEL);
-}
-
/* wrapper BMAC functions to for HIGH driver access */
void wlc_mctrl(struct wlc_info *wlc, u32 mask, u32 val)
{
wlc_bmac_mctrl(wlc->hw, mask, val);
}
-void wlc_corereset(struct wlc_info *wlc, u32 flags)
-{
- wlc_bmac_corereset(wlc->hw, flags);
-}
-
void wlc_mhf(struct wlc_info *wlc, u8 idx, u16 mask, u16 val, int bands)
{
wlc_bmac_mhf(wlc->hw, idx, mask, val, bands);
}
-u16 wlc_mhf_get(struct wlc_info *wlc, u8 idx, int bands)
-{
- return wlc_bmac_mhf_get(wlc->hw, idx, bands);
-}
-
int wlc_xmtfifo_sz_get(struct wlc_info *wlc, uint fifo, uint *blocks)
{
return wlc_bmac_xmtfifo_sz_get(wlc->hw, fifo, blocks);
@@ -8225,16 +7273,6 @@
memcpy(wlc->cfg->BSSID, addr, ETH_ALEN);
}
-void wlc_set_rcmta(struct wlc_info *wlc, int idx, const u8 *addr)
-{
- wlc_bmac_set_rcmta(wlc->hw, idx, addr);
-}
-
-void wlc_read_tsf(struct wlc_info *wlc, u32 *tsf_l_ptr, u32 *tsf_h_ptr)
-{
- wlc_bmac_read_tsf(wlc->hw, tsf_l_ptr, tsf_h_ptr);
-}
-
void wlc_set_cwmin(struct wlc_info *wlc, u16 newmin)
{
wlc->band->CWmin = newmin;
@@ -8247,12 +7285,6 @@
wlc_bmac_set_cwmax(wlc->hw, newmax);
}
-void wlc_fifoerrors(struct wlc_info *wlc)
-{
-
- wlc_bmac_fifoerrors(wlc->hw);
-}
-
/* Search mem rw utilities */
void wlc_pllreq(struct wlc_info *wlc, bool set, mbool req_bit)
@@ -8264,17 +7296,6 @@
{
}
-void wlc_ht_mimops_cap_update(struct wlc_info *wlc, u8 mimops_mode)
-{
- wlc->ht_cap.cap_info &= ~IEEE80211_HT_CAP_SM_PS;
- wlc->ht_cap.cap_info |= (mimops_mode << IEEE80211_HT_CAP_SM_PS_SHIFT);
-
- if (AP_ENAB(wlc->pub) && wlc->clk) {
- wlc_update_beacon(wlc);
- wlc_update_probe_resp(wlc, true);
- }
-}
-
/* check for the particular priority flow control bit being set */
bool
wlc_txflowcontrol_prio_isset(struct wlc_info *wlc, struct wlc_txq_info *q,
@@ -8285,7 +7306,6 @@
if (prio == ALLPRIO) {
prio_mask = TXQ_STOP_FOR_PRIOFC_MASK;
} else {
- ASSERT(prio >= 0 && prio <= MAXPRIO);
prio_mask = NBITVAL(prio);
}
@@ -8299,12 +7319,11 @@
uint prio_bits;
uint cur_bits;
- WL_TRACE("%s: flow control kicks in\n", __func__);
+ BCMMSG(wlc->wiphy, "flow control kicks in\n");
if (prio == ALLPRIO) {
prio_bits = TXQ_STOP_FOR_PRIOFC_MASK;
} else {
- ASSERT(prio >= 0 && prio <= MAXPRIO);
prio_bits = NBITVAL(prio);
}
@@ -8341,9 +7360,6 @@
{
uint prev_override;
- ASSERT(override != 0);
- ASSERT((override & TXQ_STOP_FOR_PRIOFC_MASK) == 0);
-
prev_override = (qi->stopped & ~TXQ_STOP_FOR_PRIOFC_MASK);
/* Update the flow control bits and do an early return if there is
@@ -8411,7 +7427,7 @@
{
struct wlc_txq_info *qi, *p;
- qi = wlc_calloc(wlc->pub->unit, sizeof(struct wlc_txq_info));
+ qi = kzalloc(sizeof(struct wlc_txq_info), GFP_ATOMIC);
if (qi != NULL) {
/*
* Have enough room for control packets along with HI watermark
@@ -8419,7 +7435,7 @@
* leave PS mode. The watermark for flowcontrol to OS packets
* will remain the same
*/
- pktq_init(&qi->q, WLC_PREC_COUNT,
+ bcm_pktq_init(&qi->q, WLC_PREC_COUNT,
(2 * wlc->pub->tunables->datahiwat) + PKTQ_LEN_DEFAULT
+ wlc->pub->psq_pkts_total);
@@ -8450,7 +7466,6 @@
else {
while (p != NULL && p->next != qi)
p = p->next;
- ASSERT(p->next == qi);
if (p != NULL)
p->next = p->next->next;
}
@@ -8494,3 +7509,21 @@
dma_walk_packets(dmah, dma_callback_fn, sta);
}
}
+
+int wlc_get_curband(struct wlc_info *wlc)
+{
+ return wlc->band->bandunit;
+}
+
+void wlc_wait_for_tx_completion(struct wlc_info *wlc, bool drop)
+{
+ /* flush packet queue when requested */
+ if (drop)
+ bcm_pktq_flush(&wlc->pkt_queue->q, false, NULL, NULL);
+
+ /* wait for queue and DMA fifos to run dry */
+ while (!pktq_empty(&wlc->pkt_queue->q) ||
+ TXPKTPENDTOT(wlc) > 0) {
+ wl_msleep(wlc->wl, 1);
+ }
+}
diff --git a/drivers/staging/brcm80211/brcmsmac/wlc_main.h b/drivers/staging/brcm80211/brcmsmac/wlc_main.h
index 960f82c..fb48dfcb9 100644
--- a/drivers/staging/brcm80211/brcmsmac/wlc_main.h
+++ b/drivers/staging/brcm80211/brcmsmac/wlc_main.h
@@ -98,7 +98,6 @@
(cfg)->wsec_portopen : true)
#define PS_ALLOWED(wlc) wlc_ps_allowed(wlc)
-#define STAY_AWAKE(wlc) wlc_stay_awake(wlc)
#define DATA_BLOCK_TX_SUPR (1 << 4)
@@ -166,9 +165,6 @@
#define WLC_PLLREQ_RADIO_MON 0x2 /* hold pll for radio monitor register checking */
#define WLC_PLLREQ_FLIP 0x4 /* hold/release pll for some short operation */
-/* Do we support this rate? */
-#define VALID_RATE_DBG(wlc, rspec) wlc_valid_rate(wlc, rspec, WLC_BAND_AUTO, true)
-
/*
* Macros to check if AP or STA is active.
* AP Active means more than just configured: driver and BSS are "up";
@@ -196,7 +192,7 @@
((wlc->hw->clk) ? \
((R_REG(&wlc->hw->regs->maccontrol) & \
(MCTL_PSM_JMP_0 | MCTL_IHR_EN)) != MCTL_IHR_EN) : \
- (si_deviceremoved(wlc->hw->sih)))
+ (ai_deviceremoved(wlc->hw->sih)))
#define WLCWLUNIT(wlc) ((wlc)->pub->unit)
@@ -746,9 +742,7 @@
u16 next_bsscfg_ID;
struct wlc_if *wlcif_list; /* linked list of wlc_if structs */
- struct wlc_txq_info *active_queue; /* txq for the currently active
- * transmit context
- */
+ struct wlc_txq_info *pkt_queue; /* txq for transmit packets */
u32 mpc_dur; /* total time (ms) in mpc mode except for the
* portion since radio is turned off last time
*/
@@ -757,6 +751,7 @@
*/
bool pr80838_war;
uint hwrxoff;
+ struct wiphy *wiphy;
};
/* antsel module specific state */
@@ -794,7 +789,6 @@
#define WLC_IS_MATCH_SSID(wlc, ssid1, ssid2, len1, len2) \
((len1 == len2) && !memcmp(ssid1, ssid2, len1))
-extern void wlc_high_dpc(struct wlc_info *wlc, u32 macintstatus);
extern void wlc_fatal_error(struct wlc_info *wlc);
extern void wlc_bmac_rpc_watchdog(struct wlc_info *wlc);
extern void wlc_recv(struct wlc_info *wlc, struct sk_buff *p);
@@ -811,21 +805,10 @@
void *buf);
extern void wlc_write_hw_bcntemplates(struct wlc_info *wlc, void *bcn, int len,
bool both);
-#if defined(BCMDBG)
-extern void wlc_get_rcmta(struct wlc_info *wlc, int idx,
- u8 *addr);
-#endif
-extern void wlc_set_rcmta(struct wlc_info *wlc, int idx,
- const u8 *addr);
-extern void wlc_read_tsf(struct wlc_info *wlc, u32 *tsf_l_ptr,
- u32 *tsf_h_ptr);
extern void wlc_set_cwmin(struct wlc_info *wlc, u16 newmin);
extern void wlc_set_cwmax(struct wlc_info *wlc, u16 newmax);
-extern void wlc_fifoerrors(struct wlc_info *wlc);
extern void wlc_pllreq(struct wlc_info *wlc, bool set, mbool req_bit);
extern void wlc_reset_bmac_done(struct wlc_info *wlc);
-extern void wlc_hwtimer_gptimer_set(struct wlc_info *wlc, uint us);
-extern void wlc_hwtimer_gptimer_abort(struct wlc_info *wlc);
#if defined(BCMDBG)
extern void wlc_print_rxh(d11rxhdr_t *rxh);
@@ -860,7 +843,7 @@
bool on, uint override);
extern bool wlc_txflowcontrol_prio_isset(struct wlc_info *wlc,
struct wlc_txq_info *qi, int prio);
-extern void wlc_send_q(struct wlc_info *wlc, struct wlc_txq_info *qi);
+extern void wlc_send_q(struct wlc_info *wlc);
extern int wlc_prep_pdu(struct wlc_info *wlc, struct sk_buff *pdu, uint *fifo);
extern u16 wlc_calc_lsig_len(struct wlc_info *wlc, ratespec_t ratespec,
@@ -883,21 +866,14 @@
struct bcmstrbuf *b);
#endif
-extern bool wlc_ps_check(struct wlc_info *wlc);
extern void wlc_reprate_init(struct wlc_info *wlc);
extern void wlc_bsscfg_reprate_init(struct wlc_bsscfg *bsscfg);
-extern void wlc_uint64_sub(u32 *a_high, u32 *a_low, u32 b_high,
- u32 b_low);
-extern u32 wlc_calc_tbtt_offset(u32 bi, u32 tsf_h, u32 tsf_l);
/* Shared memory access */
extern void wlc_write_shm(struct wlc_info *wlc, uint offset, u16 v);
extern u16 wlc_read_shm(struct wlc_info *wlc, uint offset);
-extern void wlc_set_shm(struct wlc_info *wlc, uint offset, u16 v, int len);
extern void wlc_copyto_shm(struct wlc_info *wlc, uint offset, const void *buf,
int len);
-extern void wlc_copyfrom_shm(struct wlc_info *wlc, uint offset, void *buf,
- int len);
extern void wlc_update_beacon(struct wlc_info *wlc);
extern void wlc_bss_update_beacon(struct wlc_info *wlc,
@@ -935,14 +911,13 @@
#endif
extern int wlc_set_nmode(struct wlc_info *wlc, s32 nmode);
-extern void wlc_ht_mimops_cap_update(struct wlc_info *wlc, u8 mimops_mode);
extern void wlc_mimops_action_ht_send(struct wlc_info *wlc,
struct wlc_bsscfg *bsscfg,
u8 mimops_mode);
extern void wlc_switch_shortslot(struct wlc_info *wlc, bool shortslot);
extern void wlc_set_bssid(struct wlc_bsscfg *cfg);
-extern void wlc_edcf_setparams(struct wlc_bsscfg *cfg, bool suspend);
+extern void wlc_edcf_setparams(struct wlc_info *wlc, bool suspend);
extern void wlc_set_ratetable(struct wlc_info *wlc);
extern int wlc_set_mac(struct wlc_bsscfg *cfg);
@@ -951,20 +926,14 @@
extern void wlc_mod_prb_rsp_rate_table(struct wlc_info *wlc, uint frame_len);
extern ratespec_t wlc_lowest_basic_rspec(struct wlc_info *wlc,
wlc_rateset_t *rs);
-extern u16 wlc_compute_bcntsfoff(struct wlc_info *wlc, ratespec_t rspec,
- bool short_preamble, bool phydelay);
extern void wlc_radio_disable(struct wlc_info *wlc);
extern void wlc_bcn_li_upd(struct wlc_info *wlc);
extern int wlc_get_revision_info(struct wlc_info *wlc, void *buf, uint len);
-extern void wlc_out(struct wlc_info *wlc);
extern void wlc_set_home_chanspec(struct wlc_info *wlc, chanspec_t chanspec);
extern void wlc_watchdog_upd(struct wlc_info *wlc, bool tbtt);
extern bool wlc_ps_allowed(struct wlc_info *wlc);
extern bool wlc_stay_awake(struct wlc_info *wlc);
extern void wlc_wme_initparams_sta(struct wlc_info *wlc, wme_param_ie_t *pe);
-extern void wlc_bss_list_free(struct wlc_info *wlc,
- struct wlc_bss_list *bss_list);
-extern void wlc_ht_mimops_cap_update(struct wlc_info *wlc, u8 mimops_mode);
#endif /* _wlc_h_ */
diff --git a/drivers/staging/brcm80211/brcmsmac/wlc_phy_shim.c b/drivers/staging/brcm80211/brcmsmac/wlc_phy_shim.c
index 96d3600..16fea02 100644
--- a/drivers/staging/brcm80211/brcmsmac/wlc_phy_shim.c
+++ b/drivers/staging/brcm80211/brcmsmac/wlc_phy_shim.c
@@ -29,14 +29,14 @@
#include <bcmdefs.h>
#include <bcmutils.h>
#include <bcmwifi.h>
-#include <siutils.h>
+#include <aiutils.h>
#include <wlioctl.h>
#include <sbconfig.h>
#include <sbchipc.h>
#include <pcicfg.h>
#include <sbhnddma.h>
#include <hnddma.h>
-#include <hndpmu.h>
+#include <wlc_pmu.h>
#include "wlc_types.h"
#include "wl_dbg.h"
@@ -68,8 +68,9 @@
physhim = kzalloc(sizeof(wlc_phy_shim_info_t), GFP_ATOMIC);
if (!physhim) {
- WL_ERROR("wl%d: wlc_phy_shim_attach: out of mem\n",
- wlc_hw->unit);
+ wiphy_err(wlc_hw->wlc->wiphy,
+ "wl%d: wlc_phy_shim_attach: out of mem\n",
+ wlc_hw->unit);
return NULL;
}
physhim->wlc_hw = wlc_hw;
diff --git a/drivers/staging/brcm80211/brcmsmac/wlc_pmu.c b/drivers/staging/brcm80211/brcmsmac/wlc_pmu.c
new file mode 100644
index 0000000..82986bd
--- /dev/null
+++ b/drivers/staging/brcm80211/brcmsmac/wlc_pmu.c
@@ -0,0 +1,1929 @@
+/*
+ * Copyright (c) 2011 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+
+#include <bcmdevs.h>
+#include <sbchipc.h>
+#include <bcmutils.h>
+#include <bcmnvram.h>
+#include "wlc_pmu.h"
+
+/*
+ * d11 slow to fast clock transition time in slow clock cycles
+ */
+#define D11SCC_SLOW2FAST_TRANSITION 2
+
+/*
+ * external LPO crystal frequency
+ */
+#define EXT_ILP_HZ 32768
+
+/*
+ * Duration for ILP clock frequency measurment in milliseconds
+ *
+ * remark: 1000 must be an integer multiple of this duration
+ */
+#define ILP_CALC_DUR 10
+
+/*
+ * FVCO frequency
+ */
+#define FVCO_880 880000 /* 880MHz */
+#define FVCO_1760 1760000 /* 1760MHz */
+#define FVCO_1440 1440000 /* 1440MHz */
+#define FVCO_960 960000 /* 960MHz */
+
+/*
+ * PMU crystal table indices for 1440MHz fvco
+ */
+#define PMU1_XTALTAB0_1440_12000K 0
+#define PMU1_XTALTAB0_1440_13000K 1
+#define PMU1_XTALTAB0_1440_14400K 2
+#define PMU1_XTALTAB0_1440_15360K 3
+#define PMU1_XTALTAB0_1440_16200K 4
+#define PMU1_XTALTAB0_1440_16800K 5
+#define PMU1_XTALTAB0_1440_19200K 6
+#define PMU1_XTALTAB0_1440_19800K 7
+#define PMU1_XTALTAB0_1440_20000K 8
+#define PMU1_XTALTAB0_1440_25000K 9
+#define PMU1_XTALTAB0_1440_26000K 10
+#define PMU1_XTALTAB0_1440_30000K 11
+#define PMU1_XTALTAB0_1440_37400K 12
+#define PMU1_XTALTAB0_1440_38400K 13
+#define PMU1_XTALTAB0_1440_40000K 14
+#define PMU1_XTALTAB0_1440_48000K 15
+
+/*
+ * PMU crystal table indices for 960MHz fvco
+ */
+#define PMU1_XTALTAB0_960_12000K 0
+#define PMU1_XTALTAB0_960_13000K 1
+#define PMU1_XTALTAB0_960_14400K 2
+#define PMU1_XTALTAB0_960_15360K 3
+#define PMU1_XTALTAB0_960_16200K 4
+#define PMU1_XTALTAB0_960_16800K 5
+#define PMU1_XTALTAB0_960_19200K 6
+#define PMU1_XTALTAB0_960_19800K 7
+#define PMU1_XTALTAB0_960_20000K 8
+#define PMU1_XTALTAB0_960_25000K 9
+#define PMU1_XTALTAB0_960_26000K 10
+#define PMU1_XTALTAB0_960_30000K 11
+#define PMU1_XTALTAB0_960_37400K 12
+#define PMU1_XTALTAB0_960_38400K 13
+#define PMU1_XTALTAB0_960_40000K 14
+#define PMU1_XTALTAB0_960_48000K 15
+
+/*
+ * PMU crystal table indices for 880MHz fvco
+ */
+#define PMU1_XTALTAB0_880_12000K 0
+#define PMU1_XTALTAB0_880_13000K 1
+#define PMU1_XTALTAB0_880_14400K 2
+#define PMU1_XTALTAB0_880_15360K 3
+#define PMU1_XTALTAB0_880_16200K 4
+#define PMU1_XTALTAB0_880_16800K 5
+#define PMU1_XTALTAB0_880_19200K 6
+#define PMU1_XTALTAB0_880_19800K 7
+#define PMU1_XTALTAB0_880_20000K 8
+#define PMU1_XTALTAB0_880_24000K 9
+#define PMU1_XTALTAB0_880_25000K 10
+#define PMU1_XTALTAB0_880_26000K 11
+#define PMU1_XTALTAB0_880_30000K 12
+#define PMU1_XTALTAB0_880_37400K 13
+#define PMU1_XTALTAB0_880_38400K 14
+#define PMU1_XTALTAB0_880_40000K 15
+
+/*
+ * crystal frequency values
+ */
+#define XTAL_FREQ_24000MHZ 24000
+#define XTAL_FREQ_30000MHZ 30000
+#define XTAL_FREQ_37400MHZ 37400
+#define XTAL_FREQ_48000MHZ 48000
+
+/*
+ * Resource dependancies mask change action
+ *
+ * @RES_DEPEND_SET: Override the dependancies mask
+ * @RES_DEPEND_ADD: Add to the dependancies mask
+ * @RES_DEPEND_REMOVE: Remove from the dependancies mask
+ */
+#define RES_DEPEND_SET 0
+#define RES_DEPEND_ADD 1
+#define RES_DEPEND_REMOVE -1
+
+/* d11 slow to fast clock transition time in slow clock cycles */
+#define D11SCC_SLOW2FAST_TRANSITION 2
+
+/* Setup resource up/down timers */
+typedef struct {
+ u8 resnum;
+ u16 updown;
+} pmu_res_updown_t;
+
+/* Change resource dependancies masks */
+typedef struct {
+ u32 res_mask; /* resources (chip specific) */
+ s8 action; /* action */
+ u32 depend_mask; /* changes to the dependancies mask */
+ bool(*filter) (si_t *sih); /* action is taken when filter is NULL or return true */
+} pmu_res_depend_t;
+
+/* setup pll and query clock speed */
+typedef struct {
+ u16 fref;
+ u8 xf;
+ u8 p1div;
+ u8 p2div;
+ u8 ndiv_int;
+ u32 ndiv_frac;
+} pmu1_xtaltab0_t;
+
+/*
+ * prototypes used in resource tables
+ */
+static bool si_pmu_res_depfltr_bb(si_t *sih);
+static bool si_pmu_res_depfltr_ncb(si_t *sih);
+static bool si_pmu_res_depfltr_paldo(si_t *sih);
+static bool si_pmu_res_depfltr_npaldo(si_t *sih);
+
+static const pmu_res_updown_t bcm4328a0_res_updown[] = {
+ {
+ RES4328_EXT_SWITCHER_PWM, 0x0101}, {
+ RES4328_BB_SWITCHER_PWM, 0x1f01}, {
+ RES4328_BB_SWITCHER_BURST, 0x010f}, {
+ RES4328_BB_EXT_SWITCHER_BURST, 0x0101}, {
+ RES4328_ILP_REQUEST, 0x0202}, {
+ RES4328_RADIO_SWITCHER_PWM, 0x0f01}, {
+ RES4328_RADIO_SWITCHER_BURST, 0x0f01}, {
+ RES4328_ROM_SWITCH, 0x0101}, {
+ RES4328_PA_REF_LDO, 0x0f01}, {
+ RES4328_RADIO_LDO, 0x0f01}, {
+ RES4328_AFE_LDO, 0x0f01}, {
+ RES4328_PLL_LDO, 0x0f01}, {
+ RES4328_BG_FILTBYP, 0x0101}, {
+ RES4328_TX_FILTBYP, 0x0101}, {
+ RES4328_RX_FILTBYP, 0x0101}, {
+ RES4328_XTAL_PU, 0x0101}, {
+ RES4328_XTAL_EN, 0xa001}, {
+ RES4328_BB_PLL_FILTBYP, 0x0101}, {
+ RES4328_RF_PLL_FILTBYP, 0x0101}, {
+ RES4328_BB_PLL_PU, 0x0701}
+};
+
+static const pmu_res_depend_t bcm4328a0_res_depend[] = {
+ /* Adjust ILP request resource not to force ext/BB switchers into burst mode */
+ {
+ PMURES_BIT(RES4328_ILP_REQUEST),
+ RES_DEPEND_SET,
+ PMURES_BIT(RES4328_EXT_SWITCHER_PWM) |
+ PMURES_BIT(RES4328_BB_SWITCHER_PWM), NULL}
+};
+
+static const pmu_res_updown_t bcm4325a0_res_updown_qt[] = {
+ {
+ RES4325_HT_AVAIL, 0x0300}, {
+ RES4325_BBPLL_PWRSW_PU, 0x0101}, {
+ RES4325_RFPLL_PWRSW_PU, 0x0101}, {
+ RES4325_ALP_AVAIL, 0x0100}, {
+ RES4325_XTAL_PU, 0x1000}, {
+ RES4325_LNLDO1_PU, 0x0800}, {
+ RES4325_CLDO_CBUCK_PWM, 0x0101}, {
+ RES4325_CBUCK_PWM, 0x0803}
+};
+
+static const pmu_res_updown_t bcm4325a0_res_updown[] = {
+ {
+ RES4325_XTAL_PU, 0x1501}
+};
+
+static const pmu_res_depend_t bcm4325a0_res_depend[] = {
+ /* Adjust OTP PU resource dependencies - remove BB BURST */
+ {
+ PMURES_BIT(RES4325_OTP_PU),
+ RES_DEPEND_REMOVE,
+ PMURES_BIT(RES4325_BUCK_BOOST_BURST), NULL},
+ /* Adjust ALP/HT Avail resource dependencies - bring up BB along if it is used. */
+ {
+ PMURES_BIT(RES4325_ALP_AVAIL) | PMURES_BIT(RES4325_HT_AVAIL),
+ RES_DEPEND_ADD,
+ PMURES_BIT(RES4325_BUCK_BOOST_BURST) |
+ PMURES_BIT(RES4325_BUCK_BOOST_PWM), si_pmu_res_depfltr_bb},
+ /* Adjust HT Avail resource dependencies - bring up RF switches along with HT. */
+ {
+ PMURES_BIT(RES4325_HT_AVAIL),
+ RES_DEPEND_ADD,
+ PMURES_BIT(RES4325_RX_PWRSW_PU) |
+ PMURES_BIT(RES4325_TX_PWRSW_PU) |
+ PMURES_BIT(RES4325_LOGEN_PWRSW_PU) |
+ PMURES_BIT(RES4325_AFE_PWRSW_PU), NULL},
+ /* Adjust ALL resource dependencies - remove CBUCK dependancies if it is not used. */
+ {
+ PMURES_BIT(RES4325_ILP_REQUEST) |
+ PMURES_BIT(RES4325_ABUCK_BURST) |
+ PMURES_BIT(RES4325_ABUCK_PWM) |
+ PMURES_BIT(RES4325_LNLDO1_PU) |
+ PMURES_BIT(RES4325C1_LNLDO2_PU) |
+ PMURES_BIT(RES4325_XTAL_PU) |
+ PMURES_BIT(RES4325_ALP_AVAIL) |
+ PMURES_BIT(RES4325_RX_PWRSW_PU) |
+ PMURES_BIT(RES4325_TX_PWRSW_PU) |
+ PMURES_BIT(RES4325_RFPLL_PWRSW_PU) |
+ PMURES_BIT(RES4325_LOGEN_PWRSW_PU) |
+ PMURES_BIT(RES4325_AFE_PWRSW_PU) |
+ PMURES_BIT(RES4325_BBPLL_PWRSW_PU) |
+ PMURES_BIT(RES4325_HT_AVAIL), RES_DEPEND_REMOVE,
+ PMURES_BIT(RES4325B0_CBUCK_LPOM) |
+ PMURES_BIT(RES4325B0_CBUCK_BURST) |
+ PMURES_BIT(RES4325B0_CBUCK_PWM), si_pmu_res_depfltr_ncb}
+};
+
+static const pmu_res_updown_t bcm4315a0_res_updown_qt[] = {
+ {
+ RES4315_HT_AVAIL, 0x0101}, {
+ RES4315_XTAL_PU, 0x0100}, {
+ RES4315_LNLDO1_PU, 0x0100}, {
+ RES4315_PALDO_PU, 0x0100}, {
+ RES4315_CLDO_PU, 0x0100}, {
+ RES4315_CBUCK_PWM, 0x0100}, {
+ RES4315_CBUCK_BURST, 0x0100}, {
+ RES4315_CBUCK_LPOM, 0x0100}
+};
+
+static const pmu_res_updown_t bcm4315a0_res_updown[] = {
+ {
+ RES4315_XTAL_PU, 0x2501}
+};
+
+static const pmu_res_depend_t bcm4315a0_res_depend[] = {
+ /* Adjust OTP PU resource dependencies - not need PALDO unless write */
+ {
+ PMURES_BIT(RES4315_OTP_PU),
+ RES_DEPEND_REMOVE,
+ PMURES_BIT(RES4315_PALDO_PU), si_pmu_res_depfltr_npaldo},
+ /* Adjust ALP/HT Avail resource dependencies - bring up PALDO along if it is used. */
+ {
+ PMURES_BIT(RES4315_ALP_AVAIL) | PMURES_BIT(RES4315_HT_AVAIL),
+ RES_DEPEND_ADD,
+ PMURES_BIT(RES4315_PALDO_PU), si_pmu_res_depfltr_paldo},
+ /* Adjust HT Avail resource dependencies - bring up RF switches along with HT. */
+ {
+ PMURES_BIT(RES4315_HT_AVAIL),
+ RES_DEPEND_ADD,
+ PMURES_BIT(RES4315_RX_PWRSW_PU) |
+ PMURES_BIT(RES4315_TX_PWRSW_PU) |
+ PMURES_BIT(RES4315_LOGEN_PWRSW_PU) |
+ PMURES_BIT(RES4315_AFE_PWRSW_PU), NULL},
+ /* Adjust ALL resource dependencies - remove CBUCK dependancies if it is not used. */
+ {
+ PMURES_BIT(RES4315_CLDO_PU) | PMURES_BIT(RES4315_ILP_REQUEST) |
+ PMURES_BIT(RES4315_LNLDO1_PU) |
+ PMURES_BIT(RES4315_OTP_PU) |
+ PMURES_BIT(RES4315_LNLDO2_PU) |
+ PMURES_BIT(RES4315_XTAL_PU) |
+ PMURES_BIT(RES4315_ALP_AVAIL) |
+ PMURES_BIT(RES4315_RX_PWRSW_PU) |
+ PMURES_BIT(RES4315_TX_PWRSW_PU) |
+ PMURES_BIT(RES4315_RFPLL_PWRSW_PU) |
+ PMURES_BIT(RES4315_LOGEN_PWRSW_PU) |
+ PMURES_BIT(RES4315_AFE_PWRSW_PU) |
+ PMURES_BIT(RES4315_BBPLL_PWRSW_PU) |
+ PMURES_BIT(RES4315_HT_AVAIL), RES_DEPEND_REMOVE,
+ PMURES_BIT(RES4315_CBUCK_LPOM) |
+ PMURES_BIT(RES4315_CBUCK_BURST) |
+ PMURES_BIT(RES4315_CBUCK_PWM), si_pmu_res_depfltr_ncb}
+};
+
+ /* 4329 specific. needs to come back this issue later */
+static const pmu_res_updown_t bcm4329_res_updown[] = {
+ {
+ RES4329_XTAL_PU, 0x1501}
+};
+
+static const pmu_res_depend_t bcm4329_res_depend[] = {
+ /* Adjust HT Avail resource dependencies */
+ {
+ PMURES_BIT(RES4329_HT_AVAIL),
+ RES_DEPEND_ADD,
+ PMURES_BIT(RES4329_CBUCK_LPOM) |
+ PMURES_BIT(RES4329_CBUCK_BURST) |
+ PMURES_BIT(RES4329_CBUCK_PWM) |
+ PMURES_BIT(RES4329_CLDO_PU) |
+ PMURES_BIT(RES4329_PALDO_PU) |
+ PMURES_BIT(RES4329_LNLDO1_PU) |
+ PMURES_BIT(RES4329_XTAL_PU) |
+ PMURES_BIT(RES4329_ALP_AVAIL) |
+ PMURES_BIT(RES4329_RX_PWRSW_PU) |
+ PMURES_BIT(RES4329_TX_PWRSW_PU) |
+ PMURES_BIT(RES4329_RFPLL_PWRSW_PU) |
+ PMURES_BIT(RES4329_LOGEN_PWRSW_PU) |
+ PMURES_BIT(RES4329_AFE_PWRSW_PU) |
+ PMURES_BIT(RES4329_BBPLL_PWRSW_PU), NULL}
+};
+
+static const pmu_res_updown_t bcm4319a0_res_updown_qt[] = {
+ {
+ RES4319_HT_AVAIL, 0x0101}, {
+ RES4319_XTAL_PU, 0x0100}, {
+ RES4319_LNLDO1_PU, 0x0100}, {
+ RES4319_PALDO_PU, 0x0100}, {
+ RES4319_CLDO_PU, 0x0100}, {
+ RES4319_CBUCK_PWM, 0x0100}, {
+ RES4319_CBUCK_BURST, 0x0100}, {
+ RES4319_CBUCK_LPOM, 0x0100}
+};
+
+static const pmu_res_updown_t bcm4319a0_res_updown[] = {
+ {
+ RES4319_XTAL_PU, 0x3f01}
+};
+
+static const pmu_res_depend_t bcm4319a0_res_depend[] = {
+ /* Adjust OTP PU resource dependencies - not need PALDO unless write */
+ {
+ PMURES_BIT(RES4319_OTP_PU),
+ RES_DEPEND_REMOVE,
+ PMURES_BIT(RES4319_PALDO_PU), si_pmu_res_depfltr_npaldo},
+ /* Adjust HT Avail resource dependencies - bring up PALDO along if it is used. */
+ {
+ PMURES_BIT(RES4319_HT_AVAIL),
+ RES_DEPEND_ADD,
+ PMURES_BIT(RES4319_PALDO_PU), si_pmu_res_depfltr_paldo},
+ /* Adjust HT Avail resource dependencies - bring up RF switches along with HT. */
+ {
+ PMURES_BIT(RES4319_HT_AVAIL),
+ RES_DEPEND_ADD,
+ PMURES_BIT(RES4319_RX_PWRSW_PU) |
+ PMURES_BIT(RES4319_TX_PWRSW_PU) |
+ PMURES_BIT(RES4319_RFPLL_PWRSW_PU) |
+ PMURES_BIT(RES4319_LOGEN_PWRSW_PU) |
+ PMURES_BIT(RES4319_AFE_PWRSW_PU), NULL}
+};
+
+static const pmu_res_updown_t bcm4336a0_res_updown_qt[] = {
+ {
+ RES4336_HT_AVAIL, 0x0101}, {
+ RES4336_XTAL_PU, 0x0100}, {
+ RES4336_CLDO_PU, 0x0100}, {
+ RES4336_CBUCK_PWM, 0x0100}, {
+ RES4336_CBUCK_BURST, 0x0100}, {
+ RES4336_CBUCK_LPOM, 0x0100}
+};
+
+static const pmu_res_updown_t bcm4336a0_res_updown[] = {
+ {
+ RES4336_HT_AVAIL, 0x0D01}
+};
+
+static const pmu_res_depend_t bcm4336a0_res_depend[] = {
+ /* Just a dummy entry for now */
+ {
+ PMURES_BIT(RES4336_RSVD), RES_DEPEND_ADD, 0, NULL}
+};
+
+static const pmu_res_updown_t bcm4330a0_res_updown_qt[] = {
+ {
+ RES4330_HT_AVAIL, 0x0101}, {
+ RES4330_XTAL_PU, 0x0100}, {
+ RES4330_CLDO_PU, 0x0100}, {
+ RES4330_CBUCK_PWM, 0x0100}, {
+ RES4330_CBUCK_BURST, 0x0100}, {
+ RES4330_CBUCK_LPOM, 0x0100}
+};
+
+static const pmu_res_updown_t bcm4330a0_res_updown[] = {
+ {
+ RES4330_HT_AVAIL, 0x0e02}
+};
+
+static const pmu_res_depend_t bcm4330a0_res_depend[] = {
+ /* Just a dummy entry for now */
+ {
+ PMURES_BIT(RES4330_HT_AVAIL), RES_DEPEND_ADD, 0, NULL}
+};
+
+/* the following table is based on 1440Mhz fvco */
+static const pmu1_xtaltab0_t pmu1_xtaltab0_1440[] = {
+ {
+ 12000, 1, 1, 1, 0x78, 0x0}, {
+ 13000, 2, 1, 1, 0x6E, 0xC4EC4E}, {
+ 14400, 3, 1, 1, 0x64, 0x0}, {
+ 15360, 4, 1, 1, 0x5D, 0xC00000}, {
+ 16200, 5, 1, 1, 0x58, 0xE38E38}, {
+ 16800, 6, 1, 1, 0x55, 0xB6DB6D}, {
+ 19200, 7, 1, 1, 0x4B, 0}, {
+ 19800, 8, 1, 1, 0x48, 0xBA2E8B}, {
+ 20000, 9, 1, 1, 0x48, 0x0}, {
+ 25000, 10, 1, 1, 0x39, 0x999999}, {
+ 26000, 11, 1, 1, 0x37, 0x627627}, {
+ 30000, 12, 1, 1, 0x30, 0x0}, {
+ 37400, 13, 2, 1, 0x4D, 0x15E76}, {
+ 38400, 13, 2, 1, 0x4B, 0x0}, {
+ 40000, 14, 2, 1, 0x48, 0x0}, {
+ 48000, 15, 2, 1, 0x3c, 0x0}, {
+ 0, 0, 0, 0, 0, 0}
+};
+
+static const pmu1_xtaltab0_t pmu1_xtaltab0_960[] = {
+ {
+ 12000, 1, 1, 1, 0x50, 0x0}, {
+ 13000, 2, 1, 1, 0x49, 0xD89D89}, {
+ 14400, 3, 1, 1, 0x42, 0xAAAAAA}, {
+ 15360, 4, 1, 1, 0x3E, 0x800000}, {
+ 16200, 5, 1, 1, 0x39, 0x425ED0}, {
+ 16800, 6, 1, 1, 0x39, 0x249249}, {
+ 19200, 7, 1, 1, 0x32, 0x0}, {
+ 19800, 8, 1, 1, 0x30, 0x7C1F07}, {
+ 20000, 9, 1, 1, 0x30, 0x0}, {
+ 25000, 10, 1, 1, 0x26, 0x666666}, {
+ 26000, 11, 1, 1, 0x24, 0xEC4EC4}, {
+ 30000, 12, 1, 1, 0x20, 0x0}, {
+ 37400, 13, 2, 1, 0x33, 0x563EF9}, {
+ 38400, 14, 2, 1, 0x32, 0x0}, {
+ 40000, 15, 2, 1, 0x30, 0x0}, {
+ 48000, 16, 2, 1, 0x28, 0x0}, {
+ 0, 0, 0, 0, 0, 0}
+};
+
+static const pmu1_xtaltab0_t pmu1_xtaltab0_880_4329[] = {
+ {
+ 12000, 1, 3, 22, 0x9, 0xFFFFEF}, {
+ 13000, 2, 1, 6, 0xb, 0x483483}, {
+ 14400, 3, 1, 10, 0xa, 0x1C71C7}, {
+ 15360, 4, 1, 5, 0xb, 0x755555}, {
+ 16200, 5, 1, 10, 0x5, 0x6E9E06}, {
+ 16800, 6, 1, 10, 0x5, 0x3Cf3Cf}, {
+ 19200, 7, 1, 4, 0xb, 0x755555}, {
+ 19800, 8, 1, 11, 0x4, 0xA57EB}, {
+ 20000, 9, 1, 11, 0x4, 0x0}, {
+ 24000, 10, 3, 11, 0xa, 0x0}, {
+ 25000, 11, 5, 16, 0xb, 0x0}, {
+ 26000, 12, 1, 1, 0x21, 0xD89D89}, {
+ 30000, 13, 3, 8, 0xb, 0x0}, {
+ 37400, 14, 3, 1, 0x46, 0x969696}, {
+ 38400, 15, 1, 1, 0x16, 0xEAAAAA}, {
+ 40000, 16, 1, 2, 0xb, 0}, {
+ 0, 0, 0, 0, 0, 0}
+};
+
+/* the following table is based on 880Mhz fvco */
+static const pmu1_xtaltab0_t pmu1_xtaltab0_880[] = {
+ {
+ 12000, 1, 3, 22, 0x9, 0xFFFFEF}, {
+ 13000, 2, 1, 6, 0xb, 0x483483}, {
+ 14400, 3, 1, 10, 0xa, 0x1C71C7}, {
+ 15360, 4, 1, 5, 0xb, 0x755555}, {
+ 16200, 5, 1, 10, 0x5, 0x6E9E06}, {
+ 16800, 6, 1, 10, 0x5, 0x3Cf3Cf}, {
+ 19200, 7, 1, 4, 0xb, 0x755555}, {
+ 19800, 8, 1, 11, 0x4, 0xA57EB}, {
+ 20000, 9, 1, 11, 0x4, 0x0}, {
+ 24000, 10, 3, 11, 0xa, 0x0}, {
+ 25000, 11, 5, 16, 0xb, 0x0}, {
+ 26000, 12, 1, 2, 0x10, 0xEC4EC4}, {
+ 30000, 13, 3, 8, 0xb, 0x0}, {
+ 33600, 14, 1, 2, 0xd, 0x186186}, {
+ 38400, 15, 1, 2, 0xb, 0x755555}, {
+ 40000, 16, 1, 2, 0xb, 0}, {
+ 0, 0, 0, 0, 0, 0}
+};
+
+/* true if the power topology uses the buck boost to provide 3.3V to VDDIO_RF and WLAN PA */
+static bool si_pmu_res_depfltr_bb(si_t *sih)
+{
+ return (sih->boardflags & BFL_BUCKBOOST) != 0;
+}
+
+/* true if the power topology doesn't use the cbuck. Key on chiprev also if the chip is BCM4325. */
+static bool si_pmu_res_depfltr_ncb(si_t *sih)
+{
+
+ return (sih->boardflags & BFL_NOCBUCK) != 0;
+}
+
+/* true if the power topology uses the PALDO */
+static bool si_pmu_res_depfltr_paldo(si_t *sih)
+{
+ return (sih->boardflags & BFL_PALDO) != 0;
+}
+
+/* true if the power topology doesn't use the PALDO */
+static bool si_pmu_res_depfltr_npaldo(si_t *sih)
+{
+ return (sih->boardflags & BFL_PALDO) == 0;
+}
+
+/* Return dependancies (direct or all/indirect) for the given resources */
+static u32
+si_pmu_res_deps(si_t *sih, chipcregs_t *cc, u32 rsrcs,
+ bool all)
+{
+ u32 deps = 0;
+ u32 i;
+
+ for (i = 0; i <= PMURES_MAX_RESNUM; i++) {
+ if (!(rsrcs & PMURES_BIT(i)))
+ continue;
+ W_REG(&cc->res_table_sel, i);
+ deps |= R_REG(&cc->res_dep_mask);
+ }
+
+ return !all ? deps : (deps
+ ? (deps |
+ si_pmu_res_deps(sih, cc, deps,
+ true)) : 0);
+}
+
+/* Determine min/max rsrc masks. Value 0 leaves hardware at default. */
+static void si_pmu_res_masks(si_t *sih, u32 * pmin, u32 * pmax)
+{
+ u32 min_mask = 0, max_mask = 0;
+ uint rsrcs;
+ char *val;
+
+ /* # resources */
+ rsrcs = (sih->pmucaps & PCAP_RC_MASK) >> PCAP_RC_SHIFT;
+
+ /* determine min/max rsrc masks */
+ switch (sih->chip) {
+ case BCM43224_CHIP_ID:
+ case BCM43225_CHIP_ID:
+ case BCM43421_CHIP_ID:
+ case BCM43235_CHIP_ID:
+ case BCM43236_CHIP_ID:
+ case BCM43238_CHIP_ID:
+ case BCM4331_CHIP_ID:
+ case BCM6362_CHIP_ID:
+ /* ??? */
+ break;
+
+ case BCM4329_CHIP_ID:
+ /* 4329 spedific issue. Needs to come back this issue later */
+ /* Down to save the power. */
+ min_mask =
+ PMURES_BIT(RES4329_CBUCK_LPOM) |
+ PMURES_BIT(RES4329_CLDO_PU);
+ /* Allow (but don't require) PLL to turn on */
+ max_mask = 0x3ff63e;
+ break;
+ case BCM4319_CHIP_ID:
+ /* We only need a few resources to be kept on all the time */
+ min_mask = PMURES_BIT(RES4319_CBUCK_LPOM) |
+ PMURES_BIT(RES4319_CLDO_PU);
+
+ /* Allow everything else to be turned on upon requests */
+ max_mask = ~(~0 << rsrcs);
+ break;
+ case BCM4336_CHIP_ID:
+ /* Down to save the power. */
+ min_mask =
+ PMURES_BIT(RES4336_CBUCK_LPOM) | PMURES_BIT(RES4336_CLDO_PU)
+ | PMURES_BIT(RES4336_LDO3P3_PU) | PMURES_BIT(RES4336_OTP_PU)
+ | PMURES_BIT(RES4336_DIS_INT_RESET_PD);
+ /* Allow (but don't require) PLL to turn on */
+ max_mask = 0x1ffffff;
+ break;
+
+ case BCM4330_CHIP_ID:
+ /* Down to save the power. */
+ min_mask =
+ PMURES_BIT(RES4330_CBUCK_LPOM) | PMURES_BIT(RES4330_CLDO_PU)
+ | PMURES_BIT(RES4330_DIS_INT_RESET_PD) |
+ PMURES_BIT(RES4330_LDO3P3_PU) | PMURES_BIT(RES4330_OTP_PU);
+ /* Allow (but don't require) PLL to turn on */
+ max_mask = 0xfffffff;
+ break;
+
+ case BCM4313_CHIP_ID:
+ min_mask = PMURES_BIT(RES4313_BB_PU_RSRC) |
+ PMURES_BIT(RES4313_XTAL_PU_RSRC) |
+ PMURES_BIT(RES4313_ALP_AVAIL_RSRC) |
+ PMURES_BIT(RES4313_BB_PLL_PWRSW_RSRC);
+ max_mask = 0xffff;
+ break;
+ default:
+ break;
+ }
+
+ /* Apply nvram override to min mask */
+ val = getvar(NULL, "rmin");
+ if (val != NULL) {
+ min_mask = (u32) simple_strtoul(val, NULL, 0);
+ }
+ /* Apply nvram override to max mask */
+ val = getvar(NULL, "rmax");
+ if (val != NULL) {
+ max_mask = (u32) simple_strtoul(val, NULL, 0);
+ }
+
+ *pmin = min_mask;
+ *pmax = max_mask;
+}
+
+/* Return up time in ILP cycles for the given resource. */
+static uint
+si_pmu_res_uptime(si_t *sih, chipcregs_t *cc, u8 rsrc) {
+ u32 deps;
+ uint up, i, dup, dmax;
+ u32 min_mask = 0, max_mask = 0;
+
+ /* uptime of resource 'rsrc' */
+ W_REG(&cc->res_table_sel, rsrc);
+ up = (R_REG(&cc->res_updn_timer) >> 8) & 0xff;
+
+ /* direct dependancies of resource 'rsrc' */
+ deps = si_pmu_res_deps(sih, cc, PMURES_BIT(rsrc), false);
+ for (i = 0; i <= PMURES_MAX_RESNUM; i++) {
+ if (!(deps & PMURES_BIT(i)))
+ continue;
+ deps &= ~si_pmu_res_deps(sih, cc, PMURES_BIT(i), true);
+ }
+ si_pmu_res_masks(sih, &min_mask, &max_mask);
+ deps &= ~min_mask;
+
+ /* max uptime of direct dependancies */
+ dmax = 0;
+ for (i = 0; i <= PMURES_MAX_RESNUM; i++) {
+ if (!(deps & PMURES_BIT(i)))
+ continue;
+ dup = si_pmu_res_uptime(sih, cc, (u8) i);
+ if (dmax < dup)
+ dmax = dup;
+ }
+
+ return up + dmax + PMURES_UP_TRANSITION;
+}
+
+static void
+si_pmu_spuravoid_pllupdate(si_t *sih, chipcregs_t *cc, u8 spuravoid)
+{
+ u32 tmp = 0;
+ u8 phypll_offset = 0;
+ u8 bcm5357_bcm43236_p1div[] = { 0x1, 0x5, 0x5 };
+ u8 bcm5357_bcm43236_ndiv[] = { 0x30, 0xf6, 0xfc };
+
+ switch (sih->chip) {
+ case BCM5357_CHIP_ID:
+ case BCM43235_CHIP_ID:
+ case BCM43236_CHIP_ID:
+ case BCM43238_CHIP_ID:
+
+ /*
+ * BCM5357 needs to touch PLL1_PLLCTL[02],
+ * so offset PLL0_PLLCTL[02] by 6
+ */
+ phypll_offset = (sih->chip == BCM5357_CHIP_ID) ? 6 : 0;
+
+ /* RMW only the P1 divider */
+ W_REG(&cc->pllcontrol_addr,
+ PMU1_PLL0_PLLCTL0 + phypll_offset);
+ tmp = R_REG(&cc->pllcontrol_data);
+ tmp &= (~(PMU1_PLL0_PC0_P1DIV_MASK));
+ tmp |=
+ (bcm5357_bcm43236_p1div[spuravoid] <<
+ PMU1_PLL0_PC0_P1DIV_SHIFT);
+ W_REG(&cc->pllcontrol_data, tmp);
+
+ /* RMW only the int feedback divider */
+ W_REG(&cc->pllcontrol_addr,
+ PMU1_PLL0_PLLCTL2 + phypll_offset);
+ tmp = R_REG(&cc->pllcontrol_data);
+ tmp &= ~(PMU1_PLL0_PC2_NDIV_INT_MASK);
+ tmp |=
+ (bcm5357_bcm43236_ndiv[spuravoid]) <<
+ PMU1_PLL0_PC2_NDIV_INT_SHIFT;
+ W_REG(&cc->pllcontrol_data, tmp);
+
+ tmp = 1 << 10;
+ break;
+
+ case BCM4331_CHIP_ID:
+ if (spuravoid == 2) {
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
+ W_REG(&cc->pllcontrol_data, 0x11500014);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
+ W_REG(&cc->pllcontrol_data, 0x0FC00a08);
+ } else if (spuravoid == 1) {
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
+ W_REG(&cc->pllcontrol_data, 0x11500014);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
+ W_REG(&cc->pllcontrol_data, 0x0F600a08);
+ } else {
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
+ W_REG(&cc->pllcontrol_data, 0x11100014);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
+ W_REG(&cc->pllcontrol_data, 0x03000a08);
+ }
+ tmp = 1 << 10;
+ break;
+
+ case BCM43224_CHIP_ID:
+ case BCM43225_CHIP_ID:
+ case BCM43421_CHIP_ID:
+ case BCM6362_CHIP_ID:
+ if (spuravoid == 1) {
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
+ W_REG(&cc->pllcontrol_data, 0x11500010);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
+ W_REG(&cc->pllcontrol_data, 0x000C0C06);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
+ W_REG(&cc->pllcontrol_data, 0x0F600a08);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
+ W_REG(&cc->pllcontrol_data, 0x00000000);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
+ W_REG(&cc->pllcontrol_data, 0x2001E920);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
+ W_REG(&cc->pllcontrol_data, 0x88888815);
+ } else {
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
+ W_REG(&cc->pllcontrol_data, 0x11100010);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
+ W_REG(&cc->pllcontrol_data, 0x000c0c06);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
+ W_REG(&cc->pllcontrol_data, 0x03000a08);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
+ W_REG(&cc->pllcontrol_data, 0x00000000);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
+ W_REG(&cc->pllcontrol_data, 0x200005c0);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
+ W_REG(&cc->pllcontrol_data, 0x88888815);
+ }
+ tmp = 1 << 10;
+ break;
+
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
+ W_REG(&cc->pllcontrol_data, 0x11100008);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
+ W_REG(&cc->pllcontrol_data, 0x0c000c06);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
+ W_REG(&cc->pllcontrol_data, 0x03000a08);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
+ W_REG(&cc->pllcontrol_data, 0x00000000);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
+ W_REG(&cc->pllcontrol_data, 0x200005c0);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
+ W_REG(&cc->pllcontrol_data, 0x88888855);
+
+ tmp = 1 << 10;
+ break;
+
+ case BCM4716_CHIP_ID:
+ case BCM4748_CHIP_ID:
+ case BCM47162_CHIP_ID:
+ if (spuravoid == 1) {
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
+ W_REG(&cc->pllcontrol_data, 0x11500060);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
+ W_REG(&cc->pllcontrol_data, 0x080C0C06);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
+ W_REG(&cc->pllcontrol_data, 0x0F600000);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
+ W_REG(&cc->pllcontrol_data, 0x00000000);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
+ W_REG(&cc->pllcontrol_data, 0x2001E924);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
+ W_REG(&cc->pllcontrol_data, 0x88888815);
+ } else {
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
+ W_REG(&cc->pllcontrol_data, 0x11100060);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
+ W_REG(&cc->pllcontrol_data, 0x080c0c06);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
+ W_REG(&cc->pllcontrol_data, 0x03000000);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
+ W_REG(&cc->pllcontrol_data, 0x00000000);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
+ W_REG(&cc->pllcontrol_data, 0x200005c0);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
+ W_REG(&cc->pllcontrol_data, 0x88888815);
+ }
+
+ tmp = 3 << 9;
+ break;
+
+ case BCM4319_CHIP_ID:
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
+ W_REG(&cc->pllcontrol_data, 0x11100070);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
+ W_REG(&cc->pllcontrol_data, 0x1014140a);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
+ W_REG(&cc->pllcontrol_data, 0x88888854);
+
+ if (spuravoid == 1) {
+ /* spur_avoid ON, so enable 41/82/164Mhz clock mode */
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
+ W_REG(&cc->pllcontrol_data, 0x05201828);
+ } else {
+ /* enable 40/80/160Mhz clock mode */
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
+ W_REG(&cc->pllcontrol_data, 0x05001828);
+ }
+ break;
+ case BCM4336_CHIP_ID:
+ /* Looks like these are only for default xtal freq 26MHz */
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
+ W_REG(&cc->pllcontrol_data, 0x02100020);
+
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
+ W_REG(&cc->pllcontrol_data, 0x0C0C0C0C);
+
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
+ W_REG(&cc->pllcontrol_data, 0x01240C0C);
+
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
+ W_REG(&cc->pllcontrol_data, 0x202C2820);
+
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
+ W_REG(&cc->pllcontrol_data, 0x88888825);
+
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
+ if (spuravoid == 1)
+ W_REG(&cc->pllcontrol_data, 0x00EC4EC4);
+ else
+ W_REG(&cc->pllcontrol_data, 0x00762762);
+
+ tmp = PCTL_PLL_PLLCTL_UPD;
+ break;
+
+ default:
+ /* bail out */
+ return;
+ }
+
+ tmp |= R_REG(&cc->pmucontrol);
+ W_REG(&cc->pmucontrol, tmp);
+}
+
+/* select default xtal frequency for each chip */
+static const pmu1_xtaltab0_t *si_pmu1_xtaldef0(si_t *sih)
+{
+ switch (sih->chip) {
+ case BCM4329_CHIP_ID:
+ /* Default to 38400Khz */
+ return &pmu1_xtaltab0_880_4329[PMU1_XTALTAB0_880_38400K];
+ case BCM4319_CHIP_ID:
+ /* Default to 30000Khz */
+ return &pmu1_xtaltab0_1440[PMU1_XTALTAB0_1440_30000K];
+ case BCM4336_CHIP_ID:
+ /* Default to 26000Khz */
+ return &pmu1_xtaltab0_960[PMU1_XTALTAB0_960_26000K];
+ case BCM4330_CHIP_ID:
+ /* Default to 37400Khz */
+ if (CST4330_CHIPMODE_SDIOD(sih->chipst))
+ return &pmu1_xtaltab0_960[PMU1_XTALTAB0_960_37400K];
+ else
+ return &pmu1_xtaltab0_1440[PMU1_XTALTAB0_1440_37400K];
+ default:
+ break;
+ }
+ return NULL;
+}
+
+/* select xtal table for each chip */
+static const pmu1_xtaltab0_t *si_pmu1_xtaltab0(si_t *sih)
+{
+ switch (sih->chip) {
+ case BCM4329_CHIP_ID:
+ return pmu1_xtaltab0_880_4329;
+ case BCM4319_CHIP_ID:
+ return pmu1_xtaltab0_1440;
+ case BCM4336_CHIP_ID:
+ return pmu1_xtaltab0_960;
+ case BCM4330_CHIP_ID:
+ if (CST4330_CHIPMODE_SDIOD(sih->chipst))
+ return pmu1_xtaltab0_960;
+ else
+ return pmu1_xtaltab0_1440;
+ default:
+ break;
+ }
+ return NULL;
+}
+
+/* query alp/xtal clock frequency */
+static u32
+si_pmu1_alpclk0(si_t *sih, chipcregs_t *cc)
+{
+ const pmu1_xtaltab0_t *xt;
+ u32 xf;
+
+ /* Find the frequency in the table */
+ xf = (R_REG(&cc->pmucontrol) & PCTL_XTALFREQ_MASK) >>
+ PCTL_XTALFREQ_SHIFT;
+ for (xt = si_pmu1_xtaltab0(sih); xt != NULL && xt->fref != 0; xt++)
+ if (xt->xf == xf)
+ break;
+ /* Could not find it so assign a default value */
+ if (xt == NULL || xt->fref == 0)
+ xt = si_pmu1_xtaldef0(sih);
+ return xt->fref * 1000;
+}
+
+/* select default pll fvco for each chip */
+static u32 si_pmu1_pllfvco0(si_t *sih)
+{
+ switch (sih->chip) {
+ case BCM4329_CHIP_ID:
+ return FVCO_880;
+ case BCM4319_CHIP_ID:
+ return FVCO_1440;
+ case BCM4336_CHIP_ID:
+ return FVCO_960;
+ case BCM4330_CHIP_ID:
+ if (CST4330_CHIPMODE_SDIOD(sih->chipst))
+ return FVCO_960;
+ else
+ return FVCO_1440;
+ default:
+ break;
+ }
+ return 0;
+}
+
+static void si_pmu_set_4330_plldivs(si_t *sih)
+{
+ u32 FVCO = si_pmu1_pllfvco0(sih) / 1000;
+ u32 m1div, m2div, m3div, m4div, m5div, m6div;
+ u32 pllc1, pllc2;
+
+ m2div = m3div = m4div = m6div = FVCO / 80;
+ m5div = FVCO / 160;
+
+ if (CST4330_CHIPMODE_SDIOD(sih->chipst))
+ m1div = FVCO / 80;
+ else
+ m1div = FVCO / 90;
+ pllc1 =
+ (m1div << PMU1_PLL0_PC1_M1DIV_SHIFT) | (m2div <<
+ PMU1_PLL0_PC1_M2DIV_SHIFT) |
+ (m3div << PMU1_PLL0_PC1_M3DIV_SHIFT) | (m4div <<
+ PMU1_PLL0_PC1_M4DIV_SHIFT);
+ si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL1, ~0, pllc1);
+
+ pllc2 = si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL1, 0, 0);
+ pllc2 &= ~(PMU1_PLL0_PC2_M5DIV_MASK | PMU1_PLL0_PC2_M6DIV_MASK);
+ pllc2 |=
+ ((m5div << PMU1_PLL0_PC2_M5DIV_SHIFT) |
+ (m6div << PMU1_PLL0_PC2_M6DIV_SHIFT));
+ si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL2, ~0, pllc2);
+}
+
+/* Set up PLL registers in the PMU as per the crystal speed.
+ * XtalFreq field in pmucontrol register being 0 indicates the PLL
+ * is not programmed and the h/w default is assumed to work, in which
+ * case the xtal frequency is unknown to the s/w so we need to call
+ * si_pmu1_xtaldef0() wherever it is needed to return a default value.
+ */
+static void si_pmu1_pllinit0(si_t *sih, chipcregs_t *cc, u32 xtal)
+{
+ const pmu1_xtaltab0_t *xt;
+ u32 tmp;
+ u32 buf_strength = 0;
+ u8 ndiv_mode = 1;
+
+ /* Use h/w default PLL config */
+ if (xtal == 0) {
+ return;
+ }
+
+ /* Find the frequency in the table */
+ for (xt = si_pmu1_xtaltab0(sih); xt != NULL && xt->fref != 0; xt++)
+ if (xt->fref == xtal)
+ break;
+
+ /* Check current PLL state, bail out if it has been programmed or
+ * we don't know how to program it.
+ */
+ if (xt == NULL || xt->fref == 0) {
+ return;
+ }
+ /* for 4319 bootloader already programs the PLL but bootloader does not
+ * program the PLL4 and PLL5. So Skip this check for 4319
+ */
+ if ((((R_REG(&cc->pmucontrol) & PCTL_XTALFREQ_MASK) >>
+ PCTL_XTALFREQ_SHIFT) == xt->xf) &&
+ !((sih->chip == BCM4319_CHIP_ID)
+ || (sih->chip == BCM4330_CHIP_ID)))
+ return;
+
+ switch (sih->chip) {
+ case BCM4329_CHIP_ID:
+ /* Change the BBPLL drive strength to 8 for all channels */
+ buf_strength = 0x888888;
+ AND_REG(&cc->min_res_mask,
+ ~(PMURES_BIT(RES4329_BBPLL_PWRSW_PU) |
+ PMURES_BIT(RES4329_HT_AVAIL)));
+ AND_REG(&cc->max_res_mask,
+ ~(PMURES_BIT(RES4329_BBPLL_PWRSW_PU) |
+ PMURES_BIT(RES4329_HT_AVAIL)));
+ SPINWAIT(R_REG(&cc->clk_ctl_st) & CCS_HTAVAIL,
+ PMU_MAX_TRANSITION_DLY);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
+ if (xt->fref == 38400)
+ tmp = 0x200024C0;
+ else if (xt->fref == 37400)
+ tmp = 0x20004500;
+ else if (xt->fref == 26000)
+ tmp = 0x200024C0;
+ else
+ tmp = 0x200005C0; /* Chip Dflt Settings */
+ W_REG(&cc->pllcontrol_data, tmp);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
+ tmp =
+ R_REG(&cc->pllcontrol_data) & PMU1_PLL0_PC5_CLK_DRV_MASK;
+ if ((xt->fref == 38400) || (xt->fref == 37400)
+ || (xt->fref == 26000))
+ tmp |= 0x15;
+ else
+ tmp |= 0x25; /* Chip Dflt Settings */
+ W_REG(&cc->pllcontrol_data, tmp);
+ break;
+
+ case BCM4319_CHIP_ID:
+ /* Change the BBPLL drive strength to 2 for all channels */
+ buf_strength = 0x222222;
+
+ /* Make sure the PLL is off */
+ /* WAR65104: Disable the HT_AVAIL resource first and then
+ * after a delay (more than downtime for HT_AVAIL) remove the
+ * BBPLL resource; backplane clock moves to ALP from HT.
+ */
+ AND_REG(&cc->min_res_mask,
+ ~(PMURES_BIT(RES4319_HT_AVAIL)));
+ AND_REG(&cc->max_res_mask,
+ ~(PMURES_BIT(RES4319_HT_AVAIL)));
+
+ udelay(100);
+ AND_REG(&cc->min_res_mask,
+ ~(PMURES_BIT(RES4319_BBPLL_PWRSW_PU)));
+ AND_REG(&cc->max_res_mask,
+ ~(PMURES_BIT(RES4319_BBPLL_PWRSW_PU)));
+
+ udelay(100);
+ SPINWAIT(R_REG(&cc->clk_ctl_st) & CCS_HTAVAIL,
+ PMU_MAX_TRANSITION_DLY);
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
+ tmp = 0x200005c0;
+ W_REG(&cc->pllcontrol_data, tmp);
+ break;
+
+ case BCM4336_CHIP_ID:
+ AND_REG(&cc->min_res_mask,
+ ~(PMURES_BIT(RES4336_HT_AVAIL) |
+ PMURES_BIT(RES4336_MACPHY_CLKAVAIL)));
+ AND_REG(&cc->max_res_mask,
+ ~(PMURES_BIT(RES4336_HT_AVAIL) |
+ PMURES_BIT(RES4336_MACPHY_CLKAVAIL)));
+ udelay(100);
+ SPINWAIT(R_REG(&cc->clk_ctl_st) & CCS_HTAVAIL,
+ PMU_MAX_TRANSITION_DLY);
+ break;
+
+ case BCM4330_CHIP_ID:
+ AND_REG(&cc->min_res_mask,
+ ~(PMURES_BIT(RES4330_HT_AVAIL) |
+ PMURES_BIT(RES4330_MACPHY_CLKAVAIL)));
+ AND_REG(&cc->max_res_mask,
+ ~(PMURES_BIT(RES4330_HT_AVAIL) |
+ PMURES_BIT(RES4330_MACPHY_CLKAVAIL)));
+ udelay(100);
+ SPINWAIT(R_REG(&cc->clk_ctl_st) & CCS_HTAVAIL,
+ PMU_MAX_TRANSITION_DLY);
+ break;
+
+ default:
+ break;
+ }
+
+ /* Write p1div and p2div to pllcontrol[0] */
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
+ tmp = R_REG(&cc->pllcontrol_data) &
+ ~(PMU1_PLL0_PC0_P1DIV_MASK | PMU1_PLL0_PC0_P2DIV_MASK);
+ tmp |=
+ ((xt->
+ p1div << PMU1_PLL0_PC0_P1DIV_SHIFT) & PMU1_PLL0_PC0_P1DIV_MASK) |
+ ((xt->
+ p2div << PMU1_PLL0_PC0_P2DIV_SHIFT) & PMU1_PLL0_PC0_P2DIV_MASK);
+ W_REG(&cc->pllcontrol_data, tmp);
+
+ if ((sih->chip == BCM4330_CHIP_ID))
+ si_pmu_set_4330_plldivs(sih);
+
+ if ((sih->chip == BCM4329_CHIP_ID)
+ && (sih->chiprev == 0)) {
+
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
+ tmp = R_REG(&cc->pllcontrol_data);
+ tmp = tmp & (~DOT11MAC_880MHZ_CLK_DIVISOR_MASK);
+ tmp = tmp | DOT11MAC_880MHZ_CLK_DIVISOR_VAL;
+ W_REG(&cc->pllcontrol_data, tmp);
+ }
+ if ((sih->chip == BCM4319_CHIP_ID) ||
+ (sih->chip == BCM4336_CHIP_ID) ||
+ (sih->chip == BCM4330_CHIP_ID))
+ ndiv_mode = PMU1_PLL0_PC2_NDIV_MODE_MFB;
+ else
+ ndiv_mode = PMU1_PLL0_PC2_NDIV_MODE_MASH;
+
+ /* Write ndiv_int and ndiv_mode to pllcontrol[2] */
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
+ tmp = R_REG(&cc->pllcontrol_data) &
+ ~(PMU1_PLL0_PC2_NDIV_INT_MASK | PMU1_PLL0_PC2_NDIV_MODE_MASK);
+ tmp |=
+ ((xt->
+ ndiv_int << PMU1_PLL0_PC2_NDIV_INT_SHIFT) &
+ PMU1_PLL0_PC2_NDIV_INT_MASK) | ((ndiv_mode <<
+ PMU1_PLL0_PC2_NDIV_MODE_SHIFT) &
+ PMU1_PLL0_PC2_NDIV_MODE_MASK);
+ W_REG(&cc->pllcontrol_data, tmp);
+
+ /* Write ndiv_frac to pllcontrol[3] */
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
+ tmp = R_REG(&cc->pllcontrol_data) & ~PMU1_PLL0_PC3_NDIV_FRAC_MASK;
+ tmp |= ((xt->ndiv_frac << PMU1_PLL0_PC3_NDIV_FRAC_SHIFT) &
+ PMU1_PLL0_PC3_NDIV_FRAC_MASK);
+ W_REG(&cc->pllcontrol_data, tmp);
+
+ /* Write clock driving strength to pllcontrol[5] */
+ if (buf_strength) {
+ W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
+ tmp =
+ R_REG(&cc->pllcontrol_data) & ~PMU1_PLL0_PC5_CLK_DRV_MASK;
+ tmp |= (buf_strength << PMU1_PLL0_PC5_CLK_DRV_SHIFT);
+ W_REG(&cc->pllcontrol_data, tmp);
+ }
+
+ /* to operate the 4319 usb in 24MHz/48MHz; chipcontrol[2][84:83] needs
+ * to be updated.
+ */
+ if ((sih->chip == BCM4319_CHIP_ID)
+ && (xt->fref != XTAL_FREQ_30000MHZ)) {
+ W_REG(&cc->chipcontrol_addr, PMU1_PLL0_CHIPCTL2);
+ tmp =
+ R_REG(&cc->chipcontrol_data) & ~CCTL_4319USB_XTAL_SEL_MASK;
+ if (xt->fref == XTAL_FREQ_24000MHZ) {
+ tmp |=
+ (CCTL_4319USB_24MHZ_PLL_SEL <<
+ CCTL_4319USB_XTAL_SEL_SHIFT);
+ } else if (xt->fref == XTAL_FREQ_48000MHZ) {
+ tmp |=
+ (CCTL_4319USB_48MHZ_PLL_SEL <<
+ CCTL_4319USB_XTAL_SEL_SHIFT);
+ }
+ W_REG(&cc->chipcontrol_data, tmp);
+ }
+
+ /* Flush deferred pll control registers writes */
+ if (sih->pmurev >= 2)
+ OR_REG(&cc->pmucontrol, PCTL_PLL_PLLCTL_UPD);
+
+ /* Write XtalFreq. Set the divisor also. */
+ tmp = R_REG(&cc->pmucontrol) &
+ ~(PCTL_ILP_DIV_MASK | PCTL_XTALFREQ_MASK);
+ tmp |= (((((xt->fref + 127) / 128) - 1) << PCTL_ILP_DIV_SHIFT) &
+ PCTL_ILP_DIV_MASK) |
+ ((xt->xf << PCTL_XTALFREQ_SHIFT) & PCTL_XTALFREQ_MASK);
+
+ if ((sih->chip == BCM4329_CHIP_ID)
+ && sih->chiprev == 0) {
+ /* clear the htstretch before clearing HTReqEn */
+ AND_REG(&cc->clkstretch, ~CSTRETCH_HT);
+ tmp &= ~PCTL_HT_REQ_EN;
+ }
+
+ W_REG(&cc->pmucontrol, tmp);
+}
+
+u32 si_pmu_ilp_clock(si_t *sih)
+{
+ static u32 ilpcycles_per_sec;
+
+ if (ISSIM_ENAB(sih) || !PMUCTL_ENAB(sih))
+ return ILP_CLOCK;
+
+ if (ilpcycles_per_sec == 0) {
+ u32 start, end, delta;
+ u32 origidx = ai_coreidx(sih);
+ chipcregs_t *cc = ai_setcoreidx(sih, SI_CC_IDX);
+ start = R_REG(&cc->pmutimer);
+ mdelay(ILP_CALC_DUR);
+ end = R_REG(&cc->pmutimer);
+ delta = end - start;
+ ilpcycles_per_sec = delta * (1000 / ILP_CALC_DUR);
+ ai_setcoreidx(sih, origidx);
+ }
+
+ return ilpcycles_per_sec;
+}
+
+void si_pmu_set_ldo_voltage(si_t *sih, u8 ldo, u8 voltage)
+{
+ u8 sr_cntl_shift = 0, rc_shift = 0, shift = 0, mask = 0;
+ u8 addr = 0;
+
+ switch (sih->chip) {
+ case BCM4336_CHIP_ID:
+ switch (ldo) {
+ case SET_LDO_VOLTAGE_CLDO_PWM:
+ addr = 4;
+ rc_shift = 1;
+ mask = 0xf;
+ break;
+ case SET_LDO_VOLTAGE_CLDO_BURST:
+ addr = 4;
+ rc_shift = 5;
+ mask = 0xf;
+ break;
+ case SET_LDO_VOLTAGE_LNLDO1:
+ addr = 4;
+ rc_shift = 17;
+ mask = 0xf;
+ break;
+ default:
+ return;
+ }
+ break;
+ case BCM4330_CHIP_ID:
+ switch (ldo) {
+ case SET_LDO_VOLTAGE_CBUCK_PWM:
+ addr = 3;
+ rc_shift = 0;
+ mask = 0x1f;
+ break;
+ default:
+ return;
+ }
+ break;
+ default:
+ return;
+ }
+
+ shift = sr_cntl_shift + rc_shift;
+
+ ai_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, regcontrol_addr),
+ ~0, addr);
+ ai_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, regcontrol_data),
+ mask << shift, (voltage & mask) << shift);
+}
+
+u16 si_pmu_fast_pwrup_delay(si_t *sih)
+{
+ uint delay = PMU_MAX_TRANSITION_DLY;
+ chipcregs_t *cc;
+ uint origidx;
+#ifdef BCMDBG
+ char chn[8];
+ chn[0] = 0; /* to suppress compile error */
+#endif
+
+ /* Remember original core before switch to chipc */
+ origidx = ai_coreidx(sih);
+ cc = ai_setcoreidx(sih, SI_CC_IDX);
+
+ switch (sih->chip) {
+ case BCM43224_CHIP_ID:
+ case BCM43225_CHIP_ID:
+ case BCM43421_CHIP_ID:
+ case BCM43235_CHIP_ID:
+ case BCM43236_CHIP_ID:
+ case BCM43238_CHIP_ID:
+ case BCM4331_CHIP_ID:
+ case BCM6362_CHIP_ID:
+ case BCM4313_CHIP_ID:
+ delay = ISSIM_ENAB(sih) ? 70 : 3700;
+ break;
+ case BCM4329_CHIP_ID:
+ if (ISSIM_ENAB(sih))
+ delay = 70;
+ else {
+ u32 ilp = si_pmu_ilp_clock(sih);
+ delay =
+ (si_pmu_res_uptime(sih, cc, RES4329_HT_AVAIL) +
+ D11SCC_SLOW2FAST_TRANSITION) * ((1000000 + ilp -
+ 1) / ilp);
+ delay = (11 * delay) / 10;
+ }
+ break;
+ case BCM4319_CHIP_ID:
+ delay = ISSIM_ENAB(sih) ? 70 : 3700;
+ break;
+ case BCM4336_CHIP_ID:
+ if (ISSIM_ENAB(sih))
+ delay = 70;
+ else {
+ u32 ilp = si_pmu_ilp_clock(sih);
+ delay =
+ (si_pmu_res_uptime(sih, cc, RES4336_HT_AVAIL) +
+ D11SCC_SLOW2FAST_TRANSITION) * ((1000000 + ilp -
+ 1) / ilp);
+ delay = (11 * delay) / 10;
+ }
+ break;
+ case BCM4330_CHIP_ID:
+ if (ISSIM_ENAB(sih))
+ delay = 70;
+ else {
+ u32 ilp = si_pmu_ilp_clock(sih);
+ delay =
+ (si_pmu_res_uptime(sih, cc, RES4330_HT_AVAIL) +
+ D11SCC_SLOW2FAST_TRANSITION) * ((1000000 + ilp -
+ 1) / ilp);
+ delay = (11 * delay) / 10;
+ }
+ break;
+ default:
+ break;
+ }
+ /* Return to original core */
+ ai_setcoreidx(sih, origidx);
+
+ return (u16) delay;
+}
+
+void si_pmu_sprom_enable(si_t *sih, bool enable)
+{
+ chipcregs_t *cc;
+ uint origidx;
+
+ /* Remember original core before switch to chipc */
+ origidx = ai_coreidx(sih);
+ cc = ai_setcoreidx(sih, SI_CC_IDX);
+
+ /* Return to original core */
+ ai_setcoreidx(sih, origidx);
+}
+
+/* Read/write a chipcontrol reg */
+u32 si_pmu_chipcontrol(si_t *sih, uint reg, u32 mask, u32 val)
+{
+ ai_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, chipcontrol_addr), ~0,
+ reg);
+ return ai_corereg(sih, SI_CC_IDX,
+ offsetof(chipcregs_t, chipcontrol_data), mask, val);
+}
+
+/* Read/write a regcontrol reg */
+u32 si_pmu_regcontrol(si_t *sih, uint reg, u32 mask, u32 val)
+{
+ ai_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, regcontrol_addr), ~0,
+ reg);
+ return ai_corereg(sih, SI_CC_IDX,
+ offsetof(chipcregs_t, regcontrol_data), mask, val);
+}
+
+/* Read/write a pllcontrol reg */
+u32 si_pmu_pllcontrol(si_t *sih, uint reg, u32 mask, u32 val)
+{
+ ai_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, pllcontrol_addr), ~0,
+ reg);
+ return ai_corereg(sih, SI_CC_IDX,
+ offsetof(chipcregs_t, pllcontrol_data), mask, val);
+}
+
+/* PMU PLL update */
+void si_pmu_pllupd(si_t *sih)
+{
+ ai_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, pmucontrol),
+ PCTL_PLL_PLLCTL_UPD, PCTL_PLL_PLLCTL_UPD);
+}
+
+/* query alp/xtal clock frequency */
+u32 si_pmu_alp_clock(si_t *sih)
+{
+ chipcregs_t *cc;
+ uint origidx;
+ u32 clock = ALP_CLOCK;
+
+ /* bail out with default */
+ if (!PMUCTL_ENAB(sih))
+ return clock;
+
+ /* Remember original core before switch to chipc */
+ origidx = ai_coreidx(sih);
+ cc = ai_setcoreidx(sih, SI_CC_IDX);
+
+ switch (sih->chip) {
+ case BCM43224_CHIP_ID:
+ case BCM43225_CHIP_ID:
+ case BCM43421_CHIP_ID:
+ case BCM43235_CHIP_ID:
+ case BCM43236_CHIP_ID:
+ case BCM43238_CHIP_ID:
+ case BCM4331_CHIP_ID:
+ case BCM6362_CHIP_ID:
+ case BCM4716_CHIP_ID:
+ case BCM4748_CHIP_ID:
+ case BCM47162_CHIP_ID:
+ case BCM4313_CHIP_ID:
+ case BCM5357_CHIP_ID:
+ /* always 20Mhz */
+ clock = 20000 * 1000;
+ break;
+ case BCM4329_CHIP_ID:
+ case BCM4319_CHIP_ID:
+ case BCM4336_CHIP_ID:
+ case BCM4330_CHIP_ID:
+
+ clock = si_pmu1_alpclk0(sih, cc);
+ break;
+ case BCM5356_CHIP_ID:
+ /* always 25Mhz */
+ clock = 25000 * 1000;
+ break;
+ default:
+ break;
+ }
+
+ /* Return to original core */
+ ai_setcoreidx(sih, origidx);
+ return clock;
+}
+
+void si_pmu_spuravoid(si_t *sih, u8 spuravoid)
+{
+ chipcregs_t *cc;
+ uint origidx, intr_val;
+ u32 tmp = 0;
+
+ /* Remember original core before switch to chipc */
+ cc = (chipcregs_t *) ai_switch_core(sih, CC_CORE_ID, &origidx,
+ &intr_val);
+
+ /* force the HT off */
+ if (sih->chip == BCM4336_CHIP_ID) {
+ tmp = R_REG(&cc->max_res_mask);
+ tmp &= ~RES4336_HT_AVAIL;
+ W_REG(&cc->max_res_mask, tmp);
+ /* wait for the ht to really go away */
+ SPINWAIT(((R_REG(&cc->clk_ctl_st) & CCS_HTAVAIL) == 0),
+ 10000);
+ }
+
+ /* update the pll changes */
+ si_pmu_spuravoid_pllupdate(sih, cc, spuravoid);
+
+ /* enable HT back on */
+ if (sih->chip == BCM4336_CHIP_ID) {
+ tmp = R_REG(&cc->max_res_mask);
+ tmp |= RES4336_HT_AVAIL;
+ W_REG(&cc->max_res_mask, tmp);
+ }
+
+ /* Return to original core */
+ ai_restore_core(sih, origidx, intr_val);
+}
+
+/* initialize PMU */
+void si_pmu_init(si_t *sih)
+{
+ chipcregs_t *cc;
+ uint origidx;
+
+ /* Remember original core before switch to chipc */
+ origidx = ai_coreidx(sih);
+ cc = ai_setcoreidx(sih, SI_CC_IDX);
+
+ if (sih->pmurev == 1)
+ AND_REG(&cc->pmucontrol, ~PCTL_NOILP_ON_WAIT);
+ else if (sih->pmurev >= 2)
+ OR_REG(&cc->pmucontrol, PCTL_NOILP_ON_WAIT);
+
+ if ((sih->chip == BCM4329_CHIP_ID) && (sih->chiprev == 2)) {
+ /* Fix for 4329b0 bad LPOM state. */
+ W_REG(&cc->regcontrol_addr, 2);
+ OR_REG(&cc->regcontrol_data, 0x100);
+
+ W_REG(&cc->regcontrol_addr, 3);
+ OR_REG(&cc->regcontrol_data, 0x4);
+ }
+
+ /* Return to original core */
+ ai_setcoreidx(sih, origidx);
+}
+
+/* initialize PMU chip controls and other chip level stuff */
+void si_pmu_chip_init(si_t *sih)
+{
+ uint origidx;
+
+ /* Gate off SPROM clock and chip select signals */
+ si_pmu_sprom_enable(sih, false);
+
+ /* Remember original core */
+ origidx = ai_coreidx(sih);
+
+ /* Return to original core */
+ ai_setcoreidx(sih, origidx);
+}
+
+/* initialize PMU switch/regulators */
+void si_pmu_swreg_init(si_t *sih)
+{
+ switch (sih->chip) {
+ case BCM4336_CHIP_ID:
+ /* Reduce CLDO PWM output voltage to 1.2V */
+ si_pmu_set_ldo_voltage(sih, SET_LDO_VOLTAGE_CLDO_PWM, 0xe);
+ /* Reduce CLDO BURST output voltage to 1.2V */
+ si_pmu_set_ldo_voltage(sih, SET_LDO_VOLTAGE_CLDO_BURST,
+ 0xe);
+ /* Reduce LNLDO1 output voltage to 1.2V */
+ si_pmu_set_ldo_voltage(sih, SET_LDO_VOLTAGE_LNLDO1, 0xe);
+ if (sih->chiprev == 0)
+ si_pmu_regcontrol(sih, 2, 0x400000, 0x400000);
+ break;
+
+ case BCM4330_CHIP_ID:
+ /* CBUCK Voltage is 1.8 by default and set that to 1.5 */
+ si_pmu_set_ldo_voltage(sih, SET_LDO_VOLTAGE_CBUCK_PWM, 0);
+ break;
+ default:
+ break;
+ }
+}
+
+/* initialize PLL */
+void si_pmu_pll_init(si_t *sih, uint xtalfreq)
+{
+ chipcregs_t *cc;
+ uint origidx;
+
+ /* Remember original core before switch to chipc */
+ origidx = ai_coreidx(sih);
+ cc = ai_setcoreidx(sih, SI_CC_IDX);
+
+ switch (sih->chip) {
+ case BCM4329_CHIP_ID:
+ if (xtalfreq == 0)
+ xtalfreq = 38400;
+ si_pmu1_pllinit0(sih, cc, xtalfreq);
+ break;
+ case BCM4313_CHIP_ID:
+ case BCM43224_CHIP_ID:
+ case BCM43225_CHIP_ID:
+ case BCM43421_CHIP_ID:
+ case BCM43235_CHIP_ID:
+ case BCM43236_CHIP_ID:
+ case BCM43238_CHIP_ID:
+ case BCM4331_CHIP_ID:
+ case BCM6362_CHIP_ID:
+ /* ??? */
+ break;
+ case BCM4319_CHIP_ID:
+ case BCM4336_CHIP_ID:
+ case BCM4330_CHIP_ID:
+ si_pmu1_pllinit0(sih, cc, xtalfreq);
+ break;
+ default:
+ break;
+ }
+
+ /* Return to original core */
+ ai_setcoreidx(sih, origidx);
+}
+
+/* initialize PMU resources */
+void si_pmu_res_init(si_t *sih)
+{
+ chipcregs_t *cc;
+ uint origidx;
+ const pmu_res_updown_t *pmu_res_updown_table = NULL;
+ uint pmu_res_updown_table_sz = 0;
+ const pmu_res_depend_t *pmu_res_depend_table = NULL;
+ uint pmu_res_depend_table_sz = 0;
+ u32 min_mask = 0, max_mask = 0;
+ char name[8], *val;
+ uint i, rsrcs;
+
+ /* Remember original core before switch to chipc */
+ origidx = ai_coreidx(sih);
+ cc = ai_setcoreidx(sih, SI_CC_IDX);
+
+ switch (sih->chip) {
+ case BCM4329_CHIP_ID:
+ /* Optimize resources up/down timers */
+ if (ISSIM_ENAB(sih)) {
+ pmu_res_updown_table = NULL;
+ pmu_res_updown_table_sz = 0;
+ } else {
+ pmu_res_updown_table = bcm4329_res_updown;
+ pmu_res_updown_table_sz =
+ ARRAY_SIZE(bcm4329_res_updown);
+ }
+ /* Optimize resources dependencies */
+ pmu_res_depend_table = bcm4329_res_depend;
+ pmu_res_depend_table_sz = ARRAY_SIZE(bcm4329_res_depend);
+ break;
+
+ case BCM4319_CHIP_ID:
+ /* Optimize resources up/down timers */
+ if (ISSIM_ENAB(sih)) {
+ pmu_res_updown_table = bcm4319a0_res_updown_qt;
+ pmu_res_updown_table_sz =
+ ARRAY_SIZE(bcm4319a0_res_updown_qt);
+ } else {
+ pmu_res_updown_table = bcm4319a0_res_updown;
+ pmu_res_updown_table_sz =
+ ARRAY_SIZE(bcm4319a0_res_updown);
+ }
+ /* Optimize resources dependancies masks */
+ pmu_res_depend_table = bcm4319a0_res_depend;
+ pmu_res_depend_table_sz = ARRAY_SIZE(bcm4319a0_res_depend);
+ break;
+
+ case BCM4336_CHIP_ID:
+ /* Optimize resources up/down timers */
+ if (ISSIM_ENAB(sih)) {
+ pmu_res_updown_table = bcm4336a0_res_updown_qt;
+ pmu_res_updown_table_sz =
+ ARRAY_SIZE(bcm4336a0_res_updown_qt);
+ } else {
+ pmu_res_updown_table = bcm4336a0_res_updown;
+ pmu_res_updown_table_sz =
+ ARRAY_SIZE(bcm4336a0_res_updown);
+ }
+ /* Optimize resources dependancies masks */
+ pmu_res_depend_table = bcm4336a0_res_depend;
+ pmu_res_depend_table_sz = ARRAY_SIZE(bcm4336a0_res_depend);
+ break;
+
+ case BCM4330_CHIP_ID:
+ /* Optimize resources up/down timers */
+ if (ISSIM_ENAB(sih)) {
+ pmu_res_updown_table = bcm4330a0_res_updown_qt;
+ pmu_res_updown_table_sz =
+ ARRAY_SIZE(bcm4330a0_res_updown_qt);
+ } else {
+ pmu_res_updown_table = bcm4330a0_res_updown;
+ pmu_res_updown_table_sz =
+ ARRAY_SIZE(bcm4330a0_res_updown);
+ }
+ /* Optimize resources dependancies masks */
+ pmu_res_depend_table = bcm4330a0_res_depend;
+ pmu_res_depend_table_sz = ARRAY_SIZE(bcm4330a0_res_depend);
+ break;
+
+ default:
+ break;
+ }
+
+ /* # resources */
+ rsrcs = (sih->pmucaps & PCAP_RC_MASK) >> PCAP_RC_SHIFT;
+
+ /* Program up/down timers */
+ while (pmu_res_updown_table_sz--) {
+ W_REG(&cc->res_table_sel,
+ pmu_res_updown_table[pmu_res_updown_table_sz].resnum);
+ W_REG(&cc->res_updn_timer,
+ pmu_res_updown_table[pmu_res_updown_table_sz].updown);
+ }
+ /* Apply nvram overrides to up/down timers */
+ for (i = 0; i < rsrcs; i++) {
+ snprintf(name, sizeof(name), "r%dt", i);
+ val = getvar(NULL, name);
+ if (val == NULL)
+ continue;
+ W_REG(&cc->res_table_sel, (u32) i);
+ W_REG(&cc->res_updn_timer,
+ (u32) simple_strtoul(val, NULL, 0));
+ }
+
+ /* Program resource dependencies table */
+ while (pmu_res_depend_table_sz--) {
+ if (pmu_res_depend_table[pmu_res_depend_table_sz].filter != NULL
+ && !(pmu_res_depend_table[pmu_res_depend_table_sz].
+ filter) (sih))
+ continue;
+ for (i = 0; i < rsrcs; i++) {
+ if ((pmu_res_depend_table[pmu_res_depend_table_sz].
+ res_mask & PMURES_BIT(i)) == 0)
+ continue;
+ W_REG(&cc->res_table_sel, i);
+ switch (pmu_res_depend_table[pmu_res_depend_table_sz].
+ action) {
+ case RES_DEPEND_SET:
+ W_REG(&cc->res_dep_mask,
+ pmu_res_depend_table
+ [pmu_res_depend_table_sz].depend_mask);
+ break;
+ case RES_DEPEND_ADD:
+ OR_REG(&cc->res_dep_mask,
+ pmu_res_depend_table
+ [pmu_res_depend_table_sz].depend_mask);
+ break;
+ case RES_DEPEND_REMOVE:
+ AND_REG(&cc->res_dep_mask,
+ ~pmu_res_depend_table
+ [pmu_res_depend_table_sz].depend_mask);
+ break;
+ default:
+ break;
+ }
+ }
+ }
+ /* Apply nvram overrides to dependancies masks */
+ for (i = 0; i < rsrcs; i++) {
+ snprintf(name, sizeof(name), "r%dd", i);
+ val = getvar(NULL, name);
+ if (val == NULL)
+ continue;
+ W_REG(&cc->res_table_sel, (u32) i);
+ W_REG(&cc->res_dep_mask,
+ (u32) simple_strtoul(val, NULL, 0));
+ }
+
+ /* Determine min/max rsrc masks */
+ si_pmu_res_masks(sih, &min_mask, &max_mask);
+
+ /* It is required to program max_mask first and then min_mask */
+
+ /* Program max resource mask */
+
+ if (max_mask)
+ W_REG(&cc->max_res_mask, max_mask);
+
+ /* Program min resource mask */
+
+ if (min_mask)
+ W_REG(&cc->min_res_mask, min_mask);
+
+ /* Add some delay; allow resources to come up and settle. */
+ mdelay(2);
+
+ /* Return to original core */
+ ai_setcoreidx(sih, origidx);
+}
+
+u32 si_pmu_measure_alpclk(si_t *sih)
+{
+ chipcregs_t *cc;
+ uint origidx;
+ u32 alp_khz;
+
+ if (sih->pmurev < 10)
+ return 0;
+
+ /* Remember original core before switch to chipc */
+ origidx = ai_coreidx(sih);
+ cc = ai_setcoreidx(sih, SI_CC_IDX);
+
+ if (R_REG(&cc->pmustatus) & PST_EXTLPOAVAIL) {
+ u32 ilp_ctr, alp_hz;
+
+ /*
+ * Enable the reg to measure the freq,
+ * in case it was disabled before
+ */
+ W_REG(&cc->pmu_xtalfreq,
+ 1U << PMU_XTALFREQ_REG_MEASURE_SHIFT);
+
+ /* Delay for well over 4 ILP clocks */
+ udelay(1000);
+
+ /* Read the latched number of ALP ticks per 4 ILP ticks */
+ ilp_ctr =
+ R_REG(&cc->pmu_xtalfreq) & PMU_XTALFREQ_REG_ILPCTR_MASK;
+
+ /*
+ * Turn off the PMU_XTALFREQ_REG_MEASURE_SHIFT
+ * bit to save power
+ */
+ W_REG(&cc->pmu_xtalfreq, 0);
+
+ /* Calculate ALP frequency */
+ alp_hz = (ilp_ctr * EXT_ILP_HZ) / 4;
+
+ /*
+ * Round to nearest 100KHz, and at
+ * the same time convert to KHz
+ */
+ alp_khz = (alp_hz + 50000) / 100000 * 100;
+ } else
+ alp_khz = 0;
+
+ /* Return to original core */
+ ai_setcoreidx(sih, origidx);
+
+ return alp_khz;
+}
+
+bool si_pmu_is_otp_powered(si_t *sih)
+{
+ uint idx;
+ chipcregs_t *cc;
+ bool st;
+
+ /* Remember original core before switch to chipc */
+ idx = ai_coreidx(sih);
+ cc = ai_setcoreidx(sih, SI_CC_IDX);
+
+ switch (sih->chip) {
+ case BCM4329_CHIP_ID:
+ st = (R_REG(&cc->res_state) & PMURES_BIT(RES4329_OTP_PU))
+ != 0;
+ break;
+ case BCM4319_CHIP_ID:
+ st = (R_REG(&cc->res_state) & PMURES_BIT(RES4319_OTP_PU))
+ != 0;
+ break;
+ case BCM4336_CHIP_ID:
+ st = (R_REG(&cc->res_state) & PMURES_BIT(RES4336_OTP_PU))
+ != 0;
+ break;
+ case BCM4330_CHIP_ID:
+ st = (R_REG(&cc->res_state) & PMURES_BIT(RES4330_OTP_PU))
+ != 0;
+ break;
+
+ /* These chip doesn't use PMU bit to power up/down OTP. OTP always on.
+ * Use OTP_INIT command to reset/refresh state.
+ */
+ case BCM43224_CHIP_ID:
+ case BCM43225_CHIP_ID:
+ case BCM43421_CHIP_ID:
+ case BCM43236_CHIP_ID:
+ case BCM43235_CHIP_ID:
+ case BCM43238_CHIP_ID:
+ st = true;
+ break;
+ default:
+ st = true;
+ break;
+ }
+
+ /* Return to original core */
+ ai_setcoreidx(sih, idx);
+ return st;
+}
+
+/* power up/down OTP through PMU resources */
+void si_pmu_otp_power(si_t *sih, bool on)
+{
+ chipcregs_t *cc;
+ uint origidx;
+ u32 rsrcs = 0; /* rsrcs to turn on/off OTP power */
+
+ /* Don't do anything if OTP is disabled */
+ if (ai_is_otp_disabled(sih))
+ return;
+
+ /* Remember original core before switch to chipc */
+ origidx = ai_coreidx(sih);
+ cc = ai_setcoreidx(sih, SI_CC_IDX);
+
+ switch (sih->chip) {
+ case BCM4329_CHIP_ID:
+ rsrcs = PMURES_BIT(RES4329_OTP_PU);
+ break;
+ case BCM4319_CHIP_ID:
+ rsrcs = PMURES_BIT(RES4319_OTP_PU);
+ break;
+ case BCM4336_CHIP_ID:
+ rsrcs = PMURES_BIT(RES4336_OTP_PU);
+ break;
+ case BCM4330_CHIP_ID:
+ rsrcs = PMURES_BIT(RES4330_OTP_PU);
+ break;
+ default:
+ break;
+ }
+
+ if (rsrcs != 0) {
+ u32 otps;
+
+ /* Figure out the dependancies (exclude min_res_mask) */
+ u32 deps = si_pmu_res_deps(sih, cc, rsrcs, true);
+ u32 min_mask = 0, max_mask = 0;
+ si_pmu_res_masks(sih, &min_mask, &max_mask);
+ deps &= ~min_mask;
+ /* Turn on/off the power */
+ if (on) {
+ OR_REG(&cc->min_res_mask, (rsrcs | deps));
+ SPINWAIT(!(R_REG(&cc->res_state) & rsrcs),
+ PMU_MAX_TRANSITION_DLY);
+ } else {
+ AND_REG(&cc->min_res_mask, ~(rsrcs | deps));
+ }
+
+ SPINWAIT((((otps = R_REG(&cc->otpstatus)) & OTPS_READY) !=
+ (on ? OTPS_READY : 0)), 100);
+ }
+
+ /* Return to original core */
+ ai_setcoreidx(sih, origidx);
+}
diff --git a/drivers/staging/brcm80211/brcmsmac/wlc_pmu.h b/drivers/staging/brcm80211/brcmsmac/wlc_pmu.h
new file mode 100644
index 0000000..bd5b809b
--- /dev/null
+++ b/drivers/staging/brcm80211/brcmsmac/wlc_pmu.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2010 Broadcom Corporation
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+ * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+ * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+ * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ */
+
+
+#ifndef WLC_PMU_H_
+#define WLC_PMU_H_
+
+#include <linux/types.h>
+
+#include <aiutils.h>
+
+/*
+ * LDO selections used in si_pmu_set_ldo_voltage
+ */
+#define SET_LDO_VOLTAGE_LDO1 1
+#define SET_LDO_VOLTAGE_LDO2 2
+#define SET_LDO_VOLTAGE_LDO3 3
+#define SET_LDO_VOLTAGE_PAREF 4
+#define SET_LDO_VOLTAGE_CLDO_PWM 5
+#define SET_LDO_VOLTAGE_CLDO_BURST 6
+#define SET_LDO_VOLTAGE_CBUCK_PWM 7
+#define SET_LDO_VOLTAGE_CBUCK_BURST 8
+#define SET_LDO_VOLTAGE_LNLDO1 9
+#define SET_LDO_VOLTAGE_LNLDO2_SEL 10
+
+extern void si_pmu_set_ldo_voltage(si_t *sih, u8 ldo, u8 voltage);
+extern u16 si_pmu_fast_pwrup_delay(si_t *sih);
+extern void si_pmu_sprom_enable(si_t *sih, bool enable);
+extern u32 si_pmu_chipcontrol(si_t *sih, uint reg, u32 mask, u32 val);
+extern u32 si_pmu_regcontrol(si_t *sih, uint reg, u32 mask, u32 val);
+extern u32 si_pmu_ilp_clock(si_t *sih);
+extern u32 si_pmu_alp_clock(si_t *sih);
+extern void si_pmu_pllupd(si_t *sih);
+extern void si_pmu_spuravoid(si_t *sih, u8 spuravoid);
+extern u32 si_pmu_pllcontrol(si_t *sih, uint reg, u32 mask, u32 val);
+extern void si_pmu_init(si_t *sih);
+extern void si_pmu_chip_init(si_t *sih);
+extern void si_pmu_pll_init(si_t *sih, u32 xtalfreq);
+extern void si_pmu_res_init(si_t *sih);
+extern void si_pmu_swreg_init(si_t *sih);
+extern u32 si_pmu_measure_alpclk(si_t *sih);
+extern bool si_pmu_is_otp_powered(si_t *sih);
+extern void si_pmu_otp_power(si_t *sih, bool on);
+
+#endif /* WLC_PMU_H_ */
diff --git a/drivers/staging/brcm80211/brcmsmac/wlc_pub.h b/drivers/staging/brcm80211/brcmsmac/wlc_pub.h
index b956c23..9334dea 100644
--- a/drivers/staging/brcm80211/brcmsmac/wlc_pub.h
+++ b/drivers/staging/brcm80211/brcmsmac/wlc_pub.h
@@ -59,6 +59,10 @@
*/
#define WLC_TXPWR_MAX (127) /* ~32 dBm = 1,500 mW */
+/* rate related definitions */
+#define WLC_RATE_FLAG 0x80 /* Flag to indicate it is a basic rate */
+#define WLC_RATE_MASK 0x7f /* Rate value mask w/o basic rate flag */
+
/* legacy rx Antenna diversity for SISO rates */
#define ANT_RX_DIV_FORCE_0 0 /* Use antenna 0 */
#define ANT_RX_DIV_FORCE_1 1 /* Use antenna 1 */
@@ -92,6 +96,8 @@
#define AIDMAPSZ (roundup(MAXSCB, NBBY)/NBBY) /* aid bitmap size in bytes */
#endif /* AIDMAPSZ */
+struct ieee80211_tx_queue_params;
+
typedef struct wlc_tunables {
int ntxd; /* size of tx descriptor table */
int nrxd; /* size of rx descriptor table */
@@ -478,7 +484,7 @@
#define WLC_PROT_N_OBSS 16 /* non-HT OBSS present */
/* common functions for every port */
-extern void *wlc_attach(void *wl, u16 vendor, u16 device, uint unit,
+extern void *wlc_attach(struct wl_info *wl, u16 vendor, u16 device, uint unit,
bool piomode, void *regsva, uint bustype, void *btparam,
uint *perr);
extern uint wlc_detach(struct wlc_info *wlc);
@@ -499,8 +505,6 @@
extern bool wlc_intrsupd(struct wlc_info *wlc);
extern bool wlc_isr(struct wlc_info *wlc, bool *wantdpc);
extern bool wlc_dpc(struct wlc_info *wlc, bool bounded);
-extern bool wlc_send80211_raw(struct wlc_info *wlc, struct wlc_if *wlcif,
- void *p, uint ac);
extern bool wlc_sendpkt_mac80211(struct wlc_info *wlc, struct sk_buff *sdu,
struct ieee80211_hw *hw);
extern int wlc_iovar_op(struct wlc_info *wlc, const char *name, void *params,
@@ -508,6 +512,8 @@
struct wlc_if *wlcif);
extern int wlc_ioctl(struct wlc_info *wlc, int cmd, void *arg, int len,
struct wlc_if *wlcif);
+extern bool wlc_aggregatable(struct wlc_info *wlc, u8 tid);
+
/* helper functions */
extern void wlc_statsupd(struct wlc_info *wlc);
extern void wlc_protection_upd(struct wlc_info *wlc, uint idx, int val);
@@ -515,24 +521,14 @@
extern void wlc_mac_bcn_promisc_change(struct wlc_info *wlc, bool promisc);
extern void wlc_set_addrmatch(struct wlc_info *wlc, int match_reg_offset,
const u8 *addr);
-extern void wlc_wme_setparams(struct wlc_info *wlc, u16 aci, void *arg,
+extern void wlc_wme_setparams(struct wlc_info *wlc, u16 aci,
+ const struct ieee80211_tx_queue_params *arg,
bool suspend);
-
extern struct wlc_pub *wlc_pub(void *wlc);
/* common functions for every port */
-extern int wlc_bmac_up_prep(struct wlc_hw_info *wlc_hw);
-extern int wlc_bmac_up_finish(struct wlc_hw_info *wlc_hw);
-extern int wlc_bmac_down_prep(struct wlc_hw_info *wlc_hw);
-extern int wlc_bmac_down_finish(struct wlc_hw_info *wlc_hw);
-
-extern u32 wlc_reg_read(struct wlc_info *wlc, void *r, uint size);
-extern void wlc_reg_write(struct wlc_info *wlc, void *r, u32 v, uint size);
-extern void wlc_corereset(struct wlc_info *wlc, u32 flags);
extern void wlc_mhf(struct wlc_info *wlc, u8 idx, u16 mask, u16 val,
int bands);
-extern u16 wlc_mhf_get(struct wlc_info *wlc, u8 idx, int bands);
-extern u32 wlc_delta_txfunfl(struct wlc_info *wlc, int fifo);
extern void wlc_rate_lookup_init(struct wlc_info *wlc, wlc_rateset_t *rateset);
extern void wlc_default_rateset(struct wlc_info *wlc, wlc_rateset_t *rs);
@@ -543,11 +539,8 @@
/* wlc_phy.c helper functions */
extern void wlc_set_ps_ctrl(struct wlc_info *wlc);
extern void wlc_mctrl(struct wlc_info *wlc, u32 mask, u32 val);
-extern void wlc_scb_ratesel_init_all(struct wlc_info *wlc);
/* ioctl */
-extern int wlc_iovar_gets8(struct wlc_info *wlc, const char *name,
- s8 *arg);
extern int wlc_iovar_check(struct wlc_pub *pub, const bcm_iovar_t *vi,
void *arg,
int len, bool set);
@@ -562,31 +555,12 @@
extern void wlc_associate_upd(struct wlc_info *wlc, bool state);
extern void wlc_scan_start(struct wlc_info *wlc);
extern void wlc_scan_stop(struct wlc_info *wlc);
-
-static inline int wlc_iovar_getuint(struct wlc_info *wlc, const char *name,
- uint *arg)
-{
- return wlc_iovar_getint(wlc, name, (int *)arg);
-}
-
-static inline int wlc_iovar_getu8(struct wlc_info *wlc, const char *name,
- u8 *arg)
-{
- return wlc_iovar_gets8(wlc, name, (s8 *) arg);
-}
-
-static inline int wlc_iovar_setuint(struct wlc_info *wlc, const char *name,
- uint arg)
-{
- return wlc_iovar_setint(wlc, name, (int)arg);
-}
+extern int wlc_get_curband(struct wlc_info *wlc);
+extern void wlc_wait_for_tx_completion(struct wlc_info *wlc, bool drop);
#if defined(BCMDBG)
extern int wlc_iocregchk(struct wlc_info *wlc, uint band);
#endif
-#if defined(BCMDBG)
-extern int wlc_iocpichk(struct wlc_info *wlc, uint phytype);
-#endif
/* helper functions */
extern bool wlc_check_radio_disabled(struct wlc_info *wlc);
diff --git a/drivers/staging/brcm80211/brcmsmac/wlc_rate.c b/drivers/staging/brcm80211/brcmsmac/wlc_rate.c
index d284f1a..87b252d 100644
--- a/drivers/staging/brcm80211/brcmsmac/wlc_rate.c
+++ b/drivers/staging/brcm80211/brcmsmac/wlc_rate.c
@@ -19,7 +19,7 @@
#include <proto/802.11.h>
#include <bcmdefs.h>
#include <bcmutils.h>
-#include <siutils.h>
+#include <aiutils.h>
#include <wlioctl.h>
#include <sbhnddma.h>
@@ -304,7 +304,7 @@
for (i = 0; i < count; i++) {
/* mask off "basic rate" bit, WLC_RATE_FLAG */
- r = (int)rs->rates[i] & RATE_MASK;
+ r = (int)rs->rates[i] & WLC_RATE_MASK;
if ((r > WLC_MAXRATE) || (rate_info[r] == 0)) {
continue;
}
@@ -314,8 +314,7 @@
/* fill out the rates in order, looking at only supported rates */
count = 0;
for (i = 0; i < hw_rs->count; i++) {
- r = hw_rs->rates[i] & RATE_MASK;
- ASSERT(r <= WLC_MAXRATE);
+ r = hw_rs->rates[i] & WLC_RATE_MASK;
if (rateset[r])
rs->rates[count++] = rateset[r];
}
@@ -333,7 +332,7 @@
}
/* calculate the rate of a rx'd frame and return it as a ratespec */
-ratespec_t BCMFASTPATH wlc_compute_rspec(d11rxhdr_t *rxh, u8 *plcp)
+ratespec_t wlc_compute_rspec(d11rxhdr_t *rxh, u8 *plcp)
{
int phy_type;
ratespec_t rspec = PHY_TXC1_BW_20MHZ << RSPEC_BW_SHIFT;
@@ -364,8 +363,7 @@
case PRXS0_STDN:
/* fallthru */
default:
- /* not supported */
- ASSERT(0);
+ /* not supported, error condition */
break;
}
if (PLCP3_ISSGI(plcp[3]))
@@ -407,9 +405,9 @@
r = src->rates[i];
if (basic_only && !(r & WLC_RATE_FLAG))
continue;
- if ((rates == WLC_RATES_CCK) && IS_OFDM((r & RATE_MASK)))
+ if ((rates == WLC_RATES_CCK) && IS_OFDM((r & WLC_RATE_MASK)))
continue;
- if ((rates == WLC_RATES_OFDM) && IS_CCK((r & RATE_MASK)))
+ if ((rates == WLC_RATES_OFDM) && IS_CCK((r & WLC_RATE_MASK)))
continue;
dst->rates[count++] = r & xmask;
}
@@ -451,7 +449,7 @@
} else if (PHYTYPE_IS(phy_type, PHY_TYPE_G)) {
rs_dflt = &cck_ofdm_rates;
} else {
- ASSERT(0); /* should not happen */
+ /* should not happen, error condition */
rs_dflt = &cck_rates; /* force cck */
}
@@ -468,7 +466,7 @@
mcsallow ? txstreams : 1);
}
-s16 BCMFASTPATH wlc_rate_legacy_phyctl(uint rate)
+s16 wlc_rate_legacy_phyctl(uint rate)
{
uint i;
for (i = 0; i < LEGACY_PHYCFG_TABLE_SIZE; i++)
diff --git a/drivers/staging/brcm80211/brcmsmac/wlc_rate.h b/drivers/staging/brcm80211/brcmsmac/wlc_rate.h
index 25ba2a4..5575e83 100644
--- a/drivers/staging/brcm80211/brcmsmac/wlc_rate.h
+++ b/drivers/staging/brcm80211/brcmsmac/wlc_rate.h
@@ -54,11 +54,8 @@
(_is40 ? mcs_table[_mcs].phy_rate_40 : mcs_table[_mcs].phy_rate_20))
#define VALID_MCS(_mcs) ((_mcs < MCS_TABLE_SIZE))
-#define WLC_RATE_FLAG 0x80 /* Rate flag: basic or ofdm */
-
-/* Macros to use the rate_info table */
-#define RATE_MASK 0x7f /* Rate value mask w/o basic rate flag */
-#define RATE_MASK_FULL 0xff /* Rate value mask with basic rate flag */
+/* Macro to use the rate_info table */
+#define WLC_RATE_MASK_FULL 0xff /* Rate value mask with basic rate flag */
#define WLC_RATE_500K_TO_BPS(rate) ((rate) * 500000) /* convert 500kbps to bps */
@@ -115,9 +112,11 @@
/* Rate info table; takes a legacy rate or ratespec_t */
#define IS_MCS(r) (r & RSPEC_MIMORATE)
#define IS_OFDM(r) (!IS_MCS(r) && (rate_info[(r) & RSPEC_RATE_MASK] & WLC_RATE_FLAG))
-#define IS_CCK(r) (!IS_MCS(r) && (((r) & RATE_MASK) == WLC_RATE_1M || \
- ((r) & RATE_MASK) == WLC_RATE_2M || \
- ((r) & RATE_MASK) == WLC_RATE_5M5 || ((r) & RATE_MASK) == WLC_RATE_11M))
+#define IS_CCK(r) (!IS_MCS(r) && ( \
+ ((r) & WLC_RATE_MASK) == WLC_RATE_1M || \
+ ((r) & WLC_RATE_MASK) == WLC_RATE_2M || \
+ ((r) & WLC_RATE_MASK) == WLC_RATE_5M5 || \
+ ((r) & WLC_RATE_MASK) == WLC_RATE_11M))
#define IS_SINGLE_STREAM(mcs) (((mcs) <= HIGHEST_SINGLE_STREAM_MCS) || ((mcs) == 32))
#define CCK_RSPEC(cck) ((cck) & RSPEC_RATE_MASK)
#define OFDM_RSPEC(ofdm) (((ofdm) & RSPEC_RATE_MASK) |\
diff --git a/drivers/staging/brcm80211/brcmsmac/wlc_scb.h b/drivers/staging/brcm80211/brcmsmac/wlc_scb.h
index 7326006..f07a891 100644
--- a/drivers/staging/brcm80211/brcmsmac/wlc_scb.h
+++ b/drivers/staging/brcm80211/brcmsmac/wlc_scb.h
@@ -17,8 +17,6 @@
#ifndef _wlc_scb_h_
#define _wlc_scb_h_
-extern bool wlc_aggregatable(struct wlc_info *wlc, u8 tid);
-
#define AMPDU_TX_BA_MAX_WSIZE 64 /* max Tx ba window size (in pdu) */
/* structure to store per-tid state for the ampdu initiator */
typedef struct scb_ampdu_tid_ini {
diff --git a/drivers/staging/brcm80211/brcmsmac/wlc_stf.c b/drivers/staging/brcm80211/brcmsmac/wlc_stf.c
index 098fd59..c4f5817 100644
--- a/drivers/staging/brcm80211/brcmsmac/wlc_stf.c
+++ b/drivers/staging/brcm80211/brcmsmac/wlc_stf.c
@@ -21,9 +21,10 @@
#include <bcmdefs.h>
#include <bcmutils.h>
-#include <siutils.h>
+#include <aiutils.h>
#include <wlioctl.h>
#include <bcmwifi.h>
+#include <bcmnvram.h>
#include <sbhnddma.h>
#include "wlc_types.h"
@@ -69,9 +70,6 @@
static void wlc_stf_stbc_rx_ht_update(struct wlc_info *wlc, int val)
{
- ASSERT((val == HT_CAP_RX_STBC_NO)
- || (val == HT_CAP_RX_STBC_ONE_STREAM));
-
/* MIMOPHYs rev3-6 cannot receive STBC with only one rx core active */
if (WLC_STF_SS_STBC_RX(wlc)) {
if ((wlc->stf->rxstreams == 1) && (val != HT_CAP_RX_STBC_NO))
@@ -193,10 +191,8 @@
static int wlc_stf_txcore_set(struct wlc_info *wlc, u8 Nsts, u8 core_mask)
{
- WL_TRACE("wl%d: %s: Nsts %d core_mask %x\n",
- wlc->pub->unit, __func__, Nsts, core_mask);
-
- ASSERT((Nsts > 0) && (Nsts <= MAX_STREAMS_SUPPORTED));
+ BCMMSG(wlc->wiphy, "wl%d: Nsts %d core_mask %x\n",
+ wlc->pub->unit, Nsts, core_mask);
if (WLC_BITSCNT(core_mask) > wlc->stf->txstreams) {
core_mask = 0;
@@ -208,8 +204,6 @@
core_mask = wlc->stf->txchain;
}
- ASSERT(!core_mask || Nsts <= WLC_BITSCNT(core_mask));
-
wlc->stf->txcore[Nsts] = core_mask;
/* Nsts = 1..4, txcore index = 1..4 */
if (Nsts == 1) {
@@ -225,7 +219,7 @@
}
}
- return BCME_OK;
+ return 0;
}
static int wlc_stf_spatial_policy_set(struct wlc_info *wlc, int val)
@@ -233,7 +227,7 @@
int i;
u8 core_mask = 0;
- WL_TRACE("wl%d: %s: val %x\n", wlc->pub->unit, __func__, val);
+ BCMMSG(wlc->wiphy, "wl%d: val %x\n", wlc->pub->unit, val);
wlc->stf->spatial_policy = (s8) val;
for (i = 1; i <= MAX_STREAMS_SUPPORTED; i++) {
@@ -241,7 +235,7 @@
wlc->stf->txchain : txcore_default[i];
wlc_stf_txcore_set(wlc, (u8) i, core_mask);
}
- return BCME_OK;
+ return 0;
}
int wlc_stf_txchain_set(struct wlc_info *wlc, s32 int_val, bool force)
@@ -251,16 +245,16 @@
uint i;
if (wlc->stf->txchain == txchain)
- return BCME_OK;
+ return 0;
if ((txchain & ~wlc->stf->hw_txchain)
|| !(txchain & wlc->stf->hw_txchain))
- return BCME_RANGE;
+ return -EINVAL;
/* if nrate override is configured to be non-SISO STF mode, reject reducing txchain to 1 */
txstreams = (u8) WLC_BITSCNT(txchain);
if (txstreams > MAX_STREAMS_SUPPORTED)
- return BCME_RANGE;
+ return -EINVAL;
if (txstreams == 1) {
for (i = 0; i < NBANDS(wlc); i++)
@@ -269,21 +263,25 @@
|| (RSPEC_STF(wlc->bandstate[i]->mrspec_override) !=
PHY_TXC1_MODE_SISO)) {
if (!force)
- return BCME_ERROR;
+ return -EBADE;
/* over-write the override rspec */
if (RSPEC_STF(wlc->bandstate[i]->rspec_override)
!= PHY_TXC1_MODE_SISO) {
wlc->bandstate[i]->rspec_override = 0;
- WL_ERROR("%s(): temp sense override non-SISO rspec_override\n",
- __func__);
+ wiphy_err(wlc->wiphy, "%s(): temp "
+ "sense override non-SISO "
+ "rspec_override\n",
+ __func__);
}
if (RSPEC_STF
(wlc->bandstate[i]->mrspec_override) !=
PHY_TXC1_MODE_SISO) {
wlc->bandstate[i]->mrspec_override = 0;
- WL_ERROR("%s(): temp sense override non-SISO mrspec_override\n",
- __func__);
+ wiphy_err(wlc->wiphy, "%s(): temp "
+ "sense override non-SISO "
+ "mrspec_override\n",
+ __func__);
}
}
}
@@ -303,7 +301,7 @@
for (i = 1; i <= MAX_STREAMS_SUPPORTED; i++)
wlc_stf_txcore_set(wlc, (u8) i, txcore_default[i]);
- return BCME_OK;
+ return 0;
}
/* update wlc->stf->ss_opmode which represents the operational stf_ss mode we're using */
@@ -319,9 +317,6 @@
if (WLC_STBC_CAP_PHY(wlc) &&
wlc->stf->ss_algosel_auto
&& (wlc->stf->ss_algo_channel != (u16) -1)) {
- ASSERT(isset(&wlc->stf->ss_algo_channel, PHY_TXC1_MODE_CDD)
- || isset(&wlc->stf->ss_algo_channel,
- PHY_TXC1_MODE_SISO));
upd_stf_ss = (wlc->stf->no_cddstbc || (wlc->stf->txstreams == 1)
|| isset(&wlc->stf->ss_algo_channel,
PHY_TXC1_MODE_SISO)) ? PHY_TXC1_MODE_SISO
@@ -371,11 +366,11 @@
int wlc_stf_ant_txant_validate(struct wlc_info *wlc, s8 val)
{
- int bcmerror = BCME_OK;
+ int bcmerror = 0;
/* when there is only 1 tx_streams, don't allow to change the txant */
if (WLCISNPHY(wlc->band) && (wlc->stf->txstreams == 1))
- return ((val == wlc->stf->txant) ? bcmerror : BCME_RANGE);
+ return ((val == wlc->stf->txant) ? bcmerror : -EINVAL);
switch (val) {
case -1:
@@ -391,11 +386,11 @@
val = ANT_TX_LAST_RX;
break;
default:
- bcmerror = BCME_RANGE;
+ bcmerror = -EINVAL;
break;
}
- if (bcmerror == BCME_OK)
+ if (bcmerror == 0)
wlc->stf->txant = (s8) val;
return bcmerror;
@@ -421,9 +416,6 @@
s8 txant;
txant = (s8) wlc->stf->txant;
- ASSERT(txant == ANT_TX_FORCE_0 || txant == ANT_TX_FORCE_1
- || txant == ANT_TX_LAST_RX);
-
if (WLC_PHY_11N_CAP(wlc->band)) {
if (txant == ANT_TX_FORCE_0) {
wlc->stf->phytxant = PHY_TXC_ANT_0;
@@ -439,8 +431,8 @@
if (WLCISLCNPHY(wlc->band) || WLCISSSLPNPHY(wlc->band))
wlc->stf->phytxant = PHY_TXC_LCNPHY_ANT_LAST;
else {
- /* keep this assert to catch out of sync wlc->stf->txcore */
- ASSERT(wlc->stf->txchain > 0);
+ /* catch out of sync wlc->stf->txcore */
+ WARN_ON(wlc->stf->txchain <= 0);
wlc->stf->phytxant =
wlc->stf->txchain << PHY_TXC_ANT_SHIFT;
}
@@ -504,7 +496,6 @@
u16 phytxant = wlc->stf->phytxant;
if (RSPEC_STF(rspec) != PHY_TXC1_MODE_SISO) {
- ASSERT(wlc->stf->txstreams > 1);
phytxant = wlc->stf->txchain << PHY_TXC_ANT_SHIFT;
} else if (wlc->stf->txant == ANT_TX_DEF)
phytxant = wlc->stf->txchain << PHY_TXC_ANT_SHIFT;
@@ -524,7 +515,6 @@
/* for non-siso rates or default setting, use the available chains */
if (WLCISNPHY(wlc->band)) {
- ASSERT(wlc->stf->txchain != 0);
phytxant = _wlc_stf_phytxchain_sel(wlc, rspec);
mask = PHY_TXC_HTANT_MASK;
}
diff --git a/drivers/staging/brcm80211/include/aidmp.h b/drivers/staging/brcm80211/include/aidmp.h
index d33f020..7e0ce8f 100644
--- a/drivers/staging/brcm80211/include/aidmp.h
+++ b/drivers/staging/brcm80211/include/aidmp.h
@@ -292,7 +292,7 @@
#define AI_OOBDINWIDTH 0x364
#define AI_OOBDOUTWIDTH 0x368
-#if defined(IL_BIGENDIAN) && defined(BCMHND74K)
+#if defined(__BIG_ENDIAN) && defined(BCMHND74K)
/* Selective swapped defines for those registers we need in
* big-endian code.
*/
@@ -303,7 +303,7 @@
#define AI_RESETCTRL 0x804
#define AI_RESETSTATUS 0x800
-#else /* !IL_BIGENDIAN || !BCMHND74K */
+#else /* !__BIG_ENDIAN || !BCMHND74K */
#define AI_IOCTRLSET 0x400
#define AI_IOCTRLCLEAR 0x404
@@ -312,7 +312,7 @@
#define AI_RESETCTRL 0x800
#define AI_RESETSTATUS 0x804
-#endif /* IL_BIGENDIAN && BCMHND74K */
+#endif /* __BIG_ENDIAN && BCMHND74K */
#define AI_IOCTRLWIDTH 0x700
#define AI_IOSTATUSWIDTH 0x704
diff --git a/drivers/staging/brcm80211/include/bcmdefs.h b/drivers/staging/brcm80211/include/bcmdefs.h
index 22a389e..55631f3 100644
--- a/drivers/staging/brcm80211/include/bcmdefs.h
+++ b/drivers/staging/brcm80211/include/bcmdefs.h
@@ -36,12 +36,6 @@
#define AUTO (-1) /* Auto = -1 */
-#ifdef mips
-#define BCMFASTPATH __attribute__ ((__section__(".text.fastpath")))
-#else
-#define BCMFASTPATH
-#endif
-
/* Bus types */
#define SI_BUS 0 /* SOC Interconnect */
#define PCI_BUS 1 /* PCI target */
@@ -114,12 +108,6 @@
#define BCMEXTRAHDROOM 172
-#ifdef BCMDBG
-#ifndef BCMDBG_ASSERT
-#define BCMDBG_ASSERT
-#endif /* BCMDBG_ASSERT */
-#endif /* BCMDBG */
-
/* Macros for doing definition and get/set of bitfields
* Usage example, e.g. a three-bit field (bits 4-6):
* #define <NAME>_M BITFIELD_MASK(3)
diff --git a/drivers/staging/brcm80211/include/bcmdevs.h b/drivers/staging/brcm80211/include/bcmdevs.h
index 075883a..26947ef 100644
--- a/drivers/staging/brcm80211/include/bcmdevs.h
+++ b/drivers/staging/brcm80211/include/bcmdevs.h
@@ -17,17 +17,10 @@
#ifndef _BCMDEVS_H
#define _BCMDEVS_H
-/* PCI vendor IDs */
-#define VENDOR_BROADCOM 0x14e4
-
-/* DONGLE VID/PIDs */
-#define BCM_DNGL_VID 0x0a5c
-#define BCM_DNGL_BDC_PID 0x0bdc
-
#define BCM4325_D11DUAL_ID 0x431b
#define BCM4325_D11G_ID 0x431c
#define BCM4325_D11A_ID 0x431d
-#define BCM4329_D11N_ID 0x432e /* 4329 802.11n dualband device */
+
#define BCM4329_D11N2G_ID 0x432f /* 4329 802.11n 2.4G device */
#define BCM4329_D11N5G_ID 0x4330 /* 4329 802.11n 5G device */
#define BCM4329_D11NDUAL_ID 0x432e
@@ -37,22 +30,13 @@
#define BCM4319_D11N5G_ID 0x4339 /* 4319 802.11n 5G device */
#define BCM43224_D11N_ID 0x4353 /* 43224 802.11n dualband device */
+
#define BCM43225_D11N2G_ID 0x4357 /* 43225 802.11n 2.4GHz device */
#define BCM43236_D11N_ID 0x4346 /* 43236 802.11n dualband device */
#define BCM43236_D11N2G_ID 0x4347 /* 43236 802.11n 2.4GHz device */
-#define BCM43236_D11N5G_ID 0x4348 /* 43236 802.11n 5GHz device */
-#define BCM43421_D11N_ID 0xA99D /* 43421 802.11n dualband device */
#define BCM4313_D11N2G_ID 0x4727 /* 4313 802.11n 2.4G device */
-#define BCM4330_D11N_ID 0x4360 /* 4330 802.11n dualband device */
-#define BCM4330_D11N2G_ID 0x4361 /* 4330 802.11n 2.4G device */
-#define BCM4330_D11N5G_ID 0x4362 /* 4330 802.11n 5G device */
-#define BCM4336_D11N_ID 0x4343 /* 4336 802.11n 2.4GHz device */
-#define BCM6362_D11N_ID 0x435f /* 6362 802.11n dualband device */
-#define BCM4331_D11N_ID 0x4331 /* 4331 802.11n dualband id */
-#define BCM4331_D11N2G_ID 0x4332 /* 4331 802.11n 2.4Ghz band id */
-#define BCM4331_D11N5G_ID 0x4333 /* 4331 802.11n 5Ghz band id */
/* Chip IDs */
#define BCM4313_CHIP_ID 0x4313 /* 4313 chip id */
@@ -60,7 +44,6 @@
#define BCM43224_CHIP_ID 43224 /* 43224 chipcommon chipid */
#define BCM43225_CHIP_ID 43225 /* 43225 chipcommon chipid */
-#define BCM43228_CHIP_ID 43228 /* 43228 chipcommon chipid */
#define BCM43421_CHIP_ID 43421 /* 43421 chipcommon chipid */
#define BCM43235_CHIP_ID 43235 /* 43235 chipcommon chipid */
#define BCM43236_CHIP_ID 43236 /* 43236 chipcommon chipid */
@@ -82,57 +65,23 @@
/* Package IDs */
#define BCM4329_289PIN_PKG_ID 0 /* 4329 289-pin package id */
#define BCM4329_182PIN_PKG_ID 1 /* 4329N 182-pin package id */
-#define BCM4716_PKG_ID 8 /* 4716 package id */
#define BCM4717_PKG_ID 9 /* 4717 package id */
#define BCM4718_PKG_ID 10 /* 4718 package id */
-#define BCM5356_PKG_NONMODE 1 /* 5356 package without nmode suppport */
-#define BCM5358U_PKG_ID 8 /* 5358U package id */
-#define BCM5358_PKG_ID 9 /* 5358 package id */
-#define BCM47186_PKG_ID 10 /* 47186 package id */
-#define BCM5357_PKG_ID 11 /* 5357 package id */
-#define BCM5356U_PKG_ID 12 /* 5356U package id */
-#define HDLSIM5350_PKG_ID 1 /* HDL simulator package id for a 5350 */
#define HDLSIM_PKG_ID 14 /* HDL simulator package id */
#define HWSIM_PKG_ID 15 /* Hardware simulator package id */
-#define BCM43224_FAB_CSM 0x8 /* the chip is manufactured by CSM */
#define BCM43224_FAB_SMIC 0xa /* the chip is manufactured by SMIC */
-#define BCM4336_WLBGA_PKG_ID 0x8
/* boardflags */
-#define BFL_RESERVED1 0x00000001
#define BFL_PACTRL 0x00000002 /* Board has gpio 9 controlling the PA */
-#define BFL_AIRLINEMODE 0x00000004 /* Board implements gpio 13 radio disable indication */
-#define BFL_ADCDIV 0x00000008 /* Board has the rssi ADC divider */
-#define BFL_ENETROBO 0x00000010 /* Board has robo switch or core */
#define BFL_NOPLLDOWN 0x00000020 /* Not ok to power down the chip pll and oscillator */
-#define BFL_CCKHIPWR 0x00000040 /* Can do high-power CCK transmission */
-#define BFL_ENETADM 0x00000080 /* Board has ADMtek switch */
-#define BFL_ENETVLAN 0x00000100 /* Board has VLAN capability */
-#define BFL_NOPCI 0x00000400 /* Board leaves PCI floating */
#define BFL_FEM 0x00000800 /* Board supports the Front End Module */
#define BFL_EXTLNA 0x00001000 /* Board has an external LNA in 2.4GHz band */
-#define BFL_HGPA 0x00002000 /* Board has a high gain PA */
-#define BFL_RESERVED2 0x00004000
-#define BFL_ALTIQ 0x00008000 /* Alternate I/Q settings */
#define BFL_NOPA 0x00010000 /* Board has no PA */
-#define BFL_RSSIINV 0x00020000 /* Board's RSSI uses positive slope(not TSSI) */
-#define BFL_PAREF 0x00040000 /* Board uses the PARef LDO */
-#define BFL_3TSWITCH 0x00080000 /* Board uses a triple throw switch shared with BT */
-#define BFL_PHASESHIFT 0x00100000 /* Board can support phase shifter */
#define BFL_BUCKBOOST 0x00200000 /* Power topology uses BUCKBOOST */
#define BFL_FEM_BT 0x00400000 /* Board has FEM and switch to share antenna w/ BT */
#define BFL_NOCBUCK 0x00800000 /* Power topology doesn't use CBUCK */
-#define BFL_CCKFAVOREVM 0x01000000 /* Favor CCK EVM over spectral mask */
#define BFL_PALDO 0x02000000 /* Power topology uses PALDO */
-#define BFL_LNLDO2_2P5 0x04000000 /* Select 2.5V as LNLDO2 output voltage */
-#define BFL_FASTPWR 0x08000000
-#define BFL_UCPWRCTL_MININDX 0x08000000 /* Enforce min power index to avoid FEM damage */
#define BFL_EXTLNA_5GHz 0x10000000 /* Board has an external LNA in 5GHz band */
-#define BFL_TRSW_1by2 0x20000000 /* Board has 2 TRSW's in 1by2 designs */
-#define BFL_LO_TRSW_R_5GHz 0x40000000 /* In 5G do not throw TRSW to T for clipLO gain */
-#define BFL_ELNA_GAINDEF 0x80000000 /* Backoff InitGain based on elna_2g/5g field
- * when this flag is set
- */
/* boardflags2 */
#define BFL2_RXBB_INT_REG_DIS 0x00000001 /* Board has an external rxbb regulator */
@@ -141,16 +90,12 @@
#define BFL2_2X4_DIV 0x00000008 /* Board supports the 2X4 diversity switch */
#define BFL2_5G_PWRGAIN 0x00000010 /* Board supports 5G band power gain */
#define BFL2_PCIEWAR_OVR 0x00000020 /* Board overrides ASPM and Clkreq settings */
-#define BFL2_CAESERS_BRD 0x00000040 /* Board is Caesers brd (unused by sw) */
#define BFL2_LEGACY 0x00000080
#define BFL2_SKWRKFEM_BRD 0x00000100 /* 4321mcm93 board uses Skyworks FEM */
#define BFL2_SPUR_WAR 0x00000200 /* Board has a WAR for clock-harmonic spurs */
#define BFL2_GPLL_WAR 0x00000400 /* Flag to narrow G-band PLL loop b/w */
-#define BFL2_TRISTATE_LED 0x00000800 /* Tri-state the LED */
#define BFL2_SINGLEANT_CCK 0x00001000 /* Tx CCK pkts on Ant 0 only */
#define BFL2_2G_SPUR_WAR 0x00002000 /* WAR to reduce and avoid clock-harmonic spurs in 2G */
-#define BFL2_BPHY_ALL_TXCORES 0x00004000 /* Transmit bphy frames using all tx cores */
-#define BFL2_FCC_BANDEDGE_WAR 0x00008000 /* using 40Mhz LPF for 20Mhz bandedge channels */
#define BFL2_GPLL_WAR2 0x00010000 /* Flag to widen G-band PLL loop b/w */
#define BFL2_IPALVLSHIFT_3P3 0x00020000
#define BFL2_INTERNDET_TXIQCAL 0x00040000 /* Use internal envelope detector for TX IQCAL */
@@ -160,32 +105,19 @@
*/
/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
-#define BOARD_GPIO_RESERVED1 0x010
-#define BOARD_GPIO_RESERVED2 0x020
-#define BOARD_GPIO_RESERVED3 0x080
-#define BOARD_GPIO_RESERVED4 0x100
#define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */
#define BOARD_GPIO_12 0x1000 /* gpio 12 */
#define BOARD_GPIO_13 0x2000 /* gpio 13 */
-#define BOARD_GPIO_RESERVED5 0x0800
-#define BOARD_GPIO_RESERVED6 0x2000
-#define BOARD_GPIO_RESERVED7 0x4000
-#define BOARD_GPIO_RESERVED8 0x8000
#define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
-#define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
#define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal power-up */
#define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL power-down */
/* power control defines */
#define PLL_DELAY 150 /* us pll on delay */
#define FREF_DELAY 200 /* us fref change delay */
-#define MIN_SLOW_CLK 32 /* us Slow clock period */
#define XTAL_ON_DELAY 1000 /* us crystal power-on delay */
-/* # of GPIO pins */
-#define GPIO_NUMPINS 16
-
/* Reference board types */
#define SPI_BOARD 0x0402
diff --git a/drivers/staging/brcm80211/include/bcmnvram.h b/drivers/staging/brcm80211/include/bcmnvram.h
index e194131..12645dd 100644
--- a/drivers/staging/brcm80211/include/bcmnvram.h
+++ b/drivers/staging/brcm80211/include/bcmnvram.h
@@ -30,31 +30,26 @@
};
/*
- * Get default value for an NVRAM variable
- */
-extern char *nvram_default_get(const char *name);
-
-/*
* Initialize NVRAM access. May be unnecessary or undefined on certain
* platforms.
*/
-extern int nvram_init(void *sih);
+extern int nvram_init(void);
/*
* Append a chunk of nvram variables to the global list
*/
-extern int nvram_append(void *si, char *vars, uint varsz);
+extern int nvram_append(char *vars, uint varsz);
/*
* Check for reset button press for restoring factory defaults.
*/
-extern int nvram_reset(void *sih);
+extern int nvram_reset(void);
/*
* Disable NVRAM access. May be unnecessary or undefined on certain
* platforms.
*/
-extern void nvram_exit(void *sih);
+extern void nvram_exit(void);
/*
* Get the value of an NVRAM variable. The pointer returned may be
@@ -65,12 +60,6 @@
extern char *nvram_get(const char *name);
/*
- * Read the reset GPIO value from the nvram and set the GPIO
- * as input
- */
-extern int nvram_resetgpio_init(void *sih);
-
-/*
* Get the value of an NVRAM variable.
* @param name name of variable to get
* @return value of variable or NUL if undefined
@@ -139,14 +128,12 @@
*/
extern int nvram_getall(char *nvram_buf, int count);
-/*
- * returns the crc value of the nvram
- * @param nvh nvram header pointer
- */
-u8 nvram_calc_crc(struct nvram_header *nvh);
-
#endif /* _LANGUAGE_ASSEMBLY */
+/* variable access */
+extern char *getvar(char *vars, const char *name);
+extern int getintvar(char *vars, const char *name);
+
/* The NVRAM version number stored as an NVRAM variable */
#define NVRAM_SOFTWARE_VERSION "1"
diff --git a/drivers/staging/brcm80211/include/bcmsdpcm.h b/drivers/staging/brcm80211/include/bcmsdpcm.h
index 4869947..5175e67 100644
--- a/drivers/staging/brcm80211/include/bcmsdpcm.h
+++ b/drivers/staging/brcm80211/include/bcmsdpcm.h
@@ -186,7 +186,7 @@
* Shared structure between dongle and the host.
* The structure contains pointers to trap or assert information.
*/
-#define SDPCM_SHARED_VERSION 0x0001
+#define SDPCM_SHARED_VERSION 0x0002
#define SDPCM_SHARED_VERSION_MASK 0x00FF
#define SDPCM_SHARED_ASSERT_BUILT 0x0100
#define SDPCM_SHARED_ASSERT 0x0200
@@ -200,6 +200,7 @@
u32 assert_line;
u32 console_addr; /* Address of hndrte_cons_t */
u32 msgtrace_addr;
+ u8 tag[32];
} sdpcm_shared_t;
extern sdpcm_shared_t sdpcm_shared;
diff --git a/drivers/staging/brcm80211/include/bcmsrom_fmt.h b/drivers/staging/brcm80211/include/bcmsrom_fmt.h
index 4768968..4666afd 100644
--- a/drivers/staging/brcm80211/include/bcmsrom_fmt.h
+++ b/drivers/staging/brcm80211/include/bcmsrom_fmt.h
@@ -105,7 +105,7 @@
/* SROM Rev 4: Reallocate the software part of the srom to accommodate
* MIMO features. It assumes up to two PCIE functions and 440 bytes
- * of useable srom i.e. the useable storage in chips with OTP that
+ * of usable srom i.e. the usable storage in chips with OTP that
* implements hardware redundancy.
*/
diff --git a/drivers/staging/brcm80211/include/bcmutils.h b/drivers/staging/brcm80211/include/bcmutils.h
index fc2a2a9..17683f2 100644
--- a/drivers/staging/brcm80211/include/bcmutils.h
+++ b/drivers/staging/brcm80211/include/bcmutils.h
@@ -74,7 +74,7 @@
#define PKTQ_PREC_ITER(pq, prec) for (prec = (pq)->num_prec - 1; prec >= 0; prec--)
/* fn(pkt, arg). return true if pkt belongs to if */
- typedef bool(*ifpkt_cb_t) (void *, int);
+typedef bool(*ifpkt_cb_t) (struct sk_buff *, void *);
/* operations on a specific precedence in packet queue */
@@ -87,30 +87,26 @@
#define pktq_ppeek(pq, prec) ((pq)->q[prec].head)
#define pktq_ppeek_tail(pq, prec) ((pq)->q[prec].tail)
-extern struct sk_buff *pktq_penq(struct pktq *pq, int prec,
+extern struct sk_buff *bcm_pktq_penq(struct pktq *pq, int prec,
struct sk_buff *p);
-extern struct sk_buff *pktq_penq_head(struct pktq *pq, int prec,
+extern struct sk_buff *bcm_pktq_penq_head(struct pktq *pq, int prec,
struct sk_buff *p);
-extern struct sk_buff *pktq_pdeq(struct pktq *pq, int prec);
-extern struct sk_buff *pktq_pdeq_tail(struct pktq *pq, int prec);
+extern struct sk_buff *bcm_pktq_pdeq(struct pktq *pq, int prec);
+extern struct sk_buff *bcm_pktq_pdeq_tail(struct pktq *pq, int prec);
/* packet primitives */
-extern struct sk_buff *pkt_buf_get_skb(uint len);
-extern void pkt_buf_free_skb(struct sk_buff *skb);
+extern struct sk_buff *bcm_pkt_buf_get_skb(uint len);
+extern void bcm_pkt_buf_free_skb(struct sk_buff *skb);
/* Empty the queue at particular precedence level */
-#ifdef BRCM_FULLMAC
- extern void pktq_pflush(struct pktq *pq, int prec,
- bool dir);
-#else
- extern void pktq_pflush(struct pktq *pq, int prec,
- bool dir, ifpkt_cb_t fn, int arg);
-#endif /* BRCM_FULLMAC */
+extern void bcm_pktq_pflush(struct pktq *pq, int prec,
+ bool dir, ifpkt_cb_t fn, void *arg);
/* operations on a set of precedences in packet queue */
-extern int pktq_mlen(struct pktq *pq, uint prec_bmp);
-extern struct sk_buff *pktq_mdeq(struct pktq *pq, uint prec_bmp, int *prec_out);
+extern int bcm_pktq_mlen(struct pktq *pq, uint prec_bmp);
+extern struct sk_buff *bcm_pktq_mdeq(struct pktq *pq, uint prec_bmp,
+ int *prec_out);
/* operations on packet queue as a whole */
@@ -121,46 +117,38 @@
#define pktq_empty(pq) ((pq)->len == 0)
/* operations for single precedence queues */
-#define pktenq(pq, p) pktq_penq(((struct pktq *)pq), 0, (p))
-#define pktenq_head(pq, p) pktq_penq_head(((struct pktq *)pq), 0, (p))
-#define pktdeq(pq) pktq_pdeq(((struct pktq *)pq), 0)
-#define pktdeq_tail(pq) pktq_pdeq_tail(((struct pktq *)pq), 0)
-#define pktqinit(pq, len) pktq_init(((struct pktq *)pq), 1, len)
+#define pktenq(pq, p) bcm_pktq_penq(((struct pktq *)pq), 0, (p))
+#define pktenq_head(pq, p) bcm_pktq_penq_head(((struct pktq *)pq), 0, (p))
+#define pktdeq(pq) bcm_pktq_pdeq(((struct pktq *)pq), 0)
+#define pktdeq_tail(pq) bcm_pktq_pdeq_tail(((struct pktq *)pq), 0)
+#define pktqinit(pq, len) bcm_pktq_init(((struct pktq *)pq), 1, len)
- extern void pktq_init(struct pktq *pq, int num_prec, int max_len);
+extern void bcm_pktq_init(struct pktq *pq, int num_prec, int max_len);
/* prec_out may be NULL if caller is not interested in return value */
- extern struct sk_buff *pktq_peek_tail(struct pktq *pq, int *prec_out);
-#ifdef BRCM_FULLMAC
- extern void pktq_flush(struct pktq *pq, bool dir);
-#else
- extern void pktq_flush(struct pktq *pq, bool dir,
- ifpkt_cb_t fn, int arg);
-#endif
+extern struct sk_buff *bcm_pktq_peek_tail(struct pktq *pq, int *prec_out);
+extern void bcm_pktq_flush(struct pktq *pq, bool dir,
+ ifpkt_cb_t fn, void *arg);
/* externs */
/* packet */
- extern uint pktfrombuf(struct sk_buff *p,
- uint offset, int len, unsigned char *buf);
- extern uint pkttotlen(struct sk_buff *p);
+extern uint bcm_pktfrombuf(struct sk_buff *p,
+ uint offset, int len, unsigned char *buf);
+extern uint bcm_pkttotlen(struct sk_buff *p);
/* ethernet address */
- extern int bcm_ether_atoe(char *p, u8 *ea);
+extern int bcm_ether_atoe(char *p, u8 *ea);
/* ip address */
struct ipv4_addr;
extern char *bcm_ip_ntoa(struct ipv4_addr *ia, char *buf);
-/* variable access */
- extern char *getvar(char *vars, const char *name);
- extern int getintvar(char *vars, const char *name);
#ifdef BCMDBG
- extern void prpkt(const char *msg, struct sk_buff *p0);
+extern void bcm_prpkt(const char *msg, struct sk_buff *p0);
#else
-#define prpkt(a, b)
+#define bcm_prpkt(a, b)
#endif /* BCMDBG */
#define bcm_perf_enable()
-#define bcmstats(fmt)
#define bcmlog(fmt, a1, a2)
#define bcmdumplog(buf, size) (*buf = '\0')
#define bcmdumplogent(buf, idx) -1
@@ -241,107 +229,6 @@
/* ** driver/apps-shared section ** */
#define BCME_STRLEN 64 /* Max string length for BCM errors */
-#define VALID_BCMERROR(e) ((e <= 0) && (e >= BCME_LAST))
-
-/*
- * error codes could be added but the defined ones shouldn't be changed/deleted
- * these error codes are exposed to the user code
- * when ever a new error code is added to this list
- * please update errorstring table with the related error string and
- * update osl files with os specific errorcode map
-*/
-
-#define BCME_OK 0 /* Success */
-#define BCME_ERROR -1 /* Error generic */
-#define BCME_BADARG -2 /* Bad Argument */
-#define BCME_BADOPTION -3 /* Bad option */
-#define BCME_NOTUP -4 /* Not up */
-#define BCME_NOTDOWN -5 /* Not down */
-#define BCME_NOTAP -6 /* Not AP */
-#define BCME_NOTSTA -7 /* Not STA */
-#define BCME_BADKEYIDX -8 /* BAD Key Index */
-#define BCME_RADIOOFF -9 /* Radio Off */
-#define BCME_NOTBANDLOCKED -10 /* Not band locked */
-#define BCME_NOCLK -11 /* No Clock */
-#define BCME_BADRATESET -12 /* BAD Rate valueset */
-#define BCME_BADBAND -13 /* BAD Band */
-#define BCME_BUFTOOSHORT -14 /* Buffer too short */
-#define BCME_BUFTOOLONG -15 /* Buffer too long */
-#define BCME_BUSY -16 /* Busy */
-#define BCME_NOTASSOCIATED -17 /* Not Associated */
-#define BCME_BADSSIDLEN -18 /* Bad SSID len */
-#define BCME_OUTOFRANGECHAN -19 /* Out of Range Channel */
-#define BCME_BADCHAN -20 /* Bad Channel */
-#define BCME_BADADDR -21 /* Bad Address */
-#define BCME_NORESOURCE -22 /* Not Enough Resources */
-#define BCME_UNSUPPORTED -23 /* Unsupported */
-#define BCME_BADLEN -24 /* Bad length */
-#define BCME_NOTREADY -25 /* Not Ready */
-#define BCME_EPERM -26 /* Not Permitted */
-#define BCME_NOMEM -27 /* No Memory */
-#define BCME_ASSOCIATED -28 /* Associated */
-#define BCME_RANGE -29 /* Not In Range */
-#define BCME_NOTFOUND -30 /* Not Found */
-#define BCME_WME_NOT_ENABLED -31 /* WME Not Enabled */
-#define BCME_TSPEC_NOTFOUND -32 /* TSPEC Not Found */
-#define BCME_ACM_NOTSUPPORTED -33 /* ACM Not Supported */
-#define BCME_NOT_WME_ASSOCIATION -34 /* Not WME Association */
-#define BCME_SDIO_ERROR -35 /* SDIO Bus Error */
-#define BCME_DONGLE_DOWN -36 /* Dongle Not Accessible */
-#define BCME_VERSION -37 /* Incorrect version */
-#define BCME_TXFAIL -38 /* TX failure */
-#define BCME_RXFAIL -39 /* RX failure */
-#define BCME_NODEVICE -40 /* Device not present */
-#define BCME_NMODE_DISABLED -41 /* NMODE disabled */
-#define BCME_NONRESIDENT -42 /* access to nonresident overlay */
-#define BCME_LAST BCME_NONRESIDENT
-
-/* These are collection of BCME Error strings */
-#define BCMERRSTRINGTABLE { \
- "OK", \
- "Undefined error", \
- "Bad Argument", \
- "Bad Option", \
- "Not up", \
- "Not down", \
- "Not AP", \
- "Not STA", \
- "Bad Key Index", \
- "Radio Off", \
- "Not band locked", \
- "No clock", \
- "Bad Rate valueset", \
- "Bad Band", \
- "Buffer too short", \
- "Buffer too long", \
- "Busy", \
- "Not Associated", \
- "Bad SSID len", \
- "Out of Range Channel", \
- "Bad Channel", \
- "Bad Address", \
- "Not Enough Resources", \
- "Unsupported", \
- "Bad length", \
- "Not Ready", \
- "Not Permitted", \
- "No Memory", \
- "Associated", \
- "Not In Range", \
- "Not Found", \
- "WME Not Enabled", \
- "TSPEC Not Found", \
- "ACM Not Supported", \
- "Not WME Association", \
- "SDIO Bus Error", \
- "Dongle Not Accessible", \
- "Incorrect version", \
- "TX Failure", \
- "RX Failure", \
- "Device Not Present", \
- "NMODE Disabled", \
- "Nonresident overlay access", \
-}
#ifndef ABS
#define ABS(a) (((a) < 0) ? -(a) : (a))
@@ -358,16 +245,6 @@
#define REG_MAP(pa, size) (void *)(0)
#endif
-extern u32 g_assert_type;
-
-#if defined(BCMDBG_ASSERT)
-#define ASSERT(exp) \
- do { if (!(exp)) osl_assert(#exp, __FILE__, __LINE__); } while (0)
-extern void osl_assert(char *exp, char *file, int line);
-#else
-#define ASSERT(exp) do {} while (0)
-#endif /* defined(BCMDBG_ASSERT) */
-
/* register access macros */
#if defined(BCMSDIO)
#ifdef BRCM_FULLMAC
@@ -399,7 +276,7 @@
#define bcopy(src, dst, len) memcpy((dst), (src), (len))
/* register access macros */
-#ifndef IL_BIGENDIAN
+#ifndef __BIG_ENDIAN
#ifndef __mips__
#define R_REG(r) (\
SELECT_BUS_READ(sizeof(*(r)) == sizeof(u8) ? \
@@ -450,7 +327,7 @@
}, \
(OSL_WRITE_REG(r, v))); \
} while (0)
-#else /* IL_BIGENDIAN */
+#else /* __BIG_ENDIAN */
#define R_REG(r) (\
SELECT_BUS_READ( \
({ \
@@ -487,7 +364,7 @@
}, \
(OSL_WRITE_REG(r, v))); \
} while (0)
-#endif /* IL_BIGENDIAN */
+#endif /* __BIG_ENDIAN */
#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
@@ -590,8 +467,7 @@
/* externs */
/* crc */
- extern u8 hndcrc8(u8 *p, uint nbytes, u8 crc);
- extern u16 hndcrc16(u8 *p, uint nbytes, u16 crc);
+extern u8 bcm_crc8(u8 *p, uint nbytes, u8 crc);
/* format/print */
#if defined(BCMDBG)
extern int bcm_format_flags(const bcm_bit_desc_t *bd, u32 flags,
@@ -599,12 +475,9 @@
extern int bcm_format_hex(char *str, const void *bytes, int len);
#endif
extern char *bcm_chipname(uint chipid, char *buf, uint len);
- extern void prhex(const char *msg, unsigned char *buf, uint len);
extern bcm_tlv_t *bcm_parse_tlvs(void *buf, int buflen,
uint key);
-/* bcmerror */
- extern const char *bcmerrorstr(int bcmerror);
/* multi-bool data type: set of bools, mbool is true if any is set */
typedef u32 mbool;
diff --git a/drivers/staging/brcm80211/include/bcmwifi.h b/drivers/staging/brcm80211/include/bcmwifi.h
index 4a0f976..a573ebf 100644
--- a/drivers/staging/brcm80211/include/bcmwifi.h
+++ b/drivers/staging/brcm80211/include/bcmwifi.h
@@ -134,14 +134,14 @@
* combination could be legal given any set of circumstances.
* RETURNS: true is the chanspec is malformed, false if it looks good.
*/
-extern bool wf_chspec_malformed(chanspec_t chanspec);
+extern bool bcm_chspec_malformed(chanspec_t chanspec);
/*
* This function returns the channel number that control traffic is being sent on, for legacy
* channels this is just the channel number, for 40MHZ channels it is the upper or lowre 20MHZ
* sideband depending on the chanspec selected
*/
-extern u8 wf_chspec_ctlchan(chanspec_t chspec);
+extern u8 bcm_chspec_ctlchan(chanspec_t chspec);
/*
* Return the channel number for a given frequency and base frequency.
@@ -162,6 +162,6 @@
*
* Reference 802.11 REVma, section 17.3.8.3, and 802.11B section 18.4.6.2
*/
-extern int wf_mhz2channel(uint freq, uint start_factor);
+extern int bcm_mhz2channel(uint freq, uint start_factor);
#endif /* _bcmwifi_h_ */
diff --git a/drivers/staging/brcm80211/include/hnddma.h b/drivers/staging/brcm80211/include/hnddma.h
index 5d079e7..fbbcb9b 100644
--- a/drivers/staging/brcm80211/include/hnddma.h
+++ b/drivers/staging/brcm80211/include/hnddma.h
@@ -204,4 +204,23 @@
extern uint dma_addrwidth(si_t *sih, void *dmaregs);
void dma_walk_packets(struct hnddma_pub *dmah, void (*callback_fnc)
(void *pkt, void *arg_a), void *arg_a);
+
+/*
+ * DMA(Bug) on some chips seems to declare that the packet is ready, but the
+ * packet length is not updated yet (by DMA) on the expected time.
+ * Workaround is to hold processor till DMA updates the length, and stay off
+ * the bus to allow DMA update the length in buffer
+ */
+static inline void dma_spin_for_len(uint len, struct sk_buff *head)
+{
+#if defined(__mips__)
+ if (!len) {
+ while (!(len = *(u16 *) KSEG1ADDR(head->data)))
+ udelay(1);
+
+ *(u16 *) (head->data) = cpu_to_le16((u16) len);
+ }
+#endif /* defined(__mips__) */
+}
+
#endif /* _hnddma_h_ */
diff --git a/drivers/staging/brcm80211/include/hndpmu.h b/drivers/staging/brcm80211/include/hndpmu.h
deleted file mode 100644
index 3eea1f9..0000000
--- a/drivers/staging/brcm80211/include/hndpmu.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#ifndef _hndpmu_h_
-#define _hndpmu_h_
-
-#define SET_LDO_VOLTAGE_LDO1 1
-#define SET_LDO_VOLTAGE_LDO2 2
-#define SET_LDO_VOLTAGE_LDO3 3
-#define SET_LDO_VOLTAGE_PAREF 4
-#define SET_LDO_VOLTAGE_CLDO_PWM 5
-#define SET_LDO_VOLTAGE_CLDO_BURST 6
-#define SET_LDO_VOLTAGE_CBUCK_PWM 7
-#define SET_LDO_VOLTAGE_CBUCK_BURST 8
-#define SET_LDO_VOLTAGE_LNLDO1 9
-#define SET_LDO_VOLTAGE_LNLDO2_SEL 10
-
-extern void si_pmu_init(si_t *sih);
-extern void si_pmu_chip_init(si_t *sih);
-extern void si_pmu_pll_init(si_t *sih, u32 xtalfreq);
-extern void si_pmu_res_init(si_t *sih);
-extern void si_pmu_swreg_init(si_t *sih);
-
-extern u32 si_pmu_force_ilp(si_t *sih, bool force);
-
-extern u32 si_pmu_si_clock(si_t *sih);
-extern u32 si_pmu_cpu_clock(si_t *sih);
-extern u32 si_pmu_mem_clock(si_t *sih);
-extern u32 si_pmu_alp_clock(si_t *sih);
-extern u32 si_pmu_ilp_clock(si_t *sih);
-
-extern void si_pmu_set_switcher_voltage(si_t *sih,
- u8 bb_voltage, u8 rf_voltage);
-extern void si_pmu_set_ldo_voltage(si_t *sih, u8 ldo, u8 voltage);
-extern u16 si_pmu_fast_pwrup_delay(si_t *sih);
-extern void si_pmu_rcal(si_t *sih);
-extern void si_pmu_pllupd(si_t *sih);
-extern void si_pmu_spuravoid(si_t *sih, u8 spuravoid);
-
-extern bool si_pmu_is_otp_powered(si_t *sih);
-extern u32 si_pmu_measure_alpclk(si_t *sih);
-
-extern u32 si_pmu_chipcontrol(si_t *sih, uint reg, u32 mask, u32 val);
-extern u32 si_pmu_regcontrol(si_t *sih, uint reg, u32 mask, u32 val);
-extern u32 si_pmu_pllcontrol(si_t *sih, uint reg, u32 mask, u32 val);
-extern void si_pmu_pllupd(si_t *sih);
-extern void si_pmu_sprom_enable(si_t *sih, bool enable);
-
-extern void si_pmu_radio_enable(si_t *sih, bool enable);
-extern u32 si_pmu_waitforclk_on_backplane(si_t *sih, u32 clk, u32 delay);
-
-extern void si_pmu_otp_power(si_t *sih, bool on);
-extern void si_sdiod_drive_strength_init(si_t *sih, u32 drivestrength);
-
-#endif /* _hndpmu_h_ */
diff --git a/drivers/staging/brcm80211/util/pci_core.h b/drivers/staging/brcm80211/include/pci_core.h
similarity index 100%
rename from drivers/staging/brcm80211/util/pci_core.h
rename to drivers/staging/brcm80211/include/pci_core.h
diff --git a/drivers/staging/brcm80211/include/pcicfg.h b/drivers/staging/brcm80211/include/pcicfg.h
index 675554a..d0c617a 100644
--- a/drivers/staging/brcm80211/include/pcicfg.h
+++ b/drivers/staging/brcm80211/include/pcicfg.h
@@ -17,508 +17,34 @@
#ifndef _h_pcicfg_
#define _h_pcicfg_
-/* The following inside ifndef's so we don't collide with NTDDK.H */
-#ifndef PCI_MAX_BUS
-#define PCI_MAX_BUS 0x100
-#endif
-#ifndef PCI_MAX_DEVICES
-#define PCI_MAX_DEVICES 0x20
-#endif
-#ifndef PCI_MAX_FUNCTION
-#define PCI_MAX_FUNCTION 0x8
-#endif
+#include <linux/pci_regs.h>
-#ifndef PCI_INVALID_VENDORID
-#define PCI_INVALID_VENDORID 0xffff
-#endif
-#ifndef PCI_INVALID_DEVICEID
-#define PCI_INVALID_DEVICEID 0xffff
-#endif
-
-/* Convert between bus-slot-function-register and config addresses */
-
-#define PCICFG_BUS_SHIFT 16 /* Bus shift */
-#define PCICFG_SLOT_SHIFT 11 /* Slot shift */
-#define PCICFG_FUN_SHIFT 8 /* Function shift */
-#define PCICFG_OFF_SHIFT 0 /* Register shift */
-
-#define PCICFG_BUS_MASK 0xff /* Bus mask */
-#define PCICFG_SLOT_MASK 0x1f /* Slot mask */
-#define PCICFG_FUN_MASK 7 /* Function mask */
-#define PCICFG_OFF_MASK 0xff /* Bus mask */
-
-#define PCI_CONFIG_ADDR(b, s, f, o) \
- ((((b) & PCICFG_BUS_MASK) << PCICFG_BUS_SHIFT) \
- | (((s) & PCICFG_SLOT_MASK) << PCICFG_SLOT_SHIFT) \
- | (((f) & PCICFG_FUN_MASK) << PCICFG_FUN_SHIFT) \
- | (((o) & PCICFG_OFF_MASK) << PCICFG_OFF_SHIFT))
-
-#define PCI_CONFIG_BUS(a) (((a) >> PCICFG_BUS_SHIFT) & PCICFG_BUS_MASK)
-#define PCI_CONFIG_SLOT(a) (((a) >> PCICFG_SLOT_SHIFT) & PCICFG_SLOT_MASK)
-#define PCI_CONFIG_FUN(a) (((a) >> PCICFG_FUN_SHIFT) & PCICFG_FUN_MASK)
-#define PCI_CONFIG_OFF(a) (((a) >> PCICFG_OFF_SHIFT) & PCICFG_OFF_MASK)
-
-/* PCIE Config space accessing MACROS */
-
-#define PCIECFG_BUS_SHIFT 24 /* Bus shift */
-#define PCIECFG_SLOT_SHIFT 19 /* Slot/Device shift */
-#define PCIECFG_FUN_SHIFT 16 /* Function shift */
-#define PCIECFG_OFF_SHIFT 0 /* Register shift */
-
-#define PCIECFG_BUS_MASK 0xff /* Bus mask */
-#define PCIECFG_SLOT_MASK 0x1f /* Slot/Device mask */
-#define PCIECFG_FUN_MASK 7 /* Function mask */
-#define PCIECFG_OFF_MASK 0xfff /* Register mask */
-
-#define PCIE_CONFIG_ADDR(b, s, f, o) \
- ((((b) & PCIECFG_BUS_MASK) << PCIECFG_BUS_SHIFT) \
- | (((s) & PCIECFG_SLOT_MASK) << PCIECFG_SLOT_SHIFT) \
- | (((f) & PCIECFG_FUN_MASK) << PCIECFG_FUN_SHIFT) \
- | (((o) & PCIECFG_OFF_MASK) << PCIECFG_OFF_SHIFT))
-
-#define PCIE_CONFIG_BUS(a) (((a) >> PCIECFG_BUS_SHIFT) & PCIECFG_BUS_MASK)
-#define PCIE_CONFIG_SLOT(a) (((a) >> PCIECFG_SLOT_SHIFT) & PCIECFG_SLOT_MASK)
-#define PCIE_CONFIG_FUN(a) (((a) >> PCIECFG_FUN_SHIFT) & PCIECFG_FUN_MASK)
-#define PCIE_CONFIG_OFF(a) (((a) >> PCIECFG_OFF_SHIFT) & PCIECFG_OFF_MASK)
-
-/* The actual config space */
-
-#define PCI_BAR_MAX 6
-
-#define PCI_ROM_BAR 8
-
-#define PCR_RSVDA_MAX 2
-
-/* Bits in PCI bars' flags */
-
-#define PCIBAR_FLAGS 0xf
-#define PCIBAR_IO 0x1
-#define PCIBAR_MEM1M 0x2
-#define PCIBAR_MEM64 0x4
-#define PCIBAR_PREFETCH 0x8
-#define PCIBAR_MEM32_MASK 0xFFFFFF80
-
-/* pci config status reg has a bit to indicate that capability ptr is present */
-
-#define PCI_CAPPTR_PRESENT 0x0010
-
-typedef struct _pci_config_regs {
- u16 vendor;
- u16 device;
- u16 command;
- u16 status;
- u8 rev_id;
- u8 prog_if;
- u8 sub_class;
- u8 base_class;
- u8 cache_line_size;
- u8 latency_timer;
- u8 header_type;
- u8 bist;
- u32 base[PCI_BAR_MAX];
- u32 cardbus_cis;
- u16 subsys_vendor;
- u16 subsys_id;
- u32 baserom;
- u32 rsvd_a[PCR_RSVDA_MAX];
- u8 int_line;
- u8 int_pin;
- u8 min_gnt;
- u8 max_lat;
- u8 dev_dep[192];
-} pci_config_regs;
-
-#define SZPCR (sizeof (pci_config_regs))
-#define MINSZPCR 64 /* offsetof (dev_dep[0] */
-
-/* A structure for the config registers is nice, but in most
- * systems the config space is not memory mapped, so we need
- * field offsetts. :-(
- */
-#define PCI_CFG_VID 0
-#define PCI_CFG_DID 2
-#define PCI_CFG_CMD 4
-#define PCI_CFG_STAT 6
-#define PCI_CFG_REV 8
-#define PCI_CFG_PROGIF 9
-#define PCI_CFG_SUBCL 0xa
-#define PCI_CFG_BASECL 0xb
-#define PCI_CFG_CLSZ 0xc
-#define PCI_CFG_LATTIM 0xd
-#define PCI_CFG_HDR 0xe
-#define PCI_CFG_BIST 0xf
-#define PCI_CFG_BAR0 0x10
-#define PCI_CFG_BAR1 0x14
-#define PCI_CFG_BAR2 0x18
-#define PCI_CFG_BAR3 0x1c
-#define PCI_CFG_BAR4 0x20
-#define PCI_CFG_BAR5 0x24
-#define PCI_CFG_CIS 0x28
-#define PCI_CFG_SVID 0x2c
-#define PCI_CFG_SSID 0x2e
-#define PCI_CFG_ROMBAR 0x30
-#define PCI_CFG_CAPPTR 0x34
-#define PCI_CFG_INT 0x3c
-#define PCI_CFG_PIN 0x3d
-#define PCI_CFG_MINGNT 0x3e
-#define PCI_CFG_MAXLAT 0x3f
-
-/* Classes and subclasses */
-
-typedef enum {
- PCI_CLASS_OLD = 0,
- PCI_CLASS_DASDI,
- PCI_CLASS_NET,
- PCI_CLASS_DISPLAY,
- PCI_CLASS_MMEDIA,
- PCI_CLASS_MEMORY,
- PCI_CLASS_BRIDGE,
- PCI_CLASS_COMM,
- PCI_CLASS_BASE,
- PCI_CLASS_INPUT,
- PCI_CLASS_DOCK,
- PCI_CLASS_CPU,
- PCI_CLASS_SERIAL,
- PCI_CLASS_INTELLIGENT = 0xe,
- PCI_CLASS_SATELLITE,
- PCI_CLASS_CRYPT,
- PCI_CLASS_DSP,
- PCI_CLASS_XOR = 0xfe
-} pci_classes;
-
-typedef enum {
- PCI_DASDI_SCSI,
- PCI_DASDI_IDE,
- PCI_DASDI_FLOPPY,
- PCI_DASDI_IPI,
- PCI_DASDI_RAID,
- PCI_DASDI_OTHER = 0x80
-} pci_dasdi_subclasses;
-
-typedef enum {
- PCI_NET_ETHER,
- PCI_NET_TOKEN,
- PCI_NET_FDDI,
- PCI_NET_ATM,
- PCI_NET_OTHER = 0x80
-} pci_net_subclasses;
-
-typedef enum {
- PCI_DISPLAY_VGA,
- PCI_DISPLAY_XGA,
- PCI_DISPLAY_3D,
- PCI_DISPLAY_OTHER = 0x80
-} pci_display_subclasses;
-
-typedef enum {
- PCI_MMEDIA_VIDEO,
- PCI_MMEDIA_AUDIO,
- PCI_MMEDIA_PHONE,
- PCI_MEDIA_OTHER = 0x80
-} pci_mmedia_subclasses;
-
-typedef enum {
- PCI_MEMORY_RAM,
- PCI_MEMORY_FLASH,
- PCI_MEMORY_OTHER = 0x80
-} pci_memory_subclasses;
-
-typedef enum {
- PCI_BRIDGE_HOST,
- PCI_BRIDGE_ISA,
- PCI_BRIDGE_EISA,
- PCI_BRIDGE_MC,
- PCI_BRIDGE_PCI,
- PCI_BRIDGE_PCMCIA,
- PCI_BRIDGE_NUBUS,
- PCI_BRIDGE_CARDBUS,
- PCI_BRIDGE_RACEWAY,
- PCI_BRIDGE_OTHER = 0x80
-} pci_bridge_subclasses;
-
-typedef enum {
- PCI_COMM_UART,
- PCI_COMM_PARALLEL,
- PCI_COMM_MULTIUART,
- PCI_COMM_MODEM,
- PCI_COMM_OTHER = 0x80
-} pci_comm_subclasses;
-
-typedef enum {
- PCI_BASE_PIC,
- PCI_BASE_DMA,
- PCI_BASE_TIMER,
- PCI_BASE_RTC,
- PCI_BASE_PCI_HOTPLUG,
- PCI_BASE_OTHER = 0x80
-} pci_base_subclasses;
-
-typedef enum {
- PCI_INPUT_KBD,
- PCI_INPUT_PEN,
- PCI_INPUT_MOUSE,
- PCI_INPUT_SCANNER,
- PCI_INPUT_GAMEPORT,
- PCI_INPUT_OTHER = 0x80
-} pci_input_subclasses;
-
-typedef enum {
- PCI_DOCK_GENERIC,
- PCI_DOCK_OTHER = 0x80
-} pci_dock_subclasses;
-
-typedef enum {
- PCI_CPU_386,
- PCI_CPU_486,
- PCI_CPU_PENTIUM,
- PCI_CPU_ALPHA = 0x10,
- PCI_CPU_POWERPC = 0x20,
- PCI_CPU_MIPS = 0x30,
- PCI_CPU_COPROC = 0x40,
- PCI_CPU_OTHER = 0x80
-} pci_cpu_subclasses;
-
-typedef enum {
- PCI_SERIAL_IEEE1394,
- PCI_SERIAL_ACCESS,
- PCI_SERIAL_SSA,
- PCI_SERIAL_USB,
- PCI_SERIAL_FIBER,
- PCI_SERIAL_SMBUS,
- PCI_SERIAL_OTHER = 0x80
-} pci_serial_subclasses;
-
-typedef enum {
- PCI_INTELLIGENT_I2O
-} pci_intelligent_subclasses;
-
-typedef enum {
- PCI_SATELLITE_TV,
- PCI_SATELLITE_AUDIO,
- PCI_SATELLITE_VOICE,
- PCI_SATELLITE_DATA,
- PCI_SATELLITE_OTHER = 0x80
-} pci_satellite_subclasses;
-
-typedef enum {
- PCI_CRYPT_NETWORK,
- PCI_CRYPT_ENTERTAINMENT,
- PCI_CRYPT_OTHER = 0x80
-} pci_crypt_subclasses;
-
-typedef enum {
- PCI_DSP_DPIO,
- PCI_DSP_OTHER = 0x80
-} pci_dsp_subclasses;
-
-typedef enum {
- PCI_XOR_QDMA,
- PCI_XOR_OTHER = 0x80
-} pci_xor_subclasses;
-
-/* Header types */
-#define PCI_HEADER_MULTI 0x80
-#define PCI_HEADER_MASK 0x7f
-typedef enum {
- PCI_HEADER_NORMAL,
- PCI_HEADER_BRIDGE,
- PCI_HEADER_CARDBUS
-} pci_header_types;
-
-/* Overlay for a PCI-to-PCI bridge */
-
-#define PPB_RSVDA_MAX 2
-#define PPB_RSVDD_MAX 8
-
-typedef struct _ppb_config_regs {
- u16 vendor;
- u16 device;
- u16 command;
- u16 status;
- u8 rev_id;
- u8 prog_if;
- u8 sub_class;
- u8 base_class;
- u8 cache_line_size;
- u8 latency_timer;
- u8 header_type;
- u8 bist;
- u32 rsvd_a[PPB_RSVDA_MAX];
- u8 prim_bus;
- u8 sec_bus;
- u8 sub_bus;
- u8 sec_lat;
- u8 io_base;
- u8 io_lim;
- u16 sec_status;
- u16 mem_base;
- u16 mem_lim;
- u16 pf_mem_base;
- u16 pf_mem_lim;
- u32 pf_mem_base_hi;
- u32 pf_mem_lim_hi;
- u16 io_base_hi;
- u16 io_lim_hi;
- u16 subsys_vendor;
- u16 subsys_id;
- u32 rsvd_b;
- u8 rsvd_c;
- u8 int_pin;
- u16 bridge_ctrl;
- u8 chip_ctrl;
- u8 diag_ctrl;
- u16 arb_ctrl;
- u32 rsvd_d[PPB_RSVDD_MAX];
- u8 dev_dep[192];
-} ppb_config_regs;
-
-/* PCI CAPABILITY DEFINES */
-#define PCI_CAP_POWERMGMTCAP_ID 0x01
-#define PCI_CAP_MSICAP_ID 0x05
-#define PCI_CAP_VENDSPEC_ID 0x09
-#define PCI_CAP_PCIECAP_ID 0x10
-
-/* Data structure to define the Message Signalled Interrupt facility
- * Valid for PCI and PCIE configurations
- */
-typedef struct _pciconfig_cap_msi {
- u8 capID;
- u8 nextptr;
- u16 msgctrl;
- u32 msgaddr;
-} pciconfig_cap_msi;
-
-/* Data structure to define the Power management facility
- * Valid for PCI and PCIE configurations
- */
-typedef struct _pciconfig_cap_pwrmgmt {
- u8 capID;
- u8 nextptr;
- u16 pme_cap;
- u16 pme_sts_ctrl;
- u8 pme_bridge_ext;
- u8 data;
-} pciconfig_cap_pwrmgmt;
-
-#define PME_CAP_PM_STATES (0x1f << 27) /* Bits 31:27 states that can generate PME */
-#define PME_CSR_OFFSET 0x4 /* 4-bytes offset */
-#define PME_CSR_PME_EN (1 << 8) /* Bit 8 Enable generating of PME */
-#define PME_CSR_PME_STAT (1 << 15) /* Bit 15 PME got asserted */
-
-/* Data structure to define the PCIE capability */
-typedef struct _pciconfig_cap_pcie {
- u8 capID;
- u8 nextptr;
- u16 pcie_cap;
- u32 dev_cap;
- u16 dev_ctrl;
- u16 dev_status;
- u32 link_cap;
- u16 link_ctrl;
- u16 link_status;
- u32 slot_cap;
- u16 slot_ctrl;
- u16 slot_status;
- u16 root_ctrl;
- u16 root_cap;
- u32 root_status;
-} pciconfig_cap_pcie;
-
-/* PCIE Enhanced CAPABILITY DEFINES */
-#define PCIE_EXTCFG_OFFSET 0x100
-#define PCIE_ADVERRREP_CAPID 0x0001
-#define PCIE_VC_CAPID 0x0002
-#define PCIE_DEVSNUM_CAPID 0x0003
-#define PCIE_PWRBUDGET_CAPID 0x0004
-
-/* PCIE Extended configuration */
-#define PCIE_ADV_CORR_ERR_MASK 0x114
-#define CORR_ERR_RE (1 << 0) /* Receiver */
-#define CORR_ERR_BT (1 << 6) /* Bad TLP */
-#define CORR_ERR_BD (1 << 7) /* Bad DLLP */
-#define CORR_ERR_RR (1 << 8) /* REPLAY_NUM rollover */
-#define CORR_ERR_RT (1 << 12) /* Reply timer timeout */
-#define ALL_CORR_ERRORS (CORR_ERR_RE | CORR_ERR_BT | CORR_ERR_BD | \
- CORR_ERR_RR | CORR_ERR_RT)
-
-/* PCIE Root Control Register bits (Host mode only) */
-#define PCIE_RC_CORR_SERR_EN 0x0001
-#define PCIE_RC_NONFATAL_SERR_EN 0x0002
-#define PCIE_RC_FATAL_SERR_EN 0x0004
-#define PCIE_RC_PME_INT_EN 0x0008
-#define PCIE_RC_CRS_EN 0x0010
-
-/* PCIE Root Capability Register bits (Host mode only) */
-#define PCIE_RC_CRS_VISIBILITY 0x0001
-
-/* Header to define the PCIE specific capabilities in the extended config space */
-typedef struct _pcie_enhanced_caphdr {
- u16 capID;
- u16 cap_ver:4;
- u16 next_ptr:12;
-} pcie_enhanced_caphdr;
+/* PCI configuration address space size */
+#define PCI_SZPCR 256
/* Everything below is BRCM HND proprietary */
/* Brcm PCI configuration registers */
-#define cap_list rsvd_a[0]
-#define bar0_window dev_dep[0x80 - 0x40]
-#define bar1_window dev_dep[0x84 - 0x40]
-#define sprom_control dev_dep[0x88 - 0x40]
-#define PCI_BAR0_WIN 0x80 /* backplane address space accessed by BAR0 */
-#define PCI_BAR1_WIN 0x84 /* backplane address space accessed by BAR1 */
-#define PCI_SPROM_CONTROL 0x88 /* sprom property control */
-#define PCI_BAR1_CONTROL 0x8c /* BAR1 region burst control */
-#define PCI_INT_STATUS 0x90 /* PCI and other cores interrupts */
-#define PCI_INT_MASK 0x94 /* mask of PCI and other cores interrupts */
-#define PCI_TO_SB_MB 0x98 /* signal backplane interrupts */
-#define PCI_BACKPLANE_ADDR 0xa0 /* address an arbitrary location on the system backplane */
-#define PCI_BACKPLANE_DATA 0xa4 /* data at the location specified by above address */
-#define PCI_CLK_CTL_ST 0xa8 /* pci config space clock control/status (>=rev14) */
-#define PCI_BAR0_WIN2 0xac /* backplane address space accessed by second 4KB of BAR0 */
-#define PCI_GPIO_IN 0xb0 /* pci config space gpio input (>=rev3) */
-#define PCI_GPIO_OUT 0xb4 /* pci config space gpio output (>=rev3) */
-#define PCI_GPIO_OUTEN 0xb8 /* pci config space gpio output enable (>=rev3) */
+#define PCI_BAR0_WIN 0x80 /* backplane address space accessed by BAR0 */
+#define PCI_SPROM_CONTROL 0x88 /* sprom property control */
+#define PCI_INT_MASK 0x94 /* mask of PCI and other cores interrupts */
+#define PCI_SBIM_SHIFT 8 /* backplane core interrupt mask bits offset */
+#define PCI_BAR0_WIN2 0xac /* backplane address space accessed by second 4KB of BAR0 */
+#define PCI_GPIO_IN 0xb0 /* pci config space gpio input (>=rev3) */
+#define PCI_GPIO_OUT 0xb4 /* pci config space gpio output (>=rev3) */
+#define PCI_GPIO_OUTEN 0xb8 /* pci config space gpio output enable (>=rev3) */
-#define PCI_BAR0_SHADOW_OFFSET (2 * 1024) /* bar0 + 2K accesses sprom shadow (in pci core) */
-#define PCI_BAR0_SPROM_OFFSET (4 * 1024) /* bar0 + 4K accesses external sprom */
-#define PCI_BAR0_PCIREGS_OFFSET (6 * 1024) /* bar0 + 6K accesses pci core registers */
-#define PCI_BAR0_PCISBR_OFFSET (4 * 1024) /* pci core SB registers are at the end of the
+#define PCI_BAR0_SPROM_OFFSET (4 * 1024) /* bar0 + 4K accesses external sprom */
+#define PCI_BAR0_PCIREGS_OFFSET (6 * 1024) /* bar0 + 6K accesses pci core registers */
+#define PCI_BAR0_PCISBR_OFFSET (4 * 1024) /* pci core SB registers are at the end of the
* 8KB window, so their address is the "regular"
* address plus 4K
*/
#define PCI_BAR0_WINSZ (16 * 1024) /* bar0 window size Match with corerev 13 */
/* On pci corerev >= 13 and all pcie, the bar0 is now 16KB and it maps: */
-#define PCI_16KB0_PCIREGS_OFFSET (8 * 1024) /* bar0 + 8K accesses pci/pcie core registers */
-#define PCI_16KB0_CCREGS_OFFSET (12 * 1024) /* bar0 + 12K accesses chipc core registers */
-#define PCI_16KBB0_WINSZ (16 * 1024) /* bar0 window size */
+#define PCI_16KB0_PCIREGS_OFFSET (8 * 1024) /* bar0 + 8K accesses pci/pcie core registers */
+#define PCI_16KB0_CCREGS_OFFSET (12 * 1024) /* bar0 + 12K accesses chipc core registers */
-/* On AI chips we have a second window to map DMP regs are mapped: */
-#define PCI_16KB0_WIN2_OFFSET (4 * 1024) /* bar0 + 4K is "Window 2" */
+#define PCI_SBIM_STATUS_SERR 0x4 /* backplane SBErr interrupt status */
-/* PCI_INT_STATUS */
-#define PCI_SBIM_STATUS_SERR 0x4 /* backplane SBErr interrupt status */
-
-/* PCI_INT_MASK */
-#define PCI_SBIM_SHIFT 8 /* backplane core interrupt mask bits offset */
-#define PCI_SBIM_MASK 0xff00 /* backplane core interrupt mask */
-#define PCI_SBIM_MASK_SERR 0x4 /* backplane SBErr interrupt mask */
-
-/* PCI_SPROM_CONTROL */
-#define SPROM_SZ_MSK 0x02 /* SPROM Size Mask */
-#define SPROM_LOCKED 0x08 /* SPROM Locked */
-#define SPROM_BLANK 0x04 /* indicating a blank SPROM */
-#define SPROM_WRITEEN 0x10 /* SPROM write enable */
-#define SPROM_BOOTROM_WE 0x20 /* external bootrom write enable */
-#define SPROM_BACKPLANE_EN 0x40 /* Enable indirect backplane access */
-#define SPROM_OTPIN_USE 0x80 /* device OTP In use */
-
-/* Bits in PCI command and status regs */
-#define PCI_CMD_IO 0x00000001 /* I/O enable */
-#define PCI_CMD_MEMORY 0x00000002 /* Memory enable */
-#define PCI_CMD_MASTER 0x00000004 /* Master enable */
-#define PCI_CMD_SPECIAL 0x00000008 /* Special cycles enable */
-#define PCI_CMD_INVALIDATE 0x00000010 /* Invalidate? */
-#define PCI_CMD_VGA_PAL 0x00000040 /* VGA Palate */
-#define PCI_STAT_TA 0x08000000 /* target abort status */
#endif /* _h_pcicfg_ */
diff --git a/drivers/staging/brcm80211/include/qmath.h b/drivers/staging/brcm80211/include/qmath.h
deleted file mode 100644
index 5f525db..0000000
--- a/drivers/staging/brcm80211/include/qmath.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#ifndef __QMATH_H__
-#define __QMATH_H__
-
-s16 qm_sat32(s32 op);
-
-s32 qm_mul321616(s16 op1, s16 op2);
-
-s16 qm_mul16(s16 op1, s16 op2);
-
-s32 qm_muls321616(s16 op1, s16 op2);
-
-u16 qm_mulu16(u16 op1, u16 op2);
-
-s16 qm_muls16(s16 op1, s16 op2);
-
-s32 qm_add32(s32 op1, s32 op2);
-
-s16 qm_add16(s16 op1, s16 op2);
-
-s16 qm_sub16(s16 op1, s16 op2);
-
-s32 qm_sub32(s32 op1, s32 op2);
-
-s32 qm_mac321616(s32 acc, s16 op1, s16 op2);
-
-s32 qm_shl32(s32 op, int shift);
-
-s32 qm_shr32(s32 op, int shift);
-
-s16 qm_shl16(s16 op, int shift);
-
-s16 qm_shr16(s16 op, int shift);
-
-s16 qm_norm16(s16 op);
-
-s16 qm_norm32(s32 op);
-
-s16 qm_div_s(s16 num, s16 denom);
-
-s16 qm_abs16(s16 op);
-
-s16 qm_div16(s16 num, s16 denom, s16 *qQuotient);
-
-s32 qm_abs32(s32 op);
-
-s16 qm_div163232(s32 num, s32 denom, s16 *qquotient);
-
-s32 qm_mul323216(s32 op1, s16 op2);
-
-s32 qm_mulsu321616(s16 op1, u16 op2);
-
-s32 qm_muls323216(s32 op1, s16 op2);
-
-s32 qm_mul32(s32 a, s32 b);
-
-s32 qm_muls32(s32 a, s32 b);
-
-void qm_log10(s32 N, s16 qN, s16 *log10N, s16 *qLog10N);
-
-void qm_1byN(s32 N, s16 qN, s32 *result, s16 *qResult);
-
-#endif /* #ifndef __QMATH_H__ */
diff --git a/drivers/staging/brcm80211/include/sbchipc.h b/drivers/staging/brcm80211/include/sbchipc.h
index f608894..8c01c63 100644
--- a/drivers/staging/brcm80211/include/sbchipc.h
+++ b/drivers/staging/brcm80211/include/sbchipc.h
@@ -225,7 +225,7 @@
#endif /* _LANGUAGE_ASSEMBLY */
-#if defined(IL_BIGENDIAN) && defined(BCMHND74K)
+#if defined(__BIG_ENDIAN) && defined(BCMHND74K)
/* Selective swapped defines for those registers we need in
* big-endian code.
*/
@@ -234,14 +234,14 @@
#define CC_CHIPST 0x28
#define CC_EROMPTR 0xf8
-#else /* !IL_BIGENDIAN || !BCMHND74K */
+#else /* !__BIG_ENDIAN || !BCMHND74K */
#define CC_CHIPID 0
#define CC_CAPABILITIES 4
#define CC_CHIPST 0x2c
#define CC_EROMPTR 0xfc
-#endif /* IL_BIGENDIAN && BCMHND74K */
+#endif /* __BIG_ENDIAN && BCMHND74K */
#define CC_OTPST 0x10
#define CC_JTAGCMD 0x30
diff --git a/drivers/staging/brcm80211/include/siutils.h b/drivers/staging/brcm80211/include/siutils.h
deleted file mode 100644
index 101e9a4..0000000
--- a/drivers/staging/brcm80211/include/siutils.h
+++ /dev/null
@@ -1,361 +0,0 @@
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#ifndef _siutils_h_
-#define _siutils_h_
-
-#include <hndsoc.h>
-
-/*
- * Data structure to export all chip specific common variables
- * public (read-only) portion of siutils handle returned by si_attach()
- */
-struct si_pub {
- uint socitype; /* SOCI_SB, SOCI_AI */
-
- uint bustype; /* SI_BUS, PCI_BUS */
- uint buscoretype; /* PCI_CORE_ID, PCIE_CORE_ID, PCMCIA_CORE_ID */
- uint buscorerev; /* buscore rev */
- uint buscoreidx; /* buscore index */
- int ccrev; /* chip common core rev */
- u32 cccaps; /* chip common capabilities */
- u32 cccaps_ext; /* chip common capabilities extension */
- int pmurev; /* pmu core rev */
- u32 pmucaps; /* pmu capabilities */
- uint boardtype; /* board type */
- uint boardvendor; /* board vendor */
- uint boardflags; /* board flags */
- uint boardflags2; /* board flags2 */
- uint chip; /* chip number */
- uint chiprev; /* chip revision */
- uint chippkg; /* chip package option */
- u32 chipst; /* chip status */
- bool issim; /* chip is in simulation or emulation */
- uint socirev; /* SOC interconnect rev */
- bool pci_pr32414;
-
-};
-
-/* for HIGH_ONLY driver, the si_t must be writable to allow states sync from BMAC to HIGH driver
- * for monolithic driver, it is readonly to prevent accident change
- */
-typedef const struct si_pub si_t;
-
-/*
- * Many of the routines below take an 'sih' handle as their first arg.
- * Allocate this by calling si_attach(). Free it by calling si_detach().
- * At any one time, the sih is logically focused on one particular si core
- * (the "current core").
- * Use si_setcore() or si_setcoreidx() to change the association to another core.
- */
-
-#define BADIDX (SI_MAXCORES + 1)
-
-/* clkctl xtal what flags */
-#define XTAL 0x1 /* primary crystal oscillator (2050) */
-#define PLL 0x2 /* main chip pll */
-
-/* clkctl clk mode */
-#define CLK_FAST 0 /* force fast (pll) clock */
-#define CLK_DYNAMIC 2 /* enable dynamic clock control */
-
-/* GPIO usage priorities */
-#define GPIO_DRV_PRIORITY 0 /* Driver */
-#define GPIO_APP_PRIORITY 1 /* Application */
-#define GPIO_HI_PRIORITY 2 /* Highest priority. Ignore GPIO reservation */
-
-/* GPIO pull up/down */
-#define GPIO_PULLUP 0
-#define GPIO_PULLDN 1
-
-/* GPIO event regtype */
-#define GPIO_REGEVT 0 /* GPIO register event */
-#define GPIO_REGEVT_INTMSK 1 /* GPIO register event int mask */
-#define GPIO_REGEVT_INTPOL 2 /* GPIO register event int polarity */
-
-/* device path */
-#define SI_DEVPATH_BUFSZ 16 /* min buffer size in bytes */
-
-/* SI routine enumeration: to be used by update function with multiple hooks */
-#define SI_DOATTACH 1
-#define SI_PCIDOWN 2
-#define SI_PCIUP 3
-
-#define ISSIM_ENAB(sih) 0
-
-/* PMU clock/power control */
-#if defined(BCMPMUCTL)
-#define PMUCTL_ENAB(sih) (BCMPMUCTL)
-#else
-#define PMUCTL_ENAB(sih) ((sih)->cccaps & CC_CAP_PMU)
-#endif
-
-/* chipcommon clock/power control (exclusive with PMU's) */
-#if defined(BCMPMUCTL) && BCMPMUCTL
-#define CCCTL_ENAB(sih) (0)
-#define CCPLL_ENAB(sih) (0)
-#else
-#define CCCTL_ENAB(sih) ((sih)->cccaps & CC_CAP_PWR_CTL)
-#define CCPLL_ENAB(sih) ((sih)->cccaps & CC_CAP_PLL_MASK)
-#endif
-
-typedef void (*gpio_handler_t) (u32 stat, void *arg);
-
-/* External PA enable mask */
-#define GPIO_CTRL_EPA_EN_MASK 0x40
-
-/* === exported functions === */
-extern si_t *si_attach(uint pcidev, void *regs, uint bustype,
- void *sdh, char **vars, uint *varsz);
-
-extern void si_detach(si_t *sih);
-extern bool si_pci_war16165(si_t *sih);
-
-extern uint si_coreid(si_t *sih);
-extern uint si_flag(si_t *sih);
-extern uint si_coreidx(si_t *sih);
-extern uint si_corerev(si_t *sih);
-extern uint si_corereg(si_t *sih, uint coreidx, uint regoff, uint mask,
- uint val);
-extern void si_write_wrapperreg(si_t *sih, u32 offset, u32 val);
-extern u32 si_core_cflags(si_t *sih, u32 mask, u32 val);
-extern u32 si_core_sflags(si_t *sih, u32 mask, u32 val);
-extern bool si_iscoreup(si_t *sih);
-extern uint si_findcoreidx(si_t *sih, uint coreid, uint coreunit);
-#ifndef BCMSDIO
-extern void *si_setcoreidx(si_t *sih, uint coreidx);
-#endif
-extern void *si_setcore(si_t *sih, uint coreid, uint coreunit);
-extern void *si_switch_core(si_t *sih, uint coreid, uint *origidx,
- uint *intr_val);
-extern void si_restore_core(si_t *sih, uint coreid, uint intr_val);
-extern void si_core_reset(si_t *sih, u32 bits, u32 resetbits);
-extern void si_core_disable(si_t *sih, u32 bits);
-extern u32 si_alp_clock(si_t *sih);
-extern u32 si_ilp_clock(si_t *sih);
-extern void si_pci_setup(si_t *sih, uint coremask);
-extern void si_setint(si_t *sih, int siflag);
-extern bool si_backplane64(si_t *sih);
-extern void si_register_intr_callback(si_t *sih, void *intrsoff_fn,
- void *intrsrestore_fn,
- void *intrsenabled_fn, void *intr_arg);
-extern void si_deregister_intr_callback(si_t *sih);
-extern void si_clkctl_init(si_t *sih);
-extern u16 si_clkctl_fast_pwrup_delay(si_t *sih);
-extern bool si_clkctl_cc(si_t *sih, uint mode);
-extern int si_clkctl_xtal(si_t *sih, uint what, bool on);
-extern bool si_deviceremoved(si_t *sih);
-extern u32 si_socram_size(si_t *sih);
-
-extern void si_watchdog(si_t *sih, uint ticks);
-extern u32 si_gpiocontrol(si_t *sih, u32 mask, u32 val,
- u8 priority);
-
-#ifdef BCMSDIO
-extern void si_sdio_init(si_t *sih);
-#endif
-
-#define si_eci(sih) 0
-#define si_eci_init(sih) (0)
-#define si_eci_notify_bt(sih, type, val) (0)
-#define si_seci(sih) 0
-
-/* OTP status */
-extern bool si_is_otp_disabled(si_t *sih);
-extern bool si_is_otp_powered(si_t *sih);
-extern void si_otp_power(si_t *sih, bool on);
-
-/* SPROM availability */
-extern bool si_is_sprom_available(si_t *sih);
-#ifdef SI_SPROM_PROBE
-extern void si_sprom_init(si_t *sih);
-#endif /* SI_SPROM_PROBE */
-
-#define SI_ERROR(args)
-
-#ifdef BCMDBG
-#define SI_MSG(args) printk args
-#else
-#define SI_MSG(args)
-#endif /* BCMDBG */
-
-/* Define SI_VMSG to printf for verbose debugging, but don't check it in */
-#define SI_VMSG(args)
-
-#define IS_SIM(chippkg) ((chippkg == HDLSIM_PKG_ID) || (chippkg == HWSIM_PKG_ID))
-
-typedef u32(*si_intrsoff_t) (void *intr_arg);
-typedef void (*si_intrsrestore_t) (void *intr_arg, u32 arg);
-typedef bool(*si_intrsenabled_t) (void *intr_arg);
-
-typedef struct gpioh_item {
- void *arg;
- bool level;
- gpio_handler_t handler;
- u32 event;
- struct gpioh_item *next;
-} gpioh_item_t;
-
-/* misc si info needed by some of the routines */
-typedef struct si_info {
- struct si_pub pub; /* back plane public state (must be first) */
- void *pbus; /* handle to bus (pci/sdio/..) */
- uint dev_coreid; /* the core provides driver functions */
- void *intr_arg; /* interrupt callback function arg */
- si_intrsoff_t intrsoff_fn; /* turns chip interrupts off */
- si_intrsrestore_t intrsrestore_fn; /* restore chip interrupts */
- si_intrsenabled_t intrsenabled_fn; /* check if interrupts are enabled */
-
- void *pch; /* PCI/E core handle */
-
- gpioh_item_t *gpioh_head; /* GPIO event handlers list */
-
- bool memseg; /* flag to toggle MEM_SEG register */
-
- char *vars;
- uint varsz;
-
- void *curmap; /* current regs va */
- void *regs[SI_MAXCORES]; /* other regs va */
-
- uint curidx; /* current core index */
- uint numcores; /* # discovered cores */
- uint coreid[SI_MAXCORES]; /* id of each core */
- u32 coresba[SI_MAXCORES]; /* backplane address of each core */
- void *regs2[SI_MAXCORES]; /* va of each core second register set (usbh20) */
- u32 coresba2[SI_MAXCORES]; /* address of each core second register set (usbh20) */
- u32 coresba_size[SI_MAXCORES]; /* backplane address space size */
- u32 coresba2_size[SI_MAXCORES]; /* second address space size */
-
- void *curwrap; /* current wrapper va */
- void *wrappers[SI_MAXCORES]; /* other cores wrapper va */
- u32 wrapba[SI_MAXCORES]; /* address of controlling wrapper */
-
- u32 cia[SI_MAXCORES]; /* erom cia entry for each core */
- u32 cib[SI_MAXCORES]; /* erom cia entry for each core */
- u32 oob_router; /* oob router registers for axi */
-} si_info_t;
-
-#define SI_INFO(sih) ((si_info_t *)(sih))
-
-#define GOODCOREADDR(x, b) (((x) >= (b)) && ((x) < ((b) + SI_MAXCORES * SI_CORE_SIZE)) && \
- IS_ALIGNED((x), SI_CORE_SIZE))
-#define GOODREGS(regs) ((regs) != NULL && IS_ALIGNED((unsigned long)(regs), SI_CORE_SIZE))
-#define BADCOREADDR 0
-#define GOODIDX(idx) (((uint)idx) < SI_MAXCORES)
-#define NOREV -1 /* Invalid rev */
-
-/* Newer chips can access PCI/PCIE and CC core without requiring to change
- * PCI BAR0 WIN
- */
-#define SI_FAST(si) (((si)->pub.buscoretype == PCIE_CORE_ID) || \
- (((si)->pub.buscoretype == PCI_CORE_ID) && (si)->pub.buscorerev >= 13))
-
-#define PCIEREGS(si) (((char *)((si)->curmap) + PCI_16KB0_PCIREGS_OFFSET))
-#define CCREGS_FAST(si) (((char *)((si)->curmap) + PCI_16KB0_CCREGS_OFFSET))
-
-/*
- * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts
- * before after core switching to avoid invalid register access inside ISR.
- */
-#define INTR_OFF(si, intr_val) \
- if ((si)->intrsoff_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
- intr_val = (*(si)->intrsoff_fn)((si)->intr_arg); }
-#define INTR_RESTORE(si, intr_val) \
- if ((si)->intrsrestore_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
- (*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); }
-
-/* dynamic clock control defines */
-#define LPOMINFREQ 25000 /* low power oscillator min */
-#define LPOMAXFREQ 43000 /* low power oscillator max */
-#define XTALMINFREQ 19800000 /* 20 MHz - 1% */
-#define XTALMAXFREQ 20200000 /* 20 MHz + 1% */
-#define PCIMINFREQ 25000000 /* 25 MHz */
-#define PCIMAXFREQ 34000000 /* 33 MHz + fudge */
-
-#define ILP_DIV_5MHZ 0 /* ILP = 5 MHz */
-#define ILP_DIV_1MHZ 4 /* ILP = 1 MHz */
-
-#define PCI(si) (((si)->pub.bustype == PCI_BUS) && \
- ((si)->pub.buscoretype == PCI_CORE_ID))
-#define PCIE(si) (((si)->pub.bustype == PCI_BUS) && \
- ((si)->pub.buscoretype == PCIE_CORE_ID))
-#define PCI_FORCEHT(si) \
- (PCIE(si) && (si->pub.chip == BCM4716_CHIP_ID))
-
-/* GPIO Based LED powersave defines */
-#define DEFAULT_GPIO_ONTIME 10 /* Default: 10% on */
-#define DEFAULT_GPIO_OFFTIME 90 /* Default: 10% on */
-
-#ifndef DEFAULT_GPIOTIMERVAL
-#define DEFAULT_GPIOTIMERVAL ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME)
-#endif
-
-/*
- * Build device path. Path size must be >= SI_DEVPATH_BUFSZ.
- * The returned path is NULL terminated and has trailing '/'.
- * Return 0 on success, nonzero otherwise.
- */
-extern int si_devpath(si_t *sih, char *path, int size);
-/* Read variable with prepending the devpath to the name */
-extern char *si_getdevpathvar(si_t *sih, const char *name);
-extern int si_getdevpathintvar(si_t *sih, const char *name);
-
-extern void si_war42780_clkreq(si_t *sih, bool clkreq);
-extern void si_pci_sleep(si_t *sih);
-extern void si_pci_down(si_t *sih);
-extern void si_pci_up(si_t *sih);
-extern void si_pcie_extendL1timer(si_t *sih, bool extend);
-extern int si_pci_fixcfg(si_t *sih);
-
-extern void si_chipcontrl_epa4331(si_t *sih, bool on);
-/* Enable Ex-PA for 4313 */
-extern void si_epa_4313war(si_t *sih);
-
-char *si_getnvramflvar(si_t *sih, const char *name);
-
-/* AMBA Interconnect exported externs */
-extern si_t *ai_attach(uint pcidev, void *regs, uint bustype,
- void *sdh, char **vars, uint *varsz);
-extern si_t *ai_kattach(void);
-extern void ai_scan(si_t *sih, void *regs, uint devid);
-
-extern uint ai_flag(si_t *sih);
-extern void ai_setint(si_t *sih, int siflag);
-extern uint ai_coreidx(si_t *sih);
-extern uint ai_corevendor(si_t *sih);
-extern uint ai_corerev(si_t *sih);
-extern bool ai_iscoreup(si_t *sih);
-extern void *ai_setcoreidx(si_t *sih, uint coreidx);
-extern u32 ai_core_cflags(si_t *sih, u32 mask, u32 val);
-extern void ai_core_cflags_wo(si_t *sih, u32 mask, u32 val);
-extern u32 ai_core_sflags(si_t *sih, u32 mask, u32 val);
-extern uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask,
- uint val);
-extern void ai_core_reset(si_t *sih, u32 bits, u32 resetbits);
-extern void ai_core_disable(si_t *sih, u32 bits);
-extern int ai_numaddrspaces(si_t *sih);
-extern u32 ai_addrspace(si_t *sih, uint asidx);
-extern u32 ai_addrspacesize(si_t *sih, uint asidx);
-extern void ai_write_wrap_reg(si_t *sih, u32 offset, u32 val);
-
-#ifdef BCMSDIO
-#define si_setcoreidx(sih, idx) sb_setcoreidx(sih, idx)
-#define si_coreid(sih) sb_coreid(sih)
-#define si_corerev(sih) sb_corerev(sih)
-#endif
-
-#endif /* _siutils_h_ */
diff --git a/drivers/staging/brcm80211/include/wlioctl.h b/drivers/staging/brcm80211/include/wlioctl.h
index 5e2b11b..2876bd9 100644
--- a/drivers/staging/brcm80211/include/wlioctl.h
+++ b/drivers/staging/brcm80211/include/wlioctl.h
@@ -259,6 +259,7 @@
/* used for association with a specific BSSID and chanspec list */
typedef struct wl_assoc_params {
u8 bssid[ETH_ALEN]; /* 00:00:00:00:00:00: broadcast scan */
+ u16 bssid_cnt;
s32 chanspec_num; /* 0: all available channels,
* otherwise count of chanspecs in chanspec_list
*/
@@ -585,15 +586,6 @@
u8 ea[1][ETH_ALEN]; /* variable length array of MAC addresses */
};
-/* get pkt count struct passed through ioctl */
-typedef struct get_pktcnt {
- uint rx_good_pkt;
- uint rx_bad_pkt;
- uint tx_good_pkt;
- uint tx_bad_pkt;
- uint rx_ocast_good_pkt; /* unicast packets destined for others */
-} get_pktcnt_t;
-
#ifdef BRCM_FULLMAC
/* Linux network driver ioctl encoding */
typedef struct wl_ioctl {
@@ -1247,8 +1239,6 @@
/* Message levels */
#define WL_ERROR_VAL 0x00000001
#define WL_TRACE_VAL 0x00000002
-#define WL_AMPDU_VAL 0x20000000
-#define WL_FFPLD_VAL 0x40000000
/* maximum channels returned by the get valid channels iovar */
#define WL_NUMCHANNELS 64
@@ -1260,348 +1250,11 @@
#define NFIFO 6 /* # tx/rx fifopairs */
-#define WL_CNT_T_VERSION 7 /* current version of wl_cnt_t struct */
-
-struct wl_cnt {
- u16 version; /* see definition of WL_CNT_T_VERSION */
- u16 length; /* length of entire structure */
-
- /* transmit stat counters */
- u32 txframe; /* tx data frames */
- u32 txbyte; /* tx data bytes */
- u32 txretrans; /* tx mac retransmits */
- u32 txerror; /* tx data errors (derived: sum of others) */
- u32 txctl; /* tx management frames */
- u32 txprshort; /* tx short preamble frames */
- u32 txserr; /* tx status errors */
- u32 txnobuf; /* tx out of buffers errors */
- u32 txnoassoc; /* tx discard because we're not associated */
- u32 txrunt; /* tx runt frames */
- u32 txchit; /* tx header cache hit (fastpath) */
- u32 txcmiss; /* tx header cache miss (slowpath) */
- u32 ieee_tx_status; /* calls to ieee80211_tx_status */
- u32 ieee_tx; /* tx calls frm mac0211 */
- u32 ieee_rx; /* calls to ieee_rx */
-
- /* transmit chip error counters */
- u32 txuflo; /* tx fifo underflows */
- u32 txphyerr; /* tx phy errors (indicated in tx status) */
- u32 txphycrs;
-
- /* receive stat counters */
- u32 rxframe; /* rx data frames */
- u32 rxbyte; /* rx data bytes */
- u32 rxerror; /* rx data errors (derived: sum of others) */
- u32 rxctl; /* rx management frames */
- u32 rxnobuf; /* rx out of buffers errors */
- u32 rxnondata; /* rx non data frames in the data channel errors */
- u32 rxbadds; /* rx bad DS errors */
- u32 rxbadcm; /* rx bad control or management frames */
- u32 rxfragerr; /* rx fragmentation errors */
- u32 rxrunt; /* rx runt frames */
- u32 rxgiant; /* rx giant frames */
- u32 rxnoscb; /* rx no scb error */
- u32 rxbadproto; /* rx invalid frames */
- u32 rxbadsrcmac; /* rx frames with Invalid Src Mac */
- u32 rxbadda; /* rx frames tossed for invalid da */
- u32 rxfilter; /* rx frames filtered out */
-
- /* receive chip error counters */
- u32 rxoflo; /* rx fifo overflow errors */
- u32 rxuflo[NFIFO]; /* rx dma descriptor underflow errors */
-
- u32 d11cnt_txrts_off; /* d11cnt txrts value when reset d11cnt */
- u32 d11cnt_rxcrc_off; /* d11cnt rxcrc value when reset d11cnt */
- u32 d11cnt_txnocts_off; /* d11cnt txnocts value when reset d11cnt */
-
- /* misc counters */
- u32 dmade; /* tx/rx dma descriptor errors */
- u32 dmada; /* tx/rx dma data errors */
- u32 dmape; /* tx/rx dma descriptor protocol errors */
- u32 reset; /* reset count */
- u32 tbtt; /* cnts the TBTT int's */
- u32 txdmawar;
- u32 pkt_callback_reg_fail; /* callbacks register failure */
-
- /* MAC counters: 32-bit version of d11.h's macstat_t */
- u32 txallfrm; /* total number of frames sent, incl. Data, ACK, RTS, CTS,
- * Control Management (includes retransmissions)
- */
- u32 txrtsfrm; /* number of RTS sent out by the MAC */
- u32 txctsfrm; /* number of CTS sent out by the MAC */
- u32 txackfrm; /* number of ACK frames sent out */
- u32 txdnlfrm; /* Not used */
- u32 txbcnfrm; /* beacons transmitted */
- u32 txfunfl[8]; /* per-fifo tx underflows */
- u32 txtplunfl; /* Template underflows (mac was too slow to transmit ACK/CTS
- * or BCN)
- */
- u32 txphyerror; /* Transmit phy error, type of error is reported in tx-status for
- * driver enqueued frames
- */
- u32 rxfrmtoolong; /* Received frame longer than legal limit (2346 bytes) */
- u32 rxfrmtooshrt; /* Received frame did not contain enough bytes for its frame type */
- u32 rxinvmachdr; /* Either the protocol version != 0 or frame type not
- * data/control/management
- */
- u32 rxbadfcs; /* number of frames for which the CRC check failed in the MAC */
- u32 rxbadplcp; /* parity check of the PLCP header failed */
- u32 rxcrsglitch; /* PHY was able to correlate the preamble but not the header */
- u32 rxstrt; /* Number of received frames with a good PLCP
- * (i.e. passing parity check)
- */
- u32 rxdfrmucastmbss; /* Number of received DATA frames with good FCS and matching RA */
- u32 rxmfrmucastmbss; /* number of received mgmt frames with good FCS and matching RA */
- u32 rxcfrmucast; /* number of received CNTRL frames with good FCS and matching RA */
- u32 rxrtsucast; /* number of unicast RTS addressed to the MAC (good FCS) */
- u32 rxctsucast; /* number of unicast CTS addressed to the MAC (good FCS) */
- u32 rxackucast; /* number of ucast ACKS received (good FCS) */
- u32 rxdfrmocast; /* number of received DATA frames (good FCS and not matching RA) */
- u32 rxmfrmocast; /* number of received MGMT frames (good FCS and not matching RA) */
- u32 rxcfrmocast; /* number of received CNTRL frame (good FCS and not matching RA) */
- u32 rxrtsocast; /* number of received RTS not addressed to the MAC */
- u32 rxctsocast; /* number of received CTS not addressed to the MAC */
- u32 rxdfrmmcast; /* number of RX Data multicast frames received by the MAC */
- u32 rxmfrmmcast; /* number of RX Management multicast frames received by the MAC */
- u32 rxcfrmmcast; /* number of RX Control multicast frames received by the MAC
- * (unlikely to see these)
- */
- u32 rxbeaconmbss; /* beacons received from member of BSS */
- u32 rxdfrmucastobss; /* number of unicast frames addressed to the MAC from
- * other BSS (WDS FRAME)
- */
- u32 rxbeaconobss; /* beacons received from other BSS */
- u32 rxrsptmout; /* Number of response timeouts for transmitted frames
- * expecting a response
- */
- u32 bcntxcancl; /* transmit beacons canceled due to receipt of beacon (IBSS) */
- u32 rxf0ovfl; /* Number of receive fifo 0 overflows */
- u32 rxf1ovfl; /* Number of receive fifo 1 overflows (obsolete) */
- u32 rxf2ovfl; /* Number of receive fifo 2 overflows (obsolete) */
- u32 txsfovfl; /* Number of transmit status fifo overflows (obsolete) */
- u32 pmqovfl; /* Number of PMQ overflows */
- u32 rxcgprqfrm; /* Number of received Probe requests that made it into
- * the PRQ fifo
- */
- u32 rxcgprsqovfl; /* Rx Probe Request Que overflow in the AP */
- u32 txcgprsfail; /* Tx Probe Response Fail. AP sent probe response but did
- * not get ACK
- */
- u32 txcgprssuc; /* Tx Probe Response Success (ACK was received) */
- u32 prs_timeout; /* Number of probe requests that were dropped from the PRQ
- * fifo because a probe response could not be sent out within
- * the time limit defined in M_PRS_MAXTIME
- */
- u32 rxnack;
- u32 frmscons;
- u32 txnack;
- u32 txglitch_nack; /* obsolete */
- u32 txburst; /* obsolete */
-
- /* 802.11 MIB counters, pp. 614 of 802.11 reaff doc. */
- u32 txfrag; /* dot11TransmittedFragmentCount */
- u32 txmulti; /* dot11MulticastTransmittedFrameCount */
- u32 txfail; /* dot11FailedCount */
- u32 txretry; /* dot11RetryCount */
- u32 txretrie; /* dot11MultipleRetryCount */
- u32 rxdup; /* dot11FrameduplicateCount */
- u32 txrts; /* dot11RTSSuccessCount */
- u32 txnocts; /* dot11RTSFailureCount */
- u32 txnoack; /* dot11ACKFailureCount */
- u32 rxfrag; /* dot11ReceivedFragmentCount */
- u32 rxmulti; /* dot11MulticastReceivedFrameCount */
- u32 rxcrc; /* dot11FCSErrorCount */
- u32 txfrmsnt; /* dot11TransmittedFrameCount (bogus MIB?) */
- u32 rxundec; /* dot11WEPUndecryptableCount */
-
- /* WPA2 counters (see rxundec for DecryptFailureCount) */
- u32 tkipmicfaill; /* TKIPLocalMICFailures */
- u32 tkipcntrmsr; /* TKIPCounterMeasuresInvoked */
- u32 tkipreplay; /* TKIPReplays */
- u32 ccmpfmterr; /* CCMPFormatErrors */
- u32 ccmpreplay; /* CCMPReplays */
- u32 ccmpundec; /* CCMPDecryptErrors */
- u32 fourwayfail; /* FourWayHandshakeFailures */
- u32 wepundec; /* dot11WEPUndecryptableCount */
- u32 wepicverr; /* dot11WEPICVErrorCount */
- u32 decsuccess; /* DecryptSuccessCount */
- u32 tkipicverr; /* TKIPICVErrorCount */
- u32 wepexcluded; /* dot11WEPExcludedCount */
-
- u32 rxundec_mcst; /* dot11WEPUndecryptableCount */
-
- /* WPA2 counters (see rxundec for DecryptFailureCount) */
- u32 tkipmicfaill_mcst; /* TKIPLocalMICFailures */
- u32 tkipcntrmsr_mcst; /* TKIPCounterMeasuresInvoked */
- u32 tkipreplay_mcst; /* TKIPReplays */
- u32 ccmpfmterr_mcst; /* CCMPFormatErrors */
- u32 ccmpreplay_mcst; /* CCMPReplays */
- u32 ccmpundec_mcst; /* CCMPDecryptErrors */
- u32 fourwayfail_mcst; /* FourWayHandshakeFailures */
- u32 wepundec_mcst; /* dot11WEPUndecryptableCount */
- u32 wepicverr_mcst; /* dot11WEPICVErrorCount */
- u32 decsuccess_mcst; /* DecryptSuccessCount */
- u32 tkipicverr_mcst; /* TKIPICVErrorCount */
- u32 wepexcluded_mcst; /* dot11WEPExcludedCount */
-
- u32 txchanrej; /* Tx frames suppressed due to channel rejection */
- u32 txexptime; /* Tx frames suppressed due to timer expiration */
- u32 psmwds; /* Count PSM watchdogs */
- u32 phywatchdog; /* Count Phy watchdogs (triggered by ucode) */
-
- /* MBSS counters, AP only */
- u32 prq_entries_handled; /* PRQ entries read in */
- u32 prq_undirected_entries; /* which were bcast bss & ssid */
- u32 prq_bad_entries; /* which could not be translated to info */
- u32 atim_suppress_count; /* TX suppressions on ATIM fifo */
- u32 bcn_template_not_ready; /* Template marked in use on send bcn ... */
- u32 bcn_template_not_ready_done; /* ...but "DMA done" interrupt rcvd */
- u32 late_tbtt_dpc; /* TBTT DPC did not happen in time */
-
- /* per-rate receive stat counters */
- u32 rx1mbps; /* packets rx at 1Mbps */
- u32 rx2mbps; /* packets rx at 2Mbps */
- u32 rx5mbps5; /* packets rx at 5.5Mbps */
- u32 rx6mbps; /* packets rx at 6Mbps */
- u32 rx9mbps; /* packets rx at 9Mbps */
- u32 rx11mbps; /* packets rx at 11Mbps */
- u32 rx12mbps; /* packets rx at 12Mbps */
- u32 rx18mbps; /* packets rx at 18Mbps */
- u32 rx24mbps; /* packets rx at 24Mbps */
- u32 rx36mbps; /* packets rx at 36Mbps */
- u32 rx48mbps; /* packets rx at 48Mbps */
- u32 rx54mbps; /* packets rx at 54Mbps */
- u32 rx108mbps; /* packets rx at 108mbps */
- u32 rx162mbps; /* packets rx at 162mbps */
- u32 rx216mbps; /* packets rx at 216 mbps */
- u32 rx270mbps; /* packets rx at 270 mbps */
- u32 rx324mbps; /* packets rx at 324 mbps */
- u32 rx378mbps; /* packets rx at 378 mbps */
- u32 rx432mbps; /* packets rx at 432 mbps */
- u32 rx486mbps; /* packets rx at 486 mbps */
- u32 rx540mbps; /* packets rx at 540 mbps */
-
- /* pkteng rx frame stats */
- u32 pktengrxducast; /* unicast frames rxed by the pkteng code */
- u32 pktengrxdmcast; /* multicast frames rxed by the pkteng code */
-
- u32 rfdisable; /* count of radio disables */
- u32 bphy_rxcrsglitch; /* PHY count of bphy glitches */
-
- u32 txmpdu_sgi; /* count for sgi transmit */
- u32 rxmpdu_sgi; /* count for sgi received */
- u32 txmpdu_stbc; /* count for stbc transmit */
- u32 rxmpdu_stbc; /* count for stbc received */
-};
-
-#define WL_DELTA_STATS_T_VERSION 1 /* current version of wl_delta_stats_t struct */
-
-typedef struct {
- u16 version; /* see definition of WL_DELTA_STATS_T_VERSION */
- u16 length; /* length of entire structure */
-
- /* transmit stat counters */
- u32 txframe; /* tx data frames */
- u32 txbyte; /* tx data bytes */
- u32 txretrans; /* tx mac retransmits */
- u32 txfail; /* tx failures */
-
- /* receive stat counters */
- u32 rxframe; /* rx data frames */
- u32 rxbyte; /* rx data bytes */
-
- /* per-rate receive stat counters */
- u32 rx1mbps; /* packets rx at 1Mbps */
- u32 rx2mbps; /* packets rx at 2Mbps */
- u32 rx5mbps5; /* packets rx at 5.5Mbps */
- u32 rx6mbps; /* packets rx at 6Mbps */
- u32 rx9mbps; /* packets rx at 9Mbps */
- u32 rx11mbps; /* packets rx at 11Mbps */
- u32 rx12mbps; /* packets rx at 12Mbps */
- u32 rx18mbps; /* packets rx at 18Mbps */
- u32 rx24mbps; /* packets rx at 24Mbps */
- u32 rx36mbps; /* packets rx at 36Mbps */
- u32 rx48mbps; /* packets rx at 48Mbps */
- u32 rx54mbps; /* packets rx at 54Mbps */
- u32 rx108mbps; /* packets rx at 108mbps */
- u32 rx162mbps; /* packets rx at 162mbps */
- u32 rx216mbps; /* packets rx at 216 mbps */
- u32 rx270mbps; /* packets rx at 270 mbps */
- u32 rx324mbps; /* packets rx at 324 mbps */
- u32 rx378mbps; /* packets rx at 378 mbps */
- u32 rx432mbps; /* packets rx at 432 mbps */
- u32 rx486mbps; /* packets rx at 486 mbps */
- u32 rx540mbps; /* packets rx at 540 mbps */
-} wl_delta_stats_t;
-
-#define WL_WME_CNT_VERSION 1 /* current version of wl_wme_cnt_t */
-
-typedef struct {
- u32 packets;
- u32 bytes;
-} wl_traffic_stats_t;
-
-typedef struct {
- u16 version; /* see definition of WL_WME_CNT_VERSION */
- u16 length; /* length of entire structure */
-
- wl_traffic_stats_t tx[AC_COUNT]; /* Packets transmitted */
- wl_traffic_stats_t tx_failed[AC_COUNT]; /* Packets dropped or failed to transmit */
- wl_traffic_stats_t rx[AC_COUNT]; /* Packets received */
- wl_traffic_stats_t rx_failed[AC_COUNT]; /* Packets failed to receive */
-
- wl_traffic_stats_t forward[AC_COUNT]; /* Packets forwarded by AP */
-
- wl_traffic_stats_t tx_expired[AC_COUNT]; /* packets dropped due to lifetime expiry */
-
-} wl_wme_cnt_t;
-
struct wl_msglevel2 {
u32 low;
u32 high;
};
-#ifdef WLBA
-
-#define WLC_BA_CNT_VERSION 1 /* current version of wlc_ba_cnt_t */
-
-/* block ack related stats */
-typedef struct wlc_ba_cnt {
- u16 version; /* WLC_BA_CNT_VERSION */
- u16 length; /* length of entire structure */
-
- /* transmit stat counters */
- u32 txpdu; /* pdus sent */
- u32 txsdu; /* sdus sent */
- u32 txfc; /* tx side flow controlled packets */
- u32 txfci; /* tx side flow control initiated */
- u32 txretrans; /* retransmitted pdus */
- u32 txbatimer; /* ba resend due to timer */
- u32 txdrop; /* dropped packets */
- u32 txaddbareq; /* addba req sent */
- u32 txaddbaresp; /* addba resp sent */
- u32 txdelba; /* delba sent */
- u32 txba; /* ba sent */
- u32 txbar; /* bar sent */
- u32 txpad[4]; /* future */
-
- /* receive side counters */
- u32 rxpdu; /* pdus recd */
- u32 rxqed; /* pdus buffered before sending up */
- u32 rxdup; /* duplicate pdus */
- u32 rxnobuf; /* pdus discarded due to no buf */
- u32 rxaddbareq; /* addba req recd */
- u32 rxaddbaresp; /* addba resp recd */
- u32 rxdelba; /* delba recd */
- u32 rxba; /* ba recd */
- u32 rxbar; /* bar recd */
- u32 rxinvba; /* invalid ba recd */
- u32 rxbaholes; /* ba recd with holes */
- u32 rxunexp; /* unexpected packets */
- u32 rxpad[4]; /* future */
-} wlc_ba_cnt_t;
-#endif /* WLBA */
-
/* structure for per-tid ampdu control */
struct ampdu_tid_control {
u8 tid; /* tid */
diff --git a/drivers/staging/brcm80211/util/Makefile b/drivers/staging/brcm80211/util/Makefile
new file mode 100644
index 0000000..f9b36ca
--- /dev/null
+++ b/drivers/staging/brcm80211/util/Makefile
@@ -0,0 +1,29 @@
+#
+# Makefile fragment for Broadcom 802.11n Networking Device Driver Utilities
+#
+# Copyright (c) 2011 Broadcom Corporation
+#
+# Permission to use, copy, modify, and/or distribute this software for any
+# purpose with or without fee is hereby granted, provided that the above
+# copyright notice and this permission notice appear in all copies.
+#
+# THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+# WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+# MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
+# SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+# WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
+# OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
+# CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+
+ccflags-y := \
+ -Idrivers/staging/brcm80211/util \
+ -Idrivers/staging/brcm80211/include
+
+BRCMUTIL_OFILES := \
+ bcmutils.o \
+ bcmwifi.o
+
+MODULEPFX := brcmutil
+
+obj-$(CONFIG_BRCMUTIL) += $(MODULEPFX).o
+$(MODULEPFX)-objs = $(BRCMUTIL_OFILES)
diff --git a/drivers/staging/brcm80211/util/aiutils.c b/drivers/staging/brcm80211/util/aiutils.c
deleted file mode 100644
index 5708690..0000000
--- a/drivers/staging/brcm80211/util/aiutils.c
+++ /dev/null
@@ -1,705 +0,0 @@
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#include <linux/delay.h>
-#include <linux/kernel.h>
-#include <linux/string.h>
-#include <bcmdefs.h>
-#include <linux/module.h>
-#include <linux/pci.h>
-#include <bcmutils.h>
-#include <siutils.h>
-#include <hndsoc.h>
-#include <sbchipc.h>
-#include <pcicfg.h>
-#include <bcmdevs.h>
-
-#define BCM47162_DMP() ((sih->chip == BCM47162_CHIP_ID) && \
- (sih->chiprev == 0) && \
- (sii->coreid[sii->curidx] == MIPS74K_CORE_ID))
-
-/* EROM parsing */
-
-static u32
-get_erom_ent(si_t *sih, u32 **eromptr, u32 mask, u32 match)
-{
- u32 ent;
- uint inv = 0, nom = 0;
-
- while (true) {
- ent = R_REG(*eromptr);
- (*eromptr)++;
-
- if (mask == 0)
- break;
-
- if ((ent & ER_VALID) == 0) {
- inv++;
- continue;
- }
-
- if (ent == (ER_END | ER_VALID))
- break;
-
- if ((ent & mask) == match)
- break;
-
- nom++;
- }
-
- SI_VMSG(("%s: Returning ent 0x%08x\n", __func__, ent));
- if (inv + nom) {
- SI_VMSG((" after %d invalid and %d non-matching entries\n",
- inv, nom));
- }
- return ent;
-}
-
-static u32
-get_asd(si_t *sih, u32 **eromptr, uint sp, uint ad, uint st,
- u32 *addrl, u32 *addrh, u32 *sizel, u32 *sizeh)
-{
- u32 asd, sz, szd;
-
- asd = get_erom_ent(sih, eromptr, ER_VALID, ER_VALID);
- if (((asd & ER_TAG1) != ER_ADD) ||
- (((asd & AD_SP_MASK) >> AD_SP_SHIFT) != sp) ||
- ((asd & AD_ST_MASK) != st)) {
- /* This is not what we want, "push" it back */
- (*eromptr)--;
- return 0;
- }
- *addrl = asd & AD_ADDR_MASK;
- if (asd & AD_AG32)
- *addrh = get_erom_ent(sih, eromptr, 0, 0);
- else
- *addrh = 0;
- *sizeh = 0;
- sz = asd & AD_SZ_MASK;
- if (sz == AD_SZ_SZD) {
- szd = get_erom_ent(sih, eromptr, 0, 0);
- *sizel = szd & SD_SZ_MASK;
- if (szd & SD_SG32)
- *sizeh = get_erom_ent(sih, eromptr, 0, 0);
- } else
- *sizel = AD_SZ_BASE << (sz >> AD_SZ_SHIFT);
-
- SI_VMSG((" SP %d, ad %d: st = %d, 0x%08x_0x%08x @ 0x%08x_0x%08x\n",
- sp, ad, st, *sizeh, *sizel, *addrh, *addrl));
-
- return asd;
-}
-
-static void ai_hwfixup(si_info_t *sii)
-{
-}
-
-/* parse the enumeration rom to identify all cores */
-void ai_scan(si_t *sih, void *regs, uint devid)
-{
- si_info_t *sii = SI_INFO(sih);
- chipcregs_t *cc = (chipcregs_t *) regs;
- u32 erombase, *eromptr, *eromlim;
-
- erombase = R_REG(&cc->eromptr);
-
- switch (sih->bustype) {
- case SI_BUS:
- eromptr = (u32 *) REG_MAP(erombase, SI_CORE_SIZE);
- break;
-
- case PCI_BUS:
- /* Set wrappers address */
- sii->curwrap = (void *)((unsigned long)regs + SI_CORE_SIZE);
-
- /* Now point the window at the erom */
- pci_write_config_dword(sii->pbus, PCI_BAR0_WIN, erombase);
- eromptr = regs;
- break;
-
- case SPI_BUS:
- case SDIO_BUS:
- eromptr = (u32 *)(unsigned long)erombase;
- break;
-
- default:
- SI_ERROR(("Don't know how to do AXI enumertion on bus %d\n",
- sih->bustype));
- ASSERT(0);
- return;
- }
- eromlim = eromptr + (ER_REMAPCONTROL / sizeof(u32));
-
- SI_VMSG(("ai_scan: regs = 0x%p, erombase = 0x%08x, eromptr = 0x%p, eromlim = 0x%p\n", regs, erombase, eromptr, eromlim));
- while (eromptr < eromlim) {
- u32 cia, cib, cid, mfg, crev, nmw, nsw, nmp, nsp;
- u32 mpd, asd, addrl, addrh, sizel, sizeh;
- u32 *base;
- uint i, j, idx;
- bool br;
-
- br = false;
-
- /* Grok a component */
- cia = get_erom_ent(sih, &eromptr, ER_TAG, ER_CI);
- if (cia == (ER_END | ER_VALID)) {
- SI_VMSG(("Found END of erom after %d cores\n",
- sii->numcores));
- ai_hwfixup(sii);
- return;
- }
- base = eromptr - 1;
- cib = get_erom_ent(sih, &eromptr, 0, 0);
-
- if ((cib & ER_TAG) != ER_CI) {
- SI_ERROR(("CIA not followed by CIB\n"));
- goto error;
- }
-
- cid = (cia & CIA_CID_MASK) >> CIA_CID_SHIFT;
- mfg = (cia & CIA_MFG_MASK) >> CIA_MFG_SHIFT;
- crev = (cib & CIB_REV_MASK) >> CIB_REV_SHIFT;
- nmw = (cib & CIB_NMW_MASK) >> CIB_NMW_SHIFT;
- nsw = (cib & CIB_NSW_MASK) >> CIB_NSW_SHIFT;
- nmp = (cib & CIB_NMP_MASK) >> CIB_NMP_SHIFT;
- nsp = (cib & CIB_NSP_MASK) >> CIB_NSP_SHIFT;
-
- SI_VMSG(("Found component 0x%04x/0x%04x rev %d at erom addr 0x%p, with nmw = %d, " "nsw = %d, nmp = %d & nsp = %d\n", mfg, cid, crev, base, nmw, nsw, nmp, nsp));
-
- if (((mfg == MFGID_ARM) && (cid == DEF_AI_COMP)) || (nsp == 0))
- continue;
- if ((nmw + nsw == 0)) {
- /* A component which is not a core */
- if (cid == OOB_ROUTER_CORE_ID) {
- asd = get_asd(sih, &eromptr, 0, 0, AD_ST_SLAVE,
- &addrl, &addrh, &sizel, &sizeh);
- if (asd != 0) {
- sii->oob_router = addrl;
- }
- }
- continue;
- }
-
- idx = sii->numcores;
-/* sii->eromptr[idx] = base; */
- sii->cia[idx] = cia;
- sii->cib[idx] = cib;
- sii->coreid[idx] = cid;
-
- for (i = 0; i < nmp; i++) {
- mpd = get_erom_ent(sih, &eromptr, ER_VALID, ER_VALID);
- if ((mpd & ER_TAG) != ER_MP) {
- SI_ERROR(("Not enough MP entries for component 0x%x\n", cid));
- goto error;
- }
- SI_VMSG((" Master port %d, mp: %d id: %d\n", i,
- (mpd & MPD_MP_MASK) >> MPD_MP_SHIFT,
- (mpd & MPD_MUI_MASK) >> MPD_MUI_SHIFT));
- }
-
- /* First Slave Address Descriptor should be port 0:
- * the main register space for the core
- */
- asd =
- get_asd(sih, &eromptr, 0, 0, AD_ST_SLAVE, &addrl, &addrh,
- &sizel, &sizeh);
- if (asd == 0) {
- /* Try again to see if it is a bridge */
- asd =
- get_asd(sih, &eromptr, 0, 0, AD_ST_BRIDGE, &addrl,
- &addrh, &sizel, &sizeh);
- if (asd != 0)
- br = true;
- else if ((addrh != 0) || (sizeh != 0)
- || (sizel != SI_CORE_SIZE)) {
- SI_ERROR(("First Slave ASD for core 0x%04x malformed " "(0x%08x)\n", cid, asd));
- goto error;
- }
- }
- sii->coresba[idx] = addrl;
- sii->coresba_size[idx] = sizel;
- /* Get any more ASDs in port 0 */
- j = 1;
- do {
- asd =
- get_asd(sih, &eromptr, 0, j, AD_ST_SLAVE, &addrl,
- &addrh, &sizel, &sizeh);
- if ((asd != 0) && (j == 1) && (sizel == SI_CORE_SIZE)) {
- sii->coresba2[idx] = addrl;
- sii->coresba2_size[idx] = sizel;
- }
- j++;
- } while (asd != 0);
-
- /* Go through the ASDs for other slave ports */
- for (i = 1; i < nsp; i++) {
- j = 0;
- do {
- asd =
- get_asd(sih, &eromptr, i, j++, AD_ST_SLAVE,
- &addrl, &addrh, &sizel, &sizeh);
- } while (asd != 0);
- if (j == 0) {
- SI_ERROR((" SP %d has no address descriptors\n",
- i));
- goto error;
- }
- }
-
- /* Now get master wrappers */
- for (i = 0; i < nmw; i++) {
- asd =
- get_asd(sih, &eromptr, i, 0, AD_ST_MWRAP, &addrl,
- &addrh, &sizel, &sizeh);
- if (asd == 0) {
- SI_ERROR(("Missing descriptor for MW %d\n", i));
- goto error;
- }
- if ((sizeh != 0) || (sizel != SI_CORE_SIZE)) {
- SI_ERROR(("Master wrapper %d is not 4KB\n", i));
- goto error;
- }
- if (i == 0)
- sii->wrapba[idx] = addrl;
- }
-
- /* And finally slave wrappers */
- for (i = 0; i < nsw; i++) {
- uint fwp = (nsp == 1) ? 0 : 1;
- asd =
- get_asd(sih, &eromptr, fwp + i, 0, AD_ST_SWRAP,
- &addrl, &addrh, &sizel, &sizeh);
- if (asd == 0) {
- SI_ERROR(("Missing descriptor for SW %d\n", i));
- goto error;
- }
- if ((sizeh != 0) || (sizel != SI_CORE_SIZE)) {
- SI_ERROR(("Slave wrapper %d is not 4KB\n", i));
- goto error;
- }
- if ((nmw == 0) && (i == 0))
- sii->wrapba[idx] = addrl;
- }
-
- /* Don't record bridges */
- if (br)
- continue;
-
- /* Done with core */
- sii->numcores++;
- }
-
- SI_ERROR(("Reached end of erom without finding END"));
-
- error:
- sii->numcores = 0;
- return;
-}
-
-/* This function changes the logical "focus" to the indicated core.
- * Return the current core's virtual address.
- */
-void *ai_setcoreidx(si_t *sih, uint coreidx)
-{
- si_info_t *sii = SI_INFO(sih);
- u32 addr = sii->coresba[coreidx];
- u32 wrap = sii->wrapba[coreidx];
- void *regs;
-
- if (coreidx >= sii->numcores)
- return NULL;
-
- /*
- * If the user has provided an interrupt mask enabled function,
- * then assert interrupts are disabled before switching the core.
- */
- ASSERT((sii->intrsenabled_fn == NULL)
- || !(*(sii)->intrsenabled_fn) ((sii)->intr_arg));
-
- switch (sih->bustype) {
- case SI_BUS:
- /* map new one */
- if (!sii->regs[coreidx]) {
- sii->regs[coreidx] = REG_MAP(addr, SI_CORE_SIZE);
- ASSERT(GOODREGS(sii->regs[coreidx]));
- }
- sii->curmap = regs = sii->regs[coreidx];
- if (!sii->wrappers[coreidx]) {
- sii->wrappers[coreidx] = REG_MAP(wrap, SI_CORE_SIZE);
- ASSERT(GOODREGS(sii->wrappers[coreidx]));
- }
- sii->curwrap = sii->wrappers[coreidx];
- break;
-
- case PCI_BUS:
- /* point bar0 window */
- pci_write_config_dword(sii->pbus, PCI_BAR0_WIN, addr);
- regs = sii->curmap;
- /* point bar0 2nd 4KB window */
- pci_write_config_dword(sii->pbus, PCI_BAR0_WIN2, wrap);
- break;
-
- case SPI_BUS:
- case SDIO_BUS:
- sii->curmap = regs = (void *)(unsigned long)addr;
- sii->curwrap = (void *)(unsigned long)wrap;
- break;
-
- default:
- ASSERT(0);
- regs = NULL;
- break;
- }
-
- sii->curmap = regs;
- sii->curidx = coreidx;
-
- return regs;
-}
-
-/* Return the number of address spaces in current core */
-int ai_numaddrspaces(si_t *sih)
-{
- return 2;
-}
-
-/* Return the address of the nth address space in the current core */
-u32 ai_addrspace(si_t *sih, uint asidx)
-{
- si_info_t *sii;
- uint cidx;
-
- sii = SI_INFO(sih);
- cidx = sii->curidx;
-
- if (asidx == 0)
- return sii->coresba[cidx];
- else if (asidx == 1)
- return sii->coresba2[cidx];
- else {
- SI_ERROR(("%s: Need to parse the erom again to find addr space %d\n", __func__, asidx));
- return 0;
- }
-}
-
-/* Return the size of the nth address space in the current core */
-u32 ai_addrspacesize(si_t *sih, uint asidx)
-{
- si_info_t *sii;
- uint cidx;
-
- sii = SI_INFO(sih);
- cidx = sii->curidx;
-
- if (asidx == 0)
- return sii->coresba_size[cidx];
- else if (asidx == 1)
- return sii->coresba2_size[cidx];
- else {
- SI_ERROR(("%s: Need to parse the erom again to find addr space %d\n", __func__, asidx));
- return 0;
- }
-}
-
-uint ai_flag(si_t *sih)
-{
- si_info_t *sii;
- aidmp_t *ai;
-
- sii = SI_INFO(sih);
- if (BCM47162_DMP()) {
- SI_ERROR(("%s: Attempting to read MIPS DMP registers on 47162a0", __func__));
- return sii->curidx;
- }
- ai = sii->curwrap;
-
- return R_REG(&ai->oobselouta30) & 0x1f;
-}
-
-void ai_setint(si_t *sih, int siflag)
-{
-}
-
-void ai_write_wrap_reg(si_t *sih, u32 offset, u32 val)
-{
- si_info_t *sii = SI_INFO(sih);
- u32 *w = (u32 *) sii->curwrap;
- W_REG(w + (offset / 4), val);
- return;
-}
-
-uint ai_corevendor(si_t *sih)
-{
- si_info_t *sii;
- u32 cia;
-
- sii = SI_INFO(sih);
- cia = sii->cia[sii->curidx];
- return (cia & CIA_MFG_MASK) >> CIA_MFG_SHIFT;
-}
-
-uint ai_corerev(si_t *sih)
-{
- si_info_t *sii;
- u32 cib;
-
- sii = SI_INFO(sih);
- cib = sii->cib[sii->curidx];
- return (cib & CIB_REV_MASK) >> CIB_REV_SHIFT;
-}
-
-bool ai_iscoreup(si_t *sih)
-{
- si_info_t *sii;
- aidmp_t *ai;
-
- sii = SI_INFO(sih);
- ai = sii->curwrap;
-
- return (((R_REG(&ai->ioctrl) & (SICF_FGC | SICF_CLOCK_EN)) ==
- SICF_CLOCK_EN)
- && ((R_REG(&ai->resetctrl) & AIRC_RESET) == 0));
-}
-
-/*
- * Switch to 'coreidx', issue a single arbitrary 32bit register mask&set operation,
- * switch back to the original core, and return the new value.
- *
- * When using the silicon backplane, no fiddling with interrupts or core switches is needed.
- *
- * Also, when using pci/pcie, we can optimize away the core switching for pci registers
- * and (on newer pci cores) chipcommon registers.
- */
-uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)
-{
- uint origidx = 0;
- u32 *r = NULL;
- uint w;
- uint intr_val = 0;
- bool fast = false;
- si_info_t *sii;
-
- sii = SI_INFO(sih);
-
- ASSERT(GOODIDX(coreidx));
- ASSERT(regoff < SI_CORE_SIZE);
- ASSERT((val & ~mask) == 0);
-
- if (coreidx >= SI_MAXCORES)
- return 0;
-
- if (sih->bustype == SI_BUS) {
- /* If internal bus, we can always get at everything */
- fast = true;
- /* map if does not exist */
- if (!sii->regs[coreidx]) {
- sii->regs[coreidx] = REG_MAP(sii->coresba[coreidx],
- SI_CORE_SIZE);
- ASSERT(GOODREGS(sii->regs[coreidx]));
- }
- r = (u32 *) ((unsigned char *) sii->regs[coreidx] + regoff);
- } else if (sih->bustype == PCI_BUS) {
- /* If pci/pcie, we can get at pci/pcie regs and on newer cores to chipc */
-
- if ((sii->coreid[coreidx] == CC_CORE_ID) && SI_FAST(sii)) {
- /* Chipc registers are mapped at 12KB */
-
- fast = true;
- r = (u32 *) ((char *)sii->curmap +
- PCI_16KB0_CCREGS_OFFSET + regoff);
- } else if (sii->pub.buscoreidx == coreidx) {
- /* pci registers are at either in the last 2KB of an 8KB window
- * or, in pcie and pci rev 13 at 8KB
- */
- fast = true;
- if (SI_FAST(sii))
- r = (u32 *) ((char *)sii->curmap +
- PCI_16KB0_PCIREGS_OFFSET +
- regoff);
- else
- r = (u32 *) ((char *)sii->curmap +
- ((regoff >= SBCONFIGOFF) ?
- PCI_BAR0_PCISBR_OFFSET :
- PCI_BAR0_PCIREGS_OFFSET) +
- regoff);
- }
- }
-
- if (!fast) {
- INTR_OFF(sii, intr_val);
-
- /* save current core index */
- origidx = si_coreidx(&sii->pub);
-
- /* switch core */
- r = (u32 *) ((unsigned char *) ai_setcoreidx(&sii->pub, coreidx) +
- regoff);
- }
- ASSERT(r != NULL);
-
- /* mask and set */
- if (mask || val) {
- w = (R_REG(r) & ~mask) | val;
- W_REG(r, w);
- }
-
- /* readback */
- w = R_REG(r);
-
- if (!fast) {
- /* restore core index */
- if (origidx != coreidx)
- ai_setcoreidx(&sii->pub, origidx);
-
- INTR_RESTORE(sii, intr_val);
- }
-
- return w;
-}
-
-void ai_core_disable(si_t *sih, u32 bits)
-{
- si_info_t *sii;
- volatile u32 dummy;
- aidmp_t *ai;
-
- sii = SI_INFO(sih);
-
- ASSERT(GOODREGS(sii->curwrap));
- ai = sii->curwrap;
-
- /* if core is already in reset, just return */
- if (R_REG(&ai->resetctrl) & AIRC_RESET)
- return;
-
- W_REG(&ai->ioctrl, bits);
- dummy = R_REG(&ai->ioctrl);
- udelay(10);
-
- W_REG(&ai->resetctrl, AIRC_RESET);
- udelay(1);
-}
-
-/* reset and re-enable a core
- * inputs:
- * bits - core specific bits that are set during and after reset sequence
- * resetbits - core specific bits that are set only during reset sequence
- */
-void ai_core_reset(si_t *sih, u32 bits, u32 resetbits)
-{
- si_info_t *sii;
- aidmp_t *ai;
- volatile u32 dummy;
-
- sii = SI_INFO(sih);
- ASSERT(GOODREGS(sii->curwrap));
- ai = sii->curwrap;
-
- /*
- * Must do the disable sequence first to work for arbitrary current core state.
- */
- ai_core_disable(sih, (bits | resetbits));
-
- /*
- * Now do the initialization sequence.
- */
- W_REG(&ai->ioctrl, (bits | SICF_FGC | SICF_CLOCK_EN));
- dummy = R_REG(&ai->ioctrl);
- W_REG(&ai->resetctrl, 0);
- udelay(1);
-
- W_REG(&ai->ioctrl, (bits | SICF_CLOCK_EN));
- dummy = R_REG(&ai->ioctrl);
- udelay(1);
-}
-
-void ai_core_cflags_wo(si_t *sih, u32 mask, u32 val)
-{
- si_info_t *sii;
- aidmp_t *ai;
- u32 w;
-
- sii = SI_INFO(sih);
-
- if (BCM47162_DMP()) {
- SI_ERROR(("%s: Accessing MIPS DMP register (ioctrl) on 47162a0",
- __func__));
- return;
- }
-
- ASSERT(GOODREGS(sii->curwrap));
- ai = sii->curwrap;
-
- ASSERT((val & ~mask) == 0);
-
- if (mask || val) {
- w = ((R_REG(&ai->ioctrl) & ~mask) | val);
- W_REG(&ai->ioctrl, w);
- }
-}
-
-u32 ai_core_cflags(si_t *sih, u32 mask, u32 val)
-{
- si_info_t *sii;
- aidmp_t *ai;
- u32 w;
-
- sii = SI_INFO(sih);
- if (BCM47162_DMP()) {
- SI_ERROR(("%s: Accessing MIPS DMP register (ioctrl) on 47162a0",
- __func__));
- return 0;
- }
-
- ASSERT(GOODREGS(sii->curwrap));
- ai = sii->curwrap;
-
- ASSERT((val & ~mask) == 0);
-
- if (mask || val) {
- w = ((R_REG(&ai->ioctrl) & ~mask) | val);
- W_REG(&ai->ioctrl, w);
- }
-
- return R_REG(&ai->ioctrl);
-}
-
-u32 ai_core_sflags(si_t *sih, u32 mask, u32 val)
-{
- si_info_t *sii;
- aidmp_t *ai;
- u32 w;
-
- sii = SI_INFO(sih);
- if (BCM47162_DMP()) {
- SI_ERROR(("%s: Accessing MIPS DMP register (iostatus) on 47162a0", __func__));
- return 0;
- }
-
- ASSERT(GOODREGS(sii->curwrap));
- ai = sii->curwrap;
-
- ASSERT((val & ~mask) == 0);
- ASSERT((mask & ~SISF_CORE_BITS) == 0);
-
- if (mask || val) {
- w = ((R_REG(&ai->iostatus) & ~mask) | val);
- W_REG(&ai->iostatus, w);
- }
-
- return R_REG(&ai->iostatus);
-}
-
diff --git a/drivers/staging/brcm80211/util/bcmotp.c b/drivers/staging/brcm80211/util/bcmotp.c
deleted file mode 100644
index 1799121..0000000
--- a/drivers/staging/brcm80211/util/bcmotp.c
+++ /dev/null
@@ -1,953 +0,0 @@
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#include <linux/delay.h>
-#include <linux/kernel.h>
-#include <linux/string.h>
-#include <bcmdefs.h>
-#include <linux/module.h>
-#include <linux/pci.h>
-#include <bcmdevs.h>
-#include <bcmutils.h>
-#include <siutils.h>
-#include <hndsoc.h>
-#include <sbchipc.h>
-#include <bcmotp.h>
-#include "siutils_priv.h"
-
-/*
- * There are two different OTP controllers so far:
- * 1. new IPX OTP controller: chipc 21, >=23
- * 2. older HND OTP controller: chipc 12, 17, 22
- *
- * Define BCMHNDOTP to include support for the HND OTP controller.
- * Define BCMIPXOTP to include support for the IPX OTP controller.
- *
- * NOTE 1: More than one may be defined
- * NOTE 2: If none are defined, the default is to include them all.
- */
-
-#if !defined(BCMHNDOTP) && !defined(BCMIPXOTP)
-#define BCMHNDOTP 1
-#define BCMIPXOTP 1
-#endif
-
-#define OTPTYPE_HND(ccrev) ((ccrev) < 21 || (ccrev) == 22)
-#define OTPTYPE_IPX(ccrev) ((ccrev) == 21 || (ccrev) >= 23)
-
-#define OTPP_TRIES 10000000 /* # of tries for OTPP */
-
-#ifdef BCMIPXOTP
-#define MAXNUMRDES 9 /* Maximum OTP redundancy entries */
-#endif
-
-/* OTP common function type */
-typedef int (*otp_status_t) (void *oh);
-typedef int (*otp_size_t) (void *oh);
-typedef void *(*otp_init_t) (si_t *sih);
-typedef u16(*otp_read_bit_t) (void *oh, chipcregs_t *cc, uint off);
-typedef int (*otp_read_region_t) (si_t *sih, int region, u16 *data,
- uint *wlen);
-typedef int (*otp_nvread_t) (void *oh, char *data, uint *len);
-
-/* OTP function struct */
-typedef struct otp_fn_s {
- otp_size_t size;
- otp_read_bit_t read_bit;
- otp_init_t init;
- otp_read_region_t read_region;
- otp_nvread_t nvread;
- otp_status_t status;
-} otp_fn_t;
-
-typedef struct {
- uint ccrev; /* chipc revision */
- otp_fn_t *fn; /* OTP functions */
- si_t *sih; /* Saved sb handle */
-
-#ifdef BCMIPXOTP
- /* IPX OTP section */
- u16 wsize; /* Size of otp in words */
- u16 rows; /* Geometry */
- u16 cols; /* Geometry */
- u32 status; /* Flag bits (lock/prog/rv).
- * (Reflected only when OTP is power cycled)
- */
- u16 hwbase; /* hardware subregion offset */
- u16 hwlim; /* hardware subregion boundary */
- u16 swbase; /* software subregion offset */
- u16 swlim; /* software subregion boundary */
- u16 fbase; /* fuse subregion offset */
- u16 flim; /* fuse subregion boundary */
- int otpgu_base; /* offset to General Use Region */
-#endif /* BCMIPXOTP */
-
-#ifdef BCMHNDOTP
- /* HND OTP section */
- uint size; /* Size of otp in bytes */
- uint hwprot; /* Hardware protection bits */
- uint signvalid; /* Signature valid bits */
- int boundary; /* hw/sw boundary */
-#endif /* BCMHNDOTP */
-} otpinfo_t;
-
-static otpinfo_t otpinfo;
-
-/*
- * IPX OTP Code
- *
- * Exported functions:
- * ipxotp_status()
- * ipxotp_size()
- * ipxotp_init()
- * ipxotp_read_bit()
- * ipxotp_read_region()
- * ipxotp_nvread()
- *
- */
-
-#ifdef BCMIPXOTP
-
-#define HWSW_RGN(rgn) (((rgn) == OTP_HW_RGN) ? "h/w" : "s/w")
-
-/* OTP layout */
-/* CC revs 21, 24 and 27 OTP General Use Region word offset */
-#define REVA4_OTPGU_BASE 12
-
-/* CC revs 23, 25, 26, 28 and above OTP General Use Region word offset */
-#define REVB8_OTPGU_BASE 20
-
-/* CC rev 36 OTP General Use Region word offset */
-#define REV36_OTPGU_BASE 12
-
-/* Subregion word offsets in General Use region */
-#define OTPGU_HSB_OFF 0
-#define OTPGU_SFB_OFF 1
-#define OTPGU_CI_OFF 2
-#define OTPGU_P_OFF 3
-#define OTPGU_SROM_OFF 4
-
-/* Flag bit offsets in General Use region */
-#define OTPGU_HWP_OFF 60
-#define OTPGU_SWP_OFF 61
-#define OTPGU_CIP_OFF 62
-#define OTPGU_FUSEP_OFF 63
-#define OTPGU_CIP_MSK 0x4000
-#define OTPGU_P_MSK 0xf000
-#define OTPGU_P_SHIFT (OTPGU_HWP_OFF % 16)
-
-/* OTP Size */
-#define OTP_SZ_FU_324 ((roundup(324, 8))/8) /* 324 bits */
-#define OTP_SZ_FU_288 (288/8) /* 288 bits */
-#define OTP_SZ_FU_216 (216/8) /* 216 bits */
-#define OTP_SZ_FU_72 (72/8) /* 72 bits */
-#define OTP_SZ_CHECKSUM (16/8) /* 16 bits */
-#define OTP4315_SWREG_SZ 178 /* 178 bytes */
-#define OTP_SZ_FU_144 (144/8) /* 144 bits */
-
-static int ipxotp_status(void *oh)
-{
- otpinfo_t *oi = (otpinfo_t *) oh;
- return (int)(oi->status);
-}
-
-/* Return size in bytes */
-static int ipxotp_size(void *oh)
-{
- otpinfo_t *oi = (otpinfo_t *) oh;
- return (int)oi->wsize * 2;
-}
-
-static u16 ipxotp_otpr(void *oh, chipcregs_t *cc, uint wn)
-{
- otpinfo_t *oi;
-
- oi = (otpinfo_t *) oh;
-
- ASSERT(wn < oi->wsize);
- ASSERT(cc != NULL);
-
- return R_REG(&cc->sromotp[wn]);
-}
-
-static u16 ipxotp_read_bit(void *oh, chipcregs_t *cc, uint off)
-{
- otpinfo_t *oi = (otpinfo_t *) oh;
- uint k, row, col;
- u32 otpp, st;
-
- row = off / oi->cols;
- col = off % oi->cols;
-
- otpp = OTPP_START_BUSY |
- ((OTPPOC_READ << OTPP_OC_SHIFT) & OTPP_OC_MASK) |
- ((row << OTPP_ROW_SHIFT) & OTPP_ROW_MASK) |
- ((col << OTPP_COL_SHIFT) & OTPP_COL_MASK);
- W_REG(&cc->otpprog, otpp);
-
- for (k = 0;
- ((st = R_REG(&cc->otpprog)) & OTPP_START_BUSY)
- && (k < OTPP_TRIES); k++)
- ;
- if (k >= OTPP_TRIES) {
- return 0xffff;
- }
- if (st & OTPP_READERR) {
- return 0xffff;
- }
- st = (st & OTPP_VALUE_MASK) >> OTPP_VALUE_SHIFT;
-
- return (int)st;
-}
-
-/* Calculate max HW/SW region byte size by subtracting fuse region and checksum size,
- * osizew is oi->wsize (OTP size - GU size) in words
- */
-static int ipxotp_max_rgnsz(si_t *sih, int osizew)
-{
- int ret = 0;
-
- switch (sih->chip) {
- case BCM43224_CHIP_ID:
- case BCM43225_CHIP_ID:
- ret = osizew * 2 - OTP_SZ_FU_72 - OTP_SZ_CHECKSUM;
- break;
- case BCM4313_CHIP_ID:
- ret = osizew * 2 - OTP_SZ_FU_72 - OTP_SZ_CHECKSUM;
- break;
- default:
- ASSERT(0); /* Don't know about this chip */
- }
-
- return ret;
-}
-
-static void _ipxotp_init(otpinfo_t *oi, chipcregs_t *cc)
-{
- uint k;
- u32 otpp, st;
-
- /* record word offset of General Use Region for various chipcommon revs */
- if (oi->sih->ccrev == 21 || oi->sih->ccrev == 24
- || oi->sih->ccrev == 27) {
- oi->otpgu_base = REVA4_OTPGU_BASE;
- } else if (oi->sih->ccrev == 36) {
- /* OTP size greater than equal to 2KB (128 words), otpgu_base is similar to rev23 */
- if (oi->wsize >= 128)
- oi->otpgu_base = REVB8_OTPGU_BASE;
- else
- oi->otpgu_base = REV36_OTPGU_BASE;
- } else if (oi->sih->ccrev == 23 || oi->sih->ccrev >= 25) {
- oi->otpgu_base = REVB8_OTPGU_BASE;
- }
-
- /* First issue an init command so the status is up to date */
- otpp =
- OTPP_START_BUSY | ((OTPPOC_INIT << OTPP_OC_SHIFT) & OTPP_OC_MASK);
-
- W_REG(&cc->otpprog, otpp);
- for (k = 0;
- ((st = R_REG(&cc->otpprog)) & OTPP_START_BUSY)
- && (k < OTPP_TRIES); k++)
- ;
- if (k >= OTPP_TRIES) {
- return;
- }
-
- /* Read OTP lock bits and subregion programmed indication bits */
- oi->status = R_REG(&cc->otpstatus);
-
- if ((oi->sih->chip == BCM43224_CHIP_ID)
- || (oi->sih->chip == BCM43225_CHIP_ID)) {
- u32 p_bits;
- p_bits =
- (ipxotp_otpr(oi, cc, oi->otpgu_base + OTPGU_P_OFF) &
- OTPGU_P_MSK)
- >> OTPGU_P_SHIFT;
- oi->status |= (p_bits << OTPS_GUP_SHIFT);
- }
-
- /*
- * h/w region base and fuse region limit are fixed to the top and
- * the bottom of the general use region. Everything else can be flexible.
- */
- oi->hwbase = oi->otpgu_base + OTPGU_SROM_OFF;
- oi->hwlim = oi->wsize;
- if (oi->status & OTPS_GUP_HW) {
- oi->hwlim =
- ipxotp_otpr(oi, cc, oi->otpgu_base + OTPGU_HSB_OFF) / 16;
- oi->swbase = oi->hwlim;
- } else
- oi->swbase = oi->hwbase;
-
- /* subtract fuse and checksum from beginning */
- oi->swlim = ipxotp_max_rgnsz(oi->sih, oi->wsize) / 2;
-
- if (oi->status & OTPS_GUP_SW) {
- oi->swlim =
- ipxotp_otpr(oi, cc, oi->otpgu_base + OTPGU_SFB_OFF) / 16;
- oi->fbase = oi->swlim;
- } else
- oi->fbase = oi->swbase;
-
- oi->flim = oi->wsize;
-}
-
-static void *ipxotp_init(si_t *sih)
-{
- uint idx;
- chipcregs_t *cc;
- otpinfo_t *oi;
-
- /* Make sure we're running IPX OTP */
- ASSERT(OTPTYPE_IPX(sih->ccrev));
- if (!OTPTYPE_IPX(sih->ccrev))
- return NULL;
-
- /* Make sure OTP is not disabled */
- if (si_is_otp_disabled(sih)) {
- return NULL;
- }
-
- /* Make sure OTP is powered up */
- if (!si_is_otp_powered(sih)) {
- return NULL;
- }
-
- oi = &otpinfo;
-
- /* Check for otp size */
- switch ((sih->cccaps & CC_CAP_OTPSIZE) >> CC_CAP_OTPSIZE_SHIFT) {
- case 0:
- /* Nothing there */
- return NULL;
- case 1: /* 32x64 */
- oi->rows = 32;
- oi->cols = 64;
- oi->wsize = 128;
- break;
- case 2: /* 64x64 */
- oi->rows = 64;
- oi->cols = 64;
- oi->wsize = 256;
- break;
- case 5: /* 96x64 */
- oi->rows = 96;
- oi->cols = 64;
- oi->wsize = 384;
- break;
- case 7: /* 16x64 *//* 1024 bits */
- oi->rows = 16;
- oi->cols = 64;
- oi->wsize = 64;
- break;
- default:
- /* Don't know the geometry */
- return NULL;
- }
-
- /* Retrieve OTP region info */
- idx = si_coreidx(sih);
- cc = si_setcoreidx(sih, SI_CC_IDX);
- ASSERT(cc != NULL);
-
- _ipxotp_init(oi, cc);
-
- si_setcoreidx(sih, idx);
-
- return (void *)oi;
-}
-
-static int ipxotp_read_region(void *oh, int region, u16 *data, uint *wlen)
-{
- otpinfo_t *oi = (otpinfo_t *) oh;
- uint idx;
- chipcregs_t *cc;
- uint base, i, sz;
-
- /* Validate region selection */
- switch (region) {
- case OTP_HW_RGN:
- sz = (uint) oi->hwlim - oi->hwbase;
- if (!(oi->status & OTPS_GUP_HW)) {
- *wlen = sz;
- return BCME_NOTFOUND;
- }
- if (*wlen < sz) {
- *wlen = sz;
- return BCME_BUFTOOSHORT;
- }
- base = oi->hwbase;
- break;
- case OTP_SW_RGN:
- sz = ((uint) oi->swlim - oi->swbase);
- if (!(oi->status & OTPS_GUP_SW)) {
- *wlen = sz;
- return BCME_NOTFOUND;
- }
- if (*wlen < sz) {
- *wlen = sz;
- return BCME_BUFTOOSHORT;
- }
- base = oi->swbase;
- break;
- case OTP_CI_RGN:
- sz = OTPGU_CI_SZ;
- if (!(oi->status & OTPS_GUP_CI)) {
- *wlen = sz;
- return BCME_NOTFOUND;
- }
- if (*wlen < sz) {
- *wlen = sz;
- return BCME_BUFTOOSHORT;
- }
- base = oi->otpgu_base + OTPGU_CI_OFF;
- break;
- case OTP_FUSE_RGN:
- sz = (uint) oi->flim - oi->fbase;
- if (!(oi->status & OTPS_GUP_FUSE)) {
- *wlen = sz;
- return BCME_NOTFOUND;
- }
- if (*wlen < sz) {
- *wlen = sz;
- return BCME_BUFTOOSHORT;
- }
- base = oi->fbase;
- break;
- case OTP_ALL_RGN:
- sz = ((uint) oi->flim - oi->hwbase);
- if (!(oi->status & (OTPS_GUP_HW | OTPS_GUP_SW))) {
- *wlen = sz;
- return BCME_NOTFOUND;
- }
- if (*wlen < sz) {
- *wlen = sz;
- return BCME_BUFTOOSHORT;
- }
- base = oi->hwbase;
- break;
- default:
- return BCME_BADARG;
- }
-
- idx = si_coreidx(oi->sih);
- cc = si_setcoreidx(oi->sih, SI_CC_IDX);
- ASSERT(cc != NULL);
-
- /* Read the data */
- for (i = 0; i < sz; i++)
- data[i] = ipxotp_otpr(oh, cc, base + i);
-
- si_setcoreidx(oi->sih, idx);
- *wlen = sz;
- return 0;
-}
-
-static int ipxotp_nvread(void *oh, char *data, uint *len)
-{
- return BCME_UNSUPPORTED;
-}
-
-static otp_fn_t ipxotp_fn = {
- (otp_size_t) ipxotp_size,
- (otp_read_bit_t) ipxotp_read_bit,
-
- (otp_init_t) ipxotp_init,
- (otp_read_region_t) ipxotp_read_region,
- (otp_nvread_t) ipxotp_nvread,
-
- (otp_status_t) ipxotp_status
-};
-
-#endif /* BCMIPXOTP */
-
-/*
- * HND OTP Code
- *
- * Exported functions:
- * hndotp_status()
- * hndotp_size()
- * hndotp_init()
- * hndotp_read_bit()
- * hndotp_read_region()
- * hndotp_nvread()
- *
- */
-
-#ifdef BCMHNDOTP
-
-/* Fields in otpstatus */
-#define OTPS_PROGFAIL 0x80000000
-#define OTPS_PROTECT 0x00000007
-#define OTPS_HW_PROTECT 0x00000001
-#define OTPS_SW_PROTECT 0x00000002
-#define OTPS_CID_PROTECT 0x00000004
-#define OTPS_RCEV_MSK 0x00003f00
-#define OTPS_RCEV_SHIFT 8
-
-/* Fields in the otpcontrol register */
-#define OTPC_RECWAIT 0xff000000
-#define OTPC_PROGWAIT 0x00ffff00
-#define OTPC_PRW_SHIFT 8
-#define OTPC_MAXFAIL 0x00000038
-#define OTPC_VSEL 0x00000006
-#define OTPC_SELVL 0x00000001
-
-/* OTP regions (Word offsets from otp size) */
-#define OTP_SWLIM_OFF (-4)
-#define OTP_CIDBASE_OFF 0
-#define OTP_CIDLIM_OFF 4
-
-/* Predefined OTP words (Word offset from otp size) */
-#define OTP_BOUNDARY_OFF (-4)
-#define OTP_HWSIGN_OFF (-3)
-#define OTP_SWSIGN_OFF (-2)
-#define OTP_CIDSIGN_OFF (-1)
-#define OTP_CID_OFF 0
-#define OTP_PKG_OFF 1
-#define OTP_FID_OFF 2
-#define OTP_RSV_OFF 3
-#define OTP_LIM_OFF 4
-#define OTP_RD_OFF 4 /* Redundancy row starts here */
-#define OTP_RC0_OFF 28 /* Redundancy control word 1 */
-#define OTP_RC1_OFF 32 /* Redundancy control word 2 */
-#define OTP_RC_LIM_OFF 36 /* Redundancy control word end */
-
-#define OTP_HW_REGION OTPS_HW_PROTECT
-#define OTP_SW_REGION OTPS_SW_PROTECT
-#define OTP_CID_REGION OTPS_CID_PROTECT
-
-#if OTP_HW_REGION != OTP_HW_RGN
-#error "incompatible OTP_HW_RGN"
-#endif
-#if OTP_SW_REGION != OTP_SW_RGN
-#error "incompatible OTP_SW_RGN"
-#endif
-#if OTP_CID_REGION != OTP_CI_RGN
-#error "incompatible OTP_CI_RGN"
-#endif
-
-/* Redundancy entry definitions */
-#define OTP_RCE_ROW_SZ 6
-#define OTP_RCE_SIGN_MASK 0x7fff
-#define OTP_RCE_ROW_MASK 0x3f
-#define OTP_RCE_BITS 21
-#define OTP_RCE_SIGN_SZ 15
-#define OTP_RCE_BIT0 1
-
-#define OTP_WPR 4
-#define OTP_SIGNATURE 0x578a
-#define OTP_MAGIC 0x4e56
-
-static int hndotp_status(void *oh)
-{
- otpinfo_t *oi = (otpinfo_t *) oh;
- return (int)(oi->hwprot | oi->signvalid);
-}
-
-static int hndotp_size(void *oh)
-{
- otpinfo_t *oi = (otpinfo_t *) oh;
- return (int)(oi->size);
-}
-
-static u16 hndotp_otpr(void *oh, chipcregs_t *cc, uint wn)
-{
-#ifdef BCMDBG
- otpinfo_t *oi = (otpinfo_t *) oh;
-#endif
- volatile u16 *ptr;
-
- ASSERT(wn < ((oi->size / 2) + OTP_RC_LIM_OFF));
- ASSERT(cc != NULL);
-
- ptr = (volatile u16 *)((volatile char *)cc + CC_SROM_OTP);
- return R_REG(&ptr[wn]);
-}
-
-static u16 hndotp_otproff(void *oh, chipcregs_t *cc, int woff)
-{
- otpinfo_t *oi = (otpinfo_t *) oh;
- volatile u16 *ptr;
-
- ASSERT(woff >= (-((int)oi->size / 2)));
- ASSERT(woff < OTP_LIM_OFF);
- ASSERT(cc != NULL);
-
- ptr = (volatile u16 *)((volatile char *)cc + CC_SROM_OTP);
-
- return R_REG(&ptr[(oi->size / 2) + woff]);
-}
-
-static u16 hndotp_read_bit(void *oh, chipcregs_t *cc, uint idx)
-{
- uint k, row, col;
- u32 otpp, st;
-
- row = idx / 65;
- col = idx % 65;
-
- otpp = OTPP_START_BUSY | OTPP_READ |
- ((row << OTPP_ROW_SHIFT) & OTPP_ROW_MASK) | (col & OTPP_COL_MASK);
-
- W_REG(&cc->otpprog, otpp);
- st = R_REG(&cc->otpprog);
- for (k = 0;
- ((st & OTPP_START_BUSY) == OTPP_START_BUSY) && (k < OTPP_TRIES);
- k++)
- st = R_REG(&cc->otpprog);
-
- if (k >= OTPP_TRIES) {
- return 0xffff;
- }
- if (st & OTPP_READERR) {
- return 0xffff;
- }
- st = (st & OTPP_VALUE_MASK) >> OTPP_VALUE_SHIFT;
- return (u16) st;
-}
-
-static void *hndotp_init(si_t *sih)
-{
- uint idx;
- chipcregs_t *cc;
- otpinfo_t *oi;
- u32 cap = 0, clkdiv, otpdiv = 0;
- void *ret = NULL;
-
- oi = &otpinfo;
-
- idx = si_coreidx(sih);
-
- /* Check for otp */
- cc = si_setcoreidx(sih, SI_CC_IDX);
- if (cc != NULL) {
- cap = R_REG(&cc->capabilities);
- if ((cap & CC_CAP_OTPSIZE) == 0) {
- /* Nothing there */
- goto out;
- }
-
- /* As of right now, support only 4320a2, 4311a1 and 4312 */
- ASSERT((oi->ccrev == 12) || (oi->ccrev == 17)
- || (oi->ccrev == 22));
- if (!
- ((oi->ccrev == 12) || (oi->ccrev == 17)
- || (oi->ccrev == 22)))
- return NULL;
-
- /* Read the OTP byte size. chipcommon rev >= 18 has RCE so the size is
- * 8 row (64 bytes) smaller
- */
- oi->size =
- 1 << (((cap & CC_CAP_OTPSIZE) >> CC_CAP_OTPSIZE_SHIFT)
- + CC_CAP_OTPSIZE_BASE);
- if (oi->ccrev >= 18)
- oi->size -= ((OTP_RC0_OFF - OTP_BOUNDARY_OFF) * 2);
-
- oi->hwprot = (int)(R_REG(&cc->otpstatus) & OTPS_PROTECT);
- oi->boundary = -1;
-
- /* Check the region signature */
- if (hndotp_otproff(oi, cc, OTP_HWSIGN_OFF) == OTP_SIGNATURE) {
- oi->signvalid |= OTP_HW_REGION;
- oi->boundary = hndotp_otproff(oi, cc, OTP_BOUNDARY_OFF);
- }
-
- if (hndotp_otproff(oi, cc, OTP_SWSIGN_OFF) == OTP_SIGNATURE)
- oi->signvalid |= OTP_SW_REGION;
-
- if (hndotp_otproff(oi, cc, OTP_CIDSIGN_OFF) == OTP_SIGNATURE)
- oi->signvalid |= OTP_CID_REGION;
-
- /* Set OTP clkdiv for stability */
- if (oi->ccrev == 22)
- otpdiv = 12;
-
- if (otpdiv) {
- clkdiv = R_REG(&cc->clkdiv);
- clkdiv =
- (clkdiv & ~CLKD_OTP) | (otpdiv << CLKD_OTP_SHIFT);
- W_REG(&cc->clkdiv, clkdiv);
- }
- udelay(10);
-
- ret = (void *)oi;
- }
-
- out: /* All done */
- si_setcoreidx(sih, idx);
-
- return ret;
-}
-
-static int hndotp_read_region(void *oh, int region, u16 *data, uint *wlen)
-{
- otpinfo_t *oi = (otpinfo_t *) oh;
- u32 idx, st;
- chipcregs_t *cc;
- int i;
-
- /* Only support HW region (no active chips use HND OTP SW region) */
- ASSERT(region == OTP_HW_REGION);
-
- /* Region empty? */
- st = oi->hwprot | oi->signvalid;
- if ((st & region) == 0)
- return BCME_NOTFOUND;
-
- *wlen =
- ((int)*wlen < oi->boundary / 2) ? *wlen : (uint) oi->boundary / 2;
-
- idx = si_coreidx(oi->sih);
- cc = si_setcoreidx(oi->sih, SI_CC_IDX);
- ASSERT(cc != NULL);
-
- for (i = 0; i < (int)*wlen; i++)
- data[i] = hndotp_otpr(oh, cc, i);
-
- si_setcoreidx(oi->sih, idx);
-
- return 0;
-}
-
-static int hndotp_nvread(void *oh, char *data, uint *len)
-{
- int rc = 0;
- otpinfo_t *oi = (otpinfo_t *) oh;
- u32 base, bound, lim = 0, st;
- int i, chunk, gchunks, tsz = 0;
- u32 idx;
- chipcregs_t *cc;
- uint offset;
- u16 *rawotp = NULL;
-
- /* save the orig core */
- idx = si_coreidx(oi->sih);
- cc = si_setcoreidx(oi->sih, SI_CC_IDX);
- ASSERT(cc != NULL);
-
- st = hndotp_status(oh);
- if (!(st & (OTP_HW_REGION | OTP_SW_REGION))) {
- rc = -1;
- goto out;
- }
-
- /* Read the whole otp so we can easily manipulate it */
- lim = hndotp_size(oh);
- rawotp = kmalloc(lim, GFP_ATOMIC);
- if (rawotp == NULL) {
- rc = -2;
- goto out;
- }
- for (i = 0; i < (int)(lim / 2); i++)
- rawotp[i] = hndotp_otpr(oh, cc, i);
-
- if ((st & OTP_HW_REGION) == 0) {
- /* This could be a programming failure in the first
- * chunk followed by one or more good chunks
- */
- for (i = 0; i < (int)(lim / 2); i++)
- if (rawotp[i] == OTP_MAGIC)
- break;
-
- if (i < (int)(lim / 2)) {
- base = i;
- bound = (i * 2) + rawotp[i + 1];
- } else {
- rc = -3;
- goto out;
- }
- } else {
- bound = rawotp[(lim / 2) + OTP_BOUNDARY_OFF];
-
- /* There are two cases: 1) The whole otp is used as nvram
- * and 2) There is a hardware header followed by nvram.
- */
- if (rawotp[0] == OTP_MAGIC) {
- base = 0;
- } else
- base = bound;
- }
-
- /* Find and copy the data */
-
- chunk = 0;
- gchunks = 0;
- i = base / 2;
- offset = 0;
- while ((i < (int)(lim / 2)) && (rawotp[i] == OTP_MAGIC)) {
- int dsz, rsz = rawotp[i + 1];
-
- if (((i * 2) + rsz) >= (int)lim) {
- /* Bad length, try to find another chunk anyway */
- rsz = 6;
- }
- if (hndcrc16((u8 *) &rawotp[i], rsz,
- CRC16_INIT_VALUE) == CRC16_GOOD_VALUE) {
- /* Good crc, copy the vars */
- gchunks++;
- dsz = rsz - 6;
- tsz += dsz;
- if (offset + dsz >= *len) {
- goto out;
- }
- memcpy(&data[offset], &rawotp[i + 2], dsz);
- offset += dsz;
- /* Remove extra null characters at the end */
- while (offset > 1 &&
- data[offset - 1] == 0 && data[offset - 2] == 0)
- offset--;
- i += rsz / 2;
- } else {
- /* bad length or crc didn't check, try to find the next set */
- if (rawotp[i + (rsz / 2)] == OTP_MAGIC) {
- /* Assume length is good */
- i += rsz / 2;
- } else {
- while (++i < (int)(lim / 2))
- if (rawotp[i] == OTP_MAGIC)
- break;
- }
- }
- chunk++;
- }
-
- *len = offset;
-
- out:
- kfree(rawotp);
- si_setcoreidx(oi->sih, idx);
-
- return rc;
-}
-
-static otp_fn_t hndotp_fn = {
- (otp_size_t) hndotp_size,
- (otp_read_bit_t) hndotp_read_bit,
-
- (otp_init_t) hndotp_init,
- (otp_read_region_t) hndotp_read_region,
- (otp_nvread_t) hndotp_nvread,
-
- (otp_status_t) hndotp_status
-};
-
-#endif /* BCMHNDOTP */
-
-/*
- * Common Code: Compiled for IPX / HND / AUTO
- * otp_status()
- * otp_size()
- * otp_read_bit()
- * otp_init()
- * otp_read_region()
- * otp_nvread()
- */
-
-int otp_status(void *oh)
-{
- otpinfo_t *oi = (otpinfo_t *) oh;
-
- return oi->fn->status(oh);
-}
-
-int otp_size(void *oh)
-{
- otpinfo_t *oi = (otpinfo_t *) oh;
-
- return oi->fn->size(oh);
-}
-
-u16 otp_read_bit(void *oh, uint offset)
-{
- otpinfo_t *oi = (otpinfo_t *) oh;
- uint idx = si_coreidx(oi->sih);
- chipcregs_t *cc = si_setcoreidx(oi->sih, SI_CC_IDX);
- u16 readBit = (u16) oi->fn->read_bit(oh, cc, offset);
- si_setcoreidx(oi->sih, idx);
- return readBit;
-}
-
-void *otp_init(si_t *sih)
-{
- otpinfo_t *oi;
- void *ret = NULL;
-
- oi = &otpinfo;
- memset(oi, 0, sizeof(otpinfo_t));
-
- oi->ccrev = sih->ccrev;
-
-#ifdef BCMIPXOTP
- if (OTPTYPE_IPX(oi->ccrev))
- oi->fn = &ipxotp_fn;
-#endif
-
-#ifdef BCMHNDOTP
- if (OTPTYPE_HND(oi->ccrev))
- oi->fn = &hndotp_fn;
-#endif
-
- if (oi->fn == NULL) {
- return NULL;
- }
-
- oi->sih = sih;
-
- ret = (oi->fn->init) (sih);
-
- return ret;
-}
-
-int
-otp_read_region(si_t *sih, int region, u16 *data,
- uint *wlen) {
- bool wasup = false;
- void *oh;
- int err = 0;
-
- wasup = si_is_otp_powered(sih);
- if (!wasup)
- si_otp_power(sih, true);
-
- if (!si_is_otp_powered(sih) || si_is_otp_disabled(sih)) {
- err = BCME_NOTREADY;
- goto out;
- }
-
- oh = otp_init(sih);
- if (oh == NULL) {
- err = BCME_ERROR;
- goto out;
- }
-
- err = (((otpinfo_t *) oh)->fn->read_region) (oh, region, data, wlen);
-
- out:
- if (!wasup)
- si_otp_power(sih, false);
-
- return err;
-}
-
-int otp_nvread(void *oh, char *data, uint *len)
-{
- otpinfo_t *oi = (otpinfo_t *) oh;
-
- return oi->fn->nvread(oh, data, len);
-}
diff --git a/drivers/staging/brcm80211/util/bcmsrom.c b/drivers/staging/brcm80211/util/bcmsrom.c
deleted file mode 100644
index 850bfa6..0000000
--- a/drivers/staging/brcm80211/util/bcmsrom.c
+++ /dev/null
@@ -1,2088 +0,0 @@
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-#include <linux/kernel.h>
-#include <linux/string.h>
-#include <linux/etherdevice.h>
-#include <bcmdefs.h>
-#include <linux/module.h>
-#include <linux/pci.h>
-#include <stdarg.h>
-#include <bcmutils.h>
-#include <hndsoc.h>
-#include <sbchipc.h>
-#include <bcmdevs.h>
-#include <pcicfg.h>
-#include <siutils.h>
-#include <bcmsrom.h>
-#include <bcmsrom_tbl.h>
-#ifdef BCMSDIO
-#include <bcmsdh.h>
-#include <sdio.h>
-#endif
-
-#include <bcmnvram.h>
-#include <bcmotp.h>
-
-#if defined(BCMSDIO)
-#include <sbsdio.h>
-#include <sbhnddma.h>
-#include <sbsdpcmdev.h>
-#endif
-
-#include <linux/if_ether.h>
-
-#define BS_ERROR(args)
-
-#define SROM_OFFSET(sih) ((sih->ccrev > 31) ? \
- (((sih->cccaps & CC_CAP_SROM) == 0) ? NULL : \
- ((u8 *)curmap + PCI_16KB0_CCREGS_OFFSET + CC_SROM_OTP)) : \
- ((u8 *)curmap + PCI_BAR0_SPROM_OFFSET))
-
-#if defined(BCMDBG)
-#define WRITE_ENABLE_DELAY 500 /* 500 ms after write enable/disable toggle */
-#define WRITE_WORD_DELAY 20 /* 20 ms between each word write */
-#endif
-
-typedef struct varbuf {
- char *base; /* pointer to buffer base */
- char *buf; /* pointer to current position */
- unsigned int size; /* current (residual) size in bytes */
-} varbuf_t;
-extern char *_vars;
-extern uint _varsz;
-
-#define SROM_CIS_SINGLE 1
-
-static int initvars_srom_si(si_t *sih, void *curmap, char **vars, uint *count);
-static void _initvars_srom_pci(u8 sromrev, u16 *srom, uint off, varbuf_t *b);
-static int initvars_srom_pci(si_t *sih, void *curmap, char **vars, uint *count);
-static int initvars_flash_si(si_t *sih, char **vars, uint *count);
-#ifdef BCMSDIO
-static int initvars_cis_sdio(char **vars, uint *count);
-static int sprom_cmd_sdio(u8 cmd);
-static int sprom_read_sdio(u16 addr, u16 *data);
-#endif /* BCMSDIO */
-static int sprom_read_pci(si_t *sih, u16 *sprom,
- uint wordoff, u16 *buf, uint nwords, bool check_crc);
-#if defined(BCMNVRAMR)
-static int otp_read_pci(si_t *sih, u16 *buf, uint bufsz);
-#endif
-static u16 srom_cc_cmd(si_t *sih, void *ccregs, u32 cmd,
- uint wordoff, u16 data);
-
-static int initvars_table(char *start, char *end,
- char **vars, uint *count);
-static int initvars_flash(si_t *sih, char **vp,
- uint len);
-
-/* Initialization of varbuf structure */
-static void varbuf_init(varbuf_t *b, char *buf, uint size)
-{
- b->size = size;
- b->base = b->buf = buf;
-}
-
-/* append a null terminated var=value string */
-static int varbuf_append(varbuf_t *b, const char *fmt, ...)
-{
- va_list ap;
- int r;
- size_t len;
- char *s;
-
- if (b->size < 2)
- return 0;
-
- va_start(ap, fmt);
- r = vsnprintf(b->buf, b->size, fmt, ap);
- va_end(ap);
-
- /* C99 snprintf behavior returns r >= size on overflow,
- * others return -1 on overflow.
- * All return -1 on format error.
- * We need to leave room for 2 null terminations, one for the current var
- * string, and one for final null of the var table. So check that the
- * strlen written, r, leaves room for 2 chars.
- */
- if ((r == -1) || (r > (int)(b->size - 2))) {
- b->size = 0;
- return 0;
- }
-
- /* Remove any earlier occurrence of the same variable */
- s = strchr(b->buf, '=');
- if (s != NULL) {
- len = (size_t) (s - b->buf);
- for (s = b->base; s < b->buf;) {
- if ((memcmp(s, b->buf, len) == 0) && s[len] == '=') {
- len = strlen(s) + 1;
- memmove(s, (s + len),
- ((b->buf + r + 1) - (s + len)));
- b->buf -= len;
- b->size += (unsigned int)len;
- break;
- }
-
- while (*s++)
- ;
- }
- }
-
- /* skip over this string's null termination */
- r++;
- b->size -= r;
- b->buf += r;
-
- return r;
-}
-
-/*
- * Initialize local vars from the right source for this platform.
- * Return 0 on success, nonzero on error.
- */
-int srom_var_init(si_t *sih, uint bustype, void *curmap,
- char **vars, uint *count)
-{
- uint len;
-
- len = 0;
-
- ASSERT(bustype == bustype);
- if (vars == NULL || count == NULL)
- return 0;
-
- *vars = NULL;
- *count = 0;
-
- switch (bustype) {
- case SI_BUS:
- case JTAG_BUS:
- return initvars_srom_si(sih, curmap, vars, count);
-
- case PCI_BUS:
- ASSERT(curmap != NULL);
- if (curmap == NULL)
- return -1;
-
- return initvars_srom_pci(sih, curmap, vars, count);
-
-#ifdef BCMSDIO
- case SDIO_BUS:
- return initvars_cis_sdio(vars, count);
-#endif /* BCMSDIO */
-
- default:
- ASSERT(0);
- }
- return -1;
-}
-
-/* support only 16-bit word read from srom */
-int
-srom_read(si_t *sih, uint bustype, void *curmap,
- uint byteoff, uint nbytes, u16 *buf, bool check_crc)
-{
- uint off, nw;
-#ifdef BCMSDIO
- uint i;
-#endif /* BCMSDIO */
-
- ASSERT(bustype == bustype);
-
- /* check input - 16-bit access only */
- if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > SROM_MAX)
- return 1;
-
- off = byteoff / 2;
- nw = nbytes / 2;
-
- if (bustype == PCI_BUS) {
- if (!curmap)
- return 1;
-
- if (si_is_sprom_available(sih)) {
- u16 *srom;
-
- srom = (u16 *) SROM_OFFSET(sih);
- if (srom == NULL)
- return 1;
-
- if (sprom_read_pci
- (sih, srom, off, buf, nw, check_crc))
- return 1;
- }
-#if defined(BCMNVRAMR)
- else {
- if (otp_read_pci(sih, buf, SROM_MAX))
- return 1;
- }
-#endif
-#ifdef BCMSDIO
- } else if (bustype == SDIO_BUS) {
- off = byteoff / 2;
- nw = nbytes / 2;
- for (i = 0; i < nw; i++) {
- if (sprom_read_sdio
- ((u16) (off + i), (u16 *) (buf + i)))
- return 1;
- }
-#endif /* BCMSDIO */
- } else if (bustype == SI_BUS) {
- return 1;
- } else {
- return 1;
- }
-
- return 0;
-}
-
-static const char vstr_manf[] = "manf=%s";
-static const char vstr_productname[] = "productname=%s";
-static const char vstr_manfid[] = "manfid=0x%x";
-static const char vstr_prodid[] = "prodid=0x%x";
-#ifdef BCMSDIO
-static const char vstr_sdmaxspeed[] = "sdmaxspeed=%d";
-static const char vstr_sdmaxblk[][13] = {
-"sdmaxblk0=%d", "sdmaxblk1=%d", "sdmaxblk2=%d"};
-#endif
-static const char vstr_regwindowsz[] = "regwindowsz=%d";
-static const char vstr_sromrev[] = "sromrev=%d";
-static const char vstr_chiprev[] = "chiprev=%d";
-static const char vstr_subvendid[] = "subvendid=0x%x";
-static const char vstr_subdevid[] = "subdevid=0x%x";
-static const char vstr_boardrev[] = "boardrev=0x%x";
-static const char vstr_aa2g[] = "aa2g=0x%x";
-static const char vstr_aa5g[] = "aa5g=0x%x";
-static const char vstr_ag[] = "ag%d=0x%x";
-static const char vstr_cc[] = "cc=%d";
-static const char vstr_opo[] = "opo=%d";
-static const char vstr_pa0b[][9] = {
-"pa0b0=%d", "pa0b1=%d", "pa0b2=%d"};
-
-static const char vstr_pa0itssit[] = "pa0itssit=%d";
-static const char vstr_pa0maxpwr[] = "pa0maxpwr=%d";
-static const char vstr_pa1b[][9] = {
-"pa1b0=%d", "pa1b1=%d", "pa1b2=%d"};
-
-static const char vstr_pa1lob[][11] = {
-"pa1lob0=%d", "pa1lob1=%d", "pa1lob2=%d"};
-
-static const char vstr_pa1hib[][11] = {
-"pa1hib0=%d", "pa1hib1=%d", "pa1hib2=%d"};
-
-static const char vstr_pa1itssit[] = "pa1itssit=%d";
-static const char vstr_pa1maxpwr[] = "pa1maxpwr=%d";
-static const char vstr_pa1lomaxpwr[] = "pa1lomaxpwr=%d";
-static const char vstr_pa1himaxpwr[] = "pa1himaxpwr=%d";
-static const char vstr_oem[] =
- "oem=%02x%02x%02x%02x%02x%02x%02x%02x";
-static const char vstr_boardflags[] = "boardflags=0x%x";
-static const char vstr_boardflags2[] = "boardflags2=0x%x";
-static const char vstr_ledbh[] = "ledbh%d=0x%x";
-static const char vstr_noccode[] = "ccode=0x0";
-static const char vstr_ccode[] = "ccode=%c%c";
-static const char vstr_cctl[] = "cctl=0x%x";
-static const char vstr_cckpo[] = "cckpo=0x%x";
-static const char vstr_ofdmpo[] = "ofdmpo=0x%x";
-static const char vstr_rdlid[] = "rdlid=0x%x";
-static const char vstr_rdlrndis[] = "rdlrndis=%d";
-static const char vstr_rdlrwu[] = "rdlrwu=%d";
-static const char vstr_usbfs[] = "usbfs=%d";
-static const char vstr_wpsgpio[] = "wpsgpio=%d";
-static const char vstr_wpsled[] = "wpsled=%d";
-static const char vstr_rdlsn[] = "rdlsn=%d";
-static const char vstr_rssismf2g[] = "rssismf2g=%d";
-static const char vstr_rssismc2g[] = "rssismc2g=%d";
-static const char vstr_rssisav2g[] = "rssisav2g=%d";
-static const char vstr_bxa2g[] = "bxa2g=%d";
-static const char vstr_rssismf5g[] = "rssismf5g=%d";
-static const char vstr_rssismc5g[] = "rssismc5g=%d";
-static const char vstr_rssisav5g[] = "rssisav5g=%d";
-static const char vstr_bxa5g[] = "bxa5g=%d";
-static const char vstr_tri2g[] = "tri2g=%d";
-static const char vstr_tri5gl[] = "tri5gl=%d";
-static const char vstr_tri5g[] = "tri5g=%d";
-static const char vstr_tri5gh[] = "tri5gh=%d";
-static const char vstr_rxpo2g[] = "rxpo2g=%d";
-static const char vstr_rxpo5g[] = "rxpo5g=%d";
-static const char vstr_boardtype[] = "boardtype=0x%x";
-static const char vstr_leddc[] = "leddc=0x%04x";
-static const char vstr_vendid[] = "vendid=0x%x";
-static const char vstr_devid[] = "devid=0x%x";
-static const char vstr_xtalfreq[] = "xtalfreq=%d";
-static const char vstr_txchain[] = "txchain=0x%x";
-static const char vstr_rxchain[] = "rxchain=0x%x";
-static const char vstr_antswitch[] = "antswitch=0x%x";
-static const char vstr_regrev[] = "regrev=0x%x";
-static const char vstr_antswctl2g[] = "antswctl2g=0x%x";
-static const char vstr_triso2g[] = "triso2g=0x%x";
-static const char vstr_pdetrange2g[] = "pdetrange2g=0x%x";
-static const char vstr_extpagain2g[] = "extpagain2g=0x%x";
-static const char vstr_tssipos2g[] = "tssipos2g=0x%x";
-static const char vstr_antswctl5g[] = "antswctl5g=0x%x";
-static const char vstr_triso5g[] = "triso5g=0x%x";
-static const char vstr_pdetrange5g[] = "pdetrange5g=0x%x";
-static const char vstr_extpagain5g[] = "extpagain5g=0x%x";
-static const char vstr_tssipos5g[] = "tssipos5g=0x%x";
-static const char vstr_maxp2ga0[] = "maxp2ga0=0x%x";
-static const char vstr_itt2ga0[] = "itt2ga0=0x%x";
-static const char vstr_pa[] = "pa%dgw%da%d=0x%x";
-static const char vstr_pahl[] = "pa%dg%cw%da%d=0x%x";
-static const char vstr_maxp5ga0[] = "maxp5ga0=0x%x";
-static const char vstr_itt5ga0[] = "itt5ga0=0x%x";
-static const char vstr_maxp5gha0[] = "maxp5gha0=0x%x";
-static const char vstr_maxp5gla0[] = "maxp5gla0=0x%x";
-static const char vstr_maxp2ga1[] = "maxp2ga1=0x%x";
-static const char vstr_itt2ga1[] = "itt2ga1=0x%x";
-static const char vstr_maxp5ga1[] = "maxp5ga1=0x%x";
-static const char vstr_itt5ga1[] = "itt5ga1=0x%x";
-static const char vstr_maxp5gha1[] = "maxp5gha1=0x%x";
-static const char vstr_maxp5gla1[] = "maxp5gla1=0x%x";
-static const char vstr_cck2gpo[] = "cck2gpo=0x%x";
-static const char vstr_ofdm2gpo[] = "ofdm2gpo=0x%x";
-static const char vstr_ofdm5gpo[] = "ofdm5gpo=0x%x";
-static const char vstr_ofdm5glpo[] = "ofdm5glpo=0x%x";
-static const char vstr_ofdm5ghpo[] = "ofdm5ghpo=0x%x";
-static const char vstr_cddpo[] = "cddpo=0x%x";
-static const char vstr_stbcpo[] = "stbcpo=0x%x";
-static const char vstr_bw40po[] = "bw40po=0x%x";
-static const char vstr_bwduppo[] = "bwduppo=0x%x";
-static const char vstr_mcspo[] = "mcs%dgpo%d=0x%x";
-static const char vstr_mcspohl[] = "mcs%dg%cpo%d=0x%x";
-static const char vstr_custom[] = "customvar%d=0x%x";
-static const char vstr_cckdigfilttype[] = "cckdigfilttype=%d";
-static const char vstr_boardnum[] = "boardnum=%d";
-static const char vstr_macaddr[] = "macaddr=%s";
-static const char vstr_usbepnum[] = "usbepnum=0x%x";
-static const char vstr_end[] = "END\0";
-
-u8 patch_pair;
-
-/* For dongle HW, accept partial calibration parameters */
-#define BCMDONGLECASE(n)
-
-int srom_parsecis(u8 *pcis[], uint ciscnt, char **vars,
- uint *count)
-{
- char eabuf[32];
- char *base;
- varbuf_t b;
- u8 *cis, tup, tlen, sromrev = 1;
- int i, j;
- bool ag_init = false;
- u32 w32;
- uint funcid;
- uint cisnum;
- s32 boardnum;
- int err;
- bool standard_cis;
-
- ASSERT(vars != NULL);
- ASSERT(count != NULL);
-
- boardnum = -1;
-
- base = kmalloc(MAXSZ_NVRAM_VARS, GFP_ATOMIC);
- ASSERT(base != NULL);
- if (!base)
- return -2;
-
- varbuf_init(&b, base, MAXSZ_NVRAM_VARS);
- memset(base, 0, MAXSZ_NVRAM_VARS);
- eabuf[0] = '\0';
- for (cisnum = 0; cisnum < ciscnt; cisnum++) {
- cis = *pcis++;
- i = 0;
- funcid = 0;
- standard_cis = true;
- do {
- if (standard_cis) {
- tup = cis[i++];
- if (tup == CISTPL_NULL || tup == CISTPL_END)
- tlen = 0;
- else
- tlen = cis[i++];
- } else {
- if (cis[i] == CISTPL_NULL
- || cis[i] == CISTPL_END) {
- tlen = 0;
- tup = cis[i];
- } else {
- tlen = cis[i];
- tup = CISTPL_BRCM_HNBU;
- }
- ++i;
- }
- if ((i + tlen) >= CIS_SIZE)
- break;
-
- switch (tup) {
- case CISTPL_VERS_1:
- /* assume the strings are good if the version field checks out */
- if (((cis[i + 1] << 8) + cis[i]) >= 0x0008) {
- varbuf_append(&b, vstr_manf,
- &cis[i + 2]);
- varbuf_append(&b, vstr_productname,
- &cis[i + 3 +
- strlen((char *)
- &cis[i +
- 2])]);
- break;
- }
-
- case CISTPL_MANFID:
- varbuf_append(&b, vstr_manfid,
- (cis[i + 1] << 8) + cis[i]);
- varbuf_append(&b, vstr_prodid,
- (cis[i + 3] << 8) + cis[i + 2]);
- break;
-
- case CISTPL_FUNCID:
- funcid = cis[i];
- break;
-
- case CISTPL_FUNCE:
- switch (funcid) {
- case CISTPL_FID_SDIO:
-#ifdef BCMSDIO
- if (cis[i] == 0) {
- u8 spd = cis[i + 3];
- static int base[] = {
- -1, 10, 12, 13, 15, 20,
- 25, 30,
- 35, 40, 45, 50, 55, 60,
- 70, 80
- };
- static int mult[] = {
- 10, 100, 1000, 10000,
- -1, -1, -1, -1
- };
- ASSERT((mult[spd & 0x7] != -1)
- &&
- (base
- [(spd >> 3) & 0x0f]));
- varbuf_append(&b,
- vstr_sdmaxblk[0],
- (cis[i + 2] << 8)
- + cis[i + 1]);
- varbuf_append(&b,
- vstr_sdmaxspeed,
- (mult[spd & 0x7] *
- base[(spd >> 3) &
- 0x0f]));
- } else if (cis[i] == 1) {
- varbuf_append(&b,
- vstr_sdmaxblk
- [cisnum],
- (cis[i + 13] << 8)
- | cis[i + 12]);
- }
-#endif /* BCMSDIO */
- funcid = 0;
- break;
- default:
- /* set macaddr if HNBU_MACADDR not seen yet */
- if (eabuf[0] == '\0' &&
- cis[i] == LAN_NID &&
- !is_zero_ether_addr(&cis[i + 2]) &&
- !is_multicast_ether_addr(&cis[i + 2])) {
- ASSERT(cis[i + 1] ==
- ETH_ALEN);
- snprintf(eabuf, sizeof(eabuf),
- "%pM", &cis[i + 2]);
-
- /* set boardnum if HNBU_BOARDNUM not seen yet */
- if (boardnum == -1)
- boardnum =
- (cis[i + 6] << 8) +
- cis[i + 7];
- }
- break;
- }
- break;
-
- case CISTPL_CFTABLE:
- varbuf_append(&b, vstr_regwindowsz,
- (cis[i + 7] << 8) | cis[i + 6]);
- break;
-
- case CISTPL_BRCM_HNBU:
- switch (cis[i]) {
- case HNBU_SROMREV:
- sromrev = cis[i + 1];
- varbuf_append(&b, vstr_sromrev,
- sromrev);
- break;
-
- case HNBU_XTALFREQ:
- varbuf_append(&b, vstr_xtalfreq,
- (cis[i + 4] << 24) |
- (cis[i + 3] << 16) |
- (cis[i + 2] << 8) |
- cis[i + 1]);
- break;
-
- case HNBU_CHIPID:
- varbuf_append(&b, vstr_vendid,
- (cis[i + 2] << 8) +
- cis[i + 1]);
- varbuf_append(&b, vstr_devid,
- (cis[i + 4] << 8) +
- cis[i + 3]);
- if (tlen >= 7) {
- varbuf_append(&b, vstr_chiprev,
- (cis[i + 6] << 8)
- + cis[i + 5]);
- }
- if (tlen >= 9) {
- varbuf_append(&b,
- vstr_subvendid,
- (cis[i + 8] << 8)
- + cis[i + 7]);
- }
- if (tlen >= 11) {
- varbuf_append(&b, vstr_subdevid,
- (cis[i + 10] << 8)
- + cis[i + 9]);
- /* subdevid doubles for boardtype */
- varbuf_append(&b,
- vstr_boardtype,
- (cis[i + 10] << 8)
- + cis[i + 9]);
- }
- break;
-
- case HNBU_BOARDNUM:
- boardnum =
- (cis[i + 2] << 8) + cis[i + 1];
- break;
-
- case HNBU_PATCH:
- {
- char vstr_paddr[16];
- char vstr_pdata[16];
-
- /* retrieve the patch pairs
- * from tlen/6; where 6 is
- * sizeof(patch addr(2)) +
- * sizeof(patch data(4)).
- */
- patch_pair = tlen / 6;
-
- for (j = 0; j < patch_pair; j++) {
- snprintf(vstr_paddr,
- sizeof
- (vstr_paddr),
- "pa%d=0x%%x",
- j);
- snprintf(vstr_pdata,
- sizeof
- (vstr_pdata),
- "pd%d=0x%%x",
- j);
-
- varbuf_append(&b,
- vstr_paddr,
- (cis
- [i +
- (j *
- 6) +
- 2] << 8)
- | cis[i +
- (j *
- 6)
- +
- 1]);
-
- varbuf_append(&b,
- vstr_pdata,
- (cis
- [i +
- (j *
- 6) +
- 6] <<
- 24) |
- (cis
- [i +
- (j *
- 6) +
- 5] <<
- 16) |
- (cis
- [i +
- (j *
- 6) +
- 4] << 8)
- | cis[i +
- (j *
- 6)
- +
- 3]);
- }
- }
- break;
-
- case HNBU_BOARDREV:
- if (tlen == 2)
- varbuf_append(&b, vstr_boardrev,
- cis[i + 1]);
- else
- varbuf_append(&b, vstr_boardrev,
- (cis[i + 2] << 8)
- + cis[i + 1]);
- break;
-
- case HNBU_BOARDFLAGS:
- w32 = (cis[i + 2] << 8) + cis[i + 1];
- if (tlen >= 5)
- w32 |=
- ((cis[i + 4] << 24) +
- (cis[i + 3] << 16));
- varbuf_append(&b, vstr_boardflags, w32);
-
- if (tlen >= 7) {
- w32 =
- (cis[i + 6] << 8) + cis[i +
- 5];
- if (tlen >= 9)
- w32 |=
- ((cis[i + 8] << 24)
- +
- (cis[i + 7] <<
- 16));
- varbuf_append(&b,
- vstr_boardflags2,
- w32);
- }
- break;
-
- case HNBU_USBFS:
- varbuf_append(&b, vstr_usbfs,
- cis[i + 1]);
- break;
-
- case HNBU_BOARDTYPE:
- varbuf_append(&b, vstr_boardtype,
- (cis[i + 2] << 8) +
- cis[i + 1]);
- break;
-
- case HNBU_HNBUCIS:
- /*
- * what follows is a nonstandard HNBU CIS
- * that lacks CISTPL_BRCM_HNBU tags
- *
- * skip 0xff (end of standard CIS)
- * after this tuple
- */
- tlen++;
- standard_cis = false;
- break;
-
- case HNBU_USBEPNUM:
- varbuf_append(&b, vstr_usbepnum,
- (cis[i + 2] << 8) | cis[i
- +
- 1]);
- break;
-
- case HNBU_AA:
- varbuf_append(&b, vstr_aa2g,
- cis[i + 1]);
- if (tlen >= 3)
- varbuf_append(&b, vstr_aa5g,
- cis[i + 2]);
- break;
-
- case HNBU_AG:
- varbuf_append(&b, vstr_ag, 0,
- cis[i + 1]);
- if (tlen >= 3)
- varbuf_append(&b, vstr_ag, 1,
- cis[i + 2]);
- if (tlen >= 4)
- varbuf_append(&b, vstr_ag, 2,
- cis[i + 3]);
- if (tlen >= 5)
- varbuf_append(&b, vstr_ag, 3,
- cis[i + 4]);
- ag_init = true;
- break;
-
- case HNBU_ANT5G:
- varbuf_append(&b, vstr_aa5g,
- cis[i + 1]);
- varbuf_append(&b, vstr_ag, 1,
- cis[i + 2]);
- break;
-
- case HNBU_CC:
- ASSERT(sromrev == 1);
- varbuf_append(&b, vstr_cc, cis[i + 1]);
- break;
-
- case HNBU_PAPARMS:
- switch (tlen) {
- case 2:
- ASSERT(sromrev == 1);
- varbuf_append(&b,
- vstr_pa0maxpwr,
- cis[i + 1]);
- break;
- case 10:
- ASSERT(sromrev >= 2);
- varbuf_append(&b, vstr_opo,
- cis[i + 9]);
- /* FALLTHROUGH */
- case 9:
- varbuf_append(&b,
- vstr_pa0maxpwr,
- cis[i + 8]);
- /* FALLTHROUGH */
- BCMDONGLECASE(8)
- varbuf_append(&b,
- vstr_pa0itssit,
- cis[i + 7]);
- /* FALLTHROUGH */
- BCMDONGLECASE(7)
- for (j = 0; j < 3; j++) {
- varbuf_append(&b,
- vstr_pa0b
- [j],
- (cis
- [i +
- (j *
- 2) +
- 2] << 8)
- + cis[i +
- (j *
- 2)
- +
- 1]);
- }
- break;
- default:
- ASSERT((tlen == 2)
- || (tlen == 9)
- || (tlen == 10));
- break;
- }
- break;
-
- case HNBU_PAPARMS5G:
- ASSERT((sromrev == 2)
- || (sromrev == 3));
- switch (tlen) {
- case 23:
- varbuf_append(&b,
- vstr_pa1himaxpwr,
- cis[i + 22]);
- varbuf_append(&b,
- vstr_pa1lomaxpwr,
- cis[i + 21]);
- varbuf_append(&b,
- vstr_pa1maxpwr,
- cis[i + 20]);
- /* FALLTHROUGH */
- case 20:
- varbuf_append(&b,
- vstr_pa1itssit,
- cis[i + 19]);
- /* FALLTHROUGH */
- case 19:
- for (j = 0; j < 3; j++) {
- varbuf_append(&b,
- vstr_pa1b
- [j],
- (cis
- [i +
- (j *
- 2) +
- 2] << 8)
- + cis[i +
- (j *
- 2)
- +
- 1]);
- }
- for (j = 3; j < 6; j++) {
- varbuf_append(&b,
- vstr_pa1lob
- [j - 3],
- (cis
- [i +
- (j *
- 2) +
- 2] << 8)
- + cis[i +
- (j *
- 2)
- +
- 1]);
- }
- for (j = 6; j < 9; j++) {
- varbuf_append(&b,
- vstr_pa1hib
- [j - 6],
- (cis
- [i +
- (j *
- 2) +
- 2] << 8)
- + cis[i +
- (j *
- 2)
- +
- 1]);
- }
- break;
- default:
- ASSERT((tlen == 19) ||
- (tlen == 20)
- || (tlen == 23));
- break;
- }
- break;
-
- case HNBU_OEM:
- ASSERT(sromrev == 1);
- varbuf_append(&b, vstr_oem,
- cis[i + 1], cis[i + 2],
- cis[i + 3], cis[i + 4],
- cis[i + 5], cis[i + 6],
- cis[i + 7], cis[i + 8]);
- break;
-
- case HNBU_LEDS:
- for (j = 1; j <= 4; j++) {
- if (cis[i + j] != 0xff) {
- varbuf_append(&b,
- vstr_ledbh,
- j - 1,
- cis[i +
- j]);
- }
- }
- break;
-
- case HNBU_CCODE:
- ASSERT(sromrev > 1);
- if ((cis[i + 1] == 0)
- || (cis[i + 2] == 0))
- varbuf_append(&b, vstr_noccode);
- else
- varbuf_append(&b, vstr_ccode,
- cis[i + 1],
- cis[i + 2]);
- varbuf_append(&b, vstr_cctl,
- cis[i + 3]);
- break;
-
- case HNBU_CCKPO:
- ASSERT(sromrev > 2);
- varbuf_append(&b, vstr_cckpo,
- (cis[i + 2] << 8) | cis[i
- +
- 1]);
- break;
-
- case HNBU_OFDMPO:
- ASSERT(sromrev > 2);
- varbuf_append(&b, vstr_ofdmpo,
- (cis[i + 4] << 24) |
- (cis[i + 3] << 16) |
- (cis[i + 2] << 8) |
- cis[i + 1]);
- break;
-
- case HNBU_WPS:
- varbuf_append(&b, vstr_wpsgpio,
- cis[i + 1]);
- if (tlen >= 3)
- varbuf_append(&b, vstr_wpsled,
- cis[i + 2]);
- break;
-
- case HNBU_RSSISMBXA2G:
- ASSERT(sromrev == 3);
- varbuf_append(&b, vstr_rssismf2g,
- cis[i + 1] & 0xf);
- varbuf_append(&b, vstr_rssismc2g,
- (cis[i + 1] >> 4) & 0xf);
- varbuf_append(&b, vstr_rssisav2g,
- cis[i + 2] & 0x7);
- varbuf_append(&b, vstr_bxa2g,
- (cis[i + 2] >> 3) & 0x3);
- break;
-
- case HNBU_RSSISMBXA5G:
- ASSERT(sromrev == 3);
- varbuf_append(&b, vstr_rssismf5g,
- cis[i + 1] & 0xf);
- varbuf_append(&b, vstr_rssismc5g,
- (cis[i + 1] >> 4) & 0xf);
- varbuf_append(&b, vstr_rssisav5g,
- cis[i + 2] & 0x7);
- varbuf_append(&b, vstr_bxa5g,
- (cis[i + 2] >> 3) & 0x3);
- break;
-
- case HNBU_TRI2G:
- ASSERT(sromrev == 3);
- varbuf_append(&b, vstr_tri2g,
- cis[i + 1]);
- break;
-
- case HNBU_TRI5G:
- ASSERT(sromrev == 3);
- varbuf_append(&b, vstr_tri5gl,
- cis[i + 1]);
- varbuf_append(&b, vstr_tri5g,
- cis[i + 2]);
- varbuf_append(&b, vstr_tri5gh,
- cis[i + 3]);
- break;
-
- case HNBU_RXPO2G:
- ASSERT(sromrev == 3);
- varbuf_append(&b, vstr_rxpo2g,
- cis[i + 1]);
- break;
-
- case HNBU_RXPO5G:
- ASSERT(sromrev == 3);
- varbuf_append(&b, vstr_rxpo5g,
- cis[i + 1]);
- break;
-
- case HNBU_MACADDR:
- if (!is_zero_ether_addr(&cis[i + 1]) &&
- !is_multicast_ether_addr(&cis[i + 1])) {
- snprintf(eabuf, sizeof(eabuf),
- "%pM", &cis[i + 1]);
-
- /* set boardnum if HNBU_BOARDNUM not seen yet */
- if (boardnum == -1)
- boardnum =
- (cis[i + 5] << 8) +
- cis[i + 6];
- }
- break;
-
- case HNBU_LEDDC:
- /* CIS leddc only has 16bits, convert it to 32bits */
- w32 = ((cis[i + 2] << 24) | /* oncount */
- (cis[i + 1] << 8)); /* offcount */
- varbuf_append(&b, vstr_leddc, w32);
- break;
-
- case HNBU_CHAINSWITCH:
- varbuf_append(&b, vstr_txchain,
- cis[i + 1]);
- varbuf_append(&b, vstr_rxchain,
- cis[i + 2]);
- varbuf_append(&b, vstr_antswitch,
- (cis[i + 4] << 8) +
- cis[i + 3]);
- break;
-
- case HNBU_REGREV:
- varbuf_append(&b, vstr_regrev,
- cis[i + 1]);
- break;
-
- case HNBU_FEM:{
- u16 fem =
- (cis[i + 2] << 8) + cis[i +
- 1];
- varbuf_append(&b,
- vstr_antswctl2g,
- (fem &
- SROM8_FEM_ANTSWLUT_MASK)
- >>
- SROM8_FEM_ANTSWLUT_SHIFT);
- varbuf_append(&b, vstr_triso2g,
- (fem &
- SROM8_FEM_TR_ISO_MASK)
- >>
- SROM8_FEM_TR_ISO_SHIFT);
- varbuf_append(&b,
- vstr_pdetrange2g,
- (fem &
- SROM8_FEM_PDET_RANGE_MASK)
- >>
- SROM8_FEM_PDET_RANGE_SHIFT);
- varbuf_append(&b,
- vstr_extpagain2g,
- (fem &
- SROM8_FEM_EXTPA_GAIN_MASK)
- >>
- SROM8_FEM_EXTPA_GAIN_SHIFT);
- varbuf_append(&b,
- vstr_tssipos2g,
- (fem &
- SROM8_FEM_TSSIPOS_MASK)
- >>
- SROM8_FEM_TSSIPOS_SHIFT);
- if (tlen < 5)
- break;
-
- fem =
- (cis[i + 4] << 8) + cis[i +
- 3];
- varbuf_append(&b,
- vstr_antswctl5g,
- (fem &
- SROM8_FEM_ANTSWLUT_MASK)
- >>
- SROM8_FEM_ANTSWLUT_SHIFT);
- varbuf_append(&b, vstr_triso5g,
- (fem &
- SROM8_FEM_TR_ISO_MASK)
- >>
- SROM8_FEM_TR_ISO_SHIFT);
- varbuf_append(&b,
- vstr_pdetrange5g,
- (fem &
- SROM8_FEM_PDET_RANGE_MASK)
- >>
- SROM8_FEM_PDET_RANGE_SHIFT);
- varbuf_append(&b,
- vstr_extpagain5g,
- (fem &
- SROM8_FEM_EXTPA_GAIN_MASK)
- >>
- SROM8_FEM_EXTPA_GAIN_SHIFT);
- varbuf_append(&b,
- vstr_tssipos5g,
- (fem &
- SROM8_FEM_TSSIPOS_MASK)
- >>
- SROM8_FEM_TSSIPOS_SHIFT);
- break;
- }
-
- case HNBU_PAPARMS_C0:
- varbuf_append(&b, vstr_maxp2ga0,
- cis[i + 1]);
- varbuf_append(&b, vstr_itt2ga0,
- cis[i + 2]);
- varbuf_append(&b, vstr_pa, 2, 0, 0,
- (cis[i + 4] << 8) +
- cis[i + 3]);
- varbuf_append(&b, vstr_pa, 2, 1, 0,
- (cis[i + 6] << 8) +
- cis[i + 5]);
- varbuf_append(&b, vstr_pa, 2, 2, 0,
- (cis[i + 8] << 8) +
- cis[i + 7]);
- if (tlen < 31)
- break;
-
- varbuf_append(&b, vstr_maxp5ga0,
- cis[i + 9]);
- varbuf_append(&b, vstr_itt5ga0,
- cis[i + 10]);
- varbuf_append(&b, vstr_maxp5gha0,
- cis[i + 11]);
- varbuf_append(&b, vstr_maxp5gla0,
- cis[i + 12]);
- varbuf_append(&b, vstr_pa, 5, 0, 0,
- (cis[i + 14] << 8) +
- cis[i + 13]);
- varbuf_append(&b, vstr_pa, 5, 1, 0,
- (cis[i + 16] << 8) +
- cis[i + 15]);
- varbuf_append(&b, vstr_pa, 5, 2, 0,
- (cis[i + 18] << 8) +
- cis[i + 17]);
- varbuf_append(&b, vstr_pahl, 5, 'l', 0,
- 0,
- (cis[i + 20] << 8) +
- cis[i + 19]);
- varbuf_append(&b, vstr_pahl, 5, 'l', 1,
- 0,
- (cis[i + 22] << 8) +
- cis[i + 21]);
- varbuf_append(&b, vstr_pahl, 5, 'l', 2,
- 0,
- (cis[i + 24] << 8) +
- cis[i + 23]);
- varbuf_append(&b, vstr_pahl, 5, 'h', 0,
- 0,
- (cis[i + 26] << 8) +
- cis[i + 25]);
- varbuf_append(&b, vstr_pahl, 5, 'h', 1,
- 0,
- (cis[i + 28] << 8) +
- cis[i + 27]);
- varbuf_append(&b, vstr_pahl, 5, 'h', 2,
- 0,
- (cis[i + 30] << 8) +
- cis[i + 29]);
- break;
-
- case HNBU_PAPARMS_C1:
- varbuf_append(&b, vstr_maxp2ga1,
- cis[i + 1]);
- varbuf_append(&b, vstr_itt2ga1,
- cis[i + 2]);
- varbuf_append(&b, vstr_pa, 2, 0, 1,
- (cis[i + 4] << 8) +
- cis[i + 3]);
- varbuf_append(&b, vstr_pa, 2, 1, 1,
- (cis[i + 6] << 8) +
- cis[i + 5]);
- varbuf_append(&b, vstr_pa, 2, 2, 1,
- (cis[i + 8] << 8) +
- cis[i + 7]);
- if (tlen < 31)
- break;
-
- varbuf_append(&b, vstr_maxp5ga1,
- cis[i + 9]);
- varbuf_append(&b, vstr_itt5ga1,
- cis[i + 10]);
- varbuf_append(&b, vstr_maxp5gha1,
- cis[i + 11]);
- varbuf_append(&b, vstr_maxp5gla1,
- cis[i + 12]);
- varbuf_append(&b, vstr_pa, 5, 0, 1,
- (cis[i + 14] << 8) +
- cis[i + 13]);
- varbuf_append(&b, vstr_pa, 5, 1, 1,
- (cis[i + 16] << 8) +
- cis[i + 15]);
- varbuf_append(&b, vstr_pa, 5, 2, 1,
- (cis[i + 18] << 8) +
- cis[i + 17]);
- varbuf_append(&b, vstr_pahl, 5, 'l', 0,
- 1,
- (cis[i + 20] << 8) +
- cis[i + 19]);
- varbuf_append(&b, vstr_pahl, 5, 'l', 1,
- 1,
- (cis[i + 22] << 8) +
- cis[i + 21]);
- varbuf_append(&b, vstr_pahl, 5, 'l', 2,
- 1,
- (cis[i + 24] << 8) +
- cis[i + 23]);
- varbuf_append(&b, vstr_pahl, 5, 'h', 0,
- 1,
- (cis[i + 26] << 8) +
- cis[i + 25]);
- varbuf_append(&b, vstr_pahl, 5, 'h', 1,
- 1,
- (cis[i + 28] << 8) +
- cis[i + 27]);
- varbuf_append(&b, vstr_pahl, 5, 'h', 2,
- 1,
- (cis[i + 30] << 8) +
- cis[i + 29]);
- break;
-
- case HNBU_PO_CCKOFDM:
- varbuf_append(&b, vstr_cck2gpo,
- (cis[i + 2] << 8) +
- cis[i + 1]);
- varbuf_append(&b, vstr_ofdm2gpo,
- (cis[i + 6] << 24) +
- (cis[i + 5] << 16) +
- (cis[i + 4] << 8) +
- cis[i + 3]);
- if (tlen < 19)
- break;
-
- varbuf_append(&b, vstr_ofdm5gpo,
- (cis[i + 10] << 24) +
- (cis[i + 9] << 16) +
- (cis[i + 8] << 8) +
- cis[i + 7]);
- varbuf_append(&b, vstr_ofdm5glpo,
- (cis[i + 14] << 24) +
- (cis[i + 13] << 16) +
- (cis[i + 12] << 8) +
- cis[i + 11]);
- varbuf_append(&b, vstr_ofdm5ghpo,
- (cis[i + 18] << 24) +
- (cis[i + 17] << 16) +
- (cis[i + 16] << 8) +
- cis[i + 15]);
- break;
-
- case HNBU_PO_MCS2G:
- for (j = 0; j <= (tlen / 2); j++) {
- varbuf_append(&b, vstr_mcspo, 2,
- j,
- (cis
- [i + 2 +
- 2 * j] << 8) +
- cis[i + 1 +
- 2 * j]);
- }
- break;
-
- case HNBU_PO_MCS5GM:
- for (j = 0; j <= (tlen / 2); j++) {
- varbuf_append(&b, vstr_mcspo, 5,
- j,
- (cis
- [i + 2 +
- 2 * j] << 8) +
- cis[i + 1 +
- 2 * j]);
- }
- break;
-
- case HNBU_PO_MCS5GLH:
- for (j = 0; j <= (tlen / 4); j++) {
- varbuf_append(&b, vstr_mcspohl,
- 5, 'l', j,
- (cis
- [i + 2 +
- 2 * j] << 8) +
- cis[i + 1 +
- 2 * j]);
- }
-
- for (j = 0; j <= (tlen / 4); j++) {
- varbuf_append(&b, vstr_mcspohl,
- 5, 'h', j,
- (cis
- [i +
- ((tlen / 2) +
- 2) +
- 2 * j] << 8) +
- cis[i +
- ((tlen / 2) +
- 1) + 2 * j]);
- }
-
- break;
-
- case HNBU_PO_CDD:
- varbuf_append(&b, vstr_cddpo,
- (cis[i + 2] << 8) +
- cis[i + 1]);
- break;
-
- case HNBU_PO_STBC:
- varbuf_append(&b, vstr_stbcpo,
- (cis[i + 2] << 8) +
- cis[i + 1]);
- break;
-
- case HNBU_PO_40M:
- varbuf_append(&b, vstr_bw40po,
- (cis[i + 2] << 8) +
- cis[i + 1]);
- break;
-
- case HNBU_PO_40MDUP:
- varbuf_append(&b, vstr_bwduppo,
- (cis[i + 2] << 8) +
- cis[i + 1]);
- break;
-
- case HNBU_OFDMPO5G:
- varbuf_append(&b, vstr_ofdm5gpo,
- (cis[i + 4] << 24) +
- (cis[i + 3] << 16) +
- (cis[i + 2] << 8) +
- cis[i + 1]);
- varbuf_append(&b, vstr_ofdm5glpo,
- (cis[i + 8] << 24) +
- (cis[i + 7] << 16) +
- (cis[i + 6] << 8) +
- cis[i + 5]);
- varbuf_append(&b, vstr_ofdm5ghpo,
- (cis[i + 12] << 24) +
- (cis[i + 11] << 16) +
- (cis[i + 10] << 8) +
- cis[i + 9]);
- break;
-
- case HNBU_CUSTOM1:
- varbuf_append(&b, vstr_custom, 1,
- ((cis[i + 4] << 24) +
- (cis[i + 3] << 16) +
- (cis[i + 2] << 8) +
- cis[i + 1]));
- break;
-
-#if defined(BCMSDIO)
- case HNBU_SROM3SWRGN:
- if (tlen >= 73) {
- u16 srom[35];
- u8 srev = cis[i + 1 + 70];
- ASSERT(srev == 3);
- /* make tuple value 16-bit aligned and parse it */
- memcpy(srom, &cis[i + 1],
- sizeof(srom));
- _initvars_srom_pci(srev, srom,
- SROM3_SWRGN_OFF,
- &b);
- /* 2.4G antenna gain is included in SROM */
- ag_init = true;
- /* Ethernet MAC address is included in SROM */
- eabuf[0] = 0;
- boardnum = -1;
- }
- /* create extra variables */
- if (tlen >= 75)
- varbuf_append(&b, vstr_vendid,
- (cis[i + 1 + 73]
- << 8) + cis[i +
- 1 +
- 72]);
- if (tlen >= 77)
- varbuf_append(&b, vstr_devid,
- (cis[i + 1 + 75]
- << 8) + cis[i +
- 1 +
- 74]);
- if (tlen >= 79)
- varbuf_append(&b, vstr_xtalfreq,
- (cis[i + 1 + 77]
- << 8) + cis[i +
- 1 +
- 76]);
- break;
-#endif /* defined(BCMSDIO) */
-
- case HNBU_CCKFILTTYPE:
- varbuf_append(&b, vstr_cckdigfilttype,
- (cis[i + 1]));
- break;
- }
-
- break;
- }
- i += tlen;
- } while (tup != CISTPL_END);
- }
-
- if (boardnum != -1) {
- varbuf_append(&b, vstr_boardnum, boardnum);
- }
-
- if (eabuf[0]) {
- varbuf_append(&b, vstr_macaddr, eabuf);
- }
-
- /* if there is no antenna gain field, set default */
- if (getvar(NULL, "ag0") == NULL && ag_init == false) {
- varbuf_append(&b, vstr_ag, 0, 0xff);
- }
-
- /* final nullbyte terminator */
- ASSERT(b.size >= 1);
- *b.buf++ = '\0';
-
- ASSERT(b.buf - base <= MAXSZ_NVRAM_VARS);
- err = initvars_table(base, b.buf, vars, count);
-
- kfree(base);
- return err;
-}
-
-/* In chips with chipcommon rev 32 and later, the srom is in chipcommon,
- * not in the bus cores.
- */
-static u16
-srom_cc_cmd(si_t *sih, void *ccregs, u32 cmd,
- uint wordoff, u16 data)
-{
- chipcregs_t *cc = (chipcregs_t *) ccregs;
- uint wait_cnt = 1000;
-
- if ((cmd == SRC_OP_READ) || (cmd == SRC_OP_WRITE)) {
- W_REG(&cc->sromaddress, wordoff * 2);
- if (cmd == SRC_OP_WRITE)
- W_REG(&cc->sromdata, data);
- }
-
- W_REG(&cc->sromcontrol, SRC_START | cmd);
-
- while (wait_cnt--) {
- if ((R_REG(&cc->sromcontrol) & SRC_BUSY) == 0)
- break;
- }
-
- if (!wait_cnt) {
- BS_ERROR(("%s: Command 0x%x timed out\n", __func__, cmd));
- return 0xffff;
- }
- if (cmd == SRC_OP_READ)
- return (u16) R_REG(&cc->sromdata);
- else
- return 0xffff;
-}
-
-static inline void ltoh16_buf(u16 *buf, unsigned int size)
-{
- for (size /= 2; size; size--)
- *(buf + size) = le16_to_cpu(*(buf + size));
-}
-
-static inline void htol16_buf(u16 *buf, unsigned int size)
-{
- for (size /= 2; size; size--)
- *(buf + size) = cpu_to_le16(*(buf + size));
-}
-
-/*
- * Read in and validate sprom.
- * Return 0 on success, nonzero on error.
- */
-static int
-sprom_read_pci(si_t *sih, u16 *sprom, uint wordoff,
- u16 *buf, uint nwords, bool check_crc)
-{
- int err = 0;
- uint i;
- void *ccregs = NULL;
-
- /* read the sprom */
- for (i = 0; i < nwords; i++) {
-
- if (sih->ccrev > 31 && ISSIM_ENAB(sih)) {
- /* use indirect since direct is too slow on QT */
- if ((sih->cccaps & CC_CAP_SROM) == 0)
- return 1;
-
- ccregs = (void *)((u8 *) sprom - CC_SROM_OTP);
- buf[i] =
- srom_cc_cmd(sih, ccregs, SRC_OP_READ,
- wordoff + i, 0);
-
- } else {
- if (ISSIM_ENAB(sih))
- buf[i] = R_REG(&sprom[wordoff + i]);
-
- buf[i] = R_REG(&sprom[wordoff + i]);
- }
-
- }
-
- /* bypass crc checking for simulation to allow srom hack */
- if (ISSIM_ENAB(sih))
- return err;
-
- if (check_crc) {
-
- if (buf[0] == 0xffff) {
- /* The hardware thinks that an srom that starts with 0xffff
- * is blank, regardless of the rest of the content, so declare
- * it bad.
- */
- BS_ERROR(("%s: buf[0] = 0x%x, returning bad-crc\n",
- __func__, buf[0]));
- return 1;
- }
-
- /* fixup the endianness so crc8 will pass */
- htol16_buf(buf, nwords * 2);
- if (hndcrc8((u8 *) buf, nwords * 2, CRC8_INIT_VALUE) !=
- CRC8_GOOD_VALUE) {
- /* DBG only pci always read srom4 first, then srom8/9 */
- /* BS_ERROR(("%s: bad crc\n", __func__)); */
- err = 1;
- }
- /* now correct the endianness of the byte array */
- ltoh16_buf(buf, nwords * 2);
- }
- return err;
-}
-
-#if defined(BCMNVRAMR)
-static int otp_read_pci(si_t *sih, u16 *buf, uint bufsz)
-{
- u8 *otp;
- uint sz = OTP_SZ_MAX / 2; /* size in words */
- int err = 0;
-
- ASSERT(bufsz <= OTP_SZ_MAX);
-
- otp = kzalloc(OTP_SZ_MAX, GFP_ATOMIC);
- if (otp == NULL) {
- return BCME_ERROR;
- }
-
- err = otp_read_region(sih, OTP_HW_RGN, (u16 *) otp, &sz);
-
- memcpy(buf, otp, bufsz);
-
- kfree(otp);
-
- /* Check CRC */
- if (buf[0] == 0xffff) {
- /* The hardware thinks that an srom that starts with 0xffff
- * is blank, regardless of the rest of the content, so declare
- * it bad.
- */
- BS_ERROR(("%s: buf[0] = 0x%x, returning bad-crc\n", __func__,
- buf[0]));
- return 1;
- }
-
- /* fixup the endianness so crc8 will pass */
- htol16_buf(buf, bufsz);
- if (hndcrc8((u8 *) buf, SROM4_WORDS * 2, CRC8_INIT_VALUE) !=
- CRC8_GOOD_VALUE) {
- BS_ERROR(("%s: bad crc\n", __func__));
- err = 1;
- }
- /* now correct the endianness of the byte array */
- ltoh16_buf(buf, bufsz);
-
- return err;
-}
-#endif /* defined(BCMNVRAMR) */
-/*
-* Create variable table from memory.
-* Return 0 on success, nonzero on error.
-*/
-static int initvars_table(char *start, char *end,
- char **vars, uint *count)
-{
- int c = (int)(end - start);
-
- /* do it only when there is more than just the null string */
- if (c > 1) {
- char *vp = kmalloc(c, GFP_ATOMIC);
- ASSERT(vp != NULL);
- if (!vp)
- return BCME_NOMEM;
- memcpy(vp, start, c);
- *vars = vp;
- *count = c;
- } else {
- *vars = NULL;
- *count = 0;
- }
-
- return 0;
-}
-
-/*
- * Find variables with <devpath> from flash. 'base' points to the beginning
- * of the table upon enter and to the end of the table upon exit when success.
- * Return 0 on success, nonzero on error.
- */
-static int initvars_flash(si_t *sih, char **base, uint len)
-{
- char *vp = *base;
- char *flash;
- int err;
- char *s;
- uint l, dl, copy_len;
- char devpath[SI_DEVPATH_BUFSZ];
-
- /* allocate memory and read in flash */
- flash = kmalloc(NVRAM_SPACE, GFP_ATOMIC);
- if (!flash)
- return BCME_NOMEM;
- err = nvram_getall(flash, NVRAM_SPACE);
- if (err)
- goto exit;
-
- si_devpath(sih, devpath, sizeof(devpath));
-
- /* grab vars with the <devpath> prefix in name */
- dl = strlen(devpath);
- for (s = flash; s && *s; s += l + 1) {
- l = strlen(s);
-
- /* skip non-matching variable */
- if (strncmp(s, devpath, dl))
- continue;
-
- /* is there enough room to copy? */
- copy_len = l - dl + 1;
- if (len < copy_len) {
- err = BCME_BUFTOOSHORT;
- goto exit;
- }
-
- /* no prefix, just the name=value */
- strncpy(vp, &s[dl], copy_len);
- vp += copy_len;
- len -= copy_len;
- }
-
- /* add null string as terminator */
- if (len < 1) {
- err = BCME_BUFTOOSHORT;
- goto exit;
- }
- *vp++ = '\0';
-
- *base = vp;
-
- exit: kfree(flash);
- return err;
-}
-
-/*
- * Initialize nonvolatile variable table from flash.
- * Return 0 on success, nonzero on error.
- */
-static int initvars_flash_si(si_t *sih, char **vars, uint *count)
-{
- char *vp, *base;
- int err;
-
- ASSERT(vars != NULL);
- ASSERT(count != NULL);
-
- base = vp = kmalloc(MAXSZ_NVRAM_VARS, GFP_ATOMIC);
- ASSERT(vp != NULL);
- if (!vp)
- return BCME_NOMEM;
-
- err = initvars_flash(sih, &vp, MAXSZ_NVRAM_VARS);
- if (err == 0)
- err = initvars_table(base, vp, vars, count);
-
- kfree(base);
-
- return err;
-}
-
-/* Parse SROM and create name=value pairs. 'srom' points to
- * the SROM word array. 'off' specifies the offset of the
- * first word 'srom' points to, which should be either 0 or
- * SROM3_SWRG_OFF (full SROM or software region).
- */
-
-static uint mask_shift(u16 mask)
-{
- uint i;
- for (i = 0; i < (sizeof(mask) << 3); i++) {
- if (mask & (1 << i))
- return i;
- }
- ASSERT(mask);
- return 0;
-}
-
-static uint mask_width(u16 mask)
-{
- int i;
- for (i = (sizeof(mask) << 3) - 1; i >= 0; i--) {
- if (mask & (1 << i))
- return (uint) (i - mask_shift(mask) + 1);
- }
- ASSERT(mask);
- return 0;
-}
-
-#if defined(BCMDBG)
-static bool mask_valid(u16 mask)
-{
- uint shift = mask_shift(mask);
- uint width = mask_width(mask);
- return mask == ((~0 << shift) & ~(~0 << (shift + width)));
-}
-#endif /* BCMDBG */
-
-static void _initvars_srom_pci(u8 sromrev, u16 *srom, uint off, varbuf_t *b)
-{
- u16 w;
- u32 val;
- const sromvar_t *srv;
- uint width;
- uint flags;
- u32 sr = (1 << sromrev);
-
- varbuf_append(b, "sromrev=%d", sromrev);
-
- for (srv = pci_sromvars; srv->name != NULL; srv++) {
- const char *name;
-
- if ((srv->revmask & sr) == 0)
- continue;
-
- if (srv->off < off)
- continue;
-
- flags = srv->flags;
- name = srv->name;
-
- /* This entry is for mfgc only. Don't generate param for it, */
- if (flags & SRFL_NOVAR)
- continue;
-
- if (flags & SRFL_ETHADDR) {
- u8 ea[ETH_ALEN];
-
- ea[0] = (srom[srv->off - off] >> 8) & 0xff;
- ea[1] = srom[srv->off - off] & 0xff;
- ea[2] = (srom[srv->off + 1 - off] >> 8) & 0xff;
- ea[3] = srom[srv->off + 1 - off] & 0xff;
- ea[4] = (srom[srv->off + 2 - off] >> 8) & 0xff;
- ea[5] = srom[srv->off + 2 - off] & 0xff;
-
- varbuf_append(b, "%s=%pM", name, ea);
- } else {
- ASSERT(mask_valid(srv->mask));
- ASSERT(mask_width(srv->mask));
-
- w = srom[srv->off - off];
- val = (w & srv->mask) >> mask_shift(srv->mask);
- width = mask_width(srv->mask);
-
- while (srv->flags & SRFL_MORE) {
- srv++;
- ASSERT(srv->name != NULL);
-
- if (srv->off == 0 || srv->off < off)
- continue;
-
- ASSERT(mask_valid(srv->mask));
- ASSERT(mask_width(srv->mask));
-
- w = srom[srv->off - off];
- val +=
- ((w & srv->mask) >> mask_shift(srv->
- mask)) <<
- width;
- width += mask_width(srv->mask);
- }
-
- if ((flags & SRFL_NOFFS)
- && ((int)val == (1 << width) - 1))
- continue;
-
- if (flags & SRFL_CCODE) {
- if (val == 0)
- varbuf_append(b, "ccode=");
- else
- varbuf_append(b, "ccode=%c%c",
- (val >> 8), (val & 0xff));
- }
- /* LED Powersave duty cycle has to be scaled:
- *(oncount >> 24) (offcount >> 8)
- */
- else if (flags & SRFL_LEDDC) {
- u32 w32 = (((val >> 8) & 0xff) << 24) | /* oncount */
- (((val & 0xff)) << 8); /* offcount */
- varbuf_append(b, "leddc=%d", w32);
- } else if (flags & SRFL_PRHEX)
- varbuf_append(b, "%s=0x%x", name, val);
- else if ((flags & SRFL_PRSIGN)
- && (val & (1 << (width - 1))))
- varbuf_append(b, "%s=%d", name,
- (int)(val | (~0 << width)));
- else
- varbuf_append(b, "%s=%u", name, val);
- }
- }
-
- if (sromrev >= 4) {
- /* Do per-path variables */
- uint p, pb, psz;
-
- if (sromrev >= 8) {
- pb = SROM8_PATH0;
- psz = SROM8_PATH1 - SROM8_PATH0;
- } else {
- pb = SROM4_PATH0;
- psz = SROM4_PATH1 - SROM4_PATH0;
- }
-
- for (p = 0; p < MAX_PATH_SROM; p++) {
- for (srv = perpath_pci_sromvars; srv->name != NULL;
- srv++) {
- if ((srv->revmask & sr) == 0)
- continue;
-
- if (pb + srv->off < off)
- continue;
-
- /* This entry is for mfgc only. Don't generate param for it, */
- if (srv->flags & SRFL_NOVAR)
- continue;
-
- w = srom[pb + srv->off - off];
-
- ASSERT(mask_valid(srv->mask));
- val = (w & srv->mask) >> mask_shift(srv->mask);
- width = mask_width(srv->mask);
-
- /* Cheating: no per-path var is more than 1 word */
-
- if ((srv->flags & SRFL_NOFFS)
- && ((int)val == (1 << width) - 1))
- continue;
-
- if (srv->flags & SRFL_PRHEX)
- varbuf_append(b, "%s%d=0x%x", srv->name,
- p, val);
- else
- varbuf_append(b, "%s%d=%d", srv->name,
- p, val);
- }
- pb += psz;
- }
- }
-}
-
-/*
- * Initialize nonvolatile variable table from sprom.
- * Return 0 on success, nonzero on error.
- */
-static int initvars_srom_pci(si_t *sih, void *curmap, char **vars, uint *count)
-{
- u16 *srom, *sromwindow;
- u8 sromrev = 0;
- u32 sr;
- varbuf_t b;
- char *vp, *base = NULL;
- bool flash = false;
- int err = 0;
-
- /*
- * Apply CRC over SROM content regardless SROM is present or not,
- * and use variable <devpath>sromrev's existence in flash to decide
- * if we should return an error when CRC fails or read SROM variables
- * from flash.
- */
- srom = kmalloc(SROM_MAX, GFP_ATOMIC);
- ASSERT(srom != NULL);
- if (!srom)
- return -2;
-
- sromwindow = (u16 *) SROM_OFFSET(sih);
- if (si_is_sprom_available(sih)) {
- err =
- sprom_read_pci(sih, sromwindow, 0, srom, SROM_WORDS,
- true);
-
- if ((srom[SROM4_SIGN] == SROM4_SIGNATURE) ||
- (((sih->buscoretype == PCIE_CORE_ID)
- && (sih->buscorerev >= 6))
- || ((sih->buscoretype == PCI_CORE_ID)
- && (sih->buscorerev >= 0xe)))) {
- /* sromrev >= 4, read more */
- err =
- sprom_read_pci(sih, sromwindow, 0, srom,
- SROM4_WORDS, true);
- sromrev = srom[SROM4_CRCREV] & 0xff;
- if (err)
- BS_ERROR(("%s: srom %d, bad crc\n", __func__,
- sromrev));
-
- } else if (err == 0) {
- /* srom is good and is rev < 4 */
- /* top word of sprom contains version and crc8 */
- sromrev = srom[SROM_CRCREV] & 0xff;
- /* bcm4401 sroms misprogrammed */
- if (sromrev == 0x10)
- sromrev = 1;
- }
- }
-#if defined(BCMNVRAMR)
- /* Use OTP if SPROM not available */
- else {
- err = otp_read_pci(sih, srom, SROM_MAX);
- if (err == 0)
- /* OTP only contain SROM rev8/rev9 for now */
- sromrev = srom[SROM4_CRCREV] & 0xff;
- else
- err = 1;
- }
-#else
- else
- err = 1;
-#endif
-
- /*
- * We want internal/wltest driver to come up with default
- * sromvars so we can program a blank SPROM/OTP.
- */
- if (err) {
- char *value;
- u32 val;
- val = 0;
-
- BS_ERROR(("Neither SPROM nor OTP has valid image\n"));
- value = si_getdevpathvar(sih, "sromrev");
- if (value) {
- sromrev = (u8) simple_strtoul(value, NULL, 0);
- flash = true;
- goto varscont;
- }
-
- BS_ERROR(("%s, SROM CRC Error\n", __func__));
-
- value = si_getnvramflvar(sih, "sromrev");
- if (value) {
- err = 0;
- goto errout;
- }
-
- {
- err = -1;
- goto errout;
- }
- }
-
- varscont:
- /* Bitmask for the sromrev */
- sr = 1 << sromrev;
-
- /* srom version check: Current valid versions: 1, 2, 3, 4, 5, 8, 9 */
- if ((sr & 0x33e) == 0) {
- err = -2;
- goto errout;
- }
-
- ASSERT(vars != NULL);
- ASSERT(count != NULL);
-
- base = vp = kmalloc(MAXSZ_NVRAM_VARS, GFP_ATOMIC);
- ASSERT(vp != NULL);
- if (!vp) {
- err = -2;
- goto errout;
- }
-
- /* read variables from flash */
- if (flash) {
- err = initvars_flash(sih, &vp, MAXSZ_NVRAM_VARS);
- if (err)
- goto errout;
- goto varsdone;
- }
-
- varbuf_init(&b, base, MAXSZ_NVRAM_VARS);
-
- /* parse SROM into name=value pairs. */
- _initvars_srom_pci(sromrev, srom, 0, &b);
-
- /* final nullbyte terminator */
- ASSERT(b.size >= 1);
- vp = b.buf;
- *vp++ = '\0';
-
- ASSERT((vp - base) <= MAXSZ_NVRAM_VARS);
-
- varsdone:
- err = initvars_table(base, vp, vars, count);
-
- errout:
- if (base)
- kfree(base);
-
- kfree(srom);
- return err;
-}
-
-#ifdef BCMSDIO
-/*
- * Read the SDIO cis and call parsecis to initialize the vars.
- * Return 0 on success, nonzero on error.
- */
-static int initvars_cis_sdio(char **vars, uint *count)
-{
- u8 *cis[SBSDIO_NUM_FUNCTION + 1];
- uint fn, numfn;
- int rc = 0;
-
- numfn = bcmsdh_query_iofnum(NULL);
- ASSERT(numfn <= SDIOD_MAX_IOFUNCS);
-
- for (fn = 0; fn <= numfn; fn++) {
- cis[fn] = kzalloc(SBSDIO_CIS_SIZE_LIMIT, GFP_ATOMIC);
- if (cis[fn] == NULL) {
- rc = -1;
- break;
- }
-
- if (bcmsdh_cis_read(NULL, fn, cis[fn], SBSDIO_CIS_SIZE_LIMIT) !=
- 0) {
- kfree(cis[fn]);
- rc = -2;
- break;
- }
- }
-
- if (!rc)
- rc = srom_parsecis(cis, fn, vars, count);
-
- while (fn-- > 0)
- kfree(cis[fn]);
-
- return rc;
-}
-
-/* set SDIO sprom command register */
-static int sprom_cmd_sdio(u8 cmd)
-{
- u8 status = 0;
- uint wait_cnt = 1000;
-
- /* write sprom command register */
- bcmsdh_cfg_write(NULL, SDIO_FUNC_1, SBSDIO_SPROM_CS, cmd, NULL);
-
- /* wait status */
- while (wait_cnt--) {
- status =
- bcmsdh_cfg_read(NULL, SDIO_FUNC_1, SBSDIO_SPROM_CS, NULL);
- if (status & SBSDIO_SPROM_DONE)
- return 0;
- }
-
- return 1;
-}
-
-/* read a word from the SDIO srom */
-static int sprom_read_sdio(u16 addr, u16 *data)
-{
- u8 addr_l, addr_h, data_l, data_h;
-
- addr_l = (u8) ((addr * 2) & 0xff);
- addr_h = (u8) (((addr * 2) >> 8) & 0xff);
-
- /* set address */
- bcmsdh_cfg_write(NULL, SDIO_FUNC_1, SBSDIO_SPROM_ADDR_HIGH, addr_h,
- NULL);
- bcmsdh_cfg_write(NULL, SDIO_FUNC_1, SBSDIO_SPROM_ADDR_LOW, addr_l,
- NULL);
-
- /* do read */
- if (sprom_cmd_sdio(SBSDIO_SPROM_READ))
- return 1;
-
- /* read data */
- data_h =
- bcmsdh_cfg_read(NULL, SDIO_FUNC_1, SBSDIO_SPROM_DATA_HIGH, NULL);
- data_l =
- bcmsdh_cfg_read(NULL, SDIO_FUNC_1, SBSDIO_SPROM_DATA_LOW, NULL);
-
- *data = (data_h << 8) | data_l;
- return 0;
-}
-#endif /* BCMSDIO */
-
-static int initvars_srom_si(si_t *sih, void *curmap, char **vars, uint *varsz)
-{
- /* Search flash nvram section for srom variables */
- return initvars_flash_si(sih, vars, varsz);
-}
diff --git a/drivers/staging/brcm80211/util/bcmsrom_tbl.h b/drivers/staging/brcm80211/util/bcmsrom_tbl.h
deleted file mode 100644
index 22ae7c1..0000000
--- a/drivers/staging/brcm80211/util/bcmsrom_tbl.h
+++ /dev/null
@@ -1,583 +0,0 @@
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#ifndef _bcmsrom_tbl_h_
-#define _bcmsrom_tbl_h_
-
-#include "sbpcmcia.h"
-#include "wlioctl.h"
-
-typedef struct {
- const char *name;
- u32 revmask;
- u32 flags;
- u16 off;
- u16 mask;
-} sromvar_t;
-
-#define SRFL_MORE 1 /* value continues as described by the next entry */
-#define SRFL_NOFFS 2 /* value bits can't be all one's */
-#define SRFL_PRHEX 4 /* value is in hexdecimal format */
-#define SRFL_PRSIGN 8 /* value is in signed decimal format */
-#define SRFL_CCODE 0x10 /* value is in country code format */
-#define SRFL_ETHADDR 0x20 /* value is an Ethernet address */
-#define SRFL_LEDDC 0x40 /* value is an LED duty cycle */
-#define SRFL_NOVAR 0x80 /* do not generate a nvram param, entry is for mfgc */
-
-/* Assumptions:
- * - Ethernet address spans across 3 consective words
- *
- * Table rules:
- * - Add multiple entries next to each other if a value spans across multiple words
- * (even multiple fields in the same word) with each entry except the last having
- * it's SRFL_MORE bit set.
- * - Ethernet address entry does not follow above rule and must not have SRFL_MORE
- * bit set. Its SRFL_ETHADDR bit implies it takes multiple words.
- * - The last entry's name field must be NULL to indicate the end of the table. Other
- * entries must have non-NULL name.
- */
-
-static const sromvar_t pci_sromvars[] = {
- {"devid", 0xffffff00, SRFL_PRHEX | SRFL_NOVAR, PCI_F0DEVID, 0xffff},
- {"boardrev", 0x0000000e, SRFL_PRHEX, SROM_AABREV, SROM_BR_MASK},
- {"boardrev", 0x000000f0, SRFL_PRHEX, SROM4_BREV, 0xffff},
- {"boardrev", 0xffffff00, SRFL_PRHEX, SROM8_BREV, 0xffff},
- {"boardflags", 0x00000002, SRFL_PRHEX, SROM_BFL, 0xffff},
- {"boardflags", 0x00000004, SRFL_PRHEX | SRFL_MORE, SROM_BFL, 0xffff},
- {"", 0, 0, SROM_BFL2, 0xffff},
- {"boardflags", 0x00000008, SRFL_PRHEX | SRFL_MORE, SROM_BFL, 0xffff},
- {"", 0, 0, SROM3_BFL2, 0xffff},
- {"boardflags", 0x00000010, SRFL_PRHEX | SRFL_MORE, SROM4_BFL0, 0xffff},
- {"", 0, 0, SROM4_BFL1, 0xffff},
- {"boardflags", 0x000000e0, SRFL_PRHEX | SRFL_MORE, SROM5_BFL0, 0xffff},
- {"", 0, 0, SROM5_BFL1, 0xffff},
- {"boardflags", 0xffffff00, SRFL_PRHEX | SRFL_MORE, SROM8_BFL0, 0xffff},
- {"", 0, 0, SROM8_BFL1, 0xffff},
- {"boardflags2", 0x00000010, SRFL_PRHEX | SRFL_MORE, SROM4_BFL2, 0xffff},
- {"", 0, 0, SROM4_BFL3, 0xffff},
- {"boardflags2", 0x000000e0, SRFL_PRHEX | SRFL_MORE, SROM5_BFL2, 0xffff},
- {"", 0, 0, SROM5_BFL3, 0xffff},
- {"boardflags2", 0xffffff00, SRFL_PRHEX | SRFL_MORE, SROM8_BFL2, 0xffff},
- {"", 0, 0, SROM8_BFL3, 0xffff},
- {"boardtype", 0xfffffffc, SRFL_PRHEX, SROM_SSID, 0xffff},
- {"boardnum", 0x00000006, 0, SROM_MACLO_IL0, 0xffff},
- {"boardnum", 0x00000008, 0, SROM3_MACLO, 0xffff},
- {"boardnum", 0x00000010, 0, SROM4_MACLO, 0xffff},
- {"boardnum", 0x000000e0, 0, SROM5_MACLO, 0xffff},
- {"boardnum", 0xffffff00, 0, SROM8_MACLO, 0xffff},
- {"cc", 0x00000002, 0, SROM_AABREV, SROM_CC_MASK},
- {"regrev", 0x00000008, 0, SROM_OPO, 0xff00},
- {"regrev", 0x00000010, 0, SROM4_REGREV, 0x00ff},
- {"regrev", 0x000000e0, 0, SROM5_REGREV, 0x00ff},
- {"regrev", 0xffffff00, 0, SROM8_REGREV, 0x00ff},
- {"ledbh0", 0x0000000e, SRFL_NOFFS, SROM_LEDBH10, 0x00ff},
- {"ledbh1", 0x0000000e, SRFL_NOFFS, SROM_LEDBH10, 0xff00},
- {"ledbh2", 0x0000000e, SRFL_NOFFS, SROM_LEDBH32, 0x00ff},
- {"ledbh3", 0x0000000e, SRFL_NOFFS, SROM_LEDBH32, 0xff00},
- {"ledbh0", 0x00000010, SRFL_NOFFS, SROM4_LEDBH10, 0x00ff},
- {"ledbh1", 0x00000010, SRFL_NOFFS, SROM4_LEDBH10, 0xff00},
- {"ledbh2", 0x00000010, SRFL_NOFFS, SROM4_LEDBH32, 0x00ff},
- {"ledbh3", 0x00000010, SRFL_NOFFS, SROM4_LEDBH32, 0xff00},
- {"ledbh0", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH10, 0x00ff},
- {"ledbh1", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH10, 0xff00},
- {"ledbh2", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH32, 0x00ff},
- {"ledbh3", 0x000000e0, SRFL_NOFFS, SROM5_LEDBH32, 0xff00},
- {"ledbh0", 0xffffff00, SRFL_NOFFS, SROM8_LEDBH10, 0x00ff},
- {"ledbh1", 0xffffff00, SRFL_NOFFS, SROM8_LEDBH10, 0xff00},
- {"ledbh2", 0xffffff00, SRFL_NOFFS, SROM8_LEDBH32, 0x00ff},
- {"ledbh3", 0xffffff00, SRFL_NOFFS, SROM8_LEDBH32, 0xff00},
- {"pa0b0", 0x0000000e, SRFL_PRHEX, SROM_WL0PAB0, 0xffff},
- {"pa0b1", 0x0000000e, SRFL_PRHEX, SROM_WL0PAB1, 0xffff},
- {"pa0b2", 0x0000000e, SRFL_PRHEX, SROM_WL0PAB2, 0xffff},
- {"pa0itssit", 0x0000000e, 0, SROM_ITT, 0x00ff},
- {"pa0maxpwr", 0x0000000e, 0, SROM_WL10MAXP, 0x00ff},
- {"pa0b0", 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB0, 0xffff},
- {"pa0b1", 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB1, 0xffff},
- {"pa0b2", 0xffffff00, SRFL_PRHEX, SROM8_W0_PAB2, 0xffff},
- {"pa0itssit", 0xffffff00, 0, SROM8_W0_ITTMAXP, 0xff00},
- {"pa0maxpwr", 0xffffff00, 0, SROM8_W0_ITTMAXP, 0x00ff},
- {"opo", 0x0000000c, 0, SROM_OPO, 0x00ff},
- {"opo", 0xffffff00, 0, SROM8_2G_OFDMPO, 0x00ff},
- {"aa2g", 0x0000000e, 0, SROM_AABREV, SROM_AA0_MASK},
- {"aa2g", 0x000000f0, 0, SROM4_AA, 0x00ff},
- {"aa2g", 0xffffff00, 0, SROM8_AA, 0x00ff},
- {"aa5g", 0x0000000e, 0, SROM_AABREV, SROM_AA1_MASK},
- {"aa5g", 0x000000f0, 0, SROM4_AA, 0xff00},
- {"aa5g", 0xffffff00, 0, SROM8_AA, 0xff00},
- {"ag0", 0x0000000e, 0, SROM_AG10, 0x00ff},
- {"ag1", 0x0000000e, 0, SROM_AG10, 0xff00},
- {"ag0", 0x000000f0, 0, SROM4_AG10, 0x00ff},
- {"ag1", 0x000000f0, 0, SROM4_AG10, 0xff00},
- {"ag2", 0x000000f0, 0, SROM4_AG32, 0x00ff},
- {"ag3", 0x000000f0, 0, SROM4_AG32, 0xff00},
- {"ag0", 0xffffff00, 0, SROM8_AG10, 0x00ff},
- {"ag1", 0xffffff00, 0, SROM8_AG10, 0xff00},
- {"ag2", 0xffffff00, 0, SROM8_AG32, 0x00ff},
- {"ag3", 0xffffff00, 0, SROM8_AG32, 0xff00},
- {"pa1b0", 0x0000000e, SRFL_PRHEX, SROM_WL1PAB0, 0xffff},
- {"pa1b1", 0x0000000e, SRFL_PRHEX, SROM_WL1PAB1, 0xffff},
- {"pa1b2", 0x0000000e, SRFL_PRHEX, SROM_WL1PAB2, 0xffff},
- {"pa1lob0", 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB0, 0xffff},
- {"pa1lob1", 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB1, 0xffff},
- {"pa1lob2", 0x0000000c, SRFL_PRHEX, SROM_WL1LPAB2, 0xffff},
- {"pa1hib0", 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB0, 0xffff},
- {"pa1hib1", 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB1, 0xffff},
- {"pa1hib2", 0x0000000c, SRFL_PRHEX, SROM_WL1HPAB2, 0xffff},
- {"pa1itssit", 0x0000000e, 0, SROM_ITT, 0xff00},
- {"pa1maxpwr", 0x0000000e, 0, SROM_WL10MAXP, 0xff00},
- {"pa1lomaxpwr", 0x0000000c, 0, SROM_WL1LHMAXP, 0xff00},
- {"pa1himaxpwr", 0x0000000c, 0, SROM_WL1LHMAXP, 0x00ff},
- {"pa1b0", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0, 0xffff},
- {"pa1b1", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1, 0xffff},
- {"pa1b2", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2, 0xffff},
- {"pa1lob0", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0_LC, 0xffff},
- {"pa1lob1", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1_LC, 0xffff},
- {"pa1lob2", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2_LC, 0xffff},
- {"pa1hib0", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB0_HC, 0xffff},
- {"pa1hib1", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB1_HC, 0xffff},
- {"pa1hib2", 0xffffff00, SRFL_PRHEX, SROM8_W1_PAB2_HC, 0xffff},
- {"pa1itssit", 0xffffff00, 0, SROM8_W1_ITTMAXP, 0xff00},
- {"pa1maxpwr", 0xffffff00, 0, SROM8_W1_ITTMAXP, 0x00ff},
- {"pa1lomaxpwr", 0xffffff00, 0, SROM8_W1_MAXP_LCHC, 0xff00},
- {"pa1himaxpwr", 0xffffff00, 0, SROM8_W1_MAXP_LCHC, 0x00ff},
- {"bxa2g", 0x00000008, 0, SROM_BXARSSI2G, 0x1800},
- {"rssisav2g", 0x00000008, 0, SROM_BXARSSI2G, 0x0700},
- {"rssismc2g", 0x00000008, 0, SROM_BXARSSI2G, 0x00f0},
- {"rssismf2g", 0x00000008, 0, SROM_BXARSSI2G, 0x000f},
- {"bxa2g", 0xffffff00, 0, SROM8_BXARSSI2G, 0x1800},
- {"rssisav2g", 0xffffff00, 0, SROM8_BXARSSI2G, 0x0700},
- {"rssismc2g", 0xffffff00, 0, SROM8_BXARSSI2G, 0x00f0},
- {"rssismf2g", 0xffffff00, 0, SROM8_BXARSSI2G, 0x000f},
- {"bxa5g", 0x00000008, 0, SROM_BXARSSI5G, 0x1800},
- {"rssisav5g", 0x00000008, 0, SROM_BXARSSI5G, 0x0700},
- {"rssismc5g", 0x00000008, 0, SROM_BXARSSI5G, 0x00f0},
- {"rssismf5g", 0x00000008, 0, SROM_BXARSSI5G, 0x000f},
- {"bxa5g", 0xffffff00, 0, SROM8_BXARSSI5G, 0x1800},
- {"rssisav5g", 0xffffff00, 0, SROM8_BXARSSI5G, 0x0700},
- {"rssismc5g", 0xffffff00, 0, SROM8_BXARSSI5G, 0x00f0},
- {"rssismf5g", 0xffffff00, 0, SROM8_BXARSSI5G, 0x000f},
- {"tri2g", 0x00000008, 0, SROM_TRI52G, 0x00ff},
- {"tri5g", 0x00000008, 0, SROM_TRI52G, 0xff00},
- {"tri5gl", 0x00000008, 0, SROM_TRI5GHL, 0x00ff},
- {"tri5gh", 0x00000008, 0, SROM_TRI5GHL, 0xff00},
- {"tri2g", 0xffffff00, 0, SROM8_TRI52G, 0x00ff},
- {"tri5g", 0xffffff00, 0, SROM8_TRI52G, 0xff00},
- {"tri5gl", 0xffffff00, 0, SROM8_TRI5GHL, 0x00ff},
- {"tri5gh", 0xffffff00, 0, SROM8_TRI5GHL, 0xff00},
- {"rxpo2g", 0x00000008, SRFL_PRSIGN, SROM_RXPO52G, 0x00ff},
- {"rxpo5g", 0x00000008, SRFL_PRSIGN, SROM_RXPO52G, 0xff00},
- {"rxpo2g", 0xffffff00, SRFL_PRSIGN, SROM8_RXPO52G, 0x00ff},
- {"rxpo5g", 0xffffff00, SRFL_PRSIGN, SROM8_RXPO52G, 0xff00},
- {"txchain", 0x000000f0, SRFL_NOFFS, SROM4_TXRXC, SROM4_TXCHAIN_MASK},
- {"rxchain", 0x000000f0, SRFL_NOFFS, SROM4_TXRXC, SROM4_RXCHAIN_MASK},
- {"antswitch", 0x000000f0, SRFL_NOFFS, SROM4_TXRXC, SROM4_SWITCH_MASK},
- {"txchain", 0xffffff00, SRFL_NOFFS, SROM8_TXRXC, SROM4_TXCHAIN_MASK},
- {"rxchain", 0xffffff00, SRFL_NOFFS, SROM8_TXRXC, SROM4_RXCHAIN_MASK},
- {"antswitch", 0xffffff00, SRFL_NOFFS, SROM8_TXRXC, SROM4_SWITCH_MASK},
- {"tssipos2g", 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_TSSIPOS_MASK},
- {"extpagain2g", 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_EXTPA_GAIN_MASK},
- {"pdetrange2g", 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_PDET_RANGE_MASK},
- {"triso2g", 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_TR_ISO_MASK},
- {"antswctl2g", 0xffffff00, 0, SROM8_FEM2G, SROM8_FEM_ANTSWLUT_MASK},
- {"tssipos5g", 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_TSSIPOS_MASK},
- {"extpagain5g", 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_EXTPA_GAIN_MASK},
- {"pdetrange5g", 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_PDET_RANGE_MASK},
- {"triso5g", 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_TR_ISO_MASK},
- {"antswctl5g", 0xffffff00, 0, SROM8_FEM5G, SROM8_FEM_ANTSWLUT_MASK},
- {"tempthresh", 0xffffff00, 0, SROM8_THERMAL, 0xff00},
- {"tempoffset", 0xffffff00, 0, SROM8_THERMAL, 0x00ff},
- {"txpid2ga0", 0x000000f0, 0, SROM4_TXPID2G, 0x00ff},
- {"txpid2ga1", 0x000000f0, 0, SROM4_TXPID2G, 0xff00},
- {"txpid2ga2", 0x000000f0, 0, SROM4_TXPID2G + 1, 0x00ff},
- {"txpid2ga3", 0x000000f0, 0, SROM4_TXPID2G + 1, 0xff00},
- {"txpid5ga0", 0x000000f0, 0, SROM4_TXPID5G, 0x00ff},
- {"txpid5ga1", 0x000000f0, 0, SROM4_TXPID5G, 0xff00},
- {"txpid5ga2", 0x000000f0, 0, SROM4_TXPID5G + 1, 0x00ff},
- {"txpid5ga3", 0x000000f0, 0, SROM4_TXPID5G + 1, 0xff00},
- {"txpid5gla0", 0x000000f0, 0, SROM4_TXPID5GL, 0x00ff},
- {"txpid5gla1", 0x000000f0, 0, SROM4_TXPID5GL, 0xff00},
- {"txpid5gla2", 0x000000f0, 0, SROM4_TXPID5GL + 1, 0x00ff},
- {"txpid5gla3", 0x000000f0, 0, SROM4_TXPID5GL + 1, 0xff00},
- {"txpid5gha0", 0x000000f0, 0, SROM4_TXPID5GH, 0x00ff},
- {"txpid5gha1", 0x000000f0, 0, SROM4_TXPID5GH, 0xff00},
- {"txpid5gha2", 0x000000f0, 0, SROM4_TXPID5GH + 1, 0x00ff},
- {"txpid5gha3", 0x000000f0, 0, SROM4_TXPID5GH + 1, 0xff00},
-
- {"ccode", 0x0000000f, SRFL_CCODE, SROM_CCODE, 0xffff},
- {"ccode", 0x00000010, SRFL_CCODE, SROM4_CCODE, 0xffff},
- {"ccode", 0x000000e0, SRFL_CCODE, SROM5_CCODE, 0xffff},
- {"ccode", 0xffffff00, SRFL_CCODE, SROM8_CCODE, 0xffff},
- {"macaddr", 0xffffff00, SRFL_ETHADDR, SROM8_MACHI, 0xffff},
- {"macaddr", 0x000000e0, SRFL_ETHADDR, SROM5_MACHI, 0xffff},
- {"macaddr", 0x00000010, SRFL_ETHADDR, SROM4_MACHI, 0xffff},
- {"macaddr", 0x00000008, SRFL_ETHADDR, SROM3_MACHI, 0xffff},
- {"il0macaddr", 0x00000007, SRFL_ETHADDR, SROM_MACHI_IL0, 0xffff},
- {"et1macaddr", 0x00000007, SRFL_ETHADDR, SROM_MACHI_ET1, 0xffff},
- {"leddc", 0xffffff00, SRFL_NOFFS | SRFL_LEDDC, SROM8_LEDDC, 0xffff},
- {"leddc", 0x000000e0, SRFL_NOFFS | SRFL_LEDDC, SROM5_LEDDC, 0xffff},
- {"leddc", 0x00000010, SRFL_NOFFS | SRFL_LEDDC, SROM4_LEDDC, 0xffff},
- {"leddc", 0x00000008, SRFL_NOFFS | SRFL_LEDDC, SROM3_LEDDC, 0xffff},
- {"rawtempsense", 0xffffff00, SRFL_PRHEX, SROM8_MPWR_RAWTS, 0x01ff},
- {"measpower", 0xffffff00, SRFL_PRHEX, SROM8_MPWR_RAWTS, 0xfe00},
- {"tempsense_slope", 0xffffff00, SRFL_PRHEX, SROM8_TS_SLP_OPT_CORRX,
- 0x00ff},
- {"tempcorrx", 0xffffff00, SRFL_PRHEX, SROM8_TS_SLP_OPT_CORRX, 0xfc00},
- {"tempsense_option", 0xffffff00, SRFL_PRHEX, SROM8_TS_SLP_OPT_CORRX,
- 0x0300},
- {"freqoffset_corr", 0xffffff00, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP,
- 0x000f},
- {"iqcal_swp_dis", 0xffffff00, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP, 0x0010},
- {"hw_iqcal_en", 0xffffff00, SRFL_PRHEX, SROM8_FOC_HWIQ_IQSWP, 0x0020},
- {"phycal_tempdelta", 0xffffff00, 0, SROM8_PHYCAL_TEMPDELTA, 0x00ff},
-
- {"cck2gpo", 0x000000f0, 0, SROM4_2G_CCKPO, 0xffff},
- {"cck2gpo", 0x00000100, 0, SROM8_2G_CCKPO, 0xffff},
- {"ofdm2gpo", 0x000000f0, SRFL_MORE, SROM4_2G_OFDMPO, 0xffff},
- {"", 0, 0, SROM4_2G_OFDMPO + 1, 0xffff},
- {"ofdm5gpo", 0x000000f0, SRFL_MORE, SROM4_5G_OFDMPO, 0xffff},
- {"", 0, 0, SROM4_5G_OFDMPO + 1, 0xffff},
- {"ofdm5glpo", 0x000000f0, SRFL_MORE, SROM4_5GL_OFDMPO, 0xffff},
- {"", 0, 0, SROM4_5GL_OFDMPO + 1, 0xffff},
- {"ofdm5ghpo", 0x000000f0, SRFL_MORE, SROM4_5GH_OFDMPO, 0xffff},
- {"", 0, 0, SROM4_5GH_OFDMPO + 1, 0xffff},
- {"ofdm2gpo", 0x00000100, SRFL_MORE, SROM8_2G_OFDMPO, 0xffff},
- {"", 0, 0, SROM8_2G_OFDMPO + 1, 0xffff},
- {"ofdm5gpo", 0x00000100, SRFL_MORE, SROM8_5G_OFDMPO, 0xffff},
- {"", 0, 0, SROM8_5G_OFDMPO + 1, 0xffff},
- {"ofdm5glpo", 0x00000100, SRFL_MORE, SROM8_5GL_OFDMPO, 0xffff},
- {"", 0, 0, SROM8_5GL_OFDMPO + 1, 0xffff},
- {"ofdm5ghpo", 0x00000100, SRFL_MORE, SROM8_5GH_OFDMPO, 0xffff},
- {"", 0, 0, SROM8_5GH_OFDMPO + 1, 0xffff},
- {"mcs2gpo0", 0x000000f0, 0, SROM4_2G_MCSPO, 0xffff},
- {"mcs2gpo1", 0x000000f0, 0, SROM4_2G_MCSPO + 1, 0xffff},
- {"mcs2gpo2", 0x000000f0, 0, SROM4_2G_MCSPO + 2, 0xffff},
- {"mcs2gpo3", 0x000000f0, 0, SROM4_2G_MCSPO + 3, 0xffff},
- {"mcs2gpo4", 0x000000f0, 0, SROM4_2G_MCSPO + 4, 0xffff},
- {"mcs2gpo5", 0x000000f0, 0, SROM4_2G_MCSPO + 5, 0xffff},
- {"mcs2gpo6", 0x000000f0, 0, SROM4_2G_MCSPO + 6, 0xffff},
- {"mcs2gpo7", 0x000000f0, 0, SROM4_2G_MCSPO + 7, 0xffff},
- {"mcs5gpo0", 0x000000f0, 0, SROM4_5G_MCSPO, 0xffff},
- {"mcs5gpo1", 0x000000f0, 0, SROM4_5G_MCSPO + 1, 0xffff},
- {"mcs5gpo2", 0x000000f0, 0, SROM4_5G_MCSPO + 2, 0xffff},
- {"mcs5gpo3", 0x000000f0, 0, SROM4_5G_MCSPO + 3, 0xffff},
- {"mcs5gpo4", 0x000000f0, 0, SROM4_5G_MCSPO + 4, 0xffff},
- {"mcs5gpo5", 0x000000f0, 0, SROM4_5G_MCSPO + 5, 0xffff},
- {"mcs5gpo6", 0x000000f0, 0, SROM4_5G_MCSPO + 6, 0xffff},
- {"mcs5gpo7", 0x000000f0, 0, SROM4_5G_MCSPO + 7, 0xffff},
- {"mcs5glpo0", 0x000000f0, 0, SROM4_5GL_MCSPO, 0xffff},
- {"mcs5glpo1", 0x000000f0, 0, SROM4_5GL_MCSPO + 1, 0xffff},
- {"mcs5glpo2", 0x000000f0, 0, SROM4_5GL_MCSPO + 2, 0xffff},
- {"mcs5glpo3", 0x000000f0, 0, SROM4_5GL_MCSPO + 3, 0xffff},
- {"mcs5glpo4", 0x000000f0, 0, SROM4_5GL_MCSPO + 4, 0xffff},
- {"mcs5glpo5", 0x000000f0, 0, SROM4_5GL_MCSPO + 5, 0xffff},
- {"mcs5glpo6", 0x000000f0, 0, SROM4_5GL_MCSPO + 6, 0xffff},
- {"mcs5glpo7", 0x000000f0, 0, SROM4_5GL_MCSPO + 7, 0xffff},
- {"mcs5ghpo0", 0x000000f0, 0, SROM4_5GH_MCSPO, 0xffff},
- {"mcs5ghpo1", 0x000000f0, 0, SROM4_5GH_MCSPO + 1, 0xffff},
- {"mcs5ghpo2", 0x000000f0, 0, SROM4_5GH_MCSPO + 2, 0xffff},
- {"mcs5ghpo3", 0x000000f0, 0, SROM4_5GH_MCSPO + 3, 0xffff},
- {"mcs5ghpo4", 0x000000f0, 0, SROM4_5GH_MCSPO + 4, 0xffff},
- {"mcs5ghpo5", 0x000000f0, 0, SROM4_5GH_MCSPO + 5, 0xffff},
- {"mcs5ghpo6", 0x000000f0, 0, SROM4_5GH_MCSPO + 6, 0xffff},
- {"mcs5ghpo7", 0x000000f0, 0, SROM4_5GH_MCSPO + 7, 0xffff},
- {"mcs2gpo0", 0x00000100, 0, SROM8_2G_MCSPO, 0xffff},
- {"mcs2gpo1", 0x00000100, 0, SROM8_2G_MCSPO + 1, 0xffff},
- {"mcs2gpo2", 0x00000100, 0, SROM8_2G_MCSPO + 2, 0xffff},
- {"mcs2gpo3", 0x00000100, 0, SROM8_2G_MCSPO + 3, 0xffff},
- {"mcs2gpo4", 0x00000100, 0, SROM8_2G_MCSPO + 4, 0xffff},
- {"mcs2gpo5", 0x00000100, 0, SROM8_2G_MCSPO + 5, 0xffff},
- {"mcs2gpo6", 0x00000100, 0, SROM8_2G_MCSPO + 6, 0xffff},
- {"mcs2gpo7", 0x00000100, 0, SROM8_2G_MCSPO + 7, 0xffff},
- {"mcs5gpo0", 0x00000100, 0, SROM8_5G_MCSPO, 0xffff},
- {"mcs5gpo1", 0x00000100, 0, SROM8_5G_MCSPO + 1, 0xffff},
- {"mcs5gpo2", 0x00000100, 0, SROM8_5G_MCSPO + 2, 0xffff},
- {"mcs5gpo3", 0x00000100, 0, SROM8_5G_MCSPO + 3, 0xffff},
- {"mcs5gpo4", 0x00000100, 0, SROM8_5G_MCSPO + 4, 0xffff},
- {"mcs5gpo5", 0x00000100, 0, SROM8_5G_MCSPO + 5, 0xffff},
- {"mcs5gpo6", 0x00000100, 0, SROM8_5G_MCSPO + 6, 0xffff},
- {"mcs5gpo7", 0x00000100, 0, SROM8_5G_MCSPO + 7, 0xffff},
- {"mcs5glpo0", 0x00000100, 0, SROM8_5GL_MCSPO, 0xffff},
- {"mcs5glpo1", 0x00000100, 0, SROM8_5GL_MCSPO + 1, 0xffff},
- {"mcs5glpo2", 0x00000100, 0, SROM8_5GL_MCSPO + 2, 0xffff},
- {"mcs5glpo3", 0x00000100, 0, SROM8_5GL_MCSPO + 3, 0xffff},
- {"mcs5glpo4", 0x00000100, 0, SROM8_5GL_MCSPO + 4, 0xffff},
- {"mcs5glpo5", 0x00000100, 0, SROM8_5GL_MCSPO + 5, 0xffff},
- {"mcs5glpo6", 0x00000100, 0, SROM8_5GL_MCSPO + 6, 0xffff},
- {"mcs5glpo7", 0x00000100, 0, SROM8_5GL_MCSPO + 7, 0xffff},
- {"mcs5ghpo0", 0x00000100, 0, SROM8_5GH_MCSPO, 0xffff},
- {"mcs5ghpo1", 0x00000100, 0, SROM8_5GH_MCSPO + 1, 0xffff},
- {"mcs5ghpo2", 0x00000100, 0, SROM8_5GH_MCSPO + 2, 0xffff},
- {"mcs5ghpo3", 0x00000100, 0, SROM8_5GH_MCSPO + 3, 0xffff},
- {"mcs5ghpo4", 0x00000100, 0, SROM8_5GH_MCSPO + 4, 0xffff},
- {"mcs5ghpo5", 0x00000100, 0, SROM8_5GH_MCSPO + 5, 0xffff},
- {"mcs5ghpo6", 0x00000100, 0, SROM8_5GH_MCSPO + 6, 0xffff},
- {"mcs5ghpo7", 0x00000100, 0, SROM8_5GH_MCSPO + 7, 0xffff},
- {"cddpo", 0x000000f0, 0, SROM4_CDDPO, 0xffff},
- {"stbcpo", 0x000000f0, 0, SROM4_STBCPO, 0xffff},
- {"bw40po", 0x000000f0, 0, SROM4_BW40PO, 0xffff},
- {"bwduppo", 0x000000f0, 0, SROM4_BWDUPPO, 0xffff},
- {"cddpo", 0x00000100, 0, SROM8_CDDPO, 0xffff},
- {"stbcpo", 0x00000100, 0, SROM8_STBCPO, 0xffff},
- {"bw40po", 0x00000100, 0, SROM8_BW40PO, 0xffff},
- {"bwduppo", 0x00000100, 0, SROM8_BWDUPPO, 0xffff},
-
- /* power per rate from sromrev 9 */
- {"cckbw202gpo", 0xfffffe00, 0, SROM9_2GPO_CCKBW20, 0xffff},
- {"cckbw20ul2gpo", 0xfffffe00, 0, SROM9_2GPO_CCKBW20UL, 0xffff},
- {"legofdmbw202gpo", 0xfffffe00, SRFL_MORE, SROM9_2GPO_LOFDMBW20,
- 0xffff},
- {"", 0, 0, SROM9_2GPO_LOFDMBW20 + 1, 0xffff},
- {"legofdmbw20ul2gpo", 0xfffffe00, SRFL_MORE, SROM9_2GPO_LOFDMBW20UL,
- 0xffff},
- {"", 0, 0, SROM9_2GPO_LOFDMBW20UL + 1, 0xffff},
- {"legofdmbw205glpo", 0xfffffe00, SRFL_MORE, SROM9_5GLPO_LOFDMBW20,
- 0xffff},
- {"", 0, 0, SROM9_5GLPO_LOFDMBW20 + 1, 0xffff},
- {"legofdmbw20ul5glpo", 0xfffffe00, SRFL_MORE, SROM9_5GLPO_LOFDMBW20UL,
- 0xffff},
- {"", 0, 0, SROM9_5GLPO_LOFDMBW20UL + 1, 0xffff},
- {"legofdmbw205gmpo", 0xfffffe00, SRFL_MORE, SROM9_5GMPO_LOFDMBW20,
- 0xffff},
- {"", 0, 0, SROM9_5GMPO_LOFDMBW20 + 1, 0xffff},
- {"legofdmbw20ul5gmpo", 0xfffffe00, SRFL_MORE, SROM9_5GMPO_LOFDMBW20UL,
- 0xffff},
- {"", 0, 0, SROM9_5GMPO_LOFDMBW20UL + 1, 0xffff},
- {"legofdmbw205ghpo", 0xfffffe00, SRFL_MORE, SROM9_5GHPO_LOFDMBW20,
- 0xffff},
- {"", 0, 0, SROM9_5GHPO_LOFDMBW20 + 1, 0xffff},
- {"legofdmbw20ul5ghpo", 0xfffffe00, SRFL_MORE, SROM9_5GHPO_LOFDMBW20UL,
- 0xffff},
- {"", 0, 0, SROM9_5GHPO_LOFDMBW20UL + 1, 0xffff},
- {"mcsbw202gpo", 0xfffffe00, SRFL_MORE, SROM9_2GPO_MCSBW20, 0xffff},
- {"", 0, 0, SROM9_2GPO_MCSBW20 + 1, 0xffff},
- {"mcsbw20ul2gpo", 0xfffffe00, SRFL_MORE, SROM9_2GPO_MCSBW20UL, 0xffff},
- {"", 0, 0, SROM9_2GPO_MCSBW20UL + 1, 0xffff},
- {"mcsbw402gpo", 0xfffffe00, SRFL_MORE, SROM9_2GPO_MCSBW40, 0xffff},
- {"", 0, 0, SROM9_2GPO_MCSBW40 + 1, 0xffff},
- {"mcsbw205glpo", 0xfffffe00, SRFL_MORE, SROM9_5GLPO_MCSBW20, 0xffff},
- {"", 0, 0, SROM9_5GLPO_MCSBW20 + 1, 0xffff},
- {"mcsbw20ul5glpo", 0xfffffe00, SRFL_MORE, SROM9_5GLPO_MCSBW20UL,
- 0xffff},
- {"", 0, 0, SROM9_5GLPO_MCSBW20UL + 1, 0xffff},
- {"mcsbw405glpo", 0xfffffe00, SRFL_MORE, SROM9_5GLPO_MCSBW40, 0xffff},
- {"", 0, 0, SROM9_5GLPO_MCSBW40 + 1, 0xffff},
- {"mcsbw205gmpo", 0xfffffe00, SRFL_MORE, SROM9_5GMPO_MCSBW20, 0xffff},
- {"", 0, 0, SROM9_5GMPO_MCSBW20 + 1, 0xffff},
- {"mcsbw20ul5gmpo", 0xfffffe00, SRFL_MORE, SROM9_5GMPO_MCSBW20UL,
- 0xffff},
- {"", 0, 0, SROM9_5GMPO_MCSBW20UL + 1, 0xffff},
- {"mcsbw405gmpo", 0xfffffe00, SRFL_MORE, SROM9_5GMPO_MCSBW40, 0xffff},
- {"", 0, 0, SROM9_5GMPO_MCSBW40 + 1, 0xffff},
- {"mcsbw205ghpo", 0xfffffe00, SRFL_MORE, SROM9_5GHPO_MCSBW20, 0xffff},
- {"", 0, 0, SROM9_5GHPO_MCSBW20 + 1, 0xffff},
- {"mcsbw20ul5ghpo", 0xfffffe00, SRFL_MORE, SROM9_5GHPO_MCSBW20UL,
- 0xffff},
- {"", 0, 0, SROM9_5GHPO_MCSBW20UL + 1, 0xffff},
- {"mcsbw405ghpo", 0xfffffe00, SRFL_MORE, SROM9_5GHPO_MCSBW40, 0xffff},
- {"", 0, 0, SROM9_5GHPO_MCSBW40 + 1, 0xffff},
- {"mcs32po", 0xfffffe00, 0, SROM9_PO_MCS32, 0xffff},
- {"legofdm40duppo", 0xfffffe00, 0, SROM9_PO_LOFDM40DUP, 0xffff},
-
- {NULL, 0, 0, 0, 0}
-};
-
-static const sromvar_t perpath_pci_sromvars[] = {
- {"maxp2ga", 0x000000f0, 0, SROM4_2G_ITT_MAXP, 0x00ff},
- {"itt2ga", 0x000000f0, 0, SROM4_2G_ITT_MAXP, 0xff00},
- {"itt5ga", 0x000000f0, 0, SROM4_5G_ITT_MAXP, 0xff00},
- {"pa2gw0a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA, 0xffff},
- {"pa2gw1a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 1, 0xffff},
- {"pa2gw2a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 2, 0xffff},
- {"pa2gw3a", 0x000000f0, SRFL_PRHEX, SROM4_2G_PA + 3, 0xffff},
- {"maxp5ga", 0x000000f0, 0, SROM4_5G_ITT_MAXP, 0x00ff},
- {"maxp5gha", 0x000000f0, 0, SROM4_5GLH_MAXP, 0x00ff},
- {"maxp5gla", 0x000000f0, 0, SROM4_5GLH_MAXP, 0xff00},
- {"pa5gw0a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA, 0xffff},
- {"pa5gw1a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 1, 0xffff},
- {"pa5gw2a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 2, 0xffff},
- {"pa5gw3a", 0x000000f0, SRFL_PRHEX, SROM4_5G_PA + 3, 0xffff},
- {"pa5glw0a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA, 0xffff},
- {"pa5glw1a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 1, 0xffff},
- {"pa5glw2a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 2, 0xffff},
- {"pa5glw3a", 0x000000f0, SRFL_PRHEX, SROM4_5GL_PA + 3, 0xffff},
- {"pa5ghw0a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA, 0xffff},
- {"pa5ghw1a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 1, 0xffff},
- {"pa5ghw2a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 2, 0xffff},
- {"pa5ghw3a", 0x000000f0, SRFL_PRHEX, SROM4_5GH_PA + 3, 0xffff},
- {"maxp2ga", 0xffffff00, 0, SROM8_2G_ITT_MAXP, 0x00ff},
- {"itt2ga", 0xffffff00, 0, SROM8_2G_ITT_MAXP, 0xff00},
- {"itt5ga", 0xffffff00, 0, SROM8_5G_ITT_MAXP, 0xff00},
- {"pa2gw0a", 0xffffff00, SRFL_PRHEX, SROM8_2G_PA, 0xffff},
- {"pa2gw1a", 0xffffff00, SRFL_PRHEX, SROM8_2G_PA + 1, 0xffff},
- {"pa2gw2a", 0xffffff00, SRFL_PRHEX, SROM8_2G_PA + 2, 0xffff},
- {"maxp5ga", 0xffffff00, 0, SROM8_5G_ITT_MAXP, 0x00ff},
- {"maxp5gha", 0xffffff00, 0, SROM8_5GLH_MAXP, 0x00ff},
- {"maxp5gla", 0xffffff00, 0, SROM8_5GLH_MAXP, 0xff00},
- {"pa5gw0a", 0xffffff00, SRFL_PRHEX, SROM8_5G_PA, 0xffff},
- {"pa5gw1a", 0xffffff00, SRFL_PRHEX, SROM8_5G_PA + 1, 0xffff},
- {"pa5gw2a", 0xffffff00, SRFL_PRHEX, SROM8_5G_PA + 2, 0xffff},
- {"pa5glw0a", 0xffffff00, SRFL_PRHEX, SROM8_5GL_PA, 0xffff},
- {"pa5glw1a", 0xffffff00, SRFL_PRHEX, SROM8_5GL_PA + 1, 0xffff},
- {"pa5glw2a", 0xffffff00, SRFL_PRHEX, SROM8_5GL_PA + 2, 0xffff},
- {"pa5ghw0a", 0xffffff00, SRFL_PRHEX, SROM8_5GH_PA, 0xffff},
- {"pa5ghw1a", 0xffffff00, SRFL_PRHEX, SROM8_5GH_PA + 1, 0xffff},
- {"pa5ghw2a", 0xffffff00, SRFL_PRHEX, SROM8_5GH_PA + 2, 0xffff},
- {NULL, 0, 0, 0, 0}
-};
-
-#if !(defined(PHY_TYPE_N) && defined(PHY_TYPE_LP))
-#define PHY_TYPE_N 4 /* N-Phy value */
-#define PHY_TYPE_LP 5 /* LP-Phy value */
-#endif /* !(defined(PHY_TYPE_N) && defined(PHY_TYPE_LP)) */
-#if !defined(PHY_TYPE_NULL)
-#define PHY_TYPE_NULL 0xf /* Invalid Phy value */
-#endif /* !defined(PHY_TYPE_NULL) */
-
-typedef struct {
- u16 phy_type;
- u16 bandrange;
- u16 chain;
- const char *vars;
-} pavars_t;
-
-static const pavars_t pavars[] = {
- /* NPHY */
- {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_2G, 0, "pa2gw0a0 pa2gw1a0 pa2gw2a0"},
- {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_2G, 1, "pa2gw0a1 pa2gw1a1 pa2gw2a1"},
- {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GL, 0,
- "pa5glw0a0 pa5glw1a0 pa5glw2a0"},
- {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GL, 1,
- "pa5glw0a1 pa5glw1a1 pa5glw2a1"},
- {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GM, 0, "pa5gw0a0 pa5gw1a0 pa5gw2a0"},
- {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GM, 1, "pa5gw0a1 pa5gw1a1 pa5gw2a1"},
- {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GH, 0,
- "pa5ghw0a0 pa5ghw1a0 pa5ghw2a0"},
- {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GH, 1,
- "pa5ghw0a1 pa5ghw1a1 pa5ghw2a1"},
- /* LPPHY */
- {PHY_TYPE_LP, WL_CHAN_FREQ_RANGE_2G, 0, "pa0b0 pa0b1 pa0b2"},
- {PHY_TYPE_LP, WL_CHAN_FREQ_RANGE_5GL, 0, "pa1lob0 pa1lob1 pa1lob2"},
- {PHY_TYPE_LP, WL_CHAN_FREQ_RANGE_5GM, 0, "pa1b0 pa1b1 pa1b2"},
- {PHY_TYPE_LP, WL_CHAN_FREQ_RANGE_5GH, 0, "pa1hib0 pa1hib1 pa1hib2"},
- {PHY_TYPE_NULL, 0, 0, ""}
-};
-
-typedef struct {
- u16 phy_type;
- u16 bandrange;
- const char *vars;
-} povars_t;
-
-static const povars_t povars[] = {
- /* NPHY */
- {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_2G,
- "mcs2gpo0 mcs2gpo1 mcs2gpo2 mcs2gpo3 "
- "mcs2gpo4 mcs2gpo5 mcs2gpo6 mcs2gpo7"},
- {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GL,
- "mcs5glpo0 mcs5glpo1 mcs5glpo2 mcs5glpo3 "
- "mcs5glpo4 mcs5glpo5 mcs5glpo6 mcs5glpo7"},
- {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GM,
- "mcs5gpo0 mcs5gpo1 mcs5gpo2 mcs5gpo3 "
- "mcs5gpo4 mcs5gpo5 mcs5gpo6 mcs5gpo7"},
- {PHY_TYPE_N, WL_CHAN_FREQ_RANGE_5GH,
- "mcs5ghpo0 mcs5ghpo1 mcs5ghpo2 mcs5ghpo3 "
- "mcs5ghpo4 mcs5ghpo5 mcs5ghpo6 mcs5ghpo7"},
- {PHY_TYPE_NULL, 0, ""}
-};
-
-typedef struct {
- u8 tag; /* Broadcom subtag name */
- u8 len; /* Length field of the tuple, note that it includes the
- * subtag name (1 byte): 1 + tuple content length
- */
- const char *params;
-} cis_tuple_t;
-
-#define OTP_RAW (0xff - 1) /* Reserved tuple number for wrvar Raw input */
-#define OTP_VERS_1 (0xff - 2) /* CISTPL_VERS_1 */
-#define OTP_MANFID (0xff - 3) /* CISTPL_MANFID */
-#define OTP_RAW1 (0xff - 4) /* Like RAW, but comes first */
-
-static const cis_tuple_t cis_hnbuvars[] = {
- {OTP_RAW1, 0, ""}, /* special case */
- {OTP_VERS_1, 0, "smanf sproductname"}, /* special case (non BRCM tuple) */
- {OTP_MANFID, 4, "2manfid 2prodid"}, /* special case (non BRCM tuple) */
- {HNBU_SROMREV, 2, "1sromrev"},
- /* NOTE: subdevid is also written to boardtype.
- * Need to write HNBU_BOARDTYPE to change it if it is different.
- */
- {HNBU_CHIPID, 11, "2vendid 2devid 2chiprev 2subvendid 2subdevid"},
- {HNBU_BOARDREV, 3, "2boardrev"},
- {HNBU_PAPARMS, 10, "2pa0b0 2pa0b1 2pa0b2 1pa0itssit 1pa0maxpwr 1opo"},
- {HNBU_AA, 3, "1aa2g 1aa5g"},
- {HNBU_AA, 3, "1aa0 1aa1"}, /* backward compatibility */
- {HNBU_AG, 5, "1ag0 1ag1 1ag2 1ag3"},
- {HNBU_BOARDFLAGS, 9, "4boardflags 4boardflags2"},
- {HNBU_LEDS, 5, "1ledbh0 1ledbh1 1ledbh2 1ledbh3"},
- {HNBU_CCODE, 4, "2ccode 1cctl"},
- {HNBU_CCKPO, 3, "2cckpo"},
- {HNBU_OFDMPO, 5, "4ofdmpo"},
- {HNBU_RDLID, 3, "2rdlid"},
- {HNBU_RSSISMBXA2G, 3, "0rssismf2g 0rssismc2g 0rssisav2g 0bxa2g"}, /* special case */
- {HNBU_RSSISMBXA5G, 3, "0rssismf5g 0rssismc5g 0rssisav5g 0bxa5g"}, /* special case */
- {HNBU_XTALFREQ, 5, "4xtalfreq"},
- {HNBU_TRI2G, 2, "1tri2g"},
- {HNBU_TRI5G, 4, "1tri5gl 1tri5g 1tri5gh"},
- {HNBU_RXPO2G, 2, "1rxpo2g"},
- {HNBU_RXPO5G, 2, "1rxpo5g"},
- {HNBU_BOARDNUM, 3, "2boardnum"},
- {HNBU_MACADDR, 7, "6macaddr"}, /* special case */
- {HNBU_RDLSN, 3, "2rdlsn"},
- {HNBU_BOARDTYPE, 3, "2boardtype"},
- {HNBU_LEDDC, 3, "2leddc"},
- {HNBU_RDLRNDIS, 2, "1rdlndis"},
- {HNBU_CHAINSWITCH, 5, "1txchain 1rxchain 2antswitch"},
- {HNBU_REGREV, 2, "1regrev"},
- {HNBU_FEM, 5, "0antswctl2g, 0triso2g, 0pdetrange2g, 0extpagain2g, 0tssipos2g" "0antswctl5g, 0triso5g, 0pdetrange5g, 0extpagain5g, 0tssipos5g"}, /* special case */
- {HNBU_PAPARMS_C0, 31, "1maxp2ga0 1itt2ga0 2pa2gw0a0 2pa2gw1a0 "
- "2pa2gw2a0 1maxp5ga0 1itt5ga0 1maxp5gha0 1maxp5gla0 2pa5gw0a0 "
- "2pa5gw1a0 2pa5gw2a0 2pa5glw0a0 2pa5glw1a0 2pa5glw2a0 2pa5ghw0a0 "
- "2pa5ghw1a0 2pa5ghw2a0"},
- {HNBU_PAPARMS_C1, 31, "1maxp2ga1 1itt2ga1 2pa2gw0a1 2pa2gw1a1 "
- "2pa2gw2a1 1maxp5ga1 1itt5ga1 1maxp5gha1 1maxp5gla1 2pa5gw0a1 "
- "2pa5gw1a1 2pa5gw2a1 2pa5glw0a1 2pa5glw1a1 2pa5glw2a1 2pa5ghw0a1 "
- "2pa5ghw1a1 2pa5ghw2a1"},
- {HNBU_PO_CCKOFDM, 19, "2cck2gpo 4ofdm2gpo 4ofdm5gpo 4ofdm5glpo "
- "4ofdm5ghpo"},
- {HNBU_PO_MCS2G, 17, "2mcs2gpo0 2mcs2gpo1 2mcs2gpo2 2mcs2gpo3 "
- "2mcs2gpo4 2mcs2gpo5 2mcs2gpo6 2mcs2gpo7"},
- {HNBU_PO_MCS5GM, 17, "2mcs5gpo0 2mcs5gpo1 2mcs5gpo2 2mcs5gpo3 "
- "2mcs5gpo4 2mcs5gpo5 2mcs5gpo6 2mcs5gpo7"},
- {HNBU_PO_MCS5GLH, 33, "2mcs5glpo0 2mcs5glpo1 2mcs5glpo2 2mcs5glpo3 "
- "2mcs5glpo4 2mcs5glpo5 2mcs5glpo6 2mcs5glpo7 "
- "2mcs5ghpo0 2mcs5ghpo1 2mcs5ghpo2 2mcs5ghpo3 "
- "2mcs5ghpo4 2mcs5ghpo5 2mcs5ghpo6 2mcs5ghpo7"},
- {HNBU_CCKFILTTYPE, 2, "1cckdigfilttype"},
- {HNBU_PO_CDD, 3, "2cddpo"},
- {HNBU_PO_STBC, 3, "2stbcpo"},
- {HNBU_PO_40M, 3, "2bw40po"},
- {HNBU_PO_40MDUP, 3, "2bwduppo"},
- {HNBU_RDLRWU, 2, "1rdlrwu"},
- {HNBU_WPS, 3, "1wpsgpio 1wpsled"},
- {HNBU_USBFS, 2, "1usbfs"},
- {HNBU_CUSTOM1, 5, "4customvar1"},
- {OTP_RAW, 0, ""}, /* special case */
- {HNBU_OFDMPO5G, 13, "4ofdm5gpo 4ofdm5glpo 4ofdm5ghpo"},
- {HNBU_USBEPNUM, 3, "2usbepnum"},
- {0xFF, 0, ""}
-};
-
-#endif /* _bcmsrom_tbl_h_ */
diff --git a/drivers/staging/brcm80211/util/bcmutils.c b/drivers/staging/brcm80211/util/bcmutils.c
index fb0bccc..43e5bb3 100644
--- a/drivers/staging/brcm80211/util/bcmutils.c
+++ b/drivers/staging/brcm80211/util/bcmutils.c
@@ -21,18 +21,20 @@
#include <linux/pci.h>
#include <linux/netdevice.h>
#include <linux/sched.h>
+#include <linux/printk.h>
#include <bcmdefs.h>
#include <stdarg.h>
#include <bcmutils.h>
-#include <siutils.h>
#include <bcmnvram.h>
#include <bcmdevs.h>
#include <proto/802.11.h>
-/* Global ASSERT type flag */
-u32 g_assert_type;
+MODULE_AUTHOR("Broadcom Corporation");
+MODULE_DESCRIPTION("Broadcom 802.11n wireless LAN driver utilities.");
+MODULE_SUPPORTED_DEVICE("Broadcom 802.11n WLAN cards");
+MODULE_LICENSE("Dual BSD/GPL");
-struct sk_buff *BCMFASTPATH pkt_buf_get_skb(uint len)
+struct sk_buff *bcm_pkt_buf_get_skb(uint len)
{
struct sk_buff *skb;
@@ -44,15 +46,14 @@
return skb;
}
+EXPORT_SYMBOL(bcm_pkt_buf_get_skb);
/* Free the driver packet. Free the tag if present */
-void BCMFASTPATH pkt_buf_free_skb(struct sk_buff *skb)
+void bcm_pkt_buf_free_skb(struct sk_buff *skb)
{
struct sk_buff *nskb;
int nest = 0;
- ASSERT(skb);
-
/* perversion: we use skb->next to chain multi-skb packets */
while (skb) {
nskb = skb->next;
@@ -73,9 +74,11 @@
skb = nskb;
}
}
+EXPORT_SYMBOL(bcm_pkt_buf_free_skb);
+
/* copy a buffer into a pkt buffer chain */
-uint pktfrombuf(struct sk_buff *p, uint offset, int len,
+uint bcm_pktfrombuf(struct sk_buff *p, uint offset, int len,
unsigned char *buf)
{
uint n, ret = 0;
@@ -102,8 +105,10 @@
return ret;
}
+EXPORT_SYMBOL(bcm_pktfrombuf);
+
/* return total length of buffer chain */
-uint BCMFASTPATH pkttotlen(struct sk_buff *p)
+uint bcm_pkttotlen(struct sk_buff *p)
{
uint total;
@@ -112,21 +117,19 @@
total += p->len;
return total;
}
+EXPORT_SYMBOL(bcm_pkttotlen);
/*
* osl multiple-precedence packet queue
* hi_prec is always >= the number of the highest non-empty precedence
*/
-struct sk_buff *BCMFASTPATH pktq_penq(struct pktq *pq, int prec,
+struct sk_buff *bcm_pktq_penq(struct pktq *pq, int prec,
struct sk_buff *p)
{
struct pktq_prec *q;
- ASSERT(prec >= 0 && prec < pq->num_prec);
- ASSERT(p->prev == NULL); /* queueing chains not allowed */
-
- ASSERT(!pktq_full(pq));
- ASSERT(!pktq_pfull(pq, prec));
+ if (pktq_full(pq) || pktq_pfull(pq, prec))
+ return NULL;
q = &pq->q[prec];
@@ -145,17 +148,15 @@
return p;
}
+EXPORT_SYMBOL(bcm_pktq_penq);
-struct sk_buff *BCMFASTPATH pktq_penq_head(struct pktq *pq, int prec,
+struct sk_buff *bcm_pktq_penq_head(struct pktq *pq, int prec,
struct sk_buff *p)
{
struct pktq_prec *q;
- ASSERT(prec >= 0 && prec < pq->num_prec);
- ASSERT(p->prev == NULL); /* queueing chains not allowed */
-
- ASSERT(!pktq_full(pq));
- ASSERT(!pktq_pfull(pq, prec));
+ if (pktq_full(pq) || pktq_pfull(pq, prec))
+ return NULL;
q = &pq->q[prec];
@@ -173,14 +174,13 @@
return p;
}
+EXPORT_SYMBOL(bcm_pktq_penq_head);
-struct sk_buff *BCMFASTPATH pktq_pdeq(struct pktq *pq, int prec)
+struct sk_buff *bcm_pktq_pdeq(struct pktq *pq, int prec)
{
struct pktq_prec *q;
struct sk_buff *p;
- ASSERT(prec >= 0 && prec < pq->num_prec);
-
q = &pq->q[prec];
p = q->head;
@@ -199,14 +199,13 @@
return p;
}
+EXPORT_SYMBOL(bcm_pktq_pdeq);
-struct sk_buff *BCMFASTPATH pktq_pdeq_tail(struct pktq *pq, int prec)
+struct sk_buff *bcm_pktq_pdeq_tail(struct pktq *pq, int prec)
{
struct pktq_prec *q;
struct sk_buff *p, *prev;
- ASSERT(prec >= 0 && prec < pq->num_prec);
-
q = &pq->q[prec];
p = q->head;
@@ -228,38 +227,11 @@
return p;
}
+EXPORT_SYMBOL(bcm_pktq_pdeq_tail);
-#ifdef BRCM_FULLMAC
-void pktq_pflush(struct pktq *pq, int prec, bool dir)
-{
- struct pktq_prec *q;
- struct sk_buff *p;
-
- q = &pq->q[prec];
- p = q->head;
- while (p) {
- q->head = p->prev;
- p->prev = NULL;
- pkt_buf_free_skb(p);
- q->len--;
- pq->len--;
- p = q->head;
- }
- ASSERT(q->len == 0);
- q->tail = NULL;
-}
-
-void pktq_flush(struct pktq *pq, bool dir)
-{
- int prec;
- for (prec = 0; prec < pq->num_prec; prec++)
- pktq_pflush(pq, prec, dir);
- ASSERT(pq->len == 0);
-}
-#else /* !BRCM_FULLMAC */
void
-pktq_pflush(struct pktq *pq, int prec, bool dir,
- ifpkt_cb_t fn, int arg)
+bcm_pktq_pflush(struct pktq *pq, int prec, bool dir,
+ ifpkt_cb_t fn, void *arg)
{
struct pktq_prec *q;
struct sk_buff *p, *prev = NULL;
@@ -274,7 +246,7 @@
else
prev->prev = p->prev;
p->prev = NULL;
- pkt_buf_free_skb(p);
+ bcm_pkt_buf_free_skb(p);
q->len--;
pq->len--;
p = (head ? q->head : prev->prev);
@@ -285,28 +257,24 @@
}
if (q->head == NULL) {
- ASSERT(q->len == 0);
q->tail = NULL;
}
}
+EXPORT_SYMBOL(bcm_pktq_pflush);
-void pktq_flush(struct pktq *pq, bool dir,
- ifpkt_cb_t fn, int arg)
+void bcm_pktq_flush(struct pktq *pq, bool dir,
+ ifpkt_cb_t fn, void *arg)
{
int prec;
for (prec = 0; prec < pq->num_prec; prec++)
- pktq_pflush(pq, prec, dir, fn, arg);
- if (fn == NULL)
- ASSERT(pq->len == 0);
+ bcm_pktq_pflush(pq, prec, dir, fn, arg);
}
-#endif /* BRCM_FULLMAC */
+EXPORT_SYMBOL(bcm_pktq_flush);
-void pktq_init(struct pktq *pq, int num_prec, int max_len)
+void bcm_pktq_init(struct pktq *pq, int num_prec, int max_len)
{
int prec;
- ASSERT(num_prec > 0 && num_prec <= PKTQ_MAX_PREC);
-
/* pq is variable size; only zero out what's requested */
memset(pq, 0,
offsetof(struct pktq, q) + (sizeof(struct pktq_prec) * num_prec));
@@ -318,8 +286,9 @@
for (prec = 0; prec < num_prec; prec++)
pq->q[prec].max = pq->max;
}
+EXPORT_SYMBOL(bcm_pktq_init);
-struct sk_buff *pktq_peek_tail(struct pktq *pq, int *prec_out)
+struct sk_buff *bcm_pktq_peek_tail(struct pktq *pq, int *prec_out)
{
int prec;
@@ -335,9 +304,10 @@
return pq->q[prec].tail;
}
+EXPORT_SYMBOL(bcm_pktq_peek_tail);
/* Return sum of lengths of a specific set of precedences */
-int pktq_mlen(struct pktq *pq, uint prec_bmp)
+int bcm_pktq_mlen(struct pktq *pq, uint prec_bmp)
{
int prec, len;
@@ -349,8 +319,10 @@
return len;
}
+EXPORT_SYMBOL(bcm_pktq_mlen);
+
/* Priority dequeue from a specific set of precedences */
-struct sk_buff *BCMFASTPATH pktq_mdeq(struct pktq *pq, uint prec_bmp,
+struct sk_buff *bcm_pktq_mdeq(struct pktq *pq, uint prec_bmp,
int *prec_out)
{
struct pktq_prec *q;
@@ -388,6 +360,7 @@
return p;
}
+EXPORT_SYMBOL(bcm_pktq_mdeq);
/* parse a xx:xx:xx:xx:xx:xx format ethernet address */
int bcm_ether_atoe(char *p, u8 *ea)
@@ -402,57 +375,11 @@
return i == 6;
}
-
-/*
- * Search the name=value vars for a specific one and return its value.
- * Returns NULL if not found.
- */
-char *getvar(char *vars, const char *name)
-{
- char *s;
- int len;
-
- if (!name)
- return NULL;
-
- len = strlen(name);
- if (len == 0)
- return NULL;
-
- /* first look in vars[] */
- for (s = vars; s && *s;) {
- if ((memcmp(s, name, len) == 0) && (s[len] == '='))
- return &s[len + 1];
-
- while (*s++)
- ;
- }
-#ifdef BRCM_FULLMAC
- return NULL;
-#else
- /* then query nvram */
- return nvram_get(name);
-#endif
-}
-
-/*
- * Search the vars for a specific one and return its value as
- * an integer. Returns 0 if not found.
- */
-int getintvar(char *vars, const char *name)
-{
- char *val;
-
- val = getvar(vars, name);
- if (val == NULL)
- return 0;
-
- return simple_strtoul(val, NULL, 0);
-}
+EXPORT_SYMBOL(bcm_ether_atoe);
#if defined(BCMDBG)
/* pretty hex print a pkt buffer chain */
-void prpkt(const char *msg, struct sk_buff *p0)
+void bcm_prpkt(const char *msg, struct sk_buff *p0)
{
struct sk_buff *p;
@@ -460,32 +387,11 @@
printk(KERN_DEBUG "%s:\n", msg);
for (p = p0; p; p = p->next)
- prhex(NULL, p->data, p->len);
+ print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, p->data, p->len);
}
+EXPORT_SYMBOL(bcm_prpkt);
#endif /* defined(BCMDBG) */
-static char bcm_undeferrstr[BCME_STRLEN];
-
-static const char *bcmerrorstrtable[] = BCMERRSTRINGTABLE;
-
-/* Convert the error codes into related error strings */
-const char *bcmerrorstr(int bcmerror)
-{
- /* check if someone added a bcmerror code but
- forgot to add errorstring */
- ASSERT(ABS(BCME_LAST) == (ARRAY_SIZE(bcmerrorstrtable) - 1));
-
- if (bcmerror > 0 || bcmerror < BCME_LAST) {
- snprintf(bcm_undeferrstr, BCME_STRLEN, "Undefined error %d",
- bcmerror);
- return bcm_undeferrstr;
- }
-
- ASSERT(strlen(bcmerrorstrtable[-bcmerror]) < BCME_STRLEN);
-
- return bcmerrorstrtable[-bcmerror];
-}
-
/* iovar table lookup */
const bcm_iovar_t *bcm_iovar_lookup(const bcm_iovar_t *table, const char *name)
{
@@ -499,8 +405,6 @@
else
lookup_name = name;
- ASSERT(table != NULL);
-
for (vi = table; vi->name; vi++) {
if (!strcmp(vi->name, lookup_name))
return vi;
@@ -509,6 +413,7 @@
return NULL; /* var name not found */
}
+EXPORT_SYMBOL(bcm_iovar_lookup);
int bcm_iovar_lencheck(const bcm_iovar_t *vi, void *arg, int len, bool set)
{
@@ -525,35 +430,35 @@
case IOVT_UINT32:
/* all integers are s32 sized args at the ioctl interface */
if (len < (int)sizeof(int)) {
- bcmerror = BCME_BUFTOOSHORT;
+ bcmerror = -EOVERFLOW;
}
break;
case IOVT_BUFFER:
/* buffer must meet minimum length requirement */
if (len < vi->minlen) {
- bcmerror = BCME_BUFTOOSHORT;
+ bcmerror = -EOVERFLOW;
}
break;
case IOVT_VOID:
if (!set) {
/* Cannot return nil... */
- bcmerror = BCME_UNSUPPORTED;
+ bcmerror = -ENOTSUPP;
} else if (len) {
/* Set is an action w/o parameters */
- bcmerror = BCME_BUFTOOLONG;
+ bcmerror = -ENOBUFS;
}
break;
default:
/* unknown type for length check in iovar info */
- ASSERT(0);
- bcmerror = BCME_UNSUPPORTED;
+ bcmerror = -ENOTSUPP;
}
return bcmerror;
}
+EXPORT_SYMBOL(bcm_iovar_lencheck);
/*******************************************************************************
* crc8
@@ -612,195 +517,18 @@
0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F
};
-#define CRC_INNER_LOOP(n, c, x) \
- ((c) = ((c) >> 8) ^ crc##n##_table[((c) ^ (x)) & 0xff])
-
-u8 hndcrc8(u8 *pdata, /* pointer to array of data to process */
+u8 bcm_crc8(u8 *pdata, /* pointer to array of data to process */
uint nbytes, /* number of input data bytes to process */
u8 crc /* either CRC8_INIT_VALUE or previous return value */
) {
- /* hard code the crc loop instead of using CRC_INNER_LOOP macro
- * to avoid the undefined and unnecessary (u8 >> 8) operation.
- */
+ /* loop over the buffer data */
while (nbytes-- > 0)
crc = crc8_table[(crc ^ *pdata++) & 0xff];
return crc;
}
+EXPORT_SYMBOL(bcm_crc8);
-/*******************************************************************************
- * crc16
- *
- * Computes a crc16 over the input data using the polynomial:
- *
- * x^16 + x^12 +x^5 + 1
- *
- * The caller provides the initial value (either CRC16_INIT_VALUE
- * or the previous returned value) to allow for processing of
- * discontiguous blocks of data. When generating the CRC the
- * caller is responsible for complementing the final return value
- * and inserting it into the byte stream. When checking, a final
- * return value of CRC16_GOOD_VALUE indicates a valid CRC.
- *
- * Reference: Dallas Semiconductor Application Note 27
- * Williams, Ross N., "A Painless Guide to CRC Error Detection Algorithms",
- * ver 3, Aug 1993, ross@guest.adelaide.edu.au, Rocksoft Pty Ltd.,
- * ftp://ftp.rocksoft.com/clients/rocksoft/papers/crc_v3.txt
- *
- * ****************************************************************************
- */
-
-static const u16 crc16_table[256] = {
- 0x0000, 0x1189, 0x2312, 0x329B, 0x4624, 0x57AD, 0x6536, 0x74BF,
- 0x8C48, 0x9DC1, 0xAF5A, 0xBED3, 0xCA6C, 0xDBE5, 0xE97E, 0xF8F7,
- 0x1081, 0x0108, 0x3393, 0x221A, 0x56A5, 0x472C, 0x75B7, 0x643E,
- 0x9CC9, 0x8D40, 0xBFDB, 0xAE52, 0xDAED, 0xCB64, 0xF9FF, 0xE876,
- 0x2102, 0x308B, 0x0210, 0x1399, 0x6726, 0x76AF, 0x4434, 0x55BD,
- 0xAD4A, 0xBCC3, 0x8E58, 0x9FD1, 0xEB6E, 0xFAE7, 0xC87C, 0xD9F5,
- 0x3183, 0x200A, 0x1291, 0x0318, 0x77A7, 0x662E, 0x54B5, 0x453C,
- 0xBDCB, 0xAC42, 0x9ED9, 0x8F50, 0xFBEF, 0xEA66, 0xD8FD, 0xC974,
- 0x4204, 0x538D, 0x6116, 0x709F, 0x0420, 0x15A9, 0x2732, 0x36BB,
- 0xCE4C, 0xDFC5, 0xED5E, 0xFCD7, 0x8868, 0x99E1, 0xAB7A, 0xBAF3,
- 0x5285, 0x430C, 0x7197, 0x601E, 0x14A1, 0x0528, 0x37B3, 0x263A,
- 0xDECD, 0xCF44, 0xFDDF, 0xEC56, 0x98E9, 0x8960, 0xBBFB, 0xAA72,
- 0x6306, 0x728F, 0x4014, 0x519D, 0x2522, 0x34AB, 0x0630, 0x17B9,
- 0xEF4E, 0xFEC7, 0xCC5C, 0xDDD5, 0xA96A, 0xB8E3, 0x8A78, 0x9BF1,
- 0x7387, 0x620E, 0x5095, 0x411C, 0x35A3, 0x242A, 0x16B1, 0x0738,
- 0xFFCF, 0xEE46, 0xDCDD, 0xCD54, 0xB9EB, 0xA862, 0x9AF9, 0x8B70,
- 0x8408, 0x9581, 0xA71A, 0xB693, 0xC22C, 0xD3A5, 0xE13E, 0xF0B7,
- 0x0840, 0x19C9, 0x2B52, 0x3ADB, 0x4E64, 0x5FED, 0x6D76, 0x7CFF,
- 0x9489, 0x8500, 0xB79B, 0xA612, 0xD2AD, 0xC324, 0xF1BF, 0xE036,
- 0x18C1, 0x0948, 0x3BD3, 0x2A5A, 0x5EE5, 0x4F6C, 0x7DF7, 0x6C7E,
- 0xA50A, 0xB483, 0x8618, 0x9791, 0xE32E, 0xF2A7, 0xC03C, 0xD1B5,
- 0x2942, 0x38CB, 0x0A50, 0x1BD9, 0x6F66, 0x7EEF, 0x4C74, 0x5DFD,
- 0xB58B, 0xA402, 0x9699, 0x8710, 0xF3AF, 0xE226, 0xD0BD, 0xC134,
- 0x39C3, 0x284A, 0x1AD1, 0x0B58, 0x7FE7, 0x6E6E, 0x5CF5, 0x4D7C,
- 0xC60C, 0xD785, 0xE51E, 0xF497, 0x8028, 0x91A1, 0xA33A, 0xB2B3,
- 0x4A44, 0x5BCD, 0x6956, 0x78DF, 0x0C60, 0x1DE9, 0x2F72, 0x3EFB,
- 0xD68D, 0xC704, 0xF59F, 0xE416, 0x90A9, 0x8120, 0xB3BB, 0xA232,
- 0x5AC5, 0x4B4C, 0x79D7, 0x685E, 0x1CE1, 0x0D68, 0x3FF3, 0x2E7A,
- 0xE70E, 0xF687, 0xC41C, 0xD595, 0xA12A, 0xB0A3, 0x8238, 0x93B1,
- 0x6B46, 0x7ACF, 0x4854, 0x59DD, 0x2D62, 0x3CEB, 0x0E70, 0x1FF9,
- 0xF78F, 0xE606, 0xD49D, 0xC514, 0xB1AB, 0xA022, 0x92B9, 0x8330,
- 0x7BC7, 0x6A4E, 0x58D5, 0x495C, 0x3DE3, 0x2C6A, 0x1EF1, 0x0F78
-};
-
-u16 hndcrc16(u8 *pdata, /* pointer to array of data to process */
- uint nbytes, /* number of input data bytes to process */
- u16 crc /* either CRC16_INIT_VALUE or previous return value */
- ) {
- while (nbytes-- > 0)
- CRC_INNER_LOOP(16, crc, *pdata++);
- return crc;
-}
-
-static const u32 crc32_table[256] = {
- 0x00000000, 0x77073096, 0xEE0E612C, 0x990951BA,
- 0x076DC419, 0x706AF48F, 0xE963A535, 0x9E6495A3,
- 0x0EDB8832, 0x79DCB8A4, 0xE0D5E91E, 0x97D2D988,
- 0x09B64C2B, 0x7EB17CBD, 0xE7B82D07, 0x90BF1D91,
- 0x1DB71064, 0x6AB020F2, 0xF3B97148, 0x84BE41DE,
- 0x1ADAD47D, 0x6DDDE4EB, 0xF4D4B551, 0x83D385C7,
- 0x136C9856, 0x646BA8C0, 0xFD62F97A, 0x8A65C9EC,
- 0x14015C4F, 0x63066CD9, 0xFA0F3D63, 0x8D080DF5,
- 0x3B6E20C8, 0x4C69105E, 0xD56041E4, 0xA2677172,
- 0x3C03E4D1, 0x4B04D447, 0xD20D85FD, 0xA50AB56B,
- 0x35B5A8FA, 0x42B2986C, 0xDBBBC9D6, 0xACBCF940,
- 0x32D86CE3, 0x45DF5C75, 0xDCD60DCF, 0xABD13D59,
- 0x26D930AC, 0x51DE003A, 0xC8D75180, 0xBFD06116,
- 0x21B4F4B5, 0x56B3C423, 0xCFBA9599, 0xB8BDA50F,
- 0x2802B89E, 0x5F058808, 0xC60CD9B2, 0xB10BE924,
- 0x2F6F7C87, 0x58684C11, 0xC1611DAB, 0xB6662D3D,
- 0x76DC4190, 0x01DB7106, 0x98D220BC, 0xEFD5102A,
- 0x71B18589, 0x06B6B51F, 0x9FBFE4A5, 0xE8B8D433,
- 0x7807C9A2, 0x0F00F934, 0x9609A88E, 0xE10E9818,
- 0x7F6A0DBB, 0x086D3D2D, 0x91646C97, 0xE6635C01,
- 0x6B6B51F4, 0x1C6C6162, 0x856530D8, 0xF262004E,
- 0x6C0695ED, 0x1B01A57B, 0x8208F4C1, 0xF50FC457,
- 0x65B0D9C6, 0x12B7E950, 0x8BBEB8EA, 0xFCB9887C,
- 0x62DD1DDF, 0x15DA2D49, 0x8CD37CF3, 0xFBD44C65,
- 0x4DB26158, 0x3AB551CE, 0xA3BC0074, 0xD4BB30E2,
- 0x4ADFA541, 0x3DD895D7, 0xA4D1C46D, 0xD3D6F4FB,
- 0x4369E96A, 0x346ED9FC, 0xAD678846, 0xDA60B8D0,
- 0x44042D73, 0x33031DE5, 0xAA0A4C5F, 0xDD0D7CC9,
- 0x5005713C, 0x270241AA, 0xBE0B1010, 0xC90C2086,
- 0x5768B525, 0x206F85B3, 0xB966D409, 0xCE61E49F,
- 0x5EDEF90E, 0x29D9C998, 0xB0D09822, 0xC7D7A8B4,
- 0x59B33D17, 0x2EB40D81, 0xB7BD5C3B, 0xC0BA6CAD,
- 0xEDB88320, 0x9ABFB3B6, 0x03B6E20C, 0x74B1D29A,
- 0xEAD54739, 0x9DD277AF, 0x04DB2615, 0x73DC1683,
- 0xE3630B12, 0x94643B84, 0x0D6D6A3E, 0x7A6A5AA8,
- 0xE40ECF0B, 0x9309FF9D, 0x0A00AE27, 0x7D079EB1,
- 0xF00F9344, 0x8708A3D2, 0x1E01F268, 0x6906C2FE,
- 0xF762575D, 0x806567CB, 0x196C3671, 0x6E6B06E7,
- 0xFED41B76, 0x89D32BE0, 0x10DA7A5A, 0x67DD4ACC,
- 0xF9B9DF6F, 0x8EBEEFF9, 0x17B7BE43, 0x60B08ED5,
- 0xD6D6A3E8, 0xA1D1937E, 0x38D8C2C4, 0x4FDFF252,
- 0xD1BB67F1, 0xA6BC5767, 0x3FB506DD, 0x48B2364B,
- 0xD80D2BDA, 0xAF0A1B4C, 0x36034AF6, 0x41047A60,
- 0xDF60EFC3, 0xA867DF55, 0x316E8EEF, 0x4669BE79,
- 0xCB61B38C, 0xBC66831A, 0x256FD2A0, 0x5268E236,
- 0xCC0C7795, 0xBB0B4703, 0x220216B9, 0x5505262F,
- 0xC5BA3BBE, 0xB2BD0B28, 0x2BB45A92, 0x5CB36A04,
- 0xC2D7FFA7, 0xB5D0CF31, 0x2CD99E8B, 0x5BDEAE1D,
- 0x9B64C2B0, 0xEC63F226, 0x756AA39C, 0x026D930A,
- 0x9C0906A9, 0xEB0E363F, 0x72076785, 0x05005713,
- 0x95BF4A82, 0xE2B87A14, 0x7BB12BAE, 0x0CB61B38,
- 0x92D28E9B, 0xE5D5BE0D, 0x7CDCEFB7, 0x0BDBDF21,
- 0x86D3D2D4, 0xF1D4E242, 0x68DDB3F8, 0x1FDA836E,
- 0x81BE16CD, 0xF6B9265B, 0x6FB077E1, 0x18B74777,
- 0x88085AE6, 0xFF0F6A70, 0x66063BCA, 0x11010B5C,
- 0x8F659EFF, 0xF862AE69, 0x616BFFD3, 0x166CCF45,
- 0xA00AE278, 0xD70DD2EE, 0x4E048354, 0x3903B3C2,
- 0xA7672661, 0xD06016F7, 0x4969474D, 0x3E6E77DB,
- 0xAED16A4A, 0xD9D65ADC, 0x40DF0B66, 0x37D83BF0,
- 0xA9BCAE53, 0xDEBB9EC5, 0x47B2CF7F, 0x30B5FFE9,
- 0xBDBDF21C, 0xCABAC28A, 0x53B39330, 0x24B4A3A6,
- 0xBAD03605, 0xCDD70693, 0x54DE5729, 0x23D967BF,
- 0xB3667A2E, 0xC4614AB8, 0x5D681B02, 0x2A6F2B94,
- 0xB40BBE37, 0xC30C8EA1, 0x5A05DF1B, 0x2D02EF8D
-};
-
-u32 hndcrc32(u8 *pdata, /* pointer to array of data to process */
- uint nbytes, /* number of input data bytes to process */
- u32 crc /* either CRC32_INIT_VALUE or previous
- return value */
-)
-{
- u8 *pend;
-#ifdef __mips__
- u8 tmp[4];
- unsigned long *tptr = (unsigned long *) tmp;
-
- /* in case the beginning of the buffer isn't aligned */
- pend = (u8 *) ((uint) (pdata + 3) & 0xfffffffc);
- nbytes -= (pend - pdata);
- while (pdata < pend)
- CRC_INNER_LOOP(32, crc, *pdata++);
-
- /* handle bulk of data as 32-bit words */
- pend = pdata + (nbytes & 0xfffffffc);
- while (pdata < pend) {
- *tptr = *(unsigned long *) pdata;
- pdata += sizeof(unsigned long *);
- CRC_INNER_LOOP(32, crc, tmp[0]);
- CRC_INNER_LOOP(32, crc, tmp[1]);
- CRC_INNER_LOOP(32, crc, tmp[2]);
- CRC_INNER_LOOP(32, crc, tmp[3]);
- }
-
- /* 1-3 bytes at end of buffer */
- pend = pdata + (nbytes & 0x03);
- while (pdata < pend)
- CRC_INNER_LOOP(32, crc, *pdata++);
-#else
- pend = pdata + nbytes;
- while (pdata < pend)
- CRC_INNER_LOOP(32, crc, *pdata++);
-#endif /* __mips__ */
-
- return crc;
-}
/*
* Traverse a string of 1-byte tag/1-byte length/variable-length value
* triples, returning a pointer to the substring whose first element
@@ -828,6 +556,7 @@
return NULL;
}
+EXPORT_SYMBOL(bcm_parse_tlvs);
#if defined(BCMDBG)
@@ -883,6 +612,7 @@
return (int)(p - buf);
}
+EXPORT_SYMBOL(bcm_format_flags);
/* print bytes formatted as hex to a string. return the resulting string length */
int bcm_format_hex(char *str, const void *bytes, int len)
@@ -897,44 +627,9 @@
}
return (int)(p - str);
}
+EXPORT_SYMBOL(bcm_format_hex);
#endif /* defined(BCMDBG) */
-/* pretty hex print a contiguous buffer */
-void prhex(const char *msg, unsigned char *buf, uint nbytes)
-{
- char line[128], *p;
- int len = sizeof(line);
- int nchar;
- uint i;
-
- if (msg && (msg[0] != '\0'))
- printk(KERN_DEBUG "%s:\n", msg);
-
- p = line;
- for (i = 0; i < nbytes; i++) {
- if (i % 16 == 0) {
- nchar = snprintf(p, len, " %04d: ", i); /* line prefix */
- p += nchar;
- len -= nchar;
- }
- if (len > 0) {
- nchar = snprintf(p, len, "%02x ", buf[i]);
- p += nchar;
- len -= nchar;
- }
-
- if (i % 16 == 15) {
- printk(KERN_DEBUG "%s\n", line); /* flush line */
- p = line;
- len = sizeof(line);
- }
- }
-
- /* flush last partial line */
- if (p != line)
- printk(KERN_DEBUG "%s\n", line);
-}
-
char *bcm_chipname(uint chipid, char *buf, uint len)
{
const char *fmt;
@@ -943,6 +638,7 @@
snprintf(buf, len, fmt, chipid);
return buf;
}
+EXPORT_SYMBOL(bcm_chipname);
uint bcm_mkiovar(char *name, char *data, uint datalen, char *buf, uint buflen)
{
@@ -961,6 +657,7 @@
return len;
}
+EXPORT_SYMBOL(bcm_mkiovar);
/* Quarter dBm units to mW
* Table starts at QDBM_OFFSET, so the first entry is mW for qdBm=153
@@ -1015,6 +712,8 @@
*/
return (nqdBm_to_mW_map[idx] + factor / 2) / factor;
}
+EXPORT_SYMBOL(bcm_qdbm_to_mw);
+
u8 bcm_mw_to_qdbm(u16 mw)
{
u8 qdbm;
@@ -1045,6 +744,8 @@
return qdbm;
}
+EXPORT_SYMBOL(bcm_mw_to_qdbm);
+
uint bcm_bitcount(u8 *bitmap, uint length)
{
uint bitcount = 0, i;
@@ -1058,12 +759,15 @@
}
return bitcount;
}
+EXPORT_SYMBOL(bcm_bitcount);
+
/* Initialization of bcmstrbuf structure */
void bcm_binit(struct bcmstrbuf *b, char *buf, uint size)
{
b->origsize = b->size = size;
b->origbuf = b->buf = buf;
}
+EXPORT_SYMBOL(bcm_binit);
/* Buffer sprintf wrapper to guard against buffer overflow */
int bcm_bprintf(struct bcmstrbuf *b, const char *fmt, ...)
@@ -1089,50 +793,4 @@
return r;
}
-
-#if defined(BCMDBG_ASSERT)
-void osl_assert(char *exp, char *file, int line)
-{
- char tempbuf[256];
- char *basename;
-
- basename = strrchr(file, '/');
- /* skip the '/' */
- if (basename)
- basename++;
-
- if (!basename)
- basename = file;
-
- snprintf(tempbuf, 256,
- "assertion \"%s\" failed: file \"%s\", line %d\n", exp,
- basename, line);
-
- /*
- * Print assert message and give it time to
- * be written to /var/log/messages
- */
- if (!in_interrupt()) {
- const int delay = 3;
- printk(KERN_ERR "%s", tempbuf);
- printk(KERN_ERR "panic in %d seconds\n", delay);
- set_current_state(TASK_INTERRUPTIBLE);
- schedule_timeout(delay * HZ);
- }
-
- switch (g_assert_type) {
- case 0:
- panic(KERN_ERR "%s", tempbuf);
- break;
- case 1:
- printk(KERN_ERR "%s", tempbuf);
- BUG();
- break;
- case 2:
- printk(KERN_ERR "%s", tempbuf);
- break;
- default:
- break;
- }
-}
-#endif /* defined(BCMDBG_ASSERT) */
+EXPORT_SYMBOL(bcm_bprintf);
diff --git a/drivers/staging/brcm80211/util/bcmwifi.c b/drivers/staging/brcm80211/util/bcmwifi.c
index d82c2b2..955a3ab 100644
--- a/drivers/staging/brcm80211/util/bcmwifi.c
+++ b/drivers/staging/brcm80211/util/bcmwifi.c
@@ -15,6 +15,7 @@
*/
#include <linux/ctype.h>
#include <linux/kernel.h>
+#include <linux/module.h>
#include <bcmdefs.h>
#include <bcmutils.h>
#include <bcmwifi.h>
@@ -25,7 +26,7 @@
* combination could be legal given any set of circumstances.
* RETURNS: true is the chanspec is malformed, false if it looks good.
*/
-bool wf_chspec_malformed(chanspec_t chanspec)
+bool bcm_chspec_malformed(chanspec_t chanspec)
{
/* must be 2G or 5G band */
if (!CHSPEC_IS5G(chanspec) && !CHSPEC_IS2G(chanspec))
@@ -45,13 +46,14 @@
return false;
}
+EXPORT_SYMBOL(bcm_chspec_malformed);
/*
* This function returns the channel number that control traffic is being sent on, for legacy
* channels this is just the channel number, for 40MHZ channels it is the upper or lowre 20MHZ
* sideband depending on the chanspec selected
*/
-u8 wf_chspec_ctlchan(chanspec_t chspec)
+u8 bcm_chspec_ctlchan(chanspec_t chspec)
{
u8 ctl_chan;
@@ -60,7 +62,6 @@
return CHSPEC_CHANNEL(chspec);
} else {
/* we only support 40MHZ with sidebands */
- ASSERT(CHSPEC_BW(chspec) == WL_CHANSPEC_BW_40);
/* chanspec channel holds the centre frequency, use that and the
* side band information to reconstruct the control channel number
*/
@@ -68,8 +69,6 @@
/* control chan is the upper 20 MHZ SB of the 40MHZ channel */
ctl_chan = UPPER_20_SB(CHSPEC_CHANNEL(chspec));
} else {
- ASSERT(CHSPEC_CTL_SB(chspec) ==
- WL_CHANSPEC_CTL_SB_LOWER);
/* control chan is the lower 20 MHZ SB of the 40MHZ channel */
ctl_chan = LOWER_20_SB(CHSPEC_CHANNEL(chspec));
}
@@ -77,6 +76,7 @@
return ctl_chan;
}
+EXPORT_SYMBOL(bcm_chspec_ctlchan);
/*
* Return the channel number for a given frequency and base frequency.
@@ -97,7 +97,7 @@
*
* Reference 802.11 REVma, section 17.3.8.3, and 802.11B section 18.4.6.2
*/
-int wf_mhz2channel(uint freq, uint start_factor)
+int bcm_mhz2channel(uint freq, uint start_factor)
{
int ch = -1;
uint base;
@@ -133,4 +133,5 @@
return ch;
}
+EXPORT_SYMBOL(bcm_mhz2channel);
diff --git a/drivers/staging/brcm80211/util/hnddma.c b/drivers/staging/brcm80211/util/hnddma.c
deleted file mode 100644
index be339fe..0000000
--- a/drivers/staging/brcm80211/util/hnddma.c
+++ /dev/null
@@ -1,1822 +0,0 @@
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#include <linux/kernel.h>
-#include <linux/string.h>
-#include <linux/netdevice.h>
-#include <linux/pci.h>
-#include <bcmdefs.h>
-#include <bcmdevs.h>
-#include <hndsoc.h>
-#include <bcmutils.h>
-#include <siutils.h>
-
-#include <sbhnddma.h>
-#include <hnddma.h>
-
-#if defined(__mips__)
-#include <asm/addrspace.h>
-#endif
-
-#ifdef BRCM_FULLMAC
-#error "hnddma.c shouldn't be needed for FULLMAC"
-#endif
-
-/* debug/trace */
-#ifdef BCMDBG
-#define DMA_ERROR(args) \
- do { \
- if (!(*di->msg_level & 1)) \
- ; \
- else \
- printk args; \
- } while (0)
-#define DMA_TRACE(args) \
- do { \
- if (!(*di->msg_level & 2)) \
- ; \
- else \
- printk args; \
- } while (0)
-#else
-#define DMA_ERROR(args)
-#define DMA_TRACE(args)
-#endif /* BCMDBG */
-
-#define DMA_NONE(args)
-
-#define d64txregs dregs.d64_u.txregs_64
-#define d64rxregs dregs.d64_u.rxregs_64
-#define txd64 dregs.d64_u.txd_64
-#define rxd64 dregs.d64_u.rxd_64
-
-/* default dma message level (if input msg_level pointer is null in dma_attach()) */
-static uint dma_msg_level;
-
-#define MAXNAMEL 8 /* 8 char names */
-
-#define DI_INFO(dmah) ((dma_info_t *)dmah)
-
-#define R_SM(r) (*(r))
-#define W_SM(r, v) (*(r) = (v))
-
-/* dma engine software state */
-typedef struct dma_info {
- struct hnddma_pub hnddma; /* exported structure */
- uint *msg_level; /* message level pointer */
- char name[MAXNAMEL]; /* callers name for diag msgs */
-
- void *pbus; /* bus handle */
-
- bool dma64; /* this dma engine is operating in 64-bit mode */
- bool addrext; /* this dma engine supports DmaExtendedAddrChanges */
-
- union {
- struct {
- dma64regs_t *txregs_64; /* 64-bit dma tx engine registers */
- dma64regs_t *rxregs_64; /* 64-bit dma rx engine registers */
- dma64dd_t *txd_64; /* pointer to dma64 tx descriptor ring */
- dma64dd_t *rxd_64; /* pointer to dma64 rx descriptor ring */
- } d64_u;
- } dregs;
-
- u16 dmadesc_align; /* alignment requirement for dma descriptors */
-
- u16 ntxd; /* # tx descriptors tunable */
- u16 txin; /* index of next descriptor to reclaim */
- u16 txout; /* index of next descriptor to post */
- void **txp; /* pointer to parallel array of pointers to packets */
- hnddma_seg_map_t *txp_dmah; /* DMA MAP meta-data handle */
- dmaaddr_t txdpa; /* Aligned physical address of descriptor ring */
- dmaaddr_t txdpaorig; /* Original physical address of descriptor ring */
- u16 txdalign; /* #bytes added to alloc'd mem to align txd */
- u32 txdalloc; /* #bytes allocated for the ring */
- u32 xmtptrbase; /* When using unaligned descriptors, the ptr register
- * is not just an index, it needs all 13 bits to be
- * an offset from the addr register.
- */
-
- u16 nrxd; /* # rx descriptors tunable */
- u16 rxin; /* index of next descriptor to reclaim */
- u16 rxout; /* index of next descriptor to post */
- void **rxp; /* pointer to parallel array of pointers to packets */
- hnddma_seg_map_t *rxp_dmah; /* DMA MAP meta-data handle */
- dmaaddr_t rxdpa; /* Aligned physical address of descriptor ring */
- dmaaddr_t rxdpaorig; /* Original physical address of descriptor ring */
- u16 rxdalign; /* #bytes added to alloc'd mem to align rxd */
- u32 rxdalloc; /* #bytes allocated for the ring */
- u32 rcvptrbase; /* Base for ptr reg when using unaligned descriptors */
-
- /* tunables */
- unsigned int rxbufsize; /* rx buffer size in bytes,
- * not including the extra headroom
- */
- uint rxextrahdrroom; /* extra rx headroom, reverseved to assist upper stack
- * e.g. some rx pkt buffers will be bridged to tx side
- * without byte copying. The extra headroom needs to be
- * large enough to fit txheader needs.
- * Some dongle driver may not need it.
- */
- uint nrxpost; /* # rx buffers to keep posted */
- unsigned int rxoffset; /* rxcontrol offset */
- uint ddoffsetlow; /* add to get dma address of descriptor ring, low 32 bits */
- uint ddoffsethigh; /* high 32 bits */
- uint dataoffsetlow; /* add to get dma address of data buffer, low 32 bits */
- uint dataoffsethigh; /* high 32 bits */
- bool aligndesc_4k; /* descriptor base need to be aligned or not */
-} dma_info_t;
-
-/* DMA Scatter-gather list is supported. Note this is limited to TX direction only */
-#ifdef BCMDMASGLISTOSL
-#define DMASGLIST_ENAB true
-#else
-#define DMASGLIST_ENAB false
-#endif /* BCMDMASGLISTOSL */
-
-/* descriptor bumping macros */
-#define XXD(x, n) ((x) & ((n) - 1)) /* faster than %, but n must be power of 2 */
-#define TXD(x) XXD((x), di->ntxd)
-#define RXD(x) XXD((x), di->nrxd)
-#define NEXTTXD(i) TXD((i) + 1)
-#define PREVTXD(i) TXD((i) - 1)
-#define NEXTRXD(i) RXD((i) + 1)
-#define PREVRXD(i) RXD((i) - 1)
-
-#define NTXDACTIVE(h, t) TXD((t) - (h))
-#define NRXDACTIVE(h, t) RXD((t) - (h))
-
-/* macros to convert between byte offsets and indexes */
-#define B2I(bytes, type) ((bytes) / sizeof(type))
-#define I2B(index, type) ((index) * sizeof(type))
-
-#define PCI32ADDR_HIGH 0xc0000000 /* address[31:30] */
-#define PCI32ADDR_HIGH_SHIFT 30 /* address[31:30] */
-
-#define PCI64ADDR_HIGH 0x80000000 /* address[63] */
-#define PCI64ADDR_HIGH_SHIFT 31 /* address[63] */
-
-/* Common prototypes */
-static bool _dma_isaddrext(dma_info_t *di);
-static bool _dma_descriptor_align(dma_info_t *di);
-static bool _dma_alloc(dma_info_t *di, uint direction);
-static void _dma_detach(dma_info_t *di);
-static void _dma_ddtable_init(dma_info_t *di, uint direction, dmaaddr_t pa);
-static void _dma_rxinit(dma_info_t *di);
-static void *_dma_rx(dma_info_t *di);
-static bool _dma_rxfill(dma_info_t *di);
-static void _dma_rxreclaim(dma_info_t *di);
-static void _dma_rxenable(dma_info_t *di);
-static void *_dma_getnextrxp(dma_info_t *di, bool forceall);
-static void _dma_rx_param_get(dma_info_t *di, u16 *rxoffset,
- u16 *rxbufsize);
-
-static void _dma_txblock(dma_info_t *di);
-static void _dma_txunblock(dma_info_t *di);
-static uint _dma_txactive(dma_info_t *di);
-static uint _dma_rxactive(dma_info_t *di);
-static uint _dma_txpending(dma_info_t *di);
-static uint _dma_txcommitted(dma_info_t *di);
-
-static void *_dma_peeknexttxp(dma_info_t *di);
-static void *_dma_peeknextrxp(dma_info_t *di);
-static unsigned long _dma_getvar(dma_info_t *di, const char *name);
-static void _dma_counterreset(dma_info_t *di);
-static void _dma_fifoloopbackenable(dma_info_t *di);
-static uint _dma_ctrlflags(dma_info_t *di, uint mask, uint flags);
-static u8 dma_align_sizetobits(uint size);
-static void *dma_ringalloc(dma_info_t *di, u32 boundary, uint size,
- u16 *alignbits, uint *alloced,
- dmaaddr_t *descpa);
-
-/* Prototypes for 64-bit routines */
-static bool dma64_alloc(dma_info_t *di, uint direction);
-static bool dma64_txreset(dma_info_t *di);
-static bool dma64_rxreset(dma_info_t *di);
-static bool dma64_txsuspendedidle(dma_info_t *di);
-static int dma64_txfast(dma_info_t *di, struct sk_buff *p0, bool commit);
-static int dma64_txunframed(dma_info_t *di, void *p0, uint len, bool commit);
-static void *dma64_getpos(dma_info_t *di, bool direction);
-static void *dma64_getnexttxp(dma_info_t *di, txd_range_t range);
-static void *dma64_getnextrxp(dma_info_t *di, bool forceall);
-static void dma64_txrotate(dma_info_t *di);
-
-static bool dma64_rxidle(dma_info_t *di);
-static void dma64_txinit(dma_info_t *di);
-static bool dma64_txenabled(dma_info_t *di);
-static void dma64_txsuspend(dma_info_t *di);
-static void dma64_txresume(dma_info_t *di);
-static bool dma64_txsuspended(dma_info_t *di);
-static void dma64_txreclaim(dma_info_t *di, txd_range_t range);
-static bool dma64_txstopped(dma_info_t *di);
-static bool dma64_rxstopped(dma_info_t *di);
-static bool dma64_rxenabled(dma_info_t *di);
-static bool _dma64_addrext(dma64regs_t *dma64regs);
-
-static inline u32 parity32(u32 data);
-
-const di_fcn_t dma64proc = {
- (di_detach_t) _dma_detach,
- (di_txinit_t) dma64_txinit,
- (di_txreset_t) dma64_txreset,
- (di_txenabled_t) dma64_txenabled,
- (di_txsuspend_t) dma64_txsuspend,
- (di_txresume_t) dma64_txresume,
- (di_txsuspended_t) dma64_txsuspended,
- (di_txsuspendedidle_t) dma64_txsuspendedidle,
- (di_txfast_t) dma64_txfast,
- (di_txunframed_t) dma64_txunframed,
- (di_getpos_t) dma64_getpos,
- (di_txstopped_t) dma64_txstopped,
- (di_txreclaim_t) dma64_txreclaim,
- (di_getnexttxp_t) dma64_getnexttxp,
- (di_peeknexttxp_t) _dma_peeknexttxp,
- (di_txblock_t) _dma_txblock,
- (di_txunblock_t) _dma_txunblock,
- (di_txactive_t) _dma_txactive,
- (di_txrotate_t) dma64_txrotate,
-
- (di_rxinit_t) _dma_rxinit,
- (di_rxreset_t) dma64_rxreset,
- (di_rxidle_t) dma64_rxidle,
- (di_rxstopped_t) dma64_rxstopped,
- (di_rxenable_t) _dma_rxenable,
- (di_rxenabled_t) dma64_rxenabled,
- (di_rx_t) _dma_rx,
- (di_rxfill_t) _dma_rxfill,
- (di_rxreclaim_t) _dma_rxreclaim,
- (di_getnextrxp_t) _dma_getnextrxp,
- (di_peeknextrxp_t) _dma_peeknextrxp,
- (di_rxparam_get_t) _dma_rx_param_get,
-
- (di_fifoloopbackenable_t) _dma_fifoloopbackenable,
- (di_getvar_t) _dma_getvar,
- (di_counterreset_t) _dma_counterreset,
- (di_ctrlflags_t) _dma_ctrlflags,
- NULL,
- NULL,
- NULL,
- (di_rxactive_t) _dma_rxactive,
- (di_txpending_t) _dma_txpending,
- (di_txcommitted_t) _dma_txcommitted,
- 39
-};
-
-struct hnddma_pub *dma_attach(char *name, si_t *sih,
- void *dmaregstx, void *dmaregsrx, uint ntxd,
- uint nrxd, uint rxbufsize, int rxextheadroom,
- uint nrxpost, uint rxoffset, uint *msg_level)
-{
- dma_info_t *di;
- uint size;
-
- /* allocate private info structure */
- di = kzalloc(sizeof(dma_info_t), GFP_ATOMIC);
- if (di == NULL) {
-#ifdef BCMDBG
- printk(KERN_ERR "dma_attach: out of memory\n");
-#endif
- return NULL;
- }
-
- di->msg_level = msg_level ? msg_level : &dma_msg_level;
-
- /* old chips w/o sb is no longer supported */
- ASSERT(sih != NULL);
-
- di->dma64 = ((si_core_sflags(sih, 0, 0) & SISF_DMA64) == SISF_DMA64);
-
- /* check arguments */
- ASSERT(ISPOWEROF2(ntxd));
- ASSERT(ISPOWEROF2(nrxd));
-
- if (nrxd == 0)
- ASSERT(dmaregsrx == NULL);
- if (ntxd == 0)
- ASSERT(dmaregstx == NULL);
-
- /* init dma reg pointer */
- ASSERT(ntxd <= D64MAXDD);
- ASSERT(nrxd <= D64MAXDD);
- di->d64txregs = (dma64regs_t *) dmaregstx;
- di->d64rxregs = (dma64regs_t *) dmaregsrx;
- di->hnddma.di_fn = (const di_fcn_t *)&dma64proc;
-
- /* Default flags (which can be changed by the driver calling dma_ctrlflags
- * before enable): For backwards compatibility both Rx Overflow Continue
- * and Parity are DISABLED.
- * supports it.
- */
- di->hnddma.di_fn->ctrlflags(&di->hnddma, DMA_CTRL_ROC | DMA_CTRL_PEN,
- 0);
-
- DMA_TRACE(("%s: dma_attach: %s flags 0x%x ntxd %d nrxd %d "
- "rxbufsize %d rxextheadroom %d nrxpost %d rxoffset %d "
- "dmaregstx %p dmaregsrx %p\n", name, "DMA64",
- di->hnddma.dmactrlflags, ntxd, nrxd, rxbufsize,
- rxextheadroom, nrxpost, rxoffset, dmaregstx, dmaregsrx));
-
- /* make a private copy of our callers name */
- strncpy(di->name, name, MAXNAMEL);
- di->name[MAXNAMEL - 1] = '\0';
-
- di->pbus = ((struct si_info *)sih)->pbus;
-
- /* save tunables */
- di->ntxd = (u16) ntxd;
- di->nrxd = (u16) nrxd;
-
- /* the actual dma size doesn't include the extra headroom */
- di->rxextrahdrroom =
- (rxextheadroom == -1) ? BCMEXTRAHDROOM : rxextheadroom;
- if (rxbufsize > BCMEXTRAHDROOM)
- di->rxbufsize = (u16) (rxbufsize - di->rxextrahdrroom);
- else
- di->rxbufsize = (u16) rxbufsize;
-
- di->nrxpost = (u16) nrxpost;
- di->rxoffset = (u8) rxoffset;
-
- /*
- * figure out the DMA physical address offset for dd and data
- * PCI/PCIE: they map silicon backplace address to zero based memory, need offset
- * Other bus: use zero
- * SI_BUS BIGENDIAN kludge: use sdram swapped region for data buffer, not descriptor
- */
- di->ddoffsetlow = 0;
- di->dataoffsetlow = 0;
- /* for pci bus, add offset */
- if (sih->bustype == PCI_BUS) {
- /* pcie with DMA64 */
- di->ddoffsetlow = 0;
- di->ddoffsethigh = SI_PCIE_DMA_H32;
- di->dataoffsetlow = di->ddoffsetlow;
- di->dataoffsethigh = di->ddoffsethigh;
- }
-#if defined(__mips__) && defined(IL_BIGENDIAN)
- di->dataoffsetlow = di->dataoffsetlow + SI_SDRAM_SWAPPED;
-#endif /* defined(__mips__) && defined(IL_BIGENDIAN) */
- /* WAR64450 : DMACtl.Addr ext fields are not supported in SDIOD core. */
- if ((si_coreid(sih) == SDIOD_CORE_ID)
- && ((si_corerev(sih) > 0) && (si_corerev(sih) <= 2)))
- di->addrext = 0;
- else if ((si_coreid(sih) == I2S_CORE_ID) &&
- ((si_corerev(sih) == 0) || (si_corerev(sih) == 1)))
- di->addrext = 0;
- else
- di->addrext = _dma_isaddrext(di);
-
- /* does the descriptors need to be aligned and if yes, on 4K/8K or not */
- di->aligndesc_4k = _dma_descriptor_align(di);
- if (di->aligndesc_4k) {
- di->dmadesc_align = D64RINGALIGN_BITS;
- if ((ntxd < D64MAXDD / 2) && (nrxd < D64MAXDD / 2)) {
- /* for smaller dd table, HW relax alignment reqmnt */
- di->dmadesc_align = D64RINGALIGN_BITS - 1;
- }
- } else
- di->dmadesc_align = 4; /* 16 byte alignment */
-
- DMA_NONE(("DMA descriptor align_needed %d, align %d\n",
- di->aligndesc_4k, di->dmadesc_align));
-
- /* allocate tx packet pointer vector */
- if (ntxd) {
- size = ntxd * sizeof(void *);
- di->txp = kzalloc(size, GFP_ATOMIC);
- if (di->txp == NULL) {
- DMA_ERROR(("%s: dma_attach: out of tx memory\n", di->name));
- goto fail;
- }
- }
-
- /* allocate rx packet pointer vector */
- if (nrxd) {
- size = nrxd * sizeof(void *);
- di->rxp = kzalloc(size, GFP_ATOMIC);
- if (di->rxp == NULL) {
- DMA_ERROR(("%s: dma_attach: out of rx memory\n", di->name));
- goto fail;
- }
- }
-
- /* allocate transmit descriptor ring, only need ntxd descriptors but it must be aligned */
- if (ntxd) {
- if (!_dma_alloc(di, DMA_TX))
- goto fail;
- }
-
- /* allocate receive descriptor ring, only need nrxd descriptors but it must be aligned */
- if (nrxd) {
- if (!_dma_alloc(di, DMA_RX))
- goto fail;
- }
-
- if ((di->ddoffsetlow != 0) && !di->addrext) {
- if (PHYSADDRLO(di->txdpa) > SI_PCI_DMA_SZ) {
- DMA_ERROR(("%s: dma_attach: txdpa 0x%x: addrext not supported\n", di->name, (u32) PHYSADDRLO(di->txdpa)));
- goto fail;
- }
- if (PHYSADDRLO(di->rxdpa) > SI_PCI_DMA_SZ) {
- DMA_ERROR(("%s: dma_attach: rxdpa 0x%x: addrext not supported\n", di->name, (u32) PHYSADDRLO(di->rxdpa)));
- goto fail;
- }
- }
-
- DMA_TRACE(("ddoffsetlow 0x%x ddoffsethigh 0x%x dataoffsetlow 0x%x dataoffsethigh " "0x%x addrext %d\n", di->ddoffsetlow, di->ddoffsethigh, di->dataoffsetlow, di->dataoffsethigh, di->addrext));
-
- /* allocate DMA mapping vectors */
- if (DMASGLIST_ENAB) {
- if (ntxd) {
- size = ntxd * sizeof(hnddma_seg_map_t);
- di->txp_dmah = kzalloc(size, GFP_ATOMIC);
- if (di->txp_dmah == NULL)
- goto fail;
- }
-
- if (nrxd) {
- size = nrxd * sizeof(hnddma_seg_map_t);
- di->rxp_dmah = kzalloc(size, GFP_ATOMIC);
- if (di->rxp_dmah == NULL)
- goto fail;
- }
- }
-
- return (struct hnddma_pub *) di;
-
- fail:
- _dma_detach(di);
- return NULL;
-}
-
-/* Check for odd number of 1's */
-static inline u32 parity32(u32 data)
-{
- data ^= data >> 16;
- data ^= data >> 8;
- data ^= data >> 4;
- data ^= data >> 2;
- data ^= data >> 1;
-
- return data & 1;
-}
-
-#define DMA64_DD_PARITY(dd) parity32((dd)->addrlow ^ (dd)->addrhigh ^ (dd)->ctrl1 ^ (dd)->ctrl2)
-
-static inline void
-dma64_dd_upd(dma_info_t *di, dma64dd_t *ddring, dmaaddr_t pa, uint outidx,
- u32 *flags, u32 bufcount)
-{
- u32 ctrl2 = bufcount & D64_CTRL2_BC_MASK;
-
- /* PCI bus with big(>1G) physical address, use address extension */
-#if defined(__mips__) && defined(IL_BIGENDIAN)
- if ((di->dataoffsetlow == SI_SDRAM_SWAPPED)
- || !(PHYSADDRLO(pa) & PCI32ADDR_HIGH)) {
-#else
- if ((di->dataoffsetlow == 0) || !(PHYSADDRLO(pa) & PCI32ADDR_HIGH)) {
-#endif /* defined(__mips__) && defined(IL_BIGENDIAN) */
- ASSERT((PHYSADDRHI(pa) & PCI64ADDR_HIGH) == 0);
-
- W_SM(&ddring[outidx].addrlow,
- BUS_SWAP32(PHYSADDRLO(pa) + di->dataoffsetlow));
- W_SM(&ddring[outidx].addrhigh,
- BUS_SWAP32(PHYSADDRHI(pa) + di->dataoffsethigh));
- W_SM(&ddring[outidx].ctrl1, BUS_SWAP32(*flags));
- W_SM(&ddring[outidx].ctrl2, BUS_SWAP32(ctrl2));
- } else {
- /* address extension for 32-bit PCI */
- u32 ae;
- ASSERT(di->addrext);
-
- ae = (PHYSADDRLO(pa) & PCI32ADDR_HIGH) >> PCI32ADDR_HIGH_SHIFT;
- PHYSADDRLO(pa) &= ~PCI32ADDR_HIGH;
- ASSERT(PHYSADDRHI(pa) == 0);
-
- ctrl2 |= (ae << D64_CTRL2_AE_SHIFT) & D64_CTRL2_AE;
- W_SM(&ddring[outidx].addrlow,
- BUS_SWAP32(PHYSADDRLO(pa) + di->dataoffsetlow));
- W_SM(&ddring[outidx].addrhigh,
- BUS_SWAP32(0 + di->dataoffsethigh));
- W_SM(&ddring[outidx].ctrl1, BUS_SWAP32(*flags));
- W_SM(&ddring[outidx].ctrl2, BUS_SWAP32(ctrl2));
- }
- if (di->hnddma.dmactrlflags & DMA_CTRL_PEN) {
- if (DMA64_DD_PARITY(&ddring[outidx])) {
- W_SM(&ddring[outidx].ctrl2,
- BUS_SWAP32(ctrl2 | D64_CTRL2_PARITY));
- }
- }
-}
-
-static bool _dma_alloc(dma_info_t *di, uint direction)
-{
- return dma64_alloc(di, direction);
-}
-
-void *dma_alloc_consistent(struct pci_dev *pdev, uint size, u16 align_bits,
- uint *alloced, unsigned long *pap)
-{
- if (align_bits) {
- u16 align = (1 << align_bits);
- if (!IS_ALIGNED(PAGE_SIZE, align))
- size += align;
- *alloced = size;
- }
- return pci_alloc_consistent(pdev, size, (dma_addr_t *) pap);
-}
-
-/* !! may be called with core in reset */
-static void _dma_detach(dma_info_t *di)
-{
-
- DMA_TRACE(("%s: dma_detach\n", di->name));
-
- /* shouldn't be here if descriptors are unreclaimed */
- ASSERT(di->txin == di->txout);
- ASSERT(di->rxin == di->rxout);
-
- /* free dma descriptor rings */
- if (di->txd64)
- pci_free_consistent(di->pbus, di->txdalloc,
- ((s8 *)di->txd64 - di->txdalign),
- (di->txdpaorig));
- if (di->rxd64)
- pci_free_consistent(di->pbus, di->rxdalloc,
- ((s8 *)di->rxd64 - di->rxdalign),
- (di->rxdpaorig));
-
- /* free packet pointer vectors */
- kfree(di->txp);
- kfree(di->rxp);
-
- /* free tx packet DMA handles */
- kfree(di->txp_dmah);
-
- /* free rx packet DMA handles */
- kfree(di->rxp_dmah);
-
- /* free our private info structure */
- kfree(di);
-
-}
-
-static bool _dma_descriptor_align(dma_info_t *di)
-{
- u32 addrl;
-
- /* Check to see if the descriptors need to be aligned on 4K/8K or not */
- if (di->d64txregs != NULL) {
- W_REG(&di->d64txregs->addrlow, 0xff0);
- addrl = R_REG(&di->d64txregs->addrlow);
- if (addrl != 0)
- return false;
- } else if (di->d64rxregs != NULL) {
- W_REG(&di->d64rxregs->addrlow, 0xff0);
- addrl = R_REG(&di->d64rxregs->addrlow);
- if (addrl != 0)
- return false;
- }
- return true;
-}
-
-/* return true if this dma engine supports DmaExtendedAddrChanges, otherwise false */
-static bool _dma_isaddrext(dma_info_t *di)
-{
- /* DMA64 supports full 32- or 64-bit operation. AE is always valid */
-
- /* not all tx or rx channel are available */
- if (di->d64txregs != NULL) {
- if (!_dma64_addrext(di->d64txregs)) {
- DMA_ERROR(("%s: _dma_isaddrext: DMA64 tx doesn't have "
- "AE set\n", di->name));
- ASSERT(0);
- }
- return true;
- } else if (di->d64rxregs != NULL) {
- if (!_dma64_addrext(di->d64rxregs)) {
- DMA_ERROR(("%s: _dma_isaddrext: DMA64 rx doesn't have "
- "AE set\n", di->name));
- ASSERT(0);
- }
- return true;
- }
- return false;
-}
-
-/* initialize descriptor table base address */
-static void _dma_ddtable_init(dma_info_t *di, uint direction, dmaaddr_t pa)
-{
- if (!di->aligndesc_4k) {
- if (direction == DMA_TX)
- di->xmtptrbase = PHYSADDRLO(pa);
- else
- di->rcvptrbase = PHYSADDRLO(pa);
- }
-
- if ((di->ddoffsetlow == 0)
- || !(PHYSADDRLO(pa) & PCI32ADDR_HIGH)) {
- if (direction == DMA_TX) {
- W_REG(&di->d64txregs->addrlow,
- (PHYSADDRLO(pa) + di->ddoffsetlow));
- W_REG(&di->d64txregs->addrhigh,
- (PHYSADDRHI(pa) + di->ddoffsethigh));
- } else {
- W_REG(&di->d64rxregs->addrlow,
- (PHYSADDRLO(pa) + di->ddoffsetlow));
- W_REG(&di->d64rxregs->addrhigh,
- (PHYSADDRHI(pa) + di->ddoffsethigh));
- }
- } else {
- /* DMA64 32bits address extension */
- u32 ae;
- ASSERT(di->addrext);
- ASSERT(PHYSADDRHI(pa) == 0);
-
- /* shift the high bit(s) from pa to ae */
- ae = (PHYSADDRLO(pa) & PCI32ADDR_HIGH) >>
- PCI32ADDR_HIGH_SHIFT;
- PHYSADDRLO(pa) &= ~PCI32ADDR_HIGH;
-
- if (direction == DMA_TX) {
- W_REG(&di->d64txregs->addrlow,
- (PHYSADDRLO(pa) + di->ddoffsetlow));
- W_REG(&di->d64txregs->addrhigh,
- di->ddoffsethigh);
- SET_REG(&di->d64txregs->control,
- D64_XC_AE, (ae << D64_XC_AE_SHIFT));
- } else {
- W_REG(&di->d64rxregs->addrlow,
- (PHYSADDRLO(pa) + di->ddoffsetlow));
- W_REG(&di->d64rxregs->addrhigh,
- di->ddoffsethigh);
- SET_REG(&di->d64rxregs->control,
- D64_RC_AE, (ae << D64_RC_AE_SHIFT));
- }
- }
-}
-
-static void _dma_fifoloopbackenable(dma_info_t *di)
-{
- DMA_TRACE(("%s: dma_fifoloopbackenable\n", di->name));
-
- OR_REG(&di->d64txregs->control, D64_XC_LE);
-}
-
-static void _dma_rxinit(dma_info_t *di)
-{
- DMA_TRACE(("%s: dma_rxinit\n", di->name));
-
- if (di->nrxd == 0)
- return;
-
- di->rxin = di->rxout = 0;
-
- /* clear rx descriptor ring */
- memset((void *)di->rxd64, '\0',
- (di->nrxd * sizeof(dma64dd_t)));
-
- /* DMA engine with out alignment requirement requires table to be inited
- * before enabling the engine
- */
- if (!di->aligndesc_4k)
- _dma_ddtable_init(di, DMA_RX, di->rxdpa);
-
- _dma_rxenable(di);
-
- if (di->aligndesc_4k)
- _dma_ddtable_init(di, DMA_RX, di->rxdpa);
-}
-
-static void _dma_rxenable(dma_info_t *di)
-{
- uint dmactrlflags = di->hnddma.dmactrlflags;
- u32 control;
-
- DMA_TRACE(("%s: dma_rxenable\n", di->name));
-
- control =
- (R_REG(&di->d64rxregs->control) & D64_RC_AE) |
- D64_RC_RE;
-
- if ((dmactrlflags & DMA_CTRL_PEN) == 0)
- control |= D64_RC_PD;
-
- if (dmactrlflags & DMA_CTRL_ROC)
- control |= D64_RC_OC;
-
- W_REG(&di->d64rxregs->control,
- ((di->rxoffset << D64_RC_RO_SHIFT) | control));
-}
-
-static void
-_dma_rx_param_get(dma_info_t *di, u16 *rxoffset, u16 *rxbufsize)
-{
- /* the normal values fit into 16 bits */
- *rxoffset = (u16) di->rxoffset;
- *rxbufsize = (u16) di->rxbufsize;
-}
-
-/* !! rx entry routine
- * returns a pointer to the next frame received, or NULL if there are no more
- * if DMA_CTRL_RXMULTI is defined, DMA scattering(multiple buffers) is supported
- * with pkts chain
- * otherwise, it's treated as giant pkt and will be tossed.
- * The DMA scattering starts with normal DMA header, followed by first buffer data.
- * After it reaches the max size of buffer, the data continues in next DMA descriptor
- * buffer WITHOUT DMA header
- */
-static void *BCMFASTPATH _dma_rx(dma_info_t *di)
-{
- struct sk_buff *p, *head, *tail;
- uint len;
- uint pkt_len;
- int resid = 0;
-
- next_frame:
- head = _dma_getnextrxp(di, false);
- if (head == NULL)
- return NULL;
-
- len = le16_to_cpu(*(u16 *) (head->data));
- DMA_TRACE(("%s: dma_rx len %d\n", di->name, len));
-
-#if defined(__mips__)
-#define OSL_UNCACHED(va) ((void *)KSEG1ADDR((va)))
- if (!len) {
- while (!(len = *(u16 *) OSL_UNCACHED(head->data)))
- udelay(1);
-
- *(u16 *) (head->data) = cpu_to_le16((u16) len);
- }
-#endif /* defined(__mips__) */
-
- /* set actual length */
- pkt_len = min((di->rxoffset + len), di->rxbufsize);
- __skb_trim(head, pkt_len);
- resid = len - (di->rxbufsize - di->rxoffset);
-
- /* check for single or multi-buffer rx */
- if (resid > 0) {
- tail = head;
- while ((resid > 0) && (p = _dma_getnextrxp(di, false))) {
- tail->next = p;
- pkt_len = min(resid, (int)di->rxbufsize);
- __skb_trim(p, pkt_len);
-
- tail = p;
- resid -= di->rxbufsize;
- }
-
-#ifdef BCMDBG
- if (resid > 0) {
- uint cur;
- ASSERT(p == NULL);
- cur =
- B2I(((R_REG(&di->d64rxregs->status0) &
- D64_RS0_CD_MASK) -
- di->rcvptrbase) & D64_RS0_CD_MASK,
- dma64dd_t);
- DMA_ERROR(("_dma_rx, rxin %d rxout %d, hw_curr %d\n",
- di->rxin, di->rxout, cur));
- }
-#endif /* BCMDBG */
-
- if ((di->hnddma.dmactrlflags & DMA_CTRL_RXMULTI) == 0) {
- DMA_ERROR(("%s: dma_rx: bad frame length (%d)\n",
- di->name, len));
- pkt_buf_free_skb(head);
- di->hnddma.rxgiants++;
- goto next_frame;
- }
- }
-
- return head;
-}
-
-/* post receive buffers
- * return false is refill failed completely and ring is empty
- * this will stall the rx dma and user might want to call rxfill again asap
- * This unlikely happens on memory-rich NIC, but often on memory-constrained dongle
- */
-static bool BCMFASTPATH _dma_rxfill(dma_info_t *di)
-{
- struct sk_buff *p;
- u16 rxin, rxout;
- u32 flags = 0;
- uint n;
- uint i;
- dmaaddr_t pa;
- uint extra_offset = 0;
- bool ring_empty;
-
- ring_empty = false;
-
- /*
- * Determine how many receive buffers we're lacking
- * from the full complement, allocate, initialize,
- * and post them, then update the chip rx lastdscr.
- */
-
- rxin = di->rxin;
- rxout = di->rxout;
-
- n = di->nrxpost - NRXDACTIVE(rxin, rxout);
-
- DMA_TRACE(("%s: dma_rxfill: post %d\n", di->name, n));
-
- if (di->rxbufsize > BCMEXTRAHDROOM)
- extra_offset = di->rxextrahdrroom;
-
- for (i = 0; i < n; i++) {
- /* the di->rxbufsize doesn't include the extra headroom, we need to add it to the
- size to be allocated
- */
-
- p = pkt_buf_get_skb(di->rxbufsize + extra_offset);
-
- if (p == NULL) {
- DMA_ERROR(("%s: dma_rxfill: out of rxbufs\n",
- di->name));
- if (i == 0 && dma64_rxidle(di)) {
- DMA_ERROR(("%s: rxfill64: ring is empty !\n",
- di->name));
- ring_empty = true;
- }
- di->hnddma.rxnobuf++;
- break;
- }
- /* reserve an extra headroom, if applicable */
- if (extra_offset)
- skb_pull(p, extra_offset);
-
- /* Do a cached write instead of uncached write since DMA_MAP
- * will flush the cache.
- */
- *(u32 *) (p->data) = 0;
-
- if (DMASGLIST_ENAB)
- memset(&di->rxp_dmah[rxout], 0,
- sizeof(hnddma_seg_map_t));
-
- pa = pci_map_single(di->pbus, p->data,
- di->rxbufsize, PCI_DMA_FROMDEVICE);
-
- ASSERT(IS_ALIGNED(PHYSADDRLO(pa), 4));
-
- /* save the free packet pointer */
- ASSERT(di->rxp[rxout] == NULL);
- di->rxp[rxout] = p;
-
- /* reset flags for each descriptor */
- flags = 0;
- if (rxout == (di->nrxd - 1))
- flags = D64_CTRL1_EOT;
-
- dma64_dd_upd(di, di->rxd64, pa, rxout, &flags,
- di->rxbufsize);
- rxout = NEXTRXD(rxout);
- }
-
- di->rxout = rxout;
-
- /* update the chip lastdscr pointer */
- W_REG(&di->d64rxregs->ptr,
- di->rcvptrbase + I2B(rxout, dma64dd_t));
-
- return ring_empty;
-}
-
-/* like getnexttxp but no reclaim */
-static void *_dma_peeknexttxp(dma_info_t *di)
-{
- uint end, i;
-
- if (di->ntxd == 0)
- return NULL;
-
- end =
- B2I(((R_REG(&di->d64txregs->status0) &
- D64_XS0_CD_MASK) - di->xmtptrbase) & D64_XS0_CD_MASK,
- dma64dd_t);
-
- for (i = di->txin; i != end; i = NEXTTXD(i))
- if (di->txp[i])
- return di->txp[i];
-
- return NULL;
-}
-
-/* like getnextrxp but not take off the ring */
-static void *_dma_peeknextrxp(dma_info_t *di)
-{
- uint end, i;
-
- if (di->nrxd == 0)
- return NULL;
-
- end =
- B2I(((R_REG(&di->d64rxregs->status0) &
- D64_RS0_CD_MASK) - di->rcvptrbase) & D64_RS0_CD_MASK,
- dma64dd_t);
-
- for (i = di->rxin; i != end; i = NEXTRXD(i))
- if (di->rxp[i])
- return di->rxp[i];
-
- return NULL;
-}
-
-static void _dma_rxreclaim(dma_info_t *di)
-{
- void *p;
-
- DMA_TRACE(("%s: dma_rxreclaim\n", di->name));
-
- while ((p = _dma_getnextrxp(di, true)))
- pkt_buf_free_skb(p);
-}
-
-static void *BCMFASTPATH _dma_getnextrxp(dma_info_t *di, bool forceall)
-{
- if (di->nrxd == 0)
- return NULL;
-
- return dma64_getnextrxp(di, forceall);
-}
-
-static void _dma_txblock(dma_info_t *di)
-{
- di->hnddma.txavail = 0;
-}
-
-static void _dma_txunblock(dma_info_t *di)
-{
- di->hnddma.txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
-}
-
-static uint _dma_txactive(dma_info_t *di)
-{
- return NTXDACTIVE(di->txin, di->txout);
-}
-
-static uint _dma_txpending(dma_info_t *di)
-{
- uint curr;
-
- curr =
- B2I(((R_REG(&di->d64txregs->status0) &
- D64_XS0_CD_MASK) - di->xmtptrbase) & D64_XS0_CD_MASK,
- dma64dd_t);
-
- return NTXDACTIVE(curr, di->txout);
-}
-
-static uint _dma_txcommitted(dma_info_t *di)
-{
- uint ptr;
- uint txin = di->txin;
-
- if (txin == di->txout)
- return 0;
-
- ptr = B2I(R_REG(&di->d64txregs->ptr), dma64dd_t);
-
- return NTXDACTIVE(di->txin, ptr);
-}
-
-static uint _dma_rxactive(dma_info_t *di)
-{
- return NRXDACTIVE(di->rxin, di->rxout);
-}
-
-static void _dma_counterreset(dma_info_t *di)
-{
- /* reset all software counter */
- di->hnddma.rxgiants = 0;
- di->hnddma.rxnobuf = 0;
- di->hnddma.txnobuf = 0;
-}
-
-static uint _dma_ctrlflags(dma_info_t *di, uint mask, uint flags)
-{
- uint dmactrlflags = di->hnddma.dmactrlflags;
-
- if (di == NULL) {
- DMA_ERROR(("%s: _dma_ctrlflags: NULL dma handle\n", di->name));
- return 0;
- }
-
- ASSERT((flags & ~mask) == 0);
-
- dmactrlflags &= ~mask;
- dmactrlflags |= flags;
-
- /* If trying to enable parity, check if parity is actually supported */
- if (dmactrlflags & DMA_CTRL_PEN) {
- u32 control;
-
- control = R_REG(&di->d64txregs->control);
- W_REG(&di->d64txregs->control,
- control | D64_XC_PD);
- if (R_REG(&di->d64txregs->control) & D64_XC_PD) {
- /* We *can* disable it so it is supported,
- * restore control register
- */
- W_REG(&di->d64txregs->control,
- control);
- } else {
- /* Not supported, don't allow it to be enabled */
- dmactrlflags &= ~DMA_CTRL_PEN;
- }
- }
-
- di->hnddma.dmactrlflags = dmactrlflags;
-
- return dmactrlflags;
-}
-
-/* get the address of the var in order to change later */
-static unsigned long _dma_getvar(dma_info_t *di, const char *name)
-{
- if (!strcmp(name, "&txavail"))
- return (unsigned long)&(di->hnddma.txavail);
- else {
- ASSERT(0);
- }
- return 0;
-}
-
-static
-u8 dma_align_sizetobits(uint size)
-{
- u8 bitpos = 0;
- ASSERT(size);
- ASSERT(!(size & (size - 1)));
- while (size >>= 1) {
- bitpos++;
- }
- return bitpos;
-}
-
-/* This function ensures that the DMA descriptor ring will not get allocated
- * across Page boundary. If the allocation is done across the page boundary
- * at the first time, then it is freed and the allocation is done at
- * descriptor ring size aligned location. This will ensure that the ring will
- * not cross page boundary
- */
-static void *dma_ringalloc(dma_info_t *di, u32 boundary, uint size,
- u16 *alignbits, uint *alloced,
- dmaaddr_t *descpa)
-{
- void *va;
- u32 desc_strtaddr;
- u32 alignbytes = 1 << *alignbits;
-
- va = dma_alloc_consistent(di->pbus, size, *alignbits, alloced, descpa);
-
- if (NULL == va)
- return NULL;
-
- desc_strtaddr = (u32) roundup((unsigned long)va, alignbytes);
- if (((desc_strtaddr + size - 1) & boundary) != (desc_strtaddr
- & boundary)) {
- *alignbits = dma_align_sizetobits(size);
- pci_free_consistent(di->pbus, size, va, *descpa);
- va = dma_alloc_consistent(di->pbus, size, *alignbits,
- alloced, descpa);
- }
- return va;
-}
-
-/* 64-bit DMA functions */
-
-static void dma64_txinit(dma_info_t *di)
-{
- u32 control = D64_XC_XE;
-
- DMA_TRACE(("%s: dma_txinit\n", di->name));
-
- if (di->ntxd == 0)
- return;
-
- di->txin = di->txout = 0;
- di->hnddma.txavail = di->ntxd - 1;
-
- /* clear tx descriptor ring */
- memset((void *)di->txd64, '\0', (di->ntxd * sizeof(dma64dd_t)));
-
- /* DMA engine with out alignment requirement requires table to be inited
- * before enabling the engine
- */
- if (!di->aligndesc_4k)
- _dma_ddtable_init(di, DMA_TX, di->txdpa);
-
- if ((di->hnddma.dmactrlflags & DMA_CTRL_PEN) == 0)
- control |= D64_XC_PD;
- OR_REG(&di->d64txregs->control, control);
-
- /* DMA engine with alignment requirement requires table to be inited
- * before enabling the engine
- */
- if (di->aligndesc_4k)
- _dma_ddtable_init(di, DMA_TX, di->txdpa);
-}
-
-static bool dma64_txenabled(dma_info_t *di)
-{
- u32 xc;
-
- /* If the chip is dead, it is not enabled :-) */
- xc = R_REG(&di->d64txregs->control);
- return (xc != 0xffffffff) && (xc & D64_XC_XE);
-}
-
-static void dma64_txsuspend(dma_info_t *di)
-{
- DMA_TRACE(("%s: dma_txsuspend\n", di->name));
-
- if (di->ntxd == 0)
- return;
-
- OR_REG(&di->d64txregs->control, D64_XC_SE);
-}
-
-static void dma64_txresume(dma_info_t *di)
-{
- DMA_TRACE(("%s: dma_txresume\n", di->name));
-
- if (di->ntxd == 0)
- return;
-
- AND_REG(&di->d64txregs->control, ~D64_XC_SE);
-}
-
-static bool dma64_txsuspended(dma_info_t *di)
-{
- return (di->ntxd == 0) ||
- ((R_REG(&di->d64txregs->control) & D64_XC_SE) ==
- D64_XC_SE);
-}
-
-static void BCMFASTPATH dma64_txreclaim(dma_info_t *di, txd_range_t range)
-{
- void *p;
-
- DMA_TRACE(("%s: dma_txreclaim %s\n", di->name,
- (range == HNDDMA_RANGE_ALL) ? "all" :
- ((range ==
- HNDDMA_RANGE_TRANSMITTED) ? "transmitted" :
- "transferred")));
-
- if (di->txin == di->txout)
- return;
-
- while ((p = dma64_getnexttxp(di, range))) {
- /* For unframed data, we don't have any packets to free */
- if (!(di->hnddma.dmactrlflags & DMA_CTRL_UNFRAMED))
- pkt_buf_free_skb(p);
- }
-}
-
-static bool dma64_txstopped(dma_info_t *di)
-{
- return ((R_REG(&di->d64txregs->status0) & D64_XS0_XS_MASK) ==
- D64_XS0_XS_STOPPED);
-}
-
-static bool dma64_rxstopped(dma_info_t *di)
-{
- return ((R_REG(&di->d64rxregs->status0) & D64_RS0_RS_MASK) ==
- D64_RS0_RS_STOPPED);
-}
-
-static bool dma64_alloc(dma_info_t *di, uint direction)
-{
- u16 size;
- uint ddlen;
- void *va;
- uint alloced = 0;
- u16 align;
- u16 align_bits;
-
- ddlen = sizeof(dma64dd_t);
-
- size = (direction == DMA_TX) ? (di->ntxd * ddlen) : (di->nrxd * ddlen);
- align_bits = di->dmadesc_align;
- align = (1 << align_bits);
-
- if (direction == DMA_TX) {
- va = dma_ringalloc(di, D64RINGALIGN, size, &align_bits,
- &alloced, &di->txdpaorig);
- if (va == NULL) {
- DMA_ERROR(("%s: dma64_alloc: DMA_ALLOC_CONSISTENT(ntxd) failed\n", di->name));
- return false;
- }
- align = (1 << align_bits);
- di->txd64 = (dma64dd_t *) roundup((unsigned long)va, align);
- di->txdalign = (uint) ((s8 *)di->txd64 - (s8 *) va);
- PHYSADDRLOSET(di->txdpa,
- PHYSADDRLO(di->txdpaorig) + di->txdalign);
- /* Make sure that alignment didn't overflow */
- ASSERT(PHYSADDRLO(di->txdpa) >= PHYSADDRLO(di->txdpaorig));
-
- PHYSADDRHISET(di->txdpa, PHYSADDRHI(di->txdpaorig));
- di->txdalloc = alloced;
- ASSERT(IS_ALIGNED((unsigned long)di->txd64, align));
- } else {
- va = dma_ringalloc(di, D64RINGALIGN, size, &align_bits,
- &alloced, &di->rxdpaorig);
- if (va == NULL) {
- DMA_ERROR(("%s: dma64_alloc: DMA_ALLOC_CONSISTENT(nrxd) failed\n", di->name));
- return false;
- }
- align = (1 << align_bits);
- di->rxd64 = (dma64dd_t *) roundup((unsigned long)va, align);
- di->rxdalign = (uint) ((s8 *)di->rxd64 - (s8 *) va);
- PHYSADDRLOSET(di->rxdpa,
- PHYSADDRLO(di->rxdpaorig) + di->rxdalign);
- /* Make sure that alignment didn't overflow */
- ASSERT(PHYSADDRLO(di->rxdpa) >= PHYSADDRLO(di->rxdpaorig));
-
- PHYSADDRHISET(di->rxdpa, PHYSADDRHI(di->rxdpaorig));
- di->rxdalloc = alloced;
- ASSERT(IS_ALIGNED((unsigned long)di->rxd64, align));
- }
-
- return true;
-}
-
-static bool dma64_txreset(dma_info_t *di)
-{
- u32 status;
-
- if (di->ntxd == 0)
- return true;
-
- /* suspend tx DMA first */
- W_REG(&di->d64txregs->control, D64_XC_SE);
- SPINWAIT(((status =
- (R_REG(&di->d64txregs->status0) & D64_XS0_XS_MASK))
- != D64_XS0_XS_DISABLED) && (status != D64_XS0_XS_IDLE)
- && (status != D64_XS0_XS_STOPPED), 10000);
-
- W_REG(&di->d64txregs->control, 0);
- SPINWAIT(((status =
- (R_REG(&di->d64txregs->status0) & D64_XS0_XS_MASK))
- != D64_XS0_XS_DISABLED), 10000);
-
- /* wait for the last transaction to complete */
- udelay(300);
-
- return status == D64_XS0_XS_DISABLED;
-}
-
-static bool dma64_rxidle(dma_info_t *di)
-{
- DMA_TRACE(("%s: dma_rxidle\n", di->name));
-
- if (di->nrxd == 0)
- return true;
-
- return ((R_REG(&di->d64rxregs->status0) & D64_RS0_CD_MASK) ==
- (R_REG(&di->d64rxregs->ptr) & D64_RS0_CD_MASK));
-}
-
-static bool dma64_rxreset(dma_info_t *di)
-{
- u32 status;
-
- if (di->nrxd == 0)
- return true;
-
- W_REG(&di->d64rxregs->control, 0);
- SPINWAIT(((status =
- (R_REG(&di->d64rxregs->status0) & D64_RS0_RS_MASK))
- != D64_RS0_RS_DISABLED), 10000);
-
- return status == D64_RS0_RS_DISABLED;
-}
-
-static bool dma64_rxenabled(dma_info_t *di)
-{
- u32 rc;
-
- rc = R_REG(&di->d64rxregs->control);
- return (rc != 0xffffffff) && (rc & D64_RC_RE);
-}
-
-static bool dma64_txsuspendedidle(dma_info_t *di)
-{
-
- if (di->ntxd == 0)
- return true;
-
- if (!(R_REG(&di->d64txregs->control) & D64_XC_SE))
- return 0;
-
- if ((R_REG(&di->d64txregs->status0) & D64_XS0_XS_MASK) ==
- D64_XS0_XS_IDLE)
- return 1;
-
- return 0;
-}
-
-/* Useful when sending unframed data. This allows us to get a progress report from the DMA.
- * We return a pointer to the beginning of the DATA buffer of the current descriptor.
- * If DMA is idle, we return NULL.
- */
-static void *dma64_getpos(dma_info_t *di, bool direction)
-{
- void *va;
- bool idle;
- u32 cd_offset;
-
- if (direction == DMA_TX) {
- cd_offset =
- R_REG(&di->d64txregs->status0) & D64_XS0_CD_MASK;
- idle = !NTXDACTIVE(di->txin, di->txout);
- va = di->txp[B2I(cd_offset, dma64dd_t)];
- } else {
- cd_offset =
- R_REG(&di->d64rxregs->status0) & D64_XS0_CD_MASK;
- idle = !NRXDACTIVE(di->rxin, di->rxout);
- va = di->rxp[B2I(cd_offset, dma64dd_t)];
- }
-
- /* If DMA is IDLE, return NULL */
- if (idle) {
- DMA_TRACE(("%s: DMA idle, return NULL\n", __func__));
- va = NULL;
- }
-
- return va;
-}
-
-/* TX of unframed data
- *
- * Adds a DMA ring descriptor for the data pointed to by "buf".
- * This is for DMA of a buffer of data and is unlike other hnddma TX functions
- * that take a pointer to a "packet"
- * Each call to this is results in a single descriptor being added for "len" bytes of
- * data starting at "buf", it doesn't handle chained buffers.
- */
-static int dma64_txunframed(dma_info_t *di, void *buf, uint len, bool commit)
-{
- u16 txout;
- u32 flags = 0;
- dmaaddr_t pa; /* phys addr */
-
- txout = di->txout;
-
- /* return nonzero if out of tx descriptors */
- if (NEXTTXD(txout) == di->txin)
- goto outoftxd;
-
- if (len == 0)
- return 0;
-
- pa = pci_map_single(di->pbus, buf, len, PCI_DMA_TODEVICE);
-
- flags = (D64_CTRL1_SOF | D64_CTRL1_IOC | D64_CTRL1_EOF);
-
- if (txout == (di->ntxd - 1))
- flags |= D64_CTRL1_EOT;
-
- dma64_dd_upd(di, di->txd64, pa, txout, &flags, len);
- ASSERT(di->txp[txout] == NULL);
-
- /* save the buffer pointer - used by dma_getpos */
- di->txp[txout] = buf;
-
- txout = NEXTTXD(txout);
- /* bump the tx descriptor index */
- di->txout = txout;
-
- /* kick the chip */
- if (commit) {
- W_REG(&di->d64txregs->ptr,
- di->xmtptrbase + I2B(txout, dma64dd_t));
- }
-
- /* tx flow control */
- di->hnddma.txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
-
- return 0;
-
- outoftxd:
- DMA_ERROR(("%s: %s: out of txds !!!\n", di->name, __func__));
- di->hnddma.txavail = 0;
- di->hnddma.txnobuf++;
- return -1;
-}
-
-/* !! tx entry routine
- * WARNING: call must check the return value for error.
- * the error(toss frames) could be fatal and cause many subsequent hard to debug problems
- */
-static int BCMFASTPATH dma64_txfast(dma_info_t *di, struct sk_buff *p0,
- bool commit)
-{
- struct sk_buff *p, *next;
- unsigned char *data;
- uint len;
- u16 txout;
- u32 flags = 0;
- dmaaddr_t pa;
-
- DMA_TRACE(("%s: dma_txfast\n", di->name));
-
- txout = di->txout;
-
- /*
- * Walk the chain of packet buffers
- * allocating and initializing transmit descriptor entries.
- */
- for (p = p0; p; p = next) {
- uint nsegs, j;
- hnddma_seg_map_t *map;
-
- data = p->data;
- len = p->len;
-#ifdef BCM_DMAPAD
- len += PKTDMAPAD(di->osh, p);
-#endif /* BCM_DMAPAD */
- next = p->next;
-
- /* return nonzero if out of tx descriptors */
- if (NEXTTXD(txout) == di->txin)
- goto outoftxd;
-
- if (len == 0)
- continue;
-
- /* get physical address of buffer start */
- if (DMASGLIST_ENAB)
- memset(&di->txp_dmah[txout], 0,
- sizeof(hnddma_seg_map_t));
-
- pa = pci_map_single(di->pbus, data, len, PCI_DMA_TODEVICE);
-
- if (DMASGLIST_ENAB) {
- map = &di->txp_dmah[txout];
-
- /* See if all the segments can be accounted for */
- if (map->nsegs >
- (uint) (di->ntxd - NTXDACTIVE(di->txin, di->txout) -
- 1))
- goto outoftxd;
-
- nsegs = map->nsegs;
- } else
- nsegs = 1;
-
- for (j = 1; j <= nsegs; j++) {
- flags = 0;
- if (p == p0 && j == 1)
- flags |= D64_CTRL1_SOF;
-
- /* With a DMA segment list, Descriptor table is filled
- * using the segment list instead of looping over
- * buffers in multi-chain DMA. Therefore, EOF for SGLIST is when
- * end of segment list is reached.
- */
- if ((!DMASGLIST_ENAB && next == NULL) ||
- (DMASGLIST_ENAB && j == nsegs))
- flags |= (D64_CTRL1_IOC | D64_CTRL1_EOF);
- if (txout == (di->ntxd - 1))
- flags |= D64_CTRL1_EOT;
-
- if (DMASGLIST_ENAB) {
- len = map->segs[j - 1].length;
- pa = map->segs[j - 1].addr;
- }
- dma64_dd_upd(di, di->txd64, pa, txout, &flags, len);
- ASSERT(di->txp[txout] == NULL);
-
- txout = NEXTTXD(txout);
- }
-
- /* See above. No need to loop over individual buffers */
- if (DMASGLIST_ENAB)
- break;
- }
-
- /* if last txd eof not set, fix it */
- if (!(flags & D64_CTRL1_EOF))
- W_SM(&di->txd64[PREVTXD(txout)].ctrl1,
- BUS_SWAP32(flags | D64_CTRL1_IOC | D64_CTRL1_EOF));
-
- /* save the packet */
- di->txp[PREVTXD(txout)] = p0;
-
- /* bump the tx descriptor index */
- di->txout = txout;
-
- /* kick the chip */
- if (commit)
- W_REG(&di->d64txregs->ptr,
- di->xmtptrbase + I2B(txout, dma64dd_t));
-
- /* tx flow control */
- di->hnddma.txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
-
- return 0;
-
- outoftxd:
- DMA_ERROR(("%s: dma_txfast: out of txds !!!\n", di->name));
- pkt_buf_free_skb(p0);
- di->hnddma.txavail = 0;
- di->hnddma.txnobuf++;
- return -1;
-}
-
-/*
- * Reclaim next completed txd (txds if using chained buffers) in the range
- * specified and return associated packet.
- * If range is HNDDMA_RANGE_TRANSMITTED, reclaim descriptors that have be
- * transmitted as noted by the hardware "CurrDescr" pointer.
- * If range is HNDDMA_RANGE_TRANSFERED, reclaim descriptors that have be
- * transferred by the DMA as noted by the hardware "ActiveDescr" pointer.
- * If range is HNDDMA_RANGE_ALL, reclaim all txd(s) posted to the ring and
- * return associated packet regardless of the value of hardware pointers.
- */
-static void *BCMFASTPATH dma64_getnexttxp(dma_info_t *di, txd_range_t range)
-{
- u16 start, end, i;
- u16 active_desc;
- void *txp;
-
- DMA_TRACE(("%s: dma_getnexttxp %s\n", di->name,
- (range == HNDDMA_RANGE_ALL) ? "all" :
- ((range ==
- HNDDMA_RANGE_TRANSMITTED) ? "transmitted" :
- "transferred")));
-
- if (di->ntxd == 0)
- return NULL;
-
- txp = NULL;
-
- start = di->txin;
- if (range == HNDDMA_RANGE_ALL)
- end = di->txout;
- else {
- dma64regs_t *dregs = di->d64txregs;
-
- end =
- (u16) (B2I
- (((R_REG(&dregs->status0) &
- D64_XS0_CD_MASK) -
- di->xmtptrbase) & D64_XS0_CD_MASK, dma64dd_t));
-
- if (range == HNDDMA_RANGE_TRANSFERED) {
- active_desc =
- (u16) (R_REG(&dregs->status1) &
- D64_XS1_AD_MASK);
- active_desc =
- (active_desc - di->xmtptrbase) & D64_XS0_CD_MASK;
- active_desc = B2I(active_desc, dma64dd_t);
- if (end != active_desc)
- end = PREVTXD(active_desc);
- }
- }
-
- if ((start == 0) && (end > di->txout))
- goto bogus;
-
- for (i = start; i != end && !txp; i = NEXTTXD(i)) {
- dmaaddr_t pa;
- hnddma_seg_map_t *map = NULL;
- uint size, j, nsegs;
-
- PHYSADDRLOSET(pa,
- (BUS_SWAP32(R_SM(&di->txd64[i].addrlow)) -
- di->dataoffsetlow));
- PHYSADDRHISET(pa,
- (BUS_SWAP32(R_SM(&di->txd64[i].addrhigh)) -
- di->dataoffsethigh));
-
- if (DMASGLIST_ENAB) {
- map = &di->txp_dmah[i];
- size = map->origsize;
- nsegs = map->nsegs;
- } else {
- size =
- (BUS_SWAP32(R_SM(&di->txd64[i].ctrl2)) &
- D64_CTRL2_BC_MASK);
- nsegs = 1;
- }
-
- for (j = nsegs; j > 0; j--) {
- W_SM(&di->txd64[i].addrlow, 0xdeadbeef);
- W_SM(&di->txd64[i].addrhigh, 0xdeadbeef);
-
- txp = di->txp[i];
- di->txp[i] = NULL;
- if (j > 1)
- i = NEXTTXD(i);
- }
-
- pci_unmap_single(di->pbus, pa, size, PCI_DMA_TODEVICE);
- }
-
- di->txin = i;
-
- /* tx flow control */
- di->hnddma.txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
-
- return txp;
-
- bogus:
- DMA_NONE(("dma_getnexttxp: bogus curr: start %d end %d txout %d force %d\n", start, end, di->txout, forceall));
- return NULL;
-}
-
-static void *BCMFASTPATH dma64_getnextrxp(dma_info_t *di, bool forceall)
-{
- uint i, curr;
- void *rxp;
- dmaaddr_t pa;
-
- /* if forcing, dma engine must be disabled */
- ASSERT(!forceall || !dma64_rxenabled(di));
-
- i = di->rxin;
-
- /* return if no packets posted */
- if (i == di->rxout)
- return NULL;
-
- curr =
- B2I(((R_REG(&di->d64rxregs->status0) & D64_RS0_CD_MASK) -
- di->rcvptrbase) & D64_RS0_CD_MASK, dma64dd_t);
-
- /* ignore curr if forceall */
- if (!forceall && (i == curr))
- return NULL;
-
- /* get the packet pointer that corresponds to the rx descriptor */
- rxp = di->rxp[i];
- ASSERT(rxp);
- di->rxp[i] = NULL;
-
- PHYSADDRLOSET(pa,
- (BUS_SWAP32(R_SM(&di->rxd64[i].addrlow)) -
- di->dataoffsetlow));
- PHYSADDRHISET(pa,
- (BUS_SWAP32(R_SM(&di->rxd64[i].addrhigh)) -
- di->dataoffsethigh));
-
- /* clear this packet from the descriptor ring */
- pci_unmap_single(di->pbus, pa, di->rxbufsize, PCI_DMA_FROMDEVICE);
-
- W_SM(&di->rxd64[i].addrlow, 0xdeadbeef);
- W_SM(&di->rxd64[i].addrhigh, 0xdeadbeef);
-
- di->rxin = NEXTRXD(i);
-
- return rxp;
-}
-
-static bool _dma64_addrext(dma64regs_t *dma64regs)
-{
- u32 w;
- OR_REG(&dma64regs->control, D64_XC_AE);
- w = R_REG(&dma64regs->control);
- AND_REG(&dma64regs->control, ~D64_XC_AE);
- return (w & D64_XC_AE) == D64_XC_AE;
-}
-
-/*
- * Rotate all active tx dma ring entries "forward" by (ActiveDescriptor - txin).
- */
-static void dma64_txrotate(dma_info_t *di)
-{
- u16 ad;
- uint nactive;
- uint rot;
- u16 old, new;
- u32 w;
- u16 first, last;
-
- ASSERT(dma64_txsuspendedidle(di));
-
- nactive = _dma_txactive(di);
- ad = (u16) (B2I
- ((((R_REG(&di->d64txregs->status1) &
- D64_XS1_AD_MASK)
- - di->xmtptrbase) & D64_XS1_AD_MASK), dma64dd_t));
- rot = TXD(ad - di->txin);
-
- ASSERT(rot < di->ntxd);
-
- /* full-ring case is a lot harder - don't worry about this */
- if (rot >= (di->ntxd - nactive)) {
- DMA_ERROR(("%s: dma_txrotate: ring full - punt\n", di->name));
- return;
- }
-
- first = di->txin;
- last = PREVTXD(di->txout);
-
- /* move entries starting at last and moving backwards to first */
- for (old = last; old != PREVTXD(first); old = PREVTXD(old)) {
- new = TXD(old + rot);
-
- /*
- * Move the tx dma descriptor.
- * EOT is set only in the last entry in the ring.
- */
- w = BUS_SWAP32(R_SM(&di->txd64[old].ctrl1)) & ~D64_CTRL1_EOT;
- if (new == (di->ntxd - 1))
- w |= D64_CTRL1_EOT;
- W_SM(&di->txd64[new].ctrl1, BUS_SWAP32(w));
-
- w = BUS_SWAP32(R_SM(&di->txd64[old].ctrl2));
- W_SM(&di->txd64[new].ctrl2, BUS_SWAP32(w));
-
- W_SM(&di->txd64[new].addrlow, R_SM(&di->txd64[old].addrlow));
- W_SM(&di->txd64[new].addrhigh, R_SM(&di->txd64[old].addrhigh));
-
- /* zap the old tx dma descriptor address field */
- W_SM(&di->txd64[old].addrlow, BUS_SWAP32(0xdeadbeef));
- W_SM(&di->txd64[old].addrhigh, BUS_SWAP32(0xdeadbeef));
-
- /* move the corresponding txp[] entry */
- ASSERT(di->txp[new] == NULL);
- di->txp[new] = di->txp[old];
-
- /* Move the map */
- if (DMASGLIST_ENAB) {
- memcpy(&di->txp_dmah[new], &di->txp_dmah[old],
- sizeof(hnddma_seg_map_t));
- memset(&di->txp_dmah[old], 0, sizeof(hnddma_seg_map_t));
- }
-
- di->txp[old] = NULL;
- }
-
- /* update txin and txout */
- di->txin = ad;
- di->txout = TXD(di->txout + rot);
- di->hnddma.txavail = di->ntxd - NTXDACTIVE(di->txin, di->txout) - 1;
-
- /* kick the chip */
- W_REG(&di->d64txregs->ptr,
- di->xmtptrbase + I2B(di->txout, dma64dd_t));
-}
-
-uint dma_addrwidth(si_t *sih, void *dmaregs)
-{
- /* Perform 64-bit checks only if we want to advertise 64-bit (> 32bit) capability) */
- /* DMA engine is 64-bit capable */
- if ((si_core_sflags(sih, 0, 0) & SISF_DMA64) == SISF_DMA64) {
- /* backplane are 64-bit capable */
- if (si_backplane64(sih))
- /* If bus is System Backplane or PCIE then we can access 64-bits */
- if ((sih->bustype == SI_BUS) ||
- ((sih->bustype == PCI_BUS) &&
- (sih->buscoretype == PCIE_CORE_ID)))
- return DMADDRWIDTH_64;
- }
- ASSERT(0); /* DMA hardware not supported by this driver*/
- return DMADDRWIDTH_64;
-}
-
-/*
- * Mac80211 initiated actions sometimes require packets in the DMA queue to be
- * modified. The modified portion of the packet is not under control of the DMA
- * engine. This function calls a caller-supplied function for each packet in
- * the caller specified dma chain.
- */
-void dma_walk_packets(struct hnddma_pub *dmah, void (*callback_fnc)
- (void *pkt, void *arg_a), void *arg_a)
-{
- dma_info_t *di = (dma_info_t *) dmah;
- uint i = di->txin;
- uint end = di->txout;
- struct sk_buff *skb;
- struct ieee80211_tx_info *tx_info;
-
- while (i != end) {
- skb = (struct sk_buff *)di->txp[i];
- if (skb != NULL) {
- tx_info = (struct ieee80211_tx_info *)skb->cb;
- (callback_fnc)(tx_info, arg_a);
- }
- i = NEXTTXD(i);
- }
-}
diff --git a/drivers/staging/brcm80211/util/hndpmu.c b/drivers/staging/brcm80211/util/hndpmu.c
deleted file mode 100644
index 59e3ede..0000000
--- a/drivers/staging/brcm80211/util/hndpmu.c
+++ /dev/null
@@ -1,2675 +0,0 @@
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-#include <linux/delay.h>
-#include <linux/kernel.h>
-#include <linux/string.h>
-#include <linux/module.h>
-#include <linux/pci.h>
-#include <bcmdefs.h>
-#include <bcmutils.h>
-#include <siutils.h>
-#include <bcmdevs.h>
-#include <hndsoc.h>
-#include <sbchipc.h>
-#include <hndpmu.h>
-#include "siutils_priv.h"
-
-#define PMU_ERROR(args)
-
-#ifdef BCMDBG
-#define PMU_MSG(args) printk args
-
-/* debug-only definitions */
-/* #define BCMDBG_FORCEHT */
-/* #define CHIPC_UART_ALWAYS_ON */
-#else
-#define PMU_MSG(args)
-#endif /* BCMDBG */
-
-/* To check in verbose debugging messages not intended
- * to be on except on private builds.
- */
-#define PMU_NONE(args)
-
-/* PLL controls/clocks */
-static void si_pmu1_pllinit0(si_t *sih, chipcregs_t *cc, u32 xtal);
-static u32 si_pmu1_cpuclk0(si_t *sih, chipcregs_t *cc);
-static u32 si_pmu1_alpclk0(si_t *sih, chipcregs_t *cc);
-
-/* PMU resources */
-static bool si_pmu_res_depfltr_bb(si_t *sih);
-static bool si_pmu_res_depfltr_ncb(si_t *sih);
-static bool si_pmu_res_depfltr_paldo(si_t *sih);
-static bool si_pmu_res_depfltr_npaldo(si_t *sih);
-static u32 si_pmu_res_deps(si_t *sih, chipcregs_t *cc, u32 rsrcs, bool all);
-static uint si_pmu_res_uptime(si_t *sih, chipcregs_t *cc, u8 rsrc);
-static void si_pmu_res_masks(si_t *sih, u32 * pmin, u32 * pmax);
-static void si_pmu_spuravoid_pllupdate(si_t *sih, chipcregs_t *cc,
- u8 spuravoid);
-
-static void si_pmu_set_4330_plldivs(si_t *sih);
-
-/* FVCO frequency */
-#define FVCO_880 880000 /* 880MHz */
-#define FVCO_1760 1760000 /* 1760MHz */
-#define FVCO_1440 1440000 /* 1440MHz */
-#define FVCO_960 960000 /* 960MHz */
-
-/* Read/write a chipcontrol reg */
-u32 si_pmu_chipcontrol(si_t *sih, uint reg, u32 mask, u32 val)
-{
- si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, chipcontrol_addr), ~0,
- reg);
- return si_corereg(sih, SI_CC_IDX,
- offsetof(chipcregs_t, chipcontrol_data), mask, val);
-}
-
-/* Read/write a regcontrol reg */
-u32 si_pmu_regcontrol(si_t *sih, uint reg, u32 mask, u32 val)
-{
- si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, regcontrol_addr), ~0,
- reg);
- return si_corereg(sih, SI_CC_IDX,
- offsetof(chipcregs_t, regcontrol_data), mask, val);
-}
-
-/* Read/write a pllcontrol reg */
-u32 si_pmu_pllcontrol(si_t *sih, uint reg, u32 mask, u32 val)
-{
- si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, pllcontrol_addr), ~0,
- reg);
- return si_corereg(sih, SI_CC_IDX,
- offsetof(chipcregs_t, pllcontrol_data), mask, val);
-}
-
-/* PMU PLL update */
-void si_pmu_pllupd(si_t *sih)
-{
- si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, pmucontrol),
- PCTL_PLL_PLLCTL_UPD, PCTL_PLL_PLLCTL_UPD);
-}
-
-/* Setup switcher voltage */
-void si_pmu_set_switcher_voltage(si_t *sih, u8 bb_voltage, u8 rf_voltage)
-{
- chipcregs_t *cc;
- uint origidx;
-
- ASSERT(sih->cccaps & CC_CAP_PMU);
-
- /* Remember original core before switch to chipc */
- origidx = si_coreidx(sih);
- cc = si_setcoreidx(sih, SI_CC_IDX);
- ASSERT(cc != NULL);
-
- W_REG(&cc->regcontrol_addr, 0x01);
- W_REG(&cc->regcontrol_data, (u32) (bb_voltage & 0x1f) << 22);
-
- W_REG(&cc->regcontrol_addr, 0x00);
- W_REG(&cc->regcontrol_data, (u32) (rf_voltage & 0x1f) << 14);
-
- /* Return to original core */
- si_setcoreidx(sih, origidx);
-}
-
-void si_pmu_set_ldo_voltage(si_t *sih, u8 ldo, u8 voltage)
-{
- u8 sr_cntl_shift = 0, rc_shift = 0, shift = 0, mask = 0;
- u8 addr = 0;
-
- ASSERT(sih->cccaps & CC_CAP_PMU);
-
- switch (sih->chip) {
- case BCM4336_CHIP_ID:
- switch (ldo) {
- case SET_LDO_VOLTAGE_CLDO_PWM:
- addr = 4;
- rc_shift = 1;
- mask = 0xf;
- break;
- case SET_LDO_VOLTAGE_CLDO_BURST:
- addr = 4;
- rc_shift = 5;
- mask = 0xf;
- break;
- case SET_LDO_VOLTAGE_LNLDO1:
- addr = 4;
- rc_shift = 17;
- mask = 0xf;
- break;
- default:
- ASSERT(false);
- return;
- }
- break;
- case BCM4330_CHIP_ID:
- switch (ldo) {
- case SET_LDO_VOLTAGE_CBUCK_PWM:
- addr = 3;
- rc_shift = 0;
- mask = 0x1f;
- break;
- default:
- ASSERT(false);
- break;
- }
- break;
- default:
- ASSERT(false);
- return;
- }
-
- shift = sr_cntl_shift + rc_shift;
-
- si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, regcontrol_addr),
- ~0, addr);
- si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, regcontrol_data),
- mask << shift, (voltage & mask) << shift);
-}
-
-/* d11 slow to fast clock transition time in slow clock cycles */
-#define D11SCC_SLOW2FAST_TRANSITION 2
-
-u16 si_pmu_fast_pwrup_delay(si_t *sih)
-{
- uint delay = PMU_MAX_TRANSITION_DLY;
- chipcregs_t *cc;
- uint origidx;
-#ifdef BCMDBG
- char chn[8];
- chn[0] = 0; /* to suppress compile error */
-#endif
-
- ASSERT(sih->cccaps & CC_CAP_PMU);
-
- /* Remember original core before switch to chipc */
- origidx = si_coreidx(sih);
- cc = si_setcoreidx(sih, SI_CC_IDX);
- ASSERT(cc != NULL);
-
- switch (sih->chip) {
- case BCM43224_CHIP_ID:
- case BCM43225_CHIP_ID:
- case BCM43421_CHIP_ID:
- case BCM43235_CHIP_ID:
- case BCM43236_CHIP_ID:
- case BCM43238_CHIP_ID:
- case BCM4331_CHIP_ID:
- case BCM6362_CHIP_ID:
- case BCM4313_CHIP_ID:
- delay = ISSIM_ENAB(sih) ? 70 : 3700;
- break;
- case BCM4329_CHIP_ID:
- if (ISSIM_ENAB(sih))
- delay = 70;
- else {
- u32 ilp = si_ilp_clock(sih);
- delay =
- (si_pmu_res_uptime(sih, cc, RES4329_HT_AVAIL) +
- D11SCC_SLOW2FAST_TRANSITION) * ((1000000 + ilp -
- 1) / ilp);
- delay = (11 * delay) / 10;
- }
- break;
- case BCM4319_CHIP_ID:
- delay = ISSIM_ENAB(sih) ? 70 : 3700;
- break;
- case BCM4336_CHIP_ID:
- if (ISSIM_ENAB(sih))
- delay = 70;
- else {
- u32 ilp = si_ilp_clock(sih);
- delay =
- (si_pmu_res_uptime(sih, cc, RES4336_HT_AVAIL) +
- D11SCC_SLOW2FAST_TRANSITION) * ((1000000 + ilp -
- 1) / ilp);
- delay = (11 * delay) / 10;
- }
- break;
- case BCM4330_CHIP_ID:
- if (ISSIM_ENAB(sih))
- delay = 70;
- else {
- u32 ilp = si_ilp_clock(sih);
- delay =
- (si_pmu_res_uptime(sih, cc, RES4330_HT_AVAIL) +
- D11SCC_SLOW2FAST_TRANSITION) * ((1000000 + ilp -
- 1) / ilp);
- delay = (11 * delay) / 10;
- }
- break;
- default:
- break;
- }
- /* Return to original core */
- si_setcoreidx(sih, origidx);
-
- return (u16) delay;
-}
-
-u32 si_pmu_force_ilp(si_t *sih, bool force)
-{
- chipcregs_t *cc;
- uint origidx;
- u32 oldpmucontrol;
-
- ASSERT(sih->cccaps & CC_CAP_PMU);
-
- /* Remember original core before switch to chipc */
- origidx = si_coreidx(sih);
- cc = si_setcoreidx(sih, SI_CC_IDX);
- ASSERT(cc != NULL);
-
- oldpmucontrol = R_REG(&cc->pmucontrol);
- if (force)
- W_REG(&cc->pmucontrol, oldpmucontrol &
- ~(PCTL_HT_REQ_EN | PCTL_ALP_REQ_EN));
- else
- W_REG(&cc->pmucontrol, oldpmucontrol |
- (PCTL_HT_REQ_EN | PCTL_ALP_REQ_EN));
-
- /* Return to original core */
- si_setcoreidx(sih, origidx);
-
- return oldpmucontrol;
-}
-
-/* Setup resource up/down timers */
-typedef struct {
- u8 resnum;
- u16 updown;
-} pmu_res_updown_t;
-
-/* Change resource dependancies masks */
-typedef struct {
- u32 res_mask; /* resources (chip specific) */
- s8 action; /* action */
- u32 depend_mask; /* changes to the dependancies mask */
- bool(*filter) (si_t *sih); /* action is taken when filter is NULL or return true */
-} pmu_res_depend_t;
-
-/* Resource dependancies mask change action */
-#define RES_DEPEND_SET 0 /* Override the dependancies mask */
-#define RES_DEPEND_ADD 1 /* Add to the dependancies mask */
-#define RES_DEPEND_REMOVE -1 /* Remove from the dependancies mask */
-
-static const pmu_res_updown_t bcm4328a0_res_updown[] = {
- {
- RES4328_EXT_SWITCHER_PWM, 0x0101}, {
- RES4328_BB_SWITCHER_PWM, 0x1f01}, {
- RES4328_BB_SWITCHER_BURST, 0x010f}, {
- RES4328_BB_EXT_SWITCHER_BURST, 0x0101}, {
- RES4328_ILP_REQUEST, 0x0202}, {
- RES4328_RADIO_SWITCHER_PWM, 0x0f01}, {
- RES4328_RADIO_SWITCHER_BURST, 0x0f01}, {
- RES4328_ROM_SWITCH, 0x0101}, {
- RES4328_PA_REF_LDO, 0x0f01}, {
- RES4328_RADIO_LDO, 0x0f01}, {
- RES4328_AFE_LDO, 0x0f01}, {
- RES4328_PLL_LDO, 0x0f01}, {
- RES4328_BG_FILTBYP, 0x0101}, {
- RES4328_TX_FILTBYP, 0x0101}, {
- RES4328_RX_FILTBYP, 0x0101}, {
- RES4328_XTAL_PU, 0x0101}, {
- RES4328_XTAL_EN, 0xa001}, {
- RES4328_BB_PLL_FILTBYP, 0x0101}, {
- RES4328_RF_PLL_FILTBYP, 0x0101}, {
- RES4328_BB_PLL_PU, 0x0701}
-};
-
-static const pmu_res_depend_t bcm4328a0_res_depend[] = {
- /* Adjust ILP request resource not to force ext/BB switchers into burst mode */
- {
- PMURES_BIT(RES4328_ILP_REQUEST),
- RES_DEPEND_SET,
- PMURES_BIT(RES4328_EXT_SWITCHER_PWM) |
- PMURES_BIT(RES4328_BB_SWITCHER_PWM), NULL}
-};
-
-static const pmu_res_updown_t bcm4325a0_res_updown_qt[] = {
- {
- RES4325_HT_AVAIL, 0x0300}, {
- RES4325_BBPLL_PWRSW_PU, 0x0101}, {
- RES4325_RFPLL_PWRSW_PU, 0x0101}, {
- RES4325_ALP_AVAIL, 0x0100}, {
- RES4325_XTAL_PU, 0x1000}, {
- RES4325_LNLDO1_PU, 0x0800}, {
- RES4325_CLDO_CBUCK_PWM, 0x0101}, {
- RES4325_CBUCK_PWM, 0x0803}
-};
-
-static const pmu_res_updown_t bcm4325a0_res_updown[] = {
- {
- RES4325_XTAL_PU, 0x1501}
-};
-
-static const pmu_res_depend_t bcm4325a0_res_depend[] = {
- /* Adjust OTP PU resource dependencies - remove BB BURST */
- {
- PMURES_BIT(RES4325_OTP_PU),
- RES_DEPEND_REMOVE,
- PMURES_BIT(RES4325_BUCK_BOOST_BURST), NULL},
- /* Adjust ALP/HT Avail resource dependencies - bring up BB along if it is used. */
- {
- PMURES_BIT(RES4325_ALP_AVAIL) | PMURES_BIT(RES4325_HT_AVAIL),
- RES_DEPEND_ADD,
- PMURES_BIT(RES4325_BUCK_BOOST_BURST) |
- PMURES_BIT(RES4325_BUCK_BOOST_PWM), si_pmu_res_depfltr_bb},
- /* Adjust HT Avail resource dependencies - bring up RF switches along with HT. */
- {
- PMURES_BIT(RES4325_HT_AVAIL),
- RES_DEPEND_ADD,
- PMURES_BIT(RES4325_RX_PWRSW_PU) |
- PMURES_BIT(RES4325_TX_PWRSW_PU) |
- PMURES_BIT(RES4325_LOGEN_PWRSW_PU) |
- PMURES_BIT(RES4325_AFE_PWRSW_PU), NULL},
- /* Adjust ALL resource dependencies - remove CBUCK dependancies if it is not used. */
- {
- PMURES_BIT(RES4325_ILP_REQUEST) |
- PMURES_BIT(RES4325_ABUCK_BURST) |
- PMURES_BIT(RES4325_ABUCK_PWM) |
- PMURES_BIT(RES4325_LNLDO1_PU) |
- PMURES_BIT(RES4325C1_LNLDO2_PU) |
- PMURES_BIT(RES4325_XTAL_PU) |
- PMURES_BIT(RES4325_ALP_AVAIL) |
- PMURES_BIT(RES4325_RX_PWRSW_PU) |
- PMURES_BIT(RES4325_TX_PWRSW_PU) |
- PMURES_BIT(RES4325_RFPLL_PWRSW_PU) |
- PMURES_BIT(RES4325_LOGEN_PWRSW_PU) |
- PMURES_BIT(RES4325_AFE_PWRSW_PU) |
- PMURES_BIT(RES4325_BBPLL_PWRSW_PU) |
- PMURES_BIT(RES4325_HT_AVAIL), RES_DEPEND_REMOVE,
- PMURES_BIT(RES4325B0_CBUCK_LPOM) |
- PMURES_BIT(RES4325B0_CBUCK_BURST) |
- PMURES_BIT(RES4325B0_CBUCK_PWM), si_pmu_res_depfltr_ncb}
-};
-
-static const pmu_res_updown_t bcm4315a0_res_updown_qt[] = {
- {
- RES4315_HT_AVAIL, 0x0101}, {
- RES4315_XTAL_PU, 0x0100}, {
- RES4315_LNLDO1_PU, 0x0100}, {
- RES4315_PALDO_PU, 0x0100}, {
- RES4315_CLDO_PU, 0x0100}, {
- RES4315_CBUCK_PWM, 0x0100}, {
- RES4315_CBUCK_BURST, 0x0100}, {
- RES4315_CBUCK_LPOM, 0x0100}
-};
-
-static const pmu_res_updown_t bcm4315a0_res_updown[] = {
- {
- RES4315_XTAL_PU, 0x2501}
-};
-
-static const pmu_res_depend_t bcm4315a0_res_depend[] = {
- /* Adjust OTP PU resource dependencies - not need PALDO unless write */
- {
- PMURES_BIT(RES4315_OTP_PU),
- RES_DEPEND_REMOVE,
- PMURES_BIT(RES4315_PALDO_PU), si_pmu_res_depfltr_npaldo},
- /* Adjust ALP/HT Avail resource dependencies - bring up PALDO along if it is used. */
- {
- PMURES_BIT(RES4315_ALP_AVAIL) | PMURES_BIT(RES4315_HT_AVAIL),
- RES_DEPEND_ADD,
- PMURES_BIT(RES4315_PALDO_PU), si_pmu_res_depfltr_paldo},
- /* Adjust HT Avail resource dependencies - bring up RF switches along with HT. */
- {
- PMURES_BIT(RES4315_HT_AVAIL),
- RES_DEPEND_ADD,
- PMURES_BIT(RES4315_RX_PWRSW_PU) |
- PMURES_BIT(RES4315_TX_PWRSW_PU) |
- PMURES_BIT(RES4315_LOGEN_PWRSW_PU) |
- PMURES_BIT(RES4315_AFE_PWRSW_PU), NULL},
- /* Adjust ALL resource dependencies - remove CBUCK dependancies if it is not used. */
- {
- PMURES_BIT(RES4315_CLDO_PU) | PMURES_BIT(RES4315_ILP_REQUEST) |
- PMURES_BIT(RES4315_LNLDO1_PU) |
- PMURES_BIT(RES4315_OTP_PU) |
- PMURES_BIT(RES4315_LNLDO2_PU) |
- PMURES_BIT(RES4315_XTAL_PU) |
- PMURES_BIT(RES4315_ALP_AVAIL) |
- PMURES_BIT(RES4315_RX_PWRSW_PU) |
- PMURES_BIT(RES4315_TX_PWRSW_PU) |
- PMURES_BIT(RES4315_RFPLL_PWRSW_PU) |
- PMURES_BIT(RES4315_LOGEN_PWRSW_PU) |
- PMURES_BIT(RES4315_AFE_PWRSW_PU) |
- PMURES_BIT(RES4315_BBPLL_PWRSW_PU) |
- PMURES_BIT(RES4315_HT_AVAIL), RES_DEPEND_REMOVE,
- PMURES_BIT(RES4315_CBUCK_LPOM) |
- PMURES_BIT(RES4315_CBUCK_BURST) |
- PMURES_BIT(RES4315_CBUCK_PWM), si_pmu_res_depfltr_ncb}
-};
-
- /* 4329 specific. needs to come back this issue later */
-static const pmu_res_updown_t bcm4329_res_updown[] = {
- {
- RES4329_XTAL_PU, 0x1501}
-};
-
-static const pmu_res_depend_t bcm4329_res_depend[] = {
- /* Adjust HT Avail resource dependencies */
- {
- PMURES_BIT(RES4329_HT_AVAIL),
- RES_DEPEND_ADD,
- PMURES_BIT(RES4329_CBUCK_LPOM) |
- PMURES_BIT(RES4329_CBUCK_BURST) |
- PMURES_BIT(RES4329_CBUCK_PWM) |
- PMURES_BIT(RES4329_CLDO_PU) |
- PMURES_BIT(RES4329_PALDO_PU) |
- PMURES_BIT(RES4329_LNLDO1_PU) |
- PMURES_BIT(RES4329_XTAL_PU) |
- PMURES_BIT(RES4329_ALP_AVAIL) |
- PMURES_BIT(RES4329_RX_PWRSW_PU) |
- PMURES_BIT(RES4329_TX_PWRSW_PU) |
- PMURES_BIT(RES4329_RFPLL_PWRSW_PU) |
- PMURES_BIT(RES4329_LOGEN_PWRSW_PU) |
- PMURES_BIT(RES4329_AFE_PWRSW_PU) |
- PMURES_BIT(RES4329_BBPLL_PWRSW_PU), NULL}
-};
-
-static const pmu_res_updown_t bcm4319a0_res_updown_qt[] = {
- {
- RES4319_HT_AVAIL, 0x0101}, {
- RES4319_XTAL_PU, 0x0100}, {
- RES4319_LNLDO1_PU, 0x0100}, {
- RES4319_PALDO_PU, 0x0100}, {
- RES4319_CLDO_PU, 0x0100}, {
- RES4319_CBUCK_PWM, 0x0100}, {
- RES4319_CBUCK_BURST, 0x0100}, {
- RES4319_CBUCK_LPOM, 0x0100}
-};
-
-static const pmu_res_updown_t bcm4319a0_res_updown[] = {
- {
- RES4319_XTAL_PU, 0x3f01}
-};
-
-static const pmu_res_depend_t bcm4319a0_res_depend[] = {
- /* Adjust OTP PU resource dependencies - not need PALDO unless write */
- {
- PMURES_BIT(RES4319_OTP_PU),
- RES_DEPEND_REMOVE,
- PMURES_BIT(RES4319_PALDO_PU), si_pmu_res_depfltr_npaldo},
- /* Adjust HT Avail resource dependencies - bring up PALDO along if it is used. */
- {
- PMURES_BIT(RES4319_HT_AVAIL),
- RES_DEPEND_ADD,
- PMURES_BIT(RES4319_PALDO_PU), si_pmu_res_depfltr_paldo},
- /* Adjust HT Avail resource dependencies - bring up RF switches along with HT. */
- {
- PMURES_BIT(RES4319_HT_AVAIL),
- RES_DEPEND_ADD,
- PMURES_BIT(RES4319_RX_PWRSW_PU) |
- PMURES_BIT(RES4319_TX_PWRSW_PU) |
- PMURES_BIT(RES4319_RFPLL_PWRSW_PU) |
- PMURES_BIT(RES4319_LOGEN_PWRSW_PU) |
- PMURES_BIT(RES4319_AFE_PWRSW_PU), NULL}
-};
-
-static const pmu_res_updown_t bcm4336a0_res_updown_qt[] = {
- {
- RES4336_HT_AVAIL, 0x0101}, {
- RES4336_XTAL_PU, 0x0100}, {
- RES4336_CLDO_PU, 0x0100}, {
- RES4336_CBUCK_PWM, 0x0100}, {
- RES4336_CBUCK_BURST, 0x0100}, {
- RES4336_CBUCK_LPOM, 0x0100}
-};
-
-static const pmu_res_updown_t bcm4336a0_res_updown[] = {
- {
- RES4336_HT_AVAIL, 0x0D01}
-};
-
-static const pmu_res_depend_t bcm4336a0_res_depend[] = {
- /* Just a dummy entry for now */
- {
- PMURES_BIT(RES4336_RSVD), RES_DEPEND_ADD, 0, NULL}
-};
-
-static const pmu_res_updown_t bcm4330a0_res_updown_qt[] = {
- {
- RES4330_HT_AVAIL, 0x0101}, {
- RES4330_XTAL_PU, 0x0100}, {
- RES4330_CLDO_PU, 0x0100}, {
- RES4330_CBUCK_PWM, 0x0100}, {
- RES4330_CBUCK_BURST, 0x0100}, {
- RES4330_CBUCK_LPOM, 0x0100}
-};
-
-static const pmu_res_updown_t bcm4330a0_res_updown[] = {
- {
- RES4330_HT_AVAIL, 0x0e02}
-};
-
-static const pmu_res_depend_t bcm4330a0_res_depend[] = {
- /* Just a dummy entry for now */
- {
- PMURES_BIT(RES4330_HT_AVAIL), RES_DEPEND_ADD, 0, NULL}
-};
-
-/* true if the power topology uses the buck boost to provide 3.3V to VDDIO_RF and WLAN PA */
-static bool si_pmu_res_depfltr_bb(si_t *sih)
-{
- return (sih->boardflags & BFL_BUCKBOOST) != 0;
-}
-
-/* true if the power topology doesn't use the cbuck. Key on chiprev also if the chip is BCM4325. */
-static bool si_pmu_res_depfltr_ncb(si_t *sih)
-{
-
- return (sih->boardflags & BFL_NOCBUCK) != 0;
-}
-
-/* true if the power topology uses the PALDO */
-static bool si_pmu_res_depfltr_paldo(si_t *sih)
-{
- return (sih->boardflags & BFL_PALDO) != 0;
-}
-
-/* true if the power topology doesn't use the PALDO */
-static bool si_pmu_res_depfltr_npaldo(si_t *sih)
-{
- return (sih->boardflags & BFL_PALDO) == 0;
-}
-
-#define BCM94325_BBVDDIOSD_BOARDS(sih) (sih->boardtype == BCM94325DEVBU_BOARD || \
- sih->boardtype == BCM94325BGABU_BOARD)
-
-/* Determine min/max rsrc masks. Value 0 leaves hardware at default. */
-static void si_pmu_res_masks(si_t *sih, u32 * pmin, u32 * pmax)
-{
- u32 min_mask = 0, max_mask = 0;
- uint rsrcs;
- char *val;
-
- /* # resources */
- rsrcs = (sih->pmucaps & PCAP_RC_MASK) >> PCAP_RC_SHIFT;
-
- /* determine min/max rsrc masks */
- switch (sih->chip) {
- case BCM43224_CHIP_ID:
- case BCM43225_CHIP_ID:
- case BCM43421_CHIP_ID:
- case BCM43235_CHIP_ID:
- case BCM43236_CHIP_ID:
- case BCM43238_CHIP_ID:
- case BCM4331_CHIP_ID:
- case BCM6362_CHIP_ID:
- /* ??? */
- break;
-
- case BCM4329_CHIP_ID:
- /* 4329 spedific issue. Needs to come back this issue later */
- /* Down to save the power. */
- min_mask =
- PMURES_BIT(RES4329_CBUCK_LPOM) |
- PMURES_BIT(RES4329_CLDO_PU);
- /* Allow (but don't require) PLL to turn on */
- max_mask = 0x3ff63e;
- break;
- case BCM4319_CHIP_ID:
- /* We only need a few resources to be kept on all the time */
- min_mask = PMURES_BIT(RES4319_CBUCK_LPOM) |
- PMURES_BIT(RES4319_CLDO_PU);
-
- /* Allow everything else to be turned on upon requests */
- max_mask = ~(~0 << rsrcs);
- break;
- case BCM4336_CHIP_ID:
- /* Down to save the power. */
- min_mask =
- PMURES_BIT(RES4336_CBUCK_LPOM) | PMURES_BIT(RES4336_CLDO_PU)
- | PMURES_BIT(RES4336_LDO3P3_PU) | PMURES_BIT(RES4336_OTP_PU)
- | PMURES_BIT(RES4336_DIS_INT_RESET_PD);
- /* Allow (but don't require) PLL to turn on */
- max_mask = 0x1ffffff;
- break;
-
- case BCM4330_CHIP_ID:
- /* Down to save the power. */
- min_mask =
- PMURES_BIT(RES4330_CBUCK_LPOM) | PMURES_BIT(RES4330_CLDO_PU)
- | PMURES_BIT(RES4330_DIS_INT_RESET_PD) |
- PMURES_BIT(RES4330_LDO3P3_PU) | PMURES_BIT(RES4330_OTP_PU);
- /* Allow (but don't require) PLL to turn on */
- max_mask = 0xfffffff;
- break;
-
- case BCM4313_CHIP_ID:
- min_mask = PMURES_BIT(RES4313_BB_PU_RSRC) |
- PMURES_BIT(RES4313_XTAL_PU_RSRC) |
- PMURES_BIT(RES4313_ALP_AVAIL_RSRC) |
- PMURES_BIT(RES4313_BB_PLL_PWRSW_RSRC);
- max_mask = 0xffff;
- break;
- default:
- break;
- }
-
- /* Apply nvram override to min mask */
- val = getvar(NULL, "rmin");
- if (val != NULL) {
- PMU_MSG(("Applying rmin=%s to min_mask\n", val));
- min_mask = (u32) simple_strtoul(val, NULL, 0);
- }
- /* Apply nvram override to max mask */
- val = getvar(NULL, "rmax");
- if (val != NULL) {
- PMU_MSG(("Applying rmax=%s to max_mask\n", val));
- max_mask = (u32) simple_strtoul(val, NULL, 0);
- }
-
- *pmin = min_mask;
- *pmax = max_mask;
-}
-
-/* initialize PMU resources */
-void si_pmu_res_init(si_t *sih)
-{
- chipcregs_t *cc;
- uint origidx;
- const pmu_res_updown_t *pmu_res_updown_table = NULL;
- uint pmu_res_updown_table_sz = 0;
- const pmu_res_depend_t *pmu_res_depend_table = NULL;
- uint pmu_res_depend_table_sz = 0;
- u32 min_mask = 0, max_mask = 0;
- char name[8], *val;
- uint i, rsrcs;
-
- ASSERT(sih->cccaps & CC_CAP_PMU);
-
- /* Remember original core before switch to chipc */
- origidx = si_coreidx(sih);
- cc = si_setcoreidx(sih, SI_CC_IDX);
- ASSERT(cc != NULL);
-
- switch (sih->chip) {
- case BCM4329_CHIP_ID:
- /* Optimize resources up/down timers */
- if (ISSIM_ENAB(sih)) {
- pmu_res_updown_table = NULL;
- pmu_res_updown_table_sz = 0;
- } else {
- pmu_res_updown_table = bcm4329_res_updown;
- pmu_res_updown_table_sz = ARRAY_SIZE(bcm4329_res_updown);
- }
- /* Optimize resources dependencies */
- pmu_res_depend_table = bcm4329_res_depend;
- pmu_res_depend_table_sz = ARRAY_SIZE(bcm4329_res_depend);
- break;
-
- case BCM4319_CHIP_ID:
- /* Optimize resources up/down timers */
- if (ISSIM_ENAB(sih)) {
- pmu_res_updown_table = bcm4319a0_res_updown_qt;
- pmu_res_updown_table_sz =
- ARRAY_SIZE(bcm4319a0_res_updown_qt);
- } else {
- pmu_res_updown_table = bcm4319a0_res_updown;
- pmu_res_updown_table_sz =
- ARRAY_SIZE(bcm4319a0_res_updown);
- }
- /* Optimize resources dependancies masks */
- pmu_res_depend_table = bcm4319a0_res_depend;
- pmu_res_depend_table_sz = ARRAY_SIZE(bcm4319a0_res_depend);
- break;
-
- case BCM4336_CHIP_ID:
- /* Optimize resources up/down timers */
- if (ISSIM_ENAB(sih)) {
- pmu_res_updown_table = bcm4336a0_res_updown_qt;
- pmu_res_updown_table_sz =
- ARRAY_SIZE(bcm4336a0_res_updown_qt);
- } else {
- pmu_res_updown_table = bcm4336a0_res_updown;
- pmu_res_updown_table_sz =
- ARRAY_SIZE(bcm4336a0_res_updown);
- }
- /* Optimize resources dependancies masks */
- pmu_res_depend_table = bcm4336a0_res_depend;
- pmu_res_depend_table_sz = ARRAY_SIZE(bcm4336a0_res_depend);
- break;
-
- case BCM4330_CHIP_ID:
- /* Optimize resources up/down timers */
- if (ISSIM_ENAB(sih)) {
- pmu_res_updown_table = bcm4330a0_res_updown_qt;
- pmu_res_updown_table_sz =
- ARRAY_SIZE(bcm4330a0_res_updown_qt);
- } else {
- pmu_res_updown_table = bcm4330a0_res_updown;
- pmu_res_updown_table_sz =
- ARRAY_SIZE(bcm4330a0_res_updown);
- }
- /* Optimize resources dependancies masks */
- pmu_res_depend_table = bcm4330a0_res_depend;
- pmu_res_depend_table_sz = ARRAY_SIZE(bcm4330a0_res_depend);
- break;
-
- default:
- break;
- }
-
- /* # resources */
- rsrcs = (sih->pmucaps & PCAP_RC_MASK) >> PCAP_RC_SHIFT;
-
- /* Program up/down timers */
- while (pmu_res_updown_table_sz--) {
- ASSERT(pmu_res_updown_table != NULL);
- PMU_MSG(("Changing rsrc %d res_updn_timer to 0x%x\n",
- pmu_res_updown_table[pmu_res_updown_table_sz].resnum,
- pmu_res_updown_table[pmu_res_updown_table_sz].updown));
- W_REG(&cc->res_table_sel,
- pmu_res_updown_table[pmu_res_updown_table_sz].resnum);
- W_REG(&cc->res_updn_timer,
- pmu_res_updown_table[pmu_res_updown_table_sz].updown);
- }
- /* Apply nvram overrides to up/down timers */
- for (i = 0; i < rsrcs; i++) {
- snprintf(name, sizeof(name), "r%dt", i);
- val = getvar(NULL, name);
- if (val == NULL)
- continue;
- PMU_MSG(("Applying %s=%s to rsrc %d res_updn_timer\n", name,
- val, i));
- W_REG(&cc->res_table_sel, (u32) i);
- W_REG(&cc->res_updn_timer,
- (u32) simple_strtoul(val, NULL, 0));
- }
-
- /* Program resource dependencies table */
- while (pmu_res_depend_table_sz--) {
- ASSERT(pmu_res_depend_table != NULL);
- if (pmu_res_depend_table[pmu_res_depend_table_sz].filter != NULL
- && !(pmu_res_depend_table[pmu_res_depend_table_sz].
- filter) (sih))
- continue;
- for (i = 0; i < rsrcs; i++) {
- if ((pmu_res_depend_table[pmu_res_depend_table_sz].
- res_mask & PMURES_BIT(i)) == 0)
- continue;
- W_REG(&cc->res_table_sel, i);
- switch (pmu_res_depend_table[pmu_res_depend_table_sz].
- action) {
- case RES_DEPEND_SET:
- PMU_MSG(("Changing rsrc %d res_dep_mask to 0x%x\n", i, pmu_res_depend_table[pmu_res_depend_table_sz].depend_mask));
- W_REG(&cc->res_dep_mask,
- pmu_res_depend_table
- [pmu_res_depend_table_sz].depend_mask);
- break;
- case RES_DEPEND_ADD:
- PMU_MSG(("Adding 0x%x to rsrc %d res_dep_mask\n", pmu_res_depend_table[pmu_res_depend_table_sz].depend_mask, i));
- OR_REG(&cc->res_dep_mask,
- pmu_res_depend_table
- [pmu_res_depend_table_sz].depend_mask);
- break;
- case RES_DEPEND_REMOVE:
- PMU_MSG(("Removing 0x%x from rsrc %d res_dep_mask\n", pmu_res_depend_table[pmu_res_depend_table_sz].depend_mask, i));
- AND_REG(&cc->res_dep_mask,
- ~pmu_res_depend_table
- [pmu_res_depend_table_sz].depend_mask);
- break;
- default:
- ASSERT(0);
- break;
- }
- }
- }
- /* Apply nvram overrides to dependancies masks */
- for (i = 0; i < rsrcs; i++) {
- snprintf(name, sizeof(name), "r%dd", i);
- val = getvar(NULL, name);
- if (val == NULL)
- continue;
- PMU_MSG(("Applying %s=%s to rsrc %d res_dep_mask\n", name, val,
- i));
- W_REG(&cc->res_table_sel, (u32) i);
- W_REG(&cc->res_dep_mask,
- (u32) simple_strtoul(val, NULL, 0));
- }
-
- /* Determine min/max rsrc masks */
- si_pmu_res_masks(sih, &min_mask, &max_mask);
-
- /* It is required to program max_mask first and then min_mask */
-
- /* Program max resource mask */
-
- if (max_mask) {
- PMU_MSG(("Changing max_res_mask to 0x%x\n", max_mask));
- W_REG(&cc->max_res_mask, max_mask);
- }
-
- /* Program min resource mask */
-
- if (min_mask) {
- PMU_MSG(("Changing min_res_mask to 0x%x\n", min_mask));
- W_REG(&cc->min_res_mask, min_mask);
- }
-
- /* Add some delay; allow resources to come up and settle. */
- mdelay(2);
-
- /* Return to original core */
- si_setcoreidx(sih, origidx);
-}
-
-/* setup pll and query clock speed */
-typedef struct {
- u16 freq;
- u8 xf;
- u8 wbint;
- u32 wbfrac;
-} pmu0_xtaltab0_t;
-
-/* the following table is based on 880Mhz fvco */
-static const pmu0_xtaltab0_t pmu0_xtaltab0[] = {
- {
- 12000, 1, 73, 349525}, {
- 13000, 2, 67, 725937}, {
- 14400, 3, 61, 116508}, {
- 15360, 4, 57, 305834}, {
- 16200, 5, 54, 336579}, {
- 16800, 6, 52, 399457}, {
- 19200, 7, 45, 873813}, {
- 19800, 8, 44, 466033}, {
- 20000, 9, 44, 0}, {
- 25000, 10, 70, 419430}, {
- 26000, 11, 67, 725937}, {
- 30000, 12, 58, 699050}, {
- 38400, 13, 45, 873813}, {
- 40000, 14, 45, 0}, {
- 0, 0, 0, 0}
-};
-
-#define PMU0_XTAL0_DEFAULT 8
-
-/* setup pll and query clock speed */
-typedef struct {
- u16 fref;
- u8 xf;
- u8 p1div;
- u8 p2div;
- u8 ndiv_int;
- u32 ndiv_frac;
-} pmu1_xtaltab0_t;
-
-static const pmu1_xtaltab0_t pmu1_xtaltab0_880_4329[] = {
- {
- 12000, 1, 3, 22, 0x9, 0xFFFFEF}, {
- 13000, 2, 1, 6, 0xb, 0x483483}, {
- 14400, 3, 1, 10, 0xa, 0x1C71C7}, {
- 15360, 4, 1, 5, 0xb, 0x755555}, {
- 16200, 5, 1, 10, 0x5, 0x6E9E06}, {
- 16800, 6, 1, 10, 0x5, 0x3Cf3Cf}, {
- 19200, 7, 1, 4, 0xb, 0x755555}, {
- 19800, 8, 1, 11, 0x4, 0xA57EB}, {
- 20000, 9, 1, 11, 0x4, 0x0}, {
- 24000, 10, 3, 11, 0xa, 0x0}, {
- 25000, 11, 5, 16, 0xb, 0x0}, {
- 26000, 12, 1, 1, 0x21, 0xD89D89}, {
- 30000, 13, 3, 8, 0xb, 0x0}, {
- 37400, 14, 3, 1, 0x46, 0x969696}, {
- 38400, 15, 1, 1, 0x16, 0xEAAAAA}, {
- 40000, 16, 1, 2, 0xb, 0}, {
- 0, 0, 0, 0, 0, 0}
-};
-
-/* the following table is based on 880Mhz fvco */
-static const pmu1_xtaltab0_t pmu1_xtaltab0_880[] = {
- {
- 12000, 1, 3, 22, 0x9, 0xFFFFEF}, {
- 13000, 2, 1, 6, 0xb, 0x483483}, {
- 14400, 3, 1, 10, 0xa, 0x1C71C7}, {
- 15360, 4, 1, 5, 0xb, 0x755555}, {
- 16200, 5, 1, 10, 0x5, 0x6E9E06}, {
- 16800, 6, 1, 10, 0x5, 0x3Cf3Cf}, {
- 19200, 7, 1, 4, 0xb, 0x755555}, {
- 19800, 8, 1, 11, 0x4, 0xA57EB}, {
- 20000, 9, 1, 11, 0x4, 0x0}, {
- 24000, 10, 3, 11, 0xa, 0x0}, {
- 25000, 11, 5, 16, 0xb, 0x0}, {
- 26000, 12, 1, 2, 0x10, 0xEC4EC4}, {
- 30000, 13, 3, 8, 0xb, 0x0}, {
- 33600, 14, 1, 2, 0xd, 0x186186}, {
- 38400, 15, 1, 2, 0xb, 0x755555}, {
- 40000, 16, 1, 2, 0xb, 0}, {
- 0, 0, 0, 0, 0, 0}
-};
-
-#define PMU1_XTALTAB0_880_12000K 0
-#define PMU1_XTALTAB0_880_13000K 1
-#define PMU1_XTALTAB0_880_14400K 2
-#define PMU1_XTALTAB0_880_15360K 3
-#define PMU1_XTALTAB0_880_16200K 4
-#define PMU1_XTALTAB0_880_16800K 5
-#define PMU1_XTALTAB0_880_19200K 6
-#define PMU1_XTALTAB0_880_19800K 7
-#define PMU1_XTALTAB0_880_20000K 8
-#define PMU1_XTALTAB0_880_24000K 9
-#define PMU1_XTALTAB0_880_25000K 10
-#define PMU1_XTALTAB0_880_26000K 11
-#define PMU1_XTALTAB0_880_30000K 12
-#define PMU1_XTALTAB0_880_37400K 13
-#define PMU1_XTALTAB0_880_38400K 14
-#define PMU1_XTALTAB0_880_40000K 15
-
-/* the following table is based on 1760Mhz fvco */
-static const pmu1_xtaltab0_t pmu1_xtaltab0_1760[] = {
- {
- 12000, 1, 3, 44, 0x9, 0xFFFFEF}, {
- 13000, 2, 1, 12, 0xb, 0x483483}, {
- 14400, 3, 1, 20, 0xa, 0x1C71C7}, {
- 15360, 4, 1, 10, 0xb, 0x755555}, {
- 16200, 5, 1, 20, 0x5, 0x6E9E06}, {
- 16800, 6, 1, 20, 0x5, 0x3Cf3Cf}, {
- 19200, 7, 1, 18, 0x5, 0x17B425}, {
- 19800, 8, 1, 22, 0x4, 0xA57EB}, {
- 20000, 9, 1, 22, 0x4, 0x0}, {
- 24000, 10, 3, 22, 0xa, 0x0}, {
- 25000, 11, 5, 32, 0xb, 0x0}, {
- 26000, 12, 1, 4, 0x10, 0xEC4EC4}, {
- 30000, 13, 3, 16, 0xb, 0x0}, {
- 38400, 14, 1, 10, 0x4, 0x955555}, {
- 40000, 15, 1, 4, 0xb, 0}, {
- 0, 0, 0, 0, 0, 0}
-};
-
-/* table index */
-#define PMU1_XTALTAB0_1760_12000K 0
-#define PMU1_XTALTAB0_1760_13000K 1
-#define PMU1_XTALTAB0_1760_14400K 2
-#define PMU1_XTALTAB0_1760_15360K 3
-#define PMU1_XTALTAB0_1760_16200K 4
-#define PMU1_XTALTAB0_1760_16800K 5
-#define PMU1_XTALTAB0_1760_19200K 6
-#define PMU1_XTALTAB0_1760_19800K 7
-#define PMU1_XTALTAB0_1760_20000K 8
-#define PMU1_XTALTAB0_1760_24000K 9
-#define PMU1_XTALTAB0_1760_25000K 10
-#define PMU1_XTALTAB0_1760_26000K 11
-#define PMU1_XTALTAB0_1760_30000K 12
-#define PMU1_XTALTAB0_1760_38400K 13
-#define PMU1_XTALTAB0_1760_40000K 14
-
-/* the following table is based on 1440Mhz fvco */
-static const pmu1_xtaltab0_t pmu1_xtaltab0_1440[] = {
- {
- 12000, 1, 1, 1, 0x78, 0x0}, {
- 13000, 2, 1, 1, 0x6E, 0xC4EC4E}, {
- 14400, 3, 1, 1, 0x64, 0x0}, {
- 15360, 4, 1, 1, 0x5D, 0xC00000}, {
- 16200, 5, 1, 1, 0x58, 0xE38E38}, {
- 16800, 6, 1, 1, 0x55, 0xB6DB6D}, {
- 19200, 7, 1, 1, 0x4B, 0}, {
- 19800, 8, 1, 1, 0x48, 0xBA2E8B}, {
- 20000, 9, 1, 1, 0x48, 0x0}, {
- 25000, 10, 1, 1, 0x39, 0x999999}, {
- 26000, 11, 1, 1, 0x37, 0x627627}, {
- 30000, 12, 1, 1, 0x30, 0x0}, {
- 37400, 13, 2, 1, 0x4D, 0x15E76}, {
- 38400, 13, 2, 1, 0x4B, 0x0}, {
- 40000, 14, 2, 1, 0x48, 0x0}, {
- 48000, 15, 2, 1, 0x3c, 0x0}, {
- 0, 0, 0, 0, 0, 0}
-};
-
-/* table index */
-#define PMU1_XTALTAB0_1440_12000K 0
-#define PMU1_XTALTAB0_1440_13000K 1
-#define PMU1_XTALTAB0_1440_14400K 2
-#define PMU1_XTALTAB0_1440_15360K 3
-#define PMU1_XTALTAB0_1440_16200K 4
-#define PMU1_XTALTAB0_1440_16800K 5
-#define PMU1_XTALTAB0_1440_19200K 6
-#define PMU1_XTALTAB0_1440_19800K 7
-#define PMU1_XTALTAB0_1440_20000K 8
-#define PMU1_XTALTAB0_1440_25000K 9
-#define PMU1_XTALTAB0_1440_26000K 10
-#define PMU1_XTALTAB0_1440_30000K 11
-#define PMU1_XTALTAB0_1440_37400K 12
-#define PMU1_XTALTAB0_1440_38400K 13
-#define PMU1_XTALTAB0_1440_40000K 14
-#define PMU1_XTALTAB0_1440_48000K 15
-
-#define XTAL_FREQ_24000MHZ 24000
-#define XTAL_FREQ_30000MHZ 30000
-#define XTAL_FREQ_37400MHZ 37400
-#define XTAL_FREQ_48000MHZ 48000
-
-static const pmu1_xtaltab0_t pmu1_xtaltab0_960[] = {
- {
- 12000, 1, 1, 1, 0x50, 0x0}, {
- 13000, 2, 1, 1, 0x49, 0xD89D89}, {
- 14400, 3, 1, 1, 0x42, 0xAAAAAA}, {
- 15360, 4, 1, 1, 0x3E, 0x800000}, {
- 16200, 5, 1, 1, 0x39, 0x425ED0}, {
- 16800, 6, 1, 1, 0x39, 0x249249}, {
- 19200, 7, 1, 1, 0x32, 0x0}, {
- 19800, 8, 1, 1, 0x30, 0x7C1F07}, {
- 20000, 9, 1, 1, 0x30, 0x0}, {
- 25000, 10, 1, 1, 0x26, 0x666666}, {
- 26000, 11, 1, 1, 0x24, 0xEC4EC4}, {
- 30000, 12, 1, 1, 0x20, 0x0}, {
- 37400, 13, 2, 1, 0x33, 0x563EF9}, {
- 38400, 14, 2, 1, 0x32, 0x0}, {
- 40000, 15, 2, 1, 0x30, 0x0}, {
- 48000, 16, 2, 1, 0x28, 0x0}, {
- 0, 0, 0, 0, 0, 0}
-};
-
-/* table index */
-#define PMU1_XTALTAB0_960_12000K 0
-#define PMU1_XTALTAB0_960_13000K 1
-#define PMU1_XTALTAB0_960_14400K 2
-#define PMU1_XTALTAB0_960_15360K 3
-#define PMU1_XTALTAB0_960_16200K 4
-#define PMU1_XTALTAB0_960_16800K 5
-#define PMU1_XTALTAB0_960_19200K 6
-#define PMU1_XTALTAB0_960_19800K 7
-#define PMU1_XTALTAB0_960_20000K 8
-#define PMU1_XTALTAB0_960_25000K 9
-#define PMU1_XTALTAB0_960_26000K 10
-#define PMU1_XTALTAB0_960_30000K 11
-#define PMU1_XTALTAB0_960_37400K 12
-#define PMU1_XTALTAB0_960_38400K 13
-#define PMU1_XTALTAB0_960_40000K 14
-#define PMU1_XTALTAB0_960_48000K 15
-
-/* select xtal table for each chip */
-static const pmu1_xtaltab0_t *si_pmu1_xtaltab0(si_t *sih)
-{
-#ifdef BCMDBG
- char chn[8];
-#endif
- switch (sih->chip) {
- case BCM4329_CHIP_ID:
- return pmu1_xtaltab0_880_4329;
- case BCM4319_CHIP_ID:
- return pmu1_xtaltab0_1440;
- case BCM4336_CHIP_ID:
- return pmu1_xtaltab0_960;
- case BCM4330_CHIP_ID:
- if (CST4330_CHIPMODE_SDIOD(sih->chipst))
- return pmu1_xtaltab0_960;
- else
- return pmu1_xtaltab0_1440;
- default:
- PMU_MSG(("si_pmu1_xtaltab0: Unknown chipid %s\n",
- bcm_chipname(sih->chip, chn, 8)));
- break;
- }
- ASSERT(0);
- return NULL;
-}
-
-/* select default xtal frequency for each chip */
-static const pmu1_xtaltab0_t *si_pmu1_xtaldef0(si_t *sih)
-{
-#ifdef BCMDBG
- char chn[8];
-#endif
-
- switch (sih->chip) {
- case BCM4329_CHIP_ID:
- /* Default to 38400Khz */
- return &pmu1_xtaltab0_880_4329[PMU1_XTALTAB0_880_38400K];
- case BCM4319_CHIP_ID:
- /* Default to 30000Khz */
- return &pmu1_xtaltab0_1440[PMU1_XTALTAB0_1440_30000K];
- case BCM4336_CHIP_ID:
- /* Default to 26000Khz */
- return &pmu1_xtaltab0_960[PMU1_XTALTAB0_960_26000K];
- case BCM4330_CHIP_ID:
- /* Default to 37400Khz */
- if (CST4330_CHIPMODE_SDIOD(sih->chipst))
- return &pmu1_xtaltab0_960[PMU1_XTALTAB0_960_37400K];
- else
- return &pmu1_xtaltab0_1440[PMU1_XTALTAB0_1440_37400K];
- default:
- PMU_MSG(("si_pmu1_xtaldef0: Unknown chipid %s\n",
- bcm_chipname(sih->chip, chn, 8)));
- break;
- }
- ASSERT(0);
- return NULL;
-}
-
-/* select default pll fvco for each chip */
-static u32 si_pmu1_pllfvco0(si_t *sih)
-{
-#ifdef BCMDBG
- char chn[8];
-#endif
-
- switch (sih->chip) {
- case BCM4329_CHIP_ID:
- return FVCO_880;
- case BCM4319_CHIP_ID:
- return FVCO_1440;
- case BCM4336_CHIP_ID:
- return FVCO_960;
- case BCM4330_CHIP_ID:
- if (CST4330_CHIPMODE_SDIOD(sih->chipst))
- return FVCO_960;
- else
- return FVCO_1440;
- default:
- PMU_MSG(("si_pmu1_pllfvco0: Unknown chipid %s\n",
- bcm_chipname(sih->chip, chn, 8)));
- break;
- }
- ASSERT(0);
- return 0;
-}
-
-/* query alp/xtal clock frequency */
-static u32
-si_pmu1_alpclk0(si_t *sih, chipcregs_t *cc)
-{
- const pmu1_xtaltab0_t *xt;
- u32 xf;
-
- /* Find the frequency in the table */
- xf = (R_REG(&cc->pmucontrol) & PCTL_XTALFREQ_MASK) >>
- PCTL_XTALFREQ_SHIFT;
- for (xt = si_pmu1_xtaltab0(sih); xt != NULL && xt->fref != 0; xt++)
- if (xt->xf == xf)
- break;
- /* Could not find it so assign a default value */
- if (xt == NULL || xt->fref == 0)
- xt = si_pmu1_xtaldef0(sih);
- ASSERT(xt != NULL && xt->fref != 0);
-
- return xt->fref * 1000;
-}
-
-/* Set up PLL registers in the PMU as per the crystal speed.
- * XtalFreq field in pmucontrol register being 0 indicates the PLL
- * is not programmed and the h/w default is assumed to work, in which
- * case the xtal frequency is unknown to the s/w so we need to call
- * si_pmu1_xtaldef0() wherever it is needed to return a default value.
- */
-static void si_pmu1_pllinit0(si_t *sih, chipcregs_t *cc, u32 xtal)
-{
- const pmu1_xtaltab0_t *xt;
- u32 tmp;
- u32 buf_strength = 0;
- u8 ndiv_mode = 1;
-
- /* Use h/w default PLL config */
- if (xtal == 0) {
- PMU_MSG(("Unspecified xtal frequency, skip PLL configuration\n"));
- return;
- }
-
- /* Find the frequency in the table */
- for (xt = si_pmu1_xtaltab0(sih); xt != NULL && xt->fref != 0; xt++)
- if (xt->fref == xtal)
- break;
-
- /* Check current PLL state, bail out if it has been programmed or
- * we don't know how to program it.
- */
- if (xt == NULL || xt->fref == 0) {
- PMU_MSG(("Unsupported xtal frequency %d.%d MHz, skip PLL configuration\n", xtal / 1000, xtal % 1000));
- return;
- }
- /* for 4319 bootloader already programs the PLL but bootloader does not program the
- PLL4 and PLL5. So Skip this check for 4319
- */
- if ((((R_REG(&cc->pmucontrol) & PCTL_XTALFREQ_MASK) >>
- PCTL_XTALFREQ_SHIFT) == xt->xf) &&
- !((sih->chip == BCM4319_CHIP_ID)
- || (sih->chip == BCM4330_CHIP_ID))) {
- PMU_MSG(("PLL already programmed for %d.%d MHz\n",
- xt->fref / 1000, xt->fref % 1000));
- return;
- }
-
- PMU_MSG(("XTAL %d.%d MHz (%d)\n", xtal / 1000, xtal % 1000, xt->xf));
- PMU_MSG(("Programming PLL for %d.%d MHz\n", xt->fref / 1000,
- xt->fref % 1000));
-
- switch (sih->chip) {
- case BCM4329_CHIP_ID:
- /* Change the BBPLL drive strength to 8 for all channels */
- buf_strength = 0x888888;
- AND_REG(&cc->min_res_mask,
- ~(PMURES_BIT(RES4329_BBPLL_PWRSW_PU) |
- PMURES_BIT(RES4329_HT_AVAIL)));
- AND_REG(&cc->max_res_mask,
- ~(PMURES_BIT(RES4329_BBPLL_PWRSW_PU) |
- PMURES_BIT(RES4329_HT_AVAIL)));
- SPINWAIT(R_REG(&cc->clk_ctl_st) & CCS_HTAVAIL,
- PMU_MAX_TRANSITION_DLY);
- ASSERT(!(R_REG(&cc->clk_ctl_st) & CCS_HTAVAIL));
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
- if (xt->fref == 38400)
- tmp = 0x200024C0;
- else if (xt->fref == 37400)
- tmp = 0x20004500;
- else if (xt->fref == 26000)
- tmp = 0x200024C0;
- else
- tmp = 0x200005C0; /* Chip Dflt Settings */
- W_REG(&cc->pllcontrol_data, tmp);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
- tmp =
- R_REG(&cc->pllcontrol_data) & PMU1_PLL0_PC5_CLK_DRV_MASK;
- if ((xt->fref == 38400) || (xt->fref == 37400)
- || (xt->fref == 26000))
- tmp |= 0x15;
- else
- tmp |= 0x25; /* Chip Dflt Settings */
- W_REG(&cc->pllcontrol_data, tmp);
- break;
-
- case BCM4319_CHIP_ID:
- /* Change the BBPLL drive strength to 2 for all channels */
- buf_strength = 0x222222;
-
- /* Make sure the PLL is off */
- /* WAR65104: Disable the HT_AVAIL resource first and then
- * after a delay (more than downtime for HT_AVAIL) remove the
- * BBPLL resource; backplane clock moves to ALP from HT.
- */
- AND_REG(&cc->min_res_mask,
- ~(PMURES_BIT(RES4319_HT_AVAIL)));
- AND_REG(&cc->max_res_mask,
- ~(PMURES_BIT(RES4319_HT_AVAIL)));
-
- udelay(100);
- AND_REG(&cc->min_res_mask,
- ~(PMURES_BIT(RES4319_BBPLL_PWRSW_PU)));
- AND_REG(&cc->max_res_mask,
- ~(PMURES_BIT(RES4319_BBPLL_PWRSW_PU)));
-
- udelay(100);
- SPINWAIT(R_REG(&cc->clk_ctl_st) & CCS_HTAVAIL,
- PMU_MAX_TRANSITION_DLY);
- ASSERT(!(R_REG(&cc->clk_ctl_st) & CCS_HTAVAIL));
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
- tmp = 0x200005c0;
- W_REG(&cc->pllcontrol_data, tmp);
- break;
-
- case BCM4336_CHIP_ID:
- AND_REG(&cc->min_res_mask,
- ~(PMURES_BIT(RES4336_HT_AVAIL) |
- PMURES_BIT(RES4336_MACPHY_CLKAVAIL)));
- AND_REG(&cc->max_res_mask,
- ~(PMURES_BIT(RES4336_HT_AVAIL) |
- PMURES_BIT(RES4336_MACPHY_CLKAVAIL)));
- udelay(100);
- SPINWAIT(R_REG(&cc->clk_ctl_st) & CCS_HTAVAIL,
- PMU_MAX_TRANSITION_DLY);
- ASSERT(!(R_REG(&cc->clk_ctl_st) & CCS_HTAVAIL));
- break;
-
- case BCM4330_CHIP_ID:
- AND_REG(&cc->min_res_mask,
- ~(PMURES_BIT(RES4330_HT_AVAIL) |
- PMURES_BIT(RES4330_MACPHY_CLKAVAIL)));
- AND_REG(&cc->max_res_mask,
- ~(PMURES_BIT(RES4330_HT_AVAIL) |
- PMURES_BIT(RES4330_MACPHY_CLKAVAIL)));
- udelay(100);
- SPINWAIT(R_REG(&cc->clk_ctl_st) & CCS_HTAVAIL,
- PMU_MAX_TRANSITION_DLY);
- ASSERT(!(R_REG(&cc->clk_ctl_st) & CCS_HTAVAIL));
- break;
-
- default:
- ASSERT(0);
- }
-
- PMU_MSG(("Done masking\n"));
-
- /* Write p1div and p2div to pllcontrol[0] */
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
- tmp = R_REG(&cc->pllcontrol_data) &
- ~(PMU1_PLL0_PC0_P1DIV_MASK | PMU1_PLL0_PC0_P2DIV_MASK);
- tmp |=
- ((xt->
- p1div << PMU1_PLL0_PC0_P1DIV_SHIFT) & PMU1_PLL0_PC0_P1DIV_MASK) |
- ((xt->
- p2div << PMU1_PLL0_PC0_P2DIV_SHIFT) & PMU1_PLL0_PC0_P2DIV_MASK);
- W_REG(&cc->pllcontrol_data, tmp);
-
- if ((sih->chip == BCM4330_CHIP_ID))
- si_pmu_set_4330_plldivs(sih);
-
- if ((sih->chip == BCM4329_CHIP_ID)
- && (sih->chiprev == 0)) {
-
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
- tmp = R_REG(&cc->pllcontrol_data);
- tmp = tmp & (~DOT11MAC_880MHZ_CLK_DIVISOR_MASK);
- tmp = tmp | DOT11MAC_880MHZ_CLK_DIVISOR_VAL;
- W_REG(&cc->pllcontrol_data, tmp);
- }
- if ((sih->chip == BCM4319_CHIP_ID) ||
- (sih->chip == BCM4336_CHIP_ID) ||
- (sih->chip == BCM4330_CHIP_ID))
- ndiv_mode = PMU1_PLL0_PC2_NDIV_MODE_MFB;
- else
- ndiv_mode = PMU1_PLL0_PC2_NDIV_MODE_MASH;
-
- /* Write ndiv_int and ndiv_mode to pllcontrol[2] */
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
- tmp = R_REG(&cc->pllcontrol_data) &
- ~(PMU1_PLL0_PC2_NDIV_INT_MASK | PMU1_PLL0_PC2_NDIV_MODE_MASK);
- tmp |=
- ((xt->
- ndiv_int << PMU1_PLL0_PC2_NDIV_INT_SHIFT) &
- PMU1_PLL0_PC2_NDIV_INT_MASK) | ((ndiv_mode <<
- PMU1_PLL0_PC2_NDIV_MODE_SHIFT) &
- PMU1_PLL0_PC2_NDIV_MODE_MASK);
- W_REG(&cc->pllcontrol_data, tmp);
-
- /* Write ndiv_frac to pllcontrol[3] */
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
- tmp = R_REG(&cc->pllcontrol_data) & ~PMU1_PLL0_PC3_NDIV_FRAC_MASK;
- tmp |= ((xt->ndiv_frac << PMU1_PLL0_PC3_NDIV_FRAC_SHIFT) &
- PMU1_PLL0_PC3_NDIV_FRAC_MASK);
- W_REG(&cc->pllcontrol_data, tmp);
-
- /* Write clock driving strength to pllcontrol[5] */
- if (buf_strength) {
- PMU_MSG(("Adjusting PLL buffer drive strength: %x\n",
- buf_strength));
-
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
- tmp =
- R_REG(&cc->pllcontrol_data) & ~PMU1_PLL0_PC5_CLK_DRV_MASK;
- tmp |= (buf_strength << PMU1_PLL0_PC5_CLK_DRV_SHIFT);
- W_REG(&cc->pllcontrol_data, tmp);
- }
-
- PMU_MSG(("Done pll\n"));
-
- /* to operate the 4319 usb in 24MHz/48MHz; chipcontrol[2][84:83] needs
- * to be updated.
- */
- if ((sih->chip == BCM4319_CHIP_ID)
- && (xt->fref != XTAL_FREQ_30000MHZ)) {
- W_REG(&cc->chipcontrol_addr, PMU1_PLL0_CHIPCTL2);
- tmp =
- R_REG(&cc->chipcontrol_data) & ~CCTL_4319USB_XTAL_SEL_MASK;
- if (xt->fref == XTAL_FREQ_24000MHZ) {
- tmp |=
- (CCTL_4319USB_24MHZ_PLL_SEL <<
- CCTL_4319USB_XTAL_SEL_SHIFT);
- } else if (xt->fref == XTAL_FREQ_48000MHZ) {
- tmp |=
- (CCTL_4319USB_48MHZ_PLL_SEL <<
- CCTL_4319USB_XTAL_SEL_SHIFT);
- }
- W_REG(&cc->chipcontrol_data, tmp);
- }
-
- /* Flush deferred pll control registers writes */
- if (sih->pmurev >= 2)
- OR_REG(&cc->pmucontrol, PCTL_PLL_PLLCTL_UPD);
-
- /* Write XtalFreq. Set the divisor also. */
- tmp = R_REG(&cc->pmucontrol) &
- ~(PCTL_ILP_DIV_MASK | PCTL_XTALFREQ_MASK);
- tmp |= (((((xt->fref + 127) / 128) - 1) << PCTL_ILP_DIV_SHIFT) &
- PCTL_ILP_DIV_MASK) |
- ((xt->xf << PCTL_XTALFREQ_SHIFT) & PCTL_XTALFREQ_MASK);
-
- if ((sih->chip == BCM4329_CHIP_ID)
- && sih->chiprev == 0) {
- /* clear the htstretch before clearing HTReqEn */
- AND_REG(&cc->clkstretch, ~CSTRETCH_HT);
- tmp &= ~PCTL_HT_REQ_EN;
- }
-
- W_REG(&cc->pmucontrol, tmp);
-}
-
-/* query the CPU clock frequency */
-static u32
-si_pmu1_cpuclk0(si_t *sih, chipcregs_t *cc)
-{
- u32 tmp, m1div;
-#ifdef BCMDBG
- u32 ndiv_int, ndiv_frac, p2div, p1div, fvco;
- u32 fref;
-#endif
- u32 FVCO = si_pmu1_pllfvco0(sih);
-
- /* Read m1div from pllcontrol[1] */
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
- tmp = R_REG(&cc->pllcontrol_data);
- m1div = (tmp & PMU1_PLL0_PC1_M1DIV_MASK) >> PMU1_PLL0_PC1_M1DIV_SHIFT;
-
-#ifdef BCMDBG
- /* Read p2div/p1div from pllcontrol[0] */
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
- tmp = R_REG(&cc->pllcontrol_data);
- p2div = (tmp & PMU1_PLL0_PC0_P2DIV_MASK) >> PMU1_PLL0_PC0_P2DIV_SHIFT;
- p1div = (tmp & PMU1_PLL0_PC0_P1DIV_MASK) >> PMU1_PLL0_PC0_P1DIV_SHIFT;
-
- /* Calculate fvco based on xtal freq and ndiv and pdiv */
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
- tmp = R_REG(&cc->pllcontrol_data);
- ndiv_int =
- (tmp & PMU1_PLL0_PC2_NDIV_INT_MASK) >> PMU1_PLL0_PC2_NDIV_INT_SHIFT;
-
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
- tmp = R_REG(&cc->pllcontrol_data);
- ndiv_frac =
- (tmp & PMU1_PLL0_PC3_NDIV_FRAC_MASK) >>
- PMU1_PLL0_PC3_NDIV_FRAC_SHIFT;
-
- fref = si_pmu1_alpclk0(sih, cc) / 1000;
-
- fvco = (fref * ndiv_int) << 8;
- fvco += (fref * (ndiv_frac >> 12)) >> 4;
- fvco += (fref * (ndiv_frac & 0xfff)) >> 12;
- fvco >>= 8;
- fvco *= p2div;
- fvco /= p1div;
- fvco /= 1000;
- fvco *= 1000;
-
- PMU_MSG(("si_pmu1_cpuclk0: ndiv_int %u ndiv_frac %u p2div %u p1div %u fvco %u\n", ndiv_int, ndiv_frac, p2div, p1div, fvco));
-
- FVCO = fvco;
-#endif /* BCMDBG */
-
- /* Return ARM/SB clock */
- return FVCO / m1div * 1000;
-}
-
-/* initialize PLL */
-void si_pmu_pll_init(si_t *sih, uint xtalfreq)
-{
- chipcregs_t *cc;
- uint origidx;
-#ifdef BCMDBG
- char chn[8];
-#endif
-
- ASSERT(sih->cccaps & CC_CAP_PMU);
-
- /* Remember original core before switch to chipc */
- origidx = si_coreidx(sih);
- cc = si_setcoreidx(sih, SI_CC_IDX);
- ASSERT(cc != NULL);
-
- switch (sih->chip) {
- case BCM4329_CHIP_ID:
- if (xtalfreq == 0)
- xtalfreq = 38400;
- si_pmu1_pllinit0(sih, cc, xtalfreq);
- break;
- case BCM4313_CHIP_ID:
- case BCM43224_CHIP_ID:
- case BCM43225_CHIP_ID:
- case BCM43421_CHIP_ID:
- case BCM43235_CHIP_ID:
- case BCM43236_CHIP_ID:
- case BCM43238_CHIP_ID:
- case BCM4331_CHIP_ID:
- case BCM6362_CHIP_ID:
- /* ??? */
- break;
- case BCM4319_CHIP_ID:
- case BCM4336_CHIP_ID:
- case BCM4330_CHIP_ID:
- si_pmu1_pllinit0(sih, cc, xtalfreq);
- break;
- default:
- PMU_MSG(("No PLL init done for chip %s rev %d pmurev %d\n",
- bcm_chipname(sih->chip, chn, 8), sih->chiprev,
- sih->pmurev));
- break;
- }
-
-#ifdef BCMDBG_FORCEHT
- OR_REG(&cc->clk_ctl_st, CCS_FORCEHT);
-#endif
-
- /* Return to original core */
- si_setcoreidx(sih, origidx);
-}
-
-/* query alp/xtal clock frequency */
-u32 si_pmu_alp_clock(si_t *sih)
-{
- chipcregs_t *cc;
- uint origidx;
- u32 clock = ALP_CLOCK;
-#ifdef BCMDBG
- char chn[8];
-#endif
-
- ASSERT(sih->cccaps & CC_CAP_PMU);
-
- /* Remember original core before switch to chipc */
- origidx = si_coreidx(sih);
- cc = si_setcoreidx(sih, SI_CC_IDX);
- ASSERT(cc != NULL);
-
- switch (sih->chip) {
- case BCM43224_CHIP_ID:
- case BCM43225_CHIP_ID:
- case BCM43421_CHIP_ID:
- case BCM43235_CHIP_ID:
- case BCM43236_CHIP_ID:
- case BCM43238_CHIP_ID:
- case BCM4331_CHIP_ID:
- case BCM6362_CHIP_ID:
- case BCM4716_CHIP_ID:
- case BCM4748_CHIP_ID:
- case BCM47162_CHIP_ID:
- case BCM4313_CHIP_ID:
- case BCM5357_CHIP_ID:
- /* always 20Mhz */
- clock = 20000 * 1000;
- break;
- case BCM4329_CHIP_ID:
- case BCM4319_CHIP_ID:
- case BCM4336_CHIP_ID:
- case BCM4330_CHIP_ID:
-
- clock = si_pmu1_alpclk0(sih, cc);
- break;
- case BCM5356_CHIP_ID:
- /* always 25Mhz */
- clock = 25000 * 1000;
- break;
- default:
- PMU_MSG(("No ALP clock specified "
- "for chip %s rev %d pmurev %d, using default %d Hz\n",
- bcm_chipname(sih->chip, chn, 8), sih->chiprev,
- sih->pmurev, clock));
- break;
- }
-
- /* Return to original core */
- si_setcoreidx(sih, origidx);
- return clock;
-}
-
-/* Find the output of the "m" pll divider given pll controls that start with
- * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
- */
-static u32
-si_pmu5_clock(si_t *sih, chipcregs_t *cc, uint pll0, uint m) {
- u32 tmp, div, ndiv, p1, p2, fc;
-
- if ((pll0 & 3) || (pll0 > PMU4716_MAINPLL_PLL0)) {
- PMU_ERROR(("%s: Bad pll0: %d\n", __func__, pll0));
- return 0;
- }
-
- /* Strictly there is an m5 divider, but I'm not sure we use it */
- if ((m == 0) || (m > 4)) {
- PMU_ERROR(("%s: Bad m divider: %d\n", __func__, m));
- return 0;
- }
-
- if (sih->chip == BCM5357_CHIP_ID) {
- /* Detect failure in clock setting */
- if ((R_REG(&cc->chipstatus) & 0x40000) != 0)
- return 133 * 1000000;
- }
-
- W_REG(&cc->pllcontrol_addr, pll0 + PMU5_PLL_P1P2_OFF);
- (void)R_REG(&cc->pllcontrol_addr);
- tmp = R_REG(&cc->pllcontrol_data);
- p1 = (tmp & PMU5_PLL_P1_MASK) >> PMU5_PLL_P1_SHIFT;
- p2 = (tmp & PMU5_PLL_P2_MASK) >> PMU5_PLL_P2_SHIFT;
-
- W_REG(&cc->pllcontrol_addr, pll0 + PMU5_PLL_M14_OFF);
- (void)R_REG(&cc->pllcontrol_addr);
- tmp = R_REG(&cc->pllcontrol_data);
- div = (tmp >> ((m - 1) * PMU5_PLL_MDIV_WIDTH)) & PMU5_PLL_MDIV_MASK;
-
- W_REG(&cc->pllcontrol_addr, pll0 + PMU5_PLL_NM5_OFF);
- (void)R_REG(&cc->pllcontrol_addr);
- tmp = R_REG(&cc->pllcontrol_data);
- ndiv = (tmp & PMU5_PLL_NDIV_MASK) >> PMU5_PLL_NDIV_SHIFT;
-
- /* Do calculation in Mhz */
- fc = si_pmu_alp_clock(sih) / 1000000;
- fc = (p1 * ndiv * fc) / p2;
-
- PMU_NONE(("%s: p1=%d, p2=%d, ndiv=%d(0x%x), m%d=%d; fc=%d, clock=%d\n",
- __func__, p1, p2, ndiv, ndiv, m, div, fc, fc / div));
-
- /* Return clock in Hertz */
- return (fc / div) * 1000000;
-}
-
-/* query backplane clock frequency */
-/* For designs that feed the same clock to both backplane
- * and CPU just return the CPU clock speed.
- */
-u32 si_pmu_si_clock(si_t *sih)
-{
- chipcregs_t *cc;
- uint origidx;
- u32 clock = HT_CLOCK;
-#ifdef BCMDBG
- char chn[8];
-#endif
-
- ASSERT(sih->cccaps & CC_CAP_PMU);
-
- /* Remember original core before switch to chipc */
- origidx = si_coreidx(sih);
- cc = si_setcoreidx(sih, SI_CC_IDX);
- ASSERT(cc != NULL);
-
- switch (sih->chip) {
- case BCM43224_CHIP_ID:
- case BCM43225_CHIP_ID:
- case BCM43421_CHIP_ID:
- case BCM4331_CHIP_ID:
- case BCM6362_CHIP_ID:
- /* 96MHz backplane clock */
- clock = 96000 * 1000;
- break;
- case BCM4716_CHIP_ID:
- case BCM4748_CHIP_ID:
- case BCM47162_CHIP_ID:
- clock =
- si_pmu5_clock(sih, cc, PMU4716_MAINPLL_PLL0,
- PMU5_MAINPLL_SI);
- break;
- case BCM4329_CHIP_ID:
- if (sih->chiprev == 0)
- clock = 38400 * 1000;
- else
- clock = si_pmu1_cpuclk0(sih, cc);
- break;
- case BCM4319_CHIP_ID:
- case BCM4336_CHIP_ID:
- case BCM4330_CHIP_ID:
- clock = si_pmu1_cpuclk0(sih, cc);
- break;
- case BCM4313_CHIP_ID:
- /* 80MHz backplane clock */
- clock = 80000 * 1000;
- break;
- case BCM43235_CHIP_ID:
- case BCM43236_CHIP_ID:
- case BCM43238_CHIP_ID:
- clock =
- (cc->chipstatus & CST43236_BP_CLK) ? (120000 *
- 1000) : (96000 *
- 1000);
- break;
- case BCM5356_CHIP_ID:
- clock =
- si_pmu5_clock(sih, cc, PMU5356_MAINPLL_PLL0,
- PMU5_MAINPLL_SI);
- break;
- case BCM5357_CHIP_ID:
- clock =
- si_pmu5_clock(sih, cc, PMU5357_MAINPLL_PLL0,
- PMU5_MAINPLL_SI);
- break;
- default:
- PMU_MSG(("No backplane clock specified "
- "for chip %s rev %d pmurev %d, using default %d Hz\n",
- bcm_chipname(sih->chip, chn, 8), sih->chiprev,
- sih->pmurev, clock));
- break;
- }
-
- /* Return to original core */
- si_setcoreidx(sih, origidx);
- return clock;
-}
-
-/* query CPU clock frequency */
-u32 si_pmu_cpu_clock(si_t *sih)
-{
- chipcregs_t *cc;
- uint origidx;
- u32 clock;
-
- ASSERT(sih->cccaps & CC_CAP_PMU);
-
- if ((sih->pmurev >= 5) &&
- !((sih->chip == BCM4329_CHIP_ID) ||
- (sih->chip == BCM4319_CHIP_ID) ||
- (sih->chip == BCM43236_CHIP_ID) ||
- (sih->chip == BCM4336_CHIP_ID) ||
- (sih->chip == BCM4330_CHIP_ID))) {
- uint pll;
-
- switch (sih->chip) {
- case BCM5356_CHIP_ID:
- pll = PMU5356_MAINPLL_PLL0;
- break;
- case BCM5357_CHIP_ID:
- pll = PMU5357_MAINPLL_PLL0;
- break;
- default:
- pll = PMU4716_MAINPLL_PLL0;
- break;
- }
-
- /* Remember original core before switch to chipc */
- origidx = si_coreidx(sih);
- cc = si_setcoreidx(sih, SI_CC_IDX);
- ASSERT(cc != NULL);
-
- clock = si_pmu5_clock(sih, cc, pll, PMU5_MAINPLL_CPU);
-
- /* Return to original core */
- si_setcoreidx(sih, origidx);
- } else
- clock = si_pmu_si_clock(sih);
-
- return clock;
-}
-
-/* query memory clock frequency */
-u32 si_pmu_mem_clock(si_t *sih)
-{
- chipcregs_t *cc;
- uint origidx;
- u32 clock;
-
- ASSERT(sih->cccaps & CC_CAP_PMU);
-
- if ((sih->pmurev >= 5) &&
- !((sih->chip == BCM4329_CHIP_ID) ||
- (sih->chip == BCM4319_CHIP_ID) ||
- (sih->chip == BCM4330_CHIP_ID) ||
- (sih->chip == BCM4336_CHIP_ID) ||
- (sih->chip == BCM43236_CHIP_ID))) {
- uint pll;
-
- switch (sih->chip) {
- case BCM5356_CHIP_ID:
- pll = PMU5356_MAINPLL_PLL0;
- break;
- case BCM5357_CHIP_ID:
- pll = PMU5357_MAINPLL_PLL0;
- break;
- default:
- pll = PMU4716_MAINPLL_PLL0;
- break;
- }
-
- /* Remember original core before switch to chipc */
- origidx = si_coreidx(sih);
- cc = si_setcoreidx(sih, SI_CC_IDX);
- ASSERT(cc != NULL);
-
- clock = si_pmu5_clock(sih, cc, pll, PMU5_MAINPLL_MEM);
-
- /* Return to original core */
- si_setcoreidx(sih, origidx);
- } else {
- clock = si_pmu_si_clock(sih);
- }
-
- return clock;
-}
-
-/* Measure ILP clock frequency */
-#define ILP_CALC_DUR 10 /* ms, make sure 1000 can be divided by it. */
-
-static u32 ilpcycles_per_sec;
-
-u32 si_pmu_ilp_clock(si_t *sih)
-{
- if (ISSIM_ENAB(sih))
- return ILP_CLOCK;
-
- if (ilpcycles_per_sec == 0) {
- u32 start, end, delta;
- u32 origidx = si_coreidx(sih);
- chipcregs_t *cc = si_setcoreidx(sih, SI_CC_IDX);
- ASSERT(cc != NULL);
- start = R_REG(&cc->pmutimer);
- mdelay(ILP_CALC_DUR);
- end = R_REG(&cc->pmutimer);
- delta = end - start;
- ilpcycles_per_sec = delta * (1000 / ILP_CALC_DUR);
- si_setcoreidx(sih, origidx);
- }
-
- return ilpcycles_per_sec;
-}
-
-/* SDIO Pad drive strength to select value mappings */
-typedef struct {
- u8 strength; /* Pad Drive Strength in mA */
- u8 sel; /* Chip-specific select value */
-} sdiod_drive_str_t;
-
-/* SDIO Drive Strength to sel value table for PMU Rev 1 */
-static const sdiod_drive_str_t sdiod_drive_strength_tab1[] = {
- {
- 4, 0x2}, {
- 2, 0x3}, {
- 1, 0x0}, {
- 0, 0x0}
- };
-
-/* SDIO Drive Strength to sel value table for PMU Rev 2, 3 */
-static const sdiod_drive_str_t sdiod_drive_strength_tab2[] = {
- {
- 12, 0x7}, {
- 10, 0x6}, {
- 8, 0x5}, {
- 6, 0x4}, {
- 4, 0x2}, {
- 2, 0x1}, {
- 0, 0x0}
- };
-
-/* SDIO Drive Strength to sel value table for PMU Rev 8 (1.8V) */
-static const sdiod_drive_str_t sdiod_drive_strength_tab3[] = {
- {
- 32, 0x7}, {
- 26, 0x6}, {
- 22, 0x5}, {
- 16, 0x4}, {
- 12, 0x3}, {
- 8, 0x2}, {
- 4, 0x1}, {
- 0, 0x0}
- };
-
-#define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu))
-
-void
-si_sdiod_drive_strength_init(si_t *sih, u32 drivestrength) {
- chipcregs_t *cc;
- uint origidx, intr_val = 0;
- sdiod_drive_str_t *str_tab = NULL;
- u32 str_mask = 0;
- u32 str_shift = 0;
-#ifdef BCMDBG
- char chn[8];
-#endif
-
- if (!(sih->cccaps & CC_CAP_PMU)) {
- return;
- }
-
- /* Remember original core before switch to chipc */
- cc = (chipcregs_t *) si_switch_core(sih, CC_CORE_ID, &origidx,
- &intr_val);
-
- switch (SDIOD_DRVSTR_KEY(sih->chip, sih->pmurev)) {
- case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 1):
- str_tab = (sdiod_drive_str_t *)&sdiod_drive_strength_tab1;
- str_mask = 0x30000000;
- str_shift = 28;
- break;
- case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 2):
- case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 3):
- str_tab = (sdiod_drive_str_t *)&sdiod_drive_strength_tab2;
- str_mask = 0x00003800;
- str_shift = 11;
- break;
- case SDIOD_DRVSTR_KEY(BCM4336_CHIP_ID, 8):
- str_tab = (sdiod_drive_str_t *) &sdiod_drive_strength_tab3;
- str_mask = 0x00003800;
- str_shift = 11;
- break;
-
- default:
- PMU_MSG(("No SDIO Drive strength init done for chip %s rev %d pmurev %d\n", bcm_chipname(sih->chip, chn, 8), sih->chiprev, sih->pmurev));
-
- break;
- }
-
- if (str_tab != NULL) {
- u32 drivestrength_sel = 0;
- u32 cc_data_temp;
- int i;
-
- for (i = 0; str_tab[i].strength != 0; i++) {
- if (drivestrength >= str_tab[i].strength) {
- drivestrength_sel = str_tab[i].sel;
- break;
- }
- }
-
- W_REG(&cc->chipcontrol_addr, 1);
- cc_data_temp = R_REG(&cc->chipcontrol_data);
- cc_data_temp &= ~str_mask;
- drivestrength_sel <<= str_shift;
- cc_data_temp |= drivestrength_sel;
- W_REG(&cc->chipcontrol_data, cc_data_temp);
-
- PMU_MSG(("SDIO: %dmA drive strength selected, set to 0x%08x\n",
- drivestrength, cc_data_temp));
- }
-
- /* Return to original core */
- si_restore_core(sih, origidx, intr_val);
-}
-
-/* initialize PMU */
-void si_pmu_init(si_t *sih)
-{
- chipcregs_t *cc;
- uint origidx;
-
- ASSERT(sih->cccaps & CC_CAP_PMU);
-
- /* Remember original core before switch to chipc */
- origidx = si_coreidx(sih);
- cc = si_setcoreidx(sih, SI_CC_IDX);
- ASSERT(cc != NULL);
-
- if (sih->pmurev == 1)
- AND_REG(&cc->pmucontrol, ~PCTL_NOILP_ON_WAIT);
- else if (sih->pmurev >= 2)
- OR_REG(&cc->pmucontrol, PCTL_NOILP_ON_WAIT);
-
- if ((sih->chip == BCM4329_CHIP_ID) && (sih->chiprev == 2)) {
- /* Fix for 4329b0 bad LPOM state. */
- W_REG(&cc->regcontrol_addr, 2);
- OR_REG(&cc->regcontrol_data, 0x100);
-
- W_REG(&cc->regcontrol_addr, 3);
- OR_REG(&cc->regcontrol_data, 0x4);
- }
-
- /* Return to original core */
- si_setcoreidx(sih, origidx);
-}
-
-/* Return up time in ILP cycles for the given resource. */
-static uint
-si_pmu_res_uptime(si_t *sih, chipcregs_t *cc, u8 rsrc) {
- u32 deps;
- uint up, i, dup, dmax;
- u32 min_mask = 0, max_mask = 0;
-
- /* uptime of resource 'rsrc' */
- W_REG(&cc->res_table_sel, rsrc);
- up = (R_REG(&cc->res_updn_timer) >> 8) & 0xff;
-
- /* direct dependancies of resource 'rsrc' */
- deps = si_pmu_res_deps(sih, cc, PMURES_BIT(rsrc), false);
- for (i = 0; i <= PMURES_MAX_RESNUM; i++) {
- if (!(deps & PMURES_BIT(i)))
- continue;
- deps &= ~si_pmu_res_deps(sih, cc, PMURES_BIT(i), true);
- }
- si_pmu_res_masks(sih, &min_mask, &max_mask);
- deps &= ~min_mask;
-
- /* max uptime of direct dependancies */
- dmax = 0;
- for (i = 0; i <= PMURES_MAX_RESNUM; i++) {
- if (!(deps & PMURES_BIT(i)))
- continue;
- dup = si_pmu_res_uptime(sih, cc, (u8) i);
- if (dmax < dup)
- dmax = dup;
- }
-
- PMU_MSG(("si_pmu_res_uptime: rsrc %u uptime %u(deps 0x%08x uptime %u)\n", rsrc, up, deps, dmax));
-
- return up + dmax + PMURES_UP_TRANSITION;
-}
-
-/* Return dependancies (direct or all/indirect) for the given resources */
-static u32
-si_pmu_res_deps(si_t *sih, chipcregs_t *cc, u32 rsrcs,
- bool all)
-{
- u32 deps = 0;
- u32 i;
-
- for (i = 0; i <= PMURES_MAX_RESNUM; i++) {
- if (!(rsrcs & PMURES_BIT(i)))
- continue;
- W_REG(&cc->res_table_sel, i);
- deps |= R_REG(&cc->res_dep_mask);
- }
-
- return !all ? deps : (deps
- ? (deps |
- si_pmu_res_deps(sih, cc, deps,
- true)) : 0);
-}
-
-/* power up/down OTP through PMU resources */
-void si_pmu_otp_power(si_t *sih, bool on)
-{
- chipcregs_t *cc;
- uint origidx;
- u32 rsrcs = 0; /* rsrcs to turn on/off OTP power */
-
- ASSERT(sih->cccaps & CC_CAP_PMU);
-
- /* Don't do anything if OTP is disabled */
- if (si_is_otp_disabled(sih)) {
- PMU_MSG(("si_pmu_otp_power: OTP is disabled\n"));
- return;
- }
-
- /* Remember original core before switch to chipc */
- origidx = si_coreidx(sih);
- cc = si_setcoreidx(sih, SI_CC_IDX);
- ASSERT(cc != NULL);
-
- switch (sih->chip) {
- case BCM4329_CHIP_ID:
- rsrcs = PMURES_BIT(RES4329_OTP_PU);
- break;
- case BCM4319_CHIP_ID:
- rsrcs = PMURES_BIT(RES4319_OTP_PU);
- break;
- case BCM4336_CHIP_ID:
- rsrcs = PMURES_BIT(RES4336_OTP_PU);
- break;
- case BCM4330_CHIP_ID:
- rsrcs = PMURES_BIT(RES4330_OTP_PU);
- break;
- default:
- break;
- }
-
- if (rsrcs != 0) {
- u32 otps;
-
- /* Figure out the dependancies (exclude min_res_mask) */
- u32 deps = si_pmu_res_deps(sih, cc, rsrcs, true);
- u32 min_mask = 0, max_mask = 0;
- si_pmu_res_masks(sih, &min_mask, &max_mask);
- deps &= ~min_mask;
- /* Turn on/off the power */
- if (on) {
- PMU_MSG(("Adding rsrc 0x%x to min_res_mask\n",
- rsrcs | deps));
- OR_REG(&cc->min_res_mask, (rsrcs | deps));
- SPINWAIT(!(R_REG(&cc->res_state) & rsrcs),
- PMU_MAX_TRANSITION_DLY);
- ASSERT(R_REG(&cc->res_state) & rsrcs);
- } else {
- PMU_MSG(("Removing rsrc 0x%x from min_res_mask\n",
- rsrcs | deps));
- AND_REG(&cc->min_res_mask, ~(rsrcs | deps));
- }
-
- SPINWAIT((((otps = R_REG(&cc->otpstatus)) & OTPS_READY) !=
- (on ? OTPS_READY : 0)), 100);
- ASSERT((otps & OTPS_READY) == (on ? OTPS_READY : 0));
- if ((otps & OTPS_READY) != (on ? OTPS_READY : 0))
- PMU_MSG(("OTP ready bit not %s after wait\n",
- (on ? "ON" : "OFF")));
- }
-
- /* Return to original core */
- si_setcoreidx(sih, origidx);
-}
-
-void si_pmu_rcal(si_t *sih)
-{
- chipcregs_t *cc;
- uint origidx;
-
- ASSERT(sih->cccaps & CC_CAP_PMU);
-
- /* Remember original core before switch to chipc */
- origidx = si_coreidx(sih);
- cc = si_setcoreidx(sih, SI_CC_IDX);
- ASSERT(cc != NULL);
-
- switch (sih->chip) {
- case BCM4329_CHIP_ID:{
- u8 rcal_code;
- u32 val;
-
- /* Kick RCal */
- W_REG(&cc->chipcontrol_addr, 1);
-
- /* Power Down RCAL Block */
- AND_REG(&cc->chipcontrol_data, ~0x04);
-
- /* Power Up RCAL block */
- OR_REG(&cc->chipcontrol_data, 0x04);
-
- /* Wait for completion */
- SPINWAIT(0 == (R_REG(&cc->chipstatus) & 0x08),
- 10 * 1000 * 1000);
- ASSERT(R_REG(&cc->chipstatus) & 0x08);
-
- /* Drop the LSB to convert from 5 bit code to 4 bit code */
- rcal_code =
- (u8) (R_REG(&cc->chipstatus) >> 5) & 0x0f;
-
- PMU_MSG(("RCal completed, status 0x%x, code 0x%x\n",
- R_REG(&cc->chipstatus), rcal_code));
-
- /* Write RCal code into pmu_vreg_ctrl[32:29] */
- W_REG(&cc->regcontrol_addr, 0);
- val =
- R_REG(&cc->regcontrol_data) & ~((u32) 0x07 << 29);
- val |= (u32) (rcal_code & 0x07) << 29;
- W_REG(&cc->regcontrol_data, val);
- W_REG(&cc->regcontrol_addr, 1);
- val = R_REG(&cc->regcontrol_data) & ~(u32) 0x01;
- val |= (u32) ((rcal_code >> 3) & 0x01);
- W_REG(&cc->regcontrol_data, val);
-
- /* Write RCal code into pmu_chip_ctrl[33:30] */
- W_REG(&cc->chipcontrol_addr, 0);
- val =
- R_REG(&cc->chipcontrol_data) & ~((u32) 0x03 << 30);
- val |= (u32) (rcal_code & 0x03) << 30;
- W_REG(&cc->chipcontrol_data, val);
- W_REG(&cc->chipcontrol_addr, 1);
- val =
- R_REG(&cc->chipcontrol_data) & ~(u32) 0x03;
- val |= (u32) ((rcal_code >> 2) & 0x03);
- W_REG(&cc->chipcontrol_data, val);
-
- /* Set override in pmu_chip_ctrl[29] */
- W_REG(&cc->chipcontrol_addr, 0);
- OR_REG(&cc->chipcontrol_data, (0x01 << 29));
-
- /* Power off RCal block */
- W_REG(&cc->chipcontrol_addr, 1);
- AND_REG(&cc->chipcontrol_data, ~0x04);
-
- break;
- }
- default:
- break;
- }
-
- /* Return to original core */
- si_setcoreidx(sih, origidx);
-}
-
-void si_pmu_spuravoid(si_t *sih, u8 spuravoid)
-{
- chipcregs_t *cc;
- uint origidx, intr_val;
- u32 tmp = 0;
-
- /* Remember original core before switch to chipc */
- cc = (chipcregs_t *) si_switch_core(sih, CC_CORE_ID, &origidx,
- &intr_val);
- ASSERT(cc != NULL);
-
- /* force the HT off */
- if (sih->chip == BCM4336_CHIP_ID) {
- tmp = R_REG(&cc->max_res_mask);
- tmp &= ~RES4336_HT_AVAIL;
- W_REG(&cc->max_res_mask, tmp);
- /* wait for the ht to really go away */
- SPINWAIT(((R_REG(&cc->clk_ctl_st) & CCS_HTAVAIL) == 0),
- 10000);
- ASSERT((R_REG(&cc->clk_ctl_st) & CCS_HTAVAIL) == 0);
- }
-
- /* update the pll changes */
- si_pmu_spuravoid_pllupdate(sih, cc, spuravoid);
-
- /* enable HT back on */
- if (sih->chip == BCM4336_CHIP_ID) {
- tmp = R_REG(&cc->max_res_mask);
- tmp |= RES4336_HT_AVAIL;
- W_REG(&cc->max_res_mask, tmp);
- }
-
- /* Return to original core */
- si_restore_core(sih, origidx, intr_val);
-}
-
-static void
-si_pmu_spuravoid_pllupdate(si_t *sih, chipcregs_t *cc, u8 spuravoid)
-{
- u32 tmp = 0;
- u8 phypll_offset = 0;
- u8 bcm5357_bcm43236_p1div[] = { 0x1, 0x5, 0x5 };
- u8 bcm5357_bcm43236_ndiv[] = { 0x30, 0xf6, 0xfc };
-
- switch (sih->chip) {
- case BCM5357_CHIP_ID:
- case BCM43235_CHIP_ID:
- case BCM43236_CHIP_ID:
- case BCM43238_CHIP_ID:
-
- /* BCM5357 needs to touch PLL1_PLLCTL[02], so offset PLL0_PLLCTL[02] by 6 */
- phypll_offset = (sih->chip == BCM5357_CHIP_ID) ? 6 : 0;
-
- /* RMW only the P1 divider */
- W_REG(&cc->pllcontrol_addr,
- PMU1_PLL0_PLLCTL0 + phypll_offset);
- tmp = R_REG(&cc->pllcontrol_data);
- tmp &= (~(PMU1_PLL0_PC0_P1DIV_MASK));
- tmp |=
- (bcm5357_bcm43236_p1div[spuravoid] <<
- PMU1_PLL0_PC0_P1DIV_SHIFT);
- W_REG(&cc->pllcontrol_data, tmp);
-
- /* RMW only the int feedback divider */
- W_REG(&cc->pllcontrol_addr,
- PMU1_PLL0_PLLCTL2 + phypll_offset);
- tmp = R_REG(&cc->pllcontrol_data);
- tmp &= ~(PMU1_PLL0_PC2_NDIV_INT_MASK);
- tmp |=
- (bcm5357_bcm43236_ndiv[spuravoid]) <<
- PMU1_PLL0_PC2_NDIV_INT_SHIFT;
- W_REG(&cc->pllcontrol_data, tmp);
-
- tmp = 1 << 10;
- break;
-
- case BCM4331_CHIP_ID:
- if (spuravoid == 2) {
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
- W_REG(&cc->pllcontrol_data, 0x11500014);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
- W_REG(&cc->pllcontrol_data, 0x0FC00a08);
- } else if (spuravoid == 1) {
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
- W_REG(&cc->pllcontrol_data, 0x11500014);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
- W_REG(&cc->pllcontrol_data, 0x0F600a08);
- } else {
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
- W_REG(&cc->pllcontrol_data, 0x11100014);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
- W_REG(&cc->pllcontrol_data, 0x03000a08);
- }
- tmp = 1 << 10;
- break;
-
- case BCM43224_CHIP_ID:
- case BCM43225_CHIP_ID:
- case BCM43421_CHIP_ID:
- case BCM6362_CHIP_ID:
- if (spuravoid == 1) {
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
- W_REG(&cc->pllcontrol_data, 0x11500010);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
- W_REG(&cc->pllcontrol_data, 0x000C0C06);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
- W_REG(&cc->pllcontrol_data, 0x0F600a08);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
- W_REG(&cc->pllcontrol_data, 0x00000000);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
- W_REG(&cc->pllcontrol_data, 0x2001E920);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
- W_REG(&cc->pllcontrol_data, 0x88888815);
- } else {
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
- W_REG(&cc->pllcontrol_data, 0x11100010);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
- W_REG(&cc->pllcontrol_data, 0x000c0c06);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
- W_REG(&cc->pllcontrol_data, 0x03000a08);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
- W_REG(&cc->pllcontrol_data, 0x00000000);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
- W_REG(&cc->pllcontrol_data, 0x200005c0);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
- W_REG(&cc->pllcontrol_data, 0x88888815);
- }
- tmp = 1 << 10;
- break;
-
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
- W_REG(&cc->pllcontrol_data, 0x11100008);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
- W_REG(&cc->pllcontrol_data, 0x0c000c06);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
- W_REG(&cc->pllcontrol_data, 0x03000a08);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
- W_REG(&cc->pllcontrol_data, 0x00000000);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
- W_REG(&cc->pllcontrol_data, 0x200005c0);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
- W_REG(&cc->pllcontrol_data, 0x88888855);
-
- tmp = 1 << 10;
- break;
-
- case BCM4716_CHIP_ID:
- case BCM4748_CHIP_ID:
- case BCM47162_CHIP_ID:
- if (spuravoid == 1) {
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
- W_REG(&cc->pllcontrol_data, 0x11500060);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
- W_REG(&cc->pllcontrol_data, 0x080C0C06);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
- W_REG(&cc->pllcontrol_data, 0x0F600000);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
- W_REG(&cc->pllcontrol_data, 0x00000000);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
- W_REG(&cc->pllcontrol_data, 0x2001E924);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
- W_REG(&cc->pllcontrol_data, 0x88888815);
- } else {
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
- W_REG(&cc->pllcontrol_data, 0x11100060);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
- W_REG(&cc->pllcontrol_data, 0x080c0c06);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
- W_REG(&cc->pllcontrol_data, 0x03000000);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
- W_REG(&cc->pllcontrol_data, 0x00000000);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
- W_REG(&cc->pllcontrol_data, 0x200005c0);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
- W_REG(&cc->pllcontrol_data, 0x88888815);
- }
-
- tmp = 3 << 9;
- break;
-
- case BCM4319_CHIP_ID:
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
- W_REG(&cc->pllcontrol_data, 0x11100070);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
- W_REG(&cc->pllcontrol_data, 0x1014140a);
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
- W_REG(&cc->pllcontrol_data, 0x88888854);
-
- if (spuravoid == 1) { /* spur_avoid ON, enable 41/82/164Mhz clock mode */
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
- W_REG(&cc->pllcontrol_data, 0x05201828);
- } else { /* enable 40/80/160Mhz clock mode */
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
- W_REG(&cc->pllcontrol_data, 0x05001828);
- }
- break;
- case BCM4336_CHIP_ID:
- /* Looks like these are only for default xtal freq 26MHz */
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL0);
- W_REG(&cc->pllcontrol_data, 0x02100020);
-
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
- W_REG(&cc->pllcontrol_data, 0x0C0C0C0C);
-
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL2);
- W_REG(&cc->pllcontrol_data, 0x01240C0C);
-
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL4);
- W_REG(&cc->pllcontrol_data, 0x202C2820);
-
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL5);
- W_REG(&cc->pllcontrol_data, 0x88888825);
-
- W_REG(&cc->pllcontrol_addr, PMU1_PLL0_PLLCTL3);
- if (spuravoid == 1) {
- W_REG(&cc->pllcontrol_data, 0x00EC4EC4);
- } else {
- W_REG(&cc->pllcontrol_data, 0x00762762);
- }
-
- tmp = PCTL_PLL_PLLCTL_UPD;
- break;
-
- default:
- PMU_ERROR(("%s: unknown spuravoidance settings for chip %s, not changing PLL\n", __func__, bcm_chipname(sih->chip, chn, 8)));
- break;
- }
-
- tmp |= R_REG(&cc->pmucontrol);
- W_REG(&cc->pmucontrol, tmp);
-}
-
-bool si_pmu_is_otp_powered(si_t *sih)
-{
- uint idx;
- chipcregs_t *cc;
- bool st;
-
- /* Remember original core before switch to chipc */
- idx = si_coreidx(sih);
- cc = si_setcoreidx(sih, SI_CC_IDX);
- ASSERT(cc != NULL);
-
- switch (sih->chip) {
- case BCM4329_CHIP_ID:
- st = (R_REG(&cc->res_state) & PMURES_BIT(RES4329_OTP_PU))
- != 0;
- break;
- case BCM4319_CHIP_ID:
- st = (R_REG(&cc->res_state) & PMURES_BIT(RES4319_OTP_PU))
- != 0;
- break;
- case BCM4336_CHIP_ID:
- st = (R_REG(&cc->res_state) & PMURES_BIT(RES4336_OTP_PU))
- != 0;
- break;
- case BCM4330_CHIP_ID:
- st = (R_REG(&cc->res_state) & PMURES_BIT(RES4330_OTP_PU))
- != 0;
- break;
-
- /* These chip doesn't use PMU bit to power up/down OTP. OTP always on.
- * Use OTP_INIT command to reset/refresh state.
- */
- case BCM43224_CHIP_ID:
- case BCM43225_CHIP_ID:
- case BCM43421_CHIP_ID:
- case BCM43236_CHIP_ID:
- case BCM43235_CHIP_ID:
- case BCM43238_CHIP_ID:
- st = true;
- break;
- default:
- st = true;
- break;
- }
-
- /* Return to original core */
- si_setcoreidx(sih, idx);
- return st;
-}
-
-void si_pmu_sprom_enable(si_t *sih, bool enable)
-{
- chipcregs_t *cc;
- uint origidx;
-
- /* Remember original core before switch to chipc */
- origidx = si_coreidx(sih);
- cc = si_setcoreidx(sih, SI_CC_IDX);
- ASSERT(cc != NULL);
-
- /* Return to original core */
- si_setcoreidx(sih, origidx);
-}
-
-/* initialize PMU chip controls and other chip level stuff */
-void si_pmu_chip_init(si_t *sih)
-{
- uint origidx;
-
- ASSERT(sih->cccaps & CC_CAP_PMU);
-
-#ifdef CHIPC_UART_ALWAYS_ON
- si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, clk_ctl_st),
- CCS_FORCEALP, CCS_FORCEALP);
-#endif /* CHIPC_UART_ALWAYS_ON */
-
- /* Gate off SPROM clock and chip select signals */
- si_pmu_sprom_enable(sih, false);
-
- /* Remember original core */
- origidx = si_coreidx(sih);
-
- /* Return to original core */
- si_setcoreidx(sih, origidx);
-}
-
-/* initialize PMU switch/regulators */
-void si_pmu_swreg_init(si_t *sih)
-{
- ASSERT(sih->cccaps & CC_CAP_PMU);
-
- switch (sih->chip) {
- case BCM4336_CHIP_ID:
- /* Reduce CLDO PWM output voltage to 1.2V */
- si_pmu_set_ldo_voltage(sih, SET_LDO_VOLTAGE_CLDO_PWM, 0xe);
- /* Reduce CLDO BURST output voltage to 1.2V */
- si_pmu_set_ldo_voltage(sih, SET_LDO_VOLTAGE_CLDO_BURST,
- 0xe);
- /* Reduce LNLDO1 output voltage to 1.2V */
- si_pmu_set_ldo_voltage(sih, SET_LDO_VOLTAGE_LNLDO1, 0xe);
- if (sih->chiprev == 0)
- si_pmu_regcontrol(sih, 2, 0x400000, 0x400000);
- break;
-
- case BCM4330_CHIP_ID:
- /* CBUCK Voltage is 1.8 by default and set that to 1.5 */
- si_pmu_set_ldo_voltage(sih, SET_LDO_VOLTAGE_CBUCK_PWM, 0);
- break;
- default:
- break;
- }
-}
-
-void si_pmu_radio_enable(si_t *sih, bool enable)
-{
- ASSERT(sih->cccaps & CC_CAP_PMU);
-
- switch (sih->chip) {
- case BCM4319_CHIP_ID:
- if (enable)
- si_write_wrapperreg(sih, AI_OOBSELOUTB74,
- (u32) 0x868584);
- else
- si_write_wrapperreg(sih, AI_OOBSELOUTB74,
- (u32) 0x060584);
- break;
- }
-}
-
-/* Wait for a particular clock level to be on the backplane */
-u32
-si_pmu_waitforclk_on_backplane(si_t *sih, u32 clk, u32 delay)
-{
- chipcregs_t *cc;
- uint origidx;
-
- ASSERT(sih->cccaps & CC_CAP_PMU);
-
- /* Remember original core before switch to chipc */
- origidx = si_coreidx(sih);
- cc = si_setcoreidx(sih, SI_CC_IDX);
- ASSERT(cc != NULL);
-
- if (delay)
- SPINWAIT(((R_REG(&cc->pmustatus) & clk) != clk), delay);
-
- /* Return to original core */
- si_setcoreidx(sih, origidx);
-
- return R_REG(&cc->pmustatus) & clk;
-}
-
-/*
- * Measures the ALP clock frequency in KHz. Returns 0 if not possible.
- * Possible only if PMU rev >= 10 and there is an external LPO 32768Hz crystal.
- */
-
-#define EXT_ILP_HZ 32768
-
-u32 si_pmu_measure_alpclk(si_t *sih)
-{
- chipcregs_t *cc;
- uint origidx;
- u32 alp_khz;
-
- if (sih->pmurev < 10)
- return 0;
-
- ASSERT(sih->cccaps & CC_CAP_PMU);
-
- /* Remember original core before switch to chipc */
- origidx = si_coreidx(sih);
- cc = si_setcoreidx(sih, SI_CC_IDX);
- ASSERT(cc != NULL);
-
- if (R_REG(&cc->pmustatus) & PST_EXTLPOAVAIL) {
- u32 ilp_ctr, alp_hz;
-
- /* Enable the reg to measure the freq, in case disabled before */
- W_REG(&cc->pmu_xtalfreq,
- 1U << PMU_XTALFREQ_REG_MEASURE_SHIFT);
-
- /* Delay for well over 4 ILP clocks */
- udelay(1000);
-
- /* Read the latched number of ALP ticks per 4 ILP ticks */
- ilp_ctr =
- R_REG(&cc->pmu_xtalfreq) & PMU_XTALFREQ_REG_ILPCTR_MASK;
-
- /* Turn off the PMU_XTALFREQ_REG_MEASURE_SHIFT bit to save power */
- W_REG(&cc->pmu_xtalfreq, 0);
-
- /* Calculate ALP frequency */
- alp_hz = (ilp_ctr * EXT_ILP_HZ) / 4;
-
- /* Round to nearest 100KHz, and at the same time convert to KHz */
- alp_khz = (alp_hz + 50000) / 100000 * 100;
- } else
- alp_khz = 0;
-
- /* Return to original core */
- si_setcoreidx(sih, origidx);
-
- return alp_khz;
-}
-
-static void si_pmu_set_4330_plldivs(si_t *sih)
-{
- u32 FVCO = si_pmu1_pllfvco0(sih) / 1000;
- u32 m1div, m2div, m3div, m4div, m5div, m6div;
- u32 pllc1, pllc2;
-
- m2div = m3div = m4div = m6div = FVCO / 80;
- m5div = FVCO / 160;
-
- if (CST4330_CHIPMODE_SDIOD(sih->chipst))
- m1div = FVCO / 80;
- else
- m1div = FVCO / 90;
- pllc1 =
- (m1div << PMU1_PLL0_PC1_M1DIV_SHIFT) | (m2div <<
- PMU1_PLL0_PC1_M2DIV_SHIFT) |
- (m3div << PMU1_PLL0_PC1_M3DIV_SHIFT) | (m4div <<
- PMU1_PLL0_PC1_M4DIV_SHIFT);
- si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL1, ~0, pllc1);
-
- pllc2 = si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL1, 0, 0);
- pllc2 &= ~(PMU1_PLL0_PC2_M5DIV_MASK | PMU1_PLL0_PC2_M6DIV_MASK);
- pllc2 |=
- ((m5div << PMU1_PLL0_PC2_M5DIV_SHIFT) |
- (m6div << PMU1_PLL0_PC2_M6DIV_SHIFT));
- si_pmu_pllcontrol(sih, PMU1_PLL0_PLLCTL2, ~0, pllc2);
-}
diff --git a/drivers/staging/brcm80211/util/nicpci.c b/drivers/staging/brcm80211/util/nicpci.c
deleted file mode 100644
index a1fb2f0..0000000
--- a/drivers/staging/brcm80211/util/nicpci.c
+++ /dev/null
@@ -1,851 +0,0 @@
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#include <linux/delay.h>
-#include <linux/string.h>
-#include <linux/pci.h>
-#include <bcmdefs.h>
-#include <bcmutils.h>
-#include <siutils.h>
-#include <hndsoc.h>
-#include <bcmdevs.h>
-#include <sbchipc.h>
-#include <pci_core.h>
-#include <pcie_core.h>
-#include <nicpci.h>
-#include <pcicfg.h>
-
-typedef struct {
- union {
- sbpcieregs_t *pcieregs;
- struct sbpciregs *pciregs;
- } regs; /* Memory mapped register to the core */
-
- si_t *sih; /* System interconnect handle */
- struct pci_dev *dev;
- u8 pciecap_lcreg_offset; /* PCIE capability LCreg offset in the config space */
- bool pcie_pr42767;
- u8 pcie_polarity;
- u8 pcie_war_aspm_ovr; /* Override ASPM/Clkreq settings */
-
- u8 pmecap_offset; /* PM Capability offset in the config space */
- bool pmecap; /* Capable of generating PME */
-} pcicore_info_t;
-
-/* debug/trace */
-#define PCI_ERROR(args)
-#define PCIE_PUB(sih) \
- (((sih)->bustype == PCI_BUS) && ((sih)->buscoretype == PCIE_CORE_ID))
-
-/* routines to access mdio slave device registers */
-static bool pcie_mdiosetblock(pcicore_info_t *pi, uint blk);
-static int pcie_mdioop(pcicore_info_t *pi, uint physmedia, uint regaddr,
- bool write, uint *val);
-static int pcie_mdiowrite(pcicore_info_t *pi, uint physmedia, uint readdr,
- uint val);
-static int pcie_mdioread(pcicore_info_t *pi, uint physmedia, uint readdr,
- uint *ret_val);
-
-static void pcie_extendL1timer(pcicore_info_t *pi, bool extend);
-static void pcie_clkreq_upd(pcicore_info_t *pi, uint state);
-
-static void pcie_war_aspm_clkreq(pcicore_info_t *pi);
-static void pcie_war_serdes(pcicore_info_t *pi);
-static void pcie_war_noplldown(pcicore_info_t *pi);
-static void pcie_war_polarity(pcicore_info_t *pi);
-static void pcie_war_pci_setup(pcicore_info_t *pi);
-
-static bool pcicore_pmecap(pcicore_info_t *pi);
-
-#define PCIE_ASPM(sih) ((PCIE_PUB(sih)) && (((sih)->buscorerev >= 3) && ((sih)->buscorerev <= 5)))
-
-
-/* delay needed between the mdio control/ mdiodata register data access */
-#define PR28829_DELAY() udelay(10)
-
-/* Initialize the PCI core. It's caller's responsibility to make sure that this is done
- * only once
- */
-void *pcicore_init(si_t *sih, void *pdev, void *regs)
-{
- pcicore_info_t *pi;
-
- ASSERT(sih->bustype == PCI_BUS);
-
- /* alloc pcicore_info_t */
- pi = kzalloc(sizeof(pcicore_info_t), GFP_ATOMIC);
- if (pi == NULL) {
- PCI_ERROR(("pci_attach: malloc failed!\n"));
- return NULL;
- }
-
- pi->sih = sih;
- pi->dev = pdev;
-
- if (sih->buscoretype == PCIE_CORE_ID) {
- u8 cap_ptr;
- pi->regs.pcieregs = (sbpcieregs_t *) regs;
- cap_ptr =
- pcicore_find_pci_capability(pi->dev, PCI_CAP_PCIECAP_ID,
- NULL, NULL);
- ASSERT(cap_ptr);
- pi->pciecap_lcreg_offset = cap_ptr + PCIE_CAP_LINKCTRL_OFFSET;
- } else
- pi->regs.pciregs = (struct sbpciregs *) regs;
-
- return pi;
-}
-
-void pcicore_deinit(void *pch)
-{
- pcicore_info_t *pi = (pcicore_info_t *) pch;
-
- if (pi == NULL)
- return;
- kfree(pi);
-}
-
-/* return cap_offset if requested capability exists in the PCI config space */
-/* Note that it's caller's responsibility to make sure it's a pci bus */
-u8
-pcicore_find_pci_capability(void *dev, u8 req_cap_id,
- unsigned char *buf, u32 *buflen)
-{
- u8 cap_id;
- u8 cap_ptr = 0;
- u32 bufsize;
- u8 byte_val;
-
- /* check for Header type 0 */
- pci_read_config_byte(dev, PCI_CFG_HDR, &byte_val);
- if ((byte_val & 0x7f) != PCI_HEADER_NORMAL)
- goto end;
-
- /* check if the capability pointer field exists */
- pci_read_config_byte(dev, PCI_CFG_STAT, &byte_val);
- if (!(byte_val & PCI_CAPPTR_PRESENT))
- goto end;
-
- pci_read_config_byte(dev, PCI_CFG_CAPPTR, &cap_ptr);
- /* check if the capability pointer is 0x00 */
- if (cap_ptr == 0x00)
- goto end;
-
- /* loop thr'u the capability list and see if the pcie capabilty exists */
-
- pci_read_config_byte(dev, cap_ptr, &cap_id);
-
- while (cap_id != req_cap_id) {
- pci_read_config_byte(dev, cap_ptr + 1, &cap_ptr);
- if (cap_ptr == 0x00)
- break;
- pci_read_config_byte(dev, cap_ptr, &cap_id);
- }
- if (cap_id != req_cap_id) {
- goto end;
- }
- /* found the caller requested capability */
- if ((buf != NULL) && (buflen != NULL)) {
- u8 cap_data;
-
- bufsize = *buflen;
- if (!bufsize)
- goto end;
- *buflen = 0;
- /* copy the cpability data excluding cap ID and next ptr */
- cap_data = cap_ptr + 2;
- if ((bufsize + cap_data) > SZPCR)
- bufsize = SZPCR - cap_data;
- *buflen = bufsize;
- while (bufsize--) {
- pci_read_config_byte(dev, cap_data, buf);
- cap_data++;
- buf++;
- }
- }
- end:
- return cap_ptr;
-}
-
-/* ***** Register Access API */
-uint
-pcie_readreg(sbpcieregs_t *pcieregs, uint addrtype,
- uint offset)
-{
- uint retval = 0xFFFFFFFF;
-
- ASSERT(pcieregs != NULL);
-
- switch (addrtype) {
- case PCIE_CONFIGREGS:
- W_REG((&pcieregs->configaddr), offset);
- (void)R_REG((&pcieregs->configaddr));
- retval = R_REG(&(pcieregs->configdata));
- break;
- case PCIE_PCIEREGS:
- W_REG(&(pcieregs->pcieindaddr), offset);
- (void)R_REG((&pcieregs->pcieindaddr));
- retval = R_REG(&(pcieregs->pcieinddata));
- break;
- default:
- ASSERT(0);
- break;
- }
-
- return retval;
-}
-
-uint
-pcie_writereg(sbpcieregs_t *pcieregs, uint addrtype,
- uint offset, uint val)
-{
- ASSERT(pcieregs != NULL);
-
- switch (addrtype) {
- case PCIE_CONFIGREGS:
- W_REG((&pcieregs->configaddr), offset);
- W_REG((&pcieregs->configdata), val);
- break;
- case PCIE_PCIEREGS:
- W_REG((&pcieregs->pcieindaddr), offset);
- W_REG((&pcieregs->pcieinddata), val);
- break;
- default:
- ASSERT(0);
- break;
- }
- return 0;
-}
-
-static bool pcie_mdiosetblock(pcicore_info_t *pi, uint blk)
-{
- sbpcieregs_t *pcieregs = pi->regs.pcieregs;
- uint mdiodata, i = 0;
- uint pcie_serdes_spinwait = 200;
-
- mdiodata =
- MDIODATA_START | MDIODATA_WRITE | (MDIODATA_DEV_ADDR <<
- MDIODATA_DEVADDR_SHF) |
- (MDIODATA_BLK_ADDR << MDIODATA_REGADDR_SHF) | MDIODATA_TA | (blk <<
- 4);
- W_REG(&pcieregs->mdiodata, mdiodata);
-
- PR28829_DELAY();
- /* retry till the transaction is complete */
- while (i < pcie_serdes_spinwait) {
- if (R_REG(&(pcieregs->mdiocontrol)) &
- MDIOCTL_ACCESS_DONE) {
- break;
- }
- udelay(1000);
- i++;
- }
-
- if (i >= pcie_serdes_spinwait) {
- PCI_ERROR(("pcie_mdiosetblock: timed out\n"));
- return false;
- }
-
- return true;
-}
-
-static int
-pcie_mdioop(pcicore_info_t *pi, uint physmedia, uint regaddr, bool write,
- uint *val)
-{
- sbpcieregs_t *pcieregs = pi->regs.pcieregs;
- uint mdiodata;
- uint i = 0;
- uint pcie_serdes_spinwait = 10;
-
- /* enable mdio access to SERDES */
- W_REG((&pcieregs->mdiocontrol),
- MDIOCTL_PREAM_EN | MDIOCTL_DIVISOR_VAL);
-
- if (pi->sih->buscorerev >= 10) {
- /* new serdes is slower in rw, using two layers of reg address mapping */
- if (!pcie_mdiosetblock(pi, physmedia))
- return 1;
- mdiodata = (MDIODATA_DEV_ADDR << MDIODATA_DEVADDR_SHF) |
- (regaddr << MDIODATA_REGADDR_SHF);
- pcie_serdes_spinwait *= 20;
- } else {
- mdiodata = (physmedia << MDIODATA_DEVADDR_SHF_OLD) |
- (regaddr << MDIODATA_REGADDR_SHF_OLD);
- }
-
- if (!write)
- mdiodata |= (MDIODATA_START | MDIODATA_READ | MDIODATA_TA);
- else
- mdiodata |=
- (MDIODATA_START | MDIODATA_WRITE | MDIODATA_TA | *val);
-
- W_REG(&pcieregs->mdiodata, mdiodata);
-
- PR28829_DELAY();
-
- /* retry till the transaction is complete */
- while (i < pcie_serdes_spinwait) {
- if (R_REG(&(pcieregs->mdiocontrol)) &
- MDIOCTL_ACCESS_DONE) {
- if (!write) {
- PR28829_DELAY();
- *val =
- (R_REG(&(pcieregs->mdiodata)) &
- MDIODATA_MASK);
- }
- /* Disable mdio access to SERDES */
- W_REG((&pcieregs->mdiocontrol), 0);
- return 0;
- }
- udelay(1000);
- i++;
- }
-
- PCI_ERROR(("pcie_mdioop: timed out op: %d\n", write));
- /* Disable mdio access to SERDES */
- W_REG((&pcieregs->mdiocontrol), 0);
- return 1;
-}
-
-/* use the mdio interface to read from mdio slaves */
-static int
-pcie_mdioread(pcicore_info_t *pi, uint physmedia, uint regaddr, uint *regval)
-{
- return pcie_mdioop(pi, physmedia, regaddr, false, regval);
-}
-
-/* use the mdio interface to write to mdio slaves */
-static int
-pcie_mdiowrite(pcicore_info_t *pi, uint physmedia, uint regaddr, uint val)
-{
- return pcie_mdioop(pi, physmedia, regaddr, true, &val);
-}
-
-/* ***** Support functions ***** */
-u8 pcie_clkreq(void *pch, u32 mask, u32 val)
-{
- pcicore_info_t *pi = (pcicore_info_t *) pch;
- u32 reg_val;
- u8 offset;
-
- offset = pi->pciecap_lcreg_offset;
- if (!offset)
- return 0;
-
- pci_read_config_dword(pi->dev, offset, ®_val);
- /* set operation */
- if (mask) {
- if (val)
- reg_val |= PCIE_CLKREQ_ENAB;
- else
- reg_val &= ~PCIE_CLKREQ_ENAB;
- pci_write_config_dword(pi->dev, offset, reg_val);
- pci_read_config_dword(pi->dev, offset, ®_val);
- }
- if (reg_val & PCIE_CLKREQ_ENAB)
- return 1;
- else
- return 0;
-}
-
-static void pcie_extendL1timer(pcicore_info_t *pi, bool extend)
-{
- u32 w;
- si_t *sih = pi->sih;
- sbpcieregs_t *pcieregs = pi->regs.pcieregs;
-
- if (!PCIE_PUB(sih) || sih->buscorerev < 7)
- return;
-
- w = pcie_readreg(pcieregs, PCIE_PCIEREGS, PCIE_DLLP_PMTHRESHREG);
- if (extend)
- w |= PCIE_ASPMTIMER_EXTEND;
- else
- w &= ~PCIE_ASPMTIMER_EXTEND;
- pcie_writereg(pcieregs, PCIE_PCIEREGS, PCIE_DLLP_PMTHRESHREG, w);
- w = pcie_readreg(pcieregs, PCIE_PCIEREGS, PCIE_DLLP_PMTHRESHREG);
-}
-
-/* centralized clkreq control policy */
-static void pcie_clkreq_upd(pcicore_info_t *pi, uint state)
-{
- si_t *sih = pi->sih;
- ASSERT(PCIE_PUB(sih));
-
- switch (state) {
- case SI_DOATTACH:
- if (PCIE_ASPM(sih))
- pcie_clkreq((void *)pi, 1, 0);
- break;
- case SI_PCIDOWN:
- if (sih->buscorerev == 6) { /* turn on serdes PLL down */
- si_corereg(sih, SI_CC_IDX,
- offsetof(chipcregs_t, chipcontrol_addr), ~0,
- 0);
- si_corereg(sih, SI_CC_IDX,
- offsetof(chipcregs_t, chipcontrol_data),
- ~0x40, 0);
- } else if (pi->pcie_pr42767) {
- pcie_clkreq((void *)pi, 1, 1);
- }
- break;
- case SI_PCIUP:
- if (sih->buscorerev == 6) { /* turn off serdes PLL down */
- si_corereg(sih, SI_CC_IDX,
- offsetof(chipcregs_t, chipcontrol_addr), ~0,
- 0);
- si_corereg(sih, SI_CC_IDX,
- offsetof(chipcregs_t, chipcontrol_data),
- ~0x40, 0x40);
- } else if (PCIE_ASPM(sih)) { /* disable clkreq */
- pcie_clkreq((void *)pi, 1, 0);
- }
- break;
- default:
- ASSERT(0);
- break;
- }
-}
-
-/* ***** PCI core WARs ***** */
-/* Done only once at attach time */
-static void pcie_war_polarity(pcicore_info_t *pi)
-{
- u32 w;
-
- if (pi->pcie_polarity != 0)
- return;
-
- w = pcie_readreg(pi->regs.pcieregs, PCIE_PCIEREGS,
- PCIE_PLP_STATUSREG);
-
- /* Detect the current polarity at attach and force that polarity and
- * disable changing the polarity
- */
- if ((w & PCIE_PLP_POLARITYINV_STAT) == 0)
- pi->pcie_polarity = (SERDES_RX_CTRL_FORCE);
- else
- pi->pcie_polarity =
- (SERDES_RX_CTRL_FORCE | SERDES_RX_CTRL_POLARITY);
-}
-
-/* enable ASPM and CLKREQ if srom doesn't have it */
-/* Needs to happen when update to shadow SROM is needed
- * : Coming out of 'standby'/'hibernate'
- * : If pcie_war_aspm_ovr state changed
- */
-static void pcie_war_aspm_clkreq(pcicore_info_t *pi)
-{
- sbpcieregs_t *pcieregs = pi->regs.pcieregs;
- si_t *sih = pi->sih;
- u16 val16, *reg16;
- u32 w;
-
- if (!PCIE_ASPM(sih))
- return;
-
- /* bypass this on QT or VSIM */
- if (!ISSIM_ENAB(sih)) {
-
- reg16 = &pcieregs->sprom[SRSH_ASPM_OFFSET];
- val16 = R_REG(reg16);
-
- val16 &= ~SRSH_ASPM_ENB;
- if (pi->pcie_war_aspm_ovr == PCIE_ASPM_ENAB)
- val16 |= SRSH_ASPM_ENB;
- else if (pi->pcie_war_aspm_ovr == PCIE_ASPM_L1_ENAB)
- val16 |= SRSH_ASPM_L1_ENB;
- else if (pi->pcie_war_aspm_ovr == PCIE_ASPM_L0s_ENAB)
- val16 |= SRSH_ASPM_L0s_ENB;
-
- W_REG(reg16, val16);
-
- pci_read_config_dword(pi->dev, pi->pciecap_lcreg_offset,
- &w);
- w &= ~PCIE_ASPM_ENAB;
- w |= pi->pcie_war_aspm_ovr;
- pci_write_config_dword(pi->dev,
- pi->pciecap_lcreg_offset, w);
- }
-
- reg16 = &pcieregs->sprom[SRSH_CLKREQ_OFFSET_REV5];
- val16 = R_REG(reg16);
-
- if (pi->pcie_war_aspm_ovr != PCIE_ASPM_DISAB) {
- val16 |= SRSH_CLKREQ_ENB;
- pi->pcie_pr42767 = true;
- } else
- val16 &= ~SRSH_CLKREQ_ENB;
-
- W_REG(reg16, val16);
-}
-
-/* Apply the polarity determined at the start */
-/* Needs to happen when coming out of 'standby'/'hibernate' */
-static void pcie_war_serdes(pcicore_info_t *pi)
-{
- u32 w = 0;
-
- if (pi->pcie_polarity != 0)
- pcie_mdiowrite(pi, MDIODATA_DEV_RX, SERDES_RX_CTRL,
- pi->pcie_polarity);
-
- pcie_mdioread(pi, MDIODATA_DEV_PLL, SERDES_PLL_CTRL, &w);
- if (w & PLL_CTRL_FREQDET_EN) {
- w &= ~PLL_CTRL_FREQDET_EN;
- pcie_mdiowrite(pi, MDIODATA_DEV_PLL, SERDES_PLL_CTRL, w);
- }
-}
-
-/* Fix MISC config to allow coming out of L2/L3-Ready state w/o PRST */
-/* Needs to happen when coming out of 'standby'/'hibernate' */
-static void pcie_misc_config_fixup(pcicore_info_t *pi)
-{
- sbpcieregs_t *pcieregs = pi->regs.pcieregs;
- u16 val16, *reg16;
-
- reg16 = &pcieregs->sprom[SRSH_PCIE_MISC_CONFIG];
- val16 = R_REG(reg16);
-
- if ((val16 & SRSH_L23READY_EXIT_NOPERST) == 0) {
- val16 |= SRSH_L23READY_EXIT_NOPERST;
- W_REG(reg16, val16);
- }
-}
-
-/* quick hack for testing */
-/* Needs to happen when coming out of 'standby'/'hibernate' */
-static void pcie_war_noplldown(pcicore_info_t *pi)
-{
- sbpcieregs_t *pcieregs = pi->regs.pcieregs;
- u16 *reg16;
-
- ASSERT(pi->sih->buscorerev == 7);
-
- /* turn off serdes PLL down */
- si_corereg(pi->sih, SI_CC_IDX, offsetof(chipcregs_t, chipcontrol),
- CHIPCTRL_4321_PLL_DOWN, CHIPCTRL_4321_PLL_DOWN);
-
- /* clear srom shadow backdoor */
- reg16 = &pcieregs->sprom[SRSH_BD_OFFSET];
- W_REG(reg16, 0);
-}
-
-/* Needs to happen when coming out of 'standby'/'hibernate' */
-static void pcie_war_pci_setup(pcicore_info_t *pi)
-{
- si_t *sih = pi->sih;
- sbpcieregs_t *pcieregs = pi->regs.pcieregs;
- u32 w;
-
- if ((sih->buscorerev == 0) || (sih->buscorerev == 1)) {
- w = pcie_readreg(pcieregs, PCIE_PCIEREGS,
- PCIE_TLP_WORKAROUNDSREG);
- w |= 0x8;
- pcie_writereg(pcieregs, PCIE_PCIEREGS,
- PCIE_TLP_WORKAROUNDSREG, w);
- }
-
- if (sih->buscorerev == 1) {
- w = pcie_readreg(pcieregs, PCIE_PCIEREGS, PCIE_DLLP_LCREG);
- w |= (0x40);
- pcie_writereg(pcieregs, PCIE_PCIEREGS, PCIE_DLLP_LCREG, w);
- }
-
- if (sih->buscorerev == 0) {
- pcie_mdiowrite(pi, MDIODATA_DEV_RX, SERDES_RX_TIMER1, 0x8128);
- pcie_mdiowrite(pi, MDIODATA_DEV_RX, SERDES_RX_CDR, 0x0100);
- pcie_mdiowrite(pi, MDIODATA_DEV_RX, SERDES_RX_CDRBW, 0x1466);
- } else if (PCIE_ASPM(sih)) {
- /* Change the L1 threshold for better performance */
- w = pcie_readreg(pcieregs, PCIE_PCIEREGS,
- PCIE_DLLP_PMTHRESHREG);
- w &= ~(PCIE_L1THRESHOLDTIME_MASK);
- w |= (PCIE_L1THRESHOLD_WARVAL << PCIE_L1THRESHOLDTIME_SHIFT);
- pcie_writereg(pcieregs, PCIE_PCIEREGS,
- PCIE_DLLP_PMTHRESHREG, w);
-
- pcie_war_serdes(pi);
-
- pcie_war_aspm_clkreq(pi);
- } else if (pi->sih->buscorerev == 7)
- pcie_war_noplldown(pi);
-
- /* Note that the fix is actually in the SROM, that's why this is open-ended */
- if (pi->sih->buscorerev >= 6)
- pcie_misc_config_fixup(pi);
-}
-
-void pcie_war_ovr_aspm_update(void *pch, u8 aspm)
-{
- pcicore_info_t *pi = (pcicore_info_t *) pch;
-
- if (!PCIE_ASPM(pi->sih))
- return;
-
- /* Validate */
- if (aspm > PCIE_ASPM_ENAB)
- return;
-
- pi->pcie_war_aspm_ovr = aspm;
-
- /* Update the current state */
- pcie_war_aspm_clkreq(pi);
-}
-
-/* ***** Functions called during driver state changes ***** */
-void pcicore_attach(void *pch, char *pvars, int state)
-{
- pcicore_info_t *pi = (pcicore_info_t *) pch;
- si_t *sih = pi->sih;
-
- /* Determine if this board needs override */
- if (PCIE_ASPM(sih)) {
- if ((u32) getintvar(pvars, "boardflags2") & BFL2_PCIEWAR_OVR) {
- pi->pcie_war_aspm_ovr = PCIE_ASPM_DISAB;
- } else {
- pi->pcie_war_aspm_ovr = PCIE_ASPM_ENAB;
- }
- }
-
- /* These need to happen in this order only */
- pcie_war_polarity(pi);
-
- pcie_war_serdes(pi);
-
- pcie_war_aspm_clkreq(pi);
-
- pcie_clkreq_upd(pi, state);
-
-}
-
-void pcicore_hwup(void *pch)
-{
- pcicore_info_t *pi = (pcicore_info_t *) pch;
-
- if (!pi || !PCIE_PUB(pi->sih))
- return;
-
- pcie_war_pci_setup(pi);
-}
-
-void pcicore_up(void *pch, int state)
-{
- pcicore_info_t *pi = (pcicore_info_t *) pch;
-
- if (!pi || !PCIE_PUB(pi->sih))
- return;
-
- /* Restore L1 timer for better performance */
- pcie_extendL1timer(pi, true);
-
- pcie_clkreq_upd(pi, state);
-}
-
-/* When the device is going to enter D3 state (or the system is going to enter S3/S4 states */
-void pcicore_sleep(void *pch)
-{
- pcicore_info_t *pi = (pcicore_info_t *) pch;
- u32 w;
-
- if (!pi || !PCIE_ASPM(pi->sih))
- return;
-
- pci_read_config_dword(pi->dev, pi->pciecap_lcreg_offset, &w);
- w &= ~PCIE_CAP_LCREG_ASPML1;
- pci_write_config_dword(pi->dev, pi->pciecap_lcreg_offset, w);
-
- pi->pcie_pr42767 = false;
-}
-
-void pcicore_down(void *pch, int state)
-{
- pcicore_info_t *pi = (pcicore_info_t *) pch;
-
- if (!pi || !PCIE_PUB(pi->sih))
- return;
-
- pcie_clkreq_upd(pi, state);
-
- /* Reduce L1 timer for better power savings */
- pcie_extendL1timer(pi, false);
-}
-
-/* ***** Wake-on-wireless-LAN (WOWL) support functions ***** */
-/* Just uses PCI config accesses to find out, when needed before sb_attach is done */
-bool pcicore_pmecap_fast(void *pch)
-{
- pcicore_info_t *pi = (pcicore_info_t *) pch;
- u8 cap_ptr;
- u32 pmecap;
-
- cap_ptr =
- pcicore_find_pci_capability(pi->dev, PCI_CAP_POWERMGMTCAP_ID, NULL,
- NULL);
-
- if (!cap_ptr)
- return false;
-
- pci_read_config_dword(pi->dev, cap_ptr, &pmecap);
-
- return (pmecap & PME_CAP_PM_STATES) != 0;
-}
-
-/* return true if PM capability exists in the pci config space
- * Uses and caches the information using core handle
- */
-static bool pcicore_pmecap(pcicore_info_t *pi)
-{
- u8 cap_ptr;
- u32 pmecap;
-
- if (!pi->pmecap_offset) {
- cap_ptr =
- pcicore_find_pci_capability(pi->dev,
- PCI_CAP_POWERMGMTCAP_ID, NULL,
- NULL);
- if (!cap_ptr)
- return false;
-
- pi->pmecap_offset = cap_ptr;
-
- pci_read_config_dword(pi->dev, pi->pmecap_offset,
- &pmecap);
-
- /* At least one state can generate PME */
- pi->pmecap = (pmecap & PME_CAP_PM_STATES) != 0;
- }
-
- return pi->pmecap;
-}
-
-/* Enable PME generation */
-void pcicore_pmeen(void *pch)
-{
- pcicore_info_t *pi = (pcicore_info_t *) pch;
- u32 w;
-
- /* if not pmecapable return */
- if (!pcicore_pmecap(pi))
- return;
-
- pci_read_config_dword(pi->dev, pi->pmecap_offset + PME_CSR_OFFSET,
- &w);
- w |= (PME_CSR_PME_EN);
- pci_write_config_dword(pi->dev,
- pi->pmecap_offset + PME_CSR_OFFSET, w);
-}
-
-/*
- * Return true if PME status set
- */
-bool pcicore_pmestat(void *pch)
-{
- pcicore_info_t *pi = (pcicore_info_t *) pch;
- u32 w;
-
- if (!pcicore_pmecap(pi))
- return false;
-
- pci_read_config_dword(pi->dev, pi->pmecap_offset + PME_CSR_OFFSET,
- &w);
-
- return (w & PME_CSR_PME_STAT) == PME_CSR_PME_STAT;
-}
-
-/* Disable PME generation, clear the PME status bit if set
- */
-void pcicore_pmeclr(void *pch)
-{
- pcicore_info_t *pi = (pcicore_info_t *) pch;
- u32 w;
-
- if (!pcicore_pmecap(pi))
- return;
-
- pci_read_config_dword(pi->dev, pi->pmecap_offset + PME_CSR_OFFSET,
- &w);
-
- PCI_ERROR(("pcicore_pci_pmeclr PMECSR : 0x%x\n", w));
-
- /* PMESTAT is cleared by writing 1 to it */
- w &= ~(PME_CSR_PME_EN);
-
- pci_write_config_dword(pi->dev,
- pi->pmecap_offset + PME_CSR_OFFSET, w);
-}
-
-u32 pcie_lcreg(void *pch, u32 mask, u32 val)
-{
- pcicore_info_t *pi = (pcicore_info_t *) pch;
- u8 offset;
- u32 tmpval;
-
- offset = pi->pciecap_lcreg_offset;
- if (!offset)
- return 0;
-
- /* set operation */
- if (mask)
- pci_write_config_dword(pi->dev, offset, val);
-
- pci_read_config_dword(pi->dev, offset, &tmpval);
- return tmpval;
-}
-
-u32
-pcicore_pciereg(void *pch, u32 offset, u32 mask, u32 val, uint type)
-{
- u32 reg_val = 0;
- pcicore_info_t *pi = (pcicore_info_t *) pch;
- sbpcieregs_t *pcieregs = pi->regs.pcieregs;
-
- if (mask) {
- PCI_ERROR(("PCIEREG: 0x%x writeval 0x%x\n", offset, val));
- pcie_writereg(pcieregs, type, offset, val);
- }
-
- /* Should not read register 0x154 */
- if (pi->sih->buscorerev <= 5 && offset == PCIE_DLLP_PCIE11
- && type == PCIE_PCIEREGS)
- return reg_val;
-
- reg_val = pcie_readreg(pcieregs, type, offset);
- PCI_ERROR(("PCIEREG: 0x%x readval is 0x%x\n", offset, reg_val));
-
- return reg_val;
-}
-
-u32
-pcicore_pcieserdesreg(void *pch, u32 mdioslave, u32 offset, u32 mask,
- u32 val)
-{
- u32 reg_val = 0;
- pcicore_info_t *pi = (pcicore_info_t *) pch;
-
- if (mask) {
- PCI_ERROR(("PCIEMDIOREG: 0x%x writeval 0x%x\n", offset, val));
- pcie_mdiowrite(pi, mdioslave, offset, val);
- }
-
- if (pcie_mdioread(pi, mdioslave, offset, ®_val))
- reg_val = 0xFFFFFFFF;
- PCI_ERROR(("PCIEMDIOREG: dev 0x%x offset 0x%x read 0x%x\n", mdioslave,
- offset, reg_val));
-
- return reg_val;
-}
diff --git a/drivers/staging/brcm80211/util/nvram/nvram_ro.c b/drivers/staging/brcm80211/util/nvram/nvram_ro.c
deleted file mode 100644
index a697ff1..0000000
--- a/drivers/staging/brcm80211/util/nvram/nvram_ro.c
+++ /dev/null
@@ -1,207 +0,0 @@
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#include <linux/slab.h>
-#include <linux/string.h>
-#include <bcmdefs.h>
-#include <bcmutils.h>
-#include <siutils.h>
-#include <bcmnvram.h>
-#include <sbchipc.h>
-#include <bcmsrom.h>
-#include <bcmotp.h>
-#include <bcmdevs.h>
-#include <hndsoc.h>
-
-#define NVR_MSG(x)
-
-typedef struct _vars {
- struct _vars *next;
- int bufsz; /* allocated size */
- int size; /* actual vars size */
- char *vars;
-} vars_t;
-
-#define VARS_T_OH sizeof(vars_t)
-
-static vars_t *vars;
-
-#define NVRAM_FILE 1
-
-static char *findvar(char *vars, char *lim, const char *name);
-
-#if defined(FLASH)
-/* copy flash to ram */
-static void get_flash_nvram(si_t *sih, struct nvram_header *nvh)
-{
- uint nvs, bufsz;
- vars_t *new;
-
- nvs = R_REG(&nvh->len) - sizeof(struct nvram_header);
- bufsz = nvs + VARS_T_OH;
-
- new = kmalloc(bufsz, GFP_ATOMIC);
- if (new == NULL) {
- NVR_MSG(("Out of memory for flash vars\n"));
- return;
- }
- new->vars = (char *)new + VARS_T_OH;
-
- new->bufsz = bufsz;
- new->size = nvs;
- new->next = vars;
- vars = new;
-
- memcpy(new->vars, &nvh[1], nvs);
-
- NVR_MSG(("%s: flash nvram @ %p, copied %d bytes to %p\n", __func__,
- nvh, nvs, new->vars));
-}
-#endif /* FLASH */
-
-int nvram_init(void *si)
-{
-
- /* Make sure we read nvram in flash just once before freeing the memory */
- if (vars != NULL) {
- NVR_MSG(("nvram_init: called again without calling nvram_exit()\n"));
- return 0;
- }
- return 0;
-}
-
-int nvram_append(void *si, char *varlst, uint varsz)
-{
- uint bufsz = VARS_T_OH;
- vars_t *new;
-
- new = kmalloc(bufsz, GFP_ATOMIC);
- if (new == NULL)
- return BCME_NOMEM;
-
- new->vars = varlst;
- new->bufsz = bufsz;
- new->size = varsz;
- new->next = vars;
- vars = new;
-
- return BCME_OK;
-}
-
-void nvram_exit(void *si)
-{
- vars_t *this, *next;
- si_t *sih;
-
- sih = (si_t *) si;
- this = vars;
-
- if (this)
- kfree(this->vars);
-
- while (this) {
- next = this->next;
- kfree(this);
- this = next;
- }
- vars = NULL;
-}
-
-static char *findvar(char *vars, char *lim, const char *name)
-{
- char *s;
- int len;
-
- len = strlen(name);
-
- for (s = vars; (s < lim) && *s;) {
- if ((memcmp(s, name, len) == 0) && (s[len] == '='))
- return &s[len + 1];
-
- while (*s++)
- ;
- }
-
- return NULL;
-}
-
-char *nvram_get(const char *name)
-{
- char *v = NULL;
- vars_t *cur;
-
- for (cur = vars; cur; cur = cur->next) {
- v = findvar(cur->vars, cur->vars + cur->size, name);
- if (v)
- break;
- }
-
- return v;
-}
-
-int nvram_set(const char *name, const char *value)
-{
- return 0;
-}
-
-int nvram_unset(const char *name)
-{
- return 0;
-}
-
-int nvram_reset(void *si)
-{
- return 0;
-}
-
-int nvram_commit(void)
-{
- return 0;
-}
-
-int nvram_getall(char *buf, int count)
-{
- int len, resid = count;
- vars_t *this;
-
- this = vars;
- while (this) {
- char *from, *lim, *to;
- int acc;
-
- from = this->vars;
- lim = (char *)(this->vars + this->size);
- to = buf;
- acc = 0;
- while ((from < lim) && (*from)) {
- len = strlen(from) + 1;
- if (resid < (acc + len))
- return BCME_BUFTOOSHORT;
- memcpy(to, from, len);
- acc += len;
- from += len;
- to += len;
- }
-
- resid -= acc;
- buf += acc;
- this = this->next;
- }
- if (resid < 1)
- return BCME_BUFTOOSHORT;
- *buf = '\0';
- return 0;
-}
diff --git a/drivers/staging/brcm80211/util/qmath.c b/drivers/staging/brcm80211/util/qmath.c
deleted file mode 100644
index 40c9929..0000000
--- a/drivers/staging/brcm80211/util/qmath.c
+++ /dev/null
@@ -1,681 +0,0 @@
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#include <linux/types.h>
-#include "qmath.h"
-
-/*
-Description: This function saturate input 32 bit number into a 16 bit number.
-If input number is greater than 0x7fff then output is saturated to 0x7fff.
-else if input number is less than 0xffff8000 then output is saturated to 0xffff8000
-else output is same as input.
-*/
-s16 qm_sat32(s32 op)
-{
- s16 result;
- if (op > (s32) 0x7fff) {
- result = 0x7fff;
- } else if (op < (s32) 0xffff8000) {
- result = (s16) (0x8000);
- } else {
- result = (s16) op;
- }
- return result;
-}
-
-/*
-Description: This function multiply two input 16 bit numbers and return the 32 bit result.
-This multiplication is similar to compiler multiplication. This operation is defined if
-16 bit multiplication on the processor platform is cheaper than 32 bit multiplication (as
-the most of qmath functions can be replaced with processor intrinsic instructions).
-*/
-s32 qm_mul321616(s16 op1, s16 op2)
-{
- return (s32) (op1) * (s32) (op2);
-}
-
-/*
-Description: This function make 16 bit multiplication and return the result in 16 bits.
-To fit the result into 16 bits the 32 bit multiplication result is right
-shifted by 16 bits.
-*/
-s16 qm_mul16(s16 op1, s16 op2)
-{
- s32 result;
- result = ((s32) (op1) * (s32) (op2));
- return (s16) (result >> 16);
-}
-
-/*
-Description: This function multiply two 16 bit numbers and return the result in 32 bits.
-This function remove the extra sign bit created by the multiplication by leftshifting the
-32 bit multiplication result by 1 bit before returning the result. So the output is
-twice that of compiler multiplication. (i.e. qm_muls321616(2,3)=12).
-When both input 16 bit numbers are 0x8000, then the result is saturated to 0x7fffffff.
-*/
-s32 qm_muls321616(s16 op1, s16 op2)
-{
- s32 result;
- if (op1 == (s16) (0x8000) && op2 == (s16) (0x8000)) {
- result = 0x7fffffff;
- } else {
- result = ((s32) (op1) * (s32) (op2));
- result = result << 1;
- }
- return result;
-}
-
-/*
-Description: This function make 16 bit unsigned multiplication. To fit the output into
-16 bits the 32 bit multiplication result is right shifted by 16 bits.
-*/
-u16 qm_mulu16(u16 op1, u16 op2)
-{
- return (u16) (((u32) op1 * (u32) op2) >> 16);
-}
-
-/*
-Description: This function make 16 bit multiplication and return the result in 16 bits.
-To fit the multiplication result into 16 bits the multiplication result is right shifted by
-15 bits. Right shifting 15 bits instead of 16 bits is done to remove the extra sign bit formed
-due to the multiplication.
-When both the 16bit inputs are 0x8000 then the output is saturated to 0x7fffffff.
-*/
-s16 qm_muls16(s16 op1, s16 op2)
-{
- s32 result;
- if (op1 == (s16) 0x8000 && op2 == (s16) 0x8000) {
- result = 0x7fffffff;
- } else {
- result = ((s32) (op1) * (s32) (op2));
- }
- return (s16) (result >> 15);
-}
-
-/*
-Description: This function add two 32 bit numbers and return the 32bit result.
-If the result overflow 32 bits, the output will be saturated to 32bits.
-*/
-s32 qm_add32(s32 op1, s32 op2)
-{
- s32 result;
- result = op1 + op2;
- if (op1 < 0 && op2 < 0 && result > 0) {
- result = 0x80000000;
- } else if (op1 > 0 && op2 > 0 && result < 0) {
- result = 0x7fffffff;
- }
- return result;
-}
-
-/*
-Description: This function add two 16 bit numbers and return the 16bit result.
-If the result overflow 16 bits, the output will be saturated to 16bits.
-*/
-s16 qm_add16(s16 op1, s16 op2)
-{
- s16 result;
- s32 temp = (s32) op1 + (s32) op2;
- if (temp > (s32) 0x7fff) {
- result = (s16) 0x7fff;
- } else if (temp < (s32) 0xffff8000) {
- result = (s16) 0xffff8000;
- } else {
- result = (s16) temp;
- }
- return result;
-}
-
-/*
-Description: This function make 16 bit subtraction and return the 16bit result.
-If the result overflow 16 bits, the output will be saturated to 16bits.
-*/
-s16 qm_sub16(s16 op1, s16 op2)
-{
- s16 result;
- s32 temp = (s32) op1 - (s32) op2;
- if (temp > (s32) 0x7fff) {
- result = (s16) 0x7fff;
- } else if (temp < (s32) 0xffff8000) {
- result = (s16) 0xffff8000;
- } else {
- result = (s16) temp;
- }
- return result;
-}
-
-/*
-Description: This function make 32 bit subtraction and return the 32bit result.
-If the result overflow 32 bits, the output will be saturated to 32bits.
-*/
-s32 qm_sub32(s32 op1, s32 op2)
-{
- s32 result;
- result = op1 - op2;
- if (op1 >= 0 && op2 < 0 && result < 0) {
- result = 0x7fffffff;
- } else if (op1 < 0 && op2 > 0 && result > 0) {
- result = 0x80000000;
- }
- return result;
-}
-
-/*
-Description: This function multiply input 16 bit numbers and accumulate the result
-into the input 32 bit number and return the 32 bit accumulated result.
-If the accumulation result in overflow, then the output will be saturated.
-*/
-s32 qm_mac321616(s32 acc, s16 op1, s16 op2)
-{
- s32 result;
- result = qm_add32(acc, qm_mul321616(op1, op2));
- return result;
-}
-
-/*
-Description: This function make a 32 bit saturated left shift when the specified shift
-is +ve. This function will make a 32 bit right shift when the specified shift is -ve.
-This function return the result after shifting operation.
-*/
-s32 qm_shl32(s32 op, int shift)
-{
- int i;
- s32 result;
- result = op;
- if (shift > 31)
- shift = 31;
- else if (shift < -31)
- shift = -31;
- if (shift >= 0) {
- for (i = 0; i < shift; i++) {
- result = qm_add32(result, result);
- }
- } else {
- result = result >> (-shift);
- }
- return result;
-}
-
-/*
-Description: This function make a 32 bit right shift when shift is +ve.
-This function make a 32 bit saturated left shift when shift is -ve. This function
-return the result of the shift operation.
-*/
-s32 qm_shr32(s32 op, int shift)
-{
- return qm_shl32(op, -shift);
-}
-
-/*
-Description: This function make a 16 bit saturated left shift when the specified shift
-is +ve. This function will make a 16 bit right shift when the specified shift is -ve.
-This function return the result after shifting operation.
-*/
-s16 qm_shl16(s16 op, int shift)
-{
- int i;
- s16 result;
- result = op;
- if (shift > 15)
- shift = 15;
- else if (shift < -15)
- shift = -15;
- if (shift > 0) {
- for (i = 0; i < shift; i++) {
- result = qm_add16(result, result);
- }
- } else {
- result = result >> (-shift);
- }
- return result;
-}
-
-/*
-Description: This function make a 16 bit right shift when shift is +ve.
-This function make a 16 bit saturated left shift when shift is -ve. This function
-return the result of the shift operation.
-*/
-s16 qm_shr16(s16 op, int shift)
-{
- return qm_shl16(op, -shift);
-}
-
-/*
-Description: This function return the number of redundant sign bits in a 16 bit number.
-Example: qm_norm16(0x0080) = 7.
-*/
-s16 qm_norm16(s16 op)
-{
- u16 u16extraSignBits;
- if (op == 0) {
- return 15;
- } else {
- u16extraSignBits = 0;
- while ((op >> 15) == (op >> 14)) {
- u16extraSignBits++;
- op = op << 1;
- }
- }
- return u16extraSignBits;
-}
-
-/*
-Description: This function return the number of redundant sign bits in a 32 bit number.
-Example: qm_norm32(0x00000080) = 23
-*/
-s16 qm_norm32(s32 op)
-{
- u16 u16extraSignBits;
- if (op == 0) {
- return 31;
- } else {
- u16extraSignBits = 0;
- while ((op >> 31) == (op >> 30)) {
- u16extraSignBits++;
- op = op << 1;
- }
- }
- return u16extraSignBits;
-}
-
-/*
-Description: This function divide two 16 bit unsigned numbers.
-The numerator should be less than denominator. So the quotient is always less than 1.
-This function return the quotient in q.15 format.
-*/
-s16 qm_div_s(s16 num, s16 denom)
-{
- s16 var_out;
- s16 iteration;
- s32 L_num;
- s32 L_denom;
- L_num = (num) << 15;
- L_denom = (denom) << 15;
- for (iteration = 0; iteration < 15; iteration++) {
- L_num <<= 1;
- if (L_num >= L_denom) {
- L_num = qm_sub32(L_num, L_denom);
- L_num = qm_add32(L_num, 1);
- }
- }
- var_out = (s16) (L_num & 0x7fff);
- return var_out;
-}
-
-/*
-Description: This function compute the absolute value of a 16 bit number.
-*/
-s16 qm_abs16(s16 op)
-{
- if (op < 0) {
- if (op == (s16) 0xffff8000) {
- return 0x7fff;
- } else {
- return -op;
- }
- } else {
- return op;
- }
-}
-
-/*
-Description: This function divide two 16 bit numbers.
-The quotient is returned through return value.
-The qformat of the quotient is returned through the pointer (qQuotient) passed
-to this function. The qformat of quotient is adjusted appropriately such that
-the quotient occupies all 16 bits.
-*/
-s16 qm_div16(s16 num, s16 denom, s16 *qQuotient)
-{
- s16 sign;
- s16 nNum, nDenom;
- sign = num ^ denom;
- num = qm_abs16(num);
- denom = qm_abs16(denom);
- nNum = qm_norm16(num);
- nDenom = qm_norm16(denom);
- num = qm_shl16(num, nNum - 1);
- denom = qm_shl16(denom, nDenom);
- *qQuotient = nNum - 1 - nDenom + 15;
- if (sign >= 0) {
- return qm_div_s(num, denom);
- } else {
- return -qm_div_s(num, denom);
- }
-}
-
-/*
-Description: This function compute absolute value of a 32 bit number.
-*/
-s32 qm_abs32(s32 op)
-{
- if (op < 0) {
- if (op == (s32) 0x80000000) {
- return 0x7fffffff;
- } else {
- return -op;
- }
- } else {
- return op;
- }
-}
-
-/*
-Description: This function divide two 32 bit numbers. The division is performed
-by considering only important 16 bits in 32 bit numbers.
-The quotient is returned through return value.
-The qformat of the quotient is returned through the pointer (qquotient) passed
-to this function. The qformat of quotient is adjusted appropriately such that
-the quotient occupies all 16 bits.
-*/
-s16 qm_div163232(s32 num, s32 denom, s16 *qquotient)
-{
- s32 sign;
- s16 nNum, nDenom;
- sign = num ^ denom;
- num = qm_abs32(num);
- denom = qm_abs32(denom);
- nNum = qm_norm32(num);
- nDenom = qm_norm32(denom);
- num = qm_shl32(num, nNum - 1);
- denom = qm_shl32(denom, nDenom);
- *qquotient = nNum - 1 - nDenom + 15;
- if (sign >= 0) {
- return qm_div_s((s16) (num >> 16), (s16) (denom >> 16));
- } else {
- return -qm_div_s((s16) (num >> 16), (s16) (denom >> 16));
- }
-}
-
-/*
-Description: This function multiply a 32 bit number with a 16 bit number.
-The multiplicaton result is right shifted by 16 bits to fit the result
-into 32 bit output.
-*/
-s32 qm_mul323216(s32 op1, s16 op2)
-{
- s16 hi;
- u16 lo;
- s32 result;
- hi = op1 >> 16;
- lo = (s16) (op1 & 0xffff);
- result = qm_mul321616(hi, op2);
- result = result + (qm_mulsu321616(op2, lo) >> 16);
- return result;
-}
-
-/*
-Description: This function multiply signed 16 bit number with unsigned 16 bit number and return
-the result in 32 bits.
-*/
-s32 qm_mulsu321616(s16 op1, u16 op2)
-{
- return (s32) (op1) * op2;
-}
-
-/*
-Description: This function multiply 32 bit number with 16 bit number. The multiplication result is
-right shifted by 15 bits to fit the result into 32 bits. Right shifting by only 15 bits instead of
-16 bits is done to remove the extra sign bit formed by multiplication from the return value.
-When the input numbers are 0x80000000, 0x8000 the return value is saturated to 0x7fffffff.
-*/
-s32 qm_muls323216(s32 op1, s16 op2)
-{
- s16 hi;
- u16 lo;
- s32 result;
- hi = op1 >> 16;
- lo = (s16) (op1 & 0xffff);
- result = qm_muls321616(hi, op2);
- result = qm_add32(result, (qm_mulsu321616(op2, lo) >> 15));
- return result;
-}
-
-/*
-Description: This function multiply two 32 bit numbers. The multiplication result is right
-shifted by 32 bits to fit the multiplication result into 32 bits. The right shifted
-multiplication result is returned as output.
-*/
-s32 qm_mul32(s32 a, s32 b)
-{
- s16 hi1, hi2;
- u16 lo1, lo2;
- s32 result;
- hi1 = a >> 16;
- hi2 = b >> 16;
- lo1 = (u16) (a & 0xffff);
- lo2 = (u16) (b & 0xffff);
- result = qm_mul321616(hi1, hi2);
- result = result + (qm_mulsu321616(hi1, lo2) >> 16);
- result = result + (qm_mulsu321616(hi2, lo1) >> 16);
- return result;
-}
-
-/*
-Description: This function multiply two 32 bit numbers. The multiplication result is
-right shifted by 31 bits to fit the multiplication result into 32 bits. The right
-shifted multiplication result is returned as output. Right shifting by only 31 bits
-instead of 32 bits is done to remove the extra sign bit formed by multiplication.
-When the input numbers are 0x80000000, 0x80000000 the return value is saturated to
-0x7fffffff.
-*/
-s32 qm_muls32(s32 a, s32 b)
-{
- s16 hi1, hi2;
- u16 lo1, lo2;
- s32 result;
- hi1 = a >> 16;
- hi2 = b >> 16;
- lo1 = (u16) (a & 0xffff);
- lo2 = (u16) (b & 0xffff);
- result = qm_muls321616(hi1, hi2);
- result = qm_add32(result, (qm_mulsu321616(hi1, lo2) >> 15));
- result = qm_add32(result, (qm_mulsu321616(hi2, lo1) >> 15));
- result = qm_add32(result, (qm_mulu16(lo1, lo2) >> 15));
- return result;
-}
-
-/* This table is log2(1+(i/32)) where i=[0:1:31], in q.15 format */
-static const s16 log_table[] = {
- 0,
- 1455,
- 2866,
- 4236,
- 5568,
- 6863,
- 8124,
- 9352,
- 10549,
- 11716,
- 12855,
- 13968,
- 15055,
- 16117,
- 17156,
- 18173,
- 19168,
- 20143,
- 21098,
- 22034,
- 22952,
- 23852,
- 24736,
- 25604,
- 26455,
- 27292,
- 28114,
- 28922,
- 29717,
- 30498,
- 31267,
- 32024
-};
-
-#define LOG_TABLE_SIZE 32 /* log_table size */
-#define LOG2_LOG_TABLE_SIZE 5 /* log2(log_table size) */
-#define Q_LOG_TABLE 15 /* qformat of log_table */
-#define LOG10_2 19728 /* log10(2) in q.16 */
-
-/*
-Description:
-This routine takes the input number N and its q format qN and compute
-the log10(N). This routine first normalizes the input no N. Then N is in mag*(2^x) format.
-mag is any number in the range 2^30-(2^31 - 1). Then log2(mag * 2^x) = log2(mag) + x is computed.
-From that log10(mag * 2^x) = log2(mag * 2^x) * log10(2) is computed.
-This routine looks the log2 value in the table considering LOG2_LOG_TABLE_SIZE+1 MSBs.
-As the MSB is always 1, only next LOG2_OF_LOG_TABLE_SIZE MSBs are used for table lookup.
-Next 16 MSBs are used for interpolation.
-Inputs:
-N - number to which log10 has to be found.
-qN - q format of N
-log10N - address where log10(N) will be written.
-qLog10N - address where log10N qformat will be written.
-Note/Problem:
-For accurate results input should be in normalized or near normalized form.
-*/
-void qm_log10(s32 N, s16 qN, s16 *log10N, s16 *qLog10N)
-{
- s16 s16norm, s16tableIndex, s16errorApproximation;
- u16 u16offset;
- s32 s32log;
-
- /* Logerithm of negative values is undefined.
- * assert N is greater than 0.
- */
- /* ASSERT(N > 0); */
-
- /* normalize the N. */
- s16norm = qm_norm32(N);
- N = N << s16norm;
-
- /* The qformat of N after normalization.
- * -30 is added to treat the no as between 1.0 to 2.0
- * i.e. after adding the -30 to the qformat the decimal point will be
- * just rigtht of the MSB. (i.e. after sign bit and 1st MSB). i.e.
- * at the right side of 30th bit.
- */
- qN = qN + s16norm - 30;
-
- /* take the table index as the LOG2_OF_LOG_TABLE_SIZE bits right of the MSB */
- s16tableIndex = (s16) (N >> (32 - (2 + LOG2_LOG_TABLE_SIZE)));
-
- /* remove the MSB. the MSB is always 1 after normalization. */
- s16tableIndex =
- s16tableIndex & (s16) ((1 << LOG2_LOG_TABLE_SIZE) - 1);
-
- /* remove the (1+LOG2_OF_LOG_TABLE_SIZE) MSBs in the N. */
- N = N & ((1 << (32 - (2 + LOG2_LOG_TABLE_SIZE))) - 1);
-
- /* take the offset as the 16 MSBS after table index.
- */
- u16offset = (u16) (N >> (32 - (2 + LOG2_LOG_TABLE_SIZE + 16)));
-
- /* look the log value in the table. */
- s32log = log_table[s16tableIndex]; /* q.15 format */
-
- /* interpolate using the offset. */
- s16errorApproximation = (s16) qm_mulu16(u16offset, (u16) (log_table[s16tableIndex + 1] - log_table[s16tableIndex])); /* q.15 */
-
- s32log = qm_add16((s16) s32log, s16errorApproximation); /* q.15 format */
-
- /* adjust for the qformat of the N as
- * log2(mag * 2^x) = log2(mag) + x
- */
- s32log = qm_add32(s32log, ((s32) -qN) << 15); /* q.15 format */
-
- /* normalize the result. */
- s16norm = qm_norm32(s32log);
-
- /* bring all the important bits into lower 16 bits */
- s32log = qm_shl32(s32log, s16norm - 16); /* q.15+s16norm-16 format */
-
- /* compute the log10(N) by multiplying log2(N) with log10(2).
- * as log10(mag * 2^x) = log2(mag * 2^x) * log10(2)
- * log10N in q.15+s16norm-16+1 (LOG10_2 is in q.16)
- */
- *log10N = qm_muls16((s16) s32log, (s16) LOG10_2);
-
- /* write the q format of the result. */
- *qLog10N = 15 + s16norm - 16 + 1;
-
- return;
-}
-
-/*
-Description:
-This routine compute 1/N.
-This routine reformates the given no N as N * 2^qN where N is in between 0.5 and 1.0
-in q.15 format in 16 bits. So the problem now boils down to finding the inverse of a
-q.15 no in 16 bits which is in the range of 0.5 to 1.0. The output is always between
-2.0 to 1. So the output is 2.0 to 1.0 in q.30 format. Once the final output format is found
-by taking the qN into account. Inverse is found with newton rapson method. Initially
-inverse (x) is guessed as 1/0.75 (with appropriate sign). The new guess is calculated
-using the formula x' = 2*x - N*x*x. After 4 or 5 iterations the inverse is very close to
-inverse of N.
-Inputs:
-N - number to which 1/N has to be found.
-qn - q format of N.
-sqrtN - address where 1/N has to be written.
-qsqrtN - address where q format of 1/N has to be written.
-*/
-#define qx 29
-void qm_1byN(s32 N, s16 qN, s32 *result, s16 *qResult)
-{
- s16 normN;
- s32 s32firstTerm, s32secondTerm, x;
- int i;
-
- normN = qm_norm32(N);
-
- /* limit N to least significant 16 bits. 15th bit is the sign bit. */
- N = qm_shl32(N, normN - 16);
- qN = qN + normN - 16 - 15;
- /* -15 is added to treat N as 16 bit q.15 number in the range from 0.5 to 1 */
-
- /* Take the initial guess as 1/0.75 in qx format with appropriate sign. */
- if (N >= 0) {
- x = (s32) ((1 / 0.75) * (1 << qx));
- /* input no is in the range 0.5 to 1. So 1/0.75 is taken as initial guess. */
- } else {
- x = (s32) ((1 / -0.75) * (1 << qx));
- /* input no is in the range -0.5 to -1. So 1/-0.75 is taken as initial guess. */
- }
-
- /* iterate the equation x = 2*x - N*x*x for 4 times. */
- for (i = 0; i < 4; i++) {
- s32firstTerm = qm_shl32(x, 1); /* s32firstTerm = 2*x in q.29 */
- s32secondTerm =
- qm_muls321616((s16) (s32firstTerm >> 16),
- (s16) (s32firstTerm >> 16));
- /* s32secondTerm = x*x in q.(29+1-16)*2+1 */
- s32secondTerm =
- qm_muls321616((s16) (s32secondTerm >> 16), (s16) N);
- /* s32secondTerm = N*x*x in q.((29+1-16)*2+1)-16+15+1 i.e. in q.29 */
- x = qm_sub32(s32firstTerm, s32secondTerm);
- /* can be added directly as both are in q.29 */
- }
-
- /* Bring the x to q.30 format. */
- *result = qm_shl32(x, 1);
- /* giving the output in q.30 format for q.15 input in 16 bits. */
-
- /* compute the final q format of the result. */
- *qResult = -qN + 30; /* adjusting the q format of actual output */
-
- return;
-}
-
-#undef qx
diff --git a/drivers/staging/brcm80211/util/sbpcmcia.h b/drivers/staging/brcm80211/util/sbpcmcia.h
deleted file mode 100644
index d4c1565..0000000
--- a/drivers/staging/brcm80211/util/sbpcmcia.h
+++ /dev/null
@@ -1,217 +0,0 @@
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#ifndef _SBPCMCIA_H
-#define _SBPCMCIA_H
-
-/* All the addresses that are offsets in attribute space are divided
- * by two to account for the fact that odd bytes are invalid in
- * attribute space and our read/write routines make the space appear
- * as if they didn't exist. Still we want to show the original numbers
- * as documented in the hnd_pcmcia core manual.
- */
-
-/* PCMCIA Function Configuration Registers */
-#define PCMCIA_FCR (0x700 / 2)
-
-#define FCR0_OFF 0
-#define FCR1_OFF (0x40 / 2)
-#define FCR2_OFF (0x80 / 2)
-#define FCR3_OFF (0xc0 / 2)
-
-#define PCMCIA_FCR0 (0x700 / 2)
-#define PCMCIA_FCR1 (0x740 / 2)
-#define PCMCIA_FCR2 (0x780 / 2)
-#define PCMCIA_FCR3 (0x7c0 / 2)
-
-/* Standard PCMCIA FCR registers */
-
-#define PCMCIA_COR 0
-
-#define COR_RST 0x80
-#define COR_LEV 0x40
-#define COR_IRQEN 0x04
-#define COR_BLREN 0x01
-#define COR_FUNEN 0x01
-
-#define PCICIA_FCSR (2 / 2)
-#define PCICIA_PRR (4 / 2)
-#define PCICIA_SCR (6 / 2)
-#define PCICIA_ESR (8 / 2)
-
-#define PCM_MEMOFF 0x0000
-#define F0_MEMOFF 0x1000
-#define F1_MEMOFF 0x2000
-#define F2_MEMOFF 0x3000
-#define F3_MEMOFF 0x4000
-
-/* Memory base in the function fcr's */
-#define MEM_ADDR0 (0x728 / 2)
-#define MEM_ADDR1 (0x72a / 2)
-#define MEM_ADDR2 (0x72c / 2)
-
-/* PCMCIA base plus Srom access in fcr0: */
-#define PCMCIA_ADDR0 (0x072e / 2)
-#define PCMCIA_ADDR1 (0x0730 / 2)
-#define PCMCIA_ADDR2 (0x0732 / 2)
-
-#define MEM_SEG (0x0734 / 2)
-#define SROM_CS (0x0736 / 2)
-#define SROM_DATAL (0x0738 / 2)
-#define SROM_DATAH (0x073a / 2)
-#define SROM_ADDRL (0x073c / 2)
-#define SROM_ADDRH (0x073e / 2)
-#define SROM_INFO2 (0x0772 / 2) /* Corerev >= 2 && <= 5 */
-#define SROM_INFO (0x07be / 2) /* Corerev >= 6 */
-
-/* Values for srom_cs: */
-#define SROM_IDLE 0
-#define SROM_WRITE 1
-#define SROM_READ 2
-#define SROM_WEN 4
-#define SROM_WDS 7
-#define SROM_DONE 8
-
-/* Fields in srom_info: */
-#define SRI_SZ_MASK 0x03
-#define SRI_BLANK 0x04
-#define SRI_OTP 0x80
-
-#if !defined(ESTA_POSTMOGRIFY_REMOVAL)
-/* CIS stuff */
-
-/* The CIS stops where the FCRs start */
-#define CIS_SIZE PCMCIA_FCR
-
-/* CIS tuple length field max */
-#define CIS_TUPLE_LEN_MAX 0xff
-
-/* Standard tuples we know about */
-
-#define CISTPL_NULL 0x00
-#define CISTPL_VERS_1 0x15 /* CIS ver, manf, dev & ver strings */
-#define CISTPL_MANFID 0x20 /* Manufacturer and device id */
-#define CISTPL_FUNCID 0x21 /* Function identification */
-#define CISTPL_FUNCE 0x22 /* Function extensions */
-#define CISTPL_CFTABLE 0x1b /* Config table entry */
-#define CISTPL_END 0xff /* End of the CIS tuple chain */
-
-/* Function identifier provides context for the function extensions tuple */
-#define CISTPL_FID_SDIO 0x0c /* Extensions defined by SDIO spec */
-
-/* Function extensions for LANs (assumed for extensions other than SDIO) */
-#define LAN_TECH 1 /* Technology type */
-#define LAN_SPEED 2 /* Raw bit rate */
-#define LAN_MEDIA 3 /* Transmission media */
-#define LAN_NID 4 /* Node identification (aka MAC addr) */
-#define LAN_CONN 5 /* Connector standard */
-
-/* CFTable */
-#define CFTABLE_REGWIN_2K 0x08 /* 2k reg windows size */
-#define CFTABLE_REGWIN_4K 0x10 /* 4k reg windows size */
-#define CFTABLE_REGWIN_8K 0x20 /* 8k reg windows size */
-
-/* Vendor unique tuples are 0x80-0x8f. Within Broadcom we'll
- * take one for HNBU, and use "extensions" (a la FUNCE) within it.
- */
-
-#define CISTPL_BRCM_HNBU 0x80
-
-/* Subtypes of BRCM_HNBU: */
-
-#define HNBU_SROMREV 0x00 /* A byte with sromrev, 1 if not present */
-#define HNBU_CHIPID 0x01 /* Two 16bit values: PCI vendor & device id */
-#define HNBU_BOARDREV 0x02 /* One byte board revision */
-#define HNBU_PAPARMS 0x03 /* PA parameters: 8 (sromrev == 1)
- * or 9 (sromrev > 1) bytes
- */
-#define HNBU_OEM 0x04 /* Eight bytes OEM data (sromrev == 1) */
-#define HNBU_CC 0x05 /* Default country code (sromrev == 1) */
-#define HNBU_AA 0x06 /* Antennas available */
-#define HNBU_AG 0x07 /* Antenna gain */
-#define HNBU_BOARDFLAGS 0x08 /* board flags (2 or 4 bytes) */
-#define HNBU_LEDS 0x09 /* LED set */
-#define HNBU_CCODE 0x0a /* Country code (2 bytes ascii + 1 byte cctl)
- * in rev 2
- */
-#define HNBU_CCKPO 0x0b /* 2 byte cck power offsets in rev 3 */
-#define HNBU_OFDMPO 0x0c /* 4 byte 11g ofdm power offsets in rev 3 */
-#define HNBU_GPIOTIMER 0x0d /* 2 bytes with on/off values in rev 3 */
-#define HNBU_PAPARMS5G 0x0e /* 5G PA params */
-#define HNBU_ANT5G 0x0f /* 4328 5G antennas available/gain */
-#define HNBU_RDLID 0x10 /* 2 byte USB remote downloader (RDL) product Id */
-#define HNBU_RSSISMBXA2G 0x11 /* 4328 2G RSSI mid pt sel & board switch arch,
- * 2 bytes, rev 3.
- */
-#define HNBU_RSSISMBXA5G 0x12 /* 4328 5G RSSI mid pt sel & board switch arch,
- * 2 bytes, rev 3.
- */
-#define HNBU_XTALFREQ 0x13 /* 4 byte Crystal frequency in kilohertz */
-#define HNBU_TRI2G 0x14 /* 4328 2G TR isolation, 1 byte */
-#define HNBU_TRI5G 0x15 /* 4328 5G TR isolation, 3 bytes */
-#define HNBU_RXPO2G 0x16 /* 4328 2G RX power offset, 1 byte */
-#define HNBU_RXPO5G 0x17 /* 4328 5G RX power offset, 1 byte */
-#define HNBU_BOARDNUM 0x18 /* board serial number, independent of mac addr */
-#define HNBU_MACADDR 0x19 /* mac addr override for the standard CIS LAN_NID */
-#define HNBU_RDLSN 0x1a /* 2 bytes; serial # advertised in USB descriptor */
-#define HNBU_BOARDTYPE 0x1b /* 2 bytes; boardtype */
-#define HNBU_LEDDC 0x1c /* 2 bytes; LED duty cycle */
-#define HNBU_HNBUCIS 0x1d /* what follows is proprietary HNBU CIS format */
-#define HNBU_PAPARMS_SSLPNPHY 0x1e /* SSLPNPHY PA params */
-#define HNBU_RSSISMBXA2G_SSLPNPHY 0x1f /* SSLPNPHY RSSI mid pt sel & board switch arch */
-#define HNBU_RDLRNDIS 0x20 /* 1 byte; 1 = RDL advertises RNDIS config */
-#define HNBU_CHAINSWITCH 0x21 /* 2 byte; txchain, rxchain */
-#define HNBU_REGREV 0x22 /* 1 byte; */
-#define HNBU_FEM 0x23 /* 2 or 4 byte: 11n frontend specification */
-#define HNBU_PAPARMS_C0 0x24 /* 8 or 30 bytes: 11n pa paramater for chain 0 */
-#define HNBU_PAPARMS_C1 0x25 /* 8 or 30 bytes: 11n pa paramater for chain 1 */
-#define HNBU_PAPARMS_C2 0x26 /* 8 or 30 bytes: 11n pa paramater for chain 2 */
-#define HNBU_PAPARMS_C3 0x27 /* 8 or 30 bytes: 11n pa paramater for chain 3 */
-#define HNBU_PO_CCKOFDM 0x28 /* 6 or 18 bytes: cck2g/ofdm2g/ofdm5g power offset */
-#define HNBU_PO_MCS2G 0x29 /* 8 bytes: mcs2g power offset */
-#define HNBU_PO_MCS5GM 0x2a /* 8 bytes: mcs5g mid band power offset */
-#define HNBU_PO_MCS5GLH 0x2b /* 16 bytes: mcs5g low-high band power offset */
-#define HNBU_PO_CDD 0x2c /* 2 bytes: cdd2g/5g power offset */
-#define HNBU_PO_STBC 0x2d /* 2 bytes: stbc2g/5g power offset */
-#define HNBU_PO_40M 0x2e /* 2 bytes: 40Mhz channel 2g/5g power offset */
-#define HNBU_PO_40MDUP 0x2f /* 2 bytes: 40Mhz channel dup 2g/5g power offset */
-
-#define HNBU_RDLRWU 0x30 /* 1 byte; 1 = RDL advertises Remote Wake-up */
-#define HNBU_WPS 0x31 /* 1 byte; GPIO pin for WPS button */
-#define HNBU_USBFS 0x32 /* 1 byte; 1 = USB advertises FS mode only */
-#define HNBU_BRMIN 0x33 /* 4 byte bootloader min resource mask */
-#define HNBU_BRMAX 0x34 /* 4 byte bootloader max resource mask */
-#define HNBU_PATCH 0x35 /* bootloader patch addr(2b) & data(4b) pair */
-#define HNBU_CCKFILTTYPE 0x36 /* CCK digital filter selection options */
-#define HNBU_OFDMPO5G 0x37 /* 4 * 3 = 12 byte 11a ofdm power offsets in rev 3 */
-
-#define HNBU_USBEPNUM 0x40 /* USB endpoint numbers */
-#define HNBU_SROM3SWRGN 0x80 /* 78 bytes; srom rev 3 s/w region without crc8
- * plus extra info appended.
- */
-#define HNBU_RESERVED 0x81 /* Reserved for non-BRCM post-mfg additions */
-#define HNBU_CUSTOM1 0x82 /* 4 byte; For non-BRCM post-mfg additions */
-#define HNBU_CUSTOM2 0x83 /* Reserved; For non-BRCM post-mfg additions */
-#endif /* !defined(ESTA_POSTMOGRIFY_REMOVAL) */
-
-/* sbtmstatelow */
-#define SBTML_INT_ACK 0x40000 /* ack the sb interrupt */
-#define SBTML_INT_EN 0x20000 /* enable sb interrupt */
-
-/* sbtmstatehigh */
-#define SBTMH_INT_STATUS 0x40000 /* sb interrupt status */
-
-#endif /* _SBPCMCIA_H */
diff --git a/drivers/staging/brcm80211/util/sbsocram.h b/drivers/staging/brcm80211/util/sbsocram.h
deleted file mode 100644
index 0cfe985..0000000
--- a/drivers/staging/brcm80211/util/sbsocram.h
+++ /dev/null
@@ -1,175 +0,0 @@
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#ifndef _SBSOCRAM_H
-#define _SBSOCRAM_H
-
-#ifndef _LANGUAGE_ASSEMBLY
-
-/* cpp contortions to concatenate w/arg prescan */
-#ifndef PAD
-#define _PADLINE(line) pad ## line
-#define _XSTR(line) _PADLINE(line)
-#define PAD _XSTR(__LINE__)
-#endif /* PAD */
-
-/* Memcsocram core registers */
-typedef volatile struct sbsocramregs {
- u32 coreinfo;
- u32 bwalloc;
- u32 extracoreinfo;
- u32 biststat;
- u32 bankidx;
- u32 standbyctrl;
-
- u32 errlogstatus; /* rev 6 */
- u32 errlogaddr; /* rev 6 */
- /* used for patching rev 3 & 5 */
- u32 cambankidx;
- u32 cambankstandbyctrl;
- u32 cambankpatchctrl;
- u32 cambankpatchtblbaseaddr;
- u32 cambankcmdreg;
- u32 cambankdatareg;
- u32 cambankmaskreg;
- u32 PAD[1];
- u32 bankinfo; /* corev 8 */
- u32 PAD[15];
- u32 extmemconfig;
- u32 extmemparitycsr;
- u32 extmemparityerrdata;
- u32 extmemparityerrcnt;
- u32 extmemwrctrlandsize;
- u32 PAD[84];
- u32 workaround;
- u32 pwrctl; /* corerev >= 2 */
-} sbsocramregs_t;
-
-#endif /* _LANGUAGE_ASSEMBLY */
-
-/* Register offsets */
-#define SR_COREINFO 0x00
-#define SR_BWALLOC 0x04
-#define SR_BISTSTAT 0x0c
-#define SR_BANKINDEX 0x10
-#define SR_BANKSTBYCTL 0x14
-#define SR_PWRCTL 0x1e8
-
-/* Coreinfo register */
-#define SRCI_PT_MASK 0x00070000 /* corerev >= 6; port type[18:16] */
-#define SRCI_PT_SHIFT 16
-/* port types : SRCI_PT_<processorPT>_<backplanePT> */
-#define SRCI_PT_OCP_OCP 0
-#define SRCI_PT_AXI_OCP 1
-#define SRCI_PT_ARM7AHB_OCP 2
-#define SRCI_PT_CM3AHB_OCP 3
-#define SRCI_PT_AXI_AXI 4
-#define SRCI_PT_AHB_AXI 5
-/* corerev >= 3 */
-#define SRCI_LSS_MASK 0x00f00000
-#define SRCI_LSS_SHIFT 20
-#define SRCI_LRS_MASK 0x0f000000
-#define SRCI_LRS_SHIFT 24
-
-/* In corerev 0, the memory size is 2 to the power of the
- * base plus 16 plus to the contents of the memsize field plus 1.
- */
-#define SRCI_MS0_MASK 0xf
-#define SR_MS0_BASE 16
-
-/*
- * In corerev 1 the bank size is 2 ^ the bank size field plus 14,
- * the memory size is number of banks times bank size.
- * The same applies to rom size.
- */
-#define SRCI_ROMNB_MASK 0xf000
-#define SRCI_ROMNB_SHIFT 12
-#define SRCI_ROMBSZ_MASK 0xf00
-#define SRCI_ROMBSZ_SHIFT 8
-#define SRCI_SRNB_MASK 0xf0
-#define SRCI_SRNB_SHIFT 4
-#define SRCI_SRBSZ_MASK 0xf
-#define SRCI_SRBSZ_SHIFT 0
-
-#define SR_BSZ_BASE 14
-
-/* Standby control register */
-#define SRSC_SBYOVR_MASK 0x80000000
-#define SRSC_SBYOVR_SHIFT 31
-#define SRSC_SBYOVRVAL_MASK 0x60000000
-#define SRSC_SBYOVRVAL_SHIFT 29
-#define SRSC_SBYEN_MASK 0x01000000 /* rev >= 3 */
-#define SRSC_SBYEN_SHIFT 24
-
-/* Power control register */
-#define SRPC_PMU_STBYDIS_MASK 0x00000010 /* rev >= 3 */
-#define SRPC_PMU_STBYDIS_SHIFT 4
-#define SRPC_STBYOVRVAL_MASK 0x00000008
-#define SRPC_STBYOVRVAL_SHIFT 3
-#define SRPC_STBYOVR_MASK 0x00000007
-#define SRPC_STBYOVR_SHIFT 0
-
-/* Extra core capability register */
-#define SRECC_NUM_BANKS_MASK 0x000000F0
-#define SRECC_NUM_BANKS_SHIFT 4
-#define SRECC_BANKSIZE_MASK 0x0000000F
-#define SRECC_BANKSIZE_SHIFT 0
-
-#define SRECC_BANKSIZE(value) (1 << (value))
-
-/* CAM bank patch control */
-#define SRCBPC_PATCHENABLE 0x80000000
-
-#define SRP_ADDRESS 0x0001FFFC
-#define SRP_VALID 0x8000
-
-/* CAM bank command reg */
-#define SRCMD_WRITE 0x00020000
-#define SRCMD_READ 0x00010000
-#define SRCMD_DONE 0x80000000
-
-#define SRCMD_DONE_DLY 1000
-
-/* bankidx and bankinfo reg defines corerev >= 8 */
-#define SOCRAM_BANKINFO_SZMASK 0x3f
-#define SOCRAM_BANKIDX_ROM_MASK 0x100
-
-#define SOCRAM_BANKIDX_MEMTYPE_SHIFT 8
-/* socram bankinfo memtype */
-#define SOCRAM_MEMTYPE_RAM 0
-#define SOCRAM_MEMTYPE_R0M 1
-#define SOCRAM_MEMTYPE_DEVRAM 2
-
-#define SOCRAM_BANKINFO_REG 0x40
-#define SOCRAM_BANKIDX_REG 0x10
-#define SOCRAM_BANKINFO_STDBY_MASK 0x400
-#define SOCRAM_BANKINFO_STDBY_TIMER 0x800
-
-/* bankinfo rev >= 10 */
-#define SOCRAM_BANKINFO_DEVRAMSEL_SHIFT 13
-#define SOCRAM_BANKINFO_DEVRAMSEL_MASK 0x2000
-#define SOCRAM_BANKINFO_DEVRAMPRO_SHIFT 14
-#define SOCRAM_BANKINFO_DEVRAMPRO_MASK 0x4000
-
-/* extracoreinfo register */
-#define SOCRAM_DEVRAMBANK_MASK 0xF000
-#define SOCRAM_DEVRAMBANK_SHIFT 12
-
-/* bank info to calculate bank size */
-#define SOCRAM_BANKINFO_SZBASE 8192
-#define SOCRAM_BANKSIZE_SHIFT 13 /* SOCRAM_BANKINFO_SZBASE */
-
-#endif /* _SBSOCRAM_H */
diff --git a/drivers/staging/brcm80211/util/sbutils.c b/drivers/staging/brcm80211/util/sbutils.c
deleted file mode 100644
index 21dde8e..0000000
--- a/drivers/staging/brcm80211/util/sbutils.c
+++ /dev/null
@@ -1,476 +0,0 @@
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#include <linux/types.h>
-#include <bcmdefs.h>
-#ifdef BRCM_FULLMAC
-#include <linux/netdevice.h>
-#endif
-#include <bcmutils.h>
-#include <siutils.h>
-#include <bcmdevs.h>
-#include <hndsoc.h>
-#include <sbchipc.h>
-#include <pci_core.h>
-#include <pcicfg.h>
-#include <sbpcmcia.h>
-#include "siutils_priv.h"
-
-/* local prototypes */
-static uint _sb_coreidx(si_info_t *sii, u32 sba);
-static uint _sb_scan(si_info_t *sii, u32 sba, void *regs, uint bus,
- u32 sbba, uint ncores);
-static u32 _sb_coresba(si_info_t *sii);
-static void *_sb_setcoreidx(si_info_t *sii, uint coreidx);
-
-#define SET_SBREG(sii, r, mask, val) \
- W_SBREG((sii), (r), ((R_SBREG((sii), (r)) & ~(mask)) | (val)))
-#define REGS2SB(va) (sbconfig_t *) ((s8 *)(va) + SBCONFIGOFF)
-
-/* sonicsrev */
-#define SONICS_2_2 (SBIDL_RV_2_2 >> SBIDL_RV_SHIFT)
-#define SONICS_2_3 (SBIDL_RV_2_3 >> SBIDL_RV_SHIFT)
-
-#define R_SBREG(sii, sbr) sb_read_sbreg((sii), (sbr))
-#define W_SBREG(sii, sbr, v) sb_write_sbreg((sii), (sbr), (v))
-#define AND_SBREG(sii, sbr, v) \
- W_SBREG((sii), (sbr), (R_SBREG((sii), (sbr)) & (v)))
-#define OR_SBREG(sii, sbr, v) \
- W_SBREG((sii), (sbr), (R_SBREG((sii), (sbr)) | (v)))
-
-static u32 sb_read_sbreg(si_info_t *sii, volatile u32 *sbr)
-{
- return R_REG(sbr);
-}
-
-static void sb_write_sbreg(si_info_t *sii, volatile u32 *sbr, u32 v)
-{
- W_REG(sbr, v);
-}
-
-uint sb_coreid(si_t *sih)
-{
- si_info_t *sii;
- sbconfig_t *sb;
-
- sii = SI_INFO(sih);
- sb = REGS2SB(sii->curmap);
-
- return (R_SBREG(sii, &sb->sbidhigh) & SBIDH_CC_MASK) >>
- SBIDH_CC_SHIFT;
-}
-
-/* return core index of the core with address 'sba' */
-static uint _sb_coreidx(si_info_t *sii, u32 sba)
-{
- uint i;
-
- for (i = 0; i < sii->numcores; i++)
- if (sba == sii->coresba[i])
- return i;
- return BADIDX;
-}
-
-/* return core address of the current core */
-static u32 _sb_coresba(si_info_t *sii)
-{
- u32 sbaddr = 0;
-
- switch (sii->pub.bustype) {
- case SPI_BUS:
- case SDIO_BUS:
- sbaddr = (u32)(unsigned long)sii->curmap;
- break;
- default:
- ASSERT(0);
- break;
- }
-
- return sbaddr;
-}
-
-uint sb_corerev(si_t *sih)
-{
- si_info_t *sii;
- sbconfig_t *sb;
- uint sbidh;
-
- sii = SI_INFO(sih);
- sb = REGS2SB(sii->curmap);
- sbidh = R_SBREG(sii, &sb->sbidhigh);
-
- return SBCOREREV(sbidh);
-}
-
-bool sb_iscoreup(si_t *sih)
-{
- si_info_t *sii;
- sbconfig_t *sb;
-
- sii = SI_INFO(sih);
- sb = REGS2SB(sii->curmap);
-
- return (R_SBREG(sii, &sb->sbtmstatelow) &
- (SBTML_RESET | SBTML_REJ_MASK |
- (SICF_CLOCK_EN << SBTML_SICF_SHIFT))) ==
- (SICF_CLOCK_EN << SBTML_SICF_SHIFT);
-}
-
-/*
- * Switch to 'coreidx', issue a single arbitrary 32bit
- * register mask&set operation,
- * switch back to the original core, and return the new value.
- *
- * When using the silicon backplane, no fidleing with interrupts
- * or core switches are needed.
- *
- * Also, when using pci/pcie, we can optimize away the core switching
- * for pci registers
- * and (on newer pci cores) chipcommon registers.
- */
-uint sb_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)
-{
- uint origidx = 0;
- u32 *r = NULL;
- uint w;
- uint intr_val = 0;
- bool fast = false;
- si_info_t *sii;
-
- sii = SI_INFO(sih);
-
- ASSERT(GOODIDX(coreidx));
- ASSERT(regoff < SI_CORE_SIZE);
- ASSERT((val & ~mask) == 0);
-
- if (coreidx >= SI_MAXCORES)
- return 0;
-
- if (!fast) {
- INTR_OFF(sii, intr_val);
-
- /* save current core index */
- origidx = si_coreidx(&sii->pub);
-
- /* switch core */
- r = (u32 *) ((unsigned char *) sb_setcoreidx(&sii->pub, coreidx) +
- regoff);
- }
- ASSERT(r != NULL);
-
- /* mask and set */
- if (mask || val) {
- if (regoff >= SBCONFIGOFF) {
- w = (R_SBREG(sii, r) & ~mask) | val;
- W_SBREG(sii, r, w);
- } else {
- w = (R_REG(r) & ~mask) | val;
- W_REG(r, w);
- }
- }
-
- /* readback */
- if (regoff >= SBCONFIGOFF)
- w = R_SBREG(sii, r);
- else
- w = R_REG(r);
-
- if (!fast) {
- /* restore core index */
- if (origidx != coreidx)
- sb_setcoreidx(&sii->pub, origidx);
-
- INTR_RESTORE(sii, intr_val);
- }
-
- return w;
-}
-
-/* Scan the enumeration space to find all cores starting from the given
- * bus 'sbba'. Append coreid and other info to the lists in 'si'. 'sba'
- * is the default core address at chip POR time and 'regs' is the virtual
- * address that the default core is mapped at. 'ncores' is the number of
- * cores expected on bus 'sbba'. It returns the total number of cores
- * starting from bus 'sbba', inclusive.
- */
-#define SB_MAXBUSES 2
-static uint _sb_scan(si_info_t *sii, u32 sba, void *regs, uint bus, u32 sbba,
- uint numcores)
-{
- uint next;
- uint ncc = 0;
- uint i;
-
- if (bus >= SB_MAXBUSES) {
- SI_ERROR(("_sb_scan: bus 0x%08x at level %d is too deep to "
- "scan\n", sbba, bus));
- return 0;
- }
- SI_MSG(("_sb_scan: scan bus 0x%08x assume %u cores\n",
- sbba, numcores));
-
- /* Scan all cores on the bus starting from core 0.
- * Core addresses must be contiguous on each bus.
- */
- for (i = 0, next = sii->numcores;
- i < numcores && next < SB_BUS_MAXCORES; i++, next++) {
- sii->coresba[next] = sbba + (i * SI_CORE_SIZE);
-
- /* change core to 'next' and read its coreid */
- sii->curmap = _sb_setcoreidx(sii, next);
- sii->curidx = next;
-
- sii->coreid[next] = sb_coreid(&sii->pub);
-
- /* core specific processing... */
- /* chipc provides # cores */
- if (sii->coreid[next] == CC_CORE_ID) {
- chipcregs_t *cc = (chipcregs_t *) sii->curmap;
- u32 ccrev = sb_corerev(&sii->pub);
-
- /* determine numcores - this is the
- total # cores in the chip */
- if (((ccrev == 4) || (ccrev >= 6)))
- numcores =
- (R_REG(&cc->chipid) & CID_CC_MASK)
- >> CID_CC_SHIFT;
- else {
- /* Older chips */
- SI_ERROR(("sb_chip2numcores: unsupported chip "
- "0x%x\n", sii->pub.chip));
- ASSERT(0);
- numcores = 1;
- }
-
- SI_VMSG(("_sb_scan: %u cores in the chip %s\n",
- numcores, sii->pub.issim ? "QT" : ""));
- }
- /* scan bridged SB(s) and add results to the end of the list */
- else if (sii->coreid[next] == OCP_CORE_ID) {
- sbconfig_t *sb = REGS2SB(sii->curmap);
- u32 nsbba = R_SBREG(sii, &sb->sbadmatch1);
- uint nsbcc;
-
- sii->numcores = next + 1;
-
- if ((nsbba & 0xfff00000) != SI_ENUM_BASE)
- continue;
- nsbba &= 0xfffff000;
- if (_sb_coreidx(sii, nsbba) != BADIDX)
- continue;
-
- nsbcc =
- (R_SBREG(sii, &sb->sbtmstatehigh) & 0x000f0000) >>
- 16;
- nsbcc = _sb_scan(sii, sba, regs, bus + 1, nsbba, nsbcc);
- if (sbba == SI_ENUM_BASE)
- numcores -= nsbcc;
- ncc += nsbcc;
- }
- }
-
- SI_MSG(("_sb_scan: found %u cores on bus 0x%08x\n", i, sbba));
-
- sii->numcores = i + ncc;
- return sii->numcores;
-}
-
-/* scan the sb enumerated space to identify all cores */
-void sb_scan(si_t *sih, void *regs, uint devid)
-{
- si_info_t *sii;
- u32 origsba;
- sbconfig_t *sb;
-
- sii = SI_INFO(sih);
- sb = REGS2SB(sii->curmap);
-
- sii->pub.socirev =
- (R_SBREG(sii, &sb->sbidlow) & SBIDL_RV_MASK) >> SBIDL_RV_SHIFT;
-
- /* Save the current core info and validate it later till we know
- * for sure what is good and what is bad.
- */
- origsba = _sb_coresba(sii);
-
- /* scan all SB(s) starting from SI_ENUM_BASE */
- sii->numcores = _sb_scan(sii, origsba, regs, 0, SI_ENUM_BASE, 1);
-}
-
-/*
- * This function changes logical "focus" to the indicated core;
- * must be called with interrupts off.
- * Moreover, callers should keep interrupts off during switching out of
- * and back to d11 core
- */
-void *sb_setcoreidx(si_t *sih, uint coreidx)
-{
- si_info_t *sii;
-
- sii = SI_INFO(sih);
-
- if (coreidx >= sii->numcores)
- return NULL;
-
- /*
- * If the user has provided an interrupt mask enabled function,
- * then assert interrupts are disabled before switching the core.
- */
- ASSERT((sii->intrsenabled_fn == NULL)
- || !(*(sii)->intrsenabled_fn) ((sii)->intr_arg));
-
- sii->curmap = _sb_setcoreidx(sii, coreidx);
- sii->curidx = coreidx;
-
- return sii->curmap;
-}
-
-/* This function changes the logical "focus" to the indicated core.
- * Return the current core's virtual address.
- */
-static void *_sb_setcoreidx(si_info_t *sii, uint coreidx)
-{
- u32 sbaddr = sii->coresba[coreidx];
- void *regs;
-
- switch (sii->pub.bustype) {
-#ifdef BCMSDIO
- case SPI_BUS:
- case SDIO_BUS:
- /* map new one */
- if (!sii->regs[coreidx]) {
- sii->regs[coreidx] = (void *)sbaddr;
- ASSERT(GOODREGS(sii->regs[coreidx]));
- }
- regs = sii->regs[coreidx];
- break;
-#endif /* BCMSDIO */
- default:
- ASSERT(0);
- regs = NULL;
- break;
- }
-
- return regs;
-}
-
-void sb_core_disable(si_t *sih, u32 bits)
-{
- si_info_t *sii;
- volatile u32 dummy;
- sbconfig_t *sb;
-
- sii = SI_INFO(sih);
-
- ASSERT(GOODREGS(sii->curmap));
- sb = REGS2SB(sii->curmap);
-
- /* if core is already in reset, just return */
- if (R_SBREG(sii, &sb->sbtmstatelow) & SBTML_RESET)
- return;
-
- /* if clocks are not enabled, put into reset and return */
- if ((R_SBREG(sii, &sb->sbtmstatelow) &
- (SICF_CLOCK_EN << SBTML_SICF_SHIFT)) == 0)
- goto disable;
-
- /* set target reject and spin until busy is clear
- (preserve core-specific bits) */
- OR_SBREG(sii, &sb->sbtmstatelow, SBTML_REJ);
- dummy = R_SBREG(sii, &sb->sbtmstatelow);
- udelay(1);
- SPINWAIT((R_SBREG(sii, &sb->sbtmstatehigh) & SBTMH_BUSY), 100000);
- if (R_SBREG(sii, &sb->sbtmstatehigh) & SBTMH_BUSY)
- SI_ERROR(("%s: target state still busy\n", __func__));
-
- if (R_SBREG(sii, &sb->sbidlow) & SBIDL_INIT) {
- OR_SBREG(sii, &sb->sbimstate, SBIM_RJ);
- dummy = R_SBREG(sii, &sb->sbimstate);
- udelay(1);
- SPINWAIT((R_SBREG(sii, &sb->sbimstate) & SBIM_BY), 100000);
- }
-
- /* set reset and reject while enabling the clocks */
- W_SBREG(sii, &sb->sbtmstatelow,
- (((bits | SICF_FGC | SICF_CLOCK_EN) << SBTML_SICF_SHIFT) |
- SBTML_REJ | SBTML_RESET));
- dummy = R_SBREG(sii, &sb->sbtmstatelow);
- udelay(10);
-
- /* don't forget to clear the initiator reject bit */
- if (R_SBREG(sii, &sb->sbidlow) & SBIDL_INIT)
- AND_SBREG(sii, &sb->sbimstate, ~SBIM_RJ);
-
-disable:
- /* leave reset and reject asserted */
- W_SBREG(sii, &sb->sbtmstatelow,
- ((bits << SBTML_SICF_SHIFT) | SBTML_REJ | SBTML_RESET));
- udelay(1);
-}
-
-/* reset and re-enable a core
- * inputs:
- * bits - core specific bits that are set during and after reset sequence
- * resetbits - core specific bits that are set only during reset sequence
- */
-void sb_core_reset(si_t *sih, u32 bits, u32 resetbits)
-{
- si_info_t *sii;
- sbconfig_t *sb;
- volatile u32 dummy;
-
- sii = SI_INFO(sih);
- ASSERT(GOODREGS(sii->curmap));
- sb = REGS2SB(sii->curmap);
-
- /*
- * Must do the disable sequence first to work for
- * arbitrary current core state.
- */
- sb_core_disable(sih, (bits | resetbits));
-
- /*
- * Now do the initialization sequence.
- */
-
- /* set reset while enabling the clock and
- forcing them on throughout the core */
- W_SBREG(sii, &sb->sbtmstatelow,
- (((bits | resetbits | SICF_FGC | SICF_CLOCK_EN) <<
- SBTML_SICF_SHIFT) | SBTML_RESET));
- dummy = R_SBREG(sii, &sb->sbtmstatelow);
- udelay(1);
-
- if (R_SBREG(sii, &sb->sbtmstatehigh) & SBTMH_SERR)
- W_SBREG(sii, &sb->sbtmstatehigh, 0);
-
- dummy = R_SBREG(sii, &sb->sbimstate);
- if (dummy & (SBIM_IBE | SBIM_TO))
- AND_SBREG(sii, &sb->sbimstate, ~(SBIM_IBE | SBIM_TO));
-
- /* clear reset and allow it to propagate throughout the core */
- W_SBREG(sii, &sb->sbtmstatelow,
- ((bits | resetbits | SICF_FGC | SICF_CLOCK_EN) <<
- SBTML_SICF_SHIFT));
- dummy = R_SBREG(sii, &sb->sbtmstatelow);
- udelay(1);
-
- /* leave clock enabled */
- W_SBREG(sii, &sb->sbtmstatelow,
- ((bits | SICF_CLOCK_EN) << SBTML_SICF_SHIFT));
- dummy = R_SBREG(sii, &sb->sbtmstatelow);
- udelay(1);
-}
diff --git a/drivers/staging/brcm80211/util/siutils.c b/drivers/staging/brcm80211/util/siutils.c
deleted file mode 100644
index 6ebd7f5..0000000
--- a/drivers/staging/brcm80211/util/siutils.c
+++ /dev/null
@@ -1,2006 +0,0 @@
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#include <linux/delay.h>
-#include <linux/kernel.h>
-#include <linux/string.h>
-#include <bcmdefs.h>
-#include <linux/module.h>
-#include <linux/pci.h>
-#include <bcmutils.h>
-#include <siutils.h>
-#include <bcmdevs.h>
-#include <hndsoc.h>
-#include <sbchipc.h>
-#include <pci_core.h>
-#include <pcie_core.h>
-#include <nicpci.h>
-#include <bcmnvram.h>
-#include <bcmsrom.h>
-#include <pcicfg.h>
-#include <sbsocram.h>
-#ifdef BCMSDIO
-#include <bcmsdh.h>
-#include <sdio.h>
-#include <sbsdio.h>
-#include <sbhnddma.h>
-#include <sbsdpcmdev.h>
-#include <bcmsdpcm.h>
-#endif /* BCMSDIO */
-#include <hndpmu.h>
-
-/* this file now contains only definitions for sb functions, only necessary
-*for devices using Sonics backplanes (bcm4329)
-*/
-
-/* if an amba SDIO device is supported, please further restrict the inclusion
- * of this file
- */
-#ifdef BCMSDIO
-#include "siutils_priv.h"
-#endif
-
-/* local prototypes */
-static si_info_t *si_doattach(si_info_t *sii, uint devid, void *regs,
- uint bustype, void *sdh, char **vars,
- uint *varsz);
-static bool si_buscore_prep(si_info_t *sii, uint bustype, uint devid,
- void *sdh);
-static bool si_buscore_setup(si_info_t *sii, chipcregs_t *cc, uint bustype,
- u32 savewin, uint *origidx, void *regs);
-static void si_nvram_process(si_info_t *sii, char *pvars);
-
-/* dev path concatenation util */
-static char *si_devpathvar(si_t *sih, char *var, int len, const char *name);
-static bool _si_clkctl_cc(si_info_t *sii, uint mode);
-static bool si_ispcie(si_info_t *sii);
-static uint socram_banksize(si_info_t *sii, sbsocramregs_t *r,
- u8 idx, u8 mtype);
-
-/* global variable to indicate reservation/release of gpio's */
-static u32 si_gpioreservation;
-
-/*
- * Allocate a si handle.
- * devid - pci device id (used to determine chip#)
- * osh - opaque OS handle
- * regs - virtual address of initial core registers
- * bustype - pci/sb/sdio/etc
- * vars - pointer to a pointer area for "environment" variables
- * varsz - pointer to int to return the size of the vars
- */
-si_t *si_attach(uint devid, void *regs, uint bustype,
- void *sdh, char **vars, uint *varsz)
-{
- si_info_t *sii;
-
- /* alloc si_info_t */
- sii = kmalloc(sizeof(si_info_t), GFP_ATOMIC);
- if (sii == NULL) {
- SI_ERROR(("si_attach: malloc failed!\n"));
- return NULL;
- }
-
- if (si_doattach(sii, devid, regs, bustype, sdh, vars, varsz) ==
- NULL) {
- kfree(sii);
- return NULL;
- }
- sii->vars = vars ? *vars : NULL;
- sii->varsz = varsz ? *varsz : 0;
-
- return (si_t *) sii;
-}
-
-/* global kernel resource */
-static si_info_t ksii;
-
-static bool si_buscore_prep(si_info_t *sii, uint bustype, uint devid,
- void *sdh)
-{
-
-#ifndef BRCM_FULLMAC
- /* kludge to enable the clock on the 4306 which lacks a slowclock */
- if (bustype == PCI_BUS && !si_ispcie(sii))
- si_clkctl_xtal(&sii->pub, XTAL | PLL, ON);
-#endif
-
-#if defined(BCMSDIO)
- if (bustype == SDIO_BUS) {
- int err;
- u8 clkset;
-
- /* Try forcing SDIO core to do ALPAvail request only */
- clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ;
- bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_CHIPCLKCSR,
- clkset, &err);
- if (!err) {
- u8 clkval;
-
- /* If register supported, wait for ALPAvail and then force ALP */
- clkval =
- bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
- SBSDIO_FUNC1_CHIPCLKCSR, NULL);
- if ((clkval & ~SBSDIO_AVBITS) == clkset) {
- SPINWAIT(((clkval =
- bcmsdh_cfg_read(sdh, SDIO_FUNC_1,
- SBSDIO_FUNC1_CHIPCLKCSR,
- NULL)),
- !SBSDIO_ALPAV(clkval)),
- PMU_MAX_TRANSITION_DLY);
- if (!SBSDIO_ALPAV(clkval)) {
- SI_ERROR(("timeout on ALPAV wait, clkval 0x%02x\n", clkval));
- return false;
- }
- clkset =
- SBSDIO_FORCE_HW_CLKREQ_OFF |
- SBSDIO_FORCE_ALP;
- bcmsdh_cfg_write(sdh, SDIO_FUNC_1,
- SBSDIO_FUNC1_CHIPCLKCSR,
- clkset, &err);
- udelay(65);
- }
- }
-
- /* Also, disable the extra SDIO pull-ups */
- bcmsdh_cfg_write(sdh, SDIO_FUNC_1, SBSDIO_FUNC1_SDIOPULLUP, 0,
- NULL);
- }
-#endif /* defined(BCMSDIO) */
-
- return true;
-}
-
-static bool si_buscore_setup(si_info_t *sii, chipcregs_t *cc, uint bustype,
- u32 savewin, uint *origidx, void *regs)
-{
- bool pci, pcie;
- uint i;
- uint pciidx, pcieidx, pcirev, pcierev;
-
- cc = si_setcoreidx(&sii->pub, SI_CC_IDX);
- ASSERT(cc);
-
- /* get chipcommon rev */
- sii->pub.ccrev = (int)si_corerev(&sii->pub);
-
- /* get chipcommon chipstatus */
- if (sii->pub.ccrev >= 11)
- sii->pub.chipst = R_REG(&cc->chipstatus);
-
- /* get chipcommon capabilites */
- sii->pub.cccaps = R_REG(&cc->capabilities);
- /* get chipcommon extended capabilities */
-
-#ifndef BRCM_FULLMAC
- if (sii->pub.ccrev >= 35)
- sii->pub.cccaps_ext = R_REG(&cc->capabilities_ext);
-#endif
- /* get pmu rev and caps */
- if (sii->pub.cccaps & CC_CAP_PMU) {
- sii->pub.pmucaps = R_REG(&cc->pmucapabilities);
- sii->pub.pmurev = sii->pub.pmucaps & PCAP_REV_MASK;
- }
-
- /*
- SI_MSG(("Chipc: rev %d, caps 0x%x, chipst 0x%x pmurev %d, pmucaps 0x%x\n",
- sii->pub.ccrev, sii->pub.cccaps, sii->pub.chipst, sii->pub.pmurev,
- sii->pub.pmucaps));
- */
-
- /* figure out bus/orignal core idx */
- sii->pub.buscoretype = NODEV_CORE_ID;
- sii->pub.buscorerev = NOREV;
- sii->pub.buscoreidx = BADIDX;
-
- pci = pcie = false;
- pcirev = pcierev = NOREV;
- pciidx = pcieidx = BADIDX;
-
- for (i = 0; i < sii->numcores; i++) {
- uint cid, crev;
-
- si_setcoreidx(&sii->pub, i);
- cid = si_coreid(&sii->pub);
- crev = si_corerev(&sii->pub);
-
- /* Display cores found */
- SI_VMSG(("CORE[%d]: id 0x%x rev %d base 0x%x regs 0x%p\n",
- i, cid, crev, sii->coresba[i], sii->regs[i]));
-
- if (bustype == PCI_BUS) {
- if (cid == PCI_CORE_ID) {
- pciidx = i;
- pcirev = crev;
- pci = true;
- } else if (cid == PCIE_CORE_ID) {
- pcieidx = i;
- pcierev = crev;
- pcie = true;
- }
- }
-#ifdef BCMSDIO
- else if (((bustype == SDIO_BUS) ||
- (bustype == SPI_BUS)) &&
- ((cid == PCMCIA_CORE_ID) || (cid == SDIOD_CORE_ID))) {
- sii->pub.buscorerev = crev;
- sii->pub.buscoretype = cid;
- sii->pub.buscoreidx = i;
- }
-#endif /* BCMSDIO */
-
- /* find the core idx before entering this func. */
- if ((savewin && (savewin == sii->coresba[i])) ||
- (regs == sii->regs[i]))
- *origidx = i;
- }
-
-#ifdef BRCM_FULLMAC
- SI_MSG(("Buscore id/type/rev %d/0x%x/%d\n", sii->pub.buscoreidx,
- sii->pub.buscoretype, sii->pub.buscorerev));
-
- /* Make sure any on-chip ARM is off (in case strapping is wrong),
- * or downloaded code was
- * already running.
- */
- if ((bustype == SDIO_BUS) || (bustype == SPI_BUS)) {
- if (si_setcore(&sii->pub, ARM7S_CORE_ID, 0) ||
- si_setcore(&sii->pub, ARMCM3_CORE_ID, 0))
- si_core_disable(&sii->pub, 0);
- }
-#else
- if (pci && pcie) {
- if (si_ispcie(sii))
- pci = false;
- else
- pcie = false;
- }
- if (pci) {
- sii->pub.buscoretype = PCI_CORE_ID;
- sii->pub.buscorerev = pcirev;
- sii->pub.buscoreidx = pciidx;
- } else if (pcie) {
- sii->pub.buscoretype = PCIE_CORE_ID;
- sii->pub.buscorerev = pcierev;
- sii->pub.buscoreidx = pcieidx;
- }
-
- SI_VMSG(("Buscore id/type/rev %d/0x%x/%d\n", sii->pub.buscoreidx,
- sii->pub.buscoretype, sii->pub.buscorerev));
-
- /* fixup necessary chip/core configurations */
- if (sii->pub.bustype == PCI_BUS) {
- if (SI_FAST(sii)) {
- if (!sii->pch) {
- sii->pch = (void *)pcicore_init(
- &sii->pub, sii->pbus,
- (void *)PCIEREGS(sii));
- if (sii->pch == NULL)
- return false;
- }
- }
- if (si_pci_fixcfg(&sii->pub)) {
- SI_ERROR(("si_doattach: sb_pci_fixcfg failed\n"));
- return false;
- }
- }
-#endif
- /* return to the original core */
- si_setcoreidx(&sii->pub, *origidx);
-
- return true;
-}
-
-static __used void si_nvram_process(si_info_t *sii, char *pvars)
-{
- uint w = 0;
-
- /* get boardtype and boardrev */
- switch (sii->pub.bustype) {
- case PCI_BUS:
- /* do a pci config read to get subsystem id and subvendor id */
- pci_read_config_dword(sii->pbus, PCI_CFG_SVID, &w);
- /* Let nvram variables override subsystem Vend/ID */
- sii->pub.boardvendor = (u16)si_getdevpathintvar(&sii->pub,
- "boardvendor");
- if (sii->pub.boardvendor == 0)
- sii->pub.boardvendor = w & 0xffff;
- else
- SI_ERROR(("Overriding boardvendor: 0x%x instead of 0x%x\n", sii->pub.boardvendor, w & 0xffff));
- sii->pub.boardtype = (u16)si_getdevpathintvar(&sii->pub,
- "boardtype");
- if (sii->pub.boardtype == 0)
- sii->pub.boardtype = (w >> 16) & 0xffff;
- else
- SI_ERROR(("Overriding boardtype: 0x%x instead of 0x%x\n", sii->pub.boardtype, (w >> 16) & 0xffff));
- break;
-
-#ifdef BCMSDIO
- case SDIO_BUS:
-#endif
- sii->pub.boardvendor = getintvar(pvars, "manfid");
- sii->pub.boardtype = getintvar(pvars, "prodid");
- break;
-
-#ifdef BCMSDIO
- case SPI_BUS:
- sii->pub.boardvendor = VENDOR_BROADCOM;
- sii->pub.boardtype = SPI_BOARD;
- break;
-#endif
-
- case SI_BUS:
- case JTAG_BUS:
- sii->pub.boardvendor = VENDOR_BROADCOM;
- sii->pub.boardtype = getintvar(pvars, "prodid");
- if (pvars == NULL || (sii->pub.boardtype == 0)) {
- sii->pub.boardtype = getintvar(NULL, "boardtype");
- if (sii->pub.boardtype == 0)
- sii->pub.boardtype = 0xffff;
- }
- break;
- }
-
- if (sii->pub.boardtype == 0) {
- SI_ERROR(("si_doattach: unknown board type\n"));
- ASSERT(sii->pub.boardtype);
- }
-
- sii->pub.boardflags = getintvar(pvars, "boardflags");
-}
-
-/* this is will make Sonics calls directly, since Sonics is no longer supported in the Si abstraction */
-/* this has been customized for the bcm 4329 ONLY */
-#ifdef BCMSDIO
-static si_info_t *si_doattach(si_info_t *sii, uint devid,
- void *regs, uint bustype, void *pbus,
- char **vars, uint *varsz)
-{
- struct si_pub *sih = &sii->pub;
- u32 w, savewin;
- chipcregs_t *cc;
- char *pvars = NULL;
- uint origidx;
-
- ASSERT(GOODREGS(regs));
-
- memset((unsigned char *) sii, 0, sizeof(si_info_t));
-
- savewin = 0;
-
- sih->buscoreidx = BADIDX;
-
- sii->curmap = regs;
- sii->pbus = pbus;
-
- /* find Chipcommon address */
- cc = (chipcregs_t *) sii->curmap;
- sih->bustype = bustype;
-
- /* bus/core/clk setup for register access */
- if (!si_buscore_prep(sii, bustype, devid, pbus)) {
- SI_ERROR(("si_doattach: si_core_clk_prep failed %d\n",
- bustype));
- return NULL;
- }
-
- /* ChipID recognition.
- * We assume we can read chipid at offset 0 from the regs arg.
- * If we add other chiptypes (or if we need to support old sdio hosts w/o chipcommon),
- * some way of recognizing them needs to be added here.
- */
- w = R_REG(&cc->chipid);
- sih->socitype = (w & CID_TYPE_MASK) >> CID_TYPE_SHIFT;
- /* Might as wll fill in chip id rev & pkg */
- sih->chip = w & CID_ID_MASK;
- sih->chiprev = (w & CID_REV_MASK) >> CID_REV_SHIFT;
- sih->chippkg = (w & CID_PKG_MASK) >> CID_PKG_SHIFT;
-
- if ((sih->chip == BCM4329_CHIP_ID) &&
- (sih->chippkg != BCM4329_289PIN_PKG_ID))
- sih->chippkg = BCM4329_182PIN_PKG_ID;
-
- sih->issim = IS_SIM(sih->chippkg);
-
- /* scan for cores */
- /* SI_MSG(("Found chip type SB (0x%08x)\n", w)); */
- sb_scan(&sii->pub, regs, devid);
-
- /* no cores found, bail out */
- if (sii->numcores == 0) {
- SI_ERROR(("si_doattach: could not find any cores\n"));
- return NULL;
- }
- /* bus/core/clk setup */
- origidx = SI_CC_IDX;
- if (!si_buscore_setup(sii, cc, bustype, savewin, &origidx, regs)) {
- SI_ERROR(("si_doattach: si_buscore_setup failed\n"));
- goto exit;
- }
-
-#ifdef BRCM_FULLMAC
- pvars = NULL;
-#else
- /* Init nvram from flash if it exists */
- nvram_init((void *)&(sii->pub));
-
- /* Init nvram from sprom/otp if they exist */
- if (srom_var_init
- (&sii->pub, bustype, regs, sii->osh, vars, varsz)) {
- SI_ERROR(("si_doattach: srom_var_init failed: bad srom\n"));
- goto exit;
- }
- pvars = vars ? *vars : NULL;
- si_nvram_process(sii, pvars);
-#endif
-
- /* === NVRAM, clock is ready === */
-
-#ifdef BRCM_FULLMAC
- if (sii->pub.ccrev >= 20) {
-#endif
- cc = (chipcregs_t *) si_setcore(sih, CC_CORE_ID, 0);
- W_REG(&cc->gpiopullup, 0);
- W_REG(&cc->gpiopulldown, 0);
- sb_setcoreidx(sih, origidx);
-#ifdef BRCM_FULLMAC
- }
-#endif
-
-#ifndef BRCM_FULLMAC
- /* PMU specific initializations */
- if (PMUCTL_ENAB(sih)) {
- u32 xtalfreq;
- si_pmu_init(sih);
- si_pmu_chip_init(sih);
- xtalfreq = getintvar(pvars, "xtalfreq");
- /* If xtalfreq var not available, try to measure it */
- if (xtalfreq == 0)
- xtalfreq = si_pmu_measure_alpclk(sih);
- si_pmu_pll_init(sih, xtalfreq);
- si_pmu_res_init(sih);
- si_pmu_swreg_init(sih);
- }
-
- /* setup the GPIO based LED powersave register */
- w = getintvar(pvars, "leddc");
- if (w == 0)
- w = DEFAULT_GPIOTIMERVAL;
- sb_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, gpiotimerval), ~0, w);
-
-#ifdef BCMDBG
- /* clear any previous epidiag-induced target abort */
- sb_taclear(sih, false);
-#endif /* BCMDBG */
-#endif
-
- return sii;
-
- exit:
- return NULL;
-}
-
-#else /* BCMSDIO */
-static si_info_t *si_doattach(si_info_t *sii, uint devid,
- void *regs, uint bustype, void *pbus,
- char **vars, uint *varsz)
-{
- struct si_pub *sih = &sii->pub;
- u32 w, savewin;
- chipcregs_t *cc;
- char *pvars = NULL;
- uint origidx;
-
- ASSERT(GOODREGS(regs));
-
- memset((unsigned char *) sii, 0, sizeof(si_info_t));
-
- savewin = 0;
-
- sih->buscoreidx = BADIDX;
-
- sii->curmap = regs;
- sii->pbus = pbus;
-
- /* check to see if we are a si core mimic'ing a pci core */
- if (bustype == PCI_BUS) {
- pci_read_config_dword(sii->pbus, PCI_SPROM_CONTROL, &w);
- if (w == 0xffffffff) {
- SI_ERROR(("%s: incoming bus is PCI but it's a lie, "
- " switching to SI devid:0x%x\n",
- __func__, devid));
- bustype = SI_BUS;
- }
- }
-
- /* find Chipcommon address */
- if (bustype == PCI_BUS) {
- pci_read_config_dword(sii->pbus, PCI_BAR0_WIN, &savewin);
- if (!GOODCOREADDR(savewin, SI_ENUM_BASE))
- savewin = SI_ENUM_BASE;
- pci_write_config_dword(sii->pbus, PCI_BAR0_WIN,
- SI_ENUM_BASE);
- cc = (chipcregs_t *) regs;
- } else {
- cc = (chipcregs_t *) REG_MAP(SI_ENUM_BASE, SI_CORE_SIZE);
- }
-
- sih->bustype = bustype;
-
- /* bus/core/clk setup for register access */
- if (!si_buscore_prep(sii, bustype, devid, pbus)) {
- SI_ERROR(("si_doattach: si_core_clk_prep failed %d\n",
- bustype));
- return NULL;
- }
-
- /* ChipID recognition.
- * We assume we can read chipid at offset 0 from the regs arg.
- * If we add other chiptypes (or if we need to support old sdio hosts w/o chipcommon),
- * some way of recognizing them needs to be added here.
- */
- w = R_REG(&cc->chipid);
- sih->socitype = (w & CID_TYPE_MASK) >> CID_TYPE_SHIFT;
- /* Might as wll fill in chip id rev & pkg */
- sih->chip = w & CID_ID_MASK;
- sih->chiprev = (w & CID_REV_MASK) >> CID_REV_SHIFT;
- sih->chippkg = (w & CID_PKG_MASK) >> CID_PKG_SHIFT;
-
- sih->issim = IS_SIM(sih->chippkg);
-
- /* scan for cores */
- if (sii->pub.socitype == SOCI_AI) {
- SI_MSG(("Found chip type AI (0x%08x)\n", w));
- /* pass chipc address instead of original core base */
- ai_scan(&sii->pub, (void *)cc, devid);
- } else {
- SI_ERROR(("Found chip of unknown type (0x%08x)\n", w));
- return NULL;
- }
- /* no cores found, bail out */
- if (sii->numcores == 0) {
- SI_ERROR(("si_doattach: could not find any cores\n"));
- return NULL;
- }
- /* bus/core/clk setup */
- origidx = SI_CC_IDX;
- if (!si_buscore_setup(sii, cc, bustype, savewin, &origidx, regs)) {
- SI_ERROR(("si_doattach: si_buscore_setup failed\n"));
- goto exit;
- }
-
- /* assume current core is CC */
- if ((sii->pub.ccrev == 0x25)
- &&
- ((sih->chip == BCM43236_CHIP_ID
- || sih->chip == BCM43235_CHIP_ID
- || sih->chip == BCM43238_CHIP_ID)
- && (sii->pub.chiprev <= 2))) {
-
- if ((cc->chipstatus & CST43236_BP_CLK) != 0) {
- uint clkdiv;
- clkdiv = R_REG(&cc->clkdiv);
- /* otp_clk_div is even number, 120/14 < 9mhz */
- clkdiv = (clkdiv & ~CLKD_OTP) | (14 << CLKD_OTP_SHIFT);
- W_REG(&cc->clkdiv, clkdiv);
- SI_ERROR(("%s: set clkdiv to %x\n", __func__, clkdiv));
- }
- udelay(10);
- }
-
- /* Init nvram from flash if it exists */
- nvram_init((void *)&(sii->pub));
-
- /* Init nvram from sprom/otp if they exist */
- if (srom_var_init
- (&sii->pub, bustype, regs, vars, varsz)) {
- SI_ERROR(("si_doattach: srom_var_init failed: bad srom\n"));
- goto exit;
- }
- pvars = vars ? *vars : NULL;
- si_nvram_process(sii, pvars);
-
- /* === NVRAM, clock is ready === */
- cc = (chipcregs_t *) si_setcore(sih, CC_CORE_ID, 0);
- W_REG(&cc->gpiopullup, 0);
- W_REG(&cc->gpiopulldown, 0);
- si_setcoreidx(sih, origidx);
-
- /* PMU specific initializations */
- if (PMUCTL_ENAB(sih)) {
- u32 xtalfreq;
- si_pmu_init(sih);
- si_pmu_chip_init(sih);
- xtalfreq = getintvar(pvars, "xtalfreq");
- /* If xtalfreq var not available, try to measure it */
- if (xtalfreq == 0)
- xtalfreq = si_pmu_measure_alpclk(sih);
- si_pmu_pll_init(sih, xtalfreq);
- si_pmu_res_init(sih);
- si_pmu_swreg_init(sih);
- }
-
- /* setup the GPIO based LED powersave register */
- w = getintvar(pvars, "leddc");
- if (w == 0)
- w = DEFAULT_GPIOTIMERVAL;
- si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, gpiotimerval), ~0, w);
-
- if (PCIE(sii)) {
- ASSERT(sii->pch != NULL);
- pcicore_attach(sii->pch, pvars, SI_DOATTACH);
- }
-
- if ((sih->chip == BCM43224_CHIP_ID) ||
- (sih->chip == BCM43421_CHIP_ID)) {
- /* enable 12 mA drive strenth for 43224 and set chipControl register bit 15 */
- if (sih->chiprev == 0) {
- SI_MSG(("Applying 43224A0 WARs\n"));
- si_corereg(sih, SI_CC_IDX,
- offsetof(chipcregs_t, chipcontrol),
- CCTRL43224_GPIO_TOGGLE,
- CCTRL43224_GPIO_TOGGLE);
- si_pmu_chipcontrol(sih, 0, CCTRL_43224A0_12MA_LED_DRIVE,
- CCTRL_43224A0_12MA_LED_DRIVE);
- }
- if (sih->chiprev >= 1) {
- SI_MSG(("Applying 43224B0+ WARs\n"));
- si_pmu_chipcontrol(sih, 0, CCTRL_43224B0_12MA_LED_DRIVE,
- CCTRL_43224B0_12MA_LED_DRIVE);
- }
- }
-
- if (sih->chip == BCM4313_CHIP_ID) {
- /* enable 12 mA drive strenth for 4313 and set chipControl register bit 1 */
- SI_MSG(("Applying 4313 WARs\n"));
- si_pmu_chipcontrol(sih, 0, CCTRL_4313_12MA_LED_DRIVE,
- CCTRL_4313_12MA_LED_DRIVE);
- }
-
- if (sih->chip == BCM4331_CHIP_ID) {
- /* Enable Ext PA lines depending on chip package option */
- si_chipcontrl_epa4331(sih, true);
- }
-
- return sii;
- exit:
- if (sih->bustype == PCI_BUS) {
- if (sii->pch)
- pcicore_deinit(sii->pch);
- sii->pch = NULL;
- }
-
- return NULL;
-}
-#endif /* BCMSDIO */
-
-/* may be called with core in reset */
-void si_detach(si_t *sih)
-{
- si_info_t *sii;
- uint idx;
-
- struct si_pub *si_local = NULL;
- memcpy(&si_local, &sih, sizeof(si_t **));
-
- sii = SI_INFO(sih);
-
- if (sii == NULL)
- return;
-
- if (sih->bustype == SI_BUS)
- for (idx = 0; idx < SI_MAXCORES; idx++)
- if (sii->regs[idx]) {
- iounmap(sii->regs[idx]);
- sii->regs[idx] = NULL;
- }
-
-#ifndef BRCM_FULLMAC
- nvram_exit((void *)si_local); /* free up nvram buffers */
-
- if (sih->bustype == PCI_BUS) {
- if (sii->pch)
- pcicore_deinit(sii->pch);
- sii->pch = NULL;
- }
-#endif
-#if !defined(BCMBUSTYPE) || (BCMBUSTYPE == SI_BUS)
- if (sii != &ksii)
-#endif /* !BCMBUSTYPE || (BCMBUSTYPE == SI_BUS) */
- kfree(sii);
-}
-
-/* register driver interrupt disabling and restoring callback functions */
-void
-si_register_intr_callback(si_t *sih, void *intrsoff_fn, void *intrsrestore_fn,
- void *intrsenabled_fn, void *intr_arg)
-{
- si_info_t *sii;
-
- sii = SI_INFO(sih);
- sii->intr_arg = intr_arg;
- sii->intrsoff_fn = (si_intrsoff_t) intrsoff_fn;
- sii->intrsrestore_fn = (si_intrsrestore_t) intrsrestore_fn;
- sii->intrsenabled_fn = (si_intrsenabled_t) intrsenabled_fn;
- /* save current core id. when this function called, the current core
- * must be the core which provides driver functions(il, et, wl, etc.)
- */
- sii->dev_coreid = sii->coreid[sii->curidx];
-}
-
-void si_deregister_intr_callback(si_t *sih)
-{
- si_info_t *sii;
-
- sii = SI_INFO(sih);
- sii->intrsoff_fn = NULL;
-}
-
-uint si_flag(si_t *sih)
-{
- if (sih->socitype == SOCI_AI)
- return ai_flag(sih);
- else {
- ASSERT(0);
- return 0;
- }
-}
-
-void si_setint(si_t *sih, int siflag)
-{
- if (sih->socitype == SOCI_AI)
- ai_setint(sih, siflag);
- else
- ASSERT(0);
-}
-
-#ifndef BCMSDIO
-uint si_coreid(si_t *sih)
-{
- si_info_t *sii;
-
- sii = SI_INFO(sih);
- return sii->coreid[sii->curidx];
-}
-#endif
-
-uint si_coreidx(si_t *sih)
-{
- si_info_t *sii;
-
- sii = SI_INFO(sih);
- return sii->curidx;
-}
-
-bool si_backplane64(si_t *sih)
-{
- return (sih->cccaps & CC_CAP_BKPLN64) != 0;
-}
-
-#ifndef BCMSDIO
-uint si_corerev(si_t *sih)
-{
- if (sih->socitype == SOCI_AI)
- return ai_corerev(sih);
- else {
- ASSERT(0);
- return 0;
- }
-}
-#endif
-
-/* return index of coreid or BADIDX if not found */
-uint si_findcoreidx(si_t *sih, uint coreid, uint coreunit)
-{
- si_info_t *sii;
- uint found;
- uint i;
-
- sii = SI_INFO(sih);
-
- found = 0;
-
- for (i = 0; i < sii->numcores; i++)
- if (sii->coreid[i] == coreid) {
- if (found == coreunit)
- return i;
- found++;
- }
-
- return BADIDX;
-}
-
-/*
- * This function changes logical "focus" to the indicated core;
- * must be called with interrupts off.
- * Moreover, callers should keep interrupts off during switching out of and back to d11 core
- */
-void *si_setcore(si_t *sih, uint coreid, uint coreunit)
-{
- uint idx;
-
- idx = si_findcoreidx(sih, coreid, coreunit);
- if (!GOODIDX(idx))
- return NULL;
-
- if (sih->socitype == SOCI_AI)
- return ai_setcoreidx(sih, idx);
- else {
-#ifdef BCMSDIO
- return sb_setcoreidx(sih, idx);
-#else
- ASSERT(0);
- return NULL;
-#endif
- }
-}
-
-#ifndef BCMSDIO
-void *si_setcoreidx(si_t *sih, uint coreidx)
-{
- if (sih->socitype == SOCI_AI)
- return ai_setcoreidx(sih, coreidx);
- else {
- ASSERT(0);
- return NULL;
- }
-}
-#endif
-
-/* Turn off interrupt as required by sb_setcore, before switch core */
-void *si_switch_core(si_t *sih, uint coreid, uint *origidx, uint *intr_val)
-{
- void *cc;
- si_info_t *sii;
-
- sii = SI_INFO(sih);
-
- if (SI_FAST(sii)) {
- /* Overloading the origidx variable to remember the coreid,
- * this works because the core ids cannot be confused with
- * core indices.
- */
- *origidx = coreid;
- if (coreid == CC_CORE_ID)
- return (void *)CCREGS_FAST(sii);
- else if (coreid == sih->buscoretype)
- return (void *)PCIEREGS(sii);
- }
- INTR_OFF(sii, *intr_val);
- *origidx = sii->curidx;
- cc = si_setcore(sih, coreid, 0);
- ASSERT(cc != NULL);
-
- return cc;
-}
-
-/* restore coreidx and restore interrupt */
-void si_restore_core(si_t *sih, uint coreid, uint intr_val)
-{
- si_info_t *sii;
-
- sii = SI_INFO(sih);
- if (SI_FAST(sii)
- && ((coreid == CC_CORE_ID) || (coreid == sih->buscoretype)))
- return;
-
- si_setcoreidx(sih, coreid);
- INTR_RESTORE(sii, intr_val);
-}
-
-u32 si_core_cflags(si_t *sih, u32 mask, u32 val)
-{
- if (sih->socitype == SOCI_AI)
- return ai_core_cflags(sih, mask, val);
- else {
- ASSERT(0);
- return 0;
- }
-}
-
-u32 si_core_sflags(si_t *sih, u32 mask, u32 val)
-{
- if (sih->socitype == SOCI_AI)
- return ai_core_sflags(sih, mask, val);
- else {
- ASSERT(0);
- return 0;
- }
-}
-
-bool si_iscoreup(si_t *sih)
-{
- if (sih->socitype == SOCI_AI)
- return ai_iscoreup(sih);
- else {
-#ifdef BCMSDIO
- return sb_iscoreup(sih);
-#else
- ASSERT(0);
- return false;
-#endif
- }
-}
-
-void si_write_wrapperreg(si_t *sih, u32 offset, u32 val)
-{
- /* only for 4319, no requirement for SOCI_SB */
- if (sih->socitype == SOCI_AI) {
- ai_write_wrap_reg(sih, offset, val);
- }
-}
-
-uint si_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val)
-{
-
- if (sih->socitype == SOCI_AI)
- return ai_corereg(sih, coreidx, regoff, mask, val);
- else {
-#ifdef BCMSDIO
- return sb_corereg(sih, coreidx, regoff, mask, val);
-#else
- ASSERT(0);
- return 0;
-#endif
- }
-}
-
-void si_core_disable(si_t *sih, u32 bits)
-{
-
- if (sih->socitype == SOCI_AI)
- ai_core_disable(sih, bits);
-#ifdef BCMSDIO
- else
- sb_core_disable(sih, bits);
-#endif
-}
-
-void si_core_reset(si_t *sih, u32 bits, u32 resetbits)
-{
- if (sih->socitype == SOCI_AI)
- ai_core_reset(sih, bits, resetbits);
-#ifdef BCMSDIO
- else
- sb_core_reset(sih, bits, resetbits);
-#endif
-}
-
-u32 si_alp_clock(si_t *sih)
-{
- if (PMUCTL_ENAB(sih))
- return si_pmu_alp_clock(sih);
-
- return ALP_CLOCK;
-}
-
-u32 si_ilp_clock(si_t *sih)
-{
- if (PMUCTL_ENAB(sih))
- return si_pmu_ilp_clock(sih);
-
- return ILP_CLOCK;
-}
-
-/* set chip watchdog reset timer to fire in 'ticks' */
-#ifdef BRCM_FULLMAC
-void
-si_watchdog(si_t *sih, uint ticks)
-{
- if (PMUCTL_ENAB(sih)) {
-
- if ((sih->chip == BCM4319_CHIP_ID) && (sih->chiprev == 0) &&
- (ticks != 0)) {
- si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t,
- clk_ctl_st), ~0, 0x2);
- si_setcore(sih, USB20D_CORE_ID, 0);
- si_core_disable(sih, 1);
- si_setcore(sih, CC_CORE_ID, 0);
- }
-
- if (ticks == 1)
- ticks = 2;
- si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, pmuwatchdog),
- ~0, ticks);
- } else {
- /* instant NMI */
- si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, watchdog),
- ~0, ticks);
- }
-}
-#else
-void si_watchdog(si_t *sih, uint ticks)
-{
- uint nb, maxt;
-
- if (PMUCTL_ENAB(sih)) {
-
- if ((sih->chip == BCM4319_CHIP_ID) &&
- (sih->chiprev == 0) && (ticks != 0)) {
- si_corereg(sih, SI_CC_IDX,
- offsetof(chipcregs_t, clk_ctl_st), ~0, 0x2);
- si_setcore(sih, USB20D_CORE_ID, 0);
- si_core_disable(sih, 1);
- si_setcore(sih, CC_CORE_ID, 0);
- }
-
- nb = (sih->ccrev < 26) ? 16 : ((sih->ccrev >= 37) ? 32 : 24);
- /* The mips compiler uses the sllv instruction,
- * so we specially handle the 32-bit case.
- */
- if (nb == 32)
- maxt = 0xffffffff;
- else
- maxt = ((1 << nb) - 1);
-
- if (ticks == 1)
- ticks = 2;
- else if (ticks > maxt)
- ticks = maxt;
-
- si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, pmuwatchdog),
- ~0, ticks);
- } else {
- /* make sure we come up in fast clock mode; or if clearing, clear clock */
- si_clkctl_cc(sih, ticks ? CLK_FAST : CLK_DYNAMIC);
- maxt = (1 << 28) - 1;
- if (ticks > maxt)
- ticks = maxt;
-
- si_corereg(sih, SI_CC_IDX, offsetof(chipcregs_t, watchdog), ~0,
- ticks);
- }
-}
-#endif
-
-/* return the slow clock source - LPO, XTAL, or PCI */
-static uint si_slowclk_src(si_info_t *sii)
-{
- chipcregs_t *cc;
- u32 val;
-
- ASSERT(SI_FAST(sii) || si_coreid(&sii->pub) == CC_CORE_ID);
-
- if (sii->pub.ccrev < 6) {
- if (sii->pub.bustype == PCI_BUS) {
- pci_read_config_dword(sii->pbus, PCI_GPIO_OUT,
- &val);
- if (val & PCI_CFG_GPIO_SCS)
- return SCC_SS_PCI;
- }
- return SCC_SS_XTAL;
- } else if (sii->pub.ccrev < 10) {
- cc = (chipcregs_t *) si_setcoreidx(&sii->pub, sii->curidx);
- return R_REG(&cc->slow_clk_ctl) & SCC_SS_MASK;
- } else /* Insta-clock */
- return SCC_SS_XTAL;
-}
-
-/* return the ILP (slowclock) min or max frequency */
-static uint si_slowclk_freq(si_info_t *sii, bool max_freq, chipcregs_t *cc)
-{
- u32 slowclk;
- uint div;
-
- ASSERT(SI_FAST(sii) || si_coreid(&sii->pub) == CC_CORE_ID);
-
- /* shouldn't be here unless we've established the chip has dynamic clk control */
- ASSERT(R_REG(&cc->capabilities) & CC_CAP_PWR_CTL);
-
- slowclk = si_slowclk_src(sii);
- if (sii->pub.ccrev < 6) {
- if (slowclk == SCC_SS_PCI)
- return max_freq ? (PCIMAXFREQ / 64)
- : (PCIMINFREQ / 64);
- else
- return max_freq ? (XTALMAXFREQ / 32)
- : (XTALMINFREQ / 32);
- } else if (sii->pub.ccrev < 10) {
- div = 4 *
- (((R_REG(&cc->slow_clk_ctl) & SCC_CD_MASK) >>
- SCC_CD_SHIFT) + 1);
- if (slowclk == SCC_SS_LPO)
- return max_freq ? LPOMAXFREQ : LPOMINFREQ;
- else if (slowclk == SCC_SS_XTAL)
- return max_freq ? (XTALMAXFREQ / div)
- : (XTALMINFREQ / div);
- else if (slowclk == SCC_SS_PCI)
- return max_freq ? (PCIMAXFREQ / div)
- : (PCIMINFREQ / div);
- else
- ASSERT(0);
- } else {
- /* Chipc rev 10 is InstaClock */
- div = R_REG(&cc->system_clk_ctl) >> SYCC_CD_SHIFT;
- div = 4 * (div + 1);
- return max_freq ? XTALMAXFREQ : (XTALMINFREQ / div);
- }
- return 0;
-}
-
-static void si_clkctl_setdelay(si_info_t *sii, void *chipcregs)
-{
- chipcregs_t *cc = (chipcregs_t *) chipcregs;
- uint slowmaxfreq, pll_delay, slowclk;
- uint pll_on_delay, fref_sel_delay;
-
- pll_delay = PLL_DELAY;
-
- /* If the slow clock is not sourced by the xtal then add the xtal_on_delay
- * since the xtal will also be powered down by dynamic clk control logic.
- */
-
- slowclk = si_slowclk_src(sii);
- if (slowclk != SCC_SS_XTAL)
- pll_delay += XTAL_ON_DELAY;
-
- /* Starting with 4318 it is ILP that is used for the delays */
- slowmaxfreq =
- si_slowclk_freq(sii, (sii->pub.ccrev >= 10) ? false : true, cc);
-
- pll_on_delay = ((slowmaxfreq * pll_delay) + 999999) / 1000000;
- fref_sel_delay = ((slowmaxfreq * FREF_DELAY) + 999999) / 1000000;
-
- W_REG(&cc->pll_on_delay, pll_on_delay);
- W_REG(&cc->fref_sel_delay, fref_sel_delay);
-}
-
-/* initialize power control delay registers */
-void si_clkctl_init(si_t *sih)
-{
- si_info_t *sii;
- uint origidx = 0;
- chipcregs_t *cc;
- bool fast;
-
- if (!CCCTL_ENAB(sih))
- return;
-
- sii = SI_INFO(sih);
- fast = SI_FAST(sii);
- if (!fast) {
- origidx = sii->curidx;
- cc = (chipcregs_t *) si_setcore(sih, CC_CORE_ID, 0);
- if (cc == NULL)
- return;
- } else {
- cc = (chipcregs_t *) CCREGS_FAST(sii);
- if (cc == NULL)
- return;
- }
- ASSERT(cc != NULL);
-
- /* set all Instaclk chip ILP to 1 MHz */
- if (sih->ccrev >= 10)
- SET_REG(&cc->system_clk_ctl, SYCC_CD_MASK,
- (ILP_DIV_1MHZ << SYCC_CD_SHIFT));
-
- si_clkctl_setdelay(sii, (void *)cc);
-
- if (!fast)
- si_setcoreidx(sih, origidx);
-}
-
-/* return the value suitable for writing to the dot11 core FAST_PWRUP_DELAY register */
-u16 si_clkctl_fast_pwrup_delay(si_t *sih)
-{
- si_info_t *sii;
- uint origidx = 0;
- chipcregs_t *cc;
- uint slowminfreq;
- u16 fpdelay;
- uint intr_val = 0;
- bool fast;
-
- sii = SI_INFO(sih);
- if (PMUCTL_ENAB(sih)) {
- INTR_OFF(sii, intr_val);
- fpdelay = si_pmu_fast_pwrup_delay(sih);
- INTR_RESTORE(sii, intr_val);
- return fpdelay;
- }
-
- if (!CCCTL_ENAB(sih))
- return 0;
-
- fast = SI_FAST(sii);
- fpdelay = 0;
- if (!fast) {
- origidx = sii->curidx;
- INTR_OFF(sii, intr_val);
- cc = (chipcregs_t *) si_setcore(sih, CC_CORE_ID, 0);
- if (cc == NULL)
- goto done;
- } else {
- cc = (chipcregs_t *) CCREGS_FAST(sii);
- if (cc == NULL)
- goto done;
- }
- ASSERT(cc != NULL);
-
- slowminfreq = si_slowclk_freq(sii, false, cc);
- fpdelay = (((R_REG(&cc->pll_on_delay) + 2) * 1000000) +
- (slowminfreq - 1)) / slowminfreq;
-
- done:
- if (!fast) {
- si_setcoreidx(sih, origidx);
- INTR_RESTORE(sii, intr_val);
- }
- return fpdelay;
-}
-
-/* turn primary xtal and/or pll off/on */
-int si_clkctl_xtal(si_t *sih, uint what, bool on)
-{
- si_info_t *sii;
- u32 in, out, outen;
-
- sii = SI_INFO(sih);
-
- switch (sih->bustype) {
-
-#ifdef BCMSDIO
- case SDIO_BUS:
- return -1;
-#endif /* BCMSDIO */
-
- case PCI_BUS:
- /* pcie core doesn't have any mapping to control the xtal pu */
- if (PCIE(sii))
- return -1;
-
- pci_read_config_dword(sii->pbus, PCI_GPIO_IN, &in);
- pci_read_config_dword(sii->pbus, PCI_GPIO_OUT, &out);
- pci_read_config_dword(sii->pbus, PCI_GPIO_OUTEN, &outen);
-
- /*
- * Avoid glitching the clock if GPRS is already using it.
- * We can't actually read the state of the PLLPD so we infer it
- * by the value of XTAL_PU which *is* readable via gpioin.
- */
- if (on && (in & PCI_CFG_GPIO_XTAL))
- return 0;
-
- if (what & XTAL)
- outen |= PCI_CFG_GPIO_XTAL;
- if (what & PLL)
- outen |= PCI_CFG_GPIO_PLL;
-
- if (on) {
- /* turn primary xtal on */
- if (what & XTAL) {
- out |= PCI_CFG_GPIO_XTAL;
- if (what & PLL)
- out |= PCI_CFG_GPIO_PLL;
- pci_write_config_dword(sii->pbus,
- PCI_GPIO_OUT, out);
- pci_write_config_dword(sii->pbus,
- PCI_GPIO_OUTEN, outen);
- udelay(XTAL_ON_DELAY);
- }
-
- /* turn pll on */
- if (what & PLL) {
- out &= ~PCI_CFG_GPIO_PLL;
- pci_write_config_dword(sii->pbus,
- PCI_GPIO_OUT, out);
- mdelay(2);
- }
- } else {
- if (what & XTAL)
- out &= ~PCI_CFG_GPIO_XTAL;
- if (what & PLL)
- out |= PCI_CFG_GPIO_PLL;
- pci_write_config_dword(sii->pbus,
- PCI_GPIO_OUT, out);
- pci_write_config_dword(sii->pbus,
- PCI_GPIO_OUTEN, outen);
- }
-
- default:
- return -1;
- }
-
- return 0;
-}
-
-/*
- * clock control policy function through chipcommon
- *
- * set dynamic clk control mode (forceslow, forcefast, dynamic)
- * returns true if we are forcing fast clock
- * this is a wrapper over the next internal function
- * to allow flexible policy settings for outside caller
- */
-bool si_clkctl_cc(si_t *sih, uint mode)
-{
- si_info_t *sii;
-
- sii = SI_INFO(sih);
-
- /* chipcommon cores prior to rev6 don't support dynamic clock control */
- if (sih->ccrev < 6)
- return false;
-
- if (PCI_FORCEHT(sii))
- return mode == CLK_FAST;
-
- return _si_clkctl_cc(sii, mode);
-}
-
-/* clk control mechanism through chipcommon, no policy checking */
-static bool _si_clkctl_cc(si_info_t *sii, uint mode)
-{
- uint origidx = 0;
- chipcregs_t *cc;
- u32 scc;
- uint intr_val = 0;
- bool fast = SI_FAST(sii);
-
- /* chipcommon cores prior to rev6 don't support dynamic clock control */
- if (sii->pub.ccrev < 6)
- return false;
-
- /* Chips with ccrev 10 are EOL and they don't have SYCC_HR which we use below */
- ASSERT(sii->pub.ccrev != 10);
-
- if (!fast) {
- INTR_OFF(sii, intr_val);
- origidx = sii->curidx;
-
- if ((sii->pub.bustype == SI_BUS) &&
- si_setcore(&sii->pub, MIPS33_CORE_ID, 0) &&
- (si_corerev(&sii->pub) <= 7) && (sii->pub.ccrev >= 10))
- goto done;
-
- cc = (chipcregs_t *) si_setcore(&sii->pub, CC_CORE_ID, 0);
- } else {
- cc = (chipcregs_t *) CCREGS_FAST(sii);
- if (cc == NULL)
- goto done;
- }
- ASSERT(cc != NULL);
-
- if (!CCCTL_ENAB(&sii->pub) && (sii->pub.ccrev < 20))
- goto done;
-
- switch (mode) {
- case CLK_FAST: /* FORCEHT, fast (pll) clock */
- if (sii->pub.ccrev < 10) {
- /* don't forget to force xtal back on before we clear SCC_DYN_XTAL.. */
- si_clkctl_xtal(&sii->pub, XTAL, ON);
- SET_REG(&cc->slow_clk_ctl,
- (SCC_XC | SCC_FS | SCC_IP), SCC_IP);
- } else if (sii->pub.ccrev < 20) {
- OR_REG(&cc->system_clk_ctl, SYCC_HR);
- } else {
- OR_REG(&cc->clk_ctl_st, CCS_FORCEHT);
- }
-
- /* wait for the PLL */
- if (PMUCTL_ENAB(&sii->pub)) {
- u32 htavail = CCS_HTAVAIL;
- SPINWAIT(((R_REG(&cc->clk_ctl_st) & htavail)
- == 0), PMU_MAX_TRANSITION_DLY);
- ASSERT(R_REG(&cc->clk_ctl_st) & htavail);
- } else {
- udelay(PLL_DELAY);
- }
- break;
-
- case CLK_DYNAMIC: /* enable dynamic clock control */
- if (sii->pub.ccrev < 10) {
- scc = R_REG(&cc->slow_clk_ctl);
- scc &= ~(SCC_FS | SCC_IP | SCC_XC);
- if ((scc & SCC_SS_MASK) != SCC_SS_XTAL)
- scc |= SCC_XC;
- W_REG(&cc->slow_clk_ctl, scc);
-
- /* for dynamic control, we have to release our xtal_pu "force on" */
- if (scc & SCC_XC)
- si_clkctl_xtal(&sii->pub, XTAL, OFF);
- } else if (sii->pub.ccrev < 20) {
- /* Instaclock */
- AND_REG(&cc->system_clk_ctl, ~SYCC_HR);
- } else {
- AND_REG(&cc->clk_ctl_st, ~CCS_FORCEHT);
- }
- break;
-
- default:
- ASSERT(0);
- }
-
- done:
- if (!fast) {
- si_setcoreidx(&sii->pub, origidx);
- INTR_RESTORE(sii, intr_val);
- }
- return mode == CLK_FAST;
-}
-
-/* Build device path. Support SI, PCI, and JTAG for now. */
-int si_devpath(si_t *sih, char *path, int size)
-{
- int slen;
-
- ASSERT(path != NULL);
- ASSERT(size >= SI_DEVPATH_BUFSZ);
-
- if (!path || size <= 0)
- return -1;
-
- switch (sih->bustype) {
- case SI_BUS:
- case JTAG_BUS:
- slen = snprintf(path, (size_t) size, "sb/%u/", si_coreidx(sih));
- break;
- case PCI_BUS:
- ASSERT((SI_INFO(sih))->pbus != NULL);
- slen = snprintf(path, (size_t) size, "pci/%u/%u/",
- ((struct pci_dev *)((SI_INFO(sih))->pbus))->bus->number,
- PCI_SLOT(
- ((struct pci_dev *)((SI_INFO(sih))->pbus))->devfn));
- break;
-
-#ifdef BCMSDIO
- case SDIO_BUS:
- SI_ERROR(("si_devpath: device 0 assumed\n"));
- slen = snprintf(path, (size_t) size, "sd/%u/", si_coreidx(sih));
- break;
-#endif
- default:
- slen = -1;
- ASSERT(0);
- break;
- }
-
- if (slen < 0 || slen >= size) {
- path[0] = '\0';
- return -1;
- }
-
- return 0;
-}
-
-/* Get a variable, but only if it has a devpath prefix */
-char *si_getdevpathvar(si_t *sih, const char *name)
-{
- char varname[SI_DEVPATH_BUFSZ + 32];
-
- si_devpathvar(sih, varname, sizeof(varname), name);
-
- return getvar(NULL, varname);
-}
-
-/* Get a variable, but only if it has a devpath prefix */
-int si_getdevpathintvar(si_t *sih, const char *name)
-{
-#if defined(BCMBUSTYPE) && (BCMBUSTYPE == SI_BUS)
- return getintvar(NULL, name);
-#else
- char varname[SI_DEVPATH_BUFSZ + 32];
-
- si_devpathvar(sih, varname, sizeof(varname), name);
-
- return getintvar(NULL, varname);
-#endif
-}
-
-char *si_getnvramflvar(si_t *sih, const char *name)
-{
- return getvar(NULL, name);
-}
-
-/* Concatenate the dev path with a varname into the given 'var' buffer
- * and return the 'var' pointer.
- * Nothing is done to the arguments if len == 0 or var is NULL, var is still returned.
- * On overflow, the first char will be set to '\0'.
- */
-static char *si_devpathvar(si_t *sih, char *var, int len, const char *name)
-{
- uint path_len;
-
- if (!var || len <= 0)
- return var;
-
- if (si_devpath(sih, var, len) == 0) {
- path_len = strlen(var);
-
- if (strlen(name) + 1 > (uint) (len - path_len))
- var[0] = '\0';
- else
- strncpy(var + path_len, name, len - path_len - 1);
- }
-
- return var;
-}
-
-/* return true if PCIE capability exists in the pci config space */
-static __used bool si_ispcie(si_info_t *sii)
-{
- u8 cap_ptr;
-
- if (sii->pub.bustype != PCI_BUS)
- return false;
-
- cap_ptr =
- pcicore_find_pci_capability(sii->pbus, PCI_CAP_PCIECAP_ID, NULL,
- NULL);
- if (!cap_ptr)
- return false;
-
- return true;
-}
-
-#ifdef BCMSDIO
-/* initialize the sdio core */
-void si_sdio_init(si_t *sih)
-{
- si_info_t *sii = SI_INFO(sih);
-
- if (((sih->buscoretype == PCMCIA_CORE_ID) && (sih->buscorerev >= 8)) ||
- (sih->buscoretype == SDIOD_CORE_ID)) {
- uint idx;
- sdpcmd_regs_t *sdpregs;
-
- /* get the current core index */
- idx = sii->curidx;
- ASSERT(idx == si_findcoreidx(sih, D11_CORE_ID, 0));
-
- /* switch to sdio core */
- sdpregs = (sdpcmd_regs_t *) si_setcore(sih, PCMCIA_CORE_ID, 0);
- if (!sdpregs)
- sdpregs =
- (sdpcmd_regs_t *) si_setcore(sih, SDIOD_CORE_ID, 0);
- ASSERT(sdpregs);
-
- SI_MSG(("si_sdio_init: For PCMCIA/SDIO Corerev %d, enable ints from core %d " "through SD core %d (%p)\n", sih->buscorerev, idx, sii->curidx, sdpregs));
-
- /* enable backplane error and core interrupts */
- W_REG(&sdpregs->hostintmask, I_SBINT);
- W_REG(&sdpregs->sbintmask,
- (I_SB_SERR | I_SB_RESPERR | (1 << idx)));
-
- /* switch back to previous core */
- si_setcoreidx(sih, idx);
- }
-
- /* enable interrupts */
- bcmsdh_intr_enable(sii->pbus);
-
-}
-#endif /* BCMSDIO */
-
-bool si_pci_war16165(si_t *sih)
-{
- si_info_t *sii;
-
- sii = SI_INFO(sih);
-
- return PCI(sii) && (sih->buscorerev <= 10);
-}
-
-void si_pci_up(si_t *sih)
-{
- si_info_t *sii;
-
- sii = SI_INFO(sih);
-
- /* if not pci bus, we're done */
- if (sih->bustype != PCI_BUS)
- return;
-
- if (PCI_FORCEHT(sii))
- _si_clkctl_cc(sii, CLK_FAST);
-
- if (PCIE(sii))
- pcicore_up(sii->pch, SI_PCIUP);
-
-}
-
-/* Unconfigure and/or apply various WARs when system is going to sleep mode */
-void si_pci_sleep(si_t *sih)
-{
- si_info_t *sii;
-
- sii = SI_INFO(sih);
-
- pcicore_sleep(sii->pch);
-}
-
-/* Unconfigure and/or apply various WARs when going down */
-void si_pci_down(si_t *sih)
-{
- si_info_t *sii;
-
- sii = SI_INFO(sih);
-
- /* if not pci bus, we're done */
- if (sih->bustype != PCI_BUS)
- return;
-
- /* release FORCEHT since chip is going to "down" state */
- if (PCI_FORCEHT(sii))
- _si_clkctl_cc(sii, CLK_DYNAMIC);
-
- pcicore_down(sii->pch, SI_PCIDOWN);
-}
-
-/*
- * Configure the pci core for pci client (NIC) action
- * coremask is the bitvec of cores by index to be enabled.
- */
-void si_pci_setup(si_t *sih, uint coremask)
-{
- si_info_t *sii;
- struct sbpciregs *pciregs = NULL;
- u32 siflag = 0, w;
- uint idx = 0;
-
- sii = SI_INFO(sih);
-
- if (sii->pub.bustype != PCI_BUS)
- return;
-
- ASSERT(PCI(sii) || PCIE(sii));
- ASSERT(sii->pub.buscoreidx != BADIDX);
-
- if (PCI(sii)) {
- /* get current core index */
- idx = sii->curidx;
-
- /* we interrupt on this backplane flag number */
- siflag = si_flag(sih);
-
- /* switch over to pci core */
- pciregs = (struct sbpciregs *)si_setcoreidx(sih, sii->pub.buscoreidx);
- }
-
- /*
- * Enable sb->pci interrupts. Assume
- * PCI rev 2.3 support was added in pci core rev 6 and things changed..
- */
- if (PCIE(sii) || (PCI(sii) && ((sii->pub.buscorerev) >= 6))) {
- /* pci config write to set this core bit in PCIIntMask */
- pci_read_config_dword(sii->pbus, PCI_INT_MASK, &w);
- w |= (coremask << PCI_SBIM_SHIFT);
- pci_write_config_dword(sii->pbus, PCI_INT_MASK, w);
- } else {
- /* set sbintvec bit for our flag number */
- si_setint(sih, siflag);
- }
-
- if (PCI(sii)) {
- OR_REG(&pciregs->sbtopci2,
- (SBTOPCI_PREF | SBTOPCI_BURST));
- if (sii->pub.buscorerev >= 11) {
- OR_REG(&pciregs->sbtopci2,
- SBTOPCI_RC_READMULTI);
- w = R_REG(&pciregs->clkrun);
- W_REG(&pciregs->clkrun,
- (w | PCI_CLKRUN_DSBL));
- w = R_REG(&pciregs->clkrun);
- }
-
- /* switch back to previous core */
- si_setcoreidx(sih, idx);
- }
-}
-
-/*
- * Fixup SROMless PCI device's configuration.
- * The current core may be changed upon return.
- */
-int si_pci_fixcfg(si_t *sih)
-{
- uint origidx, pciidx;
- struct sbpciregs *pciregs = NULL;
- sbpcieregs_t *pcieregs = NULL;
- void *regs = NULL;
- u16 val16, *reg16 = NULL;
-
- si_info_t *sii = SI_INFO(sih);
-
- ASSERT(sii->pub.bustype == PCI_BUS);
-
- /* Fixup PI in SROM shadow area to enable the correct PCI core access */
- /* save the current index */
- origidx = si_coreidx(&sii->pub);
-
- /* check 'pi' is correct and fix it if not */
- if (sii->pub.buscoretype == PCIE_CORE_ID) {
- pcieregs =
- (sbpcieregs_t *) si_setcore(&sii->pub, PCIE_CORE_ID, 0);
- regs = pcieregs;
- ASSERT(pcieregs != NULL);
- reg16 = &pcieregs->sprom[SRSH_PI_OFFSET];
- } else if (sii->pub.buscoretype == PCI_CORE_ID) {
- pciregs = (struct sbpciregs *)si_setcore(&sii->pub, PCI_CORE_ID, 0);
- regs = pciregs;
- ASSERT(pciregs != NULL);
- reg16 = &pciregs->sprom[SRSH_PI_OFFSET];
- }
- pciidx = si_coreidx(&sii->pub);
- val16 = R_REG(reg16);
- if (((val16 & SRSH_PI_MASK) >> SRSH_PI_SHIFT) != (u16) pciidx) {
- val16 =
- (u16) (pciidx << SRSH_PI_SHIFT) | (val16 &
- ~SRSH_PI_MASK);
- W_REG(reg16, val16);
- }
-
- /* restore the original index */
- si_setcoreidx(&sii->pub, origidx);
-
- pcicore_hwup(sii->pch);
- return 0;
-}
-
-/* mask&set gpiocontrol bits */
-u32 si_gpiocontrol(si_t *sih, u32 mask, u32 val, u8 priority)
-{
- uint regoff;
-
- regoff = 0;
-
- /* gpios could be shared on router platforms
- * ignore reservation if it's high priority (e.g., test apps)
- */
- if ((priority != GPIO_HI_PRIORITY) &&
- (sih->bustype == SI_BUS) && (val || mask)) {
- mask = priority ? (si_gpioreservation & mask) :
- ((si_gpioreservation | mask) & ~(si_gpioreservation));
- val &= mask;
- }
-
- regoff = offsetof(chipcregs_t, gpiocontrol);
- return si_corereg(sih, SI_CC_IDX, regoff, mask, val);
-}
-
-/* Return the size of the specified SOCRAM bank */
-static uint
-socram_banksize(si_info_t *sii, sbsocramregs_t *regs, u8 index,
- u8 mem_type)
-{
- uint banksize, bankinfo;
- uint bankidx = index | (mem_type << SOCRAM_BANKIDX_MEMTYPE_SHIFT);
-
- ASSERT(mem_type <= SOCRAM_MEMTYPE_DEVRAM);
-
- W_REG(®s->bankidx, bankidx);
- bankinfo = R_REG(®s->bankinfo);
- banksize =
- SOCRAM_BANKINFO_SZBASE * ((bankinfo & SOCRAM_BANKINFO_SZMASK) + 1);
- return banksize;
-}
-
-/* Return the RAM size of the SOCRAM core */
-u32 si_socram_size(si_t *sih)
-{
- si_info_t *sii;
- uint origidx;
- uint intr_val = 0;
-
- sbsocramregs_t *regs;
- bool wasup;
- uint corerev;
- u32 coreinfo;
- uint memsize = 0;
-
- sii = SI_INFO(sih);
-
- /* Block ints and save current core */
- INTR_OFF(sii, intr_val);
- origidx = si_coreidx(sih);
-
- /* Switch to SOCRAM core */
- regs = si_setcore(sih, SOCRAM_CORE_ID, 0);
- if (!regs)
- goto done;
-
- /* Get info for determining size */
- wasup = si_iscoreup(sih);
- if (!wasup)
- si_core_reset(sih, 0, 0);
- corerev = si_corerev(sih);
- coreinfo = R_REG(®s->coreinfo);
-
- /* Calculate size from coreinfo based on rev */
- if (corerev == 0)
- memsize = 1 << (16 + (coreinfo & SRCI_MS0_MASK));
- else if (corerev < 3) {
- memsize = 1 << (SR_BSZ_BASE + (coreinfo & SRCI_SRBSZ_MASK));
- memsize *= (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT;
- } else if ((corerev <= 7) || (corerev == 12)) {
- uint nb = (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT;
- uint bsz = (coreinfo & SRCI_SRBSZ_MASK);
- uint lss = (coreinfo & SRCI_LSS_MASK) >> SRCI_LSS_SHIFT;
- if (lss != 0)
- nb--;
- memsize = nb * (1 << (bsz + SR_BSZ_BASE));
- if (lss != 0)
- memsize += (1 << ((lss - 1) + SR_BSZ_BASE));
- } else {
- u8 i;
- uint nb = (coreinfo & SRCI_SRNB_MASK) >> SRCI_SRNB_SHIFT;
- for (i = 0; i < nb; i++)
- memsize +=
- socram_banksize(sii, regs, i, SOCRAM_MEMTYPE_RAM);
- }
-
- /* Return to previous state and core */
- if (!wasup)
- si_core_disable(sih, 0);
- si_setcoreidx(sih, origidx);
-
- done:
- INTR_RESTORE(sii, intr_val);
-
- return memsize;
-}
-
-void si_chipcontrl_epa4331(si_t *sih, bool on)
-{
- si_info_t *sii;
- chipcregs_t *cc;
- uint origidx;
- u32 val;
-
- sii = SI_INFO(sih);
- origidx = si_coreidx(sih);
-
- cc = (chipcregs_t *) si_setcore(sih, CC_CORE_ID, 0);
-
- val = R_REG(&cc->chipcontrol);
-
- if (on) {
- if (sih->chippkg == 9 || sih->chippkg == 0xb) {
- /* Ext PA Controls for 4331 12x9 Package */
- W_REG(&cc->chipcontrol, val |
- (CCTRL4331_EXTPA_EN |
- CCTRL4331_EXTPA_ON_GPIO2_5));
- } else {
- /* Ext PA Controls for 4331 12x12 Package */
- W_REG(&cc->chipcontrol,
- val | (CCTRL4331_EXTPA_EN));
- }
- } else {
- val &= ~(CCTRL4331_EXTPA_EN | CCTRL4331_EXTPA_ON_GPIO2_5);
- W_REG(&cc->chipcontrol, val);
- }
-
- si_setcoreidx(sih, origidx);
-}
-
-/* Enable BT-COEX & Ex-PA for 4313 */
-void si_epa_4313war(si_t *sih)
-{
- si_info_t *sii;
- chipcregs_t *cc;
- uint origidx;
-
- sii = SI_INFO(sih);
- origidx = si_coreidx(sih);
-
- cc = (chipcregs_t *) si_setcore(sih, CC_CORE_ID, 0);
-
- /* EPA Fix */
- W_REG(&cc->gpiocontrol,
- R_REG(&cc->gpiocontrol) | GPIO_CTRL_EPA_EN_MASK);
-
- si_setcoreidx(sih, origidx);
-}
-
-/* check if the device is removed */
-bool si_deviceremoved(si_t *sih)
-{
- u32 w;
- si_info_t *sii;
-
- sii = SI_INFO(sih);
-
- switch (sih->bustype) {
- case PCI_BUS:
- ASSERT(sii->pbus != NULL);
- pci_read_config_dword(sii->pbus, PCI_CFG_VID, &w);
- if ((w & 0xFFFF) != VENDOR_BROADCOM)
- return true;
- break;
- }
- return false;
-}
-
-bool si_is_sprom_available(si_t *sih)
-{
- if (sih->ccrev >= 31) {
- si_info_t *sii;
- uint origidx;
- chipcregs_t *cc;
- u32 sromctrl;
-
- if ((sih->cccaps & CC_CAP_SROM) == 0)
- return false;
-
- sii = SI_INFO(sih);
- origidx = sii->curidx;
- cc = si_setcoreidx(sih, SI_CC_IDX);
- sromctrl = R_REG(&cc->sromcontrol);
- si_setcoreidx(sih, origidx);
- return sromctrl & SRC_PRESENT;
- }
-
- switch (sih->chip) {
- case BCM4329_CHIP_ID:
- return (sih->chipst & CST4329_SPROM_SEL) != 0;
- case BCM4319_CHIP_ID:
- return (sih->chipst & CST4319_SPROM_SEL) != 0;
- case BCM4336_CHIP_ID:
- return (sih->chipst & CST4336_SPROM_PRESENT) != 0;
- case BCM4330_CHIP_ID:
- return (sih->chipst & CST4330_SPROM_PRESENT) != 0;
- case BCM4313_CHIP_ID:
- return (sih->chipst & CST4313_SPROM_PRESENT) != 0;
- case BCM4331_CHIP_ID:
- return (sih->chipst & CST4331_SPROM_PRESENT) != 0;
- default:
- return true;
- }
-}
-
-bool si_is_otp_disabled(si_t *sih)
-{
- switch (sih->chip) {
- case BCM4329_CHIP_ID:
- return (sih->chipst & CST4329_SPROM_OTP_SEL_MASK) ==
- CST4329_OTP_PWRDN;
- case BCM4319_CHIP_ID:
- return (sih->chipst & CST4319_SPROM_OTP_SEL_MASK) ==
- CST4319_OTP_PWRDN;
- case BCM4336_CHIP_ID:
- return (sih->chipst & CST4336_OTP_PRESENT) == 0;
- case BCM4330_CHIP_ID:
- return (sih->chipst & CST4330_OTP_PRESENT) == 0;
- case BCM4313_CHIP_ID:
- return (sih->chipst & CST4313_OTP_PRESENT) == 0;
- /* These chips always have their OTP on */
- case BCM43224_CHIP_ID:
- case BCM43225_CHIP_ID:
- case BCM43421_CHIP_ID:
- case BCM43235_CHIP_ID:
- case BCM43236_CHIP_ID:
- case BCM43238_CHIP_ID:
- case BCM4331_CHIP_ID:
- default:
- return false;
- }
-}
-
-bool si_is_otp_powered(si_t *sih)
-{
- if (PMUCTL_ENAB(sih))
- return si_pmu_is_otp_powered(sih);
- return true;
-}
-
-void si_otp_power(si_t *sih, bool on)
-{
- if (PMUCTL_ENAB(sih))
- si_pmu_otp_power(sih, on);
- udelay(1000);
-}
-
diff --git a/drivers/staging/brcm80211/util/siutils_priv.h b/drivers/staging/brcm80211/util/siutils_priv.h
deleted file mode 100644
index a03ff61..0000000
--- a/drivers/staging/brcm80211/util/siutils_priv.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * Copyright (c) 2010 Broadcom Corporation
- *
- * Permission to use, copy, modify, and/or distribute this software for any
- * purpose with or without fee is hereby granted, provided that the above
- * copyright notice and this permission notice appear in all copies.
- *
- * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
- * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
- * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
- * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
- * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
- * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
- */
-
-#ifndef _siutils_priv_h_
-#define _siutils_priv_h_
-
-/* Silicon Backplane externs */
-extern void sb_scan(si_t *sih, void *regs, uint devid);
-uint sb_coreid(si_t *sih);
-uint sb_corerev(si_t *sih);
-extern uint sb_corereg(si_t *sih, uint coreidx, uint regoff, uint mask,
- uint val);
-extern bool sb_iscoreup(si_t *sih);
-void *sb_setcoreidx(si_t *sih, uint coreidx);
-extern void sb_core_reset(si_t *sih, u32 bits, u32 resetbits);
-extern void sb_core_disable(si_t *sih, u32 bits);
-#endif /* _siutils_priv_h_ */
diff --git a/drivers/staging/comedi/drivers/addi-data/APCI1710_Ssi.c b/drivers/staging/comedi/drivers/addi-data/APCI1710_Ssi.c
index 0c890a9..c13b002 100644
--- a/drivers/staging/comedi/drivers/addi-data/APCI1710_Ssi.c
+++ b/drivers/staging/comedi/drivers/addi-data/APCI1710_Ssi.c
@@ -35,22 +35,8 @@
| Project manager: Eric Stolz | Date : 02/12/2002 |
+-----------------------------------------------------------------------+
| Description : APCI-1710 SSI counter module |
- | |
- | |
+-----------------------------------------------------------------------+
- | UPDATES |
- +-----------------------------------------------------------------------+
- | Date | Author | Description of updates |
- +----------+-----------+------------------------------------------------+
- | 13/05/98 | S. Weber | SSI digital input / output implementation |
- |----------|-----------|------------------------------------------------|
- | 22/03/00 | C.Guinot | 0100/0226 -> 0200/0227 |
- | | | Änderung in InitSSI Funktion |
- | | | b_SSIProfile >= 2 anstatt b_SSIProfile > 2 |
- | | | |
- +-----------------------------------------------------------------------+
- | 08/05/00 | Guinot C | - 0400/0228 All Function in RING 0 |
- | | | available |
+ | several changes done by S. Weber in 1998 and C. Guinot in 2000 |
+-----------------------------------------------------------------------+
*/
diff --git a/drivers/staging/comedi/drivers/addi-data/addi_common.c b/drivers/staging/comedi/drivers/addi-data/addi_common.c
index 76f2483..6cf19ed 100644
--- a/drivers/staging/comedi/drivers/addi-data/addi_common.c
+++ b/drivers/staging/comedi/drivers/addi-data/addi_common.c
@@ -77,7 +77,7 @@
/* Update-0.7.57->0.7.68MODULE_LICENSE("GPL"); */
#define devpriv ((struct addi_private *)dev->private)
-#define this_board ((struct addi_board *)dev->board_ptr)
+#define this_board ((const struct addi_board *)dev->board_ptr)
#if defined(CONFIG_APCI_1710) || defined(CONFIG_APCI_3200) || defined(CONFIG_APCI_3300)
/* BYTE b_SaveFPUReg [94]; */
@@ -2666,13 +2666,11 @@
devpriv->i_IobaseAmcc = (int) iobase_a; /* AMCC base address... */
devpriv->i_IobaseAddon = (int) iobase_addon; /* ADD ON base address.... */
devpriv->i_IobaseReserved = (int) iobase_reserved;
- devpriv->ps_BoardInfo = this_board;
} else {
dev->board_name = this_board->pc_DriverName;
dev->iobase = (unsigned long)io_addr[2];
devpriv->amcc = card;
devpriv->iobase = (int) io_addr[2];
- devpriv->ps_BoardInfo = this_board;
devpriv->i_IobaseReserved = (int) io_addr[3];
printk("\nioremap begin");
devpriv->dw_AiBase = ioremap(io_addr[3],
@@ -2680,6 +2678,21 @@
printk("\nioremap end");
}
+ /* Initialize parameters that can be overridden in EEPROM */
+ devpriv->s_EeParameters.i_NbrAiChannel = this_board->i_NbrAiChannel;
+ devpriv->s_EeParameters.i_NbrAoChannel = this_board->i_NbrAoChannel;
+ devpriv->s_EeParameters.i_AiMaxdata = this_board->i_AiMaxdata;
+ devpriv->s_EeParameters.i_AoMaxdata = this_board->i_AoMaxdata;
+ devpriv->s_EeParameters.i_NbrDiChannel = this_board->i_NbrDiChannel;
+ devpriv->s_EeParameters.i_NbrDoChannel = this_board->i_NbrDoChannel;
+ devpriv->s_EeParameters.i_DoMaxdata = this_board->i_DoMaxdata;
+ devpriv->s_EeParameters.i_Dma = this_board->i_Dma;
+ devpriv->s_EeParameters.i_Timer = this_board->i_Timer;
+ devpriv->s_EeParameters.ui_MinAcquisitiontimeNs =
+ this_board->ui_MinAcquisitiontimeNs;
+ devpriv->s_EeParameters.ui_MinDelaytimeNs =
+ this_board->ui_MinDelaytimeNs;
+
/* ## */
if (irq > 0) {
@@ -2728,7 +2741,7 @@
devpriv->us_UseDma = ADDI_ENABLE;
}
- if (this_board->i_Dma) {
+ if (devpriv->s_EeParameters.i_Dma) {
printk("\nDMA used");
if (devpriv->us_UseDma == ADDI_ENABLE) {
/* alloc DMA buffers */
@@ -2787,21 +2800,22 @@
/* Allocate and Initialise AI Subdevice Structures */
s = dev->subdevices + 0;
- if ((this_board->i_NbrAiChannel)
+ if ((devpriv->s_EeParameters.i_NbrAiChannel)
|| (this_board->i_NbrAiChannelDiff)) {
dev->read_subdev = s;
s->type = COMEDI_SUBD_AI;
s->subdev_flags =
SDF_READABLE | SDF_COMMON | SDF_GROUND
| SDF_DIFF;
- if (this_board->i_NbrAiChannel) {
- s->n_chan = this_board->i_NbrAiChannel;
+ if (devpriv->s_EeParameters.i_NbrAiChannel) {
+ s->n_chan =
+ devpriv->s_EeParameters.i_NbrAiChannel;
devpriv->b_SingelDiff = 0;
} else {
s->n_chan = this_board->i_NbrAiChannelDiff;
devpriv->b_SingelDiff = 1;
}
- s->maxdata = this_board->i_AiMaxdata;
+ s->maxdata = devpriv->s_EeParameters.i_AiMaxdata;
s->len_chanlist = this_board->i_AiChannelList;
s->range_table = this_board->pr_AiRangelist;
@@ -2825,12 +2839,13 @@
/* Allocate and Initialise AO Subdevice Structures */
s = dev->subdevices + 1;
- if (this_board->i_NbrAoChannel) {
+ if (devpriv->s_EeParameters.i_NbrAoChannel) {
s->type = COMEDI_SUBD_AO;
s->subdev_flags = SDF_WRITEABLE | SDF_GROUND | SDF_COMMON;
- s->n_chan = this_board->i_NbrAoChannel;
- s->maxdata = this_board->i_AoMaxdata;
- s->len_chanlist = this_board->i_NbrAoChannel;
+ s->n_chan = devpriv->s_EeParameters.i_NbrAoChannel;
+ s->maxdata = devpriv->s_EeParameters.i_AoMaxdata;
+ s->len_chanlist =
+ devpriv->s_EeParameters.i_NbrAoChannel;
s->range_table = this_board->pr_AoRangelist;
s->insn_config =
this_board->i_hwdrv_InsnConfigAnalogOutput;
@@ -2841,12 +2856,13 @@
}
/* Allocate and Initialise DI Subdevice Structures */
s = dev->subdevices + 2;
- if (this_board->i_NbrDiChannel) {
+ if (devpriv->s_EeParameters.i_NbrDiChannel) {
s->type = COMEDI_SUBD_DI;
s->subdev_flags = SDF_READABLE | SDF_GROUND | SDF_COMMON;
- s->n_chan = this_board->i_NbrDiChannel;
+ s->n_chan = devpriv->s_EeParameters.i_NbrDiChannel;
s->maxdata = 1;
- s->len_chanlist = this_board->i_NbrDiChannel;
+ s->len_chanlist =
+ devpriv->s_EeParameters.i_NbrDiChannel;
s->range_table = &range_digital;
s->io_bits = 0; /* all bits input */
s->insn_config =
@@ -2860,13 +2876,14 @@
}
/* Allocate and Initialise DO Subdevice Structures */
s = dev->subdevices + 3;
- if (this_board->i_NbrDoChannel) {
+ if (devpriv->s_EeParameters.i_NbrDoChannel) {
s->type = COMEDI_SUBD_DO;
s->subdev_flags =
SDF_READABLE | SDF_WRITEABLE | SDF_GROUND | SDF_COMMON;
- s->n_chan = this_board->i_NbrDoChannel;
- s->maxdata = this_board->i_DoMaxdata;
- s->len_chanlist = this_board->i_NbrDoChannel;
+ s->n_chan = devpriv->s_EeParameters.i_NbrDoChannel;
+ s->maxdata = devpriv->s_EeParameters.i_DoMaxdata;
+ s->len_chanlist =
+ devpriv->s_EeParameters.i_NbrDoChannel;
s->range_table = &range_digital;
s->io_bits = 0xf; /* all bits output */
@@ -2883,7 +2900,7 @@
/* Allocate and Initialise Timer Subdevice Structures */
s = dev->subdevices + 4;
- if (this_board->i_Timer) {
+ if (devpriv->s_EeParameters.i_Timer) {
s->type = COMEDI_SUBD_TIMER;
s->subdev_flags = SDF_WRITEABLE | SDF_GROUND | SDF_COMMON;
s->n_chan = 1;
@@ -2968,8 +2985,8 @@
free_irq(dev->irq, dev);
}
- if ((devpriv->ps_BoardInfo->pc_EepromChip == NULL)
- || (strcmp(devpriv->ps_BoardInfo->pc_EepromChip,
+ if ((this_board->pc_EepromChip == NULL)
+ || (strcmp(this_board->pc_EepromChip,
ADDIDATA_9054) != 0)) {
if (devpriv->allocated) {
i_pci_card_free(devpriv->amcc);
diff --git a/drivers/staging/comedi/drivers/addi-data/addi_common.h b/drivers/staging/comedi/drivers/addi-data/addi_common.h
index 13621d4..c6980b7 100644
--- a/drivers/staging/comedi/drivers/addi-data/addi_common.h
+++ b/drivers/staging/comedi/drivers/addi-data/addi_common.h
@@ -406,7 +406,6 @@
/* Pointer to the current process */
struct task_struct *tsk_Current;
- struct addi_board *ps_BoardInfo;
/* Hardware board infos for 1710 */
struct {
@@ -434,6 +433,22 @@
union str_ModuleInfo s_ModuleInfo[4];
unsigned int ul_TTLPortConfiguration[10];
+ /* Parameters read from EEPROM overriding static board info */
+ struct {
+ int i_NbrAiChannel; /* num of A/D chans */
+ int i_NbrAoChannel; /* num of D/A chans */
+ int i_AiMaxdata; /* resolution of A/D */
+ int i_AoMaxdata; /* resolution of D/A */
+ int i_NbrDiChannel; /* Number of DI channels */
+ int i_NbrDoChannel; /* Number of DO channels */
+ int i_DoMaxdata; /* data to set all channels high */
+ int i_Dma; /* dma present or not */
+ int i_Timer; /* timer subdevice present or not */
+ unsigned int ui_MinAcquisitiontimeNs;
+ /* Minimum Acquisition in Nano secs */
+ unsigned int ui_MinDelaytimeNs;
+ /* Minimum Delay in Nano secs */
+ } s_EeParameters;
};
static unsigned short pci_list_builded; /* set to 1 when list of card is known */
diff --git a/drivers/staging/comedi/drivers/addi-data/addi_eeprom.c b/drivers/staging/comedi/drivers/addi-data/addi_eeprom.c
index 0aa11a0..3a9339b 100644
--- a/drivers/staging/comedi/drivers/addi-data/addi_eeprom.c
+++ b/drivers/staging/comedi/drivers/addi-data/addi_eeprom.c
@@ -847,7 +847,7 @@
pc_PCIChipInformation,
s_MainHeader.s_Functions[i].w_Address,
&s_DigitalInputHeader);
- this_board->i_NbrDiChannel =
+ devpriv->s_EeParameters.i_NbrDiChannel =
s_DigitalInputHeader.w_Nchannel;
break;
@@ -856,11 +856,12 @@
pc_PCIChipInformation,
s_MainHeader.s_Functions[i].w_Address,
&s_DigitalOutputHeader);
- this_board->i_NbrDoChannel =
+ devpriv->s_EeParameters.i_NbrDoChannel =
s_DigitalOutputHeader.w_Nchannel;
ui_Temp = 0xffffffff;
- this_board->i_DoMaxdata =
- ui_Temp >> (32 - this_board->i_NbrDoChannel);
+ devpriv->s_EeParameters.i_DoMaxdata =
+ ui_Temp >> (32 -
+ devpriv->s_EeParameters.i_NbrDoChannel);
break;
case EEPROM_ANALOGINPUT:
@@ -869,20 +870,21 @@
s_MainHeader.s_Functions[i].w_Address,
&s_AnalogInputHeader);
if (!(strcmp(this_board->pc_DriverName, "apci3200")))
- this_board->i_NbrAiChannel =
+ devpriv->s_EeParameters.i_NbrAiChannel =
s_AnalogInputHeader.w_Nchannel * 4;
else
- this_board->i_NbrAiChannel =
+ devpriv->s_EeParameters.i_NbrAiChannel =
s_AnalogInputHeader.w_Nchannel;
- this_board->i_Dma = s_AnalogInputHeader.b_HasDma;
- this_board->ui_MinAcquisitiontimeNs =
+ devpriv->s_EeParameters.i_Dma =
+ s_AnalogInputHeader.b_HasDma;
+ devpriv->s_EeParameters.ui_MinAcquisitiontimeNs =
(unsigned int) s_AnalogInputHeader.w_MinConvertTiming *
1000;
- this_board->ui_MinDelaytimeNs =
+ devpriv->s_EeParameters.ui_MinDelaytimeNs =
(unsigned int) s_AnalogInputHeader.w_MinDelayTiming *
1000;
ui_Temp = 0xffff;
- this_board->i_AiMaxdata =
+ devpriv->s_EeParameters.i_AiMaxdata =
ui_Temp >> (16 -
s_AnalogInputHeader.b_Resolution);
break;
@@ -892,24 +894,28 @@
pc_PCIChipInformation,
s_MainHeader.s_Functions[i].w_Address,
&s_AnalogOutputHeader);
- this_board->i_NbrAoChannel =
+ devpriv->s_EeParameters.i_NbrAoChannel =
s_AnalogOutputHeader.w_Nchannel;
ui_Temp = 0xffff;
- this_board->i_AoMaxdata =
+ devpriv->s_EeParameters.i_AoMaxdata =
ui_Temp >> (16 -
s_AnalogOutputHeader.b_Resolution);
break;
case EEPROM_TIMER:
- this_board->i_Timer = 1; /* Timer subdevice present */
+ /* Timer subdevice present */
+ devpriv->s_EeParameters.i_Timer = 1;
break;
case EEPROM_WATCHDOG:
- this_board->i_Timer = 1; /* Timer subdevice present */
+ /* Timer subdevice present */
+ devpriv->s_EeParameters.i_Timer = 1;
break;
case EEPROM_TIMER_WATCHDOG_COUNTER:
- this_board->i_Timer = 1; /* Timer subdevice present */
+ /* Timer subdevice present */
+ devpriv->s_EeParameters.i_Timer = 1;
+ break;
}
}
diff --git a/drivers/staging/comedi/drivers/addi-data/hwdrv_apci16xx.c b/drivers/staging/comedi/drivers/addi-data/hwdrv_apci16xx.c
index 8ebb254..00a088f 100644
--- a/drivers/staging/comedi/drivers/addi-data/hwdrv_apci16xx.c
+++ b/drivers/staging/comedi/drivers/addi-data/hwdrv_apci16xx.c
@@ -97,7 +97,7 @@
unsigned char b_Command = 0;
unsigned char b_Cpt = 0;
unsigned char b_NumberOfPort =
- (unsigned char) (devpriv->ps_BoardInfo->i_NbrTTLChannel / 8);
+ (unsigned char) (this_board->i_NbrTTLChannel / 8);
/************************/
/* Test the buffer size */
@@ -289,7 +289,7 @@
int i_ReturnValue = insn->n;
unsigned char b_Command = 0;
unsigned char b_NumberOfPort =
- (unsigned char) (devpriv->ps_BoardInfo->i_NbrTTLChannel / 8);
+ (unsigned char) (this_board->i_NbrTTLChannel / 8);
unsigned char b_SelectedPort = CR_RANGE(insn->chanspec);
unsigned char b_InputChannel = CR_CHAN(insn->chanspec);
unsigned char *pb_Status;
@@ -450,9 +450,9 @@
/**********************************/
b_NumberOfPort =
- (unsigned char) (devpriv->ps_BoardInfo->i_NbrTTLChannel / 32);
+ (unsigned char) (this_board->i_NbrTTLChannel / 32);
if ((b_NumberOfPort * 32) <
- devpriv->ps_BoardInfo->i_NbrTTLChannel) {
+ this_board->i_NbrTTLChannel) {
b_NumberOfPort = b_NumberOfPort + 1;
}
@@ -576,7 +576,7 @@
int i_ReturnValue = insn->n;
unsigned char b_Command = 0;
unsigned char b_NumberOfPort =
- (unsigned char) (devpriv->ps_BoardInfo->i_NbrTTLChannel / 8);
+ (unsigned char) (this_board->i_NbrTTLChannel / 8);
unsigned char b_SelectedPort = CR_RANGE(insn->chanspec);
unsigned char b_OutputChannel = CR_CHAN(insn->chanspec);
unsigned int dw_Status = 0;
diff --git a/drivers/staging/comedi/drivers/addi-data/hwdrv_apci3120.c b/drivers/staging/comedi/drivers/addi-data/hwdrv_apci3120.c
index fc61214..e886ced 100644
--- a/drivers/staging/comedi/drivers/addi-data/hwdrv_apci3120.c
+++ b/drivers/staging/comedi/drivers/addi-data/hwdrv_apci3120.c
@@ -90,7 +90,8 @@
/* Test the number of the channel */
for (i = 0; i < data[3]; i++) {
- if (CR_CHAN(data[4 + i]) >= this_board->i_NbrAiChannel) {
+ if (CR_CHAN(data[4 + i]) >=
+ devpriv->s_EeParameters.i_NbrAiChannel) {
printk("bad channel list\n");
return -2;
}
@@ -541,8 +542,10 @@
}
if (cmd->scan_begin_src == TRIG_TIMER) { /* Test Delay timing */
- if (cmd->scan_begin_arg < this_board->ui_MinDelaytimeNs) {
- cmd->scan_begin_arg = this_board->ui_MinDelaytimeNs;
+ if (cmd->scan_begin_arg <
+ devpriv->s_EeParameters.ui_MinDelaytimeNs) {
+ cmd->scan_begin_arg =
+ devpriv->s_EeParameters.ui_MinDelaytimeNs;
err++;
}
}
@@ -551,16 +554,18 @@
if (cmd->scan_begin_src == TRIG_TIMER) {
if ((cmd->convert_arg)
&& (cmd->convert_arg <
- this_board->ui_MinAcquisitiontimeNs)) {
- cmd->convert_arg =
- this_board->ui_MinAcquisitiontimeNs;
+ devpriv->s_EeParameters.
+ ui_MinAcquisitiontimeNs)) {
+ cmd->convert_arg = devpriv->s_EeParameters.
+ ui_MinAcquisitiontimeNs;
err++;
}
} else {
if (cmd->convert_arg <
- this_board->ui_MinAcquisitiontimeNs) {
- cmd->convert_arg =
- this_board->ui_MinAcquisitiontimeNs;
+ devpriv->s_EeParameters.ui_MinAcquisitiontimeNs
+ ) {
+ cmd->convert_arg = devpriv->s_EeParameters.
+ ui_MinAcquisitiontimeNs;
err++;
}
@@ -2452,7 +2457,7 @@
struct comedi_insn *insn,
unsigned int *data)
{
- if ((data[0] > this_board->i_DoMaxdata) || (data[0] < 0)) {
+ if ((data[0] > devpriv->s_EeParameters.i_DoMaxdata) || (data[0] < 0)) {
comedi_error(dev, "Data is not valid !!! \n");
return -EINVAL;
@@ -2515,7 +2520,7 @@
"Not a valid Data !!! ,Data should be 1 or 0\n");
return -EINVAL;
}
- if (ui_NoOfChannel > this_board->i_NbrDoChannel - 1) {
+ if (ui_NoOfChannel > devpriv->s_EeParameters.i_NbrDoChannel - 1) {
comedi_error(dev,
"This board doesn't have specified channel !!! \n");
return -EINVAL;
diff --git a/drivers/staging/comedi/drivers/addi-data/hwdrv_apci3xxx.c b/drivers/staging/comedi/drivers/addi-data/hwdrv_apci3xxx.c
index d3c5963..fff99df 100644
--- a/drivers/staging/comedi/drivers/addi-data/hwdrv_apci3xxx.c
+++ b/drivers/staging/comedi/drivers/addi-data/hwdrv_apci3xxx.c
@@ -141,8 +141,7 @@
/* Test the time base */
/**********************/
- if ((devpriv->ps_BoardInfo->
- b_AvailableConvertUnit & (1 << b_TimeBase)) !=
+ if ((this_board->b_AvailableConvertUnit & (1 << b_TimeBase)) !=
0) {
/*******************************/
/* Test the convert time value */
@@ -165,12 +164,16 @@
/*******************************/
if (dw_TestReloadValue >=
- devpriv->ps_BoardInfo->
+ devpriv->s_EeParameters.
ui_MinAcquisitiontimeNs) {
if ((b_SingleDiff == APCI3XXX_SINGLE)
|| (b_SingleDiff ==
APCI3XXX_DIFF)) {
- if (((b_SingleDiff == APCI3XXX_SINGLE) && (devpriv->ps_BoardInfo->i_NbrAiChannel == 0)) || ((b_SingleDiff == APCI3XXX_DIFF) && (devpriv->ps_BoardInfo->i_NbrAiChannelDiff == 0))) {
+ if (((b_SingleDiff == APCI3XXX_SINGLE)
+ && (devpriv->s_EeParameters.i_NbrAiChannel == 0))
+ || ((b_SingleDiff == APCI3XXX_DIFF)
+ && (this_board->i_NbrAiChannelDiff == 0))
+ ) {
/*******************************/
/* Single/Diff selection error */
/*******************************/
@@ -372,10 +375,9 @@
/* Test the channel number */
/***************************/
- if (((b_Channel < devpriv->ps_BoardInfo->i_NbrAiChannel)
+ if (((b_Channel < devpriv->s_EeParameters.i_NbrAiChannel)
&& (devpriv->b_SingelDiff == APCI3XXX_SINGLE))
- || ((b_Channel < devpriv->ps_BoardInfo->
- i_NbrAiChannelDiff)
+ || ((b_Channel < this_board->i_NbrAiChannelDiff)
&& (devpriv->b_SingelDiff == APCI3XXX_DIFF))) {
/**********************************/
/* Test the channel configuration */
@@ -663,7 +665,7 @@
/* Test the channel number */
/***************************/
- if (b_Channel < devpriv->ps_BoardInfo->i_NbrAoChannel) {
+ if (b_Channel < devpriv->s_EeParameters.i_NbrAoChannel) {
/**********************************/
/* Test the channel configuration */
/**********************************/
@@ -1273,7 +1275,7 @@
/* Test the channel number */
/***************************/
- if (b_Channel <= devpriv->ps_BoardInfo->i_NbrDiChannel) {
+ if (b_Channel <= devpriv->s_EeParameters.i_NbrDiChannel) {
/************************/
/* Test the buffer size */
/************************/
@@ -1492,7 +1494,7 @@
/* Test the channel number */
/***************************/
- if (b_Channel < devpriv->ps_BoardInfo->i_NbrDoChannel) {
+ if (b_Channel < devpriv->s_EeParameters.i_NbrDoChannel) {
/*******************/
/* Get the command */
/*******************/
@@ -1568,7 +1570,7 @@
/* Test the channel number */
/***************************/
- if (b_Channel < devpriv->ps_BoardInfo->i_NbrDoChannel) {
+ if (b_Channel < devpriv->s_EeParameters.i_NbrDoChannel) {
/********************************/
/* Read the digital output port */
/********************************/
diff --git a/drivers/staging/comedi/drivers/adl_pci9118.c b/drivers/staging/comedi/drivers/adl_pci9118.c
index 632d5d0..08b71d9 100644
--- a/drivers/staging/comedi/drivers/adl_pci9118.c
+++ b/drivers/staging/comedi/drivers/adl_pci9118.c
@@ -1417,7 +1417,7 @@
comedi_error(dev,
"pci9118_ai_docmd_sampl() mode number bug!\n");
return -EIO;
- };
+ }
devpriv->int_ai_func = interrupt_pci9118_ai_onesample;
/* transfer function */
@@ -1496,7 +1496,7 @@
default:
comedi_error(dev, "pci9118_ai_docmd_dma() mode number bug!\n");
return -EIO;
- };
+ }
if (devpriv->ai12_startstop) {
pci9118_exttrg_add(dev, EXTTRG_AI);
diff --git a/drivers/staging/comedi/drivers/adv_pci_dio.c b/drivers/staging/comedi/drivers/adv_pci_dio.c
index 9102667..d23799b 100644
--- a/drivers/staging/comedi/drivers/adv_pci_dio.c
+++ b/drivers/staging/comedi/drivers/adv_pci_dio.c
@@ -117,6 +117,7 @@
/* Advantech PCI-1751/3/3E */
#define PCI1751_DIO 0 /* R/W: begin of 8255 registers block */
+#define PCI1751_CNT 24 /* R/W: begin of 8254 registers block */
#define PCI1751_ICR 32 /* W: Interrupt control register */
#define PCI1751_ISR 32 /* R: Interrupt status register */
#define PCI1753_DIO 0 /* R/W: begin of 8255 registers block */
@@ -329,7 +330,7 @@
{ {0, 0, 0, 0}, {0, 0, 0, 0} },
{ {48, PCI1751_DIO, 2, 0}, {0, 0, 0, 0} },
{0, 0, 0, 0},
- { {0, 0, 0, 0} },
+ { {3, PCI1751_CNT, 1, 0} },
IO_8b},
{"pci1752", PCI_VENDOR_ID_ADVANTECH, 0x1752, PCIDIO_MAINREG,
TYPE_PCI1752,
diff --git a/drivers/staging/comedi/drivers/cb_das16_cs.c b/drivers/staging/comedi/drivers/cb_das16_cs.c
index bb93685..8a1b8a7 100644
--- a/drivers/staging/comedi/drivers/cb_das16_cs.c
+++ b/drivers/staging/comedi/drivers/cb_das16_cs.c
@@ -772,7 +772,7 @@
/*====================================================================*/
-static struct pcmcia_device_id das16cs_id_table[] = {
+static const struct pcmcia_device_id das16cs_id_table[] = {
PCMCIA_DEVICE_MANF_CARD(0x01c5, 0x0039),
PCMCIA_DEVICE_MANF_CARD(0x01c5, 0x4009),
PCMCIA_DEVICE_NULL
diff --git a/drivers/staging/comedi/drivers/cb_pcidda.c b/drivers/staging/comedi/drivers/cb_pcidda.c
index 6383fc9..49102b3 100644
--- a/drivers/staging/comedi/drivers/cb_pcidda.c
+++ b/drivers/staging/comedi/drivers/cb_pcidda.c
@@ -650,7 +650,7 @@
case 5:
command |= UNIP | RANGE2V5;
break;
- };
+ }
/* output channel specification */
command |= channel << 2;
diff --git a/drivers/staging/comedi/drivers/cb_pcimdas.c b/drivers/staging/comedi/drivers/cb_pcimdas.c
index 3d53df0..b1b832b 100644
--- a/drivers/staging/comedi/drivers/cb_pcimdas.c
+++ b/drivers/staging/comedi/drivers/cb_pcimdas.c
@@ -264,7 +264,7 @@
default:
printk("THIS CARD IS UNSUPPORTED.\n"
"PLEASE REPORT USAGE TO <mocelet@sucs.org>\n");
- };
+ }
if (comedi_pci_enable(pcidev, "cb_pcimdas")) {
printk(" Failed to enable PCI device and request regions\n");
diff --git a/drivers/staging/comedi/drivers/das08_cs.c b/drivers/staging/comedi/drivers/das08_cs.c
index 0b32a2d..6d91d30 100644
--- a/drivers/staging/comedi/drivers/das08_cs.c
+++ b/drivers/staging/comedi/drivers/das08_cs.c
@@ -219,7 +219,7 @@
/*====================================================================*/
-static struct pcmcia_device_id das08_cs_id_table[] = {
+static const struct pcmcia_device_id das08_cs_id_table[] = {
PCMCIA_DEVICE_MANF_CARD(0x01c5, 0x4001),
PCMCIA_DEVICE_NULL
};
diff --git a/drivers/staging/comedi/drivers/jr3_pci.c b/drivers/staging/comedi/drivers/jr3_pci.c
index 5c6c727..8d98cf4 100644
--- a/drivers/staging/comedi/drivers/jr3_pci.c
+++ b/drivers/staging/comedi/drivers/jr3_pci.c
@@ -193,9 +193,8 @@
set_s16(&channel->transforms[num].link[i].link_amount,
transf.link[i].link_amount);
udelay(1);
- if (transf.link[i].link_type == end_x_form) {
+ if (transf.link[i].link_type == end_x_form)
break;
- }
}
}
@@ -460,9 +459,8 @@
unsigned int count, addr;
more = more
&& read_idm_word(data, size, &pos, &count);
- if (more && count == 0xffff) {
+ if (more && count == 0xffff)
break;
- }
more = more
&& read_idm_word(data, size, &pos, &addr);
printk("Loading#%d %4.4x bytes at %4.4x\n", i,
@@ -793,9 +791,8 @@
}
result = alloc_private(dev, sizeof(struct jr3_pci_dev_private));
- if (result < 0) {
+ if (result < 0)
return -ENOMEM;
- }
card = NULL;
devpriv = dev->private;
init_timer(&devpriv->timer);
@@ -851,9 +848,8 @@
}
result = comedi_pci_enable(card, "jr3_pci");
- if (result < 0) {
+ if (result < 0)
return -EIO;
- }
devpriv->pci_enabled = 1;
devpriv->iobase = ioremap(pci_resource_start(card, 0),
@@ -922,9 +918,8 @@
result = comedi_load_firmware(dev, "jr3pci.idm", jr3_download_firmware);
printk("Firmare load %d\n", result);
- if (result < 0) {
+ if (result < 0)
goto out;
- }
/*
* TODO: use firmware to load preferred offset tables. Suggested
* format:
@@ -973,21 +968,17 @@
del_timer_sync(&devpriv->timer);
if (dev->subdevices) {
- for (i = 0; i < devpriv->n_channels; i++) {
+ for (i = 0; i < devpriv->n_channels; i++)
kfree(dev->subdevices[i].private);
- }
}
- if (devpriv->iobase) {
+ if (devpriv->iobase)
iounmap((void *)devpriv->iobase);
- }
- if (devpriv->pci_enabled) {
+ if (devpriv->pci_enabled)
comedi_pci_disable(devpriv->pci_dev);
- }
- if (devpriv->pci_dev) {
+ if (devpriv->pci_dev)
pci_dev_put(devpriv->pci_dev);
- }
}
return 0;
}
diff --git a/drivers/staging/comedi/drivers/ni_660x.c b/drivers/staging/comedi/drivers/ni_660x.c
index ca2aeaa..35f3a47 100644
--- a/drivers/staging/comedi/drivers/ni_660x.c
+++ b/drivers/staging/comedi/drivers/ni_660x.c
@@ -1418,7 +1418,7 @@
default:
return -EINVAL;
break;
- };
+ }
return 0;
}
diff --git a/drivers/staging/comedi/drivers/ni_daq_700.c b/drivers/staging/comedi/drivers/ni_daq_700.c
index 6b7372e..2672629 100644
--- a/drivers/staging/comedi/drivers/ni_daq_700.c
+++ b/drivers/staging/comedi/drivers/ni_daq_700.c
@@ -552,7 +552,7 @@
/*====================================================================*/
-static struct pcmcia_device_id dio700_cs_ids[] = {
+static const struct pcmcia_device_id dio700_cs_ids[] = {
/* N.B. These IDs should match those in dio700_boards */
PCMCIA_DEVICE_MANF_CARD(0x010b, 0x4743), /* daqcard-700 */
PCMCIA_DEVICE_NULL
diff --git a/drivers/staging/comedi/drivers/ni_daq_dio24.c b/drivers/staging/comedi/drivers/ni_daq_dio24.c
index c9c2858..49b824c 100644
--- a/drivers/staging/comedi/drivers/ni_daq_dio24.c
+++ b/drivers/staging/comedi/drivers/ni_daq_dio24.c
@@ -304,7 +304,7 @@
/*====================================================================*/
-static struct pcmcia_device_id dio24_cs_ids[] = {
+static const struct pcmcia_device_id dio24_cs_ids[] = {
/* N.B. These IDs should match those in dio24_boards */
PCMCIA_DEVICE_MANF_CARD(0x010b, 0x475c), /* daqcard-dio24 */
PCMCIA_DEVICE_NULL
diff --git a/drivers/staging/comedi/drivers/ni_labpc_cs.c b/drivers/staging/comedi/drivers/ni_labpc_cs.c
index 6facbc8..832a517 100644
--- a/drivers/staging/comedi/drivers/ni_labpc_cs.c
+++ b/drivers/staging/comedi/drivers/ni_labpc_cs.c
@@ -267,7 +267,7 @@
return 0;
} /* labpc_cs_resume */
-static struct pcmcia_device_id labpc_cs_ids[] = {
+static const struct pcmcia_device_id labpc_cs_ids[] = {
/* N.B. These IDs should match those in labpc_cs_boards (ni_labpc.c) */
PCMCIA_DEVICE_MANF_CARD(0x010b, 0x0103), /* daqcard-1200 */
PCMCIA_DEVICE_NULL
diff --git a/drivers/staging/comedi/drivers/ni_mio_common.c b/drivers/staging/comedi/drivers/ni_mio_common.c
index 986ef67..fd232bc 100644
--- a/drivers/staging/comedi/drivers/ni_mio_common.c
+++ b/drivers/staging/comedi/drivers/ni_mio_common.c
@@ -1627,7 +1627,7 @@
default:
mite_prep_dma(devpriv->ai_mite_chan, 16, 16);
break;
- };
+ }
/*start the MITE */
mite_dma_arm(devpriv->ai_mite_chan);
spin_unlock_irqrestore(&devpriv->mite_channel_lock, flags);
@@ -2156,7 +2156,7 @@
default:
/* multiplexed inputs */
break;
- };
+ }
return boardtype.ai_speed * num_channels;
}
@@ -5173,7 +5173,7 @@
devpriv->stc_writew(dev, devpriv->an_trig_etc_reg,
Analog_Trigger_Etc_Register);
break;
- };
+ }
devpriv->gpct_mode[chan] = 0;
devpriv->gpct_input_select[chan] = 0;
diff --git a/drivers/staging/comedi/drivers/ni_mio_cs.c b/drivers/staging/comedi/drivers/ni_mio_cs.c
index 4956327..53ec24bb 100644
--- a/drivers/staging/comedi/drivers/ni_mio_cs.c
+++ b/drivers/staging/comedi/drivers/ni_mio_cs.c
@@ -416,7 +416,7 @@
#ifdef MODULE
-static struct pcmcia_device_id ni_mio_cs_ids[] = {
+static const struct pcmcia_device_id ni_mio_cs_ids[] = {
PCMCIA_DEVICE_MANF_CARD(0x010b, 0x010d), /* DAQCard-ai-16xe-50 */
PCMCIA_DEVICE_MANF_CARD(0x010b, 0x010c), /* DAQCard-ai-16e-4 */
PCMCIA_DEVICE_MANF_CARD(0x010b, 0x02c4), /* DAQCard-6062E */
diff --git a/drivers/staging/comedi/drivers/ni_tio.c b/drivers/staging/comedi/drivers/ni_tio.c
index a9bb6b1..98f8789 100644
--- a/drivers/staging/comedi/drivers/ni_tio.c
+++ b/drivers/staging/comedi/drivers/ni_tio.c
@@ -1181,7 +1181,7 @@
break;
return -EINVAL;
break;
- };
+ }
counter_dev->regs[second_gate_reg] |= Gi_Second_Gate_Mode_Bit;
counter_dev->regs[second_gate_reg] &= ~Gi_Second_Gate_Select_Mask;
counter_dev->regs[second_gate_reg] |=
@@ -1209,7 +1209,7 @@
ni_m_series_second_gate_select =
selected_second_gate & selected_second_gate_mask;
break;
- };
+ }
counter_dev->regs[second_gate_reg] |= Gi_Second_Gate_Mode_Bit;
counter_dev->regs[second_gate_reg] &= ~Gi_Second_Gate_Select_Mask;
counter_dev->regs[second_gate_reg] |=
@@ -1674,7 +1674,7 @@
counter_dev->
regs[NITIO_Gi_LoadB_Reg(counter->counter_index)];
break;
- };
+ }
return 0;
}
EXPORT_SYMBOL_GPL(ni_tio_rinsn);
diff --git a/drivers/staging/comedi/drivers/pcl724.c b/drivers/staging/comedi/drivers/pcl724.c
index 396a058..61b075d 100644
--- a/drivers/staging/comedi/drivers/pcl724.c
+++ b/drivers/staging/comedi/drivers/pcl724.c
@@ -209,7 +209,7 @@
subdev_8255_cb,
(unsigned long)(dev->iobase +
SIZE_8255 * i));
- };
+ }
return 0;
}
diff --git a/drivers/staging/comedi/drivers/pcl818.c b/drivers/staging/comedi/drivers/pcl818.c
index e3eea09..8933e50 100644
--- a/drivers/staging/comedi/drivers/pcl818.c
+++ b/drivers/staging/comedi/drivers/pcl818.c
@@ -1662,7 +1662,7 @@
tmp = (CMOS_READ(RTC_INTR_FLAGS) & 0xF0); /* restart */
restore_flags(flags);
break;
- };
+ }
}
/*
diff --git a/drivers/staging/comedi/drivers/pcm3724.c b/drivers/staging/comedi/drivers/pcm3724.c
index 7fb3c27..f5c0bd1 100644
--- a/drivers/staging/comedi/drivers/pcm3724.c
+++ b/drivers/staging/comedi/drivers/pcm3724.c
@@ -301,7 +301,7 @@
subdev_8255_init(dev, dev->subdevices + i, subdev_8255_cb,
(unsigned long)(dev->iobase + SIZE_8255 * i));
((dev->subdevices) + i)->insn_config = subdev_3724_insn_config;
- };
+ }
return 0;
}
diff --git a/drivers/staging/comedi/drivers/quatech_daqp_cs.c b/drivers/staging/comedi/drivers/quatech_daqp_cs.c
index 82942e5..e0bb734 100644
--- a/drivers/staging/comedi/drivers/quatech_daqp_cs.c
+++ b/drivers/staging/comedi/drivers/quatech_daqp_cs.c
@@ -1087,7 +1087,7 @@
#ifdef MODULE
-static struct pcmcia_device_id daqp_cs_id_table[] = {
+static const struct pcmcia_device_id daqp_cs_id_table[] = {
PCMCIA_DEVICE_MANF_CARD(0x0137, 0x0027),
PCMCIA_DEVICE_NULL
};
diff --git a/drivers/staging/comedi/drivers/usbdux.c b/drivers/staging/comedi/drivers/usbdux.c
index e543e6c..1d09bfa 100644
--- a/drivers/staging/comedi/drivers/usbdux.c
+++ b/drivers/staging/comedi/drivers/usbdux.c
@@ -1530,7 +1530,7 @@
/* we always output at 1kHz just now all channels at once */
if (0) { /* (this_usbduxsub->high_speed) */
/*
- * in usb-2.0 only one conversion it tranmitted but with 8kHz/n
+ * in usb-2.0 only one conversion it transmitted but with 8kHz/n
*/
cmd->convert_src &= TRIG_TIMER;
} else {
diff --git a/drivers/staging/comedi/drivers/vmk80xx.c b/drivers/staging/comedi/drivers/vmk80xx.c
index 6479c38..3d13ca6e1 100644
--- a/drivers/staging/comedi/drivers/vmk80xx.c
+++ b/drivers/staging/comedi/drivers/vmk80xx.c
@@ -64,6 +64,8 @@
#include "../comedidev.h"
+#define BOARDNAME "vmk80xx"
+
MODULE_AUTHOR("Manuel Gebele <forensixs@gmx.de>");
MODULE_DESCRIPTION("Velleman USB Board Low-Level Driver");
MODULE_SUPPORTED_DEVICE("K8055/K8061 aka VM110/VM140");
@@ -305,8 +307,10 @@
static int vmk80xx_check_data_link(struct vmk80xx_usb *dev)
{
- unsigned int tx_pipe, rx_pipe;
- unsigned char tx[1], rx[2];
+ unsigned int tx_pipe;
+ unsigned int rx_pipe;
+ unsigned char tx[1];
+ unsigned char rx[2];
dbgvm("vmk80xx: %s\n", __func__);
@@ -315,9 +319,11 @@
tx[0] = VMK8061_CMD_RD_PWR_STAT;
- /* Check that IC6 (PIC16F871) is powered and
+ /*
+ * Check that IC6 (PIC16F871) is powered and
* running and the data link between IC3 and
- * IC6 is working properly */
+ * IC6 is working properly
+ */
usb_bulk_msg(dev->udev, tx_pipe, tx, 1, NULL, dev->ep_tx->bInterval);
usb_bulk_msg(dev->udev, rx_pipe, rx, 2, NULL, HZ * 10);
@@ -326,8 +332,10 @@
static void vmk80xx_read_eeprom(struct vmk80xx_usb *dev, int flag)
{
- unsigned int tx_pipe, rx_pipe;
- unsigned char tx[1], rx[64];
+ unsigned int tx_pipe;
+ unsigned int rx_pipe;
+ unsigned char tx[1];
+ unsigned char rx[64];
int cnt;
dbgvm("vmk80xx: %s\n", __func__);
@@ -337,8 +345,10 @@
tx[0] = VMK8061_CMD_RD_VERSION;
- /* Read the firmware version info of IC3 and
- * IC6 from the internal EEPROM of the IC */
+ /*
+ * Read the firmware version info of IC3 and
+ * IC6 from the internal EEPROM of the IC
+ */
usb_bulk_msg(dev->udev, tx_pipe, tx, 1, NULL, dev->ep_tx->bInterval);
usb_bulk_msg(dev->udev, rx_pipe, rx, 64, &cnt, HZ * 10);
@@ -388,7 +398,8 @@
static void vmk80xx_build_int_urb(struct urb *urb, int flag)
{
struct vmk80xx_usb *dev = urb->context;
- __u8 rx_addr, tx_addr;
+ __u8 rx_addr;
+ __u8 tx_addr;
unsigned int pipe;
unsigned char *buf;
size_t size;
@@ -418,8 +429,10 @@
static void vmk80xx_do_bulk_msg(struct vmk80xx_usb *dev)
{
- __u8 tx_addr, rx_addr;
- unsigned int tx_pipe, rx_pipe;
+ __u8 tx_addr;
+ __u8 rx_addr;
+ unsigned int tx_pipe;
+ unsigned int rx_pipe;
size_t size;
dbgvm("vmk80xx: %s\n", __func__);
@@ -432,8 +445,10 @@
tx_pipe = usb_sndbulkpipe(dev->udev, tx_addr);
rx_pipe = usb_rcvbulkpipe(dev->udev, rx_addr);
- /* The max packet size attributes of the K8061
- * input/output endpoints are identical */
+ /*
+ * The max packet size attributes of the K8061
+ * input/output endpoints are identical
+ */
size = le16_to_cpu(dev->ep_tx->wMaxPacketSize);
usb_bulk_msg(dev->udev, tx_pipe, dev->usb_tx_buf,
@@ -544,34 +559,40 @@
#define DIR_IN 1
#define DIR_OUT 2
-#define rudimentary_check(dir) \
-do { \
- if (!dev) \
- return -EFAULT; \
- if (!dev->probed) \
- return -ENODEV; \
- if (!dev->attached) \
- return -ENODEV; \
- if ((dir) & DIR_IN) { \
- if (test_bit(TRANS_IN_BUSY, &dev->flags)) \
- return -EBUSY; \
- } else { /* DIR_OUT */ \
- if (test_bit(TRANS_OUT_BUSY, &dev->flags)) \
- return -EBUSY; \
- } \
-} while (0)
+static int rudimentary_check(struct vmk80xx_usb *dev, int dir)
+{
+ if (!dev)
+ return -EFAULT;
+ if (!dev->probed)
+ return -ENODEV;
+ if (!dev->attached)
+ return -ENODEV;
+ if (dir & DIR_IN) {
+ if (test_bit(TRANS_IN_BUSY, &dev->flags))
+ return -EBUSY;
+ }
+ if (dir & DIR_OUT) {
+ if (test_bit(TRANS_OUT_BUSY, &dev->flags))
+ return -EBUSY;
+ }
+
+ return 0;
+}
static int vmk80xx_ai_rinsn(struct comedi_device *cdev,
struct comedi_subdevice *s,
struct comedi_insn *insn, unsigned int *data)
{
struct vmk80xx_usb *dev = cdev->private;
- int chan, reg[2];
+ int chan;
+ int reg[2];
int n;
dbgvm("vmk80xx: %s\n", __func__);
- rudimentary_check(DIR_IN);
+ n = rudimentary_check(dev, DIR_IN);
+ if (n)
+ return n;
down(&dev->limit_sem);
chan = CR_CHAN(insn->chanspec);
@@ -615,12 +636,16 @@
struct comedi_insn *insn, unsigned int *data)
{
struct vmk80xx_usb *dev = cdev->private;
- int chan, cmd, reg;
+ int chan;
+ int cmd;
+ int reg;
int n;
dbgvm("vmk80xx: %s\n", __func__);
- rudimentary_check(DIR_OUT);
+ n = rudimentary_check(dev, DIR_OUT);
+ if (n)
+ return n;
down(&dev->limit_sem);
chan = CR_CHAN(insn->chanspec);
@@ -657,12 +682,15 @@
struct comedi_insn *insn, unsigned int *data)
{
struct vmk80xx_usb *dev = cdev->private;
- int chan, reg;
+ int chan;
+ int reg;
int n;
dbgvm("vmk80xx: %s\n", __func__);
- rudimentary_check(DIR_IN);
+ n = rudimentary_check(dev, DIR_IN);
+ if (n)
+ return n;
down(&dev->limit_sem);
chan = CR_CHAN(insn->chanspec);
@@ -683,6 +711,50 @@
return n;
}
+static int vmk80xx_di_bits(struct comedi_device *cdev,
+ struct comedi_subdevice *s,
+ struct comedi_insn *insn, unsigned int *data)
+{
+ struct vmk80xx_usb *dev = cdev->private;
+ unsigned char *rx_buf;
+ int reg;
+ int retval;
+
+ dbgvm("vmk80xx: %s\n", __func__);
+
+ retval = rudimentary_check(dev, DIR_IN);
+ if (retval)
+ return retval;
+
+ down(&dev->limit_sem);
+
+ rx_buf = dev->usb_rx_buf;
+
+ if (dev->board.model == VMK8061_MODEL) {
+ reg = VMK8061_DI_REG;
+ dev->usb_tx_buf[0] = VMK8061_CMD_RD_DI;
+ } else {
+ reg = VMK8055_DI_REG;
+ }
+
+ retval = vmk80xx_read_packet(dev);
+
+ if (!retval) {
+ if (dev->board.model == VMK8055_MODEL)
+ data[1] = (((rx_buf[reg] >> 4) & 0x03) |
+ ((rx_buf[reg] << 2) & 0x04) |
+ ((rx_buf[reg] >> 3) & 0x18));
+ else
+ data[1] = rx_buf[reg];
+
+ retval = 2;
+ }
+
+ up(&dev->limit_sem);
+
+ return retval;
+}
+
static int vmk80xx_di_rinsn(struct comedi_device *cdev,
struct comedi_subdevice *s,
struct comedi_insn *insn, unsigned int *data)
@@ -690,12 +762,15 @@
struct vmk80xx_usb *dev = cdev->private;
int chan;
unsigned char *rx_buf;
- int reg, inp;
+ int reg;
+ int inp;
int n;
dbgvm("vmk80xx: %s\n", __func__);
- rudimentary_check(DIR_IN);
+ n = rudimentary_check(dev, DIR_IN);
+ if (n)
+ return n;
down(&dev->limit_sem);
chan = CR_CHAN(insn->chanspec);
@@ -705,9 +780,9 @@
if (dev->board.model == VMK8061_MODEL) {
reg = VMK8061_DI_REG;
dev->usb_tx_buf[0] = VMK8061_CMD_RD_DI;
- } else
+ } else {
reg = VMK8055_DI_REG;
-
+ }
for (n = 0; n < insn->n; n++) {
if (vmk80xx_read_packet(dev))
break;
@@ -719,7 +794,7 @@
else
inp = rx_buf[reg];
- data[n] = ((inp & (1 << chan)) > 0);
+ data[n] = (inp >> chan) & 1;
}
up(&dev->limit_sem);
@@ -731,16 +806,18 @@
struct comedi_subdevice *s,
struct comedi_insn *insn, unsigned int *data)
{
-
struct vmk80xx_usb *dev = cdev->private;
int chan;
unsigned char *tx_buf;
- int reg, cmd;
+ int reg;
+ int cmd;
int n;
dbgvm("vmk80xx: %s\n", __func__);
- rudimentary_check(DIR_OUT);
+ n = rudimentary_check(dev, DIR_OUT);
+ if (n)
+ return n;
down(&dev->limit_sem);
chan = CR_CHAN(insn->chanspec);
@@ -755,21 +832,17 @@
tx_buf[reg] |= (1 << chan);
else
tx_buf[reg] ^= (1 << chan);
-
- goto write_packet;
+ } else { /* VMK8061_MODEL */
+ reg = VMK8061_DO_REG;
+ if (data[n] == 1) {
+ cmd = VMK8061_CMD_SET_DO;
+ tx_buf[reg] = 1 << chan;
+ } else {
+ cmd = VMK8061_CMD_CLR_DO;
+ tx_buf[reg] = 0xff - (1 << chan);
+ }
}
- /* VMK8061_MODEL */
- reg = VMK8061_DO_REG;
- if (data[n] == 1) {
- cmd = VMK8061_CMD_SET_DO;
- tx_buf[reg] = 1 << chan;
- } else {
- cmd = VMK8061_CMD_CLR_DO;
- tx_buf[reg] = 0xff - (1 << chan);
- }
-
-write_packet:
if (vmk80xx_write_packet(dev, cmd))
break;
}
@@ -784,18 +857,20 @@
struct comedi_insn *insn, unsigned int *data)
{
struct vmk80xx_usb *dev = cdev->private;
- int chan, reg, mask;
+ int chan;
+ int reg;
int n;
dbgvm("vmk80xx: %s\n", __func__);
- rudimentary_check(DIR_IN);
+ n = rudimentary_check(dev, DIR_IN);
+ if (n)
+ return n;
down(&dev->limit_sem);
chan = CR_CHAN(insn->chanspec);
reg = VMK8061_DO_REG;
- mask = 1 << chan;
dev->usb_tx_buf[0] = VMK8061_CMD_RD_DO;
@@ -803,7 +878,7 @@
if (vmk80xx_read_packet(dev))
break;
- data[n] = (dev->usb_rx_buf[reg] & mask) >> chan;
+ data[n] = (dev->usb_rx_buf[reg] >> chan) & 1;
}
up(&dev->limit_sem);
@@ -811,17 +886,87 @@
return n;
}
+static int vmk80xx_do_bits(struct comedi_device *cdev,
+ struct comedi_subdevice *s,
+ struct comedi_insn *insn, unsigned int *data)
+{
+ struct vmk80xx_usb *dev = cdev->private;
+ unsigned char *rx_buf, *tx_buf;
+ int dir, reg, cmd;
+ int retval;
+
+ dbgvm("vmk80xx: %s\n", __func__);
+
+ dir = 0;
+
+ if (data[0])
+ dir |= DIR_OUT;
+
+ if (dev->board.model == VMK8061_MODEL)
+ dir |= DIR_IN;
+
+ retval = rudimentary_check(dev, dir);
+ if (retval)
+ return retval;
+
+ down(&dev->limit_sem);
+
+ rx_buf = dev->usb_rx_buf;
+ tx_buf = dev->usb_tx_buf;
+
+ if (data[0]) {
+ if (dev->board.model == VMK8055_MODEL) {
+ reg = VMK8055_DO_REG;
+ cmd = VMK8055_CMD_WRT_AD;
+ } else { /* VMK8061_MODEL */
+ reg = VMK8061_DO_REG;
+ cmd = VMK8061_CMD_DO;
+ }
+
+ tx_buf[reg] &= ~data[0];
+ tx_buf[reg] |= (data[0] & data[1]);
+
+ retval = vmk80xx_write_packet(dev, cmd);
+
+ if (retval)
+ goto out;
+ }
+
+ if (dev->board.model == VMK8061_MODEL) {
+ reg = VMK8061_DO_REG;
+ tx_buf[0] = VMK8061_CMD_RD_DO;
+
+ retval = vmk80xx_read_packet(dev);
+
+ if (!retval) {
+ data[1] = rx_buf[reg];
+ retval = 2;
+ }
+ } else {
+ data[1] = tx_buf[reg];
+ retval = 2;
+ }
+
+out:
+ up(&dev->limit_sem);
+
+ return retval;
+}
+
static int vmk80xx_cnt_rinsn(struct comedi_device *cdev,
struct comedi_subdevice *s,
struct comedi_insn *insn, unsigned int *data)
{
struct vmk80xx_usb *dev = cdev->private;
- int chan, reg[2];
+ int chan;
+ int reg[2];
int n;
dbgvm("vmk80xx: %s\n", __func__);
- rudimentary_check(DIR_IN);
+ n = rudimentary_check(dev, DIR_IN);
+ if (n)
+ return n;
down(&dev->limit_sem);
chan = CR_CHAN(insn->chanspec);
@@ -844,14 +989,11 @@
if (vmk80xx_read_packet(dev))
break;
- if (dev->board.model == VMK8055_MODEL) {
+ if (dev->board.model == VMK8055_MODEL)
data[n] = dev->usb_rx_buf[reg[0]];
- continue;
- }
-
- /* VMK8061_MODEL */
- data[n] = dev->usb_rx_buf[reg[0] * (chan + 1) + 1]
- + 256 * dev->usb_rx_buf[reg[1] * 2 + 2];
+ else /* VMK8061_MODEL */
+ data[n] = dev->usb_rx_buf[reg[0] * (chan + 1) + 1]
+ + 256 * dev->usb_rx_buf[reg[1] * 2 + 2];
}
up(&dev->limit_sem);
@@ -865,12 +1007,16 @@
{
struct vmk80xx_usb *dev = cdev->private;
unsigned int insn_cmd;
- int chan, cmd, reg;
+ int chan;
+ int cmd;
+ int reg;
int n;
dbgvm("vmk80xx: %s\n", __func__);
- rudimentary_check(DIR_OUT);
+ n = rudimentary_check(dev, DIR_OUT);
+ if (n)
+ return n;
down(&dev->limit_sem);
@@ -890,8 +1036,9 @@
}
dev->usb_tx_buf[reg] = 0x00;
- } else
+ } else {
cmd = VMK8061_CMD_RST_CNT;
+ }
for (n = 0; n < insn->n; n++)
if (vmk80xx_write_packet(dev, cmd))
@@ -907,13 +1054,17 @@
struct comedi_insn *insn, unsigned int *data)
{
struct vmk80xx_usb *dev = cdev->private;
- unsigned long debtime, val;
- int chan, cmd;
+ unsigned long debtime;
+ unsigned long val;
+ int chan;
+ int cmd;
int n;
dbgvm("vmk80xx: %s\n", __func__);
- rudimentary_check(DIR_OUT);
+ n = rudimentary_check(dev, DIR_OUT);
+ if (n)
+ return n;
down(&dev->limit_sem);
chan = CR_CHAN(insn->chanspec);
@@ -957,7 +1108,9 @@
dbgvm("vmk80xx: %s\n", __func__);
- rudimentary_check(DIR_IN);
+ n = rudimentary_check(dev, DIR_IN);
+ if (n)
+ return n;
down(&dev->limit_sem);
@@ -984,12 +1137,15 @@
{
struct vmk80xx_usb *dev = cdev->private;
unsigned char *tx_buf;
- int reg[2], cmd;
+ int reg[2];
+ int cmd;
int n;
dbgvm("vmk80xx: %s\n", __func__);
- rudimentary_check(DIR_OUT);
+ n = rudimentary_check(dev, DIR_OUT);
+ if (n)
+ return n;
down(&dev->limit_sem);
@@ -1026,8 +1182,8 @@
return n;
}
-static int
-vmk80xx_attach(struct comedi_device *cdev, struct comedi_devconfig *it)
+static int vmk80xx_attach(struct comedi_device *cdev,
+ struct comedi_devconfig *it)
{
int i;
struct vmk80xx_usb *dev;
@@ -1094,16 +1250,18 @@
s->type = COMEDI_SUBD_DI;
s->subdev_flags = SDF_READABLE | SDF_GROUND;
s->n_chan = dev->board.di_chans;
- s->maxdata = (1 << dev->board.di_bits) - 1;
+ s->maxdata = 1;
s->insn_read = vmk80xx_di_rinsn;
+ s->insn_bits = vmk80xx_di_bits;
/* Digital output subdevice */
s = cdev->subdevices + VMK80XX_SUBD_DO;
s->type = COMEDI_SUBD_DO;
s->subdev_flags = SDF_WRITEABLE | SDF_GROUND;
s->n_chan = dev->board.do_chans;
- s->maxdata = (1 << dev->board.do_bits) - 1;
+ s->maxdata = 1;
s->insn_write = vmk80xx_do_winsn;
+ s->insn_bits = vmk80xx_do_bits;
if (dev->board.model == VMK8061_MODEL) {
s->subdev_flags |= SDF_READABLE;
@@ -1179,8 +1337,8 @@
return 0;
}
-static int
-vmk80xx_probe(struct usb_interface *intf, const struct usb_device_id *id)
+static int vmk80xx_probe(struct usb_interface *intf,
+ const struct usb_device_id *id)
{
int i;
struct vmk80xx_usb *dev;
@@ -1309,8 +1467,9 @@
vmk80xx_read_eeprom(dev, IC6_VERSION);
printk(KERN_INFO "comedi#: vmk80xx: %s\n",
dev->fw.ic6_vers);
- } else
+ } else {
dbgcm("comedi#: vmk80xx: no conn. to CPU\n");
+ }
}
if (dev->board.model == VMK8055_MODEL)
@@ -1323,6 +1482,8 @@
mutex_unlock(&glb_mutex);
+ comedi_usb_auto_config(dev->udev, BOARDNAME);
+
return 0;
error:
mutex_unlock(&glb_mutex);
@@ -1339,6 +1500,8 @@
if (!dev)
return;
+ comedi_usb_auto_unconfig(dev->udev);
+
mutex_lock(&glb_mutex);
down(&dev->limit_sem);
@@ -1376,10 +1539,16 @@
static int __init vmk80xx_init(void)
{
+ int retval;
+
printk(KERN_INFO "vmk80xx: version 0.8.01 "
"Manuel Gebele <forensixs@gmx.de>\n");
- usb_register(&vmk80xx_driver);
- return comedi_driver_register(&driver_vmk80xx);
+
+ retval = comedi_driver_register(&driver_vmk80xx);
+ if (retval < 0)
+ return retval;
+
+ return usb_register(&vmk80xx_driver);
}
static void __exit vmk80xx_exit(void)
diff --git a/drivers/staging/cptm1217/clearpad_tm1217.c b/drivers/staging/cptm1217/clearpad_tm1217.c
index 0fe713e..5456f82 100644
--- a/drivers/staging/cptm1217/clearpad_tm1217.c
+++ b/drivers/staging/cptm1217/clearpad_tm1217.c
@@ -462,8 +462,8 @@
if (input_dev == NULL) {
dev_err(ts->dev,
"cp_tm1217:Input Device Struct alloc failed\n");
- kfree(ts);
- return -ENOMEM;
+ retval = -ENOMEM;
+ goto fail;
}
input_info = &ts->cp_input_info[i];
snprintf(input_info->name, sizeof(input_info->name),
@@ -486,6 +486,7 @@
dev_err(ts->dev,
"Input dev registration failed for %s\n",
input_dev->name);
+ input_free_device(input_dev);
goto fail;
}
input_info->input = input_dev;
diff --git a/drivers/staging/crystalhd/bc_dts_types.h b/drivers/staging/crystalhd/bc_dts_types.h
index 6fd8089..d2131e7 100644
--- a/drivers/staging/crystalhd/bc_dts_types.h
+++ b/drivers/staging/crystalhd/bc_dts_types.h
@@ -65,7 +65,6 @@
#else
/* For Kernel usage.. */
-typedef bool bc_bool_t;
#endif
#else
diff --git a/drivers/staging/crystalhd/crystalhd_misc.c b/drivers/staging/crystalhd/crystalhd_misc.c
index 2c5138e..5fa0c6e 100644
--- a/drivers/staging/crystalhd/crystalhd_misc.c
+++ b/drivers/staging/crystalhd/crystalhd_misc.c
@@ -311,7 +311,7 @@
rc = -EINVAL;
sts = BC_STS_INV_ARG;
BCMLOG_ERR("Invalid len:%d\n", len);
- };
+ }
if (rc && (sts == BC_STS_SUCCESS))
sts = BC_STS_ERROR;
@@ -356,7 +356,7 @@
rc = -EINVAL;
sts = BC_STS_INV_ARG;
BCMLOG_ERR("Invalid len:%d\n", len);
- };
+ }
if (rc && (sts == BC_STS_SUCCESS))
sts = BC_STS_ERROR;
diff --git a/drivers/staging/cx25821/cx25821-video.c b/drivers/staging/cx25821/cx25821-video.c
index ab05392..7a0304a 100644
--- a/drivers/staging/cx25821/cx25821-video.c
+++ b/drivers/staging/cx25821/cx25821-video.c
@@ -832,6 +832,7 @@
if (NULL == dev) {
mutex_unlock(&cx25821_devlist_mutex);
+ kfree(fh);
return -ENODEV;
}
@@ -1573,7 +1574,7 @@
break;
default:
/* nothing */ ;
- };
+ }
switch (ctl->id) {
case V4L2_CID_BRIGHTNESS:
diff --git a/drivers/staging/easycap/easycap_main.c b/drivers/staging/easycap/easycap_main.c
index cee3252..62e07f6 100644
--- a/drivers/staging/easycap/easycap_main.c
+++ b/drivers/staging/easycap/easycap_main.c
@@ -201,9 +201,9 @@
static int reset(struct easycap *peasycap)
{
struct easycap_standard const *peasycap_standard;
- int i, rc, input, rate;
+ int fmtidx, input, rate;
bool ntsc, other;
- int fmtidx;
+ int rc;
if (!peasycap) {
SAY("ERROR: peasycap is NULL\n");
@@ -226,33 +226,27 @@
JOM(8, "peasycap->ntsc=%d\n", peasycap->ntsc);
rate = ready_saa(peasycap->pusb_device);
- if (0 > rate) {
+ if (rate < 0) {
JOM(8, "not ready to capture after %i ms ...\n", PATIENCE);
- if (peasycap->ntsc) {
- JOM(8, "... trying PAL ...\n"); ntsc = false;
- } else {
- JOM(8, "... trying NTSC ...\n"); ntsc = true;
- }
- rc = setup_stk(peasycap->pusb_device, ntsc);
- if (0 == rc)
- JOM(4, "setup_stk() OK\n");
- else {
- SAM("ERROR: setup_stk() rc = %i\n", rc);
- return -EFAULT;
- }
- rc = setup_saa(peasycap->pusb_device, ntsc);
- if (0 == rc)
- JOM(4, "setup_saa() OK\n");
- else {
- SAM("ERROR: setup_saa() rc = %i\n", rc);
- return -EFAULT;
- }
- rate = ready_saa(peasycap->pusb_device);
- if (0 > rate) {
- JOM(8, "not ready to capture after %i ms ...\n", PATIENCE);
- JOM(8, "... saa register 0x1F has 0x%02X\n",
+ ntsc = !peasycap->ntsc;
+ JOM(8, "... trying %s ..\n", ntsc ? "NTSC" : "PAL");
+ rc = setup_stk(peasycap->pusb_device, ntsc);
+ if (rc) {
+ SAM("ERROR: setup_stk() rc = %i\n", rc);
+ return -EFAULT;
+ }
+ rc = setup_saa(peasycap->pusb_device, ntsc);
+ if (rc) {
+ SAM("ERROR: setup_saa() rc = %i\n", rc);
+ return -EFAULT;
+ }
+
+ rate = ready_saa(peasycap->pusb_device);
+ if (rate < 0) {
+ JOM(8, "not ready to capture after %i ms\n", PATIENCE);
+ JOM(8, "... saa register 0x1F has 0x%02X\n",
read_saa(peasycap->pusb_device, 0x1F));
- ntsc = peasycap->ntsc;
+ ntsc = peasycap->ntsc;
} else {
JOM(8, "... success at second try: %i=rate\n", rate);
ntsc = (0 < (rate/2)) ? true : false ;
@@ -266,22 +260,17 @@
/*---------------------------------------------------------------------------*/
rc = setup_stk(peasycap->pusb_device, ntsc);
- if (0 == rc)
- JOM(4, "setup_stk() OK\n");
- else {
+ if (rc) {
SAM("ERROR: setup_stk() rc = %i\n", rc);
return -EFAULT;
}
rc = setup_saa(peasycap->pusb_device, ntsc);
- if (0 == rc)
- JOM(4, "setup_saa() OK\n");
- else {
+ if (rc) {
SAM("ERROR: setup_saa() rc = %i\n", rc);
return -EFAULT;
}
- for (i = 0; i < 180; i++)
- peasycap->merit[i] = 0;
+ memset(peasycap->merit, 0, sizeof(peasycap->merit));
peasycap->video_eof = 0;
peasycap->audio_eof = 0;
@@ -2986,26 +2975,18 @@
* TIMES, ONCE FOR EACH OF THE THREE INTERFACES. BEWARE.
*/
/*---------------------------------------------------------------------------*/
-static int easycap_usb_probe(struct usb_interface *pusb_interface,
- const struct usb_device_id *pusb_device_id)
+static int easycap_usb_probe(struct usb_interface *intf,
+ const struct usb_device_id *id)
{
- struct usb_device *pusb_device;
- struct usb_host_interface *pusb_host_interface;
- struct usb_endpoint_descriptor *pepd;
- struct usb_interface_descriptor *pusb_interface_descriptor;
+ struct usb_device *usbdev;
+ struct usb_host_interface *alt;
+ struct usb_endpoint_descriptor *ep;
+ struct usb_interface_descriptor *interface;
struct urb *purb;
struct easycap *peasycap;
int ndong;
struct data_urb *pdata_urb;
- size_t wMaxPacketSize;
- int ISOCwMaxPacketSize;
- int BULKwMaxPacketSize;
- int INTwMaxPacketSize;
- int CTRLwMaxPacketSize;
- u8 bEndpointAddress;
- u8 ISOCbEndpointAddress;
- u8 INTbEndpointAddress;
- int isin, i, j, k, m, rc;
+ int i, j, k, m, rc;
u8 bInterfaceNumber;
u8 bInterfaceClass;
u8 bInterfaceSubClass;
@@ -3021,23 +3002,17 @@
struct inputset *inputset;
struct v4l2_device *pv4l2_device;
-/*---------------------------------------------------------------------------*/
-/*
- * GET POINTER TO STRUCTURE usb_device
- */
-/*---------------------------------------------------------------------------*/
- pusb_device = interface_to_usbdev(pusb_interface);
+ usbdev = interface_to_usbdev(intf);
- JOT(4, "bNumConfigurations=%i\n", pusb_device->descriptor.bNumConfigurations);
/*---------------------------------------------------------------------------*/
- pusb_host_interface = pusb_interface->cur_altsetting;
- if (!pusb_host_interface) {
- SAY("ERROR: pusb_host_interface is NULL\n");
+ alt = usb_altnum_to_altsetting(intf, 0);
+ if (!alt) {
+ SAY("ERROR: usb_host_interface not found\n");
return -EFAULT;
}
- pusb_interface_descriptor = &(pusb_host_interface->desc);
- if (!pusb_interface_descriptor) {
- SAY("ERROR: pusb_interface_descriptor is NULL\n");
+ interface = &alt->desc;
+ if (!interface) {
+ SAY("ERROR: intf_descriptor is NULL\n");
return -EFAULT;
}
/*---------------------------------------------------------------------------*/
@@ -3045,16 +3020,15 @@
* GET PROPERTIES OF PROBED INTERFACE
*/
/*---------------------------------------------------------------------------*/
- bInterfaceNumber = pusb_interface_descriptor->bInterfaceNumber;
- bInterfaceClass = pusb_interface_descriptor->bInterfaceClass;
- bInterfaceSubClass = pusb_interface_descriptor->bInterfaceSubClass;
+ bInterfaceNumber = interface->bInterfaceNumber;
+ bInterfaceClass = interface->bInterfaceClass;
+ bInterfaceSubClass = interface->bInterfaceSubClass;
JOT(4, "intf[%i]: num_altsetting=%i\n",
- bInterfaceNumber, pusb_interface->num_altsetting);
+ bInterfaceNumber, intf->num_altsetting);
JOT(4, "intf[%i]: cur_altsetting - altsetting=%li\n",
bInterfaceNumber,
- (long int)(pusb_interface->cur_altsetting -
- pusb_interface->altsetting));
+ (long int)(intf->cur_altsetting - intf->altsetting));
JOT(4, "intf[%i]: bInterfaceClass=0x%02X bInterfaceSubClass=0x%02X\n",
bInterfaceNumber, bInterfaceClass, bInterfaceSubClass);
/*---------------------------------------------------------------------------*/
@@ -3140,8 +3114,8 @@
* ... AND FURTHER INITIALIZE THE STRUCTURE
*/
/*---------------------------------------------------------------------------*/
- peasycap->pusb_device = pusb_device;
- peasycap->pusb_interface = pusb_interface;
+ peasycap->pusb_device = usbdev;
+ peasycap->pusb_interface = intf;
peasycap->ilk = 0;
peasycap->microphone = false;
@@ -3275,7 +3249,7 @@
*/
/*---------------------------------------------------------------------------*/
for (ndong = 0; ndong < DONGLE_MANY; ndong++) {
- if (pusb_device == easycapdc60_dongle[ndong].peasycap->
+ if (usbdev == easycapdc60_dongle[ndong].peasycap->
pusb_device) {
peasycap = easycapdc60_dongle[ndong].peasycap;
JOT(8, "intf[%i]: dongle[%i].peasycap\n",
@@ -3302,7 +3276,7 @@
*/
/*---------------------------------------------------------------------------*/
if (memcmp(&peasycap->telltale[0], TELLTALE, strlen(TELLTALE))) {
- pv4l2_device = usb_get_intfdata(pusb_interface);
+ pv4l2_device = usb_get_intfdata(intf);
if (!pv4l2_device) {
SAY("ERROR: pv4l2_device is NULL\n");
return -ENODEV;
@@ -3351,220 +3325,155 @@
/*---------------------------------------------------------------------------*/
isokalt = 0;
- for (i = 0; i < pusb_interface->num_altsetting; i++) {
- pusb_host_interface = &(pusb_interface->altsetting[i]);
- if (!pusb_host_interface) {
- SAM("ERROR: pusb_host_interface is NULL\n");
+ for (i = 0; i < intf->num_altsetting; i++) {
+ alt = usb_altnum_to_altsetting(intf, i);
+ if (!alt) {
+ SAM("ERROR: alt is NULL\n");
return -EFAULT;
}
- pusb_interface_descriptor = &(pusb_host_interface->desc);
- if (!pusb_interface_descriptor) {
- SAM("ERROR: pusb_interface_descriptor is NULL\n");
+ interface = &alt->desc;
+ if (!interface) {
+ SAM("ERROR: intf_descriptor is NULL\n");
return -EFAULT;
}
- JOM(4, "intf[%i]alt[%i]: desc.bDescriptorType=0x%02X\n",
- bInterfaceNumber, i, pusb_interface_descriptor->bDescriptorType);
- JOM(4, "intf[%i]alt[%i]: desc.bInterfaceNumber=0x%02X\n",
- bInterfaceNumber, i, pusb_interface_descriptor->bInterfaceNumber);
- JOM(4, "intf[%i]alt[%i]: desc.bAlternateSetting=0x%02X\n",
- bInterfaceNumber, i, pusb_interface_descriptor->bAlternateSetting);
- JOM(4, "intf[%i]alt[%i]: desc.bNumEndpoints=0x%02X\n",
- bInterfaceNumber, i, pusb_interface_descriptor->bNumEndpoints);
- JOM(4, "intf[%i]alt[%i]: desc.bInterfaceClass=0x%02X\n",
- bInterfaceNumber, i, pusb_interface_descriptor->bInterfaceClass);
- JOM(4, "intf[%i]alt[%i]: desc.bInterfaceSubClass=0x%02X\n",
- bInterfaceNumber, i, pusb_interface_descriptor->bInterfaceSubClass);
- JOM(4, "intf[%i]alt[%i]: desc.bInterfaceProtocol=0x%02X\n",
- bInterfaceNumber, i, pusb_interface_descriptor->bInterfaceProtocol);
- JOM(4, "intf[%i]alt[%i]: desc.iInterface=0x%02X\n",
- bInterfaceNumber, i, pusb_interface_descriptor->iInterface);
-
- ISOCwMaxPacketSize = -1;
- BULKwMaxPacketSize = -1;
- INTwMaxPacketSize = -1;
- CTRLwMaxPacketSize = -1;
- ISOCbEndpointAddress = 0;
- INTbEndpointAddress = 0;
-
- if (0 == pusb_interface_descriptor->bNumEndpoints)
+ if (0 == interface->bNumEndpoints)
JOM(4, "intf[%i]alt[%i] has no endpoints\n",
bInterfaceNumber, i);
/*---------------------------------------------------------------------------*/
- for (j = 0; j < pusb_interface_descriptor->bNumEndpoints; j++) {
- pepd = &(pusb_host_interface->endpoint[j].desc);
- if (!pepd) {
- SAM("ERROR: pepd is NULL.\n");
+ for (j = 0; j < interface->bNumEndpoints; j++) {
+ ep = &alt->endpoint[j].desc;
+ if (!ep) {
+ SAM("ERROR: ep is NULL.\n");
SAM("...... skipping\n");
continue;
}
- wMaxPacketSize = le16_to_cpu(pepd->wMaxPacketSize);
- bEndpointAddress = pepd->bEndpointAddress;
- JOM(4, "intf[%i]alt[%i]end[%i]: bEndpointAddress=0x%X\n",
- bInterfaceNumber, i, j,
- pepd->bEndpointAddress);
- JOM(4, "intf[%i]alt[%i]end[%i]: bmAttributes=0x%X\n",
- bInterfaceNumber, i, j,
- pepd->bmAttributes);
- JOM(4, "intf[%i]alt[%i]end[%i]: wMaxPacketSize=%i\n",
- bInterfaceNumber, i, j,
- pepd->wMaxPacketSize);
- JOM(4, "intf[%i]alt[%i]end[%i]: bInterval=%i\n",
- bInterfaceNumber, i, j,
- pepd->bInterval);
-
- if (pepd->bEndpointAddress & USB_DIR_IN) {
- JOM(4, "intf[%i]alt[%i]end[%i] is an IN endpoint\n",
- bInterfaceNumber, i, j);
- isin = 1;
- } else {
- JOM(4, "intf[%i]alt[%i]end[%i] is an OUT endpoint\n",
- bInterfaceNumber, i, j);
- SAM("ERROR: OUT endpoint unexpected\n");
- SAM("...... continuing\n");
- isin = 0;
+ if (!usb_endpoint_is_isoc_in(ep)) {
+ JOM(4, "intf[%i]alt[%i]end[%i] is a %d endpoint\n",
+ bInterfaceNumber,
+ i, j, ep->bmAttributes);
+ if (usb_endpoint_dir_out(ep)) {
+ SAM("ERROR: OUT endpoint unexpected\n");
+ SAM("...... continuing\n");
+ }
+ continue;
}
- if ((pepd->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) ==
- USB_ENDPOINT_XFER_ISOC) {
- JOM(4, "intf[%i]alt[%i]end[%i] is an ISOC endpoint\n",
- bInterfaceNumber, i, j);
- if (isin) {
- switch (bInterfaceClass) {
- case USB_CLASS_VIDEO:
- case USB_CLASS_VENDOR_SPEC: {
- if (!peasycap) {
- SAM("MISTAKE: "
- "peasycap is NULL\n");
- return -EFAULT;
- }
- if (pepd->wMaxPacketSize) {
- if (8 > isokalt) {
- okalt[isokalt] = i;
- JOM(4,
- "%i=okalt[%i]\n",
- okalt[isokalt],
- isokalt);
- okepn[isokalt] =
- pepd->
- bEndpointAddress &
- 0x0F;
- JOM(4,
- "%i=okepn[%i]\n",
- okepn[isokalt],
- isokalt);
- okmps[isokalt] =
- le16_to_cpu(pepd->
- wMaxPacketSize);
- JOM(4,
- "%i=okmps[%i]\n",
- okmps[isokalt],
- isokalt);
- isokalt++;
- }
- } else {
- if (-1 == peasycap->
- video_altsetting_off) {
- peasycap->
- video_altsetting_off =
- i;
- JOM(4, "%i=video_"
- "altsetting_off "
- "<====\n",
- peasycap->
- video_altsetting_off);
- } else {
- SAM("ERROR: peasycap"
- "->video_altsetting_"
- "off already set\n");
- SAM("...... "
- "continuing with "
- "%i=peasycap->video_"
- "altsetting_off\n",
- peasycap->
- video_altsetting_off);
- }
- }
- break;
+ switch (bInterfaceClass) {
+ case USB_CLASS_VIDEO:
+ case USB_CLASS_VENDOR_SPEC: {
+ if (ep->wMaxPacketSize) {
+ if (8 > isokalt) {
+ okalt[isokalt] = i;
+ JOM(4,
+ "%i=okalt[%i]\n",
+ okalt[isokalt],
+ isokalt);
+ okepn[isokalt] =
+ ep->
+ bEndpointAddress &
+ 0x0F;
+ JOM(4,
+ "%i=okepn[%i]\n",
+ okepn[isokalt],
+ isokalt);
+ okmps[isokalt] =
+ le16_to_cpu(ep->
+ wMaxPacketSize);
+ JOM(4,
+ "%i=okmps[%i]\n",
+ okmps[isokalt],
+ isokalt);
+ isokalt++;
}
- case USB_CLASS_AUDIO: {
- if (bInterfaceSubClass !=
- USB_SUBCLASS_AUDIOSTREAMING)
- break;
- if (!peasycap) {
- SAM("MISTAKE: "
- "peasycap is NULL\n");
- return -EFAULT;
- }
- if (pepd->wMaxPacketSize) {
- if (8 > isokalt) {
- okalt[isokalt] = i ;
- JOM(4,
- "%i=okalt[%i]\n",
- okalt[isokalt],
- isokalt);
- okepn[isokalt] =
- pepd->
- bEndpointAddress &
- 0x0F;
- JOM(4,
- "%i=okepn[%i]\n",
- okepn[isokalt],
- isokalt);
- okmps[isokalt] =
- le16_to_cpu(pepd->
- wMaxPacketSize);
- JOM(4,
- "%i=okmps[%i]\n",
- okmps[isokalt],
- isokalt);
- isokalt++;
- }
- } else {
- if (-1 == peasycap->
- audio_altsetting_off) {
- peasycap->
- audio_altsetting_off =
- i;
- JOM(4, "%i=audio_"
- "altsetting_off "
- "<====\n",
- peasycap->
- audio_altsetting_off);
- } else {
- SAM("ERROR: peasycap"
- "->audio_altsetting_"
- "off already set\n");
- SAM("...... "
- "continuing with "
- "%i=peasycap->"
- "audio_altsetting_"
- "off\n",
- peasycap->
- audio_altsetting_off);
- }
- }
- break;
- }
- default:
- break;
+ } else {
+ if (-1 == peasycap->
+ video_altsetting_off) {
+ peasycap->
+ video_altsetting_off =
+ i;
+ JOM(4, "%i=video_"
+ "altsetting_off "
+ "<====\n",
+ peasycap->
+ video_altsetting_off);
+ } else {
+ SAM("ERROR: peasycap"
+ "->video_altsetting_"
+ "off already set\n");
+ SAM("...... "
+ "continuing with "
+ "%i=peasycap->video_"
+ "altsetting_off\n",
+ peasycap->
+ video_altsetting_off);
}
}
- } else if ((pepd->bmAttributes &
- USB_ENDPOINT_XFERTYPE_MASK) ==
- USB_ENDPOINT_XFER_BULK) {
- JOM(4, "intf[%i]alt[%i]end[%i] is a BULK endpoint\n",
- bInterfaceNumber, i, j);
- } else if ((pepd->bmAttributes &
- USB_ENDPOINT_XFERTYPE_MASK) ==
- USB_ENDPOINT_XFER_INT) {
- JOM(4, "intf[%i]alt[%i]end[%i] is an INT endpoint\n",
- bInterfaceNumber, i, j);
- } else {
- JOM(4, "intf[%i]alt[%i]end[%i] is a CTRL endpoint\n",
- bInterfaceNumber, i, j);
+ break;
}
- if (0 == pepd->wMaxPacketSize) {
+ case USB_CLASS_AUDIO: {
+ if (bInterfaceSubClass !=
+ USB_SUBCLASS_AUDIOSTREAMING)
+ break;
+ if (!peasycap) {
+ SAM("MISTAKE: "
+ "peasycap is NULL\n");
+ return -EFAULT;
+ }
+ if (ep->wMaxPacketSize) {
+ if (8 > isokalt) {
+ okalt[isokalt] = i ;
+ JOM(4,
+ "%i=okalt[%i]\n",
+ okalt[isokalt],
+ isokalt);
+ okepn[isokalt] =
+ ep->
+ bEndpointAddress &
+ 0x0F;
+ JOM(4,
+ "%i=okepn[%i]\n",
+ okepn[isokalt],
+ isokalt);
+ okmps[isokalt] =
+ le16_to_cpu(ep->
+ wMaxPacketSize);
+ JOM(4,
+ "%i=okmps[%i]\n",
+ okmps[isokalt],
+ isokalt);
+ isokalt++;
+ }
+ } else {
+ if (-1 == peasycap->
+ audio_altsetting_off) {
+ peasycap->
+ audio_altsetting_off =
+ i;
+ JOM(4, "%i=audio_"
+ "altsetting_off "
+ "<====\n",
+ peasycap->
+ audio_altsetting_off);
+ } else {
+ SAM("ERROR: peasycap"
+ "->audio_altsetting_"
+ "off already set\n");
+ SAM("...... "
+ "continuing with "
+ "%i=peasycap->"
+ "audio_altsetting_"
+ "off\n",
+ peasycap->
+ audio_altsetting_off);
+ }
+ }
+ break;
+ }
+ default:
+ break;
+ }
+ if (0 == ep->wMaxPacketSize) {
JOM(4, "intf[%i]alt[%i]end[%i] "
"has zero packet size\n",
bInterfaceNumber, i, j);
@@ -3577,7 +3486,7 @@
*/
/*---------------------------------------------------------------------------*/
JOM(4, "initialization begins for interface %i\n",
- pusb_interface_descriptor->bInterfaceNumber);
+ interface->bInterfaceNumber);
switch (bInterfaceNumber) {
/*---------------------------------------------------------------------------*/
/*
@@ -3844,7 +3753,7 @@
* SAVE POINTER peasycap IN THIS INTERFACE.
*/
/*--------------------------------------------------------------------------*/
- usb_set_intfdata(pusb_interface, peasycap);
+ usb_set_intfdata(intf, peasycap);
/*---------------------------------------------------------------------------*/
/*
* IT IS ESSENTIAL TO INITIALIZE THE HARDWARE BEFORE, RATHER THAN AFTER,
@@ -3866,7 +3775,7 @@
* THE VIDEO DEVICE CAN BE REGISTERED NOW, AS IT IS READY.
*/
/*--------------------------------------------------------------------------*/
- if (0 != (v4l2_device_register(&(pusb_interface->dev),
+ if (0 != (v4l2_device_register(&(intf->dev),
&(peasycap->v4l2_device)))) {
SAM("v4l2_device_register() failed\n");
return -ENODEV;
@@ -3924,9 +3833,9 @@
* SAVE POINTER peasycap IN INTERFACE 1
*/
/*--------------------------------------------------------------------------*/
- usb_set_intfdata(pusb_interface, peasycap);
+ usb_set_intfdata(intf, peasycap);
JOM(4, "no initialization required for interface %i\n",
- pusb_interface_descriptor->bInterfaceNumber);
+ interface->bInterfaceNumber);
break;
}
/*--------------------------------------------------------------------------*/
@@ -4188,7 +4097,7 @@
* SAVE POINTER peasycap IN THIS INTERFACE.
*/
/*---------------------------------------------------------------------------*/
- usb_set_intfdata(pusb_interface, peasycap);
+ usb_set_intfdata(intf, peasycap);
/*---------------------------------------------------------------------------*/
/*
* THE AUDIO DEVICE CAN BE REGISTERED NOW, AS IT IS READY.
@@ -4201,28 +4110,22 @@
if (rc) {
err("easycap_alsa_probe() rc = %i\n", rc);
return -ENODEV;
- } else {
- JOM(8, "kref_get() with %i=kref.refcount.counter\n",
- peasycap->kref.refcount.counter);
- kref_get(&peasycap->kref);
- peasycap->registered_audio++;
}
#else /* CONFIG_EASYCAP_OSS */
- rc = usb_register_dev(pusb_interface, &easyoss_class);
+ rc = usb_register_dev(intf, &easyoss_class);
if (rc) {
SAY("ERROR: usb_register_dev() failed\n");
- usb_set_intfdata(pusb_interface, NULL);
+ usb_set_intfdata(intf, NULL);
return -ENODEV;
- } else {
- JOM(8, "kref_get() with %i=kref.refcount.counter\n",
- peasycap->kref.refcount.counter);
- kref_get(&peasycap->kref);
- peasycap->registered_audio++;
}
- SAM("easyoss attached to minor #%d\n", pusb_interface->minor);
+ SAM("easyoss attached to minor #%d\n", intf->minor);
#endif /* CONFIG_EASYCAP_OSS */
+ JOM(8, "kref_get() with %i=kref.refcount.counter\n",
+ peasycap->kref.refcount.counter);
+ kref_get(&peasycap->kref);
+ peasycap->registered_audio++;
break;
}
/*---------------------------------------------------------------------------*/
diff --git a/drivers/staging/echo/echo.c b/drivers/staging/echo/echo.c
index 3c188d5..c0adae1 100644
--- a/drivers/staging/echo/echo.c
+++ b/drivers/staging/echo/echo.c
@@ -113,12 +113,10 @@
#define DTD_HANGOVER 600 /* 600 samples, or 75ms */
#define DC_LOG2BETA 3 /* log2() of DC filter Beta */
-
/* adapting coeffs using the traditional stochastic descent (N)LMS algorithm */
#ifdef __bfin__
-static inline void lms_adapt_bg(struct oslec_state *ec, int clean,
- int shift)
+static inline void lms_adapt_bg(struct oslec_state *ec, int clean, int shift)
{
int i, j;
int offset1;
@@ -189,8 +187,7 @@
*/
#else
-static inline void lms_adapt_bg(struct oslec_state *ec, int clean,
- int shift)
+static inline void lms_adapt_bg(struct oslec_state *ec, int clean, int shift)
{
int i;
@@ -225,7 +222,7 @@
if (bits == 0)
return -1;
else
- return (int)fls((int32_t)bits)-1;
+ return (int)fls((int32_t) bits) - 1;
}
struct oslec_state *oslec_create(int len, int adaption_mode)
@@ -279,6 +276,7 @@
kfree(ec);
return NULL;
}
+
EXPORT_SYMBOL_GPL(oslec_create);
void oslec_free(struct oslec_state *ec)
@@ -292,12 +290,14 @@
kfree(ec->snapshot);
kfree(ec);
}
+
EXPORT_SYMBOL_GPL(oslec_free);
void oslec_adaption_mode(struct oslec_state *ec, int adaption_mode)
{
ec->adaption_mode = adaption_mode;
}
+
EXPORT_SYMBOL_GPL(oslec_adaption_mode);
void oslec_flush(struct oslec_state *ec)
@@ -324,12 +324,14 @@
ec->curr_pos = ec->taps - 1;
ec->Pstates = 0;
}
+
EXPORT_SYMBOL_GPL(oslec_flush);
void oslec_snapshot(struct oslec_state *ec)
{
memcpy(ec->snapshot, ec->fir_taps16[0], ec->taps * sizeof(int16_t));
}
+
EXPORT_SYMBOL_GPL(oslec_snapshot);
/* Dual Path Echo Canceller */
@@ -404,11 +406,11 @@
/* efficient "out with the old and in with the new" algorithm so
we don't have to recalculate over the whole block of
samples. */
- new = (int)tx * (int)tx;
+ new = (int)tx *(int)tx;
old = (int)ec->fir_state.history[ec->fir_state.curr_pos] *
(int)ec->fir_state.history[ec->fir_state.curr_pos];
ec->Pstates +=
- ((new - old) + (1 << (ec->log2taps-1))) >> ec->log2taps;
+ ((new - old) + (1 << (ec->log2taps - 1))) >> ec->log2taps;
if (ec->Pstates < 0)
ec->Pstates = 0;
}
@@ -466,7 +468,7 @@
factor = (2^30) * (2^-2) * clean_bg_rx/P
- (30 - 2 - log2(P))
+ (30 - 2 - log2(P))
factor = clean_bg_rx 2 ----- (3)
To avoid a divide we approximate log2(P) as top_bit(P),
@@ -514,7 +516,7 @@
*/
ec->adapt = 1;
memcpy(ec->fir_taps16[0], ec->fir_taps16[1],
- ec->taps * sizeof(int16_t));
+ ec->taps * sizeof(int16_t));
} else
ec->cond_met++;
} else
@@ -601,6 +603,7 @@
return (int16_t) ec->clean_nlp << 1;
}
+
EXPORT_SYMBOL_GPL(oslec_update);
/* This function is separated from the echo canceller is it is usually called
@@ -625,7 +628,7 @@
giving very clean DC removal.
*/
-int16_t oslec_hpf_tx(struct oslec_state *ec, int16_t tx)
+int16_t oslec_hpf_tx(struct oslec_state * ec, int16_t tx)
{
int tmp, tmp1;
@@ -654,6 +657,7 @@
return tx;
}
+
EXPORT_SYMBOL_GPL(oslec_hpf_tx);
MODULE_LICENSE("GPL");
diff --git a/drivers/staging/ft1000/ft1000-pcmcia/ft1000_cs.c b/drivers/staging/ft1000/ft1000-pcmcia/ft1000_cs.c
index 10af477..68ea035 100644
--- a/drivers/staging/ft1000/ft1000-pcmcia/ft1000_cs.c
+++ b/drivers/staging/ft1000/ft1000-pcmcia/ft1000_cs.c
@@ -284,7 +284,7 @@
/*====================================================================*/
-static struct pcmcia_device_id ft1000_ids[] = {
+static const struct pcmcia_device_id ft1000_ids[] = {
PCMCIA_DEVICE_MANF_CARD(0x02cc, 0x0100),
PCMCIA_DEVICE_MANF_CARD(0x02cc, 0x1000),
PCMCIA_DEVICE_MANF_CARD(0x02cc, 0x1300),
diff --git a/drivers/staging/ft1000/ft1000-usb/ft1000_hw.c b/drivers/staging/ft1000/ft1000-usb/ft1000_hw.c
index 684e69e..b0a4211 100644
--- a/drivers/staging/ft1000/ft1000-usb/ft1000_hw.c
+++ b/drivers/staging/ft1000/ft1000-usb/ft1000_hw.c
@@ -6,8 +6,6 @@
//
// $Id:
//====================================================
-// 20090926; aelias; removed compiler warnings & errors; ubuntu 9.04; 2.6.28-15-generic
-
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/module.h>
@@ -38,8 +36,6 @@
static struct net_device_stats *ft1000_netdev_stats(struct net_device *dev);
static int ft1000_chkcard (struct ft1000_device *dev);
-//Jim
-
static u8 tempbuffer[1600];
#define MAX_RCV_LOOP 100
@@ -492,8 +488,6 @@
commandbuf = (unsigned char *)kmalloc(size + 2, GFP_KERNEL);
memcpy((void *)commandbuf + 2, (void *)ptempbuffer, size);
- //DEBUG("card_send_command: Command Send\n");
-
ft1000_read_register(ft1000dev, &temp, FT1000_REG_DOORBELL);
if (temp & 0x0100)
@@ -506,16 +500,14 @@
if (size % 4)
size += 4 - (size % 4);
- //DEBUG("card_send_command: write dpram ... size=%d\n", size);
ft1000_write_dpram32(ft1000dev, 0, commandbuf, size);
msleep(1);
- //DEBUG("card_send_command: write into doorbell ...\n");
ft1000_write_register(ft1000dev, FT1000_DB_DPRAM_TX,
FT1000_REG_DOORBELL);
msleep(1);
ft1000_read_register(ft1000dev, &temp, FT1000_REG_DOORBELL);
- //DEBUG("card_send_command: read doorbell ...temp=%x\n", temp);
+
if ((temp & 0x0100) == 0) {
//DEBUG("card_send_command: Message sent\n");
}
@@ -601,8 +593,6 @@
DEBUG("ft1000_hw:ft1000_reset_asic called\n");
- info->ASICResetNum++;
-
/* Let's use the register provided by the Magnemite ASIC to reset the
* ASIC and DSP.
*/
@@ -660,8 +650,6 @@
DEBUG("ft1000_hw:ft1000_reset_card: reset asic\n");
ft1000_reset_asic(dev);
- info->DSPResetNum++;
-
DEBUG("ft1000_hw:ft1000_reset_card: call dsp_reload\n");
dsp_reload(ft1000dev);
@@ -683,8 +671,6 @@
return TRUE;
}
-
-//mbelian
#ifdef HAVE_NET_DEVICE_OPS
static const struct net_device_ops ftnet_ops =
{
@@ -758,14 +744,11 @@
spin_lock_init(&pInfo->dpram_lock);
pInfo->pFt1000Dev = ft1000dev;
pInfo->DrvErrNum = 0;
- pInfo->ASICResetNum = 0;
pInfo->registered = 1;
pInfo->ft1000_reset = ft1000_reset;
pInfo->mediastate = 0;
pInfo->fifo_cnt = 0;
pInfo->DeviceCreated = FALSE;
- pInfo->CurrentInterruptEnableMask = ISR_DEFAULT_MASK;
- pInfo->InterruptsEnabled = FALSE;
pInfo->CardReady = 0;
pInfo->DSP_TIME[0] = 0;
pInfo->DSP_TIME[1] = 0;
@@ -904,14 +887,10 @@
struct ft1000_device *ft1000dev = urb->context;
- //DEBUG("ft1000_usb_transmit_complete entered\n");
-
if (urb->status)
pr_err("%s: TX status %d\n", ft1000dev->net->name, urb->status);
netif_wake_queue(ft1000dev->net);
-
- //DEBUG("Return from ft1000_usb_transmit_complete\n");
}
//---------------------------------------------------------------------------
@@ -943,8 +922,6 @@
return -ENODEV;
}
- //DEBUG("ft1000_copy_down_pkt() entered, len = %d\n", len);
-
count = sizeof(struct pseudo_hdr) + len;
if (count > MAX_BUF_SIZE) {
DEBUG("Error:ft1000_copy_down_pkt:Message Size Overflow!\n");
@@ -973,8 +950,6 @@
netif_stop_queue(netdev);
- //DEBUG ("ft1000_copy_down_pkt: count = %d\n", count);
-
usb_fill_bulk_urb(pFt1000Dev->tx_urb,
pFt1000Dev->dev,
usb_sndbulkpipe(pFt1000Dev->dev,
@@ -983,11 +958,6 @@
ft1000_usb_transmit_complete, (void *)pFt1000Dev);
t = (u8 *) pFt1000Dev->tx_urb->transfer_buffer;
- //DEBUG("transfer_length=%d\n", pFt1000Dev->tx_urb->transfer_buffer_length);
- /*for (i=0; i<count; i++ )
- {
- DEBUG("%x ", *t++ );
- } */
ret = usb_submit_urb(pFt1000Dev->tx_urb, GFP_ATOMIC);
@@ -999,8 +969,6 @@
pInfo->stats.tx_bytes += (len + 14);
}
- //DEBUG("ft1000_copy_down_pkt() exit\n");
-
return 0;
}
@@ -1026,8 +994,6 @@
u8 *pdata;
int maxlen, pipe;
- //DEBUG(" ft1000_start_xmit() entered\n");
-
if (skb == NULL) {
DEBUG("ft1000_hw: ft1000_start_xmit:skb == NULL!!!\n");
return NETDEV_TX_OK;
@@ -1037,17 +1003,12 @@
DEBUG("network driver is closed, return\n");
goto err;
}
- //DEBUG("ft1000_start_xmit 1:length of packet = %d\n", skb->len);
+
pipe =
usb_sndbulkpipe(pFt1000Dev->dev, pFt1000Dev->bulk_out_endpointAddr);
maxlen = usb_maxpacket(pFt1000Dev->dev, pipe, usb_pipeout(pipe));
- //DEBUG("ft1000_start_xmit 2: pipe=%d dev->maxpacket = %d\n", pipe, maxlen);
pdata = (u8 *) skb->data;
- /*for (i=0; i<skb->len; i++)
- DEBUG("skb->data[%d]=%x ", i, *(skb->data+i));
-
- DEBUG("\n"); */
if (pInfo->mediastate == 0) {
/* Drop packet is mediastate is down */
@@ -1060,13 +1021,12 @@
DEBUG("ft1000_hw:ft1000_start_xmit:invalid ethernet length\n");
goto err;
}
-//mbelian
+
ft1000_copy_down_pkt(dev, (pdata + ENET_HEADER_SIZE - 2),
skb->len - ENET_HEADER_SIZE + 2);
err:
dev_kfree_skb(skb);
- //DEBUG(" ft1000_start_xmit() exit\n");
return NETDEV_TX_OK;
}
@@ -1093,24 +1053,20 @@
u16 tempword;
u16 len;
- u16 lena; //mbelian
+ u16 lena;
struct sk_buff *skb;
u16 i;
u8 *pbuffer = NULL;
u8 *ptemp = NULL;
u16 *chksum;
- //DEBUG("ft1000_copy_up_pkt entered\n");
-
if (ft1000dev->status & FT1000_STATUS_CLOSING) {
DEBUG("network driver is closed, return\n");
return STATUS_SUCCESS;
}
// Read length
len = urb->transfer_buffer_length;
- lena = urb->actual_length; //mbelian
- //DEBUG("ft1000_copy_up_pkt: transfer_buffer_length=%d, actual_buffer_len=%d\n",
- // urb->transfer_buffer_length, urb->actual_length);
+ lena = urb->actual_length;
chksum = (u16 *) ft1000dev->rx_buf;
@@ -1124,8 +1080,6 @@
return STATUS_FAILURE;
}
- //DEBUG("ft1000_copy_up_pkt: checksum is correct %x\n", *chksum);
-
skb = dev_alloc_skb(len + 12 + 2);
if (skb == NULL) {
@@ -1157,12 +1111,6 @@
memcpy(pbuffer, ft1000dev->rx_buf + sizeof(struct pseudo_hdr),
len - sizeof(struct pseudo_hdr));
- //DEBUG("ft1000_copy_up_pkt: Data passed to Protocol layer\n");
- /*for (i=0; i<len+12; i++)
- {
- DEBUG("ft1000_copy_up_pkt: Protocol Data: 0x%x\n ", *ptemp++);
- } */
-
skb->dev = net;
skb->protocol = eth_type_trans(skb, net);
@@ -1171,10 +1119,10 @@
info->stats.rx_packets++;
/* Add on 12 bytes for MAC address which was removed */
- info->stats.rx_bytes += (lena + 12); //mbelian
+ info->stats.rx_bytes += (lena + 12);
ft1000_submit_rx_urb(info);
- //DEBUG("ft1000_copy_up_pkt exited\n");
+
return SUCCESS;
}
@@ -1197,10 +1145,8 @@
int result;
struct ft1000_device *pFt1000Dev = info->pFt1000Dev;
- //DEBUG ("ft1000_submit_rx_urb entered: sizeof rx_urb is %d\n", sizeof(*pFt1000Dev->rx_urb));
if (pFt1000Dev->status & FT1000_STATUS_CLOSING) {
DEBUG("network driver is closed, return\n");
- //usb_kill_urb(pFt1000Dev->rx_urb); //mbelian
return -ENODEV;
}
@@ -1218,7 +1164,6 @@
result);
return result;
}
- //DEBUG("ft1000_submit_rx_urb exit: result=%d\n", result);
return 0;
}
@@ -1241,23 +1186,22 @@
static int ft1000_open(struct net_device *dev)
{
struct ft1000_info *pInfo = netdev_priv(dev);
- struct timeval tv; //mbelian
+ struct timeval tv;
int ret;
DEBUG("ft1000_open is called for card %d\n", pInfo->CardNumber);
- //DEBUG("ft1000_open: dev->addr=%x, dev->addr_len=%d\n", dev->addr, dev->addr_len);
- pInfo->stats.rx_bytes = 0; //mbelian
- pInfo->stats.tx_bytes = 0; //mbelian
- pInfo->stats.rx_packets = 0; //mbelian
- pInfo->stats.tx_packets = 0; //mbelian
+ pInfo->stats.rx_bytes = 0;
+ pInfo->stats.tx_bytes = 0;
+ pInfo->stats.rx_packets = 0;
+ pInfo->stats.tx_packets = 0;
do_gettimeofday(&tv);
pInfo->ConTm = tv.tv_sec;
- pInfo->ProgConStat = 0; //mbelian
+ pInfo->ProgConStat = 0;
netif_start_queue(dev);
- netif_carrier_on(dev); //mbelian
+ netif_carrier_on(dev);
ret = ft1000_submit_rx_urb(pInfo);
@@ -1283,19 +1227,14 @@
struct ft1000_info *pInfo = netdev_priv(net);
struct ft1000_device *ft1000dev = pInfo->pFt1000Dev;
- //DEBUG ("ft1000_close: netdev->refcnt=%d\n", net->refcnt);
-
ft1000dev->status |= FT1000_STATUS_CLOSING;
- //DEBUG("ft1000_close: calling usb_kill_urb \n");
-
DEBUG("ft1000_close: pInfo=%p, ft1000dev=%p\n", pInfo, ft1000dev);
- netif_carrier_off(net); //mbelian
+ netif_carrier_off(net);
netif_stop_queue(net);
- //DEBUG("ft1000_close: netif_stop_queue called\n");
ft1000dev->status &= ~FT1000_STATUS_CLOSING;
- pInfo->ProgConStat = 0xff; //mbelian
+ pInfo->ProgConStat = 0xff;
return 0;
}
@@ -1304,15 +1243,10 @@
{
struct ft1000_info *info = netdev_priv(dev);
- return &(info->stats); //mbelian
+ return &(info->stats);
}
-/*********************************************************************************
-Jim
-*/
-
-
//---------------------------------------------------------------------------
//
// Function: ft1000_chkcard
@@ -1340,7 +1274,6 @@
* set to zero.
*/
status = ft1000_read_register(dev, &tempword, FT1000_REG_SUP_IMASK);
- //DEBUG("ft1000_hw:ft1000_chkcard: read FT1000_REG_SUP_IMASK = %x\n", tempword);
if (tempword == 0) {
DEBUG
("ft1000_hw:ft1000_chkcard: IMASK = 0 Card not detected\n");
@@ -1350,9 +1283,8 @@
* if the device is not present.
*/
status = ft1000_read_register(dev, &tempword, FT1000_REG_ASIC_ID);
- //DEBUG("ft1000_hw:ft1000_chkcard: read FT1000_REG_ASIC_ID = %x\n", tempword);
if (tempword != 0x1b01) {
- dev->status |= FT1000_STATUS_CLOSING; //mbelian
+ dev->status |= FT1000_STATUS_CLOSING;
DEBUG
("ft1000_hw:ft1000_chkcard: Version = 0xffff Card not detected\n");
return FALSE;
@@ -1395,7 +1327,6 @@
FT1000_REG_DPRAM_ADDR);
ret =
ft1000_read_register(dev, pbuffer, FT1000_REG_MAG_DPDATAH);
- //DEBUG("ft1000_hw:received data = 0x%x\n", *pbuffer);
pbuffer++;
ft1000_write_register(dev, FT1000_DPRAM_MAG_RX_BASE + 1,
FT1000_REG_DPRAM_ADDR);
@@ -1412,11 +1343,11 @@
/* copy odd aligned word */
ret =
ft1000_read_register(dev, pbuffer, FT1000_REG_MAG_DPDATAL);
- //DEBUG("ft1000_hw:received data = 0x%x\n", *pbuffer);
+
pbuffer++;
ret =
ft1000_read_register(dev, pbuffer, FT1000_REG_MAG_DPDATAH);
- //DEBUG("ft1000_hw:received data = 0x%x\n", *pbuffer);
+
pbuffer++;
if (size & 0x0001) {
/* copy odd byte from fifo */
@@ -1495,10 +1426,8 @@
ppseudo_hdr->portsrc = 0;
/* Calculate new checksum */
ppseudo_hdr->checksum = *pmsg++;
- //DEBUG("checksum = 0x%x\n", ppseudo_hdr->checksum);
for (i = 1; i < 7; i++) {
ppseudo_hdr->checksum ^= *pmsg++;
- //DEBUG("checksum = 0x%x\n", ppseudo_hdr->checksum);
}
TempShortBuf[0] = 0;
@@ -1582,21 +1511,16 @@
DEBUG("Media is up\n");
if (info->mediastate == 0) {
if (info->NetDevRegDone) {
- //netif_carrier_on(dev->net);//mbelian
netif_wake_queue(dev->
net);
}
info->mediastate = 1;
- /*do_gettimeofday(&tv);
- info->ConTm = tv.tv_sec; *///mbelian
}
} else {
DEBUG("Media is down\n");
if (info->mediastate == 1) {
info->mediastate = 0;
if (info->NetDevRegDone) {
- //netif_carrier_off(dev->net); mbelian
- //netif_stop_queue(dev->net);
}
info->ConTm = 0;
}
@@ -1605,10 +1529,6 @@
DEBUG("Media is down\n");
if (info->mediastate == 1) {
info->mediastate = 0;
- if (info->NetDevRegDone) {
- //netif_carrier_off(dev->net); //mbelian
- //netif_stop_queue(dev->net);
- }
info->ConTm = 0;
}
}
@@ -1860,31 +1780,26 @@
struct pseudo_hdr *ppseudo_hdr;
unsigned long flags;
- //DEBUG("Enter ft1000_poll...\n");
if (ft1000_chkcard(dev) == FALSE) {
DEBUG("ft1000_poll::ft1000_chkcard: failed\n");
return STATUS_FAILURE;
}
status = ft1000_read_register (dev, &tempword, FT1000_REG_DOORBELL);
- // DEBUG("ft1000_poll: read FT1000_REG_DOORBELL message 0x%x\n", tempword);
if ( !status )
{
if (tempword & FT1000_DB_DPRAM_RX) {
- //DEBUG("ft1000_poll: FT1000_REG_DOORBELL message type: FT1000_DB_DPRAM_RX\n");
status = ft1000_read_dpram16(dev, 0x200, (u8 *)&data, 0);
- //DEBUG("ft1000_poll:FT1000_DB_DPRAM_RX:ft1000_read_dpram16:size = 0x%x\n", data);
- size = ntohs(data) + 16 + 2; //wai
+ size = ntohs(data) + 16 + 2;
if (size % 4) {
modulo = 4 - (size % 4);
size = size + modulo;
}
status = ft1000_read_dpram16(dev, 0x201, (u8 *)&portid, 1);
portid &= 0xff;
- //DEBUG("ft1000_poll: FT1000_REG_DOORBELL message type: FT1000_DB_DPRAM_RX : portid 0x%x\n", portid);
if (size < MAX_CMD_SQSIZE) {
switch (portid)
@@ -1899,13 +1814,11 @@
case DSPBCMSGID:
// This is a dsp broadcast message
// Check which application has registered for dsp broadcast messages
- //DEBUG("ft1000_poll: FT1000_REG_DOORBELL message type: FT1000_DB_DPRAM_RX : portid DSPBCMSGID\n");
for (i=0; i<MAX_NUM_APP; i++) {
if ( (info->app_info[i].DspBCMsgFlag) && (info->app_info[i].fileobject) &&
(info->app_info[i].NumOfMsg < MAX_MSG_LIMIT) )
{
- //DEBUG("Dsp broadcast message detected for app id %d\n", i);
nxtph = FT1000_DPRAM_RX_BASE + 2;
pdpram_blk = ft1000_get_buffer (&freercvpool);
if (pdpram_blk != NULL) {
@@ -1929,15 +1842,13 @@
else {
DEBUG("Out of memory in free receive command pool\n");
info->app_info[i].nRxMsgMiss++;
- }//endof if (pdpram_blk != NULL)
- }//endof if
- //else
- // DEBUG("app_info mismatch\n");
- }// endof for
+ }
+ }
+ }
break;
default:
pdpram_blk = ft1000_get_buffer (&freercvpool);
- //DEBUG("Memory allocated = 0x%8x\n", (u32)pdpram_blk);
+
if (pdpram_blk != NULL) {
if ( ft1000_receive_cmd(dev, pdpram_blk->pbuffer, MAX_CMD_SQSIZE, &nxtph) ) {
ppseudo_hdr = (struct pseudo_hdr *)pdpram_blk->pbuffer;
@@ -1961,11 +1872,8 @@
else {
info->app_info[i].nRxMsg++;
// Put message into the appropriate application block
- //pxu spin_lock_irqsave(&free_buff_lock, flags);
list_add_tail(&pdpram_blk->list, &info->app_info[i].app_sqlist);
info->app_info[i].NumOfMsg++;
- //pxu spin_unlock_irqrestore(&free_buff_lock, flags);
- //pxu wake_up_interruptible(&info->app_info[i].wait_dpram_msg);
}
}
}
@@ -1978,15 +1886,14 @@
DEBUG("Out of memory in free receive command pool\n");
}
break;
- } //end of switch
- } //endof if (size < MAX_CMD_SQSIZE)
+ }
+ }
else {
DEBUG("FT1000:dpc:Invalid total length for SlowQ = %d\n", size);
}
status = ft1000_write_register (dev, FT1000_DB_DPRAM_RX, FT1000_REG_DOORBELL);
}
else if (tempword & FT1000_DSP_ASIC_RESET) {
- //DEBUG("ft1000_poll: FT1000_REG_DOORBELL message type: FT1000_DSP_ASIC_RESET\n");
// Let's reset the ASIC from the Host side as well
status = ft1000_write_register (dev, ASIC_RESET_BIT, FT1000_REG_RESET);
@@ -2025,10 +1932,8 @@
}
else if (tempword & FT1000_DB_COND_RESET) {
DEBUG("ft1000_poll: FT1000_REG_DOORBELL message type: FT1000_DB_COND_RESET\n");
-//By Jim
-// Reset ASIC and DSP
-//MAG
- if (info->fAppMsgPend == 0) {
+
+ if (info->fAppMsgPend == 0) {
// Reset ASIC and DSP
status = ft1000_read_dpram16(dev, FT1000_MAG_DSP_TIMER0, (u8 *)&(info->DSP_TIME[0]), FT1000_MAG_DSP_TIMER0_INDX);
@@ -2048,11 +1953,8 @@
ft1000_write_register(dev, FT1000_DB_COND_RESET, FT1000_REG_DOORBELL);
}
- }//endof if ( !status )
+ }
- //DEBUG("return from ft1000_poll.\n");
return STATUS_SUCCESS;
}
-
-/*end of Jim*/
diff --git a/drivers/staging/ft1000/ft1000-usb/ft1000_usb.h b/drivers/staging/ft1000/ft1000-usb/ft1000_usb.h
index f2ecb3e..0b30020 100644
--- a/drivers/staging/ft1000/ft1000-usb/ft1000_usb.h
+++ b/drivers/staging/ft1000/ft1000-usb/ft1000_usb.h
@@ -494,21 +494,9 @@
bool fProvComplete;
bool fCondResetPend;
bool fAppMsgPend;
- char *pfwimg;
- int fwimgsz;
u16 DrvErrNum;
- u8 *pTestImage;
u16 AsicID;
- unsigned long TestImageIndx;
- unsigned long TestImageSz;
- u8 TestImageEnable;
- u8 TestImageReady;
- int ASICResetNum;
int DspAsicReset;
- int PktIntfErr;
- int DSPResetNum;
- int NumIOCTLBufs;
- int IOCTLBufLvl;
int DeviceCreated;
int CardReady;
int NetDevRegDone;
@@ -517,13 +505,9 @@
struct ft1000_debug_dirs nodes;
int registered;
int mediastate;
- int dhcpflg;
- u16 packetseqnum;
u8 squeseqnum; // sequence number on slow queue
spinlock_t dpram_lock;
spinlock_t fifo_lock;
- u16 CurrentInterruptEnableMask;
- int InterruptsEnabled;
u16 fifo_cnt;
u8 DspVer[DSPVERSZ]; // DSP version number
u8 HwSerNum[HWSERNUMSZ]; // Hardware Serial Number
@@ -534,7 +518,6 @@
u8 RfCalVer[CALVERSZ];
u8 RfCalDate[CALDATESZ];
u16 DSP_TIME[4];
- u16 ProgSnr;
u16 LedStat; //mbelian
u16 ConStat; //mbelian
u16 ProgConStat;
@@ -586,8 +569,6 @@
struct dpram_blk *ft1000_get_buffer(struct list_head *bufflist);
void ft1000_free_buffer(struct dpram_blk *pdpram_blk, struct list_head *plist);
-char *getfw (char *fn, size_t *pimgsz);
-
int dsp_reload(struct ft1000_device *ft1000dev);
int init_ft1000_netdev(struct ft1000_device *ft1000dev);
struct usb_interface;
diff --git a/drivers/staging/gma500/Makefile b/drivers/staging/gma500/Makefile
index a52ba48..db73ec6 100644
--- a/drivers/staging/gma500/Makefile
+++ b/drivers/staging/gma500/Makefile
@@ -5,6 +5,7 @@
psb_gfx-y += psb_bl.o \
psb_drv.o \
+ psb_gem.o \
psb_fb.o \
psb_2d.o \
psb_gtt.o \
@@ -15,17 +16,11 @@
psb_intel_lvds.o \
psb_intel_modes.o \
psb_intel_sdvo.o \
- psb_reset.o \
- psb_sgx.o \
- psb_pvr_glue.o \
- psb_buffer.o \
- psb_fence.o \
+ psb_lid.o \
psb_mmu.o \
- psb_ttm_glue.o \
- psb_ttm_fence.o \
- psb_ttm_fence_user.o \
- psb_ttm_placement_user.o \
psb_powermgmt.o \
- psb_irq.o
+ psb_irq.o \
+ mrst_crtc.o \
+ mrst_lvds.o
obj-$(CONFIG_DRM_PSB) += psb_gfx.o
diff --git a/drivers/staging/gma500/mrst.h b/drivers/staging/gma500/mrst.h
new file mode 100644
index 0000000..5e4aaeb
--- /dev/null
+++ b/drivers/staging/gma500/mrst.h
@@ -0,0 +1,217 @@
+/**************************************************************************
+ * Copyright (c) 2007-2011, Intel Corporation.
+ * All Rights Reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ **************************************************************************/
+
+/* MID device specific descriptors */
+
+struct mrst_vbt {
+ s8 signature[4]; /*4 bytes,"$GCT" */
+ u8 revision;
+ u8 size;
+ u8 checksum;
+ void *mrst_gct;
+} __attribute__ ((packed));
+
+struct mrst_timing_info {
+ u16 pixel_clock;
+ u8 hactive_lo;
+ u8 hblank_lo;
+ u8 hblank_hi:4;
+ u8 hactive_hi:4;
+ u8 vactive_lo;
+ u8 vblank_lo;
+ u8 vblank_hi:4;
+ u8 vactive_hi:4;
+ u8 hsync_offset_lo;
+ u8 hsync_pulse_width_lo;
+ u8 vsync_pulse_width_lo:4;
+ u8 vsync_offset_lo:4;
+ u8 vsync_pulse_width_hi:2;
+ u8 vsync_offset_hi:2;
+ u8 hsync_pulse_width_hi:2;
+ u8 hsync_offset_hi:2;
+ u8 width_mm_lo;
+ u8 height_mm_lo;
+ u8 height_mm_hi:4;
+ u8 width_mm_hi:4;
+ u8 hborder;
+ u8 vborder;
+ u8 unknown0:1;
+ u8 hsync_positive:1;
+ u8 vsync_positive:1;
+ u8 separate_sync:2;
+ u8 stereo:1;
+ u8 unknown6:1;
+ u8 interlaced:1;
+} __attribute__((packed));
+
+struct gct_r10_timing_info {
+ u16 pixel_clock;
+ u32 hactive_lo:8;
+ u32 hactive_hi:4;
+ u32 hblank_lo:8;
+ u32 hblank_hi:4;
+ u32 hsync_offset_lo:8;
+ u16 hsync_offset_hi:2;
+ u16 hsync_pulse_width_lo:8;
+ u16 hsync_pulse_width_hi:2;
+ u16 hsync_positive:1;
+ u16 rsvd_1:3;
+ u8 vactive_lo:8;
+ u16 vactive_hi:4;
+ u16 vblank_lo:8;
+ u16 vblank_hi:4;
+ u16 vsync_offset_lo:4;
+ u16 vsync_offset_hi:2;
+ u16 vsync_pulse_width_lo:4;
+ u16 vsync_pulse_width_hi:2;
+ u16 vsync_positive:1;
+ u16 rsvd_2:3;
+} __attribute__((packed));
+
+struct mrst_panel_descriptor_v1 {
+ u32 Panel_Port_Control; /* 1 dword, Register 0x61180 if LVDS */
+ /* 0x61190 if MIPI */
+ u32 Panel_Power_On_Sequencing;/*1 dword,Register 0x61208,*/
+ u32 Panel_Power_Off_Sequencing;/*1 dword,Register 0x6120C,*/
+ u32 Panel_Power_Cycle_Delay_and_Reference_Divisor;/* 1 dword */
+ /* Register 0x61210 */
+ struct mrst_timing_info DTD;/*18 bytes, Standard definition */
+ u16 Panel_Backlight_Inverter_Descriptor;/* 16 bits, as follows */
+ /* Bit 0, Frequency, 15 bits,0 - 32767Hz */
+ /* Bit 15, Polarity, 1 bit, 0: Normal, 1: Inverted */
+ u16 Panel_MIPI_Display_Descriptor;
+ /*16 bits, Defined as follows: */
+ /* if MIPI, 0x0000 if LVDS */
+ /* Bit 0, Type, 2 bits, */
+ /* 0: Type-1, */
+ /* 1: Type-2, */
+ /* 2: Type-3, */
+ /* 3: Type-4 */
+ /* Bit 2, Pixel Format, 4 bits */
+ /* Bit0: 16bpp (not supported in LNC), */
+ /* Bit1: 18bpp loosely packed, */
+ /* Bit2: 18bpp packed, */
+ /* Bit3: 24bpp */
+ /* Bit 6, Reserved, 2 bits, 00b */
+ /* Bit 8, Minimum Supported Frame Rate, 6 bits, 0 - 63Hz */
+ /* Bit 14, Reserved, 2 bits, 00b */
+} __attribute__ ((packed));
+
+struct mrst_panel_descriptor_v2 {
+ u32 Panel_Port_Control; /* 1 dword, Register 0x61180 if LVDS */
+ /* 0x61190 if MIPI */
+ u32 Panel_Power_On_Sequencing;/*1 dword,Register 0x61208,*/
+ u32 Panel_Power_Off_Sequencing;/*1 dword,Register 0x6120C,*/
+ u8 Panel_Power_Cycle_Delay_and_Reference_Divisor;/* 1 byte */
+ /* Register 0x61210 */
+ struct mrst_timing_info DTD;/*18 bytes, Standard definition */
+ u16 Panel_Backlight_Inverter_Descriptor;/*16 bits, as follows*/
+ /*Bit 0, Frequency, 16 bits, 0 - 32767Hz*/
+ u8 Panel_Initial_Brightness;/* [7:0] 0 - 100% */
+ /*Bit 7, Polarity, 1 bit,0: Normal, 1: Inverted*/
+ u16 Panel_MIPI_Display_Descriptor;
+ /*16 bits, Defined as follows: */
+ /* if MIPI, 0x0000 if LVDS */
+ /* Bit 0, Type, 2 bits, */
+ /* 0: Type-1, */
+ /* 1: Type-2, */
+ /* 2: Type-3, */
+ /* 3: Type-4 */
+ /* Bit 2, Pixel Format, 4 bits */
+ /* Bit0: 16bpp (not supported in LNC), */
+ /* Bit1: 18bpp loosely packed, */
+ /* Bit2: 18bpp packed, */
+ /* Bit3: 24bpp */
+ /* Bit 6, Reserved, 2 bits, 00b */
+ /* Bit 8, Minimum Supported Frame Rate, 6 bits, 0 - 63Hz */
+ /* Bit 14, Reserved, 2 bits, 00b */
+} __attribute__ ((packed));
+
+union mrst_panel_rx {
+ struct{
+ u16 NumberOfLanes:2; /*Num of Lanes, 2 bits,0 = 1 lane,*/
+ /* 1 = 2 lanes, 2 = 3 lanes, 3 = 4 lanes. */
+ u16 MaxLaneFreq:3; /* 0: 100MHz, 1: 200MHz, 2: 300MHz, */
+ /*3: 400MHz, 4: 500MHz, 5: 600MHz, 6: 700MHz, 7: 800MHz.*/
+ u16 SupportedVideoTransferMode:2; /*0: Non-burst only */
+ /* 1: Burst and non-burst */
+ /* 2/3: Reserved */
+ u16 HSClkBehavior:1; /*0: Continuous, 1: Non-continuous*/
+ u16 DuoDisplaySupport:1; /*1 bit,0: No, 1: Yes*/
+ u16 ECC_ChecksumCapabilities:1;/*1 bit,0: No, 1: Yes*/
+ u16 BidirectionalCommunication:1;/*1 bit,0: No, 1: Yes */
+ u16 Rsvd:5;/*5 bits,00000b */
+ } panelrx;
+ u16 panel_receiver;
+} __attribute__ ((packed));
+
+struct mrst_gct_v1 {
+ union{ /*8 bits,Defined as follows: */
+ struct {
+ u8 PanelType:4; /*4 bits, Bit field for panels*/
+ /* 0 - 3: 0 = LVDS, 1 = MIPI*/
+ /*2 bits,Specifies which of the*/
+ u8 BootPanelIndex:2;
+ /* 4 panels to use by default*/
+ u8 BootMIPI_DSI_RxIndex:2;/*Specifies which of*/
+ /* the 4 MIPI DSI receivers to use*/
+ } PD;
+ u8 PanelDescriptor;
+ };
+ struct mrst_panel_descriptor_v1 panel[4];/*panel descrs,38 bytes each*/
+ union mrst_panel_rx panelrx[4]; /* panel receivers*/
+} __attribute__ ((packed));
+
+struct mrst_gct_v2 {
+ union{ /*8 bits,Defined as follows: */
+ struct {
+ u8 PanelType:4; /*4 bits, Bit field for panels*/
+ /* 0 - 3: 0 = LVDS, 1 = MIPI*/
+ /*2 bits,Specifies which of the*/
+ u8 BootPanelIndex:2;
+ /* 4 panels to use by default*/
+ u8 BootMIPI_DSI_RxIndex:2;/*Specifies which of*/
+ /* the 4 MIPI DSI receivers to use*/
+ } PD;
+ u8 PanelDescriptor;
+ };
+ struct mrst_panel_descriptor_v2 panel[4];/*panel descrs,38 bytes each*/
+ union mrst_panel_rx panelrx[4]; /* panel receivers*/
+} __attribute__ ((packed));
+
+struct mrst_gct_data {
+ u8 bpi; /* boot panel index, number of panel used during boot */
+ u8 pt; /* panel type, 4 bit field, 0=lvds, 1=mipi */
+ struct mrst_timing_info DTD; /* timing info for the selected panel */
+ u32 Panel_Port_Control;
+ u32 PP_On_Sequencing;/*1 dword,Register 0x61208,*/
+ u32 PP_Off_Sequencing;/*1 dword,Register 0x6120C,*/
+ u32 PP_Cycle_Delay;
+ u16 Panel_Backlight_Inverter_Descriptor;
+ u16 Panel_MIPI_Display_Descriptor;
+} __attribute__ ((packed));
+
+#define MODE_SETTING_IN_CRTC 0x1
+#define MODE_SETTING_IN_ENCODER 0x2
+#define MODE_SETTING_ON_GOING 0x3
+#define MODE_SETTING_IN_DSR 0x4
+#define MODE_SETTING_ENCODER_DONE 0x8
+#define GCT_R10_HEADER_SIZE 16
+#define GCT_R10_DISPLAY_DESC_SIZE 28
+
diff --git a/drivers/staging/gma500/mrst_crtc.c b/drivers/staging/gma500/mrst_crtc.c
new file mode 100644
index 0000000..e4a0c03
--- /dev/null
+++ b/drivers/staging/gma500/mrst_crtc.c
@@ -0,0 +1,619 @@
+/*
+ * Copyright © 2009 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ */
+
+#include <linux/i2c.h>
+#include <linux/pm_runtime.h>
+
+#include <drm/drmP.h>
+#include "psb_fb.h"
+#include "psb_drv.h"
+#include "psb_intel_drv.h"
+#include "psb_intel_reg.h"
+#include "psb_intel_display.h"
+#include "psb_powermgmt.h"
+
+struct psb_intel_range_t {
+ int min, max;
+};
+
+struct mrst_limit_t {
+ struct psb_intel_range_t dot, m, p1;
+};
+
+struct mrst_clock_t {
+ /* derived values */
+ int dot;
+ int m;
+ int p1;
+};
+
+#define MRST_LIMIT_LVDS_100L 0
+#define MRST_LIMIT_LVDS_83 1
+#define MRST_LIMIT_LVDS_100 2
+
+#define MRST_DOT_MIN 19750
+#define MRST_DOT_MAX 120000
+#define MRST_M_MIN_100L 20
+#define MRST_M_MIN_100 10
+#define MRST_M_MIN_83 12
+#define MRST_M_MAX_100L 34
+#define MRST_M_MAX_100 17
+#define MRST_M_MAX_83 20
+#define MRST_P1_MIN 2
+#define MRST_P1_MAX_0 7
+#define MRST_P1_MAX_1 8
+
+static const struct mrst_limit_t mrst_limits[] = {
+ { /* MRST_LIMIT_LVDS_100L */
+ .dot = {.min = MRST_DOT_MIN, .max = MRST_DOT_MAX},
+ .m = {.min = MRST_M_MIN_100L, .max = MRST_M_MAX_100L},
+ .p1 = {.min = MRST_P1_MIN, .max = MRST_P1_MAX_1},
+ },
+ { /* MRST_LIMIT_LVDS_83L */
+ .dot = {.min = MRST_DOT_MIN, .max = MRST_DOT_MAX},
+ .m = {.min = MRST_M_MIN_83, .max = MRST_M_MAX_83},
+ .p1 = {.min = MRST_P1_MIN, .max = MRST_P1_MAX_0},
+ },
+ { /* MRST_LIMIT_LVDS_100 */
+ .dot = {.min = MRST_DOT_MIN, .max = MRST_DOT_MAX},
+ .m = {.min = MRST_M_MIN_100, .max = MRST_M_MAX_100},
+ .p1 = {.min = MRST_P1_MIN, .max = MRST_P1_MAX_1},
+ },
+};
+
+#define MRST_M_MIN 10
+static const u32 mrst_m_converts[] = {
+ 0x2B, 0x15, 0x2A, 0x35, 0x1A, 0x0D, 0x26, 0x33, 0x19, 0x2C,
+ 0x36, 0x3B, 0x1D, 0x2E, 0x37, 0x1B, 0x2D, 0x16, 0x0B, 0x25,
+ 0x12, 0x09, 0x24, 0x32, 0x39, 0x1c,
+};
+
+static const struct mrst_limit_t *mrst_limit(struct drm_crtc *crtc)
+{
+ const struct mrst_limit_t *limit = NULL;
+ struct drm_device *dev = crtc->dev;
+ DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private;
+
+ if (psb_intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)
+ || psb_intel_pipe_has_type(crtc, INTEL_OUTPUT_MIPI)) {
+ switch (dev_priv->core_freq) {
+ case 100:
+ limit = &mrst_limits[MRST_LIMIT_LVDS_100L];
+ break;
+ case 166:
+ limit = &mrst_limits[MRST_LIMIT_LVDS_83];
+ break;
+ case 200:
+ limit = &mrst_limits[MRST_LIMIT_LVDS_100];
+ break;
+ }
+ } else {
+ limit = NULL;
+ PSB_DEBUG_ENTRY("mrst_limit Wrong display type.\n");
+ }
+
+ return limit;
+}
+
+/** Derive the pixel clock for the given refclk and divisors for 8xx chips. */
+static void mrst_clock(int refclk, struct mrst_clock_t *clock)
+{
+ clock->dot = (refclk * clock->m) / (14 * clock->p1);
+}
+
+void mrstPrintPll(char *prefix, struct mrst_clock_t *clock)
+{
+ PSB_DEBUG_ENTRY("%s: dotclock = %d, m = %d, p1 = %d.\n",
+ prefix, clock->dot, clock->m, clock->p1);
+}
+
+/**
+ * Returns a set of divisors for the desired target clock with the given refclk,
+ * or FALSE. Divisor values are the actual divisors for
+ */
+static bool
+mrstFindBestPLL(struct drm_crtc *crtc, int target, int refclk,
+ struct mrst_clock_t *best_clock)
+{
+ struct mrst_clock_t clock;
+ const struct mrst_limit_t *limit = mrst_limit(crtc);
+ int err = target;
+
+ memset(best_clock, 0, sizeof(*best_clock));
+
+ for (clock.m = limit->m.min; clock.m <= limit->m.max; clock.m++) {
+ for (clock.p1 = limit->p1.min; clock.p1 <= limit->p1.max;
+ clock.p1++) {
+ int this_err;
+
+ mrst_clock(refclk, &clock);
+
+ this_err = abs(clock.dot - target);
+ if (this_err < err) {
+ *best_clock = clock;
+ err = this_err;
+ }
+ }
+ }
+ DRM_DEBUG("mrstFindBestPLL err = %d.\n", err);
+
+ return err != target;
+}
+
+/**
+ * Sets the power management mode of the pipe and plane.
+ *
+ * This code should probably grow support for turning the cursor off and back
+ * on appropriately at the same time as we're turning the pipe off/on.
+ */
+static void mrst_crtc_dpms(struct drm_crtc *crtc, int mode)
+{
+ struct drm_device *dev = crtc->dev;
+ struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
+ int pipe = psb_intel_crtc->pipe;
+ int dpll_reg = (pipe == 0) ? MRST_DPLL_A : DPLL_B;
+ int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
+ int dspbase_reg = (pipe == 0) ? MRST_DSPABASE : DSPBBASE;
+ int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
+ u32 temp;
+ bool enabled;
+
+ PSB_DEBUG_ENTRY("mode = %d, pipe = %d\n", mode, pipe);
+
+ if (!gma_power_begin(dev, true))
+ return;
+
+ /* XXX: When our outputs are all unaware of DPMS modes other than off
+ * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
+ */
+ switch (mode) {
+ case DRM_MODE_DPMS_ON:
+ case DRM_MODE_DPMS_STANDBY:
+ case DRM_MODE_DPMS_SUSPEND:
+ /* Enable the DPLL */
+ temp = REG_READ(dpll_reg);
+ if ((temp & DPLL_VCO_ENABLE) == 0) {
+ REG_WRITE(dpll_reg, temp);
+ REG_READ(dpll_reg);
+ /* Wait for the clocks to stabilize. */
+ udelay(150);
+ REG_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
+ REG_READ(dpll_reg);
+ /* Wait for the clocks to stabilize. */
+ udelay(150);
+ REG_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
+ REG_READ(dpll_reg);
+ /* Wait for the clocks to stabilize. */
+ udelay(150);
+ }
+ /* Enable the pipe */
+ temp = REG_READ(pipeconf_reg);
+ if ((temp & PIPEACONF_ENABLE) == 0)
+ REG_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
+ /* Enable the plane */
+ temp = REG_READ(dspcntr_reg);
+ if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
+ REG_WRITE(dspcntr_reg,
+ temp | DISPLAY_PLANE_ENABLE);
+ /* Flush the plane changes */
+ REG_WRITE(dspbase_reg, REG_READ(dspbase_reg));
+ }
+
+ psb_intel_crtc_load_lut(crtc);
+
+ /* Give the overlay scaler a chance to enable
+ if it's on this pipe */
+ /* psb_intel_crtc_dpms_video(crtc, true); TODO */
+ break;
+ case DRM_MODE_DPMS_OFF:
+ /* Give the overlay scaler a chance to disable
+ * if it's on this pipe */
+ /* psb_intel_crtc_dpms_video(crtc, FALSE); TODO */
+
+ /* Disable the VGA plane that we never use */
+ REG_WRITE(VGACNTRL, VGA_DISP_DISABLE);
+ /* Disable display plane */
+ temp = REG_READ(dspcntr_reg);
+ if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
+ REG_WRITE(dspcntr_reg,
+ temp & ~DISPLAY_PLANE_ENABLE);
+ /* Flush the plane changes */
+ REG_WRITE(dspbase_reg, REG_READ(dspbase_reg));
+ REG_READ(dspbase_reg);
+ }
+
+ /* Next, disable display pipes */
+ temp = REG_READ(pipeconf_reg);
+ if ((temp & PIPEACONF_ENABLE) != 0) {
+ REG_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
+ REG_READ(pipeconf_reg);
+ }
+ /* Wait for for the pipe disable to take effect. */
+ psb_intel_wait_for_vblank(dev);
+
+ temp = REG_READ(dpll_reg);
+ if ((temp & DPLL_VCO_ENABLE) != 0) {
+ REG_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
+ REG_READ(dpll_reg);
+ }
+
+ /* Wait for the clocks to turn off. */
+ udelay(150);
+ break;
+ }
+
+ enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
+
+ /*Set FIFO Watermarks*/
+ REG_WRITE(DSPARB, 0x3FFF);
+ REG_WRITE(DSPFW1, 0x3F88080A);
+ REG_WRITE(DSPFW2, 0x0b060808);
+ REG_WRITE(DSPFW3, 0x0);
+ REG_WRITE(DSPFW4, 0x08030404);
+ REG_WRITE(DSPFW5, 0x04040404);
+ REG_WRITE(DSPFW6, 0x78);
+ REG_WRITE(0x70400, REG_READ(0x70400) | 0x4000);
+ /* Must write Bit 14 of the Chicken Bit Register */
+
+ gma_power_end(dev);
+}
+
+/**
+ * Return the pipe currently connected to the panel fitter,
+ * or -1 if the panel fitter is not present or not in use
+ */
+static int mrst_panel_fitter_pipe(struct drm_device *dev)
+{
+ u32 pfit_control;
+
+ pfit_control = REG_READ(PFIT_CONTROL);
+
+ /* See if the panel fitter is in use */
+ if ((pfit_control & PFIT_ENABLE) == 0)
+ return -1;
+ return (pfit_control >> 29) & 3;
+}
+
+static int mrst_crtc_mode_set(struct drm_crtc *crtc,
+ struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode,
+ int x, int y,
+ struct drm_framebuffer *old_fb)
+{
+ struct drm_device *dev = crtc->dev;
+ struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
+ DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private;
+ int pipe = psb_intel_crtc->pipe;
+ int fp_reg = (pipe == 0) ? MRST_FPA0 : FPB0;
+ int dpll_reg = (pipe == 0) ? MRST_DPLL_A : DPLL_B;
+ int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
+ int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
+ int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
+ int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
+ int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
+ int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
+ int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
+ int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
+ int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
+ int refclk = 0;
+ struct mrst_clock_t clock;
+ u32 dpll = 0, fp = 0, dspcntr, pipeconf;
+ bool ok, is_sdvo = false;
+ bool is_crt = false, is_lvds = false, is_tv = false;
+ bool is_mipi = false;
+ struct drm_mode_config *mode_config = &dev->mode_config;
+ struct psb_intel_output *psb_intel_output = NULL;
+ uint64_t scalingType = DRM_MODE_SCALE_FULLSCREEN;
+ struct drm_encoder *encoder;
+
+ PSB_DEBUG_ENTRY("pipe = 0x%x\n", pipe);
+
+ if (!gma_power_begin(dev, true))
+ return 0;
+
+ memcpy(&psb_intel_crtc->saved_mode,
+ mode,
+ sizeof(struct drm_display_mode));
+ memcpy(&psb_intel_crtc->saved_adjusted_mode,
+ adjusted_mode,
+ sizeof(struct drm_display_mode));
+
+ list_for_each_entry(encoder, &mode_config->encoder_list, head) {
+
+ if (encoder->crtc != crtc)
+ continue;
+
+ psb_intel_output = enc_to_psb_intel_output(encoder);
+ switch (psb_intel_output->type) {
+ case INTEL_OUTPUT_LVDS:
+ is_lvds = true;
+ break;
+ case INTEL_OUTPUT_SDVO:
+ is_sdvo = true;
+ break;
+ case INTEL_OUTPUT_TVOUT:
+ is_tv = true;
+ break;
+ case INTEL_OUTPUT_ANALOG:
+ is_crt = true;
+ break;
+ case INTEL_OUTPUT_MIPI:
+ is_mipi = true;
+ break;
+ }
+ }
+
+ /* Disable the VGA plane that we never use */
+ REG_WRITE(VGACNTRL, VGA_DISP_DISABLE);
+
+ /* Disable the panel fitter if it was on our pipe */
+ if (mrst_panel_fitter_pipe(dev) == pipe)
+ REG_WRITE(PFIT_CONTROL, 0);
+
+ REG_WRITE(pipesrc_reg,
+ ((mode->crtc_hdisplay - 1) << 16) |
+ (mode->crtc_vdisplay - 1));
+
+ if (psb_intel_output)
+ drm_connector_property_get_value(&psb_intel_output->base,
+ dev->mode_config.scaling_mode_property, &scalingType);
+
+ if (scalingType == DRM_MODE_SCALE_NO_SCALE) {
+ /* Moorestown doesn't have register support for centering so
+ * we need to mess with the h/vblank and h/vsync start and
+ * ends to get centering */
+ int offsetX = 0, offsetY = 0;
+
+ offsetX = (adjusted_mode->crtc_hdisplay -
+ mode->crtc_hdisplay) / 2;
+ offsetY = (adjusted_mode->crtc_vdisplay -
+ mode->crtc_vdisplay) / 2;
+
+ REG_WRITE(htot_reg, (mode->crtc_hdisplay - 1) |
+ ((adjusted_mode->crtc_htotal - 1) << 16));
+ REG_WRITE(vtot_reg, (mode->crtc_vdisplay - 1) |
+ ((adjusted_mode->crtc_vtotal - 1) << 16));
+ REG_WRITE(hblank_reg,
+ (adjusted_mode->crtc_hblank_start - offsetX - 1) |
+ ((adjusted_mode->crtc_hblank_end - offsetX - 1) << 16));
+ REG_WRITE(hsync_reg,
+ (adjusted_mode->crtc_hsync_start - offsetX - 1) |
+ ((adjusted_mode->crtc_hsync_end - offsetX - 1) << 16));
+ REG_WRITE(vblank_reg,
+ (adjusted_mode->crtc_vblank_start - offsetY - 1) |
+ ((adjusted_mode->crtc_vblank_end - offsetY - 1) << 16));
+ REG_WRITE(vsync_reg,
+ (adjusted_mode->crtc_vsync_start - offsetY - 1) |
+ ((adjusted_mode->crtc_vsync_end - offsetY - 1) << 16));
+ } else {
+ REG_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
+ ((adjusted_mode->crtc_htotal - 1) << 16));
+ REG_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
+ ((adjusted_mode->crtc_vtotal - 1) << 16));
+ REG_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
+ ((adjusted_mode->crtc_hblank_end - 1) << 16));
+ REG_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
+ ((adjusted_mode->crtc_hsync_end - 1) << 16));
+ REG_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
+ ((adjusted_mode->crtc_vblank_end - 1) << 16));
+ REG_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
+ ((adjusted_mode->crtc_vsync_end - 1) << 16));
+ }
+
+ /* Flush the plane changes */
+ {
+ struct drm_crtc_helper_funcs *crtc_funcs =
+ crtc->helper_private;
+ crtc_funcs->mode_set_base(crtc, x, y, old_fb);
+ }
+
+ /* setup pipeconf */
+ pipeconf = REG_READ(pipeconf_reg);
+
+ /* Set up the display plane register */
+ dspcntr = REG_READ(dspcntr_reg);
+ dspcntr |= DISPPLANE_GAMMA_ENABLE;
+
+ if (pipe == 0)
+ dspcntr |= DISPPLANE_SEL_PIPE_A;
+ else
+ dspcntr |= DISPPLANE_SEL_PIPE_B;
+
+ dev_priv->dspcntr = dspcntr |= DISPLAY_PLANE_ENABLE;
+ dev_priv->pipeconf = pipeconf |= PIPEACONF_ENABLE;
+
+ if (is_mipi)
+ goto mrst_crtc_mode_set_exit;
+
+ refclk = dev_priv->core_freq * 1000;
+
+ dpll = 0; /*BIT16 = 0 for 100MHz reference */
+
+ ok = mrstFindBestPLL(crtc, adjusted_mode->clock, refclk, &clock);
+
+ if (!ok) {
+ PSB_DEBUG_ENTRY(
+ "mrstFindBestPLL fail in mrst_crtc_mode_set.\n");
+ } else {
+ PSB_DEBUG_ENTRY("mrst_crtc_mode_set pixel clock = %d,"
+ "m = %x, p1 = %x.\n", clock.dot, clock.m,
+ clock.p1);
+ }
+
+ fp = mrst_m_converts[(clock.m - MRST_M_MIN)] << 8;
+
+ dpll |= DPLL_VGA_MODE_DIS;
+
+
+ dpll |= DPLL_VCO_ENABLE;
+
+ if (is_lvds)
+ dpll |= DPLLA_MODE_LVDS;
+ else
+ dpll |= DPLLB_MODE_DAC_SERIAL;
+
+ if (is_sdvo) {
+ int sdvo_pixel_multiply =
+ adjusted_mode->clock / mode->clock;
+
+ dpll |= DPLL_DVO_HIGH_SPEED;
+ dpll |=
+ (sdvo_pixel_multiply -
+ 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
+ }
+
+
+ /* compute bitmask from p1 value */
+ dpll |= (1 << (clock.p1 - 2)) << 17;
+
+ dpll |= DPLL_VCO_ENABLE;
+
+ mrstPrintPll("chosen", &clock);
+
+ if (dpll & DPLL_VCO_ENABLE) {
+ REG_WRITE(fp_reg, fp);
+ REG_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
+ REG_READ(dpll_reg);
+ /* Check the DPLLA lock bit PIPEACONF[29] */
+ udelay(150);
+ }
+
+ REG_WRITE(fp_reg, fp);
+ REG_WRITE(dpll_reg, dpll);
+ REG_READ(dpll_reg);
+ /* Wait for the clocks to stabilize. */
+ udelay(150);
+
+ /* write it again -- the BIOS does, after all */
+ REG_WRITE(dpll_reg, dpll);
+ REG_READ(dpll_reg);
+ /* Wait for the clocks to stabilize. */
+ udelay(150);
+
+ REG_WRITE(pipeconf_reg, pipeconf);
+ REG_READ(pipeconf_reg);
+ psb_intel_wait_for_vblank(dev);
+
+ REG_WRITE(dspcntr_reg, dspcntr);
+ psb_intel_wait_for_vblank(dev);
+
+mrst_crtc_mode_set_exit:
+ gma_power_end(dev);
+ return 0;
+}
+
+static bool mrst_crtc_mode_fixup(struct drm_crtc *crtc,
+ struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode)
+{
+ return true;
+}
+
+int mrst_pipe_set_base(struct drm_crtc *crtc,
+ int x, int y, struct drm_framebuffer *old_fb)
+{
+ struct drm_device *dev = crtc->dev;
+ /* struct drm_i915_master_private *master_priv; */
+ struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
+ struct psb_framebuffer *psbfb = to_psb_fb(crtc->fb);
+ int pipe = psb_intel_crtc->pipe;
+ unsigned long start, offset;
+ /* FIXME: check if we need this surely MRST is pipe 0 only */
+ int dspbase = (pipe == 0 ? DSPALINOFF : DSPBBASE);
+ int dspsurf = (pipe == 0 ? DSPASURF : DSPBSURF);
+ int dspstride = (pipe == 0) ? DSPASTRIDE : DSPBSTRIDE;
+ int dspcntr_reg = (pipe == 0) ? DSPACNTR : DSPBCNTR;
+ u32 dspcntr;
+ int ret = 0;
+
+ PSB_DEBUG_ENTRY("\n");
+
+ /* no fb bound */
+ if (!crtc->fb) {
+ DRM_DEBUG("No FB bound\n");
+ return 0;
+ }
+
+ if (!gma_power_begin(dev, true))
+ return 0;
+
+ start = psbfb->gtt->offset;
+ offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
+
+ REG_WRITE(dspstride, crtc->fb->pitch);
+
+ dspcntr = REG_READ(dspcntr_reg);
+ dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
+
+ switch (crtc->fb->bits_per_pixel) {
+ case 8:
+ dspcntr |= DISPPLANE_8BPP;
+ break;
+ case 16:
+ if (crtc->fb->depth == 15)
+ dspcntr |= DISPPLANE_15_16BPP;
+ else
+ dspcntr |= DISPPLANE_16BPP;
+ break;
+ case 24:
+ case 32:
+ dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
+ break;
+ default:
+ DRM_ERROR("Unknown color depth\n");
+ ret = -EINVAL;
+ goto pipe_set_base_exit;
+ }
+ REG_WRITE(dspcntr_reg, dspcntr);
+
+ DRM_DEBUG("Writing base %08lX %08lX %d %d\n", start, offset, x, y);
+ if (0 /* FIXMEAC - check what PSB needs */) {
+ REG_WRITE(dspbase, offset);
+ REG_READ(dspbase);
+ REG_WRITE(dspsurf, start);
+ REG_READ(dspsurf);
+ } else {
+ REG_WRITE(dspbase, start + offset);
+ REG_READ(dspbase);
+ }
+
+pipe_set_base_exit:
+ gma_power_end(dev);
+ return ret;
+}
+
+static void mrst_crtc_prepare(struct drm_crtc *crtc)
+{
+ struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
+ crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
+}
+
+static void mrst_crtc_commit(struct drm_crtc *crtc)
+{
+ struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
+ crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
+}
+
+const struct drm_crtc_helper_funcs mrst_helper_funcs = {
+ .dpms = mrst_crtc_dpms,
+ .mode_fixup = mrst_crtc_mode_fixup,
+ .mode_set = mrst_crtc_mode_set,
+ .mode_set_base = mrst_pipe_set_base,
+ .prepare = mrst_crtc_prepare,
+ .commit = mrst_crtc_commit,
+};
+
diff --git a/drivers/staging/gma500/mrst_lvds.c b/drivers/staging/gma500/mrst_lvds.c
new file mode 100644
index 0000000..4a08b74
--- /dev/null
+++ b/drivers/staging/gma500/mrst_lvds.c
@@ -0,0 +1,371 @@
+/*
+ * Copyright © 2006-2009 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Authors:
+ * Eric Anholt <eric@anholt.net>
+ * Dave Airlie <airlied@linux.ie>
+ * Jesse Barnes <jesse.barnes@intel.com>
+ */
+
+#include <linux/i2c.h>
+#include <drm/drmP.h>
+#include <asm/mrst.h>
+
+#include "psb_intel_bios.h"
+#include "psb_drv.h"
+#include "psb_intel_drv.h"
+#include "psb_intel_reg.h"
+#include "psb_powermgmt.h"
+#include <linux/pm_runtime.h>
+
+/* The max/min PWM frequency in BPCR[31:17] - */
+/* The smallest number is 1 (not 0) that can fit in the
+ * 15-bit field of the and then*/
+/* shifts to the left by one bit to get the actual 16-bit
+ * value that the 15-bits correspond to.*/
+#define MRST_BLC_MAX_PWM_REG_FREQ 0xFFFF
+#define BRIGHTNESS_MAX_LEVEL 100
+
+/**
+ * Sets the power state for the panel.
+ */
+static void mrst_lvds_set_power(struct drm_device *dev,
+ struct psb_intel_output *output, bool on)
+{
+ u32 pp_status;
+ DRM_DRIVER_PRIVATE_T *dev_priv = dev->dev_private;
+ PSB_DEBUG_ENTRY("\n");
+
+ if (!gma_power_begin(dev, true))
+ return;
+
+ if (on) {
+ REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) |
+ POWER_TARGET_ON);
+ do {
+ pp_status = REG_READ(PP_STATUS);
+ } while ((pp_status & (PP_ON | PP_READY)) == PP_READY);
+ dev_priv->is_lvds_on = true;
+ } else {
+ REG_WRITE(PP_CONTROL, REG_READ(PP_CONTROL) &
+ ~POWER_TARGET_ON);
+ do {
+ pp_status = REG_READ(PP_STATUS);
+ } while (pp_status & PP_ON);
+ dev_priv->is_lvds_on = false;
+ pm_request_idle(&dev->pdev->dev);
+ }
+
+ gma_power_end(dev);
+}
+
+static void mrst_lvds_dpms(struct drm_encoder *encoder, int mode)
+{
+ struct drm_device *dev = encoder->dev;
+ struct psb_intel_output *output = enc_to_psb_intel_output(encoder);
+
+ PSB_DEBUG_ENTRY("\n");
+
+ if (mode == DRM_MODE_DPMS_ON)
+ mrst_lvds_set_power(dev, output, true);
+ else
+ mrst_lvds_set_power(dev, output, false);
+
+ /* XXX: We never power down the LVDS pairs. */
+}
+
+static void mrst_lvds_mode_set(struct drm_encoder *encoder,
+ struct drm_display_mode *mode,
+ struct drm_display_mode *adjusted_mode)
+{
+ struct psb_intel_mode_device *mode_dev =
+ enc_to_psb_intel_output(encoder)->mode_dev;
+ struct drm_device *dev = encoder->dev;
+ u32 lvds_port;
+ uint64_t v = DRM_MODE_SCALE_FULLSCREEN;
+
+ PSB_DEBUG_ENTRY("\n");
+
+ if (!gma_power_begin(dev, true))
+ return;
+
+ /*
+ * The LVDS pin pair will already have been turned on in the
+ * psb_intel_crtc_mode_set since it has a large impact on the DPLL
+ * settings.
+ */
+ lvds_port = (REG_READ(LVDS) &
+ (~LVDS_PIPEB_SELECT)) |
+ LVDS_PORT_EN |
+ LVDS_BORDER_EN;
+
+ if (mode_dev->panel_wants_dither)
+ lvds_port |= MRST_PANEL_8TO6_DITHER_ENABLE;
+
+ REG_WRITE(LVDS, lvds_port);
+
+ drm_connector_property_get_value(
+ &enc_to_psb_intel_output(encoder)->base,
+ dev->mode_config.scaling_mode_property,
+ &v);
+
+ if (v == DRM_MODE_SCALE_NO_SCALE)
+ REG_WRITE(PFIT_CONTROL, 0);
+ else if (v == DRM_MODE_SCALE_ASPECT) {
+ if ((mode->vdisplay != adjusted_mode->crtc_vdisplay) ||
+ (mode->hdisplay != adjusted_mode->crtc_hdisplay)) {
+ if ((adjusted_mode->crtc_hdisplay * mode->vdisplay) ==
+ (mode->hdisplay * adjusted_mode->crtc_vdisplay))
+ REG_WRITE(PFIT_CONTROL, PFIT_ENABLE);
+ else if ((adjusted_mode->crtc_hdisplay *
+ mode->vdisplay) > (mode->hdisplay *
+ adjusted_mode->crtc_vdisplay))
+ REG_WRITE(PFIT_CONTROL, PFIT_ENABLE |
+ PFIT_SCALING_MODE_PILLARBOX);
+ else
+ REG_WRITE(PFIT_CONTROL, PFIT_ENABLE |
+ PFIT_SCALING_MODE_LETTERBOX);
+ } else
+ REG_WRITE(PFIT_CONTROL, PFIT_ENABLE);
+ } else /*(v == DRM_MODE_SCALE_FULLSCREEN)*/
+ REG_WRITE(PFIT_CONTROL, PFIT_ENABLE);
+
+ gma_power_end(dev);
+}
+
+
+static const struct drm_encoder_helper_funcs mrst_lvds_helper_funcs = {
+ .dpms = mrst_lvds_dpms,
+ .mode_fixup = psb_intel_lvds_mode_fixup,
+ .prepare = psb_intel_lvds_prepare,
+ .mode_set = mrst_lvds_mode_set,
+ .commit = psb_intel_lvds_commit,
+};
+
+static struct drm_display_mode lvds_configuration_modes[] = {
+ /* hard coded fixed mode for TPO LTPS LPJ040K001A */
+ { DRM_MODE("800x480", DRM_MODE_TYPE_DRIVER, 33264, 800, 836,
+ 846, 1056, 0, 480, 489, 491, 525, 0, 0) },
+ /* hard coded fixed mode for LVDS 800x480 */
+ { DRM_MODE("800x480", DRM_MODE_TYPE_DRIVER, 30994, 800, 801,
+ 802, 1024, 0, 480, 481, 482, 525, 0, 0) },
+ /* hard coded fixed mode for Samsung 480wsvga LVDS 1024x600@75 */
+ { DRM_MODE("1024x600", DRM_MODE_TYPE_DRIVER, 53990, 1024, 1072,
+ 1104, 1184, 0, 600, 603, 604, 608, 0, 0) },
+ /* hard coded fixed mode for Samsung 480wsvga LVDS 1024x600@75 */
+ { DRM_MODE("1024x600", DRM_MODE_TYPE_DRIVER, 53990, 1024, 1104,
+ 1136, 1184, 0, 600, 603, 604, 608, 0, 0) },
+ /* hard coded fixed mode for Sharp wsvga LVDS 1024x600 */
+ { DRM_MODE("1024x600", DRM_MODE_TYPE_DRIVER, 48885, 1024, 1124,
+ 1204, 1312, 0, 600, 607, 610, 621, 0, 0) },
+ /* hard coded fixed mode for LVDS 1024x768 */
+ { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048,
+ 1184, 1344, 0, 768, 771, 777, 806, 0, 0) },
+ /* hard coded fixed mode for LVDS 1366x768 */
+ { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 77500, 1366, 1430,
+ 1558, 1664, 0, 768, 769, 770, 776, 0, 0) },
+};
+
+/* Returns the panel fixed mode from configuration. */
+
+static struct drm_display_mode *
+mrst_lvds_get_configuration_mode(struct drm_device *dev)
+{
+ struct drm_display_mode *mode = NULL;
+ struct drm_psb_private *dev_priv = dev->dev_private;
+ struct mrst_timing_info *ti = &dev_priv->gct_data.DTD;
+
+ if (dev_priv->vbt_data.size != 0x00) { /*if non-zero, then use vbt*/
+ mode = kzalloc(sizeof(*mode), GFP_KERNEL);
+ if (!mode)
+ return NULL;
+
+ mode->hdisplay = (ti->hactive_hi << 8) | ti->hactive_lo;
+ mode->vdisplay = (ti->vactive_hi << 8) | ti->vactive_lo;
+ mode->hsync_start = mode->hdisplay + \
+ ((ti->hsync_offset_hi << 8) | \
+ ti->hsync_offset_lo);
+ mode->hsync_end = mode->hsync_start + \
+ ((ti->hsync_pulse_width_hi << 8) | \
+ ti->hsync_pulse_width_lo);
+ mode->htotal = mode->hdisplay + ((ti->hblank_hi << 8) | \
+ ti->hblank_lo);
+ mode->vsync_start = \
+ mode->vdisplay + ((ti->vsync_offset_hi << 4) | \
+ ti->vsync_offset_lo);
+ mode->vsync_end = \
+ mode->vsync_start + ((ti->vsync_pulse_width_hi << 4) | \
+ ti->vsync_pulse_width_lo);
+ mode->vtotal = mode->vdisplay + \
+ ((ti->vblank_hi << 8) | ti->vblank_lo);
+ mode->clock = ti->pixel_clock * 10;
+#if 0
+ printk(KERN_INFO "hdisplay is %d\n", mode->hdisplay);
+ printk(KERN_INFO "vdisplay is %d\n", mode->vdisplay);
+ printk(KERN_INFO "HSS is %d\n", mode->hsync_start);
+ printk(KERN_INFO "HSE is %d\n", mode->hsync_end);
+ printk(KERN_INFO "htotal is %d\n", mode->htotal);
+ printk(KERN_INFO "VSS is %d\n", mode->vsync_start);
+ printk(KERN_INFO "VSE is %d\n", mode->vsync_end);
+ printk(KERN_INFO "vtotal is %d\n", mode->vtotal);
+ printk(KERN_INFO "clock is %d\n", mode->clock);
+#endif
+ } else
+ mode = drm_mode_duplicate(dev, &lvds_configuration_modes[2]);
+
+ drm_mode_set_name(mode);
+ drm_mode_set_crtcinfo(mode, 0);
+
+ return mode;
+}
+
+/**
+ * mrst_lvds_init - setup LVDS connectors on this device
+ * @dev: drm device
+ *
+ * Create the connector, register the LVDS DDC bus, and try to figure out what
+ * modes we can display on the LVDS panel (if present).
+ */
+void mrst_lvds_init(struct drm_device *dev,
+ struct psb_intel_mode_device *mode_dev)
+{
+ struct psb_intel_output *psb_intel_output;
+ struct drm_connector *connector;
+ struct drm_encoder *encoder;
+ struct drm_psb_private *dev_priv =
+ (struct drm_psb_private *) dev->dev_private;
+ struct edid *edid;
+ int ret = 0;
+ struct i2c_adapter *i2c_adap;
+ struct drm_display_mode *scan; /* *modes, *bios_mode; */
+
+ PSB_DEBUG_ENTRY("\n");
+
+ psb_intel_output = kzalloc(sizeof(struct psb_intel_output), GFP_KERNEL);
+ if (!psb_intel_output)
+ return;
+
+ psb_intel_output->mode_dev = mode_dev;
+ connector = &psb_intel_output->base;
+ encoder = &psb_intel_output->enc;
+ dev_priv->is_lvds_on = true;
+ drm_connector_init(dev, &psb_intel_output->base,
+ &psb_intel_lvds_connector_funcs,
+ DRM_MODE_CONNECTOR_LVDS);
+
+ drm_encoder_init(dev, &psb_intel_output->enc, &psb_intel_lvds_enc_funcs,
+ DRM_MODE_ENCODER_LVDS);
+
+ drm_mode_connector_attach_encoder(&psb_intel_output->base,
+ &psb_intel_output->enc);
+ psb_intel_output->type = INTEL_OUTPUT_LVDS;
+
+ drm_encoder_helper_add(encoder, &mrst_lvds_helper_funcs);
+ drm_connector_helper_add(connector,
+ &psb_intel_lvds_connector_helper_funcs);
+ connector->display_info.subpixel_order = SubPixelHorizontalRGB;
+ connector->interlace_allowed = false;
+ connector->doublescan_allowed = false;
+
+ drm_connector_attach_property(connector,
+ dev->mode_config.scaling_mode_property,
+ DRM_MODE_SCALE_FULLSCREEN);
+ drm_connector_attach_property(connector,
+ dev_priv->backlight_property,
+ BRIGHTNESS_MAX_LEVEL);
+
+ mode_dev->panel_wants_dither = false;
+ if (dev_priv->vbt_data.size != 0x00)
+ mode_dev->panel_wants_dither = (dev_priv->gct_data.
+ Panel_Port_Control & MRST_PANEL_8TO6_DITHER_ENABLE);
+
+ /*
+ * LVDS discovery:
+ * 1) check for EDID on DDC
+ * 2) check for VBT data
+ * 3) check to see if LVDS is already on
+ * if none of the above, no panel
+ * 4) make sure lid is open
+ * if closed, act like it's not there for now
+ */
+
+ /* This ifdef can go once the cpu ident stuff is cleaned up in arch */
+#if defined(CONFIG_X86_MRST)
+ if (mrst_identify_cpu())
+ i2c_adap = i2c_get_adapter(2);
+ else /* Oaktrail uses I2C 1 */
+#endif
+ i2c_adap = i2c_get_adapter(1);
+
+ if (i2c_adap == NULL)
+ printk(KERN_ALERT "No ddc adapter available!\n");
+ /*
+ * Attempt to get the fixed panel mode from DDC. Assume that the
+ * preferred mode is the right one.
+ */
+ if (i2c_adap) {
+ edid = drm_get_edid(connector, i2c_adap);
+ if (edid) {
+ drm_mode_connector_update_edid_property(connector,
+ edid);
+ ret = drm_add_edid_modes(connector, edid);
+ kfree(edid);
+ }
+
+ list_for_each_entry(scan, &connector->probed_modes, head) {
+ if (scan->type & DRM_MODE_TYPE_PREFERRED) {
+ mode_dev->panel_fixed_mode =
+ drm_mode_duplicate(dev, scan);
+ goto out; /* FIXME: check for quirks */
+ }
+ }
+ }
+
+ /*
+ * If we didn't get EDID, try geting panel timing
+ * from configuration data
+ */
+ mode_dev->panel_fixed_mode = mrst_lvds_get_configuration_mode(dev);
+
+ if (mode_dev->panel_fixed_mode) {
+ mode_dev->panel_fixed_mode->type |=
+ DRM_MODE_TYPE_PREFERRED;
+ goto out; /* FIXME: check for quirks */
+ }
+
+ /* If we still don't have a mode after all that, give up. */
+ if (!mode_dev->panel_fixed_mode) {
+ DRM_DEBUG
+ ("Found no modes on the lvds, ignoring the LVDS\n");
+ goto failed_find;
+ }
+
+out:
+ drm_sysfs_connector_add(connector);
+ return;
+
+failed_find:
+ DRM_DEBUG("No LVDS modes found, disabling.\n");
+ if (psb_intel_output->ddc_bus)
+ psb_intel_i2c_destroy(psb_intel_output->ddc_bus);
+
+/* failed_ddc: */
+
+ drm_encoder_cleanup(encoder);
+ drm_connector_cleanup(connector);
+ kfree(connector);
+}
+
diff --git a/drivers/staging/gma500/psb_2d.c b/drivers/staging/gma500/psb_2d.c
index e4cae5d..0bd834c 100644
--- a/drivers/staging/gma500/psb_2d.c
+++ b/drivers/staging/gma500/psb_2d.c
@@ -40,7 +40,6 @@
#include "psb_reg.h"
#include "psb_drv.h"
#include "psb_fb.h"
-#include "psb_sgx.h"
void psb_spank(struct drm_psb_private *dev_priv)
{
@@ -85,7 +84,7 @@
/* FIXME: Remember if we expose the 2D engine to the DRM we need to serialize
it with console use */
-static int psbfb_2d_submit(struct drm_psb_private *dev_priv, uint32_t *cmdbuf,
+int psbfb_2d_submit(struct drm_psb_private *dev_priv, uint32_t *cmdbuf,
unsigned size)
{
int ret = 0;
@@ -161,7 +160,7 @@
if (!fb)
return;
- offset = psbfb->offset;
+ offset = psbfb->gtt->offset;
stride = fb->pitch;
switch (fb->depth) {
@@ -304,7 +303,7 @@
if (!fb)
return;
- offset = psbfb->offset;
+ offset = psbfb->gtt->offset;
stride = fb->pitch;
switch (fb->depth) {
@@ -344,7 +343,7 @@
if (unlikely(info->state != FBINFO_STATE_RUNNING))
return;
- if (1 || (info->flags & FBINFO_HWACCEL_DISABLED))
+ if (info->flags & FBINFO_HWACCEL_DISABLED)
return cfb_copyarea(info, region);
/* psb_check_power_state(dev, PSB_DEVICE_SGX); */
diff --git a/drivers/staging/gma500/psb_bl.c b/drivers/staging/gma500/psb_bl.c
index 70c17b3..5dffc71 100644
--- a/drivers/staging/gma500/psb_bl.c
+++ b/drivers/staging/gma500/psb_bl.c
@@ -33,7 +33,6 @@
#define BLC_PWM_FREQ_CALC_CONSTANT 32
#define MHz 1000000
#define BRIGHTNESS_MIN_LEVEL 1
-#define BRIGHTNESS_MAX_LEVEL 100
#define BRIGHTNESS_MASK 0xFF
#define BLC_POLARITY_NORMAL 0
#define BLC_POLARITY_INVERSE 1
@@ -59,15 +58,57 @@
DRM_DEBUG_DRIVER("backlight level set to %d\n", level);
- /* Perform value bounds checking */
- if (level < BRIGHTNESS_MIN_LEVEL)
- level = BRIGHTNESS_MIN_LEVEL;
+ /* Percentage 1-100% being valid */
+ if (level < 1)
+ level = 1;
psb_intel_lvds_set_brightness(dev, level);
psb_brightness = level;
return 0;
}
+int mrst_set_brightness(struct backlight_device *bd)
+{
+ struct drm_device *dev = bl_get_data(psb_backlight_device);
+ struct drm_psb_private *dev_priv = dev->dev_private;
+ int level = bd->props.brightness;
+ u32 blc_pwm_ctl;
+ u32 max_pwm_blc;
+
+ DRM_DEBUG_DRIVER("backlight level set to %d\n", level);
+
+ /* Percentage 1-100% being valid */
+ if (level < 1)
+ level = 1;
+
+ if (gma_power_begin(dev, 0)) {
+ /* Calculate and set the brightness value */
+ max_pwm_blc = REG_READ(BLC_PWM_CTL) >> 16;
+ blc_pwm_ctl = level * max_pwm_blc / 100;
+
+ /* Adjust the backlight level with the percent in
+ * dev_priv->blc_adj1;
+ */
+ blc_pwm_ctl = blc_pwm_ctl * dev_priv->blc_adj1;
+ blc_pwm_ctl = blc_pwm_ctl / 100;
+
+ /* Adjust the backlight level with the percent in
+ * dev_priv->blc_adj2;
+ */
+ blc_pwm_ctl = blc_pwm_ctl * dev_priv->blc_adj2;
+ blc_pwm_ctl = blc_pwm_ctl / 100;
+
+ if (blc_pol == BLC_POLARITY_INVERSE)
+ blc_pwm_ctl = max_pwm_blc - blc_pwm_ctl;
+ /* force PWM bit on */
+ REG_WRITE(BLC_PWM_CTL2, (0x80000000 | REG_READ(BLC_PWM_CTL2)));
+ REG_WRITE(BLC_PWM_CTL, (max_pwm_blc << 16) | blc_pwm_ctl);
+ gma_power_end(dev);
+ }
+ psb_brightness = level;
+ return 0;
+}
+
int psb_get_brightness(struct backlight_device *bd)
{
DRM_DEBUG_DRIVER("brightness = 0x%x\n", psb_brightness);
@@ -85,24 +126,33 @@
static int device_backlight_init(struct drm_device *dev)
{
+ struct drm_psb_private *dev_priv = dev->dev_private;
unsigned long core_clock;
/* u32 bl_max_freq; */
/* unsigned long value; */
u16 bl_max_freq;
uint32_t value;
uint32_t blc_pwm_precision_factor;
- struct drm_psb_private *dev_priv = dev->dev_private;
- /* get bl_max_freq and pol from dev_priv*/
- if (!dev_priv->lvds_bl) {
- DRM_ERROR("Has no valid LVDS backlight info\n");
- return 1;
+ if (IS_MRST(dev)) {
+ dev_priv->blc_adj1 = BLC_ADJUSTMENT_MAX;
+ dev_priv->blc_adj2 = BLC_ADJUSTMENT_MAX;
+ bl_max_freq = 256;
+ /* this needs to be set elsewhere */
+ blc_pol = BLC_POLARITY_NORMAL;
+ blc_pwm_precision_factor = BLC_PWM_PRECISION_FACTOR;
+ } else {
+ /* get bl_max_freq and pol from dev_priv*/
+ if (!dev_priv->lvds_bl) {
+ DRM_ERROR("Has no valid LVDS backlight info\n");
+ return 1;
+ }
+ bl_max_freq = dev_priv->lvds_bl->freq;
+ blc_pol = dev_priv->lvds_bl->pol;
+ blc_pwm_precision_factor = PSB_BLC_PWM_PRECISION_FACTOR;
+ blc_brightnesscmd = dev_priv->lvds_bl->brightnesscmd;
+ blc_type = dev_priv->lvds_bl->type;
}
- bl_max_freq = dev_priv->lvds_bl->freq;
- blc_pol = dev_priv->lvds_bl->pol;
- blc_pwm_precision_factor = PSB_BLC_PWM_PRECISION_FACTOR;
- blc_brightnesscmd = dev_priv->lvds_bl->brightnesscmd;
- blc_type = dev_priv->lvds_bl->type;
core_clock = dev_priv->core_freq;
@@ -111,20 +161,27 @@
value /= bl_max_freq;
value /= blc_pwm_precision_factor;
- if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND,
- OSPM_UHB_ONLY_IF_ON)) {
- /* Check: may be MFLD only */
- if (
- value > (unsigned long long)PSB_BLC_MAX_PWM_REG_FREQ ||
- value < (unsigned long long)PSB_BLC_MIN_PWM_REG_FREQ)
- return 2;
- else {
- value &= PSB_BACKLIGHT_PWM_POLARITY_BIT_CLEAR;
- REG_WRITE(BLC_PWM_CTL,
- (value << PSB_BACKLIGHT_PWM_CTL_SHIFT) |
- (value));
+ if (gma_power_begin(dev, false)) {
+ if (IS_MRST(dev)) {
+ if (value > (unsigned long long)MRST_BLC_MAX_PWM_REG_FREQ)
+ return 2;
+ else {
+ REG_WRITE(BLC_PWM_CTL2,
+ (0x80000000 | REG_READ(BLC_PWM_CTL2)));
+ REG_WRITE(BLC_PWM_CTL, value | (value << 16));
+ }
+ } else {
+ if (value > (unsigned long long)PSB_BLC_MAX_PWM_REG_FREQ ||
+ value < (unsigned long long)PSB_BLC_MIN_PWM_REG_FREQ)
+ return 2;
+ else {
+ value &= PSB_BACKLIGHT_PWM_POLARITY_BIT_CLEAR;
+ REG_WRITE(BLC_PWM_CTL,
+ (value << PSB_BACKLIGHT_PWM_CTL_SHIFT) |
+ (value));
+ }
}
- ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
+ gma_power_end(dev);
}
return 0;
}
@@ -136,7 +193,8 @@
struct backlight_properties props;
memset(&props, 0, sizeof(struct backlight_properties));
- props.max_brightness = BRIGHTNESS_MAX_LEVEL;
+ props.max_brightness = 100;
+ props.type = BACKLIGHT_PLATFORM;
psb_backlight_device = backlight_device_register("psb-bl", NULL,
(void *)dev, &psb_ops, &props);
@@ -147,8 +205,8 @@
if (ret < 0)
return ret;
- psb_backlight_device->props.brightness = BRIGHTNESS_MAX_LEVEL;
- psb_backlight_device->props.max_brightness = BRIGHTNESS_MAX_LEVEL;
+ psb_backlight_device->props.brightness = 100;
+ psb_backlight_device->props.max_brightness = 100;
backlight_update_status(psb_backlight_device);
#endif
return 0;
diff --git a/drivers/staging/gma500/psb_buffer.c b/drivers/staging/gma500/psb_buffer.c
deleted file mode 100644
index 3077f6a..0000000
--- a/drivers/staging/gma500/psb_buffer.c
+++ /dev/null
@@ -1,450 +0,0 @@
-/**************************************************************************
- * Copyright (c) 2007, Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
- *
- **************************************************************************/
-/*
- * Authors: Thomas Hellstrom <thomas-at-tungstengraphics.com>
- */
-#include "ttm/ttm_placement.h"
-#include "ttm/ttm_execbuf_util.h"
-#include "psb_ttm_fence_api.h"
-#include <drm/drmP.h>
-#include "psb_drv.h"
-
-#define DRM_MEM_TTM 26
-
-struct drm_psb_ttm_backend {
- struct ttm_backend base;
- struct page **pages;
- unsigned int desired_tile_stride;
- unsigned int hw_tile_stride;
- int mem_type;
- unsigned long offset;
- unsigned long num_pages;
-};
-
-/*
- * MSVDX/TOPAZ GPU virtual space looks like this
- * (We currently use only one MMU context).
- * PSB_MEM_MMU_START: from 0x00000000~0xe000000, for generic buffers
- * TTM_PL_CI: from 0xe0000000+half GTT space, for camear/video buffer sharing
- * TTM_PL_RAR: from TTM_PL_CI+CI size, for RAR/video buffer sharing
- * TTM_PL_TT: from TTM_PL_RAR+RAR size, for buffers need to mapping into GTT
- */
-static int psb_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
- struct ttm_mem_type_manager *man)
-{
-
- struct drm_psb_private *dev_priv =
- container_of(bdev, struct drm_psb_private, bdev);
- struct psb_gtt *pg = dev_priv->pg;
-
- switch (type) {
- case TTM_PL_SYSTEM:
- man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
- man->available_caching = TTM_PL_FLAG_CACHED |
- TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
- man->default_caching = TTM_PL_FLAG_CACHED;
- break;
- case DRM_PSB_MEM_MMU:
- man->func = &ttm_bo_manager_func;
- man->flags = TTM_MEMTYPE_FLAG_MAPPABLE |
- TTM_MEMTYPE_FLAG_CMA;
- man->gpu_offset = PSB_MEM_MMU_START;
- man->available_caching = TTM_PL_FLAG_CACHED |
- TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
- man->default_caching = TTM_PL_FLAG_WC;
- break;
- case TTM_PL_CI:
- man->func = &ttm_bo_manager_func;
- man->flags = TTM_MEMTYPE_FLAG_MAPPABLE |
- TTM_MEMTYPE_FLAG_FIXED;
- man->gpu_offset = pg->mmu_gatt_start + (pg->ci_start);
- man->available_caching = TTM_PL_FLAG_UNCACHED;
- man->default_caching = TTM_PL_FLAG_UNCACHED;
- break;
- case TTM_PL_RAR: /* Unmappable RAR memory */
- man->func = &ttm_bo_manager_func;
- man->flags = TTM_MEMTYPE_FLAG_MAPPABLE |
- TTM_MEMTYPE_FLAG_FIXED;
- man->available_caching = TTM_PL_FLAG_UNCACHED;
- man->default_caching = TTM_PL_FLAG_UNCACHED;
- man->gpu_offset = pg->mmu_gatt_start + (pg->rar_start);
- break;
- case TTM_PL_TT: /* Mappable GATT memory */
- man->func = &ttm_bo_manager_func;
-#ifdef PSB_WORKING_HOST_MMU_ACCESS
- man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
-#else
- man->flags = TTM_MEMTYPE_FLAG_MAPPABLE |
- TTM_MEMTYPE_FLAG_CMA;
-#endif
- man->available_caching = TTM_PL_FLAG_CACHED |
- TTM_PL_FLAG_UNCACHED | TTM_PL_FLAG_WC;
- man->default_caching = TTM_PL_FLAG_WC;
- man->gpu_offset = pg->mmu_gatt_start +
- (pg->rar_start + dev_priv->rar_region_size);
- break;
- default:
- DRM_ERROR("Unsupported memory type %u\n", (unsigned) type);
- return -EINVAL;
- }
- return 0;
-}
-
-
-static void psb_evict_mask(struct ttm_buffer_object *bo,
- struct ttm_placement *placement)
-{
- static uint32_t cur_placement;
-
- cur_placement = bo->mem.placement & ~TTM_PL_MASK_MEM;
- cur_placement |= TTM_PL_FLAG_SYSTEM;
-
- placement->fpfn = 0;
- placement->lpfn = 0;
- placement->num_placement = 1;
- placement->placement = &cur_placement;
- placement->num_busy_placement = 0;
- placement->busy_placement = NULL;
-
- /* all buffers evicted to system memory */
- /* return cur_placement | TTM_PL_FLAG_SYSTEM; */
-}
-
-static int psb_invalidate_caches(struct ttm_bo_device *bdev,
- uint32_t placement)
-{
- return 0;
-}
-
-static int psb_move_blit(struct ttm_buffer_object *bo,
- bool evict, bool no_wait,
- struct ttm_mem_reg *new_mem)
-{
- BUG();
- return 0;
-}
-
-/*
- * Flip destination ttm into GATT,
- * then blit and subsequently move out again.
- */
-
-static int psb_move_flip(struct ttm_buffer_object *bo,
- bool evict, bool interruptible, bool no_wait,
- struct ttm_mem_reg *new_mem)
-{
- /*struct ttm_bo_device *bdev = bo->bdev;*/
- struct ttm_mem_reg tmp_mem;
- int ret;
- struct ttm_placement placement;
- uint32_t flags = TTM_PL_FLAG_TT;
-
- tmp_mem = *new_mem;
- tmp_mem.mm_node = NULL;
-
- placement.fpfn = 0;
- placement.lpfn = 0;
- placement.num_placement = 1;
- placement.placement = &flags;
- placement.num_busy_placement = 0; /* FIXME */
- placement.busy_placement = NULL;
-
- ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, interruptible,
- false, no_wait);
- if (ret)
- return ret;
- ret = ttm_tt_bind(bo->ttm, &tmp_mem);
- if (ret)
- goto out_cleanup;
- ret = psb_move_blit(bo, true, no_wait, &tmp_mem);
- if (ret)
- goto out_cleanup;
-
- ret = ttm_bo_move_ttm(bo, evict, false, no_wait, new_mem);
-out_cleanup:
- if (tmp_mem.mm_node) {
- drm_mm_put_block(tmp_mem.mm_node);
- tmp_mem.mm_node = NULL;
- }
- return ret;
-}
-
-static int psb_move(struct ttm_buffer_object *bo,
- bool evict, bool interruptible, bool no_wait_reserve,
- bool no_wait, struct ttm_mem_reg *new_mem)
-{
- struct ttm_mem_reg *old_mem = &bo->mem;
-
- if ((old_mem->mem_type == TTM_PL_RAR) ||
- (new_mem->mem_type == TTM_PL_RAR)) {
- if (old_mem->mm_node) {
- spin_lock(&bo->glob->lru_lock);
- drm_mm_put_block(old_mem->mm_node);
- spin_unlock(&bo->glob->lru_lock);
- }
- old_mem->mm_node = NULL;
- *old_mem = *new_mem;
- } else if (old_mem->mem_type == TTM_PL_SYSTEM) {
- return ttm_bo_move_memcpy(bo, evict, false, no_wait, new_mem);
- } else if (new_mem->mem_type == TTM_PL_SYSTEM) {
- int ret = psb_move_flip(bo, evict, interruptible,
- no_wait, new_mem);
- if (unlikely(ret != 0)) {
- if (ret == -ERESTART)
- return ret;
- else
- return ttm_bo_move_memcpy(bo, evict, false,
- no_wait, new_mem);
- }
- } else {
- if (psb_move_blit(bo, evict, no_wait, new_mem))
- return ttm_bo_move_memcpy(bo, evict, false, no_wait,
- new_mem);
- }
- return 0;
-}
-
-static int drm_psb_tbe_populate(struct ttm_backend *backend,
- unsigned long num_pages,
- struct page **pages,
- struct page *dummy_read_page,
- dma_addr_t *dma_addrs)
-{
- struct drm_psb_ttm_backend *psb_be =
- container_of(backend, struct drm_psb_ttm_backend, base);
-
- psb_be->pages = pages;
- return 0;
-}
-
-static int drm_psb_tbe_unbind(struct ttm_backend *backend)
-{
- struct ttm_bo_device *bdev = backend->bdev;
- struct drm_psb_private *dev_priv =
- container_of(bdev, struct drm_psb_private, bdev);
- struct drm_psb_ttm_backend *psb_be =
- container_of(backend, struct drm_psb_ttm_backend, base);
- struct psb_mmu_pd *pd = psb_mmu_get_default_pd(dev_priv->mmu);
- /* struct ttm_mem_type_manager *man = &bdev->man[psb_be->mem_type]; */
-
- if (psb_be->mem_type == TTM_PL_TT) {
- uint32_t gatt_p_offset =
- (psb_be->offset - dev_priv->pg->mmu_gatt_start)
- >> PAGE_SHIFT;
-
- (void) psb_gtt_remove_pages(dev_priv->pg, gatt_p_offset,
- psb_be->num_pages,
- psb_be->desired_tile_stride,
- psb_be->hw_tile_stride, 0);
- }
-
- psb_mmu_remove_pages(pd, psb_be->offset,
- psb_be->num_pages,
- psb_be->desired_tile_stride,
- psb_be->hw_tile_stride);
-
- return 0;
-}
-
-static int drm_psb_tbe_bind(struct ttm_backend *backend,
- struct ttm_mem_reg *bo_mem)
-{
- struct ttm_bo_device *bdev = backend->bdev;
- struct drm_psb_private *dev_priv =
- container_of(bdev, struct drm_psb_private, bdev);
- struct drm_psb_ttm_backend *psb_be =
- container_of(backend, struct drm_psb_ttm_backend, base);
- struct psb_mmu_pd *pd = psb_mmu_get_default_pd(dev_priv->mmu);
- struct ttm_mem_type_manager *man = &bdev->man[bo_mem->mem_type];
- struct drm_mm_node *mm_node = bo_mem->mm_node;
- int type;
- int ret = 0;
-
- psb_be->mem_type = bo_mem->mem_type;
- psb_be->num_pages = bo_mem->num_pages;
- psb_be->desired_tile_stride = 0;
- psb_be->hw_tile_stride = 0;
- psb_be->offset = (mm_node->start << PAGE_SHIFT) +
- man->gpu_offset;
-
- type =
- (bo_mem->
- placement & TTM_PL_FLAG_CACHED) ? PSB_MMU_CACHED_MEMORY : 0;
-
- if (psb_be->mem_type == TTM_PL_TT) {
- uint32_t gatt_p_offset =
- (psb_be->offset - dev_priv->pg->mmu_gatt_start)
- >> PAGE_SHIFT;
-
- ret = psb_gtt_insert_pages(dev_priv->pg, psb_be->pages,
- gatt_p_offset,
- psb_be->num_pages,
- psb_be->desired_tile_stride,
- psb_be->hw_tile_stride, type);
- }
-
- ret = psb_mmu_insert_pages(pd, psb_be->pages,
- psb_be->offset, psb_be->num_pages,
- psb_be->desired_tile_stride,
- psb_be->hw_tile_stride, type);
- if (ret)
- goto out_err;
-
- return 0;
-out_err:
- drm_psb_tbe_unbind(backend);
- return ret;
-
-}
-
-static void drm_psb_tbe_clear(struct ttm_backend *backend)
-{
- struct drm_psb_ttm_backend *psb_be =
- container_of(backend, struct drm_psb_ttm_backend, base);
-
- psb_be->pages = NULL;
- return;
-}
-
-static void drm_psb_tbe_destroy(struct ttm_backend *backend)
-{
- struct drm_psb_ttm_backend *psb_be =
- container_of(backend, struct drm_psb_ttm_backend, base);
-
- if (backend)
- kfree(psb_be);
-}
-
-static struct ttm_backend_func psb_ttm_backend = {
- .populate = drm_psb_tbe_populate,
- .clear = drm_psb_tbe_clear,
- .bind = drm_psb_tbe_bind,
- .unbind = drm_psb_tbe_unbind,
- .destroy = drm_psb_tbe_destroy,
-};
-
-static struct ttm_backend *drm_psb_tbe_init(struct ttm_bo_device *bdev)
-{
- struct drm_psb_ttm_backend *psb_be;
-
- psb_be = kzalloc(sizeof(*psb_be), GFP_KERNEL);
- if (!psb_be)
- return NULL;
- psb_be->pages = NULL;
- psb_be->base.func = &psb_ttm_backend;
- psb_be->base.bdev = bdev;
- return &psb_be->base;
-}
-
-static int psb_ttm_io_mem_reserve(struct ttm_bo_device *bdev,
- struct ttm_mem_reg *mem)
-{
- struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
- struct drm_psb_private *dev_priv =
- container_of(bdev, struct drm_psb_private, bdev);
- struct psb_gtt *pg = dev_priv->pg;
- struct drm_mm_node *mm_node = mem->mm_node;
-
- mem->bus.addr = NULL;
- mem->bus.offset = 0;
- mem->bus.size = mem->num_pages << PAGE_SHIFT;
- mem->bus.base = 0;
- mem->bus.is_iomem = false;
- if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
- return -EINVAL;
- switch (mem->mem_type) {
- case TTM_PL_SYSTEM:
- /* system memory */
- return 0;
- case TTM_PL_TT:
- mem->bus.offset = mm_node->start << PAGE_SHIFT;
- mem->bus.base = pg->gatt_start;
- mem->bus.is_iomem = false;
- /* Don't know whether it is IO_MEM, this flag
- used in vm_fault handle */
- break;
- case DRM_PSB_MEM_MMU:
- mem->bus.offset = mm_node->start << PAGE_SHIFT;
- mem->bus.base = 0x00000000;
- break;
- case TTM_PL_CI:
- mem->bus.offset = mm_node->start << PAGE_SHIFT;
- mem->bus.base = dev_priv->ci_region_start;;
- mem->bus.is_iomem = true;
- break;
- case TTM_PL_RAR:
- mem->bus.offset = mm_node->start << PAGE_SHIFT;
- mem->bus.base = dev_priv->rar_region_start;;
- mem->bus.is_iomem = true;
- break;
- default:
- return -EINVAL;
- }
- return 0;
-}
-
-static void psb_ttm_io_mem_free(struct ttm_bo_device *bdev,
- struct ttm_mem_reg *mem)
-{
-}
-
-/*
- * Use this memory type priority if no eviction is needed.
- */
-/*
-static uint32_t psb_mem_prios[] = {
- TTM_PL_CI,
- TTM_PL_RAR,
- TTM_PL_TT,
- DRM_PSB_MEM_MMU,
- TTM_PL_SYSTEM
-};
-*/
-/*
- * Use this memory type priority if need to evict.
- */
-/*
-static uint32_t psb_busy_prios[] = {
- TTM_PL_TT,
- TTM_PL_CI,
- TTM_PL_RAR,
- DRM_PSB_MEM_MMU,
- TTM_PL_SYSTEM
-};
-*/
-struct ttm_bo_driver psb_ttm_bo_driver = {
-/*
- .mem_type_prio = psb_mem_prios,
- .mem_busy_prio = psb_busy_prios,
- .num_mem_type_prio = ARRAY_SIZE(psb_mem_prios),
- .num_mem_busy_prio = ARRAY_SIZE(psb_busy_prios),
-*/
- .create_ttm_backend_entry = &drm_psb_tbe_init,
- .invalidate_caches = &psb_invalidate_caches,
- .init_mem_type = &psb_init_mem_type,
- .evict_flags = &psb_evict_mask,
- .move = &psb_move,
- .verify_access = &psb_verify_access,
- .sync_obj_signaled = &ttm_fence_sync_obj_signaled,
- .sync_obj_wait = &ttm_fence_sync_obj_wait,
- .sync_obj_flush = &ttm_fence_sync_obj_flush,
- .sync_obj_unref = &ttm_fence_sync_obj_unref,
- .sync_obj_ref = &ttm_fence_sync_obj_ref,
- .io_mem_reserve = &psb_ttm_io_mem_reserve,
- .io_mem_free = &psb_ttm_io_mem_free
-};
diff --git a/drivers/staging/gma500/psb_drm.h b/drivers/staging/gma500/psb_drm.h
index a339406..49ffdd5 100644
--- a/drivers/staging/gma500/psb_drm.h
+++ b/drivers/staging/gma500/psb_drm.h
@@ -28,9 +28,6 @@
#include "drm_mode.h"
#endif
-#include "psb_ttm_fence_user.h"
-#include "psb_ttm_placement_user.h"
-
#define DRM_PSB_SAREA_MAJOR 0
#define DRM_PSB_SAREA_MINOR 2
#define PSB_FIXED_SHIFT 16
@@ -41,15 +38,6 @@
* Public memory types.
*/
-#define DRM_PSB_MEM_MMU TTM_PL_PRIV1
-#define DRM_PSB_FLAG_MEM_MMU TTM_PL_FLAG_PRIV1
-
-#define TTM_PL_CI TTM_PL_PRIV0
-#define TTM_PL_FLAG_CI TTM_PL_FLAG_PRIV0
-
-#define TTM_PL_RAR TTM_PL_PRIV2
-#define TTM_PL_FLAG_RAR TTM_PL_FLAG_PRIV2
-
typedef s32 psb_fixed;
typedef u32 psb_ufixed;
@@ -112,111 +100,12 @@
u32 num_active_scanouts;
};
-#define PSB_RELOC_MAGIC 0x67676767
-#define PSB_RELOC_SHIFT_MASK 0x0000FFFF
-#define PSB_RELOC_SHIFT_SHIFT 0
-#define PSB_RELOC_ALSHIFT_MASK 0xFFFF0000
-#define PSB_RELOC_ALSHIFT_SHIFT 16
-
-#define PSB_RELOC_OP_OFFSET 0 /* Offset of the indicated
- * buffer
- */
-
-struct drm_psb_reloc {
- u32 reloc_op;
- u32 where; /* offset in destination buffer */
- u32 buffer; /* Buffer reloc applies to */
- u32 mask; /* Destination format: */
- u32 shift; /* Destination format: */
- u32 pre_add; /* Destination format: */
- u32 background; /* Destination add */
- u32 dst_buffer; /* Destination buffer. Index into buffer_list */
- u32 arg0; /* Reloc-op dependent */
- u32 arg1;
-};
-
-
#define PSB_GPU_ACCESS_READ (1ULL << 32)
#define PSB_GPU_ACCESS_WRITE (1ULL << 33)
#define PSB_GPU_ACCESS_MASK (PSB_GPU_ACCESS_READ | PSB_GPU_ACCESS_WRITE)
#define PSB_BO_FLAG_COMMAND (1ULL << 52)
-#define PSB_ENGINE_2D 0
-#define PSB_ENGINE_VIDEO 1
-#define LNC_ENGINE_ENCODE 5
-
-/*
- * For this fence class we have a couple of
- * fence types.
- */
-
-#define _PSB_FENCE_EXE_SHIFT 0
-#define _PSB_FENCE_FEEDBACK_SHIFT 4
-
-#define _PSB_FENCE_TYPE_EXE (1 << _PSB_FENCE_EXE_SHIFT)
-#define _PSB_FENCE_TYPE_FEEDBACK (1 << _PSB_FENCE_FEEDBACK_SHIFT)
-
-#define PSB_NUM_ENGINES 6
-
-
-#define PSB_FEEDBACK_OP_VISTEST (1 << 0)
-
-struct drm_psb_extension_rep {
- s32 exists;
- u32 driver_ioctl_offset;
- u32 sarea_offset;
- u32 major;
- u32 minor;
- u32 pl;
-};
-
-#define DRM_PSB_EXT_NAME_LEN 128
-
-union drm_psb_extension_arg {
- char extension[DRM_PSB_EXT_NAME_LEN];
- struct drm_psb_extension_rep rep;
-};
-
-struct psb_validate_req {
- u64 set_flags;
- u64 clear_flags;
- u64 next;
- u64 presumed_gpu_offset;
- u32 buffer_handle;
- u32 presumed_flags;
- u32 group;
- u32 pad64;
-};
-
-struct psb_validate_rep {
- u64 gpu_offset;
- u32 placement;
- u32 fence_type_mask;
-};
-
-#define PSB_USE_PRESUMED (1 << 0)
-
-struct psb_validate_arg {
- int handled;
- int ret;
- union {
- struct psb_validate_req req;
- struct psb_validate_rep rep;
- } d;
-};
-
-
-#define DRM_PSB_FENCE_NO_USER (1 << 0)
-
-struct psb_ttm_fence_rep {
- u32 handle;
- u32 fence_class;
- u32 fence_type;
- u32 signaled_types;
- u32 error;
-};
-
/*
* Feedback components:
*/
@@ -330,17 +219,6 @@
u32 subpicture_disable_mask;
};
-struct psb_gtt_mapping_arg {
- void *hKernelMemInfo;
- u32 offset_pages;
-};
-
-struct drm_psb_getpageaddrs_arg {
- u32 handle;
- unsigned long *page_addrs;
- unsigned long gtt_offset;
-};
-
/* Controlling the kernel modesetting buffers */
#define DRM_PSB_KMS_OFF 0x00
diff --git a/drivers/staging/gma500/psb_drv.c b/drivers/staging/gma500/psb_drv.c
index d01d45e..1c45c11 100644
--- a/drivers/staging/gma500/psb_drv.c
+++ b/drivers/staging/gma500/psb_drv.c
@@ -38,30 +38,29 @@
int drm_psb_debug;
static int drm_psb_trap_pagefaults;
-int drm_psb_disable_vsync = 1;
int drm_psb_no_fb;
-int gfxrtdelay = 2 * 1000;
static int psb_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
MODULE_PARM_DESC(debug, "Enable debug output");
MODULE_PARM_DESC(no_fb, "Disable FBdev");
MODULE_PARM_DESC(trap_pagefaults, "Error and reset on MMU pagefaults");
-MODULE_PARM_DESC(disable_vsync, "Disable vsync interrupts");
-MODULE_PARM_DESC(force_pipeb, "Forces PIPEB to become primary fb");
-MODULE_PARM_DESC(ta_mem_size, "TA memory size in kiB");
-MODULE_PARM_DESC(ospm, "switch for ospm support");
-MODULE_PARM_DESC(rtpm, "Specifies Runtime PM delay for GFX");
-MODULE_PARM_DESC(hdmi_edid, "EDID info for HDMI monitor");
module_param_named(debug, drm_psb_debug, int, 0600);
module_param_named(no_fb, drm_psb_no_fb, int, 0600);
module_param_named(trap_pagefaults, drm_psb_trap_pagefaults, int, 0600);
-module_param_named(rtpm, gfxrtdelay, int, 0600);
static struct pci_device_id pciidlist[] = {
{ 0x8086, 0x8108, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PSB_8108 },
{ 0x8086, 0x8109, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_PSB_8109 },
+ { 0x8086, 0x4100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
+ { 0x8086, 0x4101, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
+ { 0x8086, 0x4102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
+ { 0x8086, 0x4103, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
+ { 0x8086, 0x4104, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
+ { 0x8086, 0x4105, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
+ { 0x8086, 0x4106, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
+ { 0x8086, 0x4107, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_MRST_4100},
{ 0, 0, 0}
};
MODULE_DEVICE_TABLE(pci, pciidlist);
@@ -74,10 +73,6 @@
DRM_IO(DRM_PSB_KMS_OFF + DRM_COMMAND_BASE)
#define DRM_IOCTL_PSB_KMS_ON \
DRM_IO(DRM_PSB_KMS_ON + DRM_COMMAND_BASE)
-#define DRM_IOCTL_PSB_VT_LEAVE \
- DRM_IO(DRM_PSB_VT_LEAVE + DRM_COMMAND_BASE)
-#define DRM_IOCTL_PSB_VT_ENTER \
- DRM_IO(DRM_PSB_VT_ENTER + DRM_COMMAND_BASE)
#define DRM_IOCTL_PSB_SIZES \
DRM_IOR(DRM_PSB_SIZES + DRM_COMMAND_BASE, \
struct drm_psb_sizes_arg)
@@ -97,18 +92,6 @@
#define DRM_IOCTL_PSB_REGISTER_RW \
DRM_IOWR(DRM_PSB_REGISTER_RW + DRM_COMMAND_BASE, \
struct drm_psb_register_rw_arg)
-#define DRM_IOCTL_PSB_GTT_MAP \
- DRM_IOWR(DRM_PSB_GTT_MAP + DRM_COMMAND_BASE, \
- struct psb_gtt_mapping_arg)
-#define DRM_IOCTL_PSB_GTT_UNMAP \
- DRM_IOW(DRM_PSB_GTT_UNMAP + DRM_COMMAND_BASE, \
- struct psb_gtt_mapping_arg)
-#define DRM_IOCTL_PSB_GETPAGEADDRS \
- DRM_IOWR(DRM_COMMAND_BASE + DRM_PSB_GETPAGEADDRS,\
- struct drm_psb_getpageaddrs_arg)
-#define DRM_IOCTL_PSB_UPDATE_GUARD \
- DRM_IOWR(DRM_PSB_UPDATE_GUARD + DRM_COMMAND_BASE, \
- uint32_t)
#define DRM_IOCTL_PSB_DPST \
DRM_IOWR(DRM_PSB_DPST + DRM_COMMAND_BASE, \
uint32_t)
@@ -122,74 +105,6 @@
DRM_IOWR(DRM_PSB_GET_PIPE_FROM_CRTC_ID + DRM_COMMAND_BASE, \
struct drm_psb_get_pipe_from_crtc_id_arg)
-/*
- * TTM execbuf extension.
- */
-
-#define DRM_PSB_CMDBUF 0x23
-#define DRM_PSB_SCENE_UNREF 0x24
-#define DRM_IOCTL_PSB_KMS_OFF DRM_IO(DRM_PSB_KMS_OFF + DRM_COMMAND_BASE)
-#define DRM_IOCTL_PSB_KMS_ON DRM_IO(DRM_PSB_KMS_ON + DRM_COMMAND_BASE)
-/*
- * TTM placement user extension.
- */
-
-#define DRM_PSB_PLACEMENT_OFFSET (DRM_PSB_SCENE_UNREF + 1)
-
-#define DRM_PSB_TTM_PL_CREATE (TTM_PL_CREATE + DRM_PSB_PLACEMENT_OFFSET)
-#define DRM_PSB_TTM_PL_REFERENCE (TTM_PL_REFERENCE + DRM_PSB_PLACEMENT_OFFSET)
-#define DRM_PSB_TTM_PL_UNREF (TTM_PL_UNREF + DRM_PSB_PLACEMENT_OFFSET)
-#define DRM_PSB_TTM_PL_SYNCCPU (TTM_PL_SYNCCPU + DRM_PSB_PLACEMENT_OFFSET)
-#define DRM_PSB_TTM_PL_WAITIDLE (TTM_PL_WAITIDLE + DRM_PSB_PLACEMENT_OFFSET)
-#define DRM_PSB_TTM_PL_SETSTATUS (TTM_PL_SETSTATUS + DRM_PSB_PLACEMENT_OFFSET)
-#define DRM_PSB_TTM_PL_CREATE_UB (TTM_PL_CREATE_UB + DRM_PSB_PLACEMENT_OFFSET)
-
-/*
- * TTM fence extension.
- */
-
-#define DRM_PSB_FENCE_OFFSET (DRM_PSB_TTM_PL_CREATE_UB + 1)
-#define DRM_PSB_TTM_FENCE_SIGNALED (TTM_FENCE_SIGNALED + DRM_PSB_FENCE_OFFSET)
-#define DRM_PSB_TTM_FENCE_FINISH (TTM_FENCE_FINISH + DRM_PSB_FENCE_OFFSET)
-#define DRM_PSB_TTM_FENCE_UNREF (TTM_FENCE_UNREF + DRM_PSB_FENCE_OFFSET)
-
-#define DRM_PSB_FLIP (DRM_PSB_TTM_FENCE_UNREF + 1) /*20*/
-
-#define DRM_IOCTL_PSB_TTM_PL_CREATE \
- DRM_IOWR(DRM_COMMAND_BASE + DRM_PSB_TTM_PL_CREATE,\
- union ttm_pl_create_arg)
-#define DRM_IOCTL_PSB_TTM_PL_REFERENCE \
- DRM_IOWR(DRM_COMMAND_BASE + DRM_PSB_TTM_PL_REFERENCE,\
- union ttm_pl_reference_arg)
-#define DRM_IOCTL_PSB_TTM_PL_UNREF \
- DRM_IOW(DRM_COMMAND_BASE + DRM_PSB_TTM_PL_UNREF,\
- struct ttm_pl_reference_req)
-#define DRM_IOCTL_PSB_TTM_PL_SYNCCPU \
- DRM_IOW(DRM_COMMAND_BASE + DRM_PSB_TTM_PL_SYNCCPU,\
- struct ttm_pl_synccpu_arg)
-#define DRM_IOCTL_PSB_TTM_PL_WAITIDLE \
- DRM_IOW(DRM_COMMAND_BASE + DRM_PSB_TTM_PL_WAITIDLE,\
- struct ttm_pl_waitidle_arg)
-#define DRM_IOCTL_PSB_TTM_PL_SETSTATUS \
- DRM_IOWR(DRM_COMMAND_BASE + DRM_PSB_TTM_PL_SETSTATUS,\
- union ttm_pl_setstatus_arg)
-#define DRM_IOCTL_PSB_TTM_PL_CREATE_UB \
- DRM_IOWR(DRM_COMMAND_BASE + DRM_PSB_TTM_PL_CREATE_UB,\
- union ttm_pl_create_ub_arg)
-#define DRM_IOCTL_PSB_TTM_FENCE_SIGNALED \
- DRM_IOWR(DRM_COMMAND_BASE + DRM_PSB_TTM_FENCE_SIGNALED, \
- union ttm_fence_signaled_arg)
-#define DRM_IOCTL_PSB_TTM_FENCE_FINISH \
- DRM_IOWR(DRM_COMMAND_BASE + DRM_PSB_TTM_FENCE_FINISH, \
- union ttm_fence_finish_arg)
-#define DRM_IOCTL_PSB_TTM_FENCE_UNREF \
- DRM_IOW(DRM_COMMAND_BASE + DRM_PSB_TTM_FENCE_UNREF, \
- struct ttm_fence_unref_arg)
-
-static int psb_vt_leave_ioctl(struct drm_device *dev, void *data,
- struct drm_file *file_priv);
-static int psb_vt_enter_ioctl(struct drm_device *dev, void *data,
- struct drm_file *file_priv);
static int psb_sizes_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv);
static int psb_dc_state_ioctl(struct drm_device *dev, void * data,
@@ -218,11 +133,6 @@
PSB_IOCTL_DEF(DRM_IOCTL_PSB_KMS_ON,
psbfb_kms_on_ioctl,
DRM_ROOT_ONLY),
- PSB_IOCTL_DEF(DRM_IOCTL_PSB_VT_LEAVE, psb_vt_leave_ioctl,
- DRM_ROOT_ONLY),
- PSB_IOCTL_DEF(DRM_IOCTL_PSB_VT_ENTER,
- psb_vt_enter_ioctl,
- DRM_ROOT_ONLY),
PSB_IOCTL_DEF(DRM_IOCTL_PSB_SIZES, psb_sizes_ioctl, DRM_AUTH),
PSB_IOCTL_DEF(DRM_IOCTL_PSB_DC_STATE, psb_dc_state_ioctl, DRM_AUTH),
PSB_IOCTL_DEF(DRM_IOCTL_PSB_ADB, psb_adb_ioctl, DRM_AUTH),
@@ -232,92 +142,226 @@
DRM_AUTH),
PSB_IOCTL_DEF(DRM_IOCTL_PSB_REGISTER_RW, psb_register_rw_ioctl,
DRM_AUTH),
- PSB_IOCTL_DEF(DRM_IOCTL_PSB_GTT_MAP,
- psb_gtt_map_meminfo_ioctl,
- DRM_AUTH),
- PSB_IOCTL_DEF(DRM_IOCTL_PSB_GTT_UNMAP,
- psb_gtt_unmap_meminfo_ioctl,
- DRM_AUTH),
- PSB_IOCTL_DEF(DRM_IOCTL_PSB_GETPAGEADDRS,
- psb_getpageaddrs_ioctl,
- DRM_AUTH),
PSB_IOCTL_DEF(DRM_IOCTL_PSB_DPST, psb_dpst_ioctl, DRM_AUTH),
PSB_IOCTL_DEF(DRM_IOCTL_PSB_GAMMA, psb_gamma_ioctl, DRM_AUTH),
PSB_IOCTL_DEF(DRM_IOCTL_PSB_DPST_BL, psb_dpst_bl_ioctl, DRM_AUTH),
PSB_IOCTL_DEF(DRM_IOCTL_PSB_GET_PIPE_FROM_CRTC_ID,
psb_intel_get_pipe_from_crtc_id, 0),
- PSB_IOCTL_DEF(DRM_IOCTL_PSB_TTM_PL_CREATE, psb_pl_create_ioctl,
- DRM_AUTH),
- PSB_IOCTL_DEF(DRM_IOCTL_PSB_TTM_PL_REFERENCE, psb_pl_reference_ioctl,
- DRM_AUTH),
- PSB_IOCTL_DEF(DRM_IOCTL_PSB_TTM_PL_UNREF, psb_pl_unref_ioctl,
- DRM_AUTH),
- PSB_IOCTL_DEF(DRM_IOCTL_PSB_TTM_PL_SYNCCPU, psb_pl_synccpu_ioctl,
- DRM_AUTH),
- PSB_IOCTL_DEF(DRM_IOCTL_PSB_TTM_PL_WAITIDLE, psb_pl_waitidle_ioctl,
- DRM_AUTH),
- PSB_IOCTL_DEF(DRM_IOCTL_PSB_TTM_PL_SETSTATUS, psb_pl_setstatus_ioctl,
- DRM_AUTH),
- PSB_IOCTL_DEF(DRM_IOCTL_PSB_TTM_PL_CREATE_UB, psb_pl_ub_create_ioctl,
- DRM_AUTH),
- PSB_IOCTL_DEF(DRM_IOCTL_PSB_TTM_FENCE_SIGNALED,
- psb_fence_signaled_ioctl, DRM_AUTH),
- PSB_IOCTL_DEF(DRM_IOCTL_PSB_TTM_FENCE_FINISH, psb_fence_finish_ioctl,
- DRM_AUTH),
- PSB_IOCTL_DEF(DRM_IOCTL_PSB_TTM_FENCE_UNREF, psb_fence_unref_ioctl,
- DRM_AUTH),
};
-static void psb_set_uopt(struct drm_psb_uopt *uopt)
-{
- return;
-}
-
static void psb_lastclose(struct drm_device *dev)
{
- struct drm_psb_private *dev_priv =
- (struct drm_psb_private *) dev->dev_private;
-
return;
-
- if (!dev->dev_private)
- return;
-
- mutex_lock(&dev_priv->cmdbuf_mutex);
- if (dev_priv->context.buffers) {
- vfree(dev_priv->context.buffers);
- dev_priv->context.buffers = NULL;
- }
- mutex_unlock(&dev_priv->cmdbuf_mutex);
}
static void psb_do_takedown(struct drm_device *dev)
{
- struct drm_psb_private *dev_priv =
- (struct drm_psb_private *) dev->dev_private;
- struct ttm_bo_device *bdev = &dev_priv->bdev;
+ /* FIXME: do we need to clean up the gtt here ? */
+}
+void mrst_get_fuse_settings(struct drm_device *dev)
+{
+ struct drm_psb_private *dev_priv = dev->dev_private;
+ struct pci_dev *pci_root = pci_get_bus_and_slot(0, 0);
+ uint32_t fuse_value = 0;
+ uint32_t fuse_value_tmp = 0;
- if (dev_priv->have_mem_mmu) {
- ttm_bo_clean_mm(bdev, DRM_PSB_MEM_MMU);
- dev_priv->have_mem_mmu = 0;
+#define FB_REG06 0xD0810600
+#define FB_MIPI_DISABLE (1 << 11)
+#define FB_REG09 0xD0810900
+#define FB_REG09 0xD0810900
+#define FB_SKU_MASK 0x7000
+#define FB_SKU_SHIFT 12
+#define FB_SKU_100 0
+#define FB_SKU_100L 1
+#define FB_SKU_83 2
+ pci_write_config_dword(pci_root, 0xD0, FB_REG06);
+ pci_read_config_dword(pci_root, 0xD4, &fuse_value);
+
+ dev_priv->iLVDS_enable = fuse_value & FB_MIPI_DISABLE;
+
+ DRM_INFO("internal display is %s\n",
+ dev_priv->iLVDS_enable ? "LVDS display" : "MIPI display");
+
+ /*prevent Runtime suspend at start*/
+ if (dev_priv->iLVDS_enable) {
+ dev_priv->is_lvds_on = true;
+ dev_priv->is_mipi_on = false;
+ }
+ else {
+ dev_priv->is_mipi_on = true;
+ dev_priv->is_lvds_on = false;
}
- if (dev_priv->have_tt) {
- ttm_bo_clean_mm(bdev, TTM_PL_TT);
- dev_priv->have_tt = 0;
+ dev_priv->video_device_fuse = fuse_value;
+
+ pci_write_config_dword(pci_root, 0xD0, FB_REG09);
+ pci_read_config_dword(pci_root, 0xD4, &fuse_value);
+
+ DRM_INFO("SKU values is 0x%x. \n", fuse_value);
+ fuse_value_tmp = (fuse_value & FB_SKU_MASK) >> FB_SKU_SHIFT;
+
+ dev_priv->fuse_reg_value = fuse_value;
+
+ switch (fuse_value_tmp) {
+ case FB_SKU_100:
+ dev_priv->core_freq = 200;
+ break;
+ case FB_SKU_100L:
+ dev_priv->core_freq = 100;
+ break;
+ case FB_SKU_83:
+ dev_priv->core_freq = 166;
+ break;
+ default:
+ DRM_ERROR("Invalid SKU values, SKU value = 0x%08x\n", fuse_value_tmp);
+ dev_priv->core_freq = 0;
+ }
+ DRM_INFO("LNC core clk is %dMHz.\n", dev_priv->core_freq);
+ pci_dev_put(pci_root);
+}
+
+void mid_get_pci_revID (struct drm_psb_private *dev_priv)
+{
+ uint32_t platform_rev_id = 0;
+ struct pci_dev *pci_gfx_root = pci_get_bus_and_slot(0, PCI_DEVFN(2, 0));
+
+ /*get the revison ID, B0:D2:F0;0x08 */
+ pci_read_config_dword(pci_gfx_root, 0x08, &platform_rev_id);
+ dev_priv->platform_rev_id = (uint8_t) platform_rev_id;
+ pci_dev_put(pci_gfx_root);
+ PSB_DEBUG_ENTRY("platform_rev_id is %x\n", dev_priv->platform_rev_id);
+}
+
+void mrst_get_vbt_data(struct drm_psb_private *dev_priv)
+{
+ struct mrst_vbt *vbt = &dev_priv->vbt_data;
+ u32 platform_config_address;
+ u16 new_size;
+ u8 *vbt_virtual;
+ u8 bpi;
+ u8 number_desc = 0;
+ struct mrst_timing_info *dp_ti = &dev_priv->gct_data.DTD;
+ struct gct_r10_timing_info ti;
+ void *pGCT;
+ struct pci_dev *pci_gfx_root = pci_get_bus_and_slot(0, PCI_DEVFN(2, 0));
+
+ /*get the address of the platform config vbt, B0:D2:F0;0xFC */
+ pci_read_config_dword(pci_gfx_root, 0xFC, &platform_config_address);
+ pci_dev_put(pci_gfx_root);
+ DRM_INFO("drm platform config address is %x\n",
+ platform_config_address);
+
+ /* check for platform config address == 0. */
+ /* this means fw doesn't support vbt */
+
+ if (platform_config_address == 0) {
+ vbt->size = 0;
+ return;
}
- if (dev_priv->have_camera) {
- ttm_bo_clean_mm(bdev, TTM_PL_CI);
- dev_priv->have_camera = 0;
- }
- if (dev_priv->have_rar) {
- ttm_bo_clean_mm(bdev, TTM_PL_RAR);
- dev_priv->have_rar = 0;
- }
+ /* get the virtual address of the vbt */
+ vbt_virtual = ioremap(platform_config_address, sizeof(*vbt));
+ memcpy(vbt, vbt_virtual, sizeof(*vbt));
+ iounmap(vbt_virtual); /* Free virtual address space */
+
+ printk(KERN_ALERT "GCT revision is %x\n", vbt->revision);
+
+ switch (vbt->revision) {
+ case 0:
+ vbt->mrst_gct = NULL;
+ vbt->mrst_gct = \
+ ioremap(platform_config_address + sizeof(*vbt) - 4,
+ vbt->size - sizeof(*vbt) + 4);
+ pGCT = vbt->mrst_gct;
+ bpi = ((struct mrst_gct_v1 *)pGCT)->PD.BootPanelIndex;
+ dev_priv->gct_data.bpi = bpi;
+ dev_priv->gct_data.pt =
+ ((struct mrst_gct_v1 *)pGCT)->PD.PanelType;
+ memcpy(&dev_priv->gct_data.DTD,
+ &((struct mrst_gct_v1 *)pGCT)->panel[bpi].DTD,
+ sizeof(struct mrst_timing_info));
+ dev_priv->gct_data.Panel_Port_Control =
+ ((struct mrst_gct_v1 *)pGCT)->panel[bpi].Panel_Port_Control;
+ dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
+ ((struct mrst_gct_v1 *)pGCT)->panel[bpi].Panel_MIPI_Display_Descriptor;
+ break;
+ case 1:
+ vbt->mrst_gct = NULL;
+ vbt->mrst_gct = \
+ ioremap(platform_config_address + sizeof(*vbt) - 4,
+ vbt->size - sizeof(*vbt) + 4);
+ pGCT = vbt->mrst_gct;
+ bpi = ((struct mrst_gct_v2 *)pGCT)->PD.BootPanelIndex;
+ dev_priv->gct_data.bpi = bpi;
+ dev_priv->gct_data.pt =
+ ((struct mrst_gct_v2 *)pGCT)->PD.PanelType;
+ memcpy(&dev_priv->gct_data.DTD,
+ &((struct mrst_gct_v2 *)pGCT)->panel[bpi].DTD,
+ sizeof(struct mrst_timing_info));
+ dev_priv->gct_data.Panel_Port_Control =
+ ((struct mrst_gct_v2 *)pGCT)->panel[bpi].Panel_Port_Control;
+ dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
+ ((struct mrst_gct_v2 *)pGCT)->panel[bpi].Panel_MIPI_Display_Descriptor;
+ break;
+ case 0x10:
+ /*header definition changed from rev 01 (v2) to rev 10h. */
+ /*so, some values have changed location*/
+ new_size = vbt->checksum; /*checksum contains lo size byte*/
+ /*LSB of mrst_gct contains hi size byte*/
+ new_size |= ((0xff & (unsigned int)vbt->mrst_gct)) << 8;
+
+ vbt->checksum = vbt->size; /*size contains the checksum*/
+ if (new_size > 0xff)
+ vbt->size = 0xff; /*restrict size to 255*/
+ else
+ vbt->size = new_size;
+
+ /* number of descriptors defined in the GCT */
+ number_desc = ((0xff00 & (unsigned int)vbt->mrst_gct)) >> 8;
+ bpi = ((0xff0000 & (unsigned int)vbt->mrst_gct)) >> 16;
+ vbt->mrst_gct = NULL;
+ vbt->mrst_gct = \
+ ioremap(platform_config_address + GCT_R10_HEADER_SIZE,
+ GCT_R10_DISPLAY_DESC_SIZE * number_desc);
+ pGCT = vbt->mrst_gct;
+ pGCT = (u8 *)pGCT + (bpi*GCT_R10_DISPLAY_DESC_SIZE);
+ dev_priv->gct_data.bpi = bpi; /*save boot panel id*/
+
+ /*copy the GCT display timings into a temp structure*/
+ memcpy(&ti, pGCT, sizeof(struct gct_r10_timing_info));
+
+ /*now copy the temp struct into the dev_priv->gct_data*/
+ dp_ti->pixel_clock = ti.pixel_clock;
+ dp_ti->hactive_hi = ti.hactive_hi;
+ dp_ti->hactive_lo = ti.hactive_lo;
+ dp_ti->hblank_hi = ti.hblank_hi;
+ dp_ti->hblank_lo = ti.hblank_lo;
+ dp_ti->hsync_offset_hi = ti.hsync_offset_hi;
+ dp_ti->hsync_offset_lo = ti.hsync_offset_lo;
+ dp_ti->hsync_pulse_width_hi = ti.hsync_pulse_width_hi;
+ dp_ti->hsync_pulse_width_lo = ti.hsync_pulse_width_lo;
+ dp_ti->vactive_hi = ti.vactive_hi;
+ dp_ti->vactive_lo = ti.vactive_lo;
+ dp_ti->vblank_hi = ti.vblank_hi;
+ dp_ti->vblank_lo = ti.vblank_lo;
+ dp_ti->vsync_offset_hi = ti.vsync_offset_hi;
+ dp_ti->vsync_offset_lo = ti.vsync_offset_lo;
+ dp_ti->vsync_pulse_width_hi = ti.vsync_pulse_width_hi;
+ dp_ti->vsync_pulse_width_lo = ti.vsync_pulse_width_lo;
+
+ /*mov the MIPI_Display_Descriptor data from GCT to dev priv*/
+ dev_priv->gct_data.Panel_MIPI_Display_Descriptor =
+ *((u8 *)pGCT + 0x0d);
+ dev_priv->gct_data.Panel_MIPI_Display_Descriptor |=
+ (*((u8 *)pGCT + 0x0e)) << 8;
+ break;
+ default:
+ printk(KERN_ERR "Unknown revision of GCT!\n");
+ vbt->size = 0;
+ }
}
static void psb_get_core_freq(struct drm_device *dev)
@@ -358,36 +402,10 @@
}
}
-#define FB_REG06 0xD0810600
-#define FB_TOPAZ_DISABLE BIT0
-#define FB_MIPI_DISABLE BIT11
-#define FB_REG09 0xD0810900
-#define FB_SKU_MASK (BIT12|BIT13|BIT14)
-#define FB_SKU_SHIFT 12
-#define FB_SKU_100 0
-#define FB_SKU_100L 1
-#define FB_SKU_83 2
-
-bool mid_get_pci_revID(struct drm_psb_private *dev_priv)
-{
- uint32_t platform_rev_id = 0;
- struct pci_dev *pci_gfx_root = pci_get_bus_and_slot(0, PCI_DEVFN(2, 0));
-
- /*get the revison ID, B0:D2:F0;0x08 */
- pci_read_config_dword(pci_gfx_root, 0x08, &platform_rev_id);
- dev_priv->platform_rev_id = (uint8_t) platform_rev_id;
- pci_dev_put(pci_gfx_root);
- PSB_DEBUG_ENTRY("platform_rev_id is %x\n",
- dev_priv->platform_rev_id);
-
- return true;
-}
-
static int psb_do_init(struct drm_device *dev)
{
struct drm_psb_private *dev_priv =
(struct drm_psb_private *) dev->dev_private;
- struct ttm_bo_device *bdev = &dev_priv->bdev;
struct psb_gtt *pg = dev_priv->pg;
uint32_t stolen_gtt;
@@ -396,16 +414,6 @@
int ret = -ENOMEM;
-
- /*
- * Initialize sequence numbers for the different command
- * submission mechanisms.
- */
-
- dev_priv->sequence[PSB_ENGINE_2D] = 0;
- dev_priv->sequence[PSB_ENGINE_VIDEO] = 0;
- dev_priv->sequence[LNC_ENGINE_ENCODE] = 0;
-
if (pg->mmu_gatt_start & 0x0FFFFFFF) {
DRM_ERROR("Gatt must be 256M aligned. This is a bug.\n");
ret = -EINVAL;
@@ -445,6 +453,7 @@
pg->gatt_pages : PSB_TT_PRIV0_PLIMIT;
tt_start = dev_priv->gatt_free_offset - pg->mmu_gatt_start;
tt_pages -= tt_start >> PAGE_SHIFT;
+ /* FIXME: can we kill ta_mem_size ? */
dev_priv->sizes.ta_mem_size = 0;
PSB_WSGX32(0x00000000, PSB_CR_BIF_BANK0);
@@ -453,30 +462,10 @@
PSB_WSGX32(PSB_RSGX32(PSB_CR_BIF_CTRL) | _PSB_MMU_ER_MASK,
PSB_CR_BIF_CTRL);
psb_spank(dev_priv);
-
- PSB_WSGX32(pg->mmu_gatt_start, PSB_CR_BIF_TWOD_REQ_BASE);
- /* TT region managed by TTM. */
- if (!ttm_bo_init_mm(bdev, TTM_PL_TT,
- pg->gatt_pages -
- (pg->ci_start >> PAGE_SHIFT) -
- ((dev_priv->ci_region_size + dev_priv->rar_region_size)
- >> PAGE_SHIFT))) {
+ /* mmu_gatt ?? */
+ PSB_WSGX32(pg->gatt_start, PSB_CR_BIF_TWOD_REQ_BASE);
- dev_priv->have_tt = 1;
- dev_priv->sizes.tt_size =
- (tt_pages << PAGE_SHIFT) / (1024 * 1024) / 2;
- }
-
- if (!ttm_bo_init_mm(bdev,
- DRM_PSB_MEM_MMU,
- PSB_MEM_TT_START >> PAGE_SHIFT)) {
- dev_priv->have_mem_mmu = 1;
- dev_priv->sizes.mmu_size =
- PSB_MEM_TT_START / (1024*1024);
- }
-
- PSB_DEBUG_INIT("Init MSVDX\n");
return 0;
out_err:
psb_do_takedown(dev);
@@ -510,39 +499,19 @@
down_read(&pg->sem);
psb_mmu_remove_pfn_sequence(
- psb_mmu_get_default_pd
- (dev_priv->mmu),
- pg->mmu_gatt_start,
- pg->vram_stolen_size >> PAGE_SHIFT);
- if (pg->ci_stolen_size != 0)
- psb_mmu_remove_pfn_sequence(
- psb_mmu_get_default_pd
- (dev_priv->mmu),
- pg->ci_start,
- pg->ci_stolen_size >> PAGE_SHIFT);
- if (pg->rar_stolen_size != 0)
- psb_mmu_remove_pfn_sequence(
- psb_mmu_get_default_pd
- (dev_priv->mmu),
- pg->rar_start,
- pg->rar_stolen_size >> PAGE_SHIFT);
+ psb_mmu_get_default_pd
+ (dev_priv->mmu),
+ pg->mmu_gatt_start,
+ dev_priv->vram_stolen_size >> PAGE_SHIFT);
up_read(&pg->sem);
psb_mmu_driver_takedown(dev_priv->mmu);
dev_priv->mmu = NULL;
}
- psb_gtt_takedown(dev_priv->pg, 1);
+ psb_gtt_takedown(dev);
if (dev_priv->scratch_page) {
__free_page(dev_priv->scratch_page);
dev_priv->scratch_page = NULL;
}
- if (dev_priv->has_bo_device) {
- ttm_bo_device_release(&dev_priv->bdev);
- dev_priv->has_bo_device = 0;
- }
- if (dev_priv->has_fence_device) {
- ttm_fence_device_release(&dev_priv->fdev);
- dev_priv->has_fence_device = 0;
- }
if (dev_priv->vdc_reg) {
iounmap(dev_priv->vdc_reg);
dev_priv->vdc_reg = NULL;
@@ -552,12 +521,6 @@
dev_priv->sgx_reg = NULL;
}
- if (dev_priv->tdev)
- ttm_object_device_release(&dev_priv->tdev);
-
- if (dev_priv->has_global)
- psb_ttm_global_release(dev_priv);
-
kfree(dev_priv);
dev->dev_private = NULL;
@@ -565,7 +528,7 @@
psb_intel_destroy_bios(dev);
}
- ospm_power_uninit();
+ gma_power_uninit(dev);
return 0;
}
@@ -574,7 +537,6 @@
static int psb_driver_load(struct drm_device *dev, unsigned long chipset)
{
struct drm_psb_private *dev_priv;
- struct ttm_bo_device *bdev;
unsigned long resource_start;
struct psb_gtt *pg;
unsigned long irqflags;
@@ -584,39 +546,16 @@
dev_priv = kzalloc(sizeof(*dev_priv), GFP_KERNEL);
if (dev_priv == NULL)
return -ENOMEM;
- INIT_LIST_HEAD(&dev_priv->video_ctx);
- dev_priv->num_pipe = 2;
-
+ if (IS_MRST(dev))
+ dev_priv->num_pipe = 1;
+ else
+ dev_priv->num_pipe = 2;
dev_priv->dev = dev;
- bdev = &dev_priv->bdev;
-
- ret = psb_ttm_global_init(dev_priv);
- if (unlikely(ret != 0))
- goto out_err;
- dev_priv->has_global = 1;
-
- dev_priv->tdev = ttm_object_device_init
- (dev_priv->mem_global_ref.object, PSB_OBJECT_HASH_ORDER);
- if (unlikely(dev_priv->tdev == NULL))
- goto out_err;
-
- mutex_init(&dev_priv->temp_mem);
- mutex_init(&dev_priv->cmdbuf_mutex);
- mutex_init(&dev_priv->reset_mutex);
- INIT_LIST_HEAD(&dev_priv->context.validate_list);
- INIT_LIST_HEAD(&dev_priv->context.kern_validate_list);
-
-/* mutex_init(&dev_priv->dsr_mutex); */
-
- spin_lock_init(&dev_priv->reloc_lock);
-
- DRM_INIT_WAITQUEUE(&dev_priv->rel_mapped_queue);
dev->dev_private = (void *) dev_priv;
dev_priv->chipset = chipset;
- psb_set_uopt(&dev_priv->uopt);
PSB_DEBUG_INIT("Mapping MMIO\n");
resource_start = pci_resource_start(dev->pdev, PSB_MMIO_RESOURCE);
@@ -626,34 +565,28 @@
if (!dev_priv->vdc_reg)
goto out_err;
- dev_priv->sgx_reg = ioremap(resource_start + PSB_SGX_OFFSET,
+ if (IS_MRST(dev))
+ dev_priv->sgx_reg = ioremap(resource_start + MRST_SGX_OFFSET,
+ PSB_SGX_SIZE);
+ else
+ dev_priv->sgx_reg = ioremap(resource_start + PSB_SGX_OFFSET,
PSB_SGX_SIZE);
if (!dev_priv->sgx_reg)
goto out_err;
- psb_get_core_freq(dev);
- psb_intel_opregion_init(dev);
- psb_intel_init_bios(dev);
-
- PSB_DEBUG_INIT("Init TTM fence and BO driver\n");
+ if (IS_MRST(dev)) {
+ mrst_get_fuse_settings(dev);
+ mrst_get_vbt_data(dev_priv);
+ mid_get_pci_revID(dev_priv);
+ } else {
+ psb_get_core_freq(dev);
+ psb_intel_opregion_init(dev);
+ psb_intel_init_bios(dev);
+ }
/* Init OSPM support */
- ospm_power_init(dev);
-
- ret = psb_ttm_fence_device_init(&dev_priv->fdev);
- if (unlikely(ret != 0))
- goto out_err;
-
- dev_priv->has_fence_device = 1;
- ret = ttm_bo_device_init(bdev,
- dev_priv->bo_global_ref.ref.object,
- &psb_ttm_bo_driver,
- DRM_PSB_FILE_PAGE_OFFSET, false);
- if (unlikely(ret != 0))
- goto out_err;
- dev_priv->has_bo_device = 1;
- ttm_lock_init(&dev_priv->ttm_lock);
+ gma_power_init(dev);
ret = -ENOMEM;
@@ -663,15 +596,7 @@
set_pages_uc(dev_priv->scratch_page, 1);
- dev_priv->pg = psb_gtt_alloc(dev);
- if (!dev_priv->pg)
- goto out_err;
-
- ret = psb_gtt_init(dev_priv->pg, 0);
- if (ret)
- goto out_err;
-
- ret = psb_gtt_mm_init(dev_priv->pg);
+ ret = psb_gtt_init(dev, 0);
if (ret)
goto out_err;
@@ -686,40 +611,6 @@
tt_pages = (pg->gatt_pages < PSB_TT_PRIV0_PLIMIT) ?
(pg->gatt_pages) : PSB_TT_PRIV0_PLIMIT;
- /* CI/RAR use the lower half of TT. */
- pg->ci_start = (tt_pages / 2) << PAGE_SHIFT;
- pg->rar_start = pg->ci_start + pg->ci_stolen_size;
-
-
- /*
- * Make MSVDX/TOPAZ MMU aware of the CI stolen memory area.
- */
- if (dev_priv->pg->ci_stolen_size != 0) {
- down_read(&pg->sem);
- ret = psb_mmu_insert_pfn_sequence(psb_mmu_get_default_pd
- (dev_priv->mmu),
- dev_priv->ci_region_start >> PAGE_SHIFT,
- pg->mmu_gatt_start + pg->ci_start,
- pg->ci_stolen_size >> PAGE_SHIFT, 0);
- up_read(&pg->sem);
- if (ret)
- goto out_err;
- }
-
- /*
- * Make MSVDX/TOPAZ MMU aware of the rar stolen memory area.
- */
- if (dev_priv->pg->rar_stolen_size != 0) {
- down_read(&pg->sem);
- ret = psb_mmu_insert_pfn_sequence(
- psb_mmu_get_default_pd(dev_priv->mmu),
- dev_priv->rar_region_start >> PAGE_SHIFT,
- pg->mmu_gatt_start + pg->rar_start,
- pg->rar_stolen_size >> PAGE_SHIFT, 0);
- up_read(&pg->sem);
- if (ret)
- goto out_err;
- }
dev_priv->pf_pd = psb_mmu_alloc_pd(dev_priv->mmu, 1, 0);
if (!dev_priv->pf_pd)
@@ -728,14 +619,13 @@
psb_mmu_set_pd_context(psb_mmu_get_default_pd(dev_priv->mmu), 0);
psb_mmu_set_pd_context(dev_priv->pf_pd, 1);
- spin_lock_init(&dev_priv->sequence_lock);
-
- PSB_DEBUG_INIT("Begin to init MSVDX/Topaz\n");
-
ret = psb_do_init(dev);
if (ret)
return ret;
+ PSB_WSGX32(0x20000000, PSB_CR_PDS_EXEC_BASE);
+ PSB_WSGX32(0x30000000, PSB_CR_BIF_3D_REQ_BASE);
+
/* igd_opregion_init(&dev_priv->opregion_dev); */
acpi_video_register();
if (dev_priv->lid_state)
@@ -783,11 +673,6 @@
#endif
/*Intel drm driver load is done, continue doing pvr load*/
DRM_DEBUG("Pvr driver load\n");
-
-/* if (PVRCore_Init() < 0)
- goto out_err; */
-/* if (MRSTLFBInit(dev) < 0)
- goto out_err;*/
return 0;
out_err:
psb_driver_unload(dev);
@@ -800,45 +685,6 @@
}
-static int psb_vt_leave_ioctl(struct drm_device *dev, void *data,
- struct drm_file *file_priv)
-{
- struct drm_psb_private *dev_priv = psb_priv(dev);
- struct ttm_bo_device *bdev = &dev_priv->bdev;
- struct ttm_mem_type_manager *man;
- int ret;
-
- ret = ttm_vt_lock(&dev_priv->ttm_lock, 1,
- psb_fpriv(file_priv)->tfile);
- if (unlikely(ret != 0))
- return ret;
-
- ret = ttm_bo_evict_mm(&dev_priv->bdev, TTM_PL_TT);
- if (unlikely(ret != 0))
- goto out_unlock;
-
- man = &bdev->man[TTM_PL_TT];
-
-#if 0 /* What to do with this ? */
- if (unlikely(!drm_mm_clean(&man->manager)))
- DRM_INFO("Warning: GATT was not clean after VT switch.\n");
-#endif
-
- ttm_bo_swapout_all(&dev_priv->bdev);
-
- return 0;
-out_unlock:
- (void) ttm_vt_unlock(&dev_priv->ttm_lock);
- return ret;
-}
-
-static int psb_vt_enter_ioctl(struct drm_device *dev, void *data,
- struct drm_file *file_priv)
-{
- struct drm_psb_private *dev_priv = psb_priv(dev);
- return ttm_vt_unlock(&dev_priv->ttm_lock);
-}
-
static int psb_sizes_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv)
{
@@ -945,13 +791,12 @@
uint32_t y;
uint32_t reg;
- if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND,
- OSPM_UHB_ONLY_IF_ON))
- return 0;
+ if (!gma_power_begin(dev, 0))
+ return -EIO;
reg = PSB_RVDC32(PIPEASRC);
- ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
+ gma_power_end(dev);
/* horizontal is the left 16 bits */
x = reg >> 16;
@@ -1028,13 +873,12 @@
drm_fb = obj_to_fb(obj);
psb_fb = to_psb_fb(drm_fb);
- if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND,
- OSPM_UHB_ONLY_IF_ON)) {
- REG_WRITE(DSPASURF, psb_fb->offset);
+ if (gma_power_begin(dev, 0)) {
+ REG_WRITE(DSPASURF, psb_fb->gtt->offset);
REG_READ(DSPASURF);
- ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
+ gma_power_end(dev);
} else {
- dev_priv->saveDSPASURF = psb_fb->offset;
+ dev_priv->saveDSPASURF = psb_fb->gtt->offset;
}
return 0;
@@ -1107,8 +951,8 @@
struct drm_psb_private *dev_priv = psb_priv(dev);
struct drm_psb_stolen_memory_arg *arg = data;
- arg->base = dev_priv->pg->stolen_base;
- arg->size = dev_priv->pg->vram_stolen_size;
+ arg->base = dev_priv->stolen_base;
+ arg->size = dev_priv->vram_stolen_size;
return 0;
}
@@ -1118,11 +962,10 @@
{
struct drm_psb_private *dev_priv = psb_priv(dev);
struct drm_psb_register_rw_arg *arg = data;
- UHBUsage usage =
- arg->b_force_hw_on ? OSPM_UHB_FORCE_POWER_ON : OSPM_UHB_ONLY_IF_ON;
+ bool usage = arg->b_force_hw_on ? true : false;
if (arg->display_write_mask != 0) {
- if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, usage)) {
+ if (gma_power_begin(dev, usage)) {
if (arg->display_write_mask & REGRWBITS_PFIT_CONTROLS)
PSB_WVDC32(arg->display.pfit_controls,
PFIT_CONTROL);
@@ -1147,7 +990,7 @@
if (arg->display_write_mask & REGRWBITS_VTOTAL_B)
PSB_WVDC32(arg->display.vtotal_b,
VTOTAL_B);
- ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
+ gma_power_end(dev);
} else {
if (arg->display_write_mask & REGRWBITS_PFIT_CONTROLS)
dev_priv->savePFIT_CONTROL =
@@ -1172,7 +1015,7 @@
}
if (arg->display_read_mask != 0) {
- if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, usage)) {
+ if (gma_power_begin(dev, usage)) {
if (arg->display_read_mask &
REGRWBITS_PFIT_CONTROLS)
arg->display.pfit_controls =
@@ -1193,7 +1036,7 @@
arg->display.vtotal_a = PSB_RVDC32(VTOTAL_A);
if (arg->display_read_mask & REGRWBITS_VTOTAL_B)
arg->display.vtotal_b = PSB_RVDC32(VTOTAL_B);
- ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
+ gma_power_end(dev);
} else {
if (arg->display_read_mask &
REGRWBITS_PFIT_CONTROLS)
@@ -1219,7 +1062,7 @@
}
if (arg->overlay_write_mask != 0) {
- if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, usage)) {
+ if (gma_power_begin(dev, usage)) {
if (arg->overlay_write_mask & OV_REGRWBITS_OGAM_ALL) {
PSB_WVDC32(arg->overlay.OGAMC5, OV_OGAMC5);
PSB_WVDC32(arg->overlay.OGAMC4, OV_OGAMC4);
@@ -1270,7 +1113,7 @@
}
}
}
- ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
+ gma_power_end(dev);
} else {
if (arg->overlay_write_mask & OV_REGRWBITS_OGAM_ALL) {
dev_priv->saveOV_OGAMC5 = arg->overlay.OGAMC5;
@@ -1296,7 +1139,7 @@
}
if (arg->overlay_read_mask != 0) {
- if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, usage)) {
+ if (gma_power_begin(dev, usage)) {
if (arg->overlay_read_mask & OV_REGRWBITS_OGAM_ALL) {
arg->overlay.OGAMC5 = PSB_RVDC32(OV_OGAMC5);
arg->overlay.OGAMC4 = PSB_RVDC32(OV_OGAMC4);
@@ -1317,7 +1160,7 @@
arg->overlay.OVADD = PSB_RVDC32(OV_OVADD);
if (arg->overlay_read_mask & OVC_REGRWBITS_OVADD)
arg->overlay.OVADD = PSB_RVDC32(OVC_OVADD);
- ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
+ gma_power_end(dev);
} else {
if (arg->overlay_read_mask & OV_REGRWBITS_OGAM_ALL) {
arg->overlay.OGAMC5 = dev_priv->saveOV_OGAMC5;
@@ -1343,7 +1186,7 @@
}
if (arg->sprite_enable_mask != 0) {
- if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, usage)) {
+ if (gma_power_begin(dev, usage)) {
PSB_WVDC32(0x1F3E, DSPARB);
PSB_WVDC32(arg->sprite.dspa_control
| PSB_RVDC32(DSPACNTR), DSPACNTR);
@@ -1358,22 +1201,22 @@
PSB_WVDC32(arg->sprite.dspc_size, DSPCSIZE);
PSB_WVDC32(arg->sprite.dspc_surface, DSPCSURF);
PSB_RVDC32(DSPCSURF);
- ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
+ gma_power_end(dev);
}
}
if (arg->sprite_disable_mask != 0) {
- if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, usage)) {
+ if (gma_power_begin(dev, usage)) {
PSB_WVDC32(0x3F3E, DSPARB);
PSB_WVDC32(0x0, DSPCCNTR);
PSB_WVDC32(arg->sprite.dspc_surface, DSPCSURF);
PSB_RVDC32(DSPCSURF);
- ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
+ gma_power_end(dev);
}
}
if (arg->subpicture_enable_mask != 0) {
- if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, usage)) {
+ if (gma_power_begin(dev, usage)) {
uint32_t temp;
if (arg->subpicture_enable_mask & REGRWBITS_DSPACNTR) {
temp = PSB_RVDC32(DSPACNTR);
@@ -1417,12 +1260,12 @@
PSB_WVDC32(temp, DSPCSURF);
PSB_RVDC32(DSPCSURF);
}
- ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
+ gma_power_end(dev);
}
}
if (arg->subpicture_disable_mask != 0) {
- if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, usage)) {
+ if (gma_power_begin(dev, usage)) {
uint32_t temp;
if (arg->subpicture_disable_mask & REGRWBITS_DSPACNTR) {
temp = PSB_RVDC32(DSPACNTR);
@@ -1463,42 +1306,20 @@
PSB_WVDC32(temp, DSPCSURF);
PSB_RVDC32(DSPCSURF);
}
- ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
+ gma_power_end(dev);
}
}
return 0;
}
-/* always available as we are SIGIO'd */
-static unsigned int psb_poll(struct file *filp,
- struct poll_table_struct *wait)
-{
- return POLLIN | POLLRDNORM;
-}
-
-/* Not sure what we will need yet - in the PVR driver this disappears into
- a tangle of abstracted handlers and per process crap */
-
-struct psb_priv {
- int dummy;
-};
-
static int psb_driver_open(struct drm_device *dev, struct drm_file *priv)
{
- struct psb_priv *psb = kzalloc(sizeof(struct psb_priv), GFP_KERNEL);
- if (psb == NULL)
- return -ENOMEM;
- priv->driver_priv = psb;
- DRM_DEBUG("\n");
- /*return PVRSRVOpen(dev, priv);*/
return 0;
}
static void psb_driver_close(struct drm_device *dev, struct drm_file *priv)
{
- kfree(priv->driver_priv);
- priv->driver_priv = NULL;
}
static long psb_unlocked_ioctl(struct file *filp, unsigned int cmd,
@@ -1517,30 +1338,9 @@
pm_runtime_allow(&dev->pdev->dev);
dev_priv->rpm_enabled = 1;
}
- /*
- * The driver private ioctls and TTM ioctls should be
- * thread-safe.
- */
-
- if ((nr >= DRM_COMMAND_BASE) && (nr < DRM_COMMAND_END)
- && (nr < DRM_COMMAND_BASE + dev->driver->num_ioctls)) {
- struct drm_ioctl_desc *ioctl =
- &psb_ioctls[nr - DRM_COMMAND_BASE];
-
- if (unlikely(ioctl->cmd != cmd)) {
- DRM_ERROR(
- "Invalid drm cmnd %d ioctl->cmd %x, cmd %x\n",
- nr - DRM_COMMAND_BASE, ioctl->cmd, cmd);
- return -EINVAL;
- }
-
- return drm_ioctl(filp, cmd, arg);
- }
- /*
- * Not all old drm ioctls are thread-safe.
- */
-
return drm_ioctl(filp, cmd, arg);
+
+ /* FIXME: do we need to wrap the other side of this */
}
@@ -1557,16 +1357,21 @@
drm_put_dev(dev);
}
-
static const struct dev_pm_ops psb_pm_ops = {
.runtime_suspend = psb_runtime_suspend,
.runtime_resume = psb_runtime_resume,
.runtime_idle = psb_runtime_idle,
};
+static struct vm_operations_struct psb_gem_vm_ops = {
+ .fault = psb_gem_fault,
+ .open = drm_gem_vm_open,
+ .close = drm_gem_vm_close,
+};
+
static struct drm_driver driver = {
.driver_features = DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | \
- DRIVER_IRQ_VBL | DRIVER_MODESET,
+ DRIVER_IRQ_VBL | DRIVER_MODESET| DRIVER_GEM ,
.load = psb_driver_load,
.unload = psb_driver_unload,
@@ -1580,27 +1385,29 @@
.enable_vblank = psb_enable_vblank,
.disable_vblank = psb_disable_vblank,
.get_vblank_counter = psb_get_vblank_counter,
- .firstopen = NULL,
.lastclose = psb_lastclose,
.open = psb_driver_open,
- .postclose = psb_driver_close,
-#if 0 /* ACFIXME */
- .get_map_ofs = drm_core_get_map_ofs,
- .get_reg_ofs = drm_core_get_reg_ofs,
- .proc_init = psb_proc_init,
- .proc_cleanup = psb_proc_cleanup,
-#endif
.preclose = psb_driver_preclose,
+ .postclose = psb_driver_close,
+ .reclaim_buffers = drm_core_reclaim_buffers,
+
+ .gem_init_object = psb_gem_init_object,
+ .gem_free_object = psb_gem_free_object,
+ .gem_vm_ops = &psb_gem_vm_ops,
+ .dumb_create = psb_gem_dumb_create,
+ .dumb_map_offset = psb_gem_dumb_map_gtt,
+ .dumb_destroy = psb_gem_dumb_destroy,
+
.fops = {
.owner = THIS_MODULE,
- .open = psb_open,
- .release = psb_release,
+ .open = drm_open,
+ .release = drm_release,
.unlocked_ioctl = psb_unlocked_ioctl,
- .mmap = psb_mmap,
- .poll = psb_poll,
+ .mmap = drm_gem_mmap,
+ .poll = drm_poll,
.fasync = drm_fasync,
.read = drm_read,
- },
+ },
.name = DRIVER_NAME,
.desc = DRIVER_DESC,
.date = PSB_DRM_DRIVER_DATE,
@@ -1612,8 +1419,8 @@
static struct pci_driver psb_pci_driver = {
.name = DRIVER_NAME,
.id_table = pciidlist,
- .resume = ospm_power_resume,
- .suspend = ospm_power_suspend,
+ .resume = gma_power_resume,
+ .suspend = gma_power_suspend,
.probe = psb_probe,
.remove = psb_remove,
#ifdef CONFIG_PM
diff --git a/drivers/staging/gma500/psb_drv.h b/drivers/staging/gma500/psb_drv.h
index 29a3605..e19a454 100644
--- a/drivers/staging/gma500/psb_drv.h
+++ b/drivers/staging/gma500/psb_drv.h
@@ -21,6 +21,7 @@
#define _PSB_DRV_H_
#include <linux/version.h>
+#include <linux/kref.h>
#include <drm/drmP.h>
#include "drm_global.h"
@@ -29,22 +30,19 @@
#include "psb_intel_drv.h"
#include "psb_gtt.h"
#include "psb_powermgmt.h"
-#include "ttm/ttm_object.h"
-#include "psb_ttm_fence_driver.h"
-#include "psb_ttm_userobj_api.h"
-#include "ttm/ttm_bo_driver.h"
-#include "ttm/ttm_lock.h"
+#include "mrst.h"
/*Append new drm mode definition here, align with libdrm definition*/
#define DRM_MODE_SCALE_NO_SCALE 2
-extern struct ttm_bo_driver psb_ttm_bo_driver;
-
enum {
CHIP_PSB_8108 = 0,
CHIP_PSB_8109 = 1,
+ CHIP_MRST_4100 = 2,
};
+#define IS_MRST(dev) (((dev)->pci_device & 0xfffc) == 0x4100)
+
/*
*Hardware bugfixes
*/
@@ -52,10 +50,6 @@
#define DRIVER_NAME "pvrsrvkm"
#define DRIVER_DESC "drm driver for the Intel GMA500"
#define DRIVER_AUTHOR "Intel Corporation"
-#define OSPM_PROC_ENTRY "ospm"
-#define RTPM_PROC_ENTRY "rtpm"
-#define BLC_PROC_ENTRY "mrst_blc"
-#define DISPLAY_PROC_ENTRY "display_status"
#define PSB_DRM_DRIVER_DATE "2009-03-10"
#define PSB_DRM_DRIVER_MAJOR 8
@@ -92,26 +86,10 @@
#define PSB_TT_PRIV0_PLIMIT (PSB_TT_PRIV0_LIMIT >> PAGE_SHIFT)
#define PSB_NUM_VALIDATE_BUFFERS 2048
-#define PSB_MEM_MMU_START 0x00000000
-#define PSB_MEM_TT_START 0xE0000000
-
-#define PSB_GL3_CACHE_CTL 0x2100
-#define PSB_GL3_CACHE_STAT 0x2108
-
/*
*Flags for external memory type field.
*/
-#define MRST_MSVDX_OFFSET 0x90000 /*MSVDX Base offset */
-#define PSB_MSVDX_OFFSET 0x50000 /*MSVDX Base offset */
-/* MSVDX MMIO region is 0x50000 - 0x57fff ==> 32KB */
-#define PSB_MSVDX_SIZE 0x10000
-
-#define LNC_TOPAZ_OFFSET 0xA0000
-#define PNW_TOPAZ_OFFSET 0xC0000
-#define PNW_GL3_OFFSET 0xB0000
-#define LNC_TOPAZ_SIZE 0x10000
-#define PNW_TOPAZ_SIZE 0x30000 /* PNW VXE285 has two cores */
#define PSB_MMU_CACHED_MEMORY 0x0001 /* Bind to MMU only */
#define PSB_MMU_RO_MEMORY 0x0002 /* MMU RO memory */
#define PSB_MMU_WO_MEMORY 0x0004 /* MMU WO memory */
@@ -223,20 +201,6 @@
#define MDFLD_PNW_B0 0x04
#define MDFLD_PNW_C0 0x08
-#define MDFLD_DSR_2D_3D_0 BIT0
-#define MDFLD_DSR_2D_3D_2 BIT1
-#define MDFLD_DSR_CURSOR_0 BIT2
-#define MDFLD_DSR_CURSOR_2 BIT3
-#define MDFLD_DSR_OVERLAY_0 BIT4
-#define MDFLD_DSR_OVERLAY_2 BIT5
-#define MDFLD_DSR_MIPI_CONTROL BIT6
-#define MDFLD_DSR_2D_3D (MDFLD_DSR_2D_3D_0 | MDFLD_DSR_2D_3D_2)
-
-#define MDFLD_DSR_RR 45
-#define MDFLD_DPU_ENABLE BIT31
-#define MDFLD_DSR_FULLSCREEN BIT30
-#define MDFLD_DSR_DELAY (DRM_HZ / MDFLD_DSR_RR)
-
#define PSB_PWR_STATE_ON 1
#define PSB_PWR_STATE_OFF 2
@@ -250,9 +214,6 @@
#define PSB_PCIx_MSI_ADDR_LOC 0x94
#define PSB_PCIx_MSI_DATA_LOC 0x98
-#define MDFLD_PLANE_MAX_WIDTH 2048
-#define MDFLD_PLANE_MAX_HEIGHT 2048
-
struct opregion_header;
struct opregion_acpi;
struct opregion_swsci;
@@ -266,142 +227,55 @@
int enabled;
};
-/*
- *User options.
- */
-
-struct drm_psb_uopt {
- int pad; /*keep it here in case we use it in future*/
-};
-
-/**
- *struct psb_context
- *
- *@buffers: array of pre-allocated validate buffers.
- *@used_buffers: number of buffers in @buffers array currently in use.
- *@validate_buffer: buffers validated from user-space.
- *@kern_validate_buffers : buffers validated from kernel-space.
- *@fence_flags : Fence flags to be used for fence creation.
- *
- *This structure is used during execbuf validation.
- */
-
-struct psb_context {
- struct psb_validate_buffer *buffers;
- uint32_t used_buffers;
- struct list_head validate_list;
- struct list_head kern_validate_list;
- uint32_t fence_types;
- uint32_t val_seq;
-};
-
-struct psb_validate_buffer;
-
-/* Currently defined profiles */
-enum VAProfile {
- VAProfileMPEG2Simple = 0,
- VAProfileMPEG2Main = 1,
- VAProfileMPEG4Simple = 2,
- VAProfileMPEG4AdvancedSimple = 3,
- VAProfileMPEG4Main = 4,
- VAProfileH264Baseline = 5,
- VAProfileH264Main = 6,
- VAProfileH264High = 7,
- VAProfileVC1Simple = 8,
- VAProfileVC1Main = 9,
- VAProfileVC1Advanced = 10,
- VAProfileH263Baseline = 11,
- VAProfileJPEGBaseline = 12,
- VAProfileH264ConstrainedBaseline = 13
-};
-
-/* Currently defined entrypoints */
-enum VAEntrypoint {
- VAEntrypointVLD = 1,
- VAEntrypointIZZ = 2,
- VAEntrypointIDCT = 3,
- VAEntrypointMoComp = 4,
- VAEntrypointDeblocking = 5,
- VAEntrypointEncSlice = 6, /* slice level encode */
- VAEntrypointEncPicture = 7 /* pictuer encode, JPEG, etc */
-};
-
-
-struct psb_video_ctx {
- struct list_head head;
- struct file *filp; /* DRM device file pointer */
- int ctx_type; /* profile<<8|entrypoint */
- /* todo: more context specific data for multi-context support */
-};
-
-#define MODE_SETTING_IN_CRTC 0x1
-#define MODE_SETTING_IN_ENCODER 0x2
-#define MODE_SETTING_ON_GOING 0x3
-#define MODE_SETTING_IN_DSR 0x4
-#define MODE_SETTING_ENCODER_DONE 0x8
-#define GCT_R10_HEADER_SIZE 16
-#define GCT_R10_DISPLAY_DESC_SIZE 28
struct drm_psb_private {
- /*
- * DSI info.
- */
- void * dbi_dsr_info;
- void * dsi_configs[2];
-
- /*
- *TTM Glue.
- */
-
- struct drm_global_reference mem_global_ref;
- struct ttm_bo_global_ref bo_global_ref;
- int has_global;
-
struct drm_device *dev;
- struct ttm_object_device *tdev;
- struct ttm_fence_device fdev;
- struct ttm_bo_device bdev;
- struct ttm_lock ttm_lock;
- struct vm_operations_struct *ttm_vm_ops;
- int has_fence_device;
- int has_bo_device;
unsigned long chipset;
- struct drm_psb_uopt uopt;
-
struct psb_gtt *pg;
- /*GTT Memory manager*/
+ /* GTT Memory manager */
struct psb_gtt_mm *gtt_mm;
-
struct page *scratch_page;
- uint32_t sequence[PSB_NUM_ENGINES];
- uint32_t last_sequence[PSB_NUM_ENGINES];
- uint32_t last_submitted_seq[PSB_NUM_ENGINES];
+ u32 *gtt_map;
+ uint32_t stolen_base;
+ void *vram_addr;
+ unsigned long vram_stolen_size;
+ int gtt_initialized;
+ u16 gmch_ctrl; /* Saved GTT setup */
+ u32 pge_ctl;
+
+ struct mutex gtt_mutex;
+ struct resource *gtt_mem; /* Our PCI resource */
struct psb_mmu_driver *mmu;
struct psb_mmu_pd *pf_pd;
+ /*
+ * Register base
+ */
+
uint8_t *sgx_reg;
uint8_t *vdc_reg;
uint32_t gatt_free_offset;
- /* IMG video context */
- struct list_head video_ctx;
-
-
-
/*
- *Fencing / irq.
+ * Fencing / irq.
*/
uint32_t vdc_irq_mask;
uint32_t pipestat[PSB_NUM_PIPE];
- bool vblanksEnabledForFlips;
spinlock_t irqmask_lock;
- spinlock_t sequence_lock;
+
+ /*
+ * Power
+ */
+
+ bool suspended;
+ bool display_power;
+ int display_count;
/*
*Modesetting
@@ -413,40 +287,9 @@
uint32_t num_pipe;
/*
- * CI share buffer
- */
- unsigned int ci_region_start;
- unsigned int ci_region_size;
-
- /*
- * RAR share buffer;
- */
- unsigned int rar_region_start;
- unsigned int rar_region_size;
-
- /*
*Memory managers
*/
- int have_camera;
- int have_rar;
- int have_tt;
- int have_mem_mmu;
- struct mutex temp_mem;
-
- /*
- *Relocation buffer mapping.
- */
-
- spinlock_t reloc_lock;
- unsigned int rel_mapped_pages;
- wait_queue_head_t rel_mapped_queue;
-
- /*
- *SAREA
- */
- struct drm_psb_sarea *sarea_priv;
-
/*
*OSPM info
*/
@@ -458,7 +301,8 @@
struct drm_psb_sizes_arg sizes;
- uint32_t fuse_reg_value;
+ u32 fuse_reg_value;
+ u32 video_device_fuse;
/* pci revision id for B0:D2:F0 */
uint8_t platform_rev_id;
@@ -483,6 +327,7 @@
unsigned int lvds_use_ssc:1;
int lvds_ssc_freq;
bool is_lvds_on;
+ bool is_mipi_on;
unsigned int core_freq;
uint32_t iLVDS_enable;
@@ -490,6 +335,20 @@
/*runtime PM state*/
int rpm_enabled;
+ /* Moorestown specific */
+ struct mrst_vbt vbt_data;
+ struct mrst_gct_data gct_data;
+
+ /* Moorestown pipe config register value cache */
+ uint32_t pipeconf;
+ uint32_t pipeconf1;
+ uint32_t pipeconf2;
+
+ /* Moorestown plane control register value cache */
+ uint32_t dspcntr;
+ uint32_t dspcntr1;
+ uint32_t dspcntr2;
+
/*
*Register state
*/
@@ -595,98 +454,11 @@
uint32_t saveOVC_OGAMC4;
uint32_t saveOVC_OGAMC5;
- /*
- * extra MDFLD Register state
- */
- uint32_t saveHDMIPHYMISCCTL;
- uint32_t saveHDMIB_CONTROL;
- uint32_t saveDSPCCNTR;
- uint32_t savePIPECCONF;
- uint32_t savePIPECSRC;
- uint32_t saveHTOTAL_C;
- uint32_t saveHBLANK_C;
- uint32_t saveHSYNC_C;
- uint32_t saveVTOTAL_C;
- uint32_t saveVBLANK_C;
- uint32_t saveVSYNC_C;
- uint32_t saveDSPCSTRIDE;
- uint32_t saveDSPCSIZE;
- uint32_t saveDSPCPOS;
- uint32_t saveDSPCSURF;
- uint32_t saveDSPCLINOFF;
- uint32_t saveDSPCTILEOFF;
- uint32_t saveDSPCCURSOR_CTRL;
- uint32_t saveDSPCCURSOR_BASE;
- uint32_t saveDSPCCURSOR_POS;
- uint32_t save_palette_c[256];
- uint32_t saveOV_OVADD_C;
- uint32_t saveOV_OGAMC0_C;
- uint32_t saveOV_OGAMC1_C;
- uint32_t saveOV_OGAMC2_C;
- uint32_t saveOV_OGAMC3_C;
- uint32_t saveOV_OGAMC4_C;
- uint32_t saveOV_OGAMC5_C;
-
- /* DSI reg save */
- uint32_t saveDEVICE_READY_REG;
- uint32_t saveINTR_EN_REG;
- uint32_t saveDSI_FUNC_PRG_REG;
- uint32_t saveHS_TX_TIMEOUT_REG;
- uint32_t saveLP_RX_TIMEOUT_REG;
- uint32_t saveTURN_AROUND_TIMEOUT_REG;
- uint32_t saveDEVICE_RESET_REG;
- uint32_t saveDPI_RESOLUTION_REG;
- uint32_t saveHORIZ_SYNC_PAD_COUNT_REG;
- uint32_t saveHORIZ_BACK_PORCH_COUNT_REG;
- uint32_t saveHORIZ_FRONT_PORCH_COUNT_REG;
- uint32_t saveHORIZ_ACTIVE_AREA_COUNT_REG;
- uint32_t saveVERT_SYNC_PAD_COUNT_REG;
- uint32_t saveVERT_BACK_PORCH_COUNT_REG;
- uint32_t saveVERT_FRONT_PORCH_COUNT_REG;
- uint32_t saveHIGH_LOW_SWITCH_COUNT_REG;
- uint32_t saveINIT_COUNT_REG;
- uint32_t saveMAX_RET_PAK_REG;
- uint32_t saveVIDEO_FMT_REG;
- uint32_t saveEOT_DISABLE_REG;
- uint32_t saveLP_BYTECLK_REG;
- uint32_t saveHS_LS_DBI_ENABLE_REG;
- uint32_t saveTXCLKESC_REG;
- uint32_t saveDPHY_PARAM_REG;
- uint32_t saveMIPI_CONTROL_REG;
- uint32_t saveMIPI;
- uint32_t saveMIPI_C;
- void (*init_drvIC)(struct drm_device *dev);
- void (*dsi_prePowerState)(struct drm_device *dev);
- void (*dsi_postPowerState)(struct drm_device *dev);
-
- /* DPST Register Save */
- uint32_t saveHISTOGRAM_INT_CONTROL_REG;
- uint32_t saveHISTOGRAM_LOGIC_CONTROL_REG;
- uint32_t savePWM_CONTROL_LOGIC;
-
/* MSI reg save */
-
uint32_t msi_addr;
uint32_t msi_data;
/*
- *Scheduling.
- */
-
- struct mutex reset_mutex;
- struct mutex cmdbuf_mutex;
- /*uint32_t ta_mem_pages;
- struct psb_ta_mem *ta_mem;
- int force_ta_mem_load;*/
- atomic_t val_seq;
-
- /*
- *TODO: change this to be per drm-context.
- */
-
- struct psb_context context;
-
- /*
* LID-Switch
*/
spinlock_t lid_lock;
@@ -699,8 +471,6 @@
*Watchdog
*/
- int timer_available;
-
uint32_t apm_reg;
uint16_t apm_base;
@@ -716,73 +486,17 @@
};
-struct psb_file_data { /* TODO: Audit this, remove the indirection and set
- it up properly in open/postclose ACFIXME */
- void *priv;
-};
-
-struct psb_fpriv {
- struct ttm_object_file *tfile;
-};
-
struct psb_mmu_driver;
extern int drm_crtc_probe_output_modes(struct drm_device *dev, int, int);
extern int drm_pick_crtcs(struct drm_device *dev);
-static inline struct psb_fpriv *psb_fpriv(struct drm_file *file_priv)
-{
- struct psb_file_data *pvr_file_priv
- = (struct psb_file_data *)file_priv->driver_priv;
- return (struct psb_fpriv *) pvr_file_priv->priv;
-}
-
static inline struct drm_psb_private *psb_priv(struct drm_device *dev)
{
return (struct drm_psb_private *) dev->dev_private;
}
/*
- *TTM glue. psb_ttm_glue.c
- */
-
-extern int psb_open(struct inode *inode, struct file *filp);
-extern int psb_release(struct inode *inode, struct file *filp);
-extern int psb_mmap(struct file *filp, struct vm_area_struct *vma);
-
-extern int psb_fence_signaled_ioctl(struct drm_device *dev, void *data,
- struct drm_file *file_priv);
-extern int psb_verify_access(struct ttm_buffer_object *bo,
- struct file *filp);
-extern ssize_t psb_ttm_read(struct file *filp, char __user *buf,
- size_t count, loff_t *f_pos);
-extern ssize_t psb_ttm_write(struct file *filp, const char __user *buf,
- size_t count, loff_t *f_pos);
-extern int psb_fence_finish_ioctl(struct drm_device *dev, void *data,
- struct drm_file *file_priv);
-extern int psb_fence_unref_ioctl(struct drm_device *dev, void *data,
- struct drm_file *file_priv);
-extern int psb_pl_waitidle_ioctl(struct drm_device *dev, void *data,
- struct drm_file *file_priv);
-extern int psb_pl_setstatus_ioctl(struct drm_device *dev, void *data,
- struct drm_file *file_priv);
-extern int psb_pl_synccpu_ioctl(struct drm_device *dev, void *data,
- struct drm_file *file_priv);
-extern int psb_pl_unref_ioctl(struct drm_device *dev, void *data,
- struct drm_file *file_priv);
-extern int psb_pl_reference_ioctl(struct drm_device *dev, void *data,
- struct drm_file *file_priv);
-extern int psb_pl_create_ioctl(struct drm_device *dev, void *data,
- struct drm_file *file_priv);
-extern int psb_pl_ub_create_ioctl(struct drm_device *dev, void *data,
- struct drm_file *file_priv);
-extern int psb_extension_ioctl(struct drm_device *dev, void *data,
- struct drm_file *file_priv);
-extern int psb_ttm_global_init(struct drm_psb_private *dev_priv);
-extern void psb_ttm_global_release(struct drm_psb_private *dev_priv);
-extern int psb_getpageaddrs_ioctl(struct drm_device *dev, void *data,
- struct drm_file *file_priv);
-/*
*MMU stuff.
*/
@@ -825,31 +539,6 @@
uint32_t desired_tile_stride,
uint32_t hw_tile_stride);
/*
- *psb_sgx.c
- */
-
-
-
-extern int psb_cmdbuf_ioctl(struct drm_device *dev, void *data,
- struct drm_file *file_priv);
-extern int psb_reg_submit(struct drm_psb_private *dev_priv,
- uint32_t *regs, unsigned int cmds);
-
-
-extern void psb_fence_or_sync(struct drm_file *file_priv,
- uint32_t engine,
- uint32_t fence_types,
- uint32_t fence_flags,
- struct list_head *list,
- struct psb_ttm_fence_rep *fence_arg,
- struct ttm_fence_object **fence_p);
-extern int psb_validate_kernel_buffer(struct psb_context *context,
- struct ttm_buffer_object *bo,
- uint32_t fence_class,
- uint64_t set_flags,
- uint64_t clr_flags);
-
-/*
*psb_irq.c
*/
@@ -859,8 +548,6 @@
extern void psb_irq_preinstall(struct drm_device *dev);
extern int psb_irq_postinstall(struct drm_device *dev);
extern void psb_irq_uninstall(struct drm_device *dev);
-extern void psb_irq_preinstall_islands(struct drm_device *dev, int hw_islands);
-extern int psb_irq_postinstall_islands(struct drm_device *dev, int hw_islands);
extern void psb_irq_turn_on_dpst(struct drm_device *dev);
extern void psb_irq_turn_off_dpst(struct drm_device *dev);
@@ -878,29 +565,6 @@
extern u32 psb_get_vblank_counter(struct drm_device *dev, int crtc);
/*
- *psb_fence.c
- */
-
-extern void psb_fence_handler(struct drm_device *dev, uint32_t class);
-
-extern int psb_fence_emit_sequence(struct ttm_fence_device *fdev,
- uint32_t fence_class,
- uint32_t flags, uint32_t *sequence,
- unsigned long *timeout_jiffies);
-extern void psb_fence_error(struct drm_device *dev,
- uint32_t class,
- uint32_t sequence, uint32_t type, int error);
-extern int psb_ttm_fence_device_init(struct ttm_fence_device *fdev);
-
-/* MSVDX/Topaz stuff */
-extern int psb_remove_videoctx(struct drm_psb_private *dev_priv, struct file *filp);
-
-extern int lnc_video_frameskip(struct drm_device *dev,
- uint64_t user_pointer);
-extern int lnc_video_getparam(struct drm_device *dev, void *data,
- struct drm_file *file_priv);
-
-/*
* psb_opregion.c
*/
extern int psb_intel_opregion_init(struct drm_device *dev);
@@ -930,6 +594,9 @@
extern void psb_spank(struct drm_psb_private *dev_priv);
+extern int psbfb_2d_submit(struct drm_psb_private *dev_priv, uint32_t *cmdbuf,
+ unsigned size);
+
/*
*psb_reset.c
*/
@@ -950,8 +617,36 @@
int psb_get_brightness(struct backlight_device *bd);
struct backlight_device * psb_get_backlight_device(void);
+/* mrst_crtc.c */
+extern const struct drm_crtc_helper_funcs mrst_helper_funcs;
+
+/* mrst_lvds.c */
+extern void mrst_lvds_init(struct drm_device *dev,
+ struct psb_intel_mode_device *mode_dev);
+
+/* psb_intel_lvds.c */
+extern void psb_intel_lvds_prepare(struct drm_encoder *encoder);
+extern void psb_intel_lvds_commit(struct drm_encoder *encoder);
+extern const struct drm_connector_helper_funcs
+ psb_intel_lvds_connector_helper_funcs;
+extern const struct drm_connector_funcs psb_intel_lvds_connector_funcs;
+
+/* psb_gem.c */
+extern int psb_gem_init_object(struct drm_gem_object *obj);
+extern void psb_gem_free_object(struct drm_gem_object *obj);
+extern int psb_gem_get_aperture(struct drm_device *dev, void *data,
+ struct drm_file *file);
+extern int psb_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
+ struct drm_mode_create_dumb *args);
+extern int psb_gem_dumb_destroy(struct drm_file *file, struct drm_device *dev,
+ uint32_t handle);
+extern int psb_gem_dumb_map_gtt(struct drm_file *file, struct drm_device *dev,
+ uint32_t handle, uint64_t *offset);
+extern int psb_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
+
+
/*
- *Debug print bits setting
+ * Debug print bits setting
*/
#define PSB_D_GENERAL (1 << 0)
#define PSB_D_INIT (1 << 1)
@@ -975,7 +670,6 @@
extern int drm_psb_debug;
extern int drm_psb_no_fb;
-extern int drm_psb_disable_vsync;
extern int drm_idle_check_interval;
#define PSB_DEBUG_GENERAL(_fmt, _arg...) \
diff --git a/drivers/staging/gma500/psb_fb.c b/drivers/staging/gma500/psb_fb.c
index f67f53b..99c03a2 100644
--- a/drivers/staging/gma500/psb_fb.c
+++ b/drivers/staging/gma500/psb_fb.c
@@ -36,10 +36,7 @@
#include "psb_drv.h"
#include "psb_intel_reg.h"
#include "psb_intel_drv.h"
-#include "psb_ttm_userobj_api.h"
#include "psb_fb.h"
-#include "psb_sgx.h"
-#include "psb_pvr_glue.h"
static void psb_user_framebuffer_destroy(struct drm_framebuffer *fb);
static int psb_user_framebuffer_create_handle(struct drm_framebuffer *fb,
@@ -193,8 +190,7 @@
struct psb_framebuffer *psbfb = vma->vm_private_data;
struct drm_device *dev = psbfb->base.dev;
struct drm_psb_private *dev_priv = dev->dev_private;
- struct psb_gtt *pg = dev_priv->pg;
- unsigned long phys_addr = (unsigned long)pg->stolen_base;;
+ unsigned long phys_addr = (unsigned long)dev_priv->stolen_base;
page_num = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT;
@@ -243,7 +239,6 @@
char *fb_screen_base = NULL;
struct drm_device *dev = psbfb->base.dev;
struct drm_psb_private *dev_priv = dev->dev_private;
- struct psb_gtt *pg = dev_priv->pg;
if (vma->vm_pgoff != 0)
return -EINVAL;
@@ -256,22 +251,48 @@
fb_screen_base = (char *)info->screen_base;
DRM_DEBUG("vm_pgoff 0x%lx, screen base %p vram_addr %p\n",
- vma->vm_pgoff, fb_screen_base, pg->vram_addr);
+ vma->vm_pgoff, fb_screen_base,
+ dev_priv->vram_addr);
- /*if using stolen memory, */
- if (fb_screen_base == pg->vram_addr) {
+ /* FIXME: ultimately this needs to become 'if entirely stolen memory' */
+ if (1 || fb_screen_base == dev_priv->vram_addr) {
vma->vm_ops = &psbfb_vm_ops;
vma->vm_private_data = (void *)psbfb;
vma->vm_flags |= VM_RESERVED | VM_IO |
VM_MIXEDMAP | VM_DONTEXPAND;
} else {
- /*using IMG meminfo, can I use pvrmmap to map it?*/
-
+ /* GTT memory backed by kernel/user pages, needs a different
+ approach ? - GEM ? */
}
return 0;
}
+static int psbfb_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)
+{
+ struct psb_fbdev *fbdev = info->par;
+ struct psb_framebuffer *psbfb = fbdev->pfb;
+ struct drm_device *dev = psbfb->base.dev;
+ struct drm_psb_private *dev_priv = dev->dev_private;
+ u32 __user *p = (u32 __user *)arg;
+ u32 l;
+ u32 buf[32];
+ switch (cmd) {
+ case 0x12345678:
+ if (!capable(CAP_SYS_RAWIO))
+ return -EPERM;
+ if (get_user(l, p))
+ return -EFAULT;
+ if (l > 32)
+ return -EMSGSIZE;
+ if (copy_from_user(buf, p + 1, l * sizeof(u32)))
+ return -EFAULT;
+ psbfb_2d_submit(dev_priv, buf, l);
+ return 0;
+ default:
+ return -ENOTTY;
+ }
+}
static struct fb_ops psbfb_ops = {
.owner = THIS_MODULE,
@@ -284,11 +305,12 @@
.fb_imageblit = psbfb_imageblit,
.fb_mmap = psbfb_mmap,
.fb_sync = psbfb_sync,
+ .fb_ioctl = psbfb_ioctl,
};
static struct drm_framebuffer *psb_framebuffer_create
(struct drm_device *dev, struct drm_mode_fb_cmd *r,
- void *mm_private)
+ struct gtt_range *gt)
{
struct psb_framebuffer *fb;
int ret;
@@ -304,7 +326,7 @@
drm_helper_mode_fill_fb_struct(&fb->base, r);
- fb->bo = mm_private;
+ fb->gtt = gt;
return &fb->base;
@@ -313,136 +335,58 @@
return NULL;
}
-static struct drm_framebuffer *psb_user_framebuffer_create
- (struct drm_device *dev, struct drm_file *filp,
- struct drm_mode_fb_cmd *r)
+/**
+ * psbfb_alloc - allocate frame buffer memory
+ * @dev: the DRM device
+ * @aligned_size: space needed
+ *
+ * Allocate the frame buffer. In the usual case we get a GTT range that
+ * is stolen memory backed and life is simple. If there isn't sufficient
+ * stolen memory or the system has no stolen memory we allocate a range
+ * and back it with a GEM object.
+ *
+ * In this case the GEM object has no handle.
+ */
+static struct gtt_range *psbfb_alloc(struct drm_device *dev, int aligned_size)
{
- struct ttm_buffer_object *bo = NULL;
- uint64_t size;
-
- bo = ttm_buffer_object_lookup(psb_fpriv(filp)->tfile, r->handle);
- if (!bo)
+ struct gtt_range *backing;
+ /* Begin by trying to use stolen memory backing */
+ backing = psb_gtt_alloc_range(dev, aligned_size, "fb", 1);
+ if (backing)
+ return backing;
+ /* Next try using GEM host memory */
+ backing = psb_gtt_alloc_range(dev, aligned_size, "fb(gem)", 0);
+ if (backing == NULL)
return NULL;
- /* JB: TODO not drop, make smarter */
- size = ((uint64_t) bo->num_pages) << PAGE_SHIFT;
- if (size < r->width * r->height * 4)
- return NULL;
-
- /* JB: TODO not drop, refcount buffer */
- return psb_framebuffer_create(dev, r, bo);
-
-#if 0
- struct psb_framebuffer *psbfb;
- struct drm_framebuffer *fb;
- struct fb_info *info;
- void *psKernelMemInfo = NULL;
- void * hKernelMemInfo = (void *)r->handle;
- struct drm_psb_private *dev_priv
- = (struct drm_psb_private *)dev->dev_private;
- struct psb_fbdev *fbdev = dev_priv->fbdev;
- struct psb_gtt *pg = dev_priv->pg;
- int ret;
- uint32_t offset;
- uint64_t size;
-
- ret = psb_get_meminfo_by_handle(hKernelMemInfo, &psKernelMemInfo);
- if (ret) {
- DRM_ERROR("Cannot get meminfo for handle 0x%x\n",
- (u32)hKernelMemInfo);
+ /* Now back it with an object */
+ if (drm_gem_object_init(dev, &backing->gem, aligned_size) != 0) {
+ psb_gtt_free_range(dev, backing);
return NULL;
}
-
- DRM_DEBUG("Got Kernel MemInfo for handle %lx\n",
- (u32)hKernelMemInfo);
-
- /* JB: TODO not drop, make smarter */
- size = psKernelMemInfo->ui32AllocSize;
- if (size < r->height * r->pitch)
- return NULL;
-
- /* JB: TODO not drop, refcount buffer */
- /* return psb_framebuffer_create(dev, r, bo); */
-
- fb = psb_framebuffer_create(dev, r, (void *)psKernelMemInfo);
- if (!fb) {
- DRM_ERROR("failed to allocate fb.\n");
- return NULL;
- }
-
- psbfb = to_psb_fb(fb);
- psbfb->size = size;
- psbfb->hKernelMemInfo = hKernelMemInfo;
-
- DRM_DEBUG("Mapping to gtt..., KernelMemInfo %p\n", psKernelMemInfo);
-
- /*if not VRAM, map it into tt aperture*/
- if (psKernelMemInfo->pvLinAddrKM != pg->vram_addr) {
- ret = psb_gtt_map_meminfo(dev, hKernelMemInfo, &offset);
- if (ret) {
- DRM_ERROR("map meminfo for 0x%x failed\n",
- (u32)hKernelMemInfo);
- return NULL;
- }
- psbfb->offset = (offset << PAGE_SHIFT);
- } else {
- psbfb->offset = 0;
- }
- info = framebuffer_alloc(0, &dev->pdev->dev);
- if (!info)
- return NULL;
-
- strcpy(info->fix.id, "psbfb");
-
- info->flags = FBINFO_DEFAULT;
- info->fix.accel = FB_ACCEL_I830; /*FIXMEAC*/
- info->fbops = &psbfb_ops;
-
- info->fix.smem_start = dev->mode_config.fb_base;
- info->fix.smem_len = size;
-
- info->screen_base = psKernelMemInfo->pvLinAddrKM;
- info->screen_size = size;
-
- drm_fb_helper_fill_fix(info, fb->pitch, fb->depth);
- drm_fb_helper_fill_var(info, &fbdev->psb_fb_helper,
- fb->width, fb->height);
-
- info->fix.mmio_start = pci_resource_start(dev->pdev, 0);
- info->fix.mmio_len = pci_resource_len(dev->pdev, 0);
-
- info->pixmap.size = 64 * 1024;
- info->pixmap.buf_align = 8;
- info->pixmap.access_align = 32;
- info->pixmap.flags = FB_PIXMAP_SYSTEM;
- info->pixmap.scan_align = 1;
-
- psbfb->fbdev = info;
- fbdev->pfb = psbfb;
-
- fbdev->psb_fb_helper.fb = fb;
- fbdev->psb_fb_helper.fbdev = info;
- MRSTLFBHandleChangeFB(dev, psbfb);
-
- return fb;
-#endif
+ return backing;
}
-
+
+/**
+ * psbfb_create - create a framebuffer
+ * @fbdev: the framebuffer device
+ * @sizes: specification of the layout
+ *
+ * Create a framebuffer to the specifications provided
+ */
static int psbfb_create(struct psb_fbdev *fbdev,
struct drm_fb_helper_surface_size *sizes)
{
struct drm_device *dev = fbdev->psb_fb_helper.dev;
struct drm_psb_private *dev_priv = dev->dev_private;
- struct psb_gtt *pg = dev_priv->pg;
struct fb_info *info;
struct drm_framebuffer *fb;
struct psb_framebuffer *psbfb;
struct drm_mode_fb_cmd mode_cmd;
struct device *device = &dev->pdev->dev;
-
- struct ttm_buffer_object *fbo = NULL;
int size, aligned_size;
int ret;
+ struct gtt_range *backing;
mode_cmd.width = sizes->surface_width;
mode_cmd.height = sizes->surface_height;
@@ -455,15 +399,19 @@
size = mode_cmd.pitch * mode_cmd.height;
aligned_size = ALIGN(size, PAGE_SIZE);
+ /* Allocate the framebuffer in the GTT with stolen page backing */
+ backing = psbfb_alloc(dev, aligned_size);
+ if (backing == NULL)
+ return -ENOMEM;
+
mutex_lock(&dev->struct_mutex);
- fb = psb_framebuffer_create(dev, &mode_cmd, fbo);
+ fb = psb_framebuffer_create(dev, &mode_cmd, backing);
if (!fb) {
DRM_ERROR("failed to allocate fb.\n");
ret = -ENOMEM;
goto out_err1;
}
psbfb = to_psb_fb(fb);
- psbfb->size = size;
info = framebuffer_alloc(sizeof(struct psb_fbdev), device);
if (!info) {
@@ -485,7 +433,11 @@
info->fbops = &psbfb_ops;
info->fix.smem_start = dev->mode_config.fb_base;
info->fix.smem_len = size;
- info->screen_base = (char *)pg->vram_addr;
+
+ /* Accessed via stolen memory directly, This only works for stolem
+ memory however. Need to address this once we start using gtt
+ pages we allocate */
+ info->screen_base = (char *)dev_priv->vram_addr + backing->offset;
info->screen_size = size;
memset(info->screen_base, 0, size);
@@ -515,9 +467,51 @@
fb->funcs->destroy(fb);
out_err1:
mutex_unlock(&dev->struct_mutex);
+ psb_gtt_free_range(dev, backing);
return ret;
}
+/**
+ * psb_user_framebuffer_create - create framebuffer
+ * @dev: our DRM device
+ * @filp: client file
+ * @cmd: mode request
+ *
+ * Create a new framebuffer backed by a userspace GEM object
+ */
+static struct drm_framebuffer *psb_user_framebuffer_create
+ (struct drm_device *dev, struct drm_file *filp,
+ struct drm_mode_fb_cmd *cmd)
+{
+ struct gtt_range *r;
+ struct drm_gem_object *obj;
+ struct psb_framebuffer *psbfb;
+
+ /* Find the GEM object and thus the gtt range object that is
+ to back this space */
+ obj = drm_gem_object_lookup(dev, filp, cmd->handle);
+ if (obj == NULL)
+ return ERR_PTR(-ENOENT);
+
+ /* Allocate a framebuffer */
+ psbfb = kzalloc(sizeof(*psbfb), GFP_KERNEL);
+ if (psbfb == NULL) {
+ drm_gem_object_unreference_unlocked(obj);
+ return ERR_PTR(-ENOMEM);
+ }
+
+ /* Let the core code do all the work */
+ r = container_of(obj, struct gtt_range, gem);
+ if (psb_framebuffer_create(dev, cmd, r) == NULL) {
+ drm_gem_object_unreference_unlocked(obj);
+ kfree(psbfb);
+ return ERR_PTR(-EINVAL);
+ }
+ /* Return the drm_framebuffer contained within the psb fbdev which
+ has been initialized by the framebuffer creation */
+ return &psbfb->base;
+}
+
static void psbfb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
u16 blue, int regno)
{
@@ -561,15 +555,20 @@
if (fbdev->psb_fb_helper.fbdev) {
info = fbdev->psb_fb_helper.fbdev;
+ /* FIXME: this is a bit more inside knowledge than I'd like
+ but I don't see how to make a fake GEM object of the
+ stolen space nicely */
+ if (psbfb->gtt->stolen)
+ psb_gtt_free_range(dev, psbfb->gtt);
+ else
+ drm_gem_object_unreference(&psbfb->gtt->gem);
unregister_framebuffer(info);
iounmap(info->screen_base);
framebuffer_release(info);
}
drm_fb_helper_fini(&fbdev->psb_fb_helper);
-
drm_framebuffer_cleanup(&psbfb->base);
-
return 0;
}
@@ -610,7 +609,6 @@
dev_priv->fbdev = NULL;
}
-
static void psbfb_output_poll_changed(struct drm_device *dev)
{
struct drm_psb_private *dev_priv = dev->dev_private;
@@ -627,7 +625,6 @@
return 0;
info = psbfb->fbdev;
- psbfb->pvrBO = NULL;
if (info)
framebuffer_release(info);
@@ -635,28 +632,48 @@
}
/*EXPORT_SYMBOL(psbfb_remove); */
+/**
+ * psb_user_framebuffer_create_handle - add hamdle to a framebuffer
+ * @fb: framebuffer
+ * @file_priv: our DRM file
+ * @handle: returned handle
+ *
+ * Our framebuffer object is a GTT range which also contains a GEM
+ * object. We need to turn it into a handle for userspace. GEM will do
+ * the work for us
+ */
static int psb_user_framebuffer_create_handle(struct drm_framebuffer *fb,
struct drm_file *file_priv,
unsigned int *handle)
{
- /* JB: TODO currently we can't go from a bo to a handle with ttm */
- (void) file_priv;
- *handle = 0;
- return 0;
+ struct psb_framebuffer *psbfb = to_psb_fb(fb);
+ struct gtt_range *r = psbfb->gtt;
+ if (r->stolen)
+ return -EOPNOTSUPP;
+ return drm_gem_handle_create(file_priv, &r->gem, handle);
}
+/**
+ * psb_user_framebuffer_destroy - destruct user created fb
+ * @fb: framebuffer
+ *
+ * User framebuffers are backed by GEM objects so all we have to do is
+ * clean up a bit and drop the reference, GEM will handle the fallout
+ */
static void psb_user_framebuffer_destroy(struct drm_framebuffer *fb)
{
struct drm_device *dev = fb->dev;
struct psb_framebuffer *psbfb = to_psb_fb(fb);
+ struct gtt_range *r = psbfb->gtt;
- /*ummap gtt pages*/
- psb_gtt_unmap_meminfo(dev, psbfb->hKernelMemInfo);
if (psbfb->fbdev)
psbfb_remove(dev, fb);
- /* JB: TODO not drop, refcount buffer */
+ /* Let DRM do its clean up */
drm_framebuffer_cleanup(fb);
+ /* We are no longer using the resource in GEM */
+ drm_gem_object_unreference_unlocked(&r->gem);
+
kfree(fb);
}
@@ -698,8 +715,15 @@
psb_create_backlight_property(dev);
- psb_intel_lvds_init(dev, &dev_priv->mode_dev);
- /* psb_intel_sdvo_init(dev, SDVOB); */
+ if (IS_MRST(dev)) {
+ if (dev_priv->iLVDS_enable)
+ mrst_lvds_init(dev, &dev_priv->mode_dev);
+ else
+ DRM_ERROR("DSI is not supported\n");
+ } else {
+ psb_intel_lvds_init(dev, &dev_priv->mode_dev);
+ psb_intel_sdvo_init(dev, SDVOB);
+ }
list_for_each_entry(connector, &dev->mode_config.connector_list,
head) {
@@ -716,7 +740,10 @@
break;
case INTEL_OUTPUT_LVDS:
PSB_DEBUG_ENTRY("LVDS.\n");
- crtc_mask = (1 << 1);
+ if (IS_MRST(dev))
+ crtc_mask = (1 << 0);
+ else
+ crtc_mask = (1 << 1);
clone_mask = (1 << INTEL_OUTPUT_LVDS);
break;
case INTEL_OUTPUT_MIPI:
@@ -743,52 +770,6 @@
}
}
-static void *psb_bo_from_handle(struct drm_device *dev,
- struct drm_file *file_priv,
- unsigned int handle)
-{
- void *psKernelMemInfo = NULL;
- void * hKernelMemInfo = (void *)handle;
- int ret;
-
- ret = psb_get_meminfo_by_handle(hKernelMemInfo, &psKernelMemInfo);
- if (ret) {
- DRM_ERROR("Cannot get meminfo for handle 0x%x\n",
- (u32)hKernelMemInfo);
- return NULL;
- }
-
- return (void *)psKernelMemInfo;
-}
-
-static size_t psb_bo_size(struct drm_device *dev, void *bof)
-{
-#if 0
- void *psKernelMemInfo = (void *)bof;
- return (size_t)psKernelMemInfo->ui32AllocSize;
-#else
- return 0;
-#endif
-}
-
-static size_t psb_bo_offset(struct drm_device *dev, void *bof)
-{
- struct psb_framebuffer *psbfb
- = (struct psb_framebuffer *)bof;
-
- return (size_t)psbfb->offset;
-}
-
-static int psb_bo_pin_for_scanout(struct drm_device *dev, void *bo)
-{
- return 0;
-}
-
-static int psb_bo_unpin_for_scanout(struct drm_device *dev, void *bo)
-{
- return 0;
-}
-
void psb_modeset_init(struct drm_device *dev)
{
struct drm_psb_private *dev_priv =
@@ -797,12 +778,6 @@
int i;
PSB_DEBUG_ENTRY("\n");
- /* Init mm functions */
- mode_dev->bo_from_handle = psb_bo_from_handle;
- mode_dev->bo_size = psb_bo_size;
- mode_dev->bo_offset = psb_bo_offset;
- mode_dev->bo_pin_for_scanout = psb_bo_pin_for_scanout;
- mode_dev->bo_unpin_for_scanout = psb_bo_unpin_for_scanout;
drm_mode_config_init(dev);
diff --git a/drivers/staging/gma500/psb_fb.h b/drivers/staging/gma500/psb_fb.h
index b4fab92..c8ec0d6 100644
--- a/drivers/staging/gma500/psb_fb.h
+++ b/drivers/staging/gma500/psb_fb.h
@@ -28,32 +28,22 @@
#include "psb_drv.h"
-/*IMG Headers*/
-/*#include "servicesint.h"*/
-
struct psb_framebuffer {
struct drm_framebuffer base;
struct address_space *addr_space;
- struct ttm_buffer_object *bo;
- struct fb_info * fbdev;
- /* struct ttm_bo_kmap_obj kmap; */
- void *pvrBO; /* FIXME: sort this out */
- void * hKernelMemInfo;
- uint32_t size;
- uint32_t offset;
+ struct fb_info *fbdev;
+ struct gtt_range *gtt;
};
struct psb_fbdev {
struct drm_fb_helper psb_fb_helper;
- struct psb_framebuffer * pfb;
+ struct psb_framebuffer *pfb;
};
#define to_psb_fb(x) container_of(x, struct psb_framebuffer, base)
-
extern int psb_intel_connector_clones(struct drm_device *dev, int type_mask);
-
#endif
diff --git a/drivers/staging/gma500/psb_fence.c b/drivers/staging/gma500/psb_fence.c
deleted file mode 100644
index a70aa64..0000000
--- a/drivers/staging/gma500/psb_fence.c
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * Copyright (c) 2007, Intel Corporation.
- * All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
- *
- *
- * Authors: Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
- */
-
-#include <drm/drmP.h>
-#include "psb_drv.h"
-
-
-static void psb_fence_poll(struct ttm_fence_device *fdev,
- uint32_t fence_class, uint32_t waiting_types)
-{
- struct drm_psb_private *dev_priv =
- container_of(fdev, struct drm_psb_private, fdev);
-
-
- if (unlikely(!dev_priv))
- return;
-
- if (waiting_types == 0)
- return;
-
- /* DRM_ERROR("Polling fence sequence, got 0x%08x\n", sequence); */
- ttm_fence_handler(fdev, fence_class, 0 /* Sequence */,
- _PSB_FENCE_TYPE_EXE, 0);
-}
-
-void psb_fence_error(struct drm_device *dev,
- uint32_t fence_class,
- uint32_t sequence, uint32_t type, int error)
-{
- struct drm_psb_private *dev_priv = psb_priv(dev);
- struct ttm_fence_device *fdev = &dev_priv->fdev;
- unsigned long irq_flags;
- struct ttm_fence_class_manager *fc =
- &fdev->fence_class[fence_class];
-
- BUG_ON(fence_class >= PSB_NUM_ENGINES);
- write_lock_irqsave(&fc->lock, irq_flags);
- ttm_fence_handler(fdev, fence_class, sequence, type, error);
- write_unlock_irqrestore(&fc->lock, irq_flags);
-}
-
-int psb_fence_emit_sequence(struct ttm_fence_device *fdev,
- uint32_t fence_class,
- uint32_t flags, uint32_t *sequence,
- unsigned long *timeout_jiffies)
-{
- struct drm_psb_private *dev_priv =
- container_of(fdev, struct drm_psb_private, fdev);
-
- if (!dev_priv)
- return -EINVAL;
-
- if (fence_class >= PSB_NUM_ENGINES)
- return -EINVAL;
-
- DRM_ERROR("Unexpected fence class\n");
- return -EINVAL;
-}
-
-static void psb_fence_lockup(struct ttm_fence_object *fence,
- uint32_t fence_types)
-{
- DRM_ERROR("Unsupported fence class\n");
-}
-
-void psb_fence_handler(struct drm_device *dev, uint32_t fence_class)
-{
- struct drm_psb_private *dev_priv = psb_priv(dev);
- struct ttm_fence_device *fdev = &dev_priv->fdev;
- struct ttm_fence_class_manager *fc =
- &fdev->fence_class[fence_class];
- unsigned long irq_flags;
-
- write_lock_irqsave(&fc->lock, irq_flags);
- psb_fence_poll(fdev, fence_class, fc->waiting_types);
- write_unlock_irqrestore(&fc->lock, irq_flags);
-}
-
-
-static struct ttm_fence_driver psb_ttm_fence_driver = {
- .has_irq = NULL,
- .emit = psb_fence_emit_sequence,
- .flush = NULL,
- .poll = psb_fence_poll,
- .needed_flush = NULL,
- .wait = NULL,
- .signaled = NULL,
- .lockup = psb_fence_lockup,
-};
-
-int psb_ttm_fence_device_init(struct ttm_fence_device *fdev)
-{
- struct drm_psb_private *dev_priv =
- container_of(fdev, struct drm_psb_private, fdev);
- struct ttm_fence_class_init fci = {.wrap_diff = (1 << 30),
- .flush_diff = (1 << 29),
- .sequence_mask = 0xFFFFFFFF
- };
-
- return ttm_fence_device_init(PSB_NUM_ENGINES,
- dev_priv->mem_global_ref.object,
- fdev, &fci, 1,
- &psb_ttm_fence_driver);
-}
diff --git a/drivers/staging/gma500/psb_gem.c b/drivers/staging/gma500/psb_gem.c
new file mode 100644
index 0000000..76ff7ba
--- /dev/null
+++ b/drivers/staging/gma500/psb_gem.c
@@ -0,0 +1,320 @@
+/*
+ * psb GEM interface
+ *
+ * Copyright (c) 2011, Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
+ *
+ * Authors: Alan Cox
+ *
+ * TODO:
+ * - we don't actually put GEM objects into the GART yet
+ * - we need to work out if the MMU is relevant as well (eg for
+ * accelerated operations on a GEM object)
+ * - cache coherency
+ *
+ * ie this is just an initial framework to get us going.
+ */
+
+#include <drm/drmP.h>
+#include <drm/drm.h>
+#include "psb_drm.h"
+#include "psb_drv.h"
+
+int psb_gem_init_object(struct drm_gem_object *obj)
+{
+ return -EINVAL;
+}
+
+void psb_gem_free_object(struct drm_gem_object *obj)
+{
+ struct gtt_range *gtt = container_of(obj, struct gtt_range, gem);
+ psb_gtt_free_range(obj->dev, gtt);
+ if (obj->map_list.map) {
+ /* Do things GEM should do for us */
+ struct drm_gem_mm *mm = obj->dev->mm_private;
+ struct drm_map_list *list = &obj->map_list;
+ drm_ht_remove_item(&mm->offset_hash, &list->hash);
+ drm_mm_put_block(list->file_offset_node);
+ kfree(list->map);
+ list->map = NULL;
+ }
+ drm_gem_object_release(obj);
+}
+
+int psb_gem_get_aperture(struct drm_device *dev, void *data,
+ struct drm_file *file)
+{
+ return -EINVAL;
+}
+
+/**
+ * psb_gem_create_mmap_offset - invent an mmap offset
+ * @obj: our object
+ *
+ * This is basically doing by hand a pile of ugly crap which should
+ * be done automatically by the GEM library code but isn't
+ */
+static int psb_gem_create_mmap_offset(struct drm_gem_object *obj)
+{
+ struct drm_device *dev = obj->dev;
+ struct drm_gem_mm *mm = dev->mm_private;
+ struct drm_map_list *list;
+ struct drm_local_map *map;
+ int ret;
+
+ list = &obj->map_list;
+ list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL);
+ if (list->map == NULL)
+ return -ENOMEM;
+ map = list->map;
+ map->type = _DRM_GEM;
+ map->size = obj->size;
+ map->handle =obj;
+
+ list->file_offset_node = drm_mm_search_free(&mm->offset_manager,
+ obj->size / PAGE_SIZE, 0, 0);
+ if (!list->file_offset_node) {
+ DRM_ERROR("failed to allocate offset for bo %d\n", obj->name);
+ ret = -ENOSPC;
+ goto free_it;
+ }
+ list->file_offset_node = drm_mm_get_block(list->file_offset_node,
+ obj->size / PAGE_SIZE, 0);
+ if (!list->file_offset_node) {
+ ret = -ENOMEM;
+ goto free_it;
+ }
+ list->hash.key = list->file_offset_node->start;
+ ret = drm_ht_insert_item(&mm->offset_hash, &list->hash);
+ if (ret) {
+ DRM_ERROR("failed to add to map hash\n");
+ goto free_mm;
+ }
+ return 0;
+
+free_mm:
+ drm_mm_put_block(list->file_offset_node);
+free_it:
+ kfree(list->map);
+ list->map = NULL;
+ return ret;
+}
+
+/**
+ * psb_gem_dumb_map_gtt - buffer mapping for dumb interface
+ * @file: our drm client file
+ * @dev: drm device
+ * @handle: GEM handle to the object (from dumb_create)
+ *
+ * Do the necessary setup to allow the mapping of the frame buffer
+ * into user memory. We don't have to do much here at the moment.
+ */
+int psb_gem_dumb_map_gtt(struct drm_file *file, struct drm_device *dev,
+ uint32_t handle, uint64_t *offset)
+{
+ int ret = 0;
+ struct drm_gem_object *obj;
+
+ if (!(dev->driver->driver_features & DRIVER_GEM))
+ return -ENODEV;
+
+ mutex_lock(&dev->struct_mutex);
+
+ /* GEM does all our handle to object mapping */
+ obj = drm_gem_object_lookup(dev, file, handle);
+ if (obj == NULL) {
+ ret = -ENOENT;
+ goto unlock;
+ }
+ /* What validation is needed here ? */
+
+ /* Make it mmapable */
+ if (!obj->map_list.map) {
+ ret = psb_gem_create_mmap_offset(obj);
+ if (ret)
+ goto out;
+ }
+ /* GEM should really work out the hash offsets for us */
+ *offset = (u64)obj->map_list.hash.key << PAGE_SHIFT;
+out:
+ drm_gem_object_unreference(obj);
+unlock:
+ mutex_unlock(&dev->struct_mutex);
+ return ret;
+}
+
+/**
+ * psb_gem_create - create a mappable object
+ * @file: the DRM file of the client
+ * @dev: our device
+ * @size: the size requested
+ * @handlep: returned handle (opaque number)
+ *
+ * Create a GEM object, fill in the boilerplate and attach a handle to
+ * it so that userspace can speak about it. This does the core work
+ * for the various methods that do/will create GEM objects for things
+ */
+static int psb_gem_create(struct drm_file *file,
+ struct drm_device *dev, uint64_t size, uint32_t *handlep)
+{
+ struct gtt_range *r;
+ int ret;
+ u32 handle;
+
+ size = roundup(size, PAGE_SIZE);
+
+ /* Allocate our object - for now a direct gtt range which is not
+ stolen memory backed */
+ r = psb_gtt_alloc_range(dev, size, "gem", 0);
+ if (r == NULL)
+ return -ENOSPC;
+ /* Initialize the extra goodies GEM needs to do all the hard work */
+ if (drm_gem_object_init(dev, &r->gem, size) != 0) {
+ psb_gtt_free_range(dev, r);
+ /* GEM doesn't give an error code and we don't have an
+ EGEMSUCKS so make something up for now - FIXME */
+ return -ENOMEM;
+ }
+ /* Give the object a handle so we can carry it more easily */
+ ret = drm_gem_handle_create(file, &r->gem, &handle);
+ if (ret) {
+ drm_gem_object_release(&r->gem);
+ psb_gtt_free_range(dev, r);
+ return ret;
+ }
+ /* We have the initial and handle reference but need only one now */
+ drm_gem_object_unreference(&r->gem);
+ *handlep = handle;
+ return 0;
+}
+
+/**
+ * psb_gem_dumb_create - create a dumb buffer
+ * @drm_file: our client file
+ * @dev: our device
+ * @args: the requested arguments copied from userspace
+ *
+ * Allocate a buffer suitable for use for a frame buffer of the
+ * form described by user space. Give userspace a handle by which
+ * to reference it.
+ */
+int psb_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
+ struct drm_mode_create_dumb *args)
+{
+ args->pitch = ALIGN(args->width * ((args->bpp + 7) / 8), 64);
+ args->size = args->pitch * args->height;
+ return psb_gem_create(file, dev, args->size, &args->handle);
+}
+
+/**
+ * psb_gem_dumb_destroy - destroy a dumb buffer
+ * @file: client file
+ * @dev: our DRM device
+ * @handle: the object handle
+ *
+ * Destroy a handle that was created via psb_gem_dumb_create, at least
+ * we hope it was created that way. i915 seems to assume the caller
+ * does the checking but that might be worth review ! FIXME
+ */
+int psb_gem_dumb_destroy(struct drm_file *file, struct drm_device *dev,
+ uint32_t handle)
+{
+ /* No special work needed, drop the reference and see what falls out */
+ return drm_gem_handle_delete(file, handle);
+}
+
+/**
+ * psb_gem_fault - pagefault handler for GEM objects
+ * @vma: the VMA of the GEM object
+ * @vmf: fault detail
+ *
+ * Invoked when a fault occurs on an mmap of a GEM managed area. GEM
+ * does most of the work for us including the actual map/unmap calls
+ * but we need to do the actual page work.
+ *
+ * This code eventually needs to handle faulting objects in and out
+ * of the GART and repacking it when we run out of space. We can put
+ * that off for now and for our simple uses
+ *
+ * The VMA was set up by GEM. In doing so it also ensured that the
+ * vma->vm_private_data points to the GEM object that is backing this
+ * mapping.
+ *
+ * To avoid aliasing and cache funnies we want to map the object
+ * through the GART. For the moment this is slightly hackish. It would
+ * be nicer if GEM provided mmap opened/closed hooks for us giving
+ * the object so that we could track things nicely. That needs changes
+ * to the core GEM code so must be tackled post staging
+ *
+ * FIXME
+ */
+int psb_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
+{
+ struct drm_gem_object *obj;
+ struct gtt_range *r;
+ int ret;
+ unsigned long pfn;
+ pgoff_t page_offset;
+ struct drm_device *dev;
+
+ obj = vma->vm_private_data; /* GEM object */
+ dev = obj->dev;
+
+ r = container_of(obj, struct gtt_range, gem); /* Get the gtt range */
+
+ /* Make sure we don't parallel update on a fault, nor move or remove
+ something from beneath our feet */
+ mutex_lock(&dev->struct_mutex);
+
+ /* For now the mmap pins the object and it stays pinned. As things
+ stand that will do us no harm */
+ if (r->mmapping == 0) {
+ ret = psb_gtt_pin(r);
+ if (ret < 0) {
+ DRM_ERROR("gma500: pin failed: %d\n", ret);
+ goto fail;
+ }
+ r->mmapping = 1;
+ }
+
+ /* FIXME: Locking. We may also need to repack the GART sometimes */
+
+ /* Page relative to the VMA start */
+ page_offset = ((unsigned long) vmf->virtual_address - vma->vm_start)
+ >> PAGE_SHIFT;
+
+ /* Bus address of the page is gart + object offset + page offset */
+ /* Assumes gtt allocations are page aligned */
+ pfn = (r->resource.start >> PAGE_SHIFT) + page_offset;
+
+ pr_debug("Object GTT base at %p\n", (void *)(r->resource.start));
+ pr_debug("Inserting %p pfn %lx, pa %lx\n", vmf->virtual_address,
+ pfn, pfn << PAGE_SHIFT);
+
+ ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn);
+
+fail:
+ mutex_unlock(&dev->struct_mutex);
+ switch (ret) {
+ case 0:
+ case -ERESTARTSYS:
+ case -EINTR:
+ return VM_FAULT_NOPAGE;
+ case -ENOMEM:
+ return VM_FAULT_OOM;
+ default:
+ return VM_FAULT_SIGBUS;
+ }
+}
diff --git a/drivers/staging/gma500/psb_gtt.c b/drivers/staging/gma500/psb_gtt.c
index 53c1e1e..74c5a65 100644
--- a/drivers/staging/gma500/psb_gtt.c
+++ b/drivers/staging/gma500/psb_gtt.c
@@ -16,12 +16,24 @@
* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
*
* Authors: Thomas Hellstrom <thomas-at-tungstengraphics.com>
+ * Alan Cox <alan@linux.intel.com>
*/
#include <drm/drmP.h>
#include "psb_drv.h"
-#include "psb_pvr_glue.h"
+
+/*
+ * GTT resource allocator - manage page mappings in GTT space
+ */
+
+/**
+ * psb_gtt_mask_pte - generate GART pte entry
+ * @pfn: page number to encode
+ * @type: type of memory in the GART
+ *
+ * Set the GART entry for the appropriate memory type.
+ */
static inline uint32_t psb_gtt_mask_pte(uint32_t pfn, int type)
{
uint32_t mask = PSB_PTE_VALID;
@@ -36,6 +48,327 @@
return (pfn << PAGE_SHIFT) | mask;
}
+/**
+ * psb_gtt_entry - find the GART entries for a gtt_range
+ * @dev: our DRM device
+ * @r: our GTT range
+ *
+ * Given a gtt_range object return the GART offset of the page table
+ * entries for this gtt_range
+ */
+u32 *psb_gtt_entry(struct drm_device *dev, struct gtt_range *r)
+{
+ struct drm_psb_private *dev_priv = dev->dev_private;
+ unsigned long offset;
+
+ offset = r->resource.start - dev_priv->gtt_mem->start;
+
+ return dev_priv->gtt_map + (offset >> PAGE_SHIFT);
+}
+
+/**
+ * psb_gtt_insert - put an object into the GART
+ * @dev: our DRM device
+ * @r: our GTT range
+ *
+ * Take our preallocated GTT range and insert the GEM object into
+ * the GART.
+ *
+ * FIXME: gtt lock ?
+ */
+static int psb_gtt_insert(struct drm_device *dev, struct gtt_range *r)
+{
+ struct drm_psb_private *dev_priv = dev->dev_private;
+ u32 *gtt_slot, pte;
+ int numpages = (r->resource.end + 1 - r->resource.start) >> PAGE_SHIFT;
+ struct page **pages;
+ int i;
+
+ if (r->pages == NULL) {
+ WARN_ON(1);
+ return -EINVAL;
+ }
+
+ WARN_ON(r->stolen); /* refcount these maybe ? */
+
+ gtt_slot = psb_gtt_entry(dev, r);
+ pages = r->pages;
+
+ /* Make sure we have no alias present */
+ wbinvd();
+
+ /* Write our page entries into the GART itself */
+ for (i = 0; i < numpages; i++) {
+ pte = psb_gtt_mask_pte(page_to_pfn(*pages++), 0/*type*/);
+ iowrite32(pte, gtt_slot++);
+ }
+ /* Make sure all the entries are set before we return */
+ ioread32(gtt_slot - 1);
+
+ return 0;
+}
+
+/**
+ * psb_gtt_remove - remove an object from the GART
+ * @dev: our DRM device
+ * @r: our GTT range
+ *
+ * Remove a preallocated GTT range from the GART. Overwrite all the
+ * page table entries with the dummy page
+ */
+
+static void psb_gtt_remove(struct drm_device *dev, struct gtt_range *r)
+{
+ struct drm_psb_private *dev_priv = dev->dev_private;
+ u32 *gtt_slot, pte;
+ int numpages = (r->resource.end + 1 - r->resource.start) >> PAGE_SHIFT;
+ int i;
+
+ WARN_ON(r->stolen);
+
+ gtt_slot = psb_gtt_entry(dev, r);
+ pte = psb_gtt_mask_pte(page_to_pfn(dev_priv->scratch_page), 0);;
+
+ for (i = 0; i < numpages; i++)
+ iowrite32(pte, gtt_slot++);
+ ioread32(gtt_slot - 1);
+}
+
+/**
+ * psb_gtt_attach_pages - attach and pin GEM pages
+ * @gt: the gtt range
+ *
+ * Pin and build an in kernel list of the pages that back our GEM object.
+ * While we hold this the pages cannot be swapped out
+ *
+ * FIXME: Do we need to cache flush when we update the GTT
+ */
+static int psb_gtt_attach_pages(struct gtt_range *gt)
+{
+ struct inode *inode;
+ struct address_space *mapping;
+ int i;
+ struct page *p;
+ int pages = (gt->resource.end + 1 - gt->resource.start) >> PAGE_SHIFT;
+
+ WARN_ON(gt->pages);
+
+ /* This is the shared memory object that backs the GEM resource */
+ inode = gt->gem.filp->f_path.dentry->d_inode;
+ mapping = inode->i_mapping;
+
+ gt->pages = kmalloc(pages * sizeof(struct page *), GFP_KERNEL);
+ if (gt->pages == NULL)
+ return -ENOMEM;
+ for (i = 0; i < pages; i++) {
+ /* FIXME: review flags later */
+ p = read_cache_page_gfp(mapping, i,
+ __GFP_COLD | GFP_KERNEL);
+ if (IS_ERR(p))
+ goto err;
+ gt->pages[i] = p;
+ }
+ return 0;
+
+err:
+ while (i--)
+ page_cache_release(gt->pages[i]);
+ kfree(gt->pages);
+ gt->pages = NULL;
+ return PTR_ERR(p);
+}
+
+/**
+ * psb_gtt_detach_pages - attach and pin GEM pages
+ * @gt: the gtt range
+ *
+ * Undo the effect of psb_gtt_attach_pages. At this point the pages
+ * must have been removed from the GART as they could now be paged out
+ * and move bus address.
+ *
+ * FIXME: Do we need to cache flush when we update the GTT
+ */
+static void psb_gtt_detach_pages(struct gtt_range *gt)
+{
+ int i;
+ int pages = (gt->resource.end + 1 - gt->resource.start) >> PAGE_SHIFT;
+
+ for (i = 0; i < pages; i++) {
+ /* FIXME: do we need to force dirty */
+ set_page_dirty(gt->pages[i]);
+ /* Undo the reference we took when populating the table */
+ page_cache_release(gt->pages[i]);
+ }
+ kfree(gt->pages);
+ gt->pages = NULL;
+}
+
+/**
+ * psb_gtt_pin - pin pages into the GTT
+ * @gt: range to pin
+ *
+ * Pin a set of pages into the GTT. The pins are refcounted so that
+ * multiple pins need multiple unpins to undo.
+ *
+ * Non GEM backed objects treat this as a no-op as they are always GTT
+ * backed objects.
+ */
+int psb_gtt_pin(struct gtt_range *gt)
+{
+ int ret;
+ struct drm_device *dev = gt->gem.dev;
+ struct drm_psb_private *dev_priv = dev->dev_private;
+
+ mutex_lock(&dev_priv->gtt_mutex);
+
+ if (gt->in_gart == 0 && gt->stolen == 0) {
+ ret = psb_gtt_attach_pages(gt);
+ if (ret < 0)
+ goto out;
+ ret = psb_gtt_insert(dev, gt);
+ if (ret < 0) {
+ psb_gtt_detach_pages(gt);
+ goto out;
+ }
+ }
+ gt->in_gart++;
+out:
+ mutex_unlock(&dev_priv->gtt_mutex);
+ return ret;
+}
+
+/**
+ * psb_gtt_unpin - Drop a GTT pin requirement
+ * @gt: range to pin
+ *
+ * Undoes the effect of psb_gtt_pin. On the last drop the GEM object
+ * will be removed from the GTT which will also drop the page references
+ * and allow the VM to clean up or page stuff.
+ *
+ * Non GEM backed objects treat this as a no-op as they are always GTT
+ * backed objects.
+ */
+void psb_gtt_unpin(struct gtt_range *gt)
+{
+ struct drm_device *dev = gt->gem.dev;
+ struct drm_psb_private *dev_priv = dev->dev_private;
+
+ mutex_lock(&dev_priv->gtt_mutex);
+
+ WARN_ON(!gt->in_gart);
+
+ gt->in_gart--;
+ if (gt->in_gart == 0 && gt->stolen == 0) {
+ psb_gtt_remove(dev, gt);
+ psb_gtt_detach_pages(gt);
+ }
+ mutex_unlock(&dev_priv->gtt_mutex);
+}
+
+/*
+ * GTT resource allocator - allocate and manage GTT address space
+ */
+
+/**
+ * psb_gtt_alloc_range - allocate GTT address space
+ * @dev: Our DRM device
+ * @len: length (bytes) of address space required
+ * @name: resource name
+ * @backed: resource should be backed by stolen pages
+ *
+ * Ask the kernel core to find us a suitable range of addresses
+ * to use for a GTT mapping.
+ *
+ * Returns a gtt_range structure describing the object, or NULL on
+ * error. On successful return the resource is both allocated and marked
+ * as in use.
+ */
+struct gtt_range *psb_gtt_alloc_range(struct drm_device *dev, int len,
+ const char *name, int backed)
+{
+ struct drm_psb_private *dev_priv = dev->dev_private;
+ struct gtt_range *gt;
+ struct resource *r = dev_priv->gtt_mem;
+ int ret;
+ unsigned long start, end;
+
+ if (backed) {
+ /* The start of the GTT is the stolen pages */
+ start = r->start;
+ end = r->start + dev_priv->pg->stolen_size - 1;
+ } else {
+ /* The rest we will use for GEM backed objects */
+ start = r->start + dev_priv->pg->stolen_size;
+ end = r->end;
+ }
+
+ gt = kzalloc(sizeof(struct gtt_range), GFP_KERNEL);
+ if (gt == NULL)
+ return NULL;
+ gt->resource.name = name;
+ gt->stolen = backed;
+ gt->in_gart = backed;
+ /* Ensure this is set for non GEM objects */
+ gt->gem.dev = dev;
+ kref_init(>->kref);
+
+ ret = allocate_resource(dev_priv->gtt_mem, >->resource,
+ len, start, end, PAGE_SIZE, NULL, NULL);
+ if (ret == 0) {
+ gt->offset = gt->resource.start - r->start;
+ return gt;
+ }
+ kfree(gt);
+ return NULL;
+}
+
+/**
+ * psb_gtt_destroy - final free up of a gtt
+ * @kref: the kref of the gtt
+ *
+ * Called from the kernel kref put when the final reference to our
+ * GTT object is dropped. At that point we can free up the resources.
+ *
+ * For now we handle mmap clean up here to work around limits in GEM
+ */
+static void psb_gtt_destroy(struct kref *kref)
+{
+ struct gtt_range *gt = container_of(kref, struct gtt_range, kref);
+
+ /* Undo the mmap pin if we are destroying the object */
+ if (gt->mmapping) {
+ psb_gtt_unpin(gt);
+ gt->mmapping = 0;
+ }
+ WARN_ON(gt->in_gart && !gt->stolen);
+ release_resource(>->resource);
+ kfree(gt);
+}
+
+/**
+ * psb_gtt_kref_put - drop reference to a GTT object
+ * @gt: the GT being dropped
+ *
+ * Drop a reference to a psb gtt
+ */
+void psb_gtt_kref_put(struct gtt_range *gt)
+{
+ kref_put(>->kref, psb_gtt_destroy);
+}
+
+/**
+ * psb_gtt_free_range - release GTT address space
+ * @dev: our DRM device
+ * @gt: a mapping created with psb_gtt_alloc_range
+ *
+ * Release a resource that was allocated with psb_gtt_alloc_range
+ */
+void psb_gtt_free_range(struct drm_device *dev, struct gtt_range *gt)
+{
+ psb_gtt_kref_put(gt);
+}
+
+
struct psb_gtt *psb_gtt_alloc(struct drm_device *dev)
{
struct psb_gtt *tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
@@ -49,98 +382,89 @@
return tmp;
}
-void psb_gtt_takedown(struct psb_gtt *pg, int free)
+void psb_gtt_takedown(struct drm_device *dev)
{
- struct drm_psb_private *dev_priv = pg->dev->dev_private;
+ struct drm_psb_private *dev_priv = dev->dev_private;
- if (!pg)
- return;
-
- if (pg->gtt_map) {
- iounmap(pg->gtt_map);
- pg->gtt_map = NULL;
+ /* FIXME: iounmap dev_priv->vram_addr etc */
+ if (dev_priv->gtt_map) {
+ iounmap(dev_priv->gtt_map);
+ dev_priv->gtt_map = NULL;
}
- if (pg->initialized) {
- pci_write_config_word(pg->dev->pdev, PSB_GMCH_CTRL,
- pg->gmch_ctrl);
- PSB_WVDC32(pg->pge_ctl, PSB_PGETBL_CTL);
+ if (dev_priv->gtt_initialized) {
+ pci_write_config_word(dev->pdev, PSB_GMCH_CTRL,
+ dev_priv->gmch_ctrl);
+ PSB_WVDC32(dev_priv->pge_ctl, PSB_PGETBL_CTL);
(void) PSB_RVDC32(PSB_PGETBL_CTL);
}
- if (free)
- kfree(pg);
+ kfree(dev_priv->pg);
+ dev_priv->pg = NULL;
}
-int psb_gtt_init(struct psb_gtt *pg, int resume)
+int psb_gtt_init(struct drm_device *dev, int resume)
{
- struct drm_device *dev = pg->dev;
struct drm_psb_private *dev_priv = dev->dev_private;
unsigned gtt_pages;
- unsigned long stolen_size, vram_stolen_size, ci_stolen_size;
- unsigned long rar_stolen_size;
+ unsigned long stolen_size, vram_stolen_size;
unsigned i, num_pages;
unsigned pfn_base;
- uint32_t ci_pages, vram_pages;
+ uint32_t vram_pages;
uint32_t tt_pages;
uint32_t *ttm_gtt_map;
uint32_t dvmt_mode = 0;
+ struct psb_gtt *pg;
int ret = 0;
uint32_t pte;
- pci_read_config_word(dev->pdev, PSB_GMCH_CTRL, &pg->gmch_ctrl);
- pci_write_config_word(dev->pdev, PSB_GMCH_CTRL,
- pg->gmch_ctrl | _PSB_GMCH_ENABLED);
+ mutex_init(&dev_priv->gtt_mutex);
- pg->pge_ctl = PSB_RVDC32(PSB_PGETBL_CTL);
- PSB_WVDC32(pg->pge_ctl | _PSB_PGETBL_ENABLED, PSB_PGETBL_CTL);
+ dev_priv->pg = pg = psb_gtt_alloc(dev);
+ if (pg == NULL)
+ return -ENOMEM;
+
+ pci_read_config_word(dev->pdev, PSB_GMCH_CTRL, &dev_priv->gmch_ctrl);
+ pci_write_config_word(dev->pdev, PSB_GMCH_CTRL,
+ dev_priv->gmch_ctrl | _PSB_GMCH_ENABLED);
+
+ dev_priv->pge_ctl = PSB_RVDC32(PSB_PGETBL_CTL);
+ PSB_WVDC32(dev_priv->pge_ctl | _PSB_PGETBL_ENABLED, PSB_PGETBL_CTL);
(void) PSB_RVDC32(PSB_PGETBL_CTL);
- pg->initialized = 1;
+ /* The root resource we allocate address space from */
+ dev_priv->gtt_mem = &dev->pdev->resource[PSB_GATT_RESOURCE];
- pg->gtt_phys_start = pg->pge_ctl & PAGE_MASK;
+ dev_priv->gtt_initialized = 1;
+
+ pg->gtt_phys_start = dev_priv->pge_ctl & PAGE_MASK;
pg->gatt_start = pci_resource_start(dev->pdev, PSB_GATT_RESOURCE);
/* fix me: video mmu has hw bug to access 0x0D0000000,
* then make gatt start at 0x0e000,0000 */
- pg->mmu_gatt_start = PSB_MEM_TT_START;
+ pg->mmu_gatt_start = 0xE0000000;
pg->gtt_start = pci_resource_start(dev->pdev, PSB_GTT_RESOURCE);
gtt_pages =
pci_resource_len(dev->pdev, PSB_GTT_RESOURCE) >> PAGE_SHIFT;
pg->gatt_pages = pci_resource_len(dev->pdev, PSB_GATT_RESOURCE)
>> PAGE_SHIFT;
- pci_read_config_dword(dev->pdev, PSB_BSM, &pg->stolen_base);
- vram_stolen_size = pg->gtt_phys_start - pg->stolen_base - PAGE_SIZE;
+ pci_read_config_dword(dev->pdev, PSB_BSM, &dev_priv->stolen_base);
+ vram_stolen_size = pg->gtt_phys_start - dev_priv->stolen_base - PAGE_SIZE;
- /* CI is not included in the stolen size since the TOPAZ MMU bug */
- ci_stolen_size = dev_priv->ci_region_size;
- /* Don't add CI & RAR share buffer space
- * managed by TTM to stolen_size */
stolen_size = vram_stolen_size;
- rar_stolen_size = dev_priv->rar_region_size;
-
printk(KERN_INFO"GMMADR(region 0) start: 0x%08x (%dM).\n",
pg->gatt_start, pg->gatt_pages/256);
printk(KERN_INFO"GTTADR(region 3) start: 0x%08x (can map %dM RAM), and actual RAM base 0x%08x.\n",
pg->gtt_start, gtt_pages * 4, pg->gtt_phys_start);
- printk(KERN_INFO "Stole memory information\n");
- printk(KERN_INFO " base in RAM: 0x%x\n", pg->stolen_base);
- printk(KERN_INFO " size: %luK, calculated by (GTT RAM base) - (Stolen base), seems wrong\n",
+ printk(KERN_INFO "Stolen memory information\n");
+ printk(KERN_INFO " base in RAM: 0x%x\n", dev_priv->stolen_base);
+ printk(KERN_INFO " size: %luK, calculated by (GTT RAM base) - (Stolen base), seems wrong\n",
vram_stolen_size/1024);
- dvmt_mode = (pg->gmch_ctrl >> 4) & 0x7;
+ dvmt_mode = (dev_priv->gmch_ctrl >> 4) & 0x7;
printk(KERN_INFO " the correct size should be: %dM(dvmt mode=%d)\n",
(dvmt_mode == 1) ? 1 : (2 << (dvmt_mode - 1)), dvmt_mode);
- if (ci_stolen_size > 0)
- printk(KERN_INFO"CI Stole memory: RAM base = 0x%08x, size = %lu M\n",
- dev_priv->ci_region_start,
- ci_stolen_size / 1024 / 1024);
- if (rar_stolen_size > 0)
- printk(KERN_INFO "RAR Stole memory: RAM base = 0x%08x, size = %lu M\n",
- dev_priv->rar_region_start,
- rar_stolen_size / 1024 / 1024);
-
if (resume && (gtt_pages != pg->gtt_pages) &&
(stolen_size != pg->stolen_size)) {
DRM_ERROR("GTT resume error.\n");
@@ -150,42 +474,40 @@
pg->gtt_pages = gtt_pages;
pg->stolen_size = stolen_size;
- pg->vram_stolen_size = vram_stolen_size;
- pg->ci_stolen_size = ci_stolen_size;
- pg->rar_stolen_size = rar_stolen_size;
- pg->gtt_map =
+ dev_priv->vram_stolen_size = vram_stolen_size;
+ dev_priv->gtt_map =
ioremap_nocache(pg->gtt_phys_start, gtt_pages << PAGE_SHIFT);
- if (!pg->gtt_map) {
+ if (!dev_priv->gtt_map) {
DRM_ERROR("Failure to map gtt.\n");
ret = -ENOMEM;
goto out_err;
}
- pg->vram_addr = ioremap_wc(pg->stolen_base, stolen_size);
- if (!pg->vram_addr) {
+ dev_priv->vram_addr = ioremap_wc(dev_priv->stolen_base, stolen_size);
+ if (!dev_priv->vram_addr) {
DRM_ERROR("Failure to map stolen base.\n");
ret = -ENOMEM;
goto out_err;
}
- DRM_DEBUG("%s: vram kernel virtual address %p\n", pg->vram_addr);
+ DRM_DEBUG("%s: vram kernel virtual address %p\n", dev_priv->vram_addr);
tt_pages = (pg->gatt_pages < PSB_TT_PRIV0_PLIMIT) ?
(pg->gatt_pages) : PSB_TT_PRIV0_PLIMIT;
- ttm_gtt_map = pg->gtt_map + tt_pages / 2;
+ ttm_gtt_map = dev_priv->gtt_map + tt_pages / 2;
/*
* insert vram stolen pages.
*/
- pfn_base = pg->stolen_base >> PAGE_SHIFT;
+ pfn_base = dev_priv->stolen_base >> PAGE_SHIFT;
vram_pages = num_pages = vram_stolen_size >> PAGE_SHIFT;
printk(KERN_INFO"Set up %d stolen pages starting at 0x%08x, GTT offset %dK\n",
num_pages, pfn_base, 0);
for (i = 0; i < num_pages; ++i) {
pte = psb_gtt_mask_pte(pfn_base + i, 0);
- iowrite32(pte, pg->gtt_map + i);
+ iowrite32(pte, dev_priv->gtt_map + i);
}
/*
@@ -194,36 +516,9 @@
pfn_base = page_to_pfn(dev_priv->scratch_page);
pte = psb_gtt_mask_pte(pfn_base, 0);
for (; i < tt_pages / 2 - 1; ++i)
- iowrite32(pte, pg->gtt_map + i);
+ iowrite32(pte, dev_priv->gtt_map + i);
/*
- * insert CI stolen pages
- */
-
- pfn_base = dev_priv->ci_region_start >> PAGE_SHIFT;
- ci_pages = num_pages = ci_stolen_size >> PAGE_SHIFT;
- printk(KERN_INFO"Set up %d CI stolen pages starting at 0x%08x, GTT offset %dK\n",
- num_pages, pfn_base, (ttm_gtt_map - pg->gtt_map) * 4);
- for (i = 0; i < num_pages; ++i) {
- pte = psb_gtt_mask_pte(pfn_base + i, 0);
- iowrite32(pte, ttm_gtt_map + i);
- }
-
- /*
- * insert RAR stolen pages
- */
- if (rar_stolen_size != 0) {
- pfn_base = dev_priv->rar_region_start >> PAGE_SHIFT;
- num_pages = rar_stolen_size >> PAGE_SHIFT;
- printk(KERN_INFO"Set up %d RAR stolen pages starting at 0x%08x, GTT offset %dK\n",
- num_pages, pfn_base,
- (ttm_gtt_map - pg->gtt_map + i) * 4);
- for (; i < num_pages + ci_pages; ++i) {
- pte = psb_gtt_mask_pte(pfn_base + i - ci_pages, 0);
- iowrite32(pte, ttm_gtt_map + i);
- }
- }
- /*
* Init rest of gtt managed by TTM.
*/
@@ -234,801 +529,11 @@
for (; i < pg->gatt_pages - tt_pages / 2; ++i)
iowrite32(pte, ttm_gtt_map + i);
- (void) ioread32(pg->gtt_map + i - 1);
+ (void) ioread32(dev_priv->gtt_map + i - 1);
return 0;
out_err:
- psb_gtt_takedown(pg, 0);
+ psb_gtt_takedown(dev);
return ret;
}
-
-int psb_gtt_insert_pages(struct psb_gtt *pg, struct page **pages,
- unsigned offset_pages, unsigned num_pages,
- unsigned desired_tile_stride,
- unsigned hw_tile_stride, int type)
-{
- unsigned rows = 1;
- unsigned add;
- unsigned row_add;
- unsigned i;
- unsigned j;
- uint32_t *cur_page = NULL;
- uint32_t pte;
-
- if (hw_tile_stride)
- rows = num_pages / desired_tile_stride;
- else
- desired_tile_stride = num_pages;
-
- add = desired_tile_stride;
- row_add = hw_tile_stride;
-
- down_read(&pg->sem);
- for (i = 0; i < rows; ++i) {
- cur_page = pg->gtt_map + offset_pages;
- for (j = 0; j < desired_tile_stride; ++j) {
- pte =
- psb_gtt_mask_pte(page_to_pfn(*pages++), type);
- iowrite32(pte, cur_page++);
- }
- offset_pages += add;
- }
- (void) ioread32(cur_page - 1);
- up_read(&pg->sem);
-
- return 0;
-}
-
-int psb_gtt_insert_phys_addresses(struct psb_gtt *pg, dma_addr_t *pPhysFrames,
- unsigned offset_pages, unsigned num_pages, int type)
-{
- unsigned j;
- uint32_t *cur_page = NULL;
- uint32_t pte;
- u32 ba;
-
- down_read(&pg->sem);
- cur_page = pg->gtt_map + offset_pages;
- for (j = 0; j < num_pages; ++j) {
- ba = *pPhysFrames++;
- pte = psb_gtt_mask_pte(ba >> PAGE_SHIFT, type);
- iowrite32(pte, cur_page++);
- }
- (void) ioread32(cur_page - 1);
- up_read(&pg->sem);
- return 0;
-}
-
-int psb_gtt_remove_pages(struct psb_gtt *pg, unsigned offset_pages,
- unsigned num_pages, unsigned desired_tile_stride,
- unsigned hw_tile_stride, int rc_prot)
-{
- struct drm_psb_private *dev_priv = pg->dev->dev_private;
- unsigned rows = 1;
- unsigned add;
- unsigned row_add;
- unsigned i;
- unsigned j;
- uint32_t *cur_page = NULL;
- unsigned pfn_base = page_to_pfn(dev_priv->scratch_page);
- uint32_t pte = psb_gtt_mask_pte(pfn_base, 0);
-
- if (hw_tile_stride)
- rows = num_pages / desired_tile_stride;
- else
- desired_tile_stride = num_pages;
-
- add = desired_tile_stride;
- row_add = hw_tile_stride;
-
- if (rc_prot)
- down_read(&pg->sem);
- for (i = 0; i < rows; ++i) {
- cur_page = pg->gtt_map + offset_pages;
- for (j = 0; j < desired_tile_stride; ++j)
- iowrite32(pte, cur_page++);
-
- offset_pages += add;
- }
- (void) ioread32(cur_page - 1);
- if (rc_prot)
- up_read(&pg->sem);
-
- return 0;
-}
-
-int psb_gtt_mm_init(struct psb_gtt *pg)
-{
- struct psb_gtt_mm *gtt_mm;
- struct drm_psb_private *dev_priv = pg->dev->dev_private;
- struct drm_open_hash *ht;
- struct drm_mm *mm;
- int ret;
- uint32_t tt_start;
- uint32_t tt_size;
-
- if (!pg || !pg->initialized) {
- DRM_DEBUG("Invalid gtt struct\n");
- return -EINVAL;
- }
-
- gtt_mm = kzalloc(sizeof(struct psb_gtt_mm), GFP_KERNEL);
- if (!gtt_mm)
- return -ENOMEM;
-
- spin_lock_init(>t_mm->lock);
-
- ht = >t_mm->hash;
- ret = drm_ht_create(ht, 20);
- if (ret) {
- DRM_DEBUG("Create hash table failed(%d)\n", ret);
- goto err_free;
- }
-
- tt_start = (pg->stolen_size + PAGE_SIZE - 1) >> PAGE_SHIFT;
- tt_start = (tt_start < pg->gatt_pages) ? tt_start : pg->gatt_pages;
- tt_size = (pg->gatt_pages < PSB_TT_PRIV0_PLIMIT) ?
- (pg->gatt_pages) : PSB_TT_PRIV0_PLIMIT;
-
- mm = >t_mm->base;
-
- /*will use tt_start ~ 128M for IMG TT buffers*/
- ret = drm_mm_init(mm, tt_start, ((tt_size / 2) - tt_start));
- if (ret) {
- DRM_DEBUG("drm_mm_int error(%d)\n", ret);
- goto err_mm_init;
- }
-
- gtt_mm->count = 0;
-
- dev_priv->gtt_mm = gtt_mm;
-
- DRM_INFO("PSB GTT mem manager ready, tt_start %ld, tt_size %ld pages\n",
- (unsigned long)tt_start,
- (unsigned long)((tt_size / 2) - tt_start));
- return 0;
-err_mm_init:
- drm_ht_remove(ht);
-
-err_free:
- kfree(gtt_mm);
- return ret;
-}
-
-/**
- * Delete all hash entries;
- */
-void psb_gtt_mm_takedown(void)
-{
- return;
-}
-
-static int psb_gtt_mm_get_ht_by_pid_locked(struct psb_gtt_mm *mm,
- u32 tgid,
- struct psb_gtt_hash_entry **hentry)
-{
- struct drm_hash_item *entry;
- struct psb_gtt_hash_entry *psb_entry;
- int ret;
-
- ret = drm_ht_find_item(&mm->hash, tgid, &entry);
- if (ret) {
- DRM_DEBUG("Cannot find entry pid=%ld\n", tgid);
- return ret;
- }
-
- psb_entry = container_of(entry, struct psb_gtt_hash_entry, item);
- if (!psb_entry) {
- DRM_DEBUG("Invalid entry");
- return -EINVAL;
- }
-
- *hentry = psb_entry;
- return 0;
-}
-
-
-static int psb_gtt_mm_insert_ht_locked(struct psb_gtt_mm *mm,
- u32 tgid,
- struct psb_gtt_hash_entry *hentry)
-{
- struct drm_hash_item *item;
- int ret;
-
- if (!hentry) {
- DRM_DEBUG("Invalid parameters\n");
- return -EINVAL;
- }
-
- item = &hentry->item;
- item->key = tgid;
-
- /**
- * NOTE: drm_ht_insert_item will perform such a check
- ret = psb_gtt_mm_get_ht_by_pid(mm, tgid, &tmp);
- if (!ret) {
- DRM_DEBUG("Entry already exists for pid %ld\n", tgid);
- return -EAGAIN;
- }
- */
-
- /*Insert the given entry*/
- ret = drm_ht_insert_item(&mm->hash, item);
- if (ret) {
- DRM_DEBUG("Insert failure\n");
- return ret;
- }
-
- mm->count++;
-
- return 0;
-}
-
-static int psb_gtt_mm_alloc_insert_ht(struct psb_gtt_mm *mm,
- u32 tgid,
- struct psb_gtt_hash_entry **entry)
-{
- struct psb_gtt_hash_entry *hentry;
- int ret;
-
- /*if the hentry for this tgid exists, just get it and return*/
- spin_lock(&mm->lock);
- ret = psb_gtt_mm_get_ht_by_pid_locked(mm, tgid, &hentry);
- if (!ret) {
- DRM_DEBUG("Entry for tgid %ld exist, hentry %p\n",
- tgid, hentry);
- *entry = hentry;
- spin_unlock(&mm->lock);
- return 0;
- }
- spin_unlock(&mm->lock);
-
- DRM_DEBUG("Entry for tgid %ld doesn't exist, will create it\n", tgid);
-
- hentry = kzalloc(sizeof(struct psb_gtt_hash_entry), GFP_KERNEL);
- if (!hentry) {
- DRM_DEBUG("Kmalloc failled\n");
- return -ENOMEM;
- }
-
- ret = drm_ht_create(&hentry->ht, 20);
- if (ret) {
- DRM_DEBUG("Create hash table failed\n");
- return ret;
- }
-
- spin_lock(&mm->lock);
- ret = psb_gtt_mm_insert_ht_locked(mm, tgid, hentry);
- spin_unlock(&mm->lock);
-
- if (!ret)
- *entry = hentry;
-
- return ret;
-}
-
-static struct psb_gtt_hash_entry *
-psb_gtt_mm_remove_ht_locked(struct psb_gtt_mm *mm, u32 tgid)
-{
- struct psb_gtt_hash_entry *tmp;
- int ret;
-
- ret = psb_gtt_mm_get_ht_by_pid_locked(mm, tgid, &tmp);
- if (ret) {
- DRM_DEBUG("Cannot find entry pid %ld\n", tgid);
- return NULL;
- }
-
- /*remove it from ht*/
- drm_ht_remove_item(&mm->hash, &tmp->item);
-
- mm->count--;
-
- return tmp;
-}
-
-static int psb_gtt_mm_remove_free_ht_locked(struct psb_gtt_mm *mm, u32 tgid)
-{
- struct psb_gtt_hash_entry *entry;
-
- entry = psb_gtt_mm_remove_ht_locked(mm, tgid);
-
- if (!entry) {
- DRM_DEBUG("Invalid entry");
- return -EINVAL;
- }
-
- /*delete ht*/
- drm_ht_remove(&entry->ht);
-
- /*free this entry*/
- kfree(entry);
- return 0;
-}
-
-static int
-psb_gtt_mm_get_mem_mapping_locked(struct drm_open_hash *ht,
- u32 key,
- struct psb_gtt_mem_mapping **hentry)
-{
- struct drm_hash_item *entry;
- struct psb_gtt_mem_mapping *mapping;
- int ret;
-
- ret = drm_ht_find_item(ht, key, &entry);
- if (ret) {
- DRM_DEBUG("Cannot find key %ld\n", key);
- return ret;
- }
-
- mapping = container_of(entry, struct psb_gtt_mem_mapping, item);
- if (!mapping) {
- DRM_DEBUG("Invalid entry\n");
- return -EINVAL;
- }
-
- *hentry = mapping;
- return 0;
-}
-
-static int
-psb_gtt_mm_insert_mem_mapping_locked(struct drm_open_hash *ht,
- u32 key,
- struct psb_gtt_mem_mapping *hentry)
-{
- struct drm_hash_item *item;
- struct psb_gtt_hash_entry *entry;
- int ret;
-
- if (!hentry) {
- DRM_DEBUG("hentry is NULL\n");
- return -EINVAL;
- }
-
- item = &hentry->item;
- item->key = key;
-
- ret = drm_ht_insert_item(ht, item);
- if (ret) {
- DRM_DEBUG("insert_item failed\n");
- return ret;
- }
-
- entry = container_of(ht, struct psb_gtt_hash_entry, ht);
- if (entry)
- entry->count++;
-
- return 0;
-}
-
-static int
-psb_gtt_mm_alloc_insert_mem_mapping(struct psb_gtt_mm *mm,
- struct drm_open_hash *ht,
- u32 key,
- struct drm_mm_node *node,
- struct psb_gtt_mem_mapping **entry)
-{
- struct psb_gtt_mem_mapping *mapping;
- int ret;
-
- if (!node || !ht) {
- DRM_DEBUG("parameter error\n");
- return -EINVAL;
- }
-
- /*try to get this mem_map */
- spin_lock(&mm->lock);
- ret = psb_gtt_mm_get_mem_mapping_locked(ht, key, &mapping);
- if (!ret) {
- DRM_DEBUG("mapping entry for key %ld exists, entry %p\n",
- key, mapping);
- *entry = mapping;
- spin_unlock(&mm->lock);
- return 0;
- }
- spin_unlock(&mm->lock);
-
- DRM_DEBUG("Mapping entry for key %ld doesn't exist, will create it\n",
- key);
-
- mapping = kzalloc(sizeof(struct psb_gtt_mem_mapping), GFP_KERNEL);
- if (!mapping) {
- DRM_DEBUG("kmalloc failed\n");
- return -ENOMEM;
- }
-
- mapping->node = node;
-
- spin_lock(&mm->lock);
- ret = psb_gtt_mm_insert_mem_mapping_locked(ht, key, mapping);
- spin_unlock(&mm->lock);
-
- if (!ret)
- *entry = mapping;
-
- return ret;
-}
-
-static struct psb_gtt_mem_mapping *
-psb_gtt_mm_remove_mem_mapping_locked(struct drm_open_hash *ht, u32 key)
-{
- struct psb_gtt_mem_mapping *tmp;
- struct psb_gtt_hash_entry *entry;
- int ret;
-
- ret = psb_gtt_mm_get_mem_mapping_locked(ht, key, &tmp);
- if (ret) {
- DRM_DEBUG("Cannot find key %ld\n", key);
- return NULL;
- }
-
- drm_ht_remove_item(ht, &tmp->item);
-
- entry = container_of(ht, struct psb_gtt_hash_entry, ht);
- if (entry)
- entry->count--;
-
- return tmp;
-}
-
-static int psb_gtt_mm_remove_free_mem_mapping_locked(struct drm_open_hash *ht,
- u32 key,
- struct drm_mm_node **node)
-{
- struct psb_gtt_mem_mapping *entry;
-
- entry = psb_gtt_mm_remove_mem_mapping_locked(ht, key);
- if (!entry) {
- DRM_DEBUG("entry is NULL\n");
- return -EINVAL;
- }
-
- *node = entry->node;
-
- kfree(entry);
- return 0;
-}
-
-static int psb_gtt_add_node(struct psb_gtt_mm *mm,
- u32 tgid,
- u32 key,
- struct drm_mm_node *node,
- struct psb_gtt_mem_mapping **entry)
-{
- struct psb_gtt_hash_entry *hentry;
- struct psb_gtt_mem_mapping *mapping;
- int ret;
-
- ret = psb_gtt_mm_alloc_insert_ht(mm, tgid, &hentry);
- if (ret) {
- DRM_DEBUG("alloc_insert failed\n");
- return ret;
- }
-
- ret = psb_gtt_mm_alloc_insert_mem_mapping(mm,
- &hentry->ht,
- key,
- node,
- &mapping);
- if (ret) {
- DRM_DEBUG("mapping alloc_insert failed\n");
- return ret;
- }
-
- *entry = mapping;
-
- return 0;
-}
-
-static int psb_gtt_remove_node(struct psb_gtt_mm *mm,
- u32 tgid,
- u32 key,
- struct drm_mm_node **node)
-{
- struct psb_gtt_hash_entry *hentry;
- struct drm_mm_node *tmp;
- int ret;
-
- spin_lock(&mm->lock);
- ret = psb_gtt_mm_get_ht_by_pid_locked(mm, tgid, &hentry);
- if (ret) {
- DRM_DEBUG("Cannot find entry for pid %ld\n", tgid);
- spin_unlock(&mm->lock);
- return ret;
- }
- spin_unlock(&mm->lock);
-
- /*remove mapping entry*/
- spin_lock(&mm->lock);
- ret = psb_gtt_mm_remove_free_mem_mapping_locked(&hentry->ht,
- key,
- &tmp);
- if (ret) {
- DRM_DEBUG("remove_free failed\n");
- spin_unlock(&mm->lock);
- return ret;
- }
-
- *node = tmp;
-
- /*check the count of mapping entry*/
- if (!hentry->count) {
- DRM_DEBUG("count of mapping entry is zero, tgid=%ld\n", tgid);
- psb_gtt_mm_remove_free_ht_locked(mm, tgid);
- }
-
- spin_unlock(&mm->lock);
-
- return 0;
-}
-
-static int psb_gtt_mm_alloc_mem(struct psb_gtt_mm *mm,
- uint32_t pages,
- uint32_t align,
- struct drm_mm_node **node)
-{
- struct drm_mm_node *tmp_node;
- int ret;
-
- do {
- ret = drm_mm_pre_get(&mm->base);
- if (unlikely(ret)) {
- DRM_DEBUG("drm_mm_pre_get error\n");
- return ret;
- }
-
- spin_lock(&mm->lock);
- tmp_node = drm_mm_search_free(&mm->base, pages, align, 1);
- if (unlikely(!tmp_node)) {
- DRM_DEBUG("No free node found\n");
- spin_unlock(&mm->lock);
- break;
- }
-
- tmp_node = drm_mm_get_block_atomic(tmp_node, pages, align);
- spin_unlock(&mm->lock);
- } while (!tmp_node);
-
- if (!tmp_node) {
- DRM_DEBUG("Node allocation failed\n");
- return -ENOMEM;
- }
-
- *node = tmp_node;
- return 0;
-}
-
-static void psb_gtt_mm_free_mem(struct psb_gtt_mm *mm, struct drm_mm_node *node)
-{
- spin_lock(&mm->lock);
- drm_mm_put_block(node);
- spin_unlock(&mm->lock);
-}
-
-int psb_gtt_map_meminfo(struct drm_device *dev,
- void *hKernelMemInfo,
- uint32_t *offset)
-{
- return -EINVAL;
- /* FIXMEAC */
-#if 0
- struct drm_psb_private *dev_priv
- = (struct drm_psb_private *)dev->dev_private;
- void *psKernelMemInfo;
- struct psb_gtt_mm *mm = dev_priv->gtt_mm;
- struct psb_gtt *pg = dev_priv->pg;
- uint32_t size, pages, offset_pages;
- void *kmem;
- struct drm_mm_node *node;
- struct page **page_list;
- struct psb_gtt_mem_mapping *mapping = NULL;
- int ret;
-
- ret = psb_get_meminfo_by_handle(hKernelMemInfo, &psKernelMemInfo);
- if (ret) {
- DRM_DEBUG("Cannot find kernelMemInfo handle %ld\n",
- hKernelMemInfo);
- return -EINVAL;
- }
-
- DRM_DEBUG("Got psKernelMemInfo %p for handle %lx\n",
- psKernelMemInfo, (u32)hKernelMemInfo);
- size = psKernelMemInfo->ui32AllocSize;
- kmem = psKernelMemInfo->pvLinAddrKM;
- pages = (size + PAGE_SIZE - 1) >> PAGE_SHIFT;
-
- DRM_DEBUG("KerMemInfo size %ld, cpuVadr %lx, pages %ld, osMemHdl %lx\n",
- size, kmem, pages, psKernelMemInfo->sMemBlk.hOSMemHandle);
-
- if (!kmem)
- DRM_DEBUG("kmem is NULL");
-
- /*get pages*/
- ret = psb_get_pages_by_mem_handle(psKernelMemInfo->sMemBlk.hOSMemHandle,
- &page_list);
- if (ret) {
- DRM_DEBUG("get pages error\n");
- return ret;
- }
-
- DRM_DEBUG("get %ld pages\n", pages);
-
- /*alloc memory in TT apeture*/
- ret = psb_gtt_mm_alloc_mem(mm, pages, 0, &node);
- if (ret) {
- DRM_DEBUG("alloc TT memory error\n");
- goto failed_pages_alloc;
- }
-
- /*update psb_gtt_mm*/
- ret = psb_gtt_add_node(mm,
- task_tgid_nr(current),
- (u32)hKernelMemInfo,
- node,
- &mapping);
- if (ret) {
- DRM_DEBUG("add_node failed");
- goto failed_add_node;
- }
-
- node = mapping->node;
- offset_pages = node->start;
-
- DRM_DEBUG("get free node for %ld pages, offset %ld pages",
- pages, offset_pages);
-
- /*update gtt*/
- psb_gtt_insert_pages(pg, page_list,
- (unsigned)offset_pages,
- (unsigned)pages,
- 0,
- 0,
- 0);
-
- *offset = offset_pages;
- return 0;
-
-failed_add_node:
- psb_gtt_mm_free_mem(mm, node);
-failed_pages_alloc:
- kfree(page_list);
- return ret;
-#endif
-}
-
-int psb_gtt_unmap_meminfo(struct drm_device *dev, void * hKernelMemInfo)
-{
- struct drm_psb_private *dev_priv
- = (struct drm_psb_private *)dev->dev_private;
- struct psb_gtt_mm *mm = dev_priv->gtt_mm;
- struct psb_gtt *pg = dev_priv->pg;
- uint32_t pages, offset_pages;
- struct drm_mm_node *node;
- int ret;
-
- ret = psb_gtt_remove_node(mm,
- task_tgid_nr(current),
- (u32)hKernelMemInfo,
- &node);
- if (ret) {
- DRM_DEBUG("remove node failed\n");
- return ret;
- }
-
- /*remove gtt entries*/
- offset_pages = node->start;
- pages = node->size;
-
- psb_gtt_remove_pages(pg, offset_pages, pages, 0, 0, 1);
-
-
- /*free tt node*/
-
- psb_gtt_mm_free_mem(mm, node);
- return 0;
-}
-
-int psb_gtt_map_meminfo_ioctl(struct drm_device *dev, void *data,
- struct drm_file *file_priv)
-{
- struct psb_gtt_mapping_arg *arg
- = (struct psb_gtt_mapping_arg *)data;
- uint32_t *offset_pages = &arg->offset_pages;
-
- DRM_DEBUG("\n");
-
- return psb_gtt_map_meminfo(dev, arg->hKernelMemInfo, offset_pages);
-}
-
-int psb_gtt_unmap_meminfo_ioctl(struct drm_device *dev, void *data,
- struct drm_file *file_priv)
-{
-
- struct psb_gtt_mapping_arg *arg
- = (struct psb_gtt_mapping_arg *)data;
-
- DRM_DEBUG("\n");
-
- return psb_gtt_unmap_meminfo(dev, arg->hKernelMemInfo);
-}
-
-int psb_gtt_map_pvr_memory(struct drm_device *dev, unsigned int hHandle,
- unsigned int ui32TaskId, dma_addr_t *pPages,
- unsigned int ui32PagesNum, unsigned int *ui32Offset)
-{
- struct drm_psb_private *dev_priv = dev->dev_private;
- struct psb_gtt_mm *mm = dev_priv->gtt_mm;
- struct psb_gtt *pg = dev_priv->pg;
- uint32_t size, pages, offset_pages;
- struct drm_mm_node *node = NULL;
- struct psb_gtt_mem_mapping *mapping = NULL;
- int ret;
-
- size = ui32PagesNum * PAGE_SIZE;
- pages = 0;
-
- /*alloc memory in TT apeture*/
- ret = psb_gtt_mm_alloc_mem(mm, ui32PagesNum, 0, &node);
- if (ret) {
- DRM_DEBUG("alloc TT memory error\n");
- goto failed_pages_alloc;
- }
-
- /*update psb_gtt_mm*/
- ret = psb_gtt_add_node(mm,
- (u32)ui32TaskId,
- (u32)hHandle,
- node,
- &mapping);
- if (ret) {
- DRM_DEBUG("add_node failed");
- goto failed_add_node;
- }
-
- node = mapping->node;
- offset_pages = node->start;
-
- DRM_DEBUG("get free node for %ld pages, offset %ld pages",
- pages, offset_pages);
-
- /*update gtt*/
- psb_gtt_insert_phys_addresses(pg, pPages, (unsigned)offset_pages,
- (unsigned)ui32PagesNum, 0);
-
- *ui32Offset = offset_pages;
- return 0;
-
-failed_add_node:
- psb_gtt_mm_free_mem(mm, node);
-failed_pages_alloc:
- return ret;
-}
-
-
-int psb_gtt_unmap_pvr_memory(struct drm_device *dev, unsigned int hHandle,
- unsigned int ui32TaskId)
-{
- struct drm_psb_private *dev_priv = dev->dev_private;
- struct psb_gtt_mm *mm = dev_priv->gtt_mm;
- struct psb_gtt *pg = dev_priv->pg;
- uint32_t pages, offset_pages;
- struct drm_mm_node *node;
- int ret;
-
- ret = psb_gtt_remove_node(mm, (u32)ui32TaskId, (u32)hHandle, &node);
- if (ret) {
- printk(KERN_ERR "remove node failed\n");
- return ret;
- }
-
- /*remove gtt entries*/
- offset_pages = node->start;
- pages = node->size;
-
- psb_gtt_remove_pages(pg, offset_pages, pages, 0, 0, 1);
-
- /*free tt node*/
- psb_gtt_mm_free_mem(mm, node);
- return 0;
-}
diff --git a/drivers/staging/gma500/psb_gtt.h b/drivers/staging/gma500/psb_gtt.h
index 0272f83..535ae00 100644
--- a/drivers/staging/gma500/psb_gtt.h
+++ b/drivers/staging/gma500/psb_gtt.h
@@ -22,84 +22,40 @@
#include <drm/drmP.h>
-/*#include "img_types.h"*/
-
struct psb_gtt {
struct drm_device *dev;
- int initialized;
uint32_t gatt_start;
uint32_t mmu_gatt_start;
- uint32_t ci_start;
- uint32_t rar_start;
uint32_t gtt_start;
uint32_t gtt_phys_start;
unsigned gtt_pages;
unsigned gatt_pages;
- uint32_t stolen_base;
- void *vram_addr;
- uint32_t pge_ctl;
- u16 gmch_ctrl;
unsigned long stolen_size;
unsigned long vram_stolen_size;
- unsigned long ci_stolen_size;
- unsigned long rar_stolen_size;
- uint32_t *gtt_map;
struct rw_semaphore sem;
};
-struct psb_gtt_mm {
- struct drm_mm base;
- struct drm_open_hash hash;
- uint32_t count;
- spinlock_t lock;
-};
-
-struct psb_gtt_hash_entry {
- struct drm_open_hash ht;
- uint32_t count;
- struct drm_hash_item item;
-};
-
-struct psb_gtt_mem_mapping {
- struct drm_mm_node *node;
- struct drm_hash_item item;
-};
-
/*Exported functions*/
-extern int psb_gtt_init(struct psb_gtt *pg, int resume);
-extern int psb_gtt_insert_pages(struct psb_gtt *pg, struct page **pages,
- unsigned offset_pages, unsigned num_pages,
- unsigned desired_tile_stride,
- unsigned hw_tile_stride, int type);
-extern int psb_gtt_remove_pages(struct psb_gtt *pg, unsigned offset_pages,
- unsigned num_pages,
- unsigned desired_tile_stride,
- unsigned hw_tile_stride,
- int rc_prot);
+extern int psb_gtt_init(struct drm_device *dev, int resume);
+extern void psb_gtt_takedown(struct drm_device *dev);
-extern struct psb_gtt *psb_gtt_alloc(struct drm_device *dev);
-extern void psb_gtt_takedown(struct psb_gtt *pg, int free);
-extern int psb_gtt_map_meminfo(struct drm_device *dev,
- void * hKernelMemInfo,
- uint32_t *offset);
-extern int psb_gtt_unmap_meminfo(struct drm_device *dev,
- void * hKernelMemInfo);
-extern int psb_gtt_map_meminfo_ioctl(struct drm_device *dev, void *data,
- struct drm_file *file_priv);
-extern int psb_gtt_unmap_meminfo_ioctl(struct drm_device *dev, void *data,
- struct drm_file *file_priv);
-extern int psb_gtt_mm_init(struct psb_gtt *pg);
-extern void psb_gtt_mm_takedown(void);
+/* Each gtt_range describes an allocation in the GTT area */
+struct gtt_range {
+ struct resource resource;
+ u32 offset;
+ struct kref kref;
+ struct drm_gem_object gem; /* GEM high level stuff */
+ int in_gart; /* Currently in the GART (ref ct) */
+ bool stolen; /* Backed from stolen RAM */
+ bool mmapping; /* Is mmappable */
+ struct page **pages; /* Backing pages if present */
+};
-extern int psb_gtt_map_pvr_memory(struct drm_device *dev,
- unsigned int hHandle,
- unsigned int ui32TaskId,
- dma_addr_t *pPages,
- unsigned int ui32PagesNum,
- unsigned int *ui32Offset);
-
-extern int psb_gtt_unmap_pvr_memory(struct drm_device *dev,
- unsigned int hHandle,
- unsigned int ui32TaskId);
+extern struct gtt_range *psb_gtt_alloc_range(struct drm_device *dev, int len,
+ const char *name, int backed);
+extern void psb_gtt_kref_put(struct gtt_range *gt);
+extern void psb_gtt_free_range(struct drm_device *dev, struct gtt_range *gt);
+extern int psb_gtt_pin(struct gtt_range *gt);
+extern void psb_gtt_unpin(struct gtt_range *gt);
#endif
diff --git a/drivers/staging/gma500/psb_intel_display.c b/drivers/staging/gma500/psb_intel_display.c
index 80b37f4..4f47d09 100644
--- a/drivers/staging/gma500/psb_intel_display.c
+++ b/drivers/staging/gma500/psb_intel_display.c
@@ -341,9 +341,8 @@
/* struct drm_i915_master_private *master_priv; */
struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
struct psb_framebuffer *psbfb = to_psb_fb(crtc->fb);
- struct psb_intel_mode_device *mode_dev = psb_intel_crtc->mode_dev;
int pipe = psb_intel_crtc->pipe;
- unsigned long Start, Offset;
+ unsigned long start, offset;
int dspbase = (pipe == 0 ? DSPABASE : DSPBBASE);
int dspsurf = (pipe == 0 ? DSPASURF : DSPBSURF);
int dspstride = (pipe == 0) ? DSPASTRIDE : DSPBSTRIDE;
@@ -359,12 +358,17 @@
return 0;
}
- if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND,
- OSPM_UHB_FORCE_POWER_ON))
+ if (!gma_power_begin(dev, true))
return 0;
- Start = mode_dev->bo_offset(dev, psbfb);
- Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
+ /* We are displaying this buffer, make sure it is actually loaded
+ into the GTT */
+ ret = psb_gtt_pin(psbfb->gtt);
+ if (ret < 0)
+ goto psb_intel_pipe_set_base_exit;
+ start = psbfb->gtt->offset;
+
+ offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
REG_WRITE(dspstride, crtc->fb->pitch);
@@ -388,25 +392,29 @@
default:
DRM_ERROR("Unknown color depth\n");
ret = -EINVAL;
+ psb_gtt_unpin(psbfb->gtt);
goto psb_intel_pipe_set_base_exit;
}
REG_WRITE(dspcntr_reg, dspcntr);
- DRM_DEBUG("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
+
+ DRM_DEBUG("Writing base %08lX %08lX %d %d\n", start, offset, x, y);
if (0 /* FIXMEAC - check what PSB needs */) {
- REG_WRITE(dspbase, Offset);
+ REG_WRITE(dspbase, offset);
REG_READ(dspbase);
- REG_WRITE(dspsurf, Start);
+ REG_WRITE(dspsurf, start);
REG_READ(dspsurf);
} else {
- REG_WRITE(dspbase, Start + Offset);
+ REG_WRITE(dspbase, start + offset);
REG_READ(dspbase);
}
+ /* If there was a previous display we can now unpin it */
+ if (old_fb)
+ psb_gtt_unpin(to_psb_fb(old_fb)->gtt);
+
psb_intel_pipe_set_base_exit:
-
- ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
-
+ gma_power_end(dev);
return ret;
}
@@ -816,8 +824,7 @@
return;
}
- if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND,
- OSPM_UHB_ONLY_IF_ON)) {
+ if (gma_power_begin(dev, false)) {
for (i = 0; i < 256; i++) {
REG_WRITE(palreg + 4 * i,
((psb_intel_crtc->lut_r[i] +
@@ -827,7 +834,7 @@
(psb_intel_crtc->lut_b[i] +
psb_intel_crtc->lut_adj[i]));
}
- ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
+ gma_power_end(dev);
} else {
for (i = 0; i < 256; i++) {
dev_priv->save_palette_a[i] =
@@ -1022,19 +1029,14 @@
uint32_t width, uint32_t height)
{
struct drm_device *dev = crtc->dev;
- struct drm_psb_private *dev_priv =
- (struct drm_psb_private *)dev->dev_private;
- struct psb_gtt *pg = dev_priv->pg;
struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
- struct psb_intel_mode_device *mode_dev = psb_intel_crtc->mode_dev;
int pipe = psb_intel_crtc->pipe;
uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
uint32_t temp;
size_t addr = 0;
- uint32_t page_offset;
- size_t size;
- void *bo;
+ struct gtt_range *gt;
+ struct drm_gem_object *obj;
int ret;
DRM_DEBUG("\n");
@@ -1043,22 +1045,21 @@
if (!handle) {
DRM_DEBUG("cursor off\n");
/* turn off the cursor */
- temp = 0;
- temp |= CURSOR_MODE_DISABLE;
+ temp = CURSOR_MODE_DISABLE;
- if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND,
- OSPM_UHB_ONLY_IF_ON)) {
+ if (gma_power_begin(dev, false)) {
REG_WRITE(control, temp);
REG_WRITE(base, 0);
- ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
+ gma_power_end(dev);
}
- /* unpin the old bo */
- if (psb_intel_crtc->cursor_bo) {
- mode_dev->bo_unpin_for_scanout(dev,
- psb_intel_crtc->
- cursor_bo);
- psb_intel_crtc->cursor_bo = NULL;
+ /* Unpin the old GEM object */
+ if (psb_intel_crtc->cursor_obj) {
+ gt = container_of(psb_intel_crtc->cursor_obj,
+ struct gtt_range, gem);
+ psb_gtt_unpin(gt);
+ drm_gem_object_unreference(psb_intel_crtc->cursor_obj);
+ psb_intel_crtc->cursor_obj = NULL;
}
return 0;
@@ -1070,32 +1071,26 @@
return -EINVAL;
}
- bo = mode_dev->bo_from_handle(dev, file_priv, handle);
- if (!bo)
+ obj = drm_gem_object_lookup(dev, file_priv, handle);
+ if (!obj)
return -ENOENT;
- ret = mode_dev->bo_pin_for_scanout(dev, bo);
- if (ret)
- return ret;
- size = mode_dev->bo_size(dev, bo);
- if (size < width * height * 4) {
+ if (obj->size < width * height * 4) {
DRM_ERROR("buffer is to small\n");
return -ENOMEM;
}
- /*insert this bo into gtt*/
- DRM_DEBUG("%s: map meminfo for hw cursor. handle %x\n",
- __func__, handle);
+ gt = container_of(obj, struct gtt_range, gem);
- ret = psb_gtt_map_meminfo(dev, (void *)handle, &page_offset);
+ /* Pin the memory into the GTT */
+ ret = psb_gtt_pin(gt);
if (ret) {
- DRM_ERROR("Can not map meminfo to GTT. handle 0x%x\n", handle);
+ DRM_ERROR("Can not pin down handle 0x%x\n", handle);
return ret;
}
- addr = page_offset << PAGE_SHIFT;
- addr += pg->stolen_base;
+ addr = gt->offset; /* Or resource.start ??? */
psb_intel_crtc->cursor_addr = addr;
@@ -1104,17 +1099,19 @@
temp |= (pipe << 28);
temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
- if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND,
- OSPM_UHB_ONLY_IF_ON)) {
+ if (gma_power_begin(dev, false)) {
REG_WRITE(control, temp);
REG_WRITE(base, addr);
- ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
+ gma_power_end(dev);
}
/* unpin the old bo */
- if (psb_intel_crtc->cursor_bo && psb_intel_crtc->cursor_bo != bo) {
- mode_dev->bo_unpin_for_scanout(dev, psb_intel_crtc->cursor_bo);
- psb_intel_crtc->cursor_bo = bo;
+ if (psb_intel_crtc->cursor_obj && psb_intel_crtc->cursor_obj != obj) {
+ gt = container_of(psb_intel_crtc->cursor_obj,
+ struct gtt_range, gem);
+ psb_gtt_unpin(gt);
+ drm_gem_object_unreference(psb_intel_crtc->cursor_obj);
+ psb_intel_crtc->cursor_obj = obj;
}
return 0;
@@ -1126,7 +1123,7 @@
struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
int pipe = psb_intel_crtc->pipe;
uint32_t temp = 0;
- uint32_t adder;
+ uint32_t addr;
if (x < 0) {
@@ -1141,13 +1138,12 @@
temp |= ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT);
temp |= ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
- adder = psb_intel_crtc->cursor_addr;
+ addr = psb_intel_crtc->cursor_addr;
- if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND,
- OSPM_UHB_ONLY_IF_ON)) {
+ if (gma_power_begin(dev, false)) {
REG_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
- REG_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
- ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
+ REG_WRITE((pipe == 0) ? CURABASE : CURBBASE, addr);
+ gma_power_end(dev);
}
return 0;
}
@@ -1197,15 +1193,14 @@
bool is_lvds;
struct drm_psb_private *dev_priv = dev->dev_private;
- if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND,
- OSPM_UHB_ONLY_IF_ON)) {
+ if (gma_power_begin(dev, false)) {
dpll = REG_READ((pipe == 0) ? DPLL_A : DPLL_B);
if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
fp = REG_READ((pipe == 0) ? FPA0 : FPB0);
else
fp = REG_READ((pipe == 0) ? FPA1 : FPB1);
is_lvds = (pipe == 1) && (REG_READ(LVDS) & LVDS_PORT_EN);
- ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
+ gma_power_end(dev);
} else {
dpll = (pipe == 0) ?
dev_priv->saveDPLL_A : dev_priv->saveDPLL_B;
@@ -1277,13 +1272,12 @@
int vsync;
struct drm_psb_private *dev_priv = dev->dev_private;
- if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND,
- OSPM_UHB_ONLY_IF_ON)) {
+ if (gma_power_begin(dev, false)) {
htot = REG_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
hsync = REG_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
vtot = REG_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
vsync = REG_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
- ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
+ gma_power_end(dev);
} else {
htot = (pipe == 0) ?
dev_priv->saveHTOTAL_A : dev_priv->saveHTOTAL_B;
@@ -1318,7 +1312,16 @@
static void psb_intel_crtc_destroy(struct drm_crtc *crtc)
{
struct psb_intel_crtc *psb_intel_crtc = to_psb_intel_crtc(crtc);
+ struct gtt_range *gt;
+ /* Unpin the old GEM object */
+ if (psb_intel_crtc->cursor_obj) {
+ gt = container_of(psb_intel_crtc->cursor_obj,
+ struct gtt_range, gem);
+ psb_gtt_unpin(gt);
+ drm_gem_object_unreference(psb_intel_crtc->cursor_obj);
+ psb_intel_crtc->cursor_obj = NULL;
+ }
kfree(psb_intel_crtc->crtc_state);
drm_crtc_cleanup(crtc);
kfree(psb_intel_crtc);
@@ -1333,10 +1336,6 @@
.commit = psb_intel_crtc_commit,
};
-static const struct drm_crtc_helper_funcs mrst_helper_funcs;
-static const struct drm_crtc_helper_funcs mdfld_helper_funcs;
-const struct drm_crtc_funcs mdfld_intel_crtc_funcs;
-
const struct drm_crtc_funcs psb_intel_crtc_funcs = {
.save = psb_intel_crtc_save,
.restore = psb_intel_crtc_restore,
@@ -1397,7 +1396,11 @@
psb_intel_crtc->mode_dev = mode_dev;
psb_intel_crtc->cursor_addr = 0;
- drm_crtc_helper_add(&psb_intel_crtc->base,
+ if (IS_MRST(dev))
+ drm_crtc_helper_add(&psb_intel_crtc->base,
+ &mrst_helper_funcs);
+ else
+ drm_crtc_helper_add(&psb_intel_crtc->base,
&psb_intel_helper_funcs);
/* Setup the array of drm_connector pointer array */
diff --git a/drivers/staging/gma500/psb_intel_drv.h b/drivers/staging/gma500/psb_intel_drv.h
index f6229c5..6006ddd 100644
--- a/drivers/staging/gma500/psb_intel_drv.h
+++ b/drivers/staging/gma500/psb_intel_drv.h
@@ -76,13 +76,7 @@
/*
* Abstracted memory manager operations
*/
- void *(*bo_from_handle) (struct drm_device *dev,
- struct drm_file *file_priv,
- unsigned int handle);
- size_t(*bo_size) (struct drm_device *dev, void *bo);
size_t(*bo_offset) (struct drm_device *dev, void *bo);
- int (*bo_pin_for_scanout) (struct drm_device *dev, void *bo);
- int (*bo_unpin_for_scanout) (struct drm_device *dev, void *bo);
/*
* Cursor
@@ -156,11 +150,8 @@
/* a mode_set for fbdev users on this crtc */
struct drm_mode_set mode_set;
- /* current bo we scanout from */
- void *scanout_bo;
-
- /* current bo we cursor from */
- void *cursor_bo;
+ /* GEM object that holds our cursor */
+ struct drm_gem_object *cursor_obj;
struct drm_display_mode saved_mode;
struct drm_display_mode saved_adjusted_mode;
diff --git a/drivers/staging/gma500/psb_intel_lvds.c b/drivers/staging/gma500/psb_intel_lvds.c
index d3d210a..b0a225b 100644
--- a/drivers/staging/gma500/psb_intel_lvds.c
+++ b/drivers/staging/gma500/psb_intel_lvds.c
@@ -32,13 +32,6 @@
#include "psb_powermgmt.h"
#include <linux/pm_runtime.h>
-/* MRST defines start */
-uint8_t blc_freq;
-uint8_t blc_minbrightness;
-uint8_t blc_i2caddr;
-uint8_t blc_brightnesscmd;
-int lvds_backlight; /* restore backlight to this value */
-
u32 CoreClock;
u32 PWMControlRegFreq;
@@ -83,13 +76,12 @@
struct drm_psb_private *dev_priv = dev->dev_private;
u32 retVal;
- if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND,
- OSPM_UHB_ONLY_IF_ON)) {
+ if (gma_power_begin(dev, false)) {
retVal = ((REG_READ(BLC_PWM_CTL) &
BACKLIGHT_MODULATION_FREQ_MASK) >>
BACKLIGHT_MODULATION_FREQ_SHIFT) * 2;
- ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
+ gma_power_end(dev);
} else
retVal = ((dev_priv->saveBLC_PWM_CTL &
BACKLIGHT_MODULATION_FREQ_MASK) >>
@@ -98,8 +90,11 @@
return retVal;
}
-/**
+/*
* Set LVDS backlight level by I2C command
+ *
+ * FIXME: at some point we need to both track this for PM and also
+ * disable runtime pm on MRST if the brightness is nil (ie blanked)
*/
static int psb_lvds_i2c_set_brightness(struct drm_device *dev,
unsigned int level)
@@ -132,7 +127,7 @@
if (i2c_transfer(&lvds_i2c_bus->adapter, msgs, 1) == 1) {
DRM_DEBUG("I2C set brightness.(command, value) (%d, %d)\n",
- blc_brightnesscmd,
+ dev_priv->lvds_bl->brightnesscmd,
blc_i2c_brightness);
return 0;
}
@@ -200,14 +195,13 @@
struct drm_psb_private *dev_priv = dev->dev_private;
u32 blc_pwm_ctl;
- if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND,
- OSPM_UHB_ONLY_IF_ON)) {
+ if (gma_power_begin(dev, false)) {
blc_pwm_ctl =
REG_READ(BLC_PWM_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK;
REG_WRITE(BLC_PWM_CTL,
(blc_pwm_ctl |
(level << BACKLIGHT_DUTY_CYCLE_SHIFT)));
- ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
+ gma_power_end(dev);
} else {
blc_pwm_ctl = dev_priv->saveBLC_PWM_CTL &
~BACKLIGHT_DUTY_CYCLE_MASK;
@@ -224,8 +218,7 @@
{
u32 pp_status;
- if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND,
- OSPM_UHB_FORCE_POWER_ON))
+ if (!gma_power_begin(dev, true))
return;
if (on) {
@@ -248,7 +241,7 @@
} while (pp_status & PP_ON);
}
- ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
+ gma_power_end(dev);
}
static void psb_intel_lvds_encoder_dpms(struct drm_encoder *encoder, int mode)
@@ -400,11 +393,15 @@
if (psb_intel_output->type == INTEL_OUTPUT_MIPI2)
panel_fixed_mode = mode_dev->panel_fixed_mode2;
- /* PSB doesn't appear to be GEN4 */
- if (psb_intel_crtc->pipe == 0) {
+ /* PSB requires the LVDS is on pipe B, MRST has only one pipe anyway */
+ if (!IS_MRST(dev) && psb_intel_crtc->pipe == 0) {
printk(KERN_ERR "Can't support LVDS on pipe A\n");
return false;
}
+ if (IS_MRST(dev) && psb_intel_crtc->pipe != 0) {
+ printk(KERN_ERR "Must use PIPE A\n");
+ return false;
+ }
/* Should never happen!! */
list_for_each_entry(tmp_encoder, &dev->mode_config.encoder_list,
head) {
@@ -445,7 +442,7 @@
return true;
}
-static void psb_intel_lvds_prepare(struct drm_encoder *encoder)
+void psb_intel_lvds_prepare(struct drm_encoder *encoder)
{
struct drm_device *dev = encoder->dev;
struct psb_intel_output *output = enc_to_psb_intel_output(encoder);
@@ -453,8 +450,7 @@
PSB_DEBUG_ENTRY("\n");
- if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND,
- OSPM_UHB_FORCE_POWER_ON))
+ if (!gma_power_begin(dev, true))
return;
mode_dev->saveBLC_PWM_CTL = REG_READ(BLC_PWM_CTL);
@@ -463,10 +459,10 @@
psb_intel_lvds_set_power(dev, output, false);
- ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
+ gma_power_end(dev);
}
-static void psb_intel_lvds_commit(struct drm_encoder *encoder)
+void psb_intel_lvds_commit(struct drm_encoder *encoder)
{
struct drm_device *dev = encoder->dev;
struct psb_intel_output *output = enc_to_psb_intel_output(encoder);
@@ -669,14 +665,14 @@
.commit = psb_intel_lvds_commit,
};
-static const struct drm_connector_helper_funcs
+const struct drm_connector_helper_funcs
psb_intel_lvds_connector_helper_funcs = {
.get_modes = psb_intel_lvds_get_modes,
.mode_valid = psb_intel_lvds_mode_valid,
.best_encoder = psb_intel_best_encoder,
};
-static const struct drm_connector_funcs psb_intel_lvds_connector_funcs = {
+const struct drm_connector_funcs psb_intel_lvds_connector_funcs = {
.dpms = drm_helper_connector_dpms,
.save = psb_intel_lvds_save,
.restore = psb_intel_lvds_restore,
diff --git a/drivers/staging/gma500/psb_intel_sdvo.c b/drivers/staging/gma500/psb_intel_sdvo.c
index 1d2bb02..df1c006 100644
--- a/drivers/staging/gma500/psb_intel_sdvo.c
+++ b/drivers/staging/gma500/psb_intel_sdvo.c
@@ -204,7 +204,7 @@
struct psb_intel_sdvo_priv *sdvo_priv = psb_intel_output->dev_priv;
int i;
- if (1) {
+ if (0) {
DRM_DEBUG("%s: W: %02X ", SDVO_NAME(sdvo_priv), cmd);
for (i = 0; i < args_len; i++)
printk(KERN_INFO"%02X ", ((u8 *) args)[i]);
@@ -266,7 +266,7 @@
SDVO_I2C_CMD_STATUS,
&status);
- if (1) {
+ if (0) {
DRM_DEBUG("%s: R: ", SDVO_NAME(sdvo_priv));
for (i = 0; i < response_len; i++)
printk(KERN_INFO"%02X ", ((u8 *) response)[i]);
diff --git a/drivers/staging/gma500/psb_irq.c b/drivers/staging/gma500/psb_irq.c
index 4597c88..9ea37e5 100644
--- a/drivers/staging/gma500/psb_irq.c
+++ b/drivers/staging/gma500/psb_irq.c
@@ -88,13 +88,12 @@
u32 reg = psb_pipestat(pipe);
dev_priv->pipestat[pipe] |= mask;
/* Enable the interrupt, clear any pending status */
- if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND,
- OSPM_UHB_ONLY_IF_ON)) {
+ if (gma_power_begin(dev_priv->dev, false)) {
u32 writeVal = PSB_RVDC32(reg);
writeVal |= (mask | (mask >> 16));
PSB_WVDC32(writeVal, reg);
(void) PSB_RVDC32(reg);
- ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
+ gma_power_end(dev_priv->dev);
}
}
}
@@ -105,39 +104,36 @@
if ((dev_priv->pipestat[pipe] & mask) != 0) {
u32 reg = psb_pipestat(pipe);
dev_priv->pipestat[pipe] &= ~mask;
- if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND,
- OSPM_UHB_ONLY_IF_ON)) {
+ if (gma_power_begin(dev_priv->dev, false)) {
u32 writeVal = PSB_RVDC32(reg);
writeVal &= ~mask;
PSB_WVDC32(writeVal, reg);
(void) PSB_RVDC32(reg);
- ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
+ gma_power_end(dev_priv->dev);
}
}
}
void mid_enable_pipe_event(struct drm_psb_private *dev_priv, int pipe)
{
- if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND,
- OSPM_UHB_ONLY_IF_ON)) {
+ if (gma_power_begin(dev_priv->dev, false)) {
u32 pipe_event = mid_pipe_event(pipe);
dev_priv->vdc_irq_mask |= pipe_event;
PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
- ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
+ gma_power_end(dev_priv->dev);
}
}
void mid_disable_pipe_event(struct drm_psb_private *dev_priv, int pipe)
{
if (dev_priv->pipestat[pipe] == 0) {
- if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND,
- OSPM_UHB_ONLY_IF_ON)) {
+ if (gma_power_begin(dev_priv->dev, false)) {
u32 pipe_event = mid_pipe_event(pipe);
dev_priv->vdc_irq_mask &= ~pipe_event;
PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
- ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
+ gma_power_end(dev_priv->dev);
}
}
}
@@ -242,7 +238,7 @@
vdc_stat &= dev_priv->vdc_irq_mask;
spin_unlock(&dev_priv->irqmask_lock);
- if (dsp_int && ospm_power_is_hw_on(OSPM_DISPLAY_ISLAND)) {
+ if (dsp_int && gma_power_is_on(dev)) {
psb_vdc_interrupt(dev, vdc_stat);
handled = 1;
}
@@ -271,54 +267,28 @@
void psb_irq_preinstall(struct drm_device *dev)
{
- psb_irq_preinstall_islands(dev, OSPM_ALL_ISLANDS);
-}
-
-/**
- * FIXME: should I remove display irq enable here??
- */
-void psb_irq_preinstall_islands(struct drm_device *dev, int hw_islands)
-{
struct drm_psb_private *dev_priv =
(struct drm_psb_private *) dev->dev_private;
unsigned long irqflags;
- PSB_DEBUG_ENTRY("\n");
-
spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
- if (hw_islands & OSPM_DISPLAY_ISLAND) {
- if (ospm_power_is_hw_on(OSPM_DISPLAY_ISLAND)) {
- PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
- if (dev->vblank_enabled[0])
- dev_priv->vdc_irq_mask |=
- _PSB_PIPEA_EVENT_FLAG;
- if (dev->vblank_enabled[1])
- dev_priv->vdc_irq_mask |=
- _MDFLD_PIPEB_EVENT_FLAG;
- if (dev->vblank_enabled[2])
- dev_priv->vdc_irq_mask |=
- _MDFLD_PIPEC_EVENT_FLAG;
- }
- }
-/* NO I DONT WANT ANY IRQS GRRR FIXMEAC */
- if (hw_islands & OSPM_GRAPHICS_ISLAND)
- dev_priv->vdc_irq_mask |= _PSB_IRQ_SGX_FLAG;
-/* */
+ if (gma_power_is_on(dev))
+ PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
+ if (dev->vblank_enabled[0])
+ dev_priv->vdc_irq_mask |= _PSB_PIPEA_EVENT_FLAG;
+ if (dev->vblank_enabled[1])
+ dev_priv->vdc_irq_mask |= _MDFLD_PIPEB_EVENT_FLAG;
+ if (dev->vblank_enabled[2])
+ dev_priv->vdc_irq_mask |= _MDFLD_PIPEC_EVENT_FLAG;
+
/*This register is safe even if display island is off*/
PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
-
spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
}
int psb_irq_postinstall(struct drm_device *dev)
{
- return psb_irq_postinstall_islands(dev, OSPM_ALL_ISLANDS);
-}
-
-int psb_irq_postinstall_islands(struct drm_device *dev, int hw_islands)
-{
-
struct drm_psb_private *dev_priv =
(struct drm_psb_private *) dev->dev_private;
unsigned long irqflags;
@@ -327,48 +297,31 @@
spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
- /*This register is safe even if display island is off*/
+ /* This register is safe even if display island is off */
PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
+ PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
- if (hw_islands & OSPM_DISPLAY_ISLAND) {
- if (true/*powermgmt_is_hw_on(dev->pdev, PSB_DISPLAY_ISLAND)*/) {
- PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
+ if (dev->vblank_enabled[0])
+ psb_enable_pipestat(dev_priv, 0, PIPE_VBLANK_INTERRUPT_ENABLE);
+ else
+ psb_disable_pipestat(dev_priv, 0, PIPE_VBLANK_INTERRUPT_ENABLE);
- if (dev->vblank_enabled[0])
- psb_enable_pipestat(dev_priv, 0,
- PIPE_VBLANK_INTERRUPT_ENABLE);
- else
- psb_disable_pipestat(dev_priv, 0,
- PIPE_VBLANK_INTERRUPT_ENABLE);
+ if (dev->vblank_enabled[1])
+ psb_enable_pipestat(dev_priv, 1, PIPE_VBLANK_INTERRUPT_ENABLE);
+ else
+ psb_disable_pipestat(dev_priv, 1, PIPE_VBLANK_INTERRUPT_ENABLE);
- if (dev->vblank_enabled[1])
- psb_enable_pipestat(dev_priv, 1,
- PIPE_VBLANK_INTERRUPT_ENABLE);
- else
- psb_disable_pipestat(dev_priv, 1,
- PIPE_VBLANK_INTERRUPT_ENABLE);
-
- if (dev->vblank_enabled[2])
- psb_enable_pipestat(dev_priv, 2,
- PIPE_VBLANK_INTERRUPT_ENABLE);
- else
- psb_disable_pipestat(dev_priv, 2,
- PIPE_VBLANK_INTERRUPT_ENABLE);
- }
- }
+ if (dev->vblank_enabled[2])
+ psb_enable_pipestat(dev_priv, 2, PIPE_VBLANK_INTERRUPT_ENABLE);
+ else
+ psb_disable_pipestat(dev_priv, 2, PIPE_VBLANK_INTERRUPT_ENABLE);
spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
-
return 0;
}
void psb_irq_uninstall(struct drm_device *dev)
{
- psb_irq_uninstall_islands(dev, OSPM_ALL_ISLANDS);
-}
-
-void psb_irq_uninstall_islands(struct drm_device *dev, int hw_islands)
-{
struct drm_psb_private *dev_priv =
(struct drm_psb_private *) dev->dev_private;
unsigned long irqflags;
@@ -377,39 +330,29 @@
spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
- if (hw_islands & OSPM_DISPLAY_ISLAND) {
- if (true/*powermgmt_is_hw_on(dev->pdev, PSB_DISPLAY_ISLAND)*/) {
- PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
+ PSB_WVDC32(0xFFFFFFFF, PSB_HWSTAM);
- if (dev->vblank_enabled[0])
- psb_disable_pipestat(dev_priv, 0,
- PIPE_VBLANK_INTERRUPT_ENABLE);
+ if (dev->vblank_enabled[0])
+ psb_disable_pipestat(dev_priv, 0, PIPE_VBLANK_INTERRUPT_ENABLE);
- if (dev->vblank_enabled[1])
- psb_disable_pipestat(dev_priv, 1,
- PIPE_VBLANK_INTERRUPT_ENABLE);
+ if (dev->vblank_enabled[1])
+ psb_disable_pipestat(dev_priv, 1, PIPE_VBLANK_INTERRUPT_ENABLE);
- if (dev->vblank_enabled[2])
- psb_disable_pipestat(dev_priv, 2,
- PIPE_VBLANK_INTERRUPT_ENABLE);
- }
- dev_priv->vdc_irq_mask &= _PSB_IRQ_SGX_FLAG |
- _PSB_IRQ_MSVDX_FLAG |
- _LNC_IRQ_TOPAZ_FLAG;
- }
- /*TODO: remove following code*/
- if (hw_islands & OSPM_GRAPHICS_ISLAND)
- dev_priv->vdc_irq_mask &= ~_PSB_IRQ_SGX_FLAG;
+ if (dev->vblank_enabled[2])
+ psb_disable_pipestat(dev_priv, 2, PIPE_VBLANK_INTERRUPT_ENABLE);
- /*These two registers are safe even if display island is off*/
+ dev_priv->vdc_irq_mask &= _PSB_IRQ_SGX_FLAG |
+ _PSB_IRQ_MSVDX_FLAG |
+ _LNC_IRQ_TOPAZ_FLAG;
+
+ /* These two registers are safe even if display island is off */
PSB_WVDC32(~dev_priv->vdc_irq_mask, PSB_INT_MASK_R);
PSB_WVDC32(dev_priv->vdc_irq_mask, PSB_INT_ENABLE_R);
wmb();
- /*This register is safe even if display island is off*/
+ /* This register is safe even if display island is off */
PSB_WVDC32(PSB_RVDC32(PSB_INT_IDENTITY_R), PSB_INT_IDENTITY_R);
-
spin_unlock_irqrestore(&dev_priv->irqmask_lock, irqflags);
}
@@ -420,8 +363,7 @@
u32 hist_reg;
u32 pwm_reg;
- if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND,
- OSPM_UHB_ONLY_IF_ON)) {
+ if (gma_power_begin(dev, false)) {
PSB_WVDC32(1 << 31, HISTOGRAM_LOGIC_CONTROL);
hist_reg = PSB_RVDC32(HISTOGRAM_LOGIC_CONTROL);
PSB_WVDC32(1 << 31, HISTOGRAM_INT_CONTROL);
@@ -443,7 +385,7 @@
PSB_WVDC32(pwm_reg | 0x80010100 | PWM_PHASEIN_ENABLE,
PWM_CONTROL_LOGIC);
- ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
+ gma_power_end(dev);
}
}
@@ -472,8 +414,7 @@
u32 hist_reg;
u32 pwm_reg;
- if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND,
- OSPM_UHB_ONLY_IF_ON)) {
+ if (gma_power_begin(dev, false)) {
PSB_WVDC32(0x00000000, HISTOGRAM_INT_CONTROL);
hist_reg = PSB_RVDC32(HISTOGRAM_INT_CONTROL);
@@ -484,7 +425,7 @@
PWM_CONTROL_LOGIC);
pwm_reg = PSB_RVDC32(PWM_CONTROL_LOGIC);
- ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
+ gma_power_end(dev);
}
}
@@ -526,18 +467,16 @@
*/
int psb_enable_vblank(struct drm_device *dev, int pipe)
{
- struct drm_psb_private *dev_priv =
- (struct drm_psb_private *) dev->dev_private;
+ struct drm_psb_private *dev_priv = dev->dev_private;
unsigned long irqflags;
uint32_t reg_val = 0;
uint32_t pipeconf_reg = mid_pipeconf(pipe);
PSB_DEBUG_ENTRY("\n");
- if (ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND,
- OSPM_UHB_ONLY_IF_ON)) {
+ if (gma_power_begin(dev, false)) {
reg_val = REG_READ(pipeconf_reg);
- ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
+ gma_power_end(dev);
}
if (!(reg_val & PIPEACONF_ENABLE))
@@ -545,7 +484,6 @@
spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
- drm_psb_disable_vsync = 0;
mid_enable_pipe_event(dev_priv, pipe);
psb_enable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE);
@@ -559,15 +497,13 @@
*/
void psb_disable_vblank(struct drm_device *dev, int pipe)
{
- struct drm_psb_private *dev_priv =
- (struct drm_psb_private *) dev->dev_private;
+ struct drm_psb_private *dev_priv = dev->dev_private;
unsigned long irqflags;
PSB_DEBUG_ENTRY("\n");
spin_lock_irqsave(&dev_priv->irqmask_lock, irqflags);
- drm_psb_disable_vsync = 1;
mid_disable_pipe_event(dev_priv, pipe);
psb_disable_pipestat(dev_priv, pipe, PIPE_VBLANK_INTERRUPT_ENABLE);
@@ -603,7 +539,7 @@
return 0;
}
- if (!ospm_power_using_hw_begin(OSPM_DISPLAY_ISLAND, false))
+ if (!gma_power_begin(dev, false))
return 0;
reg_val = REG_READ(pipeconf_reg);
@@ -632,7 +568,7 @@
psb_get_vblank_counter_exit:
- ospm_power_using_hw_end(OSPM_DISPLAY_ISLAND);
+ gma_power_end(dev);
return count;
}
diff --git a/drivers/staging/gma500/psb_reset.c b/drivers/staging/gma500/psb_lid.c
similarity index 100%
rename from drivers/staging/gma500/psb_reset.c
rename to drivers/staging/gma500/psb_lid.c
diff --git a/drivers/staging/gma500/psb_mmu.c b/drivers/staging/gma500/psb_mmu.c
index edd0d49..c904d73 100644
--- a/drivers/staging/gma500/psb_mmu.c
+++ b/drivers/staging/gma500/psb_mmu.c
@@ -444,67 +444,6 @@
pt->v[psb_mmu_pt_index(addr)] = pt->pd->invalid_pte;
}
-#if 0
-static uint32_t psb_mmu_check_pte_locked(struct psb_mmu_pd *pd,
- uint32_t mmu_offset)
-{
- uint32_t *v;
- uint32_t pfn;
-
- v = kmap_atomic(pd->p, KM_USER0);
- if (!v) {
- printk(KERN_INFO "Could not kmap pde page.\n");
- return 0;
- }
- pfn = v[psb_mmu_pd_index(mmu_offset)];
- /* printk(KERN_INFO "pde is 0x%08x\n",pfn); */
- kunmap_atomic(v, KM_USER0);
- if (((pfn & 0x0F) != PSB_PTE_VALID)) {
- printk(KERN_INFO "Strange pde at 0x%08x: 0x%08x.\n",
- mmu_offset, pfn);
- }
- v = ioremap(pfn & 0xFFFFF000, 4096);
- if (!v) {
- printk(KERN_INFO "Could not kmap pte page.\n");
- return 0;
- }
- pfn = v[psb_mmu_pt_index(mmu_offset)];
- /* printk(KERN_INFO "pte is 0x%08x\n",pfn); */
- iounmap(v);
- if (((pfn & 0x0F) != PSB_PTE_VALID)) {
- printk(KERN_INFO "Strange pte at 0x%08x: 0x%08x.\n",
- mmu_offset, pfn);
- }
- return pfn >> PAGE_SHIFT;
-}
-
-static void psb_mmu_check_mirrored_gtt(struct psb_mmu_pd *pd,
- uint32_t mmu_offset,
- uint32_t gtt_pages)
-{
- uint32_t start;
- uint32_t next;
-
- printk(KERN_INFO "Checking mirrored gtt 0x%08x %d\n",
- mmu_offset, gtt_pages);
- down_read(&pd->driver->sem);
- start = psb_mmu_check_pte_locked(pd, mmu_offset);
- mmu_offset += PAGE_SIZE;
- gtt_pages -= 1;
- while (gtt_pages--) {
- next = psb_mmu_check_pte_locked(pd, mmu_offset);
- if (next != start + 1) {
- printk(KERN_INFO
- "Ptes out of order: 0x%08x, 0x%08x.\n",
- start, next);
- }
- start = next;
- mmu_offset += PAGE_SIZE;
- }
- up_read(&pd->driver->sem);
-}
-
-#endif
void psb_mmu_mirror_gtt(struct psb_mmu_pd *pd,
uint32_t mmu_offset, uint32_t gtt_start,
diff --git a/drivers/staging/gma500/psb_powermgmt.c b/drivers/staging/gma500/psb_powermgmt.c
index 7deb1ba..1495415 100644
--- a/drivers/staging/gma500/psb_powermgmt.c
+++ b/drivers/staging/gma500/psb_powermgmt.c
@@ -24,83 +24,73 @@
* Authors:
* Benjamin Defnet <benjamin.r.defnet@intel.com>
* Rajesh Poornachandran <rajesh.poornachandran@intel.com>
- *
+ * Massively reworked
+ * Alan Cox <alan@linux.intel.com>
*/
#include "psb_powermgmt.h"
#include "psb_drv.h"
+#include "psb_reg.h"
#include "psb_intel_reg.h"
#include <linux/mutex.h>
#include <linux/pm_runtime.h>
-#undef OSPM_GFX_DPK
-
-extern u32 gui32SGXDeviceID;
-extern u32 gui32MRSTDisplayDeviceID;
-extern u32 gui32MRSTMSVDXDeviceID;
-extern u32 gui32MRSTTOPAZDeviceID;
-
-struct drm_device *gpDrmDevice = NULL;
static struct mutex power_mutex;
-static bool gbSuspendInProgress = false;
-static bool gbResumeInProgress = false;
-static int g_hw_power_status_mask;
-static atomic_t g_display_access_count;
-static atomic_t g_graphics_access_count;
-static atomic_t g_videoenc_access_count;
-static atomic_t g_videodec_access_count;
-int allow_runtime_pm = 0;
-void ospm_power_island_up(int hw_islands);
-void ospm_power_island_down(int hw_islands);
-static bool gbSuspended = false;
-bool gbgfxsuspended = false;
-
-/*
- * ospm_power_init
+/**
+ * gma_power_init - initialise power manager
+ * @dev: our device
*
- * Description: Initialize this ospm power management module
+ * Set up for power management tracking of our hardware.
*/
-void ospm_power_init(struct drm_device *dev)
+void gma_power_init(struct drm_device *dev)
{
- struct drm_psb_private *dev_priv = (struct drm_psb_private *)dev->dev_private;
-
- gpDrmDevice = dev;
+ struct drm_psb_private *dev_priv = dev->dev_private;
dev_priv->apm_base = dev_priv->apm_reg & 0xffff;
dev_priv->ospm_base &= 0xffff;
+ dev_priv->display_power = true; /* We start active */
+ dev_priv->display_count = 0; /* Currently no users */
+ dev_priv->suspended = false; /* And not suspended */
mutex_init(&power_mutex);
- g_hw_power_status_mask = OSPM_ALL_ISLANDS;
- atomic_set(&g_display_access_count, 0);
- atomic_set(&g_graphics_access_count, 0);
- atomic_set(&g_videoenc_access_count, 0);
- atomic_set(&g_videodec_access_count, 0);
+
+ if (!IS_MRST(dev)) {
+ /* FIXME: wants further review */
+ u32 gating = PSB_RSGX32(PSB_CR_CLKGATECTL);
+ /* Disable 2D clock gating */
+ gating &= ~3;
+ gating |= 1;
+ PSB_WSGX32(gating, PSB_CR_CLKGATECTL);
+ PSB_RSGX32(PSB_CR_CLKGATECTL);
+ }
}
-/*
- * ospm_power_uninit
+/**
+ * gma_power_uninit - end power manager
+ * @dev: device to end for
*
- * Description: Uninitialize this ospm power management module
+ * Undo the effects of gma_power_init
*/
-void ospm_power_uninit(void)
+void gma_power_uninit(struct drm_device *dev)
{
mutex_destroy(&power_mutex);
- pm_runtime_disable(&gpDrmDevice->pdev->dev);
- pm_runtime_set_suspended(&gpDrmDevice->pdev->dev);
+ pm_runtime_disable(&dev->pdev->dev);
+ pm_runtime_set_suspended(&dev->pdev->dev);
}
-/*
- * save_display_registers
+/**
+ * save_display_registers - save registers lost on suspend
+ * @dev: our DRM device
*
- * Description: We are going to suspend so save current display
- * register state.
+ * Save the state we need in order to be able to restore the interface
+ * upon resume from suspend
*/
static int save_display_registers(struct drm_device *dev)
{
struct drm_psb_private *dev_priv = dev->dev_private;
- struct drm_crtc * crtc;
- struct drm_connector * connector;
+ struct drm_crtc *crtc;
+ struct drm_connector *connector;
/* Display arbitration control + watermarks */
dev_priv->saveDSPARB = PSB_RVDC32(DSPARB);
@@ -112,37 +102,31 @@
dev_priv->saveDSPFW6 = PSB_RVDC32(DSPFW6);
dev_priv->saveCHICKENBIT = PSB_RVDC32(DSPCHICKENBIT);
- /*save crtc and output state*/
+ /* Save crtc and output state */
mutex_lock(&dev->mode_config.mutex);
list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
- if(drm_helper_crtc_in_use(crtc)) {
+ if (drm_helper_crtc_in_use(crtc))
crtc->funcs->save(crtc);
- }
}
- list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
+ list_for_each_entry(connector, &dev->mode_config.connector_list, head)
connector->funcs->save(connector);
- }
+
mutex_unlock(&dev->mode_config.mutex);
-
- /* Interrupt state */
- /*
- * Handled in psb_irq.c
- */
-
return 0;
}
-/*
- * restore_display_registers
+/**
+ * restore_display_registers - restore lost register state
+ * @dev: our DRM device
*
- * Description: We are going to resume so restore display register state.
+ * Restore register state that was lost during suspend and resume.
*/
static int restore_display_registers(struct drm_device *dev)
{
struct drm_psb_private *dev_priv = dev->dev_private;
- struct drm_crtc * crtc;
- struct drm_connector * connector;
+ struct drm_crtc *crtc;
+ struct drm_connector *connector;
/* Display arbitration + watermarks */
PSB_WVDC32(dev_priv->saveDSPARB, DSPARB);
@@ -158,39 +142,57 @@
PSB_WVDC32(0x80000000, VGACNTRL);
mutex_lock(&dev->mode_config.mutex);
- list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
- if(drm_helper_crtc_in_use(crtc))
+ list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
+ if (drm_helper_crtc_in_use(crtc))
crtc->funcs->restore(crtc);
- }
- list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
+
+ list_for_each_entry(connector, &dev->mode_config.connector_list, head)
connector->funcs->restore(connector);
- }
+
mutex_unlock(&dev->mode_config.mutex);
-
- /*Interrupt state*/
- /*
- * Handled in psb_irq.c
- */
-
return 0;
}
-/*
- * powermgmt_suspend_display
+
+/**
+ * power_down - power down the display island
+ * @dev: our DRM device
*
- * Description: Suspend the display hardware saving state and disabling
- * as necessary.
+ * Power down the display interface of our device
*/
-void ospm_suspend_display(struct drm_device *dev)
+static void power_down(struct drm_device *dev)
{
struct drm_psb_private *dev_priv = dev->dev_private;
- int pp_stat, ret=0;
+ u32 pwr_mask ;
+ u32 pwr_sts;
- printk(KERN_ALERT "%s \n", __func__);
+ if (IS_MRST(dev)) {
+ pwr_mask = PSB_PWRGT_DISPLAY_MASK;
+ outl(pwr_mask, dev_priv->ospm_base + PSB_PM_SSC);
-#ifdef OSPM_GFX_DPK
- printk(KERN_ALERT "%s \n", __func__);
-#endif
- if (!(g_hw_power_status_mask & OSPM_DISPLAY_ISLAND))
+ while (true) {
+ pwr_sts = inl(dev_priv->ospm_base + PSB_PM_SSS);
+ if ((pwr_sts & pwr_mask) == pwr_mask)
+ break;
+ else
+ udelay(10);
+ }
+ dev_priv->display_power = false;
+ }
+}
+
+
+/**
+ * gma_suspend_display - suspend the display logic
+ * @dev: our DRM device
+ *
+ * Suspend the display logic of the graphics interface
+ */
+static void gma_suspend_display(struct drm_device *dev)
+{
+ struct drm_psb_private *dev_priv = dev->dev_private;
+ int pp_stat;
+
+ if (dev_priv->suspended)
return;
save_display_registers(dev);
@@ -225,193 +227,22 @@
!= DPI_FIFO_EMPTY);
PSB_WVDC32(0, DEVICE_READY_REG);
/* turn off panel power */
- ret = 0;
}
- ospm_power_island_down(OSPM_DISPLAY_ISLAND);
+ power_down(dev);
}
/*
- * ospm_resume_display
- *
- * Description: Resume the display hardware restoring state and enabling
- * as necessary.
- */
-void ospm_resume_display(struct pci_dev *pdev)
-{
- struct drm_device *dev = pci_get_drvdata(pdev);
- struct drm_psb_private *dev_priv = dev->dev_private;
- struct psb_gtt *pg = dev_priv->pg;
-
- printk(KERN_ALERT "%s \n", __func__);
-
-#ifdef OSPM_GFX_DPK
- printk(KERN_ALERT "%s \n", __func__);
-#endif
- if (g_hw_power_status_mask & OSPM_DISPLAY_ISLAND)
- return;
-
- /* turn on the display power island */
- ospm_power_island_up(OSPM_DISPLAY_ISLAND);
-
- PSB_WVDC32(pg->pge_ctl | _PSB_PGETBL_ENABLED, PSB_PGETBL_CTL);
- pci_write_config_word(pdev, PSB_GMCH_CTRL,
- pg->gmch_ctrl | _PSB_GMCH_ENABLED);
-
- /* Don't reinitialize the GTT as it is unnecessary. The gtt is
- * stored in memory so it will automatically be restored. All
- * we need to do is restore the PGETBL_CTL which we already do
- * above.
- */
- /*psb_gtt_init(dev_priv->pg, 1);*/
-
- restore_display_registers(dev);
-}
-
-#if 1
-/*
- * ospm_suspend_pci
- *
- * Description: Suspend the pci device saving state and disabling
- * as necessary.
- */
-static void ospm_suspend_pci(struct pci_dev *pdev)
-{
- struct drm_device *dev = pci_get_drvdata(pdev);
- struct drm_psb_private *dev_priv = dev->dev_private;
- int bsm, vbt;
-
- if (gbSuspended)
- return;
-
-#ifdef OSPM_GFX_DPK
- printk(KERN_ALERT "ospm_suspend_pci\n");
-#endif
-
- pci_save_state(pdev);
- pci_read_config_dword(pdev, 0x5C, &bsm);
- dev_priv->saveBSM = bsm;
- pci_read_config_dword(pdev, 0xFC, &vbt);
- dev_priv->saveVBT = vbt;
- pci_read_config_dword(pdev, PSB_PCIx_MSI_ADDR_LOC, &dev_priv->msi_addr);
- pci_read_config_dword(pdev, PSB_PCIx_MSI_DATA_LOC, &dev_priv->msi_data);
-
- pci_disable_device(pdev);
- pci_set_power_state(pdev, PCI_D3hot);
-
- gbSuspended = true;
- gbgfxsuspended = true;
-}
-
-/*
- * ospm_resume_pci
- *
- * Description: Resume the pci device restoring state and enabling
- * as necessary.
- */
-static bool ospm_resume_pci(struct pci_dev *pdev)
-{
- struct drm_device *dev = pci_get_drvdata(pdev);
- struct drm_psb_private *dev_priv = dev->dev_private;
- int ret = 0;
-
- if (!gbSuspended)
- return true;
-
-#ifdef OSPM_GFX_DPK
- printk(KERN_ALERT "ospm_resume_pci\n");
-#endif
-
- pci_set_power_state(pdev, PCI_D0);
- pci_restore_state(pdev);
- pci_write_config_dword(pdev, 0x5c, dev_priv->saveBSM);
- pci_write_config_dword(pdev, 0xFC, dev_priv->saveVBT);
- /* retoring MSI address and data in PCIx space */
- pci_write_config_dword(pdev, PSB_PCIx_MSI_ADDR_LOC, dev_priv->msi_addr);
- pci_write_config_dword(pdev, PSB_PCIx_MSI_DATA_LOC, dev_priv->msi_data);
- ret = pci_enable_device(pdev);
-
- if (ret != 0)
- printk(KERN_ALERT "ospm_resume_pci: pci_enable_device failed: %d\n", ret);
- else
- gbSuspended = false;
-
- return !gbSuspended;
-}
-#endif
-/*
- * ospm_power_suspend
- *
- * Description: OSPM is telling our driver to suspend so save state
- * and power down all hardware.
- */
-int ospm_power_suspend(struct pci_dev *pdev, pm_message_t state)
-{
- int ret = 0;
- int graphics_access_count;
- int videoenc_access_count;
- int videodec_access_count;
- int display_access_count;
- bool suspend_pci = true;
-
- if(gbSuspendInProgress || gbResumeInProgress)
- {
-#ifdef OSPM_GFX_DPK
- printk(KERN_ALERT "OSPM_GFX_DPK: %s system BUSY \n", __func__);
-#endif
- return -EBUSY;
- }
-
- mutex_lock(&power_mutex);
-
- if (!gbSuspended) {
- graphics_access_count = atomic_read(&g_graphics_access_count);
- videoenc_access_count = atomic_read(&g_videoenc_access_count);
- videodec_access_count = atomic_read(&g_videodec_access_count);
- display_access_count = atomic_read(&g_display_access_count);
-
- if (graphics_access_count ||
- videoenc_access_count ||
- videodec_access_count ||
- display_access_count)
- ret = -EBUSY;
-
- if (!ret) {
- gbSuspendInProgress = true;
-
- psb_irq_uninstall_islands(gpDrmDevice, OSPM_DISPLAY_ISLAND);
- ospm_suspend_display(gpDrmDevice);
- if (suspend_pci == true) {
- ospm_suspend_pci(pdev);
- }
- gbSuspendInProgress = false;
- } else {
- printk(KERN_ALERT "ospm_power_suspend: device busy: graphics %d videoenc %d videodec %d display %d\n", graphics_access_count, videoenc_access_count, videodec_access_count, display_access_count);
- }
- }
-
-
- mutex_unlock(&power_mutex);
- return ret;
-}
-
-/*
- * ospm_power_island_up
+ * power_up
*
* Description: Restore power to the specified island(s) (powergating)
*/
-void ospm_power_island_up(int hw_islands)
+static void power_up(struct drm_device *dev)
{
- u32 pwr_cnt = 0;
- u32 pwr_sts = 0;
- u32 pwr_mask = 0;
+ struct drm_psb_private *dev_priv = dev->dev_private;
+ u32 pwr_mask = PSB_PWRGT_DISPLAY_MASK;
+ u32 pwr_sts, pwr_cnt;
- struct drm_psb_private *dev_priv =
- (struct drm_psb_private *) gpDrmDevice->dev_private;
-
-
- if (hw_islands & OSPM_DISPLAY_ISLAND) {
- pwr_mask = PSB_PWRGT_DISPLAY_MASK;
-
+ if (IS_MRST(dev)) {
pwr_cnt = inl(dev_priv->ospm_base + PSB_PM_SSC);
pwr_cnt &= ~pwr_mask;
outl(pwr_cnt, (dev_priv->ospm_base + PSB_PM_SSC));
@@ -424,355 +255,221 @@
udelay(10);
}
}
-
- g_hw_power_status_mask |= hw_islands;
+ dev_priv->suspended = false;
+ dev_priv->display_power = true;
}
-/*
- * ospm_power_resume
+/**
+ * gma_resume_display - resume display side logic
+ *
+ * Resume the display hardware restoring state and enabling
+ * as necessary.
*/
-int ospm_power_resume(struct pci_dev *pdev)
+static void gma_resume_display(struct pci_dev *pdev)
{
- if(gbSuspendInProgress || gbResumeInProgress)
- {
-#ifdef OSPM_GFX_DPK
- printk(KERN_ALERT "OSPM_GFX_DPK: %s hw_island: Suspend || gbResumeInProgress!!!! \n", __func__);
-#endif
- return 0;
- }
+ struct drm_device *dev = pci_get_drvdata(pdev);
+ struct drm_psb_private *dev_priv = dev->dev_private;
- mutex_lock(&power_mutex);
+ if (dev_priv->suspended == false)
+ return;
-#ifdef OSPM_GFX_DPK
- printk(KERN_ALERT "OSPM_GFX_DPK: ospm_power_resume \n");
-#endif
+ /* turn on the display power island */
+ power_up(dev);
- gbResumeInProgress = true;
+ PSB_WVDC32(dev_priv->pge_ctl | _PSB_PGETBL_ENABLED, PSB_PGETBL_CTL);
+ pci_write_config_word(pdev, PSB_GMCH_CTRL,
+ dev_priv->gmch_ctrl | _PSB_GMCH_ENABLED);
- ospm_resume_pci(pdev);
+ /* Don't reinitialize the GTT as it is unnecessary. The gtt is
+ * stored in memory so it will automatically be restored. All
+ * we need to do is restore the PGETBL_CTL which we already do
+ * above.
+ */
+ /*psb_gtt_init(dev_priv->pg, 1);*/
- ospm_resume_display(gpDrmDevice->pdev);
- psb_irq_preinstall_islands(gpDrmDevice, OSPM_DISPLAY_ISLAND);
- psb_irq_postinstall_islands(gpDrmDevice, OSPM_DISPLAY_ISLAND);
+ restore_display_registers(dev);
+}
- gbResumeInProgress = false;
+/**
+ * gma_suspend_pci - suspend PCI side
+ * @pdev: PCI device
+ *
+ * Perform the suspend processing on our PCI device state
+ */
+static void gma_suspend_pci(struct pci_dev *pdev)
+{
+ struct drm_device *dev = pci_get_drvdata(pdev);
+ struct drm_psb_private *dev_priv = dev->dev_private;
+ int bsm, vbt;
- mutex_unlock(&power_mutex);
+ if (dev_priv->suspended)
+ return;
+ pci_save_state(pdev);
+ pci_read_config_dword(pdev, 0x5C, &bsm);
+ dev_priv->saveBSM = bsm;
+ pci_read_config_dword(pdev, 0xFC, &vbt);
+ dev_priv->saveVBT = vbt;
+ pci_read_config_dword(pdev, PSB_PCIx_MSI_ADDR_LOC, &dev_priv->msi_addr);
+ pci_read_config_dword(pdev, PSB_PCIx_MSI_DATA_LOC, &dev_priv->msi_data);
+
+ pci_disable_device(pdev);
+ pci_set_power_state(pdev, PCI_D3hot);
+
+ dev_priv->suspended = true;
+}
+
+/**
+ * gma_resume_pci - resume helper
+ * @dev: our PCI device
+ *
+ * Perform the resume processing on our PCI device state - rewrite
+ * register state and re-enable the PCI device
+ */
+static bool gma_resume_pci(struct pci_dev *pdev)
+{
+ struct drm_device *dev = pci_get_drvdata(pdev);
+ struct drm_psb_private *dev_priv = dev->dev_private;
+ int ret;
+
+ if (!dev_priv->suspended)
+ return true;
+
+ pci_set_power_state(pdev, PCI_D0);
+ pci_restore_state(pdev);
+ pci_write_config_dword(pdev, 0x5c, dev_priv->saveBSM);
+ pci_write_config_dword(pdev, 0xFC, dev_priv->saveVBT);
+ /* retoring MSI address and data in PCIx space */
+ pci_write_config_dword(pdev, PSB_PCIx_MSI_ADDR_LOC, dev_priv->msi_addr);
+ pci_write_config_dword(pdev, PSB_PCIx_MSI_DATA_LOC, dev_priv->msi_data);
+ ret = pci_enable_device(pdev);
+
+ if (ret != 0)
+ dev_err(&pdev->dev, "pci_enable failed: %d\n", ret);
+ else
+ dev_priv->suspended = false;
+ return !dev_priv->suspended;
+}
+
+/**
+ * gma_power_suspend - bus callback for suspend
+ * @pdev: our PCI device
+ * @state: suspend type
+ *
+ * Called back by the PCI layer during a suspend of the system. We
+ * perform the necessary shut down steps and save enough state that
+ * we can undo this when resume is called.
+ */
+int gma_power_suspend(struct pci_dev *pdev, pm_message_t state)
+{
+ struct drm_device *dev = pci_get_drvdata(pdev);
+ struct drm_psb_private *dev_priv = dev->dev_private;
+
+ mutex_lock(&power_mutex);
+ if (!dev_priv->suspended) {
+ if (dev_priv->display_count) {
+ mutex_unlock(&power_mutex);
+ return -EBUSY;
+ }
+ psb_irq_uninstall(dev);
+ gma_suspend_display(dev);
+ gma_suspend_pci(pdev);
+ }
+ mutex_unlock(&power_mutex);
return 0;
}
-/*
- * ospm_power_island_down
+/**
+ * gma_power_resume - resume power
+ * @pdev: PCI device
*
- * Description: Cut power to the specified island(s) (powergating)
+ * Resume the PCI side of the graphics and then the displays
*/
-void ospm_power_island_down(int islands)
+int gma_power_resume(struct pci_dev *pdev)
{
-#if 0
- u32 pwr_cnt = 0;
- u32 pwr_mask = 0;
- u32 pwr_sts = 0;
+ struct drm_device *dev = pci_get_drvdata(pdev);
- struct drm_psb_private *dev_priv =
- (struct drm_psb_private *) gpDrmDevice->dev_private;
-
- g_hw_power_status_mask &= ~islands;
-
- if (islands & OSPM_GRAPHICS_ISLAND) {
- pwr_cnt |= PSB_PWRGT_GFX_MASK;
- pwr_mask |= PSB_PWRGT_GFX_MASK;
- if (dev_priv->graphics_state == PSB_PWR_STATE_ON) {
- dev_priv->gfx_on_time += (jiffies - dev_priv->gfx_last_mode_change) * 1000 / HZ;
- dev_priv->gfx_last_mode_change = jiffies;
- dev_priv->graphics_state = PSB_PWR_STATE_OFF;
- dev_priv->gfx_off_cnt++;
- }
- }
- if (islands & OSPM_VIDEO_ENC_ISLAND) {
- pwr_cnt |= PSB_PWRGT_VID_ENC_MASK;
- pwr_mask |= PSB_PWRGT_VID_ENC_MASK;
- }
- if (islands & OSPM_VIDEO_DEC_ISLAND) {
- pwr_cnt |= PSB_PWRGT_VID_DEC_MASK;
- pwr_mask |= PSB_PWRGT_VID_DEC_MASK;
- }
- if (pwr_cnt) {
- pwr_cnt |= inl(dev_priv->apm_base);
- outl(pwr_cnt, dev_priv->apm_base + PSB_APM_CMD);
- while (true) {
- pwr_sts = inl(dev_priv->apm_base + PSB_APM_STS);
-
- if ((pwr_sts & pwr_mask) == pwr_mask)
- break;
- else
- udelay(10);
- }
- }
-
- if (islands & OSPM_DISPLAY_ISLAND) {
- pwr_mask = PSB_PWRGT_DISPLAY_MASK;
-
- outl(pwr_mask, (dev_priv->ospm_base + PSB_PM_SSC));
-
- while (true) {
- pwr_sts = inl(dev_priv->ospm_base + PSB_PM_SSS);
- if ((pwr_sts & pwr_mask) == pwr_mask)
- break;
- else
- udelay(10);
- }
- }
-#endif
-}
-
-
-/*
- * ospm_power_is_hw_on
- *
- * Description: do an instantaneous check for if the specified islands
- * are on. Only use this in cases where you know the g_state_change_mutex
- * is already held such as in irq install/uninstall. Otherwise, use
- * ospm_power_using_hw_begin().
- */
-bool ospm_power_is_hw_on(int hw_islands)
-{
- return ((g_hw_power_status_mask & hw_islands) == hw_islands) ? true:false;
-}
-
-/*
- * ospm_power_using_hw_begin
- *
- * Description: Notify PowerMgmt module that you will be accessing the
- * specified island's hw so don't power it off. If force_on is true,
- * this will power on the specified island if it is off.
- * Otherwise, this will return false and the caller is expected to not
- * access the hw.
- *
- * NOTE *** If this is called from and interrupt handler or other atomic
- * context, then it will return false if we are in the middle of a
- * power state transition and the caller will be expected to handle that
- * even if force_on is set to true.
- */
-bool ospm_power_using_hw_begin(int hw_island, UHBUsage usage)
-{
- return 1; /*FIXMEAC */
-#if 0
- bool ret = true;
- bool island_is_off = false;
- bool b_atomic = (in_interrupt() || in_atomic());
- bool locked = true;
- struct pci_dev *pdev = gpDrmDevice->pdev;
- u32 deviceID = 0;
- bool force_on = usage ? true: false;
- /*quick path, not 100% race safe, but should be enough comapre to current other code in this file */
- if (!force_on) {
- if (hw_island & (OSPM_ALL_ISLANDS & ~g_hw_power_status_mask))
- return false;
- else {
- locked = false;
-#ifdef CONFIG_PM_RUNTIME
- /* increment pm_runtime_refcount */
- pm_runtime_get(&pdev->dev);
-#endif
- goto increase_count;
- }
- }
-
-
- if (!b_atomic)
- mutex_lock(&power_mutex);
-
- island_is_off = hw_island & (OSPM_ALL_ISLANDS & ~g_hw_power_status_mask);
-
- if (b_atomic && (gbSuspendInProgress || gbResumeInProgress || gbSuspended) && force_on && island_is_off)
- ret = false;
-
- if (ret && island_is_off && !force_on)
- ret = false;
-
- if (ret && island_is_off && force_on) {
- gbResumeInProgress = true;
-
- ret = ospm_resume_pci(pdev);
-
- if (ret) {
- switch(hw_island)
- {
- case OSPM_DISPLAY_ISLAND:
- deviceID = gui32MRSTDisplayDeviceID;
- ospm_resume_display(pdev);
- psb_irq_preinstall_islands(gpDrmDevice, OSPM_DISPLAY_ISLAND);
- psb_irq_postinstall_islands(gpDrmDevice, OSPM_DISPLAY_ISLAND);
- break;
- case OSPM_GRAPHICS_ISLAND:
- deviceID = gui32SGXDeviceID;
- ospm_power_island_up(OSPM_GRAPHICS_ISLAND);
- psb_irq_preinstall_islands(gpDrmDevice, OSPM_GRAPHICS_ISLAND);
- psb_irq_postinstall_islands(gpDrmDevice, OSPM_GRAPHICS_ISLAND);
- break;
-#if 1
- case OSPM_VIDEO_DEC_ISLAND:
- if(!ospm_power_is_hw_on(OSPM_DISPLAY_ISLAND)) {
- //printk(KERN_ALERT "%s power on display for video decode use\n", __func__);
- deviceID = gui32MRSTDisplayDeviceID;
- ospm_resume_display(pdev);
- psb_irq_preinstall_islands(gpDrmDevice, OSPM_DISPLAY_ISLAND);
- psb_irq_postinstall_islands(gpDrmDevice, OSPM_DISPLAY_ISLAND);
- }
- else{
- //printk(KERN_ALERT "%s display is already on for video decode use\n", __func__);
- }
-
- if(!ospm_power_is_hw_on(OSPM_VIDEO_DEC_ISLAND)) {
- //printk(KERN_ALERT "%s power on video decode\n", __func__);
- deviceID = gui32MRSTMSVDXDeviceID;
- ospm_power_island_up(OSPM_VIDEO_DEC_ISLAND);
- psb_irq_preinstall_islands(gpDrmDevice, OSPM_VIDEO_DEC_ISLAND);
- psb_irq_postinstall_islands(gpDrmDevice, OSPM_VIDEO_DEC_ISLAND);
- }
- else{
- //printk(KERN_ALERT "%s video decode is already on\n", __func__);
- }
-
- break;
- case OSPM_VIDEO_ENC_ISLAND:
- if(!ospm_power_is_hw_on(OSPM_DISPLAY_ISLAND)) {
- //printk(KERN_ALERT "%s power on display for video encode\n", __func__);
- deviceID = gui32MRSTDisplayDeviceID;
- ospm_resume_display(pdev);
- psb_irq_preinstall_islands(gpDrmDevice, OSPM_DISPLAY_ISLAND);
- psb_irq_postinstall_islands(gpDrmDevice, OSPM_DISPLAY_ISLAND);
- }
- else{
- //printk(KERN_ALERT "%s display is already on for video encode use\n", __func__);
- }
-
- if(!ospm_power_is_hw_on(OSPM_VIDEO_ENC_ISLAND)) {
- //printk(KERN_ALERT "%s power on video encode\n", __func__);
- deviceID = gui32MRSTTOPAZDeviceID;
- ospm_power_island_up(OSPM_VIDEO_ENC_ISLAND);
- psb_irq_preinstall_islands(gpDrmDevice, OSPM_VIDEO_ENC_ISLAND);
- psb_irq_postinstall_islands(gpDrmDevice, OSPM_VIDEO_ENC_ISLAND);
- }
- else{
- //printk(KERN_ALERT "%s video decode is already on\n", __func__);
- }
-#endif
- break;
-
- default:
- printk(KERN_ALERT "%s unknown island !!!! \n", __func__);
- break;
- }
-
- }
-
- if (!ret)
- printk(KERN_ALERT "ospm_power_using_hw_begin: forcing on %d failed\n", hw_island);
-
- gbResumeInProgress = false;
- }
-increase_count:
- if (ret) {
- switch(hw_island)
- {
- case OSPM_GRAPHICS_ISLAND:
- atomic_inc(&g_graphics_access_count);
- break;
- case OSPM_VIDEO_ENC_ISLAND:
- atomic_inc(&g_videoenc_access_count);
- break;
- case OSPM_VIDEO_DEC_ISLAND:
- atomic_inc(&g_videodec_access_count);
- break;
- case OSPM_DISPLAY_ISLAND:
- atomic_inc(&g_display_access_count);
- break;
- }
- }
-
- if (!b_atomic && locked)
- mutex_unlock(&power_mutex);
-
- return ret;
-#endif
-}
-
-
-/*
- * ospm_power_using_hw_end
- *
- * Description: Notify PowerMgmt module that you are done accessing the
- * specified island's hw so feel free to power it off. Note that this
- * function doesn't actually power off the islands.
- */
-void ospm_power_using_hw_end(int hw_island)
-{
-#if 0 /* FIXMEAC */
- switch(hw_island)
- {
- case OSPM_GRAPHICS_ISLAND:
- atomic_dec(&g_graphics_access_count);
- break;
- case OSPM_VIDEO_ENC_ISLAND:
- atomic_dec(&g_videoenc_access_count);
- break;
- case OSPM_VIDEO_DEC_ISLAND:
- atomic_dec(&g_videodec_access_count);
- break;
- case OSPM_DISPLAY_ISLAND:
- atomic_dec(&g_display_access_count);
- break;
- }
-
- //decrement runtime pm ref count
- pm_runtime_put(&gpDrmDevice->pdev->dev);
-
- WARN_ON(atomic_read(&g_graphics_access_count) < 0);
- WARN_ON(atomic_read(&g_videoenc_access_count) < 0);
- WARN_ON(atomic_read(&g_videodec_access_count) < 0);
- WARN_ON(atomic_read(&g_display_access_count) < 0);
-#endif
-}
-
-int ospm_runtime_pm_allow(struct drm_device * dev)
-{
+ mutex_lock(&power_mutex);
+ gma_resume_pci(pdev);
+ gma_resume_display(pdev);
+ psb_irq_preinstall(dev);
+ psb_irq_postinstall(dev);
+ mutex_unlock(&power_mutex);
return 0;
}
-void ospm_runtime_pm_forbid(struct drm_device * dev)
+
+
+/**
+ * gma_power_is_on - returne true if power is on
+ * @dev: our DRM device
+ *
+ * Returns true if the display island power is on at this moment
+ */
+bool gma_power_is_on(struct drm_device *dev)
{
- struct drm_psb_private * dev_priv = dev->dev_private;
+ struct drm_psb_private *dev_priv = dev->dev_private;
+ return dev_priv->display_power;
+}
- DRM_INFO("%s\n", __FUNCTION__);
- pm_runtime_forbid(&dev->pdev->dev);
- dev_priv->rpm_enabled = 0;
+/**
+ * gma_power_begin - begin requiring power
+ * @dev: our DRM device
+ * @force_on: true to force power on
+ *
+ * Begin an action that requires the display power island is enabled.
+ * We refcount the islands.
+ *
+ * FIXME: locking
+ */
+bool gma_power_begin(struct drm_device *dev, bool force_on)
+{
+ struct drm_psb_private *dev_priv = dev->dev_private;
+ int ret;
+
+ /* Power already on ? */
+ if (dev_priv->display_power) {
+ dev_priv->display_count++;
+ pm_runtime_get(&dev->pdev->dev);
+ return true;
+ }
+ if (force_on == false)
+ return false;
+
+ /* Ok power up needed */
+ ret = gma_resume_pci(dev->pdev);
+ if (ret == 0) {
+ psb_irq_preinstall(dev);
+ psb_irq_postinstall(dev);
+ pm_runtime_get(&dev->pdev->dev);
+ dev_priv->display_count++;
+ return true;
+ }
+ return false;
+}
+
+
+/**
+ * gma_power_end - end use of power
+ * @dev: Our DRM device
+ *
+ * Indicate that one of our gma_power_begin() requested periods when
+ * the diplay island power is needed has completed.
+ */
+void gma_power_end(struct drm_device *dev)
+{
+ struct drm_psb_private *dev_priv = dev->dev_private;
+ dev_priv->display_count--;
+ WARN_ON(dev_priv->display_count < 0);
+ pm_runtime_put(&dev->pdev->dev);
}
int psb_runtime_suspend(struct device *dev)
{
- pm_message_t state;
- int ret = 0;
- state.event = 0;
-
-#ifdef OSPM_GFX_DPK
- printk(KERN_ALERT "OSPM_GFX_DPK: %s \n", __func__);
-#endif
- if (atomic_read(&g_graphics_access_count) || atomic_read(&g_videoenc_access_count)
- || atomic_read(&g_videodec_access_count) || atomic_read(&g_display_access_count)){
-#ifdef OSPM_GFX_DPK
- printk(KERN_ALERT "OSPM_GFX_DPK: GFX: %d VEC: %d VED: %d DC: %d DSR: %d \n", atomic_read(&g_graphics_access_count),
- atomic_read(&g_videoenc_access_count), atomic_read(&g_videodec_access_count), atomic_read(&g_display_access_count));
-#endif
- return -EBUSY;
- }
- else
- ret = ospm_power_suspend(gpDrmDevice->pdev, state);
-
- return ret;
+ static pm_message_t dummy;
+ return gma_power_suspend(to_pci_dev(dev), dummy);
}
int psb_runtime_resume(struct device *dev)
@@ -782,11 +479,11 @@
int psb_runtime_idle(struct device *dev)
{
- /*printk (KERN_ALERT "lvds:%d,mipi:%d\n", dev_priv->is_lvds_on, dev_priv->is_mipi_on);*/
- if (atomic_read(&g_graphics_access_count) || atomic_read(&g_videoenc_access_count)
- || atomic_read(&g_videodec_access_count) || atomic_read(&g_display_access_count))
- return 1;
- else
+ struct drm_device *drmdev = pci_get_drvdata(to_pci_dev(dev));
+ struct drm_psb_private *dev_priv = drmdev->dev_private;
+ if (dev_priv->display_count)
return 0;
+ else
+ return 1;
}
diff --git a/drivers/staging/gma500/psb_powermgmt.h b/drivers/staging/gma500/psb_powermgmt.h
index bf6f27a..e005229 100644
--- a/drivers/staging/gma500/psb_powermgmt.h
+++ b/drivers/staging/gma500/psb_powermgmt.h
@@ -24,7 +24,8 @@
* Authors:
* Benjamin Defnet <benjamin.r.defnet@intel.com>
* Rajesh Poornachandran <rajesh.poornachandran@intel.com>
- *
+ * Massively reworked
+ * Alan Cox <alan@linux.intel.com>
*/
#ifndef _PSB_POWERMGMT_H_
#define _PSB_POWERMGMT_H_
@@ -32,65 +33,35 @@
#include <linux/pci.h>
#include <drm/drmP.h>
-#define OSPM_GRAPHICS_ISLAND 0x1
-#define OSPM_VIDEO_ENC_ISLAND 0x2
-#define OSPM_VIDEO_DEC_ISLAND 0x4
-#define OSPM_DISPLAY_ISLAND 0x8
-#define OSPM_GL3_CACHE_ISLAND 0x10
-#define OSPM_ALL_ISLANDS 0x1f
-
-/* IPC message and command defines used to enable/disable mipi panel voltages */
-#define IPC_MSG_PANEL_ON_OFF 0xE9
-#define IPC_CMD_PANEL_ON 1
-#define IPC_CMD_PANEL_OFF 0
-
-typedef enum _UHBUsage
-{
- OSPM_UHB_ONLY_IF_ON = 0,
- OSPM_UHB_FORCE_POWER_ON,
-} UHBUsage;
-
-/* Use these functions to power down video HW for D0i3 purpose */
-
-void ospm_power_init(struct drm_device *dev);
-void ospm_power_uninit(void);
-
+void gma_power_init(struct drm_device *dev);
+void gma_power_uninit(struct drm_device *dev);
/*
- * OSPM will call these functions
+ * The kernel bus power management will call these functions
*/
-int ospm_power_suspend(struct pci_dev *pdev, pm_message_t state);
-int ospm_power_resume(struct pci_dev *pdev);
+int gma_power_suspend(struct pci_dev *pdev, pm_message_t state);
+int gma_power_resume(struct pci_dev *pdev);
/*
* These are the functions the driver should use to wrap all hw access
* (i.e. register reads and writes)
*/
-bool ospm_power_using_hw_begin(int hw_island, UHBUsage usage);
-void ospm_power_using_hw_end(int hw_island);
+bool gma_power_begin(struct drm_device *dev, bool force);
+void gma_power_end(struct drm_device *dev);
/*
* Use this function to do an instantaneous check for if the hw is on.
- * Only use this in cases where you know the g_state_change_mutex
- * is already held such as in irq install/uninstall and you need to
- * prevent a deadlock situation. Otherwise use ospm_power_using_hw_begin().
+ * Only use this in cases where you know the mutex is already held such
+ * as in irq install/uninstall and you need to
+ * prevent a deadlock situation. Otherwise use gma_power_begin().
*/
-bool ospm_power_is_hw_on(int hw_islands);
+bool gma_power_is_on(struct drm_device *dev);
/*
- * Power up/down different hw component rails/islands
- */
-void ospm_power_island_down(int hw_islands);
-void ospm_power_island_up(int hw_islands);
-void ospm_suspend_graphics(void);
-/*
* GFX-Runtime PM callbacks
*/
int psb_runtime_suspend(struct device *dev);
int psb_runtime_resume(struct device *dev);
int psb_runtime_idle(struct device *dev);
-int ospm_runtime_pm_allow(struct drm_device * dev);
-void ospm_runtime_pm_forbid(struct drm_device * dev);
-
#endif /*_PSB_POWERMGMT_H_*/
diff --git a/drivers/staging/gma500/psb_pvr_glue.c b/drivers/staging/gma500/psb_pvr_glue.c
deleted file mode 100644
index da78946..0000000
--- a/drivers/staging/gma500/psb_pvr_glue.c
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * Copyright (c) 2009, Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
- *
- */
-
-#include "psb_pvr_glue.h"
-
-/**
- * FIXME: should NOT use these file under env/linux directly
- */
-
-int psb_get_meminfo_by_handle(void *hKernelMemInfo,
- void **ppsKernelMemInfo)
-{
- return -EINVAL;
-#if 0
- void *psKernelMemInfo = IMG_NULL;
- PVRSRV_PER_PROCESS_DATA *psPerProc = IMG_NULL;
- PVRSRV_ERROR eError;
-
- psPerProc = PVRSRVPerProcessData(task_tgid_nr(current));
- eError = PVRSRVLookupHandle(psPerProc->psHandleBase,
- (IMG_VOID *)&psKernelMemInfo,
- hKernelMemInfo,
- PVRSRV_HANDLE_TYPE_MEM_INFO);
- if (eError != PVRSRV_OK) {
- DRM_ERROR("Cannot find kernel meminfo for handle 0x%x\n",
- (u32)hKernelMemInfo);
- return -EINVAL;
- }
-
- *ppsKernelMemInfo = psKernelMemInfo;
-
- DRM_DEBUG("Got Kernel MemInfo for handle %lx\n",
- (u32)hKernelMemInfo);
- return 0;
-#endif
-}
-
-int psb_get_pages_by_mem_handle(void *hOSMemHandle, struct page ***pages)
-{
- return -EINVAL;
-#if 0
- LinuxMemArea *psLinuxMemArea = (LinuxMemArea *)hOSMemHandle;
- struct page **page_list;
- if (psLinuxMemArea->eAreaType != LINUX_MEM_AREA_ALLOC_PAGES) {
- DRM_ERROR("MemArea type is not LINUX_MEM_AREA_ALLOC_PAGES\n");
- return -EINVAL;
- }
-
- page_list = psLinuxMemArea->uData.sPageList.pvPageList;
- if (!page_list) {
- DRM_DEBUG("Page List is NULL\n");
- return -ENOMEM;
- }
-
- *pages = page_list;
- return 0;
-#endif
-}
diff --git a/drivers/staging/gma500/psb_pvr_glue.h b/drivers/staging/gma500/psb_pvr_glue.h
deleted file mode 100644
index dee8cb2..0000000
--- a/drivers/staging/gma500/psb_pvr_glue.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Copyright (c) 2009, Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
- *
- */
-
-#include "psb_drv.h"
-
-extern int psb_get_meminfo_by_handle(void * hKernelMemInfo,
- void **ppsKernelMemInfo);
-extern u32 psb_get_tgid(void);
-extern int psb_get_pages_by_mem_handle(void * hOSMemHandle,
- struct page ***pages);
diff --git a/drivers/staging/gma500/psb_sgx.c b/drivers/staging/gma500/psb_sgx.c
deleted file mode 100644
index 973134b..0000000
--- a/drivers/staging/gma500/psb_sgx.c
+++ /dev/null
@@ -1,238 +0,0 @@
-/**************************************************************************
- * Copyright (c) 2007, Intel Corporation.
- * All Rights Reserved.
- * Copyright (c) 2008, Tungsten Graphics, Inc. Cedar Park, TX. USA.
- * All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
- *
- **************************************************************************/
-
-#include <drm/drmP.h>
-#include "psb_drv.h"
-#include "psb_drm.h"
-#include "psb_reg.h"
-#include "ttm/ttm_bo_api.h"
-#include "ttm/ttm_execbuf_util.h"
-#include "psb_ttm_userobj_api.h"
-#include "ttm/ttm_placement.h"
-#include "psb_sgx.h"
-#include "psb_intel_reg.h"
-#include "psb_powermgmt.h"
-
-
-static inline int psb_same_page(unsigned long offset,
- unsigned long offset2)
-{
- return (offset & PAGE_MASK) == (offset2 & PAGE_MASK);
-}
-
-static inline unsigned long psb_offset_end(unsigned long offset,
- unsigned long end)
-{
- offset = (offset + PAGE_SIZE) & PAGE_MASK;
- return (end < offset) ? end : offset;
-}
-
-struct psb_dstbuf_cache {
- unsigned int dst;
- struct ttm_buffer_object *dst_buf;
- unsigned long dst_offset;
- uint32_t *dst_page;
- unsigned int dst_page_offset;
- struct ttm_bo_kmap_obj dst_kmap;
- bool dst_is_iomem;
-};
-
-struct psb_validate_buffer {
- struct ttm_validate_buffer base;
- struct psb_validate_req req;
- int ret;
- struct psb_validate_arg __user *user_val_arg;
- uint32_t flags;
- uint32_t offset;
- int po_correct;
-};
-static int
-psb_placement_fence_type(struct ttm_buffer_object *bo,
- uint64_t set_val_flags,
- uint64_t clr_val_flags,
- uint32_t new_fence_class,
- uint32_t *new_fence_type)
-{
- int ret;
- uint32_t n_fence_type;
- /*
- uint32_t set_flags = set_val_flags & 0xFFFFFFFF;
- uint32_t clr_flags = clr_val_flags & 0xFFFFFFFF;
- */
- struct ttm_fence_object *old_fence;
- uint32_t old_fence_type;
- struct ttm_placement placement;
-
- if (unlikely
- (!(set_val_flags &
- (PSB_GPU_ACCESS_READ | PSB_GPU_ACCESS_WRITE)))) {
- DRM_ERROR
- ("GPU access type (read / write) is not indicated.\n");
- return -EINVAL;
- }
-
- /* User space driver doesn't set any TTM placement flags in
- set_val_flags or clr_val_flags */
- placement.num_placement = 0;/* FIXME */
- placement.num_busy_placement = 0;
- placement.fpfn = 0;
- placement.lpfn = 0;
- ret = psb_ttm_bo_check_placement(bo, &placement);
- if (unlikely(ret != 0))
- return ret;
-
- switch (new_fence_class) {
- default:
- n_fence_type = _PSB_FENCE_TYPE_EXE;
- }
-
- *new_fence_type = n_fence_type;
- old_fence = (struct ttm_fence_object *) bo->sync_obj;
- old_fence_type = (uint32_t) (unsigned long) bo->sync_obj_arg;
-
- if (old_fence && ((new_fence_class != old_fence->fence_class) ||
- ((n_fence_type ^ old_fence_type) &
- old_fence_type))) {
- ret = ttm_bo_wait(bo, 0, 1, 0);
- if (unlikely(ret != 0))
- return ret;
- }
- /*
- bo->proposed_flags = (bo->proposed_flags | set_flags)
- & ~clr_flags & TTM_PL_MASK_MEMTYPE;
- */
- return 0;
-}
-
-int psb_validate_kernel_buffer(struct psb_context *context,
- struct ttm_buffer_object *bo,
- uint32_t fence_class,
- uint64_t set_flags, uint64_t clr_flags)
-{
- struct psb_validate_buffer *item;
- uint32_t cur_fence_type;
- int ret;
-
- if (unlikely(context->used_buffers >= PSB_NUM_VALIDATE_BUFFERS)) {
- DRM_ERROR("Out of free validation buffer entries for "
- "kernel buffer validation.\n");
- return -ENOMEM;
- }
-
- item = &context->buffers[context->used_buffers];
- item->user_val_arg = NULL;
- item->base.reserved = 0;
-
- ret = ttm_bo_reserve(bo, 1, 0, 1, context->val_seq);
- if (unlikely(ret != 0))
- return ret;
-
- ret = psb_placement_fence_type(bo, set_flags, clr_flags, fence_class,
- &cur_fence_type);
- if (unlikely(ret != 0)) {
- ttm_bo_unreserve(bo);
- return ret;
- }
-
- item->base.bo = ttm_bo_reference(bo);
- item->base.new_sync_obj_arg = (void *) (unsigned long) cur_fence_type;
- item->base.reserved = 1;
-
- /* Internal locking ??? FIXMEAC */
- list_add_tail(&item->base.head, &context->kern_validate_list);
- context->used_buffers++;
- /*
- ret = ttm_bo_validate(bo, 1, 0, 0);
- if (unlikely(ret != 0))
- goto out_unlock;
- */
- item->offset = bo->offset;
- item->flags = bo->mem.placement;
- context->fence_types |= cur_fence_type;
-
- return ret;
-}
-
-void psb_fence_or_sync(struct drm_file *file_priv,
- uint32_t engine,
- uint32_t fence_types,
- uint32_t fence_flags,
- struct list_head *list,
- struct psb_ttm_fence_rep *fence_arg,
- struct ttm_fence_object **fence_p)
-{
- struct drm_device *dev = file_priv->minor->dev;
- struct drm_psb_private *dev_priv = psb_priv(dev);
- struct ttm_fence_device *fdev = &dev_priv->fdev;
- int ret;
- struct ttm_fence_object *fence;
- struct ttm_object_file *tfile = psb_fpriv(file_priv)->tfile;
- uint32_t handle;
-
- ret = ttm_fence_user_create(fdev, tfile,
- engine, fence_types,
- TTM_FENCE_FLAG_EMIT, &fence, &handle);
- if (ret) {
-
- /*
- * Fence creation failed.
- * Fall back to synchronous operation and idle the engine.
- */
-
- if (!(fence_flags & DRM_PSB_FENCE_NO_USER)) {
-
- /*
- * Communicate to user-space that
- * fence creation has failed and that
- * the engine is idle.
- */
-
- fence_arg->handle = ~0;
- fence_arg->error = ret;
- }
-
- ttm_eu_backoff_reservation(list);
- if (fence_p)
- *fence_p = NULL;
- return;
- }
-
- ttm_eu_fence_buffer_objects(list, fence);
- if (!(fence_flags & DRM_PSB_FENCE_NO_USER)) {
- struct ttm_fence_info info = ttm_fence_get_info(fence);
- fence_arg->handle = handle;
- fence_arg->fence_class = ttm_fence_class(fence);
- fence_arg->fence_type = ttm_fence_types(fence);
- fence_arg->signaled_types = info.signaled_types;
- fence_arg->error = 0;
- } else {
- ret =
- ttm_ref_object_base_unref(tfile, handle,
- ttm_fence_type);
- BUG_ON(ret);
- }
-
- if (fence_p)
- *fence_p = fence;
- else if (fence)
- ttm_fence_object_unref(&fence);
-}
-
diff --git a/drivers/staging/gma500/psb_sgx.h b/drivers/staging/gma500/psb_sgx.h
deleted file mode 100644
index 9300e2d..0000000
--- a/drivers/staging/gma500/psb_sgx.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- * Copyright (c) 2008, Intel Corporation
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
- *
- * Authors:
- * Eric Anholt <eric@anholt.net>
- *
- **/
-#ifndef _PSB_SGX_H_
-#define _PSB_SGX_H_
-
-extern int psb_submit_video_cmdbuf(struct drm_device *dev,
- struct ttm_buffer_object *cmd_buffer,
- unsigned long cmd_offset,
- unsigned long cmd_size,
- struct ttm_fence_object *fence);
-
-extern int drm_idle_check_interval;
-
-#endif
diff --git a/drivers/staging/gma500/psb_ttm_fence.c b/drivers/staging/gma500/psb_ttm_fence.c
deleted file mode 100644
index d1c3590..0000000
--- a/drivers/staging/gma500/psb_ttm_fence.c
+++ /dev/null
@@ -1,605 +0,0 @@
-/**************************************************************************
- *
- * Copyright (c) 2006-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA
- * All Rights Reserved.
- * Copyright (c) 2009 VMware, Inc., Palo Alto, CA., USA
- * All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
- *
- **************************************************************************/
-/*
- * Authors: Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
- */
-
-#include "psb_ttm_fence_api.h"
-#include "psb_ttm_fence_driver.h"
-#include <linux/wait.h>
-#include <linux/sched.h>
-
-#include <drm/drmP.h>
-
-/*
- * Simple implementation for now.
- */
-
-static void ttm_fence_lockup(struct ttm_fence_object *fence, uint32_t mask)
-{
- struct ttm_fence_class_manager *fc = ttm_fence_fc(fence);
-
- printk(KERN_ERR "GPU lockup dectected on engine %u "
- "fence type 0x%08x\n",
- (unsigned int)fence->fence_class, (unsigned int)mask);
- /*
- * Give engines some time to idle?
- */
-
- write_lock(&fc->lock);
- ttm_fence_handler(fence->fdev, fence->fence_class,
- fence->sequence, mask, -EBUSY);
- write_unlock(&fc->lock);
-}
-
-/*
- * Convenience function to be called by fence::wait methods that
- * need polling.
- */
-
-int ttm_fence_wait_polling(struct ttm_fence_object *fence, bool lazy,
- bool interruptible, uint32_t mask)
-{
- struct ttm_fence_class_manager *fc = ttm_fence_fc(fence);
- const struct ttm_fence_driver *driver = ttm_fence_driver(fence);
- uint32_t count = 0;
- int ret;
- unsigned long end_jiffies = fence->timeout_jiffies;
-
- DECLARE_WAITQUEUE(entry, current);
- add_wait_queue(&fc->fence_queue, &entry);
-
- ret = 0;
-
- for (;;) {
- __set_current_state((interruptible) ?
- TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
- if (ttm_fence_object_signaled(fence, mask))
- break;
- if (time_after_eq(jiffies, end_jiffies)) {
- if (driver->lockup)
- driver->lockup(fence, mask);
- else
- ttm_fence_lockup(fence, mask);
- continue;
- }
- if (lazy)
- schedule_timeout(1);
- else if ((++count & 0x0F) == 0) {
- __set_current_state(TASK_RUNNING);
- schedule();
- __set_current_state((interruptible) ?
- TASK_INTERRUPTIBLE :
- TASK_UNINTERRUPTIBLE);
- }
- if (interruptible && signal_pending(current)) {
- ret = -ERESTART;
- break;
- }
- }
- __set_current_state(TASK_RUNNING);
- remove_wait_queue(&fc->fence_queue, &entry);
- return ret;
-}
-
-/*
- * Typically called by the IRQ handler.
- */
-
-void ttm_fence_handler(struct ttm_fence_device *fdev, uint32_t fence_class,
- uint32_t sequence, uint32_t type, uint32_t error)
-{
- int wake = 0;
- uint32_t diff;
- uint32_t relevant_type;
- uint32_t new_type;
- struct ttm_fence_class_manager *fc = &fdev->fence_class[fence_class];
- const struct ttm_fence_driver *driver = ttm_fence_driver_from_dev(fdev);
- struct list_head *head;
- struct ttm_fence_object *fence, *next;
- bool found = false;
-
- if (list_empty(&fc->ring))
- return;
-
- list_for_each_entry(fence, &fc->ring, ring) {
- diff = (sequence - fence->sequence) & fc->sequence_mask;
- if (diff > fc->wrap_diff) {
- found = true;
- break;
- }
- }
-
- fc->waiting_types &= ~type;
- head = (found) ? &fence->ring : &fc->ring;
-
- list_for_each_entry_safe_reverse(fence, next, head, ring) {
- if (&fence->ring == &fc->ring)
- break;
-
- DRM_DEBUG("Fence 0x%08lx, sequence 0x%08x, type 0x%08x\n",
- (unsigned long)fence, fence->sequence,
- fence->fence_type);
-
- if (error) {
- fence->info.error = error;
- fence->info.signaled_types = fence->fence_type;
- list_del_init(&fence->ring);
- wake = 1;
- break;
- }
-
- relevant_type = type & fence->fence_type;
- new_type = (fence->info.signaled_types | relevant_type) ^
- fence->info.signaled_types;
-
- if (new_type) {
- fence->info.signaled_types |= new_type;
- DRM_DEBUG("Fence 0x%08lx signaled 0x%08x\n",
- (unsigned long)fence,
- fence->info.signaled_types);
-
- if (unlikely(driver->signaled))
- driver->signaled(fence);
-
- if (driver->needed_flush)
- fc->pending_flush |=
- driver->needed_flush(fence);
-
- if (new_type & fence->waiting_types)
- wake = 1;
- }
-
- fc->waiting_types |=
- fence->waiting_types & ~fence->info.signaled_types;
-
- if (!(fence->fence_type & ~fence->info.signaled_types)) {
- DRM_DEBUG("Fence completely signaled 0x%08lx\n",
- (unsigned long)fence);
- list_del_init(&fence->ring);
- }
- }
-
- /*
- * Reinstate lost waiting types.
- */
-
- if ((fc->waiting_types & type) != type) {
- head = head->prev;
- list_for_each_entry(fence, head, ring) {
- if (&fence->ring == &fc->ring)
- break;
- diff =
- (fc->highest_waiting_sequence -
- fence->sequence) & fc->sequence_mask;
- if (diff > fc->wrap_diff)
- break;
-
- fc->waiting_types |=
- fence->waiting_types & ~fence->info.signaled_types;
- }
- }
-
- if (wake)
- wake_up_all(&fc->fence_queue);
-}
-
-static void ttm_fence_unring(struct ttm_fence_object *fence)
-{
- struct ttm_fence_class_manager *fc = ttm_fence_fc(fence);
- unsigned long irq_flags;
-
- write_lock_irqsave(&fc->lock, irq_flags);
- list_del_init(&fence->ring);
- write_unlock_irqrestore(&fc->lock, irq_flags);
-}
-
-bool ttm_fence_object_signaled(struct ttm_fence_object *fence, uint32_t mask)
-{
- unsigned long flags;
- bool signaled;
- const struct ttm_fence_driver *driver = ttm_fence_driver(fence);
- struct ttm_fence_class_manager *fc = ttm_fence_fc(fence);
-
- mask &= fence->fence_type;
- read_lock_irqsave(&fc->lock, flags);
- signaled = (mask & fence->info.signaled_types) == mask;
- read_unlock_irqrestore(&fc->lock, flags);
- if (!signaled && driver->poll) {
- write_lock_irqsave(&fc->lock, flags);
- driver->poll(fence->fdev, fence->fence_class, mask);
- signaled = (mask & fence->info.signaled_types) == mask;
- write_unlock_irqrestore(&fc->lock, flags);
- }
- return signaled;
-}
-
-int ttm_fence_object_flush(struct ttm_fence_object *fence, uint32_t type)
-{
- const struct ttm_fence_driver *driver = ttm_fence_driver(fence);
- struct ttm_fence_class_manager *fc = ttm_fence_fc(fence);
- unsigned long irq_flags;
- uint32_t saved_pending_flush;
- uint32_t diff;
- bool call_flush;
-
- if (type & ~fence->fence_type) {
- DRM_ERROR("Flush trying to extend fence type, "
- "0x%x, 0x%x\n", type, fence->fence_type);
- return -EINVAL;
- }
-
- write_lock_irqsave(&fc->lock, irq_flags);
- fence->waiting_types |= type;
- fc->waiting_types |= fence->waiting_types;
- diff = (fence->sequence - fc->highest_waiting_sequence) &
- fc->sequence_mask;
-
- if (diff < fc->wrap_diff)
- fc->highest_waiting_sequence = fence->sequence;
-
- /*
- * fence->waiting_types has changed. Determine whether
- * we need to initiate some kind of flush as a result of this.
- */
-
- saved_pending_flush = fc->pending_flush;
- if (driver->needed_flush)
- fc->pending_flush |= driver->needed_flush(fence);
-
- if (driver->poll)
- driver->poll(fence->fdev, fence->fence_class,
- fence->waiting_types);
-
- call_flush = (fc->pending_flush != 0);
- write_unlock_irqrestore(&fc->lock, irq_flags);
-
- if (call_flush && driver->flush)
- driver->flush(fence->fdev, fence->fence_class);
-
- return 0;
-}
-
-/*
- * Make sure old fence objects are signaled before their fence sequences are
- * wrapped around and reused.
- */
-
-void ttm_fence_flush_old(struct ttm_fence_device *fdev,
- uint32_t fence_class, uint32_t sequence)
-{
- struct ttm_fence_class_manager *fc = &fdev->fence_class[fence_class];
- struct ttm_fence_object *fence;
- unsigned long irq_flags;
- const struct ttm_fence_driver *driver = fdev->driver;
- bool call_flush;
-
- uint32_t diff;
-
- write_lock_irqsave(&fc->lock, irq_flags);
-
- list_for_each_entry_reverse(fence, &fc->ring, ring) {
- diff = (sequence - fence->sequence) & fc->sequence_mask;
- if (diff <= fc->flush_diff)
- break;
-
- fence->waiting_types = fence->fence_type;
- fc->waiting_types |= fence->fence_type;
-
- if (driver->needed_flush)
- fc->pending_flush |= driver->needed_flush(fence);
- }
-
- if (driver->poll)
- driver->poll(fdev, fence_class, fc->waiting_types);
-
- call_flush = (fc->pending_flush != 0);
- write_unlock_irqrestore(&fc->lock, irq_flags);
-
- if (call_flush && driver->flush)
- driver->flush(fdev, fence->fence_class);
-
- /*
- * FIXME: Shold we implement a wait here for really old fences?
- */
-
-}
-
-int ttm_fence_object_wait(struct ttm_fence_object *fence,
- bool lazy, bool interruptible, uint32_t mask)
-{
- const struct ttm_fence_driver *driver = ttm_fence_driver(fence);
- struct ttm_fence_class_manager *fc = ttm_fence_fc(fence);
- int ret = 0;
- unsigned long timeout;
- unsigned long cur_jiffies;
- unsigned long to_jiffies;
-
- if (mask & ~fence->fence_type) {
- DRM_ERROR("Wait trying to extend fence type"
- " 0x%08x 0x%08x\n", mask, fence->fence_type);
- BUG();
- return -EINVAL;
- }
-
- if (driver->wait)
- return driver->wait(fence, lazy, interruptible, mask);
-
- ttm_fence_object_flush(fence, mask);
-retry:
- if (!driver->has_irq ||
- driver->has_irq(fence->fdev, fence->fence_class, mask)) {
-
- cur_jiffies = jiffies;
- to_jiffies = fence->timeout_jiffies;
-
- timeout = (time_after(to_jiffies, cur_jiffies)) ?
- to_jiffies - cur_jiffies : 1;
-
- if (interruptible)
- ret = wait_event_interruptible_timeout
- (fc->fence_queue,
- ttm_fence_object_signaled(fence, mask), timeout);
- else
- ret = wait_event_timeout
- (fc->fence_queue,
- ttm_fence_object_signaled(fence, mask), timeout);
-
- if (unlikely(ret == -ERESTARTSYS))
- return -ERESTART;
-
- if (unlikely(ret == 0)) {
- if (driver->lockup)
- driver->lockup(fence, mask);
- else
- ttm_fence_lockup(fence, mask);
- goto retry;
- }
-
- return 0;
- }
-
- return ttm_fence_wait_polling(fence, lazy, interruptible, mask);
-}
-
-int ttm_fence_object_emit(struct ttm_fence_object *fence, uint32_t fence_flags,
- uint32_t fence_class, uint32_t type)
-{
- const struct ttm_fence_driver *driver = ttm_fence_driver(fence);
- struct ttm_fence_class_manager *fc = ttm_fence_fc(fence);
- unsigned long flags;
- uint32_t sequence;
- unsigned long timeout;
- int ret;
-
- ttm_fence_unring(fence);
- ret = driver->emit(fence->fdev,
- fence_class, fence_flags, &sequence, &timeout);
- if (ret)
- return ret;
-
- write_lock_irqsave(&fc->lock, flags);
- fence->fence_class = fence_class;
- fence->fence_type = type;
- fence->waiting_types = 0;
- fence->info.signaled_types = 0;
- fence->info.error = 0;
- fence->sequence = sequence;
- fence->timeout_jiffies = timeout;
- if (list_empty(&fc->ring))
- fc->highest_waiting_sequence = sequence - 1;
- list_add_tail(&fence->ring, &fc->ring);
- fc->latest_queued_sequence = sequence;
- write_unlock_irqrestore(&fc->lock, flags);
- return 0;
-}
-
-int ttm_fence_object_init(struct ttm_fence_device *fdev,
- uint32_t fence_class,
- uint32_t type,
- uint32_t create_flags,
- void (*destroy) (struct ttm_fence_object *),
- struct ttm_fence_object *fence)
-{
- int ret = 0;
-
- kref_init(&fence->kref);
- fence->fence_class = fence_class;
- fence->fence_type = type;
- fence->info.signaled_types = 0;
- fence->waiting_types = 0;
- fence->sequence = 0;
- fence->info.error = 0;
- fence->fdev = fdev;
- fence->destroy = destroy;
- INIT_LIST_HEAD(&fence->ring);
- atomic_inc(&fdev->count);
-
- if (create_flags & TTM_FENCE_FLAG_EMIT) {
- ret = ttm_fence_object_emit(fence, create_flags,
- fence->fence_class, type);
- }
-
- return ret;
-}
-
-int ttm_fence_object_create(struct ttm_fence_device *fdev,
- uint32_t fence_class,
- uint32_t type,
- uint32_t create_flags,
- struct ttm_fence_object **c_fence)
-{
- struct ttm_fence_object *fence;
- int ret;
-
- ret = ttm_mem_global_alloc(fdev->mem_glob,
- sizeof(*fence),
- false,
- false);
- if (unlikely(ret != 0)) {
- printk(KERN_ERR "Out of memory creating fence object\n");
- return ret;
- }
-
- fence = kmalloc(sizeof(*fence), GFP_KERNEL);
- if (!fence) {
- printk(KERN_ERR "Out of memory creating fence object\n");
- ttm_mem_global_free(fdev->mem_glob, sizeof(*fence));
- return -ENOMEM;
- }
-
- ret = ttm_fence_object_init(fdev, fence_class, type,
- create_flags, NULL, fence);
- if (ret) {
- ttm_fence_object_unref(&fence);
- return ret;
- }
- *c_fence = fence;
-
- return 0;
-}
-
-static void ttm_fence_object_destroy(struct kref *kref)
-{
- struct ttm_fence_object *fence =
- container_of(kref, struct ttm_fence_object, kref);
- struct ttm_fence_class_manager *fc = ttm_fence_fc(fence);
- unsigned long irq_flags;
-
- write_lock_irqsave(&fc->lock, irq_flags);
- list_del_init(&fence->ring);
- write_unlock_irqrestore(&fc->lock, irq_flags);
-
- atomic_dec(&fence->fdev->count);
- if (fence->destroy)
- fence->destroy(fence);
- else {
- ttm_mem_global_free(fence->fdev->mem_glob,
- sizeof(*fence));
- kfree(fence);
- }
-}
-
-void ttm_fence_device_release(struct ttm_fence_device *fdev)
-{
- kfree(fdev->fence_class);
-}
-
-int
-ttm_fence_device_init(int num_classes,
- struct ttm_mem_global *mem_glob,
- struct ttm_fence_device *fdev,
- const struct ttm_fence_class_init *init,
- bool replicate_init,
- const struct ttm_fence_driver *driver)
-{
- struct ttm_fence_class_manager *fc;
- const struct ttm_fence_class_init *fci;
- int i;
-
- fdev->mem_glob = mem_glob;
- fdev->fence_class = kzalloc(num_classes *
- sizeof(*fdev->fence_class), GFP_KERNEL);
-
- if (unlikely(!fdev->fence_class))
- return -ENOMEM;
-
- fdev->num_classes = num_classes;
- atomic_set(&fdev->count, 0);
- fdev->driver = driver;
-
- for (i = 0; i < fdev->num_classes; ++i) {
- fc = &fdev->fence_class[i];
- fci = &init[(replicate_init) ? 0 : i];
-
- fc->wrap_diff = fci->wrap_diff;
- fc->flush_diff = fci->flush_diff;
- fc->sequence_mask = fci->sequence_mask;
-
- rwlock_init(&fc->lock);
- INIT_LIST_HEAD(&fc->ring);
- init_waitqueue_head(&fc->fence_queue);
- }
-
- return 0;
-}
-
-struct ttm_fence_info ttm_fence_get_info(struct ttm_fence_object *fence)
-{
- struct ttm_fence_class_manager *fc = ttm_fence_fc(fence);
- struct ttm_fence_info tmp;
- unsigned long irq_flags;
-
- read_lock_irqsave(&fc->lock, irq_flags);
- tmp = fence->info;
- read_unlock_irqrestore(&fc->lock, irq_flags);
-
- return tmp;
-}
-
-void ttm_fence_object_unref(struct ttm_fence_object **p_fence)
-{
- struct ttm_fence_object *fence = *p_fence;
-
- *p_fence = NULL;
- (void)kref_put(&fence->kref, &ttm_fence_object_destroy);
-}
-
-/*
- * Placement / BO sync object glue.
- */
-
-bool ttm_fence_sync_obj_signaled(void *sync_obj, void *sync_arg)
-{
- struct ttm_fence_object *fence = (struct ttm_fence_object *)sync_obj;
- uint32_t fence_types = (uint32_t) (unsigned long)sync_arg;
-
- return ttm_fence_object_signaled(fence, fence_types);
-}
-
-int ttm_fence_sync_obj_wait(void *sync_obj, void *sync_arg,
- bool lazy, bool interruptible)
-{
- struct ttm_fence_object *fence = (struct ttm_fence_object *)sync_obj;
- uint32_t fence_types = (uint32_t) (unsigned long)sync_arg;
-
- return ttm_fence_object_wait(fence, lazy, interruptible, fence_types);
-}
-
-int ttm_fence_sync_obj_flush(void *sync_obj, void *sync_arg)
-{
- struct ttm_fence_object *fence = (struct ttm_fence_object *)sync_obj;
- uint32_t fence_types = (uint32_t) (unsigned long)sync_arg;
-
- return ttm_fence_object_flush(fence, fence_types);
-}
-
-void ttm_fence_sync_obj_unref(void **sync_obj)
-{
- ttm_fence_object_unref((struct ttm_fence_object **)sync_obj);
-}
-
-void *ttm_fence_sync_obj_ref(void *sync_obj)
-{
- return (void *)
- ttm_fence_object_ref((struct ttm_fence_object *)sync_obj);
-}
diff --git a/drivers/staging/gma500/psb_ttm_fence_api.h b/drivers/staging/gma500/psb_ttm_fence_api.h
deleted file mode 100644
index b14a427..0000000
--- a/drivers/staging/gma500/psb_ttm_fence_api.h
+++ /dev/null
@@ -1,272 +0,0 @@
-/**************************************************************************
- *
- * Copyright (c) 2006-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA
- * All Rights Reserved.
- * Copyright (c) 2009 VMware, Inc., Palo Alto, CA., USA
- * All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
- *
- **************************************************************************/
-/*
- * Authors: Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
- */
-#ifndef _TTM_FENCE_API_H_
-#define _TTM_FENCE_API_H_
-
-#include <linux/list.h>
-#include <linux/kref.h>
-
-#define TTM_FENCE_FLAG_EMIT (1 << 0)
-#define TTM_FENCE_TYPE_EXE (1 << 0)
-
-struct ttm_fence_device;
-
-/**
- * struct ttm_fence_info
- *
- * @fence_class: The fence class.
- * @fence_type: Bitfield indicating types for this fence.
- * @signaled_types: Bitfield indicating which types are signaled.
- * @error: Last error reported from the device.
- *
- * Used as output from the ttm_fence_get_info
- */
-
-struct ttm_fence_info {
- uint32_t signaled_types;
- uint32_t error;
-};
-
-/**
- * struct ttm_fence_object
- *
- * @fdev: Pointer to the fence device struct.
- * @kref: Holds the reference count of this fence object.
- * @ring: List head used for the circular list of not-completely
- * signaled fences.
- * @info: Data for fast retrieval using the ttm_fence_get_info()
- * function.
- * @timeout_jiffies: Absolute jiffies value indicating when this fence
- * object times out and, if waited on, calls ttm_fence_lockup
- * to check for and resolve a GPU lockup.
- * @sequence: Fence sequence number.
- * @waiting_types: Types currently waited on.
- * @destroy: Called to free the fence object, when its refcount has
- * reached zero. If NULL, kfree is used.
- *
- * This struct is provided in the driver interface so that drivers can
- * derive from it and create their own fence implementation. All members
- * are private to the fence implementation and the fence driver callbacks.
- * Otherwise a driver may access the derived object using container_of().
- */
-
-struct ttm_fence_object {
- struct ttm_fence_device *fdev;
- struct kref kref;
- uint32_t fence_class;
- uint32_t fence_type;
-
- /*
- * The below fields are protected by the fence class
- * manager spinlock.
- */
-
- struct list_head ring;
- struct ttm_fence_info info;
- unsigned long timeout_jiffies;
- uint32_t sequence;
- uint32_t waiting_types;
- void (*destroy) (struct ttm_fence_object *);
-};
-
-/**
- * ttm_fence_object_init
- *
- * @fdev: Pointer to a struct ttm_fence_device.
- * @fence_class: Fence class for this fence.
- * @type: Fence type for this fence.
- * @create_flags: Flags indicating varios actions at init time. At this point
- * there's only TTM_FENCE_FLAG_EMIT, which triggers a sequence emission to
- * the command stream.
- * @destroy: Destroy function. If NULL, kfree() is used.
- * @fence: The struct ttm_fence_object to initialize.
- *
- * Initialize a pre-allocated fence object. This function, together with the
- * destroy function makes it possible to derive driver-specific fence objects.
- */
-
-extern int
-ttm_fence_object_init(struct ttm_fence_device *fdev,
- uint32_t fence_class,
- uint32_t type,
- uint32_t create_flags,
- void (*destroy) (struct ttm_fence_object *fence),
- struct ttm_fence_object *fence);
-
-/**
- * ttm_fence_object_create
- *
- * @fdev: Pointer to a struct ttm_fence_device.
- * @fence_class: Fence class for this fence.
- * @type: Fence type for this fence.
- * @create_flags: Flags indicating varios actions at init time. At this point
- * there's only TTM_FENCE_FLAG_EMIT, which triggers a sequence emission to
- * the command stream.
- * @c_fence: On successful termination, *(@c_fence) will point to the created
- * fence object.
- *
- * Create and initialize a struct ttm_fence_object. The destroy function will
- * be set to kfree().
- */
-
-extern int
-ttm_fence_object_create(struct ttm_fence_device *fdev,
- uint32_t fence_class,
- uint32_t type,
- uint32_t create_flags,
- struct ttm_fence_object **c_fence);
-
-/**
- * ttm_fence_object_wait
- *
- * @fence: The fence object to wait on.
- * @lazy: Allow sleeps to reduce the cpu-usage if polling.
- * @interruptible: Sleep interruptible when waiting.
- * @type_mask: Wait for the given type_mask to signal.
- *
- * Wait for a fence to signal the given type_mask. The function will
- * perform a fence_flush using type_mask. (See ttm_fence_object_flush).
- *
- * Returns
- * -ERESTART if interrupted by a signal.
- * May return driver-specific error codes if timed-out.
- */
-
-extern int
-ttm_fence_object_wait(struct ttm_fence_object *fence,
- bool lazy, bool interruptible, uint32_t type_mask);
-
-/**
- * ttm_fence_object_flush
- *
- * @fence: The fence object to flush.
- * @flush_mask: Fence types to flush.
- *
- * Make sure that the given fence eventually signals the
- * types indicated by @flush_mask. Note that this may or may not
- * map to a CPU or GPU flush.
- */
-
-extern int
-ttm_fence_object_flush(struct ttm_fence_object *fence, uint32_t flush_mask);
-
-/**
- * ttm_fence_get_info
- *
- * @fence: The fence object.
- *
- * Copy the info block from the fence while holding relevant locks.
- */
-
-struct ttm_fence_info ttm_fence_get_info(struct ttm_fence_object *fence);
-
-/**
- * ttm_fence_object_ref
- *
- * @fence: The fence object.
- *
- * Return a ref-counted pointer to the fence object indicated by @fence.
- */
-
-static inline struct ttm_fence_object *ttm_fence_object_ref(struct
- ttm_fence_object
- *fence)
-{
- kref_get(&fence->kref);
- return fence;
-}
-
-/**
- * ttm_fence_object_unref
- *
- * @p_fence: Pointer to a ref-counted pinter to a struct ttm_fence_object.
- *
- * Unreference the fence object pointed to by *(@p_fence), clearing
- * *(p_fence).
- */
-
-extern void ttm_fence_object_unref(struct ttm_fence_object **p_fence);
-
-/**
- * ttm_fence_object_signaled
- *
- * @fence: Pointer to the struct ttm_fence_object.
- * @mask: Type mask to check whether signaled.
- *
- * This function checks (without waiting) whether the fence object
- * pointed to by @fence has signaled the types indicated by @mask,
- * and returns 1 if true, 0 if false. This function does NOT perform
- * an implicit fence flush.
- */
-
-extern bool
-ttm_fence_object_signaled(struct ttm_fence_object *fence, uint32_t mask);
-
-/**
- * ttm_fence_class
- *
- * @fence: Pointer to the struct ttm_fence_object.
- *
- * Convenience function that returns the fence class of a
- * struct ttm_fence_object.
- */
-
-static inline uint32_t ttm_fence_class(const struct ttm_fence_object *fence)
-{
- return fence->fence_class;
-}
-
-/**
- * ttm_fence_types
- *
- * @fence: Pointer to the struct ttm_fence_object.
- *
- * Convenience function that returns the fence types of a
- * struct ttm_fence_object.
- */
-
-static inline uint32_t ttm_fence_types(const struct ttm_fence_object *fence)
-{
- return fence->fence_type;
-}
-
-/*
- * The functions below are wrappers to the above functions, with
- * similar names but with sync_obj omitted. These wrappers are intended
- * to be plugged directly into the buffer object driver's sync object
- * API, if the driver chooses to use ttm_fence_objects as buffer object
- * sync objects. In the prototypes below, a sync_obj is cast to a
- * struct ttm_fence_object, whereas a sync_arg is cast to an
- * uint32_t representing a fence_type argument.
- */
-
-extern bool ttm_fence_sync_obj_signaled(void *sync_obj, void *sync_arg);
-extern int ttm_fence_sync_obj_wait(void *sync_obj, void *sync_arg,
- bool lazy, bool interruptible);
-extern int ttm_fence_sync_obj_flush(void *sync_obj, void *sync_arg);
-extern void ttm_fence_sync_obj_unref(void **sync_obj);
-extern void *ttm_fence_sync_obj_ref(void *sync_obj);
-
-#endif
diff --git a/drivers/staging/gma500/psb_ttm_fence_driver.h b/drivers/staging/gma500/psb_ttm_fence_driver.h
deleted file mode 100644
index c35c569..0000000
--- a/drivers/staging/gma500/psb_ttm_fence_driver.h
+++ /dev/null
@@ -1,302 +0,0 @@
-/**************************************************************************
- *
- * Copyright (c) 2006-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA
- * All Rights Reserved.
- * Copyright (c) 2009 VMware, Inc., Palo Alto, CA., USA
- * All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
- *
- **************************************************************************/
-/*
- * Authors: Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
- */
-#ifndef _TTM_FENCE_DRIVER_H_
-#define _TTM_FENCE_DRIVER_H_
-
-#include <linux/kref.h>
-#include <linux/spinlock.h>
-#include <linux/wait.h>
-#include "psb_ttm_fence_api.h"
-#include "ttm/ttm_memory.h"
-
-/** @file ttm_fence_driver.h
- *
- * Definitions needed for a driver implementing the
- * ttm_fence subsystem.
- */
-
-/**
- * struct ttm_fence_class_manager:
- *
- * @wrap_diff: Sequence difference to catch 32-bit wrapping.
- * if (seqa - seqb) > @wrap_diff, then seqa < seqb.
- * @flush_diff: Sequence difference to trigger fence flush.
- * if (cur_seq - seqa) > @flush_diff, then consider fence object with
- * seqa as old an needing a flush.
- * @sequence_mask: Mask of valid bits in a fence sequence.
- * @lock: Lock protecting this struct as well as fence objects
- * associated with this struct.
- * @ring: Circular sequence-ordered list of fence objects.
- * @pending_flush: Fence types currently needing a flush.
- * @waiting_types: Fence types that are currently waited for.
- * @fence_queue: Queue of waiters on fences belonging to this fence class.
- * @highest_waiting_sequence: Sequence number of the fence with highest
- * sequence number and that is waited for.
- * @latest_queued_sequence: Sequence number of the fence latest queued
- * on the ring.
- */
-
-struct ttm_fence_class_manager {
-
- /*
- * Unprotected constant members.
- */
-
- uint32_t wrap_diff;
- uint32_t flush_diff;
- uint32_t sequence_mask;
-
- /*
- * The rwlock protects this structure as well as
- * the data in all fence objects belonging to this
- * class. This should be OK as most fence objects are
- * only read from once they're created.
- */
-
- rwlock_t lock;
- struct list_head ring;
- uint32_t pending_flush;
- uint32_t waiting_types;
- wait_queue_head_t fence_queue;
- uint32_t highest_waiting_sequence;
- uint32_t latest_queued_sequence;
-};
-
-/**
- * struct ttm_fence_device
- *
- * @fence_class: Array of fence class managers.
- * @num_classes: Array dimension of @fence_class.
- * @count: Current number of fence objects for statistics.
- * @driver: Driver struct.
- *
- * Provided in the driver interface so that the driver can derive
- * from this struct for its driver_private, and accordingly
- * access the driver_private from the fence driver callbacks.
- *
- * All members except "count" are initialized at creation and
- * never touched after that. No protection needed.
- *
- * This struct is private to the fence implementation and to the fence
- * driver callbacks, and may otherwise be used by drivers only to
- * obtain the derived device_private object using container_of().
- */
-
-struct ttm_fence_device {
- struct ttm_mem_global *mem_glob;
- struct ttm_fence_class_manager *fence_class;
- uint32_t num_classes;
- atomic_t count;
- const struct ttm_fence_driver *driver;
-};
-
-/**
- * struct ttm_fence_class_init
- *
- * @wrap_diff: Fence sequence number wrap indicator. If
- * (sequence1 - sequence2) > @wrap_diff, then sequence1 is
- * considered to be older than sequence2.
- * @flush_diff: Fence sequence number flush indicator.
- * If a non-completely-signaled fence has a fence sequence number
- * sequence1 and (sequence1 - current_emit_sequence) > @flush_diff,
- * the fence is considered too old and it will be flushed upon the
- * next call of ttm_fence_flush_old(), to make sure no fences with
- * stale sequence numbers remains unsignaled. @flush_diff should
- * be sufficiently less than @wrap_diff.
- * @sequence_mask: Mask with valid bits of the fence sequence
- * number set to 1.
- *
- * This struct is used as input to ttm_fence_device_init.
- */
-
-struct ttm_fence_class_init {
- uint32_t wrap_diff;
- uint32_t flush_diff;
- uint32_t sequence_mask;
-};
-
-/**
- * struct ttm_fence_driver
- *
- * @has_irq: Called by a potential waiter. Should return 1 if a
- * fence object with indicated parameters is expected to signal
- * automatically, and 0 if the fence implementation needs to
- * repeatedly call @poll to make it signal.
- * @emit: Make sure a fence with the given parameters is
- * present in the indicated command stream. Return its sequence number
- * in "breadcrumb".
- * @poll: Check and report sequences of the given "fence_class"
- * that have signaled "types"
- * @flush: Make sure that the types indicated by the bitfield
- * ttm_fence_class_manager::pending_flush will eventually
- * signal. These bits have been put together using the
- * result from the needed_flush function described below.
- * @needed_flush: Given the fence_class and fence_types indicated by
- * "fence", and the last received fence sequence of this
- * fence class, indicate what types need a fence flush to
- * signal. Return as a bitfield.
- * @wait: Set to non-NULL if the driver wants to override the fence
- * wait implementation. Return 0 on success, -EBUSY on failure,
- * and -ERESTART if interruptible and a signal is pending.
- * @signaled: Driver callback that is called whenever a
- * ttm_fence_object::signaled_types has changed status.
- * This function is called from atomic context,
- * with the ttm_fence_class_manager::lock held in write mode.
- * @lockup: Driver callback that is called whenever a wait has exceeded
- * the lifetime of a fence object.
- * If there is a GPU lockup,
- * this function should, if possible, reset the GPU,
- * call the ttm_fence_handler with an error status, and
- * return. If no lockup was detected, simply extend the
- * fence timeout_jiffies and return. The driver might
- * want to protect the lockup check with a mutex and cache a
- * non-locked-up status for a while to avoid an excessive
- * amount of lockup checks from every waiting thread.
- */
-
-struct ttm_fence_driver {
- bool (*has_irq) (struct ttm_fence_device *fdev,
- uint32_t fence_class, uint32_t flags);
- int (*emit) (struct ttm_fence_device *fdev,
- uint32_t fence_class,
- uint32_t flags,
- uint32_t *breadcrumb, unsigned long *timeout_jiffies);
- void (*flush) (struct ttm_fence_device *fdev, uint32_t fence_class);
- void (*poll) (struct ttm_fence_device *fdev,
- uint32_t fence_class, uint32_t types);
- uint32_t(*needed_flush)
- (struct ttm_fence_object *fence);
- int (*wait) (struct ttm_fence_object *fence, bool lazy,
- bool interruptible, uint32_t mask);
- void (*signaled) (struct ttm_fence_object *fence);
- void (*lockup) (struct ttm_fence_object *fence, uint32_t fence_types);
-};
-
-/**
- * function ttm_fence_device_init
- *
- * @num_classes: Number of fence classes for this fence implementation.
- * @mem_global: Pointer to the global memory accounting info.
- * @fdev: Pointer to an uninitialised struct ttm_fence_device.
- * @init: Array of initialization info for each fence class.
- * @replicate_init: Use the first @init initialization info for all classes.
- * @driver: Driver callbacks.
- *
- * Initialize a struct ttm_fence_driver structure. Returns -ENOMEM if
- * out-of-memory. Otherwise returns 0.
- */
-extern int
-ttm_fence_device_init(int num_classes,
- struct ttm_mem_global *mem_glob,
- struct ttm_fence_device *fdev,
- const struct ttm_fence_class_init *init,
- bool replicate_init,
- const struct ttm_fence_driver *driver);
-
-/**
- * function ttm_fence_device_release
- *
- * @fdev: Pointer to the fence device.
- *
- * Release all resources held by a fence device. Note that before
- * this function is called, the caller must have made sure all fence
- * objects belonging to this fence device are completely signaled.
- */
-
-extern void ttm_fence_device_release(struct ttm_fence_device *fdev);
-
-/**
- * ttm_fence_handler - the fence handler.
- *
- * @fdev: Pointer to the fence device.
- * @fence_class: Fence class that signals.
- * @sequence: Signaled sequence.
- * @type: Types that signal.
- * @error: Error from the engine.
- *
- * This function signals all fences with a sequence previous to the
- * @sequence argument, and belonging to @fence_class. The signaled fence
- * types are provided in @type. If error is non-zero, the error member
- * of the fence with sequence = @sequence is set to @error. This value
- * may be reported back to user-space, indicating, for example an illegal
- * 3D command or illegal mpeg data.
- *
- * This function is typically called from the driver::poll method when the
- * command sequence preceding the fence marker has executed. It should be
- * called with the ttm_fence_class_manager::lock held in write mode and
- * may be called from interrupt context.
- */
-
-extern void
-ttm_fence_handler(struct ttm_fence_device *fdev,
- uint32_t fence_class,
- uint32_t sequence, uint32_t type, uint32_t error);
-
-/**
- * ttm_fence_driver_from_dev
- *
- * @fdev: The ttm fence device.
- *
- * Returns a pointer to the fence driver struct.
- */
-
-static inline const struct ttm_fence_driver *ttm_fence_driver_from_dev(
- struct ttm_fence_device *fdev)
-{
- return fdev->driver;
-}
-
-/**
- * ttm_fence_driver
- *
- * @fence: Pointer to a ttm fence object.
- *
- * Returns a pointer to the fence driver struct.
- */
-
-static inline const struct ttm_fence_driver *ttm_fence_driver(struct
- ttm_fence_object
- *fence)
-{
- return ttm_fence_driver_from_dev(fence->fdev);
-}
-
-/**
- * ttm_fence_fc
- *
- * @fence: Pointer to a ttm fence object.
- *
- * Returns a pointer to the struct ttm_fence_class_manager for the
- * fence class of @fence.
- */
-
-static inline struct ttm_fence_class_manager *ttm_fence_fc(struct
- ttm_fence_object
- *fence)
-{
- return &fence->fdev->fence_class[fence->fence_class];
-}
-
-#endif
diff --git a/drivers/staging/gma500/psb_ttm_fence_user.c b/drivers/staging/gma500/psb_ttm_fence_user.c
deleted file mode 100644
index 36f974f..0000000
--- a/drivers/staging/gma500/psb_ttm_fence_user.c
+++ /dev/null
@@ -1,237 +0,0 @@
-/**************************************************************************
- *
- * Copyright (c) 2006-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA
- * All Rights Reserved.
- * Copyright (c) 2009 VMware, Inc., Palo Alto, CA., USA
- * All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
- *
- **************************************************************************/
-/*
- * Authors: Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
- */
-
-#include <drm/drmP.h>
-#include "psb_ttm_fence_user.h"
-#include "ttm/ttm_object.h"
-#include "psb_ttm_fence_driver.h"
-#include "psb_ttm_userobj_api.h"
-
-/**
- * struct ttm_fence_user_object
- *
- * @base: The base object used for user-space visibility and refcounting.
- *
- * @fence: The fence object itself.
- *
- */
-
-struct ttm_fence_user_object {
- struct ttm_base_object base;
- struct ttm_fence_object fence;
-};
-
-static struct ttm_fence_user_object *ttm_fence_user_object_lookup(
- struct ttm_object_file *tfile,
- uint32_t handle)
-{
- struct ttm_base_object *base;
-
- base = ttm_base_object_lookup(tfile, handle);
- if (unlikely(base == NULL)) {
- printk(KERN_ERR "Invalid fence handle 0x%08lx\n",
- (unsigned long)handle);
- return NULL;
- }
-
- if (unlikely(base->object_type != ttm_fence_type)) {
- ttm_base_object_unref(&base);
- printk(KERN_ERR "Invalid fence handle 0x%08lx\n",
- (unsigned long)handle);
- return NULL;
- }
-
- return container_of(base, struct ttm_fence_user_object, base);
-}
-
-/*
- * The fence object destructor.
- */
-
-static void ttm_fence_user_destroy(struct ttm_fence_object *fence)
-{
- struct ttm_fence_user_object *ufence =
- container_of(fence, struct ttm_fence_user_object, fence);
-
- ttm_mem_global_free(fence->fdev->mem_glob, sizeof(*ufence));
- kfree(ufence);
-}
-
-/*
- * The base object destructor. We basically unly unreference the
- * attached fence object.
- */
-
-static void ttm_fence_user_release(struct ttm_base_object **p_base)
-{
- struct ttm_fence_user_object *ufence;
- struct ttm_base_object *base = *p_base;
- struct ttm_fence_object *fence;
-
- *p_base = NULL;
-
- if (unlikely(base == NULL))
- return;
-
- ufence = container_of(base, struct ttm_fence_user_object, base);
- fence = &ufence->fence;
- ttm_fence_object_unref(&fence);
-}
-
-int
-ttm_fence_user_create(struct ttm_fence_device *fdev,
- struct ttm_object_file *tfile,
- uint32_t fence_class,
- uint32_t fence_types,
- uint32_t create_flags,
- struct ttm_fence_object **fence,
- uint32_t *user_handle)
-{
- int ret;
- struct ttm_fence_object *tmp;
- struct ttm_fence_user_object *ufence;
-
- ret = ttm_mem_global_alloc(fdev->mem_glob,
- sizeof(*ufence),
- false,
- false);
- if (unlikely(ret != 0))
- return -ENOMEM;
-
- ufence = kmalloc(sizeof(*ufence), GFP_KERNEL);
- if (unlikely(ufence == NULL)) {
- ttm_mem_global_free(fdev->mem_glob, sizeof(*ufence));
- return -ENOMEM;
- }
-
- ret = ttm_fence_object_init(fdev,
- fence_class,
- fence_types, create_flags,
- &ttm_fence_user_destroy, &ufence->fence);
-
- if (unlikely(ret != 0))
- goto out_err0;
-
- /*
- * One fence ref is held by the fence ptr we return.
- * The other one by the base object. Need to up the
- * fence refcount before we publish this object to
- * user-space.
- */
-
- tmp = ttm_fence_object_ref(&ufence->fence);
- ret = ttm_base_object_init(tfile, &ufence->base,
- false, ttm_fence_type,
- &ttm_fence_user_release, NULL);
-
- if (unlikely(ret != 0))
- goto out_err1;
-
- *fence = &ufence->fence;
- *user_handle = ufence->base.hash.key;
-
- return 0;
-out_err1:
- ttm_fence_object_unref(&tmp);
- tmp = &ufence->fence;
- ttm_fence_object_unref(&tmp);
- return ret;
-out_err0:
- ttm_mem_global_free(fdev->mem_glob, sizeof(*ufence));
- kfree(ufence);
- return ret;
-}
-
-int ttm_fence_signaled_ioctl(struct ttm_object_file *tfile, void *data)
-{
- int ret;
- union ttm_fence_signaled_arg *arg = data;
- struct ttm_fence_object *fence;
- struct ttm_fence_info info;
- struct ttm_fence_user_object *ufence;
- struct ttm_base_object *base;
- ret = 0;
-
- ufence = ttm_fence_user_object_lookup(tfile, arg->req.handle);
- if (unlikely(ufence == NULL))
- return -EINVAL;
-
- fence = &ufence->fence;
-
- if (arg->req.flush) {
- ret = ttm_fence_object_flush(fence, arg->req.fence_type);
- if (unlikely(ret != 0))
- goto out;
- }
-
- info = ttm_fence_get_info(fence);
- arg->rep.signaled_types = info.signaled_types;
- arg->rep.fence_error = info.error;
-
-out:
- base = &ufence->base;
- ttm_base_object_unref(&base);
- return ret;
-}
-
-int ttm_fence_finish_ioctl(struct ttm_object_file *tfile, void *data)
-{
- int ret;
- union ttm_fence_finish_arg *arg = data;
- struct ttm_fence_user_object *ufence;
- struct ttm_base_object *base;
- struct ttm_fence_object *fence;
- ret = 0;
-
- ufence = ttm_fence_user_object_lookup(tfile, arg->req.handle);
- if (unlikely(ufence == NULL))
- return -EINVAL;
-
- fence = &ufence->fence;
-
- ret = ttm_fence_object_wait(fence,
- arg->req.mode & TTM_FENCE_FINISH_MODE_LAZY,
- true, arg->req.fence_type);
- if (likely(ret == 0)) {
- struct ttm_fence_info info = ttm_fence_get_info(fence);
-
- arg->rep.signaled_types = info.signaled_types;
- arg->rep.fence_error = info.error;
- }
-
- base = &ufence->base;
- ttm_base_object_unref(&base);
-
- return ret;
-}
-
-int ttm_fence_unref_ioctl(struct ttm_object_file *tfile, void *data)
-{
- struct ttm_fence_unref_arg *arg = data;
- int ret = 0;
-
- ret = ttm_ref_object_base_unref(tfile, arg->handle, ttm_fence_type);
- return ret;
-}
diff --git a/drivers/staging/gma500/psb_ttm_fence_user.h b/drivers/staging/gma500/psb_ttm_fence_user.h
deleted file mode 100644
index 762a057..0000000
--- a/drivers/staging/gma500/psb_ttm_fence_user.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/**************************************************************************
- *
- * Copyright 2006-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA
- * All Rights Reserved.
- * Copyright (c) 2009 VMware, Inc., Palo Alto, CA., USA
- * All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
- *
- **************************************************************************/
-/*
- * Authors
- * Thomas Hellström <thomas-at-tungstengraphics-dot-com>
- */
-
-#ifndef TTM_FENCE_USER_H
-#define TTM_FENCE_USER_H
-
-#if !defined(__KERNEL__) && !defined(_KERNEL)
-#include <stdint.h>
-#endif
-
-#define TTM_FENCE_MAJOR 0
-#define TTM_FENCE_MINOR 1
-#define TTM_FENCE_PL 0
-#define TTM_FENCE_DATE "080819"
-
-/**
- * struct ttm_fence_signaled_req
- *
- * @handle: Handle to the fence object. Input.
- *
- * @fence_type: Fence types we want to flush. Input.
- *
- * @flush: Boolean. Flush the indicated fence_types. Input.
- *
- * Argument to the TTM_FENCE_SIGNALED ioctl.
- */
-
-struct ttm_fence_signaled_req {
- uint32_t handle;
- uint32_t fence_type;
- int32_t flush;
- uint32_t pad64;
-};
-
-/**
- * struct ttm_fence_rep
- *
- * @signaled_types: Fence type that has signaled.
- *
- * @fence_error: Command execution error.
- * Hardware errors that are consequences of the execution
- * of the command stream preceding the fence are reported
- * here.
- *
- * Output argument to the TTM_FENCE_SIGNALED and
- * TTM_FENCE_FINISH ioctls.
- */
-
-struct ttm_fence_rep {
- uint32_t signaled_types;
- uint32_t fence_error;
-};
-
-union ttm_fence_signaled_arg {
- struct ttm_fence_signaled_req req;
- struct ttm_fence_rep rep;
-};
-
-/*
- * Waiting mode flags for the TTM_FENCE_FINISH ioctl.
- *
- * TTM_FENCE_FINISH_MODE_LAZY: Allow for sleeps during polling
- * wait.
- *
- * TTM_FENCE_FINISH_MODE_NO_BLOCK: Don't block waiting for GPU,
- * but return -EBUSY if the buffer is busy.
- */
-
-#define TTM_FENCE_FINISH_MODE_LAZY (1 << 0)
-#define TTM_FENCE_FINISH_MODE_NO_BLOCK (1 << 1)
-
-/**
- * struct ttm_fence_finish_req
- *
- * @handle: Handle to the fence object. Input.
- *
- * @fence_type: Fence types we want to finish.
- *
- * @mode: Wait mode.
- *
- * Input to the TTM_FENCE_FINISH ioctl.
- */
-
-struct ttm_fence_finish_req {
- uint32_t handle;
- uint32_t fence_type;
- uint32_t mode;
- uint32_t pad64;
-};
-
-union ttm_fence_finish_arg {
- struct ttm_fence_finish_req req;
- struct ttm_fence_rep rep;
-};
-
-/**
- * struct ttm_fence_unref_arg
- *
- * @handle: Handle to the fence object.
- *
- * Argument to the TTM_FENCE_UNREF ioctl.
- */
-
-struct ttm_fence_unref_arg {
- uint32_t handle;
- uint32_t pad64;
-};
-
-/*
- * Ioctl offsets from extenstion start.
- */
-
-#define TTM_FENCE_SIGNALED 0x01
-#define TTM_FENCE_FINISH 0x02
-#define TTM_FENCE_UNREF 0x03
-
-#endif
diff --git a/drivers/staging/gma500/psb_ttm_glue.c b/drivers/staging/gma500/psb_ttm_glue.c
deleted file mode 100644
index d1d965e..0000000
--- a/drivers/staging/gma500/psb_ttm_glue.c
+++ /dev/null
@@ -1,349 +0,0 @@
-/**************************************************************************
- * Copyright (c) 2008, Intel Corporation.
- * All Rights Reserved.
- * Copyright (c) 2008, Tungsten Graphics Inc. Cedar Park, TX., USA.
- * All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
- *
- **************************************************************************/
-
-
-#include <drm/drmP.h>
-#include "psb_drv.h"
-#include "psb_ttm_userobj_api.h"
-#include <linux/io.h>
-
-
-static struct vm_operations_struct psb_ttm_vm_ops;
-
-/**
- * NOTE: driver_private of drm_file is now a struct psb_file_data struct
- * pPriv in struct psb_file_data contains the original psb_fpriv;
- */
-int psb_open(struct inode *inode, struct file *filp)
-{
- struct drm_file *file_priv;
- struct drm_psb_private *dev_priv;
- struct psb_fpriv *psb_fp;
- struct psb_file_data *pvr_file_priv;
- int ret;
-
- DRM_DEBUG("\n");
-
- ret = drm_open(inode, filp);
- if (unlikely(ret))
- return ret;
-
- psb_fp = kzalloc(sizeof(*psb_fp), GFP_KERNEL);
-
- if (unlikely(psb_fp == NULL))
- goto out_err0;
-
- file_priv = (struct drm_file *) filp->private_data;
- dev_priv = psb_priv(file_priv->minor->dev);
-
- DRM_DEBUG("is_master %d\n", file_priv->is_master ? 1 : 0);
-
- psb_fp->tfile = ttm_object_file_init(dev_priv->tdev,
- PSB_FILE_OBJECT_HASH_ORDER);
- if (unlikely(psb_fp->tfile == NULL))
- goto out_err1;
-
- pvr_file_priv = (struct psb_file_data *)file_priv->driver_priv;
- if (!pvr_file_priv) {
- DRM_ERROR("drm file private is NULL\n");
- goto out_err1;
- }
-
- pvr_file_priv->priv = psb_fp;
- if (unlikely(dev_priv->bdev.dev_mapping == NULL))
- dev_priv->bdev.dev_mapping = dev_priv->dev->dev_mapping;
-
- return 0;
-
-out_err1:
- kfree(psb_fp);
-out_err0:
- (void) drm_release(inode, filp);
- return ret;
-}
-
-int psb_release(struct inode *inode, struct file *filp)
-{
- struct drm_file *file_priv;
- struct psb_fpriv *psb_fp;
- struct drm_psb_private *dev_priv;
- int ret;
- file_priv = (struct drm_file *) filp->private_data;
- psb_fp = psb_fpriv(file_priv);
- dev_priv = psb_priv(file_priv->minor->dev);
-
- ttm_object_file_release(&psb_fp->tfile);
- kfree(psb_fp);
-
- ret = drm_release(inode, filp);
-
- return ret;
-}
-
-int psb_fence_signaled_ioctl(struct drm_device *dev, void *data,
- struct drm_file *file_priv)
-{
-
- return ttm_fence_signaled_ioctl(psb_fpriv(file_priv)->tfile, data);
-}
-
-int psb_fence_finish_ioctl(struct drm_device *dev, void *data,
- struct drm_file *file_priv)
-{
- return ttm_fence_finish_ioctl(psb_fpriv(file_priv)->tfile, data);
-}
-
-int psb_fence_unref_ioctl(struct drm_device *dev, void *data,
- struct drm_file *file_priv)
-{
- return ttm_fence_unref_ioctl(psb_fpriv(file_priv)->tfile, data);
-}
-
-int psb_pl_waitidle_ioctl(struct drm_device *dev, void *data,
- struct drm_file *file_priv)
-{
- return ttm_pl_waitidle_ioctl(psb_fpriv(file_priv)->tfile, data);
-}
-
-int psb_pl_setstatus_ioctl(struct drm_device *dev, void *data,
- struct drm_file *file_priv)
-{
- return ttm_pl_setstatus_ioctl(psb_fpriv(file_priv)->tfile,
- &psb_priv(dev)->ttm_lock, data);
-
-}
-
-int psb_pl_synccpu_ioctl(struct drm_device *dev, void *data,
- struct drm_file *file_priv)
-{
- return ttm_pl_synccpu_ioctl(psb_fpriv(file_priv)->tfile, data);
-}
-
-int psb_pl_unref_ioctl(struct drm_device *dev, void *data,
- struct drm_file *file_priv)
-{
- return ttm_pl_unref_ioctl(psb_fpriv(file_priv)->tfile, data);
-
-}
-
-int psb_pl_reference_ioctl(struct drm_device *dev, void *data,
- struct drm_file *file_priv)
-{
- return ttm_pl_reference_ioctl(psb_fpriv(file_priv)->tfile, data);
-
-}
-
-int psb_pl_create_ioctl(struct drm_device *dev, void *data,
- struct drm_file *file_priv)
-{
- struct drm_psb_private *dev_priv = psb_priv(dev);
-
- return ttm_pl_create_ioctl(psb_fpriv(file_priv)->tfile,
- &dev_priv->bdev, &dev_priv->ttm_lock, data);
-
-}
-
-int psb_pl_ub_create_ioctl(struct drm_device *dev, void *data,
- struct drm_file *file_priv)
-{
- struct drm_psb_private *dev_priv = psb_priv(dev);
-
- return ttm_pl_ub_create_ioctl(psb_fpriv(file_priv)->tfile,
- &dev_priv->bdev, &dev_priv->ttm_lock, data);
-
-}
-/**
- * psb_ttm_fault - Wrapper around the ttm fault method.
- *
- * @vma: The struct vm_area_struct as in the vm fault() method.
- * @vmf: The struct vm_fault as in the vm fault() method.
- *
- * Since ttm_fault() will reserve buffers while faulting,
- * we need to take the ttm read lock around it, as this driver
- * relies on the ttm_lock in write mode to exclude all threads from
- * reserving and thus validating buffers in aperture- and memory shortage
- * situations.
- */
-
-static int psb_ttm_fault(struct vm_area_struct *vma,
- struct vm_fault *vmf)
-{
- struct ttm_buffer_object *bo = (struct ttm_buffer_object *)
- vma->vm_private_data;
- struct drm_psb_private *dev_priv =
- container_of(bo->bdev, struct drm_psb_private, bdev);
- int ret;
-
- ret = ttm_read_lock(&dev_priv->ttm_lock, true);
- if (unlikely(ret != 0))
- return VM_FAULT_NOPAGE;
-
- ret = dev_priv->ttm_vm_ops->fault(vma, vmf);
-
- ttm_read_unlock(&dev_priv->ttm_lock);
- return ret;
-}
-
-/**
- * if vm_pgoff < DRM_PSB_FILE_PAGE_OFFSET call directly to
- * PVRMMap
- */
-int psb_mmap(struct file *filp, struct vm_area_struct *vma)
-{
- struct drm_file *file_priv;
- struct drm_psb_private *dev_priv;
- int ret;
-
- if (vma->vm_pgoff < DRM_PSB_FILE_PAGE_OFFSET ||
- vma->vm_pgoff > 2 * DRM_PSB_FILE_PAGE_OFFSET)
-#if 0 /* FIXMEAC */
- return PVRMMap(filp, vma);
-#else
- return -EINVAL;
-#endif
-
- file_priv = (struct drm_file *) filp->private_data;
- dev_priv = psb_priv(file_priv->minor->dev);
-
- ret = ttm_bo_mmap(filp, vma, &dev_priv->bdev);
- if (unlikely(ret != 0))
- return ret;
-
- if (unlikely(dev_priv->ttm_vm_ops == NULL)) {
- dev_priv->ttm_vm_ops = (struct vm_operations_struct *)
- vma->vm_ops;
- psb_ttm_vm_ops = *vma->vm_ops;
- psb_ttm_vm_ops.fault = &psb_ttm_fault;
- }
-
- vma->vm_ops = &psb_ttm_vm_ops;
-
- return 0;
-}
-/*
-ssize_t psb_ttm_write(struct file *filp, const char __user *buf,
- size_t count, loff_t *f_pos)
-{
- struct drm_file *file_priv = (struct drm_file *)filp->private_data;
- struct drm_psb_private *dev_priv = psb_priv(file_priv->minor->dev);
-
- return ttm_bo_io(&dev_priv->bdev, filp, buf, NULL, count, f_pos, 1);
-}
-
-ssize_t psb_ttm_read(struct file *filp, char __user *buf,
- size_t count, loff_t *f_pos)
-{
- struct drm_file *file_priv = (struct drm_file *)filp->private_data;
- struct drm_psb_private *dev_priv = psb_priv(file_priv->minor->dev);
-
- return ttm_bo_io(&dev_priv->bdev, filp, NULL, buf, count, f_pos, 1);
-}
-*/
-int psb_verify_access(struct ttm_buffer_object *bo,
- struct file *filp)
-{
- struct drm_file *file_priv = (struct drm_file *)filp->private_data;
-
- if (capable(CAP_SYS_ADMIN))
- return 0;
-
- if (unlikely(!file_priv->authenticated))
- return -EPERM;
-
- return ttm_pl_verify_access(bo, psb_fpriv(file_priv)->tfile);
-}
-
-static int psb_ttm_mem_global_init(struct drm_global_reference *ref)
-{
- return ttm_mem_global_init(ref->object);
-}
-
-static void psb_ttm_mem_global_release(struct drm_global_reference *ref)
-{
- ttm_mem_global_release(ref->object);
-}
-
-int psb_ttm_global_init(struct drm_psb_private *dev_priv)
-{
- struct drm_global_reference *global_ref;
- int ret;
-
- global_ref = &dev_priv->mem_global_ref;
- global_ref->global_type = DRM_GLOBAL_TTM_MEM;
- global_ref->size = sizeof(struct ttm_mem_global);
- global_ref->init = &psb_ttm_mem_global_init;
- global_ref->release = &psb_ttm_mem_global_release;
-
- ret = drm_global_item_ref(global_ref);
- if (unlikely(ret != 0)) {
- DRM_ERROR("Failed referencing a global TTM memory object.\n");
- return ret;
- }
-
- dev_priv->bo_global_ref.mem_glob = dev_priv->mem_global_ref.object;
- global_ref = &dev_priv->bo_global_ref.ref;
- global_ref->global_type = DRM_GLOBAL_TTM_BO;
- global_ref->size = sizeof(struct ttm_bo_global);
- global_ref->init = &ttm_bo_global_init;
- global_ref->release = &ttm_bo_global_release;
- ret = drm_global_item_ref(global_ref);
- if (ret != 0) {
- DRM_ERROR("Failed setting up TTM BO subsystem.\n");
- drm_global_item_unref(global_ref);
- return ret;
- }
- return 0;
-}
-
-void psb_ttm_global_release(struct drm_psb_private *dev_priv)
-{
- drm_global_item_unref(&dev_priv->mem_global_ref);
-}
-
-int psb_getpageaddrs_ioctl(struct drm_device *dev, void *data,
- struct drm_file *file_priv)
-{
- struct drm_psb_getpageaddrs_arg *arg = data;
- struct ttm_buffer_object *bo;
- struct ttm_tt *ttm;
- struct page **tt_pages;
- unsigned long i, num_pages;
- unsigned long *p = arg->page_addrs;
- int ret = 0;
-
- bo = ttm_buffer_object_lookup(psb_fpriv(file_priv)->tfile,
- arg->handle);
- if (unlikely(bo == NULL)) {
- printk(KERN_ERR
- "Could not find buffer object for getpageaddrs.\n");
- return -EINVAL;
- }
-
- arg->gtt_offset = bo->offset;
- ttm = bo->ttm;
- num_pages = ttm->num_pages;
- tt_pages = ttm->pages;
-
- for (i = 0; i < num_pages; i++)
- p[i] = (unsigned long)page_to_phys(tt_pages[i]);
-
- return ret;
-}
diff --git a/drivers/staging/gma500/psb_ttm_placement_user.c b/drivers/staging/gma500/psb_ttm_placement_user.c
deleted file mode 100644
index 272b397..0000000
--- a/drivers/staging/gma500/psb_ttm_placement_user.c
+++ /dev/null
@@ -1,628 +0,0 @@
-/**************************************************************************
- *
- * Copyright (c) 2006-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA
- * All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
- *
- **************************************************************************/
-/*
- * Authors: Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
- */
-
-#include "psb_ttm_placement_user.h"
-#include "ttm/ttm_bo_driver.h"
-#include "ttm/ttm_object.h"
-#include "psb_ttm_userobj_api.h"
-#include "ttm/ttm_lock.h"
-#include <linux/slab.h>
-#include <linux/sched.h>
-
-struct ttm_bo_user_object {
- struct ttm_base_object base;
- struct ttm_buffer_object bo;
-};
-
-static size_t pl_bo_size;
-
-static uint32_t psb_busy_prios[] = {
- TTM_PL_TT,
- TTM_PL_PRIV0, /* CI */
- TTM_PL_PRIV2, /* RAR */
- TTM_PL_PRIV1, /* DRM_PSB_MEM_MMU */
- TTM_PL_SYSTEM
-};
-
-static const struct ttm_placement default_placement = {
- 0, 0, 0, NULL, 5, psb_busy_prios
-};
-
-static size_t ttm_pl_size(struct ttm_bo_device *bdev, unsigned long num_pages)
-{
- size_t page_array_size =
- (num_pages * sizeof(void *) + PAGE_SIZE - 1) & PAGE_MASK;
-
- if (unlikely(pl_bo_size == 0)) {
- pl_bo_size = bdev->glob->ttm_bo_extra_size +
- ttm_round_pot(sizeof(struct ttm_bo_user_object));
- }
-
- return bdev->glob->ttm_bo_size + 2 * page_array_size;
-}
-
-static struct ttm_bo_user_object *ttm_bo_user_lookup(struct ttm_object_file
- *tfile, uint32_t handle)
-{
- struct ttm_base_object *base;
-
- base = ttm_base_object_lookup(tfile, handle);
- if (unlikely(base == NULL)) {
- printk(KERN_ERR "Invalid buffer object handle 0x%08lx.\n",
- (unsigned long)handle);
- return NULL;
- }
-
- if (unlikely(base->object_type != ttm_buffer_type)) {
- ttm_base_object_unref(&base);
- printk(KERN_ERR "Invalid buffer object handle 0x%08lx.\n",
- (unsigned long)handle);
- return NULL;
- }
-
- return container_of(base, struct ttm_bo_user_object, base);
-}
-
-struct ttm_buffer_object *ttm_buffer_object_lookup(struct ttm_object_file
- *tfile, uint32_t handle)
-{
- struct ttm_bo_user_object *user_bo;
- struct ttm_base_object *base;
-
- user_bo = ttm_bo_user_lookup(tfile, handle);
- if (unlikely(user_bo == NULL))
- return NULL;
-
- (void)ttm_bo_reference(&user_bo->bo);
- base = &user_bo->base;
- ttm_base_object_unref(&base);
- return &user_bo->bo;
-}
-
-static void ttm_bo_user_destroy(struct ttm_buffer_object *bo)
-{
- struct ttm_bo_user_object *user_bo =
- container_of(bo, struct ttm_bo_user_object, bo);
-
- ttm_mem_global_free(bo->glob->mem_glob, bo->acc_size);
- kfree(user_bo);
-}
-
-static void ttm_bo_user_release(struct ttm_base_object **p_base)
-{
- struct ttm_bo_user_object *user_bo;
- struct ttm_base_object *base = *p_base;
- struct ttm_buffer_object *bo;
-
- *p_base = NULL;
-
- if (unlikely(base == NULL))
- return;
-
- user_bo = container_of(base, struct ttm_bo_user_object, base);
- bo = &user_bo->bo;
- ttm_bo_unref(&bo);
-}
-
-static void ttm_bo_user_ref_release(struct ttm_base_object *base,
- enum ttm_ref_type ref_type)
-{
- struct ttm_bo_user_object *user_bo =
- container_of(base, struct ttm_bo_user_object, base);
- struct ttm_buffer_object *bo = &user_bo->bo;
-
- switch (ref_type) {
- case TTM_REF_SYNCCPU_WRITE:
- ttm_bo_synccpu_write_release(bo);
- break;
- default:
- BUG();
- }
-}
-
-static void ttm_pl_fill_rep(struct ttm_buffer_object *bo,
- struct ttm_pl_rep *rep)
-{
- struct ttm_bo_user_object *user_bo =
- container_of(bo, struct ttm_bo_user_object, bo);
-
- rep->gpu_offset = bo->offset;
- rep->bo_size = bo->num_pages << PAGE_SHIFT;
- rep->map_handle = bo->addr_space_offset;
- rep->placement = bo->mem.placement;
- rep->handle = user_bo->base.hash.key;
- rep->sync_object_arg = (uint32_t) (unsigned long)bo->sync_obj_arg;
-}
-
-/* FIXME Copy from upstream TTM */
-static inline size_t ttm_bo_size(struct ttm_bo_global *glob,
- unsigned long num_pages)
-{
- size_t page_array_size = (num_pages * sizeof(void *) + PAGE_SIZE - 1) &
- PAGE_MASK;
-
- return glob->ttm_bo_size + 2 * page_array_size;
-}
-
-/* FIXME Copy from upstream TTM "ttm_bo_create", upstream TTM does not
- export this, so copy it here */
-static int ttm_bo_create_private(struct ttm_bo_device *bdev,
- unsigned long size,
- enum ttm_bo_type type,
- struct ttm_placement *placement,
- uint32_t page_alignment,
- unsigned long buffer_start,
- bool interruptible,
- struct file *persistant_swap_storage,
- struct ttm_buffer_object **p_bo)
-{
- struct ttm_buffer_object *bo;
- struct ttm_mem_global *mem_glob = bdev->glob->mem_glob;
- int ret;
-
- size_t acc_size =
- ttm_bo_size(bdev->glob, (size + PAGE_SIZE - 1) >> PAGE_SHIFT);
- ret = ttm_mem_global_alloc(mem_glob, acc_size, false, false);
- if (unlikely(ret != 0))
- return ret;
-
- bo = kzalloc(sizeof(*bo), GFP_KERNEL);
-
- if (unlikely(bo == NULL)) {
- ttm_mem_global_free(mem_glob, acc_size);
- return -ENOMEM;
- }
-
- ret = ttm_bo_init(bdev, bo, size, type, placement, page_alignment,
- buffer_start, interruptible,
- persistant_swap_storage, acc_size, NULL);
- if (likely(ret == 0))
- *p_bo = bo;
-
- return ret;
-}
-
-int psb_ttm_bo_check_placement(struct ttm_buffer_object *bo,
- struct ttm_placement *placement)
-{
- int i;
-
- for (i = 0; i < placement->num_placement; i++) {
- if (!capable(CAP_SYS_ADMIN)) {
- if (placement->placement[i] & TTM_PL_FLAG_NO_EVICT) {
- printk(KERN_ERR TTM_PFX "Need to be root to "
- "modify NO_EVICT status.\n");
- return -EINVAL;
- }
- }
- }
- for (i = 0; i < placement->num_busy_placement; i++) {
- if (!capable(CAP_SYS_ADMIN)) {
- if (placement->busy_placement[i]
- & TTM_PL_FLAG_NO_EVICT) {
- printk(KERN_ERR TTM_PFX "Need to be root to modify NO_EVICT status.\n");
- return -EINVAL;
- }
- }
- }
- return 0;
-}
-
-int ttm_buffer_object_create(struct ttm_bo_device *bdev,
- unsigned long size,
- enum ttm_bo_type type,
- uint32_t flags,
- uint32_t page_alignment,
- unsigned long buffer_start,
- bool interruptible,
- struct file *persistant_swap_storage,
- struct ttm_buffer_object **p_bo)
-{
- struct ttm_placement placement = default_placement;
- int ret;
-
- if ((flags & TTM_PL_MASK_CACHING) == 0)
- flags |= TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED;
-
- placement.num_placement = 1;
- placement.placement = &flags;
-
- ret = ttm_bo_create_private(bdev,
- size,
- type,
- &placement,
- page_alignment,
- buffer_start,
- interruptible,
- persistant_swap_storage,
- p_bo);
-
- return ret;
-}
-
-
-int ttm_pl_create_ioctl(struct ttm_object_file *tfile,
- struct ttm_bo_device *bdev,
- struct ttm_lock *lock, void *data)
-{
- union ttm_pl_create_arg *arg = data;
- struct ttm_pl_create_req *req = &arg->req;
- struct ttm_pl_rep *rep = &arg->rep;
- struct ttm_buffer_object *bo;
- struct ttm_buffer_object *tmp;
- struct ttm_bo_user_object *user_bo;
- uint32_t flags;
- int ret = 0;
- struct ttm_mem_global *mem_glob = bdev->glob->mem_glob;
- struct ttm_placement placement = default_placement;
- size_t acc_size =
- ttm_pl_size(bdev, (req->size + PAGE_SIZE - 1) >> PAGE_SHIFT);
- ret = ttm_mem_global_alloc(mem_glob, acc_size, false, false);
- if (unlikely(ret != 0))
- return ret;
-
- flags = req->placement;
- user_bo = kzalloc(sizeof(*user_bo), GFP_KERNEL);
- if (unlikely(user_bo == NULL)) {
- ttm_mem_global_free(mem_glob, acc_size);
- return -ENOMEM;
- }
-
- bo = &user_bo->bo;
- ret = ttm_read_lock(lock, true);
- if (unlikely(ret != 0)) {
- ttm_mem_global_free(mem_glob, acc_size);
- kfree(user_bo);
- return ret;
- }
-
- placement.num_placement = 1;
- placement.placement = &flags;
-
- if ((flags & TTM_PL_MASK_CACHING) == 0)
- flags |= TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED;
-
- ret = ttm_bo_init(bdev, bo, req->size,
- ttm_bo_type_device, &placement,
- req->page_alignment, 0, true,
- NULL, acc_size, &ttm_bo_user_destroy);
- ttm_read_unlock(lock);
-
- /*
- * Note that the ttm_buffer_object_init function
- * would've called the destroy function on failure!!
- */
-
- if (unlikely(ret != 0))
- goto out;
-
- tmp = ttm_bo_reference(bo);
- ret = ttm_base_object_init(tfile, &user_bo->base,
- flags & TTM_PL_FLAG_SHARED,
- ttm_buffer_type,
- &ttm_bo_user_release,
- &ttm_bo_user_ref_release);
- if (unlikely(ret != 0))
- goto out_err;
-
- ttm_pl_fill_rep(bo, rep);
- ttm_bo_unref(&bo);
-out:
- return 0;
-out_err:
- ttm_bo_unref(&tmp);
- ttm_bo_unref(&bo);
- return ret;
-}
-
-int ttm_pl_ub_create_ioctl(struct ttm_object_file *tfile,
- struct ttm_bo_device *bdev,
- struct ttm_lock *lock, void *data)
-{
- union ttm_pl_create_ub_arg *arg = data;
- struct ttm_pl_create_ub_req *req = &arg->req;
- struct ttm_pl_rep *rep = &arg->rep;
- struct ttm_buffer_object *bo;
- struct ttm_buffer_object *tmp;
- struct ttm_bo_user_object *user_bo;
- uint32_t flags;
- int ret = 0;
- struct ttm_mem_global *mem_glob = bdev->glob->mem_glob;
- struct ttm_placement placement = default_placement;
- size_t acc_size =
- ttm_pl_size(bdev, (req->size + PAGE_SIZE - 1) >> PAGE_SHIFT);
- ret = ttm_mem_global_alloc(mem_glob, acc_size, false, false);
- if (unlikely(ret != 0))
- return ret;
-
- flags = req->placement;
- user_bo = kzalloc(sizeof(*user_bo), GFP_KERNEL);
- if (unlikely(user_bo == NULL)) {
- ttm_mem_global_free(mem_glob, acc_size);
- return -ENOMEM;
- }
- ret = ttm_read_lock(lock, true);
- if (unlikely(ret != 0)) {
- ttm_mem_global_free(mem_glob, acc_size);
- kfree(user_bo);
- return ret;
- }
- bo = &user_bo->bo;
-
- placement.num_placement = 1;
- placement.placement = &flags;
-
- ret = ttm_bo_init(bdev,
- bo,
- req->size,
- ttm_bo_type_user,
- &placement,
- req->page_alignment,
- req->user_address,
- true,
- NULL,
- acc_size,
- &ttm_bo_user_destroy);
-
- /*
- * Note that the ttm_buffer_object_init function
- * would've called the destroy function on failure!!
- */
- ttm_read_unlock(lock);
- if (unlikely(ret != 0))
- goto out;
-
- tmp = ttm_bo_reference(bo);
- ret = ttm_base_object_init(tfile, &user_bo->base,
- flags & TTM_PL_FLAG_SHARED,
- ttm_buffer_type,
- &ttm_bo_user_release,
- &ttm_bo_user_ref_release);
- if (unlikely(ret != 0))
- goto out_err;
-
- ttm_pl_fill_rep(bo, rep);
- ttm_bo_unref(&bo);
-out:
- return 0;
-out_err:
- ttm_bo_unref(&tmp);
- ttm_bo_unref(&bo);
- return ret;
-}
-
-int ttm_pl_reference_ioctl(struct ttm_object_file *tfile, void *data)
-{
- union ttm_pl_reference_arg *arg = data;
- struct ttm_pl_rep *rep = &arg->rep;
- struct ttm_bo_user_object *user_bo;
- struct ttm_buffer_object *bo;
- struct ttm_base_object *base;
- int ret;
-
- user_bo = ttm_bo_user_lookup(tfile, arg->req.handle);
- if (unlikely(user_bo == NULL)) {
- printk(KERN_ERR "Could not reference buffer object.\n");
- return -EINVAL;
- }
-
- bo = &user_bo->bo;
- ret = ttm_ref_object_add(tfile, &user_bo->base, TTM_REF_USAGE, NULL);
- if (unlikely(ret != 0)) {
- printk(KERN_ERR
- "Could not add a reference to buffer object.\n");
- goto out;
- }
-
- ttm_pl_fill_rep(bo, rep);
-
-out:
- base = &user_bo->base;
- ttm_base_object_unref(&base);
- return ret;
-}
-
-int ttm_pl_unref_ioctl(struct ttm_object_file *tfile, void *data)
-{
- struct ttm_pl_reference_req *arg = data;
-
- return ttm_ref_object_base_unref(tfile, arg->handle, TTM_REF_USAGE);
-}
-
-int ttm_pl_synccpu_ioctl(struct ttm_object_file *tfile, void *data)
-{
- struct ttm_pl_synccpu_arg *arg = data;
- struct ttm_bo_user_object *user_bo;
- struct ttm_buffer_object *bo;
- struct ttm_base_object *base;
- bool existed;
- int ret;
-
- switch (arg->op) {
- case TTM_PL_SYNCCPU_OP_GRAB:
- user_bo = ttm_bo_user_lookup(tfile, arg->handle);
- if (unlikely(user_bo == NULL)) {
- printk(KERN_ERR
- "Could not find buffer object for synccpu.\n");
- return -EINVAL;
- }
- bo = &user_bo->bo;
- base = &user_bo->base;
- ret = ttm_bo_synccpu_write_grab(bo,
- arg->access_mode &
- TTM_PL_SYNCCPU_MODE_NO_BLOCK);
- if (unlikely(ret != 0)) {
- ttm_base_object_unref(&base);
- goto out;
- }
- ret = ttm_ref_object_add(tfile, &user_bo->base,
- TTM_REF_SYNCCPU_WRITE, &existed);
- if (existed || ret != 0)
- ttm_bo_synccpu_write_release(bo);
- ttm_base_object_unref(&base);
- break;
- case TTM_PL_SYNCCPU_OP_RELEASE:
- ret = ttm_ref_object_base_unref(tfile, arg->handle,
- TTM_REF_SYNCCPU_WRITE);
- break;
- default:
- ret = -EINVAL;
- break;
- }
-out:
- return ret;
-}
-
-int ttm_pl_setstatus_ioctl(struct ttm_object_file *tfile,
- struct ttm_lock *lock, void *data)
-{
- union ttm_pl_setstatus_arg *arg = data;
- struct ttm_pl_setstatus_req *req = &arg->req;
- struct ttm_pl_rep *rep = &arg->rep;
- struct ttm_buffer_object *bo;
- struct ttm_bo_device *bdev;
- struct ttm_placement placement = default_placement;
- uint32_t flags[2];
- int ret;
-
- bo = ttm_buffer_object_lookup(tfile, req->handle);
- if (unlikely(bo == NULL)) {
- printk(KERN_ERR
- "Could not find buffer object for setstatus.\n");
- return -EINVAL;
- }
-
- bdev = bo->bdev;
-
- ret = ttm_read_lock(lock, true);
- if (unlikely(ret != 0))
- goto out_err0;
-
- ret = ttm_bo_reserve(bo, true, false, false, 0);
- if (unlikely(ret != 0))
- goto out_err1;
-
- ret = ttm_bo_wait_cpu(bo, false);
- if (unlikely(ret != 0))
- goto out_err2;
-
- flags[0] = req->set_placement;
- flags[1] = req->clr_placement;
-
- placement.num_placement = 2;
- placement.placement = flags;
-
- /* Review internal locking ? FIXMEAC */
- ret = psb_ttm_bo_check_placement(bo, &placement);
- if (unlikely(ret != 0))
- goto out_err2;
-
- placement.num_placement = 1;
- flags[0] = (req->set_placement | bo->mem.placement)
- & ~req->clr_placement;
-
- ret = ttm_bo_validate(bo, &placement, true, false, false);
- if (unlikely(ret != 0))
- goto out_err2;
-
- ttm_pl_fill_rep(bo, rep);
-out_err2:
- ttm_bo_unreserve(bo);
-out_err1:
- ttm_read_unlock(lock);
-out_err0:
- ttm_bo_unref(&bo);
- return ret;
-}
-
-static int psb_ttm_bo_block_reservation(struct ttm_buffer_object *bo,
- bool interruptible, bool no_wait)
-{
- int ret;
-
- while (unlikely(atomic_cmpxchg(&bo->reserved, 0, 1) != 0)) {
- if (no_wait)
- return -EBUSY;
- else if (interruptible) {
- ret = wait_event_interruptible(bo->event_queue,
- atomic_read(&bo->reserved) == 0);
- if (unlikely(ret != 0))
- return -ERESTART;
- } else {
- wait_event(bo->event_queue,
- atomic_read(&bo->reserved) == 0);
- }
- }
- return 0;
-}
-
-static void psb_ttm_bo_unblock_reservation(struct ttm_buffer_object *bo)
-{
- atomic_set(&bo->reserved, 0);
- wake_up_all(&bo->event_queue);
-}
-
-int ttm_pl_waitidle_ioctl(struct ttm_object_file *tfile, void *data)
-{
- struct ttm_pl_waitidle_arg *arg = data;
- struct ttm_buffer_object *bo;
- int ret;
-
- bo = ttm_buffer_object_lookup(tfile, arg->handle);
- if (unlikely(bo == NULL)) {
- printk(KERN_ERR "Could not find buffer object for waitidle.\n");
- return -EINVAL;
- }
-
- ret =
- psb_ttm_bo_block_reservation(bo, true,
- arg->mode & TTM_PL_WAITIDLE_MODE_NO_BLOCK);
- if (unlikely(ret != 0))
- goto out;
- ret = ttm_bo_wait(bo,
- arg->mode & TTM_PL_WAITIDLE_MODE_LAZY,
- true, arg->mode & TTM_PL_WAITIDLE_MODE_NO_BLOCK);
- psb_ttm_bo_unblock_reservation(bo);
-out:
- ttm_bo_unref(&bo);
- return ret;
-}
-
-int ttm_pl_verify_access(struct ttm_buffer_object *bo,
- struct ttm_object_file *tfile)
-{
- struct ttm_bo_user_object *ubo;
-
- /*
- * Check bo subclass.
- */
-
- if (unlikely(bo->destroy != &ttm_bo_user_destroy))
- return -EPERM;
-
- ubo = container_of(bo, struct ttm_bo_user_object, bo);
- if (likely(ubo->base.shareable || ubo->base.tfile == tfile))
- return 0;
-
- return -EPERM;
-}
diff --git a/drivers/staging/gma500/psb_ttm_placement_user.h b/drivers/staging/gma500/psb_ttm_placement_user.h
deleted file mode 100644
index 8b7068b..0000000
--- a/drivers/staging/gma500/psb_ttm_placement_user.h
+++ /dev/null
@@ -1,252 +0,0 @@
-/**************************************************************************
- *
- * Copyright 2006-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA
- * All Rights Reserved.
- * Copyright (c) 2009 VMware, Inc., Palo Alto, CA., USA
- * All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
- *
- **************************************************************************/
-/*
- * Authors
- * Thomas Hellström <thomas-at-tungstengraphics-dot-com>
- */
-
-#ifndef _TTM_PLACEMENT_USER_H_
-#define _TTM_PLACEMENT_USER_H_
-
-#if !defined(__KERNEL__) && !defined(_KERNEL)
-#include <stdint.h>
-#else
-#include <linux/kernel.h>
-#endif
-
-#include "ttm/ttm_placement.h"
-
-#define TTM_PLACEMENT_MAJOR 0
-#define TTM_PLACEMENT_MINOR 1
-#define TTM_PLACEMENT_PL 0
-#define TTM_PLACEMENT_DATE "080819"
-
-/**
- * struct ttm_pl_create_req
- *
- * @size: The buffer object size.
- * @placement: Flags that indicate initial acceptable
- * placement.
- * @page_alignment: Required alignment in pages.
- *
- * Input to the TTM_BO_CREATE ioctl.
- */
-
-struct ttm_pl_create_req {
- uint64_t size;
- uint32_t placement;
- uint32_t page_alignment;
-};
-
-/**
- * struct ttm_pl_create_ub_req
- *
- * @size: The buffer object size.
- * @user_address: User-space address of the memory area that
- * should be used to back the buffer object cast to 64-bit.
- * @placement: Flags that indicate initial acceptable
- * placement.
- * @page_alignment: Required alignment in pages.
- *
- * Input to the TTM_BO_CREATE_UB ioctl.
- */
-
-struct ttm_pl_create_ub_req {
- uint64_t size;
- uint64_t user_address;
- uint32_t placement;
- uint32_t page_alignment;
-};
-
-/**
- * struct ttm_pl_rep
- *
- * @gpu_offset: The current offset into the memory region used.
- * This can be used directly by the GPU if there are no
- * additional GPU mapping procedures used by the driver.
- *
- * @bo_size: Actual buffer object size.
- *
- * @map_handle: Offset into the device address space.
- * Used for map, seek, read, write. This will never change
- * during the lifetime of an object.
- *
- * @placement: Flag indicating the placement status of
- * the buffer object using the TTM_PL flags above.
- *
- * @sync_object_arg: Used for user-space synchronization and
- * depends on the synchronization model used. If fences are
- * used, this is the buffer_object::fence_type_mask
- *
- * Output from the TTM_PL_CREATE and TTM_PL_REFERENCE, and
- * TTM_PL_SETSTATUS ioctls.
- */
-
-struct ttm_pl_rep {
- uint64_t gpu_offset;
- uint64_t bo_size;
- uint64_t map_handle;
- uint32_t placement;
- uint32_t handle;
- uint32_t sync_object_arg;
- uint32_t pad64;
-};
-
-/**
- * struct ttm_pl_setstatus_req
- *
- * @set_placement: Placement flags to set.
- *
- * @clr_placement: Placement flags to clear.
- *
- * @handle: The object handle
- *
- * Input to the TTM_PL_SETSTATUS ioctl.
- */
-
-struct ttm_pl_setstatus_req {
- uint32_t set_placement;
- uint32_t clr_placement;
- uint32_t handle;
- uint32_t pad64;
-};
-
-/**
- * struct ttm_pl_reference_req
- *
- * @handle: The object to put a reference on.
- *
- * Input to the TTM_PL_REFERENCE and the TTM_PL_UNREFERENCE ioctls.
- */
-
-struct ttm_pl_reference_req {
- uint32_t handle;
- uint32_t pad64;
-};
-
-/*
- * ACCESS mode flags for SYNCCPU.
- *
- * TTM_SYNCCPU_MODE_READ will guarantee that the GPU is not
- * writing to the buffer.
- *
- * TTM_SYNCCPU_MODE_WRITE will guarantee that the GPU is not
- * accessing the buffer.
- *
- * TTM_SYNCCPU_MODE_NO_BLOCK makes sure the call does not wait
- * for GPU accesses to finish but return -EBUSY.
- *
- * TTM_SYNCCPU_MODE_TRYCACHED Try to place the buffer in cacheable
- * memory while synchronized for CPU.
- */
-
-#define TTM_PL_SYNCCPU_MODE_READ TTM_ACCESS_READ
-#define TTM_PL_SYNCCPU_MODE_WRITE TTM_ACCESS_WRITE
-#define TTM_PL_SYNCCPU_MODE_NO_BLOCK (1 << 2)
-#define TTM_PL_SYNCCPU_MODE_TRYCACHED (1 << 3)
-
-/**
- * struct ttm_pl_synccpu_arg
- *
- * @handle: The object to synchronize.
- *
- * @access_mode: access mode indicated by the
- * TTM_SYNCCPU_MODE flags.
- *
- * @op: indicates whether to grab or release the
- * buffer for cpu usage.
- *
- * Input to the TTM_PL_SYNCCPU ioctl.
- */
-
-struct ttm_pl_synccpu_arg {
- uint32_t handle;
- uint32_t access_mode;
- enum {
- TTM_PL_SYNCCPU_OP_GRAB,
- TTM_PL_SYNCCPU_OP_RELEASE
- } op;
- uint32_t pad64;
-};
-
-/*
- * Waiting mode flags for the TTM_BO_WAITIDLE ioctl.
- *
- * TTM_WAITIDLE_MODE_LAZY: Allow for sleeps during polling
- * wait.
- *
- * TTM_WAITIDLE_MODE_NO_BLOCK: Don't block waiting for GPU,
- * but return -EBUSY if the buffer is busy.
- */
-
-#define TTM_PL_WAITIDLE_MODE_LAZY (1 << 0)
-#define TTM_PL_WAITIDLE_MODE_NO_BLOCK (1 << 1)
-
-/**
- * struct ttm_waitidle_arg
- *
- * @handle: The object to synchronize.
- *
- * @mode: wait mode indicated by the
- * TTM_SYNCCPU_MODE flags.
- *
- * Argument to the TTM_BO_WAITIDLE ioctl.
- */
-
-struct ttm_pl_waitidle_arg {
- uint32_t handle;
- uint32_t mode;
-};
-
-union ttm_pl_create_arg {
- struct ttm_pl_create_req req;
- struct ttm_pl_rep rep;
-};
-
-union ttm_pl_reference_arg {
- struct ttm_pl_reference_req req;
- struct ttm_pl_rep rep;
-};
-
-union ttm_pl_setstatus_arg {
- struct ttm_pl_setstatus_req req;
- struct ttm_pl_rep rep;
-};
-
-union ttm_pl_create_ub_arg {
- struct ttm_pl_create_ub_req req;
- struct ttm_pl_rep rep;
-};
-
-/*
- * Ioctl offsets.
- */
-
-#define TTM_PL_CREATE 0x00
-#define TTM_PL_REFERENCE 0x01
-#define TTM_PL_UNREF 0x02
-#define TTM_PL_SYNCCPU 0x03
-#define TTM_PL_WAITIDLE 0x04
-#define TTM_PL_SETSTATUS 0x05
-#define TTM_PL_CREATE_UB 0x06
-
-#endif
diff --git a/drivers/staging/gma500/psb_ttm_userobj_api.h b/drivers/staging/gma500/psb_ttm_userobj_api.h
deleted file mode 100644
index 6a8f7c4..0000000
--- a/drivers/staging/gma500/psb_ttm_userobj_api.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/**************************************************************************
- *
- * Copyright (c) 2006-2008 Tungsten Graphics, Inc., Cedar Park, TX., USA
- * All Rights Reserved.
- * Copyright (c) 2009 VMware, Inc., Palo Alto, CA., USA
- * All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
- *
- **************************************************************************/
-/*
- * Authors: Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
- */
-
-#ifndef _TTM_USEROBJ_API_H_
-#define _TTM_USEROBJ_API_H_
-
-#include "psb_ttm_placement_user.h"
-#include "psb_ttm_fence_user.h"
-#include "ttm/ttm_object.h"
-#include "psb_ttm_fence_api.h"
-#include "ttm/ttm_bo_api.h"
-
-struct ttm_lock;
-
-/*
- * User ioctls.
- */
-
-extern int ttm_pl_create_ioctl(struct ttm_object_file *tfile,
- struct ttm_bo_device *bdev,
- struct ttm_lock *lock, void *data);
-extern int ttm_pl_ub_create_ioctl(struct ttm_object_file *tfile,
- struct ttm_bo_device *bdev,
- struct ttm_lock *lock, void *data);
-extern int ttm_pl_reference_ioctl(struct ttm_object_file *tfile, void *data);
-extern int ttm_pl_unref_ioctl(struct ttm_object_file *tfile, void *data);
-extern int ttm_pl_synccpu_ioctl(struct ttm_object_file *tfile, void *data);
-extern int ttm_pl_setstatus_ioctl(struct ttm_object_file *tfile,
- struct ttm_lock *lock, void *data);
-extern int ttm_pl_waitidle_ioctl(struct ttm_object_file *tfile, void *data);
-extern int ttm_fence_signaled_ioctl(struct ttm_object_file *tfile, void *data);
-extern int ttm_fence_finish_ioctl(struct ttm_object_file *tfile, void *data);
-extern int ttm_fence_unref_ioctl(struct ttm_object_file *tfile, void *data);
-
-extern int
-ttm_fence_user_create(struct ttm_fence_device *fdev,
- struct ttm_object_file *tfile,
- uint32_t fence_class,
- uint32_t fence_types,
- uint32_t create_flags,
- struct ttm_fence_object **fence, uint32_t * user_handle);
-
-extern struct ttm_buffer_object *ttm_buffer_object_lookup(struct ttm_object_file
- *tfile,
- uint32_t handle);
-
-extern int
-ttm_pl_verify_access(struct ttm_buffer_object *bo,
- struct ttm_object_file *tfile);
-
-extern int ttm_buffer_object_create(struct ttm_bo_device *bdev,
- unsigned long size,
- enum ttm_bo_type type,
- uint32_t flags,
- uint32_t page_alignment,
- unsigned long buffer_start,
- bool interruptible,
- struct file *persistant_swap_storage,
- struct ttm_buffer_object **p_bo);
-
-extern int psb_ttm_bo_check_placement(struct ttm_buffer_object *bo,
- struct ttm_placement *placement);
-#endif
diff --git a/drivers/staging/hv/Kconfig b/drivers/staging/hv/Kconfig
index d41f380..5e0c9f6 100644
--- a/drivers/staging/hv/Kconfig
+++ b/drivers/staging/hv/Kconfig
@@ -1,6 +1,6 @@
config HYPERV
tristate "Microsoft Hyper-V client drivers"
- depends on X86 && m
+ depends on X86 && ACPI && PCI && m
default n
help
Select this option to run Linux as a Hyper-V client operating
@@ -31,7 +31,7 @@
config HYPERV_UTILS
tristate "Microsoft Hyper-V Utilities driver"
- depends on CONNECTOR
+ depends on CONNECTOR && NLS
default HYPERV
help
Select this option to enable the Hyper-V Utilities.
diff --git a/drivers/staging/hv/Makefile b/drivers/staging/hv/Makefile
index abeb2f7..3004674 100644
--- a/drivers/staging/hv/Makefile
+++ b/drivers/staging/hv/Makefile
@@ -9,6 +9,6 @@
hv.o connection.o channel.o \
channel_mgmt.o ring_buffer.o
hv_storvsc-y := storvsc_drv.o storvsc.o
-hv_blkvsc-y := blkvsc_drv.o blkvsc.o
+hv_blkvsc-y := blkvsc_drv.o storvsc.o
hv_netvsc-y := netvsc_drv.o netvsc.o rndis_filter.o
hv_utils-y := hv_util.o hv_kvp.o
diff --git a/drivers/staging/hv/blkvsc.c b/drivers/staging/hv/blkvsc.c
deleted file mode 100644
index 7c8729b..0000000
--- a/drivers/staging/hv/blkvsc.c
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- *
- * Copyright (c) 2009, Microsoft Corporation.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
- * Place - Suite 330, Boston, MA 02111-1307 USA.
- *
- * Authors:
- * Haiyang Zhang <haiyangz@microsoft.com>
- * Hank Janssen <hjanssen@microsoft.com>
- *
- */
-#include <linux/kernel.h>
-#include <linux/mm.h>
-#include "hv_api.h"
-#include "storvsc.c"
-
-static const char *g_blk_driver_name = "blkvsc";
-
-/* {32412632-86cb-44a2-9b5c-50d1417354f5} */
-static const struct hv_guid g_blk_device_type = {
- .data = {
- 0x32, 0x26, 0x41, 0x32, 0xcb, 0x86, 0xa2, 0x44,
- 0x9b, 0x5c, 0x50, 0xd1, 0x41, 0x73, 0x54, 0xf5
- }
-};
-
-static int blk_vsc_on_device_add(struct hv_device *device, void *additional_info)
-{
- struct storvsc_device_info *device_info;
- int ret = 0;
-
- device_info = (struct storvsc_device_info *)additional_info;
-
- ret = stor_vsc_on_device_add(device, additional_info);
- if (ret != 0)
- return ret;
-
- /*
- * We need to use the device instance guid to set the path and target
- * id. For IDE devices, the device instance id is formatted as
- * <bus id> * - <device id> - 8899 - 000000000000.
- */
- device_info->path_id = device->dev_instance.data[3] << 24 |
- device->dev_instance.data[2] << 16 |
- device->dev_instance.data[1] << 8 |
- device->dev_instance.data[0];
-
- device_info->target_id = device->dev_instance.data[5] << 8 |
- device->dev_instance.data[4];
-
- return ret;
-}
-
-int blk_vsc_initialize(struct hv_driver *driver)
-{
- struct storvsc_driver_object *stor_driver;
- int ret = 0;
-
- stor_driver = (struct storvsc_driver_object *)driver;
-
- /* Make sure we are at least 2 pages since 1 page is used for control */
- /* ASSERT(stor_driver->RingBufferSize >= (PAGE_SIZE << 1)); */
-
- driver->name = g_blk_driver_name;
- memcpy(&driver->dev_type, &g_blk_device_type, sizeof(struct hv_guid));
-
- stor_driver->request_ext_size = sizeof(struct storvsc_request_extension);
-
- /*
- * Divide the ring buffer data size (which is 1 page less than the ring
- * buffer size since that page is reserved for the ring buffer indices)
- * by the max request size (which is
- * vmbus_channel_packet_multipage_buffer + struct vstor_packet + u64)
- */
- stor_driver->max_outstanding_req_per_channel =
- ((stor_driver->ring_buffer_size - PAGE_SIZE) /
- ALIGN(MAX_MULTIPAGE_BUFFER_PACKET +
- sizeof(struct vstor_packet) + sizeof(u64),
- sizeof(u64)));
-
- DPRINT_INFO(BLKVSC, "max io outstd %u",
- stor_driver->max_outstanding_req_per_channel);
-
- /* Setup the dispatch table */
- stor_driver->base.dev_add = blk_vsc_on_device_add;
- stor_driver->base.dev_rm = stor_vsc_on_device_remove;
- stor_driver->base.cleanup = stor_vsc_on_cleanup;
- stor_driver->on_io_request = stor_vsc_on_io_request;
-
- return ret;
-}
diff --git a/drivers/staging/hv/blkvsc_drv.c b/drivers/staging/hv/blkvsc_drv.c
index 68ad17d..46daade 100644
--- a/drivers/staging/hv/blkvsc_drv.c
+++ b/drivers/staging/hv/blkvsc_drv.c
@@ -17,6 +17,7 @@
* Authors:
* Haiyang Zhang <haiyangz@microsoft.com>
* Hank Janssen <hjanssen@microsoft.com>
+ * K. Y. Srinivasan <kys@microsoft.com>
*/
#include <linux/init.h>
#include <linux/module.h>
@@ -25,17 +26,14 @@
#include <linux/major.h>
#include <linux/delay.h>
#include <linux/hdreg.h>
-#include <linux/mutex.h>
#include <linux/slab.h>
#include <scsi/scsi.h>
#include <scsi/scsi_cmnd.h>
#include <scsi/scsi_eh.h>
#include <scsi/scsi_dbg.h>
-#include "hv_api.h"
-#include "logging.h"
-#include "version_info.h"
-#include "vmbus.h"
-#include "storvsc_api.h"
+
+#include "hyperv.h"
+#include "hyperv_storage.h"
#define BLKVSC_MINORS 64
@@ -46,6 +44,12 @@
DVD_TYPE,
};
+enum blkvsc_op_type {
+ DO_INQUIRY,
+ DO_CAPACITY,
+ DO_FLUSH,
+};
+
/*
* This request ties the struct request and struct
* blkvsc_request/hv_storvsc_request together A struct request may be
@@ -72,9 +76,6 @@
/* The group this request is part of. Maybe null */
struct blkvsc_request_group *group;
- wait_queue_head_t wevent;
- int cond;
-
int write;
sector_t sector_start;
unsigned long sector_count;
@@ -84,12 +85,6 @@
unsigned char cmnd[MAX_COMMAND_SIZE];
struct hv_storvsc_request request;
- /*
- * !!!DO NOT ADD ANYTHING BELOW HERE!!! Otherwise, memory can overlap,
- * because - The extension buffer falls right here and is pointed to by
- * request.Extension;
- * Which sounds like a horrible idea, who designed this?
- */
};
/* Per device structure */
@@ -106,7 +101,6 @@
unsigned int device_id_len;
int num_outstanding_reqs;
int shutting_down;
- int media_not_present;
unsigned int sector_size;
sector_t capacity;
unsigned int port;
@@ -115,515 +109,314 @@
int users;
};
+static const char *drv_name = "blkvsc";
-/* Static decl */
-static DEFINE_MUTEX(blkvsc_mutex);
-static int blkvsc_probe(struct device *dev);
-static int blkvsc_remove(struct device *device);
-static void blkvsc_shutdown(struct device *device);
-
-static int blkvsc_open(struct block_device *bdev, fmode_t mode);
-static int blkvsc_release(struct gendisk *disk, fmode_t mode);
-static unsigned int blkvsc_check_events(struct gendisk *gd,
- unsigned int clearing);
-static int blkvsc_revalidate_disk(struct gendisk *gd);
-static int blkvsc_getgeo(struct block_device *bd, struct hd_geometry *hg);
-static int blkvsc_ioctl(struct block_device *bd, fmode_t mode,
- unsigned cmd, unsigned long argument);
-static void blkvsc_request(struct request_queue *queue);
-static void blkvsc_request_completion(struct hv_storvsc_request *request);
-static int blkvsc_do_request(struct block_device_context *blkdev,
- struct request *req);
-static int blkvsc_submit_request(struct blkvsc_request *blkvsc_req,
- void (*request_completion)(struct hv_storvsc_request *));
-static void blkvsc_init_rw(struct blkvsc_request *blkvsc_req);
-static void blkvsc_cmd_completion(struct hv_storvsc_request *request);
-static int blkvsc_do_inquiry(struct block_device_context *blkdev);
-static int blkvsc_do_read_capacity(struct block_device_context *blkdev);
-static int blkvsc_do_read_capacity16(struct block_device_context *blkdev);
-static int blkvsc_do_flush(struct block_device_context *blkdev);
-static int blkvsc_cancel_pending_reqs(struct block_device_context *blkdev);
-static int blkvsc_do_pending_reqs(struct block_device_context *blkdev);
-
-static int blkvsc_ringbuffer_size = BLKVSC_RING_BUFFER_SIZE;
-module_param(blkvsc_ringbuffer_size, int, S_IRUGO);
-MODULE_PARM_DESC(ring_size, "Ring buffer size (in bytes)");
-
-/* The one and only one */
-static struct storvsc_driver_object g_blkvsc_drv;
-
-static const struct block_device_operations block_ops = {
- .owner = THIS_MODULE,
- .open = blkvsc_open,
- .release = blkvsc_release,
- .check_events = blkvsc_check_events,
- .revalidate_disk = blkvsc_revalidate_disk,
- .getgeo = blkvsc_getgeo,
- .ioctl = blkvsc_ioctl,
+/* {32412632-86cb-44a2-9b5c-50d1417354f5} */
+static const struct hv_guid dev_type = {
+ .data = {
+ 0x32, 0x26, 0x41, 0x32, 0xcb, 0x86, 0xa2, 0x44,
+ 0x9b, 0x5c, 0x50, 0xd1, 0x41, 0x73, 0x54, 0xf5
+ }
};
/*
- * blkvsc_drv_init - BlkVsc driver initialization.
+ * There is a circular dependency involving blkvsc_request_completion()
+ * and blkvsc_do_request().
*/
-static int blkvsc_drv_init(int (*drv_init)(struct hv_driver *drv))
-{
- struct storvsc_driver_object *storvsc_drv_obj = &g_blkvsc_drv;
- struct hv_driver *drv = &g_blkvsc_drv.base;
- int ret;
+static void blkvsc_request_completion(struct hv_storvsc_request *request);
- storvsc_drv_obj->ring_buffer_size = blkvsc_ringbuffer_size;
+static int blkvsc_ringbuffer_size = BLKVSC_RING_BUFFER_SIZE;
- drv->priv = storvsc_drv_obj;
-
- /* Callback to client driver to complete the initialization */
- drv_init(&storvsc_drv_obj->base);
-
- drv->driver.name = storvsc_drv_obj->base.name;
-
- drv->driver.probe = blkvsc_probe;
- drv->driver.remove = blkvsc_remove;
- drv->driver.shutdown = blkvsc_shutdown;
-
- /* The driver belongs to vmbus */
- ret = vmbus_child_driver_register(&drv->driver);
-
- return ret;
-}
-
-static int blkvsc_drv_exit_cb(struct device *dev, void *data)
-{
- struct device **curr = (struct device **)data;
- *curr = dev;
- return 1; /* stop iterating */
-}
-
-static void blkvsc_drv_exit(void)
-{
- struct storvsc_driver_object *storvsc_drv_obj = &g_blkvsc_drv;
- struct hv_driver *drv = &g_blkvsc_drv.base;
- struct device *current_dev;
- int ret;
-
- while (1) {
- current_dev = NULL;
-
- /* Get the device */
- ret = driver_for_each_device(&drv->driver, NULL,
- (void *) ¤t_dev,
- blkvsc_drv_exit_cb);
-
- if (ret)
- DPRINT_WARN(BLKVSC_DRV,
- "driver_for_each_device returned %d", ret);
-
-
- if (current_dev == NULL)
- break;
-
- /* Initiate removal from the top-down */
- device_unregister(current_dev);
- }
-
- if (storvsc_drv_obj->base.cleanup)
- storvsc_drv_obj->base.cleanup(&storvsc_drv_obj->base);
-
- vmbus_child_driver_unregister(&drv->driver);
-
- return;
-}
+module_param(blkvsc_ringbuffer_size, int, S_IRUGO);
+MODULE_PARM_DESC(ring_size, "Ring buffer size (in bytes)");
/*
- * blkvsc_probe - Add a new device for this driver
+ * There is a circular dependency involving blkvsc_probe()
+ * and block_ops.
*/
-static int blkvsc_probe(struct device *device)
-{
- struct hv_driver *drv =
- drv_to_hv_drv(device->driver);
- struct storvsc_driver_object *storvsc_drv_obj =
- drv->priv;
- struct hv_device *device_obj = device_to_hv_device(device);
+static int blkvsc_probe(struct hv_device *dev);
- struct block_device_context *blkdev = NULL;
- struct storvsc_device_info device_info;
- int major = 0;
- int devnum = 0;
+static int blkvsc_device_add(struct hv_device *device,
+ void *additional_info)
+{
+ struct storvsc_device_info *device_info;
int ret = 0;
- static int ide0_registered;
- static int ide1_registered;
- DPRINT_DBG(BLKVSC_DRV, "blkvsc_probe - enter");
+ device_info = (struct storvsc_device_info *)additional_info;
- if (!storvsc_drv_obj->base.dev_add) {
- DPRINT_ERR(BLKVSC_DRV, "OnDeviceAdd() not set");
- ret = -1;
- goto Cleanup;
- }
+ device_info->ring_buffer_size = blkvsc_ringbuffer_size;
- blkdev = kzalloc(sizeof(struct block_device_context), GFP_KERNEL);
- if (!blkdev) {
- ret = -ENOMEM;
- goto Cleanup;
- }
-
- INIT_LIST_HEAD(&blkdev->pending_list);
-
- /* Initialize what we can here */
- spin_lock_init(&blkdev->lock);
-
- /* ASSERT(sizeof(struct blkvsc_request_group) <= */
- /* sizeof(struct blkvsc_request)); */
-
- blkdev->request_pool = kmem_cache_create(dev_name(&device_obj->device),
- sizeof(struct blkvsc_request) +
- storvsc_drv_obj->request_ext_size, 0,
- SLAB_HWCACHE_ALIGN, NULL);
- if (!blkdev->request_pool) {
- ret = -ENOMEM;
- goto Cleanup;
- }
-
-
- /* Call to the vsc driver to add the device */
- ret = storvsc_drv_obj->base.dev_add(device_obj, &device_info);
- if (ret != 0) {
- DPRINT_ERR(BLKVSC_DRV, "unable to add blkvsc device");
- goto Cleanup;
- }
-
- blkdev->device_ctx = device_obj;
- /* this identified the device 0 or 1 */
- blkdev->target = device_info.target_id;
- /* this identified the ide ctrl 0 or 1 */
- blkdev->path = device_info.path_id;
-
- dev_set_drvdata(device, blkdev);
-
- /* Calculate the major and device num */
- if (blkdev->path == 0) {
- major = IDE0_MAJOR;
- devnum = blkdev->path + blkdev->target; /* 0 or 1 */
-
- if (!ide0_registered) {
- ret = register_blkdev(major, "ide");
- if (ret != 0) {
- DPRINT_ERR(BLKVSC_DRV,
- "register_blkdev() failed! ret %d",
- ret);
- goto Remove;
- }
-
- ide0_registered = 1;
- }
- } else if (blkdev->path == 1) {
- major = IDE1_MAJOR;
- devnum = blkdev->path + blkdev->target + 1; /* 2 or 3 */
-
- if (!ide1_registered) {
- ret = register_blkdev(major, "ide");
- if (ret != 0) {
- DPRINT_ERR(BLKVSC_DRV,
- "register_blkdev() failed! ret %d",
- ret);
- goto Remove;
- }
-
- ide1_registered = 1;
- }
- } else {
- DPRINT_ERR(BLKVSC_DRV, "invalid pathid");
- ret = -1;
- goto Cleanup;
- }
-
- DPRINT_INFO(BLKVSC_DRV, "blkvsc registered for major %d!!", major);
-
- blkdev->gd = alloc_disk(BLKVSC_MINORS);
- if (!blkdev->gd) {
- DPRINT_ERR(BLKVSC_DRV, "register_blkdev() failed! ret %d", ret);
- ret = -1;
- goto Cleanup;
- }
-
- blkdev->gd->queue = blk_init_queue(blkvsc_request, &blkdev->lock);
-
- blk_queue_max_segment_size(blkdev->gd->queue, PAGE_SIZE);
- blk_queue_max_segments(blkdev->gd->queue, MAX_MULTIPAGE_BUFFER_COUNT);
- blk_queue_segment_boundary(blkdev->gd->queue, PAGE_SIZE-1);
- blk_queue_bounce_limit(blkdev->gd->queue, BLK_BOUNCE_ANY);
- blk_queue_dma_alignment(blkdev->gd->queue, 511);
-
- blkdev->gd->major = major;
- if (devnum == 1 || devnum == 3)
- blkdev->gd->first_minor = BLKVSC_MINORS;
- else
- blkdev->gd->first_minor = 0;
- blkdev->gd->fops = &block_ops;
- blkdev->gd->events = DISK_EVENT_MEDIA_CHANGE;
- blkdev->gd->private_data = blkdev;
- blkdev->gd->driverfs_dev = &(blkdev->device_ctx->device);
- sprintf(blkdev->gd->disk_name, "hd%c", 'a' + devnum);
-
- blkvsc_do_inquiry(blkdev);
- if (blkdev->device_type == DVD_TYPE) {
- set_disk_ro(blkdev->gd, 1);
- blkdev->gd->flags |= GENHD_FL_REMOVABLE;
- blkvsc_do_read_capacity(blkdev);
- } else {
- blkvsc_do_read_capacity16(blkdev);
- }
-
- set_capacity(blkdev->gd, blkdev->capacity * (blkdev->sector_size/512));
- blk_queue_logical_block_size(blkdev->gd->queue, blkdev->sector_size);
- /* go! */
- add_disk(blkdev->gd);
-
- DPRINT_INFO(BLKVSC_DRV, "%s added!! capacity %lu sector_size %d",
- blkdev->gd->disk_name, (unsigned long)blkdev->capacity,
- blkdev->sector_size);
-
- return ret;
-
-Remove:
- storvsc_drv_obj->base.dev_rm(device_obj);
-
-Cleanup:
- if (blkdev) {
- if (blkdev->request_pool) {
- kmem_cache_destroy(blkdev->request_pool);
- blkdev->request_pool = NULL;
- }
- kfree(blkdev);
- blkdev = NULL;
- }
-
- return ret;
-}
-
-static void blkvsc_shutdown(struct device *device)
-{
- struct block_device_context *blkdev = dev_get_drvdata(device);
- unsigned long flags;
-
- if (!blkdev)
- return;
-
- DPRINT_DBG(BLKVSC_DRV, "blkvsc_shutdown - users %d disk %s\n",
- blkdev->users, blkdev->gd->disk_name);
-
- spin_lock_irqsave(&blkdev->lock, flags);
-
- blkdev->shutting_down = 1;
-
- blk_stop_queue(blkdev->gd->queue);
-
- spin_unlock_irqrestore(&blkdev->lock, flags);
-
- while (blkdev->num_outstanding_reqs) {
- DPRINT_INFO(STORVSC, "waiting for %d requests to complete...",
- blkdev->num_outstanding_reqs);
- udelay(100);
- }
-
- blkvsc_do_flush(blkdev);
-
- spin_lock_irqsave(&blkdev->lock, flags);
-
- blkvsc_cancel_pending_reqs(blkdev);
-
- spin_unlock_irqrestore(&blkdev->lock, flags);
-}
-
-static int blkvsc_do_flush(struct block_device_context *blkdev)
-{
- struct blkvsc_request *blkvsc_req;
-
- DPRINT_DBG(BLKVSC_DRV, "blkvsc_do_flush()\n");
-
- if (blkdev->device_type != HARDDISK_TYPE)
- return 0;
-
- blkvsc_req = kmem_cache_alloc(blkdev->request_pool, GFP_KERNEL);
- if (!blkvsc_req)
- return -ENOMEM;
-
- memset(blkvsc_req, 0, sizeof(struct blkvsc_request));
- init_waitqueue_head(&blkvsc_req->wevent);
- blkvsc_req->dev = blkdev;
- blkvsc_req->req = NULL;
- blkvsc_req->write = 0;
-
- blkvsc_req->request.data_buffer.pfn_array[0] = 0;
- blkvsc_req->request.data_buffer.offset = 0;
- blkvsc_req->request.data_buffer.len = 0;
-
- blkvsc_req->cmnd[0] = SYNCHRONIZE_CACHE;
- blkvsc_req->cmd_len = 10;
+ ret = storvsc_dev_add(device, additional_info);
+ if (ret != 0)
+ return ret;
/*
- * Set this here since the completion routine may be invoked and
- * completed before we return
+ * We need to use the device instance guid to set the path and target
+ * id. For IDE devices, the device instance id is formatted as
+ * <bus id> * - <device id> - 8899 - 000000000000.
*/
- blkvsc_req->cond = 0;
- blkvsc_submit_request(blkvsc_req, blkvsc_cmd_completion);
+ device_info->path_id = device->dev_instance.data[3] << 24 |
+ device->dev_instance.data[2] << 16 |
+ device->dev_instance.data[1] << 8 |
+ device->dev_instance.data[0];
- wait_event_interruptible(blkvsc_req->wevent, blkvsc_req->cond);
+ device_info->target_id = device->dev_instance.data[5] << 8 |
+ device->dev_instance.data[4];
- kmem_cache_free(blkvsc_req->dev->request_pool, blkvsc_req);
+ return ret;
+}
+
+static int blkvsc_submit_request(struct blkvsc_request *blkvsc_req,
+ void (*request_completion)(struct hv_storvsc_request *))
+{
+ struct block_device_context *blkdev = blkvsc_req->dev;
+ struct hv_storvsc_request *storvsc_req;
+ struct vmscsi_request *vm_srb;
+ int ret;
+
+
+ storvsc_req = &blkvsc_req->request;
+ vm_srb = &storvsc_req->vstor_packet.vm_srb;
+
+ vm_srb->data_in = blkvsc_req->write ? WRITE_TYPE : READ_TYPE;
+
+ storvsc_req->on_io_completion = request_completion;
+ storvsc_req->context = blkvsc_req;
+
+ vm_srb->port_number = blkdev->port;
+ vm_srb->path_id = blkdev->path;
+ vm_srb->target_id = blkdev->target;
+ vm_srb->lun = 0; /* this is not really used at all */
+
+ vm_srb->cdb_length = blkvsc_req->cmd_len;
+
+ memcpy(vm_srb->cdb, blkvsc_req->cmnd, vm_srb->cdb_length);
+
+ storvsc_req->sense_buffer = blkvsc_req->sense_buffer;
+
+ ret = storvsc_do_io(blkdev->device_ctx,
+ &blkvsc_req->request);
+ if (ret == 0)
+ blkdev->num_outstanding_reqs++;
+
+ return ret;
+}
+
+
+static int blkvsc_open(struct block_device *bdev, fmode_t mode)
+{
+ struct block_device_context *blkdev = bdev->bd_disk->private_data;
+ unsigned long flags;
+
+ spin_lock_irqsave(&blkdev->lock, flags);
+
+ blkdev->users++;
+
+ spin_unlock_irqrestore(&blkdev->lock, flags);
return 0;
}
-/* Do a scsi INQUIRY cmd here to get the device type (ie disk or dvd) */
-static int blkvsc_do_inquiry(struct block_device_context *blkdev)
+
+static int blkvsc_getgeo(struct block_device *bd, struct hd_geometry *hg)
+{
+ sector_t nsect = get_capacity(bd->bd_disk);
+ sector_t cylinders = nsect;
+
+ /*
+ * We are making up these values; let us keep it simple.
+ */
+ hg->heads = 0xff;
+ hg->sectors = 0x3f;
+ sector_div(cylinders, hg->heads * hg->sectors);
+ hg->cylinders = cylinders;
+ if ((sector_t)(hg->cylinders + 1) * hg->heads * hg->sectors < nsect)
+ hg->cylinders = 0xffff;
+ return 0;
+
+}
+
+
+static void blkvsc_init_rw(struct blkvsc_request *blkvsc_req)
+{
+
+ blkvsc_req->cmd_len = 16;
+
+ if (rq_data_dir(blkvsc_req->req)) {
+ blkvsc_req->write = 1;
+ blkvsc_req->cmnd[0] = WRITE_16;
+ } else {
+ blkvsc_req->write = 0;
+ blkvsc_req->cmnd[0] = READ_16;
+ }
+
+ blkvsc_req->cmnd[1] |=
+ (blkvsc_req->req->cmd_flags & REQ_FUA) ? 0x8 : 0;
+
+ *(unsigned long long *)&blkvsc_req->cmnd[2] =
+ cpu_to_be64(blkvsc_req->sector_start);
+ *(unsigned int *)&blkvsc_req->cmnd[10] =
+ cpu_to_be32(blkvsc_req->sector_count);
+}
+
+
+static int blkvsc_ioctl(struct block_device *bd, fmode_t mode,
+ unsigned cmd, unsigned long arg)
+{
+ struct block_device_context *blkdev = bd->bd_disk->private_data;
+ int ret = 0;
+
+ switch (cmd) {
+ case HDIO_GET_IDENTITY:
+ if (copy_to_user((void __user *)arg, blkdev->device_id,
+ blkdev->device_id_len))
+ ret = -EFAULT;
+ break;
+ default:
+ ret = -EINVAL;
+ break;
+ }
+
+ return ret;
+}
+
+static void blkvsc_cmd_completion(struct hv_storvsc_request *request)
+{
+ struct blkvsc_request *blkvsc_req =
+ (struct blkvsc_request *)request->context;
+ struct block_device_context *blkdev =
+ (struct block_device_context *)blkvsc_req->dev;
+ struct scsi_sense_hdr sense_hdr;
+ struct vmscsi_request *vm_srb;
+ unsigned long flags;
+
+
+ vm_srb = &blkvsc_req->request.vstor_packet.vm_srb;
+
+ spin_lock_irqsave(&blkdev->lock, flags);
+ blkdev->num_outstanding_reqs--;
+ spin_unlock_irqrestore(&blkdev->lock, flags);
+
+ if (vm_srb->scsi_status)
+ if (scsi_normalize_sense(blkvsc_req->sense_buffer,
+ SCSI_SENSE_BUFFERSIZE, &sense_hdr))
+ scsi_print_sense_hdr("blkvsc", &sense_hdr);
+
+ complete(&blkvsc_req->request.wait_event);
+}
+
+
+static int blkvsc_do_operation(struct block_device_context *blkdev,
+ enum blkvsc_op_type op)
{
struct blkvsc_request *blkvsc_req;
struct page *page_buf;
unsigned char *buf;
unsigned char device_type;
-
- DPRINT_DBG(BLKVSC_DRV, "blkvsc_do_inquiry()\n");
-
- blkvsc_req = kmem_cache_alloc(blkdev->request_pool, GFP_KERNEL);
- if (!blkvsc_req)
- return -ENOMEM;
-
- memset(blkvsc_req, 0, sizeof(struct blkvsc_request));
- page_buf = alloc_page(GFP_KERNEL);
- if (!page_buf) {
- kmem_cache_free(blkvsc_req->dev->request_pool, blkvsc_req);
- return -ENOMEM;
- }
-
- init_waitqueue_head(&blkvsc_req->wevent);
- blkvsc_req->dev = blkdev;
- blkvsc_req->req = NULL;
- blkvsc_req->write = 0;
-
- blkvsc_req->request.data_buffer.pfn_array[0] = page_to_pfn(page_buf);
- blkvsc_req->request.data_buffer.offset = 0;
- blkvsc_req->request.data_buffer.len = 64;
-
- blkvsc_req->cmnd[0] = INQUIRY;
- blkvsc_req->cmnd[1] = 0x1; /* Get product data */
- blkvsc_req->cmnd[2] = 0x83; /* mode page 83 */
- blkvsc_req->cmnd[4] = 64;
- blkvsc_req->cmd_len = 6;
-
- /*
- * Set this here since the completion routine may be invoked and
- * completed before we return
- */
- blkvsc_req->cond = 0;
-
- blkvsc_submit_request(blkvsc_req, blkvsc_cmd_completion);
-
- DPRINT_DBG(BLKVSC_DRV, "waiting %p to complete - cond %d\n",
- blkvsc_req, blkvsc_req->cond);
-
- wait_event_interruptible(blkvsc_req->wevent, blkvsc_req->cond);
-
- buf = kmap(page_buf);
-
- /* print_hex_dump_bytes("", DUMP_PREFIX_NONE, buf, 64); */
- /* be to le */
- device_type = buf[0] & 0x1F;
-
- if (device_type == 0x0) {
- blkdev->device_type = HARDDISK_TYPE;
- } else if (device_type == 0x5) {
- blkdev->device_type = DVD_TYPE;
- } else {
- /* TODO: this is currently unsupported device type */
- blkdev->device_type = UNKNOWN_DEV_TYPE;
- }
-
- DPRINT_DBG(BLKVSC_DRV, "device type %d\n", device_type);
-
- blkdev->device_id_len = buf[7];
- if (blkdev->device_id_len > 64)
- blkdev->device_id_len = 64;
-
- memcpy(blkdev->device_id, &buf[8], blkdev->device_id_len);
- /* printk_hex_dump_bytes("", DUMP_PREFIX_NONE, blkdev->device_id,
- * blkdev->device_id_len); */
-
- kunmap(page_buf);
-
- __free_page(page_buf);
-
- kmem_cache_free(blkvsc_req->dev->request_pool, blkvsc_req);
-
- return 0;
-}
-
-/* Do a scsi READ_CAPACITY cmd here to get the size of the disk */
-static int blkvsc_do_read_capacity(struct block_device_context *blkdev)
-{
- struct blkvsc_request *blkvsc_req;
- struct page *page_buf;
- unsigned char *buf;
struct scsi_sense_hdr sense_hdr;
+ struct vmscsi_request *vm_srb;
+ unsigned long flags;
- DPRINT_DBG(BLKVSC_DRV, "blkvsc_do_read_capacity()\n");
+ int ret = 0;
- blkdev->sector_size = 0;
- blkdev->capacity = 0;
- blkdev->media_not_present = 0; /* assume a disk is present */
-
- blkvsc_req = kmem_cache_alloc(blkdev->request_pool, GFP_KERNEL);
+ blkvsc_req = kmem_cache_zalloc(blkdev->request_pool, GFP_KERNEL);
if (!blkvsc_req)
return -ENOMEM;
- memset(blkvsc_req, 0, sizeof(struct blkvsc_request));
page_buf = alloc_page(GFP_KERNEL);
if (!page_buf) {
kmem_cache_free(blkvsc_req->dev->request_pool, blkvsc_req);
return -ENOMEM;
}
- init_waitqueue_head(&blkvsc_req->wevent);
+ vm_srb = &blkvsc_req->request.vstor_packet.vm_srb;
+ init_completion(&blkvsc_req->request.wait_event);
blkvsc_req->dev = blkdev;
blkvsc_req->req = NULL;
blkvsc_req->write = 0;
- blkvsc_req->request.data_buffer.pfn_array[0] = page_to_pfn(page_buf);
+ blkvsc_req->request.data_buffer.pfn_array[0] =
+ page_to_pfn(page_buf);
blkvsc_req->request.data_buffer.offset = 0;
- blkvsc_req->request.data_buffer.len = 8;
- blkvsc_req->cmnd[0] = READ_CAPACITY;
- blkvsc_req->cmd_len = 16;
+ switch (op) {
+ case DO_INQUIRY:
+ blkvsc_req->cmnd[0] = INQUIRY;
+ blkvsc_req->cmnd[1] = 0x1; /* Get product data */
+ blkvsc_req->cmnd[2] = 0x83; /* mode page 83 */
+ blkvsc_req->cmnd[4] = 64;
+ blkvsc_req->cmd_len = 6;
+ blkvsc_req->request.data_buffer.len = 64;
+ break;
- /*
- * Set this here since the completion routine may be invoked
- * and completed before we return
- */
- blkvsc_req->cond = 0;
+ case DO_CAPACITY:
+ blkdev->sector_size = 0;
+ blkdev->capacity = 0;
+ blkvsc_req->cmnd[0] = READ_CAPACITY;
+ blkvsc_req->cmd_len = 16;
+ blkvsc_req->request.data_buffer.len = 8;
+ break;
+
+ case DO_FLUSH:
+ blkvsc_req->cmnd[0] = SYNCHRONIZE_CACHE;
+ blkvsc_req->cmd_len = 10;
+ blkvsc_req->request.data_buffer.pfn_array[0] = 0;
+ blkvsc_req->request.data_buffer.len = 0;
+ break;
+ default:
+ ret = -EINVAL;
+ goto cleanup;
+ }
+
+ spin_lock_irqsave(&blkdev->lock, flags);
blkvsc_submit_request(blkvsc_req, blkvsc_cmd_completion);
+ spin_unlock_irqrestore(&blkdev->lock, flags);
- DPRINT_DBG(BLKVSC_DRV, "waiting %p to complete - cond %d\n",
- blkvsc_req, blkvsc_req->cond);
-
- wait_event_interruptible(blkvsc_req->wevent, blkvsc_req->cond);
+ wait_for_completion_interruptible(&blkvsc_req->request.wait_event);
/* check error */
- if (blkvsc_req->request.status) {
+ if (vm_srb->scsi_status) {
scsi_normalize_sense(blkvsc_req->sense_buffer,
SCSI_SENSE_BUFFERSIZE, &sense_hdr);
- if (sense_hdr.asc == 0x3A) {
- /* Medium not present */
- blkdev->media_not_present = 1;
- }
return 0;
}
+
buf = kmap(page_buf);
- /* be to le */
- blkdev->capacity = ((buf[0] << 24) | (buf[1] << 16) |
- (buf[2] << 8) | buf[3]) + 1;
- blkdev->sector_size = (buf[4] << 24) | (buf[5] << 16) |
- (buf[6] << 8) | buf[7];
+ switch (op) {
+ case DO_INQUIRY:
+ device_type = buf[0] & 0x1F;
+
+ if (device_type == 0x0)
+ blkdev->device_type = HARDDISK_TYPE;
+ else
+ blkdev->device_type = UNKNOWN_DEV_TYPE;
+
+ blkdev->device_id_len = buf[7];
+ if (blkdev->device_id_len > 64)
+ blkdev->device_id_len = 64;
+
+ memcpy(blkdev->device_id, &buf[8], blkdev->device_id_len);
+ break;
+
+ case DO_CAPACITY:
+ /* be to le */
+ blkdev->capacity =
+ ((buf[0] << 24) | (buf[1] << 16) |
+ (buf[2] << 8) | buf[3]) + 1;
+
+ blkdev->sector_size =
+ (buf[4] << 24) | (buf[5] << 16) |
+ (buf[6] << 8) | buf[7];
+ break;
+ default:
+ break;
+
+ }
+
+cleanup:
kunmap(page_buf);
@@ -631,119 +424,86 @@
kmem_cache_free(blkvsc_req->dev->request_pool, blkvsc_req);
- return 0;
+ return ret;
}
-static int blkvsc_do_read_capacity16(struct block_device_context *blkdev)
+
+static int blkvsc_cancel_pending_reqs(struct block_device_context *blkdev)
{
- struct blkvsc_request *blkvsc_req;
- struct page *page_buf;
- unsigned char *buf;
- struct scsi_sense_hdr sense_hdr;
+ struct blkvsc_request *pend_req, *tmp;
+ struct blkvsc_request *comp_req, *tmp2;
+ struct vmscsi_request *vm_srb;
- DPRINT_DBG(BLKVSC_DRV, "blkvsc_do_read_capacity16()\n");
+ int ret = 0;
- blkdev->sector_size = 0;
- blkdev->capacity = 0;
- blkdev->media_not_present = 0; /* assume a disk is present */
- blkvsc_req = kmem_cache_alloc(blkdev->request_pool, GFP_KERNEL);
- if (!blkvsc_req)
- return -ENOMEM;
+ /* Flush the pending list first */
+ list_for_each_entry_safe(pend_req, tmp, &blkdev->pending_list,
+ pend_entry) {
+ /*
+ * The pend_req could be part of a partially completed
+ * request. If so, complete those req first until we
+ * hit the pend_req
+ */
+ list_for_each_entry_safe(comp_req, tmp2,
+ &pend_req->group->blkvsc_req_list,
+ req_entry) {
- memset(blkvsc_req, 0, sizeof(struct blkvsc_request));
- page_buf = alloc_page(GFP_KERNEL);
- if (!page_buf) {
- kmem_cache_free(blkvsc_req->dev->request_pool, blkvsc_req);
- return -ENOMEM;
- }
+ if (comp_req == pend_req)
+ break;
- init_waitqueue_head(&blkvsc_req->wevent);
- blkvsc_req->dev = blkdev;
- blkvsc_req->req = NULL;
- blkvsc_req->write = 0;
+ list_del(&comp_req->req_entry);
- blkvsc_req->request.data_buffer.pfn_array[0] = page_to_pfn(page_buf);
- blkvsc_req->request.data_buffer.offset = 0;
- blkvsc_req->request.data_buffer.len = 12;
+ if (comp_req->req) {
+ vm_srb =
+ &comp_req->request.vstor_packet.
+ vm_srb;
+ ret = __blk_end_request(comp_req->req,
+ (!vm_srb->scsi_status ? 0 : -EIO),
+ comp_req->sector_count *
+ blkdev->sector_size);
- blkvsc_req->cmnd[0] = 0x9E; /* READ_CAPACITY16; */
- blkvsc_req->cmd_len = 16;
+ /* FIXME: shouldn't this do more than return? */
+ if (ret)
+ goto out;
+ }
- /*
- * Set this here since the completion routine may be invoked
- * and completed before we return
- */
- blkvsc_req->cond = 0;
-
- blkvsc_submit_request(blkvsc_req, blkvsc_cmd_completion);
-
- DPRINT_DBG(BLKVSC_DRV, "waiting %p to complete - cond %d\n",
- blkvsc_req, blkvsc_req->cond);
-
- wait_event_interruptible(blkvsc_req->wevent, blkvsc_req->cond);
-
- /* check error */
- if (blkvsc_req->request.status) {
- scsi_normalize_sense(blkvsc_req->sense_buffer,
- SCSI_SENSE_BUFFERSIZE, &sense_hdr);
- if (sense_hdr.asc == 0x3A) {
- /* Medium not present */
- blkdev->media_not_present = 1;
+ kmem_cache_free(blkdev->request_pool, comp_req);
}
- return 0;
+
+ list_del(&pend_req->pend_entry);
+
+ list_del(&pend_req->req_entry);
+
+ if (comp_req->req) {
+ if (!__blk_end_request(pend_req->req, -EIO,
+ pend_req->sector_count *
+ blkdev->sector_size)) {
+ /*
+ * All the sectors have been xferred ie the
+ * request is done
+ */
+ kmem_cache_free(blkdev->request_pool,
+ pend_req->group);
+ }
+ }
+
+ kmem_cache_free(blkdev->request_pool, pend_req);
}
- buf = kmap(page_buf);
- /* be to le */
- blkdev->capacity = be64_to_cpu(*(unsigned long long *) &buf[0]) + 1;
- blkdev->sector_size = be32_to_cpu(*(unsigned int *)&buf[8]);
-
-#if 0
- blkdev->capacity = ((buf[0] << 24) | (buf[1] << 16) |
- (buf[2] << 8) | buf[3]) + 1;
- blkdev->sector_size = (buf[4] << 24) | (buf[5] << 16) |
- (buf[6] << 8) | buf[7];
-#endif
-
- kunmap(page_buf);
-
- __free_page(page_buf);
-
- kmem_cache_free(blkvsc_req->dev->request_pool, blkvsc_req);
-
- return 0;
+out:
+ return ret;
}
+
/*
* blkvsc_remove() - Callback when our device is removed
*/
-static int blkvsc_remove(struct device *device)
+static int blkvsc_remove(struct hv_device *dev)
{
- struct hv_driver *drv =
- drv_to_hv_drv(device->driver);
- struct storvsc_driver_object *storvsc_drv_obj =
- drv->priv;
- struct hv_device *device_obj = device_to_hv_device(device);
- struct block_device_context *blkdev = dev_get_drvdata(device);
+ struct block_device_context *blkdev = dev_get_drvdata(&dev->device);
unsigned long flags;
- int ret;
- DPRINT_DBG(BLKVSC_DRV, "blkvsc_remove()\n");
-
- if (!storvsc_drv_obj->base.dev_rm)
- return -1;
-
- /*
- * Call to the vsc driver to let it know that the device is being
- * removed
- */
- ret = storvsc_drv_obj->base.dev_rm(device_obj);
- if (ret != 0) {
- /* TODO: */
- DPRINT_ERR(BLKVSC_DRV,
- "unable to remove blkvsc device (ret %d)", ret);
- }
/* Get to a known state */
spin_lock_irqsave(&blkdev->lock, flags);
@@ -752,149 +512,77 @@
blk_stop_queue(blkdev->gd->queue);
- spin_unlock_irqrestore(&blkdev->lock, flags);
-
- while (blkdev->num_outstanding_reqs) {
- DPRINT_INFO(STORVSC, "waiting for %d requests to complete...",
- blkdev->num_outstanding_reqs);
- udelay(100);
- }
-
- blkvsc_do_flush(blkdev);
-
- spin_lock_irqsave(&blkdev->lock, flags);
-
blkvsc_cancel_pending_reqs(blkdev);
spin_unlock_irqrestore(&blkdev->lock, flags);
+ blkvsc_do_operation(blkdev, DO_FLUSH);
+
blk_cleanup_queue(blkdev->gd->queue);
+ /*
+ * Call to the vsc driver to let it know that the device is being
+ * removed
+ */
+ storvsc_dev_remove(dev);
+
del_gendisk(blkdev->gd);
kmem_cache_destroy(blkdev->request_pool);
kfree(blkdev);
- return ret;
+ return 0;
+
}
-static void blkvsc_init_rw(struct blkvsc_request *blkvsc_req)
+static void blkvsc_shutdown(struct hv_device *dev)
{
- /* ASSERT(blkvsc_req->req); */
- /* ASSERT(blkvsc_req->sector_count <= (MAX_MULTIPAGE_BUFFER_COUNT*8)); */
+ struct block_device_context *blkdev = dev_get_drvdata(&dev->device);
+ unsigned long flags;
- blkvsc_req->cmd_len = 16;
+ if (!blkdev)
+ return;
- if (blkvsc_req->sector_start > 0xffffffff) {
- if (rq_data_dir(blkvsc_req->req)) {
- blkvsc_req->write = 1;
- blkvsc_req->cmnd[0] = WRITE_16;
- } else {
- blkvsc_req->write = 0;
- blkvsc_req->cmnd[0] = READ_16;
- }
+ spin_lock_irqsave(&blkdev->lock, flags);
- blkvsc_req->cmnd[1] |=
- (blkvsc_req->req->cmd_flags & REQ_FUA) ? 0x8 : 0;
+ blkdev->shutting_down = 1;
- *(unsigned long long *)&blkvsc_req->cmnd[2] =
- cpu_to_be64(blkvsc_req->sector_start);
- *(unsigned int *)&blkvsc_req->cmnd[10] =
- cpu_to_be32(blkvsc_req->sector_count);
- } else if ((blkvsc_req->sector_count > 0xff) ||
- (blkvsc_req->sector_start > 0x1fffff)) {
- if (rq_data_dir(blkvsc_req->req)) {
- blkvsc_req->write = 1;
- blkvsc_req->cmnd[0] = WRITE_10;
- } else {
- blkvsc_req->write = 0;
- blkvsc_req->cmnd[0] = READ_10;
- }
+ blk_stop_queue(blkdev->gd->queue);
- blkvsc_req->cmnd[1] |=
- (blkvsc_req->req->cmd_flags & REQ_FUA) ? 0x8 : 0;
+ blkvsc_cancel_pending_reqs(blkdev);
- *(unsigned int *)&blkvsc_req->cmnd[2] =
- cpu_to_be32(blkvsc_req->sector_start);
- *(unsigned short *)&blkvsc_req->cmnd[7] =
- cpu_to_be16(blkvsc_req->sector_count);
- } else {
- if (rq_data_dir(blkvsc_req->req)) {
- blkvsc_req->write = 1;
- blkvsc_req->cmnd[0] = WRITE_6;
- } else {
- blkvsc_req->write = 0;
- blkvsc_req->cmnd[0] = READ_6;
- }
+ spin_unlock_irqrestore(&blkdev->lock, flags);
- *(unsigned int *)&blkvsc_req->cmnd[1] =
- cpu_to_be32(blkvsc_req->sector_start) >> 8;
- blkvsc_req->cmnd[1] &= 0x1f;
- blkvsc_req->cmnd[4] = (unsigned char)blkvsc_req->sector_count;
- }
+ blkvsc_do_operation(blkdev, DO_FLUSH);
+
+ /*
+ * Now wait for all outgoing I/O to be drained.
+ */
+ storvsc_wait_to_drain((struct storvsc_device *)dev->ext);
+
}
-static int blkvsc_submit_request(struct blkvsc_request *blkvsc_req,
- void (*request_completion)(struct hv_storvsc_request *))
+static int blkvsc_release(struct gendisk *disk, fmode_t mode)
{
- struct block_device_context *blkdev = blkvsc_req->dev;
- struct hv_device *device_ctx = blkdev->device_ctx;
- struct hv_driver *drv =
- drv_to_hv_drv(device_ctx->device.driver);
- struct storvsc_driver_object *storvsc_drv_obj =
- drv->priv;
- struct hv_storvsc_request *storvsc_req;
- int ret;
+ struct block_device_context *blkdev = disk->private_data;
+ unsigned long flags;
- DPRINT_DBG(BLKVSC_DRV, "blkvsc_submit_request() - "
- "req %p type %s start_sector %lu count %ld offset %d "
- "len %d\n", blkvsc_req,
- (blkvsc_req->write) ? "WRITE" : "READ",
- (unsigned long) blkvsc_req->sector_start,
- blkvsc_req->sector_count,
- blkvsc_req->request.data_buffer.offset,
- blkvsc_req->request.data_buffer.len);
-#if 0
- for (i = 0; i < (blkvsc_req->request.data_buffer.len >> 12); i++) {
- DPRINT_DBG(BLKVSC_DRV, "blkvsc_submit_request() - "
- "req %p pfn[%d] %llx\n",
- blkvsc_req, i,
- blkvsc_req->request.data_buffer.pfn_array[i]);
+ if (blkdev->users == 1) {
+ blkvsc_do_operation(blkdev, DO_FLUSH);
}
-#endif
- storvsc_req = &blkvsc_req->request;
- storvsc_req->extension = (void *)((unsigned long)blkvsc_req +
- sizeof(struct blkvsc_request));
+ spin_lock_irqsave(&blkdev->lock, flags);
+ blkdev->users--;
+ spin_unlock_irqrestore(&blkdev->lock, flags);
- storvsc_req->type = blkvsc_req->write ? WRITE_TYPE : READ_TYPE;
-
- storvsc_req->on_io_completion = request_completion;
- storvsc_req->context = blkvsc_req;
-
- storvsc_req->host = blkdev->port;
- storvsc_req->bus = blkdev->path;
- storvsc_req->target_id = blkdev->target;
- storvsc_req->lun_id = 0; /* this is not really used at all */
-
- storvsc_req->cdb_len = blkvsc_req->cmd_len;
- storvsc_req->cdb = blkvsc_req->cmnd;
-
- storvsc_req->sense_buffer = blkvsc_req->sense_buffer;
- storvsc_req->sense_buffer_size = SCSI_SENSE_BUFFERSIZE;
-
- ret = storvsc_drv_obj->on_io_request(blkdev->device_ctx,
- &blkvsc_req->request);
- if (ret == 0)
- blkdev->num_outstanding_reqs++;
-
- return ret;
+ return 0;
}
+
/*
* We break the request into 1 or more blkvsc_requests and submit
- * them. If we can't submit them all, we put them on the
+ * them. If we cant submit them all, we put them on the
* pending_list. The blkvsc_request() will work on the pending_list.
*/
static int blkvsc_do_request(struct block_device_context *blkdev,
@@ -913,11 +601,8 @@
int pending = 0;
struct blkvsc_request_group *group = NULL;
- DPRINT_DBG(BLKVSC_DRV, "blkdev %p req %p sect %lu\n", blkdev, req,
- (unsigned long)blk_rq_pos(req));
-
/* Create a group to tie req to list of blkvsc_reqs */
- group = kmem_cache_alloc(blkdev->request_pool, GFP_ATOMIC);
+ group = kmem_cache_zalloc(blkdev->request_pool, GFP_ATOMIC);
if (!group)
return -ENOMEM;
@@ -933,11 +618,6 @@
* Map this bio into an existing or new storvsc request
*/
bio_for_each_segment(bvec, bio, seg_idx) {
- DPRINT_DBG(BLKVSC_DRV, "bio_for_each_segment() "
- "- req %p bio %p bvec %p seg_idx %d "
- "databuf_idx %d\n", req, bio, bvec,
- seg_idx, databuf_idx);
-
/* Get a new storvsc request */
/* 1st-time */
if ((!blkvsc_req) ||
@@ -949,10 +629,15 @@
(prev_bvec->bv_len != PAGE_SIZE))) {
/* submit the prev one */
if (blkvsc_req) {
- blkvsc_req->sector_start = start_sector;
- sector_div(blkvsc_req->sector_start, (blkdev->sector_size >> 9));
+ blkvsc_req->sector_start =
+ start_sector;
+ sector_div(
+ blkvsc_req->sector_start,
+ (blkdev->sector_size >> 9));
- blkvsc_req->sector_count = num_sectors / (blkdev->sector_size >> 9);
+ blkvsc_req->sector_count =
+ num_sectors /
+ (blkdev->sector_size >> 9);
blkvsc_init_rw(blkvsc_req);
}
@@ -960,18 +645,24 @@
* Create new blkvsc_req to represent
* the current bvec
*/
- blkvsc_req = kmem_cache_alloc(blkdev->request_pool, GFP_ATOMIC);
+ blkvsc_req =
+ kmem_cache_zalloc(
+ blkdev->request_pool, GFP_ATOMIC);
if (!blkvsc_req) {
/* free up everything */
list_for_each_entry_safe(
blkvsc_req, tmp,
&group->blkvsc_req_list,
req_entry) {
- list_del(&blkvsc_req->req_entry);
- kmem_cache_free(blkdev->request_pool, blkvsc_req);
+ list_del(
+ &blkvsc_req->req_entry);
+ kmem_cache_free(
+ blkdev->request_pool,
+ blkvsc_req);
}
- kmem_cache_free(blkdev->request_pool, group);
+ kmem_cache_free(
+ blkdev->request_pool, group);
return -ENOMEM;
}
@@ -980,23 +671,27 @@
blkvsc_req->dev = blkdev;
blkvsc_req->req = req;
- blkvsc_req->request.data_buffer.offset
- = bvec->bv_offset;
- blkvsc_req->request.data_buffer.len
- = 0;
+ blkvsc_req->request.
+ data_buffer.offset
+ = bvec->bv_offset;
+ blkvsc_req->request.
+ data_buffer.len = 0;
/* Add to the group */
blkvsc_req->group = group;
blkvsc_req->group->outstanding++;
list_add_tail(&blkvsc_req->req_entry,
- &blkvsc_req->group->blkvsc_req_list);
+ &blkvsc_req->group->blkvsc_req_list);
start_sector += num_sectors;
num_sectors = 0;
databuf_idx = 0;
}
- /* Add the curr bvec/segment to the curr blkvsc_req */
+ /*
+ * Add the curr bvec/segment to the curr
+ * blkvsc_req
+ */
blkvsc_req->request.data_buffer.
pfn_array[databuf_idx]
= page_to_pfn(bvec->bv_page);
@@ -1015,10 +710,6 @@
/* Handle the last one */
if (blkvsc_req) {
- DPRINT_DBG(BLKVSC_DRV, "blkdev %p req %p group %p count %d\n",
- blkdev, req, blkvsc_req->group,
- blkvsc_req->group->outstanding);
-
blkvsc_req->sector_start = start_sector;
sector_div(blkvsc_req->sector_start,
(blkdev->sector_size >> 9));
@@ -1031,13 +722,6 @@
list_for_each_entry(blkvsc_req, &group->blkvsc_req_list, req_entry) {
if (pending) {
- DPRINT_DBG(BLKVSC_DRV, "adding blkvsc_req to "
- "pending_list - blkvsc_req %p start_sect %lu"
- " sect_count %ld (%lu %ld)\n", blkvsc_req,
- (unsigned long)blkvsc_req->sector_start,
- blkvsc_req->sector_count,
- (unsigned long)start_sector,
- (unsigned long)num_sectors);
list_add_tail(&blkvsc_req->pend_entry,
&blkdev->pending_list);
@@ -1050,39 +734,226 @@
&blkdev->pending_list);
}
- DPRINT_DBG(BLKVSC_DRV, "submitted blkvsc_req %p "
- "start_sect %lu sect_count %ld (%lu %ld) "
- "ret %d\n", blkvsc_req,
- (unsigned long)blkvsc_req->sector_start,
- blkvsc_req->sector_count,
- (unsigned long)start_sector,
- num_sectors, ret);
}
}
return pending;
}
-static void blkvsc_cmd_completion(struct hv_storvsc_request *request)
+static int blkvsc_do_pending_reqs(struct block_device_context *blkdev)
{
- struct blkvsc_request *blkvsc_req =
- (struct blkvsc_request *)request->context;
- struct block_device_context *blkdev =
- (struct block_device_context *)blkvsc_req->dev;
- struct scsi_sense_hdr sense_hdr;
+ struct blkvsc_request *pend_req, *tmp;
+ int ret = 0;
- DPRINT_DBG(BLKVSC_DRV, "blkvsc_cmd_completion() - req %p\n",
- blkvsc_req);
+ /* Flush the pending list first */
+ list_for_each_entry_safe(pend_req, tmp, &blkdev->pending_list,
+ pend_entry) {
- blkdev->num_outstanding_reqs--;
+ ret = blkvsc_submit_request(pend_req,
+ blkvsc_request_completion);
+ if (ret != 0)
+ break;
+ else
+ list_del(&pend_req->pend_entry);
+ }
- if (blkvsc_req->request.status)
- if (scsi_normalize_sense(blkvsc_req->sense_buffer,
- SCSI_SENSE_BUFFERSIZE, &sense_hdr))
- scsi_print_sense_hdr("blkvsc", &sense_hdr);
+ return ret;
+}
- blkvsc_req->cond = 1;
- wake_up_interruptible(&blkvsc_req->wevent);
+
+static void blkvsc_request(struct request_queue *queue)
+{
+ struct block_device_context *blkdev = NULL;
+ struct request *req;
+ int ret = 0;
+
+ while ((req = blk_peek_request(queue)) != NULL) {
+
+ blkdev = req->rq_disk->private_data;
+ if (blkdev->shutting_down || req->cmd_type != REQ_TYPE_FS) {
+ __blk_end_request_cur(req, 0);
+ continue;
+ }
+
+ ret = blkvsc_do_pending_reqs(blkdev);
+
+ if (ret != 0) {
+ blk_stop_queue(queue);
+ break;
+ }
+
+ blk_start_request(req);
+
+ ret = blkvsc_do_request(blkdev, req);
+ if (ret > 0) {
+ blk_stop_queue(queue);
+ break;
+ } else if (ret < 0) {
+ blk_requeue_request(queue, req);
+ blk_stop_queue(queue);
+ break;
+ }
+ }
+}
+
+
+
+/* The one and only one */
+static struct hv_driver blkvsc_drv = {
+ .probe = blkvsc_probe,
+ .remove = blkvsc_remove,
+ .shutdown = blkvsc_shutdown,
+};
+
+static const struct block_device_operations block_ops = {
+ .owner = THIS_MODULE,
+ .open = blkvsc_open,
+ .release = blkvsc_release,
+ .getgeo = blkvsc_getgeo,
+ .ioctl = blkvsc_ioctl,
+};
+
+/*
+ * blkvsc_drv_init - BlkVsc driver initialization.
+ */
+static int blkvsc_drv_init(void)
+{
+ struct hv_driver *drv = &blkvsc_drv;
+ int ret;
+
+ BUILD_BUG_ON(sizeof(sector_t) != 8);
+
+ memcpy(&drv->dev_type, &dev_type, sizeof(struct hv_guid));
+ drv->name = drv_name;
+ drv->driver.name = drv_name;
+
+ /* The driver belongs to vmbus */
+ ret = vmbus_child_driver_register(&drv->driver);
+
+ return ret;
+}
+
+
+static void blkvsc_drv_exit(void)
+{
+
+ vmbus_child_driver_unregister(&blkvsc_drv.driver);
+}
+
+/*
+ * blkvsc_probe - Add a new device for this driver
+ */
+static int blkvsc_probe(struct hv_device *dev)
+{
+ struct block_device_context *blkdev = NULL;
+ struct storvsc_device_info device_info;
+ struct storvsc_major_info major_info;
+ int ret = 0;
+
+ blkdev = kzalloc(sizeof(struct block_device_context), GFP_KERNEL);
+ if (!blkdev) {
+ ret = -ENOMEM;
+ goto cleanup;
+ }
+
+ INIT_LIST_HEAD(&blkdev->pending_list);
+
+ /* Initialize what we can here */
+ spin_lock_init(&blkdev->lock);
+
+
+ blkdev->request_pool = kmem_cache_create(dev_name(&dev->device),
+ sizeof(struct blkvsc_request), 0,
+ SLAB_HWCACHE_ALIGN, NULL);
+ if (!blkdev->request_pool) {
+ ret = -ENOMEM;
+ goto cleanup;
+ }
+
+
+ ret = blkvsc_device_add(dev, &device_info);
+ if (ret != 0)
+ goto cleanup;
+
+ blkdev->device_ctx = dev;
+ /* this identified the device 0 or 1 */
+ blkdev->target = device_info.target_id;
+ /* this identified the ide ctrl 0 or 1 */
+ blkdev->path = device_info.path_id;
+
+ dev_set_drvdata(&dev->device, blkdev);
+
+ ret = storvsc_get_major_info(&device_info, &major_info);
+
+ if (ret)
+ goto cleanup;
+
+ if (major_info.do_register) {
+ ret = register_blkdev(major_info.major, major_info.devname);
+
+ if (ret != 0) {
+ DPRINT_ERR(BLKVSC_DRV,
+ "register_blkdev() failed! ret %d", ret);
+ goto remove;
+ }
+ }
+
+ DPRINT_INFO(BLKVSC_DRV, "blkvsc registered for major %d!!",
+ major_info.major);
+
+ blkdev->gd = alloc_disk(BLKVSC_MINORS);
+ if (!blkdev->gd) {
+ ret = -1;
+ goto cleanup;
+ }
+
+ blkdev->gd->queue = blk_init_queue(blkvsc_request, &blkdev->lock);
+
+ blk_queue_max_segment_size(blkdev->gd->queue, PAGE_SIZE);
+ blk_queue_max_segments(blkdev->gd->queue, MAX_MULTIPAGE_BUFFER_COUNT);
+ blk_queue_segment_boundary(blkdev->gd->queue, PAGE_SIZE-1);
+ blk_queue_bounce_limit(blkdev->gd->queue, BLK_BOUNCE_ANY);
+ blk_queue_dma_alignment(blkdev->gd->queue, 511);
+
+ blkdev->gd->major = major_info.major;
+ if (major_info.index == 1 || major_info.index == 3)
+ blkdev->gd->first_minor = BLKVSC_MINORS;
+ else
+ blkdev->gd->first_minor = 0;
+ blkdev->gd->fops = &block_ops;
+ blkdev->gd->events = DISK_EVENT_MEDIA_CHANGE;
+ blkdev->gd->private_data = blkdev;
+ blkdev->gd->driverfs_dev = &(blkdev->device_ctx->device);
+ sprintf(blkdev->gd->disk_name, "hd%c", 'a' + major_info.index);
+
+ blkvsc_do_operation(blkdev, DO_INQUIRY);
+ blkvsc_do_operation(blkdev, DO_CAPACITY);
+
+ set_capacity(blkdev->gd, blkdev->capacity * (blkdev->sector_size/512));
+ blk_queue_logical_block_size(blkdev->gd->queue, blkdev->sector_size);
+ /* go! */
+ add_disk(blkdev->gd);
+
+ DPRINT_INFO(BLKVSC_DRV, "%s added!! capacity %lu sector_size %d",
+ blkdev->gd->disk_name, (unsigned long)blkdev->capacity,
+ blkdev->sector_size);
+
+ return ret;
+
+remove:
+ storvsc_dev_remove(dev);
+
+cleanup:
+ if (blkdev) {
+ if (blkdev->request_pool) {
+ kmem_cache_destroy(blkdev->request_pool);
+ blkdev->request_pool = NULL;
+ }
+ kfree(blkdev);
+ blkdev = NULL;
+ }
+
+ return ret;
}
static void blkvsc_request_completion(struct hv_storvsc_request *request)
@@ -1093,19 +964,8 @@
(struct block_device_context *)blkvsc_req->dev;
unsigned long flags;
struct blkvsc_request *comp_req, *tmp;
+ struct vmscsi_request *vm_srb;
- /* ASSERT(blkvsc_req->group); */
-
- DPRINT_DBG(BLKVSC_DRV, "blkdev %p blkvsc_req %p group %p type %s "
- "sect_start %lu sect_count %ld len %d group outstd %d "
- "total outstd %d\n",
- blkdev, blkvsc_req, blkvsc_req->group,
- (blkvsc_req->write) ? "WRITE" : "READ",
- (unsigned long)blkvsc_req->sector_start,
- blkvsc_req->sector_count,
- blkvsc_req->request.data_buffer.len,
- blkvsc_req->group->outstanding,
- blkdev->num_outstanding_reqs);
spin_lock_irqsave(&blkdev->lock, flags);
@@ -1121,23 +981,18 @@
list_for_each_entry_safe(comp_req, tmp,
&blkvsc_req->group->blkvsc_req_list,
req_entry) {
- DPRINT_DBG(BLKVSC_DRV, "completing blkvsc_req %p "
- "sect_start %lu sect_count %ld\n",
- comp_req,
- (unsigned long)comp_req->sector_start,
- comp_req->sector_count);
list_del(&comp_req->req_entry);
+ vm_srb =
+ &comp_req->request.vstor_packet.vm_srb;
if (!__blk_end_request(comp_req->req,
- (!comp_req->request.status ? 0 : -EIO),
+ (!vm_srb->scsi_status ? 0 : -EIO),
comp_req->sector_count * blkdev->sector_size)) {
/*
* All the sectors have been xferred ie the
* request is done
*/
- DPRINT_DBG(BLKVSC_DRV, "req %p COMPLETED\n",
- comp_req->req);
kmem_cache_free(blkdev->request_pool,
comp_req->group);
}
@@ -1155,332 +1010,6 @@
spin_unlock_irqrestore(&blkdev->lock, flags);
}
-static int blkvsc_cancel_pending_reqs(struct block_device_context *blkdev)
-{
- struct blkvsc_request *pend_req, *tmp;
- struct blkvsc_request *comp_req, *tmp2;
-
- int ret = 0;
-
- DPRINT_DBG(BLKVSC_DRV, "blkvsc_cancel_pending_reqs()");
-
- /* Flush the pending list first */
- list_for_each_entry_safe(pend_req, tmp, &blkdev->pending_list,
- pend_entry) {
- /*
- * The pend_req could be part of a partially completed
- * request. If so, complete those req first until we
- * hit the pend_req
- */
- list_for_each_entry_safe(comp_req, tmp2,
- &pend_req->group->blkvsc_req_list,
- req_entry) {
- DPRINT_DBG(BLKVSC_DRV, "completing blkvsc_req %p "
- "sect_start %lu sect_count %ld\n",
- comp_req,
- (unsigned long) comp_req->sector_start,
- comp_req->sector_count);
-
- if (comp_req == pend_req)
- break;
-
- list_del(&comp_req->req_entry);
-
- if (comp_req->req) {
- ret = __blk_end_request(comp_req->req,
- (!comp_req->request.status ? 0 : -EIO),
- comp_req->sector_count *
- blkdev->sector_size);
-
- /* FIXME: shouldn't this do more than return? */
- if (ret)
- goto out;
- }
-
- kmem_cache_free(blkdev->request_pool, comp_req);
- }
-
- DPRINT_DBG(BLKVSC_DRV, "cancelling pending request - %p\n",
- pend_req);
-
- list_del(&pend_req->pend_entry);
-
- list_del(&pend_req->req_entry);
-
- if (comp_req->req) {
- if (!__blk_end_request(pend_req->req, -EIO,
- pend_req->sector_count *
- blkdev->sector_size)) {
- /*
- * All the sectors have been xferred ie the
- * request is done
- */
- DPRINT_DBG(BLKVSC_DRV,
- "blkvsc_cancel_pending_reqs() - "
- "req %p COMPLETED\n", pend_req->req);
- kmem_cache_free(blkdev->request_pool,
- pend_req->group);
- }
- }
-
- kmem_cache_free(blkdev->request_pool, pend_req);
- }
-
-out:
- return ret;
-}
-
-static int blkvsc_do_pending_reqs(struct block_device_context *blkdev)
-{
- struct blkvsc_request *pend_req, *tmp;
- int ret = 0;
-
- /* Flush the pending list first */
- list_for_each_entry_safe(pend_req, tmp, &blkdev->pending_list,
- pend_entry) {
- DPRINT_DBG(BLKVSC_DRV, "working off pending_list - %p\n",
- pend_req);
-
- ret = blkvsc_submit_request(pend_req,
- blkvsc_request_completion);
- if (ret != 0)
- break;
- else
- list_del(&pend_req->pend_entry);
- }
-
- return ret;
-}
-
-static void blkvsc_request(struct request_queue *queue)
-{
- struct block_device_context *blkdev = NULL;
- struct request *req;
- int ret = 0;
-
- DPRINT_DBG(BLKVSC_DRV, "- enter\n");
- while ((req = blk_peek_request(queue)) != NULL) {
- DPRINT_DBG(BLKVSC_DRV, "- req %p\n", req);
-
- blkdev = req->rq_disk->private_data;
- if (blkdev->shutting_down || req->cmd_type != REQ_TYPE_FS ||
- blkdev->media_not_present) {
- __blk_end_request_cur(req, 0);
- continue;
- }
-
- ret = blkvsc_do_pending_reqs(blkdev);
-
- if (ret != 0) {
- DPRINT_DBG(BLKVSC_DRV,
- "- stop queue - pending_list not empty\n");
- blk_stop_queue(queue);
- break;
- }
-
- blk_start_request(req);
-
- ret = blkvsc_do_request(blkdev, req);
- if (ret > 0) {
- DPRINT_DBG(BLKVSC_DRV, "- stop queue - no room\n");
- blk_stop_queue(queue);
- break;
- } else if (ret < 0) {
- DPRINT_DBG(BLKVSC_DRV, "- stop queue - no mem\n");
- blk_requeue_request(queue, req);
- blk_stop_queue(queue);
- break;
- }
- }
-}
-
-static int blkvsc_open(struct block_device *bdev, fmode_t mode)
-{
- struct block_device_context *blkdev = bdev->bd_disk->private_data;
-
- DPRINT_DBG(BLKVSC_DRV, "- users %d disk %s\n", blkdev->users,
- blkdev->gd->disk_name);
-
- mutex_lock(&blkvsc_mutex);
- spin_lock(&blkdev->lock);
-
- if (!blkdev->users && blkdev->device_type == DVD_TYPE) {
- spin_unlock(&blkdev->lock);
- check_disk_change(bdev);
- spin_lock(&blkdev->lock);
- }
-
- blkdev->users++;
-
- spin_unlock(&blkdev->lock);
- mutex_unlock(&blkvsc_mutex);
- return 0;
-}
-
-static int blkvsc_release(struct gendisk *disk, fmode_t mode)
-{
- struct block_device_context *blkdev = disk->private_data;
-
- DPRINT_DBG(BLKVSC_DRV, "- users %d disk %s\n", blkdev->users,
- blkdev->gd->disk_name);
-
- mutex_lock(&blkvsc_mutex);
- spin_lock(&blkdev->lock);
- if (blkdev->users == 1) {
- spin_unlock(&blkdev->lock);
- blkvsc_do_flush(blkdev);
- spin_lock(&blkdev->lock);
- }
-
- blkdev->users--;
-
- spin_unlock(&blkdev->lock);
- mutex_unlock(&blkvsc_mutex);
- return 0;
-}
-
-static unsigned int blkvsc_check_events(struct gendisk *gd,
- unsigned int clearing)
-{
- DPRINT_DBG(BLKVSC_DRV, "- enter\n");
- return DISK_EVENT_MEDIA_CHANGE;
-}
-
-static int blkvsc_revalidate_disk(struct gendisk *gd)
-{
- struct block_device_context *blkdev = gd->private_data;
-
- DPRINT_DBG(BLKVSC_DRV, "- enter\n");
-
- if (blkdev->device_type == DVD_TYPE) {
- blkvsc_do_read_capacity(blkdev);
- set_capacity(blkdev->gd, blkdev->capacity *
- (blkdev->sector_size/512));
- blk_queue_logical_block_size(gd->queue, blkdev->sector_size);
- }
- return 0;
-}
-
-static int blkvsc_getgeo(struct block_device *bd, struct hd_geometry *hg)
-{
- sector_t total_sectors = get_capacity(bd->bd_disk);
- sector_t cylinder_times_heads = 0;
- sector_t temp = 0;
-
- int sectors_per_track = 0;
- int heads = 0;
- int cylinders = 0;
- int rem = 0;
-
- if (total_sectors > (65535 * 16 * 255))
- total_sectors = (65535 * 16 * 255);
-
- if (total_sectors >= (65535 * 16 * 63)) {
- sectors_per_track = 255;
- heads = 16;
-
- cylinder_times_heads = total_sectors;
- /* sector_div stores the quotient in cylinder_times_heads */
- rem = sector_div(cylinder_times_heads, sectors_per_track);
- } else {
- sectors_per_track = 17;
-
- cylinder_times_heads = total_sectors;
- /* sector_div stores the quotient in cylinder_times_heads */
- rem = sector_div(cylinder_times_heads, sectors_per_track);
-
- temp = cylinder_times_heads + 1023;
- /* sector_div stores the quotient in temp */
- rem = sector_div(temp, 1024);
-
- heads = temp;
-
- if (heads < 4)
- heads = 4;
-
-
- if (cylinder_times_heads >= (heads * 1024) || (heads > 16)) {
- sectors_per_track = 31;
- heads = 16;
-
- cylinder_times_heads = total_sectors;
- /*
- * sector_div stores the quotient in
- * cylinder_times_heads
- */
- rem = sector_div(cylinder_times_heads,
- sectors_per_track);
- }
-
- if (cylinder_times_heads >= (heads * 1024)) {
- sectors_per_track = 63;
- heads = 16;
-
- cylinder_times_heads = total_sectors;
- /*
- * sector_div stores the quotient in
- * cylinder_times_heads
- */
- rem = sector_div(cylinder_times_heads,
- sectors_per_track);
- }
- }
-
- temp = cylinder_times_heads;
- /* sector_div stores the quotient in temp */
- rem = sector_div(temp, heads);
- cylinders = temp;
-
- hg->heads = heads;
- hg->sectors = sectors_per_track;
- hg->cylinders = cylinders;
-
- DPRINT_INFO(BLKVSC_DRV, "CHS (%d, %d, %d)", cylinders, heads,
- sectors_per_track);
-
- return 0;
-}
-
-static int blkvsc_ioctl(struct block_device *bd, fmode_t mode,
- unsigned cmd, unsigned long argument)
-{
-/* struct block_device_context *blkdev = bd->bd_disk->private_data; */
- int ret;
-
- switch (cmd) {
- /*
- * TODO: I think there is certain format for HDIO_GET_IDENTITY rather
- * than just a GUID. Commented it out for now.
- */
-#if 0
- case HDIO_GET_IDENTITY:
- DPRINT_INFO(BLKVSC_DRV, "HDIO_GET_IDENTITY\n");
- if (copy_to_user((void __user *)arg, blkdev->device_id,
- blkdev->device_id_len))
- ret = -EFAULT;
- break;
-#endif
- default:
- ret = -EINVAL;
- break;
- }
-
- return ret;
-}
-
-static int __init blkvsc_init(void)
-{
- int ret;
-
- BUILD_BUG_ON(sizeof(sector_t) != 8);
-
- DPRINT_INFO(BLKVSC_DRV, "Blkvsc initializing....");
-
- ret = blkvsc_drv_init(blk_vsc_initialize);
-
- return ret;
-}
-
static void __exit blkvsc_exit(void)
{
blkvsc_drv_exit();
@@ -1489,5 +1018,5 @@
MODULE_LICENSE("GPL");
MODULE_VERSION(HV_DRV_VERSION);
MODULE_DESCRIPTION("Microsoft Hyper-V virtual block driver");
-module_init(blkvsc_init);
+module_init(blkvsc_drv_init);
module_exit(blkvsc_exit);
diff --git a/drivers/staging/hv/channel.c b/drivers/staging/hv/channel.c
index f7ce7d2..f655e59 100644
--- a/drivers/staging/hv/channel.c
+++ b/drivers/staging/hv/channel.c
@@ -18,15 +18,17 @@
* Haiyang Zhang <haiyangz@microsoft.com>
* Hank Janssen <hjanssen@microsoft.com>
*/
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/wait.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/module.h>
-#include "hv_api.h"
-#include "logging.h"
-#include "vmbus_private.h"
+
+#include "hyperv.h"
+#include "hyperv_vmbus.h"
#define NUM_PAGES_SPANNED(addr, len) \
((PAGE_ALIGN(addr + len) >> PAGE_SHIFT) - (addr >> PAGE_SHIFT))
@@ -40,37 +42,6 @@
static void dump_vmbus_channel(struct vmbus_channel *channel);
static void vmbus_setevent(struct vmbus_channel *channel);
-
-#if 0
-static void DumpMonitorPage(struct hv_monitor_page *MonitorPage)
-{
- int i = 0;
- int j = 0;
-
- DPRINT_DBG(VMBUS, "monitorPage - %p, trigger state - %d",
- MonitorPage, MonitorPage->trigger_state);
-
- for (i = 0; i < 4; i++)
- DPRINT_DBG(VMBUS, "trigger group (%d) - %llx", i,
- MonitorPage->trigger_group[i].as_uint64);
-
- for (i = 0; i < 4; i++) {
- for (j = 0; j < 32; j++) {
- DPRINT_DBG(VMBUS, "latency (%d)(%d) - %llx", i, j,
- MonitorPage->latency[i][j]);
- }
- }
- for (i = 0; i < 4; i++) {
- for (j = 0; j < 32; j++) {
- DPRINT_DBG(VMBUS, "param-conn id (%d)(%d) - %d", i, j,
- MonitorPage->parameter[i][j].connectionid.asu32);
- DPRINT_DBG(VMBUS, "param-flag (%d)(%d) - %d", i, j,
- MonitorPage->parameter[i][j].flag_number);
- }
- }
-}
-#endif
-
/*
* vmbus_setevent- Trigger an event notification on the specified
* channel.
@@ -97,28 +68,6 @@
}
}
-#if 0
-static void VmbusChannelClearEvent(struct vmbus_channel *channel)
-{
- struct hv_monitor_page *monitorPage;
-
- if (Channel->offermsg.monitor_allocated) {
- /* Each u32 represents 32 channels */
- sync_clear_bit(Channel->offermsg.child_relid & 31,
- (unsigned long *)vmbus_connection.send_int_page +
- (Channel->offermsg.child_relid >> 5));
-
- monitorPage = (struct hv_monitor_page *)
- vmbus_connection.monitor_pages;
- monitorPage++; /* Get the child to parent monitor page */
-
- sync_clear_bit(Channel->monitor_bit,
- (unsigned long *)&monitorPage->trigger_group
- [Channel->monitor_grp].Pending);
- }
-}
-
-#endif
/*
* vmbus_get_debug_info -Retrieve various channel debug info
*/
@@ -160,8 +109,8 @@
monitorpage->parameter[monitor_group]
[monitor_offset].connectionid.u.id;
- ringbuffer_get_debuginfo(&channel->inbound, &debuginfo->inbound);
- ringbuffer_get_debuginfo(&channel->outbound, &debuginfo->outbound);
+ hv_ringbuffer_get_debuginfo(&channel->inbound, &debuginfo->inbound);
+ hv_ringbuffer_get_debuginfo(&channel->outbound, &debuginfo->outbound);
}
/*
@@ -175,11 +124,7 @@
struct vmbus_channel_msginfo *openInfo = NULL;
void *in, *out;
unsigned long flags;
- int ret, err = 0;
-
- /* Aligned to page size */
- /* ASSERT(!(SendRingBufferSize & (PAGE_SIZE - 1))); */
- /* ASSERT(!(RecvRingBufferSize & (PAGE_SIZE - 1))); */
+ int ret, t, err = 0;
newchannel->onchannel_callback = onchannelcallback;
newchannel->channel_callback_context = context;
@@ -191,7 +136,6 @@
if (!out)
return -ENOMEM;
- /* ASSERT(((unsigned long)out & (PAGE_SIZE-1)) == 0); */
in = (void *)((unsigned long)out + send_ringbuffer_size);
@@ -199,13 +143,16 @@
newchannel->ringbuffer_pagecount = (send_ringbuffer_size +
recv_ringbuffer_size) >> PAGE_SHIFT;
- ret = ringbuffer_init(&newchannel->outbound, out, send_ringbuffer_size);
+ ret = hv_ringbuffer_init(
+ &newchannel->outbound, out, send_ringbuffer_size);
+
if (ret != 0) {
err = ret;
goto errorout;
}
- ret = ringbuffer_init(&newchannel->inbound, in, recv_ringbuffer_size);
+ ret = hv_ringbuffer_init(
+ &newchannel->inbound, in, recv_ringbuffer_size);
if (ret != 0) {
err = ret;
goto errorout;
@@ -213,9 +160,6 @@
/* Establish the gpadl for the ring buffer */
- DPRINT_DBG(VMBUS, "Establishing ring buffer's gpadl for channel %p...",
- newchannel);
-
newchannel->ringbuffer_gpadlhandle = 0;
ret = vmbus_establish_gpadl(newchannel,
@@ -229,16 +173,6 @@
goto errorout;
}
- DPRINT_DBG(VMBUS, "channel %p <relid %d gpadl 0x%x send ring %p "
- "size %d recv ring %p size %d, downstreamoffset %d>",
- newchannel, newchannel->offermsg.child_relid,
- newchannel->ringbuffer_gpadlhandle,
- newchannel->outbound.ring_buffer,
- newchannel->outbound.ring_size,
- newchannel->inbound.ring_buffer,
- newchannel->inbound.ring_size,
- send_ringbuffer_size);
-
/* Create and init the channel open message */
openInfo = kmalloc(sizeof(*openInfo) +
sizeof(struct vmbus_channel_open_channel),
@@ -248,7 +182,7 @@
goto errorout;
}
- init_waitqueue_head(&openInfo->waitevent);
+ init_completion(&openInfo->waitevent);
openMsg = (struct vmbus_channel_open_channel *)openInfo->msg;
openMsg->header.msgtype = CHANNELMSG_OPENCHANNEL;
@@ -272,30 +206,21 @@
&vmbus_connection.chn_msg_list);
spin_unlock_irqrestore(&vmbus_connection.channelmsg_lock, flags);
- DPRINT_DBG(VMBUS, "Sending channel open msg...");
-
ret = vmbus_post_msg(openMsg,
sizeof(struct vmbus_channel_open_channel));
- if (ret != 0) {
- DPRINT_ERR(VMBUS, "unable to open channel - %d", ret);
- goto Cleanup;
- }
- openInfo->wait_condition = 0;
- wait_event_timeout(openInfo->waitevent,
- openInfo->wait_condition,
- msecs_to_jiffies(1000));
- if (openInfo->wait_condition == 0) {
+ if (ret != 0)
+ goto Cleanup;
+
+ t = wait_for_completion_timeout(&openInfo->waitevent, HZ);
+ if (t == 0) {
err = -ETIMEDOUT;
goto errorout;
}
- if (openInfo->response.open_result.status == 0)
- DPRINT_INFO(VMBUS, "channel <%p> open success!!", newchannel);
- else
- DPRINT_INFO(VMBUS, "channel <%p> open failed - %d!!",
- newchannel, openInfo->response.open_result.status);
+ if (openInfo->response.open_result.status)
+ err = openInfo->response.open_result.status;
Cleanup:
spin_lock_irqsave(&vmbus_connection.channelmsg_lock, flags);
@@ -303,11 +228,11 @@
spin_unlock_irqrestore(&vmbus_connection.channelmsg_lock, flags);
kfree(openInfo);
- return 0;
+ return err;
errorout:
- ringbuffer_cleanup(&newchannel->outbound);
- ringbuffer_cleanup(&newchannel->inbound);
+ hv_ringbuffer_cleanup(&newchannel->outbound);
+ hv_ringbuffer_cleanup(&newchannel->inbound);
free_pages((unsigned long)out,
get_order(send_ringbuffer_size + recv_ringbuffer_size));
kfree(openInfo);
@@ -326,6 +251,7 @@
pfncount = (len - sizeof(struct vmbus_channel_gpadl_body)) /
sizeof(u64);
+
DPRINT_DBG(VMBUS, "gpadl body - len %d pfn count %d", len, pfncount);
for (i = 0; i < pfncount; i++)
@@ -377,9 +303,6 @@
int pfnsum, pfncount, pfnleft, pfncurr, pfnsize;
- /* ASSERT((kbuffer & (PAGE_SIZE-1)) == 0); */
- /* ASSERT((Size & (PAGE_SIZE-1)) == 0); */
-
pagecount = size >> PAGE_SHIFT;
pfn = virt_to_phys(kbuffer) >> PAGE_SHIFT;
@@ -508,6 +431,7 @@
u32 next_gpadl_handle;
unsigned long flags;
int ret = 0;
+ int t;
next_gpadl_handle = atomic_read(&vmbus_connection.next_gpadl_handle);
atomic_inc(&vmbus_connection.next_gpadl_handle);
@@ -516,7 +440,7 @@
if (ret)
return ret;
- init_waitqueue_head(&msginfo->waitevent);
+ init_completion(&msginfo->waitevent);
gpadlmsg = (struct vmbus_channel_gpadl_header *)msginfo->msg;
gpadlmsg->header.msgtype = CHANNELMSG_GPADL_HEADER;
@@ -530,19 +454,11 @@
&vmbus_connection.chn_msg_list);
spin_unlock_irqrestore(&vmbus_connection.channelmsg_lock, flags);
- DPRINT_DBG(VMBUS, "buffer %p, size %d msg cnt %d",
- kbuffer, size, msgcount);
- DPRINT_DBG(VMBUS, "Sending GPADL Header - len %zd",
- msginfo->msgsize - sizeof(*msginfo));
-
- msginfo->wait_condition = 0;
ret = vmbus_post_msg(gpadlmsg, msginfo->msgsize -
sizeof(*msginfo));
- if (ret != 0) {
- DPRINT_ERR(VMBUS, "Unable to open channel - %d", ret);
+ if (ret != 0)
goto Cleanup;
- }
if (msgcount > 1) {
list_for_each(curr, &msginfo->submsglist) {
@@ -556,10 +472,6 @@
CHANNELMSG_GPADL_BODY;
gpadl_body->gpadl = next_gpadl_handle;
- DPRINT_DBG(VMBUS, "Sending GPADL Body - len %zd",
- submsginfo->msgsize -
- sizeof(*submsginfo));
-
dump_gpadl_body(gpadl_body, submsginfo->msgsize -
sizeof(*submsginfo));
ret = vmbus_post_msg(gpadl_body,
@@ -570,19 +482,11 @@
}
}
- wait_event_timeout(msginfo->waitevent,
- msginfo->wait_condition,
- msecs_to_jiffies(1000));
- BUG_ON(msginfo->wait_condition == 0);
+ t = wait_for_completion_timeout(&msginfo->waitevent, HZ);
+ BUG_ON(t == 0);
/* At this point, we received the gpadl created msg */
- DPRINT_DBG(VMBUS, "Received GPADL created "
- "(relid %d, status %d handle %x)",
- channel->offermsg.child_relid,
- msginfo->response.gpadl_created.creation_status,
- gpadlmsg->gpadl);
-
*gpadl_handle = gpadlmsg->gpadl;
Cleanup:
@@ -603,7 +507,7 @@
struct vmbus_channel_gpadl_teardown *msg;
struct vmbus_channel_msginfo *info;
unsigned long flags;
- int ret;
+ int ret, t;
/* ASSERT(gpadl_handle != 0); */
@@ -612,7 +516,7 @@
if (!info)
return -ENOMEM;
- init_waitqueue_head(&info->waitevent);
+ init_completion(&info->waitevent);
msg = (struct vmbus_channel_gpadl_teardown *)info->msg;
@@ -624,14 +528,12 @@
list_add_tail(&info->msglistentry,
&vmbus_connection.chn_msg_list);
spin_unlock_irqrestore(&vmbus_connection.channelmsg_lock, flags);
- info->wait_condition = 0;
ret = vmbus_post_msg(msg,
sizeof(struct vmbus_channel_gpadl_teardown));
BUG_ON(ret != 0);
- wait_event_timeout(info->waitevent,
- info->wait_condition, msecs_to_jiffies(1000));
- BUG_ON(info->wait_condition == 0);
+ t = wait_for_completion_timeout(&info->waitevent, HZ);
+ BUG_ON(t == 0);
/* Received a torndown response */
spin_lock_irqsave(&vmbus_connection.channelmsg_lock, flags);
@@ -681,8 +583,8 @@
/* TODO: Send a msg to release the childRelId */
/* Cleanup the ring buffers for this channel */
- ringbuffer_cleanup(&channel->outbound);
- ringbuffer_cleanup(&channel->inbound);
+ hv_ringbuffer_cleanup(&channel->outbound);
+ hv_ringbuffer_cleanup(&channel->inbound);
free_pages((unsigned long)channel->ringbuffer_pages,
get_order(channel->ringbuffer_pagecount * PAGE_SIZE));
@@ -730,13 +632,8 @@
u64 aligned_data = 0;
int ret;
- DPRINT_DBG(VMBUS, "channel %p buffer %p len %d",
- channel, buffer, bufferlen);
-
dump_vmbus_channel(channel);
- /* ASSERT((packetLenAligned - packetLen) < sizeof(u64)); */
-
/* Setup the descriptor */
desc.type = type; /* VmbusPacketTypeDataInBand; */
desc.flags = flags; /* VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED; */
@@ -751,10 +648,10 @@
sg_set_buf(&bufferlist[2], &aligned_data,
packetlen_aligned - packetlen);
- ret = ringbuffer_write(&channel->outbound, bufferlist, 3);
+ ret = hv_ringbuffer_write(&channel->outbound, bufferlist, 3);
/* TODO: We should determine if this is optional */
- if (ret == 0 && !get_ringbuffer_interrupt_mask(&channel->outbound))
+ if (ret == 0 && !hv_get_ringbuffer_interrupt_mask(&channel->outbound))
vmbus_setevent(channel);
return ret;
@@ -794,8 +691,6 @@
packetlen = descsize + bufferlen;
packetlen_aligned = ALIGN(packetlen, sizeof(u64));
- /* ASSERT((packetLenAligned - packetLen) < sizeof(u64)); */
-
/* Setup the descriptor */
desc.type = VM_PKT_DATA_USING_GPA_DIRECT;
desc.flags = VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED;
@@ -816,10 +711,10 @@
sg_set_buf(&bufferlist[2], &aligned_data,
packetlen_aligned - packetlen);
- ret = ringbuffer_write(&channel->outbound, bufferlist, 3);
+ ret = hv_ringbuffer_write(&channel->outbound, bufferlist, 3);
/* TODO: We should determine if this is optional */
- if (ret == 0 && !get_ringbuffer_interrupt_mask(&channel->outbound))
+ if (ret == 0 && !hv_get_ringbuffer_interrupt_mask(&channel->outbound))
vmbus_setevent(channel);
return ret;
@@ -846,10 +741,6 @@
dump_vmbus_channel(channel);
- DPRINT_DBG(VMBUS, "data buffer - offset %u len %u pfn count %u",
- multi_pagebuffer->offset,
- multi_pagebuffer->len, pfncount);
-
if ((pfncount < 0) || (pfncount > MAX_MULTIPAGE_BUFFER_COUNT))
return -EINVAL;
@@ -863,7 +754,6 @@
packetlen = descsize + bufferlen;
packetlen_aligned = ALIGN(packetlen, sizeof(u64));
- /* ASSERT((packetLenAligned - packetLen) < sizeof(u64)); */
/* Setup the descriptor */
desc.type = VM_PKT_DATA_USING_GPA_DIRECT;
@@ -885,10 +775,10 @@
sg_set_buf(&bufferlist[2], &aligned_data,
packetlen_aligned - packetlen);
- ret = ringbuffer_write(&channel->outbound, bufferlist, 3);
+ ret = hv_ringbuffer_write(&channel->outbound, bufferlist, 3);
/* TODO: We should determine if this is optional */
- if (ret == 0 && !get_ringbuffer_interrupt_mask(&channel->outbound))
+ if (ret == 0 && !hv_get_ringbuffer_interrupt_mask(&channel->outbound))
vmbus_setevent(channel);
return ret;
@@ -922,32 +812,22 @@
spin_lock_irqsave(&channel->inbound_lock, flags);
- ret = ringbuffer_peek(&channel->inbound, &desc,
+ ret = hv_ringbuffer_peek(&channel->inbound, &desc,
sizeof(struct vmpacket_descriptor));
if (ret != 0) {
spin_unlock_irqrestore(&channel->inbound_lock, flags);
-
- /* DPRINT_DBG(VMBUS, "nothing to read!!"); */
return 0;
}
- /* VmbusChannelClearEvent(Channel); */
-
packetlen = desc.len8 << 3;
userlen = packetlen - (desc.offset8 << 3);
- /* ASSERT(userLen > 0); */
-
- DPRINT_DBG(VMBUS, "packet received on channel %p relid %d <type %d "
- "flag %d tid %llx pktlen %d datalen %d> ",
- channel, channel->offermsg.child_relid, desc.type,
- desc.flags, desc.trans_id, packetlen, userlen);
*buffer_actual_len = userlen;
if (userlen > bufferlen) {
spin_unlock_irqrestore(&channel->inbound_lock, flags);
- DPRINT_ERR(VMBUS, "buffer too small - got %d needs %d",
+ pr_err("Buffer too small - got %d needs %d\n",
bufferlen, userlen);
return -1;
}
@@ -955,7 +835,7 @@
*requestid = desc.trans_id;
/* Copy over the packet to the user buffer */
- ret = ringbuffer_read(&channel->inbound, buffer, userlen,
+ ret = hv_ringbuffer_read(&channel->inbound, buffer, userlen,
(desc.offset8 << 3));
spin_unlock_irqrestore(&channel->inbound_lock, flags);
@@ -982,39 +862,32 @@
spin_lock_irqsave(&channel->inbound_lock, flags);
- ret = ringbuffer_peek(&channel->inbound, &desc,
+ ret = hv_ringbuffer_peek(&channel->inbound, &desc,
sizeof(struct vmpacket_descriptor));
if (ret != 0) {
spin_unlock_irqrestore(&channel->inbound_lock, flags);
-
- /* DPRINT_DBG(VMBUS, "nothing to read!!"); */
return 0;
}
- /* VmbusChannelClearEvent(Channel); */
packetlen = desc.len8 << 3;
userlen = packetlen - (desc.offset8 << 3);
- DPRINT_DBG(VMBUS, "packet received on channel %p relid %d <type %d "
- "flag %d tid %llx pktlen %d datalen %d> ",
- channel, channel->offermsg.child_relid, desc.type,
- desc.flags, desc.trans_id, packetlen, userlen);
-
*buffer_actual_len = packetlen;
if (packetlen > bufferlen) {
spin_unlock_irqrestore(&channel->inbound_lock, flags);
- DPRINT_ERR(VMBUS, "buffer too small - needed %d bytes but "
- "got space for only %d bytes", packetlen, bufferlen);
+ pr_err("Buffer too small - needed %d bytes but "
+ "got space for only %d bytes\n",
+ packetlen, bufferlen);
return -2;
}
*requestid = desc.trans_id;
/* Copy over the entire packet to the user buffer */
- ret = ringbuffer_read(&channel->inbound, buffer, packetlen, 0);
+ ret = hv_ringbuffer_read(&channel->inbound, buffer, packetlen, 0);
spin_unlock_irqrestore(&channel->inbound_lock, flags);
return 0;
@@ -1027,7 +900,6 @@
void vmbus_onchannel_event(struct vmbus_channel *channel)
{
dump_vmbus_channel(channel);
- /* ASSERT(Channel->OnChannelCallback); */
channel->onchannel_callback(channel->channel_callback_context);
@@ -1051,6 +923,6 @@
static void dump_vmbus_channel(struct vmbus_channel *channel)
{
DPRINT_DBG(VMBUS, "Channel (%d)", channel->offermsg.child_relid);
- dump_ring_info(&channel->outbound, "Outbound ");
- dump_ring_info(&channel->inbound, "Inbound ");
+ hv_dump_ring_info(&channel->outbound, "Outbound ");
+ hv_dump_ring_info(&channel->inbound, "Inbound ");
}
diff --git a/drivers/staging/hv/channel.h b/drivers/staging/hv/channel.h
deleted file mode 100644
index de4f867..0000000
--- a/drivers/staging/hv/channel.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- *
- * Copyright (c) 2009, Microsoft Corporation.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
- * Place - Suite 330, Boston, MA 02111-1307 USA.
- *
- * Authors:
- * Haiyang Zhang <haiyangz@microsoft.com>
- * Hank Janssen <hjanssen@microsoft.com>
- *
- */
-
-
-#ifndef _CHANNEL_H_
-#define _CHANNEL_H_
-
-#include "channel_mgmt.h"
-
-/* The format must be the same as struct vmdata_gpa_direct */
-struct vmbus_channel_packet_page_buffer {
- u16 type;
- u16 dataoffset8;
- u16 length8;
- u16 flags;
- u64 transactionid;
- u32 reserved;
- u32 rangecount;
- struct hv_page_buffer range[MAX_PAGE_BUFFER_COUNT];
-} __packed;
-
-/* The format must be the same as struct vmdata_gpa_direct */
-struct vmbus_channel_packet_multipage_buffer {
- u16 type;
- u16 dataoffset8;
- u16 length8;
- u16 flags;
- u64 transactionid;
- u32 reserved;
- u32 rangecount; /* Always 1 in this case */
- struct hv_multipage_buffer range;
-} __packed;
-
-
-extern int vmbus_open(struct vmbus_channel *channel,
- u32 send_ringbuffersize,
- u32 recv_ringbuffersize,
- void *userdata,
- u32 userdatalen,
- void(*onchannel_callback)(void *context),
- void *context);
-
-extern void vmbus_close(struct vmbus_channel *channel);
-
-extern int vmbus_sendpacket(struct vmbus_channel *channel,
- const void *buffer,
- u32 bufferLen,
- u64 requestid,
- enum vmbus_packet_type type,
- u32 flags);
-
-extern int vmbus_sendpacket_pagebuffer(struct vmbus_channel *channel,
- struct hv_page_buffer pagebuffers[],
- u32 pagecount,
- void *buffer,
- u32 bufferlen,
- u64 requestid);
-
-extern int vmbus_sendpacket_multipagebuffer(struct vmbus_channel *channel,
- struct hv_multipage_buffer *mpb,
- void *buffer,
- u32 bufferlen,
- u64 requestid);
-
-extern int vmbus_establish_gpadl(struct vmbus_channel *channel,
- void *kbuffer,
- u32 size,
- u32 *gpadl_handle);
-
-extern int vmbus_teardown_gpadl(struct vmbus_channel *channel,
- u32 gpadl_handle);
-
-extern int vmbus_recvpacket(struct vmbus_channel *channel,
- void *buffer,
- u32 bufferlen,
- u32 *buffer_actual_len,
- u64 *requestid);
-
-extern int vmbus_recvpacket_raw(struct vmbus_channel *channel,
- void *buffer,
- u32 bufferlen,
- u32 *buffer_actual_len,
- u64 *requestid);
-
-extern void vmbus_onchannel_event(struct vmbus_channel *channel);
-
-extern void vmbus_get_debug_info(struct vmbus_channel *channel,
- struct vmbus_channel_debug_info *debug);
-
-extern void vmbus_ontimer(unsigned long data);
-
-#endif /* _CHANNEL_H_ */
diff --git a/drivers/staging/hv/channel_mgmt.c b/drivers/staging/hv/channel_mgmt.c
index 06b5732..957d61e 100644
--- a/drivers/staging/hv/channel_mgmt.c
+++ b/drivers/staging/hv/channel_mgmt.c
@@ -18,6 +18,8 @@
* Haiyang Zhang <haiyangz@microsoft.com>
* Hank Janssen <hjanssen@microsoft.com>
*/
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/wait.h>
@@ -26,21 +28,20 @@
#include <linux/list.h>
#include <linux/module.h>
#include <linux/completion.h>
-#include "hv_api.h"
-#include "logging.h"
-#include "vmbus_private.h"
-#include "utils.h"
+
+#include "hyperv.h"
+#include "hyperv_vmbus.h"
struct vmbus_channel_message_table_entry {
- enum vmbus_channel_message_type messageType;
- void (*messageHandler)(struct vmbus_channel_message_header *msg);
+ enum vmbus_channel_message_type message_type;
+ void (*message_handler)(struct vmbus_channel_message_header *msg);
};
#define MAX_MSG_TYPES 4
#define MAX_NUM_DEVICE_CLASSES_SUPPORTED 8
static const struct hv_guid
- gSupportedDeviceClasses[MAX_NUM_DEVICE_CLASSES_SUPPORTED] = {
+ supported_device_classes[MAX_NUM_DEVICE_CLASSES_SUPPORTED] = {
/* {ba6163d9-04a1-4d29-b605-72e2ffb1dc7f} */
/* Storage - SCSI */
{
@@ -180,6 +181,24 @@
struct icmsg_hdr *icmsghdrp;
struct icmsg_negotiate *negop = NULL;
+ if (channel->util_index >= 0) {
+ /*
+ * This is a properly initialized util channel.
+ * Route this callback appropriately and setup state
+ * so that we don't need to reroute again.
+ */
+ if (hv_cb_utils[channel->util_index].callback != NULL) {
+ /*
+ * The util driver has established a handler for
+ * this service; do the magic.
+ */
+ channel->onchannel_callback =
+ hv_cb_utils[channel->util_index].callback;
+ (hv_cb_utils[channel->util_index].callback)(channel);
+ return;
+ }
+ }
+
buflen = PAGE_SIZE;
buf = kmalloc(buflen, GFP_ATOMIC);
@@ -216,7 +235,6 @@
0x31, 0x60, 0x0B, 0X0E, 0x13, 0x52, 0x34, 0x49,
0x81, 0x8B, 0x38, 0XD9, 0x0C, 0xED, 0x39, 0xDB
},
- .callback = chn_cb_negotiate,
.log_msg = "Shutdown channel functionality initialized"
},
@@ -228,7 +246,6 @@
0x30, 0xe6, 0x27, 0x95, 0xae, 0xd0, 0x7b, 0x49,
0xad, 0xce, 0xe8, 0x0a, 0xb0, 0x17, 0x5c, 0xaf
},
- .callback = chn_cb_negotiate,
.log_msg = "Timesync channel functionality initialized"
},
/* {57164f39-9115-4e78-ab55-382f3bd5422d} */
@@ -239,7 +256,6 @@
0x39, 0x4f, 0x16, 0x57, 0x15, 0x91, 0x78, 0x4e,
0xab, 0x55, 0x38, 0x2f, 0x3b, 0xd5, 0x42, 0x2d
},
- .callback = chn_cb_negotiate,
.log_msg = "Heartbeat channel functionality initialized"
},
/* {A9A0F4E7-5A45-4d96-B827-8A841E8C03E6} */
@@ -249,7 +265,6 @@
0xe7, 0xf4, 0xa0, 0xa9, 0x45, 0x5a, 0x96, 0x4d,
0xb8, 0x27, 0x8a, 0x84, 0x1e, 0x8c, 0x3, 0xe6
},
- .callback = chn_cb_negotiate,
.log_msg = "KVP channel functionality initialized"
},
};
@@ -290,9 +305,7 @@
struct vmbus_channel,
work);
- DPRINT_DBG(VMBUS, "releasing channel (%p)", channel);
destroy_workqueue(channel->controlwq);
- DPRINT_DBG(VMBUS, "channel released (%p)", channel);
kfree(channel);
}
@@ -314,22 +327,6 @@
}
-DECLARE_COMPLETION(hv_channel_ready);
-
-/*
- * Count initialized channels, and ensure all channels are ready when hv_vmbus
- * module loading completes.
- */
-static void count_hv_channel(void)
-{
- static int counter;
- unsigned long flags;
-
- spin_lock_irqsave(&vmbus_connection.channel_lock, flags);
- if (++counter == MAX_MSG_TYPES)
- complete(&hv_channel_ready);
- spin_unlock_irqrestore(&vmbus_connection.channel_lock, flags);
-}
/*
* vmbus_process_rescind_offer -
@@ -384,8 +381,6 @@
spin_unlock_irqrestore(&vmbus_connection.channel_lock, flags);
if (!fnew) {
- DPRINT_DBG(VMBUS, "Ignoring duplicate offer for relid (%d)",
- newchannel->offermsg.child_relid);
free_channel(newchannel);
return;
}
@@ -400,9 +395,6 @@
&newchannel->offermsg.offer.if_instance,
newchannel);
- DPRINT_DBG(VMBUS, "child device object allocated - %p",
- newchannel->device_obj);
-
/*
* Add the new device to the bus. This will kick off device-driver
* binding which eventually invokes the device driver's AddDevice()
@@ -410,8 +402,7 @@
*/
ret = vmbus_child_device_register(newchannel->device_obj);
if (ret != 0) {
- DPRINT_ERR(VMBUS,
- "unable to add child device object (relid %d)",
+ pr_err("unable to add child device object (relid %d)\n",
newchannel->offermsg.child_relid);
spin_lock_irqsave(&vmbus_connection.channel_lock, flags);
@@ -426,6 +417,7 @@
* can cleanup properly
*/
newchannel->state = CHANNEL_OPEN_STATE;
+ newchannel->util_index = -1; /* Invalid index */
/* Open IC channels */
for (cnt = 0; cnt < MAX_MSG_TYPES; cnt++) {
@@ -434,12 +426,13 @@
sizeof(struct hv_guid)) == 0 &&
vmbus_open(newchannel, 2 * PAGE_SIZE,
2 * PAGE_SIZE, NULL, 0,
- hv_cb_utils[cnt].callback,
+ chn_cb_negotiate,
newchannel) == 0) {
hv_cb_utils[cnt].channel = newchannel;
- DPRINT_INFO(VMBUS, "%s",
- hv_cb_utils[cnt].log_msg);
- count_hv_channel();
+ newchannel->util_index = cnt;
+
+ pr_info("%s\n", hv_cb_utils[cnt].log_msg);
+
}
}
}
@@ -464,55 +457,26 @@
offer = (struct vmbus_channel_offer_channel *)hdr;
for (i = 0; i < MAX_NUM_DEVICE_CLASSES_SUPPORTED; i++) {
if (memcmp(&offer->offer.if_type,
- &gSupportedDeviceClasses[i], sizeof(struct hv_guid)) == 0) {
+ &supported_device_classes[i],
+ sizeof(struct hv_guid)) == 0) {
fsupported = 1;
break;
}
}
- if (!fsupported) {
- DPRINT_DBG(VMBUS, "Ignoring channel offer notification for "
- "child relid %d", offer->child_relid);
+ if (!fsupported)
return;
- }
guidtype = &offer->offer.if_type;
guidinstance = &offer->offer.if_instance;
- DPRINT_INFO(VMBUS, "Channel offer notification - "
- "child relid %d monitor id %d allocated %d, "
- "type {%02x%02x%02x%02x-%02x%02x-%02x%02x-"
- "%02x%02x%02x%02x%02x%02x%02x%02x} "
- "instance {%02x%02x%02x%02x-%02x%02x-%02x%02x-"
- "%02x%02x%02x%02x%02x%02x%02x%02x}",
- offer->child_relid, offer->monitorid,
- offer->monitor_allocated,
- guidtype->data[3], guidtype->data[2],
- guidtype->data[1], guidtype->data[0],
- guidtype->data[5], guidtype->data[4],
- guidtype->data[7], guidtype->data[6],
- guidtype->data[8], guidtype->data[9],
- guidtype->data[10], guidtype->data[11],
- guidtype->data[12], guidtype->data[13],
- guidtype->data[14], guidtype->data[15],
- guidinstance->data[3], guidinstance->data[2],
- guidinstance->data[1], guidinstance->data[0],
- guidinstance->data[5], guidinstance->data[4],
- guidinstance->data[7], guidinstance->data[6],
- guidinstance->data[8], guidinstance->data[9],
- guidinstance->data[10], guidinstance->data[11],
- guidinstance->data[12], guidinstance->data[13],
- guidinstance->data[14], guidinstance->data[15]);
-
/* Allocate the channel object and save this offer. */
newchannel = alloc_channel();
if (!newchannel) {
- DPRINT_ERR(VMBUS, "unable to allocate channel object");
+ pr_err("Unable to allocate channel object\n");
return;
}
- DPRINT_DBG(VMBUS, "channel object allocated - %p", newchannel);
-
memcpy(&newchannel->offermsg, offer,
sizeof(struct vmbus_channel_offer_channel));
newchannel->monitor_grp = (u8)offer->monitorid / 32;
@@ -535,11 +499,10 @@
rescind = (struct vmbus_channel_rescind_offer *)hdr;
channel = relid2channel(rescind->child_relid);
- if (channel == NULL) {
- DPRINT_DBG(VMBUS, "channel not found for relId %d",
- rescind->child_relid);
+
+ if (channel == NULL)
+ /* Just return here, no channel found */
return;
- }
/* work is initialized for vmbus_process_rescind_offer() from
* vmbus_process_offer() where the channel got created */
@@ -573,7 +536,6 @@
unsigned long flags;
result = (struct vmbus_channel_open_result *)hdr;
- DPRINT_DBG(VMBUS, "vmbus open result - %d", result->status);
/*
* Find the open msg, copy the result and signal/unblock the wait event
@@ -592,9 +554,9 @@
openmsg->openid == result->openid) {
memcpy(&msginfo->response.open_result,
result,
- sizeof(struct vmbus_channel_open_result));
- msginfo->wait_condition = 1;
- wake_up(&msginfo->waitevent);
+ sizeof(
+ struct vmbus_channel_open_result));
+ complete(&msginfo->waitevent);
break;
}
}
@@ -618,8 +580,6 @@
unsigned long flags;
gpadlcreated = (struct vmbus_channel_gpadl_created *)hdr;
- DPRINT_DBG(VMBUS, "vmbus gpadl created result - %d",
- gpadlcreated->creation_status);
/*
* Find the establish msg, copy the result and signal/unblock the wait
@@ -641,9 +601,9 @@
(gpadlcreated->gpadl == gpadlheader->gpadl)) {
memcpy(&msginfo->response.gpadl_created,
gpadlcreated,
- sizeof(struct vmbus_channel_gpadl_created));
- msginfo->wait_condition = 1;
- wake_up(&msginfo->waitevent);
+ sizeof(
+ struct vmbus_channel_gpadl_created));
+ complete(&msginfo->waitevent);
break;
}
}
@@ -686,9 +646,9 @@
if (gpadl_torndown->gpadl == gpadl_teardown->gpadl) {
memcpy(&msginfo->response.gpadl_torndown,
gpadl_torndown,
- sizeof(struct vmbus_channel_gpadl_torndown));
- msginfo->wait_condition = 1;
- wake_up(&msginfo->waitevent);
+ sizeof(
+ struct vmbus_channel_gpadl_torndown));
+ complete(&msginfo->waitevent);
break;
}
}
@@ -727,8 +687,7 @@
memcpy(&msginfo->response.version_response,
version_response,
sizeof(struct vmbus_channel_version_response));
- msginfo->wait_condition = 1;
- wake_up(&msginfo->waitevent);
+ complete(&msginfo->waitevent);
}
}
spin_unlock_irqrestore(&vmbus_connection.channelmsg_lock, flags);
@@ -736,7 +695,7 @@
/* Channel message dispatch table */
static struct vmbus_channel_message_table_entry
- gChannelMessageTable[CHANNELMSG_COUNT] = {
+ channel_message_table[CHANNELMSG_COUNT] = {
{CHANNELMSG_INVALID, NULL},
{CHANNELMSG_OFFERCHANNEL, vmbus_onoffer},
{CHANNELMSG_RESCIND_CHANNELOFFER, vmbus_onoffer_rescind},
@@ -770,22 +729,18 @@
hdr = (struct vmbus_channel_message_header *)msg->u.payload;
size = msg->header.payload_size;
- DPRINT_DBG(VMBUS, "message type %d size %d", hdr->msgtype, size);
-
if (hdr->msgtype >= CHANNELMSG_COUNT) {
- DPRINT_ERR(VMBUS,
- "Received invalid channel message type %d size %d",
+ pr_err("Received invalid channel message type %d size %d\n",
hdr->msgtype, size);
print_hex_dump_bytes("", DUMP_PREFIX_NONE,
(unsigned char *)msg->u.payload, size);
return;
}
- if (gChannelMessageTable[hdr->msgtype].messageHandler)
- gChannelMessageTable[hdr->msgtype].messageHandler(hdr);
+ if (channel_message_table[hdr->msgtype].message_handler)
+ channel_message_table[hdr->msgtype].message_handler(hdr);
else
- DPRINT_ERR(VMBUS, "Unhandled channel message type %d",
- hdr->msgtype);
+ pr_err("Unhandled channel message type %d\n", hdr->msgtype);
}
/*
@@ -795,7 +750,7 @@
{
struct vmbus_channel_message_header *msg;
struct vmbus_channel_msginfo *msginfo;
- int ret;
+ int ret, t;
msginfo = kmalloc(sizeof(*msginfo) +
sizeof(struct vmbus_channel_message_header),
@@ -803,7 +758,7 @@
if (!msginfo)
return -ENOMEM;
- init_waitqueue_head(&msginfo->waitevent);
+ init_completion(&msginfo->waitevent);
msg = (struct vmbus_channel_message_header *)msginfo->msg;
@@ -813,15 +768,13 @@
ret = vmbus_post_msg(msg,
sizeof(struct vmbus_channel_message_header));
if (ret != 0) {
- DPRINT_ERR(VMBUS, "Unable to request offers - %d", ret);
+ pr_err("Unable to request offers - %d\n", ret);
goto cleanup;
}
- msginfo->wait_condition = 0;
- wait_event_timeout(msginfo->waitevent, msginfo->wait_condition,
- msecs_to_jiffies(1000));
- if (msginfo->wait_condition == 0) {
+ t = wait_for_completion_timeout(&msginfo->waitevent, HZ);
+ if (t == 0) {
ret = -ETIMEDOUT;
goto cleanup;
}
@@ -834,38 +787,4 @@
return ret;
}
-/*
- * vmbus_release_unattached_channels - Release channels that are
- * unattached/unconnected ie (no drivers associated)
- */
-void vmbus_release_unattached_channels(void)
-{
- struct vmbus_channel *channel, *pos;
- struct vmbus_channel *start = NULL;
- unsigned long flags;
-
- spin_lock_irqsave(&vmbus_connection.channel_lock, flags);
-
- list_for_each_entry_safe(channel, pos, &vmbus_connection.chn_list,
- listentry) {
- if (channel == start)
- break;
-
- if (!channel->device_obj->drv) {
- list_del(&channel->listentry);
- DPRINT_INFO(VMBUS,
- "Releasing unattached device object %p",
- channel->device_obj);
-
- vmbus_child_device_unregister(channel->device_obj);
- free_channel(channel);
- } else {
- if (!start)
- start = channel;
- }
- }
-
- spin_unlock_irqrestore(&vmbus_connection.channel_lock, flags);
-}
-
/* eof */
diff --git a/drivers/staging/hv/channel_mgmt.h b/drivers/staging/hv/channel_mgmt.h
deleted file mode 100644
index 96f74e2..0000000
--- a/drivers/staging/hv/channel_mgmt.h
+++ /dev/null
@@ -1,320 +0,0 @@
-/*
- *
- * Copyright (c) 2009, Microsoft Corporation.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
- * Place - Suite 330, Boston, MA 02111-1307 USA.
- *
- * Authors:
- * Haiyang Zhang <haiyangz@microsoft.com>
- * Hank Janssen <hjanssen@microsoft.com>
- *
- */
-
-
-#ifndef _CHANNEL_MGMT_H_
-#define _CHANNEL_MGMT_H_
-
-#include <linux/list.h>
-#include <linux/timer.h>
-#include <linux/workqueue.h>
-#include "ring_buffer.h"
-#include "vmbus_channel_interface.h"
-#include "vmbus_packet_format.h"
-
-/* Version 1 messages */
-enum vmbus_channel_message_type {
- CHANNELMSG_INVALID = 0,
- CHANNELMSG_OFFERCHANNEL = 1,
- CHANNELMSG_RESCIND_CHANNELOFFER = 2,
- CHANNELMSG_REQUESTOFFERS = 3,
- CHANNELMSG_ALLOFFERS_DELIVERED = 4,
- CHANNELMSG_OPENCHANNEL = 5,
- CHANNELMSG_OPENCHANNEL_RESULT = 6,
- CHANNELMSG_CLOSECHANNEL = 7,
- CHANNELMSG_GPADL_HEADER = 8,
- CHANNELMSG_GPADL_BODY = 9,
- CHANNELMSG_GPADL_CREATED = 10,
- CHANNELMSG_GPADL_TEARDOWN = 11,
- CHANNELMSG_GPADL_TORNDOWN = 12,
- CHANNELMSG_RELID_RELEASED = 13,
- CHANNELMSG_INITIATE_CONTACT = 14,
- CHANNELMSG_VERSION_RESPONSE = 15,
- CHANNELMSG_UNLOAD = 16,
-#ifdef VMBUS_FEATURE_PARENT_OR_PEER_MEMORY_MAPPED_INTO_A_CHILD
- CHANNELMSG_VIEWRANGE_ADD = 17,
- CHANNELMSG_VIEWRANGE_REMOVE = 18,
-#endif
- CHANNELMSG_COUNT
-};
-
-struct vmbus_channel_message_header {
- enum vmbus_channel_message_type msgtype;
- u32 padding;
-} __packed;
-
-/* Query VMBus Version parameters */
-struct vmbus_channel_query_vmbus_version {
- struct vmbus_channel_message_header header;
- u32 version;
-} __packed;
-
-/* VMBus Version Supported parameters */
-struct vmbus_channel_version_supported {
- struct vmbus_channel_message_header header;
- bool version_supported;
-} __packed;
-
-/* Offer Channel parameters */
-struct vmbus_channel_offer_channel {
- struct vmbus_channel_message_header header;
- struct vmbus_channel_offer offer;
- u32 child_relid;
- u8 monitorid;
- bool monitor_allocated;
-} __packed;
-
-/* Rescind Offer parameters */
-struct vmbus_channel_rescind_offer {
- struct vmbus_channel_message_header header;
- u32 child_relid;
-} __packed;
-
-/*
- * Request Offer -- no parameters, SynIC message contains the partition ID
- * Set Snoop -- no parameters, SynIC message contains the partition ID
- * Clear Snoop -- no parameters, SynIC message contains the partition ID
- * All Offers Delivered -- no parameters, SynIC message contains the partition
- * ID
- * Flush Client -- no parameters, SynIC message contains the partition ID
- */
-
-/* Open Channel parameters */
-struct vmbus_channel_open_channel {
- struct vmbus_channel_message_header header;
-
- /* Identifies the specific VMBus channel that is being opened. */
- u32 child_relid;
-
- /* ID making a particular open request at a channel offer unique. */
- u32 openid;
-
- /* GPADL for the channel's ring buffer. */
- u32 ringbuffer_gpadlhandle;
-
- /* GPADL for the channel's server context save area. */
- u32 server_contextarea_gpadlhandle;
-
- /*
- * The upstream ring buffer begins at offset zero in the memory
- * described by RingBufferGpadlHandle. The downstream ring buffer
- * follows it at this offset (in pages).
- */
- u32 downstream_ringbuffer_pageoffset;
-
- /* User-specific data to be passed along to the server endpoint. */
- unsigned char userdata[MAX_USER_DEFINED_BYTES];
-} __packed;
-
-/* Open Channel Result parameters */
-struct vmbus_channel_open_result {
- struct vmbus_channel_message_header header;
- u32 child_relid;
- u32 openid;
- u32 status;
-} __packed;
-
-/* Close channel parameters; */
-struct vmbus_channel_close_channel {
- struct vmbus_channel_message_header header;
- u32 child_relid;
-} __packed;
-
-/* Channel Message GPADL */
-#define GPADL_TYPE_RING_BUFFER 1
-#define GPADL_TYPE_SERVER_SAVE_AREA 2
-#define GPADL_TYPE_TRANSACTION 8
-
-/*
- * The number of PFNs in a GPADL message is defined by the number of
- * pages that would be spanned by ByteCount and ByteOffset. If the
- * implied number of PFNs won't fit in this packet, there will be a
- * follow-up packet that contains more.
- */
-struct vmbus_channel_gpadl_header {
- struct vmbus_channel_message_header header;
- u32 child_relid;
- u32 gpadl;
- u16 range_buflen;
- u16 rangecount;
- struct gpa_range range[0];
-} __packed;
-
-/* This is the followup packet that contains more PFNs. */
-struct vmbus_channel_gpadl_body {
- struct vmbus_channel_message_header header;
- u32 msgnumber;
- u32 gpadl;
- u64 pfn[0];
-} __packed;
-
-struct vmbus_channel_gpadl_created {
- struct vmbus_channel_message_header header;
- u32 child_relid;
- u32 gpadl;
- u32 creation_status;
-} __packed;
-
-struct vmbus_channel_gpadl_teardown {
- struct vmbus_channel_message_header header;
- u32 child_relid;
- u32 gpadl;
-} __packed;
-
-struct vmbus_channel_gpadl_torndown {
- struct vmbus_channel_message_header header;
- u32 gpadl;
-} __packed;
-
-#ifdef VMBUS_FEATURE_PARENT_OR_PEER_MEMORY_MAPPED_INTO_A_CHILD
-struct vmbus_channel_view_range_add {
- struct vmbus_channel_message_header header;
- PHYSICAL_ADDRESS viewrange_base;
- u64 viewrange_length;
- u32 child_relid;
-} __packed;
-
-struct vmbus_channel_view_range_remove {
- struct vmbus_channel_message_header header;
- PHYSICAL_ADDRESS viewrange_base;
- u32 child_relid;
-} __packed;
-#endif
-
-struct vmbus_channel_relid_released {
- struct vmbus_channel_message_header header;
- u32 child_relid;
-} __packed;
-
-struct vmbus_channel_initiate_contact {
- struct vmbus_channel_message_header header;
- u32 vmbus_version_requested;
- u32 padding2;
- u64 interrupt_page;
- u64 monitor_page1;
- u64 monitor_page2;
-} __packed;
-
-struct vmbus_channel_version_response {
- struct vmbus_channel_message_header header;
- bool version_supported;
-} __packed;
-
-enum vmbus_channel_state {
- CHANNEL_OFFER_STATE,
- CHANNEL_OPENING_STATE,
- CHANNEL_OPEN_STATE,
-};
-
-struct vmbus_channel {
- struct list_head listentry;
-
- struct hv_device *device_obj;
-
- struct timer_list poll_timer; /* SA-111 workaround */
- struct work_struct work;
-
- enum vmbus_channel_state state;
-
- struct vmbus_channel_offer_channel offermsg;
- /*
- * These are based on the OfferMsg.MonitorId.
- * Save it here for easy access.
- */
- u8 monitor_grp;
- u8 monitor_bit;
-
- u32 ringbuffer_gpadlhandle;
-
- /* Allocated memory for ring buffer */
- void *ringbuffer_pages;
- u32 ringbuffer_pagecount;
- struct hv_ring_buffer_info outbound; /* send to parent */
- struct hv_ring_buffer_info inbound; /* receive from parent */
- spinlock_t inbound_lock;
- struct workqueue_struct *controlwq;
-
- /* Channel callback are invoked in this workqueue context */
- /* HANDLE dataWorkQueue; */
-
- void (*onchannel_callback)(void *context);
- void *channel_callback_context;
-};
-
-struct vmbus_channel_debug_info {
- u32 relid;
- enum vmbus_channel_state state;
- struct hv_guid interfacetype;
- struct hv_guid interface_instance;
- u32 monitorid;
- u32 servermonitor_pending;
- u32 servermonitor_latency;
- u32 servermonitor_connectionid;
- u32 clientmonitor_pending;
- u32 clientmonitor_latency;
- u32 clientmonitor_connectionid;
-
- struct hv_ring_buffer_debug_info inbound;
- struct hv_ring_buffer_debug_info outbound;
-};
-
-/*
- * Represents each channel msg on the vmbus connection This is a
- * variable-size data structure depending on the msg type itself
- */
-struct vmbus_channel_msginfo {
- /* Bookkeeping stuff */
- struct list_head msglistentry;
-
- /* So far, this is only used to handle gpadl body message */
- struct list_head submsglist;
-
- /* Synchronize the request/response if needed */
- int wait_condition;
- wait_queue_head_t waitevent;
- union {
- struct vmbus_channel_version_supported version_supported;
- struct vmbus_channel_open_result open_result;
- struct vmbus_channel_gpadl_torndown gpadl_torndown;
- struct vmbus_channel_gpadl_created gpadl_created;
- struct vmbus_channel_version_response version_response;
- } response;
-
- u32 msgsize;
- /*
- * The channel message that goes out on the "wire".
- * It will contain at minimum the VMBUS_CHANNEL_MESSAGE_HEADER header
- */
- unsigned char msg[0];
-};
-
-
-void free_channel(struct vmbus_channel *channel);
-
-void vmbus_onmessage(void *context);
-
-int vmbus_request_offers(void);
-
-void vmbus_release_unattached_channels(void);
-
-#endif /* _CHANNEL_MGMT_H_ */
diff --git a/drivers/staging/hv/connection.c b/drivers/staging/hv/connection.c
index afc8116..37bbf77 100644
--- a/drivers/staging/hv/connection.c
+++ b/drivers/staging/hv/connection.c
@@ -20,15 +20,17 @@
* Hank Janssen <hjanssen@microsoft.com>
*
*/
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/wait.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/vmalloc.h>
-#include "hv_api.h"
-#include "logging.h"
-#include "vmbus_private.h"
+
+#include "hyperv.h"
+#include "hyperv_vmbus.h"
struct vmbus_connection vmbus_connection = {
@@ -42,6 +44,7 @@
int vmbus_connect(void)
{
int ret = 0;
+ int t;
struct vmbus_channel_msginfo *msginfo = NULL;
struct vmbus_channel_initiate_contact *msg;
unsigned long flags;
@@ -55,7 +58,7 @@
vmbus_connection.work_queue = create_workqueue("hv_vmbus_con");
if (!vmbus_connection.work_queue) {
ret = -1;
- goto Cleanup;
+ goto cleanup;
}
INIT_LIST_HEAD(&vmbus_connection.chn_msg_list);
@@ -72,7 +75,7 @@
(void *)__get_free_pages(GFP_KERNEL|__GFP_ZERO, 0);
if (vmbus_connection.int_page == NULL) {
ret = -1;
- goto Cleanup;
+ goto cleanup;
}
vmbus_connection.recv_int_page = vmbus_connection.int_page;
@@ -88,7 +91,7 @@
(void *)__get_free_pages((GFP_KERNEL|__GFP_ZERO), 1);
if (vmbus_connection.monitor_pages == NULL) {
ret = -1;
- goto Cleanup;
+ goto cleanup;
}
msginfo = kzalloc(sizeof(*msginfo) +
@@ -96,10 +99,10 @@
GFP_KERNEL);
if (msginfo == NULL) {
ret = -ENOMEM;
- goto Cleanup;
+ goto cleanup;
}
- init_waitqueue_head(&msginfo->waitevent);
+ init_completion(&msginfo->waitevent);
msg = (struct vmbus_channel_initiate_contact *)msginfo->msg;
@@ -121,11 +124,6 @@
spin_unlock_irqrestore(&vmbus_connection.channelmsg_lock, flags);
- DPRINT_DBG(VMBUS, "Vmbus connection - interrupt pfn %llx, "
- "monitor1 pfn %llx,, monitor2 pfn %llx",
- msg->interrupt_page, msg->monitor_page1, msg->monitor_page2);
-
- DPRINT_DBG(VMBUS, "Sending channel initiate msg...");
ret = vmbus_post_msg(msg,
sizeof(struct vmbus_channel_initiate_contact));
if (ret != 0) {
@@ -133,21 +131,19 @@
list_del(&msginfo->msglistentry);
spin_unlock_irqrestore(&vmbus_connection.channelmsg_lock,
flags);
- goto Cleanup;
+ goto cleanup;
}
/* Wait for the connection response */
- msginfo->wait_condition = 0;
- wait_event_timeout(msginfo->waitevent, msginfo->wait_condition,
- msecs_to_jiffies(1000));
- if (msginfo->wait_condition == 0) {
+ t = wait_for_completion_timeout(&msginfo->waitevent, HZ);
+ if (t == 0) {
spin_lock_irqsave(&vmbus_connection.channelmsg_lock,
flags);
list_del(&msginfo->msglistentry);
spin_unlock_irqrestore(&vmbus_connection.channelmsg_lock,
flags);
ret = -ETIMEDOUT;
- goto Cleanup;
+ goto cleanup;
}
spin_lock_irqsave(&vmbus_connection.channelmsg_lock, flags);
@@ -156,21 +152,19 @@
/* Check if successful */
if (msginfo->response.version_response.version_supported) {
- DPRINT_INFO(VMBUS, "Vmbus connected!!");
vmbus_connection.conn_state = CONNECTED;
-
} else {
- DPRINT_ERR(VMBUS, "Vmbus connection failed!!..."
- "current version (%d) not supported",
- VMBUS_REVISION_NUMBER);
+ pr_err("Unable to connect, "
+ "Version %d not supported by Hyper-V\n",
+ VMBUS_REVISION_NUMBER);
ret = -1;
- goto Cleanup;
+ goto cleanup;
}
kfree(msginfo);
return 0;
-Cleanup:
+cleanup:
vmbus_connection.conn_state = DISCONNECTED;
if (vmbus_connection.work_queue)
@@ -213,7 +207,7 @@
ret = vmbus_post_msg(msg,
sizeof(struct vmbus_channel_message_header));
if (ret != 0)
- goto Cleanup;
+ goto cleanup;
free_pages((unsigned long)vmbus_connection.int_page, 0);
free_pages((unsigned long)vmbus_connection.monitor_pages, 1);
@@ -223,9 +217,9 @@
vmbus_connection.conn_state = DISCONNECTED;
- DPRINT_INFO(VMBUS, "Vmbus disconnected!!");
+ pr_info("hv_vmbus disconnected\n");
-Cleanup:
+cleanup:
kfree(msg);
return ret;
}
@@ -255,10 +249,9 @@
/*
* process_chn_event - Process a channel event notification
*/
-static void process_chn_event(void *context)
+static void process_chn_event(u32 relid)
{
struct vmbus_channel *channel;
- u32 relid = (u32)(unsigned long)context;
/* ASSERT(relId > 0); */
@@ -270,13 +263,8 @@
if (channel) {
vmbus_onchannel_event(channel);
- /*
- * WorkQueueQueueWorkItem(channel->dataWorkQueue,
- * vmbus_onchannel_event,
- * (void*)channel);
- */
} else {
- DPRINT_ERR(VMBUS, "channel not found for relid - %d.", relid);
+ pr_err("channel not found for relid - %u\n", relid);
}
}
@@ -285,39 +273,33 @@
*/
void vmbus_on_event(unsigned long data)
{
- int dword;
- int maxdword = MAX_NUM_CHANNELS_SUPPORTED >> 5;
+ u32 dword;
+ u32 maxdword = MAX_NUM_CHANNELS_SUPPORTED >> 5;
int bit;
- int relid;
+ u32 relid;
u32 *recv_int_page = vmbus_connection.recv_int_page;
/* Check events */
- if (recv_int_page) {
- for (dword = 0; dword < maxdword; dword++) {
- if (recv_int_page[dword]) {
- for (bit = 0; bit < 32; bit++) {
- if (sync_test_and_clear_bit(bit,
- (unsigned long *)
- &recv_int_page[dword])) {
- relid = (dword << 5) + bit;
- DPRINT_DBG(VMBUS, "event detected for relid - %d", relid);
+ if (!recv_int_page)
+ return;
+ for (dword = 0; dword < maxdword; dword++) {
+ if (!recv_int_page[dword])
+ continue;
+ for (bit = 0; bit < 32; bit++) {
+ if (sync_test_and_clear_bit(bit, (unsigned long *)&recv_int_page[dword])) {
+ relid = (dword << 5) + bit;
- if (relid == 0) {
- /* special case - vmbus channel protocol msg */
- DPRINT_DBG(VMBUS, "invalid relid - %d", relid);
- continue;
- } else {
- /* QueueWorkItem(VmbusProcessEvent, (void*)relid); */
- /* ret = WorkQueueQueueWorkItem(gVmbusConnection.workQueue, VmbusProcessChannelEvent, (void*)relid); */
- process_chn_event((void *)
- (unsigned long)relid);
- }
- }
+ if (relid == 0) {
+ /*
+ * Special case - vmbus
+ * channel protocol msg
+ */
+ continue;
}
+ process_chn_event(relid);
}
- }
+ }
}
- return;
}
/*
diff --git a/drivers/staging/hv/hv.c b/drivers/staging/hv/hv.c
index 0b06f4f..a2cc091 100644
--- a/drivers/staging/hv/hv.c
+++ b/drivers/staging/hv/hv.c
@@ -19,13 +19,15 @@
* Hank Janssen <hjanssen@microsoft.com>
*
*/
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
#include <linux/kernel.h>
#include <linux/mm.h>
#include <linux/slab.h>
#include <linux/vmalloc.h>
-#include "hv_api.h"
-#include "logging.h"
-#include "vmbus_private.h"
+
+#include "hyperv.h"
+#include "hyperv_vmbus.h"
/* The one and only */
struct hv_context hv_context = {
@@ -80,33 +82,7 @@
op = HVCPUID_VENDOR_MAXFUNCTION;
cpuid(op, &eax, &ebx, &ecx, &edx);
- DPRINT_INFO(VMBUS, "Vendor ID: %c%c%c%c%c%c%c%c%c%c%c%c",
- (ebx & 0xFF),
- ((ebx >> 8) & 0xFF),
- ((ebx >> 16) & 0xFF),
- ((ebx >> 24) & 0xFF),
- (ecx & 0xFF),
- ((ecx >> 8) & 0xFF),
- ((ecx >> 16) & 0xFF),
- ((ecx >> 24) & 0xFF),
- (edx & 0xFF),
- ((edx >> 8) & 0xFF),
- ((edx >> 16) & 0xFF),
- ((edx >> 24) & 0xFF));
-
max_leaf = eax;
- eax = 0;
- ebx = 0;
- ecx = 0;
- edx = 0;
- op = HVCPUID_INTERFACE;
- cpuid(op, &eax, &ebx, &ecx, &edx);
-
- DPRINT_INFO(VMBUS, "Interface ID: %c%c%c%c",
- (eax & 0xFF),
- ((eax >> 8) & 0xFF),
- ((eax >> 16) & 0xFF),
- ((eax >> 24) & 0xFF));
if (max_leaf >= HVCPUID_VERSION) {
eax = 0;
@@ -115,7 +91,7 @@
edx = 0;
op = HVCPUID_VERSION;
cpuid(op, &eax, &ebx, &ecx, &edx);
- DPRINT_INFO(VMBUS, "OS Build:%d-%d.%d-%d-%d.%d",\
+ pr_info("Hyper-V Host OS Build:%d-%d.%d-%d-%d.%d\n",
eax,
ebx >> 16,
ebx & 0xFFFF,
@@ -137,18 +113,11 @@
u64 output_address = (output) ? virt_to_phys(output) : 0;
volatile void *hypercall_page = hv_context.hypercall_page;
- DPRINT_DBG(VMBUS, "Hypercall <control %llx input phys %llx virt %p "
- "output phys %llx virt %p hypercall %p>",
- control, input_address, input,
- output_address, output, hypercall_page);
-
__asm__ __volatile__("mov %0, %%r8" : : "r" (output_address) : "r8");
__asm__ __volatile__("call *%3" : "=a" (hv_status) :
"c" (control), "d" (input_address),
"m" (hypercall_page));
- DPRINT_DBG(VMBUS, "Hypercall <return %llx>", hv_status);
-
return hv_status;
#else
@@ -165,18 +134,12 @@
u32 output_address_lo = output_address & 0xFFFFFFFF;
volatile void *hypercall_page = hv_context.hypercall_page;
- DPRINT_DBG(VMBUS, "Hypercall <control %llx input %p output %p>",
- control, input, output);
-
__asm__ __volatile__ ("call *%8" : "=d"(hv_status_hi),
"=a"(hv_status_lo) : "d" (control_hi),
"a" (control_lo), "b" (input_address_hi),
"c" (input_address_lo), "D"(output_address_hi),
"S"(output_address_lo), "m" (hypercall_page));
- DPRINT_DBG(VMBUS, "Hypercall <return %llx>",
- hv_status_lo | ((u64)hv_status_hi << 32));
-
return hv_status_lo | ((u64)hv_status_hi << 32);
#endif /* !x86_64 */
}
@@ -197,13 +160,8 @@
memset(hv_context.synic_message_page, 0,
sizeof(void *) * MAX_NUM_CPUS);
- if (!query_hypervisor_presence()) {
- DPRINT_ERR(VMBUS, "No Windows hypervisor detected!!");
- goto Cleanup;
- }
-
- DPRINT_INFO(VMBUS,
- "Windows hypervisor detected! Retrieving more info...");
+ if (!query_hypervisor_presence())
+ goto cleanup;
max_leaf = query_hypervisor_info();
/* HvQueryHypervisorFeatures(maxLeaf); */
@@ -213,11 +171,8 @@
*/
rdmsrl(HV_X64_MSR_GUEST_OS_ID, hv_context.guestid);
- if (hv_context.guestid != 0) {
- DPRINT_ERR(VMBUS, "Unknown guest id (0x%llx)!!",
- hv_context.guestid);
- goto Cleanup;
- }
+ if (hv_context.guestid != 0)
+ goto cleanup;
/* Write our OS info */
wrmsrl(HV_X64_MSR_GUEST_OS_ID, HV_LINUX_GUEST_ID);
@@ -232,11 +187,8 @@
*/
virtaddr = __vmalloc(PAGE_SIZE, GFP_KERNEL, PAGE_KERNEL_EXEC);
- if (!virtaddr) {
- DPRINT_ERR(VMBUS,
- "unable to allocate hypercall page!!");
- goto Cleanup;
- }
+ if (!virtaddr)
+ goto cleanup;
hypercall_msr.enable = 1;
@@ -247,23 +199,17 @@
hypercall_msr.as_uint64 = 0;
rdmsrl(HV_X64_MSR_HYPERCALL, hypercall_msr.as_uint64);
- if (!hypercall_msr.enable) {
- DPRINT_ERR(VMBUS, "unable to set hypercall page!!");
- goto Cleanup;
- }
+ if (!hypercall_msr.enable)
+ goto cleanup;
hv_context.hypercall_page = virtaddr;
- DPRINT_INFO(VMBUS, "Hypercall page VA=%p, PA=0x%0llx",
- hv_context.hypercall_page,
- (u64)hypercall_msr.guest_physical_address << PAGE_SHIFT);
-
/* Setup the global signal event param for the signal event hypercall */
hv_context.signal_event_buffer =
kmalloc(sizeof(struct hv_input_signal_event_buffer),
GFP_KERNEL);
if (!hv_context.signal_event_buffer)
- goto Cleanup;
+ goto cleanup;
hv_context.signal_event_param =
(struct hv_input_signal_event *)
@@ -278,7 +224,7 @@
return ret;
-Cleanup:
+cleanup:
if (virtaddr) {
if (hypercall_msr.enable) {
hypercall_msr.as_uint64 = 0;
@@ -394,24 +340,20 @@
/* Check the version */
rdmsrl(HV_X64_MSR_SVERSION, version);
- DPRINT_INFO(VMBUS, "SynIC version: %llx", version);
-
hv_context.synic_message_page[cpu] =
(void *)get_zeroed_page(GFP_ATOMIC);
if (hv_context.synic_message_page[cpu] == NULL) {
- DPRINT_ERR(VMBUS,
- "unable to allocate SYNIC message page!!");
- goto Cleanup;
+ pr_err("Unable to allocate SYNIC message page\n");
+ goto cleanup;
}
hv_context.synic_event_page[cpu] =
(void *)get_zeroed_page(GFP_ATOMIC);
if (hv_context.synic_event_page[cpu] == NULL) {
- DPRINT_ERR(VMBUS,
- "unable to allocate SYNIC event page!!");
- goto Cleanup;
+ pr_err("Unable to allocate SYNIC event page\n");
+ goto cleanup;
}
/* Setup the Synic's message page */
@@ -420,8 +362,6 @@
simp.base_simp_gpa = virt_to_phys(hv_context.synic_message_page[cpu])
>> PAGE_SHIFT;
- DPRINT_DBG(VMBUS, "HV_X64_MSR_SIMP msr set to: %llx", simp.as_uint64);
-
wrmsrl(HV_X64_MSR_SIMP, simp.as_uint64);
/* Setup the Synic's event page */
@@ -430,14 +370,8 @@
siefp.base_siefp_gpa = virt_to_phys(hv_context.synic_event_page[cpu])
>> PAGE_SHIFT;
- DPRINT_DBG(VMBUS, "HV_X64_MSR_SIEFP msr set to: %llx", siefp.as_uint64);
-
wrmsrl(HV_X64_MSR_SIEFP, siefp.as_uint64);
- /* Setup the interception SINT. */
- /* wrmsrl((HV_X64_MSR_SINT0 + HV_SYNIC_INTERCEPTION_SINT_INDEX), */
- /* interceptionSint.as_uint64); */
-
/* Setup the shared SINT. */
rdmsrl(HV_X64_MSR_SINT0 + VMBUS_MESSAGE_SINT, shared_sint.as_uint64);
@@ -446,9 +380,6 @@
shared_sint.masked = false;
shared_sint.auto_eoi = true;
- DPRINT_DBG(VMBUS, "HV_X64_MSR_SINT1 msr set to: %llx",
- shared_sint.as_uint64);
-
wrmsrl(HV_X64_MSR_SINT0 + VMBUS_MESSAGE_SINT, shared_sint.as_uint64);
/* Enable the global synic bit */
@@ -460,7 +391,7 @@
hv_context.synic_initialized = true;
return;
-Cleanup:
+cleanup:
if (hv_context.synic_event_page[cpu])
free_page((unsigned long)hv_context.synic_event_page[cpu]);
diff --git a/drivers/staging/hv/hv.h b/drivers/staging/hv/hv.h
deleted file mode 100644
index 829aff8..0000000
--- a/drivers/staging/hv/hv.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
- *
- * Copyright (c) 2009, Microsoft Corporation.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
- * Place - Suite 330, Boston, MA 02111-1307 USA.
- *
- * Authors:
- * Haiyang Zhang <haiyangz@microsoft.com>
- * Hank Janssen <hjanssen@microsoft.com>
- *
- */
-
-
-#ifndef __HV_H__
-#define __HV_H__
-
-#include "hv_api.h"
-
-enum {
- VMBUS_MESSAGE_CONNECTION_ID = 1,
- VMBUS_MESSAGE_PORT_ID = 1,
- VMBUS_EVENT_CONNECTION_ID = 2,
- VMBUS_EVENT_PORT_ID = 2,
- VMBUS_MONITOR_CONNECTION_ID = 3,
- VMBUS_MONITOR_PORT_ID = 3,
- VMBUS_MESSAGE_SINT = 2,
-};
-
-/* #defines */
-
-#define HV_PRESENT_BIT 0x80000000
-
-#define HV_LINUX_GUEST_ID_LO 0x00000000
-#define HV_LINUX_GUEST_ID_HI 0xB16B00B5
-#define HV_LINUX_GUEST_ID (((u64)HV_LINUX_GUEST_ID_HI << 32) | \
- HV_LINUX_GUEST_ID_LO)
-
-#define HV_CPU_POWER_MANAGEMENT (1 << 0)
-#define HV_RECOMMENDATIONS_MAX 4
-
-#define HV_X64_MAX 5
-#define HV_CAPS_MAX 8
-
-
-#define HV_HYPERCALL_PARAM_ALIGN sizeof(u64)
-
-
-/* Service definitions */
-
-#define HV_SERVICE_PARENT_PORT (0)
-#define HV_SERVICE_PARENT_CONNECTION (0)
-
-#define HV_SERVICE_CONNECT_RESPONSE_SUCCESS (0)
-#define HV_SERVICE_CONNECT_RESPONSE_INVALID_PARAMETER (1)
-#define HV_SERVICE_CONNECT_RESPONSE_UNKNOWN_SERVICE (2)
-#define HV_SERVICE_CONNECT_RESPONSE_CONNECTION_REJECTED (3)
-
-#define HV_SERVICE_CONNECT_REQUEST_MESSAGE_ID (1)
-#define HV_SERVICE_CONNECT_RESPONSE_MESSAGE_ID (2)
-#define HV_SERVICE_DISCONNECT_REQUEST_MESSAGE_ID (3)
-#define HV_SERVICE_DISCONNECT_RESPONSE_MESSAGE_ID (4)
-#define HV_SERVICE_MAX_MESSAGE_ID (4)
-
-#define HV_SERVICE_PROTOCOL_VERSION (0x0010)
-#define HV_CONNECT_PAYLOAD_BYTE_COUNT 64
-
-/* #define VMBUS_REVISION_NUMBER 6 */
-
-/* Our local vmbus's port and connection id. Anything >0 is fine */
-/* #define VMBUS_PORT_ID 11 */
-
-/* 628180B8-308D-4c5e-B7DB-1BEB62E62EF4 */
-static const struct hv_guid VMBUS_SERVICE_ID = {
- .data = {
- 0xb8, 0x80, 0x81, 0x62, 0x8d, 0x30, 0x5e, 0x4c,
- 0xb7, 0xdb, 0x1b, 0xeb, 0x62, 0xe6, 0x2e, 0xf4
- },
-};
-
-#define MAX_NUM_CPUS 32
-
-
-struct hv_input_signal_event_buffer {
- u64 align8;
- struct hv_input_signal_event event;
-};
-
-struct hv_context {
- /* We only support running on top of Hyper-V
- * So at this point this really can only contain the Hyper-V ID
- */
- u64 guestid;
-
- void *hypercall_page;
-
- bool synic_initialized;
-
- /*
- * This is used as an input param to HvCallSignalEvent hypercall. The
- * input param is immutable in our usage and must be dynamic mem (vs
- * stack or global). */
- struct hv_input_signal_event_buffer *signal_event_buffer;
- /* 8-bytes aligned of the buffer above */
- struct hv_input_signal_event *signal_event_param;
-
- void *synic_message_page[MAX_NUM_CPUS];
- void *synic_event_page[MAX_NUM_CPUS];
-};
-
-extern struct hv_context hv_context;
-
-
-/* Hv Interface */
-
-extern int hv_init(void);
-
-extern void hv_cleanup(void);
-
-extern u16 hv_post_message(union hv_connection_id connection_id,
- enum hv_message_type message_type,
- void *payload, size_t payload_size);
-
-extern u16 hv_signal_event(void);
-
-extern void hv_synic_init(void *irqarg);
-
-extern void hv_synic_cleanup(void *arg);
-
-#endif /* __HV_H__ */
diff --git a/drivers/staging/hv/hv_api.h b/drivers/staging/hv/hv_api.h
deleted file mode 100644
index 43a7228..0000000
--- a/drivers/staging/hv/hv_api.h
+++ /dev/null
@@ -1,910 +0,0 @@
-/*
- *
- * Copyright (c) 2009, Microsoft Corporation.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
- * Place - Suite 330, Boston, MA 02111-1307 USA.
- *
- * Authors:
- * Haiyang Zhang <haiyangz@microsoft.com>
- * Hank Janssen <hjanssen@microsoft.com>
- *
- */
-#ifndef __HV_API_H
-#define __HV_API_H
-
-struct hv_guid {
- unsigned char data[16];
-};
-
-
-
-/* Status codes for hypervisor operations. */
-
-/*
- * HV_STATUS_SUCCESS
- * The specified hypercall succeeded
- */
-#define HV_STATUS_SUCCESS ((u16)0x0000)
-
-/*
- * HV_STATUS_INVALID_HYPERCALL_CODE
- * The hypervisor does not support the operation because the specified
- * hypercall code is not supported.
- */
-#define HV_STATUS_INVALID_HYPERCALL_CODE ((u16)0x0002)
-
-/*
- * HV_STATUS_INVALID_HYPERCALL_INPUT
- * The hypervisor does not support the operation because the encoding for the
- * hypercall input register is not supported.
- */
-#define HV_STATUS_INVALID_HYPERCALL_INPUT ((u16)0x0003)
-
-/*
- * HV_STATUS_INVALID_ALIGNMENT
- * The hypervisor could not perform the operation because a parameter has an
- * invalid alignment.
- */
-#define HV_STATUS_INVALID_ALIGNMENT ((u16)0x0004)
-
-/*
- * HV_STATUS_INVALID_PARAMETER
- * The hypervisor could not perform the operation because an invalid parameter
- * was specified.
- */
-#define HV_STATUS_INVALID_PARAMETER ((u16)0x0005)
-
-/*
- * HV_STATUS_ACCESS_DENIED
- * Access to the specified object was denied.
- */
-#define HV_STATUS_ACCESS_DENIED ((u16)0x0006)
-
-/*
- * HV_STATUS_INVALID_PARTITION_STATE
- * The hypervisor could not perform the operation because the partition is
- * entering or in an invalid state.
- */
-#define HV_STATUS_INVALID_PARTITION_STATE ((u16)0x0007)
-
-/*
- * HV_STATUS_OPERATION_DENIED
- * The operation is not allowed in the current state.
- */
-#define HV_STATUS_OPERATION_DENIED ((u16)0x0008)
-
-/*
- * HV_STATUS_UNKNOWN_PROPERTY
- * The hypervisor does not recognize the specified partition property.
- */
-#define HV_STATUS_UNKNOWN_PROPERTY ((u16)0x0009)
-
-/*
- * HV_STATUS_PROPERTY_VALUE_OUT_OF_RANGE
- * The specified value of a partition property is out of range or violates an
- * invariant.
- */
-#define HV_STATUS_PROPERTY_VALUE_OUT_OF_RANGE ((u16)0x000A)
-
-/*
- * HV_STATUS_INSUFFICIENT_MEMORY
- * There is not enough memory in the hypervisor pool to complete the operation.
- */
-#define HV_STATUS_INSUFFICIENT_MEMORY ((u16)0x000B)
-
-/*
- * HV_STATUS_PARTITION_TOO_DEEP
- * The maximum partition depth has been exceeded for the partition hierarchy.
- */
-#define HV_STATUS_PARTITION_TOO_DEEP ((u16)0x000C)
-
-/*
- * HV_STATUS_INVALID_PARTITION_ID
- * A partition with the specified partition Id does not exist.
- */
-#define HV_STATUS_INVALID_PARTITION_ID ((u16)0x000D)
-
-/*
- * HV_STATUS_INVALID_VP_INDEX
- * The hypervisor could not perform the operation because the specified VP
- * index is invalid.
- */
-#define HV_STATUS_INVALID_VP_INDEX ((u16)0x000E)
-
-/*
- * HV_STATUS_NOT_FOUND
- * The iteration is complete; no addition items in the iteration could be
- * found.
- */
-#define HV_STATUS_NOT_FOUND ((u16)0x0010)
-
-/*
- * HV_STATUS_INVALID_PORT_ID
- * The hypervisor could not perform the operation because the specified port
- * identifier is invalid.
- */
-#define HV_STATUS_INVALID_PORT_ID ((u16)0x0011)
-
-/*
- * HV_STATUS_INVALID_CONNECTION_ID
- * The hypervisor could not perform the operation because the specified
- * connection identifier is invalid.
- */
-#define HV_STATUS_INVALID_CONNECTION_ID ((u16)0x0012)
-
-/*
- * HV_STATUS_INSUFFICIENT_BUFFERS
- * You did not supply enough message buffers to send a message.
- */
-#define HV_STATUS_INSUFFICIENT_BUFFERS ((u16)0x0013)
-
-/*
- * HV_STATUS_NOT_ACKNOWLEDGED
- * The previous virtual interrupt has not been acknowledged.
- */
-#define HV_STATUS_NOT_ACKNOWLEDGED ((u16)0x0014)
-
-/*
- * HV_STATUS_INVALID_VP_STATE
- * A virtual processor is not in the correct state for the performance of the
- * indicated operation.
- */
-#define HV_STATUS_INVALID_VP_STATE ((u16)0x0015)
-
-/*
- * HV_STATUS_ACKNOWLEDGED
- * The previous virtual interrupt has already been acknowledged.
- */
-#define HV_STATUS_ACKNOWLEDGED ((u16)0x0016)
-
-/*
- * HV_STATUS_INVALID_SAVE_RESTORE_STATE
- * The indicated partition is not in a valid state for saving or restoring.
- */
-#define HV_STATUS_INVALID_SAVE_RESTORE_STATE ((u16)0x0017)
-
-/*
- * HV_STATUS_INVALID_SYNIC_STATE
- * The hypervisor could not complete the operation because a required feature
- * of the synthetic interrupt controller (SynIC) was disabled.
- */
-#define HV_STATUS_INVALID_SYNIC_STATE ((u16)0x0018)
-
-/*
- * HV_STATUS_OBJECT_IN_USE
- * The hypervisor could not perform the operation because the object or value
- * was either already in use or being used for a purpose that would not permit
- * completing the operation.
- */
-#define HV_STATUS_OBJECT_IN_USE ((u16)0x0019)
-
-/*
- * HV_STATUS_INVALID_PROXIMITY_DOMAIN_INFO
- * The proximity domain information is invalid.
- */
-#define HV_STATUS_INVALID_PROXIMITY_DOMAIN_INFO ((u16)0x001A)
-
-/*
- * HV_STATUS_NO_DATA
- * An attempt to retrieve debugging data failed because none was available.
- */
-#define HV_STATUS_NO_DATA ((u16)0x001B)
-
-/*
- * HV_STATUS_INACTIVE
- * The physical connection being used for debuggging has not recorded any
- * receive activity since the last operation.
- */
-#define HV_STATUS_INACTIVE ((u16)0x001C)
-
-/*
- * HV_STATUS_NO_RESOURCES
- * There are not enough resources to complete the operation.
- */
-#define HV_STATUS_NO_RESOURCES ((u16)0x001D)
-
-/*
- * HV_STATUS_FEATURE_UNAVAILABLE
- * A hypervisor feature is not available to the user.
- */
-#define HV_STATUS_FEATURE_UNAVAILABLE ((u16)0x001E)
-
-/*
- * HV_STATUS_UNSUCCESSFUL
- * {Operation Failed} The requested operation was unsuccessful.
- */
-#define HV_STATUS_UNSUCCESSFUL ((u16)0x1001)
-
-/*
- * HV_STATUS_INSUFFICIENT_BUFFER
- * The specified buffer was too small to contain all of the requested data.
- */
-#define HV_STATUS_INSUFFICIENT_BUFFER ((u16)0x1002)
-
-/*
- * HV_STATUS_GPA_NOT_PRESENT
- * The guest physical address is not currently associated with a system
- * physical address.
- */
-#define HV_STATUS_GPA_NOT_PRESENT ((u16)0x1003)
-
-/*
- * HV_STATUS_GUEST_PAGE_FAULT
- * The operation would have resulted in a page fault in the guest.
- */
-#define HV_STATUS_GUEST_PAGE_FAULT ((u16)0x1004)
-
-/*
- * HV_STATUS_RUNDOWN_DISABLED
- * The operation cannot proceed as the rundown object was marked disabled.
- */
-#define HV_STATUS_RUNDOWN_DISABLED ((u16)0x1005)
-
-/*
- * HV_STATUS_KEY_ALREADY_EXISTS
- * The entry cannot be added as another entry with the same key already exists.
- */
-#define HV_STATUS_KEY_ALREADY_EXISTS ((u16)0x1006)
-
-/*
- * HV_STATUS_GPA_INTERCEPT
- * The operation resulted an intercept on a region of guest physical memory.
- */
-#define HV_STATUS_GPA_INTERCEPT ((u16)0x1007)
-
-/*
- * HV_STATUS_GUEST_GENERAL_PROTECTION_FAULT
- * The operation would have resulted in a general protection fault in the
- * guest.
- */
-#define HV_STATUS_GUEST_GENERAL_PROTECTION_FAULT ((u16)0x1008)
-
-/*
- * HV_STATUS_GUEST_STACK_FAULT
- * The operation would have resulted in a stack fault in the guest.
- */
-#define HV_STATUS_GUEST_STACK_FAULT ((u16)0x1009)
-
-/*
- * HV_STATUS_GUEST_INVALID_OPCODE_FAULT
- * The operation would have resulted in an invalid opcode fault in the guest.
- */
-#define HV_STATUS_GUEST_INVALID_OPCODE_FAULT ((u16)0x100A)
-
-/*
- * HV_STATUS_FINALIZE_INCOMPLETE
- * The partition is not completely finalized.
- */
-#define HV_STATUS_FINALIZE_INCOMPLETE ((u16)0x100B)
-
-/*
- * HV_STATUS_GUEST_MACHINE_CHECK_ABORT
- * The operation would have resulted in an machine check abort in the guest.
- */
-#define HV_STATUS_GUEST_MACHINE_CHECK_ABORT ((u16)0x100C)
-
-/*
- * HV_STATUS_ILLEGAL_OVERLAY_ACCESS
- * An illegal access was attempted to an overlay page.
- */
-#define HV_STATUS_ILLEGAL_OVERLAY_ACCESS ((u16)0x100D)
-
-/*
- * HV_STATUS_INSUFFICIENT_SYSTEM_VA
- * There is not enough system VA space available to satisfy the request,
- */
-#define HV_STATUS_INSUFFICIENT_SYSTEM_VA ((u16)0x100E)
-
-/*
- * HV_STATUS_VIRTUAL_ADDRESS_NOT_MAPPED
- * The passed virtual address was not mapped in the hypervisor address space.
- */
-#define HV_STATUS_VIRTUAL_ADDRESS_NOT_MAPPED ((u16)0x100F)
-
-/*
- * HV_STATUS_NOT_IMPLEMENTED
- * The requested operation is not implemented in this version of the
- * hypervisor.
- */
-#define HV_STATUS_NOT_IMPLEMENTED ((u16)0x1010)
-
-/*
- * HV_STATUS_VMX_INSTRUCTION_FAILED
- * The requested VMX instruction failed to complete successfully.
- */
-#define HV_STATUS_VMX_INSTRUCTION_FAILED ((u16)0x1011)
-
-/*
- * HV_STATUS_VMX_INSTRUCTION_FAILED_WITH_STATUS
- * The requested VMX instruction failed to complete successfully indicating
- * status.
- */
-#define HV_STATUS_VMX_INSTRUCTION_FAILED_WITH_STATUS ((u16)0x1012)
-
-/*
- * HV_STATUS_MSR_ACCESS_FAILED
- * The requested access to the model specific register failed.
- */
-#define HV_STATUS_MSR_ACCESS_FAILED ((u16)0x1013)
-
-/*
- * HV_STATUS_CR_ACCESS_FAILED
- * The requested access to the control register failed.
- */
-#define HV_STATUS_CR_ACCESS_FAILED ((u16)0x1014)
-
-/*
- * HV_STATUS_TIMEOUT
- * The specified timeout expired before the operation completed.
- */
-#define HV_STATUS_TIMEOUT ((u16)0x1016)
-
-/*
- * HV_STATUS_MSR_INTERCEPT
- * The requested access to the model specific register generated an intercept.
- */
-#define HV_STATUS_MSR_INTERCEPT ((u16)0x1017)
-
-/*
- * HV_STATUS_CPUID_INTERCEPT
- * The CPUID instruction generated an intercept.
- */
-#define HV_STATUS_CPUID_INTERCEPT ((u16)0x1018)
-
-/*
- * HV_STATUS_REPEAT_INSTRUCTION
- * The current instruction should be repeated and the instruction pointer not
- * advanced.
- */
-#define HV_STATUS_REPEAT_INSTRUCTION ((u16)0x1019)
-
-/*
- * HV_STATUS_PAGE_PROTECTION_VIOLATION
- * The current instruction should be repeated and the instruction pointer not
- * advanced.
- */
-#define HV_STATUS_PAGE_PROTECTION_VIOLATION ((u16)0x101A)
-
-/*
- * HV_STATUS_PAGE_TABLE_INVALID
- * The current instruction should be repeated and the instruction pointer not
- * advanced.
- */
-#define HV_STATUS_PAGE_TABLE_INVALID ((u16)0x101B)
-
-/*
- * HV_STATUS_PAGE_NOT_PRESENT
- * The current instruction should be repeated and the instruction pointer not
- * advanced.
- */
-#define HV_STATUS_PAGE_NOT_PRESENT ((u16)0x101C)
-
-/*
- * HV_STATUS_IO_INTERCEPT
- * The requested access to the I/O port generated an intercept.
- */
-#define HV_STATUS_IO_INTERCEPT ((u16)0x101D)
-
-/*
- * HV_STATUS_NOTHING_TO_DO
- * There is nothing to do.
- */
-#define HV_STATUS_NOTHING_TO_DO ((u16)0x101E)
-
-/*
- * HV_STATUS_THREAD_TERMINATING
- * The requested thread is terminating.
- */
-#define HV_STATUS_THREAD_TERMINATING ((u16)0x101F)
-
-/*
- * HV_STATUS_SECTION_ALREADY_CONSTRUCTED
- * The specified section was already constructed.
- */
-#define HV_STATUS_SECTION_ALREADY_CONSTRUCTED ((u16)0x1020)
-
-/* HV_STATUS_SECTION_NOT_ALREADY_CONSTRUCTED
- * The specified section was not already constructed.
- */
-#define HV_STATUS_SECTION_NOT_ALREADY_CONSTRUCTED ((u16)0x1021)
-
-/*
- * HV_STATUS_PAGE_ALREADY_COMMITTED
- * The specified virtual address was already backed by physical memory.
- */
-#define HV_STATUS_PAGE_ALREADY_COMMITTED ((u16)0x1022)
-
-/*
- * HV_STATUS_PAGE_NOT_ALREADY_COMMITTED
- * The specified virtual address was not already backed by physical memory.
- */
-#define HV_STATUS_PAGE_NOT_ALREADY_COMMITTED ((u16)0x1023)
-
-/*
- * HV_STATUS_COMMITTED_PAGES_REMAIN
- * Committed pages remain in the section.
- */
-#define HV_STATUS_COMMITTED_PAGES_REMAIN ((u16)0x1024)
-
-/*
- * HV_STATUS_NO_REMAINING_COMMITTED_PAGES
- * No additional committed pages beyond the specified page exist in the
- * section.
- */
-#define HV_STATUS_NO_REMAINING_COMMITTED_PAGES ((u16)0x1025)
-
-/*
- * HV_STATUS_INSUFFICIENT_COMPARTMENT_VA
- * The VA space of the compartment is exhausted.
- */
-#define HV_STATUS_INSUFFICIENT_COMPARTMENT_VA ((u16)0x1026)
-
-/*
- * HV_STATUS_DEREF_SPA_LIST_FULL
- * The SPA dereference list is full, and there are additional entries to be
- * added to it.
- */
-#define HV_STATUS_DEREF_SPA_LIST_FULL ((u16)0x1027)
-
-/*
- * HV_STATUS_GPA_OUT_OF_RANGE
- * The supplied GPA is out of range.
- */
-#define HV_STATUS_GPA_OUT_OF_RANGE ((u16)0x1027)
-
-/*
- * HV_STATUS_NONVOLATILE_XMM_STALE
- * The XMM register that was being accessed is stale.
- */
-#define HV_STATUS_NONVOLATILE_XMM_STALE ((u16)0x1028)
-
-/* HV_STATUS_UNSUPPORTED_PROCESSOR
- * The hypervisor does not support the processors in this system.
- */
-#define HV_STATUS_UNSUPPORTED_PROCESSOR ((u16)0x1029)
-
-/*
- * HV_STATUS_INSUFFICIENT_CROM_SPACE
- * Insufficient space existed for copying over the CROM contents.
- */
-#define HV_STATUS_INSUFFICIENT_CROM_SPACE ((u16)0x2000)
-
-/*
- * HV_STATUS_BAD_CROM_FORMAT
- * The contents of the CROM failed validation attempts.
- */
-#define HV_STATUS_BAD_CROM_FORMAT ((u16)0x2001)
-
-/*
- * HV_STATUS_UNSUPPORTED_CROM_FORMAT
- * The contents of the CROM contain contents the parser doesn't support.
- */
-#define HV_STATUS_UNSUPPORTED_CROM_FORMAT ((u16)0x2002)
-
-/*
- * HV_STATUS_UNSUPPORTED_CONTROLLER
- * The register format of the OHCI controller specified for debugging is not
- * supported.
- */
-#define HV_STATUS_UNSUPPORTED_CONTROLLER ((u16)0x2003)
-
-/*
- * HV_STATUS_CROM_TOO_LARGE
- * The CROM contents were to large to copy over.
- */
-#define HV_STATUS_CROM_TOO_LARGE ((u16)0x2004)
-
-/*
- * HV_STATUS_CONTROLLER_IN_USE
- * The OHCI controller specified for debugging cannot be used as it is already
- * in use.
- */
-#define HV_STATUS_CONTROLLER_IN_USE ((u16)0x2005)
-
-
-/*
- * The below CPUID leaves are present if VersionAndFeatures.HypervisorPresent
- * is set by CPUID(HVCPUID_VERSION_FEATURES).
- */
-enum hv_cpuid_function {
- HVCPUID_VERSION_FEATURES = 0x00000001,
- HVCPUID_VENDOR_MAXFUNCTION = 0x40000000,
- HVCPUID_INTERFACE = 0x40000001,
-
- /*
- * The remaining functions depend on the value of
- * HVCPUID_INTERFACE
- */
- HVCPUID_VERSION = 0x40000002,
- HVCPUID_FEATURES = 0x40000003,
- HVCPUID_ENLIGHTENMENT_INFO = 0x40000004,
- HVCPUID_IMPLEMENTATION_LIMITS = 0x40000005,
-};
-
-/* Define the virtual APIC registers */
-#define HV_X64_MSR_EOI (0x40000070)
-#define HV_X64_MSR_ICR (0x40000071)
-#define HV_X64_MSR_TPR (0x40000072)
-#define HV_X64_MSR_APIC_ASSIST_PAGE (0x40000073)
-
-/* Define version of the synthetic interrupt controller. */
-#define HV_SYNIC_VERSION (1)
-
-/* Define synthetic interrupt controller model specific registers. */
-#define HV_X64_MSR_SCONTROL (0x40000080)
-#define HV_X64_MSR_SVERSION (0x40000081)
-#define HV_X64_MSR_SIEFP (0x40000082)
-#define HV_X64_MSR_SIMP (0x40000083)
-#define HV_X64_MSR_EOM (0x40000084)
-#define HV_X64_MSR_SINT0 (0x40000090)
-#define HV_X64_MSR_SINT1 (0x40000091)
-#define HV_X64_MSR_SINT2 (0x40000092)
-#define HV_X64_MSR_SINT3 (0x40000093)
-#define HV_X64_MSR_SINT4 (0x40000094)
-#define HV_X64_MSR_SINT5 (0x40000095)
-#define HV_X64_MSR_SINT6 (0x40000096)
-#define HV_X64_MSR_SINT7 (0x40000097)
-#define HV_X64_MSR_SINT8 (0x40000098)
-#define HV_X64_MSR_SINT9 (0x40000099)
-#define HV_X64_MSR_SINT10 (0x4000009A)
-#define HV_X64_MSR_SINT11 (0x4000009B)
-#define HV_X64_MSR_SINT12 (0x4000009C)
-#define HV_X64_MSR_SINT13 (0x4000009D)
-#define HV_X64_MSR_SINT14 (0x4000009E)
-#define HV_X64_MSR_SINT15 (0x4000009F)
-
-/* Define the expected SynIC version. */
-#define HV_SYNIC_VERSION_1 (0x1)
-
-/* Define synthetic interrupt controller message constants. */
-#define HV_MESSAGE_SIZE (256)
-#define HV_MESSAGE_PAYLOAD_BYTE_COUNT (240)
-#define HV_MESSAGE_PAYLOAD_QWORD_COUNT (30)
-#define HV_ANY_VP (0xFFFFFFFF)
-
-/* Define synthetic interrupt controller flag constants. */
-#define HV_EVENT_FLAGS_COUNT (256 * 8)
-#define HV_EVENT_FLAGS_BYTE_COUNT (256)
-#define HV_EVENT_FLAGS_DWORD_COUNT (256 / sizeof(u32))
-
-/* Define hypervisor message types. */
-enum hv_message_type {
- HVMSG_NONE = 0x00000000,
-
- /* Memory access messages. */
- HVMSG_UNMAPPED_GPA = 0x80000000,
- HVMSG_GPA_INTERCEPT = 0x80000001,
-
- /* Timer notification messages. */
- HVMSG_TIMER_EXPIRED = 0x80000010,
-
- /* Error messages. */
- HVMSG_INVALID_VP_REGISTER_VALUE = 0x80000020,
- HVMSG_UNRECOVERABLE_EXCEPTION = 0x80000021,
- HVMSG_UNSUPPORTED_FEATURE = 0x80000022,
-
- /* Trace buffer complete messages. */
- HVMSG_EVENTLOG_BUFFERCOMPLETE = 0x80000040,
-
- /* Platform-specific processor intercept messages. */
- HVMSG_X64_IOPORT_INTERCEPT = 0x80010000,
- HVMSG_X64_MSR_INTERCEPT = 0x80010001,
- HVMSG_X64_CPUID_INTERCEPT = 0x80010002,
- HVMSG_X64_EXCEPTION_INTERCEPT = 0x80010003,
- HVMSG_X64_APIC_EOI = 0x80010004,
- HVMSG_X64_LEGACY_FP_ERROR = 0x80010005
-};
-
-/* Define the number of synthetic interrupt sources. */
-#define HV_SYNIC_SINT_COUNT (16)
-#define HV_SYNIC_STIMER_COUNT (4)
-
-/* Define invalid partition identifier. */
-#define HV_PARTITION_ID_INVALID ((u64)0x0)
-
-/* Define connection identifier type. */
-union hv_connection_id {
- u32 asu32;
- struct {
- u32 id:24;
- u32 reserved:8;
- } u;
-};
-
-/* Define port identifier type. */
-union hv_port_id {
- u32 asu32;
- struct {
- u32 id:24;
- u32 reserved:8;
- } u ;
-};
-
-/* Define port type. */
-enum hv_port_type {
- HVPORT_MSG = 1,
- HVPORT_EVENT = 2,
- HVPORT_MONITOR = 3
-};
-
-/* Define port information structure. */
-struct hv_port_info {
- enum hv_port_type port_type;
- u32 padding;
- union {
- struct {
- u32 target_sint;
- u32 target_vp;
- u64 rsvdz;
- } message_port_info;
- struct {
- u32 target_sint;
- u32 target_vp;
- u16 base_flag_bumber;
- u16 flag_count;
- u32 rsvdz;
- } event_port_info;
- struct {
- u64 monitor_address;
- u64 rsvdz;
- } monitor_port_info;
- };
-};
-
-struct hv_connection_info {
- enum hv_port_type port_type;
- u32 padding;
- union {
- struct {
- u64 rsvdz;
- } message_connection_info;
- struct {
- u64 rsvdz;
- } event_connection_info;
- struct {
- u64 monitor_address;
- } monitor_connection_info;
- };
-};
-
-/* Define synthetic interrupt controller message flags. */
-union hv_message_flags {
- u8 asu8;
- struct {
- u8 msg_pending:1;
- u8 reserved:7;
- };
-};
-
-/* Define synthetic interrupt controller message header. */
-struct hv_message_header {
- enum hv_message_type message_type;
- u8 payload_size;
- union hv_message_flags message_flags;
- u8 reserved[2];
- union {
- u64 sender;
- union hv_port_id port;
- };
-};
-
-/* Define timer message payload structure. */
-struct hv_timer_message_payload {
- u32 timer_index;
- u32 reserved;
- u64 expiration_time; /* When the timer expired */
- u64 delivery_time; /* When the message was delivered */
-};
-
-/* Define synthetic interrupt controller message format. */
-struct hv_message {
- struct hv_message_header header;
- union {
- u64 payload[HV_MESSAGE_PAYLOAD_QWORD_COUNT];
- } u ;
-};
-
-/* Define the number of message buffers associated with each port. */
-#define HV_PORT_MESSAGE_BUFFER_COUNT (16)
-
-/* Define the synthetic interrupt message page layout. */
-struct hv_message_page {
- struct hv_message sint_message[HV_SYNIC_SINT_COUNT];
-};
-
-/* Define the synthetic interrupt controller event flags format. */
-union hv_synic_event_flags {
- u8 flags8[HV_EVENT_FLAGS_BYTE_COUNT];
- u32 flags32[HV_EVENT_FLAGS_DWORD_COUNT];
-};
-
-/* Define the synthetic interrupt flags page layout. */
-struct hv_synic_event_flags_page {
- union hv_synic_event_flags sintevent_flags[HV_SYNIC_SINT_COUNT];
-};
-
-/* Define SynIC control register. */
-union hv_synic_scontrol {
- u64 as_uint64;
- struct {
- u64 enable:1;
- u64 reserved:63;
- };
-};
-
-/* Define synthetic interrupt source. */
-union hv_synic_sint {
- u64 as_uint64;
- struct {
- u64 vector:8;
- u64 reserved1:8;
- u64 masked:1;
- u64 auto_eoi:1;
- u64 reserved2:46;
- };
-};
-
-/* Define the format of the SIMP register */
-union hv_synic_simp {
- u64 as_uint64;
- struct {
- u64 simp_enabled:1;
- u64 preserved:11;
- u64 base_simp_gpa:52;
- };
-};
-
-/* Define the format of the SIEFP register */
-union hv_synic_siefp {
- u64 as_uint64;
- struct {
- u64 siefp_enabled:1;
- u64 preserved:11;
- u64 base_siefp_gpa:52;
- };
-};
-
-/* Definitions for the monitored notification facility */
-union hv_monitor_trigger_group {
- u64 as_uint64;
- struct {
- u32 pending;
- u32 armed;
- };
-};
-
-struct hv_monitor_parameter {
- union hv_connection_id connectionid;
- u16 flagnumber;
- u16 rsvdz;
-};
-
-union hv_monitor_trigger_state {
- u32 asu32;
-
- struct {
- u32 group_enable:4;
- u32 rsvdz:28;
- };
-};
-
-/* struct hv_monitor_page Layout */
-/* ------------------------------------------------------ */
-/* | 0 | TriggerState (4 bytes) | Rsvd1 (4 bytes) | */
-/* | 8 | TriggerGroup[0] | */
-/* | 10 | TriggerGroup[1] | */
-/* | 18 | TriggerGroup[2] | */
-/* | 20 | TriggerGroup[3] | */
-/* | 28 | Rsvd2[0] | */
-/* | 30 | Rsvd2[1] | */
-/* | 38 | Rsvd2[2] | */
-/* | 40 | NextCheckTime[0][0] | NextCheckTime[0][1] | */
-/* | ... | */
-/* | 240 | Latency[0][0..3] | */
-/* | 340 | Rsvz3[0] | */
-/* | 440 | Parameter[0][0] | */
-/* | 448 | Parameter[0][1] | */
-/* | ... | */
-/* | 840 | Rsvd4[0] | */
-/* ------------------------------------------------------ */
-struct hv_monitor_page {
- union hv_monitor_trigger_state trigger_state;
- u32 rsvdz1;
-
- union hv_monitor_trigger_group trigger_group[4];
- u64 rsvdz2[3];
-
- s32 next_checktime[4][32];
-
- u16 latency[4][32];
- u64 rsvdz3[32];
-
- struct hv_monitor_parameter parameter[4][32];
-
- u8 rsvdz4[1984];
-};
-
-/* Declare the various hypercall operations. */
-enum hv_call_code {
- HVCALL_POST_MESSAGE = 0x005c,
- HVCALL_SIGNAL_EVENT = 0x005d,
-};
-
-/* Definition of the hv_post_message hypercall input structure. */
-struct hv_input_post_message {
- union hv_connection_id connectionid;
- u32 reserved;
- enum hv_message_type message_type;
- u32 payload_size;
- u64 payload[HV_MESSAGE_PAYLOAD_QWORD_COUNT];
-};
-
-/* Definition of the hv_signal_event hypercall input structure. */
-struct hv_input_signal_event {
- union hv_connection_id connectionid;
- u16 flag_number;
- u16 rsvdz;
-};
-
-/*
- * Versioning definitions used for guests reporting themselves to the
- * hypervisor, and visa versa.
- */
-
-/* Version info reported by guest OS's */
-enum hv_guest_os_vendor {
- HVGUESTOS_VENDOR_MICROSOFT = 0x0001
-};
-
-enum hv_guest_os_microsoft_ids {
- HVGUESTOS_MICROSOFT_UNDEFINED = 0x00,
- HVGUESTOS_MICROSOFT_MSDOS = 0x01,
- HVGUESTOS_MICROSOFT_WINDOWS3X = 0x02,
- HVGUESTOS_MICROSOFT_WINDOWS9X = 0x03,
- HVGUESTOS_MICROSOFT_WINDOWSNT = 0x04,
- HVGUESTOS_MICROSOFT_WINDOWSCE = 0x05
-};
-
-/*
- * Declare the MSR used to identify the guest OS.
- */
-#define HV_X64_MSR_GUEST_OS_ID 0x40000000
-
-union hv_x64_msr_guest_os_id_contents {
- u64 as_uint64;
- struct {
- u64 build_number:16;
- u64 service_version:8; /* Service Pack, etc. */
- u64 minor_version:8;
- u64 major_version:8;
- u64 os_id:8; /* enum hv_guest_os_microsoft_ids (if Vendor=MS) */
- u64 vendor_id:16; /* enum hv_guest_os_vendor */
- };
-};
-
-/*
- * Declare the MSR used to setup pages used to communicate with the hypervisor.
- */
-#define HV_X64_MSR_HYPERCALL 0x40000001
-
-union hv_x64_msr_hypercall_contents {
- u64 as_uint64;
- struct {
- u64 enable:1;
- u64 reserved:11;
- u64 guest_physical_address:52;
- };
-};
-
-#endif
diff --git a/drivers/staging/hv/hv_kvp.c b/drivers/staging/hv/hv_kvp.c
index faf692e..13b0ecf 100644
--- a/drivers/staging/hv/hv_kvp.c
+++ b/drivers/staging/hv/hv_kvp.c
@@ -20,23 +20,14 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
*
*/
-
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/net.h>
#include <linux/nls.h>
#include <linux/connector.h>
#include <linux/workqueue.h>
-#include "logging.h"
-#include "hv_api.h"
-#include "vmbus.h"
-#include "vmbus_packet_format.h"
-#include "vmbus_channel_interface.h"
-#include "version_info.h"
-#include "channel.h"
-#include "vmbus_private.h"
-#include "vmbus_api.h"
-#include "utils.h"
+#include "hyperv.h"
#include "hv_kvp.h"
@@ -114,7 +105,7 @@
message = (struct hv_ku_msg *)msg->data;
if (msg->seq == KVP_REGISTER) {
- printk(KERN_INFO "KVP: user-mode registering done.\n");
+ pr_info("KVP: user-mode registering done.\n");
kvp_register();
}
@@ -174,7 +165,7 @@
/*
* This is a spurious call!
*/
- printk(KERN_WARNING "KVP: Transaction not active\n");
+ pr_warn("KVP: Transaction not active\n");
return;
}
/*
@@ -259,9 +250,6 @@
vmbus_recvpacket(channel, recv_buffer, PAGE_SIZE, &recvlen, &requestid);
if (recvlen > 0) {
- DPRINT_DBG(VMBUS, "KVP packet: len=%d, requestid=%lld",
- recvlen, requestid);
-
icmsghdrp = (struct icmsg_hdr *)&recv_buffer[
sizeof(struct vmbuspipe_hdr)];
diff --git a/drivers/staging/hv/hv_mouse.c b/drivers/staging/hv/hv_mouse.c
index 118c7be..359e737 100644
--- a/drivers/staging/hv/hv_mouse.c
+++ b/drivers/staging/hv/hv_mouse.c
@@ -26,13 +26,7 @@
#include <linux/dmi.h>
#include <linux/delay.h>
-#include "hv_api.h"
-#include "logging.h"
-#include "version_info.h"
-#include "vmbus.h"
-#include "vmbus_api.h"
-#include "channel.h"
-#include "vmbus_packet_format.h"
+#include "hyperv.h"
/*
@@ -45,13 +39,6 @@
char name[128];
};
-/* Represents the input vsc driver */
-/* FIXME - can be removed entirely */
-struct mousevsc_drv_obj {
- struct hv_driver Base;
-};
-
-
/* The maximum size of a synthetic input message. */
#define SYNTHHID_MAX_INPUT_REPORT_SIZE 16
@@ -169,23 +156,23 @@
* Represents an mousevsc device
*/
struct mousevsc_dev {
- struct hv_device *Device;
+ struct hv_device *device;
/* 0 indicates the device is being destroyed */
- atomic_t RefCount;
- int NumOutstandingRequests;
- unsigned char bInitializeComplete;
- struct mousevsc_prt_msg ProtocolReq;
- struct mousevsc_prt_msg ProtocolResp;
+ atomic_t ref_count;
+ int num_outstanding_req;
+ unsigned char init_complete;
+ struct mousevsc_prt_msg protocol_req;
+ struct mousevsc_prt_msg protocol_resp;
/* Synchronize the request/response if needed */
- wait_queue_head_t ProtocolWaitEvent;
- wait_queue_head_t DeviceInfoWaitEvent;
+ wait_queue_head_t protocol_wait_event;
+ wait_queue_head_t dev_info_wait_event;
int protocol_wait_condition;
int device_wait_condition;
- int DeviceInfoStatus;
+ int dev_info_status;
- struct hid_descriptor *HidDesc;
- unsigned char *ReportDesc;
- u32 ReportDescSize;
+ struct hid_descriptor *hid_desc;
+ unsigned char *report_desc;
+ u32 report_desc_size;
struct hv_input_dev_info hid_dev_info;
};
@@ -202,41 +189,41 @@
static void inputreport_callback(struct hv_device *dev, void *packet, u32 len);
static void reportdesc_callback(struct hv_device *dev, void *packet, u32 len);
-static struct mousevsc_dev *AllocInputDevice(struct hv_device *Device)
+static struct mousevsc_dev *alloc_input_device(struct hv_device *device)
{
- struct mousevsc_dev *inputDevice;
+ struct mousevsc_dev *input_dev;
- inputDevice = kzalloc(sizeof(struct mousevsc_dev), GFP_KERNEL);
+ input_dev = kzalloc(sizeof(struct mousevsc_dev), GFP_KERNEL);
- if (!inputDevice)
+ if (!input_dev)
return NULL;
/*
* Set to 2 to allow both inbound and outbound traffics
- * (ie GetInputDevice() and MustGetInputDevice()) to proceed.
+ * (ie get_input_device() and must_get_input_device()) to proceed.
*/
- atomic_cmpxchg(&inputDevice->RefCount, 0, 2);
+ atomic_cmpxchg(&input_dev->ref_count, 0, 2);
- inputDevice->Device = Device;
- Device->ext = inputDevice;
+ input_dev->device = device;
+ device->ext = input_dev;
- return inputDevice;
+ return input_dev;
}
-static void FreeInputDevice(struct mousevsc_dev *Device)
+static void free_input_device(struct mousevsc_dev *device)
{
- WARN_ON(atomic_read(&Device->RefCount) == 0);
- kfree(Device);
+ WARN_ON(atomic_read(&device->ref_count) == 0);
+ kfree(device);
}
/*
* Get the inputdevice object if exists and its refcount > 1
*/
-static struct mousevsc_dev *GetInputDevice(struct hv_device *Device)
+static struct mousevsc_dev *get_input_device(struct hv_device *device)
{
- struct mousevsc_dev *inputDevice;
+ struct mousevsc_dev *input_dev;
- inputDevice = (struct mousevsc_dev *)Device->ext;
+ input_dev = (struct mousevsc_dev *)device->ext;
/*
* FIXME
@@ -244,134 +231,137 @@
* what the intention is...
*
* printk(KERN_ERR "-------------------------> REFCOUNT = %d",
- * inputDevice->RefCount);
+ * input_dev->ref_count);
*/
- if (inputDevice && atomic_read(&inputDevice->RefCount) > 1)
- atomic_inc(&inputDevice->RefCount);
+ if (input_dev && atomic_read(&input_dev->ref_count) > 1)
+ atomic_inc(&input_dev->ref_count);
else
- inputDevice = NULL;
+ input_dev = NULL;
- return inputDevice;
+ return input_dev;
}
/*
* Get the inputdevice object iff exists and its refcount > 0
*/
-static struct mousevsc_dev *MustGetInputDevice(struct hv_device *Device)
+static struct mousevsc_dev *must_get_input_device(struct hv_device *device)
{
- struct mousevsc_dev *inputDevice;
+ struct mousevsc_dev *input_dev;
- inputDevice = (struct mousevsc_dev *)Device->ext;
+ input_dev = (struct mousevsc_dev *)device->ext;
- if (inputDevice && atomic_read(&inputDevice->RefCount))
- atomic_inc(&inputDevice->RefCount);
+ if (input_dev && atomic_read(&input_dev->ref_count))
+ atomic_inc(&input_dev->ref_count);
else
- inputDevice = NULL;
+ input_dev = NULL;
- return inputDevice;
+ return input_dev;
}
-static void PutInputDevice(struct hv_device *Device)
+static void put_input_device(struct hv_device *device)
{
- struct mousevsc_dev *inputDevice;
+ struct mousevsc_dev *input_dev;
- inputDevice = (struct mousevsc_dev *)Device->ext;
+ input_dev = (struct mousevsc_dev *)device->ext;
- atomic_dec(&inputDevice->RefCount);
+ atomic_dec(&input_dev->ref_count);
}
/*
- * Drop ref count to 1 to effectively disable GetInputDevice()
+ * Drop ref count to 1 to effectively disable get_input_device()
*/
-static struct mousevsc_dev *ReleaseInputDevice(struct hv_device *Device)
+static struct mousevsc_dev *release_input_device(struct hv_device *device)
{
- struct mousevsc_dev *inputDevice;
+ struct mousevsc_dev *input_dev;
- inputDevice = (struct mousevsc_dev *)Device->ext;
+ input_dev = (struct mousevsc_dev *)device->ext;
/* Busy wait until the ref drop to 2, then set it to 1 */
- while (atomic_cmpxchg(&inputDevice->RefCount, 2, 1) != 2)
+ while (atomic_cmpxchg(&input_dev->ref_count, 2, 1) != 2)
udelay(100);
- return inputDevice;
+ return input_dev;
}
/*
- * Drop ref count to 0. No one can use InputDevice object.
+ * Drop ref count to 0. No one can use input_device object.
*/
-static struct mousevsc_dev *FinalReleaseInputDevice(struct hv_device *Device)
+static struct mousevsc_dev *final_release_input_device(struct hv_device *device)
{
- struct mousevsc_dev *inputDevice;
+ struct mousevsc_dev *input_dev;
- inputDevice = (struct mousevsc_dev *)Device->ext;
+ input_dev = (struct mousevsc_dev *)device->ext;
/* Busy wait until the ref drop to 1, then set it to 0 */
- while (atomic_cmpxchg(&inputDevice->RefCount, 1, 0) != 1)
+ while (atomic_cmpxchg(&input_dev->ref_count, 1, 0) != 1)
udelay(100);
- Device->ext = NULL;
- return inputDevice;
+ device->ext = NULL;
+ return input_dev;
}
-static void MousevscOnSendCompletion(struct hv_device *Device, struct vmpacket_descriptor *Packet)
+static void mousevsc_on_send_completion(struct hv_device *device,
+ struct vmpacket_descriptor *packet)
{
- struct mousevsc_dev *inputDevice;
+ struct mousevsc_dev *input_dev;
void *request;
- inputDevice = MustGetInputDevice(Device);
- if (!inputDevice) {
+ input_dev = must_get_input_device(device);
+ if (!input_dev) {
pr_err("unable to get input device...device being destroyed?");
return;
}
- request = (void *)(unsigned long)Packet->trans_id;
+ request = (void *)(unsigned long)packet->trans_id;
- if (request == &inputDevice->ProtocolReq) {
+ if (request == &input_dev->protocol_req) {
/* FIXME */
/* Shouldn't we be doing something here? */
}
- PutInputDevice(Device);
+ put_input_device(device);
}
-static void MousevscOnReceiveDeviceInfo(struct mousevsc_dev *InputDevice, struct synthhid_device_info *DeviceInfo)
+static void mousevsc_on_receive_device_info(struct mousevsc_dev *input_device,
+ struct synthhid_device_info *device_info)
{
int ret = 0;
struct hid_descriptor *desc;
struct mousevsc_prt_msg ack;
/* Assume success for now */
- InputDevice->DeviceInfoStatus = 0;
+ input_device->dev_info_status = 0;
/* Save the device attr */
- memcpy(&InputDevice->hid_dev_info, &DeviceInfo->hid_dev_info, sizeof(struct hv_input_dev_info));
+ memcpy(&input_device->hid_dev_info, &device_info->hid_dev_info,
+ sizeof(struct hv_input_dev_info));
/* Save the hid desc */
- desc = &DeviceInfo->hid_descriptor;
+ desc = &device_info->hid_descriptor;
WARN_ON(desc->bLength > 0);
- InputDevice->HidDesc = kzalloc(desc->bLength, GFP_KERNEL);
+ input_device->hid_desc = kzalloc(desc->bLength, GFP_KERNEL);
- if (!InputDevice->HidDesc) {
+ if (!input_device->hid_desc) {
pr_err("unable to allocate hid descriptor - size %d", desc->bLength);
goto Cleanup;
}
- memcpy(InputDevice->HidDesc, desc, desc->bLength);
+ memcpy(input_device->hid_desc, desc, desc->bLength);
/* Save the report desc */
- InputDevice->ReportDescSize = desc->desc[0].wDescriptorLength;
- InputDevice->ReportDesc = kzalloc(InputDevice->ReportDescSize,
+ input_device->report_desc_size = desc->desc[0].wDescriptorLength;
+ input_device->report_desc = kzalloc(input_device->report_desc_size,
GFP_KERNEL);
- if (!InputDevice->ReportDesc) {
+ if (!input_device->report_desc) {
pr_err("unable to allocate report descriptor - size %d",
- InputDevice->ReportDescSize);
+ input_device->report_desc_size);
goto Cleanup;
}
- memcpy(InputDevice->ReportDesc,
+ memcpy(input_device->report_desc,
((unsigned char *)desc) + desc->bLength,
desc->desc[0].wDescriptorLength);
@@ -385,7 +375,7 @@
ack.ack.header.size = 1;
ack.ack.reserved = 0;
- ret = vmbus_sendpacket(InputDevice->Device->channel,
+ ret = vmbus_sendpacket(input_device->device->channel,
&ack,
sizeof(struct pipe_prt_msg) - sizeof(unsigned char) +
sizeof(struct synthhid_device_info_ack),
@@ -398,138 +388,143 @@
goto Cleanup;
}
- InputDevice->device_wait_condition = 1;
- wake_up(&InputDevice->DeviceInfoWaitEvent);
+ input_device->device_wait_condition = 1;
+ wake_up(&input_device->dev_info_wait_event);
return;
Cleanup:
- kfree(InputDevice->HidDesc);
- InputDevice->HidDesc = NULL;
+ kfree(input_device->hid_desc);
+ input_device->hid_desc = NULL;
- kfree(InputDevice->ReportDesc);
- InputDevice->ReportDesc = NULL;
+ kfree(input_device->report_desc);
+ input_device->report_desc = NULL;
- InputDevice->DeviceInfoStatus = -1;
- InputDevice->device_wait_condition = 1;
- wake_up(&InputDevice->DeviceInfoWaitEvent);
+ input_device->dev_info_status = -1;
+ input_device->device_wait_condition = 1;
+ wake_up(&input_device->dev_info_wait_event);
}
-static void MousevscOnReceiveInputReport(struct mousevsc_dev *InputDevice, struct synthhid_input_report *InputReport)
+static void mousevsc_on_receive_input_report(struct mousevsc_dev *input_device,
+ struct synthhid_input_report *input_report)
{
- struct mousevsc_drv_obj *inputDriver;
+ struct hv_driver *input_drv;
- if (!InputDevice->bInitializeComplete) {
- pr_info("Initialization incomplete...ignoring InputReport msg");
+ if (!input_device->init_complete) {
+ pr_info("Initialization incomplete...ignoring input_report msg");
return;
}
- inputDriver = (struct mousevsc_drv_obj *)InputDevice->Device->drv;
+ input_drv = drv_to_hv_drv(input_device->device->device.driver);
- inputreport_callback(InputDevice->Device,
- InputReport->buffer,
- InputReport->header.size);
+ inputreport_callback(input_device->device,
+ input_report->buffer,
+ input_report->header.size);
}
-static void MousevscOnReceive(struct hv_device *Device, struct vmpacket_descriptor *Packet)
+static void mousevsc_on_receive(struct hv_device *device,
+ struct vmpacket_descriptor *packet)
{
- struct pipe_prt_msg *pipeMsg;
- struct synthhid_msg *hidMsg;
- struct mousevsc_dev *inputDevice;
+ struct pipe_prt_msg *pipe_msg;
+ struct synthhid_msg *hid_msg;
+ struct mousevsc_dev *input_dev;
- inputDevice = MustGetInputDevice(Device);
- if (!inputDevice) {
+ input_dev = must_get_input_device(device);
+ if (!input_dev) {
pr_err("unable to get input device...device being destroyed?");
return;
}
- pipeMsg = (struct pipe_prt_msg *)((unsigned long)Packet + (Packet->offset8 << 3));
+ pipe_msg = (struct pipe_prt_msg *)((unsigned long)packet +
+ (packet->offset8 << 3));
- if (pipeMsg->type != PipeMessageData) {
+ if (pipe_msg->type != PipeMessageData) {
pr_err("unknown pipe msg type - type %d len %d",
- pipeMsg->type, pipeMsg->size);
- PutInputDevice(Device);
+ pipe_msg->type, pipe_msg->size);
+ put_input_device(device);
return ;
}
- hidMsg = (struct synthhid_msg *)&pipeMsg->data[0];
+ hid_msg = (struct synthhid_msg *)&pipe_msg->data[0];
- switch (hidMsg->header.type) {
+ switch (hid_msg->header.type) {
case SynthHidProtocolResponse:
- memcpy(&inputDevice->ProtocolResp, pipeMsg,
- pipeMsg->size + sizeof(struct pipe_prt_msg) -
+ memcpy(&input_dev->protocol_resp, pipe_msg,
+ pipe_msg->size + sizeof(struct pipe_prt_msg) -
sizeof(unsigned char));
- inputDevice->protocol_wait_condition = 1;
- wake_up(&inputDevice->ProtocolWaitEvent);
+ input_dev->protocol_wait_condition = 1;
+ wake_up(&input_dev->protocol_wait_event);
break;
case SynthHidInitialDeviceInfo:
- WARN_ON(pipeMsg->size >= sizeof(struct hv_input_dev_info));
+ WARN_ON(pipe_msg->size >= sizeof(struct hv_input_dev_info));
/*
* Parse out the device info into device attr,
* hid desc and report desc
*/
- MousevscOnReceiveDeviceInfo(inputDevice,
- (struct synthhid_device_info *)&pipeMsg->data[0]);
+ mousevsc_on_receive_device_info(input_dev,
+ (struct synthhid_device_info *)&pipe_msg->data[0]);
break;
case SynthHidInputReport:
- MousevscOnReceiveInputReport(inputDevice,
- (struct synthhid_input_report *)&pipeMsg->data[0]);
+ mousevsc_on_receive_input_report(input_dev,
+ (struct synthhid_input_report *)&pipe_msg->data[0]);
break;
default:
pr_err("unsupported hid msg type - type %d len %d",
- hidMsg->header.type, hidMsg->header.size);
+ hid_msg->header.type, hid_msg->header.size);
break;
}
- PutInputDevice(Device);
+ put_input_device(device);
}
-static void MousevscOnChannelCallback(void *Context)
+static void mousevsc_on_channel_callback(void *context)
{
const int packetSize = 0x100;
int ret = 0;
- struct hv_device *device = (struct hv_device *)Context;
- struct mousevsc_dev *inputDevice;
+ struct hv_device *device = (struct hv_device *)context;
+ struct mousevsc_dev *input_dev;
- u32 bytesRecvd;
- u64 requestId;
- unsigned char packet[packetSize];
+ u32 bytes_recvd;
+ u64 req_id;
+ unsigned char packet[0x100];
struct vmpacket_descriptor *desc;
unsigned char *buffer = packet;
int bufferlen = packetSize;
- inputDevice = MustGetInputDevice(device);
+ input_dev = must_get_input_device(device);
- if (!inputDevice) {
+ if (!input_dev) {
pr_err("unable to get input device...device being destroyed?");
return;
}
do {
- ret = vmbus_recvpacket_raw(device->channel, buffer, bufferlen, &bytesRecvd, &requestId);
+ ret = vmbus_recvpacket_raw(device->channel, buffer,
+ bufferlen, &bytes_recvd, &req_id);
if (ret == 0) {
- if (bytesRecvd > 0) {
+ if (bytes_recvd > 0) {
desc = (struct vmpacket_descriptor *)buffer;
switch (desc->type) {
case VM_PKT_COMP:
- MousevscOnSendCompletion(device,
- desc);
+ mousevsc_on_send_completion(
+ device, desc);
break;
case VM_PKT_DATA_INBAND:
- MousevscOnReceive(device, desc);
+ mousevsc_on_receive(
+ device, desc);
break;
default:
pr_err("unhandled packet type %d, tid %llx len %d\n",
desc->type,
- requestId,
- bytesRecvd);
+ req_id,
+ bytes_recvd);
break;
}
@@ -555,8 +550,8 @@
}
} else if (ret == -2) {
/* Handle large packet */
- bufferlen = bytesRecvd;
- buffer = kzalloc(bytesRecvd, GFP_KERNEL);
+ bufferlen = bytes_recvd;
+ buffer = kzalloc(bytes_recvd, GFP_KERNEL);
if (buffer == NULL) {
buffer = packet;
@@ -564,35 +559,35 @@
/* Try again next time around */
pr_err("unable to allocate buffer of size %d!",
- bytesRecvd);
+ bytes_recvd);
break;
}
}
} while (1);
- PutInputDevice(device);
+ put_input_device(device);
return;
}
-static int MousevscConnectToVsp(struct hv_device *Device)
+static int mousevsc_connect_to_vsp(struct hv_device *device)
{
int ret = 0;
- struct mousevsc_dev *inputDevice;
+ struct mousevsc_dev *input_dev;
struct mousevsc_prt_msg *request;
struct mousevsc_prt_msg *response;
- inputDevice = GetInputDevice(Device);
+ input_dev = get_input_device(device);
- if (!inputDevice) {
+ if (!input_dev) {
pr_err("unable to get input device...device being destroyed?");
return -1;
}
- init_waitqueue_head(&inputDevice->ProtocolWaitEvent);
- init_waitqueue_head(&inputDevice->DeviceInfoWaitEvent);
+ init_waitqueue_head(&input_dev->protocol_wait_event);
+ init_waitqueue_head(&input_dev->dev_info_wait_event);
- request = &inputDevice->ProtocolReq;
+ request = &input_dev->protocol_req;
/*
* Now, initiate the vsc/vsp initialization protocol on the open channel
@@ -608,7 +603,7 @@
pr_info("synthhid protocol request...");
- ret = vmbus_sendpacket(Device->channel, request,
+ ret = vmbus_sendpacket(device->channel, request,
sizeof(struct pipe_prt_msg) -
sizeof(unsigned char) +
sizeof(struct synthhid_protocol_request),
@@ -620,14 +615,15 @@
goto Cleanup;
}
- inputDevice->protocol_wait_condition = 0;
- wait_event_timeout(inputDevice->ProtocolWaitEvent, inputDevice->protocol_wait_condition, msecs_to_jiffies(1000));
- if (inputDevice->protocol_wait_condition == 0) {
+ input_dev->protocol_wait_condition = 0;
+ wait_event_timeout(input_dev->protocol_wait_event,
+ input_dev->protocol_wait_condition, msecs_to_jiffies(1000));
+ if (input_dev->protocol_wait_condition == 0) {
ret = -ETIMEDOUT;
goto Cleanup;
}
- response = &inputDevice->ProtocolResp;
+ response = &input_dev->protocol_resp;
if (!response->response.approved) {
pr_err("synthhid protocol request failed (version %d)",
@@ -636,9 +632,10 @@
goto Cleanup;
}
- inputDevice->device_wait_condition = 0;
- wait_event_timeout(inputDevice->DeviceInfoWaitEvent, inputDevice->device_wait_condition, msecs_to_jiffies(1000));
- if (inputDevice->device_wait_condition == 0) {
+ input_dev->device_wait_condition = 0;
+ wait_event_timeout(input_dev->dev_info_wait_event,
+ input_dev->device_wait_condition, msecs_to_jiffies(1000));
+ if (input_dev->device_wait_condition == 0) {
ret = -ETIMEDOUT;
goto Cleanup;
}
@@ -647,94 +644,95 @@
* We should have gotten the device attr, hid desc and report
* desc at this point
*/
- if (!inputDevice->DeviceInfoStatus)
+ if (!input_dev->dev_info_status)
pr_info("**** input channel up and running!! ****");
else
ret = -1;
Cleanup:
- PutInputDevice(Device);
+ put_input_device(device);
return ret;
}
-static int MousevscOnDeviceAdd(struct hv_device *Device, void *AdditionalInfo)
+static int mousevsc_on_device_add(struct hv_device *device,
+ void *additional_info)
{
int ret = 0;
- struct mousevsc_dev *inputDevice;
- struct mousevsc_drv_obj *inputDriver;
+ struct mousevsc_dev *input_dev;
+ struct hv_driver *input_drv;
struct hv_input_dev_info dev_info;
- inputDevice = AllocInputDevice(Device);
+ input_dev = alloc_input_device(device);
- if (!inputDevice) {
+ if (!input_dev) {
ret = -1;
goto Cleanup;
}
- inputDevice->bInitializeComplete = false;
+ input_dev->init_complete = false;
/* Open the channel */
- ret = vmbus_open(Device->channel,
+ ret = vmbus_open(device->channel,
INPUTVSC_SEND_RING_BUFFER_SIZE,
INPUTVSC_RECV_RING_BUFFER_SIZE,
NULL,
0,
- MousevscOnChannelCallback,
- Device
+ mousevsc_on_channel_callback,
+ device
);
if (ret != 0) {
pr_err("unable to open channel: %d", ret);
- FreeInputDevice(inputDevice);
+ free_input_device(input_dev);
return -1;
}
pr_info("InputVsc channel open: %d", ret);
- ret = MousevscConnectToVsp(Device);
+ ret = mousevsc_connect_to_vsp(device);
if (ret != 0) {
pr_err("unable to connect channel: %d", ret);
- vmbus_close(Device->channel);
- FreeInputDevice(inputDevice);
+ vmbus_close(device->channel);
+ free_input_device(input_dev);
return ret;
}
- inputDriver = (struct mousevsc_drv_obj *)inputDevice->Device->drv;
+ input_drv = drv_to_hv_drv(input_dev->device->device.driver);
- dev_info.vendor = inputDevice->hid_dev_info.vendor;
- dev_info.product = inputDevice->hid_dev_info.product;
- dev_info.version = inputDevice->hid_dev_info.version;
+ dev_info.vendor = input_dev->hid_dev_info.vendor;
+ dev_info.product = input_dev->hid_dev_info.product;
+ dev_info.version = input_dev->hid_dev_info.version;
strcpy(dev_info.name, "Microsoft Vmbus HID-compliant Mouse");
/* Send the device info back up */
- deviceinfo_callback(Device, &dev_info);
+ deviceinfo_callback(device, &dev_info);
/* Send the report desc back up */
/* workaround SA-167 */
- if (inputDevice->ReportDesc[14] == 0x25)
- inputDevice->ReportDesc[14] = 0x29;
+ if (input_dev->report_desc[14] == 0x25)
+ input_dev->report_desc[14] = 0x29;
- reportdesc_callback(Device, inputDevice->ReportDesc,
- inputDevice->ReportDescSize);
+ reportdesc_callback(device, input_dev->report_desc,
+ input_dev->report_desc_size);
- inputDevice->bInitializeComplete = true;
+ input_dev->init_complete = true;
Cleanup:
return ret;
}
-static int MousevscOnDeviceRemove(struct hv_device *Device)
+static int mousevsc_on_device_remove(struct hv_device *device)
{
- struct mousevsc_dev *inputDevice;
+ struct mousevsc_dev *input_dev;
int ret = 0;
pr_info("disabling input device (%p)...",
- Device->ext);
+ device->ext);
- inputDevice = ReleaseInputDevice(Device);
+ input_dev = release_input_device(device);
/*
@@ -743,29 +741,27 @@
*
* so that outstanding requests can be completed.
*/
- while (inputDevice->NumOutstandingRequests) {
- pr_info("waiting for %d requests to complete...", inputDevice->NumOutstandingRequests);
+ while (input_dev->num_outstanding_req) {
+ pr_info("waiting for %d requests to complete...",
+ input_dev->num_outstanding_req);
udelay(100);
}
- pr_info("removing input device (%p)...", Device->ext);
+ pr_info("removing input device (%p)...", device->ext);
- inputDevice = FinalReleaseInputDevice(Device);
+ input_dev = final_release_input_device(device);
- pr_info("input device (%p) safe to remove", inputDevice);
+ pr_info("input device (%p) safe to remove", input_dev);
/* Close the channel */
- vmbus_close(Device->channel);
+ vmbus_close(device->channel);
- FreeInputDevice(inputDevice);
+ free_input_device(input_dev);
return ret;
}
-static void MousevscOnCleanup(struct hv_driver *drv)
-{
-}
/*
* Data types
@@ -778,8 +774,6 @@
};
-static struct mousevsc_drv_obj g_mousevsc_drv;
-
static void deviceinfo_callback(struct hv_device *dev, struct hv_input_dev_info *info)
{
struct input_device_context *input_device_ctx =
@@ -813,24 +807,19 @@
{
}
-static int mousevsc_probe(struct device *device)
+static int mousevsc_probe(struct hv_device *dev)
{
int ret = 0;
- struct hv_driver *drv =
- drv_to_hv_drv(device->driver);
- struct mousevsc_drv_obj *mousevsc_drv_obj = drv->priv;
-
- struct hv_device *device_obj = device_to_hv_device(device);
struct input_device_context *input_dev_ctx;
input_dev_ctx = kmalloc(sizeof(struct input_device_context),
GFP_KERNEL);
- dev_set_drvdata(device, input_dev_ctx);
+ dev_set_drvdata(&dev->device, input_dev_ctx);
/* Call to the vsc driver to add the device */
- ret = mousevsc_drv_obj->Base.dev_add(device_obj, NULL);
+ ret = mousevsc_on_device_add(dev, NULL);
if (ret != 0) {
DPRINT_ERR(INPUTVSC_DRV, "unable to add input vsc device");
@@ -841,35 +830,27 @@
return 0;
}
-static int mousevsc_remove(struct device *device)
+static int mousevsc_remove(struct hv_device *dev)
{
int ret = 0;
- struct hv_driver *drv =
- drv_to_hv_drv(device->driver);
- struct mousevsc_drv_obj *mousevsc_drv_obj = drv->priv;
-
- struct hv_device *device_obj = device_to_hv_device(device);
struct input_device_context *input_dev_ctx;
input_dev_ctx = kmalloc(sizeof(struct input_device_context),
GFP_KERNEL);
- dev_set_drvdata(device, input_dev_ctx);
+ dev_set_drvdata(&dev->device, input_dev_ctx);
if (input_dev_ctx->connected) {
hidinput_disconnect(input_dev_ctx->hid_device);
input_dev_ctx->connected = 0;
}
- if (!mousevsc_drv_obj->Base.dev_rm)
- return -1;
-
/*
* Call to the vsc driver to let it know that the device
* is being removed
*/
- ret = mousevsc_drv_obj->Base.dev_rm(device_obj);
+ ret = mousevsc_on_device_remove(dev);
if (ret != 0) {
DPRINT_ERR(INPUTVSC_DRV,
@@ -934,81 +915,28 @@
kfree(hid_dev);
}
-static int mousevsc_drv_exit_cb(struct device *dev, void *data)
-{
- struct device **curr = (struct device **)data;
- *curr = dev;
- return 1;
-}
+static struct hv_driver mousevsc_drv = {
+ .probe = mousevsc_probe,
+ .remove = mousevsc_remove,
+};
static void mousevsc_drv_exit(void)
{
- struct mousevsc_drv_obj *mousevsc_drv_obj = &g_mousevsc_drv;
- struct hv_driver *drv = &g_mousevsc_drv.Base;
- int ret;
-
- struct device *current_dev = NULL;
-
- while (1) {
- current_dev = NULL;
-
- /* Get the device */
- ret = driver_for_each_device(&drv->driver, NULL,
- (void *)¤t_dev,
- mousevsc_drv_exit_cb);
- if (ret)
- printk(KERN_ERR "Can't find mouse device!\n");
-
- if (current_dev == NULL)
- break;
-
- /* Initiate removal from the top-down */
- device_unregister(current_dev);
- }
-
- if (mousevsc_drv_obj->Base.cleanup)
- mousevsc_drv_obj->Base.cleanup(&mousevsc_drv_obj->Base);
-
- vmbus_child_driver_unregister(&drv->driver);
-
- return;
+ vmbus_child_driver_unregister(&mousevsc_drv.driver);
}
-static int mouse_vsc_initialize(struct hv_driver *Driver)
-{
- struct mousevsc_drv_obj *inputDriver =
- (struct mousevsc_drv_obj *)Driver;
- int ret = 0;
-
- Driver->name = driver_name;
- memcpy(&Driver->dev_type, &mouse_guid,
- sizeof(struct hv_guid));
-
- /* Setup the dispatch table */
- inputDriver->Base.dev_add = MousevscOnDeviceAdd;
- inputDriver->Base.dev_rm = MousevscOnDeviceRemove;
- inputDriver->Base.cleanup = MousevscOnCleanup;
-
- return ret;
-}
-
-
static int __init mousevsc_init(void)
{
- struct mousevsc_drv_obj *input_drv_obj = &g_mousevsc_drv;
- struct hv_driver *drv = &g_mousevsc_drv.Base;
+ struct hv_driver *drv = &mousevsc_drv;
DPRINT_INFO(INPUTVSC_DRV, "Hyper-V Mouse driver initializing.");
- /* Callback to client driver to complete the initialization */
- mouse_vsc_initialize(&input_drv_obj->Base);
+ memcpy(&drv->dev_type, &mouse_guid,
+ sizeof(struct hv_guid));
- drv->driver.name = input_drv_obj->Base.name;
- drv->priv = input_drv_obj;
-
- drv->driver.probe = mousevsc_probe;
- drv->driver.remove = mousevsc_remove;
+ drv->driver.name = driver_name;
+ drv->name = driver_name;
/* The driver belongs to vmbus */
vmbus_child_driver_register(&drv->driver);
diff --git a/drivers/staging/hv/hv_timesource.c b/drivers/staging/hv/hv_timesource.c
index a7ee533..0efb049 100644
--- a/drivers/staging/hv/hv_timesource.c
+++ b/drivers/staging/hv/hv_timesource.c
@@ -20,6 +20,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
*
*/
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/version.h>
#include <linux/clocksource.h>
@@ -91,7 +92,7 @@
if (!dmi_check_system(hv_timesource_dmi_table))
return -ENODEV;
- printk(KERN_INFO "Registering HyperV clock source\n");
+ pr_info("Registering HyperV clock source\n");
return clocksource_register(&hyperv_cs);
}
diff --git a/drivers/staging/hv/hv_util.c b/drivers/staging/hv/hv_util.c
index 2df1568..c164b54 100644
--- a/drivers/staging/hv/hv_util.c
+++ b/drivers/staging/hv/hv_util.c
@@ -18,6 +18,8 @@
* Haiyang Zhang <haiyangz@microsoft.com>
* Hank Janssen <hjanssen@microsoft.com>
*/
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/module.h>
@@ -27,16 +29,7 @@
#include <linux/dmi.h>
#include <linux/pci.h>
-#include "logging.h"
-#include "hv_api.h"
-#include "vmbus.h"
-#include "vmbus_packet_format.h"
-#include "vmbus_channel_interface.h"
-#include "version_info.h"
-#include "channel.h"
-#include "vmbus_private.h"
-#include "vmbus_api.h"
-#include "utils.h"
+#include "hyperv.h"
#include "hv_kvp.h"
static u8 *shut_txf_buf;
@@ -59,9 +52,6 @@
PAGE_SIZE, &recvlen, &requestid);
if (recvlen > 0) {
- DPRINT_DBG(VMBUS, "shutdown packet: len=%d, requestid=%lld",
- recvlen, requestid);
-
icmsghdrp = (struct icmsg_hdr *)&shut_txf_buf[
sizeof(struct vmbuspipe_hdr)];
@@ -79,17 +69,17 @@
icmsghdrp->status = HV_S_OK;
execute_shutdown = true;
- DPRINT_INFO(VMBUS, "Shutdown request received -"
- " graceful shutdown initiated");
+ pr_info("Shutdown request received -"
+ " graceful shutdown initiated\n");
break;
default:
icmsghdrp->status = HV_E_FAIL;
execute_shutdown = false;
- DPRINT_INFO(VMBUS, "Shutdown request received -"
- " Invalid request");
+ pr_info("Shutdown request received -"
+ " Invalid request\n");
break;
- };
+ }
}
icmsghdrp->icflags = ICMSGHDRFLAG_TRANSACTION
@@ -159,9 +149,6 @@
PAGE_SIZE, &recvlen, &requestid);
if (recvlen > 0) {
- DPRINT_DBG(VMBUS, "timesync packet: recvlen=%d, requestid=%lld",
- recvlen, requestid);
-
icmsghdrp = (struct icmsg_hdr *)&time_txf_buf[
sizeof(struct vmbuspipe_hdr)];
@@ -200,9 +187,6 @@
PAGE_SIZE, &recvlen, &requestid);
if (recvlen > 0) {
- DPRINT_DBG(VMBUS, "heartbeat packet: len=%d, requestid=%lld",
- recvlen, requestid);
-
icmsghdrp = (struct icmsg_hdr *)&hbeat_txf_buf[
sizeof(struct vmbuspipe_hdr)];
@@ -214,9 +198,6 @@
sizeof(struct vmbuspipe_hdr) +
sizeof(struct icmsg_hdr)];
- DPRINT_DBG(VMBUS, "heartbeat seq = %lld",
- heartbeat_msg->seq_num);
-
heartbeat_msg->seq_num += 1;
}
@@ -254,7 +235,7 @@
static int __init init_hyperv_utils(void)
{
- printk(KERN_INFO "Registering HyperV Utility Driver\n");
+ pr_info("Registering HyperV Utility Driver\n");
if (hv_kvp_init())
return -ENODEV;
@@ -268,52 +249,48 @@
hbeat_txf_buf = kmalloc(PAGE_SIZE, GFP_KERNEL);
if (!shut_txf_buf || !time_txf_buf || !hbeat_txf_buf) {
- printk(KERN_INFO
- "Unable to allocate memory for receive buffer\n");
+ pr_info("Unable to allocate memory for receive buffer\n");
kfree(shut_txf_buf);
kfree(time_txf_buf);
kfree(hbeat_txf_buf);
return -ENOMEM;
}
- hv_cb_utils[HV_SHUTDOWN_MSG].channel->onchannel_callback =
- &shutdown_onchannelcallback;
hv_cb_utils[HV_SHUTDOWN_MSG].callback = &shutdown_onchannelcallback;
- hv_cb_utils[HV_TIMESYNC_MSG].channel->onchannel_callback =
- ×ync_onchannelcallback;
hv_cb_utils[HV_TIMESYNC_MSG].callback = ×ync_onchannelcallback;
- hv_cb_utils[HV_HEARTBEAT_MSG].channel->onchannel_callback =
- &heartbeat_onchannelcallback;
hv_cb_utils[HV_HEARTBEAT_MSG].callback = &heartbeat_onchannelcallback;
- hv_cb_utils[HV_KVP_MSG].channel->onchannel_callback =
- &hv_kvp_onchannelcallback;
-
-
+ hv_cb_utils[HV_KVP_MSG].callback = &hv_kvp_onchannelcallback;
return 0;
}
static void exit_hyperv_utils(void)
{
- printk(KERN_INFO "De-Registered HyperV Utility Driver\n");
+ pr_info("De-Registered HyperV Utility Driver\n");
- hv_cb_utils[HV_SHUTDOWN_MSG].channel->onchannel_callback =
- &chn_cb_negotiate;
- hv_cb_utils[HV_SHUTDOWN_MSG].callback = &chn_cb_negotiate;
+ if (hv_cb_utils[HV_SHUTDOWN_MSG].channel != NULL)
+ hv_cb_utils[HV_SHUTDOWN_MSG].channel->onchannel_callback =
+ &chn_cb_negotiate;
+ hv_cb_utils[HV_SHUTDOWN_MSG].callback = NULL;
- hv_cb_utils[HV_TIMESYNC_MSG].channel->onchannel_callback =
- &chn_cb_negotiate;
- hv_cb_utils[HV_TIMESYNC_MSG].callback = &chn_cb_negotiate;
+ if (hv_cb_utils[HV_TIMESYNC_MSG].channel != NULL)
+ hv_cb_utils[HV_TIMESYNC_MSG].channel->onchannel_callback =
+ &chn_cb_negotiate;
+ hv_cb_utils[HV_TIMESYNC_MSG].callback = NULL;
- hv_cb_utils[HV_HEARTBEAT_MSG].channel->onchannel_callback =
- &chn_cb_negotiate;
- hv_cb_utils[HV_HEARTBEAT_MSG].callback = &chn_cb_negotiate;
+ if (hv_cb_utils[HV_HEARTBEAT_MSG].channel != NULL)
+ hv_cb_utils[HV_HEARTBEAT_MSG].channel->onchannel_callback =
+ &chn_cb_negotiate;
+ hv_cb_utils[HV_HEARTBEAT_MSG].callback = NULL;
- hv_cb_utils[HV_KVP_MSG].channel->onchannel_callback =
- &chn_cb_negotiate;
+ if (hv_cb_utils[HV_KVP_MSG].channel != NULL)
+ hv_cb_utils[HV_KVP_MSG].channel->onchannel_callback =
+ &chn_cb_negotiate;
+ hv_cb_utils[HV_KVP_MSG].callback = NULL;
+
hv_kvp_deinit();
kfree(shut_txf_buf);
diff --git a/drivers/staging/hv/hyperv.h b/drivers/staging/hv/hyperv.h
new file mode 100644
index 0000000..3310e9b
--- /dev/null
+++ b/drivers/staging/hv/hyperv.h
@@ -0,0 +1,944 @@
+/*
+ *
+ * Copyright (c) 2011, Microsoft Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
+ * Place - Suite 330, Boston, MA 02111-1307 USA.
+ *
+ * Authors:
+ * Haiyang Zhang <haiyangz@microsoft.com>
+ * Hank Janssen <hjanssen@microsoft.com>
+ * K. Y. Srinivasan <kys@microsoft.com>
+ *
+ */
+
+#ifndef _HYPERV_H
+#define _HYPERV_H
+
+#include <linux/scatterlist.h>
+#include <linux/list.h>
+#include <linux/timer.h>
+#include <linux/workqueue.h>
+#include <linux/completion.h>
+#include <linux/device.h>
+
+
+#include <asm/hyperv.h>
+
+struct hv_guid {
+ unsigned char data[16];
+};
+
+#define MAX_PAGE_BUFFER_COUNT 16
+#define MAX_MULTIPAGE_BUFFER_COUNT 32 /* 128K */
+
+#pragma pack(push, 1)
+
+/* Single-page buffer */
+struct hv_page_buffer {
+ u32 len;
+ u32 offset;
+ u64 pfn;
+};
+
+/* Multiple-page buffer */
+struct hv_multipage_buffer {
+ /* Length and Offset determines the # of pfns in the array */
+ u32 len;
+ u32 offset;
+ u64 pfn_array[MAX_MULTIPAGE_BUFFER_COUNT];
+};
+
+/* 0x18 includes the proprietary packet header */
+#define MAX_PAGE_BUFFER_PACKET (0x18 + \
+ (sizeof(struct hv_page_buffer) * \
+ MAX_PAGE_BUFFER_COUNT))
+#define MAX_MULTIPAGE_BUFFER_PACKET (0x18 + \
+ sizeof(struct hv_multipage_buffer))
+
+
+#pragma pack(pop)
+
+struct hv_ring_buffer {
+ /* Offset in bytes from the start of ring data below */
+ u32 write_index;
+
+ /* Offset in bytes from the start of ring data below */
+ u32 read_index;
+
+ u32 interrupt_mask;
+
+ /* Pad it to PAGE_SIZE so that data starts on page boundary */
+ u8 reserved[4084];
+
+ /* NOTE:
+ * The interrupt_mask field is used only for channels but since our
+ * vmbus connection also uses this data structure and its data starts
+ * here, we commented out this field.
+ */
+
+ /*
+ * Ring data starts here + RingDataStartOffset
+ * !!! DO NOT place any fields below this !!!
+ */
+ u8 buffer[0];
+} __packed;
+
+struct hv_ring_buffer_info {
+ struct hv_ring_buffer *ring_buffer;
+ u32 ring_size; /* Include the shared header */
+ spinlock_t ring_lock;
+
+ u32 ring_datasize; /* < ring_size */
+ u32 ring_data_startoffset;
+};
+
+struct hv_ring_buffer_debug_info {
+ u32 current_interrupt_mask;
+ u32 current_read_index;
+ u32 current_write_index;
+ u32 bytes_avail_toread;
+ u32 bytes_avail_towrite;
+};
+
+/*
+ * We use the same version numbering for all Hyper-V modules.
+ *
+ * Definition of versioning is as follows;
+ *
+ * Major Number Changes for these scenarios;
+ * 1. When a new version of Windows Hyper-V
+ * is released.
+ * 2. A Major change has occurred in the
+ * Linux IC's.
+ * (For example the merge for the first time
+ * into the kernel) Every time the Major Number
+ * changes, the Revision number is reset to 0.
+ * Minor Number Changes when new functionality is added
+ * to the Linux IC's that is not a bug fix.
+ *
+ * 3.1 - Added completed hv_utils driver. Shutdown/Heartbeat/Timesync
+ */
+#define HV_DRV_VERSION "3.1"
+
+
+/*
+ * A revision number of vmbus that is used for ensuring both ends on a
+ * partition are using compatible versions.
+ */
+#define VMBUS_REVISION_NUMBER 13
+
+/* Make maximum size of pipe payload of 16K */
+#define MAX_PIPE_DATA_PAYLOAD (sizeof(u8) * 16384)
+
+/* Define PipeMode values. */
+#define VMBUS_PIPE_TYPE_BYTE 0x00000000
+#define VMBUS_PIPE_TYPE_MESSAGE 0x00000004
+
+/* The size of the user defined data buffer for non-pipe offers. */
+#define MAX_USER_DEFINED_BYTES 120
+
+/* The size of the user defined data buffer for pipe offers. */
+#define MAX_PIPE_USER_DEFINED_BYTES 116
+
+/*
+ * At the center of the Channel Management library is the Channel Offer. This
+ * struct contains the fundamental information about an offer.
+ */
+struct vmbus_channel_offer {
+ struct hv_guid if_type;
+ struct hv_guid if_instance;
+ u64 int_latency; /* in 100ns units */
+ u32 if_revision;
+ u32 server_ctx_size; /* in bytes */
+ u16 chn_flags;
+ u16 mmio_megabytes; /* in bytes * 1024 * 1024 */
+
+ union {
+ /* Non-pipes: The user has MAX_USER_DEFINED_BYTES bytes. */
+ struct {
+ unsigned char user_def[MAX_USER_DEFINED_BYTES];
+ } std;
+
+ /*
+ * Pipes:
+ * The following sructure is an integrated pipe protocol, which
+ * is implemented on top of standard user-defined data. Pipe
+ * clients have MAX_PIPE_USER_DEFINED_BYTES left for their own
+ * use.
+ */
+ struct {
+ u32 pipe_mode;
+ unsigned char user_def[MAX_PIPE_USER_DEFINED_BYTES];
+ } pipe;
+ } u;
+ u32 padding;
+} __packed;
+
+/* Server Flags */
+#define VMBUS_CHANNEL_ENUMERATE_DEVICE_INTERFACE 1
+#define VMBUS_CHANNEL_SERVER_SUPPORTS_TRANSFER_PAGES 2
+#define VMBUS_CHANNEL_SERVER_SUPPORTS_GPADLS 4
+#define VMBUS_CHANNEL_NAMED_PIPE_MODE 0x10
+#define VMBUS_CHANNEL_LOOPBACK_OFFER 0x100
+#define VMBUS_CHANNEL_PARENT_OFFER 0x200
+#define VMBUS_CHANNEL_REQUEST_MONITORED_NOTIFICATION 0x400
+
+struct vmpacket_descriptor {
+ u16 type;
+ u16 offset8;
+ u16 len8;
+ u16 flags;
+ u64 trans_id;
+} __packed;
+
+struct vmpacket_header {
+ u32 prev_pkt_start_offset;
+ struct vmpacket_descriptor descriptor;
+} __packed;
+
+struct vmtransfer_page_range {
+ u32 byte_count;
+ u32 byte_offset;
+} __packed;
+
+struct vmtransfer_page_packet_header {
+ struct vmpacket_descriptor d;
+ u16 xfer_pageset_id;
+ bool sender_owns_set;
+ u8 reserved;
+ u32 range_cnt;
+ struct vmtransfer_page_range ranges[1];
+} __packed;
+
+struct vmgpadl_packet_header {
+ struct vmpacket_descriptor d;
+ u32 gpadl;
+ u32 reserved;
+} __packed;
+
+struct vmadd_remove_transfer_page_set {
+ struct vmpacket_descriptor d;
+ u32 gpadl;
+ u16 xfer_pageset_id;
+ u16 reserved;
+} __packed;
+
+/*
+ * This structure defines a range in guest physical space that can be made to
+ * look virtually contiguous.
+ */
+struct gpa_range {
+ u32 byte_count;
+ u32 byte_offset;
+ u64 pfn_array[0];
+};
+
+/*
+ * This is the format for an Establish Gpadl packet, which contains a handle by
+ * which this GPADL will be known and a set of GPA ranges associated with it.
+ * This can be converted to a MDL by the guest OS. If there are multiple GPA
+ * ranges, then the resulting MDL will be "chained," representing multiple VA
+ * ranges.
+ */
+struct vmestablish_gpadl {
+ struct vmpacket_descriptor d;
+ u32 gpadl;
+ u32 range_cnt;
+ struct gpa_range range[1];
+} __packed;
+
+/*
+ * This is the format for a Teardown Gpadl packet, which indicates that the
+ * GPADL handle in the Establish Gpadl packet will never be referenced again.
+ */
+struct vmteardown_gpadl {
+ struct vmpacket_descriptor d;
+ u32 gpadl;
+ u32 reserved; /* for alignment to a 8-byte boundary */
+} __packed;
+
+/*
+ * This is the format for a GPA-Direct packet, which contains a set of GPA
+ * ranges, in addition to commands and/or data.
+ */
+struct vmdata_gpa_direct {
+ struct vmpacket_descriptor d;
+ u32 reserved;
+ u32 range_cnt;
+ struct gpa_range range[1];
+} __packed;
+
+/* This is the format for a Additional Data Packet. */
+struct vmadditional_data {
+ struct vmpacket_descriptor d;
+ u64 total_bytes;
+ u32 offset;
+ u32 byte_cnt;
+ unsigned char data[1];
+} __packed;
+
+union vmpacket_largest_possible_header {
+ struct vmpacket_descriptor simple_hdr;
+ struct vmtransfer_page_packet_header xfer_page_hdr;
+ struct vmgpadl_packet_header gpadl_hdr;
+ struct vmadd_remove_transfer_page_set add_rm_xfer_page_hdr;
+ struct vmestablish_gpadl establish_gpadl_hdr;
+ struct vmteardown_gpadl teardown_gpadl_hdr;
+ struct vmdata_gpa_direct data_gpa_direct_hdr;
+};
+
+#define VMPACKET_DATA_START_ADDRESS(__packet) \
+ (void *)(((unsigned char *)__packet) + \
+ ((struct vmpacket_descriptor)__packet)->offset8 * 8)
+
+#define VMPACKET_DATA_LENGTH(__packet) \
+ ((((struct vmpacket_descriptor)__packet)->len8 - \
+ ((struct vmpacket_descriptor)__packet)->offset8) * 8)
+
+#define VMPACKET_TRANSFER_MODE(__packet) \
+ (((struct IMPACT)__packet)->type)
+
+enum vmbus_packet_type {
+ VM_PKT_INVALID = 0x0,
+ VM_PKT_SYNCH = 0x1,
+ VM_PKT_ADD_XFER_PAGESET = 0x2,
+ VM_PKT_RM_XFER_PAGESET = 0x3,
+ VM_PKT_ESTABLISH_GPADL = 0x4,
+ VM_PKT_TEARDOWN_GPADL = 0x5,
+ VM_PKT_DATA_INBAND = 0x6,
+ VM_PKT_DATA_USING_XFER_PAGES = 0x7,
+ VM_PKT_DATA_USING_GPADL = 0x8,
+ VM_PKT_DATA_USING_GPA_DIRECT = 0x9,
+ VM_PKT_CANCEL_REQUEST = 0xa,
+ VM_PKT_COMP = 0xb,
+ VM_PKT_DATA_USING_ADDITIONAL_PKT = 0xc,
+ VM_PKT_ADDITIONAL_DATA = 0xd
+};
+
+#define VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED 1
+
+
+/* Version 1 messages */
+enum vmbus_channel_message_type {
+ CHANNELMSG_INVALID = 0,
+ CHANNELMSG_OFFERCHANNEL = 1,
+ CHANNELMSG_RESCIND_CHANNELOFFER = 2,
+ CHANNELMSG_REQUESTOFFERS = 3,
+ CHANNELMSG_ALLOFFERS_DELIVERED = 4,
+ CHANNELMSG_OPENCHANNEL = 5,
+ CHANNELMSG_OPENCHANNEL_RESULT = 6,
+ CHANNELMSG_CLOSECHANNEL = 7,
+ CHANNELMSG_GPADL_HEADER = 8,
+ CHANNELMSG_GPADL_BODY = 9,
+ CHANNELMSG_GPADL_CREATED = 10,
+ CHANNELMSG_GPADL_TEARDOWN = 11,
+ CHANNELMSG_GPADL_TORNDOWN = 12,
+ CHANNELMSG_RELID_RELEASED = 13,
+ CHANNELMSG_INITIATE_CONTACT = 14,
+ CHANNELMSG_VERSION_RESPONSE = 15,
+ CHANNELMSG_UNLOAD = 16,
+#ifdef VMBUS_FEATURE_PARENT_OR_PEER_MEMORY_MAPPED_INTO_A_CHILD
+ CHANNELMSG_VIEWRANGE_ADD = 17,
+ CHANNELMSG_VIEWRANGE_REMOVE = 18,
+#endif
+ CHANNELMSG_COUNT
+};
+
+struct vmbus_channel_message_header {
+ enum vmbus_channel_message_type msgtype;
+ u32 padding;
+} __packed;
+
+/* Query VMBus Version parameters */
+struct vmbus_channel_query_vmbus_version {
+ struct vmbus_channel_message_header header;
+ u32 version;
+} __packed;
+
+/* VMBus Version Supported parameters */
+struct vmbus_channel_version_supported {
+ struct vmbus_channel_message_header header;
+ bool version_supported;
+} __packed;
+
+/* Offer Channel parameters */
+struct vmbus_channel_offer_channel {
+ struct vmbus_channel_message_header header;
+ struct vmbus_channel_offer offer;
+ u32 child_relid;
+ u8 monitorid;
+ bool monitor_allocated;
+} __packed;
+
+/* Rescind Offer parameters */
+struct vmbus_channel_rescind_offer {
+ struct vmbus_channel_message_header header;
+ u32 child_relid;
+} __packed;
+
+/*
+ * Request Offer -- no parameters, SynIC message contains the partition ID
+ * Set Snoop -- no parameters, SynIC message contains the partition ID
+ * Clear Snoop -- no parameters, SynIC message contains the partition ID
+ * All Offers Delivered -- no parameters, SynIC message contains the partition
+ * ID
+ * Flush Client -- no parameters, SynIC message contains the partition ID
+ */
+
+/* Open Channel parameters */
+struct vmbus_channel_open_channel {
+ struct vmbus_channel_message_header header;
+
+ /* Identifies the specific VMBus channel that is being opened. */
+ u32 child_relid;
+
+ /* ID making a particular open request at a channel offer unique. */
+ u32 openid;
+
+ /* GPADL for the channel's ring buffer. */
+ u32 ringbuffer_gpadlhandle;
+
+ /* GPADL for the channel's server context save area. */
+ u32 server_contextarea_gpadlhandle;
+
+ /*
+ * The upstream ring buffer begins at offset zero in the memory
+ * described by RingBufferGpadlHandle. The downstream ring buffer
+ * follows it at this offset (in pages).
+ */
+ u32 downstream_ringbuffer_pageoffset;
+
+ /* User-specific data to be passed along to the server endpoint. */
+ unsigned char userdata[MAX_USER_DEFINED_BYTES];
+} __packed;
+
+/* Open Channel Result parameters */
+struct vmbus_channel_open_result {
+ struct vmbus_channel_message_header header;
+ u32 child_relid;
+ u32 openid;
+ u32 status;
+} __packed;
+
+/* Close channel parameters; */
+struct vmbus_channel_close_channel {
+ struct vmbus_channel_message_header header;
+ u32 child_relid;
+} __packed;
+
+/* Channel Message GPADL */
+#define GPADL_TYPE_RING_BUFFER 1
+#define GPADL_TYPE_SERVER_SAVE_AREA 2
+#define GPADL_TYPE_TRANSACTION 8
+
+/*
+ * The number of PFNs in a GPADL message is defined by the number of
+ * pages that would be spanned by ByteCount and ByteOffset. If the
+ * implied number of PFNs won't fit in this packet, there will be a
+ * follow-up packet that contains more.
+ */
+struct vmbus_channel_gpadl_header {
+ struct vmbus_channel_message_header header;
+ u32 child_relid;
+ u32 gpadl;
+ u16 range_buflen;
+ u16 rangecount;
+ struct gpa_range range[0];
+} __packed;
+
+/* This is the followup packet that contains more PFNs. */
+struct vmbus_channel_gpadl_body {
+ struct vmbus_channel_message_header header;
+ u32 msgnumber;
+ u32 gpadl;
+ u64 pfn[0];
+} __packed;
+
+struct vmbus_channel_gpadl_created {
+ struct vmbus_channel_message_header header;
+ u32 child_relid;
+ u32 gpadl;
+ u32 creation_status;
+} __packed;
+
+struct vmbus_channel_gpadl_teardown {
+ struct vmbus_channel_message_header header;
+ u32 child_relid;
+ u32 gpadl;
+} __packed;
+
+struct vmbus_channel_gpadl_torndown {
+ struct vmbus_channel_message_header header;
+ u32 gpadl;
+} __packed;
+
+#ifdef VMBUS_FEATURE_PARENT_OR_PEER_MEMORY_MAPPED_INTO_A_CHILD
+struct vmbus_channel_view_range_add {
+ struct vmbus_channel_message_header header;
+ PHYSICAL_ADDRESS viewrange_base;
+ u64 viewrange_length;
+ u32 child_relid;
+} __packed;
+
+struct vmbus_channel_view_range_remove {
+ struct vmbus_channel_message_header header;
+ PHYSICAL_ADDRESS viewrange_base;
+ u32 child_relid;
+} __packed;
+#endif
+
+struct vmbus_channel_relid_released {
+ struct vmbus_channel_message_header header;
+ u32 child_relid;
+} __packed;
+
+struct vmbus_channel_initiate_contact {
+ struct vmbus_channel_message_header header;
+ u32 vmbus_version_requested;
+ u32 padding2;
+ u64 interrupt_page;
+ u64 monitor_page1;
+ u64 monitor_page2;
+} __packed;
+
+struct vmbus_channel_version_response {
+ struct vmbus_channel_message_header header;
+ bool version_supported;
+} __packed;
+
+enum vmbus_channel_state {
+ CHANNEL_OFFER_STATE,
+ CHANNEL_OPENING_STATE,
+ CHANNEL_OPEN_STATE,
+};
+
+struct vmbus_channel {
+ struct list_head listentry;
+
+ struct hv_device *device_obj;
+
+ struct timer_list poll_timer; /* SA-111 workaround */
+ struct work_struct work;
+
+ enum vmbus_channel_state state;
+ /*
+ * For util channels, stash the
+ * the service index for easy access.
+ */
+ s8 util_index;
+
+ struct vmbus_channel_offer_channel offermsg;
+ /*
+ * These are based on the OfferMsg.MonitorId.
+ * Save it here for easy access.
+ */
+ u8 monitor_grp;
+ u8 monitor_bit;
+
+ u32 ringbuffer_gpadlhandle;
+
+ /* Allocated memory for ring buffer */
+ void *ringbuffer_pages;
+ u32 ringbuffer_pagecount;
+ struct hv_ring_buffer_info outbound; /* send to parent */
+ struct hv_ring_buffer_info inbound; /* receive from parent */
+ spinlock_t inbound_lock;
+ struct workqueue_struct *controlwq;
+
+ /* Channel callback are invoked in this workqueue context */
+ /* HANDLE dataWorkQueue; */
+
+ void (*onchannel_callback)(void *context);
+ void *channel_callback_context;
+};
+
+struct vmbus_channel_debug_info {
+ u32 relid;
+ enum vmbus_channel_state state;
+ struct hv_guid interfacetype;
+ struct hv_guid interface_instance;
+ u32 monitorid;
+ u32 servermonitor_pending;
+ u32 servermonitor_latency;
+ u32 servermonitor_connectionid;
+ u32 clientmonitor_pending;
+ u32 clientmonitor_latency;
+ u32 clientmonitor_connectionid;
+
+ struct hv_ring_buffer_debug_info inbound;
+ struct hv_ring_buffer_debug_info outbound;
+};
+
+/*
+ * Represents each channel msg on the vmbus connection This is a
+ * variable-size data structure depending on the msg type itself
+ */
+struct vmbus_channel_msginfo {
+ /* Bookkeeping stuff */
+ struct list_head msglistentry;
+
+ /* So far, this is only used to handle gpadl body message */
+ struct list_head submsglist;
+
+ /* Synchronize the request/response if needed */
+ struct completion waitevent;
+ union {
+ struct vmbus_channel_version_supported version_supported;
+ struct vmbus_channel_open_result open_result;
+ struct vmbus_channel_gpadl_torndown gpadl_torndown;
+ struct vmbus_channel_gpadl_created gpadl_created;
+ struct vmbus_channel_version_response version_response;
+ } response;
+
+ u32 msgsize;
+ /*
+ * The channel message that goes out on the "wire".
+ * It will contain at minimum the VMBUS_CHANNEL_MESSAGE_HEADER header
+ */
+ unsigned char msg[0];
+};
+
+
+void free_channel(struct vmbus_channel *channel);
+
+void vmbus_onmessage(void *context);
+
+int vmbus_request_offers(void);
+
+/* The format must be the same as struct vmdata_gpa_direct */
+struct vmbus_channel_packet_page_buffer {
+ u16 type;
+ u16 dataoffset8;
+ u16 length8;
+ u16 flags;
+ u64 transactionid;
+ u32 reserved;
+ u32 rangecount;
+ struct hv_page_buffer range[MAX_PAGE_BUFFER_COUNT];
+} __packed;
+
+/* The format must be the same as struct vmdata_gpa_direct */
+struct vmbus_channel_packet_multipage_buffer {
+ u16 type;
+ u16 dataoffset8;
+ u16 length8;
+ u16 flags;
+ u64 transactionid;
+ u32 reserved;
+ u32 rangecount; /* Always 1 in this case */
+ struct hv_multipage_buffer range;
+} __packed;
+
+
+extern int vmbus_open(struct vmbus_channel *channel,
+ u32 send_ringbuffersize,
+ u32 recv_ringbuffersize,
+ void *userdata,
+ u32 userdatalen,
+ void(*onchannel_callback)(void *context),
+ void *context);
+
+extern void vmbus_close(struct vmbus_channel *channel);
+
+extern int vmbus_sendpacket(struct vmbus_channel *channel,
+ const void *buffer,
+ u32 bufferLen,
+ u64 requestid,
+ enum vmbus_packet_type type,
+ u32 flags);
+
+extern int vmbus_sendpacket_pagebuffer(struct vmbus_channel *channel,
+ struct hv_page_buffer pagebuffers[],
+ u32 pagecount,
+ void *buffer,
+ u32 bufferlen,
+ u64 requestid);
+
+extern int vmbus_sendpacket_multipagebuffer(struct vmbus_channel *channel,
+ struct hv_multipage_buffer *mpb,
+ void *buffer,
+ u32 bufferlen,
+ u64 requestid);
+
+extern int vmbus_establish_gpadl(struct vmbus_channel *channel,
+ void *kbuffer,
+ u32 size,
+ u32 *gpadl_handle);
+
+extern int vmbus_teardown_gpadl(struct vmbus_channel *channel,
+ u32 gpadl_handle);
+
+extern int vmbus_recvpacket(struct vmbus_channel *channel,
+ void *buffer,
+ u32 bufferlen,
+ u32 *buffer_actual_len,
+ u64 *requestid);
+
+extern int vmbus_recvpacket_raw(struct vmbus_channel *channel,
+ void *buffer,
+ u32 bufferlen,
+ u32 *buffer_actual_len,
+ u64 *requestid);
+
+extern void vmbus_onchannel_event(struct vmbus_channel *channel);
+
+extern void vmbus_get_debug_info(struct vmbus_channel *channel,
+ struct vmbus_channel_debug_info *debug);
+
+extern void vmbus_ontimer(unsigned long data);
+
+
+#define LOWORD(dw) ((unsigned short)(dw))
+#define HIWORD(dw) ((unsigned short)(((unsigned int) (dw) >> 16) & 0xFFFF))
+
+
+#define VMBUS 0x0001
+#define STORVSC 0x0002
+#define NETVSC 0x0004
+#define INPUTVSC 0x0008
+#define BLKVSC 0x0010
+#define VMBUS_DRV 0x0100
+#define STORVSC_DRV 0x0200
+#define NETVSC_DRV 0x0400
+#define INPUTVSC_DRV 0x0800
+#define BLKVSC_DRV 0x1000
+
+#define ALL_MODULES (VMBUS |\
+ STORVSC |\
+ NETVSC |\
+ INPUTVSC |\
+ BLKVSC |\
+ VMBUS_DRV |\
+ STORVSC_DRV |\
+ NETVSC_DRV |\
+ INPUTVSC_DRV|\
+ BLKVSC_DRV)
+
+/* Logging Level */
+#define ERROR_LVL 3
+#define WARNING_LVL 4
+#define INFO_LVL 6
+#define DEBUG_LVL 7
+#define DEBUG_LVL_ENTEREXIT 8
+#define DEBUG_RING_LVL 9
+
+extern unsigned int vmbus_loglevel;
+
+#define DPRINT(mod, lvl, fmt, args...) do {\
+ if ((mod & (HIWORD(vmbus_loglevel))) && \
+ (lvl <= LOWORD(vmbus_loglevel))) \
+ printk(KERN_DEBUG #mod": %s() " fmt "\n", __func__, ## args);\
+ } while (0)
+
+#define DPRINT_DBG(mod, fmt, args...) do {\
+ if ((mod & (HIWORD(vmbus_loglevel))) && \
+ (DEBUG_LVL <= LOWORD(vmbus_loglevel))) \
+ printk(KERN_DEBUG #mod": %s() " fmt "\n", __func__, ## args);\
+ } while (0)
+
+#define DPRINT_INFO(mod, fmt, args...) do {\
+ if ((mod & (HIWORD(vmbus_loglevel))) && \
+ (INFO_LVL <= LOWORD(vmbus_loglevel))) \
+ printk(KERN_INFO #mod": " fmt "\n", ## args);\
+ } while (0)
+
+#define DPRINT_WARN(mod, fmt, args...) do {\
+ if ((mod & (HIWORD(vmbus_loglevel))) && \
+ (WARNING_LVL <= LOWORD(vmbus_loglevel))) \
+ printk(KERN_WARNING #mod": WARNING! " fmt "\n", ## args);\
+ } while (0)
+
+#define DPRINT_ERR(mod, fmt, args...) do {\
+ if ((mod & (HIWORD(vmbus_loglevel))) && \
+ (ERROR_LVL <= LOWORD(vmbus_loglevel))) \
+ printk(KERN_ERR #mod": %s() ERROR!! " fmt "\n", \
+ __func__, ## args);\
+ } while (0)
+
+
+
+struct hv_driver;
+struct hv_device;
+
+struct hv_dev_port_info {
+ u32 int_mask;
+ u32 read_idx;
+ u32 write_idx;
+ u32 bytes_avail_toread;
+ u32 bytes_avail_towrite;
+};
+
+struct hv_device_info {
+ u32 chn_id;
+ u32 chn_state;
+ struct hv_guid chn_type;
+ struct hv_guid chn_instance;
+
+ u32 monitor_id;
+ u32 server_monitor_pending;
+ u32 server_monitor_latency;
+ u32 server_monitor_conn_id;
+ u32 client_monitor_pending;
+ u32 client_monitor_latency;
+ u32 client_monitor_conn_id;
+
+ struct hv_dev_port_info inbound;
+ struct hv_dev_port_info outbound;
+};
+
+/* Base driver object */
+struct hv_driver {
+ const char *name;
+
+ /* the device type supported by this driver */
+ struct hv_guid dev_type;
+
+ struct device_driver driver;
+
+ int (*probe)(struct hv_device *);
+ int (*remove)(struct hv_device *);
+ void (*shutdown)(struct hv_device *);
+
+};
+
+/* Base device object */
+struct hv_device {
+ /* the device type id of this device */
+ struct hv_guid dev_type;
+
+ /* the device instance id of this device */
+ struct hv_guid dev_instance;
+
+ struct device device;
+
+ struct vmbus_channel *channel;
+
+ /* Device extension; */
+ void *ext;
+};
+
+
+static inline struct hv_device *device_to_hv_device(struct device *d)
+{
+ return container_of(d, struct hv_device, device);
+}
+
+static inline struct hv_driver *drv_to_hv_drv(struct device_driver *d)
+{
+ return container_of(d, struct hv_driver, driver);
+}
+
+
+/* Vmbus interface */
+int vmbus_child_driver_register(struct device_driver *drv);
+void vmbus_child_driver_unregister(struct device_driver *drv);
+
+/*
+ * Common header for Hyper-V ICs
+ */
+
+#define ICMSGTYPE_NEGOTIATE 0
+#define ICMSGTYPE_HEARTBEAT 1
+#define ICMSGTYPE_KVPEXCHANGE 2
+#define ICMSGTYPE_SHUTDOWN 3
+#define ICMSGTYPE_TIMESYNC 4
+#define ICMSGTYPE_VSS 5
+
+#define ICMSGHDRFLAG_TRANSACTION 1
+#define ICMSGHDRFLAG_REQUEST 2
+#define ICMSGHDRFLAG_RESPONSE 4
+
+#define HV_S_OK 0x00000000
+#define HV_E_FAIL 0x80004005
+#define HV_ERROR_NOT_SUPPORTED 0x80070032
+#define HV_ERROR_MACHINE_LOCKED 0x800704F7
+
+struct vmbuspipe_hdr {
+ u32 flags;
+ u32 msgsize;
+} __packed;
+
+struct ic_version {
+ u16 major;
+ u16 minor;
+} __packed;
+
+struct icmsg_hdr {
+ struct ic_version icverframe;
+ u16 icmsgtype;
+ struct ic_version icvermsg;
+ u16 icmsgsize;
+ u32 status;
+ u8 ictransaction_id;
+ u8 icflags;
+ u8 reserved[2];
+} __packed;
+
+struct icmsg_negotiate {
+ u16 icframe_vercnt;
+ u16 icmsg_vercnt;
+ u32 reserved;
+ struct ic_version icversion_data[1]; /* any size array */
+} __packed;
+
+struct shutdown_msg_data {
+ u32 reason_code;
+ u32 timeout_seconds;
+ u32 flags;
+ u8 display_message[2048];
+} __packed;
+
+struct heartbeat_msg_data {
+ u64 seq_num;
+ u32 reserved[8];
+} __packed;
+
+/* Time Sync IC defs */
+#define ICTIMESYNCFLAG_PROBE 0
+#define ICTIMESYNCFLAG_SYNC 1
+#define ICTIMESYNCFLAG_SAMPLE 2
+
+#ifdef __x86_64__
+#define WLTIMEDELTA 116444736000000000L /* in 100ns unit */
+#else
+#define WLTIMEDELTA 116444736000000000LL
+#endif
+
+struct ictimesync_data {
+ u64 parenttime;
+ u64 childtime;
+ u64 roundtriptime;
+ u8 flags;
+} __packed;
+
+/* Index for each IC struct in array hv_cb_utils[] */
+#define HV_SHUTDOWN_MSG 0
+#define HV_TIMESYNC_MSG 1
+#define HV_HEARTBEAT_MSG 2
+#define HV_KVP_MSG 3
+
+struct hyperv_service_callback {
+ u8 msg_type;
+ char *log_msg;
+ unsigned char data[16];
+ struct vmbus_channel *channel;
+ void (*callback) (void *context);
+};
+
+extern void prep_negotiate_resp(struct icmsg_hdr *,
+ struct icmsg_negotiate *, u8 *);
+extern void chn_cb_negotiate(void *);
+extern struct hyperv_service_callback hv_cb_utils[];
+
+#endif /* _HYPERV_H */
diff --git a/drivers/staging/hv/hyperv_net.h b/drivers/staging/hv/hyperv_net.h
new file mode 100644
index 0000000..315097d
--- /dev/null
+++ b/drivers/staging/hv/hyperv_net.h
@@ -0,0 +1,1067 @@
+/*
+ *
+ * Copyright (c) 2011, Microsoft Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
+ * Place - Suite 330, Boston, MA 02111-1307 USA.
+ *
+ * Authors:
+ * Haiyang Zhang <haiyangz@microsoft.com>
+ * Hank Janssen <hjanssen@microsoft.com>
+ * K. Y. Srinivasan <kys@microsoft.com>
+ *
+ */
+
+#ifndef _HYPERV_NET_H
+#define _HYPERV_NET_H
+
+#include <linux/list.h>
+#include "hyperv.h"
+
+/* Fwd declaration */
+struct hv_netvsc_packet;
+
+/* Represent the xfer page packet which contains 1 or more netvsc packet */
+struct xferpage_packet {
+ struct list_head list_ent;
+
+ /* # of netvsc packets this xfer packet contains */
+ u32 count;
+};
+
+/* The number of pages which are enough to cover jumbo frame buffer. */
+#define NETVSC_PACKET_MAXPAGE 4
+
+/*
+ * Represent netvsc packet which contains 1 RNDIS and 1 ethernet frame
+ * within the RNDIS
+ */
+struct hv_netvsc_packet {
+ /* Bookkeeping stuff */
+ struct list_head list_ent;
+
+ struct hv_device *device;
+ bool is_data_pkt;
+
+ /*
+ * Valid only for receives when we break a xfer page packet
+ * into multiple netvsc packets
+ */
+ struct xferpage_packet *xfer_page_pkt;
+
+ union {
+ struct {
+ u64 recv_completion_tid;
+ void *recv_completion_ctx;
+ void (*recv_completion)(void *context);
+ } recv;
+ struct {
+ u64 send_completion_tid;
+ void *send_completion_ctx;
+ void (*send_completion)(void *context);
+ } send;
+ } completion;
+
+ /* This points to the memory after page_buf */
+ void *extension;
+
+ u32 total_data_buflen;
+ /* Points to the send/receive buffer where the ethernet frame is */
+ u32 page_buf_cnt;
+ struct hv_page_buffer page_buf[NETVSC_PACKET_MAXPAGE];
+};
+
+struct netvsc_device_info {
+ unsigned char mac_adr[6];
+ bool link_state; /* 0 - link up, 1 - link down */
+ int ring_size;
+};
+
+/* Interface */
+int netvsc_device_add(struct hv_device *device, void *additional_info);
+int netvsc_device_remove(struct hv_device *device);
+int netvsc_send(struct hv_device *device,
+ struct hv_netvsc_packet *packet);
+void netvsc_linkstatus_callback(struct hv_device *device_obj,
+ unsigned int status);
+int netvsc_recv_callback(struct hv_device *device_obj,
+ struct hv_netvsc_packet *packet);
+int netvsc_initialize(struct hv_driver *drv);
+int rndis_filter_open(struct hv_device *dev);
+int rndis_filter_close(struct hv_device *dev);
+int rndis_filte_device_add(struct hv_device *dev,
+ void *additional_info);
+int rndis_filter_device_remove(struct hv_device *dev);
+int rndis_filter_receive(struct hv_device *dev,
+ struct hv_netvsc_packet *pkt);
+
+
+
+int rndis_filter_send(struct hv_device *dev,
+ struct hv_netvsc_packet *pkt);
+
+#define NVSP_INVALID_PROTOCOL_VERSION ((u32)0xFFFFFFFF)
+
+#define NVSP_PROTOCOL_VERSION_1 2
+#define NVSP_MIN_PROTOCOL_VERSION NVSP_PROTOCOL_VERSION_1
+#define NVSP_MAX_PROTOCOL_VERSION NVSP_PROTOCOL_VERSION_1
+
+enum {
+ NVSP_MSG_TYPE_NONE = 0,
+
+ /* Init Messages */
+ NVSP_MSG_TYPE_INIT = 1,
+ NVSP_MSG_TYPE_INIT_COMPLETE = 2,
+
+ NVSP_VERSION_MSG_START = 100,
+
+ /* Version 1 Messages */
+ NVSP_MSG1_TYPE_SEND_NDIS_VER = NVSP_VERSION_MSG_START,
+
+ NVSP_MSG1_TYPE_SEND_RECV_BUF,
+ NVSP_MSG1_TYPE_SEND_RECV_BUF_COMPLETE,
+ NVSP_MSG1_TYPE_REVOKE_RECV_BUF,
+
+ NVSP_MSG1_TYPE_SEND_SEND_BUF,
+ NVSP_MSG1_TYPE_SEND_SEND_BUF_COMPLETE,
+ NVSP_MSG1_TYPE_REVOKE_SEND_BUF,
+
+ NVSP_MSG1_TYPE_SEND_RNDIS_PKT,
+ NVSP_MSG1_TYPE_SEND_RNDIS_PKT_COMPLETE,
+
+ /*
+ * This should be set to the number of messages for the version with
+ * the maximum number of messages.
+ */
+ NVSP_NUM_MSG_PER_VERSION = 9,
+};
+
+enum {
+ NVSP_STAT_NONE = 0,
+ NVSP_STAT_SUCCESS,
+ NVSP_STAT_FAIL,
+ NVSP_STAT_PROTOCOL_TOO_NEW,
+ NVSP_STAT_PROTOCOL_TOO_OLD,
+ NVSP_STAT_INVALID_RNDIS_PKT,
+ NVSP_STAT_BUSY,
+ NVSP_STAT_MAX,
+};
+
+struct nvsp_message_header {
+ u32 msg_type;
+};
+
+/* Init Messages */
+
+/*
+ * This message is used by the VSC to initialize the channel after the channels
+ * has been opened. This message should never include anything other then
+ * versioning (i.e. this message will be the same for ever).
+ */
+struct nvsp_message_init {
+ u32 min_protocol_ver;
+ u32 max_protocol_ver;
+} __packed;
+
+/*
+ * This message is used by the VSP to complete the initialization of the
+ * channel. This message should never include anything other then versioning
+ * (i.e. this message will be the same for ever).
+ */
+struct nvsp_message_init_complete {
+ u32 negotiated_protocol_ver;
+ u32 max_mdl_chain_len;
+ u32 status;
+} __packed;
+
+union nvsp_message_init_uber {
+ struct nvsp_message_init init;
+ struct nvsp_message_init_complete init_complete;
+} __packed;
+
+/* Version 1 Messages */
+
+/*
+ * This message is used by the VSC to send the NDIS version to the VSP. The VSP
+ * can use this information when handling OIDs sent by the VSC.
+ */
+struct nvsp_1_message_send_ndis_version {
+ u32 ndis_major_ver;
+ u32 ndis_minor_ver;
+} __packed;
+
+/*
+ * This message is used by the VSC to send a receive buffer to the VSP. The VSP
+ * can then use the receive buffer to send data to the VSC.
+ */
+struct nvsp_1_message_send_receive_buffer {
+ u32 gpadl_handle;
+ u16 id;
+} __packed;
+
+struct nvsp_1_receive_buffer_section {
+ u32 offset;
+ u32 sub_alloc_size;
+ u32 num_sub_allocs;
+ u32 end_offset;
+} __packed;
+
+/*
+ * This message is used by the VSP to acknowledge a receive buffer send by the
+ * VSC. This message must be sent by the VSP before the VSP uses the receive
+ * buffer.
+ */
+struct nvsp_1_message_send_receive_buffer_complete {
+ u32 status;
+ u32 num_sections;
+
+ /*
+ * The receive buffer is split into two parts, a large suballocation
+ * section and a small suballocation section. These sections are then
+ * suballocated by a certain size.
+ */
+
+ /*
+ * For example, the following break up of the receive buffer has 6
+ * large suballocations and 10 small suballocations.
+ */
+
+ /*
+ * | Large Section | | Small Section |
+ * ------------------------------------------------------------
+ * | | | | | | | | | | | | | | | | | |
+ * | |
+ * LargeOffset SmallOffset
+ */
+
+ struct nvsp_1_receive_buffer_section sections[1];
+} __packed;
+
+/*
+ * This message is sent by the VSC to revoke the receive buffer. After the VSP
+ * completes this transaction, the vsp should never use the receive buffer
+ * again.
+ */
+struct nvsp_1_message_revoke_receive_buffer {
+ u16 id;
+};
+
+/*
+ * This message is used by the VSC to send a send buffer to the VSP. The VSC
+ * can then use the send buffer to send data to the VSP.
+ */
+struct nvsp_1_message_send_send_buffer {
+ u32 gpadl_handle;
+ u16 id;
+} __packed;
+
+/*
+ * This message is used by the VSP to acknowledge a send buffer sent by the
+ * VSC. This message must be sent by the VSP before the VSP uses the sent
+ * buffer.
+ */
+struct nvsp_1_message_send_send_buffer_complete {
+ u32 status;
+
+ /*
+ * The VSC gets to choose the size of the send buffer and the VSP gets
+ * to choose the sections size of the buffer. This was done to enable
+ * dynamic reconfigurations when the cost of GPA-direct buffers
+ * decreases.
+ */
+ u32 section_size;
+} __packed;
+
+/*
+ * This message is sent by the VSC to revoke the send buffer. After the VSP
+ * completes this transaction, the vsp should never use the send buffer again.
+ */
+struct nvsp_1_message_revoke_send_buffer {
+ u16 id;
+};
+
+/*
+ * This message is used by both the VSP and the VSC to send a RNDIS message to
+ * the opposite channel endpoint.
+ */
+struct nvsp_1_message_send_rndis_packet {
+ /*
+ * This field is specified by RNIDS. They assume there's two different
+ * channels of communication. However, the Network VSP only has one.
+ * Therefore, the channel travels with the RNDIS packet.
+ */
+ u32 channel_type;
+
+ /*
+ * This field is used to send part or all of the data through a send
+ * buffer. This values specifies an index into the send buffer. If the
+ * index is 0xFFFFFFFF, then the send buffer is not being used and all
+ * of the data was sent through other VMBus mechanisms.
+ */
+ u32 send_buf_section_index;
+ u32 send_buf_section_size;
+} __packed;
+
+/*
+ * This message is used by both the VSP and the VSC to complete a RNDIS message
+ * to the opposite channel endpoint. At this point, the initiator of this
+ * message cannot use any resources associated with the original RNDIS packet.
+ */
+struct nvsp_1_message_send_rndis_packet_complete {
+ u32 status;
+};
+
+union nvsp_1_message_uber {
+ struct nvsp_1_message_send_ndis_version send_ndis_ver;
+
+ struct nvsp_1_message_send_receive_buffer send_recv_buf;
+ struct nvsp_1_message_send_receive_buffer_complete
+ send_recv_buf_complete;
+ struct nvsp_1_message_revoke_receive_buffer revoke_recv_buf;
+
+ struct nvsp_1_message_send_send_buffer send_send_buf;
+ struct nvsp_1_message_send_send_buffer_complete send_send_buf_complete;
+ struct nvsp_1_message_revoke_send_buffer revoke_send_buf;
+
+ struct nvsp_1_message_send_rndis_packet send_rndis_pkt;
+ struct nvsp_1_message_send_rndis_packet_complete
+ send_rndis_pkt_complete;
+} __packed;
+
+union nvsp_all_messages {
+ union nvsp_message_init_uber init_msg;
+ union nvsp_1_message_uber v1_msg;
+} __packed;
+
+/* ALL Messages */
+struct nvsp_message {
+ struct nvsp_message_header hdr;
+ union nvsp_all_messages msg;
+} __packed;
+
+
+
+
+/* #define NVSC_MIN_PROTOCOL_VERSION 1 */
+/* #define NVSC_MAX_PROTOCOL_VERSION 1 */
+
+#define NETVSC_SEND_BUFFER_SIZE (64*1024) /* 64K */
+#define NETVSC_SEND_BUFFER_ID 0xface
+
+
+#define NETVSC_RECEIVE_BUFFER_SIZE (1024*1024) /* 1MB */
+
+#define NETVSC_RECEIVE_BUFFER_ID 0xcafe
+
+#define NETVSC_RECEIVE_SG_COUNT 1
+
+/* Preallocated receive packets */
+#define NETVSC_RECEIVE_PACKETLIST_COUNT 256
+
+#define NETVSC_PACKET_SIZE 2048
+
+/* Per netvsc channel-specific */
+struct netvsc_device {
+ struct hv_device *dev;
+
+ atomic_t refcnt;
+ atomic_t num_outstanding_sends;
+ /*
+ * List of free preallocated hv_netvsc_packet to represent receive
+ * packet
+ */
+ struct list_head recv_pkt_list;
+ spinlock_t recv_pkt_list_lock;
+
+ /* Send buffer allocated by us but manages by NetVSP */
+ void *send_buf;
+ u32 send_buf_size;
+ u32 send_buf_gpadl_handle;
+ u32 send_section_size;
+
+ /* Receive buffer allocated by us but manages by NetVSP */
+ void *recv_buf;
+ u32 recv_buf_size;
+ u32 recv_buf_gpadl_handle;
+ u32 recv_section_cnt;
+ struct nvsp_1_receive_buffer_section *recv_section;
+
+ /* Used for NetVSP initialization protocol */
+ struct completion channel_init_wait;
+ struct nvsp_message channel_init_pkt;
+
+ struct nvsp_message revoke_packet;
+ /* unsigned char HwMacAddr[HW_MACADDR_LEN]; */
+
+ /* Holds rndis device info */
+ void *extension;
+};
+
+
+/* Status codes */
+
+
+#ifndef STATUS_SUCCESS
+#define STATUS_SUCCESS (0x00000000L)
+#endif
+
+#ifndef STATUS_UNSUCCESSFUL
+#define STATUS_UNSUCCESSFUL (0xC0000001L)
+#endif
+
+#ifndef STATUS_PENDING
+#define STATUS_PENDING (0x00000103L)
+#endif
+
+#ifndef STATUS_INSUFFICIENT_RESOURCES
+#define STATUS_INSUFFICIENT_RESOURCES (0xC000009AL)
+#endif
+
+#ifndef STATUS_BUFFER_OVERFLOW
+#define STATUS_BUFFER_OVERFLOW (0x80000005L)
+#endif
+
+#ifndef STATUS_NOT_SUPPORTED
+#define STATUS_NOT_SUPPORTED (0xC00000BBL)
+#endif
+
+#define RNDIS_STATUS_SUCCESS (STATUS_SUCCESS)
+#define RNDIS_STATUS_PENDING (STATUS_PENDING)
+#define RNDIS_STATUS_NOT_RECOGNIZED (0x00010001L)
+#define RNDIS_STATUS_NOT_COPIED (0x00010002L)
+#define RNDIS_STATUS_NOT_ACCEPTED (0x00010003L)
+#define RNDIS_STATUS_CALL_ACTIVE (0x00010007L)
+
+#define RNDIS_STATUS_ONLINE (0x40010003L)
+#define RNDIS_STATUS_RESET_START (0x40010004L)
+#define RNDIS_STATUS_RESET_END (0x40010005L)
+#define RNDIS_STATUS_RING_STATUS (0x40010006L)
+#define RNDIS_STATUS_CLOSED (0x40010007L)
+#define RNDIS_STATUS_WAN_LINE_UP (0x40010008L)
+#define RNDIS_STATUS_WAN_LINE_DOWN (0x40010009L)
+#define RNDIS_STATUS_WAN_FRAGMENT (0x4001000AL)
+#define RNDIS_STATUS_MEDIA_CONNECT (0x4001000BL)
+#define RNDIS_STATUS_MEDIA_DISCONNECT (0x4001000CL)
+#define RNDIS_STATUS_HARDWARE_LINE_UP (0x4001000DL)
+#define RNDIS_STATUS_HARDWARE_LINE_DOWN (0x4001000EL)
+#define RNDIS_STATUS_INTERFACE_UP (0x4001000FL)
+#define RNDIS_STATUS_INTERFACE_DOWN (0x40010010L)
+#define RNDIS_STATUS_MEDIA_BUSY (0x40010011L)
+#define RNDIS_STATUS_MEDIA_SPECIFIC_INDICATION (0x40010012L)
+#define RNDIS_STATUS_WW_INDICATION RDIA_SPECIFIC_INDICATION
+#define RNDIS_STATUS_LINK_SPEED_CHANGE (0x40010013L)
+
+#define RNDIS_STATUS_NOT_RESETTABLE (0x80010001L)
+#define RNDIS_STATUS_SOFT_ERRORS (0x80010003L)
+#define RNDIS_STATUS_HARD_ERRORS (0x80010004L)
+#define RNDIS_STATUS_BUFFER_OVERFLOW (STATUS_BUFFER_OVERFLOW)
+
+#define RNDIS_STATUS_FAILURE (STATUS_UNSUCCESSFUL)
+#define RNDIS_STATUS_RESOURCES (STATUS_INSUFFICIENT_RESOURCES)
+#define RNDIS_STATUS_CLOSING (0xC0010002L)
+#define RNDIS_STATUS_BAD_VERSION (0xC0010004L)
+#define RNDIS_STATUS_BAD_CHARACTERISTICS (0xC0010005L)
+#define RNDIS_STATUS_ADAPTER_NOT_FOUND (0xC0010006L)
+#define RNDIS_STATUS_OPEN_FAILED (0xC0010007L)
+#define RNDIS_STATUS_DEVICE_FAILED (0xC0010008L)
+#define RNDIS_STATUS_MULTICAST_FULL (0xC0010009L)
+#define RNDIS_STATUS_MULTICAST_EXISTS (0xC001000AL)
+#define RNDIS_STATUS_MULTICAST_NOT_FOUND (0xC001000BL)
+#define RNDIS_STATUS_REQUEST_ABORTED (0xC001000CL)
+#define RNDIS_STATUS_RESET_IN_PROGRESS (0xC001000DL)
+#define RNDIS_STATUS_CLOSING_INDICATING (0xC001000EL)
+#define RNDIS_STATUS_NOT_SUPPORTED (STATUS_NOT_SUPPORTED)
+#define RNDIS_STATUS_INVALID_PACKET (0xC001000FL)
+#define RNDIS_STATUS_OPEN_LIST_FULL (0xC0010010L)
+#define RNDIS_STATUS_ADAPTER_NOT_READY (0xC0010011L)
+#define RNDIS_STATUS_ADAPTER_NOT_OPEN (0xC0010012L)
+#define RNDIS_STATUS_NOT_INDICATING (0xC0010013L)
+#define RNDIS_STATUS_INVALID_LENGTH (0xC0010014L)
+#define RNDIS_STATUS_INVALID_DATA (0xC0010015L)
+#define RNDIS_STATUS_BUFFER_TOO_SHORT (0xC0010016L)
+#define RNDIS_STATUS_INVALID_OID (0xC0010017L)
+#define RNDIS_STATUS_ADAPTER_REMOVED (0xC0010018L)
+#define RNDIS_STATUS_UNSUPPORTED_MEDIA (0xC0010019L)
+#define RNDIS_STATUS_GROUP_ADDRESS_IN_USE (0xC001001AL)
+#define RNDIS_STATUS_FILE_NOT_FOUND (0xC001001BL)
+#define RNDIS_STATUS_ERROR_READING_FILE (0xC001001CL)
+#define RNDIS_STATUS_ALREADY_MAPPED (0xC001001DL)
+#define RNDIS_STATUS_RESOURCE_CONFLICT (0xC001001EL)
+#define RNDIS_STATUS_NO_CABLE (0xC001001FL)
+
+#define RNDIS_STATUS_INVALID_SAP (0xC0010020L)
+#define RNDIS_STATUS_SAP_IN_USE (0xC0010021L)
+#define RNDIS_STATUS_INVALID_ADDRESS (0xC0010022L)
+#define RNDIS_STATUS_VC_NOT_ACTIVATED (0xC0010023L)
+#define RNDIS_STATUS_DEST_OUT_OF_ORDER (0xC0010024L)
+#define RNDIS_STATUS_VC_NOT_AVAILABLE (0xC0010025L)
+#define RNDIS_STATUS_CELLRATE_NOT_AVAILABLE (0xC0010026L)
+#define RNDIS_STATUS_INCOMPATABLE_QOS (0xC0010027L)
+#define RNDIS_STATUS_AAL_PARAMS_UNSUPPORTED (0xC0010028L)
+#define RNDIS_STATUS_NO_ROUTE_TO_DESTINATION (0xC0010029L)
+
+#define RNDIS_STATUS_TOKEN_RING_OPEN_ERROR (0xC0011000L)
+
+/* Object Identifiers used by NdisRequest Query/Set Information */
+/* General Objects */
+#define RNDIS_OID_GEN_SUPPORTED_LIST 0x00010101
+#define RNDIS_OID_GEN_HARDWARE_STATUS 0x00010102
+#define RNDIS_OID_GEN_MEDIA_SUPPORTED 0x00010103
+#define RNDIS_OID_GEN_MEDIA_IN_USE 0x00010104
+#define RNDIS_OID_GEN_MAXIMUM_LOOKAHEAD 0x00010105
+#define RNDIS_OID_GEN_MAXIMUM_FRAME_SIZE 0x00010106
+#define RNDIS_OID_GEN_LINK_SPEED 0x00010107
+#define RNDIS_OID_GEN_TRANSMIT_BUFFER_SPACE 0x00010108
+#define RNDIS_OID_GEN_RECEIVE_BUFFER_SPACE 0x00010109
+#define RNDIS_OID_GEN_TRANSMIT_BLOCK_SIZE 0x0001010A
+#define RNDIS_OID_GEN_RECEIVE_BLOCK_SIZE 0x0001010B
+#define RNDIS_OID_GEN_VENDOR_ID 0x0001010C
+#define RNDIS_OID_GEN_VENDOR_DESCRIPTION 0x0001010D
+#define RNDIS_OID_GEN_CURRENT_PACKET_FILTER 0x0001010E
+#define RNDIS_OID_GEN_CURRENT_LOOKAHEAD 0x0001010F
+#define RNDIS_OID_GEN_DRIVER_VERSION 0x00010110
+#define RNDIS_OID_GEN_MAXIMUM_TOTAL_SIZE 0x00010111
+#define RNDIS_OID_GEN_PROTOCOL_OPTIONS 0x00010112
+#define RNDIS_OID_GEN_MAC_OPTIONS 0x00010113
+#define RNDIS_OID_GEN_MEDIA_CONNECT_STATUS 0x00010114
+#define RNDIS_OID_GEN_MAXIMUM_SEND_PACKETS 0x00010115
+#define RNDIS_OID_GEN_VENDOR_DRIVER_VERSION 0x00010116
+#define RNDIS_OID_GEN_NETWORK_LAYER_ADDRESSES 0x00010118
+#define RNDIS_OID_GEN_TRANSPORT_HEADER_OFFSET 0x00010119
+#define RNDIS_OID_GEN_MACHINE_NAME 0x0001021A
+#define RNDIS_OID_GEN_RNDIS_CONFIG_PARAMETER 0x0001021B
+
+#define RNDIS_OID_GEN_XMIT_OK 0x00020101
+#define RNDIS_OID_GEN_RCV_OK 0x00020102
+#define RNDIS_OID_GEN_XMIT_ERROR 0x00020103
+#define RNDIS_OID_GEN_RCV_ERROR 0x00020104
+#define RNDIS_OID_GEN_RCV_NO_BUFFER 0x00020105
+
+#define RNDIS_OID_GEN_DIRECTED_BYTES_XMIT 0x00020201
+#define RNDIS_OID_GEN_DIRECTED_FRAMES_XMIT 0x00020202
+#define RNDIS_OID_GEN_MULTICAST_BYTES_XMIT 0x00020203
+#define RNDIS_OID_GEN_MULTICAST_FRAMES_XMIT 0x00020204
+#define RNDIS_OID_GEN_BROADCAST_BYTES_XMIT 0x00020205
+#define RNDIS_OID_GEN_BROADCAST_FRAMES_XMIT 0x00020206
+#define RNDIS_OID_GEN_DIRECTED_BYTES_RCV 0x00020207
+#define RNDIS_OID_GEN_DIRECTED_FRAMES_RCV 0x00020208
+#define RNDIS_OID_GEN_MULTICAST_BYTES_RCV 0x00020209
+#define RNDIS_OID_GEN_MULTICAST_FRAMES_RCV 0x0002020A
+#define RNDIS_OID_GEN_BROADCAST_BYTES_RCV 0x0002020B
+#define RNDIS_OID_GEN_BROADCAST_FRAMES_RCV 0x0002020C
+
+#define RNDIS_OID_GEN_RCV_CRC_ERROR 0x0002020D
+#define RNDIS_OID_GEN_TRANSMIT_QUEUE_LENGTH 0x0002020E
+
+#define RNDIS_OID_GEN_GET_TIME_CAPS 0x0002020F
+#define RNDIS_OID_GEN_GET_NETCARD_TIME 0x00020210
+
+/* These are connection-oriented general OIDs. */
+/* These replace the above OIDs for connection-oriented media. */
+#define RNDIS_OID_GEN_CO_SUPPORTED_LIST 0x00010101
+#define RNDIS_OID_GEN_CO_HARDWARE_STATUS 0x00010102
+#define RNDIS_OID_GEN_CO_MEDIA_SUPPORTED 0x00010103
+#define RNDIS_OID_GEN_CO_MEDIA_IN_USE 0x00010104
+#define RNDIS_OID_GEN_CO_LINK_SPEED 0x00010105
+#define RNDIS_OID_GEN_CO_VENDOR_ID 0x00010106
+#define RNDIS_OID_GEN_CO_VENDOR_DESCRIPTION 0x00010107
+#define RNDIS_OID_GEN_CO_DRIVER_VERSION 0x00010108
+#define RNDIS_OID_GEN_CO_PROTOCOL_OPTIONS 0x00010109
+#define RNDIS_OID_GEN_CO_MAC_OPTIONS 0x0001010A
+#define RNDIS_OID_GEN_CO_MEDIA_CONNECT_STATUS 0x0001010B
+#define RNDIS_OID_GEN_CO_VENDOR_DRIVER_VERSION 0x0001010C
+#define RNDIS_OID_GEN_CO_MINIMUM_LINK_SPEED 0x0001010D
+
+#define RNDIS_OID_GEN_CO_GET_TIME_CAPS 0x00010201
+#define RNDIS_OID_GEN_CO_GET_NETCARD_TIME 0x00010202
+
+/* These are connection-oriented statistics OIDs. */
+#define RNDIS_OID_GEN_CO_XMIT_PDUS_OK 0x00020101
+#define RNDIS_OID_GEN_CO_RCV_PDUS_OK 0x00020102
+#define RNDIS_OID_GEN_CO_XMIT_PDUS_ERROR 0x00020103
+#define RNDIS_OID_GEN_CO_RCV_PDUS_ERROR 0x00020104
+#define RNDIS_OID_GEN_CO_RCV_PDUS_NO_BUFFER 0x00020105
+
+
+#define RNDIS_OID_GEN_CO_RCV_CRC_ERROR 0x00020201
+#define RNDIS_OID_GEN_CO_TRANSMIT_QUEUE_LENGTH 0x00020202
+#define RNDIS_OID_GEN_CO_BYTES_XMIT 0x00020203
+#define RNDIS_OID_GEN_CO_BYTES_RCV 0x00020204
+#define RNDIS_OID_GEN_CO_BYTES_XMIT_OUTSTANDING 0x00020205
+#define RNDIS_OID_GEN_CO_NETCARD_LOAD 0x00020206
+
+/* These are objects for Connection-oriented media call-managers. */
+#define RNDIS_OID_CO_ADD_PVC 0xFF000001
+#define RNDIS_OID_CO_DELETE_PVC 0xFF000002
+#define RNDIS_OID_CO_GET_CALL_INFORMATION 0xFF000003
+#define RNDIS_OID_CO_ADD_ADDRESS 0xFF000004
+#define RNDIS_OID_CO_DELETE_ADDRESS 0xFF000005
+#define RNDIS_OID_CO_GET_ADDRESSES 0xFF000006
+#define RNDIS_OID_CO_ADDRESS_CHANGE 0xFF000007
+#define RNDIS_OID_CO_SIGNALING_ENABLED 0xFF000008
+#define RNDIS_OID_CO_SIGNALING_DISABLED 0xFF000009
+
+/* 802.3 Objects (Ethernet) */
+#define RNDIS_OID_802_3_PERMANENT_ADDRESS 0x01010101
+#define RNDIS_OID_802_3_CURRENT_ADDRESS 0x01010102
+#define RNDIS_OID_802_3_MULTICAST_LIST 0x01010103
+#define RNDIS_OID_802_3_MAXIMUM_LIST_SIZE 0x01010104
+#define RNDIS_OID_802_3_MAC_OPTIONS 0x01010105
+
+#define NDIS_802_3_MAC_OPTION_PRIORITY 0x00000001
+
+#define RNDIS_OID_802_3_RCV_ERROR_ALIGNMENT 0x01020101
+#define RNDIS_OID_802_3_XMIT_ONE_COLLISION 0x01020102
+#define RNDIS_OID_802_3_XMIT_MORE_COLLISIONS 0x01020103
+
+#define RNDIS_OID_802_3_XMIT_DEFERRED 0x01020201
+#define RNDIS_OID_802_3_XMIT_MAX_COLLISIONS 0x01020202
+#define RNDIS_OID_802_3_RCV_OVERRUN 0x01020203
+#define RNDIS_OID_802_3_XMIT_UNDERRUN 0x01020204
+#define RNDIS_OID_802_3_XMIT_HEARTBEAT_FAILURE 0x01020205
+#define RNDIS_OID_802_3_XMIT_TIMES_CRS_LOST 0x01020206
+#define RNDIS_OID_802_3_XMIT_LATE_COLLISIONS 0x01020207
+
+/* Remote NDIS message types */
+#define REMOTE_NDIS_PACKET_MSG 0x00000001
+#define REMOTE_NDIS_INITIALIZE_MSG 0x00000002
+#define REMOTE_NDIS_HALT_MSG 0x00000003
+#define REMOTE_NDIS_QUERY_MSG 0x00000004
+#define REMOTE_NDIS_SET_MSG 0x00000005
+#define REMOTE_NDIS_RESET_MSG 0x00000006
+#define REMOTE_NDIS_INDICATE_STATUS_MSG 0x00000007
+#define REMOTE_NDIS_KEEPALIVE_MSG 0x00000008
+
+#define REMOTE_CONDIS_MP_CREATE_VC_MSG 0x00008001
+#define REMOTE_CONDIS_MP_DELETE_VC_MSG 0x00008002
+#define REMOTE_CONDIS_MP_ACTIVATE_VC_MSG 0x00008005
+#define REMOTE_CONDIS_MP_DEACTIVATE_VC_MSG 0x00008006
+#define REMOTE_CONDIS_INDICATE_STATUS_MSG 0x00008007
+
+/* Remote NDIS message completion types */
+#define REMOTE_NDIS_INITIALIZE_CMPLT 0x80000002
+#define REMOTE_NDIS_QUERY_CMPLT 0x80000004
+#define REMOTE_NDIS_SET_CMPLT 0x80000005
+#define REMOTE_NDIS_RESET_CMPLT 0x80000006
+#define REMOTE_NDIS_KEEPALIVE_CMPLT 0x80000008
+
+#define REMOTE_CONDIS_MP_CREATE_VC_CMPLT 0x80008001
+#define REMOTE_CONDIS_MP_DELETE_VC_CMPLT 0x80008002
+#define REMOTE_CONDIS_MP_ACTIVATE_VC_CMPLT 0x80008005
+#define REMOTE_CONDIS_MP_DEACTIVATE_VC_CMPLT 0x80008006
+
+/*
+ * Reserved message type for private communication between lower-layer host
+ * driver and remote device, if necessary.
+ */
+#define REMOTE_NDIS_BUS_MSG 0xff000001
+
+/* Defines for DeviceFlags in struct rndis_initialize_complete */
+#define RNDIS_DF_CONNECTIONLESS 0x00000001
+#define RNDIS_DF_CONNECTION_ORIENTED 0x00000002
+#define RNDIS_DF_RAW_DATA 0x00000004
+
+/* Remote NDIS medium types. */
+#define RNDIS_MEDIUM_802_3 0x00000000
+#define RNDIS_MEDIUM_802_5 0x00000001
+#define RNDIS_MEDIUM_FDDI 0x00000002
+#define RNDIS_MEDIUM_WAN 0x00000003
+#define RNDIS_MEDIUM_LOCAL_TALK 0x00000004
+#define RNDIS_MEDIUM_ARCNET_RAW 0x00000006
+#define RNDIS_MEDIUM_ARCNET_878_2 0x00000007
+#define RNDIS_MEDIUM_ATM 0x00000008
+#define RNDIS_MEDIUM_WIRELESS_WAN 0x00000009
+#define RNDIS_MEDIUM_IRDA 0x0000000a
+#define RNDIS_MEDIUM_CO_WAN 0x0000000b
+/* Not a real medium, defined as an upper-bound */
+#define RNDIS_MEDIUM_MAX 0x0000000d
+
+
+/* Remote NDIS medium connection states. */
+#define RNDIS_MEDIA_STATE_CONNECTED 0x00000000
+#define RNDIS_MEDIA_STATE_DISCONNECTED 0x00000001
+
+/* Remote NDIS version numbers */
+#define RNDIS_MAJOR_VERSION 0x00000001
+#define RNDIS_MINOR_VERSION 0x00000000
+
+
+/* NdisInitialize message */
+struct rndis_initialize_request {
+ u32 req_id;
+ u32 major_ver;
+ u32 minor_ver;
+ u32 max_xfer_size;
+};
+
+/* Response to NdisInitialize */
+struct rndis_initialize_complete {
+ u32 req_id;
+ u32 status;
+ u32 major_ver;
+ u32 minor_ver;
+ u32 dev_flags;
+ u32 medium;
+ u32 max_pkt_per_msg;
+ u32 max_xfer_size;
+ u32 pkt_alignment_factor;
+ u32 af_list_offset;
+ u32 af_list_size;
+};
+
+/* Call manager devices only: Information about an address family */
+/* supported by the device is appended to the response to NdisInitialize. */
+struct rndis_co_address_family {
+ u32 address_family;
+ u32 major_ver;
+ u32 minor_ver;
+};
+
+/* NdisHalt message */
+struct rndis_halt_request {
+ u32 req_id;
+};
+
+/* NdisQueryRequest message */
+struct rndis_query_request {
+ u32 req_id;
+ u32 oid;
+ u32 info_buflen;
+ u32 info_buf_offset;
+ u32 dev_vc_handle;
+};
+
+/* Response to NdisQueryRequest */
+struct rndis_query_complete {
+ u32 req_id;
+ u32 status;
+ u32 info_buflen;
+ u32 info_buf_offset;
+};
+
+/* NdisSetRequest message */
+struct rndis_set_request {
+ u32 req_id;
+ u32 oid;
+ u32 info_buflen;
+ u32 info_buf_offset;
+ u32 dev_vc_handle;
+};
+
+/* Response to NdisSetRequest */
+struct rndis_set_complete {
+ u32 req_id;
+ u32 status;
+};
+
+/* NdisReset message */
+struct rndis_reset_request {
+ u32 reserved;
+};
+
+/* Response to NdisReset */
+struct rndis_reset_complete {
+ u32 status;
+ u32 addressing_reset;
+};
+
+/* NdisMIndicateStatus message */
+struct rndis_indicate_status {
+ u32 status;
+ u32 status_buflen;
+ u32 status_buf_offset;
+};
+
+/* Diagnostic information passed as the status buffer in */
+/* struct rndis_indicate_status messages signifying error conditions. */
+struct rndis_diagnostic_info {
+ u32 diag_status;
+ u32 error_offset;
+};
+
+/* NdisKeepAlive message */
+struct rndis_keepalive_request {
+ u32 req_id;
+};
+
+/* Response to NdisKeepAlive */
+struct rndis_keepalive_complete {
+ u32 req_id;
+ u32 status;
+};
+
+/*
+ * Data message. All Offset fields contain byte offsets from the beginning of
+ * struct rndis_packet. All Length fields are in bytes. VcHandle is set
+ * to 0 for connectionless data, otherwise it contains the VC handle.
+ */
+struct rndis_packet {
+ u32 data_offset;
+ u32 data_len;
+ u32 oob_data_offset;
+ u32 oob_data_len;
+ u32 num_oob_data_elements;
+ u32 per_pkt_info_offset;
+ u32 per_pkt_info_len;
+ u32 vc_handle;
+ u32 reserved;
+};
+
+/* Optional Out of Band data associated with a Data message. */
+struct rndis_oobd {
+ u32 size;
+ u32 type;
+ u32 class_info_offset;
+};
+
+/* Packet extension field contents associated with a Data message. */
+struct rndis_per_packet_info {
+ u32 size;
+ u32 type;
+ u32 per_pkt_info_offset;
+};
+
+/* Format of Information buffer passed in a SetRequest for the OID */
+/* OID_GEN_RNDIS_CONFIG_PARAMETER. */
+struct rndis_config_parameter_info {
+ u32 parameter_name_offset;
+ u32 parameter_name_length;
+ u32 parameter_type;
+ u32 parameter_value_offset;
+ u32 parameter_value_length;
+};
+
+/* Values for ParameterType in struct rndis_config_parameter_info */
+#define RNDIS_CONFIG_PARAM_TYPE_INTEGER 0
+#define RNDIS_CONFIG_PARAM_TYPE_STRING 2
+
+/* CONDIS Miniport messages for connection oriented devices */
+/* that do not implement a call manager. */
+
+/* CoNdisMiniportCreateVc message */
+struct rcondis_mp_create_vc {
+ u32 req_id;
+ u32 ndis_vc_handle;
+};
+
+/* Response to CoNdisMiniportCreateVc */
+struct rcondis_mp_create_vc_complete {
+ u32 req_id;
+ u32 dev_vc_handle;
+ u32 status;
+};
+
+/* CoNdisMiniportDeleteVc message */
+struct rcondis_mp_delete_vc {
+ u32 req_id;
+ u32 dev_vc_handle;
+};
+
+/* Response to CoNdisMiniportDeleteVc */
+struct rcondis_mp_delete_vc_complete {
+ u32 req_id;
+ u32 status;
+};
+
+/* CoNdisMiniportQueryRequest message */
+struct rcondis_mp_query_request {
+ u32 req_id;
+ u32 request_type;
+ u32 oid;
+ u32 dev_vc_handle;
+ u32 info_buflen;
+ u32 info_buf_offset;
+};
+
+/* CoNdisMiniportSetRequest message */
+struct rcondis_mp_set_request {
+ u32 req_id;
+ u32 request_type;
+ u32 oid;
+ u32 dev_vc_handle;
+ u32 info_buflen;
+ u32 info_buf_offset;
+};
+
+/* CoNdisIndicateStatus message */
+struct rcondis_indicate_status {
+ u32 ndis_vc_handle;
+ u32 status;
+ u32 status_buflen;
+ u32 status_buf_offset;
+};
+
+/* CONDIS Call/VC parameters */
+struct rcondis_specific_parameters {
+ u32 parameter_type;
+ u32 parameter_length;
+ u32 parameter_lffset;
+};
+
+struct rcondis_media_parameters {
+ u32 flags;
+ u32 reserved1;
+ u32 reserved2;
+ struct rcondis_specific_parameters media_specific;
+};
+
+struct rndis_flowspec {
+ u32 token_rate;
+ u32 token_bucket_size;
+ u32 peak_bandwidth;
+ u32 latency;
+ u32 delay_variation;
+ u32 service_type;
+ u32 max_sdu_size;
+ u32 minimum_policed_size;
+};
+
+struct rcondis_call_manager_parameters {
+ struct rndis_flowspec transmit;
+ struct rndis_flowspec receive;
+ struct rcondis_specific_parameters call_mgr_specific;
+};
+
+/* CoNdisMiniportActivateVc message */
+struct rcondis_mp_activate_vc_request {
+ u32 req_id;
+ u32 flags;
+ u32 dev_vc_handle;
+ u32 media_params_offset;
+ u32 media_params_length;
+ u32 call_mgr_params_offset;
+ u32 call_mgr_params_length;
+};
+
+/* Response to CoNdisMiniportActivateVc */
+struct rcondis_mp_activate_vc_complete {
+ u32 req_id;
+ u32 status;
+};
+
+/* CoNdisMiniportDeactivateVc message */
+struct rcondis_mp_deactivate_vc_request {
+ u32 req_id;
+ u32 flags;
+ u32 dev_vc_handle;
+};
+
+/* Response to CoNdisMiniportDeactivateVc */
+struct rcondis_mp_deactivate_vc_complete {
+ u32 req_id;
+ u32 status;
+};
+
+
+/* union with all of the RNDIS messages */
+union rndis_message_container {
+ struct rndis_packet pkt;
+ struct rndis_initialize_request init_req;
+ struct rndis_halt_request halt_req;
+ struct rndis_query_request query_req;
+ struct rndis_set_request set_req;
+ struct rndis_reset_request reset_req;
+ struct rndis_keepalive_request keep_alive_req;
+ struct rndis_indicate_status indicate_status;
+ struct rndis_initialize_complete init_complete;
+ struct rndis_query_complete query_complete;
+ struct rndis_set_complete set_complete;
+ struct rndis_reset_complete reset_complete;
+ struct rndis_keepalive_complete keep_alive_complete;
+ struct rcondis_mp_create_vc co_miniport_create_vc;
+ struct rcondis_mp_delete_vc co_miniport_delete_vc;
+ struct rcondis_indicate_status co_indicate_status;
+ struct rcondis_mp_activate_vc_request co_miniport_activate_vc;
+ struct rcondis_mp_deactivate_vc_request co_miniport_deactivate_vc;
+ struct rcondis_mp_create_vc_complete co_miniport_create_vc_complete;
+ struct rcondis_mp_delete_vc_complete co_miniport_delete_vc_complete;
+ struct rcondis_mp_activate_vc_complete co_miniport_activate_vc_complete;
+ struct rcondis_mp_deactivate_vc_complete
+ co_miniport_deactivate_vc_complete;
+};
+
+/* Remote NDIS message format */
+struct rndis_message {
+ u32 ndis_msg_type;
+
+ /* Total length of this message, from the beginning */
+ /* of the sruct rndis_message, in bytes. */
+ u32 msg_len;
+
+ /* Actual message */
+ union rndis_message_container msg;
+};
+
+
+struct rndis_filter_packet {
+ void *completion_ctx;
+ void (*completion)(void *context);
+ struct rndis_message msg;
+};
+
+/* Handy macros */
+
+/* get the size of an RNDIS message. Pass in the message type, */
+/* struct rndis_set_request, struct rndis_packet for example */
+#define RNDIS_MESSAGE_SIZE(msg) \
+ (sizeof(msg) + (sizeof(struct rndis_message) - \
+ sizeof(union rndis_message_container)))
+
+/* get pointer to info buffer with message pointer */
+#define MESSAGE_TO_INFO_BUFFER(msg) \
+ (((unsigned char *)(msg)) + msg->info_buf_offset)
+
+/* get pointer to status buffer with message pointer */
+#define MESSAGE_TO_STATUS_BUFFER(msg) \
+ (((unsigned char *)(msg)) + msg->status_buf_offset)
+
+/* get pointer to OOBD buffer with message pointer */
+#define MESSAGE_TO_OOBD_BUFFER(msg) \
+ (((unsigned char *)(msg)) + msg->oob_data_offset)
+
+/* get pointer to data buffer with message pointer */
+#define MESSAGE_TO_DATA_BUFFER(msg) \
+ (((unsigned char *)(msg)) + msg->per_pkt_info_offset)
+
+/* get pointer to contained message from NDIS_MESSAGE pointer */
+#define RNDIS_MESSAGE_PTR_TO_MESSAGE_PTR(rndis_msg) \
+ ((void *) &rndis_msg->msg)
+
+/* get pointer to contained message from NDIS_MESSAGE pointer */
+#define RNDIS_MESSAGE_RAW_PTR_TO_MESSAGE_PTR(rndis_msg) \
+ ((void *) rndis_msg)
+
+
+#define __struct_bcount(x)
+
+
+
+#define RNDIS_HEADER_SIZE (sizeof(struct rndis_message) - \
+ sizeof(union rndis_message_container))
+
+#define NDIS_PACKET_TYPE_DIRECTED 0x00000001
+#define NDIS_PACKET_TYPE_MULTICAST 0x00000002
+#define NDIS_PACKET_TYPE_ALL_MULTICAST 0x00000004
+#define NDIS_PACKET_TYPE_BROADCAST 0x00000008
+#define NDIS_PACKET_TYPE_SOURCE_ROUTING 0x00000010
+#define NDIS_PACKET_TYPE_PROMISCUOUS 0x00000020
+#define NDIS_PACKET_TYPE_SMT 0x00000040
+#define NDIS_PACKET_TYPE_ALL_LOCAL 0x00000080
+#define NDIS_PACKET_TYPE_GROUP 0x00000100
+#define NDIS_PACKET_TYPE_ALL_FUNCTIONAL 0x00000200
+#define NDIS_PACKET_TYPE_FUNCTIONAL 0x00000400
+#define NDIS_PACKET_TYPE_MAC_FRAME 0x00000800
+
+
+
+#endif /* _HYPERV_NET_H */
diff --git a/drivers/staging/hv/hyperv_storage.h b/drivers/staging/hv/hyperv_storage.h
new file mode 100644
index 0000000..a01f9a0
--- /dev/null
+++ b/drivers/staging/hv/hyperv_storage.h
@@ -0,0 +1,334 @@
+/*
+ *
+ * Copyright (c) 2011, Microsoft Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
+ * Place - Suite 330, Boston, MA 02111-1307 USA.
+ *
+ * Authors:
+ * Haiyang Zhang <haiyangz@microsoft.com>
+ * Hank Janssen <hjanssen@microsoft.com>
+ * K. Y. Srinivasan <kys@microsoft.com>
+ *
+ */
+
+#ifndef _HYPERV_STORAGE_H
+#define _HYPERV_STORAGE_H
+
+
+/* vstorage.w revision number. This is used in the case of a version match, */
+/* to alert the user that structure sizes may be mismatched even though the */
+/* protocol versions match. */
+
+
+#define REVISION_STRING(REVISION_) #REVISION_
+#define FILL_VMSTOR_REVISION(RESULT_LVALUE_) \
+ do { \
+ char *revision_string \
+ = REVISION_STRING($Rev : 6 $) + 6; \
+ RESULT_LVALUE_ = 0; \
+ while (*revision_string >= '0' \
+ && *revision_string <= '9') { \
+ RESULT_LVALUE_ *= 10; \
+ RESULT_LVALUE_ += *revision_string - '0'; \
+ revision_string++; \
+ } \
+ } while (0)
+
+/* Major/minor macros. Minor version is in LSB, meaning that earlier flat */
+/* version numbers will be interpreted as "0.x" (i.e., 1 becomes 0.1). */
+#define VMSTOR_PROTOCOL_MAJOR(VERSION_) (((VERSION_) >> 8) & 0xff)
+#define VMSTOR_PROTOCOL_MINOR(VERSION_) (((VERSION_)) & 0xff)
+#define VMSTOR_PROTOCOL_VERSION(MAJOR_, MINOR_) ((((MAJOR_) & 0xff) << 8) | \
+ (((MINOR_) & 0xff)))
+#define VMSTOR_INVALID_PROTOCOL_VERSION (-1)
+
+/* Version history: */
+/* V1 Beta 0.1 */
+/* V1 RC < 2008/1/31 1.0 */
+/* V1 RC > 2008/1/31 2.0 */
+#define VMSTOR_PROTOCOL_VERSION_CURRENT VMSTOR_PROTOCOL_VERSION(2, 0)
+
+
+
+
+/* This will get replaced with the max transfer length that is possible on */
+/* the host adapter. */
+/* The max transfer length will be published when we offer a vmbus channel. */
+#define MAX_TRANSFER_LENGTH 0x40000
+#define DEFAULT_PACKET_SIZE (sizeof(struct vmdata_gpa_direct) + \
+ sizeof(struct vstor_packet) + \
+ sizesizeof(u64) * (MAX_TRANSFER_LENGTH / PAGE_SIZE)))
+
+
+/* Packet structure describing virtual storage requests. */
+enum vstor_packet_operation {
+ VSTOR_OPERATION_COMPLETE_IO = 1,
+ VSTOR_OPERATION_REMOVE_DEVICE = 2,
+ VSTOR_OPERATION_EXECUTE_SRB = 3,
+ VSTOR_OPERATION_RESET_LUN = 4,
+ VSTOR_OPERATION_RESET_ADAPTER = 5,
+ VSTOR_OPERATION_RESET_BUS = 6,
+ VSTOR_OPERATION_BEGIN_INITIALIZATION = 7,
+ VSTOR_OPERATION_END_INITIALIZATION = 8,
+ VSTOR_OPERATION_QUERY_PROTOCOL_VERSION = 9,
+ VSTOR_OPERATION_QUERY_PROPERTIES = 10,
+ VSTOR_OPERATION_MAXIMUM = 10
+};
+
+/*
+ * Platform neutral description of a scsi request -
+ * this remains the same across the write regardless of 32/64 bit
+ * note: it's patterned off the SCSI_PASS_THROUGH structure
+ */
+#define CDB16GENERIC_LENGTH 0x10
+
+#ifndef SENSE_BUFFER_SIZE
+#define SENSE_BUFFER_SIZE 0x12
+#endif
+
+#define MAX_DATA_BUF_LEN_WITH_PADDING 0x14
+
+struct vmscsi_request {
+ unsigned short length;
+ unsigned char srb_status;
+ unsigned char scsi_status;
+
+ unsigned char port_number;
+ unsigned char path_id;
+ unsigned char target_id;
+ unsigned char lun;
+
+ unsigned char cdb_length;
+ unsigned char sense_info_length;
+ unsigned char data_in;
+ unsigned char reserved;
+
+ unsigned int data_transfer_length;
+
+ union {
+ unsigned char cdb[CDB16GENERIC_LENGTH];
+ unsigned char sense_data[SENSE_BUFFER_SIZE];
+ unsigned char reserved_array[MAX_DATA_BUF_LEN_WITH_PADDING];
+ };
+} __attribute((packed));
+
+
+/*
+ * This structure is sent during the intialization phase to get the different
+ * properties of the channel.
+ */
+struct vmstorage_channel_properties {
+ unsigned short protocol_version;
+ unsigned char path_id;
+ unsigned char target_id;
+
+ /* Note: port number is only really known on the client side */
+ unsigned int port_number;
+ unsigned int flags;
+ unsigned int max_transfer_bytes;
+
+ /* This id is unique for each channel and will correspond with */
+ /* vendor specific data in the inquirydata */
+ unsigned long long unique_id;
+} __packed;
+
+/* This structure is sent during the storage protocol negotiations. */
+struct vmstorage_protocol_version {
+ /* Major (MSW) and minor (LSW) version numbers. */
+ unsigned short major_minor;
+
+ /*
+ * Revision number is auto-incremented whenever this file is changed
+ * (See FILL_VMSTOR_REVISION macro above). Mismatch does not
+ * definitely indicate incompatibility--but it does indicate mismatched
+ * builds.
+ */
+ unsigned short revision;
+} __packed;
+
+/* Channel Property Flags */
+#define STORAGE_CHANNEL_REMOVABLE_FLAG 0x1
+#define STORAGE_CHANNEL_EMULATED_IDE_FLAG 0x2
+
+struct vstor_packet {
+ /* Requested operation type */
+ enum vstor_packet_operation operation;
+
+ /* Flags - see below for values */
+ unsigned int flags;
+
+ /* Status of the request returned from the server side. */
+ unsigned int status;
+
+ /* Data payload area */
+ union {
+ /*
+ * Structure used to forward SCSI commands from the
+ * client to the server.
+ */
+ struct vmscsi_request vm_srb;
+
+ /* Structure used to query channel properties. */
+ struct vmstorage_channel_properties storage_channel_properties;
+
+ /* Used during version negotiations. */
+ struct vmstorage_protocol_version version;
+ };
+} __packed;
+
+/* Packet flags */
+/*
+ * This flag indicates that the server should send back a completion for this
+ * packet.
+ */
+#define REQUEST_COMPLETION_FLAG 0x1
+
+/* This is the set of flags that the vsc can set in any packets it sends */
+#define VSC_LEGAL_FLAGS (REQUEST_COMPLETION_FLAG)
+
+
+#include <linux/kernel.h>
+#include <linux/wait.h>
+#include "hyperv_storage.h"
+#include "hyperv.h"
+
+/* Defines */
+#define STORVSC_RING_BUFFER_SIZE (20*PAGE_SIZE)
+#define BLKVSC_RING_BUFFER_SIZE (20*PAGE_SIZE)
+
+#define STORVSC_MAX_IO_REQUESTS 128
+
+/*
+ * In Hyper-V, each port/path/target maps to 1 scsi host adapter. In
+ * reality, the path/target is not used (ie always set to 0) so our
+ * scsi host adapter essentially has 1 bus with 1 target that contains
+ * up to 256 luns.
+ */
+#define STORVSC_MAX_LUNS_PER_TARGET 64
+#define STORVSC_MAX_TARGETS 1
+#define STORVSC_MAX_CHANNELS 1
+
+struct hv_storvsc_request;
+
+/* Matches Windows-end */
+enum storvsc_request_type {
+ WRITE_TYPE,
+ READ_TYPE,
+ UNKNOWN_TYPE,
+};
+
+
+struct hv_storvsc_request {
+ struct hv_storvsc_request *request;
+ struct hv_device *device;
+
+ /* Synchronize the request/response if needed */
+ struct completion wait_event;
+
+ unsigned char *sense_buffer;
+ void *context;
+ void (*on_io_completion)(struct hv_storvsc_request *request);
+ struct hv_multipage_buffer data_buffer;
+
+ struct vstor_packet vstor_packet;
+};
+
+
+struct storvsc_device_info {
+ u32 ring_buffer_size;
+ unsigned int port_number;
+ unsigned char path_id;
+ unsigned char target_id;
+};
+
+struct storvsc_major_info {
+ int major;
+ int index;
+ bool do_register;
+ char *devname;
+ char *diskname;
+};
+
+/* A storvsc device is a device object that contains a vmbus channel */
+struct storvsc_device {
+ struct hv_device *device;
+
+ /* 0 indicates the device is being destroyed */
+ atomic_t ref_count;
+
+ bool drain_notify;
+ atomic_t num_outstanding_req;
+
+ wait_queue_head_t waiting_to_drain;
+
+ /*
+ * Each unique Port/Path/Target represents 1 channel ie scsi
+ * controller. In reality, the pathid, targetid is always 0
+ * and the port is set by us
+ */
+ unsigned int port_number;
+ unsigned char path_id;
+ unsigned char target_id;
+
+ /* Used for vsc/vsp channel reset process */
+ struct hv_storvsc_request init_request;
+ struct hv_storvsc_request reset_request;
+};
+
+
+/* Get the stordevice object iff exists and its refcount > 1 */
+static inline struct storvsc_device *get_stor_device(struct hv_device *device)
+{
+ struct storvsc_device *stor_device;
+
+ stor_device = (struct storvsc_device *)device->ext;
+ if (stor_device && atomic_read(&stor_device->ref_count) > 1)
+ atomic_inc(&stor_device->ref_count);
+ else
+ stor_device = NULL;
+
+ return stor_device;
+}
+
+
+static inline void put_stor_device(struct hv_device *device)
+{
+ struct storvsc_device *stor_device;
+
+ stor_device = (struct storvsc_device *)device->ext;
+
+ atomic_dec(&stor_device->ref_count);
+}
+
+static inline void storvsc_wait_to_drain(struct storvsc_device *dev)
+{
+ dev->drain_notify = true;
+ wait_event(dev->waiting_to_drain,
+ atomic_read(&dev->num_outstanding_req) == 0);
+ dev->drain_notify = false;
+}
+
+/* Interface */
+
+int storvsc_dev_add(struct hv_device *device,
+ void *additional_info);
+int storvsc_dev_remove(struct hv_device *device);
+
+int storvsc_do_io(struct hv_device *device,
+ struct hv_storvsc_request *request);
+
+int storvsc_get_major_info(struct storvsc_device_info *device_info,
+ struct storvsc_major_info *major_info);
+
+#endif /* _HYPERV_STORAGE_H */
diff --git a/drivers/staging/hv/hyperv_vmbus.h b/drivers/staging/hv/hyperv_vmbus.h
new file mode 100644
index 0000000..bf30a42
--- /dev/null
+++ b/drivers/staging/hv/hyperv_vmbus.h
@@ -0,0 +1,631 @@
+/*
+ *
+ * Copyright (c) 2011, Microsoft Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
+ * Place - Suite 330, Boston, MA 02111-1307 USA.
+ *
+ * Authors:
+ * Haiyang Zhang <haiyangz@microsoft.com>
+ * Hank Janssen <hjanssen@microsoft.com>
+ * K. Y. Srinivasan <kys@microsoft.com>
+ *
+ */
+
+#ifndef _HYPERV_VMBUS_H
+#define _HYPERV_VMBUS_H
+
+#include <linux/list.h>
+#include <asm/sync_bitops.h>
+#include <linux/atomic.h>
+
+#include "hyperv.h"
+
+/*
+ * The below CPUID leaves are present if VersionAndFeatures.HypervisorPresent
+ * is set by CPUID(HVCPUID_VERSION_FEATURES).
+ */
+enum hv_cpuid_function {
+ HVCPUID_VERSION_FEATURES = 0x00000001,
+ HVCPUID_VENDOR_MAXFUNCTION = 0x40000000,
+ HVCPUID_INTERFACE = 0x40000001,
+
+ /*
+ * The remaining functions depend on the value of
+ * HVCPUID_INTERFACE
+ */
+ HVCPUID_VERSION = 0x40000002,
+ HVCPUID_FEATURES = 0x40000003,
+ HVCPUID_ENLIGHTENMENT_INFO = 0x40000004,
+ HVCPUID_IMPLEMENTATION_LIMITS = 0x40000005,
+};
+
+/* Define version of the synthetic interrupt controller. */
+#define HV_SYNIC_VERSION (1)
+
+/* Define the expected SynIC version. */
+#define HV_SYNIC_VERSION_1 (0x1)
+
+/* Define synthetic interrupt controller message constants. */
+#define HV_MESSAGE_SIZE (256)
+#define HV_MESSAGE_PAYLOAD_BYTE_COUNT (240)
+#define HV_MESSAGE_PAYLOAD_QWORD_COUNT (30)
+#define HV_ANY_VP (0xFFFFFFFF)
+
+/* Define synthetic interrupt controller flag constants. */
+#define HV_EVENT_FLAGS_COUNT (256 * 8)
+#define HV_EVENT_FLAGS_BYTE_COUNT (256)
+#define HV_EVENT_FLAGS_DWORD_COUNT (256 / sizeof(u32))
+
+/* Define hypervisor message types. */
+enum hv_message_type {
+ HVMSG_NONE = 0x00000000,
+
+ /* Memory access messages. */
+ HVMSG_UNMAPPED_GPA = 0x80000000,
+ HVMSG_GPA_INTERCEPT = 0x80000001,
+
+ /* Timer notification messages. */
+ HVMSG_TIMER_EXPIRED = 0x80000010,
+
+ /* Error messages. */
+ HVMSG_INVALID_VP_REGISTER_VALUE = 0x80000020,
+ HVMSG_UNRECOVERABLE_EXCEPTION = 0x80000021,
+ HVMSG_UNSUPPORTED_FEATURE = 0x80000022,
+
+ /* Trace buffer complete messages. */
+ HVMSG_EVENTLOG_BUFFERCOMPLETE = 0x80000040,
+
+ /* Platform-specific processor intercept messages. */
+ HVMSG_X64_IOPORT_INTERCEPT = 0x80010000,
+ HVMSG_X64_MSR_INTERCEPT = 0x80010001,
+ HVMSG_X64_CPUID_INTERCEPT = 0x80010002,
+ HVMSG_X64_EXCEPTION_INTERCEPT = 0x80010003,
+ HVMSG_X64_APIC_EOI = 0x80010004,
+ HVMSG_X64_LEGACY_FP_ERROR = 0x80010005
+};
+
+/* Define the number of synthetic interrupt sources. */
+#define HV_SYNIC_SINT_COUNT (16)
+#define HV_SYNIC_STIMER_COUNT (4)
+
+/* Define invalid partition identifier. */
+#define HV_PARTITION_ID_INVALID ((u64)0x0)
+
+/* Define connection identifier type. */
+union hv_connection_id {
+ u32 asu32;
+ struct {
+ u32 id:24;
+ u32 reserved:8;
+ } u;
+};
+
+/* Define port identifier type. */
+union hv_port_id {
+ u32 asu32;
+ struct {
+ u32 id:24;
+ u32 reserved:8;
+ } u ;
+};
+
+/* Define port type. */
+enum hv_port_type {
+ HVPORT_MSG = 1,
+ HVPORT_EVENT = 2,
+ HVPORT_MONITOR = 3
+};
+
+/* Define port information structure. */
+struct hv_port_info {
+ enum hv_port_type port_type;
+ u32 padding;
+ union {
+ struct {
+ u32 target_sint;
+ u32 target_vp;
+ u64 rsvdz;
+ } message_port_info;
+ struct {
+ u32 target_sint;
+ u32 target_vp;
+ u16 base_flag_bumber;
+ u16 flag_count;
+ u32 rsvdz;
+ } event_port_info;
+ struct {
+ u64 monitor_address;
+ u64 rsvdz;
+ } monitor_port_info;
+ };
+};
+
+struct hv_connection_info {
+ enum hv_port_type port_type;
+ u32 padding;
+ union {
+ struct {
+ u64 rsvdz;
+ } message_connection_info;
+ struct {
+ u64 rsvdz;
+ } event_connection_info;
+ struct {
+ u64 monitor_address;
+ } monitor_connection_info;
+ };
+};
+
+/* Define synthetic interrupt controller message flags. */
+union hv_message_flags {
+ u8 asu8;
+ struct {
+ u8 msg_pending:1;
+ u8 reserved:7;
+ };
+};
+
+/* Define synthetic interrupt controller message header. */
+struct hv_message_header {
+ enum hv_message_type message_type;
+ u8 payload_size;
+ union hv_message_flags message_flags;
+ u8 reserved[2];
+ union {
+ u64 sender;
+ union hv_port_id port;
+ };
+};
+
+/* Define timer message payload structure. */
+struct hv_timer_message_payload {
+ u32 timer_index;
+ u32 reserved;
+ u64 expiration_time; /* When the timer expired */
+ u64 delivery_time; /* When the message was delivered */
+};
+
+/* Define synthetic interrupt controller message format. */
+struct hv_message {
+ struct hv_message_header header;
+ union {
+ u64 payload[HV_MESSAGE_PAYLOAD_QWORD_COUNT];
+ } u ;
+};
+
+/* Define the number of message buffers associated with each port. */
+#define HV_PORT_MESSAGE_BUFFER_COUNT (16)
+
+/* Define the synthetic interrupt message page layout. */
+struct hv_message_page {
+ struct hv_message sint_message[HV_SYNIC_SINT_COUNT];
+};
+
+/* Define the synthetic interrupt controller event flags format. */
+union hv_synic_event_flags {
+ u8 flags8[HV_EVENT_FLAGS_BYTE_COUNT];
+ u32 flags32[HV_EVENT_FLAGS_DWORD_COUNT];
+};
+
+/* Define the synthetic interrupt flags page layout. */
+struct hv_synic_event_flags_page {
+ union hv_synic_event_flags sintevent_flags[HV_SYNIC_SINT_COUNT];
+};
+
+/* Define SynIC control register. */
+union hv_synic_scontrol {
+ u64 as_uint64;
+ struct {
+ u64 enable:1;
+ u64 reserved:63;
+ };
+};
+
+/* Define synthetic interrupt source. */
+union hv_synic_sint {
+ u64 as_uint64;
+ struct {
+ u64 vector:8;
+ u64 reserved1:8;
+ u64 masked:1;
+ u64 auto_eoi:1;
+ u64 reserved2:46;
+ };
+};
+
+/* Define the format of the SIMP register */
+union hv_synic_simp {
+ u64 as_uint64;
+ struct {
+ u64 simp_enabled:1;
+ u64 preserved:11;
+ u64 base_simp_gpa:52;
+ };
+};
+
+/* Define the format of the SIEFP register */
+union hv_synic_siefp {
+ u64 as_uint64;
+ struct {
+ u64 siefp_enabled:1;
+ u64 preserved:11;
+ u64 base_siefp_gpa:52;
+ };
+};
+
+/* Definitions for the monitored notification facility */
+union hv_monitor_trigger_group {
+ u64 as_uint64;
+ struct {
+ u32 pending;
+ u32 armed;
+ };
+};
+
+struct hv_monitor_parameter {
+ union hv_connection_id connectionid;
+ u16 flagnumber;
+ u16 rsvdz;
+};
+
+union hv_monitor_trigger_state {
+ u32 asu32;
+
+ struct {
+ u32 group_enable:4;
+ u32 rsvdz:28;
+ };
+};
+
+/* struct hv_monitor_page Layout */
+/* ------------------------------------------------------ */
+/* | 0 | TriggerState (4 bytes) | Rsvd1 (4 bytes) | */
+/* | 8 | TriggerGroup[0] | */
+/* | 10 | TriggerGroup[1] | */
+/* | 18 | TriggerGroup[2] | */
+/* | 20 | TriggerGroup[3] | */
+/* | 28 | Rsvd2[0] | */
+/* | 30 | Rsvd2[1] | */
+/* | 38 | Rsvd2[2] | */
+/* | 40 | NextCheckTime[0][0] | NextCheckTime[0][1] | */
+/* | ... | */
+/* | 240 | Latency[0][0..3] | */
+/* | 340 | Rsvz3[0] | */
+/* | 440 | Parameter[0][0] | */
+/* | 448 | Parameter[0][1] | */
+/* | ... | */
+/* | 840 | Rsvd4[0] | */
+/* ------------------------------------------------------ */
+struct hv_monitor_page {
+ union hv_monitor_trigger_state trigger_state;
+ u32 rsvdz1;
+
+ union hv_monitor_trigger_group trigger_group[4];
+ u64 rsvdz2[3];
+
+ s32 next_checktime[4][32];
+
+ u16 latency[4][32];
+ u64 rsvdz3[32];
+
+ struct hv_monitor_parameter parameter[4][32];
+
+ u8 rsvdz4[1984];
+};
+
+/* Declare the various hypercall operations. */
+enum hv_call_code {
+ HVCALL_POST_MESSAGE = 0x005c,
+ HVCALL_SIGNAL_EVENT = 0x005d,
+};
+
+/* Definition of the hv_post_message hypercall input structure. */
+struct hv_input_post_message {
+ union hv_connection_id connectionid;
+ u32 reserved;
+ enum hv_message_type message_type;
+ u32 payload_size;
+ u64 payload[HV_MESSAGE_PAYLOAD_QWORD_COUNT];
+};
+
+/* Definition of the hv_signal_event hypercall input structure. */
+struct hv_input_signal_event {
+ union hv_connection_id connectionid;
+ u16 flag_number;
+ u16 rsvdz;
+};
+
+/*
+ * Versioning definitions used for guests reporting themselves to the
+ * hypervisor, and visa versa.
+ */
+
+/* Version info reported by guest OS's */
+enum hv_guest_os_vendor {
+ HVGUESTOS_VENDOR_MICROSOFT = 0x0001
+};
+
+enum hv_guest_os_microsoft_ids {
+ HVGUESTOS_MICROSOFT_UNDEFINED = 0x00,
+ HVGUESTOS_MICROSOFT_MSDOS = 0x01,
+ HVGUESTOS_MICROSOFT_WINDOWS3X = 0x02,
+ HVGUESTOS_MICROSOFT_WINDOWS9X = 0x03,
+ HVGUESTOS_MICROSOFT_WINDOWSNT = 0x04,
+ HVGUESTOS_MICROSOFT_WINDOWSCE = 0x05
+};
+
+/*
+ * Declare the MSR used to identify the guest OS.
+ */
+#define HV_X64_MSR_GUEST_OS_ID 0x40000000
+
+union hv_x64_msr_guest_os_id_contents {
+ u64 as_uint64;
+ struct {
+ u64 build_number:16;
+ u64 service_version:8; /* Service Pack, etc. */
+ u64 minor_version:8;
+ u64 major_version:8;
+ u64 os_id:8; /* enum hv_guest_os_microsoft_ids (if Vendor=MS) */
+ u64 vendor_id:16; /* enum hv_guest_os_vendor */
+ };
+};
+
+/*
+ * Declare the MSR used to setup pages used to communicate with the hypervisor.
+ */
+#define HV_X64_MSR_HYPERCALL 0x40000001
+
+union hv_x64_msr_hypercall_contents {
+ u64 as_uint64;
+ struct {
+ u64 enable:1;
+ u64 reserved:11;
+ u64 guest_physical_address:52;
+ };
+};
+
+
+enum {
+ VMBUS_MESSAGE_CONNECTION_ID = 1,
+ VMBUS_MESSAGE_PORT_ID = 1,
+ VMBUS_EVENT_CONNECTION_ID = 2,
+ VMBUS_EVENT_PORT_ID = 2,
+ VMBUS_MONITOR_CONNECTION_ID = 3,
+ VMBUS_MONITOR_PORT_ID = 3,
+ VMBUS_MESSAGE_SINT = 2,
+};
+
+/* #defines */
+
+#define HV_PRESENT_BIT 0x80000000
+
+#define HV_LINUX_GUEST_ID_LO 0x00000000
+#define HV_LINUX_GUEST_ID_HI 0xB16B00B5
+#define HV_LINUX_GUEST_ID (((u64)HV_LINUX_GUEST_ID_HI << 32) | \
+ HV_LINUX_GUEST_ID_LO)
+
+#define HV_CPU_POWER_MANAGEMENT (1 << 0)
+#define HV_RECOMMENDATIONS_MAX 4
+
+#define HV_X64_MAX 5
+#define HV_CAPS_MAX 8
+
+
+#define HV_HYPERCALL_PARAM_ALIGN sizeof(u64)
+
+
+/* Service definitions */
+
+#define HV_SERVICE_PARENT_PORT (0)
+#define HV_SERVICE_PARENT_CONNECTION (0)
+
+#define HV_SERVICE_CONNECT_RESPONSE_SUCCESS (0)
+#define HV_SERVICE_CONNECT_RESPONSE_INVALID_PARAMETER (1)
+#define HV_SERVICE_CONNECT_RESPONSE_UNKNOWN_SERVICE (2)
+#define HV_SERVICE_CONNECT_RESPONSE_CONNECTION_REJECTED (3)
+
+#define HV_SERVICE_CONNECT_REQUEST_MESSAGE_ID (1)
+#define HV_SERVICE_CONNECT_RESPONSE_MESSAGE_ID (2)
+#define HV_SERVICE_DISCONNECT_REQUEST_MESSAGE_ID (3)
+#define HV_SERVICE_DISCONNECT_RESPONSE_MESSAGE_ID (4)
+#define HV_SERVICE_MAX_MESSAGE_ID (4)
+
+#define HV_SERVICE_PROTOCOL_VERSION (0x0010)
+#define HV_CONNECT_PAYLOAD_BYTE_COUNT 64
+
+/* #define VMBUS_REVISION_NUMBER 6 */
+
+/* Our local vmbus's port and connection id. Anything >0 is fine */
+/* #define VMBUS_PORT_ID 11 */
+
+/* 628180B8-308D-4c5e-B7DB-1BEB62E62EF4 */
+static const struct hv_guid VMBUS_SERVICE_ID = {
+ .data = {
+ 0xb8, 0x80, 0x81, 0x62, 0x8d, 0x30, 0x5e, 0x4c,
+ 0xb7, 0xdb, 0x1b, 0xeb, 0x62, 0xe6, 0x2e, 0xf4
+ },
+};
+
+#define MAX_NUM_CPUS 32
+
+
+struct hv_input_signal_event_buffer {
+ u64 align8;
+ struct hv_input_signal_event event;
+};
+
+struct hv_context {
+ /* We only support running on top of Hyper-V
+ * So at this point this really can only contain the Hyper-V ID
+ */
+ u64 guestid;
+
+ void *hypercall_page;
+
+ bool synic_initialized;
+
+ /*
+ * This is used as an input param to HvCallSignalEvent hypercall. The
+ * input param is immutable in our usage and must be dynamic mem (vs
+ * stack or global). */
+ struct hv_input_signal_event_buffer *signal_event_buffer;
+ /* 8-bytes aligned of the buffer above */
+ struct hv_input_signal_event *signal_event_param;
+
+ void *synic_message_page[MAX_NUM_CPUS];
+ void *synic_event_page[MAX_NUM_CPUS];
+};
+
+extern struct hv_context hv_context;
+
+
+/* Hv Interface */
+
+extern int hv_init(void);
+
+extern void hv_cleanup(void);
+
+extern u16 hv_post_message(union hv_connection_id connection_id,
+ enum hv_message_type message_type,
+ void *payload, size_t payload_size);
+
+extern u16 hv_signal_event(void);
+
+extern void hv_synic_init(void *irqarg);
+
+extern void hv_synic_cleanup(void *arg);
+
+
+/* Interface */
+
+
+int hv_ringbuffer_init(struct hv_ring_buffer_info *ring_info, void *buffer,
+ u32 buflen);
+
+void hv_ringbuffer_cleanup(struct hv_ring_buffer_info *ring_info);
+
+int hv_ringbuffer_write(struct hv_ring_buffer_info *ring_info,
+ struct scatterlist *sglist,
+ u32 sgcount);
+
+int hv_ringbuffer_peek(struct hv_ring_buffer_info *ring_info, void *buffer,
+ u32 buflen);
+
+int hv_ringbuffer_read(struct hv_ring_buffer_info *ring_info,
+ void *buffer,
+ u32 buflen,
+ u32 offset);
+
+u32 hv_get_ringbuffer_interrupt_mask(struct hv_ring_buffer_info *ring_info);
+
+void hv_dump_ring_info(struct hv_ring_buffer_info *ring_info, char *prefix);
+
+void hv_ringbuffer_get_debuginfo(struct hv_ring_buffer_info *ring_info,
+ struct hv_ring_buffer_debug_info *debug_info);
+
+/*
+ * Maximum channels is determined by the size of the interrupt page
+ * which is PAGE_SIZE. 1/2 of PAGE_SIZE is for send endpoint interrupt
+ * and the other is receive endpoint interrupt
+ */
+#define MAX_NUM_CHANNELS ((PAGE_SIZE >> 1) << 3) /* 16348 channels */
+
+/* The value here must be in multiple of 32 */
+/* TODO: Need to make this configurable */
+#define MAX_NUM_CHANNELS_SUPPORTED 256
+
+
+enum vmbus_connect_state {
+ DISCONNECTED,
+ CONNECTING,
+ CONNECTED,
+ DISCONNECTING
+};
+
+#define MAX_SIZE_CHANNEL_MESSAGE HV_MESSAGE_PAYLOAD_BYTE_COUNT
+
+struct vmbus_connection {
+ enum vmbus_connect_state conn_state;
+
+ atomic_t next_gpadl_handle;
+
+ /*
+ * Represents channel interrupts. Each bit position represents a
+ * channel. When a channel sends an interrupt via VMBUS, it finds its
+ * bit in the sendInterruptPage, set it and calls Hv to generate a port
+ * event. The other end receives the port event and parse the
+ * recvInterruptPage to see which bit is set
+ */
+ void *int_page;
+ void *send_int_page;
+ void *recv_int_page;
+
+ /*
+ * 2 pages - 1st page for parent->child notification and 2nd
+ * is child->parent notification
+ */
+ void *monitor_pages;
+ struct list_head chn_msg_list;
+ spinlock_t channelmsg_lock;
+
+ /* List of channels */
+ struct list_head chn_list;
+ spinlock_t channel_lock;
+
+ struct workqueue_struct *work_queue;
+};
+
+
+struct vmbus_msginfo {
+ /* Bookkeeping stuff */
+ struct list_head msglist_entry;
+
+ /* The message itself */
+ unsigned char msg[0];
+};
+
+
+extern struct vmbus_connection vmbus_connection;
+
+/* General vmbus interface */
+
+struct hv_device *vmbus_child_device_create(struct hv_guid *type,
+ struct hv_guid *instance,
+ struct vmbus_channel *channel);
+
+int vmbus_child_device_register(struct hv_device *child_device_obj);
+void vmbus_child_device_unregister(struct hv_device *device_obj);
+
+/* static void */
+/* VmbusChildDeviceDestroy( */
+/* struct hv_device *); */
+
+struct vmbus_channel *relid2channel(u32 relid);
+
+
+/* Connection interface */
+
+int vmbus_connect(void);
+
+int vmbus_disconnect(void);
+
+int vmbus_post_msg(void *buffer, size_t buflen);
+
+int vmbus_set_event(u32 child_relid);
+
+void vmbus_on_event(unsigned long data);
+
+
+#endif /* _HYPERV_VMBUS_H */
diff --git a/drivers/staging/hv/logging.h b/drivers/staging/hv/logging.h
deleted file mode 100644
index 1799951..0000000
--- a/drivers/staging/hv/logging.h
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- *
- * Copyright (c) 2009, Microsoft Corporation.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
- * Place - Suite 330, Boston, MA 02111-1307 USA.
- *
- * Authors:
- * Haiyang Zhang <haiyangz@microsoft.com>
- * Hank Janssen <hjanssen@microsoft.com>
- *
- */
-
-
-#ifndef _LOGGING_H_
-#define _LOGGING_H_
-
-#define LOWORD(dw) ((unsigned short)(dw))
-#define HIWORD(dw) ((unsigned short)(((unsigned int) (dw) >> 16) & 0xFFFF))
-
-/* #include <linux/init.h> */
-/* #include <linux/module.h> */
-
-
-#define VMBUS 0x0001
-#define STORVSC 0x0002
-#define NETVSC 0x0004
-#define INPUTVSC 0x0008
-#define BLKVSC 0x0010
-#define VMBUS_DRV 0x0100
-#define STORVSC_DRV 0x0200
-#define NETVSC_DRV 0x0400
-#define INPUTVSC_DRV 0x0800
-#define BLKVSC_DRV 0x1000
-
-#define ALL_MODULES (VMBUS |\
- STORVSC |\
- NETVSC |\
- INPUTVSC |\
- BLKVSC |\
- VMBUS_DRV |\
- STORVSC_DRV |\
- NETVSC_DRV |\
- INPUTVSC_DRV|\
- BLKVSC_DRV)
-
-/* Logging Level */
-#define ERROR_LVL 3
-#define WARNING_LVL 4
-#define INFO_LVL 6
-#define DEBUG_LVL 7
-#define DEBUG_LVL_ENTEREXIT 8
-#define DEBUG_RING_LVL 9
-
-extern unsigned int vmbus_loglevel;
-
-#define DPRINT(mod, lvl, fmt, args...) do {\
- if ((mod & (HIWORD(vmbus_loglevel))) && \
- (lvl <= LOWORD(vmbus_loglevel))) \
- printk(KERN_DEBUG #mod": %s() " fmt "\n", __func__, ## args);\
- } while (0)
-
-#define DPRINT_DBG(mod, fmt, args...) do {\
- if ((mod & (HIWORD(vmbus_loglevel))) && \
- (DEBUG_LVL <= LOWORD(vmbus_loglevel))) \
- printk(KERN_DEBUG #mod": %s() " fmt "\n", __func__, ## args);\
- } while (0)
-
-#define DPRINT_INFO(mod, fmt, args...) do {\
- if ((mod & (HIWORD(vmbus_loglevel))) && \
- (INFO_LVL <= LOWORD(vmbus_loglevel))) \
- printk(KERN_INFO #mod": " fmt "\n", ## args);\
- } while (0)
-
-#define DPRINT_WARN(mod, fmt, args...) do {\
- if ((mod & (HIWORD(vmbus_loglevel))) && \
- (WARNING_LVL <= LOWORD(vmbus_loglevel))) \
- printk(KERN_WARNING #mod": WARNING! " fmt "\n", ## args);\
- } while (0)
-
-#define DPRINT_ERR(mod, fmt, args...) do {\
- if ((mod & (HIWORD(vmbus_loglevel))) && \
- (ERROR_LVL <= LOWORD(vmbus_loglevel))) \
- printk(KERN_ERR #mod": %s() ERROR!! " fmt "\n", \
- __func__, ## args);\
- } while (0)
-
-#endif /* _LOGGING_H_ */
diff --git a/drivers/staging/hv/netvsc.c b/drivers/staging/hv/netvsc.c
index 20b15977..41cbb26 100644
--- a/drivers/staging/hv/netvsc.c
+++ b/drivers/staging/hv/netvsc.c
@@ -18,6 +18,8 @@
* Haiyang Zhang <haiyangz@microsoft.com>
* Hank Janssen <hjanssen@microsoft.com>
*/
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
#include <linux/kernel.h>
#include <linux/sched.h>
#include <linux/wait.h>
@@ -25,11 +27,9 @@
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/slab.h>
-#include "hv_api.h"
-#include "logging.h"
-#include "netvsc.h"
-#include "rndis_filter.h"
-#include "channel.h"
+
+#include "hyperv.h"
+#include "hyperv_net.h"
/* Globals */
@@ -43,38 +43,6 @@
}
};
-static int netvsc_device_add(struct hv_device *device, void *additional_info);
-
-static int netvsc_device_remove(struct hv_device *device);
-
-static void netvsc_cleanup(struct hv_driver *driver);
-
-static void netvsc_channel_cb(void *context);
-
-static int netvsc_init_send_buf(struct hv_device *device);
-
-static int netvsc_init_recv_buf(struct hv_device *device);
-
-static int netvsc_destroy_send_buf(struct netvsc_device *net_device);
-
-static int netvsc_destroy_recv_buf(struct netvsc_device *net_device);
-
-static int netvsc_connect_vsp(struct hv_device *device);
-
-static void netvsc_send_completion(struct hv_device *device,
- struct vmpacket_descriptor *packet);
-
-static int netvsc_send(struct hv_device *device,
- struct hv_netvsc_packet *packet);
-
-static void netvsc_receive(struct hv_device *device,
- struct vmpacket_descriptor *packet);
-
-static void netvsc_receive_completion(void *context);
-
-static void netvsc_send_recv_completion(struct hv_device *device,
- u64 transaction_id);
-
static struct netvsc_device *alloc_net_device(struct hv_device *device)
{
@@ -171,43 +139,85 @@
return net_device;
}
-/*
- * netvsc_initialize - Main entry point
- */
-int netvsc_initialize(struct hv_driver *drv)
+static int netvsc_destroy_recv_buf(struct netvsc_device *net_device)
{
- struct netvsc_driver *driver = (struct netvsc_driver *)drv;
+ struct nvsp_message *revoke_packet;
+ int ret = 0;
- DPRINT_DBG(NETVSC, "sizeof(struct hv_netvsc_packet)=%zd, "
- "sizeof(struct nvsp_message)=%zd, "
- "sizeof(struct vmtransfer_page_packet_header)=%zd",
- sizeof(struct hv_netvsc_packet),
- sizeof(struct nvsp_message),
- sizeof(struct vmtransfer_page_packet_header));
+ /*
+ * If we got a section count, it means we received a
+ * SendReceiveBufferComplete msg (ie sent
+ * NvspMessage1TypeSendReceiveBuffer msg) therefore, we need
+ * to send a revoke msg here
+ */
+ if (net_device->recv_section_cnt) {
+ /* Send the revoke receive buffer */
+ revoke_packet = &net_device->revoke_packet;
+ memset(revoke_packet, 0, sizeof(struct nvsp_message));
- drv->name = driver_name;
- memcpy(&drv->dev_type, &netvsc_device_type, sizeof(struct hv_guid));
+ revoke_packet->hdr.msg_type =
+ NVSP_MSG1_TYPE_REVOKE_RECV_BUF;
+ revoke_packet->msg.v1_msg.
+ revoke_recv_buf.id = NETVSC_RECEIVE_BUFFER_ID;
- /* Setup the dispatch table */
- driver->base.dev_add = netvsc_device_add;
- driver->base.dev_rm = netvsc_device_remove;
- driver->base.cleanup = netvsc_cleanup;
+ ret = vmbus_sendpacket(net_device->dev->channel,
+ revoke_packet,
+ sizeof(struct nvsp_message),
+ (unsigned long)revoke_packet,
+ VM_PKT_DATA_INBAND, 0);
+ /*
+ * If we failed here, we might as well return and
+ * have a leak rather than continue and a bugchk
+ */
+ if (ret != 0) {
+ dev_err(&net_device->dev->device, "unable to send "
+ "revoke receive buffer to netvsp");
+ return -1;
+ }
+ }
- driver->send = netvsc_send;
+ /* Teardown the gpadl on the vsp end */
+ if (net_device->recv_buf_gpadl_handle) {
+ ret = vmbus_teardown_gpadl(net_device->dev->channel,
+ net_device->recv_buf_gpadl_handle);
- rndis_filter_init(driver);
- return 0;
+ /* If we failed here, we might as well return and have a leak
+ * rather than continue and a bugchk
+ */
+ if (ret != 0) {
+ dev_err(&net_device->dev->device,
+ "unable to teardown receive buffer's gpadl");
+ return -1;
+ }
+ net_device->recv_buf_gpadl_handle = 0;
+ }
+
+ if (net_device->recv_buf) {
+ /* Free up the receive buffer */
+ free_pages((unsigned long)net_device->recv_buf,
+ get_order(net_device->recv_buf_size));
+ net_device->recv_buf = NULL;
+ }
+
+ if (net_device->recv_section) {
+ net_device->recv_section_cnt = 0;
+ kfree(net_device->recv_section);
+ net_device->recv_section = NULL;
+ }
+
+ return ret;
}
static int netvsc_init_recv_buf(struct hv_device *device)
{
int ret = 0;
+ int t;
struct netvsc_device *net_device;
struct nvsp_message *init_packet;
net_device = get_outbound_net_device(device);
if (!net_device) {
- DPRINT_ERR(NETVSC, "unable to get net device..."
+ dev_err(&device->device, "unable to get net device..."
"device being destroyed?");
return -1;
}
@@ -216,15 +226,12 @@
(void *)__get_free_pages(GFP_KERNEL|__GFP_ZERO,
get_order(net_device->recv_buf_size));
if (!net_device->recv_buf) {
- DPRINT_ERR(NETVSC,
- "unable to allocate receive buffer of size %d",
- net_device->recv_buf_size);
+ dev_err(&device->device, "unable to allocate receive "
+ "buffer of size %d", net_device->recv_buf_size);
ret = -1;
goto cleanup;
}
- DPRINT_INFO(NETVSC, "Establishing receive buffer's GPADL...");
-
/*
* Establish the gpadl handle for this buffer on this
* channel. Note: This call uses the vmbus connection rather
@@ -234,15 +241,13 @@
net_device->recv_buf_size,
&net_device->recv_buf_gpadl_handle);
if (ret != 0) {
- DPRINT_ERR(NETVSC,
- "unable to establish receive buffer's gpadl");
+ dev_err(&device->device,
+ "unable to establish receive buffer's gpadl");
goto cleanup;
}
/* Notify the NetVsp of the gpadl handle */
- DPRINT_INFO(NETVSC, "Sending NvspMessage1TypeSendReceiveBuffer...");
-
init_packet = &net_device->channel_init_pkt;
memset(init_packet, 0, sizeof(struct nvsp_message));
@@ -254,28 +259,25 @@
send_recv_buf.id = NETVSC_RECEIVE_BUFFER_ID;
/* Send the gpadl notification request */
- net_device->wait_condition = 0;
ret = vmbus_sendpacket(device->channel, init_packet,
sizeof(struct nvsp_message),
(unsigned long)init_packet,
VM_PKT_DATA_INBAND,
VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED);
if (ret != 0) {
- DPRINT_ERR(NETVSC,
- "unable to send receive buffer's gpadl to netvsp");
+ dev_err(&device->device,
+ "unable to send receive buffer's gpadl to netvsp");
goto cleanup;
}
- wait_event_timeout(net_device->channel_init_wait,
- net_device->wait_condition,
- msecs_to_jiffies(1000));
- BUG_ON(net_device->wait_condition == 0);
+ t = wait_for_completion_timeout(&net_device->channel_init_wait, HZ);
+ BUG_ON(t == 0);
/* Check the response */
if (init_packet->msg.v1_msg.
send_recv_buf_complete.status != NVSP_STAT_SUCCESS) {
- DPRINT_ERR(NETVSC, "Unable to complete receive buffer "
+ dev_err(&device->device, "Unable to complete receive buffer "
"initialzation with NetVsp - status %d",
init_packet->msg.v1_msg.
send_recv_buf_complete.status);
@@ -301,14 +303,6 @@
net_device->recv_section_cnt *
sizeof(struct nvsp_1_receive_buffer_section));
- DPRINT_INFO(NETVSC, "Receive sections info (count %d, offset %d, "
- "endoffset %d, suballoc size %d, num suballocs %d)",
- net_device->recv_section_cnt,
- net_device->recv_section[0].offset,
- net_device->recv_section[0].end_offset,
- net_device->recv_section[0].sub_alloc_size,
- net_device->recv_section[0].num_sub_allocs);
-
/*
* For 1st release, there should only be 1 section that represents the
* entire receive buffer
@@ -329,15 +323,80 @@
return ret;
}
+static int netvsc_destroy_send_buf(struct netvsc_device *net_device)
+{
+ struct nvsp_message *revoke_packet;
+ int ret = 0;
+
+ /*
+ * If we got a section count, it means we received a
+ * SendReceiveBufferComplete msg (ie sent
+ * NvspMessage1TypeSendReceiveBuffer msg) therefore, we need
+ * to send a revoke msg here
+ */
+ if (net_device->send_section_size) {
+ /* Send the revoke send buffer */
+ revoke_packet = &net_device->revoke_packet;
+ memset(revoke_packet, 0, sizeof(struct nvsp_message));
+
+ revoke_packet->hdr.msg_type =
+ NVSP_MSG1_TYPE_REVOKE_SEND_BUF;
+ revoke_packet->msg.v1_msg.
+ revoke_send_buf.id = NETVSC_SEND_BUFFER_ID;
+
+ ret = vmbus_sendpacket(net_device->dev->channel,
+ revoke_packet,
+ sizeof(struct nvsp_message),
+ (unsigned long)revoke_packet,
+ VM_PKT_DATA_INBAND, 0);
+ /*
+ * If we failed here, we might as well return and have a leak
+ * rather than continue and a bugchk
+ */
+ if (ret != 0) {
+ dev_err(&net_device->dev->device, "unable to send "
+ "revoke send buffer to netvsp");
+ return -1;
+ }
+ }
+
+ /* Teardown the gpadl on the vsp end */
+ if (net_device->send_buf_gpadl_handle) {
+ ret = vmbus_teardown_gpadl(net_device->dev->channel,
+ net_device->send_buf_gpadl_handle);
+
+ /*
+ * If we failed here, we might as well return and have a leak
+ * rather than continue and a bugchk
+ */
+ if (ret != 0) {
+ dev_err(&net_device->dev->device,
+ "unable to teardown send buffer's gpadl");
+ return -1;
+ }
+ net_device->send_buf_gpadl_handle = 0;
+ }
+
+ if (net_device->send_buf) {
+ /* Free up the receive buffer */
+ free_pages((unsigned long)net_device->send_buf,
+ get_order(net_device->send_buf_size));
+ net_device->send_buf = NULL;
+ }
+
+ return ret;
+}
+
static int netvsc_init_send_buf(struct hv_device *device)
{
int ret = 0;
+ int t;
struct netvsc_device *net_device;
struct nvsp_message *init_packet;
net_device = get_outbound_net_device(device);
if (!net_device) {
- DPRINT_ERR(NETVSC, "unable to get net device..."
+ dev_err(&device->device, "unable to get net device..."
"device being destroyed?");
return -1;
}
@@ -350,14 +409,12 @@
(void *)__get_free_pages(GFP_KERNEL|__GFP_ZERO,
get_order(net_device->send_buf_size));
if (!net_device->send_buf) {
- DPRINT_ERR(NETVSC, "unable to allocate send buffer of size %d",
- net_device->send_buf_size);
+ dev_err(&device->device, "unable to allocate send "
+ "buffer of size %d", net_device->send_buf_size);
ret = -1;
goto cleanup;
}
- DPRINT_INFO(NETVSC, "Establishing send buffer's GPADL...");
-
/*
* Establish the gpadl handle for this buffer on this
* channel. Note: This call uses the vmbus connection rather
@@ -367,13 +424,11 @@
net_device->send_buf_size,
&net_device->send_buf_gpadl_handle);
if (ret != 0) {
- DPRINT_ERR(NETVSC, "unable to establish send buffer's gpadl");
+ dev_err(&device->device, "unable to establish send buffer's gpadl");
goto cleanup;
}
/* Notify the NetVsp of the gpadl handle */
- DPRINT_INFO(NETVSC, "Sending NvspMessage1TypeSendSendBuffer...");
-
init_packet = &net_device->channel_init_pkt;
memset(init_packet, 0, sizeof(struct nvsp_message));
@@ -385,27 +440,25 @@
NETVSC_SEND_BUFFER_ID;
/* Send the gpadl notification request */
- net_device->wait_condition = 0;
ret = vmbus_sendpacket(device->channel, init_packet,
sizeof(struct nvsp_message),
(unsigned long)init_packet,
VM_PKT_DATA_INBAND,
VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED);
if (ret != 0) {
- DPRINT_ERR(NETVSC,
+ dev_err(&device->device,
"unable to send receive buffer's gpadl to netvsp");
goto cleanup;
}
- wait_event_timeout(net_device->channel_init_wait,
- net_device->wait_condition,
- msecs_to_jiffies(1000));
- BUG_ON(net_device->wait_condition == 0);
+ t = wait_for_completion_timeout(&net_device->channel_init_wait, HZ);
+
+ BUG_ON(t == 0);
/* Check the response */
if (init_packet->msg.v1_msg.
send_send_buf_complete.status != NVSP_STAT_SUCCESS) {
- DPRINT_ERR(NETVSC, "Unable to complete send buffer "
+ dev_err(&device->device, "Unable to complete send buffer "
"initialzation with NetVsp - status %d",
init_packet->msg.v1_msg.
send_send_buf_complete.status);
@@ -426,161 +479,17 @@
return ret;
}
-static int netvsc_destroy_recv_buf(struct netvsc_device *net_device)
-{
- struct nvsp_message *revoke_packet;
- int ret = 0;
-
- /*
- * If we got a section count, it means we received a
- * SendReceiveBufferComplete msg (ie sent
- * NvspMessage1TypeSendReceiveBuffer msg) therefore, we need
- * to send a revoke msg here
- */
- if (net_device->recv_section_cnt) {
- DPRINT_INFO(NETVSC,
- "Sending NvspMessage1TypeRevokeReceiveBuffer...");
-
- /* Send the revoke receive buffer */
- revoke_packet = &net_device->revoke_packet;
- memset(revoke_packet, 0, sizeof(struct nvsp_message));
-
- revoke_packet->hdr.msg_type =
- NVSP_MSG1_TYPE_REVOKE_RECV_BUF;
- revoke_packet->msg.v1_msg.
- revoke_recv_buf.id = NETVSC_RECEIVE_BUFFER_ID;
-
- ret = vmbus_sendpacket(net_device->dev->channel,
- revoke_packet,
- sizeof(struct nvsp_message),
- (unsigned long)revoke_packet,
- VM_PKT_DATA_INBAND, 0);
- /*
- * If we failed here, we might as well return and
- * have a leak rather than continue and a bugchk
- */
- if (ret != 0) {
- DPRINT_ERR(NETVSC, "unable to send revoke receive "
- "buffer to netvsp");
- return -1;
- }
- }
-
- /* Teardown the gpadl on the vsp end */
- if (net_device->recv_buf_gpadl_handle) {
- DPRINT_INFO(NETVSC, "Tearing down receive buffer's GPADL...");
-
- ret = vmbus_teardown_gpadl(net_device->dev->channel,
- net_device->recv_buf_gpadl_handle);
-
- /* If we failed here, we might as well return and have a leak rather than continue and a bugchk */
- if (ret != 0) {
- DPRINT_ERR(NETVSC,
- "unable to teardown receive buffer's gpadl");
- return -1;
- }
- net_device->recv_buf_gpadl_handle = 0;
- }
-
- if (net_device->recv_buf) {
- DPRINT_INFO(NETVSC, "Freeing up receive buffer...");
-
- /* Free up the receive buffer */
- free_pages((unsigned long)net_device->recv_buf,
- get_order(net_device->recv_buf_size));
- net_device->recv_buf = NULL;
- }
-
- if (net_device->recv_section) {
- net_device->recv_section_cnt = 0;
- kfree(net_device->recv_section);
- net_device->recv_section = NULL;
- }
-
- return ret;
-}
-
-static int netvsc_destroy_send_buf(struct netvsc_device *net_device)
-{
- struct nvsp_message *revoke_packet;
- int ret = 0;
-
- /*
- * If we got a section count, it means we received a
- * SendReceiveBufferComplete msg (ie sent
- * NvspMessage1TypeSendReceiveBuffer msg) therefore, we need
- * to send a revoke msg here
- */
- if (net_device->send_section_size) {
- DPRINT_INFO(NETVSC,
- "Sending NvspMessage1TypeRevokeSendBuffer...");
-
- /* Send the revoke send buffer */
- revoke_packet = &net_device->revoke_packet;
- memset(revoke_packet, 0, sizeof(struct nvsp_message));
-
- revoke_packet->hdr.msg_type =
- NVSP_MSG1_TYPE_REVOKE_SEND_BUF;
- revoke_packet->msg.v1_msg.
- revoke_send_buf.id = NETVSC_SEND_BUFFER_ID;
-
- ret = vmbus_sendpacket(net_device->dev->channel,
- revoke_packet,
- sizeof(struct nvsp_message),
- (unsigned long)revoke_packet,
- VM_PKT_DATA_INBAND, 0);
- /*
- * If we failed here, we might as well return and have a leak
- * rather than continue and a bugchk
- */
- if (ret != 0) {
- DPRINT_ERR(NETVSC, "unable to send revoke send buffer "
- "to netvsp");
- return -1;
- }
- }
-
- /* Teardown the gpadl on the vsp end */
- if (net_device->send_buf_gpadl_handle) {
- DPRINT_INFO(NETVSC, "Tearing down send buffer's GPADL...");
- ret = vmbus_teardown_gpadl(net_device->dev->channel,
- net_device->send_buf_gpadl_handle);
-
- /*
- * If we failed here, we might as well return and have a leak
- * rather than continue and a bugchk
- */
- if (ret != 0) {
- DPRINT_ERR(NETVSC, "unable to teardown send buffer's "
- "gpadl");
- return -1;
- }
- net_device->send_buf_gpadl_handle = 0;
- }
-
- if (net_device->send_buf) {
- DPRINT_INFO(NETVSC, "Freeing up send buffer...");
-
- /* Free up the receive buffer */
- free_pages((unsigned long)net_device->send_buf,
- get_order(net_device->send_buf_size));
- net_device->send_buf = NULL;
- }
-
- return ret;
-}
-
static int netvsc_connect_vsp(struct hv_device *device)
{
- int ret;
+ int ret, t;
struct netvsc_device *net_device;
struct nvsp_message *init_packet;
int ndis_version;
net_device = get_outbound_net_device(device);
if (!net_device) {
- DPRINT_ERR(NETVSC, "unable to get net device..."
+ dev_err(&device->device, "unable to get net device..."
"device being destroyed?");
return -1;
}
@@ -594,54 +503,34 @@
init_packet->msg.init_msg.init.max_protocol_ver =
NVSP_MAX_PROTOCOL_VERSION;
- DPRINT_INFO(NETVSC, "Sending NvspMessageTypeInit...");
-
/* Send the init request */
- net_device->wait_condition = 0;
ret = vmbus_sendpacket(device->channel, init_packet,
sizeof(struct nvsp_message),
(unsigned long)init_packet,
VM_PKT_DATA_INBAND,
VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED);
- if (ret != 0) {
- DPRINT_ERR(NETVSC, "unable to send NvspMessageTypeInit");
+ if (ret != 0)
goto cleanup;
- }
- wait_event_timeout(net_device->channel_init_wait,
- net_device->wait_condition,
- msecs_to_jiffies(1000));
- if (net_device->wait_condition == 0) {
+ t = wait_for_completion_timeout(&net_device->channel_init_wait, HZ);
+
+ if (t == 0) {
ret = -ETIMEDOUT;
goto cleanup;
}
- DPRINT_INFO(NETVSC, "NvspMessageTypeInit status(%d) max mdl chain (%d)",
- init_packet->msg.init_msg.init_complete.status,
- init_packet->msg.init_msg.
- init_complete.max_mdl_chain_len);
-
if (init_packet->msg.init_msg.init_complete.status !=
NVSP_STAT_SUCCESS) {
- DPRINT_ERR(NETVSC,
- "unable to initialize with netvsp (status 0x%x)",
- init_packet->msg.init_msg.init_complete.status);
ret = -1;
goto cleanup;
}
if (init_packet->msg.init_msg.init_complete.
negotiated_protocol_ver != NVSP_PROTOCOL_VERSION_1) {
- DPRINT_ERR(NETVSC, "unable to initialize with netvsp "
- "(version expected 1 got %d)",
- init_packet->msg.init_msg.
- init_complete.negotiated_protocol_ver);
ret = -1;
goto cleanup;
}
- DPRINT_INFO(NETVSC, "Sending NvspMessage1TypeSendNdisVersion...");
-
/* Send the ndis version */
memset(init_packet, 0, sizeof(struct nvsp_message));
@@ -661,8 +550,6 @@
(unsigned long)init_packet,
VM_PKT_DATA_INBAND, 0);
if (ret != 0) {
- DPRINT_ERR(NETVSC,
- "unable to send NvspMessage1TypeSendNdisVersion");
ret = -1;
goto cleanup;
}
@@ -677,143 +564,42 @@
return ret;
}
-static void NetVscDisconnectFromVsp(struct netvsc_device *net_device)
+static void netvsc_disconnect_vsp(struct netvsc_device *net_device)
{
netvsc_destroy_recv_buf(net_device);
netvsc_destroy_send_buf(net_device);
}
/*
- * netvsc_device_add - Callback when the device belonging to this
- * driver is added
- */
-static int netvsc_device_add(struct hv_device *device, void *additional_info)
-{
- int ret = 0;
- int i;
- struct netvsc_device *net_device;
- struct hv_netvsc_packet *packet, *pos;
- struct netvsc_driver *net_driver =
- (struct netvsc_driver *)device->drv;
-
- net_device = alloc_net_device(device);
- if (!net_device) {
- ret = -1;
- goto cleanup;
- }
-
- DPRINT_DBG(NETVSC, "netvsc channel object allocated - %p", net_device);
-
- /* Initialize the NetVSC channel extension */
- net_device->recv_buf_size = NETVSC_RECEIVE_BUFFER_SIZE;
- spin_lock_init(&net_device->recv_pkt_list_lock);
-
- net_device->send_buf_size = NETVSC_SEND_BUFFER_SIZE;
-
- INIT_LIST_HEAD(&net_device->recv_pkt_list);
-
- for (i = 0; i < NETVSC_RECEIVE_PACKETLIST_COUNT; i++) {
- packet = kzalloc(sizeof(struct hv_netvsc_packet) +
- (NETVSC_RECEIVE_SG_COUNT *
- sizeof(struct hv_page_buffer)), GFP_KERNEL);
- if (!packet) {
- DPRINT_DBG(NETVSC, "unable to allocate netvsc pkts "
- "for receive pool (wanted %d got %d)",
- NETVSC_RECEIVE_PACKETLIST_COUNT, i);
- break;
- }
- list_add_tail(&packet->list_ent,
- &net_device->recv_pkt_list);
- }
- init_waitqueue_head(&net_device->channel_init_wait);
-
- /* Open the channel */
- ret = vmbus_open(device->channel, net_driver->ring_buf_size,
- net_driver->ring_buf_size, NULL, 0,
- netvsc_channel_cb, device);
-
- if (ret != 0) {
- DPRINT_ERR(NETVSC, "unable to open channel: %d", ret);
- ret = -1;
- goto cleanup;
- }
-
- /* Channel is opened */
- DPRINT_INFO(NETVSC, "*** NetVSC channel opened successfully! ***");
-
- /* Connect with the NetVsp */
- ret = netvsc_connect_vsp(device);
- if (ret != 0) {
- DPRINT_ERR(NETVSC, "unable to connect to NetVSP - %d", ret);
- ret = -1;
- goto close;
- }
-
- DPRINT_INFO(NETVSC, "*** NetVSC channel handshake result - %d ***",
- ret);
-
- return ret;
-
-close:
- /* Now, we can close the channel safely */
- vmbus_close(device->channel);
-
-cleanup:
-
- if (net_device) {
- list_for_each_entry_safe(packet, pos,
- &net_device->recv_pkt_list,
- list_ent) {
- list_del(&packet->list_ent);
- kfree(packet);
- }
-
- release_outbound_net_device(device);
- release_inbound_net_device(device);
-
- free_net_device(net_device);
- }
-
- return ret;
-}
-
-/*
* netvsc_device_remove - Callback when the root bus device is removed
*/
-static int netvsc_device_remove(struct hv_device *device)
+int netvsc_device_remove(struct hv_device *device)
{
struct netvsc_device *net_device;
struct hv_netvsc_packet *netvsc_packet, *pos;
- DPRINT_INFO(NETVSC, "Disabling outbound traffic on net device (%p)...",
- device->ext);
-
/* Stop outbound traffic ie sends and receives completions */
net_device = release_outbound_net_device(device);
if (!net_device) {
- DPRINT_ERR(NETVSC, "No net device present!!");
+ dev_err(&device->device, "No net device present!!");
return -1;
}
/* Wait for all send completions */
while (atomic_read(&net_device->num_outstanding_sends)) {
- DPRINT_INFO(NETVSC, "waiting for %d requests to complete...",
- atomic_read(&net_device->num_outstanding_sends));
+ dev_err(&device->device,
+ "waiting for %d requests to complete...",
+ atomic_read(&net_device->num_outstanding_sends));
udelay(100);
}
- DPRINT_INFO(NETVSC, "Disconnecting from netvsp...");
-
- NetVscDisconnectFromVsp(net_device);
-
- DPRINT_INFO(NETVSC, "Disabling inbound traffic on net device (%p)...",
- device->ext);
+ netvsc_disconnect_vsp(net_device);
/* Stop inbound traffic ie receives and sends completions */
net_device = release_inbound_net_device(device);
/* At this point, no one should be accessing netDevice except in here */
- DPRINT_INFO(NETVSC, "net device (%p) safe to remove", net_device);
+ dev_notice(&device->device, "net device safe to remove");
/* Now, we can close the channel safely */
vmbus_close(device->channel);
@@ -829,13 +615,6 @@
return 0;
}
-/*
- * netvsc_cleanup - Perform any cleanup when the driver is removed
- */
-static void netvsc_cleanup(struct hv_driver *drv)
-{
-}
-
static void netvsc_send_completion(struct hv_device *device,
struct vmpacket_descriptor *packet)
{
@@ -845,7 +624,7 @@
net_device = get_inbound_net_device(device);
if (!net_device) {
- DPRINT_ERR(NETVSC, "unable to get net device..."
+ dev_err(&device->device, "unable to get net device..."
"device being destroyed?");
return;
}
@@ -853,9 +632,6 @@
nvsp_packet = (struct nvsp_message *)((unsigned long)packet +
(packet->offset8 << 3));
- DPRINT_DBG(NETVSC, "send completion packet - type %d",
- nvsp_packet->hdr.msg_type);
-
if ((nvsp_packet->hdr.msg_type == NVSP_MSG_TYPE_INIT_COMPLETE) ||
(nvsp_packet->hdr.msg_type ==
NVSP_MSG1_TYPE_SEND_RECV_BUF_COMPLETE) ||
@@ -864,8 +640,7 @@
/* Copy the response back */
memcpy(&net_device->channel_init_pkt, nvsp_packet,
sizeof(struct nvsp_message));
- net_device->wait_condition = 1;
- wake_up(&net_device->channel_init_wait);
+ complete(&net_device->channel_init_wait);
} else if (nvsp_packet->hdr.msg_type ==
NVSP_MSG1_TYPE_SEND_RNDIS_PKT_COMPLETE) {
/* Get the send context */
@@ -878,14 +653,14 @@
atomic_dec(&net_device->num_outstanding_sends);
} else {
- DPRINT_ERR(NETVSC, "Unknown send completion packet type - "
+ dev_err(&device->device, "Unknown send completion packet type- "
"%d received!!", nvsp_packet->hdr.msg_type);
}
put_net_device(device);
}
-static int netvsc_send(struct hv_device *device,
+int netvsc_send(struct hv_device *device,
struct hv_netvsc_packet *packet)
{
struct netvsc_device *net_device;
@@ -895,7 +670,7 @@
net_device = get_outbound_net_device(device);
if (!net_device) {
- DPRINT_ERR(NETVSC, "net device (%p) shutting down..."
+ dev_err(&device->device, "net device (%p) shutting down..."
"ignoring outbound packets", net_device);
return -2;
}
@@ -931,7 +706,7 @@
}
if (ret != 0)
- DPRINT_ERR(NETVSC, "Unable to send packet %p ret %d",
+ dev_err(&device->device, "Unable to send packet %p ret %d",
packet, ret);
atomic_inc(&net_device->num_outstanding_sends);
@@ -939,6 +714,98 @@
return ret;
}
+static void netvsc_send_recv_completion(struct hv_device *device,
+ u64 transaction_id)
+{
+ struct nvsp_message recvcompMessage;
+ int retries = 0;
+ int ret;
+
+ recvcompMessage.hdr.msg_type =
+ NVSP_MSG1_TYPE_SEND_RNDIS_PKT_COMPLETE;
+
+ /* FIXME: Pass in the status */
+ recvcompMessage.msg.v1_msg.send_rndis_pkt_complete.status =
+ NVSP_STAT_SUCCESS;
+
+retry_send_cmplt:
+ /* Send the completion */
+ ret = vmbus_sendpacket(device->channel, &recvcompMessage,
+ sizeof(struct nvsp_message), transaction_id,
+ VM_PKT_COMP, 0);
+ if (ret == 0) {
+ /* success */
+ /* no-op */
+ } else if (ret == -1) {
+ /* no more room...wait a bit and attempt to retry 3 times */
+ retries++;
+ dev_err(&device->device, "unable to send receive completion pkt"
+ " (tid %llx)...retrying %d", transaction_id, retries);
+
+ if (retries < 4) {
+ udelay(100);
+ goto retry_send_cmplt;
+ } else {
+ dev_err(&device->device, "unable to send receive "
+ "completion pkt (tid %llx)...give up retrying",
+ transaction_id);
+ }
+ } else {
+ dev_err(&device->device, "unable to send receive "
+ "completion pkt - %llx", transaction_id);
+ }
+}
+
+/* Send a receive completion packet to RNDIS device (ie NetVsp) */
+static void netvsc_receive_completion(void *context)
+{
+ struct hv_netvsc_packet *packet = context;
+ struct hv_device *device = (struct hv_device *)packet->device;
+ struct netvsc_device *net_device;
+ u64 transaction_id = 0;
+ bool fsend_receive_comp = false;
+ unsigned long flags;
+
+ /*
+ * Even though it seems logical to do a GetOutboundNetDevice() here to
+ * send out receive completion, we are using GetInboundNetDevice()
+ * since we may have disable outbound traffic already.
+ */
+ net_device = get_inbound_net_device(device);
+ if (!net_device) {
+ dev_err(&device->device, "unable to get net device..."
+ "device being destroyed?");
+ return;
+ }
+
+ /* Overloading use of the lock. */
+ spin_lock_irqsave(&net_device->recv_pkt_list_lock, flags);
+
+ packet->xfer_page_pkt->count--;
+
+ /*
+ * Last one in the line that represent 1 xfer page packet.
+ * Return the xfer page packet itself to the freelist
+ */
+ if (packet->xfer_page_pkt->count == 0) {
+ fsend_receive_comp = true;
+ transaction_id = packet->completion.recv.recv_completion_tid;
+ list_add_tail(&packet->xfer_page_pkt->list_ent,
+ &net_device->recv_pkt_list);
+
+ }
+
+ /* Put the packet back */
+ list_add_tail(&packet->list_ent, &net_device->recv_pkt_list);
+ spin_unlock_irqrestore(&net_device->recv_pkt_list_lock, flags);
+
+ /* Send a receive completion for the xfer page packet */
+ if (fsend_receive_comp)
+ netvsc_send_recv_completion(device, transaction_id);
+
+ put_net_device(device);
+}
+
static void netvsc_receive(struct hv_device *device,
struct vmpacket_descriptor *packet)
{
@@ -953,11 +820,12 @@
int i, j;
int count = 0, bytes_remain = 0;
unsigned long flags;
+
LIST_HEAD(listHead);
net_device = get_inbound_net_device(device);
if (!net_device) {
- DPRINT_ERR(NETVSC, "unable to get net device..."
+ dev_err(&device->device, "unable to get net device..."
"device being destroyed?");
return;
}
@@ -967,7 +835,7 @@
* packet
*/
if (packet->type != VM_PKT_DATA_USING_XFER_PAGES) {
- DPRINT_ERR(NETVSC, "Unknown packet type received - %d",
+ dev_err(&device->device, "Unknown packet type received - %d",
packet->type);
put_net_device(device);
return;
@@ -979,28 +847,22 @@
/* Make sure this is a valid nvsp packet */
if (nvsp_packet->hdr.msg_type !=
NVSP_MSG1_TYPE_SEND_RNDIS_PKT) {
- DPRINT_ERR(NETVSC, "Unknown nvsp packet type received - %d",
- nvsp_packet->hdr.msg_type);
+ dev_err(&device->device, "Unknown nvsp packet type received-"
+ " %d", nvsp_packet->hdr.msg_type);
put_net_device(device);
return;
}
- DPRINT_DBG(NETVSC, "NVSP packet received - type %d",
- nvsp_packet->hdr.msg_type);
-
vmxferpage_packet = (struct vmtransfer_page_packet_header *)packet;
if (vmxferpage_packet->xfer_pageset_id != NETVSC_RECEIVE_BUFFER_ID) {
- DPRINT_ERR(NETVSC, "Invalid xfer page set id - "
+ dev_err(&device->device, "Invalid xfer page set id - "
"expecting %x got %x", NETVSC_RECEIVE_BUFFER_ID,
vmxferpage_packet->xfer_pageset_id);
put_net_device(device);
return;
}
- DPRINT_DBG(NETVSC, "xfer page - range count %d",
- vmxferpage_packet->range_cnt);
-
/*
* Grab free packets (range count + 1) to represent this xfer
* page packet. +1 to represent the xfer page packet itself.
@@ -1021,9 +883,9 @@
* some of the xfer page packet ranges...
*/
if (count < 2) {
- DPRINT_ERR(NETVSC, "Got only %d netvsc pkt...needed %d pkts. "
- "Dropping this xfer page packet completely!",
- count, vmxferpage_packet->range_cnt + 1);
+ dev_err(&device->device, "Got only %d netvsc pkt...needed "
+ "%d pkts. Dropping this xfer page packet completely!",
+ count, vmxferpage_packet->range_cnt + 1);
/* Return it to the freelist */
spin_lock_irqsave(&net_device->recv_pkt_list_lock, flags);
@@ -1049,9 +911,9 @@
xferpage_packet->count = count - 1;
if (xferpage_packet->count != vmxferpage_packet->range_cnt) {
- DPRINT_INFO(NETVSC, "Needed %d netvsc pkts to satisy this xfer "
- "page...got %d", vmxferpage_packet->range_cnt,
- xferpage_packet->count);
+ dev_err(&device->device, "Needed %d netvsc pkts to satisy "
+ "this xfer page...got %d",
+ vmxferpage_packet->range_cnt, xferpage_packet->count);
}
/* Each range represents 1 RNDIS pkt that contains 1 ethernet frame */
@@ -1117,17 +979,9 @@
break;
}
}
- DPRINT_DBG(NETVSC, "[%d] - (abs offset %u len %u) => "
- "(pfn %llx, offset %u, len %u)", i,
- vmxferpage_packet->ranges[i].byte_offset,
- vmxferpage_packet->ranges[i].byte_count,
- netvsc_packet->page_buf[0].pfn,
- netvsc_packet->page_buf[0].offset,
- netvsc_packet->page_buf[0].len);
/* Pass it to the upper layer */
- ((struct netvsc_driver *)device->drv)->
- recv_cb(device, netvsc_packet);
+ rndis_filter_receive(device, netvsc_packet);
netvsc_receive_completion(netvsc_packet->
completion.recv.recv_completion_ctx);
@@ -1136,101 +990,6 @@
put_net_device(device);
}
-static void netvsc_send_recv_completion(struct hv_device *device,
- u64 transaction_id)
-{
- struct nvsp_message recvcompMessage;
- int retries = 0;
- int ret;
-
- DPRINT_DBG(NETVSC, "Sending receive completion pkt - %llx",
- transaction_id);
-
- recvcompMessage.hdr.msg_type =
- NVSP_MSG1_TYPE_SEND_RNDIS_PKT_COMPLETE;
-
- /* FIXME: Pass in the status */
- recvcompMessage.msg.v1_msg.send_rndis_pkt_complete.status =
- NVSP_STAT_SUCCESS;
-
-retry_send_cmplt:
- /* Send the completion */
- ret = vmbus_sendpacket(device->channel, &recvcompMessage,
- sizeof(struct nvsp_message), transaction_id,
- VM_PKT_COMP, 0);
- if (ret == 0) {
- /* success */
- /* no-op */
- } else if (ret == -1) {
- /* no more room...wait a bit and attempt to retry 3 times */
- retries++;
- DPRINT_ERR(NETVSC, "unable to send receive completion pkt "
- "(tid %llx)...retrying %d", transaction_id, retries);
-
- if (retries < 4) {
- udelay(100);
- goto retry_send_cmplt;
- } else {
- DPRINT_ERR(NETVSC, "unable to send receive completion "
- "pkt (tid %llx)...give up retrying",
- transaction_id);
- }
- } else {
- DPRINT_ERR(NETVSC, "unable to send receive completion pkt - "
- "%llx", transaction_id);
- }
-}
-
-/* Send a receive completion packet to RNDIS device (ie NetVsp) */
-static void netvsc_receive_completion(void *context)
-{
- struct hv_netvsc_packet *packet = context;
- struct hv_device *device = (struct hv_device *)packet->device;
- struct netvsc_device *net_device;
- u64 transaction_id = 0;
- bool fsend_receive_comp = false;
- unsigned long flags;
-
- /*
- * Even though it seems logical to do a GetOutboundNetDevice() here to
- * send out receive completion, we are using GetInboundNetDevice()
- * since we may have disable outbound traffic already.
- */
- net_device = get_inbound_net_device(device);
- if (!net_device) {
- DPRINT_ERR(NETVSC, "unable to get net device..."
- "device being destroyed?");
- return;
- }
-
- /* Overloading use of the lock. */
- spin_lock_irqsave(&net_device->recv_pkt_list_lock, flags);
-
- packet->xfer_page_pkt->count--;
-
- /*
- * Last one in the line that represent 1 xfer page packet.
- * Return the xfer page packet itself to the freelist
- */
- if (packet->xfer_page_pkt->count == 0) {
- fsend_receive_comp = true;
- transaction_id = packet->completion.recv.recv_completion_tid;
- list_add_tail(&packet->xfer_page_pkt->list_ent,
- &net_device->recv_pkt_list);
-
- }
-
- /* Put the packet back */
- list_add_tail(&packet->list_ent, &net_device->recv_pkt_list);
- spin_unlock_irqrestore(&net_device->recv_pkt_list_lock, flags);
-
- /* Send a receive completion for the xfer page packet */
- if (fsend_receive_comp)
- netvsc_send_recv_completion(device, transaction_id);
-
- put_net_device(device);
-}
-
static void netvsc_channel_cb(void *context)
{
int ret;
@@ -1251,7 +1010,7 @@
net_device = get_inbound_net_device(device);
if (!net_device) {
- DPRINT_ERR(NETVSC, "net device (%p) shutting down..."
+ dev_err(&device->device, "net device (%p) shutting down..."
"ignoring inbound packets", net_device);
goto out;
}
@@ -1261,9 +1020,6 @@
&bytes_recvd, &request_id);
if (ret == 0) {
if (bytes_recvd > 0) {
- DPRINT_DBG(NETVSC, "receive %d bytes, tid %llx",
- bytes_recvd, request_id);
-
desc = (struct vmpacket_descriptor *)buffer;
switch (desc->type) {
case VM_PKT_COMP:
@@ -1275,7 +1031,7 @@
break;
default:
- DPRINT_ERR(NETVSC,
+ dev_err(&device->device,
"unhandled packet type %d, "
"tid %llx len %d\n",
desc->type, request_id,
@@ -1304,7 +1060,7 @@
buffer = kmalloc(bytes_recvd, GFP_ATOMIC);
if (buffer == NULL) {
/* Try again next time around */
- DPRINT_ERR(NETVSC,
+ dev_err(&device->device,
"unable to allocate buffer of size "
"(%d)!!", bytes_recvd);
break;
@@ -1319,3 +1075,102 @@
kfree(buffer);
return;
}
+
+/*
+ * netvsc_device_add - Callback when the device belonging to this
+ * driver is added
+ */
+int netvsc_device_add(struct hv_device *device, void *additional_info)
+{
+ int ret = 0;
+ int i;
+ int ring_size =
+ ((struct netvsc_device_info *)additional_info)->ring_size;
+ struct netvsc_device *net_device;
+ struct hv_netvsc_packet *packet, *pos;
+
+ net_device = alloc_net_device(device);
+ if (!net_device) {
+ ret = -1;
+ goto cleanup;
+ }
+
+ /* Initialize the NetVSC channel extension */
+ net_device->recv_buf_size = NETVSC_RECEIVE_BUFFER_SIZE;
+ spin_lock_init(&net_device->recv_pkt_list_lock);
+
+ net_device->send_buf_size = NETVSC_SEND_BUFFER_SIZE;
+
+ INIT_LIST_HEAD(&net_device->recv_pkt_list);
+
+ for (i = 0; i < NETVSC_RECEIVE_PACKETLIST_COUNT; i++) {
+ packet = kzalloc(sizeof(struct hv_netvsc_packet) +
+ (NETVSC_RECEIVE_SG_COUNT *
+ sizeof(struct hv_page_buffer)), GFP_KERNEL);
+ if (!packet)
+ break;
+
+ list_add_tail(&packet->list_ent,
+ &net_device->recv_pkt_list);
+ }
+ init_completion(&net_device->channel_init_wait);
+
+ /* Open the channel */
+ ret = vmbus_open(device->channel, ring_size * PAGE_SIZE,
+ ring_size * PAGE_SIZE, NULL, 0,
+ netvsc_channel_cb, device);
+
+ if (ret != 0) {
+ dev_err(&device->device, "unable to open channel: %d", ret);
+ ret = -1;
+ goto cleanup;
+ }
+
+ /* Channel is opened */
+ pr_info("hv_netvsc channel opened successfully");
+
+ /* Connect with the NetVsp */
+ ret = netvsc_connect_vsp(device);
+ if (ret != 0) {
+ dev_err(&device->device,
+ "unable to connect to NetVSP - %d", ret);
+ ret = -1;
+ goto close;
+ }
+
+ return ret;
+
+close:
+ /* Now, we can close the channel safely */
+ vmbus_close(device->channel);
+
+cleanup:
+
+ if (net_device) {
+ list_for_each_entry_safe(packet, pos,
+ &net_device->recv_pkt_list,
+ list_ent) {
+ list_del(&packet->list_ent);
+ kfree(packet);
+ }
+
+ release_outbound_net_device(device);
+ release_inbound_net_device(device);
+
+ free_net_device(net_device);
+ }
+
+ return ret;
+}
+
+/*
+ * netvsc_initialize - Main entry point
+ */
+int netvsc_initialize(struct hv_driver *drv)
+{
+
+ drv->name = driver_name;
+ memcpy(&drv->dev_type, &netvsc_device_type, sizeof(struct hv_guid));
+
+ return 0;
+}
diff --git a/drivers/staging/hv/netvsc.h b/drivers/staging/hv/netvsc.h
deleted file mode 100644
index 45d24b9..0000000
--- a/drivers/staging/hv/netvsc.h
+++ /dev/null
@@ -1,332 +0,0 @@
-/*
- *
- * Copyright (c) 2009, Microsoft Corporation.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
- * Place - Suite 330, Boston, MA 02111-1307 USA.
- *
- * Authors:
- * Haiyang Zhang <haiyangz@microsoft.com>
- * Hank Janssen <hjanssen@microsoft.com>
- *
- */
-
-
-#ifndef _NETVSC_H_
-#define _NETVSC_H_
-
-#include <linux/list.h>
-#include "vmbus_packet_format.h"
-#include "vmbus_channel_interface.h"
-#include "netvsc_api.h"
-
-
-#define NVSP_INVALID_PROTOCOL_VERSION ((u32)0xFFFFFFFF)
-
-#define NVSP_PROTOCOL_VERSION_1 2
-#define NVSP_MIN_PROTOCOL_VERSION NVSP_PROTOCOL_VERSION_1
-#define NVSP_MAX_PROTOCOL_VERSION NVSP_PROTOCOL_VERSION_1
-
-enum {
- NVSP_MSG_TYPE_NONE = 0,
-
- /* Init Messages */
- NVSP_MSG_TYPE_INIT = 1,
- NVSP_MSG_TYPE_INIT_COMPLETE = 2,
-
- NVSP_VERSION_MSG_START = 100,
-
- /* Version 1 Messages */
- NVSP_MSG1_TYPE_SEND_NDIS_VER = NVSP_VERSION_MSG_START,
-
- NVSP_MSG1_TYPE_SEND_RECV_BUF,
- NVSP_MSG1_TYPE_SEND_RECV_BUF_COMPLETE,
- NVSP_MSG1_TYPE_REVOKE_RECV_BUF,
-
- NVSP_MSG1_TYPE_SEND_SEND_BUF,
- NVSP_MSG1_TYPE_SEND_SEND_BUF_COMPLETE,
- NVSP_MSG1_TYPE_REVOKE_SEND_BUF,
-
- NVSP_MSG1_TYPE_SEND_RNDIS_PKT,
- NVSP_MSG1_TYPE_SEND_RNDIS_PKT_COMPLETE,
-
- /*
- * This should be set to the number of messages for the version with
- * the maximum number of messages.
- */
- NVSP_NUM_MSG_PER_VERSION = 9,
-};
-
-enum {
- NVSP_STAT_NONE = 0,
- NVSP_STAT_SUCCESS,
- NVSP_STAT_FAIL,
- NVSP_STAT_PROTOCOL_TOO_NEW,
- NVSP_STAT_PROTOCOL_TOO_OLD,
- NVSP_STAT_INVALID_RNDIS_PKT,
- NVSP_STAT_BUSY,
- NVSP_STAT_MAX,
-};
-
-struct nvsp_message_header {
- u32 msg_type;
-};
-
-/* Init Messages */
-
-/*
- * This message is used by the VSC to initialize the channel after the channels
- * has been opened. This message should never include anything other then
- * versioning (i.e. this message will be the same for ever).
- */
-struct nvsp_message_init {
- u32 min_protocol_ver;
- u32 max_protocol_ver;
-} __packed;
-
-/*
- * This message is used by the VSP to complete the initialization of the
- * channel. This message should never include anything other then versioning
- * (i.e. this message will be the same for ever).
- */
-struct nvsp_message_init_complete {
- u32 negotiated_protocol_ver;
- u32 max_mdl_chain_len;
- u32 status;
-} __packed;
-
-union nvsp_message_init_uber {
- struct nvsp_message_init init;
- struct nvsp_message_init_complete init_complete;
-} __packed;
-
-/* Version 1 Messages */
-
-/*
- * This message is used by the VSC to send the NDIS version to the VSP. The VSP
- * can use this information when handling OIDs sent by the VSC.
- */
-struct nvsp_1_message_send_ndis_version {
- u32 ndis_major_ver;
- u32 ndis_minor_ver;
-} __packed;
-
-/*
- * This message is used by the VSC to send a receive buffer to the VSP. The VSP
- * can then use the receive buffer to send data to the VSC.
- */
-struct nvsp_1_message_send_receive_buffer {
- u32 gpadl_handle;
- u16 id;
-} __packed;
-
-struct nvsp_1_receive_buffer_section {
- u32 offset;
- u32 sub_alloc_size;
- u32 num_sub_allocs;
- u32 end_offset;
-} __packed;
-
-/*
- * This message is used by the VSP to acknowledge a receive buffer send by the
- * VSC. This message must be sent by the VSP before the VSP uses the receive
- * buffer.
- */
-struct nvsp_1_message_send_receive_buffer_complete {
- u32 status;
- u32 num_sections;
-
- /*
- * The receive buffer is split into two parts, a large suballocation
- * section and a small suballocation section. These sections are then
- * suballocated by a certain size.
- */
-
- /*
- * For example, the following break up of the receive buffer has 6
- * large suballocations and 10 small suballocations.
- */
-
- /*
- * | Large Section | | Small Section |
- * ------------------------------------------------------------
- * | | | | | | | | | | | | | | | | | |
- * | |
- * LargeOffset SmallOffset
- */
-
- struct nvsp_1_receive_buffer_section sections[1];
-} __packed;
-
-/*
- * This message is sent by the VSC to revoke the receive buffer. After the VSP
- * completes this transaction, the vsp should never use the receive buffer
- * again.
- */
-struct nvsp_1_message_revoke_receive_buffer {
- u16 id;
-};
-
-/*
- * This message is used by the VSC to send a send buffer to the VSP. The VSC
- * can then use the send buffer to send data to the VSP.
- */
-struct nvsp_1_message_send_send_buffer {
- u32 gpadl_handle;
- u16 id;
-} __packed;
-
-/*
- * This message is used by the VSP to acknowledge a send buffer sent by the
- * VSC. This message must be sent by the VSP before the VSP uses the sent
- * buffer.
- */
-struct nvsp_1_message_send_send_buffer_complete {
- u32 status;
-
- /*
- * The VSC gets to choose the size of the send buffer and the VSP gets
- * to choose the sections size of the buffer. This was done to enable
- * dynamic reconfigurations when the cost of GPA-direct buffers
- * decreases.
- */
- u32 section_size;
-} __packed;
-
-/*
- * This message is sent by the VSC to revoke the send buffer. After the VSP
- * completes this transaction, the vsp should never use the send buffer again.
- */
-struct nvsp_1_message_revoke_send_buffer {
- u16 id;
-};
-
-/*
- * This message is used by both the VSP and the VSC to send a RNDIS message to
- * the opposite channel endpoint.
- */
-struct nvsp_1_message_send_rndis_packet {
- /*
- * This field is specified by RNIDS. They assume there's two different
- * channels of communication. However, the Network VSP only has one.
- * Therefore, the channel travels with the RNDIS packet.
- */
- u32 channel_type;
-
- /*
- * This field is used to send part or all of the data through a send
- * buffer. This values specifies an index into the send buffer. If the
- * index is 0xFFFFFFFF, then the send buffer is not being used and all
- * of the data was sent through other VMBus mechanisms.
- */
- u32 send_buf_section_index;
- u32 send_buf_section_size;
-} __packed;
-
-/*
- * This message is used by both the VSP and the VSC to complete a RNDIS message
- * to the opposite channel endpoint. At this point, the initiator of this
- * message cannot use any resources associated with the original RNDIS packet.
- */
-struct nvsp_1_message_send_rndis_packet_complete {
- u32 status;
-};
-
-union nvsp_1_message_uber {
- struct nvsp_1_message_send_ndis_version send_ndis_ver;
-
- struct nvsp_1_message_send_receive_buffer send_recv_buf;
- struct nvsp_1_message_send_receive_buffer_complete
- send_recv_buf_complete;
- struct nvsp_1_message_revoke_receive_buffer revoke_recv_buf;
-
- struct nvsp_1_message_send_send_buffer send_send_buf;
- struct nvsp_1_message_send_send_buffer_complete send_send_buf_complete;
- struct nvsp_1_message_revoke_send_buffer revoke_send_buf;
-
- struct nvsp_1_message_send_rndis_packet send_rndis_pkt;
- struct nvsp_1_message_send_rndis_packet_complete
- send_rndis_pkt_complete;
-} __packed;
-
-union nvsp_all_messages {
- union nvsp_message_init_uber init_msg;
- union nvsp_1_message_uber v1_msg;
-} __packed;
-
-/* ALL Messages */
-struct nvsp_message {
- struct nvsp_message_header hdr;
- union nvsp_all_messages msg;
-} __packed;
-
-
-
-
-/* #define NVSC_MIN_PROTOCOL_VERSION 1 */
-/* #define NVSC_MAX_PROTOCOL_VERSION 1 */
-
-#define NETVSC_SEND_BUFFER_SIZE (64*1024) /* 64K */
-#define NETVSC_SEND_BUFFER_ID 0xface
-
-
-#define NETVSC_RECEIVE_BUFFER_SIZE (1024*1024) /* 1MB */
-
-#define NETVSC_RECEIVE_BUFFER_ID 0xcafe
-
-#define NETVSC_RECEIVE_SG_COUNT 1
-
-/* Preallocated receive packets */
-#define NETVSC_RECEIVE_PACKETLIST_COUNT 256
-
-#define NETVSC_PACKET_SIZE 2048
-
-/* Per netvsc channel-specific */
-struct netvsc_device {
- struct hv_device *dev;
-
- atomic_t refcnt;
- atomic_t num_outstanding_sends;
- /*
- * List of free preallocated hv_netvsc_packet to represent receive
- * packet
- */
- struct list_head recv_pkt_list;
- spinlock_t recv_pkt_list_lock;
-
- /* Send buffer allocated by us but manages by NetVSP */
- void *send_buf;
- u32 send_buf_size;
- u32 send_buf_gpadl_handle;
- u32 send_section_size;
-
- /* Receive buffer allocated by us but manages by NetVSP */
- void *recv_buf;
- u32 recv_buf_size;
- u32 recv_buf_gpadl_handle;
- u32 recv_section_cnt;
- struct nvsp_1_receive_buffer_section *recv_section;
-
- /* Used for NetVSP initialization protocol */
- int wait_condition;
- wait_queue_head_t channel_init_wait;
- struct nvsp_message channel_init_pkt;
-
- struct nvsp_message revoke_packet;
- /* unsigned char HwMacAddr[HW_MACADDR_LEN]; */
-
- /* Holds rndis device info */
- void *extension;
-};
-
-#endif /* _NETVSC_H_ */
diff --git a/drivers/staging/hv/netvsc_api.h b/drivers/staging/hv/netvsc_api.h
deleted file mode 100644
index b4bed36..0000000
--- a/drivers/staging/hv/netvsc_api.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- *
- * Copyright (c) 2009, Microsoft Corporation.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
- * Place - Suite 330, Boston, MA 02111-1307 USA.
- *
- * Authors:
- * Haiyang Zhang <haiyangz@microsoft.com>
- * Hank Janssen <hjanssen@microsoft.com>
- *
- */
-
-
-#ifndef _NETVSC_API_H_
-#define _NETVSC_API_H_
-
-#include "vmbus_api.h"
-
-/* Fwd declaration */
-struct hv_netvsc_packet;
-
-/* Represent the xfer page packet which contains 1 or more netvsc packet */
-struct xferpage_packet {
- struct list_head list_ent;
-
- /* # of netvsc packets this xfer packet contains */
- u32 count;
-};
-
-/* The number of pages which are enough to cover jumbo frame buffer. */
-#define NETVSC_PACKET_MAXPAGE 4
-
-/*
- * Represent netvsc packet which contains 1 RNDIS and 1 ethernet frame
- * within the RNDIS
- */
-struct hv_netvsc_packet {
- /* Bookkeeping stuff */
- struct list_head list_ent;
-
- struct hv_device *device;
- bool is_data_pkt;
-
- /*
- * Valid only for receives when we break a xfer page packet
- * into multiple netvsc packets
- */
- struct xferpage_packet *xfer_page_pkt;
-
- union {
- struct{
- u64 recv_completion_tid;
- void *recv_completion_ctx;
- void (*recv_completion)(void *context);
- } recv;
- struct{
- u64 send_completion_tid;
- void *send_completion_ctx;
- void (*send_completion)(void *context);
- } send;
- } completion;
-
- /* This points to the memory after page_buf */
- void *extension;
-
- u32 total_data_buflen;
- /* Points to the send/receive buffer where the ethernet frame is */
- u32 page_buf_cnt;
- struct hv_page_buffer page_buf[NETVSC_PACKET_MAXPAGE];
-};
-
-/* Represents the net vsc driver */
-struct netvsc_driver {
- /* Must be the first field */
- /* Which is a bug FIXME! */
- struct hv_driver base;
-
- u32 ring_buf_size;
- u32 req_ext_size;
-
- /*
- * This is set by the caller to allow us to callback when we
- * receive a packet from the "wire"
- */
- int (*recv_cb)(struct hv_device *dev,
- struct hv_netvsc_packet *packet);
- void (*link_status_change)(struct hv_device *dev, u32 status);
-
- /* Specific to this driver */
- int (*send)(struct hv_device *dev, struct hv_netvsc_packet *packet);
-
- void *ctx;
-};
-
-struct netvsc_device_info {
- unsigned char mac_adr[6];
- bool link_state; /* 0 - link up, 1 - link down */
-};
-
-/* Interface */
-int netvsc_initialize(struct hv_driver *drv);
-int rndis_filter_open(struct hv_device *dev);
-int rndis_filter_close(struct hv_device *dev);
-
-#endif /* _NETVSC_API_H_ */
diff --git a/drivers/staging/hv/netvsc_drv.c b/drivers/staging/hv/netvsc_drv.c
index aaa81883..7b9c229 100644
--- a/drivers/staging/hv/netvsc_drv.c
+++ b/drivers/staging/hv/netvsc_drv.c
@@ -18,6 +18,8 @@
* Haiyang Zhang <haiyangz@microsoft.com>
* Hank Janssen <hjanssen@microsoft.com>
*/
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
#include <linux/init.h>
#include <linux/module.h>
#include <linux/highmem.h>
@@ -36,11 +38,9 @@
#include <net/route.h>
#include <net/sock.h>
#include <net/pkt_sched.h>
-#include "hv_api.h"
-#include "logging.h"
-#include "version_info.h"
-#include "vmbus.h"
-#include "netvsc_api.h"
+
+#include "hyperv.h"
+#include "hyperv_net.h"
struct net_device_context {
/* point back to our device context */
@@ -58,9 +58,6 @@
module_param(ring_size, int, S_IRUGO);
MODULE_PARM_DESC(ring_size, "Ring buffer size (# of pages)");
-/* The one and only one */
-static struct netvsc_driver g_netvsc_drv;
-
/* no-op so the netdev core doesn't return -EINVAL when modifying the the
* multicast address list in SIOCADDMULTI. hv is setup to get all multicast
* when it calls RndisFilterOnOpen() */
@@ -78,14 +75,14 @@
/* Open up the device */
ret = rndis_filter_open(device_obj);
if (ret != 0) {
- DPRINT_ERR(NETVSC_DRV,
- "unable to open device (ret %d).", ret);
+ netdev_err(net, "unable to open device (ret %d).\n",
+ ret);
return ret;
}
netif_start_queue(net);
} else {
- DPRINT_ERR(NETVSC_DRV, "unable to open device...link is down.");
+ netdev_err(net, "unable to open device...link is down.\n");
}
return ret;
@@ -101,7 +98,7 @@
ret = rndis_filter_close(device_obj);
if (ret != 0)
- DPRINT_ERR(NETVSC_DRV, "unable to close device (ret %d).", ret);
+ netdev_err(net, "unable to close device (ret %d).\n", ret);
return ret;
}
@@ -130,16 +127,10 @@
static int netvsc_start_xmit(struct sk_buff *skb, struct net_device *net)
{
struct net_device_context *net_device_ctx = netdev_priv(net);
- struct hv_driver *drv =
- drv_to_hv_drv(net_device_ctx->device_ctx->device.driver);
- struct netvsc_driver *net_drv_obj = drv->priv;
struct hv_netvsc_packet *packet;
int ret;
unsigned int i, num_pages;
- DPRINT_DBG(NETVSC_DRV, "xmit packet - len %d data_len %d",
- skb->len, skb->data_len);
-
/* Add 1 for skb->data and additional one for RNDIS */
num_pages = skb_shinfo(skb)->nr_frags + 1 + 1;
if (num_pages > net_device_ctx->avail)
@@ -148,10 +139,10 @@
/* Allocate a netvsc packet based on # of frags. */
packet = kzalloc(sizeof(struct hv_netvsc_packet) +
(num_pages * sizeof(struct hv_page_buffer)) +
- net_drv_obj->req_ext_size, GFP_ATOMIC);
+ sizeof(struct rndis_filter_packet), GFP_ATOMIC);
if (!packet) {
/* out of memory, silently drop packet */
- DPRINT_ERR(NETVSC_DRV, "unable to allocate hv_netvsc_packet");
+ netdev_err(net, "unable to allocate hv_netvsc_packet\n");
dev_kfree_skb(skb);
net->stats.tx_dropped++;
@@ -191,16 +182,12 @@
packet->completion.send.send_completion_ctx = packet;
packet->completion.send.send_completion_tid = (unsigned long)skb;
- ret = net_drv_obj->send(net_device_ctx->device_ctx,
+ ret = rndis_filter_send(net_device_ctx->device_ctx,
packet);
if (ret == 0) {
net->stats.tx_bytes += skb->len;
net->stats.tx_packets++;
- DPRINT_DBG(NETVSC_DRV, "# of xmits %lu total size %lu",
- net->stats.tx_packets,
- net->stats.tx_bytes);
-
net_device_ctx->avail -= num_pages;
if (net_device_ctx->avail < PACKET_PAGES_LOWATER)
netif_stop_queue(net);
@@ -216,15 +203,15 @@
/*
* netvsc_linkstatus_callback - Link up/down notification
*/
-static void netvsc_linkstatus_callback(struct hv_device *device_obj,
+void netvsc_linkstatus_callback(struct hv_device *device_obj,
unsigned int status)
{
struct net_device *net = dev_get_drvdata(&device_obj->device);
struct net_device_context *ndev_ctx;
if (!net) {
- DPRINT_ERR(NETVSC_DRV, "got link status but net device "
- "not initialized yet");
+ netdev_err(net, "got link status but net device "
+ "not initialized yet\n");
return;
}
@@ -244,7 +231,7 @@
* netvsc_recv_callback - Callback when we receive a packet from the
* "wire" on the specified device.
*/
-static int netvsc_recv_callback(struct hv_device *device_obj,
+int netvsc_recv_callback(struct hv_device *device_obj,
struct hv_netvsc_packet *packet)
{
struct net_device *net = dev_get_drvdata(&device_obj->device);
@@ -254,8 +241,8 @@
unsigned long flags;
if (!net) {
- DPRINT_ERR(NETVSC_DRV, "got receive callback but net device "
- "not initialized yet");
+ netdev_err(net, "got receive callback but net device"
+ " not initialized yet\n");
return 0;
}
@@ -301,9 +288,6 @@
*/
netif_rx(skb);
- DPRINT_DBG(NETVSC_DRV, "# of recvs %lu total size %lu",
- net->stats.rx_packets, net->stats.rx_bytes);
-
return 0;
}
@@ -349,20 +333,13 @@
}
-static int netvsc_probe(struct device *device)
+static int netvsc_probe(struct hv_device *dev)
{
- struct hv_driver *drv =
- drv_to_hv_drv(device->driver);
- struct netvsc_driver *net_drv_obj = drv->priv;
- struct hv_device *device_obj = device_to_hv_device(device);
struct net_device *net = NULL;
struct net_device_context *net_device_ctx;
struct netvsc_device_info device_info;
int ret;
- if (!net_drv_obj->base.dev_add)
- return -1;
-
net = alloc_etherdev(sizeof(struct net_device_context));
if (!net)
return -1;
@@ -371,19 +348,19 @@
netif_carrier_off(net);
net_device_ctx = netdev_priv(net);
- net_device_ctx->device_ctx = device_obj;
+ net_device_ctx->device_ctx = dev;
net_device_ctx->avail = ring_size;
- dev_set_drvdata(device, net);
+ dev_set_drvdata(&dev->device, net);
INIT_WORK(&net_device_ctx->work, netvsc_send_garp);
/* Notify the netvsc driver of the new device */
- ret = net_drv_obj->base.dev_add(device_obj, &device_info);
+ device_info.ring_size = ring_size;
+ ret = rndis_filte_device_add(dev, &device_info);
if (ret != 0) {
free_netdev(net);
- dev_set_drvdata(device, NULL);
+ dev_set_drvdata(&dev->device, NULL);
- DPRINT_ERR(NETVSC_DRV, "unable to add netvsc device (ret %d)",
- ret);
+ netdev_err(net, "unable to add netvsc device (ret %d)\n", ret);
return ret;
}
@@ -408,35 +385,28 @@
net->features = NETIF_F_SG;
SET_ETHTOOL_OPS(net, ðtool_ops);
- SET_NETDEV_DEV(net, device);
+ SET_NETDEV_DEV(net, &dev->device);
ret = register_netdev(net);
if (ret != 0) {
/* Remove the device and release the resource */
- net_drv_obj->base.dev_rm(device_obj);
+ rndis_filter_device_remove(dev);
free_netdev(net);
}
return ret;
}
-static int netvsc_remove(struct device *device)
+static int netvsc_remove(struct hv_device *dev)
{
- struct hv_driver *drv =
- drv_to_hv_drv(device->driver);
- struct netvsc_driver *net_drv_obj = drv->priv;
- struct hv_device *device_obj = device_to_hv_device(device);
- struct net_device *net = dev_get_drvdata(&device_obj->device);
+ struct net_device *net = dev_get_drvdata(&dev->device);
int ret;
if (net == NULL) {
- DPRINT_INFO(NETVSC, "no net device to remove");
+ dev_err(&dev->device, "No net device to remove\n");
return 0;
}
- if (!net_drv_obj->base.dev_rm)
- return -1;
-
/* Stop outbound asap */
netif_stop_queue(net);
/* netif_carrier_off(net); */
@@ -447,84 +417,27 @@
* Call to the vsc driver to let it know that the device is being
* removed
*/
- ret = net_drv_obj->base.dev_rm(device_obj);
+ ret = rndis_filter_device_remove(dev);
if (ret != 0) {
/* TODO: */
- DPRINT_ERR(NETVSC, "unable to remove vsc device (ret %d)", ret);
+ netdev_err(net, "unable to remove vsc device (ret %d)\n", ret);
}
free_netdev(net);
return ret;
}
-static int netvsc_drv_exit_cb(struct device *dev, void *data)
-{
- struct device **curr = (struct device **)data;
+/* The one and only one */
+static struct hv_driver netvsc_drv = {
+ .probe = netvsc_probe,
+ .remove = netvsc_remove,
+};
- *curr = dev;
- /* stop iterating */
- return 1;
+static void __exit netvsc_drv_exit(void)
+{
+ vmbus_child_driver_unregister(&netvsc_drv.driver);
}
-static void netvsc_drv_exit(void)
-{
- struct netvsc_driver *netvsc_drv_obj = &g_netvsc_drv;
- struct hv_driver *drv = &g_netvsc_drv.base;
- struct device *current_dev;
- int ret;
-
- while (1) {
- current_dev = NULL;
-
- /* Get the device */
- ret = driver_for_each_device(&drv->driver, NULL,
- ¤t_dev, netvsc_drv_exit_cb);
- if (ret)
- DPRINT_WARN(NETVSC_DRV,
- "driver_for_each_device returned %d", ret);
-
- if (current_dev == NULL)
- break;
-
- /* Initiate removal from the top-down */
- DPRINT_INFO(NETVSC_DRV, "unregistering device (%p)...",
- current_dev);
-
- device_unregister(current_dev);
- }
-
- if (netvsc_drv_obj->base.cleanup)
- netvsc_drv_obj->base.cleanup(&netvsc_drv_obj->base);
-
- vmbus_child_driver_unregister(&drv->driver);
-
- return;
-}
-
-static int netvsc_drv_init(int (*drv_init)(struct hv_driver *drv))
-{
- struct netvsc_driver *net_drv_obj = &g_netvsc_drv;
- struct hv_driver *drv = &g_netvsc_drv.base;
- int ret;
-
- net_drv_obj->ring_buf_size = ring_size * PAGE_SIZE;
- net_drv_obj->recv_cb = netvsc_recv_callback;
- net_drv_obj->link_status_change = netvsc_linkstatus_callback;
- drv->priv = net_drv_obj;
-
- /* Callback to client driver to complete the initialization */
- drv_init(&net_drv_obj->base);
-
- drv->driver.name = net_drv_obj->base.name;
-
- drv->driver.probe = netvsc_probe;
- drv->driver.remove = netvsc_remove;
-
- /* The driver belongs to vmbus */
- ret = vmbus_child_driver_register(&drv->driver);
-
- return ret;
-}
static const struct dmi_system_id __initconst
hv_netvsc_dmi_table[] __maybe_unused = {
@@ -540,19 +453,26 @@
};
MODULE_DEVICE_TABLE(dmi, hv_netvsc_dmi_table);
-static int __init netvsc_init(void)
+static int __init netvsc_drv_init(void)
{
- DPRINT_INFO(NETVSC_DRV, "Netvsc initializing....");
+ struct hv_driver *drv = &netvsc_drv;
+ int ret;
+
+ pr_info("initializing....");
if (!dmi_check_system(hv_netvsc_dmi_table))
return -ENODEV;
- return netvsc_drv_init(netvsc_initialize);
-}
-static void __exit netvsc_exit(void)
-{
- netvsc_drv_exit();
+ /* Callback to client driver to complete the initialization */
+ netvsc_initialize(drv);
+
+ drv->driver.name = drv->name;
+
+ /* The driver belongs to vmbus */
+ ret = vmbus_child_driver_register(&drv->driver);
+
+ return ret;
}
static const struct pci_device_id __initconst
@@ -566,5 +486,5 @@
MODULE_VERSION(HV_DRV_VERSION);
MODULE_DESCRIPTION("Microsoft Hyper-V network driver");
-module_init(netvsc_init);
-module_exit(netvsc_exit);
+module_init(netvsc_drv_init);
+module_exit(netvsc_drv_exit);
diff --git a/drivers/staging/hv/ring_buffer.c b/drivers/staging/hv/ring_buffer.c
index 66688fb..3da3330 100644
--- a/drivers/staging/hv/ring_buffer.c
+++ b/drivers/staging/hv/ring_buffer.c
@@ -18,13 +18,16 @@
* Authors:
* Haiyang Zhang <haiyangz@microsoft.com>
* Hank Janssen <hjanssen@microsoft.com>
+ * K. Y. Srinivasan <kys@microsoft.com>
*
*/
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
#include <linux/kernel.h>
#include <linux/mm.h>
-#include "logging.h"
-#include "ring_buffer.h"
+
+#include "hyperv.h"
+#include "hyperv_vmbus.h"
/* #defines */
@@ -34,18 +37,15 @@
#define BYTES_AVAIL_TO_WRITE(r, w, z) ((w) >= (r)) ? ((z) - ((w) - (r))) : ((r) - (w))
-/*++
-
-Name:
- get_ringbuffer_availbytes()
-
-Description:
- Get number of bytes available to read and to write to
- for the specified ring buffer
-
---*/
+/*
+ *
+ * hv_get_ringbuffer_availbytes()
+ *
+ * Get number of bytes available to read and to write to
+ * for the specified ring buffer
+ */
static inline void
-get_ringbuffer_availbytes(struct hv_ring_buffer_info *rbi,
+hv_get_ringbuffer_availbytes(struct hv_ring_buffer_info *rbi,
u32 *read, u32 *write)
{
u32 read_loc, write_loc;
@@ -58,162 +58,131 @@
*read = rbi->ring_datasize - *write;
}
-/*++
-
-Name:
- get_next_write_location()
-
-Description:
- Get the next write location for the specified ring buffer
-
---*/
+/*
+ * hv_get_next_write_location()
+ *
+ * Get the next write location for the specified ring buffer
+ *
+ */
static inline u32
-get_next_write_location(struct hv_ring_buffer_info *ring_info)
+hv_get_next_write_location(struct hv_ring_buffer_info *ring_info)
{
u32 next = ring_info->ring_buffer->write_index;
- /* ASSERT(next < ring_info->RingDataSize); */
-
return next;
}
-/*++
-
-Name:
- set_next_write_location()
-
-Description:
- Set the next write location for the specified ring buffer
-
---*/
+/*
+ * hv_set_next_write_location()
+ *
+ * Set the next write location for the specified ring buffer
+ *
+ */
static inline void
-set_next_write_location(struct hv_ring_buffer_info *ring_info,
+hv_set_next_write_location(struct hv_ring_buffer_info *ring_info,
u32 next_write_location)
{
ring_info->ring_buffer->write_index = next_write_location;
}
-/*++
-
-Name:
- get_next_read_location()
-
-Description:
- Get the next read location for the specified ring buffer
-
---*/
+/*
+ * hv_get_next_read_location()
+ *
+ * Get the next read location for the specified ring buffer
+ */
static inline u32
-get_next_read_location(struct hv_ring_buffer_info *ring_info)
+hv_get_next_read_location(struct hv_ring_buffer_info *ring_info)
{
u32 next = ring_info->ring_buffer->read_index;
- /* ASSERT(next < ring_info->RingDataSize); */
-
return next;
}
-/*++
-
-Name:
- get_next_readlocation_withoffset()
-
-Description:
- Get the next read location + offset for the specified ring buffer.
- This allows the caller to skip
-
---*/
+/*
+ * hv_get_next_readlocation_withoffset()
+ *
+ * Get the next read location + offset for the specified ring buffer.
+ * This allows the caller to skip
+ */
static inline u32
-get_next_readlocation_withoffset(struct hv_ring_buffer_info *ring_info,
+hv_get_next_readlocation_withoffset(struct hv_ring_buffer_info *ring_info,
u32 offset)
{
u32 next = ring_info->ring_buffer->read_index;
- /* ASSERT(next < ring_info->RingDataSize); */
next += offset;
next %= ring_info->ring_datasize;
return next;
}
-/*++
-
-Name:
- set_next_read_location()
-
-Description:
- Set the next read location for the specified ring buffer
-
---*/
+/*
+ *
+ * hv_set_next_read_location()
+ *
+ * Set the next read location for the specified ring buffer
+ *
+ */
static inline void
-set_next_read_location(struct hv_ring_buffer_info *ring_info,
+hv_set_next_read_location(struct hv_ring_buffer_info *ring_info,
u32 next_read_location)
{
ring_info->ring_buffer->read_index = next_read_location;
}
-/*++
-
-Name:
- get_ring_buffer()
-
-Description:
- Get the start of the ring buffer
-
---*/
+/*
+ *
+ * hv_get_ring_buffer()
+ *
+ * Get the start of the ring buffer
+ */
static inline void *
-get_ring_buffer(struct hv_ring_buffer_info *ring_info)
+hv_get_ring_buffer(struct hv_ring_buffer_info *ring_info)
{
return (void *)ring_info->ring_buffer->buffer;
}
-/*++
-
-Name:
- get_ring_buffersize()
-
-Description:
- Get the size of the ring buffer
-
---*/
+/*
+ *
+ * hv_get_ring_buffersize()
+ *
+ * Get the size of the ring buffer
+ */
static inline u32
-get_ring_buffersize(struct hv_ring_buffer_info *ring_info)
+hv_get_ring_buffersize(struct hv_ring_buffer_info *ring_info)
{
return ring_info->ring_datasize;
}
-/*++
-
-Name:
- get_ring_bufferindices()
-
-Description:
- Get the read and write indices as u64 of the specified ring buffer
-
---*/
+/*
+ *
+ * hv_get_ring_bufferindices()
+ *
+ * Get the read and write indices as u64 of the specified ring buffer
+ *
+ */
static inline u64
-get_ring_bufferindices(struct hv_ring_buffer_info *ring_info)
+hv_get_ring_bufferindices(struct hv_ring_buffer_info *ring_info)
{
return (u64)ring_info->ring_buffer->write_index << 32;
}
-/*++
-
-Name:
- dump_ring_info()
-
-Description:
- Dump out to console the ring buffer info
-
---*/
-void dump_ring_info(struct hv_ring_buffer_info *ring_info, char *prefix)
+/*
+ *
+ * hv_dump_ring_info()
+ *
+ * Dump out to console the ring buffer info
+ *
+ */
+void hv_dump_ring_info(struct hv_ring_buffer_info *ring_info, char *prefix)
{
u32 bytes_avail_towrite;
u32 bytes_avail_toread;
- get_ringbuffer_availbytes(ring_info,
+ hv_get_ringbuffer_availbytes(ring_info,
&bytes_avail_toread,
&bytes_avail_towrite);
@@ -231,41 +200,90 @@
}
-/* Internal routines */
-
-static u32
-copyto_ringbuffer(
- struct hv_ring_buffer_info *ring_info,
- u32 start_write_offset,
- void *src,
- u32 srclen);
-
-static u32
-copyfrom_ringbuffer(
+/*
+ *
+ * hv_copyfrom_ringbuffer()
+ *
+ * Helper routine to copy to source from ring buffer.
+ * Assume there is enough room. Handles wrap-around in src case only!!
+ *
+ */
+static u32 hv_copyfrom_ringbuffer(
struct hv_ring_buffer_info *ring_info,
void *dest,
u32 destlen,
- u32 start_read_offset);
+ u32 start_read_offset)
+{
+ void *ring_buffer = hv_get_ring_buffer(ring_info);
+ u32 ring_buffer_size = hv_get_ring_buffersize(ring_info);
+
+ u32 frag_len;
+
+ /* wrap-around detected at the src */
+ if (destlen > ring_buffer_size - start_read_offset) {
+ frag_len = ring_buffer_size - start_read_offset;
+
+ memcpy(dest, ring_buffer + start_read_offset, frag_len);
+ memcpy(dest + frag_len, ring_buffer, destlen - frag_len);
+ } else
+
+ memcpy(dest, ring_buffer + start_read_offset, destlen);
+ start_read_offset += destlen;
+ start_read_offset %= ring_buffer_size;
-/*++
+ return start_read_offset;
+}
-Name:
- ringbuffer_get_debuginfo()
-Description:
- Get various debug metrics for the specified ring buffer
+/*
+ *
+ * hv_copyto_ringbuffer()
+ *
+ * Helper routine to copy from source to ring buffer.
+ * Assume there is enough room. Handles wrap-around in dest case only!!
+ *
+ */
+static u32 hv_copyto_ringbuffer(
+ struct hv_ring_buffer_info *ring_info,
+ u32 start_write_offset,
+ void *src,
+ u32 srclen)
+{
+ void *ring_buffer = hv_get_ring_buffer(ring_info);
+ u32 ring_buffer_size = hv_get_ring_buffersize(ring_info);
+ u32 frag_len;
---*/
-void ringbuffer_get_debuginfo(struct hv_ring_buffer_info *ring_info,
+ /* wrap-around detected! */
+ if (srclen > ring_buffer_size - start_write_offset) {
+ frag_len = ring_buffer_size - start_write_offset;
+ memcpy(ring_buffer + start_write_offset, src, frag_len);
+ memcpy(ring_buffer, src + frag_len, srclen - frag_len);
+ } else
+ memcpy(ring_buffer + start_write_offset, src, srclen);
+
+ start_write_offset += srclen;
+ start_write_offset %= ring_buffer_size;
+
+ return start_write_offset;
+}
+
+/*
+ *
+ * hv_ringbuffer_get_debuginfo()
+ *
+ * Get various debug metrics for the specified ring buffer
+ *
+ */
+void hv_ringbuffer_get_debuginfo(struct hv_ring_buffer_info *ring_info,
struct hv_ring_buffer_debug_info *debug_info)
{
u32 bytes_avail_towrite;
u32 bytes_avail_toread;
if (ring_info->ring_buffer) {
- get_ringbuffer_availbytes(ring_info,
+ hv_get_ringbuffer_availbytes(ring_info,
&bytes_avail_toread,
&bytes_avail_towrite);
@@ -281,30 +299,26 @@
}
-/*++
-
-Name:
- get_ringbuffer_interrupt_mask()
-
-Description:
- Get the interrupt mask for the specified ring buffer
-
---*/
-u32 get_ringbuffer_interrupt_mask(struct hv_ring_buffer_info *rbi)
+/*
+ *
+ * hv_get_ringbuffer_interrupt_mask()
+ *
+ * Get the interrupt mask for the specified ring buffer
+ *
+ */
+u32 hv_get_ringbuffer_interrupt_mask(struct hv_ring_buffer_info *rbi)
{
return rbi->ring_buffer->interrupt_mask;
}
-/*++
-
-Name:
- ringbuffer_init()
-
-Description:
- Initialize the ring buffer
-
---*/
-int ringbuffer_init(struct hv_ring_buffer_info *ring_info,
+/*
+ *
+ * hv_ringbuffer_init()
+ *
+ *Initialize the ring buffer
+ *
+ */
+int hv_ringbuffer_init(struct hv_ring_buffer_info *ring_info,
void *buffer, u32 buflen)
{
if (sizeof(struct hv_ring_buffer) != PAGE_SIZE)
@@ -324,29 +338,25 @@
return 0;
}
-/*++
-
-Name:
- ringbuffer_cleanup()
-
-Description:
- Cleanup the ring buffer
-
---*/
-void ringbuffer_cleanup(struct hv_ring_buffer_info *ring_info)
+/*
+ *
+ * hv_ringbuffer_cleanup()
+ *
+ * Cleanup the ring buffer
+ *
+ */
+void hv_ringbuffer_cleanup(struct hv_ring_buffer_info *ring_info)
{
}
-/*++
-
-Name:
- ringbuffer_write()
-
-Description:
- Write to the ring buffer
-
---*/
-int ringbuffer_write(struct hv_ring_buffer_info *outring_info,
+/*
+ *
+ * hv_ringbuffer_write()
+ *
+ * Write to the ring buffer
+ *
+ */
+int hv_ringbuffer_write(struct hv_ring_buffer_info *outring_info,
struct scatterlist *sglist, u32 sgcount)
{
int i = 0;
@@ -355,7 +365,7 @@
u32 totalbytes_towrite = 0;
struct scatterlist *sg;
- volatile u32 next_write_location;
+ u32 next_write_location;
u64 prev_indices = 0;
unsigned long flags;
@@ -368,43 +378,34 @@
spin_lock_irqsave(&outring_info->ring_lock, flags);
- get_ringbuffer_availbytes(outring_info,
+ hv_get_ringbuffer_availbytes(outring_info,
&bytes_avail_toread,
&bytes_avail_towrite);
- DPRINT_DBG(VMBUS, "Writing %u bytes...", totalbytes_towrite);
-
- /* Dumpring_info(Outring_info, "BEFORE "); */
/* If there is only room for the packet, assume it is full. */
/* Otherwise, the next time around, we think the ring buffer */
/* is empty since the read index == write index */
if (bytes_avail_towrite <= totalbytes_towrite) {
- DPRINT_DBG(VMBUS,
- "No more space left on outbound ring buffer "
- "(needed %u, avail %u)",
- totalbytes_towrite,
- bytes_avail_towrite);
-
spin_unlock_irqrestore(&outring_info->ring_lock, flags);
return -1;
}
/* Write to the ring buffer */
- next_write_location = get_next_write_location(outring_info);
+ next_write_location = hv_get_next_write_location(outring_info);
for_each_sg(sglist, sg, sgcount, i)
{
- next_write_location = copyto_ringbuffer(outring_info,
+ next_write_location = hv_copyto_ringbuffer(outring_info,
next_write_location,
sg_virt(sg),
sg->length);
}
/* Set previous packet start */
- prev_indices = get_ring_bufferindices(outring_info);
+ prev_indices = hv_get_ring_bufferindices(outring_info);
- next_write_location = copyto_ringbuffer(outring_info,
+ next_write_location = hv_copyto_ringbuffer(outring_info,
next_write_location,
&prev_indices,
sizeof(u64));
@@ -413,25 +414,22 @@
mb();
/* Now, update the write location */
- set_next_write_location(outring_info, next_write_location);
+ hv_set_next_write_location(outring_info, next_write_location);
- /* Dumpring_info(Outring_info, "AFTER "); */
spin_unlock_irqrestore(&outring_info->ring_lock, flags);
return 0;
}
-/*++
-
-Name:
- ringbuffer_peek()
-
-Description:
- Read without advancing the read index
-
---*/
-int ringbuffer_peek(struct hv_ring_buffer_info *Inring_info,
+/*
+ *
+ * hv_ringbuffer_peek()
+ *
+ * Read without advancing the read index
+ *
+ */
+int hv_ringbuffer_peek(struct hv_ring_buffer_info *Inring_info,
void *Buffer, u32 buflen)
{
u32 bytes_avail_towrite;
@@ -441,17 +439,12 @@
spin_lock_irqsave(&Inring_info->ring_lock, flags);
- get_ringbuffer_availbytes(Inring_info,
+ hv_get_ringbuffer_availbytes(Inring_info,
&bytes_avail_toread,
&bytes_avail_towrite);
/* Make sure there is something to read */
if (bytes_avail_toread < buflen) {
- /* DPRINT_DBG(VMBUS,
- "got callback but not enough to read "
- "<avail to read %d read size %d>!!",
- bytes_avail_toread,
- BufferLen); */
spin_unlock_irqrestore(&Inring_info->ring_lock, flags);
@@ -459,9 +452,9 @@
}
/* Convert to byte offset */
- next_read_location = get_next_read_location(Inring_info);
+ next_read_location = hv_get_next_read_location(Inring_info);
- next_read_location = copyfrom_ringbuffer(Inring_info,
+ next_read_location = hv_copyfrom_ringbuffer(Inring_info,
Buffer,
buflen,
next_read_location);
@@ -472,16 +465,14 @@
}
-/*++
-
-Name:
- ringbuffer_read()
-
-Description:
- Read and advance the read index
-
---*/
-int ringbuffer_read(struct hv_ring_buffer_info *inring_info, void *buffer,
+/*
+ *
+ * hv_ringbuffer_read()
+ *
+ * Read and advance the read index
+ *
+ */
+int hv_ringbuffer_read(struct hv_ring_buffer_info *inring_info, void *buffer,
u32 buflen, u32 offset)
{
u32 bytes_avail_towrite;
@@ -495,36 +486,26 @@
spin_lock_irqsave(&inring_info->ring_lock, flags);
- get_ringbuffer_availbytes(inring_info,
+ hv_get_ringbuffer_availbytes(inring_info,
&bytes_avail_toread,
&bytes_avail_towrite);
- DPRINT_DBG(VMBUS, "Reading %u bytes...", buflen);
-
- /* Dumpring_info(Inring_info, "BEFORE "); */
-
/* Make sure there is something to read */
if (bytes_avail_toread < buflen) {
- DPRINT_DBG(VMBUS,
- "got callback but not enough to read "
- "<avail to read %d read size %d>!!",
- bytes_avail_toread,
- buflen);
-
spin_unlock_irqrestore(&inring_info->ring_lock, flags);
return -1;
}
next_read_location =
- get_next_readlocation_withoffset(inring_info, offset);
+ hv_get_next_readlocation_withoffset(inring_info, offset);
- next_read_location = copyfrom_ringbuffer(inring_info,
+ next_read_location = hv_copyfrom_ringbuffer(inring_info,
buffer,
buflen,
next_read_location);
- next_read_location = copyfrom_ringbuffer(inring_info,
+ next_read_location = hv_copyfrom_ringbuffer(inring_info,
&prev_indices,
sizeof(u64),
next_read_location);
@@ -535,94 +516,9 @@
mb();
/* Update the read index */
- set_next_read_location(inring_info, next_read_location);
-
- /* Dumpring_info(Inring_info, "AFTER "); */
+ hv_set_next_read_location(inring_info, next_read_location);
spin_unlock_irqrestore(&inring_info->ring_lock, flags);
return 0;
}
-
-
-/*++
-
-Name:
- copyto_ringbuffer()
-
-Description:
- Helper routine to copy from source to ring buffer.
- Assume there is enough room. Handles wrap-around in dest case only!!
-
---*/
-static u32
-copyto_ringbuffer(
- struct hv_ring_buffer_info *ring_info,
- u32 start_write_offset,
- void *src,
- u32 srclen)
-{
- void *ring_buffer = get_ring_buffer(ring_info);
- u32 ring_buffer_size = get_ring_buffersize(ring_info);
- u32 frag_len;
-
- /* wrap-around detected! */
- if (srclen > ring_buffer_size - start_write_offset) {
- DPRINT_DBG(VMBUS, "wrap-around detected!");
-
- frag_len = ring_buffer_size - start_write_offset;
- memcpy(ring_buffer + start_write_offset, src, frag_len);
- memcpy(ring_buffer, src + frag_len, srclen - frag_len);
- } else
- memcpy(ring_buffer + start_write_offset, src, srclen);
-
- start_write_offset += srclen;
- start_write_offset %= ring_buffer_size;
-
- return start_write_offset;
-}
-
-
-/*++
-
-Name:
- copyfrom_ringbuffer()
-
-Description:
- Helper routine to copy to source from ring buffer.
- Assume there is enough room. Handles wrap-around in src case only!!
-
---*/
-static u32
-copyfrom_ringbuffer(
- struct hv_ring_buffer_info *ring_info,
- void *dest,
- u32 destlen,
- u32 start_read_offset)
-{
- void *ring_buffer = get_ring_buffer(ring_info);
- u32 ring_buffer_size = get_ring_buffersize(ring_info);
-
- u32 frag_len;
-
- /* wrap-around detected at the src */
- if (destlen > ring_buffer_size - start_read_offset) {
- DPRINT_DBG(VMBUS, "src wrap-around detected!");
-
- frag_len = ring_buffer_size - start_read_offset;
-
- memcpy(dest, ring_buffer + start_read_offset, frag_len);
- memcpy(dest + frag_len, ring_buffer, destlen - frag_len);
- } else
-
- memcpy(dest, ring_buffer + start_read_offset, destlen);
-
-
- start_read_offset += destlen;
- start_read_offset %= ring_buffer_size;
-
- return start_read_offset;
-}
-
-
-/* eof */
diff --git a/drivers/staging/hv/ring_buffer.h b/drivers/staging/hv/ring_buffer.h
deleted file mode 100644
index 7bf20d6..0000000
--- a/drivers/staging/hv/ring_buffer.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- *
- * Copyright (c) 2009, Microsoft Corporation.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
- * Place - Suite 330, Boston, MA 02111-1307 USA.
- *
- * Authors:
- * Haiyang Zhang <haiyangz@microsoft.com>
- * Hank Janssen <hjanssen@microsoft.com>
- *
- */
-
-
-#ifndef _RING_BUFFER_H_
-#define _RING_BUFFER_H_
-
-#include <linux/scatterlist.h>
-
-struct hv_ring_buffer {
- /* Offset in bytes from the start of ring data below */
- volatile u32 write_index;
-
- /* Offset in bytes from the start of ring data below */
- volatile u32 read_index;
-
- volatile u32 interrupt_mask;
-
- /* Pad it to PAGE_SIZE so that data starts on page boundary */
- u8 reserved[4084];
-
- /* NOTE:
- * The interrupt_mask field is used only for channels but since our
- * vmbus connection also uses this data structure and its data starts
- * here, we commented out this field.
- */
- /* volatile u32 InterruptMask; */
-
- /*
- * Ring data starts here + RingDataStartOffset
- * !!! DO NOT place any fields below this !!!
- */
- u8 buffer[0];
-} __packed;
-
-struct hv_ring_buffer_info {
- struct hv_ring_buffer *ring_buffer;
- u32 ring_size; /* Include the shared header */
- spinlock_t ring_lock;
-
- u32 ring_datasize; /* < ring_size */
- u32 ring_data_startoffset;
-};
-
-struct hv_ring_buffer_debug_info {
- u32 current_interrupt_mask;
- u32 current_read_index;
- u32 current_write_index;
- u32 bytes_avail_toread;
- u32 bytes_avail_towrite;
-};
-
-
-
-/* Interface */
-
-
-int ringbuffer_init(struct hv_ring_buffer_info *ring_info, void *buffer,
- u32 buflen);
-
-void ringbuffer_cleanup(struct hv_ring_buffer_info *ring_info);
-
-int ringbuffer_write(struct hv_ring_buffer_info *ring_info,
- struct scatterlist *sglist,
- u32 sgcount);
-
-int ringbuffer_peek(struct hv_ring_buffer_info *ring_info, void *buffer,
- u32 buflen);
-
-int ringbuffer_read(struct hv_ring_buffer_info *ring_info,
- void *buffer,
- u32 buflen,
- u32 offset);
-
-u32 get_ringbuffer_interrupt_mask(struct hv_ring_buffer_info *ring_info);
-
-void dump_ring_info(struct hv_ring_buffer_info *ring_info, char *prefix);
-
-void ringbuffer_get_debuginfo(struct hv_ring_buffer_info *ring_info,
- struct hv_ring_buffer_debug_info *debug_info);
-
-#endif /* _RING_BUFFER_H_ */
diff --git a/drivers/staging/hv/rndis.h b/drivers/staging/hv/rndis.h
deleted file mode 100644
index 014de04..0000000
--- a/drivers/staging/hv/rndis.h
+++ /dev/null
@@ -1,653 +0,0 @@
-/*
- *
- * Copyright (c) 2009, Microsoft Corporation.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
- * Place - Suite 330, Boston, MA 02111-1307 USA.
- *
- * Authors:
- * Haiyang Zhang <haiyangz@microsoft.com>
- * Hank Janssen <hjanssen@microsoft.com>
- *
- */
-
-#ifndef _RNDIS_H_
-#define _RNDIS_H_
-
-/* Status codes */
-
-
-#ifndef STATUS_SUCCESS
-#define STATUS_SUCCESS (0x00000000L)
-#endif
-
-#ifndef STATUS_UNSUCCESSFUL
-#define STATUS_UNSUCCESSFUL (0xC0000001L)
-#endif
-
-#ifndef STATUS_PENDING
-#define STATUS_PENDING (0x00000103L)
-#endif
-
-#ifndef STATUS_INSUFFICIENT_RESOURCES
-#define STATUS_INSUFFICIENT_RESOURCES (0xC000009AL)
-#endif
-
-#ifndef STATUS_BUFFER_OVERFLOW
-#define STATUS_BUFFER_OVERFLOW (0x80000005L)
-#endif
-
-#ifndef STATUS_NOT_SUPPORTED
-#define STATUS_NOT_SUPPORTED (0xC00000BBL)
-#endif
-
-#define RNDIS_STATUS_SUCCESS (STATUS_SUCCESS)
-#define RNDIS_STATUS_PENDING (STATUS_PENDING)
-#define RNDIS_STATUS_NOT_RECOGNIZED (0x00010001L)
-#define RNDIS_STATUS_NOT_COPIED (0x00010002L)
-#define RNDIS_STATUS_NOT_ACCEPTED (0x00010003L)
-#define RNDIS_STATUS_CALL_ACTIVE (0x00010007L)
-
-#define RNDIS_STATUS_ONLINE (0x40010003L)
-#define RNDIS_STATUS_RESET_START (0x40010004L)
-#define RNDIS_STATUS_RESET_END (0x40010005L)
-#define RNDIS_STATUS_RING_STATUS (0x40010006L)
-#define RNDIS_STATUS_CLOSED (0x40010007L)
-#define RNDIS_STATUS_WAN_LINE_UP (0x40010008L)
-#define RNDIS_STATUS_WAN_LINE_DOWN (0x40010009L)
-#define RNDIS_STATUS_WAN_FRAGMENT (0x4001000AL)
-#define RNDIS_STATUS_MEDIA_CONNECT (0x4001000BL)
-#define RNDIS_STATUS_MEDIA_DISCONNECT (0x4001000CL)
-#define RNDIS_STATUS_HARDWARE_LINE_UP (0x4001000DL)
-#define RNDIS_STATUS_HARDWARE_LINE_DOWN (0x4001000EL)
-#define RNDIS_STATUS_INTERFACE_UP (0x4001000FL)
-#define RNDIS_STATUS_INTERFACE_DOWN (0x40010010L)
-#define RNDIS_STATUS_MEDIA_BUSY (0x40010011L)
-#define RNDIS_STATUS_MEDIA_SPECIFIC_INDICATION (0x40010012L)
-#define RNDIS_STATUS_WW_INDICATION RDIA_SPECIFIC_INDICATION
-#define RNDIS_STATUS_LINK_SPEED_CHANGE (0x40010013L)
-
-#define RNDIS_STATUS_NOT_RESETTABLE (0x80010001L)
-#define RNDIS_STATUS_SOFT_ERRORS (0x80010003L)
-#define RNDIS_STATUS_HARD_ERRORS (0x80010004L)
-#define RNDIS_STATUS_BUFFER_OVERFLOW (STATUS_BUFFER_OVERFLOW)
-
-#define RNDIS_STATUS_FAILURE (STATUS_UNSUCCESSFUL)
-#define RNDIS_STATUS_RESOURCES (STATUS_INSUFFICIENT_RESOURCES)
-#define RNDIS_STATUS_CLOSING (0xC0010002L)
-#define RNDIS_STATUS_BAD_VERSION (0xC0010004L)
-#define RNDIS_STATUS_BAD_CHARACTERISTICS (0xC0010005L)
-#define RNDIS_STATUS_ADAPTER_NOT_FOUND (0xC0010006L)
-#define RNDIS_STATUS_OPEN_FAILED (0xC0010007L)
-#define RNDIS_STATUS_DEVICE_FAILED (0xC0010008L)
-#define RNDIS_STATUS_MULTICAST_FULL (0xC0010009L)
-#define RNDIS_STATUS_MULTICAST_EXISTS (0xC001000AL)
-#define RNDIS_STATUS_MULTICAST_NOT_FOUND (0xC001000BL)
-#define RNDIS_STATUS_REQUEST_ABORTED (0xC001000CL)
-#define RNDIS_STATUS_RESET_IN_PROGRESS (0xC001000DL)
-#define RNDIS_STATUS_CLOSING_INDICATING (0xC001000EL)
-#define RNDIS_STATUS_NOT_SUPPORTED (STATUS_NOT_SUPPORTED)
-#define RNDIS_STATUS_INVALID_PACKET (0xC001000FL)
-#define RNDIS_STATUS_OPEN_LIST_FULL (0xC0010010L)
-#define RNDIS_STATUS_ADAPTER_NOT_READY (0xC0010011L)
-#define RNDIS_STATUS_ADAPTER_NOT_OPEN (0xC0010012L)
-#define RNDIS_STATUS_NOT_INDICATING (0xC0010013L)
-#define RNDIS_STATUS_INVALID_LENGTH (0xC0010014L)
-#define RNDIS_STATUS_INVALID_DATA (0xC0010015L)
-#define RNDIS_STATUS_BUFFER_TOO_SHORT (0xC0010016L)
-#define RNDIS_STATUS_INVALID_OID (0xC0010017L)
-#define RNDIS_STATUS_ADAPTER_REMOVED (0xC0010018L)
-#define RNDIS_STATUS_UNSUPPORTED_MEDIA (0xC0010019L)
-#define RNDIS_STATUS_GROUP_ADDRESS_IN_USE (0xC001001AL)
-#define RNDIS_STATUS_FILE_NOT_FOUND (0xC001001BL)
-#define RNDIS_STATUS_ERROR_READING_FILE (0xC001001CL)
-#define RNDIS_STATUS_ALREADY_MAPPED (0xC001001DL)
-#define RNDIS_STATUS_RESOURCE_CONFLICT (0xC001001EL)
-#define RNDIS_STATUS_NO_CABLE (0xC001001FL)
-
-#define RNDIS_STATUS_INVALID_SAP (0xC0010020L)
-#define RNDIS_STATUS_SAP_IN_USE (0xC0010021L)
-#define RNDIS_STATUS_INVALID_ADDRESS (0xC0010022L)
-#define RNDIS_STATUS_VC_NOT_ACTIVATED (0xC0010023L)
-#define RNDIS_STATUS_DEST_OUT_OF_ORDER (0xC0010024L)
-#define RNDIS_STATUS_VC_NOT_AVAILABLE (0xC0010025L)
-#define RNDIS_STATUS_CELLRATE_NOT_AVAILABLE (0xC0010026L)
-#define RNDIS_STATUS_INCOMPATABLE_QOS (0xC0010027L)
-#define RNDIS_STATUS_AAL_PARAMS_UNSUPPORTED (0xC0010028L)
-#define RNDIS_STATUS_NO_ROUTE_TO_DESTINATION (0xC0010029L)
-
-#define RNDIS_STATUS_TOKEN_RING_OPEN_ERROR (0xC0011000L)
-
-/* Object Identifiers used by NdisRequest Query/Set Information */
-/* General Objects */
-#define RNDIS_OID_GEN_SUPPORTED_LIST 0x00010101
-#define RNDIS_OID_GEN_HARDWARE_STATUS 0x00010102
-#define RNDIS_OID_GEN_MEDIA_SUPPORTED 0x00010103
-#define RNDIS_OID_GEN_MEDIA_IN_USE 0x00010104
-#define RNDIS_OID_GEN_MAXIMUM_LOOKAHEAD 0x00010105
-#define RNDIS_OID_GEN_MAXIMUM_FRAME_SIZE 0x00010106
-#define RNDIS_OID_GEN_LINK_SPEED 0x00010107
-#define RNDIS_OID_GEN_TRANSMIT_BUFFER_SPACE 0x00010108
-#define RNDIS_OID_GEN_RECEIVE_BUFFER_SPACE 0x00010109
-#define RNDIS_OID_GEN_TRANSMIT_BLOCK_SIZE 0x0001010A
-#define RNDIS_OID_GEN_RECEIVE_BLOCK_SIZE 0x0001010B
-#define RNDIS_OID_GEN_VENDOR_ID 0x0001010C
-#define RNDIS_OID_GEN_VENDOR_DESCRIPTION 0x0001010D
-#define RNDIS_OID_GEN_CURRENT_PACKET_FILTER 0x0001010E
-#define RNDIS_OID_GEN_CURRENT_LOOKAHEAD 0x0001010F
-#define RNDIS_OID_GEN_DRIVER_VERSION 0x00010110
-#define RNDIS_OID_GEN_MAXIMUM_TOTAL_SIZE 0x00010111
-#define RNDIS_OID_GEN_PROTOCOL_OPTIONS 0x00010112
-#define RNDIS_OID_GEN_MAC_OPTIONS 0x00010113
-#define RNDIS_OID_GEN_MEDIA_CONNECT_STATUS 0x00010114
-#define RNDIS_OID_GEN_MAXIMUM_SEND_PACKETS 0x00010115
-#define RNDIS_OID_GEN_VENDOR_DRIVER_VERSION 0x00010116
-#define RNDIS_OID_GEN_NETWORK_LAYER_ADDRESSES 0x00010118
-#define RNDIS_OID_GEN_TRANSPORT_HEADER_OFFSET 0x00010119
-#define RNDIS_OID_GEN_MACHINE_NAME 0x0001021A
-#define RNDIS_OID_GEN_RNDIS_CONFIG_PARAMETER 0x0001021B
-
-#define RNDIS_OID_GEN_XMIT_OK 0x00020101
-#define RNDIS_OID_GEN_RCV_OK 0x00020102
-#define RNDIS_OID_GEN_XMIT_ERROR 0x00020103
-#define RNDIS_OID_GEN_RCV_ERROR 0x00020104
-#define RNDIS_OID_GEN_RCV_NO_BUFFER 0x00020105
-
-#define RNDIS_OID_GEN_DIRECTED_BYTES_XMIT 0x00020201
-#define RNDIS_OID_GEN_DIRECTED_FRAMES_XMIT 0x00020202
-#define RNDIS_OID_GEN_MULTICAST_BYTES_XMIT 0x00020203
-#define RNDIS_OID_GEN_MULTICAST_FRAMES_XMIT 0x00020204
-#define RNDIS_OID_GEN_BROADCAST_BYTES_XMIT 0x00020205
-#define RNDIS_OID_GEN_BROADCAST_FRAMES_XMIT 0x00020206
-#define RNDIS_OID_GEN_DIRECTED_BYTES_RCV 0x00020207
-#define RNDIS_OID_GEN_DIRECTED_FRAMES_RCV 0x00020208
-#define RNDIS_OID_GEN_MULTICAST_BYTES_RCV 0x00020209
-#define RNDIS_OID_GEN_MULTICAST_FRAMES_RCV 0x0002020A
-#define RNDIS_OID_GEN_BROADCAST_BYTES_RCV 0x0002020B
-#define RNDIS_OID_GEN_BROADCAST_FRAMES_RCV 0x0002020C
-
-#define RNDIS_OID_GEN_RCV_CRC_ERROR 0x0002020D
-#define RNDIS_OID_GEN_TRANSMIT_QUEUE_LENGTH 0x0002020E
-
-#define RNDIS_OID_GEN_GET_TIME_CAPS 0x0002020F
-#define RNDIS_OID_GEN_GET_NETCARD_TIME 0x00020210
-
-/* These are connection-oriented general OIDs. */
-/* These replace the above OIDs for connection-oriented media. */
-#define RNDIS_OID_GEN_CO_SUPPORTED_LIST 0x00010101
-#define RNDIS_OID_GEN_CO_HARDWARE_STATUS 0x00010102
-#define RNDIS_OID_GEN_CO_MEDIA_SUPPORTED 0x00010103
-#define RNDIS_OID_GEN_CO_MEDIA_IN_USE 0x00010104
-#define RNDIS_OID_GEN_CO_LINK_SPEED 0x00010105
-#define RNDIS_OID_GEN_CO_VENDOR_ID 0x00010106
-#define RNDIS_OID_GEN_CO_VENDOR_DESCRIPTION 0x00010107
-#define RNDIS_OID_GEN_CO_DRIVER_VERSION 0x00010108
-#define RNDIS_OID_GEN_CO_PROTOCOL_OPTIONS 0x00010109
-#define RNDIS_OID_GEN_CO_MAC_OPTIONS 0x0001010A
-#define RNDIS_OID_GEN_CO_MEDIA_CONNECT_STATUS 0x0001010B
-#define RNDIS_OID_GEN_CO_VENDOR_DRIVER_VERSION 0x0001010C
-#define RNDIS_OID_GEN_CO_MINIMUM_LINK_SPEED 0x0001010D
-
-#define RNDIS_OID_GEN_CO_GET_TIME_CAPS 0x00010201
-#define RNDIS_OID_GEN_CO_GET_NETCARD_TIME 0x00010202
-
-/* These are connection-oriented statistics OIDs. */
-#define RNDIS_OID_GEN_CO_XMIT_PDUS_OK 0x00020101
-#define RNDIS_OID_GEN_CO_RCV_PDUS_OK 0x00020102
-#define RNDIS_OID_GEN_CO_XMIT_PDUS_ERROR 0x00020103
-#define RNDIS_OID_GEN_CO_RCV_PDUS_ERROR 0x00020104
-#define RNDIS_OID_GEN_CO_RCV_PDUS_NO_BUFFER 0x00020105
-
-
-#define RNDIS_OID_GEN_CO_RCV_CRC_ERROR 0x00020201
-#define RNDIS_OID_GEN_CO_TRANSMIT_QUEUE_LENGTH 0x00020202
-#define RNDIS_OID_GEN_CO_BYTES_XMIT 0x00020203
-#define RNDIS_OID_GEN_CO_BYTES_RCV 0x00020204
-#define RNDIS_OID_GEN_CO_BYTES_XMIT_OUTSTANDING 0x00020205
-#define RNDIS_OID_GEN_CO_NETCARD_LOAD 0x00020206
-
-/* These are objects for Connection-oriented media call-managers. */
-#define RNDIS_OID_CO_ADD_PVC 0xFF000001
-#define RNDIS_OID_CO_DELETE_PVC 0xFF000002
-#define RNDIS_OID_CO_GET_CALL_INFORMATION 0xFF000003
-#define RNDIS_OID_CO_ADD_ADDRESS 0xFF000004
-#define RNDIS_OID_CO_DELETE_ADDRESS 0xFF000005
-#define RNDIS_OID_CO_GET_ADDRESSES 0xFF000006
-#define RNDIS_OID_CO_ADDRESS_CHANGE 0xFF000007
-#define RNDIS_OID_CO_SIGNALING_ENABLED 0xFF000008
-#define RNDIS_OID_CO_SIGNALING_DISABLED 0xFF000009
-
-/* 802.3 Objects (Ethernet) */
-#define RNDIS_OID_802_3_PERMANENT_ADDRESS 0x01010101
-#define RNDIS_OID_802_3_CURRENT_ADDRESS 0x01010102
-#define RNDIS_OID_802_3_MULTICAST_LIST 0x01010103
-#define RNDIS_OID_802_3_MAXIMUM_LIST_SIZE 0x01010104
-#define RNDIS_OID_802_3_MAC_OPTIONS 0x01010105
-
-#define NDIS_802_3_MAC_OPTION_PRIORITY 0x00000001
-
-#define RNDIS_OID_802_3_RCV_ERROR_ALIGNMENT 0x01020101
-#define RNDIS_OID_802_3_XMIT_ONE_COLLISION 0x01020102
-#define RNDIS_OID_802_3_XMIT_MORE_COLLISIONS 0x01020103
-
-#define RNDIS_OID_802_3_XMIT_DEFERRED 0x01020201
-#define RNDIS_OID_802_3_XMIT_MAX_COLLISIONS 0x01020202
-#define RNDIS_OID_802_3_RCV_OVERRUN 0x01020203
-#define RNDIS_OID_802_3_XMIT_UNDERRUN 0x01020204
-#define RNDIS_OID_802_3_XMIT_HEARTBEAT_FAILURE 0x01020205
-#define RNDIS_OID_802_3_XMIT_TIMES_CRS_LOST 0x01020206
-#define RNDIS_OID_802_3_XMIT_LATE_COLLISIONS 0x01020207
-
-/* Remote NDIS message types */
-#define REMOTE_NDIS_PACKET_MSG 0x00000001
-#define REMOTE_NDIS_INITIALIZE_MSG 0x00000002
-#define REMOTE_NDIS_HALT_MSG 0x00000003
-#define REMOTE_NDIS_QUERY_MSG 0x00000004
-#define REMOTE_NDIS_SET_MSG 0x00000005
-#define REMOTE_NDIS_RESET_MSG 0x00000006
-#define REMOTE_NDIS_INDICATE_STATUS_MSG 0x00000007
-#define REMOTE_NDIS_KEEPALIVE_MSG 0x00000008
-
-#define REMOTE_CONDIS_MP_CREATE_VC_MSG 0x00008001
-#define REMOTE_CONDIS_MP_DELETE_VC_MSG 0x00008002
-#define REMOTE_CONDIS_MP_ACTIVATE_VC_MSG 0x00008005
-#define REMOTE_CONDIS_MP_DEACTIVATE_VC_MSG 0x00008006
-#define REMOTE_CONDIS_INDICATE_STATUS_MSG 0x00008007
-
-/* Remote NDIS message completion types */
-#define REMOTE_NDIS_INITIALIZE_CMPLT 0x80000002
-#define REMOTE_NDIS_QUERY_CMPLT 0x80000004
-#define REMOTE_NDIS_SET_CMPLT 0x80000005
-#define REMOTE_NDIS_RESET_CMPLT 0x80000006
-#define REMOTE_NDIS_KEEPALIVE_CMPLT 0x80000008
-
-#define REMOTE_CONDIS_MP_CREATE_VC_CMPLT 0x80008001
-#define REMOTE_CONDIS_MP_DELETE_VC_CMPLT 0x80008002
-#define REMOTE_CONDIS_MP_ACTIVATE_VC_CMPLT 0x80008005
-#define REMOTE_CONDIS_MP_DEACTIVATE_VC_CMPLT 0x80008006
-
-/*
- * Reserved message type for private communication between lower-layer host
- * driver and remote device, if necessary.
- */
-#define REMOTE_NDIS_BUS_MSG 0xff000001
-
-/* Defines for DeviceFlags in struct rndis_initialize_complete */
-#define RNDIS_DF_CONNECTIONLESS 0x00000001
-#define RNDIS_DF_CONNECTION_ORIENTED 0x00000002
-#define RNDIS_DF_RAW_DATA 0x00000004
-
-/* Remote NDIS medium types. */
-#define RNDIS_MEDIUM_802_3 0x00000000
-#define RNDIS_MEDIUM_802_5 0x00000001
-#define RNDIS_MEDIUM_FDDI 0x00000002
-#define RNDIS_MEDIUM_WAN 0x00000003
-#define RNDIS_MEDIUM_LOCAL_TALK 0x00000004
-#define RNDIS_MEDIUM_ARCNET_RAW 0x00000006
-#define RNDIS_MEDIUM_ARCNET_878_2 0x00000007
-#define RNDIS_MEDIUM_ATM 0x00000008
-#define RNDIS_MEDIUM_WIRELESS_WAN 0x00000009
-#define RNDIS_MEDIUM_IRDA 0x0000000a
-#define RNDIS_MEDIUM_CO_WAN 0x0000000b
-/* Not a real medium, defined as an upper-bound */
-#define RNDIS_MEDIUM_MAX 0x0000000d
-
-
-/* Remote NDIS medium connection states. */
-#define RNDIS_MEDIA_STATE_CONNECTED 0x00000000
-#define RNDIS_MEDIA_STATE_DISCONNECTED 0x00000001
-
-/* Remote NDIS version numbers */
-#define RNDIS_MAJOR_VERSION 0x00000001
-#define RNDIS_MINOR_VERSION 0x00000000
-
-
-/* NdisInitialize message */
-struct rndis_initialize_request {
- u32 req_id;
- u32 major_ver;
- u32 minor_ver;
- u32 max_xfer_size;
-};
-
-/* Response to NdisInitialize */
-struct rndis_initialize_complete {
- u32 req_id;
- u32 status;
- u32 major_ver;
- u32 minor_ver;
- u32 dev_flags;
- u32 medium;
- u32 max_pkt_per_msg;
- u32 max_xfer_size;
- u32 pkt_alignment_factor;
- u32 af_list_offset;
- u32 af_list_size;
-};
-
-/* Call manager devices only: Information about an address family */
-/* supported by the device is appended to the response to NdisInitialize. */
-struct rndis_co_address_family {
- u32 address_family;
- u32 major_ver;
- u32 minor_ver;
-};
-
-/* NdisHalt message */
-struct rndis_halt_request {
- u32 req_id;
-};
-
-/* NdisQueryRequest message */
-struct rndis_query_request {
- u32 req_id;
- u32 oid;
- u32 info_buflen;
- u32 info_buf_offset;
- u32 dev_vc_handle;
-};
-
-/* Response to NdisQueryRequest */
-struct rndis_query_complete {
- u32 req_id;
- u32 status;
- u32 info_buflen;
- u32 info_buf_offset;
-};
-
-/* NdisSetRequest message */
-struct rndis_set_request {
- u32 req_id;
- u32 oid;
- u32 info_buflen;
- u32 info_buf_offset;
- u32 dev_vc_handle;
-};
-
-/* Response to NdisSetRequest */
-struct rndis_set_complete {
- u32 req_id;
- u32 status;
-};
-
-/* NdisReset message */
-struct rndis_reset_request {
- u32 reserved;
-};
-
-/* Response to NdisReset */
-struct rndis_reset_complete {
- u32 status;
- u32 addressing_reset;
-};
-
-/* NdisMIndicateStatus message */
-struct rndis_indicate_status {
- u32 status;
- u32 status_buflen;
- u32 status_buf_offset;
-};
-
-/* Diagnostic information passed as the status buffer in */
-/* struct rndis_indicate_status messages signifying error conditions. */
-struct rndis_diagnostic_info {
- u32 diag_status;
- u32 error_offset;
-};
-
-/* NdisKeepAlive message */
-struct rndis_keepalive_request {
- u32 req_id;
-};
-
-/* Response to NdisKeepAlive */
-struct rndis_keepalive_complete {
- u32 req_id;
- u32 status;
-};
-
-/*
- * Data message. All Offset fields contain byte offsets from the beginning of
- * struct rndis_packet. All Length fields are in bytes. VcHandle is set
- * to 0 for connectionless data, otherwise it contains the VC handle.
- */
-struct rndis_packet {
- u32 data_offset;
- u32 data_len;
- u32 oob_data_offset;
- u32 oob_data_len;
- u32 num_oob_data_elements;
- u32 per_pkt_info_offset;
- u32 per_pkt_info_len;
- u32 vc_handle;
- u32 reserved;
-};
-
-/* Optional Out of Band data associated with a Data message. */
-struct rndis_oobd {
- u32 size;
- u32 type;
- u32 class_info_offset;
-};
-
-/* Packet extension field contents associated with a Data message. */
-struct rndis_per_packet_info {
- u32 size;
- u32 type;
- u32 per_pkt_info_offset;
-};
-
-/* Format of Information buffer passed in a SetRequest for the OID */
-/* OID_GEN_RNDIS_CONFIG_PARAMETER. */
-struct rndis_config_parameter_info {
- u32 parameter_name_offset;
- u32 parameter_name_length;
- u32 parameter_type;
- u32 parameter_value_offset;
- u32 parameter_value_length;
-};
-
-/* Values for ParameterType in struct rndis_config_parameter_info */
-#define RNDIS_CONFIG_PARAM_TYPE_INTEGER 0
-#define RNDIS_CONFIG_PARAM_TYPE_STRING 2
-
-/* CONDIS Miniport messages for connection oriented devices */
-/* that do not implement a call manager. */
-
-/* CoNdisMiniportCreateVc message */
-struct rcondis_mp_create_vc {
- u32 req_id;
- u32 ndis_vc_handle;
-};
-
-/* Response to CoNdisMiniportCreateVc */
-struct rcondis_mp_create_vc_complete {
- u32 req_id;
- u32 dev_vc_handle;
- u32 status;
-};
-
-/* CoNdisMiniportDeleteVc message */
-struct rcondis_mp_delete_vc {
- u32 req_id;
- u32 dev_vc_handle;
-};
-
-/* Response to CoNdisMiniportDeleteVc */
-struct rcondis_mp_delete_vc_complete {
- u32 req_id;
- u32 status;
-};
-
-/* CoNdisMiniportQueryRequest message */
-struct rcondis_mp_query_request {
- u32 req_id;
- u32 request_type;
- u32 oid;
- u32 dev_vc_handle;
- u32 info_buflen;
- u32 info_buf_offset;
-};
-
-/* CoNdisMiniportSetRequest message */
-struct rcondis_mp_set_request {
- u32 req_id;
- u32 request_type;
- u32 oid;
- u32 dev_vc_handle;
- u32 info_buflen;
- u32 info_buf_offset;
-};
-
-/* CoNdisIndicateStatus message */
-struct rcondis_indicate_status {
- u32 ndis_vc_handle;
- u32 status;
- u32 status_buflen;
- u32 status_buf_offset;
-};
-
-/* CONDIS Call/VC parameters */
-struct rcondis_specific_parameters {
- u32 parameter_type;
- u32 parameter_length;
- u32 parameter_lffset;
-};
-
-struct rcondis_media_parameters {
- u32 flags;
- u32 reserved1;
- u32 reserved2;
- struct rcondis_specific_parameters media_specific;
-};
-
-struct rndis_flowspec {
- u32 token_rate;
- u32 token_bucket_size;
- u32 peak_bandwidth;
- u32 latency;
- u32 delay_variation;
- u32 service_type;
- u32 max_sdu_size;
- u32 minimum_policed_size;
-};
-
-struct rcondis_call_manager_parameters {
- struct rndis_flowspec transmit;
- struct rndis_flowspec receive;
- struct rcondis_specific_parameters call_mgr_specific;
-};
-
-/* CoNdisMiniportActivateVc message */
-struct rcondis_mp_activate_vc_request {
- u32 req_id;
- u32 flags;
- u32 dev_vc_handle;
- u32 media_params_offset;
- u32 media_params_length;
- u32 call_mgr_params_offset;
- u32 call_mgr_params_length;
-};
-
-/* Response to CoNdisMiniportActivateVc */
-struct rcondis_mp_activate_vc_complete {
- u32 req_id;
- u32 status;
-};
-
-/* CoNdisMiniportDeactivateVc message */
-struct rcondis_mp_deactivate_vc_request {
- u32 req_id;
- u32 flags;
- u32 dev_vc_handle;
-};
-
-/* Response to CoNdisMiniportDeactivateVc */
-struct rcondis_mp_deactivate_vc_complete {
- u32 req_id;
- u32 status;
-};
-
-
-/* union with all of the RNDIS messages */
-union rndis_message_container {
- struct rndis_packet pkt;
- struct rndis_initialize_request init_req;
- struct rndis_halt_request halt_req;
- struct rndis_query_request query_req;
- struct rndis_set_request set_req;
- struct rndis_reset_request reset_req;
- struct rndis_keepalive_request keep_alive_req;
- struct rndis_indicate_status indicate_status;
- struct rndis_initialize_complete init_complete;
- struct rndis_query_complete query_complete;
- struct rndis_set_complete set_complete;
- struct rndis_reset_complete reset_complete;
- struct rndis_keepalive_complete keep_alive_complete;
- struct rcondis_mp_create_vc co_miniport_create_vc;
- struct rcondis_mp_delete_vc co_miniport_delete_vc;
- struct rcondis_indicate_status co_indicate_status;
- struct rcondis_mp_activate_vc_request co_miniport_activate_vc;
- struct rcondis_mp_deactivate_vc_request co_miniport_deactivate_vc;
- struct rcondis_mp_create_vc_complete co_miniport_create_vc_complete;
- struct rcondis_mp_delete_vc_complete co_miniport_delete_vc_complete;
- struct rcondis_mp_activate_vc_complete co_miniport_activate_vc_complete;
- struct rcondis_mp_deactivate_vc_complete
- co_miniport_deactivate_vc_complete;
-};
-
-/* Remote NDIS message format */
-struct rndis_message {
- u32 ndis_msg_type;
-
- /* Total length of this message, from the beginning */
- /* of the sruct rndis_message, in bytes. */
- u32 msg_len;
-
- /* Actual message */
- union rndis_message_container msg;
-};
-
-/* Handy macros */
-
-/* get the size of an RNDIS message. Pass in the message type, */
-/* struct rndis_set_request, struct rndis_packet for example */
-#define RNDIS_MESSAGE_SIZE(msg) \
- (sizeof(msg) + (sizeof(struct rndis_message) - \
- sizeof(union rndis_message_container)))
-
-/* get pointer to info buffer with message pointer */
-#define MESSAGE_TO_INFO_BUFFER(msg) \
- (((unsigned char *)(msg)) + msg->info_buf_offset)
-
-/* get pointer to status buffer with message pointer */
-#define MESSAGE_TO_STATUS_BUFFER(msg) \
- (((unsigned char *)(msg)) + msg->status_buf_offset)
-
-/* get pointer to OOBD buffer with message pointer */
-#define MESSAGE_TO_OOBD_BUFFER(msg) \
- (((unsigned char *)(msg)) + msg->oob_data_offset)
-
-/* get pointer to data buffer with message pointer */
-#define MESSAGE_TO_DATA_BUFFER(msg) \
- (((unsigned char *)(msg)) + msg->per_pkt_info_offset)
-
-/* get pointer to contained message from NDIS_MESSAGE pointer */
-#define RNDIS_MESSAGE_PTR_TO_MESSAGE_PTR(rndis_msg) \
- ((void *) &rndis_msg->msg)
-
-/* get pointer to contained message from NDIS_MESSAGE pointer */
-#define RNDIS_MESSAGE_RAW_PTR_TO_MESSAGE_PTR(rndis_msg) \
- ((void *) rndis_msg)
-
-#endif /* _RNDIS_H_ */
diff --git a/drivers/staging/hv/rndis_filter.c b/drivers/staging/hv/rndis_filter.c
index 048376b..60ebdb1 100644
--- a/drivers/staging/hv/rndis_filter.c
+++ b/drivers/staging/hv/rndis_filter.c
@@ -25,17 +25,11 @@
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/if_ether.h>
+#include <linux/netdevice.h>
-#include "logging.h"
-#include "hv_api.h"
-#include "netvsc_api.h"
-#include "rndis_filter.h"
+#include "hyperv.h"
+#include "hyperv_net.h"
-/* Data types */
-struct rndis_filter_driver_object {
- /* The original driver */
- struct netvsc_driver inner_drv;
-};
enum rndis_device_state {
RNDIS_DEV_UNINITIALIZED = 0,
@@ -59,8 +53,7 @@
struct rndis_request {
struct list_head list_ent;
- int wait_condition;
- wait_queue_head_t wait_event;
+ struct completion wait_event;
/*
* FIXME: We assumed a fixed size response here. If we do ever need to
@@ -76,31 +69,11 @@
struct rndis_message request_msg;
};
-
-struct rndis_filter_packet {
- void *completion_ctx;
- void (*completion)(void *context);
- struct rndis_message msg;
-};
-
-
-static int rndis_filte_device_add(struct hv_device *dev,
- void *additional_info);
-
-static int rndis_filter_device_remove(struct hv_device *dev);
-
-static void rndis_filter_cleanup(struct hv_driver *drv);
-
-static int rndis_filter_send(struct hv_device *dev,
- struct hv_netvsc_packet *pkt);
-
static void rndis_filter_send_completion(void *ctx);
static void rndis_filter_send_request_completion(void *ctx);
-/* The one and only */
-static struct rndis_filter_driver_object rndis_filter;
static struct rndis_device *get_rndis_device(void)
{
@@ -132,7 +105,7 @@
if (!request)
return NULL;
- init_waitqueue_head(&request->wait_event);
+ init_completion(&request->wait_event);
rndis_msg = &request->request_msg;
rndis_msg->ndis_msg_type = msg_type;
@@ -264,7 +237,7 @@
rndis_filter_send_request_completion;
packet->completion.send.send_completion_tid = (unsigned long)dev;
- ret = rndis_filter.inner_drv.send(dev->net_dev->dev, packet);
+ ret = netvsc_send(dev->net_dev->dev, packet);
return ret;
}
@@ -283,14 +256,6 @@
*/
if (request->request_msg.msg.init_req.req_id
== resp->msg.init_complete.req_id) {
- DPRINT_DBG(NETVSC, "found rndis request for "
- "this response (id 0x%x req type 0x%x res "
- "type 0x%x)",
- request->request_msg.msg.
- init_req.req_id,
- request->request_msg.ndis_msg_type,
- resp->ndis_msg_type);
-
found = true;
break;
}
@@ -302,10 +267,11 @@
memcpy(&request->response_msg, resp,
resp->msg_len);
} else {
- DPRINT_ERR(NETVSC, "rndis response buffer overflow "
- "detected (size %u max %zu)",
- resp->msg_len,
- sizeof(struct rndis_filter_packet));
+ dev_err(&dev->net_dev->dev->device,
+ "rndis response buffer overflow "
+ "detected (size %u max %zu)\n",
+ resp->msg_len,
+ sizeof(struct rndis_filter_packet));
if (resp->ndis_msg_type ==
REMOTE_NDIS_RESET_CMPLT) {
@@ -319,13 +285,13 @@
}
}
- request->wait_condition = 1;
- wake_up(&request->wait_event);
+ complete(&request->wait_event);
} else {
- DPRINT_ERR(NETVSC, "no rndis request found for this response "
- "(id 0x%x res type 0x%x)",
- resp->msg.init_complete.req_id,
- resp->ndis_msg_type);
+ dev_err(&dev->net_dev->dev->device,
+ "no rndis request found for this response "
+ "(id 0x%x res type 0x%x)\n",
+ resp->msg.init_complete.req_id,
+ resp->ndis_msg_type);
}
}
@@ -336,10 +302,10 @@
&resp->msg.indicate_status;
if (indicate->status == RNDIS_STATUS_MEDIA_CONNECT) {
- rndis_filter.inner_drv.link_status_change(
+ netvsc_linkstatus_callback(
dev->net_dev->dev, 1);
} else if (indicate->status == RNDIS_STATUS_MEDIA_DISCONNECT) {
- rndis_filter.inner_drv.link_status_change(
+ netvsc_linkstatus_callback(
dev->net_dev->dev, 0);
} else {
/*
@@ -371,11 +337,10 @@
pkt->is_data_pkt = true;
- rndis_filter.inner_drv.recv_cb(dev->net_dev->dev,
- pkt);
+ netvsc_recv_callback(dev->net_dev->dev, pkt);
}
-static int rndis_filter_receive(struct hv_device *dev,
+int rndis_filter_receive(struct hv_device *dev,
struct hv_netvsc_packet *pkt)
{
struct netvsc_device *net_dev = dev->ext;
@@ -388,15 +353,15 @@
/* Make sure the rndis device state is initialized */
if (!net_dev->extension) {
- DPRINT_ERR(NETVSC, "got rndis message but no rndis device..."
- "dropping this message!");
+ dev_err(&dev->device, "got rndis message but no rndis device - "
+ "dropping this message!\n");
return -1;
}
rndis_dev = (struct rndis_device *)net_dev->extension;
if (rndis_dev->state == RNDIS_DEV_UNINITIALIZED) {
- DPRINT_ERR(NETVSC, "got rndis message but rndis device "
- "uninitialized...dropping this message!");
+ dev_err(&dev->device, "got rndis message but rndis device "
+ "uninitialized...dropping this message!\n");
return -1;
}
@@ -417,8 +382,8 @@
kunmap_atomic(rndis_hdr - pkt->page_buf[0].offset,
KM_IRQ0);
- DPRINT_ERR(NETVSC, "invalid rndis message? (expected %u "
- "bytes got %u)...dropping this message!",
+ dev_err(&dev->device, "invalid rndis message? (expected %u "
+ "bytes got %u)...dropping this message!\n",
rndis_hdr->msg_len,
pkt->total_data_buflen);
return -1;
@@ -427,8 +392,8 @@
if ((rndis_hdr->ndis_msg_type != REMOTE_NDIS_PACKET_MSG) &&
(rndis_hdr->msg_len > sizeof(struct rndis_message))) {
- DPRINT_ERR(NETVSC, "incoming rndis message buffer overflow "
- "detected (got %u, max %zu)...marking it an error!",
+ dev_err(&dev->device, "incoming rndis message buffer overflow "
+ "detected (got %u, max %zu)..marking it an error!\n",
rndis_hdr->msg_len,
sizeof(struct rndis_message));
}
@@ -460,7 +425,8 @@
rndis_filter_receive_indicate_status(rndis_dev, &rndis_msg);
break;
default:
- DPRINT_ERR(NETVSC, "unhandled rndis message (type %u len %u)",
+ dev_err(&dev->device,
+ "unhandled rndis message (type %u len %u)\n",
rndis_msg.ndis_msg_type,
rndis_msg.msg_len);
break;
@@ -477,6 +443,7 @@
struct rndis_query_request *query;
struct rndis_query_complete *query_complete;
int ret = 0;
+ int t;
if (!result)
return -EINVAL;
@@ -496,14 +463,12 @@
query->info_buflen = 0;
query->dev_vc_handle = 0;
- request->wait_condition = 0;
ret = rndis_filter_send_request(dev, request);
if (ret != 0)
goto Cleanup;
- wait_event_timeout(request->wait_event, request->wait_condition,
- msecs_to_jiffies(1000));
- if (request->wait_condition == 0) {
+ t = wait_for_completion_timeout(&request->wait_event, HZ);
+ if (t == 0) {
ret = -ETIMEDOUT;
goto Cleanup;
}
@@ -555,7 +520,7 @@
struct rndis_set_request *set;
struct rndis_set_complete *set_complete;
u32 status;
- int ret;
+ int ret, t;
request = get_rndis_request(dev, REMOTE_NDIS_SET_MSG,
RNDIS_MESSAGE_SIZE(struct rndis_set_request) +
@@ -574,16 +539,16 @@
memcpy((void *)(unsigned long)set + sizeof(struct rndis_set_request),
&new_filter, sizeof(u32));
- request->wait_condition = 0;
ret = rndis_filter_send_request(dev, request);
if (ret != 0)
goto Cleanup;
- wait_event_timeout(request->wait_event, request->wait_condition,
- msecs_to_jiffies(2000));
- if (request->wait_condition == 0) {
+ t = wait_for_completion_timeout(&request->wait_event, HZ);
+
+ if (t == 0) {
ret = -1;
- DPRINT_ERR(NETVSC, "timeout before we got a set response...");
+ dev_err(&dev->net_dev->dev->device,
+ "timeout before we got a set response...\n");
/*
* We can't deallocate the request since we may still receive a
* send completion for it.
@@ -603,42 +568,6 @@
return ret;
}
-int rndis_filter_init(struct netvsc_driver *drv)
-{
- DPRINT_DBG(NETVSC, "sizeof(struct rndis_filter_packet) == %zd",
- sizeof(struct rndis_filter_packet));
-
- drv->req_ext_size = sizeof(struct rndis_filter_packet);
-
- /* Driver->Context = rndisDriver; */
-
- memset(&rndis_filter, 0, sizeof(struct rndis_filter_driver_object));
-
- /*rndisDriver->Driver = Driver;
-
- ASSERT(Driver->OnLinkStatusChanged);
- rndisDriver->OnLinkStatusChanged = Driver->OnLinkStatusChanged;*/
-
- /* Save the original dispatch handlers before we override it */
- rndis_filter.inner_drv.base.dev_add = drv->base.dev_add;
- rndis_filter.inner_drv.base.dev_rm =
- drv->base.dev_rm;
- rndis_filter.inner_drv.base.cleanup = drv->base.cleanup;
-
- rndis_filter.inner_drv.send = drv->send;
- rndis_filter.inner_drv.recv_cb = drv->recv_cb;
- rndis_filter.inner_drv.link_status_change =
- drv->link_status_change;
-
- /* Override */
- drv->base.dev_add = rndis_filte_device_add;
- drv->base.dev_rm = rndis_filter_device_remove;
- drv->base.cleanup = rndis_filter_cleanup;
- drv->send = rndis_filter_send;
- drv->recv_cb = rndis_filter_receive;
-
- return 0;
-}
static int rndis_filter_init_device(struct rndis_device *dev)
{
@@ -646,7 +575,7 @@
struct rndis_initialize_request *init;
struct rndis_initialize_complete *init_complete;
u32 status;
- int ret;
+ int ret, t;
request = get_rndis_request(dev, REMOTE_NDIS_INITIALIZE_MSG,
RNDIS_MESSAGE_SIZE(struct rndis_initialize_request));
@@ -664,7 +593,6 @@
dev->state = RNDIS_DEV_INITIALIZING;
- request->wait_condition = 0;
ret = rndis_filter_send_request(dev, request);
if (ret != 0) {
dev->state = RNDIS_DEV_UNINITIALIZED;
@@ -672,9 +600,9 @@
}
- wait_event_timeout(request->wait_event, request->wait_condition,
- msecs_to_jiffies(1000));
- if (request->wait_condition == 0) {
+ t = wait_for_completion_timeout(&request->wait_event, HZ);
+
+ if (t == 0) {
ret = -ETIMEDOUT;
goto Cleanup;
}
@@ -753,7 +681,7 @@
return ret;
}
-static int rndis_filte_device_add(struct hv_device *dev,
+int rndis_filte_device_add(struct hv_device *dev,
void *additional_info)
{
int ret;
@@ -765,14 +693,12 @@
if (!rndisDevice)
return -1;
- DPRINT_DBG(NETVSC, "rndis device object allocated - %p", rndisDevice);
-
/*
* Let the inner driver handle this first to create the netvsc channel
* NOTE! Once the channel is created, we may get a receive callback
* (RndisFilterOnReceive()) before this call is completed
*/
- ret = rndis_filter.inner_drv.base.dev_add(dev, additional_info);
+ ret = netvsc_device_add(dev, additional_info);
if (ret != 0) {
kfree(rndisDevice);
return ret;
@@ -802,21 +728,20 @@
*/
}
- DPRINT_INFO(NETVSC, "Device 0x%p mac addr %pM",
- rndisDevice, rndisDevice->hw_mac_adr);
-
memcpy(deviceInfo->mac_adr, rndisDevice->hw_mac_adr, ETH_ALEN);
rndis_filter_query_device_link_status(rndisDevice);
deviceInfo->link_state = rndisDevice->link_stat;
- DPRINT_INFO(NETVSC, "Device 0x%p link state %s", rndisDevice,
- ((deviceInfo->link_state) ? ("down") : ("up")));
+
+ dev_info(&dev->device, "Device MAC %pM link state %s",
+ rndisDevice->hw_mac_adr,
+ ((deviceInfo->link_state) ? ("down\n") : ("up\n")));
return ret;
}
-static int rndis_filter_device_remove(struct hv_device *dev)
+int rndis_filter_device_remove(struct hv_device *dev)
{
struct netvsc_device *net_dev = dev->ext;
struct rndis_device *rndis_dev = net_dev->extension;
@@ -827,15 +752,11 @@
kfree(rndis_dev);
net_dev->extension = NULL;
- /* Pass control to inner driver to remove the device */
- rndis_filter.inner_drv.base.dev_rm(dev);
+ netvsc_device_remove(dev);
return 0;
}
-static void rndis_filter_cleanup(struct hv_driver *drv)
-{
-}
int rndis_filter_open(struct hv_device *dev)
{
@@ -857,7 +778,7 @@
return rndis_filter_close_device(netDevice->extension);
}
-static int rndis_filter_send(struct hv_device *dev,
+int rndis_filter_send(struct hv_device *dev,
struct hv_netvsc_packet *pkt)
{
int ret;
@@ -897,7 +818,7 @@
pkt->completion.send.send_completion = rndis_filter_send_completion;
pkt->completion.send.send_completion_ctx = filterPacket;
- ret = rndis_filter.inner_drv.send(dev, pkt);
+ ret = netvsc_send(dev, pkt);
if (ret != 0) {
/*
* Reset the completion to originals to allow retries from
diff --git a/drivers/staging/hv/rndis_filter.h b/drivers/staging/hv/rndis_filter.h
deleted file mode 100644
index 4da18f3..0000000
--- a/drivers/staging/hv/rndis_filter.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- *
- * Copyright (c) 2009, Microsoft Corporation.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
- * Place - Suite 330, Boston, MA 02111-1307 USA.
- *
- * Authors:
- * Haiyang Zhang <haiyangz@microsoft.com>
- * Hank Janssen <hjanssen@microsoft.com>
- *
- */
-
-
-#ifndef _RNDISFILTER_H_
-#define _RNDISFILTER_H_
-
-#define __struct_bcount(x)
-
-#include "netvsc.h"
-
-#include "rndis.h"
-
-#define RNDIS_HEADER_SIZE (sizeof(struct rndis_message) - \
- sizeof(union rndis_message_container))
-
-#define NDIS_PACKET_TYPE_DIRECTED 0x00000001
-#define NDIS_PACKET_TYPE_MULTICAST 0x00000002
-#define NDIS_PACKET_TYPE_ALL_MULTICAST 0x00000004
-#define NDIS_PACKET_TYPE_BROADCAST 0x00000008
-#define NDIS_PACKET_TYPE_SOURCE_ROUTING 0x00000010
-#define NDIS_PACKET_TYPE_PROMISCUOUS 0x00000020
-#define NDIS_PACKET_TYPE_SMT 0x00000040
-#define NDIS_PACKET_TYPE_ALL_LOCAL 0x00000080
-#define NDIS_PACKET_TYPE_GROUP 0x00000100
-#define NDIS_PACKET_TYPE_ALL_FUNCTIONAL 0x00000200
-#define NDIS_PACKET_TYPE_FUNCTIONAL 0x00000400
-#define NDIS_PACKET_TYPE_MAC_FRAME 0x00000800
-
-
-/* Interface */
-
-extern int rndis_filter_init(struct netvsc_driver *driver);
-
-#endif /* _RNDISFILTER_H_ */
diff --git a/drivers/staging/hv/storvsc.c b/drivers/staging/hv/storvsc.c
index e2ad729..06cd327 100644
--- a/drivers/staging/hv/storvsc.c
+++ b/drivers/staging/hv/storvsc.c
@@ -17,71 +17,19 @@
* Authors:
* Haiyang Zhang <haiyangz@microsoft.com>
* Hank Janssen <hjanssen@microsoft.com>
+ * K. Y. Srinivasan <kys@microsoft.com>
+ *
*/
#include <linux/kernel.h>
#include <linux/sched.h>
-#include <linux/wait.h>
+#include <linux/completion.h>
#include <linux/string.h>
#include <linux/slab.h>
#include <linux/mm.h>
#include <linux/delay.h>
-#include "hv_api.h"
-#include "logging.h"
-#include "storvsc_api.h"
-#include "vmbus_packet_format.h"
-#include "vstorage.h"
-#include "channel.h"
-
-struct storvsc_request_extension {
- /* LIST_ENTRY ListEntry; */
-
- struct hv_storvsc_request *request;
- struct hv_device *device;
-
- /* Synchronize the request/response if needed */
- int wait_condition;
- wait_queue_head_t wait_event;
-
- struct vstor_packet vstor_packet;
-};
-
-/* A storvsc device is a device object that contains a vmbus channel */
-struct storvsc_device {
- struct hv_device *device;
-
- /* 0 indicates the device is being destroyed */
- atomic_t ref_count;
-
- atomic_t num_outstanding_req;
-
- /*
- * Each unique Port/Path/Target represents 1 channel ie scsi
- * controller. In reality, the pathid, targetid is always 0
- * and the port is set by us
- */
- unsigned int port_number;
- unsigned char path_id;
- unsigned char target_id;
-
- /* LIST_ENTRY OutstandingRequestList; */
- /* HANDLE OutstandingRequestLock; */
-
- /* Used for vsc/vsp channel reset process */
- struct storvsc_request_extension init_request;
- struct storvsc_request_extension reset_request;
-};
-
-
-static const char *g_driver_name = "storvsc";
-
-/* {ba6163d9-04a1-4d29-b605-72e2ffb1dc7f} */
-static const struct hv_guid gStorVscDeviceType = {
- .data = {
- 0xd9, 0x63, 0x61, 0xba, 0xa1, 0x04, 0x29, 0x4d,
- 0xb6, 0x05, 0x72, 0xe2, 0xff, 0xb1, 0xdc, 0x7f
- }
-};
+#include "hyperv.h"
+#include "hyperv_storage.h"
static inline struct storvsc_device *alloc_stor_device(struct hv_device *device)
@@ -96,6 +44,7 @@
/* (ie get_stor_device() and must_get_stor_device()) to proceed. */
atomic_cmpxchg(&stor_device->ref_count, 0, 2);
+ init_waitqueue_head(&stor_device->waiting_to_drain);
stor_device->device = device;
device->ext = stor_device;
@@ -104,24 +53,9 @@
static inline void free_stor_device(struct storvsc_device *device)
{
- /* ASSERT(atomic_read(&device->ref_count) == 0); */
kfree(device);
}
-/* Get the stordevice object iff exists and its refcount > 1 */
-static inline struct storvsc_device *get_stor_device(struct hv_device *device)
-{
- struct storvsc_device *stor_device;
-
- stor_device = (struct storvsc_device *)device->ext;
- if (stor_device && atomic_read(&stor_device->ref_count) > 1)
- atomic_inc(&stor_device->ref_count);
- else
- stor_device = NULL;
-
- return stor_device;
-}
-
/* Get the stordevice object iff exists and its refcount > 0 */
static inline struct storvsc_device *must_get_stor_device(
struct hv_device *device)
@@ -137,17 +71,6 @@
return stor_device;
}
-static inline void put_stor_device(struct hv_device *device)
-{
- struct storvsc_device *stor_device;
-
- stor_device = (struct storvsc_device *)device->ext;
- /* ASSERT(stor_device); */
-
- atomic_dec(&stor_device->ref_count);
- /* ASSERT(atomic_read(&stor_device->ref_count)); */
-}
-
/* Drop ref count to 1 to effectively disable get_stor_device() */
static inline struct storvsc_device *release_stor_device(
struct hv_device *device)
@@ -155,7 +78,6 @@
struct storvsc_device *stor_device;
stor_device = (struct storvsc_device *)device->ext;
- /* ASSERT(stor_device); */
/* Busy wait until the ref drop to 2, then set it to 1 */
while (atomic_cmpxchg(&stor_device->ref_count, 2, 1) != 2)
@@ -171,7 +93,6 @@
struct storvsc_device *stor_device;
stor_device = (struct storvsc_device *)device->ext;
- /* ASSERT(stor_device); */
/* Busy wait until the ref drop to 1, then set it to 0 */
while (atomic_cmpxchg(&stor_device->ref_count, 1, 0) != 1)
@@ -181,19 +102,16 @@
return stor_device;
}
-static int stor_vsc_channel_init(struct hv_device *device)
+static int storvsc_channel_init(struct hv_device *device)
{
struct storvsc_device *stor_device;
- struct storvsc_request_extension *request;
+ struct hv_storvsc_request *request;
struct vstor_packet *vstor_packet;
- int ret;
+ int ret, t;
stor_device = get_stor_device(device);
- if (!stor_device) {
- DPRINT_ERR(STORVSC, "unable to get stor device..."
- "device being destroyed?");
+ if (!stor_device)
return -1;
- }
request = &stor_device->init_request;
vstor_packet = &request->vstor_packet;
@@ -202,40 +120,30 @@
* Now, initiate the vsc/vsp initialization protocol on the open
* channel
*/
- memset(request, 0, sizeof(struct storvsc_request_extension));
- init_waitqueue_head(&request->wait_event);
+ memset(request, 0, sizeof(struct hv_storvsc_request));
+ init_completion(&request->wait_event);
vstor_packet->operation = VSTOR_OPERATION_BEGIN_INITIALIZATION;
vstor_packet->flags = REQUEST_COMPLETION_FLAG;
DPRINT_INFO(STORVSC, "BEGIN_INITIALIZATION_OPERATION...");
- request->wait_condition = 0;
ret = vmbus_sendpacket(device->channel, vstor_packet,
sizeof(struct vstor_packet),
(unsigned long)request,
VM_PKT_DATA_INBAND,
VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED);
- if (ret != 0) {
- DPRINT_ERR(STORVSC,
- "unable to send BEGIN_INITIALIZATION_OPERATION");
+ if (ret != 0)
goto cleanup;
- }
- wait_event_timeout(request->wait_event, request->wait_condition,
- msecs_to_jiffies(1000));
- if (request->wait_condition == 0) {
+ t = wait_for_completion_timeout(&request->wait_event, HZ);
+ if (t == 0) {
ret = -ETIMEDOUT;
goto cleanup;
}
-
if (vstor_packet->operation != VSTOR_OPERATION_COMPLETE_IO ||
- vstor_packet->status != 0) {
- DPRINT_ERR(STORVSC, "BEGIN_INITIALIZATION_OPERATION failed "
- "(op %d status 0x%x)",
- vstor_packet->operation, vstor_packet->status);
+ vstor_packet->status != 0)
goto cleanup;
- }
DPRINT_INFO(STORVSC, "QUERY_PROTOCOL_VERSION_OPERATION...");
@@ -247,33 +155,24 @@
vstor_packet->version.major_minor = VMSTOR_PROTOCOL_VERSION_CURRENT;
FILL_VMSTOR_REVISION(vstor_packet->version.revision);
- request->wait_condition = 0;
ret = vmbus_sendpacket(device->channel, vstor_packet,
sizeof(struct vstor_packet),
(unsigned long)request,
VM_PKT_DATA_INBAND,
VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED);
- if (ret != 0) {
- DPRINT_ERR(STORVSC,
- "unable to send BEGIN_INITIALIZATION_OPERATION");
+ if (ret != 0)
goto cleanup;
- }
- wait_event_timeout(request->wait_event, request->wait_condition,
- msecs_to_jiffies(1000));
- if (request->wait_condition == 0) {
+ t = wait_for_completion_timeout(&request->wait_event, HZ);
+ if (t == 0) {
ret = -ETIMEDOUT;
goto cleanup;
}
/* TODO: Check returned version */
if (vstor_packet->operation != VSTOR_OPERATION_COMPLETE_IO ||
- vstor_packet->status != 0) {
- DPRINT_ERR(STORVSC, "QUERY_PROTOCOL_VERSION_OPERATION failed "
- "(op %d status 0x%x)",
- vstor_packet->operation, vstor_packet->status);
+ vstor_packet->status != 0)
goto cleanup;
- }
/* Query channel properties */
DPRINT_INFO(STORVSC, "QUERY_PROPERTIES_OPERATION...");
@@ -284,76 +183,54 @@
vstor_packet->storage_channel_properties.port_number =
stor_device->port_number;
- request->wait_condition = 0;
ret = vmbus_sendpacket(device->channel, vstor_packet,
sizeof(struct vstor_packet),
(unsigned long)request,
VM_PKT_DATA_INBAND,
VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED);
- if (ret != 0) {
- DPRINT_ERR(STORVSC,
- "unable to send QUERY_PROPERTIES_OPERATION");
+ if (ret != 0)
goto cleanup;
- }
- wait_event_timeout(request->wait_event, request->wait_condition,
- msecs_to_jiffies(1000));
- if (request->wait_condition == 0) {
+ t = wait_for_completion_timeout(&request->wait_event, HZ);
+ if (t == 0) {
ret = -ETIMEDOUT;
goto cleanup;
}
/* TODO: Check returned version */
if (vstor_packet->operation != VSTOR_OPERATION_COMPLETE_IO ||
- vstor_packet->status != 0) {
- DPRINT_ERR(STORVSC, "QUERY_PROPERTIES_OPERATION failed "
- "(op %d status 0x%x)",
- vstor_packet->operation, vstor_packet->status);
+ vstor_packet->status != 0)
goto cleanup;
- }
stor_device->path_id = vstor_packet->storage_channel_properties.path_id;
stor_device->target_id
= vstor_packet->storage_channel_properties.target_id;
- DPRINT_DBG(STORVSC, "channel flag 0x%x, max xfer len 0x%x",
- vstor_packet->storage_channel_properties.flags,
- vstor_packet->storage_channel_properties.max_transfer_bytes);
-
DPRINT_INFO(STORVSC, "END_INITIALIZATION_OPERATION...");
memset(vstor_packet, 0, sizeof(struct vstor_packet));
vstor_packet->operation = VSTOR_OPERATION_END_INITIALIZATION;
vstor_packet->flags = REQUEST_COMPLETION_FLAG;
- request->wait_condition = 0;
ret = vmbus_sendpacket(device->channel, vstor_packet,
sizeof(struct vstor_packet),
(unsigned long)request,
VM_PKT_DATA_INBAND,
VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED);
- if (ret != 0) {
- DPRINT_ERR(STORVSC,
- "unable to send END_INITIALIZATION_OPERATION");
+ if (ret != 0)
goto cleanup;
- }
- wait_event_timeout(request->wait_event, request->wait_condition,
- msecs_to_jiffies(1000));
- if (request->wait_condition == 0) {
+ t = wait_for_completion_timeout(&request->wait_event, HZ);
+ if (t == 0) {
ret = -ETIMEDOUT;
goto cleanup;
}
if (vstor_packet->operation != VSTOR_OPERATION_COMPLETE_IO ||
- vstor_packet->status != 0) {
- DPRINT_ERR(STORVSC, "END_INITIALIZATION_OPERATION failed "
- "(op %d status 0x%x)",
- vstor_packet->operation, vstor_packet->status);
+ vstor_packet->status != 0)
goto cleanup;
- }
DPRINT_INFO(STORVSC, "**** storage channel up and running!! ****");
@@ -362,78 +239,70 @@
return ret;
}
-static void stor_vsc_on_io_completion(struct hv_device *device,
+static void storvsc_on_io_completion(struct hv_device *device,
struct vstor_packet *vstor_packet,
- struct storvsc_request_extension *request_ext)
+ struct hv_storvsc_request *request)
{
- struct hv_storvsc_request *request;
struct storvsc_device *stor_device;
+ struct vstor_packet *stor_pkt;
stor_device = must_get_stor_device(device);
- if (!stor_device) {
- DPRINT_ERR(STORVSC, "unable to get stor device..."
- "device being destroyed?");
+ if (!stor_device)
return;
- }
- DPRINT_DBG(STORVSC, "IO_COMPLETE_OPERATION - request extension %p "
- "completed bytes xfer %u", request_ext,
- vstor_packet->vm_srb.data_transfer_length);
+ stor_pkt = &request->vstor_packet;
- /* ASSERT(request_ext != NULL); */
- /* ASSERT(request_ext->request != NULL); */
-
- request = request_ext->request;
-
- /* ASSERT(request->OnIOCompletion != NULL); */
/* Copy over the status...etc */
- request->status = vstor_packet->vm_srb.scsi_status;
+ stor_pkt->vm_srb.scsi_status = vstor_packet->vm_srb.scsi_status;
+ stor_pkt->vm_srb.srb_status = vstor_packet->vm_srb.srb_status;
+ stor_pkt->vm_srb.sense_info_length =
+ vstor_packet->vm_srb.sense_info_length;
- if (request->status != 0 || vstor_packet->vm_srb.srb_status != 1) {
+ if (vstor_packet->vm_srb.scsi_status != 0 ||
+ vstor_packet->vm_srb.srb_status != 1){
DPRINT_WARN(STORVSC,
"cmd 0x%x scsi status 0x%x srb status 0x%x\n",
- request->cdb[0], vstor_packet->vm_srb.scsi_status,
+ stor_pkt->vm_srb.cdb[0],
+ vstor_packet->vm_srb.scsi_status,
vstor_packet->vm_srb.srb_status);
}
- if ((request->status & 0xFF) == 0x02) {
+ if ((vstor_packet->vm_srb.scsi_status & 0xFF) == 0x02) {
/* CHECK_CONDITION */
if (vstor_packet->vm_srb.srb_status & 0x80) {
/* autosense data available */
DPRINT_WARN(STORVSC, "storvsc pkt %p autosense data "
- "valid - len %d\n", request_ext,
+ "valid - len %d\n", request,
vstor_packet->vm_srb.sense_info_length);
- /* ASSERT(vstor_packet->vm_srb.sense_info_length <= */
- /* request->SenseBufferSize); */
memcpy(request->sense_buffer,
vstor_packet->vm_srb.sense_data,
vstor_packet->vm_srb.sense_info_length);
- request->sense_buffer_size =
- vstor_packet->vm_srb.sense_info_length;
}
}
- /* TODO: */
- request->bytes_xfer = vstor_packet->vm_srb.data_transfer_length;
+ stor_pkt->vm_srb.data_transfer_length =
+ vstor_packet->vm_srb.data_transfer_length;
request->on_io_completion(request);
- atomic_dec(&stor_device->num_outstanding_req);
+ if (atomic_dec_and_test(&stor_device->num_outstanding_req) &&
+ stor_device->drain_notify)
+ wake_up(&stor_device->waiting_to_drain);
+
put_stor_device(device);
}
-static void stor_vsc_on_receive(struct hv_device *device,
+static void storvsc_on_receive(struct hv_device *device,
struct vstor_packet *vstor_packet,
- struct storvsc_request_extension *request_ext)
+ struct hv_storvsc_request *request)
{
switch (vstor_packet->operation) {
case VSTOR_OPERATION_COMPLETE_IO:
- DPRINT_DBG(STORVSC, "IO_COMPLETE_OPERATION");
- stor_vsc_on_io_completion(device, vstor_packet, request_ext);
+ storvsc_on_io_completion(device, vstor_packet, request);
break;
case VSTOR_OPERATION_REMOVE_DEVICE:
DPRINT_INFO(STORVSC, "REMOVE_DEVICE_OPERATION");
@@ -447,60 +316,42 @@
}
}
-static void stor_vsc_on_channel_callback(void *context)
+static void storvsc_on_channel_callback(void *context)
{
struct hv_device *device = (struct hv_device *)context;
struct storvsc_device *stor_device;
u32 bytes_recvd;
u64 request_id;
unsigned char packet[ALIGN(sizeof(struct vstor_packet), 8)];
- struct storvsc_request_extension *request;
+ struct hv_storvsc_request *request;
int ret;
- /* ASSERT(device); */
stor_device = must_get_stor_device(device);
- if (!stor_device) {
- DPRINT_ERR(STORVSC, "unable to get stor device..."
- "device being destroyed?");
+ if (!stor_device)
return;
- }
do {
ret = vmbus_recvpacket(device->channel, packet,
ALIGN(sizeof(struct vstor_packet), 8),
&bytes_recvd, &request_id);
if (ret == 0 && bytes_recvd > 0) {
- DPRINT_DBG(STORVSC, "receive %d bytes - tid %llx",
- bytes_recvd, request_id);
- /* ASSERT(bytes_recvd ==
- sizeof(struct vstor_packet)); */
-
- request = (struct storvsc_request_extension *)
+ request = (struct hv_storvsc_request *)
(unsigned long)request_id;
- /* ASSERT(request);c */
- /* if (vstor_packet.Flags & SYNTHETIC_FLAG) */
if ((request == &stor_device->init_request) ||
(request == &stor_device->reset_request)) {
- /* DPRINT_INFO(STORVSC,
- * "reset completion - operation "
- * "%u status %u",
- * vstor_packet.Operation,
- * vstor_packet.Status); */
memcpy(&request->vstor_packet, packet,
sizeof(struct vstor_packet));
- request->wait_condition = 1;
- wake_up(&request->wait_event);
+ complete(&request->wait_event);
} else {
- stor_vsc_on_receive(device,
+ storvsc_on_receive(device,
(struct vstor_packet *)packet,
request);
}
} else {
- /* DPRINT_DBG(STORVSC, "nothing else to read..."); */
break;
}
} while (1);
@@ -509,45 +360,33 @@
return;
}
-static int stor_vsc_connect_to_vsp(struct hv_device *device)
+static int storvsc_connect_to_vsp(struct hv_device *device, u32 ring_size)
{
struct vmstorage_channel_properties props;
- struct storvsc_driver_object *stor_driver;
int ret;
- stor_driver = (struct storvsc_driver_object *)device->drv;
memset(&props, 0, sizeof(struct vmstorage_channel_properties));
/* Open the channel */
ret = vmbus_open(device->channel,
- stor_driver->ring_buffer_size,
- stor_driver->ring_buffer_size,
+ ring_size,
+ ring_size,
(void *)&props,
sizeof(struct vmstorage_channel_properties),
- stor_vsc_on_channel_callback, device);
+ storvsc_on_channel_callback, device);
- DPRINT_DBG(STORVSC, "storage props: path id %d, tgt id %d, max xfer %d",
- props.path_id, props.target_id, props.max_transfer_bytes);
-
- if (ret != 0) {
- DPRINT_ERR(STORVSC, "unable to open channel: %d", ret);
+ if (ret != 0)
return -1;
- }
- ret = stor_vsc_channel_init(device);
+ ret = storvsc_channel_init(device);
return ret;
}
-/*
- * stor_vsc_on_device_add - Callback when the device belonging to this driver
- * is added
- */
-static int stor_vsc_on_device_add(struct hv_device *device,
+int storvsc_dev_add(struct hv_device *device,
void *additional_info)
{
struct storvsc_device *stor_device;
- /* struct vmstorage_channel_properties *props; */
struct storvsc_device_info *device_info;
int ret = 0;
@@ -559,8 +398,6 @@
}
/* Save the channel properties to our storvsc channel */
- /* props = (struct vmstorage_channel_properties *)
- * channel->offerMsg.Offer.u.Standard.UserDefined; */
/* FIXME: */
/*
@@ -569,30 +406,18 @@
* scsi channel prior to the bus scan
*/
- /* storChannel->PortNumber = 0;
- storChannel->PathId = props->PathId;
- storChannel->TargetId = props->TargetId; */
-
stor_device->port_number = device_info->port_number;
/* Send it back up */
- ret = stor_vsc_connect_to_vsp(device);
+ ret = storvsc_connect_to_vsp(device, device_info->ring_buffer_size);
- /* device_info->PortNumber = stor_device->PortNumber; */
device_info->path_id = stor_device->path_id;
device_info->target_id = stor_device->target_id;
- DPRINT_DBG(STORVSC, "assigned port %u, path %u target %u\n",
- stor_device->port_number, stor_device->path_id,
- stor_device->target_id);
-
cleanup:
return ret;
}
-/*
- * stor_vsc_on_device_remove - Callback when the our device is being removed
- */
-static int stor_vsc_on_device_remove(struct hv_device *device)
+int storvsc_dev_remove(struct hv_device *device)
{
struct storvsc_device *stor_device;
@@ -606,19 +431,11 @@
* only allow inbound traffic (responses) to proceed so that
* outstanding requests can be completed.
*/
- while (atomic_read(&stor_device->num_outstanding_req)) {
- DPRINT_INFO(STORVSC, "waiting for %d requests to complete...",
- atomic_read(&stor_device->num_outstanding_req));
- udelay(100);
- }
- DPRINT_INFO(STORVSC, "removing storage device (%p)...",
- device->ext);
+ storvsc_wait_to_drain(stor_device);
stor_device = final_release_stor_device(device);
- DPRINT_INFO(STORVSC, "storage device (%p) safe to remove", stor_device);
-
/* Close the channel */
vmbus_close(device->channel);
@@ -626,148 +443,52 @@
return 0;
}
-int stor_vsc_on_host_reset(struct hv_device *device)
-{
- struct storvsc_device *stor_device;
- struct storvsc_request_extension *request;
- struct vstor_packet *vstor_packet;
- int ret;
-
- DPRINT_INFO(STORVSC, "resetting host adapter...");
-
- stor_device = get_stor_device(device);
- if (!stor_device) {
- DPRINT_ERR(STORVSC, "unable to get stor device..."
- "device being destroyed?");
- return -1;
- }
-
- request = &stor_device->reset_request;
- vstor_packet = &request->vstor_packet;
-
- init_waitqueue_head(&request->wait_event);
-
- vstor_packet->operation = VSTOR_OPERATION_RESET_BUS;
- vstor_packet->flags = REQUEST_COMPLETION_FLAG;
- vstor_packet->vm_srb.path_id = stor_device->path_id;
-
- request->wait_condition = 0;
- ret = vmbus_sendpacket(device->channel, vstor_packet,
- sizeof(struct vstor_packet),
- (unsigned long)&stor_device->reset_request,
- VM_PKT_DATA_INBAND,
- VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED);
- if (ret != 0) {
- DPRINT_ERR(STORVSC, "Unable to send reset packet %p ret %d",
- vstor_packet, ret);
- goto cleanup;
- }
-
- wait_event_timeout(request->wait_event, request->wait_condition,
- msecs_to_jiffies(1000));
- if (request->wait_condition == 0) {
- ret = -ETIMEDOUT;
- goto cleanup;
- }
-
- DPRINT_INFO(STORVSC, "host adapter reset completed");
-
- /*
- * At this point, all outstanding requests in the adapter
- * should have been flushed out and return to us
- */
-
-cleanup:
- put_stor_device(device);
- return ret;
-}
-
-/*
- * stor_vsc_on_io_request - Callback to initiate an I/O request
- */
-static int stor_vsc_on_io_request(struct hv_device *device,
+int storvsc_do_io(struct hv_device *device,
struct hv_storvsc_request *request)
{
struct storvsc_device *stor_device;
- struct storvsc_request_extension *request_extension;
struct vstor_packet *vstor_packet;
int ret = 0;
- request_extension =
- (struct storvsc_request_extension *)request->extension;
- vstor_packet = &request_extension->vstor_packet;
+ vstor_packet = &request->vstor_packet;
stor_device = get_stor_device(device);
- DPRINT_DBG(STORVSC, "enter - Device %p, DeviceExt %p, Request %p, "
- "Extension %p", device, stor_device, request,
- request_extension);
-
- DPRINT_DBG(STORVSC, "req %p len %d bus %d, target %d, lun %d cdblen %d",
- request, request->data_buffer.len, request->bus,
- request->target_id, request->lun_id, request->cdb_len);
-
- if (!stor_device) {
- DPRINT_ERR(STORVSC, "unable to get stor device..."
- "device being destroyed?");
+ if (!stor_device)
return -2;
- }
- /* print_hex_dump_bytes("", DUMP_PREFIX_NONE, request->Cdb,
- * request->CdbLen); */
- request_extension->request = request;
- request_extension->device = device;
+ request->device = device;
- memset(vstor_packet, 0 , sizeof(struct vstor_packet));
vstor_packet->flags |= REQUEST_COMPLETION_FLAG;
vstor_packet->vm_srb.length = sizeof(struct vmscsi_request);
- vstor_packet->vm_srb.port_number = request->host;
- vstor_packet->vm_srb.path_id = request->bus;
- vstor_packet->vm_srb.target_id = request->target_id;
- vstor_packet->vm_srb.lun = request->lun_id;
vstor_packet->vm_srb.sense_info_length = SENSE_BUFFER_SIZE;
- /* Copy over the scsi command descriptor block */
- vstor_packet->vm_srb.cdb_length = request->cdb_len;
- memcpy(&vstor_packet->vm_srb.cdb, request->cdb, request->cdb_len);
- vstor_packet->vm_srb.data_in = request->type;
- vstor_packet->vm_srb.data_transfer_length = request->data_buffer.len;
+ vstor_packet->vm_srb.data_transfer_length =
+ request->data_buffer.len;
vstor_packet->operation = VSTOR_OPERATION_EXECUTE_SRB;
- DPRINT_DBG(STORVSC, "srb - len %d port %d, path %d, target %d, "
- "lun %d senselen %d cdblen %d",
- vstor_packet->vm_srb.length,
- vstor_packet->vm_srb.port_number,
- vstor_packet->vm_srb.path_id,
- vstor_packet->vm_srb.target_id,
- vstor_packet->vm_srb.lun,
- vstor_packet->vm_srb.sense_info_length,
- vstor_packet->vm_srb.cdb_length);
-
- if (request_extension->request->data_buffer.len) {
+ if (request->data_buffer.len) {
ret = vmbus_sendpacket_multipagebuffer(device->channel,
- &request_extension->request->data_buffer,
+ &request->data_buffer,
vstor_packet,
sizeof(struct vstor_packet),
- (unsigned long)request_extension);
+ (unsigned long)request);
} else {
ret = vmbus_sendpacket(device->channel, vstor_packet,
sizeof(struct vstor_packet),
- (unsigned long)request_extension,
+ (unsigned long)request,
VM_PKT_DATA_INBAND,
VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED);
}
- if (ret != 0) {
- DPRINT_DBG(STORVSC, "Unable to send packet %p ret %d",
- vstor_packet, ret);
- }
+ if (ret != 0)
+ return ret;
atomic_inc(&stor_device->num_outstanding_req);
@@ -776,62 +497,68 @@
}
/*
- * stor_vsc_on_cleanup - Perform any cleanup when the driver is removed
+ * The channel properties uniquely specify how the device is to be
+ * presented to the guest. Map this information for use by the block
+ * driver. For Linux guests on Hyper-V, we emulate a scsi HBA in the guest
+ * (storvsc_drv) and so scsi devices in the guest are handled by
+ * native upper level Linux drivers. Consequently, Hyper-V
+ * block driver, while being a generic block driver, presently does not
+ * deal with anything other than devices that would need to be presented
+ * to the guest as an IDE disk.
+ *
+ * This function maps the channel properties as embedded in the input
+ * parameter device_info onto information necessary to register the
+ * corresponding block device.
+ *
+ * Currently, there is no way to stop the emulation of the block device
+ * on the host side. And so, to prevent the native IDE drivers in Linux
+ * from taking over these devices (to be managedby Hyper-V block
+ * driver), we will take over if need be the major of the IDE controllers.
+ *
*/
-static void stor_vsc_on_cleanup(struct hv_driver *driver)
+
+int storvsc_get_major_info(struct storvsc_device_info *device_info,
+ struct storvsc_major_info *major_info)
{
-}
-
-/*
- * stor_vsc_initialize - Main entry point
- */
-int stor_vsc_initialize(struct hv_driver *driver)
-{
- struct storvsc_driver_object *stor_driver;
-
- stor_driver = (struct storvsc_driver_object *)driver;
-
- DPRINT_DBG(STORVSC, "sizeof(STORVSC_REQUEST)=%zd "
- "sizeof(struct storvsc_request_extension)=%zd "
- "sizeof(struct vstor_packet)=%zd, "
- "sizeof(struct vmscsi_request)=%zd",
- sizeof(struct hv_storvsc_request),
- sizeof(struct storvsc_request_extension),
- sizeof(struct vstor_packet),
- sizeof(struct vmscsi_request));
-
- /* Make sure we are at least 2 pages since 1 page is used for control */
- /* ASSERT(stor_driver->RingBufferSize >= (PAGE_SIZE << 1)); */
-
- driver->name = g_driver_name;
- memcpy(&driver->dev_type, &gStorVscDeviceType,
- sizeof(struct hv_guid));
-
- stor_driver->request_ext_size =
- sizeof(struct storvsc_request_extension);
+ static bool ide0_registered;
+ static bool ide1_registered;
/*
- * Divide the ring buffer data size (which is 1 page less
- * than the ring buffer size since that page is reserved for
- * the ring buffer indices) by the max request size (which is
- * vmbus_channel_packet_multipage_buffer + struct vstor_packet + u64)
+ * For now we only support IDE disks.
*/
- stor_driver->max_outstanding_req_per_channel =
- ((stor_driver->ring_buffer_size - PAGE_SIZE) /
- ALIGN(MAX_MULTIPAGE_BUFFER_PACKET +
- sizeof(struct vstor_packet) + sizeof(u64),
- sizeof(u64)));
+ major_info->devname = "ide";
+ major_info->diskname = "hd";
- DPRINT_INFO(STORVSC, "max io %u, currently %u\n",
- stor_driver->max_outstanding_req_per_channel,
- STORVSC_MAX_IO_REQUESTS);
+ if (device_info->path_id) {
+ major_info->major = 22;
+ if (!ide1_registered) {
+ major_info->do_register = true;
+ ide1_registered = true;
+ } else
+ major_info->do_register = false;
- /* Setup the dispatch table */
- stor_driver->base.dev_add = stor_vsc_on_device_add;
- stor_driver->base.dev_rm = stor_vsc_on_device_remove;
- stor_driver->base.cleanup = stor_vsc_on_cleanup;
+ if (device_info->target_id)
+ major_info->index = 3;
+ else
+ major_info->index = 2;
- stor_driver->on_io_request = stor_vsc_on_io_request;
+ return 0;
+ } else {
+ major_info->major = 3;
+ if (!ide0_registered) {
+ major_info->do_register = true;
+ ide0_registered = true;
+ } else
+ major_info->do_register = false;
- return 0;
+ if (device_info->target_id)
+ major_info->index = 1;
+ else
+ major_info->index = 0;
+
+ return 0;
+ }
+
+ return -ENODEV;
}
+
diff --git a/drivers/staging/hv/storvsc_api.h b/drivers/staging/hv/storvsc_api.h
deleted file mode 100644
index fbf5755..0000000
--- a/drivers/staging/hv/storvsc_api.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- *
- * Copyright (c) 2009, Microsoft Corporation.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
- * Place - Suite 330, Boston, MA 02111-1307 USA.
- *
- * Authors:
- * Haiyang Zhang <haiyangz@microsoft.com>
- * Hank Janssen <hjanssen@microsoft.com>
- *
- */
-
-
-#ifndef _STORVSC_API_H_
-#define _STORVSC_API_H_
-
-#include "vmbus_api.h"
-
-/* Defines */
-#define STORVSC_RING_BUFFER_SIZE (20*PAGE_SIZE)
-#define BLKVSC_RING_BUFFER_SIZE (20*PAGE_SIZE)
-
-#define STORVSC_MAX_IO_REQUESTS 128
-
-/*
- * In Hyper-V, each port/path/target maps to 1 scsi host adapter. In
- * reality, the path/target is not used (ie always set to 0) so our
- * scsi host adapter essentially has 1 bus with 1 target that contains
- * up to 256 luns.
- */
-#define STORVSC_MAX_LUNS_PER_TARGET 64
-#define STORVSC_MAX_TARGETS 1
-#define STORVSC_MAX_CHANNELS 1
-
-struct hv_storvsc_request;
-
-/* Matches Windows-end */
-enum storvsc_request_type{
- WRITE_TYPE,
- READ_TYPE,
- UNKNOWN_TYPE,
-};
-
-struct hv_storvsc_request {
- enum storvsc_request_type type;
- u32 host;
- u32 bus;
- u32 target_id;
- u32 lun_id;
- u8 *cdb;
- u32 cdb_len;
- u32 status;
- u32 bytes_xfer;
-
- unsigned char *sense_buffer;
- u32 sense_buffer_size;
-
- void *context;
-
- void (*on_io_completion)(struct hv_storvsc_request *request);
-
- /* This points to the memory after DataBuffer */
- void *extension;
-
- struct hv_multipage_buffer data_buffer;
-};
-
-/* Represents the block vsc driver */
-struct storvsc_driver_object {
- /* Must be the first field */
- /* Which is a bug FIXME! */
- struct hv_driver base;
-
- /* Set by caller (in bytes) */
- u32 ring_buffer_size;
-
- /* Allocate this much private extension for each I/O request */
- u32 request_ext_size;
-
- /* Maximum # of requests in flight per channel/device */
- u32 max_outstanding_req_per_channel;
-
- /* Specific to this driver */
- int (*on_io_request)(struct hv_device *device,
- struct hv_storvsc_request *request);
-};
-
-struct storvsc_device_info {
- unsigned int port_number;
- unsigned char path_id;
- unsigned char target_id;
-};
-
-/* Interface */
-int stor_vsc_initialize(struct hv_driver *driver);
-int stor_vsc_on_host_reset(struct hv_device *device);
-int blk_vsc_initialize(struct hv_driver *driver);
-
-#endif /* _STORVSC_API_H_ */
diff --git a/drivers/staging/hv/storvsc_drv.c b/drivers/staging/hv/storvsc_drv.c
index e6462a2..942cc5f 100644
--- a/drivers/staging/hv/storvsc_drv.c
+++ b/drivers/staging/hv/storvsc_drv.c
@@ -17,6 +17,7 @@
* Authors:
* Haiyang Zhang <haiyangz@microsoft.com>
* Hank Janssen <hjanssen@microsoft.com>
+ * K. Y. Srinivasan <kys@microsoft.com>
*/
#include <linux/init.h>
#include <linux/slab.h>
@@ -31,18 +32,27 @@
#include <scsi/scsi_eh.h>
#include <scsi/scsi_devinfo.h>
#include <scsi/scsi_dbg.h>
-#include "hv_api.h"
-#include "logging.h"
-#include "version_info.h"
-#include "vmbus.h"
-#include "storvsc_api.h"
+#include "hyperv.h"
+#include "hyperv_storage.h"
-struct host_device_context {
- /* must be 1st field
- * FIXME this is a bug */
- /* point back to our device context */
- struct hv_device *device_ctx;
+static int storvsc_ringbuffer_size = STORVSC_RING_BUFFER_SIZE;
+
+module_param(storvsc_ringbuffer_size, int, S_IRUGO);
+MODULE_PARM_DESC(storvsc_ringbuffer_size, "Ring buffer size (bytes)");
+
+static const char *driver_name = "storvsc";
+
+/* {ba6163d9-04a1-4d29-b605-72e2ffb1dc7f} */
+static const struct hv_guid gStorVscDeviceType = {
+ .data = {
+ 0xd9, 0x63, 0x61, 0xba, 0xa1, 0x04, 0x29, 0x4d,
+ 0xb6, 0x05, 0x72, 0xe2, 0xff, 0xb1, 0xdc, 0x7f
+ }
+};
+
+struct hv_host_device {
+ struct hv_device *dev;
struct kmem_cache *request_pool;
unsigned int port;
unsigned char path;
@@ -57,331 +67,57 @@
struct scatterlist *bounce_sgl;
struct hv_storvsc_request request;
- /* !!!DO NOT ADD ANYTHING BELOW HERE!!! */
- /* The extension buffer falls right here and is pointed to by
- * request.Extension;
- * Which sounds like a very bad design... */
};
-/* Static decl */
-static int storvsc_probe(struct device *dev);
-static int storvsc_queuecommand(struct Scsi_Host *shost, struct scsi_cmnd *scmnd);
-static int storvsc_device_alloc(struct scsi_device *);
-static int storvsc_device_configure(struct scsi_device *);
-static int storvsc_host_reset_handler(struct scsi_cmnd *scmnd);
-static int storvsc_remove(struct device *dev);
+static int storvsc_device_alloc(struct scsi_device *sdevice)
+{
+ /*
+ * This enables luns to be located sparsely. Otherwise, we may not
+ * discovered them.
+ */
+ sdevice->sdev_bflags |= BLIST_SPARSELUN | BLIST_LARGELUN;
+ return 0;
+}
-static struct scatterlist *create_bounce_buffer(struct scatterlist *sgl,
- unsigned int sg_count,
- unsigned int len);
+static int storvsc_merge_bvec(struct request_queue *q,
+ struct bvec_merge_data *bmd, struct bio_vec *bvec)
+{
+ /* checking done by caller. */
+ return bvec->bv_len;
+}
+
+static int storvsc_device_configure(struct scsi_device *sdevice)
+{
+ scsi_adjust_queue_depth(sdevice, MSG_SIMPLE_TAG,
+ STORVSC_MAX_IO_REQUESTS);
+
+ DPRINT_INFO(STORVSC_DRV, "sdev (%p) - setting max segment size to %ld",
+ sdevice, PAGE_SIZE);
+ blk_queue_max_segment_size(sdevice->request_queue, PAGE_SIZE);
+
+ DPRINT_INFO(STORVSC_DRV, "sdev (%p) - adding merge bio vec routine",
+ sdevice);
+ blk_queue_merge_bvec(sdevice->request_queue, storvsc_merge_bvec);
+
+ blk_queue_bounce_limit(sdevice->request_queue, BLK_BOUNCE_ANY);
+
+ return 0;
+}
+
static void destroy_bounce_buffer(struct scatterlist *sgl,
- unsigned int sg_count);
-static int do_bounce_buffer(struct scatterlist *sgl, unsigned int sg_count);
-static unsigned int copy_from_bounce_buffer(struct scatterlist *orig_sgl,
- struct scatterlist *bounce_sgl,
- unsigned int orig_sgl_count);
-static unsigned int copy_to_bounce_buffer(struct scatterlist *orig_sgl,
- struct scatterlist *bounce_sgl,
- unsigned int orig_sgl_count);
-
-static int storvsc_get_chs(struct scsi_device *sdev, struct block_device *bdev,
- sector_t capacity, int *info);
-
-
-static int storvsc_ringbuffer_size = STORVSC_RING_BUFFER_SIZE;
-module_param(storvsc_ringbuffer_size, int, S_IRUGO);
-MODULE_PARM_DESC(storvsc_ringbuffer_size, "Ring buffer size (bytes)");
-
-/* The one and only one */
-static struct storvsc_driver_object g_storvsc_drv;
-
-/* Scsi driver */
-static struct scsi_host_template scsi_driver = {
- .module = THIS_MODULE,
- .name = "storvsc_host_t",
- .bios_param = storvsc_get_chs,
- .queuecommand = storvsc_queuecommand,
- .eh_host_reset_handler = storvsc_host_reset_handler,
- .slave_alloc = storvsc_device_alloc,
- .slave_configure = storvsc_device_configure,
- .cmd_per_lun = 1,
- /* 64 max_queue * 1 target */
- .can_queue = STORVSC_MAX_IO_REQUESTS*STORVSC_MAX_TARGETS,
- .this_id = -1,
- /* no use setting to 0 since ll_blk_rw reset it to 1 */
- /* currently 32 */
- .sg_tablesize = MAX_MULTIPAGE_BUFFER_COUNT,
- /*
- * ENABLE_CLUSTERING allows mutiple physically contig bio_vecs to merge
- * into 1 sg element. If set, we must limit the max_segment_size to
- * PAGE_SIZE, otherwise we may get 1 sg element that represents
- * multiple
- */
- /* physically contig pfns (ie sg[x].length > PAGE_SIZE). */
- .use_clustering = ENABLE_CLUSTERING,
- /* Make sure we dont get a sg segment crosses a page boundary */
- .dma_boundary = PAGE_SIZE-1,
-};
-
-
-/*
- * storvsc_drv_init - StorVsc driver initialization.
- */
-static int storvsc_drv_init(int (*drv_init)(struct hv_driver *drv))
+ unsigned int sg_count)
{
- int ret;
- struct storvsc_driver_object *storvsc_drv_obj = &g_storvsc_drv;
- struct hv_driver *drv = &g_storvsc_drv.base;
+ int i;
+ struct page *page_buf;
- storvsc_drv_obj->ring_buffer_size = storvsc_ringbuffer_size;
-
- /* Callback to client driver to complete the initialization */
- drv_init(&storvsc_drv_obj->base);
-
- drv->priv = storvsc_drv_obj;
-
- DPRINT_INFO(STORVSC_DRV,
- "request extension size %u, max outstanding reqs %u",
- storvsc_drv_obj->request_ext_size,
- storvsc_drv_obj->max_outstanding_req_per_channel);
-
- if (storvsc_drv_obj->max_outstanding_req_per_channel <
- STORVSC_MAX_IO_REQUESTS) {
- DPRINT_ERR(STORVSC_DRV,
- "The number of outstanding io requests (%d) "
- "is larger than that supported (%d) internally.",
- STORVSC_MAX_IO_REQUESTS,
- storvsc_drv_obj->max_outstanding_req_per_channel);
- return -1;
+ for (i = 0; i < sg_count; i++) {
+ page_buf = sg_page((&sgl[i]));
+ if (page_buf != NULL)
+ __free_page(page_buf);
}
- drv->driver.name = storvsc_drv_obj->base.name;
-
- drv->driver.probe = storvsc_probe;
- drv->driver.remove = storvsc_remove;
-
- /* The driver belongs to vmbus */
- ret = vmbus_child_driver_register(&drv->driver);
-
- return ret;
-}
-
-static int storvsc_drv_exit_cb(struct device *dev, void *data)
-{
- struct device **curr = (struct device **)data;
- *curr = dev;
- return 1; /* stop iterating */
-}
-
-static void storvsc_drv_exit(void)
-{
- struct storvsc_driver_object *storvsc_drv_obj = &g_storvsc_drv;
- struct hv_driver *drv = &g_storvsc_drv.base;
- struct device *current_dev = NULL;
- int ret;
-
- while (1) {
- current_dev = NULL;
-
- /* Get the device */
- ret = driver_for_each_device(&drv->driver, NULL,
- (void *) ¤t_dev,
- storvsc_drv_exit_cb);
-
- if (ret)
- DPRINT_WARN(STORVSC_DRV,
- "driver_for_each_device returned %d", ret);
-
- if (current_dev == NULL)
- break;
-
- /* Initiate removal from the top-down */
- device_unregister(current_dev);
- }
-
- if (storvsc_drv_obj->base.cleanup)
- storvsc_drv_obj->base.cleanup(&storvsc_drv_obj->base);
-
- vmbus_child_driver_unregister(&drv->driver);
- return;
-}
-
-/*
- * storvsc_probe - Add a new device for this driver
- */
-static int storvsc_probe(struct device *device)
-{
- int ret;
- struct hv_driver *drv =
- drv_to_hv_drv(device->driver);
- struct storvsc_driver_object *storvsc_drv_obj = drv->priv;
- struct hv_device *device_obj = device_to_hv_device(device);
- struct Scsi_Host *host;
- struct host_device_context *host_device_ctx;
- struct storvsc_device_info device_info;
-
- if (!storvsc_drv_obj->base.dev_add)
- return -1;
-
- host = scsi_host_alloc(&scsi_driver,
- sizeof(struct host_device_context));
- if (!host) {
- DPRINT_ERR(STORVSC_DRV, "unable to allocate scsi host object");
- return -ENOMEM;
- }
-
- dev_set_drvdata(device, host);
-
- host_device_ctx = (struct host_device_context *)host->hostdata;
- memset(host_device_ctx, 0, sizeof(struct host_device_context));
-
- host_device_ctx->port = host->host_no;
- host_device_ctx->device_ctx = device_obj;
-
- host_device_ctx->request_pool =
- kmem_cache_create(dev_name(&device_obj->device),
- sizeof(struct storvsc_cmd_request) +
- storvsc_drv_obj->request_ext_size, 0,
- SLAB_HWCACHE_ALIGN, NULL);
-
- if (!host_device_ctx->request_pool) {
- scsi_host_put(host);
- return -ENOMEM;
- }
-
- device_info.port_number = host->host_no;
- /* Call to the vsc driver to add the device */
- ret = storvsc_drv_obj->base.dev_add(device_obj,
- (void *)&device_info);
- if (ret != 0) {
- DPRINT_ERR(STORVSC_DRV, "unable to add scsi vsc device");
- kmem_cache_destroy(host_device_ctx->request_pool);
- scsi_host_put(host);
- return -1;
- }
-
- /* host_device_ctx->port = device_info.PortNumber; */
- host_device_ctx->path = device_info.path_id;
- host_device_ctx->target = device_info.target_id;
-
- /* max # of devices per target */
- host->max_lun = STORVSC_MAX_LUNS_PER_TARGET;
- /* max # of targets per channel */
- host->max_id = STORVSC_MAX_TARGETS;
- /* max # of channels */
- host->max_channel = STORVSC_MAX_CHANNELS - 1;
-
- /* Register the HBA and start the scsi bus scan */
- ret = scsi_add_host(host, device);
- if (ret != 0) {
- DPRINT_ERR(STORVSC_DRV, "unable to add scsi host device");
-
- storvsc_drv_obj->base.dev_rm(device_obj);
-
- kmem_cache_destroy(host_device_ctx->request_pool);
- scsi_host_put(host);
- return -1;
- }
-
- scsi_scan_host(host);
- return ret;
-}
-
-/*
- * storvsc_remove - Callback when our device is removed
- */
-static int storvsc_remove(struct device *device)
-{
- int ret;
- struct hv_driver *drv =
- drv_to_hv_drv(device->driver);
- struct storvsc_driver_object *storvsc_drv_obj = drv->priv;
- struct hv_device *device_obj = device_to_hv_device(device);
- struct Scsi_Host *host = dev_get_drvdata(device);
- struct host_device_context *host_device_ctx =
- (struct host_device_context *)host->hostdata;
-
-
- if (!storvsc_drv_obj->base.dev_rm)
- return -1;
-
- /*
- * Call to the vsc driver to let it know that the device is being
- * removed
- */
- ret = storvsc_drv_obj->base.dev_rm(device_obj);
- if (ret != 0) {
- /* TODO: */
- DPRINT_ERR(STORVSC, "unable to remove vsc device (ret %d)",
- ret);
- }
-
- if (host_device_ctx->request_pool) {
- kmem_cache_destroy(host_device_ctx->request_pool);
- host_device_ctx->request_pool = NULL;
- }
-
- DPRINT_INFO(STORVSC, "removing host adapter (%p)...", host);
- scsi_remove_host(host);
-
- DPRINT_INFO(STORVSC, "releasing host adapter (%p)...", host);
- scsi_host_put(host);
- return ret;
-}
-
-/*
- * storvsc_commmand_completion - Command completion processing
- */
-static void storvsc_commmand_completion(struct hv_storvsc_request *request)
-{
- struct storvsc_cmd_request *cmd_request =
- (struct storvsc_cmd_request *)request->context;
- struct scsi_cmnd *scmnd = cmd_request->cmd;
- struct host_device_context *host_device_ctx =
- (struct host_device_context *)scmnd->device->host->hostdata;
- void (*scsi_done_fn)(struct scsi_cmnd *);
- struct scsi_sense_hdr sense_hdr;
-
- /* ASSERT(request == &cmd_request->request); */
- /* ASSERT(scmnd); */
- /* ASSERT((unsigned long)scmnd->host_scribble == */
- /* (unsigned long)cmd_request); */
- /* ASSERT(scmnd->scsi_done); */
-
- if (cmd_request->bounce_sgl_count) {
- /* using bounce buffer */
- /* printk("copy_from_bounce_buffer\n"); */
-
- /* FIXME: We can optimize on writes by just skipping this */
- copy_from_bounce_buffer(scsi_sglist(scmnd),
- cmd_request->bounce_sgl,
- scsi_sg_count(scmnd));
- destroy_bounce_buffer(cmd_request->bounce_sgl,
- cmd_request->bounce_sgl_count);
- }
-
- scmnd->result = request->status;
-
- if (scmnd->result) {
- if (scsi_normalize_sense(scmnd->sense_buffer,
- request->sense_buffer_size, &sense_hdr))
- scsi_print_sense_hdr("storvsc", &sense_hdr);
- }
-
- /* ASSERT(request->BytesXfer <= request->data_buffer.Length); */
- scsi_set_resid(scmnd,
- request->data_buffer.len - request->bytes_xfer);
-
- scsi_done_fn = scmnd->scsi_done;
-
- scmnd->host_scribble = NULL;
- scmnd->scsi_done = NULL;
-
- /* !!DO NOT MODIFY the scmnd after this call */
- scsi_done_fn(scmnd);
-
- kmem_cache_free(host_device_ctx->request_pool, cmd_request);
+ kfree(sgl);
}
static int do_bounce_buffer(struct scatterlist *sgl, unsigned int sg_count)
@@ -440,21 +176,72 @@
return NULL;
}
-static void destroy_bounce_buffer(struct scatterlist *sgl,
- unsigned int sg_count)
+
+/* Assume the original sgl has enough room */
+static unsigned int copy_from_bounce_buffer(struct scatterlist *orig_sgl,
+ struct scatterlist *bounce_sgl,
+ unsigned int orig_sgl_count)
{
int i;
- struct page *page_buf;
+ int j = 0;
+ unsigned long src, dest;
+ unsigned int srclen, destlen, copylen;
+ unsigned int total_copied = 0;
+ unsigned long bounce_addr = 0;
+ unsigned long dest_addr = 0;
+ unsigned long flags;
- for (i = 0; i < sg_count; i++) {
- page_buf = sg_page((&sgl[i]));
- if (page_buf != NULL)
- __free_page(page_buf);
+ local_irq_save(flags);
+
+ for (i = 0; i < orig_sgl_count; i++) {
+ dest_addr = (unsigned long)kmap_atomic(sg_page((&orig_sgl[i])),
+ KM_IRQ0) + orig_sgl[i].offset;
+ dest = dest_addr;
+ destlen = orig_sgl[i].length;
+
+ if (bounce_addr == 0)
+ bounce_addr =
+ (unsigned long)kmap_atomic(sg_page((&bounce_sgl[j])),
+ KM_IRQ0);
+
+ while (destlen) {
+ src = bounce_addr + bounce_sgl[j].offset;
+ srclen = bounce_sgl[j].length - bounce_sgl[j].offset;
+
+ copylen = min(srclen, destlen);
+ memcpy((void *)dest, (void *)src, copylen);
+
+ total_copied += copylen;
+ bounce_sgl[j].offset += copylen;
+ destlen -= copylen;
+ dest += copylen;
+
+ if (bounce_sgl[j].offset == bounce_sgl[j].length) {
+ /* full */
+ kunmap_atomic((void *)bounce_addr, KM_IRQ0);
+ j++;
+
+ /* if we need to use another bounce buffer */
+ if (destlen || i != orig_sgl_count - 1)
+ bounce_addr =
+ (unsigned long)kmap_atomic(
+ sg_page((&bounce_sgl[j])), KM_IRQ0);
+ } else if (destlen == 0 && i == orig_sgl_count - 1) {
+ /* unmap the last bounce that is < PAGE_SIZE */
+ kunmap_atomic((void *)bounce_addr, KM_IRQ0);
+ }
+ }
+
+ kunmap_atomic((void *)(dest_addr - orig_sgl[i].offset),
+ KM_IRQ0);
}
- kfree(sgl);
+ local_irq_restore(flags);
+
+ return total_copied;
}
+
/* Assume the bounce_sgl has enough room ie using the create_bounce_buffer() */
static unsigned int copy_to_bounce_buffer(struct scatterlist *orig_sgl,
struct scatterlist *bounce_sgl,
@@ -477,10 +264,10 @@
src = src_addr;
srclen = orig_sgl[i].length;
- /* ASSERT(orig_sgl[i].offset + orig_sgl[i].length <= PAGE_SIZE); */
-
if (bounce_addr == 0)
- bounce_addr = (unsigned long)kmap_atomic(sg_page((&bounce_sgl[j])), KM_IRQ0);
+ bounce_addr =
+ (unsigned long)kmap_atomic(sg_page((&bounce_sgl[j])),
+ KM_IRQ0);
while (srclen) {
/* assume bounce offset always == 0 */
@@ -502,7 +289,10 @@
/* if we need to use another bounce buffer */
if (srclen || i != orig_sgl_count - 1)
- bounce_addr = (unsigned long)kmap_atomic(sg_page((&bounce_sgl[j])), KM_IRQ0);
+ bounce_addr =
+ (unsigned long)kmap_atomic(
+ sg_page((&bounce_sgl[j])), KM_IRQ0);
+
} else if (srclen == 0 && i == orig_sgl_count - 1) {
/* unmap the last bounce that is < PAGE_SIZE */
kunmap_atomic((void *)bounce_addr, KM_IRQ0);
@@ -517,67 +307,185 @@
return total_copied;
}
-/* Assume the original sgl has enough room */
-static unsigned int copy_from_bounce_buffer(struct scatterlist *orig_sgl,
- struct scatterlist *bounce_sgl,
- unsigned int orig_sgl_count)
+
+/*
+ * storvsc_remove - Callback when our device is removed
+ */
+static int storvsc_remove(struct hv_device *dev)
{
- int i;
- int j = 0;
- unsigned long src, dest;
- unsigned int srclen, destlen, copylen;
- unsigned int total_copied = 0;
- unsigned long bounce_addr = 0;
- unsigned long dest_addr = 0;
- unsigned long flags;
+ struct Scsi_Host *host = dev_get_drvdata(&dev->device);
+ struct hv_host_device *host_dev =
+ (struct hv_host_device *)host->hostdata;
- local_irq_save(flags);
+ /*
+ * Call to the vsc driver to let it know that the device is being
+ * removed
+ */
+ storvsc_dev_remove(dev);
- for (i = 0; i < orig_sgl_count; i++) {
- dest_addr = (unsigned long)kmap_atomic(sg_page((&orig_sgl[i])),
- KM_IRQ0) + orig_sgl[i].offset;
- dest = dest_addr;
- destlen = orig_sgl[i].length;
- /* ASSERT(orig_sgl[i].offset + orig_sgl[i].length <= PAGE_SIZE); */
-
- if (bounce_addr == 0)
- bounce_addr = (unsigned long)kmap_atomic(sg_page((&bounce_sgl[j])), KM_IRQ0);
-
- while (destlen) {
- src = bounce_addr + bounce_sgl[j].offset;
- srclen = bounce_sgl[j].length - bounce_sgl[j].offset;
-
- copylen = min(srclen, destlen);
- memcpy((void *)dest, (void *)src, copylen);
-
- total_copied += copylen;
- bounce_sgl[j].offset += copylen;
- destlen -= copylen;
- dest += copylen;
-
- if (bounce_sgl[j].offset == bounce_sgl[j].length) {
- /* full */
- kunmap_atomic((void *)bounce_addr, KM_IRQ0);
- j++;
-
- /* if we need to use another bounce buffer */
- if (destlen || i != orig_sgl_count - 1)
- bounce_addr = (unsigned long)kmap_atomic(sg_page((&bounce_sgl[j])), KM_IRQ0);
- } else if (destlen == 0 && i == orig_sgl_count - 1) {
- /* unmap the last bounce that is < PAGE_SIZE */
- kunmap_atomic((void *)bounce_addr, KM_IRQ0);
- }
- }
-
- kunmap_atomic((void *)(dest_addr - orig_sgl[i].offset),
- KM_IRQ0);
+ if (host_dev->request_pool) {
+ kmem_cache_destroy(host_dev->request_pool);
+ host_dev->request_pool = NULL;
}
- local_irq_restore(flags);
+ DPRINT_INFO(STORVSC, "removing host adapter (%p)...", host);
+ scsi_remove_host(host);
- return total_copied;
+ DPRINT_INFO(STORVSC, "releasing host adapter (%p)...", host);
+ scsi_host_put(host);
+ return 0;
}
+
+static int storvsc_get_chs(struct scsi_device *sdev, struct block_device * bdev,
+ sector_t capacity, int *info)
+{
+ sector_t nsect = capacity;
+ sector_t cylinders = nsect;
+ int heads, sectors_pt;
+
+ /*
+ * We are making up these values; let us keep it simple.
+ */
+ heads = 0xff;
+ sectors_pt = 0x3f; /* Sectors per track */
+ sector_div(cylinders, heads * sectors_pt);
+ if ((sector_t)(cylinders + 1) * heads * sectors_pt < nsect)
+ cylinders = 0xffff;
+
+ info[0] = heads;
+ info[1] = sectors_pt;
+ info[2] = (int)cylinders;
+
+ DPRINT_INFO(STORVSC_DRV, "CHS (%d, %d, %d)", (int)cylinders, heads,
+ sectors_pt);
+
+ return 0;
+}
+
+static int storvsc_host_reset(struct hv_device *device)
+{
+ struct storvsc_device *stor_device;
+ struct hv_storvsc_request *request;
+ struct vstor_packet *vstor_packet;
+ int ret, t;
+
+ DPRINT_INFO(STORVSC, "resetting host adapter...");
+
+ stor_device = get_stor_device(device);
+ if (!stor_device)
+ return -1;
+
+ request = &stor_device->reset_request;
+ vstor_packet = &request->vstor_packet;
+
+ init_completion(&request->wait_event);
+
+ vstor_packet->operation = VSTOR_OPERATION_RESET_BUS;
+ vstor_packet->flags = REQUEST_COMPLETION_FLAG;
+ vstor_packet->vm_srb.path_id = stor_device->path_id;
+
+ ret = vmbus_sendpacket(device->channel, vstor_packet,
+ sizeof(struct vstor_packet),
+ (unsigned long)&stor_device->reset_request,
+ VM_PKT_DATA_INBAND,
+ VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED);
+ if (ret != 0)
+ goto cleanup;
+
+ t = wait_for_completion_timeout(&request->wait_event, HZ);
+ if (t == 0) {
+ ret = -ETIMEDOUT;
+ goto cleanup;
+ }
+
+ DPRINT_INFO(STORVSC, "host adapter reset completed");
+
+ /*
+ * At this point, all outstanding requests in the adapter
+ * should have been flushed out and return to us
+ */
+
+cleanup:
+ put_stor_device(device);
+ return ret;
+}
+
+
+/*
+ * storvsc_host_reset_handler - Reset the scsi HBA
+ */
+static int storvsc_host_reset_handler(struct scsi_cmnd *scmnd)
+{
+ int ret;
+ struct hv_host_device *host_dev =
+ (struct hv_host_device *)scmnd->device->host->hostdata;
+ struct hv_device *dev = host_dev->dev;
+
+ DPRINT_INFO(STORVSC_DRV, "sdev (%p) dev obj (%p) - host resetting...",
+ scmnd->device, dev);
+
+ /* Invokes the vsc to reset the host/bus */
+ ret = storvsc_host_reset(dev);
+ if (ret != 0)
+ return ret;
+
+ DPRINT_INFO(STORVSC_DRV, "sdev (%p) dev obj (%p) - host reseted",
+ scmnd->device, dev);
+
+ return ret;
+}
+
+
+/*
+ * storvsc_commmand_completion - Command completion processing
+ */
+static void storvsc_commmand_completion(struct hv_storvsc_request *request)
+{
+ struct storvsc_cmd_request *cmd_request =
+ (struct storvsc_cmd_request *)request->context;
+ struct scsi_cmnd *scmnd = cmd_request->cmd;
+ struct hv_host_device *host_dev =
+ (struct hv_host_device *)scmnd->device->host->hostdata;
+ void (*scsi_done_fn)(struct scsi_cmnd *);
+ struct scsi_sense_hdr sense_hdr;
+ struct vmscsi_request *vm_srb;
+
+ if (cmd_request->bounce_sgl_count) {
+
+ /* FIXME: We can optimize on writes by just skipping this */
+ copy_from_bounce_buffer(scsi_sglist(scmnd),
+ cmd_request->bounce_sgl,
+ scsi_sg_count(scmnd));
+ destroy_bounce_buffer(cmd_request->bounce_sgl,
+ cmd_request->bounce_sgl_count);
+ }
+
+ vm_srb = &request->vstor_packet.vm_srb;
+ scmnd->result = vm_srb->scsi_status;
+
+ if (scmnd->result) {
+ if (scsi_normalize_sense(scmnd->sense_buffer,
+ SCSI_SENSE_BUFFERSIZE, &sense_hdr))
+ scsi_print_sense_hdr("storvsc", &sense_hdr);
+ }
+
+ scsi_set_resid(scmnd,
+ request->data_buffer.len -
+ vm_srb->data_transfer_length);
+
+ scsi_done_fn = scmnd->scsi_done;
+
+ scmnd->host_scribble = NULL;
+ scmnd->scsi_done = NULL;
+
+ /* !!DO NOT MODIFY the scmnd after this call */
+ scsi_done_fn(scmnd);
+
+ kmem_cache_free(host_dev->request_pool, cmd_request);
+}
+
+
/*
* storvsc_queuecommand - Initiate command processing
*/
@@ -585,28 +493,20 @@
void (*done)(struct scsi_cmnd *))
{
int ret;
- struct host_device_context *host_device_ctx =
- (struct host_device_context *)scmnd->device->host->hostdata;
- struct hv_device *device_ctx = host_device_ctx->device_ctx;
- struct hv_driver *drv =
- drv_to_hv_drv(device_ctx->device.driver);
- struct storvsc_driver_object *storvsc_drv_obj = drv->priv;
+ struct hv_host_device *host_dev =
+ (struct hv_host_device *)scmnd->device->host->hostdata;
+ struct hv_device *dev = host_dev->dev;
struct hv_storvsc_request *request;
struct storvsc_cmd_request *cmd_request;
unsigned int request_size = 0;
int i;
struct scatterlist *sgl;
unsigned int sg_count = 0;
+ struct vmscsi_request *vm_srb;
- DPRINT_DBG(STORVSC_DRV, "scmnd %p dir %d, use_sg %d buf %p len %d "
- "queue depth %d tagged %d", scmnd, scmnd->sc_data_direction,
- scsi_sg_count(scmnd), scsi_sglist(scmnd),
- scsi_bufflen(scmnd), scmnd->device->queue_depth,
- scmnd->device->tagged_supported);
/* If retrying, no need to prep the cmd */
if (scmnd->host_scribble) {
- /* ASSERT(scmnd->scsi_done != NULL); */
cmd_request =
(struct storvsc_cmd_request *)scmnd->host_scribble;
@@ -616,18 +516,13 @@
goto retry_request;
}
- /* ASSERT(scmnd->scsi_done == NULL); */
- /* ASSERT(scmnd->host_scribble == NULL); */
-
scmnd->scsi_done = done;
request_size = sizeof(struct storvsc_cmd_request);
- cmd_request = kmem_cache_alloc(host_device_ctx->request_pool,
+ cmd_request = kmem_cache_zalloc(host_dev->request_pool,
GFP_ATOMIC);
if (!cmd_request) {
- DPRINT_ERR(STORVSC_DRV, "scmnd (%p) - unable to allocate "
- "storvsc_cmd_request...marking queue busy", scmnd);
scmnd->scsi_done = NULL;
return SCSI_MLQUEUE_DEVICE_BUSY;
}
@@ -640,40 +535,35 @@
scmnd->host_scribble = (unsigned char *)cmd_request;
request = &cmd_request->request;
+ vm_srb = &request->vstor_packet.vm_srb;
- request->extension =
- (void *)((unsigned long)cmd_request + request_size);
- DPRINT_DBG(STORVSC_DRV, "req %p size %d ext %d", request, request_size,
- storvsc_drv_obj->request_ext_size);
/* Build the SRB */
switch (scmnd->sc_data_direction) {
case DMA_TO_DEVICE:
- request->type = WRITE_TYPE;
+ vm_srb->data_in = WRITE_TYPE;
break;
case DMA_FROM_DEVICE:
- request->type = READ_TYPE;
+ vm_srb->data_in = READ_TYPE;
break;
default:
- request->type = UNKNOWN_TYPE;
+ vm_srb->data_in = UNKNOWN_TYPE;
break;
}
request->on_io_completion = storvsc_commmand_completion;
request->context = cmd_request;/* scmnd; */
- /* request->PortId = scmnd->device->channel; */
- request->host = host_device_ctx->port;
- request->bus = scmnd->device->channel;
- request->target_id = scmnd->device->id;
- request->lun_id = scmnd->device->lun;
+ vm_srb->port_number = host_dev->port;
+ vm_srb->path_id = scmnd->device->channel;
+ vm_srb->target_id = scmnd->device->id;
+ vm_srb->lun = scmnd->device->lun;
- /* ASSERT(scmnd->cmd_len <= 16); */
- request->cdb_len = scmnd->cmd_len;
- request->cdb = scmnd->cmnd;
+ vm_srb->cdb_length = scmnd->cmd_len;
+
+ memcpy(vm_srb->cdb, scmnd->cmnd, vm_srb->cdb_length);
request->sense_buffer = scmnd->sense_buffer;
- request->sense_buffer_size = SCSI_SENSE_BUFFERSIZE;
request->data_buffer.len = scsi_bufflen(scmnd);
@@ -683,20 +573,13 @@
/* check if we need to bounce the sgl */
if (do_bounce_buffer(sgl, scsi_sg_count(scmnd)) != -1) {
- DPRINT_INFO(STORVSC_DRV,
- "need to bounce buffer for this scmnd %p",
- scmnd);
cmd_request->bounce_sgl =
create_bounce_buffer(sgl, scsi_sg_count(scmnd),
scsi_bufflen(scmnd));
if (!cmd_request->bounce_sgl) {
- DPRINT_ERR(STORVSC_DRV,
- "unable to create bounce buffer for "
- "this scmnd %p", scmnd);
-
scmnd->scsi_done = NULL;
scmnd->host_scribble = NULL;
- kmem_cache_free(host_device_ctx->request_pool,
+ kmem_cache_free(host_dev->request_pool,
cmd_request);
return SCSI_MLQUEUE_HOST_BUSY;
@@ -719,14 +602,11 @@
request->data_buffer.offset = sgl[0].offset;
- for (i = 0; i < sg_count; i++) {
- DPRINT_DBG(STORVSC_DRV, "sgl[%d] len %d offset %d\n",
- i, sgl[i].length, sgl[i].offset);
+ for (i = 0; i < sg_count; i++)
request->data_buffer.pfn_array[i] =
page_to_pfn(sg_page((&sgl[i])));
- }
+
} else if (scsi_sglist(scmnd)) {
- /* ASSERT(scsi_bufflen(scmnd) <= PAGE_SIZE); */
request->data_buffer.offset =
virt_to_phys(scsi_sglist(scmnd)) & (PAGE_SIZE-1);
request->data_buffer.pfn_array[0] =
@@ -735,13 +615,10 @@
retry_request:
/* Invokes the vsc to start an IO */
- ret = storvsc_drv_obj->on_io_request(device_ctx,
- &cmd_request->request);
+ ret = storvsc_do_io(dev, &cmd_request->request);
+
if (ret == -1) {
/* no more space */
- DPRINT_ERR(STORVSC_DRV,
- "scmnd (%p) - queue FULL...marking queue busy",
- scmnd);
if (cmd_request->bounce_sgl_count) {
/*
@@ -755,7 +632,7 @@
cmd_request->bounce_sgl_count);
}
- kmem_cache_free(host_device_ctx->request_pool, cmd_request);
+ kmem_cache_free(host_dev->request_pool, cmd_request);
scmnd->scsi_done = NULL;
scmnd->host_scribble = NULL;
@@ -768,154 +645,156 @@
static DEF_SCSI_QCMD(storvsc_queuecommand)
-static int storvsc_merge_bvec(struct request_queue *q,
- struct bvec_merge_data *bmd, struct bio_vec *bvec)
-{
- /* checking done by caller. */
- return bvec->bv_len;
-}
-/*
- * storvsc_device_configure - Configure the specified scsi device
- */
-static int storvsc_device_alloc(struct scsi_device *sdevice)
-{
- DPRINT_DBG(STORVSC_DRV, "sdev (%p) - setting device flag to %d",
- sdevice, BLIST_SPARSELUN);
+/* Scsi driver */
+static struct scsi_host_template scsi_driver = {
+ .module = THIS_MODULE,
+ .name = "storvsc_host_t",
+ .bios_param = storvsc_get_chs,
+ .queuecommand = storvsc_queuecommand,
+ .eh_host_reset_handler = storvsc_host_reset_handler,
+ .slave_alloc = storvsc_device_alloc,
+ .slave_configure = storvsc_device_configure,
+ .cmd_per_lun = 1,
+ /* 64 max_queue * 1 target */
+ .can_queue = STORVSC_MAX_IO_REQUESTS*STORVSC_MAX_TARGETS,
+ .this_id = -1,
+ /* no use setting to 0 since ll_blk_rw reset it to 1 */
+ /* currently 32 */
+ .sg_tablesize = MAX_MULTIPAGE_BUFFER_COUNT,
/*
- * This enables luns to be located sparsely. Otherwise, we may not
- * discovered them.
+ * ENABLE_CLUSTERING allows mutiple physically contig bio_vecs to merge
+ * into 1 sg element. If set, we must limit the max_segment_size to
+ * PAGE_SIZE, otherwise we may get 1 sg element that represents
+ * multiple
*/
- sdevice->sdev_bflags |= BLIST_SPARSELUN | BLIST_LARGELUN;
- return 0;
-}
+ /* physically contig pfns (ie sg[x].length > PAGE_SIZE). */
+ .use_clustering = ENABLE_CLUSTERING,
+ /* Make sure we dont get a sg segment crosses a page boundary */
+ .dma_boundary = PAGE_SIZE-1,
+};
-static int storvsc_device_configure(struct scsi_device *sdevice)
-{
- DPRINT_INFO(STORVSC_DRV, "sdev (%p) - curr queue depth %d", sdevice,
- sdevice->queue_depth);
-
- DPRINT_INFO(STORVSC_DRV, "sdev (%p) - setting queue depth to %d",
- sdevice, STORVSC_MAX_IO_REQUESTS);
- scsi_adjust_queue_depth(sdevice, MSG_SIMPLE_TAG,
- STORVSC_MAX_IO_REQUESTS);
-
- DPRINT_INFO(STORVSC_DRV, "sdev (%p) - setting max segment size to %ld",
- sdevice, PAGE_SIZE);
- blk_queue_max_segment_size(sdevice->request_queue, PAGE_SIZE);
-
- DPRINT_INFO(STORVSC_DRV, "sdev (%p) - adding merge bio vec routine",
- sdevice);
- blk_queue_merge_bvec(sdevice->request_queue, storvsc_merge_bvec);
-
- blk_queue_bounce_limit(sdevice->request_queue, BLK_BOUNCE_ANY);
- /* sdevice->timeout = (2000 * HZ);//(75 * HZ); */
-
- return 0;
-}
/*
- * storvsc_host_reset_handler - Reset the scsi HBA
+ * storvsc_probe - Add a new device for this driver
*/
-static int storvsc_host_reset_handler(struct scsi_cmnd *scmnd)
+
+static int storvsc_probe(struct hv_device *device)
{
int ret;
- struct host_device_context *host_device_ctx =
- (struct host_device_context *)scmnd->device->host->hostdata;
- struct hv_device *device_ctx = host_device_ctx->device_ctx;
+ struct Scsi_Host *host;
+ struct hv_host_device *host_dev;
+ struct storvsc_device_info device_info;
- DPRINT_INFO(STORVSC_DRV, "sdev (%p) dev obj (%p) - host resetting...",
- scmnd->device, device_ctx);
+ host = scsi_host_alloc(&scsi_driver,
+ sizeof(struct hv_host_device));
+ if (!host)
+ return -ENOMEM;
- /* Invokes the vsc to reset the host/bus */
- ret = stor_vsc_on_host_reset(device_ctx);
- if (ret != 0)
- return ret;
+ dev_set_drvdata(&device->device, host);
- DPRINT_INFO(STORVSC_DRV, "sdev (%p) dev obj (%p) - host reseted",
- scmnd->device, device_ctx);
+ host_dev = (struct hv_host_device *)host->hostdata;
+ memset(host_dev, 0, sizeof(struct hv_host_device));
+
+ host_dev->port = host->host_no;
+ host_dev->dev = device;
+
+ host_dev->request_pool =
+ kmem_cache_create(dev_name(&device->device),
+ sizeof(struct storvsc_cmd_request), 0,
+ SLAB_HWCACHE_ALIGN, NULL);
+
+ if (!host_dev->request_pool) {
+ scsi_host_put(host);
+ return -ENOMEM;
+ }
+
+ device_info.port_number = host->host_no;
+ device_info.ring_buffer_size = storvsc_ringbuffer_size;
+ /* Call to the vsc driver to add the device */
+ ret = storvsc_dev_add(device, (void *)&device_info);
+
+ if (ret != 0) {
+ kmem_cache_destroy(host_dev->request_pool);
+ scsi_host_put(host);
+ return -1;
+ }
+
+ host_dev->path = device_info.path_id;
+ host_dev->target = device_info.target_id;
+
+ /* max # of devices per target */
+ host->max_lun = STORVSC_MAX_LUNS_PER_TARGET;
+ /* max # of targets per channel */
+ host->max_id = STORVSC_MAX_TARGETS;
+ /* max # of channels */
+ host->max_channel = STORVSC_MAX_CHANNELS - 1;
+
+ /* Register the HBA and start the scsi bus scan */
+ ret = scsi_add_host(host, &device->device);
+ if (ret != 0) {
+
+ storvsc_dev_remove(device);
+
+ kmem_cache_destroy(host_dev->request_pool);
+ scsi_host_put(host);
+ return -1;
+ }
+
+ scsi_scan_host(host);
+ return ret;
+}
+
+/* The one and only one */
+
+static struct hv_driver storvsc_drv = {
+ .probe = storvsc_probe,
+ .remove = storvsc_remove,
+};
+
+
+/*
+ * storvsc_drv_init - StorVsc driver initialization.
+ */
+static int storvsc_drv_init(void)
+{
+ int ret;
+ struct hv_driver *drv = &storvsc_drv;
+ u32 max_outstanding_req_per_channel;
+
+ /*
+ * Divide the ring buffer data size (which is 1 page less
+ * than the ring buffer size since that page is reserved for
+ * the ring buffer indices) by the max request size (which is
+ * vmbus_channel_packet_multipage_buffer + struct vstor_packet + u64)
+ */
+
+ max_outstanding_req_per_channel =
+ ((storvsc_ringbuffer_size - PAGE_SIZE) /
+ ALIGN(MAX_MULTIPAGE_BUFFER_PACKET +
+ sizeof(struct vstor_packet) + sizeof(u64),
+ sizeof(u64)));
+
+ memcpy(&drv->dev_type, &gStorVscDeviceType,
+ sizeof(struct hv_guid));
+
+ if (max_outstanding_req_per_channel <
+ STORVSC_MAX_IO_REQUESTS)
+ return -1;
+
+ drv->name = driver_name;
+ drv->driver.name = driver_name;
+
+
+ /* The driver belongs to vmbus */
+ ret = vmbus_child_driver_register(&drv->driver);
return ret;
}
-static int storvsc_get_chs(struct scsi_device *sdev, struct block_device * bdev,
- sector_t capacity, int *info)
+static void storvsc_drv_exit(void)
{
- sector_t total_sectors = capacity;
- sector_t cylinder_times_heads = 0;
- sector_t temp = 0;
-
- int sectors_per_track = 0;
- int heads = 0;
- int cylinders = 0;
- int rem = 0;
-
- if (total_sectors > (65535 * 16 * 255))
- total_sectors = (65535 * 16 * 255);
-
- if (total_sectors >= (65535 * 16 * 63)) {
- sectors_per_track = 255;
- heads = 16;
-
- cylinder_times_heads = total_sectors;
- /* sector_div stores the quotient in cylinder_times_heads */
- rem = sector_div(cylinder_times_heads, sectors_per_track);
- } else {
- sectors_per_track = 17;
-
- cylinder_times_heads = total_sectors;
- /* sector_div stores the quotient in cylinder_times_heads */
- rem = sector_div(cylinder_times_heads, sectors_per_track);
-
- temp = cylinder_times_heads + 1023;
- /* sector_div stores the quotient in temp */
- rem = sector_div(temp, 1024);
-
- heads = temp;
-
- if (heads < 4)
- heads = 4;
-
- if (cylinder_times_heads >= (heads * 1024) || (heads > 16)) {
- sectors_per_track = 31;
- heads = 16;
-
- cylinder_times_heads = total_sectors;
- /*
- * sector_div stores the quotient in
- * cylinder_times_heads
- */
- rem = sector_div(cylinder_times_heads,
- sectors_per_track);
- }
-
- if (cylinder_times_heads >= (heads * 1024)) {
- sectors_per_track = 63;
- heads = 16;
-
- cylinder_times_heads = total_sectors;
- /*
- * sector_div stores the quotient in
- * cylinder_times_heads
- */
- rem = sector_div(cylinder_times_heads,
- sectors_per_track);
- }
- }
-
- temp = cylinder_times_heads;
- /* sector_div stores the quotient in temp */
- rem = sector_div(temp, heads);
- cylinders = temp;
-
- info[0] = heads;
- info[1] = sectors_per_track;
- info[2] = cylinders;
-
- DPRINT_INFO(STORVSC_DRV, "CHS (%d, %d, %d)", cylinders, heads,
- sectors_per_track);
-
- return 0;
+ vmbus_child_driver_unregister(&storvsc_drv.driver);
}
static int __init storvsc_init(void)
@@ -923,7 +802,7 @@
int ret;
DPRINT_INFO(STORVSC_DRV, "Storvsc initializing....");
- ret = storvsc_drv_init(stor_vsc_initialize);
+ ret = storvsc_drv_init();
return ret;
}
diff --git a/drivers/staging/hv/utils.h b/drivers/staging/hv/utils.h
deleted file mode 100644
index acebbbf..0000000
--- a/drivers/staging/hv/utils.h
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * Copyright (c) 2009, Microsoft Corporation.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
- * Place - Suite 330, Boston, MA 02111-1307 USA.
- *
- * Authors:
- * Haiyang Zhang <haiyangz@microsoft.com>
- * Hank Janssen <hjanssen@microsoft.com>
- */
-#ifndef __HV_UTILS_H_
-#define __HV_UTILS_H_
-
-/*
- * Common header for Hyper-V ICs
- */
-#define ICMSGTYPE_NEGOTIATE 0
-#define ICMSGTYPE_HEARTBEAT 1
-#define ICMSGTYPE_KVPEXCHANGE 2
-#define ICMSGTYPE_SHUTDOWN 3
-#define ICMSGTYPE_TIMESYNC 4
-#define ICMSGTYPE_VSS 5
-
-#define ICMSGHDRFLAG_TRANSACTION 1
-#define ICMSGHDRFLAG_REQUEST 2
-#define ICMSGHDRFLAG_RESPONSE 4
-
-#define HV_S_OK 0x00000000
-#define HV_E_FAIL 0x80004005
-#define HV_ERROR_NOT_SUPPORTED 0x80070032
-#define HV_ERROR_MACHINE_LOCKED 0x800704F7
-
-struct vmbuspipe_hdr {
- u32 flags;
- u32 msgsize;
-} __packed;
-
-struct ic_version {
- u16 major;
- u16 minor;
-} __packed;
-
-struct icmsg_hdr {
- struct ic_version icverframe;
- u16 icmsgtype;
- struct ic_version icvermsg;
- u16 icmsgsize;
- u32 status;
- u8 ictransaction_id;
- u8 icflags;
- u8 reserved[2];
-} __packed;
-
-struct icmsg_negotiate {
- u16 icframe_vercnt;
- u16 icmsg_vercnt;
- u32 reserved;
- struct ic_version icversion_data[1]; /* any size array */
-} __packed;
-
-struct shutdown_msg_data {
- u32 reason_code;
- u32 timeout_seconds;
- u32 flags;
- u8 display_message[2048];
-} __packed;
-
-struct heartbeat_msg_data {
- u64 seq_num;
- u32 reserved[8];
-} __packed;
-
-/* Time Sync IC defs */
-#define ICTIMESYNCFLAG_PROBE 0
-#define ICTIMESYNCFLAG_SYNC 1
-#define ICTIMESYNCFLAG_SAMPLE 2
-
-#ifdef __x86_64__
-#define WLTIMEDELTA 116444736000000000L /* in 100ns unit */
-#else
-#define WLTIMEDELTA 116444736000000000LL
-#endif
-
-struct ictimesync_data{
- u64 parenttime;
- u64 childtime;
- u64 roundtriptime;
- u8 flags;
-} __packed;
-
-/* Index for each IC struct in array hv_cb_utils[] */
-#define HV_SHUTDOWN_MSG 0
-#define HV_TIMESYNC_MSG 1
-#define HV_HEARTBEAT_MSG 2
-#define HV_KVP_MSG 3
-
-struct hyperv_service_callback {
- u8 msg_type;
- char *log_msg;
- unsigned char data[16];
- struct vmbus_channel *channel;
- void (*callback) (void *context);
-};
-
-extern void prep_negotiate_resp(struct icmsg_hdr *,
- struct icmsg_negotiate *, u8 *);
-extern void chn_cb_negotiate(void *);
-extern struct hyperv_service_callback hv_cb_utils[];
-
-#endif /* __HV_UTILS_H_ */
diff --git a/drivers/staging/hv/version_info.h b/drivers/staging/hv/version_info.h
deleted file mode 100644
index 35178f2..0000000
--- a/drivers/staging/hv/version_info.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- *
- * Copyright (c) 2009, Microsoft Corporation.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
- * Place - Suite 330, Boston, MA 02111-1307 USA.
- *
- * Authors:
- * Haiyang Zhang <haiyangz@microsoft.com>
- * Hank Janssen <hjanssen@microsoft.com>
- *
- */
-
-#ifndef __HV_VERSION_INFO
-#define __HV_VERSION_INFO
-
-/*
- * We use the same version numbering for all Hyper-V modules.
- *
- * Definition of versioning is as follows;
- *
- * Major Number Changes for these scenarios;
- * 1. When a new version of Windows Hyper-V
- * is released.
- * 2. A Major change has occurred in the
- * Linux IC's.
- * (For example the merge for the first time
- * into the kernel) Every time the Major Number
- * changes, the Revision number is reset to 0.
- * Minor Number Changes when new functionality is added
- * to the Linux IC's that is not a bug fix.
- *
- * 3.1 - Added completed hv_utils driver. Shutdown/Heartbeat/Timesync
- */
-#define HV_DRV_VERSION "3.1"
-
-
-#endif
diff --git a/drivers/staging/hv/vmbus.h b/drivers/staging/hv/vmbus.h
deleted file mode 100644
index 73087f2..0000000
--- a/drivers/staging/hv/vmbus.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- *
- * Copyright (c) 2009, Microsoft Corporation.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
- * Place - Suite 330, Boston, MA 02111-1307 USA.
- *
- * Authors:
- * Haiyang Zhang <haiyangz@microsoft.com>
- * Hank Janssen <hjanssen@microsoft.com>
- *
- */
-
-
-#ifndef _VMBUS_H_
-#define _VMBUS_H_
-
-#include <linux/device.h>
-#include "vmbus_api.h"
-
-
-
-
-static inline struct hv_device *device_to_hv_device(struct device *d)
-{
- return container_of(d, struct hv_device, device);
-}
-
-static inline struct hv_driver *drv_to_hv_drv(struct device_driver *d)
-{
- return container_of(d, struct hv_driver, driver);
-}
-
-
-/* Vmbus interface */
-int vmbus_child_driver_register(struct device_driver *drv);
-void vmbus_child_driver_unregister(struct device_driver *drv);
-
-extern struct completion hv_channel_ready;
-
-#endif /* _VMBUS_H_ */
diff --git a/drivers/staging/hv/vmbus_api.h b/drivers/staging/hv/vmbus_api.h
deleted file mode 100644
index f0d96eb..0000000
--- a/drivers/staging/hv/vmbus_api.h
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
- *
- * Copyright (c) 2009, Microsoft Corporation.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
- * Place - Suite 330, Boston, MA 02111-1307 USA.
- *
- * Authors:
- * Haiyang Zhang <haiyangz@microsoft.com>
- * Hank Janssen <hjanssen@microsoft.com>
- *
- */
-
-
-#ifndef _VMBUS_API_H_
-#define _VMBUS_API_H_
-
-#include <linux/device.h>
-#include <linux/workqueue.h>
-
-#define MAX_PAGE_BUFFER_COUNT 16
-#define MAX_MULTIPAGE_BUFFER_COUNT 32 /* 128K */
-
-#pragma pack(push, 1)
-
-/* Single-page buffer */
-struct hv_page_buffer {
- u32 len;
- u32 offset;
- u64 pfn;
-};
-
-/* Multiple-page buffer */
-struct hv_multipage_buffer {
- /* Length and Offset determines the # of pfns in the array */
- u32 len;
- u32 offset;
- u64 pfn_array[MAX_MULTIPAGE_BUFFER_COUNT];
-};
-
-/* 0x18 includes the proprietary packet header */
-#define MAX_PAGE_BUFFER_PACKET (0x18 + \
- (sizeof(struct hv_page_buffer) * \
- MAX_PAGE_BUFFER_COUNT))
-#define MAX_MULTIPAGE_BUFFER_PACKET (0x18 + \
- sizeof(struct hv_multipage_buffer))
-
-
-#pragma pack(pop)
-
-struct hv_driver;
-struct hv_device;
-
-struct hv_dev_port_info {
- u32 int_mask;
- u32 read_idx;
- u32 write_idx;
- u32 bytes_avail_toread;
- u32 bytes_avail_towrite;
-};
-
-struct hv_device_info {
- u32 chn_id;
- u32 chn_state;
- struct hv_guid chn_type;
- struct hv_guid chn_instance;
-
- u32 monitor_id;
- u32 server_monitor_pending;
- u32 server_monitor_latency;
- u32 server_monitor_conn_id;
- u32 client_monitor_pending;
- u32 client_monitor_latency;
- u32 client_monitor_conn_id;
-
- struct hv_dev_port_info inbound;
- struct hv_dev_port_info outbound;
-};
-
-/* Base driver object */
-struct hv_driver {
- const char *name;
-
- /* the device type supported by this driver */
- struct hv_guid dev_type;
-
- /*
- * Device type specific drivers (net, blk etc.)
- * need a mechanism to get a pointer to
- * device type specific driver structure given
- * a pointer to the base hyperv driver structure.
- * The current code solves this problem using
- * a hack. Support this need explicitly
- */
- void *priv;
-
- struct device_driver driver;
-
- int (*dev_add)(struct hv_device *device, void *data);
- int (*dev_rm)(struct hv_device *device);
- void (*cleanup)(struct hv_driver *driver);
-};
-
-/* Base device object */
-struct hv_device {
- /* the driver for this device */
- struct hv_driver *drv;
-
- char name[64];
-
- struct work_struct probe_failed_work_item;
-
- int probe_error;
-
- /* the device type id of this device */
- struct hv_guid dev_type;
-
- /* the device instance id of this device */
- struct hv_guid dev_instance;
-
- struct device device;
-
- struct vmbus_channel *channel;
-
- /* Device extension; */
- void *ext;
-};
-
-#endif /* _VMBUS_API_H_ */
diff --git a/drivers/staging/hv/vmbus_channel_interface.h b/drivers/staging/hv/vmbus_channel_interface.h
deleted file mode 100644
index 20ae258..0000000
--- a/drivers/staging/hv/vmbus_channel_interface.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- *
- * Copyright (c) 2009, Microsoft Corporation.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
- * Place - Suite 330, Boston, MA 02111-1307 USA.
- *
- * Authors:
- * Haiyang Zhang <haiyangz@microsoft.com>
- * Hank Janssen <hjanssen@microsoft.com>
- *
- */
-
-#ifndef __VMBUSCHANNELINTERFACE_H
-#define __VMBUSCHANNELINTERFACE_H
-
-/*
- * A revision number of vmbus that is used for ensuring both ends on a
- * partition are using compatible versions.
- */
-#define VMBUS_REVISION_NUMBER 13
-
-/* Make maximum size of pipe payload of 16K */
-#define MAX_PIPE_DATA_PAYLOAD (sizeof(u8) * 16384)
-
-/* Define PipeMode values. */
-#define VMBUS_PIPE_TYPE_BYTE 0x00000000
-#define VMBUS_PIPE_TYPE_MESSAGE 0x00000004
-
-/* The size of the user defined data buffer for non-pipe offers. */
-#define MAX_USER_DEFINED_BYTES 120
-
-/* The size of the user defined data buffer for pipe offers. */
-#define MAX_PIPE_USER_DEFINED_BYTES 116
-
-/*
- * At the center of the Channel Management library is the Channel Offer. This
- * struct contains the fundamental information about an offer.
- */
-struct vmbus_channel_offer {
- struct hv_guid if_type;
- struct hv_guid if_instance;
- u64 int_latency; /* in 100ns units */
- u32 if_revision;
- u32 server_ctx_size; /* in bytes */
- u16 chn_flags;
- u16 mmio_megabytes; /* in bytes * 1024 * 1024 */
-
- union {
- /* Non-pipes: The user has MAX_USER_DEFINED_BYTES bytes. */
- struct {
- unsigned char user_def[MAX_USER_DEFINED_BYTES];
- } std;
-
- /*
- * Pipes:
- * The following sructure is an integrated pipe protocol, which
- * is implemented on top of standard user-defined data. Pipe
- * clients have MAX_PIPE_USER_DEFINED_BYTES left for their own
- * use.
- */
- struct {
- u32 pipe_mode;
- unsigned char user_def[MAX_PIPE_USER_DEFINED_BYTES];
- } pipe;
- } u;
- u32 padding;
-} __packed;
-
-/* Server Flags */
-#define VMBUS_CHANNEL_ENUMERATE_DEVICE_INTERFACE 1
-#define VMBUS_CHANNEL_SERVER_SUPPORTS_TRANSFER_PAGES 2
-#define VMBUS_CHANNEL_SERVER_SUPPORTS_GPADLS 4
-#define VMBUS_CHANNEL_NAMED_PIPE_MODE 0x10
-#define VMBUS_CHANNEL_LOOPBACK_OFFER 0x100
-#define VMBUS_CHANNEL_PARENT_OFFER 0x200
-#define VMBUS_CHANNEL_REQUEST_MONITORED_NOTIFICATION 0x400
-
-#endif
diff --git a/drivers/staging/hv/vmbus_drv.c b/drivers/staging/hv/vmbus_drv.c
index 79089f8..ec1d38c 100644
--- a/drivers/staging/hv/vmbus_drv.c
+++ b/drivers/staging/hv/vmbus_drv.c
@@ -17,7 +17,11 @@
* Authors:
* Haiyang Zhang <haiyangz@microsoft.com>
* Hank Janssen <hjanssen@microsoft.com>
+ * K. Y. Srinivasan <kys@microsoft.com>
+ *
*/
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
#include <linux/init.h>
#include <linux/module.h>
#include <linux/device.h>
@@ -27,240 +31,27 @@
#include <linux/pci.h>
#include <linux/dmi.h>
#include <linux/slab.h>
+#include <linux/acpi.h>
+#include <acpi/acpi_bus.h>
#include <linux/completion.h>
-#include "version_info.h"
-#include "hv_api.h"
-#include "logging.h"
-#include "vmbus.h"
-#include "channel.h"
-#include "vmbus_private.h"
+
+#include "hyperv.h"
+#include "hyperv_vmbus.h"
-/* FIXME! We need to do this dynamically for PIC and APIC system */
-#define VMBUS_IRQ 0x5
-#define VMBUS_IRQ_VECTOR IRQ5_VECTOR
+static struct pci_dev *hv_pci_dev;
-/* Main vmbus driver data structure */
-struct vmbus_driver_context {
-
- struct bus_type bus;
- struct tasklet_struct msg_dpc;
- struct tasklet_struct event_dpc;
-
- /* The bus root device */
- struct hv_device device_ctx;
-};
-
-static int vmbus_match(struct device *device, struct device_driver *driver);
-static int vmbus_probe(struct device *device);
-static int vmbus_remove(struct device *device);
-static void vmbus_shutdown(struct device *device);
-static int vmbus_uevent(struct device *device, struct kobj_uevent_env *env);
-
-static irqreturn_t vmbus_isr(int irq, void *dev_id);
-
-static void vmbus_device_release(struct device *device);
-static void vmbus_bus_release(struct device *device);
-
-static ssize_t vmbus_show_device_attr(struct device *dev,
- struct device_attribute *dev_attr,
- char *buf);
-
+static struct tasklet_struct msg_dpc;
+static struct tasklet_struct event_dpc;
unsigned int vmbus_loglevel = (ALL_MODULES << 16 | INFO_LVL);
EXPORT_SYMBOL(vmbus_loglevel);
/* (ALL_MODULES << 16 | DEBUG_LVL_ENTEREXIT); */
/* (((VMBUS | VMBUS_DRV)<<16) | DEBUG_LVL_ENTEREXIT); */
-static int vmbus_irq = VMBUS_IRQ;
-
-/* Set up per device attributes in /sys/bus/vmbus/devices/<bus device> */
-static struct device_attribute vmbus_device_attrs[] = {
- __ATTR(id, S_IRUGO, vmbus_show_device_attr, NULL),
- __ATTR(state, S_IRUGO, vmbus_show_device_attr, NULL),
- __ATTR(class_id, S_IRUGO, vmbus_show_device_attr, NULL),
- __ATTR(device_id, S_IRUGO, vmbus_show_device_attr, NULL),
- __ATTR(monitor_id, S_IRUGO, vmbus_show_device_attr, NULL),
-
- __ATTR(server_monitor_pending, S_IRUGO, vmbus_show_device_attr, NULL),
- __ATTR(server_monitor_latency, S_IRUGO, vmbus_show_device_attr, NULL),
- __ATTR(server_monitor_conn_id, S_IRUGO, vmbus_show_device_attr, NULL),
-
- __ATTR(client_monitor_pending, S_IRUGO, vmbus_show_device_attr, NULL),
- __ATTR(client_monitor_latency, S_IRUGO, vmbus_show_device_attr, NULL),
- __ATTR(client_monitor_conn_id, S_IRUGO, vmbus_show_device_attr, NULL),
-
- __ATTR(out_intr_mask, S_IRUGO, vmbus_show_device_attr, NULL),
- __ATTR(out_read_index, S_IRUGO, vmbus_show_device_attr, NULL),
- __ATTR(out_write_index, S_IRUGO, vmbus_show_device_attr, NULL),
- __ATTR(out_read_bytes_avail, S_IRUGO, vmbus_show_device_attr, NULL),
- __ATTR(out_write_bytes_avail, S_IRUGO, vmbus_show_device_attr, NULL),
-
- __ATTR(in_intr_mask, S_IRUGO, vmbus_show_device_attr, NULL),
- __ATTR(in_read_index, S_IRUGO, vmbus_show_device_attr, NULL),
- __ATTR(in_write_index, S_IRUGO, vmbus_show_device_attr, NULL),
- __ATTR(in_read_bytes_avail, S_IRUGO, vmbus_show_device_attr, NULL),
- __ATTR(in_write_bytes_avail, S_IRUGO, vmbus_show_device_attr, NULL),
- __ATTR_NULL
-};
-
-/* The one and only one */
-static struct vmbus_driver_context vmbus_drv = {
- .bus.name = "vmbus",
- .bus.match = vmbus_match,
- .bus.shutdown = vmbus_shutdown,
- .bus.remove = vmbus_remove,
- .bus.probe = vmbus_probe,
- .bus.uevent = vmbus_uevent,
- .bus.dev_attrs = vmbus_device_attrs,
-};
-
-static const char *driver_name = "hyperv";
-
-/*
- * Windows vmbus does not defined this.
- * We defined this to be consistent with other devices
- */
-/* {c5295816-f63a-4d5f-8d1a-4daf999ca185} */
-static const struct hv_guid device_type = {
- .data = {
- 0x16, 0x58, 0x29, 0xc5, 0x3a, 0xf6, 0x5f, 0x4d,
- 0x8d, 0x1a, 0x4d, 0xaf, 0x99, 0x9c, 0xa1, 0x85
- }
-};
-
-/* {ac3760fc-9adf-40aa-9427-a70ed6de95c5} */
-static const struct hv_guid device_id = {
- .data = {
- 0xfc, 0x60, 0x37, 0xac, 0xdf, 0x9a, 0xaa, 0x40,
- 0x94, 0x27, 0xa7, 0x0e, 0xd6, 0xde, 0x95, 0xc5
- }
-};
-
-static struct hv_device *vmbus_device; /* vmbus root device */
-
-
-/*
- * vmbus_dev_add - Callback when the root bus device is added
- */
-static int vmbus_dev_add(struct hv_device *dev, void *info)
-{
- u32 *irqvector = info;
- int ret;
-
- vmbus_device = dev;
-
- memcpy(&vmbus_device->dev_type, &device_type, sizeof(struct hv_guid));
- memcpy(&vmbus_device->dev_instance, &device_id,
- sizeof(struct hv_guid));
-
- /* strcpy(dev->name, "vmbus"); */
- /* SynIC setup... */
- on_each_cpu(hv_synic_init, (void *)irqvector, 1);
-
- /* Connect to VMBus in the root partition */
- ret = vmbus_connect();
-
- /* VmbusSendEvent(device->localPortId+1); */
- return ret;
-}
-
-
-struct onmessage_work_context {
- struct work_struct work;
- struct hv_message msg;
-};
-
-static void vmbus_onmessage_work(struct work_struct *work)
-{
- struct onmessage_work_context *ctx;
-
- ctx = container_of(work, struct onmessage_work_context,
- work);
- vmbus_onmessage(&ctx->msg);
- kfree(ctx);
-}
-
-/*
- * vmbus_on_msg_dpc - DPC routine to handle messages from the hypervisior
- */
-static void vmbus_on_msg_dpc(unsigned long data)
-{
- int cpu = smp_processor_id();
- void *page_addr = hv_context.synic_message_page[cpu];
- struct hv_message *msg = (struct hv_message *)page_addr +
- VMBUS_MESSAGE_SINT;
- struct onmessage_work_context *ctx;
-
- while (1) {
- if (msg->header.message_type == HVMSG_NONE) {
- /* no msg */
- break;
- } else {
- ctx = kmalloc(sizeof(*ctx), GFP_ATOMIC);
- if (ctx == NULL)
- continue;
- INIT_WORK(&ctx->work, vmbus_onmessage_work);
- memcpy(&ctx->msg, msg, sizeof(*msg));
- queue_work(vmbus_connection.work_queue, &ctx->work);
- }
-
- msg->header.message_type = HVMSG_NONE;
-
- /*
- * Make sure the write to MessageType (ie set to
- * HVMSG_NONE) happens before we read the
- * MessagePending and EOMing. Otherwise, the EOMing
- * will not deliver any more messages since there is
- * no empty slot
- */
- mb();
-
- if (msg->header.message_flags.msg_pending) {
- /*
- * This will cause message queue rescan to
- * possibly deliver another msg from the
- * hypervisor
- */
- wrmsrl(HV_X64_MSR_EOM, 0);
- }
- }
-}
-
-/*
- * vmbus_on_isr - ISR routine
- */
-static int vmbus_on_isr(void)
-{
- int ret = 0;
- int cpu = smp_processor_id();
- void *page_addr;
- struct hv_message *msg;
- union hv_synic_event_flags *event;
-
- page_addr = hv_context.synic_message_page[cpu];
- msg = (struct hv_message *)page_addr + VMBUS_MESSAGE_SINT;
-
- /* Check if there are actual msgs to be process */
- if (msg->header.message_type != HVMSG_NONE) {
- DPRINT_DBG(VMBUS, "received msg type %d size %d",
- msg->header.message_type,
- msg->header.payload_size);
- ret |= 0x1;
- }
-
- /* TODO: Check if there are events to be process */
- page_addr = hv_context.synic_event_page[cpu];
- event = (union hv_synic_event_flags *)page_addr + VMBUS_MESSAGE_SINT;
-
- /* Since we are a child, we only need to check bit 0 */
- if (sync_test_and_clear_bit(0, (unsigned long *) &event->flags32[0])) {
- DPRINT_DBG(VMBUS, "received event %d", event->flags32[0]);
- ret |= 0x2;
- }
-
- return ret;
-}
+static int pci_probe_error;
+static struct completion probe_event;
+static int irq;
static void get_channel_info(struct hv_device *device,
struct hv_device_info *info)
@@ -411,308 +202,36 @@
}
}
-/*
- * vmbus_bus_init -Main vmbus driver initialization routine.
- *
- * Here, we
- * - initialize the vmbus driver context
- * - setup various driver entry points
- * - invoke the vmbus hv main init routine
- * - get the irq resource
- * - invoke the vmbus to add the vmbus root device
- * - setup the vmbus root device
- * - retrieve the channel offers
- */
-static int vmbus_bus_init(void)
-{
- struct vmbus_driver_context *vmbus_drv_ctx = &vmbus_drv;
- struct hv_device *dev_ctx = &vmbus_drv.device_ctx;
- int ret;
- unsigned int vector;
+/* Set up per device attributes in /sys/bus/vmbus/devices/<bus device> */
+static struct device_attribute vmbus_device_attrs[] = {
+ __ATTR(id, S_IRUGO, vmbus_show_device_attr, NULL),
+ __ATTR(state, S_IRUGO, vmbus_show_device_attr, NULL),
+ __ATTR(class_id, S_IRUGO, vmbus_show_device_attr, NULL),
+ __ATTR(device_id, S_IRUGO, vmbus_show_device_attr, NULL),
+ __ATTR(monitor_id, S_IRUGO, vmbus_show_device_attr, NULL),
- DPRINT_INFO(VMBUS, "+++++++ HV Driver version = %s +++++++",
- HV_DRV_VERSION);
- DPRINT_INFO(VMBUS, "+++++++ Vmbus supported version = %d +++++++",
- VMBUS_REVISION_NUMBER);
- DPRINT_INFO(VMBUS, "+++++++ Vmbus using SINT %d +++++++",
- VMBUS_MESSAGE_SINT);
- DPRINT_DBG(VMBUS, "sizeof(vmbus_channel_packet_page_buffer)=%zd, "
- "sizeof(VMBUS_CHANNEL_PACKET_MULITPAGE_BUFFER)=%zd",
- sizeof(struct vmbus_channel_packet_page_buffer),
- sizeof(struct vmbus_channel_packet_multipage_buffer));
+ __ATTR(server_monitor_pending, S_IRUGO, vmbus_show_device_attr, NULL),
+ __ATTR(server_monitor_latency, S_IRUGO, vmbus_show_device_attr, NULL),
+ __ATTR(server_monitor_conn_id, S_IRUGO, vmbus_show_device_attr, NULL),
+ __ATTR(client_monitor_pending, S_IRUGO, vmbus_show_device_attr, NULL),
+ __ATTR(client_monitor_latency, S_IRUGO, vmbus_show_device_attr, NULL),
+ __ATTR(client_monitor_conn_id, S_IRUGO, vmbus_show_device_attr, NULL),
- /* Hypervisor initialization...setup hypercall page..etc */
- ret = hv_init();
- if (ret != 0) {
- DPRINT_ERR(VMBUS, "Unable to initialize the hypervisor - 0x%x",
- ret);
- goto cleanup;
- }
+ __ATTR(out_intr_mask, S_IRUGO, vmbus_show_device_attr, NULL),
+ __ATTR(out_read_index, S_IRUGO, vmbus_show_device_attr, NULL),
+ __ATTR(out_write_index, S_IRUGO, vmbus_show_device_attr, NULL),
+ __ATTR(out_read_bytes_avail, S_IRUGO, vmbus_show_device_attr, NULL),
+ __ATTR(out_write_bytes_avail, S_IRUGO, vmbus_show_device_attr, NULL),
+ __ATTR(in_intr_mask, S_IRUGO, vmbus_show_device_attr, NULL),
+ __ATTR(in_read_index, S_IRUGO, vmbus_show_device_attr, NULL),
+ __ATTR(in_write_index, S_IRUGO, vmbus_show_device_attr, NULL),
+ __ATTR(in_read_bytes_avail, S_IRUGO, vmbus_show_device_attr, NULL),
+ __ATTR(in_write_bytes_avail, S_IRUGO, vmbus_show_device_attr, NULL),
+ __ATTR_NULL
+};
- vmbus_drv_ctx->bus.name = driver_name;
-
- /* Initialize the bus context */
- tasklet_init(&vmbus_drv_ctx->msg_dpc, vmbus_on_msg_dpc,
- (unsigned long)NULL);
- tasklet_init(&vmbus_drv_ctx->event_dpc, vmbus_on_event,
- (unsigned long)NULL);
-
- /* Now, register the bus with LDM */
- ret = bus_register(&vmbus_drv_ctx->bus);
- if (ret) {
- ret = -1;
- goto cleanup;
- }
-
- /* Get the interrupt resource */
- ret = request_irq(vmbus_irq, vmbus_isr, IRQF_SAMPLE_RANDOM,
- driver_name, NULL);
-
- if (ret != 0) {
- DPRINT_ERR(VMBUS_DRV, "ERROR - Unable to request IRQ %d",
- vmbus_irq);
-
- bus_unregister(&vmbus_drv_ctx->bus);
-
- ret = -1;
- goto cleanup;
- }
- vector = VMBUS_IRQ_VECTOR;
-
- DPRINT_INFO(VMBUS_DRV, "irq 0x%x vector 0x%x", vmbus_irq, vector);
-
- /* Add the root device */
- memset(dev_ctx, 0, sizeof(struct hv_device));
-
- ret = vmbus_dev_add(dev_ctx, &vector);
- if (ret != 0) {
- DPRINT_ERR(VMBUS_DRV,
- "ERROR - Unable to add vmbus root device");
-
- free_irq(vmbus_irq, NULL);
-
- bus_unregister(&vmbus_drv_ctx->bus);
-
- ret = -1;
- goto cleanup;
- }
- /* strcpy(dev_ctx->device.bus_id, dev_ctx->device_obj.name); */
- dev_set_name(&dev_ctx->device, "vmbus_0_0");
-
- /* No need to bind a driver to the root device. */
- dev_ctx->device.parent = NULL;
- /* NULL; vmbus_remove() does not get invoked */
- dev_ctx->device.bus = &vmbus_drv_ctx->bus;
-
- /* Setup the device dispatch table */
- dev_ctx->device.release = vmbus_bus_release;
-
- /* register the root device */
- ret = device_register(&dev_ctx->device);
- if (ret) {
- DPRINT_ERR(VMBUS_DRV,
- "ERROR - Unable to register vmbus root device");
-
- free_irq(vmbus_irq, NULL);
- bus_unregister(&vmbus_drv_ctx->bus);
-
- ret = -1;
- goto cleanup;
- }
-
- vmbus_request_offers();
- wait_for_completion(&hv_channel_ready);
-
-cleanup:
- return ret;
-}
-
-/*
- * vmbus_bus_exit - Terminate the vmbus driver.
- *
- * This routine is opposite of vmbus_bus_init()
- */
-static void vmbus_bus_exit(void)
-{
- struct vmbus_driver_context *vmbus_drv_ctx = &vmbus_drv;
-
- struct hv_device *dev_ctx = &vmbus_drv.device_ctx;
-
- vmbus_release_unattached_channels();
- vmbus_disconnect();
- on_each_cpu(hv_synic_cleanup, NULL, 1);
-
- hv_cleanup();
-
- /* Unregister the root bus device */
- device_unregister(&dev_ctx->device);
-
- bus_unregister(&vmbus_drv_ctx->bus);
-
- free_irq(vmbus_irq, NULL);
-
- tasklet_kill(&vmbus_drv_ctx->msg_dpc);
- tasklet_kill(&vmbus_drv_ctx->event_dpc);
-}
-
-
-/**
- * vmbus_child_driver_register() - Register a vmbus's child driver
- * @drv: Pointer to driver structure you want to register
- *
- *
- * Registers the given driver with Linux through the 'driver_register()' call
- * And sets up the hyper-v vmbus handling for this driver.
- * It will return the state of the 'driver_register()' call.
- *
- * Mainly used by Hyper-V drivers.
- */
-int vmbus_child_driver_register(struct device_driver *drv)
-{
- int ret;
-
- DPRINT_INFO(VMBUS_DRV, "child driver (%p) registering - name %s",
- drv, drv->name);
-
- /* The child driver on this vmbus */
- drv->bus = &vmbus_drv.bus;
-
- ret = driver_register(drv);
-
- vmbus_request_offers();
-
- return ret;
-}
-EXPORT_SYMBOL(vmbus_child_driver_register);
-
-/**
- * vmbus_child_driver_unregister() - Unregister a vmbus's child driver
- * @drv: Pointer to driver structure you want to un-register
- *
- *
- * Un-register the given driver with Linux through the 'driver_unregister()'
- * call. And ungegisters the driver from the Hyper-V vmbus handler.
- *
- * Mainly used by Hyper-V drivers.
- */
-void vmbus_child_driver_unregister(struct device_driver *drv)
-{
- DPRINT_INFO(VMBUS_DRV, "child driver (%p) unregistering - name %s",
- drv, drv->name);
-
- driver_unregister(drv);
-
- drv->bus = NULL;
-}
-EXPORT_SYMBOL(vmbus_child_driver_unregister);
-
-/*
- * vmbus_child_device_create - Creates and registers a new child device
- * on the vmbus.
- */
-struct hv_device *vmbus_child_device_create(struct hv_guid *type,
- struct hv_guid *instance,
- struct vmbus_channel *channel)
-{
- struct hv_device *child_device_obj;
-
- /* Allocate the new child device */
- child_device_obj = kzalloc(sizeof(struct hv_device), GFP_KERNEL);
- if (!child_device_obj) {
- DPRINT_ERR(VMBUS_DRV,
- "unable to allocate device_context for child device");
- return NULL;
- }
-
- DPRINT_DBG(VMBUS_DRV, "child device (%p) allocated - "
- "type {%02x%02x%02x%02x-%02x%02x-%02x%02x-"
- "%02x%02x%02x%02x%02x%02x%02x%02x},"
- "id {%02x%02x%02x%02x-%02x%02x-%02x%02x-"
- "%02x%02x%02x%02x%02x%02x%02x%02x}",
- &child_device_obj->device,
- type->data[3], type->data[2], type->data[1], type->data[0],
- type->data[5], type->data[4], type->data[7], type->data[6],
- type->data[8], type->data[9], type->data[10], type->data[11],
- type->data[12], type->data[13], type->data[14], type->data[15],
- instance->data[3], instance->data[2],
- instance->data[1], instance->data[0],
- instance->data[5], instance->data[4],
- instance->data[7], instance->data[6],
- instance->data[8], instance->data[9],
- instance->data[10], instance->data[11],
- instance->data[12], instance->data[13],
- instance->data[14], instance->data[15]);
-
- child_device_obj->channel = channel;
- memcpy(&child_device_obj->dev_type, type, sizeof(struct hv_guid));
- memcpy(&child_device_obj->dev_instance, instance,
- sizeof(struct hv_guid));
-
-
- return child_device_obj;
-}
-
-/*
- * vmbus_child_device_register - Register the child device
- */
-int vmbus_child_device_register(struct hv_device *child_device_obj)
-{
- int ret = 0;
-
- static atomic_t device_num = ATOMIC_INIT(0);
-
- DPRINT_DBG(VMBUS_DRV, "child device (%p) registering",
- child_device_obj);
-
- /* Set the device name. Otherwise, device_register() will fail. */
- dev_set_name(&child_device_obj->device, "vmbus_0_%d",
- atomic_inc_return(&device_num));
-
- /* The new device belongs to this bus */
- child_device_obj->device.bus = &vmbus_drv.bus; /* device->dev.bus; */
- child_device_obj->device.parent = &vmbus_device->device;
- child_device_obj->device.release = vmbus_device_release;
-
- /*
- * Register with the LDM. This will kick off the driver/device
- * binding...which will eventually call vmbus_match() and vmbus_probe()
- */
- ret = device_register(&child_device_obj->device);
-
- /* vmbus_probe() error does not get propergate to device_register(). */
- ret = child_device_obj->probe_error;
-
- if (ret)
- DPRINT_ERR(VMBUS_DRV, "unable to register child device (%p)",
- &child_device_obj->device);
- else
- DPRINT_INFO(VMBUS_DRV, "child device (%p) registered",
- &child_device_obj->device);
-
- return ret;
-}
-
-/*
- * vmbus_child_device_unregister - Remove the specified child device
- * from the vmbus.
- */
-void vmbus_child_device_unregister(struct hv_device *device_obj)
-{
-
- DPRINT_INFO(VMBUS_DRV, "unregistering child device (%p)",
- &device_obj->device);
-
- /*
- * Kick off the process of unregistering the device.
- * This will call vmbus_remove() and eventually vmbus_device_release()
- */
- device_unregister(&device_obj->device);
-
- DPRINT_INFO(VMBUS_DRV, "child device (%p) unregistered",
- &device_obj->device);
-}
/*
* vmbus_uevent - add uevent for our device
@@ -726,21 +245,6 @@
struct hv_device *dev = device_to_hv_device(device);
int ret;
- DPRINT_INFO(VMBUS_DRV, "generating uevent - VMBUS_DEVICE_CLASS_GUID={"
- "%02x%02x%02x%02x-%02x%02x-%02x%02x-"
- "%02x%02x%02x%02x%02x%02x%02x%02x}",
- dev->dev_type.data[3], dev->dev_type.data[2],
- dev->dev_type.data[1], dev->dev_type.data[0],
- dev->dev_type.data[5], dev->dev_type.data[4],
- dev->dev_type.data[7], dev->dev_type.data[6],
- dev->dev_type.data[8], dev->dev_type.data[9],
- dev->dev_type.data[10],
- dev->dev_type.data[11],
- dev->dev_type.data[12],
- dev->dev_type.data[13],
- dev->dev_type.data[14],
- dev->dev_type.data[15]);
-
ret = add_uevent_var(env, "VMBUS_DEVICE_CLASS_GUID={"
"%02x%02x%02x%02x-%02x%02x-%02x%02x-"
"%02x%02x%02x%02x%02x%02x%02x%02x}",
@@ -789,6 +293,7 @@
return 0;
}
+
/*
* vmbus_match - Attempt to match the specified device to the specified driver
*/
@@ -800,40 +305,13 @@
/* We found our driver ? */
if (memcmp(&device_ctx->dev_type, &drv->dev_type,
- sizeof(struct hv_guid)) == 0) {
-
- device_ctx->drv = drv->priv;
- DPRINT_INFO(VMBUS_DRV,
- "device object (%p) set to driver object (%p)",
- &device_ctx,
- device_ctx->drv);
-
+ sizeof(struct hv_guid)) == 0)
match = 1;
- }
+
return match;
}
/*
- * vmbus_probe_failed_cb - Callback when a driver probe failed in vmbus_probe()
- *
- * We need a callback because we cannot invoked device_unregister() inside
- * vmbus_probe() since vmbus_probe() may be invoked inside device_register()
- * i.e. we cannot call device_unregister() inside device_register()
- */
-static void vmbus_probe_failed_cb(struct work_struct *context)
-{
- struct hv_device *device_ctx = (struct hv_device *)context;
-
- /*
- * Kick off the process of unregistering the device.
- * This will call vmbus_remove() and eventually vmbus_device_release()
- */
- device_unregister(&device_ctx->device);
-
- /* put_device(&device_ctx->device); */
-}
-
-/*
* vmbus_probe - Add the new vmbus's child device
*/
static int vmbus_probe(struct device *child_device)
@@ -843,23 +321,15 @@
drv_to_hv_drv(child_device->driver);
struct hv_device *dev = device_to_hv_device(child_device);
- /* Let the specific open-source driver handles the probe if it can */
- if (drv->driver.probe) {
- ret = dev->probe_error =
- drv->driver.probe(child_device);
- if (ret != 0) {
- DPRINT_ERR(VMBUS_DRV, "probe() failed for device %s "
- "(%p) on driver %s (%d)...",
- dev_name(child_device), child_device,
- child_device->driver->name, ret);
+ if (drv->probe) {
+ ret = drv->probe(dev);
+ if (ret != 0)
+ pr_err("probe failed for device %s (%d)\n",
+ dev_name(child_device), ret);
- INIT_WORK(&dev->probe_failed_work_item,
- vmbus_probe_failed_cb);
- schedule_work(&dev->probe_failed_work_item);
- }
} else {
- DPRINT_ERR(VMBUS_DRV, "probe() method not set for driver - %s",
- child_device->driver->name);
+ pr_err("probe not set for driver %s\n",
+ dev_name(child_device));
ret = -1;
}
return ret;
@@ -873,28 +343,16 @@
int ret;
struct hv_driver *drv;
- /* Special case root bus device */
- if (child_device->parent == NULL) {
- /*
- * No-op since it is statically defined and handle in
- * vmbus_bus_exit()
- */
- return 0;
- }
+ struct hv_device *dev = device_to_hv_device(child_device);
if (child_device->driver) {
drv = drv_to_hv_drv(child_device->driver);
- /*
- * Let the specific open-source driver handles the removal if
- * it can
- */
- if (drv->driver.remove) {
- ret = drv->driver.remove(child_device);
+ if (drv->remove) {
+ ret = drv->remove(dev);
} else {
- DPRINT_ERR(VMBUS_DRV,
- "remove() method not set for driver - %s",
- child_device->driver->name);
+ pr_err("remove not set for driver %s\n",
+ dev_name(child_device));
ret = -1;
}
}
@@ -902,21 +360,15 @@
return 0;
}
+
/*
* vmbus_shutdown - Shutdown a vmbus device
*/
static void vmbus_shutdown(struct device *child_device)
{
struct hv_driver *drv;
+ struct hv_device *dev = device_to_hv_device(child_device);
- /* Special case root bus device */
- if (child_device->parent == NULL) {
- /*
- * No-op since it is statically defined and handle in
- * vmbus_bus_exit()
- */
- return;
- }
/* The device may not be attached yet */
if (!child_device->driver)
@@ -924,24 +376,12 @@
drv = drv_to_hv_drv(child_device->driver);
- /* Let the specific open-source driver handles the removal if it can */
- if (drv->driver.shutdown)
- drv->driver.shutdown(child_device);
+ if (drv->shutdown)
+ drv->shutdown(dev);
return;
}
-/*
- * vmbus_bus_release - Final callback release of the vmbus root device
- */
-static void vmbus_bus_release(struct device *device)
-{
- /* FIXME */
- /* Empty release functions are a bug, or a major sign
- * of a problem design, this MUST BE FIXED! */
- dev_err(device, "%s needs to be fixed!\n", __func__);
- WARN_ON(1);
-}
/*
* vmbus_device_release - Final callback release of the vmbus child device
@@ -952,9 +392,111 @@
kfree(device_ctx);
- /* !!DO NOT REFERENCE device_ctx anymore at this point!! */
}
+/* The one and only one */
+static struct bus_type hv_bus = {
+ .name = "vmbus",
+ .match = vmbus_match,
+ .shutdown = vmbus_shutdown,
+ .remove = vmbus_remove,
+ .probe = vmbus_probe,
+ .uevent = vmbus_uevent,
+ .dev_attrs = vmbus_device_attrs,
+};
+
+static const char *driver_name = "hyperv";
+
+
+struct onmessage_work_context {
+ struct work_struct work;
+ struct hv_message msg;
+};
+
+static void vmbus_onmessage_work(struct work_struct *work)
+{
+ struct onmessage_work_context *ctx;
+
+ ctx = container_of(work, struct onmessage_work_context,
+ work);
+ vmbus_onmessage(&ctx->msg);
+ kfree(ctx);
+}
+
+/*
+ * vmbus_on_msg_dpc - DPC routine to handle messages from the hypervisior
+ */
+static void vmbus_on_msg_dpc(unsigned long data)
+{
+ int cpu = smp_processor_id();
+ void *page_addr = hv_context.synic_message_page[cpu];
+ struct hv_message *msg = (struct hv_message *)page_addr +
+ VMBUS_MESSAGE_SINT;
+ struct onmessage_work_context *ctx;
+
+ while (1) {
+ if (msg->header.message_type == HVMSG_NONE) {
+ /* no msg */
+ break;
+ } else {
+ ctx = kmalloc(sizeof(*ctx), GFP_ATOMIC);
+ if (ctx == NULL)
+ continue;
+ INIT_WORK(&ctx->work, vmbus_onmessage_work);
+ memcpy(&ctx->msg, msg, sizeof(*msg));
+ queue_work(vmbus_connection.work_queue, &ctx->work);
+ }
+
+ msg->header.message_type = HVMSG_NONE;
+
+ /*
+ * Make sure the write to MessageType (ie set to
+ * HVMSG_NONE) happens before we read the
+ * MessagePending and EOMing. Otherwise, the EOMing
+ * will not deliver any more messages since there is
+ * no empty slot
+ */
+ mb();
+
+ if (msg->header.message_flags.msg_pending) {
+ /*
+ * This will cause message queue rescan to
+ * possibly deliver another msg from the
+ * hypervisor
+ */
+ wrmsrl(HV_X64_MSR_EOM, 0);
+ }
+ }
+}
+
+/*
+ * vmbus_on_isr - ISR routine
+ */
+static int vmbus_on_isr(void)
+{
+ int ret = 0;
+ int cpu = smp_processor_id();
+ void *page_addr;
+ struct hv_message *msg;
+ union hv_synic_event_flags *event;
+
+ page_addr = hv_context.synic_message_page[cpu];
+ msg = (struct hv_message *)page_addr + VMBUS_MESSAGE_SINT;
+
+ /* Check if there are actual msgs to be process */
+ if (msg->header.message_type != HVMSG_NONE)
+ ret |= 0x1;
+
+ /* TODO: Check if there are events to be process */
+ page_addr = hv_context.synic_event_page[cpu];
+ event = (union hv_synic_event_flags *)page_addr + VMBUS_MESSAGE_SINT;
+
+ /* Since we are a child, we only need to check bit 0 */
+ if (sync_test_and_clear_bit(0, (unsigned long *) &event->flags32[0]))
+ ret |= 0x2;
+
+ return ret;
+}
static irqreturn_t vmbus_isr(int irq, void *dev_id)
@@ -966,10 +508,10 @@
/* Schedules a dpc if necessary */
if (ret > 0) {
if (test_bit(0, (unsigned long *)&ret))
- tasklet_schedule(&vmbus_drv.msg_dpc);
+ tasklet_schedule(&msg_dpc);
if (test_bit(1, (unsigned long *)&ret))
- tasklet_schedule(&vmbus_drv.event_dpc);
+ tasklet_schedule(&event_dpc);
return IRQ_HANDLED;
} else {
@@ -977,36 +519,291 @@
}
}
-static struct dmi_system_id __initdata microsoft_hv_dmi_table[] = {
- {
- .ident = "Hyper-V",
- .matches = {
- DMI_MATCH(DMI_SYS_VENDOR, "Microsoft Corporation"),
- DMI_MATCH(DMI_PRODUCT_NAME, "Virtual Machine"),
- DMI_MATCH(DMI_BOARD_NAME, "Virtual Machine"),
- },
- },
- { },
-};
-MODULE_DEVICE_TABLE(dmi, microsoft_hv_dmi_table);
-
-static int __init vmbus_init(void)
+/*
+ * vmbus_bus_init -Main vmbus driver initialization routine.
+ *
+ * Here, we
+ * - initialize the vmbus driver context
+ * - invoke the vmbus hv main init routine
+ * - get the irq resource
+ * - retrieve the channel offers
+ */
+static int vmbus_bus_init(struct pci_dev *pdev)
{
- DPRINT_INFO(VMBUS_DRV,
- "Vmbus initializing.... current log level 0x%x (%x,%x)",
- vmbus_loglevel, HIWORD(vmbus_loglevel), LOWORD(vmbus_loglevel));
- /* Todo: it is used for loglevel, to be ported to new kernel. */
+ int ret;
+ unsigned int vector;
- if (!dmi_check_system(microsoft_hv_dmi_table))
- return -ENODEV;
+ /* Hypervisor initialization...setup hypercall page..etc */
+ ret = hv_init();
+ if (ret != 0) {
+ pr_err("Unable to initialize the hypervisor - 0x%x\n", ret);
+ goto cleanup;
+ }
- return vmbus_bus_init();
+ /* Initialize the bus context */
+ tasklet_init(&msg_dpc, vmbus_on_msg_dpc, 0);
+ tasklet_init(&event_dpc, vmbus_on_event, 0);
+
+ /* Now, register the bus with LDM */
+ ret = bus_register(&hv_bus);
+ if (ret) {
+ ret = -1;
+ goto cleanup;
+ }
+
+ /* Get the interrupt resource */
+ ret = request_irq(pdev->irq, vmbus_isr,
+ IRQF_SHARED | IRQF_SAMPLE_RANDOM,
+ driver_name, pdev);
+
+ if (ret != 0) {
+ pr_err("Unable to request IRQ %d\n",
+ pdev->irq);
+
+ bus_unregister(&hv_bus);
+
+ ret = -1;
+ goto cleanup;
+ }
+
+ vector = IRQ0_VECTOR + pdev->irq;
+
+ /*
+ * Notify the hypervisor of our irq and
+ * connect to the host.
+ */
+ on_each_cpu(hv_synic_init, (void *)&vector, 1);
+ ret = vmbus_connect();
+ if (ret) {
+ free_irq(pdev->irq, pdev);
+ bus_unregister(&hv_bus);
+ goto cleanup;
+ }
+
+
+ vmbus_request_offers();
+
+cleanup:
+ return ret;
}
-static void __exit vmbus_exit(void)
+/**
+ * vmbus_child_driver_register() - Register a vmbus's child driver
+ * @drv: Pointer to driver structure you want to register
+ *
+ *
+ * Registers the given driver with Linux through the 'driver_register()' call
+ * And sets up the hyper-v vmbus handling for this driver.
+ * It will return the state of the 'driver_register()' call.
+ *
+ * Mainly used by Hyper-V drivers.
+ */
+int vmbus_child_driver_register(struct device_driver *drv)
{
- vmbus_bus_exit();
- /* Todo: it is used for loglevel, to be ported to new kernel. */
+ int ret;
+
+ pr_info("child driver registering - name %s\n", drv->name);
+
+ /* The child driver on this vmbus */
+ drv->bus = &hv_bus;
+
+ ret = driver_register(drv);
+
+ vmbus_request_offers();
+
+ return ret;
+}
+EXPORT_SYMBOL(vmbus_child_driver_register);
+
+/**
+ * vmbus_child_driver_unregister() - Unregister a vmbus's child driver
+ * @drv: Pointer to driver structure you want to un-register
+ *
+ *
+ * Un-register the given driver with Linux through the 'driver_unregister()'
+ * call. And ungegisters the driver from the Hyper-V vmbus handler.
+ *
+ * Mainly used by Hyper-V drivers.
+ */
+void vmbus_child_driver_unregister(struct device_driver *drv)
+{
+ pr_info("child driver unregistering - name %s\n", drv->name);
+
+ driver_unregister(drv);
+
+ drv->bus = NULL;
+}
+EXPORT_SYMBOL(vmbus_child_driver_unregister);
+
+/*
+ * vmbus_child_device_create - Creates and registers a new child device
+ * on the vmbus.
+ */
+struct hv_device *vmbus_child_device_create(struct hv_guid *type,
+ struct hv_guid *instance,
+ struct vmbus_channel *channel)
+{
+ struct hv_device *child_device_obj;
+
+ /* Allocate the new child device */
+ child_device_obj = kzalloc(sizeof(struct hv_device), GFP_KERNEL);
+ if (!child_device_obj) {
+ pr_err("Unable to allocate device object for child device\n");
+ return NULL;
+ }
+
+ child_device_obj->channel = channel;
+ memcpy(&child_device_obj->dev_type, type, sizeof(struct hv_guid));
+ memcpy(&child_device_obj->dev_instance, instance,
+ sizeof(struct hv_guid));
+
+
+ return child_device_obj;
+}
+
+/*
+ * vmbus_child_device_register - Register the child device
+ */
+int vmbus_child_device_register(struct hv_device *child_device_obj)
+{
+ int ret = 0;
+
+ static atomic_t device_num = ATOMIC_INIT(0);
+
+ /* Set the device name. Otherwise, device_register() will fail. */
+ dev_set_name(&child_device_obj->device, "vmbus_0_%d",
+ atomic_inc_return(&device_num));
+
+ /* The new device belongs to this bus */
+ child_device_obj->device.bus = &hv_bus; /* device->dev.bus; */
+ child_device_obj->device.parent = &hv_pci_dev->dev;
+ child_device_obj->device.release = vmbus_device_release;
+
+ /*
+ * Register with the LDM. This will kick off the driver/device
+ * binding...which will eventually call vmbus_match() and vmbus_probe()
+ */
+ ret = device_register(&child_device_obj->device);
+
+ if (ret)
+ pr_err("Unable to register child device\n");
+ else
+ pr_info("child device %s registered\n",
+ dev_name(&child_device_obj->device));
+
+ return ret;
+}
+
+/*
+ * vmbus_child_device_unregister - Remove the specified child device
+ * from the vmbus.
+ */
+void vmbus_child_device_unregister(struct hv_device *device_obj)
+{
+ /*
+ * Kick off the process of unregistering the device.
+ * This will call vmbus_remove() and eventually vmbus_device_release()
+ */
+ device_unregister(&device_obj->device);
+
+ pr_info("child device %s unregistered\n",
+ dev_name(&device_obj->device));
+}
+
+
+/*
+ * VMBUS is an acpi enumerated device. Get the the IRQ information
+ * from DSDT.
+ */
+
+static acpi_status vmbus_walk_resources(struct acpi_resource *res, void *irq)
+{
+
+ if (res->type == ACPI_RESOURCE_TYPE_IRQ) {
+ struct acpi_resource_irq *irqp;
+ irqp = &res->data.irq;
+
+ *((unsigned int *)irq) = irqp->interrupts[0];
+ }
+
+ return AE_OK;
+}
+
+static int vmbus_acpi_add(struct acpi_device *device)
+{
+ acpi_status result;
+
+ result =
+ acpi_walk_resources(device->handle, METHOD_NAME__CRS,
+ vmbus_walk_resources, &irq);
+
+ if (ACPI_FAILURE(result)) {
+ complete(&probe_event);
+ return -ENODEV;
+ }
+ complete(&probe_event);
+ return 0;
+}
+
+static const struct acpi_device_id vmbus_acpi_device_ids[] = {
+ {"VMBUS", 0},
+ {"", 0},
+};
+MODULE_DEVICE_TABLE(acpi, vmbus_acpi_device_ids);
+
+static struct acpi_driver vmbus_acpi_driver = {
+ .name = "vmbus",
+ .ids = vmbus_acpi_device_ids,
+ .ops = {
+ .add = vmbus_acpi_add,
+ },
+};
+
+static int vmbus_acpi_init(void)
+{
+ int result;
+
+
+ result = acpi_bus_register_driver(&vmbus_acpi_driver);
+ if (result < 0)
+ return result;
+
+ return 0;
+}
+
+static void vmbus_acpi_exit(void)
+{
+ acpi_bus_unregister_driver(&vmbus_acpi_driver);
+
+ return;
+}
+
+
+static int __devinit hv_pci_probe(struct pci_dev *pdev,
+ const struct pci_device_id *ent)
+{
+ hv_pci_dev = pdev;
+
+ pci_probe_error = pci_enable_device(pdev);
+ if (pci_probe_error)
+ goto probe_cleanup;
+
+ /*
+ * If the PCI sub-sytem did not assign us an
+ * irq, use the bios provided one.
+ */
+
+ if (pdev->irq == 0)
+ pdev->irq = irq;
+
+ pci_probe_error = vmbus_bus_init(pdev);
+
+ if (pci_probe_error)
+ pci_disable_device(pdev);
+
+probe_cleanup:
+ complete(&probe_event);
+ return pci_probe_error;
}
/*
@@ -1021,10 +818,53 @@
};
MODULE_DEVICE_TABLE(pci, microsoft_hv_pci_table);
+static struct pci_driver hv_bus_driver = {
+ .name = "hv_bus",
+ .probe = hv_pci_probe,
+ .id_table = microsoft_hv_pci_table,
+};
+
+static int __init hv_pci_init(void)
+{
+ int ret;
+
+ init_completion(&probe_event);
+
+ /*
+ * Get irq resources first.
+ */
+
+ ret = vmbus_acpi_init();
+ if (ret)
+ return ret;
+
+ wait_for_completion(&probe_event);
+
+ if (irq <= 0) {
+ vmbus_acpi_exit();
+ return -ENODEV;
+ }
+
+ vmbus_acpi_exit();
+ init_completion(&probe_event);
+ ret = pci_register_driver(&hv_bus_driver);
+ if (ret)
+ return ret;
+ /*
+ * All the vmbus initialization occurs within the
+ * hv_pci_probe() function. Wait for hv_pci_probe()
+ * to complete.
+ */
+ wait_for_completion(&probe_event);
+
+ if (pci_probe_error)
+ pci_unregister_driver(&hv_bus_driver);
+ return pci_probe_error;
+}
+
+
MODULE_LICENSE("GPL");
MODULE_VERSION(HV_DRV_VERSION);
-module_param(vmbus_irq, int, S_IRUGO);
-module_param(vmbus_loglevel, int, S_IRUGO);
+module_param(vmbus_loglevel, int, S_IRUGO|S_IWUSR);
-module_init(vmbus_init);
-module_exit(vmbus_exit);
+module_init(hv_pci_init);
diff --git a/drivers/staging/hv/vmbus_packet_format.h b/drivers/staging/hv/vmbus_packet_format.h
deleted file mode 100644
index c0b2c2b..0000000
--- a/drivers/staging/hv/vmbus_packet_format.h
+++ /dev/null
@@ -1,161 +0,0 @@
-/*
- *
- * Copyright (c) 2009, Microsoft Corporation.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
- * Place - Suite 330, Boston, MA 02111-1307 USA.
- *
- * Authors:
- * Haiyang Zhang <haiyangz@microsoft.com>
- * Hank Janssen <hjanssen@microsoft.com>
- *
- */
-
-#ifndef _VMBUSPACKETFORMAT_H_
-#define _VMBUSPACKETFORMAT_H_
-
-struct vmpacket_descriptor {
- u16 type;
- u16 offset8;
- u16 len8;
- u16 flags;
- u64 trans_id;
-} __packed;
-
-struct vmpacket_header {
- u32 prev_pkt_start_offset;
- struct vmpacket_descriptor descriptor;
-} __packed;
-
-struct vmtransfer_page_range {
- u32 byte_count;
- u32 byte_offset;
-} __packed;
-
-struct vmtransfer_page_packet_header {
- struct vmpacket_descriptor d;
- u16 xfer_pageset_id;
- bool sender_owns_set;
- u8 reserved;
- u32 range_cnt;
- struct vmtransfer_page_range ranges[1];
-} __packed;
-
-struct vmgpadl_packet_header {
- struct vmpacket_descriptor d;
- u32 gpadl;
- u32 reserved;
-} __packed;
-
-struct vmadd_remove_transfer_page_set {
- struct vmpacket_descriptor d;
- u32 gpadl;
- u16 xfer_pageset_id;
- u16 reserved;
-} __packed;
-
-/*
- * This structure defines a range in guest physical space that can be made to
- * look virtually contiguous.
- */
-struct gpa_range {
- u32 byte_count;
- u32 byte_offset;
- u64 pfn_array[0];
-};
-
-/*
- * This is the format for an Establish Gpadl packet, which contains a handle by
- * which this GPADL will be known and a set of GPA ranges associated with it.
- * This can be converted to a MDL by the guest OS. If there are multiple GPA
- * ranges, then the resulting MDL will be "chained," representing multiple VA
- * ranges.
- */
-struct vmestablish_gpadl {
- struct vmpacket_descriptor d;
- u32 gpadl;
- u32 range_cnt;
- struct gpa_range range[1];
-} __packed;
-
-/*
- * This is the format for a Teardown Gpadl packet, which indicates that the
- * GPADL handle in the Establish Gpadl packet will never be referenced again.
- */
-struct vmteardown_gpadl {
- struct vmpacket_descriptor d;
- u32 gpadl;
- u32 reserved; /* for alignment to a 8-byte boundary */
-} __packed;
-
-/*
- * This is the format for a GPA-Direct packet, which contains a set of GPA
- * ranges, in addition to commands and/or data.
- */
-struct vmdata_gpa_direct {
- struct vmpacket_descriptor d;
- u32 reserved;
- u32 range_cnt;
- struct gpa_range range[1];
-} __packed;
-
-/* This is the format for a Additional Data Packet. */
-struct vmadditional_data {
- struct vmpacket_descriptor d;
- u64 total_bytes;
- u32 offset;
- u32 byte_cnt;
- unsigned char data[1];
-} __packed;
-
-union vmpacket_largest_possible_header {
- struct vmpacket_descriptor simple_hdr;
- struct vmtransfer_page_packet_header xfer_page_hdr;
- struct vmgpadl_packet_header gpadl_hdr;
- struct vmadd_remove_transfer_page_set add_rm_xfer_page_hdr;
- struct vmestablish_gpadl establish_gpadl_hdr;
- struct vmteardown_gpadl teardown_gpadl_hdr;
- struct vmdata_gpa_direct data_gpa_direct_hdr;
-};
-
-#define VMPACKET_DATA_START_ADDRESS(__packet) \
- (void *)(((unsigned char *)__packet) + \
- ((struct vmpacket_descriptor)__packet)->offset8 * 8)
-
-#define VMPACKET_DATA_LENGTH(__packet) \
- ((((struct vmpacket_descriptor)__packet)->len8 - \
- ((struct vmpacket_descriptor)__packet)->offset8) * 8)
-
-#define VMPACKET_TRANSFER_MODE(__packet) \
- (((struct IMPACT)__packet)->type)
-
-enum vmbus_packet_type {
- VM_PKT_INVALID = 0x0,
- VM_PKT_SYNCH = 0x1,
- VM_PKT_ADD_XFER_PAGESET = 0x2,
- VM_PKT_RM_XFER_PAGESET = 0x3,
- VM_PKT_ESTABLISH_GPADL = 0x4,
- VM_PKT_TEARDOWN_GPADL = 0x5,
- VM_PKT_DATA_INBAND = 0x6,
- VM_PKT_DATA_USING_XFER_PAGES = 0x7,
- VM_PKT_DATA_USING_GPADL = 0x8,
- VM_PKT_DATA_USING_GPA_DIRECT = 0x9,
- VM_PKT_CANCEL_REQUEST = 0xa,
- VM_PKT_COMP = 0xb,
- VM_PKT_DATA_USING_ADDITIONAL_PKT = 0xc,
- VM_PKT_ADDITIONAL_DATA = 0xd
-};
-
-#define VMBUS_DATA_PACKET_FLAG_COMPLETION_REQUESTED 1
-
-#endif
diff --git a/drivers/staging/hv/vmbus_private.h b/drivers/staging/hv/vmbus_private.h
deleted file mode 100644
index 6f0d8df..0000000
--- a/drivers/staging/hv/vmbus_private.h
+++ /dev/null
@@ -1,134 +0,0 @@
-/*
- *
- * Copyright (c) 2009, Microsoft Corporation.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
- * Place - Suite 330, Boston, MA 02111-1307 USA.
- *
- * Authors:
- * Haiyang Zhang <haiyangz@microsoft.com>
- * Hank Janssen <hjanssen@microsoft.com>
- *
- */
-
-
-#ifndef _VMBUS_PRIVATE_H_
-#define _VMBUS_PRIVATE_H_
-
-#include "hv.h"
-#include "vmbus_api.h"
-#include "channel.h"
-#include "channel_mgmt.h"
-#include "ring_buffer.h"
-#include <linux/list.h>
-#include <asm/sync_bitops.h>
-
-
-/*
- * Maximum channels is determined by the size of the interrupt page
- * which is PAGE_SIZE. 1/2 of PAGE_SIZE is for send endpoint interrupt
- * and the other is receive endpoint interrupt
- */
-#define MAX_NUM_CHANNELS ((PAGE_SIZE >> 1) << 3) /* 16348 channels */
-
-/* The value here must be in multiple of 32 */
-/* TODO: Need to make this configurable */
-#define MAX_NUM_CHANNELS_SUPPORTED 256
-
-
-enum vmbus_connect_state {
- DISCONNECTED,
- CONNECTING,
- CONNECTED,
- DISCONNECTING
-};
-
-#define MAX_SIZE_CHANNEL_MESSAGE HV_MESSAGE_PAYLOAD_BYTE_COUNT
-
-struct vmbus_connection {
- enum vmbus_connect_state conn_state;
-
- atomic_t next_gpadl_handle;
-
- /*
- * Represents channel interrupts. Each bit position represents a
- * channel. When a channel sends an interrupt via VMBUS, it finds its
- * bit in the sendInterruptPage, set it and calls Hv to generate a port
- * event. The other end receives the port event and parse the
- * recvInterruptPage to see which bit is set
- */
- void *int_page;
- void *send_int_page;
- void *recv_int_page;
-
- /*
- * 2 pages - 1st page for parent->child notification and 2nd
- * is child->parent notification
- */
- void *monitor_pages;
- struct list_head chn_msg_list;
- spinlock_t channelmsg_lock;
-
- /* List of channels */
- struct list_head chn_list;
- spinlock_t channel_lock;
-
- struct workqueue_struct *work_queue;
-};
-
-
-struct vmbus_msginfo {
- /* Bookkeeping stuff */
- struct list_head msglist_entry;
-
- /* Synchronize the request/response if needed */
- int wait_condition;
- wait_queue_head_t wait_event;
-
- /* The message itself */
- unsigned char msg[0];
-};
-
-
-extern struct vmbus_connection vmbus_connection;
-
-/* General vmbus interface */
-
-struct hv_device *vmbus_child_device_create(struct hv_guid *type,
- struct hv_guid *instance,
- struct vmbus_channel *channel);
-
-int vmbus_child_device_register(struct hv_device *child_device_obj);
-void vmbus_child_device_unregister(struct hv_device *device_obj);
-
-/* static void */
-/* VmbusChildDeviceDestroy( */
-/* struct hv_device *); */
-
-struct vmbus_channel *relid2channel(u32 relid);
-
-
-/* Connection interface */
-
-int vmbus_connect(void);
-
-int vmbus_disconnect(void);
-
-int vmbus_post_msg(void *buffer, size_t buflen);
-
-int vmbus_set_event(u32 child_relid);
-
-void vmbus_on_event(unsigned long data);
-
-
-#endif /* _VMBUS_PRIVATE_H_ */
diff --git a/drivers/staging/hv/vstorage.h b/drivers/staging/hv/vstorage.h
deleted file mode 100644
index ebb4d67..0000000
--- a/drivers/staging/hv/vstorage.h
+++ /dev/null
@@ -1,192 +0,0 @@
-/*
- *
- * Copyright (c) 2009, Microsoft Corporation.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
- * Place - Suite 330, Boston, MA 02111-1307 USA.
- *
- * Authors:
- * Haiyang Zhang <haiyangz@microsoft.com>
- * Hank Janssen <hjanssen@microsoft.com>
- *
- */
-
-/* vstorage.w revision number. This is used in the case of a version match, */
-/* to alert the user that structure sizes may be mismatched even though the */
-/* protocol versions match. */
-
-#define REVISION_STRING(REVISION_) #REVISION_
-#define FILL_VMSTOR_REVISION(RESULT_LVALUE_) \
- do { \
- char *revision_string \
- = REVISION_STRING($Rev : 6 $) + 6; \
- RESULT_LVALUE_ = 0; \
- while (*revision_string >= '0' \
- && *revision_string <= '9') { \
- RESULT_LVALUE_ *= 10; \
- RESULT_LVALUE_ += *revision_string - '0'; \
- revision_string++; \
- } \
- } while (0)
-
-/* Major/minor macros. Minor version is in LSB, meaning that earlier flat */
-/* version numbers will be interpreted as "0.x" (i.e., 1 becomes 0.1). */
-#define VMSTOR_PROTOCOL_MAJOR(VERSION_) (((VERSION_) >> 8) & 0xff)
-#define VMSTOR_PROTOCOL_MINOR(VERSION_) (((VERSION_)) & 0xff)
-#define VMSTOR_PROTOCOL_VERSION(MAJOR_, MINOR_) ((((MAJOR_) & 0xff) << 8) | \
- (((MINOR_) & 0xff)))
-#define VMSTOR_INVALID_PROTOCOL_VERSION (-1)
-
-/* Version history: */
-/* V1 Beta 0.1 */
-/* V1 RC < 2008/1/31 1.0 */
-/* V1 RC > 2008/1/31 2.0 */
-#define VMSTOR_PROTOCOL_VERSION_CURRENT VMSTOR_PROTOCOL_VERSION(2, 0)
-
-
-
-
-/* This will get replaced with the max transfer length that is possible on */
-/* the host adapter. */
-/* The max transfer length will be published when we offer a vmbus channel. */
-#define MAX_TRANSFER_LENGTH 0x40000
-#define DEFAULT_PACKET_SIZE (sizeof(struct vmdata_gpa_direct) + \
- sizeof(struct vstor_packet) + \
- sizesizeof(u64) * (MAX_TRANSFER_LENGTH / PAGE_SIZE)))
-
-
-/* Packet structure describing virtual storage requests. */
-enum vstor_packet_operation {
- VSTOR_OPERATION_COMPLETE_IO = 1,
- VSTOR_OPERATION_REMOVE_DEVICE = 2,
- VSTOR_OPERATION_EXECUTE_SRB = 3,
- VSTOR_OPERATION_RESET_LUN = 4,
- VSTOR_OPERATION_RESET_ADAPTER = 5,
- VSTOR_OPERATION_RESET_BUS = 6,
- VSTOR_OPERATION_BEGIN_INITIALIZATION = 7,
- VSTOR_OPERATION_END_INITIALIZATION = 8,
- VSTOR_OPERATION_QUERY_PROTOCOL_VERSION = 9,
- VSTOR_OPERATION_QUERY_PROPERTIES = 10,
- VSTOR_OPERATION_MAXIMUM = 10
-};
-
-/*
- * Platform neutral description of a scsi request -
- * this remains the same across the write regardless of 32/64 bit
- * note: it's patterned off the SCSI_PASS_THROUGH structure
- */
-#define CDB16GENERIC_LENGTH 0x10
-
-#ifndef SENSE_BUFFER_SIZE
-#define SENSE_BUFFER_SIZE 0x12
-#endif
-
-#define MAX_DATA_BUF_LEN_WITH_PADDING 0x14
-
-struct vmscsi_request {
- unsigned short length;
- unsigned char srb_status;
- unsigned char scsi_status;
-
- unsigned char port_number;
- unsigned char path_id;
- unsigned char target_id;
- unsigned char lun;
-
- unsigned char cdb_length;
- unsigned char sense_info_length;
- unsigned char data_in;
- unsigned char reserved;
-
- unsigned int data_transfer_length;
-
- union {
- unsigned char cdb[CDB16GENERIC_LENGTH];
- unsigned char sense_data[SENSE_BUFFER_SIZE];
- unsigned char reserved_array[MAX_DATA_BUF_LEN_WITH_PADDING];
- };
-} __attribute((packed));
-
-
-/*
- * This structure is sent during the intialization phase to get the different
- * properties of the channel.
- */
-struct vmstorage_channel_properties {
- unsigned short protocol_version;
- unsigned char path_id;
- unsigned char target_id;
-
- /* Note: port number is only really known on the client side */
- unsigned int port_number;
- unsigned int flags;
- unsigned int max_transfer_bytes;
-
- /* This id is unique for each channel and will correspond with */
- /* vendor specific data in the inquirydata */
- unsigned long long unique_id;
-} __packed;
-
-/* This structure is sent during the storage protocol negotiations. */
-struct vmstorage_protocol_version {
- /* Major (MSW) and minor (LSW) version numbers. */
- unsigned short major_minor;
-
- /*
- * Revision number is auto-incremented whenever this file is changed
- * (See FILL_VMSTOR_REVISION macro above). Mismatch does not
- * definitely indicate incompatibility--but it does indicate mismatched
- * builds.
- */
- unsigned short revision;
-} __packed;
-
-/* Channel Property Flags */
-#define STORAGE_CHANNEL_REMOVABLE_FLAG 0x1
-#define STORAGE_CHANNEL_EMULATED_IDE_FLAG 0x2
-
-struct vstor_packet {
- /* Requested operation type */
- enum vstor_packet_operation operation;
-
- /* Flags - see below for values */
- unsigned int flags;
-
- /* Status of the request returned from the server side. */
- unsigned int status;
-
- /* Data payload area */
- union {
- /*
- * Structure used to forward SCSI commands from the
- * client to the server.
- */
- struct vmscsi_request vm_srb;
-
- /* Structure used to query channel properties. */
- struct vmstorage_channel_properties storage_channel_properties;
-
- /* Used during version negotiations. */
- struct vmstorage_protocol_version version;
- };
-} __packed;
-
-/* Packet flags */
-/*
- * This flag indicates that the server should send back a completion for this
- * packet.
- */
-#define REQUEST_COMPLETION_FLAG 0x1
-
-/* This is the set of flags that the vsc can set in any packets it sends */
-#define VSC_LEGAL_FLAGS (REQUEST_COMPLETION_FLAG)
diff --git a/drivers/staging/iio/Documentation/device.txt b/drivers/staging/iio/Documentation/device.txt
index 69d9570..1abb80c 100644
--- a/drivers/staging/iio/Documentation/device.txt
+++ b/drivers/staging/iio/Documentation/device.txt
@@ -8,34 +8,66 @@
First allocate one using:
-struct iio_dev *indio_dev = iio_allocate_device();
+struct iio_dev *indio_dev = iio_allocate_device(sizeof(struct chip_state));
+where chip_state is a structure of local state data for this instance of
+the chip.
+
+That data can be accessed using iio_priv(struct iio_dev *)
Then fill in the following:
-indio_dev->dev.parent
- the struct device associated with the underlying hardware.
+- indio_dev->dev.parent
+ Struct device associated with the underlying hardware.
+- indio_dev->name
+ Name of the device being driven - made available as the name
+ attribute in sysfs.
-indio_dev->num_interrupt_lines
- number of event triggering hardware lines the device has.
+- indio_dev->info
+ pointer to a structure with elements that tend to be fixed for
+ large sets of different parts supported by a given driver.
+ This contains:
+ * info->driver_module:
+ Set to THIS_MODULE. Used to ensure correct ownership
+ of various resources allocate by the core.
+ * info->num_interrupt_lines:
+ Number of event triggering hardware lines the device has.
+ * info->event_attrs:
+ Attributes used to enable / disable hardware events.
+ * info->attrs:
+ General device attributes. Typically used for the weird
+ and the wonderful bits not covered by the channel specification.
+ * info->read_raw:
+ Raw data reading function. Used for both raw channel access
+ and for associate parameters such as offsets and scales.
+ * info->write_raw:
+ Raw value writing function. Used for writable device values such
+ as DAC values and caliboffset.
+ * info->read_event_config:
+ Typically only set if there are some interrupt lines. This
+ is used to read if an on sensor event detector is enabled.
+ * info->write_event_config:
+ Enable / disable an on sensor event detector.
+ * info->read_event_value:
+ Read value associated with on sensor event detectors. Note that
+ the meaning of the returned value is dependent on the event
+ type.
+ * info->write_event_value:
+ Write the value associated with on sensor event detectors. E.g.
+ a threshold above which an interrupt occurs. Note that the
+ meaning of the value to be set is event type dependant.
-indio_dev->event_attrs
- attributes used to enable / disable hardware events - note the
- attributes are embedded in iio_event_attr structures with an
- associated iio_event_handler which may or may note be shared.
- If num_interrupt_lines = 0, then no need to fill this in.
-
-indio_dev->attrs
- general attributes such as polled access to device channels.
-
-indio_dev->dev_data
- private device specific data.
-
-indio_dev->driver_module
- typically set to THIS_MODULE. Used to specify ownership of some
- iio created resources.
-
-indio_dev->modes
- whether direct access and / or ring buffer access is supported.
+- indio_dev->modes:
+ Specify whether direct access and / or ring buffer access is supported.
+- indio_dev->ring:
+ An optional associated buffer.
+- indio_dev->pollfunc:
+ Poll function related elements. This controls what occurs when a trigger
+ to which this device is attached sends and event.
+- indio_dev->channels:
+ Specification of device channels. Most attributes etc are built
+ form this spec.
+- indio_dev->num_channels:
+ How many channels are there?
Once these are set up, a call to iio_device_register(indio_dev),
will register the device with the iio core.
diff --git a/drivers/staging/iio/Documentation/generic_buffer.c b/drivers/staging/iio/Documentation/generic_buffer.c
index 3cc18ab..f82894f 100644
--- a/drivers/staging/iio/Documentation/generic_buffer.c
+++ b/drivers/staging/iio/Documentation/generic_buffer.c
@@ -27,6 +27,7 @@
#include <sys/dir.h>
#include <linux/types.h>
#include <string.h>
+#include <poll.h>
#include "iio_utils.h"
/**
@@ -53,6 +54,24 @@
return bytes;
}
+void print2byte(int input, struct iio_channel_info *info)
+{
+ /* shift before conversion to avoid sign extension
+ of left aligned data */
+ input = input >> info->shift;
+ if (info->is_signed) {
+ int16_t val = input;
+ val &= (1 << info->bits_used) - 1;
+ val = (int16_t)(val << (16 - info->bits_used)) >>
+ (16 - info->bits_used);
+ printf("%05f ", val,
+ (float)(val + info->offset)*info->scale);
+ } else {
+ uint16_t val = input;
+ val &= (1 << info->bits_used) - 1;
+ printf("%05f ", ((float)val + info->offset)*info->scale);
+ }
+}
/**
* process_scan() - print out the values in SI units
* @data: pointer to the start of the scan
@@ -70,25 +89,8 @@
switch (infoarray[k].bytes) {
/* only a few cases implemented so far */
case 2:
- if (infoarray[k].is_signed) {
- int16_t val = *(int16_t *)
- (data
- + infoarray[k].location);
- if ((val >> infoarray[k].bits_used) & 1)
- val = (val & infoarray[k].mask) |
- ~infoarray[k].mask;
- printf("%05f ", ((float)val +
- infoarray[k].offset)*
- infoarray[k].scale);
- } else {
- uint16_t val = *(uint16_t *)
- (data +
- infoarray[k].location);
- val = (val & infoarray[k].mask);
- printf("%05f ", ((float)val +
- infoarray[k].offset)*
- infoarray[k].scale);
- }
+ print2byte(*(uint16_t *)(data + infoarray[k].location),
+ &infoarray[k]);
break;
case 8:
if (infoarray[k].is_signed) {
@@ -132,10 +134,9 @@
int datardytrigger = 1;
char *data;
- size_t read_size;
- struct iio_event_data dat;
+ ssize_t read_size;
int dev_num, trig_num;
- char *buffer_access, *buffer_event;
+ char *buffer_access;
int scan_size;
int noevents = 0;
char *dummy;
@@ -210,7 +211,7 @@
*/
ret = build_channel_array(dev_dir_name, &infoarray, &num_channels);
if (ret) {
- printf("Problem reading scan element information \n");
+ printf("Problem reading scan element information\n");
goto error_free_triggername;
}
@@ -251,54 +252,32 @@
}
ret = asprintf(&buffer_access,
- "/dev/device%d:buffer0:access0",
+ "/dev/device%d:buffer0",
dev_num);
if (ret < 0) {
ret = -ENOMEM;
goto error_free_data;
}
- ret = asprintf(&buffer_event, "/dev/device%d:buffer0:event0", dev_num);
- if (ret < 0) {
- ret = -ENOMEM;
- goto error_free_buffer_access;
- }
/* Attempt to open non blocking the access dev */
fp = open(buffer_access, O_RDONLY | O_NONBLOCK);
if (fp == -1) { /*If it isn't there make the node */
printf("Failed to open %s\n", buffer_access);
ret = -errno;
- goto error_free_buffer_event;
- }
- /* Attempt to open the event access dev (blocking this time) */
- fp_ev = fopen(buffer_event, "rb");
- if (fp_ev == NULL) {
- printf("Failed to open %s\n", buffer_event);
- ret = -errno;
- goto error_close_buffer_access;
+ goto error_free_buffer_access;
}
/* Wait for events 10 times */
for (j = 0; j < num_loops; j++) {
if (!noevents) {
- read_size = fread(&dat,
- 1,
- sizeof(struct iio_event_data),
- fp_ev);
- switch (dat.id) {
- case IIO_EVENT_CODE_RING_100_FULL:
- toread = buf_len;
- break;
- case IIO_EVENT_CODE_RING_75_FULL:
- toread = buf_len*3/4;
- break;
- case IIO_EVENT_CODE_RING_50_FULL:
- toread = buf_len/2;
- break;
- default:
- printf("Unexpecteded event code\n");
- continue;
- }
+ struct pollfd pfd = {
+ .fd = fp,
+ .events = POLLIN,
+ };
+
+ poll(&pfd, 1, -1);
+ toread = buf_len;
+
} else {
usleep(timedelay);
toread = 64;
@@ -320,22 +299,18 @@
/* Stop the ring buffer */
ret = write_sysfs_int("enable", buf_dir_name, 0);
if (ret < 0)
- goto error_close_buffer_event;
+ goto error_close_buffer_access;
/* Disconnect from the trigger - just write a dummy name.*/
write_sysfs_string("trigger/current_trigger",
dev_dir_name, "NULL");
-error_close_buffer_event:
- fclose(fp_ev);
error_close_buffer_access:
close(fp);
error_free_data:
free(data);
error_free_buffer_access:
free(buffer_access);
-error_free_buffer_event:
- free(buffer_event);
error_free_buf_dir_name:
free(buf_dir_name);
error_free_triggername:
diff --git a/drivers/staging/iio/Documentation/iio_utils.h b/drivers/staging/iio/Documentation/iio_utils.h
index fd78e4f..150f440 100644
--- a/drivers/staging/iio/Documentation/iio_utils.h
+++ b/drivers/staging/iio/Documentation/iio_utils.h
@@ -16,25 +16,11 @@
#define IIO_MAX_NAME_LENGTH 30
-#define IIO_EV_CLASS_BUFFER 0
-#define IIO_BUFFER_EVENT_CODE(code) \
- (IIO_EV_CLASS_BUFFER | (code << 8))
-
-#define IIO_EVENT_CODE_RING_50_FULL IIO_BUFFER_EVENT_CODE(0)
-#define IIO_EVENT_CODE_RING_75_FULL IIO_BUFFER_EVENT_CODE(1)
-#define IIO_EVENT_CODE_RING_100_FULL IIO_BUFFER_EVENT_CODE(2)
-
-
#define FORMAT_SCAN_ELEMENTS_DIR "%s:buffer0/scan_elements"
#define FORMAT_TYPE_FILE "%s_type"
const char *iio_dir = "/sys/bus/iio/devices/";
-struct iio_event_data {
- int id;
- __s64 timestamp;
-};
-
/**
* iioutils_break_up_name() - extract generic name from full channel name
* @full_name: the full channel name
@@ -85,6 +71,7 @@
unsigned index;
unsigned bytes;
unsigned bits_used;
+ unsigned shift;
uint64_t mask;
unsigned is_signed;
unsigned enabled;
@@ -103,6 +90,7 @@
inline int iioutils_get_type(unsigned *is_signed,
unsigned *bytes,
unsigned *bits_used,
+ unsigned *shift,
uint64_t *mask,
const char *device_dir,
const char *name,
@@ -157,7 +145,8 @@
goto error_free_filename;
}
fscanf(sysfsfp,
- "%c%u/%u", &signchar, bits_used, &padint);
+ "%c%u/%u>>%u", &signchar, bits_used,
+ &padint, shift);
*bytes = padint / 8;
if (*bits_used == 64)
*mask = ~0;
@@ -395,6 +384,7 @@
ret = iioutils_get_type(¤t->is_signed,
¤t->bytes,
¤t->bits_used,
+ ¤t->shift,
¤t->mask,
device_dir,
current->name,
diff --git a/drivers/staging/iio/Documentation/overview.txt b/drivers/staging/iio/Documentation/overview.txt
index d97106c..afc39ec 100644
--- a/drivers/staging/iio/Documentation/overview.txt
+++ b/drivers/staging/iio/Documentation/overview.txt
@@ -3,8 +3,7 @@
The Industrial I/O subsystem is intended to provide support for devices
that in some sense are analog to digital converters (ADCs). As many
actual devices combine some ADCs with digital to analog converters
-(DACs) the intention is to add that functionality at a future date
-(hence the name).
+(DACs) that functionality is also supported.
The aim is to fill the gap between the somewhat similar hwmon and
input subsystems. Hwmon is very much directed at low sample rate
@@ -31,32 +30,28 @@
Note: A given device may have one or more event channel. These events are
turned on or off (if possible) via sysfs interfaces.
-* Hardware ring buffer support. Some recent sensors have included
+* Hardware buffer support. Some recent sensors have included
fifo / ring buffers on the sensor chip. These greatly reduce the load
on the host CPU by buffering relatively large numbers of data samples
based on an internal sampling clock. Examples include VTI SCA3000
-series and Analog Device ADXL345 accelerometers. Each ring buffer
-typically has an event chrdev (similar to the more general ones above)
-to pass on events such as buffer 50% full and an access chrdev via
-which the raw data it self may be read back.
+series and Analog Device ADXL345 accelerometers. Each buffer supports
+polling to establish when data is available.
-* Trigger and software ring buffer support. In many data analysis
+* Trigger and software buffer support. In many data analysis
applications it it useful to be able to capture data based on some
external signal (trigger). These triggers might be a data ready
signal, a gpio line connected to some external system or an on
processor periodic interrupt. A single trigger may initialize data
capture or reading from a number of sensors. These triggers are
-used in IIO to fill software ring buffers acting in a very similar
+used in IIO to fill software buffers acting in a very similar
fashion to the hardware buffers described above.
Other documentation:
-userspace.txt - overview of ring buffer reading from userspace.
-
device.txt - elements of a typical device driver.
trigger.txt - elements of a typical trigger driver.
-ring.txt - additional elements required for ring buffer support.
+ring.txt - additional elements required for buffer support.
sysfs-bus-iio - abi documentation file.
diff --git a/drivers/staging/iio/Documentation/ring.txt b/drivers/staging/iio/Documentation/ring.txt
index 3696c36..7e99ef2 100644
--- a/drivers/staging/iio/Documentation/ring.txt
+++ b/drivers/staging/iio/Documentation/ring.txt
@@ -1,57 +1,55 @@
-Ring buffer support within IIO
+Buffer support within IIO
This document is intended as a general overview of the functionality
-a ring buffer may supply and how it is specified within IIO. For more
-specific information on a given ring buffer implementation, see the
-comments in the source code. Note that the intention is to allow
-some drivers to specify ring buffers choice at probe or runtime, but
-for now the selection is hard coded within a given driver.
+a buffer may supply and how it is specified within IIO. For more
+specific information on a given buffer implementation, see the
+comments in the source code. Note that some drivers allow buffer
+implementation to be selected at compile time via Kconfig options.
-A given ring buffer implementation typically embedded a struct
+A given buffer implementation typically embeds a struct
iio_ring_buffer and it is a pointer to this that is provided to the
IIO core. Access to the embedding structure is typically done via
container_of functions.
-struct iio_ring_buffer contains 4 function pointers
-(preenable, postenable, predisable, postdisable).
-These are used to perform implementation specific steps on either side
-of the core changing it's current mode to indicate that the ring buffer
+struct iio_ring_buffer contains a struct iio_ring_setup_ops *setup_ops
+which in turn contains the 4 function pointers
+(preenable, postenable, predisable and postdisable).
+These are used to perform device specific steps on either side
+of the core changing it's current mode to indicate that the buffer
is enabled or disabled (along with enabling triggering etc as appropriate).
Also in struct iio_ring_buffer is a struct iio_ring_access_funcs.
The function pointers within here are used to allow the core to handle
-as much ring buffer functionality as possible. Note almost all of these
+as much buffer functionality as possible. Note almost all of these
are optional.
mark_in_use, unmark_in_use
- Basically indicate that not changes should be made to the ring
- buffer state that will effect the form of the data being captures
- (e.g. scan elements or length)
+ Basically indicate that not changes should be made to the buffer state that
+ will effect the form of the data being captures (e.g. scan elements or length)
store_to
- If possible, push data to ring buffer.
+ If possible, push data to the buffer.
read_last
- If possible get the most recent entry from the buffer (without removal).
+ If possible, get the most recent scan from the buffer (without removal).
This provides polling like functionality whilst the ring buffering is in
use without a separate read from the device.
-rip_lots
- The primary ring buffer reading function. Note that it may well not return
- as much data as requested. The deadoffset is used to indicate that some
- initial data in the data array is not guaranteed to be valid.
+rip_first_n
+ The primary buffer reading function. Note that it may well not return
+ as much data as requested.
mark_param_changed
Used to indicate that something has changed. Used in conjunction with
request_update
If parameters have changed that require reinitialization or configuration of
- the ring buffer this will trigger it.
+ the buffer this will trigger it.
get_bytes_per_datum, set_bytes_per_datum
Get/set the number of bytes for a complete scan. (All samples + timestamp)
get_length / set_length
- Get/set the number of sample sets that may be held by the buffer.
+ Get/set the number of complete scans that may be held by the buffer.
is_enabled
Query if ring buffer is in use
diff --git a/drivers/staging/iio/Documentation/sysfs-bus-iio b/drivers/staging/iio/Documentation/sysfs-bus-iio
index 4915aee..467c49a 100644
--- a/drivers/staging/iio/Documentation/sysfs-bus-iio
+++ b/drivers/staging/iio/Documentation/sysfs-bus-iio
@@ -6,6 +6,12 @@
Corresponds to a grouping of sensor channels. X is the IIO
index of the device.
+What: /sys/bus/iio/devices/device[n]/power_state
+KernelVersion: 2.6.37
+Contact: linux-iio@vger.kernel.org
+Description:
+ This property gets/sets the device power state.
+
What: /sys/bus/iio/devices/triggerX
KernelVersion: 2.6.35
Contact: linux-iio@vger.kernel.org
@@ -698,3 +704,10 @@
with all _en attributes to establish which channels are present,
and the relevant _type attributes to establish the data storage
format.
+
+What: /sys/bus/iio/devices/deviceX/gyro_z_quadrature_correction_raw
+KernelVersion: 2.6.38
+Contact: linux-iio@xxxxxxxxxxxxxxx
+Description:
+ This attribute is used to read the amount of quadrature error
+ present in the device at a given time.
diff --git a/drivers/staging/iio/Documentation/sysfs-bus-iio-light b/drivers/staging/iio/Documentation/sysfs-bus-iio-light
index 5d84856..21d2774 100644
--- a/drivers/staging/iio/Documentation/sysfs-bus-iio-light
+++ b/drivers/staging/iio/Documentation/sysfs-bus-iio-light
@@ -62,3 +62,16 @@
sensing mode. This value should be the output from a reading
and if expressed in SI units, should include _input. If this
value is not in SI units, then it should include _raw.
+
+What: /sys/bus/iio/devices/device[n]/illuminance0_target
+KernelVersion: 2.6.37
+Contact: linux-iio@vger.kernel.org
+Description:
+ This property gets/sets the last known external
+ lux measurement used in/for calibration.
+
+What: /sys/bus/iio/devices/device[n]/illuminance0_integration_time
+KernelVersion: 2.6.37
+Contact: linux-iio@vger.kernel.org
+Description:
+ This property gets/sets the sensors ADC analog integration time.
diff --git a/drivers/staging/iio/Documentation/sysfs-bus-iio-light-tsl2583 b/drivers/staging/iio/Documentation/sysfs-bus-iio-light-tsl2583
new file mode 100644
index 0000000..660781d
--- /dev/null
+++ b/drivers/staging/iio/Documentation/sysfs-bus-iio-light-tsl2583
@@ -0,0 +1,20 @@
+What: /sys/bus/iio/devices/device[n]/lux_table
+KernelVersion: 2.6.37
+Contact: linux-iio@vger.kernel.org
+Description:
+ This property gets/sets the table of coefficients
+ used in calculating illuminance in lux.
+
+What: /sys/bus/iio/devices/device[n]/illuminance0_calibrate
+KernelVersion: 2.6.37
+Contact: linux-iio@vger.kernel.org
+Description:
+ This property causes an internal calibration of the als gain trim
+ value which is later used in calculating illuminance in lux.
+
+What: /sys/bus/iio/devices/device[n]/illuminance0_input_target
+KernelVersion: 2.6.37
+Contact: linux-iio@vger.kernel.org
+Description:
+ This property is the known externally illuminance (in lux).
+ It is used in the process of calibrating the device accuracy.
diff --git a/drivers/staging/iio/Documentation/trigger.txt b/drivers/staging/iio/Documentation/trigger.txt
index 650157f..fc2012e 100644
--- a/drivers/staging/iio/Documentation/trigger.txt
+++ b/drivers/staging/iio/Documentation/trigger.txt
@@ -5,14 +5,11 @@
such triggers are registered with the core in the same way as
stand-alone triggers.
-struct iio_trig *trig = iio_allocate_trigger();
+struct iio_trig *trig = iio_allocate_trigger("<trigger format string>", ...);
allocates a trigger structure. The key elements to then fill in within
a driver are:
-trig->control_attrs
- Any sysfs attributes needed to control parameters of the trigger
-
trig->private_data
Device specific private data.
@@ -20,8 +17,12 @@
Typically set to THIS_MODULE. Used to ensure correct
ownership of core allocated resources.
-trig->name
- A unique name for the trigger.
+trig->set_trigger_state:
+ Function that enables / disables the underlying source of the trigger.
+
+There is also a
+trig->alloc_list which is useful for drivers that allocate multiple
+triggers to keep track of what they have created.
When these have been set call:
@@ -30,9 +31,8 @@
to register the trigger with the core, making it available to trigger
consumers.
-
Trigger Consumers
-Currently triggers are only used for the filling of software ring
+Currently triggers are only used for the filling of software
buffers and as such any device supporting INDIO_RING_TRIGGERED has the
consumer interface automatically created.
diff --git a/drivers/staging/iio/Documentation/userspace.txt b/drivers/staging/iio/Documentation/userspace.txt
deleted file mode 100644
index ff06e5d..0000000
--- a/drivers/staging/iio/Documentation/userspace.txt
+++ /dev/null
@@ -1,12 +0,0 @@
-Userspace access to IIO
-
-The sysfs attributes are documented in sysfs-bus-iio.
-
-Udev will create the following entries under /dev by default:
-
-device0:buffer0:access0 - ring access chrdev
-device0:buffer0:event0 - ring event chrdev
-device0:event0 - general event chrdev.
-
-The files, lis3l02dqbuffersimple.c and iio_utils.h in this directory provide an example
-of how to use the ring buffer and event interfaces.
diff --git a/drivers/staging/iio/Kconfig b/drivers/staging/iio/Kconfig
index 6775bf9..f96d5b5 100644
--- a/drivers/staging/iio/Kconfig
+++ b/drivers/staging/iio/Kconfig
@@ -5,17 +5,17 @@
menuconfig IIO
tristate "Industrial I/O support"
depends on !S390
- ---help---
+ help
The industrial I/O subsystem provides a unified framework for
drivers for many different types of embedded sensors using a
number of different physical interfaces (i2c, spi, etc). See
- Documentation/industrialio for more information.
+ drivers/staging/iio/Documentation for more information.
if IIO
config IIO_RING_BUFFER
- bool "Enable ring buffer support within IIO"
+ bool "Enable buffer support within IIO"
help
- Provide core support for various ring buffer based data
+ Provide core support for various buffer based data
acquisition methods.
if IIO_RING_BUFFER
@@ -48,6 +48,13 @@
ring buffers. The triggers are effectively a 'capture
data now' interrupt.
+config IIO_CONSUMERS_PER_TRIGGER
+ int "Maximum number of consumers per trigger"
+ depends on IIO_TRIGGER
+ default "2"
+ help
+ This value controls the maximum number of consumers that a
+ given trigger may handle. Default is 2.
source "drivers/staging/iio/accel/Kconfig"
source "drivers/staging/iio/adc/Kconfig"
diff --git a/drivers/staging/iio/accel/adis16201.h b/drivers/staging/iio/accel/adis16201.h
index 23fe54d..0b9b854 100644
--- a/drivers/staging/iio/accel/adis16201.h
+++ b/drivers/staging/iio/accel/adis16201.h
@@ -64,9 +64,6 @@
/**
* struct adis16201_state - device instance specific data
* @us: actual spi_device
- * @work_trigger_to_ring: bh for triggered event handling
- * @inter: used to check if new interrupt has been triggered
- * @last_timestamp: passing timestamp from th to bh of interrupt handler
* @indio_dev: industrial I/O device structure
* @trig: data ready trigger registered with iio
* @tx: transmit buffer
@@ -75,8 +72,6 @@
**/
struct adis16201_state {
struct spi_device *us;
- struct work_struct work_trigger_to_ring;
- s64 last_timestamp;
struct iio_dev *indio_dev;
struct iio_trigger *trig;
u8 *tx;
@@ -84,7 +79,7 @@
struct mutex buf_lock;
};
-int adis16201_set_irq(struct device *dev, bool enable);
+int adis16201_set_irq(struct iio_dev *indio_dev, bool enable);
#ifdef CONFIG_IIO_RING_BUFFER
enum adis16201_scan {
@@ -107,8 +102,6 @@
int adis16201_configure_ring(struct iio_dev *indio_dev);
void adis16201_unconfigure_ring(struct iio_dev *indio_dev);
-int adis16201_initialize_ring(struct iio_ring_buffer *ring);
-void adis16201_uninitialize_ring(struct iio_ring_buffer *ring);
#else /* CONFIG_IIO_RING_BUFFER */
static inline void adis16201_remove_trigger(struct iio_dev *indio_dev)
diff --git a/drivers/staging/iio/accel/adis16201_core.c b/drivers/staging/iio/accel/adis16201_core.c
index 79b785a..e4c49f0 100644
--- a/drivers/staging/iio/accel/adis16201_core.c
+++ b/drivers/staging/iio/accel/adis16201_core.c
@@ -6,9 +6,6 @@
* Licensed under the GPL-2 or later.
*/
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/gpio.h>
#include <linux/delay.h>
#include <linux/mutex.h>
#include <linux/device.h>
@@ -16,20 +13,28 @@
#include <linux/spi/spi.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
-#include <linux/list.h>
#include "../iio.h"
#include "../sysfs.h"
+#include "../ring_generic.h"
+
#include "accel.h"
#include "inclinometer.h"
-#include "../gyro/gyro.h"
#include "../adc/adc.h"
#include "adis16201.h"
#define DRIVER_NAME "adis16201"
-static int adis16201_check_status(struct device *dev);
+enum adis16201_chan {
+ in_supply,
+ temp,
+ accel_x,
+ accel_y,
+ incli_x,
+ incli_y,
+ in_aux,
+};
/**
* adis16201_spi_write_reg_8() - write single byte to a register
@@ -57,18 +62,17 @@
/**
* adis16201_spi_write_reg_16() - write 2 bytes to a pair of registers
- * @dev: device associated with child of actual device (iio_dev or iio_trig)
+ * @indio_dev: iio device associated with child of actual device
* @reg_address: the address of the lower of the two registers. Second register
* is assumed to have address one greater.
* @val: value to be written
**/
-static int adis16201_spi_write_reg_16(struct device *dev,
- u8 lower_reg_address,
- u16 value)
+static int adis16201_spi_write_reg_16(struct iio_dev *indio_dev,
+ u8 lower_reg_address,
+ u16 value)
{
int ret;
struct spi_message msg;
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct adis16201_state *st = iio_dev_get_devdata(indio_dev);
struct spi_transfer xfers[] = {
{
@@ -80,7 +84,6 @@
.tx_buf = st->tx + 2,
.bits_per_word = 8,
.len = 2,
- .cs_change = 1,
},
};
@@ -101,17 +104,16 @@
/**
* adis16201_spi_read_reg_16() - read 2 bytes from a 16-bit register
- * @dev: device associated with child of actual device (iio_dev or iio_trig)
+ * @indio_dev: iio device associated with child of actual device
* @reg_address: the address of the lower of the two registers. Second register
* is assumed to have address one greater.
* @val: somewhere to pass back the value read
**/
-static int adis16201_spi_read_reg_16(struct device *dev,
+static int adis16201_spi_read_reg_16(struct iio_dev *indio_dev,
u8 lower_reg_address,
u16 *val)
{
struct spi_message msg;
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct adis16201_state *st = iio_dev_get_devdata(indio_dev);
int ret;
struct spi_transfer xfers[] = {
@@ -125,7 +127,6 @@
.rx_buf = st->rx,
.bits_per_word = 8,
.len = 2,
- .cs_change = 1,
.delay_usecs = 20,
},
};
@@ -150,160 +151,6 @@
return ret;
}
-static ssize_t adis16201_read_12bit_unsigned(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- int ret;
- u16 val = 0;
- struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
-
- ret = adis16201_spi_read_reg_16(dev, this_attr->address, &val);
- if (ret)
- return ret;
-
- if (val & ADIS16201_ERROR_ACTIVE) {
- ret = adis16201_check_status(dev);
- if (ret)
- return ret;
- }
-
- return sprintf(buf, "%u\n", val & 0x0FFF);
-}
-
-static ssize_t adis16201_read_temp(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
- ssize_t ret;
- u16 val;
-
- /* Take the iio_dev status lock */
- mutex_lock(&indio_dev->mlock);
-
- ret = adis16201_spi_read_reg_16(dev, ADIS16201_TEMP_OUT, (u16 *)&val);
- if (ret)
- goto error_ret;
-
- if (val & ADIS16201_ERROR_ACTIVE) {
- ret = adis16201_check_status(dev);
- if (ret)
- goto error_ret;
- }
-
- val &= 0xFFF;
- ret = sprintf(buf, "%d\n", val);
-
-error_ret:
- mutex_unlock(&indio_dev->mlock);
- return ret;
-}
-
-static ssize_t adis16201_read_9bit_signed(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
- struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
- s16 val = 0;
- ssize_t ret;
-
- mutex_lock(&indio_dev->mlock);
-
- ret = adis16201_spi_read_reg_16(dev, this_attr->address, (u16 *)&val);
- if (!ret) {
- if (val & ADIS16201_ERROR_ACTIVE) {
- ret = adis16201_check_status(dev);
- if (ret)
- goto error_ret;
- }
- val = ((s16)(val << 7) >> 7);
- ret = sprintf(buf, "%d\n", val);
- }
-
-error_ret:
- mutex_unlock(&indio_dev->mlock);
-
- return ret;
-}
-
-static ssize_t adis16201_read_12bit_signed(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
- struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
- s16 val = 0;
- ssize_t ret;
-
- mutex_lock(&indio_dev->mlock);
-
- ret = adis16201_spi_read_reg_16(dev, this_attr->address, (u16 *)&val);
- if (!ret) {
- if (val & ADIS16201_ERROR_ACTIVE) {
- ret = adis16201_check_status(dev);
- if (ret)
- goto error_ret;
- }
-
- val = ((s16)(val << 4) >> 4);
- ret = sprintf(buf, "%d\n", val);
- }
-
-error_ret:
- mutex_unlock(&indio_dev->mlock);
-
- return ret;
-}
-
-static ssize_t adis16201_read_14bit_signed(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
- struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
- s16 val = 0;
- ssize_t ret;
-
- mutex_lock(&indio_dev->mlock);
-
- ret = adis16201_spi_read_reg_16(dev, this_attr->address, (u16 *)&val);
- if (!ret) {
- if (val & ADIS16201_ERROR_ACTIVE) {
- ret = adis16201_check_status(dev);
- if (ret)
- goto error_ret;
- }
-
- val = ((s16)(val << 2) >> 2);
- ret = sprintf(buf, "%d\n", val);
- }
-
-error_ret:
- mutex_unlock(&indio_dev->mlock);
-
- return ret;
-}
-
-static ssize_t adis16201_write_16bit(struct device *dev,
- struct device_attribute *attr,
- const char *buf,
- size_t len)
-{
- struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
- int ret;
- long val;
-
- ret = strict_strtol(buf, 10, &val);
- if (ret)
- goto error_ret;
- ret = adis16201_spi_write_reg_16(dev, this_attr->address, val);
-
-error_ret:
- return ret ? ret : len;
-}
-
static int adis16201_reset(struct device *dev)
{
int ret;
@@ -331,12 +178,12 @@
return -EINVAL;
}
-int adis16201_set_irq(struct device *dev, bool enable)
+int adis16201_set_irq(struct iio_dev *indio_dev, bool enable)
{
int ret = 0;
u16 msc;
- ret = adis16201_spi_read_reg_16(dev, ADIS16201_MSC_CTRL, &msc);
+ ret = adis16201_spi_read_reg_16(indio_dev, ADIS16201_MSC_CTRL, &msc);
if (ret)
goto error_ret;
@@ -347,20 +194,21 @@
else
msc &= ~ADIS16201_MSC_CTRL_DATA_RDY_EN;
- ret = adis16201_spi_write_reg_16(dev, ADIS16201_MSC_CTRL, msc);
+ ret = adis16201_spi_write_reg_16(indio_dev, ADIS16201_MSC_CTRL, msc);
error_ret:
return ret;
}
-static int adis16201_check_status(struct device *dev)
+static int adis16201_check_status(struct iio_dev *indio_dev)
{
u16 status;
int ret;
- ret = adis16201_spi_read_reg_16(dev, ADIS16201_DIAG_STAT, &status);
+ ret = adis16201_spi_read_reg_16(indio_dev,
+ ADIS16201_DIAG_STAT, &status);
if (ret < 0) {
- dev_err(dev, "Reading status failed\n");
+ dev_err(&indio_dev->dev, "Reading status failed\n");
goto error_ret;
}
ret = status & 0xF;
@@ -368,30 +216,30 @@
ret = -EFAULT;
if (status & ADIS16201_DIAG_STAT_SPI_FAIL)
- dev_err(dev, "SPI failure\n");
+ dev_err(&indio_dev->dev, "SPI failure\n");
if (status & ADIS16201_DIAG_STAT_FLASH_UPT)
- dev_err(dev, "Flash update failed\n");
+ dev_err(&indio_dev->dev, "Flash update failed\n");
if (status & ADIS16201_DIAG_STAT_POWER_HIGH)
- dev_err(dev, "Power supply above 3.625V\n");
+ dev_err(&indio_dev->dev, "Power supply above 3.625V\n");
if (status & ADIS16201_DIAG_STAT_POWER_LOW)
- dev_err(dev, "Power supply below 3.15V\n");
+ dev_err(&indio_dev->dev, "Power supply below 3.15V\n");
error_ret:
return ret;
}
-static int adis16201_self_test(struct device *dev)
+static int adis16201_self_test(struct iio_dev *indio_dev)
{
int ret;
- ret = adis16201_spi_write_reg_16(dev,
+ ret = adis16201_spi_write_reg_16(indio_dev,
ADIS16201_MSC_CTRL,
ADIS16201_MSC_CTRL_SELF_TEST_EN);
if (ret) {
- dev_err(dev, "problem starting self test");
+ dev_err(&indio_dev->dev, "problem starting self test");
goto err_ret;
}
- ret = adis16201_check_status(dev);
+ ret = adis16201_check_status(indio_dev);
err_ret:
return ret;
@@ -403,26 +251,26 @@
struct device *dev = &st->indio_dev->dev;
/* Disable IRQ */
- ret = adis16201_set_irq(dev, false);
+ ret = adis16201_set_irq(st->indio_dev, false);
if (ret) {
dev_err(dev, "disable irq failed");
goto err_ret;
}
/* Do self test */
- ret = adis16201_self_test(dev);
+ ret = adis16201_self_test(st->indio_dev);
if (ret) {
dev_err(dev, "self test failure");
goto err_ret;
}
/* Read status register to check the result */
- ret = adis16201_check_status(dev);
+ ret = adis16201_check_status(st->indio_dev);
if (ret) {
adis16201_reset(dev);
dev_err(dev, "device not playing ball -> reset");
msleep(ADIS16201_STARTUP_DELAY);
- ret = adis16201_check_status(dev);
+ ret = adis16201_check_status(st->indio_dev);
if (ret) {
dev_err(dev, "giving up");
goto err_ret;
@@ -436,77 +284,172 @@
return ret;
}
-static IIO_DEV_ATTR_IN_NAMED_RAW(0, supply, adis16201_read_12bit_unsigned,
- ADIS16201_SUPPLY_OUT);
-static IIO_CONST_ATTR(in0_supply_scale, "0.00122");
-static IIO_DEV_ATTR_IN_RAW(1, adis16201_read_12bit_unsigned,
- ADIS16201_AUX_ADC);
-static IIO_CONST_ATTR(in1_scale, "0.00061");
+static u8 adis16201_addresses[7][2] = {
+ [in_supply] = { ADIS16201_SUPPLY_OUT, },
+ [temp] = { ADIS16201_TEMP_OUT },
+ [accel_x] = { ADIS16201_XACCL_OUT, ADIS16201_XACCL_OFFS },
+ [accel_y] = { ADIS16201_YACCL_OUT, ADIS16201_YACCL_OFFS },
+ [in_aux] = { ADIS16201_AUX_ADC },
+ [incli_x] = { ADIS16201_XINCL_OUT },
+ [incli_y] = { ADIS16201_YINCL_OUT },
+};
-static IIO_DEV_ATTR_ACCEL_X(adis16201_read_14bit_signed,
- ADIS16201_XACCL_OUT);
-static IIO_DEV_ATTR_ACCEL_Y(adis16201_read_14bit_signed,
- ADIS16201_YACCL_OUT);
-static IIO_DEV_ATTR_ACCEL_X_OFFSET(S_IWUSR | S_IRUGO,
- adis16201_read_12bit_signed,
- adis16201_write_16bit,
- ADIS16201_XACCL_OFFS);
-static IIO_DEV_ATTR_ACCEL_Y_OFFSET(S_IWUSR | S_IRUGO,
- adis16201_read_12bit_signed,
- adis16201_write_16bit,
- ADIS16201_YACCL_OFFS);
-static IIO_CONST_ATTR(accel_scale, "0.4625");
+static int adis16201_read_raw(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ int *val, int *val2,
+ long mask)
+{
+ int ret;
+ int bits;
+ u8 addr;
+ s16 val16;
-static IIO_DEV_ATTR_INCLI_X(adis16201_read_14bit_signed,
- ADIS16201_XINCL_OUT);
-static IIO_DEV_ATTR_INCLI_Y(adis16201_read_14bit_signed,
- ADIS16201_YINCL_OUT);
-static IIO_DEV_ATTR_INCLI_X_OFFSET(S_IWUSR | S_IRUGO,
- adis16201_read_9bit_signed,
- adis16201_write_16bit,
- ADIS16201_XACCL_OFFS);
-static IIO_DEV_ATTR_INCLI_Y_OFFSET(S_IWUSR | S_IRUGO,
- adis16201_read_9bit_signed,
- adis16201_write_16bit,
- ADIS16201_YACCL_OFFS);
-static IIO_CONST_ATTR(incli_scale, "0.1");
+ switch (mask) {
+ case 0:
+ mutex_lock(&indio_dev->mlock);
+ addr = adis16201_addresses[chan->address][0];
+ ret = adis16201_spi_read_reg_16(indio_dev, addr, &val16);
+ if (ret)
+ return ret;
-static IIO_DEV_ATTR_TEMP_RAW(adis16201_read_temp);
-static IIO_CONST_ATTR(temp_offset, "25");
-static IIO_CONST_ATTR(temp_scale, "-0.47");
+ if (val16 & ADIS16201_ERROR_ACTIVE) {
+ ret = adis16201_check_status(indio_dev);
+ if (ret)
+ return ret;
+ }
+ val16 = val16 & ((1 << chan->scan_type.realbits) - 1);
+ if (chan->scan_type.sign == 's')
+ val16 = (s16)(val16 <<
+ (16 - chan->scan_type.realbits)) >>
+ (16 - chan->scan_type.realbits);
+ *val = val16;
+ mutex_unlock(&indio_dev->mlock);
+ return IIO_VAL_INT;
+ case (1 << IIO_CHAN_INFO_SCALE_SEPARATE):
+ case (1 << IIO_CHAN_INFO_SCALE_SHARED):
+ switch (chan->type) {
+ case IIO_IN:
+ *val = 0;
+ if (chan->channel == 0)
+ *val2 = 1220;
+ else
+ *val2 = 610;
+ return IIO_VAL_INT_PLUS_MICRO;
+ case IIO_TEMP:
+ *val = 0;
+ *val2 = -470000;
+ return IIO_VAL_INT_PLUS_MICRO;
+ case IIO_ACCEL:
+ *val = 0;
+ *val2 = 462500;
+ return IIO_VAL_INT_PLUS_MICRO;
+ case IIO_INCLI:
+ *val = 0;
+ *val2 = 100000;
+ return IIO_VAL_INT_PLUS_MICRO;
+ default:
+ return -EINVAL;
+ }
+ break;
+ case (1 << IIO_CHAN_INFO_OFFSET_SEPARATE):
+ *val = 25;
+ return IIO_VAL_INT;
+ case (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE):
+ switch (chan->type) {
+ case IIO_ACCEL:
+ bits = 12;
+ break;
+ case IIO_INCLI:
+ bits = 9;
+ break;
+ default:
+ return -EINVAL;
+ };
+ mutex_lock(&indio_dev->mlock);
+ addr = adis16201_addresses[chan->address][1];
+ ret = adis16201_spi_read_reg_16(indio_dev, addr, &val16);
+ if (ret) {
+ mutex_unlock(&indio_dev->mlock);
+ return ret;
+ }
+ val16 &= (1 << bits) - 1;
+ val16 = (s16)(val16 << (16 - bits)) >> (16 - bits);
+ *val = val16;
+ mutex_unlock(&indio_dev->mlock);
+ return IIO_VAL_INT;
+ }
+ return -EINVAL;
+}
+
+static int adis16201_write_raw(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ int val,
+ int val2,
+ long mask)
+{
+ int bits;
+ s16 val16;
+ u8 addr;
+ switch (mask) {
+ case (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE):
+ switch (chan->type) {
+ case IIO_ACCEL:
+ bits = 12;
+ break;
+ case IIO_INCLI:
+ bits = 9;
+ break;
+ default:
+ return -EINVAL;
+ };
+ val16 = val & ((1 << bits) - 1);
+ addr = adis16201_addresses[chan->address][1];
+ return adis16201_spi_write_reg_16(indio_dev, addr, val16);
+ }
+ return -EINVAL;
+}
+
+static struct iio_chan_spec adis16201_channels[] = {
+ IIO_CHAN(IIO_IN, 0, 1, 0, "supply", 0, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SEPARATE),
+ in_supply, ADIS16201_SCAN_SUPPLY,
+ IIO_ST('u', 12, 16, 0), 0),
+ IIO_CHAN(IIO_TEMP, 0, 1, 0, NULL, 0, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SEPARATE) |
+ (1 << IIO_CHAN_INFO_OFFSET_SEPARATE),
+ temp, ADIS16201_SCAN_TEMP,
+ IIO_ST('u', 12, 16, 0), 0),
+ IIO_CHAN(IIO_ACCEL, 1, 0, 0, NULL, 0, IIO_MOD_X,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED) |
+ (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE),
+ accel_x, ADIS16201_SCAN_ACC_X,
+ IIO_ST('s', 14, 16, 0), 0),
+ IIO_CHAN(IIO_ACCEL, 1, 0, 0, NULL, 0, IIO_MOD_Y,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED) |
+ (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE),
+ accel_y, ADIS16201_SCAN_ACC_Y,
+ IIO_ST('s', 14, 16, 0), 0),
+ IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 1, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SEPARATE),
+ in_aux, ADIS16201_SCAN_AUX_ADC,
+ IIO_ST('u', 12, 16, 0), 0),
+ IIO_CHAN(IIO_INCLI, 1, 0, 0, NULL, 0, IIO_MOD_X,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED) |
+ (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE),
+ incli_x, ADIS16201_SCAN_INCLI_X,
+ IIO_ST('s', 14, 16, 0), 0),
+ IIO_CHAN(IIO_INCLI, 1, 0, 0, NULL, 0, IIO_MOD_Y,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED) |
+ (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE),
+ incli_y, ADIS16201_SCAN_INCLI_Y,
+ IIO_ST('s', 14, 16, 0), 0),
+ IIO_CHAN_SOFT_TIMESTAMP(7)
+};
static IIO_DEVICE_ATTR(reset, S_IWUSR, NULL, adis16201_write_reset, 0);
-static IIO_CONST_ATTR(name, "adis16201");
-
-static struct attribute *adis16201_event_attributes[] = {
- NULL
-};
-
-static struct attribute_group adis16201_event_attribute_group = {
- .attrs = adis16201_event_attributes,
-};
-
static struct attribute *adis16201_attributes[] = {
- &iio_dev_attr_in0_supply_raw.dev_attr.attr,
- &iio_const_attr_in0_supply_scale.dev_attr.attr,
- &iio_dev_attr_temp_raw.dev_attr.attr,
- &iio_const_attr_temp_offset.dev_attr.attr,
- &iio_const_attr_temp_scale.dev_attr.attr,
&iio_dev_attr_reset.dev_attr.attr,
- &iio_const_attr_name.dev_attr.attr,
- &iio_dev_attr_in1_raw.dev_attr.attr,
- &iio_const_attr_in1_scale.dev_attr.attr,
- &iio_dev_attr_accel_x_raw.dev_attr.attr,
- &iio_dev_attr_accel_y_raw.dev_attr.attr,
- &iio_dev_attr_accel_x_offset.dev_attr.attr,
- &iio_dev_attr_accel_y_offset.dev_attr.attr,
- &iio_const_attr_accel_scale.dev_attr.attr,
- &iio_dev_attr_incli_x_raw.dev_attr.attr,
- &iio_dev_attr_incli_y_raw.dev_attr.attr,
- &iio_dev_attr_incli_x_offset.dev_attr.attr,
- &iio_dev_attr_incli_y_offset.dev_attr.attr,
- &iio_const_attr_incli_scale.dev_attr.attr,
NULL
};
@@ -514,6 +457,13 @@
.attrs = adis16201_attributes,
};
+static const struct iio_info adis16201_info = {
+ .attrs = &adis16201_attribute_group,
+ .read_raw = &adis16201_read_raw,
+ .write_raw = &adis16201_write_raw,
+ .driver_module = THIS_MODULE,
+};
+
static int __devinit adis16201_probe(struct spi_device *spi)
{
int ret, regdone = 0;
@@ -539,18 +489,19 @@
st->us = spi;
mutex_init(&st->buf_lock);
/* setup the industrialio driver allocated elements */
- st->indio_dev = iio_allocate_device();
+ st->indio_dev = iio_allocate_device(0);
if (st->indio_dev == NULL) {
ret = -ENOMEM;
goto error_free_tx;
}
+ st->indio_dev->name = spi->dev.driver->name;
st->indio_dev->dev.parent = &spi->dev;
- st->indio_dev->num_interrupt_lines = 1;
- st->indio_dev->event_attrs = &adis16201_event_attribute_group;
- st->indio_dev->attrs = &adis16201_attribute_group;
+ st->indio_dev->info = &adis16201_info;
+
+ st->indio_dev->channels = adis16201_channels;
+ st->indio_dev->num_channels = ARRAY_SIZE(adis16201_channels);
st->indio_dev->dev_data = (void *)(st);
- st->indio_dev->driver_module = THIS_MODULE;
st->indio_dev->modes = INDIO_DIRECT_MODE;
ret = adis16201_configure_ring(st->indio_dev);
@@ -562,24 +513,18 @@
goto error_unreg_ring_funcs;
regdone = 1;
- ret = adis16201_initialize_ring(st->indio_dev->ring);
+ ret = iio_ring_buffer_register_ex(st->indio_dev->ring, 0,
+ adis16201_channels,
+ ARRAY_SIZE(adis16201_channels));
if (ret) {
printk(KERN_ERR "failed to initialize the ring\n");
goto error_unreg_ring_funcs;
}
if (spi->irq) {
- ret = iio_register_interrupt_line(spi->irq,
- st->indio_dev,
- 0,
- IRQF_TRIGGER_RISING,
- "adis16201");
- if (ret)
- goto error_uninitialize_ring;
-
ret = adis16201_probe_trigger(st->indio_dev);
if (ret)
- goto error_unregister_line;
+ goto error_uninitialize_ring;
}
/* Get the device into a sane initial state */
@@ -590,11 +535,8 @@
error_remove_trigger:
adis16201_remove_trigger(st->indio_dev);
-error_unregister_line:
- if (spi->irq)
- iio_unregister_interrupt_line(st->indio_dev, 0);
error_uninitialize_ring:
- adis16201_uninitialize_ring(st->indio_dev->ring);
+ iio_ring_buffer_unregister(st->indio_dev->ring);
error_unreg_ring_funcs:
adis16201_unconfigure_ring(st->indio_dev);
error_free_dev:
@@ -617,13 +559,8 @@
struct adis16201_state *st = spi_get_drvdata(spi);
struct iio_dev *indio_dev = st->indio_dev;
- flush_scheduled_work();
-
adis16201_remove_trigger(indio_dev);
- if (spi->irq)
- iio_unregister_interrupt_line(indio_dev, 0);
-
- adis16201_uninitialize_ring(indio_dev->ring);
+ iio_ring_buffer_unregister(indio_dev->ring);
iio_device_unregister(indio_dev);
adis16201_unconfigure_ring(indio_dev);
kfree(st->tx);
diff --git a/drivers/staging/iio/accel/adis16201_ring.c b/drivers/staging/iio/accel/adis16201_ring.c
index e6870a2..c61f981 100644
--- a/drivers/staging/iio/accel/adis16201_ring.c
+++ b/drivers/staging/iio/accel/adis16201_ring.c
@@ -1,14 +1,11 @@
#include <linux/interrupt.h>
#include <linux/irq.h>
-#include <linux/gpio.h>
-#include <linux/workqueue.h>
#include <linux/mutex.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/spi/spi.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
-#include <linux/list.h>
#include "../iio.h"
#include "../sysfs.h"
@@ -17,74 +14,15 @@
#include "../trigger.h"
#include "adis16201.h"
-static IIO_SCAN_EL_C(in_supply, ADIS16201_SCAN_SUPPLY, ADIS16201_SUPPLY_OUT, NULL);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(in_supply, u, 12, 16);
-static IIO_SCAN_EL_C(accel_x, ADIS16201_SCAN_ACC_X, ADIS16201_XACCL_OUT, NULL);
-static IIO_SCAN_EL_C(accel_y, ADIS16201_SCAN_ACC_Y, ADIS16201_YACCL_OUT, NULL);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(accel, s, 14, 16);
-static IIO_SCAN_EL_C(in0, ADIS16201_SCAN_AUX_ADC, ADIS16201_AUX_ADC, NULL);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(in0, u, 12, 16);
-static IIO_SCAN_EL_C(temp, ADIS16201_SCAN_TEMP, ADIS16201_TEMP_OUT, NULL);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(temp, u, 12, 16);
-static IIO_SCAN_EL_C(incli_x, ADIS16201_SCAN_INCLI_X,
- ADIS16201_XINCL_OUT, NULL);
-static IIO_SCAN_EL_C(incli_y, ADIS16201_SCAN_INCLI_Y,
- ADIS16201_YINCL_OUT, NULL);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(incli, s, 14, 16);
-static IIO_SCAN_EL_TIMESTAMP(7);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(timestamp, s, 64, 64);
-
-static struct attribute *adis16201_scan_el_attrs[] = {
- &iio_scan_el_in_supply.dev_attr.attr,
- &iio_const_attr_in_supply_index.dev_attr.attr,
- &iio_const_attr_in_supply_type.dev_attr.attr,
- &iio_scan_el_accel_x.dev_attr.attr,
- &iio_const_attr_accel_x_index.dev_attr.attr,
- &iio_scan_el_accel_y.dev_attr.attr,
- &iio_const_attr_accel_y_index.dev_attr.attr,
- &iio_const_attr_accel_type.dev_attr.attr,
- &iio_scan_el_in0.dev_attr.attr,
- &iio_const_attr_in0_index.dev_attr.attr,
- &iio_const_attr_in0_type.dev_attr.attr,
- &iio_scan_el_temp.dev_attr.attr,
- &iio_const_attr_temp_index.dev_attr.attr,
- &iio_const_attr_temp_type.dev_attr.attr,
- &iio_scan_el_incli_x.dev_attr.attr,
- &iio_const_attr_incli_x_index.dev_attr.attr,
- &iio_scan_el_incli_y.dev_attr.attr,
- &iio_const_attr_incli_y_index.dev_attr.attr,
- &iio_const_attr_incli_type.dev_attr.attr,
- &iio_scan_el_timestamp.dev_attr.attr,
- &iio_const_attr_timestamp_index.dev_attr.attr,
- &iio_const_attr_timestamp_type.dev_attr.attr,
- NULL,
-};
-
-static struct attribute_group adis16201_scan_el_group = {
- .attrs = adis16201_scan_el_attrs,
- .name = "scan_elements",
-};
-
-/**
- * adis16201_poll_func_th() top half interrupt handler called by trigger
- * @private_data: iio_dev
- **/
-static void adis16201_poll_func_th(struct iio_dev *indio_dev, s64 time)
-{
- struct adis16201_state *st = iio_dev_get_devdata(indio_dev);
- st->last_timestamp = time;
- schedule_work(&st->work_trigger_to_ring);
-}
/**
* adis16201_read_ring_data() read data registers which will be placed into ring
* @dev: device associated with child of actual device (iio_dev or iio_trig)
* @rx: somewhere to pass back the value read
**/
-static int adis16201_read_ring_data(struct device *dev, u8 *rx)
+static int adis16201_read_ring_data(struct iio_dev *indio_dev, u8 *rx)
{
struct spi_message msg;
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct adis16201_state *st = iio_dev_get_devdata(indio_dev);
struct spi_transfer xfers[ADIS16201_OUTPUTS + 1];
int ret;
@@ -101,7 +39,8 @@
xfers[i].len = 2;
xfers[i].delay_usecs = 20;
xfers[i].tx_buf = st->tx + 2 * i;
- st->tx[2 * i] = ADIS16201_READ_REG(ADIS16201_SUPPLY_OUT + 2 * i);
+ st->tx[2 * i] = ADIS16201_READ_REG(ADIS16201_SUPPLY_OUT +
+ 2 * i);
st->tx[2 * i + 1] = 0;
if (i >= 1)
xfers[i].rx_buf = rx + 2 * (i - 1);
@@ -120,55 +59,57 @@
/* Whilst this makes a lot of calls to iio_sw_ring functions - it is to device
* specific to be rolled into the core.
*/
-static void adis16201_trigger_bh_to_ring(struct work_struct *work_s)
+static irqreturn_t adis16201_trigger_handler(int irq, void *p)
{
- struct adis16201_state *st
- = container_of(work_s, struct adis16201_state,
- work_trigger_to_ring);
- struct iio_ring_buffer *ring = st->indio_dev->ring;
+ struct iio_poll_func *pf = p;
+ struct iio_dev *indio_dev = pf->private_data;
+ struct adis16201_state *st = iio_dev_get_devdata(indio_dev);
+ struct iio_ring_buffer *ring = indio_dev->ring;
int i = 0;
s16 *data;
- size_t datasize = ring->access.get_bytes_per_datum(ring);
+ size_t datasize = ring->access->get_bytes_per_datum(ring);
data = kmalloc(datasize, GFP_KERNEL);
if (data == NULL) {
dev_err(&st->us->dev, "memory alloc failed in ring bh");
- return;
+ return -ENOMEM;
}
if (ring->scan_count)
- if (adis16201_read_ring_data(&st->indio_dev->dev, st->rx) >= 0)
+ if (adis16201_read_ring_data(st->indio_dev, st->rx) >= 0)
for (; i < ring->scan_count; i++)
data[i] = be16_to_cpup(
(__be16 *)&(st->rx[i*2]));
/* Guaranteed to be aligned with 8 byte boundary */
if (ring->scan_timestamp)
- *((s64 *)(data + ((i + 3)/4)*4)) = st->last_timestamp;
+ *((s64 *)(data + ((i + 3)/4)*4)) = pf->timestamp;
- ring->access.store_to(ring,
- (u8 *)data,
- st->last_timestamp);
+ ring->access->store_to(ring, (u8 *)data, pf->timestamp);
iio_trigger_notify_done(st->indio_dev->trig);
kfree(data);
- return;
+ return IRQ_HANDLED;
}
void adis16201_unconfigure_ring(struct iio_dev *indio_dev)
{
- kfree(indio_dev->pollfunc);
+ iio_dealloc_pollfunc(indio_dev->pollfunc);
iio_sw_rb_free(indio_dev->ring);
}
+static const struct iio_ring_setup_ops adis16201_ring_setup_ops = {
+ .preenable = &iio_sw_ring_preenable,
+ .postenable = &iio_triggered_ring_postenable,
+ .predisable = &iio_triggered_ring_predisable,
+};
+
int adis16201_configure_ring(struct iio_dev *indio_dev)
{
int ret = 0;
- struct adis16201_state *st = indio_dev->dev_data;
struct iio_ring_buffer *ring;
- INIT_WORK(&st->work_trigger_to_ring, adis16201_trigger_bh_to_ring);
ring = iio_sw_rb_allocate(indio_dev);
if (!ring) {
@@ -177,42 +118,35 @@
}
indio_dev->ring = ring;
/* Effectively select the ring buffer implementation */
- iio_ring_sw_register_funcs(&ring->access);
ring->bpe = 2;
- ring->scan_el_attrs = &adis16201_scan_el_group;
ring->scan_timestamp = true;
- ring->preenable = &iio_sw_ring_preenable;
- ring->postenable = &iio_triggered_ring_postenable;
- ring->predisable = &iio_triggered_ring_predisable;
+ ring->access = &ring_sw_access_funcs;
+ ring->setup_ops = &adis16201_ring_setup_ops;
ring->owner = THIS_MODULE;
/* Set default scan mode */
- iio_scan_mask_set(ring, iio_scan_el_in_supply.number);
- iio_scan_mask_set(ring, iio_scan_el_accel_x.number);
- iio_scan_mask_set(ring, iio_scan_el_accel_y.number);
- iio_scan_mask_set(ring, iio_scan_el_temp.number);
- iio_scan_mask_set(ring, iio_scan_el_in0.number);
- iio_scan_mask_set(ring, iio_scan_el_incli_x.number);
- iio_scan_mask_set(ring, iio_scan_el_incli_y.number);
+ iio_scan_mask_set(ring, ADIS16201_SCAN_SUPPLY);
+ iio_scan_mask_set(ring, ADIS16201_SCAN_ACC_X);
+ iio_scan_mask_set(ring, ADIS16201_SCAN_ACC_Y);
+ iio_scan_mask_set(ring, ADIS16201_SCAN_AUX_ADC);
+ iio_scan_mask_set(ring, ADIS16201_SCAN_TEMP);
+ iio_scan_mask_set(ring, ADIS16201_SCAN_INCLI_X);
+ iio_scan_mask_set(ring, ADIS16201_SCAN_INCLI_Y);
- ret = iio_alloc_pollfunc(indio_dev, NULL, &adis16201_poll_func_th);
- if (ret)
+ indio_dev->pollfunc = iio_alloc_pollfunc(&iio_pollfunc_store_time,
+ &adis16201_trigger_handler,
+ IRQF_ONESHOT,
+ indio_dev,
+ "adis16201_consumer%d",
+ indio_dev->id);
+ if (indio_dev->pollfunc == NULL) {
+ ret = -ENOMEM;
goto error_iio_sw_rb_free;
+ }
indio_dev->modes |= INDIO_RING_TRIGGERED;
return 0;
-
error_iio_sw_rb_free:
iio_sw_rb_free(indio_dev->ring);
return ret;
}
-
-int adis16201_initialize_ring(struct iio_ring_buffer *ring)
-{
- return iio_ring_buffer_register(ring, 0);
-}
-
-void adis16201_uninitialize_ring(struct iio_ring_buffer *ring)
-{
- iio_ring_buffer_unregister(ring);
-}
diff --git a/drivers/staging/iio/accel/adis16201_trigger.c b/drivers/staging/iio/accel/adis16201_trigger.c
index 8a9cea19..bea917e 100644
--- a/drivers/staging/iio/accel/adis16201_trigger.c
+++ b/drivers/staging/iio/accel/adis16201_trigger.c
@@ -4,7 +4,6 @@
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/sysfs.h>
-#include <linux/list.h>
#include <linux/spi/spi.h>
#include "../iio.h"
@@ -13,35 +12,6 @@
#include "adis16201.h"
/**
- * adis16201_data_rdy_trig_poll() the event handler for the data rdy trig
- **/
-static int adis16201_data_rdy_trig_poll(struct iio_dev *dev_info,
- int index,
- s64 timestamp,
- int no_test)
-{
- struct adis16201_state *st = iio_dev_get_devdata(dev_info);
- struct iio_trigger *trig = st->trig;
-
- iio_trigger_poll(trig, timestamp);
-
- return IRQ_HANDLED;
-}
-
-IIO_EVENT_SH(data_rdy_trig, &adis16201_data_rdy_trig_poll);
-
-static DEVICE_ATTR(name, S_IRUGO, iio_trigger_read_name, NULL);
-
-static struct attribute *adis16201_trigger_attrs[] = {
- &dev_attr_name.attr,
- NULL,
-};
-
-static const struct attribute_group adis16201_trigger_attr_group = {
- .attrs = adis16201_trigger_attrs,
-};
-
-/**
* adis16201_data_rdy_trigger_set_state() set datardy interrupt state
**/
static int adis16201_data_rdy_trigger_set_state(struct iio_trigger *trig,
@@ -49,31 +19,9 @@
{
struct adis16201_state *st = trig->private_data;
struct iio_dev *indio_dev = st->indio_dev;
- int ret = 0;
dev_dbg(&indio_dev->dev, "%s (%d)\n", __func__, state);
- ret = adis16201_set_irq(&st->indio_dev->dev, state);
- if (state == false) {
- iio_remove_event_from_list(&iio_event_data_rdy_trig,
- &indio_dev->interrupts[0]
- ->ev_list);
- flush_scheduled_work();
- } else {
- iio_add_event_to_list(&iio_event_data_rdy_trig,
- &indio_dev->interrupts[0]->ev_list);
- }
- return ret;
-}
-
-/**
- * adis16201_trig_try_reen() try renabling irq for data rdy trigger
- * @trig: the datardy trigger
- **/
-static int adis16201_trig_try_reen(struct iio_trigger *trig)
-{
- struct adis16201_state *st = trig->private_data;
- enable_irq(st->us->irq);
- return 0;
+ return adis16201_set_irq(st->indio_dev, state);
}
int adis16201_probe_trigger(struct iio_dev *indio_dev)
@@ -81,34 +29,36 @@
int ret;
struct adis16201_state *st = indio_dev->dev_data;
- st->trig = iio_allocate_trigger();
- st->trig->name = kasprintf(GFP_KERNEL,
- "adis16201-dev%d",
- indio_dev->id);
- if (!st->trig->name) {
+ st->trig = iio_allocate_trigger("adis16201-dev%d", indio_dev->id);
+ if (st->trig == NULL) {
ret = -ENOMEM;
- goto error_free_trig;
+ goto error_ret;
}
+ ret = request_irq(st->us->irq,
+ &iio_trigger_generic_data_rdy_poll,
+ IRQF_TRIGGER_RISING,
+ "adis16201",
+ st->trig);
+ if (ret)
+ goto error_free_trig;
st->trig->dev.parent = &st->us->dev;
st->trig->owner = THIS_MODULE;
st->trig->private_data = st;
st->trig->set_trigger_state = &adis16201_data_rdy_trigger_set_state;
- st->trig->try_reenable = &adis16201_trig_try_reen;
- st->trig->control_attrs = &adis16201_trigger_attr_group;
ret = iio_trigger_register(st->trig);
/* select default trigger */
indio_dev->trig = st->trig;
if (ret)
- goto error_free_trig_name;
+ goto error_free_irq;
return 0;
-error_free_trig_name:
- kfree(st->trig->name);
+error_free_irq:
+ free_irq(st->us->irq, st->trig);
error_free_trig:
iio_free_trigger(st->trig);
-
+error_ret:
return ret;
}
@@ -117,6 +67,6 @@
struct adis16201_state *state = indio_dev->dev_data;
iio_trigger_unregister(state->trig);
- kfree(state->trig->name);
+ free_irq(state->us->irq, state->trig);
iio_free_trigger(state->trig);
}
diff --git a/drivers/staging/iio/accel/adis16203.h b/drivers/staging/iio/accel/adis16203.h
index b886881..8bb8ce5 100644
--- a/drivers/staging/iio/accel/adis16203.h
+++ b/drivers/staging/iio/accel/adis16203.h
@@ -59,9 +59,6 @@
/**
* struct adis16203_state - device instance specific data
* @us: actual spi_device
- * @work_trigger_to_ring: bh for triggered event handling
- * @inter: used to check if new interrupt has been triggered
- * @last_timestamp: passing timestamp from th to bh of interrupt handler
* @indio_dev: industrial I/O device structure
* @trig: data ready trigger registered with iio
* @tx: transmit buffer
@@ -70,8 +67,6 @@
**/
struct adis16203_state {
struct spi_device *us;
- struct work_struct work_trigger_to_ring;
- s64 last_timestamp;
struct iio_dev *indio_dev;
struct iio_trigger *trig;
u8 *tx;
@@ -79,7 +74,7 @@
struct mutex buf_lock;
};
-int adis16203_set_irq(struct device *dev, bool enable);
+int adis16203_set_irq(struct iio_dev *indio_dev, bool enable);
#ifdef CONFIG_IIO_RING_BUFFER
enum adis16203_scan {
@@ -100,8 +95,6 @@
int adis16203_configure_ring(struct iio_dev *indio_dev);
void adis16203_unconfigure_ring(struct iio_dev *indio_dev);
-int adis16203_initialize_ring(struct iio_ring_buffer *ring);
-void adis16203_uninitialize_ring(struct iio_ring_buffer *ring);
#else /* CONFIG_IIO_RING_BUFFER */
static inline void adis16203_remove_trigger(struct iio_dev *indio_dev)
@@ -130,14 +123,5 @@
{
}
-static inline int adis16203_initialize_ring(struct iio_ring_buffer *ring)
-{
- return 0;
-}
-
-static inline void adis16203_uninitialize_ring(struct iio_ring_buffer *ring)
-{
-}
-
#endif /* CONFIG_IIO_RING_BUFFER */
#endif /* SPI_ADIS16203_H_ */
diff --git a/drivers/staging/iio/accel/adis16203_core.c b/drivers/staging/iio/accel/adis16203_core.c
index b57f190..36be4d5 100644
--- a/drivers/staging/iio/accel/adis16203_core.c
+++ b/drivers/staging/iio/accel/adis16203_core.c
@@ -6,9 +6,6 @@
* Licensed under the GPL-2 or later.
*/
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/gpio.h>
#include <linux/delay.h>
#include <linux/mutex.h>
#include <linux/device.h>
@@ -16,33 +13,29 @@
#include <linux/spi/spi.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
-#include <linux/list.h>
#include "../iio.h"
#include "../sysfs.h"
#include "accel.h"
#include "inclinometer.h"
-#include "../gyro/gyro.h"
+#include "../ring_generic.h"
#include "../adc/adc.h"
#include "adis16203.h"
#define DRIVER_NAME "adis16203"
-static int adis16203_check_status(struct device *dev);
-
/**
* adis16203_spi_write_reg_8() - write single byte to a register
- * @dev: device associated with child of actual device (iio_dev or iio_trig)
+ * @indio_dev: iio device associated with child of actual device
* @reg_address: the address of the register to be written
* @val: the value to write
**/
-static int adis16203_spi_write_reg_8(struct device *dev,
- u8 reg_address,
- u8 val)
+static int adis16203_spi_write_reg_8(struct iio_dev *indio_dev,
+ u8 reg_address,
+ u8 val)
{
int ret;
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct adis16203_state *st = iio_dev_get_devdata(indio_dev);
mutex_lock(&st->buf_lock);
@@ -57,18 +50,17 @@
/**
* adis16203_spi_write_reg_16() - write 2 bytes to a pair of registers
- * @dev: device associated with child of actual device (iio_dev or iio_trig)
+ * @indio_dev: iio device associated with child of actual device
* @reg_address: the address of the lower of the two registers. Second register
* is assumed to have address one greater.
* @val: value to be written
**/
-static int adis16203_spi_write_reg_16(struct device *dev,
- u8 lower_reg_address,
- u16 value)
+static int adis16203_spi_write_reg_16(struct iio_dev *indio_dev,
+ u8 lower_reg_address,
+ u16 value)
{
int ret;
struct spi_message msg;
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct adis16203_state *st = iio_dev_get_devdata(indio_dev);
struct spi_transfer xfers[] = {
{
@@ -80,7 +72,6 @@
.tx_buf = st->tx + 2,
.bits_per_word = 8,
.len = 2,
- .cs_change = 1,
},
};
@@ -101,17 +92,16 @@
/**
* adis16203_spi_read_reg_16() - read 2 bytes from a 16-bit register
- * @dev: device associated with child of actual device (iio_dev or iio_trig)
+ * @indio_dev: iio device associated with child of actual device
* @reg_address: the address of the lower of the two registers. Second register
* is assumed to have address one greater.
* @val: somewhere to pass back the value read
**/
-static int adis16203_spi_read_reg_16(struct device *dev,
+static int adis16203_spi_read_reg_16(struct iio_dev *indio_dev,
u8 lower_reg_address,
u16 *val)
{
struct spi_message msg;
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct adis16203_state *st = iio_dev_get_devdata(indio_dev);
int ret;
struct spi_transfer xfers[] = {
@@ -125,7 +115,6 @@
.rx_buf = st->rx,
.bits_per_word = 8,
.len = 2,
- .cs_change = 1,
.delay_usecs = 20,
},
};
@@ -150,101 +139,43 @@
return ret;
}
-static ssize_t adis16203_read_12bit_unsigned(struct device *dev,
- struct device_attribute *attr,
- char *buf)
+static int adis16203_check_status(struct iio_dev *indio_dev)
{
+ u16 status;
int ret;
- u16 val = 0;
- struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
- ret = adis16203_spi_read_reg_16(dev, this_attr->address, &val);
- if (ret)
- return ret;
-
- if (val & ADIS16203_ERROR_ACTIVE)
- adis16203_check_status(dev);
-
- return sprintf(buf, "%u\n", val & 0x0FFF);
-}
-
-static ssize_t adis16203_read_temp(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
- ssize_t ret;
- u16 val;
-
- /* Take the iio_dev status lock */
- mutex_lock(&indio_dev->mlock);
-
- ret = adis16203_spi_read_reg_16(dev, ADIS16203_TEMP_OUT, (u16 *)&val);
- if (ret)
+ ret = adis16203_spi_read_reg_16(indio_dev,
+ ADIS16203_DIAG_STAT,
+ &status);
+ if (ret < 0) {
+ dev_err(&indio_dev->dev, "Reading status failed\n");
goto error_ret;
-
- if (val & ADIS16203_ERROR_ACTIVE)
- adis16203_check_status(dev);
-
- val &= 0xFFF;
- ret = sprintf(buf, "%d\n", val);
-
-error_ret:
- mutex_unlock(&indio_dev->mlock);
- return ret;
-}
-
-static ssize_t adis16203_read_14bit_signed(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
- struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
- s16 val = 0;
- ssize_t ret;
-
- mutex_lock(&indio_dev->mlock);
-
- ret = adis16203_spi_read_reg_16(dev, this_attr->address, (u16 *)&val);
- if (!ret) {
- if (val & ADIS16203_ERROR_ACTIVE)
- adis16203_check_status(dev);
-
- val = ((s16)(val << 2) >> 2);
- ret = sprintf(buf, "%d\n", val);
}
+ ret = status & 0x1F;
- mutex_unlock(&indio_dev->mlock);
+ if (status & ADIS16203_DIAG_STAT_SELFTEST_FAIL)
+ dev_err(&indio_dev->dev, "Self test failure\n");
+ if (status & ADIS16203_DIAG_STAT_SPI_FAIL)
+ dev_err(&indio_dev->dev, "SPI failure\n");
+ if (status & ADIS16203_DIAG_STAT_FLASH_UPT)
+ dev_err(&indio_dev->dev, "Flash update failed\n");
+ if (status & ADIS16203_DIAG_STAT_POWER_HIGH)
+ dev_err(&indio_dev->dev, "Power supply above 3.625V\n");
+ if (status & ADIS16203_DIAG_STAT_POWER_LOW)
+ dev_err(&indio_dev->dev, "Power supply below 3.15V\n");
+error_ret:
return ret;
}
-static ssize_t adis16203_write_16bit(struct device *dev,
- struct device_attribute *attr,
- const char *buf,
- size_t len)
-{
- struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
- int ret;
- long val;
-
- ret = strict_strtol(buf, 10, &val);
- if (ret)
- goto error_ret;
- ret = adis16203_spi_write_reg_16(dev, this_attr->address, val);
-
-error_ret:
- return ret ? ret : len;
-}
-
-static int adis16203_reset(struct device *dev)
+static int adis16203_reset(struct iio_dev *indio_dev)
{
int ret;
- ret = adis16203_spi_write_reg_8(dev,
+ ret = adis16203_spi_write_reg_8(indio_dev,
ADIS16203_GLOB_CMD,
ADIS16203_GLOB_CMD_SW_RESET);
if (ret)
- dev_err(dev, "problem resetting device");
+ dev_err(&indio_dev->dev, "problem resetting device");
return ret;
}
@@ -253,23 +184,24 @@
struct device_attribute *attr,
const char *buf, size_t len)
{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
if (len < 1)
return -EINVAL;
switch (buf[0]) {
case '1':
case 'y':
case 'Y':
- return adis16203_reset(dev);
+ return adis16203_reset(indio_dev);
}
return -EINVAL;
}
-int adis16203_set_irq(struct device *dev, bool enable)
+int adis16203_set_irq(struct iio_dev *indio_dev, bool enable)
{
int ret = 0;
u16 msc;
- ret = adis16203_spi_read_reg_16(dev, ADIS16203_MSC_CTRL, &msc);
+ ret = adis16203_spi_read_reg_16(indio_dev, ADIS16203_MSC_CTRL, &msc);
if (ret)
goto error_ret;
@@ -280,142 +212,195 @@
else
msc &= ~ADIS16203_MSC_CTRL_DATA_RDY_EN;
- ret = adis16203_spi_write_reg_16(dev, ADIS16203_MSC_CTRL, msc);
+ ret = adis16203_spi_write_reg_16(indio_dev, ADIS16203_MSC_CTRL, msc);
error_ret:
return ret;
}
-static int adis16203_check_status(struct device *dev)
-{
- u16 status;
- int ret;
-
- ret = adis16203_spi_read_reg_16(dev, ADIS16203_DIAG_STAT, &status);
- if (ret < 0) {
- dev_err(dev, "Reading status failed\n");
- goto error_ret;
- }
- ret = status & 0x1F;
-
- if (status & ADIS16203_DIAG_STAT_SELFTEST_FAIL)
- dev_err(dev, "Self test failure\n");
- if (status & ADIS16203_DIAG_STAT_SPI_FAIL)
- dev_err(dev, "SPI failure\n");
- if (status & ADIS16203_DIAG_STAT_FLASH_UPT)
- dev_err(dev, "Flash update failed\n");
- if (status & ADIS16203_DIAG_STAT_POWER_HIGH)
- dev_err(dev, "Power supply above 3.625V\n");
- if (status & ADIS16203_DIAG_STAT_POWER_LOW)
- dev_err(dev, "Power supply below 3.15V\n");
-
-error_ret:
- return ret;
-}
-
-static int adis16203_self_test(struct device *dev)
+static int adis16203_self_test(struct iio_dev *indio_dev)
{
int ret;
- ret = adis16203_spi_write_reg_16(dev,
+ ret = adis16203_spi_write_reg_16(indio_dev,
ADIS16203_MSC_CTRL,
ADIS16203_MSC_CTRL_SELF_TEST_EN);
if (ret) {
- dev_err(dev, "problem starting self test");
+ dev_err(&indio_dev->dev, "problem starting self test");
goto err_ret;
}
- adis16203_check_status(dev);
+ adis16203_check_status(indio_dev);
err_ret:
return ret;
}
-static int adis16203_initial_setup(struct adis16203_state *st)
+static int adis16203_initial_setup(struct iio_dev *indio_dev)
{
int ret;
- struct device *dev = &st->indio_dev->dev;
/* Disable IRQ */
- ret = adis16203_set_irq(dev, false);
+ ret = adis16203_set_irq(indio_dev, false);
if (ret) {
- dev_err(dev, "disable irq failed");
+ dev_err(&indio_dev->dev, "disable irq failed");
goto err_ret;
}
/* Do self test */
- ret = adis16203_self_test(dev);
+ ret = adis16203_self_test(indio_dev);
if (ret) {
- dev_err(dev, "self test failure");
+ dev_err(&indio_dev->dev, "self test failure");
goto err_ret;
}
/* Read status register to check the result */
- ret = adis16203_check_status(dev);
+ ret = adis16203_check_status(indio_dev);
if (ret) {
- adis16203_reset(dev);
- dev_err(dev, "device not playing ball -> reset");
+ adis16203_reset(indio_dev);
+ dev_err(&indio_dev->dev, "device not playing ball -> reset");
msleep(ADIS16203_STARTUP_DELAY);
- ret = adis16203_check_status(dev);
+ ret = adis16203_check_status(indio_dev);
if (ret) {
- dev_err(dev, "giving up");
+ dev_err(&indio_dev->dev, "giving up");
goto err_ret;
}
}
- printk(KERN_INFO DRIVER_NAME ": at CS%d (irq %d)\n",
- st->us->chip_select, st->us->irq);
-
err_ret:
return ret;
}
-static IIO_DEV_ATTR_IN_NAMED_RAW(0, supply, adis16203_read_12bit_unsigned,
- ADIS16203_SUPPLY_OUT);
-static IIO_CONST_ATTR(in0_supply_scale, "0.00122");
-static IIO_DEV_ATTR_IN_RAW(1, adis16203_read_12bit_unsigned,
- ADIS16203_AUX_ADC);
-static IIO_CONST_ATTR(in1_scale, "0.00061");
+enum adis16203_chan {
+ in_supply,
+ in_aux,
+ incli_x,
+ incli_y,
+ temp,
+};
-static IIO_DEV_ATTR_INCLI_X(adis16203_read_14bit_signed,
- ADIS16203_XINCL_OUT);
-static IIO_DEV_ATTR_INCLI_Y(adis16203_read_14bit_signed,
- ADIS16203_YINCL_OUT);
-static IIO_DEV_ATTR_INCLI_X_OFFSET(S_IWUSR | S_IRUGO,
- adis16203_read_14bit_signed,
- adis16203_write_16bit,
- ADIS16203_INCL_NULL);
-static IIO_CONST_ATTR(incli_scale, "0.025");
+static u8 adis16203_addresses[5][2] = {
+ [in_supply] = { ADIS16203_SUPPLY_OUT },
+ [in_aux] = { ADIS16203_AUX_ADC },
+ [incli_x] = { ADIS16203_XINCL_OUT, ADIS16203_INCL_NULL},
+ [incli_y] = { ADIS16203_YINCL_OUT },
+ [temp] = { ADIS16203_TEMP_OUT }
+};
-static IIO_DEV_ATTR_TEMP_RAW(adis16203_read_temp);
-static IIO_CONST_ATTR(temp_offset, "25");
-static IIO_CONST_ATTR(temp_scale, "-0.47");
+static int adis16203_write_raw(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ int val,
+ int val2,
+ long mask)
+{
+ /* currently only one writable parameter which keeps this simple */
+ u8 addr = adis16203_addresses[chan->address][1];
+ return adis16203_spi_write_reg_16(indio_dev, addr, val & 0x3FFF);
+}
+
+static int adis16203_read_raw(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ int *val, int *val2,
+ long mask)
+{
+ int ret;
+ int bits;
+ u8 addr;
+ s16 val16;
+ switch (mask) {
+ case 0:
+ mutex_lock(&indio_dev->mlock);
+ addr = adis16203_addresses[chan->address][0];
+ ret = adis16203_spi_read_reg_16(indio_dev, addr, &val16);
+ if (ret)
+ return ret;
+
+ if (val16 & ADIS16203_ERROR_ACTIVE) {
+ ret = adis16203_check_status(indio_dev);
+ if (ret)
+ return ret;
+ }
+ val16 = val16 & ((1 << chan->scan_type.realbits) - 1);
+ if (chan->scan_type.sign == 's')
+ val16 = (s16)(val16 <<
+ (16 - chan->scan_type.realbits)) >>
+ (16 - chan->scan_type.realbits);
+ *val = val16;
+ mutex_unlock(&indio_dev->mlock);
+ return IIO_VAL_INT;
+ case (1 << IIO_CHAN_INFO_SCALE_SEPARATE):
+ case (1 << IIO_CHAN_INFO_SCALE_SHARED):
+ switch (chan->type) {
+ case IIO_IN:
+ *val = 0;
+ if (chan->channel == 0)
+ *val2 = 1220;
+ else
+ *val2 = 610;
+ return IIO_VAL_INT_PLUS_MICRO;
+ case IIO_TEMP:
+ *val = 0;
+ *val2 = -470000;
+ return IIO_VAL_INT_PLUS_MICRO;
+ case IIO_INCLI:
+ *val = 0;
+ *val2 = 25000;
+ return IIO_VAL_INT_PLUS_MICRO;
+ default:
+ return -EINVAL;
+ }
+ case (1 << IIO_CHAN_INFO_OFFSET_SEPARATE):
+ *val = 25;
+ return IIO_VAL_INT;
+ case (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE):
+ bits = 14;
+ mutex_lock(&indio_dev->mlock);
+ addr = adis16203_addresses[chan->address][1];
+ ret = adis16203_spi_read_reg_16(indio_dev, addr, &val16);
+ if (ret) {
+ mutex_unlock(&indio_dev->mlock);
+ return ret;
+ }
+ val16 &= (1 << bits) - 1;
+ val16 = (s16)(val16 << (16 - bits)) >> (16 - bits);
+ *val = val16;
+ mutex_unlock(&indio_dev->mlock);
+ return IIO_VAL_INT;
+ default:
+ return -EINVAL;
+ }
+}
+
+static struct iio_chan_spec adis16203_channels[] = {
+ IIO_CHAN(IIO_IN, 0, 1, 0, "supply", 0, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SEPARATE),
+ in_supply, ADIS16203_SCAN_SUPPLY,
+ IIO_ST('u', 12, 16, 0), 0),
+ IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 1, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SEPARATE),
+ in_aux, ADIS16203_SCAN_AUX_ADC,
+ IIO_ST('u', 12, 16, 0), 0),
+ IIO_CHAN(IIO_INCLI, 1, 0, 0, NULL, 0, IIO_MOD_X,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED) |
+ (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE),
+ incli_x, ADIS16203_SCAN_INCLI_X,
+ IIO_ST('s', 14, 16, 0), 0),
+ /* Fixme: Not what it appears to be - see data sheet */
+ IIO_CHAN(IIO_INCLI, 1, 0, 0, NULL, 0, IIO_MOD_Y,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ incli_y, ADIS16203_SCAN_INCLI_Y,
+ IIO_ST('s', 14, 16, 0), 0),
+ IIO_CHAN(IIO_TEMP, 0, 1, 0, NULL, 0, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SEPARATE) |
+ (1 << IIO_CHAN_INFO_OFFSET_SEPARATE),
+ temp, ADIS16203_SCAN_TEMP,
+ IIO_ST('u', 12, 16, 0), 0),
+ IIO_CHAN_SOFT_TIMESTAMP(5),
+};
static IIO_DEVICE_ATTR(reset, S_IWUSR, NULL, adis16203_write_reset, 0);
-static IIO_CONST_ATTR(name, "adis16203");
-
-static struct attribute *adis16203_event_attributes[] = {
- NULL
-};
-
-static struct attribute_group adis16203_event_attribute_group = {
- .attrs = adis16203_event_attributes,
-};
-
static struct attribute *adis16203_attributes[] = {
- &iio_dev_attr_in0_supply_raw.dev_attr.attr,
- &iio_const_attr_in0_supply_scale.dev_attr.attr,
- &iio_dev_attr_temp_raw.dev_attr.attr,
- &iio_const_attr_temp_offset.dev_attr.attr,
- &iio_const_attr_temp_scale.dev_attr.attr,
&iio_dev_attr_reset.dev_attr.attr,
- &iio_const_attr_name.dev_attr.attr,
- &iio_dev_attr_in1_raw.dev_attr.attr,
- &iio_const_attr_in1_scale.dev_attr.attr,
- &iio_dev_attr_incli_x_raw.dev_attr.attr,
- &iio_dev_attr_incli_y_raw.dev_attr.attr,
- &iio_dev_attr_incli_x_offset.dev_attr.attr,
- &iio_const_attr_incli_scale.dev_attr.attr,
NULL
};
@@ -423,6 +408,13 @@
.attrs = adis16203_attributes,
};
+static const struct iio_info adis16203_info = {
+ .attrs = &adis16203_attribute_group,
+ .read_raw = &adis16203_read_raw,
+ .write_raw = &adis16203_write_raw,
+ .driver_module = THIS_MODULE,
+};
+
static int __devinit adis16203_probe(struct spi_device *spi)
{
int ret, regdone = 0;
@@ -448,18 +440,17 @@
st->us = spi;
mutex_init(&st->buf_lock);
/* setup the industrialio driver allocated elements */
- st->indio_dev = iio_allocate_device();
+ st->indio_dev = iio_allocate_device(0);
if (st->indio_dev == NULL) {
ret = -ENOMEM;
goto error_free_tx;
}
-
+ st->indio_dev->name = spi->dev.driver->name;
st->indio_dev->dev.parent = &spi->dev;
- st->indio_dev->num_interrupt_lines = 1;
- st->indio_dev->event_attrs = &adis16203_event_attribute_group;
- st->indio_dev->attrs = &adis16203_attribute_group;
+ st->indio_dev->channels = adis16203_channels;
+ st->indio_dev->num_channels = ARRAY_SIZE(adis16203_channels);
+ st->indio_dev->info = &adis16203_info;
st->indio_dev->dev_data = (void *)(st);
- st->indio_dev->driver_module = THIS_MODULE;
st->indio_dev->modes = INDIO_DIRECT_MODE;
ret = adis16203_configure_ring(st->indio_dev);
@@ -471,39 +462,30 @@
goto error_unreg_ring_funcs;
regdone = 1;
- ret = adis16203_initialize_ring(st->indio_dev->ring);
+ ret = iio_ring_buffer_register_ex(st->indio_dev->ring, 0,
+ adis16203_channels,
+ ARRAY_SIZE(adis16203_channels));
if (ret) {
printk(KERN_ERR "failed to initialize the ring\n");
goto error_unreg_ring_funcs;
}
if (spi->irq) {
- ret = iio_register_interrupt_line(spi->irq,
- st->indio_dev,
- 0,
- IRQF_TRIGGER_RISING,
- "adis16203");
- if (ret)
- goto error_uninitialize_ring;
-
ret = adis16203_probe_trigger(st->indio_dev);
if (ret)
- goto error_unregister_line;
+ goto error_uninitialize_ring;
}
/* Get the device into a sane initial state */
- ret = adis16203_initial_setup(st);
+ ret = adis16203_initial_setup(st->indio_dev);
if (ret)
goto error_remove_trigger;
return 0;
error_remove_trigger:
adis16203_remove_trigger(st->indio_dev);
-error_unregister_line:
- if (spi->irq)
- iio_unregister_interrupt_line(st->indio_dev, 0);
error_uninitialize_ring:
- adis16203_uninitialize_ring(st->indio_dev->ring);
+ iio_ring_buffer_unregister(st->indio_dev->ring);
error_unreg_ring_funcs:
adis16203_unconfigure_ring(st->indio_dev);
error_free_dev:
@@ -526,13 +508,8 @@
struct adis16203_state *st = spi_get_drvdata(spi);
struct iio_dev *indio_dev = st->indio_dev;
- flush_scheduled_work();
-
adis16203_remove_trigger(indio_dev);
- if (spi->irq)
- iio_unregister_interrupt_line(indio_dev, 0);
-
- adis16203_uninitialize_ring(indio_dev->ring);
+ iio_ring_buffer_unregister(indio_dev->ring);
iio_device_unregister(indio_dev);
adis16203_unconfigure_ring(indio_dev);
kfree(st->tx);
diff --git a/drivers/staging/iio/accel/adis16203_ring.c b/drivers/staging/iio/accel/adis16203_ring.c
index 3d774f7..a9a789d 100644
--- a/drivers/staging/iio/accel/adis16203_ring.c
+++ b/drivers/staging/iio/accel/adis16203_ring.c
@@ -17,57 +17,6 @@
#include "../trigger.h"
#include "adis16203.h"
-static IIO_SCAN_EL_C(in_supply, ADIS16203_SCAN_SUPPLY, ADIS16203_SUPPLY_OUT, NULL);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(in_supply, u, 12, 16);
-static IIO_SCAN_EL_C(in0, ADIS16203_SCAN_AUX_ADC, ADIS16203_AUX_ADC, NULL);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(in0, u, 12, 16);
-static IIO_SCAN_EL_C(temp, ADIS16203_SCAN_TEMP, ADIS16203_TEMP_OUT, NULL);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(temp, u, 12, 16);
-static IIO_SCAN_EL_C(incli_x, ADIS16203_SCAN_INCLI_X,
- ADIS16203_XINCL_OUT, NULL);
-static IIO_SCAN_EL_C(incli_y, ADIS16203_SCAN_INCLI_Y,
- ADIS16203_YINCL_OUT, NULL);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(incli, s, 14, 16);
-static IIO_SCAN_EL_TIMESTAMP(5);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(timestamp, s, 64, 64);
-
-static struct attribute *adis16203_scan_el_attrs[] = {
- &iio_scan_el_in_supply.dev_attr.attr,
- &iio_const_attr_in_supply_index.dev_attr.attr,
- &iio_const_attr_in_supply_type.dev_attr.attr,
- &iio_scan_el_in0.dev_attr.attr,
- &iio_const_attr_in0_index.dev_attr.attr,
- &iio_const_attr_in0_type.dev_attr.attr,
- &iio_scan_el_temp.dev_attr.attr,
- &iio_const_attr_temp_index.dev_attr.attr,
- &iio_const_attr_temp_type.dev_attr.attr,
- &iio_scan_el_incli_x.dev_attr.attr,
- &iio_const_attr_incli_x_index.dev_attr.attr,
- &iio_scan_el_incli_y.dev_attr.attr,
- &iio_const_attr_incli_y_index.dev_attr.attr,
- &iio_const_attr_incli_type.dev_attr.attr,
- &iio_scan_el_timestamp.dev_attr.attr,
- &iio_const_attr_timestamp_index.dev_attr.attr,
- &iio_const_attr_timestamp_type.dev_attr.attr,
- NULL,
-};
-
-static struct attribute_group adis16203_scan_el_group = {
- .attrs = adis16203_scan_el_attrs,
- .name = "scan_elements",
-};
-
-/**
- * adis16203_poll_func_th() top half interrupt handler called by trigger
- * @private_data: iio_dev
- **/
-static void adis16203_poll_func_th(struct iio_dev *indio_dev, s64 timestamp)
-{
- struct adis16203_state *st = iio_dev_get_devdata(indio_dev);
- st->last_timestamp = timestamp;
- schedule_work(&st->work_trigger_to_ring);
-}
-
/**
* adis16203_read_ring_data() read data registers which will be placed into ring
* @dev: device associated with child of actual device (iio_dev or iio_trig)
@@ -115,21 +64,21 @@
/* Whilst this makes a lot of calls to iio_sw_ring functions - it is to device
* specific to be rolled into the core.
*/
-static void adis16203_trigger_bh_to_ring(struct work_struct *work_s)
+static irqreturn_t adis16203_trigger_handler(int irq, void *p)
{
- struct adis16203_state *st
- = container_of(work_s, struct adis16203_state,
- work_trigger_to_ring);
- struct iio_ring_buffer *ring = st->indio_dev->ring;
+ struct iio_poll_func *pf = p;
+ struct iio_dev *indio_dev = pf->private_data;
+ struct adis16203_state *st = iio_dev_get_devdata(indio_dev);
+ struct iio_ring_buffer *ring = indio_dev->ring;
int i = 0;
s16 *data;
- size_t datasize = ring->access.get_bytes_per_datum(ring);
+ size_t datasize = ring->access->get_bytes_per_datum(ring);
data = kmalloc(datasize, GFP_KERNEL);
if (data == NULL) {
dev_err(&st->us->dev, "memory alloc failed in ring bh");
- return;
+ return -ENOMEM;
}
if (ring->scan_count)
@@ -140,30 +89,34 @@
/* Guaranteed to be aligned with 8 byte boundary */
if (ring->scan_timestamp)
- *((s64 *)(data + ((i + 3)/4)*4)) = st->last_timestamp;
+ *((s64 *)(data + ((i + 3)/4)*4)) = pf->timestamp;
- ring->access.store_to(ring,
+ ring->access->store_to(ring,
(u8 *)data,
- st->last_timestamp);
+ pf->timestamp);
iio_trigger_notify_done(st->indio_dev->trig);
kfree(data);
- return;
+ return IRQ_HANDLED;
}
void adis16203_unconfigure_ring(struct iio_dev *indio_dev)
{
- kfree(indio_dev->pollfunc);
+ iio_dealloc_pollfunc(indio_dev->pollfunc);
iio_sw_rb_free(indio_dev->ring);
}
+static const struct iio_ring_setup_ops adis16203_ring_setup_ops = {
+ .preenable = &iio_sw_ring_preenable,
+ .postenable = &iio_triggered_ring_postenable,
+ .predisable = &iio_triggered_ring_predisable,
+};
+
int adis16203_configure_ring(struct iio_dev *indio_dev)
{
int ret = 0;
- struct adis16203_state *st = indio_dev->dev_data;
struct iio_ring_buffer *ring;
- INIT_WORK(&st->work_trigger_to_ring, adis16203_trigger_bh_to_ring);
ring = iio_sw_rb_allocate(indio_dev);
if (!ring) {
@@ -172,25 +125,29 @@
}
indio_dev->ring = ring;
/* Effectively select the ring buffer implementation */
- iio_ring_sw_register_funcs(&ring->access);
ring->bpe = 2;
- ring->scan_el_attrs = &adis16203_scan_el_group;
ring->scan_timestamp = true;
- ring->preenable = &iio_sw_ring_preenable;
- ring->postenable = &iio_triggered_ring_postenable;
- ring->predisable = &iio_triggered_ring_predisable;
+ ring->access = &ring_sw_access_funcs;
+ ring->setup_ops = &adis16203_ring_setup_ops;
ring->owner = THIS_MODULE;
/* Set default scan mode */
- iio_scan_mask_set(ring, iio_scan_el_in_supply.number);
- iio_scan_mask_set(ring, iio_scan_el_temp.number);
- iio_scan_mask_set(ring, iio_scan_el_in0.number);
- iio_scan_mask_set(ring, iio_scan_el_incli_x.number);
- iio_scan_mask_set(ring, iio_scan_el_incli_y.number);
+ iio_scan_mask_set(ring, ADIS16203_SCAN_SUPPLY);
+ iio_scan_mask_set(ring, ADIS16203_SCAN_TEMP);
+ iio_scan_mask_set(ring, ADIS16203_SCAN_AUX_ADC);
+ iio_scan_mask_set(ring, ADIS16203_SCAN_INCLI_X);
+ iio_scan_mask_set(ring, ADIS16203_SCAN_INCLI_Y);
- ret = iio_alloc_pollfunc(indio_dev, NULL, &adis16203_poll_func_th);
- if (ret)
+ indio_dev->pollfunc = iio_alloc_pollfunc(&iio_pollfunc_store_time,
+ &adis16203_trigger_handler,
+ IRQF_ONESHOT,
+ indio_dev,
+ "adis16203_consumer%d",
+ indio_dev->id);
+ if (indio_dev->pollfunc == NULL) {
+ ret = -ENOMEM;
goto error_iio_sw_rb_free;
+ }
indio_dev->modes |= INDIO_RING_TRIGGERED;
return 0;
@@ -199,13 +156,3 @@
iio_sw_rb_free(indio_dev->ring);
return ret;
}
-
-int adis16203_initialize_ring(struct iio_ring_buffer *ring)
-{
- return iio_ring_buffer_register(ring, 0);
-}
-
-void adis16203_uninitialize_ring(struct iio_ring_buffer *ring)
-{
- iio_ring_buffer_unregister(ring);
-}
diff --git a/drivers/staging/iio/accel/adis16203_trigger.c b/drivers/staging/iio/accel/adis16203_trigger.c
index 50be51c..ca5db17 100644
--- a/drivers/staging/iio/accel/adis16203_trigger.c
+++ b/drivers/staging/iio/accel/adis16203_trigger.c
@@ -13,35 +13,6 @@
#include "adis16203.h"
/**
- * adis16203_data_rdy_trig_poll() the event handler for the data rdy trig
- **/
-static int adis16203_data_rdy_trig_poll(struct iio_dev *dev_info,
- int index,
- s64 timestamp,
- int no_test)
-{
- struct adis16203_state *st = iio_dev_get_devdata(dev_info);
- struct iio_trigger *trig = st->trig;
-
- iio_trigger_poll(trig, timestamp);
-
- return IRQ_HANDLED;
-}
-
-IIO_EVENT_SH(data_rdy_trig, &adis16203_data_rdy_trig_poll);
-
-static DEVICE_ATTR(name, S_IRUGO, iio_trigger_read_name, NULL);
-
-static struct attribute *adis16203_trigger_attrs[] = {
- &dev_attr_name.attr,
- NULL,
-};
-
-static const struct attribute_group adis16203_trigger_attr_group = {
- .attrs = adis16203_trigger_attrs,
-};
-
-/**
* adis16203_data_rdy_trigger_set_state() set datardy interrupt state
**/
static int adis16203_data_rdy_trigger_set_state(struct iio_trigger *trig,
@@ -49,31 +20,9 @@
{
struct adis16203_state *st = trig->private_data;
struct iio_dev *indio_dev = st->indio_dev;
- int ret = 0;
dev_dbg(&indio_dev->dev, "%s (%d)\n", __func__, state);
- ret = adis16203_set_irq(&st->indio_dev->dev, state);
- if (state == false) {
- iio_remove_event_from_list(&iio_event_data_rdy_trig,
- &indio_dev->interrupts[0]
- ->ev_list);
- flush_scheduled_work();
- } else {
- iio_add_event_to_list(&iio_event_data_rdy_trig,
- &indio_dev->interrupts[0]->ev_list);
- }
- return ret;
-}
-
-/**
- * adis16203_trig_try_reen() try renabling irq for data rdy trigger
- * @trig: the datardy trigger
- **/
-static int adis16203_trig_try_reen(struct iio_trigger *trig)
-{
- struct adis16203_state *st = trig->private_data;
- enable_irq(st->us->irq);
- return 0;
+ return adis16203_set_irq(st->indio_dev, state);
}
int adis16203_probe_trigger(struct iio_dev *indio_dev)
@@ -81,34 +30,38 @@
int ret;
struct adis16203_state *st = indio_dev->dev_data;
- st->trig = iio_allocate_trigger();
- st->trig->name = kasprintf(GFP_KERNEL,
- "adis16203-dev%d",
- indio_dev->id);
- if (!st->trig->name) {
+ st->trig = iio_allocate_trigger("adis16203-dev%d", indio_dev->id);
+ if (st->trig == NULL) {
ret = -ENOMEM;
- goto error_free_trig;
+ goto error_ret;
}
+
+ ret = request_irq(st->us->irq,
+ &iio_trigger_generic_data_rdy_poll,
+ IRQF_TRIGGER_RISING,
+ "adis16203",
+ st->trig);
+ if (ret)
+ goto error_free_trig;
+
st->trig->dev.parent = &st->us->dev;
st->trig->owner = THIS_MODULE;
st->trig->private_data = st;
st->trig->set_trigger_state = &adis16203_data_rdy_trigger_set_state;
- st->trig->try_reenable = &adis16203_trig_try_reen;
- st->trig->control_attrs = &adis16203_trigger_attr_group;
ret = iio_trigger_register(st->trig);
/* select default trigger */
indio_dev->trig = st->trig;
if (ret)
- goto error_free_trig_name;
+ goto error_free_irq;
return 0;
-error_free_trig_name:
- kfree(st->trig->name);
+error_free_irq:
+ free_irq(st->us->irq, st->trig);
error_free_trig:
iio_free_trigger(st->trig);
-
+error_ret:
return ret;
}
@@ -117,6 +70,6 @@
struct adis16203_state *state = indio_dev->dev_data;
iio_trigger_unregister(state->trig);
- kfree(state->trig->name);
+ free_irq(state->us->irq, state->trig);
iio_free_trigger(state->trig);
}
diff --git a/drivers/staging/iio/accel/adis16204.h b/drivers/staging/iio/accel/adis16204.h
index e6184468..5310a42 100644
--- a/drivers/staging/iio/accel/adis16204.h
+++ b/drivers/staging/iio/accel/adis16204.h
@@ -67,9 +67,6 @@
/**
* struct adis16204_state - device instance specific data
* @us: actual spi_device
- * @work_trigger_to_ring: bh for triggered event handling
- * @inter: used to check if new interrupt has been triggered
- * @last_timestamp: passing timestamp from th to bh of interrupt handler
* @indio_dev: industrial I/O device structure
* @trig: data ready trigger registered with iio
* @tx: transmit buffer
@@ -78,8 +75,6 @@
**/
struct adis16204_state {
struct spi_device *us;
- struct work_struct work_trigger_to_ring;
- s64 last_timestamp;
struct iio_dev *indio_dev;
struct iio_trigger *trig;
u8 *tx;
@@ -87,7 +82,7 @@
struct mutex buf_lock;
};
-int adis16204_set_irq(struct device *dev, bool enable);
+int adis16204_set_irq(struct iio_dev *indio_dev, bool enable);
#ifdef CONFIG_IIO_RING_BUFFER
enum adis16204_scan {
@@ -108,8 +103,6 @@
int adis16204_configure_ring(struct iio_dev *indio_dev);
void adis16204_unconfigure_ring(struct iio_dev *indio_dev);
-int adis16204_initialize_ring(struct iio_ring_buffer *ring);
-void adis16204_uninitialize_ring(struct iio_ring_buffer *ring);
#else /* CONFIG_IIO_RING_BUFFER */
static inline void adis16204_remove_trigger(struct iio_dev *indio_dev)
@@ -138,14 +131,5 @@
{
}
-static inline int adis16204_initialize_ring(struct iio_ring_buffer *ring)
-{
- return 0;
-}
-
-static inline void adis16204_uninitialize_ring(struct iio_ring_buffer *ring)
-{
-}
-
#endif /* CONFIG_IIO_RING_BUFFER */
#endif /* SPI_ADIS16204_H_ */
diff --git a/drivers/staging/iio/accel/adis16204_core.c b/drivers/staging/iio/accel/adis16204_core.c
index cc15e40..1680670 100644
--- a/drivers/staging/iio/accel/adis16204_core.c
+++ b/drivers/staging/iio/accel/adis16204_core.c
@@ -20,28 +20,25 @@
#include "../iio.h"
#include "../sysfs.h"
+#include "../ring_generic.h"
#include "accel.h"
-#include "../gyro/gyro.h"
#include "../adc/adc.h"
#include "adis16204.h"
#define DRIVER_NAME "adis16204"
-static int adis16204_check_status(struct device *dev);
-
/**
* adis16204_spi_write_reg_8() - write single byte to a register
* @dev: device associated with child of actual device (iio_dev or iio_trig)
* @reg_address: the address of the register to be written
* @val: the value to write
**/
-static int adis16204_spi_write_reg_8(struct device *dev,
+static int adis16204_spi_write_reg_8(struct iio_dev *indio_dev,
u8 reg_address,
u8 val)
{
int ret;
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct adis16204_state *st = iio_dev_get_devdata(indio_dev);
mutex_lock(&st->buf_lock);
@@ -56,18 +53,17 @@
/**
* adis16204_spi_write_reg_16() - write 2 bytes to a pair of registers
- * @dev: device associated with child of actual device (iio_dev or iio_trig)
+ * @indio_dev: iio device associated with child of actual device
* @reg_address: the address of the lower of the two registers. Second register
* is assumed to have address one greater.
* @val: value to be written
**/
-static int adis16204_spi_write_reg_16(struct device *dev,
+static int adis16204_spi_write_reg_16(struct iio_dev *indio_dev,
u8 lower_reg_address,
u16 value)
{
int ret;
struct spi_message msg;
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct adis16204_state *st = iio_dev_get_devdata(indio_dev);
struct spi_transfer xfers[] = {
{
@@ -100,17 +96,16 @@
/**
* adis16204_spi_read_reg_16() - read 2 bytes from a 16-bit register
- * @dev: device associated with child of actual device (iio_dev or iio_trig)
+ * @indio_dev: iio device associated with child of actual device
* @reg_address: the address of the lower of the two registers. Second register
* is assumed to have address one greater.
* @val: somewhere to pass back the value read
**/
-static int adis16204_spi_read_reg_16(struct device *dev,
- u8 lower_reg_address,
- u16 *val)
+static int adis16204_spi_read_reg_16(struct iio_dev *indio_dev,
+ u8 lower_reg_address,
+ u16 *val)
{
struct spi_message msg;
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct adis16204_state *st = iio_dev_get_devdata(indio_dev);
int ret;
struct spi_transfer xfers[] = {
@@ -124,7 +119,6 @@
.rx_buf = st->rx,
.bits_per_word = 8,
.len = 2,
- .cs_change = 1,
.delay_usecs = 20,
},
};
@@ -149,72 +143,31 @@
return ret;
}
-static ssize_t adis16204_read_12bit_unsigned(struct device *dev,
- struct device_attribute *attr,
- char *buf)
+static int adis16204_check_status(struct iio_dev *indio_dev)
{
+ u16 status;
int ret;
- u16 val = 0;
- struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
- ret = adis16204_spi_read_reg_16(dev, this_attr->address, &val);
- if (ret)
- return ret;
-
- if (val & ADIS16204_ERROR_ACTIVE)
- adis16204_check_status(dev);
-
- return sprintf(buf, "%u\n", val & 0x0FFF);
-}
-
-static ssize_t adis16204_read_temp(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
- ssize_t ret;
- u16 val;
-
- /* Take the iio_dev status lock */
- mutex_lock(&indio_dev->mlock);
-
- ret = adis16204_spi_read_reg_16(dev, ADIS16204_TEMP_OUT, (u16 *)&val);
- if (ret)
+ ret = adis16204_spi_read_reg_16(indio_dev,
+ ADIS16204_DIAG_STAT, &status);
+ if (ret < 0) {
+ dev_err(&indio_dev->dev, "Reading status failed\n");
goto error_ret;
+ }
+ ret = status & 0x1F;
- if (val & ADIS16204_ERROR_ACTIVE)
- adis16204_check_status(dev);
-
- val &= 0xFFF;
- ret = sprintf(buf, "%d\n", val);
+ if (status & ADIS16204_DIAG_STAT_SELFTEST_FAIL)
+ dev_err(&indio_dev->dev, "Self test failure\n");
+ if (status & ADIS16204_DIAG_STAT_SPI_FAIL)
+ dev_err(&indio_dev->dev, "SPI failure\n");
+ if (status & ADIS16204_DIAG_STAT_FLASH_UPT)
+ dev_err(&indio_dev->dev, "Flash update failed\n");
+ if (status & ADIS16204_DIAG_STAT_POWER_HIGH)
+ dev_err(&indio_dev->dev, "Power supply above 3.625V\n");
+ if (status & ADIS16204_DIAG_STAT_POWER_LOW)
+ dev_err(&indio_dev->dev, "Power supply below 2.975V\n");
error_ret:
- mutex_unlock(&indio_dev->mlock);
- return ret;
-}
-
-static ssize_t adis16204_read_12bit_signed(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
- struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
- s16 val = 0;
- ssize_t ret;
-
- mutex_lock(&indio_dev->mlock);
-
- ret = adis16204_spi_read_reg_16(dev, this_attr->address, (u16 *)&val);
- if (!ret) {
- if (val & ADIS16204_ERROR_ACTIVE)
- adis16204_check_status(dev);
-
- val = ((s16)(val << 4) >> 4);
- ret = sprintf(buf, "%d\n", val);
- }
-
- mutex_unlock(&indio_dev->mlock);
-
return ret;
}
@@ -229,10 +182,11 @@
mutex_lock(&indio_dev->mlock);
- ret = adis16204_spi_read_reg_16(dev, this_attr->address, (u16 *)&val);
+ ret = adis16204_spi_read_reg_16(indio_dev,
+ this_attr->address, (u16 *)&val);
if (!ret) {
if (val & ADIS16204_ERROR_ACTIVE)
- adis16204_check_status(dev);
+ adis16204_check_status(indio_dev);
val = ((s16)(val << 2) >> 2);
ret = sprintf(buf, "%d\n", val);
@@ -243,32 +197,14 @@
return ret;
}
-static ssize_t adis16204_write_16bit(struct device *dev,
- struct device_attribute *attr,
- const char *buf,
- size_t len)
-{
- struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
- int ret;
- long val;
-
- ret = strict_strtol(buf, 10, &val);
- if (ret)
- goto error_ret;
- ret = adis16204_spi_write_reg_16(dev, this_attr->address, val);
-
-error_ret:
- return ret ? ret : len;
-}
-
-static int adis16204_reset(struct device *dev)
+static int adis16204_reset(struct iio_dev *indio_dev)
{
int ret;
- ret = adis16204_spi_write_reg_8(dev,
+ ret = adis16204_spi_write_reg_8(indio_dev,
ADIS16204_GLOB_CMD,
ADIS16204_GLOB_CMD_SW_RESET);
if (ret)
- dev_err(dev, "problem resetting device");
+ dev_err(&indio_dev->dev, "problem resetting device");
return ret;
}
@@ -277,23 +213,25 @@
struct device_attribute *attr,
const char *buf, size_t len)
{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+
if (len < 1)
return -EINVAL;
switch (buf[0]) {
case '1':
case 'y':
case 'Y':
- return adis16204_reset(dev);
+ return adis16204_reset(indio_dev);
}
return -EINVAL;
}
-int adis16204_set_irq(struct device *dev, bool enable)
+int adis16204_set_irq(struct iio_dev *indio_dev, bool enable)
{
int ret = 0;
u16 msc;
- ret = adis16204_spi_read_reg_16(dev, ADIS16204_MSC_CTRL, &msc);
+ ret = adis16204_spi_read_reg_16(indio_dev, ADIS16204_MSC_CTRL, &msc);
if (ret)
goto error_ret;
@@ -304,106 +242,63 @@
else
msc &= ~ADIS16204_MSC_CTRL_DATA_RDY_EN;
- ret = adis16204_spi_write_reg_16(dev, ADIS16204_MSC_CTRL, msc);
+ ret = adis16204_spi_write_reg_16(indio_dev, ADIS16204_MSC_CTRL, msc);
error_ret:
return ret;
}
-static int adis16204_check_status(struct device *dev)
-{
- u16 status;
- int ret;
-
- ret = adis16204_spi_read_reg_16(dev, ADIS16204_DIAG_STAT, &status);
- if (ret < 0) {
- dev_err(dev, "Reading status failed\n");
- goto error_ret;
- }
- ret = status & 0x1F;
-
- if (status & ADIS16204_DIAG_STAT_SELFTEST_FAIL)
- dev_err(dev, "Self test failure\n");
- if (status & ADIS16204_DIAG_STAT_SPI_FAIL)
- dev_err(dev, "SPI failure\n");
- if (status & ADIS16204_DIAG_STAT_FLASH_UPT)
- dev_err(dev, "Flash update failed\n");
- if (status & ADIS16204_DIAG_STAT_POWER_HIGH)
- dev_err(dev, "Power supply above 3.625V\n");
- if (status & ADIS16204_DIAG_STAT_POWER_LOW)
- dev_err(dev, "Power supply below 2.975V\n");
-
-error_ret:
- return ret;
-}
-
-static int adis16204_self_test(struct device *dev)
+static int adis16204_self_test(struct iio_dev *indio_dev)
{
int ret;
- ret = adis16204_spi_write_reg_16(dev,
+ ret = adis16204_spi_write_reg_16(indio_dev,
ADIS16204_MSC_CTRL,
ADIS16204_MSC_CTRL_SELF_TEST_EN);
if (ret) {
- dev_err(dev, "problem starting self test");
+ dev_err(&indio_dev->dev, "problem starting self test");
goto err_ret;
}
- adis16204_check_status(dev);
+ adis16204_check_status(indio_dev);
err_ret:
return ret;
}
-static int adis16204_initial_setup(struct adis16204_state *st)
+static int adis16204_initial_setup(struct iio_dev *indio_dev)
{
int ret;
- struct device *dev = &st->indio_dev->dev;
/* Disable IRQ */
- ret = adis16204_set_irq(dev, false);
+ ret = adis16204_set_irq(indio_dev, false);
if (ret) {
- dev_err(dev, "disable irq failed");
+ dev_err(&indio_dev->dev, "disable irq failed");
goto err_ret;
}
/* Do self test */
- ret = adis16204_self_test(dev);
+ ret = adis16204_self_test(indio_dev);
if (ret) {
- dev_err(dev, "self test failure");
+ dev_err(&indio_dev->dev, "self test failure");
goto err_ret;
}
/* Read status register to check the result */
- ret = adis16204_check_status(dev);
+ ret = adis16204_check_status(indio_dev);
if (ret) {
- adis16204_reset(dev);
- dev_err(dev, "device not playing ball -> reset");
+ adis16204_reset(indio_dev);
+ dev_err(&indio_dev->dev, "device not playing ball -> reset");
msleep(ADIS16204_STARTUP_DELAY);
- ret = adis16204_check_status(dev);
+ ret = adis16204_check_status(indio_dev);
if (ret) {
- dev_err(dev, "giving up");
+ dev_err(&indio_dev->dev, "giving up");
goto err_ret;
}
}
- printk(KERN_INFO DRIVER_NAME ": at CS%d (irq %d)\n",
- st->us->chip_select, st->us->irq);
-
err_ret:
return ret;
}
-
-static IIO_DEV_ATTR_IN_NAMED_RAW(0, supply, adis16204_read_12bit_unsigned,
- ADIS16204_SUPPLY_OUT);
-static IIO_CONST_ATTR(in0_supply_scale, "0.00122");
-static IIO_DEV_ATTR_IN_RAW(1, adis16204_read_12bit_unsigned,
- ADIS16204_AUX_ADC);
-static IIO_CONST_ATTR(in1_scale, "0.00061");
-
-static IIO_DEV_ATTR_ACCEL_X(adis16204_read_14bit_signed,
- ADIS16204_XACCL_OUT);
-static IIO_DEV_ATTR_ACCEL_Y(adis16204_read_14bit_signed,
- ADIS16204_YACCL_OUT);
static IIO_DEV_ATTR_ACCEL_XY(adis16204_read_14bit_signed,
ADIS16204_XY_RSS_OUT);
static IIO_DEV_ATTR_ACCEL_XPEAK(adis16204_read_14bit_signed,
@@ -412,54 +307,164 @@
ADIS16204_Y_PEAK_OUT);
static IIO_DEV_ATTR_ACCEL_XYPEAK(adis16204_read_14bit_signed,
ADIS16204_XY_PEAK_OUT);
-static IIO_DEV_ATTR_ACCEL_X_OFFSET(S_IWUSR | S_IRUGO,
- adis16204_read_12bit_signed,
- adis16204_write_16bit,
- ADIS16204_XACCL_NULL);
-static IIO_DEV_ATTR_ACCEL_Y_OFFSET(S_IWUSR | S_IRUGO,
- adis16204_read_12bit_signed,
- adis16204_write_16bit,
- ADIS16204_YACCL_NULL);
-static IIO_CONST_ATTR(accel_x_scale, "0.017125");
-static IIO_CONST_ATTR(accel_y_scale, "0.008407");
static IIO_CONST_ATTR(accel_xy_scale, "0.017125");
-static IIO_DEV_ATTR_TEMP_RAW(adis16204_read_temp);
-static IIO_CONST_ATTR(temp_offset, "25");
-static IIO_CONST_ATTR(temp_scale, "-0.47");
-
static IIO_DEVICE_ATTR(reset, S_IWUSR, NULL, adis16204_write_reset, 0);
-static IIO_CONST_ATTR(name, "adis16204");
-
-static struct attribute *adis16204_event_attributes[] = {
- NULL
+enum adis16204_channel {
+ in_supply,
+ in_aux,
+ temp,
+ accel_x,
+ accel_y,
};
-static struct attribute_group adis16204_event_attribute_group = {
- .attrs = adis16204_event_attributes,
+static u8 adis16204_addresses[5][2] = {
+ [in_supply] = { ADIS16204_SUPPLY_OUT },
+ [in_aux] = { ADIS16204_AUX_ADC },
+ [temp] = { ADIS16204_TEMP_OUT },
+ [accel_x] = { ADIS16204_XACCL_OUT, ADIS16204_XACCL_NULL },
+ [accel_y] = { ADIS16204_XACCL_OUT, ADIS16204_YACCL_NULL },
};
+static int adis16204_read_raw(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ int *val, int *val2,
+ long mask)
+{
+ int ret;
+ int bits;
+ u8 addr;
+ s16 val16;
+ switch (mask) {
+ case 0:
+ mutex_lock(&indio_dev->mlock);
+ addr = adis16204_addresses[chan->address][0];
+ ret = adis16204_spi_read_reg_16(indio_dev, addr, &val16);
+ if (ret)
+ return ret;
+
+ if (val16 & ADIS16204_ERROR_ACTIVE) {
+ ret = adis16204_check_status(indio_dev);
+ if (ret)
+ return ret;
+ }
+ val16 = val16 & ((1 << chan->scan_type.realbits) - 1);
+ if (chan->scan_type.sign == 's')
+ val16 = (s16)(val16 <<
+ (16 - chan->scan_type.realbits)) >>
+ (16 - chan->scan_type.realbits);
+ *val = val16;
+ mutex_unlock(&indio_dev->mlock);
+ return IIO_VAL_INT;
+ case (1 << IIO_CHAN_INFO_SCALE_SEPARATE):
+ switch (chan->type) {
+ case IIO_IN:
+ *val = 0;
+ if (chan->channel == 0)
+ *val2 = 1220;
+ else
+ *val2 = 610;
+ return IIO_VAL_INT_PLUS_MICRO;
+ case IIO_TEMP:
+ *val = 0;
+ *val2 = -470000;
+ return IIO_VAL_INT_PLUS_MICRO;
+ case IIO_ACCEL:
+ *val = 0;
+ if (chan->channel == 'x')
+ *val2 = 17125;
+ else
+ *val2 = 8407;
+ return IIO_VAL_INT_PLUS_MICRO;
+ default:
+ return -EINVAL;
+ }
+ break;
+ case (1 << IIO_CHAN_INFO_OFFSET_SEPARATE):
+ *val = 25;
+ return IIO_VAL_INT;
+ case (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE):
+ switch (chan->type) {
+ case IIO_ACCEL:
+ bits = 12;
+ break;
+ default:
+ return -EINVAL;
+ };
+ mutex_lock(&indio_dev->mlock);
+ addr = adis16204_addresses[chan->address][1];
+ ret = adis16204_spi_read_reg_16(indio_dev, addr, &val16);
+ if (ret) {
+ mutex_unlock(&indio_dev->mlock);
+ return ret;
+ }
+ val16 &= (1 << bits) - 1;
+ val16 = (s16)(val16 << (16 - bits)) >> (16 - bits);
+ *val = val16;
+ mutex_unlock(&indio_dev->mlock);
+ return IIO_VAL_INT;
+ }
+ return -EINVAL;
+}
+
+static int adis16204_write_raw(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ int val,
+ int val2,
+ long mask)
+{
+ int bits;
+ s16 val16;
+ u8 addr;
+ switch (mask) {
+ case (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE):
+ switch (chan->type) {
+ case IIO_ACCEL:
+ bits = 12;
+ break;
+ default:
+ return -EINVAL;
+ };
+ val16 = val & ((1 << bits) - 1);
+ addr = adis16204_addresses[chan->address][1];
+ return adis16204_spi_write_reg_16(indio_dev, addr, val16);
+ }
+ return -EINVAL;
+}
+
+static struct iio_chan_spec adis16204_channels[] = {
+ IIO_CHAN(IIO_IN, 0, 0, 0, "supply", 0, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SEPARATE),
+ in_supply, ADIS16204_SCAN_SUPPLY,
+ IIO_ST('u', 12, 16, 0), 0),
+ IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 1, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SEPARATE),
+ in_aux, ADIS16204_SCAN_AUX_ADC,
+ IIO_ST('u', 12, 16, 0), 0),
+ IIO_CHAN(IIO_TEMP, 0, 1, 0, NULL, 0, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SEPARATE) |
+ (1 << IIO_CHAN_INFO_OFFSET_SEPARATE),
+ temp, ADIS16204_SCAN_TEMP,
+ IIO_ST('u', 12, 16, 0), 0),
+ IIO_CHAN(IIO_ACCEL, 1, 0, 0, NULL, 0, IIO_MOD_X,
+ (1 << IIO_CHAN_INFO_SCALE_SEPARATE) |
+ (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE),
+ accel_x, ADIS16204_SCAN_ACC_X,
+ IIO_ST('s', 14, 16, 0), 0),
+ IIO_CHAN(IIO_ACCEL, 1, 0, 0, NULL, 0, IIO_MOD_Y,
+ (1 << IIO_CHAN_INFO_SCALE_SEPARATE) |
+ (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE),
+ accel_y, ADIS16204_SCAN_ACC_Y,
+ IIO_ST('s', 14, 16, 0), 0),
+ IIO_CHAN_SOFT_TIMESTAMP(5),
+};
static struct attribute *adis16204_attributes[] = {
- &iio_dev_attr_in0_supply_raw.dev_attr.attr,
- &iio_const_attr_in0_supply_scale.dev_attr.attr,
- &iio_dev_attr_temp_raw.dev_attr.attr,
- &iio_const_attr_temp_offset.dev_attr.attr,
- &iio_const_attr_temp_scale.dev_attr.attr,
&iio_dev_attr_reset.dev_attr.attr,
- &iio_const_attr_name.dev_attr.attr,
- &iio_dev_attr_in1_raw.dev_attr.attr,
- &iio_const_attr_in1_scale.dev_attr.attr,
- &iio_dev_attr_accel_x_raw.dev_attr.attr,
- &iio_dev_attr_accel_y_raw.dev_attr.attr,
&iio_dev_attr_accel_xy.dev_attr.attr,
&iio_dev_attr_accel_xpeak.dev_attr.attr,
&iio_dev_attr_accel_ypeak.dev_attr.attr,
&iio_dev_attr_accel_xypeak.dev_attr.attr,
- &iio_dev_attr_accel_x_offset.dev_attr.attr,
- &iio_dev_attr_accel_y_offset.dev_attr.attr,
- &iio_const_attr_accel_x_scale.dev_attr.attr,
- &iio_const_attr_accel_y_scale.dev_attr.attr,
&iio_const_attr_accel_xy_scale.dev_attr.attr,
NULL
};
@@ -468,6 +473,13 @@
.attrs = adis16204_attributes,
};
+static const struct iio_info adis16204_info = {
+ .attrs = &adis16204_attribute_group,
+ .read_raw = &adis16204_read_raw,
+ .write_raw = &adis16204_write_raw,
+ .driver_module = THIS_MODULE,
+};
+
static int __devinit adis16204_probe(struct spi_device *spi)
{
int ret, regdone = 0;
@@ -493,18 +505,18 @@
st->us = spi;
mutex_init(&st->buf_lock);
/* setup the industrialio driver allocated elements */
- st->indio_dev = iio_allocate_device();
+ st->indio_dev = iio_allocate_device(0);
if (st->indio_dev == NULL) {
ret = -ENOMEM;
goto error_free_tx;
}
+ st->indio_dev->name = spi->dev.driver->name;
st->indio_dev->dev.parent = &spi->dev;
- st->indio_dev->num_interrupt_lines = 1;
- st->indio_dev->event_attrs = &adis16204_event_attribute_group;
- st->indio_dev->attrs = &adis16204_attribute_group;
+ st->indio_dev->info = &adis16204_info;
+ st->indio_dev->channels = adis16204_channels;
+ st->indio_dev->num_channels = ARRAY_SIZE(adis16204_channels);
st->indio_dev->dev_data = (void *)(st);
- st->indio_dev->driver_module = THIS_MODULE;
st->indio_dev->modes = INDIO_DIRECT_MODE;
ret = adis16204_configure_ring(st->indio_dev);
@@ -516,39 +528,30 @@
goto error_unreg_ring_funcs;
regdone = 1;
- ret = adis16204_initialize_ring(st->indio_dev->ring);
+ ret = iio_ring_buffer_register_ex(st->indio_dev->ring, 0,
+ adis16204_channels,
+ ARRAY_SIZE(adis16204_channels));
if (ret) {
printk(KERN_ERR "failed to initialize the ring\n");
goto error_unreg_ring_funcs;
}
if (spi->irq) {
- ret = iio_register_interrupt_line(spi->irq,
- st->indio_dev,
- 0,
- IRQF_TRIGGER_RISING,
- "adis16204");
- if (ret)
- goto error_uninitialize_ring;
-
ret = adis16204_probe_trigger(st->indio_dev);
if (ret)
- goto error_unregister_line;
+ goto error_uninitialize_ring;
}
/* Get the device into a sane initial state */
- ret = adis16204_initial_setup(st);
+ ret = adis16204_initial_setup(st->indio_dev);
if (ret)
goto error_remove_trigger;
return 0;
error_remove_trigger:
adis16204_remove_trigger(st->indio_dev);
-error_unregister_line:
- if (spi->irq)
- iio_unregister_interrupt_line(st->indio_dev, 0);
error_uninitialize_ring:
- adis16204_uninitialize_ring(st->indio_dev->ring);
+ iio_ring_buffer_unregister(st->indio_dev->ring);
error_unreg_ring_funcs:
adis16204_unconfigure_ring(st->indio_dev);
error_free_dev:
@@ -571,13 +574,8 @@
struct adis16204_state *st = spi_get_drvdata(spi);
struct iio_dev *indio_dev = st->indio_dev;
- flush_scheduled_work();
-
adis16204_remove_trigger(indio_dev);
- if (spi->irq)
- iio_unregister_interrupt_line(indio_dev, 0);
-
- adis16204_uninitialize_ring(indio_dev->ring);
+ iio_ring_buffer_unregister(st->indio_dev->ring);
iio_device_unregister(indio_dev);
adis16204_unconfigure_ring(indio_dev);
kfree(st->tx);
@@ -609,5 +607,5 @@
module_exit(adis16204_exit);
MODULE_AUTHOR("Barry Song <21cnbao@gmail.com>");
-MODULE_DESCRIPTION("Analog Devices ADIS16204 Programmable High-g Digital Impact Sensor and Recorder");
+MODULE_DESCRIPTION("ADIS16204 High-g Digital Impact Sensor and Recorder");
MODULE_LICENSE("GPL v2");
diff --git a/drivers/staging/iio/accel/adis16204_ring.c b/drivers/staging/iio/accel/adis16204_ring.c
index 420b160f..a2d36fb 100644
--- a/drivers/staging/iio/accel/adis16204_ring.c
+++ b/drivers/staging/iio/accel/adis16204_ring.c
@@ -17,55 +17,6 @@
#include "../trigger.h"
#include "adis16204.h"
-static IIO_SCAN_EL_C(in_supply, ADIS16204_SCAN_SUPPLY, ADIS16204_SUPPLY_OUT, NULL);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(in_supply, u, 12, 16);
-static IIO_SCAN_EL_C(accel_x, ADIS16204_SCAN_ACC_X, ADIS16204_XACCL_OUT, NULL);
-static IIO_SCAN_EL_C(accel_y, ADIS16204_SCAN_ACC_Y, ADIS16204_YACCL_OUT, NULL);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(accel, s, 14, 16);
-static IIO_SCAN_EL_C(in0, ADIS16204_SCAN_AUX_ADC, ADIS16204_AUX_ADC, NULL);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(in0, u, 12, 16);
-static IIO_SCAN_EL_C(temp, ADIS16204_SCAN_TEMP, ADIS16204_TEMP_OUT, NULL);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(temp, u, 12, 16);
-static IIO_SCAN_EL_TIMESTAMP(5);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(timestamp, s, 64, 64);
-
-static struct attribute *adis16204_scan_el_attrs[] = {
- &iio_scan_el_in_supply.dev_attr.attr,
- &iio_const_attr_in_supply_index.dev_attr.attr,
- &iio_const_attr_in_supply_type.dev_attr.attr,
- &iio_scan_el_accel_x.dev_attr.attr,
- &iio_const_attr_accel_x_index.dev_attr.attr,
- &iio_scan_el_accel_y.dev_attr.attr,
- &iio_const_attr_accel_y_index.dev_attr.attr,
- &iio_const_attr_accel_type.dev_attr.attr,
- &iio_scan_el_in0.dev_attr.attr,
- &iio_const_attr_in0_index.dev_attr.attr,
- &iio_const_attr_in0_type.dev_attr.attr,
- &iio_scan_el_temp.dev_attr.attr,
- &iio_const_attr_temp_index.dev_attr.attr,
- &iio_const_attr_temp_type.dev_attr.attr,
- &iio_scan_el_timestamp.dev_attr.attr,
- &iio_const_attr_timestamp_index.dev_attr.attr,
- &iio_const_attr_timestamp_type.dev_attr.attr,
- NULL,
-};
-
-static struct attribute_group adis16204_scan_el_group = {
- .attrs = adis16204_scan_el_attrs,
- .name = "scan_elements",
-};
-
-/**
- * adis16204_poll_func_th() top half interrupt handler called by trigger
- * @private_data: iio_dev
- **/
-static void adis16204_poll_func_th(struct iio_dev *indio_dev, s64 timestamp)
-{
- struct adis16204_state *st = iio_dev_get_devdata(indio_dev);
- st->last_timestamp = timestamp;
- schedule_work(&st->work_trigger_to_ring);
-}
-
/**
* adis16204_read_ring_data() read data registers which will be placed into ring
* @dev: device associated with child of actual device (iio_dev or iio_trig)
@@ -91,7 +42,8 @@
xfers[i].len = 2;
xfers[i].delay_usecs = 20;
xfers[i].tx_buf = st->tx + 2 * i;
- st->tx[2 * i] = ADIS16204_READ_REG(ADIS16204_SUPPLY_OUT + 2 * i);
+ st->tx[2 * i]
+ = ADIS16204_READ_REG(ADIS16204_SUPPLY_OUT + 2 * i);
st->tx[2 * i + 1] = 0;
if (i >= 1)
xfers[i].rx_buf = rx + 2 * (i - 1);
@@ -110,21 +62,20 @@
/* Whilst this makes a lot of calls to iio_sw_ring functions - it is to device
* specific to be rolled into the core.
*/
-static void adis16204_trigger_bh_to_ring(struct work_struct *work_s)
+static irqreturn_t adis16204_trigger_handler(int irq, void *p)
{
- struct adis16204_state *st
- = container_of(work_s, struct adis16204_state,
- work_trigger_to_ring);
- struct iio_ring_buffer *ring = st->indio_dev->ring;
-
+ struct iio_poll_func *pf = p;
+ struct iio_dev *indio_dev = pf->private_data;
+ struct adis16204_state *st = iio_dev_get_devdata(indio_dev);
+ struct iio_ring_buffer *ring = indio_dev->ring;
int i = 0;
s16 *data;
- size_t datasize = ring->access.get_bytes_per_datum(ring);
+ size_t datasize = ring->access->get_bytes_per_datum(ring);
data = kmalloc(datasize, GFP_KERNEL);
if (data == NULL) {
dev_err(&st->us->dev, "memory alloc failed in ring bh");
- return;
+ return -ENOMEM;
}
if (ring->scan_count)
@@ -135,30 +86,32 @@
/* Guaranteed to be aligned with 8 byte boundary */
if (ring->scan_timestamp)
- *((s64 *)(data + ((i + 3)/4)*4)) = st->last_timestamp;
+ *((s64 *)(data + ((i + 3)/4)*4)) = pf->timestamp;
- ring->access.store_to(ring,
- (u8 *)data,
- st->last_timestamp);
+ ring->access->store_to(ring, (u8 *)data, pf->timestamp);
iio_trigger_notify_done(st->indio_dev->trig);
kfree(data);
- return;
+ return IRQ_HANDLED;
}
void adis16204_unconfigure_ring(struct iio_dev *indio_dev)
{
- kfree(indio_dev->pollfunc);
+ iio_dealloc_pollfunc(indio_dev->pollfunc);
iio_sw_rb_free(indio_dev->ring);
}
+static const struct iio_ring_setup_ops adis16204_ring_setup_ops = {
+ .preenable = &iio_sw_ring_preenable,
+ .postenable = &iio_triggered_ring_postenable,
+ .predisable = &iio_triggered_ring_predisable,
+};
+
int adis16204_configure_ring(struct iio_dev *indio_dev)
{
int ret = 0;
- struct adis16204_state *st = indio_dev->dev_data;
struct iio_ring_buffer *ring;
- INIT_WORK(&st->work_trigger_to_ring, adis16204_trigger_bh_to_ring);
ring = iio_sw_rb_allocate(indio_dev);
if (!ring) {
@@ -167,25 +120,30 @@
}
indio_dev->ring = ring;
/* Effectively select the ring buffer implementation */
- iio_ring_sw_register_funcs(&ring->access);
+ ring->access = &ring_sw_access_funcs;
ring->bpe = 2;
- ring->scan_el_attrs = &adis16204_scan_el_group;
ring->scan_timestamp = true;
- ring->preenable = &iio_sw_ring_preenable;
- ring->postenable = &iio_triggered_ring_postenable;
- ring->predisable = &iio_triggered_ring_predisable;
+ ring->setup_ops = &adis16204_ring_setup_ops;
ring->owner = THIS_MODULE;
/* Set default scan mode */
- iio_scan_mask_set(ring, iio_scan_el_in_supply.number);
- iio_scan_mask_set(ring, iio_scan_el_accel_x.number);
- iio_scan_mask_set(ring, iio_scan_el_accel_y.number);
- iio_scan_mask_set(ring, iio_scan_el_temp.number);
- iio_scan_mask_set(ring, iio_scan_el_in0.number);
+ iio_scan_mask_set(ring, ADIS16204_SCAN_SUPPLY);
+ iio_scan_mask_set(ring, ADIS16204_SCAN_ACC_X);
+ iio_scan_mask_set(ring, ADIS16204_SCAN_ACC_Y);
+ iio_scan_mask_set(ring, ADIS16204_SCAN_AUX_ADC);
+ iio_scan_mask_set(ring, ADIS16204_SCAN_TEMP);
- ret = iio_alloc_pollfunc(indio_dev, NULL, &adis16204_poll_func_th);
- if (ret)
+ indio_dev->pollfunc = iio_alloc_pollfunc(&iio_pollfunc_store_time,
+ &adis16204_trigger_handler,
+ IRQF_ONESHOT,
+ indio_dev,
+ "%s_consumer%d",
+ indio_dev->name,
+ indio_dev->id);
+ if (indio_dev->pollfunc == NULL) {
+ ret = -ENOMEM;
goto error_iio_sw_rb_free;
+ }
indio_dev->modes |= INDIO_RING_TRIGGERED;
return 0;
@@ -194,13 +152,3 @@
iio_sw_rb_free(indio_dev->ring);
return ret;
}
-
-int adis16204_initialize_ring(struct iio_ring_buffer *ring)
-{
- return iio_ring_buffer_register(ring, 0);
-}
-
-void adis16204_uninitialize_ring(struct iio_ring_buffer *ring)
-{
- iio_ring_buffer_unregister(ring);
-}
diff --git a/drivers/staging/iio/accel/adis16204_trigger.c b/drivers/staging/iio/accel/adis16204_trigger.c
index 8e9db90..5e1f9ae 100644
--- a/drivers/staging/iio/accel/adis16204_trigger.c
+++ b/drivers/staging/iio/accel/adis16204_trigger.c
@@ -13,35 +13,6 @@
#include "adis16204.h"
/**
- * adis16204_data_rdy_trig_poll() the event handler for the data rdy trig
- **/
-static int adis16204_data_rdy_trig_poll(struct iio_dev *dev_info,
- int index,
- s64 timestamp,
- int no_test)
-{
- struct adis16204_state *st = iio_dev_get_devdata(dev_info);
- struct iio_trigger *trig = st->trig;
-
- iio_trigger_poll(trig, timestamp);
-
- return IRQ_HANDLED;
-}
-
-IIO_EVENT_SH(data_rdy_trig, &adis16204_data_rdy_trig_poll);
-
-static DEVICE_ATTR(name, S_IRUGO, iio_trigger_read_name, NULL);
-
-static struct attribute *adis16204_trigger_attrs[] = {
- &dev_attr_name.attr,
- NULL,
-};
-
-static const struct attribute_group adis16204_trigger_attr_group = {
- .attrs = adis16204_trigger_attrs,
-};
-
-/**
* adis16204_data_rdy_trigger_set_state() set datardy interrupt state
**/
static int adis16204_data_rdy_trigger_set_state(struct iio_trigger *trig,
@@ -49,31 +20,9 @@
{
struct adis16204_state *st = trig->private_data;
struct iio_dev *indio_dev = st->indio_dev;
- int ret = 0;
dev_dbg(&indio_dev->dev, "%s (%d)\n", __func__, state);
- ret = adis16204_set_irq(&st->indio_dev->dev, state);
- if (state == false) {
- iio_remove_event_from_list(&iio_event_data_rdy_trig,
- &indio_dev->interrupts[0]
- ->ev_list);
- flush_scheduled_work();
- } else {
- iio_add_event_to_list(&iio_event_data_rdy_trig,
- &indio_dev->interrupts[0]->ev_list);
- }
- return ret;
-}
-
-/**
- * adis16204_trig_try_reen() try renabling irq for data rdy trigger
- * @trig: the datardy trigger
- **/
-static int adis16204_trig_try_reen(struct iio_trigger *trig)
-{
- struct adis16204_state *st = trig->private_data;
- enable_irq(st->us->irq);
- return 0;
+ return adis16204_set_irq(st->indio_dev, state);
}
int adis16204_probe_trigger(struct iio_dev *indio_dev)
@@ -81,34 +30,38 @@
int ret;
struct adis16204_state *st = indio_dev->dev_data;
- st->trig = iio_allocate_trigger();
- st->trig->name = kasprintf(GFP_KERNEL,
- "adis16204-dev%d",
- indio_dev->id);
- if (!st->trig->name) {
+ st->trig = iio_allocate_trigger("adis16204-dev%d", indio_dev->id);
+ if (st->trig == NULL) {
ret = -ENOMEM;
- goto error_free_trig;
+ goto error_ret;
}
+
+ ret = request_irq(st->us->irq,
+ &iio_trigger_generic_data_rdy_poll,
+ IRQF_TRIGGER_RISING,
+ "adis16204",
+ st->trig);
+ if (ret)
+ goto error_free_trig;
+
st->trig->dev.parent = &st->us->dev;
st->trig->owner = THIS_MODULE;
st->trig->private_data = st;
st->trig->set_trigger_state = &adis16204_data_rdy_trigger_set_state;
- st->trig->try_reenable = &adis16204_trig_try_reen;
- st->trig->control_attrs = &adis16204_trigger_attr_group;
ret = iio_trigger_register(st->trig);
/* select default trigger */
indio_dev->trig = st->trig;
if (ret)
- goto error_free_trig_name;
+ goto error_free_irq;
return 0;
-error_free_trig_name:
- kfree(st->trig->name);
+error_free_irq:
+ free_irq(st->us->irq, st->trig);
error_free_trig:
iio_free_trigger(st->trig);
-
+error_ret:
return ret;
}
@@ -117,6 +70,6 @@
struct adis16204_state *state = indio_dev->dev_data;
iio_trigger_unregister(state->trig);
- kfree(state->trig->name);
+ free_irq(state->us->irq, state->trig);
iio_free_trigger(state->trig);
}
diff --git a/drivers/staging/iio/accel/adis16209.h b/drivers/staging/iio/accel/adis16209.h
index 8b0da13..58d08db 100644
--- a/drivers/staging/iio/accel/adis16209.h
+++ b/drivers/staging/iio/accel/adis16209.h
@@ -104,8 +104,6 @@
/**
* struct adis16209_state - device instance specific data
* @us: actual spi_device
- * @work_trigger_to_ring: bh for triggered event handling
- * @last_timestamp: passing timestamp from th to bh of interrupt handler
* @indio_dev: industrial I/O device structure
* @trig: data ready trigger registered with iio
* @tx: transmit buffer
@@ -114,8 +112,6 @@
**/
struct adis16209_state {
struct spi_device *us;
- struct work_struct work_trigger_to_ring;
- s64 last_timestamp;
struct iio_dev *indio_dev;
struct iio_trigger *trig;
u8 *tx;
@@ -123,7 +119,7 @@
struct mutex buf_lock;
};
-int adis16209_set_irq(struct device *dev, bool enable);
+int adis16209_set_irq(struct iio_dev *indio_dev, bool enable);
#ifdef CONFIG_IIO_RING_BUFFER
diff --git a/drivers/staging/iio/accel/adis16209_core.c b/drivers/staging/iio/accel/adis16209_core.c
index e4ac956..c423cc9 100644
--- a/drivers/staging/iio/accel/adis16209_core.c
+++ b/drivers/staging/iio/accel/adis16209_core.c
@@ -6,9 +6,6 @@
* Licensed under the GPL-2 or later.
*/
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/gpio.h>
#include <linux/delay.h>
#include <linux/mutex.h>
#include <linux/device.h>
@@ -23,27 +20,23 @@
#include "../ring_generic.h"
#include "accel.h"
#include "inclinometer.h"
-#include "../gyro/gyro.h"
#include "../adc/adc.h"
#include "adis16209.h"
#define DRIVER_NAME "adis16209"
-static int adis16209_check_status(struct device *dev);
-
/**
* adis16209_spi_write_reg_8() - write single byte to a register
- * @dev: device associated with child of actual device (iio_dev or iio_trig)
+ * @indio_dev: iio device associated with actual device
* @reg_address: the address of the register to be written
* @val: the value to write
**/
-static int adis16209_spi_write_reg_8(struct device *dev,
- u8 reg_address,
- u8 val)
+static int adis16209_spi_write_reg_8(struct iio_dev *indio_dev,
+ u8 reg_address,
+ u8 val)
{
int ret;
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct adis16209_state *st = iio_dev_get_devdata(indio_dev);
mutex_lock(&st->buf_lock);
@@ -58,18 +51,17 @@
/**
* adis16209_spi_write_reg_16() - write 2 bytes to a pair of registers
- * @dev: device associated with child of actual device (iio_dev or iio_trig)
+ * @indio_dev: iio device associated actual device
* @reg_address: the address of the lower of the two registers. Second register
* is assumed to have address one greater.
* @val: value to be written
**/
-static int adis16209_spi_write_reg_16(struct device *dev,
- u8 lower_reg_address,
- u16 value)
+static int adis16209_spi_write_reg_16(struct iio_dev *indio_dev,
+ u8 lower_reg_address,
+ u16 value)
{
int ret;
struct spi_message msg;
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct adis16209_state *st = iio_dev_get_devdata(indio_dev);
struct spi_transfer xfers[] = {
{
@@ -82,7 +74,6 @@
.tx_buf = st->tx + 2,
.bits_per_word = 8,
.len = 2,
- .cs_change = 1,
.delay_usecs = 30,
},
};
@@ -104,17 +95,16 @@
/**
* adis16209_spi_read_reg_16() - read 2 bytes from a 16-bit register
- * @dev: device associated with child of actual device (iio_dev or iio_trig)
+ * @indio_dev: iio device associated with device
* @reg_address: the address of the lower of the two registers. Second register
* is assumed to have address one greater.
* @val: somewhere to pass back the value read
**/
-static int adis16209_spi_read_reg_16(struct device *dev,
- u8 lower_reg_address,
- u16 *val)
+static int adis16209_spi_read_reg_16(struct iio_dev *indio_dev,
+ u8 lower_reg_address,
+ u16 *val)
{
struct spi_message msg;
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct adis16209_state *st = iio_dev_get_devdata(indio_dev);
int ret;
struct spi_transfer xfers[] = {
@@ -128,7 +118,6 @@
.rx_buf = st->rx,
.bits_per_word = 8,
.len = 2,
- .cs_change = 1,
.delay_usecs = 30,
},
};
@@ -154,119 +143,14 @@
return ret;
}
-static ssize_t adis16209_read_12bit_unsigned(struct device *dev,
- struct device_attribute *attr,
- char *buf)
+static int adis16209_reset(struct iio_dev *indio_dev)
{
int ret;
- u16 val = 0;
- struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
-
- ret = adis16209_spi_read_reg_16(dev, this_attr->address, &val);
- if (ret)
- return ret;
-
- if (val & ADIS16209_ERROR_ACTIVE)
- adis16209_check_status(dev);
-
- return sprintf(buf, "%u\n", val & 0x0FFF);
-}
-
-static ssize_t adis16209_read_14bit_unsigned(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- int ret;
- u16 val = 0;
- struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
-
- ret = adis16209_spi_read_reg_16(dev, this_attr->address, &val);
- if (ret)
- return ret;
-
- if (val & ADIS16209_ERROR_ACTIVE)
- adis16209_check_status(dev);
-
- return sprintf(buf, "%u\n", val & 0x3FFF);
-}
-
-static ssize_t adis16209_read_temp(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
- ssize_t ret;
- u16 val;
-
- /* Take the iio_dev status lock */
- mutex_lock(&indio_dev->mlock);
-
- ret = adis16209_spi_read_reg_16(dev, ADIS16209_TEMP_OUT, (u16 *)&val);
- if (ret)
- goto error_ret;
-
- if (val & ADIS16209_ERROR_ACTIVE)
- adis16209_check_status(dev);
-
- val &= 0xFFF;
- ret = sprintf(buf, "%d\n", val);
-
-error_ret:
- mutex_unlock(&indio_dev->mlock);
- return ret;
-}
-
-static ssize_t adis16209_read_14bit_signed(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
- struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
- s16 val = 0;
- ssize_t ret;
-
- mutex_lock(&indio_dev->mlock);
-
- ret = adis16209_spi_read_reg_16(dev, this_attr->address, (u16 *)&val);
- if (!ret) {
- if (val & ADIS16209_ERROR_ACTIVE)
- adis16209_check_status(dev);
-
- val = ((s16)(val << 2) >> 2);
- ret = sprintf(buf, "%d\n", val);
- }
-
- mutex_unlock(&indio_dev->mlock);
-
- return ret;
-}
-
-static ssize_t adis16209_write_16bit(struct device *dev,
- struct device_attribute *attr,
- const char *buf,
- size_t len)
-{
- struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
- int ret;
- long val;
-
- ret = strict_strtol(buf, 10, &val);
- if (ret)
- goto error_ret;
- ret = adis16209_spi_write_reg_16(dev, this_attr->address, val);
-
-error_ret:
- return ret ? ret : len;
-}
-
-static int adis16209_reset(struct device *dev)
-{
- int ret;
- ret = adis16209_spi_write_reg_8(dev,
+ ret = adis16209_spi_write_reg_8(indio_dev,
ADIS16209_GLOB_CMD,
ADIS16209_GLOB_CMD_SW_RESET);
if (ret)
- dev_err(dev, "problem resetting device");
+ dev_err(&indio_dev->dev, "problem resetting device");
return ret;
}
@@ -275,23 +159,25 @@
struct device_attribute *attr,
const char *buf, size_t len)
{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+
if (len < 1)
return -EINVAL;
switch (buf[0]) {
case '1':
case 'y':
case 'Y':
- return adis16209_reset(dev);
+ return adis16209_reset(indio_dev);
}
return -EINVAL;
}
-int adis16209_set_irq(struct device *dev, bool enable)
+int adis16209_set_irq(struct iio_dev *indio_dev, bool enable)
{
int ret = 0;
u16 msc;
- ret = adis16209_spi_read_reg_16(dev, ADIS16209_MSC_CTRL, &msc);
+ ret = adis16209_spi_read_reg_16(indio_dev, ADIS16209_MSC_CTRL, &msc);
if (ret)
goto error_ret;
@@ -302,160 +188,267 @@
else
msc &= ~ADIS16209_MSC_CTRL_DATA_RDY_EN;
- ret = adis16209_spi_write_reg_16(dev, ADIS16209_MSC_CTRL, msc);
+ ret = adis16209_spi_write_reg_16(indio_dev, ADIS16209_MSC_CTRL, msc);
error_ret:
return ret;
}
-static int adis16209_check_status(struct device *dev)
+static int adis16209_check_status(struct iio_dev *indio_dev)
{
u16 status;
int ret;
- ret = adis16209_spi_read_reg_16(dev, ADIS16209_DIAG_STAT, &status);
+ ret = adis16209_spi_read_reg_16(indio_dev,
+ ADIS16209_DIAG_STAT, &status);
if (ret < 0) {
- dev_err(dev, "Reading status failed\n");
+ dev_err(&indio_dev->dev, "Reading status failed\n");
goto error_ret;
}
ret = status & 0x1F;
if (status & ADIS16209_DIAG_STAT_SELFTEST_FAIL)
- dev_err(dev, "Self test failure\n");
+ dev_err(&indio_dev->dev, "Self test failure\n");
if (status & ADIS16209_DIAG_STAT_SPI_FAIL)
- dev_err(dev, "SPI failure\n");
+ dev_err(&indio_dev->dev, "SPI failure\n");
if (status & ADIS16209_DIAG_STAT_FLASH_UPT)
- dev_err(dev, "Flash update failed\n");
+ dev_err(&indio_dev->dev, "Flash update failed\n");
if (status & ADIS16209_DIAG_STAT_POWER_HIGH)
- dev_err(dev, "Power supply above 3.625V\n");
+ dev_err(&indio_dev->dev, "Power supply above 3.625V\n");
if (status & ADIS16209_DIAG_STAT_POWER_LOW)
- dev_err(dev, "Power supply below 3.15V\n");
+ dev_err(&indio_dev->dev, "Power supply below 3.15V\n");
error_ret:
return ret;
}
-static int adis16209_self_test(struct device *dev)
+static int adis16209_self_test(struct iio_dev *indio_dev)
{
int ret;
- ret = adis16209_spi_write_reg_16(dev,
+ ret = adis16209_spi_write_reg_16(indio_dev,
ADIS16209_MSC_CTRL,
ADIS16209_MSC_CTRL_SELF_TEST_EN);
if (ret) {
- dev_err(dev, "problem starting self test");
+ dev_err(&indio_dev->dev, "problem starting self test");
goto err_ret;
}
- adis16209_check_status(dev);
+ adis16209_check_status(indio_dev);
err_ret:
return ret;
}
-static int adis16209_initial_setup(struct adis16209_state *st)
+static int adis16209_initial_setup(struct iio_dev *indio_dev)
{
int ret;
- struct device *dev = &st->indio_dev->dev;
/* Disable IRQ */
- ret = adis16209_set_irq(dev, false);
+ ret = adis16209_set_irq(indio_dev, false);
if (ret) {
- dev_err(dev, "disable irq failed");
+ dev_err(&indio_dev->dev, "disable irq failed");
goto err_ret;
}
/* Do self test */
- ret = adis16209_self_test(dev);
+ ret = adis16209_self_test(indio_dev);
if (ret) {
- dev_err(dev, "self test failure");
+ dev_err(&indio_dev->dev, "self test failure");
goto err_ret;
}
/* Read status register to check the result */
- ret = adis16209_check_status(dev);
+ ret = adis16209_check_status(indio_dev);
if (ret) {
- adis16209_reset(dev);
- dev_err(dev, "device not playing ball -> reset");
+ adis16209_reset(indio_dev);
+ dev_err(&indio_dev->dev, "device not playing ball -> reset");
msleep(ADIS16209_STARTUP_DELAY);
- ret = adis16209_check_status(dev);
+ ret = adis16209_check_status(indio_dev);
if (ret) {
- dev_err(dev, "giving up");
+ dev_err(&indio_dev->dev, "giving up");
goto err_ret;
}
}
- printk(KERN_INFO DRIVER_NAME ": at CS%d (irq %d)\n",
- st->us->chip_select, st->us->irq);
-
err_ret:
return ret;
}
-static IIO_DEV_ATTR_IN_NAMED_RAW(0, supply, adis16209_read_14bit_unsigned,
- ADIS16209_SUPPLY_OUT);
-static IIO_CONST_ATTR_IN_NAMED_SCALE(0, supply, "0.30518");
-static IIO_DEV_ATTR_IN_RAW(1, adis16209_read_12bit_unsigned,
- ADIS16209_AUX_ADC);
-static IIO_CONST_ATTR(in1_scale, "0.6105");
+enum adis16209_chan {
+ in_supply,
+ temp,
+ accel_x,
+ accel_y,
+ incli_x,
+ incli_y,
+ in_aux,
+ rot,
+};
-static IIO_DEV_ATTR_ACCEL_X(adis16209_read_14bit_signed,
- ADIS16209_XACCL_OUT);
-static IIO_DEV_ATTR_ACCEL_Y(adis16209_read_14bit_signed,
- ADIS16209_YACCL_OUT);
-static IIO_DEV_ATTR_ACCEL_X_CALIBBIAS(S_IWUSR | S_IRUGO,
- adis16209_read_14bit_signed,
- adis16209_write_16bit,
- ADIS16209_XACCL_NULL);
-static IIO_DEV_ATTR_ACCEL_Y_CALIBBIAS(S_IWUSR | S_IRUGO,
- adis16209_read_14bit_signed,
- adis16209_write_16bit,
- ADIS16209_YACCL_NULL);
-static IIO_CONST_ATTR_ACCEL_SCALE("0.002394195531");
+static const u8 adis16209_addresses[8][2] = {
+ [in_supply] = { ADIS16209_SUPPLY_OUT },
+ [in_aux] = { ADIS16209_AUX_ADC },
+ [accel_x] = { ADIS16209_XACCL_OUT, ADIS16209_XACCL_NULL },
+ [accel_y] = { ADIS16209_YACCL_OUT, ADIS16209_YACCL_NULL },
+ [incli_x] = { ADIS16209_XINCL_OUT, ADIS16209_XINCL_NULL },
+ [incli_y] = { ADIS16209_YINCL_OUT, ADIS16209_YINCL_NULL },
+ [rot] = { ADIS16209_ROT_OUT },
+ [temp] = { ADIS16209_TEMP_OUT },
+};
-static IIO_DEV_ATTR_INCLI_X(adis16209_read_14bit_signed,
- ADIS16209_XINCL_OUT);
-static IIO_DEV_ATTR_INCLI_Y(adis16209_read_14bit_signed,
- ADIS16209_YINCL_OUT);
-static IIO_CONST_ATTR(incli_scale, "0.00043633231");
+static int adis16209_write_raw(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ int val,
+ int val2,
+ long mask)
+{
+ int bits;
+ s16 val16;
+ u8 addr;
+ switch (mask) {
+ case (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE):
+ switch (chan->type) {
+ case IIO_ACCEL:
+ case IIO_INCLI:
+ bits = 14;
+ break;
+ default:
+ return -EINVAL;
+ };
+ val16 = val & ((1 << bits) - 1);
+ addr = adis16209_addresses[chan->address][1];
+ return adis16209_spi_write_reg_16(indio_dev, addr, val16);
+ }
+ return -EINVAL;
+}
-static IIO_DEVICE_ATTR(rot_raw, S_IRUGO, adis16209_read_14bit_signed,
- NULL, ADIS16209_ROT_OUT);
+static int adis16209_read_raw(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ int *val, int *val2,
+ long mask)
+{
+ int ret;
+ int bits;
+ u8 addr;
+ s16 val16;
-static IIO_DEV_ATTR_TEMP_RAW(adis16209_read_temp);
-static IIO_CONST_ATTR_TEMP_OFFSET("25");
-static IIO_CONST_ATTR_TEMP_SCALE("-0.47");
+ switch (mask) {
+ case 0:
+ mutex_lock(&indio_dev->mlock);
+ addr = adis16209_addresses[chan->address][0];
+ ret = adis16209_spi_read_reg_16(indio_dev, addr, &val16);
+ if (ret)
+ return ret;
+
+ if (val16 & ADIS16209_ERROR_ACTIVE) {
+ ret = adis16209_check_status(indio_dev);
+ if (ret)
+ return ret;
+ }
+ val16 = val16 & ((1 << chan->scan_type.realbits) - 1);
+ if (chan->scan_type.sign == 's')
+ val16 = (s16)(val16 <<
+ (16 - chan->scan_type.realbits)) >>
+ (16 - chan->scan_type.realbits);
+ *val = val16;
+ mutex_unlock(&indio_dev->mlock);
+ return IIO_VAL_INT;
+ case (1 << IIO_CHAN_INFO_SCALE_SEPARATE):
+ case (1 << IIO_CHAN_INFO_SCALE_SHARED):
+ switch (chan->type) {
+ case IIO_IN:
+ *val = 0;
+ if (chan->channel == 0)
+ *val2 = 305180;
+ else
+ *val2 = 610500;
+ return IIO_VAL_INT_PLUS_MICRO;
+ case IIO_TEMP:
+ *val = 0;
+ *val2 = -470000;
+ return IIO_VAL_INT_PLUS_MICRO;
+ case IIO_ACCEL:
+ *val = 0;
+ *val2 = 2394;
+ return IIO_VAL_INT_PLUS_MICRO;
+ case IIO_INCLI:
+ *val = 0;
+ *val2 = 436;
+ return IIO_VAL_INT_PLUS_MICRO;
+ default:
+ return -EINVAL;
+ }
+ break;
+ case (1 << IIO_CHAN_INFO_OFFSET_SEPARATE):
+ *val = 25;
+ return IIO_VAL_INT;
+ case (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE):
+ switch (chan->type) {
+ case IIO_ACCEL:
+ bits = 14;
+ break;
+ default:
+ return -EINVAL;
+ };
+ mutex_lock(&indio_dev->mlock);
+ addr = adis16209_addresses[chan->address][1];
+ ret = adis16209_spi_read_reg_16(indio_dev, addr, &val16);
+ if (ret) {
+ mutex_unlock(&indio_dev->mlock);
+ return ret;
+ }
+ val16 &= (1 << bits) - 1;
+ val16 = (s16)(val16 << (16 - bits)) >> (16 - bits);
+ *val = val16;
+ mutex_unlock(&indio_dev->mlock);
+ return IIO_VAL_INT;
+ }
+ return -EINVAL;
+}
+
+static struct iio_chan_spec adis16209_channels[] = {
+ IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 0, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SEPARATE),
+ in_supply, ADIS16209_SCAN_SUPPLY,
+ IIO_ST('u', 14, 16, 0), 0),
+ IIO_CHAN(IIO_TEMP, 0, 1, 0, NULL, 0, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SEPARATE) |
+ (1 << IIO_CHAN_INFO_OFFSET_SEPARATE),
+ temp, ADIS16209_SCAN_TEMP,
+ IIO_ST('u', 12, 16, 0), 0),
+ IIO_CHAN(IIO_ACCEL, 1, 0, 0, NULL, 0, IIO_MOD_X,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED) |
+ (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE),
+ accel_x, ADIS16209_SCAN_ACC_X,
+ IIO_ST('s', 14, 16, 0), 0),
+ IIO_CHAN(IIO_ACCEL, 1, 0, 0, NULL, 0, IIO_MOD_Y,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED) |
+ (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE),
+ accel_y, ADIS16209_SCAN_ACC_Y,
+ IIO_ST('s', 14, 16, 0), 0),
+ IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 1, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SEPARATE),
+ in_aux, ADIS16209_SCAN_AUX_ADC,
+ IIO_ST('u', 12, 16, 0), 0),
+ IIO_CHAN(IIO_INCLI, 0, 1, 0, NULL, 0, IIO_MOD_X,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ incli_x, ADIS16209_SCAN_INCLI_X,
+ IIO_ST('s', 14, 16, 0), 0),
+ IIO_CHAN(IIO_INCLI, 0, 1, 0, NULL, 0, IIO_MOD_Y,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ incli_y, ADIS16209_SCAN_INCLI_Y,
+ IIO_ST('s', 14, 16, 0), 0),
+ IIO_CHAN(IIO_ROT, 0, 1, 0, NULL, 0, IIO_MOD_X,
+ 0,
+ rot, ADIS16209_SCAN_ROT,
+ IIO_ST('s', 14, 16, 0), 0),
+ IIO_CHAN_SOFT_TIMESTAMP(8)
+};
static IIO_DEVICE_ATTR(reset, S_IWUSR, NULL, adis16209_write_reset, 0);
-static IIO_CONST_ATTR_NAME("adis16209");
-
-static struct attribute *adis16209_event_attributes[] = {
- NULL
-};
-
-static struct attribute_group adis16209_event_attribute_group = {
- .attrs = adis16209_event_attributes,
-};
-
static struct attribute *adis16209_attributes[] = {
- &iio_dev_attr_in0_supply_raw.dev_attr.attr,
- &iio_const_attr_in0_supply_scale.dev_attr.attr,
- &iio_dev_attr_temp_raw.dev_attr.attr,
- &iio_const_attr_temp_offset.dev_attr.attr,
- &iio_const_attr_temp_scale.dev_attr.attr,
&iio_dev_attr_reset.dev_attr.attr,
- &iio_const_attr_name.dev_attr.attr,
- &iio_dev_attr_in1_raw.dev_attr.attr,
- &iio_const_attr_in1_scale.dev_attr.attr,
- &iio_dev_attr_accel_x_raw.dev_attr.attr,
- &iio_dev_attr_accel_y_raw.dev_attr.attr,
- &iio_dev_attr_accel_x_calibbias.dev_attr.attr,
- &iio_dev_attr_accel_y_calibbias.dev_attr.attr,
- &iio_const_attr_accel_scale.dev_attr.attr,
- &iio_dev_attr_incli_x_raw.dev_attr.attr,
- &iio_dev_attr_incli_y_raw.dev_attr.attr,
- &iio_const_attr_incli_scale.dev_attr.attr,
- &iio_dev_attr_rot_raw.dev_attr.attr,
NULL
};
@@ -463,6 +456,13 @@
.attrs = adis16209_attributes,
};
+static const struct iio_info adis16209_info = {
+ .attrs = &adis16209_attribute_group,
+ .read_raw = &adis16209_read_raw,
+ .write_raw = &adis16209_write_raw,
+ .driver_module = THIS_MODULE,
+};
+
static int __devinit adis16209_probe(struct spi_device *spi)
{
int ret, regdone = 0;
@@ -488,18 +488,18 @@
st->us = spi;
mutex_init(&st->buf_lock);
/* setup the industrialio driver allocated elements */
- st->indio_dev = iio_allocate_device();
+ st->indio_dev = iio_allocate_device(0);
if (st->indio_dev == NULL) {
ret = -ENOMEM;
goto error_free_tx;
}
+ st->indio_dev->name = spi->dev.driver->name;
st->indio_dev->dev.parent = &spi->dev;
- st->indio_dev->num_interrupt_lines = 1;
- st->indio_dev->event_attrs = &adis16209_event_attribute_group;
- st->indio_dev->attrs = &adis16209_attribute_group;
+ st->indio_dev->info = &adis16209_info;
+ st->indio_dev->channels = adis16209_channels;
+ st->indio_dev->num_channels = ARRAY_SIZE(adis16209_channels);
st->indio_dev->dev_data = (void *)(st);
- st->indio_dev->driver_module = THIS_MODULE;
st->indio_dev->modes = INDIO_DIRECT_MODE;
ret = adis16209_configure_ring(st->indio_dev);
@@ -511,37 +511,28 @@
goto error_unreg_ring_funcs;
regdone = 1;
- ret = iio_ring_buffer_register(st->indio_dev->ring, 0);
+ ret = iio_ring_buffer_register_ex(st->indio_dev->ring, 0,
+ adis16209_channels,
+ ARRAY_SIZE(adis16209_channels));
if (ret) {
printk(KERN_ERR "failed to initialize the ring\n");
goto error_unreg_ring_funcs;
}
if (spi->irq) {
- ret = iio_register_interrupt_line(spi->irq,
- st->indio_dev,
- 0,
- IRQF_TRIGGER_RISING,
- "adis16209");
- if (ret)
- goto error_uninitialize_ring;
-
ret = adis16209_probe_trigger(st->indio_dev);
if (ret)
- goto error_unregister_line;
+ goto error_uninitialize_ring;
}
/* Get the device into a sane initial state */
- ret = adis16209_initial_setup(st);
+ ret = adis16209_initial_setup(st->indio_dev);
if (ret)
goto error_remove_trigger;
return 0;
error_remove_trigger:
adis16209_remove_trigger(st->indio_dev);
-error_unregister_line:
- if (spi->irq)
- iio_unregister_interrupt_line(st->indio_dev, 0);
error_uninitialize_ring:
iio_ring_buffer_unregister(st->indio_dev->ring);
error_unreg_ring_funcs:
@@ -569,9 +560,6 @@
flush_scheduled_work();
adis16209_remove_trigger(indio_dev);
- if (spi->irq)
- iio_unregister_interrupt_line(indio_dev, 0);
-
iio_ring_buffer_unregister(indio_dev->ring);
iio_device_unregister(indio_dev);
adis16209_unconfigure_ring(indio_dev);
diff --git a/drivers/staging/iio/accel/adis16209_ring.c b/drivers/staging/iio/accel/adis16209_ring.c
index 8eba0af..390908b 100644
--- a/drivers/staging/iio/accel/adis16209_ring.c
+++ b/drivers/staging/iio/accel/adis16209_ring.c
@@ -17,71 +17,6 @@
#include "../trigger.h"
#include "adis16209.h"
-static IIO_SCAN_EL_C(in_supply, ADIS16209_SCAN_SUPPLY,
- ADIS16209_SUPPLY_OUT, NULL);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(in_supply, u, 14, 16)
-static IIO_SCAN_EL_C(accel_x, ADIS16209_SCAN_ACC_X, ADIS16209_XACCL_OUT, NULL);
-static IIO_SCAN_EL_C(accel_y, ADIS16209_SCAN_ACC_Y, ADIS16209_YACCL_OUT, NULL);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(accel, s, 14, 16);
-static IIO_SCAN_EL_C(in0, ADIS16209_SCAN_AUX_ADC, ADIS16209_AUX_ADC, NULL);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(in0, u, 12, 16);
-static IIO_SCAN_EL_C(temp, ADIS16209_SCAN_TEMP, ADIS16209_TEMP_OUT, NULL);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(temp, u, 12, 16);
-static IIO_SCAN_EL_C(incli_x, ADIS16209_SCAN_INCLI_X,
- ADIS16209_XINCL_OUT, NULL);
-static IIO_SCAN_EL_C(incli_y, ADIS16209_SCAN_INCLI_Y,
- ADIS16209_YINCL_OUT, NULL);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(incli, s, 14, 16);
-static IIO_SCAN_EL_C(rot, ADIS16209_SCAN_ROT, ADIS16209_ROT_OUT, NULL);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(rot, s, 14, 16);
-static IIO_SCAN_EL_TIMESTAMP(8);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(timestamp, s, 64, 64);
-
-static struct attribute *adis16209_scan_el_attrs[] = {
- &iio_scan_el_in_supply.dev_attr.attr,
- &iio_const_attr_in_supply_index.dev_attr.attr,
- &iio_const_attr_in_supply_type.dev_attr.attr,
- &iio_scan_el_accel_x.dev_attr.attr,
- &iio_const_attr_accel_x_index.dev_attr.attr,
- &iio_scan_el_accel_y.dev_attr.attr,
- &iio_const_attr_accel_y_index.dev_attr.attr,
- &iio_const_attr_accel_type.dev_attr.attr,
- &iio_scan_el_in0.dev_attr.attr,
- &iio_const_attr_in0_index.dev_attr.attr,
- &iio_const_attr_in0_type.dev_attr.attr,
- &iio_scan_el_temp.dev_attr.attr,
- &iio_const_attr_temp_index.dev_attr.attr,
- &iio_const_attr_temp_type.dev_attr.attr,
- &iio_scan_el_incli_x.dev_attr.attr,
- &iio_const_attr_incli_x_index.dev_attr.attr,
- &iio_scan_el_incli_y.dev_attr.attr,
- &iio_const_attr_incli_y_index.dev_attr.attr,
- &iio_const_attr_incli_type.dev_attr.attr,
- &iio_scan_el_rot.dev_attr.attr,
- &iio_const_attr_rot_index.dev_attr.attr,
- &iio_const_attr_rot_type.dev_attr.attr,
- &iio_scan_el_timestamp.dev_attr.attr,
- &iio_const_attr_timestamp_index.dev_attr.attr,
- &iio_const_attr_timestamp_type.dev_attr.attr,
- NULL,
-};
-
-static struct attribute_group adis16209_scan_el_group = {
- .attrs = adis16209_scan_el_attrs,
- .name = "scan_elements",
-};
-
-/**
- * adis16209_poll_func_th() top half interrupt handler called by trigger
- * @private_data: iio_dev
- **/
-static void adis16209_poll_func_th(struct iio_dev *indio_dev, s64 time)
-{
- struct adis16209_state *st = iio_dev_get_devdata(indio_dev);
- st->last_timestamp = time;
- schedule_work(&st->work_trigger_to_ring);
-}
-
/**
* adis16209_read_ring_data() read data registers which will be placed into ring
* @dev: device associated with child of actual device (iio_dev or iio_trig)
@@ -127,55 +62,56 @@
/* Whilst this makes a lot of calls to iio_sw_ring functions - it is to device
* specific to be rolled into the core.
*/
-static void adis16209_trigger_bh_to_ring(struct work_struct *work_s)
+static irqreturn_t adis16209_trigger_handler(int irq, void *p)
{
- struct adis16209_state *st
- = container_of(work_s, struct adis16209_state,
- work_trigger_to_ring);
- struct iio_ring_buffer *ring = st->indio_dev->ring;
+ struct iio_poll_func *pf = p;
+ struct iio_dev *indio_dev = pf->private_data;
+ struct adis16209_state *st = iio_dev_get_devdata(indio_dev);
+ struct iio_ring_buffer *ring = indio_dev->ring;
int i = 0;
s16 *data;
- size_t datasize = ring->access.get_bytes_per_datum(ring);
+ size_t datasize = ring->access->get_bytes_per_datum(ring);
data = kmalloc(datasize , GFP_KERNEL);
if (data == NULL) {
dev_err(&st->us->dev, "memory alloc failed in ring bh");
- return;
+ return -ENOMEM;
}
- if (ring->scan_count)
- if (adis16209_read_ring_data(&st->indio_dev->dev, st->rx) >= 0)
- for (; i < ring->scan_count; i++)
- data[i] = be16_to_cpup(
- (__be16 *)&(st->rx[i*2]));
+ if (ring->scan_count &&
+ adis16209_read_ring_data(&st->indio_dev->dev, st->rx) >= 0)
+ for (; i < ring->scan_count; i++)
+ data[i] = be16_to_cpup((__be16 *)&(st->rx[i*2]));
/* Guaranteed to be aligned with 8 byte boundary */
if (ring->scan_timestamp)
- *((s64 *)(data + ((i + 3)/4)*4)) = st->last_timestamp;
+ *((s64 *)(data + ((i + 3)/4)*4)) = pf->timestamp;
- ring->access.store_to(ring,
- (u8 *)data,
- st->last_timestamp);
+ ring->access->store_to(ring, (u8 *)data, pf->timestamp);
iio_trigger_notify_done(st->indio_dev->trig);
kfree(data);
- return;
+ return IRQ_HANDLED;
}
void adis16209_unconfigure_ring(struct iio_dev *indio_dev)
{
- kfree(indio_dev->pollfunc);
+ iio_dealloc_pollfunc(indio_dev->pollfunc);
iio_sw_rb_free(indio_dev->ring);
}
+static const struct iio_ring_setup_ops adis16209_ring_setup_ops = {
+ .preenable = &iio_sw_ring_preenable,
+ .postenable = &iio_triggered_ring_postenable,
+ .predisable = &iio_triggered_ring_predisable,
+};
+
int adis16209_configure_ring(struct iio_dev *indio_dev)
{
int ret = 0;
- struct adis16209_state *st = indio_dev->dev_data;
struct iio_ring_buffer *ring;
- INIT_WORK(&st->work_trigger_to_ring, adis16209_trigger_bh_to_ring);
ring = iio_sw_rb_allocate(indio_dev);
if (!ring) {
@@ -184,28 +120,33 @@
}
indio_dev->ring = ring;
/* Effectively select the ring buffer implementation */
- iio_ring_sw_register_funcs(&ring->access);
+ ring->access = &ring_sw_access_funcs;
ring->bpe = 2;
- ring->scan_el_attrs = &adis16209_scan_el_group;
ring->scan_timestamp = true;
- ring->preenable = &iio_sw_ring_preenable;
- ring->postenable = &iio_triggered_ring_postenable;
- ring->predisable = &iio_triggered_ring_predisable;
+ ring->setup_ops = &adis16209_ring_setup_ops;
ring->owner = THIS_MODULE;
/* Set default scan mode */
- iio_scan_mask_set(ring, iio_scan_el_in_supply.number);
- iio_scan_mask_set(ring, iio_scan_el_rot.number);
- iio_scan_mask_set(ring, iio_scan_el_accel_x.number);
- iio_scan_mask_set(ring, iio_scan_el_accel_y.number);
- iio_scan_mask_set(ring, iio_scan_el_temp.number);
- iio_scan_mask_set(ring, iio_scan_el_in0.number);
- iio_scan_mask_set(ring, iio_scan_el_incli_x.number);
- iio_scan_mask_set(ring, iio_scan_el_incli_y.number);
+ iio_scan_mask_set(ring, ADIS16209_SCAN_SUPPLY);
+ iio_scan_mask_set(ring, ADIS16209_SCAN_ACC_X);
+ iio_scan_mask_set(ring, ADIS16209_SCAN_ACC_Y);
+ iio_scan_mask_set(ring, ADIS16209_SCAN_AUX_ADC);
+ iio_scan_mask_set(ring, ADIS16209_SCAN_TEMP);
+ iio_scan_mask_set(ring, ADIS16209_SCAN_INCLI_X);
+ iio_scan_mask_set(ring, ADIS16209_SCAN_INCLI_Y);
+ iio_scan_mask_set(ring, ADIS16209_SCAN_ROT);
- ret = iio_alloc_pollfunc(indio_dev, NULL, &adis16209_poll_func_th);
- if (ret)
+ indio_dev->pollfunc = iio_alloc_pollfunc(&iio_pollfunc_store_time,
+ &adis16209_trigger_handler,
+ IRQF_ONESHOT,
+ indio_dev,
+ "%s_consumer%d",
+ indio_dev->name,
+ indio_dev->id);
+ if (indio_dev->pollfunc == NULL) {
+ ret = -ENOMEM;
goto error_iio_sw_rb_free;
+ }
indio_dev->modes |= INDIO_RING_TRIGGERED;
return 0;
diff --git a/drivers/staging/iio/accel/adis16209_trigger.c b/drivers/staging/iio/accel/adis16209_trigger.c
index d2980dc..211ee70 100644
--- a/drivers/staging/iio/accel/adis16209_trigger.c
+++ b/drivers/staging/iio/accel/adis16209_trigger.c
@@ -15,32 +15,12 @@
/**
* adis16209_data_rdy_trig_poll() the event handler for the data rdy trig
**/
-static int adis16209_data_rdy_trig_poll(struct iio_dev *dev_info,
- int index,
- s64 timestamp,
- int no_test)
+static irqreturn_t adis16209_data_rdy_trig_poll(int irq, void *trig)
{
- struct adis16209_state *st = iio_dev_get_devdata(dev_info);
- struct iio_trigger *trig = st->trig;
-
- iio_trigger_poll(trig, timestamp);
-
+ iio_trigger_poll(trig, iio_get_time_ns());
return IRQ_HANDLED;
}
-IIO_EVENT_SH(data_rdy_trig, &adis16209_data_rdy_trig_poll);
-
-static IIO_TRIGGER_NAME_ATTR;
-
-static struct attribute *adis16209_trigger_attrs[] = {
- &dev_attr_name.attr,
- NULL,
-};
-
-static const struct attribute_group adis16209_trigger_attr_group = {
- .attrs = adis16209_trigger_attrs,
-};
-
/**
* adis16209_data_rdy_trigger_set_state() set datardy interrupt state
**/
@@ -49,31 +29,9 @@
{
struct adis16209_state *st = trig->private_data;
struct iio_dev *indio_dev = st->indio_dev;
- int ret = 0;
dev_dbg(&indio_dev->dev, "%s (%d)\n", __func__, state);
- ret = adis16209_set_irq(&st->indio_dev->dev, state);
- if (state == false) {
- iio_remove_event_from_list(&iio_event_data_rdy_trig,
- &indio_dev->interrupts[0]
- ->ev_list);
- flush_scheduled_work();
- } else {
- iio_add_event_to_list(&iio_event_data_rdy_trig,
- &indio_dev->interrupts[0]->ev_list);
- }
- return ret;
-}
-
-/**
- * adis16209_trig_try_reen() try renabling irq for data rdy trigger
- * @trig: the datardy trigger
- **/
-static int adis16209_trig_try_reen(struct iio_trigger *trig)
-{
- struct adis16209_state *st = trig->private_data;
- enable_irq(st->us->irq);
- return 0;
+ return adis16209_set_irq(st->indio_dev, state);
}
int adis16209_probe_trigger(struct iio_dev *indio_dev)
@@ -81,34 +39,37 @@
int ret;
struct adis16209_state *st = indio_dev->dev_data;
- st->trig = iio_allocate_trigger();
- st->trig->name = kasprintf(GFP_KERNEL,
- "adis16209-dev%d",
- indio_dev->id);
- if (!st->trig->name) {
+ st->trig = iio_allocate_trigger("adis16209-dev%d", indio_dev->id);
+ if (st->trig == NULL) {
ret = -ENOMEM;
- goto error_free_trig;
+ goto error_ret;
}
+
+ ret = request_irq(st->us->irq,
+ adis16209_data_rdy_trig_poll,
+ IRQF_TRIGGER_RISING,
+ "adis16209",
+ st->trig);
+ if (ret)
+ goto error_free_trig;
st->trig->dev.parent = &st->us->dev;
st->trig->owner = THIS_MODULE;
st->trig->private_data = st;
st->trig->set_trigger_state = &adis16209_data_rdy_trigger_set_state;
- st->trig->try_reenable = &adis16209_trig_try_reen;
- st->trig->control_attrs = &adis16209_trigger_attr_group;
ret = iio_trigger_register(st->trig);
/* select default trigger */
indio_dev->trig = st->trig;
if (ret)
- goto error_free_trig_name;
+ goto error_free_irq;
return 0;
-error_free_trig_name:
- kfree(st->trig->name);
+error_free_irq:
+ free_irq(st->us->irq, st->trig);
error_free_trig:
iio_free_trigger(st->trig);
-
+error_ret:
return ret;
}
@@ -117,6 +78,6 @@
struct adis16209_state *state = indio_dev->dev_data;
iio_trigger_unregister(state->trig);
- kfree(state->trig->name);
+ free_irq(state->us->irq, state->trig);
iio_free_trigger(state->trig);
}
diff --git a/drivers/staging/iio/accel/adis16220_core.c b/drivers/staging/iio/accel/adis16220_core.c
index 1c1e98a..605a75e 100644
--- a/drivers/staging/iio/accel/adis16220_core.c
+++ b/drivers/staging/iio/accel/adis16220_core.c
@@ -521,8 +521,6 @@
static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("100200");
-static IIO_CONST_ATTR_NAME("adis16220");
-
static struct attribute *adis16220_attributes[] = {
&iio_dev_attr_in0_supply_raw.dev_attr.attr,
&iio_const_attr_in0_supply_scale.dev_attr.attr,
@@ -539,7 +537,6 @@
&iio_dev_attr_reset.dev_attr.attr,
&iio_dev_attr_capture.dev_attr.attr,
&iio_dev_attr_capture_count.dev_attr.attr,
- &iio_const_attr_name.dev_attr.attr,
NULL
};
@@ -547,6 +544,10 @@
.attrs = adis16220_attributes,
};
+static const struct iio_info adis16220_info = {
+ .attrs = &adis16220_attribute_group,
+ .driver_module = THIS_MODULE,
+};
static int __devinit adis16220_probe(struct spi_device *spi)
{
int ret, regdone = 0;
@@ -572,16 +573,16 @@
st->us = spi;
mutex_init(&st->buf_lock);
/* setup the industrialio driver allocated elements */
- st->indio_dev = iio_allocate_device();
+ st->indio_dev = iio_allocate_device(0);
if (st->indio_dev == NULL) {
ret = -ENOMEM;
goto error_free_tx;
}
+ st->indio_dev->name = spi->dev.driver->name;
st->indio_dev->dev.parent = &spi->dev;
- st->indio_dev->attrs = &adis16220_attribute_group;
+ st->indio_dev->info = &adis16220_info;
st->indio_dev->dev_data = (void *)(st);
- st->indio_dev->driver_module = THIS_MODULE;
st->indio_dev->modes = INDIO_DIRECT_MODE;
ret = iio_device_register(st->indio_dev);
diff --git a/drivers/staging/iio/accel/adis16240.h b/drivers/staging/iio/accel/adis16240.h
index 76a4579..162b1f4 100644
--- a/drivers/staging/iio/accel/adis16240.h
+++ b/drivers/staging/iio/accel/adis16240.h
@@ -126,9 +126,6 @@
/**
* struct adis16240_state - device instance specific data
* @us: actual spi_device
- * @work_trigger_to_ring: bh for triggered event handling
- * @inter: used to check if new interrupt has been triggered
- * @last_timestamp: passing timestamp from th to bh of interrupt handler
* @indio_dev: industrial I/O device structure
* @trig: data ready trigger registered with iio
* @tx: transmit buffer
@@ -137,8 +134,6 @@
**/
struct adis16240_state {
struct spi_device *us;
- struct work_struct work_trigger_to_ring;
- s64 last_timestamp;
struct iio_dev *indio_dev;
struct iio_trigger *trig;
u8 *tx;
@@ -146,7 +141,7 @@
struct mutex buf_lock;
};
-int adis16240_set_irq(struct device *dev, bool enable);
+int adis16240_set_irq(struct iio_dev *indio_dev, bool enable);
#ifdef CONFIG_IIO_RING_BUFFER
/* At the moment triggers are only used for ring buffer
diff --git a/drivers/staging/iio/accel/adis16240_core.c b/drivers/staging/iio/accel/adis16240_core.c
index d11d164..ac60385 100644
--- a/drivers/staging/iio/accel/adis16240_core.c
+++ b/drivers/staging/iio/accel/adis16240_core.c
@@ -28,20 +28,19 @@
#define DRIVER_NAME "adis16240"
-static int adis16240_check_status(struct device *dev);
+static int adis16240_check_status(struct iio_dev *indio_dev);
/**
* adis16240_spi_write_reg_8() - write single byte to a register
- * @dev: device associated with child of actual device (iio_dev or iio_trig)
+ * @indio_dev: iio_dev associated with device
* @reg_address: the address of the register to be written
* @val: the value to write
**/
-static int adis16240_spi_write_reg_8(struct device *dev,
- u8 reg_address,
- u8 val)
+static int adis16240_spi_write_reg_8(struct iio_dev *indio_dev,
+ u8 reg_address,
+ u8 val)
{
int ret;
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct adis16240_state *st = iio_dev_get_devdata(indio_dev);
mutex_lock(&st->buf_lock);
@@ -56,18 +55,17 @@
/**
* adis16240_spi_write_reg_16() - write 2 bytes to a pair of registers
- * @dev: device associated with child of actual device (iio_dev or iio_trig)
+ * @indio_dev: iio_dev for this device
* @reg_address: the address of the lower of the two registers. Second register
* is assumed to have address one greater.
* @val: value to be written
**/
-static int adis16240_spi_write_reg_16(struct device *dev,
- u8 lower_reg_address,
- u16 value)
+static int adis16240_spi_write_reg_16(struct iio_dev *indio_dev,
+ u8 lower_reg_address,
+ u16 value)
{
int ret;
struct spi_message msg;
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct adis16240_state *st = iio_dev_get_devdata(indio_dev);
struct spi_transfer xfers[] = {
{
@@ -80,7 +78,6 @@
.tx_buf = st->tx + 2,
.bits_per_word = 8,
.len = 2,
- .cs_change = 1,
.delay_usecs = 35,
},
};
@@ -102,17 +99,16 @@
/**
* adis16240_spi_read_reg_16() - read 2 bytes from a 16-bit register
- * @dev: device associated with child of actual device (iio_dev or iio_trig)
+ * @indio_dev: iio_dev for this device
* @reg_address: the address of the lower of the two registers. Second register
* is assumed to have address one greater.
* @val: somewhere to pass back the value read
**/
-static int adis16240_spi_read_reg_16(struct device *dev,
+static int adis16240_spi_read_reg_16(struct iio_dev *indio_dev,
u8 lower_reg_address,
u16 *val)
{
struct spi_message msg;
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct adis16240_state *st = iio_dev_get_devdata(indio_dev);
int ret;
struct spi_transfer xfers[] = {
@@ -159,61 +155,30 @@
char *buf,
unsigned bits)
{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
int ret;
s16 val = 0;
unsigned shift = 16 - bits;
struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
- ret = adis16240_spi_read_reg_16(dev, this_attr->address, (u16 *)&val);
+ ret = adis16240_spi_read_reg_16(indio_dev,
+ this_attr->address, (u16 *)&val);
if (ret)
return ret;
if (val & ADIS16240_ERROR_ACTIVE)
- adis16240_check_status(dev);
+ adis16240_check_status(indio_dev);
val = ((s16)(val << shift) >> shift);
return sprintf(buf, "%d\n", val);
}
-static ssize_t adis16240_read_10bit_unsigned(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- int ret;
- u16 val = 0;
- struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
-
- ret = adis16240_spi_read_reg_16(dev, this_attr->address, &val);
- if (ret)
- return ret;
-
- if (val & ADIS16240_ERROR_ACTIVE)
- adis16240_check_status(dev);
-
- return sprintf(buf, "%u\n", val & 0x03FF);
-}
-
-static ssize_t adis16240_read_10bit_signed(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
- ssize_t ret;
-
- /* Take the iio_dev status lock */
- mutex_lock(&indio_dev->mlock);
- ret = adis16240_spi_read_signed(dev, attr, buf, 10);
- mutex_unlock(&indio_dev->mlock);
-
- return ret;
-}
-
static ssize_t adis16240_read_12bit_signed(struct device *dev,
struct device_attribute *attr,
char *buf)
{
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
ssize_t ret;
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
/* Take the iio_dev status lock */
mutex_lock(&indio_dev->mlock);
@@ -223,32 +188,14 @@
return ret;
}
-static ssize_t adis16240_write_16bit(struct device *dev,
- struct device_attribute *attr,
- const char *buf,
- size_t len)
-{
- struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
- int ret;
- long val;
-
- ret = strict_strtol(buf, 10, &val);
- if (ret)
- goto error_ret;
- ret = adis16240_spi_write_reg_16(dev, this_attr->address, val);
-
-error_ret:
- return ret ? ret : len;
-}
-
-static int adis16240_reset(struct device *dev)
+static int adis16240_reset(struct iio_dev *indio_dev)
{
int ret;
- ret = adis16240_spi_write_reg_8(dev,
+ ret = adis16240_spi_write_reg_8(indio_dev,
ADIS16240_GLOB_CMD,
ADIS16240_GLOB_CMD_SW_RESET);
if (ret)
- dev_err(dev, "problem resetting device");
+ dev_err(&indio_dev->dev, "problem resetting device");
return ret;
}
@@ -257,23 +204,26 @@
struct device_attribute *attr,
const char *buf, size_t len)
{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+
if (len < 1)
return -EINVAL;
switch (buf[0]) {
case '1':
case 'y':
case 'Y':
- return adis16240_reset(dev);
+ return adis16240_reset(indio_dev);
}
return -EINVAL;
}
-int adis16240_set_irq(struct device *dev, bool enable)
+int adis16240_set_irq(struct iio_dev *indio_dev, bool enable)
{
int ret = 0;
u16 msc;
- ret = adis16240_spi_read_reg_16(dev, ADIS16240_MSC_CTRL, &msc);
+ ret = adis16240_spi_read_reg_16(indio_dev,
+ ADIS16240_MSC_CTRL, &msc);
if (ret)
goto error_ret;
@@ -284,37 +234,40 @@
else
msc &= ~ADIS16240_MSC_CTRL_DATA_RDY_EN;
- ret = adis16240_spi_write_reg_16(dev, ADIS16240_MSC_CTRL, msc);
+ ret = adis16240_spi_write_reg_16(indio_dev,
+ ADIS16240_MSC_CTRL, msc);
error_ret:
return ret;
}
-static int adis16240_self_test(struct device *dev)
+static int adis16240_self_test(struct iio_dev *indio_dev)
{
int ret;
- ret = adis16240_spi_write_reg_16(dev,
+ ret = adis16240_spi_write_reg_16(indio_dev,
ADIS16240_MSC_CTRL,
ADIS16240_MSC_CTRL_SELF_TEST_EN);
if (ret) {
- dev_err(dev, "problem starting self test");
+ dev_err(&indio_dev->dev, "problem starting self test");
goto err_ret;
}
msleep(ADIS16240_STARTUP_DELAY);
- adis16240_check_status(dev);
+ adis16240_check_status(indio_dev);
err_ret:
return ret;
}
-static int adis16240_check_status(struct device *dev)
+static int adis16240_check_status(struct iio_dev *indio_dev)
{
u16 status;
int ret;
+ struct device *dev = &indio_dev->dev;
- ret = adis16240_spi_read_reg_16(dev, ADIS16240_DIAG_STAT, &status);
+ ret = adis16240_spi_read_reg_16(indio_dev,
+ ADIS16240_DIAG_STAT, &status);
if (ret < 0) {
dev_err(dev, "Reading status failed\n");
@@ -337,122 +290,216 @@
return ret;
}
-static int adis16240_initial_setup(struct adis16240_state *st)
+static int adis16240_initial_setup(struct iio_dev *indio_dev)
{
int ret;
- struct device *dev = &st->indio_dev->dev;
+ struct device *dev = &indio_dev->dev;
/* Disable IRQ */
- ret = adis16240_set_irq(dev, false);
+ ret = adis16240_set_irq(indio_dev, false);
if (ret) {
dev_err(dev, "disable irq failed");
goto err_ret;
}
/* Do self test */
- ret = adis16240_self_test(dev);
+ ret = adis16240_self_test(indio_dev);
if (ret) {
dev_err(dev, "self test failure");
goto err_ret;
}
/* Read status register to check the result */
- ret = adis16240_check_status(dev);
+ ret = adis16240_check_status(indio_dev);
if (ret) {
- adis16240_reset(dev);
+ adis16240_reset(indio_dev);
dev_err(dev, "device not playing ball -> reset");
msleep(ADIS16240_STARTUP_DELAY);
- ret = adis16240_check_status(dev);
+ ret = adis16240_check_status(indio_dev);
if (ret) {
dev_err(dev, "giving up");
goto err_ret;
}
}
- printk(KERN_INFO DRIVER_NAME ": at CS%d (irq %d)\n",
- st->us->chip_select, st->us->irq);
-
err_ret:
return ret;
}
-static IIO_DEV_ATTR_IN_NAMED_RAW(0, supply, adis16240_read_10bit_unsigned,
- ADIS16240_SUPPLY_OUT);
-static IIO_DEV_ATTR_IN_RAW(1, adis16240_read_10bit_signed,
- ADIS16240_AUX_ADC);
-static IIO_CONST_ATTR_IN_NAMED_SCALE(0, supply, "0.00488");
-
-static IIO_CONST_ATTR_ACCEL_SCALE("0.50406181");
-static IIO_CONST_ATTR(accel_peak_scale, "6.6292954");
-static IIO_DEV_ATTR_ACCEL_X(adis16240_read_10bit_signed,
- ADIS16240_XACCL_OUT);
-static IIO_DEVICE_ATTR(accel_x_peak_raw, S_IRUGO,
- adis16240_read_10bit_signed, NULL,
- ADIS16240_XPEAK_OUT);
-static IIO_DEV_ATTR_ACCEL_Y(adis16240_read_10bit_signed,
- ADIS16240_YACCL_OUT);
-static IIO_DEVICE_ATTR(accel_y_peak_raw, S_IRUGO,
- adis16240_read_10bit_signed, NULL,
- ADIS16240_YPEAK_OUT);
-static IIO_DEV_ATTR_ACCEL_Z(adis16240_read_10bit_signed,
- ADIS16240_ZACCL_OUT);
-static IIO_DEVICE_ATTR(accel_z_peak_raw, S_IRUGO,
- adis16240_read_10bit_signed, NULL,
- ADIS16240_ZPEAK_OUT);
-
static IIO_DEVICE_ATTR(accel_xyz_squared_peak_raw, S_IRUGO,
adis16240_read_12bit_signed, NULL,
ADIS16240_XYZPEAK_OUT);
-static IIO_DEV_ATTR_ACCEL_X_CALIBBIAS(S_IWUSR | S_IRUGO,
- adis16240_read_10bit_signed,
- adis16240_write_16bit,
- ADIS16240_XACCL_OFF);
-static IIO_DEV_ATTR_ACCEL_Y_CALIBBIAS(S_IWUSR | S_IRUGO,
- adis16240_read_10bit_signed,
- adis16240_write_16bit,
- ADIS16240_YACCL_OFF);
-static IIO_DEV_ATTR_ACCEL_Z_CALIBBIAS(S_IWUSR | S_IRUGO,
- adis16240_read_10bit_signed,
- adis16240_write_16bit,
- ADIS16240_ZACCL_OFF);
-static IIO_DEV_ATTR_TEMP_RAW(adis16240_read_10bit_unsigned);
-static IIO_CONST_ATTR_TEMP_SCALE("0.244");
static IIO_DEVICE_ATTR(reset, S_IWUSR, NULL, adis16240_write_reset, 0);
static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("4096");
-static IIO_CONST_ATTR_NAME("adis16240");
-
-static struct attribute *adis16240_event_attributes[] = {
- NULL
+enum adis16240_chan {
+ in_supply,
+ in_aux,
+ accel_x,
+ accel_y,
+ accel_z,
+ temp,
};
-static struct attribute_group adis16240_event_attribute_group = {
- .attrs = adis16240_event_attributes,
+static const u8 adis16240_addresses[6][3] = {
+ [in_supply] = { ADIS16240_SUPPLY_OUT },
+ [in_aux] = { ADIS16240_AUX_ADC },
+ [accel_x] = { ADIS16240_XACCL_OUT, ADIS16240_XACCL_OFF,
+ ADIS16240_XPEAK_OUT },
+ [accel_y] = { ADIS16240_YACCL_OUT, ADIS16240_YACCL_OFF,
+ ADIS16240_YPEAK_OUT },
+ [accel_z] = { ADIS16240_ZACCL_OUT, ADIS16240_ZACCL_OFF,
+ ADIS16240_ZPEAK_OUT },
+ [temp] = { ADIS16240_TEMP_OUT },
+};
+
+static int adis16240_read_raw(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ int *val, int *val2,
+ long mask)
+{
+ int ret;
+ int bits;
+ u8 addr;
+ s16 val16;
+
+ switch (mask) {
+ case 0:
+ mutex_lock(&indio_dev->mlock);
+ addr = adis16240_addresses[chan->address][0];
+ ret = adis16240_spi_read_reg_16(indio_dev, addr, &val16);
+ if (ret)
+ return ret;
+
+ if (val16 & ADIS16240_ERROR_ACTIVE) {
+ ret = adis16240_check_status(indio_dev);
+ if (ret)
+ return ret;
+ }
+ val16 = val16 & ((1 << chan->scan_type.realbits) - 1);
+ if (chan->scan_type.sign == 's')
+ val16 = (s16)(val16 <<
+ (16 - chan->scan_type.realbits)) >>
+ (16 - chan->scan_type.realbits);
+ *val = val16;
+ mutex_unlock(&indio_dev->mlock);
+ return IIO_VAL_INT;
+ case (1 << IIO_CHAN_INFO_SCALE_SEPARATE):
+ case (1 << IIO_CHAN_INFO_SCALE_SHARED):
+ switch (chan->type) {
+ case IIO_IN:
+ *val = 0;
+ if (chan->channel == 0)
+ *val2 = 4880;
+ else
+ return -EINVAL;
+ return IIO_VAL_INT_PLUS_MICRO;
+ case IIO_TEMP:
+ *val = 0;
+ *val2 = 244000;
+ return IIO_VAL_INT_PLUS_MICRO;
+ case IIO_ACCEL:
+ *val = 0;
+ *val2 = 504062;
+ return IIO_VAL_INT_PLUS_MICRO;
+ default:
+ return -EINVAL;
+ }
+ break;
+ case (1 << IIO_CHAN_INFO_PEAK_SCALE_SHARED):
+ *val = 6;
+ *val2 = 629295;
+ return IIO_VAL_INT_PLUS_MICRO;
+ case (1 << IIO_CHAN_INFO_OFFSET_SEPARATE):
+ *val = 25;
+ return IIO_VAL_INT;
+ case (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE):
+ bits = 10;
+ mutex_lock(&indio_dev->mlock);
+ addr = adis16240_addresses[chan->address][1];
+ ret = adis16240_spi_read_reg_16(indio_dev, addr, &val16);
+ if (ret) {
+ mutex_unlock(&indio_dev->mlock);
+ return ret;
+ }
+ val16 &= (1 << bits) - 1;
+ val16 = (s16)(val16 << (16 - bits)) >> (16 - bits);
+ *val = val16;
+ mutex_unlock(&indio_dev->mlock);
+ return IIO_VAL_INT;
+ case (1 << IIO_CHAN_INFO_PEAK_SEPARATE):
+ bits = 10;
+ mutex_lock(&indio_dev->mlock);
+ addr = adis16240_addresses[chan->address][2];
+ ret = adis16240_spi_read_reg_16(indio_dev, addr, &val16);
+ if (ret) {
+ mutex_unlock(&indio_dev->mlock);
+ return ret;
+ }
+ val16 &= (1 << bits) - 1;
+ val16 = (s16)(val16 << (16 - bits)) >> (16 - bits);
+ *val = val16;
+ mutex_unlock(&indio_dev->mlock);
+ return IIO_VAL_INT;
+ }
+ return -EINVAL;
+}
+
+static int adis16240_write_raw(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ int val,
+ int val2,
+ long mask)
+{
+ int bits = 10;
+ s16 val16;
+ u8 addr;
+ switch (mask) {
+ case (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE):
+ val16 = val & ((1 << bits) - 1);
+ addr = adis16240_addresses[chan->address][1];
+ return adis16240_spi_write_reg_16(indio_dev, addr, val16);
+ }
+ return -EINVAL;
+}
+
+static struct iio_chan_spec adis16240_channels[] = {
+ IIO_CHAN(IIO_IN, 0, 1, 0, "supply", 0, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SEPARATE),
+ in_supply, ADIS16240_SCAN_SUPPLY,
+ IIO_ST('u', 10, 16, 0), 0),
+ IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 1, 0,
+ 0,
+ in_aux, ADIS16240_SCAN_AUX_ADC,
+ IIO_ST('u', 10, 16, 0), 0),
+ IIO_CHAN(IIO_ACCEL, 1, 0, 0, NULL, 0, IIO_MOD_X,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED) |
+ (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE),
+ accel_x, ADIS16240_SCAN_ACC_X,
+ IIO_ST('s', 10, 16, 0), 0),
+ IIO_CHAN(IIO_ACCEL, 1, 0, 0, NULL, 0, IIO_MOD_Y,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED) |
+ (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE),
+ accel_y, ADIS16240_SCAN_ACC_Y,
+ IIO_ST('s', 10, 16, 0), 0),
+ IIO_CHAN(IIO_ACCEL, 1, 0, 0, NULL, 0, IIO_MOD_Z,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED) |
+ (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE),
+ accel_z, ADIS16240_SCAN_ACC_Z,
+ IIO_ST('s', 10, 16, 0), 0),
+ IIO_CHAN(IIO_TEMP, 0, 1, 0, NULL, 0, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SEPARATE),
+ temp, ADIS16240_SCAN_TEMP,
+ IIO_ST('u', 10, 16, 0), 0),
+ IIO_CHAN_SOFT_TIMESTAMP(6)
};
static struct attribute *adis16240_attributes[] = {
- &iio_dev_attr_in0_supply_raw.dev_attr.attr,
- &iio_const_attr_in0_supply_scale.dev_attr.attr,
- &iio_dev_attr_in1_raw.dev_attr.attr,
- &iio_const_attr_accel_scale.dev_attr.attr,
- &iio_const_attr_accel_peak_scale.dev_attr.attr,
- &iio_dev_attr_accel_x_raw.dev_attr.attr,
- &iio_dev_attr_accel_x_calibbias.dev_attr.attr,
- &iio_dev_attr_accel_x_peak_raw.dev_attr.attr,
- &iio_dev_attr_accel_y_raw.dev_attr.attr,
- &iio_dev_attr_accel_y_calibbias.dev_attr.attr,
- &iio_dev_attr_accel_y_peak_raw.dev_attr.attr,
- &iio_dev_attr_accel_z_raw.dev_attr.attr,
- &iio_dev_attr_accel_z_calibbias.dev_attr.attr,
- &iio_dev_attr_accel_z_peak_raw.dev_attr.attr,
&iio_dev_attr_accel_xyz_squared_peak_raw.dev_attr.attr,
- &iio_dev_attr_temp_raw.dev_attr.attr,
- &iio_const_attr_temp_scale.dev_attr.attr,
&iio_const_attr_sampling_frequency_available.dev_attr.attr,
&iio_dev_attr_reset.dev_attr.attr,
- &iio_const_attr_name.dev_attr.attr,
NULL
};
@@ -460,6 +507,13 @@
.attrs = adis16240_attributes,
};
+static const struct iio_info adis16240_info = {
+ .attrs = &adis16240_attribute_group,
+ .read_raw = &adis16240_read_raw,
+ .write_raw = &adis16240_write_raw,
+ .driver_module = THIS_MODULE,
+};
+
static int __devinit adis16240_probe(struct spi_device *spi)
{
int ret, regdone = 0;
@@ -485,18 +539,18 @@
st->us = spi;
mutex_init(&st->buf_lock);
/* setup the industrialio driver allocated elements */
- st->indio_dev = iio_allocate_device();
+ st->indio_dev = iio_allocate_device(0);
if (st->indio_dev == NULL) {
ret = -ENOMEM;
goto error_free_tx;
}
+ st->indio_dev->name = spi->dev.driver->name;
st->indio_dev->dev.parent = &spi->dev;
- st->indio_dev->num_interrupt_lines = 1;
- st->indio_dev->event_attrs = &adis16240_event_attribute_group;
- st->indio_dev->attrs = &adis16240_attribute_group;
+ st->indio_dev->info = &adis16240_info;
+ st->indio_dev->channels = adis16240_channels;
+ st->indio_dev->num_channels = ARRAY_SIZE(adis16240_channels);
st->indio_dev->dev_data = (void *)(st);
- st->indio_dev->driver_module = THIS_MODULE;
st->indio_dev->modes = INDIO_DIRECT_MODE;
ret = adis16240_configure_ring(st->indio_dev);
@@ -508,37 +562,28 @@
goto error_unreg_ring_funcs;
regdone = 1;
- ret = iio_ring_buffer_register(st->indio_dev->ring, 0);
+ ret = iio_ring_buffer_register_ex(st->indio_dev->ring, 0,
+ adis16240_channels,
+ ARRAY_SIZE(adis16240_channels));
if (ret) {
printk(KERN_ERR "failed to initialize the ring\n");
goto error_unreg_ring_funcs;
}
if (spi->irq) {
- ret = iio_register_interrupt_line(spi->irq,
- st->indio_dev,
- 0,
- IRQF_TRIGGER_RISING,
- "adis16240");
- if (ret)
- goto error_uninitialize_ring;
-
ret = adis16240_probe_trigger(st->indio_dev);
if (ret)
- goto error_unregister_line;
+ goto error_uninitialize_ring;
}
/* Get the device into a sane initial state */
- ret = adis16240_initial_setup(st);
+ ret = adis16240_initial_setup(st->indio_dev);
if (ret)
goto error_remove_trigger;
return 0;
error_remove_trigger:
adis16240_remove_trigger(st->indio_dev);
-error_unregister_line:
- if (spi->irq)
- iio_unregister_interrupt_line(st->indio_dev, 0);
error_uninitialize_ring:
iio_ring_buffer_unregister(st->indio_dev->ring);
error_unreg_ring_funcs:
@@ -566,9 +611,6 @@
flush_scheduled_work();
adis16240_remove_trigger(indio_dev);
- if (spi->irq)
- iio_unregister_interrupt_line(indio_dev, 0);
-
iio_ring_buffer_unregister(indio_dev->ring);
iio_device_unregister(indio_dev);
adis16240_unconfigure_ring(indio_dev);
diff --git a/drivers/staging/iio/accel/adis16240_ring.c b/drivers/staging/iio/accel/adis16240_ring.c
index f882e9c..0c6d781 100644
--- a/drivers/staging/iio/accel/adis16240_ring.c
+++ b/drivers/staging/iio/accel/adis16240_ring.c
@@ -17,59 +17,6 @@
#include "../trigger.h"
#include "adis16240.h"
-static IIO_SCAN_EL_C(in_supply, ADIS16240_SCAN_SUPPLY,
- ADIS16240_SUPPLY_OUT, NULL);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(in_supply, u, 10, 16);
-static IIO_SCAN_EL_C(accel_x, ADIS16240_SCAN_ACC_X, ADIS16240_XACCL_OUT, NULL);
-static IIO_SCAN_EL_C(accel_y, ADIS16240_SCAN_ACC_Y, ADIS16240_YACCL_OUT, NULL);
-static IIO_SCAN_EL_C(accel_z, ADIS16240_SCAN_ACC_Z, ADIS16240_ZACCL_OUT, NULL);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(accel, s, 10, 16);
-static IIO_SCAN_EL_C(in0, ADIS16240_SCAN_AUX_ADC, ADIS16240_AUX_ADC, NULL);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(in0, u, 10, 16);
-static IIO_SCAN_EL_C(temp, ADIS16240_SCAN_TEMP, ADIS16240_TEMP_OUT, NULL);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(temp, u, 10, 16);
-static IIO_SCAN_EL_TIMESTAMP(6);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(timestamp, s, 64, 64);
-
-static struct attribute *adis16240_scan_el_attrs[] = {
- &iio_scan_el_in_supply.dev_attr.attr,
- &iio_const_attr_in_supply_index.dev_attr.attr,
- &iio_const_attr_in_supply_type.dev_attr.attr,
- &iio_scan_el_accel_x.dev_attr.attr,
- &iio_const_attr_accel_x_index.dev_attr.attr,
- &iio_scan_el_accel_y.dev_attr.attr,
- &iio_const_attr_accel_y_index.dev_attr.attr,
- &iio_scan_el_accel_z.dev_attr.attr,
- &iio_const_attr_accel_z_index.dev_attr.attr,
- &iio_const_attr_accel_type.dev_attr.attr,
- &iio_scan_el_in0.dev_attr.attr,
- &iio_const_attr_in0_index.dev_attr.attr,
- &iio_const_attr_in0_type.dev_attr.attr,
- &iio_scan_el_temp.dev_attr.attr,
- &iio_const_attr_temp_index.dev_attr.attr,
- &iio_const_attr_temp_type.dev_attr.attr,
- &iio_scan_el_timestamp.dev_attr.attr,
- &iio_const_attr_timestamp_index.dev_attr.attr,
- &iio_const_attr_timestamp_type.dev_attr.attr,
- NULL,
-};
-
-static struct attribute_group adis16240_scan_el_group = {
- .attrs = adis16240_scan_el_attrs,
- .name = "scan_elements",
-};
-
-/**
- * adis16240_poll_func_th() top half interrupt handler called by trigger
- * @private_data: iio_dev
- **/
-static void adis16240_poll_func_th(struct iio_dev *indio_dev, s64 time)
-{
- struct adis16240_state *st = iio_dev_get_devdata(indio_dev);
- st->last_timestamp = time;
- schedule_work(&st->work_trigger_to_ring);
-}
-
/**
* adis16240_read_ring_data() read data registers which will be placed into ring
* @dev: device associated with child of actual device (iio_dev or iio_trig)
@@ -112,56 +59,56 @@
return ret;
}
-
-static void adis16240_trigger_bh_to_ring(struct work_struct *work_s)
+static irqreturn_t adis16240_trigger_handler(int irq, void *p)
{
- struct adis16240_state *st
- = container_of(work_s, struct adis16240_state,
- work_trigger_to_ring);
- struct iio_ring_buffer *ring = st->indio_dev->ring;
+ struct iio_poll_func *pf = p;
+ struct iio_dev *indio_dev = pf->private_data;
+ struct adis16240_state *st = iio_dev_get_devdata(indio_dev);
+ struct iio_ring_buffer *ring = indio_dev->ring;
int i = 0;
s16 *data;
- size_t datasize = ring->access.get_bytes_per_datum(ring);
+ size_t datasize = ring->access->get_bytes_per_datum(ring);
- data = kmalloc(datasize , GFP_KERNEL);
+ data = kmalloc(datasize, GFP_KERNEL);
if (data == NULL) {
dev_err(&st->us->dev, "memory alloc failed in ring bh");
- return;
+ return -ENOMEM;
}
- if (ring->scan_count)
- if (adis16240_read_ring_data(&st->indio_dev->dev, st->rx) >= 0)
- for (; i < ring->scan_count; i++)
- data[i] = be16_to_cpup(
- (__be16 *)&(st->rx[i*2]));
+ if (ring->scan_count &&
+ adis16240_read_ring_data(&st->indio_dev->dev, st->rx) >= 0)
+ for (; i < ring->scan_count; i++)
+ data[i] = be16_to_cpup((__be16 *)&(st->rx[i*2]));
/* Guaranteed to be aligned with 8 byte boundary */
if (ring->scan_timestamp)
- *((s64 *)(data + ((i + 3)/4)*4)) = st->last_timestamp;
+ *((s64 *)(data + ((i + 3)/4)*4)) = pf->timestamp;
- ring->access.store_to(ring,
- (u8 *)data,
- st->last_timestamp);
+ ring->access->store_to(ring, (u8 *)data, pf->timestamp);
iio_trigger_notify_done(st->indio_dev->trig);
kfree(data);
- return;
+ return IRQ_HANDLED;
}
void adis16240_unconfigure_ring(struct iio_dev *indio_dev)
{
- kfree(indio_dev->pollfunc);
+ iio_dealloc_pollfunc(indio_dev->pollfunc);
iio_sw_rb_free(indio_dev->ring);
}
+static const struct iio_ring_setup_ops adis16240_ring_setup_ops = {
+ .preenable = &iio_sw_ring_preenable,
+ .postenable = &iio_triggered_ring_postenable,
+ .predisable = &iio_triggered_ring_predisable,
+};
+
int adis16240_configure_ring(struct iio_dev *indio_dev)
{
int ret = 0;
- struct adis16240_state *st = indio_dev->dev_data;
struct iio_ring_buffer *ring;
- INIT_WORK(&st->work_trigger_to_ring, adis16240_trigger_bh_to_ring);
ring = iio_sw_rb_allocate(indio_dev);
if (!ring) {
@@ -170,26 +117,31 @@
}
indio_dev->ring = ring;
/* Effectively select the ring buffer implementation */
- iio_ring_sw_register_funcs(&ring->access);
+ ring->access = &ring_sw_access_funcs;
ring->bpe = 2;
- ring->scan_el_attrs = &adis16240_scan_el_group;
ring->scan_timestamp = true;
- ring->preenable = &iio_sw_ring_preenable;
- ring->postenable = &iio_triggered_ring_postenable;
- ring->predisable = &iio_triggered_ring_predisable;
+ ring->setup_ops = &adis16240_ring_setup_ops;
ring->owner = THIS_MODULE;
/* Set default scan mode */
- iio_scan_mask_set(ring, iio_scan_el_in_supply.number);
- iio_scan_mask_set(ring, iio_scan_el_accel_x.number);
- iio_scan_mask_set(ring, iio_scan_el_accel_y.number);
- iio_scan_mask_set(ring, iio_scan_el_accel_z.number);
- iio_scan_mask_set(ring, iio_scan_el_temp.number);
- iio_scan_mask_set(ring, iio_scan_el_in0.number);
+ iio_scan_mask_set(ring, ADIS16240_SCAN_SUPPLY);
+ iio_scan_mask_set(ring, ADIS16240_SCAN_ACC_X);
+ iio_scan_mask_set(ring, ADIS16240_SCAN_ACC_Y);
+ iio_scan_mask_set(ring, ADIS16240_SCAN_ACC_Z);
+ iio_scan_mask_set(ring, ADIS16240_SCAN_AUX_ADC);
+ iio_scan_mask_set(ring, ADIS16240_SCAN_TEMP);
- ret = iio_alloc_pollfunc(indio_dev, NULL, &adis16240_poll_func_th);
- if (ret)
+ indio_dev->pollfunc = iio_alloc_pollfunc(&iio_pollfunc_store_time,
+ &adis16240_trigger_handler,
+ IRQF_ONESHOT,
+ indio_dev,
+ "%s_consumer%d",
+ indio_dev->name,
+ indio_dev->id);
+ if (indio_dev->pollfunc == NULL) {
+ ret = -ENOMEM;
goto error_iio_sw_rb_free;
+ }
indio_dev->modes |= INDIO_RING_TRIGGERED;
return 0;
@@ -198,4 +150,3 @@
iio_sw_rb_free(indio_dev->ring);
return ret;
}
-
diff --git a/drivers/staging/iio/accel/adis16240_trigger.c b/drivers/staging/iio/accel/adis16240_trigger.c
index 6cb8681..ece3ca8 100644
--- a/drivers/staging/iio/accel/adis16240_trigger.c
+++ b/drivers/staging/iio/accel/adis16240_trigger.c
@@ -15,32 +15,12 @@
/**
* adis16240_data_rdy_trig_poll() the event handler for the data rdy trig
**/
-static int adis16240_data_rdy_trig_poll(struct iio_dev *dev_info,
- int index,
- s64 timestamp,
- int no_test)
+static irqreturn_t adis16240_data_rdy_trig_poll(int irq, void *trig)
{
- struct adis16240_state *st = iio_dev_get_devdata(dev_info);
- struct iio_trigger *trig = st->trig;
-
- iio_trigger_poll(trig, timestamp);
-
+ iio_trigger_poll(trig, iio_get_time_ns());
return IRQ_HANDLED;
}
-IIO_EVENT_SH(data_rdy_trig, &adis16240_data_rdy_trig_poll);
-
-static IIO_TRIGGER_NAME_ATTR;
-
-static struct attribute *adis16240_trigger_attrs[] = {
- &dev_attr_name.attr,
- NULL,
-};
-
-static const struct attribute_group adis16240_trigger_attr_group = {
- .attrs = adis16240_trigger_attrs,
-};
-
/**
* adis16240_data_rdy_trigger_set_state() set datardy interrupt state
**/
@@ -49,31 +29,9 @@
{
struct adis16240_state *st = trig->private_data;
struct iio_dev *indio_dev = st->indio_dev;
- int ret = 0;
dev_dbg(&indio_dev->dev, "%s (%d)\n", __func__, state);
- ret = adis16240_set_irq(&st->indio_dev->dev, state);
- if (state == false) {
- iio_remove_event_from_list(&iio_event_data_rdy_trig,
- &indio_dev->interrupts[0]
- ->ev_list);
- flush_scheduled_work();
- } else {
- iio_add_event_to_list(&iio_event_data_rdy_trig,
- &indio_dev->interrupts[0]->ev_list);
- }
- return ret;
-}
-
-/**
- * adis16240_trig_try_reen() try renabling irq for data rdy trigger
- * @trig: the datardy trigger
- **/
-static int adis16240_trig_try_reen(struct iio_trigger *trig)
-{
- struct adis16240_state *st = trig->private_data;
- enable_irq(st->us->irq);
- return 0;
+ return adis16240_set_irq(st->indio_dev, state);
}
int adis16240_probe_trigger(struct iio_dev *indio_dev)
@@ -81,34 +39,38 @@
int ret;
struct adis16240_state *st = indio_dev->dev_data;
- st->trig = iio_allocate_trigger();
- st->trig->name = kasprintf(GFP_KERNEL,
- "adis16240-dev%d",
- indio_dev->id);
- if (!st->trig->name) {
+ st->trig = iio_allocate_trigger("adis16240-dev%d", indio_dev->id);
+ if (st->trig == NULL) {
ret = -ENOMEM;
- goto error_free_trig;
+ goto error_ret;
}
+
+ ret = request_irq(st->us->irq,
+ adis16240_data_rdy_trig_poll,
+ IRQF_TRIGGER_RISING,
+ "adis16240",
+ st->trig);
+ if (ret)
+ goto error_free_trig;
+
st->trig->dev.parent = &st->us->dev;
st->trig->owner = THIS_MODULE;
st->trig->private_data = st;
st->trig->set_trigger_state = &adis16240_data_rdy_trigger_set_state;
- st->trig->try_reenable = &adis16240_trig_try_reen;
- st->trig->control_attrs = &adis16240_trigger_attr_group;
ret = iio_trigger_register(st->trig);
/* select default trigger */
indio_dev->trig = st->trig;
if (ret)
- goto error_free_trig_name;
+ goto error_free_irq;
return 0;
-error_free_trig_name:
- kfree(st->trig->name);
+error_free_irq:
+ free_irq(st->us->irq, st->trig);
error_free_trig:
iio_free_trigger(st->trig);
-
+error_ret:
return ret;
}
@@ -117,6 +79,6 @@
struct adis16240_state *state = indio_dev->dev_data;
iio_trigger_unregister(state->trig);
- kfree(state->trig->name);
+ free_irq(state->us->irq, state->trig);
iio_free_trigger(state->trig);
}
diff --git a/drivers/staging/iio/accel/kxsd9.c b/drivers/staging/iio/accel/kxsd9.c
index 79f5795..973156e 100644
--- a/drivers/staging/iio/accel/kxsd9.c
+++ b/drivers/staging/iio/accel/kxsd9.c
@@ -301,6 +301,11 @@
};
+static const struct iio_info kxsd9_info = {
+ .attrs = &kxsd9_attribute_group,
+ .driver_module = THIS_MODULE,
+};
+
static int __devinit kxsd9_probe(struct spi_device *spi)
{
@@ -329,19 +334,14 @@
st->us = spi;
mutex_init(&st->buf_lock);
- st->indio_dev = iio_allocate_device();
+ st->indio_dev = iio_allocate_device(0);
if (st->indio_dev == NULL) {
ret = -ENOMEM;
goto error_free_tx;
}
st->indio_dev->dev.parent = &spi->dev;
- /* for now */
- st->indio_dev->num_interrupt_lines = 0;
- st->indio_dev->event_attrs = NULL;
-
- st->indio_dev->attrs = &kxsd9_attribute_group;
+ st->indio_dev->info = &kxsd9_info;
st->indio_dev->dev_data = (void *)(st);
- st->indio_dev->driver_module = THIS_MODULE;
st->indio_dev->modes = INDIO_DIRECT_MODE;
ret = iio_device_register(st->indio_dev);
diff --git a/drivers/staging/iio/accel/lis3l02dq.h b/drivers/staging/iio/accel/lis3l02dq.h
index 1140218..18b23ac 100644
--- a/drivers/staging/iio/accel/lis3l02dq.h
+++ b/drivers/staging/iio/accel/lis3l02dq.h
@@ -148,38 +148,31 @@
#define LIS3L02DQ_MAX_RX 12
/**
* struct lis3l02dq_state - device instance specific data
- * @helper: data and func pointer allowing generic functions
* @us: actual spi_device
- * @work_thresh: bh for threshold events
- * @thresh_timestamp: timestamp for threshold interrupts.
- * @inter: used to check if new interrupt has been triggered
* @trig: data ready trigger registered with iio
* @tx: transmit buffer
* @rx: receive buffer
* @buf_lock: mutex to protect tx and rx
**/
struct lis3l02dq_state {
- struct iio_sw_ring_helper_state help;
struct spi_device *us;
- struct work_struct work_thresh;
- s64 thresh_timestamp;
- bool inter;
struct iio_trigger *trig;
- u8 *tx;
- u8 *rx;
struct mutex buf_lock;
+ bool trigger_on;
+
+ u8 tx[LIS3L02DQ_MAX_RX] ____cacheline_aligned;
+ u8 rx[LIS3L02DQ_MAX_RX] ____cacheline_aligned;
};
-#define lis3l02dq_h_to_s(_h) \
- container_of(_h, struct lis3l02dq_state, help)
-
-int lis3l02dq_spi_read_reg_8(struct device *dev,
+int lis3l02dq_spi_read_reg_8(struct iio_dev *indio_dev,
u8 reg_address,
u8 *val);
-int lis3l02dq_spi_write_reg_8(struct device *dev,
+int lis3l02dq_spi_write_reg_8(struct iio_dev *indio_dev,
u8 reg_address,
- u8 *val);
+ u8 val);
+
+int lis3l02dq_disable_all_events(struct iio_dev *indio_dev);
#ifdef CONFIG_IIO_RING_BUFFER
/* At the moment triggers are only used for ring buffer
@@ -188,9 +181,9 @@
void lis3l02dq_remove_trigger(struct iio_dev *indio_dev);
int lis3l02dq_probe_trigger(struct iio_dev *indio_dev);
-ssize_t lis3l02dq_read_accel_from_ring(struct device *dev,
- struct device_attribute *attr,
- char *buf);
+ssize_t lis3l02dq_read_accel_from_ring(struct iio_ring_buffer *ring,
+ int index,
+ int *val);
int lis3l02dq_configure_ring(struct iio_dev *indio_dev);
@@ -199,14 +192,18 @@
#ifdef CONFIG_LIS3L02DQ_BUF_RING_SW
#define lis3l02dq_free_buf iio_sw_rb_free
#define lis3l02dq_alloc_buf iio_sw_rb_allocate
-#define lis3l02dq_register_buf_funcs iio_ring_sw_register_funcs
+#define lis3l02dq_access_funcs ring_sw_access_funcs
#endif
#ifdef CONFIG_LIS3L02DQ_BUF_KFIFO
#define lis3l02dq_free_buf iio_kfifo_free
#define lis3l02dq_alloc_buf iio_kfifo_allocate
-#define lis3l02dq_register_buf_funcs iio_kfifo_register_funcs
+#define lis3l02dq_access_funcs kfifo_access_funcs
#endif
+irqreturn_t lis3l02dq_data_rdy_trig_poll(int irq, void *private);
+#define lis3l02dq_th lis3l02dq_data_rdy_trig_poll
+
#else /* CONFIG_IIO_RING_BUFFER */
+#define lis3l02dq_th lis3l02dq_noring
static inline void lis3l02dq_remove_trigger(struct iio_dev *indio_dev)
{
@@ -215,11 +212,10 @@
{
return 0;
}
-
static inline ssize_t
-lis3l02dq_read_accel_from_ring(struct device *dev,
- struct device_attribute *attr,
- char *buf)
+lis3l02dq_read_accel_from_ring(struct iio_ring_buffer *ring,
+ int index,
+ int *val)
{
return 0;
}
diff --git a/drivers/staging/iio/accel/lis3l02dq_core.c b/drivers/staging/iio/accel/lis3l02dq_core.c
index 3067f96..ba5bc67 100644
--- a/drivers/staging/iio/accel/lis3l02dq_core.c
+++ b/drivers/staging/iio/accel/lis3l02dq_core.c
@@ -15,20 +15,16 @@
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/gpio.h>
-#include <linux/workqueue.h>
#include <linux/mutex.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/spi/spi.h>
#include <linux/slab.h>
-
#include <linux/sysfs.h>
-#include <linux/list.h>
#include "../iio.h"
#include "../sysfs.h"
#include "../ring_generic.h"
-#include "../ring_sw.h"
#include "accel.h"
@@ -38,27 +34,31 @@
* It's in the likely to be added comment at the top of spi.h.
* This means that use cannot be made of spi_write etc.
*/
+/* direct copy of the irq_default_primary_handler */
+#ifndef CONFIG_IIO_RING_BUFFER
+static irqreturn_t lis3l02dq_noring(int irq, void *private)
+{
+ return IRQ_WAKE_THREAD;
+}
+#endif
/**
* lis3l02dq_spi_read_reg_8() - read single byte from a single register
- * @dev: device asosciated with child of actual device (iio_dev or iio_trig)
+ * @indio_dev: iio_dev for this actual device
* @reg_address: the address of the register to be read
* @val: pass back the resulting value
**/
-int lis3l02dq_spi_read_reg_8(struct device *dev, u8 reg_address, u8 *val)
+int lis3l02dq_spi_read_reg_8(struct iio_dev *indio_dev,
+ u8 reg_address, u8 *val)
{
- int ret;
+ struct lis3l02dq_state *st = iio_priv(indio_dev);
struct spi_message msg;
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
- struct iio_sw_ring_helper_state *h = iio_dev_get_devdata(indio_dev);
- struct lis3l02dq_state *st = lis3l02dq_h_to_s(h);
-
+ int ret;
struct spi_transfer xfer = {
.tx_buf = st->tx,
.rx_buf = st->rx,
.bits_per_word = 8,
.len = 2,
- .cs_change = 1,
};
mutex_lock(&st->buf_lock);
@@ -76,34 +76,21 @@
/**
* lis3l02dq_spi_write_reg_8() - write single byte to a register
- * @dev: device associated with child of actual device (iio_dev or iio_trig)
+ * @indio_dev: iio_dev for this device
* @reg_address: the address of the register to be written
* @val: the value to write
**/
-int lis3l02dq_spi_write_reg_8(struct device *dev,
+int lis3l02dq_spi_write_reg_8(struct iio_dev *indio_dev,
u8 reg_address,
- u8 *val)
+ u8 val)
{
int ret;
- struct spi_message msg;
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
- struct iio_sw_ring_helper_state *h
- = iio_dev_get_devdata(indio_dev);
- struct lis3l02dq_state *st = lis3l02dq_h_to_s(h);
- struct spi_transfer xfer = {
- .tx_buf = st->tx,
- .bits_per_word = 8,
- .len = 2,
- .cs_change = 1,
- };
+ struct lis3l02dq_state *st = iio_priv(indio_dev);
mutex_lock(&st->buf_lock);
st->tx[0] = LIS3L02DQ_WRITE_REG(reg_address);
- st->tx[1] = *val;
-
- spi_message_init(&msg);
- spi_message_add_tail(&xfer, &msg);
- ret = spi_sync(st->us, &msg);
+ st->tx[1] = val;
+ ret = spi_write(st->us, st->tx, 2);
mutex_unlock(&st->buf_lock);
return ret;
@@ -111,21 +98,18 @@
/**
* lisl302dq_spi_write_reg_s16() - write 2 bytes to a pair of registers
- * @dev: device associated with child of actual device (iio_dev or iio_trig)
- * @reg_address: the address of the lower of the two registers. Second register
- * is assumed to have address one greater.
- * @val: value to be written
+ * @indio_dev: iio_dev for this device
+ * @lower_reg_address: the address of the lower of the two registers.
+ * Second register is assumed to have address one greater.
+ * @value: value to be written
**/
-static int lis3l02dq_spi_write_reg_s16(struct device *dev,
+static int lis3l02dq_spi_write_reg_s16(struct iio_dev *indio_dev,
u8 lower_reg_address,
s16 value)
{
int ret;
struct spi_message msg;
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
- struct iio_sw_ring_helper_state *h
- = iio_dev_get_devdata(indio_dev);
- struct lis3l02dq_state *st = lis3l02dq_h_to_s(h);
+ struct lis3l02dq_state *st = iio_priv(indio_dev);
struct spi_transfer xfers[] = { {
.tx_buf = st->tx,
.bits_per_word = 8,
@@ -135,7 +119,6 @@
.tx_buf = st->tx + 2,
.bits_per_word = 8,
.len = 2,
- .cs_change = 1,
},
};
@@ -154,23 +137,15 @@
return ret;
}
-/**
- * lisl302dq_spi_read_reg_s16() - write 2 bytes to a pair of registers
- * @dev: device associated with child of actual device (iio_dev or iio_trig)
- * @reg_address: the address of the lower of the two registers. Second register
- * is assumed to have address one greater.
- * @val: somewhere to pass back the value read
- **/
-static int lis3l02dq_spi_read_reg_s16(struct device *dev,
- u8 lower_reg_address,
- s16 *val)
+static int lis3l02dq_read_reg_s16(struct iio_dev *indio_dev,
+ u8 lower_reg_address,
+ int *val)
{
+ struct lis3l02dq_state *st = iio_priv(indio_dev);
+
struct spi_message msg;
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
- struct iio_sw_ring_helper_state *h
- = iio_dev_get_devdata(indio_dev);
- struct lis3l02dq_state *st = lis3l02dq_h_to_s(h);
int ret;
+ s16 tempval;
struct spi_transfer xfers[] = { {
.tx_buf = st->tx,
.rx_buf = st->rx,
@@ -182,15 +157,13 @@
.rx_buf = st->rx + 2,
.bits_per_word = 8,
.len = 2,
- .cs_change = 1,
-
},
};
mutex_lock(&st->buf_lock);
st->tx[0] = LIS3L02DQ_READ_REG(lower_reg_address);
st->tx[1] = 0;
- st->tx[2] = LIS3L02DQ_READ_REG(lower_reg_address+1);
+ st->tx[2] = LIS3L02DQ_READ_REG(lower_reg_address + 1);
st->tx[3] = 0;
spi_message_init(&msg);
@@ -201,144 +174,135 @@
dev_err(&st->us->dev, "problem when reading 16 bit register");
goto error_ret;
}
- *val = (s16)(st->rx[1]) | ((s16)(st->rx[3]) << 8);
+ tempval = (s16)(st->rx[1]) | ((s16)(st->rx[3]) << 8);
+ *val = tempval;
error_ret:
mutex_unlock(&st->buf_lock);
return ret;
}
-/**
- * lis3l02dq_read_signed() - attribute function used for 8 bit signed values
- * @dev: the child device associated with the iio_dev or iio_trigger
- * @attr: the attribute being processed
- * @buf: buffer into which put the output string
- **/
-static ssize_t lis3l02dq_read_signed(struct device *dev,
- struct device_attribute *attr,
- char *buf)
+enum lis3l02dq_rm_ind {
+ LIS3L02DQ_ACCEL,
+ LIS3L02DQ_GAIN,
+ LIS3L02DQ_BIAS,
+};
+
+static u8 lis3l02dq_axis_map[3][3] = {
+ [LIS3L02DQ_ACCEL] = { LIS3L02DQ_REG_OUT_X_L_ADDR,
+ LIS3L02DQ_REG_OUT_Y_L_ADDR,
+ LIS3L02DQ_REG_OUT_Z_L_ADDR },
+ [LIS3L02DQ_GAIN] = { LIS3L02DQ_REG_GAIN_X_ADDR,
+ LIS3L02DQ_REG_GAIN_Y_ADDR,
+ LIS3L02DQ_REG_GAIN_Z_ADDR },
+ [LIS3L02DQ_BIAS] = { LIS3L02DQ_REG_OFFSET_X_ADDR,
+ LIS3L02DQ_REG_OFFSET_Y_ADDR,
+ LIS3L02DQ_REG_OFFSET_Z_ADDR }
+};
+
+static int lis3l02dq_read_thresh(struct iio_dev *indio_dev,
+ int e,
+ int *val)
{
- int ret;
- s8 val;
- struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
-
- ret = lis3l02dq_spi_read_reg_8(dev, this_attr->address, (u8 *)&val);
-
- return ret ? ret : sprintf(buf, "%d\n", val);
+ return lis3l02dq_read_reg_s16(indio_dev, LIS3L02DQ_REG_THS_L_ADDR, val);
}
-static ssize_t lis3l02dq_read_unsigned(struct device *dev,
- struct device_attribute *attr,
- char *buf)
+static int lis3l02dq_write_thresh(struct iio_dev *indio_dev,
+ int event_code,
+ int val)
{
- int ret;
- u8 val;
- struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
-
- ret = lis3l02dq_spi_read_reg_8(dev, this_attr->address, &val);
-
- return ret ? ret : sprintf(buf, "%d\n", val);
+ u16 value = val;
+ return lis3l02dq_spi_write_reg_s16(indio_dev,
+ LIS3L02DQ_REG_THS_L_ADDR,
+ value);
}
-static ssize_t lis3l02dq_write_signed(struct device *dev,
- struct device_attribute *attr,
- const char *buf,
- size_t len)
+static int lis3l02dq_write_raw(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ int val,
+ int val2,
+ long mask)
{
- long valin;
- s8 val;
- int ret;
- struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
-
- ret = strict_strtol(buf, 10, &valin);
- if (ret)
- goto error_ret;
- val = valin;
- ret = lis3l02dq_spi_write_reg_8(dev, this_attr->address, (u8 *)&val);
-
-error_ret:
- return ret ? ret : len;
-}
-
-static ssize_t lis3l02dq_write_unsigned(struct device *dev,
- struct device_attribute *attr,
- const char *buf,
- size_t len)
-{
- int ret;
- ulong valin;
- u8 val;
- struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
-
- ret = strict_strtoul(buf, 10, &valin);
- if (ret)
- goto err_ret;
- val = valin;
- ret = lis3l02dq_spi_write_reg_8(dev, this_attr->address, &val);
-
-err_ret:
- return ret ? ret : len;
-}
-
-static ssize_t lis3l02dq_read_16bit_signed(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- int ret;
- s16 val = 0;
- struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
-
- ret = lis3l02dq_spi_read_reg_s16(dev, this_attr->address, &val);
-
- if (ret)
- return ret;
-
- return sprintf(buf, "%d\n", val);
-}
-
-static ssize_t lis3l02dq_read_accel(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
- ssize_t ret;
-
- /* Take the iio_dev status lock */
- mutex_lock(&indio_dev->mlock);
- if (indio_dev->currentmode == INDIO_RING_TRIGGERED)
- ret = lis3l02dq_read_accel_from_ring(dev, attr, buf);
- else
- ret = lis3l02dq_read_16bit_signed(dev, attr, buf);
- mutex_unlock(&indio_dev->mlock);
-
+ int ret = -EINVAL, reg;
+ u8 uval;
+ s8 sval;
+ switch (mask) {
+ case (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE):
+ if (val > 255 || val < -256)
+ return -EINVAL;
+ sval = val;
+ reg = lis3l02dq_axis_map[LIS3L02DQ_BIAS][chan->address];
+ ret = lis3l02dq_spi_write_reg_8(indio_dev, reg, sval);
+ break;
+ case (1 << IIO_CHAN_INFO_CALIBSCALE_SEPARATE):
+ if (val & ~0xFF)
+ return -EINVAL;
+ uval = val;
+ reg = lis3l02dq_axis_map[LIS3L02DQ_GAIN][chan->address];
+ ret = lis3l02dq_spi_write_reg_8(indio_dev, reg, uval);
+ break;
+ }
return ret;
}
-static ssize_t lis3l02dq_write_16bit_signed(struct device *dev,
- struct device_attribute *attr,
- const char *buf,
- size_t len)
+static int lis3l02dq_read_raw(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ int *val,
+ int *val2,
+ long mask)
{
- struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
- int ret;
- long val;
+ u8 utemp;
+ s8 stemp;
+ ssize_t ret = 0;
+ u8 reg;
- ret = strict_strtol(buf, 10, &val);
- if (ret)
- goto error_ret;
- ret = lis3l02dq_spi_write_reg_s16(dev, this_attr->address, val);
+ switch (mask) {
+ case 0:
+ /* Take the iio_dev status lock */
+ mutex_lock(&indio_dev->mlock);
+ if (indio_dev->currentmode == INDIO_RING_TRIGGERED)
+ ret = lis3l02dq_read_accel_from_ring(indio_dev->ring,
+ chan->scan_index,
+ val);
+ else {
+ reg = lis3l02dq_axis_map
+ [LIS3L02DQ_ACCEL][chan->address];
+ ret = lis3l02dq_read_reg_s16(indio_dev, reg, val);
+ }
+ mutex_unlock(&indio_dev->mlock);
+ return IIO_VAL_INT;
+ case (1 << IIO_CHAN_INFO_SCALE_SHARED):
+ *val = 0;
+ *val2 = 9580;
+ return IIO_VAL_INT_PLUS_MICRO;
+ case (1 << IIO_CHAN_INFO_CALIBSCALE_SEPARATE):
+ reg = lis3l02dq_axis_map[LIS3L02DQ_GAIN][chan->address];
+ ret = lis3l02dq_spi_read_reg_8(indio_dev, reg, &utemp);
+ if (ret)
+ goto error_ret;
+ /* to match with what previous code does */
+ *val = utemp;
+ return IIO_VAL_INT;
+ case (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE):
+ reg = lis3l02dq_axis_map[LIS3L02DQ_BIAS][chan->address];
+ ret = lis3l02dq_spi_read_reg_8(indio_dev, reg, (u8 *)&stemp);
+ /* to match with what previous code does */
+ *val = stemp;
+ return IIO_VAL_INT;
+ }
error_ret:
- return ret ? ret : len;
+ return ret;
}
static ssize_t lis3l02dq_read_frequency(struct device *dev,
struct device_attribute *attr,
char *buf)
{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
int ret, len = 0;
s8 t;
- ret = lis3l02dq_spi_read_reg_8(dev,
+ ret = lis3l02dq_spi_read_reg_8(indio_dev,
LIS3L02DQ_REG_CTRL_1_ADDR,
(u8 *)&t);
if (ret)
@@ -376,7 +340,7 @@
return ret;
mutex_lock(&indio_dev->mlock);
- ret = lis3l02dq_spi_read_reg_8(dev,
+ ret = lis3l02dq_spi_read_reg_8(indio_dev,
LIS3L02DQ_REG_CTRL_1_ADDR,
&t);
if (ret)
@@ -399,11 +363,11 @@
default:
ret = -EINVAL;
goto error_ret_mutex;
- };
+ }
- ret = lis3l02dq_spi_write_reg_8(dev,
+ ret = lis3l02dq_spi_write_reg_8(indio_dev,
LIS3L02DQ_REG_CTRL_1_ADDR,
- &t);
+ t);
error_ret_mutex:
mutex_unlock(&indio_dev->mlock);
@@ -411,8 +375,9 @@
return ret ? ret : len;
}
-static int lis3l02dq_initial_setup(struct lis3l02dq_state *st)
+static int lis3l02dq_initial_setup(struct iio_dev *indio_dev)
{
+ struct lis3l02dq_state *st = iio_priv(indio_dev);
int ret;
u8 val, valtest;
@@ -422,17 +387,17 @@
val = LIS3L02DQ_DEFAULT_CTRL1;
/* Write suitable defaults to ctrl1 */
- ret = lis3l02dq_spi_write_reg_8(&st->help.indio_dev->dev,
+ ret = lis3l02dq_spi_write_reg_8(indio_dev,
LIS3L02DQ_REG_CTRL_1_ADDR,
- &val);
+ val);
if (ret) {
dev_err(&st->us->dev, "problem with setup control register 1");
goto err_ret;
}
/* Repeat as sometimes doesn't work first time?*/
- ret = lis3l02dq_spi_write_reg_8(&st->help.indio_dev->dev,
+ ret = lis3l02dq_spi_write_reg_8(indio_dev,
LIS3L02DQ_REG_CTRL_1_ADDR,
- &val);
+ val);
if (ret) {
dev_err(&st->us->dev, "problem with setup control register 1");
goto err_ret;
@@ -440,28 +405,29 @@
/* Read back to check this has worked acts as loose test of correct
* chip */
- ret = lis3l02dq_spi_read_reg_8(&st->help.indio_dev->dev,
+ ret = lis3l02dq_spi_read_reg_8(indio_dev,
LIS3L02DQ_REG_CTRL_1_ADDR,
&valtest);
if (ret || (valtest != val)) {
- dev_err(&st->help.indio_dev->dev, "device not playing ball");
+ dev_err(&indio_dev->dev,
+ "device not playing ball %d %d\n", valtest, val);
ret = -EINVAL;
goto err_ret;
}
val = LIS3L02DQ_DEFAULT_CTRL2;
- ret = lis3l02dq_spi_write_reg_8(&st->help.indio_dev->dev,
+ ret = lis3l02dq_spi_write_reg_8(indio_dev,
LIS3L02DQ_REG_CTRL_2_ADDR,
- &val);
+ val);
if (ret) {
dev_err(&st->us->dev, "problem with setup control register 2");
goto err_ret;
}
val = LIS3L02DQ_REG_WAKE_UP_CFG_LATCH_SRC;
- ret = lis3l02dq_spi_write_reg_8(&st->help.indio_dev->dev,
+ ret = lis3l02dq_spi_write_reg_8(indio_dev,
LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
- &val);
+ val);
if (ret)
dev_err(&st->us->dev, "problem with interrupt cfg register");
err_ret:
@@ -469,309 +435,215 @@
return ret;
}
-#define LIS3L02DQ_SIGNED_ATTR(name, reg) \
- IIO_DEVICE_ATTR(name, \
- S_IWUSR | S_IRUGO, \
- lis3l02dq_read_signed, \
- lis3l02dq_write_signed, \
- reg);
-
-#define LIS3L02DQ_UNSIGNED_ATTR(name, reg) \
- IIO_DEVICE_ATTR(name, \
- S_IWUSR | S_IRUGO, \
- lis3l02dq_read_unsigned, \
- lis3l02dq_write_unsigned, \
- reg);
-
-static LIS3L02DQ_SIGNED_ATTR(accel_x_calibbias,
- LIS3L02DQ_REG_OFFSET_X_ADDR);
-static LIS3L02DQ_SIGNED_ATTR(accel_y_calibbias,
- LIS3L02DQ_REG_OFFSET_Y_ADDR);
-static LIS3L02DQ_SIGNED_ATTR(accel_z_calibbias,
- LIS3L02DQ_REG_OFFSET_Z_ADDR);
-
-static LIS3L02DQ_UNSIGNED_ATTR(accel_x_calibscale,
- LIS3L02DQ_REG_GAIN_X_ADDR);
-static LIS3L02DQ_UNSIGNED_ATTR(accel_y_calibscale,
- LIS3L02DQ_REG_GAIN_Y_ADDR);
-static LIS3L02DQ_UNSIGNED_ATTR(accel_z_calibscale,
- LIS3L02DQ_REG_GAIN_Z_ADDR);
-
-static IIO_DEVICE_ATTR(accel_raw_mag_value,
- S_IWUSR | S_IRUGO,
- lis3l02dq_read_16bit_signed,
- lis3l02dq_write_16bit_signed,
- LIS3L02DQ_REG_THS_L_ADDR);
-/* RFC The reading method for these will change depending on whether
- * ring buffer capture is in use. Is it worth making these take two
- * functions and let the core handle which to call, or leave as in this
- * driver where it is the drivers problem to manage this?
- */
-
-static IIO_DEV_ATTR_ACCEL_X(lis3l02dq_read_accel,
- LIS3L02DQ_REG_OUT_X_L_ADDR);
-
-static IIO_DEV_ATTR_ACCEL_Y(lis3l02dq_read_accel,
- LIS3L02DQ_REG_OUT_Y_L_ADDR);
-
-static IIO_DEV_ATTR_ACCEL_Z(lis3l02dq_read_accel,
- LIS3L02DQ_REG_OUT_Z_L_ADDR);
-
static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO,
lis3l02dq_read_frequency,
lis3l02dq_write_frequency);
static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("280 560 1120 4480");
-static ssize_t lis3l02dq_read_interrupt_config(struct device *dev,
- struct device_attribute *attr,
- char *buf)
+static irqreturn_t lis3l02dq_event_handler(int irq, void *private)
{
- int ret;
- s8 val;
- struct iio_event_attr *this_attr = to_iio_event_attr(attr);
-
- ret = lis3l02dq_spi_read_reg_8(dev->parent,
- LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
- (u8 *)&val);
-
- return ret ? ret : sprintf(buf, "%d\n", !!(val & this_attr->mask));
-}
-
-static ssize_t lis3l02dq_write_interrupt_config(struct device *dev,
- struct device_attribute *attr,
- const char *buf,
- size_t len)
-{
- struct iio_event_attr *this_attr = to_iio_event_attr(attr);
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
- int ret, currentlyset, changed = 0;
- u8 valold, controlold;
- bool val;
-
- val = !(buf[0] == '0');
-
- mutex_lock(&indio_dev->mlock);
- /* read current value */
- ret = lis3l02dq_spi_read_reg_8(dev->parent,
- LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
- &valold);
- if (ret)
- goto error_mutex_unlock;
-
- /* read current control */
- ret = lis3l02dq_spi_read_reg_8(dev,
- LIS3L02DQ_REG_CTRL_2_ADDR,
- &controlold);
- if (ret)
- goto error_mutex_unlock;
- currentlyset = !!(valold & this_attr->mask);
- if (val == false && currentlyset) {
- valold &= ~this_attr->mask;
- changed = 1;
- iio_remove_event_from_list(this_attr->listel,
- &indio_dev->interrupts[0]
- ->ev_list);
- } else if (val == true && !currentlyset) {
- changed = 1;
- valold |= this_attr->mask;
- iio_add_event_to_list(this_attr->listel,
- &indio_dev->interrupts[0]->ev_list);
- }
-
- if (changed) {
- ret = lis3l02dq_spi_write_reg_8(dev,
- LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
- &valold);
- if (ret)
- goto error_mutex_unlock;
- /* This always enables the interrupt, even if we've remove the
- * last thing using it. For this device we can use the reference
- * count on the handler to tell us if anyone wants the interrupt
- */
- controlold = this_attr->listel->refcount ?
- (controlold | LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT) :
- (controlold & ~LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT);
- ret = lis3l02dq_spi_write_reg_8(dev,
- LIS3L02DQ_REG_CTRL_2_ADDR,
- &controlold);
- if (ret)
- goto error_mutex_unlock;
- }
-error_mutex_unlock:
- mutex_unlock(&indio_dev->mlock);
-
- return ret ? ret : len;
-}
-
-
-static int lis3l02dq_thresh_handler_th(struct iio_dev *indio_dev,
- int index,
- s64 timestamp,
- int no_test)
-{
- struct iio_sw_ring_helper_state *h
- = iio_dev_get_devdata(indio_dev);
- struct lis3l02dq_state *st = lis3l02dq_h_to_s(h);
-
- /* Stash the timestamp somewhere convenient for the bh */
- st->thresh_timestamp = timestamp;
- schedule_work(&st->work_thresh);
-
- return 0;
-}
-
-
-/* Unforunately it appears the interrupt won't clear unless you read from the
- * src register.
- */
-static void lis3l02dq_thresh_handler_bh_no_check(struct work_struct *work_s)
-{
- struct lis3l02dq_state *st
- = container_of(work_s,
- struct lis3l02dq_state, work_thresh);
-
+ struct iio_dev *indio_dev = private;
u8 t;
- lis3l02dq_spi_read_reg_8(&st->help.indio_dev->dev,
+ s64 timestamp = iio_get_time_ns();
+
+ lis3l02dq_spi_read_reg_8(indio_dev,
LIS3L02DQ_REG_WAKE_UP_SRC_ADDR,
&t);
if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Z_HIGH)
- iio_push_event(st->help.indio_dev, 0,
+ iio_push_event(indio_dev, 0,
IIO_MOD_EVENT_CODE(IIO_EV_CLASS_ACCEL,
0,
IIO_EV_MOD_Z,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_RISING),
- st->thresh_timestamp);
+ timestamp);
if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Z_LOW)
- iio_push_event(st->help.indio_dev, 0,
+ iio_push_event(indio_dev, 0,
IIO_MOD_EVENT_CODE(IIO_EV_CLASS_ACCEL,
0,
IIO_EV_MOD_Z,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_FALLING),
- st->thresh_timestamp);
+ timestamp);
if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Y_HIGH)
- iio_push_event(st->help.indio_dev, 0,
+ iio_push_event(indio_dev, 0,
IIO_MOD_EVENT_CODE(IIO_EV_CLASS_ACCEL,
0,
IIO_EV_MOD_Y,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_RISING),
- st->thresh_timestamp);
+ timestamp);
if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_Y_LOW)
- iio_push_event(st->help.indio_dev, 0,
+ iio_push_event(indio_dev, 0,
IIO_MOD_EVENT_CODE(IIO_EV_CLASS_ACCEL,
0,
IIO_EV_MOD_Y,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_FALLING),
- st->thresh_timestamp);
+ timestamp);
if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_X_HIGH)
- iio_push_event(st->help.indio_dev, 0,
+ iio_push_event(indio_dev, 0,
IIO_MOD_EVENT_CODE(IIO_EV_CLASS_ACCEL,
0,
IIO_EV_MOD_X,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_RISING),
- st->thresh_timestamp);
+ timestamp);
if (t & LIS3L02DQ_REG_WAKE_UP_SRC_INTERRUPT_X_LOW)
- iio_push_event(st->help.indio_dev, 0,
+ iio_push_event(indio_dev, 0,
IIO_MOD_EVENT_CODE(IIO_EV_CLASS_ACCEL,
0,
IIO_EV_MOD_X,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_FALLING),
- st->thresh_timestamp);
- /* reenable the irq */
- enable_irq(st->us->irq);
+ timestamp);
+
/* Ack and allow for new interrupts */
- lis3l02dq_spi_read_reg_8(&st->help.indio_dev->dev,
+ lis3l02dq_spi_read_reg_8(indio_dev,
LIS3L02DQ_REG_WAKE_UP_ACK_ADDR,
&t);
- return;
+ return IRQ_HANDLED;
}
-/* A shared handler for a number of threshold types */
-IIO_EVENT_SH(threshold, &lis3l02dq_thresh_handler_th);
+#define LIS3L02DQ_INFO_MASK \
+ ((1 << IIO_CHAN_INFO_SCALE_SHARED) | \
+ (1 << IIO_CHAN_INFO_CALIBSCALE_SEPARATE) | \
+ (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE))
-IIO_EVENT_ATTR_SH(accel_x_thresh_rising_en,
- iio_event_threshold,
- lis3l02dq_read_interrupt_config,
- lis3l02dq_write_interrupt_config,
- LIS3L02DQ_REG_WAKE_UP_CFG_INTERRUPT_X_HIGH);
+#define LIS3L02DQ_EVENT_MASK \
+ (IIO_EV_BIT(IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING) | \
+ IIO_EV_BIT(IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING))
-IIO_EVENT_ATTR_SH(accel_y_thresh_rising_en,
- iio_event_threshold,
- lis3l02dq_read_interrupt_config,
- lis3l02dq_write_interrupt_config,
- LIS3L02DQ_REG_WAKE_UP_CFG_INTERRUPT_Y_HIGH);
-
-IIO_EVENT_ATTR_SH(accel_z_thresh_rising_en,
- iio_event_threshold,
- lis3l02dq_read_interrupt_config,
- lis3l02dq_write_interrupt_config,
- LIS3L02DQ_REG_WAKE_UP_CFG_INTERRUPT_Z_HIGH);
-
-IIO_EVENT_ATTR_SH(accel_x_thresh_falling_en,
- iio_event_threshold,
- lis3l02dq_read_interrupt_config,
- lis3l02dq_write_interrupt_config,
- LIS3L02DQ_REG_WAKE_UP_CFG_INTERRUPT_X_LOW);
-
-IIO_EVENT_ATTR_SH(accel_y_thresh_falling_en,
- iio_event_threshold,
- lis3l02dq_read_interrupt_config,
- lis3l02dq_write_interrupt_config,
- LIS3L02DQ_REG_WAKE_UP_CFG_INTERRUPT_Y_LOW);
-
-IIO_EVENT_ATTR_SH(accel_z_thresh_falling_en,
- iio_event_threshold,
- lis3l02dq_read_interrupt_config,
- lis3l02dq_write_interrupt_config,
- LIS3L02DQ_REG_WAKE_UP_CFG_INTERRUPT_Z_LOW);
-
-
-static struct attribute *lis3l02dq_event_attributes[] = {
- &iio_event_attr_accel_x_thresh_rising_en.dev_attr.attr,
- &iio_event_attr_accel_y_thresh_rising_en.dev_attr.attr,
- &iio_event_attr_accel_z_thresh_rising_en.dev_attr.attr,
- &iio_event_attr_accel_x_thresh_falling_en.dev_attr.attr,
- &iio_event_attr_accel_y_thresh_falling_en.dev_attr.attr,
- &iio_event_attr_accel_z_thresh_falling_en.dev_attr.attr,
- &iio_dev_attr_accel_raw_mag_value.dev_attr.attr,
- NULL
+static struct iio_chan_spec lis3l02dq_channels[] = {
+ IIO_CHAN(IIO_ACCEL, 1, 0, 0, NULL, 0, IIO_MOD_X, LIS3L02DQ_INFO_MASK,
+ 0, 0, IIO_ST('s', 12, 16, 0), LIS3L02DQ_EVENT_MASK),
+ IIO_CHAN(IIO_ACCEL, 1, 0, 0, NULL, 0, IIO_MOD_Y, LIS3L02DQ_INFO_MASK,
+ 1, 1, IIO_ST('s', 12, 16, 0), LIS3L02DQ_EVENT_MASK),
+ IIO_CHAN(IIO_ACCEL, 1, 0, 0, NULL, 0, IIO_MOD_Z, LIS3L02DQ_INFO_MASK,
+ 2, 2, IIO_ST('s', 12, 16, 0), LIS3L02DQ_EVENT_MASK),
+ IIO_CHAN_SOFT_TIMESTAMP(3)
};
-static struct attribute_group lis3l02dq_event_attribute_group = {
- .attrs = lis3l02dq_event_attributes,
-};
-static IIO_CONST_ATTR_NAME("lis3l02dq");
-static IIO_CONST_ATTR(accel_scale, "0.00958");
+static ssize_t lis3l02dq_read_event_config(struct iio_dev *indio_dev,
+ int event_code)
+{
+
+ u8 val;
+ int ret;
+ u8 mask = (1 << (IIO_EVENT_CODE_EXTRACT_MODIFIER(event_code)*2 +
+ (IIO_EVENT_CODE_EXTRACT_DIR(event_code) ==
+ IIO_EV_DIR_RISING)));
+ ret = lis3l02dq_spi_read_reg_8(indio_dev,
+ LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
+ &val);
+ if (ret < 0)
+ return ret;
+
+ return !!(val & mask);
+}
+
+int lis3l02dq_disable_all_events(struct iio_dev *indio_dev)
+{
+ int ret;
+ u8 control, val;
+
+ ret = lis3l02dq_spi_read_reg_8(indio_dev,
+ LIS3L02DQ_REG_CTRL_2_ADDR,
+ &control);
+
+ control &= ~LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT;
+ ret = lis3l02dq_spi_write_reg_8(indio_dev,
+ LIS3L02DQ_REG_CTRL_2_ADDR,
+ control);
+ if (ret)
+ goto error_ret;
+ /* Also for consistency clear the mask */
+ ret = lis3l02dq_spi_read_reg_8(indio_dev,
+ LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
+ &val);
+ if (ret)
+ goto error_ret;
+ val &= ~0x3f;
+
+ ret = lis3l02dq_spi_write_reg_8(indio_dev,
+ LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
+ val);
+ if (ret)
+ goto error_ret;
+
+ ret = control;
+error_ret:
+ return ret;
+}
+
+static int lis3l02dq_write_event_config(struct iio_dev *indio_dev,
+ int event_code,
+ int state)
+{
+ int ret = 0;
+ u8 val, control;
+ u8 currentlyset;
+ bool changed = false;
+ u8 mask = (1 << (IIO_EVENT_CODE_EXTRACT_MODIFIER(event_code)*2 +
+ (IIO_EVENT_CODE_EXTRACT_DIR(event_code) ==
+ IIO_EV_DIR_RISING)));
+
+ mutex_lock(&indio_dev->mlock);
+ /* read current control */
+ ret = lis3l02dq_spi_read_reg_8(indio_dev,
+ LIS3L02DQ_REG_CTRL_2_ADDR,
+ &control);
+ if (ret)
+ goto error_ret;
+ ret = lis3l02dq_spi_read_reg_8(indio_dev,
+ LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
+ &val);
+ if (ret < 0)
+ goto error_ret;
+ currentlyset = val & mask;
+
+ if (!currentlyset && state) {
+ changed = true;
+ val |= mask;
+ } else if (currentlyset && !state) {
+ changed = true;
+ val &= ~mask;
+ }
+
+ if (changed) {
+ ret = lis3l02dq_spi_write_reg_8(indio_dev,
+ LIS3L02DQ_REG_WAKE_UP_CFG_ADDR,
+ val);
+ if (ret)
+ goto error_ret;
+ control = val & 0x3f ?
+ (control | LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT) :
+ (control & ~LIS3L02DQ_REG_CTRL_2_ENABLE_INTERRUPT);
+ ret = lis3l02dq_spi_write_reg_8(indio_dev,
+ LIS3L02DQ_REG_CTRL_2_ADDR,
+ control);
+ if (ret)
+ goto error_ret;
+ }
+
+error_ret:
+ mutex_unlock(&indio_dev->mlock);
+ return ret;
+}
static struct attribute *lis3l02dq_attributes[] = {
- &iio_dev_attr_accel_x_calibbias.dev_attr.attr,
- &iio_dev_attr_accel_y_calibbias.dev_attr.attr,
- &iio_dev_attr_accel_z_calibbias.dev_attr.attr,
- &iio_dev_attr_accel_x_calibscale.dev_attr.attr,
- &iio_dev_attr_accel_y_calibscale.dev_attr.attr,
- &iio_dev_attr_accel_z_calibscale.dev_attr.attr,
- &iio_const_attr_accel_scale.dev_attr.attr,
- &iio_dev_attr_accel_x_raw.dev_attr.attr,
- &iio_dev_attr_accel_y_raw.dev_attr.attr,
- &iio_dev_attr_accel_z_raw.dev_attr.attr,
&iio_dev_attr_sampling_frequency.dev_attr.attr,
&iio_const_attr_sampling_frequency_available.dev_attr.attr,
- &iio_const_attr_name.dev_attr.attr,
NULL
};
@@ -779,103 +651,96 @@
.attrs = lis3l02dq_attributes,
};
+static const struct iio_info lis3l02dq_info = {
+ .num_interrupt_lines = 1,
+ .read_raw = &lis3l02dq_read_raw,
+ .write_raw = &lis3l02dq_write_raw,
+ .read_event_value = &lis3l02dq_read_thresh,
+ .write_event_value = &lis3l02dq_write_thresh,
+ .write_event_config = &lis3l02dq_write_event_config,
+ .read_event_config = &lis3l02dq_read_event_config,
+ .driver_module = THIS_MODULE,
+ .attrs = &lis3l02dq_attribute_group,
+};
+
static int __devinit lis3l02dq_probe(struct spi_device *spi)
{
int ret, regdone = 0;
- struct lis3l02dq_state *st = kzalloc(sizeof *st, GFP_KERNEL);
- if (!st) {
- ret = -ENOMEM;
+ struct lis3l02dq_state *st;
+ struct iio_dev *indio_dev;
+
+ indio_dev = iio_allocate_device(sizeof *st);
+ if (indio_dev == NULL) {
+ ret = -ENOMEM;
goto error_ret;
}
- INIT_WORK(&st->work_thresh, lis3l02dq_thresh_handler_bh_no_check);
+ st = iio_priv(indio_dev);
/* this is only used tor removal purposes */
spi_set_drvdata(spi, st);
- /* Allocate the comms buffers */
- st->rx = kzalloc(sizeof(*st->rx)*LIS3L02DQ_MAX_RX, GFP_KERNEL);
- if (st->rx == NULL) {
- ret = -ENOMEM;
- goto error_free_st;
- }
- st->tx = kzalloc(sizeof(*st->tx)*LIS3L02DQ_MAX_TX, GFP_KERNEL);
- if (st->tx == NULL) {
- ret = -ENOMEM;
- goto error_free_rx;
- }
st->us = spi;
mutex_init(&st->buf_lock);
- /* setup the industrialio driver allocated elements */
- st->help.indio_dev = iio_allocate_device();
- if (st->help.indio_dev == NULL) {
- ret = -ENOMEM;
- goto error_free_tx;
- }
+ indio_dev->name = spi->dev.driver->name;
+ indio_dev->dev.parent = &spi->dev;
+ indio_dev->info = &lis3l02dq_info;
+ indio_dev->channels = lis3l02dq_channels;
+ indio_dev->num_channels = ARRAY_SIZE(lis3l02dq_channels);
- st->help.indio_dev->dev.parent = &spi->dev;
- st->help.indio_dev->num_interrupt_lines = 1;
- st->help.indio_dev->event_attrs = &lis3l02dq_event_attribute_group;
- st->help.indio_dev->attrs = &lis3l02dq_attribute_group;
- st->help.indio_dev->dev_data = (void *)(&st->help);
- st->help.indio_dev->driver_module = THIS_MODULE;
- st->help.indio_dev->modes = INDIO_DIRECT_MODE;
+ indio_dev->modes = INDIO_DIRECT_MODE;
- ret = lis3l02dq_configure_ring(st->help.indio_dev);
+ ret = lis3l02dq_configure_ring(indio_dev);
if (ret)
goto error_free_dev;
- ret = iio_device_register(st->help.indio_dev);
+ ret = iio_device_register(indio_dev);
if (ret)
goto error_unreg_ring_funcs;
regdone = 1;
- ret = iio_ring_buffer_register(st->help.indio_dev->ring, 0);
+ ret = iio_ring_buffer_register_ex(indio_dev->ring, 0,
+ lis3l02dq_channels,
+ ARRAY_SIZE(lis3l02dq_channels));
if (ret) {
printk(KERN_ERR "failed to initialize the ring\n");
goto error_unreg_ring_funcs;
}
if (spi->irq && gpio_is_valid(irq_to_gpio(spi->irq)) > 0) {
- st->inter = 0;
- ret = iio_register_interrupt_line(spi->irq,
- st->help.indio_dev,
- 0,
- IRQF_TRIGGER_RISING,
- "lis3l02dq");
+ ret = request_threaded_irq(st->us->irq,
+ &lis3l02dq_th,
+ &lis3l02dq_event_handler,
+ IRQF_TRIGGER_RISING,
+ "lis3l02dq",
+ indio_dev);
if (ret)
goto error_uninitialize_ring;
- ret = lis3l02dq_probe_trigger(st->help.indio_dev);
+ ret = lis3l02dq_probe_trigger(indio_dev);
if (ret)
- goto error_unregister_line;
+ goto error_free_interrupt;
}
/* Get the device into a sane initial state */
- ret = lis3l02dq_initial_setup(st);
+ ret = lis3l02dq_initial_setup(indio_dev);
if (ret)
goto error_remove_trigger;
return 0;
error_remove_trigger:
- if (st->help.indio_dev->modes & INDIO_RING_TRIGGERED)
- lis3l02dq_remove_trigger(st->help.indio_dev);
-error_unregister_line:
- if (st->help.indio_dev->modes & INDIO_RING_TRIGGERED)
- iio_unregister_interrupt_line(st->help.indio_dev, 0);
+ if (indio_dev->modes & INDIO_RING_TRIGGERED)
+ lis3l02dq_remove_trigger(indio_dev);
+error_free_interrupt:
+ if (spi->irq && gpio_is_valid(irq_to_gpio(spi->irq)) > 0)
+ free_irq(st->us->irq, indio_dev);
error_uninitialize_ring:
- iio_ring_buffer_unregister(st->help.indio_dev->ring);
+ iio_ring_buffer_unregister(indio_dev->ring);
error_unreg_ring_funcs:
- lis3l02dq_unconfigure_ring(st->help.indio_dev);
+ lis3l02dq_unconfigure_ring(indio_dev);
error_free_dev:
if (regdone)
- iio_device_unregister(st->help.indio_dev);
+ iio_device_unregister(indio_dev);
else
- iio_free_device(st->help.indio_dev);
-error_free_tx:
- kfree(st->tx);
-error_free_rx:
- kfree(st->rx);
-error_free_st:
- kfree(st);
+ iio_free_device(indio_dev);
error_ret:
return ret;
}
@@ -884,23 +749,21 @@
static int lis3l02dq_stop_device(struct iio_dev *indio_dev)
{
int ret;
- struct iio_sw_ring_helper_state *h
- = iio_dev_get_devdata(indio_dev);
- struct lis3l02dq_state *st = lis3l02dq_h_to_s(h);
+ struct lis3l02dq_state *st = iio_priv(indio_dev);
u8 val = 0;
mutex_lock(&indio_dev->mlock);
- ret = lis3l02dq_spi_write_reg_8(&indio_dev->dev,
+ ret = lis3l02dq_spi_write_reg_8(indio_dev,
LIS3L02DQ_REG_CTRL_1_ADDR,
- &val);
+ val);
if (ret) {
dev_err(&st->us->dev, "problem with turning device off: ctrl1");
goto err_ret;
}
- ret = lis3l02dq_spi_write_reg_8(&indio_dev->dev,
+ ret = lis3l02dq_spi_write_reg_8(indio_dev,
LIS3L02DQ_REG_CTRL_2_ADDR,
- &val);
+ val);
if (ret)
dev_err(&st->us->dev, "problem with turning device off: ctrl2");
err_ret:
@@ -912,25 +775,24 @@
static int lis3l02dq_remove(struct spi_device *spi)
{
int ret;
- struct lis3l02dq_state *st = spi_get_drvdata(spi);
- struct iio_dev *indio_dev = st->help.indio_dev;
+ struct iio_dev *indio_dev = spi_get_drvdata(spi);
+ struct lis3l02dq_state *st = iio_priv(indio_dev);
+
+ ret = lis3l02dq_disable_all_events(indio_dev);
+ if (ret)
+ goto err_ret;
ret = lis3l02dq_stop_device(indio_dev);
if (ret)
goto err_ret;
- flush_scheduled_work();
+ if (spi->irq && gpio_is_valid(irq_to_gpio(spi->irq)) > 0)
+ free_irq(st->us->irq, indio_dev);
lis3l02dq_remove_trigger(indio_dev);
- if (spi->irq && gpio_is_valid(irq_to_gpio(spi->irq)) > 0)
- iio_unregister_interrupt_line(indio_dev, 0);
-
iio_ring_buffer_unregister(indio_dev->ring);
lis3l02dq_unconfigure_ring(indio_dev);
iio_device_unregister(indio_dev);
- kfree(st->tx);
- kfree(st->rx);
- kfree(st);
return 0;
diff --git a/drivers/staging/iio/accel/lis3l02dq_ring.c b/drivers/staging/iio/accel/lis3l02dq_ring.c
index 529a3cc..8d5c8ac 100644
--- a/drivers/staging/iio/accel/lis3l02dq_ring.c
+++ b/drivers/staging/iio/accel/lis3l02dq_ring.c
@@ -1,13 +1,11 @@
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/gpio.h>
-#include <linux/workqueue.h>
#include <linux/mutex.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/spi/spi.h>
#include <linux/sysfs.h>
-#include <linux/list.h>
#include <linux/slab.h>
#include "../iio.h"
@@ -29,180 +27,49 @@
}
/**
- * lis3l02dq_scan_el_set_state() set whether a scan contains a given channel
- * @scan_el: associtate iio scan element attribute
- * @indio_dev: the device structure
- * @bool: desired state
- *
- * mlock already held when this is called.
- **/
-static int lis3l02dq_scan_el_set_state(struct iio_scan_el *scan_el,
- struct iio_dev *indio_dev,
- bool state)
-{
- u8 t, mask;
- int ret;
-
- ret = lis3l02dq_spi_read_reg_8(&indio_dev->dev,
- LIS3L02DQ_REG_CTRL_1_ADDR,
- &t);
- if (ret)
- goto error_ret;
- switch (scan_el->label) {
- case LIS3L02DQ_REG_OUT_X_L_ADDR:
- mask = LIS3L02DQ_REG_CTRL_1_AXES_X_ENABLE;
- break;
- case LIS3L02DQ_REG_OUT_Y_L_ADDR:
- mask = LIS3L02DQ_REG_CTRL_1_AXES_Y_ENABLE;
- break;
- case LIS3L02DQ_REG_OUT_Z_L_ADDR:
- mask = LIS3L02DQ_REG_CTRL_1_AXES_Z_ENABLE;
- break;
- default:
- ret = -EINVAL;
- goto error_ret;
- }
-
- if (!(mask & t) == state) {
- if (state)
- t |= mask;
- else
- t &= ~mask;
- ret = lis3l02dq_spi_write_reg_8(&indio_dev->dev,
- LIS3L02DQ_REG_CTRL_1_ADDR,
- &t);
- }
-error_ret:
- return ret;
-
-}
-static IIO_SCAN_EL_C(accel_x, 0,
- LIS3L02DQ_REG_OUT_X_L_ADDR,
- &lis3l02dq_scan_el_set_state);
-static IIO_SCAN_EL_C(accel_y, 1,
- LIS3L02DQ_REG_OUT_Y_L_ADDR,
- &lis3l02dq_scan_el_set_state);
-static IIO_SCAN_EL_C(accel_z, 2,
- LIS3L02DQ_REG_OUT_Z_L_ADDR,
- &lis3l02dq_scan_el_set_state);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(accel, s, 12, 16);
-static IIO_SCAN_EL_TIMESTAMP(3);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(timestamp, s, 64, 64);
-
-static struct attribute *lis3l02dq_scan_el_attrs[] = {
- &iio_scan_el_accel_x.dev_attr.attr,
- &iio_const_attr_accel_x_index.dev_attr.attr,
- &iio_scan_el_accel_y.dev_attr.attr,
- &iio_const_attr_accel_y_index.dev_attr.attr,
- &iio_scan_el_accel_z.dev_attr.attr,
- &iio_const_attr_accel_z_index.dev_attr.attr,
- &iio_const_attr_accel_type.dev_attr.attr,
- &iio_scan_el_timestamp.dev_attr.attr,
- &iio_const_attr_timestamp_index.dev_attr.attr,
- &iio_const_attr_timestamp_type.dev_attr.attr,
- NULL,
-};
-
-static struct attribute_group lis3l02dq_scan_el_group = {
- .attrs = lis3l02dq_scan_el_attrs,
- .name = "scan_elements",
-};
-
-/**
- * lis3l02dq_poll_func_th() top half interrupt handler called by trigger
- * @private_data: iio_dev
- **/
-static void lis3l02dq_poll_func_th(struct iio_dev *indio_dev, s64 time)
-{
- struct iio_sw_ring_helper_state *h
- = iio_dev_get_devdata(indio_dev);
- struct lis3l02dq_state *st = lis3l02dq_h_to_s(h);
- /* in this case we need to slightly extend the helper function */
- iio_sw_poll_func_th(indio_dev, time);
-
- /* Indicate that this interrupt is being handled */
- /* Technically this is trigger related, but without this
- * handler running there is currently now way for the interrupt
- * to clear.
- */
- st->inter = 1;
-}
-
-/**
* lis3l02dq_data_rdy_trig_poll() the event handler for the data rdy trig
**/
-static int lis3l02dq_data_rdy_trig_poll(struct iio_dev *indio_dev,
- int index,
- s64 timestamp,
- int no_test)
+irqreturn_t lis3l02dq_data_rdy_trig_poll(int irq, void *private)
{
- struct iio_sw_ring_helper_state *h
- = iio_dev_get_devdata(indio_dev);
- struct lis3l02dq_state *st = lis3l02dq_h_to_s(h);
+ struct iio_dev *indio_dev = private;
+ struct lis3l02dq_state *st = iio_priv(indio_dev);
- iio_trigger_poll(st->trig, timestamp);
-
- return IRQ_HANDLED;
+ if (st->trigger_on) {
+ iio_trigger_poll(st->trig, iio_get_time_ns());
+ return IRQ_HANDLED;
+ } else
+ return IRQ_WAKE_THREAD;
}
-/* This is an event as it is a response to a physical interrupt */
-IIO_EVENT_SH(data_rdy_trig, &lis3l02dq_data_rdy_trig_poll);
-
/**
* lis3l02dq_read_accel_from_ring() individual acceleration read from ring
**/
-ssize_t lis3l02dq_read_accel_from_ring(struct device *dev,
- struct device_attribute *attr,
- char *buf)
+ssize_t lis3l02dq_read_accel_from_ring(struct iio_ring_buffer *ring,
+ int index,
+ int *val)
{
- struct iio_scan_el *el = NULL;
- int ret, len = 0, i = 0;
- struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
- struct iio_dev *dev_info = dev_get_drvdata(dev);
- struct iio_ring_buffer *ring = dev_info->ring;
- struct attribute_group *scan_el_attrs = ring->scan_el_attrs;
+ int ret;
s16 *data;
- while (scan_el_attrs->attrs[i]) {
- el = to_iio_scan_el((struct device_attribute *)
- (scan_el_attrs->attrs[i]));
- /* label is in fact the address */
- if (el->label == this_attr->address)
- break;
- i++;
- }
- if (!scan_el_attrs->attrs[i]) {
- ret = -EINVAL;
- goto error_ret;
- }
- /* If this element is in the scan mask */
- ret = iio_scan_mask_query(ring, el->number);
- if (ret < 0)
- goto error_ret;
- if (ret) {
- data = kmalloc(ring->access.get_bytes_per_datum(ring),
- GFP_KERNEL);
- if (data == NULL)
- return -ENOMEM;
- ret = ring->access.read_last(ring,
- (u8 *)data);
- if (ret)
- goto error_free_data;
- } else {
- ret = -EINVAL;
- goto error_ret;
- }
- len = iio_scan_mask_count_to_right(ring, el->number);
- if (len < 0) {
- ret = len;
+ if (!iio_scan_mask_query(ring, index))
+ return -EINVAL;
+
+ if (!ring->access->read_last)
+ return -EBUSY;
+
+ data = kmalloc(ring->access->get_bytes_per_datum(ring),
+ GFP_KERNEL);
+ if (data == NULL)
+ return -ENOMEM;
+
+ ret = ring->access->read_last(ring, (u8 *)data);
+ if (ret)
goto error_free_data;
- }
- len = sprintf(buf, "ring %d\n", data[len]);
+ *val = data[bitmap_weight(&ring->scan_mask, index)];
error_free_data:
kfree(data);
-error_ret:
- return ret ? ret : len;
+ return ret;
}
static const u8 read_all_tx_array[] = {
@@ -220,9 +87,10 @@
* @rx_array: (dma capable) receive array, must be at least
* 4*number of channels
**/
-static int lis3l02dq_read_all(struct lis3l02dq_state *st, u8 *rx_array)
+static int lis3l02dq_read_all(struct iio_dev *indio_dev, u8 *rx_array)
{
- struct iio_ring_buffer *ring = st->help.indio_dev->ring;
+ struct iio_ring_buffer *ring = indio_dev->ring;
+ struct lis3l02dq_state *st = iio_priv(indio_dev);
struct spi_transfer *xfers;
struct spi_message msg;
int ret, i, j = 0;
@@ -234,7 +102,7 @@
mutex_lock(&st->buf_lock);
- for (i = 0; i < ARRAY_SIZE(read_all_tx_array)/4; i++) {
+ for (i = 0; i < ARRAY_SIZE(read_all_tx_array)/4; i++)
if (ring->scan_mask & (1 << i)) {
/* lower byte */
xfers[j].tx_buf = st->tx + 2*j;
@@ -258,7 +126,7 @@
xfers[j].cs_change = 1;
j++;
}
- }
+
/* After these are transmitted, the rx_buff should have
* values in alternate bytes
*/
@@ -273,31 +141,20 @@
return ret;
}
-static void lis3l02dq_trigger_bh_to_ring(struct work_struct *work_s)
-{
- struct iio_sw_ring_helper_state *h
- = container_of(work_s, struct iio_sw_ring_helper_state,
- work_trigger_to_ring);
- struct lis3l02dq_state *st = lis3l02dq_h_to_s(h);
-
- st->inter = 0;
- iio_sw_trigger_bh_to_ring(work_s);
-}
-
-static int lis3l02dq_get_ring_element(struct iio_sw_ring_helper_state *h,
+static int lis3l02dq_get_ring_element(struct iio_dev *indio_dev,
u8 *buf)
{
int ret, i;
u8 *rx_array ;
s16 *data = (s16 *)buf;
- rx_array = kzalloc(4 * (h->indio_dev->ring->scan_count), GFP_KERNEL);
+ rx_array = kzalloc(4 * (indio_dev->ring->scan_count), GFP_KERNEL);
if (rx_array == NULL)
return -ENOMEM;
- ret = lis3l02dq_read_all(lis3l02dq_h_to_s(h), rx_array);
+ ret = lis3l02dq_read_all(indio_dev, rx_array);
if (ret < 0)
return ret;
- for (i = 0; i < h->indio_dev->ring->scan_count; i++)
+ for (i = 0; i < indio_dev->ring->scan_count; i++)
data[i] = combine_8_to_16(rx_array[i*4+1],
rx_array[i*4+3]);
kfree(rx_array);
@@ -305,19 +162,48 @@
return i*sizeof(data[0]);
}
+static irqreturn_t lis3l02dq_trigger_handler(int irq, void *p)
+{
+ struct iio_poll_func *pf = p;
+ struct iio_dev *indio_dev = pf->private_data;
+ struct iio_ring_buffer *ring = indio_dev->ring;
+ int len = 0;
+ size_t datasize = ring->access->get_bytes_per_datum(ring);
+ char *data = kmalloc(datasize, GFP_KERNEL);
+
+ if (data == NULL) {
+ dev_err(indio_dev->dev.parent,
+ "memory alloc failed in ring bh");
+ return -ENOMEM;
+ }
+
+ if (ring->scan_count)
+ len = lis3l02dq_get_ring_element(indio_dev, data);
+
+ /* Guaranteed to be aligned with 8 byte boundary */
+ if (ring->scan_timestamp)
+ *(s64 *)(((phys_addr_t)data + len
+ + sizeof(s64) - 1) & ~(sizeof(s64) - 1))
+ = pf->timestamp;
+ ring->access->store_to(ring, (u8 *)data, pf->timestamp);
+
+ iio_trigger_notify_done(indio_dev->trig);
+ kfree(data);
+ return IRQ_HANDLED;
+}
+
/* Caller responsible for locking as necessary. */
static int
-__lis3l02dq_write_data_ready_config(struct device *dev,
- struct iio_event_handler_list *list,
- bool state)
+__lis3l02dq_write_data_ready_config(struct device *dev, bool state)
{
int ret;
u8 valold;
bool currentlyset;
struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ struct lis3l02dq_state *st = iio_priv(indio_dev);
/* Get the current event mask register */
- ret = lis3l02dq_spi_read_reg_8(dev,
+ ret = lis3l02dq_spi_read_reg_8(indio_dev,
LIS3L02DQ_REG_CTRL_2_ADDR,
&valold);
if (ret)
@@ -328,32 +214,36 @@
/* Disable requested */
if (!state && currentlyset) {
-
+ /* disable the data ready signal */
valold &= ~LIS3L02DQ_REG_CTRL_2_ENABLE_DATA_READY_GENERATION;
+
/* The double write is to overcome a hardware bug?*/
- ret = lis3l02dq_spi_write_reg_8(dev,
+ ret = lis3l02dq_spi_write_reg_8(indio_dev,
LIS3L02DQ_REG_CTRL_2_ADDR,
- &valold);
+ valold);
if (ret)
goto error_ret;
- ret = lis3l02dq_spi_write_reg_8(dev,
+ ret = lis3l02dq_spi_write_reg_8(indio_dev,
LIS3L02DQ_REG_CTRL_2_ADDR,
- &valold);
+ valold);
if (ret)
goto error_ret;
-
- iio_remove_event_from_list(list,
- &indio_dev->interrupts[0]
- ->ev_list);
-
+ st->trigger_on = false;
/* Enable requested */
} else if (state && !currentlyset) {
/* if not set, enable requested */
- valold |= LIS3L02DQ_REG_CTRL_2_ENABLE_DATA_READY_GENERATION;
- iio_add_event_to_list(list, &indio_dev->interrupts[0]->ev_list);
- ret = lis3l02dq_spi_write_reg_8(dev,
+ /* first disable all events */
+ ret = lis3l02dq_disable_all_events(indio_dev);
+ if (ret < 0)
+ goto error_ret;
+
+ valold = ret |
+ LIS3L02DQ_REG_CTRL_2_ENABLE_DATA_READY_GENERATION;
+
+ st->trigger_on = true;
+ ret = lis3l02dq_spi_write_reg_8(indio_dev,
LIS3L02DQ_REG_CTRL_2_ADDR,
- &valold);
+ valold);
if (ret)
goto error_ret;
}
@@ -373,65 +263,45 @@
static int lis3l02dq_data_rdy_trigger_set_state(struct iio_trigger *trig,
bool state)
{
- struct lis3l02dq_state *st = trig->private_data;
+ struct iio_dev *indio_dev = trig->private_data;
int ret = 0;
u8 t;
- __lis3l02dq_write_data_ready_config(&st->help.indio_dev->dev,
- &iio_event_data_rdy_trig,
- state);
+
+ __lis3l02dq_write_data_ready_config(&indio_dev->dev, state);
if (state == false) {
- /* possible quirk with handler currently worked around
- by ensuring the work queue is empty */
- flush_scheduled_work();
- /* Clear any outstanding ready events */
- ret = lis3l02dq_read_all(st, NULL);
+ /*
+ * A possible quirk with teh handler is currently worked around
+ * by ensuring outstanding read events are cleared.
+ */
+ ret = lis3l02dq_read_all(indio_dev, NULL);
}
- lis3l02dq_spi_read_reg_8(&st->help.indio_dev->dev,
+ lis3l02dq_spi_read_reg_8(indio_dev,
LIS3L02DQ_REG_WAKE_UP_SRC_ADDR,
&t);
return ret;
}
-static IIO_TRIGGER_NAME_ATTR;
-
-static struct attribute *lis3l02dq_trigger_attrs[] = {
- &dev_attr_name.attr,
- NULL,
-};
-
-static const struct attribute_group lis3l02dq_trigger_attr_group = {
- .attrs = lis3l02dq_trigger_attrs,
-};
-
/**
* lis3l02dq_trig_try_reen() try renabling irq for data rdy trigger
* @trig: the datardy trigger
- *
- * As the trigger may occur on any data element being updated it is
- * really rather likely to occur during the read from the previous
- * trigger event. The only way to discover if this has occurred on
- * boards not supporting level interrupts is to take a look at the line.
- * If it is indicating another interrupt and we don't seem to have a
- * handler looking at it, then we need to notify the core that we need
- * to tell the triggering core to try reading all these again.
- **/
+ */
static int lis3l02dq_trig_try_reen(struct iio_trigger *trig)
{
- struct lis3l02dq_state *st = trig->private_data;
- enable_irq(st->us->irq);
+ struct iio_dev *indio_dev = trig->private_data;
+ struct lis3l02dq_state *st = iio_priv(indio_dev);
+ int i;
+
/* If gpio still high (or high again) */
- if (gpio_get_value(irq_to_gpio(st->us->irq)))
- if (st->inter == 0) {
- /* already interrupt handler dealing with it */
- disable_irq_nosync(st->us->irq);
- if (st->inter == 1) {
- /* interrupt handler snuck in between test
- * and disable */
- enable_irq(st->us->irq);
- return 0;
- }
- return -EAGAIN;
- }
+ /* In theory possible we will need to do this several times */
+ for (i = 0; i < 5; i++)
+ if (gpio_get_value(irq_to_gpio(st->us->irq)))
+ lis3l02dq_read_all(indio_dev, NULL);
+ else
+ break;
+ if (i == 5)
+ printk(KERN_INFO
+ "Failed to clear the interrupt for lis3l02dq\n");
+
/* irq reenabled so success! */
return 0;
}
@@ -439,62 +309,124 @@
int lis3l02dq_probe_trigger(struct iio_dev *indio_dev)
{
int ret;
- struct lis3l02dq_state *state = indio_dev->dev_data;
+ struct lis3l02dq_state *st = iio_priv(indio_dev);
- state->trig = iio_allocate_trigger();
- if (!state->trig)
- return -ENOMEM;
-
- state->trig->name = kasprintf(GFP_KERNEL,
- "lis3l02dq-dev%d",
- indio_dev->id);
- if (!state->trig->name) {
+ st->trig = iio_allocate_trigger("lis3l02dq-dev%d", indio_dev->id);
+ if (!st->trig) {
ret = -ENOMEM;
- goto error_free_trig;
+ goto error_ret;
}
- state->trig->dev.parent = &state->us->dev;
- state->trig->owner = THIS_MODULE;
- state->trig->private_data = state;
- state->trig->set_trigger_state = &lis3l02dq_data_rdy_trigger_set_state;
- state->trig->try_reenable = &lis3l02dq_trig_try_reen;
- state->trig->control_attrs = &lis3l02dq_trigger_attr_group;
- ret = iio_trigger_register(state->trig);
+ st->trig->dev.parent = &st->us->dev;
+ st->trig->owner = THIS_MODULE;
+ st->trig->private_data = indio_dev;
+ st->trig->set_trigger_state = &lis3l02dq_data_rdy_trigger_set_state;
+ st->trig->try_reenable = &lis3l02dq_trig_try_reen;
+ ret = iio_trigger_register(st->trig);
if (ret)
- goto error_free_trig_name;
+ goto error_free_trig;
return 0;
-error_free_trig_name:
- kfree(state->trig->name);
error_free_trig:
- iio_free_trigger(state->trig);
-
+ iio_free_trigger(st->trig);
+error_ret:
return ret;
}
void lis3l02dq_remove_trigger(struct iio_dev *indio_dev)
{
- struct lis3l02dq_state *state = indio_dev->dev_data;
+ struct lis3l02dq_state *st = iio_priv(indio_dev);
- iio_trigger_unregister(state->trig);
- kfree(state->trig->name);
- iio_free_trigger(state->trig);
+ iio_trigger_unregister(st->trig);
+ iio_free_trigger(st->trig);
}
void lis3l02dq_unconfigure_ring(struct iio_dev *indio_dev)
{
- kfree(indio_dev->pollfunc);
+ iio_dealloc_pollfunc(indio_dev->pollfunc);
lis3l02dq_free_buf(indio_dev->ring);
}
+static int lis3l02dq_ring_postenable(struct iio_dev *indio_dev)
+{
+ /* Disable unwanted channels otherwise the interrupt will not clear */
+ u8 t;
+ int ret;
+ bool oneenabled = false;
+
+ ret = lis3l02dq_spi_read_reg_8(indio_dev,
+ LIS3L02DQ_REG_CTRL_1_ADDR,
+ &t);
+ if (ret)
+ goto error_ret;
+
+ if (iio_scan_mask_query(indio_dev->ring, 0)) {
+ t |= LIS3L02DQ_REG_CTRL_1_AXES_X_ENABLE;
+ oneenabled = true;
+ } else
+ t &= ~LIS3L02DQ_REG_CTRL_1_AXES_X_ENABLE;
+ if (iio_scan_mask_query(indio_dev->ring, 1)) {
+ t |= LIS3L02DQ_REG_CTRL_1_AXES_Y_ENABLE;
+ oneenabled = true;
+ } else
+ t &= ~LIS3L02DQ_REG_CTRL_1_AXES_Y_ENABLE;
+ if (iio_scan_mask_query(indio_dev->ring, 2)) {
+ t |= LIS3L02DQ_REG_CTRL_1_AXES_Z_ENABLE;
+ oneenabled = true;
+ } else
+ t &= ~LIS3L02DQ_REG_CTRL_1_AXES_Z_ENABLE;
+
+ if (!oneenabled) /* what happens in this case is unknown */
+ return -EINVAL;
+ ret = lis3l02dq_spi_write_reg_8(indio_dev,
+ LIS3L02DQ_REG_CTRL_1_ADDR,
+ t);
+ if (ret)
+ goto error_ret;
+
+ return iio_triggered_ring_postenable(indio_dev);
+error_ret:
+ return ret;
+}
+
+/* Turn all channels on again */
+static int lis3l02dq_ring_predisable(struct iio_dev *indio_dev)
+{
+ u8 t;
+ int ret;
+
+ ret = iio_triggered_ring_predisable(indio_dev);
+ if (ret)
+ goto error_ret;
+
+ ret = lis3l02dq_spi_read_reg_8(indio_dev,
+ LIS3L02DQ_REG_CTRL_1_ADDR,
+ &t);
+ if (ret)
+ goto error_ret;
+ t |= LIS3L02DQ_REG_CTRL_1_AXES_X_ENABLE |
+ LIS3L02DQ_REG_CTRL_1_AXES_Y_ENABLE |
+ LIS3L02DQ_REG_CTRL_1_AXES_Z_ENABLE;
+
+ ret = lis3l02dq_spi_write_reg_8(indio_dev,
+ LIS3L02DQ_REG_CTRL_1_ADDR,
+ t);
+
+error_ret:
+ return ret;
+}
+
+static const struct iio_ring_setup_ops lis3l02dq_ring_setup_ops = {
+ .preenable = &iio_sw_ring_preenable,
+ .postenable = &lis3l02dq_ring_postenable,
+ .predisable = &lis3l02dq_ring_predisable,
+};
+
int lis3l02dq_configure_ring(struct iio_dev *indio_dev)
{
int ret;
- struct iio_sw_ring_helper_state *h = iio_dev_get_devdata(indio_dev);
struct iio_ring_buffer *ring;
- INIT_WORK(&h->work_trigger_to_ring, lis3l02dq_trigger_bh_to_ring);
- h->get_ring_element = &lis3l02dq_get_ring_element;
ring = lis3l02dq_alloc_buf(indio_dev);
if (!ring)
@@ -502,23 +434,31 @@
indio_dev->ring = ring;
/* Effectively select the ring buffer implementation */
- lis3l02dq_register_buf_funcs(&ring->access);
+ indio_dev->ring->access = &lis3l02dq_access_funcs;
ring->bpe = 2;
- ring->scan_el_attrs = &lis3l02dq_scan_el_group;
+
ring->scan_timestamp = true;
- ring->preenable = &iio_sw_ring_preenable;
- ring->postenable = &iio_triggered_ring_postenable;
- ring->predisable = &iio_triggered_ring_predisable;
+ ring->setup_ops = &lis3l02dq_ring_setup_ops;
ring->owner = THIS_MODULE;
/* Set default scan mode */
- iio_scan_mask_set(ring, iio_scan_el_accel_x.number);
- iio_scan_mask_set(ring, iio_scan_el_accel_y.number);
- iio_scan_mask_set(ring, iio_scan_el_accel_z.number);
+ iio_scan_mask_set(ring, 0);
+ iio_scan_mask_set(ring, 1);
+ iio_scan_mask_set(ring, 2);
- ret = iio_alloc_pollfunc(indio_dev, NULL, &lis3l02dq_poll_func_th);
- if (ret)
+ /* Functions are NULL as we set handler below */
+ indio_dev->pollfunc = iio_alloc_pollfunc(&iio_pollfunc_store_time,
+ &lis3l02dq_trigger_handler,
+ 0,
+ indio_dev,
+ "lis3l02dq_consumer%d",
+ indio_dev->id);
+
+ if (indio_dev->pollfunc == NULL) {
+ ret = -ENOMEM;
goto error_iio_sw_rb_free;
+ }
+
indio_dev->modes |= INDIO_RING_TRIGGERED;
return 0;
diff --git a/drivers/staging/iio/accel/sca3000.h b/drivers/staging/iio/accel/sca3000.h
index db71033..cf0751d 100644
--- a/drivers/staging/iio/accel/sca3000.h
+++ b/drivers/staging/iio/accel/sca3000.h
@@ -158,17 +158,17 @@
/**
* struct sca3000_state - device instance state information
- * @us: the associated spi device
- * @info: chip variant information
- * @indio_dev: device information used by the IIO core
- * @interrupt_handler_ws: event interrupt handler for all events
- * @last_timestamp: the timestamp of the last event
- * @mo_det_use_count: reference counter for the motion detection unit
- * @lock: lock used to protect elements of sca3000_state
- * and the underlying device state.
- * @bpse: number of bits per scan element
- * @tx: dma-able transmit buffer
- * @rx: dma-able receive buffer
+ * @us: the associated spi device
+ * @info: chip variant information
+ * @indio_dev: device information used by the IIO core
+ * @interrupt_handler_ws: event interrupt handler for all events
+ * @last_timestamp: the timestamp of the last event
+ * @mo_det_use_count: reference counter for the motion detection unit
+ * @lock: lock used to protect elements of sca3000_state
+ * and the underlying device state.
+ * @bpse: number of bits per scan element
+ * @tx: dma-able transmit buffer
+ * @rx: dma-able receive buffer
**/
struct sca3000_state {
struct spi_device *us;
@@ -179,15 +179,14 @@
int mo_det_use_count;
struct mutex lock;
int bpse;
- u8 *tx;
- /* not used during a ring buffer read */
- u8 *rx;
+ /* Can these share a cacheline ? */
+ u8 rx[2] ____cacheline_aligned;
+ u8 tx[6] ____cacheline_aligned;
};
/**
* struct sca3000_chip_info - model dependent parameters
- * @name: model identification
- * @scale: string containing floating point scale factor
+ * @scale: scale * 10^-6
* @temp_output: some devices have temperature sensors.
* @measurement_mode_freq: normal mode sampling frequency
* @option_mode_1: first optional mode. Not all models have one
@@ -199,30 +198,20 @@
* sca3000 variant.
**/
struct sca3000_chip_info {
- const char *name;
- const char *scale;
+ unsigned int scale;
bool temp_output;
int measurement_mode_freq;
int option_mode_1;
int option_mode_1_freq;
int option_mode_2;
int option_mode_2_freq;
+ int mot_det_mult_xz[6];
+ int mot_det_mult_y[7];
};
-/**
- * sca3000_read_data() read a series of values from the device
- * @dev: device
- * @reg_address_high: start address (decremented read)
- * @rx: pointer where received data is placed. Callee
- * responsible for freeing this.
- * @len: number of bytes to read
- *
- * The main lock must be held.
- **/
-int sca3000_read_data(struct sca3000_state *st,
- u8 reg_address_high,
- u8 **rx_p,
- int len);
+int sca3000_read_data_short(struct sca3000_state *st,
+ u8 reg_address_high,
+ int len);
/**
* sca3000_write_reg() write a single register
@@ -233,29 +222,6 @@
**/
int sca3000_write_reg(struct sca3000_state *st, u8 address, u8 val);
-/* Conversion function for use with the ring buffer when in 11bit mode */
-static inline int sca3000_11bit_convert(uint8_t msb, uint8_t lsb)
-{
- int16_t val;
-
- val = ((lsb >> 3) & 0x1C) | (msb << 5);
- val |= (val & (1 << 12)) ? 0xE000 : 0;
-
- return val;
-}
-
-static inline int sca3000_13bit_convert(uint8_t msb, uint8_t lsb)
-{
- s16 val;
-
- val = ((lsb >> 3) & 0x1F) | (msb << 5);
- /* sign fill */
- val |= (val & (1 << 12)) ? 0xE000 : 0;
-
- return val;
-}
-
-
#ifdef CONFIG_IIO_RING_BUFFER
/**
* sca3000_register_ring_funcs() setup the ring state change functions
diff --git a/drivers/staging/iio/accel/sca3000_core.c b/drivers/staging/iio/accel/sca3000_core.c
index 5b06dea..f213b86 100644
--- a/drivers/staging/iio/accel/sca3000_core.c
+++ b/drivers/staging/iio/accel/sca3000_core.c
@@ -40,95 +40,74 @@
* do not actually appear to be available.
*/
static const struct sca3000_chip_info sca3000_spi_chip_info_tbl[] = {
- {
- .name = "sca3000-d01",
- .scale = " 0.0073575",
+ [d01] = {
+ .scale = 7357,
.temp_output = true,
.measurement_mode_freq = 250,
.option_mode_1 = SCA3000_OP_MODE_BYPASS,
.option_mode_1_freq = 250,
- }, {
- .name = "sca3000-e02",
- .scale = "0.00981",
+ .mot_det_mult_xz = {50, 100, 200, 350, 650, 1300},
+ .mot_det_mult_y = {50, 100, 150, 250, 450, 850, 1750},
+ },
+ [e02] = {
+ .scale = 9810,
.measurement_mode_freq = 125,
.option_mode_1 = SCA3000_OP_MODE_NARROW,
.option_mode_1_freq = 63,
- }, {
- .name = "sca3000-e04",
- .scale = "0.01962",
+ .mot_det_mult_xz = {100, 150, 300, 550, 1050, 2050},
+ .mot_det_mult_y = {50, 100, 200, 350, 700, 1350, 2700},
+ },
+ [e04] = {
+ .scale = 19620,
.measurement_mode_freq = 100,
.option_mode_1 = SCA3000_OP_MODE_NARROW,
.option_mode_1_freq = 50,
.option_mode_2 = SCA3000_OP_MODE_WIDE,
.option_mode_2_freq = 400,
- }, {
- .name = "sca3000-e05",
- .scale = "0.0613125",
+ .mot_det_mult_xz = {200, 300, 600, 1100, 2100, 4100},
+ .mot_det_mult_y = {100, 200, 400, 7000, 1400, 2700, 54000},
+ },
+ [e05] = {
+ .scale = 61313,
.measurement_mode_freq = 200,
.option_mode_1 = SCA3000_OP_MODE_NARROW,
.option_mode_1_freq = 50,
.option_mode_2 = SCA3000_OP_MODE_WIDE,
.option_mode_2_freq = 400,
+ .mot_det_mult_xz = {600, 900, 1700, 3200, 6100, 11900},
+ .mot_det_mult_y = {300, 600, 1200, 2000, 4100, 7800, 15600},
},
};
-
int sca3000_write_reg(struct sca3000_state *st, u8 address, u8 val)
{
- struct spi_transfer xfer = {
- .bits_per_word = 8,
- .len = 2,
- .cs_change = 1,
- .tx_buf = st->tx,
- };
- struct spi_message msg;
-
st->tx[0] = SCA3000_WRITE_REG(address);
st->tx[1] = val;
+ return spi_write(st->us, st->tx, 2);
+}
+
+int sca3000_read_data_short(struct sca3000_state *st,
+ uint8_t reg_address_high,
+ int len)
+{
+ struct spi_message msg;
+ struct spi_transfer xfer[2] = {
+ {
+ .len = 1,
+ .tx_buf = st->tx,
+ }, {
+ .len = len,
+ .rx_buf = st->rx,
+ }
+ };
+ st->tx[0] = SCA3000_READ_REG(reg_address_high);
spi_message_init(&msg);
- spi_message_add_tail(&xfer, &msg);
+ spi_message_add_tail(&xfer[0], &msg);
+ spi_message_add_tail(&xfer[1], &msg);
return spi_sync(st->us, &msg);
}
-int sca3000_read_data(struct sca3000_state *st,
- uint8_t reg_address_high,
- u8 **rx_p,
- int len)
-{
- int ret;
- struct spi_message msg;
- struct spi_transfer xfer = {
- .bits_per_word = 8,
- .len = len + 1,
- .cs_change = 1,
- .tx_buf = st->tx,
- };
-
- *rx_p = kmalloc(len + 1, GFP_KERNEL);
- if (*rx_p == NULL) {
- ret = -ENOMEM;
- goto error_ret;
- }
- xfer.rx_buf = *rx_p;
- st->tx[0] = SCA3000_READ_REG(reg_address_high);
- spi_message_init(&msg);
- spi_message_add_tail(&xfer, &msg);
-
- ret = spi_sync(st->us, &msg);
-
- if (ret) {
- dev_err(get_device(&st->us->dev), "problem reading register");
- goto error_free_rx;
- }
-
- return 0;
-error_free_rx:
- kfree(*rx_p);
-error_ret:
- return ret;
-
-}
/**
* sca3000_reg_lock_on() test if the ctrl register lock is on
*
@@ -136,17 +115,13 @@
**/
static int sca3000_reg_lock_on(struct sca3000_state *st)
{
- u8 *rx;
int ret;
- ret = sca3000_read_data(st, SCA3000_REG_ADDR_STATUS, &rx, 1);
-
+ ret = sca3000_read_data_short(st, SCA3000_REG_ADDR_STATUS, 1);
if (ret < 0)
return ret;
- ret = !(rx[1] & SCA3000_LOCKED);
- kfree(rx);
- return ret;
+ return !(st->rx[0] & SCA3000_LOCKED);
}
/**
@@ -161,19 +136,15 @@
struct spi_message msg;
struct spi_transfer xfer[3] = {
{
- .bits_per_word = 8,
.len = 2,
.cs_change = 1,
.tx_buf = st->tx,
}, {
- .bits_per_word = 8,
.len = 2,
.cs_change = 1,
.tx_buf = st->tx + 2,
}, {
- .bits_per_word = 8,
.len = 2,
- .cs_change = 1,
.tx_buf = st->tx + 4,
},
};
@@ -236,8 +207,7 @@
* Lock must be held.
**/
static int sca3000_read_ctrl_reg(struct sca3000_state *st,
- u8 ctrl_reg,
- u8 **rx_p)
+ u8 ctrl_reg)
{
int ret;
@@ -253,8 +223,11 @@
ret = sca3000_write_reg(st, SCA3000_REG_ADDR_CTRL_SEL, ctrl_reg);
if (ret)
goto error_ret;
- ret = sca3000_read_data(st, SCA3000_REG_ADDR_CTRL_DATA, rx_p, 1);
-
+ ret = sca3000_read_data_short(st, SCA3000_REG_ADDR_CTRL_DATA, 1);
+ if (ret)
+ goto error_ret;
+ else
+ return st->rx[0];
error_ret:
return ret;
}
@@ -267,20 +240,18 @@
**/
static int sca3000_check_status(struct device *dev)
{
- u8 *rx;
int ret;
struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct sca3000_state *st = indio_dev->dev_data;
mutex_lock(&st->lock);
- ret = sca3000_read_data(st, SCA3000_REG_ADDR_STATUS, &rx, 1);
+ ret = sca3000_read_data_short(st, SCA3000_REG_ADDR_STATUS, 1);
if (ret < 0)
goto error_ret;
- if (rx[1] & SCA3000_EEPROM_CS_ERROR)
+ if (st->rx[0] & SCA3000_EEPROM_CS_ERROR)
dev_err(dev, "eeprom error\n");
- if (rx[1] & SCA3000_SPI_FRAME_ERROR)
+ if (st->rx[0] & SCA3000_SPI_FRAME_ERROR)
dev_err(dev, "Previous SPI Frame was corrupt\n");
- kfree(rx);
error_ret:
mutex_unlock(&st->lock);
@@ -288,53 +259,7 @@
}
#endif /* SCA3000_DEBUG */
-/**
- * sca3000_read_13bit_signed() sysfs interface to read 13 bit signed registers
- *
- * These are described as signed 12 bit on the data sheet, which appears
- * to be a conventional 2's complement 13 bit.
- **/
-static ssize_t sca3000_read_13bit_signed(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- int len = 0, ret;
- int val;
- struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
- u8 *rx;
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
- struct sca3000_state *st = indio_dev->dev_data;
- mutex_lock(&st->lock);
- ret = sca3000_read_data(st, this_attr->address, &rx, 2);
- if (ret < 0)
- goto error_ret;
- val = sca3000_13bit_convert(rx[1], rx[2]);
- len += sprintf(buf + len, "%d\n", val);
- kfree(rx);
-error_ret:
- mutex_unlock(&st->lock);
-
- return ret ? ret : len;
-}
-
-static ssize_t sca3000_show_scale(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- struct iio_dev *dev_info = dev_get_drvdata(dev);
- struct sca3000_state *st = dev_info->dev_data;
- return sprintf(buf, "%s\n", st->info->scale);
-}
-
-static ssize_t sca3000_show_name(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- struct iio_dev *dev_info = dev_get_drvdata(dev);
- struct sca3000_state *st = dev_info->dev_data;
- return sprintf(buf, "%s\n", st->info->name);
-}
/**
* sca3000_show_reg() - sysfs interface to read the chip revision number
**/
@@ -346,18 +271,14 @@
struct iio_dev *dev_info = dev_get_drvdata(dev);
struct sca3000_state *st = dev_info->dev_data;
- u8 *rx;
-
mutex_lock(&st->lock);
- ret = sca3000_read_data(st, SCA3000_REG_ADDR_REVID, &rx, 1);
+ ret = sca3000_read_data_short(st, SCA3000_REG_ADDR_REVID, 1);
if (ret < 0)
goto error_ret;
len += sprintf(buf + len,
"major=%d, minor=%d\n",
- rx[1] & SCA3000_REVID_MAJOR_MASK,
- rx[1] & SCA3000_REVID_MINOR_MASK);
- kfree(rx);
-
+ st->rx[0] & SCA3000_REVID_MAJOR_MASK,
+ st->rx[0] & SCA3000_REVID_MINOR_MASK);
error_ret:
mutex_unlock(&st->lock);
@@ -410,15 +331,14 @@
struct iio_dev *dev_info = dev_get_drvdata(dev);
struct sca3000_state *st = dev_info->dev_data;
int len = 0, ret;
- u8 *rx;
mutex_lock(&st->lock);
- ret = sca3000_read_data(st, SCA3000_REG_ADDR_MODE, &rx, 1);
+ ret = sca3000_read_data_short(st, SCA3000_REG_ADDR_MODE, 1);
if (ret)
goto error_ret;
/* mask bottom 2 bits - only ones that are relevant */
- rx[1] &= 0x03;
- switch (rx[1]) {
+ st->rx[0] &= 0x03;
+ switch (st->rx[0]) {
case SCA3000_MEAS_MODE_NORMAL:
len += sprintf(buf + len, "0 - normal mode\n");
break;
@@ -462,7 +382,6 @@
struct iio_dev *dev_info = dev_get_drvdata(dev);
struct sca3000_state *st = dev_info->dev_data;
int ret;
- u8 *rx;
int mask = 0x03;
long val;
@@ -470,20 +389,18 @@
ret = strict_strtol(buf, 10, &val);
if (ret)
goto error_ret;
- ret = sca3000_read_data(st, SCA3000_REG_ADDR_MODE, &rx, 1);
+ ret = sca3000_read_data_short(st, SCA3000_REG_ADDR_MODE, 1);
if (ret)
goto error_ret;
- rx[1] &= ~mask;
- rx[1] |= (val & mask);
- ret = sca3000_write_reg(st, SCA3000_REG_ADDR_MODE, rx[1]);
+ st->rx[0] &= ~mask;
+ st->rx[0] |= (val & mask);
+ ret = sca3000_write_reg(st, SCA3000_REG_ADDR_MODE, st->rx[0]);
if (ret)
- goto error_free_rx;
+ goto error_ret;
mutex_unlock(&st->lock);
return len;
-error_free_rx:
- kfree(rx);
error_ret:
mutex_unlock(&st->lock);
@@ -505,18 +422,70 @@
/* More standard attributes */
-static IIO_DEV_ATTR_NAME(sca3000_show_name);
static IIO_DEV_ATTR_REV(sca3000_show_rev);
-static IIO_DEVICE_ATTR(accel_scale, S_IRUGO, sca3000_show_scale,
- NULL, 0);
-static IIO_DEV_ATTR_ACCEL_X(sca3000_read_13bit_signed,
- SCA3000_REG_ADDR_X_MSB);
-static IIO_DEV_ATTR_ACCEL_Y(sca3000_read_13bit_signed,
- SCA3000_REG_ADDR_Y_MSB);
-static IIO_DEV_ATTR_ACCEL_Z(sca3000_read_13bit_signed,
- SCA3000_REG_ADDR_Z_MSB);
+#define SCA3000_INFO_MASK \
+ (1 << IIO_CHAN_INFO_SCALE_SHARED)
+#define SCA3000_EVENT_MASK \
+ (IIO_EV_BIT(IIO_EV_TYPE_MAG, IIO_EV_DIR_RISING))
+static struct iio_chan_spec sca3000_channels[] = {
+ IIO_CHAN(IIO_ACCEL, 1, 0, 0, NULL, 0, IIO_MOD_X, SCA3000_INFO_MASK,
+ 0, 0, IIO_ST('s', 11, 16, 5), SCA3000_EVENT_MASK),
+ IIO_CHAN(IIO_ACCEL, 1, 0, 0, NULL, 0, IIO_MOD_Y, SCA3000_INFO_MASK,
+ 1, 1, IIO_ST('s', 11, 16, 5), SCA3000_EVENT_MASK),
+ IIO_CHAN(IIO_ACCEL, 1, 0, 0, NULL, 0, IIO_MOD_Z, SCA3000_INFO_MASK,
+ 2, 2, IIO_ST('s', 11, 16, 5), SCA3000_EVENT_MASK),
+};
+
+static u8 sca3000_addresses[3][3] = {
+ [0] = {SCA3000_REG_ADDR_X_MSB, SCA3000_REG_CTRL_SEL_MD_X_TH,
+ SCA3000_MD_CTRL_OR_X},
+ [1] = {SCA3000_REG_ADDR_Y_MSB, SCA3000_REG_CTRL_SEL_MD_Y_TH,
+ SCA3000_MD_CTRL_OR_Y},
+ [2] = {SCA3000_REG_ADDR_Z_MSB, SCA3000_REG_CTRL_SEL_MD_Z_TH,
+ SCA3000_MD_CTRL_OR_Z},
+};
+
+static int sca3000_read_raw(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ int *val,
+ int *val2,
+ long mask)
+{
+ struct sca3000_state *st = indio_dev->dev_data;
+ int ret;
+ u8 address;
+
+ switch (mask) {
+ case 0:
+ mutex_lock(&st->lock);
+ if (st->mo_det_use_count) {
+ mutex_unlock(&st->lock);
+ return -EBUSY;
+ }
+ address = sca3000_addresses[chan->address][0];
+ ret = sca3000_read_data_short(st, address, 2);
+ if (ret < 0) {
+ mutex_unlock(&st->lock);
+ return ret;
+ }
+ *val = (be16_to_cpup((__be16 *)st->rx) >> 3) & 0x1FFF;
+ *val = ((*val) << (sizeof(*val)*8 - 13)) >>
+ (sizeof(*val)*8 - 13);
+ mutex_unlock(&st->lock);
+ return IIO_VAL_INT;
+ case (1 << IIO_CHAN_INFO_SCALE_SHARED):
+ *val = 0;
+ if (chan->type == IIO_ACCEL)
+ *val2 = st->info->scale;
+ else /* temperature */
+ *val2 = 555556;
+ return IIO_VAL_INT_PLUS_MICRO;
+ default:
+ return -EINVAL;
+ }
+}
/**
* sca3000_read_av_freq() sysfs function to get available frequencies
@@ -532,15 +501,16 @@
{
struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct sca3000_state *st = indio_dev->dev_data;
- int len = 0, ret;
- u8 *rx;
+ int len = 0, ret, val;
+
mutex_lock(&st->lock);
- ret = sca3000_read_data(st, SCA3000_REG_ADDR_MODE, &rx, 1);
+ ret = sca3000_read_data_short(st, SCA3000_REG_ADDR_MODE, 1);
+ val = st->rx[0];
mutex_unlock(&st->lock);
if (ret)
goto error_ret;
- rx[1] &= 0x03;
- switch (rx[1]) {
+
+ switch (val & 0x03) {
case SCA3000_MEAS_MODE_NORMAL:
len += sprintf(buf + len, "%d %d %d\n",
st->info->measurement_mode_freq,
@@ -560,7 +530,6 @@
st->info->option_mode_2_freq/4);
break;
}
- kfree(rx);
return len;
error_ret:
return ret;
@@ -575,12 +544,11 @@
int *base_freq)
{
int ret;
- u8 *rx;
- ret = sca3000_read_data(st, SCA3000_REG_ADDR_MODE, &rx, 1);
+ ret = sca3000_read_data_short(st, SCA3000_REG_ADDR_MODE, 1);
if (ret)
goto error_ret;
- switch (0x03 & rx[1]) {
+ switch (0x03 & st->rx[0]) {
case SCA3000_MEAS_MODE_NORMAL:
*base_freq = info->measurement_mode_freq;
break;
@@ -591,7 +559,6 @@
*base_freq = info->option_mode_2_freq;
break;
}
- kfree(rx);
error_ret:
return ret;
}
@@ -605,18 +572,19 @@
{
struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct sca3000_state *st = indio_dev->dev_data;
- int ret, len = 0, base_freq = 0;
- u8 *rx;
+ int ret, len = 0, base_freq = 0, val;
+
mutex_lock(&st->lock);
ret = __sca3000_get_base_freq(st, st->info, &base_freq);
if (ret)
goto error_ret_mut;
- ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL, &rx);
+ ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL);
mutex_unlock(&st->lock);
if (ret)
goto error_ret;
+ val = ret;
if (base_freq > 0)
- switch (rx[1]&0x03) {
+ switch (val & 0x03) {
case 0x00:
case 0x03:
len = sprintf(buf, "%d\n", base_freq);
@@ -628,7 +596,7 @@
len = sprintf(buf, "%d\n", base_freq/4);
break;
}
- kfree(rx);
+
return len;
error_ret_mut:
mutex_unlock(&st->lock);
@@ -647,7 +615,7 @@
struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct sca3000_state *st = indio_dev->dev_data;
int ret, base_freq = 0;
- u8 *rx;
+ int ctrlval;
long val;
ret = strict_strtol(buf, 10, &val);
@@ -660,21 +628,23 @@
if (ret)
goto error_free_lock;
- ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL, &rx);
- if (ret)
+ ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL);
+ if (ret < 0)
goto error_free_lock;
+ ctrlval = ret;
/* clear the bits */
- rx[1] &= ~0x03;
+ ctrlval &= ~0x03;
if (val == base_freq/2) {
- rx[1] |= SCA3000_OUT_CTRL_BUF_DIV_2;
+ ctrlval |= SCA3000_OUT_CTRL_BUF_DIV_2;
} else if (val == base_freq/4) {
- rx[1] |= SCA3000_OUT_CTRL_BUF_DIV_4;
+ ctrlval |= SCA3000_OUT_CTRL_BUF_DIV_4;
} else if (val != base_freq) {
ret = -EINVAL;
goto error_free_lock;
}
- ret = sca3000_write_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL, rx[1]);
+ ret = sca3000_write_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL,
+ ctrlval);
error_free_lock:
mutex_unlock(&st->lock);
@@ -704,17 +674,14 @@
{
struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct sca3000_state *st = indio_dev->dev_data;
- int len = 0, ret;
+ int ret;
int val;
- u8 *rx;
- ret = sca3000_read_data(st, SCA3000_REG_ADDR_TEMP_MSB, &rx, 2);
+ ret = sca3000_read_data_short(st, SCA3000_REG_ADDR_TEMP_MSB, 2);
if (ret < 0)
goto error_ret;
- val = ((rx[1]&0x3F) << 3) | ((rx[2] & 0xE0) >> 5);
- len += sprintf(buf + len, "%d\n", val);
- kfree(rx);
+ val = ((st->rx[0] & 0x3F) << 3) | ((st->rx[1] & 0xE0) >> 5);
- return len;
+ return sprintf(buf, "%d\n", val);
error_ret:
return ret;
@@ -725,80 +692,71 @@
static IIO_CONST_ATTR_TEMP_OFFSET("-214.6");
/**
- * sca3000_show_thresh() sysfs query of a threshold
+ * sca3000_read_thresh() - query of a threshold
**/
-static ssize_t sca3000_show_thresh(struct device *dev,
- struct device_attribute *attr,
- char *buf)
+static int sca3000_read_thresh(struct iio_dev *indio_dev,
+ int e,
+ int *val)
{
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ int ret, i;
struct sca3000_state *st = indio_dev->dev_data;
- struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
- int len = 0, ret;
- u8 *rx;
-
+ int num = IIO_EVENT_CODE_EXTRACT_MODIFIER(e);
mutex_lock(&st->lock);
- ret = sca3000_read_ctrl_reg(st,
- this_attr->address,
- &rx);
+ ret = sca3000_read_ctrl_reg(st, sca3000_addresses[num][1]);
mutex_unlock(&st->lock);
- if (ret)
+ if (ret < 0)
return ret;
- len += sprintf(buf + len, "%d\n", rx[1]);
- kfree(rx);
+ *val = 0;
+ if (num == 1)
+ for_each_set_bit(i, (unsigned long *)&ret,
+ ARRAY_SIZE(st->info->mot_det_mult_y))
+ *val += st->info->mot_det_mult_y[i];
+ else
+ for_each_set_bit(i, (unsigned long *)&ret,
+ ARRAY_SIZE(st->info->mot_det_mult_xz))
+ *val += st->info->mot_det_mult_xz[i];
- return len;
+ return 0;
}
/**
- * sca3000_write_thresh() sysfs control of threshold
+ * sca3000_write_thresh() control of threshold
**/
-static ssize_t sca3000_write_thresh(struct device *dev,
- struct device_attribute *attr,
- const char *buf,
- size_t len)
+static int sca3000_write_thresh(struct iio_dev *indio_dev,
+ int e,
+ int val)
{
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct sca3000_state *st = indio_dev->dev_data;
- struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
+ int num = IIO_EVENT_CODE_EXTRACT_MODIFIER(e);
int ret;
- long val;
+ int i;
+ u8 nonlinear = 0;
- ret = strict_strtol(buf, 10, &val);
- if (ret)
- return ret;
+ if (num == 1) {
+ i = ARRAY_SIZE(st->info->mot_det_mult_y);
+ while (i > 0)
+ if (val >= st->info->mot_det_mult_y[--i]) {
+ nonlinear |= (1 << i);
+ val -= st->info->mot_det_mult_y[i];
+ }
+ } else {
+ i = ARRAY_SIZE(st->info->mot_det_mult_xz);
+ while (i > 0)
+ if (val >= st->info->mot_det_mult_xz[--i]) {
+ nonlinear |= (1 << i);
+ val -= st->info->mot_det_mult_xz[i];
+ }
+ }
+
mutex_lock(&st->lock);
- ret = sca3000_write_ctrl_reg(st, this_attr->address, val);
+ ret = sca3000_write_ctrl_reg(st, sca3000_addresses[num][1], nonlinear);
mutex_unlock(&st->lock);
- return ret ? ret : len;
+ return ret;
}
-static IIO_DEVICE_ATTR(accel_x_raw_mag_rising_value,
- S_IRUGO | S_IWUSR,
- sca3000_show_thresh,
- sca3000_write_thresh,
- SCA3000_REG_CTRL_SEL_MD_X_TH);
-
-static IIO_DEVICE_ATTR(accel_y_raw_mag_rising_value,
- S_IRUGO | S_IWUSR,
- sca3000_show_thresh,
- sca3000_write_thresh,
- SCA3000_REG_CTRL_SEL_MD_Y_TH);
-
-static IIO_DEVICE_ATTR(accel_z_raw_mag_rising_value,
- S_IRUGO | S_IWUSR,
- sca3000_show_thresh,
- sca3000_write_thresh,
- SCA3000_REG_CTRL_SEL_MD_Z_TH);
-
static struct attribute *sca3000_attributes[] = {
- &iio_dev_attr_name.dev_attr.attr,
&iio_dev_attr_revision.dev_attr.attr,
- &iio_dev_attr_accel_scale.dev_attr.attr,
- &iio_dev_attr_accel_x_raw.dev_attr.attr,
- &iio_dev_attr_accel_y_raw.dev_attr.attr,
- &iio_dev_attr_accel_z_raw.dev_attr.attr,
&iio_dev_attr_measurement_mode_available.dev_attr.attr,
&iio_dev_attr_measurement_mode.dev_attr.attr,
&iio_dev_attr_sampling_frequency_available.dev_attr.attr,
@@ -807,12 +765,7 @@
};
static struct attribute *sca3000_attributes_with_temp[] = {
- &iio_dev_attr_name.dev_attr.attr,
&iio_dev_attr_revision.dev_attr.attr,
- &iio_dev_attr_accel_scale.dev_attr.attr,
- &iio_dev_attr_accel_x_raw.dev_attr.attr,
- &iio_dev_attr_accel_y_raw.dev_attr.attr,
- &iio_dev_attr_accel_z_raw.dev_attr.attr,
&iio_dev_attr_measurement_mode_available.dev_attr.attr,
&iio_dev_attr_measurement_mode.dev_attr.attr,
&iio_dev_attr_sampling_frequency_available.dev_attr.attr,
@@ -836,134 +789,102 @@
/* depending on event, push to the ring buffer event chrdev or the event one */
/**
- * sca3000_interrupt_handler_bh() - handling ring and non ring events
+ * sca3000_event_handler() - handling ring and non ring events
*
* This function is complicated by the fact that the devices can signify ring
* and non ring events via the same interrupt line and they can only
* be distinguished via a read of the relevant status register.
**/
-static void sca3000_interrupt_handler_bh(struct work_struct *work_s)
+static irqreturn_t sca3000_event_handler(int irq, void *private)
{
- struct sca3000_state *st
- = container_of(work_s, struct sca3000_state,
- interrupt_handler_ws);
- u8 *rx;
- int ret;
+ struct iio_dev *indio_dev = private;
+ struct sca3000_state *st;
+ int ret, val;
+ s64 last_timestamp = iio_get_time_ns();
+ st = indio_dev->dev_data;
/* Could lead if badly timed to an extra read of status reg,
* but ensures no interrupt is missed.
*/
- enable_irq(st->us->irq);
mutex_lock(&st->lock);
- ret = sca3000_read_data(st, SCA3000_REG_ADDR_INT_STATUS,
- &rx, 1);
+ ret = sca3000_read_data_short(st, SCA3000_REG_ADDR_INT_STATUS, 1);
+ val = st->rx[0];
mutex_unlock(&st->lock);
if (ret)
goto done;
- sca3000_ring_int_process(rx[1], st->indio_dev->ring);
+ sca3000_ring_int_process(val, st->indio_dev->ring);
- if (rx[1] & SCA3000_INT_STATUS_FREE_FALL)
+ if (val & SCA3000_INT_STATUS_FREE_FALL)
iio_push_event(st->indio_dev, 0,
IIO_MOD_EVENT_CODE(IIO_EV_CLASS_ACCEL,
0,
IIO_EV_MOD_X_AND_Y_AND_Z,
IIO_EV_TYPE_MAG,
IIO_EV_DIR_FALLING),
- st->last_timestamp);
+ last_timestamp);
- if (rx[1] & SCA3000_INT_STATUS_Y_TRIGGER)
+ if (val & SCA3000_INT_STATUS_Y_TRIGGER)
iio_push_event(st->indio_dev, 0,
IIO_MOD_EVENT_CODE(IIO_EV_CLASS_ACCEL,
0,
IIO_EV_MOD_Y,
IIO_EV_TYPE_MAG,
IIO_EV_DIR_RISING),
- st->last_timestamp);
+ last_timestamp);
- if (rx[1] & SCA3000_INT_STATUS_X_TRIGGER)
+ if (val & SCA3000_INT_STATUS_X_TRIGGER)
iio_push_event(st->indio_dev, 0,
IIO_MOD_EVENT_CODE(IIO_EV_CLASS_ACCEL,
0,
IIO_EV_MOD_X,
IIO_EV_TYPE_MAG,
IIO_EV_DIR_RISING),
- st->last_timestamp);
+ last_timestamp);
- if (rx[1] & SCA3000_INT_STATUS_Z_TRIGGER)
+ if (val & SCA3000_INT_STATUS_Z_TRIGGER)
iio_push_event(st->indio_dev, 0,
IIO_MOD_EVENT_CODE(IIO_EV_CLASS_ACCEL,
0,
IIO_EV_MOD_Z,
IIO_EV_TYPE_MAG,
IIO_EV_DIR_RISING),
- st->last_timestamp);
+ last_timestamp);
done:
- kfree(rx);
- return;
+ return IRQ_HANDLED;
}
/**
- * sca3000_handler_th() handles all interrupt events from device
- *
- * These devices deploy unified interrupt status registers meaning
- * all interrupts must be handled together
+ * sca3000_read_event_config() what events are enabled
**/
-static int sca3000_handler_th(struct iio_dev *dev_info,
- int index,
- s64 timestamp,
- int no_test)
+static int sca3000_read_event_config(struct iio_dev *indio_dev,
+ int e)
{
- struct sca3000_state *st = dev_info->dev_data;
-
- st->last_timestamp = timestamp;
- schedule_work(&st->interrupt_handler_ws);
-
- return 0;
-}
-
-/**
- * sca3000_query_mo_det() is motion detection enabled for this axis
- *
- * First queries if motion detection is enabled and then if this axis is
- * on.
- **/
-static ssize_t sca3000_query_mo_det(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- struct iio_dev *indio_dev = dev_get_drvdata(dev->parent);
struct sca3000_state *st = indio_dev->dev_data;
- struct iio_event_attr *this_attr = to_iio_event_attr(attr);
- int ret, len = 0;
- u8 *rx;
+ int ret;
u8 protect_mask = 0x03;
+ int num = IIO_EVENT_CODE_EXTRACT_MODIFIER(e);
/* read current value of mode register */
mutex_lock(&st->lock);
- ret = sca3000_read_data(st, SCA3000_REG_ADDR_MODE, &rx, 1);
+ ret = sca3000_read_data_short(st, SCA3000_REG_ADDR_MODE, 1);
if (ret)
goto error_ret;
- if ((rx[1]&protect_mask) != SCA3000_MEAS_MODE_MOT_DET)
- len += sprintf(buf + len, "0\n");
+ if ((st->rx[0] & protect_mask) != SCA3000_MEAS_MODE_MOT_DET)
+ ret = 0;
else {
- kfree(rx);
- ret = sca3000_read_ctrl_reg(st,
- SCA3000_REG_CTRL_SEL_MD_CTRL,
- &rx);
- if (ret)
+ ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_MD_CTRL);
+ if (ret < 0)
goto error_ret;
/* only supporting logical or's for now */
- len += sprintf(buf + len, "%d\n",
- (rx[1] & this_attr->mask) ? 1 : 0);
+ ret = !!(ret & sca3000_addresses[num][2]);
}
- kfree(rx);
error_ret:
mutex_unlock(&st->lock);
- return ret ? ret : len;
+ return ret;
}
/**
* sca3000_query_free_fall_mode() is free fall mode enabled
@@ -973,80 +894,20 @@
char *buf)
{
int ret, len;
- u8 *rx;
struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct sca3000_state *st = indio_dev->dev_data;
+ int val;
mutex_lock(&st->lock);
- ret = sca3000_read_data(st, SCA3000_REG_ADDR_MODE, &rx, 1);
+ ret = sca3000_read_data_short(st, SCA3000_REG_ADDR_MODE, 1);
+ val = st->rx[0];
mutex_unlock(&st->lock);
- if (ret)
+ if (ret < 0)
return ret;
len = sprintf(buf, "%d\n",
- !!(rx[1] & SCA3000_FREE_FALL_DETECT));
- kfree(rx);
-
+ !!(val & SCA3000_FREE_FALL_DETECT));
return len;
}
-/**
- * sca3000_query_ring_int() is the hardware ring status interrupt enabled
- **/
-static ssize_t sca3000_query_ring_int(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- struct iio_event_attr *this_attr = to_iio_event_attr(attr);
- int ret, len;
- u8 *rx;
- struct iio_dev *indio_dev = dev_get_drvdata(dev->parent);
- struct sca3000_state *st = indio_dev->dev_data;
- mutex_lock(&st->lock);
- ret = sca3000_read_data(st, SCA3000_REG_ADDR_INT_MASK, &rx, 1);
- mutex_unlock(&st->lock);
- if (ret)
- return ret;
- len = sprintf(buf, "%d\n", (rx[1] & this_attr->mask) ? 1 : 0);
- kfree(rx);
-
- return len;
-}
-/**
- * sca3000_set_ring_int() set state of ring status interrupt
- **/
-static ssize_t sca3000_set_ring_int(struct device *dev,
- struct device_attribute *attr,
- const char *buf,
- size_t len)
-{
- struct iio_dev *indio_dev = dev_get_drvdata(dev->parent);
- struct sca3000_state *st = indio_dev->dev_data;
- struct iio_event_attr *this_attr = to_iio_event_attr(attr);
-
- long val;
- int ret;
- u8 *rx;
-
- mutex_lock(&st->lock);
- ret = strict_strtol(buf, 10, &val);
- if (ret)
- goto error_ret;
- ret = sca3000_read_data(st, SCA3000_REG_ADDR_INT_MASK, &rx, 1);
- if (ret)
- goto error_ret;
- if (val)
- ret = sca3000_write_reg(st,
- SCA3000_REG_ADDR_INT_MASK,
- rx[1] | this_attr->mask);
- else
- ret = sca3000_write_reg(st,
- SCA3000_REG_ADDR_INT_MASK,
- rx[1] & ~this_attr->mask);
- kfree(rx);
-error_ret:
- mutex_unlock(&st->lock);
-
- return ret ? ret : len;
-}
/**
* sca3000_set_free_fall_mode() simple on off control for free fall int
@@ -1065,7 +926,6 @@
struct sca3000_state *st = indio_dev->dev_data;
long val;
int ret;
- u8 *rx;
u8 protect_mask = SCA3000_FREE_FALL_DETECT;
mutex_lock(&st->lock);
@@ -1074,20 +934,18 @@
goto error_ret;
/* read current value of mode register */
- ret = sca3000_read_data(st, SCA3000_REG_ADDR_MODE, &rx, 1);
+ ret = sca3000_read_data_short(st, SCA3000_REG_ADDR_MODE, 1);
if (ret)
goto error_ret;
/*if off and should be on*/
- if (val && !(rx[1] & protect_mask))
+ if (val && !(st->rx[0] & protect_mask))
ret = sca3000_write_reg(st, SCA3000_REG_ADDR_MODE,
- (rx[1] | SCA3000_FREE_FALL_DETECT));
+ (st->rx[0] | SCA3000_FREE_FALL_DETECT));
/* if on and should be off */
- else if (!val && (rx[1]&protect_mask))
+ else if (!val && (st->rx[0] & protect_mask))
ret = sca3000_write_reg(st, SCA3000_REG_ADDR_MODE,
- (rx[1] & ~protect_mask));
-
- kfree(rx);
+ (st->rx[0] & ~protect_mask));
error_ret:
mutex_unlock(&st->lock);
@@ -1103,127 +961,77 @@
* There is a complexity in knowing which mode to return to when
* this mode is disabled. Currently normal mode is assumed.
**/
-static ssize_t sca3000_set_mo_det(struct device *dev,
- struct device_attribute *attr,
- const char *buf,
- size_t len)
+static int sca3000_write_event_config(struct iio_dev *indio_dev,
+ int e,
+ int state)
{
- struct iio_dev *indio_dev = dev_get_drvdata(dev->parent);
struct sca3000_state *st = indio_dev->dev_data;
- struct iio_event_attr *this_attr = to_iio_event_attr(attr);
- long val;
- int ret;
- u8 *rx;
+ int ret, ctrlval;
u8 protect_mask = 0x03;
- ret = strict_strtol(buf, 10, &val);
- if (ret)
- return ret;
+ int num = IIO_EVENT_CODE_EXTRACT_MODIFIER(e);
mutex_lock(&st->lock);
/* First read the motion detector config to find out if
* this axis is on*/
- ret = sca3000_read_ctrl_reg(st,
- SCA3000_REG_CTRL_SEL_MD_CTRL,
- &rx);
- if (ret)
+ ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_MD_CTRL);
+ if (ret < 0)
goto exit_point;
+ ctrlval = ret;
/* Off and should be on */
- if (val && !(rx[1] & this_attr->mask)) {
+ if (state && !(ctrlval & sca3000_addresses[num][2])) {
ret = sca3000_write_ctrl_reg(st,
SCA3000_REG_CTRL_SEL_MD_CTRL,
- rx[1] | this_attr->mask);
+ ctrlval |
+ sca3000_addresses[num][2]);
if (ret)
- goto exit_point_free_rx;
+ goto exit_point;
st->mo_det_use_count++;
- } else if (!val && (rx[1]&this_attr->mask)) {
+ } else if (!state && (ctrlval & sca3000_addresses[num][2])) {
ret = sca3000_write_ctrl_reg(st,
SCA3000_REG_CTRL_SEL_MD_CTRL,
- rx[1] & ~(this_attr->mask));
+ ctrlval &
+ ~(sca3000_addresses[num][2]));
if (ret)
- goto exit_point_free_rx;
+ goto exit_point;
st->mo_det_use_count--;
- } else /* relies on clean state for device on boot */
- goto exit_point_free_rx;
- kfree(rx);
+ }
+
/* read current value of mode register */
- ret = sca3000_read_data(st, SCA3000_REG_ADDR_MODE, &rx, 1);
+ ret = sca3000_read_data_short(st, SCA3000_REG_ADDR_MODE, 1);
if (ret)
goto exit_point;
/*if off and should be on*/
if ((st->mo_det_use_count)
- && ((rx[1]&protect_mask) != SCA3000_MEAS_MODE_MOT_DET))
+ && ((st->rx[0] & protect_mask) != SCA3000_MEAS_MODE_MOT_DET))
ret = sca3000_write_reg(st, SCA3000_REG_ADDR_MODE,
- (rx[1] & ~protect_mask)
+ (st->rx[0] & ~protect_mask)
| SCA3000_MEAS_MODE_MOT_DET);
/* if on and should be off */
else if (!(st->mo_det_use_count)
- && ((rx[1]&protect_mask) == SCA3000_MEAS_MODE_MOT_DET))
+ && ((st->rx[0] & protect_mask) == SCA3000_MEAS_MODE_MOT_DET))
ret = sca3000_write_reg(st, SCA3000_REG_ADDR_MODE,
- (rx[1] & ~protect_mask));
-exit_point_free_rx:
- kfree(rx);
+ (st->rx[0] & ~protect_mask));
exit_point:
mutex_unlock(&st->lock);
- return ret ? ret : len;
+ return ret;
}
-/* Shared event handler for all events as single event status register */
-IIO_EVENT_SH(all, &sca3000_handler_th);
-
/* Free fall detector related event attribute */
-IIO_EVENT_ATTR_NAMED_SH(accel_xayaz_mag_falling_en,
- accel_x&y&z_mag_falling_en,
- iio_event_all,
- sca3000_query_free_fall_mode,
- sca3000_set_free_fall_mode,
- 0);
+static IIO_DEVICE_ATTR_NAMED(accel_xayaz_mag_falling_en,
+ accel_x&y&z_mag_falling_en,
+ S_IRUGO | S_IWUSR,
+ sca3000_query_free_fall_mode,
+ sca3000_set_free_fall_mode,
+ 0);
-IIO_CONST_ATTR_NAMED(accel_xayaz_mag_falling_period,
- accel_x&y&z_mag_falling_period,
- "0.226");
-
-/* Motion detector related event attributes */
-IIO_EVENT_ATTR_SH(accel_x_mag_rising_en,
- iio_event_all,
- sca3000_query_mo_det,
- sca3000_set_mo_det,
- SCA3000_MD_CTRL_OR_X);
-
-IIO_EVENT_ATTR_SH(accel_y_mag_rising_en,
- iio_event_all,
- sca3000_query_mo_det,
- sca3000_set_mo_det,
- SCA3000_MD_CTRL_OR_Y);
-
-IIO_EVENT_ATTR_SH(accel_z_mag_rising_en,
- iio_event_all,
- sca3000_query_mo_det,
- sca3000_set_mo_det,
- SCA3000_MD_CTRL_OR_Z);
-
-/* Hardware ring buffer related event attributes */
-IIO_EVENT_ATTR_RING_50_FULL_SH(iio_event_all,
- sca3000_query_ring_int,
- sca3000_set_ring_int,
- SCA3000_INT_MASK_RING_HALF);
-
-IIO_EVENT_ATTR_RING_75_FULL_SH(iio_event_all,
- sca3000_query_ring_int,
- sca3000_set_ring_int,
- SCA3000_INT_MASK_RING_THREE_QUARTER);
+static IIO_CONST_ATTR_NAMED(accel_xayaz_mag_falling_period,
+ accel_x&y&z_mag_falling_period,
+ "0.226");
static struct attribute *sca3000_event_attributes[] = {
- &iio_event_attr_accel_xayaz_mag_falling_en.dev_attr.attr,
+ &iio_dev_attr_accel_xayaz_mag_falling_en.dev_attr.attr,
&iio_const_attr_accel_xayaz_mag_falling_period.dev_attr.attr,
- &iio_event_attr_accel_x_mag_rising_en.dev_attr.attr,
- &iio_dev_attr_accel_x_raw_mag_rising_value.dev_attr.attr,
- &iio_event_attr_accel_y_mag_rising_en.dev_attr.attr,
- &iio_dev_attr_accel_y_raw_mag_rising_value.dev_attr.attr,
- &iio_event_attr_accel_z_mag_rising_en.dev_attr.attr,
- &iio_dev_attr_accel_z_raw_mag_rising_value.dev_attr.attr,
- &iio_event_attr_ring_50_full.dev_attr.attr,
- &iio_event_attr_ring_75_full.dev_attr.attr,
NULL,
};
@@ -1241,70 +1049,50 @@
static int sca3000_clean_setup(struct sca3000_state *st)
{
int ret;
- u8 *rx;
mutex_lock(&st->lock);
/* Ensure all interrupts have been acknowledged */
- ret = sca3000_read_data(st, SCA3000_REG_ADDR_INT_STATUS, &rx, 1);
+ ret = sca3000_read_data_short(st, SCA3000_REG_ADDR_INT_STATUS, 1);
if (ret)
goto error_ret;
- kfree(rx);
/* Turn off all motion detection channels */
- ret = sca3000_read_ctrl_reg(st,
- SCA3000_REG_CTRL_SEL_MD_CTRL,
- &rx);
- if (ret)
+ ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_MD_CTRL);
+ if (ret < 0)
goto error_ret;
- ret = sca3000_write_ctrl_reg(st,
- SCA3000_REG_CTRL_SEL_MD_CTRL,
- rx[1] & SCA3000_MD_CTRL_PROT_MASK);
- kfree(rx);
+ ret = sca3000_write_ctrl_reg(st, SCA3000_REG_CTRL_SEL_MD_CTRL,
+ ret & SCA3000_MD_CTRL_PROT_MASK);
if (ret)
goto error_ret;
/* Disable ring buffer */
- sca3000_read_ctrl_reg(st,
- SCA3000_REG_CTRL_SEL_OUT_CTRL,
- &rx);
- /* Frequency of ring buffer sampling deliberately restricted to make
- * debugging easier - add control of this later */
- ret = sca3000_write_ctrl_reg(st,
- SCA3000_REG_CTRL_SEL_OUT_CTRL,
- (rx[1] & SCA3000_OUT_CTRL_PROT_MASK)
+ ret = sca3000_read_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL);
+ ret = sca3000_write_ctrl_reg(st, SCA3000_REG_CTRL_SEL_OUT_CTRL,
+ (ret & SCA3000_OUT_CTRL_PROT_MASK)
| SCA3000_OUT_CTRL_BUF_X_EN
| SCA3000_OUT_CTRL_BUF_Y_EN
| SCA3000_OUT_CTRL_BUF_Z_EN
| SCA3000_OUT_CTRL_BUF_DIV_4);
- kfree(rx);
-
if (ret)
goto error_ret;
/* Enable interrupts, relevant to mode and set up as active low */
- ret = sca3000_read_data(st,
- SCA3000_REG_ADDR_INT_MASK,
- &rx, 1);
+ ret = sca3000_read_data_short(st, SCA3000_REG_ADDR_INT_MASK, 1);
if (ret)
goto error_ret;
ret = sca3000_write_reg(st,
SCA3000_REG_ADDR_INT_MASK,
- (rx[1] & SCA3000_INT_MASK_PROT_MASK)
+ (ret & SCA3000_INT_MASK_PROT_MASK)
| SCA3000_INT_MASK_ACTIVE_LOW);
- kfree(rx);
if (ret)
goto error_ret;
/* Select normal measurement mode, free fall off, ring off */
/* Ring in 12 bit mode - it is fine to overwrite reserved bits 3,5
* as that occurs in one of the example on the datasheet */
- ret = sca3000_read_data(st,
- SCA3000_REG_ADDR_MODE,
- &rx, 1);
+ ret = sca3000_read_data_short(st, SCA3000_REG_ADDR_MODE, 1);
if (ret)
goto error_ret;
- ret = sca3000_write_reg(st,
- SCA3000_REG_ADDR_MODE,
- (rx[1] & SCA3000_MODE_PROT_MASK));
- kfree(rx);
+ ret = sca3000_write_reg(st, SCA3000_REG_ADDR_MODE,
+ (st->rx[0] & SCA3000_MODE_PROT_MASK));
st->bpse = 11;
error_ret:
@@ -1312,8 +1100,29 @@
return ret;
}
-static int __devinit __sca3000_probe(struct spi_device *spi,
- enum sca3000_variant variant)
+static const struct iio_info sca3000_info = {
+ .attrs = &sca3000_attribute_group,
+ .read_raw = &sca3000_read_raw,
+ .num_interrupt_lines = 1,
+ .event_attrs = &sca3000_event_attribute_group,
+ .read_event_value = &sca3000_read_thresh,
+ .write_event_value = &sca3000_write_thresh,
+ .read_event_config = &sca3000_read_event_config,
+ .write_event_config = &sca3000_write_event_config,
+ .driver_module = THIS_MODULE,
+};
+
+static const struct iio_info sca3000_info_with_temp = {
+ .attrs = &sca3000_attribute_group_with_temp,
+ .read_raw = &sca3000_read_raw,
+ .read_event_value = &sca3000_read_thresh,
+ .write_event_value = &sca3000_write_thresh,
+ .read_event_config = &sca3000_read_event_config,
+ .write_event_config = &sca3000_write_event_config,
+ .driver_module = THIS_MODULE,
+};
+
+static int __devinit sca3000_probe(struct spi_device *spi)
{
int ret, regdone = 0;
struct sca3000_state *st;
@@ -1325,75 +1134,57 @@
}
spi_set_drvdata(spi, st);
- st->tx = kmalloc(sizeof(*st->tx)*6, GFP_KERNEL);
- if (st->tx == NULL) {
+ st->us = spi;
+ mutex_init(&st->lock);
+ st->info = &sca3000_spi_chip_info_tbl[spi_get_device_id(spi)
+ ->driver_data];
+
+ st->indio_dev = iio_allocate_device(0);
+ if (st->indio_dev == NULL) {
ret = -ENOMEM;
goto error_clear_st;
}
- st->rx = kmalloc(sizeof(*st->rx)*3, GFP_KERNEL);
- if (st->rx == NULL) {
- ret = -ENOMEM;
- goto error_free_tx;
- }
- st->us = spi;
- mutex_init(&st->lock);
- st->info = &sca3000_spi_chip_info_tbl[variant];
-
- st->indio_dev = iio_allocate_device();
- if (st->indio_dev == NULL) {
- ret = -ENOMEM;
- goto error_free_rx;
- }
-
st->indio_dev->dev.parent = &spi->dev;
- st->indio_dev->num_interrupt_lines = 1;
- st->indio_dev->event_attrs = &sca3000_event_attribute_group;
+ st->indio_dev->name = spi_get_device_id(spi)->name;
if (st->info->temp_output)
- st->indio_dev->attrs = &sca3000_attribute_group_with_temp;
- else
- st->indio_dev->attrs = &sca3000_attribute_group;
+ st->indio_dev->info = &sca3000_info_with_temp;
+ else {
+ st->indio_dev->info = &sca3000_info;
+ st->indio_dev->channels = sca3000_channels;
+ st->indio_dev->num_channels = ARRAY_SIZE(sca3000_channels);
+ }
st->indio_dev->dev_data = (void *)(st);
st->indio_dev->modes = INDIO_DIRECT_MODE;
sca3000_configure_ring(st->indio_dev);
-
ret = iio_device_register(st->indio_dev);
if (ret < 0)
goto error_free_dev;
regdone = 1;
- ret = iio_ring_buffer_register(st->indio_dev->ring, 0);
+ ret = iio_ring_buffer_register_ex(st->indio_dev->ring, 0,
+ sca3000_channels,
+ ARRAY_SIZE(sca3000_channels));
if (ret < 0)
goto error_unregister_dev;
if (spi->irq && gpio_is_valid(irq_to_gpio(spi->irq)) > 0) {
- INIT_WORK(&st->interrupt_handler_ws,
- sca3000_interrupt_handler_bh);
- ret = iio_register_interrupt_line(spi->irq,
- st->indio_dev,
- 0,
- IRQF_TRIGGER_FALLING,
- "sca3000");
+ ret = request_threaded_irq(spi->irq,
+ NULL,
+ &sca3000_event_handler,
+ IRQF_TRIGGER_FALLING,
+ "sca3000",
+ st->indio_dev);
if (ret)
goto error_unregister_ring;
- /* RFC
- * Probably a common situation. All interrupts need an ack
- * and there is only one handler so the complicated list system
- * is overkill. At very least a simpler registration method
- * might be worthwhile.
- */
- iio_add_event_to_list(
- iio_event_attr_accel_z_mag_rising_en.listel,
- &st->indio_dev
- ->interrupts[0]->ev_list);
}
sca3000_register_ring_funcs(st->indio_dev);
ret = sca3000_clean_setup(st);
if (ret)
- goto error_unregister_interrupt_line;
+ goto error_free_irq;
return 0;
-error_unregister_interrupt_line:
+error_free_irq:
if (spi->irq && gpio_is_valid(irq_to_gpio(spi->irq)) > 0)
- iio_unregister_interrupt_line(st->indio_dev, 0);
+ free_irq(spi->irq, st->indio_dev);
error_unregister_ring:
iio_ring_buffer_unregister(st->indio_dev->ring);
error_unregister_dev:
@@ -1402,10 +1193,6 @@
iio_device_unregister(st->indio_dev);
else
iio_free_device(st->indio_dev);
-error_free_rx:
- kfree(st->rx);
-error_free_tx:
- kfree(st->tx);
error_clear_st:
kfree(st);
error_ret:
@@ -1415,20 +1202,19 @@
static int sca3000_stop_all_interrupts(struct sca3000_state *st)
{
int ret;
- u8 *rx;
mutex_lock(&st->lock);
- ret = sca3000_read_data(st, SCA3000_REG_ADDR_INT_MASK, &rx, 1);
+ ret = sca3000_read_data_short(st, SCA3000_REG_ADDR_INT_MASK, 1);
if (ret)
goto error_ret;
ret = sca3000_write_reg(st, SCA3000_REG_ADDR_INT_MASK,
- (rx[1] & ~(SCA3000_INT_MASK_RING_THREE_QUARTER
- | SCA3000_INT_MASK_RING_HALF
- | SCA3000_INT_MASK_ALL_INTS)));
+ (st->rx[0] &
+ ~(SCA3000_INT_MASK_RING_THREE_QUARTER |
+ SCA3000_INT_MASK_RING_HALF |
+ SCA3000_INT_MASK_ALL_INTS)));
error_ret:
- kfree(rx);
+ mutex_unlock(&st->lock);
return ret;
-
}
static int sca3000_remove(struct spi_device *spi)
@@ -1441,87 +1227,44 @@
if (ret)
return ret;
if (spi->irq && gpio_is_valid(irq_to_gpio(spi->irq)) > 0)
- iio_unregister_interrupt_line(indio_dev, 0);
+ free_irq(spi->irq, indio_dev);
iio_ring_buffer_unregister(indio_dev->ring);
sca3000_unconfigure_ring(indio_dev);
iio_device_unregister(indio_dev);
- kfree(st->tx);
- kfree(st->rx);
kfree(st);
return 0;
}
-/* These macros save on an awful lot of repeated code */
-#define SCA3000_VARIANT_PROBE(_name) \
- static int __devinit \
- sca3000_##_name##_probe(struct spi_device *spi) \
- { \
- return __sca3000_probe(spi, _name); \
- }
+static const struct spi_device_id sca3000_id[] = {
+ {"sca3000_d01", d01},
+ {"sca3000_e02", e02},
+ {"sca3000_e04", e04},
+ {"sca3000_e05", e05},
+ {}
+};
-#define SCA3000_VARIANT_SPI_DRIVER(_name) \
- struct spi_driver sca3000_##_name##_driver = { \
- .driver = { \
- .name = "sca3000_" #_name, \
- .owner = THIS_MODULE, \
- }, \
- .probe = sca3000_##_name##_probe, \
- .remove = __devexit_p(sca3000_remove), \
- }
-
-SCA3000_VARIANT_PROBE(d01);
-static SCA3000_VARIANT_SPI_DRIVER(d01);
-
-SCA3000_VARIANT_PROBE(e02);
-static SCA3000_VARIANT_SPI_DRIVER(e02);
-
-SCA3000_VARIANT_PROBE(e04);
-static SCA3000_VARIANT_SPI_DRIVER(e04);
-
-SCA3000_VARIANT_PROBE(e05);
-static SCA3000_VARIANT_SPI_DRIVER(e05);
+static struct spi_driver sca3000_driver = {
+ .driver = {
+ .name = "sca3000",
+ .owner = THIS_MODULE,
+ },
+ .probe = sca3000_probe,
+ .remove = __devexit_p(sca3000_remove),
+ .id_table = sca3000_id,
+};
static __init int sca3000_init(void)
{
- int ret;
-
- ret = spi_register_driver(&sca3000_d01_driver);
- if (ret)
- goto error_ret;
- ret = spi_register_driver(&sca3000_e02_driver);
- if (ret)
- goto error_unreg_d01;
- ret = spi_register_driver(&sca3000_e04_driver);
- if (ret)
- goto error_unreg_e02;
- ret = spi_register_driver(&sca3000_e05_driver);
- if (ret)
- goto error_unreg_e04;
-
- return 0;
-
-error_unreg_e04:
- spi_unregister_driver(&sca3000_e04_driver);
-error_unreg_e02:
- spi_unregister_driver(&sca3000_e02_driver);
-error_unreg_d01:
- spi_unregister_driver(&sca3000_d01_driver);
-error_ret:
-
- return ret;
+ return spi_register_driver(&sca3000_driver);
}
+module_init(sca3000_init);
static __exit void sca3000_exit(void)
{
- spi_unregister_driver(&sca3000_e05_driver);
- spi_unregister_driver(&sca3000_e04_driver);
- spi_unregister_driver(&sca3000_e02_driver);
- spi_unregister_driver(&sca3000_d01_driver);
+ spi_unregister_driver(&sca3000_driver);
}
-
-module_init(sca3000_init);
module_exit(sca3000_exit);
MODULE_AUTHOR("Jonathan Cameron <jic23@cam.ac.uk>");
diff --git a/drivers/staging/iio/accel/sca3000_ring.c b/drivers/staging/iio/accel/sca3000_ring.c
index a730a76..7c4ff0b 100644
--- a/drivers/staging/iio/accel/sca3000_ring.c
+++ b/drivers/staging/iio/accel/sca3000_ring.c
@@ -17,6 +17,8 @@
#include <linux/kernel.h>
#include <linux/spi/spi.h>
#include <linux/sysfs.h>
+#include <linux/sched.h>
+#include <linux/poll.h>
#include "../iio.h"
#include "../sysfs.h"
@@ -34,26 +36,61 @@
* Currently scan elements aren't configured so it doesn't matter.
*/
+static int sca3000_read_data(struct sca3000_state *st,
+ uint8_t reg_address_high,
+ u8 **rx_p,
+ int len)
+{
+ int ret;
+ struct spi_message msg;
+ struct spi_transfer xfer[2] = {
+ {
+ .len = 1,
+ .tx_buf = st->tx,
+ }, {
+ .len = len,
+ }
+ };
+ *rx_p = kmalloc(len, GFP_KERNEL);
+ if (*rx_p == NULL) {
+ ret = -ENOMEM;
+ goto error_ret;
+ }
+ xfer[1].rx_buf = *rx_p;
+ st->tx[0] = SCA3000_READ_REG(reg_address_high);
+ spi_message_init(&msg);
+ spi_message_add_tail(&xfer[0], &msg);
+ spi_message_add_tail(&xfer[1], &msg);
+ ret = spi_sync(st->us, &msg);
+ if (ret) {
+ dev_err(get_device(&st->us->dev), "problem reading register");
+ goto error_free_rx;
+ }
+
+ return 0;
+error_free_rx:
+ kfree(*rx_p);
+error_ret:
+ return ret;
+}
+
/**
- * sca3000_rip_hw_rb() - main ring access function, pulls data from ring
+ * sca3000_read_first_n_hw_rb() - main ring access, pulls data from ring
* @r: the ring
* @count: number of samples to try and pull
* @data: output the actual samples pulled from the hw ring
- * @dead_offset: cheating a bit here: Set to 1 so as to allow for the
- * leading byte used in bus comms.
*
* Currently does not provide timestamps. As the hardware doesn't add them they
* can only be inferred approximately from ring buffer events such as 50% full
* and knowledge of when buffer was last emptied. This is left to userspace.
**/
-static int sca3000_rip_hw_rb(struct iio_ring_buffer *r,
- size_t count, u8 **data, int *dead_offset)
+static int sca3000_read_first_n_hw_rb(struct iio_ring_buffer *r,
+ size_t count, char __user *buf)
{
struct iio_hw_ring_buffer *hw_ring = iio_to_hw_ring_buf(r);
struct iio_dev *indio_dev = hw_ring->private;
struct sca3000_state *st = indio_dev->dev_data;
u8 *rx;
- s16 *samples;
int ret, i, num_available, num_read = 0;
int bytes_per_sample = 1;
@@ -61,44 +98,38 @@
bytes_per_sample = 2;
mutex_lock(&st->lock);
- /* Check how much data is available:
- * RFC: Implement an ioctl to not bother checking whether there
- * is enough data in the ring? Afterall, if we are responding
- * to an interrupt we have a minimum content guaranteed so it
- * seems slight silly to waste time checking it is there.
- */
- ret = sca3000_read_data(st,
- SCA3000_REG_ADDR_BUF_COUNT,
- &rx, 1);
+ if (count % bytes_per_sample) {
+ ret = -EINVAL;
+ goto error_ret;
+ }
+
+ ret = sca3000_read_data_short(st, SCA3000_REG_ADDR_BUF_COUNT, 1);
if (ret)
goto error_ret;
else
- num_available = rx[1];
- /* num_available is the total number of samples available
+ num_available = st->rx[0];
+ /*
+ * num_available is the total number of samples available
* i.e. number of time points * number of channels.
*/
- kfree(rx);
if (count > num_available * bytes_per_sample)
num_read = num_available*bytes_per_sample;
else
- num_read = count - (count % (bytes_per_sample));
+ num_read = count;
- /* Avoid the read request byte */
- *dead_offset = 1;
ret = sca3000_read_data(st,
SCA3000_REG_ADDR_RING_OUT,
- data, num_read);
+ &rx, num_read);
+ if (ret)
+ goto error_ret;
- /* Convert byte order and shift to default resolution */
- if (st->bpse == 11) {
- samples = (s16*)(*data+1);
- for (i = 0; i < (num_read/2); i++) {
- samples[i] = be16_to_cpup(
- (__be16 *)&(samples[i]));
- samples[i] >>= 3;
- }
- }
+ for (i = 0; i < num_read; i++)
+ *(((u16 *)rx) + i) = be16_to_cpup((u16 *)rx + i);
+ if (copy_to_user(buf, rx, num_read))
+ ret = -EFAULT;
+ kfree(rx);
+ r->stufftoread = 0;
error_ret:
mutex_unlock(&st->lock);
@@ -127,6 +158,76 @@
static IIO_RING_LENGTH_ATTR;
/**
+ * sca3000_query_ring_int() is the hardware ring status interrupt enabled
+ **/
+static ssize_t sca3000_query_ring_int(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
+ int ret, val;
+ struct iio_ring_buffer *ring = dev_get_drvdata(dev);
+ struct iio_dev *indio_dev = ring->indio_dev;
+ struct sca3000_state *st = indio_dev->dev_data;
+
+ mutex_lock(&st->lock);
+ ret = sca3000_read_data_short(st, SCA3000_REG_ADDR_INT_MASK, 1);
+ val = st->rx[0];
+ mutex_unlock(&st->lock);
+ if (ret)
+ return ret;
+
+ return sprintf(buf, "%d\n", !!(val & this_attr->address));
+}
+
+/**
+ * sca3000_set_ring_int() set state of ring status interrupt
+ **/
+static ssize_t sca3000_set_ring_int(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf,
+ size_t len)
+{
+ struct iio_ring_buffer *ring = dev_get_drvdata(dev);
+ struct iio_dev *indio_dev = ring->indio_dev;
+ struct sca3000_state *st = indio_dev->dev_data;
+ struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
+ long val;
+ int ret;
+
+ mutex_lock(&st->lock);
+ ret = strict_strtol(buf, 10, &val);
+ if (ret)
+ goto error_ret;
+ ret = sca3000_read_data_short(st, SCA3000_REG_ADDR_INT_MASK, 1);
+ if (ret)
+ goto error_ret;
+ if (val)
+ ret = sca3000_write_reg(st,
+ SCA3000_REG_ADDR_INT_MASK,
+ st->rx[0] | this_attr->address);
+ else
+ ret = sca3000_write_reg(st,
+ SCA3000_REG_ADDR_INT_MASK,
+ st->rx[0] & ~this_attr->address);
+error_ret:
+ mutex_unlock(&st->lock);
+
+ return ret ? ret : len;
+}
+
+static IIO_DEVICE_ATTR(50_percent, S_IRUGO | S_IWUSR,
+ sca3000_query_ring_int,
+ sca3000_set_ring_int,
+ SCA3000_INT_MASK_RING_HALF);
+
+static IIO_DEVICE_ATTR(75_percent, S_IRUGO | S_IWUSR,
+ sca3000_query_ring_int,
+ sca3000_set_ring_int,
+ SCA3000_INT_MASK_RING_THREE_QUARTER);
+
+
+/**
* sca3000_show_ring_bpse() -sysfs function to query bits per sample from ring
* @dev: ring buffer device
* @attr: this device attribute
@@ -137,20 +238,18 @@
char *buf)
{
int len = 0, ret;
- u8 *rx;
struct iio_ring_buffer *ring = dev_get_drvdata(dev);
struct iio_dev *indio_dev = ring->indio_dev;
struct sca3000_state *st = indio_dev->dev_data;
mutex_lock(&st->lock);
- ret = sca3000_read_data(st, SCA3000_REG_ADDR_MODE, &rx, 1);
+ ret = sca3000_read_data_short(st, SCA3000_REG_ADDR_MODE, 1);
if (ret)
goto error_ret;
- if (rx[1] & SCA3000_RING_BUF_8BIT)
+ if (st->rx[0] & SCA3000_RING_BUF_8BIT)
len = sprintf(buf, "s8/8\n");
else
len = sprintf(buf, "s11/16\n");
- kfree(rx);
error_ret:
mutex_unlock(&st->lock);
@@ -173,20 +272,19 @@
struct iio_dev *indio_dev = ring->indio_dev;
struct sca3000_state *st = indio_dev->dev_data;
int ret;
- u8 *rx;
mutex_lock(&st->lock);
- ret = sca3000_read_data(st, SCA3000_REG_ADDR_MODE, &rx, 1);
+ ret = sca3000_read_data_short(st, SCA3000_REG_ADDR_MODE, 1);
if (ret)
goto error_ret;
- if (strncmp(buf, "s8/8", 4) == 0) {
+ if (sysfs_streq(buf, "s8/8")) {
ret = sca3000_write_reg(st, SCA3000_REG_ADDR_MODE,
- rx[1] | SCA3000_RING_BUF_8BIT);
+ st->rx[0] | SCA3000_RING_BUF_8BIT);
st->bpse = 8;
- } else if (strncmp(buf, "s11/16", 5) == 0) {
+ } else if (sysfs_streq(buf, "s11/16")) {
ret = sca3000_write_reg(st, SCA3000_REG_ADDR_MODE,
- rx[1] & ~SCA3000_RING_BUF_8BIT);
+ st->rx[0] & ~SCA3000_RING_BUF_8BIT);
st->bpse = 11;
} else
ret = -EINVAL;
@@ -196,33 +294,23 @@
return ret ? ret : len;
}
-static IIO_SCAN_EL_C(accel_x, 0, 0, NULL);
-static IIO_SCAN_EL_C(accel_y, 1, 0, NULL);
-static IIO_SCAN_EL_C(accel_z, 2, 0, NULL);
-static IIO_CONST_ATTR(accel_type_available, "s8/8 s11/16");
-static IIO_DEVICE_ATTR(accel_type,
- S_IRUGO | S_IWUSR,
- sca3000_show_ring_bpse,
- sca3000_store_ring_bpse,
+static ssize_t sca3000_show_buffer_scale(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct iio_ring_buffer *ring = dev_get_drvdata(dev);
+ struct iio_dev *indio_dev = ring->indio_dev;
+ struct sca3000_state *st = indio_dev->dev_data;
+
+ return sprintf(buf, "0.%06d\n", 4*st->info->scale);
+}
+
+static IIO_DEVICE_ATTR(accel_scale,
+ S_IRUGO,
+ sca3000_show_buffer_scale,
+ NULL,
0);
-static struct attribute *sca3000_scan_el_attrs[] = {
- &iio_scan_el_accel_x.dev_attr.attr,
- &iio_const_attr_accel_x_index.dev_attr.attr,
- &iio_scan_el_accel_y.dev_attr.attr,
- &iio_const_attr_accel_y_index.dev_attr.attr,
- &iio_scan_el_accel_z.dev_attr.attr,
- &iio_const_attr_accel_z_index.dev_attr.attr,
- &iio_const_attr_accel_type_available.dev_attr.attr,
- &iio_dev_attr_accel_type.dev_attr.attr,
- NULL
-};
-
-static struct attribute_group sca3000_scan_el_group = {
- .attrs = sca3000_scan_el_attrs,
- .name = "scan_elements",
-};
-
/*
* Ring buffer attributes
* This device is a bit unusual in that the sampling frequency and bpse
@@ -233,6 +321,9 @@
&dev_attr_length.attr,
&dev_attr_bytes_per_datum.attr,
&dev_attr_enable.attr,
+ &iio_dev_attr_50_percent.dev_attr.attr,
+ &iio_dev_attr_75_percent.dev_attr.attr,
+ &iio_dev_attr_accel_scale.dev_attr.attr,
NULL,
};
@@ -258,11 +349,12 @@
ring = kzalloc(sizeof *ring, GFP_KERNEL);
if (!ring)
return NULL;
+
ring->private = indio_dev;
buf = &ring->buf;
+ buf->stufftoread = 0;
iio_ring_buffer_init(buf, indio_dev);
buf->dev.type = &sca3000_ring_type;
- device_initialize(&buf->dev);
buf->dev.parent = &indio_dev->dev;
dev_set_drvdata(&buf->dev, (void *)buf);
@@ -275,6 +367,12 @@
iio_put_ring_buffer(r);
}
+static const struct iio_ring_access_funcs sca3000_ring_access_funcs = {
+ .read_first_n = &sca3000_read_first_n_hw_rb,
+ .get_length = &sca3000_ring_get_length,
+ .get_bytes_per_datum = &sca3000_ring_get_bytes_per_datum,
+};
+
int sca3000_configure_ring(struct iio_dev *indio_dev)
{
indio_dev->ring = sca3000_rb_allocate(indio_dev);
@@ -282,10 +380,11 @@
return -ENOMEM;
indio_dev->modes |= INDIO_RING_HARDWARE_BUFFER;
- indio_dev->ring->scan_el_attrs = &sca3000_scan_el_group;
- indio_dev->ring->access.rip_lots = &sca3000_rip_hw_rb;
- indio_dev->ring->access.get_length = &sca3000_ring_get_length;
- indio_dev->ring->access.get_bytes_per_datum = &sca3000_ring_get_bytes_per_datum;
+ indio_dev->ring->access = &sca3000_ring_access_funcs;
+
+ iio_scan_mask_set(indio_dev->ring, 0);
+ iio_scan_mask_set(indio_dev->ring, 1);
+ iio_scan_mask_set(indio_dev->ring, 2);
return 0;
}
@@ -300,22 +399,20 @@
{
struct sca3000_state *st = indio_dev->dev_data;
int ret;
- u8 *rx;
mutex_lock(&st->lock);
- ret = sca3000_read_data(st, SCA3000_REG_ADDR_MODE, &rx, 1);
+ ret = sca3000_read_data_short(st, SCA3000_REG_ADDR_MODE, 1);
if (ret)
goto error_ret;
if (state) {
printk(KERN_INFO "supposedly enabling ring buffer\n");
ret = sca3000_write_reg(st,
SCA3000_REG_ADDR_MODE,
- (rx[1] | SCA3000_RING_BUF_ENABLE));
+ (st->rx[0] | SCA3000_RING_BUF_ENABLE));
} else
ret = sca3000_write_reg(st,
SCA3000_REG_ADDR_MODE,
- (rx[1] & ~SCA3000_RING_BUF_ENABLE));
- kfree(rx);
+ (st->rx[0] & ~SCA3000_RING_BUF_ENABLE));
error_ret:
mutex_unlock(&st->lock);
@@ -338,10 +435,14 @@
return __sca3000_hw_ring_state_set(indio_dev, 0);
}
+static const struct iio_ring_setup_ops sca3000_ring_setup_ops = {
+ .preenable = &sca3000_hw_ring_preenable,
+ .postdisable = &sca3000_hw_ring_postdisable,
+};
+
void sca3000_register_ring_funcs(struct iio_dev *indio_dev)
{
- indio_dev->ring->preenable = &sca3000_hw_ring_preenable;
- indio_dev->ring->postdisable = &sca3000_hw_ring_postdisable;
+ indio_dev->ring->setup_ops = &sca3000_ring_setup_ops;
}
/**
@@ -352,11 +453,9 @@
**/
void sca3000_ring_int_process(u8 val, struct iio_ring_buffer *ring)
{
- if (val & SCA3000_INT_STATUS_THREE_QUARTERS)
- iio_push_or_escallate_ring_event(ring,
- IIO_EVENT_CODE_RING_75_FULL,
- 0);
- else if (val & SCA3000_INT_STATUS_HALF)
- iio_push_ring_event(ring,
- IIO_EVENT_CODE_RING_50_FULL, 0);
+ if (val & (SCA3000_INT_STATUS_THREE_QUARTERS |
+ SCA3000_INT_STATUS_HALF)) {
+ ring->stufftoread = true;
+ wake_up_interruptible(&ring->pollq);
+ }
}
diff --git a/drivers/staging/iio/adc/Kconfig b/drivers/staging/iio/adc/Kconfig
index 6692a3d..8c751c4 100644
--- a/drivers/staging/iio/adc/Kconfig
+++ b/drivers/staging/iio/adc/Kconfig
@@ -3,30 +3,6 @@
#
comment "Analog to digital convertors"
-config MAX1363
- tristate "MAXIM max1363 ADC driver"
- depends on I2C
- select IIO_TRIGGER if IIO_RING_BUFFER
- select MAX1363_RING_BUFFER
- help
- Say yes here to build support for many MAXIM i2c analog to digital
- convertors (ADC). (max1361, max1362, max1363, max1364, max1036,
- max1037, max1038, max1039, max1136, max1136, max1137, max1138,
- max1139, max1236, max1237, max11238, max1239, max11600, max11601,
- max11602, max11603, max11604, max11605, max11606, max11607,
- max11608, max11609, max11610, max11611, max11612, max11613,
- max11614, max11615, max11616, max11617) Provides direct access
- via sysfs.
-
-config MAX1363_RING_BUFFER
- bool "MAXIM max1363: use ring buffer"
- depends on MAX1363
- select IIO_RING_BUFFER
- select IIO_SW_RING
- help
- Say yes here to include ring buffer support in the MAX1363
- ADC driver.
-
config AD7150
tristate "Analog Devices ad7150/1/6 capacitive sensor driver"
depends on I2C
@@ -142,6 +118,18 @@
To compile this driver as a module, choose M here: the
module will be called ad7887.
+config AD7780
+ tristate "Analog Devices AD7780 AD7781 ADC driver"
+ depends on SPI
+ depends on GPIOLIB
+ help
+ Say yes here to build support for Analog Devices
+ AD7780 and AD7781 SPI analog to digital convertors (ADC).
+ If unsure, say N (but it's safe to say "Y").
+
+ To compile this driver as a module, choose M here: the
+ module will be called ad7780.
+
config AD7745
tristate "Analog Devices AD7745, AD7746 AD7747 capacitive sensor driver"
depends on I2C
@@ -179,3 +167,27 @@
help
Say yes here to build support for Analog Devices ADT7410
temperature sensors.
+
+config MAX1363
+ tristate "Maxim max1363 ADC driver"
+ depends on I2C
+ select IIO_TRIGGER if IIO_RING_BUFFER
+ select MAX1363_RING_BUFFER
+ help
+ Say yes here to build support for many Maxim i2c analog to digital
+ convertors (ADC). (max1361, max1362, max1363, max1364, max1036,
+ max1037, max1038, max1039, max1136, max1136, max1137, max1138,
+ max1139, max1236, max1237, max11238, max1239, max11600, max11601,
+ max11602, max11603, max11604, max11605, max11606, max11607,
+ max11608, max11609, max11610, max11611, max11612, max11613,
+ max11614, max11615, max11616, max11617, max11644, max11645,
+ max11646, max11647) Provides direct access via sysfs.
+
+config MAX1363_RING_BUFFER
+ bool "Maxim max1363: use ring buffer"
+ depends on MAX1363
+ select IIO_RING_BUFFER
+ select IIO_SW_RING
+ help
+ Say yes here to include ring buffer support in the MAX1363
+ ADC driver.
diff --git a/drivers/staging/iio/adc/Makefile b/drivers/staging/iio/adc/Makefile
index 31067de..1d9b3f5 100644
--- a/drivers/staging/iio/adc/Makefile
+++ b/drivers/staging/iio/adc/Makefile
@@ -34,6 +34,7 @@
obj-$(CONFIG_AD7291) += ad7291.o
obj-$(CONFIG_AD7314) += ad7314.o
obj-$(CONFIG_AD7745) += ad7745.o
+obj-$(CONFIG_AD7780) += ad7780.o
obj-$(CONFIG_AD7816) += ad7816.o
obj-$(CONFIG_ADT75) += adt75.o
obj-$(CONFIG_ADT7310) += adt7310.o
diff --git a/drivers/staging/iio/adc/ad7150.c b/drivers/staging/iio/adc/ad7150.c
index 8555766..ca32b67 100644
--- a/drivers/staging/iio/adc/ad7150.c
+++ b/drivers/staging/iio/adc/ad7150.c
@@ -7,15 +7,10 @@
*/
#include <linux/interrupt.h>
-#include <linux/gpio.h>
-#include <linux/workqueue.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/slab.h>
-#include <linux/sysfs.h>
-#include <linux/list.h>
#include <linux/i2c.h>
-#include <linux/rtc.h>
#include "../iio.h"
#include "../sysfs.h"
@@ -63,12 +58,9 @@
*/
struct ad7150_chip_info {
- const char *name;
struct i2c_client *client;
struct iio_dev *indio_dev;
- struct work_struct thresh_work;
bool inter;
- s64 last_timestamp;
u16 ch1_threshold; /* Ch1 Threshold (in fixed threshold mode) */
u8 ch1_sensitivity; /* Ch1 Sensitivity (in adaptive threshold mode) */
u8 ch1_timeout; /* Ch1 Timeout (in adaptive threshold mode) */
@@ -88,7 +80,8 @@
u8 reg_cfg;
};
-struct ad7150_conversion_mode ad7150_conv_mode_table[AD7150_MAX_CONV_MODE] = {
+static struct ad7150_conversion_mode
+ad7150_conv_mode_table[AD7150_MAX_CONV_MODE] = {
{ "idle", 0 },
{ "continuous-conversion", 1 },
{ "single-conversion", 2 },
@@ -590,17 +583,6 @@
ad7150_show_ch2_setup,
ad7150_store_ch2_setup);
-static ssize_t ad7150_show_name(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- struct iio_dev *dev_info = dev_get_drvdata(dev);
- struct ad7150_chip_info *chip = dev_info->dev_data;
- return sprintf(buf, "%s\n", chip->name);
-}
-
-static IIO_DEVICE_ATTR(name, S_IRUGO, ad7150_show_name, NULL, 0);
-
static ssize_t ad7150_show_powerdown_timer(struct device *dev,
struct device_attribute *attr,
char *buf)
@@ -649,7 +631,6 @@
&iio_dev_attr_powerdown_timer.dev_attr.attr,
&iio_dev_attr_ch1_value.dev_attr.attr,
&iio_dev_attr_ch2_value.dev_attr.attr,
- &iio_dev_attr_name.dev_attr.attr,
NULL,
};
@@ -661,96 +642,57 @@
* threshold events
*/
-#define IIO_EVENT_CODE_CH1_HIGH IIO_BUFFER_EVENT_CODE(0)
-#define IIO_EVENT_CODE_CH1_LOW IIO_BUFFER_EVENT_CODE(1)
-#define IIO_EVENT_CODE_CH2_HIGH IIO_BUFFER_EVENT_CODE(2)
-#define IIO_EVENT_CODE_CH2_LOW IIO_BUFFER_EVENT_CODE(3)
-
-#define IIO_EVENT_ATTR_CH1_HIGH_SH(_evlist, _show, _store, _mask) \
- IIO_EVENT_ATTR_SH(ch1_high, _evlist, _show, _store, _mask)
-
-#define IIO_EVENT_ATTR_CH2_HIGH_SH(_evlist, _show, _store, _mask) \
- IIO_EVENT_ATTR_SH(ch2_high, _evlist, _show, _store, _mask)
-
-#define IIO_EVENT_ATTR_CH1_LOW_SH(_evlist, _show, _store, _mask) \
- IIO_EVENT_ATTR_SH(ch1_low, _evlist, _show, _store, _mask)
-
-#define IIO_EVENT_ATTR_CH2_LOW_SH(_evlist, _show, _store, _mask) \
- IIO_EVENT_ATTR_SH(ch2_low, _evlist, _show, _store, _mask)
-
-static void ad7150_interrupt_handler_bh(struct work_struct *work_s)
+static irqreturn_t ad7150_event_handler(int irq, void *private)
{
- struct ad7150_chip_info *chip =
- container_of(work_s, struct ad7150_chip_info, thresh_work);
+ struct iio_dev *indio_dev = private;
+ struct ad7150_chip_info *chip = iio_dev_get_devdata(indio_dev);
u8 int_status;
-
- enable_irq(chip->client->irq);
+ s64 timestamp = iio_get_time_ns();
ad7150_i2c_read(chip, AD7150_STATUS, &int_status, 1);
if ((int_status & AD7150_STATUS_OUT1) && !(chip->old_state & AD7150_STATUS_OUT1))
- iio_push_event(chip->indio_dev, 0,
- IIO_EVENT_CODE_CH1_HIGH,
- chip->last_timestamp);
+ iio_push_event(indio_dev, 0,
+ IIO_UNMOD_EVENT_CODE(IIO_EV_CLASS_IN,
+ 0,
+ IIO_EV_TYPE_THRESH,
+ IIO_EV_DIR_RISING),
+ timestamp);
else if ((!(int_status & AD7150_STATUS_OUT1)) && (chip->old_state & AD7150_STATUS_OUT1))
- iio_push_event(chip->indio_dev, 0,
- IIO_EVENT_CODE_CH1_LOW,
- chip->last_timestamp);
+ iio_push_event(indio_dev, 0,
+ IIO_UNMOD_EVENT_CODE(IIO_EV_CLASS_IN,
+ 0,
+ IIO_EV_TYPE_THRESH,
+ IIO_EV_DIR_FALLING),
+ timestamp);
if ((int_status & AD7150_STATUS_OUT2) && !(chip->old_state & AD7150_STATUS_OUT2))
- iio_push_event(chip->indio_dev, 0,
- IIO_EVENT_CODE_CH2_HIGH,
- chip->last_timestamp);
+ iio_push_event(indio_dev, 0,
+ IIO_UNMOD_EVENT_CODE(IIO_EV_CLASS_IN,
+ 1,
+ IIO_EV_TYPE_THRESH,
+ IIO_EV_DIR_RISING),
+ timestamp);
else if ((!(int_status & AD7150_STATUS_OUT2)) && (chip->old_state & AD7150_STATUS_OUT2))
- iio_push_event(chip->indio_dev, 0,
- IIO_EVENT_CODE_CH2_LOW,
- chip->last_timestamp);
+ iio_push_event(indio_dev, 0,
+ IIO_UNMOD_EVENT_CODE(IIO_EV_CLASS_IN,
+ 1,
+ IIO_EV_TYPE_THRESH,
+ IIO_EV_DIR_FALLING),
+ timestamp);
+ return IRQ_HANDLED;
}
-static int ad7150_interrupt_handler_th(struct iio_dev *dev_info,
- int index,
- s64 timestamp,
- int no_test)
-{
- struct ad7150_chip_info *chip = dev_info->dev_data;
-
- chip->last_timestamp = timestamp;
- schedule_work(&chip->thresh_work);
-
- return 0;
-}
-
-IIO_EVENT_SH(threshold, &ad7150_interrupt_handler_th);
-
-static ssize_t ad7150_query_out_mode(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- /*
- * AD7150 provides two logic output channels, which can be used as interrupt
- * but the pins are not configurable
- */
- return sprintf(buf, "1\n");
-}
-
-static ssize_t ad7150_set_out_mode(struct device *dev,
- struct device_attribute *attr,
- const char *buf,
- size_t len)
-{
- return len;
-}
-
-IIO_EVENT_ATTR_CH1_HIGH_SH(iio_event_threshold, ad7150_query_out_mode, ad7150_set_out_mode, 0);
-IIO_EVENT_ATTR_CH2_HIGH_SH(iio_event_threshold, ad7150_query_out_mode, ad7150_set_out_mode, 0);
-IIO_EVENT_ATTR_CH1_LOW_SH(iio_event_threshold, ad7150_query_out_mode, ad7150_set_out_mode, 0);
-IIO_EVENT_ATTR_CH2_LOW_SH(iio_event_threshold, ad7150_query_out_mode, ad7150_set_out_mode, 0);
+static IIO_CONST_ATTR(ch1_high_en, "1");
+static IIO_CONST_ATTR(ch2_high_en, "1");
+static IIO_CONST_ATTR(ch1_low_en, "1");
+static IIO_CONST_ATTR(ch2_low_en, "1");
static struct attribute *ad7150_event_attributes[] = {
- &iio_event_attr_ch1_high.dev_attr.attr,
- &iio_event_attr_ch2_high.dev_attr.attr,
- &iio_event_attr_ch1_low.dev_attr.attr,
- &iio_event_attr_ch2_low.dev_attr.attr,
+ &iio_const_attr_ch1_high_en.dev_attr.attr,
+ &iio_const_attr_ch2_high_en.dev_attr.attr,
+ &iio_const_attr_ch1_low_en.dev_attr.attr,
+ &iio_const_attr_ch2_low_en.dev_attr.attr,
NULL,
};
@@ -758,6 +700,12 @@
.attrs = ad7150_event_attributes,
};
+static const struct iio_info ad7150_info = {
+ .attrs = &ad7150_attribute_group,
+ .num_interrupt_lines = 1,
+ .event_attrs = &ad7150_event_attribute_group,
+ .driver_module = THIS_MODULE,
+};
/*
* device probe and remove
*/
@@ -776,21 +724,20 @@
i2c_set_clientdata(client, chip);
chip->client = client;
- chip->name = id->name;
- chip->indio_dev = iio_allocate_device();
+ chip->indio_dev = iio_allocate_device(0);
if (chip->indio_dev == NULL) {
ret = -ENOMEM;
goto error_free_chip;
}
- /* Echipabilish that the iio_dev is a child of the i2c device */
+ /* Establish that the iio_dev is a child of the i2c device */
+ chip->indio_dev->name = id->name;
chip->indio_dev->dev.parent = &client->dev;
- chip->indio_dev->attrs = &ad7150_attribute_group;
- chip->indio_dev->event_attrs = &ad7150_event_attribute_group;
+
+ chip->indio_dev->info = &ad7150_info;
chip->indio_dev->dev_data = (void *)(chip);
- chip->indio_dev->driver_module = THIS_MODULE;
- chip->indio_dev->num_interrupt_lines = 1;
+
chip->indio_dev->modes = INDIO_DIRECT_MODE;
ret = iio_device_register(chip->indio_dev);
@@ -798,19 +745,16 @@
goto error_free_dev;
regdone = 1;
- if (client->irq && gpio_is_valid(irq_to_gpio(client->irq)) > 0) {
- ret = iio_register_interrupt_line(client->irq,
- chip->indio_dev,
- 0,
- IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING,
- "ad7150");
+ if (client->irq) {
+ ret = request_threaded_irq(client->irq,
+ NULL,
+ &ad7150_event_handler,
+ IRQF_TRIGGER_RISING |
+ IRQF_TRIGGER_FALLING,
+ "ad7150",
+ chip->indio_dev);
if (ret)
goto error_free_dev;
-
- iio_add_event_to_list(iio_event_attr_ch2_low.listel,
- &chip->indio_dev->interrupts[0]->ev_list);
-
- INIT_WORK(&chip->thresh_work, ad7150_interrupt_handler_bh);
}
dev_err(&client->dev, "%s capacitive sensor registered, irq: %d\n", id->name, client->irq);
@@ -833,8 +777,8 @@
struct ad7150_chip_info *chip = i2c_get_clientdata(client);
struct iio_dev *indio_dev = chip->indio_dev;
- if (client->irq && gpio_is_valid(irq_to_gpio(client->irq)) > 0)
- iio_unregister_interrupt_line(indio_dev, 0);
+ if (client->irq)
+ free_irq(client->irq, indio_dev);
iio_device_unregister(indio_dev);
kfree(chip);
diff --git a/drivers/staging/iio/adc/ad7152.c b/drivers/staging/iio/adc/ad7152.c
index fa7f8406..7a38bcb 100644
--- a/drivers/staging/iio/adc/ad7152.c
+++ b/drivers/staging/iio/adc/ad7152.c
@@ -7,15 +7,11 @@
*/
#include <linux/interrupt.h>
-#include <linux/gpio.h>
-#include <linux/workqueue.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
-#include <linux/list.h>
#include <linux/i2c.h>
-#include <linux/rtc.h>
#include "../iio.h"
#include "../sysfs.h"
@@ -54,7 +50,6 @@
*/
struct ad7152_chip_info {
- const char *name;
struct i2c_client *client;
struct iio_dev *indio_dev;
u16 ch1_offset; /* Channel 1 offset calibration coefficient */
@@ -72,7 +67,8 @@
u8 reg_cfg;
};
-struct ad7152_conversion_mode ad7152_conv_mode_table[AD7152_MAX_CONV_MODE] = {
+static struct ad7152_conversion_mode
+ad7152_conv_mode_table[AD7152_MAX_CONV_MODE] = {
{ "idle", 0 },
{ "continuous-conversion", 1 },
{ "single-conversion", 2 },
@@ -482,17 +478,6 @@
ad7152_show_filter_rate_setup,
ad7152_store_filter_rate_setup);
-static ssize_t ad7152_show_name(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- struct iio_dev *dev_info = dev_get_drvdata(dev);
- struct ad7152_chip_info *chip = dev_info->dev_data;
- return sprintf(buf, "%s\n", chip->name);
-}
-
-static IIO_DEVICE_ATTR(name, S_IRUGO, ad7152_show_name, NULL, 0);
-
static struct attribute *ad7152_attributes[] = {
&iio_dev_attr_available_conversion_modes.dev_attr.attr,
&iio_dev_attr_conversion_mode.dev_attr.attr,
@@ -505,7 +490,6 @@
&iio_dev_attr_ch1_setup.dev_attr.attr,
&iio_dev_attr_ch2_setup.dev_attr.attr,
&iio_dev_attr_filter_rate_setup.dev_attr.attr,
- &iio_dev_attr_name.dev_attr.attr,
NULL,
};
@@ -513,6 +497,10 @@
.attrs = ad7152_attributes,
};
+static const struct iio_info ad7152_info = {
+ .attrs = &ad7152_attribute_group,
+ .driver_module = THIS_MODULE,
+};
/*
* device probe and remove
*/
@@ -531,19 +519,18 @@
i2c_set_clientdata(client, chip);
chip->client = client;
- chip->name = id->name;
- chip->indio_dev = iio_allocate_device();
+ chip->indio_dev = iio_allocate_device(0);
if (chip->indio_dev == NULL) {
ret = -ENOMEM;
goto error_free_chip;
}
/* Echipabilish that the iio_dev is a child of the i2c device */
+ chip->indio_dev->name = id->name;
chip->indio_dev->dev.parent = &client->dev;
- chip->indio_dev->attrs = &ad7152_attribute_group;
+ chip->indio_dev->info = &ad7152_info;
chip->indio_dev->dev_data = (void *)(chip);
- chip->indio_dev->driver_module = THIS_MODULE;
chip->indio_dev->modes = INDIO_DIRECT_MODE;
ret = iio_device_register(chip->indio_dev);
@@ -567,8 +554,6 @@
struct ad7152_chip_info *chip = i2c_get_clientdata(client);
struct iio_dev *indio_dev = chip->indio_dev;
- if (client->irq && gpio_is_valid(irq_to_gpio(client->irq)) > 0)
- iio_unregister_interrupt_line(indio_dev, 0);
iio_device_unregister(indio_dev);
kfree(chip);
diff --git a/drivers/staging/iio/adc/ad7291.c b/drivers/staging/iio/adc/ad7291.c
index 34041a7..1be3453 100644
--- a/drivers/staging/iio/adc/ad7291.c
+++ b/drivers/staging/iio/adc/ad7291.c
@@ -8,14 +8,12 @@
#include <linux/interrupt.h>
#include <linux/gpio.h>
-#include <linux/workqueue.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
#include <linux/list.h>
#include <linux/i2c.h>
-#include <linux/rtc.h>
#include "../iio.h"
#include "../sysfs.h"
@@ -62,11 +60,8 @@
*/
struct ad7291_chip_info {
- const char *name;
struct i2c_client *client;
struct iio_dev *indio_dev;
- struct work_struct thresh_work;
- s64 last_timestamp;
u16 command;
u8 channels; /* Active voltage channels */
};
@@ -438,17 +433,6 @@
ad7291_store_channel_mask,
0);
-static ssize_t ad7291_show_name(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- struct iio_dev *dev_info = dev_get_drvdata(dev);
- struct ad7291_chip_info *chip = dev_info->dev_data;
- return sprintf(buf, "%s\n", chip->name);
-}
-
-static IIO_DEVICE_ATTR(name, S_IRUGO, ad7291_show_name, NULL, 0);
-
static struct attribute *ad7291_attributes[] = {
&iio_dev_attr_available_modes.dev_attr.attr,
&iio_dev_attr_mode.dev_attr.attr,
@@ -459,7 +443,6 @@
&iio_dev_attr_t_average.dev_attr.attr,
&iio_dev_attr_voltage.dev_attr.attr,
&iio_dev_attr_channel_mask.dev_attr.attr,
- &iio_dev_attr_name.dev_attr.attr,
NULL,
};
@@ -471,28 +454,23 @@
* temperature bound events
*/
-#define IIO_EVENT_CODE_AD7291_T_SENSE_HIGH IIO_BUFFER_EVENT_CODE(0)
-#define IIO_EVENT_CODE_AD7291_T_SENSE_LOW IIO_BUFFER_EVENT_CODE(1)
-#define IIO_EVENT_CODE_AD7291_T_AVG_HIGH IIO_BUFFER_EVENT_CODE(2)
-#define IIO_EVENT_CODE_AD7291_T_AVG_LOW IIO_BUFFER_EVENT_CODE(3)
-#define IIO_EVENT_CODE_AD7291_VOLTAGE_BASE IIO_BUFFER_EVENT_CODE(4)
-
-static void ad7291_interrupt_bh(struct work_struct *work_s)
+static irqreturn_t ad7291_event_handler(int irq, void *private)
{
- struct ad7291_chip_info *chip =
- container_of(work_s, struct ad7291_chip_info, thresh_work);
+ struct iio_dev *indio_dev = private;
+ struct ad7291_chip_info *chip = iio_dev_get_devdata(private);
u16 t_status, v_status;
u16 command;
int i;
+ s64 timestamp = iio_get_time_ns();
if (ad7291_i2c_read(chip, AD7291_T_ALERT_STATUS, &t_status))
- return;
+ return IRQ_HANDLED;
if (ad7291_i2c_read(chip, AD7291_VOLTAGE_ALERT_STATUS, &v_status))
- return;
+ return IRQ_HANDLED;
if (!(t_status || v_status))
- return;
+ return IRQ_HANDLED;
command = chip->command | AD7291_ALART_CLEAR;
ad7291_i2c_write(chip, AD7291_COMMAND, command);
@@ -500,50 +478,67 @@
command = chip->command & ~AD7291_ALART_CLEAR;
ad7291_i2c_write(chip, AD7291_COMMAND, command);
- enable_irq(chip->client->irq);
+ if (t_status & (1 << 0))
+ iio_push_event(indio_dev, 0,
+ IIO_UNMOD_EVENT_CODE(IIO_TEMP,
+ 0,
+ IIO_EV_TYPE_THRESH,
+ IIO_EV_DIR_FALLING),
+ timestamp);
+ if (t_status & (1 << 1))
+ iio_push_event(indio_dev, 0,
+ IIO_UNMOD_EVENT_CODE(IIO_TEMP,
+ 0,
+ IIO_EV_TYPE_THRESH,
+ IIO_EV_DIR_RISING),
+ timestamp);
+ if (t_status & (1 << 2))
+ iio_push_event(indio_dev, 0,
+ IIO_UNMOD_EVENT_CODE(IIO_TEMP,
+ 0,
+ IIO_EV_TYPE_THRESH,
+ IIO_EV_DIR_FALLING),
+ timestamp);
+ if (t_status & (1 << 3))
+ iio_push_event(indio_dev, 0,
+ IIO_UNMOD_EVENT_CODE(IIO_TEMP,
+ 0,
+ IIO_EV_TYPE_THRESH,
+ IIO_EV_DIR_RISING),
+ timestamp);
- for (i = 0; i < 4; i++) {
- if (t_status & (1 << i))
- iio_push_event(chip->indio_dev, 0,
- IIO_EVENT_CODE_AD7291_T_SENSE_HIGH + i,
- chip->last_timestamp);
- }
-
- for (i = 0; i < AD7291_VOLTAGE_LIMIT_COUNT*2; i++) {
+ for (i = 0; i < AD7291_VOLTAGE_LIMIT_COUNT*2; i += 2) {
if (v_status & (1 << i))
- iio_push_event(chip->indio_dev, 0,
- IIO_EVENT_CODE_AD7291_VOLTAGE_BASE + i,
- chip->last_timestamp);
+ iio_push_event(indio_dev, 0,
+ IIO_UNMOD_EVENT_CODE(IIO_IN,
+ i/2,
+ IIO_EV_TYPE_THRESH,
+ IIO_EV_DIR_FALLING),
+ timestamp);
+ if (v_status & (1 << (i + 1)))
+ iio_push_event(indio_dev, 0,
+ IIO_UNMOD_EVENT_CODE(IIO_IN,
+ i/2,
+ IIO_EV_TYPE_THRESH,
+ IIO_EV_DIR_RISING),
+ timestamp);
}
+
+ return IRQ_HANDLED;
}
-static int ad7291_interrupt(struct iio_dev *dev_info,
- int index,
- s64 timestamp,
- int no_test)
-{
- struct ad7291_chip_info *chip = dev_info->dev_data;
-
- chip->last_timestamp = timestamp;
- schedule_work(&chip->thresh_work);
-
- return 0;
-}
-
-IIO_EVENT_SH(ad7291, &ad7291_interrupt);
-
static inline ssize_t ad7291_show_t_bound(struct device *dev,
struct device_attribute *attr,
- u8 bound_reg,
char *buf)
{
struct iio_dev *dev_info = dev_get_drvdata(dev);
struct ad7291_chip_info *chip = dev_info->dev_data;
+ struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
u16 data;
char sign = ' ';
int ret;
- ret = ad7291_i2c_read(chip, bound_reg, &data);
+ ret = ad7291_i2c_read(chip, this_attr->address, &data);
if (ret)
return -EIO;
@@ -561,12 +556,12 @@
static inline ssize_t ad7291_set_t_bound(struct device *dev,
struct device_attribute *attr,
- u8 bound_reg,
const char *buf,
size_t len)
{
struct iio_dev *dev_info = dev_get_drvdata(dev);
struct ad7291_chip_info *chip = dev_info->dev_data;
+ struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
long tmp1, tmp2;
u16 data;
char *pos;
@@ -600,64 +595,13 @@
/* convert positive value to supplyment */
data = (AD7291_T_VALUE_SIGN << 1) - data;
- ret = ad7291_i2c_write(chip, bound_reg, data);
+ ret = ad7291_i2c_write(chip, this_attr->address, data);
if (ret)
return -EIO;
return ret;
}
-static ssize_t ad7291_show_t_sense_high(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- return ad7291_show_t_bound(dev, attr,
- AD7291_T_SENSE_HIGH, buf);
-}
-
-static inline ssize_t ad7291_set_t_sense_high(struct device *dev,
- struct device_attribute *attr,
- const char *buf,
- size_t len)
-{
- return ad7291_set_t_bound(dev, attr,
- AD7291_T_SENSE_HIGH, buf, len);
-}
-
-static ssize_t ad7291_show_t_sense_low(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- return ad7291_show_t_bound(dev, attr,
- AD7291_T_SENSE_LOW, buf);
-}
-
-static inline ssize_t ad7291_set_t_sense_low(struct device *dev,
- struct device_attribute *attr,
- const char *buf,
- size_t len)
-{
- return ad7291_set_t_bound(dev, attr,
- AD7291_T_SENSE_LOW, buf, len);
-}
-
-static ssize_t ad7291_show_t_sense_hyst(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- return ad7291_show_t_bound(dev, attr,
- AD7291_T_SENSE_HYST, buf);
-}
-
-static inline ssize_t ad7291_set_t_sense_hyst(struct device *dev,
- struct device_attribute *attr,
- const char *buf,
- size_t len)
-{
- return ad7291_set_t_bound(dev, attr,
- AD7291_T_SENSE_HYST, buf, len);
-}
-
static inline ssize_t ad7291_show_v_bound(struct device *dev,
struct device_attribute *attr,
u8 bound_reg,
@@ -712,191 +656,121 @@
return ret;
}
-static int ad7291_get_voltage_limit_regs(const char *channel)
-{
- int index;
-
- if (strlen(channel) < 3 && channel[0] != 'v')
- return -EINVAL;
-
- index = channel[1] - '0';
- if (index >= AD7291_VOLTAGE_LIMIT_COUNT)
- return -EINVAL;
-
- return index;
-}
-
-static ssize_t ad7291_show_voltage_high(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- int regs;
-
- regs = ad7291_get_voltage_limit_regs(attr->attr.name);
-
- if (regs < 0)
- return regs;
-
- return ad7291_show_t_bound(dev, attr, regs, buf);
-}
-
-static inline ssize_t ad7291_set_voltage_high(struct device *dev,
- struct device_attribute *attr,
- const char *buf,
- size_t len)
-{
- int regs;
-
- regs = ad7291_get_voltage_limit_regs(attr->attr.name);
-
- if (regs < 0)
- return regs;
-
- return ad7291_set_t_bound(dev, attr, regs, buf, len);
-}
-
-static ssize_t ad7291_show_voltage_low(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- int regs;
-
- regs = ad7291_get_voltage_limit_regs(attr->attr.name);
-
- if (regs < 0)
- return regs;
-
- return ad7291_show_t_bound(dev, attr, regs+1, buf);
-}
-
-static inline ssize_t ad7291_set_voltage_low(struct device *dev,
- struct device_attribute *attr,
- const char *buf,
- size_t len)
-{
- int regs;
-
- regs = ad7291_get_voltage_limit_regs(attr->attr.name);
-
- if (regs < 0)
- return regs;
-
- return ad7291_set_t_bound(dev, attr, regs+1, buf, len);
-}
-
-static ssize_t ad7291_show_voltage_hyst(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- int regs;
-
- regs = ad7291_get_voltage_limit_regs(attr->attr.name);
-
- if (regs < 0)
- return regs;
-
- return ad7291_show_t_bound(dev, attr, regs+2, buf);
-}
-
-static inline ssize_t ad7291_set_voltage_hyst(struct device *dev,
- struct device_attribute *attr,
- const char *buf,
- size_t len)
-{
- int regs;
-
- regs = ad7291_get_voltage_limit_regs(attr->attr.name);
-
- if (regs < 0)
- return regs;
-
- return ad7291_set_t_bound(dev, attr, regs+2, buf, len);
-}
-
-IIO_EVENT_ATTR_SH(t_sense_high, iio_event_ad7291,
- ad7291_show_t_sense_high, ad7291_set_t_sense_high, 0);
-IIO_EVENT_ATTR_SH(t_sense_low, iio_event_ad7291,
- ad7291_show_t_sense_low, ad7291_set_t_sense_low, 0);
-IIO_EVENT_ATTR_SH(t_sense_hyst, iio_event_ad7291,
- ad7291_show_t_sense_hyst, ad7291_set_t_sense_hyst, 0);
-
-IIO_EVENT_ATTR_SH(v0_high, iio_event_ad7291,
- ad7291_show_voltage_high, ad7291_set_voltage_high, 0);
-IIO_EVENT_ATTR_SH(v0_low, iio_event_ad7291,
- ad7291_show_voltage_low, ad7291_set_voltage_low, 0);
-IIO_EVENT_ATTR_SH(v0_hyst, iio_event_ad7291,
- ad7291_show_voltage_hyst, ad7291_set_voltage_hyst, 0);
-IIO_EVENT_ATTR_SH(v1_high, iio_event_ad7291,
- ad7291_show_voltage_high, ad7291_set_voltage_high, 0);
-IIO_EVENT_ATTR_SH(v1_low, iio_event_ad7291,
- ad7291_show_voltage_low, ad7291_set_voltage_low, 0);
-IIO_EVENT_ATTR_SH(v1_hyst, iio_event_ad7291,
- ad7291_show_voltage_hyst, ad7291_set_voltage_hyst, 0);
-IIO_EVENT_ATTR_SH(v2_high, iio_event_ad7291,
- ad7291_show_voltage_high, ad7291_set_voltage_high, 0);
-IIO_EVENT_ATTR_SH(v2_low, iio_event_ad7291,
- ad7291_show_voltage_low, ad7291_set_voltage_low, 0);
-IIO_EVENT_ATTR_SH(v2_hyst, iio_event_ad7291,
- ad7291_show_voltage_hyst, ad7291_set_voltage_hyst, 0);
-IIO_EVENT_ATTR_SH(v3_high, iio_event_ad7291,
- ad7291_show_voltage_high, ad7291_set_voltage_high, 0);
-IIO_EVENT_ATTR_SH(v3_low, iio_event_ad7291,
- ad7291_show_voltage_low, ad7291_set_voltage_low, 0);
-IIO_EVENT_ATTR_SH(v3_hyst, iio_event_ad7291,
- ad7291_show_voltage_hyst, ad7291_set_voltage_hyst, 0);
-IIO_EVENT_ATTR_SH(v4_high, iio_event_ad7291,
- ad7291_show_voltage_high, ad7291_set_voltage_high, 0);
-IIO_EVENT_ATTR_SH(v4_low, iio_event_ad7291,
- ad7291_show_voltage_low, ad7291_set_voltage_low, 0);
-IIO_EVENT_ATTR_SH(v4_hyst, iio_event_ad7291,
- ad7291_show_voltage_hyst, ad7291_set_voltage_hyst, 0);
-IIO_EVENT_ATTR_SH(v5_high, iio_event_ad7291,
- ad7291_show_voltage_high, ad7291_set_voltage_high, 0);
-IIO_EVENT_ATTR_SH(v5_low, iio_event_ad7291,
- ad7291_show_voltage_low, ad7291_set_voltage_low, 0);
-IIO_EVENT_ATTR_SH(v5_hyst, iio_event_ad7291,
- ad7291_show_voltage_hyst, ad7291_set_voltage_hyst, 0);
-IIO_EVENT_ATTR_SH(v6_high, iio_event_ad7291,
- ad7291_show_voltage_high, ad7291_set_voltage_high, 0);
-IIO_EVENT_ATTR_SH(v6_low, iio_event_ad7291,
- ad7291_show_voltage_low, ad7291_set_voltage_low, 0);
-IIO_EVENT_ATTR_SH(v6_hyst, iio_event_ad7291,
- ad7291_show_voltage_hyst, ad7291_set_voltage_hyst, 0);
-IIO_EVENT_ATTR_SH(v7_high, iio_event_ad7291,
- ad7291_show_voltage_high, ad7291_set_voltage_high, 0);
-IIO_EVENT_ATTR_SH(v7_low, iio_event_ad7291,
- ad7291_show_voltage_low, ad7291_set_voltage_low, 0);
-IIO_EVENT_ATTR_SH(v7_hyst, iio_event_ad7291,
- ad7291_show_voltage_hyst, ad7291_set_voltage_hyst, 0);
+static IIO_DEVICE_ATTR(t_sense_high_value,
+ S_IRUGO | S_IWUSR,
+ ad7291_show_t_bound, ad7291_set_t_bound,
+ AD7291_T_SENSE_HIGH);
+static IIO_DEVICE_ATTR(t_sense_low_value,
+ S_IRUGO | S_IWUSR,
+ ad7291_show_t_bound, ad7291_set_t_bound,
+ AD7291_T_SENSE_LOW);
+static IIO_DEVICE_ATTR(t_sense_hyst_value,
+ S_IRUGO | S_IWUSR,
+ ad7291_show_t_bound, ad7291_set_t_bound,
+ AD7291_T_SENSE_HYST);
+static IIO_DEVICE_ATTR(v0_high,
+ S_IRUGO | S_IWUSR,
+ ad7291_show_t_bound, ad7291_set_t_bound, 0x04);
+static IIO_DEVICE_ATTR(v0_low,
+ S_IRUGO | S_IWUSR,
+ ad7291_show_t_bound, ad7291_set_t_bound, 0x05);
+static IIO_DEVICE_ATTR(v0_hyst,
+ S_IRUGO | S_IWUSR,
+ ad7291_show_t_bound, ad7291_set_t_bound, 0x06);
+static IIO_DEVICE_ATTR(v1_high,
+ S_IRUGO | S_IWUSR,
+ ad7291_show_t_bound, ad7291_set_t_bound, 0x07);
+static IIO_DEVICE_ATTR(v1_low,
+ S_IRUGO | S_IWUSR,
+ ad7291_show_t_bound, ad7291_set_t_bound, 0x08);
+static IIO_DEVICE_ATTR(v1_hyst,
+ S_IRUGO | S_IWUSR,
+ ad7291_show_t_bound, ad7291_set_t_bound, 0x09);
+static IIO_DEVICE_ATTR(v2_high,
+ S_IRUGO | S_IWUSR,
+ ad7291_show_t_bound, ad7291_set_t_bound, 0x0A);
+static IIO_DEVICE_ATTR(v2_low,
+ S_IRUGO | S_IWUSR,
+ ad7291_show_t_bound, ad7291_set_t_bound, 0x0B);
+static IIO_DEVICE_ATTR(v2_hyst,
+ S_IRUGO | S_IWUSR,
+ ad7291_show_t_bound, ad7291_set_t_bound, 0x0C);
+static IIO_DEVICE_ATTR(v3_high,
+ S_IRUGO | S_IWUSR,
+ /* Datasheet suggests this one and this one only
+ has the registers in different order */
+ ad7291_show_t_bound, ad7291_set_t_bound, 0x0E);
+static IIO_DEVICE_ATTR(v3_low,
+ S_IRUGO | S_IWUSR,
+ ad7291_show_t_bound, ad7291_set_t_bound, 0x0D);
+static IIO_DEVICE_ATTR(v3_hyst,
+ S_IRUGO | S_IWUSR,
+ ad7291_show_t_bound, ad7291_set_t_bound, 0x0F);
+static IIO_DEVICE_ATTR(v4_high,
+ S_IRUGO | S_IWUSR,
+ ad7291_show_t_bound, ad7291_set_t_bound, 0x10);
+static IIO_DEVICE_ATTR(v4_low,
+ S_IRUGO | S_IWUSR,
+ ad7291_show_t_bound, ad7291_set_t_bound, 0x11);
+static IIO_DEVICE_ATTR(v4_hyst,
+ S_IRUGO | S_IWUSR,
+ ad7291_show_t_bound, ad7291_set_t_bound, 0x12);
+static IIO_DEVICE_ATTR(v5_high,
+ S_IRUGO | S_IWUSR,
+ ad7291_show_t_bound, ad7291_set_t_bound, 0x13);
+static IIO_DEVICE_ATTR(v5_low,
+ S_IRUGO | S_IWUSR,
+ ad7291_show_t_bound, ad7291_set_t_bound, 0x14);
+static IIO_DEVICE_ATTR(v5_hyst,
+ S_IRUGO | S_IWUSR,
+ ad7291_show_t_bound, ad7291_set_t_bound, 0x15);
+static IIO_DEVICE_ATTR(v6_high,
+ S_IRUGO | S_IWUSR,
+ ad7291_show_t_bound, ad7291_set_t_bound, 0x16);
+static IIO_DEVICE_ATTR(v6_low,
+ S_IRUGO | S_IWUSR,
+ ad7291_show_t_bound, ad7291_set_t_bound, 0x17);
+static IIO_DEVICE_ATTR(v6_hyst,
+ S_IRUGO | S_IWUSR,
+ ad7291_show_t_bound, ad7291_set_t_bound, 0x18);
+static IIO_DEVICE_ATTR(v7_high,
+ S_IRUGO | S_IWUSR,
+ ad7291_show_t_bound, ad7291_set_t_bound, 0x19);
+static IIO_DEVICE_ATTR(v7_low,
+ S_IRUGO | S_IWUSR,
+ ad7291_show_t_bound, ad7291_set_t_bound, 0x1A);
+static IIO_DEVICE_ATTR(v7_hyst,
+ S_IRUGO | S_IWUSR,
+ ad7291_show_t_bound, ad7291_set_t_bound, 0x1B);
static struct attribute *ad7291_event_attributes[] = {
- &iio_event_attr_t_sense_high.dev_attr.attr,
- &iio_event_attr_t_sense_low.dev_attr.attr,
- &iio_event_attr_t_sense_hyst.dev_attr.attr,
- &iio_event_attr_v0_high.dev_attr.attr,
- &iio_event_attr_v0_low.dev_attr.attr,
- &iio_event_attr_v0_hyst.dev_attr.attr,
- &iio_event_attr_v1_high.dev_attr.attr,
- &iio_event_attr_v1_low.dev_attr.attr,
- &iio_event_attr_v1_hyst.dev_attr.attr,
- &iio_event_attr_v2_high.dev_attr.attr,
- &iio_event_attr_v2_low.dev_attr.attr,
- &iio_event_attr_v2_hyst.dev_attr.attr,
- &iio_event_attr_v3_high.dev_attr.attr,
- &iio_event_attr_v3_low.dev_attr.attr,
- &iio_event_attr_v3_hyst.dev_attr.attr,
- &iio_event_attr_v4_high.dev_attr.attr,
- &iio_event_attr_v4_low.dev_attr.attr,
- &iio_event_attr_v4_hyst.dev_attr.attr,
- &iio_event_attr_v5_high.dev_attr.attr,
- &iio_event_attr_v5_low.dev_attr.attr,
- &iio_event_attr_v5_hyst.dev_attr.attr,
- &iio_event_attr_v6_high.dev_attr.attr,
- &iio_event_attr_v6_low.dev_attr.attr,
- &iio_event_attr_v6_hyst.dev_attr.attr,
- &iio_event_attr_v7_high.dev_attr.attr,
- &iio_event_attr_v7_low.dev_attr.attr,
- &iio_event_attr_v7_hyst.dev_attr.attr,
+ &iio_dev_attr_t_sense_high_value.dev_attr.attr,
+ &iio_dev_attr_t_sense_low_value.dev_attr.attr,
+ &iio_dev_attr_t_sense_hyst_value.dev_attr.attr,
+ &iio_dev_attr_v0_high.dev_attr.attr,
+ &iio_dev_attr_v0_low.dev_attr.attr,
+ &iio_dev_attr_v0_hyst.dev_attr.attr,
+ &iio_dev_attr_v1_high.dev_attr.attr,
+ &iio_dev_attr_v1_low.dev_attr.attr,
+ &iio_dev_attr_v1_hyst.dev_attr.attr,
+ &iio_dev_attr_v2_high.dev_attr.attr,
+ &iio_dev_attr_v2_low.dev_attr.attr,
+ &iio_dev_attr_v2_hyst.dev_attr.attr,
+ &iio_dev_attr_v3_high.dev_attr.attr,
+ &iio_dev_attr_v3_low.dev_attr.attr,
+ &iio_dev_attr_v3_hyst.dev_attr.attr,
+ &iio_dev_attr_v4_high.dev_attr.attr,
+ &iio_dev_attr_v4_low.dev_attr.attr,
+ &iio_dev_attr_v4_hyst.dev_attr.attr,
+ &iio_dev_attr_v5_high.dev_attr.attr,
+ &iio_dev_attr_v5_low.dev_attr.attr,
+ &iio_dev_attr_v5_hyst.dev_attr.attr,
+ &iio_dev_attr_v6_high.dev_attr.attr,
+ &iio_dev_attr_v6_low.dev_attr.attr,
+ &iio_dev_attr_v6_hyst.dev_attr.attr,
+ &iio_dev_attr_v7_high.dev_attr.attr,
+ &iio_dev_attr_v7_low.dev_attr.attr,
+ &iio_dev_attr_v7_hyst.dev_attr.attr,
NULL,
};
@@ -904,6 +778,12 @@
.attrs = ad7291_event_attributes,
};
+static const struct iio_info ad7291_info = {
+ .attrs = &ad7291_attribute_group,
+ .num_interrupt_lines = 1,
+ .event_attrs = &ad7291_event_attribute_group,
+};
+
/*
* device probe and remove
*/
@@ -923,21 +803,18 @@
i2c_set_clientdata(client, chip);
chip->client = client;
- chip->name = id->name;
chip->command = AD7291_NOISE_DELAY | AD7291_T_SENSE_MASK;
- chip->indio_dev = iio_allocate_device();
+ chip->indio_dev = iio_allocate_device(0);
if (chip->indio_dev == NULL) {
ret = -ENOMEM;
goto error_free_chip;
}
+ chip->indio_dev->name = id->name;
chip->indio_dev->dev.parent = &client->dev;
- chip->indio_dev->attrs = &ad7291_attribute_group;
- chip->indio_dev->event_attrs = &ad7291_event_attribute_group;
+ chip->indio_dev->info = &ad7291_info;
chip->indio_dev->dev_data = (void *)chip;
- chip->indio_dev->driver_module = THIS_MODULE;
- chip->indio_dev->num_interrupt_lines = 1;
chip->indio_dev->modes = INDIO_DIRECT_MODE;
ret = iio_device_register(chip->indio_dev);
@@ -945,24 +822,15 @@
goto error_free_dev;
if (client->irq > 0) {
- ret = iio_register_interrupt_line(client->irq,
- chip->indio_dev,
- 0,
- IRQF_TRIGGER_LOW,
- chip->name);
+ ret = request_threaded_irq(client->irq,
+ NULL,
+ &ad7291_event_handler,
+ IRQF_TRIGGER_LOW | IRQF_ONESHOT,
+ id->name,
+ chip->indio_dev);
if (ret)
goto error_unreg_dev;
- /*
- * The event handler list element refer to iio_event_ad7291.
- * All event attributes bind to the same event handler.
- * So, only register event handler once.
- */
- iio_add_event_to_list(&iio_event_ad7291,
- &chip->indio_dev->interrupts[0]->ev_list);
-
- INIT_WORK(&chip->thresh_work, ad7291_interrupt_bh);
-
/* set irq polarity low level */
chip->command |= AD7291_ALART_POLARITY;
}
@@ -979,7 +847,7 @@
return 0;
error_unreg_irq:
- iio_unregister_interrupt_line(chip->indio_dev, 0);
+ free_irq(client->irq, chip->indio_dev);
error_unreg_dev:
iio_device_unregister(chip->indio_dev);
error_free_dev:
@@ -996,7 +864,7 @@
struct iio_dev *indio_dev = chip->indio_dev;
if (client->irq)
- iio_unregister_interrupt_line(indio_dev, 0);
+ free_irq(client->irq, chip->indio_dev);
iio_device_unregister(indio_dev);
iio_free_device(chip->indio_dev);
kfree(chip);
diff --git a/drivers/staging/iio/adc/ad7298.h b/drivers/staging/iio/adc/ad7298.h
index fe7ed77..628f5ad 100644
--- a/drivers/staging/iio/adc/ad7298.h
+++ b/drivers/staging/iio/adc/ad7298.h
@@ -17,14 +17,13 @@
#define AD7298_TAVG (1 << 1) /* temperature sensor averaging enable */
#define AD7298_PDD (1 << 0) /* partial power down enable */
-#define AD7298_CH_MASK (AD7298_CH0 | AD7298_CH1 | AD7298_CH2 | AD7298_CH3 | \
- AD7298_CH4 | AD7298_CH5 | AD7298_CH6 | AD7298_CH7)
-
#define AD7298_MAX_CHAN 8
#define AD7298_BITS 12
#define AD7298_STORAGE_BITS 16
#define AD7298_INTREF_mV 2500
+#define AD7298_CH_TEMP 9
+
#define RES_MASK(bits) ((1 << (bits)) - 1)
/*
@@ -37,11 +36,8 @@
};
struct ad7298_state {
- struct iio_dev *indio_dev;
struct spi_device *spi;
struct regulator *reg;
- struct work_struct poll_work;
- atomic_t protect_ring;
size_t d_size;
u16 int_vref_mv;
unsigned ext_ref;
@@ -58,11 +54,11 @@
};
#ifdef CONFIG_IIO_RING_BUFFER
-int ad7298_scan_from_ring(struct ad7298_state *st, long ch);
+int ad7298_scan_from_ring(struct iio_dev *indio_dev, long ch);
int ad7298_register_ring_funcs_and_init(struct iio_dev *indio_dev);
void ad7298_ring_cleanup(struct iio_dev *indio_dev);
#else /* CONFIG_IIO_RING_BUFFER */
-static inline int ad7298_scan_from_ring(struct ad7298_state *st, long ch)
+static inline int ad7298_scan_from_ring(struct iio_dev *indio_dev, long ch)
{
return 0;
}
diff --git a/drivers/staging/iio/adc/ad7298_core.c b/drivers/staging/iio/adc/ad7298_core.c
index 2e9154e..b8e4ae2 100644
--- a/drivers/staging/iio/adc/ad7298_core.c
+++ b/drivers/staging/iio/adc/ad7298_core.c
@@ -6,7 +6,6 @@
* Licensed under the GPL-2.
*/
-#include <linux/workqueue.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/slab.h>
@@ -23,6 +22,37 @@
#include "ad7298.h"
+static struct iio_chan_spec ad7298_channels[] = {
+ IIO_CHAN(IIO_TEMP, 0, 1, 0, NULL, 0, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SEPARATE),
+ 9, AD7298_CH_TEMP, IIO_ST('s', 32, 32, 0), 0),
+ IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 0, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 0, 0, IIO_ST('u', 12, 16, 0), 0),
+ IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 1, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 1, 1, IIO_ST('u', 12, 16, 0), 0),
+ IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 2, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 2, 2, IIO_ST('u', 12, 16, 0), 0),
+ IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 3, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 3, 3, IIO_ST('u', 12, 16, 0), 0),
+ IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 4, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 4, 4, IIO_ST('u', 12, 16, 0), 0),
+ IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 5, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 5, 5, IIO_ST('u', 12, 16, 0), 0),
+ IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 6, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 6, 6, IIO_ST('u', 12, 16, 0), 0),
+ IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 7, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 7, 7, IIO_ST('u', 12, 16, 0), 0),
+ IIO_CHAN_SOFT_TIMESTAMP(8),
+};
+
static int ad7298_scan_direct(struct ad7298_state *st, unsigned ch)
{
int ret;
@@ -36,55 +66,28 @@
return be16_to_cpu(st->rx_buf[0]);
}
-static ssize_t ad7298_scan(struct device *dev,
- struct device_attribute *attr,
- char *buf)
+static int ad7298_scan_temp(struct ad7298_state *st, int *val)
{
- struct iio_dev *dev_info = dev_get_drvdata(dev);
- struct ad7298_state *st = dev_info->dev_data;
- struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
- int ret;
-
- mutex_lock(&dev_info->mlock);
- if (iio_ring_enabled(dev_info))
- ret = ad7298_scan_from_ring(st, this_attr->address);
- else
- ret = ad7298_scan_direct(st, this_attr->address);
- mutex_unlock(&dev_info->mlock);
-
- if (ret < 0)
- return ret;
-
- return sprintf(buf, "%d\n", ret & RES_MASK(AD7298_BITS));
-}
-
-static IIO_DEV_ATTR_IN_RAW(0, ad7298_scan, 0);
-static IIO_DEV_ATTR_IN_RAW(1, ad7298_scan, 1);
-static IIO_DEV_ATTR_IN_RAW(2, ad7298_scan, 2);
-static IIO_DEV_ATTR_IN_RAW(3, ad7298_scan, 3);
-static IIO_DEV_ATTR_IN_RAW(4, ad7298_scan, 4);
-static IIO_DEV_ATTR_IN_RAW(5, ad7298_scan, 5);
-static IIO_DEV_ATTR_IN_RAW(6, ad7298_scan, 6);
-static IIO_DEV_ATTR_IN_RAW(7, ad7298_scan, 7);
-
-static ssize_t ad7298_show_temp(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- struct iio_dev *dev_info = dev_get_drvdata(dev);
- struct ad7298_state *st = iio_dev_get_devdata(dev_info);
- int tmp;
+ int tmp, ret;
tmp = cpu_to_be16(AD7298_WRITE | AD7298_TSENSE |
AD7298_TAVG | st->ext_ref);
- mutex_lock(&dev_info->mlock);
- spi_write(st->spi, (u8 *)&tmp, 2);
+ ret = spi_write(st->spi, (u8 *)&tmp, 2);
+ if (ret)
+ return ret;
+
tmp = 0;
- spi_write(st->spi, (u8 *)&tmp, 2);
+
+ ret = spi_write(st->spi, (u8 *)&tmp, 2);
+ if (ret)
+ return ret;
+
usleep_range(101, 1000); /* sleep > 100us */
- spi_read(st->spi, (u8 *)&tmp, 2);
- mutex_unlock(&dev_info->mlock);
+
+ ret = spi_read(st->spi, (u8 *)&tmp, 2);
+ if (ret)
+ return ret;
tmp = be16_to_cpu(tmp) & RES_MASK(AD7298_BITS);
@@ -101,65 +104,74 @@
tmp *= 250; /* temperature in milli degrees Celsius */
}
- return sprintf(buf, "%d\n", tmp);
+ *val = tmp;
+
+ return 0;
}
-static IIO_DEVICE_ATTR(temp0_input, S_IRUGO, ad7298_show_temp, NULL, 0);
-
-static ssize_t ad7298_show_scale(struct device *dev,
- struct device_attribute *attr,
- char *buf)
+static int ad7298_read_raw(struct iio_dev *dev_info,
+ struct iio_chan_spec const *chan,
+ int *val,
+ int *val2,
+ long m)
{
- struct iio_dev *dev_info = dev_get_drvdata(dev);
- struct ad7298_state *st = iio_dev_get_devdata(dev_info);
- /* Corresponds to Vref / 2^(bits) */
- unsigned int scale_uv = (st->int_vref_mv * 1000) >> AD7298_BITS;
+ int ret;
+ struct ad7298_state *st = iio_priv(dev_info);
+ unsigned int scale_uv;
- return sprintf(buf, "%d.%03d\n", scale_uv / 1000, scale_uv % 1000);
+ switch (m) {
+ case 0:
+ mutex_lock(&dev_info->mlock);
+ if (iio_ring_enabled(dev_info)) {
+ if (chan->address == AD7298_CH_TEMP)
+ ret = -ENODEV;
+ else
+ ret = ad7298_scan_from_ring(dev_info,
+ chan->address);
+ } else {
+ if (chan->address == AD7298_CH_TEMP)
+ ret = ad7298_scan_temp(st, val);
+ else
+ ret = ad7298_scan_direct(st, chan->address);
+ }
+ mutex_unlock(&dev_info->mlock);
+
+ if (ret < 0)
+ return ret;
+
+ if (chan->address != AD7298_CH_TEMP)
+ *val = ret & RES_MASK(AD7298_BITS);
+
+ return IIO_VAL_INT;
+ case (1 << IIO_CHAN_INFO_SCALE_SHARED):
+ scale_uv = (st->int_vref_mv * 1000) >> AD7298_BITS;
+ *val = scale_uv / 1000;
+ *val2 = (scale_uv % 1000) * 1000;
+ return IIO_VAL_INT_PLUS_MICRO;
+ case (1 << IIO_CHAN_INFO_SCALE_SEPARATE):
+ *val = 1;
+ *val2 = 0;
+ return IIO_VAL_INT_PLUS_MICRO;
+ }
+ return -EINVAL;
}
-static IIO_DEVICE_ATTR(in_scale, S_IRUGO, ad7298_show_scale, NULL, 0);
-static ssize_t ad7298_show_name(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- struct iio_dev *dev_info = dev_get_drvdata(dev);
- struct ad7298_state *st = iio_dev_get_devdata(dev_info);
-
- return sprintf(buf, "%s\n", spi_get_device_id(st->spi)->name);
-}
-static IIO_DEVICE_ATTR(name, S_IRUGO, ad7298_show_name, NULL, 0);
-
-static struct attribute *ad7298_attributes[] = {
- &iio_dev_attr_in0_raw.dev_attr.attr,
- &iio_dev_attr_in1_raw.dev_attr.attr,
- &iio_dev_attr_in2_raw.dev_attr.attr,
- &iio_dev_attr_in3_raw.dev_attr.attr,
- &iio_dev_attr_in4_raw.dev_attr.attr,
- &iio_dev_attr_in5_raw.dev_attr.attr,
- &iio_dev_attr_in6_raw.dev_attr.attr,
- &iio_dev_attr_in7_raw.dev_attr.attr,
- &iio_dev_attr_in_scale.dev_attr.attr,
- &iio_dev_attr_temp0_input.dev_attr.attr,
- &iio_dev_attr_name.dev_attr.attr,
- NULL,
-};
-
-static const struct attribute_group ad7298_attribute_group = {
- .attrs = ad7298_attributes,
+static const struct iio_info ad7298_info = {
+ .read_raw = &ad7298_read_raw,
+ .driver_module = THIS_MODULE,
};
static int __devinit ad7298_probe(struct spi_device *spi)
{
struct ad7298_platform_data *pdata = spi->dev.platform_data;
struct ad7298_state *st;
- int ret;
+ int ret, regdone = 0;
+ struct iio_dev *indio_dev = iio_allocate_device(sizeof(*st));
- st = kzalloc(sizeof(*st), GFP_KERNEL);
- if (st == NULL) {
- ret = -ENOMEM;
- goto error_ret;
- }
+ if (indio_dev == NULL)
+ return -ENOMEM;
+
+ st = iio_priv(indio_dev);
st->reg = regulator_get(&spi->dev, "vcc");
if (!IS_ERR(st->reg)) {
@@ -168,22 +180,16 @@
goto error_put_reg;
}
- spi_set_drvdata(spi, st);
+ spi_set_drvdata(spi, indio_dev);
- atomic_set(&st->protect_ring, 0);
st->spi = spi;
- st->indio_dev = iio_allocate_device();
- if (st->indio_dev == NULL) {
- ret = -ENOMEM;
- goto error_disable_reg;
- }
-
- st->indio_dev->dev.parent = &spi->dev;
- st->indio_dev->attrs = &ad7298_attribute_group;
- st->indio_dev->dev_data = (void *)(st);
- st->indio_dev->driver_module = THIS_MODULE;
- st->indio_dev->modes = INDIO_DIRECT_MODE;
+ indio_dev->name = spi_get_device_id(spi)->name;
+ indio_dev->dev.parent = &spi->dev;
+ indio_dev->modes = INDIO_DIRECT_MODE;
+ indio_dev->channels = ad7298_channels;
+ indio_dev->num_channels = ARRAY_SIZE(ad7298_channels);
+ indio_dev->info = &ad7298_info;
/* Setup default message */
@@ -208,39 +214,44 @@
st->int_vref_mv = AD7298_INTREF_mV;
}
- ret = ad7298_register_ring_funcs_and_init(st->indio_dev);
+ ret = ad7298_register_ring_funcs_and_init(indio_dev);
if (ret)
- goto error_free_device;
+ goto error_disable_reg;
- ret = iio_device_register(st->indio_dev);
+ ret = iio_device_register(indio_dev);
if (ret)
- goto error_free_device;
+ goto error_disable_reg;
+ regdone = 1;
- ret = iio_ring_buffer_register(st->indio_dev->ring, 0);
+ ret = iio_ring_buffer_register_ex(indio_dev->ring, 0,
+ &ad7298_channels[1], /* skip temp0 */
+ ARRAY_SIZE(ad7298_channels) - 1);
if (ret)
goto error_cleanup_ring;
+
return 0;
error_cleanup_ring:
- ad7298_ring_cleanup(st->indio_dev);
- iio_device_unregister(st->indio_dev);
-error_free_device:
- iio_free_device(st->indio_dev);
+ ad7298_ring_cleanup(indio_dev);
error_disable_reg:
if (!IS_ERR(st->reg))
regulator_disable(st->reg);
error_put_reg:
if (!IS_ERR(st->reg))
regulator_put(st->reg);
- kfree(st);
-error_ret:
+
+ if (regdone)
+ iio_device_unregister(indio_dev);
+ else
+ iio_free_device(indio_dev);
+
return ret;
}
static int __devexit ad7298_remove(struct spi_device *spi)
{
- struct ad7298_state *st = spi_get_drvdata(spi);
- struct iio_dev *indio_dev = st->indio_dev;
+ struct iio_dev *indio_dev = spi_get_drvdata(spi);
+ struct ad7298_state *st = iio_priv(indio_dev);
iio_ring_buffer_unregister(indio_dev->ring);
ad7298_ring_cleanup(indio_dev);
@@ -249,7 +260,8 @@
regulator_disable(st->reg);
regulator_put(st->reg);
}
- kfree(st);
+ iio_device_unregister(indio_dev);
+
return 0;
}
diff --git a/drivers/staging/iio/adc/ad7298_ring.c b/drivers/staging/iio/adc/ad7298_ring.c
index 9068d7f..a04c033 100644
--- a/drivers/staging/iio/adc/ad7298_ring.c
+++ b/drivers/staging/iio/adc/ad7298_ring.c
@@ -7,7 +7,6 @@
*/
#include <linux/interrupt.h>
-#include <linux/workqueue.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/slab.h>
@@ -22,52 +21,9 @@
#include "ad7298.h"
-static IIO_SCAN_EL_C(in0, 0, 0, NULL);
-static IIO_SCAN_EL_C(in1, 1, 0, NULL);
-static IIO_SCAN_EL_C(in2, 2, 0, NULL);
-static IIO_SCAN_EL_C(in3, 3, 0, NULL);
-static IIO_SCAN_EL_C(in4, 4, 0, NULL);
-static IIO_SCAN_EL_C(in5, 5, 0, NULL);
-static IIO_SCAN_EL_C(in6, 6, 0, NULL);
-static IIO_SCAN_EL_C(in7, 7, 0, NULL);
-
-static IIO_SCAN_EL_TIMESTAMP(8);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(timestamp, s, 64, 64);
-
-static IIO_CONST_ATTR(in_type, "u12/16") ;
-
-static struct attribute *ad7298_scan_el_attrs[] = {
- &iio_scan_el_in0.dev_attr.attr,
- &iio_const_attr_in0_index.dev_attr.attr,
- &iio_scan_el_in1.dev_attr.attr,
- &iio_const_attr_in1_index.dev_attr.attr,
- &iio_scan_el_in2.dev_attr.attr,
- &iio_const_attr_in2_index.dev_attr.attr,
- &iio_scan_el_in3.dev_attr.attr,
- &iio_const_attr_in3_index.dev_attr.attr,
- &iio_scan_el_in4.dev_attr.attr,
- &iio_const_attr_in4_index.dev_attr.attr,
- &iio_scan_el_in5.dev_attr.attr,
- &iio_const_attr_in5_index.dev_attr.attr,
- &iio_scan_el_in6.dev_attr.attr,
- &iio_const_attr_in6_index.dev_attr.attr,
- &iio_scan_el_in7.dev_attr.attr,
- &iio_const_attr_in7_index.dev_attr.attr,
- &iio_const_attr_timestamp_index.dev_attr.attr,
- &iio_scan_el_timestamp.dev_attr.attr,
- &iio_const_attr_timestamp_type.dev_attr.attr,
- &iio_const_attr_in_type.dev_attr.attr,
- NULL,
-};
-
-static struct attribute_group ad7298_scan_el_group = {
- .name = "scan_elements",
- .attrs = ad7298_scan_el_attrs,
-};
-
-int ad7298_scan_from_ring(struct ad7298_state *st, long ch)
+int ad7298_scan_from_ring(struct iio_dev *dev_info, long ch)
{
- struct iio_ring_buffer *ring = st->indio_dev->ring;
+ struct iio_ring_buffer *ring = dev_info->ring;
int ret;
u16 *ring_data;
@@ -76,12 +32,13 @@
goto error_ret;
}
- ring_data = kmalloc(ring->access.get_bytes_per_datum(ring), GFP_KERNEL);
+ ring_data = kmalloc(ring->access->get_bytes_per_datum(ring),
+ GFP_KERNEL);
if (ring_data == NULL) {
ret = -ENOMEM;
goto error_ret;
}
- ret = ring->access.read_last(ring, (u8 *) ring_data);
+ ret = ring->access->read_last(ring, (u8 *) ring_data);
if (ret)
goto error_free_ring_data;
@@ -102,7 +59,7 @@
**/
static int ad7298_ring_preenable(struct iio_dev *indio_dev)
{
- struct ad7298_state *st = indio_dev->dev_data;
+ struct ad7298_state *st = iio_priv(indio_dev);
struct iio_ring_buffer *ring = indio_dev->ring;
size_t d_size;
int i, m;
@@ -117,8 +74,8 @@
d_size += sizeof(s64) - (d_size % sizeof(s64));
}
- if (ring->access.set_bytes_per_datum)
- ring->access.set_bytes_per_datum(ring, d_size);
+ if (ring->access->set_bytes_per_datum)
+ ring->access->set_bytes_per_datum(ring, d_size);
st->d_size = d_size;
@@ -155,47 +112,24 @@
}
/**
- * ad7298_poll_func_th() th of trigger launched polling to ring buffer
- *
- * As sampling only occurs on spi comms occurring, leave timestamping until
- * then. Some triggers will generate their own time stamp. Currently
- * there is no way of notifying them when no one cares.
- **/
-static void ad7298_poll_func_th(struct iio_dev *indio_dev, s64 time)
-{
- struct ad7298_state *st = indio_dev->dev_data;
-
- schedule_work(&st->poll_work);
- return;
-}
-
-/**
- * ad7298_poll_bh_to_ring() bh of trigger launched polling to ring buffer
- * @work_s: the work struct through which this was scheduled
+ * ad7298_trigger_handler() bh of trigger launched polling to ring buffer
*
* Currently there is no option in this driver to disable the saving of
* timestamps within the ring.
- * I think the one copy of this at a time was to avoid problems if the
- * trigger was set far too high and the reads then locked up the computer.
**/
-static void ad7298_poll_bh_to_ring(struct work_struct *work_s)
+static irqreturn_t ad7298_trigger_handler(int irq, void *p)
{
- struct ad7298_state *st = container_of(work_s, struct ad7298_state,
- poll_work);
- struct iio_dev *indio_dev = st->indio_dev;
- struct iio_sw_ring_buffer *sw_ring = iio_to_sw_ring(indio_dev->ring);
+ struct iio_poll_func *pf = p;
+ struct iio_dev *indio_dev = pf->private_data;
+ struct ad7298_state *st = iio_priv(indio_dev);
struct iio_ring_buffer *ring = indio_dev->ring;
s64 time_ns;
__u16 buf[16];
int b_sent, i;
- /* Ensure only one copy of this function running at a time */
- if (atomic_inc_return(&st->protect_ring) > 1)
- return;
-
b_sent = spi_sync(st->spi, &st->ring_msg);
if (b_sent)
- goto done;
+ return b_sent;
if (ring->scan_timestamp) {
time_ns = iio_get_time_ns();
@@ -206,14 +140,20 @@
for (i = 0; i < ring->scan_count; i++)
buf[i] = be16_to_cpu(st->rx_buf[i]);
- indio_dev->ring->access.store_to(&sw_ring->buf, (u8 *)buf, time_ns);
-done:
- atomic_dec(&st->protect_ring);
+ indio_dev->ring->access->store_to(ring, (u8 *)buf, time_ns);
+ iio_trigger_notify_done(indio_dev->trig);
+
+ return IRQ_HANDLED;
}
+static const struct iio_ring_setup_ops ad7298_ring_setup_ops = {
+ .preenable = &ad7298_ring_preenable,
+ .postenable = &iio_triggered_ring_postenable,
+ .predisable = &iio_triggered_ring_predisable,
+};
+
int ad7298_register_ring_funcs_and_init(struct iio_dev *indio_dev)
{
- struct ad7298_state *st = indio_dev->dev_data;
int ret;
indio_dev->ring = iio_sw_rb_allocate(indio_dev);
@@ -222,24 +162,28 @@
goto error_ret;
}
/* Effectively select the ring buffer implementation */
- iio_ring_sw_register_funcs(&indio_dev->ring->access);
- ret = iio_alloc_pollfunc(indio_dev, NULL, &ad7298_poll_func_th);
- if (ret)
+ indio_dev->ring->access = &ring_sw_access_funcs;
+
+ indio_dev->pollfunc = iio_alloc_pollfunc(NULL,
+ &ad7298_trigger_handler,
+ IRQF_ONESHOT,
+ indio_dev,
+ "ad7298_consumer%d",
+ indio_dev->id);
+
+ if (indio_dev->pollfunc == NULL) {
+ ret = -ENOMEM;
goto error_deallocate_sw_rb;
+ }
/* Ring buffer functions - here trigger setup related */
-
- indio_dev->ring->preenable = &ad7298_ring_preenable;
- indio_dev->ring->postenable = &iio_triggered_ring_postenable;
- indio_dev->ring->predisable = &iio_triggered_ring_predisable;
- indio_dev->ring->scan_el_attrs = &ad7298_scan_el_group;
+ indio_dev->ring->setup_ops = &ad7298_ring_setup_ops;
indio_dev->ring->scan_timestamp = true;
- INIT_WORK(&st->poll_work, &ad7298_poll_bh_to_ring);
-
/* Flag that polled ring buffering is possible */
indio_dev->modes |= INDIO_RING_TRIGGERED;
return 0;
+
error_deallocate_sw_rb:
iio_sw_rb_free(indio_dev->ring);
error_ret:
@@ -253,6 +197,6 @@
iio_trigger_dettach_poll_func(indio_dev->trig,
indio_dev->pollfunc);
}
- kfree(indio_dev->pollfunc);
+ iio_dealloc_pollfunc(indio_dev->pollfunc);
iio_sw_rb_free(indio_dev->ring);
}
diff --git a/drivers/staging/iio/adc/ad7314.c b/drivers/staging/iio/adc/ad7314.c
index 8c17b1f..98bb16f 100644
--- a/drivers/staging/iio/adc/ad7314.c
+++ b/drivers/staging/iio/adc/ad7314.c
@@ -6,16 +6,11 @@
* Licensed under the GPL-2 or later.
*/
-#include <linux/interrupt.h>
-#include <linux/gpio.h>
-#include <linux/workqueue.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
-#include <linux/list.h>
#include <linux/spi/spi.h>
-#include <linux/rtc.h>
#include "../iio.h"
#include "../sysfs.h"
@@ -47,7 +42,6 @@
*/
struct ad7314_chip_info {
- const char *name;
struct spi_device *spi_dev;
struct iio_dev *indio_dev;
s64 last_timestamp;
@@ -160,7 +154,7 @@
if (chip->mode)
ad7314_spi_write(chip, chip->mode);
- if (strcmp(chip->name, "ad7314")) {
+ if (strcmp(dev_info->name, "ad7314")) {
data = (data & AD7314_TEMP_MASK) >>
AD7314_TEMP_OFFSET;
if (data & AD7314_TEMP_SIGN) {
@@ -186,22 +180,10 @@
static IIO_DEVICE_ATTR(temperature, S_IRUGO, ad7314_show_temperature, NULL, 0);
-static ssize_t ad7314_show_name(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- struct iio_dev *dev_info = dev_get_drvdata(dev);
- struct ad7314_chip_info *chip = dev_info->dev_data;
- return sprintf(buf, "%s\n", chip->name);
-}
-
-static IIO_DEVICE_ATTR(name, S_IRUGO, ad7314_show_name, NULL, 0);
-
static struct attribute *ad7314_attributes[] = {
&iio_dev_attr_available_modes.dev_attr.attr,
&iio_dev_attr_mode.dev_attr.attr,
&iio_dev_attr_temperature.dev_attr.attr,
- &iio_dev_attr_name.dev_attr.attr,
NULL,
};
@@ -209,6 +191,10 @@
.attrs = ad7314_attributes,
};
+static const struct iio_info ad7314_info = {
+ .attrs = &ad7314_attribute_group,
+ .driver_module = THIS_MODULE,
+};
/*
* device probe and remove
*/
@@ -227,25 +213,24 @@
dev_set_drvdata(&spi_dev->dev, chip);
chip->spi_dev = spi_dev;
- chip->name = spi_dev->modalias;
- chip->indio_dev = iio_allocate_device();
+ chip->indio_dev = iio_allocate_device(0);
if (chip->indio_dev == NULL) {
ret = -ENOMEM;
goto error_free_chip;
}
+ chip->indio_dev->name = spi_get_device_id(spi_dev)->name;
chip->indio_dev->dev.parent = &spi_dev->dev;
- chip->indio_dev->attrs = &ad7314_attribute_group;
+ chip->indio_dev->info = &ad7314_info;
chip->indio_dev->dev_data = (void *)chip;
- chip->indio_dev->driver_module = THIS_MODULE;
ret = iio_device_register(chip->indio_dev);
if (ret)
goto error_free_dev;
dev_info(&spi_dev->dev, "%s temperature sensor registered.\n",
- chip->name);
+ chip->indio_dev->name);
return 0;
error_free_dev:
@@ -262,8 +247,6 @@
struct iio_dev *indio_dev = chip->indio_dev;
dev_set_drvdata(&spi_dev->dev, NULL);
- if (spi_dev->irq)
- iio_unregister_interrupt_line(indio_dev, 0);
iio_device_unregister(indio_dev);
iio_free_device(chip->indio_dev);
kfree(chip);
diff --git a/drivers/staging/iio/adc/ad7476.h b/drivers/staging/iio/adc/ad7476.h
index f917e9c..01a7021 100644
--- a/drivers/staging/iio/adc/ad7476.h
+++ b/drivers/staging/iio/adc/ad7476.h
@@ -19,11 +19,8 @@
};
struct ad7476_chip_info {
- u8 bits;
- u8 storagebits;
- u8 res_shift;
- char sign;
u16 int_vref_mv;
+ struct iio_chan_spec channel[2];
};
struct ad7476_state {
@@ -31,8 +28,6 @@
struct spi_device *spi;
const struct ad7476_chip_info *chip_info;
struct regulator *reg;
- struct work_struct poll_work;
- atomic_t protect_ring;
size_t d_size;
u16 int_vref_mv;
struct spi_transfer xfer;
diff --git a/drivers/staging/iio/adc/ad7476_core.c b/drivers/staging/iio/adc/ad7476_core.c
index d263904..50cedb4 100644
--- a/drivers/staging/iio/adc/ad7476_core.c
+++ b/drivers/staging/iio/adc/ad7476_core.c
@@ -6,13 +6,10 @@
* Licensed under the GPL-2 or later.
*/
-#include <linux/interrupt.h>
-#include <linux/workqueue.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
-#include <linux/list.h>
#include <linux/spi/spi.h>
#include <linux/regulator/consumer.h>
#include <linux/err.h>
@@ -35,117 +32,97 @@
return (st->data[0] << 8) | st->data[1];
}
-static ssize_t ad7476_scan(struct device *dev,
- struct device_attribute *attr,
- char *buf)
+static int ad7476_read_raw(struct iio_dev *dev_info,
+ struct iio_chan_spec const *chan,
+ int *val,
+ int *val2,
+ long m)
{
- struct iio_dev *dev_info = dev_get_drvdata(dev);
- struct ad7476_state *st = dev_info->dev_data;
int ret;
+ struct ad7476_state *st = dev_info->dev_data;
+ unsigned int scale_uv;
- mutex_lock(&dev_info->mlock);
- if (iio_ring_enabled(dev_info))
- ret = ad7476_scan_from_ring(st);
- else
- ret = ad7476_scan_direct(st);
- mutex_unlock(&dev_info->mlock);
+ switch (m) {
+ case 0:
+ mutex_lock(&dev_info->mlock);
+ if (iio_ring_enabled(dev_info))
+ ret = ad7476_scan_from_ring(st);
+ else
+ ret = ad7476_scan_direct(st);
+ mutex_unlock(&dev_info->mlock);
- if (ret < 0)
- return ret;
-
- return sprintf(buf, "%d\n", (ret >> st->chip_info->res_shift) &
- RES_MASK(st->chip_info->bits));
+ if (ret < 0)
+ return ret;
+ *val = (ret >> st->chip_info->channel[0].scan_type.shift) &
+ RES_MASK(st->chip_info->channel[0].scan_type.realbits);
+ return IIO_VAL_INT;
+ case (1 << IIO_CHAN_INFO_SCALE_SHARED):
+ scale_uv = (st->int_vref_mv * 1000)
+ >> st->chip_info->channel[0].scan_type.realbits;
+ *val = scale_uv/1000;
+ *val2 = (scale_uv%1000)*1000;
+ return IIO_VAL_INT_PLUS_MICRO;
+ }
+ return -EINVAL;
}
-static IIO_DEV_ATTR_IN_RAW(0, ad7476_scan, 0);
-
-static ssize_t ad7476_show_scale(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- /* Driver currently only support internal vref */
- struct iio_dev *dev_info = dev_get_drvdata(dev);
- struct ad7476_state *st = iio_dev_get_devdata(dev_info);
- /* Corresponds to Vref / 2^(bits) */
- unsigned int scale_uv = (st->int_vref_mv * 1000) >> st->chip_info->bits;
-
- return sprintf(buf, "%d.%03d\n", scale_uv / 1000, scale_uv % 1000);
-}
-static IIO_DEVICE_ATTR(in_scale, S_IRUGO, ad7476_show_scale, NULL, 0);
-
-static ssize_t ad7476_show_name(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- struct iio_dev *dev_info = dev_get_drvdata(dev);
- struct ad7476_state *st = iio_dev_get_devdata(dev_info);
-
- return sprintf(buf, "%s\n", spi_get_device_id(st->spi)->name);
-}
-static IIO_DEVICE_ATTR(name, S_IRUGO, ad7476_show_name, NULL, 0);
-
-static struct attribute *ad7476_attributes[] = {
- &iio_dev_attr_in0_raw.dev_attr.attr,
- &iio_dev_attr_in_scale.dev_attr.attr,
- &iio_dev_attr_name.dev_attr.attr,
- NULL,
-};
-
-static const struct attribute_group ad7476_attribute_group = {
- .attrs = ad7476_attributes,
-};
static const struct ad7476_chip_info ad7476_chip_info_tbl[] = {
[ID_AD7466] = {
- .bits = 12,
- .storagebits = 16,
- .res_shift = 0,
- .sign = IIO_SCAN_EL_TYPE_UNSIGNED,
+ .channel[0] = IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 0, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 0, 0, IIO_ST('u', 12, 16, 0), 0),
+ .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
},
[ID_AD7467] = {
- .bits = 10,
- .storagebits = 16,
- .res_shift = 2,
- .sign = IIO_SCAN_EL_TYPE_UNSIGNED,
+ .channel[0] = IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 0, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 0, 0, IIO_ST('u', 10, 16, 2), 0),
+ .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
},
[ID_AD7468] = {
- .bits = 8,
- .storagebits = 16,
- .res_shift = 4,
- .sign = IIO_SCAN_EL_TYPE_UNSIGNED,
+ .channel[0] = IIO_CHAN(IIO_IN, 0, 1 , 0, NULL, 0, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 0, 0, IIO_ST('u', 8, 16, 4), 0),
+ .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
},
[ID_AD7475] = {
- .bits = 12,
- .storagebits = 16,
- .res_shift = 0,
- .sign = IIO_SCAN_EL_TYPE_UNSIGNED,
+ .channel[0] = IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 0, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 0, 0, IIO_ST('u', 12, 16, 0), 0),
+ .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
},
[ID_AD7476] = {
- .bits = 12,
- .storagebits = 16,
- .res_shift = 0,
- .sign = IIO_SCAN_EL_TYPE_UNSIGNED,
+ .channel[0] = IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 0, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 0, 0, IIO_ST('u', 12, 16, 0), 0),
+ .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
},
[ID_AD7477] = {
- .bits = 10,
- .storagebits = 16,
- .res_shift = 2,
- .sign = IIO_SCAN_EL_TYPE_UNSIGNED,
+ .channel[0] = IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 0, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 0, 0, IIO_ST('u', 10, 16, 2), 0),
+ .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
},
[ID_AD7478] = {
- .bits = 8,
- .storagebits = 16,
- .res_shift = 4,
- .sign = IIO_SCAN_EL_TYPE_UNSIGNED,
+ .channel[0] = IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 0, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 0, 0, IIO_ST('u', 8, 16, 4), 0),
+ .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
},
[ID_AD7495] = {
- .bits = 12,
- .storagebits = 16,
- .res_shift = 0,
+ .channel[0] = IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 0, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 0, 0, IIO_ST('u', 12, 16, 0), 0),
+ .channel[1] = IIO_CHAN_SOFT_TIMESTAMP(1),
.int_vref_mv = 2500,
- .sign = IIO_SCAN_EL_TYPE_UNSIGNED,
},
};
+static const struct iio_info ad7476_info = {
+ .driver_module = THIS_MODULE,
+ .read_raw = &ad7476_read_raw,
+};
+
static int __devinit ad7476_probe(struct spi_device *spi)
{
struct ad7476_platform_data *pdata = spi->dev.platform_data;
@@ -181,10 +158,9 @@
spi_set_drvdata(spi, st);
- atomic_set(&st->protect_ring, 0);
st->spi = spi;
- st->indio_dev = iio_allocate_device();
+ st->indio_dev = iio_allocate_device(0);
if (st->indio_dev == NULL) {
ret = -ENOMEM;
goto error_disable_reg;
@@ -192,15 +168,16 @@
/* Establish that the iio_dev is a child of the spi device */
st->indio_dev->dev.parent = &spi->dev;
- st->indio_dev->attrs = &ad7476_attribute_group;
+ st->indio_dev->name = spi_get_device_id(spi)->name;
st->indio_dev->dev_data = (void *)(st);
- st->indio_dev->driver_module = THIS_MODULE;
st->indio_dev->modes = INDIO_DIRECT_MODE;
-
+ st->indio_dev->channels = st->chip_info->channel;
+ st->indio_dev->num_channels = 2;
+ st->indio_dev->info = &ad7476_info;
/* Setup default message */
st->xfer.rx_buf = &st->data;
- st->xfer.len = st->chip_info->storagebits / 8;
+ st->xfer.len = st->chip_info->channel[0].scan_type.storagebits / 8;
spi_message_init(&st->msg);
spi_message_add_tail(&st->xfer, &st->msg);
@@ -213,7 +190,9 @@
if (ret)
goto error_free_device;
- ret = iio_ring_buffer_register(st->indio_dev->ring, 0);
+ ret = iio_ring_buffer_register_ex(st->indio_dev->ring, 0,
+ st->chip_info->channel,
+ ARRAY_SIZE(st->chip_info->channel));
if (ret)
goto error_cleanup_ring;
return 0;
diff --git a/drivers/staging/iio/adc/ad7476_ring.c b/drivers/staging/iio/adc/ad7476_ring.c
index 92d9378..b1b2ee2 100644
--- a/drivers/staging/iio/adc/ad7476_ring.c
+++ b/drivers/staging/iio/adc/ad7476_ring.c
@@ -8,13 +8,10 @@
*/
#include <linux/interrupt.h>
-#include <linux/gpio.h>
-#include <linux/workqueue.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
-#include <linux/list.h>
#include <linux/spi/spi.h>
#include "../iio.h"
@@ -25,51 +22,19 @@
#include "ad7476.h"
-static IIO_SCAN_EL_C(in0, 0, 0, NULL);
-static IIO_SCAN_EL_TIMESTAMP(1);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(timestamp, s, 64, 64);
-
-static ssize_t ad7476_show_type(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- struct iio_ring_buffer *ring = dev_get_drvdata(dev);
- struct iio_dev *indio_dev = ring->indio_dev;
- struct ad7476_state *st = indio_dev->dev_data;
-
- return sprintf(buf, "%c%d/%d>>%d\n", st->chip_info->sign,
- st->chip_info->bits, st->chip_info->storagebits,
- st->chip_info->res_shift);
-}
-static IIO_DEVICE_ATTR(in_type, S_IRUGO, ad7476_show_type, NULL, 0);
-
-static struct attribute *ad7476_scan_el_attrs[] = {
- &iio_scan_el_in0.dev_attr.attr,
- &iio_const_attr_in0_index.dev_attr.attr,
- &iio_const_attr_timestamp_index.dev_attr.attr,
- &iio_scan_el_timestamp.dev_attr.attr,
- &iio_const_attr_timestamp_type.dev_attr.attr,
- &iio_dev_attr_in_type.dev_attr.attr,
- NULL,
-};
-
-static struct attribute_group ad7476_scan_el_group = {
- .name = "scan_elements",
- .attrs = ad7476_scan_el_attrs,
-};
-
int ad7476_scan_from_ring(struct ad7476_state *st)
{
struct iio_ring_buffer *ring = st->indio_dev->ring;
int ret;
u8 *ring_data;
- ring_data = kmalloc(ring->access.get_bytes_per_datum(ring), GFP_KERNEL);
+ ring_data = kmalloc(ring->access->get_bytes_per_datum(ring),
+ GFP_KERNEL);
if (ring_data == NULL) {
ret = -ENOMEM;
goto error_ret;
}
- ret = ring->access.read_last(ring, ring_data);
+ ret = ring->access->read_last(ring, ring_data);
if (ret)
goto error_free_ring_data;
@@ -93,7 +58,8 @@
struct ad7476_state *st = indio_dev->dev_data;
struct iio_ring_buffer *ring = indio_dev->ring;
- st->d_size = ring->scan_count * st->chip_info->storagebits / 8;
+ st->d_size = ring->scan_count *
+ st->chip_info->channel[0].scan_type.storagebits / 8;
if (ring->scan_timestamp) {
st->d_size += sizeof(s64);
@@ -102,55 +68,28 @@
st->d_size += sizeof(s64) - (st->d_size % sizeof(s64));
}
- if (indio_dev->ring->access.set_bytes_per_datum)
- indio_dev->ring->access.set_bytes_per_datum(indio_dev->ring,
+ if (indio_dev->ring->access->set_bytes_per_datum)
+ indio_dev->ring->access->set_bytes_per_datum(indio_dev->ring,
st->d_size);
return 0;
}
-/**
- * ad7476_poll_func_th() th of trigger launched polling to ring buffer
- *
- * As sampling only occurs on i2c comms occurring, leave timestamping until
- * then. Some triggers will generate their own time stamp. Currently
- * there is no way of notifying them when no one cares.
- **/
-static void ad7476_poll_func_th(struct iio_dev *indio_dev, s64 time)
+static irqreturn_t ad7476_trigger_handler(int irq, void *p)
{
- struct ad7476_state *st = indio_dev->dev_data;
-
- schedule_work(&st->poll_work);
- return;
-}
-/**
- * ad7476_poll_bh_to_ring() bh of trigger launched polling to ring buffer
- * @work_s: the work struct through which this was scheduled
- *
- * Currently there is no option in this driver to disable the saving of
- * timestamps within the ring.
- * I think the one copy of this at a time was to avoid problems if the
- * trigger was set far too high and the reads then locked up the computer.
- **/
-static void ad7476_poll_bh_to_ring(struct work_struct *work_s)
-{
- struct ad7476_state *st = container_of(work_s, struct ad7476_state,
- poll_work);
- struct iio_dev *indio_dev = st->indio_dev;
- struct iio_sw_ring_buffer *sw_ring = iio_to_sw_ring(indio_dev->ring);
+ struct iio_poll_func *pf = p;
+ struct iio_dev *indio_dev = pf->private_data;
+ struct ad7476_state *st = iio_dev_get_devdata(indio_dev);
s64 time_ns;
__u8 *rxbuf;
int b_sent;
- /* Ensure only one copy of this function running at a time */
- if (atomic_inc_return(&st->protect_ring) > 1)
- return;
-
rxbuf = kzalloc(st->d_size, GFP_KERNEL);
if (rxbuf == NULL)
- return;
+ return -ENOMEM;
- b_sent = spi_read(st->spi, rxbuf, st->chip_info->storagebits / 8);
+ b_sent = spi_read(st->spi, rxbuf,
+ st->chip_info->channel[0].scan_type.storagebits / 8);
if (b_sent < 0)
goto done;
@@ -160,12 +99,20 @@
memcpy(rxbuf + st->d_size - sizeof(s64),
&time_ns, sizeof(time_ns));
- indio_dev->ring->access.store_to(&sw_ring->buf, rxbuf, time_ns);
+ indio_dev->ring->access->store_to(indio_dev->ring, rxbuf, time_ns);
done:
+ iio_trigger_notify_done(indio_dev->trig);
kfree(rxbuf);
- atomic_dec(&st->protect_ring);
+
+ return IRQ_HANDLED;
}
+static const struct iio_ring_setup_ops ad7476_ring_setup_ops = {
+ .preenable = &ad7476_ring_preenable,
+ .postenable = &iio_triggered_ring_postenable,
+ .predisable = &iio_triggered_ring_predisable,
+};
+
int ad7476_register_ring_funcs_and_init(struct iio_dev *indio_dev)
{
struct ad7476_state *st = indio_dev->dev_data;
@@ -177,24 +124,28 @@
goto error_ret;
}
/* Effectively select the ring buffer implementation */
- iio_ring_sw_register_funcs(&indio_dev->ring->access);
- ret = iio_alloc_pollfunc(indio_dev, NULL, &ad7476_poll_func_th);
- if (ret)
+ indio_dev->ring->access = &ring_sw_access_funcs;
+ indio_dev->pollfunc
+ = iio_alloc_pollfunc(NULL,
+ &ad7476_trigger_handler,
+ IRQF_ONESHOT,
+ indio_dev,
+ "%s_consumer%d",
+ spi_get_device_id(st->spi)->name,
+ indio_dev->id);
+ if (indio_dev->pollfunc == NULL) {
+ ret = -ENOMEM;
goto error_deallocate_sw_rb;
+ }
/* Ring buffer functions - here trigger setup related */
-
- indio_dev->ring->preenable = &ad7476_ring_preenable;
- indio_dev->ring->postenable = &iio_triggered_ring_postenable;
- indio_dev->ring->predisable = &iio_triggered_ring_predisable;
- indio_dev->ring->scan_el_attrs = &ad7476_scan_el_group;
+ indio_dev->ring->setup_ops = &ad7476_ring_setup_ops;
indio_dev->ring->scan_timestamp = true;
- INIT_WORK(&st->poll_work, &ad7476_poll_bh_to_ring);
-
/* Flag that polled ring buffering is possible */
indio_dev->modes |= INDIO_RING_TRIGGERED;
return 0;
+
error_deallocate_sw_rb:
iio_sw_rb_free(indio_dev->ring);
error_ret:
@@ -209,6 +160,6 @@
iio_trigger_dettach_poll_func(indio_dev->trig,
indio_dev->pollfunc);
}
- kfree(indio_dev->pollfunc);
+ iio_dealloc_pollfunc(indio_dev->pollfunc);
iio_sw_rb_free(indio_dev->ring);
}
diff --git a/drivers/staging/iio/adc/ad7606.h b/drivers/staging/iio/adc/ad7606.h
index 338bade..b8b3d8e 100644
--- a/drivers/staging/iio/adc/ad7606.h
+++ b/drivers/staging/iio/adc/ad7606.h
@@ -43,17 +43,17 @@
/**
* struct ad7606_chip_info - chip specifc information
* @name: indentification string for chip
- * @bits: accuracy of the adc in bits
- * @bits: output coding [s]igned or [u]nsigned
* @int_vref_mv: the internal reference voltage
- * @num_channels: number of physical inputs on chip
+ * @channels: channel specification
+ * @num_channels: number of channels
*/
struct ad7606_chip_info {
- char name[10];
+ const char *name;
u8 bits;
char sign;
u16 int_vref_mv;
+ struct iio_chan_spec *channels;
unsigned num_channels;
};
@@ -62,14 +62,12 @@
*/
struct ad7606_state {
- struct iio_dev *indio_dev;
struct device *dev;
const struct ad7606_chip_info *chip_info;
struct ad7606_platform_data *pdata;
struct regulator *reg;
struct work_struct poll_work;
wait_queue_head_t wq_data_avail;
- atomic_t protect_ring;
size_t d_size;
const struct ad7606_bus_ops *bops;
int irq;
@@ -97,12 +95,12 @@
int (*read_block)(struct device *, int, void *);
};
-void ad7606_suspend(struct ad7606_state *st);
-void ad7606_resume(struct ad7606_state *st);
-struct ad7606_state *ad7606_probe(struct device *dev, int irq,
+void ad7606_suspend(struct iio_dev *indio_dev);
+void ad7606_resume(struct iio_dev *indio_dev);
+struct iio_dev *ad7606_probe(struct device *dev, int irq,
void __iomem *base_address, unsigned id,
const struct ad7606_bus_ops *bops);
-int ad7606_remove(struct ad7606_state *st);
+int ad7606_remove(struct iio_dev *indio_dev);
int ad7606_reset(struct ad7606_state *st);
enum ad7606_supported_device_ids {
@@ -111,7 +109,7 @@
ID_AD7606_4
};
-int ad7606_scan_from_ring(struct ad7606_state *st, unsigned ch);
+int ad7606_scan_from_ring(struct iio_dev *indio_dev, unsigned ch);
int ad7606_register_ring_funcs_and_init(struct iio_dev *indio_dev);
void ad7606_ring_cleanup(struct iio_dev *indio_dev);
#endif /* IIO_ADC_AD7606_H_ */
diff --git a/drivers/staging/iio/adc/ad7606_core.c b/drivers/staging/iio/adc/ad7606_core.c
index 4c700f0..459371a 100644
--- a/drivers/staging/iio/adc/ad7606_core.c
+++ b/drivers/staging/iio/adc/ad7606_core.c
@@ -7,12 +7,10 @@
*/
#include <linux/interrupt.h>
-#include <linux/workqueue.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
-#include <linux/list.h>
#include <linux/regulator/consumer.h>
#include <linux/err.h>
#include <linux/gpio.h>
@@ -38,8 +36,9 @@
return -ENODEV;
}
-static int ad7606_scan_direct(struct ad7606_state *st, unsigned ch)
+static int ad7606_scan_direct(struct iio_dev *indio_dev, unsigned ch)
{
+ struct ad7606_state *st = iio_priv(indio_dev);
int ret;
st->done = false;
@@ -78,67 +77,44 @@
return ret;
}
-static ssize_t ad7606_scan(struct device *dev,
- struct device_attribute *attr,
- char *buf)
+static int ad7606_read_raw(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ int *val,
+ int *val2,
+ long m)
{
- struct iio_dev *dev_info = dev_get_drvdata(dev);
- struct ad7606_state *st = dev_info->dev_data;
- struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
int ret;
+ struct ad7606_state *st = iio_priv(indio_dev);
+ unsigned int scale_uv;
- mutex_lock(&dev_info->mlock);
- if (iio_ring_enabled(dev_info))
- ret = ad7606_scan_from_ring(st, this_attr->address);
- else
- ret = ad7606_scan_direct(st, this_attr->address);
- mutex_unlock(&dev_info->mlock);
+ switch (m) {
+ case 0:
+ mutex_lock(&indio_dev->mlock);
+ if (iio_ring_enabled(indio_dev))
+ ret = ad7606_scan_from_ring(indio_dev, chan->address);
+ else
+ ret = ad7606_scan_direct(indio_dev, chan->address);
+ mutex_unlock(&indio_dev->mlock);
- if (ret < 0)
- return ret;
-
- return sprintf(buf, "%d\n", (short) ret);
+ if (ret < 0)
+ return ret;
+ *val = (short) ret;
+ return IIO_VAL_INT;
+ case (1 << IIO_CHAN_INFO_SCALE_SHARED):
+ scale_uv = (st->range * 1000 * 2)
+ >> st->chip_info->channels[0].scan_type.realbits;
+ *val = scale_uv / 1000;
+ *val2 = (scale_uv % 1000) * 1000;
+ return IIO_VAL_INT_PLUS_MICRO;
+ }
+ return -EINVAL;
}
-static IIO_DEV_ATTR_IN_RAW(0, ad7606_scan, 0);
-static IIO_DEV_ATTR_IN_RAW(1, ad7606_scan, 1);
-static IIO_DEV_ATTR_IN_RAW(2, ad7606_scan, 2);
-static IIO_DEV_ATTR_IN_RAW(3, ad7606_scan, 3);
-static IIO_DEV_ATTR_IN_RAW(4, ad7606_scan, 4);
-static IIO_DEV_ATTR_IN_RAW(5, ad7606_scan, 5);
-static IIO_DEV_ATTR_IN_RAW(6, ad7606_scan, 6);
-static IIO_DEV_ATTR_IN_RAW(7, ad7606_scan, 7);
-
-static ssize_t ad7606_show_scale(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- /* Driver currently only support internal vref */
- struct iio_dev *dev_info = dev_get_drvdata(dev);
- struct ad7606_state *st = iio_dev_get_devdata(dev_info);
- unsigned int scale_uv = (st->range * 1000 * 2) >> st->chip_info->bits;
-
- return sprintf(buf, "%d.%03d\n", scale_uv / 1000, scale_uv % 1000);
-}
-static IIO_DEVICE_ATTR(in_scale, S_IRUGO, ad7606_show_scale, NULL, 0);
-
-static ssize_t ad7606_show_name(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- struct iio_dev *dev_info = dev_get_drvdata(dev);
- struct ad7606_state *st = iio_dev_get_devdata(dev_info);
-
- return sprintf(buf, "%s\n", st->chip_info->name);
-}
-
-static IIO_DEVICE_ATTR(name, S_IRUGO, ad7606_show_name, NULL, 0);
-
static ssize_t ad7606_show_range(struct device *dev,
struct device_attribute *attr, char *buf)
{
- struct iio_dev *dev_info = dev_get_drvdata(dev);
- struct ad7606_state *st = iio_dev_get_devdata(dev_info);
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ struct ad7606_state *st = iio_priv(indio_dev);
return sprintf(buf, "%u\n", st->range);
}
@@ -146,8 +122,8 @@
static ssize_t ad7606_store_range(struct device *dev,
struct device_attribute *attr, const char *buf, size_t count)
{
- struct iio_dev *dev_info = dev_get_drvdata(dev);
- struct ad7606_state *st = iio_dev_get_devdata(dev_info);
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ struct ad7606_state *st = iio_priv(indio_dev);
unsigned long lval;
if (strict_strtoul(buf, 10, &lval))
@@ -156,10 +132,10 @@
dev_err(dev, "range is not supported\n");
return -EINVAL;
}
- mutex_lock(&dev_info->mlock);
+ mutex_lock(&indio_dev->mlock);
gpio_set_value(st->pdata->gpio_range, lval == 10000);
st->range = lval;
- mutex_unlock(&dev_info->mlock);
+ mutex_unlock(&indio_dev->mlock);
return count;
}
@@ -171,8 +147,8 @@
static ssize_t ad7606_show_oversampling_ratio(struct device *dev,
struct device_attribute *attr, char *buf)
{
- struct iio_dev *dev_info = dev_get_drvdata(dev);
- struct ad7606_state *st = iio_dev_get_devdata(dev_info);
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ struct ad7606_state *st = iio_priv(indio_dev);
return sprintf(buf, "%u\n", st->oversampling);
}
@@ -192,8 +168,8 @@
static ssize_t ad7606_store_oversampling_ratio(struct device *dev,
struct device_attribute *attr, const char *buf, size_t count)
{
- struct iio_dev *dev_info = dev_get_drvdata(dev);
- struct ad7606_state *st = iio_dev_get_devdata(dev_info);
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ struct ad7606_state *st = iio_priv(indio_dev);
unsigned long lval;
int ret;
@@ -206,12 +182,12 @@
return ret;
}
- mutex_lock(&dev_info->mlock);
+ mutex_lock(&indio_dev->mlock);
gpio_set_value(st->pdata->gpio_os0, (ret >> 0) & 1);
gpio_set_value(st->pdata->gpio_os1, (ret >> 1) & 1);
gpio_set_value(st->pdata->gpio_os1, (ret >> 2) & 1);
st->oversampling = lval;
- mutex_unlock(&dev_info->mlock);
+ mutex_unlock(&indio_dev->mlock);
return count;
}
@@ -222,16 +198,6 @@
static IIO_CONST_ATTR(oversampling_ratio_available, "0 2 4 8 16 32 64");
static struct attribute *ad7606_attributes[] = {
- &iio_dev_attr_in0_raw.dev_attr.attr,
- &iio_dev_attr_in1_raw.dev_attr.attr,
- &iio_dev_attr_in2_raw.dev_attr.attr,
- &iio_dev_attr_in3_raw.dev_attr.attr,
- &iio_dev_attr_in4_raw.dev_attr.attr,
- &iio_dev_attr_in5_raw.dev_attr.attr,
- &iio_dev_attr_in6_raw.dev_attr.attr,
- &iio_dev_attr_in7_raw.dev_attr.attr,
- &iio_dev_attr_in_scale.dev_attr.attr,
- &iio_dev_attr_name.dev_attr.attr,
&iio_dev_attr_range.dev_attr.attr,
&iio_const_attr_range_available.dev_attr.attr,
&iio_dev_attr_oversampling_ratio.dev_attr.attr,
@@ -243,20 +209,12 @@
struct attribute *attr, int n)
{
struct device *dev = container_of(kobj, struct device, kobj);
- struct iio_dev *dev_info = dev_get_drvdata(dev);
- struct ad7606_state *st = iio_dev_get_devdata(dev_info);
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ struct ad7606_state *st = iio_priv(indio_dev);
mode_t mode = attr->mode;
- if (st->chip_info->num_channels <= 6 &&
- (attr == &iio_dev_attr_in7_raw.dev_attr.attr ||
- attr == &iio_dev_attr_in6_raw.dev_attr.attr))
- mode = 0;
- else if (st->chip_info->num_channels <= 4 &&
- (attr == &iio_dev_attr_in5_raw.dev_attr.attr ||
- attr == &iio_dev_attr_in4_raw.dev_attr.attr))
- mode = 0;
- else if (!st->have_os &&
+ if (!st->have_os &&
(attr == &iio_dev_attr_oversampling_ratio.dev_attr.attr ||
attr ==
&iio_const_attr_oversampling_ratio_available.dev_attr.attr))
@@ -274,29 +232,92 @@
.is_visible = ad7606_attr_is_visible,
};
+static struct iio_chan_spec ad7606_8_channels[] = {
+ IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 0, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 0, 0, IIO_ST('s', 16, 16, 0), 0),
+ IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 1, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 1, 1, IIO_ST('s', 16, 16, 0), 0),
+ IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 2, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 2, 2, IIO_ST('s', 16, 16, 0), 0),
+ IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 3, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 3, 3, IIO_ST('s', 16, 16, 0), 0),
+ IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 4, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 4, 4, IIO_ST('s', 16, 16, 0), 0),
+ IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 5, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 5, 5, IIO_ST('s', 16, 16, 0), 0),
+ IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 6, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 6, 6, IIO_ST('s', 16, 16, 0), 0),
+ IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 7, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 7, 7, IIO_ST('s', 16, 16, 0), 0),
+ IIO_CHAN_SOFT_TIMESTAMP(8),
+};
+
+static struct iio_chan_spec ad7606_6_channels[] = {
+ IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 0, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 0, 0, IIO_ST('s', 16, 16, 0), 0),
+ IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 1, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 1, 1, IIO_ST('s', 16, 16, 0), 0),
+ IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 2, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 2, 2, IIO_ST('s', 16, 16, 0), 0),
+ IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 3, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 3, 3, IIO_ST('s', 16, 16, 0), 0),
+ IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 4, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 4, 4, IIO_ST('s', 16, 16, 0), 0),
+ IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 5, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 5, 5, IIO_ST('s', 16, 16, 0), 0),
+ IIO_CHAN_SOFT_TIMESTAMP(6),
+};
+
+static struct iio_chan_spec ad7606_4_channels[] = {
+ IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 0, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 0, 0, IIO_ST('s', 16, 16, 0), 0),
+ IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 1, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 1, 1, IIO_ST('s', 16, 16, 0), 0),
+ IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 2, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 2, 2, IIO_ST('s', 16, 16, 0), 0),
+ IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 3, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 3, 3, IIO_ST('s', 16, 16, 0), 0),
+ IIO_CHAN_SOFT_TIMESTAMP(4),
+};
+
static const struct ad7606_chip_info ad7606_chip_info_tbl[] = {
/*
* More devices added in future
*/
[ID_AD7606_8] = {
.name = "ad7606",
- .bits = 16,
- .sign = IIO_SCAN_EL_TYPE_SIGNED,
.int_vref_mv = 2500,
+ .channels = ad7606_8_channels,
.num_channels = 8,
},
[ID_AD7606_6] = {
.name = "ad7606-6",
- .bits = 16,
- .sign = IIO_SCAN_EL_TYPE_SIGNED,
.int_vref_mv = 2500,
+ .channels = ad7606_6_channels,
.num_channels = 6,
},
[ID_AD7606_4] = {
.name = "ad7606-4",
- .bits = 16,
- .sign = IIO_SCAN_EL_TYPE_SIGNED,
.int_vref_mv = 2500,
+ .channels = ad7606_4_channels,
.num_channels = 4,
},
};
@@ -343,8 +364,8 @@
st->have_reset = true;
ret = gpio_request_one(st->pdata->gpio_range, GPIOF_DIR_OUT |
- ((st->range == 10000) ? GPIOF_INIT_HIGH :
- GPIOF_INIT_LOW), "AD7606_RANGE");
+ ((st->range == 10000) ? GPIOF_INIT_HIGH :
+ GPIOF_INIT_LOW), "AD7606_RANGE");
if (!ret)
st->have_range = true;
@@ -391,9 +412,10 @@
*/
static irqreturn_t ad7606_interrupt(int irq, void *dev_id)
{
- struct ad7606_state *st = dev_id;
+ struct iio_dev *indio_dev = dev_id;
+ struct ad7606_state *st = iio_priv(indio_dev);
- if (iio_ring_enabled(st->indio_dev)) {
+ if (iio_ring_enabled(indio_dev)) {
if (!work_pending(&st->poll_work))
schedule_work(&st->poll_work);
} else {
@@ -404,21 +426,29 @@
return IRQ_HANDLED;
};
-struct ad7606_state *ad7606_probe(struct device *dev, int irq,
+static const struct iio_info ad7606_info = {
+ .driver_module = THIS_MODULE,
+ .read_raw = &ad7606_read_raw,
+ .attrs = &ad7606_attribute_group,
+};
+
+struct iio_dev *ad7606_probe(struct device *dev, int irq,
void __iomem *base_address,
unsigned id,
const struct ad7606_bus_ops *bops)
{
struct ad7606_platform_data *pdata = dev->platform_data;
struct ad7606_state *st;
- int ret;
+ int ret, regdone = 0;
+ struct iio_dev *indio_dev = iio_allocate_device(sizeof(*st));
- st = kzalloc(sizeof(*st), GFP_KERNEL);
- if (st == NULL) {
+ if (indio_dev == NULL) {
ret = -ENOMEM;
goto error_ret;
}
+ st = iio_priv(indio_dev);
+
st->dev = dev;
st->id = id;
st->irq = irq;
@@ -445,93 +475,91 @@
st->pdata = pdata;
st->chip_info = &ad7606_chip_info_tbl[id];
- atomic_set(&st->protect_ring, 0);
-
- st->indio_dev = iio_allocate_device();
- if (st->indio_dev == NULL) {
- ret = -ENOMEM;
- goto error_disable_reg;
- }
-
- st->indio_dev->dev.parent = dev;
- st->indio_dev->attrs = &ad7606_attribute_group;
- st->indio_dev->dev_data = (void *)(st);
- st->indio_dev->driver_module = THIS_MODULE;
- st->indio_dev->modes = INDIO_DIRECT_MODE;
+ indio_dev->dev.parent = dev;
+ indio_dev->info = &ad7606_info;
+ indio_dev->modes = INDIO_DIRECT_MODE;
+ indio_dev->name = st->chip_info->name;
+ indio_dev->channels = st->chip_info->channels;
+ indio_dev->num_channels = st->chip_info->num_channels;
init_waitqueue_head(&st->wq_data_avail);
ret = ad7606_request_gpios(st);
if (ret)
- goto error_free_device;
+ goto error_disable_reg;
ret = ad7606_reset(st);
if (ret)
dev_warn(st->dev, "failed to RESET: no RESET GPIO specified\n");
ret = request_irq(st->irq, ad7606_interrupt,
- IRQF_TRIGGER_FALLING, st->chip_info->name, st);
+ IRQF_TRIGGER_FALLING, st->chip_info->name, indio_dev);
if (ret)
goto error_free_gpios;
- ret = ad7606_register_ring_funcs_and_init(st->indio_dev);
+ ret = ad7606_register_ring_funcs_and_init(indio_dev);
if (ret)
goto error_free_irq;
- ret = iio_device_register(st->indio_dev);
+ ret = iio_device_register(indio_dev);
if (ret)
goto error_free_irq;
+ regdone = 1;
- ret = iio_ring_buffer_register(st->indio_dev->ring, 0);
+ ret = iio_ring_buffer_register_ex(indio_dev->ring, 0,
+ indio_dev->channels,
+ indio_dev->num_channels);
if (ret)
goto error_cleanup_ring;
- return st;
+ return indio_dev;
error_cleanup_ring:
- ad7606_ring_cleanup(st->indio_dev);
- iio_device_unregister(st->indio_dev);
+ ad7606_ring_cleanup(indio_dev);
error_free_irq:
- free_irq(st->irq, st);
+ free_irq(st->irq, indio_dev);
error_free_gpios:
ad7606_free_gpios(st);
-error_free_device:
- iio_free_device(st->indio_dev);
-
error_disable_reg:
if (!IS_ERR(st->reg))
regulator_disable(st->reg);
error_put_reg:
if (!IS_ERR(st->reg))
regulator_put(st->reg);
- kfree(st);
+ if (regdone)
+ iio_device_unregister(indio_dev);
+ else
+ iio_free_device(indio_dev);
error_ret:
return ERR_PTR(ret);
}
-int ad7606_remove(struct ad7606_state *st)
+int ad7606_remove(struct iio_dev *indio_dev)
{
- struct iio_dev *indio_dev = st->indio_dev;
+ struct ad7606_state *st = iio_priv(indio_dev);
+
iio_ring_buffer_unregister(indio_dev->ring);
ad7606_ring_cleanup(indio_dev);
- iio_device_unregister(indio_dev);
- free_irq(st->irq, st);
+
+ free_irq(st->irq, indio_dev);
if (!IS_ERR(st->reg)) {
regulator_disable(st->reg);
regulator_put(st->reg);
}
ad7606_free_gpios(st);
+ iio_device_unregister(indio_dev);
- kfree(st);
return 0;
}
-void ad7606_suspend(struct ad7606_state *st)
+void ad7606_suspend(struct iio_dev *indio_dev)
{
+ struct ad7606_state *st = iio_priv(indio_dev);
+
if (st->have_stby) {
if (st->have_range)
gpio_set_value(st->pdata->gpio_range, 1);
@@ -539,8 +567,10 @@
}
}
-void ad7606_resume(struct ad7606_state *st)
+void ad7606_resume(struct iio_dev *indio_dev)
{
+ struct ad7606_state *st = iio_priv(indio_dev);
+
if (st->have_stby) {
if (st->have_range)
gpio_set_value(st->pdata->gpio_range,
diff --git a/drivers/staging/iio/adc/ad7606_par.c b/drivers/staging/iio/adc/ad7606_par.c
index 43a554c..d21218d 100644
--- a/drivers/staging/iio/adc/ad7606_par.c
+++ b/drivers/staging/iio/adc/ad7606_par.c
@@ -12,13 +12,15 @@
#include <linux/err.h>
#include <linux/io.h>
+#include "../iio.h"
#include "ad7606.h"
static int ad7606_par16_read_block(struct device *dev,
int count, void *buf)
{
struct platform_device *pdev = to_platform_device(dev);
- struct ad7606_state *st = platform_get_drvdata(pdev);
+ struct iio_dev *indio_dev = platform_get_drvdata(pdev);
+ struct ad7606_state *st = iio_priv(indio_dev);
insw((unsigned long) st->base_address, buf, count);
@@ -33,7 +35,8 @@
int count, void *buf)
{
struct platform_device *pdev = to_platform_device(dev);
- struct ad7606_state *st = platform_get_drvdata(pdev);
+ struct iio_dev *indio_dev = platform_get_drvdata(pdev);
+ struct ad7606_state *st = iio_priv(indio_dev);
insb((unsigned long) st->base_address, buf, count * 2);
@@ -47,7 +50,7 @@
static int __devinit ad7606_par_probe(struct platform_device *pdev)
{
struct resource *res;
- struct ad7606_state *st;
+ struct iio_dev *indio_dev;
void __iomem *addr;
resource_size_t remap_size;
int ret, irq;
@@ -75,17 +78,17 @@
goto out1;
}
- st = ad7606_probe(&pdev->dev, irq, addr,
+ indio_dev = ad7606_probe(&pdev->dev, irq, addr,
platform_get_device_id(pdev)->driver_data,
remap_size > 1 ? &ad7606_par16_bops :
&ad7606_par8_bops);
- if (IS_ERR(st)) {
- ret = PTR_ERR(st);
+ if (IS_ERR(indio_dev)) {
+ ret = PTR_ERR(indio_dev);
goto out2;
}
- platform_set_drvdata(pdev, st);
+ platform_set_drvdata(pdev, indio_dev);
return 0;
@@ -99,10 +102,11 @@
static int __devexit ad7606_par_remove(struct platform_device *pdev)
{
- struct ad7606_state *st = platform_get_drvdata(pdev);
+ struct iio_dev *indio_dev = platform_get_drvdata(pdev);
struct resource *res;
+ struct ad7606_state *st = iio_priv(indio_dev);
- ad7606_remove(st);
+ ad7606_remove(indio_dev);
iounmap(st->base_address);
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -116,18 +120,18 @@
#ifdef CONFIG_PM
static int ad7606_par_suspend(struct device *dev)
{
- struct ad7606_state *st = dev_get_drvdata(dev);
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
- ad7606_suspend(st);
+ ad7606_suspend(indio_dev);
return 0;
}
static int ad7606_par_resume(struct device *dev)
{
- struct ad7606_state *st = dev_get_drvdata(dev);
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
- ad7606_resume(st);
+ ad7606_resume(indio_dev);
return 0;
}
diff --git a/drivers/staging/iio/adc/ad7606_ring.c b/drivers/staging/iio/adc/ad7606_ring.c
index b32cb0d..a199bf4 100644
--- a/drivers/staging/iio/adc/ad7606_ring.c
+++ b/drivers/staging/iio/adc/ad7606_ring.c
@@ -7,7 +7,6 @@
#include <linux/interrupt.h>
#include <linux/gpio.h>
-#include <linux/workqueue.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/slab.h>
@@ -21,99 +20,19 @@
#include "ad7606.h"
-static IIO_SCAN_EL_C(in0, 0, 0, NULL);
-static IIO_SCAN_EL_C(in1, 1, 0, NULL);
-static IIO_SCAN_EL_C(in2, 2, 0, NULL);
-static IIO_SCAN_EL_C(in3, 3, 0, NULL);
-static IIO_SCAN_EL_C(in4, 4, 0, NULL);
-static IIO_SCAN_EL_C(in5, 5, 0, NULL);
-static IIO_SCAN_EL_C(in6, 6, 0, NULL);
-static IIO_SCAN_EL_C(in7, 7, 0, NULL);
-
-static IIO_SCAN_EL_TIMESTAMP(8);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(timestamp, s, 64, 64);
-
-static ssize_t ad7606_show_type(struct device *dev,
- struct device_attribute *attr,
- char *buf)
+int ad7606_scan_from_ring(struct iio_dev *indio_dev, unsigned ch)
{
- struct iio_ring_buffer *ring = dev_get_drvdata(dev);
- struct iio_dev *indio_dev = ring->indio_dev;
- struct ad7606_state *st = indio_dev->dev_data;
-
- return sprintf(buf, "%c%d/%d\n", st->chip_info->sign,
- st->chip_info->bits, st->chip_info->bits);
-}
-static IIO_DEVICE_ATTR(in_type, S_IRUGO, ad7606_show_type, NULL, 0);
-
-static struct attribute *ad7606_scan_el_attrs[] = {
- &iio_scan_el_in0.dev_attr.attr,
- &iio_const_attr_in0_index.dev_attr.attr,
- &iio_scan_el_in1.dev_attr.attr,
- &iio_const_attr_in1_index.dev_attr.attr,
- &iio_scan_el_in2.dev_attr.attr,
- &iio_const_attr_in2_index.dev_attr.attr,
- &iio_scan_el_in3.dev_attr.attr,
- &iio_const_attr_in3_index.dev_attr.attr,
- &iio_scan_el_in4.dev_attr.attr,
- &iio_const_attr_in4_index.dev_attr.attr,
- &iio_scan_el_in5.dev_attr.attr,
- &iio_const_attr_in5_index.dev_attr.attr,
- &iio_scan_el_in6.dev_attr.attr,
- &iio_const_attr_in6_index.dev_attr.attr,
- &iio_scan_el_in7.dev_attr.attr,
- &iio_const_attr_in7_index.dev_attr.attr,
- &iio_const_attr_timestamp_index.dev_attr.attr,
- &iio_scan_el_timestamp.dev_attr.attr,
- &iio_const_attr_timestamp_type.dev_attr.attr,
- &iio_dev_attr_in_type.dev_attr.attr,
- NULL,
-};
-
-static mode_t ad7606_scan_el_attr_is_visible(struct kobject *kobj,
- struct attribute *attr, int n)
-{
- struct device *dev = container_of(kobj, struct device, kobj);
- struct iio_ring_buffer *ring = dev_get_drvdata(dev);
- struct iio_dev *indio_dev = ring->indio_dev;
- struct ad7606_state *st = indio_dev->dev_data;
-
- mode_t mode = attr->mode;
-
- if (st->chip_info->num_channels <= 6 &&
- (attr == &iio_scan_el_in7.dev_attr.attr ||
- attr == &iio_const_attr_in7_index.dev_attr.attr ||
- attr == &iio_scan_el_in6.dev_attr.attr ||
- attr == &iio_const_attr_in6_index.dev_attr.attr))
- mode = 0;
- else if (st->chip_info->num_channels <= 4 &&
- (attr == &iio_scan_el_in5.dev_attr.attr ||
- attr == &iio_const_attr_in5_index.dev_attr.attr ||
- attr == &iio_scan_el_in4.dev_attr.attr ||
- attr == &iio_const_attr_in4_index.dev_attr.attr))
- mode = 0;
-
- return mode;
-}
-
-static struct attribute_group ad7606_scan_el_group = {
- .name = "scan_elements",
- .attrs = ad7606_scan_el_attrs,
- .is_visible = ad7606_scan_el_attr_is_visible,
-};
-
-int ad7606_scan_from_ring(struct ad7606_state *st, unsigned ch)
-{
- struct iio_ring_buffer *ring = st->indio_dev->ring;
+ struct iio_ring_buffer *ring = indio_dev->ring;
int ret;
u16 *ring_data;
- ring_data = kmalloc(ring->access.get_bytes_per_datum(ring), GFP_KERNEL);
+ ring_data = kmalloc(ring->access->get_bytes_per_datum(ring),
+ GFP_KERNEL);
if (ring_data == NULL) {
ret = -ENOMEM;
goto error_ret;
}
- ret = ring->access.read_last(ring, (u8 *) ring_data);
+ ret = ring->access->read_last(ring, (u8 *) ring_data);
if (ret)
goto error_free_ring_data;
@@ -134,12 +53,12 @@
**/
static int ad7606_ring_preenable(struct iio_dev *indio_dev)
{
- struct ad7606_state *st = indio_dev->dev_data;
+ struct ad7606_state *st = iio_priv(indio_dev);
struct iio_ring_buffer *ring = indio_dev->ring;
size_t d_size;
d_size = st->chip_info->num_channels *
- st->chip_info->bits / 8;
+ st->chip_info->channels[0].scan_type.storagebits / 8;
if (ring->scan_timestamp) {
d_size += sizeof(s64);
@@ -148,8 +67,8 @@
d_size += sizeof(s64) - (d_size % sizeof(s64));
}
- if (ring->access.set_bytes_per_datum)
- ring->access.set_bytes_per_datum(ring, d_size);
+ if (ring->access->set_bytes_per_datum)
+ ring->access->set_bytes_per_datum(ring, d_size);
st->d_size = d_size;
@@ -157,16 +76,20 @@
}
/**
- * ad7606_poll_func_th() th of trigger launched polling to ring buffer
+ * ad7606_trigger_handler_th() th/bh of trigger launched polling to ring buffer
*
**/
-static void ad7606_poll_func_th(struct iio_dev *indio_dev, s64 time)
+static irqreturn_t ad7606_trigger_handler_th_bh(int irq, void *p)
{
- struct ad7606_state *st = indio_dev->dev_data;
+ struct iio_poll_func *pf = p;
+ struct iio_dev *indio_dev = pf->private_data;
+ struct ad7606_state *st = iio_priv(indio_dev);
+
gpio_set_value(st->pdata->gpio_convst, 1);
- return;
+ return IRQ_HANDLED;
}
+
/**
* ad7606_poll_bh_to_ring() bh of trigger launched polling to ring buffer
* @work_s: the work struct through which this was scheduled
@@ -180,17 +103,12 @@
{
struct ad7606_state *st = container_of(work_s, struct ad7606_state,
poll_work);
- struct iio_dev *indio_dev = st->indio_dev;
- struct iio_sw_ring_buffer *sw_ring = iio_to_sw_ring(indio_dev->ring);
+ struct iio_dev *indio_dev = iio_priv_to_dev(st);
struct iio_ring_buffer *ring = indio_dev->ring;
s64 time_ns;
__u8 *buf;
int ret;
- /* Ensure only one copy of this function running at a time */
- if (atomic_inc_return(&st->protect_ring) > 1)
- return;
-
buf = kzalloc(st->d_size, GFP_KERNEL);
if (buf == NULL)
return;
@@ -225,16 +143,22 @@
memcpy(buf + st->d_size - sizeof(s64),
&time_ns, sizeof(time_ns));
- ring->access.store_to(&sw_ring->buf, buf, time_ns);
+ ring->access->store_to(indio_dev->ring, buf, time_ns);
done:
gpio_set_value(st->pdata->gpio_convst, 0);
+ iio_trigger_notify_done(indio_dev->trig);
kfree(buf);
- atomic_dec(&st->protect_ring);
}
+static const struct iio_ring_setup_ops ad7606_ring_setup_ops = {
+ .preenable = &ad7606_ring_preenable,
+ .postenable = &iio_triggered_ring_postenable,
+ .predisable = &iio_triggered_ring_predisable,
+};
+
int ad7606_register_ring_funcs_and_init(struct iio_dev *indio_dev)
{
- struct ad7606_state *st = indio_dev->dev_data;
+ struct ad7606_state *st = iio_priv(indio_dev);
int ret;
indio_dev->ring = iio_sw_rb_allocate(indio_dev);
@@ -244,17 +168,22 @@
}
/* Effectively select the ring buffer implementation */
- iio_ring_sw_register_funcs(&indio_dev->ring->access);
- ret = iio_alloc_pollfunc(indio_dev, NULL, &ad7606_poll_func_th);
- if (ret)
+ indio_dev->ring->access = &ring_sw_access_funcs;
+ indio_dev->pollfunc = iio_alloc_pollfunc(&ad7606_trigger_handler_th_bh,
+ &ad7606_trigger_handler_th_bh,
+ 0,
+ indio_dev,
+ "%s_consumer%d",
+ indio_dev->name,
+ indio_dev->id);
+ if (indio_dev->pollfunc == NULL) {
+ ret = -ENOMEM;
goto error_deallocate_sw_rb;
+ }
/* Ring buffer functions - here trigger setup related */
- indio_dev->ring->preenable = &ad7606_ring_preenable;
- indio_dev->ring->postenable = &iio_triggered_ring_postenable;
- indio_dev->ring->predisable = &iio_triggered_ring_predisable;
- indio_dev->ring->scan_el_attrs = &ad7606_scan_el_group;
+ indio_dev->ring->setup_ops = &ad7606_ring_setup_ops;
indio_dev->ring->scan_timestamp = true ;
INIT_WORK(&st->poll_work, &ad7606_poll_bh_to_ring);
@@ -262,6 +191,7 @@
/* Flag that polled ring buffering is possible */
indio_dev->modes |= INDIO_RING_TRIGGERED;
return 0;
+
error_deallocate_sw_rb:
iio_sw_rb_free(indio_dev->ring);
error_ret:
@@ -275,6 +205,6 @@
iio_trigger_dettach_poll_func(indio_dev->trig,
indio_dev->pollfunc);
}
- kfree(indio_dev->pollfunc);
+ iio_dealloc_pollfunc(indio_dev->pollfunc);
iio_sw_rb_free(indio_dev->ring);
}
diff --git a/drivers/staging/iio/adc/ad7606_spi.c b/drivers/staging/iio/adc/ad7606_spi.c
index d738491..0769c80 100644
--- a/drivers/staging/iio/adc/ad7606_spi.c
+++ b/drivers/staging/iio/adc/ad7606_spi.c
@@ -10,6 +10,8 @@
#include <linux/spi/spi.h>
#include <linux/types.h>
#include <linux/err.h>
+
+#include "../iio.h"
#include "ad7606.h"
#define MAX_SPI_FREQ_HZ 23500000 /* VDRIVE above 4.75 V */
@@ -39,42 +41,42 @@
static int __devinit ad7606_spi_probe(struct spi_device *spi)
{
- struct ad7606_state *st;
+ struct iio_dev *indio_dev;
- st = ad7606_probe(&spi->dev, spi->irq, NULL,
+ indio_dev = ad7606_probe(&spi->dev, spi->irq, NULL,
spi_get_device_id(spi)->driver_data,
&ad7606_spi_bops);
- if (IS_ERR(st))
- return PTR_ERR(st);
+ if (IS_ERR(indio_dev))
+ return PTR_ERR(indio_dev);
- spi_set_drvdata(spi, st);
+ spi_set_drvdata(spi, indio_dev);
return 0;
}
static int __devexit ad7606_spi_remove(struct spi_device *spi)
{
- struct ad7606_state *st = dev_get_drvdata(&spi->dev);
+ struct iio_dev *indio_dev = dev_get_drvdata(&spi->dev);
- return ad7606_remove(st);
+ return ad7606_remove(indio_dev);
}
#ifdef CONFIG_PM
static int ad7606_spi_suspend(struct device *dev)
{
- struct ad7606_state *st = dev_get_drvdata(dev);
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
- ad7606_suspend(st);
+ ad7606_suspend(indio_dev);
return 0;
}
static int ad7606_spi_resume(struct device *dev)
{
- struct ad7606_state *st = dev_get_drvdata(dev);
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
- ad7606_resume(st);
+ ad7606_resume(indio_dev);
return 0;
}
diff --git a/drivers/staging/iio/adc/ad7745.c b/drivers/staging/iio/adc/ad7745.c
index ab7ef84..1944223 100644
--- a/drivers/staging/iio/adc/ad7745.c
+++ b/drivers/staging/iio/adc/ad7745.c
@@ -8,14 +8,12 @@
#include <linux/interrupt.h>
#include <linux/gpio.h>
-#include <linux/workqueue.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
#include <linux/list.h>
#include <linux/i2c.h>
-#include <linux/rtc.h>
#include "../iio.h"
#include "../sysfs.h"
@@ -55,12 +53,9 @@
*/
struct ad774x_chip_info {
- const char *name;
struct i2c_client *client;
struct iio_dev *indio_dev;
- struct work_struct thresh_work;
bool inter;
- s64 last_timestamp;
u16 cap_offs; /* Capacitive offset */
u16 cap_gain; /* Capacitive gain calibration */
u16 volt_gain; /* Voltage gain calibration */
@@ -76,7 +71,8 @@
u8 reg_cfg;
};
-struct ad774x_conversion_mode ad774x_conv_mode_table[AD774X_MAX_CONV_MODE] = {
+static struct ad774x_conversion_mode
+ad774x_conv_mode_table[AD774X_MAX_CONV_MODE] = {
{ "idle", 0 },
{ "continuous-conversion", 1 },
{ "single-conversion", 2 },
@@ -502,17 +498,6 @@
ad774x_show_cap_gain,
ad774x_store_cap_gain);
-static ssize_t ad774x_show_name(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- struct iio_dev *dev_info = dev_get_drvdata(dev);
- struct ad774x_chip_info *chip = dev_info->dev_data;
- return sprintf(buf, "%s\n", chip->name);
-}
-
-static IIO_DEVICE_ATTR(name, S_IRUGO, ad774x_show_name, NULL, 0);
-
static struct attribute *ad774x_attributes[] = {
&iio_dev_attr_available_conversion_modes.dev_attr.attr,
&iio_dev_attr_conversion_mode.dev_attr.attr,
@@ -526,7 +511,6 @@
&iio_dev_attr_cap0_raw.dev_attr.attr,
&iio_dev_attr_capdac0_raw.dev_attr.attr,
&iio_dev_attr_capdac1_raw.dev_attr.attr,
- &iio_dev_attr_name.dev_attr.attr,
NULL,
};
@@ -538,8 +522,8 @@
* data ready events
*/
-#define IIO_EVENT_CODE_CAP_RDY IIO_BUFFER_EVENT_CODE(0)
-#define IIO_EVENT_CODE_VT_RDY IIO_BUFFER_EVENT_CODE(1)
+#define IIO_EVENT_CODE_CAP_RDY 0
+#define IIO_EVENT_CODE_VT_RDY 1
#define IIO_EVENT_ATTR_CAP_RDY_SH(_evlist, _show, _store, _mask) \
IIO_EVENT_ATTR_SH(cap_rdy, _evlist, _show, _store, _mask)
@@ -547,67 +531,33 @@
#define IIO_EVENT_ATTR_VT_RDY_SH(_evlist, _show, _store, _mask) \
IIO_EVENT_ATTR_SH(vt_rdy, _evlist, _show, _store, _mask)
-static void ad774x_interrupt_handler_bh(struct work_struct *work_s)
+static irqreturn_t ad774x_event_handler(int irq, void *private)
{
- struct ad774x_chip_info *chip =
- container_of(work_s, struct ad774x_chip_info, thresh_work);
+ struct iio_dev *indio_dev = private;
+ struct ad774x_chip_info *chip = iio_dev_get_devdata(indio_dev);
u8 int_status;
- enable_irq(chip->client->irq);
-
ad774x_i2c_read(chip, AD774X_STATUS, &int_status, 1);
if (int_status & AD774X_STATUS_RDYCAP)
- iio_push_event(chip->indio_dev, 0,
- IIO_EVENT_CODE_CAP_RDY,
- chip->last_timestamp);
+ iio_push_event(indio_dev, 0,
+ IIO_EVENT_CODE_CAP_RDY,
+ iio_get_time_ns());
if (int_status & AD774X_STATUS_RDYVT)
- iio_push_event(chip->indio_dev, 0,
- IIO_EVENT_CODE_VT_RDY,
- chip->last_timestamp);
+ iio_push_event(indio_dev, 0,
+ IIO_EVENT_CODE_VT_RDY,
+ iio_get_time_ns());
+
+ return IRQ_HANDLED;
}
-static int ad774x_interrupt_handler_th(struct iio_dev *dev_info,
- int index,
- s64 timestamp,
- int no_test)
-{
- struct ad774x_chip_info *chip = dev_info->dev_data;
-
- chip->last_timestamp = timestamp;
- schedule_work(&chip->thresh_work);
-
- return 0;
-}
-
-IIO_EVENT_SH(data_rdy, &ad774x_interrupt_handler_th);
-
-static ssize_t ad774x_query_out_mode(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- /*
- * AD774X provides one /RDY pin, which can be used as interrupt
- * but the pin is not configurable
- */
- return sprintf(buf, "1\n");
-}
-
-static ssize_t ad774x_set_out_mode(struct device *dev,
- struct device_attribute *attr,
- const char *buf,
- size_t len)
-{
- return len;
-}
-
-IIO_EVENT_ATTR_CAP_RDY_SH(iio_event_data_rdy, ad774x_query_out_mode, ad774x_set_out_mode, 0);
-IIO_EVENT_ATTR_VT_RDY_SH(iio_event_data_rdy, ad774x_query_out_mode, ad774x_set_out_mode, 0);
+static IIO_CONST_ATTR(cap_rdy_en, "1");
+static IIO_CONST_ATTR(vt_rdy_en, "1");
static struct attribute *ad774x_event_attributes[] = {
- &iio_event_attr_cap_rdy.dev_attr.attr,
- &iio_event_attr_vt_rdy.dev_attr.attr,
+ &iio_const_attr_cap_rdy_en.dev_attr.attr,
+ &iio_const_attr_vt_rdy_en.dev_attr.attr,
NULL,
};
@@ -615,6 +565,12 @@
.attrs = ad774x_event_attributes,
};
+static const struct iio_info ad774x_info = {
+ .attrs = &ad774x_event_attribute_group,
+ .event_attrs = &ad774x_event_attribute_group,
+ .num_interrupt_lines = 1,
+ .driver_module = THIS_MODULE,
+};
/*
* device probe and remove
*/
@@ -633,21 +589,18 @@
i2c_set_clientdata(client, chip);
chip->client = client;
- chip->name = id->name;
- chip->indio_dev = iio_allocate_device();
+ chip->indio_dev = iio_allocate_device(0);
if (chip->indio_dev == NULL) {
ret = -ENOMEM;
goto error_free_chip;
}
/* Establish that the iio_dev is a child of the i2c device */
+ chip->indio_dev->name = id->name;
chip->indio_dev->dev.parent = &client->dev;
- chip->indio_dev->attrs = &ad774x_attribute_group;
- chip->indio_dev->event_attrs = &ad774x_event_attribute_group;
+ chip->indio_dev->info = &ad774x_info;
chip->indio_dev->dev_data = (void *)(chip);
- chip->indio_dev->driver_module = THIS_MODULE;
- chip->indio_dev->num_interrupt_lines = 1;
chip->indio_dev->modes = INDIO_DIRECT_MODE;
ret = iio_device_register(chip->indio_dev);
@@ -656,18 +609,14 @@
regdone = 1;
if (client->irq) {
- ret = iio_register_interrupt_line(client->irq,
- chip->indio_dev,
- 0,
- IRQF_TRIGGER_FALLING,
- "ad774x");
+ ret = request_threaded_irq(client->irq,
+ NULL,
+ &ad774x_event_handler,
+ IRQF_TRIGGER_FALLING,
+ "ad774x",
+ chip->indio_dev);
if (ret)
goto error_free_dev;
-
- iio_add_event_to_list(iio_event_attr_cap_rdy.listel,
- &chip->indio_dev->interrupts[0]->ev_list);
-
- INIT_WORK(&chip->thresh_work, ad774x_interrupt_handler_bh);
}
dev_err(&client->dev, "%s capacitive sensor registered, irq: %d\n", id->name, client->irq);
@@ -676,7 +625,7 @@
error_free_dev:
if (regdone)
- iio_device_unregister(chip->indio_dev);
+ free_irq(client->irq, chip->indio_dev);
else
iio_free_device(chip->indio_dev);
error_free_chip:
@@ -691,7 +640,7 @@
struct iio_dev *indio_dev = chip->indio_dev;
if (client->irq)
- iio_unregister_interrupt_line(indio_dev, 0);
+ free_irq(client->irq, indio_dev);
iio_device_unregister(indio_dev);
kfree(chip);
diff --git a/drivers/staging/iio/adc/ad7780.c b/drivers/staging/iio/adc/ad7780.c
new file mode 100644
index 0000000..e0c7b6c
--- /dev/null
+++ b/drivers/staging/iio/adc/ad7780.c
@@ -0,0 +1,301 @@
+/*
+ * AD7780/AD7781 SPI ADC driver
+ *
+ * Copyright 2011 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2.
+ */
+
+#include <linux/interrupt.h>
+#include <linux/device.h>
+#include <linux/kernel.h>
+#include <linux/slab.h>
+#include <linux/sysfs.h>
+#include <linux/spi/spi.h>
+#include <linux/regulator/consumer.h>
+#include <linux/err.h>
+#include <linux/sched.h>
+#include <linux/gpio.h>
+
+#include "../iio.h"
+#include "../sysfs.h"
+#include "../ring_generic.h"
+#include "adc.h"
+
+#include "ad7780.h"
+
+#define AD7780_RDY (1 << 7)
+#define AD7780_FILTER (1 << 6)
+#define AD7780_ERR (1 << 5)
+#define AD7780_ID1 (1 << 4)
+#define AD7780_ID0 (1 << 3)
+#define AD7780_GAIN (1 << 2)
+#define AD7780_PAT1 (1 << 1)
+#define AD7780_PAT0 (1 << 0)
+
+struct ad7780_chip_info {
+ struct iio_chan_spec channel;
+};
+
+struct ad7780_state {
+ struct spi_device *spi;
+ const struct ad7780_chip_info *chip_info;
+ struct regulator *reg;
+ struct ad7780_platform_data *pdata;
+ wait_queue_head_t wq_data_avail;
+ bool done;
+ u16 int_vref_mv;
+ struct spi_transfer xfer;
+ struct spi_message msg;
+ /*
+ * DMA (thus cache coherency maintenance) requires the
+ * transfer buffers to live in their own cache lines.
+ */
+ unsigned int data ____cacheline_aligned;
+};
+
+enum ad7780_supported_device_ids {
+ ID_AD7780,
+ ID_AD7781,
+};
+
+static int ad7780_read(struct ad7780_state *st, int *val)
+{
+ int ret;
+
+ spi_bus_lock(st->spi->master);
+
+ enable_irq(st->spi->irq);
+ st->done = false;
+ gpio_set_value(st->pdata->gpio_pdrst, 1);
+
+ ret = wait_event_interruptible(st->wq_data_avail, st->done);
+ disable_irq_nosync(st->spi->irq);
+ if (ret)
+ goto out;
+
+ ret = spi_sync_locked(st->spi, &st->msg);
+ *val = be32_to_cpu(st->data);
+out:
+ gpio_set_value(st->pdata->gpio_pdrst, 0);
+ spi_bus_unlock(st->spi->master);
+
+ return ret;
+}
+
+static int ad7780_read_raw(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ int *val,
+ int *val2,
+ long m)
+{
+ struct ad7780_state *st = iio_priv(indio_dev);
+ struct iio_chan_spec channel = st->chip_info->channel;
+ int ret, smpl = 0;
+ unsigned long scale_uv;
+
+ switch (m) {
+ case 0:
+ mutex_lock(&indio_dev->mlock);
+ ret = ad7780_read(st, &smpl);
+ mutex_unlock(&indio_dev->mlock);
+
+ if (ret < 0)
+ return ret;
+
+ if ((smpl & AD7780_ERR) ||
+ !((smpl & AD7780_PAT0) && !(smpl & AD7780_PAT1)))
+ return -EIO;
+
+ *val = (smpl >> channel.scan_type.shift) &
+ ((1 << (channel.scan_type.realbits)) - 1);
+ *val -= (1 << (channel.scan_type.realbits - 1));
+
+ if (!(smpl & AD7780_GAIN))
+ *val *= 128;
+
+ return IIO_VAL_INT;
+ case (1 << IIO_CHAN_INFO_SCALE_SHARED):
+ scale_uv = (st->int_vref_mv * 100000)
+ >> (channel.scan_type.realbits - 1);
+ *val = scale_uv / 100000;
+ *val2 = (scale_uv % 100000) * 10;
+ return IIO_VAL_INT_PLUS_MICRO;
+ }
+ return -EINVAL;
+}
+
+static const struct ad7780_chip_info ad7780_chip_info_tbl[] = {
+ [ID_AD7780] = {
+ .channel = IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 0, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 0, 0, IIO_ST('s', 24, 32, 8), 0),
+ },
+ [ID_AD7781] = {
+ .channel = IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 0, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 0, 0, IIO_ST('s', 20, 32, 12), 0),
+ },
+};
+
+/**
+ * Interrupt handler
+ */
+static irqreturn_t ad7780_interrupt(int irq, void *dev_id)
+{
+ struct ad7780_state *st = dev_id;
+
+ st->done = true;
+ wake_up_interruptible(&st->wq_data_avail);
+
+ return IRQ_HANDLED;
+};
+
+static const struct iio_info ad7780_info = {
+ .read_raw = &ad7780_read_raw,
+ .driver_module = THIS_MODULE,
+};
+
+static int __devinit ad7780_probe(struct spi_device *spi)
+{
+ struct ad7780_platform_data *pdata = spi->dev.platform_data;
+ struct ad7780_state *st;
+ struct iio_dev *indio_dev;
+ int ret, voltage_uv = 0;
+
+ if (!pdata) {
+ dev_dbg(&spi->dev, "no platform data?\n");
+ return -ENODEV;
+ }
+
+ indio_dev = iio_allocate_device(sizeof(*st));
+ if (indio_dev == NULL)
+ return -ENOMEM;
+
+ st = iio_priv(indio_dev);
+
+ st->reg = regulator_get(&spi->dev, "vcc");
+ if (!IS_ERR(st->reg)) {
+ ret = regulator_enable(st->reg);
+ if (ret)
+ goto error_put_reg;
+
+ voltage_uv = regulator_get_voltage(st->reg);
+ }
+
+ st->chip_info =
+ &ad7780_chip_info_tbl[spi_get_device_id(spi)->driver_data];
+
+ st->pdata = pdata;
+
+ if (pdata && pdata->vref_mv)
+ st->int_vref_mv = pdata->vref_mv;
+ else if (voltage_uv)
+ st->int_vref_mv = voltage_uv / 1000;
+ else
+ dev_warn(&spi->dev, "reference voltage unspecified\n");
+
+ spi_set_drvdata(spi, indio_dev);
+ st->spi = spi;
+
+ indio_dev->dev.parent = &spi->dev;
+ indio_dev->name = spi_get_device_id(spi)->name;
+ indio_dev->modes = INDIO_DIRECT_MODE;
+ indio_dev->channels = &st->chip_info->channel;
+ indio_dev->num_channels = 1;
+ indio_dev->info = &ad7780_info;
+
+ init_waitqueue_head(&st->wq_data_avail);
+
+ /* Setup default message */
+
+ st->xfer.rx_buf = &st->data;
+ st->xfer.len = st->chip_info->channel.scan_type.storagebits / 8;
+
+ spi_message_init(&st->msg);
+ spi_message_add_tail(&st->xfer, &st->msg);
+
+ ret = gpio_request_one(st->pdata->gpio_pdrst, GPIOF_OUT_INIT_LOW,
+ "AD7780 /PDRST");
+ if (ret) {
+ dev_err(&spi->dev, "failed to request GPIO PDRST\n");
+ goto error_disable_reg;
+ }
+
+ ret = request_irq(spi->irq, ad7780_interrupt,
+ IRQF_TRIGGER_FALLING, spi_get_device_id(spi)->name, st);
+ if (ret)
+ goto error_free_gpio;
+
+ disable_irq(spi->irq);
+
+ ret = iio_device_register(indio_dev);
+ if (ret)
+ goto error_free_irq;
+
+ return 0;
+
+error_free_irq:
+ free_irq(spi->irq, st);
+error_free_gpio:
+ gpio_free(st->pdata->gpio_pdrst);
+error_disable_reg:
+ if (!IS_ERR(st->reg))
+ regulator_disable(st->reg);
+error_put_reg:
+ if (!IS_ERR(st->reg))
+ regulator_put(st->reg);
+
+ iio_free_device(indio_dev);
+
+ return ret;
+}
+
+static int ad7780_remove(struct spi_device *spi)
+{
+ struct iio_dev *indio_dev = spi_get_drvdata(spi);
+ struct ad7780_state *st = iio_priv(indio_dev);
+
+ free_irq(spi->irq, st);
+ gpio_free(st->pdata->gpio_pdrst);
+ if (!IS_ERR(st->reg)) {
+ regulator_disable(st->reg);
+ regulator_put(st->reg);
+ }
+ iio_device_unregister(indio_dev);
+
+ return 0;
+}
+
+static const struct spi_device_id ad7780_id[] = {
+ {"ad7780", ID_AD7780},
+ {"ad7781", ID_AD7781},
+ {}
+};
+
+static struct spi_driver ad7780_driver = {
+ .driver = {
+ .name = "ad7780",
+ .bus = &spi_bus_type,
+ .owner = THIS_MODULE,
+ },
+ .probe = ad7780_probe,
+ .remove = __devexit_p(ad7780_remove),
+ .id_table = ad7780_id,
+};
+
+static int __init ad7780_init(void)
+{
+ return spi_register_driver(&ad7780_driver);
+}
+module_init(ad7780_init);
+
+static void __exit ad7780_exit(void)
+{
+ spi_unregister_driver(&ad7780_driver);
+}
+module_exit(ad7780_exit);
+
+MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
+MODULE_DESCRIPTION("Analog Devices AD7780/1 ADC");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/staging/iio/adc/ad7780.h b/drivers/staging/iio/adc/ad7780.h
new file mode 100644
index 0000000..67e511c
--- /dev/null
+++ b/drivers/staging/iio/adc/ad7780.h
@@ -0,0 +1,30 @@
+/*
+ * AD7780/AD7781 SPI ADC driver
+ *
+ * Copyright 2011 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2.
+ */
+#ifndef IIO_ADC_AD7780_H_
+#define IIO_ADC_AD7780_H_
+
+/*
+ * TODO: struct ad7780_platform_data needs to go into include/linux/iio
+ */
+
+/* NOTE:
+ * The AD7780 doesn't feature a dedicated SPI chip select, in addition it
+ * features a dual use data out ready DOUT/RDY output.
+ * In order to avoid contentions on the SPI bus, it's therefore necessary
+ * to use spi bus locking combined with a dedicated GPIO to control the
+ * power down reset signal of the AD7780.
+ *
+ * The DOUT/RDY output must also be wired to an interrupt capable GPIO.
+ */
+
+struct ad7780_platform_data {
+ u16 vref_mv;
+ int gpio_pdrst;
+};
+
+#endif /* IIO_ADC_AD7780_H_ */
diff --git a/drivers/staging/iio/adc/ad7816.c b/drivers/staging/iio/adc/ad7816.c
index ad7415a..11379e4 100644
--- a/drivers/staging/iio/adc/ad7816.c
+++ b/drivers/staging/iio/adc/ad7816.c
@@ -8,14 +8,12 @@
#include <linux/interrupt.h>
#include <linux/gpio.h>
-#include <linux/workqueue.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
#include <linux/list.h>
#include <linux/spi/spi.h>
-#include <linux/rtc.h>
#include "../iio.h"
#include "../sysfs.h"
@@ -44,11 +42,8 @@
*/
struct ad7816_chip_info {
- const char *name;
struct spi_device *spi_dev;
struct iio_dev *indio_dev;
- struct work_struct thresh_work;
- s64 last_timestamp;
u16 rdwr_pin;
u16 convert_pin;
u16 busy_pin;
@@ -185,13 +180,13 @@
if (data > AD7816_CS_MAX && data != AD7816_CS_MASK) {
dev_err(&chip->spi_dev->dev, "Invalid channel id %lu for %s.\n",
- data, chip->name);
+ data, dev_info->name);
return -EINVAL;
- } else if (strcmp(chip->name, "ad7818") == 0 && data > 1) {
+ } else if (strcmp(dev_info->name, "ad7818") == 0 && data > 1) {
dev_err(&chip->spi_dev->dev,
"Invalid channel id %lu for ad7818.\n", data);
return -EINVAL;
- } else if (strcmp(chip->name, "ad7816") == 0 && data > 0) {
+ } else if (strcmp(dev_info->name, "ad7816") == 0 && data > 0) {
dev_err(&chip->spi_dev->dev,
"Invalid channel id %lu for ad7816.\n", data);
return -EINVAL;
@@ -236,23 +231,11 @@
static IIO_DEVICE_ATTR(value, S_IRUGO, ad7816_show_value, NULL, 0);
-static ssize_t ad7816_show_name(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- struct iio_dev *dev_info = dev_get_drvdata(dev);
- struct ad7816_chip_info *chip = dev_info->dev_data;
- return sprintf(buf, "%s\n", chip->name);
-}
-
-static IIO_DEVICE_ATTR(name, S_IRUGO, ad7816_show_name, NULL, 0);
-
static struct attribute *ad7816_attributes[] = {
&iio_dev_attr_available_modes.dev_attr.attr,
&iio_dev_attr_mode.dev_attr.attr,
&iio_dev_attr_channel.dev_attr.attr,
&iio_dev_attr_value.dev_attr.attr,
- &iio_dev_attr_name.dev_attr.attr,
NULL,
};
@@ -264,35 +247,19 @@
* temperature bound events
*/
-#define IIO_EVENT_CODE_AD7816_OTI IIO_BUFFER_EVENT_CODE(0)
+#define IIO_EVENT_CODE_AD7816_OTI IIO_UNMOD_EVENT_CODE(IIO_EV_CLASS_TEMP, \
+ 0, \
+ IIO_EV_TYPE_THRESH, \
+ IIO_EV_DIR_FALLING)
-static void ad7816_interrupt_bh(struct work_struct *work_s)
+static irqreturn_t ad7816_event_handler(int irq, void *private)
{
- struct ad7816_chip_info *chip =
- container_of(work_s, struct ad7816_chip_info, thresh_work);
-
- enable_irq(chip->spi_dev->irq);
-
- iio_push_event(chip->indio_dev, 0,
- IIO_EVENT_CODE_AD7816_OTI,
- chip->last_timestamp);
+ iio_push_event(private, 0,
+ IIO_EVENT_CODE_AD7816_OTI,
+ iio_get_time_ns());
+ return IRQ_HANDLED;
}
-static int ad7816_interrupt(struct iio_dev *dev_info,
- int index,
- s64 timestamp,
- int no_test)
-{
- struct ad7816_chip_info *chip = dev_info->dev_data;
-
- chip->last_timestamp = timestamp;
- schedule_work(&chip->thresh_work);
-
- return 0;
-}
-
-IIO_EVENT_SH(ad7816, &ad7816_interrupt);
-
static ssize_t ad7816_show_oti(struct device *dev,
struct device_attribute *attr,
char *buf)
@@ -352,11 +319,11 @@
return len;
}
-IIO_EVENT_ATTR_SH(oti, iio_event_ad7816,
- ad7816_show_oti, ad7816_set_oti, 0);
+static IIO_DEVICE_ATTR(oti, S_IRUGO | S_IWUSR,
+ ad7816_show_oti, ad7816_set_oti, 0);
static struct attribute *ad7816_event_attributes[] = {
- &iio_event_attr_oti.dev_attr.attr,
+ &iio_dev_attr_oti.dev_attr.attr,
NULL,
};
@@ -364,6 +331,13 @@
.attrs = ad7816_event_attributes,
};
+static const struct iio_info ad7816_info = {
+ .attrs = &ad7816_attribute_group,
+ .num_interrupt_lines = 1,
+ .event_attrs = &ad7816_event_attribute_group,
+ .driver_module = THIS_MODULE,
+};
+
/*
* device probe and remove
*/
@@ -389,28 +363,27 @@
dev_set_drvdata(&spi_dev->dev, chip);
chip->spi_dev = spi_dev;
- chip->name = spi_dev->modalias;
for (i = 0; i <= AD7816_CS_MAX; i++)
chip->oti_data[i] = 203;
chip->rdwr_pin = pins[0];
chip->convert_pin = pins[1];
chip->busy_pin = pins[2];
- ret = gpio_request(chip->rdwr_pin, chip->name);
+ ret = gpio_request(chip->rdwr_pin, spi_get_device_id(spi_dev)->name);
if (ret) {
dev_err(&spi_dev->dev, "Fail to request rdwr gpio PIN %d.\n",
chip->rdwr_pin);
goto error_free_chip;
}
gpio_direction_input(chip->rdwr_pin);
- ret = gpio_request(chip->convert_pin, chip->name);
+ ret = gpio_request(chip->convert_pin, spi_get_device_id(spi_dev)->name);
if (ret) {
dev_err(&spi_dev->dev, "Fail to request convert gpio PIN %d.\n",
chip->convert_pin);
goto error_free_gpio_rdwr;
}
gpio_direction_input(chip->convert_pin);
- ret = gpio_request(chip->busy_pin, chip->name);
+ ret = gpio_request(chip->busy_pin, spi_get_device_id(spi_dev)->name);
if (ret) {
dev_err(&spi_dev->dev, "Fail to request busy gpio PIN %d.\n",
chip->busy_pin);
@@ -418,18 +391,15 @@
}
gpio_direction_input(chip->busy_pin);
- chip->indio_dev = iio_allocate_device();
+ chip->indio_dev = iio_allocate_device(0);
if (chip->indio_dev == NULL) {
ret = -ENOMEM;
goto error_free_gpio;
}
-
+ chip->indio_dev->name = spi_get_device_id(spi_dev)->name;
chip->indio_dev->dev.parent = &spi_dev->dev;
- chip->indio_dev->attrs = &ad7816_attribute_group;
- chip->indio_dev->event_attrs = &ad7816_event_attribute_group;
+ chip->indio_dev->info = &ad7816_info;
chip->indio_dev->dev_data = (void *)chip;
- chip->indio_dev->driver_module = THIS_MODULE;
- chip->indio_dev->num_interrupt_lines = 1;
chip->indio_dev->modes = INDIO_DIRECT_MODE;
ret = iio_device_register(chip->indio_dev);
@@ -438,27 +408,18 @@
if (spi_dev->irq) {
/* Only low trigger is supported in ad7816/7/8 */
- ret = iio_register_interrupt_line(spi_dev->irq,
- chip->indio_dev,
- 0,
- IRQF_TRIGGER_LOW,
- chip->name);
+ ret = request_threaded_irq(spi_dev->irq,
+ NULL,
+ &ad7816_event_handler,
+ IRQF_TRIGGER_LOW,
+ chip->indio_dev->name,
+ chip->indio_dev);
if (ret)
goto error_unreg_dev;
-
- /*
- * The event handler list element refer to iio_event_ad7816.
- * All event attributes bind to the same event handler.
- * So, only register event handler once.
- */
- iio_add_event_to_list(&iio_event_ad7816,
- &chip->indio_dev->interrupts[0]->ev_list);
-
- INIT_WORK(&chip->thresh_work, ad7816_interrupt_bh);
}
dev_info(&spi_dev->dev, "%s temperature sensor and ADC registered.\n",
- chip->name);
+ chip->indio_dev->name);
return 0;
@@ -485,7 +446,7 @@
dev_set_drvdata(&spi_dev->dev, NULL);
if (spi_dev->irq)
- iio_unregister_interrupt_line(indio_dev, 0);
+ free_irq(spi_dev->irq, indio_dev);
iio_device_unregister(indio_dev);
iio_free_device(chip->indio_dev);
gpio_free(chip->busy_pin);
diff --git a/drivers/staging/iio/adc/ad7887.h b/drivers/staging/iio/adc/ad7887.h
index 439c802..837046c 100644
--- a/drivers/staging/iio/adc/ad7887.h
+++ b/drivers/staging/iio/adc/ad7887.h
@@ -48,24 +48,23 @@
bool use_onchip_ref;
};
+/**
+ * struct ad7887_chip_info - chip specifc information
+ * @int_vref_mv: the internal reference voltage
+ * @channel: channel specification
+ */
+
struct ad7887_chip_info {
- u8 bits; /* number of ADC bits */
- u8 storagebits; /* number of bits read from the ADC */
- u8 left_shift; /* number of bits the sample must be shifted */
- char sign; /* [s]igned or [u]nsigned */
- u16 int_vref_mv; /* internal reference voltage */
+ u16 int_vref_mv;
+ struct iio_chan_spec channel[3];
};
struct ad7887_state {
- struct iio_dev *indio_dev;
struct spi_device *spi;
const struct ad7887_chip_info *chip_info;
struct regulator *reg;
- struct work_struct poll_work;
- atomic_t protect_ring;
size_t d_size;
u16 int_vref_mv;
- bool en_dual;
struct spi_transfer xfer[4];
struct spi_message msg[3];
struct spi_message *ring_msg;
diff --git a/drivers/staging/iio/adc/ad7887_core.c b/drivers/staging/iio/adc/ad7887_core.c
index 5d85efa..de14b17 100644
--- a/drivers/staging/iio/adc/ad7887_core.c
+++ b/drivers/staging/iio/adc/ad7887_core.c
@@ -1,18 +1,15 @@
/*
* AD7887 SPI ADC driver
*
- * Copyright 2010 Analog Devices Inc.
+ * Copyright 2010-2011 Analog Devices Inc.
*
- * Licensed under the GPL-2 or later.
+ * Licensed under the GPL-2.
*/
-#include <linux/interrupt.h>
-#include <linux/workqueue.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
-#include <linux/list.h>
#include <linux/spi/spi.h>
#include <linux/regulator/consumer.h>
#include <linux/err.h>
@@ -33,108 +30,75 @@
return (st->data[(ch * 2)] << 8) | st->data[(ch * 2) + 1];
}
-static ssize_t ad7887_scan(struct device *dev,
- struct device_attribute *attr,
- char *buf)
+static int ad7887_read_raw(struct iio_dev *dev_info,
+ struct iio_chan_spec const *chan,
+ int *val,
+ int *val2,
+ long m)
{
- struct iio_dev *dev_info = dev_get_drvdata(dev);
- struct ad7887_state *st = dev_info->dev_data;
- struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
int ret;
+ struct ad7887_state *st = dev_info->dev_data;
+ unsigned int scale_uv;
- mutex_lock(&dev_info->mlock);
- if (iio_ring_enabled(dev_info))
- ret = ad7887_scan_from_ring(st, 1 << this_attr->address);
- else
- ret = ad7887_scan_direct(st, this_attr->address);
- mutex_unlock(&dev_info->mlock);
+ switch (m) {
+ case 0:
+ mutex_lock(&dev_info->mlock);
+ if (iio_ring_enabled(dev_info))
+ ret = ad7887_scan_from_ring(st, 1 << chan->address);
+ else
+ ret = ad7887_scan_direct(st, chan->address);
+ mutex_unlock(&dev_info->mlock);
- if (ret < 0)
- return ret;
-
- return sprintf(buf, "%d\n", (ret >> st->chip_info->left_shift) &
- RES_MASK(st->chip_info->bits));
-}
-static IIO_DEV_ATTR_IN_RAW(0, ad7887_scan, 0);
-static IIO_DEV_ATTR_IN_RAW(1, ad7887_scan, 1);
-
-static ssize_t ad7887_show_scale(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- /* Driver currently only support internal vref */
- struct iio_dev *dev_info = dev_get_drvdata(dev);
- struct ad7887_state *st = iio_dev_get_devdata(dev_info);
- /* Corresponds to Vref / 2^(bits) */
- unsigned int scale_uv = (st->int_vref_mv * 1000) >> st->chip_info->bits;
-
- return sprintf(buf, "%d.%03d\n", scale_uv / 1000, scale_uv % 1000);
-}
-static IIO_DEVICE_ATTR(in_scale, S_IRUGO, ad7887_show_scale, NULL, 0);
-
-static ssize_t ad7887_show_name(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- struct iio_dev *dev_info = dev_get_drvdata(dev);
- struct ad7887_state *st = iio_dev_get_devdata(dev_info);
-
- return sprintf(buf, "%s\n", spi_get_device_id(st->spi)->name);
-}
-static IIO_DEVICE_ATTR(name, S_IRUGO, ad7887_show_name, NULL, 0);
-
-static struct attribute *ad7887_attributes[] = {
- &iio_dev_attr_in0_raw.dev_attr.attr,
- &iio_dev_attr_in1_raw.dev_attr.attr,
- &iio_dev_attr_in_scale.dev_attr.attr,
- &iio_dev_attr_name.dev_attr.attr,
- NULL,
-};
-
-static mode_t ad7887_attr_is_visible(struct kobject *kobj,
- struct attribute *attr, int n)
-{
- struct device *dev = container_of(kobj, struct device, kobj);
- struct iio_dev *dev_info = dev_get_drvdata(dev);
- struct ad7887_state *st = iio_dev_get_devdata(dev_info);
-
- mode_t mode = attr->mode;
-
- if ((attr == &iio_dev_attr_in1_raw.dev_attr.attr) && !st->en_dual)
- mode = 0;
-
- return mode;
+ if (ret < 0)
+ return ret;
+ *val = (ret >> st->chip_info->channel[0].scan_type.shift) &
+ RES_MASK(st->chip_info->channel[0].scan_type.realbits);
+ return IIO_VAL_INT;
+ case (1 << IIO_CHAN_INFO_SCALE_SHARED):
+ scale_uv = (st->int_vref_mv * 1000)
+ >> st->chip_info->channel[0].scan_type.realbits;
+ *val = scale_uv/1000;
+ *val2 = (scale_uv%1000)*1000;
+ return IIO_VAL_INT_PLUS_MICRO;
+ }
+ return -EINVAL;
}
-static const struct attribute_group ad7887_attribute_group = {
- .attrs = ad7887_attributes,
- .is_visible = ad7887_attr_is_visible,
-};
static const struct ad7887_chip_info ad7887_chip_info_tbl[] = {
/*
* More devices added in future
*/
[ID_AD7887] = {
- .bits = 12,
- .storagebits = 16,
- .left_shift = 0,
- .sign = IIO_SCAN_EL_TYPE_UNSIGNED,
+ .channel[0] = IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 1, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 1, 1, IIO_ST('u', 12, 16, 0), 0),
+
+ .channel[1] = IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 0, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 0, 0, IIO_ST('u', 12, 16, 0), 0),
+
+ .channel[2] = IIO_CHAN_SOFT_TIMESTAMP(2),
.int_vref_mv = 2500,
},
};
+static const struct iio_info ad7887_info = {
+ .read_raw = &ad7887_read_raw,
+ .driver_module = THIS_MODULE,
+};
+
static int __devinit ad7887_probe(struct spi_device *spi)
{
struct ad7887_platform_data *pdata = spi->dev.platform_data;
struct ad7887_state *st;
- int ret, voltage_uv = 0;
+ int ret, voltage_uv = 0, regdone = 0;
+ struct iio_dev *indio_dev = iio_allocate_device(sizeof(*st));
- st = kzalloc(sizeof(*st), GFP_KERNEL);
- if (st == NULL) {
- ret = -ENOMEM;
- goto error_ret;
- }
+ if (indio_dev == NULL)
+ return -ENOMEM;
+
+ st = iio_priv(indio_dev);
st->reg = regulator_get(&spi->dev, "vcc");
if (!IS_ERR(st->reg)) {
@@ -148,23 +112,15 @@
st->chip_info =
&ad7887_chip_info_tbl[spi_get_device_id(spi)->driver_data];
- spi_set_drvdata(spi, st);
-
- atomic_set(&st->protect_ring, 0);
+ spi_set_drvdata(spi, indio_dev);
st->spi = spi;
- st->indio_dev = iio_allocate_device();
- if (st->indio_dev == NULL) {
- ret = -ENOMEM;
- goto error_disable_reg;
- }
-
/* Estabilish that the iio_dev is a child of the spi device */
- st->indio_dev->dev.parent = &spi->dev;
- st->indio_dev->attrs = &ad7887_attribute_group;
- st->indio_dev->dev_data = (void *)(st);
- st->indio_dev->driver_module = THIS_MODULE;
- st->indio_dev->modes = INDIO_DIRECT_MODE;
+ indio_dev->dev.parent = &spi->dev;
+ indio_dev->name = spi_get_device_id(spi)->name;
+ indio_dev->dev_data = (void *)(st);
+ indio_dev->info = &ad7887_info;
+ indio_dev->modes = INDIO_DIRECT_MODE;
/* Setup default message */
@@ -208,8 +164,6 @@
spi_message_init(&st->msg[AD7887_CH1]);
spi_message_add_tail(&st->xfer[3], &st->msg[AD7887_CH1]);
- st->en_dual = true;
-
if (pdata && pdata->vref_mv)
st->int_vref_mv = pdata->vref_mv;
else if (voltage_uv)
@@ -217,6 +171,8 @@
else
dev_warn(&spi->dev, "reference voltage unspecified\n");
+ indio_dev->channels = st->chip_info->channel;
+ indio_dev->num_channels = 3;
} else {
if (pdata && pdata->vref_mv)
st->int_vref_mv = pdata->vref_mv;
@@ -224,50 +180,56 @@
st->int_vref_mv = st->chip_info->int_vref_mv;
else
dev_warn(&spi->dev, "reference voltage unspecified\n");
+
+ indio_dev->channels = &st->chip_info->channel[1];
+ indio_dev->num_channels = 2;
}
-
- ret = ad7887_register_ring_funcs_and_init(st->indio_dev);
+ ret = ad7887_register_ring_funcs_and_init(indio_dev);
if (ret)
- goto error_free_device;
+ goto error_disable_reg;
- ret = iio_device_register(st->indio_dev);
+ ret = iio_device_register(indio_dev);
if (ret)
- goto error_free_device;
+ goto error_disable_reg;
+ regdone = 1;
- ret = iio_ring_buffer_register(st->indio_dev->ring, 0);
+ ret = iio_ring_buffer_register_ex(indio_dev->ring, 0,
+ indio_dev->channels,
+ indio_dev->num_channels);
if (ret)
goto error_cleanup_ring;
return 0;
error_cleanup_ring:
- ad7887_ring_cleanup(st->indio_dev);
- iio_device_unregister(st->indio_dev);
-error_free_device:
- iio_free_device(st->indio_dev);
+ ad7887_ring_cleanup(indio_dev);
error_disable_reg:
if (!IS_ERR(st->reg))
regulator_disable(st->reg);
error_put_reg:
if (!IS_ERR(st->reg))
regulator_put(st->reg);
- kfree(st);
-error_ret:
+ if (regdone)
+ iio_device_unregister(indio_dev);
+ else
+ iio_free_device(indio_dev);
+
return ret;
}
static int ad7887_remove(struct spi_device *spi)
{
- struct ad7887_state *st = spi_get_drvdata(spi);
- struct iio_dev *indio_dev = st->indio_dev;
+ struct iio_dev *indio_dev = spi_get_drvdata(spi);
+ struct ad7887_state *st = iio_priv(indio_dev);
+
iio_ring_buffer_unregister(indio_dev->ring);
ad7887_ring_cleanup(indio_dev);
- iio_device_unregister(indio_dev);
if (!IS_ERR(st->reg)) {
regulator_disable(st->reg);
regulator_put(st->reg);
}
- kfree(st);
+ iio_device_unregister(indio_dev);
+
return 0;
}
diff --git a/drivers/staging/iio/adc/ad7887_ring.c b/drivers/staging/iio/adc/ad7887_ring.c
index da77f26..0e4a5f4 100644
--- a/drivers/staging/iio/adc/ad7887_ring.c
+++ b/drivers/staging/iio/adc/ad7887_ring.c
@@ -1,20 +1,17 @@
/*
- * Copyright 2010 Analog Devices Inc.
+ * Copyright 2010-2011 Analog Devices Inc.
* Copyright (C) 2008 Jonathan Cameron
*
- * Licensed under the GPL-2 or later.
+ * Licensed under the GPL-2.
*
* ad7887_ring.c
*/
#include <linux/interrupt.h>
-#include <linux/gpio.h>
-#include <linux/workqueue.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
-#include <linux/list.h>
#include <linux/spi/spi.h>
#include "../iio.h"
@@ -25,64 +22,9 @@
#include "ad7887.h"
-static IIO_SCAN_EL_C(in0, 0, 0, NULL);
-static IIO_SCAN_EL_C(in1, 1, 0, NULL);
-static IIO_SCAN_EL_TIMESTAMP(2);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(timestamp, s, 64, 64);
-
-static ssize_t ad7887_show_type(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- struct iio_ring_buffer *ring = dev_get_drvdata(dev);
- struct iio_dev *indio_dev = ring->indio_dev;
- struct ad7887_state *st = indio_dev->dev_data;
-
- return sprintf(buf, "%c%d/%d>>%d\n", st->chip_info->sign,
- st->chip_info->bits, st->chip_info->storagebits,
- st->chip_info->left_shift);
-}
-static IIO_DEVICE_ATTR(in_type, S_IRUGO, ad7887_show_type, NULL, 0);
-
-static struct attribute *ad7887_scan_el_attrs[] = {
- &iio_scan_el_in0.dev_attr.attr,
- &iio_const_attr_in0_index.dev_attr.attr,
- &iio_scan_el_in1.dev_attr.attr,
- &iio_const_attr_in1_index.dev_attr.attr,
- &iio_const_attr_timestamp_index.dev_attr.attr,
- &iio_scan_el_timestamp.dev_attr.attr,
- &iio_const_attr_timestamp_type.dev_attr.attr,
- &iio_dev_attr_in_type.dev_attr.attr,
- NULL,
-};
-
-static mode_t ad7887_scan_el_attr_is_visible(struct kobject *kobj,
- struct attribute *attr, int n)
-{
- struct device *dev = container_of(kobj, struct device, kobj);
- struct iio_ring_buffer *ring = dev_get_drvdata(dev);
- struct iio_dev *indio_dev = ring->indio_dev;
- struct ad7887_state *st = indio_dev->dev_data;
-
- mode_t mode = attr->mode;
-
- if ((attr == &iio_scan_el_in1.dev_attr.attr) ||
- (attr == &iio_const_attr_in1_index.dev_attr.attr))
- if (!st->en_dual)
- mode = 0;
-
- return mode;
-}
-
-static struct attribute_group ad7887_scan_el_group = {
- .name = "scan_elements",
- .attrs = ad7887_scan_el_attrs,
- .is_visible = ad7887_scan_el_attr_is_visible,
-};
-
int ad7887_scan_from_ring(struct ad7887_state *st, long mask)
{
- struct iio_ring_buffer *ring = st->indio_dev->ring;
+ struct iio_ring_buffer *ring = iio_priv_to_dev(st)->ring;
int count = 0, ret;
u16 *ring_data;
@@ -91,12 +33,13 @@
goto error_ret;
}
- ring_data = kmalloc(ring->access.get_bytes_per_datum(ring), GFP_KERNEL);
+ ring_data = kmalloc(ring->access->get_bytes_per_datum(ring),
+ GFP_KERNEL);
if (ring_data == NULL) {
ret = -ENOMEM;
goto error_ret;
}
- ret = ring->access.read_last(ring, (u8 *) ring_data);
+ ret = ring->access->read_last(ring, (u8 *) ring_data);
if (ret)
goto error_free_ring_data;
@@ -124,7 +67,8 @@
struct ad7887_state *st = indio_dev->dev_data;
struct iio_ring_buffer *ring = indio_dev->ring;
- st->d_size = ring->scan_count * st->chip_info->storagebits / 8;
+ st->d_size = ring->scan_count *
+ st->chip_info->channel[0].scan_type.storagebits / 8;
if (ring->scan_timestamp) {
st->d_size += sizeof(s64);
@@ -133,8 +77,8 @@
st->d_size += sizeof(s64) - (st->d_size % sizeof(s64));
}
- if (indio_dev->ring->access.set_bytes_per_datum)
- indio_dev->ring->access.set_bytes_per_datum(indio_dev->ring,
+ if (indio_dev->ring->access->set_bytes_per_datum)
+ indio_dev->ring->access->set_bytes_per_datum(indio_dev->ring,
st->d_size);
switch (ring->scan_mask) {
@@ -163,48 +107,27 @@
}
/**
- * ad7887_poll_func_th() th of trigger launched polling to ring buffer
- *
- * As sampling only occurs on spi comms occurring, leave timestamping until
- * then. Some triggers will generate their own time stamp. Currently
- * there is no way of notifying them when no one cares.
- **/
-static void ad7887_poll_func_th(struct iio_dev *indio_dev, s64 time)
-{
- struct ad7887_state *st = indio_dev->dev_data;
-
- schedule_work(&st->poll_work);
- return;
-}
-/**
- * ad7887_poll_bh_to_ring() bh of trigger launched polling to ring buffer
- * @work_s: the work struct through which this was scheduled
+ * ad7887_trigger_handler() bh of trigger launched polling to ring buffer
*
* Currently there is no option in this driver to disable the saving of
* timestamps within the ring.
- * I think the one copy of this at a time was to avoid problems if the
- * trigger was set far too high and the reads then locked up the computer.
**/
-static void ad7887_poll_bh_to_ring(struct work_struct *work_s)
+static irqreturn_t ad7887_trigger_handler(int irq, void *p)
{
- struct ad7887_state *st = container_of(work_s, struct ad7887_state,
- poll_work);
- struct iio_dev *indio_dev = st->indio_dev;
- struct iio_sw_ring_buffer *sw_ring = iio_to_sw_ring(indio_dev->ring);
+ struct iio_poll_func *pf = p;
+ struct iio_dev *indio_dev = pf->private_data;
+ struct ad7887_state *st = iio_dev_get_devdata(indio_dev);
struct iio_ring_buffer *ring = indio_dev->ring;
s64 time_ns;
__u8 *buf;
int b_sent;
- unsigned int bytes = ring->scan_count * st->chip_info->storagebits / 8;
-
- /* Ensure only one copy of this function running at a time */
- if (atomic_inc_return(&st->protect_ring) > 1)
- return;
+ unsigned int bytes = ring->scan_count *
+ st->chip_info->channel[0].scan_type.storagebits / 8;
buf = kzalloc(st->d_size, GFP_KERNEL);
if (buf == NULL)
- return;
+ return -ENOMEM;
b_sent = spi_sync(st->spi, st->ring_msg);
if (b_sent)
@@ -215,17 +138,25 @@
memcpy(buf, st->data, bytes);
if (ring->scan_timestamp)
memcpy(buf + st->d_size - sizeof(s64),
- &time_ns, sizeof(time_ns));
+ &time_ns, sizeof(time_ns));
- indio_dev->ring->access.store_to(&sw_ring->buf, buf, time_ns);
+ indio_dev->ring->access->store_to(indio_dev->ring, buf, time_ns);
done:
kfree(buf);
- atomic_dec(&st->protect_ring);
+ iio_trigger_notify_done(indio_dev->trig);
+
+ return IRQ_HANDLED;
}
+static const struct iio_ring_setup_ops ad7887_ring_setup_ops = {
+ .preenable = &ad7887_ring_preenable,
+ .postenable = &iio_triggered_ring_postenable,
+ .predisable = &iio_triggered_ring_predisable,
+ .postdisable = &ad7887_ring_postdisable,
+};
+
int ad7887_register_ring_funcs_and_init(struct iio_dev *indio_dev)
{
- struct ad7887_state *st = indio_dev->dev_data;
int ret;
indio_dev->ring = iio_sw_rb_allocate(indio_dev);
@@ -234,25 +165,24 @@
goto error_ret;
}
/* Effectively select the ring buffer implementation */
- iio_ring_sw_register_funcs(&indio_dev->ring->access);
- ret = iio_alloc_pollfunc(indio_dev, NULL, &ad7887_poll_func_th);
- if (ret)
+ indio_dev->ring->access = &ring_sw_access_funcs;
+ indio_dev->pollfunc = iio_alloc_pollfunc(&iio_pollfunc_store_time,
+ &ad7887_trigger_handler,
+ IRQF_ONESHOT,
+ indio_dev,
+ "ad7887_consumer%d",
+ indio_dev->id);
+ if (indio_dev->pollfunc == NULL) {
+ ret = -ENOMEM;
goto error_deallocate_sw_rb;
-
+ }
/* Ring buffer functions - here trigger setup related */
-
- indio_dev->ring->preenable = &ad7887_ring_preenable;
- indio_dev->ring->postenable = &iio_triggered_ring_postenable;
- indio_dev->ring->predisable = &iio_triggered_ring_predisable;
- indio_dev->ring->postdisable = &ad7887_ring_postdisable;
- indio_dev->ring->scan_el_attrs = &ad7887_scan_el_group;
- indio_dev->ring->scan_timestamp = true;
-
- INIT_WORK(&st->poll_work, &ad7887_poll_bh_to_ring);
+ indio_dev->ring->setup_ops = &ad7887_ring_setup_ops;
/* Flag that polled ring buffering is possible */
indio_dev->modes |= INDIO_RING_TRIGGERED;
return 0;
+
error_deallocate_sw_rb:
iio_sw_rb_free(indio_dev->ring);
error_ret:
@@ -267,6 +197,6 @@
iio_trigger_dettach_poll_func(indio_dev->trig,
indio_dev->pollfunc);
}
- kfree(indio_dev->pollfunc);
+ iio_dealloc_pollfunc(indio_dev->pollfunc);
iio_sw_rb_free(indio_dev->ring);
}
diff --git a/drivers/staging/iio/adc/ad799x.h b/drivers/staging/iio/adc/ad799x.h
index a421362..0dc9b4c 100644
--- a/drivers/staging/iio/adc/ad799x.h
+++ b/drivers/staging/iio/adc/ad799x.h
@@ -1,5 +1,5 @@
/*
- * Copyright (C) 2010 Michael Hennerich, Analog Devices Inc.
+ * Copyright (C) 2010-2011 Michael Hennerich, Analog Devices Inc.
* Copyright (C) 2008-2010 Jonathan Cameron
*
* This program is free software; you can redistribute it and/or modify
@@ -67,6 +67,8 @@
#define AD7997_8_READ_SINGLE 0x80
#define AD7997_8_READ_SEQUENCE 0x70
+/* TODO: move this into a common header */
+#define RES_MASK(bits) ((1 << (bits)) - 1)
enum {
ad7991,
@@ -83,43 +85,28 @@
/**
* struct ad799x_chip_info - chip specifc information
- * @num_inputs: number of physical inputs on chip
- * @bits: accuracy of the adc in bits
+ * @channel: channel specification
+ * @num_channels: number of channels
* @int_vref_mv: the internal reference voltage
* @monitor_mode: whether the chip supports monitor interrupts
* @default_config: device default configuration
- * @dev_attrs: pointer to the device attribute group
- * @scan_attrs: pointer to the scan element attribute group
* @event_attrs: pointer to the monitor event attribute group
- * @ad799x_set_scan_mode: function pointer to the device specific mode function
-
*/
+
struct ad799x_chip_info {
- u8 num_inputs;
- u8 bits;
- u8 storagebits;
- char sign;
+ struct iio_chan_spec channel[9];
+ int num_channels;
u16 int_vref_mv;
- bool monitor_mode;
u16 default_config;
- struct attribute_group *dev_attrs;
- struct attribute_group *scan_attrs;
- struct attribute_group *event_attrs;
- int (*ad799x_set_scan_mode) (struct ad799x_state *st,
- unsigned mask);
+ const struct iio_info *info;
};
struct ad799x_state {
- struct iio_dev *indio_dev;
struct i2c_client *client;
const struct ad799x_chip_info *chip_info;
- struct work_struct poll_work;
- struct work_struct work_thresh;
- atomic_t protect_ring;
size_t d_size;
struct iio_trigger *trig;
struct regulator *reg;
- s64 last_timestamp;
u16 int_vref_mv;
unsigned id;
char *name;
@@ -134,7 +121,7 @@
u16 vref_mv;
};
-int ad799x_set_scan_mode(struct ad799x_state *st, unsigned mask);
+int ad7997_8_set_scan_mode(struct ad799x_state *st, unsigned mask);
#ifdef CONFIG_AD799X_RING_BUFFER
int ad799x_single_channel_from_ring(struct ad799x_state *st, long mask);
diff --git a/drivers/staging/iio/adc/ad799x_core.c b/drivers/staging/iio/adc/ad799x_core.c
index f04e642..29bfbcf 100644
--- a/drivers/staging/iio/adc/ad799x_core.c
+++ b/drivers/staging/iio/adc/ad799x_core.c
@@ -1,6 +1,6 @@
/*
* iio/adc/ad799x.c
- * Copyright (C) 2010 Michael Hennerich, Analog Devices Inc.
+ * Copyright (C) 2010-1011 Michael Hennerich, Analog Devices Inc.
*
* based on iio/adc/max1363
* Copyright (C) 2008-2010 Jonathan Cameron
@@ -23,11 +23,9 @@
*/
#include <linux/interrupt.h>
-#include <linux/workqueue.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/sysfs.h>
-#include <linux/list.h>
#include <linux/i2c.h>
#include <linux/regulator/consumer.h>
#include <linux/slab.h>
@@ -100,130 +98,77 @@
return ret;
}
-static int ad799x_scan_el_set_state(struct iio_scan_el *scan_el,
- struct iio_dev *indio_dev,
- bool state)
-{
- struct ad799x_state *st = indio_dev->dev_data;
- return ad799x_set_scan_mode(st, st->indio_dev->ring->scan_mask);
-}
-
-/* Here we claim all are 16 bits. This currently does no harm and saves
- * us a lot of scan element listings */
-
-#define AD799X_SCAN_EL(number) \
- IIO_SCAN_EL_C(in##number, number, 0, ad799x_scan_el_set_state);
-
-static AD799X_SCAN_EL(0);
-static AD799X_SCAN_EL(1);
-static AD799X_SCAN_EL(2);
-static AD799X_SCAN_EL(3);
-static AD799X_SCAN_EL(4);
-static AD799X_SCAN_EL(5);
-static AD799X_SCAN_EL(6);
-static AD799X_SCAN_EL(7);
-
-static IIO_SCAN_EL_TIMESTAMP(8);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(timestamp, s, 64, 64)
-
-static ssize_t ad799x_show_type(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- struct iio_ring_buffer *ring = dev_get_drvdata(dev);
- struct iio_dev *indio_dev = ring->indio_dev;
- struct ad799x_state *st = indio_dev->dev_data;
-
- return sprintf(buf, "%c%d/%d\n", st->chip_info->sign,
- st->chip_info->bits, AD799X_STORAGEBITS);
-}
-static IIO_DEVICE_ATTR(in_type, S_IRUGO, ad799x_show_type, NULL, 0);
-
-static int ad7991_5_9_set_scan_mode(struct ad799x_state *st, unsigned mask)
-{
- return i2c_smbus_write_byte(st->client,
- st->config | (mask << AD799X_CHANNEL_SHIFT));
-}
-
-static int ad7992_3_4_set_scan_mode(struct ad799x_state *st, unsigned mask)
-{
- return ad799x_i2c_write8(st, AD7998_CONF_REG,
- st->config | (mask << AD799X_CHANNEL_SHIFT));
-}
-
-static int ad7997_8_set_scan_mode(struct ad799x_state *st, unsigned mask)
+int ad7997_8_set_scan_mode(struct ad799x_state *st, unsigned mask)
{
return ad799x_i2c_write16(st, AD7998_CONF_REG,
st->config | (mask << AD799X_CHANNEL_SHIFT));
}
-int ad799x_set_scan_mode(struct ad799x_state *st, unsigned mask)
+static int ad799x_scan_direct(struct ad799x_state *st, unsigned ch)
{
+ u16 rxbuf;
+ u8 cmd;
int ret;
- if (st->chip_info->ad799x_set_scan_mode != NULL) {
- ret = st->chip_info->ad799x_set_scan_mode(st, mask);
- return (ret > 0) ? 0 : ret;
+ switch (st->id) {
+ case ad7991:
+ case ad7995:
+ case ad7999:
+ cmd = st->config | ((1 << ch) << AD799X_CHANNEL_SHIFT);
+ break;
+ case ad7992:
+ case ad7993:
+ case ad7994:
+ cmd = (1 << ch) << AD799X_CHANNEL_SHIFT;
+ break;
+ case ad7997:
+ case ad7998:
+ cmd = (ch << AD799X_CHANNEL_SHIFT) | AD7997_8_READ_SINGLE;
+ break;
+ default:
+ return -EINVAL;
}
- return 0;
+ ret = ad799x_i2c_read16(st, cmd, &rxbuf);
+ if (ret < 0)
+ return ret;
+
+ return rxbuf;
}
-static ssize_t ad799x_read_single_channel(struct device *dev,
- struct device_attribute *attr,
- char *buf)
+static int ad799x_read_raw(struct iio_dev *dev_info,
+ struct iio_chan_spec const *chan,
+ int *val,
+ int *val2,
+ long m)
{
- struct iio_dev *dev_info = dev_get_drvdata(dev);
- struct ad799x_state *st = iio_dev_get_devdata(dev_info);
- struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
- int ret = 0, len = 0;
- u32 data ;
- u16 rxbuf[1];
- u8 cmd;
- long mask;
+ int ret;
+ struct ad799x_state *st = dev_info->dev_data;
+ unsigned int scale_uv;
- mutex_lock(&dev_info->mlock);
- mask = 1 << this_attr->address;
- /* If ring buffer capture is occurring, query the buffer */
- if (iio_ring_enabled(dev_info)) {
- data = ret = ad799x_single_channel_from_ring(st, mask);
+ switch (m) {
+ case 0:
+ mutex_lock(&dev_info->mlock);
+ if (iio_ring_enabled(dev_info))
+ ret = ad799x_single_channel_from_ring(st,
+ 1 << chan->address);
+ else
+ ret = ad799x_scan_direct(st, chan->address);
+ mutex_unlock(&dev_info->mlock);
+
if (ret < 0)
- goto error_ret;
- ret = 0;
- } else {
- switch (st->id) {
- case ad7991:
- case ad7995:
- case ad7999:
- cmd = st->config | (mask << AD799X_CHANNEL_SHIFT);
- break;
- case ad7992:
- case ad7993:
- case ad7994:
- cmd = mask << AD799X_CHANNEL_SHIFT;
- break;
- case ad7997:
- case ad7998:
- cmd = (this_attr->address <<
- AD799X_CHANNEL_SHIFT) | AD7997_8_READ_SINGLE;
- break;
- default:
- cmd = 0;
-
- }
- ret = ad799x_i2c_read16(st, cmd, rxbuf);
- if (ret < 0)
- goto error_ret;
-
- data = rxbuf[0];
+ return ret;
+ *val = (ret >> st->chip_info->channel[0].scan_type.shift) &
+ RES_MASK(st->chip_info->channel[0].scan_type.realbits);
+ return IIO_VAL_INT;
+ case (1 << IIO_CHAN_INFO_SCALE_SHARED):
+ scale_uv = (st->int_vref_mv * 1000)
+ >> st->chip_info->channel[0].scan_type.realbits;
+ *val = scale_uv / 1000;
+ *val2 = (scale_uv % 1000) * 1000;
+ return IIO_VAL_INT_PLUS_MICRO;
}
-
- /* Pretty print the result */
- len = sprintf(buf, "%u\n", data & ((1 << (st->chip_info->bits)) - 1));
-
-error_ret:
- mutex_unlock(&dev_info->mlock);
- return ret ? ret : len;
+ return -EINVAL;
}
static ssize_t ad799x_read_frequency(struct device *dev,
@@ -331,18 +276,17 @@
return ret ? ret : len;
}
-
static ssize_t ad799x_read_channel_config(struct device *dev,
struct device_attribute *attr,
char *buf)
{
struct iio_dev *dev_info = dev_get_drvdata(dev);
struct ad799x_state *st = iio_dev_get_devdata(dev_info);
- struct iio_event_attr *this_attr = to_iio_event_attr(attr);
+ struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
int ret;
u16 val;
- ret = ad799x_i2c_read16(st, this_attr->mask, &val);
+ ret = ad799x_i2c_read16(st, this_attr->address, &val);
if (ret)
return ret;
@@ -356,7 +300,7 @@
{
struct iio_dev *dev_info = dev_get_drvdata(dev);
struct ad799x_state *st = iio_dev_get_devdata(dev_info);
- struct iio_event_attr *this_attr = to_iio_event_attr(attr);
+ struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
long val;
int ret;
@@ -366,273 +310,111 @@
return ret;
mutex_lock(&dev_info->mlock);
- ret = ad799x_i2c_write16(st, this_attr->mask, val);
+ ret = ad799x_i2c_write16(st, this_attr->address, val);
mutex_unlock(&dev_info->mlock);
return ret ? ret : len;
}
-static void ad799x_interrupt_bh(struct work_struct *work_s)
+static irqreturn_t ad799x_event_handler(int irq, void *private)
{
- struct ad799x_state *st = container_of(work_s,
- struct ad799x_state, work_thresh);
+ struct iio_dev *indio_dev = private;
+ struct ad799x_state *st = iio_dev_get_devdata(private);
u8 status;
- int i;
+ int i, ret;
- if (ad799x_i2c_read8(st, AD7998_ALERT_STAT_REG, &status))
- goto err_out;
+ ret = ad799x_i2c_read8(st, AD7998_ALERT_STAT_REG, &status);
+ if (ret)
+ return ret;
if (!status)
- goto err_out;
+ return -EIO;
ad799x_i2c_write8(st, AD7998_ALERT_STAT_REG, AD7998_ALERT_STAT_CLEAR);
for (i = 0; i < 8; i++) {
if (status & (1 << i))
- iio_push_event(st->indio_dev, 0,
- i & 0x1 ?
- IIO_EVENT_CODE_IN_HIGH_THRESH(i >> 1) :
- IIO_EVENT_CODE_IN_LOW_THRESH(i >> 1),
- st->last_timestamp);
+ iio_push_event(indio_dev, 0,
+ i & 0x1 ?
+ IIO_EVENT_CODE_IN_HIGH_THRESH(i >> 1) :
+ IIO_EVENT_CODE_IN_LOW_THRESH(i >> 1),
+ iio_get_time_ns());
}
-err_out:
- enable_irq(st->client->irq);
+ return IRQ_HANDLED;
}
-static int ad799x_interrupt(struct iio_dev *dev_info,
- int index,
- s64 timestamp,
- int no_test)
-{
- struct ad799x_state *st = dev_info->dev_data;
+static IIO_DEVICE_ATTR(in0_thresh_low_value,
+ S_IRUGO | S_IWUSR,
+ ad799x_read_channel_config,
+ ad799x_write_channel_config,
+ AD7998_DATALOW_CH1_REG);
- st->last_timestamp = timestamp;
- schedule_work(&st->work_thresh);
- return 0;
-}
+static IIO_DEVICE_ATTR(in0_thresh_high_value,
+ S_IRUGO | S_IWUSR,
+ ad799x_read_channel_config,
+ ad799x_write_channel_config,
+ AD7998_DATAHIGH_CH1_REG);
-IIO_EVENT_SH(ad799x, &ad799x_interrupt);
+static IIO_DEVICE_ATTR(in0_thresh_both_hyst_raw,
+ S_IRUGO | S_IWUSR,
+ ad799x_read_channel_config,
+ ad799x_write_channel_config,
+ AD7998_HYST_CH1_REG);
-/* Direct read attribtues */
-static IIO_DEV_ATTR_IN_RAW(0, ad799x_read_single_channel, 0);
-static IIO_DEV_ATTR_IN_RAW(1, ad799x_read_single_channel, 1);
-static IIO_DEV_ATTR_IN_RAW(2, ad799x_read_single_channel, 2);
-static IIO_DEV_ATTR_IN_RAW(3, ad799x_read_single_channel, 3);
-static IIO_DEV_ATTR_IN_RAW(4, ad799x_read_single_channel, 4);
-static IIO_DEV_ATTR_IN_RAW(5, ad799x_read_single_channel, 5);
-static IIO_DEV_ATTR_IN_RAW(6, ad799x_read_single_channel, 6);
-static IIO_DEV_ATTR_IN_RAW(7, ad799x_read_single_channel, 7);
+static IIO_DEVICE_ATTR(in1_thresh_low_value,
+ S_IRUGO | S_IWUSR,
+ ad799x_read_channel_config,
+ ad799x_write_channel_config,
+ AD7998_DATALOW_CH2_REG);
-static ssize_t ad799x_show_scale(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- /* Driver currently only support internal vref */
- struct iio_dev *dev_info = dev_get_drvdata(dev);
- struct ad799x_state *st = iio_dev_get_devdata(dev_info);
+static IIO_DEVICE_ATTR(in1_thresh_high_value,
+ S_IRUGO | S_IWUSR,
+ ad799x_read_channel_config,
+ ad799x_write_channel_config,
+ AD7998_DATAHIGH_CH2_REG);
- /* Corresponds to Vref / 2^(bits) */
- unsigned int scale_uv = (st->int_vref_mv * 1000) >> st->chip_info->bits;
+static IIO_DEVICE_ATTR(in1_thresh_both_hyst_raw,
+ S_IRUGO | S_IWUSR,
+ ad799x_read_channel_config,
+ ad799x_write_channel_config,
+ AD7998_HYST_CH2_REG);
- return sprintf(buf, "%d.%03d\n", scale_uv / 1000, scale_uv % 1000);
-}
+static IIO_DEVICE_ATTR(in2_thresh_low_value,
+ S_IRUGO | S_IWUSR,
+ ad799x_read_channel_config,
+ ad799x_write_channel_config,
+ AD7998_DATALOW_CH3_REG);
-static IIO_DEVICE_ATTR(in_scale, S_IRUGO, ad799x_show_scale, NULL, 0);
+static IIO_DEVICE_ATTR(in2_thresh_high_value,
+ S_IRUGO | S_IWUSR,
+ ad799x_read_channel_config,
+ ad799x_write_channel_config,
+ AD7998_DATAHIGH_CH3_REG);
-static ssize_t ad799x_show_name(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- struct iio_dev *dev_info = dev_get_drvdata(dev);
- struct ad799x_state *st = iio_dev_get_devdata(dev_info);
- return sprintf(buf, "%s\n", st->client->name);
-}
+static IIO_DEVICE_ATTR(in2_thresh_both_hyst_raw,
+ S_IRUGO | S_IWUSR,
+ ad799x_read_channel_config,
+ ad799x_write_channel_config,
+ AD7998_HYST_CH3_REG);
-static IIO_DEVICE_ATTR(name, S_IRUGO, ad799x_show_name, NULL, 0);
+static IIO_DEVICE_ATTR(in3_thresh_low_value,
+ S_IRUGO | S_IWUSR,
+ ad799x_read_channel_config,
+ ad799x_write_channel_config,
+ AD7998_DATALOW_CH4_REG);
-static struct attribute *ad7991_5_9_3_4_device_attrs[] = {
- &iio_dev_attr_in0_raw.dev_attr.attr,
- &iio_dev_attr_in1_raw.dev_attr.attr,
- &iio_dev_attr_in2_raw.dev_attr.attr,
- &iio_dev_attr_in3_raw.dev_attr.attr,
- &iio_dev_attr_name.dev_attr.attr,
- &iio_dev_attr_in_scale.dev_attr.attr,
- NULL
-};
+static IIO_DEVICE_ATTR(in3_thresh_high_value,
+ S_IRUGO | S_IWUSR,
+ ad799x_read_channel_config,
+ ad799x_write_channel_config,
+ AD7998_DATAHIGH_CH4_REG);
-static struct attribute_group ad7991_5_9_3_4_dev_attr_group = {
- .attrs = ad7991_5_9_3_4_device_attrs,
-};
-
-static struct attribute *ad7991_5_9_3_4_scan_el_attrs[] = {
- &iio_scan_el_in0.dev_attr.attr,
- &iio_const_attr_in0_index.dev_attr.attr,
- &iio_scan_el_in1.dev_attr.attr,
- &iio_const_attr_in1_index.dev_attr.attr,
- &iio_scan_el_in2.dev_attr.attr,
- &iio_const_attr_in2_index.dev_attr.attr,
- &iio_scan_el_in3.dev_attr.attr,
- &iio_const_attr_in3_index.dev_attr.attr,
- &iio_const_attr_timestamp_index.dev_attr.attr,
- &iio_scan_el_timestamp.dev_attr.attr,
- &iio_const_attr_timestamp_type.dev_attr.attr,
- &iio_dev_attr_in_type.dev_attr.attr,
- NULL,
-};
-
-static struct attribute_group ad7991_5_9_3_4_scan_el_group = {
- .name = "scan_elements",
- .attrs = ad7991_5_9_3_4_scan_el_attrs,
-};
-
-static struct attribute *ad7992_device_attrs[] = {
- &iio_dev_attr_in0_raw.dev_attr.attr,
- &iio_dev_attr_in1_raw.dev_attr.attr,
- &iio_dev_attr_name.dev_attr.attr,
- &iio_dev_attr_in_scale.dev_attr.attr,
- NULL
-};
-
-static struct attribute_group ad7992_dev_attr_group = {
- .attrs = ad7992_device_attrs,
-};
-
-static struct attribute *ad7992_scan_el_attrs[] = {
- &iio_scan_el_in0.dev_attr.attr,
- &iio_const_attr_in0_index.dev_attr.attr,
- &iio_scan_el_in1.dev_attr.attr,
- &iio_const_attr_in1_index.dev_attr.attr,
- &iio_const_attr_timestamp_index.dev_attr.attr,
- &iio_scan_el_timestamp.dev_attr.attr,
- &iio_const_attr_timestamp_type.dev_attr.attr,
- &iio_dev_attr_in_type.dev_attr.attr,
- NULL,
-};
-
-static struct attribute_group ad7992_scan_el_group = {
- .name = "scan_elements",
- .attrs = ad7992_scan_el_attrs,
-};
-
-static struct attribute *ad7997_8_device_attrs[] = {
- &iio_dev_attr_in0_raw.dev_attr.attr,
- &iio_dev_attr_in1_raw.dev_attr.attr,
- &iio_dev_attr_in2_raw.dev_attr.attr,
- &iio_dev_attr_in3_raw.dev_attr.attr,
- &iio_dev_attr_in4_raw.dev_attr.attr,
- &iio_dev_attr_in5_raw.dev_attr.attr,
- &iio_dev_attr_in6_raw.dev_attr.attr,
- &iio_dev_attr_in7_raw.dev_attr.attr,
- &iio_dev_attr_name.dev_attr.attr,
- &iio_dev_attr_in_scale.dev_attr.attr,
- NULL
-};
-
-static struct attribute_group ad7997_8_dev_attr_group = {
- .attrs = ad7997_8_device_attrs,
-};
-
-static struct attribute *ad7997_8_scan_el_attrs[] = {
- &iio_scan_el_in0.dev_attr.attr,
- &iio_const_attr_in0_index.dev_attr.attr,
- &iio_scan_el_in1.dev_attr.attr,
- &iio_const_attr_in1_index.dev_attr.attr,
- &iio_scan_el_in2.dev_attr.attr,
- &iio_const_attr_in2_index.dev_attr.attr,
- &iio_scan_el_in3.dev_attr.attr,
- &iio_const_attr_in3_index.dev_attr.attr,
- &iio_scan_el_in4.dev_attr.attr,
- &iio_const_attr_in4_index.dev_attr.attr,
- &iio_scan_el_in5.dev_attr.attr,
- &iio_const_attr_in5_index.dev_attr.attr,
- &iio_scan_el_in6.dev_attr.attr,
- &iio_const_attr_in6_index.dev_attr.attr,
- &iio_scan_el_in7.dev_attr.attr,
- &iio_const_attr_in7_index.dev_attr.attr,
- &iio_const_attr_timestamp_index.dev_attr.attr,
- &iio_scan_el_timestamp.dev_attr.attr,
- &iio_const_attr_timestamp_type.dev_attr.attr,
- &iio_dev_attr_in_type.dev_attr.attr,
- NULL,
-};
-
-static struct attribute_group ad7997_8_scan_el_group = {
- .name = "scan_elements",
- .attrs = ad7997_8_scan_el_attrs,
-};
-
-IIO_EVENT_ATTR_SH(in0_thresh_low_value,
- iio_event_ad799x,
- ad799x_read_channel_config,
- ad799x_write_channel_config,
- AD7998_DATALOW_CH1_REG);
-
-IIO_EVENT_ATTR_SH(in0_thresh_high_value,
- iio_event_ad799x,
- ad799x_read_channel_config,
- ad799x_write_channel_config,
- AD7998_DATAHIGH_CH1_REG);
-
-IIO_EVENT_ATTR_SH(in0_thresh_both_hyst_raw,
- iio_event_ad799x,
- ad799x_read_channel_config,
- ad799x_write_channel_config,
- AD7998_HYST_CH1_REG);
-
-IIO_EVENT_ATTR_SH(in1_thresh_low_value,
- iio_event_ad799x,
- ad799x_read_channel_config,
- ad799x_write_channel_config,
- AD7998_DATALOW_CH2_REG);
-
-IIO_EVENT_ATTR_SH(in1_thresh_high_value,
- iio_event_ad799x,
- ad799x_read_channel_config,
- ad799x_write_channel_config,
- AD7998_DATAHIGH_CH2_REG);
-
-IIO_EVENT_ATTR_SH(in1_thresh_both_hyst_raw,
- iio_event_ad799x,
- ad799x_read_channel_config,
- ad799x_write_channel_config,
- AD7998_HYST_CH2_REG);
-
-IIO_EVENT_ATTR_SH(in2_thresh_low_value,
- iio_event_ad799x,
- ad799x_read_channel_config,
- ad799x_write_channel_config,
- AD7998_DATALOW_CH3_REG);
-
-IIO_EVENT_ATTR_SH(in2_thresh_high_value,
- iio_event_ad799x,
- ad799x_read_channel_config,
- ad799x_write_channel_config,
- AD7998_DATAHIGH_CH3_REG);
-
-IIO_EVENT_ATTR_SH(in2_thresh_both_hyst_raw,
- iio_event_ad799x,
- ad799x_read_channel_config,
- ad799x_write_channel_config,
- AD7998_HYST_CH3_REG);
-
-IIO_EVENT_ATTR_SH(in3_thresh_low_value,
- iio_event_ad799x,
- ad799x_read_channel_config,
- ad799x_write_channel_config,
- AD7998_DATALOW_CH4_REG);
-
-IIO_EVENT_ATTR_SH(in3_thresh_high_value,
- iio_event_ad799x,
- ad799x_read_channel_config,
- ad799x_write_channel_config,
- AD7998_DATAHIGH_CH4_REG);
-
-IIO_EVENT_ATTR_SH(in3_thresh_both_hyst_raw,
- iio_event_ad799x,
- ad799x_read_channel_config,
- ad799x_write_channel_config,
- AD7998_HYST_CH4_REG);
+static IIO_DEVICE_ATTR(in3_thresh_both_hyst_raw,
+ S_IRUGO | S_IWUSR,
+ ad799x_read_channel_config,
+ ad799x_write_channel_config,
+ AD7998_HYST_CH4_REG);
static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO,
ad799x_read_frequency,
@@ -640,18 +422,18 @@
static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("15625 7812 3906 1953 976 488 244 0");
static struct attribute *ad7993_4_7_8_event_attributes[] = {
- &iio_event_attr_in0_thresh_low_value.dev_attr.attr,
- &iio_event_attr_in0_thresh_high_value.dev_attr.attr,
- &iio_event_attr_in0_thresh_both_hyst_raw.dev_attr.attr,
- &iio_event_attr_in1_thresh_low_value.dev_attr.attr,
- &iio_event_attr_in1_thresh_high_value.dev_attr.attr,
- &iio_event_attr_in1_thresh_both_hyst_raw.dev_attr.attr,
- &iio_event_attr_in2_thresh_low_value.dev_attr.attr,
- &iio_event_attr_in2_thresh_high_value.dev_attr.attr,
- &iio_event_attr_in2_thresh_both_hyst_raw.dev_attr.attr,
- &iio_event_attr_in3_thresh_low_value.dev_attr.attr,
- &iio_event_attr_in3_thresh_high_value.dev_attr.attr,
- &iio_event_attr_in3_thresh_both_hyst_raw.dev_attr.attr,
+ &iio_dev_attr_in0_thresh_low_value.dev_attr.attr,
+ &iio_dev_attr_in0_thresh_high_value.dev_attr.attr,
+ &iio_dev_attr_in0_thresh_both_hyst_raw.dev_attr.attr,
+ &iio_dev_attr_in1_thresh_low_value.dev_attr.attr,
+ &iio_dev_attr_in1_thresh_high_value.dev_attr.attr,
+ &iio_dev_attr_in1_thresh_both_hyst_raw.dev_attr.attr,
+ &iio_dev_attr_in2_thresh_low_value.dev_attr.attr,
+ &iio_dev_attr_in2_thresh_high_value.dev_attr.attr,
+ &iio_dev_attr_in2_thresh_both_hyst_raw.dev_attr.attr,
+ &iio_dev_attr_in3_thresh_low_value.dev_attr.attr,
+ &iio_dev_attr_in3_thresh_high_value.dev_attr.attr,
+ &iio_dev_attr_in3_thresh_both_hyst_raw.dev_attr.attr,
&iio_dev_attr_sampling_frequency.dev_attr.attr,
&iio_const_attr_sampling_frequency_available.dev_attr.attr,
NULL,
@@ -662,12 +444,12 @@
};
static struct attribute *ad7992_event_attributes[] = {
- &iio_event_attr_in0_thresh_low_value.dev_attr.attr,
- &iio_event_attr_in0_thresh_high_value.dev_attr.attr,
- &iio_event_attr_in0_thresh_both_hyst_raw.dev_attr.attr,
- &iio_event_attr_in1_thresh_low_value.dev_attr.attr,
- &iio_event_attr_in1_thresh_high_value.dev_attr.attr,
- &iio_event_attr_in1_thresh_both_hyst_raw.dev_attr.attr,
+ &iio_dev_attr_in0_thresh_low_value.dev_attr.attr,
+ &iio_dev_attr_in0_thresh_high_value.dev_attr.attr,
+ &iio_dev_attr_in0_thresh_both_hyst_raw.dev_attr.attr,
+ &iio_dev_attr_in1_thresh_low_value.dev_attr.attr,
+ &iio_dev_attr_in1_thresh_high_value.dev_attr.attr,
+ &iio_dev_attr_in1_thresh_both_hyst_raw.dev_attr.attr,
&iio_dev_attr_sampling_frequency.dev_attr.attr,
&iio_const_attr_sampling_frequency_available.dev_attr.attr,
NULL,
@@ -677,93 +459,192 @@
.attrs = ad7992_event_attributes,
};
+static const struct iio_info ad7991_info = {
+ .read_raw = &ad799x_read_raw,
+ .driver_module = THIS_MODULE,
+};
+
+static const struct iio_info ad7992_info = {
+ .read_raw = &ad799x_read_raw,
+ .num_interrupt_lines = 1,
+ .event_attrs = &ad7992_event_attrs_group,
+ .driver_module = THIS_MODULE,
+};
+
+static const struct iio_info ad7993_4_7_8_info = {
+ .read_raw = &ad799x_read_raw,
+ .num_interrupt_lines = 1,
+ .event_attrs = &ad7993_4_7_8_event_attrs_group,
+ .driver_module = THIS_MODULE,
+};
+
static const struct ad799x_chip_info ad799x_chip_info_tbl[] = {
[ad7991] = {
- .num_inputs = 4,
- .bits = 12,
- .sign = IIO_SCAN_EL_TYPE_UNSIGNED,
+ .channel[0] = IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 0, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 0, 0, IIO_ST('u', 12, 16, 0), 0),
+ .channel[1] = IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 1, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 1, 1, IIO_ST('u', 12, 16, 0), 0),
+ .channel[2] = IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 2, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 2, 2, IIO_ST('u', 12, 16, 0), 0),
+ .channel[3] = IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 3, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 3, 3, IIO_ST('u', 12, 16, 0), 0),
+ .channel[4] = IIO_CHAN_SOFT_TIMESTAMP(4),
+ .num_channels = 5,
.int_vref_mv = 4096,
- .dev_attrs = &ad7991_5_9_3_4_dev_attr_group,
- .scan_attrs = &ad7991_5_9_3_4_scan_el_group,
- .ad799x_set_scan_mode = ad7991_5_9_set_scan_mode,
+ .info = &ad7991_info,
},
[ad7995] = {
- .num_inputs = 4,
- .bits = 10,
- .sign = IIO_SCAN_EL_TYPE_UNSIGNED,
+ .channel[0] = IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 0, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 0, 0, IIO_ST('u', 10, 16, 0), 0),
+ .channel[1] = IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 1, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 1, 1, IIO_ST('u', 10, 16, 0), 0),
+ .channel[2] = IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 2, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 2, 2, IIO_ST('u', 10, 16, 0), 0),
+ .channel[3] = IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 3, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 3, 3, IIO_ST('u', 10, 16, 0), 0),
+ .channel[4] = IIO_CHAN_SOFT_TIMESTAMP(4),
+ .num_channels = 5,
.int_vref_mv = 1024,
- .dev_attrs = &ad7991_5_9_3_4_dev_attr_group,
- .scan_attrs = &ad7991_5_9_3_4_scan_el_group,
- .ad799x_set_scan_mode = ad7991_5_9_set_scan_mode,
+ .info = &ad7991_info,
},
[ad7999] = {
- .num_inputs = 4,
- .bits = 10,
- .sign = IIO_SCAN_EL_TYPE_UNSIGNED,
+ .channel[0] = IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 0, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 0, 0, IIO_ST('u', 10, 16, 0), 0),
+ .channel[1] = IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 1, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 1, 1, IIO_ST('u', 10, 16, 0), 0),
+ .channel[2] = IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 2, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 2, 2, IIO_ST('u', 10, 16, 0), 0),
+ .channel[3] = IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 3, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 3, 3, IIO_ST('u', 10, 16, 0), 0),
+ .channel[4] = IIO_CHAN_SOFT_TIMESTAMP(4),
+ .num_channels = 5,
.int_vref_mv = 1024,
- .dev_attrs = &ad7991_5_9_3_4_dev_attr_group,
- .scan_attrs = &ad7991_5_9_3_4_scan_el_group,
- .ad799x_set_scan_mode = ad7991_5_9_set_scan_mode,
+ .info = &ad7991_info,
},
[ad7992] = {
- .num_inputs = 2,
- .bits = 12,
- .sign = IIO_SCAN_EL_TYPE_UNSIGNED,
+ .channel[0] = IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 0, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 0, 0, IIO_ST('u', 12, 16, 0), 0),
+ .channel[1] = IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 1, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 1, 1, IIO_ST('u', 12, 16, 0), 0),
+ .channel[2] = IIO_CHAN_SOFT_TIMESTAMP(2),
+ .num_channels = 3,
.int_vref_mv = 4096,
- .monitor_mode = true,
.default_config = AD7998_ALERT_EN,
- .dev_attrs = &ad7992_dev_attr_group,
- .scan_attrs = &ad7992_scan_el_group,
- .event_attrs = &ad7992_event_attrs_group,
- .ad799x_set_scan_mode = ad7992_3_4_set_scan_mode,
+ .info = &ad7992_info,
},
[ad7993] = {
- .num_inputs = 4,
- .bits = 10,
- .sign = IIO_SCAN_EL_TYPE_UNSIGNED,
+ .channel[0] = IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 0, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 0, 0, IIO_ST('u', 10, 16, 0), 0),
+ .channel[1] = IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 1, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 1, 1, IIO_ST('u', 10, 16, 0), 0),
+ .channel[2] = IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 2, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 2, 2, IIO_ST('u', 10, 16, 0), 0),
+ .channel[3] = IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 3, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 3, 3, IIO_ST('u', 10, 16, 0), 0),
+ .channel[4] = IIO_CHAN_SOFT_TIMESTAMP(4),
+ .num_channels = 5,
.int_vref_mv = 1024,
- .monitor_mode = true,
.default_config = AD7998_ALERT_EN,
- .dev_attrs = &ad7991_5_9_3_4_dev_attr_group,
- .scan_attrs = &ad7991_5_9_3_4_scan_el_group,
- .event_attrs = &ad7993_4_7_8_event_attrs_group,
- .ad799x_set_scan_mode = ad7992_3_4_set_scan_mode,
+ .info = &ad7993_4_7_8_info,
},
[ad7994] = {
- .num_inputs = 4,
- .bits = 12,
- .sign = IIO_SCAN_EL_TYPE_UNSIGNED,
+ .channel[0] = IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 0, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 0, 0, IIO_ST('u', 12, 16, 0), 0),
+ .channel[1] = IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 1, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 1, 1, IIO_ST('u', 12, 16, 0), 0),
+ .channel[2] = IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 2, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 2, 2, IIO_ST('u', 12, 16, 0), 0),
+ .channel[3] = IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 3, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 3, 3, IIO_ST('u', 12, 16, 0), 0),
+ .channel[4] = IIO_CHAN_SOFT_TIMESTAMP(4),
+ .num_channels = 5,
.int_vref_mv = 4096,
- .monitor_mode = true,
.default_config = AD7998_ALERT_EN,
- .dev_attrs = &ad7991_5_9_3_4_dev_attr_group,
- .scan_attrs = &ad7991_5_9_3_4_scan_el_group,
- .event_attrs = &ad7993_4_7_8_event_attrs_group,
- .ad799x_set_scan_mode = ad7992_3_4_set_scan_mode,
+ .info = &ad7993_4_7_8_info,
},
[ad7997] = {
- .num_inputs = 8,
- .bits = 10,
- .sign = IIO_SCAN_EL_TYPE_UNSIGNED,
+ .channel[0] = IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 0, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 0, 0, IIO_ST('u', 10, 16, 0), 0),
+ .channel[1] = IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 1, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 1, 1, IIO_ST('u', 10, 16, 0), 0),
+ .channel[2] = IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 2, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 2, 2, IIO_ST('u', 10, 16, 0), 0),
+ .channel[3] = IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 3, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 3, 3, IIO_ST('u', 10, 16, 0), 0),
+ .channel[4] = IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 4, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 4, 4, IIO_ST('u', 10, 16, 0), 0),
+ .channel[5] = IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 5, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 5, 5, IIO_ST('u', 10, 16, 0), 0),
+ .channel[6] = IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 6, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 6, 6, IIO_ST('u', 10, 16, 0), 0),
+ .channel[7] = IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 7, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 7, 7, IIO_ST('u', 10, 16, 0), 0),
+ .channel[8] = IIO_CHAN_SOFT_TIMESTAMP(8),
+ .num_channels = 9,
.int_vref_mv = 1024,
- .monitor_mode = true,
.default_config = AD7998_ALERT_EN,
- .dev_attrs = &ad7997_8_dev_attr_group,
- .scan_attrs = &ad7997_8_scan_el_group,
- .event_attrs = &ad7993_4_7_8_event_attrs_group,
- .ad799x_set_scan_mode = ad7997_8_set_scan_mode,
+ .info = &ad7993_4_7_8_info,
},
[ad7998] = {
- .num_inputs = 8,
- .bits = 12,
- .sign = IIO_SCAN_EL_TYPE_UNSIGNED,
+ .channel[0] = IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 0, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 0, 0, IIO_ST('u', 12, 16, 0), 0),
+ .channel[1] = IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 1, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 1, 1, IIO_ST('u', 12, 16, 0), 0),
+ .channel[2] = IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 2, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 2, 2, IIO_ST('u', 12, 16, 0), 0),
+ .channel[3] = IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 3, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 3, 3, IIO_ST('u', 12, 16, 0), 0),
+ .channel[4] = IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 4, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 4, 4, IIO_ST('u', 12, 16, 0), 0),
+ .channel[5] = IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 5, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 5, 5, IIO_ST('u', 12, 16, 0), 0),
+ .channel[6] = IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 6, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 6, 6, IIO_ST('u', 12, 16, 0), 0),
+ .channel[7] = IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 7, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 7, 7, IIO_ST('u', 12, 16, 0), 0),
+ .channel[8] = IIO_CHAN_SOFT_TIMESTAMP(8),
+ .num_channels = 9,
.int_vref_mv = 4096,
- .monitor_mode = true,
.default_config = AD7998_ALERT_EN,
- .dev_attrs = &ad7997_8_dev_attr_group,
- .scan_attrs = &ad7997_8_scan_el_group,
- .event_attrs = &ad7993_4_7_8_event_attrs_group,
- .ad799x_set_scan_mode = ad7997_8_set_scan_mode,
+ .info = &ad7993_4_7_8_info,
},
};
@@ -772,16 +653,16 @@
{
int ret, regdone = 0;
struct ad799x_platform_data *pdata = client->dev.platform_data;
- struct ad799x_state *st = kzalloc(sizeof(*st), GFP_KERNEL);
- if (st == NULL) {
- ret = -ENOMEM;
- goto error_ret;
- }
+ struct ad799x_state *st;
+ struct iio_dev *indio_dev = iio_allocate_device(sizeof(*st));
+ if (indio_dev == NULL)
+ return -ENOMEM;
+
+ st = iio_priv(indio_dev);
/* this is only used for device removal purposes */
- i2c_set_clientdata(client, st);
+ i2c_set_clientdata(client, indio_dev);
- atomic_set(&st->protect_ring, 0);
st->id = id->driver_data;
st->chip_info = &ad799x_chip_info_tbl[st->id];
st->config = st->chip_info->default_config;
@@ -801,94 +682,76 @@
}
st->client = client;
- st->indio_dev = iio_allocate_device();
- if (st->indio_dev == NULL) {
- ret = -ENOMEM;
+ indio_dev->dev.parent = &client->dev;
+ indio_dev->name = id->name;
+ indio_dev->info = st->chip_info->info;
+ indio_dev->name = id->name;
+ indio_dev->dev_data = (void *)(st);
+
+ indio_dev->modes = INDIO_DIRECT_MODE;
+ indio_dev->channels = st->chip_info->channel;
+ indio_dev->num_channels = st->chip_info->num_channels;
+
+ ret = ad799x_register_ring_funcs_and_init(indio_dev);
+ if (ret)
goto error_disable_reg;
- }
- /* Estabilish that the iio_dev is a child of the i2c device */
- st->indio_dev->dev.parent = &client->dev;
- st->indio_dev->attrs = st->chip_info->dev_attrs;
- st->indio_dev->event_attrs = st->chip_info->event_attrs;
-
- st->indio_dev->dev_data = (void *)(st);
- st->indio_dev->driver_module = THIS_MODULE;
- st->indio_dev->modes = INDIO_DIRECT_MODE;
- st->indio_dev->num_interrupt_lines = 1;
-
- ret = ad799x_set_scan_mode(st, 0);
- if (ret)
- goto error_free_device;
-
- ret = ad799x_register_ring_funcs_and_init(st->indio_dev);
- if (ret)
- goto error_free_device;
-
- ret = iio_device_register(st->indio_dev);
+ ret = iio_device_register(indio_dev);
if (ret)
goto error_cleanup_ring;
regdone = 1;
- ret = iio_ring_buffer_register(st->indio_dev->ring, 0);
+ ret = iio_ring_buffer_register_ex(indio_dev->ring, 0,
+ indio_dev->channels,
+ indio_dev->num_channels);
if (ret)
goto error_cleanup_ring;
- if (client->irq > 0 && st->chip_info->monitor_mode) {
- INIT_WORK(&st->work_thresh, ad799x_interrupt_bh);
-
- ret = iio_register_interrupt_line(client->irq,
- st->indio_dev,
- 0,
- IRQF_TRIGGER_FALLING,
- client->name);
+ if (client->irq > 0) {
+ ret = request_threaded_irq(client->irq,
+ NULL,
+ ad799x_event_handler,
+ IRQF_TRIGGER_FALLING |
+ IRQF_ONESHOT,
+ client->name,
+ indio_dev);
if (ret)
goto error_cleanup_ring;
-
- /*
- * The event handler list element refer to iio_event_ad799x.
- * All event attributes bind to the same event handler.
- * So, only register event handler once.
- */
- iio_add_event_to_list(&iio_event_ad799x,
- &st->indio_dev->interrupts[0]->ev_list);
}
return 0;
+
error_cleanup_ring:
- ad799x_ring_cleanup(st->indio_dev);
-error_free_device:
- if (!regdone)
- iio_free_device(st->indio_dev);
- else
- iio_device_unregister(st->indio_dev);
+ ad799x_ring_cleanup(indio_dev);
error_disable_reg:
if (!IS_ERR(st->reg))
regulator_disable(st->reg);
error_put_reg:
if (!IS_ERR(st->reg))
regulator_put(st->reg);
- kfree(st);
-error_ret:
+ if (regdone)
+ iio_device_unregister(indio_dev);
+ else
+ iio_free_device(indio_dev);
+
return ret;
}
static __devexit int ad799x_remove(struct i2c_client *client)
{
- struct ad799x_state *st = i2c_get_clientdata(client);
- struct iio_dev *indio_dev = st->indio_dev;
+ struct iio_dev *indio_dev = i2c_get_clientdata(client);
+ struct ad799x_state *st = iio_priv(indio_dev);
- if (client->irq > 0 && st->chip_info->monitor_mode)
- iio_unregister_interrupt_line(indio_dev, 0);
+ if (client->irq > 0)
+ free_irq(client->irq, indio_dev);
iio_ring_buffer_unregister(indio_dev->ring);
ad799x_ring_cleanup(indio_dev);
- iio_device_unregister(indio_dev);
if (!IS_ERR(st->reg)) {
regulator_disable(st->reg);
regulator_put(st->reg);
}
- kfree(st);
+ iio_device_unregister(indio_dev);
return 0;
}
diff --git a/drivers/staging/iio/adc/ad799x_ring.c b/drivers/staging/iio/adc/ad799x_ring.c
index 0875a7e..1ae8857 100644
--- a/drivers/staging/iio/adc/ad799x_ring.c
+++ b/drivers/staging/iio/adc/ad799x_ring.c
@@ -10,7 +10,6 @@
*/
#include <linux/interrupt.h>
-#include <linux/workqueue.h>
#include <linux/device.h>
#include <linux/slab.h>
#include <linux/kernel.h>
@@ -29,7 +28,7 @@
int ad799x_single_channel_from_ring(struct ad799x_state *st, long mask)
{
- struct iio_ring_buffer *ring = st->indio_dev->ring;
+ struct iio_ring_buffer *ring = iio_priv_to_dev(st)->ring;
int count = 0, ret;
u16 *ring_data;
@@ -38,12 +37,13 @@
goto error_ret;
}
- ring_data = kmalloc(ring->access.get_bytes_per_datum(ring), GFP_KERNEL);
+ ring_data = kmalloc(ring->access->get_bytes_per_datum(ring),
+ GFP_KERNEL);
if (ring_data == NULL) {
ret = -ENOMEM;
goto error_ret;
}
- ret = ring->access.read_last(ring, (u8 *) ring_data);
+ ret = ring->access->read_last(ring, (u8 *) ring_data);
if (ret)
goto error_free_ring_data;
/* Need a count of channels prior to this one */
@@ -72,7 +72,7 @@
static int ad799x_ring_preenable(struct iio_dev *indio_dev)
{
struct iio_ring_buffer *ring = indio_dev->ring;
- struct ad799x_state *st = indio_dev->dev_data;
+ struct ad799x_state *st = iio_dev_get_devdata(indio_dev);
/*
* Need to figure out the current mode based upon the requested
@@ -80,7 +80,7 @@
*/
if (st->id == ad7997 || st->id == ad7998)
- ad799x_set_scan_mode(st, ring->scan_mask);
+ ad7997_8_set_scan_mode(st, ring->scan_mask);
st->d_size = ring->scan_count * 2;
@@ -91,56 +91,34 @@
st->d_size += sizeof(s64) - (st->d_size % sizeof(s64));
}
- if (indio_dev->ring->access.set_bytes_per_datum)
- indio_dev->ring->access.set_bytes_per_datum(indio_dev->ring,
+ if (indio_dev->ring->access->set_bytes_per_datum)
+ indio_dev->ring->access->set_bytes_per_datum(indio_dev->ring,
st->d_size);
return 0;
}
/**
- * ad799x_poll_func_th() th of trigger launched polling to ring buffer
- *
- * As sampling only occurs on i2c comms occurring, leave timestamping until
- * then. Some triggers will generate their own time stamp. Currently
- * there is no way of notifying them when no one cares.
- **/
-static void ad799x_poll_func_th(struct iio_dev *indio_dev, s64 time)
-{
- struct ad799x_state *st = indio_dev->dev_data;
-
- schedule_work(&st->poll_work);
-
- return;
-}
-/**
- * ad799x_poll_bh_to_ring() bh of trigger launched polling to ring buffer
- * @work_s: the work struct through which this was scheduled
+ * ad799x_trigger_handler() bh of trigger launched polling to ring buffer
*
* Currently there is no option in this driver to disable the saving of
* timestamps within the ring.
- * I think the one copy of this at a time was to avoid problems if the
- * trigger was set far too high and the reads then locked up the computer.
**/
-static void ad799x_poll_bh_to_ring(struct work_struct *work_s)
+
+static irqreturn_t ad799x_trigger_handler(int irq, void *p)
{
- struct ad799x_state *st = container_of(work_s, struct ad799x_state,
- poll_work);
- struct iio_dev *indio_dev = st->indio_dev;
+ struct iio_poll_func *pf = p;
+ struct iio_dev *indio_dev = pf->private_data;
+ struct ad799x_state *st = iio_dev_get_devdata(indio_dev);
struct iio_ring_buffer *ring = indio_dev->ring;
- struct iio_sw_ring_buffer *ring_sw = iio_to_sw_ring(indio_dev->ring);
s64 time_ns;
__u8 *rxbuf;
int b_sent;
u8 cmd;
- /* Ensure only one copy of this function running at a time */
- if (atomic_inc_return(&st->protect_ring) > 1)
- return;
-
rxbuf = kmalloc(st->d_size, GFP_KERNEL);
if (rxbuf == NULL)
- return;
+ goto out;
switch (st->id) {
case ad7991:
@@ -173,16 +151,25 @@
memcpy(rxbuf + st->d_size - sizeof(s64),
&time_ns, sizeof(time_ns));
- ring->access.store_to(&ring_sw->buf, rxbuf, time_ns);
+ ring->access->store_to(indio_dev->ring, rxbuf, time_ns);
done:
kfree(rxbuf);
- atomic_dec(&st->protect_ring);
+ if (b_sent < 0)
+ return b_sent;
+out:
+ iio_trigger_notify_done(indio_dev->trig);
+
+ return IRQ_HANDLED;
}
+static const struct iio_ring_setup_ops ad799x_buf_setup_ops = {
+ .preenable = &ad799x_ring_preenable,
+ .postenable = &iio_triggered_ring_postenable,
+ .predisable = &iio_triggered_ring_predisable,
+};
int ad799x_register_ring_funcs_and_init(struct iio_dev *indio_dev)
{
- struct ad799x_state *st = indio_dev->dev_data;
int ret = 0;
indio_dev->ring = iio_sw_rb_allocate(indio_dev);
@@ -191,25 +178,27 @@
goto error_ret;
}
/* Effectively select the ring buffer implementation */
- iio_ring_sw_register_funcs(&st->indio_dev->ring->access);
- ret = iio_alloc_pollfunc(indio_dev, NULL, &ad799x_poll_func_th);
- if (ret)
+ indio_dev->ring->access = &ring_sw_access_funcs;
+ indio_dev->pollfunc = iio_alloc_pollfunc(NULL,
+ &ad799x_trigger_handler,
+ IRQF_ONESHOT,
+ indio_dev,
+ "%s_consumer%d",
+ indio_dev->name,
+ indio_dev->id);
+ if (indio_dev->pollfunc == NULL) {
+ ret = -ENOMEM;
goto error_deallocate_sw_rb;
+ }
/* Ring buffer functions - here trigger setup related */
-
- indio_dev->ring->preenable = &ad799x_ring_preenable;
- indio_dev->ring->postenable = &iio_triggered_ring_postenable;
- indio_dev->ring->predisable = &iio_triggered_ring_predisable;
+ indio_dev->ring->setup_ops = &ad799x_buf_setup_ops;
indio_dev->ring->scan_timestamp = true;
- INIT_WORK(&st->poll_work, &ad799x_poll_bh_to_ring);
-
- indio_dev->ring->scan_el_attrs = st->chip_info->scan_attrs;
-
/* Flag that polled ring buffering is possible */
indio_dev->modes |= INDIO_RING_TRIGGERED;
return 0;
+
error_deallocate_sw_rb:
iio_sw_rb_free(indio_dev->ring);
error_ret:
@@ -224,6 +213,6 @@
iio_trigger_dettach_poll_func(indio_dev->trig,
indio_dev->pollfunc);
}
- kfree(indio_dev->pollfunc);
+ iio_dealloc_pollfunc(indio_dev->pollfunc);
iio_sw_rb_free(indio_dev->ring);
}
diff --git a/drivers/staging/iio/adc/adt7310.c b/drivers/staging/iio/adc/adt7310.c
index 771a409..68eca0b 100644
--- a/drivers/staging/iio/adc/adt7310.c
+++ b/drivers/staging/iio/adc/adt7310.c
@@ -7,15 +7,12 @@
*/
#include <linux/interrupt.h>
-#include <linux/gpio.h>
-#include <linux/workqueue.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
#include <linux/list.h>
#include <linux/spi/spi.h>
-#include <linux/rtc.h>
#include "../iio.h"
#include "../sysfs.h"
@@ -82,11 +79,8 @@
*/
struct adt7310_chip_info {
- const char *name;
struct spi_device *spi_dev;
struct iio_dev *indio_dev;
- struct work_struct thresh_work;
- s64 last_timestamp;
u8 config;
};
@@ -380,24 +374,12 @@
static IIO_DEVICE_ATTR(value, S_IRUGO, adt7310_show_value, NULL, 0);
-static ssize_t adt7310_show_name(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- struct iio_dev *dev_info = dev_get_drvdata(dev);
- struct adt7310_chip_info *chip = dev_info->dev_data;
- return sprintf(buf, "%s\n", chip->name);
-}
-
-static IIO_DEVICE_ATTR(name, S_IRUGO, adt7310_show_name, NULL, 0);
-
static struct attribute *adt7310_attributes[] = {
&iio_dev_attr_available_modes.dev_attr.attr,
&iio_dev_attr_mode.dev_attr.attr,
&iio_dev_attr_resolution.dev_attr.attr,
&iio_dev_attr_id.dev_attr.attr,
&iio_dev_attr_value.dev_attr.attr,
- &iio_dev_attr_name.dev_attr.attr,
NULL,
};
@@ -405,53 +387,39 @@
.attrs = adt7310_attributes,
};
-/*
- * temperature bound events
- */
-
-#define IIO_EVENT_CODE_ADT7310_ABOVE_ALARM IIO_BUFFER_EVENT_CODE(0)
-#define IIO_EVENT_CODE_ADT7310_BELLOW_ALARM IIO_BUFFER_EVENT_CODE(1)
-#define IIO_EVENT_CODE_ADT7310_ABOVE_CRIT IIO_BUFFER_EVENT_CODE(2)
-
-static void adt7310_interrupt_bh(struct work_struct *work_s)
+static irqreturn_t adt7310_event_handler(int irq, void *private)
{
- struct adt7310_chip_info *chip =
- container_of(work_s, struct adt7310_chip_info, thresh_work);
+ struct iio_dev *indio_dev = private;
+ struct adt7310_chip_info *chip = iio_dev_get_devdata(indio_dev);
+ s64 timestamp = iio_get_time_ns();
u8 status;
+ int ret;
- if (adt7310_spi_read_byte(chip, ADT7310_STATUS, &status))
- return;
+ ret = adt7310_spi_read_byte(chip, ADT7310_STATUS, &status);
+ if (ret)
+ return ret;
if (status & ADT7310_STAT_T_HIGH)
- iio_push_event(chip->indio_dev, 0,
- IIO_EVENT_CODE_ADT7310_ABOVE_ALARM,
- chip->last_timestamp);
+ iio_push_event(indio_dev, 0,
+ IIO_UNMOD_EVENT_CODE(IIO_TEMP, 0,
+ IIO_EV_TYPE_THRESH,
+ IIO_EV_DIR_RISING),
+ timestamp);
if (status & ADT7310_STAT_T_LOW)
- iio_push_event(chip->indio_dev, 0,
- IIO_EVENT_CODE_ADT7310_BELLOW_ALARM,
- chip->last_timestamp);
+ iio_push_event(indio_dev, 0,
+ IIO_UNMOD_EVENT_CODE(IIO_TEMP, 0,
+ IIO_EV_TYPE_THRESH,
+ IIO_EV_DIR_FALLING),
+ timestamp);
if (status & ADT7310_STAT_T_CRIT)
- iio_push_event(chip->indio_dev, 0,
- IIO_EVENT_CODE_ADT7310_ABOVE_CRIT,
- chip->last_timestamp);
+ iio_push_event(indio_dev, 0,
+ IIO_UNMOD_EVENT_CODE(IIO_TEMP, 0,
+ IIO_EV_TYPE_THRESH,
+ IIO_EV_DIR_RISING),
+ timestamp);
+ return IRQ_HANDLED;
}
-static int adt7310_interrupt(struct iio_dev *dev_info,
- int index,
- s64 timestamp,
- int no_test)
-{
- struct adt7310_chip_info *chip = dev_info->dev_data;
-
- chip->last_timestamp = timestamp;
- schedule_work(&chip->thresh_work);
-
- return 0;
-}
-
-IIO_EVENT_SH(adt7310, &adt7310_interrupt);
-IIO_EVENT_SH(adt7310_ct, &adt7310_interrupt);
-
static ssize_t adt7310_show_event_mode(struct device *dev,
struct device_attribute *attr,
char *buf)
@@ -729,49 +697,62 @@
return len;
}
-IIO_EVENT_ATTR_SH(event_mode, iio_event_adt7310,
- adt7310_show_event_mode, adt7310_set_event_mode, 0);
-IIO_EVENT_ATTR_SH(available_event_modes, iio_event_adt7310,
- adt7310_show_available_event_modes, NULL, 0);
-IIO_EVENT_ATTR_SH(fault_queue, iio_event_adt7310,
- adt7310_show_fault_queue, adt7310_set_fault_queue, 0);
-IIO_EVENT_ATTR_SH(t_alarm_high, iio_event_adt7310,
- adt7310_show_t_alarm_high, adt7310_set_t_alarm_high, 0);
-IIO_EVENT_ATTR_SH(t_alarm_low, iio_event_adt7310,
- adt7310_show_t_alarm_low, adt7310_set_t_alarm_low, 0);
-IIO_EVENT_ATTR_SH(t_crit, iio_event_adt7310_ct,
- adt7310_show_t_crit, adt7310_set_t_crit, 0);
-IIO_EVENT_ATTR_SH(t_hyst, iio_event_adt7310,
- adt7310_show_t_hyst, adt7310_set_t_hyst, 0);
+static IIO_DEVICE_ATTR(event_mode,
+ S_IRUGO | S_IWUSR,
+ adt7310_show_event_mode, adt7310_set_event_mode, 0);
+static IIO_DEVICE_ATTR(available_event_modes,
+ S_IRUGO | S_IWUSR,
+ adt7310_show_available_event_modes, NULL, 0);
+static IIO_DEVICE_ATTR(fault_queue,
+ S_IRUGO | S_IWUSR,
+ adt7310_show_fault_queue, adt7310_set_fault_queue, 0);
+static IIO_DEVICE_ATTR(t_alarm_high,
+ S_IRUGO | S_IWUSR,
+ adt7310_show_t_alarm_high, adt7310_set_t_alarm_high, 0);
+static IIO_DEVICE_ATTR(t_alarm_low,
+ S_IRUGO | S_IWUSR,
+ adt7310_show_t_alarm_low, adt7310_set_t_alarm_low, 0);
+static IIO_DEVICE_ATTR(t_crit,
+ S_IRUGO | S_IWUSR,
+ adt7310_show_t_crit, adt7310_set_t_crit, 0);
+static IIO_DEVICE_ATTR(t_hyst,
+ S_IRUGO | S_IWUSR,
+ adt7310_show_t_hyst, adt7310_set_t_hyst, 0);
static struct attribute *adt7310_event_int_attributes[] = {
- &iio_event_attr_event_mode.dev_attr.attr,
- &iio_event_attr_available_event_modes.dev_attr.attr,
- &iio_event_attr_fault_queue.dev_attr.attr,
- &iio_event_attr_t_alarm_high.dev_attr.attr,
- &iio_event_attr_t_alarm_low.dev_attr.attr,
- &iio_event_attr_t_hyst.dev_attr.attr,
+ &iio_dev_attr_event_mode.dev_attr.attr,
+ &iio_dev_attr_available_event_modes.dev_attr.attr,
+ &iio_dev_attr_fault_queue.dev_attr.attr,
+ &iio_dev_attr_t_alarm_high.dev_attr.attr,
+ &iio_dev_attr_t_alarm_low.dev_attr.attr,
+ &iio_dev_attr_t_hyst.dev_attr.attr,
NULL,
};
static struct attribute *adt7310_event_ct_attributes[] = {
- &iio_event_attr_event_mode.dev_attr.attr,
- &iio_event_attr_available_event_modes.dev_attr.attr,
- &iio_event_attr_fault_queue.dev_attr.attr,
- &iio_event_attr_t_crit.dev_attr.attr,
- &iio_event_attr_t_hyst.dev_attr.attr,
+ &iio_dev_attr_event_mode.dev_attr.attr,
+ &iio_dev_attr_available_event_modes.dev_attr.attr,
+ &iio_dev_attr_fault_queue.dev_attr.attr,
+ &iio_dev_attr_t_crit.dev_attr.attr,
+ &iio_dev_attr_t_hyst.dev_attr.attr,
NULL,
};
static struct attribute_group adt7310_event_attribute_group[ADT7310_IRQS] = {
{
.attrs = adt7310_event_int_attributes,
- },
- {
+ }, {
.attrs = adt7310_event_ct_attributes,
}
};
+static const struct iio_info adt7310_info = {
+ .attrs = &adt7310_attribute_group,
+ .num_interrupt_lines = ADT7310_IRQS,
+ .event_attrs = adt7310_event_attribute_group,
+ .driver_module = THIS_MODULE,
+};
+
/*
* device probe and remove
*/
@@ -792,20 +773,17 @@
dev_set_drvdata(&spi_dev->dev, chip);
chip->spi_dev = spi_dev;
- chip->name = spi_dev->modalias;
- chip->indio_dev = iio_allocate_device();
+ chip->indio_dev = iio_allocate_device(0);
if (chip->indio_dev == NULL) {
ret = -ENOMEM;
goto error_free_chip;
}
chip->indio_dev->dev.parent = &spi_dev->dev;
- chip->indio_dev->attrs = &adt7310_attribute_group;
- chip->indio_dev->event_attrs = adt7310_event_attribute_group;
+ chip->indio_dev->name = spi_get_device_id(spi_dev)->name;
+ chip->indio_dev->info = &adt7310_info;
chip->indio_dev->dev_data = (void *)chip;
- chip->indio_dev->driver_module = THIS_MODULE;
- chip->indio_dev->num_interrupt_lines = ADT7310_IRQS;
chip->indio_dev->modes = INDIO_DIRECT_MODE;
ret = iio_device_register(chip->indio_dev);
@@ -818,45 +796,29 @@
irq_flags = adt7310_platform_data[2];
else
irq_flags = IRQF_TRIGGER_LOW;
- ret = iio_register_interrupt_line(spi_dev->irq,
- chip->indio_dev,
- 0,
- irq_flags,
- chip->name);
+ ret = request_threaded_irq(spi_dev->irq,
+ NULL,
+ &adt7310_event_handler,
+ irq_flags,
+ chip->indio_dev->name,
+ chip->indio_dev);
if (ret)
goto error_unreg_dev;
-
- /*
- * The event handler list element refer to iio_event_adt7310.
- * All event attributes bind to the same event handler.
- * One event handler can only be added to one event list.
- */
- iio_add_event_to_list(&iio_event_adt7310,
- &chip->indio_dev->interrupts[0]->ev_list);
}
/* INT bound temperature alarm event. line 1 */
if (adt7310_platform_data[0]) {
- ret = iio_register_interrupt_line(adt7310_platform_data[0],
- chip->indio_dev,
- 1,
- adt7310_platform_data[1],
- chip->name);
+ ret = request_threaded_irq(adt7310_platform_data[0],
+ NULL,
+ &adt7310_event_handler,
+ adt7310_platform_data[1],
+ chip->indio_dev->name,
+ chip->indio_dev);
if (ret)
goto error_unreg_ct_irq;
-
- /*
- * The event handler list element refer to iio_event_adt7310.
- * All event attributes bind to the same event handler.
- * One event handler can only be added to one event list.
- */
- iio_add_event_to_list(&iio_event_adt7310_ct,
- &chip->indio_dev->interrupts[1]->ev_list);
}
if (spi_dev->irq && adt7310_platform_data[0]) {
- INIT_WORK(&chip->thresh_work, adt7310_interrupt_bh);
-
ret = adt7310_spi_read_byte(chip, ADT7310_CONFIG, &chip->config);
if (ret) {
ret = -EIO;
@@ -879,14 +841,14 @@
}
dev_info(&spi_dev->dev, "%s temperature sensor registered.\n",
- chip->name);
+ chip->indio_dev->name);
return 0;
error_unreg_int_irq:
- iio_unregister_interrupt_line(chip->indio_dev, 1);
+ free_irq(adt7310_platform_data[0], chip->indio_dev);
error_unreg_ct_irq:
- iio_unregister_interrupt_line(chip->indio_dev, 0);
+ free_irq(spi_dev->irq, chip->indio_dev);
error_unreg_dev:
iio_device_unregister(chip->indio_dev);
error_free_dev:
@@ -905,9 +867,9 @@
dev_set_drvdata(&spi_dev->dev, NULL);
if (adt7310_platform_data[0])
- iio_unregister_interrupt_line(indio_dev, 1);
+ free_irq(adt7310_platform_data[0], chip->indio_dev);
if (spi_dev->irq)
- iio_unregister_interrupt_line(indio_dev, 0);
+ free_irq(spi_dev->irq, chip->indio_dev);
iio_device_unregister(indio_dev);
iio_free_device(chip->indio_dev);
kfree(chip);
diff --git a/drivers/staging/iio/adc/adt7410.c b/drivers/staging/iio/adc/adt7410.c
index c345f27..c40a84f 100644
--- a/drivers/staging/iio/adc/adt7410.c
+++ b/drivers/staging/iio/adc/adt7410.c
@@ -7,15 +7,12 @@
*/
#include <linux/interrupt.h>
-#include <linux/gpio.h>
-#include <linux/workqueue.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
#include <linux/list.h>
#include <linux/i2c.h>
-#include <linux/rtc.h>
#include "../iio.h"
#include "../sysfs.h"
@@ -77,11 +74,8 @@
*/
struct adt7410_chip_info {
- const char *name;
struct i2c_client *client;
struct iio_dev *indio_dev;
- struct work_struct thresh_work;
- s64 last_timestamp;
u8 config;
};
@@ -348,24 +342,12 @@
static IIO_DEVICE_ATTR(value, S_IRUGO, adt7410_show_value, NULL, 0);
-static ssize_t adt7410_show_name(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- struct iio_dev *dev_info = dev_get_drvdata(dev);
- struct adt7410_chip_info *chip = dev_info->dev_data;
- return sprintf(buf, "%s\n", chip->name);
-}
-
-static IIO_DEVICE_ATTR(name, S_IRUGO, adt7410_show_name, NULL, 0);
-
static struct attribute *adt7410_attributes[] = {
&iio_dev_attr_available_modes.dev_attr.attr,
&iio_dev_attr_mode.dev_attr.attr,
&iio_dev_attr_resolution.dev_attr.attr,
&iio_dev_attr_id.dev_attr.attr,
&iio_dev_attr_value.dev_attr.attr,
- &iio_dev_attr_name.dev_attr.attr,
NULL,
};
@@ -373,55 +355,38 @@
.attrs = adt7410_attributes,
};
-/*
- * temperature bound events
- */
-
-#define IIO_EVENT_CODE_ADT7410_ABOVE_ALARM IIO_BUFFER_EVENT_CODE(0)
-#define IIO_EVENT_CODE_ADT7410_BELLOW_ALARM IIO_BUFFER_EVENT_CODE(1)
-#define IIO_EVENT_CODE_ADT7410_ABOVE_CRIT IIO_BUFFER_EVENT_CODE(2)
-
-static void adt7410_interrupt_bh(struct work_struct *work_s)
+static irqreturn_t adt7410_event_handler(int irq, void *private)
{
- struct adt7410_chip_info *chip =
- container_of(work_s, struct adt7410_chip_info, thresh_work);
+ struct iio_dev *indio_dev = private;
+ struct adt7410_chip_info *chip = iio_dev_get_devdata(indio_dev);
+ s64 timestamp = iio_get_time_ns();
u8 status;
if (adt7410_i2c_read_byte(chip, ADT7410_STATUS, &status))
- return;
-
- enable_irq(chip->client->irq);
+ return IRQ_HANDLED;
if (status & ADT7410_STAT_T_HIGH)
- iio_push_event(chip->indio_dev, 0,
- IIO_EVENT_CODE_ADT7410_ABOVE_ALARM,
- chip->last_timestamp);
+ iio_push_event(indio_dev, 0,
+ IIO_UNMOD_EVENT_CODE(IIO_TEMP, 0,
+ IIO_EV_TYPE_THRESH,
+ IIO_EV_DIR_RISING),
+ timestamp);
if (status & ADT7410_STAT_T_LOW)
- iio_push_event(chip->indio_dev, 0,
- IIO_EVENT_CODE_ADT7410_BELLOW_ALARM,
- chip->last_timestamp);
+ iio_push_event(indio_dev, 0,
+ IIO_UNMOD_EVENT_CODE(IIO_TEMP, 0,
+ IIO_EV_TYPE_THRESH,
+ IIO_EV_DIR_FALLING),
+ timestamp);
if (status & ADT7410_STAT_T_CRIT)
- iio_push_event(chip->indio_dev, 0,
- IIO_EVENT_CODE_ADT7410_ABOVE_CRIT,
- chip->last_timestamp);
+ iio_push_event(indio_dev, 0,
+ IIO_UNMOD_EVENT_CODE(IIO_TEMP, 0,
+ IIO_EV_TYPE_THRESH,
+ IIO_EV_DIR_RISING),
+ timestamp);
+
+ return IRQ_HANDLED;
}
-static int adt7410_interrupt(struct iio_dev *dev_info,
- int index,
- s64 timestamp,
- int no_test)
-{
- struct adt7410_chip_info *chip = dev_info->dev_data;
-
- chip->last_timestamp = timestamp;
- schedule_work(&chip->thresh_work);
-
- return 0;
-}
-
-IIO_EVENT_SH(adt7410, &adt7410_interrupt);
-IIO_EVENT_SH(adt7410_ct, &adt7410_interrupt);
-
static ssize_t adt7410_show_event_mode(struct device *dev,
struct device_attribute *attr,
char *buf)
@@ -699,49 +664,62 @@
return ret;
}
-IIO_EVENT_ATTR_SH(event_mode, iio_event_adt7410,
- adt7410_show_event_mode, adt7410_set_event_mode, 0);
-IIO_EVENT_ATTR_SH(available_event_modes, iio_event_adt7410,
- adt7410_show_available_event_modes, NULL, 0);
-IIO_EVENT_ATTR_SH(fault_queue, iio_event_adt7410,
- adt7410_show_fault_queue, adt7410_set_fault_queue, 0);
-IIO_EVENT_ATTR_SH(t_alarm_high, iio_event_adt7410,
- adt7410_show_t_alarm_high, adt7410_set_t_alarm_high, 0);
-IIO_EVENT_ATTR_SH(t_alarm_low, iio_event_adt7410,
- adt7410_show_t_alarm_low, adt7410_set_t_alarm_low, 0);
-IIO_EVENT_ATTR_SH(t_crit, iio_event_adt7410_ct,
- adt7410_show_t_crit, adt7410_set_t_crit, 0);
-IIO_EVENT_ATTR_SH(t_hyst, iio_event_adt7410,
- adt7410_show_t_hyst, adt7410_set_t_hyst, 0);
+static IIO_DEVICE_ATTR(event_mode,
+ S_IRUGO | S_IWUSR,
+ adt7410_show_event_mode, adt7410_set_event_mode, 0);
+static IIO_DEVICE_ATTR(available_event_modes,
+ S_IRUGO,
+ adt7410_show_available_event_modes, NULL, 0);
+static IIO_DEVICE_ATTR(fault_queue,
+ S_IRUGO | S_IWUSR,
+ adt7410_show_fault_queue, adt7410_set_fault_queue, 0);
+static IIO_DEVICE_ATTR(t_alarm_high,
+ S_IRUGO | S_IWUSR,
+ adt7410_show_t_alarm_high, adt7410_set_t_alarm_high, 0);
+static IIO_DEVICE_ATTR(t_alarm_low,
+ S_IRUGO | S_IWUSR,
+ adt7410_show_t_alarm_low, adt7410_set_t_alarm_low, 0);
+static IIO_DEVICE_ATTR(t_crit,
+ S_IRUGO | S_IWUSR,
+ adt7410_show_t_crit, adt7410_set_t_crit, 0);
+static IIO_DEVICE_ATTR(t_hyst,
+ S_IRUGO | S_IWUSR,
+ adt7410_show_t_hyst, adt7410_set_t_hyst, 0);
static struct attribute *adt7410_event_int_attributes[] = {
- &iio_event_attr_event_mode.dev_attr.attr,
- &iio_event_attr_available_event_modes.dev_attr.attr,
- &iio_event_attr_fault_queue.dev_attr.attr,
- &iio_event_attr_t_alarm_high.dev_attr.attr,
- &iio_event_attr_t_alarm_low.dev_attr.attr,
- &iio_event_attr_t_hyst.dev_attr.attr,
+ &iio_dev_attr_event_mode.dev_attr.attr,
+ &iio_dev_attr_available_event_modes.dev_attr.attr,
+ &iio_dev_attr_fault_queue.dev_attr.attr,
+ &iio_dev_attr_t_alarm_high.dev_attr.attr,
+ &iio_dev_attr_t_alarm_low.dev_attr.attr,
+ &iio_dev_attr_t_hyst.dev_attr.attr,
NULL,
};
static struct attribute *adt7410_event_ct_attributes[] = {
- &iio_event_attr_event_mode.dev_attr.attr,
- &iio_event_attr_available_event_modes.dev_attr.attr,
- &iio_event_attr_fault_queue.dev_attr.attr,
- &iio_event_attr_t_crit.dev_attr.attr,
- &iio_event_attr_t_hyst.dev_attr.attr,
+ &iio_dev_attr_event_mode.dev_attr.attr,
+ &iio_dev_attr_available_event_modes.dev_attr.attr,
+ &iio_dev_attr_fault_queue.dev_attr.attr,
+ &iio_dev_attr_t_crit.dev_attr.attr,
+ &iio_dev_attr_t_hyst.dev_attr.attr,
NULL,
};
static struct attribute_group adt7410_event_attribute_group[ADT7410_IRQS] = {
{
.attrs = adt7410_event_int_attributes,
- },
- {
+ }, {
.attrs = adt7410_event_ct_attributes,
}
};
+static const struct iio_info adt7410_info = {
+ .attrs = &adt7410_attribute_group,
+ .num_interrupt_lines = ADT7410_IRQS,
+ .event_attrs = adt7410_event_attribute_group,
+ .driver_module = THIS_MODULE,
+};
+
/*
* device probe and remove
*/
@@ -762,20 +740,16 @@
i2c_set_clientdata(client, chip);
chip->client = client;
- chip->name = id->name;
- chip->indio_dev = iio_allocate_device();
+ chip->indio_dev = iio_allocate_device(0);
if (chip->indio_dev == NULL) {
ret = -ENOMEM;
goto error_free_chip;
}
-
+ chip->indio_dev->name = id->name;
chip->indio_dev->dev.parent = &client->dev;
- chip->indio_dev->attrs = &adt7410_attribute_group;
- chip->indio_dev->event_attrs = adt7410_event_attribute_group;
+ chip->indio_dev->info = &adt7410_info;
chip->indio_dev->dev_data = (void *)chip;
- chip->indio_dev->driver_module = THIS_MODULE;
- chip->indio_dev->num_interrupt_lines = ADT7410_IRQS;
chip->indio_dev->modes = INDIO_DIRECT_MODE;
ret = iio_device_register(chip->indio_dev);
@@ -784,44 +758,29 @@
/* CT critcal temperature event. line 0 */
if (client->irq) {
- ret = iio_register_interrupt_line(client->irq,
- chip->indio_dev,
- 0,
- IRQF_TRIGGER_LOW,
- chip->name);
+ ret = request_threaded_irq(client->irq,
+ NULL,
+ &adt7410_event_handler,
+ IRQF_TRIGGER_LOW,
+ id->name,
+ chip->indio_dev);
if (ret)
goto error_unreg_dev;
-
- /*
- * The event handler list element refer to iio_event_adt7410.
- * All event attributes bind to the same event handler.
- * One event handler can only be added to one event list.
- */
- iio_add_event_to_list(&iio_event_adt7410,
- &chip->indio_dev->interrupts[0]->ev_list);
}
/* INT bound temperature alarm event. line 1 */
if (adt7410_platform_data[0]) {
- ret = iio_register_interrupt_line(adt7410_platform_data[0],
- chip->indio_dev,
- 1,
- adt7410_platform_data[1],
- chip->name);
+ ret = request_threaded_irq(adt7410_platform_data[0],
+ NULL,
+ &adt7410_event_handler,
+ adt7410_platform_data[1],
+ id->name,
+ chip->indio_dev);
if (ret)
goto error_unreg_ct_irq;
-
- /*
- * The event handler list element refer to iio_event_adt7410.
- * All event attributes bind to the same event handler.
- * One event handler can only be added to one event list.
- */
- iio_add_event_to_list(&iio_event_adt7410_ct,
- &chip->indio_dev->interrupts[1]->ev_list);
}
if (client->irq && adt7410_platform_data[0]) {
- INIT_WORK(&chip->thresh_work, adt7410_interrupt_bh);
ret = adt7410_i2c_read_byte(chip, ADT7410_CONFIG, &chip->config);
if (ret) {
@@ -850,9 +809,9 @@
return 0;
error_unreg_int_irq:
- iio_unregister_interrupt_line(chip->indio_dev, 1);
+ free_irq(adt7410_platform_data[0], chip->indio_dev);
error_unreg_ct_irq:
- iio_unregister_interrupt_line(chip->indio_dev, 0);
+ free_irq(client->irq, chip->indio_dev);
error_unreg_dev:
iio_device_unregister(chip->indio_dev);
error_free_dev:
@@ -870,9 +829,9 @@
unsigned long *adt7410_platform_data = client->dev.platform_data;
if (adt7410_platform_data[0])
- iio_unregister_interrupt_line(indio_dev, 1);
+ free_irq(adt7410_platform_data[0], chip->indio_dev);
if (client->irq)
- iio_unregister_interrupt_line(indio_dev, 0);
+ free_irq(client->irq, chip->indio_dev);
iio_device_unregister(indio_dev);
iio_free_device(chip->indio_dev);
kfree(chip);
diff --git a/drivers/staging/iio/adc/adt75.c b/drivers/staging/iio/adc/adt75.c
index aff4d31..1171fb9 100644
--- a/drivers/staging/iio/adc/adt75.c
+++ b/drivers/staging/iio/adc/adt75.c
@@ -7,15 +7,11 @@
*/
#include <linux/interrupt.h>
-#include <linux/gpio.h>
-#include <linux/workqueue.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/sysfs.h>
-#include <linux/list.h>
#include <linux/i2c.h>
-#include <linux/rtc.h>
#include "../iio.h"
#include "../sysfs.h"
@@ -54,11 +50,8 @@
*/
struct adt75_chip_info {
- const char *name;
struct i2c_client *client;
struct iio_dev *indio_dev;
- struct work_struct thresh_work;
- s64 last_timestamp;
u8 config;
};
@@ -249,23 +242,11 @@
static IIO_DEVICE_ATTR(value, S_IRUGO, adt75_show_value, NULL, 0);
-static ssize_t adt75_show_name(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- struct iio_dev *dev_info = dev_get_drvdata(dev);
- struct adt75_chip_info *chip = dev_info->dev_data;
- return sprintf(buf, "%s\n", chip->name);
-}
-
-static IIO_DEVICE_ATTR(name, S_IRUGO, adt75_show_name, NULL, 0);
-
static struct attribute *adt75_attributes[] = {
&iio_dev_attr_available_modes.dev_attr.attr,
&iio_dev_attr_mode.dev_attr.attr,
&iio_dev_attr_oneshot.dev_attr.attr,
&iio_dev_attr_value.dev_attr.attr,
- &iio_dev_attr_name.dev_attr.attr,
NULL,
};
@@ -277,35 +258,20 @@
* temperature bound events
*/
-#define IIO_EVENT_CODE_ADT75_OTI IIO_BUFFER_EVENT_CODE(0)
+#define IIO_EVENT_CODE_ADT75_OTI IIO_UNMOD_EVENT_CODE(IIO_EV_CLASS_TEMP, \
+ 0, \
+ IIO_EV_TYPE_THRESH, \
+ IIO_EV_DIR_FALLING)
-static void adt75_interrupt_bh(struct work_struct *work_s)
+static irqreturn_t adt75_event_handler(int irq, void *private)
{
- struct adt75_chip_info *chip =
- container_of(work_s, struct adt75_chip_info, thresh_work);
+ iio_push_event(private, 0,
+ IIO_EVENT_CODE_ADT75_OTI,
+ iio_get_time_ns());
- enable_irq(chip->client->irq);
-
- iio_push_event(chip->indio_dev, 0,
- IIO_EVENT_CODE_ADT75_OTI,
- chip->last_timestamp);
+ return IRQ_HANDLED;
}
-static int adt75_interrupt(struct iio_dev *dev_info,
- int index,
- s64 timestamp,
- int no_test)
-{
- struct adt75_chip_info *chip = dev_info->dev_data;
-
- chip->last_timestamp = timestamp;
- schedule_work(&chip->thresh_work);
-
- return 0;
-}
-
-IIO_EVENT_SH(adt75, &adt75_interrupt);
-
static ssize_t adt75_show_oti_mode(struct device *dev,
struct device_attribute *attr,
char *buf)
@@ -458,16 +424,16 @@
}
static inline ssize_t adt75_show_t_bound(struct device *dev,
struct device_attribute *attr,
- u8 bound_reg,
char *buf)
{
+ struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
struct iio_dev *dev_info = dev_get_drvdata(dev);
struct adt75_chip_info *chip = dev_info->dev_data;
u16 data;
char sign = ' ';
int ret;
- ret = adt75_i2c_read(chip, bound_reg, (u8 *)&data);
+ ret = adt75_i2c_read(chip, this_attr->address, (u8 *)&data);
if (ret)
return -EIO;
@@ -485,10 +451,10 @@
static inline ssize_t adt75_set_t_bound(struct device *dev,
struct device_attribute *attr,
- u8 bound_reg,
const char *buf,
size_t len)
{
+ struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
struct iio_dev *dev_info = dev_get_drvdata(dev);
struct adt75_chip_info *chip = dev_info->dev_data;
long tmp1, tmp2;
@@ -525,67 +491,42 @@
data <<= ADT75_VALUE_OFFSET;
data = swab16(data);
- ret = adt75_i2c_write(chip, bound_reg, (u8)data);
+ ret = adt75_i2c_write(chip, this_attr->address, (u8)data);
if (ret)
return -EIO;
return ret;
}
-static ssize_t adt75_show_t_os(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- return adt75_show_t_bound(dev, attr,
- ADT75_T_OS, buf);
-}
-static inline ssize_t adt75_set_t_os(struct device *dev,
- struct device_attribute *attr,
- const char *buf,
- size_t len)
-{
- return adt75_set_t_bound(dev, attr,
- ADT75_T_OS, buf, len);
-}
-
-static ssize_t adt75_show_t_hyst(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- return adt75_show_t_bound(dev, attr,
- ADT75_T_HYST, buf);
-}
-
-static inline ssize_t adt75_set_t_hyst(struct device *dev,
- struct device_attribute *attr,
- const char *buf,
- size_t len)
-{
- return adt75_set_t_bound(dev, attr,
- ADT75_T_HYST, buf, len);
-}
-
-IIO_EVENT_ATTR_SH(oti_mode, iio_event_adt75,
- adt75_show_oti_mode, adt75_set_oti_mode, 0);
-IIO_EVENT_ATTR_SH(available_oti_modes, iio_event_adt75,
- adt75_show_available_oti_modes, NULL, 0);
-IIO_EVENT_ATTR_SH(smbus_alart, iio_event_adt75,
- adt75_show_smbus_alart, adt75_set_smbus_alart, 0);
-IIO_EVENT_ATTR_SH(fault_queue, iio_event_adt75,
- adt75_show_fault_queue, adt75_set_fault_queue, 0);
-IIO_EVENT_ATTR_SH(t_os, iio_event_adt75,
- adt75_show_t_os, adt75_set_t_os, 0);
-IIO_EVENT_ATTR_SH(t_hyst, iio_event_adt75,
- adt75_show_t_hyst, adt75_set_t_hyst, 0);
+static IIO_DEVICE_ATTR(oti_mode,
+ S_IRUGO | S_IWUSR,
+ adt75_show_oti_mode, adt75_set_oti_mode, 0);
+static IIO_DEVICE_ATTR(available_oti_modes,
+ S_IRUGO,
+ adt75_show_available_oti_modes, NULL, 0);
+static IIO_DEVICE_ATTR(smbus_alart,
+ S_IRUGO | S_IWUSR,
+ adt75_show_smbus_alart, adt75_set_smbus_alart, 0);
+static IIO_DEVICE_ATTR(fault_queue,
+ S_IRUGO | S_IWUSR,
+ adt75_show_fault_queue, adt75_set_fault_queue, 0);
+static IIO_DEVICE_ATTR(t_os_value,
+ S_IRUGO | S_IWUSR,
+ adt75_show_t_bound, adt75_set_t_bound,
+ ADT75_T_OS);
+static IIO_DEVICE_ATTR(t_hyst_value,
+ S_IRUGO | S_IWUSR,
+ adt75_show_t_bound, adt75_set_t_bound,
+ ADT75_T_HYST);
static struct attribute *adt75_event_attributes[] = {
- &iio_event_attr_oti_mode.dev_attr.attr,
- &iio_event_attr_available_oti_modes.dev_attr.attr,
- &iio_event_attr_smbus_alart.dev_attr.attr,
- &iio_event_attr_fault_queue.dev_attr.attr,
- &iio_event_attr_t_os.dev_attr.attr,
- &iio_event_attr_t_hyst.dev_attr.attr,
+ &iio_dev_attr_oti_mode.dev_attr.attr,
+ &iio_dev_attr_available_oti_modes.dev_attr.attr,
+ &iio_dev_attr_smbus_alart.dev_attr.attr,
+ &iio_dev_attr_fault_queue.dev_attr.attr,
+ &iio_dev_attr_t_os_value.dev_attr.attr,
+ &iio_dev_attr_t_hyst_value.dev_attr.attr,
NULL,
};
@@ -593,6 +534,13 @@
.attrs = adt75_event_attributes,
};
+static const struct iio_info adt75_info = {
+ .attrs = &adt75_attribute_group,
+ .num_interrupt_lines = 1,
+ .event_attrs = &adt75_event_attribute_group,
+ .driver_module = THIS_MODULE,
+};
+
/*
* device probe and remove
*/
@@ -612,20 +560,17 @@
i2c_set_clientdata(client, chip);
chip->client = client;
- chip->name = id->name;
- chip->indio_dev = iio_allocate_device();
+ chip->indio_dev = iio_allocate_device(0);
if (chip->indio_dev == NULL) {
ret = -ENOMEM;
goto error_free_chip;
}
+ chip->indio_dev->name = id->name;
chip->indio_dev->dev.parent = &client->dev;
- chip->indio_dev->attrs = &adt75_attribute_group;
- chip->indio_dev->event_attrs = &adt75_event_attribute_group;
+ chip->indio_dev->info = &adt75_info;
chip->indio_dev->dev_data = (void *)chip;
- chip->indio_dev->driver_module = THIS_MODULE;
- chip->indio_dev->num_interrupt_lines = 1;
chip->indio_dev->modes = INDIO_DIRECT_MODE;
ret = iio_device_register(chip->indio_dev);
@@ -633,24 +578,15 @@
goto error_free_dev;
if (client->irq > 0) {
- ret = iio_register_interrupt_line(client->irq,
- chip->indio_dev,
- 0,
- IRQF_TRIGGER_LOW,
- chip->name);
+ ret = request_threaded_irq(client->irq,
+ NULL,
+ &adt75_event_handler,
+ IRQF_TRIGGER_LOW,
+ chip->indio_dev->name,
+ chip->indio_dev);
if (ret)
goto error_unreg_dev;
- /*
- * The event handler list element refer to iio_event_adt75.
- * All event attributes bind to the same event handler.
- * So, only register event handler once.
- */
- iio_add_event_to_list(&iio_event_adt75,
- &chip->indio_dev->interrupts[0]->ev_list);
-
- INIT_WORK(&chip->thresh_work, adt75_interrupt_bh);
-
ret = adt75_i2c_read(chip, ADT75_CONFIG, &chip->config);
if (ret) {
ret = -EIO;
@@ -668,11 +604,11 @@
}
dev_info(&client->dev, "%s temperature sensor registered.\n",
- id->name);
+ chip->indio_dev->name);
return 0;
error_unreg_irq:
- iio_unregister_interrupt_line(chip->indio_dev, 0);
+ free_irq(client->irq, chip->indio_dev);
error_unreg_dev:
iio_device_unregister(chip->indio_dev);
error_free_dev:
@@ -689,7 +625,7 @@
struct iio_dev *indio_dev = chip->indio_dev;
if (client->irq)
- iio_unregister_interrupt_line(indio_dev, 0);
+ free_irq(client->irq, chip->indio_dev);
iio_device_unregister(indio_dev);
iio_free_device(chip->indio_dev);
kfree(chip);
diff --git a/drivers/staging/iio/adc/max1363.h b/drivers/staging/iio/adc/max1363.h
index 8f0fe1c..360bfc5 100644
--- a/drivers/staging/iio/adc/max1363.h
+++ b/drivers/staging/iio/adc/max1363.h
@@ -67,70 +67,6 @@
long modemask;
};
-#define MAX1363_MODE_SINGLE(_num, _mask) { \
- .conf = MAX1363_CHANNEL_SEL(_num) \
- | MAX1363_CONFIG_SCAN_SINGLE_1 \
- | MAX1363_CONFIG_SE, \
- .modemask = _mask, \
- }
-
-#define MAX1363_MODE_SCAN_TO_CHANNEL(_num, _mask) { \
- .conf = MAX1363_CHANNEL_SEL(_num) \
- | MAX1363_CONFIG_SCAN_TO_CS \
- | MAX1363_CONFIG_SE, \
- .modemask = _mask, \
- }
-
-
-/* note not available for max1363 hence naming */
-#define MAX1236_MODE_SCAN_MID_TO_CHANNEL(_mid, _num, _mask) { \
- .conf = MAX1363_CHANNEL_SEL(_num) \
- | MAX1236_SCAN_MID_TO_CHANNEL \
- | MAX1363_CONFIG_SE, \
- .modemask = _mask \
-}
-
-#define MAX1363_MODE_DIFF_SINGLE(_nump, _numm, _mask) { \
- .conf = MAX1363_CHANNEL_SEL(_nump) \
- | MAX1363_CONFIG_SCAN_SINGLE_1 \
- | MAX1363_CONFIG_DE, \
- .modemask = _mask \
- }
-
-/* Can't think how to automate naming so specify for now */
-#define MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(_num, _numvals, _mask) { \
- .conf = MAX1363_CHANNEL_SEL(_num) \
- | MAX1363_CONFIG_SCAN_TO_CS \
- | MAX1363_CONFIG_DE, \
- .modemask = _mask \
- }
-
-/* note only available for max1363 hence naming */
-#define MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(_num, _numvals, _mask) { \
- .conf = MAX1363_CHANNEL_SEL(_num) \
- | MAX1236_SCAN_MID_TO_CHANNEL \
- | MAX1363_CONFIG_SE, \
- .modemask = _mask \
-}
-
-/* This may seem an overly long winded way to do this, but at least it makes
- * clear what all the various options actually do. Alternative suggestions
- * that don't require user to have intimate knowledge of the chip welcomed.
- */
-enum max1363_channels {
- max1363_in0, max1363_in1, max1363_in2, max1363_in3,
- max1363_in4, max1363_in5, max1363_in6, max1363_in7,
- max1363_in8, max1363_in9, max1363_in10, max1363_in11,
-
- max1363_in0min1, max1363_in2min3,
- max1363_in4min5, max1363_in6min7,
- max1363_in8min9, max1363_in10min11,
-
- max1363_in1min0, max1363_in3min2,
- max1363_in5min4, max1363_in7min6,
- max1363_in9min8, max1363_in11min10,
-};
-
/* This must be maintained along side the max1363_mode_table in max1363_core */
enum max1363_modes {
/* Single read of a single channel */
@@ -152,37 +88,34 @@
/**
* struct max1363_chip_info - chip specifc information
* @name: indentification string for chip
- * @num_inputs: number of physical inputs on chip
* @bits: accuracy of the adc in bits
* @int_vref_mv: the internal reference voltage
- * @monitor_mode: whether the chip supports monitor interrupts
+ * @info: iio core function callbacks structure
* @mode_list: array of available scan modes
* @num_modes: the number of scan modes available
* @default_mode: the scan mode in which the chip starts up
+ * @channel: channel specification
+ * @num_channels: number of channels
*/
struct max1363_chip_info {
- u8 num_inputs;
- u8 bits;
- u16 int_vref_mv;
- bool monitor_mode;
+ const struct iio_info *info;
+ struct iio_chan_spec *channels;
+ int num_channels;
const enum max1363_modes *mode_list;
- int num_modes;
enum max1363_modes default_mode;
- struct attribute_group *dev_attrs;
- struct attribute_group *scan_attrs;
+ u16 int_vref_mv;
+ u8 num_modes;
+ u8 bits;
};
/**
* struct max1363_state - driver instance specific data
- * @indio_dev: the industrial I/O device
* @client: i2c_client
* @setupbyte: cache of current device setup byte
* @configbyte: cache of current device config byte
* @chip_info: chip model specific constants, available modes etc
* @current_mode: the scan mode of this chip
* @requestedmask: a valid requested set of channels
- * @poll_work: bottom half of polling interrupt handler
- * @protect_ring: used to ensure only one polling bh running at a time
* @reg: supply regulator
* @monitor_on: whether monitor mode is enabled
* @monitor_speed: parameter corresponding to device monitor speed setting
@@ -190,20 +123,14 @@
* @mask_low: bitmask for enabled low thresholds
* @thresh_high: high threshold values
* @thresh_low: low threshold values
- * @last_timestamp: timestamp of last event interrupt
- * @thresh_work: bh work structure for event handling
*/
struct max1363_state {
- struct iio_dev *indio_dev;
struct i2c_client *client;
u8 setupbyte;
u8 configbyte;
const struct max1363_chip_info *chip_info;
const struct max1363_mode *current_mode;
u32 requestedmask;
- struct work_struct poll_work;
- atomic_t protect_ring;
- struct iio_trigger *trig;
struct regulator *reg;
/* Using monitor modes and buffer at the same time is
@@ -215,8 +142,6 @@
/* 4x unipolar first then the fours bipolar ones */
s16 thresh_high[8];
s16 thresh_low[8];
- s64 last_timestamp;
- struct work_struct thresh_work;
};
const struct max1363_mode
diff --git a/drivers/staging/iio/adc/max1363_core.c b/drivers/staging/iio/adc/max1363_core.c
index de83c3b..98cebd2 100644
--- a/drivers/staging/iio/adc/max1363_core.c
+++ b/drivers/staging/iio/adc/max1363_core.c
@@ -22,7 +22,6 @@
*/
#include <linux/interrupt.h>
-#include <linux/workqueue.h>
#include <linux/device.h>
#include <linux/kernel.h>
#include <linux/sysfs.h>
@@ -39,38 +38,50 @@
#include "adc.h"
#include "max1363.h"
-/* Here we claim all are 16 bits. This currently does no harm and saves
- * us a lot of scan element listings */
+#define MAX1363_MODE_SINGLE(_num, _mask) { \
+ .conf = MAX1363_CHANNEL_SEL(_num) \
+ | MAX1363_CONFIG_SCAN_SINGLE_1 \
+ | MAX1363_CONFIG_SE, \
+ .modemask = _mask, \
+ }
-#define MAX1363_SCAN_EL(number) \
- IIO_SCAN_EL_C(in##number, number, 0, NULL);
-#define MAX1363_SCAN_EL_D(p, n, number) \
- IIO_SCAN_NAMED_EL_C(in##p##m##in##n, in##p-in##n, number, 0, NULL);
+#define MAX1363_MODE_SCAN_TO_CHANNEL(_num, _mask) { \
+ .conf = MAX1363_CHANNEL_SEL(_num) \
+ | MAX1363_CONFIG_SCAN_TO_CS \
+ | MAX1363_CONFIG_SE, \
+ .modemask = _mask, \
+ }
-static MAX1363_SCAN_EL(0);
-static MAX1363_SCAN_EL(1);
-static MAX1363_SCAN_EL(2);
-static MAX1363_SCAN_EL(3);
-static MAX1363_SCAN_EL(4);
-static MAX1363_SCAN_EL(5);
-static MAX1363_SCAN_EL(6);
-static MAX1363_SCAN_EL(7);
-static MAX1363_SCAN_EL(8);
-static MAX1363_SCAN_EL(9);
-static MAX1363_SCAN_EL(10);
-static MAX1363_SCAN_EL(11);
-static MAX1363_SCAN_EL_D(0, 1, 12);
-static MAX1363_SCAN_EL_D(2, 3, 13);
-static MAX1363_SCAN_EL_D(4, 5, 14);
-static MAX1363_SCAN_EL_D(6, 7, 15);
-static MAX1363_SCAN_EL_D(8, 9, 16);
-static MAX1363_SCAN_EL_D(10, 11, 17);
-static MAX1363_SCAN_EL_D(1, 0, 18);
-static MAX1363_SCAN_EL_D(3, 2, 19);
-static MAX1363_SCAN_EL_D(5, 4, 20);
-static MAX1363_SCAN_EL_D(7, 6, 21);
-static MAX1363_SCAN_EL_D(9, 8, 22);
-static MAX1363_SCAN_EL_D(11, 10, 23);
+/* note not available for max1363 hence naming */
+#define MAX1236_MODE_SCAN_MID_TO_CHANNEL(_mid, _num, _mask) { \
+ .conf = MAX1363_CHANNEL_SEL(_num) \
+ | MAX1236_SCAN_MID_TO_CHANNEL \
+ | MAX1363_CONFIG_SE, \
+ .modemask = _mask \
+}
+
+#define MAX1363_MODE_DIFF_SINGLE(_nump, _numm, _mask) { \
+ .conf = MAX1363_CHANNEL_SEL(_nump) \
+ | MAX1363_CONFIG_SCAN_SINGLE_1 \
+ | MAX1363_CONFIG_DE, \
+ .modemask = _mask \
+ }
+
+/* Can't think how to automate naming so specify for now */
+#define MAX1363_MODE_DIFF_SCAN_TO_CHANNEL(_num, _numvals, _mask) { \
+ .conf = MAX1363_CHANNEL_SEL(_num) \
+ | MAX1363_CONFIG_SCAN_TO_CS \
+ | MAX1363_CONFIG_DE, \
+ .modemask = _mask \
+ }
+
+/* note only available for max1363 hence naming */
+#define MAX1236_MODE_DIFF_SCAN_MID_TO_CHANNEL(_num, _numvals, _mask) { \
+ .conf = MAX1363_CHANNEL_SEL(_num) \
+ | MAX1236_SCAN_MID_TO_CHANNEL \
+ | MAX1363_CONFIG_SE, \
+ .modemask = _mask \
+}
static const struct max1363_mode max1363_mode_table[] = {
/* All of the single channel options first */
@@ -147,76 +158,13 @@
return NULL;
}
-static ssize_t max1363_show_precision_u(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- struct iio_ring_buffer *ring = dev_get_drvdata(dev);
- struct iio_dev *dev_info = ring->indio_dev;
- struct max1363_state *st = iio_dev_get_devdata(dev_info);
- return sprintf(buf, "u%d/16\n", st->chip_info->bits);
-}
-
-static ssize_t max1363_show_precision_s(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- struct iio_ring_buffer *ring = dev_get_drvdata(dev);
- struct iio_dev *dev_info = ring->indio_dev;
- struct max1363_state *st = iio_dev_get_devdata(dev_info);
- return sprintf(buf, "s%d/16\n", st->chip_info->bits);
-}
-
-#define MAX1363_SCAN_TYPE(n) \
- DEVICE_ATTR(in##n##_type, S_IRUGO, \
- max1363_show_precision_u, NULL);
-#define MAX1363_SCAN_TYPE_D(p, n) \
- struct device_attribute dev_attr_in##p##m##in##n##_type = \
- __ATTR(in##p-in##n##_type, S_IRUGO, \
- max1363_show_precision_s, NULL);
-
-static MAX1363_SCAN_TYPE(0);
-static MAX1363_SCAN_TYPE(1);
-static MAX1363_SCAN_TYPE(2);
-static MAX1363_SCAN_TYPE(3);
-static MAX1363_SCAN_TYPE(4);
-static MAX1363_SCAN_TYPE(5);
-static MAX1363_SCAN_TYPE(6);
-static MAX1363_SCAN_TYPE(7);
-static MAX1363_SCAN_TYPE(8);
-static MAX1363_SCAN_TYPE(9);
-static MAX1363_SCAN_TYPE(10);
-static MAX1363_SCAN_TYPE(11);
-
-static MAX1363_SCAN_TYPE_D(0, 1);
-static MAX1363_SCAN_TYPE_D(2, 3);
-static MAX1363_SCAN_TYPE_D(4, 5);
-static MAX1363_SCAN_TYPE_D(6, 7);
-static MAX1363_SCAN_TYPE_D(8, 9);
-static MAX1363_SCAN_TYPE_D(10, 11);
-static MAX1363_SCAN_TYPE_D(1, 0);
-static MAX1363_SCAN_TYPE_D(3, 2);
-static MAX1363_SCAN_TYPE_D(5, 4);
-static MAX1363_SCAN_TYPE_D(7, 6);
-static MAX1363_SCAN_TYPE_D(9, 8);
-static MAX1363_SCAN_TYPE_D(11, 10);
-
static int max1363_write_basic_config(struct i2c_client *client,
unsigned char d1,
unsigned char d2)
{
- int ret;
- u8 *tx_buf = kmalloc(2, GFP_KERNEL);
+ u8 tx_buf[2] = {d1, d2};
- if (!tx_buf)
- return -ENOMEM;
- tx_buf[0] = d1;
- tx_buf[1] = d2;
-
- ret = i2c_master_send(client, tx_buf, 2);
- kfree(tx_buf);
-
- return (ret > 0) ? 0 : ret;
+ return i2c_master_send(client, tx_buf, 2);
}
int max1363_set_scan_mode(struct max1363_state *st)
@@ -231,20 +179,19 @@
st->configbyte);
}
-static ssize_t max1363_read_single_channel(struct device *dev,
- struct device_attribute *attr,
- char *buf)
+static int max1363_read_single_chan(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ int *val,
+ long m)
{
- struct iio_dev *dev_info = dev_get_drvdata(dev);
- struct max1363_state *st = iio_dev_get_devdata(dev_info);
- struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
- struct i2c_client *client = st->client;
- int ret = 0, len = 0;
- s32 data ;
+ int ret = 0;
+ s32 data;
char rxbuf[2];
long mask;
+ struct max1363_state *st = iio_priv(indio_dev);
+ struct i2c_client *client = st->client;
- mutex_lock(&dev_info->mlock);
+ mutex_lock(&indio_dev->mlock);
/*
* If monitor mode is enabled, the method for reading a single
* channel will have to be rather different and has not yet
@@ -256,8 +203,8 @@
}
/* If ring buffer capture is occurring, query the buffer */
- if (iio_ring_enabled(dev_info)) {
- mask = max1363_mode_table[this_attr->address].modemask;
+ if (iio_ring_enabled(indio_dev)) {
+ mask = max1363_mode_table[chan->address].modemask;
data = max1363_single_channel_from_ring(mask, st);
if (data < 0) {
ret = data;
@@ -265,13 +212,11 @@
}
} else {
/* Check to see if current scan mode is correct */
- if (st->current_mode !=
- &max1363_mode_table[this_attr->address]) {
+ if (st->current_mode != &max1363_mode_table[chan->address]) {
/* Update scan mode if needed */
- st->current_mode
- = &max1363_mode_table[this_attr->address];
+ st->current_mode = &max1363_mode_table[chan->address];
ret = max1363_set_scan_mode(st);
- if (ret)
+ if (ret < 0)
goto error_ret;
}
if (st->chip_info->bits != 8) {
@@ -281,7 +226,6 @@
ret = data;
goto error_ret;
}
-
data = (s32)(rxbuf[1]) | ((s32)(rxbuf[0] & 0x0F)) << 8;
} else {
/* Get reading */
@@ -293,72 +237,44 @@
data = rxbuf[0];
}
}
- /* Pretty print the result */
- len = sprintf(buf, "%u\n", data);
-
+ *val = data;
error_ret:
- mutex_unlock(&dev_info->mlock);
- return ret ? ret : len;
+ mutex_unlock(&indio_dev->mlock);
+ return ret;
+
}
-/* Direct read attribtues */
-static IIO_DEV_ATTR_IN_RAW(0, max1363_read_single_channel, _s0);
-static IIO_DEV_ATTR_IN_RAW(1, max1363_read_single_channel, _s1);
-static IIO_DEV_ATTR_IN_RAW(2, max1363_read_single_channel, _s2);
-static IIO_DEV_ATTR_IN_RAW(3, max1363_read_single_channel, _s3);
-static IIO_DEV_ATTR_IN_RAW(4, max1363_read_single_channel, _s4);
-static IIO_DEV_ATTR_IN_RAW(5, max1363_read_single_channel, _s5);
-static IIO_DEV_ATTR_IN_RAW(6, max1363_read_single_channel, _s6);
-static IIO_DEV_ATTR_IN_RAW(7, max1363_read_single_channel, _s7);
-static IIO_DEV_ATTR_IN_RAW(8, max1363_read_single_channel, _s8);
-static IIO_DEV_ATTR_IN_RAW(9, max1363_read_single_channel, _s9);
-static IIO_DEV_ATTR_IN_RAW(10, max1363_read_single_channel, _s10);
-static IIO_DEV_ATTR_IN_RAW(11, max1363_read_single_channel, _s11);
-
-static IIO_DEV_ATTR_IN_DIFF_RAW(0, 1, max1363_read_single_channel, d0m1);
-static IIO_DEV_ATTR_IN_DIFF_RAW(2, 3, max1363_read_single_channel, d2m3);
-static IIO_DEV_ATTR_IN_DIFF_RAW(4, 5, max1363_read_single_channel, d4m5);
-static IIO_DEV_ATTR_IN_DIFF_RAW(6, 7, max1363_read_single_channel, d6m7);
-static IIO_DEV_ATTR_IN_DIFF_RAW(8, 9, max1363_read_single_channel, d8m9);
-static IIO_DEV_ATTR_IN_DIFF_RAW(10, 11, max1363_read_single_channel, d10m11);
-static IIO_DEV_ATTR_IN_DIFF_RAW(1, 0, max1363_read_single_channel, d1m0);
-static IIO_DEV_ATTR_IN_DIFF_RAW(3, 2, max1363_read_single_channel, d3m2);
-static IIO_DEV_ATTR_IN_DIFF_RAW(5, 4, max1363_read_single_channel, d5m4);
-static IIO_DEV_ATTR_IN_DIFF_RAW(7, 6, max1363_read_single_channel, d7m6);
-static IIO_DEV_ATTR_IN_DIFF_RAW(9, 8, max1363_read_single_channel, d9m8);
-static IIO_DEV_ATTR_IN_DIFF_RAW(11, 10, max1363_read_single_channel, d11m10);
-
-
-static ssize_t max1363_show_scale(struct device *dev,
- struct device_attribute *attr,
- char *buf)
+static int max1363_read_raw(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ int *val,
+ int *val2,
+ long m)
{
- /* Driver currently only support internal vref */
- struct iio_dev *dev_info = dev_get_drvdata(dev);
- struct max1363_state *st = iio_dev_get_devdata(dev_info);
- /* Corresponds to Vref / 2^(bits) */
-
- if ((1 << (st->chip_info->bits + 1))
- > st->chip_info->int_vref_mv)
- return sprintf(buf, "0.5\n");
- else
- return sprintf(buf, "%d\n",
- st->chip_info->int_vref_mv >> st->chip_info->bits);
+ struct max1363_state *st = iio_priv(indio_dev);
+ int ret;
+ switch (m) {
+ case 0:
+ ret = max1363_read_single_chan(indio_dev, chan, val, m);
+ if (ret)
+ return ret;
+ return IIO_VAL_INT;
+ case (1 << IIO_CHAN_INFO_SCALE_SHARED):
+ if ((1 << (st->chip_info->bits + 1)) >
+ st->chip_info->int_vref_mv) {
+ *val = 0;
+ *val2 = 500000;
+ return IIO_VAL_INT_PLUS_MICRO;
+ } else {
+ *val = (st->chip_info->int_vref_mv)
+ >> st->chip_info->bits;
+ return IIO_VAL_INT;
+ }
+ default:
+ return -EINVAL;
+ }
+ return 0;
}
-static IIO_DEVICE_ATTR(in_scale, S_IRUGO, max1363_show_scale, NULL, 0);
-
-static ssize_t max1363_show_name(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- struct iio_dev *dev_info = dev_get_drvdata(dev);
- struct max1363_state *st = iio_dev_get_devdata(dev_info);
- return sprintf(buf, "%s\n", st->client->name);
-}
-
-static IIO_DEVICE_ATTR(name, S_IRUGO, max1363_show_name, NULL, 0);
-
/* Applies to max1363 */
static const enum max1363_modes max1363_mode_list[] = {
_s0, _s1, _s2, _s3,
@@ -367,48 +283,76 @@
d0m1to2m3, d1m0to3m2,
};
-static struct attribute *max1363_device_attrs[] = {
- &iio_dev_attr_in0_raw.dev_attr.attr,
- &iio_dev_attr_in1_raw.dev_attr.attr,
- &iio_dev_attr_in2_raw.dev_attr.attr,
- &iio_dev_attr_in3_raw.dev_attr.attr,
- &iio_dev_attr_in0min1_raw.dev_attr.attr,
- &iio_dev_attr_in2min3_raw.dev_attr.attr,
- &iio_dev_attr_in1min0_raw.dev_attr.attr,
- &iio_dev_attr_in3min2_raw.dev_attr.attr,
- &iio_dev_attr_name.dev_attr.attr,
- &iio_dev_attr_in_scale.dev_attr.attr,
- NULL
+#define MAX1363_EV_M \
+ (IIO_EV_BIT(IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING) \
+ | IIO_EV_BIT(IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING))
+#define MAX1363_INFO_MASK (1 << IIO_CHAN_INFO_SCALE_SHARED)
+
+static struct iio_chan_spec max1363_channels[] = {
+ IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 0, 0, MAX1363_INFO_MASK,
+ _s0, 0, IIO_ST('u', 12, 16, 0), MAX1363_EV_M),
+ IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 1, 0, MAX1363_INFO_MASK,
+ _s1, 1, IIO_ST('u', 12, 16, 0), MAX1363_EV_M),
+ IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 2, 0, MAX1363_INFO_MASK,
+ _s2, 2, IIO_ST('u', 12, 16, 0), MAX1363_EV_M),
+ IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 3, 0, MAX1363_INFO_MASK,
+ _s3, 3, IIO_ST('u', 12, 16, 0), MAX1363_EV_M),
+ IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, 0, 1, MAX1363_INFO_MASK,
+ d0m1, 4, IIO_ST('s', 12, 16, 0), MAX1363_EV_M),
+ IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, 2, 3, MAX1363_INFO_MASK,
+ d2m3, 5, IIO_ST('s', 12, 16, 0), MAX1363_EV_M),
+ IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, 1, 0, MAX1363_INFO_MASK,
+ d1m0, 6, IIO_ST('s', 12, 16, 0), MAX1363_EV_M),
+ IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, 3, 2, MAX1363_INFO_MASK,
+ d3m2, 7, IIO_ST('s', 12, 16, 0), MAX1363_EV_M),
+ IIO_CHAN_SOFT_TIMESTAMP(8)
};
-static struct attribute_group max1363_dev_attr_group = {
- .attrs = max1363_device_attrs,
+static struct iio_chan_spec max1361_channels[] = {
+ IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 0, 0, MAX1363_INFO_MASK,
+ _s0, 0, IIO_ST('u', 10, 16, 0), MAX1363_EV_M),
+ IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 1, 0, MAX1363_INFO_MASK,
+ _s1, 1, IIO_ST('u', 10, 16, 0), MAX1363_EV_M),
+ IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 2, 0, MAX1363_INFO_MASK,
+ _s2, 2, IIO_ST('u', 10, 16, 0), MAX1363_EV_M),
+ IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 3, 0, MAX1363_INFO_MASK,
+ _s3, 3, IIO_ST('u', 10, 16, 0), MAX1363_EV_M),
+ IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, 0, 1, MAX1363_INFO_MASK,
+ d0m1, 4, IIO_ST('s', 10, 16, 0), MAX1363_EV_M),
+ IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, 2, 3, MAX1363_INFO_MASK,
+ d2m3, 5, IIO_ST('s', 10, 16, 0), MAX1363_EV_M),
+ IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, 1, 0, MAX1363_INFO_MASK,
+ d1m0, 6, IIO_ST('s', 10, 16, 0), MAX1363_EV_M),
+ IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, 3, 2, MAX1363_INFO_MASK,
+ d3m2, 7, IIO_ST('s', 10, 16, 0), MAX1363_EV_M),
+ IIO_CHAN_SOFT_TIMESTAMP(8)
};
-static struct attribute *max1363_scan_el_attrs[] = {
- &iio_scan_el_in0.dev_attr.attr, &dev_attr_in0_type.attr,
- &iio_const_attr_in0_index.dev_attr.attr,
- &iio_scan_el_in1.dev_attr.attr, &dev_attr_in1_type.attr,
- &iio_const_attr_in1_index.dev_attr.attr,
- &iio_scan_el_in2.dev_attr.attr, &dev_attr_in2_type.attr,
- &iio_const_attr_in2_index.dev_attr.attr,
- &iio_scan_el_in3.dev_attr.attr, &dev_attr_in3_type.attr,
- &iio_const_attr_in3_index.dev_attr.attr,
- &iio_scan_el_in0min1.dev_attr.attr, &dev_attr_in0min1_type.attr,
- &iio_const_attr_in0min1_index.dev_attr.attr,
- &iio_scan_el_in2min3.dev_attr.attr, &dev_attr_in2min3_type.attr,
- &iio_const_attr_in2min3_index.dev_attr.attr,
- &iio_scan_el_in1min0.dev_attr.attr, &dev_attr_in1min0_type.attr,
- &iio_const_attr_in1min0_index.dev_attr.attr,
- &iio_scan_el_in3min2.dev_attr.attr, &dev_attr_in3min2_type.attr,
- &iio_const_attr_in3min2_index.dev_attr.attr,
- NULL,
-};
+#define MAX1363_CHAN_U(num, address, scan_index, bits) \
+ IIO_CHAN(IIO_IN, 0, 1, 0, NULL, num, 0, MAX1363_INFO_MASK, \
+ address, scan_index, IIO_ST('u', bits, \
+ (bits == 8) ? 8 : 16, 0), 0)
+/* bipolar channel */
+#define MAX1363_CHAN_B(num, num2, address, scan_index, bits) \
+ IIO_CHAN(IIO_IN_DIFF, 0, 1, 0, NULL, num, num2, MAX1363_INFO_MASK,\
+ address, scan_index, IIO_ST('s', bits, \
+ (bits == 8) ? 8 : 16, 0), 0)
-static struct attribute_group max1363_scan_el_group = {
- .name = "scan_elements",
- .attrs = max1363_scan_el_attrs,
-};
+#define MAX1363_4X_CHANS(bits) { \
+ MAX1363_CHAN_U(0, _s0, 0, bits), \
+ MAX1363_CHAN_U(1, _s1, 1, bits), \
+ MAX1363_CHAN_U(2, _s2, 2, bits), \
+ MAX1363_CHAN_U(3, _s3, 3, bits), \
+ MAX1363_CHAN_B(0, 1, d0m1, 4, bits), \
+ MAX1363_CHAN_B(2, 3, d2m3, 5, bits), \
+ MAX1363_CHAN_B(1, 0, d1m0, 6, bits), \
+ MAX1363_CHAN_B(3, 2, d3m2, 7, bits), \
+ IIO_CHAN_SOFT_TIMESTAMP(8) \
+ }
+
+static struct iio_chan_spec max1036_channels[] = MAX1363_4X_CHANS(8);
+static struct iio_chan_spec max1136_channels[] = MAX1363_4X_CHANS(10);
+static struct iio_chan_spec max1236_channels[] = MAX1363_4X_CHANS(12);
/* Appies to max1236, max1237 */
static const enum max1363_modes max1236_mode_list[] = {
@@ -432,97 +376,36 @@
d6m7to8m9, d6m7to10m11, d7m6to9m8, d7m6to11m10,
};
-static struct attribute *max1238_device_attrs[] = {
- &iio_dev_attr_in0_raw.dev_attr.attr,
- &iio_dev_attr_in1_raw.dev_attr.attr,
- &iio_dev_attr_in2_raw.dev_attr.attr,
- &iio_dev_attr_in3_raw.dev_attr.attr,
- &iio_dev_attr_in4_raw.dev_attr.attr,
- &iio_dev_attr_in5_raw.dev_attr.attr,
- &iio_dev_attr_in6_raw.dev_attr.attr,
- &iio_dev_attr_in7_raw.dev_attr.attr,
- &iio_dev_attr_in8_raw.dev_attr.attr,
- &iio_dev_attr_in9_raw.dev_attr.attr,
- &iio_dev_attr_in10_raw.dev_attr.attr,
- &iio_dev_attr_in11_raw.dev_attr.attr,
- &iio_dev_attr_in0min1_raw.dev_attr.attr,
- &iio_dev_attr_in2min3_raw.dev_attr.attr,
- &iio_dev_attr_in4min5_raw.dev_attr.attr,
- &iio_dev_attr_in6min7_raw.dev_attr.attr,
- &iio_dev_attr_in8min9_raw.dev_attr.attr,
- &iio_dev_attr_in10min11_raw.dev_attr.attr,
- &iio_dev_attr_in1min0_raw.dev_attr.attr,
- &iio_dev_attr_in3min2_raw.dev_attr.attr,
- &iio_dev_attr_in5min4_raw.dev_attr.attr,
- &iio_dev_attr_in7min6_raw.dev_attr.attr,
- &iio_dev_attr_in9min8_raw.dev_attr.attr,
- &iio_dev_attr_in11min10_raw.dev_attr.attr,
- &iio_dev_attr_name.dev_attr.attr,
- &iio_dev_attr_in_scale.dev_attr.attr,
- NULL
-};
-
-static struct attribute_group max1238_dev_attr_group = {
- .attrs = max1238_device_attrs,
-};
-
-static struct attribute *max1238_scan_el_attrs[] = {
- &iio_scan_el_in0.dev_attr.attr, &dev_attr_in0_type.attr,
- &iio_const_attr_in0_index.dev_attr.attr,
- &iio_scan_el_in1.dev_attr.attr, &dev_attr_in1_type.attr,
- &iio_const_attr_in1_index.dev_attr.attr,
- &iio_scan_el_in2.dev_attr.attr, &dev_attr_in2_type.attr,
- &iio_const_attr_in2_index.dev_attr.attr,
- &iio_scan_el_in3.dev_attr.attr, &dev_attr_in3_type.attr,
- &iio_const_attr_in3_index.dev_attr.attr,
- &iio_scan_el_in4.dev_attr.attr, &dev_attr_in4_type.attr,
- &iio_const_attr_in4_index.dev_attr.attr,
- &iio_scan_el_in5.dev_attr.attr, &dev_attr_in5_type.attr,
- &iio_const_attr_in5_index.dev_attr.attr,
- &iio_scan_el_in6.dev_attr.attr, &dev_attr_in6_type.attr,
- &iio_const_attr_in6_index.dev_attr.attr,
- &iio_scan_el_in7.dev_attr.attr, &dev_attr_in7_type.attr,
- &iio_const_attr_in7_index.dev_attr.attr,
- &iio_scan_el_in8.dev_attr.attr, &dev_attr_in8_type.attr,
- &iio_const_attr_in8_index.dev_attr.attr,
- &iio_scan_el_in9.dev_attr.attr, &dev_attr_in9_type.attr,
- &iio_const_attr_in9_index.dev_attr.attr,
- &iio_scan_el_in10.dev_attr.attr, &dev_attr_in10_type.attr,
- &iio_const_attr_in10_index.dev_attr.attr,
- &iio_scan_el_in11.dev_attr.attr, &dev_attr_in11_type.attr,
- &iio_const_attr_in11_index.dev_attr.attr,
- &iio_scan_el_in0min1.dev_attr.attr, &dev_attr_in0min1_type.attr,
- &iio_const_attr_in0min1_index.dev_attr.attr,
- &iio_scan_el_in2min3.dev_attr.attr, &dev_attr_in2min3_type.attr,
- &iio_const_attr_in2min3_index.dev_attr.attr,
- &iio_scan_el_in4min5.dev_attr.attr, &dev_attr_in4min5_type.attr,
- &iio_const_attr_in4min5_index.dev_attr.attr,
- &iio_scan_el_in6min7.dev_attr.attr, &dev_attr_in6min7_type.attr,
- &iio_const_attr_in6min7_index.dev_attr.attr,
- &iio_scan_el_in8min9.dev_attr.attr, &dev_attr_in8min9_type.attr,
- &iio_const_attr_in8min9_index.dev_attr.attr,
- &iio_scan_el_in10min11.dev_attr.attr, &dev_attr_in10min11_type.attr,
- &iio_const_attr_in10min11_index.dev_attr.attr,
- &iio_scan_el_in1min0.dev_attr.attr, &dev_attr_in1min0_type.attr,
- &iio_const_attr_in1min0_index.dev_attr.attr,
- &iio_scan_el_in3min2.dev_attr.attr, &dev_attr_in3min2_type.attr,
- &iio_const_attr_in3min2_index.dev_attr.attr,
- &iio_scan_el_in5min4.dev_attr.attr, &dev_attr_in5min4_type.attr,
- &iio_const_attr_in5min4_index.dev_attr.attr,
- &iio_scan_el_in7min6.dev_attr.attr, &dev_attr_in7min6_type.attr,
- &iio_const_attr_in7min6_index.dev_attr.attr,
- &iio_scan_el_in9min8.dev_attr.attr, &dev_attr_in9min8_type.attr,
- &iio_const_attr_in9min8_index.dev_attr.attr,
- &iio_scan_el_in11min10.dev_attr.attr, &dev_attr_in11min10_type.attr,
- &iio_const_attr_in11min10_index.dev_attr.attr,
- NULL,
-};
-
-static struct attribute_group max1238_scan_el_group = {
- .name = "scan_elements",
- .attrs = max1238_scan_el_attrs,
-};
-
+#define MAX1363_12X_CHANS(bits) { \
+ MAX1363_CHAN_U(0, _s0, 0, bits), \
+ MAX1363_CHAN_U(1, _s1, 1, bits), \
+ MAX1363_CHAN_U(2, _s2, 2, bits), \
+ MAX1363_CHAN_U(3, _s3, 3, bits), \
+ MAX1363_CHAN_U(4, _s4, 4, bits), \
+ MAX1363_CHAN_U(5, _s5, 5, bits), \
+ MAX1363_CHAN_U(6, _s6, 6, bits), \
+ MAX1363_CHAN_U(7, _s7, 7, bits), \
+ MAX1363_CHAN_U(8, _s8, 8, bits), \
+ MAX1363_CHAN_U(9, _s9, 9, bits), \
+ MAX1363_CHAN_U(10, _s10, 10, bits), \
+ MAX1363_CHAN_U(11, _s11, 11, bits), \
+ MAX1363_CHAN_B(0, 1, d0m1, 12, bits), \
+ MAX1363_CHAN_B(2, 3, d2m3, 13, bits), \
+ MAX1363_CHAN_B(4, 5, d4m5, 14, bits), \
+ MAX1363_CHAN_B(6, 7, d6m7, 15, bits), \
+ MAX1363_CHAN_B(8, 9, d8m9, 16, bits), \
+ MAX1363_CHAN_B(10, 11, d10m11, 17, bits), \
+ MAX1363_CHAN_B(1, 0, d1m0, 18, bits), \
+ MAX1363_CHAN_B(3, 2, d3m2, 19, bits), \
+ MAX1363_CHAN_B(5, 4, d5m4, 20, bits), \
+ MAX1363_CHAN_B(7, 6, d7m6, 21, bits), \
+ MAX1363_CHAN_B(9, 8, d9m8, 22, bits), \
+ MAX1363_CHAN_B(11, 10, d11m10, 23, bits), \
+ IIO_CHAN_SOFT_TIMESTAMP(24) \
+ }
+static struct iio_chan_spec max1038_channels[] = MAX1363_12X_CHANS(8);
+static struct iio_chan_spec max1138_channels[] = MAX1363_12X_CHANS(10);
+static struct iio_chan_spec max1238_channels[] = MAX1363_12X_CHANS(12);
static const enum max1363_modes max11607_mode_list[] = {
_s0, _s1, _s2, _s3,
@@ -542,72 +425,43 @@
d1m0to3m2, d1m0to5m4, d1m0to7m6,
};
-static struct attribute *max11608_device_attrs[] = {
- &iio_dev_attr_in0_raw.dev_attr.attr,
- &iio_dev_attr_in1_raw.dev_attr.attr,
- &iio_dev_attr_in2_raw.dev_attr.attr,
- &iio_dev_attr_in3_raw.dev_attr.attr,
- &iio_dev_attr_in4_raw.dev_attr.attr,
- &iio_dev_attr_in5_raw.dev_attr.attr,
- &iio_dev_attr_in6_raw.dev_attr.attr,
- &iio_dev_attr_in7_raw.dev_attr.attr,
- &iio_dev_attr_in0min1_raw.dev_attr.attr,
- &iio_dev_attr_in2min3_raw.dev_attr.attr,
- &iio_dev_attr_in4min5_raw.dev_attr.attr,
- &iio_dev_attr_in6min7_raw.dev_attr.attr,
- &iio_dev_attr_in1min0_raw.dev_attr.attr,
- &iio_dev_attr_in3min2_raw.dev_attr.attr,
- &iio_dev_attr_in5min4_raw.dev_attr.attr,
- &iio_dev_attr_in7min6_raw.dev_attr.attr,
- &iio_dev_attr_name.dev_attr.attr,
- &iio_dev_attr_in_scale.dev_attr.attr,
- NULL
+#define MAX1363_8X_CHANS(bits) { \
+ MAX1363_CHAN_U(0, _s0, 0, bits), \
+ MAX1363_CHAN_U(1, _s1, 1, bits), \
+ MAX1363_CHAN_U(2, _s2, 2, bits), \
+ MAX1363_CHAN_U(3, _s3, 3, bits), \
+ MAX1363_CHAN_U(4, _s4, 4, bits), \
+ MAX1363_CHAN_U(5, _s5, 5, bits), \
+ MAX1363_CHAN_U(6, _s6, 6, bits), \
+ MAX1363_CHAN_U(7, _s7, 7, bits), \
+ MAX1363_CHAN_B(0, 1, d0m1, 8, bits), \
+ MAX1363_CHAN_B(2, 3, d2m3, 9, bits), \
+ MAX1363_CHAN_B(4, 5, d4m5, 10, bits), \
+ MAX1363_CHAN_B(6, 7, d6m7, 11, bits), \
+ MAX1363_CHAN_B(1, 0, d1m0, 12, bits), \
+ MAX1363_CHAN_B(3, 2, d3m2, 13, bits), \
+ MAX1363_CHAN_B(5, 4, d5m4, 14, bits), \
+ MAX1363_CHAN_B(7, 6, d7m6, 15, bits), \
+ IIO_CHAN_SOFT_TIMESTAMP(16) \
+ }
+static struct iio_chan_spec max11602_channels[] = MAX1363_8X_CHANS(8);
+static struct iio_chan_spec max11608_channels[] = MAX1363_8X_CHANS(10);
+static struct iio_chan_spec max11614_channels[] = MAX1363_8X_CHANS(12);
+
+static const enum max1363_modes max11644_mode_list[] = {
+ _s0, _s1, s0to1, d0m1, d1m0,
};
-static struct attribute_group max11608_dev_attr_group = {
- .attrs = max11608_device_attrs,
-};
+#define MAX1363_2X_CHANS(bits) { \
+ MAX1363_CHAN_U(0, _s0, 0, bits), \
+ MAX1363_CHAN_U(1, _s1, 1, bits), \
+ MAX1363_CHAN_B(0, 1, d0m1, 2, bits), \
+ MAX1363_CHAN_B(1, 0, d1m0, 3, bits), \
+ IIO_CHAN_SOFT_TIMESTAMP(4) \
+ }
-static struct attribute *max11608_scan_el_attrs[] = {
- &iio_scan_el_in0.dev_attr.attr, &dev_attr_in0_type.attr,
- &iio_const_attr_in0_index.dev_attr.attr,
- &iio_scan_el_in1.dev_attr.attr, &dev_attr_in1_type.attr,
- &iio_const_attr_in1_index.dev_attr.attr,
- &iio_scan_el_in2.dev_attr.attr, &dev_attr_in2_type.attr,
- &iio_const_attr_in2_index.dev_attr.attr,
- &iio_scan_el_in3.dev_attr.attr, &dev_attr_in3_type.attr,
- &iio_const_attr_in3_index.dev_attr.attr,
- &iio_scan_el_in4.dev_attr.attr, &dev_attr_in4_type.attr,
- &iio_const_attr_in4_index.dev_attr.attr,
- &iio_scan_el_in5.dev_attr.attr, &dev_attr_in5_type.attr,
- &iio_const_attr_in5_index.dev_attr.attr,
- &iio_scan_el_in6.dev_attr.attr, &dev_attr_in6_type.attr,
- &iio_const_attr_in6_index.dev_attr.attr,
- &iio_scan_el_in7.dev_attr.attr, &dev_attr_in7_type.attr,
- &iio_const_attr_in7_index.dev_attr.attr,
- &iio_scan_el_in0min1.dev_attr.attr, &dev_attr_in0min1_type.attr,
- &iio_const_attr_in0min1_index.dev_attr.attr,
- &iio_scan_el_in2min3.dev_attr.attr, &dev_attr_in2min3_type.attr,
- &iio_const_attr_in2min3_index.dev_attr.attr,
- &iio_scan_el_in4min5.dev_attr.attr, &dev_attr_in4min5_type.attr,
- &iio_const_attr_in4min5_index.dev_attr.attr,
- &iio_scan_el_in6min7.dev_attr.attr, &dev_attr_in6min7_type.attr,
- &iio_const_attr_in6min7_index.dev_attr.attr,
- &iio_scan_el_in1min0.dev_attr.attr, &dev_attr_in1min0_type.attr,
- &iio_const_attr_in1min0_index.dev_attr.attr,
- &iio_scan_el_in3min2.dev_attr.attr, &dev_attr_in3min2_type.attr,
- &iio_const_attr_in3min2_index.dev_attr.attr,
- &iio_scan_el_in5min4.dev_attr.attr, &dev_attr_in5min4_type.attr,
- &iio_const_attr_in5min4_index.dev_attr.attr,
- &iio_scan_el_in7min6.dev_attr.attr, &dev_attr_in7min6_type.attr,
- &iio_const_attr_in7min6_index.dev_attr.attr,
- NULL
-};
-
-static struct attribute_group max11608_scan_el_group = {
- .name = "scan_elements",
- .attrs = max11608_scan_el_attrs,
-};
+static struct iio_chan_spec max11646_channels[] = MAX1363_2X_CHANS(10);
+static struct iio_chan_spec max11644_channels[] = MAX1363_2X_CHANS(12);
enum { max1361,
max1362,
@@ -643,354 +497,10 @@
max11615,
max11616,
max11617,
-};
-
-/* max1363 and max1368 tested - rest from data sheet */
-static const struct max1363_chip_info max1363_chip_info_tbl[] = {
- [max1361] = {
- .num_inputs = 4,
- .bits = 10,
- .int_vref_mv = 2048,
- .monitor_mode = 1,
- .mode_list = max1363_mode_list,
- .num_modes = ARRAY_SIZE(max1363_mode_list),
- .default_mode = s0to3,
- .dev_attrs = &max1363_dev_attr_group,
- .scan_attrs = &max1363_scan_el_group,
- },
- [max1362] = {
- .num_inputs = 4,
- .bits = 10,
- .int_vref_mv = 4096,
- .monitor_mode = 1,
- .mode_list = max1363_mode_list,
- .num_modes = ARRAY_SIZE(max1363_mode_list),
- .default_mode = s0to3,
- .dev_attrs = &max1363_dev_attr_group,
- .scan_attrs = &max1363_scan_el_group,
- },
- [max1363] = {
- .num_inputs = 4,
- .bits = 12,
- .int_vref_mv = 2048,
- .monitor_mode = 1,
- .mode_list = max1363_mode_list,
- .num_modes = ARRAY_SIZE(max1363_mode_list),
- .default_mode = s0to3,
- .dev_attrs = &max1363_dev_attr_group,
- .scan_attrs = &max1363_scan_el_group,
- },
- [max1364] = {
- .num_inputs = 4,
- .bits = 12,
- .int_vref_mv = 4096,
- .monitor_mode = 1,
- .mode_list = max1363_mode_list,
- .num_modes = ARRAY_SIZE(max1363_mode_list),
- .default_mode = s0to3,
- .dev_attrs = &max1363_dev_attr_group,
- .scan_attrs = &max1363_scan_el_group,
- },
- [max1036] = {
- .num_inputs = 4,
- .bits = 8,
- .int_vref_mv = 4096,
- .mode_list = max1236_mode_list,
- .num_modes = ARRAY_SIZE(max1236_mode_list),
- .default_mode = s0to3,
- .dev_attrs = &max1363_dev_attr_group,
- .scan_attrs = &max1363_scan_el_group,
- },
- [max1037] = {
- .num_inputs = 4,
- .bits = 8,
- .int_vref_mv = 2048,
- .mode_list = max1236_mode_list,
- .num_modes = ARRAY_SIZE(max1236_mode_list),
- .default_mode = s0to3,
- .dev_attrs = &max1363_dev_attr_group,
- .scan_attrs = &max1363_scan_el_group,
- },
- [max1038] = {
- .num_inputs = 12,
- .bits = 8,
- .int_vref_mv = 4096,
- .mode_list = max1238_mode_list,
- .num_modes = ARRAY_SIZE(max1238_mode_list),
- .default_mode = s0to11,
- .dev_attrs = &max1238_dev_attr_group,
- .scan_attrs = &max1238_scan_el_group,
- },
- [max1039] = {
- .num_inputs = 12,
- .bits = 8,
- .int_vref_mv = 2048,
- .mode_list = max1238_mode_list,
- .num_modes = ARRAY_SIZE(max1238_mode_list),
- .default_mode = s0to11,
- .dev_attrs = &max1238_dev_attr_group,
- .scan_attrs = &max1238_scan_el_group,
- },
- [max1136] = {
- .num_inputs = 4,
- .bits = 10,
- .int_vref_mv = 4096,
- .mode_list = max1236_mode_list,
- .num_modes = ARRAY_SIZE(max1236_mode_list),
- .default_mode = s0to3,
- .dev_attrs = &max1363_dev_attr_group,
- .scan_attrs = &max1363_scan_el_group,
- },
- [max1137] = {
- .num_inputs = 4,
- .bits = 10,
- .int_vref_mv = 2048,
- .mode_list = max1236_mode_list,
- .num_modes = ARRAY_SIZE(max1236_mode_list),
- .default_mode = s0to3,
- .dev_attrs = &max1363_dev_attr_group,
- .scan_attrs = &max1363_scan_el_group,
- },
- [max1138] = {
- .num_inputs = 12,
- .bits = 10,
- .int_vref_mv = 4096,
- .mode_list = max1238_mode_list,
- .num_modes = ARRAY_SIZE(max1238_mode_list),
- .default_mode = s0to11,
- .dev_attrs = &max1238_dev_attr_group,
- .scan_attrs = &max1238_scan_el_group,
- },
- [max1139] = {
- .num_inputs = 12,
- .bits = 10,
- .int_vref_mv = 2048,
- .mode_list = max1238_mode_list,
- .num_modes = ARRAY_SIZE(max1238_mode_list),
- .default_mode = s0to11,
- .dev_attrs = &max1238_dev_attr_group,
- .scan_attrs = &max1238_scan_el_group,
- },
- [max1236] = {
- .num_inputs = 4,
- .bits = 12,
- .int_vref_mv = 4096,
- .mode_list = max1236_mode_list,
- .num_modes = ARRAY_SIZE(max1236_mode_list),
- .default_mode = s0to3,
- .dev_attrs = &max1363_dev_attr_group,
- .scan_attrs = &max1363_scan_el_group,
- },
- [max1237] = {
- .num_inputs = 4,
- .bits = 12,
- .int_vref_mv = 2048,
- .mode_list = max1236_mode_list,
- .num_modes = ARRAY_SIZE(max1236_mode_list),
- .default_mode = s0to3,
- .dev_attrs = &max1363_dev_attr_group,
- .scan_attrs = &max1363_scan_el_group,
- },
- [max1238] = {
- .num_inputs = 12,
- .bits = 12,
- .int_vref_mv = 4096,
- .mode_list = max1238_mode_list,
- .num_modes = ARRAY_SIZE(max1238_mode_list),
- .default_mode = s0to11,
- .dev_attrs = &max1238_dev_attr_group,
- .scan_attrs = &max1238_scan_el_group,
- },
- [max1239] = {
- .num_inputs = 12,
- .bits = 12,
- .int_vref_mv = 2048,
- .mode_list = max1238_mode_list,
- .num_modes = ARRAY_SIZE(max1238_mode_list),
- .default_mode = s0to11,
- .dev_attrs = &max1238_dev_attr_group,
- .scan_attrs = &max1238_scan_el_group,
- },
- [max11600] = {
- .num_inputs = 4,
- .bits = 8,
- .int_vref_mv = 4096,
- .mode_list = max11607_mode_list,
- .num_modes = ARRAY_SIZE(max11607_mode_list),
- .default_mode = s0to3,
- .dev_attrs = &max1363_dev_attr_group,
- .scan_attrs = &max1363_scan_el_group,
- },
- [max11601] = {
- .num_inputs = 4,
- .bits = 8,
- .int_vref_mv = 2048,
- .mode_list = max11607_mode_list,
- .num_modes = ARRAY_SIZE(max11607_mode_list),
- .default_mode = s0to3,
- .dev_attrs = &max1363_dev_attr_group,
- .scan_attrs = &max1363_scan_el_group,
- },
- [max11602] = {
- .num_inputs = 8,
- .bits = 8,
- .int_vref_mv = 4096,
- .mode_list = max11608_mode_list,
- .num_modes = ARRAY_SIZE(max11608_mode_list),
- .default_mode = s0to7,
- .dev_attrs = &max11608_dev_attr_group,
- .scan_attrs = &max11608_scan_el_group,
- },
- [max11603] = {
- .num_inputs = 8,
- .bits = 8,
- .int_vref_mv = 2048,
- .mode_list = max11608_mode_list,
- .num_modes = ARRAY_SIZE(max11608_mode_list),
- .default_mode = s0to7,
- .dev_attrs = &max11608_dev_attr_group,
- .scan_attrs = &max11608_scan_el_group,
- },
- [max11604] = {
- .num_inputs = 12,
- .bits = 8,
- .int_vref_mv = 4098,
- .mode_list = max1238_mode_list,
- .num_modes = ARRAY_SIZE(max1238_mode_list),
- .default_mode = s0to11,
- .dev_attrs = &max1238_dev_attr_group,
- .scan_attrs = &max1238_scan_el_group,
- },
- [max11605] = {
- .num_inputs = 12,
- .bits = 8,
- .int_vref_mv = 2048,
- .mode_list = max1238_mode_list,
- .num_modes = ARRAY_SIZE(max1238_mode_list),
- .default_mode = s0to11,
- .dev_attrs = &max1238_dev_attr_group,
- .scan_attrs = &max1238_scan_el_group,
- },
- [max11606] = {
- .num_inputs = 4,
- .bits = 10,
- .int_vref_mv = 4096,
- .mode_list = max11607_mode_list,
- .num_modes = ARRAY_SIZE(max11607_mode_list),
- .default_mode = s0to3,
- .dev_attrs = &max1363_dev_attr_group,
- .scan_attrs = &max1363_scan_el_group,
- },
- [max11607] = {
- .num_inputs = 4,
- .bits = 10,
- .int_vref_mv = 2048,
- .mode_list = max11607_mode_list,
- .num_modes = ARRAY_SIZE(max11607_mode_list),
- .default_mode = s0to3,
- .dev_attrs = &max1363_dev_attr_group,
- .scan_attrs = &max1363_scan_el_group,
- },
- [max11608] = {
- .num_inputs = 8,
- .bits = 10,
- .int_vref_mv = 4096,
- .mode_list = max11608_mode_list,
- .num_modes = ARRAY_SIZE(max11608_mode_list),
- .default_mode = s0to7,
- .dev_attrs = &max11608_dev_attr_group,
- .scan_attrs = &max11608_scan_el_group,
- },
- [max11609] = {
- .num_inputs = 8,
- .bits = 10,
- .int_vref_mv = 2048,
- .mode_list = max11608_mode_list,
- .num_modes = ARRAY_SIZE(max11608_mode_list),
- .default_mode = s0to7,
- .dev_attrs = &max11608_dev_attr_group,
- .scan_attrs = &max11608_scan_el_group,
- },
- [max11610] = {
- .num_inputs = 12,
- .bits = 10,
- .int_vref_mv = 4098,
- .mode_list = max1238_mode_list,
- .num_modes = ARRAY_SIZE(max1238_mode_list),
- .default_mode = s0to11,
- .dev_attrs = &max1238_dev_attr_group,
- .scan_attrs = &max1238_scan_el_group,
- },
- [max11611] = {
- .num_inputs = 12,
- .bits = 10,
- .int_vref_mv = 2048,
- .mode_list = max1238_mode_list,
- .num_modes = ARRAY_SIZE(max1238_mode_list),
- .default_mode = s0to11,
- .dev_attrs = &max1238_dev_attr_group,
- .scan_attrs = &max1238_scan_el_group,
- },
- [max11612] = {
- .num_inputs = 4,
- .bits = 12,
- .int_vref_mv = 4096,
- .mode_list = max11607_mode_list,
- .num_modes = ARRAY_SIZE(max11607_mode_list),
- .default_mode = s0to3,
- .dev_attrs = &max1363_dev_attr_group,
- .scan_attrs = &max1363_scan_el_group,
- },
- [max11613] = {
- .num_inputs = 4,
- .bits = 12,
- .int_vref_mv = 2048,
- .mode_list = max11607_mode_list,
- .num_modes = ARRAY_SIZE(max11607_mode_list),
- .default_mode = s0to3,
- .dev_attrs = &max1363_dev_attr_group,
- .scan_attrs = &max1363_scan_el_group,
- },
- [max11614] = {
- .num_inputs = 8,
- .bits = 12,
- .int_vref_mv = 4096,
- .mode_list = max11608_mode_list,
- .num_modes = ARRAY_SIZE(max11608_mode_list),
- .default_mode = s0to7,
- .dev_attrs = &max11608_dev_attr_group,
- .scan_attrs = &max11608_scan_el_group,
- },
- [max11615] = {
- .num_inputs = 8,
- .bits = 12,
- .int_vref_mv = 2048,
- .mode_list = max11608_mode_list,
- .num_modes = ARRAY_SIZE(max11608_mode_list),
- .default_mode = s0to7,
- .dev_attrs = &max11608_dev_attr_group,
- .scan_attrs = &max11608_scan_el_group,
- },
- [max11616] = {
- .num_inputs = 12,
- .bits = 12,
- .int_vref_mv = 4098,
- .mode_list = max1238_mode_list,
- .num_modes = ARRAY_SIZE(max1238_mode_list),
- .default_mode = s0to11,
- .dev_attrs = &max1238_dev_attr_group,
- .scan_attrs = &max1238_scan_el_group,
- },
- [max11617] = {
- .num_inputs = 12,
- .bits = 12,
- .int_vref_mv = 2048,
- .mode_list = max1238_mode_list,
- .num_modes = ARRAY_SIZE(max1238_mode_list),
- .default_mode = s0to11,
- .dev_attrs = &max1238_dev_attr_group,
- .scan_attrs = &max1238_scan_el_group,
- }
+ max11644,
+ max11645,
+ max11646,
+ max11647
};
static const int max1363_monitor_speeds[] = { 133000, 665000, 33300, 16600,
@@ -1000,8 +510,7 @@
struct device_attribute *attr,
char *buf)
{
- struct iio_dev *dev_info = dev_get_drvdata(dev);
- struct max1363_state *st = iio_dev_get_devdata(dev_info);
+ struct max1363_state *st = iio_priv(dev_get_drvdata(dev));
return sprintf(buf, "%d\n", max1363_monitor_speeds[st->monitor_speed]);
}
@@ -1010,8 +519,8 @@
const char *buf,
size_t len)
{
- struct iio_dev *dev_info = dev_get_drvdata(dev);
- struct max1363_state *st = iio_dev_get_devdata(dev_info);
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ struct max1363_state *st = iio_priv(indio_dev);
int i, ret;
unsigned long val;
bool found = false;
@@ -1027,9 +536,9 @@
if (!found)
return -EINVAL;
- mutex_lock(&dev_info->mlock);
+ mutex_lock(&indio_dev->mlock);
st->monitor_speed = i;
- mutex_unlock(&dev_info->mlock);
+ mutex_unlock(&indio_dev->mlock);
return 0;
}
@@ -1041,52 +550,24 @@
static IIO_CONST_ATTR(sampling_frequency_available,
"133000 665000 33300 16600 8300 4200 2000 1000");
-static ssize_t max1363_show_thresh(struct device *dev,
- struct device_attribute *attr,
- char *buf,
- bool high)
+static int max1363_read_thresh(struct iio_dev *indio_dev,
+ int event_code,
+ int *val)
{
- struct iio_dev *dev_info = dev_get_drvdata(dev);
- struct max1363_state *st = iio_dev_get_devdata(dev_info);
- struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
-
- if (high)
- return sprintf(buf, "%d\n",
- st->thresh_high[this_attr->address]);
+ struct max1363_state *st = iio_priv(indio_dev);
+ if (IIO_EVENT_CODE_EXTRACT_DIR(event_code) == IIO_EV_DIR_FALLING)
+ *val = st->thresh_low[IIO_EVENT_CODE_EXTRACT_NUM(event_code)];
else
- return sprintf(buf, "%d\n",
- st->thresh_low[this_attr->address & 0x7]);
+ *val = st->thresh_high[IIO_EVENT_CODE_EXTRACT_NUM(event_code)];
+ return 0;
}
-static ssize_t max1363_show_thresh_low(struct device *dev,
- struct device_attribute *attr,
- char *buf)
+static int max1363_write_thresh(struct iio_dev *indio_dev,
+ int event_code,
+ int val)
{
- return max1363_show_thresh(dev, attr, buf, false);
-}
-
-static ssize_t max1363_show_thresh_high(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- return max1363_show_thresh(dev, attr, buf, true);
-}
-
-static ssize_t max1363_store_thresh_unsigned(struct device *dev,
- struct device_attribute *attr,
- const char *buf,
- size_t len,
- bool high)
-{
- struct iio_dev *dev_info = dev_get_drvdata(dev);
- struct max1363_state *st = iio_dev_get_devdata(dev_info);
- struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
- unsigned long val;
- int ret;
-
- ret = strict_strtoul(buf, 10, &val);
- if (ret)
- return -EINVAL;
+ struct max1363_state *st = iio_priv(indio_dev);
+ /* make it handle signed correctly as well */
switch (st->chip_info->bits) {
case 10:
if (val > 0x3FF)
@@ -1098,220 +579,60 @@
break;
}
- switch (high) {
- case 1:
- st->thresh_high[this_attr->address] = val;
+ switch (IIO_EVENT_CODE_EXTRACT_DIR(event_code)) {
+ case IIO_EV_DIR_FALLING:
+ st->thresh_low[IIO_EVENT_CODE_EXTRACT_NUM(event_code)] = val;
break;
- case 0:
- st->thresh_low[this_attr->address & 0x7] = val;
+ case IIO_EV_DIR_RISING:
+ st->thresh_high[IIO_EVENT_CODE_EXTRACT_NUM(event_code)] = val;
break;
}
- return len;
-}
-
-static ssize_t max1363_store_thresh_high_unsigned(struct device *dev,
- struct device_attribute *attr,
- const char *buf,
- size_t len)
-{
- return max1363_store_thresh_unsigned(dev, attr, buf, len, true);
-}
-
-static ssize_t max1363_store_thresh_low_unsigned(struct device *dev,
- struct device_attribute *attr,
- const char *buf,
- size_t len)
-{
- return max1363_store_thresh_unsigned(dev, attr, buf, len, false);
-}
-
-static ssize_t max1363_store_thresh_signed(struct device *dev,
- struct device_attribute *attr,
- const char *buf,
- size_t len,
- bool high)
-{
- struct iio_dev *dev_info = dev_get_drvdata(dev);
- struct max1363_state *st = iio_dev_get_devdata(dev_info);
- struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
- long val;
- int ret;
-
- ret = strict_strtol(buf, 10, &val);
- if (ret)
- return -EINVAL;
- switch (st->chip_info->bits) {
- case 10:
- if (val < -512 || val > 511)
- return -EINVAL;
- break;
- case 12:
- if (val < -2048 || val > 2047)
- return -EINVAL;
- break;
- }
-
- switch (high) {
- case 1:
- st->thresh_high[this_attr->address] = val;
- break;
- case 0:
- st->thresh_low[this_attr->address & 0x7] = val;
- break;
- }
-
- return len;
-}
-
-static ssize_t max1363_store_thresh_high_signed(struct device *dev,
- struct device_attribute *attr,
- const char *buf,
- size_t len)
-{
- return max1363_store_thresh_signed(dev, attr, buf, len, true);
-}
-
-static ssize_t max1363_store_thresh_low_signed(struct device *dev,
- struct device_attribute *attr,
- const char *buf,
- size_t len)
-{
- return max1363_store_thresh_signed(dev, attr, buf, len, false);
-}
-
-static IIO_DEVICE_ATTR(in0_thresh_high_value, S_IRUGO | S_IWUSR,
- max1363_show_thresh_high,
- max1363_store_thresh_high_unsigned, 0);
-static IIO_DEVICE_ATTR(in0_thresh_low_value, S_IRUGO | S_IWUSR,
- max1363_show_thresh_low,
- max1363_store_thresh_low_unsigned, 0);
-static IIO_DEVICE_ATTR(in1_thresh_high_value, S_IRUGO | S_IWUSR,
- max1363_show_thresh_high,
- max1363_store_thresh_high_unsigned, 1);
-static IIO_DEVICE_ATTR(in1_thresh_low_value, S_IRUGO | S_IWUSR,
- max1363_show_thresh_low,
- max1363_store_thresh_low_unsigned, 1);
-static IIO_DEVICE_ATTR(in2_thresh_high_value, S_IRUGO | S_IWUSR,
- max1363_show_thresh_high,
- max1363_store_thresh_high_unsigned, 2);
-static IIO_DEVICE_ATTR(in2_thresh_low_value, S_IRUGO | S_IWUSR,
- max1363_show_thresh_low,
- max1363_store_thresh_low_unsigned, 2);
-static IIO_DEVICE_ATTR(in3_thresh_high_value, S_IRUGO | S_IWUSR,
- max1363_show_thresh_high,
- max1363_store_thresh_high_unsigned, 3);
-static IIO_DEVICE_ATTR(in3_thresh_low_value, S_IRUGO | S_IWUSR,
- max1363_show_thresh_low,
- max1363_store_thresh_low_unsigned, 3);
-
-static IIO_DEVICE_ATTR_NAMED(in0min1_thresh_high_value,
- in0-in1_thresh_high_value,
- S_IRUGO | S_IWUSR, max1363_show_thresh_high,
- max1363_store_thresh_high_signed, 4);
-static IIO_DEVICE_ATTR_NAMED(in0min1_thresh_low_value,
- in0-in1_thresh_low_value,
- S_IRUGO | S_IWUSR, max1363_show_thresh_low,
- max1363_store_thresh_low_signed, 4);
-static IIO_DEVICE_ATTR_NAMED(in2min3_thresh_high_value,
- in2-in3_thresh_high_value,
- S_IRUGO | S_IWUSR, max1363_show_thresh_high,
- max1363_store_thresh_high_signed, 5);
-static IIO_DEVICE_ATTR_NAMED(in2min3_thresh_low_value,
- in2-in3_thresh_low_value,
- S_IRUGO | S_IWUSR, max1363_show_thresh_low,
- max1363_store_thresh_low_signed, 5);
-static IIO_DEVICE_ATTR_NAMED(in1min0_thresh_high_value,
- in1-in0_thresh_high_value,
- S_IRUGO | S_IWUSR, max1363_show_thresh_high,
- max1363_store_thresh_high_signed, 6);
-static IIO_DEVICE_ATTR_NAMED(in1min0_thresh_low_value,
- in1-in0_thresh_low_value,
- S_IRUGO | S_IWUSR, max1363_show_thresh_low,
- max1363_store_thresh_low_signed, 6);
-static IIO_DEVICE_ATTR_NAMED(in3min2_thresh_high_value,
- in3-in2_thresh_high_value,
- S_IRUGO | S_IWUSR, max1363_show_thresh_high,
- max1363_store_thresh_high_signed, 7);
-static IIO_DEVICE_ATTR_NAMED(in3min2_thresh_low_value,
- in3-in2_thresh_low_value,
- S_IRUGO | S_IWUSR, max1363_show_thresh_low,
- max1363_store_thresh_low_signed, 7);
-
-static int max1363_int_th(struct iio_dev *dev_info,
- int index,
- s64 timestamp,
- int not_test)
-{
- struct max1363_state *st = dev_info->dev_data;
-
- st->last_timestamp = timestamp;
- schedule_work(&st->thresh_work);
return 0;
}
-static void max1363_thresh_handler_bh(struct work_struct *work_s)
+static const int max1363_event_codes[] = {
+ IIO_EVENT_CODE_IN_LOW_THRESH(3), IIO_EVENT_CODE_IN_HIGH_THRESH(3),
+ IIO_EVENT_CODE_IN_LOW_THRESH(2), IIO_EVENT_CODE_IN_HIGH_THRESH(2),
+ IIO_EVENT_CODE_IN_LOW_THRESH(1), IIO_EVENT_CODE_IN_HIGH_THRESH(1),
+ IIO_EVENT_CODE_IN_LOW_THRESH(0), IIO_EVENT_CODE_IN_HIGH_THRESH(0)
+};
+
+static irqreturn_t max1363_event_handler(int irq, void *private)
{
- struct max1363_state *st = container_of(work_s, struct max1363_state,
- thresh_work);
+ struct iio_dev *indio_dev = private;
+ struct max1363_state *st = iio_priv(indio_dev);
+ s64 timestamp = iio_get_time_ns();
+ unsigned long mask, loc;
u8 rx;
u8 tx[2] = { st->setupbyte,
MAX1363_MON_INT_ENABLE | (st->monitor_speed << 1) | 0xF0 };
i2c_master_recv(st->client, &rx, 1);
- if (rx & (1 << 0))
- iio_push_event(st->indio_dev, 0,
- IIO_EVENT_CODE_IN_LOW_THRESH(3),
- st->last_timestamp);
- if (rx & (1 << 1))
- iio_push_event(st->indio_dev, 0,
- IIO_EVENT_CODE_IN_HIGH_THRESH(3),
- st->last_timestamp);
- if (rx & (1 << 2))
- iio_push_event(st->indio_dev, 0,
- IIO_EVENT_CODE_IN_LOW_THRESH(2),
- st->last_timestamp);
- if (rx & (1 << 3))
- iio_push_event(st->indio_dev, 0,
- IIO_EVENT_CODE_IN_HIGH_THRESH(2),
- st->last_timestamp);
- if (rx & (1 << 4))
- iio_push_event(st->indio_dev, 0,
- IIO_EVENT_CODE_IN_LOW_THRESH(1),
- st->last_timestamp);
- if (rx & (1 << 5))
- iio_push_event(st->indio_dev, 0,
- IIO_EVENT_CODE_IN_HIGH_THRESH(1),
- st->last_timestamp);
- if (rx & (1 << 6))
- iio_push_event(st->indio_dev, 0,
- IIO_EVENT_CODE_IN_LOW_THRESH(0),
- st->last_timestamp);
- if (rx & (1 << 7))
- iio_push_event(st->indio_dev, 0,
- IIO_EVENT_CODE_IN_HIGH_THRESH(0),
- st->last_timestamp);
- enable_irq(st->client->irq);
+ mask = rx;
+ for_each_set_bit(loc, &mask, 8)
+ iio_push_event(indio_dev, 0, max1363_event_codes[loc],
+ timestamp);
i2c_master_send(st->client, tx, 2);
+
+ return IRQ_HANDLED;
}
-static ssize_t max1363_read_interrupt_config(struct device *dev,
- struct device_attribute *attr,
- char *buf)
+static int max1363_read_event_config(struct iio_dev *indio_dev,
+ int event_code)
{
- struct iio_dev *dev_info = dev_get_drvdata(dev);
- struct max1363_state *st = iio_dev_get_devdata(dev_info);
- struct iio_event_attr *this_attr = to_iio_event_attr(attr);
+ struct max1363_state *st = iio_priv(indio_dev);
+
int val;
-
- mutex_lock(&dev_info->mlock);
- if (this_attr->mask & 0x8)
- val = (1 << (this_attr->mask & 0x7)) & st->mask_low;
+ int number = IIO_EVENT_CODE_EXTRACT_NUM(event_code);
+ mutex_lock(&indio_dev->mlock);
+ if (IIO_EVENT_CODE_EXTRACT_DIR(event_code) == IIO_EV_DIR_FALLING)
+ val = (1 << number) & st->mask_low;
else
- val = (1 << this_attr->mask) & st->mask_high;
- mutex_unlock(&dev_info->mlock);
+ val = (1 << number) & st->mask_high;
+ mutex_unlock(&indio_dev->mlock);
- return sprintf(buf, "%d\n", !!val);
+ return val;
}
static int max1363_monitor_mode_update(struct max1363_state *st, int enabled)
@@ -1428,6 +749,7 @@
* To keep this manageable we always use one of 3 scan modes.
* Scan 0...3, 0-1,2-3 and 1-0,3-2
*/
+
static inline int __max1363_check_event_mask(int thismask, int checkmask)
{
int ret = 0;
@@ -1448,206 +770,54 @@
return ret;
}
-static ssize_t max1363_write_interrupt_config(struct device *dev,
- struct device_attribute *attr,
- const char *buf,
- size_t len)
+static int max1363_write_event_config(struct iio_dev *indio_dev,
+ int event_code,
+ int state)
{
- struct iio_dev *dev_info = dev_get_drvdata(dev);
- struct max1363_state *st = iio_dev_get_devdata(dev_info);
- struct iio_event_attr *this_attr = to_iio_event_attr(attr);
- unsigned long val;
- int ret;
+ int ret = 0;
+ struct max1363_state *st = iio_priv(indio_dev);
u16 unifiedmask;
- ret = strict_strtoul(buf, 10, &val);
- if (ret)
- return -EINVAL;
- mutex_lock(&st->indio_dev->mlock);
+ int number = IIO_EVENT_CODE_EXTRACT_NUM(event_code);
+
+ mutex_lock(&indio_dev->mlock);
unifiedmask = st->mask_low | st->mask_high;
- if (this_attr->mask & 0x08) {
- /* If we are disabling no need to test */
- if (val == 0)
- st->mask_low &= ~(1 << (this_attr->mask & 0x7));
+ if (IIO_EVENT_CODE_EXTRACT_DIR(event_code) == IIO_EV_DIR_FALLING) {
+
+ if (state == 0)
+ st->mask_low &= ~(1 << number);
else {
- ret = __max1363_check_event_mask(this_attr->mask & 0x7,
- unifiedmask);
+ ret = __max1363_check_event_mask((1 << number),
+ unifiedmask);
if (ret)
goto error_ret;
- st->mask_low |= (1 << (this_attr->mask & 0x7));
+ st->mask_low |= (1 << number);
}
} else {
- if (val == 0)
- st->mask_high &= ~(1 << (this_attr->mask));
+ if (state == 0)
+ st->mask_high &= ~(1 << number);
else {
- ret = __max1363_check_event_mask(this_attr->mask,
- unifiedmask);
+ ret = __max1363_check_event_mask((1 << number),
+ unifiedmask);
if (ret)
goto error_ret;
- st->mask_high |= (1 << this_attr->mask);
+ st->mask_high |= (1 << number);
}
}
- if (st->monitor_on && !st->mask_high && !st->mask_low)
- iio_remove_event_from_list(this_attr->listel,
- &dev_info->interrupts[0]->ev_list);
- if (!st->monitor_on && val)
- iio_add_event_to_list(this_attr->listel,
- &dev_info->interrupts[0]->ev_list);
max1363_monitor_mode_update(st, !!(st->mask_high | st->mask_low));
error_ret:
- mutex_unlock(&st->indio_dev->mlock);
+ mutex_unlock(&indio_dev->mlock);
- return len;
+ return ret;
}
-IIO_EVENT_SH(max1363_thresh, max1363_int_th);
-
-#define MAX1363_HIGH_THRESH(a) a
-#define MAX1363_LOW_THRESH(a) (a | 0x8)
-
-IIO_EVENT_ATTR_SH(in0_thresh_high_en,
- iio_event_max1363_thresh,
- max1363_read_interrupt_config,
- max1363_write_interrupt_config,
- MAX1363_HIGH_THRESH(0));
-
-IIO_EVENT_ATTR_SH(in0_thresh_low_en,
- iio_event_max1363_thresh,
- max1363_read_interrupt_config,
- max1363_write_interrupt_config,
- MAX1363_LOW_THRESH(0));
-
-IIO_EVENT_ATTR_SH(in1_thresh_high_en,
- iio_event_max1363_thresh,
- max1363_read_interrupt_config,
- max1363_write_interrupt_config,
- MAX1363_HIGH_THRESH(1));
-
-IIO_EVENT_ATTR_SH(in1_thresh_low_en,
- iio_event_max1363_thresh,
- max1363_read_interrupt_config,
- max1363_write_interrupt_config,
- MAX1363_LOW_THRESH(1));
-
-IIO_EVENT_ATTR_SH(in2_thresh_high_en,
- iio_event_max1363_thresh,
- max1363_read_interrupt_config,
- max1363_write_interrupt_config,
- MAX1363_HIGH_THRESH(2));
-
-IIO_EVENT_ATTR_SH(in2_thresh_low_en,
- iio_event_max1363_thresh,
- max1363_read_interrupt_config,
- max1363_write_interrupt_config,
- MAX1363_LOW_THRESH(2));
-
-IIO_EVENT_ATTR_SH(in3_thresh_high_en,
- iio_event_max1363_thresh,
- max1363_read_interrupt_config,
- max1363_write_interrupt_config,
- MAX1363_HIGH_THRESH(3));
-
-IIO_EVENT_ATTR_SH(in3_thresh_low_en,
- iio_event_max1363_thresh,
- max1363_read_interrupt_config,
- max1363_write_interrupt_config,
- MAX1363_LOW_THRESH(3));
-
-IIO_EVENT_ATTR_NAMED_SH(in0min1_thresh_high_en,
- in0-in1_thresh_high_en,
- iio_event_max1363_thresh,
- max1363_read_interrupt_config,
- max1363_write_interrupt_config,
- MAX1363_HIGH_THRESH(4));
-
-IIO_EVENT_ATTR_NAMED_SH(in0min1_thresh_low_en,
- in0-in1_thresh_low_en,
- iio_event_max1363_thresh,
- max1363_read_interrupt_config,
- max1363_write_interrupt_config,
- MAX1363_LOW_THRESH(4));
-
-IIO_EVENT_ATTR_NAMED_SH(in3min2_thresh_high_en,
- in3-in2_thresh_high_en,
- iio_event_max1363_thresh,
- max1363_read_interrupt_config,
- max1363_write_interrupt_config,
- MAX1363_HIGH_THRESH(5));
-
-IIO_EVENT_ATTR_NAMED_SH(in3min2_thresh_low_en,
- in3-in2_thresh_low_en,
- iio_event_max1363_thresh,
- max1363_read_interrupt_config,
- max1363_write_interrupt_config,
- MAX1363_LOW_THRESH(5));
-
-IIO_EVENT_ATTR_NAMED_SH(in1min0_thresh_high_en,
- in1-in0_thresh_high_en,
- iio_event_max1363_thresh,
- max1363_read_interrupt_config,
- max1363_write_interrupt_config,
- MAX1363_HIGH_THRESH(6));
-
-IIO_EVENT_ATTR_NAMED_SH(in1min0_thresh_low_en,
- in1-in0_thresh_low_en,
- iio_event_max1363_thresh,
- max1363_read_interrupt_config,
- max1363_write_interrupt_config,
- MAX1363_LOW_THRESH(6));
-
-IIO_EVENT_ATTR_NAMED_SH(in2min3_thresh_high_en,
- in2-in3_thresh_high_en,
- iio_event_max1363_thresh,
- max1363_read_interrupt_config,
- max1363_write_interrupt_config,
- MAX1363_HIGH_THRESH(7));
-
-IIO_EVENT_ATTR_NAMED_SH(in2min3_thresh_low_en,
- in2-in3_thresh_low_en,
- iio_event_max1363_thresh,
- max1363_read_interrupt_config,
- max1363_write_interrupt_config,
- MAX1363_LOW_THRESH(7));
-
/*
* As with scan_elements, only certain sets of these can
* be combined.
*/
static struct attribute *max1363_event_attributes[] = {
- &iio_dev_attr_in0_thresh_high_value.dev_attr.attr,
- &iio_dev_attr_in0_thresh_low_value.dev_attr.attr,
- &iio_dev_attr_in1_thresh_high_value.dev_attr.attr,
- &iio_dev_attr_in1_thresh_low_value.dev_attr.attr,
- &iio_dev_attr_in2_thresh_high_value.dev_attr.attr,
- &iio_dev_attr_in2_thresh_low_value.dev_attr.attr,
- &iio_dev_attr_in3_thresh_high_value.dev_attr.attr,
- &iio_dev_attr_in3_thresh_low_value.dev_attr.attr,
- &iio_dev_attr_in0min1_thresh_high_value.dev_attr.attr,
- &iio_dev_attr_in0min1_thresh_low_value.dev_attr.attr,
- &iio_dev_attr_in2min3_thresh_high_value.dev_attr.attr,
- &iio_dev_attr_in2min3_thresh_low_value.dev_attr.attr,
- &iio_dev_attr_in1min0_thresh_high_value.dev_attr.attr,
- &iio_dev_attr_in1min0_thresh_low_value.dev_attr.attr,
- &iio_dev_attr_in3min2_thresh_high_value.dev_attr.attr,
- &iio_dev_attr_in3min2_thresh_low_value.dev_attr.attr,
&iio_dev_attr_sampling_frequency.dev_attr.attr,
&iio_const_attr_sampling_frequency_available.dev_attr.attr,
- &iio_event_attr_in0_thresh_high_en.dev_attr.attr,
- &iio_event_attr_in0_thresh_low_en.dev_attr.attr,
- &iio_event_attr_in1_thresh_high_en.dev_attr.attr,
- &iio_event_attr_in1_thresh_low_en.dev_attr.attr,
- &iio_event_attr_in2_thresh_high_en.dev_attr.attr,
- &iio_event_attr_in2_thresh_low_en.dev_attr.attr,
- &iio_event_attr_in3_thresh_high_en.dev_attr.attr,
- &iio_event_attr_in3_thresh_low_en.dev_attr.attr,
- &iio_event_attr_in0min1_thresh_high_en.dev_attr.attr,
- &iio_event_attr_in0min1_thresh_low_en.dev_attr.attr,
- &iio_event_attr_in3min2_thresh_high_en.dev_attr.attr,
- &iio_event_attr_in3min2_thresh_low_en.dev_attr.attr,
- &iio_event_attr_in1min0_thresh_high_en.dev_attr.attr,
- &iio_event_attr_in1min0_thresh_low_en.dev_attr.attr,
- &iio_event_attr_in2min3_thresh_high_en.dev_attr.attr,
- &iio_event_attr_in2min3_thresh_low_en.dev_attr.attr,
NULL,
};
@@ -1655,6 +825,411 @@
.attrs = max1363_event_attributes,
};
+#define MAX1363_EVENT_FUNCS \
+
+
+static const struct iio_info max1238_info = {
+ .read_raw = &max1363_read_raw,
+ .driver_module = THIS_MODULE,
+};
+
+static const struct iio_info max1363_info = {
+ .read_event_value = &max1363_read_thresh,
+ .write_event_value = &max1363_write_thresh,
+ .read_event_config = &max1363_read_event_config,
+ .write_event_config = &max1363_write_event_config,
+ .read_raw = &max1363_read_raw,
+ .driver_module = THIS_MODULE,
+ .num_interrupt_lines = 1,
+ .event_attrs = &max1363_event_attribute_group,
+};
+
+/* max1363 and max1368 tested - rest from data sheet */
+static const struct max1363_chip_info max1363_chip_info_tbl[] = {
+ [max1361] = {
+ .bits = 10,
+ .int_vref_mv = 2048,
+ .mode_list = max1363_mode_list,
+ .num_modes = ARRAY_SIZE(max1363_mode_list),
+ .default_mode = s0to3,
+ .channels = max1361_channels,
+ .num_channels = ARRAY_SIZE(max1361_channels),
+ .info = &max1363_info,
+ },
+ [max1362] = {
+ .bits = 10,
+ .int_vref_mv = 4096,
+ .mode_list = max1363_mode_list,
+ .num_modes = ARRAY_SIZE(max1363_mode_list),
+ .default_mode = s0to3,
+ .channels = max1361_channels,
+ .num_channels = ARRAY_SIZE(max1361_channels),
+ .info = &max1363_info,
+ },
+ [max1363] = {
+ .bits = 12,
+ .int_vref_mv = 2048,
+ .mode_list = max1363_mode_list,
+ .num_modes = ARRAY_SIZE(max1363_mode_list),
+ .default_mode = s0to3,
+ .channels = max1363_channels,
+ .num_channels = ARRAY_SIZE(max1363_channels),
+ .info = &max1363_info,
+ },
+ [max1364] = {
+ .bits = 12,
+ .int_vref_mv = 4096,
+ .mode_list = max1363_mode_list,
+ .num_modes = ARRAY_SIZE(max1363_mode_list),
+ .default_mode = s0to3,
+ .channels = max1363_channels,
+ .num_channels = ARRAY_SIZE(max1363_channels),
+ .info = &max1363_info,
+ },
+ [max1036] = {
+ .bits = 8,
+ .int_vref_mv = 4096,
+ .mode_list = max1236_mode_list,
+ .num_modes = ARRAY_SIZE(max1236_mode_list),
+ .default_mode = s0to3,
+ .info = &max1238_info,
+ .channels = max1036_channels,
+ .num_channels = ARRAY_SIZE(max1036_channels),
+ },
+ [max1037] = {
+ .bits = 8,
+ .int_vref_mv = 2048,
+ .mode_list = max1236_mode_list,
+ .num_modes = ARRAY_SIZE(max1236_mode_list),
+ .default_mode = s0to3,
+ .info = &max1238_info,
+ .channels = max1036_channels,
+ .num_channels = ARRAY_SIZE(max1036_channels),
+ },
+ [max1038] = {
+ .bits = 8,
+ .int_vref_mv = 4096,
+ .mode_list = max1238_mode_list,
+ .num_modes = ARRAY_SIZE(max1238_mode_list),
+ .default_mode = s0to11,
+ .info = &max1238_info,
+ .channels = max1038_channels,
+ .num_channels = ARRAY_SIZE(max1038_channels),
+ },
+ [max1039] = {
+ .bits = 8,
+ .int_vref_mv = 2048,
+ .mode_list = max1238_mode_list,
+ .num_modes = ARRAY_SIZE(max1238_mode_list),
+ .default_mode = s0to11,
+ .info = &max1238_info,
+ .channels = max1038_channels,
+ .num_channels = ARRAY_SIZE(max1038_channels),
+ },
+ [max1136] = {
+ .bits = 10,
+ .int_vref_mv = 4096,
+ .mode_list = max1236_mode_list,
+ .num_modes = ARRAY_SIZE(max1236_mode_list),
+ .default_mode = s0to3,
+ .info = &max1238_info,
+ .channels = max1136_channels,
+ .num_channels = ARRAY_SIZE(max1136_channels),
+ },
+ [max1137] = {
+ .bits = 10,
+ .int_vref_mv = 2048,
+ .mode_list = max1236_mode_list,
+ .num_modes = ARRAY_SIZE(max1236_mode_list),
+ .default_mode = s0to3,
+ .info = &max1238_info,
+ .channels = max1136_channels,
+ .num_channels = ARRAY_SIZE(max1136_channels),
+ },
+ [max1138] = {
+ .bits = 10,
+ .int_vref_mv = 4096,
+ .mode_list = max1238_mode_list,
+ .num_modes = ARRAY_SIZE(max1238_mode_list),
+ .default_mode = s0to11,
+ .info = &max1238_info,
+ .channels = max1138_channels,
+ .num_channels = ARRAY_SIZE(max1138_channels),
+ },
+ [max1139] = {
+ .bits = 10,
+ .int_vref_mv = 2048,
+ .mode_list = max1238_mode_list,
+ .num_modes = ARRAY_SIZE(max1238_mode_list),
+ .default_mode = s0to11,
+ .info = &max1238_info,
+ .channels = max1138_channels,
+ .num_channels = ARRAY_SIZE(max1138_channels),
+ },
+ [max1236] = {
+ .bits = 12,
+ .int_vref_mv = 4096,
+ .mode_list = max1236_mode_list,
+ .num_modes = ARRAY_SIZE(max1236_mode_list),
+ .default_mode = s0to3,
+ .info = &max1238_info,
+ .channels = max1236_channels,
+ .num_channels = ARRAY_SIZE(max1236_channels),
+ },
+ [max1237] = {
+ .bits = 12,
+ .int_vref_mv = 2048,
+ .mode_list = max1236_mode_list,
+ .num_modes = ARRAY_SIZE(max1236_mode_list),
+ .default_mode = s0to3,
+ .info = &max1238_info,
+ .channels = max1236_channels,
+ .num_channels = ARRAY_SIZE(max1236_channels),
+ },
+ [max1238] = {
+ .bits = 12,
+ .int_vref_mv = 4096,
+ .mode_list = max1238_mode_list,
+ .num_modes = ARRAY_SIZE(max1238_mode_list),
+ .default_mode = s0to11,
+ .info = &max1238_info,
+ .channels = max1238_channels,
+ .num_channels = ARRAY_SIZE(max1238_channels),
+ },
+ [max1239] = {
+ .bits = 12,
+ .int_vref_mv = 2048,
+ .mode_list = max1238_mode_list,
+ .num_modes = ARRAY_SIZE(max1238_mode_list),
+ .default_mode = s0to11,
+ .info = &max1238_info,
+ .channels = max1238_channels,
+ .num_channels = ARRAY_SIZE(max1238_channels),
+ },
+ [max11600] = {
+ .bits = 8,
+ .int_vref_mv = 4096,
+ .mode_list = max11607_mode_list,
+ .num_modes = ARRAY_SIZE(max11607_mode_list),
+ .default_mode = s0to3,
+ .info = &max1238_info,
+ .channels = max1036_channels,
+ .num_channels = ARRAY_SIZE(max1036_channels),
+ },
+ [max11601] = {
+ .bits = 8,
+ .int_vref_mv = 2048,
+ .mode_list = max11607_mode_list,
+ .num_modes = ARRAY_SIZE(max11607_mode_list),
+ .default_mode = s0to3,
+ .info = &max1238_info,
+ .channels = max1036_channels,
+ .num_channels = ARRAY_SIZE(max1036_channels),
+ },
+ [max11602] = {
+ .bits = 8,
+ .int_vref_mv = 4096,
+ .mode_list = max11608_mode_list,
+ .num_modes = ARRAY_SIZE(max11608_mode_list),
+ .default_mode = s0to7,
+ .info = &max1238_info,
+ .channels = max11602_channels,
+ .num_channels = ARRAY_SIZE(max11602_channels),
+ },
+ [max11603] = {
+ .bits = 8,
+ .int_vref_mv = 2048,
+ .mode_list = max11608_mode_list,
+ .num_modes = ARRAY_SIZE(max11608_mode_list),
+ .default_mode = s0to7,
+ .info = &max1238_info,
+ .channels = max11602_channels,
+ .num_channels = ARRAY_SIZE(max11602_channels),
+ },
+ [max11604] = {
+ .bits = 8,
+ .int_vref_mv = 4098,
+ .mode_list = max1238_mode_list,
+ .num_modes = ARRAY_SIZE(max1238_mode_list),
+ .default_mode = s0to11,
+ .info = &max1238_info,
+ .channels = max1238_channels,
+ .num_channels = ARRAY_SIZE(max1238_channels),
+ },
+ [max11605] = {
+ .bits = 8,
+ .int_vref_mv = 2048,
+ .mode_list = max1238_mode_list,
+ .num_modes = ARRAY_SIZE(max1238_mode_list),
+ .default_mode = s0to11,
+ .info = &max1238_info,
+ .channels = max1238_channels,
+ .num_channels = ARRAY_SIZE(max1238_channels),
+ },
+ [max11606] = {
+ .bits = 10,
+ .int_vref_mv = 4096,
+ .mode_list = max11607_mode_list,
+ .num_modes = ARRAY_SIZE(max11607_mode_list),
+ .default_mode = s0to3,
+ .info = &max1238_info,
+ .channels = max1136_channels,
+ .num_channels = ARRAY_SIZE(max1136_channels),
+ },
+ [max11607] = {
+ .bits = 10,
+ .int_vref_mv = 2048,
+ .mode_list = max11607_mode_list,
+ .num_modes = ARRAY_SIZE(max11607_mode_list),
+ .default_mode = s0to3,
+ .info = &max1238_info,
+ .channels = max1136_channels,
+ .num_channels = ARRAY_SIZE(max1136_channels),
+ },
+ [max11608] = {
+ .bits = 10,
+ .int_vref_mv = 4096,
+ .mode_list = max11608_mode_list,
+ .num_modes = ARRAY_SIZE(max11608_mode_list),
+ .default_mode = s0to7,
+ .info = &max1238_info,
+ .channels = max11608_channels,
+ .num_channels = ARRAY_SIZE(max11608_channels),
+ },
+ [max11609] = {
+ .bits = 10,
+ .int_vref_mv = 2048,
+ .mode_list = max11608_mode_list,
+ .num_modes = ARRAY_SIZE(max11608_mode_list),
+ .default_mode = s0to7,
+ .info = &max1238_info,
+ .channels = max11608_channels,
+ .num_channels = ARRAY_SIZE(max11608_channels),
+ },
+ [max11610] = {
+ .bits = 10,
+ .int_vref_mv = 4098,
+ .mode_list = max1238_mode_list,
+ .num_modes = ARRAY_SIZE(max1238_mode_list),
+ .default_mode = s0to11,
+ .info = &max1238_info,
+ .channels = max1238_channels,
+ .num_channels = ARRAY_SIZE(max1238_channels),
+ },
+ [max11611] = {
+ .bits = 10,
+ .int_vref_mv = 2048,
+ .mode_list = max1238_mode_list,
+ .num_modes = ARRAY_SIZE(max1238_mode_list),
+ .default_mode = s0to11,
+ .info = &max1238_info,
+ .channels = max1238_channels,
+ .num_channels = ARRAY_SIZE(max1238_channels),
+ },
+ [max11612] = {
+ .bits = 12,
+ .int_vref_mv = 4096,
+ .mode_list = max11607_mode_list,
+ .num_modes = ARRAY_SIZE(max11607_mode_list),
+ .default_mode = s0to3,
+ .info = &max1238_info,
+ .channels = max1363_channels,
+ .num_channels = ARRAY_SIZE(max1363_channels),
+ },
+ [max11613] = {
+ .bits = 12,
+ .int_vref_mv = 2048,
+ .mode_list = max11607_mode_list,
+ .num_modes = ARRAY_SIZE(max11607_mode_list),
+ .default_mode = s0to3,
+ .info = &max1238_info,
+ .channels = max1363_channels,
+ .num_channels = ARRAY_SIZE(max1363_channels),
+ },
+ [max11614] = {
+ .bits = 12,
+ .int_vref_mv = 4096,
+ .mode_list = max11608_mode_list,
+ .num_modes = ARRAY_SIZE(max11608_mode_list),
+ .default_mode = s0to7,
+ .info = &max1238_info,
+ .channels = max11614_channels,
+ .num_channels = ARRAY_SIZE(max11614_channels),
+ },
+ [max11615] = {
+ .bits = 12,
+ .int_vref_mv = 2048,
+ .mode_list = max11608_mode_list,
+ .num_modes = ARRAY_SIZE(max11608_mode_list),
+ .default_mode = s0to7,
+ .info = &max1238_info,
+ .channels = max11614_channels,
+ .num_channels = ARRAY_SIZE(max11614_channels),
+ },
+ [max11616] = {
+ .bits = 12,
+ .int_vref_mv = 4098,
+ .mode_list = max1238_mode_list,
+ .num_modes = ARRAY_SIZE(max1238_mode_list),
+ .default_mode = s0to11,
+ .info = &max1238_info,
+ .channels = max1238_channels,
+ .num_channels = ARRAY_SIZE(max1238_channels),
+ },
+ [max11617] = {
+ .bits = 12,
+ .int_vref_mv = 2048,
+ .mode_list = max1238_mode_list,
+ .num_modes = ARRAY_SIZE(max1238_mode_list),
+ .default_mode = s0to11,
+ .info = &max1238_info,
+ .channels = max1238_channels,
+ .num_channels = ARRAY_SIZE(max1238_channels),
+ },
+ [max11644] = {
+ .bits = 12,
+ .int_vref_mv = 2048,
+ .mode_list = max11644_mode_list,
+ .num_modes = ARRAY_SIZE(max11644_mode_list),
+ .default_mode = s0to1,
+ .info = &max1238_info,
+ .channels = max11644_channels,
+ .num_channels = ARRAY_SIZE(max11644_channels),
+ },
+ [max11645] = {
+ .bits = 12,
+ .int_vref_mv = 4096,
+ .mode_list = max11644_mode_list,
+ .num_modes = ARRAY_SIZE(max11644_mode_list),
+ .default_mode = s0to1,
+ .info = &max1238_info,
+ .channels = max11644_channels,
+ .num_channels = ARRAY_SIZE(max11644_channels),
+ },
+ [max11646] = {
+ .bits = 10,
+ .int_vref_mv = 2048,
+ .mode_list = max11644_mode_list,
+ .num_modes = ARRAY_SIZE(max11644_mode_list),
+ .default_mode = s0to1,
+ .info = &max1238_info,
+ .channels = max11646_channels,
+ .num_channels = ARRAY_SIZE(max11646_channels),
+ },
+ [max11647] = {
+ .bits = 10,
+ .int_vref_mv = 4096,
+ .mode_list = max11644_mode_list,
+ .num_modes = ARRAY_SIZE(max11644_mode_list),
+ .default_mode = s0to1,
+ .info = &max1238_info,
+ .channels = max11646_channels,
+ .num_channels = ARRAY_SIZE(max11646_channels),
+ },
+};
+
+
+
static int max1363_initial_setup(struct max1363_state *st)
{
st->setupbyte = MAX1363_SETUP_AIN3_IS_AIN3_REF_IS_VDD
@@ -1675,126 +1250,116 @@
const struct i2c_device_id *id)
{
int ret, i, regdone = 0;
- struct max1363_state *st = kzalloc(sizeof(*st), GFP_KERNEL);
- if (st == NULL) {
- ret = -ENOMEM;
- goto error_ret;
- }
+ struct max1363_state *st;
+ struct iio_dev *indio_dev;
+ struct regulator *reg;
- /* this is only used for device removal purposes */
- i2c_set_clientdata(client, st);
-
- atomic_set(&st->protect_ring, 0);
-
- st->chip_info = &max1363_chip_info_tbl[id->driver_data];
- st->reg = regulator_get(&client->dev, "vcc");
- if (!IS_ERR(st->reg)) {
- ret = regulator_enable(st->reg);
+ reg = regulator_get(&client->dev, "vcc");
+ if (!IS_ERR(reg)) {
+ ret = regulator_enable(reg);
if (ret)
goto error_put_reg;
}
- st->client = client;
- st->indio_dev = iio_allocate_device();
- if (st->indio_dev == NULL) {
+ indio_dev = iio_allocate_device(sizeof(struct max1363_state));
+ if (indio_dev == NULL) {
ret = -ENOMEM;
goto error_disable_reg;
}
+ st = iio_priv(indio_dev);
+ st->reg = reg;
+ /* this is only used for device removal purposes */
+ i2c_set_clientdata(client, indio_dev);
- st->indio_dev->available_scan_masks
- = kzalloc(sizeof(*st->indio_dev->available_scan_masks)*
+ st->chip_info = &max1363_chip_info_tbl[id->driver_data];
+ st->client = client;
+
+ indio_dev->available_scan_masks
+ = kzalloc(sizeof(*indio_dev->available_scan_masks)*
(st->chip_info->num_modes + 1), GFP_KERNEL);
- if (!st->indio_dev->available_scan_masks) {
+ if (!indio_dev->available_scan_masks) {
ret = -ENOMEM;
goto error_free_device;
}
for (i = 0; i < st->chip_info->num_modes; i++)
- st->indio_dev->available_scan_masks[i] =
+ indio_dev->available_scan_masks[i] =
max1363_mode_table[st->chip_info->mode_list[i]]
.modemask;
/* Estabilish that the iio_dev is a child of the i2c device */
- st->indio_dev->dev.parent = &client->dev;
- st->indio_dev->attrs = st->chip_info->dev_attrs;
+ indio_dev->dev.parent = &client->dev;
+ indio_dev->name = id->name;
- /* Todo: this shouldn't be here. */
- st->indio_dev->dev_data = (void *)(st);
- st->indio_dev->driver_module = THIS_MODULE;
- st->indio_dev->modes = INDIO_DIRECT_MODE;
- if (st->chip_info->monitor_mode && client->irq) {
- st->indio_dev->num_interrupt_lines = 1;
- st->indio_dev->event_attrs
- = &max1363_event_attribute_group;
- }
-
+ indio_dev->info = st->chip_info->info;
+ indio_dev->modes = INDIO_DIRECT_MODE;
ret = max1363_initial_setup(st);
+ if (ret < 0)
+ goto error_free_available_scan_masks;
+
+ ret = max1363_register_ring_funcs_and_init(indio_dev);
if (ret)
goto error_free_available_scan_masks;
- ret = max1363_register_ring_funcs_and_init(st->indio_dev);
- if (ret)
- goto error_free_available_scan_masks;
-
- ret = iio_device_register(st->indio_dev);
+ ret = iio_device_register(indio_dev);
if (ret)
goto error_cleanup_ring;
regdone = 1;
- ret = iio_ring_buffer_register(st->indio_dev->ring, 0);
+ ret = iio_ring_buffer_register_ex(indio_dev->ring, 0,
+ st->chip_info->channels,
+ st->chip_info->num_channels);
if (ret)
goto error_cleanup_ring;
- if (st->chip_info->monitor_mode && client->irq) {
- ret = iio_register_interrupt_line(client->irq,
- st->indio_dev,
- 0,
- IRQF_TRIGGER_RISING,
- client->name);
+ if (client->irq) {
+ ret = request_threaded_irq(st->client->irq,
+ NULL,
+ &max1363_event_handler,
+ IRQF_TRIGGER_RISING | IRQF_ONESHOT,
+ "max1363_event",
+ indio_dev);
+
if (ret)
goto error_uninit_ring;
-
- INIT_WORK(&st->thresh_work, max1363_thresh_handler_bh);
}
return 0;
error_uninit_ring:
- iio_ring_buffer_unregister(st->indio_dev->ring);
+ iio_ring_buffer_unregister(indio_dev->ring);
error_cleanup_ring:
- max1363_ring_cleanup(st->indio_dev);
+ max1363_ring_cleanup(indio_dev);
error_free_available_scan_masks:
- kfree(st->indio_dev->available_scan_masks);
+ kfree(indio_dev->available_scan_masks);
error_free_device:
if (!regdone)
- iio_free_device(st->indio_dev);
+ iio_free_device(indio_dev);
else
- iio_device_unregister(st->indio_dev);
+ iio_device_unregister(indio_dev);
error_disable_reg:
if (!IS_ERR(st->reg))
regulator_disable(st->reg);
error_put_reg:
if (!IS_ERR(st->reg))
regulator_put(st->reg);
- kfree(st);
-error_ret:
return ret;
}
static int max1363_remove(struct i2c_client *client)
{
- struct max1363_state *st = i2c_get_clientdata(client);
- struct iio_dev *indio_dev = st->indio_dev;
+ struct iio_dev *indio_dev = i2c_get_clientdata(client);
+ struct max1363_state *st = iio_priv(indio_dev);
+ struct regulator *reg = st->reg;
- if (st->chip_info->monitor_mode && client->irq)
- iio_unregister_interrupt_line(st->indio_dev, 0);
+ if (client->irq)
+ free_irq(st->client->irq, indio_dev);
iio_ring_buffer_unregister(indio_dev->ring);
max1363_ring_cleanup(indio_dev);
- kfree(st->indio_dev->available_scan_masks);
- iio_device_unregister(indio_dev);
- if (!IS_ERR(st->reg)) {
- regulator_disable(st->reg);
- regulator_put(st->reg);
+ kfree(indio_dev->available_scan_masks);
+ if (!IS_ERR(reg)) {
+ regulator_disable(reg);
+ regulator_put(reg);
}
- kfree(st);
+ iio_device_unregister(indio_dev);
return 0;
}
diff --git a/drivers/staging/iio/adc/max1363_ring.c b/drivers/staging/iio/adc/max1363_ring.c
index d36fcc6..f43befd 100644
--- a/drivers/staging/iio/adc/max1363_ring.c
+++ b/drivers/staging/iio/adc/max1363_ring.c
@@ -9,8 +9,6 @@
*/
#include <linux/interrupt.h>
-#include <linux/gpio.h>
-#include <linux/workqueue.h>
#include <linux/device.h>
#include <linux/slab.h>
#include <linux/kernel.h>
@@ -27,10 +25,9 @@
#include "max1363.h"
-/* Todo: test this */
int max1363_single_channel_from_ring(long mask, struct max1363_state *st)
{
- struct iio_ring_buffer *ring = st->indio_dev->ring;
+ struct iio_ring_buffer *ring = iio_priv_to_dev(st)->ring;
int count = 0, ret;
u8 *ring_data;
if (!(st->current_mode->modemask & mask)) {
@@ -38,12 +35,13 @@
goto error_ret;
}
- ring_data = kmalloc(ring->access.get_bytes_per_datum(ring), GFP_KERNEL);
+ ring_data = kmalloc(ring->access->get_bytes_per_datum(ring),
+ GFP_KERNEL);
if (ring_data == NULL) {
ret = -ENOMEM;
goto error_ret;
}
- ret = ring->access.read_last(ring, ring_data);
+ ret = ring->access->read_last(ring, ring_data);
if (ret)
goto error_free_ring_data;
/* Need a count of channels prior to this one */
@@ -65,6 +63,7 @@
return ret;
}
+
/**
* max1363_ring_preenable() - setup the parameters of the ring before enabling
*
@@ -74,9 +73,9 @@
**/
static int max1363_ring_preenable(struct iio_dev *indio_dev)
{
- struct max1363_state *st = indio_dev->dev_data;
+ struct max1363_state *st = iio_priv(indio_dev);
struct iio_ring_buffer *ring = indio_dev->ring;
- size_t d_size;
+ size_t d_size = 0;
unsigned long numvals;
/*
@@ -91,50 +90,26 @@
max1363_set_scan_mode(st);
numvals = hweight_long(st->current_mode->modemask);
- if (ring->access.set_bytes_per_datum) {
+ if (ring->access->set_bytes_per_datum) {
+ if (ring->scan_timestamp)
+ d_size += sizeof(s64);
if (st->chip_info->bits != 8)
- d_size = numvals*2 + sizeof(s64);
+ d_size += numvals*2;
else
- d_size = numvals + sizeof(s64);
- if (d_size % 8)
+ d_size += numvals;
+ if (ring->scan_timestamp && (d_size % 8))
d_size += 8 - (d_size % 8);
- ring->access.set_bytes_per_datum(ring, d_size);
+ ring->access->set_bytes_per_datum(ring, d_size);
}
return 0;
}
-
-/**
- * max1363_poll_func_th() - th of trigger launched polling to ring buffer
- *
- * As sampling only occurs on i2c comms occurring, leave timestamping until
- * then. Some triggers will generate their own time stamp. Currently
- * there is no way of notifying them when no one cares.
- **/
-static void max1363_poll_func_th(struct iio_dev *indio_dev, s64 time)
+static irqreturn_t max1363_trigger_handler(int irq, void *p)
{
- struct max1363_state *st = indio_dev->dev_data;
-
- schedule_work(&st->poll_work);
-
- return;
-}
-/**
- * max1363_poll_bh_to_ring() - bh of trigger launched polling to ring buffer
- * @work_s: the work struct through which this was scheduled
- *
- * Currently there is no option in this driver to disable the saving of
- * timestamps within the ring.
- * I think the one copy of this at a time was to avoid problems if the
- * trigger was set far too high and the reads then locked up the computer.
- **/
-static void max1363_poll_bh_to_ring(struct work_struct *work_s)
-{
- struct max1363_state *st = container_of(work_s, struct max1363_state,
- poll_work);
- struct iio_dev *indio_dev = st->indio_dev;
- struct iio_sw_ring_buffer *sw_ring = iio_to_sw_ring(indio_dev->ring);
+ struct iio_poll_func *pf = p;
+ struct iio_dev *indio_dev = pf->private_data;
+ struct max1363_state *st = iio_priv(indio_dev);
s64 time_ns;
__u8 *rxbuf;
int b_sent;
@@ -149,20 +124,16 @@
if (d_size % sizeof(s64))
d_size += sizeof(s64) - (d_size % sizeof(s64));
- /* Ensure only one copy of this function running at a time */
- if (atomic_inc_return(&st->protect_ring) > 1)
- return;
-
/* Monitor mode prevents reading. Whilst not currently implemented
* might as well have this test in here in the meantime as it does
* no harm.
*/
if (numvals == 0)
- return;
+ return IRQ_HANDLED;
rxbuf = kmalloc(d_size, GFP_KERNEL);
if (rxbuf == NULL)
- return;
+ return -ENOMEM;
if (st->chip_info->bits != 8)
b_sent = i2c_master_recv(st->client, rxbuf, numvals*2);
else
@@ -174,16 +145,23 @@
memcpy(rxbuf + d_size - sizeof(s64), &time_ns, sizeof(time_ns));
- indio_dev->ring->access.store_to(&sw_ring->buf, rxbuf, time_ns);
+ indio_dev->ring->access->store_to(indio_dev->ring, rxbuf, time_ns);
done:
+ iio_trigger_notify_done(indio_dev->trig);
kfree(rxbuf);
- atomic_dec(&st->protect_ring);
+
+ return IRQ_HANDLED;
}
+static const struct iio_ring_setup_ops max1363_ring_setup_ops = {
+ .postenable = &iio_triggered_ring_postenable,
+ .preenable = &max1363_ring_preenable,
+ .predisable = &iio_triggered_ring_predisable,
+};
int max1363_register_ring_funcs_and_init(struct iio_dev *indio_dev)
{
- struct max1363_state *st = indio_dev->dev_data;
+ struct max1363_state *st = iio_priv(indio_dev);
int ret = 0;
indio_dev->ring = iio_sw_rb_allocate(indio_dev);
@@ -191,22 +169,27 @@
ret = -ENOMEM;
goto error_ret;
}
- /* Effectively select the ring buffer implementation */
- iio_ring_sw_register_funcs(&indio_dev->ring->access);
- ret = iio_alloc_pollfunc(indio_dev, NULL, &max1363_poll_func_th);
- if (ret)
+ indio_dev->pollfunc = iio_alloc_pollfunc(NULL,
+ &max1363_trigger_handler,
+ IRQF_ONESHOT,
+ indio_dev,
+ "%s_consumer%d",
+ st->client->name,
+ indio_dev->id);
+ if (indio_dev->pollfunc == NULL) {
+ ret = -ENOMEM;
goto error_deallocate_sw_rb;
-
+ }
+ /* Effectively select the ring buffer implementation */
+ indio_dev->ring->access = &ring_sw_access_funcs;
/* Ring buffer functions - here trigger setup related */
- indio_dev->ring->scan_el_attrs = st->chip_info->scan_attrs;
- indio_dev->ring->postenable = &iio_triggered_ring_postenable;
- indio_dev->ring->preenable = &max1363_ring_preenable;
- indio_dev->ring->predisable = &iio_triggered_ring_predisable;
- INIT_WORK(&st->poll_work, &max1363_poll_bh_to_ring);
+ indio_dev->ring->setup_ops = &max1363_ring_setup_ops;
/* Flag that polled ring buffering is possible */
indio_dev->modes |= INDIO_RING_TRIGGERED;
+
return 0;
+
error_deallocate_sw_rb:
iio_sw_rb_free(indio_dev->ring);
error_ret:
@@ -221,6 +204,6 @@
iio_trigger_dettach_poll_func(indio_dev->trig,
indio_dev->pollfunc);
}
- kfree(indio_dev->pollfunc);
+ iio_dealloc_pollfunc(indio_dev->pollfunc);
iio_sw_rb_free(indio_dev->ring);
}
diff --git a/drivers/staging/iio/addac/adt7316.c b/drivers/staging/iio/addac/adt7316.c
index d1b5b13..7097deb 100644
--- a/drivers/staging/iio/addac/adt7316.c
+++ b/drivers/staging/iio/addac/adt7316.c
@@ -174,10 +174,7 @@
*/
struct adt7316_chip_info {
- const char *name;
struct iio_dev *indio_dev;
- struct work_struct thresh_work;
- s64 last_timestamp;
struct adt7316_bus bus;
u16 ldac_pin;
u16 int_mask; /* 0x2f */
@@ -403,7 +400,7 @@
return sprintf(buf, "5 - AIN4\n");
default:
return sprintf(buf, "N/A\n");
- };
+ }
}
static ssize_t adt7316_store_ad_channel(struct device *dev,
@@ -465,7 +462,7 @@
if ((chip->id & ID_FAMILY_MASK) == ID_ADT75XX)
return sprintf(buf, "0 - VDD\n1 - Internal Temperature\n"
- "2 - External Temperature or AIN2\n"
+ "2 - External Temperature or AIN1\n"
"3 - AIN2\n4 - AIN3\n5 - AIN4\n");
else
return sprintf(buf, "0 - VDD\n1 - Internal Temperature\n"
@@ -893,7 +890,7 @@
return sprintf(buf, "2 - auto at MSB DAC ABCD writing\n");
default: /* ADT7316_DA_EN_MODE_LDAC */
return sprintf(buf, "3 - manual\n");
- };
+ }
}
}
@@ -1205,7 +1202,7 @@
return sprintf(buf, "%d\n", data);
else
break;
- };
+ }
if (data & ADT7316_T_VALUE_SIGN) {
/* convert supplement to positive value */
@@ -1674,18 +1671,6 @@
static IIO_DEVICE_ATTR(bus_type, S_IRUGO, adt7316_show_bus_type, NULL, 0);
-static ssize_t adt7316_show_name(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- struct iio_dev *dev_info = dev_get_drvdata(dev);
- struct adt7316_chip_info *chip = dev_info->dev_data;
-
- return sprintf(buf, "%s\n", chip->name);
-}
-
-static IIO_DEVICE_ATTR(name, S_IRUGO, adt7316_show_name, NULL, 0);
-
static struct attribute *adt7316_attributes[] = {
&iio_dev_attr_all_modes.dev_attr.attr,
&iio_dev_attr_mode.dev_attr.attr,
@@ -1722,7 +1707,6 @@
&iio_dev_attr_manufactorer_id.dev_attr.attr,
&iio_dev_attr_device_rev.dev_attr.attr,
&iio_dev_attr_bus_type.dev_attr.attr,
- &iio_dev_attr_name.dev_attr.attr,
NULL,
};
@@ -1771,7 +1755,6 @@
&iio_dev_attr_manufactorer_id.dev_attr.attr,
&iio_dev_attr_device_rev.dev_attr.attr,
&iio_dev_attr_bus_type.dev_attr.attr,
- &iio_dev_attr_name.dev_attr.attr,
NULL,
};
@@ -1779,70 +1762,77 @@
.attrs = adt7516_attributes,
};
-
-/*
- * temperature bound events
- */
-
-#define IIO_EVENT_CODE_ADT7316_IN_TEMP_HIGH IIO_BUFFER_EVENT_CODE(0)
-#define IIO_EVENT_CODE_ADT7316_IN_TEMP_LOW IIO_BUFFER_EVENT_CODE(1)
-#define IIO_EVENT_CODE_ADT7316_EX_TEMP_HIGH IIO_BUFFER_EVENT_CODE(2)
-#define IIO_EVENT_CODE_ADT7316_EX_TEMP_LOW IIO_BUFFER_EVENT_CODE(3)
-#define IIO_EVENT_CODE_ADT7316_EX_TEMP_FAULT IIO_BUFFER_EVENT_CODE(4)
-#define IIO_EVENT_CODE_ADT7516_AIN1 IIO_BUFFER_EVENT_CODE(5)
-#define IIO_EVENT_CODE_ADT7516_AIN2 IIO_BUFFER_EVENT_CODE(6)
-#define IIO_EVENT_CODE_ADT7516_AIN3 IIO_BUFFER_EVENT_CODE(7)
-#define IIO_EVENT_CODE_ADT7516_AIN4 IIO_BUFFER_EVENT_CODE(8)
-#define IIO_EVENT_CODE_ADT7316_VDD IIO_BUFFER_EVENT_CODE(9)
-
-static void adt7316_interrupt_bh(struct work_struct *work_s)
+static irqreturn_t adt7316_event_handler(int irq, void *private)
{
- struct adt7316_chip_info *chip =
- container_of(work_s, struct adt7316_chip_info, thresh_work);
+ struct iio_dev *indio_dev = private;
+ struct adt7316_chip_info *chip = iio_dev_get_devdata(indio_dev);
u8 stat1, stat2;
- int i, ret, count;
+ int ret;
+ s64 time;
ret = chip->bus.read(chip->bus.client, ADT7316_INT_STAT1, &stat1);
if (!ret) {
- if ((chip->id & ID_FAMILY_MASK) == ID_ADT75XX)
- count = 8;
- else
- count = 5;
+ if ((chip->id & ID_FAMILY_MASK) != ID_ADT75XX)
+ stat1 &= 0x1F;
- for (i = 0; i < count; i++) {
- if (stat1 & (1 << i))
- iio_push_event(chip->indio_dev, 0,
- IIO_EVENT_CODE_ADT7316_IN_TEMP_HIGH + i,
- chip->last_timestamp);
+ time = iio_get_time_ns();
+ if (stat1 & (1 << 0))
+ iio_push_event(chip->indio_dev, 0,
+ IIO_UNMOD_EVENT_CODE(IIO_TEMP, 0,
+ IIO_EV_TYPE_THRESH,
+ IIO_EV_DIR_RISING),
+ time);
+ if (stat1 & (1 << 1))
+ iio_push_event(chip->indio_dev, 0,
+ IIO_UNMOD_EVENT_CODE(IIO_TEMP, 0,
+ IIO_EV_TYPE_THRESH,
+ IIO_EV_DIR_FALLING),
+ time);
+ if (stat1 & (1 << 2))
+ iio_push_event(chip->indio_dev, 0,
+ IIO_UNMOD_EVENT_CODE(IIO_TEMP, 1,
+ IIO_EV_TYPE_THRESH,
+ IIO_EV_DIR_RISING),
+ time);
+ if (stat1 & (1 << 3))
+ iio_push_event(chip->indio_dev, 0,
+ IIO_UNMOD_EVENT_CODE(IIO_TEMP, 1,
+ IIO_EV_TYPE_THRESH,
+ IIO_EV_DIR_FALLING),
+ time);
+ if (stat1 & (1 << 5))
+ iio_push_event(chip->indio_dev, 0,
+ IIO_UNMOD_EVENT_CODE(IIO_IN, 1,
+ IIO_EV_TYPE_THRESH,
+ IIO_EV_DIR_EITHER),
+ time);
+ if (stat1 & (1 << 6))
+ iio_push_event(chip->indio_dev, 0,
+ IIO_UNMOD_EVENT_CODE(IIO_IN, 2,
+ IIO_EV_TYPE_THRESH,
+ IIO_EV_DIR_EITHER),
+ time);
+ if (stat1 & (1 << 7))
+ iio_push_event(chip->indio_dev, 0,
+ IIO_UNMOD_EVENT_CODE(IIO_IN, 3,
+ IIO_EV_TYPE_THRESH,
+ IIO_EV_DIR_EITHER),
+ time);
}
- }
-
ret = chip->bus.read(chip->bus.client, ADT7316_INT_STAT2, &stat2);
if (!ret) {
if (stat2 & ADT7316_INT_MASK2_VDD)
iio_push_event(chip->indio_dev, 0,
- IIO_EVENT_CODE_ADT7316_VDD,
- chip->last_timestamp);
+ IIO_UNMOD_EVENT_CODE(IIO_IN,
+ 0,
+ IIO_EV_TYPE_THRESH,
+ IIO_EV_DIR_RISING),
+ iio_get_time_ns());
}
- enable_irq(chip->bus.irq);
+ return IRQ_HANDLED;
}
-static int adt7316_interrupt(struct iio_dev *dev_info,
- int index,
- s64 timestamp,
- int no_test)
-{
- struct adt7316_chip_info *chip = dev_info->dev_data;
-
- chip->last_timestamp = timestamp;
- schedule_work(&chip->thresh_work);
-
- return 0;
-}
-
-IIO_EVENT_SH(adt7316, &adt7316_interrupt);
-
/*
* Show mask of enabled interrupts in Hex.
*/
@@ -1901,9 +1891,9 @@
}
static inline ssize_t adt7316_show_ad_bound(struct device *dev,
struct device_attribute *attr,
- u8 bound_reg,
char *buf)
{
+ struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
struct iio_dev *dev_info = dev_get_drvdata(dev);
struct adt7316_chip_info *chip = dev_info->dev_data;
u8 val;
@@ -1911,10 +1901,10 @@
int ret;
if ((chip->id & ID_FAMILY_MASK) == ID_ADT73XX &&
- bound_reg > ADT7316_EX_TEMP_LOW)
+ this_attr->address > ADT7316_EX_TEMP_LOW)
return -EPERM;
- ret = chip->bus.read(chip->bus.client, bound_reg, &val);
+ ret = chip->bus.read(chip->bus.client, this_attr->address, &val);
if (ret)
return -EIO;
@@ -1931,10 +1921,10 @@
static inline ssize_t adt7316_set_ad_bound(struct device *dev,
struct device_attribute *attr,
- u8 bound_reg,
const char *buf,
size_t len)
{
+ struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
struct iio_dev *dev_info = dev_get_drvdata(dev);
struct adt7316_chip_info *chip = dev_info->dev_data;
long data;
@@ -1942,7 +1932,7 @@
int ret;
if ((chip->id & ID_FAMILY_MASK) == ID_ADT73XX &&
- bound_reg > ADT7316_EX_TEMP_LOW)
+ this_attr->address > ADT7316_EX_TEMP_LOW)
return -EPERM;
ret = strict_strtol(buf, 10, &data);
@@ -1963,183 +1953,13 @@
val = (u8)data;
- ret = chip->bus.write(chip->bus.client, bound_reg, val);
+ ret = chip->bus.write(chip->bus.client, this_attr->address, val);
if (ret)
return -EIO;
return len;
}
-static ssize_t adt7316_show_in_temp_high(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- return adt7316_show_ad_bound(dev, attr,
- ADT7316_IN_TEMP_HIGH, buf);
-}
-
-static inline ssize_t adt7316_set_in_temp_high(struct device *dev,
- struct device_attribute *attr,
- const char *buf,
- size_t len)
-{
- return adt7316_set_ad_bound(dev, attr,
- ADT7316_IN_TEMP_HIGH, buf, len);
-}
-
-static ssize_t adt7316_show_in_temp_low(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- return adt7316_show_ad_bound(dev, attr,
- ADT7316_IN_TEMP_LOW, buf);
-}
-
-static inline ssize_t adt7316_set_in_temp_low(struct device *dev,
- struct device_attribute *attr,
- const char *buf,
- size_t len)
-{
- return adt7316_set_ad_bound(dev, attr,
- ADT7316_IN_TEMP_LOW, buf, len);
-}
-
-static ssize_t adt7316_show_ex_temp_ain1_high(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- return adt7316_show_ad_bound(dev, attr,
- ADT7316_EX_TEMP_HIGH, buf);
-}
-
-static inline ssize_t adt7316_set_ex_temp_ain1_high(struct device *dev,
- struct device_attribute *attr,
- const char *buf,
- size_t len)
-{
- return adt7316_set_ad_bound(dev, attr,
- ADT7316_EX_TEMP_HIGH, buf, len);
-}
-
-static ssize_t adt7316_show_ex_temp_ain1_low(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- return adt7316_show_ad_bound(dev, attr,
- ADT7316_EX_TEMP_LOW, buf);
-}
-
-static inline ssize_t adt7316_set_ex_temp_ain1_low(struct device *dev,
- struct device_attribute *attr,
- const char *buf,
- size_t len)
-{
- return adt7316_set_ad_bound(dev, attr,
- ADT7316_EX_TEMP_LOW, buf, len);
-}
-
-static ssize_t adt7316_show_ain2_high(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- return adt7316_show_ad_bound(dev, attr,
- ADT7516_AIN2_HIGH, buf);
-}
-
-static inline ssize_t adt7316_set_ain2_high(struct device *dev,
- struct device_attribute *attr,
- const char *buf,
- size_t len)
-{
- return adt7316_set_ad_bound(dev, attr,
- ADT7516_AIN2_HIGH, buf, len);
-}
-
-static ssize_t adt7316_show_ain2_low(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- return adt7316_show_ad_bound(dev, attr,
- ADT7516_AIN2_LOW, buf);
-}
-
-static inline ssize_t adt7316_set_ain2_low(struct device *dev,
- struct device_attribute *attr,
- const char *buf,
- size_t len)
-{
- return adt7316_set_ad_bound(dev, attr,
- ADT7516_AIN2_LOW, buf, len);
-}
-
-static ssize_t adt7316_show_ain3_high(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- return adt7316_show_ad_bound(dev, attr,
- ADT7516_AIN3_HIGH, buf);
-}
-
-static inline ssize_t adt7316_set_ain3_high(struct device *dev,
- struct device_attribute *attr,
- const char *buf,
- size_t len)
-{
- return adt7316_set_ad_bound(dev, attr,
- ADT7516_AIN3_HIGH, buf, len);
-}
-
-static ssize_t adt7316_show_ain3_low(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- return adt7316_show_ad_bound(dev, attr,
- ADT7516_AIN3_LOW, buf);
-}
-
-static inline ssize_t adt7316_set_ain3_low(struct device *dev,
- struct device_attribute *attr,
- const char *buf,
- size_t len)
-{
- return adt7316_set_ad_bound(dev, attr,
- ADT7516_AIN3_LOW, buf, len);
-}
-
-static ssize_t adt7316_show_ain4_high(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- return adt7316_show_ad_bound(dev, attr,
- ADT7516_AIN4_HIGH, buf);
-}
-
-static inline ssize_t adt7316_set_ain4_high(struct device *dev,
- struct device_attribute *attr,
- const char *buf,
- size_t len)
-{
- return adt7316_set_ad_bound(dev, attr,
- ADT7516_AIN4_HIGH, buf, len);
-}
-
-static ssize_t adt7316_show_ain4_low(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- return adt7316_show_ad_bound(dev, attr,
- ADT7516_AIN4_LOW, buf);
-}
-
-static inline ssize_t adt7316_set_ain4_low(struct device *dev,
- struct device_attribute *attr,
- const char *buf,
- size_t len)
-{
- return adt7316_set_ad_bound(dev, attr,
- ADT7516_AIN4_LOW, buf, len);
-}
-
static ssize_t adt7316_show_int_enabled(struct device *dev,
struct device_attribute *attr,
char *buf)
@@ -2173,47 +1993,72 @@
return len;
}
+static IIO_DEVICE_ATTR(int_mask,
+ S_IRUGO | S_IWUSR,
+ adt7316_show_int_mask, adt7316_set_int_mask,
+ 0);
+static IIO_DEVICE_ATTR(in_temp_high_value,
+ S_IRUGO | S_IWUSR,
+ adt7316_show_ad_bound, adt7316_set_ad_bound,
+ ADT7316_IN_TEMP_HIGH);
+static IIO_DEVICE_ATTR(in_temp_low_value,
+ S_IRUGO | S_IWUSR,
+ adt7316_show_ad_bound, adt7316_set_ad_bound,
+ ADT7316_IN_TEMP_LOW);
+static IIO_DEVICE_ATTR(ex_temp_high_value,
+ S_IRUGO | S_IWUSR,
+ adt7316_show_ad_bound, adt7316_set_ad_bound,
+ ADT7316_EX_TEMP_HIGH);
+static IIO_DEVICE_ATTR(ex_temp_low_value,
+ S_IRUGO | S_IWUSR,
+ adt7316_show_ad_bound, adt7316_set_ad_bound,
+ ADT7316_EX_TEMP_LOW);
-IIO_EVENT_ATTR_SH(int_mask, iio_event_adt7316,
- adt7316_show_int_mask, adt7316_set_int_mask, 0);
-IIO_EVENT_ATTR_SH(in_temp_high, iio_event_adt7316,
- adt7316_show_in_temp_high, adt7316_set_in_temp_high, 0);
-IIO_EVENT_ATTR_SH(in_temp_low, iio_event_adt7316,
- adt7316_show_in_temp_low, adt7316_set_in_temp_low, 0);
-IIO_EVENT_ATTR_SH(ex_temp_high, iio_event_adt7316,
- adt7316_show_ex_temp_ain1_high,
- adt7316_set_ex_temp_ain1_high, 0);
-IIO_EVENT_ATTR_SH(ex_temp_low, iio_event_adt7316,
- adt7316_show_ex_temp_ain1_low,
- adt7316_set_ex_temp_ain1_low, 0);
-IIO_EVENT_ATTR_SH(ex_temp_ain1_high, iio_event_adt7316,
- adt7316_show_ex_temp_ain1_high,
- adt7316_set_ex_temp_ain1_high, 0);
-IIO_EVENT_ATTR_SH(ex_temp_ain1_low, iio_event_adt7316,
- adt7316_show_ex_temp_ain1_low,
- adt7316_set_ex_temp_ain1_low, 0);
-IIO_EVENT_ATTR_SH(ain2_high, iio_event_adt7316,
- adt7316_show_ain2_high, adt7316_set_ain2_high, 0);
-IIO_EVENT_ATTR_SH(ain2_low, iio_event_adt7316,
- adt7316_show_ain2_low, adt7316_set_ain2_low, 0);
-IIO_EVENT_ATTR_SH(ain3_high, iio_event_adt7316,
- adt7316_show_ain3_high, adt7316_set_ain3_high, 0);
-IIO_EVENT_ATTR_SH(ain3_low, iio_event_adt7316,
- adt7316_show_ain3_low, adt7316_set_ain3_low, 0);
-IIO_EVENT_ATTR_SH(ain4_high, iio_event_adt7316,
- adt7316_show_ain4_high, adt7316_set_ain4_high, 0);
-IIO_EVENT_ATTR_SH(ain4_low, iio_event_adt7316,
- adt7316_show_ain4_low, adt7316_set_ain4_low, 0);
-IIO_EVENT_ATTR_SH(int_enabled, iio_event_adt7316,
- adt7316_show_int_enabled, adt7316_set_int_enabled, 0);
+/* NASTY duplication to be fixed */
+static IIO_DEVICE_ATTR(ex_temp_ain1_high_value,
+ S_IRUGO | S_IWUSR,
+ adt7316_show_ad_bound, adt7316_set_ad_bound,
+ ADT7316_EX_TEMP_HIGH);
+static IIO_DEVICE_ATTR(ex_temp_ain1_low_value,
+ S_IRUGO | S_IWUSR,
+ adt7316_show_ad_bound, adt7316_set_ad_bound,
+ ADT7316_EX_TEMP_LOW);
+static IIO_DEVICE_ATTR(ain2_high_value,
+ S_IRUGO | S_IWUSR,
+ adt7316_show_ad_bound, adt7316_set_ad_bound,
+ ADT7516_AIN2_HIGH);
+static IIO_DEVICE_ATTR(ain2_low_value,
+ S_IRUGO | S_IWUSR,
+ adt7316_show_ad_bound, adt7316_set_ad_bound,
+ ADT7516_AIN2_LOW);
+static IIO_DEVICE_ATTR(ain3_high_value,
+ S_IRUGO | S_IWUSR,
+ adt7316_show_ad_bound, adt7316_set_ad_bound,
+ ADT7516_AIN3_HIGH);
+static IIO_DEVICE_ATTR(ain3_low_value,
+ S_IRUGO | S_IWUSR,
+ adt7316_show_ad_bound, adt7316_set_ad_bound,
+ ADT7516_AIN3_LOW);
+static IIO_DEVICE_ATTR(ain4_high_value,
+ S_IRUGO | S_IWUSR,
+ adt7316_show_ad_bound, adt7316_set_ad_bound,
+ ADT7516_AIN4_HIGH);
+static IIO_DEVICE_ATTR(ain4_low_value,
+ S_IRUGO | S_IWUSR,
+ adt7316_show_ad_bound, adt7316_set_ad_bound,
+ ADT7516_AIN4_LOW);
+static IIO_DEVICE_ATTR(int_enabled,
+ S_IRUGO | S_IWUSR,
+ adt7316_show_int_enabled,
+ adt7316_set_int_enabled, 0);
static struct attribute *adt7316_event_attributes[] = {
- &iio_event_attr_int_mask.dev_attr.attr,
- &iio_event_attr_in_temp_high.dev_attr.attr,
- &iio_event_attr_in_temp_low.dev_attr.attr,
- &iio_event_attr_ex_temp_high.dev_attr.attr,
- &iio_event_attr_ex_temp_low.dev_attr.attr,
- &iio_event_attr_int_enabled.dev_attr.attr,
+ &iio_dev_attr_int_mask.dev_attr.attr,
+ &iio_dev_attr_in_temp_high_value.dev_attr.attr,
+ &iio_dev_attr_in_temp_low_value.dev_attr.attr,
+ &iio_dev_attr_ex_temp_high_value.dev_attr.attr,
+ &iio_dev_attr_ex_temp_low_value.dev_attr.attr,
+ &iio_dev_attr_int_enabled.dev_attr.attr,
NULL,
};
@@ -2222,18 +2067,18 @@
};
static struct attribute *adt7516_event_attributes[] = {
- &iio_event_attr_int_mask.dev_attr.attr,
- &iio_event_attr_in_temp_high.dev_attr.attr,
- &iio_event_attr_in_temp_low.dev_attr.attr,
- &iio_event_attr_ex_temp_ain1_high.dev_attr.attr,
- &iio_event_attr_ex_temp_ain1_low.dev_attr.attr,
- &iio_event_attr_ain2_high.dev_attr.attr,
- &iio_event_attr_ain2_low.dev_attr.attr,
- &iio_event_attr_ain3_high.dev_attr.attr,
- &iio_event_attr_ain3_low.dev_attr.attr,
- &iio_event_attr_ain4_high.dev_attr.attr,
- &iio_event_attr_ain4_low.dev_attr.attr,
- &iio_event_attr_int_enabled.dev_attr.attr,
+ &iio_dev_attr_int_mask.dev_attr.attr,
+ &iio_dev_attr_in_temp_high_value.dev_attr.attr,
+ &iio_dev_attr_in_temp_low_value.dev_attr.attr,
+ &iio_dev_attr_ex_temp_ain1_high_value.dev_attr.attr,
+ &iio_dev_attr_ex_temp_ain1_low_value.dev_attr.attr,
+ &iio_dev_attr_ain2_high_value.dev_attr.attr,
+ &iio_dev_attr_ain2_low_value.dev_attr.attr,
+ &iio_dev_attr_ain3_high_value.dev_attr.attr,
+ &iio_dev_attr_ain3_low_value.dev_attr.attr,
+ &iio_dev_attr_ain4_high_value.dev_attr.attr,
+ &iio_dev_attr_ain4_low_value.dev_attr.attr,
+ &iio_dev_attr_int_enabled.dev_attr.attr,
NULL,
};
@@ -2261,6 +2106,20 @@
EXPORT_SYMBOL(adt7316_enable);
#endif
+static const struct iio_info adt7316_info = {
+ .attrs = &adt7316_attribute_group,
+ .num_interrupt_lines = 1,
+ .event_attrs = &adt7316_event_attribute_group,
+ .driver_module = THIS_MODULE,
+};
+
+static const struct iio_info adt7516_info = {
+ .attrs = &adt7516_attribute_group,
+ .num_interrupt_lines = 1,
+ .event_attrs = &adt7516_event_attribute_group,
+ .driver_module = THIS_MODULE,
+};
+
/*
* device probe and remove
*/
@@ -2280,7 +2139,6 @@
dev_set_drvdata(dev, chip);
chip->bus = *bus;
- chip->name = name;
if (name[4] == '3')
chip->id = ID_ADT7316 + (name[6] - '6');
@@ -2299,23 +2157,19 @@
if ((chip->id & ID_FAMILY_MASK) == ID_ADT75XX)
chip->int_mask |= ADT7516_AIN_INT_MASK;
- chip->indio_dev = iio_allocate_device();
+ chip->indio_dev = iio_allocate_device(0);
if (chip->indio_dev == NULL) {
ret = -ENOMEM;
goto error_free_chip;
}
chip->indio_dev->dev.parent = dev;
- if ((chip->id & ID_FAMILY_MASK) == ID_ADT75XX) {
- chip->indio_dev->attrs = &adt7516_attribute_group;
- chip->indio_dev->event_attrs = &adt7516_event_attribute_group;
- } else {
- chip->indio_dev->attrs = &adt7316_attribute_group;
- chip->indio_dev->event_attrs = &adt7316_event_attribute_group;
- }
+ if ((chip->id & ID_FAMILY_MASK) == ID_ADT75XX)
+ chip->indio_dev->info = &adt7516_info;
+ else
+ chip->indio_dev->info = &adt7316_info;
+ chip->indio_dev->name = name;
chip->indio_dev->dev_data = (void *)chip;
- chip->indio_dev->driver_module = THIS_MODULE;
- chip->indio_dev->num_interrupt_lines = 1;
chip->indio_dev->modes = INDIO_DIRECT_MODE;
ret = iio_device_register(chip->indio_dev);
@@ -2326,24 +2180,15 @@
if (adt7316_platform_data[0])
chip->bus.irq_flags = adt7316_platform_data[0];
- ret = iio_register_interrupt_line(chip->bus.irq,
- chip->indio_dev,
- 0,
- chip->bus.irq_flags,
- chip->name);
+ ret = request_threaded_irq(chip->bus.irq,
+ NULL,
+ &adt7316_event_handler,
+ chip->bus.irq_flags | IRQF_ONESHOT,
+ chip->indio_dev->name,
+ chip->indio_dev);
if (ret)
goto error_unreg_dev;
- /*
- * The event handler list element refer to iio_event_adt7316.
- * All event attributes bind to the same event handler.
- * So, only register event handler once.
- */
- iio_add_event_to_list(&iio_event_adt7316,
- &chip->indio_dev->interrupts[0]->ev_list);
-
- INIT_WORK(&chip->thresh_work, adt7316_interrupt_bh);
-
if (chip->bus.irq_flags & IRQF_TRIGGER_HIGH)
chip->config1 |= ADT7316_INT_POLARITY;
}
@@ -2361,12 +2206,12 @@
}
dev_info(dev, "%s temperature sensor, ADC and DAC registered.\n",
- chip->name);
+ chip->indio_dev->name);
return 0;
error_unreg_irq:
- iio_unregister_interrupt_line(chip->indio_dev, 0);
+ free_irq(chip->bus.irq, chip->indio_dev);
error_unreg_dev:
iio_device_unregister(chip->indio_dev);
error_free_dev:
@@ -2383,12 +2228,11 @@
struct iio_dev *dev_info = dev_get_drvdata(dev);
struct adt7316_chip_info *chip = dev_info->dev_data;
- struct iio_dev *indio_dev = chip->indio_dev;
dev_set_drvdata(dev, NULL);
if (chip->bus.irq)
- iio_unregister_interrupt_line(indio_dev, 0);
- iio_device_unregister(indio_dev);
+ free_irq(chip->bus.irq, chip->indio_dev);
+ iio_device_unregister(chip->indio_dev);
iio_free_device(chip->indio_dev);
kfree(chip);
diff --git a/drivers/staging/iio/chrdev.h b/drivers/staging/iio/chrdev.h
index 4fcb99c..3e31ee6 100644
--- a/drivers/staging/iio/chrdev.h
+++ b/drivers/staging/iio/chrdev.h
@@ -45,23 +45,10 @@
* struct iio_detected_event_list - list element for events that have occurred
* @list: linked list header
* @ev: the event itself
- * @shared_pointer: used when the event is shared - i.e. can be escallated
- * on demand (eg ring buffer 50%->100% full)
*/
struct iio_detected_event_list {
struct list_head list;
struct iio_event_data ev;
- struct iio_shared_ev_pointer *shared_pointer;
-};
-/**
- * struct iio_shared_ev_pointer - allows shared events to identify if currently
- * in the detected event list
- * @ev_p: pointer to detected event list element (null if not in list)
- * @lock: protect this element to prevent simultaneous edit and remove
- */
-struct iio_shared_ev_pointer {
- struct iio_detected_event_list *ev_p;
- spinlock_t lock;
};
/**
@@ -73,43 +60,16 @@
* @det_events: list of detected events
* @max_events: maximum number of events before new ones are dropped
* @current_events: number of events in detected list
- * @owner: ensure the driver module owns the file, not iio
- * @private: driver specific data
- * @_name: used internally to store the sysfs name for minor id
- * attribute
- * @_attrname: the event interface's attribute name
*/
struct iio_event_interface {
struct device dev;
struct iio_handler handler;
wait_queue_head_t wait;
struct mutex event_list_lock;
- struct iio_detected_event_list det_events;
+ struct list_head det_events;
int max_events;
int current_events;
- struct module *owner;
- void *private;
- char _name[35];
- char _attrname[20];
-};
-
-/**
- * struct iio_event_handler_list - element in list of handlers for events
- * @list: list header
- * @refcount: as the handler may be shared between multiple device
- * side events, reference counting ensures clean removal
- * @exist_lock: prevents race conditions related to refcount usage.
- * @handler: event handler function - called on event if this
- * event_handler is enabled.
- *
- * Each device has one list of these per interrupt line.
- **/
-struct iio_event_handler_list {
- struct list_head list;
- int refcount;
- struct mutex exist_lock;
- int (*handler)(struct iio_dev *dev_info, int index, s64 timestamp,
- int no_test);
+ struct list_head dev_attr_list;
};
#endif
diff --git a/drivers/staging/iio/dac/Kconfig b/drivers/staging/iio/dac/Kconfig
index 67defcb..d5a5556 100644
--- a/drivers/staging/iio/dac/Kconfig
+++ b/drivers/staging/iio/dac/Kconfig
@@ -21,6 +21,27 @@
To compile this driver as a module, choose M here: the
module will be called ad5446.
+config AD5504
+ tristate "Analog Devices AD5504/AD5501 DAC SPI driver"
+ depends on SPI
+ help
+ Say yes here to build support for Analog Devices AD5504, AD5501,
+ High Voltage Digital to Analog Converter.
+
+ To compile this driver as a module, choose M here: the
+ module will be called ad5504.
+
+config AD5791
+ tristate "Analog Devices AD5760/AD5780/AD5781/AD5791 DAC SPI driver"
+ depends on SPI
+ help
+ Say yes here to build support for Analog Devices AD5760, AD5780,
+ AD5781, AD5791 High Resolution Voltage Output Digital to
+ Analog Converter.
+
+ To compile this driver as a module, choose M here: the
+ module will be called ad5791.
+
config MAX517
tristate "Maxim MAX517/518/519 DAC driver"
depends on I2C && EXPERIMENTAL
diff --git a/drivers/staging/iio/dac/Makefile b/drivers/staging/iio/dac/Makefile
index 1197aef..83196de 100644
--- a/drivers/staging/iio/dac/Makefile
+++ b/drivers/staging/iio/dac/Makefile
@@ -3,5 +3,7 @@
#
obj-$(CONFIG_AD5624R_SPI) += ad5624r_spi.o
+obj-$(CONFIG_AD5504) += ad5504.o
obj-$(CONFIG_AD5446) += ad5446.o
+obj-$(CONFIG_AD5791) += ad5791.o
obj-$(CONFIG_MAX517) += max517.o
diff --git a/drivers/staging/iio/dac/ad5446.c b/drivers/staging/iio/dac/ad5446.c
index 8623a72..86cb08c 100644
--- a/drivers/staging/iio/dac/ad5446.c
+++ b/drivers/staging/iio/dac/ad5446.c
@@ -106,17 +106,6 @@
}
static IIO_DEVICE_ATTR(out_scale, S_IRUGO, ad5446_show_scale, NULL, 0);
-static ssize_t ad5446_show_name(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- struct iio_dev *dev_info = dev_get_drvdata(dev);
- struct ad5446_state *st = iio_dev_get_devdata(dev_info);
-
- return sprintf(buf, "%s\n", spi_get_device_id(st->spi)->name);
-}
-static IIO_DEVICE_ATTR(name, S_IRUGO, ad5446_show_name, NULL, 0);
-
static ssize_t ad5446_write_powerdown_mode(struct device *dev,
struct device_attribute *attr,
const char *buf, size_t len)
@@ -204,7 +193,6 @@
&iio_dev_attr_out0_powerdown.dev_attr.attr,
&iio_dev_attr_out_powerdown_mode.dev_attr.attr,
&iio_const_attr_out_powerdown_mode_available.dev_attr.attr,
- &iio_dev_attr_name.dev_attr.attr,
NULL,
};
@@ -245,6 +233,12 @@
.left_shift = 0,
.store_sample = ad5446_store_sample,
},
+ [ID_AD5541A] = {
+ .bits = 16,
+ .storagebits = 16,
+ .left_shift = 0,
+ .store_sample = ad5542_store_sample,
+ },
[ID_AD5542A] = {
.bits = 16,
.storagebits = 16,
@@ -340,6 +334,11 @@
},
};
+static const struct iio_info ad5446_info = {
+ .attrs = &ad5446_attribute_group,
+ .driver_module = THIS_MODULE,
+};
+
static int __devinit ad5446_probe(struct spi_device *spi)
{
struct ad5446_state *st;
@@ -367,7 +366,7 @@
st->spi = spi;
- st->indio_dev = iio_allocate_device();
+ st->indio_dev = iio_allocate_device(0);
if (st->indio_dev == NULL) {
ret = -ENOMEM;
goto error_disable_reg;
@@ -375,9 +374,9 @@
/* Estabilish that the iio_dev is a child of the spi device */
st->indio_dev->dev.parent = &spi->dev;
- st->indio_dev->attrs = &ad5446_attribute_group;
+ st->indio_dev->name = spi_get_device_id(spi)->name;
+ st->indio_dev->info = &ad5446_info;
st->indio_dev->dev_data = (void *)(st);
- st->indio_dev->driver_module = THIS_MODULE;
st->indio_dev->modes = INDIO_DIRECT_MODE;
/* Setup default message */
@@ -442,6 +441,7 @@
{"ad5444", ID_AD5444},
{"ad5446", ID_AD5446},
{"ad5512a", ID_AD5512A},
+ {"ad5541a", ID_AD5541A},
{"ad5542a", ID_AD5542A},
{"ad5543", ID_AD5543},
{"ad5553", ID_AD5553},
diff --git a/drivers/staging/iio/dac/ad5446.h b/drivers/staging/iio/dac/ad5446.h
index 7ac63ab8a..e6ffd2b 100644
--- a/drivers/staging/iio/dac/ad5446.h
+++ b/drivers/staging/iio/dac/ad5446.h
@@ -92,6 +92,7 @@
enum ad5446_supported_device_ids {
ID_AD5444,
ID_AD5446,
+ ID_AD5541A,
ID_AD5542A,
ID_AD5543,
ID_AD5512A,
diff --git a/drivers/staging/iio/dac/ad5504.c b/drivers/staging/iio/dac/ad5504.c
new file mode 100644
index 0000000..ed029cd
--- /dev/null
+++ b/drivers/staging/iio/dac/ad5504.c
@@ -0,0 +1,404 @@
+/*
+ * AD5504, AD5501 High Voltage Digital to Analog Converter
+ *
+ * Copyright 2011 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2.
+ */
+
+#include <linux/interrupt.h>
+#include <linux/gpio.h>
+#include <linux/fs.h>
+#include <linux/device.h>
+#include <linux/kernel.h>
+#include <linux/spi/spi.h>
+#include <linux/slab.h>
+#include <linux/sysfs.h>
+#include <linux/regulator/consumer.h>
+
+#include "../iio.h"
+#include "../sysfs.h"
+#include "dac.h"
+#include "ad5504.h"
+
+static int ad5504_spi_write(struct spi_device *spi, u8 addr, u16 val)
+{
+ u16 tmp = cpu_to_be16(AD5504_CMD_WRITE |
+ AD5504_ADDR(addr) |
+ (val & AD5504_RES_MASK));
+
+ return spi_write(spi, (u8 *)&tmp, 2);
+}
+
+static int ad5504_spi_read(struct spi_device *spi, u8 addr, u16 *val)
+{
+ u16 tmp = cpu_to_be16(AD5504_CMD_READ | AD5504_ADDR(addr));
+ int ret;
+ struct spi_transfer t = {
+ .tx_buf = &tmp,
+ .rx_buf = val,
+ .len = 2,
+ };
+ struct spi_message m;
+
+ spi_message_init(&m);
+ spi_message_add_tail(&t, &m);
+ ret = spi_sync(spi, &m);
+
+ *val = be16_to_cpu(*val) & AD5504_RES_MASK;
+
+ return ret;
+}
+
+static ssize_t ad5504_write_dac(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t len)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ struct ad5504_state *st = iio_dev_get_devdata(indio_dev);
+ struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
+ long readin;
+ int ret;
+
+ ret = strict_strtol(buf, 10, &readin);
+ if (ret)
+ return ret;
+
+ ret = ad5504_spi_write(st->spi, this_attr->address, readin);
+ return ret ? ret : len;
+}
+
+static ssize_t ad5504_read_dac(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ struct ad5504_state *st = iio_dev_get_devdata(indio_dev);
+ struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
+ int ret;
+ u16 val;
+
+ ret = ad5504_spi_read(st->spi, this_attr->address, &val);
+ if (ret)
+ return ret;
+
+ return sprintf(buf, "%d\n", val);
+}
+
+static ssize_t ad5504_read_powerdown_mode(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ struct ad5504_state *st = iio_dev_get_devdata(indio_dev);
+
+ const char mode[][14] = {"20kohm_to_gnd", "three_state"};
+
+ return sprintf(buf, "%s\n", mode[st->pwr_down_mode]);
+}
+
+static ssize_t ad5504_write_powerdown_mode(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t len)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ struct ad5504_state *st = iio_dev_get_devdata(indio_dev);
+ int ret;
+
+ if (sysfs_streq(buf, "20kohm_to_gnd"))
+ st->pwr_down_mode = AD5504_DAC_PWRDN_20K;
+ else if (sysfs_streq(buf, "three_state"))
+ st->pwr_down_mode = AD5504_DAC_PWRDN_3STATE;
+ else
+ ret = -EINVAL;
+
+ return ret ? ret : len;
+}
+
+static ssize_t ad5504_read_dac_powerdown(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ struct ad5504_state *st = iio_dev_get_devdata(indio_dev);
+ struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
+
+ return sprintf(buf, "%d\n",
+ !(st->pwr_down_mask & (1 << this_attr->address)));
+}
+
+static ssize_t ad5504_write_dac_powerdown(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t len)
+{
+ long readin;
+ int ret;
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ struct ad5504_state *st = iio_dev_get_devdata(indio_dev);
+ struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
+
+ ret = strict_strtol(buf, 10, &readin);
+ if (ret)
+ return ret;
+
+ if (readin == 0)
+ st->pwr_down_mask |= (1 << this_attr->address);
+ else if (readin == 1)
+ st->pwr_down_mask &= ~(1 << this_attr->address);
+ else
+ ret = -EINVAL;
+
+ ret = ad5504_spi_write(st->spi, AD5504_ADDR_CTRL,
+ AD5504_DAC_PWRDWN_MODE(st->pwr_down_mode) |
+ AD5504_DAC_PWR(st->pwr_down_mask));
+
+ /* writes to the CTRL register must be followed by a NOOP */
+ ad5504_spi_write(st->spi, AD5504_ADDR_NOOP, 0);
+
+ return ret ? ret : len;
+}
+
+static ssize_t ad5504_show_scale(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ struct ad5504_state *st = iio_dev_get_devdata(indio_dev);
+ /* Corresponds to Vref / 2^(bits) */
+ unsigned int scale_uv = (st->vref_mv * 1000) >> AD5505_BITS;
+
+ return sprintf(buf, "%d.%03d\n", scale_uv / 1000, scale_uv % 1000);
+}
+static IIO_DEVICE_ATTR(out_scale, S_IRUGO, ad5504_show_scale, NULL, 0);
+
+#define IIO_DEV_ATTR_OUT_RW_RAW(_num, _show, _store, _addr) \
+ IIO_DEVICE_ATTR(out##_num##_raw, \
+ S_IRUGO | S_IWUSR, _show, _store, _addr)
+
+static IIO_DEV_ATTR_OUT_RW_RAW(0, ad5504_read_dac,
+ ad5504_write_dac, AD5504_ADDR_DAC0);
+static IIO_DEV_ATTR_OUT_RW_RAW(1, ad5504_read_dac,
+ ad5504_write_dac, AD5504_ADDR_DAC1);
+static IIO_DEV_ATTR_OUT_RW_RAW(2, ad5504_read_dac,
+ ad5504_write_dac, AD5504_ADDR_DAC2);
+static IIO_DEV_ATTR_OUT_RW_RAW(3, ad5504_read_dac,
+ ad5504_write_dac, AD5504_ADDR_DAC3);
+
+static IIO_DEVICE_ATTR(out_powerdown_mode, S_IRUGO |
+ S_IWUSR, ad5504_read_powerdown_mode,
+ ad5504_write_powerdown_mode, 0);
+
+static IIO_CONST_ATTR(out_powerdown_mode_available,
+ "20kohm_to_gnd three_state");
+
+#define IIO_DEV_ATTR_DAC_POWERDOWN(_num, _show, _store, _addr) \
+ IIO_DEVICE_ATTR(out##_num##_powerdown, \
+ S_IRUGO | S_IWUSR, _show, _store, _addr)
+
+static IIO_DEV_ATTR_DAC_POWERDOWN(0, ad5504_read_dac_powerdown,
+ ad5504_write_dac_powerdown, 0);
+static IIO_DEV_ATTR_DAC_POWERDOWN(1, ad5504_read_dac_powerdown,
+ ad5504_write_dac_powerdown, 1);
+static IIO_DEV_ATTR_DAC_POWERDOWN(2, ad5504_read_dac_powerdown,
+ ad5504_write_dac_powerdown, 2);
+static IIO_DEV_ATTR_DAC_POWERDOWN(3, ad5504_read_dac_powerdown,
+ ad5504_write_dac_powerdown, 3);
+
+static struct attribute *ad5504_attributes[] = {
+ &iio_dev_attr_out0_raw.dev_attr.attr,
+ &iio_dev_attr_out1_raw.dev_attr.attr,
+ &iio_dev_attr_out2_raw.dev_attr.attr,
+ &iio_dev_attr_out3_raw.dev_attr.attr,
+ &iio_dev_attr_out0_powerdown.dev_attr.attr,
+ &iio_dev_attr_out1_powerdown.dev_attr.attr,
+ &iio_dev_attr_out2_powerdown.dev_attr.attr,
+ &iio_dev_attr_out3_powerdown.dev_attr.attr,
+ &iio_dev_attr_out_powerdown_mode.dev_attr.attr,
+ &iio_const_attr_out_powerdown_mode_available.dev_attr.attr,
+ &iio_dev_attr_out_scale.dev_attr.attr,
+ NULL,
+};
+
+static const struct attribute_group ad5504_attribute_group = {
+ .attrs = ad5504_attributes,
+};
+
+static struct attribute *ad5501_attributes[] = {
+ &iio_dev_attr_out0_raw.dev_attr.attr,
+ &iio_dev_attr_out0_powerdown.dev_attr.attr,
+ &iio_dev_attr_out_powerdown_mode.dev_attr.attr,
+ &iio_const_attr_out_powerdown_mode_available.dev_attr.attr,
+ &iio_dev_attr_out_scale.dev_attr.attr,
+ NULL,
+};
+
+static const struct attribute_group ad5501_attribute_group = {
+ .attrs = ad5501_attributes,
+};
+
+static IIO_CONST_ATTR(temp0_thresh_rising_value, "110000");
+static IIO_CONST_ATTR(temp0_thresh_rising_en, "1");
+
+static struct attribute *ad5504_ev_attributes[] = {
+ &iio_const_attr_temp0_thresh_rising_value.dev_attr.attr,
+ &iio_const_attr_temp0_thresh_rising_en.dev_attr.attr,
+ NULL,
+};
+
+static struct attribute_group ad5504_ev_attribute_group = {
+ .attrs = ad5504_ev_attributes,
+};
+
+static irqreturn_t ad5504_event_handler(int irq, void *private)
+{
+ iio_push_event(private, 0,
+ IIO_UNMOD_EVENT_CODE(IIO_EV_CLASS_TEMP,
+ 0,
+ IIO_EV_TYPE_THRESH,
+ IIO_EV_DIR_RISING),
+ iio_get_time_ns());
+
+ return IRQ_HANDLED;
+}
+
+static const struct iio_info ad5504_info = {
+ .attrs = &ad5504_attribute_group,
+ .num_interrupt_lines = 1,
+ .event_attrs = &ad5504_ev_attribute_group,
+ .driver_module = THIS_MODULE,
+};
+
+static const struct iio_info ad5501_info = {
+ .attrs = &ad5501_attribute_group,
+ .num_interrupt_lines = 1,
+ .event_attrs = &ad5504_ev_attribute_group,
+ .driver_module = THIS_MODULE,
+};
+
+static int __devinit ad5504_probe(struct spi_device *spi)
+{
+ struct ad5504_platform_data *pdata = spi->dev.platform_data;
+ struct ad5504_state *st;
+ int ret, voltage_uv = 0;
+
+ st = kzalloc(sizeof(*st), GFP_KERNEL);
+ if (st == NULL) {
+ ret = -ENOMEM;
+ goto error_ret;
+ }
+
+ spi_set_drvdata(spi, st);
+
+ st->reg = regulator_get(&spi->dev, "vcc");
+ if (!IS_ERR(st->reg)) {
+ ret = regulator_enable(st->reg);
+ if (ret)
+ goto error_put_reg;
+
+ voltage_uv = regulator_get_voltage(st->reg);
+ }
+
+ if (voltage_uv)
+ st->vref_mv = voltage_uv / 1000;
+ else if (pdata)
+ st->vref_mv = pdata->vref_mv;
+ else
+ dev_warn(&spi->dev, "reference voltage unspecified\n");
+
+ st->spi = spi;
+ st->indio_dev = iio_allocate_device(0);
+ if (st->indio_dev == NULL) {
+ ret = -ENOMEM;
+ goto error_disable_reg;
+ }
+ st->indio_dev->dev.parent = &spi->dev;
+ st->indio_dev->name = spi_get_device_id(st->spi)->name;
+ if (spi_get_device_id(st->spi)->driver_data == ID_AD5501)
+ st->indio_dev->info = &ad5501_info;
+ else
+ st->indio_dev->info = &ad5504_info;
+ st->indio_dev->dev_data = (void *)(st);
+ st->indio_dev->modes = INDIO_DIRECT_MODE;
+
+ ret = iio_device_register(st->indio_dev);
+ if (ret)
+ goto error_free_dev;
+
+ if (spi->irq) {
+ ret = request_threaded_irq(spi->irq,
+ NULL,
+ &ad5504_event_handler,
+ IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
+ spi_get_device_id(st->spi)->name,
+ st->indio_dev);
+ if (ret)
+ goto error_unreg_iio_device;
+ }
+
+ return 0;
+
+error_unreg_iio_device:
+ iio_device_unregister(st->indio_dev);
+error_free_dev:
+ iio_free_device(st->indio_dev);
+error_disable_reg:
+ if (!IS_ERR(st->reg))
+ regulator_disable(st->reg);
+error_put_reg:
+ if (!IS_ERR(st->reg))
+ regulator_put(st->reg);
+
+ kfree(st);
+error_ret:
+ return ret;
+}
+
+static int __devexit ad5504_remove(struct spi_device *spi)
+{
+ struct ad5504_state *st = spi_get_drvdata(spi);
+
+ if (spi->irq)
+ free_irq(spi->irq, st->indio_dev);
+
+ iio_device_unregister(st->indio_dev);
+
+ if (!IS_ERR(st->reg)) {
+ regulator_disable(st->reg);
+ regulator_put(st->reg);
+ }
+
+ kfree(st);
+
+ return 0;
+}
+
+static const struct spi_device_id ad5504_id[] = {
+ {"ad5504", ID_AD5504},
+ {"ad5501", ID_AD5501},
+ {}
+};
+
+static struct spi_driver ad5504_driver = {
+ .driver = {
+ .name = "ad5504",
+ .owner = THIS_MODULE,
+ },
+ .probe = ad5504_probe,
+ .remove = __devexit_p(ad5504_remove),
+ .id_table = ad5504_id,
+};
+
+static __init int ad5504_spi_init(void)
+{
+ return spi_register_driver(&ad5504_driver);
+}
+module_init(ad5504_spi_init);
+
+static __exit void ad5504_spi_exit(void)
+{
+ spi_unregister_driver(&ad5504_driver);
+}
+module_exit(ad5504_spi_exit);
+
+MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
+MODULE_DESCRIPTION("Analog Devices AD5501/AD5501 DAC");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/staging/iio/dac/ad5504.h b/drivers/staging/iio/dac/ad5504.h
new file mode 100644
index 0000000..13ef353
--- /dev/null
+++ b/drivers/staging/iio/dac/ad5504.h
@@ -0,0 +1,70 @@
+/*
+ * AD5504 SPI DAC driver
+ *
+ * Copyright 2011 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2.
+ */
+
+#ifndef SPI_AD5504_H_
+#define SPI_AD5504_H_
+
+#define AD5505_BITS 12
+#define AD5504_RES_MASK ((1 << (AD5505_BITS)) - 1)
+
+#define AD5504_CMD_READ (1 << 15)
+#define AD5504_CMD_WRITE (0 << 15)
+#define AD5504_ADDR(addr) ((addr) << 12)
+
+/* Registers */
+#define AD5504_ADDR_NOOP 0
+#define AD5504_ADDR_DAC0 1
+#define AD5504_ADDR_DAC1 2
+#define AD5504_ADDR_DAC2 3
+#define AD5504_ADDR_DAC3 4
+#define AD5504_ADDR_ALL_DAC 5
+#define AD5504_ADDR_CTRL 7
+
+/* Control Register */
+#define AD5504_DAC_PWR(ch) ((ch) << 2)
+#define AD5504_DAC_PWRDWN_MODE(mode) ((mode) << 6)
+#define AD5504_DAC_PWRDN_20K 0
+#define AD5504_DAC_PWRDN_3STATE 1
+
+/*
+ * TODO: struct ad5504_platform_data needs to go into include/linux/iio
+ */
+
+struct ad5504_platform_data {
+ u16 vref_mv;
+};
+
+/**
+ * struct ad5446_state - driver instance specific data
+ * @indio_dev: the industrial I/O device
+ * @us: spi_device
+ * @reg: supply regulator
+ * @vref_mv: actual reference voltage used
+ * @pwr_down_mask power down mask
+ * @pwr_down_mode current power down mode
+ */
+
+struct ad5504_state {
+ struct iio_dev *indio_dev;
+ struct spi_device *spi;
+ struct regulator *reg;
+ unsigned short vref_mv;
+ unsigned pwr_down_mask;
+ unsigned pwr_down_mode;
+};
+
+/**
+ * ad5504_supported_device_ids:
+ */
+
+enum ad5504_supported_device_ids {
+ ID_AD5504,
+ ID_AD5501,
+};
+
+#endif /* SPI_AD5504_H_ */
diff --git a/drivers/staging/iio/dac/ad5624r_spi.c b/drivers/staging/iio/dac/ad5624r_spi.c
index a945b18..c679981 100644
--- a/drivers/staging/iio/dac/ad5624r_spi.c
+++ b/drivers/staging/iio/dac/ad5624r_spi.c
@@ -174,17 +174,6 @@
}
static IIO_DEVICE_ATTR(out_scale, S_IRUGO, ad5624r_show_scale, NULL, 0);
-static ssize_t ad5624r_show_name(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
- struct ad5624r_state *st = iio_dev_get_devdata(indio_dev);
-
- return sprintf(buf, "%s\n", spi_get_device_id(st->us)->name);
-}
-static IIO_DEVICE_ATTR(name, S_IRUGO, ad5624r_show_name, NULL, 0);
-
static IIO_DEV_ATTR_OUT_RAW(0, ad5624r_write_dac, AD5624R_ADDR_DAC0);
static IIO_DEV_ATTR_OUT_RAW(1, ad5624r_write_dac, AD5624R_ADDR_DAC1);
static IIO_DEV_ATTR_OUT_RAW(2, ad5624r_write_dac, AD5624R_ADDR_DAC2);
@@ -222,7 +211,6 @@
&iio_dev_attr_out_powerdown_mode.dev_attr.attr,
&iio_const_attr_out_powerdown_mode_available.dev_attr.attr,
&iio_dev_attr_out_scale.dev_attr.attr,
- &iio_dev_attr_name.dev_attr.attr,
NULL,
};
@@ -230,6 +218,11 @@
.attrs = ad5624r_attributes,
};
+static const struct iio_info ad5624r_info = {
+ .attrs = &ad5624r_attribute_group,
+ .driver_module = THIS_MODULE,
+};
+
static int __devinit ad5624r_probe(struct spi_device *spi)
{
struct ad5624r_state *st;
@@ -260,15 +253,15 @@
st->vref_mv = st->chip_info->int_vref_mv;
st->us = spi;
- st->indio_dev = iio_allocate_device();
+ st->indio_dev = iio_allocate_device(0);
if (st->indio_dev == NULL) {
ret = -ENOMEM;
goto error_disable_reg;
}
st->indio_dev->dev.parent = &spi->dev;
- st->indio_dev->attrs = &ad5624r_attribute_group;
+ st->indio_dev->name = spi_get_device_id(spi)->name;
+ st->indio_dev->info = &ad5624r_info;
st->indio_dev->dev_data = (void *)(st);
- st->indio_dev->driver_module = THIS_MODULE;
st->indio_dev->modes = INDIO_DIRECT_MODE;
ret = iio_device_register(st->indio_dev);
diff --git a/drivers/staging/iio/dac/ad5791.c b/drivers/staging/iio/dac/ad5791.c
new file mode 100644
index 0000000..4eda25c
--- /dev/null
+++ b/drivers/staging/iio/dac/ad5791.c
@@ -0,0 +1,444 @@
+/*
+ * AD5760, AD5780, AD5781, AD5791 Voltage Output Digital to Analog Converter
+ *
+ * Copyright 2011 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2.
+ */
+
+#include <linux/interrupt.h>
+#include <linux/gpio.h>
+#include <linux/fs.h>
+#include <linux/device.h>
+#include <linux/kernel.h>
+#include <linux/spi/spi.h>
+#include <linux/slab.h>
+#include <linux/sysfs.h>
+#include <linux/regulator/consumer.h>
+
+#include "../iio.h"
+#include "../sysfs.h"
+#include "dac.h"
+#include "ad5791.h"
+
+static int ad5791_spi_write(struct spi_device *spi, u8 addr, u32 val)
+{
+ union {
+ u32 d32;
+ u8 d8[4];
+ } data;
+
+ data.d32 = cpu_to_be32(AD5791_CMD_WRITE |
+ AD5791_ADDR(addr) |
+ (val & AD5791_DAC_MASK));
+
+ return spi_write(spi, &data.d8[1], 3);
+}
+
+static int ad5791_spi_read(struct spi_device *spi, u8 addr, u32 *val)
+{
+ union {
+ u32 d32;
+ u8 d8[4];
+ } data[3];
+ int ret;
+ struct spi_message msg;
+ struct spi_transfer xfers[] = {
+ {
+ .tx_buf = &data[0].d8[1],
+ .bits_per_word = 8,
+ .len = 3,
+ .cs_change = 1,
+ }, {
+ .tx_buf = &data[1].d8[1],
+ .rx_buf = &data[2].d8[1],
+ .bits_per_word = 8,
+ .len = 3,
+ },
+ };
+
+ data[0].d32 = cpu_to_be32(AD5791_CMD_READ |
+ AD5791_ADDR(addr));
+ data[1].d32 = cpu_to_be32(AD5791_ADDR(AD5791_ADDR_NOOP));
+
+ spi_message_init(&msg);
+ spi_message_add_tail(&xfers[0], &msg);
+ spi_message_add_tail(&xfers[1], &msg);
+ ret = spi_sync(spi, &msg);
+
+ *val = be32_to_cpu(data[2].d32);
+
+ return ret;
+}
+
+static ssize_t ad5791_write_dac(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t len)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ struct ad5791_state *st = iio_dev_get_devdata(indio_dev);
+ struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
+ long readin;
+ int ret;
+
+ ret = strict_strtol(buf, 10, &readin);
+ if (ret)
+ return ret;
+
+ readin += (1 << (st->chip_info->bits - 1));
+ readin &= AD5791_RES_MASK(st->chip_info->bits);
+ readin <<= st->chip_info->left_shift;
+
+ ret = ad5791_spi_write(st->spi, this_attr->address, readin);
+ return ret ? ret : len;
+}
+
+static ssize_t ad5791_read_dac(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ struct ad5791_state *st = iio_dev_get_devdata(indio_dev);
+ struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
+ int ret;
+ int val;
+
+ ret = ad5791_spi_read(st->spi, this_attr->address, &val);
+ if (ret)
+ return ret;
+
+ val &= AD5791_DAC_MASK;
+ val >>= st->chip_info->left_shift;
+ val -= (1 << (st->chip_info->bits - 1));
+
+ return sprintf(buf, "%d\n", val);
+}
+
+static ssize_t ad5791_read_powerdown_mode(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ struct ad5791_state *st = iio_dev_get_devdata(indio_dev);
+
+ const char mode[][14] = {"6kohm_to_gnd", "three_state"};
+
+ return sprintf(buf, "%s\n", mode[st->pwr_down_mode]);
+}
+
+static ssize_t ad5791_write_powerdown_mode(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t len)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ struct ad5791_state *st = iio_dev_get_devdata(indio_dev);
+ int ret;
+
+ if (sysfs_streq(buf, "6kohm_to_gnd"))
+ st->pwr_down_mode = AD5791_DAC_PWRDN_6K;
+ else if (sysfs_streq(buf, "three_state"))
+ st->pwr_down_mode = AD5791_DAC_PWRDN_3STATE;
+ else
+ ret = -EINVAL;
+
+ return ret ? ret : len;
+}
+
+static ssize_t ad5791_read_dac_powerdown(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ struct ad5791_state *st = iio_dev_get_devdata(indio_dev);
+
+ return sprintf(buf, "%d\n", st->pwr_down);
+}
+
+static ssize_t ad5791_write_dac_powerdown(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t len)
+{
+ long readin;
+ int ret;
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ struct ad5791_state *st = iio_dev_get_devdata(indio_dev);
+
+ ret = strict_strtol(buf, 10, &readin);
+ if (ret)
+ return ret;
+
+ if (readin == 0) {
+ st->pwr_down = false;
+ st->ctrl &= ~(AD5791_CTRL_OPGND | AD5791_CTRL_DACTRI);
+ } else if (readin == 1) {
+ st->pwr_down = true;
+ if (st->pwr_down_mode == AD5791_DAC_PWRDN_6K)
+ st->ctrl |= AD5791_CTRL_OPGND;
+ else if (st->pwr_down_mode == AD5791_DAC_PWRDN_3STATE)
+ st->ctrl |= AD5791_CTRL_DACTRI;
+ } else
+ ret = -EINVAL;
+
+ ret = ad5791_spi_write(st->spi, AD5791_ADDR_CTRL, st->ctrl);
+
+ return ret ? ret : len;
+}
+
+static ssize_t ad5791_show_scale(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ struct ad5791_state *st = iio_dev_get_devdata(indio_dev);
+ /* Corresponds to Vref / 2^(bits) */
+ unsigned int scale_uv = (st->vref_mv * 1000) >> st->chip_info->bits;
+
+ return sprintf(buf, "%d.%03d\n", scale_uv / 1000, scale_uv % 1000);
+}
+static IIO_DEVICE_ATTR(out_scale, S_IRUGO, ad5791_show_scale, NULL, 0);
+
+static ssize_t ad5791_show_name(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ struct ad5791_state *st = iio_dev_get_devdata(indio_dev);
+
+ return sprintf(buf, "%s\n", spi_get_device_id(st->spi)->name);
+}
+static IIO_DEVICE_ATTR(name, S_IRUGO, ad5791_show_name, NULL, 0);
+
+#define IIO_DEV_ATTR_OUT_RW_RAW(_num, _show, _store, _addr) \
+ IIO_DEVICE_ATTR(out##_num##_raw, \
+ S_IRUGO | S_IWUSR, _show, _store, _addr)
+
+static IIO_DEV_ATTR_OUT_RW_RAW(0, ad5791_read_dac,
+ ad5791_write_dac, AD5791_ADDR_DAC0);
+
+static IIO_DEVICE_ATTR(out_powerdown_mode, S_IRUGO |
+ S_IWUSR, ad5791_read_powerdown_mode,
+ ad5791_write_powerdown_mode, 0);
+
+static IIO_CONST_ATTR(out_powerdown_mode_available,
+ "6kohm_to_gnd three_state");
+
+#define IIO_DEV_ATTR_DAC_POWERDOWN(_num, _show, _store, _addr) \
+ IIO_DEVICE_ATTR(out##_num##_powerdown, \
+ S_IRUGO | S_IWUSR, _show, _store, _addr)
+
+static IIO_DEV_ATTR_DAC_POWERDOWN(0, ad5791_read_dac_powerdown,
+ ad5791_write_dac_powerdown, 0);
+
+static struct attribute *ad5791_attributes[] = {
+ &iio_dev_attr_out0_raw.dev_attr.attr,
+ &iio_dev_attr_out0_powerdown.dev_attr.attr,
+ &iio_dev_attr_out_powerdown_mode.dev_attr.attr,
+ &iio_const_attr_out_powerdown_mode_available.dev_attr.attr,
+ &iio_dev_attr_out_scale.dev_attr.attr,
+ &iio_dev_attr_name.dev_attr.attr,
+ NULL,
+};
+
+static const struct attribute_group ad5791_attribute_group = {
+ .attrs = ad5791_attributes,
+};
+
+static int ad5791_get_lin_comp(unsigned int span)
+{
+ if (span <= 10000)
+ return AD5791_LINCOMP_0_10;
+ else if (span <= 12000)
+ return AD5791_LINCOMP_10_12;
+ else if (span <= 16000)
+ return AD5791_LINCOMP_12_16;
+ else if (span <= 19000)
+ return AD5791_LINCOMP_16_19;
+ else
+ return AD5791_LINCOMP_19_20;
+}
+
+static int ad5780_get_lin_comp(unsigned int span)
+{
+ if (span <= 10000)
+ return AD5780_LINCOMP_0_10;
+ else
+ return AD5780_LINCOMP_10_20;
+}
+
+static const struct ad5791_chip_info ad5791_chip_info_tbl[] = {
+ [ID_AD5760] = {
+ .bits = 16,
+ .left_shift = 4,
+ .get_lin_comp = ad5780_get_lin_comp,
+ },
+ [ID_AD5780] = {
+ .bits = 18,
+ .left_shift = 2,
+ .get_lin_comp = ad5780_get_lin_comp,
+ },
+ [ID_AD5781] = {
+ .bits = 18,
+ .left_shift = 2,
+ .get_lin_comp = ad5791_get_lin_comp,
+ },
+ [ID_AD5791] = {
+ .bits = 20,
+ .left_shift = 0,
+ .get_lin_comp = ad5791_get_lin_comp,
+ },
+};
+
+static const struct iio_info ad5791_info = {
+ .attrs = &ad5791_attribute_group,
+ .driver_module = THIS_MODULE,
+};
+
+static int __devinit ad5791_probe(struct spi_device *spi)
+{
+ struct ad5791_platform_data *pdata = spi->dev.platform_data;
+ struct ad5791_state *st;
+ int ret, pos_voltage_uv = 0, neg_voltage_uv = 0;
+
+ st = kzalloc(sizeof(*st), GFP_KERNEL);
+ if (st == NULL) {
+ ret = -ENOMEM;
+ goto error_ret;
+ }
+
+ spi_set_drvdata(spi, st);
+
+ st->reg_vdd = regulator_get(&spi->dev, "vdd");
+ if (!IS_ERR(st->reg_vdd)) {
+ ret = regulator_enable(st->reg_vdd);
+ if (ret)
+ goto error_put_reg_pos;
+
+ pos_voltage_uv = regulator_get_voltage(st->reg_vdd);
+ }
+
+ st->reg_vss = regulator_get(&spi->dev, "vss");
+ if (!IS_ERR(st->reg_vss)) {
+ ret = regulator_enable(st->reg_vss);
+ if (ret)
+ goto error_put_reg_neg;
+
+ neg_voltage_uv = regulator_get_voltage(st->reg_vss);
+ }
+
+ if (!IS_ERR(st->reg_vss) && !IS_ERR(st->reg_vdd))
+ st->vref_mv = (pos_voltage_uv - neg_voltage_uv) / 1000;
+ else if (pdata)
+ st->vref_mv = pdata->vref_pos_mv - pdata->vref_neg_mv;
+ else
+ dev_warn(&spi->dev, "reference voltage unspecified\n");
+
+ ret = ad5791_spi_write(spi, AD5791_ADDR_SW_CTRL, AD5791_SWCTRL_RESET);
+ if (ret)
+ goto error_disable_reg_neg;
+
+ st->chip_info =
+ &ad5791_chip_info_tbl[spi_get_device_id(spi)->driver_data];
+
+
+ st->ctrl = AD5761_CTRL_LINCOMP(st->chip_info->get_lin_comp(st->vref_mv))
+ | ((pdata && pdata->use_rbuf_gain2) ? 0 : AD5791_CTRL_RBUF) |
+ AD5791_CTRL_BIN2SC;
+
+ ret = ad5791_spi_write(spi, AD5791_ADDR_CTRL, st->ctrl |
+ AD5791_CTRL_OPGND | AD5791_CTRL_DACTRI);
+ if (ret)
+ goto error_disable_reg_neg;
+
+ st->pwr_down = true;
+
+ st->spi = spi;
+ st->indio_dev = iio_allocate_device(0);
+ if (st->indio_dev == NULL) {
+ ret = -ENOMEM;
+ goto error_disable_reg_neg;
+ }
+ st->indio_dev->dev.parent = &spi->dev;
+ st->indio_dev->dev_data = (void *)(st);
+ st->indio_dev->info = &ad5791_info;
+ st->indio_dev->modes = INDIO_DIRECT_MODE;
+
+ ret = iio_device_register(st->indio_dev);
+ if (ret)
+ goto error_free_dev;
+
+ return 0;
+
+error_free_dev:
+ iio_free_device(st->indio_dev);
+
+error_disable_reg_neg:
+ if (!IS_ERR(st->reg_vss))
+ regulator_disable(st->reg_vss);
+error_put_reg_neg:
+ if (!IS_ERR(st->reg_vss))
+ regulator_put(st->reg_vss);
+
+ if (!IS_ERR(st->reg_vdd))
+ regulator_disable(st->reg_vdd);
+error_put_reg_pos:
+ if (!IS_ERR(st->reg_vdd))
+ regulator_put(st->reg_vdd);
+
+ kfree(st);
+error_ret:
+ return ret;
+}
+
+static int __devexit ad5791_remove(struct spi_device *spi)
+{
+ struct ad5791_state *st = spi_get_drvdata(spi);
+
+ iio_device_unregister(st->indio_dev);
+
+ if (!IS_ERR(st->reg_vdd)) {
+ regulator_disable(st->reg_vdd);
+ regulator_put(st->reg_vdd);
+ }
+
+ if (!IS_ERR(st->reg_vss)) {
+ regulator_disable(st->reg_vss);
+ regulator_put(st->reg_vss);
+ }
+
+ kfree(st);
+
+ return 0;
+}
+
+static const struct spi_device_id ad5791_id[] = {
+ {"ad5760", ID_AD5760},
+ {"ad5780", ID_AD5780},
+ {"ad5781", ID_AD5781},
+ {"ad5791", ID_AD5791},
+ {}
+};
+
+static struct spi_driver ad5791_driver = {
+ .driver = {
+ .name = "ad5791",
+ .owner = THIS_MODULE,
+ },
+ .probe = ad5791_probe,
+ .remove = __devexit_p(ad5791_remove),
+ .id_table = ad5791_id,
+};
+
+static __init int ad5791_spi_init(void)
+{
+ return spi_register_driver(&ad5791_driver);
+}
+module_init(ad5791_spi_init);
+
+static __exit void ad5791_spi_exit(void)
+{
+ spi_unregister_driver(&ad5791_driver);
+}
+module_exit(ad5791_spi_exit);
+
+MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
+MODULE_DESCRIPTION("Analog Devices AD5760/AD5780/AD5781/AD5791 DAC");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/staging/iio/dac/ad5791.h b/drivers/staging/iio/dac/ad5791.h
new file mode 100644
index 0000000..f09ad9a
--- /dev/null
+++ b/drivers/staging/iio/dac/ad5791.h
@@ -0,0 +1,116 @@
+/*
+ * AD5791 SPI DAC driver
+ *
+ * Copyright 2011 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2.
+ */
+
+#ifndef SPI_AD5791_H_
+#define SPI_AD5791_H_
+
+#define AD5791_RES_MASK(x) ((1 << (x)) - 1)
+#define AD5791_DAC_MASK AD5791_RES_MASK(20)
+#define AD5791_DAC_MSB (1 << 19)
+
+#define AD5791_CMD_READ (1 << 23)
+#define AD5791_CMD_WRITE (0 << 23)
+#define AD5791_ADDR(addr) ((addr) << 20)
+
+/* Registers */
+#define AD5791_ADDR_NOOP 0
+#define AD5791_ADDR_DAC0 1
+#define AD5791_ADDR_CTRL 2
+#define AD5791_ADDR_CLRCODE 3
+#define AD5791_ADDR_SW_CTRL 4
+
+/* Control Register */
+#define AD5791_CTRL_RBUF (1 << 1)
+#define AD5791_CTRL_OPGND (1 << 2)
+#define AD5791_CTRL_DACTRI (1 << 3)
+#define AD5791_CTRL_BIN2SC (1 << 4)
+#define AD5791_CTRL_SDODIS (1 << 5)
+#define AD5761_CTRL_LINCOMP(x) ((x) << 6)
+
+#define AD5791_LINCOMP_0_10 0
+#define AD5791_LINCOMP_10_12 1
+#define AD5791_LINCOMP_12_16 2
+#define AD5791_LINCOMP_16_19 3
+#define AD5791_LINCOMP_19_20 12
+
+#define AD5780_LINCOMP_0_10 0
+#define AD5780_LINCOMP_10_20 12
+
+/* Software Control Register */
+#define AD5791_SWCTRL_LDAC (1 << 0)
+#define AD5791_SWCTRL_CLR (1 << 1)
+#define AD5791_SWCTRL_RESET (1 << 2)
+
+#define AD5791_DAC_PWRDN_6K 0
+#define AD5791_DAC_PWRDN_3STATE 1
+
+/*
+ * TODO: struct ad5791_platform_data needs to go into include/linux/iio
+ */
+
+/**
+ * struct ad5791_platform_data - platform specific information
+ * @vref_pos_mv: Vdd Positive Analog Supply Volatge (mV)
+ * @vref_neg_mv: Vdd Negative Analog Supply Volatge (mV)
+ * @use_rbuf_gain2: ext. amplifier connected in gain of two configuration
+ */
+
+struct ad5791_platform_data {
+ u16 vref_pos_mv;
+ u16 vref_neg_mv;
+ bool use_rbuf_gain2;
+};
+
+/**
+ * struct ad5791_chip_info - chip specific information
+ * @bits: accuracy of the DAC in bits
+ * @left_shift: number of bits the datum must be shifted
+ * @get_lin_comp: function pointer to the device specific function
+ */
+
+struct ad5791_chip_info {
+ u8 bits;
+ u8 left_shift;
+ int (*get_lin_comp) (unsigned int span);
+};
+
+/**
+ * struct ad5791_state - driver instance specific data
+ * @indio_dev: the industrial I/O device
+ * @us: spi_device
+ * @reg_vdd: positive supply regulator
+ * @reg_vss: negative supply regulator
+ * @chip_info: chip model specific constants
+ * @vref_mv: actual reference voltage used
+ * @pwr_down_mode current power down mode
+ */
+
+struct ad5791_state {
+ struct iio_dev *indio_dev;
+ struct spi_device *spi;
+ struct regulator *reg_vdd;
+ struct regulator *reg_vss;
+ const struct ad5791_chip_info *chip_info;
+ unsigned short vref_mv;
+ unsigned ctrl;
+ unsigned pwr_down_mode;
+ bool pwr_down;
+};
+
+/**
+ * ad5791_supported_device_ids:
+ */
+
+enum ad5791_supported_device_ids {
+ ID_AD5760,
+ ID_AD5780,
+ ID_AD5781,
+ ID_AD5791,
+};
+
+#endif /* SPI_AD5791_H_ */
diff --git a/drivers/staging/iio/dac/max517.c b/drivers/staging/iio/dac/max517.c
index 7071f713..881768d 100644
--- a/drivers/staging/iio/dac/max517.c
+++ b/drivers/staging/iio/dac/max517.c
@@ -189,6 +189,16 @@
return i2c_master_send(client, &outbuf, 1);
}
+static const struct iio_info max517_info = {
+ .attrs = &max517_attribute_group,
+ .driver_module = THIS_MODULE,
+};
+
+static const struct iio_info max518_info = {
+ .attrs = &max517_attribute_group,
+ .driver_module = THIS_MODULE,
+};
+
static int max517_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
@@ -206,7 +216,7 @@
data->client = client;
- data->indio_dev = iio_allocate_device();
+ data->indio_dev = iio_allocate_device(0);
if (data->indio_dev == NULL) {
err = -ENOMEM;
goto exit_free_data;
@@ -217,11 +227,10 @@
/* reduced attribute set for MAX517 */
if (id->driver_data == ID_MAX517)
- data->indio_dev->attrs = &max517_attribute_group;
+ data->indio_dev->info = &max517_info;
else
- data->indio_dev->attrs = &max518_attribute_group;
+ data->indio_dev->info = &max518_info;
data->indio_dev->dev_data = (void *)(data);
- data->indio_dev->driver_module = THIS_MODULE;
data->indio_dev->modes = INDIO_DIRECT_MODE;
/*
diff --git a/drivers/staging/iio/dds/Kconfig b/drivers/staging/iio/dds/Kconfig
index 06b6f3a..e07431d 100644
--- a/drivers/staging/iio/dds/Kconfig
+++ b/drivers/staging/iio/dds/Kconfig
@@ -21,11 +21,11 @@
module will be called ad9832.
config AD9834
- tristate "Analog Devices ad9833/4/ driver"
+ tristate "Analog Devices AD9833/4/7/8 driver"
depends on SPI
help
Say yes here to build support for Analog Devices DDS chip
- AD9833 and AD9834, provides direct access via sysfs.
+ AD9833, AD9834, AD9837 and AD9838, provides direct access via sysfs.
To compile this driver as a module, choose M here: the
module will be called ad9834.
diff --git a/drivers/staging/iio/dds/ad5930.c b/drivers/staging/iio/dds/ad5930.c
index f80039c..490c363 100644
--- a/drivers/staging/iio/dds/ad5930.c
+++ b/drivers/staging/iio/dds/ad5930.c
@@ -87,6 +87,12 @@
.attrs = ad5930_attributes,
};
+static const struct iio_info ad5930_info = {
+ .attrs = &ad5930_attribute_group,
+
+ .driver_module = THIS_MODULE,
+};
+
static int __devinit ad5930_probe(struct spi_device *spi)
{
struct ad5930_state *st;
@@ -102,18 +108,14 @@
mutex_init(&st->lock);
st->sdev = spi;
- st->idev = iio_allocate_device();
+ st->idev = iio_allocate_device(0);
if (st->idev == NULL) {
ret = -ENOMEM;
goto error_free_st;
}
st->idev->dev.parent = &spi->dev;
- st->idev->num_interrupt_lines = 0;
- st->idev->event_attrs = NULL;
-
- st->idev->attrs = &ad5930_attribute_group;
st->idev->dev_data = (void *)(st);
- st->idev->driver_module = THIS_MODULE;
+ st->idev->info = &ad5930_info;
st->idev->modes = INDIO_DIRECT_MODE;
ret = iio_device_register(st->idev);
diff --git a/drivers/staging/iio/dds/ad9832.c b/drivers/staging/iio/dds/ad9832.c
index 3e8491f..e8fe142 100644
--- a/drivers/staging/iio/dds/ad9832.c
+++ b/drivers/staging/iio/dds/ad9832.c
@@ -153,17 +153,6 @@
return ret ? ret : len;
}
-static ssize_t ad9832_show_name(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- struct iio_dev *dev_info = dev_get_drvdata(dev);
- struct ad9832_state *st = iio_dev_get_devdata(dev_info);
-
- return sprintf(buf, "%s\n", spi_get_device_id(st->spi)->name);
-}
-static IIO_DEVICE_ATTR(name, S_IRUGO, ad9832_show_name, NULL, 0);
-
/**
* see dds.h for further information
*/
@@ -199,7 +188,6 @@
&iio_dev_attr_dds0_freqsymbol.dev_attr.attr,
&iio_dev_attr_dds0_phasesymbol.dev_attr.attr,
&iio_dev_attr_dds0_out_enable.dev_attr.attr,
- &iio_dev_attr_name.dev_attr.attr,
NULL,
};
@@ -207,6 +195,11 @@
.attrs = ad9832_attributes,
};
+static const struct iio_info ad9832_info = {
+ .attrs = &ad9832_attribute_group,
+ .driver_module = THIS_MODULE,
+};
+
static int __devinit ad9832_probe(struct spi_device *spi)
{
struct ad9832_platform_data *pdata = spi->dev.platform_data;
@@ -236,16 +229,16 @@
spi_set_drvdata(spi, st);
st->spi = spi;
- st->indio_dev = iio_allocate_device();
+ st->indio_dev = iio_allocate_device(0);
if (st->indio_dev == NULL) {
ret = -ENOMEM;
goto error_disable_reg;
}
st->indio_dev->dev.parent = &spi->dev;
- st->indio_dev->attrs = &ad9832_attribute_group;
+ st->indio_dev->name = spi_get_device_id(spi)->name;
+ st->indio_dev->info = &ad9832_info;
st->indio_dev->dev_data = (void *) st;
- st->indio_dev->driver_module = THIS_MODULE;
st->indio_dev->modes = INDIO_DIRECT_MODE;
/* Setup default messages */
diff --git a/drivers/staging/iio/dds/ad9834.c b/drivers/staging/iio/dds/ad9834.c
index eb1a681..0ebe8d5 100644
--- a/drivers/staging/iio/dds/ad9834.c
+++ b/drivers/staging/iio/dds/ad9834.c
@@ -1,9 +1,9 @@
/*
- * AD9834 SPI DAC driver
+ * AD9833/AD9834/AD9837/AD9838 SPI DDS driver
*
- * Copyright 2010 Analog Devices Inc.
+ * Copyright 2010-2011 Analog Devices Inc.
*
- * Licensed under the GPL-2 or later.
+ * Licensed under the GPL-2.
*/
#include <linux/interrupt.h>
@@ -47,7 +47,7 @@
(AD9834_FREQ_BITS / 2)) &
RES_MASK(AD9834_FREQ_BITS / 2)));
- return spi_sync(st->spi, &st->freq_msg);;
+ return spi_sync(st->spi, &st->freq_msg);
}
static int ad9834_write_phase(struct ad9834_state *st,
@@ -148,7 +148,7 @@
struct ad9834_state *st = dev_info->dev_data;
struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
int ret = 0;
- bool is_ad9833 = st->devid == ID_AD9833;
+ bool is_ad9833_7 = (st->devid == ID_AD9833) || (st->devid == ID_AD9837);
mutex_lock(&dev_info->mlock);
@@ -156,10 +156,10 @@
case 0:
if (sysfs_streq(buf, "sine")) {
st->control &= ~AD9834_MODE;
- if (is_ad9833)
+ if (is_ad9833_7)
st->control &= ~AD9834_OPBITEN;
} else if (sysfs_streq(buf, "triangle")) {
- if (is_ad9833) {
+ if (is_ad9833_7) {
st->control &= ~AD9834_OPBITEN;
st->control |= AD9834_MODE;
} else if (st->control & AD9834_OPBITEN) {
@@ -167,7 +167,7 @@
} else {
st->control |= AD9834_MODE;
}
- } else if (is_ad9833 && sysfs_streq(buf, "square")) {
+ } else if (is_ad9833_7 && sysfs_streq(buf, "square")) {
st->control &= ~AD9834_MODE;
st->control |= AD9834_OPBITEN;
} else {
@@ -198,17 +198,6 @@
return ret ? ret : len;
}
-static ssize_t ad9834_show_name(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- struct iio_dev *dev_info = dev_get_drvdata(dev);
- struct ad9834_state *st = iio_dev_get_devdata(dev_info);
-
- return sprintf(buf, "%s\n", spi_get_device_id(st->spi)->name);
-}
-static IIO_DEVICE_ATTR(name, S_IRUGO, ad9834_show_name, NULL, 0);
-
static ssize_t ad9834_show_out0_wavetype_available(struct device *dev,
struct device_attribute *attr,
char *buf)
@@ -217,7 +206,7 @@
struct ad9834_state *st = iio_dev_get_devdata(dev_info);
char *str;
- if (st->devid == ID_AD9833)
+ if ((st->devid == ID_AD9833) || (st->devid == ID_AD9837))
str = "sine triangle square";
else if (st->control & AD9834_OPBITEN)
str = "sine";
@@ -288,7 +277,6 @@
&iio_dev_attr_dds0_out1_wavetype.dev_attr.attr,
&iio_dev_attr_dds0_out0_wavetype_available.dev_attr.attr,
&iio_dev_attr_dds0_out1_wavetype_available.dev_attr.attr,
- &iio_dev_attr_name.dev_attr.attr,
NULL,
};
@@ -301,13 +289,12 @@
mode_t mode = attr->mode;
- if (st->devid == ID_AD9834)
- return mode;
-
- if ((attr == &iio_dev_attr_dds0_out1_enable.dev_attr.attr) ||
+ if (((st->devid == ID_AD9833) || (st->devid == ID_AD9837)) &&
+ ((attr == &iio_dev_attr_dds0_out1_enable.dev_attr.attr) ||
(attr == &iio_dev_attr_dds0_out1_wavetype.dev_attr.attr) ||
(attr ==
- &iio_dev_attr_dds0_out1_wavetype_available.dev_attr.attr))
+ &iio_dev_attr_dds0_out1_wavetype_available.dev_attr.attr) ||
+ (attr == &iio_dev_attr_dds0_pincontrol_en.dev_attr.attr)))
mode = 0;
return mode;
@@ -318,6 +305,11 @@
.is_visible = ad9834_attr_is_visible,
};
+static const struct iio_info ad9834_info = {
+ .attrs = &ad9834_attribute_group,
+ .driver_module = THIS_MODULE,
+};
+
static int __devinit ad9834_probe(struct spi_device *spi)
{
struct ad9834_platform_data *pdata = spi->dev.platform_data;
@@ -349,16 +341,16 @@
st->spi = spi;
st->devid = spi_get_device_id(spi)->driver_data;
- st->indio_dev = iio_allocate_device();
+ st->indio_dev = iio_allocate_device(0);
if (st->indio_dev == NULL) {
ret = -ENOMEM;
goto error_disable_reg;
}
st->indio_dev->dev.parent = &spi->dev;
- st->indio_dev->attrs = &ad9834_attribute_group;
+ st->indio_dev->name = spi_get_device_id(spi)->name;
+ st->indio_dev->info = &ad9834_info;
st->indio_dev->dev_data = (void *) st;
- st->indio_dev->driver_module = THIS_MODULE;
st->indio_dev->modes = INDIO_DIRECT_MODE;
/* Setup default messages */
@@ -445,6 +437,8 @@
static const struct spi_device_id ad9834_id[] = {
{"ad9833", ID_AD9833},
{"ad9834", ID_AD9834},
+ {"ad9837", ID_AD9837},
+ {"ad9838", ID_AD9838},
{}
};
@@ -472,6 +466,6 @@
module_exit(ad9834_exit);
MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
-MODULE_DESCRIPTION("Analog Devices AD9833/AD9834 DDS");
+MODULE_DESCRIPTION("Analog Devices AD9833/AD9834/AD9837/AD9838 DDS");
MODULE_LICENSE("GPL v2");
MODULE_ALIAS("spi:ad9834");
diff --git a/drivers/staging/iio/dds/ad9834.h b/drivers/staging/iio/dds/ad9834.h
index 0fc3b88..2abd635 100644
--- a/drivers/staging/iio/dds/ad9834.h
+++ b/drivers/staging/iio/dds/ad9834.h
@@ -1,9 +1,9 @@
/*
- * AD9834 SPI DDS driver
+ * AD9833/AD9834/AD9837/AD9838 SPI DDS driver
*
- * Copyright 2010 Analog Devices Inc.
+ * Copyright 2010-2011 Analog Devices Inc.
*
- * Licensed under the GPL-2 or later.
+ * Licensed under the GPL-2.
*/
#ifndef IIO_DDS_AD9834_H_
#define IIO_DDS_AD9834_H_
@@ -107,6 +107,8 @@
enum ad9834_supported_device_ids {
ID_AD9833,
ID_AD9834,
+ ID_AD9837,
+ ID_AD9838,
};
#endif /* IIO_DDS_AD9834_H_ */
diff --git a/drivers/staging/iio/dds/ad9850.c b/drivers/staging/iio/dds/ad9850.c
index b259bfe..b580d85 100644
--- a/drivers/staging/iio/dds/ad9850.c
+++ b/drivers/staging/iio/dds/ad9850.c
@@ -73,6 +73,11 @@
.attrs = ad9850_attributes,
};
+static const struct iio_info ad9850_info = {
+ .attrs = &ad9850_attribute_group,
+ .driver_module = THIS_MODULE,
+};
+
static int __devinit ad9850_probe(struct spi_device *spi)
{
struct ad9850_state *st;
@@ -88,18 +93,15 @@
mutex_init(&st->lock);
st->sdev = spi;
- st->idev = iio_allocate_device();
+ st->idev = iio_allocate_device(0);
if (st->idev == NULL) {
ret = -ENOMEM;
goto error_free_st;
}
st->idev->dev.parent = &spi->dev;
- st->idev->num_interrupt_lines = 0;
- st->idev->event_attrs = NULL;
- st->idev->attrs = &ad9850_attribute_group;
+ st->idev->info = &ad9850_info;
st->idev->dev_data = (void *)(st);
- st->idev->driver_module = THIS_MODULE;
st->idev->modes = INDIO_DIRECT_MODE;
ret = iio_device_register(st->idev);
diff --git a/drivers/staging/iio/dds/ad9852.c b/drivers/staging/iio/dds/ad9852.c
index 594fb6a..08020f9 100644
--- a/drivers/staging/iio/dds/ad9852.c
+++ b/drivers/staging/iio/dds/ad9852.c
@@ -222,6 +222,11 @@
.attrs = ad9852_attributes,
};
+static const struct iio_info ad9852_info = {
+ .attrs = &ad9852_attribute_group,
+ .driver_module = THIS_MODULE,
+};
+
static int __devinit ad9852_probe(struct spi_device *spi)
{
struct ad9852_state *st;
@@ -237,18 +242,15 @@
mutex_init(&st->lock);
st->sdev = spi;
- st->idev = iio_allocate_device();
+ st->idev = iio_allocate_device(0);
if (st->idev == NULL) {
ret = -ENOMEM;
goto error_free_st;
}
st->idev->dev.parent = &spi->dev;
- st->idev->num_interrupt_lines = 0;
- st->idev->event_attrs = NULL;
- st->idev->attrs = &ad9852_attribute_group;
+ st->idev->info = &ad9852_info;
st->idev->dev_data = (void *)(st);
- st->idev->driver_module = THIS_MODULE;
st->idev->modes = INDIO_DIRECT_MODE;
ret = iio_device_register(st->idev);
diff --git a/drivers/staging/iio/dds/ad9910.c b/drivers/staging/iio/dds/ad9910.c
index e8fb75c..97d75d7 100644
--- a/drivers/staging/iio/dds/ad9910.c
+++ b/drivers/staging/iio/dds/ad9910.c
@@ -357,6 +357,11 @@
.attrs = ad9910_attributes,
};
+static const struct iio_info ad9910_info = {
+ .attrs = &ad9910_attribute_group,
+ .driver_module = THIS_MODULE,
+};
+
static int __devinit ad9910_probe(struct spi_device *spi)
{
struct ad9910_state *st;
@@ -372,18 +377,15 @@
mutex_init(&st->lock);
st->sdev = spi;
- st->idev = iio_allocate_device();
+ st->idev = iio_allocate_device(0);
if (st->idev == NULL) {
ret = -ENOMEM;
goto error_free_st;
}
st->idev->dev.parent = &spi->dev;
- st->idev->num_interrupt_lines = 0;
- st->idev->event_attrs = NULL;
- st->idev->attrs = &ad9910_attribute_group;
+ st->idev->info = &ad9910_info;
st->idev->dev_data = (void *)(st);
- st->idev->driver_module = THIS_MODULE;
st->idev->modes = INDIO_DIRECT_MODE;
ret = iio_device_register(st->idev);
diff --git a/drivers/staging/iio/dds/ad9951.c b/drivers/staging/iio/dds/ad9951.c
index 57eddf6..d4dfcd4 100644
--- a/drivers/staging/iio/dds/ad9951.c
+++ b/drivers/staging/iio/dds/ad9951.c
@@ -166,6 +166,11 @@
.attrs = ad9951_attributes,
};
+static const struct iio_info ad9951_info = {
+ .attrs = &ad9951_attribute_group,
+ .driver_module = THIS_MODULE,
+};
+
static int __devinit ad9951_probe(struct spi_device *spi)
{
struct ad9951_state *st;
@@ -181,18 +186,15 @@
mutex_init(&st->lock);
st->sdev = spi;
- st->idev = iio_allocate_device();
+ st->idev = iio_allocate_device(0);
if (st->idev == NULL) {
ret = -ENOMEM;
goto error_free_st;
}
st->idev->dev.parent = &spi->dev;
- st->idev->num_interrupt_lines = 0;
- st->idev->event_attrs = NULL;
- st->idev->attrs = &ad9951_attribute_group;
+ st->idev->info = &ad9951_info;
st->idev->dev_data = (void *)(st);
- st->idev->driver_module = THIS_MODULE;
st->idev->modes = INDIO_DIRECT_MODE;
ret = iio_device_register(st->idev);
diff --git a/drivers/staging/iio/gyro/Kconfig b/drivers/staging/iio/gyro/Kconfig
index 8b78fa0..ae2e7d3 100644
--- a/drivers/staging/iio/gyro/Kconfig
+++ b/drivers/staging/iio/gyro/Kconfig
@@ -35,3 +35,13 @@
This driver can also be built as a module. If so, the module
will be called adis16260.
+
+config ADXRS450
+ tristate "Analog Devices ADXRS450 Digital Output Gyroscope SPI driver"
+ depends on SPI
+ help
+ Say yes here to build support for Analog Devices ADXRS450 programmable
+ digital output gyroscope.
+
+ This driver can also be built as a module. If so, the module
+ will be called adxrs450.
diff --git a/drivers/staging/iio/gyro/Makefile b/drivers/staging/iio/gyro/Makefile
index 2764c15..2212240 100644
--- a/drivers/staging/iio/gyro/Makefile
+++ b/drivers/staging/iio/gyro/Makefile
@@ -17,3 +17,6 @@
adis16251-y := adis16251_core.o
obj-$(CONFIG_ADIS16251) += adis16251.o
+
+adxrs450-y := adxrs450_core.o
+obj-$(CONFIG_ADXRS450) += adxrs450.o
diff --git a/drivers/staging/iio/gyro/adis16060_core.c b/drivers/staging/iio/gyro/adis16060_core.c
index ae53e71..edf9e3b 100644
--- a/drivers/staging/iio/gyro/adis16060_core.c
+++ b/drivers/staging/iio/gyro/adis16060_core.c
@@ -133,6 +133,11 @@
.attrs = adis16060_attributes,
};
+static const struct iio_info adis16060_info = {
+ .attrs = &adis16060_attribute_group,
+ .driver_module = THIS_MODULE,
+};
+
static int __devinit adis16060_r_probe(struct spi_device *spi)
{
int ret, regdone = 0;
@@ -147,16 +152,15 @@
st->us_r = spi;
mutex_init(&st->buf_lock);
/* setup the industrialio driver allocated elements */
- st->indio_dev = iio_allocate_device();
+ st->indio_dev = iio_allocate_device(0);
if (st->indio_dev == NULL) {
ret = -ENOMEM;
goto error_free_st;
}
st->indio_dev->dev.parent = &spi->dev;
- st->indio_dev->attrs = &adis16060_attribute_group;
+ st->indio_dev->info = &adis16060_info;
st->indio_dev->dev_data = (void *)(st);
- st->indio_dev->driver_module = THIS_MODULE;
st->indio_dev->modes = INDIO_DIRECT_MODE;
ret = iio_device_register(st->indio_dev);
diff --git a/drivers/staging/iio/gyro/adis16080_core.c b/drivers/staging/iio/gyro/adis16080_core.c
index ef9e304..d42690b 100644
--- a/drivers/staging/iio/gyro/adis16080_core.c
+++ b/drivers/staging/iio/gyro/adis16080_core.c
@@ -110,14 +110,12 @@
ADIS16080_DIN_TEMP);
static IIO_DEV_ATTR_IN_RAW(0, adis16080_read, ADIS16080_DIN_AIN1);
static IIO_DEV_ATTR_IN_RAW(1, adis16080_read, ADIS16080_DIN_AIN2);
-static IIO_CONST_ATTR(name, "adis16080");
static struct attribute *adis16080_attributes[] = {
&iio_dev_attr_gyro_z_raw.dev_attr.attr,
&iio_dev_attr_temp_raw.dev_attr.attr,
&iio_dev_attr_in0_raw.dev_attr.attr,
&iio_dev_attr_in1_raw.dev_attr.attr,
- &iio_const_attr_name.dev_attr.attr,
NULL
};
@@ -125,6 +123,11 @@
.attrs = adis16080_attributes,
};
+static const struct iio_info adis16080_info = {
+ .attrs = &adis16080_attribute_group,
+ .driver_module = THIS_MODULE,
+};
+
static int __devinit adis16080_probe(struct spi_device *spi)
{
int ret, regdone = 0;
@@ -140,16 +143,16 @@
st->us = spi;
mutex_init(&st->buf_lock);
/* setup the industrialio driver allocated elements */
- st->indio_dev = iio_allocate_device();
+ st->indio_dev = iio_allocate_device(0);
if (st->indio_dev == NULL) {
ret = -ENOMEM;
goto error_free_st;
}
+ st->indio_dev->name = spi->dev.driver->name;
st->indio_dev->dev.parent = &spi->dev;
- st->indio_dev->attrs = &adis16080_attribute_group;
+ st->indio_dev->info = &adis16080_info;
st->indio_dev->dev_data = (void *)(st);
- st->indio_dev->driver_module = THIS_MODULE;
st->indio_dev->modes = INDIO_DIRECT_MODE;
ret = iio_device_register(st->indio_dev);
diff --git a/drivers/staging/iio/gyro/adis16130_core.c b/drivers/staging/iio/gyro/adis16130_core.c
index 70e2831..14d5a34 100644
--- a/drivers/staging/iio/gyro/adis16130_core.c
+++ b/drivers/staging/iio/gyro/adis16130_core.c
@@ -155,8 +155,6 @@
static IIO_DEVICE_ATTR(temp_raw, S_IRUGO, adis16130_val_read, NULL,
ADIS16130_TEMPDATA);
-static IIO_CONST_ATTR(name, "adis16130");
-
static IIO_DEV_ATTR_GYRO_Z(adis16130_val_read, ADIS16130_RATEDATA);
static IIO_DEVICE_ATTR(gyro_z_type, S_IWUSR | S_IRUGO, adis16130_bitsmode_read,
@@ -167,7 +165,6 @@
static struct attribute *adis16130_attributes[] = {
&iio_dev_attr_temp_raw.dev_attr.attr,
- &iio_const_attr_name.dev_attr.attr,
&iio_dev_attr_gyro_z_raw.dev_attr.attr,
&iio_dev_attr_gyro_z_type.dev_attr.attr,
&iio_const_attr_gyro_z_type_available.dev_attr.attr,
@@ -178,6 +175,11 @@
.attrs = adis16130_attributes,
};
+static const struct iio_info adis16130_info = {
+ .attrs = &adis16130_attribute_group,
+ .driver_module = THIS_MODULE,
+};
+
static int __devinit adis16130_probe(struct spi_device *spi)
{
int ret;
@@ -191,16 +193,16 @@
st->us = spi;
mutex_init(&st->buf_lock);
/* setup the industrialio driver allocated elements */
- st->indio_dev = iio_allocate_device();
+ st->indio_dev = iio_allocate_device(0);
if (st->indio_dev == NULL) {
ret = -ENOMEM;
goto error_free_st;
}
+ st->indio_dev->name = spi->dev.driver->name;
st->indio_dev->dev.parent = &spi->dev;
- st->indio_dev->attrs = &adis16130_attribute_group;
+ st->indio_dev->info = &adis16130_info;
st->indio_dev->dev_data = (void *)(st);
- st->indio_dev->driver_module = THIS_MODULE;
st->indio_dev->modes = INDIO_DIRECT_MODE;
st->mode = 1;
diff --git a/drivers/staging/iio/gyro/adis16260.h b/drivers/staging/iio/gyro/adis16260.h
index 1369501..702dc98 100644
--- a/drivers/staging/iio/gyro/adis16260.h
+++ b/drivers/staging/iio/gyro/adis16260.h
@@ -85,9 +85,6 @@
/**
* struct adis16260_state - device instance specific data
* @us: actual spi_device
- * @work_trigger_to_ring: bh for triggered event handling
- * @inter: used to check if new interrupt has been triggered
- * @last_timestamp: passing timestamp from th to bh of interrupt handler
* @indio_dev: industrial I/O device structure
* @trig: data ready trigger registered with iio
* @tx: transmit buffer
@@ -97,8 +94,6 @@
**/
struct adis16260_state {
struct spi_device *us;
- struct work_struct work_trigger_to_ring;
- s64 last_timestamp;
struct iio_dev *indio_dev;
struct iio_trigger *trig;
u8 *tx;
@@ -107,7 +102,7 @@
unsigned negate:1;
};
-int adis16260_set_irq(struct device *dev, bool enable);
+int adis16260_set_irq(struct iio_dev *indio_dev, bool enable);
#ifdef CONFIG_IIO_RING_BUFFER
/* At the moment triggers are only used for ring buffer
diff --git a/drivers/staging/iio/gyro/adis16260_core.c b/drivers/staging/iio/gyro/adis16260_core.c
index 69a29ec..3dc9a27 100644
--- a/drivers/staging/iio/gyro/adis16260_core.c
+++ b/drivers/staging/iio/gyro/adis16260_core.c
@@ -28,20 +28,19 @@
#define DRIVER_NAME "adis16260"
-static int adis16260_check_status(struct device *dev);
+static int adis16260_check_status(struct iio_dev *indio_dev);
/**
* adis16260_spi_write_reg_8() - write single byte to a register
- * @dev: device associated with child of actual device (iio_dev or iio_trig)
+ * @indio_dev: iio_dev for the device
* @reg_address: the address of the register to be written
* @val: the value to write
**/
-static int adis16260_spi_write_reg_8(struct device *dev,
+static int adis16260_spi_write_reg_8(struct iio_dev *indio_dev,
u8 reg_address,
u8 val)
{
int ret;
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct adis16260_state *st = iio_dev_get_devdata(indio_dev);
mutex_lock(&st->buf_lock);
@@ -56,18 +55,17 @@
/**
* adis16260_spi_write_reg_16() - write 2 bytes to a pair of registers
- * @dev: device associated with child of actual device (iio_dev or iio_trig)
+ * @indio_dev: iio_dev for the device
* @reg_address: the address of the lower of the two registers. Second register
* is assumed to have address one greater.
* @val: value to be written
**/
-static int adis16260_spi_write_reg_16(struct device *dev,
+static int adis16260_spi_write_reg_16(struct iio_dev *indio_dev,
u8 lower_reg_address,
u16 value)
{
int ret;
struct spi_message msg;
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct adis16260_state *st = iio_dev_get_devdata(indio_dev);
struct spi_transfer xfers[] = {
{
@@ -80,7 +78,6 @@
.tx_buf = st->tx + 2,
.bits_per_word = 8,
.len = 2,
- .cs_change = 1,
.delay_usecs = 20,
},
};
@@ -102,17 +99,16 @@
/**
* adis16260_spi_read_reg_16() - read 2 bytes from a 16-bit register
- * @dev: device associated with child of actual device (iio_dev or iio_trig)
+ * @indio_dev: iio_dev for the device
* @reg_address: the address of the lower of the two registers. Second register
* is assumed to have address one greater.
* @val: somewhere to pass back the value read
**/
-static int adis16260_spi_read_reg_16(struct device *dev,
+static int adis16260_spi_read_reg_16(struct iio_dev *indio_dev,
u8 lower_reg_address,
u16 *val)
{
struct spi_message msg;
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
struct adis16260_state *st = iio_dev_get_devdata(indio_dev);
int ret;
struct spi_transfer xfers[] = {
@@ -126,7 +122,6 @@
.rx_buf = st->rx,
.bits_per_word = 8,
.len = 2,
- .cs_change = 1,
.delay_usecs = 30,
},
};
@@ -152,92 +147,6 @@
return ret;
}
-static ssize_t adis16260_spi_read_signed(struct device *dev,
- struct device_attribute *attr,
- char *buf,
- unsigned bits)
-{
- int ret;
- s16 val = 0;
- unsigned shift = 16 - bits;
- struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
-
- ret = adis16260_spi_read_reg_16(dev, this_attr->address, (u16 *)&val);
- if (ret)
- return ret;
-
- if (val & ADIS16260_ERROR_ACTIVE)
- adis16260_check_status(dev);
- val = ((s16)(val << shift) >> shift);
- return sprintf(buf, "%d\n", val);
-}
-
-static ssize_t adis16260_read_12bit_unsigned(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- int ret;
- u16 val = 0;
- struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
-
- ret = adis16260_spi_read_reg_16(dev, this_attr->address, &val);
- if (ret)
- return ret;
-
- if (val & ADIS16260_ERROR_ACTIVE)
- adis16260_check_status(dev);
-
- return sprintf(buf, "%u\n", val & 0x0FFF);
-}
-
-static ssize_t adis16260_read_12bit_signed(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
- ssize_t ret;
-
- /* Take the iio_dev status lock */
- mutex_lock(&indio_dev->mlock);
- ret = adis16260_spi_read_signed(dev, attr, buf, 12);
- mutex_unlock(&indio_dev->mlock);
-
- return ret;
-}
-
-static ssize_t adis16260_read_14bit_signed(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
- ssize_t ret;
-
- /* Take the iio_dev status lock */
- mutex_lock(&indio_dev->mlock);
- ret = adis16260_spi_read_signed(dev, attr, buf, 14);
- mutex_unlock(&indio_dev->mlock);
-
- return ret;
-}
-
-static ssize_t adis16260_write_16bit(struct device *dev,
- struct device_attribute *attr,
- const char *buf,
- size_t len)
-{
- struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
- int ret;
- long val;
-
- ret = strict_strtol(buf, 10, &val);
- if (ret)
- goto error_ret;
- ret = adis16260_spi_write_reg_16(dev, this_attr->address, val);
-
-error_ret:
- return ret ? ret : len;
-}
-
static ssize_t adis16260_read_frequency_available(struct device *dev,
struct device_attribute *attr,
char *buf)
@@ -259,7 +168,7 @@
int ret, len = 0;
u16 t;
int sps;
- ret = adis16260_spi_read_reg_16(dev,
+ ret = adis16260_spi_read_reg_16(indio_dev,
ADIS16260_SMPL_PRD,
&t);
if (ret)
@@ -305,7 +214,7 @@
st->us->max_speed_hz = ADIS16260_SPI_SLOW;
else
st->us->max_speed_hz = ADIS16260_SPI_FAST;
- ret = adis16260_spi_write_reg_8(dev,
+ ret = adis16260_spi_write_reg_8(indio_dev,
ADIS16260_SMPL_PRD,
t);
@@ -314,33 +223,14 @@
return ret ? ret : len;
}
-static ssize_t adis16260_read_gyro_scale(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
- struct adis16260_state *st = iio_dev_get_devdata(indio_dev);
- ssize_t ret = 0;
-
- if (st->negate)
- ret = sprintf(buf, "-");
- /* Take the iio_dev status lock */
- if (spi_get_device_id(st->us)->driver_data)
- ret += sprintf(buf + ret, "%s\n", "0.00031974432");
- else
- ret += sprintf(buf + ret, "%s\n", "0.00127862821");
-
- return ret;
-}
-
-static int adis16260_reset(struct device *dev)
+static int adis16260_reset(struct iio_dev *indio_dev)
{
int ret;
- ret = adis16260_spi_write_reg_8(dev,
+ ret = adis16260_spi_write_reg_8(indio_dev,
ADIS16260_GLOB_CMD,
ADIS16260_GLOB_CMD_SW_RESET);
if (ret)
- dev_err(dev, "problem resetting device");
+ dev_err(&indio_dev->dev, "problem resetting device");
return ret;
}
@@ -349,22 +239,23 @@
struct device_attribute *attr,
const char *buf, size_t len)
{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
if (len < 1)
return -EINVAL;
switch (buf[0]) {
case '1':
case 'y':
case 'Y':
- return adis16260_reset(dev);
+ return adis16260_reset(indio_dev);
}
return -EINVAL;
}
-int adis16260_set_irq(struct device *dev, bool enable)
+int adis16260_set_irq(struct iio_dev *indio_dev, bool enable)
{
int ret;
u16 msc;
- ret = adis16260_spi_read_reg_16(dev, ADIS16260_MSC_CTRL, &msc);
+ ret = adis16260_spi_read_reg_16(indio_dev, ADIS16260_MSC_CTRL, &msc);
if (ret)
goto error_ret;
@@ -374,7 +265,7 @@
else
msc &= ~ADIS16260_MSC_CTRL_DATA_RDY_EN;
- ret = adis16260_spi_write_reg_16(dev, ADIS16260_MSC_CTRL, msc);
+ ret = adis16260_spi_write_reg_16(indio_dev, ADIS16260_MSC_CTRL, msc);
if (ret)
goto error_ret;
@@ -383,41 +274,44 @@
}
/* Power down the device */
-static int adis16260_stop_device(struct device *dev)
+static int adis16260_stop_device(struct iio_dev *indio_dev)
{
int ret;
u16 val = ADIS16260_SLP_CNT_POWER_OFF;
- ret = adis16260_spi_write_reg_16(dev, ADIS16260_SLP_CNT, val);
+ ret = adis16260_spi_write_reg_16(indio_dev, ADIS16260_SLP_CNT, val);
if (ret)
- dev_err(dev, "problem with turning device off: SLP_CNT");
+ dev_err(&indio_dev->dev, "problem with turning device off: SLP_CNT");
return ret;
}
-static int adis16260_self_test(struct device *dev)
+static int adis16260_self_test(struct iio_dev *indio_dev)
{
int ret;
- ret = adis16260_spi_write_reg_16(dev,
+ ret = adis16260_spi_write_reg_16(indio_dev,
ADIS16260_MSC_CTRL,
ADIS16260_MSC_CTRL_MEM_TEST);
if (ret) {
- dev_err(dev, "problem starting self test");
+ dev_err(&indio_dev->dev, "problem starting self test");
goto err_ret;
}
- adis16260_check_status(dev);
+ adis16260_check_status(indio_dev);
err_ret:
return ret;
}
-static int adis16260_check_status(struct device *dev)
+static int adis16260_check_status(struct iio_dev *indio_dev)
{
u16 status;
int ret;
+ struct device *dev = &indio_dev->dev;
- ret = adis16260_spi_read_reg_16(dev, ADIS16260_DIAG_STAT, &status);
+ ret = adis16260_spi_read_reg_16(indio_dev,
+ ADIS16260_DIAG_STAT,
+ &status);
if (ret < 0) {
dev_err(dev, "Reading status failed\n");
@@ -443,130 +337,240 @@
return ret;
}
-static int adis16260_initial_setup(struct adis16260_state *st)
+static int adis16260_initial_setup(struct iio_dev *indio_dev)
{
int ret;
- struct device *dev = &st->indio_dev->dev;
+ struct device *dev = &indio_dev->dev;
/* Disable IRQ */
- ret = adis16260_set_irq(dev, false);
+ ret = adis16260_set_irq(indio_dev, false);
if (ret) {
dev_err(dev, "disable irq failed");
goto err_ret;
}
/* Do self test */
- ret = adis16260_self_test(dev);
+ ret = adis16260_self_test(indio_dev);
if (ret) {
dev_err(dev, "self test failure");
goto err_ret;
}
/* Read status register to check the result */
- ret = adis16260_check_status(dev);
+ ret = adis16260_check_status(indio_dev);
if (ret) {
- adis16260_reset(dev);
+ adis16260_reset(indio_dev);
dev_err(dev, "device not playing ball -> reset");
msleep(ADIS16260_STARTUP_DELAY);
- ret = adis16260_check_status(dev);
+ ret = adis16260_check_status(indio_dev);
if (ret) {
dev_err(dev, "giving up");
goto err_ret;
}
}
- printk(KERN_INFO DRIVER_NAME ": at CS%d (irq %d)\n",
- st->us->chip_select, st->us->irq);
-
err_ret:
return ret;
}
-static IIO_DEV_ATTR_IN_NAMED_RAW(0, supply,
- adis16260_read_12bit_unsigned,
- ADIS16260_SUPPLY_OUT);
-static IIO_CONST_ATTR_IN_NAMED_SCALE(0, supply, "0.0018315");
-
-static IIO_DEV_ATTR_TEMP_RAW(adis16260_read_12bit_unsigned);
-static IIO_CONST_ATTR_TEMP_OFFSET("25");
-static IIO_CONST_ATTR_TEMP_SCALE("0.1453");
-
-static IIO_DEV_ATTR_IN_RAW(1, adis16260_read_12bit_unsigned,
- ADIS16260_AUX_ADC);
-static IIO_CONST_ATTR(in1_scale, "0.0006105");
-
static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO,
adis16260_read_frequency,
adis16260_write_frequency);
static IIO_DEVICE_ATTR(reset, S_IWUSR, NULL, adis16260_write_reset, 0);
-
static IIO_DEVICE_ATTR(sampling_frequency_available,
S_IRUGO, adis16260_read_frequency_available, NULL, 0);
-static IIO_CONST_ATTR_NAME("adis16260");
+enum adis16260_channel {
+ gyro,
+ temp,
+ in_supply,
+ in_aux,
+ angle,
+};
+#define ADIS16260_GYRO_CHANNEL_SET(axis, mod) \
+ struct iio_chan_spec adis16260_channels_##axis[] = { \
+ IIO_CHAN(IIO_GYRO, 1, 0, 0, NULL, 0, mod, \
+ (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE) | \
+ (1 << IIO_CHAN_INFO_CALIBSCALE_SEPARATE) | \
+ (1 << IIO_CHAN_INFO_SCALE_SEPARATE), \
+ gyro, ADIS16260_SCAN_GYRO, \
+ IIO_ST('s', 14, 16, 0), 0), \
+ IIO_CHAN(IIO_ANGL, 1, 0, 0, NULL, 0, mod, \
+ 0, \
+ angle, ADIS16260_SCAN_ANGL, \
+ IIO_ST('u', 14, 16, 0), 0), \
+ IIO_CHAN(IIO_TEMP, 0, 1, 0, NULL, 0, 0, \
+ (1 << IIO_CHAN_INFO_OFFSET_SEPARATE) | \
+ (1 << IIO_CHAN_INFO_SCALE_SEPARATE), \
+ temp, ADIS16260_SCAN_TEMP, \
+ IIO_ST('u', 12, 16, 0), 0), \
+ IIO_CHAN(IIO_IN, 0, 1, 0, "supply", 0, 0, \
+ (1 << IIO_CHAN_INFO_SCALE_SEPARATE), \
+ in_supply, ADIS16260_SCAN_SUPPLY, \
+ IIO_ST('u', 12, 16, 0), 0), \
+ IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 1, 0, \
+ (1 << IIO_CHAN_INFO_SCALE_SEPARATE), \
+ in_aux, ADIS16260_SCAN_AUX_ADC, \
+ IIO_ST('u', 12, 16, 0), 0), \
+ IIO_CHAN_SOFT_TIMESTAMP(5) \
+ }
-static struct attribute *adis16260_event_attributes[] = {
+static const ADIS16260_GYRO_CHANNEL_SET(x, IIO_MOD_X);
+static const ADIS16260_GYRO_CHANNEL_SET(y, IIO_MOD_Y);
+static const ADIS16260_GYRO_CHANNEL_SET(z, IIO_MOD_Z);
+
+static const u8 adis16260_addresses[5][3] = {
+ [gyro] = { ADIS16260_GYRO_OUT,
+ ADIS16260_GYRO_OFF,
+ ADIS16260_GYRO_SCALE },
+ [angle] = { ADIS16260_ANGL_OUT },
+ [in_supply] = { ADIS16260_SUPPLY_OUT },
+ [in_aux] = { ADIS16260_AUX_ADC },
+ [temp] = { ADIS16260_TEMP_OUT },
+};
+static int adis16260_read_raw(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ int *val, int *val2,
+ long mask)
+{
+ struct adis16260_state *st = iio_dev_get_devdata(indio_dev);
+ int ret;
+ int bits;
+ u8 addr;
+ s16 val16;
+
+ switch (mask) {
+ case 0:
+ mutex_lock(&indio_dev->mlock);
+ addr = adis16260_addresses[chan->address][0];
+ ret = adis16260_spi_read_reg_16(indio_dev, addr, &val16);
+ if (ret)
+ return ret;
+
+ if (val16 & ADIS16260_ERROR_ACTIVE) {
+ ret = adis16260_check_status(indio_dev);
+ if (ret)
+ return ret;
+ }
+ val16 = val16 & ((1 << chan->scan_type.realbits) - 1);
+ if (chan->scan_type.sign == 's')
+ val16 = (s16)(val16 <<
+ (16 - chan->scan_type.realbits)) >>
+ (16 - chan->scan_type.realbits);
+ *val = val16;
+ mutex_unlock(&indio_dev->mlock);
+ return IIO_VAL_INT;
+ case (1 << IIO_CHAN_INFO_SCALE_SEPARATE):
+ case (1 << IIO_CHAN_INFO_SCALE_SHARED):
+ switch (chan->type) {
+ case IIO_GYRO:
+ *val = 0;
+ if (spi_get_device_id(st->us)->driver_data)
+ *val2 = 320;
+ else
+ *val2 = 1278;
+ return IIO_VAL_INT_PLUS_MICRO;
+ case IIO_IN:
+ *val = 0;
+ if (chan->channel == 0)
+ *val2 = 18315;
+ else
+ *val2 = 610500;
+ return IIO_VAL_INT_PLUS_MICRO;
+ case IIO_TEMP:
+ *val = 0;
+ *val2 = 145300;
+ return IIO_VAL_INT_PLUS_MICRO;
+ default:
+ return -EINVAL;
+ }
+ break;
+ case (1 << IIO_CHAN_INFO_OFFSET_SEPARATE):
+ *val = 25;
+ return IIO_VAL_INT;
+ case (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE):
+ switch (chan->type) {
+ case IIO_GYRO:
+ bits = 12;
+ break;
+ default:
+ return -EINVAL;
+ };
+ mutex_lock(&indio_dev->mlock);
+ addr = adis16260_addresses[chan->address][1];
+ ret = adis16260_spi_read_reg_16(indio_dev, addr, &val16);
+ if (ret) {
+ mutex_unlock(&indio_dev->mlock);
+ return ret;
+ }
+ val16 &= (1 << bits) - 1;
+ val16 = (s16)(val16 << (16 - bits)) >> (16 - bits);
+ *val = val16;
+ mutex_unlock(&indio_dev->mlock);
+ return IIO_VAL_INT;
+ case (1 << IIO_CHAN_INFO_CALIBSCALE_SEPARATE):
+ switch (chan->type) {
+ case IIO_GYRO:
+ bits = 12;
+ break;
+ default:
+ return -EINVAL;
+ };
+ mutex_lock(&indio_dev->mlock);
+ addr = adis16260_addresses[chan->address][2];
+ ret = adis16260_spi_read_reg_16(indio_dev, addr, &val16);
+ if (ret) {
+ mutex_unlock(&indio_dev->mlock);
+ return ret;
+ }
+ *val = (1 << bits) - 1;
+ mutex_unlock(&indio_dev->mlock);
+ return IIO_VAL_INT;
+ }
+ return -EINVAL;
+}
+
+static int adis16260_write_raw(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ int val,
+ int val2,
+ long mask)
+{
+ int bits = 12;
+ s16 val16;
+ u8 addr;
+ switch (mask) {
+ case (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE):
+ val16 = val & ((1 << bits) - 1);
+ addr = adis16260_addresses[chan->address][1];
+ return adis16260_spi_write_reg_16(indio_dev, addr, val16);
+ case (1 << IIO_CHAN_INFO_CALIBSCALE_SEPARATE):
+ val16 = val & ((1 << bits) - 1);
+ addr = adis16260_addresses[chan->address][2];
+ return adis16260_spi_write_reg_16(indio_dev, addr, val16);
+ }
+ return -EINVAL;
+}
+
+static struct attribute *adis16260_attributes[] = {
+ &iio_dev_attr_sampling_frequency.dev_attr.attr,
+ &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
+ &iio_dev_attr_reset.dev_attr.attr,
NULL
};
-static struct attribute_group adis16260_event_attribute_group = {
- .attrs = adis16260_event_attributes,
+static const struct attribute_group adis16260_attribute_group = {
+ .attrs = adis16260_attributes,
};
-#define ADIS16260_GYRO_ATTR_SET(axis) \
- IIO_DEV_ATTR_GYRO##axis(adis16260_read_14bit_signed, \
- ADIS16260_GYRO_OUT); \
- static IIO_DEV_ATTR_GYRO##axis##_SCALE(S_IRUGO, \
- adis16260_read_gyro_scale, \
- NULL, \
- 0); \
- static IIO_DEV_ATTR_GYRO##axis##_CALIBSCALE(S_IRUGO | S_IWUSR, \
- adis16260_read_12bit_unsigned, \
- adis16260_write_16bit, \
- ADIS16260_GYRO_SCALE); \
- static IIO_DEV_ATTR_GYRO##axis##_CALIBBIAS(S_IWUSR | S_IRUGO, \
- adis16260_read_12bit_signed, \
- adis16260_write_16bit, \
- ADIS16260_GYRO_OFF); \
- static IIO_DEV_ATTR_ANGL##axis(adis16260_read_14bit_signed, \
- ADIS16260_ANGL_OUT);
-
-static ADIS16260_GYRO_ATTR_SET();
-static ADIS16260_GYRO_ATTR_SET(_X);
-static ADIS16260_GYRO_ATTR_SET(_Y);
-static ADIS16260_GYRO_ATTR_SET(_Z);
-
-#define ADIS16260_ATTR_GROUP(axis) \
- struct attribute *adis16260_attributes##axis[] = { \
- &iio_dev_attr_in0_supply_raw.dev_attr.attr, \
- &iio_const_attr_in0_supply_scale.dev_attr.attr, \
- &iio_dev_attr_gyro##axis##_raw.dev_attr.attr, \
- &iio_dev_attr_gyro##axis##_scale.dev_attr.attr, \
- &iio_dev_attr_gyro##axis##_calibscale.dev_attr.attr, \
- &iio_dev_attr_gyro##axis##_calibbias.dev_attr.attr, \
- &iio_dev_attr_angl##axis##_raw.dev_attr.attr, \
- &iio_dev_attr_temp_raw.dev_attr.attr, \
- &iio_const_attr_temp_offset.dev_attr.attr, \
- &iio_const_attr_temp_scale.dev_attr.attr, \
- &iio_dev_attr_in1_raw.dev_attr.attr, \
- &iio_const_attr_in1_scale.dev_attr.attr, \
- &iio_dev_attr_sampling_frequency.dev_attr.attr, \
- &iio_dev_attr_sampling_frequency_available.dev_attr.attr, \
- &iio_dev_attr_reset.dev_attr.attr, \
- &iio_const_attr_name.dev_attr.attr, \
- NULL \
- }; \
- static const struct attribute_group adis16260_attribute_group##axis \
- = { \
- .attrs = adis16260_attributes##axis, \
- };
-
-static ADIS16260_ATTR_GROUP();
-static ADIS16260_ATTR_GROUP(_x);
-static ADIS16260_ATTR_GROUP(_y);
-static ADIS16260_ATTR_GROUP(_z);
+static const struct iio_info adis16260_info = {
+ .attrs = &adis16260_attribute_group,
+ .read_raw = &adis16260_read_raw,
+ .write_raw = &adis16260_write_raw,
+ .driver_module = THIS_MODULE,
+};
static int __devinit adis16260_probe(struct spi_device *spi)
{
@@ -596,35 +600,35 @@
st->us = spi;
mutex_init(&st->buf_lock);
/* setup the industrialio driver allocated elements */
- st->indio_dev = iio_allocate_device();
+ st->indio_dev = iio_allocate_device(0);
if (st->indio_dev == NULL) {
ret = -ENOMEM;
goto error_free_tx;
}
+ st->indio_dev->name = spi_get_device_id(st->us)->name;
st->indio_dev->dev.parent = &spi->dev;
- st->indio_dev->num_interrupt_lines = 1;
- st->indio_dev->event_attrs = &adis16260_event_attribute_group;
+ st->indio_dev->info = &adis16260_info;
+ st->indio_dev->num_channels
+ = ARRAY_SIZE(adis16260_channels_x);
if (pd && pd->direction)
switch (pd->direction) {
case 'x':
- st->indio_dev->attrs = &adis16260_attribute_group_x;
+ st->indio_dev->channels = adis16260_channels_x;
break;
case 'y':
- st->indio_dev->attrs = &adis16260_attribute_group_y;
+ st->indio_dev->channels = adis16260_channels_y;
break;
case 'z':
- st->indio_dev->attrs = &adis16260_attribute_group_z;
+ st->indio_dev->channels = adis16260_channels_z;
break;
default:
- st->indio_dev->attrs = &adis16260_attribute_group;
- break;
+ return -EINVAL;
}
else
- st->indio_dev->attrs = &adis16260_attribute_group;
+ st->indio_dev->channels = adis16260_channels_x;
st->indio_dev->dev_data = (void *)(st);
- st->indio_dev->driver_module = THIS_MODULE;
st->indio_dev->modes = INDIO_DIRECT_MODE;
ret = adis16260_configure_ring(st->indio_dev);
@@ -635,37 +639,28 @@
if (ret)
goto error_unreg_ring_funcs;
regdone = 1;
- ret = iio_ring_buffer_register(st->indio_dev->ring, 0);
+ ret = iio_ring_buffer_register_ex(st->indio_dev->ring, 0,
+ st->indio_dev->channels,
+ ARRAY_SIZE(adis16260_channels_x));
if (ret) {
printk(KERN_ERR "failed to initialize the ring\n");
goto error_unreg_ring_funcs;
}
if (spi->irq) {
- ret = iio_register_interrupt_line(spi->irq,
- st->indio_dev,
- 0,
- IRQF_TRIGGER_RISING,
- "adis16260");
- if (ret)
- goto error_uninitialize_ring;
-
ret = adis16260_probe_trigger(st->indio_dev);
if (ret)
- goto error_unregister_line;
+ goto error_uninitialize_ring;
}
/* Get the device into a sane initial state */
- ret = adis16260_initial_setup(st);
+ ret = adis16260_initial_setup(st->indio_dev);
if (ret)
goto error_remove_trigger;
return 0;
error_remove_trigger:
adis16260_remove_trigger(st->indio_dev);
-error_unregister_line:
- if (spi->irq)
- iio_unregister_interrupt_line(st->indio_dev, 0);
error_uninitialize_ring:
iio_ring_buffer_unregister(st->indio_dev->ring);
error_unreg_ring_funcs:
@@ -691,15 +686,13 @@
struct adis16260_state *st = spi_get_drvdata(spi);
struct iio_dev *indio_dev = st->indio_dev;
- ret = adis16260_stop_device(&(indio_dev->dev));
+ ret = adis16260_stop_device(indio_dev);
if (ret)
goto err_ret;
flush_scheduled_work();
adis16260_remove_trigger(indio_dev);
- if (spi->irq)
- iio_unregister_interrupt_line(indio_dev, 0);
iio_ring_buffer_unregister(st->indio_dev->ring);
iio_device_unregister(indio_dev);
diff --git a/drivers/staging/iio/gyro/adis16260_ring.c b/drivers/staging/iio/gyro/adis16260_ring.c
index 2342889..a092504 100644
--- a/drivers/staging/iio/gyro/adis16260_ring.c
+++ b/drivers/staging/iio/gyro/adis16260_ring.c
@@ -17,57 +17,6 @@
#include "../trigger.h"
#include "adis16260.h"
-static IIO_SCAN_EL_C(in_supply, ADIS16260_SCAN_SUPPLY,
- ADIS16260_SUPPLY_OUT, NULL);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(in_supply, u, 12, 16);
-static IIO_SCAN_EL_C(gyro, ADIS16260_SCAN_GYRO, ADIS16260_GYRO_OUT, NULL);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(gyro, s, 14, 16);
-static IIO_SCAN_EL_C(in0, ADIS16260_SCAN_AUX_ADC, ADIS16260_AUX_ADC, NULL);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(in0, u, 12, 16);
-static IIO_SCAN_EL_C(temp, ADIS16260_SCAN_TEMP, ADIS16260_TEMP_OUT, NULL);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(temp, u, 12, 16);
-static IIO_SCAN_EL_C(angl, ADIS16260_SCAN_ANGL, ADIS16260_ANGL_OUT, NULL);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(angl, u, 14, 16);
-static IIO_SCAN_EL_TIMESTAMP(5);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(timestamp, s, 64, 64);
-
-static struct attribute *adis16260_scan_el_attrs[] = {
- &iio_scan_el_in_supply.dev_attr.attr,
- &iio_const_attr_in_supply_index.dev_attr.attr,
- &iio_const_attr_in_supply_type.dev_attr.attr,
- &iio_scan_el_gyro.dev_attr.attr,
- &iio_const_attr_gyro_index.dev_attr.attr,
- &iio_const_attr_gyro_type.dev_attr.attr,
- &iio_scan_el_in0.dev_attr.attr,
- &iio_const_attr_in0_index.dev_attr.attr,
- &iio_const_attr_in0_type.dev_attr.attr,
- &iio_scan_el_temp.dev_attr.attr,
- &iio_const_attr_temp_index.dev_attr.attr,
- &iio_const_attr_temp_type.dev_attr.attr,
- &iio_scan_el_angl.dev_attr.attr,
- &iio_const_attr_angl_index.dev_attr.attr,
- &iio_const_attr_angl_type.dev_attr.attr,
- &iio_scan_el_timestamp.dev_attr.attr,
- &iio_const_attr_timestamp_index.dev_attr.attr,
- &iio_const_attr_timestamp_type.dev_attr.attr,
- NULL,
-};
-
-static struct attribute_group adis16260_scan_el_group = {
- .attrs = adis16260_scan_el_attrs,
- .name = "scan_elements",
-};
-
-/**
- * adis16260_poll_func_th() top half interrupt handler called by trigger
- * @private_data: iio_dev
- **/
-static void adis16260_poll_func_th(struct iio_dev *indio_dev, s64 time)
-{
- struct adis16260_state *st = iio_dev_get_devdata(indio_dev);
- st->last_timestamp = time;
- schedule_work(&st->work_trigger_to_ring);
-}
/**
* adis16260_read_ring_data() read data registers which will be placed into ring
@@ -117,56 +66,55 @@
return ret;
}
-
-static void adis16260_trigger_bh_to_ring(struct work_struct *work_s)
+static irqreturn_t adis16260_trigger_handler(int irq, void *p)
{
- struct adis16260_state *st
- = container_of(work_s, struct adis16260_state,
- work_trigger_to_ring);
- struct iio_ring_buffer *ring = st->indio_dev->ring;
-
+ struct iio_poll_func *pf = p;
+ struct iio_dev *indio_dev = pf->private_data;
+ struct adis16260_state *st = iio_dev_get_devdata(indio_dev);
+ struct iio_ring_buffer *ring = indio_dev->ring;
int i = 0;
s16 *data;
- size_t datasize = ring->access.get_bytes_per_datum(ring);
+ size_t datasize = ring->access->get_bytes_per_datum(ring);
data = kmalloc(datasize , GFP_KERNEL);
if (data == NULL) {
dev_err(&st->us->dev, "memory alloc failed in ring bh");
- return;
+ return -ENOMEM;
}
- if (ring->scan_count)
- if (adis16260_read_ring_data(&st->indio_dev->dev, st->rx) >= 0)
- for (; i < ring->scan_count; i++)
- data[i] = be16_to_cpup(
- (__be16 *)&(st->rx[i*2]));
+ if (ring->scan_count &&
+ adis16260_read_ring_data(&st->indio_dev->dev, st->rx) >= 0)
+ for (; i < ring->scan_count; i++)
+ data[i] = be16_to_cpup((__be16 *)&(st->rx[i*2]));
/* Guaranteed to be aligned with 8 byte boundary */
if (ring->scan_timestamp)
- *((s64 *)(data + ((i + 3)/4)*4)) = st->last_timestamp;
+ *((s64 *)(data + ((i + 3)/4)*4)) = pf->timestamp;
- ring->access.store_to(ring,
- (u8 *)data,
- st->last_timestamp);
+ ring->access->store_to(ring, (u8 *)data, pf->timestamp);
iio_trigger_notify_done(st->indio_dev->trig);
kfree(data);
- return;
+ return IRQ_HANDLED;
}
void adis16260_unconfigure_ring(struct iio_dev *indio_dev)
{
- kfree(indio_dev->pollfunc);
+ iio_dealloc_pollfunc(indio_dev->pollfunc);
iio_sw_rb_free(indio_dev->ring);
}
+static const struct iio_ring_setup_ops adis16260_ring_setup_ops = {
+ .preenable = &iio_sw_ring_preenable,
+ .postenable = &iio_triggered_ring_postenable,
+ .predisable = &iio_triggered_ring_predisable,
+};
+
int adis16260_configure_ring(struct iio_dev *indio_dev)
{
int ret = 0;
- struct adis16260_state *st = indio_dev->dev_data;
struct iio_ring_buffer *ring;
- INIT_WORK(&st->work_trigger_to_ring, adis16260_trigger_bh_to_ring);
ring = iio_sw_rb_allocate(indio_dev);
if (!ring) {
@@ -175,25 +123,29 @@
}
indio_dev->ring = ring;
/* Effectively select the ring buffer implementation */
- iio_ring_sw_register_funcs(&ring->access);
+ ring->access = &ring_sw_access_funcs;
ring->bpe = 2;
- ring->scan_el_attrs = &adis16260_scan_el_group;
ring->scan_timestamp = true;
- ring->preenable = &iio_sw_ring_preenable;
- ring->postenable = &iio_triggered_ring_postenable;
- ring->predisable = &iio_triggered_ring_predisable;
+ ring->setup_ops = &adis16260_ring_setup_ops;
ring->owner = THIS_MODULE;
/* Set default scan mode */
- iio_scan_mask_set(ring, iio_scan_el_in_supply.number);
- iio_scan_mask_set(ring, iio_scan_el_gyro.number);
- iio_scan_mask_set(ring, iio_scan_el_in0.number);
- iio_scan_mask_set(ring, iio_scan_el_temp.number);
- iio_scan_mask_set(ring, iio_scan_el_angl.number);
+ iio_scan_mask_set(ring, ADIS16260_SCAN_SUPPLY);
+ iio_scan_mask_set(ring, ADIS16260_SCAN_GYRO);
+ iio_scan_mask_set(ring, ADIS16260_SCAN_AUX_ADC);
+ iio_scan_mask_set(ring, ADIS16260_SCAN_TEMP);
+ iio_scan_mask_set(ring, ADIS16260_SCAN_ANGL);
- ret = iio_alloc_pollfunc(indio_dev, NULL, &adis16260_poll_func_th);
- if (ret)
+ indio_dev->pollfunc = iio_alloc_pollfunc(&iio_pollfunc_store_time,
+ &adis16260_trigger_handler,
+ IRQF_ONESHOT,
+ indio_dev,
+ "adis16260_consumer%d",
+ indio_dev->id);
+ if (indio_dev->pollfunc == NULL) {
+ ret = -ENOMEM;
goto error_iio_sw_rb_free;
+ }
indio_dev->modes |= INDIO_RING_TRIGGERED;
return 0;
diff --git a/drivers/staging/iio/gyro/adis16260_trigger.c b/drivers/staging/iio/gyro/adis16260_trigger.c
index 4a744c1..4f10fb5 100644
--- a/drivers/staging/iio/gyro/adis16260_trigger.c
+++ b/drivers/staging/iio/gyro/adis16260_trigger.c
@@ -13,35 +13,6 @@
#include "adis16260.h"
/**
- * adis16260_data_rdy_trig_poll() the event handler for the data rdy trig
- **/
-static int adis16260_data_rdy_trig_poll(struct iio_dev *dev_info,
- int index,
- s64 timestamp,
- int no_test)
-{
- struct adis16260_state *st = iio_dev_get_devdata(dev_info);
- struct iio_trigger *trig = st->trig;
-
- iio_trigger_poll(trig, timestamp);
-
- return IRQ_HANDLED;
-}
-
-IIO_EVENT_SH(data_rdy_trig, &adis16260_data_rdy_trig_poll);
-
-static IIO_TRIGGER_NAME_ATTR;
-
-static struct attribute *adis16260_trigger_attrs[] = {
- &dev_attr_name.attr,
- NULL,
-};
-
-static const struct attribute_group adis16260_trigger_attr_group = {
- .attrs = adis16260_trigger_attrs,
-};
-
-/**
* adis16260_data_rdy_trigger_set_state() set datardy interrupt state
**/
static int adis16260_data_rdy_trigger_set_state(struct iio_trigger *trig,
@@ -49,31 +20,9 @@
{
struct adis16260_state *st = trig->private_data;
struct iio_dev *indio_dev = st->indio_dev;
- int ret = 0;
dev_dbg(&indio_dev->dev, "%s (%d)\n", __func__, state);
- ret = adis16260_set_irq(&st->indio_dev->dev, state);
- if (state == false) {
- iio_remove_event_from_list(&iio_event_data_rdy_trig,
- &indio_dev->interrupts[0]
- ->ev_list);
- flush_scheduled_work();
- } else {
- iio_add_event_to_list(&iio_event_data_rdy_trig,
- &indio_dev->interrupts[0]->ev_list);
- }
- return ret;
-}
-
-/**
- * adis16260_trig_try_reen() try renabling irq for data rdy trigger
- * @trig: the datardy trigger
- **/
-static int adis16260_trig_try_reen(struct iio_trigger *trig)
-{
- struct adis16260_state *st = trig->private_data;
- enable_irq(st->us->irq);
- return 0;
+ return adis16260_set_irq(indio_dev, state);
}
int adis16260_probe_trigger(struct iio_dev *indio_dev)
@@ -81,34 +30,40 @@
int ret;
struct adis16260_state *st = indio_dev->dev_data;
- st->trig = iio_allocate_trigger();
- st->trig->name = kasprintf(GFP_KERNEL,
- "adis16260-dev%d",
- indio_dev->id);
- if (!st->trig->name) {
+ st->trig = iio_allocate_trigger("%s-dev%d",
+ spi_get_device_id(st->us)->name,
+ indio_dev->id);
+ if (st->trig == NULL) {
ret = -ENOMEM;
- goto error_free_trig;
+ goto error_ret;
}
+
+ ret = request_irq(st->us->irq,
+ &iio_trigger_generic_data_rdy_poll,
+ IRQF_TRIGGER_RISING,
+ "adis16260",
+ st->trig);
+ if (ret)
+ goto error_free_trig;
+
st->trig->dev.parent = &st->us->dev;
st->trig->owner = THIS_MODULE;
st->trig->private_data = st;
st->trig->set_trigger_state = &adis16260_data_rdy_trigger_set_state;
- st->trig->try_reenable = &adis16260_trig_try_reen;
- st->trig->control_attrs = &adis16260_trigger_attr_group;
ret = iio_trigger_register(st->trig);
/* select default trigger */
indio_dev->trig = st->trig;
if (ret)
- goto error_free_trig_name;
+ goto error_free_irq;
return 0;
-error_free_trig_name:
- kfree(st->trig->name);
+error_free_irq:
+ free_irq(st->us->irq, st->trig);
error_free_trig:
iio_free_trigger(st->trig);
-
+error_ret:
return ret;
}
@@ -117,6 +72,6 @@
struct adis16260_state *state = indio_dev->dev_data;
iio_trigger_unregister(state->trig);
- kfree(state->trig->name);
+ free_irq(state->us->irq, state->trig);
iio_free_trigger(state->trig);
}
diff --git a/drivers/staging/iio/gyro/adxrs450.h b/drivers/staging/iio/gyro/adxrs450.h
new file mode 100644
index 0000000..c92f694
--- /dev/null
+++ b/drivers/staging/iio/gyro/adxrs450.h
@@ -0,0 +1,58 @@
+#ifndef SPI_ADXRS450_H_
+#define SPI_ADXRS450_H_
+
+#define ADXRS450_STARTUP_DELAY 50 /* ms */
+
+/* The MSB for the spi commands */
+#define ADXRS450_SENSOR_DATA 0x20
+#define ADXRS450_WRITE_DATA 0x40
+#define ADXRS450_READ_DATA 0x80
+
+#define ADXRS450_RATE1 0x00 /* Rate Registers */
+#define ADXRS450_TEMP1 0x02 /* Temperature Registers */
+#define ADXRS450_LOCST1 0x04 /* Low CST Memory Registers */
+#define ADXRS450_HICST1 0x06 /* High CST Memory Registers */
+#define ADXRS450_QUAD1 0x08 /* Quad Memory Registers */
+#define ADXRS450_FAULT1 0x0A /* Fault Registers */
+#define ADXRS450_PID1 0x0C /* Part ID Register 1 */
+#define ADXRS450_SNH 0x0E /* Serial Number Registers, 4 bytes */
+#define ADXRS450_SNL 0x10
+#define ADXRS450_DNC1 0x12 /* Dynamic Null Correction Registers */
+/* Check bits */
+#define ADXRS450_P 0x01
+#define ADXRS450_CHK 0x02
+#define ADXRS450_CST 0x04
+#define ADXRS450_PWR 0x08
+#define ADXRS450_POR 0x10
+#define ADXRS450_NVM 0x20
+#define ADXRS450_Q 0x40
+#define ADXRS450_PLL 0x80
+#define ADXRS450_UV 0x100
+#define ADXRS450_OV 0x200
+#define ADXRS450_AMP 0x400
+#define ADXRS450_FAIL 0x800
+
+#define ADXRS450_WRERR_MASK (0x7 << 29)
+
+#define ADXRS450_MAX_RX 4
+#define ADXRS450_MAX_TX 4
+
+#define ADXRS450_GET_ST(a) ((a >> 26) & 0x3)
+
+/**
+ * struct adxrs450_state - device instance specific data
+ * @us: actual spi_device
+ * @indio_dev: industrial I/O device structure
+ * @tx: transmit buffer
+ * @rx: recieve buffer
+ * @buf_lock: mutex to protect tx and rx
+ **/
+struct adxrs450_state {
+ struct spi_device *us;
+ struct iio_dev *indio_dev;
+ u8 *tx;
+ u8 *rx;
+ struct mutex buf_lock;
+};
+
+#endif /* SPI_ADXRS450_H_ */
diff --git a/drivers/staging/iio/gyro/adxrs450_core.c b/drivers/staging/iio/gyro/adxrs450_core.c
new file mode 100644
index 0000000..3714e4a
--- /dev/null
+++ b/drivers/staging/iio/gyro/adxrs450_core.c
@@ -0,0 +1,455 @@
+/*
+ * ADXRS450 Digital Output Gyroscope Driver
+ *
+ * Copyright 2011 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2.
+ */
+
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/gpio.h>
+#include <linux/delay.h>
+#include <linux/mutex.h>
+#include <linux/device.h>
+#include <linux/kernel.h>
+#include <linux/spi/spi.h>
+#include <linux/slab.h>
+#include <linux/sysfs.h>
+#include <linux/list.h>
+
+#include "../iio.h"
+#include "../sysfs.h"
+#include "gyro.h"
+#include "../adc/adc.h"
+
+#include "adxrs450.h"
+
+/**
+ * adxrs450_spi_read_reg_16() - read 2 bytes from a register pair
+ * @dev: device associated with child of actual iio_dev
+ * @reg_address: the address of the lower of the two registers,which should be an even address,
+ * Second register's address is reg_address + 1.
+ * @val: somewhere to pass back the value read
+ **/
+static int adxrs450_spi_read_reg_16(struct device *dev,
+ u8 reg_address,
+ u16 *val)
+{
+ struct spi_message msg;
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ struct adxrs450_state *st = iio_dev_get_devdata(indio_dev);
+ int ret;
+ struct spi_transfer xfers[] = {
+ {
+ .tx_buf = st->tx,
+ .bits_per_word = 8,
+ .len = 4,
+ .cs_change = 1,
+ }, {
+ .rx_buf = st->rx,
+ .bits_per_word = 8,
+ .len = 4,
+ },
+ };
+
+ mutex_lock(&st->buf_lock);
+ st->tx[0] = ADXRS450_READ_DATA | (reg_address >> 7);
+ st->tx[1] = reg_address << 1;
+ st->tx[2] = 0;
+ st->tx[3] = 0;
+
+ if (!(hweight32(be32_to_cpu(*(u32 *)st->tx)) & 1))
+ st->tx[3] |= ADXRS450_P;
+
+ spi_message_init(&msg);
+ spi_message_add_tail(&xfers[0], &msg);
+ spi_message_add_tail(&xfers[1], &msg);
+ ret = spi_sync(st->us, &msg);
+ if (ret) {
+ dev_err(&st->us->dev, "problem while reading 16 bit register 0x%02x\n",
+ reg_address);
+ goto error_ret;
+ }
+
+ *val = (be32_to_cpu(*(u32 *)st->rx) >> 5) & 0xFFFF;
+
+error_ret:
+ mutex_unlock(&st->buf_lock);
+ return ret;
+}
+
+/**
+ * adxrs450_spi_write_reg_16() - write 2 bytes data to a register pair
+ * @dev: device associated with child of actual actual iio_dev
+ * @reg_address: the address of the lower of the two registers,which should be an even address,
+ * Second register's address is reg_address + 1.
+ * @val: value to be written.
+ **/
+static int adxrs450_spi_write_reg_16(struct device *dev,
+ u8 reg_address,
+ u16 val)
+{
+ struct spi_message msg;
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ struct adxrs450_state *st = iio_dev_get_devdata(indio_dev);
+ int ret;
+ struct spi_transfer xfers = {
+ .tx_buf = st->tx,
+ .rx_buf = st->rx,
+ .bits_per_word = 8,
+ .len = 4,
+ };
+
+ mutex_lock(&st->buf_lock);
+ st->tx[0] = ADXRS450_WRITE_DATA | reg_address >> 7;
+ st->tx[1] = reg_address << 1 | val >> 15;
+ st->tx[2] = val >> 7;
+ st->tx[3] = val << 1;
+
+ if (!(hweight32(be32_to_cpu(*(u32 *)st->tx)) & 1))
+ st->tx[3] |= ADXRS450_P;
+
+ spi_message_init(&msg);
+ spi_message_add_tail(&xfers, &msg);
+ ret = spi_sync(st->us, &msg);
+ if (ret)
+ dev_err(&st->us->dev, "problem while writing 16 bit register 0x%02x\n",
+ reg_address);
+ msleep(1); /* enforce sequential transfer delay 0.1ms */
+ mutex_unlock(&st->buf_lock);
+ return ret;
+}
+
+/**
+ * adxrs450_spi_sensor_data() - read 2 bytes sensor data
+ * @dev: device associated with child of actual iio_dev
+ * @val: somewhere to pass back the value read
+ **/
+static int adxrs450_spi_sensor_data(struct device *dev, s16 *val)
+{
+ struct spi_message msg;
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ struct adxrs450_state *st = iio_dev_get_devdata(indio_dev);
+ int ret;
+ struct spi_transfer xfers[] = {
+ {
+ .tx_buf = st->tx,
+ .bits_per_word = 8,
+ .len = 4,
+ .cs_change = 1,
+ }, {
+ .rx_buf = st->rx,
+ .bits_per_word = 8,
+ .len = 4,
+ },
+ };
+
+ mutex_lock(&st->buf_lock);
+ st->tx[0] = ADXRS450_SENSOR_DATA;
+ st->tx[1] = 0;
+ st->tx[2] = 0;
+ st->tx[3] = 0;
+
+ spi_message_init(&msg);
+ spi_message_add_tail(&xfers[0], &msg);
+ spi_message_add_tail(&xfers[1], &msg);
+ ret = spi_sync(st->us, &msg);
+ if (ret) {
+ dev_err(&st->us->dev, "Problem while reading sensor data\n");
+ goto error_ret;
+ }
+
+ *val = (be32_to_cpu(*(u32 *)st->rx) >> 10) & 0xFFFF;
+
+error_ret:
+ mutex_unlock(&st->buf_lock);
+ return ret;
+}
+
+/**
+ * adxrs450_spi_initial() - use for initializing procedure.
+ * @st: device instance specific data
+ * @val: somewhere to pass back the value read
+ **/
+static int adxrs450_spi_initial(struct adxrs450_state *st,
+ u32 *val, char chk)
+{
+ struct spi_message msg;
+ int ret;
+ struct spi_transfer xfers = {
+ .tx_buf = st->tx,
+ .rx_buf = st->rx,
+ .bits_per_word = 8,
+ .len = 4,
+ };
+
+ mutex_lock(&st->buf_lock);
+ st->tx[0] = ADXRS450_SENSOR_DATA;
+ st->tx[1] = 0;
+ st->tx[2] = 0;
+ st->tx[3] = 0;
+ if (chk)
+ st->tx[3] |= (ADXRS450_CHK | ADXRS450_P);
+ spi_message_init(&msg);
+ spi_message_add_tail(&xfers, &msg);
+ ret = spi_sync(st->us, &msg);
+ if (ret) {
+ dev_err(&st->us->dev, "Problem while reading initializing data\n");
+ goto error_ret;
+ }
+
+ *val = be32_to_cpu(*(u32 *)st->rx);
+
+error_ret:
+ mutex_unlock(&st->buf_lock);
+ return ret;
+}
+
+static ssize_t adxrs450_read_temp(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ int ret;
+ u16 t;
+ ret = adxrs450_spi_read_reg_16(dev,
+ ADXRS450_TEMP1,
+ &t);
+ if (ret)
+ return ret;
+ return sprintf(buf, "%d\n", t >> 7);
+}
+
+static ssize_t adxrs450_read_quad(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ int ret;
+ s16 t;
+ ret = adxrs450_spi_read_reg_16(dev,
+ ADXRS450_QUAD1,
+ &t);
+ if (ret)
+ return ret;
+ return sprintf(buf, "%d\n", t);
+}
+
+static ssize_t adxrs450_write_dnc(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf,
+ size_t len)
+{
+ int ret;
+ long val;
+
+ ret = strict_strtol(buf, 10, &val);
+ if (ret)
+ goto error_ret;
+ ret = adxrs450_spi_write_reg_16(dev,
+ ADXRS450_DNC1,
+ val & 0x3FF);
+error_ret:
+ return ret ? ret : len;
+}
+
+static ssize_t adxrs450_read_sensor_data(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ int ret;
+ s16 t;
+
+ ret = adxrs450_spi_sensor_data(dev, &t);
+ if (ret)
+ return ret;
+
+ return sprintf(buf, "%d\n", t);
+}
+
+/* Recommended Startup Sequence by spec */
+static int adxrs450_initial_setup(struct adxrs450_state *st)
+{
+ u32 t;
+ u16 data;
+ int ret;
+ struct device *dev = &st->indio_dev->dev;
+
+ msleep(ADXRS450_STARTUP_DELAY*2);
+ ret = adxrs450_spi_initial(st, &t, 1);
+ if (ret)
+ return ret;
+ if (t != 0x01)
+ dev_warn(&st->us->dev, "The initial power on response "
+ "is not correct! Restart without reset?\n");
+
+ msleep(ADXRS450_STARTUP_DELAY);
+ ret = adxrs450_spi_initial(st, &t, 0);
+ if (ret)
+ return ret;
+
+ msleep(ADXRS450_STARTUP_DELAY);
+ ret = adxrs450_spi_initial(st, &t, 0);
+ if (ret)
+ return ret;
+ if (((t & 0xff) | 0x01) != 0xff || ADXRS450_GET_ST(t) != 2) {
+ dev_err(&st->us->dev, "The second response is not correct!\n");
+ return -EIO;
+
+ }
+ ret = adxrs450_spi_initial(st, &t, 0);
+ if (ret)
+ return ret;
+ if (((t & 0xff) | 0x01) != 0xff || ADXRS450_GET_ST(t) != 2) {
+ dev_err(&st->us->dev, "The third response is not correct!\n");
+ return -EIO;
+
+ }
+ ret = adxrs450_spi_read_reg_16(dev, ADXRS450_FAULT1, &data);
+ if (ret)
+ return ret;
+ if (data & 0x0fff) {
+ dev_err(&st->us->dev, "The device is not in normal status!\n");
+ return -EINVAL;
+ }
+ ret = adxrs450_spi_read_reg_16(dev, ADXRS450_PID1, &data);
+ if (ret)
+ return ret;
+ dev_info(&st->us->dev, "The Part ID is 0x%x\n", data);
+
+ ret = adxrs450_spi_read_reg_16(dev, ADXRS450_SNL, &data);
+ if (ret)
+ return ret;
+ t = data;
+ ret = adxrs450_spi_read_reg_16(dev, ADXRS450_SNH, &data);
+ if (ret)
+ return ret;
+ t |= data << 16;
+ dev_info(&st->us->dev, "The Serial Number is 0x%x\n", t);
+
+ return 0;
+}
+
+static IIO_DEV_ATTR_GYRO_Z(adxrs450_read_sensor_data, 0);
+static IIO_DEV_ATTR_TEMP_RAW(adxrs450_read_temp);
+static IIO_DEV_ATTR_GYRO_Z_QUADRATURE_CORRECTION(adxrs450_read_quad, 0);
+static IIO_DEV_ATTR_GYRO_Z_CALIBBIAS(S_IWUSR,
+ NULL, adxrs450_write_dnc, 0);
+static IIO_CONST_ATTR(name, "adxrs450");
+
+static struct attribute *adxrs450_attributes[] = {
+ &iio_dev_attr_gyro_z_raw.dev_attr.attr,
+ &iio_dev_attr_temp_raw.dev_attr.attr,
+ &iio_dev_attr_gyro_z_quadrature_correction_raw.dev_attr.attr,
+ &iio_dev_attr_gyro_z_calibbias.dev_attr.attr,
+ &iio_const_attr_name.dev_attr.attr,
+ NULL
+};
+
+static const struct attribute_group adxrs450_attribute_group = {
+ .attrs = adxrs450_attributes,
+};
+
+static const struct iio_info adxrs450_info = {
+ .attrs = &adxrs450_attribute_group,
+ .driver_module = THIS_MODULE,
+};
+
+static int __devinit adxrs450_probe(struct spi_device *spi)
+{
+ int ret, regdone = 0;
+ struct adxrs450_state *st = kzalloc(sizeof *st, GFP_KERNEL);
+ if (!st) {
+ ret = -ENOMEM;
+ goto error_ret;
+ }
+ /* This is only used for removal purposes */
+ spi_set_drvdata(spi, st);
+
+ /* Allocate the comms buffers */
+ st->rx = kzalloc(sizeof(*st->rx)*ADXRS450_MAX_RX, GFP_KERNEL);
+ if (st->rx == NULL) {
+ ret = -ENOMEM;
+ goto error_free_st;
+ }
+ st->tx = kzalloc(sizeof(*st->tx)*ADXRS450_MAX_TX, GFP_KERNEL);
+ if (st->tx == NULL) {
+ ret = -ENOMEM;
+ goto error_free_rx;
+ }
+ st->us = spi;
+ mutex_init(&st->buf_lock);
+ /* setup the industrialio driver allocated elements */
+ st->indio_dev = iio_allocate_device(0);
+ if (st->indio_dev == NULL) {
+ ret = -ENOMEM;
+ goto error_free_tx;
+ }
+
+ st->indio_dev->dev.parent = &spi->dev;
+ st->indio_dev->info = &adxrs450_info;
+ st->indio_dev->dev_data = (void *)(st);
+ st->indio_dev->modes = INDIO_DIRECT_MODE;
+
+ ret = iio_device_register(st->indio_dev);
+ if (ret)
+ goto error_free_dev;
+ regdone = 1;
+
+ /* Get the device into a sane initial state */
+ ret = adxrs450_initial_setup(st);
+ if (ret)
+ goto error_initial;
+ return 0;
+
+error_initial:
+error_free_dev:
+ if (regdone)
+ iio_device_unregister(st->indio_dev);
+ else
+ iio_free_device(st->indio_dev);
+error_free_tx:
+ kfree(st->tx);
+error_free_rx:
+ kfree(st->rx);
+error_free_st:
+ kfree(st);
+error_ret:
+ return ret;
+}
+
+static int adxrs450_remove(struct spi_device *spi)
+{
+ struct adxrs450_state *st = spi_get_drvdata(spi);
+
+ iio_device_unregister(st->indio_dev);
+ kfree(st->tx);
+ kfree(st->rx);
+ kfree(st);
+
+ return 0;
+}
+
+static struct spi_driver adxrs450_driver = {
+ .driver = {
+ .name = "adxrs450",
+ .owner = THIS_MODULE,
+ },
+ .probe = adxrs450_probe,
+ .remove = __devexit_p(adxrs450_remove),
+};
+
+static __init int adxrs450_init(void)
+{
+ return spi_register_driver(&adxrs450_driver);
+}
+module_init(adxrs450_init);
+
+static __exit void adxrs450_exit(void)
+{
+ spi_unregister_driver(&adxrs450_driver);
+}
+module_exit(adxrs450_exit);
+
+MODULE_AUTHOR("Cliff Cai <cliff.cai@xxxxxxxxxx>");
+MODULE_DESCRIPTION("Analog Devices ADXRS450 Gyroscope SPI driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/staging/iio/gyro/gyro.h b/drivers/staging/iio/gyro/gyro.h
index b4ea5bf..b5495613 100644
--- a/drivers/staging/iio/gyro/gyro.h
+++ b/drivers/staging/iio/gyro/gyro.h
@@ -57,6 +57,9 @@
#define IIO_DEV_ATTR_GYRO_Z_CALIBSCALE(_mode, _show, _store, _addr) \
IIO_DEVICE_ATTR(gyro_z_calibscale, _mode, _show, _store, _addr)
+#define IIO_DEV_ATTR_GYRO_Z_QUADRATURE_CORRECTION(_show, _addr) \
+ IIO_DEVICE_ATTR(gyro_z_quadrature_correction_raw, S_IRUGO, _show, NULL, _addr)
+
#define IIO_DEV_ATTR_GYRO(_show, _addr) \
IIO_DEVICE_ATTR(gyro_raw, S_IRUGO, _show, NULL, _addr)
diff --git a/drivers/staging/iio/iio.h b/drivers/staging/iio/iio.h
index 7127f26..38f1425 100644
--- a/drivers/staging/iio/iio.h
+++ b/drivers/staging/iio/iio.h
@@ -12,6 +12,7 @@
#include <linux/device.h>
#include <linux/cdev.h>
+#include <linux/irq.h>
#include "sysfs.h"
#include "chrdev.h"
@@ -24,8 +25,157 @@
/* Event interface flags */
#define IIO_BUSY_BIT_POS 1
-struct iio_dev;
+/* naughty temporary hack to match these against the event version
+ - need to flattern these together */
+enum iio_chan_type {
+ /* real channel types */
+ IIO_IN,
+ IIO_CURRENT,
+ IIO_POWER,
+ IIO_ACCEL,
+ IIO_IN_DIFF,
+ IIO_GYRO,
+ IIO_MAGN,
+ IIO_LIGHT,
+ IIO_INTENSITY,
+ IIO_PROXIMITY,
+ IIO_TEMP,
+ IIO_INCLI,
+ IIO_ROT,
+ IIO_ANGL,
+ IIO_TIMESTAMP,
+};
+#define IIO_MOD_X 0
+#define IIO_MOD_LIGHT_BOTH 0
+#define IIO_MOD_Y 1
+#define IIO_MOD_LIGHT_IR 1
+#define IIO_MOD_Z 2
+#define IIO_MOD_X_AND_Y 3
+#define IIO_MOD_X_ANX_Z 4
+#define IIO_MOD_Y_AND_Z 5
+#define IIO_MOD_X_AND_Y_AND_Z 6
+#define IIO_MOD_X_OR_Y 7
+#define IIO_MOD_X_OR_Z 8
+#define IIO_MOD_Y_OR_Z 9
+#define IIO_MOD_X_OR_Y_OR_Z 10
+
+/* Could add the raw attributes as well - allowing buffer only devices */
+enum iio_chan_info_enum {
+ IIO_CHAN_INFO_SCALE_SHARED,
+ IIO_CHAN_INFO_SCALE_SEPARATE,
+ IIO_CHAN_INFO_OFFSET_SHARED,
+ IIO_CHAN_INFO_OFFSET_SEPARATE,
+ IIO_CHAN_INFO_CALIBSCALE_SHARED,
+ IIO_CHAN_INFO_CALIBSCALE_SEPARATE,
+ IIO_CHAN_INFO_CALIBBIAS_SHARED,
+ IIO_CHAN_INFO_CALIBBIAS_SEPARATE,
+ IIO_CHAN_INFO_PEAK_SHARED,
+ IIO_CHAN_INFO_PEAK_SEPARATE,
+ IIO_CHAN_INFO_PEAK_SCALE_SHARED,
+ IIO_CHAN_INFO_PEAK_SCALE_SEPARATE,
+};
+
+/**
+ * struct iio_chan_spec - specification of a single channel
+ * @type: What type of measurement is the channel making.
+ * @channel: What number or name do we wish to asign the channel.
+ * @channel2: If there is a second number for a differential
+ * channel then this is it. If modified is set then the
+ * value here specifies the modifier.
+ * @address: Driver specific identifier.
+ * @scan_index: Monotonic index to give ordering in scans when read
+ * from a buffer.
+ * @scan_type: Sign: 's' or 'u' to specify signed or unsigned
+ * realbits: Number of valid bits of data
+ * storage_bits: Realbits + padding
+ * shift: Shift right by this before masking out
+ * realbits.
+ * @info_mask: What information is to be exported about this channel.
+ * This includes calibbias, scale etc.
+ * @event_mask: What events can this channel produce.
+ * @extend_name: Allows labeling of channel attributes with an
+ * informative name. Note this has no effect codes etc,
+ * unlike modifiers.
+ * @processed_val: Flag to specify the data access attribute should be
+ * *_input rather than *_raw.
+ * @modified: Does a modifier apply to this channel. What these are
+ * depends on the channel type. Modifier is set in
+ * channel2. Examples are IIO_MOD_X for axial sensors about
+ * the 'x' axis.
+ * @indexed: Specify the channel has a numerical index. If not,
+ * the value in channel will be suppressed for attribute
+ * but not for event codes. Typically set it to 0 when
+ * the index is false.
+ */
+struct iio_chan_spec {
+ enum iio_chan_type type;
+ int channel;
+ int channel2;
+ unsigned long address;
+ int scan_index;
+ struct {
+ char sign;
+ u8 realbits;
+ u8 storagebits;
+ u8 shift;
+ } scan_type;
+ const long info_mask;
+ const long event_mask;
+ const char *extend_name;
+ unsigned processed_val:1;
+ unsigned modified:1;
+ unsigned indexed:1;
+};
+/* Meant for internal use only */
+void __iio_device_attr_deinit(struct device_attribute *dev_attr);
+int __iio_device_attr_init(struct device_attribute *dev_attr,
+ const char *postfix,
+ struct iio_chan_spec const *chan,
+ ssize_t (*readfunc)(struct device *dev,
+ struct device_attribute *attr,
+ char *buf),
+ ssize_t (*writefunc)(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf,
+ size_t len),
+ bool generic);
+#define IIO_ST(si, rb, sb, sh) \
+ { .sign = si, .realbits = rb, .storagebits = sb, .shift = sh }
+
+#define IIO_CHAN(_type, _mod, _indexed, _proc, _name, _chan, _chan2, \
+ _inf_mask, _address, _si, _stype, _event_mask) \
+ { .type = _type, \
+ .modified = _mod, \
+ .indexed = _indexed, \
+ .processed_val = _proc, \
+ .extend_name = _name, \
+ .channel = _chan, \
+ .channel2 = _chan2, \
+ .info_mask = _inf_mask, \
+ .address = _address, \
+ .scan_index = _si, \
+ .scan_type = _stype, \
+ .event_mask = _event_mask }
+
+#define IIO_CHAN_SOFT_TIMESTAMP(_si) \
+ { .type = IIO_TIMESTAMP, .channel = -1, \
+ .scan_index = _si, .scan_type = IIO_ST('s', 64, 64, 0) }
+
+int __iio_add_chan_devattr(const char *postfix,
+ const char *group,
+ struct iio_chan_spec const *chan,
+ ssize_t (*func)(struct device *dev,
+ struct device_attribute *attr,
+ char *buf),
+ ssize_t (*writefunc)(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf,
+ size_t len),
+ int mask,
+ bool generic,
+ struct device *dev,
+ struct list_head *attr_list);
/**
* iio_get_time_ns() - utility function to get a time stamp for events etc
**/
@@ -41,26 +191,6 @@
return timespec_to_ns(&ts);
}
-/**
- * iio_add_event_to_list() - Wraps adding to event lists
- * @el: the list element of the event to be handled.
- * @head: the list associated with the event handler being used.
- *
- * Does reference counting to allow shared handlers.
- **/
-void iio_add_event_to_list(struct iio_event_handler_list *el,
- struct list_head *head);
-
-/**
- * iio_remove_event_from_list() - Wraps removing from event list
- * @el: element to be removed
- * @head: associate list head for the interrupt handler.
- *
- * Does reference counting to allow shared handlers.
- **/
-void iio_remove_event_from_list(struct iio_event_handler_list *el,
- struct list_head *head);
-
/* Device operating modes */
#define INDIO_DIRECT_MODE 0x01
#define INDIO_RING_TRIGGERED 0x02
@@ -70,6 +200,62 @@
/* Vast majority of this is set by the industrialio subsystem on a
* call to iio_device_register. */
+#define IIO_VAL_INT 1
+#define IIO_VAL_INT_PLUS_MICRO 2
+
+/**
+ * struct iio_info - constant information about device
+ * @driver_module: module structure used to ensure correct
+ * ownership of chrdevs etc
+ * @num_interrupt_lines:number of physical interrupt lines from device
+ * @event_attrs: event control attributes
+ * @attrs: general purpose device attributes
+ * @read_raw: function to request a value from the device.
+ * mask specifies which value. Note 0 means a reading of
+ * the channel in question. Return value will specify the
+ * type of value returned by the device. val and val2 will
+ * contain the elements making up the returned value.
+ * @write_raw: function to write a value to the device.
+ * Parameters are the same as for read_raw.
+ * @read_event_config: find out if the event is enabled.
+ * @write_event_config: set if the event is enabled.
+ * @read_event_value: read a value associated with the event. Meaning
+ * is event dependant. event_code specifies which event.
+ * @write_event_value: write the value associate with the event.
+ * Meaning is event dependent.
+ **/
+struct iio_info {
+ struct module *driver_module;
+ int num_interrupt_lines;
+ struct attribute_group *event_attrs;
+ const struct attribute_group *attrs;
+
+ int (*read_raw)(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ int *val,
+ int *val2,
+ long mask);
+
+ int (*write_raw)(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ int val,
+ int val2,
+ long mask);
+
+ int (*read_event_config)(struct iio_dev *indio_dev,
+ int event_code);
+
+ int (*write_event_config)(struct iio_dev *indio_dev,
+ int event_code,
+ int state);
+
+ int (*read_event_value)(struct iio_dev *indio_dev,
+ int event_code,
+ int *val);
+ int (*write_event_value)(struct iio_dev *indio_dev,
+ int event_code,
+ int val);
+};
/**
* struct iio_dev - industrial I/O device
@@ -79,13 +265,6 @@
* @currentmode: [DRIVER] current operating mode
* @dev: [DRIVER] device structure, should be assigned a parent
* and owner
- * @attrs: [DRIVER] general purpose device attributes
- * @driver_module: [DRIVER] module structure used to ensure correct
- * ownership of chrdevs etc
- * @num_interrupt_lines:[DRIVER] number of physical interrupt lines from device
- * @interrupts: [INTERN] interrupt line specific event lists etc
- * @event_attrs: [DRIVER] event control attributes
- * @event_conf_attrs: [DRIVER] event configuration attributes
* @event_interfaces: [INTERN] event chrdevs associated with interrupt lines
* @ring: [DRIVER] any ring buffer present
* @mlock: [INTERN] lock used to prevent simultaneous device state
@@ -93,6 +272,11 @@
* @available_scan_masks: [DRIVER] optional array of allowed bitmasks
* @trig: [INTERN] current device trigger (ring buffer modes)
* @pollfunc: [DRIVER] function run on trigger being received
+ * @channels: [DRIVER] channel specification structure table
+ * @num_channels: [DRIVER] number of chanels specified in @channels.
+ * @channel_attr_list: [INTERN] keep track of automatically created channel
+ * attributes.
+ * @name: [DRIVER] name of the device.
**/
struct iio_dev {
int id;
@@ -100,13 +284,6 @@
int modes;
int currentmode;
struct device dev;
- const struct attribute_group *attrs;
- struct module *driver_module;
-
- int num_interrupt_lines;
- struct iio_interrupt **interrupts;
- struct attribute_group *event_attrs;
- struct attribute_group *event_conf_attrs;
struct iio_event_interface *event_interfaces;
@@ -116,6 +293,13 @@
u32 *available_scan_masks;
struct iio_trigger *trig;
struct iio_poll_func *pollfunc;
+
+ struct iio_chan_spec const *channels;
+ int num_channels;
+
+ struct list_head channel_attr_list;
+ const char *name;
+ const struct iio_info *info;
};
/**
@@ -131,47 +315,6 @@
void iio_device_unregister(struct iio_dev *dev_info);
/**
- * struct iio_interrupt - wrapper used to allow easy handling of multiple
- * physical interrupt lines
- * @dev_info: the iio device for which the is an interrupt line
- * @line_number: associated line number
- * @id: ida allocated unique id number
- * @irq: associate interrupt number
- * @ev_list: event handler list for associated events
- * @ev_list_lock: ensure only one access to list at a time
- **/
-struct iio_interrupt {
- struct iio_dev *dev_info;
- int line_number;
- int id;
- int irq;
- struct list_head ev_list;
- spinlock_t ev_list_lock;
-};
-
-#define to_iio_interrupt(i) container_of(i, struct iio_interrupt, ev_list)
-
-/**
- * iio_register_interrupt_line() - Tell IIO about interrupt lines
- *
- * @irq: Typically provided via platform data
- * @dev_info: IIO device info structure for device
- * @line_number: Which interrupt line of the device is this?
- * @type: Interrupt type (e.g. edge triggered etc)
- * @name: Identifying name.
- **/
-int iio_register_interrupt_line(unsigned int irq,
- struct iio_dev *dev_info,
- int line_number,
- unsigned long type,
- const char *name);
-
-void iio_unregister_interrupt_line(struct iio_dev *dev_info,
- int line_number);
-
-
-
-/**
* iio_push_event() - try to add event to the list for userspace reading
* @dev_info: IIO device structure
* @ev_line: Which event line (hardware interrupt)
@@ -183,50 +326,6 @@
int ev_code,
s64 timestamp);
-/**
- * __iio_push_event() - tries to add an event to the list associated with a chrdev
- * @ev_int: the event interface to which we are pushing the event
- * @ev_code: the outgoing event code
- * @timestamp: timestamp of the event
- * @shared_pointer_p: the shared event pointer
- **/
-int __iio_push_event(struct iio_event_interface *ev_int,
- int ev_code,
- s64 timestamp,
- struct iio_shared_ev_pointer*
- shared_pointer_p);
-/**
- * __iio_change_event() - change an event code in case of event escalation
- * @ev: the event to be changed
- * @ev_code: new event code
- * @timestamp: new timestamp
- **/
-void __iio_change_event(struct iio_detected_event_list *ev,
- int ev_code,
- s64 timestamp);
-
-/**
- * iio_setup_ev_int() - configure an event interface (chrdev)
- * @name: name used for resulting sysfs directory etc.
- * @ev_int: interface we are configuring
- * @owner: module that is responsible for registering this ev_int
- * @dev: device whose ev_int this is
- **/
-int iio_setup_ev_int(struct iio_event_interface *ev_int,
- const char *name,
- struct module *owner,
- struct device *dev);
-
-void iio_free_ev_int(struct iio_event_interface *ev_int);
-
-/**
- * iio_allocate_chrdev() - Allocate a chrdev
- * @handler: struct that contains relevant file handling for chrdev
- * @dev_info: iio_dev for which chrdev is being created
- **/
-int iio_allocate_chrdev(struct iio_handler *handler, struct iio_dev *dev_info);
-void iio_deallocate_chrdev(struct iio_handler *handler);
-
/* Used to distinguish between bipolar and unipolar scan elemenents.
* Whilst this may seem obvious, we may well want to change the representation
* in the future!*/
@@ -264,10 +363,25 @@
return d->dev_data;
}
+
+/* Can we make this smaller? */
+#define IIO_ALIGN L1_CACHE_BYTES
/**
* iio_allocate_device() - allocate an iio_dev from a driver
+ * @sizeof_priv: Space to allocate for private structure.
**/
-struct iio_dev *iio_allocate_device(void);
+struct iio_dev *iio_allocate_device(int sizeof_priv);
+
+static inline void *iio_priv(const struct iio_dev *dev)
+{
+ return (char *)dev + ALIGN(sizeof(struct iio_dev), IIO_ALIGN);
+}
+
+static inline struct iio_dev *iio_priv_to_dev(void *priv)
+{
+ return (struct iio_dev *)((char *)priv -
+ ALIGN(sizeof(struct iio_dev), IIO_ALIGN));
+}
/**
* iio_free_device() - free an iio_dev from a driver
diff --git a/drivers/staging/iio/imu/Kconfig b/drivers/staging/iio/imu/Kconfig
index 31a6233..e0e0144 100644
--- a/drivers/staging/iio/imu/Kconfig
+++ b/drivers/staging/iio/imu/Kconfig
@@ -3,29 +3,13 @@
#
comment "Inertial measurement units"
-config ADIS16300
- tristate "Analog Devices ADIS16300 IMU SPI driver"
- depends on SPI
- select IIO_SW_RING if IIO_RING_BUFFER
- select IIO_TRIGGER if IIO_RING_BUFFER
- help
- Say yes here to build support for Analog Devices adis16300 four degrees
- of freedom inertial sensor.
-
-config ADIS16350
- tristate "Analog Devices ADIS16350/54/55/60/62/64/65 IMU SPI driver"
- depends on SPI
- select IIO_TRIGGER if IIO_RING_BUFFER
- select IIO_SW_RING if IIO_RING_BUFFER
- help
- Say yes here to build support for Analog Devices adis16350/54/55/60/62/64/65
- high precision tri-axis inertial sensor.
-
config ADIS16400
- tristate "Analog Devices ADIS16400/5 IMU SPI driver"
+ tristate "Analog Devices ADIS16400 and similar IMU SPI driver"
depends on SPI
select IIO_SW_RING if IIO_RING_BUFFER
select IIO_TRIGGER if IIO_RING_BUFFER
help
- Say yes here to build support for Analog Devices adis16400/5 triaxial
- inertial sensor with Magnetometer.
+ Say yes here to build support for Analog Devices adis16300, adis16350,
+ adis16354, adis16355, adis16360, adis16362, adis16364, adis16365,
+ adis16400 and adis16405 triaxial inertial sensors (adis16400 series
+ also have magnetometers).
diff --git a/drivers/staging/iio/imu/Makefile b/drivers/staging/iio/imu/Makefile
index f3b450b..d46a691 100644
--- a/drivers/staging/iio/imu/Makefile
+++ b/drivers/staging/iio/imu/Makefile
@@ -2,14 +2,6 @@
# Makefile for Inertial Measurement Units
#
-adis16300-y := adis16300_core.o
-adis16300-$(CONFIG_IIO_RING_BUFFER) += adis16300_ring.o adis16300_trigger.o
-obj-$(CONFIG_ADIS16300) += adis16300.o
-
-adis16350-y := adis16350_core.o
-adis16350-$(CONFIG_IIO_RING_BUFFER) += adis16350_ring.o adis16350_trigger.o
-obj-$(CONFIG_ADIS16350) += adis16350.o
-
adis16400-y := adis16400_core.o
adis16400-$(CONFIG_IIO_RING_BUFFER) += adis16400_ring.o adis16400_trigger.o
obj-$(CONFIG_ADIS16400) += adis16400.o
diff --git a/drivers/staging/iio/imu/adis16300.h b/drivers/staging/iio/imu/adis16300.h
deleted file mode 100644
index c095759..0000000
--- a/drivers/staging/iio/imu/adis16300.h
+++ /dev/null
@@ -1,184 +0,0 @@
-#ifndef SPI_ADIS16300_H_
-#define SPI_ADIS16300_H_
-
-#define ADIS16300_STARTUP_DELAY 220 /* ms */
-
-#define ADIS16300_READ_REG(a) a
-#define ADIS16300_WRITE_REG(a) ((a) | 0x80)
-
-#define ADIS16300_FLASH_CNT 0x00 /* Flash memory write count */
-#define ADIS16300_SUPPLY_OUT 0x02 /* Power supply measurement */
-#define ADIS16300_XGYRO_OUT 0x04 /* X-axis gyroscope output */
-#define ADIS16300_XACCL_OUT 0x0A /* X-axis accelerometer output */
-#define ADIS16300_YACCL_OUT 0x0C /* Y-axis accelerometer output */
-#define ADIS16300_ZACCL_OUT 0x0E /* Z-axis accelerometer output */
-#define ADIS16300_TEMP_OUT 0x10 /* Temperature output */
-#define ADIS16300_XINCLI_OUT 0x12 /* X-axis inclinometer output measurement */
-#define ADIS16300_YINCLI_OUT 0x14 /* Y-axis inclinometer output measurement */
-#define ADIS16300_AUX_ADC 0x16 /* Auxiliary ADC measurement */
-
-/* Calibration parameters */
-#define ADIS16300_XGYRO_OFF 0x1A /* X-axis gyroscope bias offset factor */
-#define ADIS16300_XACCL_OFF 0x20 /* X-axis acceleration bias offset factor */
-#define ADIS16300_YACCL_OFF 0x22 /* Y-axis acceleration bias offset factor */
-#define ADIS16300_ZACCL_OFF 0x24 /* Z-axis acceleration bias offset factor */
-
-#define ADIS16300_GPIO_CTRL 0x32 /* Auxiliary digital input/output control */
-#define ADIS16300_MSC_CTRL 0x34 /* Miscellaneous control */
-#define ADIS16300_SMPL_PRD 0x36 /* Internal sample period (rate) control */
-#define ADIS16300_SENS_AVG 0x38 /* Dynamic range and digital filter control */
-#define ADIS16300_SLP_CNT 0x3A /* Sleep mode control */
-#define ADIS16300_DIAG_STAT 0x3C /* System status */
-
-/* Alarm functions */
-#define ADIS16300_GLOB_CMD 0x3E /* System command */
-#define ADIS16300_ALM_MAG1 0x26 /* Alarm 1 amplitude threshold */
-#define ADIS16300_ALM_MAG2 0x28 /* Alarm 2 amplitude threshold */
-#define ADIS16300_ALM_SMPL1 0x2A /* Alarm 1 sample size */
-#define ADIS16300_ALM_SMPL2 0x2C /* Alarm 2 sample size */
-#define ADIS16300_ALM_CTRL 0x2E /* Alarm control */
-#define ADIS16300_AUX_DAC 0x30 /* Auxiliary DAC data */
-
-#define ADIS16300_ERROR_ACTIVE (1<<14)
-#define ADIS16300_NEW_DATA (1<<15)
-
-/* MSC_CTRL */
-#define ADIS16300_MSC_CTRL_MEM_TEST (1<<11)
-#define ADIS16300_MSC_CTRL_INT_SELF_TEST (1<<10)
-#define ADIS16300_MSC_CTRL_NEG_SELF_TEST (1<<9)
-#define ADIS16300_MSC_CTRL_POS_SELF_TEST (1<<8)
-#define ADIS16300_MSC_CTRL_GYRO_BIAS (1<<7)
-#define ADIS16300_MSC_CTRL_ACCL_ALIGN (1<<6)
-#define ADIS16300_MSC_CTRL_DATA_RDY_EN (1<<2)
-#define ADIS16300_MSC_CTRL_DATA_RDY_POL_HIGH (1<<1)
-#define ADIS16300_MSC_CTRL_DATA_RDY_DIO2 (1<<0)
-
-/* SMPL_PRD */
-#define ADIS16300_SMPL_PRD_TIME_BASE (1<<7)
-#define ADIS16300_SMPL_PRD_DIV_MASK 0x7F
-
-/* DIAG_STAT */
-#define ADIS16300_DIAG_STAT_ZACCL_FAIL (1<<15)
-#define ADIS16300_DIAG_STAT_YACCL_FAIL (1<<14)
-#define ADIS16300_DIAG_STAT_XACCL_FAIL (1<<13)
-#define ADIS16300_DIAG_STAT_XGYRO_FAIL (1<<10)
-#define ADIS16300_DIAG_STAT_ALARM2 (1<<9)
-#define ADIS16300_DIAG_STAT_ALARM1 (1<<8)
-#define ADIS16300_DIAG_STAT_FLASH_CHK (1<<6)
-#define ADIS16300_DIAG_STAT_SELF_TEST (1<<5)
-#define ADIS16300_DIAG_STAT_OVERFLOW (1<<4)
-#define ADIS16300_DIAG_STAT_SPI_FAIL (1<<3)
-#define ADIS16300_DIAG_STAT_FLASH_UPT (1<<2)
-#define ADIS16300_DIAG_STAT_POWER_HIGH (1<<1)
-#define ADIS16300_DIAG_STAT_POWER_LOW (1<<0)
-
-/* GLOB_CMD */
-#define ADIS16300_GLOB_CMD_SW_RESET (1<<7)
-#define ADIS16300_GLOB_CMD_P_AUTO_NULL (1<<4)
-#define ADIS16300_GLOB_CMD_FLASH_UPD (1<<3)
-#define ADIS16300_GLOB_CMD_DAC_LATCH (1<<2)
-#define ADIS16300_GLOB_CMD_FAC_CALIB (1<<1)
-#define ADIS16300_GLOB_CMD_AUTO_NULL (1<<0)
-
-/* SLP_CNT */
-#define ADIS16300_SLP_CNT_POWER_OFF (1<<8)
-
-#define ADIS16300_MAX_TX 18
-#define ADIS16300_MAX_RX 18
-
-#define ADIS16300_SPI_SLOW (u32)(300 * 1000)
-#define ADIS16300_SPI_BURST (u32)(1000 * 1000)
-#define ADIS16300_SPI_FAST (u32)(2000 * 1000)
-
-/**
- * struct adis16300_state - device instance specific data
- * @us: actual spi_device
- * @work_trigger_to_ring: bh for triggered event handling
- * @inter: used to check if new interrupt has been triggered
- * @last_timestamp: passing timestamp from th to bh of interrupt handler
- * @indio_dev: industrial I/O device structure
- * @trig: data ready trigger registered with iio
- * @tx: transmit buffer
- * @rx: receive buffer
- * @buf_lock: mutex to protect tx and rx
- **/
-struct adis16300_state {
- struct spi_device *us;
- struct work_struct work_trigger_to_ring;
- s64 last_timestamp;
- struct iio_dev *indio_dev;
- struct iio_trigger *trig;
- u8 *tx;
- u8 *rx;
- struct mutex buf_lock;
-};
-
-int adis16300_set_irq(struct device *dev, bool enable);
-
-#ifdef CONFIG_IIO_RING_BUFFER
-/* At the moment triggers are only used for ring buffer
- * filling. This may change!
- */
-
-#define ADIS16300_SCAN_SUPPLY 0
-#define ADIS16300_SCAN_GYRO_X 1
-#define ADIS16300_SCAN_ACC_X 2
-#define ADIS16300_SCAN_ACC_Y 3
-#define ADIS16300_SCAN_ACC_Z 4
-#define ADIS16300_SCAN_TEMP 5
-#define ADIS16300_SCAN_ADC_0 6
-#define ADIS16300_SCAN_INCLI_X 7
-#define ADIS16300_SCAN_INCLI_Y 8
-
-void adis16300_remove_trigger(struct iio_dev *indio_dev);
-int adis16300_probe_trigger(struct iio_dev *indio_dev);
-
-ssize_t adis16300_read_data_from_ring(struct device *dev,
- struct device_attribute *attr,
- char *buf);
-
-
-int adis16300_configure_ring(struct iio_dev *indio_dev);
-void adis16300_unconfigure_ring(struct iio_dev *indio_dev);
-
-int adis16300_initialize_ring(struct iio_ring_buffer *ring);
-void adis16300_uninitialize_ring(struct iio_ring_buffer *ring);
-#else /* CONFIG_IIO_RING_BUFFER */
-
-static inline void adis16300_remove_trigger(struct iio_dev *indio_dev)
-{
-}
-
-static inline int adis16300_probe_trigger(struct iio_dev *indio_dev)
-{
- return 0;
-}
-
-static inline ssize_t
-adis16300_read_data_from_ring(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- return 0;
-}
-
-static int adis16300_configure_ring(struct iio_dev *indio_dev)
-{
- return 0;
-}
-
-static inline void adis16300_unconfigure_ring(struct iio_dev *indio_dev)
-{
-}
-
-static inline int adis16300_initialize_ring(struct iio_ring_buffer *ring)
-{
- return 0;
-}
-
-static inline void adis16300_uninitialize_ring(struct iio_ring_buffer *ring)
-{
-}
-
-#endif /* CONFIG_IIO_RING_BUFFER */
-#endif /* SPI_ADIS16300_H_ */
diff --git a/drivers/staging/iio/imu/adis16300_core.c b/drivers/staging/iio/imu/adis16300_core.c
deleted file mode 100644
index 7ad13f4..0000000
--- a/drivers/staging/iio/imu/adis16300_core.c
+++ /dev/null
@@ -1,756 +0,0 @@
-/*
- * ADIS16300 Four Degrees of Freedom Inertial Sensor Driver
- *
- * Copyright 2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/gpio.h>
-#include <linux/delay.h>
-#include <linux/mutex.h>
-#include <linux/device.h>
-#include <linux/kernel.h>
-#include <linux/spi/spi.h>
-#include <linux/slab.h>
-#include <linux/sysfs.h>
-#include <linux/list.h>
-
-#include "../iio.h"
-#include "../sysfs.h"
-#include "../ring_generic.h"
-#include "../accel/accel.h"
-#include "../accel/inclinometer.h"
-#include "../gyro/gyro.h"
-#include "../adc/adc.h"
-
-#include "adis16300.h"
-
-#define DRIVER_NAME "adis16300"
-
-static int adis16300_check_status(struct device *dev);
-
-/**
- * adis16300_spi_write_reg_8() - write single byte to a register
- * @dev: device associated with child of actual device (iio_dev or iio_trig)
- * @reg_address: the address of the register to be written
- * @val: the value to write
- **/
-static int adis16300_spi_write_reg_8(struct device *dev,
- u8 reg_address,
- u8 val)
-{
- int ret;
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
- struct adis16300_state *st = iio_dev_get_devdata(indio_dev);
-
- mutex_lock(&st->buf_lock);
- st->tx[0] = ADIS16300_WRITE_REG(reg_address);
- st->tx[1] = val;
-
- ret = spi_write(st->us, st->tx, 2);
- mutex_unlock(&st->buf_lock);
-
- return ret;
-}
-
-/**
- * adis16300_spi_write_reg_16() - write 2 bytes to a pair of registers
- * @dev: device associated with child of actual device (iio_dev or iio_trig)
- * @reg_address: the address of the lower of the two registers. Second register
- * is assumed to have address one greater.
- * @val: value to be written
- **/
-static int adis16300_spi_write_reg_16(struct device *dev,
- u8 lower_reg_address,
- u16 value)
-{
- int ret;
- struct spi_message msg;
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
- struct adis16300_state *st = iio_dev_get_devdata(indio_dev);
- struct spi_transfer xfers[] = {
- {
- .tx_buf = st->tx,
- .bits_per_word = 8,
- .len = 2,
- .cs_change = 1,
- .delay_usecs = 75,
- }, {
- .tx_buf = st->tx + 2,
- .bits_per_word = 8,
- .len = 2,
- .cs_change = 1,
- .delay_usecs = 75,
- },
- };
-
- mutex_lock(&st->buf_lock);
- st->tx[0] = ADIS16300_WRITE_REG(lower_reg_address);
- st->tx[1] = value & 0xFF;
- st->tx[2] = ADIS16300_WRITE_REG(lower_reg_address + 1);
- st->tx[3] = (value >> 8) & 0xFF;
-
- spi_message_init(&msg);
- spi_message_add_tail(&xfers[0], &msg);
- spi_message_add_tail(&xfers[1], &msg);
- ret = spi_sync(st->us, &msg);
- mutex_unlock(&st->buf_lock);
-
- return ret;
-}
-
-/**
- * adis16300_spi_read_reg_16() - read 2 bytes from a 16-bit register
- * @dev: device associated with child of actual device (iio_dev or iio_trig)
- * @reg_address: the address of the lower of the two registers. Second register
- * is assumed to have address one greater.
- * @val: somewhere to pass back the value read
- **/
-static int adis16300_spi_read_reg_16(struct device *dev,
- u8 lower_reg_address,
- u16 *val)
-{
- struct spi_message msg;
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
- struct adis16300_state *st = iio_dev_get_devdata(indio_dev);
- int ret;
- struct spi_transfer xfers[] = {
- {
- .tx_buf = st->tx,
- .bits_per_word = 8,
- .len = 2,
- .cs_change = 1,
- .delay_usecs = 75,
- }, {
- .rx_buf = st->rx,
- .bits_per_word = 8,
- .len = 2,
- .cs_change = 1,
- .delay_usecs = 75,
- },
- };
-
- mutex_lock(&st->buf_lock);
- st->tx[0] = ADIS16300_READ_REG(lower_reg_address);
- st->tx[1] = 0;
- st->tx[2] = 0;
- st->tx[3] = 0;
-
- spi_message_init(&msg);
- spi_message_add_tail(&xfers[0], &msg);
- spi_message_add_tail(&xfers[1], &msg);
- ret = spi_sync(st->us, &msg);
- if (ret) {
- dev_err(&st->us->dev,
- "problem when reading 16 bit register 0x%02X",
- lower_reg_address);
- goto error_ret;
- }
- *val = (st->rx[0] << 8) | st->rx[1];
-
-error_ret:
- mutex_unlock(&st->buf_lock);
- return ret;
-}
-
-static ssize_t adis16300_spi_read_signed(struct device *dev,
- struct device_attribute *attr,
- char *buf,
- unsigned bits)
-{
- int ret;
- s16 val = 0;
- unsigned shift = 16 - bits;
- struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
-
- ret = adis16300_spi_read_reg_16(dev, this_attr->address, (u16 *)&val);
- if (ret)
- return ret;
-
- if (val & ADIS16300_ERROR_ACTIVE)
- adis16300_check_status(dev);
- val = ((s16)(val << shift) >> shift);
- return sprintf(buf, "%d\n", val);
-}
-
-static ssize_t adis16300_read_12bit_unsigned(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- int ret;
- u16 val = 0;
- struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
-
- ret = adis16300_spi_read_reg_16(dev, this_attr->address, &val);
- if (ret)
- return ret;
-
- if (val & ADIS16300_ERROR_ACTIVE)
- adis16300_check_status(dev);
-
- return sprintf(buf, "%u\n", val & 0x0FFF);
-}
-
-static ssize_t adis16300_read_14bit_unsigned(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- int ret;
- u16 val = 0;
- struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
-
- ret = adis16300_spi_read_reg_16(dev, this_attr->address, &val);
- if (ret)
- return ret;
-
- if (val & ADIS16300_ERROR_ACTIVE)
- adis16300_check_status(dev);
-
- return sprintf(buf, "%u\n", val & 0x3FFF);
-}
-
-static ssize_t adis16300_read_14bit_signed(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
- ssize_t ret;
-
- /* Take the iio_dev status lock */
- mutex_lock(&indio_dev->mlock);
- ret = adis16300_spi_read_signed(dev, attr, buf, 14);
- mutex_unlock(&indio_dev->mlock);
-
- return ret;
-}
-
-static ssize_t adis16300_read_12bit_signed(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
- ssize_t ret;
-
- /* Take the iio_dev status lock */
- mutex_lock(&indio_dev->mlock);
- ret = adis16300_spi_read_signed(dev, attr, buf, 12);
- mutex_unlock(&indio_dev->mlock);
-
- return ret;
-}
-
-static ssize_t adis16300_read_13bit_signed(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
- ssize_t ret;
-
- /* Take the iio_dev status lock */
- mutex_lock(&indio_dev->mlock);
- ret = adis16300_spi_read_signed(dev, attr, buf, 13);
- mutex_unlock(&indio_dev->mlock);
-
- return ret;
-}
-
-static ssize_t adis16300_write_16bit(struct device *dev,
- struct device_attribute *attr,
- const char *buf,
- size_t len)
-{
- struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
- int ret;
- long val;
-
- ret = strict_strtol(buf, 10, &val);
- if (ret)
- goto error_ret;
- ret = adis16300_spi_write_reg_16(dev, this_attr->address, val);
-
-error_ret:
- return ret ? ret : len;
-}
-
-static ssize_t adis16300_read_frequency(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- int ret, len = 0;
- u16 t;
- int sps;
- ret = adis16300_spi_read_reg_16(dev,
- ADIS16300_SMPL_PRD,
- &t);
- if (ret)
- return ret;
- sps = (t & ADIS16300_SMPL_PRD_TIME_BASE) ? 53 : 1638;
- sps /= (t & ADIS16300_SMPL_PRD_DIV_MASK) + 1;
- len = sprintf(buf, "%d SPS\n", sps);
- return len;
-}
-
-static ssize_t adis16300_write_frequency(struct device *dev,
- struct device_attribute *attr,
- const char *buf,
- size_t len)
-{
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
- struct adis16300_state *st = iio_dev_get_devdata(indio_dev);
- long val;
- int ret;
- u8 t;
-
- ret = strict_strtol(buf, 10, &val);
- if (ret)
- return ret;
-
- mutex_lock(&indio_dev->mlock);
-
- t = (1638 / val);
- if (t > 0)
- t--;
- t &= ADIS16300_SMPL_PRD_DIV_MASK;
- if ((t & ADIS16300_SMPL_PRD_DIV_MASK) >= 0x0A)
- st->us->max_speed_hz = ADIS16300_SPI_SLOW;
- else
- st->us->max_speed_hz = ADIS16300_SPI_FAST;
-
- ret = adis16300_spi_write_reg_8(dev,
- ADIS16300_SMPL_PRD,
- t);
-
- mutex_unlock(&indio_dev->mlock);
-
- return ret ? ret : len;
-}
-
-static int adis16300_reset(struct device *dev)
-{
- int ret;
- ret = adis16300_spi_write_reg_8(dev,
- ADIS16300_GLOB_CMD,
- ADIS16300_GLOB_CMD_SW_RESET);
- if (ret)
- dev_err(dev, "problem resetting device");
-
- return ret;
-}
-
-static ssize_t adis16300_write_reset(struct device *dev,
- struct device_attribute *attr,
- const char *buf, size_t len)
-{
- if (len < 1)
- return -1;
- switch (buf[0]) {
- case '1':
- case 'y':
- case 'Y':
- return adis16300_reset(dev);
- }
- return -1;
-}
-
-int adis16300_set_irq(struct device *dev, bool enable)
-{
- int ret;
- u16 msc;
- ret = adis16300_spi_read_reg_16(dev, ADIS16300_MSC_CTRL, &msc);
- if (ret)
- goto error_ret;
-
- msc |= ADIS16300_MSC_CTRL_DATA_RDY_POL_HIGH;
- msc &= ~ADIS16300_MSC_CTRL_DATA_RDY_DIO2;
- if (enable)
- msc |= ADIS16300_MSC_CTRL_DATA_RDY_EN;
- else
- msc &= ~ADIS16300_MSC_CTRL_DATA_RDY_EN;
-
- ret = adis16300_spi_write_reg_16(dev, ADIS16300_MSC_CTRL, msc);
- if (ret)
- goto error_ret;
-
-error_ret:
- return ret;
-}
-
-/* Power down the device */
-static int adis16300_stop_device(struct device *dev)
-{
- int ret;
- u16 val = ADIS16300_SLP_CNT_POWER_OFF;
-
- ret = adis16300_spi_write_reg_16(dev, ADIS16300_SLP_CNT, val);
- if (ret)
- dev_err(dev, "problem with turning device off: SLP_CNT");
-
- return ret;
-}
-
-static int adis16300_self_test(struct device *dev)
-{
- int ret;
- ret = adis16300_spi_write_reg_16(dev,
- ADIS16300_MSC_CTRL,
- ADIS16300_MSC_CTRL_MEM_TEST);
- if (ret) {
- dev_err(dev, "problem starting self test");
- goto err_ret;
- }
-
- adis16300_check_status(dev);
-
-err_ret:
- return ret;
-}
-
-static int adis16300_check_status(struct device *dev)
-{
- u16 status;
- int ret;
-
- ret = adis16300_spi_read_reg_16(dev, ADIS16300_DIAG_STAT, &status);
-
- if (ret < 0) {
- dev_err(dev, "Reading status failed\n");
- goto error_ret;
- }
- ret = status;
- if (status & ADIS16300_DIAG_STAT_ZACCL_FAIL)
- dev_err(dev, "Z-axis accelerometer self-test failure\n");
- if (status & ADIS16300_DIAG_STAT_YACCL_FAIL)
- dev_err(dev, "Y-axis accelerometer self-test failure\n");
- if (status & ADIS16300_DIAG_STAT_XACCL_FAIL)
- dev_err(dev, "X-axis accelerometer self-test failure\n");
- if (status & ADIS16300_DIAG_STAT_XGYRO_FAIL)
- dev_err(dev, "X-axis gyroscope self-test failure\n");
- if (status & ADIS16300_DIAG_STAT_ALARM2)
- dev_err(dev, "Alarm 2 active\n");
- if (status & ADIS16300_DIAG_STAT_ALARM1)
- dev_err(dev, "Alarm 1 active\n");
- if (status & ADIS16300_DIAG_STAT_FLASH_CHK)
- dev_err(dev, "Flash checksum error\n");
- if (status & ADIS16300_DIAG_STAT_SELF_TEST)
- dev_err(dev, "Self test error\n");
- if (status & ADIS16300_DIAG_STAT_OVERFLOW)
- dev_err(dev, "Sensor overrange\n");
- if (status & ADIS16300_DIAG_STAT_SPI_FAIL)
- dev_err(dev, "SPI failure\n");
- if (status & ADIS16300_DIAG_STAT_FLASH_UPT)
- dev_err(dev, "Flash update failed\n");
- if (status & ADIS16300_DIAG_STAT_POWER_HIGH)
- dev_err(dev, "Power supply above 5.25V\n");
- if (status & ADIS16300_DIAG_STAT_POWER_LOW)
- dev_err(dev, "Power supply below 4.75V\n");
-
-error_ret:
- return ret;
-}
-
-static int adis16300_initial_setup(struct adis16300_state *st)
-{
- int ret;
- u16 smp_prd;
- struct device *dev = &st->indio_dev->dev;
-
- /* use low spi speed for init */
- st->us->max_speed_hz = ADIS16300_SPI_SLOW;
- st->us->mode = SPI_MODE_3;
- spi_setup(st->us);
-
- /* Disable IRQ */
- ret = adis16300_set_irq(dev, false);
- if (ret) {
- dev_err(dev, "disable irq failed");
- goto err_ret;
- }
-
- /* Do self test */
- ret = adis16300_self_test(dev);
- if (ret) {
- dev_err(dev, "self test failure");
- goto err_ret;
- }
-
- /* Read status register to check the result */
- ret = adis16300_check_status(dev);
- if (ret) {
- adis16300_reset(dev);
- dev_err(dev, "device not playing ball -> reset");
- msleep(ADIS16300_STARTUP_DELAY);
- ret = adis16300_check_status(dev);
- if (ret) {
- dev_err(dev, "giving up");
- goto err_ret;
- }
- }
-
- printk(KERN_INFO DRIVER_NAME ": at CS%d (irq %d)\n",
- st->us->chip_select, st->us->irq);
-
- /* use high spi speed if possible */
- ret = adis16300_spi_read_reg_16(dev, ADIS16300_SMPL_PRD, &smp_prd);
- if (!ret && (smp_prd & ADIS16300_SMPL_PRD_DIV_MASK) < 0x0A) {
- st->us->max_speed_hz = ADIS16300_SPI_SLOW;
- spi_setup(st->us);
- }
-
-err_ret:
- return ret;
-}
-
-static IIO_DEV_ATTR_GYRO_X_CALIBBIAS(S_IWUSR | S_IRUGO,
- adis16300_read_12bit_signed,
- adis16300_write_16bit,
- ADIS16300_XGYRO_OFF);
-
-static IIO_DEV_ATTR_ACCEL_X_CALIBBIAS(S_IWUSR | S_IRUGO,
- adis16300_read_12bit_signed,
- adis16300_write_16bit,
- ADIS16300_XACCL_OFF);
-
-static IIO_DEV_ATTR_ACCEL_Y_CALIBBIAS(S_IWUSR | S_IRUGO,
- adis16300_read_12bit_signed,
- adis16300_write_16bit,
- ADIS16300_YACCL_OFF);
-
-static IIO_DEV_ATTR_ACCEL_Z_CALIBBIAS(S_IWUSR | S_IRUGO,
- adis16300_read_12bit_signed,
- adis16300_write_16bit,
- ADIS16300_ZACCL_OFF);
-
-static IIO_DEV_ATTR_IN_NAMED_RAW(0, supply, adis16300_read_14bit_unsigned,
- ADIS16300_SUPPLY_OUT);
-static IIO_CONST_ATTR_IN_NAMED_SCALE(0, supply, "0.00242");
-
-static IIO_DEV_ATTR_GYRO_X(adis16300_read_14bit_signed,
- ADIS16300_XGYRO_OUT);
-static IIO_CONST_ATTR_GYRO_SCALE("0.000872664");
-
-static IIO_DEV_ATTR_ACCEL_X(adis16300_read_14bit_signed,
- ADIS16300_XACCL_OUT);
-static IIO_DEV_ATTR_ACCEL_Y(adis16300_read_14bit_signed,
- ADIS16300_YACCL_OUT);
-static IIO_DEV_ATTR_ACCEL_Z(adis16300_read_14bit_signed,
- ADIS16300_ZACCL_OUT);
-static IIO_CONST_ATTR_ACCEL_SCALE("0.00588399");
-
-static IIO_DEV_ATTR_INCLI_X(adis16300_read_13bit_signed,
- ADIS16300_XINCLI_OUT);
-static IIO_DEV_ATTR_INCLI_Y(adis16300_read_13bit_signed,
- ADIS16300_YINCLI_OUT);
-static IIO_CONST_ATTR_INCLI_SCALE("0.00076794487");
-
-static IIO_DEV_ATTR_TEMP_RAW(adis16300_read_12bit_unsigned);
-static IIO_CONST_ATTR_TEMP_OFFSET("198.16");
-static IIO_CONST_ATTR_TEMP_SCALE("0.14");
-
-static IIO_DEV_ATTR_IN_RAW(1, adis16300_read_12bit_unsigned,
- ADIS16300_AUX_ADC);
-static IIO_CONST_ATTR(in1_scale, "0.000806");
-
-static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO,
- adis16300_read_frequency,
- adis16300_write_frequency);
-
-static IIO_DEVICE_ATTR(reset, S_IWUSR, NULL, adis16300_write_reset, 0);
-
-static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("409 546 819 1638");
-
-static IIO_CONST_ATTR_NAME("adis16300");
-
-static struct attribute *adis16300_event_attributes[] = {
- NULL
-};
-
-static struct attribute_group adis16300_event_attribute_group = {
- .attrs = adis16300_event_attributes,
-};
-
-static struct attribute *adis16300_attributes[] = {
- &iio_dev_attr_gyro_x_calibbias.dev_attr.attr,
- &iio_dev_attr_accel_x_calibbias.dev_attr.attr,
- &iio_dev_attr_accel_y_calibbias.dev_attr.attr,
- &iio_dev_attr_accel_z_calibbias.dev_attr.attr,
- &iio_dev_attr_in0_supply_raw.dev_attr.attr,
- &iio_const_attr_in0_supply_scale.dev_attr.attr,
- &iio_dev_attr_gyro_x_raw.dev_attr.attr,
- &iio_const_attr_gyro_scale.dev_attr.attr,
- &iio_dev_attr_accel_x_raw.dev_attr.attr,
- &iio_dev_attr_accel_y_raw.dev_attr.attr,
- &iio_dev_attr_accel_z_raw.dev_attr.attr,
- &iio_const_attr_accel_scale.dev_attr.attr,
- &iio_dev_attr_incli_x_raw.dev_attr.attr,
- &iio_dev_attr_incli_y_raw.dev_attr.attr,
- &iio_const_attr_incli_scale.dev_attr.attr,
- &iio_dev_attr_temp_raw.dev_attr.attr,
- &iio_const_attr_temp_offset.dev_attr.attr,
- &iio_const_attr_temp_scale.dev_attr.attr,
- &iio_dev_attr_in1_raw.dev_attr.attr,
- &iio_const_attr_in1_scale.dev_attr.attr,
- &iio_dev_attr_sampling_frequency.dev_attr.attr,
- &iio_const_attr_sampling_frequency_available.dev_attr.attr,
- &iio_dev_attr_reset.dev_attr.attr,
- &iio_const_attr_name.dev_attr.attr,
- NULL
-};
-
-static const struct attribute_group adis16300_attribute_group = {
- .attrs = adis16300_attributes,
-};
-
-static int __devinit adis16300_probe(struct spi_device *spi)
-{
- int ret, regdone = 0;
- struct adis16300_state *st = kzalloc(sizeof *st, GFP_KERNEL);
- if (!st) {
- ret = -ENOMEM;
- goto error_ret;
- }
- /* this is only used for removal purposes */
- spi_set_drvdata(spi, st);
-
- /* Allocate the comms buffers */
- st->rx = kzalloc(sizeof(*st->rx)*ADIS16300_MAX_RX, GFP_KERNEL);
- if (st->rx == NULL) {
- ret = -ENOMEM;
- goto error_free_st;
- }
- st->tx = kzalloc(sizeof(*st->tx)*ADIS16300_MAX_TX, GFP_KERNEL);
- if (st->tx == NULL) {
- ret = -ENOMEM;
- goto error_free_rx;
- }
- st->us = spi;
- mutex_init(&st->buf_lock);
- /* setup the industrialio driver allocated elements */
- st->indio_dev = iio_allocate_device();
- if (st->indio_dev == NULL) {
- ret = -ENOMEM;
- goto error_free_tx;
- }
-
- st->indio_dev->dev.parent = &spi->dev;
- st->indio_dev->num_interrupt_lines = 1;
- st->indio_dev->event_attrs = &adis16300_event_attribute_group;
- st->indio_dev->attrs = &adis16300_attribute_group;
- st->indio_dev->dev_data = (void *)(st);
- st->indio_dev->driver_module = THIS_MODULE;
- st->indio_dev->modes = INDIO_DIRECT_MODE;
-
- ret = adis16300_configure_ring(st->indio_dev);
- if (ret)
- goto error_free_dev;
-
- ret = iio_device_register(st->indio_dev);
- if (ret)
- goto error_unreg_ring_funcs;
- regdone = 1;
-
- ret = iio_ring_buffer_register(st->indio_dev->ring, 0);
- if (ret) {
- printk(KERN_ERR "failed to initialize the ring\n");
- goto error_unreg_ring_funcs;
- }
-
- if (spi->irq) {
- ret = iio_register_interrupt_line(spi->irq,
- st->indio_dev,
- 0,
- IRQF_TRIGGER_RISING,
- "adis16300");
- if (ret)
- goto error_uninitialize_ring;
-
- ret = adis16300_probe_trigger(st->indio_dev);
- if (ret)
- goto error_unregister_line;
- }
-
- /* Get the device into a sane initial state */
- ret = adis16300_initial_setup(st);
- if (ret)
- goto error_remove_trigger;
- return 0;
-
-error_remove_trigger:
- adis16300_remove_trigger(st->indio_dev);
-error_unregister_line:
- if (spi->irq)
- iio_unregister_interrupt_line(st->indio_dev, 0);
-error_uninitialize_ring:
- iio_ring_buffer_unregister(st->indio_dev->ring);
-error_unreg_ring_funcs:
- adis16300_unconfigure_ring(st->indio_dev);
-error_free_dev:
- if (regdone)
- iio_device_unregister(st->indio_dev);
- else
- iio_free_device(st->indio_dev);
-error_free_tx:
- kfree(st->tx);
-error_free_rx:
- kfree(st->rx);
-error_free_st:
- kfree(st);
-error_ret:
- return ret;
-}
-
-static int adis16300_remove(struct spi_device *spi)
-{
- int ret;
- struct adis16300_state *st = spi_get_drvdata(spi);
- struct iio_dev *indio_dev = st->indio_dev;
-
- ret = adis16300_stop_device(&(indio_dev->dev));
- if (ret)
- goto err_ret;
-
- flush_scheduled_work();
-
- adis16300_remove_trigger(indio_dev);
- if (spi->irq)
- iio_unregister_interrupt_line(indio_dev, 0);
-
- iio_ring_buffer_unregister(indio_dev->ring);
- iio_device_unregister(indio_dev);
- adis16300_unconfigure_ring(indio_dev);
- kfree(st->tx);
- kfree(st->rx);
- kfree(st);
-
- return 0;
-
-err_ret:
- return ret;
-}
-
-static struct spi_driver adis16300_driver = {
- .driver = {
- .name = "adis16300",
- .owner = THIS_MODULE,
- },
- .probe = adis16300_probe,
- .remove = __devexit_p(adis16300_remove),
-};
-
-static __init int adis16300_init(void)
-{
- return spi_register_driver(&adis16300_driver);
-}
-module_init(adis16300_init);
-
-static __exit void adis16300_exit(void)
-{
- spi_unregister_driver(&adis16300_driver);
-}
-module_exit(adis16300_exit);
-
-MODULE_AUTHOR("Barry Song <21cnbao@gmail.com>");
-MODULE_DESCRIPTION("Analog Devices ADIS16300 IMU SPI driver");
-MODULE_LICENSE("GPL v2");
diff --git a/drivers/staging/iio/imu/adis16300_ring.c b/drivers/staging/iio/imu/adis16300_ring.c
deleted file mode 100644
index 114fdf4..0000000
--- a/drivers/staging/iio/imu/adis16300_ring.c
+++ /dev/null
@@ -1,238 +0,0 @@
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/gpio.h>
-#include <linux/workqueue.h>
-#include <linux/mutex.h>
-#include <linux/device.h>
-#include <linux/kernel.h>
-#include <linux/spi/spi.h>
-#include <linux/slab.h>
-#include <linux/sysfs.h>
-#include <linux/list.h>
-
-#include "../iio.h"
-#include "../sysfs.h"
-#include "../ring_sw.h"
-#include "../accel/accel.h"
-#include "../trigger.h"
-#include "adis16300.h"
-
-static IIO_SCAN_EL_C(in0_supply, ADIS16300_SCAN_SUPPLY,
- ADIS16300_SUPPLY_OUT, NULL);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(in0_supply, u, 12, 16);
-static IIO_SCAN_EL_C(gyro_x, ADIS16300_SCAN_GYRO_X, ADIS16300_XGYRO_OUT, NULL);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(gyro, s, 14, 16);
-
-static IIO_SCAN_EL_C(accel_x, ADIS16300_SCAN_ACC_X, ADIS16300_XACCL_OUT, NULL);
-static IIO_SCAN_EL_C(accel_y, ADIS16300_SCAN_ACC_Y, ADIS16300_YACCL_OUT, NULL);
-static IIO_SCAN_EL_C(accel_z, ADIS16300_SCAN_ACC_Z, ADIS16300_ZACCL_OUT, NULL);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(accel, s, 14, 16);
-
-static IIO_SCAN_EL_C(temp, ADIS16300_SCAN_TEMP, ADIS16300_TEMP_OUT, NULL);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(temp, s, 12, 16);
-
-static IIO_SCAN_EL_C(in1, ADIS16300_SCAN_ADC_0, ADIS16300_AUX_ADC, NULL);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(in1, u, 12, 16);
-
-static IIO_SCAN_EL_C(incli_x, ADIS16300_SCAN_INCLI_X,
- ADIS16300_XINCLI_OUT, NULL);
-static IIO_SCAN_EL_C(incli_y, ADIS16300_SCAN_INCLI_Y,
- ADIS16300_YINCLI_OUT, NULL);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(incli, s, 13, 16);
-
-static IIO_SCAN_EL_TIMESTAMP(9);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(timestamp, s, 64, 64);
-
-static struct attribute *adis16300_scan_el_attrs[] = {
- &iio_scan_el_in0_supply.dev_attr.attr,
- &iio_const_attr_in0_supply_index.dev_attr.attr,
- &iio_const_attr_in0_supply_type.dev_attr.attr,
- &iio_scan_el_gyro_x.dev_attr.attr,
- &iio_const_attr_gyro_x_index.dev_attr.attr,
- &iio_const_attr_gyro_type.dev_attr.attr,
- &iio_scan_el_temp.dev_attr.attr,
- &iio_const_attr_temp_index.dev_attr.attr,
- &iio_const_attr_temp_type.dev_attr.attr,
- &iio_scan_el_accel_x.dev_attr.attr,
- &iio_const_attr_accel_x_index.dev_attr.attr,
- &iio_scan_el_accel_y.dev_attr.attr,
- &iio_const_attr_accel_y_index.dev_attr.attr,
- &iio_scan_el_accel_z.dev_attr.attr,
- &iio_const_attr_accel_z_index.dev_attr.attr,
- &iio_const_attr_accel_type.dev_attr.attr,
- &iio_scan_el_incli_x.dev_attr.attr,
- &iio_const_attr_incli_x_index.dev_attr.attr,
- &iio_scan_el_incli_y.dev_attr.attr,
- &iio_const_attr_incli_y_index.dev_attr.attr,
- &iio_const_attr_incli_type.dev_attr.attr,
- &iio_scan_el_in1.dev_attr.attr,
- &iio_const_attr_in1_index.dev_attr.attr,
- &iio_const_attr_in1_type.dev_attr.attr,
- &iio_scan_el_timestamp.dev_attr.attr,
- &iio_const_attr_timestamp_index.dev_attr.attr,
- &iio_const_attr_timestamp_type.dev_attr.attr,
- NULL,
-};
-
-static struct attribute_group adis16300_scan_el_group = {
- .attrs = adis16300_scan_el_attrs,
- .name = "scan_elements",
-};
-
-/**
- * adis16300_poll_func_th() top half interrupt handler called by trigger
- * @private_data: iio_dev
- **/
-static void adis16300_poll_func_th(struct iio_dev *indio_dev, s64 time)
-{
- struct adis16300_state *st = iio_dev_get_devdata(indio_dev);
- st->last_timestamp = time;
- schedule_work(&st->work_trigger_to_ring);
- /* Indicate that this interrupt is being handled */
-
- /* Technically this is trigger related, but without this
- * handler running there is currently no way for the interrupt
- * to clear.
- */
-}
-
-/**
- * adis16300_spi_read_burst() - read all data registers
- * @dev: device associated with child of actual device (iio_dev or iio_trig)
- * @rx: somewhere to pass back the value read (min size is 24 bytes)
- **/
-static int adis16300_spi_read_burst(struct device *dev, u8 *rx)
-{
- struct spi_message msg;
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
- struct adis16300_state *st = iio_dev_get_devdata(indio_dev);
- u32 old_speed_hz = st->us->max_speed_hz;
- int ret;
-
- struct spi_transfer xfers[] = {
- {
- .tx_buf = st->tx,
- .bits_per_word = 8,
- .len = 2,
- .cs_change = 0,
- }, {
- .rx_buf = rx,
- .bits_per_word = 8,
- .len = 18,
- .cs_change = 0,
- },
- };
-
- mutex_lock(&st->buf_lock);
- st->tx[0] = ADIS16300_READ_REG(ADIS16300_GLOB_CMD);
- st->tx[1] = 0;
-
- spi_message_init(&msg);
- spi_message_add_tail(&xfers[0], &msg);
- spi_message_add_tail(&xfers[1], &msg);
-
- st->us->max_speed_hz = ADIS16300_SPI_BURST;
- spi_setup(st->us);
-
- ret = spi_sync(st->us, &msg);
- if (ret)
- dev_err(&st->us->dev, "problem when burst reading");
-
- st->us->max_speed_hz = old_speed_hz;
- spi_setup(st->us);
- mutex_unlock(&st->buf_lock);
- return ret;
-}
-
-/* Whilst this makes a lot of calls to iio_sw_ring functions - it is to device
- * specific to be rolled into the core.
- */
-static void adis16300_trigger_bh_to_ring(struct work_struct *work_s)
-{
- struct adis16300_state *st
- = container_of(work_s, struct adis16300_state,
- work_trigger_to_ring);
- struct iio_ring_buffer *ring = st->indio_dev->ring;
-
- int i = 0;
- s16 *data;
- size_t datasize = ring->access.get_bytes_per_datum(ring);
-
- data = kmalloc(datasize , GFP_KERNEL);
- if (data == NULL) {
- dev_err(&st->us->dev, "memory alloc failed in ring bh");
- return;
- }
-
- if (ring->scan_count)
- if (adis16300_spi_read_burst(&st->indio_dev->dev, st->rx) >= 0)
- for (; i < ring->scan_count; i++)
- data[i] = be16_to_cpup(
- (__be16 *)&(st->rx[i*2]));
-
- /* Guaranteed to be aligned with 8 byte boundary */
- if (ring->scan_timestamp)
- *((s64 *)(data + ((i + 3)/4)*4)) = st->last_timestamp;
-
- ring->access.store_to(ring,
- (u8 *)data,
- st->last_timestamp);
-
- iio_trigger_notify_done(st->indio_dev->trig);
- kfree(data);
-
- return;
-}
-
-void adis16300_unconfigure_ring(struct iio_dev *indio_dev)
-{
- kfree(indio_dev->pollfunc);
- iio_sw_rb_free(indio_dev->ring);
-}
-
-int adis16300_configure_ring(struct iio_dev *indio_dev)
-{
- int ret = 0;
- struct adis16300_state *st = indio_dev->dev_data;
- struct iio_ring_buffer *ring;
- INIT_WORK(&st->work_trigger_to_ring, adis16300_trigger_bh_to_ring);
-
- ring = iio_sw_rb_allocate(indio_dev);
- if (!ring) {
- ret = -ENOMEM;
- return ret;
- }
- indio_dev->ring = ring;
- /* Effectively select the ring buffer implementation */
- iio_ring_sw_register_funcs(&ring->access);
- ring->bpe = 2;
- ring->scan_el_attrs = &adis16300_scan_el_group;
- ring->scan_timestamp = true;
- ring->preenable = &iio_sw_ring_preenable;
- ring->postenable = &iio_triggered_ring_postenable;
- ring->predisable = &iio_triggered_ring_predisable;
- ring->owner = THIS_MODULE;
-
- /* Set default scan mode */
- iio_scan_mask_set(ring, iio_scan_el_in0_supply.number);
- iio_scan_mask_set(ring, iio_scan_el_gyro_x.number);
- iio_scan_mask_set(ring, iio_scan_el_accel_x.number);
- iio_scan_mask_set(ring, iio_scan_el_accel_y.number);
- iio_scan_mask_set(ring, iio_scan_el_accel_z.number);
- iio_scan_mask_set(ring, iio_scan_el_temp.number);
- iio_scan_mask_set(ring, iio_scan_el_in1.number);
- iio_scan_mask_set(ring, iio_scan_el_incli_x.number);
- iio_scan_mask_set(ring, iio_scan_el_incli_y.number);
-
- ret = iio_alloc_pollfunc(indio_dev, NULL, &adis16300_poll_func_th);
- if (ret)
- goto error_iio_sw_rb_free;
-
- indio_dev->modes |= INDIO_RING_TRIGGERED;
- return 0;
-
-error_iio_sw_rb_free:
- iio_sw_rb_free(indio_dev->ring);
- return ret;
-}
-
diff --git a/drivers/staging/iio/imu/adis16300_trigger.c b/drivers/staging/iio/imu/adis16300_trigger.c
deleted file mode 100644
index d6677b6..0000000
--- a/drivers/staging/iio/imu/adis16300_trigger.c
+++ /dev/null
@@ -1,125 +0,0 @@
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/mutex.h>
-#include <linux/device.h>
-#include <linux/kernel.h>
-#include <linux/sysfs.h>
-#include <linux/list.h>
-#include <linux/spi/spi.h>
-
-#include "../iio.h"
-#include "../sysfs.h"
-#include "../trigger.h"
-#include "adis16300.h"
-
-/**
- * adis16300_data_rdy_trig_poll() the event handler for the data rdy trig
- **/
-static int adis16300_data_rdy_trig_poll(struct iio_dev *dev_info,
- int index,
- s64 timestamp,
- int no_test)
-{
- struct adis16300_state *st = iio_dev_get_devdata(dev_info);
- struct iio_trigger *trig = st->trig;
-
- iio_trigger_poll(trig, timestamp);
-
- return IRQ_HANDLED;
-}
-
-IIO_EVENT_SH(data_rdy_trig, &adis16300_data_rdy_trig_poll);
-
-static IIO_TRIGGER_NAME_ATTR;
-
-static struct attribute *adis16300_trigger_attrs[] = {
- &dev_attr_name.attr,
- NULL,
-};
-
-static const struct attribute_group adis16300_trigger_attr_group = {
- .attrs = adis16300_trigger_attrs,
-};
-
-/**
- * adis16300_data_rdy_trigger_set_state() set datardy interrupt state
- **/
-static int adis16300_data_rdy_trigger_set_state(struct iio_trigger *trig,
- bool state)
-{
- struct adis16300_state *st = trig->private_data;
- struct iio_dev *indio_dev = st->indio_dev;
- int ret = 0;
-
- dev_dbg(&indio_dev->dev, "%s (%d)\n", __func__, state);
- ret = adis16300_set_irq(&st->indio_dev->dev, state);
- if (state == false) {
- iio_remove_event_from_list(&iio_event_data_rdy_trig,
- &indio_dev->interrupts[0]
- ->ev_list);
- /* possible quirk with handler currently worked around
- by ensuring the work queue is empty */
- flush_scheduled_work();
- } else {
- iio_add_event_to_list(&iio_event_data_rdy_trig,
- &indio_dev->interrupts[0]->ev_list);
- }
- return ret;
-}
-
-/**
- * adis16300_trig_try_reen() try renabling irq for data rdy trigger
- * @trig: the datardy trigger
- **/
-static int adis16300_trig_try_reen(struct iio_trigger *trig)
-{
- struct adis16300_state *st = trig->private_data;
- enable_irq(st->us->irq);
- /* irq reenabled so success! */
- return 0;
-}
-
-int adis16300_probe_trigger(struct iio_dev *indio_dev)
-{
- int ret;
- struct adis16300_state *st = indio_dev->dev_data;
-
- st->trig = iio_allocate_trigger();
- st->trig->name = kasprintf(GFP_KERNEL,
- "adis16300-dev%d",
- indio_dev->id);
- if (!st->trig->name) {
- ret = -ENOMEM;
- goto error_free_trig;
- }
- st->trig->dev.parent = &st->us->dev;
- st->trig->owner = THIS_MODULE;
- st->trig->private_data = st;
- st->trig->set_trigger_state = &adis16300_data_rdy_trigger_set_state;
- st->trig->try_reenable = &adis16300_trig_try_reen;
- st->trig->control_attrs = &adis16300_trigger_attr_group;
- ret = iio_trigger_register(st->trig);
-
- /* select default trigger */
- indio_dev->trig = st->trig;
- if (ret)
- goto error_free_trig_name;
-
- return 0;
-
-error_free_trig_name:
- kfree(st->trig->name);
-error_free_trig:
- iio_free_trigger(st->trig);
-
- return ret;
-}
-
-void adis16300_remove_trigger(struct iio_dev *indio_dev)
-{
- struct adis16300_state *state = indio_dev->dev_data;
-
- iio_trigger_unregister(state->trig);
- kfree(state->trig->name);
- iio_free_trigger(state->trig);
-}
diff --git a/drivers/staging/iio/imu/adis16350.h b/drivers/staging/iio/imu/adis16350.h
deleted file mode 100644
index b1ad486..0000000
--- a/drivers/staging/iio/imu/adis16350.h
+++ /dev/null
@@ -1,177 +0,0 @@
-#ifndef SPI_ADIS16350_H_
-#define SPI_ADIS16350_H_
-
-#define ADIS16350_STARTUP_DELAY 220 /* ms */
-
-#define ADIS16350_READ_REG(a) a
-#define ADIS16350_WRITE_REG(a) ((a) | 0x80)
-
-#define ADIS16350_FLASH_CNT 0x00 /* Flash memory write count */
-#define ADIS16350_SUPPLY_OUT 0x02 /* Power supply measurement */
-#define ADIS16350_XGYRO_OUT 0x04 /* X-axis gyroscope output */
-#define ADIS16350_YGYRO_OUT 0x06 /* Y-axis gyroscope output */
-#define ADIS16350_ZGYRO_OUT 0x08 /* Z-axis gyroscope output */
-#define ADIS16350_XACCL_OUT 0x0A /* X-axis accelerometer output */
-#define ADIS16350_YACCL_OUT 0x0C /* Y-axis accelerometer output */
-#define ADIS16350_ZACCL_OUT 0x0E /* Z-axis accelerometer output */
-#define ADIS16350_XTEMP_OUT 0x10 /* X-axis gyroscope temperature measurement */
-#define ADIS16350_YTEMP_OUT 0x12 /* Y-axis gyroscope temperature measurement */
-#define ADIS16350_ZTEMP_OUT 0x14 /* Z-axis gyroscope temperature measurement */
-#define ADIS16350_AUX_ADC 0x16 /* Auxiliary ADC measurement */
-
-/* Calibration parameters */
-#define ADIS16350_XGYRO_OFF 0x1A /* X-axis gyroscope bias offset factor */
-#define ADIS16350_YGYRO_OFF 0x1C /* Y-axis gyroscope bias offset factor */
-#define ADIS16350_ZGYRO_OFF 0x1E /* Z-axis gyroscope bias offset factor */
-#define ADIS16350_XACCL_OFF 0x20 /* X-axis acceleration bias offset factor */
-#define ADIS16350_YACCL_OFF 0x22 /* Y-axis acceleration bias offset factor */
-#define ADIS16350_ZACCL_OFF 0x24 /* Z-axis acceleration bias offset factor */
-
-#define ADIS16350_GPIO_CTRL 0x32 /* Auxiliary digital input/output control */
-#define ADIS16350_MSC_CTRL 0x34 /* Miscellaneous control */
-#define ADIS16350_SMPL_PRD 0x36 /* Internal sample period (rate) control */
-#define ADIS16350_SENS_AVG 0x38 /* Dynamic range and digital filter control */
-#define ADIS16350_SLP_CNT 0x3A /* Sleep mode control */
-#define ADIS16350_DIAG_STAT 0x3C /* System status */
-
-/* Alarm functions */
-#define ADIS16350_GLOB_CMD 0x3E /* System command */
-#define ADIS16350_ALM_MAG1 0x26 /* Alarm 1 amplitude threshold */
-#define ADIS16350_ALM_MAG2 0x28 /* Alarm 2 amplitude threshold */
-#define ADIS16350_ALM_SMPL1 0x2A /* Alarm 1 sample size */
-#define ADIS16350_ALM_SMPL2 0x2C /* Alarm 2 sample size */
-#define ADIS16350_ALM_CTRL 0x2E /* Alarm control */
-#define ADIS16350_AUX_DAC 0x30 /* Auxiliary DAC data */
-
-#define ADIS16350_ERROR_ACTIVE (1<<14)
-#define ADIS16350_NEW_DATA (1<<15)
-
-/* MSC_CTRL */
-#define ADIS16350_MSC_CTRL_MEM_TEST (1<<11)
-#define ADIS16350_MSC_CTRL_INT_SELF_TEST (1<<10)
-#define ADIS16350_MSC_CTRL_NEG_SELF_TEST (1<<9)
-#define ADIS16350_MSC_CTRL_POS_SELF_TEST (1<<8)
-#define ADIS16350_MSC_CTRL_GYRO_BIAS (1<<7)
-#define ADIS16350_MSC_CTRL_ACCL_ALIGN (1<<6)
-#define ADIS16350_MSC_CTRL_DATA_RDY_EN (1<<2)
-#define ADIS16350_MSC_CTRL_DATA_RDY_POL_HIGH (1<<1)
-#define ADIS16350_MSC_CTRL_DATA_RDY_DIO2 (1<<0)
-
-/* SMPL_PRD */
-#define ADIS16350_SMPL_PRD_TIME_BASE (1<<7)
-#define ADIS16350_SMPL_PRD_DIV_MASK 0x7F
-
-/* DIAG_STAT */
-#define ADIS16350_DIAG_STAT_ZACCL_FAIL (1<<15)
-#define ADIS16350_DIAG_STAT_YACCL_FAIL (1<<14)
-#define ADIS16350_DIAG_STAT_XACCL_FAIL (1<<13)
-#define ADIS16350_DIAG_STAT_XGYRO_FAIL (1<<12)
-#define ADIS16350_DIAG_STAT_YGYRO_FAIL (1<<11)
-#define ADIS16350_DIAG_STAT_ZGYRO_FAIL (1<<10)
-#define ADIS16350_DIAG_STAT_ALARM2 (1<<9)
-#define ADIS16350_DIAG_STAT_ALARM1 (1<<8)
-#define ADIS16350_DIAG_STAT_FLASH_CHK (1<<6)
-#define ADIS16350_DIAG_STAT_SELF_TEST (1<<5)
-#define ADIS16350_DIAG_STAT_OVERFLOW (1<<4)
-#define ADIS16350_DIAG_STAT_SPI_FAIL (1<<3)
-#define ADIS16350_DIAG_STAT_FLASH_UPT (1<<2)
-#define ADIS16350_DIAG_STAT_POWER_HIGH (1<<1)
-#define ADIS16350_DIAG_STAT_POWER_LOW (1<<0)
-
-/* GLOB_CMD */
-#define ADIS16350_GLOB_CMD_SW_RESET (1<<7)
-#define ADIS16350_GLOB_CMD_P_AUTO_NULL (1<<4)
-#define ADIS16350_GLOB_CMD_FLASH_UPD (1<<3)
-#define ADIS16350_GLOB_CMD_DAC_LATCH (1<<2)
-#define ADIS16350_GLOB_CMD_FAC_CALIB (1<<1)
-#define ADIS16350_GLOB_CMD_AUTO_NULL (1<<0)
-
-/* SLP_CNT */
-#define ADIS16350_SLP_CNT_POWER_OFF (1<<8)
-
-#define ADIS16350_MAX_TX 24
-#define ADIS16350_MAX_RX 24
-
-#define ADIS16350_SPI_SLOW (u32)(300 * 1000)
-#define ADIS16350_SPI_BURST (u32)(1000 * 1000)
-#define ADIS16350_SPI_FAST (u32)(2000 * 1000)
-
-/**
- * struct adis16350_state - device instance specific data
- * @us: actual spi_device
- * @work_trigger_to_ring: bh for triggered event handling
- * @inter: used to check if new interrupt has been triggered
- * @last_timestamp: passing timestamp from th to bh of interrupt handler
- * @indio_dev: industrial I/O device structure
- * @trig: data ready trigger registered with iio
- * @tx: transmit buffer
- * @rx: receive buffer
- * @buf_lock: mutex to protect tx and rx
- **/
-struct adis16350_state {
- struct spi_device *us;
- struct work_struct work_trigger_to_ring;
- s64 last_timestamp;
- struct iio_dev *indio_dev;
- struct iio_trigger *trig;
- u8 *tx;
- u8 *rx;
- struct mutex buf_lock;
-};
-
-int adis16350_set_irq(struct device *dev, bool enable);
-
-#ifdef CONFIG_IIO_RING_BUFFER
-
-#define ADIS16350_SCAN_SUPPLY 0
-#define ADIS16350_SCAN_GYRO_X 1
-#define ADIS16350_SCAN_GYRO_Y 2
-#define ADIS16350_SCAN_GYRO_Z 3
-#define ADIS16350_SCAN_ACC_X 4
-#define ADIS16350_SCAN_ACC_Y 5
-#define ADIS16350_SCAN_ACC_Z 6
-#define ADIS16350_SCAN_TEMP_X 7
-#define ADIS16350_SCAN_TEMP_Y 8
-#define ADIS16350_SCAN_TEMP_Z 9
-#define ADIS16350_SCAN_ADC_0 10
-
-void adis16350_remove_trigger(struct iio_dev *indio_dev);
-int adis16350_probe_trigger(struct iio_dev *indio_dev);
-
-ssize_t adis16350_read_data_from_ring(struct device *dev,
- struct device_attribute *attr,
- char *buf);
-
-
-int adis16350_configure_ring(struct iio_dev *indio_dev);
-void adis16350_unconfigure_ring(struct iio_dev *indio_dev);
-
-#else /* CONFIG_IIO_RING_BUFFER */
-
-static inline void adis16350_remove_trigger(struct iio_dev *indio_dev)
-{
-}
-
-static inline int adis16350_probe_trigger(struct iio_dev *indio_dev)
-{
- return 0;
-}
-
-static inline ssize_t
-adis16350_read_data_from_ring(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- return 0;
-}
-
-static inline int adis16350_configure_ring(struct iio_dev *indio_dev)
-{
- return 0;
-}
-
-static inline void adis16350_unconfigure_ring(struct iio_dev *indio_dev)
-{
-}
-#endif /* CONFIG_IIO_RING_BUFFER */
-#endif /* SPI_ADIS16350_H_ */
diff --git a/drivers/staging/iio/imu/adis16350_core.c b/drivers/staging/iio/imu/adis16350_core.c
deleted file mode 100644
index cf7176b..0000000
--- a/drivers/staging/iio/imu/adis16350_core.c
+++ /dev/null
@@ -1,757 +0,0 @@
-/*
- * ADIS16350/54/55/60/62/64/65 high precision tri-axis inertial sensor
- *
- * Copyright 2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/gpio.h>
-#include <linux/delay.h>
-#include <linux/mutex.h>
-#include <linux/device.h>
-#include <linux/kernel.h>
-#include <linux/spi/spi.h>
-#include <linux/slab.h>
-#include <linux/sysfs.h>
-#include <linux/list.h>
-
-#include "../iio.h"
-#include "../sysfs.h"
-#include "../ring_generic.h"
-#include "../accel/accel.h"
-#include "../adc/adc.h"
-#include "../gyro/gyro.h"
-
-#include "adis16350.h"
-
-#define DRIVER_NAME "adis16350"
-
-static int adis16350_check_status(struct device *dev);
-
-/**
- * adis16350_spi_write_reg_8() - write single byte to a register
- * @dev: device associated with child of actual device (iio_dev or iio_trig)
- * @reg_address: the address of the register to be written
- * @val: the value to write
- **/
-static int adis16350_spi_write_reg_8(struct device *dev,
- u8 reg_address,
- u8 val)
-{
- int ret;
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
- struct adis16350_state *st = iio_dev_get_devdata(indio_dev);
-
- mutex_lock(&st->buf_lock);
- st->tx[0] = ADIS16350_WRITE_REG(reg_address);
- st->tx[1] = val;
-
- ret = spi_write(st->us, st->tx, 2);
- mutex_unlock(&st->buf_lock);
-
- return ret;
-}
-
-/**
- * adis16350_spi_write_reg_16() - write 2 bytes to a pair of registers
- * @dev: device associated with child of actual device (iio_dev or iio_trig)
- * @reg_address: the address of the lower of the two registers. Second register
- * is assumed to have address one greater.
- * @val: value to be written
- **/
-static int adis16350_spi_write_reg_16(struct device *dev,
- u8 lower_reg_address,
- u16 value)
-{
- int ret;
- struct spi_message msg;
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
- struct adis16350_state *st = iio_dev_get_devdata(indio_dev);
- struct spi_transfer xfers[] = {
- {
- .tx_buf = st->tx,
- .bits_per_word = 8,
- .len = 2,
- .cs_change = 1,
- .delay_usecs = 35,
- }, {
- .tx_buf = st->tx + 2,
- .bits_per_word = 8,
- .len = 2,
- .cs_change = 1,
- .delay_usecs = 35,
- },
- };
-
- mutex_lock(&st->buf_lock);
- st->tx[0] = ADIS16350_WRITE_REG(lower_reg_address);
- st->tx[1] = value & 0xFF;
- st->tx[2] = ADIS16350_WRITE_REG(lower_reg_address + 1);
- st->tx[3] = (value >> 8) & 0xFF;
-
- spi_message_init(&msg);
- spi_message_add_tail(&xfers[0], &msg);
- spi_message_add_tail(&xfers[1], &msg);
- ret = spi_sync(st->us, &msg);
- mutex_unlock(&st->buf_lock);
-
- return ret;
-}
-
-/**
- * adis16350_spi_read_reg_16() - read 2 bytes from a 16-bit register
- * @dev: device associated with child of actual device (iio_dev or iio_trig)
- * @reg_address: the address of the lower of the two registers. Second register
- * is assumed to have address one greater.
- * @val: somewhere to pass back the value read
- **/
-static int adis16350_spi_read_reg_16(struct device *dev,
- u8 lower_reg_address,
- u16 *val)
-{
- struct spi_message msg;
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
- struct adis16350_state *st = iio_dev_get_devdata(indio_dev);
- int ret;
- struct spi_transfer xfers[] = {
- {
- .tx_buf = st->tx,
- .bits_per_word = 8,
- .len = 2,
- .cs_change = 1,
- .delay_usecs = 35,
- }, {
- .rx_buf = st->rx,
- .bits_per_word = 8,
- .len = 2,
- .cs_change = 1,
- .delay_usecs = 35,
- },
- };
-
- mutex_lock(&st->buf_lock);
- st->tx[0] = ADIS16350_READ_REG(lower_reg_address);
- st->tx[1] = 0;
- st->tx[2] = 0;
- st->tx[3] = 0;
-
- spi_message_init(&msg);
- spi_message_add_tail(&xfers[0], &msg);
- spi_message_add_tail(&xfers[1], &msg);
- ret = spi_sync(st->us, &msg);
- if (ret) {
- dev_err(&st->us->dev,
- "problem when reading 16 bit register 0x%02X",
- lower_reg_address);
- goto error_ret;
- }
- *val = (st->rx[0] << 8) | st->rx[1];
-
-error_ret:
- mutex_unlock(&st->buf_lock);
- return ret;
-}
-
-
-static ssize_t adis16350_spi_read_signed(struct device *dev,
- struct device_attribute *attr,
- char *buf,
- unsigned bits)
-{
- int ret;
- s16 val = 0;
- unsigned shift = 16 - bits;
- struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
-
- ret = adis16350_spi_read_reg_16(dev, this_attr->address, (u16 *)&val);
- if (ret)
- return ret;
-
- if (val & ADIS16350_ERROR_ACTIVE)
- adis16350_check_status(dev);
- val = ((s16)(val << shift) >> shift);
- return sprintf(buf, "%d\n", val);
-}
-
-static ssize_t adis16350_read_12bit_unsigned(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- int ret;
- u16 val = 0;
- struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
-
- ret = adis16350_spi_read_reg_16(dev, this_attr->address, &val);
- if (ret)
- return ret;
-
- if (val & ADIS16350_ERROR_ACTIVE)
- adis16350_check_status(dev);
-
- return sprintf(buf, "%u\n", val & 0x0FFF);
-}
-
-static ssize_t adis16350_read_14bit_signed(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
- ssize_t ret;
-
- /* Take the iio_dev status lock */
- mutex_lock(&indio_dev->mlock);
- ret = adis16350_spi_read_signed(dev, attr, buf, 14);
- mutex_unlock(&indio_dev->mlock);
-
- return ret;
-}
-
-static ssize_t adis16350_read_12bit_signed(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
- ssize_t ret;
-
- /* Take the iio_dev status lock */
- mutex_lock(&indio_dev->mlock);
- ret = adis16350_spi_read_signed(dev, attr, buf, 12);
- mutex_unlock(&indio_dev->mlock);
-
- return ret;
-}
-
-static ssize_t adis16350_write_16bit(struct device *dev,
- struct device_attribute *attr,
- const char *buf,
- size_t len)
-{
- struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
- int ret;
- long val;
-
- ret = strict_strtol(buf, 10, &val);
- if (ret)
- goto error_ret;
- ret = adis16350_spi_write_reg_16(dev, this_attr->address, val);
-
-error_ret:
- return ret ? ret : len;
-}
-
-static ssize_t adis16350_read_frequency(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- int ret, len = 0;
- u16 t;
- int sps;
- ret = adis16350_spi_read_reg_16(dev,
- ADIS16350_SMPL_PRD,
- &t);
- if (ret)
- return ret;
- sps = (t & ADIS16350_SMPL_PRD_TIME_BASE) ? 53 : 1638;
- sps /= (t & ADIS16350_SMPL_PRD_DIV_MASK) + 1;
- len = sprintf(buf, "%d SPS\n", sps);
- return len;
-}
-
-static ssize_t adis16350_write_frequency(struct device *dev,
- struct device_attribute *attr,
- const char *buf,
- size_t len)
-{
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
- struct adis16350_state *st = iio_dev_get_devdata(indio_dev);
- long val;
- int ret;
- u8 t;
-
- ret = strict_strtol(buf, 10, &val);
- if (ret)
- return ret;
-
- mutex_lock(&indio_dev->mlock);
-
- t = (1638 / val);
- if (t > 0)
- t--;
- t &= ADIS16350_SMPL_PRD_DIV_MASK;
- if ((t & ADIS16350_SMPL_PRD_DIV_MASK) >= 0x0A)
- st->us->max_speed_hz = ADIS16350_SPI_SLOW;
- else
- st->us->max_speed_hz = ADIS16350_SPI_FAST;
-
- ret = adis16350_spi_write_reg_8(dev,
- ADIS16350_SMPL_PRD,
- t);
-
- mutex_unlock(&indio_dev->mlock);
-
- return ret ? ret : len;
-}
-
-static int adis16350_reset(struct device *dev)
-{
- int ret;
- ret = adis16350_spi_write_reg_8(dev,
- ADIS16350_GLOB_CMD,
- ADIS16350_GLOB_CMD_SW_RESET);
- if (ret)
- dev_err(dev, "problem resetting device");
-
- return ret;
-}
-
-static ssize_t adis16350_write_reset(struct device *dev,
- struct device_attribute *attr,
- const char *buf, size_t len)
-{
- if (len < 1)
- return -1;
- switch (buf[0]) {
- case '1':
- case 'y':
- case 'Y':
- return adis16350_reset(dev);
- }
- return -1;
-}
-
-int adis16350_set_irq(struct device *dev, bool enable)
-{
- int ret;
- u16 msc;
- ret = adis16350_spi_read_reg_16(dev, ADIS16350_MSC_CTRL, &msc);
- if (ret)
- goto error_ret;
-
- msc |= ADIS16350_MSC_CTRL_DATA_RDY_POL_HIGH;
- msc &= ~ADIS16350_MSC_CTRL_DATA_RDY_DIO2;
-
- if (enable)
- msc |= ADIS16350_MSC_CTRL_DATA_RDY_EN;
- else
- msc &= ~ADIS16350_MSC_CTRL_DATA_RDY_EN;
-
- ret = adis16350_spi_write_reg_16(dev, ADIS16350_MSC_CTRL, msc);
- if (ret)
- goto error_ret;
-
-error_ret:
- return ret;
-}
-
-/* Power down the device */
-static int adis16350_stop_device(struct device *dev)
-{
- int ret;
- u16 val = ADIS16350_SLP_CNT_POWER_OFF;
-
- ret = adis16350_spi_write_reg_16(dev, ADIS16350_SLP_CNT, val);
- if (ret)
- dev_err(dev, "problem with turning device off: SLP_CNT");
-
- return ret;
-}
-
-static int adis16350_self_test(struct device *dev)
-{
- int ret;
- ret = adis16350_spi_write_reg_16(dev,
- ADIS16350_MSC_CTRL,
- ADIS16350_MSC_CTRL_MEM_TEST);
- if (ret) {
- dev_err(dev, "problem starting self test");
- goto err_ret;
- }
-
- adis16350_check_status(dev);
-
-err_ret:
- return ret;
-}
-
-static int adis16350_check_status(struct device *dev)
-{
- u16 status;
- int ret;
-
- ret = adis16350_spi_read_reg_16(dev, ADIS16350_DIAG_STAT, &status);
-
- if (ret < 0) {
- dev_err(dev, "Reading status failed\n");
- goto error_ret;
- }
- ret = status;
- if (status & ADIS16350_DIAG_STAT_ZACCL_FAIL)
- dev_err(dev, "Z-axis accelerometer self-test failure\n");
- if (status & ADIS16350_DIAG_STAT_YACCL_FAIL)
- dev_err(dev, "Y-axis accelerometer self-test failure\n");
- if (status & ADIS16350_DIAG_STAT_XACCL_FAIL)
- dev_err(dev, "X-axis accelerometer self-test failure\n");
- if (status & ADIS16350_DIAG_STAT_XGYRO_FAIL)
- dev_err(dev, "X-axis gyroscope self-test failure\n");
- if (status & ADIS16350_DIAG_STAT_YGYRO_FAIL)
- dev_err(dev, "Y-axis gyroscope self-test failure\n");
- if (status & ADIS16350_DIAG_STAT_ZGYRO_FAIL)
- dev_err(dev, "Z-axis gyroscope self-test failure\n");
- if (status & ADIS16350_DIAG_STAT_ALARM2)
- dev_err(dev, "Alarm 2 active\n");
- if (status & ADIS16350_DIAG_STAT_ALARM1)
- dev_err(dev, "Alarm 1 active\n");
- if (status & ADIS16350_DIAG_STAT_FLASH_CHK)
- dev_err(dev, "Flash checksum error\n");
- if (status & ADIS16350_DIAG_STAT_SELF_TEST)
- dev_err(dev, "Self test error\n");
- if (status & ADIS16350_DIAG_STAT_OVERFLOW)
- dev_err(dev, "Sensor overrange\n");
- if (status & ADIS16350_DIAG_STAT_SPI_FAIL)
- dev_err(dev, "SPI failure\n");
- if (status & ADIS16350_DIAG_STAT_FLASH_UPT)
- dev_err(dev, "Flash update failed\n");
- if (status & ADIS16350_DIAG_STAT_POWER_HIGH)
- dev_err(dev, "Power supply above 5.25V\n");
- if (status & ADIS16350_DIAG_STAT_POWER_LOW)
- dev_err(dev, "Power supply below 4.75V\n");
-
-error_ret:
- return ret;
-}
-
-static int adis16350_initial_setup(struct adis16350_state *st)
-{
- int ret;
- u16 smp_prd;
- struct device *dev = &st->indio_dev->dev;
-
- /* use low spi speed for init */
- st->us->max_speed_hz = ADIS16350_SPI_SLOW;
- st->us->mode = SPI_MODE_3;
- spi_setup(st->us);
-
- /* Disable IRQ */
- ret = adis16350_set_irq(dev, false);
- if (ret) {
- dev_err(dev, "disable irq failed");
- goto err_ret;
- }
-
- /* Do self test */
- ret = adis16350_self_test(dev);
- if (ret) {
- dev_err(dev, "self test failure");
- goto err_ret;
- }
-
- /* Read status register to check the result */
- ret = adis16350_check_status(dev);
- if (ret) {
- adis16350_reset(dev);
- dev_err(dev, "device not playing ball -> reset");
- msleep(ADIS16350_STARTUP_DELAY);
- ret = adis16350_check_status(dev);
- if (ret) {
- dev_err(dev, "giving up");
- goto err_ret;
- }
- }
-
- printk(KERN_INFO DRIVER_NAME ": at CS%d (irq %d)\n",
- st->us->chip_select, st->us->irq);
-
- /* use high spi speed if possible */
- ret = adis16350_spi_read_reg_16(dev, ADIS16350_SMPL_PRD, &smp_prd);
- if (!ret && (smp_prd & ADIS16350_SMPL_PRD_DIV_MASK) < 0x0A) {
- st->us->max_speed_hz = ADIS16350_SPI_SLOW;
- spi_setup(st->us);
- }
-
-err_ret:
- return ret;
-}
-
-static IIO_DEV_ATTR_GYRO_X_CALIBBIAS(S_IWUSR | S_IRUGO,
- adis16350_read_12bit_signed,
- adis16350_write_16bit,
- ADIS16350_XGYRO_OFF);
-
-static IIO_DEV_ATTR_GYRO_Y_CALIBBIAS(S_IWUSR | S_IRUGO,
- adis16350_read_12bit_signed,
- adis16350_write_16bit,
- ADIS16350_YGYRO_OFF);
-
-static IIO_DEV_ATTR_GYRO_Z_CALIBBIAS(S_IWUSR | S_IRUGO,
- adis16350_read_12bit_signed,
- adis16350_write_16bit,
- ADIS16350_ZGYRO_OFF);
-
-static IIO_DEV_ATTR_ACCEL_X_CALIBBIAS(S_IWUSR | S_IRUGO,
- adis16350_read_12bit_signed,
- adis16350_write_16bit,
- ADIS16350_XACCL_OFF);
-
-static IIO_DEV_ATTR_ACCEL_Y_CALIBBIAS(S_IWUSR | S_IRUGO,
- adis16350_read_12bit_signed,
- adis16350_write_16bit,
- ADIS16350_YACCL_OFF);
-
-static IIO_DEV_ATTR_ACCEL_Z_CALIBBIAS(S_IWUSR | S_IRUGO,
- adis16350_read_12bit_signed,
- adis16350_write_16bit,
- ADIS16350_ZACCL_OFF);
-
-static IIO_DEV_ATTR_IN_NAMED_RAW(0, supply, adis16350_read_12bit_unsigned,
- ADIS16350_SUPPLY_OUT);
-static IIO_CONST_ATTR_IN_NAMED_SCALE(0, supply, "0.002418");
-
-static IIO_DEV_ATTR_GYRO_X(adis16350_read_14bit_signed,
- ADIS16350_XGYRO_OUT);
-static IIO_DEV_ATTR_GYRO_Y(adis16350_read_14bit_signed,
- ADIS16350_YGYRO_OUT);
-static IIO_DEV_ATTR_GYRO_Z(adis16350_read_14bit_signed,
- ADIS16350_ZGYRO_OUT);
-static IIO_CONST_ATTR_GYRO_SCALE("0.00127862821");
-
-static IIO_DEV_ATTR_ACCEL_X(adis16350_read_14bit_signed,
- ADIS16350_XACCL_OUT);
-static IIO_DEV_ATTR_ACCEL_Y(adis16350_read_14bit_signed,
- ADIS16350_YACCL_OUT);
-static IIO_DEV_ATTR_ACCEL_Z(adis16350_read_14bit_signed,
- ADIS16350_ZACCL_OUT);
-static IIO_CONST_ATTR_ACCEL_SCALE("0.0247323713");
-
-static IIO_DEVICE_ATTR(temp_x_raw, S_IRUGO, adis16350_read_12bit_signed,
- NULL, ADIS16350_XTEMP_OUT);
-static IIO_DEVICE_ATTR(temp_y_raw, S_IRUGO, adis16350_read_12bit_signed,
- NULL, ADIS16350_YTEMP_OUT);
-static IIO_DEVICE_ATTR(temp_z_raw, S_IRUGO, adis16350_read_12bit_signed,
- NULL, ADIS16350_ZTEMP_OUT);
-static IIO_CONST_ATTR_TEMP_SCALE("0.14534");
-static IIO_CONST_ATTR_TEMP_OFFSET("198.16");
-
-static IIO_DEV_ATTR_IN_RAW(1, adis16350_read_12bit_unsigned,
- ADIS16350_AUX_ADC);
-static IIO_CONST_ATTR(in1_scale, "0.000806");
-
-static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO,
- adis16350_read_frequency,
- adis16350_write_frequency);
-
-static IIO_DEVICE_ATTR(reset, S_IWUSR, NULL,
- adis16350_write_reset, 0);
-
-static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("409 546 819 1638");
-
-static IIO_CONST_ATTR_NAME("adis16350");
-
-static struct attribute *adis16350_attributes[] = {
- &iio_dev_attr_gyro_x_calibbias.dev_attr.attr,
- &iio_dev_attr_gyro_y_calibbias.dev_attr.attr,
- &iio_dev_attr_gyro_z_calibbias.dev_attr.attr,
- &iio_dev_attr_accel_x_calibbias.dev_attr.attr,
- &iio_dev_attr_accel_y_calibbias.dev_attr.attr,
- &iio_dev_attr_accel_z_calibbias.dev_attr.attr,
- &iio_dev_attr_in0_supply_raw.dev_attr.attr,
- &iio_const_attr_in0_supply_scale.dev_attr.attr,
- &iio_dev_attr_gyro_x_raw.dev_attr.attr,
- &iio_dev_attr_gyro_y_raw.dev_attr.attr,
- &iio_dev_attr_gyro_z_raw.dev_attr.attr,
- &iio_const_attr_gyro_scale.dev_attr.attr,
- &iio_dev_attr_accel_x_raw.dev_attr.attr,
- &iio_dev_attr_accel_y_raw.dev_attr.attr,
- &iio_dev_attr_accel_z_raw.dev_attr.attr,
- &iio_const_attr_accel_scale.dev_attr.attr,
- &iio_dev_attr_temp_x_raw.dev_attr.attr,
- &iio_dev_attr_temp_y_raw.dev_attr.attr,
- &iio_dev_attr_temp_z_raw.dev_attr.attr,
- &iio_const_attr_temp_scale.dev_attr.attr,
- &iio_const_attr_temp_offset.dev_attr.attr,
- &iio_dev_attr_in1_raw.dev_attr.attr,
- &iio_const_attr_in1_scale.dev_attr.attr,
- &iio_dev_attr_sampling_frequency.dev_attr.attr,
- &iio_const_attr_sampling_frequency_available.dev_attr.attr,
- &iio_dev_attr_reset.dev_attr.attr,
- &iio_const_attr_name.dev_attr.attr,
- NULL
-};
-
-static const struct attribute_group adis16350_attribute_group = {
- .attrs = adis16350_attributes,
-};
-
-static struct attribute *adis16350_event_attributes[] = {
- NULL,
-};
-
-static struct attribute_group adis16350_event_attribute_group = {
- .attrs = adis16350_event_attributes,
-};
-
-static int __devinit adis16350_probe(struct spi_device *spi)
-{
- int ret, regdone = 0;
- struct adis16350_state *st = kzalloc(sizeof *st, GFP_KERNEL);
- if (!st) {
- ret = -ENOMEM;
- goto error_ret;
- }
- /* this is only used for removal purposes */
- spi_set_drvdata(spi, st);
-
- /* Allocate the comms buffers */
- st->rx = kzalloc(sizeof(*st->rx)*ADIS16350_MAX_RX, GFP_KERNEL);
- if (st->rx == NULL) {
- ret = -ENOMEM;
- goto error_free_st;
- }
- st->tx = kzalloc(sizeof(*st->tx)*ADIS16350_MAX_TX, GFP_KERNEL);
- if (st->tx == NULL) {
- ret = -ENOMEM;
- goto error_free_rx;
- }
- st->us = spi;
- mutex_init(&st->buf_lock);
- /* setup the industrialio driver allocated elements */
- st->indio_dev = iio_allocate_device();
- if (st->indio_dev == NULL) {
- ret = -ENOMEM;
- goto error_free_tx;
- }
-
- st->indio_dev->dev.parent = &spi->dev;
- st->indio_dev->num_interrupt_lines = 1;
- st->indio_dev->event_attrs = &adis16350_event_attribute_group;
- st->indio_dev->attrs = &adis16350_attribute_group;
- st->indio_dev->dev_data = (void *)(st);
- st->indio_dev->driver_module = THIS_MODULE;
- st->indio_dev->modes = INDIO_DIRECT_MODE;
-
- ret = adis16350_configure_ring(st->indio_dev);
- if (ret)
- goto error_free_dev;
-
- ret = iio_device_register(st->indio_dev);
- if (ret)
- goto error_unreg_ring_funcs;
- regdone = 1;
-
- ret = iio_ring_buffer_register(st->indio_dev->ring, 0);
- if (ret) {
- printk(KERN_ERR "failed to initialize the ring\n");
- goto error_unreg_ring_funcs;
- }
-
- if (spi->irq) {
- ret = iio_register_interrupt_line(spi->irq,
- st->indio_dev,
- 0,
- IRQF_TRIGGER_RISING,
- "adis16350");
- if (ret)
- goto error_uninitialize_ring;
-
- ret = adis16350_probe_trigger(st->indio_dev);
- if (ret)
- goto error_unregister_line;
- }
-
- /* Get the device into a sane initial state */
- ret = adis16350_initial_setup(st);
- if (ret)
- goto error_remove_trigger;
- return 0;
-
-error_remove_trigger:
- adis16350_remove_trigger(st->indio_dev);
-error_unregister_line:
- if (spi->irq)
- iio_unregister_interrupt_line(st->indio_dev, 0);
-error_uninitialize_ring:
- iio_ring_buffer_unregister(st->indio_dev->ring);
-error_unreg_ring_funcs:
- adis16350_unconfigure_ring(st->indio_dev);
-error_free_dev:
- if (regdone)
- iio_device_unregister(st->indio_dev);
- else
- iio_free_device(st->indio_dev);
-error_free_tx:
- kfree(st->tx);
-error_free_rx:
- kfree(st->rx);
-error_free_st:
- kfree(st);
-error_ret:
- return ret;
-}
-
-static int adis16350_remove(struct spi_device *spi)
-{
- int ret;
- struct adis16350_state *st = spi_get_drvdata(spi);
- struct iio_dev *indio_dev = st->indio_dev;
-
- ret = adis16350_stop_device(&(indio_dev->dev));
- if (ret)
- goto err_ret;
-
- flush_scheduled_work();
-
- adis16350_remove_trigger(indio_dev);
- if (spi->irq)
- iio_unregister_interrupt_line(indio_dev, 0);
-
- iio_ring_buffer_unregister(indio_dev->ring);
- iio_device_unregister(indio_dev);
- adis16350_unconfigure_ring(indio_dev);
- kfree(st->tx);
- kfree(st->rx);
- kfree(st);
-
- return 0;
-
-err_ret:
- return ret;
-}
-
-static const struct spi_device_id adis16350_id[] = {
- {"adis16350", 0},
- {"adis16354", 0},
- {"adis16355", 0},
- {"adis16360", 0},
- {"adis16362", 0},
- {"adis16364", 0},
- {"adis16365", 0},
- {}
-};
-
-static struct spi_driver adis16350_driver = {
- .driver = {
- .name = "adis16350",
- .owner = THIS_MODULE,
- },
- .probe = adis16350_probe,
- .remove = __devexit_p(adis16350_remove),
- .id_table = adis16350_id,
-};
-
-static __init int adis16350_init(void)
-{
- return spi_register_driver(&adis16350_driver);
-}
-module_init(adis16350_init);
-
-static __exit void adis16350_exit(void)
-{
- spi_unregister_driver(&adis16350_driver);
-}
-module_exit(adis16350_exit);
-
-MODULE_AUTHOR("Barry Song <21cnbao@gmail.com>");
-MODULE_DESCRIPTION("Analog Devices ADIS16350/54/55/60/62/64/65 IMU SPI driver");
-MODULE_LICENSE("GPL v2");
diff --git a/drivers/staging/iio/imu/adis16350_ring.c b/drivers/staging/iio/imu/adis16350_ring.c
deleted file mode 100644
index 56b70cf..0000000
--- a/drivers/staging/iio/imu/adis16350_ring.c
+++ /dev/null
@@ -1,236 +0,0 @@
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/gpio.h>
-#include <linux/workqueue.h>
-#include <linux/mutex.h>
-#include <linux/device.h>
-#include <linux/kernel.h>
-#include <linux/spi/spi.h>
-#include <linux/slab.h>
-#include <linux/sysfs.h>
-#include <linux/list.h>
-
-#include "../iio.h"
-#include "../sysfs.h"
-#include "../ring_sw.h"
-#include "../accel/accel.h"
-#include "../trigger.h"
-#include "adis16350.h"
-
-static IIO_SCAN_EL_C(in0_supply, ADIS16350_SCAN_SUPPLY,
- ADIS16350_SUPPLY_OUT, NULL);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(in0_supply, u, 12, 16);
-
-static IIO_SCAN_EL_C(gyro_x, ADIS16350_SCAN_GYRO_X, ADIS16350_XGYRO_OUT, NULL);
-static IIO_SCAN_EL_C(gyro_y, ADIS16350_SCAN_GYRO_Y, ADIS16350_YGYRO_OUT, NULL);
-static IIO_SCAN_EL_C(gyro_z, ADIS16350_SCAN_GYRO_Z, ADIS16350_ZGYRO_OUT, NULL);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(gyro, s, 14, 16);
-
-static IIO_SCAN_EL_C(accel_x, ADIS16350_SCAN_ACC_X, ADIS16350_XACCL_OUT, NULL);
-static IIO_SCAN_EL_C(accel_y, ADIS16350_SCAN_ACC_Y, ADIS16350_YACCL_OUT, NULL);
-static IIO_SCAN_EL_C(accel_z, ADIS16350_SCAN_ACC_Z, ADIS16350_ZACCL_OUT, NULL);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(accel, s, 14, 16);
-
-static IIO_SCAN_EL_C(temp_x, ADIS16350_SCAN_TEMP_X, ADIS16350_XTEMP_OUT, NULL);
-static IIO_SCAN_EL_C(temp_y, ADIS16350_SCAN_TEMP_Y, ADIS16350_YTEMP_OUT, NULL);
-static IIO_SCAN_EL_C(temp_z, ADIS16350_SCAN_TEMP_Z, ADIS16350_ZTEMP_OUT, NULL);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(temp, s, 12, 16);
-
-static IIO_SCAN_EL_C(in1, ADIS16350_SCAN_ADC_0, ADIS16350_AUX_ADC, NULL);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(in1, u, 12, 16);
-
-static IIO_SCAN_EL_TIMESTAMP(11);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(timestamp, s, 64, 64);
-
-static struct attribute *adis16350_scan_el_attrs[] = {
- &iio_scan_el_in0_supply.dev_attr.attr,
- &iio_const_attr_in0_supply_index.dev_attr.attr,
- &iio_const_attr_in0_supply_type.dev_attr.attr,
- &iio_scan_el_gyro_x.dev_attr.attr,
- &iio_const_attr_gyro_x_index.dev_attr.attr,
- &iio_scan_el_gyro_y.dev_attr.attr,
- &iio_const_attr_gyro_y_index.dev_attr.attr,
- &iio_scan_el_gyro_z.dev_attr.attr,
- &iio_const_attr_gyro_z_index.dev_attr.attr,
- &iio_const_attr_gyro_type.dev_attr.attr,
- &iio_scan_el_accel_x.dev_attr.attr,
- &iio_const_attr_accel_x_index.dev_attr.attr,
- &iio_scan_el_accel_y.dev_attr.attr,
- &iio_const_attr_accel_y_index.dev_attr.attr,
- &iio_scan_el_accel_z.dev_attr.attr,
- &iio_const_attr_accel_z_index.dev_attr.attr,
- &iio_const_attr_accel_type.dev_attr.attr,
- &iio_scan_el_temp_x.dev_attr.attr,
- &iio_const_attr_temp_x_index.dev_attr.attr,
- &iio_scan_el_temp_y.dev_attr.attr,
- &iio_const_attr_temp_y_index.dev_attr.attr,
- &iio_scan_el_temp_z.dev_attr.attr,
- &iio_const_attr_temp_z_index.dev_attr.attr,
- &iio_const_attr_temp_type.dev_attr.attr,
- &iio_scan_el_in1.dev_attr.attr,
- &iio_const_attr_in1_index.dev_attr.attr,
- &iio_const_attr_in1_type.dev_attr.attr,
- &iio_scan_el_timestamp.dev_attr.attr,
- &iio_const_attr_timestamp_index.dev_attr.attr,
- &iio_const_attr_timestamp_type.dev_attr.attr,
- NULL,
-};
-
-static struct attribute_group adis16350_scan_el_group = {
- .attrs = adis16350_scan_el_attrs,
- .name = "scan_elements",
-};
-
-/**
- * adis16350_poll_func_th() top half interrupt handler called by trigger
- * @private_data: iio_dev
- **/
-static void adis16350_poll_func_th(struct iio_dev *indio_dev, s64 time)
-{
- struct adis16350_state *st = iio_dev_get_devdata(indio_dev);
- st->last_timestamp = time;
- schedule_work(&st->work_trigger_to_ring);
-}
-
-/**
- * adis16350_spi_read_burst() - read all data registers
- * @dev: device associated with child of actual device (iio_dev or iio_trig)
- * @rx: somewhere to pass back the value read (min size is 24 bytes)
- **/
-static int adis16350_spi_read_burst(struct device *dev, u8 *rx)
-{
- struct spi_message msg;
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
- struct adis16350_state *st = iio_dev_get_devdata(indio_dev);
- u32 old_speed_hz = st->us->max_speed_hz;
- int ret;
-
- struct spi_transfer xfers[] = {
- {
- .tx_buf = st->tx,
- .bits_per_word = 8,
- .len = 2,
- .cs_change = 0,
- }, {
- .rx_buf = rx,
- .bits_per_word = 8,
- .len = 22,
- .cs_change = 0,
- },
- };
-
- mutex_lock(&st->buf_lock);
- st->tx[0] = ADIS16350_READ_REG(ADIS16350_GLOB_CMD);
- st->tx[1] = 0;
-
- spi_message_init(&msg);
- spi_message_add_tail(&xfers[0], &msg);
- spi_message_add_tail(&xfers[1], &msg);
-
- st->us->max_speed_hz = ADIS16350_SPI_BURST;
- spi_setup(st->us);
-
- ret = spi_sync(st->us, &msg);
- if (ret)
- dev_err(&st->us->dev, "problem when burst reading");
-
- st->us->max_speed_hz = old_speed_hz;
- spi_setup(st->us);
- mutex_unlock(&st->buf_lock);
- return ret;
-}
-
-/* Whilst this makes a lot of calls to iio_sw_ring functions - it is to device
- * specific to be rolled into the core.
- */
-static void adis16350_trigger_bh_to_ring(struct work_struct *work_s)
-{
- struct adis16350_state *st
- = container_of(work_s, struct adis16350_state,
- work_trigger_to_ring);
- struct iio_ring_buffer *ring = st->indio_dev->ring;
-
- int i = 0;
- s16 *data;
- size_t datasize = ring->access.get_bytes_per_datum(ring);
-
- data = kmalloc(datasize , GFP_KERNEL);
- if (data == NULL) {
- dev_err(&st->us->dev, "memory alloc failed in ring bh");
- return;
- }
-
- if (ring->scan_count)
- if (adis16350_spi_read_burst(&st->indio_dev->dev, st->rx) >= 0)
- for (; i < ring->scan_count; i++)
- data[i] = be16_to_cpup(
- (__be16 *)&(st->rx[i*2]));
-
- /* Guaranteed to be aligned with 8 byte boundary */
- if (ring->scan_timestamp)
- *((s64 *)(data + ((i + 3)/4)*4)) = st->last_timestamp;
-
- ring->access.store_to(ring,
- (u8 *)data,
- st->last_timestamp);
-
- iio_trigger_notify_done(st->indio_dev->trig);
- kfree(data);
-
- return;
-}
-
-void adis16350_unconfigure_ring(struct iio_dev *indio_dev)
-{
- kfree(indio_dev->pollfunc);
- iio_sw_rb_free(indio_dev->ring);
-}
-
-int adis16350_configure_ring(struct iio_dev *indio_dev)
-{
- int ret = 0;
- struct adis16350_state *st = indio_dev->dev_data;
- struct iio_ring_buffer *ring;
- INIT_WORK(&st->work_trigger_to_ring, adis16350_trigger_bh_to_ring);
-
- ring = iio_sw_rb_allocate(indio_dev);
- if (!ring) {
- ret = -ENOMEM;
- return ret;
- }
- indio_dev->ring = ring;
- /* Effectively select the ring buffer implementation */
- iio_ring_sw_register_funcs(&ring->access);
- ring->bpe = 2;
- ring->scan_el_attrs = &adis16350_scan_el_group;
- ring->scan_timestamp = true;
- ring->preenable = &iio_sw_ring_preenable;
- ring->postenable = &iio_triggered_ring_postenable;
- ring->predisable = &iio_triggered_ring_predisable;
- ring->owner = THIS_MODULE;
-
- /* Set default scan mode */
- iio_scan_mask_set(ring, iio_scan_el_in0_supply.number);
- iio_scan_mask_set(ring, iio_scan_el_gyro_x.number);
- iio_scan_mask_set(ring, iio_scan_el_gyro_y.number);
- iio_scan_mask_set(ring, iio_scan_el_gyro_z.number);
- iio_scan_mask_set(ring, iio_scan_el_accel_x.number);
- iio_scan_mask_set(ring, iio_scan_el_accel_y.number);
- iio_scan_mask_set(ring, iio_scan_el_accel_z.number);
- iio_scan_mask_set(ring, iio_scan_el_temp_x.number);
- iio_scan_mask_set(ring, iio_scan_el_temp_y.number);
- iio_scan_mask_set(ring, iio_scan_el_temp_z.number);
- iio_scan_mask_set(ring, iio_scan_el_in1.number);
-
- ret = iio_alloc_pollfunc(indio_dev, NULL, &adis16350_poll_func_th);
- if (ret)
- goto error_iio_sw_rb_free;
-
- indio_dev->modes |= INDIO_RING_TRIGGERED;
- return 0;
-
-error_iio_sw_rb_free:
- iio_sw_rb_free(indio_dev->ring);
- return ret;
-}
-
diff --git a/drivers/staging/iio/imu/adis16350_trigger.c b/drivers/staging/iio/imu/adis16350_trigger.c
deleted file mode 100644
index 739b7ec..0000000
--- a/drivers/staging/iio/imu/adis16350_trigger.c
+++ /dev/null
@@ -1,125 +0,0 @@
-#include <linux/interrupt.h>
-#include <linux/irq.h>
-#include <linux/mutex.h>
-#include <linux/device.h>
-#include <linux/kernel.h>
-#include <linux/sysfs.h>
-#include <linux/list.h>
-#include <linux/spi/spi.h>
-
-#include "../iio.h"
-#include "../sysfs.h"
-#include "../trigger.h"
-#include "adis16350.h"
-
-/**
- * adis16350_data_rdy_trig_poll() the event handler for the data rdy trig
- **/
-static int adis16350_data_rdy_trig_poll(struct iio_dev *dev_info,
- int index,
- s64 timestamp,
- int no_test)
-{
- struct adis16350_state *st = iio_dev_get_devdata(dev_info);
- struct iio_trigger *trig = st->trig;
-
- iio_trigger_poll(trig, timestamp);
-
- return IRQ_HANDLED;
-}
-
-IIO_EVENT_SH(data_rdy_trig, &adis16350_data_rdy_trig_poll);
-
-static IIO_TRIGGER_NAME_ATTR;
-
-static struct attribute *adis16350_trigger_attrs[] = {
- &dev_attr_name.attr,
- NULL,
-};
-
-static const struct attribute_group adis16350_trigger_attr_group = {
- .attrs = adis16350_trigger_attrs,
-};
-
-/**
- * adis16350_data_rdy_trigger_set_state() set datardy interrupt state
- **/
-static int adis16350_data_rdy_trigger_set_state(struct iio_trigger *trig,
- bool state)
-{
- struct adis16350_state *st = trig->private_data;
- struct iio_dev *indio_dev = st->indio_dev;
- int ret = 0;
-
- dev_dbg(&indio_dev->dev, "%s (%d)\n", __func__, state);
- ret = adis16350_set_irq(&st->indio_dev->dev, state);
- if (state == false) {
- iio_remove_event_from_list(&iio_event_data_rdy_trig,
- &indio_dev->interrupts[0]
- ->ev_list);
- /* possible quirk with handler currently worked around
- by ensuring the work queue is empty */
- flush_scheduled_work();
- } else {
- iio_add_event_to_list(&iio_event_data_rdy_trig,
- &indio_dev->interrupts[0]->ev_list);
- }
- return ret;
-}
-
-/**
- * adis16350_trig_try_reen() try renabling irq for data rdy trigger
- * @trig: the datardy trigger
- **/
-static int adis16350_trig_try_reen(struct iio_trigger *trig)
-{
- struct adis16350_state *st = trig->private_data;
- enable_irq(st->us->irq);
- /* irq reenabled so success! */
- return 0;
-}
-
-int adis16350_probe_trigger(struct iio_dev *indio_dev)
-{
- int ret;
- struct adis16350_state *st = indio_dev->dev_data;
-
- st->trig = iio_allocate_trigger();
- st->trig->name = kasprintf(GFP_KERNEL,
- "adis16350-dev%d",
- indio_dev->id);
- if (!st->trig->name) {
- ret = -ENOMEM;
- goto error_free_trig;
- }
- st->trig->dev.parent = &st->us->dev;
- st->trig->owner = THIS_MODULE;
- st->trig->private_data = st;
- st->trig->set_trigger_state = &adis16350_data_rdy_trigger_set_state;
- st->trig->try_reenable = &adis16350_trig_try_reen;
- st->trig->control_attrs = &adis16350_trigger_attr_group;
- ret = iio_trigger_register(st->trig);
-
- /* select default trigger */
- indio_dev->trig = st->trig;
- if (ret)
- goto error_free_trig_name;
-
- return 0;
-
-error_free_trig_name:
- kfree(st->trig->name);
-error_free_trig:
- iio_free_trigger(st->trig);
-
- return ret;
-}
-
-void adis16350_remove_trigger(struct iio_dev *indio_dev)
-{
- struct adis16350_state *state = indio_dev->dev_data;
-
- iio_trigger_unregister(state->trig);
- kfree(state->trig->name);
- iio_free_trigger(state->trig);
-}
diff --git a/drivers/staging/iio/imu/adis16400.h b/drivers/staging/iio/imu/adis16400.h
index e328bcc..db184d1 100644
--- a/drivers/staging/iio/imu/adis16400.h
+++ b/drivers/staging/iio/imu/adis16400.h
@@ -37,6 +37,10 @@
#define ADIS16400_TEMP_OUT 0x16 /* Temperature output */
#define ADIS16400_AUX_ADC 0x18 /* Auxiliary ADC measurement */
+#define ADIS16350_XTEMP_OUT 0x10 /* X-axis gyroscope temperature measurement */
+#define ADIS16350_YTEMP_OUT 0x12 /* Y-axis gyroscope temperature measurement */
+#define ADIS16350_ZTEMP_OUT 0x14 /* Z-axis gyroscope temperature measurement */
+
/* Calibration parameters */
#define ADIS16400_XGYRO_OFF 0x1A /* X-axis gyroscope bias offset factor */
#define ADIS16400_YGYRO_OFF 0x1C /* Y-axis gyroscope bias offset factor */
@@ -68,7 +72,6 @@
#define ADIS16400_AUX_DAC 0x4A /* Auxiliary DAC data */
#define ADIS16400_PRODUCT_ID 0x56 /* Product identifier */
-#define ADIS16400_PRODUCT_ID_DEFAULT 0x4015 /* Datasheet says 0x4105, I get 0x4015 */
#define ADIS16400_ERROR_ACTIVE (1<<14)
#define ADIS16400_NEW_DATA (1<<14)
@@ -123,13 +126,21 @@
#define ADIS16400_SPI_BURST (u32)(1000 * 1000)
#define ADIS16400_SPI_FAST (u32)(2000 * 1000)
+#define ADIS16400_HAS_PROD_ID 1
+#define ADIS16400_NO_BURST 2
+struct adis16400_chip_info {
+ const struct iio_chan_spec *channels;
+ const int num_channels;
+ const int product_id;
+ const long flags;
+ unsigned int gyro_scale_micro;
+ unsigned int accel_scale_micro;
+ unsigned long default_scan_mask;
+};
+
/**
* struct adis16400_state - device instance specific data
* @us: actual spi_device
- * @work_trigger_to_ring: bh for triggered event handling
- * @inter: used to check if new interrupt has been triggered
- * @last_timestamp: passing timestamp from th to bh of interrupt handler
- * @indio_dev: industrial I/O device structure
* @trig: data ready trigger registered with iio
* @tx: transmit buffer
* @rx: receive buffer
@@ -137,16 +148,15 @@
**/
struct adis16400_state {
struct spi_device *us;
- struct work_struct work_trigger_to_ring;
- s64 last_timestamp;
- struct iio_dev *indio_dev;
struct iio_trigger *trig;
- u8 *tx;
- u8 *rx;
struct mutex buf_lock;
+ struct adis16400_chip_info *variant;
+
+ u8 tx[ADIS16400_MAX_TX] ____cacheline_aligned;
+ u8 rx[ADIS16400_MAX_RX] ____cacheline_aligned;
};
-int adis16400_set_irq(struct device *dev, bool enable);
+int adis16400_set_irq(struct iio_dev *indio_dev, bool enable);
#ifdef CONFIG_IIO_RING_BUFFER
/* At the moment triggers are only used for ring buffer
@@ -161,10 +171,16 @@
#define ADIS16400_SCAN_ACC_Y 5
#define ADIS16400_SCAN_ACC_Z 6
#define ADIS16400_SCAN_MAGN_X 7
+#define ADIS16350_SCAN_TEMP_X 7
#define ADIS16400_SCAN_MAGN_Y 8
+#define ADIS16350_SCAN_TEMP_Y 8
#define ADIS16400_SCAN_MAGN_Z 9
+#define ADIS16350_SCAN_TEMP_Z 9
#define ADIS16400_SCAN_TEMP 10
+#define ADIS16350_SCAN_ADC_0 10
#define ADIS16400_SCAN_ADC_0 11
+#define ADIS16300_SCAN_INCLI_X 12
+#define ADIS16300_SCAN_INCLI_Y 13
void adis16400_remove_trigger(struct iio_dev *indio_dev);
int adis16400_probe_trigger(struct iio_dev *indio_dev);
diff --git a/drivers/staging/iio/imu/adis16400_core.c b/drivers/staging/iio/imu/adis16400_core.c
index 540bde6..fe89802 100644
--- a/drivers/staging/iio/imu/adis16400_core.c
+++ b/drivers/staging/iio/imu/adis16400_core.c
@@ -38,7 +38,17 @@
#define DRIVER_NAME "adis16400"
-static int adis16400_check_status(struct device *dev);
+enum adis16400_chip_variant {
+ ADIS16300,
+ ADIS16350,
+ ADIS16360,
+ ADIS16362,
+ ADIS16364,
+ ADIS16365,
+ ADIS16400,
+};
+
+static int adis16400_check_status(struct iio_dev *indio_dev);
/* At the moment the spi framework doesn't allow global setting of cs_change.
* It's in the likely to be added comment at the top of spi.h.
@@ -51,13 +61,12 @@
* @reg_address: the address of the register to be written
* @val: the value to write
**/
-static int adis16400_spi_write_reg_8(struct device *dev,
- u8 reg_address,
- u8 val)
+static int adis16400_spi_write_reg_8(struct iio_dev *indio_dev,
+ u8 reg_address,
+ u8 val)
{
int ret;
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
- struct adis16400_state *st = iio_dev_get_devdata(indio_dev);
+ struct adis16400_state *st = iio_priv(indio_dev);
mutex_lock(&st->buf_lock);
st->tx[0] = ADIS16400_WRITE_REG(reg_address);
@@ -76,14 +85,13 @@
* is assumed to have address one greater.
* @val: value to be written
**/
-static int adis16400_spi_write_reg_16(struct device *dev,
+static int adis16400_spi_write_reg_16(struct iio_dev *indio_dev,
u8 lower_reg_address,
u16 value)
{
int ret;
struct spi_message msg;
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
- struct adis16400_state *st = iio_dev_get_devdata(indio_dev);
+ struct adis16400_state *st = iio_priv(indio_dev);
struct spi_transfer xfers[] = {
{
.tx_buf = st->tx,
@@ -114,18 +122,17 @@
/**
* adis16400_spi_read_reg_16() - read 2 bytes from a 16-bit register
- * @dev: device associated with child of actual device (iio_dev or iio_trig)
+ * @indio_dev: iio device
* @reg_address: the address of the lower of the two registers. Second register
* is assumed to have address one greater.
* @val: somewhere to pass back the value read
**/
-static int adis16400_spi_read_reg_16(struct device *dev,
+static int adis16400_spi_read_reg_16(struct iio_dev *indio_dev,
u8 lower_reg_address,
u16 *val)
{
struct spi_message msg;
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
- struct adis16400_state *st = iio_dev_get_devdata(indio_dev);
+ struct adis16400_state *st = iio_priv(indio_dev);
int ret;
struct spi_transfer xfers[] = {
{
@@ -163,100 +170,15 @@
return ret;
}
-static ssize_t adis16400_spi_read_signed(struct device *dev,
- struct device_attribute *attr,
- char *buf,
- unsigned bits)
-{
- int ret;
- s16 val = 0;
- unsigned shift = 16 - bits;
- struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
-
- ret = adis16400_spi_read_reg_16(dev, this_attr->address, (u16 *)&val);
- if (ret)
- return ret;
-
- if (val & ADIS16400_ERROR_ACTIVE)
- adis16400_check_status(dev);
- val = ((s16)(val << shift) >> shift);
- return sprintf(buf, "%d\n", val);
-}
-
-static ssize_t adis16400_read_12bit_unsigned(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- int ret;
- u16 val = 0;
- struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
-
- ret = adis16400_spi_read_reg_16(dev, this_attr->address, &val);
- if (ret)
- return ret;
-
- if (val & ADIS16400_ERROR_ACTIVE)
- adis16400_check_status(dev);
-
- return sprintf(buf, "%u\n", val & 0x0FFF);
-}
-
-static ssize_t adis16400_read_14bit_signed(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
- ssize_t ret;
-
- /* Take the iio_dev status lock */
- mutex_lock(&indio_dev->mlock);
- ret = adis16400_spi_read_signed(dev, attr, buf, 14);
- mutex_unlock(&indio_dev->mlock);
-
- return ret;
-}
-
-static ssize_t adis16400_read_12bit_signed(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
- ssize_t ret;
-
- /* Take the iio_dev status lock */
- mutex_lock(&indio_dev->mlock);
- ret = adis16400_spi_read_signed(dev, attr, buf, 12);
- mutex_unlock(&indio_dev->mlock);
-
- return ret;
-}
-
-static ssize_t adis16400_write_16bit(struct device *dev,
- struct device_attribute *attr,
- const char *buf,
- size_t len)
-{
- struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
- int ret;
- long val;
-
- ret = strict_strtol(buf, 10, &val);
- if (ret)
- goto error_ret;
- ret = adis16400_spi_write_reg_16(dev, this_attr->address, val);
-
-error_ret:
- return ret ? ret : len;
-}
-
static ssize_t adis16400_read_frequency(struct device *dev,
struct device_attribute *attr,
char *buf)
{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
int ret, len = 0;
u16 t;
int sps;
- ret = adis16400_spi_read_reg_16(dev,
+ ret = adis16400_spi_read_reg_16(indio_dev,
ADIS16400_SMPL_PRD,
&t);
if (ret)
@@ -273,7 +195,7 @@
size_t len)
{
struct iio_dev *indio_dev = dev_get_drvdata(dev);
- struct adis16400_state *st = iio_dev_get_devdata(indio_dev);
+ struct adis16400_state *st = iio_priv(indio_dev);
long val;
int ret;
u8 t;
@@ -293,7 +215,7 @@
else
st->us->max_speed_hz = ADIS16400_SPI_FAST;
- ret = adis16400_spi_write_reg_8(dev,
+ ret = adis16400_spi_write_reg_8(indio_dev,
ADIS16400_SMPL_PRD,
t);
@@ -302,14 +224,14 @@
return ret ? ret : len;
}
-static int adis16400_reset(struct device *dev)
+static int adis16400_reset(struct iio_dev *indio_dev)
{
int ret;
- ret = adis16400_spi_write_reg_8(dev,
+ ret = adis16400_spi_write_reg_8(indio_dev,
ADIS16400_GLOB_CMD,
ADIS16400_GLOB_CMD_SW_RESET);
if (ret)
- dev_err(dev, "problem resetting device");
+ dev_err(&indio_dev->dev, "problem resetting device");
return ret;
}
@@ -318,22 +240,24 @@
struct device_attribute *attr,
const char *buf, size_t len)
{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+
if (len < 1)
return -1;
switch (buf[0]) {
case '1':
case 'y':
case 'Y':
- return adis16400_reset(dev);
+ return adis16400_reset(indio_dev);
}
return -1;
}
-int adis16400_set_irq(struct device *dev, bool enable)
+int adis16400_set_irq(struct iio_dev *indio_dev, bool enable)
{
int ret;
u16 msc;
- ret = adis16400_spi_read_reg_16(dev, ADIS16400_MSC_CTRL, &msc);
+ ret = adis16400_spi_read_reg_16(indio_dev, ADIS16400_MSC_CTRL, &msc);
if (ret)
goto error_ret;
@@ -343,7 +267,7 @@
else
msc &= ~ADIS16400_MSC_CTRL_DATA_RDY_EN;
- ret = adis16400_spi_write_reg_16(dev, ADIS16400_MSC_CTRL, msc);
+ ret = adis16400_spi_write_reg_16(indio_dev, ADIS16400_MSC_CTRL, msc);
if (ret)
goto error_ret;
@@ -352,41 +276,45 @@
}
/* Power down the device */
-static int adis16400_stop_device(struct device *dev)
+static int adis16400_stop_device(struct iio_dev *indio_dev)
{
int ret;
u16 val = ADIS16400_SLP_CNT_POWER_OFF;
- ret = adis16400_spi_write_reg_16(dev, ADIS16400_SLP_CNT, val);
+ ret = adis16400_spi_write_reg_16(indio_dev, ADIS16400_SLP_CNT, val);
if (ret)
- dev_err(dev, "problem with turning device off: SLP_CNT");
+ dev_err(&indio_dev->dev,
+ "problem with turning device off: SLP_CNT");
return ret;
}
-static int adis16400_self_test(struct device *dev)
+static int adis16400_self_test(struct iio_dev *indio_dev)
{
int ret;
- ret = adis16400_spi_write_reg_16(dev,
+ ret = adis16400_spi_write_reg_16(indio_dev,
ADIS16400_MSC_CTRL,
ADIS16400_MSC_CTRL_MEM_TEST);
if (ret) {
- dev_err(dev, "problem starting self test");
+ dev_err(&indio_dev->dev, "problem starting self test");
goto err_ret;
}
+
msleep(ADIS16400_MTEST_DELAY);
- adis16400_check_status(dev);
+ adis16400_check_status(indio_dev);
err_ret:
return ret;
}
-static int adis16400_check_status(struct device *dev)
+static int adis16400_check_status(struct iio_dev *indio_dev)
{
u16 status;
int ret;
+ struct device *dev = &indio_dev->dev;
- ret = adis16400_spi_read_reg_16(dev, ADIS16400_DIAG_STAT, &status);
+ ret = adis16400_spi_read_reg_16(indio_dev,
+ ADIS16400_DIAG_STAT, &status);
if (ret < 0) {
dev_err(dev, "Reading status failed\n");
@@ -428,11 +356,12 @@
return ret;
}
-static int adis16400_initial_setup(struct adis16400_state *st)
+static int adis16400_initial_setup(struct iio_dev *indio_dev)
{
int ret;
u16 prod_id, smp_prd;
- struct device *dev = &st->indio_dev->dev;
+ struct device *dev = &indio_dev->dev;
+ struct adis16400_state *st = iio_priv(indio_dev);
/* use low spi speed for init */
st->us->max_speed_hz = ADIS16400_SPI_SLOW;
@@ -440,45 +369,46 @@
spi_setup(st->us);
/* Disable IRQ */
- ret = adis16400_set_irq(dev, false);
+ ret = adis16400_set_irq(indio_dev, false);
if (ret) {
dev_err(dev, "disable irq failed");
goto err_ret;
}
/* Do self test */
- ret = adis16400_self_test(dev);
+ ret = adis16400_self_test(indio_dev);
if (ret) {
dev_err(dev, "self test failure");
goto err_ret;
}
/* Read status register to check the result */
- ret = adis16400_check_status(dev);
+ ret = adis16400_check_status(indio_dev);
if (ret) {
- adis16400_reset(dev);
+ adis16400_reset(indio_dev);
dev_err(dev, "device not playing ball -> reset");
msleep(ADIS16400_STARTUP_DELAY);
- ret = adis16400_check_status(dev);
+ ret = adis16400_check_status(indio_dev);
if (ret) {
dev_err(dev, "giving up");
goto err_ret;
}
}
+ if (st->variant->flags & ADIS16400_HAS_PROD_ID) {
+ ret = adis16400_spi_read_reg_16(indio_dev,
+ ADIS16400_PRODUCT_ID, &prod_id);
+ if (ret)
+ goto err_ret;
- ret = adis16400_spi_read_reg_16(dev, ADIS16400_PRODUCT_ID, &prod_id);
- if (ret)
- goto err_ret;
+ if ((prod_id & 0xF000) != st->variant->product_id)
+ dev_warn(dev, "incorrect id");
- if ((prod_id & 0xF000) != ADIS16400_PRODUCT_ID_DEFAULT)
- dev_warn(dev, "unknown product id");
-
-
- dev_info(dev, ": prod_id 0x%04x at CS%d (irq %d)\n",
- prod_id, st->us->chip_select, st->us->irq);
-
+ printk(KERN_INFO DRIVER_NAME ": prod_id 0x%04x at CS%d (irq %d)\n",
+ prod_id, st->us->chip_select, st->us->irq);
+ }
/* use high spi speed if possible */
- ret = adis16400_spi_read_reg_16(dev, ADIS16400_SMPL_PRD, &smp_prd);
+ ret = adis16400_spi_read_reg_16(indio_dev,
+ ADIS16400_SMPL_PRD, &smp_prd);
if (!ret && (smp_prd & ADIS16400_SMPL_PRD_DIV_MASK) < 0x0A) {
st->us->max_speed_hz = ADIS16400_SPI_SLOW;
spi_setup(st->us);
@@ -490,58 +420,6 @@
return ret;
}
-#define ADIS16400_DEV_ATTR_CALIBBIAS(_channel, _reg) \
- IIO_DEV_ATTR_##_channel##_CALIBBIAS(S_IWUSR | S_IRUGO, \
- adis16400_read_12bit_signed, \
- adis16400_write_16bit, \
- _reg)
-
-static ADIS16400_DEV_ATTR_CALIBBIAS(GYRO_X, ADIS16400_XGYRO_OFF);
-static ADIS16400_DEV_ATTR_CALIBBIAS(GYRO_Y, ADIS16400_YGYRO_OFF);
-static ADIS16400_DEV_ATTR_CALIBBIAS(GYRO_Z, ADIS16400_ZGYRO_OFF);
-
-static ADIS16400_DEV_ATTR_CALIBBIAS(ACCEL_X, ADIS16400_XACCL_OFF);
-static ADIS16400_DEV_ATTR_CALIBBIAS(ACCEL_Y, ADIS16400_YACCL_OFF);
-static ADIS16400_DEV_ATTR_CALIBBIAS(ACCEL_Z, ADIS16400_ZACCL_OFF);
-
-
-static IIO_DEV_ATTR_IN_NAMED_RAW(0, supply, adis16400_read_14bit_signed,
- ADIS16400_SUPPLY_OUT);
-static IIO_CONST_ATTR_IN_NAMED_SCALE(0, supply, "0.002418 V");
-
-static IIO_DEV_ATTR_GYRO_X(adis16400_read_14bit_signed,
- ADIS16400_XGYRO_OUT);
-static IIO_DEV_ATTR_GYRO_Y(adis16400_read_14bit_signed,
- ADIS16400_YGYRO_OUT);
-static IIO_DEV_ATTR_GYRO_Z(adis16400_read_14bit_signed,
- ADIS16400_ZGYRO_OUT);
-static IIO_CONST_ATTR(gyro_scale, "0.0008726646");
-
-static IIO_DEV_ATTR_ACCEL_X(adis16400_read_14bit_signed,
- ADIS16400_XACCL_OUT);
-static IIO_DEV_ATTR_ACCEL_Y(adis16400_read_14bit_signed,
- ADIS16400_YACCL_OUT);
-static IIO_DEV_ATTR_ACCEL_Z(adis16400_read_14bit_signed,
- ADIS16400_ZACCL_OUT);
-static IIO_CONST_ATTR(accel_scale, "0.0326561445");
-
-static IIO_DEV_ATTR_MAGN_X(adis16400_read_14bit_signed,
- ADIS16400_XMAGN_OUT);
-static IIO_DEV_ATTR_MAGN_Y(adis16400_read_14bit_signed,
- ADIS16400_YMAGN_OUT);
-static IIO_DEV_ATTR_MAGN_Z(adis16400_read_14bit_signed,
- ADIS16400_ZMAGN_OUT);
-static IIO_CONST_ATTR(magn_scale, "0.0005 Gs");
-
-
-static IIO_DEV_ATTR_TEMP_RAW(adis16400_read_12bit_signed);
-static IIO_CONST_ATTR_TEMP_OFFSET("198.16 K");
-static IIO_CONST_ATTR_TEMP_SCALE("0.14 K");
-
-static IIO_DEV_ATTR_IN_RAW(1, adis16400_read_12bit_unsigned,
- ADIS16400_AUX_ADC);
-static IIO_CONST_ATTR(in1_scale, "0.000806 V");
-
static IIO_DEV_ATTR_SAMP_FREQ(S_IWUSR | S_IRUGO,
adis16400_read_frequency,
adis16400_write_frequency);
@@ -550,46 +428,273 @@
static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("409 546 819 1638");
-static IIO_CONST_ATTR_NAME("adis16400");
-
-static struct attribute *adis16400_event_attributes[] = {
- NULL
+enum adis16400_chan {
+ in_supply,
+ gyro_x,
+ gyro_y,
+ gyro_z,
+ accel_x,
+ accel_y,
+ accel_z,
+ magn_x,
+ magn_y,
+ magn_z,
+ temp,
+ temp0, temp1, temp2,
+ in1
};
-static struct attribute_group adis16400_event_attribute_group = {
- .attrs = adis16400_event_attributes,
+static u8 adis16400_addresses[16][2] = {
+ [in_supply] = { ADIS16400_SUPPLY_OUT, 0 },
+ [gyro_x] = { ADIS16400_XGYRO_OUT, ADIS16400_XGYRO_OFF },
+ [gyro_y] = { ADIS16400_YGYRO_OUT, ADIS16400_YGYRO_OFF },
+ [gyro_z] = { ADIS16400_ZGYRO_OUT, ADIS16400_ZGYRO_OFF },
+ [accel_x] = { ADIS16400_XACCL_OUT, ADIS16400_XACCL_OFF },
+ [accel_y] = { ADIS16400_YACCL_OUT, ADIS16400_YACCL_OFF },
+ [accel_z] = { ADIS16400_ZACCL_OUT, ADIS16400_ZACCL_OFF },
+ [magn_x] = { ADIS16400_XMAGN_OUT, 0 },
+ [magn_y] = { ADIS16400_YMAGN_OUT, 0 },
+ [magn_z] = { ADIS16400_ZMAGN_OUT, 0 },
+ [temp] = { ADIS16400_TEMP_OUT, 0 },
+ [temp0] = { ADIS16350_XTEMP_OUT },
+ [temp1] = { ADIS16350_YTEMP_OUT },
+ [temp2] = { ADIS16350_ZTEMP_OUT },
+ [in1] = { ADIS16400_AUX_ADC , 0 },
+};
+
+static int adis16400_write_raw(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ int val,
+ int val2,
+ long mask)
+{
+ int ret;
+ switch (mask) {
+ case (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE):
+ mutex_lock(&indio_dev->mlock);
+ ret = adis16400_spi_write_reg_16(indio_dev,
+ adis16400_addresses[chan->address][1],
+ val);
+ mutex_unlock(&indio_dev->mlock);
+ return ret;
+ default:
+ return -EINVAL;
+ }
+}
+
+static int adis16400_read_raw(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ int *val,
+ int *val2,
+ long mask)
+{
+ struct adis16400_state *st = iio_priv(indio_dev);
+ int ret;
+ s16 val16;
+ int shift;
+
+ switch (mask) {
+ case 0:
+ mutex_lock(&indio_dev->mlock);
+ ret = adis16400_spi_read_reg_16(indio_dev,
+ adis16400_addresses[chan->address][0],
+ &val16);
+ if (ret) {
+ mutex_unlock(&indio_dev->mlock);
+ return ret;
+ }
+ val16 &= (1 << chan->scan_type.realbits) - 1;
+ if (chan->scan_type.sign == 's') {
+ shift = 16 - chan->scan_type.realbits;
+ val16 = (s16)(val16 << shift) >> shift;
+ }
+ *val = val16;
+ mutex_unlock(&indio_dev->mlock);
+ return IIO_VAL_INT;
+ case (1 << IIO_CHAN_INFO_SCALE_SHARED):
+ case (1 << IIO_CHAN_INFO_SCALE_SEPARATE):
+ switch (chan->type) {
+ case IIO_GYRO:
+ *val = 0;
+ *val2 = st->variant->gyro_scale_micro;
+ return IIO_VAL_INT_PLUS_MICRO;
+ case IIO_IN:
+ *val = 0;
+ if (chan->channel == 0)
+ *val2 = 2418;
+ else
+ *val2 = 806;
+ return IIO_VAL_INT_PLUS_MICRO;
+ case IIO_ACCEL:
+ *val = 0;
+ *val2 = st->variant->accel_scale_micro;
+ return IIO_VAL_INT_PLUS_MICRO;
+ case IIO_MAGN:
+ *val = 0;
+ *val2 = 500;
+ return IIO_VAL_INT_PLUS_MICRO;
+ case IIO_TEMP:
+ *val = 0;
+ *val2 = 140000;
+ return IIO_VAL_INT_PLUS_MICRO;
+ default:
+ return -EINVAL;
+ }
+ case (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE):
+ mutex_lock(&indio_dev->mlock);
+ ret = adis16400_spi_read_reg_16(indio_dev,
+ adis16400_addresses[chan->address][1],
+ &val16);
+ mutex_unlock(&indio_dev->mlock);
+ if (ret)
+ return ret;
+ val16 = ((val16 & 0xFFF) << 4) >> 4;
+ *val = val16;
+ return IIO_VAL_INT;
+ case (1 << IIO_CHAN_INFO_OFFSET_SEPARATE):
+ /* currently only temperature */
+ *val = 198;
+ *val2 = 160000;
+ return IIO_VAL_INT_PLUS_MICRO;
+ default:
+ return -EINVAL;
+ }
+}
+
+static struct iio_chan_spec adis16400_channels[] = {
+ IIO_CHAN(IIO_IN, 0, 1, 0, "supply", 0, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SEPARATE),
+ in_supply, ADIS16400_SCAN_SUPPLY,
+ IIO_ST('u', 14, 16, 0), 0),
+ IIO_CHAN(IIO_GYRO, 1, 0, 0, NULL, 0, IIO_MOD_X,
+ (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE) |
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ gyro_x, ADIS16400_SCAN_GYRO_X, IIO_ST('s', 14, 16, 0), 0),
+ IIO_CHAN(IIO_GYRO, 1, 0, 0, NULL, 0, IIO_MOD_Y,
+ (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE) |
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ gyro_y, ADIS16400_SCAN_GYRO_Y, IIO_ST('s', 14, 16, 0), 0),
+ IIO_CHAN(IIO_GYRO, 1, 0, 0, NULL, 0, IIO_MOD_Z,
+ (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE) |
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ gyro_z, ADIS16400_SCAN_GYRO_Z, IIO_ST('s', 14, 16, 0), 0),
+ IIO_CHAN(IIO_ACCEL, 1, 0, 0, NULL, 0, IIO_MOD_X,
+ (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE) |
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ accel_x, ADIS16400_SCAN_ACC_X, IIO_ST('s', 14, 16, 0), 0),
+ IIO_CHAN(IIO_ACCEL, 1, 0, 0, NULL, 0, IIO_MOD_Y,
+ (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE) |
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ accel_y, ADIS16400_SCAN_ACC_Y, IIO_ST('s', 14, 16, 0), 0),
+ IIO_CHAN(IIO_ACCEL, 1, 0, 0, NULL, 0, IIO_MOD_Z,
+ (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE) |
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ accel_z, ADIS16400_SCAN_ACC_Z, IIO_ST('s', 14, 16, 0), 0),
+ IIO_CHAN(IIO_MAGN, 1, 0, 0, NULL, 0, IIO_MOD_X,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ magn_x, ADIS16400_SCAN_MAGN_X, IIO_ST('s', 14, 16, 0), 0),
+ IIO_CHAN(IIO_MAGN, 1, 0, 0, NULL, 0, IIO_MOD_Y,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ magn_y, ADIS16400_SCAN_MAGN_Y, IIO_ST('s', 14, 16, 0), 0),
+ IIO_CHAN(IIO_MAGN, 1, 0, 0, NULL, 0, IIO_MOD_Z,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ magn_z, ADIS16400_SCAN_MAGN_Z, IIO_ST('s', 14, 16, 0), 0),
+ IIO_CHAN(IIO_TEMP, 0, 1, 0, NULL, 0, 0,
+ (1 << IIO_CHAN_INFO_OFFSET_SEPARATE) |
+ (1 << IIO_CHAN_INFO_SCALE_SEPARATE),
+ temp, ADIS16400_SCAN_TEMP, IIO_ST('s', 12, 16, 0), 0),
+ IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 1, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SEPARATE),
+ in1, ADIS16400_SCAN_ADC_0, IIO_ST('s', 12, 16, 0), 0),
+ IIO_CHAN_SOFT_TIMESTAMP(12)
+};
+
+static struct iio_chan_spec adis16350_channels[] = {
+ IIO_CHAN(IIO_IN, 0, 1, 0, "supply", 0, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SEPARATE),
+ 0, ADIS16400_SCAN_SUPPLY, IIO_ST('u', 12, 16, 0), 0),
+ IIO_CHAN(IIO_GYRO, 1, 0, 0, NULL, 0, IIO_MOD_X,
+ (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE) |
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 1, ADIS16400_SCAN_GYRO_X, IIO_ST('s', 14, 16, 0), 0),
+ IIO_CHAN(IIO_GYRO, 1, 0, 0, NULL, 0, IIO_MOD_Y,
+ (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE) |
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 2, ADIS16400_SCAN_GYRO_Y, IIO_ST('s', 14, 16, 0), 0),
+ IIO_CHAN(IIO_GYRO, 1, 0, 0, NULL, 0, IIO_MOD_Z,
+ (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE) |
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 3, ADIS16400_SCAN_GYRO_Z, IIO_ST('s', 14, 16, 0), 0),
+ IIO_CHAN(IIO_ACCEL, 1, 0, 0, NULL, 0, IIO_MOD_X,
+ (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE) |
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 4, ADIS16400_SCAN_ACC_X, IIO_ST('s', 14, 16, 0), 0),
+ IIO_CHAN(IIO_ACCEL, 1, 0, 0, NULL, 0, IIO_MOD_Y,
+ (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE) |
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 0, ADIS16400_SCAN_ACC_Y, IIO_ST('s', 14, 16, 0), 0),
+ IIO_CHAN(IIO_ACCEL, 1, 0, 0, NULL, 0, IIO_MOD_Z,
+ (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE) |
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 0, ADIS16400_SCAN_ACC_Z, IIO_ST('s', 14, 16, 0), 0),
+ IIO_CHAN(IIO_TEMP, 0, 1, 0, "x", 0, 0,
+ (1 << IIO_CHAN_INFO_OFFSET_SEPARATE) |
+ (1 << IIO_CHAN_INFO_SCALE_SEPARATE),
+ 0, ADIS16350_SCAN_TEMP_X, IIO_ST('s', 12, 16, 0), 0),
+ IIO_CHAN(IIO_TEMP, 0, 1, 0, "y", 1, 0,
+ (1 << IIO_CHAN_INFO_OFFSET_SEPARATE) |
+ (1 << IIO_CHAN_INFO_SCALE_SEPARATE),
+ 0, ADIS16350_SCAN_TEMP_Y, IIO_ST('s', 12, 16, 0), 0),
+ IIO_CHAN(IIO_TEMP, 0, 1, 0, "z", 2, 0,
+ (1 << IIO_CHAN_INFO_OFFSET_SEPARATE) |
+ (1 << IIO_CHAN_INFO_SCALE_SEPARATE),
+ 0, ADIS16350_SCAN_TEMP_Z, IIO_ST('s', 12, 16, 0), 0),
+ IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 1, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SEPARATE),
+ 0, ADIS16350_SCAN_ADC_0, IIO_ST('s', 12, 16, 0), 0),
+ IIO_CHAN_SOFT_TIMESTAMP(11)
+};
+
+static struct iio_chan_spec adis16300_channels[] = {
+ IIO_CHAN(IIO_IN, 0, 1, 0, "supply", 0, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SEPARATE),
+ 0, ADIS16400_SCAN_SUPPLY, IIO_ST('u', 12, 16, 0), 0),
+ IIO_CHAN(IIO_GYRO, 1, 0, 0, NULL, 0, IIO_MOD_X,
+ (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE) |
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 1, ADIS16400_SCAN_GYRO_X, IIO_ST('s', 14, 16, 0), 0),
+ IIO_CHAN(IIO_ACCEL, 1, 0, 0, NULL, 0, IIO_MOD_X,
+ (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE) |
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 4, ADIS16400_SCAN_ACC_X, IIO_ST('s', 14, 16, 0), 0),
+ IIO_CHAN(IIO_ACCEL, 1, 0, 0, NULL, 0, IIO_MOD_Y,
+ (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE) |
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 0, ADIS16400_SCAN_ACC_Y, IIO_ST('s', 14, 16, 0), 0),
+ IIO_CHAN(IIO_ACCEL, 1, 0, 0, NULL, 0, IIO_MOD_Z,
+ (1 << IIO_CHAN_INFO_CALIBBIAS_SEPARATE) |
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 0, ADIS16400_SCAN_ACC_Z, IIO_ST('s', 14, 16, 0), 0),
+ IIO_CHAN(IIO_TEMP, 0, 1, 0, NULL, 0, 0,
+ (1 << IIO_CHAN_INFO_OFFSET_SEPARATE) |
+ (1 << IIO_CHAN_INFO_SCALE_SEPARATE),
+ 0, ADIS16400_SCAN_TEMP, IIO_ST('s', 12, 16, 0), 0),
+ IIO_CHAN(IIO_IN, 0, 1, 0, NULL, 1, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SEPARATE),
+ 0, ADIS16350_SCAN_ADC_0, IIO_ST('s', 12, 16, 0), 0),
+ IIO_CHAN(IIO_INCLI, 1, 0, 0, NULL, 0, IIO_MOD_X,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 0, ADIS16300_SCAN_INCLI_X, IIO_ST('s', 13, 16, 0), 0),
+ IIO_CHAN(IIO_INCLI, 1, 0, 0, NULL, 0, IIO_MOD_Y,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ 0, ADIS16300_SCAN_INCLI_Y, IIO_ST('s', 13, 16, 0), 0),
+ IIO_CHAN_SOFT_TIMESTAMP(14)
};
static struct attribute *adis16400_attributes[] = {
- &iio_dev_attr_gyro_x_calibbias.dev_attr.attr,
- &iio_dev_attr_gyro_y_calibbias.dev_attr.attr,
- &iio_dev_attr_gyro_z_calibbias.dev_attr.attr,
- &iio_dev_attr_accel_x_calibbias.dev_attr.attr,
- &iio_dev_attr_accel_y_calibbias.dev_attr.attr,
- &iio_dev_attr_accel_z_calibbias.dev_attr.attr,
- &iio_dev_attr_in0_supply_raw.dev_attr.attr,
- &iio_const_attr_in0_supply_scale.dev_attr.attr,
- &iio_dev_attr_gyro_x_raw.dev_attr.attr,
- &iio_dev_attr_gyro_y_raw.dev_attr.attr,
- &iio_dev_attr_gyro_z_raw.dev_attr.attr,
- &iio_const_attr_gyro_scale.dev_attr.attr,
- &iio_dev_attr_accel_x_raw.dev_attr.attr,
- &iio_dev_attr_accel_y_raw.dev_attr.attr,
- &iio_dev_attr_accel_z_raw.dev_attr.attr,
- &iio_const_attr_accel_scale.dev_attr.attr,
- &iio_dev_attr_magn_x_raw.dev_attr.attr,
- &iio_dev_attr_magn_y_raw.dev_attr.attr,
- &iio_dev_attr_magn_z_raw.dev_attr.attr,
- &iio_const_attr_magn_scale.dev_attr.attr,
- &iio_dev_attr_temp_raw.dev_attr.attr,
- &iio_const_attr_temp_offset.dev_attr.attr,
- &iio_const_attr_temp_scale.dev_attr.attr,
- &iio_dev_attr_in1_raw.dev_attr.attr,
- &iio_const_attr_in1_scale.dev_attr.attr,
&iio_dev_attr_sampling_frequency.dev_attr.attr,
&iio_const_attr_sampling_frequency_available.dev_attr.attr,
&iio_dev_attr_reset.dev_attr.attr,
- &iio_const_attr_name.dev_attr.attr,
NULL
};
@@ -597,101 +702,147 @@
.attrs = adis16400_attributes,
};
+static struct adis16400_chip_info adis16400_chips[] = {
+ [ADIS16300] = {
+ .channels = adis16300_channels,
+ .num_channels = ARRAY_SIZE(adis16300_channels),
+ .gyro_scale_micro = 873,
+ .accel_scale_micro = 5884,
+ .default_scan_mask = (1 << ADIS16400_SCAN_SUPPLY) |
+ (1 << ADIS16400_SCAN_GYRO_X) | (1 << ADIS16400_SCAN_ACC_X) |
+ (1 << ADIS16400_SCAN_ACC_Y) | (1 << ADIS16400_SCAN_ACC_Z) |
+ (1 << ADIS16400_SCAN_TEMP) | (1 << ADIS16400_SCAN_ADC_0) |
+ (1 << ADIS16300_SCAN_INCLI_X) | (1 << ADIS16300_SCAN_INCLI_Y) |
+ (1 << 14),
+ },
+ [ADIS16350] = {
+ .channels = adis16350_channels,
+ .num_channels = ARRAY_SIZE(adis16350_channels),
+ .gyro_scale_micro = 872664,
+ .accel_scale_micro = 24732,
+ .default_scan_mask = 0x7FF,
+ .flags = ADIS16400_NO_BURST,
+ },
+ [ADIS16360] = {
+ .channels = adis16350_channels,
+ .num_channels = ARRAY_SIZE(adis16350_channels),
+ .flags = ADIS16400_HAS_PROD_ID,
+ .product_id = 0x3FE8,
+ .gyro_scale_micro = 1279,
+ .accel_scale_micro = 24732,
+ .default_scan_mask = 0x7FF,
+ },
+ [ADIS16362] = {
+ .channels = adis16350_channels,
+ .num_channels = ARRAY_SIZE(adis16350_channels),
+ .flags = ADIS16400_HAS_PROD_ID,
+ .product_id = 0x3FEA,
+ .gyro_scale_micro = 1279,
+ .accel_scale_micro = 24732,
+ .default_scan_mask = 0x7FF,
+ },
+ [ADIS16364] = {
+ .channels = adis16350_channels,
+ .num_channels = ARRAY_SIZE(adis16350_channels),
+ .flags = ADIS16400_HAS_PROD_ID,
+ .product_id = 0x3FEC,
+ .gyro_scale_micro = 1279,
+ .accel_scale_micro = 24732,
+ .default_scan_mask = 0x7FF,
+ },
+ [ADIS16365] = {
+ .channels = adis16350_channels,
+ .num_channels = ARRAY_SIZE(adis16350_channels),
+ .flags = ADIS16400_HAS_PROD_ID,
+ .product_id = 0x3FED,
+ .gyro_scale_micro = 1279,
+ .accel_scale_micro = 24732,
+ .default_scan_mask = 0x7FF,
+ },
+ [ADIS16400] = {
+ .channels = adis16400_channels,
+ .num_channels = ARRAY_SIZE(adis16400_channels),
+ .flags = ADIS16400_HAS_PROD_ID,
+ .product_id = 0x4015,
+ .gyro_scale_micro = 873,
+ .accel_scale_micro = 32656,
+ .default_scan_mask = 0xFFF,
+ }
+};
+
+static const struct iio_info adis16400_info = {
+ .driver_module = THIS_MODULE,
+ .read_raw = &adis16400_read_raw,
+ .write_raw = &adis16400_write_raw,
+ .attrs = &adis16400_attribute_group,
+};
+
static int __devinit adis16400_probe(struct spi_device *spi)
{
int ret, regdone = 0;
- struct adis16400_state *st = kzalloc(sizeof *st, GFP_KERNEL);
- if (!st) {
+ struct adis16400_state *st;
+ struct iio_dev *indio_dev = iio_allocate_device(sizeof(*st));
+ if (indio_dev == NULL) {
ret = -ENOMEM;
goto error_ret;
}
+ st = iio_priv(indio_dev);
/* this is only used for removal purposes */
- spi_set_drvdata(spi, st);
+ spi_set_drvdata(spi, indio_dev);
- /* Allocate the comms buffers */
- st->rx = kzalloc(sizeof(*st->rx)*ADIS16400_MAX_RX, GFP_KERNEL);
- if (st->rx == NULL) {
- ret = -ENOMEM;
- goto error_free_st;
- }
- st->tx = kzalloc(sizeof(*st->tx)*ADIS16400_MAX_TX, GFP_KERNEL);
- if (st->tx == NULL) {
- ret = -ENOMEM;
- goto error_free_rx;
- }
st->us = spi;
mutex_init(&st->buf_lock);
+
/* setup the industrialio driver allocated elements */
- st->indio_dev = iio_allocate_device();
- if (st->indio_dev == NULL) {
- ret = -ENOMEM;
- goto error_free_tx;
- }
+ st->variant = &adis16400_chips[spi_get_device_id(spi)->driver_data];
+ indio_dev->dev.parent = &spi->dev;
+ indio_dev->name = spi_get_device_id(spi)->name;
+ indio_dev->channels = st->variant->channels;
+ indio_dev->num_channels = st->variant->num_channels;
+ indio_dev->info = &adis16400_info;
+ indio_dev->modes = INDIO_DIRECT_MODE;
- st->indio_dev->dev.parent = &spi->dev;
- st->indio_dev->num_interrupt_lines = 1;
- st->indio_dev->event_attrs = &adis16400_event_attribute_group;
- st->indio_dev->attrs = &adis16400_attribute_group;
- st->indio_dev->dev_data = (void *)(st);
- st->indio_dev->driver_module = THIS_MODULE;
- st->indio_dev->modes = INDIO_DIRECT_MODE;
-
- ret = adis16400_configure_ring(st->indio_dev);
+ ret = adis16400_configure_ring(indio_dev);
if (ret)
goto error_free_dev;
- ret = iio_device_register(st->indio_dev);
+ ret = iio_device_register(indio_dev);
if (ret)
goto error_unreg_ring_funcs;
regdone = 1;
- ret = iio_ring_buffer_register(st->indio_dev->ring, 0);
+ ret = iio_ring_buffer_register_ex(indio_dev->ring, 0,
+ st->variant->channels,
+ st->variant->num_channels);
if (ret) {
dev_err(&spi->dev, "failed to initialize the ring\n");
goto error_unreg_ring_funcs;
}
if (spi->irq && gpio_is_valid(irq_to_gpio(spi->irq)) > 0) {
- ret = iio_register_interrupt_line(spi->irq,
- st->indio_dev,
- 0,
- IRQF_TRIGGER_RISING,
- "adis16400");
+ ret = adis16400_probe_trigger(indio_dev);
if (ret)
goto error_uninitialize_ring;
-
- ret = adis16400_probe_trigger(st->indio_dev);
- if (ret)
- goto error_unregister_line;
}
/* Get the device into a sane initial state */
- ret = adis16400_initial_setup(st);
+ ret = adis16400_initial_setup(indio_dev);
if (ret)
goto error_remove_trigger;
return 0;
error_remove_trigger:
- if (st->indio_dev->modes & INDIO_RING_TRIGGERED)
- adis16400_remove_trigger(st->indio_dev);
-error_unregister_line:
- if (st->indio_dev->modes & INDIO_RING_TRIGGERED)
- iio_unregister_interrupt_line(st->indio_dev, 0);
+ if (indio_dev->modes & INDIO_RING_TRIGGERED)
+ adis16400_remove_trigger(indio_dev);
error_uninitialize_ring:
- iio_ring_buffer_unregister(st->indio_dev->ring);
+ iio_ring_buffer_unregister(indio_dev->ring);
error_unreg_ring_funcs:
- adis16400_unconfigure_ring(st->indio_dev);
+ adis16400_unconfigure_ring(indio_dev);
error_free_dev:
if (regdone)
- iio_device_unregister(st->indio_dev);
+ iio_device_unregister(indio_dev);
else
- iio_free_device(st->indio_dev);
-error_free_tx:
- kfree(st->tx);
-error_free_rx:
- kfree(st->rx);
-error_free_st:
- kfree(st);
+ iio_free_device(indio_dev);
error_ret:
return ret;
}
@@ -700,25 +851,16 @@
static int adis16400_remove(struct spi_device *spi)
{
int ret;
- struct adis16400_state *st = spi_get_drvdata(spi);
- struct iio_dev *indio_dev = st->indio_dev;
+ struct iio_dev *indio_dev = spi_get_drvdata(spi);
- ret = adis16400_stop_device(&(indio_dev->dev));
+ ret = adis16400_stop_device(indio_dev);
if (ret)
goto err_ret;
- flush_scheduled_work();
-
adis16400_remove_trigger(indio_dev);
- if (spi->irq && gpio_is_valid(irq_to_gpio(spi->irq)) > 0)
- iio_unregister_interrupt_line(indio_dev, 0);
-
- iio_ring_buffer_unregister(st->indio_dev->ring);
+ iio_ring_buffer_unregister(indio_dev->ring);
adis16400_unconfigure_ring(indio_dev);
iio_device_unregister(indio_dev);
- kfree(st->tx);
- kfree(st->rx);
- kfree(st);
return 0;
@@ -726,11 +868,26 @@
return ret;
}
+static const struct spi_device_id adis16400_id[] = {
+ {"adis16300", ADIS16300},
+ {"adis16350", ADIS16350},
+ {"adis16354", ADIS16350},
+ {"adis16355", ADIS16350},
+ {"adis16360", ADIS16360},
+ {"adis16362", ADIS16362},
+ {"adis16364", ADIS16364},
+ {"adis16365", ADIS16365},
+ {"adis16400", ADIS16400},
+ {"adis16405", ADIS16400},
+ {}
+};
+
static struct spi_driver adis16400_driver = {
.driver = {
.name = "adis16400",
.owner = THIS_MODULE,
},
+ .id_table = adis16400_id,
.probe = adis16400_probe,
.remove = __devexit_p(adis16400_remove),
};
diff --git a/drivers/staging/iio/imu/adis16400_ring.c b/drivers/staging/iio/imu/adis16400_ring.c
index da28cb4..2589a7e 100644
--- a/drivers/staging/iio/imu/adis16400_ring.c
+++ b/drivers/staging/iio/imu/adis16400_ring.c
@@ -9,6 +9,7 @@
#include <linux/slab.h>
#include <linux/sysfs.h>
#include <linux/list.h>
+#include <linux/bitops.h>
#include "../iio.h"
#include "../sysfs.h"
@@ -17,93 +18,6 @@
#include "../trigger.h"
#include "adis16400.h"
-static IIO_SCAN_EL_C(in0_supply, ADIS16400_SCAN_SUPPLY,
- ADIS16400_SUPPLY_OUT, NULL);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(in0_supply, u, 14, 16);
-
-static IIO_SCAN_EL_C(gyro_x, ADIS16400_SCAN_GYRO_X, ADIS16400_XGYRO_OUT, NULL);
-static IIO_SCAN_EL_C(gyro_y, ADIS16400_SCAN_GYRO_Y, ADIS16400_YGYRO_OUT, NULL);
-static IIO_SCAN_EL_C(gyro_z, ADIS16400_SCAN_GYRO_Z, ADIS16400_ZGYRO_OUT, NULL);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(gyro, s, 14, 16);
-
-static IIO_SCAN_EL_C(accel_x, ADIS16400_SCAN_ACC_X, ADIS16400_XACCL_OUT, NULL);
-static IIO_SCAN_EL_C(accel_y, ADIS16400_SCAN_ACC_Y, ADIS16400_YACCL_OUT, NULL);
-static IIO_SCAN_EL_C(accel_z, ADIS16400_SCAN_ACC_Z, ADIS16400_ZACCL_OUT, NULL);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(accel, s, 14, 16);
-
-static IIO_SCAN_EL_C(magn_x, ADIS16400_SCAN_MAGN_X, ADIS16400_XMAGN_OUT, NULL);
-static IIO_SCAN_EL_C(magn_y, ADIS16400_SCAN_MAGN_Y, ADIS16400_YMAGN_OUT, NULL);
-static IIO_SCAN_EL_C(magn_z, ADIS16400_SCAN_MAGN_Z, ADIS16400_ZMAGN_OUT, NULL);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(magn, s, 14, 16);
-
-static IIO_SCAN_EL_C(temp, ADIS16400_SCAN_TEMP, ADIS16400_TEMP_OUT, NULL);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(temp, s, 12, 16);
-
-static IIO_SCAN_EL_C(in1, ADIS16400_SCAN_ADC_0, ADIS16400_AUX_ADC, NULL);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(in1, u, 12, 16);
-
-static IIO_SCAN_EL_TIMESTAMP(12);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(timestamp, s, 64, 64);
-
-static struct attribute *adis16400_scan_el_attrs[] = {
- &iio_scan_el_in0_supply.dev_attr.attr,
- &iio_const_attr_in0_supply_index.dev_attr.attr,
- &iio_const_attr_in0_supply_type.dev_attr.attr,
- &iio_scan_el_gyro_x.dev_attr.attr,
- &iio_const_attr_gyro_x_index.dev_attr.attr,
- &iio_scan_el_gyro_y.dev_attr.attr,
- &iio_const_attr_gyro_y_index.dev_attr.attr,
- &iio_scan_el_gyro_z.dev_attr.attr,
- &iio_const_attr_gyro_z_index.dev_attr.attr,
- &iio_const_attr_gyro_type.dev_attr.attr,
- &iio_scan_el_accel_x.dev_attr.attr,
- &iio_const_attr_accel_x_index.dev_attr.attr,
- &iio_scan_el_accel_y.dev_attr.attr,
- &iio_const_attr_accel_y_index.dev_attr.attr,
- &iio_scan_el_accel_z.dev_attr.attr,
- &iio_const_attr_accel_z_index.dev_attr.attr,
- &iio_const_attr_accel_type.dev_attr.attr,
- &iio_scan_el_magn_x.dev_attr.attr,
- &iio_const_attr_magn_x_index.dev_attr.attr,
- &iio_scan_el_magn_y.dev_attr.attr,
- &iio_const_attr_magn_y_index.dev_attr.attr,
- &iio_scan_el_magn_z.dev_attr.attr,
- &iio_const_attr_magn_z_index.dev_attr.attr,
- &iio_const_attr_magn_type.dev_attr.attr,
- &iio_scan_el_temp.dev_attr.attr,
- &iio_const_attr_temp_index.dev_attr.attr,
- &iio_const_attr_temp_type.dev_attr.attr,
- &iio_scan_el_in1.dev_attr.attr,
- &iio_const_attr_in1_index.dev_attr.attr,
- &iio_const_attr_in1_type.dev_attr.attr,
- &iio_scan_el_timestamp.dev_attr.attr,
- &iio_const_attr_timestamp_index.dev_attr.attr,
- &iio_const_attr_timestamp_type.dev_attr.attr,
- NULL,
-};
-
-static struct attribute_group adis16400_scan_el_group = {
- .attrs = adis16400_scan_el_attrs,
- .name = "scan_elements",
-};
-
-/**
- * adis16400_poll_func_th() top half interrupt handler called by trigger
- * @private_data: iio_dev
- **/
-static void adis16400_poll_func_th(struct iio_dev *indio_dev, s64 time)
-{
- struct adis16400_state *st = iio_dev_get_devdata(indio_dev);
- st->last_timestamp = time;
- schedule_work(&st->work_trigger_to_ring);
- /* Indicate that this interrupt is being handled */
-
- /* Technically this is trigger related, but without this
- * handler running there is currently no way for the interrupt
- * to clear.
- */
-}
-
/**
* adis16400_spi_read_burst() - read all data registers
* @dev: device associated with child of actual device (iio_dev or iio_trig)
@@ -113,7 +27,7 @@
{
struct spi_message msg;
struct iio_dev *indio_dev = dev_get_drvdata(dev);
- struct adis16400_state *st = iio_dev_get_devdata(indio_dev);
+ struct adis16400_state *st = iio_priv(indio_dev);
u32 old_speed_hz = st->us->max_speed_hz;
int ret;
@@ -150,62 +64,122 @@
return ret;
}
+static const u16 read_all_tx_array[] = {
+ cpu_to_be16(ADIS16400_READ_REG(ADIS16400_SUPPLY_OUT)),
+ cpu_to_be16(ADIS16400_READ_REG(ADIS16400_XGYRO_OUT)),
+ cpu_to_be16(ADIS16400_READ_REG(ADIS16400_YGYRO_OUT)),
+ cpu_to_be16(ADIS16400_READ_REG(ADIS16400_ZGYRO_OUT)),
+ cpu_to_be16(ADIS16400_READ_REG(ADIS16400_XACCL_OUT)),
+ cpu_to_be16(ADIS16400_READ_REG(ADIS16400_YACCL_OUT)),
+ cpu_to_be16(ADIS16400_READ_REG(ADIS16400_ZACCL_OUT)),
+ cpu_to_be16(ADIS16400_READ_REG(ADIS16350_XTEMP_OUT)),
+ cpu_to_be16(ADIS16400_READ_REG(ADIS16350_YTEMP_OUT)),
+ cpu_to_be16(ADIS16400_READ_REG(ADIS16350_ZTEMP_OUT)),
+ cpu_to_be16(ADIS16400_READ_REG(ADIS16400_AUX_ADC)),
+};
+
+static int adis16350_spi_read_all(struct device *dev, u8 *rx)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ struct adis16400_state *st = iio_priv(indio_dev);
+
+ struct spi_message msg;
+ int i, j = 0, ret;
+ struct spi_transfer *xfers;
+
+ xfers = kzalloc(sizeof(*xfers)*indio_dev->ring->scan_count + 1,
+ GFP_KERNEL);
+ if (xfers == NULL)
+ return -ENOMEM;
+
+ for (i = 0; i < ARRAY_SIZE(read_all_tx_array); i++)
+ if (indio_dev->ring->scan_mask & (1 << i)) {
+ xfers[j].tx_buf = &read_all_tx_array[i];
+ xfers[j].bits_per_word = 16;
+ xfers[j].len = 2;
+ xfers[j + 1].rx_buf = rx + j*2;
+ j++;
+ }
+ xfers[j].bits_per_word = 16;
+ xfers[j].len = 2;
+
+ spi_message_init(&msg);
+ for (j = 0; j < indio_dev->ring->scan_count + 1; j++)
+ spi_message_add_tail(&xfers[j], &msg);
+
+ ret = spi_sync(st->us, &msg);
+ kfree(xfers);
+
+ return ret;
+}
+
/* Whilst this makes a lot of calls to iio_sw_ring functions - it is to device
* specific to be rolled into the core.
*/
-static void adis16400_trigger_bh_to_ring(struct work_struct *work_s)
+static irqreturn_t adis16400_trigger_handler(int irq, void *p)
{
- struct adis16400_state *st
- = container_of(work_s, struct adis16400_state,
- work_trigger_to_ring);
- struct iio_ring_buffer *ring = st->indio_dev->ring;
-
- int i = 0, j;
+ struct iio_poll_func *pf = p;
+ struct iio_dev *indio_dev = pf->private_data;
+ struct adis16400_state *st = iio_priv(indio_dev);
+ struct iio_ring_buffer *ring = indio_dev->ring;
+ int i = 0, j, ret = 0;
s16 *data;
- size_t datasize = ring->access.get_bytes_per_datum(ring);
+ size_t datasize = ring->access->get_bytes_per_datum(ring);
unsigned long mask = ring->scan_mask;
data = kmalloc(datasize , GFP_KERNEL);
if (data == NULL) {
dev_err(&st->us->dev, "memory alloc failed in ring bh");
- return;
+ return -ENOMEM;
}
- if (ring->scan_count)
- if (adis16400_spi_read_burst(&st->indio_dev->dev, st->rx) >= 0)
- for (; i < ring->scan_count; i++) {
+ if (ring->scan_count) {
+ if (st->variant->flags & ADIS16400_NO_BURST) {
+ ret = adis16350_spi_read_all(&indio_dev->dev, st->rx);
+ if (ret < 0)
+ return ret;
+ for (; i < ring->scan_count; i++)
+ data[i] = *(s16 *)(st->rx + i*2);
+ } else {
+ ret = adis16400_spi_read_burst(&indio_dev->dev, st->rx);
+ if (ret < 0)
+ return ret;
+ for (; i < indio_dev->ring->scan_count; i++) {
j = __ffs(mask);
mask &= ~(1 << j);
- data[i] = be16_to_cpup(
+ data[i] = be16_to_cpup(
(__be16 *)&(st->rx[j*2]));
}
-
+ }
+ }
/* Guaranteed to be aligned with 8 byte boundary */
if (ring->scan_timestamp)
- *((s64 *)(data + ((i + 3)/4)*4)) = st->last_timestamp;
+ *((s64 *)(data + ((i + 3)/4)*4)) = pf->timestamp;
+ ring->access->store_to(indio_dev->ring, (u8 *) data, pf->timestamp);
- ring->access.store_to(ring,
- (u8 *) data,
- st->last_timestamp);
-
- iio_trigger_notify_done(st->indio_dev->trig);
+ iio_trigger_notify_done(indio_dev->trig);
kfree(data);
- return;
+ return IRQ_HANDLED;
}
void adis16400_unconfigure_ring(struct iio_dev *indio_dev)
{
- kfree(indio_dev->pollfunc);
+ iio_dealloc_pollfunc(indio_dev->pollfunc);
iio_sw_rb_free(indio_dev->ring);
}
+static const struct iio_ring_setup_ops adis16400_ring_setup_ops = {
+ .preenable = &iio_sw_ring_preenable,
+ .postenable = &iio_triggered_ring_postenable,
+ .predisable = &iio_triggered_ring_predisable,
+};
+
int adis16400_configure_ring(struct iio_dev *indio_dev)
{
int ret = 0;
- struct adis16400_state *st = indio_dev->dev_data;
+ struct adis16400_state *st = iio_priv(indio_dev);
struct iio_ring_buffer *ring;
- INIT_WORK(&st->work_trigger_to_ring, adis16400_trigger_bh_to_ring);
ring = iio_sw_rb_allocate(indio_dev);
if (!ring) {
@@ -214,36 +188,29 @@
}
indio_dev->ring = ring;
/* Effectively select the ring buffer implementation */
- iio_ring_sw_register_funcs(&ring->access);
+ ring->access = &ring_sw_access_funcs;
ring->bpe = 2;
- ring->scan_el_attrs = &adis16400_scan_el_group;
ring->scan_timestamp = true;
- ring->preenable = &iio_sw_ring_preenable;
- ring->postenable = &iio_triggered_ring_postenable;
- ring->predisable = &iio_triggered_ring_predisable;
+ ring->setup_ops = &adis16400_ring_setup_ops;
ring->owner = THIS_MODULE;
-
/* Set default scan mode */
- iio_scan_mask_set(ring, iio_scan_el_in0_supply.number);
- iio_scan_mask_set(ring, iio_scan_el_gyro_x.number);
- iio_scan_mask_set(ring, iio_scan_el_gyro_y.number);
- iio_scan_mask_set(ring, iio_scan_el_gyro_z.number);
- iio_scan_mask_set(ring, iio_scan_el_accel_x.number);
- iio_scan_mask_set(ring, iio_scan_el_accel_y.number);
- iio_scan_mask_set(ring, iio_scan_el_accel_z.number);
- iio_scan_mask_set(ring, iio_scan_el_magn_x.number);
- iio_scan_mask_set(ring, iio_scan_el_magn_y.number);
- iio_scan_mask_set(ring, iio_scan_el_magn_z.number);
- iio_scan_mask_set(ring, iio_scan_el_temp.number);
- iio_scan_mask_set(ring, iio_scan_el_in1.number);
+ ring->scan_mask = st->variant->default_scan_mask;
+ ring->scan_count = hweight_long(st->variant->default_scan_mask);
- ret = iio_alloc_pollfunc(indio_dev, NULL, &adis16400_poll_func_th);
- if (ret)
+ indio_dev->pollfunc = iio_alloc_pollfunc(&iio_pollfunc_store_time,
+ &adis16400_trigger_handler,
+ IRQF_ONESHOT,
+ indio_dev,
+ "%s_consumer%d",
+ indio_dev->name,
+ indio_dev->id);
+ if (indio_dev->pollfunc == NULL) {
+ ret = -ENOMEM;
goto error_iio_sw_rb_free;
+ }
indio_dev->modes |= INDIO_RING_TRIGGERED;
return 0;
-
error_iio_sw_rb_free:
iio_sw_rb_free(indio_dev->ring);
return ret;
diff --git a/drivers/staging/iio/imu/adis16400_trigger.c b/drivers/staging/iio/imu/adis16400_trigger.c
index 36b5ff5..c6ec41a 100644
--- a/drivers/staging/iio/imu/adis16400_trigger.c
+++ b/drivers/staging/iio/imu/adis16400_trigger.c
@@ -13,113 +13,63 @@
#include "adis16400.h"
/**
- * adis16400_data_rdy_trig_poll() the event handler for the data rdy trig
- **/
-static int adis16400_data_rdy_trig_poll(struct iio_dev *dev_info,
- int index,
- s64 timestamp,
- int no_test)
-{
- struct adis16400_state *st = iio_dev_get_devdata(dev_info);
- struct iio_trigger *trig = st->trig;
-
- iio_trigger_poll(trig, timestamp);
-
- return IRQ_HANDLED;
-}
-
-IIO_EVENT_SH(data_rdy_trig, &adis16400_data_rdy_trig_poll);
-
-static IIO_TRIGGER_NAME_ATTR;
-
-static struct attribute *adis16400_trigger_attrs[] = {
- &dev_attr_name.attr,
- NULL,
-};
-
-static const struct attribute_group adis16400_trigger_attr_group = {
- .attrs = adis16400_trigger_attrs,
-};
-
-/**
* adis16400_data_rdy_trigger_set_state() set datardy interrupt state
**/
static int adis16400_data_rdy_trigger_set_state(struct iio_trigger *trig,
bool state)
{
- struct adis16400_state *st = trig->private_data;
- struct iio_dev *indio_dev = st->indio_dev;
- int ret = 0;
+ struct iio_dev *indio_dev = trig->private_data;
dev_dbg(&indio_dev->dev, "%s (%d)\n", __func__, state);
- ret = adis16400_set_irq(&st->indio_dev->dev, state);
- if (state == false) {
- iio_remove_event_from_list(&iio_event_data_rdy_trig,
- &indio_dev->interrupts[0]
- ->ev_list);
- /* possible quirk with handler currently worked around
- by ensuring the work queue is empty */
- flush_scheduled_work();
- } else {
- iio_add_event_to_list(&iio_event_data_rdy_trig,
- &indio_dev->interrupts[0]->ev_list);
- }
- return ret;
-}
-
-/**
- * adis16400_trig_try_reen() try renabling irq for data rdy trigger
- * @trig: the datardy trigger
- **/
-static int adis16400_trig_try_reen(struct iio_trigger *trig)
-{
- struct adis16400_state *st = trig->private_data;
- enable_irq(st->us->irq);
- /* irq reenabled so success! */
- return 0;
+ return adis16400_set_irq(indio_dev, state);
}
int adis16400_probe_trigger(struct iio_dev *indio_dev)
{
int ret;
- struct adis16400_state *st = indio_dev->dev_data;
+ struct adis16400_state *st = iio_priv(indio_dev);
- st->trig = iio_allocate_trigger();
- st->trig->name = kasprintf(GFP_KERNEL,
- "adis16400-dev%d",
- indio_dev->id);
- if (!st->trig->name) {
+ st->trig = iio_allocate_trigger("%s-dev%d",
+ spi_get_device_id(st->us)->name,
+ indio_dev->id);
+ if (st->trig == NULL) {
ret = -ENOMEM;
- goto error_free_trig;
+ goto error_ret;
}
+
+ ret = request_irq(st->us->irq,
+ &iio_trigger_generic_data_rdy_poll,
+ IRQF_TRIGGER_RISING,
+ "adis16400",
+ st->trig);
+ if (ret)
+ goto error_free_trig;
st->trig->dev.parent = &st->us->dev;
st->trig->owner = THIS_MODULE;
- st->trig->private_data = st;
+ st->trig->private_data = indio_dev;
st->trig->set_trigger_state = &adis16400_data_rdy_trigger_set_state;
- st->trig->try_reenable = &adis16400_trig_try_reen;
- st->trig->control_attrs = &adis16400_trigger_attr_group;
ret = iio_trigger_register(st->trig);
/* select default trigger */
indio_dev->trig = st->trig;
if (ret)
- goto error_free_trig_name;
+ goto error_free_irq;
return 0;
-error_free_trig_name:
- kfree(st->trig->name);
+error_free_irq:
+ free_irq(st->us->irq, st->trig);
error_free_trig:
iio_free_trigger(st->trig);
-
+error_ret:
return ret;
}
void adis16400_remove_trigger(struct iio_dev *indio_dev)
{
- struct adis16400_state *state = indio_dev->dev_data;
+ struct adis16400_state *st = iio_priv(indio_dev);
- iio_trigger_unregister(state->trig);
- kfree(state->trig->name);
- iio_free_trigger(state->trig);
+ iio_trigger_unregister(st->trig);
+ free_irq(st->us->irq, st->trig);
+ iio_free_trigger(st->trig);
}
diff --git a/drivers/staging/iio/industrialio-core.c b/drivers/staging/iio/industrialio-core.c
index 1795ee1..94d3bfa 100644
--- a/drivers/staging/iio/industrialio-core.c
+++ b/drivers/staging/iio/industrialio-core.c
@@ -16,7 +16,6 @@
#include <linux/err.h>
#include <linux/device.h>
#include <linux/fs.h>
-#include <linux/interrupt.h>
#include <linux/poll.h>
#include <linux/sched.h>
#include <linux/wait.h>
@@ -44,27 +43,55 @@
};
EXPORT_SYMBOL(iio_bus_type);
-void __iio_change_event(struct iio_detected_event_list *ev,
- int ev_code,
- s64 timestamp)
-{
- ev->ev.id = ev_code;
- ev->ev.timestamp = timestamp;
-}
-EXPORT_SYMBOL(__iio_change_event);
+static const char * const iio_chan_type_name_spec_shared[] = {
+ [IIO_TIMESTAMP] = "timestamp",
+ [IIO_ACCEL] = "accel",
+ [IIO_IN] = "in",
+ [IIO_CURRENT] = "current",
+ [IIO_POWER] = "power",
+ [IIO_IN_DIFF] = "in-in",
+ [IIO_GYRO] = "gyro",
+ [IIO_TEMP] = "temp",
+ [IIO_MAGN] = "magn",
+ [IIO_INCLI] = "incli",
+ [IIO_ROT] = "rot",
+ [IIO_INTENSITY] = "intensity",
+ [IIO_LIGHT] = "illuminance",
+ [IIO_ANGL] = "angl",
+};
-/* Used both in the interrupt line put events and the ring buffer ones */
+static const char * const iio_chan_type_name_spec_complex[] = {
+ [IIO_IN_DIFF] = "in%d-in%d",
+};
-/* Note that in it's current form someone has to be listening before events
- * are queued. Hence a client MUST open the chrdev before the ring buffer is
- * switched on.
- */
-int __iio_push_event(struct iio_event_interface *ev_int,
- int ev_code,
- s64 timestamp,
- struct iio_shared_ev_pointer *
- shared_pointer_p)
+static const char * const iio_modifier_names_light[] = {
+ [IIO_MOD_LIGHT_BOTH] = "both",
+ [IIO_MOD_LIGHT_IR] = "ir",
+};
+
+static const char * const iio_modifier_names_axial[] = {
+ [IIO_MOD_X] = "x",
+ [IIO_MOD_Y] = "y",
+ [IIO_MOD_Z] = "z",
+};
+
+/* relies on pairs of these shared then separate */
+static const char * const iio_chan_info_postfix[] = {
+ [IIO_CHAN_INFO_SCALE_SHARED/2] = "scale",
+ [IIO_CHAN_INFO_OFFSET_SHARED/2] = "offset",
+ [IIO_CHAN_INFO_CALIBSCALE_SHARED/2] = "calibscale",
+ [IIO_CHAN_INFO_CALIBBIAS_SHARED/2] = "calibbias",
+ [IIO_CHAN_INFO_PEAK_SHARED/2] = "peak_raw",
+ [IIO_CHAN_INFO_PEAK_SCALE_SHARED/2] = "peak_scale",
+};
+
+int iio_push_event(struct iio_dev *dev_info,
+ int ev_line,
+ int ev_code,
+ s64 timestamp)
{
+ struct iio_event_interface *ev_int
+ = &dev_info->event_interfaces[ev_line];
struct iio_detected_event_list *ev;
int ret = 0;
@@ -83,11 +110,8 @@
}
ev->ev.id = ev_code;
ev->ev.timestamp = timestamp;
- ev->shared_pointer = shared_pointer_p;
- if (ev->shared_pointer)
- shared_pointer_p->ev_p = ev;
- list_add_tail(&ev->list, &ev_int->det_events.list);
+ list_add_tail(&ev->list, &ev_int->det_events);
ev_int->current_events++;
mutex_unlock(&ev_int->event_list_lock);
wake_up_interruptible(&ev_int->wait);
@@ -97,85 +121,8 @@
error_ret:
return ret;
}
-EXPORT_SYMBOL(__iio_push_event);
-
-int iio_push_event(struct iio_dev *dev_info,
- int ev_line,
- int ev_code,
- s64 timestamp)
-{
- return __iio_push_event(&dev_info->event_interfaces[ev_line],
- ev_code, timestamp, NULL);
-}
EXPORT_SYMBOL(iio_push_event);
-/* Generic interrupt line interrupt handler */
-static irqreturn_t iio_interrupt_handler(int irq, void *_int_info)
-{
- struct iio_interrupt *int_info = _int_info;
- struct iio_dev *dev_info = int_info->dev_info;
- struct iio_event_handler_list *p;
- s64 time_ns;
- unsigned long flags;
-
- spin_lock_irqsave(&int_info->ev_list_lock, flags);
- if (list_empty(&int_info->ev_list)) {
- spin_unlock_irqrestore(&int_info->ev_list_lock, flags);
- return IRQ_NONE;
- }
-
- time_ns = iio_get_time_ns();
- list_for_each_entry(p, &int_info->ev_list, list) {
- disable_irq_nosync(irq);
- p->handler(dev_info, 1, time_ns, !(p->refcount > 1));
- }
- spin_unlock_irqrestore(&int_info->ev_list_lock, flags);
-
- return IRQ_HANDLED;
-}
-
-static struct iio_interrupt *iio_allocate_interrupt(void)
-{
- struct iio_interrupt *i = kmalloc(sizeof *i, GFP_KERNEL);
- if (i) {
- spin_lock_init(&i->ev_list_lock);
- INIT_LIST_HEAD(&i->ev_list);
- }
- return i;
-}
-
-/* Confirming the validity of supplied irq is left to drivers.*/
-int iio_register_interrupt_line(unsigned int irq,
- struct iio_dev *dev_info,
- int line_number,
- unsigned long type,
- const char *name)
-{
- int ret;
-
- dev_info->interrupts[line_number] = iio_allocate_interrupt();
- if (dev_info->interrupts[line_number] == NULL) {
- ret = -ENOMEM;
- goto error_ret;
- }
- dev_info->interrupts[line_number]->line_number = line_number;
- dev_info->interrupts[line_number]->irq = irq;
- dev_info->interrupts[line_number]->dev_info = dev_info;
-
- /* Possibly only request on demand?
- * Can see this may complicate the handling of interrupts.
- * However, with this approach we might end up handling lots of
- * events no-one cares about.*/
- ret = request_irq(irq,
- &iio_interrupt_handler,
- type,
- name,
- dev_info->interrupts[line_number]);
-
-error_ret:
- return ret;
-}
-EXPORT_SYMBOL(iio_register_interrupt_line);
/* This turns up an awful lot */
ssize_t iio_read_const_attr(struct device *dev,
@@ -186,54 +133,6 @@
}
EXPORT_SYMBOL(iio_read_const_attr);
-/* Before this runs the interrupt generator must have been disabled */
-void iio_unregister_interrupt_line(struct iio_dev *dev_info, int line_number)
-{
- /* make sure the interrupt handlers are all done */
- flush_scheduled_work();
- free_irq(dev_info->interrupts[line_number]->irq,
- dev_info->interrupts[line_number]);
- kfree(dev_info->interrupts[line_number]);
-}
-EXPORT_SYMBOL(iio_unregister_interrupt_line);
-
-/* Reference counted add and remove */
-void iio_add_event_to_list(struct iio_event_handler_list *el,
- struct list_head *head)
-{
- unsigned long flags;
- struct iio_interrupt *inter = to_iio_interrupt(head);
-
- /* take mutex to protect this element */
- mutex_lock(&el->exist_lock);
- if (el->refcount == 0) {
- /* Take the event list spin lock */
- spin_lock_irqsave(&inter->ev_list_lock, flags);
- list_add(&el->list, head);
- spin_unlock_irqrestore(&inter->ev_list_lock, flags);
- }
- el->refcount++;
- mutex_unlock(&el->exist_lock);
-}
-EXPORT_SYMBOL(iio_add_event_to_list);
-
-void iio_remove_event_from_list(struct iio_event_handler_list *el,
- struct list_head *head)
-{
- unsigned long flags;
- struct iio_interrupt *inter = to_iio_interrupt(head);
-
- mutex_lock(&el->exist_lock);
- el->refcount--;
- if (el->refcount == 0) {
- /* Take the event list spin lock */
- spin_lock_irqsave(&inter->ev_list_lock, flags);
- list_del_init(&el->list);
- spin_unlock_irqrestore(&inter->ev_list_lock, flags);
- }
- mutex_unlock(&el->exist_lock);
-}
-EXPORT_SYMBOL(iio_remove_event_from_list);
static ssize_t iio_event_chrdev_read(struct file *filep,
char __user *buf,
@@ -246,7 +145,7 @@
size_t len;
mutex_lock(&ev_int->event_list_lock);
- if (list_empty(&ev_int->det_events.list)) {
+ if (list_empty(&ev_int->det_events)) {
if (filep->f_flags & O_NONBLOCK) {
ret = -EAGAIN;
goto error_mutex_unlock;
@@ -255,14 +154,14 @@
/* Blocking on device; waiting for something to be there */
ret = wait_event_interruptible(ev_int->wait,
!list_empty(&ev_int
- ->det_events.list));
+ ->det_events));
if (ret)
goto error_ret;
/* Single access device so no one else can get the data */
mutex_lock(&ev_int->event_list_lock);
}
- el = list_first_entry(&ev_int->det_events.list,
+ el = list_first_entry(&ev_int->det_events,
struct iio_detected_event_list,
list);
len = sizeof el->ev;
@@ -273,18 +172,6 @@
list_del(&el->list);
ev_int->current_events--;
mutex_unlock(&ev_int->event_list_lock);
- /*
- * Possible concurency issue if an update of this event is on its way
- * through. May lead to new event being removed whilst the reported
- * event was the unescalated event. In typical use case this is not a
- * problem as userspace will say read half the buffer due to a 50%
- * full event which would make the correct 100% full incorrect anyway.
- */
- if (el->shared_pointer) {
- spin_lock(&el->shared_pointer->lock);
- (el->shared_pointer->ev_p) = NULL;
- spin_unlock(&el->shared_pointer->lock);
- }
kfree(el);
return len;
@@ -309,7 +196,7 @@
* clear out any awaiting events. The mask will prevent
* any new __iio_push_event calls running.
*/
- list_for_each_entry_safe(el, t, &ev_int->det_events.list, list) {
+ list_for_each_entry_safe(el, t, &ev_int->det_events, list) {
list_del(&el->list);
kfree(el);
}
@@ -381,10 +268,11 @@
spin_unlock(&iio_ida_lock);
}
-int iio_setup_ev_int(struct iio_event_interface *ev_int,
- const char *name,
- struct module *owner,
- struct device *dev)
+static int iio_setup_ev_int(struct iio_event_interface *ev_int,
+ const char *dev_name,
+ int index,
+ struct module *owner,
+ struct device *dev)
{
int ret, minor;
@@ -399,7 +287,7 @@
goto error_device_put;
}
ev_int->dev.devt = MKDEV(MAJOR(iio_devt), minor);
- dev_set_name(&ev_int->dev, "%s", name);
+ dev_set_name(&ev_int->dev, "%s:event%d", dev_name, index);
ret = device_add(&ev_int->dev);
if (ret)
@@ -412,7 +300,7 @@
/* discussion point - make this variable? */
ev_int->max_events = 10;
ev_int->current_events = 0;
- INIT_LIST_HEAD(&ev_int->det_events.list);
+ INIT_LIST_HEAD(&ev_int->det_events);
init_waitqueue_head(&ev_int->wait);
ev_int->handler.private = ev_int;
ev_int->handler.flags = 0;
@@ -433,7 +321,7 @@
return ret;
}
-void iio_free_ev_int(struct iio_event_interface *ev_int)
+static void iio_free_ev_int(struct iio_event_interface *ev_int)
{
device_unregister(&ev_int->dev);
put_device(&ev_int->dev);
@@ -488,24 +376,397 @@
bus_unregister(&iio_bus_type);
}
-static int iio_device_register_sysfs(struct iio_dev *dev_info)
+static ssize_t iio_read_channel_info(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
{
- int ret = 0;
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
+ int val, val2;
+ int ret = indio_dev->info->read_raw(indio_dev, this_attr->c,
+ &val, &val2, this_attr->address);
- ret = sysfs_create_group(&dev_info->dev.kobj, dev_info->attrs);
- if (ret) {
- dev_err(dev_info->dev.parent,
- "Failed to register sysfs hooks\n");
- goto error_ret;
+ if (ret < 0)
+ return ret;
+
+ if (ret == IIO_VAL_INT)
+ return sprintf(buf, "%d\n", val);
+ else if (ret == IIO_VAL_INT_PLUS_MICRO) {
+ if (val2 < 0)
+ return sprintf(buf, "-%d.%06u\n", val, -val2);
+ else
+ return sprintf(buf, "%d.%06u\n", val, val2);
+ } else
+ return 0;
+}
+
+static ssize_t iio_write_channel_info(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf,
+ size_t len)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
+ int ret, integer = 0, micro = 0, micro_mult = 100000;
+ bool integer_part = true, negative = false;
+
+ /* Assumes decimal - precision based on number of digits */
+ if (!indio_dev->info->write_raw)
+ return -EINVAL;
+ if (buf[0] == '-') {
+ negative = true;
+ buf++;
+ }
+ while (*buf) {
+ if ('0' <= *buf && *buf <= '9') {
+ if (integer_part)
+ integer = integer*10 + *buf - '0';
+ else {
+ micro += micro_mult*(*buf - '0');
+ if (micro_mult == 1)
+ break;
+ micro_mult /= 10;
+ }
+ } else if (*buf == '\n') {
+ if (*(buf + 1) == '\0')
+ break;
+ else
+ return -EINVAL;
+ } else if (*buf == '.') {
+ integer_part = false;
+ } else {
+ return -EINVAL;
+ }
+ buf++;
+ }
+ if (negative) {
+ if (integer)
+ integer = -integer;
+ else
+ micro = -micro;
}
+ ret = indio_dev->info->write_raw(indio_dev, this_attr->c,
+ integer, micro, this_attr->address);
+ if (ret)
+ return ret;
+
+ return len;
+}
+
+static int __iio_build_postfix(struct iio_chan_spec const *chan,
+ bool generic,
+ const char *postfix,
+ char **result)
+{
+ char *all_post;
+ /* 3 options - generic, extend_name, modified - if generic, extend_name
+ * and modified cannot apply.*/
+
+ if (generic || (!chan->modified && !chan->extend_name)) {
+ all_post = kasprintf(GFP_KERNEL, "%s", postfix);
+ } else if (chan->modified) {
+ const char *intermediate;
+ switch (chan->type) {
+ case IIO_INTENSITY:
+ intermediate
+ = iio_modifier_names_light[chan->channel2];
+ break;
+ case IIO_ACCEL:
+ case IIO_GYRO:
+ case IIO_MAGN:
+ case IIO_INCLI:
+ case IIO_ROT:
+ case IIO_ANGL:
+ intermediate
+ = iio_modifier_names_axial[chan->channel2];
+ break;
+ default:
+ return -EINVAL;
+ }
+ if (chan->extend_name)
+ all_post = kasprintf(GFP_KERNEL, "%s_%s_%s",
+ intermediate,
+ chan->extend_name,
+ postfix);
+ else
+ all_post = kasprintf(GFP_KERNEL, "%s_%s",
+ intermediate,
+ postfix);
+ } else
+ all_post = kasprintf(GFP_KERNEL, "%s_%s", chan->extend_name,
+ postfix);
+ if (all_post == NULL)
+ return -ENOMEM;
+ *result = all_post;
+ return 0;
+}
+
+int __iio_device_attr_init(struct device_attribute *dev_attr,
+ const char *postfix,
+ struct iio_chan_spec const *chan,
+ ssize_t (*readfunc)(struct device *dev,
+ struct device_attribute *attr,
+ char *buf),
+ ssize_t (*writefunc)(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf,
+ size_t len),
+ bool generic)
+{
+ int ret;
+ char *name_format, *full_postfix;
+ sysfs_attr_init(&dev_attr->attr);
+ ret = __iio_build_postfix(chan, generic, postfix, &full_postfix);
+ if (ret)
+ goto error_ret;
+
+ /* Special case for types that uses both channel numbers in naming */
+ if (chan->type == IIO_IN_DIFF && !generic)
+ name_format
+ = kasprintf(GFP_KERNEL, "%s_%s",
+ iio_chan_type_name_spec_complex[chan->type],
+ full_postfix);
+ else if (generic || !chan->indexed)
+ name_format
+ = kasprintf(GFP_KERNEL, "%s_%s",
+ iio_chan_type_name_spec_shared[chan->type],
+ full_postfix);
+ else
+ name_format
+ = kasprintf(GFP_KERNEL, "%s%d_%s",
+ iio_chan_type_name_spec_shared[chan->type],
+ chan->channel,
+ full_postfix);
+
+ if (name_format == NULL) {
+ ret = -ENOMEM;
+ goto error_free_full_postfix;
+ }
+ dev_attr->attr.name = kasprintf(GFP_KERNEL,
+ name_format,
+ chan->channel,
+ chan->channel2);
+ if (dev_attr->attr.name == NULL) {
+ ret = -ENOMEM;
+ goto error_free_name_format;
+ }
+
+ if (readfunc) {
+ dev_attr->attr.mode |= S_IRUGO;
+ dev_attr->show = readfunc;
+ }
+
+ if (writefunc) {
+ dev_attr->attr.mode |= S_IWUSR;
+ dev_attr->store = writefunc;
+ }
+ kfree(name_format);
+ kfree(full_postfix);
+
+ return 0;
+
+error_free_name_format:
+ kfree(name_format);
+error_free_full_postfix:
+ kfree(full_postfix);
error_ret:
return ret;
}
+void __iio_device_attr_deinit(struct device_attribute *dev_attr)
+{
+ kfree(dev_attr->attr.name);
+}
+
+int __iio_add_chan_devattr(const char *postfix,
+ const char *group,
+ struct iio_chan_spec const *chan,
+ ssize_t (*readfunc)(struct device *dev,
+ struct device_attribute *attr,
+ char *buf),
+ ssize_t (*writefunc)(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf,
+ size_t len),
+ int mask,
+ bool generic,
+ struct device *dev,
+ struct list_head *attr_list)
+{
+ int ret;
+ struct iio_dev_attr *iio_attr, *t;
+
+ iio_attr = kzalloc(sizeof *iio_attr, GFP_KERNEL);
+ if (iio_attr == NULL) {
+ ret = -ENOMEM;
+ goto error_ret;
+ }
+ ret = __iio_device_attr_init(&iio_attr->dev_attr,
+ postfix, chan,
+ readfunc, writefunc, generic);
+ if (ret)
+ goto error_iio_dev_attr_free;
+ iio_attr->c = chan;
+ iio_attr->address = mask;
+ list_for_each_entry(t, attr_list, l)
+ if (strcmp(t->dev_attr.attr.name,
+ iio_attr->dev_attr.attr.name) == 0) {
+ if (!generic)
+ dev_err(dev, "tried to double register : %s\n",
+ t->dev_attr.attr.name);
+ ret = -EBUSY;
+ goto error_device_attr_deinit;
+ }
+
+ ret = sysfs_add_file_to_group(&dev->kobj,
+ &iio_attr->dev_attr.attr, group);
+ if (ret < 0)
+ goto error_device_attr_deinit;
+
+ list_add(&iio_attr->l, attr_list);
+
+ return 0;
+
+error_device_attr_deinit:
+ __iio_device_attr_deinit(&iio_attr->dev_attr);
+error_iio_dev_attr_free:
+ kfree(iio_attr);
+error_ret:
+ return ret;
+}
+
+static int iio_device_add_channel_sysfs(struct iio_dev *dev_info,
+ struct iio_chan_spec const *chan)
+{
+ int ret, i;
+
+
+ if (chan->channel < 0)
+ return 0;
+ if (chan->processed_val)
+ ret = __iio_add_chan_devattr("input", NULL, chan,
+ &iio_read_channel_info,
+ NULL,
+ 0,
+ 0,
+ &dev_info->dev,
+ &dev_info->channel_attr_list);
+ else
+ ret = __iio_add_chan_devattr("raw", NULL, chan,
+ &iio_read_channel_info,
+ NULL,
+ 0,
+ 0,
+ &dev_info->dev,
+ &dev_info->channel_attr_list);
+ if (ret)
+ goto error_ret;
+
+ for_each_set_bit(i, &chan->info_mask, sizeof(long)*8) {
+ ret = __iio_add_chan_devattr(iio_chan_info_postfix[i/2],
+ NULL, chan,
+ &iio_read_channel_info,
+ &iio_write_channel_info,
+ (1 << i),
+ !(i%2),
+ &dev_info->dev,
+ &dev_info->channel_attr_list);
+ if (ret == -EBUSY && (i%2 == 0)) {
+ ret = 0;
+ continue;
+ }
+ if (ret < 0)
+ goto error_ret;
+ }
+error_ret:
+ return ret;
+}
+
+static void iio_device_remove_and_free_read_attr(struct iio_dev *dev_info,
+ struct iio_dev_attr *p)
+{
+ sysfs_remove_file_from_group(&dev_info->dev.kobj,
+ &p->dev_attr.attr, NULL);
+ kfree(p->dev_attr.attr.name);
+ kfree(p);
+}
+
+static ssize_t iio_show_dev_name(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ return sprintf(buf, "%s\n", indio_dev->name);
+}
+
+static DEVICE_ATTR(name, S_IRUGO, iio_show_dev_name, NULL);
+
+static int iio_device_register_sysfs(struct iio_dev *dev_info)
+{
+ int i, ret = 0;
+ struct iio_dev_attr *p, *n;
+
+ if (dev_info->info->attrs) {
+ ret = sysfs_create_group(&dev_info->dev.kobj,
+ dev_info->info->attrs);
+ if (ret) {
+ dev_err(dev_info->dev.parent,
+ "Failed to register sysfs hooks\n");
+ goto error_ret;
+ }
+ }
+
+ /*
+ * New channel registration method - relies on the fact a group does
+ * not need to be initialized if it is name is NULL.
+ */
+ INIT_LIST_HEAD(&dev_info->channel_attr_list);
+ if (dev_info->channels)
+ for (i = 0; i < dev_info->num_channels; i++) {
+ ret = iio_device_add_channel_sysfs(dev_info,
+ &dev_info
+ ->channels[i]);
+ if (ret < 0)
+ goto error_clear_attrs;
+ }
+ if (dev_info->name) {
+ ret = sysfs_add_file_to_group(&dev_info->dev.kobj,
+ &dev_attr_name.attr,
+ NULL);
+ if (ret)
+ goto error_clear_attrs;
+ }
+ return 0;
+
+error_clear_attrs:
+ list_for_each_entry_safe(p, n,
+ &dev_info->channel_attr_list, l) {
+ list_del(&p->l);
+ iio_device_remove_and_free_read_attr(dev_info, p);
+ }
+ if (dev_info->info->attrs)
+ sysfs_remove_group(&dev_info->dev.kobj, dev_info->info->attrs);
+error_ret:
+ return ret;
+
+}
+
static void iio_device_unregister_sysfs(struct iio_dev *dev_info)
{
- sysfs_remove_group(&dev_info->dev.kobj, dev_info->attrs);
+
+ struct iio_dev_attr *p, *n;
+ if (dev_info->name)
+ sysfs_remove_file_from_group(&dev_info->dev.kobj,
+ &dev_attr_name.attr,
+ NULL);
+ list_for_each_entry_safe(p, n, &dev_info->channel_attr_list, l) {
+ list_del(&p->l);
+ iio_device_remove_and_free_read_attr(dev_info, p);
+ }
+
+ if (dev_info->info->attrs)
+ sysfs_remove_group(&dev_info->dev.kobj, dev_info->info->attrs);
}
/* Return a negative errno on failure */
@@ -538,48 +799,209 @@
}
EXPORT_SYMBOL(iio_free_ida_val);
-static int iio_device_register_id(struct iio_dev *dev_info,
- struct ida *this_ida)
+static const char * const iio_ev_type_text[] = {
+ [IIO_EV_TYPE_THRESH] = "thresh",
+ [IIO_EV_TYPE_MAG] = "mag",
+ [IIO_EV_TYPE_ROC] = "roc"
+};
+
+static const char * const iio_ev_dir_text[] = {
+ [IIO_EV_DIR_EITHER] = "either",
+ [IIO_EV_DIR_RISING] = "rising",
+ [IIO_EV_DIR_FALLING] = "falling"
+};
+
+static ssize_t iio_ev_state_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf,
+ size_t len)
{
- dev_info->id = iio_get_new_ida_val(&iio_ida);
- if (dev_info->id < 0)
- return dev_info->id;
- return 0;
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
+ int ret;
+ bool val;
+
+ ret = strtobool(buf, &val);
+ if (ret < 0)
+ return ret;
+
+ ret = indio_dev->info->write_event_config(indio_dev,
+ this_attr->address,
+ val);
+ return (ret < 0) ? ret : len;
}
-static void iio_device_unregister_id(struct iio_dev *dev_info)
+static ssize_t iio_ev_state_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
{
- iio_free_ida_val(&iio_ida, dev_info->id);
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
+ int val = indio_dev->info->read_event_config(indio_dev,
+ this_attr->address);
+
+ if (val < 0)
+ return val;
+ else
+ return sprintf(buf, "%d\n", val);
+}
+
+static ssize_t iio_ev_value_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
+ int val, ret;
+
+ ret = indio_dev->info->read_event_value(indio_dev,
+ this_attr->address, &val);
+ if (ret < 0)
+ return ret;
+
+ return sprintf(buf, "%d\n", val);
+}
+
+static ssize_t iio_ev_value_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf,
+ size_t len)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
+ unsigned long val;
+ int ret;
+
+ ret = strict_strtoul(buf, 10, &val);
+ if (ret)
+ return ret;
+
+ ret = indio_dev->info->write_event_value(indio_dev, this_attr->address,
+ val);
+ if (ret < 0)
+ return ret;
+
+ return len;
+}
+
+static int iio_device_add_event_sysfs(struct iio_dev *dev_info,
+ struct iio_chan_spec const *chan)
+{
+
+ int ret = 0, i, mask;
+ char *postfix;
+ if (!chan->event_mask)
+ return 0;
+
+ for_each_set_bit(i, &chan->event_mask, sizeof(chan->event_mask)*8) {
+ postfix = kasprintf(GFP_KERNEL, "%s_%s_en",
+ iio_ev_type_text[i/IIO_EV_TYPE_MAX],
+ iio_ev_dir_text[i%IIO_EV_TYPE_MAX]);
+ if (postfix == NULL) {
+ ret = -ENOMEM;
+ goto error_ret;
+ }
+ switch (chan->type) {
+ /* Switch this to a table at some point */
+ case IIO_IN:
+ mask = IIO_UNMOD_EVENT_CODE(chan->type, chan->channel,
+ i/IIO_EV_TYPE_MAX,
+ i%IIO_EV_TYPE_MAX);
+ break;
+ case IIO_ACCEL:
+ mask = IIO_MOD_EVENT_CODE(chan->type, 0, chan->channel,
+ i/IIO_EV_TYPE_MAX,
+ i%IIO_EV_TYPE_MAX);
+ break;
+ case IIO_IN_DIFF:
+ mask = IIO_MOD_EVENT_CODE(chan->type, chan->channel,
+ chan->channel2,
+ i/IIO_EV_TYPE_MAX,
+ i%IIO_EV_TYPE_MAX);
+ break;
+ default:
+ printk(KERN_INFO "currently unhandled type of event\n");
+ }
+ ret = __iio_add_chan_devattr(postfix,
+ NULL,
+ chan,
+ &iio_ev_state_show,
+ iio_ev_state_store,
+ mask,
+ /*HACK. - limits us to one
+ event interface - fix by
+ extending the bitmask - but
+ how far*/
+ 0,
+ &dev_info->event_interfaces[0].dev,
+ &dev_info->event_interfaces[0].
+ dev_attr_list);
+ kfree(postfix);
+ if (ret)
+ goto error_ret;
+
+ postfix = kasprintf(GFP_KERNEL, "%s_%s_value",
+ iio_ev_type_text[i/IIO_EV_TYPE_MAX],
+ iio_ev_dir_text[i%IIO_EV_TYPE_MAX]);
+ if (postfix == NULL) {
+ ret = -ENOMEM;
+ goto error_ret;
+ }
+ ret = __iio_add_chan_devattr(postfix, NULL, chan,
+ iio_ev_value_show,
+ iio_ev_value_store,
+ mask,
+ 0,
+ &dev_info->event_interfaces[0]
+ .dev,
+ &dev_info->event_interfaces[0]
+ .dev_attr_list);
+ kfree(postfix);
+ if (ret)
+ goto error_ret;
+
+ }
+
+error_ret:
+ return ret;
+}
+
+static inline void __iio_remove_all_event_sysfs(struct iio_dev *dev_info,
+ const char *groupname,
+ int num)
+{
+ struct iio_dev_attr *p, *n;
+ list_for_each_entry_safe(p, n,
+ &dev_info->event_interfaces[num].
+ dev_attr_list, l) {
+ sysfs_remove_file_from_group(&dev_info
+ ->event_interfaces[num].dev.kobj,
+ &p->dev_attr.attr,
+ groupname);
+ kfree(p->dev_attr.attr.name);
+ kfree(p);
+ }
}
static inline int __iio_add_event_config_attrs(struct iio_dev *dev_info, int i)
{
+ int j;
int ret;
- /*p for adding, q for removing */
- struct attribute **attrp, **attrq;
-
- if (dev_info->event_conf_attrs && dev_info->event_conf_attrs[i].attrs) {
- attrp = dev_info->event_conf_attrs[i].attrs;
- while (*attrp) {
- ret = sysfs_add_file_to_group(&dev_info->dev.kobj,
- *attrp,
- dev_info
- ->event_attrs[i].name);
+ INIT_LIST_HEAD(&dev_info->event_interfaces[0].dev_attr_list);
+ /* Dynically created from the channels array */
+ if (dev_info->channels) {
+ for (j = 0; j < dev_info->num_channels; j++) {
+ ret = iio_device_add_event_sysfs(dev_info,
+ &dev_info
+ ->channels[j]);
if (ret)
- goto error_ret;
- attrp++;
+ goto error_clear_attrs;
}
}
return 0;
-error_ret:
- attrq = dev_info->event_conf_attrs[i].attrs;
- while (attrq != attrp) {
- sysfs_remove_file_from_group(&dev_info->dev.kobj,
- *attrq,
- dev_info->event_attrs[i].name);
- attrq++;
- }
+error_clear_attrs:
+ __iio_remove_all_event_sysfs(dev_info, NULL, i);
return ret;
}
@@ -587,20 +1009,7 @@
static inline int __iio_remove_event_config_attrs(struct iio_dev *dev_info,
int i)
{
- struct attribute **attrq;
-
- if (dev_info->event_conf_attrs
- && dev_info->event_conf_attrs[i].attrs) {
- attrq = dev_info->event_conf_attrs[i].attrs;
- while (*attrq) {
- sysfs_remove_file_from_group(&dev_info->dev.kobj,
- *attrq,
- dev_info
- ->event_attrs[i].name);
- attrq++;
- }
- }
-
+ __iio_remove_all_event_sysfs(dev_info, NULL, i);
return 0;
}
@@ -608,39 +1017,23 @@
{
int ret = 0, i, j;
- if (dev_info->num_interrupt_lines == 0)
+ if (dev_info->info->num_interrupt_lines == 0)
return 0;
dev_info->event_interfaces =
kzalloc(sizeof(struct iio_event_interface)
- *dev_info->num_interrupt_lines,
+ *dev_info->info->num_interrupt_lines,
GFP_KERNEL);
if (dev_info->event_interfaces == NULL) {
ret = -ENOMEM;
goto error_ret;
}
- dev_info->interrupts = kzalloc(sizeof(struct iio_interrupt *)
- *dev_info->num_interrupt_lines,
- GFP_KERNEL);
- if (dev_info->interrupts == NULL) {
- ret = -ENOMEM;
- goto error_free_event_interfaces;
- }
-
- for (i = 0; i < dev_info->num_interrupt_lines; i++) {
- dev_info->event_interfaces[i].owner = dev_info->driver_module;
-
- snprintf(dev_info->event_interfaces[i]._name, 20,
- "%s:event%d",
- dev_name(&dev_info->dev),
- i);
-
+ for (i = 0; i < dev_info->info->num_interrupt_lines; i++) {
ret = iio_setup_ev_int(&dev_info->event_interfaces[i],
- (const char *)(dev_info
- ->event_interfaces[i]
- ._name),
- dev_info->driver_module,
+ dev_name(&dev_info->dev),
+ i,
+ dev_info->info->driver_module,
&dev_info->dev);
if (ret) {
dev_err(&dev_info->dev,
@@ -650,10 +1043,13 @@
dev_set_drvdata(&dev_info->event_interfaces[i].dev,
(void *)dev_info);
- ret = sysfs_create_group(&dev_info
- ->event_interfaces[i]
- .dev.kobj,
- &dev_info->event_attrs[i]);
+
+ if (dev_info->info->event_attrs != NULL)
+ ret = sysfs_create_group(&dev_info
+ ->event_interfaces[i]
+ .dev.kobj,
+ &dev_info->info
+ ->event_attrs[i]);
if (ret) {
dev_err(&dev_info->dev,
@@ -662,7 +1058,7 @@
}
}
- for (i = 0; i < dev_info->num_interrupt_lines; i++) {
+ for (i = 0; i < dev_info->info->num_interrupt_lines; i++) {
ret = __iio_add_event_config_attrs(dev_info, i);
if (ret)
goto error_unregister_config_attrs;
@@ -673,17 +1069,16 @@
error_unregister_config_attrs:
for (j = 0; j < i; j++)
__iio_remove_event_config_attrs(dev_info, i);
- i = dev_info->num_interrupt_lines - 1;
+ i = dev_info->info->num_interrupt_lines - 1;
error_remove_sysfs_interfaces:
for (j = 0; j < i; j++)
- sysfs_remove_group(&dev_info
+ if (dev_info->info->event_attrs != NULL)
+ sysfs_remove_group(&dev_info
->event_interfaces[j].dev.kobj,
- &dev_info->event_attrs[j]);
+ &dev_info->info->event_attrs[j]);
error_free_setup_ev_ints:
for (j = 0; j < i; j++)
iio_free_ev_int(&dev_info->event_interfaces[j]);
- kfree(dev_info->interrupts);
-error_free_event_interfaces:
kfree(dev_info->event_interfaces);
error_ret:
@@ -694,25 +1089,25 @@
{
int i;
- if (dev_info->num_interrupt_lines == 0)
+ if (dev_info->info->num_interrupt_lines == 0)
return;
- for (i = 0; i < dev_info->num_interrupt_lines; i++)
- sysfs_remove_group(&dev_info
- ->event_interfaces[i].dev.kobj,
- &dev_info->event_attrs[i]);
+ for (i = 0; i < dev_info->info->num_interrupt_lines; i++) {
+ __iio_remove_event_config_attrs(dev_info, i);
+ if (dev_info->info->event_attrs != NULL)
+ sysfs_remove_group(&dev_info
+ ->event_interfaces[i].dev.kobj,
+ &dev_info->info->event_attrs[i]);
+ }
- for (i = 0; i < dev_info->num_interrupt_lines; i++)
+ for (i = 0; i < dev_info->info->num_interrupt_lines; i++)
iio_free_ev_int(&dev_info->event_interfaces[i]);
- kfree(dev_info->interrupts);
kfree(dev_info->event_interfaces);
}
static void iio_dev_release(struct device *device)
{
- struct iio_dev *dev = to_iio_dev(device);
-
iio_put();
- kfree(dev);
+ kfree(to_iio_dev(device));
}
static struct device_type iio_dev_type = {
@@ -720,9 +1115,20 @@
.release = iio_dev_release,
};
-struct iio_dev *iio_allocate_device(void)
+struct iio_dev *iio_allocate_device(int sizeof_priv)
{
- struct iio_dev *dev = kzalloc(sizeof *dev, GFP_KERNEL);
+ struct iio_dev *dev;
+ size_t alloc_size;
+
+ alloc_size = sizeof(struct iio_dev);
+ if (sizeof_priv) {
+ alloc_size = ALIGN(alloc_size, IIO_ALIGN);
+ alloc_size += sizeof_priv;
+ }
+ /* ensure 32-byte alignment of whole construct ? */
+ alloc_size += IIO_ALIGN - 1;
+
+ dev = kzalloc(alloc_size, GFP_KERNEL);
if (dev) {
dev->dev.type = &iio_dev_type;
@@ -748,8 +1154,9 @@
{
int ret;
- ret = iio_device_register_id(dev_info, &iio_ida);
- if (ret) {
+ dev_info->id = iio_get_new_ida_val(&iio_ida);
+ if (dev_info->id < 0) {
+ ret = dev_info->id;
dev_err(&dev_info->dev, "Failed to get id\n");
goto error_ret;
}
@@ -780,7 +1187,7 @@
error_del_device:
device_del(&dev_info->dev);
error_free_ida:
- iio_device_unregister_id(dev_info);
+ iio_free_ida_val(&iio_ida, dev_info->id);
error_ret:
return ret;
}
@@ -792,7 +1199,7 @@
iio_device_unregister_trigger_consumer(dev_info);
iio_device_unregister_eventset(dev_info);
iio_device_unregister_sysfs(dev_info);
- iio_device_unregister_id(dev_info);
+ iio_free_ida_val(&iio_ida, dev_info->id);
device_unregister(&dev_info->dev);
}
EXPORT_SYMBOL(iio_device_unregister);
diff --git a/drivers/staging/iio/industrialio-ring.c b/drivers/staging/iio/industrialio-ring.c
index bd4373a..843eb82 100644
--- a/drivers/staging/iio/industrialio-ring.c
+++ b/drivers/staging/iio/industrialio-ring.c
@@ -18,37 +18,11 @@
#include <linux/fs.h>
#include <linux/cdev.h>
#include <linux/slab.h>
+#include <linux/poll.h>
#include "iio.h"
#include "ring_generic.h"
-int iio_push_ring_event(struct iio_ring_buffer *ring_buf,
- int event_code,
- s64 timestamp)
-{
- return __iio_push_event(&ring_buf->ev_int,
- event_code,
- timestamp,
- &ring_buf->shared_ev_pointer);
-}
-EXPORT_SYMBOL(iio_push_ring_event);
-
-int iio_push_or_escallate_ring_event(struct iio_ring_buffer *ring_buf,
- int event_code,
- s64 timestamp)
-{
- if (ring_buf->shared_ev_pointer.ev_p)
- __iio_change_event(ring_buf->shared_ev_pointer.ev_p,
- event_code,
- timestamp);
- else
- return iio_push_ring_event(ring_buf,
- event_code,
- timestamp);
- return 0;
-}
-EXPORT_SYMBOL(iio_push_or_escallate_ring_event);
-
/**
* iio_ring_open() - chrdev file open for ring buffer access
*
@@ -62,8 +36,8 @@
struct iio_ring_buffer *rb = hand->private;
filp->private_data = hand->private;
- if (rb->access.mark_in_use)
- rb->access.mark_in_use(rb);
+ if (rb->access->mark_in_use)
+ rb->access->mark_in_use(rb);
return 0;
}
@@ -81,184 +55,316 @@
struct iio_ring_buffer *rb = hand->private;
clear_bit(IIO_BUSY_BIT_POS, &rb->access_handler.flags);
- if (rb->access.unmark_in_use)
- rb->access.unmark_in_use(rb);
+ if (rb->access->unmark_in_use)
+ rb->access->unmark_in_use(rb);
return 0;
}
/**
- * iio_ring_rip_outer() - chrdev read for ring buffer access
+ * iio_ring_read_first_n_outer() - chrdev read for ring buffer access
*
* This function relies on all ring buffer implementations having an
* iio_ring _bufer as their first element.
**/
-static ssize_t iio_ring_rip_outer(struct file *filp, char __user *buf,
- size_t count, loff_t *f_ps)
+static ssize_t iio_ring_read_first_n_outer(struct file *filp, char __user *buf,
+ size_t n, loff_t *f_ps)
{
struct iio_ring_buffer *rb = filp->private_data;
- int ret, dead_offset;
- /* rip lots must exist. */
- if (!rb->access.rip_lots)
+ if (!rb->access->read_first_n)
return -EINVAL;
- ret = rb->access.rip_lots(rb, count, buf, &dead_offset);
+ return rb->access->read_first_n(rb, n, buf);
+}
- return ret;
+/**
+ * iio_ring_poll() - poll the ring to find out if it has data
+ */
+static unsigned int iio_ring_poll(struct file *filp,
+ struct poll_table_struct *wait)
+{
+ struct iio_ring_buffer *rb = filp->private_data;
+
+ poll_wait(filp, &rb->pollq, wait);
+ if (rb->stufftoread)
+ return POLLIN | POLLRDNORM;
+ /* need a way of knowing if there may be enough data... */
+ return 0;
}
static const struct file_operations iio_ring_fileops = {
- .read = iio_ring_rip_outer,
+ .read = iio_ring_read_first_n_outer,
.release = iio_ring_release,
.open = iio_ring_open,
+ .poll = iio_ring_poll,
.owner = THIS_MODULE,
.llseek = noop_llseek,
};
-/**
- * __iio_request_ring_buffer_event_chrdev() - allocate ring event chrdev
- * @buf: ring buffer whose event chrdev we are allocating
- * @id: id of this ring buffer (typically 0)
- * @owner: the module who owns the ring buffer (for ref counting)
- * @dev: device with which the chrdev is associated
- **/
-static inline int
-__iio_request_ring_buffer_event_chrdev(struct iio_ring_buffer *buf,
- int id,
- struct module *owner,
- struct device *dev)
-{
- int ret;
-
- snprintf(buf->ev_int._name, sizeof(buf->ev_int._name),
- "%s:event%d",
- dev_name(&buf->dev),
- id);
- ret = iio_setup_ev_int(&(buf->ev_int),
- buf->ev_int._name,
- owner,
- dev);
- if (ret)
- goto error_ret;
- return 0;
-
-error_ret:
- return ret;
-}
-
-static inline void
-__iio_free_ring_buffer_event_chrdev(struct iio_ring_buffer *buf)
-{
- iio_free_ev_int(&(buf->ev_int));
-}
-
-static void iio_ring_access_release(struct device *dev)
+void iio_ring_access_release(struct device *dev)
{
struct iio_ring_buffer *buf
- = access_dev_to_iio_ring_buffer(dev);
+ = container_of(dev, struct iio_ring_buffer, dev);
cdev_del(&buf->access_handler.chrdev);
iio_device_free_chrdev_minor(MINOR(dev->devt));
}
-
-static struct device_type iio_ring_access_type = {
- .release = iio_ring_access_release,
-};
+EXPORT_SYMBOL(iio_ring_access_release);
static inline int
-__iio_request_ring_buffer_access_chrdev(struct iio_ring_buffer *buf,
- int id,
- struct module *owner)
+__iio_request_ring_buffer_chrdev(struct iio_ring_buffer *buf,
+ struct module *owner,
+ int id)
{
- int ret, minor;
+ int ret;
buf->access_handler.flags = 0;
+ buf->dev.bus = &iio_bus_type;
+ device_initialize(&buf->dev);
- buf->access_dev.parent = &buf->dev;
- buf->access_dev.bus = &iio_bus_type;
- buf->access_dev.type = &iio_ring_access_type;
- device_initialize(&buf->access_dev);
-
- minor = iio_device_get_chrdev_minor();
- if (minor < 0) {
- ret = minor;
+ ret = iio_device_get_chrdev_minor();
+ if (ret < 0)
goto error_device_put;
- }
- buf->access_dev.devt = MKDEV(MAJOR(iio_devt), minor);
-
- buf->access_id = id;
-
- dev_set_name(&buf->access_dev, "%s:access%d",
- dev_name(&buf->dev),
- buf->access_id);
- ret = device_add(&buf->access_dev);
+ buf->dev.devt = MKDEV(MAJOR(iio_devt), ret);
+ dev_set_name(&buf->dev, "%s:buffer%d",
+ dev_name(buf->dev.parent),
+ id);
+ ret = device_add(&buf->dev);
if (ret < 0) {
- printk(KERN_ERR "failed to add the ring access dev\n");
+ printk(KERN_ERR "failed to add the ring dev\n");
goto error_device_put;
}
-
cdev_init(&buf->access_handler.chrdev, &iio_ring_fileops);
buf->access_handler.chrdev.owner = owner;
-
- ret = cdev_add(&buf->access_handler.chrdev, buf->access_dev.devt, 1);
+ ret = cdev_add(&buf->access_handler.chrdev, buf->dev.devt, 1);
if (ret) {
- printk(KERN_ERR "failed to allocate ring access chrdev\n");
+ printk(KERN_ERR "failed to allocate ring chrdev\n");
goto error_device_unregister;
}
return 0;
error_device_unregister:
- device_unregister(&buf->access_dev);
+ device_unregister(&buf->dev);
error_device_put:
- put_device(&buf->access_dev);
+ put_device(&buf->dev);
return ret;
}
-static void __iio_free_ring_buffer_access_chrdev(struct iio_ring_buffer *buf)
+static void __iio_free_ring_buffer_chrdev(struct iio_ring_buffer *buf)
{
- device_unregister(&buf->access_dev);
+ device_unregister(&buf->dev);
}
void iio_ring_buffer_init(struct iio_ring_buffer *ring,
struct iio_dev *dev_info)
{
- if (ring->access.mark_param_change)
- ring->access.mark_param_change(ring);
ring->indio_dev = dev_info;
- ring->ev_int.private = ring;
ring->access_handler.private = ring;
- ring->shared_ev_pointer.ev_p = NULL;
- spin_lock_init(&ring->shared_ev_pointer.lock);
+ init_waitqueue_head(&ring->pollq);
}
EXPORT_SYMBOL(iio_ring_buffer_init);
-int iio_ring_buffer_register(struct iio_ring_buffer *ring, int id)
+static ssize_t iio_show_scan_index(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ return sprintf(buf, "%u\n", to_iio_dev_attr(attr)->c->scan_index);
+}
+
+static ssize_t iio_show_fixed_type(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
+ return sprintf(buf, "%c%d/%d>>%u\n",
+ this_attr->c->scan_type.sign,
+ this_attr->c->scan_type.realbits,
+ this_attr->c->scan_type.storagebits,
+ this_attr->c->scan_type.shift);
+}
+
+static ssize_t iio_scan_el_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ int ret;
+ struct iio_ring_buffer *ring = dev_get_drvdata(dev);
+
+ ret = iio_scan_mask_query(ring, to_iio_dev_attr(attr)->address);
+ if (ret < 0)
+ return ret;
+ return sprintf(buf, "%d\n", ret);
+}
+
+static int iio_scan_mask_clear(struct iio_ring_buffer *ring, int bit)
+{
+ if (bit > IIO_MAX_SCAN_LENGTH)
+ return -EINVAL;
+ ring->scan_mask &= ~(1 << bit);
+ ring->scan_count--;
+ return 0;
+}
+
+static ssize_t iio_scan_el_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf,
+ size_t len)
+{
+ int ret = 0;
+ bool state;
+ struct iio_ring_buffer *ring = dev_get_drvdata(dev);
+ struct iio_dev *indio_dev = ring->indio_dev;
+ struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
+
+ state = !(buf[0] == '0');
+ mutex_lock(&indio_dev->mlock);
+ if (indio_dev->currentmode == INDIO_RING_TRIGGERED) {
+ ret = -EBUSY;
+ goto error_ret;
+ }
+ ret = iio_scan_mask_query(ring, this_attr->address);
+ if (ret < 0)
+ goto error_ret;
+ if (!state && ret) {
+ ret = iio_scan_mask_clear(ring, this_attr->address);
+ if (ret)
+ goto error_ret;
+ } else if (state && !ret) {
+ ret = iio_scan_mask_set(ring, this_attr->address);
+ if (ret)
+ goto error_ret;
+ }
+
+error_ret:
+ mutex_unlock(&indio_dev->mlock);
+
+ return ret ? ret : len;
+
+}
+
+static ssize_t iio_scan_el_ts_show(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct iio_ring_buffer *ring = dev_get_drvdata(dev);
+ return sprintf(buf, "%d\n", ring->scan_timestamp);
+}
+
+static ssize_t iio_scan_el_ts_store(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf,
+ size_t len)
+{
+ int ret = 0;
+ struct iio_ring_buffer *ring = dev_get_drvdata(dev);
+ struct iio_dev *indio_dev = ring->indio_dev;
+ bool state;
+ state = !(buf[0] == '0');
+ mutex_lock(&indio_dev->mlock);
+ if (indio_dev->currentmode == INDIO_RING_TRIGGERED) {
+ ret = -EBUSY;
+ goto error_ret;
+ }
+ ring->scan_timestamp = state;
+error_ret:
+ mutex_unlock(&indio_dev->mlock);
+
+ return ret ? ret : len;
+}
+
+static int iio_ring_add_channel_sysfs(struct iio_ring_buffer *ring,
+ const struct iio_chan_spec *chan)
{
int ret;
- ring->id = id;
-
- dev_set_name(&ring->dev, "%s:buffer%d",
- dev_name(ring->dev.parent),
- ring->id);
- ret = device_add(&ring->dev);
+ ret = __iio_add_chan_devattr("index", "scan_elements",
+ chan,
+ &iio_show_scan_index,
+ NULL,
+ 0,
+ 0,
+ &ring->dev,
+ &ring->scan_el_dev_attr_list);
if (ret)
goto error_ret;
- ret = __iio_request_ring_buffer_event_chrdev(ring,
- 0,
- ring->owner,
- &ring->dev);
+ ret = __iio_add_chan_devattr("type", "scan_elements",
+ chan,
+ &iio_show_fixed_type,
+ NULL,
+ 0,
+ 0,
+ &ring->dev,
+ &ring->scan_el_dev_attr_list);
if (ret)
- goto error_remove_device;
+ goto error_ret;
- ret = __iio_request_ring_buffer_access_chrdev(ring,
- 0,
- ring->owner);
+ if (chan->type != IIO_TIMESTAMP)
+ ret = __iio_add_chan_devattr("en", "scan_elements",
+ chan,
+ &iio_scan_el_show,
+ &iio_scan_el_store,
+ chan->scan_index,
+ 0,
+ &ring->dev,
+ &ring->scan_el_dev_attr_list);
+ else
+ ret = __iio_add_chan_devattr("en", "scan_elements",
+ chan,
+ &iio_scan_el_ts_show,
+ &iio_scan_el_ts_store,
+ chan->scan_index,
+ 0,
+ &ring->dev,
+ &ring->scan_el_dev_attr_list);
+error_ret:
+ return ret;
+}
+static void iio_ring_remove_and_free_scan_dev_attr(struct iio_ring_buffer *ring,
+ struct iio_dev_attr *p)
+{
+ sysfs_remove_file_from_group(&ring->dev.kobj,
+ &p->dev_attr.attr, "scan_elements");
+ kfree(p->dev_attr.attr.name);
+ kfree(p);
+}
+
+static struct attribute *iio_scan_el_dummy_attrs[] = {
+ NULL
+};
+
+static struct attribute_group iio_scan_el_dummy_group = {
+ .name = "scan_elements",
+ .attrs = iio_scan_el_dummy_attrs
+};
+
+static void __iio_ring_attr_cleanup(struct iio_ring_buffer *ring)
+{
+ struct iio_dev_attr *p, *n;
+ int anydynamic = !list_empty(&ring->scan_el_dev_attr_list);
+ list_for_each_entry_safe(p, n,
+ &ring->scan_el_dev_attr_list, l)
+ iio_ring_remove_and_free_scan_dev_attr(ring, p);
+
+ if (ring->scan_el_attrs)
+ sysfs_remove_group(&ring->dev.kobj,
+ ring->scan_el_attrs);
+ else if (anydynamic)
+ sysfs_remove_group(&ring->dev.kobj,
+ &iio_scan_el_dummy_group);
+}
+
+int iio_ring_buffer_register_ex(struct iio_ring_buffer *ring, int id,
+ const struct iio_chan_spec *channels,
+ int num_channels)
+{
+ int ret, i;
+
+ ret = __iio_request_ring_buffer_chrdev(ring, ring->owner, id);
if (ret)
- goto error_free_ring_buffer_event_chrdev;
+ goto error_ret;
if (ring->scan_el_attrs) {
ret = sysfs_create_group(&ring->dev.kobj,
@@ -266,29 +372,39 @@
if (ret) {
dev_err(&ring->dev,
"Failed to add sysfs scan elements\n");
- goto error_free_ring_buffer_event_chrdev;
+ goto error_free_ring_buffer_chrdev;
+ }
+ } else if (channels) {
+ ret = sysfs_create_group(&ring->dev.kobj,
+ &iio_scan_el_dummy_group);
+ if (ret)
+ goto error_free_ring_buffer_chrdev;
+ }
+
+ INIT_LIST_HEAD(&ring->scan_el_dev_attr_list);
+ if (channels) {
+ /* new magic */
+ for (i = 0; i < num_channels; i++) {
+ ret = iio_ring_add_channel_sysfs(ring, &channels[i]);
+ if (ret < 0)
+ goto error_cleanup_dynamic;
}
}
- return ret;
-error_free_ring_buffer_event_chrdev:
- __iio_free_ring_buffer_event_chrdev(ring);
-error_remove_device:
- device_del(&ring->dev);
+ return 0;
+error_cleanup_dynamic:
+ __iio_ring_attr_cleanup(ring);
+error_free_ring_buffer_chrdev:
+ __iio_free_ring_buffer_chrdev(ring);
error_ret:
return ret;
}
-EXPORT_SYMBOL(iio_ring_buffer_register);
+EXPORT_SYMBOL(iio_ring_buffer_register_ex);
void iio_ring_buffer_unregister(struct iio_ring_buffer *ring)
{
- if (ring->scan_el_attrs)
- sysfs_remove_group(&ring->dev.kobj,
- ring->scan_el_attrs);
-
- __iio_free_ring_buffer_access_chrdev(ring);
- __iio_free_ring_buffer_event_chrdev(ring);
- device_del(&ring->dev);
+ __iio_ring_attr_cleanup(ring);
+ __iio_free_ring_buffer_chrdev(ring);
}
EXPORT_SYMBOL(iio_ring_buffer_unregister);
@@ -296,14 +412,13 @@
struct device_attribute *attr,
char *buf)
{
- int len = 0;
struct iio_ring_buffer *ring = dev_get_drvdata(dev);
- if (ring->access.get_length)
- len = sprintf(buf, "%d\n",
- ring->access.get_length(ring));
+ if (ring->access->get_length)
+ return sprintf(buf, "%d\n",
+ ring->access->get_length(ring));
- return len;
+ return 0;
}
EXPORT_SYMBOL(iio_read_ring_length);
@@ -315,18 +430,19 @@
int ret;
ulong val;
struct iio_ring_buffer *ring = dev_get_drvdata(dev);
+
ret = strict_strtoul(buf, 10, &val);
if (ret)
return ret;
- if (ring->access.get_length)
- if (val == ring->access.get_length(ring))
+ if (ring->access->get_length)
+ if (val == ring->access->get_length(ring))
return len;
- if (ring->access.set_length) {
- ring->access.set_length(ring, val);
- if (ring->access.mark_param_change)
- ring->access.mark_param_change(ring);
+ if (ring->access->set_length) {
+ ring->access->set_length(ring, val);
+ if (ring->access->mark_param_change)
+ ring->access->mark_param_change(ring);
}
return len;
@@ -337,14 +453,13 @@
struct device_attribute *attr,
char *buf)
{
- int len = 0;
struct iio_ring_buffer *ring = dev_get_drvdata(dev);
- if (ring->access.get_bytes_per_datum)
- len = sprintf(buf, "%d\n",
- ring->access.get_bytes_per_datum(ring));
+ if (ring->access->get_bytes_per_datum)
+ return sprintf(buf, "%d\n",
+ ring->access->get_bytes_per_datum(ring));
- return len;
+ return 0;
}
EXPORT_SYMBOL(iio_read_ring_bytes_per_datum);
@@ -368,8 +483,8 @@
goto done;
}
if (requested_state) {
- if (ring->preenable) {
- ret = ring->preenable(dev_info);
+ if (ring->setup_ops->preenable) {
+ ret = ring->setup_ops->preenable(dev_info);
if (ret) {
printk(KERN_ERR
"Buffer not started:"
@@ -377,8 +492,8 @@
goto error_ret;
}
}
- if (ring->access.request_update) {
- ret = ring->access.request_update(ring);
+ if (ring->access->request_update) {
+ ret = ring->access->request_update(ring);
if (ret) {
printk(KERN_INFO
"Buffer not started:"
@@ -386,16 +501,16 @@
goto error_ret;
}
}
- if (ring->access.mark_in_use)
- ring->access.mark_in_use(ring);
+ if (ring->access->mark_in_use)
+ ring->access->mark_in_use(ring);
/* Definitely possible for devices to support both of these.*/
if (dev_info->modes & INDIO_RING_TRIGGERED) {
if (!dev_info->trig) {
printk(KERN_INFO
"Buffer not started: no trigger\n");
ret = -EINVAL;
- if (ring->access.unmark_in_use)
- ring->access.unmark_in_use(ring);
+ if (ring->access->unmark_in_use)
+ ring->access->unmark_in_use(ring);
goto error_ret;
}
dev_info->currentmode = INDIO_RING_TRIGGERED;
@@ -406,32 +521,31 @@
goto error_ret;
}
- if (ring->postenable) {
-
- ret = ring->postenable(dev_info);
+ if (ring->setup_ops->postenable) {
+ ret = ring->setup_ops->postenable(dev_info);
if (ret) {
printk(KERN_INFO
"Buffer not started:"
"postenable failed\n");
- if (ring->access.unmark_in_use)
- ring->access.unmark_in_use(ring);
+ if (ring->access->unmark_in_use)
+ ring->access->unmark_in_use(ring);
dev_info->currentmode = previous_mode;
- if (ring->postdisable)
- ring->postdisable(dev_info);
+ if (ring->setup_ops->postdisable)
+ ring->setup_ops->postdisable(dev_info);
goto error_ret;
}
}
} else {
- if (ring->predisable) {
- ret = ring->predisable(dev_info);
+ if (ring->setup_ops->predisable) {
+ ret = ring->setup_ops->predisable(dev_info);
if (ret)
goto error_ret;
}
- if (ring->access.unmark_in_use)
- ring->access.unmark_in_use(ring);
+ if (ring->access->unmark_in_use)
+ ring->access->unmark_in_use(ring);
dev_info->currentmode = INDIO_DIRECT_MODE;
- if (ring->postdisable) {
- ret = ring->postdisable(dev_info);
+ if (ring->setup_ops->postdisable) {
+ ret = ring->setup_ops->postdisable(dev_info);
if (ret)
goto error_ret;
}
@@ -445,6 +559,7 @@
return ret;
}
EXPORT_SYMBOL(iio_store_ring_enable);
+
ssize_t iio_show_ring_enable(struct device *dev,
struct device_attribute *attr,
char *buf)
@@ -455,89 +570,27 @@
}
EXPORT_SYMBOL(iio_show_ring_enable);
-ssize_t iio_scan_el_show(struct device *dev,
- struct device_attribute *attr,
- char *buf)
+int iio_sw_ring_preenable(struct iio_dev *indio_dev)
{
- int ret;
- struct iio_ring_buffer *ring = dev_get_drvdata(dev);
- struct iio_scan_el *this_el = to_iio_scan_el(attr);
+ struct iio_ring_buffer *ring = indio_dev->ring;
+ size_t size;
+ dev_dbg(&indio_dev->dev, "%s\n", __func__);
+ /* Check if there are any scan elements enabled, if not fail*/
+ if (!(ring->scan_count || ring->scan_timestamp))
+ return -EINVAL;
+ if (ring->scan_timestamp)
+ if (ring->scan_count)
+ /* Timestamp (aligned to s64) and data */
+ size = (((ring->scan_count * ring->bpe)
+ + sizeof(s64) - 1)
+ & ~(sizeof(s64) - 1))
+ + sizeof(s64);
+ else /* Timestamp only */
+ size = sizeof(s64);
+ else /* Data only */
+ size = ring->scan_count * ring->bpe;
+ ring->access->set_bytes_per_datum(ring, size);
- ret = iio_scan_mask_query(ring, this_el->number);
- if (ret < 0)
- return ret;
- return sprintf(buf, "%d\n", ret);
+ return 0;
}
-EXPORT_SYMBOL(iio_scan_el_show);
-
-ssize_t iio_scan_el_store(struct device *dev,
- struct device_attribute *attr,
- const char *buf,
- size_t len)
-{
- int ret = 0;
- bool state;
- struct iio_ring_buffer *ring = dev_get_drvdata(dev);
- struct iio_dev *indio_dev = ring->indio_dev;
- struct iio_scan_el *this_el = to_iio_scan_el(attr);
-
- state = !(buf[0] == '0');
- mutex_lock(&indio_dev->mlock);
- if (indio_dev->currentmode == INDIO_RING_TRIGGERED) {
- ret = -EBUSY;
- goto error_ret;
- }
- ret = iio_scan_mask_query(ring, this_el->number);
- if (ret < 0)
- goto error_ret;
- if (!state && ret) {
- ret = iio_scan_mask_clear(ring, this_el->number);
- if (ret)
- goto error_ret;
- } else if (state && !ret) {
- ret = iio_scan_mask_set(ring, this_el->number);
- if (ret)
- goto error_ret;
- }
- if (this_el->set_state)
- ret = this_el->set_state(this_el, indio_dev, state);
-error_ret:
- mutex_unlock(&indio_dev->mlock);
-
- return ret ? ret : len;
-
-}
-EXPORT_SYMBOL(iio_scan_el_store);
-
-ssize_t iio_scan_el_ts_show(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- struct iio_ring_buffer *ring = dev_get_drvdata(dev);
- return sprintf(buf, "%d\n", ring->scan_timestamp);
-}
-EXPORT_SYMBOL(iio_scan_el_ts_show);
-
-ssize_t iio_scan_el_ts_store(struct device *dev,
- struct device_attribute *attr,
- const char *buf,
- size_t len)
-{
- int ret = 0;
- struct iio_ring_buffer *ring = dev_get_drvdata(dev);
- struct iio_dev *indio_dev = ring->indio_dev;
- bool state;
- state = !(buf[0] == '0');
- mutex_lock(&indio_dev->mlock);
- if (indio_dev->currentmode == INDIO_RING_TRIGGERED) {
- ret = -EBUSY;
- goto error_ret;
- }
- ring->scan_timestamp = state;
-error_ret:
- mutex_unlock(&indio_dev->mlock);
-
- return ret ? ret : len;
-}
-EXPORT_SYMBOL(iio_scan_el_ts_store);
-
+EXPORT_SYMBOL(iio_sw_ring_preenable);
diff --git a/drivers/staging/iio/industrialio-trigger.c b/drivers/staging/iio/industrialio-trigger.c
index 57dd923..6159023 100644
--- a/drivers/staging/iio/industrialio-trigger.c
+++ b/drivers/staging/iio/industrialio-trigger.c
@@ -39,6 +39,19 @@
static DEFINE_MUTEX(iio_trigger_list_lock);
/**
+ * iio_trigger_read_name() - retrieve useful identifying name
+ **/
+static ssize_t iio_trigger_read_name(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct iio_trigger *trig = dev_get_drvdata(dev);
+ return sprintf(buf, "%s\n", trig->name);
+}
+
+static DEVICE_ATTR(name, S_IRUGO, iio_trigger_read_name, NULL);
+
+/**
* iio_trigger_register_sysfs() - create a device for this trigger
* @trig_info: the trigger
*
@@ -46,20 +59,16 @@
**/
static int iio_trigger_register_sysfs(struct iio_trigger *trig_info)
{
- int ret = 0;
-
- if (trig_info->control_attrs)
- ret = sysfs_create_group(&trig_info->dev.kobj,
- trig_info->control_attrs);
-
- return ret;
+ return sysfs_add_file_to_group(&trig_info->dev.kobj,
+ &dev_attr_name.attr,
+ NULL);
}
static void iio_trigger_unregister_sysfs(struct iio_trigger *trig_info)
{
- if (trig_info->control_attrs)
- sysfs_remove_group(&trig_info->dev.kobj,
- trig_info->control_attrs);
+ sysfs_remove_file_from_group(&trig_info->dev.kobj,
+ &dev_attr_name.attr,
+ NULL);
}
@@ -134,14 +143,8 @@
void iio_trigger_unregister(struct iio_trigger *trig_info)
{
- struct iio_trigger *cursor;
-
mutex_lock(&iio_trigger_list_lock);
- list_for_each_entry(cursor, &iio_trigger_list, list)
- if (cursor == trig_info) {
- list_del(&cursor->list);
- break;
- }
+ list_del(&trig_info->list);
mutex_unlock(&iio_trigger_list_lock);
iio_trigger_unregister_sysfs(trig_info);
@@ -151,47 +154,55 @@
}
EXPORT_SYMBOL(iio_trigger_unregister);
-struct iio_trigger *iio_trigger_find_by_name(const char *name, size_t len)
+static struct iio_trigger *iio_trigger_find_by_name(const char *name,
+ size_t len)
{
- struct iio_trigger *trig;
- bool found = false;
-
- if (len && name[len - 1] == '\n')
- len--;
+ struct iio_trigger *trig = NULL, *iter;
mutex_lock(&iio_trigger_list_lock);
- list_for_each_entry(trig, &iio_trigger_list, list) {
- if (strncmp(trig->name, name, len) == 0) {
- found = true;
+ list_for_each_entry(iter, &iio_trigger_list, list)
+ if (sysfs_streq(iter->name, name)) {
+ trig = iter;
break;
}
- }
mutex_unlock(&iio_trigger_list_lock);
- return found ? trig : NULL;
+ return trig;
}
-EXPORT_SYMBOL(iio_trigger_find_by_name);
void iio_trigger_poll(struct iio_trigger *trig, s64 time)
{
- struct iio_poll_func *pf_cursor;
-
- list_for_each_entry(pf_cursor, &trig->pollfunc_list, list) {
- if (pf_cursor->poll_func_immediate) {
- pf_cursor->poll_func_immediate(pf_cursor->private_data);
- trig->use_count++;
- }
- }
- list_for_each_entry(pf_cursor, &trig->pollfunc_list, list) {
- if (pf_cursor->poll_func_main) {
- pf_cursor->poll_func_main(pf_cursor->private_data,
- time);
- trig->use_count++;
- }
+ int i;
+ if (!trig->use_count) {
+ for (i = 0; i < CONFIG_IIO_CONSUMERS_PER_TRIGGER; i++)
+ if (trig->subirqs[i].enabled) {
+ trig->use_count++;
+ generic_handle_irq(trig->subirq_base + i);
+ }
}
}
EXPORT_SYMBOL(iio_trigger_poll);
+irqreturn_t iio_trigger_generic_data_rdy_poll(int irq, void *private)
+{
+ iio_trigger_poll(private, iio_get_time_ns());
+ return IRQ_HANDLED;
+}
+EXPORT_SYMBOL(iio_trigger_generic_data_rdy_poll);
+
+void iio_trigger_poll_chained(struct iio_trigger *trig, s64 time)
+{
+ int i;
+ if (!trig->use_count) {
+ for (i = 0; i < CONFIG_IIO_CONSUMERS_PER_TRIGGER; i++)
+ if (trig->subirqs[i].enabled) {
+ trig->use_count++;
+ handle_nested_irq(trig->subirq_base + i);
+ }
+ }
+}
+EXPORT_SYMBOL(iio_trigger_poll_chained);
+
void iio_trigger_notify_done(struct iio_trigger *trig)
{
trig->use_count--;
@@ -203,18 +214,6 @@
}
EXPORT_SYMBOL(iio_trigger_notify_done);
-/**
- * iio_trigger_read_name() - retrieve useful identifying name
- **/
-ssize_t iio_trigger_read_name(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- struct iio_trigger *trig = dev_get_drvdata(dev);
- return sprintf(buf, "%s\n", trig->name);
-}
-EXPORT_SYMBOL(iio_trigger_read_name);
-
/* Trigger Consumer related functions */
/* Complexity in here. With certain triggers (datardy) an acknowledgement
@@ -228,18 +227,16 @@
struct iio_poll_func *pf)
{
int ret = 0;
- unsigned long flags;
+ bool notinuse
+ = bitmap_empty(trig->pool, CONFIG_IIO_CONSUMERS_PER_TRIGGER);
- spin_lock_irqsave(&trig->pollfunc_list_lock, flags);
- list_add_tail(&pf->list, &trig->pollfunc_list);
- spin_unlock_irqrestore(&trig->pollfunc_list_lock, flags);
-
- if (trig->set_trigger_state)
+ pf->irq = iio_trigger_get_irq(trig);
+ ret = request_threaded_irq(pf->irq, pf->h, pf->thread,
+ pf->type, pf->name,
+ pf);
+ if (trig->set_trigger_state && notinuse)
ret = trig->set_trigger_state(trig, true);
- if (ret) {
- printk(KERN_ERR "set trigger state failed\n");
- list_del(&pf->list);
- }
+
return ret;
}
EXPORT_SYMBOL(iio_trigger_attach_poll_func);
@@ -247,41 +244,68 @@
int iio_trigger_dettach_poll_func(struct iio_trigger *trig,
struct iio_poll_func *pf)
{
- struct iio_poll_func *pf_cursor;
- unsigned long flags;
- int ret = -EINVAL;
-
- spin_lock_irqsave(&trig->pollfunc_list_lock, flags);
- list_for_each_entry(pf_cursor, &trig->pollfunc_list, list)
- if (pf_cursor == pf) {
- ret = 0;
- break;
- }
- if (!ret) {
- if (list_is_singular(&trig->pollfunc_list)
- && trig->set_trigger_state) {
- spin_unlock_irqrestore(&trig->pollfunc_list_lock,
- flags);
- /* May sleep hence cannot hold the spin lock */
- ret = trig->set_trigger_state(trig, false);
- if (ret)
- goto error_ret;
- spin_lock_irqsave(&trig->pollfunc_list_lock, flags);
- }
- /*
- * Now we can delete safe in the knowledge that, if this is
- * the last pollfunc then we have disabled the trigger anyway
- * and so nothing should be able to call the pollfunc.
- */
- list_del(&pf_cursor->list);
+ int ret = 0;
+ bool no_other_users
+ = (bitmap_weight(trig->pool,
+ CONFIG_IIO_CONSUMERS_PER_TRIGGER)
+ == 1);
+ if (trig->set_trigger_state && no_other_users) {
+ ret = trig->set_trigger_state(trig, false);
+ if (ret)
+ goto error_ret;
}
- spin_unlock_irqrestore(&trig->pollfunc_list_lock, flags);
+ iio_trigger_put_irq(trig, pf->irq);
+ free_irq(pf->irq, pf);
error_ret:
return ret;
}
EXPORT_SYMBOL(iio_trigger_dettach_poll_func);
+irqreturn_t iio_pollfunc_store_time(int irq, void *p)
+{
+ struct iio_poll_func *pf = p;
+ pf->timestamp = iio_get_time_ns();
+ return IRQ_WAKE_THREAD;
+}
+EXPORT_SYMBOL(iio_pollfunc_store_time);
+
+struct iio_poll_func
+*iio_alloc_pollfunc(irqreturn_t (*h)(int irq, void *p),
+ irqreturn_t (*thread)(int irq, void *p),
+ int type,
+ void *private,
+ const char *fmt,
+ ...)
+{
+ va_list vargs;
+ struct iio_poll_func *pf;
+
+ pf = kmalloc(sizeof *pf, GFP_KERNEL);
+ if (pf == NULL)
+ return NULL;
+ va_start(vargs, fmt);
+ pf->name = kvasprintf(GFP_KERNEL, fmt, vargs);
+ va_end(vargs);
+ if (pf->name == NULL) {
+ kfree(pf);
+ return NULL;
+ }
+ pf->h = h;
+ pf->thread = thread;
+ pf->type = type;
+
+ return pf;
+}
+EXPORT_SYMBOL_GPL(iio_alloc_pollfunc);
+
+void iio_dealloc_pollfunc(struct iio_poll_func *pf)
+{
+ kfree(pf->name);
+ kfree(pf);
+}
+EXPORT_SYMBOL_GPL(iio_dealloc_pollfunc);
+
/**
* iio_trigger_read_currrent() - trigger consumer sysfs query which trigger
*
@@ -348,6 +372,23 @@
static void iio_trig_release(struct device *device)
{
struct iio_trigger *trig = to_iio_trigger(device);
+ int i;
+
+ if (trig->subirq_base) {
+ for (i = 0; i < CONFIG_IIO_CONSUMERS_PER_TRIGGER; i++) {
+ irq_modify_status(trig->subirq_base + i,
+ IRQ_NOAUTOEN,
+ IRQ_NOREQUEST | IRQ_NOPROBE);
+ irq_set_chip(trig->subirq_base + i,
+ NULL);
+ irq_set_handler(trig->subirq_base + i,
+ NULL);
+ }
+
+ irq_free_descs(trig->subirq_base,
+ CONFIG_IIO_CONSUMERS_PER_TRIGGER);
+ }
+ kfree(trig->name);
kfree(trig);
iio_put();
}
@@ -356,18 +397,66 @@
.release = iio_trig_release,
};
-struct iio_trigger *iio_allocate_trigger(void)
+static void iio_trig_subirqmask(struct irq_data *d)
{
+ struct irq_chip *chip = irq_data_get_irq_chip(d);
+ struct iio_trigger *trig
+ = container_of(chip,
+ struct iio_trigger, subirq_chip);
+ trig->subirqs[d->irq - trig->subirq_base].enabled = false;
+}
+
+static void iio_trig_subirqunmask(struct irq_data *d)
+{
+ struct irq_chip *chip = irq_data_get_irq_chip(d);
+ struct iio_trigger *trig
+ = container_of(chip,
+ struct iio_trigger, subirq_chip);
+ trig->subirqs[d->irq - trig->subirq_base].enabled = true;
+}
+
+struct iio_trigger *iio_allocate_trigger(const char *fmt, ...)
+{
+ va_list vargs;
struct iio_trigger *trig;
trig = kzalloc(sizeof *trig, GFP_KERNEL);
if (trig) {
+ int i;
trig->dev.type = &iio_trig_type;
trig->dev.bus = &iio_bus_type;
device_initialize(&trig->dev);
dev_set_drvdata(&trig->dev, (void *)trig);
- spin_lock_init(&trig->pollfunc_list_lock);
- INIT_LIST_HEAD(&trig->list);
- INIT_LIST_HEAD(&trig->pollfunc_list);
+
+ mutex_init(&trig->pool_lock);
+ trig->subirq_base
+ = irq_alloc_descs(-1, 0,
+ CONFIG_IIO_CONSUMERS_PER_TRIGGER,
+ 0);
+ if (trig->subirq_base < 0) {
+ kfree(trig);
+ return NULL;
+ }
+ va_start(vargs, fmt);
+ trig->name = kvasprintf(GFP_KERNEL, fmt, vargs);
+ va_end(vargs);
+ if (trig->name == NULL) {
+ irq_free_descs(trig->subirq_base,
+ CONFIG_IIO_CONSUMERS_PER_TRIGGER);
+ kfree(trig);
+ return NULL;
+ }
+ trig->subirq_chip.name = trig->name;
+ trig->subirq_chip.irq_mask = &iio_trig_subirqmask;
+ trig->subirq_chip.irq_unmask = &iio_trig_subirqunmask;
+ for (i = 0; i < CONFIG_IIO_CONSUMERS_PER_TRIGGER; i++) {
+ irq_set_chip(trig->subirq_base + i,
+ &trig->subirq_chip);
+ irq_set_handler(trig->subirq_base + i,
+ &handle_simple_irq);
+ irq_modify_status(trig->subirq_base + i,
+ IRQ_NOREQUEST | IRQ_NOAUTOEN,
+ IRQ_NOPROBE);
+ }
iio_get();
}
return trig;
@@ -398,20 +487,6 @@
}
EXPORT_SYMBOL(iio_device_unregister_trigger_consumer);
-int iio_alloc_pollfunc(struct iio_dev *indio_dev,
- void (*immediate)(struct iio_dev *indio_dev),
- void (*main)(struct iio_dev *private_data, s64 time))
-{
- indio_dev->pollfunc = kzalloc(sizeof(*indio_dev->pollfunc), GFP_KERNEL);
- if (indio_dev->pollfunc == NULL)
- return -ENOMEM;
- indio_dev->pollfunc->poll_func_immediate = immediate;
- indio_dev->pollfunc->poll_func_main = main;
- indio_dev->pollfunc->private_data = indio_dev;
- return 0;
-}
-EXPORT_SYMBOL(iio_alloc_pollfunc);
-
int iio_triggered_ring_postenable(struct iio_dev *indio_dev)
{
return indio_dev->trig
diff --git a/drivers/staging/iio/kfifo_buf.c b/drivers/staging/iio/kfifo_buf.c
index a56c0cb..cc14b96 100644
--- a/drivers/staging/iio/kfifo_buf.c
+++ b/drivers/staging/iio/kfifo_buf.c
@@ -8,6 +8,8 @@
#include "kfifo_buf.h"
+#define iio_to_kfifo(r) container_of(r, struct iio_kfifo, ring)
+
static inline int __iio_allocate_kfifo(struct iio_kfifo *buf,
int bytes_per_datum, int length)
{
@@ -18,7 +20,7 @@
return kfifo_alloc(&buf->kf, bytes_per_datum*length, GFP_KERNEL);
}
-int iio_request_update_kfifo(struct iio_ring_buffer *r)
+static int iio_request_update_kfifo(struct iio_ring_buffer *r)
{
int ret = 0;
struct iio_kfifo *buf = iio_to_kfifo(r);
@@ -37,31 +39,27 @@
mutex_unlock(&buf->use_lock);
return ret;
}
-EXPORT_SYMBOL(iio_request_update_kfifo);
-void iio_mark_kfifo_in_use(struct iio_ring_buffer *r)
+static void iio_mark_kfifo_in_use(struct iio_ring_buffer *r)
{
struct iio_kfifo *buf = iio_to_kfifo(r);
mutex_lock(&buf->use_lock);
buf->use_count++;
mutex_unlock(&buf->use_lock);
}
-EXPORT_SYMBOL(iio_mark_kfifo_in_use);
-void iio_unmark_kfifo_in_use(struct iio_ring_buffer *r)
+static void iio_unmark_kfifo_in_use(struct iio_ring_buffer *r)
{
struct iio_kfifo *buf = iio_to_kfifo(r);
mutex_lock(&buf->use_lock);
buf->use_count--;
mutex_unlock(&buf->use_lock);
}
-EXPORT_SYMBOL(iio_unmark_kfifo_in_use);
-int iio_get_length_kfifo(struct iio_ring_buffer *r)
+static int iio_get_length_kfifo(struct iio_ring_buffer *r)
{
return r->length;
}
-EXPORT_SYMBOL(iio_get_length_kfifo);
static inline void __iio_init_kfifo(struct iio_kfifo *kf)
{
@@ -108,6 +106,7 @@
kf = kzalloc(sizeof *kf, GFP_KERNEL);
if (!kf)
return NULL;
+ kf->update_needed = true;
iio_ring_buffer_init(&kf->ring, indio_dev);
__iio_init_kfifo(kf);
kf->ring.dev.type = &iio_kfifo_type;
@@ -120,41 +119,37 @@
}
EXPORT_SYMBOL(iio_kfifo_allocate);
-int iio_get_bytes_per_datum_kfifo(struct iio_ring_buffer *r)
+static int iio_get_bytes_per_datum_kfifo(struct iio_ring_buffer *r)
{
return r->bytes_per_datum;
}
-EXPORT_SYMBOL(iio_get_bytes_per_datum_kfifo);
-int iio_set_bytes_per_datum_kfifo(struct iio_ring_buffer *r, size_t bpd)
+static int iio_set_bytes_per_datum_kfifo(struct iio_ring_buffer *r, size_t bpd)
{
if (r->bytes_per_datum != bpd) {
r->bytes_per_datum = bpd;
- if (r->access.mark_param_change)
- r->access.mark_param_change(r);
+ if (r->access->mark_param_change)
+ r->access->mark_param_change(r);
}
return 0;
}
-EXPORT_SYMBOL(iio_set_bytes_per_datum_kfifo);
-int iio_mark_update_needed_kfifo(struct iio_ring_buffer *r)
+static int iio_mark_update_needed_kfifo(struct iio_ring_buffer *r)
{
struct iio_kfifo *kf = iio_to_kfifo(r);
kf->update_needed = true;
return 0;
}
-EXPORT_SYMBOL(iio_mark_update_needed_kfifo);
-int iio_set_length_kfifo(struct iio_ring_buffer *r, int length)
+static int iio_set_length_kfifo(struct iio_ring_buffer *r, int length)
{
if (r->length != length) {
r->length = length;
- if (r->access.mark_param_change)
- r->access.mark_param_change(r);
+ if (r->access->mark_param_change)
+ r->access->mark_param_change(r);
}
return 0;
}
-EXPORT_SYMBOL(iio_set_length_kfifo);
void iio_kfifo_free(struct iio_ring_buffer *r)
{
@@ -163,7 +158,9 @@
}
EXPORT_SYMBOL(iio_kfifo_free);
-int iio_store_to_kfifo(struct iio_ring_buffer *r, u8 *data, s64 timestamp)
+static int iio_store_to_kfifo(struct iio_ring_buffer *r,
+ u8 *data,
+ s64 timestamp)
{
int ret;
struct iio_kfifo *kf = iio_to_kfifo(r);
@@ -179,18 +176,30 @@
kfree(datal);
return 0;
}
-EXPORT_SYMBOL(iio_store_to_kfifo);
-int iio_rip_kfifo(struct iio_ring_buffer *r,
- size_t count, char __user *buf, int *deadoffset)
+static int iio_read_first_n_kfifo(struct iio_ring_buffer *r,
+ size_t n, char __user *buf)
{
int ret, copied;
struct iio_kfifo *kf = iio_to_kfifo(r);
- *deadoffset = 0;
- ret = kfifo_to_user(&kf->kf, buf, r->bytes_per_datum*count, &copied);
+ ret = kfifo_to_user(&kf->kf, buf, r->bytes_per_datum*n, &copied);
return copied;
}
-EXPORT_SYMBOL(iio_rip_kfifo);
+
+const struct iio_ring_access_funcs kfifo_access_funcs = {
+ .mark_in_use = &iio_mark_kfifo_in_use,
+ .unmark_in_use = &iio_unmark_kfifo_in_use,
+ .store_to = &iio_store_to_kfifo,
+ .read_first_n = &iio_read_first_n_kfifo,
+ .mark_param_change = &iio_mark_update_needed_kfifo,
+ .request_update = &iio_request_update_kfifo,
+ .get_bytes_per_datum = &iio_get_bytes_per_datum_kfifo,
+ .set_bytes_per_datum = &iio_set_bytes_per_datum_kfifo,
+ .get_length = &iio_get_length_kfifo,
+ .set_length = &iio_set_length_kfifo,
+};
+EXPORT_SYMBOL(kfifo_access_funcs);
+
MODULE_LICENSE("GPL");
diff --git a/drivers/staging/iio/kfifo_buf.h b/drivers/staging/iio/kfifo_buf.h
index 8064383..aac3053 100644
--- a/drivers/staging/iio/kfifo_buf.h
+++ b/drivers/staging/iio/kfifo_buf.h
@@ -11,45 +11,7 @@
struct mutex use_lock;
};
-#define iio_to_kfifo(r) container_of(r, struct iio_kfifo, ring)
-
-int iio_create_kfifo(struct iio_ring_buffer **r);
-int iio_init_kfifo(struct iio_ring_buffer *r, struct iio_dev *indio_dev);
-void iio_exit_kfifo(struct iio_ring_buffer *r);
-void iio_free_kfifo(struct iio_ring_buffer *r);
-void iio_mark_kfifo_in_use(struct iio_ring_buffer *r);
-void iio_unmark_kfifo_in_use(struct iio_ring_buffer *r);
-
-int iio_store_to_kfifo(struct iio_ring_buffer *r, u8 *data, s64 timestamp);
-int iio_rip_kfifo(struct iio_ring_buffer *r,
- size_t count,
- char __user *buf,
- int *dead_offset);
-
-int iio_request_update_kfifo(struct iio_ring_buffer *r);
-int iio_mark_update_needed_kfifo(struct iio_ring_buffer *r);
-
-int iio_get_bytes_per_datum_kfifo(struct iio_ring_buffer *r);
-int iio_set_bytes_per_datum_kfifo(struct iio_ring_buffer *r, size_t bpd);
-int iio_get_length_kfifo(struct iio_ring_buffer *r);
-int iio_set_length_kfifo(struct iio_ring_buffer *r, int length);
-
-static inline void iio_kfifo_register_funcs(struct iio_ring_access_funcs *ra)
-{
- ra->mark_in_use = &iio_mark_kfifo_in_use;
- ra->unmark_in_use = &iio_unmark_kfifo_in_use;
-
- ra->store_to = &iio_store_to_kfifo;
- ra->rip_lots = &iio_rip_kfifo;
-
- ra->mark_param_change = &iio_mark_update_needed_kfifo;
- ra->request_update = &iio_request_update_kfifo;
-
- ra->get_bytes_per_datum = &iio_get_bytes_per_datum_kfifo;
- ra->set_bytes_per_datum = &iio_set_bytes_per_datum_kfifo;
- ra->get_length = &iio_get_length_kfifo;
- ra->set_length = &iio_set_length_kfifo;
-};
+extern const struct iio_ring_access_funcs kfifo_access_funcs;
struct iio_ring_buffer *iio_kfifo_allocate(struct iio_dev *indio_dev);
void iio_kfifo_free(struct iio_ring_buffer *r);
diff --git a/drivers/staging/iio/light/Kconfig b/drivers/staging/iio/light/Kconfig
index 36d8bbe..46d62d1 100644
--- a/drivers/staging/iio/light/Kconfig
+++ b/drivers/staging/iio/light/Kconfig
@@ -1,18 +1,8 @@
-#
+\#
# Light sensors
#
comment "Light sensors"
-config SENSORS_TSL2563
- tristate "TAOS TSL256[0-3] ambient light sensor"
- depends on I2C
- help
- If you say yes here you get support for the Taos TSL2560,
- TSL2561, TSL2562 and TSL2563 ambient light sensors.
-
- This driver can also be built as a module. If so, the module
- will be called tsl2563.
-
config SENSORS_ISL29018
tristate "ISL 29018 light and proximity sensor"
depends on I2C
@@ -24,3 +14,19 @@
in lux, proximity infrared sensing and normal infrared sensing.
Data from sensor is accessible via sysfs.
+config SENSORS_TSL2563
+ tristate "TAOS TSL2560, TSL2561, TSL2562 and TSL2563 ambient light sensors"
+ depends on I2C
+ help
+ If you say yes here you get support for the Taos TSL2560,
+ TSL2561, TSL2562 and TSL2563 ambient light sensors.
+
+ This driver can also be built as a module. If so, the module
+ will be called tsl2563.
+
+config TSL2583
+ tristate "TAOS TSL2580, TSL2581 and TSL2583 light-to-digital converters"
+ depends on I2C
+ help
+ Provides support for the TAOS tsl2580, tsl2581 and tsl2583 devices.
+ Access ALS data via iio, sysfs.
diff --git a/drivers/staging/iio/light/Makefile b/drivers/staging/iio/light/Makefile
index 9142c0e..3011fbf 100644
--- a/drivers/staging/iio/light/Makefile
+++ b/drivers/staging/iio/light/Makefile
@@ -4,3 +4,4 @@
obj-$(CONFIG_SENSORS_TSL2563) += tsl2563.o
obj-$(CONFIG_SENSORS_ISL29018) += isl29018.o
+obj-$(CONFIG_TSL2583) += tsl2583.o
diff --git a/drivers/staging/iio/light/isl29018.c b/drivers/staging/iio/light/isl29018.c
index f919cc1..4794ffd 100644
--- a/drivers/staging/iio/light/isl29018.c
+++ b/drivers/staging/iio/light/isl29018.c
@@ -402,16 +402,6 @@
return get_sensor_data(dev, buf, COMMMAND1_OPMODE_PROX_ONCE);
}
-/* Read name */
-static ssize_t show_name(struct device *dev,
- struct device_attribute *attr, char *buf)
-{
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
- struct isl29018_chip *chip = indio_dev->dev_data;
-
- return sprintf(buf, "%s\n", chip->client->name);
-}
-
static IIO_DEVICE_ATTR(range, S_IRUGO | S_IWUSR, show_range, store_range, 0);
static IIO_CONST_ATTR(range_available, "1000 4000 16000 64000");
static IIO_CONST_ATTR(adc_resolution_available, "4 8 12 16");
@@ -424,12 +414,10 @@
static IIO_DEVICE_ATTR(illuminance0_input, S_IRUGO, show_lux, NULL, 0);
static IIO_DEVICE_ATTR(intensity_infrared_raw, S_IRUGO, show_ir, NULL, 0);
static IIO_DEVICE_ATTR(proximity_raw, S_IRUGO, show_proxim_ir, NULL, 0);
-static IIO_DEVICE_ATTR(name, S_IRUGO, show_name, NULL, 0);
#define ISL29018_DEV_ATTR(name) (&iio_dev_attr_##name.dev_attr.attr)
#define ISL29018_CONST_ATTR(name) (&iio_const_attr_##name.dev_attr.attr)
static struct attribute *isl29018_attributes[] = {
- ISL29018_DEV_ATTR(name),
ISL29018_DEV_ATTR(range),
ISL29018_CONST_ATTR(range_available),
ISL29018_DEV_ATTR(adc_resolution),
@@ -467,6 +455,11 @@
return 0;
}
+static const struct iio_info isl29108_info = {
+ .attrs = &isl29108_group,
+ .driver_module = THIS_MODULE,
+};
+
static int __devinit isl29018_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
@@ -492,15 +485,15 @@
if (err)
goto exit_free;
- chip->indio_dev = iio_allocate_device();
+ chip->indio_dev = iio_allocate_device(0);
if (!chip->indio_dev) {
dev_err(&client->dev, "iio allocation fails\n");
goto exit_free;
}
- chip->indio_dev->attrs = &isl29108_group;
+ chip->indio_dev->info = &isl29108_info;
+ chip->indio_dev->name = id->name;
chip->indio_dev->dev.parent = &client->dev;
chip->indio_dev->dev_data = (void *)(chip);
- chip->indio_dev->driver_module = THIS_MODULE;
chip->indio_dev->modes = INDIO_DIRECT_MODE;
err = iio_device_register(chip->indio_dev);
if (err) {
diff --git a/drivers/staging/iio/light/tsl2563.c b/drivers/staging/iio/light/tsl2563.c
index dadae75..9cffa2e 100644
--- a/drivers/staging/iio/light/tsl2563.c
+++ b/drivers/staging/iio/light/tsl2563.c
@@ -92,7 +92,7 @@
u16 max;
};
-static struct tsl2563_gainlevel_coeff tsl2563_gainlevel_table[] = {
+static const struct tsl2563_gainlevel_coeff tsl2563_gainlevel_table[] = {
{
.gaintime = TSL2563_TIMING_400MS | TSL2563_TIMING_GAIN16,
.min = 0,
@@ -115,15 +115,12 @@
struct tsl2563_chip {
struct mutex lock;
struct i2c_client *client;
- struct iio_dev *indio_dev;
struct delayed_work poweroff_work;
- struct work_struct work_thresh;
- s64 event_timestamp;
/* Remember state for suspend and resume functions */
pm_message_t state;
- struct tsl2563_gainlevel_coeff *gainlevel;
+ struct tsl2563_gainlevel_coeff const *gainlevel;
u16 low_thres;
u16 high_thres;
@@ -467,32 +464,6 @@
/* Sysfs interface */
/*--------------------------------------------------------------*/
-static ssize_t tsl2563_adc_show(struct device *dev,
- struct device_attribute *attr, char *buf)
-{
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
- struct tsl2563_chip *chip = indio_dev->dev_data;
- struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
- int ret;
-
- mutex_lock(&chip->lock);
-
- ret = tsl2563_get_adc(chip);
- if (ret)
- goto out;
-
- switch (this_attr->address) {
- case 0:
- ret = snprintf(buf, PAGE_SIZE, "%d\n", chip->data0);
- break;
- case 1:
- ret = snprintf(buf, PAGE_SIZE, "%d\n", chip->data1);
- break;
- }
-out:
- mutex_unlock(&chip->lock);
- return ret;
-}
/* Apply calibration coefficient to ADC count. */
static u32 calib_adc(u32 adc, u32 calib)
@@ -505,237 +476,165 @@
return (u32) scaled;
}
-static ssize_t tsl2563_lux_show(struct device *dev,
- struct device_attribute *attr, char *buf)
+static int tsl2563_write_raw(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ int val,
+ int val2,
+ long mask)
{
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
- struct tsl2563_chip *chip = indio_dev->dev_data;
- u32 calib0, calib1;
- int ret;
+ struct tsl2563_chip *chip = iio_priv(indio_dev);
- mutex_lock(&chip->lock);
-
- ret = tsl2563_get_adc(chip);
- if (ret)
- goto out;
-
- calib0 = calib_adc(chip->data0, chip->calib0) * chip->cover_comp_gain;
- calib1 = calib_adc(chip->data1, chip->calib1) * chip->cover_comp_gain;
-
- ret = snprintf(buf, PAGE_SIZE, "%d\n", adc_to_lux(calib0, calib1));
-
-out:
- mutex_unlock(&chip->lock);
- return ret;
-}
-
-static ssize_t format_calib(char *buf, int len, u32 calib)
-{
- return snprintf(buf, PAGE_SIZE, "%d\n", calib_to_sysfs(calib));
-}
-
-static ssize_t tsl2563_calib_show(struct device *dev,
- struct device_attribute *attr, char *buf)
-{
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
- struct tsl2563_chip *chip = indio_dev->dev_data;
- struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
- int ret;
-
- mutex_lock(&chip->lock);
- switch (this_attr->address) {
- case 0:
- ret = format_calib(buf, PAGE_SIZE, chip->calib0);
- break;
- case 1:
- ret = format_calib(buf, PAGE_SIZE, chip->calib1);
- break;
- default:
- ret = -ENODEV;
- }
- mutex_unlock(&chip->lock);
- return ret;
-}
-
-static ssize_t tsl2563_calib_store(struct device *dev,
- struct device_attribute *attr,
- const char *buf, size_t len)
-{
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
- struct tsl2563_chip *chip = indio_dev->dev_data;
- struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
- int value;
- u32 calib;
-
- if (1 != sscanf(buf, "%d", &value))
- return -EINVAL;
-
- calib = calib_from_sysfs(value);
-
- switch (this_attr->address) {
- case 0:
- chip->calib0 = calib;
- break;
- case 1:
- chip->calib1 = calib;
- break;
- }
-
- return len;
-}
-
-static IIO_DEVICE_ATTR(intensity0_both_raw, S_IRUGO,
- tsl2563_adc_show, NULL, 0);
-static IIO_DEVICE_ATTR(intensity1_ir_raw, S_IRUGO,
- tsl2563_adc_show, NULL, 1);
-static DEVICE_ATTR(illuminance0_input, S_IRUGO, tsl2563_lux_show, NULL);
-static IIO_DEVICE_ATTR(intensity0_both_calibgain, S_IRUGO | S_IWUSR,
- tsl2563_calib_show, tsl2563_calib_store, 0);
-static IIO_DEVICE_ATTR(intensity1_ir_calibgain, S_IRUGO | S_IWUSR,
- tsl2563_calib_show, tsl2563_calib_store, 1);
-
-static ssize_t tsl2563_show_name(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
- struct tsl2563_chip *chip = indio_dev->dev_data;
- return sprintf(buf, "%s\n", chip->client->name);
-}
-
-static DEVICE_ATTR(name, S_IRUGO, tsl2563_show_name, NULL);
-
-static struct attribute *tsl2563_attributes[] = {
- &iio_dev_attr_intensity0_both_raw.dev_attr.attr,
- &iio_dev_attr_intensity1_ir_raw.dev_attr.attr,
- &dev_attr_illuminance0_input.attr,
- &iio_dev_attr_intensity0_both_calibgain.dev_attr.attr,
- &iio_dev_attr_intensity1_ir_calibgain.dev_attr.attr,
- &dev_attr_name.attr,
- NULL
-};
-
-static const struct attribute_group tsl2563_group = {
- .attrs = tsl2563_attributes,
-};
-
-static ssize_t tsl2563_read_thresh(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
- struct tsl2563_chip *chip = indio_dev->dev_data;
- struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
- u16 val = 0;
- switch (this_attr->address) {
- case TSL2563_REG_HIGHLOW:
- val = chip->high_thres;
- break;
- case TSL2563_REG_LOWLOW:
- val = chip->low_thres;
- break;
- }
- return snprintf(buf, PAGE_SIZE, "%d\n", val);
-}
-
-static ssize_t tsl2563_write_thresh(struct device *dev,
- struct device_attribute *attr,
- const char *buf,
- size_t len)
-{
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
- struct tsl2563_chip *chip = indio_dev->dev_data;
- struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
- unsigned long val;
- int ret;
-
- ret = strict_strtoul(buf, 10, &val);
- if (ret)
- return ret;
- mutex_lock(&chip->lock);
- ret = tsl2563_write(chip->client, this_attr->address, val & 0xFF);
- if (ret)
- goto error_ret;
- ret = tsl2563_write(chip->client, this_attr->address + 1,
- (val >> 8) & 0xFF);
- switch (this_attr->address) {
- case TSL2563_REG_HIGHLOW:
- chip->high_thres = val;
- break;
- case TSL2563_REG_LOWLOW:
- chip->low_thres = val;
- break;
- }
-
-error_ret:
- mutex_unlock(&chip->lock);
-
- return ret < 0 ? ret : len;
-}
-
-static IIO_DEVICE_ATTR(intensity0_both_raw_thresh_rising_value,
- S_IRUGO | S_IWUSR,
- tsl2563_read_thresh,
- tsl2563_write_thresh,
- TSL2563_REG_HIGHLOW);
-
-static IIO_DEVICE_ATTR(intensity0_both_raw_thresh_falling_value,
- S_IRUGO | S_IWUSR,
- tsl2563_read_thresh,
- tsl2563_write_thresh,
- TSL2563_REG_LOWLOW);
-
-static int tsl2563_int_th(struct iio_dev *dev_info,
- int index,
- s64 timestamp,
- int not_test)
-{
- struct tsl2563_chip *chip = dev_info->dev_data;
-
- chip->event_timestamp = timestamp;
- schedule_work(&chip->work_thresh);
+ if (chan->channel == 0)
+ chip->calib0 = calib_from_sysfs(val);
+ else
+ chip->calib1 = calib_from_sysfs(val);
return 0;
}
-static void tsl2563_int_bh(struct work_struct *work_s)
+static int tsl2563_read_raw(struct iio_dev *indio_dev,
+ struct iio_chan_spec const *chan,
+ int *val,
+ int *val2,
+ long m)
{
- struct tsl2563_chip *chip
- = container_of(work_s,
- struct tsl2563_chip, work_thresh);
+ int ret = -EINVAL;
+ u32 calib0, calib1;
+ struct tsl2563_chip *chip = iio_priv(indio_dev);
+
+ mutex_lock(&chip->lock);
+ switch (m) {
+ case 0:
+ switch (chan->type) {
+ case IIO_LIGHT:
+ ret = tsl2563_get_adc(chip);
+ if (ret)
+ goto error_ret;
+ calib0 = calib_adc(chip->data0, chip->calib0) *
+ chip->cover_comp_gain;
+ calib1 = calib_adc(chip->data1, chip->calib1) *
+ chip->cover_comp_gain;
+ *val = adc_to_lux(calib0, calib1);
+ ret = IIO_VAL_INT;
+ break;
+ case IIO_INTENSITY:
+ ret = tsl2563_get_adc(chip);
+ if (ret)
+ goto error_ret;
+ if (chan->channel == 0)
+ *val = chip->data0;
+ else
+ *val = chip->data1;
+ ret = IIO_VAL_INT;
+ break;
+ default:
+ break;
+ }
+ break;
+
+ case (1 << IIO_CHAN_INFO_CALIBSCALE_SEPARATE):
+ if (chan->channel == 0)
+ *val = calib_to_sysfs(chip->calib0);
+ else
+ *val = calib_to_sysfs(chip->calib1);
+ ret = IIO_VAL_INT;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+error_ret:
+ mutex_unlock(&chip->lock);
+ return ret;
+}
+
+static const struct iio_chan_spec tsl2563_channels[] = {
+ IIO_CHAN(IIO_LIGHT, 0, 1, 1, NULL, 0, 0, 0, 0, 0, {}, 0),
+ IIO_CHAN(IIO_INTENSITY, 1, 1, 0, "both", 0,
+ (1 << IIO_CHAN_INFO_CALIBSCALE_SEPARATE), 0, 0, 0, {},
+ IIO_EV_BIT(IIO_EV_TYPE_THRESH, IIO_EV_DIR_RISING) |
+ IIO_EV_BIT(IIO_EV_TYPE_THRESH, IIO_EV_DIR_FALLING)),
+ IIO_CHAN(IIO_INTENSITY, 1, 1, 0, "ir", 1,
+ (1 << IIO_CHAN_INFO_CALIBSCALE_SEPARATE), 0, 0, 0, {},
+ 0)
+};
+
+static int tsl2563_read_thresh(struct iio_dev *indio_dev,
+ int event_code,
+ int *val)
+{
+ struct tsl2563_chip *chip = iio_priv(indio_dev);
+
+ switch (IIO_EVENT_CODE_EXTRACT_DIR(event_code)) {
+ case IIO_EV_DIR_RISING:
+ *val = chip->high_thres;
+ break;
+ case IIO_EV_DIR_FALLING:
+ *val = chip->low_thres;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static ssize_t tsl2563_write_thresh(struct iio_dev *indio_dev,
+ int event_code,
+ int val)
+{
+ struct tsl2563_chip *chip = iio_priv(indio_dev);
+ int ret;
+ u8 address;
+
+ if (IIO_EVENT_CODE_EXTRACT_DIR(event_code) == IIO_EV_DIR_RISING)
+ address = TSL2563_REG_HIGHLOW;
+ else
+ address = TSL2563_REG_LOWLOW;
+ mutex_lock(&chip->lock);
+ ret = tsl2563_write(chip->client, address, val & 0xFF);
+ if (ret)
+ goto error_ret;
+ ret = tsl2563_write(chip->client, address + 1,
+ (val >> 8) & 0xFF);
+ if (IIO_EVENT_CODE_EXTRACT_DIR(event_code) == IIO_EV_DIR_RISING)
+ chip->high_thres = val;
+ else
+ chip->low_thres = val;
+
+error_ret:
+ mutex_unlock(&chip->lock);
+
+ return ret;
+}
+
+static irqreturn_t tsl2563_event_handler(int irq, void *private)
+{
+ struct iio_dev *dev_info = private;
+ struct tsl2563_chip *chip = iio_priv(dev_info);
u8 cmd = TSL2563_CMD | TSL2563_CLEARINT;
- iio_push_event(chip->indio_dev, 0,
+ iio_push_event(dev_info, 0,
IIO_UNMOD_EVENT_CODE(IIO_EV_CLASS_LIGHT,
0,
IIO_EV_TYPE_THRESH,
IIO_EV_DIR_EITHER),
- chip->event_timestamp);
+ iio_get_time_ns());
- /* reenable_irq */
- enable_irq(chip->client->irq);
/* clear the interrupt and push the event */
i2c_master_send(chip->client, &cmd, sizeof(cmd));
-
+ return IRQ_HANDLED;
}
-static ssize_t tsl2563_write_interrupt_config(struct device *dev,
- struct device_attribute *attr,
- const char *buf,
- size_t len)
+static int tsl2563_write_interrupt_config(struct iio_dev *indio_dev,
+ int event_code,
+ int state)
{
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
- struct tsl2563_chip *chip = indio_dev->dev_data;
- struct iio_event_attr *this_attr = to_iio_event_attr(attr);
- int input, ret = 0;
+ struct tsl2563_chip *chip = iio_priv(indio_dev);
+ int ret = 0;
- ret = sscanf(buf, "%d", &input);
- if (ret != 1)
- return -EINVAL;
mutex_lock(&chip->lock);
- if (input && !(chip->intr & 0x30)) {
- iio_add_event_to_list(this_attr->listel,
- &indio_dev->interrupts[0]->ev_list);
+ if (state && !(chip->intr & 0x30)) {
chip->intr &= ~0x30;
chip->intr |= 0x10;
/* ensure the chip is actually on */
@@ -752,11 +651,9 @@
chip->int_enabled = true;
}
- if (!input && (chip->intr & 0x30)) {
+ if (!state && (chip->intr & 0x30)) {
chip->intr |= ~0x30;
ret = tsl2563_write(chip->client, TSL2563_REG_INT, chip->intr);
- iio_remove_event_from_list(this_attr->listel,
- &indio_dev->interrupts[0]->ev_list);
chip->int_enabled = false;
/* now the interrupt is not enabled, we can go to sleep */
schedule_delayed_work(&chip->poweroff_work, 5 * HZ);
@@ -764,69 +661,64 @@
out:
mutex_unlock(&chip->lock);
- return (ret < 0) ? ret : len;
+ return ret;
}
-static ssize_t tsl2563_read_interrupt_config(struct device *dev,
- struct device_attribute *attr,
- char *buf)
+static int tsl2563_read_interrupt_config(struct iio_dev *indio_dev,
+ int event_code)
{
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
- struct tsl2563_chip *chip = indio_dev->dev_data;
- int ret;
+ struct tsl2563_chip *chip = iio_priv(indio_dev);
u8 rxbuf;
- ssize_t len;
+ int ret;
mutex_lock(&chip->lock);
- ret = tsl2563_read(chip->client,
- TSL2563_REG_INT,
- &rxbuf,
- sizeof(rxbuf));
+ ret = tsl2563_read(chip->client, TSL2563_REG_INT,
+ &rxbuf, sizeof(rxbuf));
mutex_unlock(&chip->lock);
if (ret < 0)
goto error_ret;
- len = snprintf(buf, PAGE_SIZE, "%d\n", !!(rxbuf & 0x30));
+ ret = !!(rxbuf & 0x30);
error_ret:
- return (ret < 0) ? ret : len;
+ return ret;
}
-IIO_EVENT_ATTR(intensity0_both_thresh_en,
- tsl2563_read_interrupt_config,
- tsl2563_write_interrupt_config,
- 0,
- tsl2563_int_th);
-
-static struct attribute *tsl2563_event_attributes[] = {
- &iio_event_attr_intensity0_both_thresh_en.dev_attr.attr,
- &iio_dev_attr_intensity0_both_raw_thresh_rising_value.dev_attr.attr,
- &iio_dev_attr_intensity0_both_raw_thresh_falling_value.dev_attr.attr,
- NULL,
-};
-
-static struct attribute_group tsl2563_event_attribute_group = {
- .attrs = tsl2563_event_attributes,
-};
-
/*--------------------------------------------------------------*/
/* Probe, Attach, Remove */
/*--------------------------------------------------------------*/
static struct i2c_driver tsl2563_i2c_driver;
+static const struct iio_info tsl2563_info_no_irq = {
+ .driver_module = THIS_MODULE,
+};
+
+static const struct iio_info tsl2563_info = {
+ .driver_module = THIS_MODULE,
+ .num_interrupt_lines = 1,
+ .read_raw = &tsl2563_read_raw,
+ .write_raw = &tsl2563_write_raw,
+ .read_event_value = &tsl2563_read_thresh,
+ .write_event_value = &tsl2563_write_thresh,
+ .read_event_config = &tsl2563_read_interrupt_config,
+ .write_event_config = &tsl2563_write_interrupt_config,
+};
+
static int __devinit tsl2563_probe(struct i2c_client *client,
const struct i2c_device_id *device_id)
{
+ struct iio_dev *indio_dev;
struct tsl2563_chip *chip;
struct tsl2563_platform_data *pdata = client->dev.platform_data;
int err = 0;
int ret;
u8 id;
- chip = kzalloc(sizeof(*chip), GFP_KERNEL);
- if (!chip)
+ indio_dev = iio_allocate_device(sizeof(*chip));
+ if (!indio_dev)
return -ENOMEM;
- INIT_WORK(&chip->work_thresh, tsl2563_int_bh);
+ chip = iio_priv(indio_dev);
+
i2c_set_clientdata(client, chip);
chip->client = client;
@@ -856,30 +748,25 @@
chip->cover_comp_gain = 1;
dev_info(&client->dev, "model %d, rev. %d\n", id >> 4, id & 0x0f);
-
- chip->indio_dev = iio_allocate_device();
- if (!chip->indio_dev)
- goto fail1;
- chip->indio_dev->attrs = &tsl2563_group;
- chip->indio_dev->dev.parent = &client->dev;
- chip->indio_dev->dev_data = (void *)(chip);
- chip->indio_dev->driver_module = THIS_MODULE;
- chip->indio_dev->modes = INDIO_DIRECT_MODE;
- if (client->irq) {
- chip->indio_dev->num_interrupt_lines = 1;
- chip->indio_dev->event_attrs
- = &tsl2563_event_attribute_group;
- }
- ret = iio_device_register(chip->indio_dev);
+ indio_dev->name = client->name;
+ indio_dev->channels = tsl2563_channels;
+ indio_dev->num_channels = ARRAY_SIZE(tsl2563_channels);
+ indio_dev->dev.parent = &client->dev;
+ indio_dev->modes = INDIO_DIRECT_MODE;
+ if (client->irq)
+ indio_dev->info = &tsl2563_info;
+ else
+ indio_dev->info = &tsl2563_info_no_irq;
+ ret = iio_device_register(indio_dev);
if (ret)
goto fail1;
-
if (client->irq) {
- ret = iio_register_interrupt_line(client->irq,
- chip->indio_dev,
- 0,
- IRQF_TRIGGER_RISING,
- client->name);
+ ret = request_threaded_irq(client->irq,
+ NULL,
+ &tsl2563_event_handler,
+ IRQF_TRIGGER_RISING | IRQF_ONESHOT,
+ "tsl2563_event",
+ indio_dev);
if (ret)
goto fail2;
}
@@ -894,9 +781,9 @@
return 0;
fail3:
if (client->irq)
- iio_unregister_interrupt_line(chip->indio_dev, 0);
+ free_irq(client->irq, indio_dev);
fail2:
- iio_device_unregister(chip->indio_dev);
+ iio_device_unregister(indio_dev);
fail1:
kfree(chip);
return err;
@@ -905,6 +792,7 @@
static int tsl2563_remove(struct i2c_client *client)
{
struct tsl2563_chip *chip = i2c_get_clientdata(client);
+ struct iio_dev *indio_dev = iio_priv_to_dev(chip);
if (!chip->int_enabled)
cancel_delayed_work(&chip->poweroff_work);
/* Ensure that interrupts are disabled - then flush any bottom halves */
@@ -913,10 +801,9 @@
flush_scheduled_work();
tsl2563_set_power(chip, 0);
if (client->irq)
- iio_unregister_interrupt_line(chip->indio_dev, 0);
- iio_device_unregister(chip->indio_dev);
+ free_irq(client->irq, indio_dev);
+ iio_device_unregister(indio_dev);
- kfree(chip);
return 0;
}
diff --git a/drivers/staging/iio/light/tsl2583.c b/drivers/staging/iio/light/tsl2583.c
new file mode 100644
index 0000000..5694610
--- /dev/null
+++ b/drivers/staging/iio/light/tsl2583.c
@@ -0,0 +1,964 @@
+/*
+ * Device driver for monitoring ambient light intensity (lux)
+ * within the TAOS tsl258x family of devices (tsl2580, tsl2581).
+ *
+ * Copyright (c) 2011, TAOS Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/i2c.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/string.h>
+#include <linux/mutex.h>
+#include <linux/unistd.h>
+#include <linux/slab.h>
+#include "../iio.h"
+
+#define TSL258X_MAX_DEVICE_REGS 32
+
+/* Triton register offsets */
+#define TSL258X_REG_MAX 8
+
+/* Device Registers and Masks */
+#define TSL258X_CNTRL 0x00
+#define TSL258X_ALS_TIME 0X01
+#define TSL258X_INTERRUPT 0x02
+#define TSL258X_GAIN 0x07
+#define TSL258X_REVID 0x11
+#define TSL258X_CHIPID 0x12
+#define TSL258X_ALS_CHAN0LO 0x14
+#define TSL258X_ALS_CHAN0HI 0x15
+#define TSL258X_ALS_CHAN1LO 0x16
+#define TSL258X_ALS_CHAN1HI 0x17
+#define TSL258X_TMR_LO 0x18
+#define TSL258X_TMR_HI 0x19
+
+/* tsl2583 cmd reg masks */
+#define TSL258X_CMD_REG 0x80
+#define TSL258X_CMD_SPL_FN 0x60
+#define TSL258X_CMD_ALS_INT_CLR 0X01
+
+/* tsl2583 cntrl reg masks */
+#define TSL258X_CNTL_ADC_ENBL 0x02
+#define TSL258X_CNTL_PWR_ON 0x01
+
+/* tsl2583 status reg masks */
+#define TSL258X_STA_ADC_VALID 0x01
+#define TSL258X_STA_ADC_INTR 0x10
+
+/* Lux calculation constants */
+#define TSL258X_LUX_CALC_OVER_FLOW 65535
+
+enum {
+ TSL258X_CHIP_UNKNOWN = 0,
+ TSL258X_CHIP_WORKING = 1,
+ TSL258X_CHIP_SUSPENDED = 2
+} TSL258X_CHIP_WORKING_STATUS;
+
+/* Per-device data */
+struct taos_als_info {
+ u16 als_ch0;
+ u16 als_ch1;
+ u16 lux;
+};
+
+struct taos_settings {
+ int als_time;
+ int als_gain;
+ int als_gain_trim;
+ int als_cal_target;
+};
+
+struct tsl2583_chip {
+ struct mutex als_mutex;
+ struct i2c_client *client;
+ struct iio_dev *iio_dev;
+ struct taos_als_info als_cur_info;
+ struct taos_settings taos_settings;
+ int als_time_scale;
+ int als_saturation;
+ int taos_chip_status;
+ u8 taos_config[8];
+};
+
+/*
+ * Initial values for device - this values can/will be changed by driver.
+ * and applications as needed.
+ * These values are dynamic.
+ */
+static const u8 taos_config[8] = {
+ 0x00, 0xee, 0x00, 0x03, 0x00, 0xFF, 0xFF, 0x00
+}; /* cntrl atime intC Athl0 Athl1 Athh0 Athh1 gain */
+
+struct taos_lux {
+ unsigned int ratio;
+ unsigned int ch0;
+ unsigned int ch1;
+};
+
+/* This structure is intentionally large to accommodate updates via sysfs. */
+/* Sized to 11 = max 10 segments + 1 termination segment */
+/* Assumption is is one and only one type of glass used */
+struct taos_lux taos_device_lux[11] = {
+ { 9830, 8520, 15729 },
+ { 12452, 10807, 23344 },
+ { 14746, 6383, 11705 },
+ { 17695, 4063, 6554 },
+};
+
+struct gainadj {
+ s16 ch0;
+ s16 ch1;
+};
+
+/* Index = (0 - 3) Used to validate the gain selection index */
+static const struct gainadj gainadj[] = {
+ { 1, 1 },
+ { 8, 8 },
+ { 16, 16 },
+ { 107, 115 }
+};
+
+/*
+ * Provides initial operational parameter defaults.
+ * These defaults may be changed through the device's sysfs files.
+ */
+static void taos_defaults(struct tsl2583_chip *chip)
+{
+ /* Operational parameters */
+ chip->taos_settings.als_time = 100;
+ /* must be a multiple of 50mS */
+ chip->taos_settings.als_gain = 0;
+ /* this is actually an index into the gain table */
+ /* assume clear glass as default */
+ chip->taos_settings.als_gain_trim = 1000;
+ /* default gain trim to account for aperture effects */
+ chip->taos_settings.als_cal_target = 130;
+ /* Known external ALS reading used for calibration */
+}
+
+/*
+ * Read a number of bytes starting at register (reg) location.
+ * Return 0, or i2c_smbus_write_byte ERROR code.
+ */
+static int
+taos_i2c_read(struct i2c_client *client, u8 reg, u8 *val, unsigned int len)
+{
+ int ret;
+ int i;
+
+ for (i = 0; i < len; i++) {
+ /* select register to write */
+ ret = i2c_smbus_write_byte(client, (TSL258X_CMD_REG | reg));
+ if (ret < 0) {
+ dev_err(&client->dev, "taos_i2c_read failed to write"
+ " register %x\n", reg);
+ return ret;
+ }
+ /* read the data */
+ *val = i2c_smbus_read_byte(client);
+ val++;
+ reg++;
+ }
+ return 0;
+}
+
+/*
+ * Reads and calculates current lux value.
+ * The raw ch0 and ch1 values of the ambient light sensed in the last
+ * integration cycle are read from the device.
+ * Time scale factor array values are adjusted based on the integration time.
+ * The raw values are multiplied by a scale factor, and device gain is obtained
+ * using gain index. Limit checks are done next, then the ratio of a multiple
+ * of ch1 value, to the ch0 value, is calculated. The array taos_device_lux[]
+ * declared above is then scanned to find the first ratio value that is just
+ * above the ratio we just calculated. The ch0 and ch1 multiplier constants in
+ * the array are then used along with the time scale factor array values, to
+ * calculate the lux.
+ */
+static int taos_get_lux(struct i2c_client *client)
+{
+ u16 ch0, ch1; /* separated ch0/ch1 data from device */
+ u32 lux; /* raw lux calculated from device data */
+ u32 ratio;
+ u8 buf[5];
+ struct taos_lux *p;
+ struct tsl2583_chip *chip = i2c_get_clientdata(client);
+ int i, ret;
+ u32 ch0lux = 0;
+ u32 ch1lux = 0;
+
+ if (mutex_trylock(&chip->als_mutex) == 0) {
+ dev_info(&client->dev, "taos_get_lux device is busy\n");
+ return chip->als_cur_info.lux; /* busy, so return LAST VALUE */
+ }
+
+ if (chip->taos_chip_status != TSL258X_CHIP_WORKING) {
+ /* device is not enabled */
+ dev_err(&client->dev, "taos_get_lux device is not enabled\n");
+ ret = -EBUSY ;
+ goto out_unlock;
+ }
+
+ ret = taos_i2c_read(client, (TSL258X_CMD_REG), &buf[0], 1);
+ if (ret < 0) {
+ dev_err(&client->dev, "taos_get_lux failed to read CMD_REG\n");
+ goto out_unlock;
+ }
+ /* is data new & valid */
+ if (!(buf[0] & TSL258X_STA_ADC_INTR)) {
+ dev_err(&client->dev, "taos_get_lux data not valid\n");
+ ret = chip->als_cur_info.lux; /* return LAST VALUE */
+ goto out_unlock;
+ }
+
+ for (i = 0; i < 4; i++) {
+ int reg = TSL258X_CMD_REG | (TSL258X_ALS_CHAN0LO + i);
+ ret = taos_i2c_read(client, reg, &buf[i], 1);
+ if (ret < 0) {
+ dev_err(&client->dev, "taos_get_lux failed to read"
+ " register %x\n", reg);
+ goto out_unlock;
+ }
+ }
+
+ /* clear status, really interrupt status (interrupts are off), but
+ * we use the bit anyway - don't forget 0x80 - this is a command*/
+ ret = i2c_smbus_write_byte(client,
+ (TSL258X_CMD_REG | TSL258X_CMD_SPL_FN | TSL258X_CMD_ALS_INT_CLR));
+
+ if (ret < 0) {
+ dev_err(&client->dev,
+ "taos_i2c_write_command failed in taos_get_lux, err = %d\n",
+ ret);
+ goto out_unlock; /* have no data, so return failure */
+ }
+
+ /* extract ALS/lux data */
+ ch0 = le16_to_cpup((const __le16 *)&buf[0]);
+ ch1 = le16_to_cpup((const __le16 *)&buf[2]);
+
+ chip->als_cur_info.als_ch0 = ch0;
+ chip->als_cur_info.als_ch1 = ch1;
+
+ if ((ch0 >= chip->als_saturation) || (ch1 >= chip->als_saturation))
+ goto return_max;
+
+ if (ch0 == 0) {
+ /* have no data, so return LAST VALUE */
+ ret = chip->als_cur_info.lux = 0;
+ goto out_unlock;
+ }
+ /* calculate ratio */
+ ratio = (ch1 << 15) / ch0;
+ /* convert to unscaled lux using the pointer to the table */
+ for (p = (struct taos_lux *) taos_device_lux;
+ p->ratio != 0 && p->ratio < ratio; p++)
+ ;
+
+ if (p->ratio == 0) {
+ lux = 0;
+ } else {
+ ch0lux = ((ch0 * p->ch0) +
+ (gainadj[chip->taos_settings.als_gain].ch0 >> 1))
+ / gainadj[chip->taos_settings.als_gain].ch0;
+ ch1lux = ((ch1 * p->ch1) +
+ (gainadj[chip->taos_settings.als_gain].ch1 >> 1))
+ / gainadj[chip->taos_settings.als_gain].ch1;
+ lux = ch0lux - ch1lux;
+ }
+
+ /* note: lux is 31 bit max at this point */
+ if (ch1lux > ch0lux) {
+ dev_dbg(&client->dev, "No Data - Return last value\n");
+ ret = chip->als_cur_info.lux = 0;
+ goto out_unlock;
+ }
+
+ /* adjust for active time scale */
+ if (chip->als_time_scale == 0)
+ lux = 0;
+ else
+ lux = (lux + (chip->als_time_scale >> 1)) /
+ chip->als_time_scale;
+
+ /* adjust for active gain scale */
+ lux >>= 13; /* tables have factor of 8192 builtin for accuracy */
+ lux = (lux * chip->taos_settings.als_gain_trim + 500) / 1000;
+ if (lux > TSL258X_LUX_CALC_OVER_FLOW) { /* check for overflow */
+return_max:
+ lux = TSL258X_LUX_CALC_OVER_FLOW;
+ }
+
+ /* Update the structure with the latest VALID lux. */
+ chip->als_cur_info.lux = lux;
+ ret = lux;
+
+out_unlock:
+ mutex_unlock(&chip->als_mutex);
+ return ret;
+}
+
+/*
+ * Obtain single reading and calculate the als_gain_trim (later used
+ * to derive actual lux).
+ * Return updated gain_trim value.
+ */
+int taos_als_calibrate(struct i2c_client *client)
+{
+ struct tsl2583_chip *chip = i2c_get_clientdata(client);
+ u8 reg_val;
+ unsigned int gain_trim_val;
+ int ret;
+ int lux_val;
+
+ ret = i2c_smbus_write_byte(client, (TSL258X_CMD_REG | TSL258X_CNTRL));
+ if (ret < 0) {
+ dev_err(&client->dev,
+ "taos_als_calibrate failed to reach the CNTRL register, ret=%d\n",
+ ret);
+ return ret;
+ }
+
+ reg_val = i2c_smbus_read_byte(client);
+ if ((reg_val & (TSL258X_CNTL_ADC_ENBL | TSL258X_CNTL_PWR_ON))
+ != (TSL258X_CNTL_ADC_ENBL | TSL258X_CNTL_PWR_ON)) {
+ dev_err(&client->dev,
+ "taos_als_calibrate failed: device not powered on with ADC enabled\n");
+ return -1;
+ }
+
+ ret = i2c_smbus_write_byte(client, (TSL258X_CMD_REG | TSL258X_CNTRL));
+ if (ret < 0) {
+ dev_err(&client->dev,
+ "taos_als_calibrate failed to reach the STATUS register, ret=%d\n",
+ ret);
+ return ret;
+ }
+ reg_val = i2c_smbus_read_byte(client);
+
+ if ((reg_val & TSL258X_STA_ADC_VALID) != TSL258X_STA_ADC_VALID) {
+ dev_err(&client->dev,
+ "taos_als_calibrate failed: STATUS - ADC not valid.\n");
+ return -ENODATA;
+ }
+ lux_val = taos_get_lux(client);
+ if (lux_val < 0) {
+ dev_err(&client->dev, "taos_als_calibrate failed to get lux\n");
+ return lux_val;
+ }
+ gain_trim_val = (unsigned int) (((chip->taos_settings.als_cal_target)
+ * chip->taos_settings.als_gain_trim) / lux_val);
+
+ if ((gain_trim_val < 250) || (gain_trim_val > 4000)) {
+ dev_err(&client->dev,
+ "taos_als_calibrate failed: trim_val of %d is out of range\n",
+ gain_trim_val);
+ return -ENODATA;
+ }
+ chip->taos_settings.als_gain_trim = (int) gain_trim_val;
+
+ return (int) gain_trim_val;
+}
+
+/*
+ * Turn the device on.
+ * Configuration must be set before calling this function.
+ */
+static int taos_chip_on(struct i2c_client *client)
+{
+ int i;
+ int ret = 0;
+ u8 *uP;
+ u8 utmp;
+ int als_count;
+ int als_time;
+ struct tsl2583_chip *chip = i2c_get_clientdata(client);
+
+ /* and make sure we're not already on */
+ if (chip->taos_chip_status == TSL258X_CHIP_WORKING) {
+ /* if forcing a register update - turn off, then on */
+ dev_info(&client->dev, "device is already enabled\n");
+ return -EINVAL;
+ }
+
+ /* determine als integration regster */
+ als_count = (chip->taos_settings.als_time * 100 + 135) / 270;
+ if (als_count == 0)
+ als_count = 1; /* ensure at least one cycle */
+
+ /* convert back to time (encompasses overrides) */
+ als_time = (als_count * 27 + 5) / 10;
+ chip->taos_config[TSL258X_ALS_TIME] = 256 - als_count;
+
+ /* Set the gain based on taos_settings struct */
+ chip->taos_config[TSL258X_GAIN] = chip->taos_settings.als_gain;
+
+ /* set chip struct re scaling and saturation */
+ chip->als_saturation = als_count * 922; /* 90% of full scale */
+ chip->als_time_scale = (als_time + 25) / 50;
+
+ /* TSL258x Specific power-on / adc enable sequence
+ * Power on the device 1st. */
+ utmp = TSL258X_CNTL_PWR_ON;
+ ret = i2c_smbus_write_byte_data(client,
+ TSL258X_CMD_REG | TSL258X_CNTRL, utmp);
+ if (ret < 0) {
+ dev_err(&client->dev, "taos_chip_on failed on CNTRL reg.\n");
+ return -1;
+ }
+
+ /* Use the following shadow copy for our delay before enabling ADC.
+ * Write all the registers. */
+ for (i = 0, uP = chip->taos_config; i < TSL258X_REG_MAX; i++) {
+ ret = i2c_smbus_write_byte_data(client, TSL258X_CMD_REG + i,
+ *uP++);
+ if (ret < 0) {
+ dev_err(&client->dev,
+ "taos_chip_on failed on reg %d.\n", i);
+ return -1;
+ }
+ }
+
+ msleep(3);
+ /* NOW enable the ADC
+ * initialize the desired mode of operation */
+ utmp = TSL258X_CNTL_PWR_ON | TSL258X_CNTL_ADC_ENBL;
+ ret = i2c_smbus_write_byte_data(client, TSL258X_CMD_REG | TSL258X_CNTRL,
+ utmp);
+ if (ret < 0) {
+ dev_err(&client->dev, "taos_chip_on failed on 2nd CTRL reg.\n");
+ return -1;
+ }
+ chip->taos_chip_status = TSL258X_CHIP_WORKING;
+
+ return ret;
+}
+
+static int taos_chip_off(struct i2c_client *client)
+{
+ struct tsl2583_chip *chip = i2c_get_clientdata(client);
+ int ret;
+
+ /* turn device off */
+ chip->taos_chip_status = TSL258X_CHIP_SUSPENDED;
+ ret = i2c_smbus_write_byte_data(client, TSL258X_CMD_REG | TSL258X_CNTRL,
+ 0x00);
+ return ret;
+}
+
+/* Sysfs Interface Functions */
+static ssize_t taos_device_id(struct device *dev,
+struct device_attribute *attr, char *buf)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ struct tsl2583_chip *chip = indio_dev->dev_data;
+
+ return sprintf(buf, "%s\n", chip->client->name);
+}
+
+static ssize_t taos_power_state_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ struct tsl2583_chip *chip = indio_dev->dev_data;
+
+ return sprintf(buf, "%d\n", chip->taos_chip_status);
+}
+
+static ssize_t taos_power_state_store(struct device *dev,
+ struct device_attribute *attr, const char *buf, size_t len)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ struct tsl2583_chip *chip = indio_dev->dev_data;
+ unsigned long value;
+
+ if (strict_strtoul(buf, 0, &value))
+ return -EINVAL;
+
+ if (value == 0)
+ taos_chip_off(chip->client);
+ else
+ taos_chip_on(chip->client);
+
+ return len;
+}
+
+static ssize_t taos_gain_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ struct tsl2583_chip *chip = indio_dev->dev_data;
+ char gain[4] = {0};
+
+ switch (chip->taos_settings.als_gain) {
+ case 0:
+ strcpy(gain, "001");
+ break;
+ case 1:
+ strcpy(gain, "008");
+ break;
+ case 2:
+ strcpy(gain, "016");
+ break;
+ case 3:
+ strcpy(gain, "111");
+ break;
+ }
+
+ return sprintf(buf, "%s\n", gain);
+}
+
+static ssize_t taos_gain_store(struct device *dev,
+ struct device_attribute *attr, const char *buf, size_t len)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ struct tsl2583_chip *chip = indio_dev->dev_data;
+ unsigned long value;
+
+ if (strict_strtoul(buf, 0, &value))
+ return -EINVAL;
+
+ switch (value) {
+ case 1:
+ chip->taos_settings.als_gain = 0;
+ break;
+ case 8:
+ chip->taos_settings.als_gain = 1;
+ break;
+ case 16:
+ chip->taos_settings.als_gain = 2;
+ break;
+ case 111:
+ chip->taos_settings.als_gain = 3;
+ break;
+ default:
+ dev_err(dev, "Invalid Gain Index (must be 1,8,16,111)\n");
+ return -1;
+ }
+
+ return len;
+}
+
+static ssize_t taos_gain_available_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%s\n", "1 8 16 111");
+}
+
+static ssize_t taos_als_time_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ struct tsl2583_chip *chip = indio_dev->dev_data;
+
+ return sprintf(buf, "%d\n", chip->taos_settings.als_time);
+}
+
+static ssize_t taos_als_time_store(struct device *dev,
+ struct device_attribute *attr, const char *buf, size_t len)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ struct tsl2583_chip *chip = indio_dev->dev_data;
+ unsigned long value;
+
+ if (strict_strtoul(buf, 0, &value))
+ return -EINVAL;
+
+ if ((value < 50) || (value > 650))
+ return -EINVAL;
+
+ if (value % 50)
+ return -EINVAL;
+
+ chip->taos_settings.als_time = value;
+
+ return len;
+}
+
+static ssize_t taos_als_time_available_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%s\n",
+ "50 100 150 200 250 300 350 400 450 500 550 600 650");
+}
+
+static ssize_t taos_als_trim_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ struct tsl2583_chip *chip = indio_dev->dev_data;
+
+ return sprintf(buf, "%d\n", chip->taos_settings.als_gain_trim);
+}
+
+static ssize_t taos_als_trim_store(struct device *dev,
+ struct device_attribute *attr, const char *buf, size_t len)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ struct tsl2583_chip *chip = indio_dev->dev_data;
+ unsigned long value;
+
+ if (strict_strtoul(buf, 0, &value))
+ return -EINVAL;
+
+ if (value)
+ chip->taos_settings.als_gain_trim = value;
+
+ return len;
+}
+
+static ssize_t taos_als_cal_target_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ struct tsl2583_chip *chip = indio_dev->dev_data;
+
+ return sprintf(buf, "%d\n", chip->taos_settings.als_cal_target);
+}
+
+static ssize_t taos_als_cal_target_store(struct device *dev,
+ struct device_attribute *attr, const char *buf, size_t len)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ struct tsl2583_chip *chip = indio_dev->dev_data;
+ unsigned long value;
+
+ if (strict_strtoul(buf, 0, &value))
+ return -EINVAL;
+
+ if (value)
+ chip->taos_settings.als_cal_target = value;
+
+ return len;
+}
+
+static ssize_t taos_lux_show(struct device *dev, struct device_attribute *attr,
+ char *buf)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ struct tsl2583_chip *chip = indio_dev->dev_data;
+ int lux;
+
+ lux = taos_get_lux(chip->client);
+
+ return sprintf(buf, "%d\n", lux);
+}
+
+static ssize_t taos_do_calibrate(struct device *dev,
+ struct device_attribute *attr, const char *buf, size_t len)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ struct tsl2583_chip *chip = indio_dev->dev_data;
+ unsigned long value;
+
+ if (strict_strtoul(buf, 0, &value))
+ return -EINVAL;
+
+ if (value == 1)
+ taos_als_calibrate(chip->client);
+
+ return len;
+}
+
+static ssize_t taos_luxtable_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ int i;
+ int offset = 0;
+
+ for (i = 0; i < ARRAY_SIZE(taos_device_lux); i++) {
+ offset += sprintf(buf + offset, "%d,%d,%d,",
+ taos_device_lux[i].ratio,
+ taos_device_lux[i].ch0,
+ taos_device_lux[i].ch1);
+ if (taos_device_lux[i].ratio == 0) {
+ /* We just printed the first "0" entry.
+ * Now get rid of the extra "," and break. */
+ offset--;
+ break;
+ }
+ }
+
+ offset += sprintf(buf + offset, "\n");
+ return offset;
+}
+
+static ssize_t taos_luxtable_store(struct device *dev,
+ struct device_attribute *attr, const char *buf, size_t len)
+{
+ struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ struct tsl2583_chip *chip = indio_dev->dev_data;
+ int value[ARRAY_SIZE(taos_device_lux)];
+ int n;
+
+ get_options(buf, ARRAY_SIZE(value), value);
+
+ /* We now have an array of ints starting at value[1], and
+ * enumerated by value[0].
+ * We expect each group of three ints is one table entry,
+ * and the last table entry is all 0.
+ */
+ n = value[0];
+ if ((n % 3) || n < 6 || n > ((ARRAY_SIZE(taos_device_lux) - 1) * 3)) {
+ dev_info(dev, "LUX TABLE INPUT ERROR 1 Value[0]=%d\n", n);
+ return -EINVAL;
+ }
+ if ((value[(n - 2)] | value[(n - 1)] | value[n]) != 0) {
+ dev_info(dev, "LUX TABLE INPUT ERROR 2 Value[0]=%d\n", n);
+ return -EINVAL;
+ }
+
+ if (chip->taos_chip_status == TSL258X_CHIP_WORKING)
+ taos_chip_off(chip->client);
+
+ /* Zero out the table */
+ memset(taos_device_lux, 0, sizeof(taos_device_lux));
+ memcpy(taos_device_lux, &value[1], (value[0] * 4));
+
+ taos_chip_on(chip->client);
+
+ return len;
+}
+
+static DEVICE_ATTR(name, S_IRUGO, taos_device_id, NULL);
+static DEVICE_ATTR(power_state, S_IRUGO | S_IWUSR,
+ taos_power_state_show, taos_power_state_store);
+
+static DEVICE_ATTR(illuminance0_calibscale, S_IRUGO | S_IWUSR,
+ taos_gain_show, taos_gain_store);
+static DEVICE_ATTR(illuminance0_calibscale_available, S_IRUGO,
+ taos_gain_available_show, NULL);
+
+static DEVICE_ATTR(illuminance0_integration_time, S_IRUGO | S_IWUSR,
+ taos_als_time_show, taos_als_time_store);
+static DEVICE_ATTR(illuminance0_integration_time_available, S_IRUGO,
+ taos_als_time_available_show, NULL);
+
+static DEVICE_ATTR(illuminance0_calibbias, S_IRUGO | S_IWUSR,
+ taos_als_trim_show, taos_als_trim_store);
+
+static DEVICE_ATTR(illuminance0_input_target, S_IRUGO | S_IWUSR,
+ taos_als_cal_target_show, taos_als_cal_target_store);
+
+static DEVICE_ATTR(illuminance0_input, S_IRUGO, taos_lux_show, NULL);
+static DEVICE_ATTR(illuminance0_calibrate, S_IWUSR, NULL, taos_do_calibrate);
+static DEVICE_ATTR(illuminance0_lux_table, S_IRUGO | S_IWUSR,
+ taos_luxtable_show, taos_luxtable_store);
+
+static struct attribute *sysfs_attrs_ctrl[] = {
+ &dev_attr_name.attr,
+ &dev_attr_power_state.attr,
+ &dev_attr_illuminance0_calibscale.attr, /* Gain */
+ &dev_attr_illuminance0_calibscale_available.attr,
+ &dev_attr_illuminance0_integration_time.attr, /* I time*/
+ &dev_attr_illuminance0_integration_time_available.attr,
+ &dev_attr_illuminance0_calibbias.attr, /* trim */
+ &dev_attr_illuminance0_input_target.attr,
+ &dev_attr_illuminance0_input.attr,
+ &dev_attr_illuminance0_calibrate.attr,
+ &dev_attr_illuminance0_lux_table.attr,
+ NULL
+};
+
+static struct attribute_group tsl2583_attribute_group = {
+ .attrs = sysfs_attrs_ctrl,
+};
+
+/* Use the default register values to identify the Taos device */
+static int taos_tsl258x_device(unsigned char *bufp)
+{
+ return ((bufp[TSL258X_CHIPID] & 0xf0) == 0x90);
+}
+
+static const struct iio_info tsl2583_info = {
+ .attrs = &tsl2583_attribute_group,
+ .driver_module = THIS_MODULE,
+};
+
+/*
+ * Client probe function - When a valid device is found, the driver's device
+ * data structure is updated, and initialization completes successfully.
+ */
+static int __devinit taos_probe(struct i2c_client *clientp,
+ const struct i2c_device_id *idp)
+{
+ int i, ret = 0;
+ unsigned char buf[TSL258X_MAX_DEVICE_REGS];
+ static struct tsl2583_chip *chip;
+
+ if (!i2c_check_functionality(clientp->adapter,
+ I2C_FUNC_SMBUS_BYTE_DATA)) {
+ dev_err(&clientp->dev,
+ "taos_probe() - i2c smbus byte data "
+ "functions unsupported\n");
+ return -EOPNOTSUPP;
+ }
+
+ chip = kzalloc(sizeof(struct tsl2583_chip), GFP_KERNEL);
+ if (!chip)
+ return -ENOMEM;
+
+ chip->client = clientp;
+ i2c_set_clientdata(clientp, chip);
+
+ mutex_init(&chip->als_mutex);
+ chip->taos_chip_status = TSL258X_CHIP_UNKNOWN;
+ memcpy(chip->taos_config, taos_config, sizeof(chip->taos_config));
+
+ for (i = 0; i < TSL258X_MAX_DEVICE_REGS; i++) {
+ ret = i2c_smbus_write_byte(clientp,
+ (TSL258X_CMD_REG | (TSL258X_CNTRL + i)));
+ if (ret < 0) {
+ dev_err(&clientp->dev, "i2c_smbus_write_bytes() to cmd "
+ "reg failed in taos_probe(), err = %d\n", ret);
+ goto fail1;
+ }
+ ret = i2c_smbus_read_byte(clientp);
+ if (ret < 0) {
+ dev_err(&clientp->dev, "i2c_smbus_read_byte from "
+ "reg failed in taos_probe(), err = %d\n", ret);
+
+ goto fail1;
+ }
+ buf[i] = ret;
+ }
+
+ if (!taos_tsl258x_device(buf)) {
+ dev_info(&clientp->dev, "i2c device found but does not match "
+ "expected id in taos_probe()\n");
+ goto fail1;
+ }
+
+ ret = i2c_smbus_write_byte(clientp, (TSL258X_CMD_REG | TSL258X_CNTRL));
+ if (ret < 0) {
+ dev_err(&clientp->dev, "i2c_smbus_write_byte() to cmd reg "
+ "failed in taos_probe(), err = %d\n", ret);
+ goto fail1;
+ }
+
+ chip->iio_dev = iio_allocate_device(0);
+ if (!chip->iio_dev) {
+ ret = -ENOMEM;
+ dev_err(&clientp->dev, "iio allocation failed\n");
+ goto fail1;
+ }
+
+ chip->iio_dev->info = &tsl2583_info;
+ chip->iio_dev->dev.parent = &clientp->dev;
+ chip->iio_dev->dev_data = (void *)(chip);
+ chip->iio_dev->modes = INDIO_DIRECT_MODE;
+ ret = iio_device_register(chip->iio_dev);
+ if (ret) {
+ dev_err(&clientp->dev, "iio registration failed\n");
+ goto fail1;
+ }
+
+ /* Load up the V2 defaults (these are hard coded defaults for now) */
+ taos_defaults(chip);
+
+ /* Make sure the chip is on */
+ taos_chip_on(clientp);
+
+ dev_info(&clientp->dev, "Light sensor found.\n");
+
+ return 0;
+
+fail1:
+ kfree(chip);
+
+ return ret;
+}
+
+static int taos_suspend(struct i2c_client *client, pm_message_t state)
+{
+ struct tsl2583_chip *chip = i2c_get_clientdata(client);
+ int ret = 0;
+
+ mutex_lock(&chip->als_mutex);
+
+ if (chip->taos_chip_status == TSL258X_CHIP_WORKING) {
+ ret = taos_chip_off(client);
+ chip->taos_chip_status = TSL258X_CHIP_SUSPENDED;
+ }
+
+ mutex_unlock(&chip->als_mutex);
+ return ret;
+}
+
+static int taos_resume(struct i2c_client *client)
+{
+ struct tsl2583_chip *chip = i2c_get_clientdata(client);
+ int ret = 0;
+
+ mutex_lock(&chip->als_mutex);
+
+ if (chip->taos_chip_status == TSL258X_CHIP_SUSPENDED)
+ ret = taos_chip_on(client);
+
+ mutex_unlock(&chip->als_mutex);
+ return ret;
+}
+
+
+static int __devexit taos_remove(struct i2c_client *client)
+{
+ struct tsl2583_chip *chip = i2c_get_clientdata(client);
+
+ iio_device_unregister(chip->iio_dev);
+
+ kfree(chip);
+ return 0;
+}
+
+static struct i2c_device_id taos_idtable[] = {
+ { "tsl2580", 0 },
+ { "tsl2581", 1 },
+ { "tsl2583", 2 },
+ {}
+};
+MODULE_DEVICE_TABLE(i2c, taos_idtable);
+
+/* Driver definition */
+static struct i2c_driver taos_driver = {
+ .driver = {
+ .name = "tsl2583",
+ },
+ .id_table = taos_idtable,
+ .suspend = taos_suspend,
+ .resume = taos_resume,
+ .probe = taos_probe,
+ .remove = __devexit_p(taos_remove),
+};
+
+static int __init taos_init(void)
+{
+ return i2c_add_driver(&taos_driver);
+}
+
+static void __exit taos_exit(void)
+{
+ i2c_del_driver(&taos_driver);
+}
+
+module_init(taos_init);
+module_exit(taos_exit);
+
+MODULE_AUTHOR("J. August Brenner<jbrenner@taosinc.com>");
+MODULE_DESCRIPTION("TAOS tsl2583 ambient light sensor driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/staging/iio/magnetometer/ak8975.c b/drivers/staging/iio/magnetometer/ak8975.c
index 420f206..700f96c 100644
--- a/drivers/staging/iio/magnetometer/ak8975.c
+++ b/drivers/staging/iio/magnetometer/ak8975.c
@@ -206,7 +206,7 @@
}
/* Precalculate scale factor for each axis and
- store in the device data. */
+ store in the device data. */
data->raw_to_gauss[0] = ((data->asa[0] + 128) * 30) >> 8;
data->raw_to_gauss[1] = ((data->asa[1] + 128) * 30) >> 8;
data->raw_to_gauss[2] = ((data->asa[2] + 128) * 30) >> 8;
@@ -316,6 +316,59 @@
return sprintf(buf, "%ld\n", data->raw_to_gauss[this_attr->address]);
}
+static int wait_conversion_complete_gpio(struct ak8975_data *data)
+{
+ struct i2c_client *client = data->client;
+ u8 read_status;
+ u32 timeout_ms = AK8975_MAX_CONVERSION_TIMEOUT;
+ int ret;
+
+ /* Wait for the conversion to complete. */
+ while (timeout_ms) {
+ msleep(AK8975_CONVERSION_DONE_POLL_TIME);
+ if (gpio_get_value(data->eoc_gpio))
+ break;
+ timeout_ms -= AK8975_CONVERSION_DONE_POLL_TIME;
+ }
+ if (!timeout_ms) {
+ dev_err(&client->dev, "Conversion timeout happened\n");
+ return -EINVAL;
+ }
+
+ ret = ak8975_read_data(client, AK8975_REG_ST1, 1, &read_status);
+ if (ret < 0) {
+ dev_err(&client->dev, "Error in reading ST1\n");
+ return ret;
+ }
+ return read_status;
+}
+
+static int wait_conversion_complete_polled(struct ak8975_data *data)
+{
+ struct i2c_client *client = data->client;
+ u8 read_status;
+ u32 timeout_ms = AK8975_MAX_CONVERSION_TIMEOUT;
+ int ret;
+
+ /* Wait for the conversion to complete. */
+ while (timeout_ms) {
+ msleep(AK8975_CONVERSION_DONE_POLL_TIME);
+ ret = ak8975_read_data(client, AK8975_REG_ST1, 1, &read_status);
+ if (ret < 0) {
+ dev_err(&client->dev, "Error in reading ST1\n");
+ return ret;
+ }
+ if (read_status)
+ break;
+ timeout_ms -= AK8975_CONVERSION_DONE_POLL_TIME;
+ }
+ if (!timeout_ms) {
+ dev_err(&client->dev, "Conversion timeout happened\n");
+ return -EINVAL;
+ }
+ return read_status;
+}
+
/*
* Emits the raw flux value for the x, y, or z axis.
*/
@@ -326,7 +379,6 @@
struct ak8975_data *data = indio_dev->dev_data;
struct i2c_client *client = data->client;
struct iio_dev_attr *this_attr = to_iio_dev_attr(devattr);
- u32 timeout_ms = AK8975_MAX_CONVERSION_TIMEOUT;
u16 meas_reg;
s16 raw;
u8 read_status;
@@ -352,23 +404,14 @@
}
/* Wait for the conversion to complete. */
- while (timeout_ms) {
- msleep(AK8975_CONVERSION_DONE_POLL_TIME);
- if (gpio_get_value(data->eoc_gpio))
- break;
- timeout_ms -= AK8975_CONVERSION_DONE_POLL_TIME;
- }
- if (!timeout_ms) {
- dev_err(&client->dev, "Conversion timeout happened\n");
- ret = -EINVAL;
+ if (data->eoc_gpio)
+ ret = wait_conversion_complete_gpio(data);
+ else
+ ret = wait_conversion_complete_polled(data);
+ if (ret < 0)
goto exit;
- }
- ret = ak8975_read_data(client, AK8975_REG_ST1, 1, &read_status);
- if (ret < 0) {
- dev_err(&client->dev, "Error in reading ST1\n");
- goto exit;
- }
+ read_status = ret;
if (read_status & AK8975_REG_ST1_DRDY_MASK) {
ret = ak8975_read_data(client, AK8975_REG_ST2, 1, &read_status);
@@ -431,6 +474,11 @@
.attrs = ak8975_attr,
};
+static const struct iio_info ak8975_info = {
+ .attrs = &ak8975_attr_group,
+ .driver_module = THIS_MODULE,
+};
+
static int ak8975_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
@@ -454,25 +502,26 @@
data->eoc_irq = client->irq;
data->eoc_gpio = irq_to_gpio(client->irq);
- if (!data->eoc_gpio) {
- dev_err(&client->dev, "failed, no valid GPIO\n");
- err = -EINVAL;
- goto exit_free;
- }
+ /* We may not have a GPIO based IRQ to scan, that is fine, we will
+ poll if so */
+ if (data->eoc_gpio > 0) {
+ err = gpio_request(data->eoc_gpio, "ak_8975");
+ if (err < 0) {
+ dev_err(&client->dev,
+ "failed to request GPIO %d, error %d\n",
+ data->eoc_gpio, err);
+ goto exit_free;
+ }
- err = gpio_request(data->eoc_gpio, "ak_8975");
- if (err < 0) {
- dev_err(&client->dev, "failed to request GPIO %d, error %d\n",
- data->eoc_gpio, err);
- goto exit_free;
- }
-
- err = gpio_direction_input(data->eoc_gpio);
- if (err < 0) {
- dev_err(&client->dev, "Failed to configure input direction for"
- " GPIO %d, error %d\n", data->eoc_gpio, err);
- goto exit_gpio;
- }
+ err = gpio_direction_input(data->eoc_gpio);
+ if (err < 0) {
+ dev_err(&client->dev,
+ "Failed to configure input direction for GPIO %d, error %d\n",
+ data->eoc_gpio, err);
+ goto exit_gpio;
+ }
+ } else
+ data->eoc_gpio = 0; /* No GPIO available */
/* Perform some basic start-of-day setup of the device. */
err = ak8975_setup(client);
@@ -482,16 +531,15 @@
}
/* Register with IIO */
- data->indio_dev = iio_allocate_device();
+ data->indio_dev = iio_allocate_device(0);
if (data->indio_dev == NULL) {
err = -ENOMEM;
goto exit_gpio;
}
data->indio_dev->dev.parent = &client->dev;
- data->indio_dev->attrs = &ak8975_attr_group;
+ data->indio_dev->info = &ak8975_info;
data->indio_dev->dev_data = (void *)(data);
- data->indio_dev->driver_module = THIS_MODULE;
data->indio_dev->modes = INDIO_DIRECT_MODE;
err = iio_device_register(data->indio_dev);
@@ -503,7 +551,8 @@
exit_free_iio:
iio_free_device(data->indio_dev);
exit_gpio:
- gpio_free(data->eoc_gpio);
+ if (data->eoc_gpio)
+ gpio_free(data->eoc_gpio);
exit_free:
kfree(data);
exit:
@@ -517,7 +566,8 @@
iio_device_unregister(data->indio_dev);
iio_free_device(data->indio_dev);
- gpio_free(data->eoc_gpio);
+ if (data->eoc_gpio)
+ gpio_free(data->eoc_gpio);
kfree(data);
diff --git a/drivers/staging/iio/magnetometer/hmc5843.c b/drivers/staging/iio/magnetometer/hmc5843.c
index 5168917..dd9a3bb 100644
--- a/drivers/staging/iio/magnetometer/hmc5843.c
+++ b/drivers/staging/iio/magnetometer/hmc5843.c
@@ -529,6 +529,11 @@
pr_info("HMC5843 initialized\n");
}
+static const struct iio_info hmc5843_info = {
+ .attrs = &hmc5843_group,
+ .driver_module = THIS_MODULE,
+};
+
static int hmc5843_probe(struct i2c_client *client,
const struct i2c_device_id *id)
{
@@ -552,15 +557,14 @@
/* Initialize the HMC5843 chip */
hmc5843_init_client(client);
- data->indio_dev = iio_allocate_device();
+ data->indio_dev = iio_allocate_device(0);
if (!data->indio_dev) {
err = -ENOMEM;
goto exit_free1;
}
- data->indio_dev->attrs = &hmc5843_group;
+ data->indio_dev->info = &hmc5843_info;
data->indio_dev->dev.parent = &client->dev;
data->indio_dev->dev_data = (void *)(data);
- data->indio_dev->driver_module = THIS_MODULE;
data->indio_dev->modes = INDIO_DIRECT_MODE;
err = iio_device_register(data->indio_dev);
if (err)
diff --git a/drivers/staging/iio/meter/ade7753.c b/drivers/staging/iio/meter/ade7753.c
index 8b86d82..6c9c23f 100644
--- a/drivers/staging/iio/meter/ade7753.c
+++ b/drivers/staging/iio/meter/ade7753.c
@@ -463,8 +463,6 @@
static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("27900 14000 7000 3500");
-static IIO_CONST_ATTR(name, "ade7753");
-
static struct attribute *ade7753_attributes[] = {
&iio_dev_attr_temp_raw.dev_attr.attr,
&iio_const_attr_temp_offset.dev_attr.attr,
@@ -472,7 +470,6 @@
&iio_dev_attr_sampling_frequency.dev_attr.attr,
&iio_const_attr_sampling_frequency_available.dev_attr.attr,
&iio_dev_attr_reset.dev_attr.attr,
- &iio_const_attr_name.dev_attr.attr,
&iio_dev_attr_phcal.dev_attr.attr,
&iio_dev_attr_cfden.dev_attr.attr,
&iio_dev_attr_aenergy.dev_attr.attr,
@@ -507,6 +504,11 @@
.attrs = ade7753_attributes,
};
+static const struct iio_info ade7753_info = {
+ .attrs = &ade7753_attribute_group,
+ .driver_module = THIS_MODULE,
+};
+
static int __devinit ade7753_probe(struct spi_device *spi)
{
int ret, regdone = 0;
@@ -532,16 +534,16 @@
st->us = spi;
mutex_init(&st->buf_lock);
/* setup the industrialio driver allocated elements */
- st->indio_dev = iio_allocate_device();
+ st->indio_dev = iio_allocate_device(0);
if (st->indio_dev == NULL) {
ret = -ENOMEM;
goto error_free_tx;
}
+ st->indio_dev->name = spi->dev.driver->name;
st->indio_dev->dev.parent = &spi->dev;
- st->indio_dev->attrs = &ade7753_attribute_group;
+ st->indio_dev->info = &ade7753_info;
st->indio_dev->dev_data = (void *)(st);
- st->indio_dev->driver_module = THIS_MODULE;
st->indio_dev->modes = INDIO_DIRECT_MODE;
ret = iio_device_register(st->indio_dev);
diff --git a/drivers/staging/iio/meter/ade7754.c b/drivers/staging/iio/meter/ade7754.c
index 4272818..378f2c8 100644
--- a/drivers/staging/iio/meter/ade7754.c
+++ b/drivers/staging/iio/meter/ade7754.c
@@ -482,8 +482,6 @@
static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("26000 13000 65000 33000");
-static IIO_CONST_ATTR(name, "ade7754");
-
static struct attribute *ade7754_attributes[] = {
&iio_dev_attr_temp_raw.dev_attr.attr,
&iio_const_attr_temp_offset.dev_attr.attr,
@@ -491,7 +489,6 @@
&iio_dev_attr_sampling_frequency.dev_attr.attr,
&iio_const_attr_sampling_frequency_available.dev_attr.attr,
&iio_dev_attr_reset.dev_attr.attr,
- &iio_const_attr_name.dev_attr.attr,
&iio_dev_attr_aenergy.dev_attr.attr,
&iio_dev_attr_laenergy.dev_attr.attr,
&iio_dev_attr_vaenergy.dev_attr.attr,
@@ -530,7 +527,10 @@
.attrs = ade7754_attributes,
};
-
+static const struct iio_info ade7754_info = {
+ .attrs = &ade7754_attribute_group,
+ .driver_module = THIS_MODULE,
+};
static int __devinit ade7754_probe(struct spi_device *spi)
{
@@ -557,16 +557,16 @@
st->us = spi;
mutex_init(&st->buf_lock);
/* setup the industrialio driver allocated elements */
- st->indio_dev = iio_allocate_device();
+ st->indio_dev = iio_allocate_device(0);
if (st->indio_dev == NULL) {
ret = -ENOMEM;
goto error_free_tx;
}
+ st->indio_dev->name = spi->dev.driver->name;
st->indio_dev->dev.parent = &spi->dev;
- st->indio_dev->attrs = &ade7754_attribute_group;
+ st->indio_dev->info = &ade7754_info;
st->indio_dev->dev_data = (void *)(st);
- st->indio_dev->driver_module = THIS_MODULE;
st->indio_dev->modes = INDIO_DIRECT_MODE;
ret = iio_device_register(st->indio_dev);
diff --git a/drivers/staging/iio/meter/ade7758.h b/drivers/staging/iio/meter/ade7758.h
index c6fd94f..fd74e15 100644
--- a/drivers/staging/iio/meter/ade7758.h
+++ b/drivers/staging/iio/meter/ade7758.h
@@ -1,3 +1,11 @@
+/*
+ * ADE7758 Poly Phase Multifunction Energy Metering IC driver
+ *
+ * Copyright 2010-2011 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2.
+ */
+
#ifndef _ADE7758_H
#define _ADE7758_H
@@ -83,43 +91,54 @@
#define ADE7758_MAX_RX 4
#define ADE7758_STARTUP_DELAY 1
-#define ADE7758_SPI_SLOW (u32)(300 * 1000)
-#define ADE7758_SPI_BURST (u32)(1000 * 1000)
-#define ADE7758_SPI_FAST (u32)(2000 * 1000)
+#define AD7758_NUM_WAVSEL 5
+#define AD7758_NUM_PHSEL 3
+#define AD7758_NUM_WAVESRC (AD7758_NUM_WAVSEL * AD7758_NUM_PHSEL)
+
+#define AD7758_PHASE_A 0
+#define AD7758_PHASE_B 1
+#define AD7758_PHASE_C 2
+#define AD7758_CURRENT 0
+#define AD7758_VOLTAGE 1
+#define AD7758_ACT_PWR 2
+#define AD7758_REACT_PWR 3
+#define AD7758_APP_PWR 4
+#define AD7758_WT(p, w) (((w) << 2) | (p))
#define DRIVER_NAME "ade7758"
+
/**
* struct ade7758_state - device instance specific data
* @us: actual spi_device
- * @work_trigger_to_ring: bh for triggered event handling
- * @inter: used to check if new interrupt has been triggered
- * @last_timestamp: passing timestamp from th to bh of interrupt handler
- * @indio_dev: industrial I/O device structure
* @trig: data ready trigger registered with iio
* @tx: transmit buffer
* @rx: receive buffer
* @buf_lock: mutex to protect tx and rx
**/
struct ade7758_state {
- struct spi_device *us;
- struct work_struct work_trigger_to_ring;
- s64 last_timestamp;
- struct iio_dev *indio_dev;
- struct iio_trigger *trig;
- u8 *tx;
- u8 *rx;
- struct mutex buf_lock;
+ struct spi_device *us;
+ struct iio_trigger *trig;
+ u8 *tx;
+ u8 *rx;
+ struct mutex buf_lock;
+ u32 available_scan_masks[AD7758_NUM_WAVESRC];
+ struct iio_chan_spec *ade7758_ring_channels;
+ struct spi_transfer ring_xfer[4];
+ struct spi_message ring_msg;
+ /*
+ * DMA (thus cache coherency maintenance) requires the
+ * transfer buffers to live in their own cache lines.
+ */
+ unsigned char rx_buf[8] ____cacheline_aligned;
+ unsigned char tx_buf[8];
+
};
#ifdef CONFIG_IIO_RING_BUFFER
/* At the moment triggers are only used for ring buffer
* filling. This may change!
*/
-enum ade7758_scan {
- ADE7758_SCAN_WFORM,
-};
-
void ade7758_remove_trigger(struct iio_dev *indio_dev);
int ade7758_probe_trigger(struct iio_dev *indio_dev);
@@ -134,6 +153,12 @@
int ade7758_initialize_ring(struct iio_ring_buffer *ring);
void ade7758_uninitialize_ring(struct iio_ring_buffer *ring);
int ade7758_set_irq(struct device *dev, bool enable);
+
+int ade7758_spi_write_reg_8(struct device *dev,
+ u8 reg_address, u8 val);
+int ade7758_spi_read_reg_8(struct device *dev,
+ u8 reg_address, u8 *val);
+
#else /* CONFIG_IIO_RING_BUFFER */
static inline void ade7758_remove_trigger(struct iio_dev *indio_dev)
@@ -144,14 +169,6 @@
return 0;
}
-static inline ssize_t
-ade7758_read_data_from_ring(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- return 0;
-}
-
static int ade7758_configure_ring(struct iio_dev *indio_dev)
{
return 0;
diff --git a/drivers/staging/iio/meter/ade7758_core.c b/drivers/staging/iio/meter/ade7758_core.c
index b7634cb..299b954 100644
--- a/drivers/staging/iio/meter/ade7758_core.c
+++ b/drivers/staging/iio/meter/ade7758_core.c
@@ -1,9 +1,9 @@
/*
- * ADE7758 Polyphase Multifunction Energy Metering IC Driver
+ * ADE7758 Poly Phase Multifunction Energy Metering IC driver
*
- * Copyright 2010 Analog Devices Inc.
+ * Copyright 2010-2011 Analog Devices Inc.
*
- * Licensed under the GPL-2 or later.
+ * Licensed under the GPL-2.
*/
#include <linux/interrupt.h>
@@ -20,6 +20,7 @@
#include "../iio.h"
#include "../sysfs.h"
+#include "../ring_generic.h"
#include "meter.h"
#include "ade7758.h"
@@ -29,7 +30,7 @@
{
int ret;
struct iio_dev *indio_dev = dev_get_drvdata(dev);
- struct ade7758_state *st = iio_dev_get_devdata(indio_dev);
+ struct ade7758_state *st = iio_priv(indio_dev);
mutex_lock(&st->buf_lock);
st->tx[0] = ADE7758_WRITE_REG(reg_address);
@@ -48,7 +49,7 @@
int ret;
struct spi_message msg;
struct iio_dev *indio_dev = dev_get_drvdata(dev);
- struct ade7758_state *st = iio_dev_get_devdata(indio_dev);
+ struct ade7758_state *st = iio_priv(indio_dev);
struct spi_transfer xfers[] = {
{
.tx_buf = st->tx,
@@ -77,7 +78,7 @@
int ret;
struct spi_message msg;
struct iio_dev *indio_dev = dev_get_drvdata(dev);
- struct ade7758_state *st = iio_dev_get_devdata(indio_dev);
+ struct ade7758_state *st = iio_priv(indio_dev);
struct spi_transfer xfers[] = {
{
.tx_buf = st->tx,
@@ -100,20 +101,26 @@
return ret;
}
-static int ade7758_spi_read_reg_8(struct device *dev,
+int ade7758_spi_read_reg_8(struct device *dev,
u8 reg_address,
u8 *val)
{
struct spi_message msg;
struct iio_dev *indio_dev = dev_get_drvdata(dev);
- struct ade7758_state *st = iio_dev_get_devdata(indio_dev);
+ struct ade7758_state *st = iio_priv(indio_dev);
int ret;
struct spi_transfer xfers[] = {
{
.tx_buf = st->tx,
+ .bits_per_word = 8,
+ .len = 1,
+ .delay_usecs = 4,
+ },
+ {
+ .tx_buf = &st->tx[1],
.rx_buf = st->rx,
.bits_per_word = 8,
- .len = 2,
+ .len = 1,
},
};
@@ -122,14 +129,15 @@
st->tx[1] = 0;
spi_message_init(&msg);
- spi_message_add_tail(xfers, &msg);
+ spi_message_add_tail(&xfers[0], &msg);
+ spi_message_add_tail(&xfers[1], &msg);
ret = spi_sync(st->us, &msg);
if (ret) {
dev_err(&st->us->dev, "problem when reading 8 bit register 0x%02X",
reg_address);
goto error_ret;
}
- *val = st->rx[1];
+ *val = st->rx[0];
error_ret:
mutex_unlock(&st->buf_lock);
@@ -142,31 +150,40 @@
{
struct spi_message msg;
struct iio_dev *indio_dev = dev_get_drvdata(dev);
- struct ade7758_state *st = iio_dev_get_devdata(indio_dev);
+ struct ade7758_state *st = iio_priv(indio_dev);
int ret;
struct spi_transfer xfers[] = {
{
.tx_buf = st->tx,
+ .bits_per_word = 8,
+ .len = 1,
+ .delay_usecs = 4,
+ },
+ {
+ .tx_buf = &st->tx[1],
.rx_buf = st->rx,
.bits_per_word = 8,
- .len = 3,
+ .len = 2,
},
};
+
mutex_lock(&st->buf_lock);
st->tx[0] = ADE7758_READ_REG(reg_address);
st->tx[1] = 0;
st->tx[2] = 0;
spi_message_init(&msg);
- spi_message_add_tail(xfers, &msg);
+ spi_message_add_tail(&xfers[0], &msg);
+ spi_message_add_tail(&xfers[1], &msg);
ret = spi_sync(st->us, &msg);
if (ret) {
dev_err(&st->us->dev, "problem when reading 16 bit register 0x%02X",
reg_address);
goto error_ret;
}
- *val = (st->rx[1] << 8) | st->rx[2];
+
+ *val = (st->rx[0] << 8) | st->rx[1];
error_ret:
mutex_unlock(&st->buf_lock);
@@ -179,14 +196,20 @@
{
struct spi_message msg;
struct iio_dev *indio_dev = dev_get_drvdata(dev);
- struct ade7758_state *st = iio_dev_get_devdata(indio_dev);
+ struct ade7758_state *st = iio_priv(indio_dev);
int ret;
struct spi_transfer xfers[] = {
{
.tx_buf = st->tx,
+ .bits_per_word = 8,
+ .len = 1,
+ .delay_usecs = 4,
+ },
+ {
+ .tx_buf = &st->tx[1],
.rx_buf = st->rx,
.bits_per_word = 8,
- .len = 4,
+ .len = 3,
},
};
@@ -197,14 +220,15 @@
st->tx[3] = 0;
spi_message_init(&msg);
- spi_message_add_tail(xfers, &msg);
+ spi_message_add_tail(&xfers[0], &msg);
+ spi_message_add_tail(&xfers[1], &msg);
ret = spi_sync(st->us, &msg);
if (ret) {
dev_err(&st->us->dev, "problem when reading 24 bit register 0x%02X",
reg_address);
goto error_ret;
}
- *val = (st->rx[1] << 16) | (st->rx[2] << 8) | st->rx[3];
+ *val = (st->rx[0] << 16) | (st->rx[1] << 8) | st->rx[2];
error_ret:
mutex_unlock(&st->buf_lock);
@@ -292,7 +316,7 @@
return ret ? ret : len;
}
-int ade7758_reset(struct device *dev)
+static int ade7758_reset(struct device *dev)
{
int ret;
u8 val;
@@ -319,7 +343,7 @@
case 'Y':
return ade7758_reset(dev);
}
- return -1;
+ return len;
}
static IIO_DEV_ATTR_VPEAK(S_IWUSR | S_IRUGO,
@@ -461,13 +485,14 @@
return ret;
}
-static int ade7758_initial_setup(struct ade7758_state *st)
+static int ade7758_initial_setup(struct iio_dev *indio_dev)
{
+ struct ade7758_state *st = iio_priv(indio_dev);
+ struct device *dev = &indio_dev->dev;
int ret;
- struct device *dev = &st->indio_dev->dev;
/* use low spi speed for init */
- st->us->mode = SPI_MODE_3;
+ st->us->mode = SPI_MODE_1;
spi_setup(st->us);
/* Disable IRQ */
@@ -510,7 +535,6 @@
size_t len)
{
struct iio_dev *indio_dev = dev_get_drvdata(dev);
- struct ade7758_state *st = iio_dev_get_devdata(indio_dev);
unsigned long val;
int ret;
u8 reg, t;
@@ -521,14 +545,23 @@
mutex_lock(&indio_dev->mlock);
- t = (26040 / val);
- if (t > 0)
- t >>= 1;
-
- if (t > 1)
- st->us->max_speed_hz = ADE7758_SPI_SLOW;
- else
- st->us->max_speed_hz = ADE7758_SPI_FAST;
+ switch (val) {
+ case 26040:
+ t = 0;
+ break;
+ case 13020:
+ t = 1;
+ break;
+ case 6510:
+ t = 2;
+ break;
+ case 3255:
+ t = 3;
+ break;
+ default:
+ ret = -EINVAL;
+ goto out;
+ }
ret = ade7758_spi_read_reg_8(dev,
ADE7758_WAVMODE,
@@ -549,63 +582,6 @@
return ret ? ret : len;
}
-static ssize_t ade7758_read_waveform_type(struct device *dev,
- struct device_attribute *attr,
- char *buf)
-{
- int ret, len = 0;
- u8 t;
- ret = ade7758_spi_read_reg_8(dev,
- ADE7758_WAVMODE,
- &t);
- if (ret)
- return ret;
-
- t = (t >> 2) & 0x7;
-
- len = sprintf(buf, "%d\n", t);
-
- return len;
-}
-
-static ssize_t ade7758_write_waveform_type(struct device *dev,
- struct device_attribute *attr,
- const char *buf,
- size_t len)
-{
- struct iio_dev *indio_dev = dev_get_drvdata(dev);
- unsigned long val;
- int ret;
- u8 reg;
-
- ret = strict_strtol(buf, 10, &val);
- if (ret)
- return ret;
-
- if (val > 4)
- return -EINVAL;
-
- mutex_lock(&indio_dev->mlock);
-
- ret = ade7758_spi_read_reg_8(dev,
- ADE7758_WAVMODE,
- ®);
- if (ret)
- goto out;
-
- reg &= ~(7 << 2);
- reg |= val << 2;
-
- ret = ade7758_spi_write_reg_8(dev,
- ADE7758_WAVMODE,
- reg);
-
-out:
- mutex_unlock(&indio_dev->mlock);
-
- return ret ? ret : len;
-}
-
static IIO_DEV_ATTR_TEMP_RAW(ade7758_read_8bit);
static IIO_CONST_ATTR(temp_offset, "129 C");
static IIO_CONST_ATTR(temp_scale, "4 C");
@@ -633,42 +609,17 @@
ade7758_read_frequency,
ade7758_write_frequency);
-/**
- * IIO_DEV_ATTR_WAVEFORM_TYPE - set the type of waveform.
- * @_mode: sysfs file mode/permissions
- * @_show: output method for the attribute
- * @_store: input method for the attribute
- **/
-#define IIO_DEV_ATTR_WAVEFORM_TYPE(_mode, _show, _store) \
- IIO_DEVICE_ATTR(waveform_type, _mode, _show, _store, 0)
-
-static IIO_DEV_ATTR_WAVEFORM_TYPE(S_IWUSR | S_IRUGO,
- ade7758_read_waveform_type,
- ade7758_write_waveform_type);
-
static IIO_DEV_ATTR_RESET(ade7758_write_reset);
-static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("26000 13000 65000 33000");
-
-static IIO_CONST_ATTR(name, "ade7758");
-
-static struct attribute *ade7758_event_attributes[] = {
- NULL
-};
-
-static struct attribute_group ade7758_event_attribute_group = {
- .attrs = ade7758_event_attributes,
-};
+static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("26040 13020 6510 3255");
static struct attribute *ade7758_attributes[] = {
&iio_dev_attr_temp_raw.dev_attr.attr,
&iio_const_attr_temp_offset.dev_attr.attr,
&iio_const_attr_temp_scale.dev_attr.attr,
&iio_dev_attr_sampling_frequency.dev_attr.attr,
- &iio_dev_attr_waveform_type.dev_attr.attr,
&iio_const_attr_sampling_frequency_available.dev_attr.attr,
&iio_dev_attr_reset.dev_attr.attr,
- &iio_const_attr_name.dev_attr.attr,
&iio_dev_attr_awatthr.dev_attr.attr,
&iio_dev_attr_bwatthr.dev_attr.attr,
&iio_dev_attr_cwatthr.dev_attr.attr,
@@ -710,24 +661,95 @@
.attrs = ade7758_attributes,
};
+static struct iio_chan_spec ade7758_channels[] = {
+ IIO_CHAN(IIO_IN, 0, 1, 0, "raw", 0, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ AD7758_WT(AD7758_PHASE_A, AD7758_VOLTAGE),
+ 0, IIO_ST('s', 24, 32, 0), 0),
+ IIO_CHAN(IIO_CURRENT, 0, 1, 0, "raw", 0, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ AD7758_WT(AD7758_PHASE_A, AD7758_CURRENT),
+ 1, IIO_ST('s', 24, 32, 0), 0),
+ IIO_CHAN(IIO_POWER, 0, 1, 0, "apparent_raw", 0, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ AD7758_WT(AD7758_PHASE_A, AD7758_APP_PWR),
+ 2, IIO_ST('s', 24, 32, 0), 0),
+ IIO_CHAN(IIO_POWER, 0, 1, 0, "active_raw", 0, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ AD7758_WT(AD7758_PHASE_A, AD7758_ACT_PWR),
+ 3, IIO_ST('s', 24, 32, 0), 0),
+ IIO_CHAN(IIO_POWER, 0, 1, 0, "reactive_raw", 0, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ AD7758_WT(AD7758_PHASE_A, AD7758_REACT_PWR),
+ 4, IIO_ST('s', 24, 32, 0), 0),
+ IIO_CHAN(IIO_IN, 0, 1, 0, "raw", 1, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ AD7758_WT(AD7758_PHASE_B, AD7758_VOLTAGE),
+ 5, IIO_ST('s', 24, 32, 0), 0),
+ IIO_CHAN(IIO_CURRENT, 0, 1, 0, "raw", 1, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ AD7758_WT(AD7758_PHASE_B, AD7758_CURRENT),
+ 6, IIO_ST('s', 24, 32, 0), 0),
+ IIO_CHAN(IIO_POWER, 0, 1, 0, "apparent_raw", 1, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ AD7758_WT(AD7758_PHASE_B, AD7758_APP_PWR),
+ 7, IIO_ST('s', 24, 32, 0), 0),
+ IIO_CHAN(IIO_POWER, 0, 1, 0, "active_raw", 1, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ AD7758_WT(AD7758_PHASE_B, AD7758_ACT_PWR),
+ 8, IIO_ST('s', 24, 32, 0), 0),
+ IIO_CHAN(IIO_POWER, 0, 1, 0, "reactive_raw", 1, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ AD7758_WT(AD7758_PHASE_B, AD7758_REACT_PWR),
+ 9, IIO_ST('s', 24, 32, 0), 0),
+ IIO_CHAN(IIO_IN, 0, 1, 0, "raw", 2, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ AD7758_WT(AD7758_PHASE_C, AD7758_VOLTAGE),
+ 10, IIO_ST('s', 24, 32, 0), 0),
+ IIO_CHAN(IIO_CURRENT, 0, 1, 0, "raw", 2, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ AD7758_WT(AD7758_PHASE_C, AD7758_CURRENT),
+ 11, IIO_ST('s', 24, 32, 0), 0),
+ IIO_CHAN(IIO_POWER, 0, 1, 0, "apparent_raw", 2, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ AD7758_WT(AD7758_PHASE_C, AD7758_APP_PWR),
+ 12, IIO_ST('s', 24, 32, 0), 0),
+ IIO_CHAN(IIO_POWER, 0, 1, 0, "active_raw", 2, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ AD7758_WT(AD7758_PHASE_C, AD7758_ACT_PWR),
+ 13, IIO_ST('s', 24, 32, 0), 0),
+ IIO_CHAN(IIO_POWER, 0, 1, 0, "reactive_raw", 2, 0,
+ (1 << IIO_CHAN_INFO_SCALE_SHARED),
+ AD7758_WT(AD7758_PHASE_C, AD7758_REACT_PWR),
+ 14, IIO_ST('s', 24, 32, 0), 0),
+ IIO_CHAN_SOFT_TIMESTAMP(15),
+};
+static const struct iio_info ade7758_info = {
+ .attrs = &ade7758_attribute_group,
+ .driver_module = THIS_MODULE,
+};
static int __devinit ade7758_probe(struct spi_device *spi)
{
- int ret, regdone = 0;
- struct ade7758_state *st = kzalloc(sizeof *st, GFP_KERNEL);
- if (!st) {
- ret = -ENOMEM;
+ int i, ret, regdone = 0;
+ struct ade7758_state *st;
+ struct iio_dev *indio_dev = iio_allocate_device(sizeof(*st));
+
+ if (indio_dev == NULL) {
+ ret = -ENOMEM;
goto error_ret;
}
+
+ st = iio_priv(indio_dev);
/* this is only used for removal purposes */
- spi_set_drvdata(spi, st);
+ spi_set_drvdata(spi, indio_dev);
/* Allocate the comms buffers */
st->rx = kzalloc(sizeof(*st->rx)*ADE7758_MAX_RX, GFP_KERNEL);
if (st->rx == NULL) {
ret = -ENOMEM;
- goto error_free_st;
+ goto error_free_dev;
}
st->tx = kzalloc(sizeof(*st->tx)*ADE7758_MAX_TX, GFP_KERNEL);
if (st->tx == NULL) {
@@ -735,111 +757,96 @@
goto error_free_rx;
}
st->us = spi;
+ st->ade7758_ring_channels = &ade7758_channels[0];
mutex_init(&st->buf_lock);
- /* setup the industrialio driver allocated elements */
- st->indio_dev = iio_allocate_device();
- if (st->indio_dev == NULL) {
- ret = -ENOMEM;
- goto error_free_tx;
- }
- st->indio_dev->dev.parent = &spi->dev;
- st->indio_dev->num_interrupt_lines = 1;
- st->indio_dev->event_attrs = &ade7758_event_attribute_group;
- st->indio_dev->attrs = &ade7758_attribute_group;
- st->indio_dev->dev_data = (void *)(st);
- st->indio_dev->driver_module = THIS_MODULE;
- st->indio_dev->modes = INDIO_DIRECT_MODE;
+ indio_dev->name = spi->dev.driver->name;
+ indio_dev->dev.parent = &spi->dev;
+ indio_dev->info = &ade7758_info;
+ indio_dev->modes = INDIO_DIRECT_MODE;
- ret = ade7758_configure_ring(st->indio_dev);
+ for (i = 0; i < AD7758_NUM_WAVESRC; i++)
+ st->available_scan_masks[i] = 1 << i;
+
+ indio_dev->available_scan_masks = st->available_scan_masks;
+
+ ret = ade7758_configure_ring(indio_dev);
if (ret)
- goto error_free_dev;
+ goto error_free_tx;
- ret = iio_device_register(st->indio_dev);
+ ret = iio_device_register(indio_dev);
if (ret)
goto error_unreg_ring_funcs;
regdone = 1;
- ret = ade7758_initialize_ring(st->indio_dev->ring);
+ ret = iio_ring_buffer_register_ex(indio_dev->ring, 0,
+ &ade7758_channels[0],
+ ARRAY_SIZE(ade7758_channels));
if (ret) {
- printk(KERN_ERR "failed to initialize the ring\n");
+ dev_err(&spi->dev, "failed to initialize the ring\n");
goto error_unreg_ring_funcs;
}
- if (spi->irq) {
- ret = iio_register_interrupt_line(spi->irq,
- st->indio_dev,
- 0,
- IRQF_TRIGGER_FALLING,
- "ade7758");
- if (ret)
- goto error_uninitialize_ring;
+ /* Get the device into a sane initial state */
+ ret = ade7758_initial_setup(indio_dev);
+ if (ret)
+ goto error_uninitialize_ring;
- ret = ade7758_probe_trigger(st->indio_dev);
+ if (spi->irq) {
+ ret = ade7758_probe_trigger(indio_dev);
if (ret)
- goto error_unregister_line;
+ goto error_remove_trigger;
}
- /* Get the device into a sane initial state */
- ret = ade7758_initial_setup(st);
- if (ret)
- goto error_remove_trigger;
return 0;
error_remove_trigger:
- if (st->indio_dev->modes & INDIO_RING_TRIGGERED)
- ade7758_remove_trigger(st->indio_dev);
-error_unregister_line:
- if (st->indio_dev->modes & INDIO_RING_TRIGGERED)
- iio_unregister_interrupt_line(st->indio_dev, 0);
+ if (indio_dev->modes & INDIO_RING_TRIGGERED)
+ ade7758_remove_trigger(indio_dev);
error_uninitialize_ring:
- ade7758_uninitialize_ring(st->indio_dev->ring);
+ ade7758_uninitialize_ring(indio_dev->ring);
error_unreg_ring_funcs:
- ade7758_unconfigure_ring(st->indio_dev);
-error_free_dev:
- if (regdone)
- iio_device_unregister(st->indio_dev);
- else
- iio_free_device(st->indio_dev);
+ ade7758_unconfigure_ring(indio_dev);
error_free_tx:
kfree(st->tx);
error_free_rx:
kfree(st->rx);
-error_free_st:
- kfree(st);
+error_free_dev:
+ if (regdone)
+ iio_device_unregister(indio_dev);
+ else
+ iio_free_device(indio_dev);
error_ret:
return ret;
}
static int ade7758_remove(struct spi_device *spi)
{
+ struct iio_dev *indio_dev = spi_get_drvdata(spi);
+ struct ade7758_state *st = iio_priv(indio_dev);
int ret;
- struct ade7758_state *st = spi_get_drvdata(spi);
- struct iio_dev *indio_dev = st->indio_dev;
- ret = ade7758_stop_device(&(indio_dev->dev));
+ ret = ade7758_stop_device(&indio_dev->dev);
if (ret)
goto err_ret;
- flush_scheduled_work();
-
ade7758_remove_trigger(indio_dev);
- if (spi->irq && gpio_is_valid(irq_to_gpio(spi->irq)) > 0)
- iio_unregister_interrupt_line(indio_dev, 0);
-
ade7758_uninitialize_ring(indio_dev->ring);
- iio_device_unregister(indio_dev);
ade7758_unconfigure_ring(indio_dev);
kfree(st->tx);
kfree(st->rx);
- kfree(st);
+ iio_device_unregister(indio_dev);
return 0;
-
err_ret:
return ret;
}
+static const struct spi_device_id ade7758_id[] = {
+ {"ade7758", 0},
+ {}
+};
+
static struct spi_driver ade7758_driver = {
.driver = {
.name = "ade7758",
@@ -847,6 +854,7 @@
},
.probe = ade7758_probe,
.remove = __devexit_p(ade7758_remove),
+ .id_table = ade7758_id,
};
static __init int ade7758_init(void)
diff --git a/drivers/staging/iio/meter/ade7758_ring.c b/drivers/staging/iio/meter/ade7758_ring.c
index 274b4a0..b89b7f8 100644
--- a/drivers/staging/iio/meter/ade7758_ring.c
+++ b/drivers/staging/iio/meter/ade7758_ring.c
@@ -1,3 +1,10 @@
+/*
+ * ADE7758 Poly Phase Multifunction Energy Metering IC driver
+ *
+ * Copyright 2010-2011 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2.
+ */
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/gpio.h>
@@ -9,6 +16,7 @@
#include <linux/slab.h>
#include <linux/sysfs.h>
#include <linux/list.h>
+#include <asm/unaligned.h>
#include "../iio.h"
#include "../sysfs.h"
@@ -18,182 +26,188 @@
#include "ade7758.h"
/**
- * combine_8_to_32() utility function to munge to u8s into u32
- **/
-static inline u32 combine_8_to_32(u8 lower, u8 mid, u8 upper)
-{
- u32 _lower = lower;
- u32 _mid = mid;
- u32 _upper = upper;
-
- return _lower | (_mid << 8) | (_upper << 16);
-}
-
-static IIO_SCAN_EL_C(wform, ADE7758_SCAN_WFORM, ADE7758_WFORM, NULL);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(wform, s, 24, 32);
-static IIO_SCAN_EL_TIMESTAMP(1);
-static IIO_CONST_ATTR_SCAN_EL_TYPE(timestamp, s, 64, 64);
-
-static struct attribute *ade7758_scan_el_attrs[] = {
- &iio_scan_el_wform.dev_attr.attr,
- &iio_const_attr_wform_index.dev_attr.attr,
- &iio_const_attr_wform_type.dev_attr.attr,
- &iio_scan_el_timestamp.dev_attr.attr,
- &iio_const_attr_timestamp_index.dev_attr.attr,
- &iio_const_attr_timestamp_type.dev_attr.attr,
- NULL,
-};
-
-static struct attribute_group ade7758_scan_el_group = {
- .attrs = ade7758_scan_el_attrs,
- .name = "scan_elements",
-};
-
-/**
- * ade7758_poll_func_th() top half interrupt handler called by trigger
- * @private_data: iio_dev
- **/
-static void ade7758_poll_func_th(struct iio_dev *indio_dev, s64 time)
-{
- struct ade7758_state *st = iio_dev_get_devdata(indio_dev);
- st->last_timestamp = time;
- schedule_work(&st->work_trigger_to_ring);
- /* Indicate that this interrupt is being handled */
-
- /* Technically this is trigger related, but without this
- * handler running there is currently no way for the interrupt
- * to clear.
- */
-}
-
-/**
- * ade7758_spi_read_burst() - read all data registers
+ * ade7758_spi_read_burst() - read data registers
* @dev: device associated with child of actual device (iio_dev or iio_trig)
- * @rx: somewhere to pass back the value read (min size is 24 bytes)
**/
-static int ade7758_spi_read_burst(struct device *dev, u8 *rx)
+static int ade7758_spi_read_burst(struct device *dev)
{
- struct spi_message msg;
struct iio_dev *indio_dev = dev_get_drvdata(dev);
- struct ade7758_state *st = iio_dev_get_devdata(indio_dev);
+ struct ade7758_state *st = iio_priv(indio_dev);
int ret;
- struct spi_transfer xfers[] = {
- {
- .tx_buf = st->tx,
- .rx_buf = rx,
- .bits_per_word = 8,
- .len = 4,
- }, {
- .tx_buf = st->tx + 4,
- .rx_buf = rx,
- .bits_per_word = 8,
- .len = 4,
- },
- };
-
- mutex_lock(&st->buf_lock);
- st->tx[0] = ADE7758_READ_REG(ADE7758_RSTATUS);
- st->tx[1] = 0;
- st->tx[2] = 0;
- st->tx[3] = 0;
- st->tx[4] = ADE7758_READ_REG(ADE7758_WFORM);
- st->tx[5] = 0;
- st->tx[6] = 0;
- st->tx[7] = 0;
-
- spi_message_init(&msg);
- spi_message_add_tail(&xfers[0], &msg);
- spi_message_add_tail(&xfers[1], &msg);
- ret = spi_sync(st->us, &msg);
+ ret = spi_sync(st->us, &st->ring_msg);
if (ret)
dev_err(&st->us->dev, "problem when reading WFORM value\n");
- mutex_unlock(&st->buf_lock);
+ return ret;
+}
+static int ade7758_write_waveform_type(struct device *dev, unsigned type)
+{
+ int ret;
+ u8 reg;
+
+ ret = ade7758_spi_read_reg_8(dev,
+ ADE7758_WAVMODE,
+ ®);
+ if (ret)
+ goto out;
+
+ reg &= ~0x1F;
+ reg |= type & 0x1F;
+
+ ret = ade7758_spi_write_reg_8(dev,
+ ADE7758_WAVMODE,
+ reg);
+out:
return ret;
}
/* Whilst this makes a lot of calls to iio_sw_ring functions - it is to device
* specific to be rolled into the core.
*/
-static void ade7758_trigger_bh_to_ring(struct work_struct *work_s)
+static irqreturn_t ade7758_trigger_handler(int irq, void *p)
{
- struct ade7758_state *st
- = container_of(work_s, struct ade7758_state,
- work_trigger_to_ring);
- struct iio_ring_buffer *ring = st->indio_dev->ring;
-
- int i = 0;
- s32 *data;
- size_t datasize = ring->access.get_bytes_per_datum(ring);
-
- data = kmalloc(datasize, GFP_KERNEL);
- if (data == NULL) {
- dev_err(&st->us->dev, "memory alloc failed in ring bh");
- return;
- }
+ struct iio_poll_func *pf = p;
+ struct iio_dev *indio_dev = pf->private_data;
+ struct iio_ring_buffer *ring = indio_dev->ring;
+ struct ade7758_state *st = iio_priv(indio_dev);
+ s64 dat64[2];
+ u32 *dat32 = (u32 *)dat64;
if (ring->scan_count)
- if (ade7758_spi_read_burst(&st->indio_dev->dev, st->rx) >= 0)
- for (; i < ring->scan_count; i++)
- data[i] = combine_8_to_32(st->rx[i*2+2],
- st->rx[i*2+1],
- st->rx[i*2]);
+ if (ade7758_spi_read_burst(&indio_dev->dev) >= 0)
+ *dat32 = get_unaligned_be32(&st->rx_buf[5]) & 0xFFFFFF;
/* Guaranteed to be aligned with 8 byte boundary */
if (ring->scan_timestamp)
- *((s64 *)
- (((u32)data + 4 * ring->scan_count + 4) & ~0x7)) =
- st->last_timestamp;
+ dat64[1] = pf->timestamp;
- ring->access.store_to(ring,
- (u8 *)data,
- st->last_timestamp);
+ ring->access->store_to(ring, (u8 *)dat64, pf->timestamp);
- iio_trigger_notify_done(st->indio_dev->trig);
- kfree(data);
+ iio_trigger_notify_done(indio_dev->trig);
- return;
+ return IRQ_HANDLED;
}
+/**
+ * ade7758_ring_preenable() setup the parameters of the ring before enabling
+ *
+ * The complex nature of the setting of the nuber of bytes per datum is due
+ * to this driver currently ensuring that the timestamp is stored at an 8
+ * byte boundary.
+ **/
+static int ade7758_ring_preenable(struct iio_dev *indio_dev)
+{
+ struct ade7758_state *st = iio_priv(indio_dev);
+ struct iio_ring_buffer *ring = indio_dev->ring;
+ size_t d_size;
+ unsigned channel;
+
+ if (!ring->scan_count)
+ return -EINVAL;
+
+ channel = __ffs(ring->scan_mask);
+
+ d_size = st->ade7758_ring_channels[channel].scan_type.storagebits / 8;
+
+ if (ring->scan_timestamp) {
+ d_size += sizeof(s64);
+
+ if (d_size % sizeof(s64))
+ d_size += sizeof(s64) - (d_size % sizeof(s64));
+ }
+
+ if (indio_dev->ring->access->set_bytes_per_datum)
+ indio_dev->ring->access->set_bytes_per_datum(indio_dev->ring,
+ d_size);
+
+ ade7758_write_waveform_type(&indio_dev->dev,
+ st->ade7758_ring_channels[channel].address);
+
+ return 0;
+}
+
+static const struct iio_ring_setup_ops ade7758_ring_setup_ops = {
+ .preenable = &ade7758_ring_preenable,
+ .postenable = &iio_triggered_ring_postenable,
+ .predisable = &iio_triggered_ring_predisable,
+};
+
void ade7758_unconfigure_ring(struct iio_dev *indio_dev)
{
- kfree(indio_dev->pollfunc);
+ /* ensure that the trigger has been detached */
+ if (indio_dev->trig) {
+ iio_put_trigger(indio_dev->trig);
+ iio_trigger_dettach_poll_func(indio_dev->trig,
+ indio_dev->pollfunc);
+ }
+ iio_dealloc_pollfunc(indio_dev->pollfunc);
iio_sw_rb_free(indio_dev->ring);
}
int ade7758_configure_ring(struct iio_dev *indio_dev)
{
+ struct ade7758_state *st = iio_priv(indio_dev);
int ret = 0;
- struct ade7758_state *st = indio_dev->dev_data;
- struct iio_ring_buffer *ring;
- INIT_WORK(&st->work_trigger_to_ring, ade7758_trigger_bh_to_ring);
- ring = iio_sw_rb_allocate(indio_dev);
- if (!ring) {
+ indio_dev->ring = iio_sw_rb_allocate(indio_dev);
+ if (!indio_dev->ring) {
ret = -ENOMEM;
return ret;
}
- indio_dev->ring = ring;
+
/* Effectively select the ring buffer implementation */
- iio_ring_sw_register_funcs(&ring->access);
- ring->bpe = 4;
- ring->scan_el_attrs = &ade7758_scan_el_group;
- ring->scan_timestamp = true;
- ring->preenable = &iio_sw_ring_preenable;
- ring->postenable = &iio_triggered_ring_postenable;
- ring->predisable = &iio_triggered_ring_predisable;
- ring->owner = THIS_MODULE;
+ indio_dev->ring->access = &ring_sw_access_funcs;
+ indio_dev->ring->setup_ops = &ade7758_ring_setup_ops;
+ indio_dev->ring->owner = THIS_MODULE;
- /* Set default scan mode */
- iio_scan_mask_set(ring, iio_scan_el_wform.number);
-
- ret = iio_alloc_pollfunc(indio_dev, NULL, &ade7758_poll_func_th);
- if (ret)
+ indio_dev->pollfunc = iio_alloc_pollfunc(&iio_pollfunc_store_time,
+ &ade7758_trigger_handler,
+ 0,
+ indio_dev,
+ "ade7759_consumer%d",
+ indio_dev->id);
+ if (indio_dev->pollfunc == NULL) {
+ ret = -ENOMEM;
goto error_iio_sw_rb_free;
+ }
indio_dev->modes |= INDIO_RING_TRIGGERED;
+
+ st->tx_buf[0] = ADE7758_READ_REG(ADE7758_RSTATUS);
+ st->tx_buf[1] = 0;
+ st->tx_buf[2] = 0;
+ st->tx_buf[3] = 0;
+ st->tx_buf[4] = ADE7758_READ_REG(ADE7758_WFORM);
+ st->tx_buf[5] = 0;
+ st->tx_buf[6] = 0;
+ st->tx_buf[7] = 0;
+
+ /* build spi ring message */
+ st->ring_xfer[0].tx_buf = &st->tx_buf[0];
+ st->ring_xfer[0].len = 1;
+ st->ring_xfer[0].bits_per_word = 8;
+ st->ring_xfer[0].delay_usecs = 4;
+ st->ring_xfer[1].rx_buf = &st->rx_buf[1];
+ st->ring_xfer[1].len = 3;
+ st->ring_xfer[1].bits_per_word = 8;
+ st->ring_xfer[1].cs_change = 1;
+
+ st->ring_xfer[2].tx_buf = &st->tx_buf[4];
+ st->ring_xfer[2].len = 1;
+ st->ring_xfer[2].bits_per_word = 8;
+ st->ring_xfer[2].delay_usecs = 1;
+ st->ring_xfer[3].rx_buf = &st->rx_buf[5];
+ st->ring_xfer[3].len = 3;
+ st->ring_xfer[3].bits_per_word = 8;
+
+ spi_message_init(&st->ring_msg);
+ spi_message_add_tail(&st->ring_xfer[0], &st->ring_msg);
+ spi_message_add_tail(&st->ring_xfer[1], &st->ring_msg);
+ spi_message_add_tail(&st->ring_xfer[2], &st->ring_msg);
+ spi_message_add_tail(&st->ring_xfer[3], &st->ring_msg);
+
return 0;
error_iio_sw_rb_free:
@@ -201,11 +215,6 @@
return ret;
}
-int ade7758_initialize_ring(struct iio_ring_buffer *ring)
-{
- return iio_ring_buffer_register(ring, 0);
-}
-
void ade7758_uninitialize_ring(struct iio_ring_buffer *ring)
{
iio_ring_buffer_unregister(ring);
diff --git a/drivers/staging/iio/meter/ade7758_trigger.c b/drivers/staging/iio/meter/ade7758_trigger.c
index 60abca0..a5c3248 100644
--- a/drivers/staging/iio/meter/ade7758_trigger.c
+++ b/drivers/staging/iio/meter/ade7758_trigger.c
@@ -1,3 +1,11 @@
+/*
+ * ADE7758 Poly Phase Multifunction Energy Metering IC driver
+ *
+ * Copyright 2010-2011 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2.
+ */
+
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/mutex.h>
@@ -15,56 +23,24 @@
/**
* ade7758_data_rdy_trig_poll() the event handler for the data rdy trig
**/
-static int ade7758_data_rdy_trig_poll(struct iio_dev *dev_info,
- int index,
- s64 timestamp,
- int no_test)
+static irqreturn_t ade7758_data_rdy_trig_poll(int irq, void *private)
{
- struct ade7758_state *st = iio_dev_get_devdata(dev_info);
- struct iio_trigger *trig = st->trig;
-
- iio_trigger_poll(trig, timestamp);
+ disable_irq_nosync(irq);
+ iio_trigger_poll(private, iio_get_time_ns());
return IRQ_HANDLED;
}
-IIO_EVENT_SH(data_rdy_trig, &ade7758_data_rdy_trig_poll);
-
-static DEVICE_ATTR(name, S_IRUGO, iio_trigger_read_name, NULL);
-
-static struct attribute *ade7758_trigger_attrs[] = {
- &dev_attr_name.attr,
- NULL,
-};
-
-static const struct attribute_group ade7758_trigger_attr_group = {
- .attrs = ade7758_trigger_attrs,
-};
-
/**
* ade7758_data_rdy_trigger_set_state() set datardy interrupt state
**/
static int ade7758_data_rdy_trigger_set_state(struct iio_trigger *trig,
bool state)
{
- struct ade7758_state *st = trig->private_data;
- struct iio_dev *indio_dev = st->indio_dev;
- int ret = 0;
+ struct iio_dev *indio_dev = trig->private_data;
dev_dbg(&indio_dev->dev, "%s (%d)\n", __func__, state);
- ret = ade7758_set_irq(&st->indio_dev->dev, state);
- if (state == false) {
- iio_remove_event_from_list(&iio_event_data_rdy_trig,
- &indio_dev->interrupts[0]
- ->ev_list);
- /* possible quirk with handler currently worked around
- by ensuring the work queue is empty */
- flush_scheduled_work();
- } else {
- iio_add_event_to_list(&iio_event_data_rdy_trig,
- &indio_dev->interrupts[0]->ev_list);
- }
- return ret;
+ return ade7758_set_irq(&indio_dev->dev, state);
}
/**
@@ -73,7 +49,9 @@
**/
static int ade7758_trig_try_reen(struct iio_trigger *trig)
{
- struct ade7758_state *st = trig->private_data;
+ struct iio_dev *indio_dev = trig->private_data;
+ struct ade7758_state *st = iio_priv(indio_dev);
+
enable_irq(st->us->irq);
/* irq reenabled so success! */
return 0;
@@ -81,45 +59,52 @@
int ade7758_probe_trigger(struct iio_dev *indio_dev)
{
+ struct ade7758_state *st = iio_priv(indio_dev);
int ret;
- struct ade7758_state *st = indio_dev->dev_data;
- st->trig = iio_allocate_trigger();
- st->trig->name = kasprintf(GFP_KERNEL,
- "ade7758-dev%d",
- indio_dev->id);
- if (!st->trig->name) {
+ st->trig = iio_allocate_trigger("%s-dev%d",
+ spi_get_device_id(st->us)->name,
+ indio_dev->id);
+ if (st->trig == NULL) {
ret = -ENOMEM;
- goto error_free_trig;
+ goto error_ret;
}
+
+ ret = request_irq(st->us->irq,
+ ade7758_data_rdy_trig_poll,
+ IRQF_TRIGGER_LOW,
+ spi_get_device_id(st->us)->name,
+ st->trig);
+ if (ret)
+ goto error_free_trig;
+
st->trig->dev.parent = &st->us->dev;
st->trig->owner = THIS_MODULE;
- st->trig->private_data = st;
+ st->trig->private_data = indio_dev;
st->trig->set_trigger_state = &ade7758_data_rdy_trigger_set_state;
st->trig->try_reenable = &ade7758_trig_try_reen;
- st->trig->control_attrs = &ade7758_trigger_attr_group;
ret = iio_trigger_register(st->trig);
/* select default trigger */
indio_dev->trig = st->trig;
if (ret)
- goto error_free_trig_name;
+ goto error_free_irq;
return 0;
-error_free_trig_name:
- kfree(st->trig->name);
+error_free_irq:
+ free_irq(st->us->irq, st->trig);
error_free_trig:
iio_free_trigger(st->trig);
-
+error_ret:
return ret;
}
void ade7758_remove_trigger(struct iio_dev *indio_dev)
{
- struct ade7758_state *state = indio_dev->dev_data;
+ struct ade7758_state *st = iio_priv(indio_dev);
- iio_trigger_unregister(state->trig);
- kfree(state->trig->name);
- iio_free_trigger(state->trig);
+ iio_trigger_unregister(st->trig);
+ free_irq(st->us->irq, st->trig);
+ iio_free_trigger(st->trig);
}
diff --git a/drivers/staging/iio/meter/ade7759.c b/drivers/staging/iio/meter/ade7759.c
index a9d3203..730f6d9 100644
--- a/drivers/staging/iio/meter/ade7759.c
+++ b/drivers/staging/iio/meter/ade7759.c
@@ -422,8 +422,6 @@
static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("27900 14000 7000 3500");
-static IIO_CONST_ATTR(name, "ade7759");
-
static struct attribute *ade7759_attributes[] = {
&iio_dev_attr_temp_raw.dev_attr.attr,
&iio_const_attr_temp_offset.dev_attr.attr,
@@ -431,7 +429,6 @@
&iio_dev_attr_sampling_frequency.dev_attr.attr,
&iio_const_attr_sampling_frequency_available.dev_attr.attr,
&iio_dev_attr_reset.dev_attr.attr,
- &iio_const_attr_name.dev_attr.attr,
&iio_dev_attr_phcal.dev_attr.attr,
&iio_dev_attr_cfden.dev_attr.attr,
&iio_dev_attr_aenergy.dev_attr.attr,
@@ -453,6 +450,11 @@
.attrs = ade7759_attributes,
};
+static const struct iio_info ade7759_info = {
+ .attrs = &ade7759_attribute_group,
+ .driver_module = THIS_MODULE,
+};
+
static int __devinit ade7759_probe(struct spi_device *spi)
{
int ret;
@@ -478,18 +480,17 @@
st->us = spi;
mutex_init(&st->buf_lock);
/* setup the industrialio driver allocated elements */
- st->indio_dev = iio_allocate_device();
+ st->indio_dev = iio_allocate_device(0);
if (st->indio_dev == NULL) {
ret = -ENOMEM;
goto error_free_tx;
}
+ st->indio_dev->name = spi->dev.driver->name;
st->indio_dev->dev.parent = &spi->dev;
- st->indio_dev->num_interrupt_lines = 1;
- st->indio_dev->attrs = &ade7759_attribute_group;
+ st->indio_dev->info = &ade7759_info;
st->indio_dev->dev_data = (void *)(st);
- st->indio_dev->driver_module = THIS_MODULE;
st->indio_dev->modes = INDIO_DIRECT_MODE;
ret = iio_device_register(st->indio_dev);
diff --git a/drivers/staging/iio/meter/ade7854.c b/drivers/staging/iio/meter/ade7854.c
index 866e585..44cd3ec 100644
--- a/drivers/staging/iio/meter/ade7854.c
+++ b/drivers/staging/iio/meter/ade7854.c
@@ -551,6 +551,11 @@
.attrs = ade7854_attributes,
};
+static const struct iio_info ade7854_info = {
+ .attrs = &ade7854_attribute_group,
+ .driver_module = THIS_MODULE,
+};
+
int ade7854_probe(struct ade7854_state *st, struct device *dev)
{
int ret;
@@ -568,16 +573,15 @@
}
mutex_init(&st->buf_lock);
/* setup the industrialio driver allocated elements */
- st->indio_dev = iio_allocate_device();
+ st->indio_dev = iio_allocate_device(0);
if (st->indio_dev == NULL) {
ret = -ENOMEM;
goto error_free_tx;
}
st->indio_dev->dev.parent = dev;
- st->indio_dev->attrs = &ade7854_attribute_group;
+ st->indio_dev->info = &ade7854_info;
st->indio_dev->dev_data = (void *)(st);
- st->indio_dev->driver_module = THIS_MODULE;
st->indio_dev->modes = INDIO_DIRECT_MODE;
ret = iio_device_register(st->indio_dev);
diff --git a/drivers/staging/iio/resolver/ad2s120x.c b/drivers/staging/iio/resolver/ad2s120x.c
index 8f497a2..f83e142 100644
--- a/drivers/staging/iio/resolver/ad2s120x.c
+++ b/drivers/staging/iio/resolver/ad2s120x.c
@@ -209,10 +209,14 @@
};
static const struct attribute_group ad2s120x_attribute_group = {
- .name = DRV_NAME,
.attrs = ad2s120x_attributes,
};
+static const struct iio_info ad2s120x_info = {
+ .attrs = &ad2s120x_attribute_group,
+ .driver_module = THIS_MODULE,
+};
+
static int __devinit ad2s120x_probe(struct spi_device *spi)
{
struct ad2s120x_state *st;
@@ -240,18 +244,15 @@
st->sample = pins[0];
st->rdvel = pins[1];
- st->idev = iio_allocate_device();
+ st->idev = iio_allocate_device(0);
if (st->idev == NULL) {
ret = -ENOMEM;
goto error_free_st;
}
st->idev->dev.parent = &spi->dev;
- st->idev->num_interrupt_lines = 0;
- st->idev->event_attrs = NULL;
- st->idev->attrs = &ad2s120x_attribute_group;
+ st->idev->info = &ad2s120x_info;
st->idev->dev_data = (void *)(st);
- st->idev->driver_module = THIS_MODULE;
st->idev->modes = INDIO_DIRECT_MODE;
ret = iio_device_register(st->idev);
diff --git a/drivers/staging/iio/resolver/ad2s1210.c b/drivers/staging/iio/resolver/ad2s1210.c
index c12f64c..09f4fcf 100644
--- a/drivers/staging/iio/resolver/ad2s1210.c
+++ b/drivers/staging/iio/resolver/ad2s1210.c
@@ -755,6 +755,11 @@
return ret;
}
+static const struct iio_info ad2s1210_info = {
+ .attrs = &ad2s1210_attribute_group,
+ .driver_module = THIS_MODULE,
+};
+
static int __devinit ad2s1210_probe(struct spi_device *spi)
{
struct ad2s1210_state *st;
@@ -800,18 +805,15 @@
st->res0 = pins[3];
st->res1 = pins[4];
- st->idev = iio_allocate_device();
+ st->idev = iio_allocate_device(0);
if (st->idev == NULL) {
ret = -ENOMEM;
goto error_free_st;
}
st->idev->dev.parent = &spi->dev;
- st->idev->num_interrupt_lines = 0;
- st->idev->event_attrs = NULL;
- st->idev->attrs = &ad2s1210_attribute_group;
+ st->idev->info = &ad2s1210_info;
st->idev->dev_data = (void *)(st);
- st->idev->driver_module = THIS_MODULE;
st->idev->modes = INDIO_DIRECT_MODE;
ret = iio_device_register(st->idev);
diff --git a/drivers/staging/iio/resolver/ad2s90.c b/drivers/staging/iio/resolver/ad2s90.c
index 4143535..9b72a95 100644
--- a/drivers/staging/iio/resolver/ad2s90.c
+++ b/drivers/staging/iio/resolver/ad2s90.c
@@ -75,6 +75,11 @@
.attrs = ad2s90_attributes,
};
+static const struct iio_info ad2s90_info = {
+ .attrs = &ad2s90_attribute_group,
+ .driver_module = THIS_MODULE,
+};
+
static int __devinit ad2s90_probe(struct spi_device *spi)
{
struct ad2s90_state *st;
@@ -90,18 +95,15 @@
mutex_init(&st->lock);
st->sdev = spi;
- st->idev = iio_allocate_device();
+ st->idev = iio_allocate_device(0);
if (st->idev == NULL) {
ret = -ENOMEM;
goto error_free_st;
}
st->idev->dev.parent = &spi->dev;
- st->idev->num_interrupt_lines = 0;
- st->idev->event_attrs = NULL;
- st->idev->attrs = &ad2s90_attribute_group;
+ st->idev->info = &ad2s90_info;
st->idev->dev_data = (void *)(st);
- st->idev->driver_module = THIS_MODULE;
st->idev->modes = INDIO_DIRECT_MODE;
ret = iio_device_register(st->idev);
diff --git a/drivers/staging/iio/ring_generic.h b/drivers/staging/iio/ring_generic.h
index 32948e5..3f26f71 100644
--- a/drivers/staging/iio/ring_generic.h
+++ b/drivers/staging/iio/ring_generic.h
@@ -16,35 +16,12 @@
struct iio_ring_buffer;
/**
- * iio_push_ring_event() - ring buffer specific push to event chrdev
- * @ring_buf: ring buffer that is the event source
- * @event_code: event indentification code
- * @timestamp: time of event
- **/
-int iio_push_ring_event(struct iio_ring_buffer *ring_buf,
- int event_code,
- s64 timestamp);
-/**
- * iio_push_or_escallate_ring_event() - escalate or add as appropriate
- * @ring_buf: ring buffer that is the event source
- * @event_code: event indentification code
- * @timestamp: time of event
- *
- * Typical usecase is to escalate a 50% ring full to 75% full if no one has yet
- * read the first event. Clearly the 50% full is no longer of interest in
- * typical use case.
- **/
-int iio_push_or_escallate_ring_event(struct iio_ring_buffer *ring_buf,
- int event_code,
- s64 timestamp);
-
-/**
* struct iio_ring_access_funcs - access functions for ring buffers.
* @mark_in_use: reference counting, typically to prevent module removal
* @unmark_in_use: reduce reference count when no longer using ring buffer
* @store_to: actually store stuff to the ring buffer
* @read_last: get the last element stored
- * @rip_lots: try to get a specified number of elements (must exist)
+ * @read_first_n: try to get a specified number of elements (must exist)
* @mark_param_change: notify ring that some relevant parameter has changed
* Often this means the underlying storage may need to
* change.
@@ -71,10 +48,9 @@
int (*store_to)(struct iio_ring_buffer *ring, u8 *data, s64 timestamp);
int (*read_last)(struct iio_ring_buffer *ring, u8 *data);
- int (*rip_lots)(struct iio_ring_buffer *ring,
- size_t count,
- char __user *buf,
- int *dead_offset);
+ int (*read_first_n)(struct iio_ring_buffer *ring,
+ size_t n,
+ char __user *buf);
int (*mark_param_change)(struct iio_ring_buffer *ring);
int (*request_update)(struct iio_ring_buffer *ring);
@@ -88,58 +64,52 @@
int (*enable)(struct iio_ring_buffer *ring);
};
+struct iio_ring_setup_ops {
+ int (*preenable)(struct iio_dev *);
+ int (*postenable)(struct iio_dev *);
+ int (*predisable)(struct iio_dev *);
+ int (*postdisable)(struct iio_dev *);
+};
+
/**
* struct iio_ring_buffer - general ring buffer structure
* @dev: ring buffer device struct
- * @access_dev: system device struct for the chrdev
* @indio_dev: industrial I/O device structure
* @owner: module that owns the ring buffer (for ref counting)
- * @id: unique id number
- * @access_id: device id number
* @length: [DEVICE] number of datums in ring
* @bytes_per_datum: [DEVICE] size of individual datum including timestamp
* @bpe: [DEVICE] size of individual channel value
- * @loopcount: [INTERN] number of times the ring has looped
* @scan_el_attrs: [DRIVER] control of scan elements if that scan mode
* control method is used
* @scan_count: [INTERN] the number of elements in the current scan mode
* @scan_mask: [INTERN] bitmask used in masking scan mode elements
* @scan_timestamp: [INTERN] does the scan mode include a timestamp
* @access_handler: [INTERN] chrdev access handling
- * @ev_int: [INTERN] chrdev interface for the event chrdev
- * @shared_ev_pointer: [INTERN] the shared event pointer to allow escalation of
- * events
* @access: [DRIVER] ring access functions associated with the
* implementation.
* @preenable: [DRIVER] function to run prior to marking ring enabled
* @postenable: [DRIVER] function to run after marking ring enabled
* @predisable: [DRIVER] function to run prior to marking ring disabled
* @postdisable: [DRIVER] function to run after marking ring disabled
- **/
+ **/
struct iio_ring_buffer {
- struct device dev;
- struct device access_dev;
- struct iio_dev *indio_dev;
- struct module *owner;
- int id;
- int access_id;
- int length;
- int bytes_per_datum;
- int bpe;
- int loopcount;
- struct attribute_group *scan_el_attrs;
- int scan_count;
- u32 scan_mask;
- bool scan_timestamp;
- struct iio_handler access_handler;
- struct iio_event_interface ev_int;
- struct iio_shared_ev_pointer shared_ev_pointer;
- struct iio_ring_access_funcs access;
- int (*preenable)(struct iio_dev *);
- int (*postenable)(struct iio_dev *);
- int (*predisable)(struct iio_dev *);
- int (*postdisable)(struct iio_dev *);
+ struct device dev;
+ struct iio_dev *indio_dev;
+ struct module *owner;
+ int length;
+ int bytes_per_datum;
+ int bpe;
+ struct attribute_group *scan_el_attrs;
+ int scan_count;
+ unsigned long scan_mask;
+ bool scan_timestamp;
+ struct iio_handler access_handler;
+ const struct iio_ring_access_funcs *access;
+ const struct iio_ring_setup_ops *setup_ops;
+ struct list_head scan_el_dev_attr_list;
+ wait_queue_head_t pollq;
+ bool stufftoread;
};
/**
@@ -161,154 +131,8 @@
{
ring->bytes_per_datum = bytes_per_datum;
ring->length = length;
- ring->loopcount = 0;
}
-/**
- * struct iio_scan_el - an individual element of a scan
- * @dev_attr: control attribute (if directly controllable)
- * @number: unique identifier of element (used for bit mask)
- * @label: useful data for the scan el (often reg address)
- * @set_state: for some devices datardy signals are generated
- * for any enabled lines. This allows unwanted lines
- * to be disabled and hence not get in the way.
- **/
-struct iio_scan_el {
- struct device_attribute dev_attr;
- unsigned int number;
- unsigned int label;
-
- int (*set_state)(struct iio_scan_el *scanel,
- struct iio_dev *dev_info,
- bool state);
-};
-
-#define to_iio_scan_el(_dev_attr) \
- container_of(_dev_attr, struct iio_scan_el, dev_attr);
-
-/**
- * iio_scan_el_store() - sysfs scan element selection interface
- * @dev: the target device
- * @attr: the device attribute that is being processed
- * @buf: input from userspace
- * @len: length of input
- *
- * A generic function used to enable various scan elements. In some
- * devices explicit read commands for each channel mean this is merely
- * a software switch. In others this must actively disable the channel.
- * Complexities occur when this interacts with data ready type triggers
- * which may not reset unless every channel that is enabled is explicitly
- * read.
- **/
-ssize_t iio_scan_el_store(struct device *dev, struct device_attribute *attr,
- const char *buf, size_t len);
-/**
- * iio_scan_el_show() - sysfs interface to query whether a scan element
- * is enabled or not
- * @dev: the target device
- * @attr: the device attribute that is being processed
- * @buf: output buffer
- **/
-ssize_t iio_scan_el_show(struct device *dev, struct device_attribute *attr,
- char *buf);
-
-/**
- * iio_scan_el_ts_store() - sysfs interface to set whether a timestamp is included
- * in the scan.
- **/
-ssize_t iio_scan_el_ts_store(struct device *dev, struct device_attribute *attr,
- const char *buf, size_t len);
-/**
- * iio_scan_el_ts_show() - sysfs interface to query if a timestamp is included
- * in the scan.
- **/
-ssize_t iio_scan_el_ts_show(struct device *dev, struct device_attribute *attr,
- char *buf);
-/**
- * IIO_SCAN_EL_C - declare and initialize a scan element with a control func
- *
- * @_name: identifying name. Resulting struct is iio_scan_el_##_name,
- * sysfs element, _name##_en.
- * @_number: unique id number for the scan element.
- * length devices).
- * @_label: indentification variable used by drivers. Often a reg address.
- * @_controlfunc: function used to notify hardware of whether state changes
- **/
-#define __IIO_SCAN_EL_C(_name, _number, _label, _controlfunc) \
- struct iio_scan_el iio_scan_el_##_name = { \
- .dev_attr = __ATTR(_name##_en, \
- S_IRUGO | S_IWUSR, \
- iio_scan_el_show, \
- iio_scan_el_store), \
- .number = _number, \
- .label = _label, \
- .set_state = _controlfunc, \
- }; \
- static IIO_CONST_ATTR(_name##_index, #_number)
-
-#define IIO_SCAN_EL_C(_name, _number, _label, _controlfunc) \
- __IIO_SCAN_EL_C(_name, _number, _label, _controlfunc)
-
-#define __IIO_SCAN_NAMED_EL_C(_name, _string, _number, _label, _cf) \
- struct iio_scan_el iio_scan_el_##_name = { \
- .dev_attr = __ATTR(_string##_en, \
- S_IRUGO | S_IWUSR, \
- iio_scan_el_show, \
- iio_scan_el_store), \
- .number = _number, \
- .label = _label, \
- .set_state = _cf, \
- }; \
- static struct iio_const_attr iio_const_attr_##_name##_index = { \
- .string = #_number, \
- .dev_attr = __ATTR(_string##_index, \
- S_IRUGO, iio_read_const_attr, NULL) \
- }
-
-
-#define IIO_SCAN_NAMED_EL_C(_name, _string, _number, _label, _cf) \
- __IIO_SCAN_NAMED_EL_C(_name, _string, _number, _label, _cf)
-/**
- * IIO_SCAN_EL_TIMESTAMP - declare a special scan element for timestamps
- * @number: specify where in the scan order this is stored.
- *
- * Odd one out. Handled slightly differently from other scan elements.
- **/
-#define IIO_SCAN_EL_TIMESTAMP(number) \
- struct iio_scan_el iio_scan_el_timestamp = { \
- .dev_attr = __ATTR(timestamp_en, \
- S_IRUGO | S_IWUSR, \
- iio_scan_el_ts_show, \
- iio_scan_el_ts_store), \
- }; \
- static IIO_CONST_ATTR(timestamp_index, #number)
-
-/**
- * IIO_CONST_ATTR_SCAN_EL_TYPE - attr to specify the data format of a scan el
- * @name: the scan el name (may be more general and cover a set of scan elements
- * @_sign: either s or u for signed or unsigned
- * @_bits: number of actual bits occuplied by the value
- * @_storagebits: number of bits _bits is padded to when read out of buffer
- **/
-#define IIO_CONST_ATTR_SCAN_EL_TYPE(_name, _sign, _bits, _storagebits) \
- IIO_CONST_ATTR(_name##_type, #_sign#_bits"/"#_storagebits);
-
-/**
- * IIO_CONST_ATTR_SCAN_EL_TYPE_WITH_SHIFT - attr to specify the data format of a scan el
- * @name: the scan el name (may be more general and cover a set of scan elements
- * @_sign: either s or u for signed or unsigned
- * @_bits: number of actual bits occuplied by the value
- * @_storagebits: number of bits _bits is padded to when read out of buffer
- * @_shiftbits: number of bits _shiftbits the result must be shifted
- **/
-#define IIO_CONST_ATTR_SCAN_EL_TYPE_WITH_SHIFT(_name, _sign, _bits, \
- _storagebits, _shiftbits) \
- IIO_CONST_ATTR(_name##_type, #_sign#_bits"/"#_storagebits \
- ">>"#_shiftbits);
-
-#define IIO_SCAN_EL_TYPE_SIGNED 's'
-#define IIO_SCAN_EL_TYPE_UNSIGNED 'u'
-
/*
* These are mainly provided to allow for a change of implementation if a device
* has a large number of scan elements
@@ -375,41 +199,6 @@
};
/**
- * iio_scan_mask_clear() - clear a particular element from the scan mask
- * @ring: the ring buffer whose scan mask we are interested in
- * @bit: the bit to clear
- **/
-static inline int iio_scan_mask_clear(struct iio_ring_buffer *ring, int bit)
-{
- if (bit > IIO_MAX_SCAN_LENGTH)
- return -EINVAL;
- ring->scan_mask &= ~(1 << bit);
- ring->scan_count--;
- return 0;
-};
-
-/**
- * iio_scan_mask_count_to_right() - how many scan elements occur before here
- * @ring: the ring buffer whose scan mask we interested in
- * @bit: which number scan element is this
- **/
-static inline int iio_scan_mask_count_to_right(struct iio_ring_buffer *ring,
- int bit)
-{
- int count = 0;
- int mask = (1 << bit);
- if (bit > IIO_MAX_SCAN_LENGTH)
- return -EINVAL;
- while (mask) {
- mask >>= 1;
- if (mask & ring->scan_mask)
- count++;
- }
-
- return count;
-}
-
-/**
* iio_put_ring_buffer() - notify done with buffer
* @ring: the buffer we are done with.
**/
@@ -418,17 +207,19 @@
put_device(&ring->dev);
};
-#define to_iio_ring_buffer(d) \
+#define to_iio_ring_buffer(d) \
container_of(d, struct iio_ring_buffer, dev)
-#define access_dev_to_iio_ring_buffer(d) \
- container_of(d, struct iio_ring_buffer, access_dev)
/**
- * iio_ring_buffer_register() - register the buffer with IIO core
+ * iio_ring_buffer_register_ex() - register the buffer with IIO core
* @ring: the buffer to be registered
* @id: the id of the buffer (typically 0)
**/
-int iio_ring_buffer_register(struct iio_ring_buffer *ring, int id);
+int iio_ring_buffer_register_ex(struct iio_ring_buffer *ring, int id,
+ const struct iio_chan_spec *channels,
+ int num_channels);
+
+void iio_ring_access_release(struct device *dev);
/**
* iio_ring_buffer_unregister() - unregister the buffer from IIO core
@@ -476,11 +267,19 @@
#define IIO_RING_ENABLE_ATTR DEVICE_ATTR(enable, S_IRUGO | S_IWUSR, \
iio_show_ring_enable, \
iio_store_ring_enable)
+
+int iio_sw_ring_preenable(struct iio_dev *indio_dev);
+
#else /* CONFIG_IIO_RING_BUFFER */
-static inline int iio_ring_buffer_register(struct iio_ring_buffer *ring, int id)
+
+static inline int iio_ring_buffer_register_ex(struct iio_ring_buffer *ring,
+ int id,
+ struct iio_chan_spec *channels,
+ int num_channels)
{
return 0;
-};
+}
+
static inline void iio_ring_buffer_unregister(struct iio_ring_buffer *ring)
{};
diff --git a/drivers/staging/iio/ring_sw.c b/drivers/staging/iio/ring_sw.c
index b71ce39..feb84e2 100644
--- a/drivers/staging/iio/ring_sw.c
+++ b/drivers/staging/iio/ring_sw.c
@@ -12,10 +12,41 @@
#include <linux/module.h>
#include <linux/device.h>
#include <linux/workqueue.h>
+#include <linux/sched.h>
#include <linux/poll.h>
#include "ring_sw.h"
#include "trigger.h"
+/**
+ * struct iio_sw_ring_buffer - software ring buffer
+ * @buf: generic ring buffer elements
+ * @data: the ring buffer memory
+ * @read_p: read pointer (oldest available)
+ * @write_p: write pointer
+ * @last_written_p: read pointer (newest available)
+ * @half_p: half buffer length behind write_p (event generation)
+ * @use_count: reference count to prevent resizing when in use
+ * @update_needed: flag to indicated change in size requested
+ * @use_lock: lock to prevent change in size when in use
+ *
+ * Note that the first element of all ring buffers must be a
+ * struct iio_ring_buffer.
+**/
+struct iio_sw_ring_buffer {
+ struct iio_ring_buffer buf;
+ unsigned char *data;
+ unsigned char *read_p;
+ unsigned char *write_p;
+ unsigned char *last_written_p;
+ /* used to act as a point at which to signal an event */
+ unsigned char *half_p;
+ int use_count;
+ int update_needed;
+ spinlock_t use_lock;
+};
+
+#define iio_to_sw_ring(r) container_of(r, struct iio_sw_ring_buffer, buf)
+
static inline int __iio_allocate_sw_ring_buffer(struct iio_sw_ring_buffer *ring,
int bytes_per_datum, int length)
{
@@ -40,23 +71,21 @@
kfree(ring->data);
}
-void iio_mark_sw_rb_in_use(struct iio_ring_buffer *r)
+static void iio_mark_sw_rb_in_use(struct iio_ring_buffer *r)
{
struct iio_sw_ring_buffer *ring = iio_to_sw_ring(r);
spin_lock(&ring->use_lock);
ring->use_count++;
spin_unlock(&ring->use_lock);
}
-EXPORT_SYMBOL(iio_mark_sw_rb_in_use);
-void iio_unmark_sw_rb_in_use(struct iio_ring_buffer *r)
+static void iio_unmark_sw_rb_in_use(struct iio_ring_buffer *r)
{
struct iio_sw_ring_buffer *ring = iio_to_sw_ring(r);
spin_lock(&ring->use_lock);
ring->use_count--;
spin_unlock(&ring->use_lock);
}
-EXPORT_SYMBOL(iio_unmark_sw_rb_in_use);
/* Ring buffer related functionality */
@@ -68,7 +97,6 @@
unsigned char *data, s64 timestamp)
{
int ret = 0;
- int code;
unsigned char *temp_ptr, *change_test_ptr;
/* initial store */
@@ -123,14 +151,6 @@
*/
if (change_test_ptr == ring->read_p)
ring->read_p = temp_ptr;
-
- spin_lock(&ring->buf.shared_ev_pointer.lock);
-
- ret = iio_push_or_escallate_ring_event(&ring->buf,
- IIO_EVENT_CODE_RING_100_FULL, timestamp);
- spin_unlock(&ring->buf.shared_ev_pointer.lock);
- if (ret)
- goto error_ret;
}
/* investigate if our event barrier has been passed */
/* There are definite 'issues' with this and chances of
@@ -140,41 +160,35 @@
if (ring->half_p == ring->data + ring->buf.length*ring->buf.bytes_per_datum)
ring->half_p = ring->data;
if (ring->half_p == ring->read_p) {
- spin_lock(&ring->buf.shared_ev_pointer.lock);
- code = IIO_EVENT_CODE_RING_50_FULL;
- ret = __iio_push_event(&ring->buf.ev_int,
- code,
- timestamp,
- &ring->buf.shared_ev_pointer);
- spin_unlock(&ring->buf.shared_ev_pointer.lock);
+ ring->buf.stufftoread = true;
+ wake_up_interruptible(&ring->buf.pollq);
}
-error_ret:
return ret;
}
-int iio_rip_sw_rb(struct iio_ring_buffer *r,
- size_t count, char __user *buf, int *dead_offset)
+static int iio_read_first_n_sw_rb(struct iio_ring_buffer *r,
+ size_t n, char __user *buf)
{
struct iio_sw_ring_buffer *ring = iio_to_sw_ring(r);
u8 *initial_read_p, *initial_write_p, *current_read_p, *end_read_p;
u8 *data;
- int ret, max_copied;
- int bytes_to_rip;
+ int ret, max_copied, bytes_to_rip, dead_offset;
/* A userspace program has probably made an error if it tries to
* read something that is not a whole number of bpds.
* Return an error.
*/
- if (count % ring->buf.bytes_per_datum) {
+ if (n % ring->buf.bytes_per_datum) {
ret = -EINVAL;
printk(KERN_INFO "Ring buffer read request not whole number of"
"samples: Request bytes %zd, Current bytes per datum %d\n",
- count, ring->buf.bytes_per_datum);
+ n, ring->buf.bytes_per_datum);
goto error_ret;
}
/* Limit size to whole of ring buffer */
- bytes_to_rip = min((size_t)(ring->buf.bytes_per_datum*ring->buf.length), count);
+ bytes_to_rip = min((size_t)(ring->buf.bytes_per_datum*ring->buf.length),
+ n);
data = kmalloc(bytes_to_rip, GFP_KERNEL);
if (data == NULL) {
@@ -240,9 +254,9 @@
current_read_p = ring->read_p;
if (initial_read_p <= current_read_p)
- *dead_offset = current_read_p - initial_read_p;
+ dead_offset = current_read_p - initial_read_p;
else
- *dead_offset = ring->buf.length*ring->buf.bytes_per_datum
+ dead_offset = ring->buf.length*ring->buf.bytes_per_datum
- (initial_read_p - current_read_p);
/* possible issue if the initial write has been lapped or indeed
@@ -250,7 +264,7 @@
/* No valid data read.
* In this case the read pointer is already correct having been
* pushed further than we would look. */
- if (max_copied - *dead_offset < 0) {
+ if (max_copied - dead_offset < 0) {
ret = 0;
goto error_free_data_cpy;
}
@@ -266,26 +280,30 @@
while (ring->read_p != end_read_p)
ring->read_p = end_read_p;
- ret = max_copied - *dead_offset;
+ ret = max_copied - dead_offset;
- if (copy_to_user(buf, data + *dead_offset, ret)) {
+ if (copy_to_user(buf, data + dead_offset, ret)) {
ret = -EFAULT;
goto error_free_data_cpy;
}
+
+ if (bytes_to_rip >= ring->buf.length*ring->buf.bytes_per_datum/2)
+ ring->buf.stufftoread = 0;
+
error_free_data_cpy:
kfree(data);
error_ret:
return ret;
}
-EXPORT_SYMBOL(iio_rip_sw_rb);
-int iio_store_to_sw_rb(struct iio_ring_buffer *r, u8 *data, s64 timestamp)
+static int iio_store_to_sw_rb(struct iio_ring_buffer *r,
+ u8 *data,
+ s64 timestamp)
{
struct iio_sw_ring_buffer *ring = iio_to_sw_ring(r);
return iio_store_to_sw_ring(ring, data, timestamp);
}
-EXPORT_SYMBOL(iio_store_to_sw_rb);
static int iio_read_last_from_sw_ring(struct iio_sw_ring_buffer *ring,
unsigned char *data)
@@ -309,18 +327,18 @@
return 0;
}
-int iio_read_last_from_sw_rb(struct iio_ring_buffer *r,
+static int iio_read_last_from_sw_rb(struct iio_ring_buffer *r,
unsigned char *data)
{
return iio_read_last_from_sw_ring(iio_to_sw_ring(r), data);
}
-EXPORT_SYMBOL(iio_read_last_from_sw_rb);
-int iio_request_update_sw_rb(struct iio_ring_buffer *r)
+static int iio_request_update_sw_rb(struct iio_ring_buffer *r)
{
int ret = 0;
struct iio_sw_ring_buffer *ring = iio_to_sw_ring(r);
+ r->stufftoread = false;
spin_lock(&ring->use_lock);
if (!ring->update_needed)
goto error_ret;
@@ -335,54 +353,49 @@
spin_unlock(&ring->use_lock);
return ret;
}
-EXPORT_SYMBOL(iio_request_update_sw_rb);
-int iio_get_bytes_per_datum_sw_rb(struct iio_ring_buffer *r)
+static int iio_get_bytes_per_datum_sw_rb(struct iio_ring_buffer *r)
{
struct iio_sw_ring_buffer *ring = iio_to_sw_ring(r);
return ring->buf.bytes_per_datum;
}
-EXPORT_SYMBOL(iio_get_bytes_per_datum_sw_rb);
-int iio_set_bytes_per_datum_sw_rb(struct iio_ring_buffer *r, size_t bpd)
+static int iio_set_bytes_per_datum_sw_rb(struct iio_ring_buffer *r, size_t bpd)
{
if (r->bytes_per_datum != bpd) {
r->bytes_per_datum = bpd;
- if (r->access.mark_param_change)
- r->access.mark_param_change(r);
+ if (r->access->mark_param_change)
+ r->access->mark_param_change(r);
}
return 0;
}
-EXPORT_SYMBOL(iio_set_bytes_per_datum_sw_rb);
-int iio_get_length_sw_rb(struct iio_ring_buffer *r)
+static int iio_get_length_sw_rb(struct iio_ring_buffer *r)
{
return r->length;
}
-EXPORT_SYMBOL(iio_get_length_sw_rb);
-int iio_set_length_sw_rb(struct iio_ring_buffer *r, int length)
+static int iio_set_length_sw_rb(struct iio_ring_buffer *r, int length)
{
if (r->length != length) {
r->length = length;
- if (r->access.mark_param_change)
- r->access.mark_param_change(r);
+ if (r->access->mark_param_change)
+ r->access->mark_param_change(r);
}
return 0;
}
-EXPORT_SYMBOL(iio_set_length_sw_rb);
-int iio_mark_update_needed_sw_rb(struct iio_ring_buffer *r)
+static int iio_mark_update_needed_sw_rb(struct iio_ring_buffer *r)
{
struct iio_sw_ring_buffer *ring = iio_to_sw_ring(r);
ring->update_needed = true;
return 0;
}
-EXPORT_SYMBOL(iio_mark_update_needed_sw_rb);
static void iio_sw_rb_release(struct device *dev)
{
struct iio_ring_buffer *r = to_iio_ring_buffer(dev);
+ iio_ring_access_release(&r->dev);
kfree(iio_to_sw_ring(r));
}
@@ -420,13 +433,12 @@
ring = kzalloc(sizeof *ring, GFP_KERNEL);
if (!ring)
return NULL;
+ ring->update_needed = true;
buf = &ring->buf;
iio_ring_buffer_init(buf, indio_dev);
__iio_init_sw_ring_buffer(ring);
buf->dev.type = &iio_sw_ring_type;
- device_initialize(&buf->dev);
buf->dev.parent = &indio_dev->dev;
- buf->dev.bus = &iio_bus_type;
dev_set_drvdata(&buf->dev, (void *)buf);
return buf;
@@ -440,73 +452,20 @@
}
EXPORT_SYMBOL(iio_sw_rb_free);
-int iio_sw_ring_preenable(struct iio_dev *indio_dev)
-{
- struct iio_ring_buffer *ring = indio_dev->ring;
- size_t size;
- dev_dbg(&indio_dev->dev, "%s\n", __func__);
- /* Check if there are any scan elements enabled, if not fail*/
- if (!(ring->scan_count || ring->scan_timestamp))
- return -EINVAL;
- if (ring->scan_timestamp)
- if (ring->scan_count)
- /* Timestamp (aligned to s64) and data */
- size = (((ring->scan_count * ring->bpe)
- + sizeof(s64) - 1)
- & ~(sizeof(s64) - 1))
- + sizeof(s64);
- else /* Timestamp only */
- size = sizeof(s64);
- else /* Data only */
- size = ring->scan_count * ring->bpe;
- ring->access.set_bytes_per_datum(ring, size);
-
- return 0;
-}
-EXPORT_SYMBOL(iio_sw_ring_preenable);
-
-void iio_sw_trigger_bh_to_ring(struct work_struct *work_s)
-{
- struct iio_sw_ring_helper_state *st
- = container_of(work_s, struct iio_sw_ring_helper_state,
- work_trigger_to_ring);
- struct iio_ring_buffer *ring = st->indio_dev->ring;
- int len = 0;
- size_t datasize = ring->access.get_bytes_per_datum(ring);
- char *data = kmalloc(datasize, GFP_KERNEL);
-
- if (data == NULL) {
- dev_err(st->indio_dev->dev.parent,
- "memory alloc failed in ring bh");
- return;
- }
-
- if (ring->scan_count)
- len = st->get_ring_element(st, data);
-
- /* Guaranteed to be aligned with 8 byte boundary */
- if (ring->scan_timestamp)
- *(s64 *)(((phys_addr_t)data + len
- + sizeof(s64) - 1) & ~(sizeof(s64) - 1))
- = st->last_timestamp;
- ring->access.store_to(ring,
- (u8 *)data,
- st->last_timestamp);
-
- iio_trigger_notify_done(st->indio_dev->trig);
- kfree(data);
-
- return;
-}
-EXPORT_SYMBOL(iio_sw_trigger_bh_to_ring);
-
-void iio_sw_poll_func_th(struct iio_dev *indio_dev, s64 time)
-{ struct iio_sw_ring_helper_state *h
- = iio_dev_get_devdata(indio_dev);
- h->last_timestamp = time;
- schedule_work(&h->work_trigger_to_ring);
-}
-EXPORT_SYMBOL(iio_sw_poll_func_th);
+const struct iio_ring_access_funcs ring_sw_access_funcs = {
+ .mark_in_use = &iio_mark_sw_rb_in_use,
+ .unmark_in_use = &iio_unmark_sw_rb_in_use,
+ .store_to = &iio_store_to_sw_rb,
+ .read_last = &iio_read_last_from_sw_rb,
+ .read_first_n = &iio_read_first_n_sw_rb,
+ .mark_param_change = &iio_mark_update_needed_sw_rb,
+ .request_update = &iio_request_update_sw_rb,
+ .get_bytes_per_datum = &iio_get_bytes_per_datum_sw_rb,
+ .set_bytes_per_datum = &iio_set_bytes_per_datum_sw_rb,
+ .get_length = &iio_get_length_sw_rb,
+ .set_length = &iio_set_length_sw_rb,
+};
+EXPORT_SYMBOL(ring_sw_access_funcs);
MODULE_DESCRIPTION("Industrialio I/O software ring buffer");
MODULE_LICENSE("GPL");
diff --git a/drivers/staging/iio/ring_sw.h b/drivers/staging/iio/ring_sw.h
index 13341c1e..1527163 100644
--- a/drivers/staging/iio/ring_sw.h
+++ b/drivers/staging/iio/ring_sw.h
@@ -23,205 +23,13 @@
#ifndef _IIO_RING_SW_H_
#define _IIO_RING_SW_H_
-/* NEEDS COMMENTS */
-/* The intention is that this should be a separate module from the iio core.
- * This is a bit like supporting algorithms dependent on what the device
- * driver requests - some may support multiple options */
-
-
-#include "iio.h"
#include "ring_generic.h"
-#if defined CONFIG_IIO_SW_RING || defined CONFIG_IIO_SW_RING_MODULE
-
/**
- * iio_create_sw_rb() - software ring buffer allocation
- * @r: pointer to ring buffer pointer
+ * ring_sw_access_funcs - access functions for a software ring buffer
**/
-int iio_create_sw_rb(struct iio_ring_buffer **r);
-
-/**
- * iio_init_sw_rb() - initialize the software ring buffer
- * @r: pointer to a software ring buffer created by an
- * iio_create_sw_rb call
- * @indio_dev: industrial I/O device structure
- **/
-int iio_init_sw_rb(struct iio_ring_buffer *r, struct iio_dev *indio_dev);
-
-/**
- * iio_exit_sw_rb() - reverse what was done in iio_init_sw_rb
- * @r: pointer to a software ring buffer created by an
- * iio_create_sw_rb call
- **/
-void iio_exit_sw_rb(struct iio_ring_buffer *r);
-
-/**
- * iio_free_sw_rb() - free memory occupied by the core ring buffer struct
- * @r: pointer to a software ring buffer created by an
- * iio_create_sw_rb call
- **/
-void iio_free_sw_rb(struct iio_ring_buffer *r);
-
-/**
- * iio_mark_sw_rb_in_use() - reference counting to prevent incorrect chances
- * @r: pointer to a software ring buffer created by an
- * iio_create_sw_rb call
- **/
-void iio_mark_sw_rb_in_use(struct iio_ring_buffer *r);
-
-/**
- * iio_unmark_sw_rb_in_use() - notify the ring buffer that we don't care anymore
- * @r: pointer to a software ring buffer created by an
- * iio_create_sw_rb call
- **/
-void iio_unmark_sw_rb_in_use(struct iio_ring_buffer *r);
-
-/**
- * iio_read_last_from_sw_rb() - attempt to read the last stored datum from the rb
- * @r: pointer to a software ring buffer created by an
- * iio_create_sw_rb call
- * @data: where to store the last datum
- **/
-int iio_read_last_from_sw_rb(struct iio_ring_buffer *r, u8 *data);
-
-/**
- * iio_store_to_sw_rb() - store a new datum to the ring buffer
- * @r: pointer to ring buffer instance
- * @data: the datum to be stored including timestamp if relevant
- * @timestamp: timestamp which will be attached to buffer events if relevant
- **/
-int iio_store_to_sw_rb(struct iio_ring_buffer *r, u8 *data, s64 timestamp);
-
-/**
- * iio_rip_sw_rb() - attempt to read data from the ring buffer
- * @r: ring buffer instance
- * @count: number of datum's to try and read
- * @buf: userspace buffer into which data is copied
- * @dead_offset: how much of the stored data was possibly invalidated by
- * the end of the copy.
- **/
-int iio_rip_sw_rb(struct iio_ring_buffer *r,
- size_t count,
- char __user *buf,
- int *dead_offset);
-
-/**
- * iio_request_update_sw_rb() - update params if update needed
- * @r: pointer to a software ring buffer created by an
- * iio_create_sw_rb call
- **/
-int iio_request_update_sw_rb(struct iio_ring_buffer *r);
-
-/**
- * iio_mark_update_needed_sw_rb() - tell the ring buffer it needs a param update
- * @r: pointer to a software ring buffer created by an
- * iio_create_sw_rb call
- **/
-int iio_mark_update_needed_sw_rb(struct iio_ring_buffer *r);
-
-
-/**
- * iio_get_bytes_per_datum_sw_rb() - get the datum size in bytes
- * @r: pointer to a software ring buffer created by an
- * iio_create_sw_rb call
- **/
-int iio_get_bytes_per_datum_sw_rb(struct iio_ring_buffer *r);
-
-/**
- * iio_set_bytes_per_datum_sw_rb() - set the datum size in bytes
- * @r: pointer to a software ring buffer created by an
- * iio_create_sw_rb call
- * @bpd: bytes per datum value
- **/
-int iio_set_bytes_per_datum_sw_rb(struct iio_ring_buffer *r, size_t bpd);
-
-/**
- * iio_get_length_sw_rb() - get how many datums the rb may contain
- * @r: pointer to a software ring buffer created by an
- * iio_create_sw_rb call
- **/
-int iio_get_length_sw_rb(struct iio_ring_buffer *r);
-
-/**
- * iio_set_length_sw_rb() - set how many datums the rb may contain
- * @r: pointer to a software ring buffer created by an
- * iio_create_sw_rb call
- * @length: max number of data items for the ring buffer
- **/
-int iio_set_length_sw_rb(struct iio_ring_buffer *r, int length);
-
-/**
- * iio_ring_sw_register_funcs() - helper function to set up rb access
- * @ra: pointer to @iio_ring_access_funcs
- **/
-static inline void iio_ring_sw_register_funcs(struct iio_ring_access_funcs *ra)
-{
- ra->mark_in_use = &iio_mark_sw_rb_in_use;
- ra->unmark_in_use = &iio_unmark_sw_rb_in_use;
-
- ra->store_to = &iio_store_to_sw_rb;
- ra->read_last = &iio_read_last_from_sw_rb;
- ra->rip_lots = &iio_rip_sw_rb;
-
- ra->mark_param_change = &iio_mark_update_needed_sw_rb;
- ra->request_update = &iio_request_update_sw_rb;
-
- ra->get_bytes_per_datum = &iio_get_bytes_per_datum_sw_rb;
- ra->set_bytes_per_datum = &iio_set_bytes_per_datum_sw_rb;
-
- ra->get_length = &iio_get_length_sw_rb;
- ra->set_length = &iio_set_length_sw_rb;
-};
-
-/**
- * struct iio_sw_ring_buffer - software ring buffer
- * @buf: generic ring buffer elements
- * @data: the ring buffer memory
- * @read_p: read pointer (oldest available)
- * @write_p: write pointer
- * @last_written_p: read pointer (newest available)
- * @half_p: half buffer length behind write_p (event generation)
- * @use_count: reference count to prevent resizing when in use
- * @update_needed: flag to indicated change in size requested
- * @use_lock: lock to prevent change in size when in use
- *
- * Note that the first element of all ring buffers must be a
- * struct iio_ring_buffer.
-**/
-
-struct iio_sw_ring_buffer {
- struct iio_ring_buffer buf;
- unsigned char *data;
- unsigned char *read_p;
- unsigned char *write_p;
- unsigned char *last_written_p;
- /* used to act as a point at which to signal an event */
- unsigned char *half_p;
- int use_count;
- int update_needed;
- spinlock_t use_lock;
-};
-
-#define iio_to_sw_ring(r) container_of(r, struct iio_sw_ring_buffer, buf)
+extern const struct iio_ring_access_funcs ring_sw_access_funcs;
struct iio_ring_buffer *iio_sw_rb_allocate(struct iio_dev *indio_dev);
void iio_sw_rb_free(struct iio_ring_buffer *ring);
-
-int iio_sw_ring_preenable(struct iio_dev *indio_dev);
-
-struct iio_sw_ring_helper_state {
- struct work_struct work_trigger_to_ring;
- struct iio_dev *indio_dev;
- int (*get_ring_element)(struct iio_sw_ring_helper_state *st, u8 *buf);
- s64 last_timestamp;
-};
-
-void iio_sw_poll_func_th(struct iio_dev *indio_dev, s64 time);
-void iio_sw_trigger_bh_to_ring(struct work_struct *work_s);
-
-#else /* CONFIG_IIO_RING_BUFFER*/
-struct iio_sw_ring_helper_state {
- struct iio_dev *indio_dev;
-};
-#endif /* !CONFIG_IIO_RING_BUFFER */
#endif /* _IIO_RING_SW_H_ */
diff --git a/drivers/staging/iio/sysfs.h b/drivers/staging/iio/sysfs.h
index 24b74dd..dd79b58 100644
--- a/drivers/staging/iio/sysfs.h
+++ b/drivers/staging/iio/sysfs.h
@@ -15,30 +15,18 @@
#include "iio.h"
/**
- * struct iio_event_attr - event control attribute
- * @dev_attr: underlying device attribute
- * @mask: mask for the event when detecting
- * @listel: list header to allow addition to list of event handlers
-*/
-struct iio_event_attr {
- struct device_attribute dev_attr;
- int mask;
- struct iio_event_handler_list *listel;
-};
-
-#define to_iio_event_attr(_dev_attr) \
- container_of(_dev_attr, struct iio_event_attr, dev_attr)
-
-/**
* struct iio_dev_attr - iio specific device attribute
* @dev_attr: underlying device attribute
* @address: associated register address
* @val2: secondary attribute value
+ * @l: list head for maintaining list of dynamically created attrs.
*/
struct iio_dev_attr {
struct device_attribute dev_attr;
int address;
int val2;
+ struct list_head l;
+ struct iio_chan_spec const *c;
};
#define to_iio_dev_attr(_dev_attr) \
@@ -101,13 +89,6 @@
IIO_DEVICE_ATTR(revision, S_IRUGO, _show, NULL, 0)
/**
- * IIO_DEV_ATTR_NAME - chip type dependent identifier
- * @_show: output method for the attribute
- **/
-#define IIO_DEV_ATTR_NAME(_show) \
- IIO_DEVICE_ATTR(name, S_IRUGO, _show, NULL, 0)
-
-/**
* IIO_DEV_ATTR_RESET: resets the device
**/
#define IIO_DEV_ATTR_RESET(_store) \
@@ -180,104 +161,27 @@
#define IIO_CONST_ATTR_TEMP_SCALE(_string) \
IIO_CONST_ATTR(temp_scale, _string)
-/**
- * IIO_EVENT_SH - generic shared event handler
- * @_name: event name
- * @_handler: handler function to be called
- *
- * This is used in cases where more than one event may result from a single
- * handler. Often the case that some alarm register must be read and multiple
- * alarms may have been triggered.
- **/
-#define IIO_EVENT_SH(_name, _handler) \
- static struct iio_event_handler_list \
- iio_event_##_name = { \
- .handler = _handler, \
- .refcount = 0, \
- .exist_lock = __MUTEX_INITIALIZER(iio_event_##_name \
- .exist_lock), \
- .list = { \
- .next = &iio_event_##_name.list, \
- .prev = &iio_event_##_name.list, \
- }, \
- };
+/* must match our channel defs */
+#define IIO_EV_CLASS_IN IIO_IN
+#define IIO_EV_CLASS_IN_DIFF IIO_IN_DIFF
+#define IIO_EV_CLASS_ACCEL IIO_ACCEL
+#define IIO_EV_CLASS_GYRO IIO_GYRO
+#define IIO_EV_CLASS_MAGN IIO_MAGN
+#define IIO_EV_CLASS_LIGHT IIO_LIGHT
+#define IIO_EV_CLASS_PROXIMITY IIO_PROXIMITY
+#define IIO_EV_CLASS_TEMP IIO_TEMP
-/**
- * IIO_EVENT_ATTR_SH - generic shared event attribute
- * @_name: event name
- * @_ev_list: event handler list
- * @_show: output method for the attribute
- * @_store: input method for the attribute
- * @_mask: mask used when detecting the event
- *
- * An attribute with an associated IIO_EVENT_SH
- **/
-#define IIO_EVENT_ATTR_SH(_name, _ev_list, _show, _store, _mask) \
- static struct iio_event_attr \
- iio_event_attr_##_name \
- = { .dev_attr = __ATTR(_name, S_IRUGO | S_IWUSR, \
- _show, _store), \
- .mask = _mask, \
- .listel = &_ev_list };
-
-#define IIO_EVENT_ATTR_NAMED_SH(_vname, _name, _ev_list, _show, _store, _mask) \
- static struct iio_event_attr \
- iio_event_attr_##_vname \
- = { .dev_attr = __ATTR(_name, S_IRUGO | S_IWUSR, \
- _show, _store), \
- .mask = _mask, \
- .listel = &_ev_list };
-
-/**
- * IIO_EVENT_ATTR - non-shared event attribute
- * @_name: event name
- * @_show: output method for the attribute
- * @_store: input method for the attribute
- * @_mask: mask used when detecting the event
- * @_handler: handler function to be called
- **/
-#define IIO_EVENT_ATTR(_name, _show, _store, _mask, _handler) \
- IIO_EVENT_SH(_name, _handler); \
- static struct \
- iio_event_attr \
- iio_event_attr_##_name \
- = { .dev_attr = __ATTR(_name, S_IRUGO | S_IWUSR, \
- _show, _store), \
- .mask = _mask, \
- .listel = &iio_event_##_name }; \
-
-/**
- * IIO_EVENT_ATTR_DATA_RDY - event driven by data ready signal
- * @_show: output method for the attribute
- * @_store: input method for the attribute
- * @_mask: mask used when detecting the event
- * @_handler: handler function to be called
- *
- * Not typically implemented in devices where full triggering support
- * has been implemented.
- **/
-#define IIO_EVENT_ATTR_DATA_RDY(_show, _store, _mask, _handler) \
- IIO_EVENT_ATTR(data_rdy, _show, _store, _mask, _handler)
-
-#define IIO_EV_CLASS_BUFFER 0
-#define IIO_EV_CLASS_IN 1
-#define IIO_EV_CLASS_ACCEL 2
-#define IIO_EV_CLASS_GYRO 3
-#define IIO_EV_CLASS_MAGN 4
-#define IIO_EV_CLASS_LIGHT 5
-#define IIO_EV_CLASS_PROXIMITY 6
-
-#define IIO_EV_MOD_X 0
-#define IIO_EV_MOD_Y 1
-#define IIO_EV_MOD_Z 2
-#define IIO_EV_MOD_X_AND_Y 3
-#define IIO_EV_MOD_X_ANX_Z 4
-#define IIO_EV_MOD_Y_AND_Z 5
-#define IIO_EV_MOD_X_AND_Y_AND_Z 6
-#define IIO_EV_MOD_X_OR_Y 7
-#define IIO_EV_MOD_X_OR_Z 8
-#define IIO_EV_MOD_Y_OR_Z 9
-#define IIO_EV_MOD_X_OR_Y_OR_Z 10
+#define IIO_EV_MOD_X IIO_MOD_X
+#define IIO_EV_MOD_Y IIO_MOD_Y
+#define IIO_EV_MOD_Z IIO_MOD_Z
+#define IIO_EV_MOD_X_AND_Y IIO_MOD_X_AND_Y
+#define IIO_EV_MOD_X_ANX_Z IIO_MOD_X_AND_Z
+#define IIO_EV_MOD_Y_AND_Z IIO_MOD_Y_AND_Z
+#define IIO_EV_MOD_X_AND_Y_AND_Z IIO_MOD_X_AND_Y_AND_Z
+#define IIO_EV_MOD_X_OR_Y IIO_MOD_X_OR_Y
+#define IIO_EV_MOD_X_OR_Z IIO_MOD_X_OR_Z
+#define IIO_EV_MOD_Y_OR_Z IIO_MOD_Y_OR_Z
+#define IIO_EV_MOD_X_OR_Y_OR_Z IIO_MOD_X_OR_Y_OR_Z
#define IIO_EV_TYPE_THRESH 0
#define IIO_EV_TYPE_MAG 1
@@ -287,6 +191,10 @@
#define IIO_EV_DIR_RISING 1
#define IIO_EV_DIR_FALLING 2
+#define IIO_EV_TYPE_MAX 8
+#define IIO_EV_BIT(type, direction) \
+ (1 << (type*IIO_EV_TYPE_MAX + direction))
+
#define IIO_EVENT_CODE(channelclass, orient_bit, number, \
modifier, type, direction) \
(channelclass | (orient_bit << 8) | ((number) << 9) | \
@@ -303,38 +211,12 @@
#define IIO_BUFFER_EVENT_CODE(code) \
(IIO_EV_CLASS_BUFFER | (code << 8))
-/**
- * IIO_EVENT_ATTR_RING_50_FULL - ring buffer event to indicate 50% full
- * @_show: output method for the attribute
- * @_store: input method for the attribute
- * @_mask: mask used when detecting the event
- * @_handler: handler function to be called
- **/
-#define IIO_EVENT_ATTR_RING_50_FULL(_show, _store, _mask, _handler) \
- IIO_EVENT_ATTR(ring_50_full, _show, _store, _mask, _handler)
+#define IIO_EVENT_CODE_EXTRACT_DIR(mask) ((mask >> 24) & 0xf)
-/**
- * IIO_EVENT_ATTR_RING_50_FULL_SH - shared ring event to indicate 50% full
- * @_evlist: event handler list
- * @_show: output method for the attribute
- * @_store: input method for the attribute
- * @_mask: mask used when detecting the event
- **/
-#define IIO_EVENT_ATTR_RING_50_FULL_SH(_evlist, _show, _store, _mask) \
- IIO_EVENT_ATTR_SH(ring_50_full, _evlist, _show, _store, _mask)
+/* Event code number extraction depends on which type of event we have.
+ * Perhaps review this function in the future*/
+#define IIO_EVENT_CODE_EXTRACT_NUM(mask) ((mask >> 9) & 0x0f)
-/**
- * IIO_EVENT_ATTR_RING_75_FULL_SH - shared ring event to indicate 75% full
- * @_evlist: event handler list
- * @_show: output method for the attribute
- * @_store: input method for the attribute
- * @_mask: mask used when detecting the event
- **/
-#define IIO_EVENT_ATTR_RING_75_FULL_SH(_evlist, _show, _store, _mask) \
- IIO_EVENT_ATTR_SH(ring_75_full, _evlist, _show, _store, _mask)
-
-#define IIO_EVENT_CODE_RING_50_FULL IIO_BUFFER_EVENT_CODE(0)
-#define IIO_EVENT_CODE_RING_75_FULL IIO_BUFFER_EVENT_CODE(1)
-#define IIO_EVENT_CODE_RING_100_FULL IIO_BUFFER_EVENT_CODE(2)
+#define IIO_EVENT_CODE_EXTRACT_MODIFIER(mask) ((mask >> 13) & 0x7)
#endif /* _INDUSTRIAL_IO_SYSFS_H_ */
diff --git a/drivers/staging/iio/trigger.h b/drivers/staging/iio/trigger.h
index 469beba..f329fe1 100644
--- a/drivers/staging/iio/trigger.h
+++ b/drivers/staging/iio/trigger.h
@@ -6,9 +6,15 @@
* under the terms of the GNU General Public License version 2 as published by
* the Free Software Foundation.
*/
+#include <linux/irq.h>
+
#ifndef _IIO_TRIGGER_H_
#define _IIO_TRIGGER_H_
+struct iio_subirq {
+ bool enabled;
+};
+
/**
* struct iio_trigger - industrial I/O trigger device
*
@@ -18,14 +24,16 @@
* @private_data: [DRIVER] device specific data
* @list: [INTERN] used in maintenance of global trigger list
* @alloc_list: [DRIVER] used for driver specific trigger list
- * @pollfunc_list_lock: [INTERN] protection of the polling function list
- * @pollfunc_list: [INTERN] list of functions to run on trigger.
- * @control_attrs: [DRIVER] sysfs attributes relevant to trigger type
* @owner: [DRIVER] used to monitor usage count of the trigger.
* @use_count: use count for the trigger
* @set_trigger_state: [DRIVER] switch on/off the trigger on demand
* @try_reenable: function to reenable the trigger when the
* use count is zero (may be NULL)
+ * @subirq_chip: [INTERN] associate 'virtual' irq chip.
+ * @subirq_base: [INTERN] base number for irqs provided by trigger.
+ * @subirqs: [INTERN] information about the 'child' irqs.
+ * @pool: [INTERN] bitmap of irqs currently in use.
+ * @pool_lock: [INTERN] protection of the irq pool.
**/
struct iio_trigger {
int id;
@@ -35,14 +43,18 @@
void *private_data;
struct list_head list;
struct list_head alloc_list;
- spinlock_t pollfunc_list_lock;
- struct list_head pollfunc_list;
- const struct attribute_group *control_attrs;
struct module *owner;
int use_count;
int (*set_trigger_state)(struct iio_trigger *trig, bool state);
int (*try_reenable)(struct iio_trigger *trig);
+
+ struct irq_chip subirq_chip;
+ int subirq_base;
+
+ struct iio_subirq subirqs[CONFIG_IIO_CONSUMERS_PER_TRIGGER];
+ unsigned long pool[BITS_TO_LONGS(CONFIG_IIO_CONSUMERS_PER_TRIGGER)];
+ struct mutex pool_lock;
};
static inline struct iio_trigger *to_iio_trigger(struct device *d)
@@ -63,27 +75,6 @@
};
/**
- * iio_trigger_read_name() - sysfs access function to get the trigger name
- * @dev: the system device
- * @attr: device attributes for the device
- * @buf: output buffer to store the trigger name
- **/
-ssize_t iio_trigger_read_name(struct device *dev,
- struct device_attribute *attr,
- char *buf);
-
-#define IIO_TRIGGER_NAME_ATTR DEVICE_ATTR(name, S_IRUGO, \
- iio_trigger_read_name, \
- NULL);
-
-/**
- * iio_trigger_find_by_name() - search global trigger list
- * @name: trigger name to search for
- * @len: trigger name string length to compare
- **/
-struct iio_trigger *iio_trigger_find_by_name(const char *name, size_t len);
-
-/**
* iio_trigger_register() - register a trigger with the IIO core
* @trig_info: trigger to be registered
**/
@@ -119,36 +110,65 @@
* Typically called in relevant hardware interrupt handler.
**/
void iio_trigger_poll(struct iio_trigger *trig, s64 time);
+void iio_trigger_poll_chained(struct iio_trigger *trig, s64 time);
void iio_trigger_notify_done(struct iio_trigger *trig);
+irqreturn_t iio_trigger_generic_data_rdy_poll(int irq, void *private);
+
+static inline int iio_trigger_get_irq(struct iio_trigger *trig)
+{
+ int ret;
+ mutex_lock(&trig->pool_lock);
+ ret = bitmap_find_free_region(trig->pool,
+ CONFIG_IIO_CONSUMERS_PER_TRIGGER,
+ ilog2(1));
+ mutex_unlock(&trig->pool_lock);
+ if (ret >= 0)
+ ret += trig->subirq_base;
+
+ return ret;
+};
+
+static inline void iio_trigger_put_irq(struct iio_trigger *trig, int irq)
+{
+ mutex_lock(&trig->pool_lock);
+ clear_bit(irq - trig->subirq_base, trig->pool);
+ mutex_unlock(&trig->pool_lock);
+};
+
/**
* struct iio_poll_func - poll function pair
*
- * @list: associate this with a triggers pollfunc_list
* @private_data: data specific to device (passed into poll func)
- * @poll_func_immediate: function in here is run first. They should be
- * extremely lightweight. Typically used for latch
- * control on sensor supporting it.
- * @poll_func_main: function in here is run after all immediates.
- * Reading from sensor etc typically involves
- * scheduling from here.
- *
- * The two stage approach used here is only important when multiple sensors are
- * being triggered by a single trigger. This really comes into its own with
- * simultaneous sampling devices where a simple latch command can be used to
- * make the device store the values on all inputs.
+ * @h: the function that is actually run on trigger
+ * @thread: threaded interrupt part
+ * @type: the type of interrupt (basically if oneshot)
+ * @name: name used to identify the trigger consumer.
+ * @irq: the corresponding irq as allocated from the
+ * trigger pool
+ * @timestamp: some devices need a timestamp grabbed as soon
+ * as possible after the trigger - hence handler
+ * passes it via here.
**/
struct iio_poll_func {
- struct list_head list;
void *private_data;
- void (*poll_func_immediate)(struct iio_dev *indio_dev);
- void (*poll_func_main)(struct iio_dev *private_data, s64 time);
-
+ irqreturn_t (*h)(int irq, void *p);
+ irqreturn_t (*thread)(int irq, void *p);
+ int type;
+ char *name;
+ int irq;
+ s64 timestamp;
};
-int iio_alloc_pollfunc(struct iio_dev *indio_dev,
- void (*immediate)(struct iio_dev *indio_dev),
- void (*main)(struct iio_dev *private_data, s64 time));
+struct iio_poll_func
+*iio_alloc_pollfunc(irqreturn_t (*h)(int irq, void *p),
+ irqreturn_t (*thread)(int irq, void *p),
+ int type,
+ void *private,
+ const char *fmt,
+ ...);
+void iio_dealloc_pollfunc(struct iio_poll_func *pf);
+irqreturn_t iio_pollfunc_store_time(int irq, void *p);
/*
* Two functions for common case where all that happens is a pollfunc
@@ -157,8 +177,8 @@
int iio_triggered_ring_postenable(struct iio_dev *indio_dev);
int iio_triggered_ring_predisable(struct iio_dev *indio_dev);
-struct iio_trigger *iio_allocate_trigger(void);
-
+struct iio_trigger *iio_allocate_trigger(const char *fmt, ...)
+ __attribute__((format(printf, 1, 2)));
void iio_free_trigger(struct iio_trigger *trig);
#endif /* _IIO_TRIGGER_H_ */
diff --git a/drivers/staging/iio/trigger/Kconfig b/drivers/staging/iio/trigger/Kconfig
index c33777e..b8abf54 100644
--- a/drivers/staging/iio/trigger/Kconfig
+++ b/drivers/staging/iio/trigger/Kconfig
@@ -31,6 +31,7 @@
config IIO_BFIN_TMR_TRIGGER
tristate "Blackfin TIMER trigger"
depends on BLACKFIN
+ select BFIN_GPTIMERS
help
Provides support for using a Blackfin timer as IIO triggers.
If unsure, say N (but it's safe to say "Y").
diff --git a/drivers/staging/iio/trigger/iio-trig-bfin-timer.c b/drivers/staging/iio/trigger/iio-trig-bfin-timer.c
index 583bef0..4f17295 100644
--- a/drivers/staging/iio/trigger/iio-trig-bfin-timer.c
+++ b/drivers/staging/iio/trigger/iio-trig-bfin-timer.c
@@ -106,11 +106,9 @@
static DEVICE_ATTR(frequency, S_IRUGO | S_IWUSR, iio_bfin_tmr_frequency_show,
iio_bfin_tmr_frequency_store);
-static IIO_TRIGGER_NAME_ATTR;
static struct attribute *iio_bfin_tmr_trigger_attrs[] = {
&dev_attr_frequency.attr,
- &dev_attr_name.attr,
NULL,
};
@@ -118,6 +116,11 @@
.attrs = iio_bfin_tmr_trigger_attrs,
};
+static const struct attribute_group *iio_bfin_tmr_trigger_attr_groups[] = {
+ &iio_bfin_tmr_trigger_attr_group,
+ NULL
+};
+
static irqreturn_t iio_bfin_tmr_trigger_isr(int irq, void *devid)
{
@@ -165,24 +168,18 @@
st->timer_num = ret;
st->t = &iio_bfin_timer_code[st->timer_num];
- st->trig = iio_allocate_trigger();
+ st->trig = iio_allocate_trigger("bfintmr%d", st->timer_num);
if (!st->trig) {
ret = -ENOMEM;
goto out1;
}
st->trig->private_data = st;
- st->trig->control_attrs = &iio_bfin_tmr_trigger_attr_group;
st->trig->owner = THIS_MODULE;
- st->trig->name = kasprintf(GFP_KERNEL, "bfintmr%d", st->timer_num);
- if (st->trig->name == NULL) {
- ret = -ENOMEM;
- goto out2;
- }
-
+ st->trig->dev.groups = iio_bfin_tmr_trigger_attr_groups;
ret = iio_trigger_register(st->trig);
if (ret)
- goto out3;
+ goto out2;
ret = request_irq(st->irq, iio_bfin_tmr_trigger_isr,
0, st->trig->name, st);
@@ -201,8 +198,6 @@
return 0;
out4:
iio_trigger_unregister(st->trig);
-out3:
- kfree(st->trig->name);
out2:
iio_put_trigger(st->trig);
out1:
@@ -218,7 +213,6 @@
disable_gptimers(st->t->bit);
free_irq(st->irq, st);
iio_trigger_unregister(st->trig);
- kfree(st->trig->name);
iio_put_trigger(st->trig);
kfree(st);
diff --git a/drivers/staging/iio/trigger/iio-trig-gpio.c b/drivers/staging/iio/trigger/iio-trig-gpio.c
index 2ce95e9..b188635 100644
--- a/drivers/staging/iio/trigger/iio-trig-gpio.c
+++ b/drivers/staging/iio/trigger/iio-trig-gpio.c
@@ -47,17 +47,6 @@
return IRQ_HANDLED;
}
-static IIO_TRIGGER_NAME_ATTR;
-
-static struct attribute *iio_gpio_trigger_attrs[] = {
- &dev_attr_name.attr,
- NULL,
-};
-
-static const struct attribute_group iio_gpio_trigger_attr_group = {
- .attrs = iio_gpio_trigger_attrs,
-};
-
static int iio_gpio_trigger_probe(struct platform_device *pdev)
{
struct iio_gpio_trigger_info *trig_info;
@@ -79,7 +68,7 @@
for (irq = irq_res->start; irq <= irq_res->end; irq++) {
- trig = iio_allocate_trigger();
+ trig = iio_allocate_trigger("irqtrig%d", irq);
if (!trig) {
ret = -ENOMEM;
goto error_free_completed_registrations;
@@ -90,21 +79,15 @@
ret = -ENOMEM;
goto error_put_trigger;
}
- trig->control_attrs = &iio_gpio_trigger_attr_group;
trig->private_data = trig_info;
trig_info->irq = irq;
trig->owner = THIS_MODULE;
- trig->name = kasprintf(GFP_KERNEL, "irqtrig%d", irq);
- if (trig->name == NULL) {
- ret = -ENOMEM;
- goto error_free_trig_info;
- }
ret = request_irq(irq, iio_gpio_trigger_poll,
irqflags, trig->name, trig);
if (ret) {
dev_err(&pdev->dev,
"request IRQ-%d failed", irq);
- goto error_free_name;
+ goto error_free_trig_info;
}
ret = iio_trigger_register(trig);
@@ -124,8 +107,6 @@
/* First clean up the partly allocated trigger */
error_release_irq:
free_irq(irq, trig);
-error_free_name:
- kfree(trig->name);
error_free_trig_info:
kfree(trig_info);
error_put_trigger:
@@ -138,7 +119,6 @@
alloc_list) {
trig_info = trig->private_data;
free_irq(gpio_to_irq(trig_info->irq), trig);
- kfree(trig->name);
kfree(trig_info);
iio_trigger_unregister(trig);
}
@@ -159,7 +139,6 @@
trig_info = trig->private_data;
iio_trigger_unregister(trig);
free_irq(trig_info->irq, trig);
- kfree(trig->name);
kfree(trig_info);
iio_put_trigger(trig);
}
diff --git a/drivers/staging/iio/trigger/iio-trig-periodic-rtc.c b/drivers/staging/iio/trigger/iio-trig-periodic-rtc.c
index 24f174e..01cf7e2 100644
--- a/drivers/staging/iio/trigger/iio-trig-periodic-rtc.c
+++ b/drivers/staging/iio/trigger/iio-trig-periodic-rtc.c
@@ -72,20 +72,24 @@
return ret;
}
-static IIO_TRIGGER_NAME_ATTR;
static DEVICE_ATTR(frequency, S_IRUGO | S_IWUSR,
iio_trig_periodic_read_freq,
iio_trig_periodic_write_freq);
static struct attribute *iio_trig_prtc_attrs[] = {
&dev_attr_frequency.attr,
- &dev_attr_name.attr,
NULL,
};
+
static const struct attribute_group iio_trig_prtc_attr_group = {
.attrs = iio_trig_prtc_attrs,
};
+static const struct attribute_group *iio_trig_prtc_attr_groups[] = {
+ &iio_trig_prtc_attr_group,
+ NULL
+};
+
static void iio_prtc_trigger_poll(void *private_data)
{
/* Timestamp is not provided currently */
@@ -103,7 +107,7 @@
for (i = 0;; i++) {
if (pdata[i] == NULL)
break;
- trig = iio_allocate_trigger();
+ trig = iio_allocate_trigger("periodic%s", pdata[i]);
if (!trig) {
ret = -ENOMEM;
goto error_free_completed_registrations;
@@ -118,25 +122,19 @@
trig->private_data = trig_info;
trig->owner = THIS_MODULE;
trig->set_trigger_state = &iio_trig_periodic_rtc_set_state;
- trig->name = kasprintf(GFP_KERNEL, "periodic%s", pdata[i]);
- if (trig->name == NULL) {
- ret = -ENOMEM;
- goto error_free_trig_info;
- }
-
/* RTC access */
trig_info->rtc
= rtc_class_open(pdata[i]);
if (trig_info->rtc == NULL) {
ret = -EINVAL;
- goto error_free_name;
+ goto error_free_trig_info;
}
trig_info->task.func = iio_prtc_trigger_poll;
trig_info->task.private_data = trig;
ret = rtc_irq_register(trig_info->rtc, &trig_info->task);
if (ret)
goto error_close_rtc;
- trig->control_attrs = &iio_trig_prtc_attr_group;
+ trig->dev.groups = iio_trig_prtc_attr_groups;
ret = iio_trigger_register(trig);
if (ret)
goto error_unregister_rtc_irq;
@@ -146,8 +144,6 @@
rtc_irq_unregister(trig_info->rtc, &trig_info->task);
error_close_rtc:
rtc_class_close(trig_info->rtc);
-error_free_name:
- kfree(trig->name);
error_free_trig_info:
kfree(trig_info);
error_put_trigger_and_remove_from_list:
@@ -161,7 +157,6 @@
trig_info = trig->private_data;
rtc_irq_unregister(trig_info->rtc, &trig_info->task);
rtc_class_close(trig_info->rtc);
- kfree(trig->name);
kfree(trig_info);
iio_trigger_unregister(trig);
}
@@ -180,7 +175,6 @@
trig_info = trig->private_data;
rtc_irq_unregister(trig_info->rtc, &trig_info->task);
rtc_class_close(trig_info->rtc);
- kfree(trig->name);
kfree(trig_info);
iio_trigger_unregister(trig);
}
diff --git a/drivers/staging/iio/trigger/iio-trig-sysfs.c b/drivers/staging/iio/trigger/iio-trig-sysfs.c
index 127a2a3..47248cd 100644
--- a/drivers/staging/iio/trigger/iio-trig-sysfs.c
+++ b/drivers/staging/iio/trigger/iio-trig-sysfs.c
@@ -9,25 +9,92 @@
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/slab.h>
+#include <linux/list.h>
#include "../iio.h"
#include "../trigger.h"
+struct iio_sysfs_trig {
+ struct iio_trigger *trig;
+ int id;
+ struct list_head l;
+};
+
+static LIST_HEAD(iio_sysfs_trig_list);
+static DEFINE_MUTEX(iio_syfs_trig_list_mut);
+
+static int iio_sysfs_trigger_probe(int id);
+static ssize_t iio_sysfs_trig_add(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf,
+ size_t len)
+{
+ int ret;
+ unsigned long input;
+
+ ret = strict_strtoul(buf, 10, &input);
+ if (ret)
+ return ret;
+ ret = iio_sysfs_trigger_probe(input);
+ if (ret)
+ return ret;
+ return len;
+}
+static DEVICE_ATTR(add_trigger, S_IWUSR, NULL, &iio_sysfs_trig_add);
+
+static int iio_sysfs_trigger_remove(int id);
+static ssize_t iio_sysfs_trig_remove(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf,
+ size_t len)
+{
+ int ret;
+ unsigned long input;
+
+ ret = strict_strtoul(buf, 10, &input);
+ if (ret)
+ return ret;
+ ret = iio_sysfs_trigger_remove(input);
+ if (ret)
+ return ret;
+ return len;
+}
+
+static DEVICE_ATTR(remove_trigger, S_IWUSR, NULL, &iio_sysfs_trig_remove);
+
+static struct attribute *iio_sysfs_trig_attrs[] = {
+ &dev_attr_add_trigger.attr,
+ &dev_attr_remove_trigger.attr,
+ NULL,
+};
+
+static const struct attribute_group iio_sysfs_trig_group = {
+ .attrs = iio_sysfs_trig_attrs,
+};
+
+static const struct attribute_group *iio_sysfs_trig_groups[] = {
+ &iio_sysfs_trig_group,
+ NULL
+};
+
+static struct device iio_sysfs_trig_dev = {
+ .bus = &iio_bus_type,
+ .groups = iio_sysfs_trig_groups,
+};
+
static ssize_t iio_sysfs_trigger_poll(struct device *dev,
struct device_attribute *attr, const char *buf, size_t count)
{
struct iio_trigger *trig = dev_get_drvdata(dev);
- iio_trigger_poll(trig, 0);
+ iio_trigger_poll_chained(trig, 0);
return count;
}
static DEVICE_ATTR(trigger_now, S_IWUSR, NULL, iio_sysfs_trigger_poll);
-static IIO_TRIGGER_NAME_ATTR;
static struct attribute *iio_sysfs_trigger_attrs[] = {
&dev_attr_trigger_now.attr,
- &dev_attr_name.attr,
NULL,
};
@@ -35,70 +102,96 @@
.attrs = iio_sysfs_trigger_attrs,
};
-static int __devinit iio_sysfs_trigger_probe(struct platform_device *pdev)
-{
- struct iio_trigger *trig;
- int ret;
+static const struct attribute_group *iio_sysfs_trigger_attr_groups[] = {
+ &iio_sysfs_trigger_attr_group,
+ NULL
+};
- trig = iio_allocate_trigger();
- if (!trig) {
+static int iio_sysfs_trigger_probe(int id)
+{
+ struct iio_sysfs_trig *t;
+ int ret;
+ bool foundit = false;
+ mutex_lock(&iio_syfs_trig_list_mut);
+ list_for_each_entry(t, &iio_sysfs_trig_list, l)
+ if (id == t->id) {
+ foundit = true;
+ break;
+ }
+ if (foundit) {
+ ret = -EINVAL;
+ goto out1;
+ }
+ t = kmalloc(sizeof(*t), GFP_KERNEL);
+ if (t == NULL) {
ret = -ENOMEM;
goto out1;
}
-
- trig->control_attrs = &iio_sysfs_trigger_attr_group;
- trig->owner = THIS_MODULE;
- trig->name = kasprintf(GFP_KERNEL, "sysfstrig%d", pdev->id);
- if (trig->name == NULL) {
+ t->id = id;
+ t->trig = iio_allocate_trigger("sysfstrig%d", id);
+ if (!t->trig) {
ret = -ENOMEM;
- goto out2;
+ goto free_t;
}
- ret = iio_trigger_register(trig);
+ t->trig->dev.groups = iio_sysfs_trigger_attr_groups;
+ t->trig->owner = THIS_MODULE;
+ t->trig->dev.parent = &iio_sysfs_trig_dev;
+
+ ret = iio_trigger_register(t->trig);
if (ret)
- goto out3;
-
- platform_set_drvdata(pdev, trig);
-
+ goto out2;
+ list_add(&t->l, &iio_sysfs_trig_list);
+ __module_get(THIS_MODULE);
+ mutex_unlock(&iio_syfs_trig_list_mut);
return 0;
-out3:
- kfree(trig->name);
-out2:
- iio_put_trigger(trig);
-out1:
+out2:
+ iio_put_trigger(t->trig);
+free_t:
+ kfree(t);
+out1:
+ mutex_unlock(&iio_syfs_trig_list_mut);
return ret;
}
-static int __devexit iio_sysfs_trigger_remove(struct platform_device *pdev)
+static int iio_sysfs_trigger_remove(int id)
{
- struct iio_trigger *trig = platform_get_drvdata(pdev);
+ bool foundit = false;
+ struct iio_sysfs_trig *t;
+ mutex_lock(&iio_syfs_trig_list_mut);
+ list_for_each_entry(t, &iio_sysfs_trig_list, l)
+ if (id == t->id) {
+ foundit = true;
+ break;
+ }
+ if (!foundit) {
+ mutex_unlock(&iio_syfs_trig_list_mut);
+ return -EINVAL;
+ }
- iio_trigger_unregister(trig);
- kfree(trig->name);
- iio_put_trigger(trig);
+ iio_trigger_unregister(t->trig);
+ iio_free_trigger(t->trig);
+ list_del(&t->l);
+ kfree(t);
+ module_put(THIS_MODULE);
+ mutex_unlock(&iio_syfs_trig_list_mut);
return 0;
}
-static struct platform_driver iio_sysfs_trigger_driver = {
- .driver = {
- .name = "iio_sysfs_trigger",
- .owner = THIS_MODULE,
- },
- .probe = iio_sysfs_trigger_probe,
- .remove = __devexit_p(iio_sysfs_trigger_remove),
-};
static int __init iio_sysfs_trig_init(void)
{
- return platform_driver_register(&iio_sysfs_trigger_driver);
+ device_initialize(&iio_sysfs_trig_dev);
+ dev_set_name(&iio_sysfs_trig_dev, "iio_sysfs_trigger");
+ return device_add(&iio_sysfs_trig_dev);
}
module_init(iio_sysfs_trig_init);
static void __exit iio_sysfs_trig_exit(void)
{
- platform_driver_unregister(&iio_sysfs_trigger_driver);
+ device_unregister(&iio_sysfs_trig_dev);
}
module_exit(iio_sysfs_trig_exit);
diff --git a/drivers/staging/intel_sst/intel_sst.c b/drivers/staging/intel_sst/intel_sst.c
index 81c24d1..c0c144a 100644
--- a/drivers/staging/intel_sst/intel_sst.c
+++ b/drivers/staging/intel_sst/intel_sst.c
@@ -107,6 +107,9 @@
unsigned int size = 0, str_id;
struct stream_info *stream ;
+ /* Do not handle interrupt in suspended state */
+ if (drv->sst_state == SST_SUSPENDED)
+ return IRQ_NONE;
/* Interrupt arrived, check src */
isr.full = sst_shim_read(drv->shim, SST_ISRX);
@@ -316,14 +319,30 @@
if (sst_drv_ctx->pci_id == SST_MRST_PCI_ID) {
ret = misc_register(&lpe_dev);
if (ret) {
- pr_err("couldn't register misc driver\n");
+ pr_err("couldn't register LPE device\n");
goto do_free_misc;
}
+ } else if (sst_drv_ctx->pci_id == SST_MFLD_PCI_ID) {
+ u32 csr;
+
+ /*allocate mem for fw context save during suspend*/
+ sst_drv_ctx->fw_cntx = kzalloc(FW_CONTEXT_MEM, GFP_KERNEL);
+ if (!sst_drv_ctx->fw_cntx) {
+ ret = -ENOMEM;
+ goto do_free_misc;
+ }
+ /*setting zero as that is valid mem to restore*/
+ sst_drv_ctx->fw_cntx_size = 0;
+
+ /*set lpe start clock and ram size*/
+ csr = sst_shim_read(sst_drv_ctx->shim, SST_CSR);
+ csr |= 0x30060; /*remove the clock ratio after fw fix*/
+ sst_shim_write(sst_drv_ctx->shim, SST_CSR, csr);
}
sst_drv_ctx->lpe_stalled = 0;
- pm_runtime_set_active(&pci->dev);
- pm_runtime_enable(&pci->dev);
+ pci_set_drvdata(pci, sst_drv_ctx);
pm_runtime_allow(&pci->dev);
+ pm_runtime_put_noidle(&pci->dev);
pr_debug("...successfully done!!!\n");
return ret;
@@ -355,7 +374,8 @@
destroy_workqueue(sst_drv_ctx->mad_wq);
do_free_drv_ctx:
kfree(sst_drv_ctx);
- pr_err("Probe failed with 0x%x\n", ret);
+ sst_drv_ctx = NULL;
+ pr_err("Probe failed with %d\n", ret);
return ret;
}
@@ -369,35 +389,76 @@
*/
static void __devexit intel_sst_remove(struct pci_dev *pci)
{
+ pm_runtime_get_noresume(&pci->dev);
+ pm_runtime_forbid(&pci->dev);
pci_dev_put(sst_drv_ctx->pci);
mutex_lock(&sst_drv_ctx->sst_lock);
sst_drv_ctx->sst_state = SST_UN_INIT;
mutex_unlock(&sst_drv_ctx->sst_lock);
misc_deregister(&lpe_ctrl);
- if (sst_drv_ctx->pci_id == SST_MRST_PCI_ID)
- misc_deregister(&lpe_dev);
free_irq(pci->irq, sst_drv_ctx);
iounmap(sst_drv_ctx->dram);
iounmap(sst_drv_ctx->iram);
iounmap(sst_drv_ctx->mailbox);
iounmap(sst_drv_ctx->shim);
sst_drv_ctx->pmic_state = SND_MAD_UN_INIT;
- if (sst_drv_ctx->pci_id == SST_MRST_PCI_ID)
+ if (sst_drv_ctx->pci_id == SST_MRST_PCI_ID) {
+ misc_deregister(&lpe_dev);
kfree(sst_drv_ctx->mmap_mem);
+ } else
+ kfree(sst_drv_ctx->fw_cntx);
flush_scheduled_work();
destroy_workqueue(sst_drv_ctx->process_reply_wq);
destroy_workqueue(sst_drv_ctx->process_msg_wq);
destroy_workqueue(sst_drv_ctx->post_msg_wq);
destroy_workqueue(sst_drv_ctx->mad_wq);
- kfree(sst_drv_ctx);
- pci_release_region(pci, 1);
- pci_release_region(pci, 2);
- pci_release_region(pci, 3);
- pci_release_region(pci, 4);
- pci_release_region(pci, 5);
+ kfree(pci_get_drvdata(pci));
+ sst_drv_ctx = NULL;
+ pci_release_regions(pci);
+ pci_disable_device(pci);
pci_set_drvdata(pci, NULL);
}
+void sst_save_dsp_context(void)
+{
+ struct snd_sst_ctxt_params fw_context;
+ unsigned int pvt_id, i;
+ struct ipc_post *msg = NULL;
+
+ /*check cpu type*/
+ if (sst_drv_ctx->pci_id != SST_MFLD_PCI_ID)
+ return;
+ /*not supported for rest*/
+ if (sst_drv_ctx->sst_state != SST_FW_RUNNING) {
+ pr_debug("fw not running no context save ...\n");
+ return;
+ }
+
+ /*send msg to fw*/
+ if (sst_create_large_msg(&msg))
+ return;
+ pvt_id = sst_assign_pvt_id(sst_drv_ctx);
+ i = sst_get_block_stream(sst_drv_ctx);
+ sst_drv_ctx->alloc_block[i].sst_id = pvt_id;
+ sst_fill_header(&msg->header, IPC_IA_GET_FW_CTXT, 1, pvt_id);
+ msg->header.part.data = sizeof(fw_context) + sizeof(u32);
+ fw_context.address = virt_to_phys((void *)sst_drv_ctx->fw_cntx);
+ fw_context.size = FW_CONTEXT_MEM;
+ memcpy(msg->mailbox_data, &msg->header, sizeof(u32));
+ memcpy(msg->mailbox_data + sizeof(u32),
+ &fw_context, sizeof(fw_context));
+ spin_lock(&sst_drv_ctx->list_spin_lock);
+ list_add_tail(&msg->node, &sst_drv_ctx->ipc_dispatch_list);
+ spin_unlock(&sst_drv_ctx->list_spin_lock);
+ sst_post_message(&sst_drv_ctx->ipc_post_msg_wq);
+ /*wait for reply*/
+ if (sst_wait_timeout(sst_drv_ctx, &sst_drv_ctx->alloc_block[i]))
+ pr_debug("err fw context save timeout ...\n");
+ sst_drv_ctx->alloc_block[i].sst_id = BLOCK_UNINIT;
+ pr_debug("fw context saved ...\n");
+ return;
+}
+
/* Power Management */
/*
* intel_sst_suspend - PCI suspend function
@@ -417,6 +478,8 @@
pr_err("active streams,not able to suspend\n");
return -EBUSY;
}
+ /*save fw context*/
+ sst_save_dsp_context();
/*Assert RESET on LPE Processor*/
csr.full = sst_shim_read(sst_drv_ctx->shim, SST_CSR);
csr.full = csr.full | 0x2;
@@ -461,18 +524,45 @@
return 0;
}
+/* The runtime_suspend/resume is pretty much similar to the legacy suspend/resume with the noted exception below:
+ * The PCI core takes care of taking the system through D3hot and restoring it back to D0 and so there is
+ * no need to duplicate that here.
+ */
static int intel_sst_runtime_suspend(struct device *dev)
{
- struct pci_dev *pci_dev = to_pci_dev(dev);
- pr_debug("runtime_suspend called\n");
- return intel_sst_suspend(pci_dev, PMSG_SUSPEND);
+ union config_status_reg csr;
+
+ pr_debug("intel_sst_runtime_suspend called\n");
+ if (sst_drv_ctx->stream_cnt) {
+ pr_err("active streams,not able to suspend\n");
+ return -EBUSY;
+ }
+ /*save fw context*/
+ sst_save_dsp_context();
+ /*Assert RESET on LPE Processor*/
+ csr.full = sst_shim_read(sst_drv_ctx->shim, SST_CSR);
+ csr.full = csr.full | 0x2;
+ /* Move the SST state to Suspended */
+ mutex_lock(&sst_drv_ctx->sst_lock);
+ sst_drv_ctx->sst_state = SST_SUSPENDED;
+ sst_shim_write(sst_drv_ctx->shim, SST_CSR, csr.full);
+ mutex_unlock(&sst_drv_ctx->sst_lock);
+ return 0;
}
static int intel_sst_runtime_resume(struct device *dev)
{
- struct pci_dev *pci_dev = to_pci_dev(dev);
- pr_debug("runtime_resume called\n");
- return intel_sst_resume(pci_dev);
+
+ pr_debug("intel_sst_runtime_resume called\n");
+ if (sst_drv_ctx->sst_state != SST_SUSPENDED) {
+ pr_err("SST is not in suspended state\n");
+ return 0;
+ }
+
+ mutex_lock(&sst_drv_ctx->sst_lock);
+ sst_drv_ctx->sst_state = SST_UN_INIT;
+ mutex_unlock(&sst_drv_ctx->sst_lock);
+ return 0;
}
static int intel_sst_runtime_idle(struct device *dev)
@@ -545,6 +635,7 @@
pci_unregister_driver(&driver);
pr_debug("driver unloaded\n");
+ sst_drv_ctx = NULL;
return;
}
diff --git a/drivers/staging/intel_sst/intel_sst.h b/drivers/staging/intel_sst/intel_sst.h
index cb03ff7..4ad2829 100644
--- a/drivers/staging/intel_sst/intel_sst.h
+++ b/drivers/staging/intel_sst/intel_sst.h
@@ -30,9 +30,11 @@
* This file is shared between the SST and MAD drivers
*/
#include "intel_sst_ioctl.h"
+#include <sound/jack.h>
#define SST_CARD_NAMES "intel_mid_card"
+#define MFLD_MAX_HW_CH 4
/* control list Pmic & Lpe */
/* Input controls */
enum port_status {
@@ -82,12 +84,16 @@
int num_channel;
int input_dev_id;
int mute_status;
- int pb_on;
+ struct mutex lock;
+ int pb_on, pbhs_on;
int cap_on;
int output_dev_id;
+ int lineout_dev_id, line_out_names_cnt;
+ int prev_lineout_dev_id;
+ bool jack_interrupt_status;
int (*set_input_dev) (u8 value);
int (*set_output_dev) (u8 value);
-
+ int (*set_lineout_dev) (u8 value);
int (*set_mute) (int dev_id, u8 value);
int (*get_mute) (int dev_id, u8 *value);
@@ -103,11 +109,30 @@
int (*power_up_pmic_pb) (unsigned int port);
int (*power_up_pmic_cp) (unsigned int port);
- int (*power_down_pmic_pb) (void);
- int (*power_down_pmic_cp) (void);
+ int (*power_down_pmic_pb) (unsigned int device);
+ int (*power_down_pmic_cp) (unsigned int device);
int (*power_down_pmic) (void);
+ void (*pmic_irq_cb) (void *cb_data, u8 value);
+ void (*pmic_irq_enable)(void *data);
+ int (*pmic_jack_enable) (void);
+ int (*pmic_get_mic_bias)(void *intelmaddata);
+ int (*pmic_set_headset_state)(int state);
+
+ unsigned int hw_dmic_map[MFLD_MAX_HW_CH];
+ unsigned int available_dmics;
+ int (*set_hw_dmic_route) (u8 index);
+
+ int gpio_amp;
};
+extern void sst_mad_send_jack_report(struct snd_jack *jack,
+ int buttonpressevent,
+ int status);
+
+
+int intemad_set_headset_state(int state);
+int intelmad_get_mic_bias(void);
+
struct intel_sst_pcm_control {
int (*open) (struct snd_sst_params *str_param);
int (*device_control) (int cmd, void *arg);
diff --git a/drivers/staging/intel_sst/intel_sst_app_interface.c b/drivers/staging/intel_sst/intel_sst_app_interface.c
index 1d06212..b8c7ddb 100644
--- a/drivers/staging/intel_sst/intel_sst_app_interface.c
+++ b/drivers/staging/intel_sst/intel_sst_app_interface.c
@@ -418,10 +418,6 @@
static int sent_offset;
static unsigned long sent_index;
- stream_bufs = kzalloc(sizeof(*stream_bufs), GFP_KERNEL);
- if (!stream_bufs)
- return -ENOMEM;
- stream_bufs->addr = sst_drv_ctx->mmap_mem;
#ifdef CONFIG_MRST_RAR_HANDLER
if (stream->ops == STREAM_OPS_PLAYBACK_DRM) {
for (index = stream->sg_index; index < nr_segs; index++) {
@@ -448,6 +444,10 @@
return retval;
}
#endif
+ stream_bufs = kzalloc(sizeof(*stream_bufs), GFP_KERNEL);
+ if (!stream_bufs)
+ return -ENOMEM;
+ stream_bufs->addr = sst_drv_ctx->mmap_mem;
mmap_len = sst_drv_ctx->mmap_len;
stream_bufs->addr = sst_drv_ctx->mmap_mem;
bufp = stream->cur_ptr;
@@ -961,6 +961,34 @@
return retval;
}
+
+int sst_ioctl_tuning_params(unsigned long arg)
+{
+ struct snd_sst_tuning_params params;
+ struct ipc_post *msg;
+
+ if (copy_from_user(¶ms, (void __user *)arg, sizeof(params)))
+ return -EFAULT;
+ if (params.size > SST_MAILBOX_SIZE)
+ return -ENOMEM;
+ pr_debug("Parameter %d, Stream %d, Size %d\n", params.type,
+ params.str_id, params.size);
+ if (sst_create_large_msg(&msg))
+ return -ENOMEM;
+
+ sst_fill_header(&msg->header, IPC_IA_TUNING_PARAMS, 1, params.str_id);
+ msg->header.part.data = sizeof(u32) + sizeof(params) + params.size;
+ memcpy(msg->mailbox_data, &msg->header.full, sizeof(u32));
+ memcpy(msg->mailbox_data + sizeof(u32), ¶ms, sizeof(params));
+ if (copy_from_user(msg->mailbox_data + sizeof(params),
+ (void __user *)(unsigned long)params.addr,
+ params.size)) {
+ kfree(msg->mailbox_data);
+ kfree(msg);
+ return -EFAULT;
+ }
+ return sst_send_algo_ipc(&msg);
+}
/**
* intel_sst_ioctl - receives the device ioctl's
* @file_ptr:pointer to file
@@ -1412,6 +1440,15 @@
}
retval = intel_sst_ioctl_dsp(cmd, arg);
break;
+
+ case _IOC_NR(SNDRV_SST_TUNING_PARAMS):
+ if (minor != AM_MODULE) {
+ retval = -EBADRQC;
+ break;
+ }
+ retval = sst_ioctl_tuning_params(arg);
+ break;
+
default:
retval = -EINVAL;
}
diff --git a/drivers/staging/intel_sst/intel_sst_common.h b/drivers/staging/intel_sst/intel_sst_common.h
index 0a60e86..f8e9da6 100644
--- a/drivers/staging/intel_sst/intel_sst_common.h
+++ b/drivers/staging/intel_sst/intel_sst_common.h
@@ -28,8 +28,8 @@
* Common private declarations for SST
*/
-#define SST_DRIVER_VERSION "1.2.09"
-#define SST_VERSION_NUM 0x1209
+#define SST_DRIVER_VERSION "1.2.17"
+#define SST_VERSION_NUM 0x1217
/* driver names */
#define SST_DRV_NAME "intel_sst_driver"
@@ -37,6 +37,7 @@
#define SST_MFLD_PCI_ID 0x082F
#define PCI_ID_LENGTH 4
#define SST_SUSPEND_DELAY 2000
+#define FW_CONTEXT_MEM (64*1024)
enum sst_states {
SST_FW_LOADED = 1,
@@ -94,7 +95,7 @@
/* SST shim registers to structure mapping */
union config_status_reg {
struct {
- u32 rsvd0:1;
+ u32 mfld_strb:1;
u32 sst_reset:1;
u32 hw_rsvd:3;
u32 sst_clk:2;
@@ -417,6 +418,8 @@
unsigned int audio_start;
dev_t devt_d, devt_c;
unsigned int max_streams;
+ unsigned int *fw_cntx;
+ unsigned int fw_cntx_size;
};
extern struct intel_sst_drv *sst_drv_ctx;
diff --git a/drivers/staging/intel_sst/intel_sst_drv_interface.c b/drivers/staging/intel_sst/intel_sst_drv_interface.c
index 971588c..1021477 100644
--- a/drivers/staging/intel_sst/intel_sst_drv_interface.c
+++ b/drivers/staging/intel_sst/intel_sst_drv_interface.c
@@ -105,21 +105,28 @@
if (!sst_validate_strid(str_id)) {
/* str_id is valid, so stream is alloacted */
stream = &sst_drv_ctx->streams[str_id];
+ if (sst_free_stream(str_id))
+ sst_clean_stream(&sst_drv_ctx->streams[str_id]);
if (stream->ops == STREAM_OPS_PLAYBACK ||
stream->ops == STREAM_OPS_PLAYBACK_DRM) {
sst_drv_ctx->pb_streams--;
- if (sst_drv_ctx->pb_streams == 0)
- sst_drv_ctx->scard_ops->power_down_pmic_pb();
+ if (sst_drv_ctx->pci_id == SST_MFLD_PCI_ID)
+ sst_drv_ctx->scard_ops->power_down_pmic_pb(
+ stream->device);
+ else {
+ if (sst_drv_ctx->pb_streams == 0)
+ sst_drv_ctx->scard_ops->
+ power_down_pmic_pb(stream->device);
+ }
} else if (stream->ops == STREAM_OPS_CAPTURE) {
sst_drv_ctx->cp_streams--;
if (sst_drv_ctx->cp_streams == 0)
- sst_drv_ctx->scard_ops->power_down_pmic_cp();
+ sst_drv_ctx->scard_ops->power_down_pmic_cp(
+ stream->device);
}
if (sst_drv_ctx->pb_streams == 0
&& sst_drv_ctx->cp_streams == 0)
sst_drv_ctx->scard_ops->power_down_pmic();
- if (sst_free_stream(str_id))
- sst_clean_stream(&sst_drv_ctx->streams[str_id]);
}
}
@@ -276,8 +283,8 @@
retval = sst_resume_stream(mad_ops->stream_id);
break;
case SST_SND_DROP:
-/* retval = sst_drop_stream(mad_ops->stream_id);
-*/ break;
+ retval = sst_drop_stream(mad_ops->stream_id);
+ break;
case SST_SND_START:
pr_debug("SST Debug: start stream\n");
retval = sst_start_stream(mad_ops->stream_id);
@@ -519,6 +526,9 @@
pr_err("Repeat for registration..denied\n");
return -EBADRQC;
}
+ /* The ASoC code doesn't set scard_ops */
+ if (sst_drv_ctx->scard_ops)
+ sst_drv_ctx->scard_ops->card_status = SND_CARD_UN_INIT;
return 0;
}
EXPORT_SYMBOL_GPL(register_sst_card);
diff --git a/drivers/staging/intel_sst/intel_sst_dsp.c b/drivers/staging/intel_sst/intel_sst_dsp.c
index bffe4c6..a89e1ad 100644
--- a/drivers/staging/intel_sst/intel_sst_dsp.c
+++ b/drivers/staging/intel_sst/intel_sst_dsp.c
@@ -73,7 +73,8 @@
union config_status_reg csr;
pr_debug("Resetting the DSP in medfield\n");
- csr.full = 0x048303E2;
+ csr.full = sst_shim_read(sst_drv_ctx->shim, SST_CSR);
+ csr.full |= 0x382;
sst_shim_write(sst_drv_ctx->shim, SST_CSR, csr.full);
return 0;
@@ -109,11 +110,16 @@
{
union config_status_reg csr;
- csr.full = 0x04830062;
+ csr.full = sst_shim_read(sst_drv_ctx->shim, SST_CSR);
+ csr.part.bypass = 0;
sst_shim_write(sst_drv_ctx->shim, SST_CSR, csr.full);
- csr.full = 0x04830063;
+ csr.full = sst_shim_read(sst_drv_ctx->shim, SST_CSR);
+ csr.part.mfld_strb = 1;
sst_shim_write(sst_drv_ctx->shim, SST_CSR, csr.full);
- csr.full = 0x04830061;
+ csr.full = sst_shim_read(sst_drv_ctx->shim, SST_CSR);
+ csr.part.run_stall = 0;
+ csr.part.sst_reset = 0;
+ pr_debug("Starting the DSP_medfld %x\n", csr.full);
sst_shim_write(sst_drv_ctx->shim, SST_CSR, csr.full);
pr_debug("Starting the DSP_medfld\n");
diff --git a/drivers/staging/intel_sst/intel_sst_fw_ipc.h b/drivers/staging/intel_sst/intel_sst_fw_ipc.h
index 0f0c5bb..5d0cc56 100644
--- a/drivers/staging/intel_sst/intel_sst_fw_ipc.h
+++ b/drivers/staging/intel_sst/intel_sst_fw_ipc.h
@@ -56,6 +56,8 @@
#define IPC_IA_GET_FW_VERSION 0x04
#define IPC_IA_GET_FW_BUILD_INF 0x05
#define IPC_IA_GET_FW_INFO 0x06
+#define IPC_IA_GET_FW_CTXT 0x07
+#define IPC_IA_SET_FW_CTXT 0x08
/* I2L Codec Config/control msgs */
#define IPC_IA_SET_CODEC_PARAMS 0x10
@@ -69,6 +71,7 @@
#define IPC_IA_DECODE_FRAMES 0x18
#define IPC_IA_ALG_PARAMS 0x1A
+#define IPC_IA_TUNING_PARAMS 0x1B
/* I2L Stream config/control msgs */
#define IPC_IA_ALLOC_STREAM 0x20 /* Allocate a stream ID */
@@ -406,4 +409,8 @@
char *mailbox_data;
};
+struct snd_sst_ctxt_params {
+ u32 address; /* Physical Address in DDR where the context is stored */
+ u32 size; /* size of the context */
+};
#endif /* __INTEL_SST_FW_IPC_H__ */
diff --git a/drivers/staging/intel_sst/intel_sst_ioctl.h b/drivers/staging/intel_sst/intel_sst_ioctl.h
index bebc395..5da5ee0 100644
--- a/drivers/staging/intel_sst/intel_sst_ioctl.h
+++ b/drivers/staging/intel_sst/intel_sst_ioctl.h
@@ -400,6 +400,13 @@
struct snd_sst_buffs *obufs;
};
+struct snd_sst_tuning_params {
+ __u8 type;
+ __u8 str_id;
+ __u8 size;
+ __u8 rsvd;
+ __aligned_u64 addr;
+} __attribute__ ((packed));
/*IOCTL defined here */
/*SST MMF IOCTLS only */
#define SNDRV_SST_STREAM_SET_PARAMS _IOR('L', 0x00, \
@@ -428,5 +435,6 @@
/*DSP Ioctls on /dev/intel_sst_ctrl only*/
#define SNDRV_SST_SET_ALGO _IOW('L', 0x30, struct snd_ppp_params *)
#define SNDRV_SST_GET_ALGO _IOWR('L', 0x31, struct snd_ppp_params *)
+#define SNDRV_SST_TUNING_PARAMS _IOW('L', 0x32, struct snd_sst_tuning_params *)
#endif /* __INTEL_SST_IOCTL_H__ */
diff --git a/drivers/staging/intel_sst/intel_sst_ipc.c b/drivers/staging/intel_sst/intel_sst_ipc.c
index 0742dde..5c3444f 100644
--- a/drivers/staging/intel_sst/intel_sst_ipc.c
+++ b/drivers/staging/intel_sst/intel_sst_ipc.c
@@ -154,6 +154,37 @@
sst_shim_write(sst_drv_ctx->shim, SST_IMRX, imr.full);
}
+void sst_restore_fw_context(void)
+{
+ struct snd_sst_ctxt_params fw_context;
+ struct ipc_post *msg = NULL;
+
+ pr_debug("restore_fw_context\n");
+ /*check cpu type*/
+ if (sst_drv_ctx->pci_id != SST_MFLD_PCI_ID)
+ return;
+ /*not supported for rest*/
+ if (!sst_drv_ctx->fw_cntx_size)
+ return;
+ /*nothing to restore*/
+ pr_debug("restoring context......\n");
+ /*send msg to fw*/
+ if (sst_create_large_msg(&msg))
+ return;
+
+ sst_fill_header(&msg->header, IPC_IA_SET_FW_CTXT, 1, 0);
+ msg->header.part.data = sizeof(fw_context) + sizeof(u32);
+ fw_context.address = virt_to_phys((void *)sst_drv_ctx->fw_cntx);
+ fw_context.size = sst_drv_ctx->fw_cntx_size;
+ memcpy(msg->mailbox_data, &msg->header, sizeof(u32));
+ memcpy(msg->mailbox_data + sizeof(u32),
+ &fw_context, sizeof(fw_context));
+ spin_lock(&sst_drv_ctx->list_spin_lock);
+ list_add_tail(&msg->node, &sst_drv_ctx->ipc_dispatch_list);
+ spin_unlock(&sst_drv_ctx->list_spin_lock);
+ sst_post_message(&sst_drv_ctx->ipc_post_msg_wq);
+ return;
+}
/*
* process_fw_init - process the FW init msg
*
@@ -184,13 +215,13 @@
sst_drv_ctx->sst_state = SST_FW_RUNNING;
sst_drv_ctx->lpe_stalled = 0;
mutex_unlock(&sst_drv_ctx->sst_lock);
- pr_debug("FW Version %x.%x\n",
- init->fw_version.major, init->fw_version.minor);
- pr_debug("Build No %x Type %x\n",
- init->fw_version.build, init->fw_version.type);
+ pr_debug("FW Version %02x.%02x.%02x\n", init->fw_version.major,
+ init->fw_version.minor, init->fw_version.build);
+ pr_debug("Build Type %x\n", init->fw_version.type);
pr_debug(" Build date %s Time %s\n",
init->build_info.date, init->build_info.time);
sst_wake_up_alloc_block(sst_drv_ctx, FW_DWNL_ID, retval, NULL);
+ sst_restore_fw_context();
return retval;
}
/**
@@ -385,6 +416,24 @@
}
break;
}
+
+ case IPC_IA_TUNING_PARAMS: {
+ pr_debug("sst:IPC_TUNING_PARAMS resp: %x\n", msg->header.full);
+ pr_debug("data value %x\n", msg->header.part.data);
+ if (msg->header.part.large) {
+ pr_debug("alg set failed\n");
+ sst_drv_ctx->ppp_params_blk.ret_code =
+ -msg->header.part.data;
+ } else {
+ pr_debug("alg set success\n");
+ sst_drv_ctx->ppp_params_blk.ret_code = 0;
+ }
+ if (sst_drv_ctx->ppp_params_blk.on == true) {
+ sst_drv_ctx->ppp_params_blk.condition = true;
+ wake_up(&sst_drv_ctx->wait_queue);
+ }
+ }
+
case IPC_IA_GET_FW_INFO: {
struct snd_sst_fw_info *fw_info =
(struct snd_sst_fw_info *)msg->mailbox;
@@ -615,12 +664,18 @@
break;
case IPC_IA_FREE_STREAM:
+ str_info = &sst_drv_ctx->streams[str_id];
if (!msg->header.part.data) {
pr_debug("Stream %d freed\n", str_id);
} else {
pr_err("Free for %d ret error %x\n",
str_id, msg->header.part.data);
}
+ if (str_info->ctrl_blk.on == true) {
+ str_info->ctrl_blk.on = false;
+ str_info->ctrl_blk.condition = true;
+ wake_up(&sst_drv_ctx->wait_queue);
+ }
break;
case IPC_IA_ALLOC_STREAM: {
/* map to stream, call play */
@@ -699,6 +754,17 @@
case IPC_IA_START_STREAM:
pr_debug("reply for START STREAM %x\n", msg->header.full);
break;
+
+ case IPC_IA_GET_FW_CTXT:
+ pr_debug("reply for get fw ctxt %x\n", msg->header.full);
+ if (msg->header.part.data)
+ sst_drv_ctx->fw_cntx_size = 0;
+ else
+ sst_drv_ctx->fw_cntx_size = *sst_drv_ctx->fw_cntx;
+ pr_debug("fw copied data %x\n", sst_drv_ctx->fw_cntx_size);
+ sst_wake_up_alloc_block(
+ sst_drv_ctx, str_id, msg->header.part.data, NULL);
+ break;
default:
/* Illegal case */
pr_err("process reply:default = %x\n", msg->header.full);
diff --git a/drivers/staging/intel_sst/intel_sst_pvt.c b/drivers/staging/intel_sst/intel_sst_pvt.c
index 01f8c3b..e034bea 100644
--- a/drivers/staging/intel_sst/intel_sst_pvt.c
+++ b/drivers/staging/intel_sst/intel_sst_pvt.c
@@ -203,7 +203,7 @@
kfree(msg);
pr_err("kzalloc mailbox_data failed");
return -ENOMEM;
- };
+ }
*arg = msg;
return 0;
}
diff --git a/drivers/staging/intel_sst/intel_sst_stream.c b/drivers/staging/intel_sst/intel_sst_stream.c
index dd58be5..be4565e 100644
--- a/drivers/staging/intel_sst/intel_sst_stream.c
+++ b/drivers/staging/intel_sst/intel_sst_stream.c
@@ -31,6 +31,7 @@
#include <linux/pci.h>
#include <linux/firmware.h>
#include <linux/sched.h>
+#include <linux/delay.h>
#include "intel_sst_ioctl.h"
#include "intel_sst.h"
#include "intel_sst_fw_ipc.h"
@@ -47,7 +48,7 @@
*/
int sst_check_device_type(u32 device, u32 num_chan, u32 *pcm_slot)
{
- if (device > MAX_NUM_STREAMS_MFLD) {
+ if (device >= MAX_NUM_STREAMS_MFLD) {
pr_debug("device type invalid %d\n", device);
return -EINVAL;
}
@@ -72,6 +73,8 @@
*pcm_slot = 0x07;
else if (device == SND_SST_DEVICE_CAPTURE && num_chan == 4)
*pcm_slot = 0x0F;
+ else if (device == SND_SST_DEVICE_CAPTURE && num_chan > 4)
+ *pcm_slot = 0x1F;
else {
pr_debug("No condition satisfied.. ret err\n");
return -EINVAL;
@@ -519,10 +522,6 @@
str_info->data_blk.on = true;
retval = sst_wait_interruptible(sst_drv_ctx, &str_info->data_blk);
str_info->need_draining = false;
- if (retval == -SST_ERR_INVALID_STREAM_ID) {
- retval = -EINVAL;
- sst_clean_stream(str_info);
- }
return retval;
}
@@ -563,6 +562,12 @@
str_info->data_blk.ret_code = 0;
wake_up(&sst_drv_ctx->wait_queue);
}
+ str_info->data_blk.on = true;
+ str_info->data_blk.condition = false;
+ retval = sst_wait_interruptible_timeout(sst_drv_ctx,
+ &str_info->ctrl_blk, SST_BLOCK_TIMEOUT);
+ pr_debug("wait for free returned %d\n", retval);
+ msleep(100);
mutex_lock(&sst_drv_ctx->stream_lock);
sst_clean_stream(str_info);
mutex_unlock(&sst_drv_ctx->stream_lock);
diff --git a/drivers/staging/intel_sst/intel_sst_stream_encoded.c b/drivers/staging/intel_sst/intel_sst_stream_encoded.c
index d5f07b8..2be58c5 100644
--- a/drivers/staging/intel_sst/intel_sst_stream_encoded.c
+++ b/drivers/staging/intel_sst/intel_sst_stream_encoded.c
@@ -363,7 +363,6 @@
pr_err("SST_Activate_target_fail\n");
else
pr_err("SST_Activate_target_pass\n");
- return retval;
} else if (slot->action == SND_SST_PORT_PREPARE &&
slot->device_type == SND_SST_DEVICE_PCM) {
retval = sst_prepare_target(slot);
@@ -371,12 +370,11 @@
pr_err("SST_prepare_target_fail\n");
else
pr_err("SST_prepare_target_pass\n");
- return retval;
} else {
pr_err("slot_action : %d, device_type: %d\n",
slot->action, slot->device_type);
- return retval;
}
+ return retval;
}
int sst_send_target(struct snd_sst_target_device *target)
@@ -886,8 +884,7 @@
int *input_index, int *in_copied,
int *input_index_valid_size, int *new_entry_flag)
{
- int retval = 0;
- int i;
+ int retval = 0, i;
if (str_info->ops == STREAM_OPS_PLAYBACK_DRM) {
struct RAR_buffer rar_buffers;
@@ -924,7 +921,6 @@
return retval;
}
#endif
-
/*This function is used to prepare the kernel input buffers with contents
before sending for decode*/
static int sst_prepare_input_buffers(struct stream_info *str_info,
diff --git a/drivers/staging/intel_sst/intelmid.c b/drivers/staging/intel_sst/intelmid.c
index ebb6d03..25656ad 100644
--- a/drivers/staging/intel_sst/intelmid.c
+++ b/drivers/staging/intel_sst/intelmid.c
@@ -33,17 +33,20 @@
#include <linux/interrupt.h>
#include <linux/sched.h>
#include <linux/firmware.h>
+#include <linux/input.h>
#include <sound/control.h>
#include <asm/mrst.h>
#include <sound/pcm.h>
-#include "jack.h"
+#include <sound/jack.h>
#include <sound/pcm_params.h>
#include <sound/initval.h>
+#include <linux/gpio.h>
#include "intel_sst.h"
#include "intel_sst_ioctl.h"
#include "intel_sst_fw_ipc.h"
#include "intel_sst_common.h"
#include "intelmid_snd_control.h"
+#include "intelmid_adc_control.h"
#include "intelmid.h"
MODULE_AUTHOR("Vinod Koul <vinod.koul@intel.com>");
@@ -65,7 +68,14 @@
int sst_card_vendor_id;
int intelmid_audio_interrupt_enable;/*checkpatch fix*/
+struct snd_intelmad *intelmad_drv;
+#define INFO(_cpu_id, _irq_cache, _size) \
+ ((kernel_ulong_t)&(struct snd_intelmad_probe_info) { \
+ .cpu_id = (_cpu_id), \
+ .irq_cache = (_irq_cache), \
+ .size = (_size), \
+ })
/* Data path functionalities */
static struct snd_pcm_hardware snd_intelmad_stream = {
.info = (SNDRV_PCM_INFO_INTERLEAVED |
@@ -187,7 +197,7 @@
return ret_val;
}
- ret_val = snd_intelmad_alloc_stream(substream);
+ ret_val = snd_intelmad_alloc_stream(substream);
if (ret_val < 0)
return ret_val;
stream->dbg_cum_bytes = 0;
@@ -326,6 +336,16 @@
runtime = substream->runtime;
/* set the runtime hw parameter with local snd_pcm_hardware struct */
runtime->hw = snd_intelmad_stream;
+ if (intelmaddata->cpu_id == CPU_CHIP_LINCROFT) {
+ /*
+ * MRST firmware currently denies stereo recording requests.
+ */
+ if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
+ runtime->hw.formats = (SNDRV_PCM_FMTBIT_S16 |
+ SNDRV_PCM_FMTBIT_U16);
+ runtime->hw.channels_max = 1;
+ }
+ }
if (intelmaddata->cpu_id == CPU_CHIP_PENWELL) {
runtime->hw = snd_intelmad_stream;
runtime->hw.rates = SNDRV_PCM_RATE_48000;
@@ -426,7 +446,55 @@
.pointer = snd_intelmad_pcm_pointer,
};
+int intelmad_get_mic_bias(void)
+{
+ struct snd_pmic_ops *pmic_ops;
+ if (!intelmad_drv || !intelmad_drv->sstdrv_ops)
+ return -ENODEV;
+ pmic_ops = intelmad_drv->sstdrv_ops->scard_ops;
+ if (pmic_ops && pmic_ops->pmic_get_mic_bias)
+ return pmic_ops->pmic_get_mic_bias(intelmad_drv);
+ else
+ return -ENODEV;
+}
+EXPORT_SYMBOL_GPL(intelmad_get_mic_bias);
+
+int intelmad_set_headset_state(int state)
+{
+ struct snd_pmic_ops *pmic_ops;
+
+ if (!intelmad_drv || !intelmad_drv->sstdrv_ops)
+ return -ENODEV;
+ pmic_ops = intelmad_drv->sstdrv_ops->scard_ops;
+ if (pmic_ops && pmic_ops->pmic_set_headset_state)
+ return pmic_ops->pmic_set_headset_state(state);
+ else
+ return -ENODEV;
+}
+EXPORT_SYMBOL_GPL(intelmad_set_headset_state);
+
+void sst_process_mad_jack_detection(struct work_struct *work)
+{
+ u8 interrupt_status;
+ struct mad_jack_msg_wq *mad_jack_detect =
+ container_of(work, struct mad_jack_msg_wq, wq);
+
+ struct snd_intelmad *intelmaddata =
+ mad_jack_detect->intelmaddata;
+
+ if (!intelmaddata)
+ return;
+
+ interrupt_status = mad_jack_detect->intsts;
+ if (intelmaddata->sstdrv_ops && intelmaddata->sstdrv_ops->scard_ops
+ && intelmaddata->sstdrv_ops->scard_ops->pmic_irq_cb) {
+ intelmaddata->sstdrv_ops->scard_ops->pmic_irq_cb(
+ (void *)intelmaddata, interrupt_status);
+ intelmaddata->sstdrv_ops->scard_ops->pmic_jack_enable();
+ }
+ kfree(mad_jack_detect);
+}
/**
* snd_intelmad_intr_handler- interrupt handler
*
@@ -439,15 +507,17 @@
{
struct snd_intelmad *intelmaddata =
(struct snd_intelmad *)dev;
- u8 intsts;
-
- memcpy_fromio(&intsts,
+ u8 interrupt_status;
+ struct mad_jack_msg_wq *mad_jack_msg;
+ memcpy_fromio(&interrupt_status,
((void *)(intelmaddata->int_base)),
sizeof(u8));
- intelmaddata->mad_jack_msg.intsts = intsts;
- intelmaddata->mad_jack_msg.intelmaddata = intelmaddata;
- queue_work(intelmaddata->mad_jack_wq, &intelmaddata->mad_jack_msg.wq);
+ mad_jack_msg = kzalloc(sizeof(*mad_jack_msg), GFP_ATOMIC);
+ mad_jack_msg->intsts = interrupt_status;
+ mad_jack_msg->intelmaddata = intelmaddata;
+ INIT_WORK(&mad_jack_msg->wq, sst_process_mad_jack_detection);
+ queue_work(intelmaddata->mad_jack_wq, &mad_jack_msg->wq);
return IRQ_HANDLED;
}
@@ -460,286 +530,22 @@
pr_debug("MAD error jack empty\n");
} else {
- pr_debug("MAD send jack report for = %d!!!\n", status);
- pr_debug("MAD send jack report %d\n", jack->type);
snd_jack_report(jack, status);
-
- /*button pressed and released */
+ /* button pressed and released */
if (buttonpressevent)
snd_jack_report(jack, 0);
pr_debug("MAD sending jack report Done !!!\n");
}
-
-
-
}
-void sst_mad_jackdetection_fs(u8 intsts , struct snd_intelmad *intelmaddata)
-{
- struct snd_jack *jack = NULL;
- unsigned int present = 0, jack_event_flag = 0, buttonpressflag = 0;
- struct sc_reg_access sc_access[] = {
- {0x187, 0x00, MASK7},
- {0x188, 0x10, MASK4},
- {0x18b, 0x10, MASK4},
- };
-
- struct sc_reg_access sc_access_write[] = {
- {0x198, 0x00, 0x0},
- };
-
- if (intsts & 0x4) {
-
- if (!(intelmid_audio_interrupt_enable)) {
- pr_debug("Audio interrupt enable\n");
- sst_sc_reg_access(sc_access, PMIC_READ_MODIFY, 3);
-
- sst_sc_reg_access(sc_access_write, PMIC_WRITE, 1);
- intelmid_audio_interrupt_enable = 1;
- intelmaddata->jack[0].jack_status = 0;
- intelmaddata->jack[1].jack_status = 0;
-
- }
- /* send headphone detect */
- pr_debug("MAD headphone %d\n", intsts & 0x4);
- jack = &intelmaddata->jack[0].jack;
- present = !(intelmaddata->jack[0].jack_status);
- intelmaddata->jack[0].jack_status = present;
- jack_event_flag = 1;
-
- }
-
- if (intsts & 0x2) {
- /* send short push */
- pr_debug("MAD short push %d\n", intsts & 0x2);
- jack = &intelmaddata->jack[2].jack;
- present = 1;
- jack_event_flag = 1;
- buttonpressflag = 1;
- }
- if (intsts & 0x1) {
- /* send long push */
- pr_debug("MAD long push %d\n", intsts & 0x1);
- jack = &intelmaddata->jack[3].jack;
- present = 1;
- jack_event_flag = 1;
- buttonpressflag = 1;
- }
- if (intsts & 0x8) {
- if (!(intelmid_audio_interrupt_enable)) {
- pr_debug("Audio interrupt enable\n");
- sst_sc_reg_access(sc_access, PMIC_READ_MODIFY, 3);
-
- sst_sc_reg_access(sc_access_write, PMIC_WRITE, 1);
- intelmid_audio_interrupt_enable = 1;
- intelmaddata->jack[0].jack_status = 0;
- intelmaddata->jack[1].jack_status = 0;
- }
- /* send headset detect */
- pr_debug("MAD headset = %d\n", intsts & 0x8);
- jack = &intelmaddata->jack[1].jack;
- present = !(intelmaddata->jack[1].jack_status);
- intelmaddata->jack[1].jack_status = present;
- jack_event_flag = 1;
- }
-
- if (jack_event_flag)
- sst_mad_send_jack_report(jack, buttonpressflag, present);
-}
-
-
-void sst_mad_jackdetection_mx(u8 intsts, struct snd_intelmad *intelmaddata)
-{
- u8 value = 0, jack_prev_state = 0;
- struct snd_jack *jack = NULL;
- unsigned int present = 0, jack_event_flag = 0, buttonpressflag = 0;
- time_t timediff;
- struct sc_reg_access sc_access_read = {0,};
- struct snd_pmic_ops *scard_ops;
-
- scard_ops = intelmaddata->sstdrv_ops->scard_ops;
-
- pr_debug("previous value: %x\n", intelmaddata->jack_prev_state);
-
- if (!(intelmid_audio_interrupt_enable)) {
- pr_debug("Audio interrupt enable\n");
- intelmaddata->jack_prev_state = 0xC0;
- intelmid_audio_interrupt_enable = 1;
- }
-
- if (intsts & 0x2) {
- jack_prev_state = intelmaddata->jack_prev_state;
- if (intelmaddata->pmic_status == PMIC_INIT) {
- sc_access_read.reg_addr = 0x201;
- sst_sc_reg_access(&sc_access_read, PMIC_READ, 1);
- value = (sc_access_read.value);
- pr_debug("value returned = 0x%x\n", value);
- }
-
- if (jack_prev_state == 0xc0 && value == 0x40) {
- /*headset detected. */
- pr_debug("MAD headset inserted\n");
- jack = &intelmaddata->jack[1].jack;
- present = 1;
- jack_event_flag = 1;
- intelmaddata->jack[1].jack_status = 1;
-
- }
-
- if (jack_prev_state == 0xc0 && value == 0x00) {
- /* headphone detected. */
- pr_debug("MAD headphone inserted\n");
- jack = &intelmaddata->jack[0].jack;
- present = 1;
- jack_event_flag = 1;
-
- }
-
- if (jack_prev_state == 0x40 && value == 0xc0) {
- /*headset removed*/
- pr_debug("Jack headset status %d\n",
- intelmaddata->jack[1].jack_status);
- pr_debug("MAD headset removed\n");
- jack = &intelmaddata->jack[1].jack;
- present = 0;
- jack_event_flag = 1;
- intelmaddata->jack[1].jack_status = 0;
- }
-
- if (jack_prev_state == 0x00 && value == 0xc0) {
- /* headphone detected. */
- pr_debug("Jack headphone status %d\n",
- intelmaddata->jack[0].jack_status);
- pr_debug("headphone removed\n");
- jack = &intelmaddata->jack[0].jack;
- present = 0;
- jack_event_flag = 1;
- }
-
- if (jack_prev_state == 0x40 && value == 0x00) {
- /*button pressed*/
- do_gettimeofday(&intelmaddata->jack[1].buttonpressed);
- pr_debug("MAD button press detected\n");
- }
-
-
- if (jack_prev_state == 0x00 && value == 0x40) {
- if (intelmaddata->jack[1].jack_status) {
- /*button pressed*/
- do_gettimeofday(
- &intelmaddata->jack[1].buttonreleased);
- /*button pressed */
- pr_debug("Button Released detected\n");
- timediff = intelmaddata->jack[1].
- buttonreleased.tv_sec - intelmaddata->
- jack[1].buttonpressed.tv_sec;
- buttonpressflag = 1;
- if (timediff > 1) {
- pr_debug("long press detected\n");
- /* send headphone detect/undetect */
- jack = &intelmaddata->jack[3].jack;
- present = 1;
- jack_event_flag = 1;
- } else {
- pr_debug("short press detected\n");
- /* send headphone detect/undetect */
- jack = &intelmaddata->jack[2].jack;
- present = 1;
- jack_event_flag = 1;
- }
- }
-
- }
- intelmaddata->jack_prev_state = value;
- }
- if (jack_event_flag)
- sst_mad_send_jack_report(jack, buttonpressflag, present);
-}
-
-
-void sst_mad_jackdetection_nec(u8 intsts, struct snd_intelmad *intelmaddata)
-{
- u8 value = 0;
- struct snd_jack *jack = NULL;
- unsigned int present = 0, jack_event_flag = 0, buttonpressflag = 0;
- struct sc_reg_access sc_access_read = {0,};
-
- if (intelmaddata->pmic_status == PMIC_INIT) {
- sc_access_read.reg_addr = 0x132;
- sst_sc_reg_access(&sc_access_read, PMIC_READ, 1);
- value = (sc_access_read.value);
- pr_debug("value returned = 0x%x\n", value);
- }
- if (intsts & 0x1) {
- pr_debug("headset detected\n");
- /* send headset detect/undetect */
- jack = &intelmaddata->jack[1].jack;
- present = (value == 0x1) ? 1 : 0;
- jack_event_flag = 1;
- }
- if (intsts & 0x2) {
- pr_debug("headphone detected\n");
- /* send headphone detect/undetect */
- jack = &intelmaddata->jack[0].jack;
- present = (value == 0x2) ? 1 : 0;
- jack_event_flag = 1;
- }
- if (intsts & 0x4) {
- pr_debug("short push detected\n");
- /* send short push */
- jack = &intelmaddata->jack[2].jack;
- present = 1;
- jack_event_flag = 1;
- buttonpressflag = 1;
- }
- if (intsts & 0x8) {
- pr_debug("long push detected\n");
- /* send long push */
- jack = &intelmaddata->jack[3].jack;
- present = 1;
- jack_event_flag = 1;
- buttonpressflag = 1;
- }
-
- if (jack_event_flag)
- sst_mad_send_jack_report(jack, buttonpressflag, present);
-
-
-}
-
-void sst_process_mad_jack_detection(struct work_struct *work)
-{
- u8 intsts;
- struct mad_jack_msg_wq *mad_jack_detect =
- container_of(work, struct mad_jack_msg_wq, wq);
-
- struct snd_intelmad *intelmaddata =
- mad_jack_detect->intelmaddata;
-
- intsts = mad_jack_detect->intsts;
-
- switch (intelmaddata->sstdrv_ops->vendor_id) {
- case SND_FS:
- sst_mad_jackdetection_fs(intsts , intelmaddata);
- break;
- case SND_MX:
- sst_mad_jackdetection_mx(intsts , intelmaddata);
- break;
- case SND_NC:
- sst_mad_jackdetection_nec(intsts , intelmaddata);
- break;
- }
-}
-
-
static int __devinit snd_intelmad_register_irq(
- struct snd_intelmad *intelmaddata)
+ struct snd_intelmad *intelmaddata, unsigned int regbase,
+ unsigned int regsize)
{
int ret_val;
- u32 regbase = AUDINT_BASE, regsize = 8;
char *drv_name;
- pr_debug("irq reg done, regbase 0x%x, regsize 0x%x\n",
+ pr_debug("irq reg regbase 0x%x, regsize 0x%x\n",
regbase, regsize);
intelmaddata->int_base = ioremap_nocache(regbase, regsize);
if (!intelmaddata->int_base)
@@ -797,6 +603,7 @@
intelmaddata->sstdrv_ops->scard_ops->input_dev_id = DMIC;
intelmaddata->sstdrv_ops->scard_ops->output_dev_id =
STEREO_HEADPHONE;
+ intelmaddata->sstdrv_ops->scard_ops->lineout_dev_id = NONE;
}
/* registering with SST driver to get access to SST APIs to use */
@@ -805,13 +612,15 @@
pr_err("sst card registration failed\n");
return ret_val;
}
- sst_drv_ctx->scard_ops->card_status = SND_CARD_UN_INIT;
-
sst_card_vendor_id = intelmaddata->sstdrv_ops->vendor_id;
intelmaddata->pmic_status = PMIC_UNINIT;
return ret_val;
}
+static void snd_intelmad_page_free(struct snd_pcm *pcm)
+{
+ snd_pcm_lib_preallocate_free_for_all(pcm);
+}
/* Driver Init/exit functionalities */
/**
* snd_intelmad_pcm_new - to setup pcm for the card
@@ -863,6 +672,7 @@
snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, cap_ops);
/* setup private data which can be retrieved when required */
pcm->private_data = intelmaddata;
+ pcm->private_free = snd_intelmad_page_free;
pcm->info_flags = 0;
strncpy(pcm->name, card->shortname, strlen(card->shortname));
/* allocate dma pages for ALSA stream operations */
@@ -907,8 +717,12 @@
pr_debug("snd_intelmad_jack called\n");
jack = &intelmaddata->jack[0].jack;
- retval = snd_jack_new(intelmaddata->card, "Headphone",
- SND_JACK_HEADPHONE, &jack);
+ snd_jack_set_key(jack, SND_JACK_BTN_0, KEY_PHONE);
+ retval = snd_jack_new(intelmaddata->card, "Intel(R) MID Audio Jack",
+ SND_JACK_HEADPHONE | SND_JACK_HEADSET |
+ SW_JACK_PHYSICAL_INSERT | SND_JACK_BTN_0
+ | SND_JACK_BTN_1, &jack);
+ pr_debug("snd_intelmad_jack called\n");
if (retval < 0)
return retval;
snd_jack_report(jack, 0);
@@ -916,40 +730,6 @@
jack->private_data = jack;
intelmaddata->jack[0].jack = *jack;
-
- jack = &intelmaddata->jack[1].jack;
- retval = snd_jack_new(intelmaddata->card, "Headset",
- SND_JACK_HEADSET, &jack);
- if (retval < 0)
- return retval;
-
-
-
- jack->private_data = jack;
- intelmaddata->jack[1].jack = *jack;
-
-
- jack = &intelmaddata->jack[2].jack;
- retval = snd_jack_new(intelmaddata->card, "Short Press",
- SND_JACK_HS_SHORT_PRESS, &jack);
- if (retval < 0)
- return retval;
-
-
- jack->private_data = jack;
- intelmaddata->jack[2].jack = *jack;
-
-
- jack = &intelmaddata->jack[3].jack;
- retval = snd_jack_new(intelmaddata->card, "Long Press",
- SND_JACK_HS_LONG_PRESS, &jack);
- if (retval < 0)
- return retval;
-
-
- jack->private_data = jack;
- intelmaddata->jack[3].jack = *jack;
-
return retval;
}
@@ -1002,14 +782,14 @@
intelmaddata = device->device_data;
pr_debug("snd_intelmad_dev_free called\n");
- snd_card_free(intelmaddata->card);
- /*genl_unregister_family(&audio_event_genl_family);*/
unregister_sst_card(intelmaddata->sstdrv_ops);
/* free allocated memory for internal context */
destroy_workqueue(intelmaddata->mad_jack_wq);
+ device->device_data = NULL;
kfree(intelmaddata->sstdrv_ops);
kfree(intelmaddata);
+
return 0;
}
@@ -1040,9 +820,10 @@
int ret_val;
struct snd_intelmad *intelmaddata;
const struct platform_device_id *id = platform_get_device_id(pdev);
- unsigned int cpu_id = (unsigned int)id->driver_data;
+ struct snd_intelmad_probe_info *info = (void *)id->driver_data;
- pr_debug("probe for %s cpu_id %d\n", pdev->name, cpu_id);
+ pr_debug("probe for %s cpu_id %d\n", pdev->name, info->cpu_id);
+ pr_debug("rq_chache %x of size %x\n", info->irq_cache, info->size);
if (!strcmp(pdev->name, DRIVER_NAME_MRST))
pr_debug("detected MRST\n");
else if (!strcmp(pdev->name, DRIVER_NAME_MFLD))
@@ -1051,7 +832,8 @@
pr_err("detected unknown device abort!!\n");
return -EIO;
}
- if ((cpu_id < CPU_CHIP_LINCROFT) || (cpu_id > CPU_CHIP_PENWELL)) {
+ if ((info->cpu_id < CPU_CHIP_LINCROFT) ||
+ (info->cpu_id > CPU_CHIP_PENWELL)) {
pr_err("detected unknown cpu_id abort!!\n");
return -EIO;
}
@@ -1061,6 +843,7 @@
pr_debug("mem alloctn fail\n");
return -ENOMEM;
}
+ intelmad_drv = intelmaddata;
/* allocate memory for LPE API set */
intelmaddata->sstdrv_ops = kzalloc(sizeof(struct intel_sst_card_ops),
@@ -1071,7 +854,7 @@
return -ENOMEM;
}
- intelmaddata->cpu_id = cpu_id;
+ intelmaddata->cpu_id = info->cpu_id;
/* create a card instance with ALSA framework */
ret_val = snd_card_create(card_index, card_id, THIS_MODULE, 0, &card);
if (ret_val) {
@@ -1095,7 +878,7 @@
ret_val = snd_intelmad_sst_register(intelmaddata);
if (ret_val) {
pr_err("snd_intelmad_sst_register failed\n");
- goto free_allocs;
+ goto set_null_data;
}
intelmaddata->pmic_status = PMIC_INIT;
@@ -1103,20 +886,21 @@
ret_val = snd_intelmad_pcm(card, intelmaddata);
if (ret_val) {
pr_err("snd_intelmad_pcm failed\n");
- goto free_allocs;
+ goto free_sst;
}
ret_val = snd_intelmad_mixer(intelmaddata);
if (ret_val) {
pr_err("snd_intelmad_mixer failed\n");
- goto free_allocs;
+ goto free_card;
}
ret_val = snd_intelmad_jack(intelmaddata);
if (ret_val) {
pr_err("snd_intelmad_jack failed\n");
- goto free_allocs;
+ goto free_card;
}
+ intelmaddata->adc_address = mid_initialize_adc();
/*create work queue for jack interrupt*/
INIT_WORK(&intelmaddata->mad_jack_msg.wq,
@@ -1124,33 +908,48 @@
intelmaddata->mad_jack_wq = create_workqueue("sst_mad_jack_wq");
if (!intelmaddata->mad_jack_wq)
- goto free_mad_jack_wq;
+ goto free_card;
- ret_val = snd_intelmad_register_irq(intelmaddata);
+ ret_val = snd_intelmad_register_irq(intelmaddata,
+ info->irq_cache, info->size);
if (ret_val) {
pr_err("snd_intelmad_register_irq fail\n");
- goto free_allocs;
+ goto free_mad_jack_wq;
}
/* internal function call to register device with ALSA */
ret_val = snd_intelmad_create(intelmaddata, card);
if (ret_val) {
pr_err("snd_intelmad_create failed\n");
- goto free_allocs;
+ goto set_pvt_data;
}
card->private_data = &intelmaddata;
snd_card_set_dev(card, &pdev->dev);
ret_val = snd_card_register(card);
if (ret_val) {
pr_err("snd_card_register failed\n");
- goto free_allocs;
+ goto set_pvt_data;
+ }
+ if (pdev->dev.platform_data) {
+ int gpio_amp = *(int *)pdev->dev.platform_data;
+ if (gpio_request_one(gpio_amp, GPIOF_OUT_INIT_LOW, "amp power"))
+ gpio_amp = 0;
+ intelmaddata->sstdrv_ops->scard_ops->gpio_amp = gpio_amp;
}
pr_debug("snd_intelmad_probe complete\n");
return ret_val;
+set_pvt_data:
+ card->private_data = NULL;
free_mad_jack_wq:
destroy_workqueue(intelmaddata->mad_jack_wq);
+free_card:
+ snd_card_free(intelmaddata->card);
+free_sst:
+ unregister_sst_card(intelmaddata->sstdrv_ops);
+set_null_data:
+ platform_set_drvdata(pdev, NULL);
free_allocs:
pr_err("probe failed\n");
snd_card_free(card);
@@ -1165,13 +964,13 @@
struct snd_intelmad *intelmaddata = platform_get_drvdata(pdev);
if (intelmaddata) {
+ if (intelmaddata->sstdrv_ops->scard_ops->gpio_amp)
+ gpio_free(intelmaddata->sstdrv_ops->scard_ops->gpio_amp);
+ free_irq(intelmaddata->irq, intelmaddata);
snd_card_free(intelmaddata->card);
- unregister_sst_card(intelmaddata->sstdrv_ops);
- /* free allocated memory for internal context */
- destroy_workqueue(intelmaddata->mad_jack_wq);
- kfree(intelmaddata->sstdrv_ops);
- kfree(intelmaddata);
}
+ intelmad_drv = NULL;
+ platform_set_drvdata(pdev, NULL);
return 0;
}
@@ -1179,8 +978,8 @@
* Driver initialization and exit
*********************************************************************/
static const struct platform_device_id snd_intelmad_ids[] = {
- {DRIVER_NAME_MRST, CPU_CHIP_LINCROFT},
- {DRIVER_NAME_MFLD, CPU_CHIP_PENWELL},
+ {DRIVER_NAME_MRST, INFO(CPU_CHIP_LINCROFT, AUDINT_BASE, 1)},
+ {DRIVER_NAME_MFLD, INFO(CPU_CHIP_PENWELL, 0xFFFF7FCD, 1)},
{"", 0},
};
diff --git a/drivers/staging/intel_sst/intelmid.h b/drivers/staging/intel_sst/intelmid.h
index e77da87..14a7ba0 100644
--- a/drivers/staging/intel_sst/intelmid.h
+++ b/drivers/staging/intel_sst/intelmid.h
@@ -28,6 +28,7 @@
#define __INTELMID_H
#include <linux/time.h>
+#include <sound/jack.h>
#define DRIVER_NAME_MFLD "msic_audio"
#define DRIVER_NAME_MRST "pmic_audio"
@@ -43,7 +44,7 @@
#define MAX_BUFFER (800*1024) /* for PCM */
#define MIN_BUFFER (800*1024)
#define MAX_PERIODS (1024*2)
-#define MIN_PERIODS 1
+#define MIN_PERIODS 2
#define MAX_PERIOD_BYTES MAX_BUFFER
#define MIN_PERIOD_BYTES 32
/*#define MIN_PERIOD_BYTES 160*/
@@ -53,12 +54,12 @@
#define STEREO_CNTL 2
#define MIN_CHANNEL 1
#define MAX_CHANNEL_AMIC 2
-#define MAX_CHANNEL_DMIC 4
+#define MAX_CHANNEL_DMIC 5
#define FIFO_SIZE 0 /* fifo not being used */
#define INTEL_MAD "Intel MAD"
-#define MAX_CTRL_MRST 7
-#define MAX_CTRL_MFLD 2
-#define MAX_CTRL 7
+#define MAX_CTRL_MRST 8
+#define MAX_CTRL_MFLD 7
+#define MAX_CTRL 8
#define MAX_VENDORS 4
/* TODO +6 db */
#define MAX_VOL 64
@@ -66,12 +67,17 @@
#define MIN_VOL 0
#define PLAYBACK_COUNT 1
#define CAPTURE_COUNT 1
+#define ADC_ONE_LSB_MULTIPLIER 2346
+
+#define MID_JACK_HS_LONG_PRESS SND_JACK_BTN_0
+#define MID_JACK_HS_SHORT_PRESS SND_JACK_BTN_1
extern int sst_card_vendor_id;
struct mad_jack {
struct snd_jack jack;
int jack_status;
+ int jack_dev_state;
struct timeval buttonpressed;
struct timeval buttonreleased;
};
@@ -83,6 +89,12 @@
};
+struct snd_intelmad_probe_info {
+ unsigned int cpu_id;
+ unsigned int irq_cache;
+ unsigned int size;
+};
+
/**
* struct snd_intelmad - intelmad driver structure
*
@@ -116,10 +128,12 @@
void __iomem *int_base;
int output_sel;
int input_sel;
+ int lineout_sel;
int master_mute;
struct mad_jack jack[4];
int playback_cnt;
int capture_cnt;
+ u16 adc_address;
struct mad_jack_msg_wq mad_jack_msg;
struct workqueue_struct *mad_jack_wq;
u8 jack_prev_state;
@@ -131,6 +145,8 @@
int playback_vol_min;
int capture_vol_max;
int capture_vol_min;
+ int master_vol_max;
+ int master_vol_min;
};
struct mad_stream_pvt {
@@ -161,8 +177,18 @@
PLAYBACK_MUTE,
CAPTURE_VOL,
CAPTURE_MUTE,
+ MASTER_VOL,
MASTER_MUTE
};
+enum _widget_ctrl_mfld {
+ LINEOUT_SEL_MFLD = 3,
+};
+enum hw_chs {
+ HW_CH0 = 0,
+ HW_CH1,
+ HW_CH2,
+ HW_CH3
+};
void period_elapsed(void *mad_substream);
int snd_intelmad_alloc_stream(struct snd_pcm_substream *substream);
@@ -177,5 +203,7 @@
extern struct snd_kcontrol_new snd_intelmad_controls_mrst[];
extern struct snd_kcontrol_new snd_intelmad_controls_mfld[];
extern struct snd_pmic_ops *intelmad_vendor_ops[];
+void sst_mad_send_jack_report(struct snd_jack *jack,
+ int buttonpressevent , int status);
#endif /* __INTELMID_H */
diff --git a/drivers/staging/intel_sst/intelmid_adc_control.h b/drivers/staging/intel_sst/intelmid_adc_control.h
new file mode 100644
index 0000000..65d5c39
--- /dev/null
+++ b/drivers/staging/intel_sst/intelmid_adc_control.h
@@ -0,0 +1,193 @@
+#ifndef __INTELMID_ADC_CONTROL_H__
+#define __INTELMID_ADC_CONTROL_H_
+/*
+ * intelmid_adc_control.h - Intel SST Driver for audio engine
+ *
+ * Copyright (C) 2008-10 Intel Corporation
+ * Authors: R Durgadadoss <r.durgadoss@intel.com>
+ * Dharageswari R <dharageswari.r@intel.com>
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ * Common private ADC declarations for SST
+ */
+
+
+#define MSIC_ADC1CNTL1 0x1C0
+#define MSIC_ADC_ENBL 0x10
+#define MSIC_ADC_START 0x08
+
+#define MSIC_ADC1CNTL3 0x1C2
+#define MSIC_ADCTHERM_ENBL 0x04
+#define MSIC_ADCRRDATA_ENBL 0x05
+
+#define MSIC_STOPBIT_MASK 16
+#define MSIC_ADCTHERM_MASK 4
+
+#define ADC_CHANLS_MAX 15 /* Number of ADC channels */
+#define ADC_LOOP_MAX (ADC_CHANLS_MAX - 1)
+
+/* ADC channel code values */
+#define AUDIO_DETECT_CODE 0x06
+
+/* ADC base addresses */
+#define ADC_CHNL_START_ADDR 0x1C5 /* increments by 1 */
+#define ADC_DATA_START_ADDR 0x1D4 /* increments by 2 */
+
+
+/**
+ * configure_adc - enables/disables the ADC for conversion
+ * @val: zero: disables the ADC non-zero:enables the ADC
+ *
+ * Enable/Disable the ADC depending on the argument
+ *
+ * Can sleep
+ */
+static inline int configure_adc(int val)
+{
+ int ret;
+ struct sc_reg_access sc_access = {0,};
+
+
+ sc_access.reg_addr = MSIC_ADC1CNTL1;
+ ret = sst_sc_reg_access(&sc_access, PMIC_READ, 1);
+ if (ret)
+ return ret;
+
+ if (val)
+ /* Enable and start the ADC */
+ sc_access.value |= (MSIC_ADC_ENBL | MSIC_ADC_START);
+ else
+ /* Just stop the ADC */
+ sc_access.value &= (~MSIC_ADC_START);
+ sc_access.reg_addr = MSIC_ADC1CNTL1;
+ return sst_sc_reg_access(&sc_access, PMIC_WRITE, 1);
+}
+
+/**
+ * reset_stopbit - sets the stop bit to 0 on the given channel
+ * @addr: address of the channel
+ *
+ * Can sleep
+ */
+static inline int reset_stopbit(uint16_t addr)
+{
+ int ret;
+ struct sc_reg_access sc_access = {0,};
+ sc_access.reg_addr = addr;
+ ret = sst_sc_reg_access(&sc_access, PMIC_READ, 1);
+ if (ret)
+ return ret;
+ /* Set the stop bit to zero */
+ sc_access.reg_addr = addr;
+ sc_access.value = (sc_access.value) & 0xEF;
+ return sst_sc_reg_access(&sc_access, PMIC_WRITE, 1);
+}
+
+/**
+ * find_free_channel - finds an empty channel for conversion
+ *
+ * If the ADC is not enabled then start using 0th channel
+ * itself. Otherwise find an empty channel by looking for a
+ * channel in which the stopbit is set to 1. returns the index
+ * of the first free channel if succeeds or an error code.
+ *
+ * Context: can sleep
+ *
+ */
+static inline int find_free_channel(void)
+{
+ int ret;
+ int i;
+
+ struct sc_reg_access sc_access = {0,};
+
+ /* check whether ADC is enabled */
+ sc_access.reg_addr = MSIC_ADC1CNTL1;
+ ret = sst_sc_reg_access(&sc_access, PMIC_READ, 1);
+ if (ret)
+ return ret;
+
+ if ((sc_access.value & MSIC_ADC_ENBL) == 0)
+ return 0;
+
+ /* ADC is already enabled; Looking for an empty channel */
+ for (i = 0; i < ADC_CHANLS_MAX; i++) {
+
+ sc_access.reg_addr = ADC_CHNL_START_ADDR + i;
+ ret = sst_sc_reg_access(&sc_access, PMIC_READ, 1);
+ if (ret)
+ return ret;
+
+ if (sc_access.value & MSIC_STOPBIT_MASK) {
+ ret = i;
+ break;
+ }
+ }
+ return (ret > ADC_LOOP_MAX) ? (-EINVAL) : ret;
+}
+
+/**
+ * mid_initialize_adc - initializing the ADC
+ * @dev: our device structure
+ *
+ * Initialize the ADC for reading thermistor values. Can sleep.
+ */
+static inline int mid_initialize_adc(void)
+{
+ int base_addr, chnl_addr;
+ int ret;
+ static int channel_index;
+ struct sc_reg_access sc_access = {0,};
+
+ /* Index of the first channel in which the stop bit is set */
+ channel_index = find_free_channel();
+ if (channel_index < 0) {
+ pr_err("No free ADC channels");
+ return channel_index;
+ }
+
+ base_addr = ADC_CHNL_START_ADDR + channel_index;
+
+ if (!(channel_index == 0 || channel_index == ADC_LOOP_MAX)) {
+ /* Reset stop bit for channels other than 0 and 12 */
+ ret = reset_stopbit(base_addr);
+ if (ret)
+ return ret;
+
+ /* Index of the first free channel */
+ base_addr++;
+ channel_index++;
+ }
+
+ /* Since this is the last channel, set the stop bit
+ to 1 by ORing the DIE_SENSOR_CODE with 0x10 */
+ sc_access.reg_addr = base_addr;
+ sc_access.value = AUDIO_DETECT_CODE | 0x10;
+ ret = sst_sc_reg_access(&sc_access, PMIC_WRITE, 1);
+ if (ret) {
+ pr_err("unable to enable ADC");
+ return ret;
+ }
+
+ chnl_addr = ADC_DATA_START_ADDR + 2 * channel_index;
+ pr_debug("mid_initialize : %x", chnl_addr);
+ configure_adc(1);
+ return chnl_addr;
+}
+#endif
+
diff --git a/drivers/staging/intel_sst/intelmid_ctrl.c b/drivers/staging/intel_sst/intelmid_ctrl.c
index 69af070..19ec474 100644
--- a/drivers/staging/intel_sst/intelmid_ctrl.c
+++ b/drivers/staging/intel_sst/intelmid_ctrl.c
@@ -29,17 +29,37 @@
#include <sound/core.h>
#include <sound/control.h>
-#include "jack.h"
#include "intel_sst.h"
#include "intel_sst_ioctl.h"
#include "intelmid_snd_control.h"
#include "intelmid.h"
+#define HW_CH_BASE 4
+
+
+#define HW_CH_0 "Hw1"
+#define HW_CH_1 "Hw2"
+#define HW_CH_2 "Hw3"
+#define HW_CH_3 "Hw4"
+
+static char *router_dmics[] = { "DMIC1",
+ "DMIC2",
+ "DMIC3",
+ "DMIC4",
+ "DMIC5",
+ "DMIC6"
+ };
+
static char *out_names_mrst[] = {"Headphones",
"Internal speakers"};
static char *in_names_mrst[] = {"AMIC",
"DMIC",
"HS_MIC"};
+static char *line_out_names_mfld[] = {"Headset",
+ "IHF ",
+ "Vibra1 ",
+ "Vibra2 ",
+ "NONE "};
static char *out_names_mfld[] = {"Headset ",
"EarPiece "};
static char *in_names_mfld[] = {"AMIC",
@@ -60,9 +80,11 @@
},
{
.playback_vol_max = 0,
- .playback_vol_min = -126,
+ .playback_vol_min = -31,
.capture_vol_max = 0,
.capture_vol_min = -31,
+ .master_vol_max = 0,
+ .master_vol_min = -126,
},
};
@@ -139,6 +161,15 @@
return 0;
}
+static int snd_intelmad_master_volume_info(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_info *uinfo)
+{
+ snd_intelmad_volume_info(uinfo, STEREO_CNTL,
+ intelmad_ctrl_val[sst_card_vendor_id].master_vol_max,
+ intelmad_ctrl_val[sst_card_vendor_id].master_vol_min);
+ return 0;
+}
+
/**
* snd_intelmad_device_info_mrst - provides information about the devices available
*
@@ -179,13 +210,27 @@
static int snd_intelmad_device_info_mfld(struct snd_kcontrol *kcontrol,
struct snd_ctl_elem_info *uinfo)
{
+ struct snd_pmic_ops *scard_ops;
+ struct snd_intelmad *intelmaddata;
+
WARN_ON(!kcontrol);
WARN_ON(!uinfo);
+
+ intelmaddata = kcontrol->private_data;
+
+ WARN_ON(!intelmaddata->sstdrv_ops);
+
+ scard_ops = intelmaddata->sstdrv_ops->scard_ops;
/* setup device select as drop down controls with different values */
if (kcontrol->id.numid == OUTPUT_SEL)
uinfo->value.enumerated.items = ARRAY_SIZE(out_names_mfld);
- else
+ else if (kcontrol->id.numid == INPUT_SEL)
uinfo->value.enumerated.items = ARRAY_SIZE(in_names_mfld);
+ else if (kcontrol->id.numid == LINEOUT_SEL_MFLD) {
+ uinfo->value.enumerated.items = ARRAY_SIZE(line_out_names_mfld);
+ scard_ops->line_out_names_cnt = uinfo->value.enumerated.items;
+ } else
+ return -EINVAL;
uinfo->count = MONO_CNTL;
uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
@@ -195,10 +240,16 @@
strncpy(uinfo->value.enumerated.name,
out_names_mfld[uinfo->value.enumerated.item],
sizeof(uinfo->value.enumerated.name)-1);
- else
+ else if (kcontrol->id.numid == INPUT_SEL)
strncpy(uinfo->value.enumerated.name,
in_names_mfld[uinfo->value.enumerated.item],
sizeof(uinfo->value.enumerated.name)-1);
+ else if (kcontrol->id.numid == LINEOUT_SEL_MFLD)
+ strncpy(uinfo->value.enumerated.name,
+ line_out_names_mfld[uinfo->value.enumerated.item],
+ sizeof(uinfo->value.enumerated.name)-1);
+ else
+ return -EINVAL;
return 0;
}
@@ -241,6 +292,11 @@
case CAPTURE_VOL:
cntl_list[0] = PMIC_SND_CAPTURE_VOL;
break;
+
+ case MASTER_VOL:
+ cntl_list[0] = PMIC_SND_RIGHT_MASTER_VOL;
+ cntl_list[1] = PMIC_SND_LEFT_MASTER_VOL;
+ break;
default:
return -EINVAL;
}
@@ -251,7 +307,8 @@
if (ret_val)
return ret_val;
- if (kcontrol->id.numid == PLAYBACK_VOL) {
+ if (kcontrol->id.numid == PLAYBACK_VOL ||
+ kcontrol->id.numid == MASTER_VOL) {
ret_val = scard_ops->get_vol(cntl_list[1], &value);
uval->value.integer.value[1] = value;
}
@@ -359,6 +416,12 @@
case CAPTURE_VOL:
cntl_list[0] = PMIC_SND_CAPTURE_VOL;
break;
+
+ case MASTER_VOL:
+ cntl_list[0] = PMIC_SND_LEFT_MASTER_VOL;
+ cntl_list[1] = PMIC_SND_RIGHT_MASTER_VOL;
+ break;
+
default:
return -EINVAL;
}
@@ -368,7 +431,8 @@
if (ret_val)
return ret_val;
- if (kcontrol->id.numid == PLAYBACK_VOL)
+ if (kcontrol->id.numid == PLAYBACK_VOL ||
+ kcontrol->id.numid == MASTER_VOL)
ret_val = scard_ops->set_vol(cntl_list[1],
uval->value.integer.value[1]);
return ret_val;
@@ -464,14 +528,36 @@
WARN_ON(!kcontrol);
intelmaddata = kcontrol->private_data;
+ scard_ops = intelmaddata->sstdrv_ops->scard_ops;
if (intelmaddata->cpu_id == CPU_CHIP_PENWELL) {
- scard_ops = intelmaddata->sstdrv_ops->scard_ops;
if (kcontrol->id.numid == OUTPUT_SEL)
uval->value.enumerated.item[0] =
scard_ops->output_dev_id;
else if (kcontrol->id.numid == INPUT_SEL)
uval->value.enumerated.item[0] =
scard_ops->input_dev_id;
+ else if (kcontrol->id.numid == LINEOUT_SEL_MFLD)
+ uval->value.enumerated.item[0] =
+ scard_ops->lineout_dev_id;
+ else
+ return -EINVAL;
+ } else if (intelmaddata->cpu_id == CPU_CHIP_LINCROFT) {
+ if (kcontrol->id.numid == OUTPUT_SEL)
+ /* There is a mismatch here.
+ * ALSA expects 1 for internal speaker.
+ * But internally, we may give 2 for internal speaker.
+ */
+ if (scard_ops->output_dev_id == MONO_EARPIECE ||
+ scard_ops->output_dev_id == INTERNAL_SPKR)
+ uval->value.enumerated.item[0] = MONO_EARPIECE;
+ else if (scard_ops->output_dev_id == STEREO_HEADPHONE)
+ uval->value.enumerated.item[0] =
+ STEREO_HEADPHONE;
+ else
+ return -EINVAL;
+ else if (kcontrol->id.numid == INPUT_SEL)
+ uval->value.enumerated.item[0] =
+ scard_ops->input_dev_id;
else
return -EINVAL;
} else
@@ -534,6 +620,11 @@
uval->value.enumerated.item[0]);
intelmaddata->input_sel = uval->value.enumerated.item[0];
break;
+ case LINEOUT_SEL_MFLD:
+ ret_val = scard_ops->set_lineout_dev(
+ uval->value.enumerated.item[0]);
+ intelmaddata->lineout_sel = uval->value.enumerated.item[0];
+ break;
default:
return -EINVAL;
}
@@ -541,6 +632,151 @@
return ret_val;
}
+static int snd_intelmad_device_dmic_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *uval)
+{
+ struct snd_intelmad *intelmaddata;
+ struct snd_pmic_ops *scard_ops;
+
+ WARN_ON(!uval);
+ WARN_ON(!kcontrol);
+
+ intelmaddata = kcontrol->private_data;
+ scard_ops = intelmaddata->sstdrv_ops->scard_ops;
+
+ if (scard_ops->input_dev_id != DMIC) {
+ pr_debug("input dev = 0x%x\n", scard_ops->input_dev_id);
+ return 0;
+ }
+
+ if (intelmaddata->cpu_id == CPU_CHIP_PENWELL)
+ uval->value.enumerated.item[0] = kcontrol->private_value;
+ else
+ pr_debug(" CPU id = 0x%xis invalid.\n",
+ intelmaddata->cpu_id);
+ return 0;
+}
+
+void msic_set_bit(u8 index, unsigned int *available_dmics)
+{
+ *available_dmics |= (1 << index);
+}
+
+void msic_clear_bit(u8 index, unsigned int *available_dmics)
+{
+ *available_dmics &= ~(1 << index);
+}
+
+int msic_is_set_bit(u8 index, unsigned int *available_dmics)
+{
+ int ret_val;
+
+ ret_val = (*available_dmics & (1 << index));
+ return ret_val;
+}
+
+static int snd_intelmad_device_dmic_set(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *uval)
+{
+ struct snd_intelmad *intelmaddata;
+ struct snd_pmic_ops *scard_ops;
+ int i, dmic_index;
+ unsigned int available_dmics;
+ int jump_count;
+ int max_dmics = ARRAY_SIZE(router_dmics);
+
+ WARN_ON(!uval);
+ WARN_ON(!kcontrol);
+
+ intelmaddata = kcontrol->private_data;
+ WARN_ON(!intelmaddata->sstdrv_ops);
+
+ scard_ops = intelmaddata->sstdrv_ops->scard_ops;
+ WARN_ON(!scard_ops);
+
+ if (scard_ops->input_dev_id != DMIC) {
+ pr_debug("input dev = 0x%x\n", scard_ops->input_dev_id);
+ return 0;
+ }
+
+ available_dmics = scard_ops->available_dmics;
+
+ if (kcontrol->private_value > uval->value.enumerated.item[0]) {
+ pr_debug("jump count -1.\n");
+ jump_count = -1;
+ } else {
+ pr_debug("jump count 1.\n");
+ jump_count = 1;
+ }
+
+ dmic_index = uval->value.enumerated.item[0];
+ pr_debug("set function. dmic_index = %d, avl_dmic = 0x%x\n",
+ dmic_index, available_dmics);
+ for (i = 0; i < max_dmics; i++) {
+ pr_debug("set function. loop index = 0x%x. dmic_index = 0x%x\n",
+ i, dmic_index);
+ if (!msic_is_set_bit(dmic_index, &available_dmics)) {
+ msic_clear_bit(kcontrol->private_value,
+ &available_dmics);
+ msic_set_bit(dmic_index, &available_dmics);
+ kcontrol->private_value = dmic_index;
+ scard_ops->available_dmics = available_dmics;
+ scard_ops->hw_dmic_map[kcontrol->id.numid-HW_CH_BASE] =
+ kcontrol->private_value;
+ scard_ops->set_hw_dmic_route
+ (kcontrol->id.numid-HW_CH_BASE);
+ return 0;
+ }
+
+ dmic_index += jump_count;
+
+ if (dmic_index > (max_dmics - 1) && jump_count == 1) {
+ pr_debug("Resettingthe dmic index to 0.\n");
+ dmic_index = 0;
+ } else if (dmic_index == -1 && jump_count == -1) {
+ pr_debug("Resetting the dmic index to 5.\n");
+ dmic_index = max_dmics - 1;
+ }
+ }
+
+ return -EINVAL;
+}
+
+static int snd_intelmad_device_dmic_info_mfld(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_info *uinfo)
+{
+ struct snd_intelmad *intelmaddata;
+ struct snd_pmic_ops *scard_ops;
+
+ uinfo->count = MONO_CNTL;
+ uinfo->type = SNDRV_CTL_ELEM_TYPE_ENUMERATED;
+ uinfo->value.enumerated.items = ARRAY_SIZE(router_dmics);
+
+ intelmaddata = kcontrol->private_data;
+ WARN_ON(!intelmaddata->sstdrv_ops);
+
+ scard_ops = intelmaddata->sstdrv_ops->scard_ops;
+ WARN_ON(!scard_ops);
+
+ if (uinfo->value.enumerated.item >= uinfo->value.enumerated.items)
+ uinfo->value.enumerated.item =
+ uinfo->value.enumerated.items - 1;
+
+ strncpy(uinfo->value.enumerated.name,
+ router_dmics[uinfo->value.enumerated.item],
+ sizeof(uinfo->value.enumerated.name)-1);
+
+
+ msic_set_bit(kcontrol->private_value, &scard_ops->available_dmics);
+ pr_debug("info function. avl_dmic = 0x%x",
+ scard_ops->available_dmics);
+
+ scard_ops->hw_dmic_map[kcontrol->id.numid-HW_CH_BASE] =
+ kcontrol->private_value;
+
+ return 0;
+}
+
struct snd_kcontrol_new snd_intelmad_controls_mrst[MAX_CTRL] __devinitdata = {
{
.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
@@ -598,6 +834,15 @@
},
{
.iface = SNDRV_CTL_ELEM_IFACE_MIXER,
+ .name = "Master Playback Volume",
+ .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
+ .info = snd_intelmad_master_volume_info,
+ .get = snd_intelmad_volume_get,
+ .put = snd_intelmad_volume_set,
+ .private_value = 0,
+},
+{
+ .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
.name = "Master Playback Switch",
.access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
.info = snd_intelmad_mute_info,
@@ -627,5 +872,50 @@
.put = snd_intelmad_device_set,
.private_value = 0,
},
+{
+ .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
+ .name = "Line out",
+ .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
+ .info = snd_intelmad_device_info_mfld,
+ .get = snd_intelmad_device_get,
+ .put = snd_intelmad_device_set,
+ .private_value = 0,
+},
+{
+ .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
+ .name = HW_CH_0,
+ .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
+ .info = snd_intelmad_device_dmic_info_mfld,
+ .get = snd_intelmad_device_dmic_get,
+ .put = snd_intelmad_device_dmic_set,
+ .private_value = 0
+},
+{
+ .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
+ .name = HW_CH_1,
+ .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
+ .info = snd_intelmad_device_dmic_info_mfld,
+ .get = snd_intelmad_device_dmic_get,
+ .put = snd_intelmad_device_dmic_set,
+ .private_value = 1
+},
+{
+ .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
+ .name = HW_CH_2,
+ .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
+ .info = snd_intelmad_device_dmic_info_mfld,
+ .get = snd_intelmad_device_dmic_get,
+ .put = snd_intelmad_device_dmic_set,
+ .private_value = 2
+},
+{
+ .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
+ .name = HW_CH_3,
+ .access = SNDRV_CTL_ELEM_ACCESS_READWRITE,
+ .info = snd_intelmad_device_dmic_info_mfld,
+ .get = snd_intelmad_device_dmic_get,
+ .put = snd_intelmad_device_dmic_set,
+ .private_value = 3
+}
};
diff --git a/drivers/staging/intel_sst/intelmid_msic_control.c b/drivers/staging/intel_sst/intelmid_msic_control.c
index da093ed..70cdb16 100644
--- a/drivers/staging/intel_sst/intelmid_msic_control.c
+++ b/drivers/staging/intel_sst/intelmid_msic_control.c
@@ -28,9 +28,15 @@
#include <linux/pci.h>
#include <linux/file.h>
+#include <linux/delay.h>
+#include <sound/control.h>
#include "intel_sst.h"
-#include "intel_sst_ioctl.h"
+#include <linux/input.h>
#include "intelmid_snd_control.h"
+#include "intelmid.h"
+
+#define AUDIOMUX12 0x24c
+#define AUDIOMUX34 0x24d
static int msic_init_card(void)
{
@@ -54,116 +60,359 @@
/*TI vibra w/a settings*/
{0x384, 0x80, 0},
{0x385, 0x80, 0},
- /*vibra settings*/
{0x267, 0x00, 0},
- {0x26A, 0x10, 0},
{0x261, 0x00, 0},
- {0x264, 0x10, 0},
/* pcm port setting */
{0x278, 0x00, 0},
{0x27B, 0x01, 0},
{0x27C, 0x0a, 0},
/* Set vol HSLRVOLCTRL, IHFVOL */
- {0x259, 0x04, 0},
- {0x25A, 0x04, 0},
- {0x25B, 0x04, 0},
- {0x25C, 0x04, 0},
+ {0x259, 0x08, 0},
+ {0x25A, 0x08, 0},
+ {0x25B, 0x08, 0},
+ {0x25C, 0x08, 0},
/* HSEPRXCTRL Enable the headset left and right FIR filters */
{0x250, 0x30, 0},
/* HSMIXER */
{0x256, 0x11, 0},
/* amic configuration */
- {0x249, 0x09, 0x0},
- {0x24A, 0x09, 0x0},
+ {0x249, 0x01, 0x0},
+ {0x24A, 0x01, 0x0},
/* unmask ocaudio/accdet interrupts */
{0x1d, 0x00, 0x00},
{0x1e, 0x00, 0x00},
};
snd_msic_ops.card_status = SND_CARD_INIT_DONE;
- sst_sc_reg_access(sc_access, PMIC_WRITE, 30);
+ sst_sc_reg_access(sc_access, PMIC_WRITE, 28);
snd_msic_ops.pb_on = 0;
+ snd_msic_ops.pbhs_on = 0;
snd_msic_ops.cap_on = 0;
snd_msic_ops.input_dev_id = DMIC; /*def dev*/
snd_msic_ops.output_dev_id = STEREO_HEADPHONE;
+ snd_msic_ops.jack_interrupt_status = false;
pr_debug("msic init complete!!\n");
return 0;
}
+static int msic_line_out_restore(u8 value)
+{
+ struct sc_reg_access hs_drv_en[] = {
+ {0x25d, 0x03, 0x03},
+ };
+ struct sc_reg_access ep_drv_en[] = {
+ {0x25d, 0x40, 0x40},
+ };
+ struct sc_reg_access ihf_drv_en[] = {
+ {0x25d, 0x0c, 0x0c},
+ };
+ struct sc_reg_access vib1_drv_en[] = {
+ {0x25d, 0x10, 0x10},
+ };
+ struct sc_reg_access vib2_drv_en[] = {
+ {0x25d, 0x20, 0x20},
+ };
+ struct sc_reg_access pmode_enable[] = {
+ {0x381, 0x10, 0x10},
+ };
+ int retval = 0;
+
+ pr_debug("msic_lineout_restore_lineout_dev:%d\n", value);
+
+ switch (value) {
+ case HEADSET:
+ pr_debug("Selecting Lineout-HEADSET-restore\n");
+ if (snd_msic_ops.output_dev_id == STEREO_HEADPHONE)
+ retval = sst_sc_reg_access(hs_drv_en,
+ PMIC_READ_MODIFY, 1);
+ else
+ retval = sst_sc_reg_access(ep_drv_en,
+ PMIC_READ_MODIFY, 1);
+ break;
+ case IHF:
+ pr_debug("Selecting Lineout-IHF-restore\n");
+ retval = sst_sc_reg_access(ihf_drv_en, PMIC_READ_MODIFY, 1);
+ if (retval)
+ return retval;
+ retval = sst_sc_reg_access(pmode_enable, PMIC_READ_MODIFY, 1);
+ break;
+ case VIBRA1:
+ pr_debug("Selecting Lineout-Vibra1-restore\n");
+ retval = sst_sc_reg_access(vib1_drv_en, PMIC_READ_MODIFY, 1);
+ break;
+ case VIBRA2:
+ pr_debug("Selecting Lineout-VIBRA2-restore\n");
+ retval = sst_sc_reg_access(vib2_drv_en, PMIC_READ_MODIFY, 1);
+ break;
+ case NONE:
+ pr_debug("Selecting Lineout-NONE-restore\n");
+ break;
+ default:
+ return -EINVAL;
+ }
+ return retval;
+}
+static int msic_get_lineout_prvstate(void)
+{
+ struct sc_reg_access hs_ihf_drv[2] = {
+ {0x257, 0x0, 0x0},
+ {0x25d, 0x0, 0x0},
+ };
+ struct sc_reg_access vib1drv[2] = {
+ {0x264, 0x0, 0x0},
+ {0x25D, 0x0, 0x0},
+ };
+ struct sc_reg_access vib2drv[2] = {
+ {0x26A, 0x0, 0x0},
+ {0x25D, 0x0, 0x0},
+ };
+ int retval = 0, drv_en, dac_en, dev_id, mask;
+ for (dev_id = 0; dev_id < snd_msic_ops.line_out_names_cnt; dev_id++) {
+ switch (dev_id) {
+ case HEADSET:
+ pr_debug("msic_get_lineout_prvs_state: HEADSET\n");
+ sst_sc_reg_access(hs_ihf_drv, PMIC_READ, 2);
+
+ mask = (MASK0|MASK1);
+ dac_en = (hs_ihf_drv[0].value) & mask;
+
+ mask = ((MASK0|MASK1)|MASK6);
+ drv_en = (hs_ihf_drv[1].value) & mask;
+
+ if (dac_en && (!drv_en)) {
+ snd_msic_ops.prev_lineout_dev_id = HEADSET;
+ return retval;
+ }
+ break;
+ case IHF:
+ pr_debug("msic_get_lineout_prvstate: IHF\n");
+ sst_sc_reg_access(hs_ihf_drv, PMIC_READ, 2);
+
+ mask = (MASK2 | MASK3);
+ dac_en = (hs_ihf_drv[0].value) & mask;
+
+ mask = (MASK2 | MASK3);
+ drv_en = (hs_ihf_drv[1].value) & mask;
+
+ if (dac_en && (!drv_en)) {
+ snd_msic_ops.prev_lineout_dev_id = IHF;
+ return retval;
+ }
+ break;
+ case VIBRA1:
+ pr_debug("msic_get_lineout_prvstate: vibra1\n");
+ sst_sc_reg_access(vib1drv, PMIC_READ, 2);
+
+ mask = MASK1;
+ dac_en = (vib1drv[0].value) & mask;
+
+ mask = MASK4;
+ drv_en = (vib1drv[1].value) & mask;
+
+ if (dac_en && (!drv_en)) {
+ snd_msic_ops.prev_lineout_dev_id = VIBRA1;
+ return retval;
+ }
+ break;
+ case VIBRA2:
+ pr_debug("msic_get_lineout_prvstate: vibra2\n");
+ sst_sc_reg_access(vib2drv, PMIC_READ, 2);
+
+ mask = MASK1;
+ dac_en = (vib2drv[0].value) & mask;
+
+ mask = MASK5;
+ drv_en = ((vib2drv[1].value) & mask);
+
+ if (dac_en && (!drv_en)) {
+ snd_msic_ops.prev_lineout_dev_id = VIBRA2;
+ return retval;
+ }
+ break;
+ case NONE:
+ pr_debug("msic_get_lineout_prvstate: NONE\n");
+ snd_msic_ops.prev_lineout_dev_id = NONE;
+ return retval;
+ default:
+ pr_debug("Invalid device id\n");
+ snd_msic_ops.prev_lineout_dev_id = NONE;
+ return -EINVAL;
+ }
+ }
+ return retval;
+}
+static int msic_set_selected_lineout_dev(u8 value)
+{
+ struct sc_reg_access lout_hs[] = {
+ {0x25e, 0x33, 0xFF},
+ {0x25d, 0x0, 0x43},
+ };
+ struct sc_reg_access lout_ihf[] = {
+ {0x25e, 0x55, 0xff},
+ {0x25d, 0x0, 0x0c},
+ };
+ struct sc_reg_access lout_vibra1[] = {
+
+ {0x25e, 0x61, 0xff},
+ {0x25d, 0x0, 0x10},
+ };
+ struct sc_reg_access lout_vibra2[] = {
+
+ {0x25e, 0x16, 0xff},
+ {0x25d, 0x0, 0x20},
+ };
+ struct sc_reg_access lout_def[] = {
+ {0x25e, 0x66, 0x0},
+ };
+ struct sc_reg_access pmode_disable[] = {
+ {0x381, 0x00, 0x10},
+ };
+ struct sc_reg_access pmode_enable[] = {
+ {0x381, 0x10, 0x10},
+ };
+ int retval = 0;
+
+ pr_debug("msic_set_selected_lineout_dev:%d\n", value);
+ msic_get_lineout_prvstate();
+ msic_line_out_restore(snd_msic_ops.prev_lineout_dev_id);
+ snd_msic_ops.lineout_dev_id = value;
+
+ switch (value) {
+ case HEADSET:
+ pr_debug("Selecting Lineout-HEADSET\n");
+ if (snd_msic_ops.pb_on)
+ retval = sst_sc_reg_access(lout_hs,
+ PMIC_READ_MODIFY, 2);
+ if (retval)
+ return retval;
+ retval = sst_sc_reg_access(pmode_disable,
+ PMIC_READ_MODIFY, 1);
+ break;
+ case IHF:
+ pr_debug("Selecting Lineout-IHF\n");
+ if (snd_msic_ops.pb_on)
+ retval = sst_sc_reg_access(lout_ihf,
+ PMIC_READ_MODIFY, 2);
+ if (retval)
+ return retval;
+ retval = sst_sc_reg_access(pmode_enable,
+ PMIC_READ_MODIFY, 1);
+ break;
+ case VIBRA1:
+ pr_debug("Selecting Lineout-Vibra1\n");
+ if (snd_msic_ops.pb_on)
+ retval = sst_sc_reg_access(lout_vibra1,
+ PMIC_READ_MODIFY, 2);
+ if (retval)
+ return retval;
+ retval = sst_sc_reg_access(pmode_disable,
+ PMIC_READ_MODIFY, 1);
+ break;
+ case VIBRA2:
+ pr_debug("Selecting Lineout-VIBRA2\n");
+ if (snd_msic_ops.pb_on)
+ retval = sst_sc_reg_access(lout_vibra2,
+ PMIC_READ_MODIFY, 2);
+ if (retval)
+ return retval;
+ retval = sst_sc_reg_access(pmode_disable,
+ PMIC_READ_MODIFY, 1);
+ break;
+ case NONE:
+ pr_debug("Selecting Lineout-NONE\n");
+ retval = sst_sc_reg_access(lout_def,
+ PMIC_WRITE, 1);
+ if (retval)
+ return retval;
+ retval = sst_sc_reg_access(pmode_disable,
+ PMIC_READ_MODIFY, 1);
+ break;
+ default:
+ return -EINVAL;
+ }
+ return retval;
+}
+
static int msic_power_up_pb(unsigned int device)
{
- struct sc_reg_access sc_access1[] = {
+ struct sc_reg_access vaud[] = {
/* turn on the audio power supplies */
- {0x0DB, 0x05, 0},
+ {0x0DB, 0x07, 0},
+ };
+ struct sc_reg_access pll[] = {
+ /* turn on PLL */
+ {0x240, 0x20, 0},
+ };
+ struct sc_reg_access vhs[] = {
/* VHSP */
- {0x0DC, 0xFF, 0},
+ {0x0DC, 0x3D, 0},
/* VHSN */
{0x0DD, 0x3F, 0},
- /* turn on PLL */
- {0x240, 0x21, 0},
};
- struct sc_reg_access sc_access2[] = {
+ struct sc_reg_access hsdac[] = {
+ {0x382, 0x40, 0x40},
/* disable driver */
{0x25D, 0x0, 0x43},
/* DAC CONFIG ; both HP, LP on */
{0x257, 0x03, 0x03},
};
- struct sc_reg_access sc_access3[] = {
+ struct sc_reg_access hs_filter[] = {
/* HSEPRXCTRL Enable the headset left and right FIR filters */
{0x250, 0x30, 0},
/* HSMIXER */
{0x256, 0x11, 0},
};
- struct sc_reg_access sc_access4[] = {
+ struct sc_reg_access hs_enable[] = {
/* enable driver */
{0x25D, 0x3, 0x3},
+ {0x26C, 0x0, 0x2},
/* unmute the headset */
{ 0x259, 0x80, 0x80},
{ 0x25A, 0x80, 0x80},
};
- struct sc_reg_access sc_access_vihf[] = {
+ struct sc_reg_access vihf[] = {
/* VIHF ON */
- {0x0C9, 0x2D, 0x00},
+ {0x0C9, 0x27, 0x00},
};
- struct sc_reg_access sc_access22[] = {
+ struct sc_reg_access ihf_filter[] = {
/* disable driver */
{0x25D, 0x00, 0x0C},
/*Filer DAC enable*/
{0x251, 0x03, 0x03},
{0x257, 0x0C, 0x0C},
};
- struct sc_reg_access sc_access32[] = {
+ struct sc_reg_access ihf_en[] = {
/*enable drv*/
{0x25D, 0x0C, 0x0c},
};
- struct sc_reg_access sc_access42[] = {
+ struct sc_reg_access ihf_unmute[] = {
/*unmute headset*/
{0x25B, 0x80, 0x80},
{0x25C, 0x80, 0x80},
};
- struct sc_reg_access sc_access23[] = {
+ struct sc_reg_access epdac[] = {
/* disable driver */
{0x25D, 0x0, 0x43},
/* DAC CONFIG ; both HP, LP on */
{0x257, 0x03, 0x03},
};
- struct sc_reg_access sc_access43[] = {
+ struct sc_reg_access ep_enable[] = {
/* enable driver */
{0x25D, 0x40, 0x40},
/* unmute the headset */
{ 0x259, 0x80, 0x80},
{ 0x25A, 0x80, 0x80},
};
- struct sc_reg_access sc_access_vib[] = {
+ struct sc_reg_access vib1_en[] = {
/* enable driver, ADC */
{0x25D, 0x10, 0x10},
- {0x264, 0x02, 0x02},
+ {0x264, 0x02, 0x82},
};
- struct sc_reg_access sc_access_hap[] = {
+ struct sc_reg_access vib2_en[] = {
/* enable driver, ADC */
{0x25D, 0x20, 0x20},
- {0x26A, 0x02, 0x02},
+ {0x26A, 0x02, 0x82},
};
- struct sc_reg_access sc_access_pcm2[] = {
+ struct sc_reg_access pcm2_en[] = {
/* enable pcm 2 */
{0x27C, 0x1, 0x1},
};
@@ -176,89 +425,95 @@
}
pr_debug("powering up pb.... Device %d\n", device);
- sst_sc_reg_access(sc_access1, PMIC_WRITE, 4);
+ sst_sc_reg_access(vaud, PMIC_WRITE, 1);
+ msleep(1);
+ sst_sc_reg_access(pll, PMIC_WRITE, 1);
+ msleep(1);
switch (device) {
case SND_SST_DEVICE_HEADSET:
- if (snd_msic_ops.output_dev_id == STEREO_HEADPHONE) {
- sst_sc_reg_access(sc_access2, PMIC_READ_MODIFY, 2);
- sst_sc_reg_access(sc_access3, PMIC_WRITE, 2);
- sst_sc_reg_access(sc_access4, PMIC_READ_MODIFY, 3);
- } else {
- sst_sc_reg_access(sc_access23, PMIC_READ_MODIFY, 2);
- sst_sc_reg_access(sc_access3, PMIC_WRITE, 2);
- sst_sc_reg_access(sc_access43, PMIC_READ_MODIFY, 3);
- }
snd_msic_ops.pb_on = 1;
+ snd_msic_ops.pbhs_on = 1;
+ if (snd_msic_ops.output_dev_id == STEREO_HEADPHONE) {
+ sst_sc_reg_access(vhs, PMIC_WRITE, 2);
+ sst_sc_reg_access(hsdac, PMIC_READ_MODIFY, 3);
+ sst_sc_reg_access(hs_filter, PMIC_WRITE, 2);
+ sst_sc_reg_access(hs_enable, PMIC_READ_MODIFY, 4);
+ } else {
+ sst_sc_reg_access(epdac, PMIC_READ_MODIFY, 2);
+ sst_sc_reg_access(hs_filter, PMIC_WRITE, 2);
+ sst_sc_reg_access(ep_enable, PMIC_READ_MODIFY, 3);
+ }
+ if (snd_msic_ops.lineout_dev_id == HEADSET)
+ msic_set_selected_lineout_dev(HEADSET);
break;
-
case SND_SST_DEVICE_IHF:
- sst_sc_reg_access(sc_access_vihf, PMIC_WRITE, 1);
- sst_sc_reg_access(sc_access22, PMIC_READ_MODIFY, 3);
- sst_sc_reg_access(sc_access32, PMIC_READ_MODIFY, 1);
- sst_sc_reg_access(sc_access42, PMIC_READ_MODIFY, 2);
+ snd_msic_ops.pb_on = 1;
+ sst_sc_reg_access(vihf, PMIC_WRITE, 1);
+ sst_sc_reg_access(ihf_filter, PMIC_READ_MODIFY, 3);
+ sst_sc_reg_access(ihf_en, PMIC_READ_MODIFY, 1);
+ sst_sc_reg_access(ihf_unmute, PMIC_READ_MODIFY, 2);
+ if (snd_msic_ops.lineout_dev_id == IHF)
+ msic_set_selected_lineout_dev(IHF);
break;
case SND_SST_DEVICE_VIBRA:
- sst_sc_reg_access(sc_access_vib, PMIC_READ_MODIFY, 2);
+ snd_msic_ops.pb_on = 1;
+ sst_sc_reg_access(vib1_en, PMIC_READ_MODIFY, 2);
+ if (snd_msic_ops.lineout_dev_id == VIBRA1)
+ msic_set_selected_lineout_dev(VIBRA1);
break;
case SND_SST_DEVICE_HAPTIC:
- sst_sc_reg_access(sc_access_hap, PMIC_READ_MODIFY, 2);
+ snd_msic_ops.pb_on = 1;
+ sst_sc_reg_access(vib2_en, PMIC_READ_MODIFY, 2);
+ if (snd_msic_ops.lineout_dev_id == VIBRA2)
+ msic_set_selected_lineout_dev(VIBRA2);
break;
default:
pr_warn("Wrong Device %d, selected %d\n",
device, snd_msic_ops.output_dev_id);
}
- return sst_sc_reg_access(sc_access_pcm2, PMIC_READ_MODIFY, 1);
+ return sst_sc_reg_access(pcm2_en, PMIC_READ_MODIFY, 1);
}
static int msic_power_up_cp(unsigned int device)
{
- struct sc_reg_access sc_access[] = {
+ struct sc_reg_access vaud[] = {
/* turn on the audio power supplies */
- {0x0DB, 0x05, 0},
- /* VHSP */
- {0x0DC, 0xFF, 0},
- /* VHSN */
- {0x0DD, 0x3F, 0},
- /* turn on PLL */
- {0x240, 0x21, 0},
-
- /* Turn on DMIC supply */
- {0x247, 0xA0, 0x0},
- {0x240, 0x21, 0x0},
- {0x24C, 0x10, 0x0},
-
- /* mic demux enable */
- {0x245, 0x3F, 0x0},
- {0x246, 0x7, 0x0},
-
+ {0x0DB, 0x07, 0},
};
- struct sc_reg_access sc_access_amic[] = {
- /* turn on the audio power supplies */
- {0x0DB, 0x05, 0},
- /* VHSP */
- {0x0DC, 0xFF, 0},
- /* VHSN */
- {0x0DD, 0x3F, 0},
+ struct sc_reg_access pll[] = {
/* turn on PLL */
- {0x240, 0x21, 0},
- /*ADC EN*/
- {0x248, 0x05, 0x0},
- {0x24C, 0x76, 0x0},
- /*MIC EN*/
- {0x249, 0x09, 0x0},
- {0x24A, 0x09, 0x0},
+ {0x240, 0x20, 0},
+ };
+ struct sc_reg_access dmic_bias[] = {
/* Turn on AMIC supply */
- {0x247, 0xFC, 0x0},
+ {0x247, 0xA0, 0xA0},
+ };
+ struct sc_reg_access dmic[] = {
+ /* mic demux enable */
+ {0x245, 0x3F, 0x3F},
+ {0x246, 0x07, 0x07},
};
- struct sc_reg_access sc_access2[] = {
+ struct sc_reg_access amic_bias[] = {
+ /* Turn on AMIC supply */
+ {0x247, 0xFC, 0xFC},
+ };
+ struct sc_reg_access amic[] = {
+ /*MIC EN*/
+ {0x249, 0x01, 0x01},
+ {0x24A, 0x01, 0x01},
+ /*ADC EN*/
+ {0x248, 0x05, 0x0F},
+
+ };
+ struct sc_reg_access pcm2[] = {
/* enable pcm 2 */
{0x27C, 0x1, 0x1},
};
- struct sc_reg_access sc_access3[] = {
+ struct sc_reg_access tx_on[] = {
/*wait for mic to stabalize before turning on audio channels*/
{0x24F, 0x3C, 0x0},
};
@@ -271,42 +526,161 @@
}
pr_debug("powering up cp....%d\n", snd_msic_ops.input_dev_id);
- sst_sc_reg_access(sc_access2, PMIC_READ_MODIFY, 1);
+ sst_sc_reg_access(vaud, PMIC_WRITE, 1);
+ msleep(500);/*FIXME need optimzed value here*/
+ sst_sc_reg_access(pll, PMIC_WRITE, 1);
+ msleep(1);
snd_msic_ops.cap_on = 1;
- if (snd_msic_ops.input_dev_id == AMIC)
- sst_sc_reg_access(sc_access_amic, PMIC_WRITE, 9);
- else
- sst_sc_reg_access(sc_access, PMIC_WRITE, 9);
- return sst_sc_reg_access(sc_access3, PMIC_WRITE, 1);
-
+ if (snd_msic_ops.input_dev_id == AMIC) {
+ sst_sc_reg_access(amic_bias, PMIC_READ_MODIFY, 1);
+ msleep(1);
+ sst_sc_reg_access(amic, PMIC_READ_MODIFY, 3);
+ } else {
+ sst_sc_reg_access(dmic_bias, PMIC_READ_MODIFY, 1);
+ msleep(1);
+ sst_sc_reg_access(dmic, PMIC_READ_MODIFY, 2);
+ }
+ msleep(1);
+ sst_sc_reg_access(tx_on, PMIC_WRITE, 1);
+ return sst_sc_reg_access(pcm2, PMIC_READ_MODIFY, 1);
}
static int msic_power_down(void)
{
- int retval = 0;
+ struct sc_reg_access power_dn[] = {
+ /* VHSP */
+ {0x0DC, 0xC4, 0},
+ /* VHSN */
+ {0x0DD, 0x04, 0},
+ /* VIHF */
+ {0x0C9, 0x24, 0},
+ };
+ struct sc_reg_access pll[] = {
+ /* turn off PLL*/
+ {0x240, 0x00, 0x0},
+ };
+ struct sc_reg_access vaud[] = {
+ /* turn off VAUD*/
+ {0x0DB, 0x04, 0},
+ };
pr_debug("powering dn msic\n");
+ snd_msic_ops.pbhs_on = 0;
snd_msic_ops.pb_on = 0;
snd_msic_ops.cap_on = 0;
- return retval;
+ sst_sc_reg_access(power_dn, PMIC_WRITE, 3);
+ msleep(1);
+ sst_sc_reg_access(pll, PMIC_WRITE, 1);
+ msleep(1);
+ sst_sc_reg_access(vaud, PMIC_WRITE, 1);
+ return 0;
}
-static int msic_power_down_pb(void)
+static int msic_power_down_pb(unsigned int device)
{
- int retval = 0;
+ struct sc_reg_access drv_enable[] = {
+ {0x25D, 0x00, 0x00},
+ };
+ struct sc_reg_access hs_mute[] = {
+ {0x259, 0x80, 0x80},
+ {0x25A, 0x80, 0x80},
+ {0x26C, 0x02, 0x02},
+ };
+ struct sc_reg_access hs_off[] = {
+ {0x257, 0x00, 0x03},
+ {0x250, 0x00, 0x30},
+ {0x382, 0x00, 0x40},
+ };
+ struct sc_reg_access ihf_mute[] = {
+ {0x25B, 0x80, 0x80},
+ {0x25C, 0x80, 0x80},
+ };
+ struct sc_reg_access ihf_off[] = {
+ {0x257, 0x00, 0x0C},
+ {0x251, 0x00, 0x03},
+ };
+ struct sc_reg_access vib1_off[] = {
+ {0x264, 0x00, 0x82},
+ };
+ struct sc_reg_access vib2_off[] = {
+ {0x26A, 0x00, 0x82},
+ };
+ struct sc_reg_access lout_off[] = {
+ {0x25e, 0x66, 0x00},
+ };
+ struct sc_reg_access pmode_disable[] = {
+ {0x381, 0x00, 0x10},
+ };
- pr_debug("powering dn pb....\n");
- snd_msic_ops.pb_on = 0;
- return retval;
+
+
+ pr_debug("powering dn pb for device %d\n", device);
+ switch (device) {
+ case SND_SST_DEVICE_HEADSET:
+ snd_msic_ops.pbhs_on = 0;
+ sst_sc_reg_access(hs_mute, PMIC_READ_MODIFY, 3);
+ drv_enable[0].mask = 0x43;
+ sst_sc_reg_access(drv_enable, PMIC_READ_MODIFY, 1);
+ sst_sc_reg_access(hs_off, PMIC_READ_MODIFY, 3);
+ if (snd_msic_ops.lineout_dev_id == HEADSET)
+ sst_sc_reg_access(lout_off, PMIC_WRITE, 1);
+ break;
+
+ case SND_SST_DEVICE_IHF:
+ sst_sc_reg_access(ihf_mute, PMIC_READ_MODIFY, 2);
+ drv_enable[0].mask = 0x0C;
+ sst_sc_reg_access(drv_enable, PMIC_READ_MODIFY, 1);
+ sst_sc_reg_access(ihf_off, PMIC_READ_MODIFY, 2);
+ if (snd_msic_ops.lineout_dev_id == IHF) {
+ sst_sc_reg_access(lout_off, PMIC_WRITE, 1);
+ sst_sc_reg_access(pmode_disable, PMIC_READ_MODIFY, 1);
+ }
+ break;
+
+ case SND_SST_DEVICE_VIBRA:
+ sst_sc_reg_access(vib1_off, PMIC_READ_MODIFY, 1);
+ drv_enable[0].mask = 0x10;
+ sst_sc_reg_access(drv_enable, PMIC_READ_MODIFY, 1);
+ if (snd_msic_ops.lineout_dev_id == VIBRA1)
+ sst_sc_reg_access(lout_off, PMIC_WRITE, 1);
+ break;
+
+ case SND_SST_DEVICE_HAPTIC:
+ sst_sc_reg_access(vib2_off, PMIC_READ_MODIFY, 1);
+ drv_enable[0].mask = 0x20;
+ sst_sc_reg_access(drv_enable, PMIC_READ_MODIFY, 1);
+ if (snd_msic_ops.lineout_dev_id == VIBRA2)
+ sst_sc_reg_access(lout_off, PMIC_WRITE, 1);
+ break;
+ }
+ return 0;
}
-static int msic_power_down_cp(void)
+static int msic_power_down_cp(unsigned int device)
{
- int retval = 0;
+ struct sc_reg_access dmic[] = {
+ {0x247, 0x00, 0xA0},
+ {0x245, 0x00, 0x38},
+ {0x246, 0x00, 0x07},
+ };
+ struct sc_reg_access amic[] = {
+ {0x248, 0x00, 0x05},
+ {0x249, 0x00, 0x01},
+ {0x24A, 0x00, 0x01},
+ {0x247, 0x00, 0xA3},
+ };
+ struct sc_reg_access tx_off[] = {
+ {0x24F, 0x00, 0x3C},
+ };
pr_debug("powering dn cp....\n");
snd_msic_ops.cap_on = 0;
- return retval;
+ sst_sc_reg_access(tx_off, PMIC_READ_MODIFY, 1);
+ if (snd_msic_ops.input_dev_id == DMIC)
+ sst_sc_reg_access(dmic, PMIC_READ_MODIFY, 3);
+ else
+ sst_sc_reg_access(amic, PMIC_READ_MODIFY, 4);
+ return 0;
}
static int msic_set_selected_output_dev(u8 value)
@@ -315,7 +689,7 @@
pr_debug("msic set selected output:%d\n", value);
snd_msic_ops.output_dev_id = value;
- if (snd_msic_ops.pb_on)
+ if (snd_msic_ops.pbhs_on)
msic_power_up_pb(SND_SST_DEVICE_HEADSET);
return retval;
}
@@ -352,6 +726,57 @@
return retval;
}
+static int msic_set_hw_dmic_route(u8 hw_ch_index)
+{
+ struct sc_reg_access sc_access_router;
+ int retval = -EINVAL;
+
+ switch (hw_ch_index) {
+ case HW_CH0:
+ sc_access_router.reg_addr = AUDIOMUX12;
+ sc_access_router.value = snd_msic_ops.hw_dmic_map[0];
+ sc_access_router.mask = (MASK2 | MASK1 | MASK0);
+ pr_debug("hw_ch0. value = 0x%x\n",
+ sc_access_router.value);
+ retval = sst_sc_reg_access(&sc_access_router,
+ PMIC_READ_MODIFY, 1);
+ break;
+
+ case HW_CH1:
+ sc_access_router.reg_addr = AUDIOMUX12;
+ sc_access_router.value = (snd_msic_ops.hw_dmic_map[1]) << 4;
+ sc_access_router.mask = (MASK6 | MASK5 | MASK4);
+ pr_debug("### hw_ch1. value = 0x%x\n",
+ sc_access_router.value);
+ retval = sst_sc_reg_access(&sc_access_router,
+ PMIC_READ_MODIFY, 1);
+ break;
+
+ case HW_CH2:
+ sc_access_router.reg_addr = AUDIOMUX34;
+ sc_access_router.value = snd_msic_ops.hw_dmic_map[2];
+ sc_access_router.mask = (MASK2 | MASK1 | MASK0);
+ pr_debug("hw_ch2. value = 0x%x\n",
+ sc_access_router.value);
+ retval = sst_sc_reg_access(&sc_access_router,
+ PMIC_READ_MODIFY, 1);
+ break;
+
+ case HW_CH3:
+ sc_access_router.reg_addr = AUDIOMUX34;
+ sc_access_router.value = (snd_msic_ops.hw_dmic_map[3]) << 4;
+ sc_access_router.mask = (MASK6 | MASK5 | MASK4);
+ pr_debug("hw_ch3. value = 0x%x\n",
+ sc_access_router.value);
+ retval = sst_sc_reg_access(&sc_access_router,
+ PMIC_READ_MODIFY, 1);
+ break;
+ }
+
+ return retval;
+}
+
+
static int msic_set_pcm_voice_params(void)
{
return 0;
@@ -392,9 +817,215 @@
return 0;
}
+static int msic_set_headset_state(int state)
+{
+ struct sc_reg_access hs_enable[] = {
+ {0x25D, 0x03, 0x03},
+ };
+
+ if (state)
+ /*enable*/
+ sst_sc_reg_access(hs_enable, PMIC_READ_MODIFY, 1);
+ else {
+ hs_enable[0].value = 0;
+ sst_sc_reg_access(hs_enable, PMIC_READ_MODIFY, 1);
+ }
+ return 0;
+}
+
+static int msic_enable_mic_bias(void)
+{
+ struct sc_reg_access jack_interrupt_reg[] = {
+ {0x0DB, 0x07, 0x00},
+
+ };
+ struct sc_reg_access jack_bias_reg[] = {
+ {0x247, 0x0C, 0x0C},
+ };
+
+ sst_sc_reg_access(jack_interrupt_reg, PMIC_WRITE, 1);
+ sst_sc_reg_access(jack_bias_reg, PMIC_READ_MODIFY, 1);
+ return 0;
+}
+
+static int msic_disable_mic_bias(void)
+{
+ if (snd_msic_ops.jack_interrupt_status == true)
+ return 0;
+ if (!(snd_msic_ops.pb_on || snd_msic_ops.cap_on))
+ msic_power_down();
+ return 0;
+}
+
+static int msic_disable_jack_btn(void)
+{
+ struct sc_reg_access btn_disable[] = {
+ {0x26C, 0x00, 0x01}
+ };
+
+ if (!(snd_msic_ops.pb_on || snd_msic_ops.cap_on))
+ msic_power_down();
+ snd_msic_ops.jack_interrupt_status = false;
+ return sst_sc_reg_access(btn_disable, PMIC_READ_MODIFY, 1);
+}
+
+static int msic_enable_jack_btn(void)
+{
+ struct sc_reg_access btn_enable[] = {
+ {0x26b, 0x77, 0x00},
+ {0x26C, 0x01, 0x00},
+ };
+ return sst_sc_reg_access(btn_enable, PMIC_WRITE, 2);
+}
+static int msic_convert_adc_to_mvolt(unsigned int mic_bias)
+{
+ return (ADC_ONE_LSB_MULTIPLIER * mic_bias) / 1000;
+}
+int msic_get_headset_state(int mic_bias)
+{
+ struct sc_reg_access msic_hs_toggle[] = {
+ {0x070, 0x00, 0x01},
+ };
+ if (mic_bias >= 0 && mic_bias < 400) {
+
+ pr_debug("Detected Headphone!!!\n");
+ sst_sc_reg_access(msic_hs_toggle, PMIC_READ_MODIFY, 1);
+
+ } else if (mic_bias > 400 && mic_bias < 650) {
+
+ pr_debug("Detected American headset\n");
+ msic_hs_toggle[0].value = 0x01;
+ sst_sc_reg_access(msic_hs_toggle, PMIC_READ_MODIFY, 1);
+
+ } else if (mic_bias >= 650 && mic_bias < 2000) {
+
+ pr_debug("Detected Headset!!!\n");
+ sst_sc_reg_access(msic_hs_toggle, PMIC_READ_MODIFY, 1);
+ /*power on jack and btn*/
+ snd_msic_ops.jack_interrupt_status = true;
+ msic_enable_jack_btn();
+ msic_enable_mic_bias();
+ return SND_JACK_HEADSET;
+
+ } else
+ pr_debug("Detected Open Cable!!!\n");
+
+ return SND_JACK_HEADPHONE;
+}
+
+static int msic_get_mic_bias(void *arg)
+{
+ struct snd_intelmad *intelmad_drv = (struct snd_intelmad *)arg;
+ u16 adc_adr = intelmad_drv->adc_address;
+ u16 adc_val;
+ int ret;
+ struct sc_reg_access adc_ctrl3[2] = {
+ {0x1C2, 0x05, 0x0},
+ };
+
+ struct sc_reg_access audio_adc_reg1 = {0,};
+ struct sc_reg_access audio_adc_reg2 = {0,};
+
+ msic_enable_mic_bias();
+ /* Enable the msic for conversion before reading */
+ ret = sst_sc_reg_access(adc_ctrl3, PMIC_WRITE, 1);
+ if (ret)
+ return ret;
+ adc_ctrl3[0].value = 0x04;
+ /* Re-toggle the RRDATARD bit */
+ ret = sst_sc_reg_access(adc_ctrl3, PMIC_WRITE, 1);
+ if (ret)
+ return ret;
+
+ audio_adc_reg1.reg_addr = adc_adr;
+ /* Read the higher bits of data */
+ msleep(1000);
+ ret = sst_sc_reg_access(&audio_adc_reg1, PMIC_READ, 1);
+ if (ret)
+ return ret;
+ pr_debug("adc read value %x", audio_adc_reg1.value);
+
+ /* Shift bits to accomodate the lower two data bits */
+ adc_val = (audio_adc_reg1.value << 2);
+ adc_adr++;
+ audio_adc_reg2. reg_addr = adc_adr;
+ ret = sst_sc_reg_access(&audio_adc_reg2, PMIC_READ, 1);
+ if (ret)
+ return ret;
+ pr_debug("adc read value %x", audio_adc_reg2.value);
+
+ /* Adding lower two bits to the higher bits */
+ audio_adc_reg2.value &= 03;
+ adc_val += audio_adc_reg2.value;
+
+ pr_debug("ADC value 0x%x", adc_val);
+ msic_disable_mic_bias();
+ return adc_val;
+}
+
+static void msic_pmic_irq_cb(void *cb_data, u8 intsts)
+{
+ struct mad_jack *mjack = NULL;
+ unsigned int present = 0, jack_event_flag = 0, buttonpressflag = 0;
+ struct snd_intelmad *intelmaddata = cb_data;
+ int retval = 0;
+
+ pr_debug("value returned = 0x%x\n", intsts);
+
+ if (snd_msic_ops.card_status == SND_CARD_UN_INIT) {
+ retval = msic_init_card();
+ if (retval)
+ return;
+ }
+
+ mjack = &intelmaddata->jack[0];
+ if (intsts & 0x1) {
+ pr_debug("MAD short_push detected\n");
+ present = SND_JACK_BTN_0;
+ jack_event_flag = buttonpressflag = 1;
+ mjack->jack.type = SND_JACK_BTN_0;
+ mjack->jack.key[0] = BTN_0 ;
+ }
+
+ if (intsts & 0x2) {
+ pr_debug(":MAD long_push detected\n");
+ jack_event_flag = buttonpressflag = 1;
+ mjack->jack.type = present = SND_JACK_BTN_1;
+ mjack->jack.key[1] = BTN_1;
+ }
+
+ if (intsts & 0x4) {
+ unsigned int mic_bias;
+ jack_event_flag = 1;
+ buttonpressflag = 0;
+ mic_bias = msic_get_mic_bias(intelmaddata);
+ pr_debug("mic_bias = %d\n", mic_bias);
+ mic_bias = msic_convert_adc_to_mvolt(mic_bias);
+ pr_debug("mic_bias after conversion = %d mV\n", mic_bias);
+ mjack->jack_dev_state = msic_get_headset_state(mic_bias);
+ mjack->jack.type = present = mjack->jack_dev_state;
+ }
+
+ if (intsts & 0x8) {
+ mjack->jack.type = mjack->jack_dev_state;
+ present = 0;
+ jack_event_flag = 1;
+ buttonpressflag = 0;
+ msic_disable_jack_btn();
+ msic_disable_mic_bias();
+ }
+ if (jack_event_flag)
+ sst_mad_send_jack_report(&mjack->jack,
+ buttonpressflag, present);
+}
+
+
+
struct snd_pmic_ops snd_msic_ops = {
.set_input_dev = msic_set_selected_input_dev,
.set_output_dev = msic_set_selected_output_dev,
+ .set_lineout_dev = msic_set_selected_lineout_dev,
+ .set_hw_dmic_route = msic_set_hw_dmic_route,
.set_mute = msic_set_mute,
.get_mute = msic_get_mute,
.set_vol = msic_set_vol,
@@ -408,5 +1039,9 @@
.power_up_pmic_cp = msic_power_up_cp,
.power_down_pmic_pb = msic_power_down_pb,
.power_down_pmic_cp = msic_power_down_cp,
- .power_down_pmic = msic_power_down,
+ .power_down_pmic = msic_power_down,
+ .pmic_irq_cb = msic_pmic_irq_cb,
+ .pmic_jack_enable = msic_enable_mic_bias,
+ .pmic_get_mic_bias = msic_get_mic_bias,
+ .pmic_set_headset_state = msic_set_headset_state,
};
diff --git a/drivers/staging/intel_sst/intelmid_pvt.c b/drivers/staging/intel_sst/intelmid_pvt.c
index 3ba9daf..90e0e64 100644
--- a/drivers/staging/intel_sst/intelmid_pvt.c
+++ b/drivers/staging/intel_sst/intelmid_pvt.c
@@ -31,7 +31,6 @@
#include <sound/core.h>
#include <sound/control.h>
#include <sound/pcm.h>
-#include "jack.h"
#include "intel_sst.h"
#include "intel_sst_ioctl.h"
#include "intelmid_snd_control.h"
diff --git a/drivers/staging/intel_sst/intelmid_snd_control.h b/drivers/staging/intel_sst/intelmid_snd_control.h
index a4565f3..06ad3a1 100644
--- a/drivers/staging/intel_sst/intelmid_snd_control.h
+++ b/drivers/staging/intel_sst/intelmid_snd_control.h
@@ -80,6 +80,13 @@
HS_MIC,
IN_UNDEFINED
};
+enum SND_LINE_OUT_DEVICE {
+ HEADSET,
+ IHF,
+ VIBRA1,
+ VIBRA2,
+ NONE,
+};
enum SND_OUTPUT_DEVICE {
STEREO_HEADPHONE,
@@ -104,6 +111,8 @@
PMIC_SND_RIGHT_SPEAKER_MUTE = 0x0015,
PMIC_SND_RECEIVER_VOL = 0x0016,
PMIC_SND_RECEIVER_MUTE = 0x0017,
+ PMIC_SND_LEFT_MASTER_VOL = 0x0018,
+ PMIC_SND_RIGHT_MASTER_VOL = 0x0019,
/* Other controls */
PMIC_SND_MUTE_ALL = 0x0020,
PMIC_MAX_CONTROLS = 0x0020,
diff --git a/drivers/staging/intel_sst/intelmid_v0_control.c b/drivers/staging/intel_sst/intelmid_v0_control.c
index 7756f8f..b8dfdb9 100644
--- a/drivers/staging/intel_sst/intelmid_v0_control.c
+++ b/drivers/staging/intel_sst/intelmid_v0_control.c
@@ -30,9 +30,10 @@
#include <linux/pci.h>
#include <linux/file.h>
+#include <sound/control.h>
#include "intel_sst.h"
#include "intelmid_snd_control.h"
-
+#include "intelmid.h"
enum _reg_v1 {
VOICEPORT1 = 0x180,
@@ -64,6 +65,7 @@
};
int rev_id = 0x20;
+static bool jack_det_enabled;
/****
* fs_init_card - initialize the sound card
@@ -157,7 +159,7 @@
return fs_enable_audiodac(UNMUTE);
}
-static int fs_power_down_pb(void)
+static int fs_power_down_pb(unsigned int device)
{
struct sc_reg_access sc_access[] = {
{POWERCTRL1, 0x00, 0xC6},
@@ -195,7 +197,7 @@
return sst_sc_reg_access(sc_access, PMIC_READ_MODIFY, 2);
}
-static int fs_power_down_cp(void)
+static int fs_power_down_cp(unsigned int device)
{
struct sc_reg_access sc_access[] = {
{POWERCTRL2, 0x00, 0x03},
@@ -753,6 +755,90 @@
return retval;
}
+static void fs_pmic_irq_enable(void *data)
+{
+ struct snd_intelmad *intelmaddata = data;
+ struct sc_reg_access sc_access[] = {
+ {0x187, 0x00, MASK7},
+ {0x188, 0x10, MASK4},
+ {0x18b, 0x10, MASK4},
+ };
+
+ struct sc_reg_access sc_access_write[] = {
+ {0x198, 0x00, 0x0},
+ };
+ pr_debug("Audio interrupt enable\n");
+ sst_sc_reg_access(sc_access, PMIC_READ_MODIFY, 3);
+ sst_sc_reg_access(sc_access_write, PMIC_WRITE, 1);
+
+ intelmaddata->jack[0].jack_status = 0;
+ /*intelmaddata->jack[1].jack_status = 0;*/
+
+ jack_det_enabled = true;
+ return;
+}
+
+static void fs_pmic_irq_cb(void *cb_data, u8 value)
+{
+ struct mad_jack *mjack = NULL;
+ struct snd_intelmad *intelmaddata = cb_data;
+ unsigned int present = 0, jack_event_flag = 0, buttonpressflag = 0;
+
+ mjack = &intelmaddata->jack[0];
+
+ if (value & 0x4) {
+ if (!jack_det_enabled)
+ fs_pmic_irq_enable(intelmaddata);
+
+ /* send headphone detect */
+ pr_debug(":MAD headphone %d\n", value & 0x4);
+ present = !(mjack->jack_status);
+ mjack->jack_status = present;
+ jack_event_flag = 1;
+ mjack->jack.type = SND_JACK_HEADPHONE;
+ }
+
+ if (value & 0x2) {
+ /* send short push */
+ pr_debug(":MAD short push %d\n", value & 0x2);
+ present = 1;
+ jack_event_flag = 1;
+ buttonpressflag = 1;
+ mjack->jack.type = MID_JACK_HS_SHORT_PRESS;
+ }
+
+ if (value & 0x1) {
+ /* send long push */
+ pr_debug(":MAD long push %d\n", value & 0x1);
+ present = 1;
+ jack_event_flag = 1;
+ buttonpressflag = 1;
+ mjack->jack.type = MID_JACK_HS_LONG_PRESS;
+ }
+
+ if (value & 0x8) {
+ if (!jack_det_enabled)
+ fs_pmic_irq_enable(intelmaddata);
+ /* send headset detect */
+ pr_debug(":MAD headset = %d\n", value & 0x8);
+ present = !(mjack->jack_status);
+ mjack->jack_status = present;
+ jack_event_flag = 1;
+ mjack->jack.type = SND_JACK_HEADSET;
+ }
+
+
+ if (jack_event_flag)
+ sst_mad_send_jack_report(&mjack->jack,
+ buttonpressflag, present);
+
+ return;
+}
+static int fs_jack_enable(void)
+{
+ return 0;
+}
+
struct snd_pmic_ops snd_pmic_ops_fs = {
.set_input_dev = fs_set_selected_input_dev,
.set_output_dev = fs_set_selected_output_dev,
@@ -765,9 +851,16 @@
.set_pcm_voice_params = fs_set_pcm_voice_params,
.set_voice_port = fs_set_voice_port,
.set_audio_port = fs_set_audio_port,
- .power_up_pmic_pb = fs_power_up_pb,
- .power_up_pmic_cp = fs_power_up_cp,
- .power_down_pmic_pb = fs_power_down_pb,
- .power_down_pmic_cp = fs_power_down_cp,
- .power_down_pmic = fs_power_down,
+ .power_up_pmic_pb = fs_power_up_pb,
+ .power_up_pmic_cp = fs_power_up_cp,
+ .power_down_pmic_pb = fs_power_down_pb,
+ .power_down_pmic_cp = fs_power_down_cp,
+ .power_down_pmic = fs_power_down,
+ .pmic_irq_cb = fs_pmic_irq_cb,
+ /*
+ * Jack detection enabling
+ * need be delayed till first IRQ happen.
+ */
+ .pmic_irq_enable = NULL,
+ .pmic_jack_enable = fs_jack_enable,
};
diff --git a/drivers/staging/intel_sst/intelmid_v1_control.c b/drivers/staging/intel_sst/intelmid_v1_control.c
index 1ea8142..9d00728 100644
--- a/drivers/staging/intel_sst/intelmid_v1_control.c
+++ b/drivers/staging/intel_sst/intelmid_v1_control.c
@@ -32,7 +32,6 @@
#include <linux/file.h>
#include <asm/mrst.h>
#include <sound/pcm.h>
-#include "jack.h"
#include <sound/pcm_params.h>
#include <sound/control.h>
#include <sound/initval.h>
@@ -212,7 +211,7 @@
return mx_enable_audiodac(UNMUTE);
}
-static int mx_power_down_pb(void)
+static int mx_power_down_pb(unsigned int device)
{
struct sc_reg_access sc_access[3];
int retval = 0;
@@ -255,7 +254,7 @@
return sst_sc_reg_access(sc_access, PMIC_READ_MODIFY, 2);
}
-static int mx_power_down_cp(void)
+static int mx_power_down_cp(unsigned int device)
{
struct sc_reg_access sc_access[] = {
{ENABLE_OPDEV_CTRL, 0x00, MASK1|MASK0},
@@ -832,6 +831,129 @@
return retval;
}
+static u8 mx_get_jack_status(void)
+{
+ struct sc_reg_access sc_access_read = {0,};
+
+ sc_access_read.reg_addr = 0x201;
+ sst_sc_reg_access(&sc_access_read, PMIC_READ, 1);
+ pr_debug("value returned = 0x%x\n", sc_access_read.value);
+ return sc_access_read.value;
+}
+
+static void mx_pmic_irq_enable(void *data)
+{
+ struct snd_intelmad *intelmaddata = data;
+
+ intelmaddata->jack_prev_state = 0xc0;
+ return;
+}
+
+static void mx_pmic_irq_cb(void *cb_data, u8 intsts)
+{
+ u8 jack_cur_status, jack_prev_state = 0;
+ struct mad_jack *mjack = NULL;
+ unsigned int present = 0, jack_event_flag = 0, buttonpressflag = 0;
+ time_t timediff;
+ struct snd_intelmad *intelmaddata = cb_data;
+
+ mjack = &intelmaddata->jack[0];
+ if (intsts & 0x2) {
+ jack_cur_status = mx_get_jack_status();
+ jack_prev_state = intelmaddata->jack_prev_state;
+ if ((jack_prev_state == 0xc0) && (jack_cur_status == 0x40)) {
+ /*headset insert detected. */
+ pr_debug("MAD headset inserted\n");
+ present = 1;
+ jack_event_flag = 1;
+ mjack->jack_status = 1;
+ mjack->jack.type = SND_JACK_HEADSET;
+ }
+
+ if ((jack_prev_state == 0xc0) && (jack_cur_status == 0x00)) {
+ /* headphone insert detected. */
+ pr_debug("MAD headphone inserted\n");
+ present = 1;
+ jack_event_flag = 1;
+ mjack->jack.type = SND_JACK_HEADPHONE;
+ }
+
+ if ((jack_prev_state == 0x40) && (jack_cur_status == 0xc0)) {
+ /* headset remove detected. */
+ pr_debug("MAD headset removed\n");
+
+ present = 0;
+ jack_event_flag = 1;
+ mjack->jack_status = 0;
+ mjack->jack.type = SND_JACK_HEADSET;
+ }
+
+ if ((jack_prev_state == 0x00) && (jack_cur_status == 0xc0)) {
+ /* headphone remove detected. */
+ pr_debug("MAD headphone removed\n");
+ present = 0;
+ jack_event_flag = 1;
+ mjack->jack.type = SND_JACK_HEADPHONE;
+ }
+
+ if ((jack_prev_state == 0x40) && (jack_cur_status == 0x00)) {
+ /* button pressed */
+ do_gettimeofday(&mjack->buttonpressed);
+ pr_debug("MAD button press detected\n");
+ }
+
+ if ((jack_prev_state == 0x00) && (jack_cur_status == 0x40)) {
+ if (mjack->jack_status) {
+ /*button pressed */
+ do_gettimeofday(
+ &mjack->buttonreleased);
+ /*button pressed */
+ pr_debug("MAD Button Released detected\n");
+ timediff = mjack->buttonreleased.tv_sec -
+ mjack->buttonpressed.tv_sec;
+ buttonpressflag = 1;
+
+ if (timediff > 1) {
+ pr_debug("MAD long press dtd\n");
+ /* send headphone detect/undetect */
+ present = 1;
+ jack_event_flag = 1;
+ mjack->jack.type =
+ MID_JACK_HS_LONG_PRESS;
+ } else {
+ pr_debug("MAD short press dtd\n");
+ /* send headphone detect/undetect */
+ present = 1;
+ jack_event_flag = 1;
+ mjack->jack.type =
+ MID_JACK_HS_SHORT_PRESS;
+ }
+ } else {
+ /***workaround for maxim
+ hw issue,0x00 t 0x40 is not
+ a valid transiton for Headset insertion */
+ /*headset insert detected. */
+ pr_debug("MAD headset inserted\n");
+ present = 1;
+ jack_event_flag = 1;
+ mjack->jack_status = 1;
+ mjack->jack.type = SND_JACK_HEADSET;
+ }
+ }
+ intelmaddata->jack_prev_state = jack_cur_status;
+ pr_debug("mx_pmic_irq_cb prv_state= 0x%x\n",
+ intelmaddata->jack_prev_state);
+ }
+
+ if (jack_event_flag)
+ sst_mad_send_jack_report(&mjack->jack,
+ buttonpressflag, present);
+}
+static int mx_jack_enable(void)
+{
+ return 0;
+}
+
struct snd_pmic_ops snd_pmic_ops_mx = {
.set_input_dev = mx_set_selected_input_dev,
.set_output_dev = mx_set_selected_output_dev,
@@ -844,10 +966,13 @@
.set_pcm_voice_params = mx_set_pcm_voice_params,
.set_voice_port = mx_set_voice_port,
.set_audio_port = mx_set_audio_port,
- .power_up_pmic_pb = mx_power_up_pb,
- .power_up_pmic_cp = mx_power_up_cp,
- .power_down_pmic_pb = mx_power_down_pb,
- .power_down_pmic_cp = mx_power_down_cp,
- .power_down_pmic = mx_power_down,
+ .power_up_pmic_pb = mx_power_up_pb,
+ .power_up_pmic_cp = mx_power_up_cp,
+ .power_down_pmic_pb = mx_power_down_pb,
+ .power_down_pmic_cp = mx_power_down_cp,
+ .power_down_pmic = mx_power_down,
+ .pmic_irq_cb = mx_pmic_irq_cb,
+ .pmic_irq_enable = mx_pmic_irq_enable,
+ .pmic_jack_enable = mx_jack_enable,
};
diff --git a/drivers/staging/intel_sst/intelmid_v2_control.c b/drivers/staging/intel_sst/intelmid_v2_control.c
index 3c6b3ab..000378a 100644
--- a/drivers/staging/intel_sst/intelmid_v2_control.c
+++ b/drivers/staging/intel_sst/intelmid_v2_control.c
@@ -28,11 +28,14 @@
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+#include <linux/gpio.h>
#include <linux/pci.h>
#include <linux/delay.h>
#include <linux/file.h>
+#include <sound/control.h>
#include "intel_sst.h"
#include "intelmid_snd_control.h"
+#include "intelmid.h"
enum reg_v3 {
VAUDIOCNT = 0x51,
@@ -82,8 +85,15 @@
HPLMIXSEL = 0x12b,
HPRMIXSEL = 0x12c,
LOANTIPOP = 0x12d,
+ AUXDBNC = 0x12f,
};
+static void nc_set_amp_power(int power)
+{
+ if (snd_pmic_ops_nc.gpio_amp)
+ gpio_set_value(snd_pmic_ops_nc.gpio_amp, power);
+}
+
/****
* nc_init_card - initialize the sound card
*
@@ -111,18 +121,20 @@
{VOICEVOL, 0x0e, 0},
{HPLVOL, 0x06, 0},
{HPRVOL, 0x06, 0},
- {MICCTRL, 0x41, 0x00},
+ {MICCTRL, 0x51, 0x00},
{ADCSAMPLERATE, 0x8B, 0x00},
{MICSELVOL, 0x5B, 0x00},
{LILSEL, 0x06, 0},
{LIRSEL, 0x46, 0},
{LOANTIPOP, 0x00, 0},
{DMICCTRL1, 0x40, 0},
+ {AUXDBNC, 0xff, 0},
};
snd_pmic_ops_nc.card_status = SND_CARD_INIT_DONE;
snd_pmic_ops_nc.master_mute = UNMUTE;
snd_pmic_ops_nc.mute_status = UNMUTE;
- sst_sc_reg_access(sc_access, PMIC_WRITE, 26);
+ sst_sc_reg_access(sc_access, PMIC_WRITE, 27);
+ mutex_init(&snd_pmic_ops_nc.lock);
pr_debug("init complete!!\n");
return 0;
}
@@ -169,6 +181,7 @@
return retval;
if (port == 0xFF)
return 0;
+ mutex_lock(&snd_pmic_ops_nc.lock);
nc_enable_audiodac(MUTE);
msleep(30);
@@ -209,8 +222,21 @@
msleep(30);
- return nc_enable_audiodac(UNMUTE);
+ snd_pmic_ops_nc.pb_on = 1;
+ /*
+ * There is a mismatch between Playback Sources and the enumerated
+ * values of output sources. This mismatch causes ALSA upper to send
+ * Item 1 for Internal Speaker, but the expected enumeration is 2! For
+ * now, treat MONO_EARPIECE and INTERNAL_SPKR identically and power up
+ * the needed resources
+ */
+ if (snd_pmic_ops_nc.output_dev_id == MONO_EARPIECE ||
+ snd_pmic_ops_nc.output_dev_id == INTERNAL_SPKR)
+ nc_set_amp_power(1);
+ nc_enable_audiodac(UNMUTE);
+ mutex_unlock(&snd_pmic_ops_nc.lock);
+ return 0;
}
static int nc_power_up_cp(unsigned int port)
@@ -270,7 +296,6 @@
int retval = 0;
struct sc_reg_access sc_access[5];
-
if (snd_pmic_ops_nc.card_status == SND_CARD_UN_INIT)
retval = nc_init_card();
if (retval)
@@ -280,6 +305,10 @@
pr_debug("powering dn nc_power_down ....\n");
+ if (snd_pmic_ops_nc.output_dev_id == MONO_EARPIECE ||
+ snd_pmic_ops_nc.output_dev_id == INTERNAL_SPKR)
+ nc_set_amp_power(0);
+
msleep(30);
sc_access[0].reg_addr = DRVPOWERCTRL;
@@ -316,7 +345,7 @@
return nc_enable_audiodac(UNMUTE);
}
-static int nc_power_down_pb(void)
+static int nc_power_down_pb(unsigned int device)
{
int retval = 0;
@@ -328,7 +357,7 @@
return retval;
pr_debug("powering dn pb....\n");
-
+ mutex_lock(&snd_pmic_ops_nc.lock);
nc_enable_audiodac(MUTE);
@@ -355,12 +384,14 @@
msleep(30);
- return nc_enable_audiodac(UNMUTE);
+ snd_pmic_ops_nc.pb_on = 0;
-
+ nc_enable_audiodac(UNMUTE);
+ mutex_unlock(&snd_pmic_ops_nc.lock);
+ return 0;
}
-static int nc_power_down_cp(void)
+static int nc_power_down_cp(unsigned int device)
{
struct sc_reg_access sc_access[] = {
{POWERCTRL1, 0x00, 0xBE},
@@ -498,11 +529,13 @@
{
struct sc_reg_access sc_access_HP[] = {
{LMUTE, 0x02, 0x06},
- {RMUTE, 0x02, 0x06}
+ {RMUTE, 0x02, 0x06},
+ {DRVPOWERCTRL, 0x06, 0x06},
};
struct sc_reg_access sc_access_IS[] = {
{LMUTE, 0x04, 0x06},
- {RMUTE, 0x04, 0x06}
+ {RMUTE, 0x04, 0x06},
+ {DRVPOWERCTRL, 0x00, 0x06},
};
int retval = 0;
@@ -512,17 +545,26 @@
if (retval)
return retval;
pr_debug("nc set selected output:%d\n", value);
+ mutex_lock(&snd_pmic_ops_nc.lock);
switch (value) {
case STEREO_HEADPHONE:
+ if (snd_pmic_ops_nc.pb_on)
+ sst_sc_reg_access(sc_access_HP+2, PMIC_WRITE, 1);
retval = sst_sc_reg_access(sc_access_HP, PMIC_WRITE, 2);
+ nc_set_amp_power(0);
break;
+ case MONO_EARPIECE:
case INTERNAL_SPKR:
- retval = sst_sc_reg_access(sc_access_IS, PMIC_WRITE, 2);
+ retval = sst_sc_reg_access(sc_access_IS, PMIC_WRITE, 3);
+ if (snd_pmic_ops_nc.pb_on)
+ nc_set_amp_power(1);
break;
default:
pr_err("rcvd illegal request: %d\n", value);
+ mutex_unlock(&snd_pmic_ops_nc.lock);
return -EINVAL;
}
+ mutex_unlock(&snd_pmic_ops_nc.lock);
return retval;
}
@@ -784,9 +826,8 @@
case PMIC_SND_LEFT_PB_VOL:
pr_debug("PMIC_SND_LEFT_HP_VOL %d\n", value);
sc_access[0].value = -value;
- sc_access[0].reg_addr = AUDIOLVOL;
- sc_access[0].mask =
- (MASK0|MASK1|MASK2|MASK3|MASK4|MASK5|MASK6);
+ sc_access[0].reg_addr = HPLVOL;
+ sc_access[0].mask = (MASK0|MASK1|MASK2|MASK3|MASK4);
entries = 1;
break;
@@ -794,15 +835,32 @@
pr_debug("PMIC_SND_RIGHT_HP_VOL value %d\n", value);
if (snd_pmic_ops_nc.num_channel == 1) {
sc_access[0].value = 0x04;
- sc_access[0].reg_addr = RMUTE;
+ sc_access[0].reg_addr = RMUTE;
sc_access[0].mask = MASK2;
} else {
+ sc_access[0].value = -value;
+ sc_access[0].reg_addr = HPRVOL;
+ sc_access[0].mask = (MASK0|MASK1|MASK2|MASK3|MASK4);
+ }
+ entries = 1;
+ break;
+
+ case PMIC_SND_LEFT_MASTER_VOL:
+ pr_debug("PMIC_SND_LEFT_MASTER_VOL value %d\n", value);
sc_access[0].value = -value;
- sc_access[0].reg_addr = AUDIORVOL;
+ sc_access[0].reg_addr = AUDIOLVOL;
+ sc_access[0].mask =
+ (MASK0|MASK1|MASK2|MASK3|MASK4|MASK5|MASK6);
+ entries = 1;
+ break;
+
+ case PMIC_SND_RIGHT_MASTER_VOL:
+ pr_debug("PMIC_SND_RIGHT_MASTER_VOL value %d\n", value);
+ sc_access[0].value = -value;
+ sc_access[0].reg_addr = AUDIORVOL;
sc_access[0].mask =
(MASK0|MASK1|MASK2|MASK3|MASK4|MASK5|MASK6);
entries = 1;
- }
break;
default:
@@ -831,7 +889,7 @@
pr_debug("Selecting AMIC\n");
sc_access[0].reg_addr = 0x107;
sc_access[0].value = 0x40;
- sc_access[0].mask = MASK6|MASK4|MASK3|MASK1|MASK0;
+ sc_access[0].mask = MASK6|MASK3|MASK1|MASK0;
sc_access[1].reg_addr = 0x10a;
sc_access[1].value = 0x40;
sc_access[1].mask = MASK6;
@@ -846,9 +904,9 @@
case HS_MIC:
pr_debug("Selecting HS_MIC\n");
- sc_access[0].reg_addr = 0x107;
- sc_access[0].mask = MASK6|MASK4|MASK3|MASK1|MASK0;
- sc_access[0].value = 0x10;
+ sc_access[0].reg_addr = MICCTRL;
+ sc_access[0].mask = MASK6|MASK3|MASK1|MASK0;
+ sc_access[0].value = 0x00;
sc_access[1].reg_addr = 0x109;
sc_access[1].mask = MASK6;
sc_access[1].value = 0x40;
@@ -858,13 +916,16 @@
sc_access[3].reg_addr = 0x105;
sc_access[3].value = 0x40;
sc_access[3].mask = MASK6;
- num_val = 4;
+ sc_access[4].reg_addr = ADCSAMPLERATE;
+ sc_access[4].mask = MASK7|MASK6|MASK5|MASK4|MASK3;
+ sc_access[4].value = 0xc8;
+ num_val = 5;
break;
case DMIC:
pr_debug("DMIC\n");
- sc_access[0].reg_addr = 0x107;
- sc_access[0].mask = MASK6|MASK4|MASK3|MASK1|MASK0;
+ sc_access[0].reg_addr = MICCTRL;
+ sc_access[0].mask = MASK6|MASK3|MASK1|MASK0;
sc_access[0].value = 0x0B;
sc_access[1].reg_addr = 0x105;
sc_access[1].value = 0x80;
@@ -872,12 +933,12 @@
sc_access[2].reg_addr = 0x10a;
sc_access[2].value = 0x40;
sc_access[2].mask = MASK6;
- sc_access[3].reg_addr = 0x109;
+ sc_access[3].reg_addr = LILSEL;
sc_access[3].mask = MASK6;
sc_access[3].value = 0x00;
- sc_access[4].reg_addr = 0x104;
- sc_access[4].value = 0x3C;
- sc_access[4].mask = 0xff;
+ sc_access[4].reg_addr = ADCSAMPLERATE;
+ sc_access[4].mask = MASK7|MASK6|MASK5|MASK4|MASK3;
+ sc_access[4].value = 0x33;
num_val = 5;
break;
default:
@@ -964,18 +1025,30 @@
mask = (MASK0|MASK1|MASK2|MASK3|MASK4|MASK5);
break;
- case PMIC_SND_RIGHT_PB_VOL:
- pr_debug("GET_VOLUME_PMIC_LEFT_HP_VOL\n");
+ case PMIC_SND_LEFT_MASTER_VOL:
+ pr_debug("GET_VOLUME_PMIC_LEFT_MASTER_VOL\n");
sc_access.reg_addr = AUDIOLVOL;
mask = (MASK0|MASK1|MASK2|MASK3|MASK4|MASK5|MASK6);
break;
- case PMIC_SND_LEFT_PB_VOL:
- pr_debug("GET_VOLUME_PMIC_RIGHT_HP_VOL\n");
+ case PMIC_SND_RIGHT_MASTER_VOL:
+ pr_debug("GET_VOLUME_PMIC_RIGHT_MASTER_VOL\n");
sc_access.reg_addr = AUDIORVOL;
mask = (MASK0|MASK1|MASK2|MASK3|MASK4|MASK5|MASK6);
break;
+ case PMIC_SND_RIGHT_PB_VOL:
+ pr_debug("GET_VOLUME_PMIC_RIGHT_HP_VOL\n");
+ sc_access.reg_addr = HPRVOL;
+ mask = (MASK0|MASK1|MASK2|MASK3|MASK4);
+ break;
+
+ case PMIC_SND_LEFT_PB_VOL:
+ pr_debug("GET_VOLUME_PMIC_LEFT_HP_VOL\n");
+ sc_access.reg_addr = HPLVOL;
+ mask = (MASK0|MASK1|MASK2|MASK3|MASK4);
+ break;
+
default:
return -EINVAL;
@@ -987,7 +1060,81 @@
return retval;
}
+static void hp_automute(enum snd_jack_types type, int present)
+{
+ u8 in = DMIC;
+ u8 out = INTERNAL_SPKR;
+ if (present) {
+ if (type == SND_JACK_HEADSET)
+ in = HS_MIC;
+ out = STEREO_HEADPHONE;
+ }
+ nc_set_selected_input_dev(in);
+ nc_set_selected_output_dev(out);
+}
+
+static void nc_pmic_irq_cb(void *cb_data, u8 intsts)
+{
+ u8 value = 0;
+ struct mad_jack *mjack = NULL;
+ unsigned int present = 0, jack_event_flag = 0, buttonpressflag = 0;
+ struct snd_intelmad *intelmaddata = cb_data;
+ struct sc_reg_access sc_access_read = {0,};
+
+ sc_access_read.reg_addr = 0x132;
+ sst_sc_reg_access(&sc_access_read, PMIC_READ, 1);
+ value = (sc_access_read.value);
+ pr_debug("value returned = 0x%x\n", value);
+
+ mjack = &intelmaddata->jack[0];
+ if (intsts & 0x1) {
+ pr_debug("SST DBG:MAD headset detected\n");
+ /* send headset detect/undetect */
+ present = (value == 0x1) ? 1 : 0;
+ jack_event_flag = 1;
+ mjack->jack.type = SND_JACK_HEADSET;
+ hp_automute(SND_JACK_HEADSET, present);
+ }
+
+ if (intsts & 0x2) {
+ pr_debug(":MAD headphone detected\n");
+ /* send headphone detect/undetect */
+ present = (value == 0x2) ? 1 : 0;
+ jack_event_flag = 1;
+ mjack->jack.type = SND_JACK_HEADPHONE;
+ hp_automute(SND_JACK_HEADPHONE, present);
+ }
+
+ if (intsts & 0x4) {
+ pr_debug("MAD short push detected\n");
+ /* send short push */
+ present = 1;
+ jack_event_flag = 1;
+ buttonpressflag = 1;
+ mjack->jack.type = MID_JACK_HS_SHORT_PRESS;
+ }
+
+ if (intsts & 0x8) {
+ pr_debug(":MAD long push detected\n");
+ /* send long push */
+ present = 1;
+ jack_event_flag = 1;
+ buttonpressflag = 1;
+ mjack->jack.type = MID_JACK_HS_LONG_PRESS;
+ }
+
+ if (jack_event_flag)
+ sst_mad_send_jack_report(&mjack->jack,
+ buttonpressflag, present);
+}
+static int nc_jack_enable(void)
+{
+ return 0;
+}
+
struct snd_pmic_ops snd_pmic_ops_nc = {
+ .input_dev_id = DMIC,
+ .output_dev_id = INTERNAL_SPKR,
.set_input_dev = nc_set_selected_input_dev,
.set_output_dev = nc_set_selected_output_dev,
.set_mute = nc_set_mute,
@@ -1003,5 +1150,7 @@
.power_up_pmic_cp = nc_power_up_cp,
.power_down_pmic_pb = nc_power_down_pb,
.power_down_pmic_cp = nc_power_down_cp,
- .power_down_pmic = nc_power_down,
+ .power_down_pmic = nc_power_down,
+ .pmic_irq_cb = nc_pmic_irq_cb,
+ .pmic_jack_enable = nc_jack_enable,
};
diff --git a/drivers/staging/intel_sst/jack.h b/drivers/staging/intel_sst/jack.h
deleted file mode 100644
index 9a6e483..0000000
--- a/drivers/staging/intel_sst/jack.h
+++ /dev/null
@@ -1,10 +0,0 @@
-/* Temporary staging glue */
-
-#include <sound/jack.h>
-
-/* These want adding to jack.h as enum entries once approved */
-
-#define SND_JACK_HS_SHORT_PRESS (SND_JACK_HEADSET | 0x0020)
-#define SND_JACK_HS_LONG_PRESS (SND_JACK_HEADSET | 0x0040)
-
-
diff --git a/drivers/staging/keucr/common.h b/drivers/staging/keucr/common.h
index b87dc7a..cf347cc 100644
--- a/drivers/staging/keucr/common.h
+++ b/drivers/staging/keucr/common.h
@@ -9,5 +9,7 @@
typedef u32 DWORD;
typedef u32 *PDWORD;
+#define BYTE_MASK 0xff
+
#endif
diff --git a/drivers/staging/keucr/init.c b/drivers/staging/keucr/init.c
index 8af7c84..b5a8937 100644
--- a/drivers/staging/keucr/init.c
+++ b/drivers/staging/keucr/init.c
@@ -11,9 +11,6 @@
#include "transport.h"
#include "init.h"
-BYTE IsSSFDCCompliance;
-BYTE IsXDCompliance;
-
/*
* ENE_InitMedia():
*/
diff --git a/drivers/staging/keucr/init.h b/drivers/staging/keucr/init.h
index 953a31e..f709055 100644
--- a/drivers/staging/keucr/init.h
+++ b/drivers/staging/keucr/init.h
@@ -4,7 +4,7 @@
extern int Check_D_MediaFmt(struct us_data *);
-BYTE MS_Init[] = {
+static BYTE MS_Init[] = {
0x90, 0xF0, 0x15, 0xE0, 0xF5, 0x1C, 0x11, 0x2C,
0x90, 0xFF, 0x09, 0xE0, 0x30, 0xE1, 0x06, 0x90,
0xFF, 0x23, 0x74, 0x80, 0xF0, 0x90, 0xFF, 0x09,
@@ -262,7 +262,7 @@
0x4D, 0x53, 0x2D, 0x49, 0x6E, 0x69, 0x74, 0x20,
0x20, 0x20, 0x20, 0x31, 0x30, 0x30, 0x30, 0x30 };
-BYTE MSP_Rdwr[] = {
+static BYTE MSP_Rdwr[] = {
0x90, 0xF0, 0x10, 0xE0, 0x90, 0xEA, 0x46, 0xF0,
0xB4, 0x04, 0x03, 0x02, 0xE1, 0x1E, 0x90, 0xFF,
0x09, 0xE0, 0x30, 0xE1, 0x06, 0x90, 0xFF, 0x23,
@@ -520,7 +520,7 @@
0x4D, 0x53, 0x50, 0x2D, 0x52, 0x57, 0x20, 0x20,
0x20, 0x20, 0x20, 0x31, 0x30, 0x30, 0x30, 0x30 };
-BYTE MS_Rdwr[] = {
+static BYTE MS_Rdwr[] = {
0x90, 0xF0, 0x10, 0xE0, 0x90, 0xEA, 0x46, 0xF0,
0xB4, 0x02, 0x02, 0x80, 0x36, 0x90, 0xF0, 0x11,
0xE0, 0xF5, 0x17, 0x90, 0xF0, 0x12, 0xE0, 0xF5,
@@ -778,7 +778,7 @@
0x4D, 0x53, 0x2D, 0x52, 0x57, 0x20, 0x20, 0x20,
0x20, 0x20, 0x20, 0x31, 0x30, 0x30, 0x30, 0x30 };
-BYTE SM_Init[] = {
+static BYTE SM_Init[] = {
0x7B, 0x09, 0x7C, 0xF0, 0x7D, 0x10, 0x7E, 0xE9,
0x7F, 0xCC, 0x12, 0x2F, 0x71, 0x90, 0xE9, 0xCC,
0xE0, 0xB4, 0x07, 0x12, 0x90, 0xFF, 0x09, 0xE0,
@@ -1036,7 +1036,7 @@
0x58, 0x44, 0x2D, 0x49, 0x6E, 0x69, 0x74, 0x20,
0x20, 0x20, 0x20, 0x31, 0x30, 0x30, 0x30, 0x31 };
-BYTE SM_Rdwr[] = {
+static BYTE SM_Rdwr[] = {
0x7B, 0x0C, 0x7C, 0xF0, 0x7D, 0x10, 0x7E, 0xE9,
0x7F, 0xCC, 0x12, 0x2F, 0x71, 0x90, 0xE9, 0xC3,
0xE0, 0xB4, 0x73, 0x04, 0x74, 0x40, 0x80, 0x09,
diff --git a/drivers/staging/keucr/ms.c b/drivers/staging/keucr/ms.c
index a713721..087ad73 100644
--- a/drivers/staging/keucr/ms.c
+++ b/drivers/staging/keucr/ms.c
@@ -6,13 +6,17 @@
#include "transport.h"
#include "ms.h"
-//----- MS_ReaderCopyBlock() ------------------------------------------
-int MS_ReaderCopyBlock(struct us_data *us, WORD oldphy, WORD newphy, WORD PhyBlockAddr, BYTE PageNum, PBYTE buf, WORD len)
+/*
+ * MS_ReaderCopyBlock()
+ */
+int MS_ReaderCopyBlock(struct us_data *us, WORD oldphy, WORD newphy,
+ WORD PhyBlockAddr, BYTE PageNum, PBYTE buf, WORD len)
{
struct bulk_cb_wrap *bcb = (struct bulk_cb_wrap *) us->iobuf;
int result;
- //printk("MS_ReaderCopyBlock --- PhyBlockAddr = %x, PageNum = %x\n", PhyBlockAddr, PageNum);
+ /* printk(KERN_INFO "MS_ReaderCopyBlock --- PhyBlockAddr = %x,
+ PageNum = %x\n", PhyBlockAddr, PageNum); */
result = ENE_LoadBinCode(us, MS_RW_PATTERN);
if (result != USB_STOR_XFER_GOOD)
return USB_STOR_TRANSPORT_ERROR;
@@ -25,10 +29,10 @@
bcb->CDB[1] = 0x08;
bcb->CDB[4] = (BYTE)(oldphy);
bcb->CDB[3] = (BYTE)(oldphy>>8);
- bcb->CDB[2] = (BYTE)(oldphy>>16);
+ bcb->CDB[2] = 0; /* (BYTE)(oldphy>>16) */
bcb->CDB[7] = (BYTE)(newphy);
bcb->CDB[6] = (BYTE)(newphy>>8);
- bcb->CDB[5] = (BYTE)(newphy>>16);
+ bcb->CDB[5] = 0; /* (BYTE)(newphy>>16) */
bcb->CDB[9] = (BYTE)(PhyBlockAddr);
bcb->CDB[8] = (BYTE)(PhyBlockAddr>>8);
bcb->CDB[10] = PageNum;
@@ -40,21 +44,25 @@
return USB_STOR_TRANSPORT_GOOD;
}
-//----- MS_ReaderReadPage() ------------------------------------------
-int MS_ReaderReadPage(struct us_data *us, DWORD PhyBlockAddr, BYTE PageNum, PDWORD PageBuf, MS_LibTypeExtdat *ExtraDat)
+/*
+ * MS_ReaderReadPage()
+ */
+int MS_ReaderReadPage(struct us_data *us, DWORD PhyBlockAddr,
+ BYTE PageNum, PDWORD PageBuf, MS_LibTypeExtdat *ExtraDat)
{
struct bulk_cb_wrap *bcb = (struct bulk_cb_wrap *) us->iobuf;
int result;
BYTE ExtBuf[4];
DWORD bn = PhyBlockAddr * 0x20 + PageNum;
- //printk("MS --- MS_ReaderReadPage, PhyBlockAddr = %x, PageNum = %x\n", PhyBlockAddr, PageNum);
+ /* printk(KERN_INFO "MS --- MS_ReaderReadPage,
+ PhyBlockAddr = %x, PageNum = %x\n", PhyBlockAddr, PageNum); */
result = ENE_LoadBinCode(us, MS_RW_PATTERN);
if (result != USB_STOR_XFER_GOOD)
return USB_STOR_TRANSPORT_ERROR;
- // Read Page Data
+ /* Read Page Data */
memset(bcb, 0, sizeof(struct bulk_cb_wrap));
bcb->Signature = cpu_to_le32(US_BULK_CB_SIGN);
bcb->DataTransferLength = 0x200;
@@ -65,12 +73,12 @@
bcb->CDB[4] = (BYTE)(bn>>8);
bcb->CDB[3] = (BYTE)(bn>>16);
bcb->CDB[2] = (BYTE)(bn>>24);
-
+
result = ENE_SendScsiCmd(us, FDIR_READ, PageBuf, 0);
if (result != USB_STOR_XFER_GOOD)
return USB_STOR_TRANSPORT_ERROR;
- // Read Extra Data
+ /* Read Extra Data */
memset(bcb, 0, sizeof(struct bulk_cb_wrap));
bcb->Signature = cpu_to_le32(US_BULK_CB_SIGN);
bcb->DataTransferLength = 0x4;
@@ -88,9 +96,9 @@
return USB_STOR_TRANSPORT_ERROR;
ExtraDat->reserved = 0;
- ExtraDat->intr = 0x80; // Not yet, ¥ý°²³], µ¥ fireware support
- ExtraDat->status0 = 0x10; // Not yet, ¥ý°²³], µ¥ fireware support
- ExtraDat->status1 = 0x00; // Not yet, ¥ý°²³], µ¥ fireware support
+ ExtraDat->intr = 0x80; /* Not yet,fireware support */
+ ExtraDat->status0 = 0x10; /* Not yet,fireware support */
+ ExtraDat->status1 = 0x00; /* Not yet,fireware support */
ExtraDat->ovrflg = ExtBuf[0];
ExtraDat->mngflg = ExtBuf[1];
ExtraDat->logadr = MemStickLogAddr(ExtBuf[2], ExtBuf[3]);
@@ -98,14 +106,17 @@
return USB_STOR_TRANSPORT_GOOD;
}
-//----- MS_ReaderEraseBlock() ----------------------------------------
+/*
+ * MS_ReaderEraseBlock()
+ */
int MS_ReaderEraseBlock(struct us_data *us, DWORD PhyBlockAddr)
{
struct bulk_cb_wrap *bcb = (struct bulk_cb_wrap *) us->iobuf;
int result;
DWORD bn = PhyBlockAddr;
- //printk("MS --- MS_ReaderEraseBlock, PhyBlockAddr = %x\n", PhyBlockAddr);
+ /* printk(KERN_INFO "MS --- MS_ReaderEraseBlock,
+ PhyBlockAddr = %x\n", PhyBlockAddr); */
result = ENE_LoadBinCode(us, MS_RW_PATTERN);
if (result != USB_STOR_XFER_GOOD)
return USB_STOR_TRANSPORT_ERROR;
@@ -119,7 +130,7 @@
bcb->CDB[4] = (BYTE)(bn);
bcb->CDB[3] = (BYTE)(bn>>8);
bcb->CDB[2] = (BYTE)(bn>>16);
-
+
result = ENE_SendScsiCmd(us, FDIR_READ, NULL, 0);
if (result != USB_STOR_XFER_GOOD)
return USB_STOR_TRANSPORT_ERROR;
@@ -127,23 +138,25 @@
return USB_STOR_TRANSPORT_GOOD;
}
-//----- MS_CardInit() ------------------------------------------------
+/*
+ * MS_CardInit()
+ */
int MS_CardInit(struct us_data *us)
{
- DWORD result=0;
+ DWORD result = 0;
WORD TmpBlock;
PBYTE PageBuffer0 = NULL, PageBuffer1 = NULL;
MS_LibTypeExtdat extdat;
WORD btBlk1st, btBlk2nd;
DWORD btBlk1stErred;
- printk("MS_CardInit start\n");
+ printk(KERN_INFO "MS_CardInit start\n");
MS_LibFreeAllocatedArea(us);
- if (((PageBuffer0 = kmalloc(MS_BYTES_PER_PAGE, GFP_KERNEL)) == NULL) ||
- ((PageBuffer1 = kmalloc(MS_BYTES_PER_PAGE, GFP_KERNEL)) == NULL))
- {
+ PageBuffer0 = kmalloc(MS_BYTES_PER_PAGE, GFP_KERNEL);
+ PageBuffer1 = kmalloc(MS_BYTES_PER_PAGE, GFP_KERNEL);
+ if ((PageBuffer0 == NULL) || (PageBuffer1 == NULL)) {
result = MS_NO_MEMORY_ERROR;
goto exit;
}
@@ -151,16 +164,16 @@
btBlk1st = btBlk2nd = MS_LB_NOT_USED;
btBlk1stErred = 0;
- for (TmpBlock=0; TmpBlock < MS_MAX_INITIAL_ERROR_BLOCKS+2; TmpBlock++)
- {
- switch (MS_ReaderReadPage(us, TmpBlock, 0, (DWORD *)PageBuffer0, &extdat))
- {
- case MS_STATUS_SUCCESS:
+ for (TmpBlock = 0; TmpBlock < MS_MAX_INITIAL_ERROR_BLOCKS+2;
+ TmpBlock++) {
+ switch (MS_ReaderReadPage(us, TmpBlock, 0,
+ (DWORD *)PageBuffer0, &extdat)) {
+ case MS_STATUS_SUCCESS:
break;
- case MS_STATUS_INT_ERROR:
+ case MS_STATUS_INT_ERROR:
break;
- case MS_STATUS_ERROR:
- default:
+ case MS_STATUS_ERROR:
+ default:
continue;
}
@@ -173,38 +186,37 @@
(((MemStickBootBlockPage0 *)PageBuffer0)->header.bNumberOfDataEntry != MS_BOOT_BLOCK_DATA_ENTRIES))
continue;
- if (btBlk1st != MS_LB_NOT_USED)
- {
+ if (btBlk1st != MS_LB_NOT_USED) {
btBlk2nd = TmpBlock;
break;
}
btBlk1st = TmpBlock;
memcpy(PageBuffer1, PageBuffer0, MS_BYTES_PER_PAGE);
- if (extdat.status1 & (MS_REG_ST1_DTER | MS_REG_ST1_EXER | MS_REG_ST1_FGER))
+ if (extdat.status1 &
+ (MS_REG_ST1_DTER | MS_REG_ST1_EXER | MS_REG_ST1_FGER))
btBlk1stErred = 1;
}
- if (btBlk1st == MS_LB_NOT_USED)
- {
+ if (btBlk1st == MS_LB_NOT_USED) {
result = MS_STATUS_ERROR;
goto exit;
}
- // write protect
+ /* write protect */
if ((extdat.status0 & MS_REG_ST0_WP) == MS_REG_ST0_WP_ON)
MS_LibCtrlSet(us, MS_LIB_CTRL_WRPROTECT);
result = MS_STATUS_ERROR;
- // 1st Boot Block
+ /* 1st Boot Block */
if (btBlk1stErred == 0)
- result = MS_LibProcessBootBlock(us, btBlk1st, PageBuffer1); // 1st
- // 2nd Boot Block
+ result = MS_LibProcessBootBlock(us, btBlk1st, PageBuffer1);
+ /* 1st */
+ /* 2nd Boot Block */
if (result && (btBlk2nd != MS_LB_NOT_USED))
result = MS_LibProcessBootBlock(us, btBlk2nd, PageBuffer0);
- if (result)
- {
+ if (result) {
result = MS_STATUS_ERROR;
goto exit;
}
@@ -214,8 +226,7 @@
us->MS_Lib.Phy2LogMap[btBlk1st] = MS_LB_BOOT_BLOCK;
- if (btBlk2nd != MS_LB_NOT_USED)
- {
+ if (btBlk2nd != MS_LB_NOT_USED) {
for (TmpBlock = btBlk1st + 1; TmpBlock < btBlk2nd; TmpBlock++)
us->MS_Lib.Phy2LogMap[TmpBlock] = MS_LB_INITIAL_ERROR;
us->MS_Lib.Phy2LogMap[btBlk2nd] = MS_LB_BOOT_BLOCK;
@@ -225,18 +236,17 @@
if (result)
goto exit;
- for (TmpBlock=MS_PHYSICAL_BLOCKS_PER_SEGMENT; TmpBlock<us->MS_Lib.NumberOfPhyBlock; TmpBlock+=MS_PHYSICAL_BLOCKS_PER_SEGMENT)
- {
- if (MS_CountFreeBlock(us, TmpBlock) == 0)
- {
+ for (TmpBlock = MS_PHYSICAL_BLOCKS_PER_SEGMENT;
+ TmpBlock < us->MS_Lib.NumberOfPhyBlock;
+ TmpBlock += MS_PHYSICAL_BLOCKS_PER_SEGMENT) {
+ if (MS_CountFreeBlock(us, TmpBlock) == 0) {
MS_LibCtrlSet(us, MS_LIB_CTRL_WRPROTECT);
break;
}
}
- // write
- if (MS_LibAllocWriteBuf(us))
- {
+ /* write */
+ if (MS_LibAllocWriteBuf(us)) {
result = MS_NO_MEMORY_ERROR;
goto exit;
}
@@ -245,46 +255,48 @@
exit:
kfree(PageBuffer1);
- kfree(PageBuffer0);
+ kfree(PageBuffer0);
- printk("MS_CardInit end\n");
+ printk(KERN_INFO "MS_CardInit end\n");
return result;
}
-//----- MS_LibCheckDisableBlock() ------------------------------------
+/*
+ * MS_LibCheckDisableBlock()
+ */
int MS_LibCheckDisableBlock(struct us_data *us, WORD PhyBlock)
{
- PWORD PageBuf=NULL;
- DWORD result=MS_STATUS_SUCCESS;
- DWORD blk, index=0;
+ PWORD PageBuf = NULL;
+ DWORD result = MS_STATUS_SUCCESS;
+ DWORD blk, index = 0;
MS_LibTypeExtdat extdat;
- if (((PageBuf = kmalloc(MS_BYTES_PER_PAGE, GFP_KERNEL)) == NULL))
- {
+ PageBuf = kmalloc(MS_BYTES_PER_PAGE, GFP_KERNEL);
+ if (PageBuf == NULL) {
result = MS_NO_MEMORY_ERROR;
goto exit;
}
MS_ReaderReadPage(us, PhyBlock, 1, (DWORD *)PageBuf, &extdat);
- do
- {
+ do {
blk = be16_to_cpu(PageBuf[index]);
if (blk == MS_LB_NOT_USED)
break;
- if (blk == us->MS_Lib.Log2PhyMap[0])
- {
+ if (blk == us->MS_Lib.Log2PhyMap[0]) {
result = MS_ERROR_FLASH_READ;
break;
}
index++;
- } while(1);
+ } while (1);
exit:
kfree(PageBuf);
return result;
}
-//----- MS_LibFreeAllocatedArea() ------------------------------------
+/*
+ * MS_LibFreeAllocatedArea()
+ */
void MS_LibFreeAllocatedArea(struct us_data *us)
{
MS_LibFreeWriteBuf(us);
@@ -302,26 +314,31 @@
us->MS_Lib.NumberOfLogBlock = 0;
}
-//----- MS_LibFreeWriteBuf() -----------------------------------------
+/*
+ * MS_LibFreeWriteBuf()
+ */
void MS_LibFreeWriteBuf(struct us_data *us)
{
- us->MS_Lib.wrtblk = (WORD)-1; //set to -1
- MS_LibClearPageMap(us); // memset((fdoExt)->MS_Lib.pagemap, 0, sizeof((fdoExt)->MS_Lib.pagemap))
+ us->MS_Lib.wrtblk = (WORD)-1; /* set to -1 */
- if (us->MS_Lib.blkpag)
- {
- kfree((BYTE *)(us->MS_Lib.blkpag)); // Arnold test ...
+ /* memset((fdoExt)->MS_Lib.pagemap, 0,
+ sizeof((fdoExt)->MS_Lib.pagemap)) */
+ MS_LibClearPageMap(us);
+
+ if (us->MS_Lib.blkpag) {
+ kfree((BYTE *)(us->MS_Lib.blkpag)); /* Arnold test ... */
us->MS_Lib.blkpag = NULL;
}
- if (us->MS_Lib.blkext)
- {
- kfree((BYTE *)(us->MS_Lib.blkext)); // Arnold test ...
+ if (us->MS_Lib.blkext) {
+ kfree((BYTE *)(us->MS_Lib.blkext)); /* Arnold test ... */
us->MS_Lib.blkext = NULL;
}
}
-//----- MS_LibFreeLogicalMap() ---------------------------------------
+/*
+ * MS_LibFreeLogicalMap()
+ */
int MS_LibFreeLogicalMap(struct us_data *us)
{
kfree(us->MS_Lib.Phy2LogMap);
@@ -330,10 +347,12 @@
kfree(us->MS_Lib.Log2PhyMap);
us->MS_Lib.Log2PhyMap = NULL;
- return 0;
+ return 0;
}
-//----- MS_LibProcessBootBlock() -------------------------------------
+/*
+ * MS_LibProcessBootBlock()
+ */
int MS_LibProcessBootBlock(struct us_data *us, WORD PhyBlock, BYTE *PageData)
{
MemStickBootBlockSysEnt *SysEntry;
@@ -343,144 +362,165 @@
BYTE *PageBuffer;
MS_LibTypeExtdat ExtraData;
- if ((PageBuffer = kmalloc(MS_BYTES_PER_PAGE, GFP_KERNEL))==NULL)
+
+ PageBuffer = kmalloc(MS_BYTES_PER_PAGE, GFP_KERNEL);
+ if (PageBuffer == NULL)
return (DWORD)-1;
result = (DWORD)-1;
- SysInfo= &(((MemStickBootBlockPage0 *)PageData)->sysinf);
+ SysInfo = &(((MemStickBootBlockPage0 *)PageData)->sysinf);
- if ((SysInfo->bMsClass != MS_SYSINF_MSCLASS_TYPE_1) ||
- (be16_to_cpu(SysInfo->wPageSize) != MS_SYSINF_PAGE_SIZE) ||
+ if ((SysInfo->bMsClass != MS_SYSINF_MSCLASS_TYPE_1) ||
+ (be16_to_cpu(SysInfo->wPageSize) != MS_SYSINF_PAGE_SIZE) ||
((SysInfo->bSecuritySupport & MS_SYSINF_SECURITY) == MS_SYSINF_SECURITY_SUPPORT) ||
- (SysInfo->bReserved1 != MS_SYSINF_RESERVED1) ||
- (SysInfo->bReserved2 != MS_SYSINF_RESERVED2) ||
- (SysInfo->bFormatType!= MS_SYSINF_FORMAT_FAT) ||
+ (SysInfo->bReserved1 != MS_SYSINF_RESERVED1) ||
+ (SysInfo->bReserved2 != MS_SYSINF_RESERVED2) ||
+ (SysInfo->bFormatType != MS_SYSINF_FORMAT_FAT) ||
(SysInfo->bUsage != MS_SYSINF_USAGE_GENERAL))
goto exit;
- switch (us->MS_Lib.cardType = SysInfo->bCardType)
- {
- case MS_SYSINF_CARDTYPE_RDONLY:
- MS_LibCtrlSet(us, MS_LIB_CTRL_RDONLY);
- break;
- case MS_SYSINF_CARDTYPE_RDWR:
- MS_LibCtrlReset(us, MS_LIB_CTRL_RDONLY);
- break;
- case MS_SYSINF_CARDTYPE_HYBRID:
- default:
- goto exit;
+ switch (us->MS_Lib.cardType = SysInfo->bCardType) {
+ case MS_SYSINF_CARDTYPE_RDONLY:
+ MS_LibCtrlSet(us, MS_LIB_CTRL_RDONLY);
+ break;
+ case MS_SYSINF_CARDTYPE_RDWR:
+ MS_LibCtrlReset(us, MS_LIB_CTRL_RDONLY);
+ break;
+ case MS_SYSINF_CARDTYPE_HYBRID:
+ default:
+ goto exit;
}
us->MS_Lib.blockSize = be16_to_cpu(SysInfo->wBlockSize);
us->MS_Lib.NumberOfPhyBlock = be16_to_cpu(SysInfo->wBlockNumber);
- us->MS_Lib.NumberOfLogBlock = be16_to_cpu(SysInfo->wTotalBlockNumber) - 2;
- us->MS_Lib.PagesPerBlock = us->MS_Lib.blockSize * SIZE_OF_KIRO / MS_BYTES_PER_PAGE;
- us->MS_Lib.NumberOfSegment = us->MS_Lib.NumberOfPhyBlock / MS_PHYSICAL_BLOCKS_PER_SEGMENT;
+ us->MS_Lib.NumberOfLogBlock = be16_to_cpu(SysInfo->wTotalBlockNumber)
+ -2;
+ us->MS_Lib.PagesPerBlock = us->MS_Lib.blockSize * SIZE_OF_KIRO /
+ MS_BYTES_PER_PAGE;
+ us->MS_Lib.NumberOfSegment = us->MS_Lib.NumberOfPhyBlock /
+ MS_PHYSICAL_BLOCKS_PER_SEGMENT;
us->MS_Model = be16_to_cpu(SysInfo->wMemorySize);
- if (MS_LibAllocLogicalMap(us)) //Allocate to all number of logicalblock and physicalblock
+ /*Allocate to all number of logicalblock and physicalblock */
+ if (MS_LibAllocLogicalMap(us))
goto exit;
- MS_LibSetBootBlockMark(us, PhyBlock); //Mark the book block
+ /* Mark the book block */
+ MS_LibSetBootBlockMark(us, PhyBlock);
SysEntry = &(((MemStickBootBlockPage0 *)PageData)->sysent);
- for (i=0; i<MS_NUMBER_OF_SYSTEM_ENTRY; i++)
- {
+ for (i = 0; i < MS_NUMBER_OF_SYSTEM_ENTRY; i++) {
DWORD EntryOffset, EntrySize;
- if ((EntryOffset = be32_to_cpu(SysEntry->entry[i].dwStart)) == 0xffffff)
+ EntryOffset = be32_to_cpu(SysEntry->entry[i].dwStart);
+
+ if (EntryOffset == 0xffffff)
+ continue;
+ EntrySize = be32_to_cpu(SysEntry->entry[i].dwSize);
+
+ if (EntrySize == 0)
continue;
- if ((EntrySize = be32_to_cpu(SysEntry->entry[i].dwSize)) == 0)
+ if (EntryOffset + MS_BYTES_PER_PAGE + EntrySize >
+ us->MS_Lib.blockSize * (DWORD)SIZE_OF_KIRO)
continue;
- if (EntryOffset + MS_BYTES_PER_PAGE + EntrySize > us->MS_Lib.blockSize * (DWORD)SIZE_OF_KIRO)
- continue;
-
- if (i == 0)
- {
+ if (i == 0) {
BYTE PrevPageNumber = 0;
WORD phyblk;
- if (SysEntry->entry[i].bType != MS_SYSENT_TYPE_INVALID_BLOCK)
+ if (SysEntry->entry[i].bType !=
+ MS_SYSENT_TYPE_INVALID_BLOCK)
goto exit;
- while (EntrySize > 0)
- {
- if ((PageNumber = (BYTE)(EntryOffset / MS_BYTES_PER_PAGE + 1)) != PrevPageNumber)
- {
- switch (MS_ReaderReadPage(us, PhyBlock, PageNumber, (DWORD *)PageBuffer, &ExtraData))
- {
- case MS_STATUS_SUCCESS:
- break;
- case MS_STATUS_WRITE_PROTECT:
- case MS_ERROR_FLASH_READ:
- case MS_STATUS_ERROR:
- default:
- goto exit;
+ while (EntrySize > 0) {
+
+ PageNumber = (BYTE)(EntryOffset /
+ MS_BYTES_PER_PAGE + 1);
+ if (PageNumber != PrevPageNumber) {
+ switch (MS_ReaderReadPage(us, PhyBlock,
+ PageNumber, (DWORD *)PageBuffer,
+ &ExtraData)) {
+ case MS_STATUS_SUCCESS:
+ break;
+ case MS_STATUS_WRITE_PROTECT:
+ case MS_ERROR_FLASH_READ:
+ case MS_STATUS_ERROR:
+ default:
+ goto exit;
}
PrevPageNumber = PageNumber;
}
- if ((phyblk = be16_to_cpu(*(WORD *)(PageBuffer + (EntryOffset % MS_BYTES_PER_PAGE)))) < 0x0fff)
+ phyblk = be16_to_cpu(*(WORD *)(PageBuffer +
+ (EntryOffset % MS_BYTES_PER_PAGE)));
+ if (phyblk < 0x0fff)
MS_LibSetInitialErrorBlock(us, phyblk);
EntryOffset += 2;
EntrySize -= 2;
}
- }
- else if (i == 1)
- { // CIS/IDI
+ } else if (i == 1) { /* CIS/IDI */
MemStickBootBlockIDI *idi;
if (SysEntry->entry[i].bType != MS_SYSENT_TYPE_CIS_IDI)
goto exit;
- switch (MS_ReaderReadPage(us, PhyBlock, (BYTE)(EntryOffset / MS_BYTES_PER_PAGE + 1), (DWORD *)PageBuffer, &ExtraData))
- {
- case MS_STATUS_SUCCESS:
- break;
- case MS_STATUS_WRITE_PROTECT:
- case MS_ERROR_FLASH_READ:
- case MS_STATUS_ERROR:
- default:
- goto exit;
+ switch (MS_ReaderReadPage(us, PhyBlock,
+ (BYTE)(EntryOffset / MS_BYTES_PER_PAGE + 1),
+ (DWORD *)PageBuffer, &ExtraData)) {
+ case MS_STATUS_SUCCESS:
+ break;
+ case MS_STATUS_WRITE_PROTECT:
+ case MS_ERROR_FLASH_READ:
+ case MS_STATUS_ERROR:
+ default:
+ goto exit;
}
- idi = &((MemStickBootBlockCIS_IDI *)(PageBuffer + (EntryOffset % MS_BYTES_PER_PAGE)))->idi.idi;
- if (le16_to_cpu(idi->wIDIgeneralConfiguration) != MS_IDI_GENERAL_CONF)
+ idi = &((MemStickBootBlockCIS_IDI *)(PageBuffer +
+ (EntryOffset % MS_BYTES_PER_PAGE)))->idi.idi;
+ if (le16_to_cpu(idi->wIDIgeneralConfiguration) !=
+ MS_IDI_GENERAL_CONF)
goto exit;
- us->MS_Lib.BytesPerSector = le16_to_cpu(idi->wIDIbytesPerSector);
+ us->MS_Lib.BytesPerSector =
+ le16_to_cpu(idi->wIDIbytesPerSector);
if (us->MS_Lib.BytesPerSector != MS_BYTES_PER_PAGE)
goto exit;
}
- } // End for ..
+ } /* End for .. */
result = 0;
exit:
- if (result) MS_LibFreeLogicalMap(us);
+ if (result)
+ MS_LibFreeLogicalMap(us);
+
kfree(PageBuffer);
result = 0;
return result;
}
-//----- MS_LibAllocLogicalMap() --------------------------------------
+/*
+ * MS_LibAllocLogicalMap()
+ */
int MS_LibAllocLogicalMap(struct us_data *us)
{
DWORD i;
- us->MS_Lib.Phy2LogMap = kmalloc(us->MS_Lib.NumberOfPhyBlock * sizeof(WORD), GFP_KERNEL);
- us->MS_Lib.Log2PhyMap = kmalloc(us->MS_Lib.NumberOfLogBlock * sizeof(WORD), GFP_KERNEL);
+ us->MS_Lib.Phy2LogMap = kmalloc(us->MS_Lib.NumberOfPhyBlock *
+ sizeof(WORD), GFP_KERNEL);
+ us->MS_Lib.Log2PhyMap = kmalloc(us->MS_Lib.NumberOfLogBlock *
+ sizeof(WORD), GFP_KERNEL);
- if ((us->MS_Lib.Phy2LogMap == NULL) || (us->MS_Lib.Log2PhyMap == NULL))
- {
+ if ((us->MS_Lib.Phy2LogMap == NULL) ||
+ (us->MS_Lib.Log2PhyMap == NULL)) {
MS_LibFreeLogicalMap(us);
return (DWORD)-1;
}
@@ -489,128 +529,142 @@
us->MS_Lib.Phy2LogMap[i] = MS_LB_NOT_USED;
for (i = 0; i < us->MS_Lib.NumberOfLogBlock; i++)
- us->MS_Lib.Log2PhyMap[i] = MS_LB_NOT_USED;
+ us->MS_Lib.Log2PhyMap[i] = MS_LB_NOT_USED;
return 0;
}
-//----- MS_LibSetBootBlockMark() -------------------------------------
+/*
+ * MS_LibSetBootBlockMark()
+ */
int MS_LibSetBootBlockMark(struct us_data *us, WORD phyblk)
{
- return MS_LibSetLogicalBlockMark(us, phyblk, MS_LB_BOOT_BLOCK);
+ return MS_LibSetLogicalBlockMark(us, phyblk, MS_LB_BOOT_BLOCK);
}
-//----- MS_LibSetLogicalBlockMark() ----------------------------------
+/*
+ * MS_LibSetLogicalBlockMark()
+ */
int MS_LibSetLogicalBlockMark(struct us_data *us, WORD phyblk, WORD mark)
{
- if (phyblk >= us->MS_Lib.NumberOfPhyBlock)
- return (DWORD)-1;
+ if (phyblk >= us->MS_Lib.NumberOfPhyBlock)
+ return (DWORD)-1;
- us->MS_Lib.Phy2LogMap[phyblk] = mark;
+ us->MS_Lib.Phy2LogMap[phyblk] = mark;
- return 0;
+ return 0;
}
-//----- MS_LibSetInitialErrorBlock() ---------------------------------
+/*
+ * MS_LibSetInitialErrorBlock()
+ */
int MS_LibSetInitialErrorBlock(struct us_data *us, WORD phyblk)
{
- return MS_LibSetLogicalBlockMark(us, phyblk, MS_LB_INITIAL_ERROR);
+ return MS_LibSetLogicalBlockMark(us, phyblk, MS_LB_INITIAL_ERROR);
}
-//----- MS_LibScanLogicalBlockNumber() -------------------------------
+/*
+ * MS_LibScanLogicalBlockNumber()
+ */
int MS_LibScanLogicalBlockNumber(struct us_data *us, WORD btBlk1st)
{
WORD PhyBlock, newblk, i;
WORD LogStart, LogEnde;
MS_LibTypeExtdat extdat;
BYTE buf[0x200];
- DWORD count=0, index=0;
+ DWORD count = 0, index = 0;
- for (PhyBlock = 0; PhyBlock < us->MS_Lib.NumberOfPhyBlock;)
- {
+ for (PhyBlock = 0; PhyBlock < us->MS_Lib.NumberOfPhyBlock;) {
MS_LibPhy2LogRange(PhyBlock, &LogStart, &LogEnde);
- for (i=0; i<MS_PHYSICAL_BLOCKS_PER_SEGMENT; i++, PhyBlock++)
- {
- switch (MS_LibConv2Logical(us, PhyBlock))
- {
- case MS_STATUS_ERROR:
- continue;
- default:
- break;
+ for (i = 0; i < MS_PHYSICAL_BLOCKS_PER_SEGMENT;
+ i++, PhyBlock++) {
+ switch (MS_LibConv2Logical(us, PhyBlock)) {
+ case MS_STATUS_ERROR:
+ continue;
+ default:
+ break;
}
- if (count == PhyBlock)
- {
- MS_LibReadExtraBlock(us, PhyBlock, 0, 0x80, &buf);
+ if (count == PhyBlock) {
+ MS_LibReadExtraBlock(us, PhyBlock,
+ 0, 0x80, &buf);
count += 0x80;
}
index = (PhyBlock % 0x80) * 4;
extdat.ovrflg = buf[index];
extdat.mngflg = buf[index+1];
- extdat.logadr = MemStickLogAddr(buf[index+2], buf[index+3]);
+ extdat.logadr = MemStickLogAddr(buf[index+2],
+ buf[index+3]);
- if ((extdat.ovrflg & MS_REG_OVR_BKST) != MS_REG_OVR_BKST_OK)
- {
+ if ((extdat.ovrflg & MS_REG_OVR_BKST) !=
+ MS_REG_OVR_BKST_OK) {
MS_LibSetAcquiredErrorBlock(us, PhyBlock);
continue;
}
- if ((extdat.mngflg & MS_REG_MNG_ATFLG) == MS_REG_MNG_ATFLG_ATTBL)
- {
+ if ((extdat.mngflg & MS_REG_MNG_ATFLG) ==
+ MS_REG_MNG_ATFLG_ATTBL) {
MS_LibErasePhyBlock(us, PhyBlock);
continue;
}
- if (extdat.logadr != MS_LB_NOT_USED)
- {
- if ((extdat.logadr < LogStart) || (LogEnde <= extdat.logadr))
- {
+ if (extdat.logadr != MS_LB_NOT_USED) {
+ if ((extdat.logadr < LogStart) ||
+ (LogEnde <= extdat.logadr)) {
MS_LibErasePhyBlock(us, PhyBlock);
continue;
}
- if ((newblk = MS_LibConv2Physical(us, extdat.logadr)) != MS_LB_NOT_USED)
- {
- if (extdat.logadr==0)
- {
- MS_LibSetLogicalPair(us, extdat.logadr, PhyBlock);
- if ( MS_LibCheckDisableBlock(us, btBlk1st) )
- {
- MS_LibSetLogicalPair(us, extdat.logadr, newblk);
+ newblk = MS_LibConv2Physical(us, extdat.logadr);
+
+ if (newblk != MS_LB_NOT_USED) {
+ if (extdat.logadr == 0) {
+ MS_LibSetLogicalPair(us,
+ extdat.logadr,
+ PhyBlock);
+ if (MS_LibCheckDisableBlock(us,
+ btBlk1st)) {
+ MS_LibSetLogicalPair(us,
+ extdat.logadr, newblk);
continue;
}
}
MS_LibReadExtra(us, newblk, 0, &extdat);
- if ((extdat.ovrflg & MS_REG_OVR_UDST) == MS_REG_OVR_UDST_UPDATING)
- {
- MS_LibErasePhyBlock(us, PhyBlock);
+ if ((extdat.ovrflg & MS_REG_OVR_UDST) ==
+ MS_REG_OVR_UDST_UPDATING) {
+ MS_LibErasePhyBlock(us,
+ PhyBlock);
continue;
- }
- else
+ } else {
MS_LibErasePhyBlock(us, newblk);
+ }
}
- MS_LibSetLogicalPair(us, extdat.logadr, PhyBlock);
+ MS_LibSetLogicalPair(us, extdat.logadr,
+ PhyBlock);
}
}
- } //End for ...
+ } /* End for ... */
return MS_STATUS_SUCCESS;
}
-//----- MS_LibAllocWriteBuf() ----------------------------------------
+/*
+ * MS_LibAllocWriteBuf()
+ */
int MS_LibAllocWriteBuf(struct us_data *us)
{
us->MS_Lib.wrtblk = (WORD)-1;
- us->MS_Lib.blkpag = kmalloc(us->MS_Lib.PagesPerBlock * us->MS_Lib.BytesPerSector, GFP_KERNEL);
- us->MS_Lib.blkext = kmalloc(us->MS_Lib.PagesPerBlock * sizeof(MS_LibTypeExtdat), GFP_KERNEL);
+ us->MS_Lib.blkpag = kmalloc(us->MS_Lib.PagesPerBlock *
+ us->MS_Lib.BytesPerSector, GFP_KERNEL);
+ us->MS_Lib.blkext = kmalloc(us->MS_Lib.PagesPerBlock *
+ sizeof(MS_LibTypeExtdat), GFP_KERNEL);
- if ((us->MS_Lib.blkpag == NULL) || (us->MS_Lib.blkext == NULL))
- {
+ if ((us->MS_Lib.blkpag == NULL) || (us->MS_Lib.blkext == NULL)) {
MS_LibFreeWriteBuf(us);
return (DWORD)-1;
}
@@ -620,7 +674,9 @@
return 0;
}
-//----- MS_LibClearWriteBuf() ----------------------------------------
+/*
+ * MS_LibClearWriteBuf()
+ */
void MS_LibClearWriteBuf(struct us_data *us)
{
int i;
@@ -629,12 +685,11 @@
MS_LibClearPageMap(us);
if (us->MS_Lib.blkpag)
- memset(us->MS_Lib.blkpag, 0xff, us->MS_Lib.PagesPerBlock * us->MS_Lib.BytesPerSector);
+ memset(us->MS_Lib.blkpag, 0xff,
+ us->MS_Lib.PagesPerBlock * us->MS_Lib.BytesPerSector);
- if (us->MS_Lib.blkext)
- {
- for (i = 0; i < us->MS_Lib.PagesPerBlock; i++)
- {
+ if (us->MS_Lib.blkext) {
+ for (i = 0; i < us->MS_Lib.PagesPerBlock; i++) {
us->MS_Lib.blkext[i].status1 = MS_REG_ST1_DEFAULT;
us->MS_Lib.blkext[i].ovrflg = MS_REG_OVR_DEFAULT;
us->MS_Lib.blkext[i].mngflg = MS_REG_MNG_DEFAULT;
@@ -643,32 +698,36 @@
}
}
-//----- MS_LibPhy2LogRange() -----------------------------------------
+/*
+ * MS_LibPhy2LogRange()
+ */
void MS_LibPhy2LogRange(WORD PhyBlock, WORD *LogStart, WORD *LogEnde)
{
PhyBlock /= MS_PHYSICAL_BLOCKS_PER_SEGMENT;
- if (PhyBlock)
- {
- *LogStart = MS_LOGICAL_BLOCKS_IN_1ST_SEGMENT + (PhyBlock - 1) * MS_LOGICAL_BLOCKS_PER_SEGMENT;//496
- *LogEnde = *LogStart + MS_LOGICAL_BLOCKS_PER_SEGMENT;//496
- }
- else
- {
+ if (PhyBlock) {
+ *LogStart = MS_LOGICAL_BLOCKS_IN_1ST_SEGMENT +
+ (PhyBlock - 1) * MS_LOGICAL_BLOCKS_PER_SEGMENT;/*496*/
+ *LogEnde = *LogStart + MS_LOGICAL_BLOCKS_PER_SEGMENT;/*496*/
+ } else {
*LogStart = 0;
- *LogEnde = MS_LOGICAL_BLOCKS_IN_1ST_SEGMENT;//494
+ *LogEnde = MS_LOGICAL_BLOCKS_IN_1ST_SEGMENT;/*494*/
}
}
-//----- MS_LibReadExtraBlock() --------------------------------------------
-int MS_LibReadExtraBlock(struct us_data *us, DWORD PhyBlock, BYTE PageNum, BYTE blen, void *buf)
+/*
+ * MS_LibReadExtraBlock()
+ */
+int MS_LibReadExtraBlock(struct us_data *us, DWORD PhyBlock,
+ BYTE PageNum, BYTE blen, void *buf)
{
struct bulk_cb_wrap *bcb = (struct bulk_cb_wrap *) us->iobuf;
int result;
- //printk("MS_LibReadExtraBlock --- PhyBlock = %x, PageNum = %x, blen = %x\n", PhyBlock, PageNum, blen);
+ /* printk("MS_LibReadExtraBlock --- PhyBlock = %x,
+ PageNum = %x, blen = %x\n", PhyBlock, PageNum, blen); */
- // Read Extra Data
+ /* Read Extra Data */
memset(bcb, 0, sizeof(struct bulk_cb_wrap));
bcb->Signature = cpu_to_le32(US_BULK_CB_SIGN);
bcb->DataTransferLength = 0x4 * blen;
@@ -688,14 +747,18 @@
return USB_STOR_TRANSPORT_GOOD;
}
-//----- MS_LibReadExtra() --------------------------------------------
-int MS_LibReadExtra(struct us_data *us, DWORD PhyBlock, BYTE PageNum, MS_LibTypeExtdat *ExtraDat)
+/*
+ * MS_LibReadExtra()
+ */
+int MS_LibReadExtra(struct us_data *us, DWORD PhyBlock,
+ BYTE PageNum, MS_LibTypeExtdat *ExtraDat)
{
struct bulk_cb_wrap *bcb = (struct bulk_cb_wrap *) us->iobuf;
int result;
BYTE ExtBuf[4];
- //printk("MS_LibReadExtra --- PhyBlock = %x, PageNum = %x\n", PhyBlock, PageNum);
+ /* printk("MS_LibReadExtra --- PhyBlock = %x, PageNum = %x\n"
+ , PhyBlock, PageNum); */
memset(bcb, 0, sizeof(struct bulk_cb_wrap));
bcb->Signature = cpu_to_le32(US_BULK_CB_SIGN);
bcb->DataTransferLength = 0x4;
@@ -707,23 +770,25 @@
bcb->CDB[3] = (BYTE)(PhyBlock>>8);
bcb->CDB[2] = (BYTE)(PhyBlock>>16);
bcb->CDB[6] = 0x01;
-
+
result = ENE_SendScsiCmd(us, FDIR_READ, &ExtBuf, 0);
if (result != USB_STOR_XFER_GOOD)
return USB_STOR_TRANSPORT_ERROR;
ExtraDat->reserved = 0;
- ExtraDat->intr = 0x80; // Not yet, waiting for fireware support
- ExtraDat->status0 = 0x10; // Not yet, waiting for fireware support
- ExtraDat->status1 = 0x00; // Not yet, waiting for fireware support
+ ExtraDat->intr = 0x80; /* Not yet, waiting for fireware support */
+ ExtraDat->status0 = 0x10; /* Not yet, waiting for fireware support */
+ ExtraDat->status1 = 0x00; /* Not yet, waiting for fireware support */
ExtraDat->ovrflg = ExtBuf[0];
ExtraDat->mngflg = ExtBuf[1];
ExtraDat->logadr = MemStickLogAddr(ExtBuf[2], ExtBuf[3]);
-
+
return USB_STOR_TRANSPORT_GOOD;
}
-//----- MS_LibSetAcquiredErrorBlock() --------------------------------
+/*
+ * MS_LibSetAcquiredErrorBlock()
+ */
int MS_LibSetAcquiredErrorBlock(struct us_data *us, WORD phyblk)
{
WORD log;
@@ -731,7 +796,9 @@
if (phyblk >= us->MS_Lib.NumberOfPhyBlock)
return (DWORD)-1;
- if ((log = us->MS_Lib.Phy2LogMap[phyblk]) < us->MS_Lib.NumberOfLogBlock)
+ log = us->MS_Lib.Phy2LogMap[phyblk];
+
+ if (log < us->MS_Lib.NumberOfLogBlock)
us->MS_Lib.Log2PhyMap[log] = MS_LB_NOT_USED;
if (us->MS_Lib.Phy2LogMap[phyblk] != MS_LB_INITIAL_ERROR)
@@ -740,7 +807,9 @@
return 0;
}
-//----- MS_LibErasePhyBlock() ----------------------------------------
+/*
+ * MS_LibErasePhyBlock()
+ */
int MS_LibErasePhyBlock(struct us_data *us, WORD phyblk)
{
WORD log;
@@ -748,27 +817,27 @@
if (phyblk >= us->MS_Lib.NumberOfPhyBlock)
return MS_STATUS_ERROR;
- if ((log = us->MS_Lib.Phy2LogMap[phyblk]) < us->MS_Lib.NumberOfLogBlock)
+ log = us->MS_Lib.Phy2LogMap[phyblk];
+
+ if (log < us->MS_Lib.NumberOfLogBlock)
us->MS_Lib.Log2PhyMap[log] = MS_LB_NOT_USED;
us->MS_Lib.Phy2LogMap[phyblk] = MS_LB_NOT_USED;
- if (MS_LibIsWritable(us))
- {
- switch (MS_ReaderEraseBlock(us, phyblk))
- {
- case MS_STATUS_SUCCESS:
- us->MS_Lib.Phy2LogMap[phyblk] = MS_LB_NOT_USED_ERASED;
- return MS_STATUS_SUCCESS;
- case MS_ERROR_FLASH_ERASE:
- case MS_STATUS_INT_ERROR :
- MS_LibErrorPhyBlock(us, phyblk);
- return MS_ERROR_FLASH_ERASE;
- case MS_STATUS_ERROR:
- default:
- MS_LibCtrlSet(us, MS_LIB_CTRL_RDONLY);
- MS_LibSetAcquiredErrorBlock(us, phyblk);
- return MS_STATUS_ERROR;
+ if (MS_LibIsWritable(us)) {
+ switch (MS_ReaderEraseBlock(us, phyblk)) {
+ case MS_STATUS_SUCCESS:
+ us->MS_Lib.Phy2LogMap[phyblk] = MS_LB_NOT_USED_ERASED;
+ return MS_STATUS_SUCCESS;
+ case MS_ERROR_FLASH_ERASE:
+ case MS_STATUS_INT_ERROR:
+ MS_LibErrorPhyBlock(us, phyblk);
+ return MS_ERROR_FLASH_ERASE;
+ case MS_STATUS_ERROR:
+ default:
+ MS_LibCtrlSet(us, MS_LIB_CTRL_RDONLY);
+ MS_LibSetAcquiredErrorBlock(us, phyblk);
+ return MS_STATUS_ERROR;
}
}
@@ -777,28 +846,35 @@
return MS_STATUS_SUCCESS;
}
-//----- MS_LibErrorPhyBlock() ----------------------------------------
+/*
+ * MS_LibErrorPhyBlock()
+ */
int MS_LibErrorPhyBlock(struct us_data *us, WORD phyblk)
{
- if (phyblk >= us->MS_Lib.NumberOfPhyBlock)
- return MS_STATUS_ERROR;
+ if (phyblk >= us->MS_Lib.NumberOfPhyBlock)
+ return MS_STATUS_ERROR;
- MS_LibSetAcquiredErrorBlock(us, phyblk);
+ MS_LibSetAcquiredErrorBlock(us, phyblk);
- if (MS_LibIsWritable(us))
- return MS_LibOverwriteExtra(us, phyblk, 0, (BYTE)(~MS_REG_OVR_BKST));
+ if (MS_LibIsWritable(us))
+ return MS_LibOverwriteExtra(us, phyblk, 0,
+ (BYTE)(~MS_REG_OVR_BKST & BYTE_MASK));
- return MS_STATUS_SUCCESS;
+ return MS_STATUS_SUCCESS;
}
-//----- MS_LibOverwriteExtra() ---------------------------------------
-int MS_LibOverwriteExtra(struct us_data *us, DWORD PhyBlockAddr, BYTE PageNum, BYTE OverwriteFlag)
+/*
+ * MS_LibOverwriteExtra()
+ */
+int MS_LibOverwriteExtra(struct us_data *us, DWORD PhyBlockAddr,
+ BYTE PageNum, BYTE OverwriteFlag)
{
struct bulk_cb_wrap *bcb = (struct bulk_cb_wrap *) us->iobuf;
int result;
- //printk("MS --- MS_LibOverwriteExtra, PhyBlockAddr = %x, PageNum = %x\n", PhyBlockAddr, PageNum);
+ /* printk("MS --- MS_LibOverwriteExtra, \
+ PhyBlockAddr = %x, PageNum = %x\n", PhyBlockAddr, PageNum); */
result = ENE_LoadBinCode(us, MS_RW_PATTERN);
if (result != USB_STOR_XFER_GOOD)
return USB_STOR_TRANSPORT_ERROR;
@@ -817,7 +893,7 @@
bcb->CDB[7] = 0xFF;
bcb->CDB[8] = 0xFF;
bcb->CDB[9] = 0xFF;
-
+
result = ENE_SendScsiCmd(us, FDIR_READ, NULL, 0);
if (result != USB_STOR_XFER_GOOD)
return USB_STOR_TRANSPORT_ERROR;
@@ -825,13 +901,16 @@
return USB_STOR_TRANSPORT_GOOD;
}
-//----- MS_LibForceSetLogicalPair() ----------------------------------
+/*
+ * MS_LibForceSetLogicalPair()
+ */
int MS_LibForceSetLogicalPair(struct us_data *us, WORD logblk, WORD phyblk)
{
if (logblk == MS_LB_NOT_USED)
return 0;
- if ((logblk >= us->MS_Lib.NumberOfLogBlock) || (phyblk >= us->MS_Lib.NumberOfPhyBlock))
+ if ((logblk >= us->MS_Lib.NumberOfLogBlock) ||
+ (phyblk >= us->MS_Lib.NumberOfPhyBlock))
return (DWORD)-1;
us->MS_Lib.Phy2LogMap[phyblk] = logblk;
@@ -840,10 +919,13 @@
return 0;
}
-//----- MS_LibSetLogicalPair() ---------------------------------------
+/*
+ * MS_LibSetLogicalPair()
+ */
int MS_LibSetLogicalPair(struct us_data *us, WORD logblk, WORD phyblk)
{
- if ((logblk >= us->MS_Lib.NumberOfLogBlock) || (phyblk >= us->MS_Lib.NumberOfPhyBlock))
+ if ((logblk >= us->MS_Lib.NumberOfLogBlock) ||
+ (phyblk >= us->MS_Lib.NumberOfPhyBlock))
return (DWORD)-1;
us->MS_Lib.Phy2LogMap[phyblk] = logblk;
@@ -852,28 +934,30 @@
return 0;
}
-//----- MS_CountFreeBlock() ------------------------------------------
+/*
+ * MS_CountFreeBlock()
+ */
int MS_CountFreeBlock(struct us_data *us, WORD PhyBlock)
{
DWORD Ende, Count;
Ende = PhyBlock + MS_PHYSICAL_BLOCKS_PER_SEGMENT;
- for (Count = 0; PhyBlock < Ende; PhyBlock++)
- {
- switch (us->MS_Lib.Phy2LogMap[PhyBlock])
- {
- case MS_LB_NOT_USED:
- case MS_LB_NOT_USED_ERASED:
- Count++;
- default:
- break;
+ for (Count = 0; PhyBlock < Ende; PhyBlock++) {
+ switch (us->MS_Lib.Phy2LogMap[PhyBlock]) {
+ case MS_LB_NOT_USED:
+ case MS_LB_NOT_USED_ERASED:
+ Count++;
+ default:
+ break;
}
}
return Count;
}
-//----- MS_LibSearchBlockFromPhysical() ------------------------------
+/*
+ * MS_LibSearchBlockFromPhysical()
+ */
int MS_LibSearchBlockFromPhysical(struct us_data *us, WORD phyblk)
{
WORD Newblk;
@@ -883,70 +967,68 @@
if (phyblk >= us->MS_Lib.NumberOfPhyBlock)
return MS_LB_ERROR;
- for (blk = phyblk + 1; blk != phyblk; blk++)
- {
+ for (blk = phyblk + 1; blk != phyblk; blk++) {
if ((blk & MS_PHYSICAL_BLOCKS_PER_SEGMENT_MASK) == 0)
blk -= MS_PHYSICAL_BLOCKS_PER_SEGMENT;
Newblk = us->MS_Lib.Phy2LogMap[blk];
if (us->MS_Lib.Phy2LogMap[blk] == MS_LB_NOT_USED_ERASED)
return blk;
- else if (us->MS_Lib.Phy2LogMap[blk] == MS_LB_NOT_USED)
- {
- switch (MS_LibReadExtra(us, blk, 0, &extdat))
- {
- case MS_STATUS_SUCCESS :
- case MS_STATUS_SUCCESS_WITH_ECC:
- break;
- case MS_NOCARD_ERROR:
- return MS_NOCARD_ERROR;
- case MS_STATUS_INT_ERROR:
- return MS_LB_ERROR;
- case MS_ERROR_FLASH_READ:
- default:
- MS_LibSetAcquiredErrorBlock(us, blk); // MS_LibErrorPhyBlock(fdoExt, blk);
- continue;
- } // End switch
+ else if (us->MS_Lib.Phy2LogMap[blk] == MS_LB_NOT_USED) {
+ switch (MS_LibReadExtra(us, blk, 0, &extdat)) {
+ case MS_STATUS_SUCCESS:
+ case MS_STATUS_SUCCESS_WITH_ECC:
+ break;
+ case MS_NOCARD_ERROR:
+ return MS_NOCARD_ERROR;
+ case MS_STATUS_INT_ERROR:
+ return MS_LB_ERROR;
+ case MS_ERROR_FLASH_READ:
+ default:
+ MS_LibSetAcquiredErrorBlock(us, blk);
+ /* MS_LibErrorPhyBlock(fdoExt, blk); */
+ continue;
+ } /* End switch */
- if ((extdat.ovrflg & MS_REG_OVR_BKST) != MS_REG_OVR_BKST_OK)
- {
+ if ((extdat.ovrflg & MS_REG_OVR_BKST) !=
+ MS_REG_OVR_BKST_OK) {
MS_LibSetAcquiredErrorBlock(us, blk);
continue;
}
- switch (MS_LibErasePhyBlock(us, blk))
- {
- case MS_STATUS_SUCCESS:
- return blk;
- case MS_STATUS_ERROR:
- return MS_LB_ERROR;
- case MS_ERROR_FLASH_ERASE:
- default:
- MS_LibErrorPhyBlock(us, blk);
- break;
+ switch (MS_LibErasePhyBlock(us, blk)) {
+ case MS_STATUS_SUCCESS:
+ return blk;
+ case MS_STATUS_ERROR:
+ return MS_LB_ERROR;
+ case MS_ERROR_FLASH_ERASE:
+ default:
+ MS_LibErrorPhyBlock(us, blk);
+ break;
}
}
- } // End for
+ } /* End for */
return MS_LB_ERROR;
}
-//----- MS_LibSearchBlockFromLogical() -------------------------------
+/*
+ * MS_LibSearchBlockFromLogical()
+ */
int MS_LibSearchBlockFromLogical(struct us_data *us, WORD logblk)
{
WORD phyblk;
- if ((phyblk=MS_LibConv2Physical(us, logblk)) >= MS_LB_ERROR)
- {
+ phyblk = MS_LibConv2Physical(us, logblk);
+ if (phyblk >= MS_LB_ERROR) {
if (logblk >= us->MS_Lib.NumberOfLogBlock)
return MS_LB_ERROR;
- phyblk = (logblk + MS_NUMBER_OF_BOOT_BLOCK) / MS_LOGICAL_BLOCKS_PER_SEGMENT;
+ phyblk = (logblk + MS_NUMBER_OF_BOOT_BLOCK) /
+ MS_LOGICAL_BLOCKS_PER_SEGMENT;
phyblk *= MS_PHYSICAL_BLOCKS_PER_SEGMENT;
phyblk += MS_PHYSICAL_BLOCKS_PER_SEGMENT - 1;
}
return MS_LibSearchBlockFromPhysical(us, phyblk);
}
-
-
diff --git a/drivers/staging/keucr/ms.h b/drivers/staging/keucr/ms.h
index 4509db7..a3da4be 100644
--- a/drivers/staging/keucr/ms.h
+++ b/drivers/staging/keucr/ms.h
@@ -4,41 +4,41 @@
#include <linux/blkdev.h>
#include "common.h"
-// MemoryStick Register
-// Status Register 0
-#define MS_REG_ST0_MB 0x80 // media busy
-#define MS_REG_ST0_FB0 0x40 // flush busy 0
-#define MS_REG_ST0_BE 0x20 // buffer empty
-#define MS_REG_ST0_BF 0x10 // buffer full
-#define MS_REG_ST0_SL 0x02 // sleep
-#define MS_REG_ST0_WP 0x01 // write protected
+/* MemoryStick Register */
+/* Status Register 0 */
+#define MS_REG_ST0_MB 0x80 /* media busy */
+#define MS_REG_ST0_FB0 0x40 /* flush busy 0 */
+#define MS_REG_ST0_BE 0x20 /* buffer empty */
+#define MS_REG_ST0_BF 0x10 /* buffer full */
+#define MS_REG_ST0_SL 0x02 /* sleep */
+#define MS_REG_ST0_WP 0x01 /* write protected */
#define MS_REG_ST0_WP_ON MS_REG_ST0_WP
#define MS_REG_ST0_WP_OFF 0x00
-// Status Register 1
-#define MS_REG_ST1_MB 0x80 // media busy
-#define MS_REG_ST1_FB1 0x40 // flush busy 1
-#define MS_REG_ST1_DTER 0x20 // error on data(corrected)
-#define MS_REG_ST1_UCDT 0x10 // unable to correct data
-#define MS_REG_ST1_EXER 0x08 // error on extra(corrected)
-#define MS_REG_ST1_UCEX 0x04 // unable to correct extra
-#define MS_REG_ST1_FGER 0x02 // error on overwrite flag(corrected)
-#define MS_REG_ST1_UCFG 0x01 // unable to correct overwrite flag
-#define MS_REG_ST1_DEFAULT (MS_REG_ST1_MB | MS_REG_ST1_FB1 | \
- MS_REG_ST1_DTER | MS_REG_ST1_UCDT | \
- MS_REG_ST1_EXER | MS_REG_ST1_UCEX | \
- MS_REG_ST1_FGER | MS_REG_ST1_UCFG)
+/* Status Register 1 */
+#define MS_REG_ST1_MB 0x80 /* media busy */
+#define MS_REG_ST1_FB1 0x40 /* flush busy 1 */
+#define MS_REG_ST1_DTER 0x20 /* error on data(corrected) */
+#define MS_REG_ST1_UCDT 0x10 /* unable to correct data */
+#define MS_REG_ST1_EXER 0x08 /* error on extra(corrected) */
+#define MS_REG_ST1_UCEX 0x04 /* unable to correct extra */
+#define MS_REG_ST1_FGER 0x02 /* error on overwrite flag(corrected) */
+#define MS_REG_ST1_UCFG 0x01 /* unable to correct overwrite flag */
+#define MS_REG_ST1_DEFAULT (MS_REG_ST1_MB | MS_REG_ST1_FB1 | \
+ MS_REG_ST1_DTER | MS_REG_ST1_UCDT | \
+ MS_REG_ST1_EXER | MS_REG_ST1_UCEX | \
+ MS_REG_ST1_FGER | MS_REG_ST1_UCFG)
-// System Parameter
-#define MS_REG_SYSPAR_BAMD 0x80 // block address mode
-#define MS_REG_SYSPAR_BAND_LINEAR MS_REG_SYSPAR_BAMD // linear mode
-#define MS_REG_SYSPAR_BAND_CHIP 0x00 // chip mode
-#define MS_REG_SYSPAR_ATEN 0x40 // attribute ROM enable
-#define MS_REG_SYSPAR_ATEN_ENABLE MS_REG_SYSPAR_ATEN // enable
-#define MS_REG_SYSPAR_ATEN_DISABLE 0x00 // disable
+/* System Parameter */
+#define MS_REG_SYSPAR_BAMD 0x80 /* block address mode */
+#define MS_REG_SYSPAR_BAND_LINEAR MS_REG_SYSPAR_BAMD /* linear mode */
+#define MS_REG_SYSPAR_BAND_CHIP 0x00 /* chip mode */
+#define MS_REG_SYSPAR_ATEN 0x40 /* attribute ROM enable */
+#define MS_REG_SYSPAR_ATEN_ENABLE MS_REG_SYSPAR_ATEN /* enable */
+#define MS_REG_SYSPAR_ATEN_DISABLE 0x00 /* disable */
#define MS_REG_SYSPAR_RESERVED 0x2f
-// Command Parameter
+/* Command Parameter */
#define MS_REG_CMDPAR_CP2 0x80
#define MS_REG_CMDPAR_CP1 0x40
#define MS_REG_CMDPAR_CP0 0x20
@@ -48,44 +48,44 @@
#define MS_REG_CMDPAR_OVERWRITE MS_REG_CMDPAR_CP2
#define MS_REG_CMDPAR_RESERVED 0x1f
-// Overwrite Area
-#define MS_REG_OVR_BKST 0x80 // block status
-#define MS_REG_OVR_BKST_OK MS_REG_OVR_BKST // OK
-#define MS_REG_OVR_BKST_NG 0x00 // NG
-#define MS_REG_OVR_PGST0 0x40 // page status
+/* Overwrite Area */
+#define MS_REG_OVR_BKST 0x80 /* block status */
+#define MS_REG_OVR_BKST_OK MS_REG_OVR_BKST /* OK */
+#define MS_REG_OVR_BKST_NG 0x00 /* NG */
+#define MS_REG_OVR_PGST0 0x40 /* page status */
#define MS_REG_OVR_PGST1 0x20
-#define MS_REG_OVR_PGST_MASK (MS_REG_OVR_PGST0 | MS_REG_OVR_PGST1)
-#define MS_REG_OVR_PGST_OK (MS_REG_OVR_PGST0 | MS_REG_OVR_PGST1) // OK
-#define MS_REG_OVR_PGST_NG MS_REG_OVR_PGST1 // NG
-#define MS_REG_OVR_PGST_DATA_ERROR 0x00 // data error
-#define MS_REG_OVR_UDST 0x10 // update status
-#define MS_REG_OVR_UDST_UPDATING 0x00 // updating
+#define MS_REG_OVR_PGST_MASK (MS_REG_OVR_PGST0 | MS_REG_OVR_PGST1)
+#define MS_REG_OVR_PGST_OK (MS_REG_OVR_PGST0 | MS_REG_OVR_PGST1) /* OK */
+#define MS_REG_OVR_PGST_NG MS_REG_OVR_PGST1 /* NG */
+#define MS_REG_OVR_PGST_DATA_ERROR 0x00 /* data error */
+#define MS_REG_OVR_UDST 0x10 /* update status */
+#define MS_REG_OVR_UDST_UPDATING 0x00 /* updating */
#define MS_REG_OVR_UDST_NO_UPDATE MS_REG_OVR_UDST
#define MS_REG_OVR_RESERVED 0x08
#define MS_REG_OVR_DEFAULT (MS_REG_OVR_BKST_OK | \
- MS_REG_OVR_PGST_OK | \
- MS_REG_OVR_UDST_NO_UPDATE | \
- MS_REG_OVR_RESERVED)
-// Management Flag
-#define MS_REG_MNG_SCMS0 0x20 // serial copy management system
+ MS_REG_OVR_PGST_OK | \
+ MS_REG_OVR_UDST_NO_UPDATE | \
+ MS_REG_OVR_RESERVED)
+/* Management Flag */
+#define MS_REG_MNG_SCMS0 0x20 /* serial copy management system */
#define MS_REG_MNG_SCMS1 0x10
-#define MS_REG_MNG_SCMS_MASK (MS_REG_MNG_SCMS0 | MS_REG_MNG_SCMS1)
-#define MS_REG_MNG_SCMS_COPY_OK (MS_REG_MNG_SCMS0 | MS_REG_MNG_SCMS1)
+#define MS_REG_MNG_SCMS_MASK (MS_REG_MNG_SCMS0 | MS_REG_MNG_SCMS1)
+#define MS_REG_MNG_SCMS_COPY_OK (MS_REG_MNG_SCMS0 | MS_REG_MNG_SCMS1)
#define MS_REG_MNG_SCMS_ONE_COPY MS_REG_MNG_SCMS1
#define MS_REG_MNG_SCMS_NO_COPY 0x00
-#define MS_REG_MNG_ATFLG 0x08 // address transfer table flag
-#define MS_REG_MNG_ATFLG_OTHER MS_REG_MNG_ATFLG // other
-#define MS_REG_MNG_ATFLG_ATTBL 0x00 // address transfer table
-#define MS_REG_MNG_SYSFLG 0x04 // system flag
-#define MS_REG_MNG_SYSFLG_USER MS_REG_MNG_SYSFLG // user block
-#define MS_REG_MNG_SYSFLG_BOOT 0x00 // system block
+#define MS_REG_MNG_ATFLG 0x08 /* address transfer table flag */
+#define MS_REG_MNG_ATFLG_OTHER MS_REG_MNG_ATFLG /* other */
+#define MS_REG_MNG_ATFLG_ATTBL 0x00 /* address transfer table */
+#define MS_REG_MNG_SYSFLG 0x04 /* system flag */
+#define MS_REG_MNG_SYSFLG_USER MS_REG_MNG_SYSFLG /* user block */
+#define MS_REG_MNG_SYSFLG_BOOT 0x00 /* system block */
#define MS_REG_MNG_RESERVED 0xc3
#define MS_REG_MNG_DEFAULT (MS_REG_MNG_SCMS_COPY_OK | \
MS_REG_MNG_ATFLG_OTHER | \
MS_REG_MNG_SYSFLG_USER | \
MS_REG_MNG_RESERVED)
-// Error codes
+/* Error codes */
#define MS_STATUS_SUCCESS 0x0000
#define MS_ERROR_OUT_OF_SPACE 0x0103
#define MS_STATUS_WRITE_PROTECT 0x0106
@@ -110,29 +110,41 @@
#define MS_LB_ACQUIRED_ERROR 0xfff4
#define MS_LB_NOT_USED_ERASED 0xfff5
-#define MS_LibConv2Physical(pdx, LogBlock) (((LogBlock) >= (pdx)->MS_Lib.NumberOfLogBlock) ? MS_STATUS_ERROR : (pdx)->MS_Lib.Log2PhyMap[LogBlock])
-#define MS_LibConv2Logical(pdx, PhyBlock) (((PhyBlock) >= (pdx)->MS_Lib.NumberOfPhyBlock) ? MS_STATUS_ERROR : (pdx)->MS_Lib.Phy2LogMap[PhyBlock]) //¬dphy->log table
+#define MS_LibConv2Physical(pdx, LogBlock) \
+ (((LogBlock) >= (pdx)->MS_Lib.NumberOfLogBlock) ? \
+ MS_STATUS_ERROR : (pdx)->MS_Lib.Log2PhyMap[LogBlock])
+#define MS_LibConv2Logical(pdx, PhyBlock) \
+ (((PhyBlock) >= (pdx)->MS_Lib.NumberOfPhyBlock) ? \
+ MS_STATUS_ERROR : (pdx)->MS_Lib.Phy2LogMap[PhyBlock])
+ /*dphy->log table */
#define MS_LIB_CTRL_RDONLY 0
#define MS_LIB_CTRL_WRPROTECT 1
-#define MS_LibCtrlCheck(pdx, Flag) ((pdx)->MS_Lib.flags & (1 << (Flag)))
+#define MS_LibCtrlCheck(pdx, Flag) ((pdx)->MS_Lib.flags & (1 << (Flag)))
-#define MS_LibCtrlSet(pdx, Flag) (pdx)->MS_Lib.flags |= (1 << (Flag))
-#define MS_LibCtrlReset(pdx, Flag) (pdx)->MS_Lib.flags &= ~(1 << (Flag))
-#define MS_LibIsWritable(pdx) ((MS_LibCtrlCheck((pdx), MS_LIB_CTRL_RDONLY) == 0) && (MS_LibCtrlCheck(pdx, MS_LIB_CTRL_WRPROTECT) == 0))
+#define MS_LibCtrlSet(pdx, Flag) ((pdx)->MS_Lib.flags |= (1 << (Flag)))
+#define MS_LibCtrlReset(pdx, Flag) ((pdx)->MS_Lib.flags &= ~(1 << (Flag)))
+#define MS_LibIsWritable(pdx) \
+ ((MS_LibCtrlCheck((pdx), MS_LIB_CTRL_RDONLY) == 0) && \
+ (MS_LibCtrlCheck(pdx, MS_LIB_CTRL_WRPROTECT) == 0))
#define MS_MAX_PAGES_PER_BLOCK 32
#define MS_LIB_BITS_PER_BYTE 8
-#define MS_LibPageMapIdx(n) ((n) / MS_LIB_BITS_PER_BYTE)
-#define MS_LibPageMapBit(n) (1 << ((n) % MS_LIB_BITS_PER_BYTE))
-#define MS_LibCheckPageMapBit(pdx, n) ((pdx)->MS_Lib.pagemap[MS_LibPageMapIdx(n)] & MS_LibPageMapBit(n))
-#define MS_LibSetPageMapBit(pdx, n) ((pdx)->MS_Lib.pagemap[MS_LibPageMapIdx(n)] |= MS_LibPageMapBit(n))
-#define MS_LibResetPageMapBit(pdx, n) ((pdx)->MS_Lib.pagemap[MS_LibPageMapIdx(n)] &= ~MS_LibPageMapBit(n))
-#define MS_LibClearPageMap(pdx) memset((pdx)->MS_Lib.pagemap, 0, sizeof((pdx)->MS_Lib.pagemap))
+#define MS_LibPageMapIdx(n) ((n) / MS_LIB_BITS_PER_BYTE)
+#define MS_LibPageMapBit(n) (1 << ((n) % MS_LIB_BITS_PER_BYTE))
+#define MS_LibCheckPageMapBit(pdx, n) \
+ ((pdx)->MS_Lib.pagemap[MS_LibPageMapIdx(n)] & MS_LibPageMapBit(n))
+#define MS_LibSetPageMapBit(pdx, n) \
+ ((pdx)->MS_Lib.pagemap[MS_LibPageMapIdx(n)] |= MS_LibPageMapBit(n))
+#define MS_LibResetPageMapBit(pdx, n) \
+ ((pdx)->MS_Lib.pagemap[MS_LibPageMapIdx(n)] &= ~MS_LibPageMapBit(n))
+#define MS_LibClearPageMap(pdx) \
+ memset((pdx)->MS_Lib.pagemap, 0, sizeof((pdx)->MS_Lib.pagemap))
-#define MemStickLogAddr(logadr1, logadr0) ((((WORD)(logadr1)) << 8) | (logadr0))
+#define MemStickLogAddr(logadr1, logadr0) \
+ ((((WORD)(logadr1)) << 8) | (logadr0))
#define MS_BYTES_PER_PAGE 512
@@ -144,7 +156,7 @@
#define MS_NUMBER_OF_SYSTEM_BLOCK 4
#define MS_LOGICAL_BLOCKS_PER_SEGMENT 496
#define MS_LOGICAL_BLOCKS_IN_1ST_SEGMENT 494
-#define MS_PHYSICAL_BLOCKS_PER_SEGMENT 0x200 // 512
+#define MS_PHYSICAL_BLOCKS_PER_SEGMENT 0x200 /* 512 */
#define MS_PHYSICAL_BLOCKS_PER_SEGMENT_MASK 0x1ff
#define MS_SECTOR_SIZE 512
@@ -165,51 +177,53 @@
#define MS_SYSINF_SECURITY 0x01
#define MS_SYSINF_SECURITY_NO_SUPPORT MS_SYSINF_SECURITY
#define MS_SYSINF_SECURITY_SUPPORT 0
-#define MS_SYSINF_FORMAT_MAT 0 // ?
+#define MS_SYSINF_FORMAT_MAT 0 /* ? */
#define MS_SYSINF_FORMAT_FAT 1
#define MS_SYSINF_USAGE_GENERAL 0
-#define MS_SYSINF_PAGE_SIZE MS_BYTES_PER_PAGE // fixed
+#define MS_SYSINF_PAGE_SIZE MS_BYTES_PER_PAGE /* fixed */
#define MS_SYSINF_RESERVED1 1
#define MS_SYSINF_RESERVED2 1
#define MS_SYSENT_TYPE_INVALID_BLOCK 0x01
-#define MS_SYSENT_TYPE_CIS_IDI 0x0a // CIS/IDI
+#define MS_SYSENT_TYPE_CIS_IDI 0x0a /* CIS/IDI */
#define SIZE_OF_KIRO 1024
-// BOOT BLOCK
+/* BOOT BLOCK */
#define MS_NUMBER_OF_SYSTEM_ENTRY 4
-//----- MemStickRegisters --------------------------------------------
-// Status registers (16 bytes)
+/*
+ * MemStickRegisters
+ */
+/* Status registers (16 bytes) */
typedef struct {
- BYTE Reserved0; // 00
- BYTE INTRegister; // 01
- BYTE StatusRegister0; // 02
- BYTE StatusRegister1; // 03
- BYTE Reserved1[12]; // 04-0F
+ BYTE Reserved0; /* 00 */
+ BYTE INTRegister; /* 01 */
+ BYTE StatusRegister0; /* 02 */
+ BYTE StatusRegister1; /* 03 */
+ BYTE Reserved1[12]; /* 04-0F */
} MemStickStatusRegisters;
-// Parameter registers (6 bytes)
+/* Parameter registers (6 bytes) */
typedef struct {
- BYTE SystemParameter; // 10
- BYTE BlockAddress2; // 11
- BYTE BlockAddress1; // 12
- BYTE BlockAddress0; // 13
- BYTE CMDParameter; // 14
- BYTE PageAddress; // 15
+ BYTE SystemParameter; /* 10 */
+ BYTE BlockAddress2; /* 11 */
+ BYTE BlockAddress1; /* 12 */
+ BYTE BlockAddress0; /* 13 */
+ BYTE CMDParameter; /* 14 */
+ BYTE PageAddress; /* 15 */
} MemStickParameterRegisters;
-// Extra registers (9 bytes)
+/* Extra registers (9 bytes) */
typedef struct {
- BYTE OverwriteFlag; // 16
- BYTE ManagementFlag; // 17
- BYTE LogicalAddress1; // 18
- BYTE LogicalAddress0; // 19
- BYTE ReservedArea[5]; // 1A-1E
+ BYTE OverwriteFlag; /* 16 */
+ BYTE ManagementFlag; /* 17 */
+ BYTE LogicalAddress1; /* 18 */
+ BYTE LogicalAddress0; /* 19 */
+ BYTE ReservedArea[5]; /* 1A-1E */
} MemStickExtraDataRegisters;
-// All registers in Memory Stick (32 bytes, includes 1 byte padding)
+/* All registers in Memory Stick (32 bytes, includes 1 byte padding) */
typedef struct {
MemStickStatusRegisters status;
MemStickParameterRegisters param;
@@ -217,7 +231,9 @@
BYTE padding;
} MemStickRegisters, *PMemStickRegisters;
-//----- MemStickBootBlockPage0 ---------------------------------------
+/*
+ * MemStickBootBlockPage0
+ */
typedef struct {
WORD wBlockID;
WORD wFormatVersion;
@@ -238,13 +254,13 @@
} MemStickBootBlockSysEnt;
typedef struct {
- BYTE bMsClass; // must be 1
- BYTE bCardType; // see below
- WORD wBlockSize; // n KB
- WORD wBlockNumber; // number of physical block
- WORD wTotalBlockNumber; // number of logical block
- WORD wPageSize; // must be 0x200
- BYTE bExtraSize; // 0x10
+ BYTE bMsClass; /* must be 1 */
+ BYTE bCardType; /* see below */
+ WORD wBlockSize; /* n KB */
+ WORD wBlockNumber; /* number of physical block */
+ WORD wTotalBlockNumber; /* number of logical block */
+ WORD wPageSize; /* must be 0x200 */
+ BYTE bExtraSize; /* 0x10 */
BYTE bSecuritySupport;
BYTE bAssemblyDate[8];
BYTE bFactoryArea[4];
@@ -258,10 +274,10 @@
BYTE bVCC;
BYTE bVPP;
WORD wControllerChipNumber;
- WORD wControllerFunction; // New MS
- BYTE bReserved3[9]; // New MS
- BYTE bParallelSupport; // New MS
- WORD wFormatValue; // New MS
+ WORD wControllerFunction; /* New MS */
+ BYTE bReserved3[9]; /* New MS */
+ BYTE bParallelSupport; /* New MS */
+ WORD wFormatValue; /* New MS */
BYTE bFormatType;
BYTE bUsage;
BYTE bDeviceType;
@@ -277,60 +293,62 @@
MemStickBootBlockSysInf sysinf;
} MemStickBootBlockPage0;
-//----- MemStickBootBlockCIS_IDI -------------------------------------
+/*
+ * MemStickBootBlockCIS_IDI
+ */
typedef struct {
- BYTE bCistplDEVICE[6]; // 0
- BYTE bCistplDEVICE0C[6]; // 6
- BYTE bCistplJEDECC[4]; // 12
- BYTE bCistplMANFID[6]; // 16
- BYTE bCistplVER1[32]; // 22
- BYTE bCistplFUNCID[4]; // 54
- BYTE bCistplFUNCE0[4]; // 58
- BYTE bCistplFUNCE1[5]; // 62
- BYTE bCistplCONF[7]; // 67
- BYTE bCistplCFTBLENT0[10]; // 74
- BYTE bCistplCFTBLENT1[8]; // 84
- BYTE bCistplCFTBLENT2[12]; // 92
- BYTE bCistplCFTBLENT3[8]; // 104
- BYTE bCistplCFTBLENT4[17]; // 112
- BYTE bCistplCFTBLENT5[8]; // 129
- BYTE bCistplCFTBLENT6[17]; // 137
- BYTE bCistplCFTBLENT7[8]; // 154
- BYTE bCistplNOLINK[3]; // 162
+ BYTE bCistplDEVICE[6]; /* 0 */
+ BYTE bCistplDEVICE0C[6]; /* 6 */
+ BYTE bCistplJEDECC[4]; /* 12 */
+ BYTE bCistplMANFID[6]; /* 16 */
+ BYTE bCistplVER1[32]; /* 22 */
+ BYTE bCistplFUNCID[4]; /* 54 */
+ BYTE bCistplFUNCE0[4]; /* 58 */
+ BYTE bCistplFUNCE1[5]; /* 62 */
+ BYTE bCistplCONF[7]; /* 67 */
+ BYTE bCistplCFTBLENT0[10]; /* 74 */
+ BYTE bCistplCFTBLENT1[8]; /* 84 */
+ BYTE bCistplCFTBLENT2[12]; /* 92 */
+ BYTE bCistplCFTBLENT3[8]; /* 104 */
+ BYTE bCistplCFTBLENT4[17]; /* 112 */
+ BYTE bCistplCFTBLENT5[8]; /* 129 */
+ BYTE bCistplCFTBLENT6[17]; /* 137 */
+ BYTE bCistplCFTBLENT7[8]; /* 154 */
+ BYTE bCistplNOLINK[3]; /* 162 */
} MemStickBootBlockCIS;
typedef struct {
#define MS_IDI_GENERAL_CONF 0x848A
- WORD wIDIgeneralConfiguration; // 0
- WORD wIDInumberOfCylinder; // 1
- WORD wIDIreserved0; // 2
- WORD wIDInumberOfHead; // 3
- WORD wIDIbytesPerTrack; // 4
- WORD wIDIbytesPerSector; // 5
- WORD wIDIsectorsPerTrack; // 6
- WORD wIDItotalSectors[2]; // 7-8 high,low
- WORD wIDIreserved1[11]; // 9-19
- WORD wIDIbufferType; // 20
- WORD wIDIbufferSize; // 21
- WORD wIDIlongCmdECC; // 22
- WORD wIDIfirmVersion[4]; // 23-26
- WORD wIDImodelName[20]; // 27-46
- WORD wIDIreserved2; // 47
- WORD wIDIlongWordSupported; // 48
- WORD wIDIdmaSupported; // 49
- WORD wIDIreserved3; // 50
- WORD wIDIpioTiming; // 51
- WORD wIDIdmaTiming; // 52
- WORD wIDItransferParameter; // 53
- WORD wIDIformattedCylinder; // 54
- WORD wIDIformattedHead; // 55
- WORD wIDIformattedSectorsPerTrack; // 56
- WORD wIDIformattedTotalSectors[2]; // 57-58
- WORD wIDImultiSector; // 59
- WORD wIDIlbaSectors[2]; // 60-61
- WORD wIDIsingleWordDMA; // 62
- WORD wIDImultiWordDMA; // 63
- WORD wIDIreserved4[192]; // 64-255
+ WORD wIDIgeneralConfiguration; /* 0 */
+ WORD wIDInumberOfCylinder; /* 1 */
+ WORD wIDIreserved0; /* 2 */
+ WORD wIDInumberOfHead; /* 3 */
+ WORD wIDIbytesPerTrack; /* 4 */
+ WORD wIDIbytesPerSector; /* 5 */
+ WORD wIDIsectorsPerTrack; /* 6 */
+ WORD wIDItotalSectors[2]; /* 7-8 high,low */
+ WORD wIDIreserved1[11]; /* 9-19 */
+ WORD wIDIbufferType; /* 20 */
+ WORD wIDIbufferSize; /* 21 */
+ WORD wIDIlongCmdECC; /* 22 */
+ WORD wIDIfirmVersion[4]; /* 23-26 */
+ WORD wIDImodelName[20]; /* 27-46 */
+ WORD wIDIreserved2; /* 47 */
+ WORD wIDIlongWordSupported; /* 48 */
+ WORD wIDIdmaSupported; /* 49 */
+ WORD wIDIreserved3; /* 50 */
+ WORD wIDIpioTiming; /* 51 */
+ WORD wIDIdmaTiming; /* 52 */
+ WORD wIDItransferParameter; /* 53 */
+ WORD wIDIformattedCylinder; /* 54 */
+ WORD wIDIformattedHead; /* 55 */
+ WORD wIDIformattedSectorsPerTrack; /* 56 */
+ WORD wIDIformattedTotalSectors[2]; /* 57-58 */
+ WORD wIDImultiSector; /* 59 */
+ WORD wIDIlbaSectors[2]; /* 60-61 */
+ WORD wIDIsingleWordDMA; /* 62 */
+ WORD wIDImultiWordDMA; /* 63 */
+ WORD wIDIreserved4[192]; /* 64-255 */
} MemStickBootBlockIDI;
typedef struct {
@@ -346,7 +364,9 @@
} MemStickBootBlockCIS_IDI;
-//----- MS_LibControl ------------------------------------------------
+/*
+ * MS_LibControl
+ */
typedef struct {
BYTE reserved;
BYTE intr;
@@ -362,14 +382,14 @@
DWORD BytesPerSector;
DWORD NumberOfCylinder;
DWORD SectorsPerCylinder;
- WORD cardType; // R/W, RO, Hybrid
+ WORD cardType; /* R/W, RO, Hybrid */
WORD blockSize;
WORD PagesPerBlock;
WORD NumberOfPhyBlock;
WORD NumberOfLogBlock;
WORD NumberOfSegment;
- WORD *Phy2LogMap; // phy2log table
- WORD *Log2PhyMap; // log2phy table
+ WORD *Phy2LogMap; /* phy2log table */
+ WORD *Log2PhyMap; /* log2phy table */
WORD wrtblk;
BYTE pagemap[(MS_MAX_PAGES_PER_BLOCK + (MS_LIB_BITS_PER_BYTE-1)) /
MS_LIB_BITS_PER_BYTE];
diff --git a/drivers/staging/keucr/msscsi.c b/drivers/staging/keucr/msscsi.c
index cb92d25..cb7190e 100644
--- a/drivers/staging/keucr/msscsi.c
+++ b/drivers/staging/keucr/msscsi.c
@@ -1,3 +1,5 @@
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
#include <linux/sched.h>
#include <linux/errno.h>
#include <linux/slab.h>
@@ -10,68 +12,48 @@
#include "scsiglue.h"
#include "transport.h"
-int MS_SCSI_Test_Unit_Ready (struct us_data *us, struct scsi_cmnd *srb);
-int MS_SCSI_Inquiry (struct us_data *us, struct scsi_cmnd *srb);
-int MS_SCSI_Mode_Sense (struct us_data *us, struct scsi_cmnd *srb);
-int MS_SCSI_Start_Stop (struct us_data *us, struct scsi_cmnd *srb);
-int MS_SCSI_Read_Capacity (struct us_data *us, struct scsi_cmnd *srb);
-int MS_SCSI_Read (struct us_data *us, struct scsi_cmnd *srb);
-int MS_SCSI_Write (struct us_data *us, struct scsi_cmnd *srb);
-
-//----- MS_SCSIIrp() --------------------------------------------------
-int MS_SCSIIrp(struct us_data *us, struct scsi_cmnd *srb)
-{
- int result;
-
- us->SrbStatus = SS_SUCCESS;
- switch (srb->cmnd[0])
- {
- case TEST_UNIT_READY : result = MS_SCSI_Test_Unit_Ready (us, srb); break; //0x00
- case INQUIRY : result = MS_SCSI_Inquiry (us, srb); break; //0x12
- case MODE_SENSE : result = MS_SCSI_Mode_Sense (us, srb); break; //0x1A
- case READ_CAPACITY : result = MS_SCSI_Read_Capacity (us, srb); break; //0x25
- case READ_10 : result = MS_SCSI_Read (us, srb); break; //0x28
- case WRITE_10 : result = MS_SCSI_Write (us, srb); break; //0x2A
-
- default:
- us->SrbStatus = SS_ILLEGAL_REQUEST;
- result = USB_STOR_TRANSPORT_FAILED;
- break;
- }
- return result;
-}
-
-//----- MS_SCSI_Test_Unit_Ready() --------------------------------------------------
+/*
+ * MS_SCSI_Test_Unit_Ready()
+ */
int MS_SCSI_Test_Unit_Ready(struct us_data *us, struct scsi_cmnd *srb)
{
- //printk("MS_SCSI_Test_Unit_Ready\n");
+ /* pr_info("MS_SCSI_Test_Unit_Ready\n"); */
if (us->MS_Status.Insert && us->MS_Status.Ready)
return USB_STOR_TRANSPORT_GOOD;
- else
- {
+ else {
ENE_MSInit(us);
return USB_STOR_TRANSPORT_GOOD;
}
-
+
return USB_STOR_TRANSPORT_GOOD;
}
-//----- MS_SCSI_Inquiry() --------------------------------------------------
+/*
+ * MS_SCSI_Inquiry()
+ */
int MS_SCSI_Inquiry(struct us_data *us, struct scsi_cmnd *srb)
{
- //printk("MS_SCSI_Inquiry\n");
- BYTE data_ptr[36] = {0x00, 0x80, 0x02, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x55, 0x53, 0x42, 0x32, 0x2E, 0x30, 0x20, 0x20, 0x43, 0x61, 0x72, 0x64, 0x52, 0x65, 0x61, 0x64, 0x65, 0x72, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x30, 0x31, 0x30, 0x30};
+ /* pr_info("MS_SCSI_Inquiry\n"); */
+ BYTE data_ptr[36] = {0x00, 0x80, 0x02, 0x00, 0x1F, 0x00,
+ 0x00, 0x00, 0x55, 0x53, 0x42, 0x32,
+ 0x2E, 0x30, 0x20, 0x20, 0x43, 0x61,
+ 0x72, 0x64, 0x52, 0x65, 0x61, 0x64,
+ 0x65, 0x72, 0x20, 0x20, 0x20, 0x20,
+ 0x20, 0x20, 0x30, 0x31, 0x30, 0x30};
usb_stor_set_xfer_buf(us, data_ptr, 36, srb, TO_XFER_BUF);
return USB_STOR_TRANSPORT_GOOD;
}
-
-//----- MS_SCSI_Mode_Sense() --------------------------------------------------
+/*
+ * MS_SCSI_Mode_Sense()
+ */
int MS_SCSI_Mode_Sense(struct us_data *us, struct scsi_cmnd *srb)
{
- BYTE mediaNoWP[12] = {0x0b,0x00,0x00,0x08,0x00,0x00,0x71,0xc0,0x00,0x00,0x02,0x00};
- BYTE mediaWP[12] = {0x0b,0x00,0x80,0x08,0x00,0x00,0x71,0xc0,0x00,0x00,0x02,0x00};
+ BYTE mediaNoWP[12] = {0x0b, 0x00, 0x00, 0x08, 0x00, 0x00,
+ 0x71, 0xc0, 0x00, 0x00, 0x02, 0x00};
+ BYTE mediaWP[12] = {0x0b, 0x00, 0x80, 0x08, 0x00, 0x00,
+ 0x71, 0xc0, 0x00, 0x00, 0x02, 0x00};
if (us->MS_Status.WtP)
usb_stor_set_xfer_buf(us, mediaWP, 12, srb, TO_XFER_BUF);
@@ -82,7 +64,9 @@
return USB_STOR_TRANSPORT_GOOD;
}
-//----- MS_SCSI_Read_Capacity() --------------------------------------------------
+/*
+ * MS_SCSI_Read_Capacity()
+ */
int MS_SCSI_Read_Capacity(struct us_data *us, struct scsi_cmnd *srb)
{
unsigned int offset = 0;
@@ -91,60 +75,65 @@
WORD bl_len;
BYTE buf[8];
- printk("MS_SCSI_Read_Capacity\n");
+ pr_info("MS_SCSI_Read_Capacity\n");
bl_len = 0x200;
- if ( us->MS_Status.IsMSPro )
+ if (us->MS_Status.IsMSPro)
bl_num = us->MSP_TotalBlock - 1;
else
- bl_num = us->MS_Lib.NumberOfLogBlock * us->MS_Lib.blockSize * 2 - 1;
+ bl_num = us->MS_Lib.NumberOfLogBlock *
+ us->MS_Lib.blockSize * 2 - 1;
us->bl_num = bl_num;
- printk("bl_len = %x\n", bl_len);
- printk("bl_num = %x\n", bl_num);
+ pr_info("bl_len = %x\n", bl_len);
+ pr_info("bl_num = %x\n", bl_num);
- //srb->request_bufflen = 8;
- buf[0] = (bl_num>>24) & 0xff;
- buf[1] = (bl_num>>16) & 0xff;
- buf[2] = (bl_num>> 8) & 0xff;
- buf[3] = (bl_num>> 0) & 0xff;
- buf[4] = (bl_len>>24) & 0xff;
- buf[5] = (bl_len>>16) & 0xff;
- buf[6] = (bl_len>> 8) & 0xff;
- buf[7] = (bl_len>> 0) & 0xff;
-
+ /* srb->request_bufflen = 8; */
+ buf[0] = (bl_num >> 24) & 0xff;
+ buf[1] = (bl_num >> 16) & 0xff;
+ buf[2] = (bl_num >> 8) & 0xff;
+ buf[3] = (bl_num >> 0) & 0xff;
+ buf[4] = (bl_len >> 24) & 0xff;
+ buf[5] = (bl_len >> 16) & 0xff;
+ buf[6] = (bl_len >> 8) & 0xff;
+ buf[7] = (bl_len >> 0) & 0xff;
+
usb_stor_access_xfer_buf(us, buf, 8, srb, &sg, &offset, TO_XFER_BUF);
- //usb_stor_set_xfer_buf(us, buf, srb->request_bufflen, srb, TO_XFER_BUF);
+ /* usb_stor_set_xfer_buf(us, buf, srb->request_bufflen,
+ srb, TO_XFER_BUF); */
return USB_STOR_TRANSPORT_GOOD;
}
-//----- MS_SCSI_Read() --------------------------------------------------
+/*
+ * MS_SCSI_Read()
+ */
int MS_SCSI_Read(struct us_data *us, struct scsi_cmnd *srb)
{
struct bulk_cb_wrap *bcb = (struct bulk_cb_wrap *) us->iobuf;
- int result=0;
+ int result = 0;
PBYTE Cdb = srb->cmnd;
- DWORD bn = ((Cdb[2]<<24) & 0xff000000) | ((Cdb[3]<<16) & 0x00ff0000) |
- ((Cdb[4]<< 8) & 0x0000ff00) | ((Cdb[5]<< 0) & 0x000000ff);
- WORD blen = ((Cdb[7]<< 8) & 0xff00) | ((Cdb[8]<< 0) & 0x00ff);
+ DWORD bn = ((Cdb[2] << 24) & 0xff000000) |
+ ((Cdb[3] << 16) & 0x00ff0000) |
+ ((Cdb[4] << 8) & 0x0000ff00) |
+ ((Cdb[5] << 0) & 0x000000ff);
+ WORD blen = ((Cdb[7] << 8) & 0xff00) | ((Cdb[8] << 0) & 0x00ff);
DWORD blenByte = blen * 0x200;
- //printk("SCSIOP_READ --- bn = %X, blen = %X, srb->use_sg = %X\n", bn, blen, srb->use_sg);
-
+ /* pr_info("SCSIOP_READ --- bn = %X, blen = %X, srb->use_sg = %X\n",
+ bn, blen, srb->use_sg); */
+
if (bn > us->bl_num)
return USB_STOR_TRANSPORT_ERROR;
- if (us->MS_Status.IsMSPro)
- {
+ if (us->MS_Status.IsMSPro) {
result = ENE_LoadBinCode(us, MSP_RW_PATTERN);
- if (result != USB_STOR_XFER_GOOD)
- {
- printk("Load MSP RW pattern Fail !!\n");
+ if (result != USB_STOR_XFER_GOOD) {
+ pr_info("Load MSP RW pattern Fail !!\n");
return USB_STOR_TRANSPORT_ERROR;
}
- // set up the command wrapper
+ /* set up the command wrapper */
memset(bcb, 0, sizeof(struct bulk_cb_wrap));
bcb->Signature = cpu_to_le32(US_BULK_CB_SIGN);
bcb->DataTransferLength = blenByte;
@@ -157,11 +146,9 @@
bcb->CDB[2] = (BYTE)(bn>>24);
result = ENE_SendScsiCmd(us, FDIR_READ, scsi_sglist(srb), 1);
- }
- else
- {
+ } else {
void *buf;
- int offset=0;
+ int offset = 0;
WORD phyblk, logblk;
BYTE PageNum;
WORD len;
@@ -172,9 +159,8 @@
return USB_STOR_TRANSPORT_ERROR;
result = ENE_LoadBinCode(us, MS_RW_PATTERN);
- if (result != USB_STOR_XFER_GOOD)
- {
- printk("Load MS RW pattern Fail !!\n");
+ if (result != USB_STOR_XFER_GOOD) {
+ pr_info("Load MS RW pattern Fail !!\n");
result = USB_STOR_TRANSPORT_ERROR;
goto exit;
}
@@ -182,9 +168,8 @@
logblk = (WORD)(bn / us->MS_Lib.PagesPerBlock);
PageNum = (BYTE)(bn % us->MS_Lib.PagesPerBlock);
- while(1)
- {
- if (blen > (us->MS_Lib.PagesPerBlock-PageNum) )
+ while (1) {
+ if (blen > (us->MS_Lib.PagesPerBlock-PageNum))
len = us->MS_Lib.PagesPerBlock-PageNum;
else
len = blen;
@@ -192,7 +177,7 @@
phyblk = MS_LibConv2Physical(us, logblk);
blkno = phyblk * 0x20 + PageNum;
- // set up the command wrapper
+ /* set up the command wrapper */
memset(bcb, 0, sizeof(struct bulk_cb_wrap));
bcb->Signature = cpu_to_le32(US_BULK_CB_SIGN);
bcb->DataTransferLength = 0x200 * len;
@@ -205,15 +190,15 @@
bcb->CDB[2] = (BYTE)(blkno>>24);
result = ENE_SendScsiCmd(us, FDIR_READ, buf+offset, 0);
- if (result != USB_STOR_XFER_GOOD)
- {
- printk("MS_SCSI_Read --- result = %x\n", result);
+ if (result != USB_STOR_XFER_GOOD) {
+ pr_info("MS_SCSI_Read --- result = %x\n",
+ result);
result = USB_STOR_TRANSPORT_ERROR;
goto exit;
}
blen -= len;
- if (blen<=0)
+ if (blen <= 0)
break;
logblk++;
PageNum = 0;
@@ -226,30 +211,32 @@
return result;
}
-//----- MS_SCSI_Write() --------------------------------------------------
+/*
+ * MS_SCSI_Write()
+ */
int MS_SCSI_Write(struct us_data *us, struct scsi_cmnd *srb)
{
struct bulk_cb_wrap *bcb = (struct bulk_cb_wrap *) us->iobuf;
- int result=0;
+ int result = 0;
PBYTE Cdb = srb->cmnd;
- DWORD bn = ((Cdb[2]<<24) & 0xff000000) | ((Cdb[3]<<16) & 0x00ff0000) |
- ((Cdb[4]<< 8) & 0x0000ff00) | ((Cdb[5]<< 0) & 0x000000ff);
- WORD blen = ((Cdb[7]<< 8) & 0xff00) | ((Cdb[8]<< 0) & 0x00ff);
+ DWORD bn = ((Cdb[2] << 24) & 0xff000000) |
+ ((Cdb[3] << 16) & 0x00ff0000) |
+ ((Cdb[4] << 8) & 0x0000ff00) |
+ ((Cdb[5] << 0) & 0x000000ff);
+ WORD blen = ((Cdb[7] << 8) & 0xff00) | ((Cdb[8] << 0) & 0x00ff);
DWORD blenByte = blen * 0x200;
if (bn > us->bl_num)
return USB_STOR_TRANSPORT_ERROR;
- if (us->MS_Status.IsMSPro)
- {
+ if (us->MS_Status.IsMSPro) {
result = ENE_LoadBinCode(us, MSP_RW_PATTERN);
- if (result != USB_STOR_XFER_GOOD)
- {
- printk("Load MSP RW pattern Fail !!\n");
+ if (result != USB_STOR_XFER_GOOD) {
+ pr_info("Load MSP RW pattern Fail !!\n");
return USB_STOR_TRANSPORT_ERROR;
}
- // set up the command wrapper
+ /* set up the command wrapper */
memset(bcb, 0, sizeof(struct bulk_cb_wrap));
bcb->Signature = cpu_to_le32(US_BULK_CB_SIGN);
bcb->DataTransferLength = blenByte;
@@ -262,11 +249,9 @@
bcb->CDB[2] = (BYTE)(bn>>24);
result = ENE_SendScsiCmd(us, FDIR_WRITE, scsi_sglist(srb), 1);
- }
- else
- {
+ } else {
void *buf;
- int offset=0;
+ int offset = 0;
WORD PhyBlockAddr;
BYTE PageNum;
DWORD result;
@@ -278,9 +263,8 @@
usb_stor_set_xfer_buf(us, buf, blenByte, srb, FROM_XFER_BUF);
result = ENE_LoadBinCode(us, MS_RW_PATTERN);
- if (result != USB_STOR_XFER_GOOD)
- {
- printk("Load MS RW pattern Fail !!\n");
+ if (result != USB_STOR_XFER_GOOD) {
+ pr_info("Load MS RW pattern Fail !!\n");
result = USB_STOR_TRANSPORT_ERROR;
goto exit;
}
@@ -288,9 +272,8 @@
PhyBlockAddr = (WORD)(bn / us->MS_Lib.PagesPerBlock);
PageNum = (BYTE)(bn % us->MS_Lib.PagesPerBlock);
- while(1)
- {
- if (blen > (us->MS_Lib.PagesPerBlock-PageNum) )
+ while (1) {
+ if (blen > (us->MS_Lib.PagesPerBlock-PageNum))
len = us->MS_Lib.PagesPerBlock-PageNum;
else
len = blen;
@@ -298,10 +281,12 @@
oldphy = MS_LibConv2Physical(us, PhyBlockAddr);
newphy = MS_LibSearchBlockFromLogical(us, PhyBlockAddr);
- result = MS_ReaderCopyBlock(us, oldphy, newphy, PhyBlockAddr, PageNum, buf+offset, len);
- if (result != USB_STOR_XFER_GOOD)
- {
- printk("MS_SCSI_Write --- result = %x\n", result);
+ result = MS_ReaderCopyBlock(us, oldphy, newphy,
+ PhyBlockAddr, PageNum,
+ buf+offset, len);
+ if (result != USB_STOR_XFER_GOOD) {
+ pr_info("MS_SCSI_Write --- result = %x\n",
+ result);
result = USB_STOR_TRANSPORT_ERROR;
goto exit;
}
@@ -310,7 +295,7 @@
MS_LibForceSetLogicalPair(us, PhyBlockAddr, newphy);
blen -= len;
- if (blen<=0)
+ if (blen <= 0)
break;
PhyBlockAddr++;
PageNum = 0;
@@ -322,3 +307,38 @@
return result;
}
+/*
+ * MS_SCSIIrp()
+ */
+int MS_SCSIIrp(struct us_data *us, struct scsi_cmnd *srb)
+{
+ int result;
+
+ us->SrbStatus = SS_SUCCESS;
+ switch (srb->cmnd[0]) {
+ case TEST_UNIT_READY:
+ result = MS_SCSI_Test_Unit_Ready(us, srb);
+ break; /* 0x00 */
+ case INQUIRY:
+ result = MS_SCSI_Inquiry(us, srb);
+ break; /* 0x12 */
+ case MODE_SENSE:
+ result = MS_SCSI_Mode_Sense(us, srb);
+ break; /* 0x1A */
+ case READ_CAPACITY:
+ result = MS_SCSI_Read_Capacity(us, srb);
+ break; /* 0x25 */
+ case READ_10:
+ result = MS_SCSI_Read(us, srb);
+ break; /* 0x28 */
+ case WRITE_10:
+ result = MS_SCSI_Write(us, srb);
+ break; /* 0x2A */
+ default:
+ us->SrbStatus = SS_ILLEGAL_REQUEST;
+ result = USB_STOR_TRANSPORT_FAILED;
+ break;
+ }
+ return result;
+}
+
diff --git a/drivers/staging/keucr/scsiglue.c b/drivers/staging/keucr/scsiglue.c
index da4f42a..135f7f2 100644
--- a/drivers/staging/keucr/scsiglue.c
+++ b/drivers/staging/keucr/scsiglue.c
@@ -1,3 +1,5 @@
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/mutex.h>
@@ -13,19 +15,23 @@
#include "transport.h"
/* Host functions */
-//----- host_info() ---------------------
-static const char* host_info(struct Scsi_Host *host)
+/*
+ * host_info()
+ */
+static const char *host_info(struct Scsi_Host *host)
{
- //printk("scsiglue --- host_info\n");
+ /* pr_info("scsiglue --- host_info\n"); */
return "SCSI emulation for USB Mass Storage devices";
}
-//----- slave_alloc() ---------------------
+/*
+ * slave_alloc()
+ */
static int slave_alloc(struct scsi_device *sdev)
{
struct us_data *us = host_to_us(sdev->host);
- //printk("scsiglue --- slave_alloc\n");
+ /* pr_info("scsiglue --- slave_alloc\n"); */
sdev->inquiry_len = 36;
blk_queue_update_dma_alignment(sdev->request_queue, (512 - 1));
@@ -36,14 +42,15 @@
return 0;
}
-//----- slave_configure() ---------------------
+/*
+ * slave_configure()
+ */
static int slave_configure(struct scsi_device *sdev)
{
struct us_data *us = host_to_us(sdev->host);
- //printk("scsiglue --- slave_configure\n");
- if (us->fflags & (US_FL_MAX_SECTORS_64 | US_FL_MAX_SECTORS_MIN))
- {
+ /* pr_info("scsiglue --- slave_configure\n"); */
+ if (us->fflags & (US_FL_MAX_SECTORS_64 | US_FL_MAX_SECTORS_MIN)) {
unsigned int max_sectors = 64;
if (us->fflags & US_FL_MAX_SECTORS_MIN)
@@ -53,9 +60,9 @@
max_sectors);
}
- if (sdev->type == TYPE_DISK)
- {
- if (us->subclass != USB_SC_SCSI && us->subclass != USB_SC_CYP_ATACB)
+ if (sdev->type == TYPE_DISK) {
+ if (us->subclass != USB_SC_SCSI &&
+ us->subclass != USB_SC_CYP_ATACB)
sdev->use_10_for_ms = 1;
sdev->use_192_bytes_for_3f = 1;
if (us->fflags & US_FL_NO_WP_DETECT)
@@ -70,13 +77,12 @@
sdev->retry_hwerror = 1;
sdev->allow_restart = 1;
sdev->last_sector_bug = 1;
- }
- else
- {
+ } else {
sdev->use_10_for_ms = 1;
}
- if ((us->protocol == USB_PR_CB || us->protocol == USB_PR_CBI) && sdev->scsi_level == SCSI_UNKNOWN)
+ if ((us->protocol == USB_PR_CB || us->protocol == USB_PR_CBI) &&
+ sdev->scsi_level == SCSI_UNKNOWN)
us->max_lun = 0;
if (us->fflags & US_FL_NOT_LOCKABLE)
@@ -86,24 +92,26 @@
}
/* This is always called with scsi_lock(host) held */
-//----- queuecommand() ---------------------
-static int queuecommand_lck(struct scsi_cmnd *srb, void (*done)(struct scsi_cmnd *))
+/*
+ * queuecommand()
+ */
+static int queuecommand_lck(struct scsi_cmnd *srb,
+ void (*done)(struct scsi_cmnd *))
{
struct us_data *us = host_to_us(srb->device->host);
- //printk("scsiglue --- queuecommand\n");
+ /* pr_info("scsiglue --- queuecommand\n"); */
/* check for state-transition errors */
- if (us->srb != NULL)
- {
- printk("Error in %s: us->srb = %p\n", __FUNCTION__, us->srb);
+ if (us->srb != NULL) {
+ /* pr_info("Error in %s: us->srb = %p\n"
+ __FUNCTION__, us->srb); */
return SCSI_MLQUEUE_HOST_BUSY;
}
/* fail the command if we are disconnecting */
- if (test_bit(US_FLIDX_DISCONNECTING, &us->dflags))
- {
- printk("Fail command during disconnect\n");
+ if (test_bit(US_FLIDX_DISCONNECTING, &us->dflags)) {
+ pr_info("Fail command during disconnect\n");
srb->result = DID_NO_CONNECT << 16;
done(srb);
return 0;
@@ -124,24 +132,24 @@
***********************************************************************/
/* Command timeout and abort */
-//----- command_abort() ---------------------
+/*
+ * command_abort()
+ */
static int command_abort(struct scsi_cmnd *srb)
{
struct us_data *us = host_to_us(srb->device->host);
- //printk("scsiglue --- command_abort\n");
+ /* pr_info("scsiglue --- command_abort\n"); */
scsi_lock(us_to_host(us));
- if (us->srb != srb)
- {
+ if (us->srb != srb) {
scsi_unlock(us_to_host(us));
printk ("-- nothing to abort\n");
return FAILED;
}
set_bit(US_FLIDX_TIMED_OUT, &us->dflags);
- if (!test_bit(US_FLIDX_RESETTING, &us->dflags))
- {
+ if (!test_bit(US_FLIDX_RESETTING, &us->dflags)) {
set_bit(US_FLIDX_ABORTING, &us->dflags);
usb_stor_stop_transport(us);
}
@@ -152,14 +160,18 @@
return SUCCESS;
}
-/* This invokes the transport reset mechanism to reset the state of the device */
-//----- device_reset() ---------------------
+/* This invokes the transport reset mechanism to reset the state of the
+ * device.
+ */
+/*
+ * device_reset()
+ */
static int device_reset(struct scsi_cmnd *srb)
{
struct us_data *us = host_to_us(srb->device->host);
int result;
- //printk("scsiglue --- device_reset\n");
+ /* pr_info("scsiglue --- device_reset\n"); */
/* lock the device pointers and do the reset */
mutex_lock(&(us->dev_mutex));
@@ -169,38 +181,43 @@
return result < 0 ? FAILED : SUCCESS;
}
-//----- bus_reset() ---------------------
+/*
+ * bus_reset()
+ */
static int bus_reset(struct scsi_cmnd *srb)
{
struct us_data *us = host_to_us(srb->device->host);
int result;
- //printk("scsiglue --- bus_reset\n");
+ /* pr_info("scsiglue --- bus_reset\n"); */
result = usb_stor_port_reset(us);
return result < 0 ? FAILED : SUCCESS;
}
-//----- usb_stor_report_device_reset() ---------------------
+/*
+ * usb_stor_report_device_reset()
+ */
void usb_stor_report_device_reset(struct us_data *us)
{
int i;
struct Scsi_Host *host = us_to_host(us);
- //printk("scsiglue --- usb_stor_report_device_reset\n");
+ /* pr_info("scsiglue --- usb_stor_report_device_reset\n"); */
scsi_report_device_reset(host, 0, 0);
- if (us->fflags & US_FL_SCM_MULT_TARG)
- {
+ if (us->fflags & US_FL_SCM_MULT_TARG) {
for (i = 1; i < host->max_id; ++i)
scsi_report_device_reset(host, 0, i);
}
}
-//----- usb_stor_report_bus_reset() ---------------------
+/*
+ * usb_stor_report_bus_reset()
+ */
void usb_stor_report_bus_reset(struct us_data *us)
{
struct Scsi_Host *host = us_to_host(us);
- //printk("scsiglue --- usb_stor_report_bus_reset\n");
+ /* pr_info("scsiglue --- usb_stor_report_bus_reset\n"); */
scsi_lock(host);
scsi_report_bus_reset(host, 0);
scsi_unlock(host);
@@ -215,14 +232,17 @@
#define SPRINTF(args...) \
do { if (pos < buffer+length) pos += sprintf(pos, ## args); } while (0)
-//----- proc_info() ---------------------
-static int proc_info (struct Scsi_Host *host, char *buffer, char **start, off_t offset, int length, int inout)
+/*
+ * proc_info()
+ */
+static int proc_info(struct Scsi_Host *host, char *buffer, char **start,
+ off_t offset, int length, int inout)
{
struct us_data *us = host_to_us(host);
char *pos = buffer;
const char *string;
- //printk("scsiglue --- proc_info\n");
+ /* pr_info("scsiglue --- proc_info\n"); */
if (inout)
return length;
@@ -255,8 +275,7 @@
SPRINTF(" Transport: %s\n", us->transport_name);
/* show the device flags */
- if (pos < buffer + length)
- {
+ if (pos < buffer + length) {
pos += sprintf(pos, " Quirks:");
#define US_FLAG(name, value) \
@@ -271,11 +290,11 @@
*start = buffer + offset;
if ((pos - buffer) < offset)
- return (0);
+ return 0;
else if ((pos - buffer - offset) < length)
- return (pos - buffer - offset);
+ return pos - buffer - offset;
else
- return (length);
+ return length;
}
/***********************************************************************
@@ -283,29 +302,35 @@
***********************************************************************/
/* Output routine for the sysfs max_sectors file */
-//----- show_max_sectors() ---------------------
-static ssize_t show_max_sectors(struct device *dev, struct device_attribute *attr, char *buf)
+/*
+ * show_max_sectors()
+ */
+static ssize_t show_max_sectors(struct device *dev,
+ struct device_attribute *attr, char *buf)
{
struct scsi_device *sdev = to_scsi_device(dev);
- //printk("scsiglue --- ssize_t show_max_sectors\n");
+ /* pr_info("scsiglue --- ssize_t show_max_sectors\n"); */
return sprintf(buf, "%u\n", queue_max_sectors(sdev->request_queue));
}
/* Input routine for the sysfs max_sectors file */
-//----- store_max_sectors() ---------------------
-static ssize_t store_max_sectors(struct device *dev, struct device_attribute *attr, const char *buf, size_t count)
+/*
+ * store_max_sectors()
+ */
+static ssize_t store_max_sectors(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
{
struct scsi_device *sdev = to_scsi_device(dev);
unsigned short ms;
- //printk("scsiglue --- ssize_t store_max_sectors\n");
- if (sscanf(buf, "%hu", &ms) > 0 && ms <= SCSI_DEFAULT_MAX_SECTORS)
- {
+ /* pr_info("scsiglue --- ssize_t store_max_sectors\n"); */
+ if (sscanf(buf, "%hu", &ms) > 0 && ms <= SCSI_DEFAULT_MAX_SECTORS) {
blk_queue_max_hw_sectors(sdev->request_queue, ms);
return strlen(buf);
}
- return -EINVAL;
+ return -EINVAL;
}
static DEVICE_ATTR(max_sectors, S_IRUGO | S_IWUSR, show_max_sectors, store_max_sectors);
@@ -313,7 +338,9 @@
/* this defines our host template, with which we'll allocate hosts */
-//----- usb_stor_host_template() ---------------------
+/*
+ * usb_stor_host_template()
+ */
struct scsi_host_template usb_stor_host_template = {
/* basic userland interface stuff */
.name = "eucr-storage",
@@ -376,42 +403,41 @@
* Scatter-gather transfer buffer access routines
***********************************************************************/
-//----- usb_stor_access_xfer_buf() ---------------------
+/*
+ * usb_stor_access_xfer_buf()
+ */
unsigned int usb_stor_access_xfer_buf(struct us_data *us, unsigned char *buffer,
unsigned int buflen, struct scsi_cmnd *srb, struct scatterlist **sgptr,
unsigned int *offset, enum xfer_buf_dir dir)
{
unsigned int cnt;
- //printk("transport --- usb_stor_access_xfer_buf\n");
+ /* pr_info("transport --- usb_stor_access_xfer_buf\n"); */
struct scatterlist *sg = *sgptr;
if (!sg)
sg = scsi_sglist(srb);
cnt = 0;
- while (cnt < buflen && sg)
- {
- struct page *page = sg_page(sg) + ((sg->offset + *offset) >> PAGE_SHIFT);
+ while (cnt < buflen && sg) {
+ struct page *page = sg_page(sg) +
+ ((sg->offset + *offset) >> PAGE_SHIFT);
unsigned int poff = (sg->offset + *offset) & (PAGE_SIZE-1);
unsigned int sglen = sg->length - *offset;
- if (sglen > buflen - cnt)
- {
+ if (sglen > buflen - cnt) {
/* Transfer ends within this s-g entry */
sglen = buflen - cnt;
*offset += sglen;
- }
- else
- {
+ } else {
/* Transfer continues to next s-g entry */
*offset = 0;
sg = sg_next(sg);
}
- while (sglen > 0)
- {
- unsigned int plen = min(sglen, (unsigned int)PAGE_SIZE - poff);
+ while (sglen > 0) {
+ unsigned int plen = min(sglen,
+ (unsigned int)PAGE_SIZE - poff);
unsigned char *ptr = kmap(page);
if (dir == TO_XFER_BUF)
@@ -433,18 +459,24 @@
return cnt;
}
-/* Store the contents of buffer into srb's transfer buffer and set the SCSI residue. */
-//----- usb_stor_set_xfer_buf() ---------------------
-void usb_stor_set_xfer_buf(struct us_data *us, unsigned char *buffer, unsigned int buflen, struct scsi_cmnd *srb,
- unsigned int dir)
+/*
+ * Store the contents of buffer into srb's transfer
+ * buffer and set the SCSI residue.
+ */
+/*
+ * usb_stor_set_xfer_buf()
+ */
+void usb_stor_set_xfer_buf(struct us_data *us, unsigned char *buffer,
+ unsigned int buflen, struct scsi_cmnd *srb, unsigned int dir)
{
unsigned int offset = 0;
struct scatterlist *sg = NULL;
- //printk("transport --- usb_stor_set_xfer_buf\n");
- // TO_XFER_BUF = 0, FROM_XFER_BUF = 1
+ /* pr_info("transport --- usb_stor_set_xfer_buf\n"); */
+ /* TO_XFER_BUF = 0, FROM_XFER_BUF = 1 */
buflen = min(buflen, scsi_bufflen(srb));
- buflen = usb_stor_access_xfer_buf(us, buffer, buflen, srb, &sg, &offset, dir);
+ buflen = usb_stor_access_xfer_buf(us, buffer, buflen, srb,
+ &sg, &offset, dir);
if (buflen < scsi_bufflen(srb))
scsi_set_resid(srb, scsi_bufflen(srb) - buflen);
}
diff --git a/drivers/staging/keucr/smcommon.h b/drivers/staging/keucr/smcommon.h
index 00064ca..278bdb8 100644
--- a/drivers/staging/keucr/smcommon.h
+++ b/drivers/staging/keucr/smcommon.h
@@ -6,7 +6,7 @@
/***************************************************************************
Define Difinetion
***************************************************************************/
-#define SUCCESS 0x0000 /* SUCCESS */
+#define SMSUCCESS 0x0000 /* SUCCESS */
#define ERROR 0xFFFF /* ERROR */
#define CORRECT 0x0001 /* CORRECTABLE */
diff --git a/drivers/staging/keucr/smil.h b/drivers/staging/keucr/smil.h
index 4226813..b5a8fa7 100644
--- a/drivers/staging/keucr/smil.h
+++ b/drivers/staging/keucr/smil.h
@@ -44,21 +44,22 @@
/***************************************************************************
Hardware ECC Definition
***************************************************************************/
-#define HW_ECC_SUPPORTED 1 /* Hardware ECC Supported */ /* No difinition for Software ECC */
+#define HW_ECC_SUPPORTED 1 /* Hardware ECC Supported */
+/* No difinition for Software ECC */
/***************************************************************************
SmartMedia Command & Status Definition
***************************************************************************/
/* SmartMedia Command */
#define WRDATA 0x80
-//#define READ 0x00
+/* #define READ 0x00 */
#define READ_REDT 0x50
-//#define WRITE 0x10
+/* #define WRITE 0x10 */
#define RDSTATUS 0x70
-#define READ1 0x00 //NO
-#define READ2 0x01 //NO
-#define READ3 0x50 //NO
+#define READ1 0x00 /* NO */
+#define READ2 0x01 /* NO */
+#define READ3 0x50 /* NO */
#define RST_CHIP 0xFF
#define ERASE1 0x60
#define ERASE2 0xD0
@@ -67,19 +68,19 @@
#define READ_ID_3 0x9A
/* 712 SmartMedia Command */
-#define SM_CMD_RESET 0x00 // 0xFF
-#define SM_CMD_READ_ID_1 0x10 // 0x90
-#define SM_CMD_READ_ID_2 0x20 // 0x91
-#define SM_CMD_READ_STAT 0x30 // 0x70
-#define SM_CMD_RDMULTPL_STAT 0x40 // 0x71
-#define SM_CMD_READ_1 0x50 // 0x00
-#define SM_CMD_READ_2 0x60 // 0x01
-#define SM_CMD_READ_3 0x70 // 0x50
-#define SM_CMD_PAGPRGM_TRUE 0x80 // {0x80, 0x10}
-#define SM_CMD_PAGPRGM_DUMY 0x90 // {0x80, 0x11}
-#define SM_CMD_PAGPRGM_MBLK 0xA0 // {0x80, 0x15}
-#define SM_CMD_BLKERASE 0xB0 // {0x60, 0xD0}
-#define SM_CMD_BLKERASE_MULTPL 0xC0 // {0x60-0x60, 0xD0}
+#define SM_CMD_RESET 0x00 /* 0xFF */
+#define SM_CMD_READ_ID_1 0x10 /* 0x90 */
+#define SM_CMD_READ_ID_2 0x20 /* 0x91 */
+#define SM_CMD_READ_STAT 0x30 /* 0x70 */
+#define SM_CMD_RDMULTPL_STAT 0x40 /* 0x71 */
+#define SM_CMD_READ_1 0x50 /* 0x00 */
+#define SM_CMD_READ_2 0x60 /* 0x01 */
+#define SM_CMD_READ_3 0x70 /* 0x50 */
+#define SM_CMD_PAGPRGM_TRUE 0x80 /* {0x80, 0x10} */
+#define SM_CMD_PAGPRGM_DUMY 0x90 /* {0x80, 0x11} */
+#define SM_CMD_PAGPRGM_MBLK 0xA0 /* {0x80, 0x15} */
+#define SM_CMD_BLKERASE 0xB0 /* {0x60, 0xD0} */
+#define SM_CMD_BLKERASE_MULTPL 0xC0 /* {0x60-0x60, 0xD0} */
#define SM_CRADDTCT_DEBNCETIMER_EN 0x02
#define SM_CMD_START_BIT 0x01
@@ -87,27 +88,31 @@
#define SM_WaitCmdDone { while (!SM_CmdDone); }
#define SM_WaitDmaDone { while (!SM_DmaDone); }
-// SmartMedia Status
-#define WR_FAIL 0x01 // 0:Pass, 1:Fail
-#define SUSPENDED 0x20 // 0:Not Suspended, 1:Suspended
-#define READY 0x40 // 0:Busy, 1:Ready
-#define WR_PRTCT 0x80 // 0:Protect, 1:Not Protect
+/* SmartMedia Status */
+#define WR_FAIL 0x01 /* 0:Pass, 1:Fail */
+#define SUSPENDED 0x20 /* 0:Not Suspended, 1:Suspended */
+#define READY 0x40 /* 0:Busy, 1:Ready */
+#define WR_PRTCT 0x80 /* 0:Protect, 1:Not Protect */
-// SmartMedia Busy Time (1bit:0.1ms)
-#define BUSY_PROG 200 // tPROG : 20ms ----- Program Time old : 200
-#define BUSY_ERASE 4000 // tBERASE : 400ms ----- Block Erase Time old : 4000
-//for 712 Test
-//#define BUSY_READ 1 // tR : 100us ----- Data transfer Time old : 1
-//#define BUSY_READ 10 // tR : 100us ----- Data transfer Time old : 1
-#define BUSY_READ 200 // tR : 20ms ----- Data transfer Time old : 1
-//#define BUSY_RESET 60 // tRST : 6ms ----- Device Resetting Time old : 60
-#define BUSY_RESET 600 // tRST : 60ms ----- Device Resetting Time old : 60
+/* SmartMedia Busy Time (1bit:0.1ms) */
+#define BUSY_PROG 200 /* tPROG : 20ms ----- Program Time old : 200 */
+#define BUSY_ERASE 4000 /* tBERASE : 400ms ----- Block Erase Time old : 4000 */
-// Hardware Timer (1bit:0.1ms)
-#define TIME_PON 3000 // 300ms ------ Power On Wait Time
-#define TIME_CDCHK 200 // 20ms ------ Card Check Interval Timer
-#define TIME_WPCHK 50 // 5ms ------ WP Check Interval Timer
-#define TIME_5VCHK 10 // 1ms ------ 5V Check Interval Timer
+/*for 712 Test */
+/* #define BUSY_READ 1 *//* tR : 100us ----- Data transfer Time old : 1 */
+/* #define BUSY_READ 10 *//* tR : 100us ----- Data transfer Time old : 1 */
+
+#define BUSY_READ 200 /* tR : 20ms ----- Data transfer Time old : 1 */
+
+/* #define BUSY_RESET 60 *//* tRST : 6ms ----- Device Resetting Time old : 60 */
+
+#define BUSY_RESET 600 /* tRST : 60ms ----- Device Resetting Time old : 60 */
+
+/* Hardware Timer (1bit:0.1ms) */
+#define TIME_PON 3000 /* 300ms ------ Power On Wait Time */
+#define TIME_CDCHK 200 /* 20ms ------ Card Check Interval Timer */
+#define TIME_WPCHK 50 /* 5ms ------ WP Check Interval Timer */
+#define TIME_5VCHK 10 /* 1ms ------ 5V Check Interval Timer */
/***************************************************************************
Redundant Data
@@ -129,32 +134,32 @@
SmartMedia Model & Attribute
***************************************************************************/
/* SmartMedia Attribute */
-#define NOWP 0x00 // 0... .... No Write Protect
-#define WP 0x80 // 1... .... Write Protected
-#define MASK 0x00 // .00. .... NAND MASK ROM Model
-#define FLASH 0x20 // .01. .... NAND Flash ROM Model
-#define AD3CYC 0x00 // ...0 .... Address 3-cycle
-#define AD4CYC 0x10 // ...1 .... Address 4-cycle
-#define BS16 0x00 // .... 00.. 16page/block
-#define BS32 0x04 // .... 01.. 32page/block
-#define PS256 0x00 // .... ..00 256byte/page
-#define PS512 0x01 // .... ..01 512byte/page
-#define MWP 0x80 // WriteProtect mask
-#define MFLASH 0x60 // Flash Rom mask
-#define MADC 0x10 // Address Cycle
-#define MBS 0x0C // BlockSize mask
-#define MPS 0x03 // PageSize mask
+#define NOWP 0x00 /* 0... .... No Write Protect */
+#define WP 0x80 /* 1... .... Write Protected */
+#define MASK 0x00 /* .00. .... NAND MASK ROM Model */
+#define FLASH 0x20 /* .01. .... NAND Flash ROM Model */
+#define AD3CYC 0x00 /* ...0 .... Address 3-cycle */
+#define AD4CYC 0x10 /* ...1 .... Address 4-cycle */
+#define BS16 0x00 /* .... 00.. 16page/block */
+#define BS32 0x04 /* .... 01.. 32page/block */
+#define PS256 0x00 /* .... ..00 256byte/page */
+#define PS512 0x01 /* .... ..01 512byte/page */
+#define MWP 0x80 /* WriteProtect mask */
+#define MFLASH 0x60 /* Flash Rom mask */
+#define MADC 0x10 /* Address Cycle */
+#define MBS 0x0C /* BlockSize mask */
+#define MPS 0x03 /* PageSize mask */
/* SmartMedia Model */
-#define NOSSFDC 0x00 // NO SmartMedia
-#define SSFDC1MB 0x01 // 1MB SmartMedia
-#define SSFDC2MB 0x02 // 2MB SmartMedia
-#define SSFDC4MB 0x03 // 4MB SmartMedia
-#define SSFDC8MB 0x04 // 8MB SmartMedia
-#define SSFDC16MB 0x05 // 16MB SmartMedia
-#define SSFDC32MB 0x06 // 32MB SmartMedia
-#define SSFDC64MB 0x07 // 64MB SmartMedia
-#define SSFDC128MB 0x08 //128MB SmartMedia
+#define NOSSFDC 0x00 /* NO SmartMedia */
+#define SSFDC1MB 0x01 /* 1MB SmartMedia */
+#define SSFDC2MB 0x02 /* 2MB SmartMedia */
+#define SSFDC4MB 0x03 /* 4MB SmartMedia */
+#define SSFDC8MB 0x04 /* 8MB SmartMedia */
+#define SSFDC16MB 0x05 /* 16MB SmartMedia */
+#define SSFDC32MB 0x06 /* 32MB SmartMedia */
+#define SSFDC64MB 0x07 /* 64MB SmartMedia */
+#define SSFDC128MB 0x08 /*128MB SmartMedia */
#define SSFDC256MB 0x09
#define SSFDC512MB 0x0A
#define SSFDC1GB 0x0B
@@ -163,8 +168,7 @@
/***************************************************************************
Struct Definition
***************************************************************************/
-struct SSFDCTYPE
-{
+struct SSFDCTYPE {
BYTE Model;
BYTE Attribute;
BYTE MaxZones;
@@ -183,8 +187,7 @@
WORD MaxLogBlocks;
} *SSFDCTYPE_T;
-struct ADDRESS
-{
+struct ADDRESS {
BYTE Zone; /* Zone Number */
BYTE Sector; /* Sector(512byte) Number on Block */
WORD PhyBlock; /* Physical Block Number on Zone */
@@ -199,92 +202,112 @@
WORD LogBlock; /* Logical Block Number of Zone */
} *ADDRESS_T;
-struct CIS_AREA
-{
+struct CIS_AREA {
BYTE Sector; /* Sector(512byte) Number on Block */
WORD PhyBlock; /* Physical Block Number on Zone 0 */
};
-//----- SMILMain.c ---------------------------------------------------
+extern BYTE IsSSFDCCompliance;
+extern BYTE IsXDCompliance;
+
+extern DWORD ErrXDCode;
+extern DWORD ErrCode;
+extern WORD ReadBlock;
+extern WORD WriteBlock;
+extern DWORD MediaChange;
+
+extern struct SSFDCTYPE Ssfdc;
+extern struct ADDRESS Media;
+extern struct CIS_AREA CisArea;
+
+/*
+ * SMILMain.c
+ */
/******************************************/
-int Init_D_SmartMedia (void);
-int Pwoff_D_SmartMedia (void);
-int Check_D_SmartMedia (void);
-int Check_D_Parameter (struct us_data *,WORD *,BYTE *,BYTE *);
-int Media_D_ReadSector (struct us_data *,DWORD,WORD,BYTE *);
-int Media_D_WriteSector (struct us_data *,DWORD,WORD,BYTE *);
-int Media_D_CopySector (struct us_data *,DWORD,WORD,BYTE *);
-int Media_D_EraseBlock (struct us_data *,DWORD,WORD);
-int Media_D_EraseAll (struct us_data *);
+int Init_D_SmartMedia(void);
+int Pwoff_D_SmartMedia(void);
+int Check_D_SmartMedia(void);
+int Check_D_Parameter(struct us_data *, WORD *, BYTE *, BYTE *);
+int Media_D_ReadSector(struct us_data *, DWORD, WORD, BYTE *);
+int Media_D_WriteSector(struct us_data *, DWORD, WORD, BYTE *);
+int Media_D_CopySector(struct us_data *, DWORD, WORD, BYTE *);
+int Media_D_EraseBlock(struct us_data *, DWORD, WORD);
+int Media_D_EraseAll(struct us_data *);
/******************************************/
-int Media_D_OneSectWriteStart (struct us_data *,DWORD,BYTE *);
-int Media_D_OneSectWriteNext (struct us_data *,BYTE *);
-int Media_D_OneSectWriteFlush (struct us_data *);
+int Media_D_OneSectWriteStart(struct us_data *, DWORD, BYTE *);
+int Media_D_OneSectWriteNext(struct us_data *, BYTE *);
+int Media_D_OneSectWriteFlush(struct us_data *);
/******************************************/
-void SM_EnableLED (struct us_data *,BOOLEAN);
-void Led_D_TernOn (void);
-void Led_D_TernOff (void);
+extern int SM_FreeMem(void); /* ENE SM function */
+void SM_EnableLED(struct us_data *, BOOLEAN);
+void Led_D_TernOn(void);
+void Led_D_TernOff(void);
-int Media_D_EraseAllRedtData (DWORD Index, BOOLEAN CheckBlock);
-//DWORD Media_D_GetMediaInfo (struct us_data * fdoExt, PIOCTL_MEDIA_INFO_IN pParamIn, PIOCTL_MEDIA_INFO_OUT pParamOut);
+int Media_D_EraseAllRedtData(DWORD Index, BOOLEAN CheckBlock);
+/*DWORD Media_D_GetMediaInfo(struct us_data * fdoExt,
+ PIOCTL_MEDIA_INFO_IN pParamIn, PIOCTL_MEDIA_INFO_OUT pParamOut); */
-//----- SMILSub.c ----------------------------------------------------
+/*
+ * SMILSub.c
+ */
/******************************************/
-int Check_D_DataBlank (BYTE *);
-int Check_D_FailBlock (BYTE *);
-int Check_D_DataStatus (BYTE *);
-int Load_D_LogBlockAddr (BYTE *);
-void Clr_D_RedundantData (BYTE *);
-void Set_D_LogBlockAddr (BYTE *);
-void Set_D_FailBlock (BYTE *);
-void Set_D_DataStaus (BYTE *);
+int Check_D_DataBlank(BYTE *);
+int Check_D_FailBlock(BYTE *);
+int Check_D_DataStatus(BYTE *);
+int Load_D_LogBlockAddr(BYTE *);
+void Clr_D_RedundantData(BYTE *);
+void Set_D_LogBlockAddr(BYTE *);
+void Set_D_FailBlock(BYTE *);
+void Set_D_DataStaus(BYTE *);
/******************************************/
-void Ssfdc_D_Reset (struct us_data *);
-int Ssfdc_D_ReadCisSect (struct us_data *, BYTE *,BYTE *);
-void Ssfdc_D_WriteRedtMode (void);
-void Ssfdc_D_ReadID (BYTE *, BYTE);
-int Ssfdc_D_ReadSect (struct us_data *, BYTE *,BYTE *);
-int Ssfdc_D_ReadBlock (struct us_data *, WORD, BYTE *,BYTE *);
-int Ssfdc_D_WriteSect (struct us_data *, BYTE *,BYTE *);
-int Ssfdc_D_WriteBlock (struct us_data *, WORD, BYTE *,BYTE *);
-int Ssfdc_D_CopyBlock (struct us_data *, WORD, BYTE *,BYTE *);
-int Ssfdc_D_WriteSectForCopy (struct us_data *, BYTE *,BYTE *);
-int Ssfdc_D_EraseBlock (struct us_data *);
-int Ssfdc_D_ReadRedtData (struct us_data *, BYTE *);
-int Ssfdc_D_WriteRedtData (struct us_data *, BYTE *);
-int Ssfdc_D_CheckStatus (void);
-int Set_D_SsfdcModel (BYTE);
-void Cnt_D_Reset (void);
-int Cnt_D_PowerOn (void);
-void Cnt_D_PowerOff (void);
-void Cnt_D_LedOn (void);
-void Cnt_D_LedOff (void);
-int Check_D_CntPower (void);
-int Check_D_CardExist (void);
-int Check_D_CardStsChg (void);
-int Check_D_SsfdcWP (void);
-int SM_ReadBlock (struct us_data *, BYTE *,BYTE *);
+void Ssfdc_D_Reset(struct us_data *);
+int Ssfdc_D_ReadCisSect(struct us_data *, BYTE *, BYTE *);
+void Ssfdc_D_WriteRedtMode(void);
+void Ssfdc_D_ReadID(BYTE *, BYTE);
+int Ssfdc_D_ReadSect(struct us_data *, BYTE *, BYTE *);
+int Ssfdc_D_ReadBlock(struct us_data *, WORD, BYTE *, BYTE *);
+int Ssfdc_D_WriteSect(struct us_data *, BYTE *, BYTE *);
+int Ssfdc_D_WriteBlock(struct us_data *, WORD, BYTE *, BYTE *);
+int Ssfdc_D_CopyBlock(struct us_data *, WORD, BYTE *, BYTE *);
+int Ssfdc_D_WriteSectForCopy(struct us_data *, BYTE *, BYTE *);
+int Ssfdc_D_EraseBlock(struct us_data *);
+int Ssfdc_D_ReadRedtData(struct us_data *, BYTE *);
+int Ssfdc_D_WriteRedtData(struct us_data *, BYTE *);
+int Ssfdc_D_CheckStatus(void);
+int Set_D_SsfdcModel(BYTE);
+void Cnt_D_Reset(void);
+int Cnt_D_PowerOn(void);
+void Cnt_D_PowerOff(void);
+void Cnt_D_LedOn(void);
+void Cnt_D_LedOff(void);
+int Check_D_CntPower(void);
+int Check_D_CardExist(void);
+int Check_D_CardStsChg(void);
+int Check_D_SsfdcWP(void);
+int SM_ReadBlock(struct us_data *, BYTE *, BYTE *);
-int Ssfdc_D_ReadSect_DMA (struct us_data *, BYTE *,BYTE *);
-int Ssfdc_D_ReadSect_PIO (struct us_data *, BYTE *,BYTE *);
-int Ssfdc_D_WriteSect_DMA (struct us_data *, BYTE *,BYTE *);
-int Ssfdc_D_WriteSect_PIO (struct us_data *, BYTE *,BYTE *);
+int Ssfdc_D_ReadSect_DMA(struct us_data *, BYTE *, BYTE *);
+int Ssfdc_D_ReadSect_PIO(struct us_data *, BYTE *, BYTE *);
+int Ssfdc_D_WriteSect_DMA(struct us_data *, BYTE *, BYTE *);
+int Ssfdc_D_WriteSect_PIO(struct us_data *, BYTE *, BYTE *);
/******************************************/
-int Check_D_ReadError (BYTE *);
-int Check_D_Correct (BYTE *,BYTE *);
-int Check_D_CISdata (BYTE *,BYTE *);
-void Set_D_RightECC (BYTE *);
+int Check_D_ReadError(BYTE *);
+int Check_D_Correct(BYTE *, BYTE *);
+int Check_D_CISdata(BYTE *, BYTE *);
+void Set_D_RightECC(BYTE *);
-//----- SMILECC.c ----------------------------------------------------
-void calculate_ecc (BYTE *, BYTE *, BYTE *, BYTE *, BYTE *);
-BYTE correct_data (BYTE *, BYTE *, BYTE, BYTE, BYTE);
-int _Correct_D_SwECC (BYTE *,BYTE *,BYTE *);
-void _Calculate_D_SwECC (BYTE *,BYTE *);
+/*
+ * SMILECC.c
+ */
+void calculate_ecc(BYTE *, BYTE *, BYTE *, BYTE *, BYTE *);
+BYTE correct_data(BYTE *, BYTE *, BYTE, BYTE, BYTE);
+int _Correct_D_SwECC(BYTE *, BYTE *, BYTE *);
+void _Calculate_D_SwECC(BYTE *, BYTE *);
-void SM_Init (void);
+void SM_Init(void);
-#endif // already included
+#endif /* already included */
diff --git a/drivers/staging/keucr/smilecc.c b/drivers/staging/keucr/smilecc.c
index 5659dea..3085f1d 100644
--- a/drivers/staging/keucr/smilecc.c
+++ b/drivers/staging/keucr/smilecc.c
@@ -1,39 +1,42 @@
#include "usb.h"
#include "scsiglue.h"
#include "transport.h"
-//#include "stdlib.h"
-//#include "EUCR6SK.h"
+/* #include "stdlib.h" */
+/* #include "EUCR6SK.h" */
#include "smcommon.h"
#include "smil.h"
-//#include <stdio.h>
-//#include <stdlib.h>
-//#include <string.h>
-//#include <dos.h>
-//
-//#include "EMCRIOS.h"
+/* #include <stdio.h> */
+/* #include <stdlib.h> */
+/* #include <string.h> */
+/* #include <dos.h> */
+/* #include "EMCRIOS.h" */
-// CP0-CP5 code table
+/* CP0-CP5 code table */
static BYTE ecctable[256] = {
-0x00,0x55,0x56,0x03,0x59,0x0C,0x0F,0x5A,0x5A,0x0F,0x0C,0x59,0x03,0x56,0x55,0x00,
-0x65,0x30,0x33,0x66,0x3C,0x69,0x6A,0x3F,0x3F,0x6A,0x69,0x3C,0x66,0x33,0x30,0x65,
-0x66,0x33,0x30,0x65,0x3F,0x6A,0x69,0x3C,0x3C,0x69,0x6A,0x3F,0x65,0x30,0x33,0x66,
-0x03,0x56,0x55,0x00,0x5A,0x0F,0x0C,0x59,0x59,0x0C,0x0F,0x5A,0x00,0x55,0x56,0x03,
-0x69,0x3C,0x3F,0x6A,0x30,0x65,0x66,0x33,0x33,0x66,0x65,0x30,0x6A,0x3F,0x3C,0x69,
-0x0C,0x59,0x5A,0x0F,0x55,0x00,0x03,0x56,0x56,0x03,0x00,0x55,0x0F,0x5A,0x59,0x0C,
-0x0F,0x5A,0x59,0x0C,0x56,0x03,0x00,0x55,0x55,0x00,0x03,0x56,0x0C,0x59,0x5A,0x0F,
-0x6A,0x3F,0x3C,0x69,0x33,0x66,0x65,0x30,0x30,0x65,0x66,0x33,0x69,0x3C,0x3F,0x6A,
-0x6A,0x3F,0x3C,0x69,0x33,0x66,0x65,0x30,0x30,0x65,0x66,0x33,0x69,0x3C,0x3F,0x6A,
-0x0F,0x5A,0x59,0x0C,0x56,0x03,0x00,0x55,0x55,0x00,0x03,0x56,0x0C,0x59,0x5A,0x0F,
-0x0C,0x59,0x5A,0x0F,0x55,0x00,0x03,0x56,0x56,0x03,0x00,0x55,0x0F,0x5A,0x59,0x0C,
-0x69,0x3C,0x3F,0x6A,0x30,0x65,0x66,0x33,0x33,0x66,0x65,0x30,0x6A,0x3F,0x3C,0x69,
-0x03,0x56,0x55,0x00,0x5A,0x0F,0x0C,0x59,0x59,0x0C,0x0F,0x5A,0x00,0x55,0x56,0x03,
-0x66,0x33,0x30,0x65,0x3F,0x6A,0x69,0x3C,0x3C,0x69,0x6A,0x3F,0x65,0x30,0x33,0x66,
-0x65,0x30,0x33,0x66,0x3C,0x69,0x6A,0x3F,0x3F,0x6A,0x69,0x3C,0x66,0x33,0x30,0x65,
-0x00,0x55,0x56,0x03,0x59,0x0C,0x0F,0x5A,0x5A,0x0F,0x0C,0x59,0x03,0x56,0x55,0x00
+0x00, 0x55, 0x56, 0x03, 0x59, 0x0C, 0x0F, 0x5A, 0x5A, 0x0F, 0x0C, 0x59, 0x03,
+0x56, 0x55, 0x00, 0x65, 0x30, 0x33, 0x66, 0x3C, 0x69, 0x6A, 0x3F, 0x3F, 0x6A,
+0x69, 0x3C, 0x66, 0x33, 0x30, 0x65, 0x66, 0x33, 0x30, 0x65, 0x3F, 0x6A, 0x69,
+0x3C, 0x3C, 0x69, 0x6A, 0x3F, 0x65, 0x30, 0x33, 0x66, 0x03, 0x56, 0x55, 0x00,
+0x5A, 0x0F, 0x0C, 0x59, 0x59, 0x0C, 0x0F, 0x5A, 0x00, 0x55, 0x56, 0x03, 0x69,
+0x3C, 0x3F, 0x6A, 0x30, 0x65, 0x66, 0x33, 0x33, 0x66, 0x65, 0x30, 0x6A, 0x3F,
+0x3C, 0x69, 0x0C, 0x59, 0x5A, 0x0F, 0x55, 0x00, 0x03, 0x56, 0x56, 0x03, 0x00,
+0x55, 0x0F, 0x5A, 0x59, 0x0C, 0x0F, 0x5A, 0x59, 0x0C, 0x56, 0x03, 0x00, 0x55,
+0x55, 0x00, 0x03, 0x56, 0x0C, 0x59, 0x5A, 0x0F, 0x6A, 0x3F, 0x3C, 0x69, 0x33,
+0x66, 0x65, 0x30, 0x30, 0x65, 0x66, 0x33, 0x69, 0x3C, 0x3F, 0x6A, 0x6A, 0x3F,
+0x3C, 0x69, 0x33, 0x66, 0x65, 0x30, 0x30, 0x65, 0x66, 0x33, 0x69, 0x3C, 0x3F,
+0x6A, 0x0F, 0x5A, 0x59, 0x0C, 0x56, 0x03, 0x00, 0x55, 0x55, 0x00, 0x03, 0x56,
+0x0C, 0x59, 0x5A, 0x0F, 0x0C, 0x59, 0x5A, 0x0F, 0x55, 0x00, 0x03, 0x56, 0x56,
+0x03, 0x00, 0x55, 0x0F, 0x5A, 0x59, 0x0C, 0x69, 0x3C, 0x3F, 0x6A, 0x30, 0x65,
+0x66, 0x33, 0x33, 0x66, 0x65, 0x30, 0x6A, 0x3F, 0x3C, 0x69, 0x03, 0x56, 0x55,
+0x00, 0x5A, 0x0F, 0x0C, 0x59, 0x59, 0x0C, 0x0F, 0x5A, 0x00, 0x55, 0x56, 0x03,
+0x66, 0x33, 0x30, 0x65, 0x3F, 0x6A, 0x69, 0x3C, 0x3C, 0x69, 0x6A, 0x3F, 0x65,
+0x30, 0x33, 0x66, 0x65, 0x30, 0x33, 0x66, 0x3C, 0x69, 0x6A, 0x3F, 0x3F, 0x6A,
+0x69, 0x3C, 0x66, 0x33, 0x30, 0x65, 0x00, 0x55, 0x56, 0x03, 0x59, 0x0C, 0x0F,
+0x5A, 0x5A, 0x0F, 0x0C, 0x59, 0x03, 0x56, 0x55, 0x00
};
-static void trans_result (BYTE, BYTE, BYTE *, BYTE *);
+static void trans_result(BYTE, BYTE, BYTE *, BYTE *);
#define BIT7 0x80
#define BIT6 0x40
@@ -48,139 +51,144 @@
#define MASK_CPS 0x3f
#define CORRECTABLE 0x00555554L
-static void trans_result(reg2,reg3,ecc1,ecc2)
-BYTE reg2; // LP14,LP12,LP10,...
-BYTE reg3; // LP15,LP13,LP11,...
-BYTE *ecc1; // LP15,LP14,LP13,...
-BYTE *ecc2; // LP07,LP06,LP05,...
+/*
+ * reg2; * LP14,LP12,LP10,...
+ * reg3; * LP15,LP13,LP11,...
+ * *ecc1; * LP15,LP14,LP13,...
+ * *ecc2; * LP07,LP06,LP05,...
+ */
+static void trans_result(BYTE reg2, BYTE reg3, BYTE *ecc1, BYTE *ecc2)
{
- BYTE a; // Working for reg2,reg3
- BYTE b; // Working for ecc1,ecc2
- BYTE i; // For counting
+ BYTE a; /* Working for reg2,reg3 */
+ BYTE b; /* Working for ecc1,ecc2 */
+ BYTE i; /* For counting */
- a=BIT7; b=BIT7; // 80h=10000000b
- *ecc1=*ecc2=0; // Clear ecc1,ecc2
- for(i=0; i<4; ++i) {
- if ((reg3&a)!=0)
- *ecc1|=b; // LP15,13,11,9 -> ecc1
- b=b>>1; // Right shift
- if ((reg2&a)!=0)
- *ecc1|=b; // LP14,12,10,8 -> ecc1
- b=b>>1; // Right shift
- a=a>>1; // Right shift
- }
+ a = BIT7; b = BIT7; /* 80h=10000000b */
+ *ecc1 = *ecc2 = 0; /* Clear ecc1,ecc2 */
+ for (i = 0; i < 4; ++i) {
+ if ((reg3&a) != 0)
+ *ecc1 |= b; /* LP15,13,11,9 -> ecc1 */
+ b = b>>1; /* Right shift */
+ if ((reg2&a) != 0)
+ *ecc1 |= b; /* LP14,12,10,8 -> ecc1 */
+ b = b>>1; /* Right shift */
+ a = a>>1; /* Right shift */
+ }
- b=BIT7; // 80h=10000000b
- for(i=0; i<4; ++i) {
- if ((reg3&a)!=0)
- *ecc2|=b; // LP7,5,3,1 -> ecc2
- b=b>>1; // Right shift
- if ((reg2&a)!=0)
- *ecc2|=b; // LP6,4,2,0 -> ecc2
- b=b>>1; // Right shift
- a=a>>1; // Right shift
- }
+ b = BIT7; /* 80h=10000000b */
+ for (i = 0; i < 4; ++i) {
+ if ((reg3&a) != 0)
+ *ecc2 |= b; /* LP7,5,3,1 -> ecc2 */
+ b = b>>1; /* Right shift */
+ if ((reg2&a) != 0)
+ *ecc2 |= b; /* LP6,4,2,0 -> ecc2 */
+ b = b>>1; /* Right shift */
+ a = a>>1; /* Right shift */
+ }
}
-//static void calculate_ecc(table,data,ecc1,ecc2,ecc3)
-void calculate_ecc(table,data,ecc1,ecc2,ecc3)
-BYTE *table; // CP0-CP5 code table
-BYTE *data; // DATA
-BYTE *ecc1; // LP15,LP14,LP13,...
-BYTE *ecc2; // LP07,LP06,LP05,...
-BYTE *ecc3; // CP5,CP4,CP3,...,"1","1"
+/*static void calculate_ecc(table,data,ecc1,ecc2,ecc3) */
+/*
+ * *table; * CP0-CP5 code table
+ * *data; * DATA
+ * *ecc1; * LP15,LP14,LP13,...
+ * *ecc2; * LP07,LP06,LP05,...
+ * *ecc3; * CP5,CP4,CP3,...,"1","1"
+ */
+void calculate_ecc(BYTE *table, BYTE *data, BYTE *ecc1, BYTE *ecc2, BYTE *ecc3)
{
- DWORD i; // For counting
- BYTE a; // Working for table
- BYTE reg1; // D-all,CP5,CP4,CP3,...
- BYTE reg2; // LP14,LP12,L10,...
- BYTE reg3; // LP15,LP13,L11,...
+ DWORD i; /* For counting */
+ BYTE a; /* Working for table */
+ BYTE reg1; /* D-all,CP5,CP4,CP3,... */
+ BYTE reg2; /* LP14,LP12,L10,... */
+ BYTE reg3; /* LP15,LP13,L11,... */
- reg1=reg2=reg3=0; // Clear parameter
- for(i=0; i<256; ++i) {
- a=table[data[i]]; // Get CP0-CP5 code from table
- reg1^=(a&MASK_CPS); // XOR with a
- if ((a&BIT6)!=0)
- { // If D_all(all bit XOR) = 1
- reg3^=(BYTE)i; // XOR with counter
- reg2^=~((BYTE)i); // XOR with inv. of counter
- }
- }
+ reg1 = reg2 = reg3 = 0; /* Clear parameter */
+ for (i = 0; i < 256; ++i) {
+ a = table[data[i]]; /* Get CP0-CP5 code from table */
+ reg1 ^= (a&MASK_CPS); /* XOR with a */
+ if ((a&BIT6) != 0) { /* If D_all(all bit XOR) = 1 */
+ reg3 ^= (BYTE)i; /* XOR with counter */
+ reg2 ^= ~((BYTE)i); /* XOR with inv. of counter */
+ }
+ }
- // Trans LP14,12,10,... & LP15,13,11,... -> LP15,14,13,... & LP7,6,5,..
- trans_result(reg2,reg3,ecc1,ecc2);
- *ecc1=~(*ecc1); *ecc2=~(*ecc2); // Inv. ecc2 & ecc3
- *ecc3=((~reg1)<<2)|BIT1BIT0; // Make TEL format
+ /* Trans LP14,12,10,... & LP15,13,11,... ->
+ LP15,14,13,... & LP7,6,5,.. */
+ trans_result(reg2, reg3, ecc1, ecc2);
+ *ecc1 = ~(*ecc1); *ecc2 = ~(*ecc2); /* Inv. ecc2 & ecc3 */
+ *ecc3 = ((~reg1)<<2)|BIT1BIT0; /* Make TEL format */
}
-BYTE correct_data(data,eccdata,ecc1,ecc2,ecc3)
-BYTE *data; // DATA
-BYTE *eccdata; // ECC DATA
-BYTE ecc1; // LP15,LP14,LP13,...
-BYTE ecc2; // LP07,LP06,LP05,...
-BYTE ecc3; // CP5,CP4,CP3,...,"1","1"
+/*
+ * *data; * DATA
+ * *eccdata; * ECC DATA
+ * ecc1; * LP15,LP14,LP13,...
+ * ecc2; * LP07,LP06,LP05,...
+ * ecc3; * CP5,CP4,CP3,...,"1","1"
+ */
+BYTE correct_data(BYTE *data, BYTE *eccdata, BYTE ecc1, BYTE ecc2, BYTE ecc3)
{
- DWORD l; // Working to check d
- DWORD d; // Result of comparison
- DWORD i; // For counting
- BYTE d1,d2,d3; // Result of comparison
- BYTE a; // Working for add
- BYTE add; // Byte address of cor. DATA
- BYTE b; // Working for bit
- BYTE bit; // Bit address of cor. DATA
+ DWORD l; /* Working to check d */
+ DWORD d; /* Result of comparison */
+ DWORD i; /* For counting */
+ BYTE d1, d2, d3; /* Result of comparison */
+ BYTE a; /* Working for add */
+ BYTE add; /* Byte address of cor. DATA */
+ BYTE b; /* Working for bit */
+ BYTE bit; /* Bit address of cor. DATA */
- d1=ecc1^eccdata[1]; d2=ecc2^eccdata[0]; // Compare LP's
- d3=ecc3^eccdata[2]; // Comapre CP's
- d=((DWORD)d1<<16) // Result of comparison
- +((DWORD)d2<<8)
- +(DWORD)d3;
+ d1 = ecc1^eccdata[1]; d2 = ecc2^eccdata[0]; /* Compare LP's */
+ d3 = ecc3^eccdata[2]; /* Comapre CP's */
+ d = ((DWORD)d1<<16) /* Result of comparison */
+ +((DWORD)d2<<8)
+ +(DWORD)d3;
- if (d==0) return(0); // If No error, return
+ if (d == 0)
+ return 0; /* If No error, return */
- if (((d^(d>>1))&CORRECTABLE)==CORRECTABLE)
- { // If correctable
- l=BIT23;
- add=0; // Clear parameter
- a=BIT7;
+ if (((d^(d>>1))&CORRECTABLE) == CORRECTABLE) { /* If correctable */
+ l = BIT23;
+ add = 0; /* Clear parameter */
+ a = BIT7;
- for(i=0; i<8; ++i) { // Checking 8 bit
- if ((d&l)!=0) add|=a; // Make byte address from LP's
- l>>=2; a>>=1; // Right Shift
- }
+ for (i = 0; i < 8; ++i) { /* Checking 8 bit */
+ if ((d&l) != 0)
+ add |= a; /* Make byte address from LP's */
+ l >>= 2; a >>= 1; /* Right Shift */
+ }
- bit=0; // Clear parameter
- b=BIT2;
- for(i=0; i<3; ++i) { // Checking 3 bit
- if ((d&l)!=0) bit|=b; // Make bit address from CP's
- l>>=2; b>>=1; // Right shift
- }
+ bit = 0; /* Clear parameter */
+ b = BIT2;
+ for (i = 0; i < 3; ++i) { /* Checking 3 bit */
+ if ((d&l) != 0)
+ bit |= b; /* Make bit address from CP's */
+ l >>= 2; b >>= 1; /* Right shift */
+ }
- b=BIT0;
- data[add]^=(b<<bit); // Put corrected data
- return(1);
- }
+ b = BIT0;
+ data[add] ^= (b<<bit); /* Put corrected data */
+ return 1;
+ }
- i=0; // Clear count
- d&=0x00ffffffL; // Masking
+ i = 0; /* Clear count */
+ d &= 0x00ffffffL; /* Masking */
- while(d) { // If d=0 finish counting
- if (d&BIT0) ++i; // Count number of 1 bit
- d>>=1; // Right shift
- }
+ while (d) { /* If d=0 finish counting */
+ if (d&BIT0)
+ ++i; /* Count number of 1 bit */
+ d >>= 1; /* Right shift */
+ }
- if (i==1)
- { // If ECC error
- eccdata[1]=ecc1; eccdata[0]=ecc2; // Put right ECC code
- eccdata[2]=ecc3;
- return(2);
- }
- return(3); // Uncorrectable error
+ if (i == 1) { /* If ECC error */
+ eccdata[1] = ecc1; eccdata[0] = ecc2; /* Put right ECC code */
+ eccdata[2] = ecc3;
+ return 2;
+ }
+ return 3; /* Uncorrectable error */
}
-int _Correct_D_SwECC(buf,redundant_ecc,calculate_ecc)
-BYTE *buf;
-BYTE *redundant_ecc;
-BYTE *calculate_ecc;
+int _Correct_D_SwECC(BYTE *buf, BYTE *redundant_ecc, BYTE *calculate_ecc)
{
DWORD err;
@@ -195,11 +203,9 @@
return -1;
}
-void _Calculate_D_SwECC(buf,ecc)
-BYTE *buf;
-BYTE *ecc;
+void _Calculate_D_SwECC(BYTE *buf, BYTE *ecc)
{
- calculate_ecc(ecctable,buf,ecc+1,ecc+0,ecc+2);
+ calculate_ecc(ecctable, buf, ecc+1, ecc+0, ecc+2);
}
diff --git a/drivers/staging/keucr/smilmain.c b/drivers/staging/keucr/smilmain.c
index 95c688a..31f7813 100644
--- a/drivers/staging/keucr/smilmain.c
+++ b/drivers/staging/keucr/smilmain.c
@@ -48,31 +48,27 @@
DWORD ErrXDCode;
DWORD ErrCode;
//BYTE SectBuf[SECTSIZE];
-BYTE WorkBuf[SECTSIZE];
-BYTE Redundant[REDTSIZE];
-BYTE WorkRedund[REDTSIZE];
+static BYTE WorkBuf[SECTSIZE];
+static BYTE Redundant[REDTSIZE];
+static BYTE WorkRedund[REDTSIZE];
//WORD Log2Phy[MAX_ZONENUM][MAX_LOGBLOCK];
-WORD *Log2Phy[MAX_ZONENUM]; // 128 x 1000, Log2Phy[MAX_ZONENUM][MAX_LOGBLOCK];
-BYTE Assign[MAX_ZONENUM][MAX_BLOCKNUM/8];
-WORD AssignStart[MAX_ZONENUM];
+static WORD *Log2Phy[MAX_ZONENUM]; // 128 x 1000, Log2Phy[MAX_ZONENUM][MAX_LOGBLOCK];
+static BYTE Assign[MAX_ZONENUM][MAX_BLOCKNUM/8];
+static WORD AssignStart[MAX_ZONENUM];
WORD ReadBlock;
WORD WriteBlock;
DWORD MediaChange;
-DWORD SectCopyMode;
-
-extern struct SSFDCTYPE Ssfdc;
-extern struct ADDRESS Media;
-extern struct CIS_AREA CisArea;
+static DWORD SectCopyMode;
//BIT Control Macro
-BYTE BitData[] = { 0x01,0x02,0x04,0x08,0x10,0x20,0x40,0x80 } ;
+static BYTE BitData[] = { 0x01,0x02,0x04,0x08,0x10,0x20,0x40,0x80 } ;
#define Set_D_Bit(a,b) (a[(BYTE)((b)/8)]|= BitData[(b)%8])
#define Clr_D_Bit(a,b) (a[(BYTE)((b)/8)]&=~BitData[(b)%8])
#define Chk_D_Bit(a,b) (a[(BYTE)((b)/8)] & BitData[(b)%8])
//extern PBYTE SMHostAddr;
-extern BYTE IsSSFDCCompliance;
-extern BYTE IsXDCompliance;
+BYTE IsSSFDCCompliance;
+BYTE IsXDCompliance;
//
@@ -102,12 +98,12 @@
{
int i;
- printk("SM_FreeMem start\n");
+ pr_info("SM_FreeMem start\n");
for (i=0; i<MAX_ZONENUM; i++)
{
if (Log2Phy[i]!=NULL)
{
- printk("Free Zone = %x, Addr = %p\n", i, Log2Phy[i]);
+ pr_info("Free Zone = %x, Addr = %p\n", i, Log2Phy[i]);
kfree(Log2Phy[i]);
Log2Phy[i] = NULL;
}
@@ -198,7 +194,7 @@
//SSFDCTYPE_T aa = (SSFDCTYPE_T ) &Ssfdc;
//ADDRESS_T bb = (ADDRESS_T) &Media;
- //printk("Media_D_CopySector !!!\n");
+ /* pr_info("Media_D_CopySector !!!\n"); */
if (Conv_D_MediaAddr(us, start))
return(ErrCode);
@@ -256,13 +252,13 @@
if (Media.PhyBlock==NO_ASSIGN)
{
Media.PhyBlock=WriteBlock;
- return(SUCCESS);
+ return(SMSUCCESS);
}
Clr_D_Bit(Assign[Media.Zone],Media.PhyBlock);
Media.PhyBlock=WriteBlock;
- return(SUCCESS);
+ return(SMSUCCESS);
}
/*
//----- Media_D_WriteSector() ------------------------------------------
@@ -572,7 +568,7 @@
// default: *c= 0; *h= 0; *s= 0; ErrCode = ERR_NoSmartMedia; return(ERROR);
// }
//
-// return(SUCCESS);
+// return(SMSUCCESS);
//}
//
////Power Control & Media Exist Check Subroutine
@@ -599,7 +595,7 @@
// MediaChange = ERROR;
// //usleep(56*1024);
// if ((!Check_D_CntPower())&&(!MediaChange)) // ¦³ power & Media ¨S³Q change, «h return success
-// return(SUCCESS);
+// return(SMSUCCESS);
// //usleep(56*1024);
//
// if (Check_D_CardExist()) // Check if card is not exist, return err
@@ -618,7 +614,7 @@
// //usleep(56*1024);
// Ssfdc_D_Reset(fdoExt);
// //usleep(56*1024);
-// return(SUCCESS);
+// return(SMSUCCESS);
//}
//
////-----Check_D_MediaExist() --------------------------------------------
@@ -630,7 +626,7 @@
// if (!Check_D_CardExist())
// {
// if (!MediaChange)
-// return(SUCCESS);
+// return(SMSUCCESS);
//
// ErrCode = ERR_ChangedMedia;
// return(ERROR);
@@ -650,19 +646,19 @@
// return(ERROR);
// }
//
-// return(SUCCESS);
+// return(SMSUCCESS);
//}
*/
//SmartMedia Physical Format Test Subroutine
//----- Check_D_MediaFmt() ---------------------------------------------
int Check_D_MediaFmt(struct us_data *us)
{
- printk("Check_D_MediaFmt\n");
+ pr_info("Check_D_MediaFmt\n");
//ULONG i,j, result=FALSE, zone,block;
//usleep(56*1024);
if (!MediaChange)
- return(SUCCESS);
+ return(SMSUCCESS);
MediaChange = ERROR;
SectCopyMode = COMPLETED;
@@ -682,8 +678,8 @@
}
- MediaChange = SUCCESS;
- return(SUCCESS);
+ MediaChange = SMSUCCESS;
+ return(SMSUCCESS);
}
/*
////----- Check_D_BlockIsFull() ----------------------------------
@@ -735,7 +731,7 @@
// return(ERROR);
// }
//
-// return(SUCCESS);
+// return(SMSUCCESS);
//}
*/
//SmartMedia Physical Address Control Subroutine
@@ -767,7 +763,7 @@
Clr_D_RedundantData(Redundant);
Set_D_LogBlockAddr(Redundant);
Media.PhyBlock = Log2Phy[Media.Zone][Media.LogBlock];
- return(SUCCESS);
+ return(SMSUCCESS);
}
ErrCode = ERR_OutOfLBA;
@@ -782,7 +778,7 @@
//ADDRESS_T bb = (ADDRESS_T) &Media;
if (++Media.Sector<Ssfdc.MaxSectors)
- return(SUCCESS);
+ return(SMSUCCESS);
if (Log2Phy[Media.Zone]==NULL)
{
@@ -801,7 +797,7 @@
Clr_D_RedundantData(Redundant);
Set_D_LogBlockAddr(Redundant);
Media.PhyBlock=Log2Phy[Media.Zone][Media.LogBlock];
- return(SUCCESS);
+ return(SMSUCCESS);
}
Media.LogBlock=0;
@@ -822,7 +818,7 @@
Clr_D_RedundantData(Redundant);
Set_D_LogBlockAddr(Redundant);
Media.PhyBlock=Log2Phy[Media.Zone][Media.LogBlock];
- return(SUCCESS);
+ return(SMSUCCESS);
}
Media.Zone=0;
@@ -838,7 +834,7 @@
ADDRESS_T bb = (ADDRESS_T) &Media;
if (!Media.Sector)
- return(SUCCESS);
+ return(SMSUCCESS);
return(ERROR);
}
@@ -852,7 +848,7 @@
if (Media.Sector<(Ssfdc.MaxSectors-1))
return(ERROR);
- return(SUCCESS);
+ return(SMSUCCESS);
}
*/
//SmartMedia Read/Write Subroutine with Retry
@@ -862,7 +858,7 @@
DWORD err, retry;
if (!Read_D_PhyOneSect(us, count, buf))
- return(SUCCESS);
+ return(SMSUCCESS);
if (ErrCode==ERR_HwError)
return(ERROR);
if (ErrCode==ERR_DataStatus)
@@ -872,7 +868,7 @@
if (Ssfdc.Attribute &MWP)
{
if (ErrCode==ERR_CorReadErr)
- return(SUCCESS);
+ return(SMSUCCESS);
return(ERROR);
}
@@ -888,13 +884,13 @@
ErrCode = err;
if (ErrCode==ERR_CorReadErr)
- return(SUCCESS);
+ return(SMSUCCESS);
return(ERROR);
}
MediaChange = ERROR;
#else
- if (ErrCode==ERR_CorReadErr) return(SUCCESS);
+ if (ErrCode==ERR_CorReadErr) return(SMSUCCESS);
#endif
return(ERROR);
@@ -908,7 +904,7 @@
ADDRESS_T bb = (ADDRESS_T) &Media;
if (!Write_D_PhyOneSect(fdoExt, count, buf))
- return(SUCCESS);
+ return(SMSUCCESS);
if (ErrCode==ERR_HwError)
return(ERROR);
@@ -922,7 +918,7 @@
}
if (!Write_D_PhyOneSect(fdoExt, count, buf))
- return(SUCCESS);
+ return(SMSUCCESS);
if (ErrCode==ERR_HwError)
return(ERROR);
}
@@ -944,7 +940,7 @@
for(retry=0; retry<2; retry++)
{
if (!Copy_D_BlockHead(fdoExt))
- return(SUCCESS);
+ return(SMSUCCESS);
if (ErrCode==ERR_HwError)
return(ERROR);
}
@@ -959,7 +955,7 @@
DWORD retry;
if (!Copy_D_BlockTail(fdoExt))
- return(SUCCESS);
+ return(SMSUCCESS);
if (ErrCode==ERR_HwError)
return(ERROR);
@@ -973,7 +969,7 @@
}
if (!Copy_D_BlockTail(fdoExt))
- return(SUCCESS);
+ return(SMSUCCESS);
if (ErrCode==ERR_HwError)
return(ERROR);
}
@@ -995,7 +991,7 @@
// ADDRESS_T bb = (ADDRESS_T) &Media;
//
// if (Media.PhyBlock==NO_ASSIGN)
-// return(SUCCESS);
+// return(SMSUCCESS);
//
// if (Log2Phy[Media.Zone]==NULL)
// {
@@ -1023,7 +1019,7 @@
//
// Clr_D_Bit(Assign[Media.Zone],Media.PhyBlock);
// Media.PhyBlock=NO_ASSIGN;
-// return(SUCCESS);
+// return(SMSUCCESS);
//}
//
////SmartMedia Erase Subroutine
@@ -1076,7 +1072,7 @@
// }
//
// }
-// return(SUCCESS);
+// return(SMSUCCESS);
//}
*/
//SmartMedia Physical Sector Data Copy Subroutine
@@ -1116,7 +1112,7 @@
Media.PhyBlock=WriteBlock;
Media.Sector=sect;
- return(SUCCESS);
+ return(SMSUCCESS);
}
/*
//----- Copy_D_BlockHead() ---------------------------------------------
@@ -1149,7 +1145,7 @@
Media.PhyBlock=WriteBlock;
Media.Sector=sect;
- return(SUCCESS);
+ return(SMSUCCESS);
}
//----- Copy_D_BlockTail() ---------------------------------------------
@@ -1178,7 +1174,7 @@
Media.PhyBlock=WriteBlock;
Media.Sector=sect;
- return(SUCCESS);
+ return(SMSUCCESS);
}
//----- Reassign_D_BlockHead() -----------------------------------------
@@ -1226,7 +1222,7 @@
ReadBlock=block;
Media.Sector=sect;
Media.PhyBlock=WriteBlock;
- return(SUCCESS);
+ return(SMSUCCESS);
}
*/
//SmartMedia Physical Block Assign/Release Subroutine
@@ -1246,7 +1242,7 @@
Media.PhyBlock=WriteBlock;
SectCopyMode=REQ_ERASE;
//ErrXDCode = NO_ERROR;
- return(SUCCESS);
+ return(SMSUCCESS);
}
}
@@ -1259,7 +1255,7 @@
Media.PhyBlock=WriteBlock;
SectCopyMode=REQ_ERASE;
//ErrXDCode = NO_ERROR;
- return(SUCCESS);
+ return(SMSUCCESS);
}
}
@@ -1282,7 +1278,7 @@
SectCopyMode=COMPLETED;
if (mode==COMPLETED)
- return(SUCCESS);
+ return(SMSUCCESS);
Log2Phy[Media.Zone][Media.LogBlock]=WriteBlock;
Media.PhyBlock=ReadBlock;
@@ -1290,7 +1286,7 @@
if (Media.PhyBlock==NO_ASSIGN)
{
Media.PhyBlock=WriteBlock;
- return(SUCCESS);
+ return(SMSUCCESS);
}
if (mode==REQ_ERASE)
@@ -1307,7 +1303,7 @@
return(ERROR);
Media.PhyBlock=WriteBlock;
- return(SUCCESS);
+ return(SMSUCCESS);
}
//----- Release_D_WriteBlock() -----------------------------------------
@@ -1322,7 +1318,7 @@
return(ERROR);
Media.PhyBlock=ReadBlock;
- return(SUCCESS);
+ return(SMSUCCESS);
}
//SmartMedia Physical Sector Data Copy Subroutine
@@ -1334,7 +1330,7 @@
//SSFDCTYPE_T aa = (SSFDCTYPE_T ) &Ssfdc;
//ADDRESS_T bb = (ADDRESS_T) &Media;
- //printk("Copy_D_PhyOneSect --- Secotr = %x\n", Media.Sector);
+ /* pr_info("Copy_D_PhyOneSect --- Secotr = %x\n", Media.Sector); */
if (ReadBlock!=NO_ASSIGN)
{
Media.PhyBlock=ReadBlock;
@@ -1355,9 +1351,9 @@
if (Check_D_DataStatus(WorkRedund))
{ err=ERROR; break; }
if (!Check_D_ReadError(WorkRedund))
- { err=SUCCESS; break; }
+ { err=SMSUCCESS; break; }
if (!Check_D_Correct(WorkBuf,WorkRedund))
- { err=SUCCESS; break; }
+ { err=SMSUCCESS; break; }
err=ERROR;
SectCopyMode=REQ_FAIL;
@@ -1365,7 +1361,7 @@
}
else
{
- err=SUCCESS;
+ err=SMSUCCESS;
for(i=0; i<SECTSIZE; i++)
WorkBuf[i]=DUMMY_DATA;
Clr_D_RedundantData(WorkRedund);
@@ -1386,7 +1382,7 @@
{ ErrCode = ERR_WriteFault; return(ERROR); }
Media.PhyBlock=ReadBlock;
- return(SUCCESS);
+ return(SMSUCCESS);
}
//SmartMedia Physical Sector Read/Write/Erase Subroutine
@@ -1402,7 +1398,7 @@
{
for(i=0; i<SECTSIZE; i++)
*buf++=DUMMY_DATA;
- return(SUCCESS);
+ return(SMSUCCESS);
}
for(retry=0; retry<2; retry++)
@@ -1424,7 +1420,7 @@
{ ErrCode = ERR_DataStatus; return(ERROR); }
if (!Check_D_ReadError(Redundant))
- return(SUCCESS);
+ return(SMSUCCESS);
if (!Check_D_Correct(buf,Redundant))
{ ErrCode = ERR_CorReadErr; return(ERROR); }
@@ -1446,7 +1442,7 @@
if (Ssfdc_D_CheckStatus())
{ ErrCode = ERR_WriteFault; return(ERROR); }
- return(SUCCESS);
+ return(SMSUCCESS);
}
*/
//----- Erase_D_PhyOneBlock() ------------------------------------------
@@ -1460,7 +1456,7 @@
if (Ssfdc_D_CheckStatus())
{ ErrCode = ERR_WriteFault; return(ERROR); }
- return(SUCCESS);
+ return(SMSUCCESS);
}
//SmartMedia Physical Format Check Local Subroutine
@@ -1544,7 +1540,7 @@
// }
// }
- return(SUCCESS);
+ return(SMSUCCESS);
}
//----- Search_D_CIS() -------------------------------------------------
@@ -1600,7 +1596,7 @@
CisArea.PhyBlock=Media.PhyBlock;
CisArea.Sector=Media.Sector;
Ssfdc_D_Reset(us);
- return(SUCCESS);
+ return(SMSUCCESS);
}
Media.Sector++;
@@ -1620,7 +1616,8 @@
if (Log2Phy[Media.Zone]==NULL)
{
Log2Phy[Media.Zone] = kmalloc(MAX_LOGBLOCK*sizeof(WORD), GFP_KERNEL);
- //printk("ExAllocatePool Zone = %x, Addr = %x\n", Media.Zone, Log2Phy[Media.Zone]);
+ /* pr_info("ExAllocatePool Zone = %x, Addr = %x\n",
+ Media.Zone, Log2Phy[Media.Zone]); */
if (Log2Phy[Media.Zone]==NULL)
return(ERROR);
}
@@ -1630,7 +1627,8 @@
//for(Media.Zone=0; Media.Zone<MAX_ZONENUM; Media.Zone++)
//for(Media.Zone=0; Media.Zone<Ssfdc.MaxZones; Media.Zone++)
{
- //printk("Make_D_LogTable --- MediaZone = 0x%x\n", Media.Zone);
+ /* pr_info("Make_D_LogTable --- MediaZone = 0x%x\n",
+ Media.Zone); */
for(Media.LogBlock=0; Media.LogBlock<Ssfdc.MaxLogBlocks; Media.LogBlock++)
Log2Phy[Media.Zone][Media.LogBlock]=NO_ASSIGN;
@@ -1735,7 +1733,7 @@
} // End for (Media.Zone<MAX_ZONENUM)
Ssfdc_D_Reset(us);
- return(SUCCESS);
+ return(SMSUCCESS);
}
//----- MarkFail_D_PhyOneBlock() ---------------------------------------
@@ -1763,7 +1761,7 @@
Ssfdc_D_Reset(us);
Media.Sector=sect;
- return(SUCCESS);
+ return(SMSUCCESS);
}
/*
//
@@ -1821,7 +1819,7 @@
//
// Ssfdc_D_Reset(fdoExt);
//
-// return(SUCCESS);
+// return(SMSUCCESS);
//}
//
////----- Media_D_GetMediaInfo() ---------------------------------------
diff --git a/drivers/staging/keucr/smilsub.c b/drivers/staging/keucr/smilsub.c
index 4fe4742..b315d5f 100644
--- a/drivers/staging/keucr/smilsub.c
+++ b/drivers/staging/keucr/smilsub.c
@@ -42,10 +42,8 @@
struct ADDRESS Media;
struct CIS_AREA CisArea;
-BYTE EccBuf[6];
+static BYTE EccBuf[6];
extern PBYTE SMHostAddr;
-extern BYTE IsSSFDCCompliance;
-extern BYTE IsXDCompliance;
extern DWORD ErrXDCode;
extern WORD ReadBlock;
@@ -67,7 +65,7 @@
if (*redundant++!=0xFF)
return(ERROR);
- return(SUCCESS);
+ return(SMSUCCESS);
}
//----- Check_D_FailBlock() --------------------------------------------
@@ -76,13 +74,13 @@
redundant+=REDT_BLOCK;
if (*redundant==0xFF)
- return(SUCCESS);
+ return(SMSUCCESS);
if (!*redundant)
return(ERROR);
if (hweight8(*redundant)<7)
return(ERROR);
- return(SUCCESS);
+ return(SMSUCCESS);
}
//----- Check_D_DataStatus() -------------------------------------------
@@ -91,7 +89,7 @@
redundant+=REDT_DATA;
if (*redundant==0xFF)
- return(SUCCESS);
+ return(SMSUCCESS);
if (!*redundant)
{
ErrXDCode = ERR_DataStatus;
@@ -103,7 +101,7 @@
if (hweight8(*redundant)<5)
return(ERROR);
- return(SUCCESS);
+ return(SMSUCCESS);
}
//----- Load_D_LogBlockAddr() ------------------------------------------
@@ -118,17 +116,17 @@
if (addr1==addr2)
if ((addr1 &0xF000)==0x1000)
- { Media.LogBlock=(addr1 &0x0FFF)/2; return(SUCCESS); }
+ { Media.LogBlock=(addr1 &0x0FFF)/2; return(SMSUCCESS); }
if (hweight16((WORD)(addr1^addr2))!=0x01) return(ERROR);
if ((addr1 &0xF000)==0x1000)
if (!(hweight16(addr1) &0x01))
- { Media.LogBlock=(addr1 &0x0FFF)/2; return(SUCCESS); }
+ { Media.LogBlock=(addr1 &0x0FFF)/2; return(SMSUCCESS); }
if ((addr2 &0xF000)==0x1000)
if (!(hweight16(addr2) &0x01))
- { Media.LogBlock=(addr2 &0x0FFF)/2; return(SUCCESS); }
+ { Media.LogBlock=(addr2 &0x0FFF)/2; return(SMSUCCESS); }
return(ERROR);
}
@@ -222,7 +220,7 @@
}
Media.Zone=zone; Media.PhyBlock=block; Media.Sector=sector;
- return(SUCCESS);
+ return(SMSUCCESS);
}
/*
////----- Ssfdc_D_WriteRedtMode() ----------------------------------------
@@ -428,7 +426,7 @@
//
// if (!_Hw_D_ChkCardIn())
// return(ERROR);
-// return(SUCCESS);
+// return(SMSUCCESS);
//}
//
////----- Ssfdc_D_ReadSect_PIO() ---------------------------------------------
@@ -451,7 +449,7 @@
//
// _Calc_D_ECCdata(buf);
// _Set_D_SsfdcRdStandby();
-// return(SUCCESS);
+// return(SMSUCCESS);
//}
// 6250 CMD 3
@@ -509,7 +507,7 @@
// ENE_Print("Error\n");
// }
- return(SUCCESS);
+ return(SMSUCCESS);
}
*/
//----- Ssfdc_D_CopyBlock() --------------------------------------------
@@ -614,7 +612,7 @@
// ENE_Print("Error\n");
// }
- return(SUCCESS);
+ return(SMSUCCESS);
}
//
////----- Ssfdc_D_WriteSect_DMA() --------------------------------------------
@@ -704,7 +702,7 @@
// if (!_Hw_D_ChkCardIn())
// return(ERROR);
//
-// return(SUCCESS);
+// return(SMSUCCESS);
//}
//
////----- Ssfdc_D_WriteSect_PIO() --------------------------------------------
@@ -729,7 +727,7 @@
//
// _Set_D_SsfdcWrStandby();
// _Set_D_SsfdcRdStandby();
-// return(SUCCESS);
+// return(SMSUCCESS);
//}
*/
//----- Ssfdc_D_WriteSectForCopy() -------------------------------------
@@ -893,14 +891,14 @@
int Ssfdc_D_CheckStatus(void)
{
// Driver ¤£°µ
- return(SUCCESS);
+ return(SMSUCCESS);
//_Set_D_SsfdcRdCmd(RDSTATUS);
//
//if (_Check_D_SsfdcStatus())
//{ _Set_D_SsfdcRdStandby(); return(ERROR); }
//
//_Set_D_SsfdcRdStandby();
- //return(SUCCESS);
+ //return(SMSUCCESS);
}
/*
////NAND Memory (SmartMedia) Control Subroutine for Read Data
@@ -1095,7 +1093,7 @@
//
// do {
// if (!_Hw_D_ChkBusy())
-// return(SUCCESS);
+// return(SMSUCCESS);
// EDelay(100);
// count++;
// } while (count<=time);
@@ -1109,7 +1107,7 @@
// if (_Hw_D_InData() & WR_FAIL)
// return(ERROR);
//
-// return(SUCCESS);
+// return(SMSUCCESS);
//}
//
//// For 712
@@ -1339,7 +1337,7 @@
return(ERROR);
}
- return(SUCCESS);
+ return(SMSUCCESS);
}
//----- _Check_D_DevCode() ---------------------------------------------
@@ -1388,7 +1386,7 @@
// if (_Hw_D_ChkPower())
// {
// _Hw_D_EnableOB(); // Set SM_REG_CTRL_5 Reg. to 0x83
-// return(SUCCESS);
+// return(SMSUCCESS);
// }
//
// _Hw_D_SetVccOff();
@@ -1419,7 +1417,7 @@
//int Check_D_CntPower(void)
//{
// if (_Hw_D_ChkPower())
-// return(SUCCESS); // Power On
+// return(SMSUCCESS); // Power On
//
// return(ERROR); // Power Off
//}
@@ -1431,7 +1429,7 @@
//
// if (!_Hw_D_ChkStatus()) // Not Status Change
// if (_Hw_D_ChkCardIn())
-// return(SUCCESS); // Card exist in Slot
+// return(SMSUCCESS); // Card exist in Slot
//
// for(i=0,j=0,k=0; i<16; i++) {
// if (_Hw_D_ChkCardIn()) // Status Change
@@ -1444,7 +1442,7 @@
// }
//
// if (j>3)
-// return(SUCCESS); // Card exist in Slot
+// return(SMSUCCESS); // Card exist in Slot
// if (k>3)
// return(ERROR); // NO Card exist in Slot
//
@@ -1460,12 +1458,12 @@
// if (_Hw_D_ChkStatus())
// return(ERROR); // Status Change
//
-// return(SUCCESS); // Not Status Change
+// return(SMSUCCESS); // Not Status Change
//}
//
////----- Check_D_SsfdcWP() ----------------------------------------------
//int Check_D_SsfdcWP(void)
-//{ // ERROR: WP, SUCCESS: Not WP
+//{ // ERROR: WP, SMSUCCESS: Not WP
// char i;
//
// for(i=0; i<8; i++) {
@@ -1474,7 +1472,7 @@
// _Wait_D_Timer(TIME_WPCHK);
// }
//
-// return(SUCCESS);
+// return(SMSUCCESS);
//}
//
*/
@@ -1482,13 +1480,13 @@
//----- Check_D_ReadError() ----------------------------------------------
int Check_D_ReadError(BYTE *redundant)
{
- return SUCCESS;
+ return SMSUCCESS;
}
//----- Check_D_Correct() ----------------------------------------------
int Check_D_Correct(BYTE *buf,BYTE *redundant)
{
- return SUCCESS;
+ return SMSUCCESS;
}
//----- Check_D_CISdata() ----------------------------------------------
@@ -1500,7 +1498,7 @@
int cis_len = sizeof(cis);
if (!IsSSFDCCompliance && !IsXDCompliance)
- return SUCCESS;
+ return SMSUCCESS;
if (!memcmp(redundant + 0x0D, EccBuf, 3))
return memcmp(buf, cis, cis_len);
@@ -1599,5 +1597,5 @@
if (!NT_SUCCESS(ntStatus))
return(ERROR);
- return(SUCCESS);
+ return(SMSUCCESS);
}*/
diff --git a/drivers/staging/keucr/smscsi.c b/drivers/staging/keucr/smscsi.c
index 6211686..a6fa77f 100644
--- a/drivers/staging/keucr/smscsi.c
+++ b/drivers/staging/keucr/smscsi.c
@@ -20,8 +20,6 @@
int SM_SCSI_Read (struct us_data *us, struct scsi_cmnd *srb);
int SM_SCSI_Write (struct us_data *us, struct scsi_cmnd *srb);
-extern struct SSFDCTYPE Ssfdc;
-extern struct ADDRESS Media;
extern PBYTE SMHostAddr;
extern DWORD ErrXDCode;
diff --git a/drivers/staging/keucr/transport.c b/drivers/staging/keucr/transport.c
index a53402f..0274cb0 100644
--- a/drivers/staging/keucr/transport.c
+++ b/drivers/staging/keucr/transport.c
@@ -1,3 +1,5 @@
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+
#include <linux/sched.h>
#include <linux/errno.h>
#include <linux/slab.h>
@@ -13,23 +15,27 @@
/***********************************************************************
* Data transfer routines
***********************************************************************/
-//----- usb_stor_blocking_completion() ---------------------
+/*
+ * usb_stor_blocking_completion()
+ */
static void usb_stor_blocking_completion(struct urb *urb)
{
struct completion *urb_done_ptr = urb->context;
- //printk("transport --- usb_stor_blocking_completion\n");
+ /* pr_info("transport --- usb_stor_blocking_completion\n"); */
complete(urb_done_ptr);
}
-//----- usb_stor_msg_common() ---------------------
+/*
+ * usb_stor_msg_common()
+ */
static int usb_stor_msg_common(struct us_data *us, int timeout)
{
struct completion urb_done;
long timeleft;
int status;
- //printk("transport --- usb_stor_msg_common\n");
+ /* pr_info("transport --- usb_stor_msg_common\n"); */
if (test_bit(US_FLIDX_ABORTING, &us->dflags))
return -EIO;
@@ -52,35 +58,36 @@
set_bit(US_FLIDX_URB_ACTIVE, &us->dflags);
- if (test_bit(US_FLIDX_ABORTING, &us->dflags))
- {
- if (test_and_clear_bit(US_FLIDX_URB_ACTIVE, &us->dflags))
- {
- //printk("-- cancelling URB\n");
+ if (test_bit(US_FLIDX_ABORTING, &us->dflags)) {
+ if (test_and_clear_bit(US_FLIDX_URB_ACTIVE, &us->dflags)) {
+ /* pr_info("-- cancelling URB\n"); */
usb_unlink_urb(us->current_urb);
}
}
- timeleft = wait_for_completion_interruptible_timeout(&urb_done, timeout ? : MAX_SCHEDULE_TIMEOUT);
+ timeleft = wait_for_completion_interruptible_timeout(&urb_done,
+ timeout ? : MAX_SCHEDULE_TIMEOUT);
clear_bit(US_FLIDX_URB_ACTIVE, &us->dflags);
- if (timeleft <= 0)
- {
- //printk("%s -- cancelling URB\n", timeleft == 0 ? "Timeout" : "Signal");
+ if (timeleft <= 0) {
+ /* pr_info("%s -- cancelling URB\n",
+ timeleft == 0 ? "Timeout" : "Signal"); */
usb_kill_urb(us->current_urb);
}
return us->current_urb->status;
}
-//----- usb_stor_control_msg() ---------------------
+/*
+ * usb_stor_control_msg()
+ */
int usb_stor_control_msg(struct us_data *us, unsigned int pipe,
u8 request, u8 requesttype, u16 value, u16 index,
void *data, u16 size, int timeout)
{
int status;
- //printk("transport --- usb_stor_control_msg\n");
+ /* pr_info("transport --- usb_stor_control_msg\n"); */
/* fill in the devrequest structure */
us->cr->bRequestType = requesttype;
@@ -91,7 +98,7 @@
/* fill and submit the URB */
usb_fill_control_urb(us->current_urb, us->pusb_dev, pipe,
- (unsigned char*) us->cr, data, size,
+ (unsigned char *) us->cr, data, size,
usb_stor_blocking_completion, NULL);
status = usb_stor_msg_common(us, timeout);
@@ -101,14 +108,16 @@
return status;
}
-//----- usb_stor_clear_halt() ---------------------
+/*
+ * usb_stor_clear_halt()
+ */
int usb_stor_clear_halt(struct us_data *us, unsigned int pipe)
{
int result;
int endp = usb_pipeendpoint(pipe);
- //printk("transport --- usb_stor_clear_halt\n");
- if (usb_pipein (pipe))
+ /* pr_info("transport --- usb_stor_clear_halt\n"); */
+ if (usb_pipein(pipe))
endp |= USB_DIR_IN;
result = usb_stor_control_msg(us, us->send_ctrl_pipe,
@@ -118,103 +127,109 @@
/* reset the endpoint toggle */
if (result >= 0)
- //usb_settoggle(us->pusb_dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 0);
- usb_reset_endpoint(us->pusb_dev, endp);
+ /* usb_settoggle(us->pusb_dev, usb_pipeendpoint(pipe),
+ usb_pipeout(pipe), 0); */
+ usb_reset_endpoint(us->pusb_dev, endp);
return result;
}
-//----- interpret_urb_result() ---------------------
+/*
+ * interpret_urb_result()
+ */
static int interpret_urb_result(struct us_data *us, unsigned int pipe,
unsigned int length, int result, unsigned int partial)
{
- //printk("transport --- interpret_urb_result\n");
+ /* pr_info("transport --- interpret_urb_result\n"); */
switch (result) {
/* no error code; did we send all the data? */
case 0:
- if (partial != length)
- {
- //printk("-- short transfer\n");
+ if (partial != length) {
+ /* pr_info("-- short transfer\n"); */
return USB_STOR_XFER_SHORT;
}
- //printk("-- transfer complete\n");
+ /* pr_info("-- transfer complete\n"); */
return USB_STOR_XFER_GOOD;
case -EPIPE:
- if (usb_pipecontrol(pipe))
- {
- //printk("-- stall on control pipe\n");
+ if (usb_pipecontrol(pipe)) {
+ /* pr_info("-- stall on control pipe\n"); */
return USB_STOR_XFER_STALLED;
}
- //printk("clearing endpoint halt for pipe 0x%x\n", pipe);
+ /* pr_info("clearing endpoint halt for pipe 0x%x\n", pipe); */
if (usb_stor_clear_halt(us, pipe) < 0)
return USB_STOR_XFER_ERROR;
return USB_STOR_XFER_STALLED;
case -EOVERFLOW:
- //printk("-- babble\n");
+ /* pr_info("-- babble\n"); */
return USB_STOR_XFER_LONG;
case -ECONNRESET:
- //printk("-- transfer cancelled\n");
+ /* pr_info("-- transfer cancelled\n"); */
return USB_STOR_XFER_ERROR;
case -EREMOTEIO:
- //printk("-- short read transfer\n");
+ /* pr_info("-- short read transfer\n"); */
return USB_STOR_XFER_SHORT;
case -EIO:
- //printk("-- abort or disconnect in progress\n");
+ /* pr_info("-- abort or disconnect in progress\n"); */
return USB_STOR_XFER_ERROR;
default:
- //printk("-- unknown error\n");
+ /* pr_info("-- unknown error\n"); */
return USB_STOR_XFER_ERROR;
}
}
-//----- usb_stor_bulk_transfer_buf() ---------------------
+/*
+ * usb_stor_bulk_transfer_buf()
+ */
int usb_stor_bulk_transfer_buf(struct us_data *us, unsigned int pipe,
void *buf, unsigned int length, unsigned int *act_len)
{
int result;
- //printk("transport --- usb_stor_bulk_transfer_buf\n");
+ /* pr_info("transport --- usb_stor_bulk_transfer_buf\n"); */
/* fill and submit the URB */
- usb_fill_bulk_urb(us->current_urb, us->pusb_dev, pipe, buf, length, usb_stor_blocking_completion, NULL);
+ usb_fill_bulk_urb(us->current_urb, us->pusb_dev, pipe, buf,
+ length, usb_stor_blocking_completion, NULL);
result = usb_stor_msg_common(us, 0);
/* store the actual length of the data transferred */
if (act_len)
*act_len = us->current_urb->actual_length;
- return interpret_urb_result(us, pipe, length, result, us->current_urb->actual_length);
+ return interpret_urb_result(us, pipe, length, result,
+ us->current_urb->actual_length);
}
-//----- usb_stor_bulk_transfer_sglist() ---------------------
+/*
+ * usb_stor_bulk_transfer_sglist()
+ */
static int usb_stor_bulk_transfer_sglist(struct us_data *us, unsigned int pipe,
struct scatterlist *sg, int num_sg, unsigned int length,
unsigned int *act_len)
{
int result;
- //printk("transport --- usb_stor_bulk_transfer_sglist\n");
+ /* pr_info("transport --- usb_stor_bulk_transfer_sglist\n"); */
if (test_bit(US_FLIDX_ABORTING, &us->dflags))
return USB_STOR_XFER_ERROR;
/* initialize the scatter-gather request block */
- result = usb_sg_init(&us->current_sg, us->pusb_dev, pipe, 0, sg, num_sg, length, GFP_NOIO);
- if (result)
- {
- //printk("usb_sg_init returned %d\n", result);
+ result = usb_sg_init(&us->current_sg, us->pusb_dev, pipe, 0,
+ sg, num_sg, length, GFP_NOIO);
+ if (result) {
+ /* pr_info("usb_sg_init returned %d\n", result); */
return USB_STOR_XFER_ERROR;
}
- /* since the block has been initialized successfully, it's now okay to cancel it */
+ /* since the block has been initialized successfully,
+ it's now okay to cancel it */
set_bit(US_FLIDX_SG_ACTIVE, &us->dflags);
/* did an abort/disconnect occur during the submission? */
- if (test_bit(US_FLIDX_ABORTING, &us->dflags))
- {
+ if (test_bit(US_FLIDX_ABORTING, &us->dflags)) {
/* cancel the request, if it hasn't been cancelled already */
- if (test_and_clear_bit(US_FLIDX_SG_ACTIVE, &us->dflags))
- {
- //printk("-- cancelling sg request\n");
+ if (test_and_clear_bit(US_FLIDX_SG_ACTIVE, &us->dflags)) {
+ /* pr_info("-- cancelling sg request\n"); */
usb_sg_cancel(&us->current_sg);
}
}
@@ -227,11 +242,15 @@
if (act_len)
*act_len = us->current_sg.bytes;
- return interpret_urb_result(us, pipe, length, result, us->current_sg.bytes);
+ return interpret_urb_result(us, pipe, length,
+ result, us->current_sg.bytes);
}
-//----- usb_stor_bulk_srb() ---------------------
-int usb_stor_bulk_srb(struct us_data* us, unsigned int pipe, struct scsi_cmnd* srb)
+/*
+ * usb_stor_bulk_srb()
+ */
+int usb_stor_bulk_srb(struct us_data *us, unsigned int pipe,
+ struct scsi_cmnd *srb)
{
unsigned int partial;
int result = usb_stor_bulk_transfer_sglist(us, pipe, scsi_sglist(srb),
@@ -242,27 +261,27 @@
return result;
}
-//----- usb_stor_bulk_transfer_sg() ---------------------
-int usb_stor_bulk_transfer_sg(struct us_data* us, unsigned int pipe,
+/*
+ * usb_stor_bulk_transfer_sg()
+ */
+int usb_stor_bulk_transfer_sg(struct us_data *us, unsigned int pipe,
void *buf, unsigned int length_left, int use_sg, int *residual)
{
int result;
unsigned int partial;
- //printk("transport --- usb_stor_bulk_transfer_sg\n");
+ /* pr_info("transport --- usb_stor_bulk_transfer_sg\n"); */
/* are we scatter-gathering? */
- if (use_sg)
- {
+ if (use_sg) {
/* use the usb core scatter-gather primitives */
result = usb_stor_bulk_transfer_sglist(us, pipe,
(struct scatterlist *) buf, use_sg,
length_left, &partial);
length_left -= partial;
- }
- else
- {
+ } else {
/* no scatter-gather, just make the request */
- result = usb_stor_bulk_transfer_buf(us, pipe, buf, length_left, &partial);
+ result = usb_stor_bulk_transfer_buf(us, pipe, buf,
+ length_left, &partial);
length_left -= partial;
}
@@ -275,37 +294,37 @@
/***********************************************************************
* Transport routines
***********************************************************************/
-//----- usb_stor_invoke_transport() ---------------------
+/*
+ * usb_stor_invoke_transport()
+ */
void usb_stor_invoke_transport(struct scsi_cmnd *srb, struct us_data *us)
{
int need_auto_sense;
int result;
- //printk("transport --- usb_stor_invoke_transport\n");
+ /* pr_info("transport --- usb_stor_invoke_transport\n"); */
usb_stor_print_cmd(srb);
/* send the command to the transport layer */
scsi_set_resid(srb, 0);
- result = us->transport(srb, us); //usb_stor_Bulk_transport;
-
- /* if the command gets aborted by the higher layers, we need to short-circuit all other processing */
- if (test_bit(US_FLIDX_TIMED_OUT, &us->dflags))
- {
- //printk("-- command was aborted\n");
+ result = us->transport(srb, us); /* usb_stor_Bulk_transport; */
+
+ /* if the command gets aborted by the higher layers,
+ we need to short-circuit all other processing */
+ if (test_bit(US_FLIDX_TIMED_OUT, &us->dflags)) {
+ /* pr_info("-- command was aborted\n"); */
srb->result = DID_ABORT << 16;
goto Handle_Errors;
}
/* if there is a transport error, reset and don't auto-sense */
- if (result == USB_STOR_TRANSPORT_ERROR)
- {
- //printk("-- transport indicates error, resetting\n");
+ if (result == USB_STOR_TRANSPORT_ERROR) {
+ /* pr_info("-- transport indicates error, resetting\n"); */
srb->result = DID_ERROR << 16;
goto Handle_Errors;
}
/* if the transport provided its own sense data, don't auto-sense */
- if (result == USB_STOR_TRANSPORT_NO_SENSE)
- {
+ if (result == USB_STOR_TRANSPORT_NO_SENSE) {
srb->result = SAM_STAT_CHECK_CONDITION;
return;
}
@@ -315,34 +334,34 @@
/* Determine if we need to auto-sense */
need_auto_sense = 0;
- if ((us->protocol == USB_PR_CB || us->protocol == USB_PR_DPCM_USB) && srb->sc_data_direction != DMA_FROM_DEVICE)
- {
- //printk("-- CB transport device requiring auto-sense\n");
+ if ((us->protocol == USB_PR_CB || us->protocol == USB_PR_DPCM_USB) &&
+ srb->sc_data_direction != DMA_FROM_DEVICE) {
+ /* pr_info("-- CB transport device requiring auto-sense\n"); */
need_auto_sense = 1;
}
- if (result == USB_STOR_TRANSPORT_FAILED)
- {
- //printk("-- transport indicates command failure\n");
+ if (result == USB_STOR_TRANSPORT_FAILED) {
+ /* pr_info("-- transport indicates command failure\n"); */
need_auto_sense = 1;
}
/* Now, if we need to do the auto-sense, let's do it */
- if (need_auto_sense)
- {
+ if (need_auto_sense) {
int temp_result;
struct scsi_eh_save ses;
- printk("Issuing auto-REQUEST_SENSE\n");
+ pr_info("Issuing auto-REQUEST_SENSE\n");
scsi_eh_prep_cmnd(srb, &ses, NULL, 0, US_SENSE_SIZE);
/* we must do the protocol translation here */
- if (us->subclass == USB_SC_RBC || us->subclass == USB_SC_SCSI || us->subclass == USB_SC_CYP_ATACB)
+ if (us->subclass == USB_SC_RBC ||
+ us->subclass == USB_SC_SCSI ||
+ us->subclass == USB_SC_CYP_ATACB) {
srb->cmd_len = 6;
- else
+ } else {
srb->cmd_len = 12;
-
+ }
/* issue the auto-sense command */
scsi_set_resid(srb, 0);
temp_result = us->transport(us->srb, us);
@@ -350,15 +369,13 @@
/* let's clean up right away */
scsi_eh_restore_cmnd(srb, &ses);
- if (test_bit(US_FLIDX_TIMED_OUT, &us->dflags))
- {
- //printk("-- auto-sense aborted\n");
+ if (test_bit(US_FLIDX_TIMED_OUT, &us->dflags)) {
+ /* pr_info("-- auto-sense aborted\n"); */
srb->result = DID_ABORT << 16;
goto Handle_Errors;
}
- if (temp_result != USB_STOR_TRANSPORT_GOOD)
- {
- //printk("-- auto-sense failure\n");
+ if (temp_result != USB_STOR_TRANSPORT_GOOD) {
+ /* pr_info("-- auto-sense failure\n"); */
srb->result = DID_ERROR << 16;
if (!(us->fflags & US_FL_SCM_MULT_TARG))
goto Handle_Errors;
@@ -371,16 +388,17 @@
if (result == USB_STOR_TRANSPORT_GOOD &&
(srb->sense_buffer[2] & 0xaf) == 0 &&
srb->sense_buffer[12] == 0 &&
- srb->sense_buffer[13] == 0)
- {
+ srb->sense_buffer[13] == 0) {
srb->result = SAM_STAT_GOOD;
srb->sense_buffer[0] = 0x0;
}
}
/* Did we transfer less than the minimum amount required? */
- if (srb->result == SAM_STAT_GOOD && scsi_bufflen(srb) - scsi_get_resid(srb) < srb->underflow)
- srb->result = (DID_ERROR << 16);//v02 | (SUGGEST_RETRY << 24);
+ if (srb->result == SAM_STAT_GOOD && scsi_bufflen(srb) -
+ scsi_get_resid(srb) < srb->underflow)
+ srb->result = (DID_ERROR << 16);
+ /* v02 | (SUGGEST_RETRY << 24); */
return;
@@ -394,8 +412,7 @@
result = usb_stor_port_reset(us);
mutex_lock(&us->dev_mutex);
- if (result < 0)
- {
+ if (result < 0) {
scsi_lock(us_to_host(us));
usb_stor_report_device_reset(us);
scsi_unlock(us_to_host(us));
@@ -404,61 +421,64 @@
clear_bit(US_FLIDX_RESETTING, &us->dflags);
}
-//----- ENE_stor_invoke_transport() ---------------------
+/*
+ * ENE_stor_invoke_transport()
+ */
void ENE_stor_invoke_transport(struct scsi_cmnd *srb, struct us_data *us)
{
- int result=0;
+ int result = 0;
- //printk("transport --- ENE_stor_invoke_transport\n");
+ /* pr_info("transport --- ENE_stor_invoke_transport\n"); */
usb_stor_print_cmd(srb);
/* send the command to the transport layer */
scsi_set_resid(srb, 0);
if (!(us->MS_Status.Ready || us->SM_Status.Ready))
result = ENE_InitMedia(us);
-
+
if (us->Power_IsResum == true) {
result = ENE_InitMedia(us);
- us->Power_IsResum = false;
- }
-
- if (us->MS_Status.Ready) result = MS_SCSIIrp(us, srb);
- if (us->SM_Status.Ready) result = SM_SCSIIrp(us, srb);
+ us->Power_IsResum = false;
+ }
- /* if the command gets aborted by the higher layers, we need to short-circuit all other processing */
- if (test_bit(US_FLIDX_TIMED_OUT, &us->dflags))
- {
- //printk("-- command was aborted\n");
+ if (us->MS_Status.Ready)
+ result = MS_SCSIIrp(us, srb);
+ if (us->SM_Status.Ready)
+ result = SM_SCSIIrp(us, srb);
+
+ /* if the command gets aborted by the higher layers,
+ we need to short-circuit all other processing */
+ if (test_bit(US_FLIDX_TIMED_OUT, &us->dflags)) {
+ /* pr_info("-- command was aborted\n"); */
srb->result = DID_ABORT << 16;
goto Handle_Errors;
}
/* if there is a transport error, reset and don't auto-sense */
- if (result == USB_STOR_TRANSPORT_ERROR)
- {
- //printk("-- transport indicates error, resetting\n");
+ if (result == USB_STOR_TRANSPORT_ERROR) {
+ /* pr_info("-- transport indicates error, resetting\n"); */
srb->result = DID_ERROR << 16;
goto Handle_Errors;
}
/* if the transport provided its own sense data, don't auto-sense */
- if (result == USB_STOR_TRANSPORT_NO_SENSE)
- {
+ if (result == USB_STOR_TRANSPORT_NO_SENSE) {
srb->result = SAM_STAT_CHECK_CONDITION;
return;
}
srb->result = SAM_STAT_GOOD;
- if (result == USB_STOR_TRANSPORT_FAILED)
- {
- //printk("-- transport indicates command failure\n");
- //need_auto_sense = 1;
+ if (result == USB_STOR_TRANSPORT_FAILED) {
+ /* pr_info("-- transport indicates command failure\n"); */
+ /* need_auto_sense = 1; */
BuildSenseBuffer(srb, us->SrbStatus);
srb->result = SAM_STAT_CHECK_CONDITION;
}
/* Did we transfer less than the minimum amount required? */
- if (srb->result == SAM_STAT_GOOD && scsi_bufflen(srb) - scsi_get_resid(srb) < srb->underflow)
- srb->result = (DID_ERROR << 16);//v02 | (SUGGEST_RETRY << 24);
+ if (srb->result == SAM_STAT_GOOD && scsi_bufflen(srb) -
+ scsi_get_resid(srb) < srb->underflow)
+ srb->result = (DID_ERROR << 16);
+ /* v02 | (SUGGEST_RETRY << 24); */
return;
@@ -472,8 +492,7 @@
result = usb_stor_port_reset(us);
mutex_lock(&us->dev_mutex);
- if (result < 0)
- {
+ if (result < 0) {
scsi_lock(us_to_host(us));
usb_stor_report_device_reset(us);
scsi_unlock(us_to_host(us));
@@ -482,52 +501,63 @@
clear_bit(US_FLIDX_RESETTING, &us->dflags);
}
-//----- BuildSenseBuffer() -------------------------------------------
+/*
+ * BuildSenseBuffer()
+ */
void BuildSenseBuffer(struct scsi_cmnd *srb, int SrbStatus)
{
- BYTE *buf = srb->sense_buffer;
- BYTE asc;
+ BYTE *buf = srb->sense_buffer;
+ BYTE asc;
- printk("transport --- BuildSenseBuffer\n");
- switch (SrbStatus)
- {
- case SS_NOT_READY: asc = 0x3a; break; // sense key = 0x02
- case SS_MEDIUM_ERR: asc = 0x0c; break; // sense key = 0x03
- case SS_ILLEGAL_REQUEST: asc = 0x20; break; // sense key = 0x05
- default: asc = 0x00; break; // ??
- }
+ pr_info("transport --- BuildSenseBuffer\n");
+ switch (SrbStatus) {
+ case SS_NOT_READY:
+ asc = 0x3a;
+ break; /* sense key = 0x02 */
+ case SS_MEDIUM_ERR:
+ asc = 0x0c;
+ break; /* sense key = 0x03 */
+ case SS_ILLEGAL_REQUEST:
+ asc = 0x20;
+ break; /* sense key = 0x05 */
+ default:
+ asc = 0x00;
+ break; /* ?? */
+ }
- memset(buf, 0, 18);
- buf[0x00] = 0xf0;
- buf[0x02] = SrbStatus;
- buf[0x07] = 0x0b;
- buf[0x0c] = asc;
+ memset(buf, 0, 18);
+ buf[0x00] = 0xf0;
+ buf[0x02] = SrbStatus;
+ buf[0x07] = 0x0b;
+ buf[0x0c] = asc;
}
-//----- usb_stor_stop_transport() ---------------------
+/*
+ * usb_stor_stop_transport()
+ */
void usb_stor_stop_transport(struct us_data *us)
{
- //printk("transport --- usb_stor_stop_transport\n");
+ /* pr_info("transport --- usb_stor_stop_transport\n"); */
- if (test_and_clear_bit(US_FLIDX_URB_ACTIVE, &us->dflags))
- {
- //printk("-- cancelling URB\n");
+ if (test_and_clear_bit(US_FLIDX_URB_ACTIVE, &us->dflags)) {
+ /* pr_info("-- cancelling URB\n"); */
usb_unlink_urb(us->current_urb);
}
- if (test_and_clear_bit(US_FLIDX_SG_ACTIVE, &us->dflags))
- {
- //printk("-- cancelling sg request\n");
+ if (test_and_clear_bit(US_FLIDX_SG_ACTIVE, &us->dflags)) {
+ /* pr_info("-- cancelling sg request\n"); */
usb_sg_cancel(&us->current_sg);
}
}
-//----- usb_stor_Bulk_max_lun() ---------------------
+/*
+ * usb_stor_Bulk_max_lun()
+ */
int usb_stor_Bulk_max_lun(struct us_data *us)
{
int result;
- //printk("transport --- usb_stor_Bulk_max_lun\n");
+ /* pr_info("transport --- usb_stor_Bulk_max_lun\n"); */
/* issue the command */
us->iobuf[0] = 0;
result = usb_stor_control_msg(us, us->recv_ctrl_pipe,
@@ -536,7 +566,8 @@
USB_RECIP_INTERFACE,
0, us->ifnum, us->iobuf, 1, HZ);
- //printk("GetMaxLUN command result is %d, data is %d\n", result, us->iobuf[0]);
+ /* pr_info("GetMaxLUN command result is %d, data is %d\n",
+ result, us->iobuf[0]); */
/* if we have a successful request, return the result */
if (result > 0)
@@ -545,7 +576,9 @@
return 0;
}
-//----- usb_stor_Bulk_transport() ---------------------
+/*
+ * usb_stor_Bulk_transport()
+ */
int usb_stor_Bulk_transport(struct scsi_cmnd *srb, struct us_data *us)
{
struct bulk_cb_wrap *bcb = (struct bulk_cb_wrap *) us->iobuf;
@@ -557,10 +590,9 @@
unsigned int cswlen;
unsigned int cbwlen = US_BULK_CB_WRAP_LEN;
- //printk("transport --- usb_stor_Bulk_transport\n");
+ /* pr_info("transport --- usb_stor_Bulk_transport\n"); */
/* Take care of BULK32 devices; set extra byte to 0 */
- if (unlikely(us->fflags & US_FL_BULK32))
- {
+ if (unlikely(us->fflags & US_FL_BULK32)) {
cbwlen = 32;
us->iobuf[31] = 0;
}
@@ -579,27 +611,32 @@
memset(bcb->CDB, 0, sizeof(bcb->CDB));
memcpy(bcb->CDB, srb->cmnd, bcb->Length);
- // send command
+ /* send command */
/* send it to out endpoint */
- /*printk("Bulk Command S 0x%x T 0x%x L %d F %d Trg %d LUN %d CL %d\n",
+ /* pr_info("Bulk Command S 0x%x T 0x%x L %d F %d Trg %d LUN %d CL %d\n",
le32_to_cpu(bcb->Signature), bcb->Tag,
le32_to_cpu(bcb->DataTransferLength), bcb->Flags,
(bcb->Lun >> 4), (bcb->Lun & 0x0F),
- bcb->Length);*/
- result = usb_stor_bulk_transfer_buf(us, us->send_bulk_pipe, bcb, cbwlen, NULL);
- //printk("Bulk command transfer result=%d\n", result);
+ bcb->Length); */
+ result = usb_stor_bulk_transfer_buf(us, us->send_bulk_pipe,
+ bcb, cbwlen, NULL);
+ /* pr_info("Bulk command transfer result=%d\n", result); */
if (result != USB_STOR_XFER_GOOD)
return USB_STOR_TRANSPORT_ERROR;
if (unlikely(us->fflags & US_FL_GO_SLOW))
udelay(125);
- // R/W data
- if (transfer_length)
- {
- unsigned int pipe = srb->sc_data_direction == DMA_FROM_DEVICE ? us->recv_bulk_pipe : us->send_bulk_pipe;
+ /* R/W data */
+ if (transfer_length) {
+ unsigned int pipe;
+ if (srb->sc_data_direction == DMA_FROM_DEVICE)
+ pipe = us->recv_bulk_pipe;
+ else
+ pipe = us->send_bulk_pipe;
+
result = usb_stor_bulk_srb(us, pipe, srb);
- //printk("Bulk data transfer result 0x%x\n", result);
+ /* pr_info("Bulk data transfer result 0x%x\n", result); */
if (result == USB_STOR_XFER_ERROR)
return USB_STOR_TRANSPORT_ERROR;
@@ -608,55 +645,56 @@
}
/* get CSW for device status */
- //printk("Attempting to get CSW...\n");
- result = usb_stor_bulk_transfer_buf(us, us->recv_bulk_pipe, bcs, US_BULK_CS_WRAP_LEN, &cswlen);
+ /* pr_info("Attempting to get CSW...\n"); */
+ result = usb_stor_bulk_transfer_buf(us, us->recv_bulk_pipe, bcs,
+ US_BULK_CS_WRAP_LEN, &cswlen);
- if (result == USB_STOR_XFER_SHORT && cswlen == 0)
- {
- //printk("Received 0-length CSW; retrying...\n");
- result = usb_stor_bulk_transfer_buf(us, us->recv_bulk_pipe, bcs, US_BULK_CS_WRAP_LEN, &cswlen);
+ if (result == USB_STOR_XFER_SHORT && cswlen == 0) {
+ /* pr_info("Received 0-length CSW; retrying...\n"); */
+ result = usb_stor_bulk_transfer_buf(us, us->recv_bulk_pipe, bcs,
+ US_BULK_CS_WRAP_LEN, &cswlen);
}
/* did the attempt to read the CSW fail? */
- if (result == USB_STOR_XFER_STALLED)
- {
+ if (result == USB_STOR_XFER_STALLED) {
/* get the status again */
- //printk("Attempting to get CSW (2nd try)...\n");
- result = usb_stor_bulk_transfer_buf(us, us->recv_bulk_pipe, bcs, US_BULK_CS_WRAP_LEN, NULL);
+ /* pr_info("Attempting to get CSW (2nd try)...\n"); */
+ result = usb_stor_bulk_transfer_buf(us, us->recv_bulk_pipe, bcs,
+ US_BULK_CS_WRAP_LEN, NULL);
}
/* if we still have a failure at this point, we're in trouble */
- //printk("Bulk status result = %d\n", result);
+ /* pr_info("Bulk status result = %d\n", result); */
if (result != USB_STOR_XFER_GOOD)
return USB_STOR_TRANSPORT_ERROR;
/* check bulk status */
residue = le32_to_cpu(bcs->Residue);
- //printk("Bulk Status S 0x%x T 0x%x R %u Stat 0x%x\n", le32_to_cpu(bcs->Signature), bcs->Tag, residue, bcs->Status);
- if (!(bcs->Tag == us->tag || (us->fflags & US_FL_BULK_IGNORE_TAG)) || bcs->Status > US_BULK_STAT_PHASE)
- {
- //printk("Bulk logical error\n");
+ /* pr_info("Bulk Status S 0x%x T 0x%x R %u Stat 0x%x\n",
+ le32_to_cpu(bcs->Signature),
+ bcs->Tag, residue, bcs->Status); */
+ if (!(bcs->Tag == us->tag ||
+ (us->fflags & US_FL_BULK_IGNORE_TAG)) ||
+ bcs->Status > US_BULK_STAT_PHASE) {
+ /* pr_info("Bulk logical error\n"); */
return USB_STOR_TRANSPORT_ERROR;
}
- if (!us->bcs_signature)
- {
+ if (!us->bcs_signature) {
us->bcs_signature = bcs->Signature;
- //if (us->bcs_signature != cpu_to_le32(US_BULK_CS_SIGN))
- // printk("Learnt BCS signature 0x%08X\n", le32_to_cpu(us->bcs_signature));
- }
- else if (bcs->Signature != us->bcs_signature)
- {
- /*printk("Signature mismatch: got %08X, expecting %08X\n",
+ /* if (us->bcs_signature != cpu_to_le32(US_BULK_CS_SIGN)) */
+ /* pr_info("Learnt BCS signature 0x%08X\n",
+ le32_to_cpu(us->bcs_signature)); */
+ } else if (bcs->Signature != us->bcs_signature) {
+ /* pr_info("Signature mismatch: got %08X, expecting %08X\n",
le32_to_cpu(bcs->Signature),
- le32_to_cpu(us->bcs_signature));*/
+ le32_to_cpu(us->bcs_signature)); */
return USB_STOR_TRANSPORT_ERROR;
}
/* try to compute the actual residue, based on how much data
* was really transferred and what the device tells us */
- if (residue && !(us->fflags & US_FL_IGNORE_RESIDUE))
- {
+ if (residue && !(us->fflags & US_FL_IGNORE_RESIDUE)) {
/* Heuristically detect devices that generate bogus residues
* by seeing what happens with INQUIRY and READ CAPACITY
@@ -667,34 +705,31 @@
((srb->cmnd[0] == INQUIRY &&
transfer_length == 36) ||
(srb->cmnd[0] == READ_CAPACITY &&
- transfer_length == 8)))
- {
+ transfer_length == 8))) {
us->fflags |= US_FL_IGNORE_RESIDUE;
- }
- else
- {
+ } else {
residue = min(residue, transfer_length);
- scsi_set_resid(srb, max(scsi_get_resid(srb), (int) residue));
+ scsi_set_resid(srb, max(scsi_get_resid(srb),
+ (int) residue));
}
}
/* based on the status code, we report good or bad */
- switch (bcs->Status)
- {
- case US_BULK_STAT_OK:
- if (fake_sense)
- {
- memcpy(srb->sense_buffer, usb_stor_sense_invalidCDB, sizeof(usb_stor_sense_invalidCDB));
- return USB_STOR_TRANSPORT_NO_SENSE;
- }
- return USB_STOR_TRANSPORT_GOOD;
+ switch (bcs->Status) {
+ case US_BULK_STAT_OK:
+ if (fake_sense) {
+ memcpy(srb->sense_buffer, usb_stor_sense_invalidCDB,
+ sizeof(usb_stor_sense_invalidCDB));
+ return USB_STOR_TRANSPORT_NO_SENSE;
+ }
+ return USB_STOR_TRANSPORT_GOOD;
- case US_BULK_STAT_FAIL:
- return USB_STOR_TRANSPORT_FAILED;
+ case US_BULK_STAT_FAIL:
+ return USB_STOR_TRANSPORT_FAILED;
- case US_BULK_STAT_PHASE:
- return USB_STOR_TRANSPORT_ERROR;
+ case US_BULK_STAT_PHASE:
+ return USB_STOR_TRANSPORT_ERROR;
}
return USB_STOR_TRANSPORT_ERROR;
}
@@ -702,7 +737,9 @@
/***********************************************************************
* Reset routines
***********************************************************************/
-//----- usb_stor_reset_common() ---------------------
+/*
+ * usb_stor_reset_common()
+ */
static int usb_stor_reset_common(struct us_data *us,
u8 request, u8 requesttype,
u16 value, u16 index, void *data, u16 size)
@@ -710,69 +747,75 @@
int result;
int result2;
- //printk("transport --- usb_stor_reset_common\n");
- if (test_bit(US_FLIDX_DISCONNECTING, &us->dflags))
- {
- //printk("No reset during disconnect\n");
+ /* pr_info("transport --- usb_stor_reset_common\n"); */
+ if (test_bit(US_FLIDX_DISCONNECTING, &us->dflags)) {
+ /* pr_info("No reset during disconnect\n"); */
return -EIO;
}
- result = usb_stor_control_msg(us, us->send_ctrl_pipe, request, requesttype, value, index, data, size, 5*HZ);
- if (result < 0)
- {
- //printk("Soft reset failed: %d\n", result);
+ result = usb_stor_control_msg(us, us->send_ctrl_pipe,
+ request, requesttype, value, index, data, size, 5*HZ);
+
+ if (result < 0) {
+ /* pr_info("Soft reset failed: %d\n", result); */
return result;
}
- wait_event_interruptible_timeout(us->delay_wait, test_bit(US_FLIDX_DISCONNECTING, &us->dflags), HZ*6);
- if (test_bit(US_FLIDX_DISCONNECTING, &us->dflags))
- {
- //printk("Reset interrupted by disconnect\n");
+ wait_event_interruptible_timeout(us->delay_wait,
+ test_bit(US_FLIDX_DISCONNECTING, &us->dflags), HZ*6);
+
+ if (test_bit(US_FLIDX_DISCONNECTING, &us->dflags)) {
+ /* pr_info("Reset interrupted by disconnect\n"); */
return -EIO;
}
- //printk("Soft reset: clearing bulk-in endpoint halt\n");
+ /* pr_info("Soft reset: clearing bulk-in endpoint halt\n"); */
result = usb_stor_clear_halt(us, us->recv_bulk_pipe);
- //printk("Soft reset: clearing bulk-out endpoint halt\n");
+ /* pr_info("Soft reset: clearing bulk-out endpoint halt\n"); */
result2 = usb_stor_clear_halt(us, us->send_bulk_pipe);
/* return a result code based on the result of the clear-halts */
if (result >= 0)
result = result2;
- //if (result < 0)
- // printk("Soft reset failed\n");
- //else
- // printk("Soft reset done\n");
+ /* if (result < 0) */
+ /* pr_info("Soft reset failed\n"); */
+ /* else */
+ /* pr_info("Soft reset done\n"); */
return result;
}
-//----- usb_stor_Bulk_reset() ---------------------
+/*
+ * usb_stor_Bulk_reset()
+ */
int usb_stor_Bulk_reset(struct us_data *us)
{
- //printk("transport --- usb_stor_Bulk_reset\n");
+ /* pr_info("transport --- usb_stor_Bulk_reset\n"); */
return usb_stor_reset_common(us, US_BULK_RESET_REQUEST,
USB_TYPE_CLASS | USB_RECIP_INTERFACE,
0, us->ifnum, NULL, 0);
}
-//----- usb_stor_port_reset() ---------------------
+/*
+ * usb_stor_port_reset()
+ */
int usb_stor_port_reset(struct us_data *us)
{
int result;
- //printk("transport --- usb_stor_port_reset\n");
+ /* pr_info("transport --- usb_stor_port_reset\n"); */
result = usb_lock_device_for_reset(us->pusb_dev, us->pusb_intf);
if (result < 0)
- printk("unable to lock device for reset: %d\n", result);
+ pr_info("unable to lock device for reset: %d\n", result);
else {
/* Were we disconnected while waiting for the lock? */
if (test_bit(US_FLIDX_DISCONNECTING, &us->dflags)) {
result = -EIO;
- //printk("No reset during disconnect\n");
+ /* pr_info("No reset during disconnect\n"); */
} else {
result = usb_reset_device(us->pusb_dev);
- //printk("usb_reset_composite_device returns %d\n", result);
+ /* pr_info("usb_reset_composite_device returns %d\n",
+ result); */
}
usb_unlock_device(us->pusb_dev);
}
diff --git a/drivers/staging/keucr/transport.h b/drivers/staging/keucr/transport.h
index 565d98c..7529615 100644
--- a/drivers/staging/keucr/transport.h
+++ b/drivers/staging/keucr/transport.h
@@ -8,7 +8,7 @@
/* command block wrapper */
struct bulk_cb_wrap {
__le32 Signature; /* contains 'USBC' */
- __u32 Tag; /* unique per command id */
+ __u32 Tag; /* unique per command id */
__le32 DataTransferLength; /* size of data */
__u8 Flags; /* direction in bit 0 */
__u8 Lun; /* LUN normally 0 */
@@ -49,9 +49,9 @@
/* Transport return codes */
#define USB_STOR_TRANSPORT_GOOD 0 /* Transport good, command good */
-#define USB_STOR_TRANSPORT_FAILED 1 /* Transport good, command failed */
-#define USB_STOR_TRANSPORT_NO_SENSE 2 /* Command failed, no auto-sense */
-#define USB_STOR_TRANSPORT_ERROR 3 /* Transport bad (i.e. device dead) */
+#define USB_STOR_TRANSPORT_FAILED 1 /* Transport good, command failed */
+#define USB_STOR_TRANSPORT_NO_SENSE 2 /* Command failed, no auto-sense */
+#define USB_STOR_TRANSPORT_ERROR 3 /* Transport bad (i.e. device dead) */
/*
* We used to have USB_STOR_XFER_ABORTED and USB_STOR_TRANSPORT_ABORTED
@@ -64,11 +64,11 @@
/* CBI accept device specific command */
#define US_CBI_ADSC 0
extern int usb_stor_Bulk_transport(struct scsi_cmnd *, struct us_data*);
-extern int usb_stor_Bulk_max_lun(struct us_data*);
-extern int usb_stor_Bulk_reset(struct us_data*);
+extern int usb_stor_Bulk_max_lun(struct us_data *);
+extern int usb_stor_Bulk_reset(struct us_data *);
extern void usb_stor_print_cmd(struct scsi_cmnd *);
extern void usb_stor_invoke_transport(struct scsi_cmnd *, struct us_data*);
-extern void usb_stor_stop_transport(struct us_data*);
+extern void usb_stor_stop_transport(struct us_data *);
extern int usb_stor_control_msg(struct us_data *us, unsigned int pipe,
u8 request, u8 requesttype, u16 value, u16 index,
void *data, u16 size, int timeout);
@@ -77,23 +77,26 @@
void *buf, unsigned int length, unsigned int *act_len);
extern int usb_stor_bulk_transfer_sg(struct us_data *us, unsigned int pipe,
void *buf, unsigned int length, int use_sg, int *residual);
-extern int usb_stor_bulk_srb(struct us_data* us, unsigned int pipe,
- struct scsi_cmnd* srb);
+extern int usb_stor_bulk_srb(struct us_data *us, unsigned int pipe,
+ struct scsi_cmnd *srb);
extern int usb_stor_port_reset(struct us_data *us);
/* Protocol handling routines */
enum xfer_buf_dir {TO_XFER_BUF, FROM_XFER_BUF};
-extern unsigned int usb_stor_access_xfer_buf(struct us_data*, unsigned char *buffer,
- unsigned int buflen, struct scsi_cmnd *srb, struct scatterlist **,
- unsigned int *offset, enum xfer_buf_dir dir);
-extern void usb_stor_set_xfer_buf(struct us_data*, unsigned char *buffer, unsigned int buflen, struct scsi_cmnd *srb,
+extern unsigned int usb_stor_access_xfer_buf(struct us_data*,
+ unsigned char *buffer, unsigned int buflen, struct scsi_cmnd *srb,
+ struct scatterlist **, unsigned int *offset, enum xfer_buf_dir dir);
+extern void usb_stor_set_xfer_buf(struct us_data*, unsigned char *buffer,
+ unsigned int buflen, struct scsi_cmnd *srb,
unsigned int dir);
-// ENE scsi function
-extern void ENE_stor_invoke_transport(struct scsi_cmnd *, struct us_data*);
-extern int ENE_InitMedia(struct us_data*);
-extern int ENE_MSInit(struct us_data*);
-extern int ENE_SMInit(struct us_data*);
+/*
+ * ENE scsi function
+ */
+extern void ENE_stor_invoke_transport(struct scsi_cmnd *, struct us_data *);
+extern int ENE_InitMedia(struct us_data *);
+extern int ENE_MSInit(struct us_data *);
+extern int ENE_SMInit(struct us_data *);
extern int ENE_SendScsiCmd(struct us_data*, BYTE, void*, int);
extern int ENE_LoadBinCode(struct us_data*, BYTE);
extern int ENE_Read_BYTE(struct us_data*, WORD index, void *buf);
@@ -101,41 +104,54 @@
extern int ENE_Write_Data(struct us_data*, void *buf, unsigned int length);
extern void BuildSenseBuffer(struct scsi_cmnd *, int);
-// ENE scsi function
+/*
+ * ENE scsi function
+ */
extern int MS_SCSIIrp(struct us_data *us, struct scsi_cmnd *srb);
extern int SM_SCSIIrp(struct us_data *us, struct scsi_cmnd *srb);
-// ENE MS function
-extern int MS_CardInit(struct us_data *us);
+/*
+ * ENE MS function
+ */
+extern int MS_CardInit(struct us_data *us);
extern void MS_LibFreeAllocatedArea(struct us_data *us);
extern void MS_LibFreeWriteBuf(struct us_data *us);
extern int MS_LibFreeLogicalMap(struct us_data *us);
-extern int MS_LibForceSetLogicalPair(struct us_data *us, WORD logblk, WORD phyblk);
-extern int MS_ReaderReadPage(struct us_data *us, DWORD PhyBlockAddr, BYTE PageNum, DWORD *PageBuf, MS_LibTypeExtdat *ExtraDat);
-extern int MS_ReaderCopyBlock(struct us_data *us, WORD oldphy, WORD newphy, WORD PhyBlockAddr, BYTE PageNum, PBYTE buf, WORD len);
+extern int MS_LibForceSetLogicalPair(struct us_data *us, WORD logblk,
+ WORD phyblk);
+extern int MS_ReaderReadPage(struct us_data *us, DWORD PhyBlockAddr,
+ BYTE PageNum, DWORD *PageBuf,
+ MS_LibTypeExtdat *ExtraDat);
+extern int MS_ReaderCopyBlock(struct us_data *us, WORD oldphy,
+ WORD newphy, WORD PhyBlockAddr,
+ BYTE PageNum, PBYTE buf, WORD len);
extern int MS_ReaderEraseBlock(struct us_data *us, DWORD PhyBlockAddr);
-extern int MS_LibProcessBootBlock(struct us_data *us, WORD PhyBlock, BYTE *PageData);
+extern int MS_LibProcessBootBlock(struct us_data *us, WORD PhyBlock,
+ BYTE *PageData);
extern int MS_LibAllocLogicalMap(struct us_data *us);
extern int MS_LibSetBootBlockMark(struct us_data *us, WORD phyblk);
-extern int MS_LibSetLogicalBlockMark(struct us_data *us, WORD phyblk, WORD mark);
+extern int MS_LibSetLogicalBlockMark(struct us_data *us, WORD phyblk,
+ WORD mark);
extern int MS_LibSetInitialErrorBlock(struct us_data *us, WORD phyblk);
extern int MS_LibScanLogicalBlockNumber(struct us_data *us, WORD phyblk);
extern int MS_LibAllocWriteBuf(struct us_data *us);
void MS_LibClearWriteBuf(struct us_data *us);
-void MS_LibPhy2LogRange(WORD PhyBlock, WORD *LogStart, WORD *LogEnde);
-extern int MS_LibReadExtra(struct us_data *us, DWORD PhyBlock, BYTE PageNum, MS_LibTypeExtdat *ExtraDat);
-extern int MS_LibReadExtraBlock(struct us_data *us, DWORD PhyBlock, BYTE PageNum, BYTE blen, void *buf);
+void MS_LibPhy2LogRange(WORD PhyBlock, WORD *LogStart,
+ WORD *LogEnde);
+extern int MS_LibReadExtra(struct us_data *us, DWORD PhyBlock,
+ BYTE PageNum, MS_LibTypeExtdat *ExtraDat);
+extern int MS_LibReadExtraBlock(struct us_data *us, DWORD PhyBlock,
+ BYTE PageNum, BYTE blen, void *buf);
extern int MS_LibSetAcquiredErrorBlock(struct us_data *us, WORD phyblk);
extern int MS_LibErasePhyBlock(struct us_data *us, WORD phyblk);
extern int MS_LibErrorPhyBlock(struct us_data *us, WORD phyblk);
-extern int MS_LibOverwriteExtra(struct us_data *us, DWORD PhyBlockAddr, BYTE PageNum, BYTE OverwriteFlag);
-extern int MS_LibSetLogicalPair(struct us_data *us, WORD logblk, WORD phyblk);
+extern int MS_LibOverwriteExtra(struct us_data *us, DWORD PhyBlockAddr,
+ BYTE PageNum, BYTE OverwriteFlag);
+extern int MS_LibSetLogicalPair(struct us_data *us,
+ WORD logblk, WORD phyblk);
extern int MS_LibCheckDisableBlock(struct us_data *us, WORD PhyBlock);
extern int MS_CountFreeBlock(struct us_data *us, WORD PhyBlock);
extern int MS_LibSearchBlockFromLogical(struct us_data *us, WORD logblk);
extern int MS_LibSearchBlockFromPhysical(struct us_data *us, WORD phyblk);
-// ENE SM function
-extern int SM_FreeMem(void);
-
#endif
diff --git a/drivers/staging/keucr/usb.c b/drivers/staging/keucr/usb.c
index 8c2332e..d8c5c62 100644
--- a/drivers/staging/keucr/usb.c
+++ b/drivers/staging/keucr/usb.c
@@ -14,6 +14,7 @@
#include "usb.h"
#include "scsiglue.h"
+#include "smil.h"
#include "transport.h"
/* Some informational data */
@@ -34,10 +35,10 @@
#ifdef CONFIG_PM
-int eucr_suspend(struct usb_interface *iface, pm_message_t message)
+static int eucr_suspend(struct usb_interface *iface, pm_message_t message)
{
struct us_data *us = usb_get_intfdata(iface);
- printk("--- eucr_suspend ---\n");
+ pr_info("--- eucr_suspend ---\n");
/* Wait until no command is running */
mutex_lock(&us->dev_mutex);
@@ -55,12 +56,12 @@
}
//EXPORT_SYMBOL_GPL(eucr_suspend);
-int eucr_resume(struct usb_interface *iface)
+static int eucr_resume(struct usb_interface *iface)
{
BYTE tmp = 0;
struct us_data *us = usb_get_intfdata(iface);
- printk("--- eucr_resume---\n");
+ pr_info("--- eucr_resume---\n");
mutex_lock(&us->dev_mutex);
//US_DEBUGP("%s\n", __func__);
@@ -80,12 +81,12 @@
return 0;
}
//EXPORT_SYMBOL_GPL(eucr_resume);
-int eucr_reset_resume(struct usb_interface *iface)
+static int eucr_reset_resume(struct usb_interface *iface)
{
BYTE tmp = 0;
struct us_data *us = usb_get_intfdata(iface);
- printk("--- eucr_reset_resume---\n");
+ pr_info("--- eucr_reset_resume---\n");
//US_DEBUGP("%s\n", __func__);
/* Report the reset to the SCSI core */
@@ -116,7 +117,7 @@
{
struct us_data *us = usb_get_intfdata(iface);
- printk("usb --- eucr_pre_reset\n");
+ pr_info("usb --- eucr_pre_reset\n");
/* Make sure no command runs during the reset */
mutex_lock(&us->dev_mutex);
@@ -128,7 +129,7 @@
{
struct us_data *us = usb_get_intfdata(iface);
- printk("usb --- eucr_post_reset\n");
+ pr_info("usb --- eucr_post_reset\n");
/* Report the reset to the SCSI core */
usb_stor_report_bus_reset(us);
@@ -140,7 +141,7 @@
//----- fill_inquiry_response() ---------------------
void fill_inquiry_response(struct us_data *us, unsigned char *data, unsigned int data_len)
{
- printk("usb --- fill_inquiry_response\n");
+ pr_info("usb --- fill_inquiry_response\n");
if (data_len<36) // You lose.
return;
@@ -171,7 +172,7 @@
struct us_data *us = (struct us_data *)__us;
struct Scsi_Host *host = us_to_host(us);
- printk("usb --- usb_stor_control_thread\n");
+ pr_info("usb --- usb_stor_control_thread\n");
for(;;)
{
if (wait_for_completion_interruptible(&us->cmnd_ready))
@@ -242,7 +243,7 @@
else
{
SkipForAbort:
- printk("scsi command aborted\n");
+ pr_info("scsi command aborted\n");
}
if (test_bit(US_FLIDX_TIMED_OUT, &us->dflags))
@@ -277,7 +278,7 @@
//----- associate_dev() ---------------------
static int associate_dev(struct us_data *us, struct usb_interface *intf)
{
- printk("usb --- associate_dev\n");
+ pr_info("usb --- associate_dev\n");
/* Fill in the device-related fields */
us->pusb_dev = interface_to_usbdev(intf);
@@ -291,21 +292,21 @@
us->cr = usb_alloc_coherent(us->pusb_dev, sizeof(*us->cr), GFP_KERNEL, &us->cr_dma);
if (!us->cr)
{
- printk("usb_ctrlrequest allocation failed\n");
+ pr_info("usb_ctrlrequest allocation failed\n");
return -ENOMEM;
}
us->iobuf = usb_alloc_coherent(us->pusb_dev, US_IOBUF_SIZE, GFP_KERNEL, &us->iobuf_dma);
if (!us->iobuf)
{
- printk("I/O buffer allocation failed\n");
+ pr_info("I/O buffer allocation failed\n");
return -ENOMEM;
}
us->sensebuf = kmalloc(US_SENSE_SIZE, GFP_KERNEL);
if (!us->sensebuf)
{
- printk("Sense buffer allocation failed\n");
+ pr_info("Sense buffer allocation failed\n");
return -ENOMEM;
}
return 0;
@@ -317,7 +318,7 @@
struct usb_device *dev = us->pusb_dev;
struct usb_interface_descriptor *idesc = &us->pusb_intf->cur_altsetting->desc;
- printk("usb --- get_device_info\n");
+ pr_info("usb --- get_device_info\n");
us->subclass = idesc->bInterfaceSubClass;
us->protocol = idesc->bInterfaceProtocol;
@@ -326,7 +327,7 @@
if (us->fflags & US_FL_IGNORE_DEVICE)
{
- printk("device ignored\n");
+ pr_info("device ignored\n");
return -ENODEV;
}
@@ -339,7 +340,7 @@
//----- get_transport() ---------------------
static int get_transport(struct us_data *us)
{
- printk("usb --- get_transport\n");
+ pr_info("usb --- get_transport\n");
switch (us->protocol) {
case USB_PR_BULK:
us->transport_name = "Bulk";
@@ -350,7 +351,7 @@
default:
return -EIO;
}
- //printk("Transport: %s\n", us->transport_name);
+ /* pr_info("Transport: %s\n", us->transport_name); */
/* fix for single-lun devices */
if (us->fflags & US_FL_SINGLE_LUN)
@@ -361,9 +362,11 @@
//----- get_protocol() ---------------------
static int get_protocol(struct us_data *us)
{
- printk("usb --- get_protocol\n");
- printk("us->pusb_dev->descriptor.idVendor = %x\n", us->pusb_dev->descriptor.idVendor);
- printk("us->pusb_dev->descriptor.idProduct = %x\n", us->pusb_dev->descriptor.idProduct);
+ pr_info("usb --- get_protocol\n");
+ pr_info("us->pusb_dev->descriptor.idVendor = %x\n",
+ us->pusb_dev->descriptor.idVendor);
+ pr_info("us->pusb_dev->descriptor.idProduct = %x\n",
+ us->pusb_dev->descriptor.idProduct);
switch (us->subclass) {
case USB_SC_SCSI:
us->protocol_name = "Transparent SCSI";
@@ -376,7 +379,7 @@
default:
return -EIO;
}
- //printk("Protocol: %s\n", us->protocol_name);
+ /* pr_info("Protocol: %s\n", us->protocol_name); */
return 0;
}
@@ -390,7 +393,7 @@
struct usb_endpoint_descriptor *ep_out = NULL;
struct usb_endpoint_descriptor *ep_int = NULL;
- printk("usb --- get_pipes\n");
+ pr_info("usb --- get_pipes\n");
for (i = 0; i < altsetting->desc.bNumEndpoints; i++)
{
@@ -418,7 +421,7 @@
if (!ep_in || !ep_out || (us->protocol == USB_PR_CBI && !ep_int))
{
- printk("Endpoint sanity check failed! Rejecting dev.\n");
+ pr_info("Endpoint sanity check failed! Rejecting dev.\n");
return -EIO;
}
@@ -440,11 +443,11 @@
{
struct task_struct *th;
- printk("usb --- usb_stor_acquire_resources\n");
+ pr_info("usb --- usb_stor_acquire_resources\n");
us->current_urb = usb_alloc_urb(0, GFP_KERNEL);
if (!us->current_urb)
{
- printk("URB allocation failed\n");
+ pr_info("URB allocation failed\n");
return -ENOMEM;
}
@@ -452,7 +455,7 @@
th = kthread_run(usb_stor_control_thread, us, "eucr-storage");
if (IS_ERR(th))
{
- printk("Unable to start control thread\n");
+ pr_info("Unable to start control thread\n");
return PTR_ERR(th);
}
us->ctl_thread = th;
@@ -463,7 +466,7 @@
//----- usb_stor_release_resources() ---------------------
static void usb_stor_release_resources(struct us_data *us)
{
- printk("usb --- usb_stor_release_resources\n");
+ pr_info("usb --- usb_stor_release_resources\n");
SM_FreeMem();
@@ -474,7 +477,7 @@
/* Call the destructor routine, if it exists */
if (us->extra_destructor)
{
- printk("-- calling extra_destructor()\n");
+ pr_info("-- calling extra_destructor()\n");
us->extra_destructor(us->extra);
}
@@ -486,7 +489,7 @@
//----- dissociate_dev() ---------------------
static void dissociate_dev(struct us_data *us)
{
- printk("usb --- dissociate_dev\n");
+ pr_info("usb --- dissociate_dev\n");
kfree(us->sensebuf);
@@ -505,7 +508,7 @@
{
struct Scsi_Host *host = us_to_host(us);
- printk("usb --- quiesce_and_remove_host\n");
+ pr_info("usb --- quiesce_and_remove_host\n");
/* If the device is really gone, cut short reset delays */
if (us->pusb_dev->state == USB_STATE_NOTATTACHED)
@@ -535,7 +538,7 @@
//----- release_everything() ---------------------
static void release_everything(struct us_data *us)
{
- printk("usb --- release_everything\n");
+ pr_info("usb --- release_everything\n");
usb_stor_release_resources(us);
dissociate_dev(us);
@@ -547,8 +550,8 @@
{
struct us_data *us = (struct us_data *)__us;
- printk("usb --- usb_stor_scan_thread\n");
- printk("EUCR : device found at %d\n", us->pusb_dev->devnum);
+ pr_info("usb --- usb_stor_scan_thread\n");
+ pr_info("EUCR : device found at %d\n", us->pusb_dev->devnum);
set_freezable();
/* Wait for the timeout to expire or for a disconnect */
@@ -569,7 +572,7 @@
mutex_unlock(&us->dev_mutex);
}
scsi_scan_host(us_to_host(us));
- printk("EUCR : device scan complete\n");
+ pr_info("EUCR : device scan complete\n");
}
complete_and_exit(&us->scanning_done, 0);
}
@@ -583,12 +586,12 @@
BYTE MiscReg03 = 0;
struct task_struct *th;
- printk("usb --- eucr_probe\n");
+ pr_info("usb --- eucr_probe\n");
host = scsi_host_alloc(&usb_stor_host_template, sizeof(*us));
if (!host)
{
- printk("Unable to allocate the scsi host\n");
+ pr_info("Unable to allocate the scsi host\n");
return -ENOMEM;
}
@@ -631,7 +634,7 @@
result = scsi_add_host(host, &intf->dev);
if (result)
{
- printk("Unable to add the scsi host\n");
+ pr_info("Unable to add the scsi host\n");
goto BadDevice;
}
@@ -639,7 +642,7 @@
th = kthread_create(usb_stor_scan_thread, us, "eucr-stor-scan");
if (IS_ERR(th))
{
- printk("Unable to start the device-scanning thread\n");
+ pr_info("Unable to start the device-scanning thread\n");
complete(&us->scanning_done);
quiesce_and_remove_host(us);
result = PTR_ERR(th);
@@ -658,7 +661,7 @@
if (!(MiscReg03 & 0x02)) {
result = -ENODEV;
quiesce_and_remove_host(us);
- printk(KERN_NOTICE "keucr: The driver only supports SM/MS card.\
+ pr_info("keucr: The driver only supports SM/MS card.\
To use SD card, \
please build driver/usb/storage/ums-eneub6250.ko\n");
goto BadDevice;
@@ -668,7 +671,7 @@
/* We come here if there are any problems */
BadDevice:
- printk("usb --- eucr_probe failed\n");
+ pr_info("usb --- eucr_probe failed\n");
release_everything(us);
return result;
}
@@ -678,7 +681,7 @@
{
struct us_data *us = usb_get_intfdata(intf);
- printk("usb --- eucr_disconnect\n");
+ pr_info("usb --- eucr_disconnect\n");
quiesce_and_remove_host(us);
release_everything(us);
}
@@ -705,11 +708,11 @@
static int __init usb_stor_init(void)
{
int retval;
- printk("usb --- usb_stor_init start\n");
+ pr_info("usb --- usb_stor_init start\n");
retval = usb_register(&usb_storage_driver);
if (retval == 0)
- printk("ENE USB Mass Storage support registered.\n");
+ pr_info("ENE USB Mass Storage support registered.\n");
return retval;
}
@@ -717,7 +720,7 @@
//----- usb_stor_exit() ---------------------
static void __exit usb_stor_exit(void)
{
- printk("usb --- usb_stor_exit\n");
+ pr_info("usb --- usb_stor_exit\n");
usb_deregister(&usb_storage_driver) ;
}
diff --git a/drivers/staging/line6/driver.c b/drivers/staging/line6/driver.c
index ea9209d..851b762 100644
--- a/drivers/staging/line6/driver.c
+++ b/drivers/staging/line6/driver.c
@@ -1094,8 +1094,6 @@
err_destruct:
line6_destruct(interface);
err_put:
- usb_put_intf(interface);
- usb_put_dev(usbdev);
return ret;
}
diff --git a/drivers/staging/lirc/lirc_parallel.c b/drivers/staging/lirc/lirc_parallel.c
index 832522c..50724c4 100644
--- a/drivers/staging/lirc/lirc_parallel.c
+++ b/drivers/staging/lirc/lirc_parallel.c
@@ -568,17 +568,17 @@
}
static struct lirc_driver driver = {
- .name = LIRC_DRIVER_NAME,
- .minor = -1,
- .code_length = 1,
- .sample_rate = 0,
- .data = NULL,
- .add_to_buf = NULL,
- .set_use_inc = set_use_inc,
- .set_use_dec = set_use_dec,
- .fops = &lirc_fops,
- .dev = NULL,
- .owner = THIS_MODULE,
+ .name = LIRC_DRIVER_NAME,
+ .minor = -1,
+ .code_length = 1,
+ .sample_rate = 0,
+ .data = NULL,
+ .add_to_buf = NULL,
+ .set_use_inc = set_use_inc,
+ .set_use_dec = set_use_dec,
+ .fops = &lirc_fops,
+ .dev = NULL,
+ .owner = THIS_MODULE,
};
static struct platform_device *lirc_parallel_dev;
@@ -594,7 +594,7 @@
}
static int lirc_parallel_suspend(struct platform_device *dev,
- pm_message_t state)
+ pm_message_t state)
{
return 0;
}
@@ -647,7 +647,8 @@
result = platform_driver_register(&lirc_parallel_driver);
if (result) {
- printk("platform_driver_register returned %d\n", result);
+ printk(KERN_NOTICE "platform_driver_register"
+ " returned %d\n", result);
return result;
}
diff --git a/drivers/staging/lirc/lirc_sasem.c b/drivers/staging/lirc/lirc_sasem.c
index 63a438d..7080cde 100644
--- a/drivers/staging/lirc/lirc_sasem.c
+++ b/drivers/staging/lirc/lirc_sasem.c
@@ -570,6 +570,7 @@
unsigned char *buf = urb->transfer_buffer;
long ms;
struct timeval tv;
+ int i;
if (len != 8) {
printk(KERN_WARNING "%s: invalid incoming packet size (%d)\n",
@@ -577,12 +578,12 @@
return;
}
-#ifdef DEBUG
- int i;
- for (i = 0; i < 8; ++i)
- printk(KERN_INFO "%02x ", buf[i]);
- printk(KERN_INFO "\n");
-#endif
+ if (debug) {
+ printk(KERN_INFO "Incoming data: ");
+ for (i = 0; i < 8; ++i)
+ printk(KERN_CONT "%02x ", buf[i]);
+ printk(KERN_CONT "\n");
+ }
/*
* Lirc could deal with the repeat code, but we really need to block it
diff --git a/drivers/staging/lirc/lirc_serial.c b/drivers/staging/lirc/lirc_serial.c
index 1c3099b..4a3cca0 100644
--- a/drivers/staging/lirc/lirc_serial.c
+++ b/drivers/staging/lirc/lirc_serial.c
@@ -919,7 +919,7 @@
default:
dprintk("Interrupt %d, port %04x obtained\n", irq, io);
break;
- };
+ }
spin_lock_irqsave(&hardware[type].lock, flags);
diff --git a/drivers/staging/lirc/lirc_sir.c b/drivers/staging/lirc/lirc_sir.c
index 76be7b8..a7b46f2 100644
--- a/drivers/staging/lirc/lirc_sir.c
+++ b/drivers/staging/lirc/lirc_sir.c
@@ -143,9 +143,9 @@
#endif
#ifndef LIRC_PORT
/* for external dongles, default to com1 */
-#if defined(LIRC_SIR_ACTISYS_ACT200L) || \
- defined(LIRC_SIR_ACTISYS_ACT220L) || \
- defined(LIRC_SIR_TEKRAM)
+#if defined(LIRC_SIR_ACTISYS_ACT200L) || \
+ defined(LIRC_SIR_ACTISYS_ACT220L) || \
+ defined(LIRC_SIR_TEKRAM)
#define LIRC_PORT 0x3f8
#else
/* onboard sir ports are typically com3 */
@@ -467,7 +467,7 @@
static int set_use_inc(void *data)
{
- return 0;
+ return 0;
}
static void set_use_dec(void *data)
@@ -475,17 +475,17 @@
}
static struct lirc_driver driver = {
- .name = LIRC_DRIVER_NAME,
- .minor = -1,
- .code_length = 1,
- .sample_rate = 0,
- .data = NULL,
- .add_to_buf = NULL,
- .set_use_inc = set_use_inc,
- .set_use_dec = set_use_dec,
- .fops = &lirc_fops,
- .dev = NULL,
- .owner = THIS_MODULE,
+ .name = LIRC_DRIVER_NAME,
+ .minor = -1,
+ .code_length = 1,
+ .sample_rate = 0,
+ .data = NULL,
+ .add_to_buf = NULL,
+ .set_use_inc = set_use_inc,
+ .set_use_dec = set_use_dec,
+ .fops = &lirc_fops,
+ .dev = NULL,
+ .owner = THIS_MODULE,
};
diff --git a/drivers/staging/mei/Kconfig b/drivers/staging/mei/Kconfig
new file mode 100644
index 0000000..3f3f170
--- /dev/null
+++ b/drivers/staging/mei/Kconfig
@@ -0,0 +1,28 @@
+config INTEL_MEI
+ tristate "Intel Management Engine Interface (Intel MEI)"
+ depends on X86 && PCI && EXPERIMENTAL
+ help
+ The Intel Management Engine (Intel ME) provides Manageability,
+ Security and Media services for system containing Intel chipsets.
+ if selected /dev/mei misc device will be created.
+
+ Supported Chipsets are:
+ 7 Series Chipset Family
+ 6 Series Chipset Family
+ 5 Series Chipset Family
+ 4 Series Chipset Family
+ Mobile 4 Series Chipset Family
+ ICH9
+ 82946GZ/GL
+ 82G35 Express
+ 82Q963/Q965
+ 82P965/G965
+ Mobile PM965/GM965
+ Mobile GME965/GLE960
+ 82Q35 Express
+ 82G33/G31/P35/P31 Express
+ 82Q33 Express
+ 82X38/X48 Express
+
+ For more information see
+ <http://software.intel.com/en-us/manageability/>
diff --git a/drivers/staging/mei/Makefile b/drivers/staging/mei/Makefile
new file mode 100644
index 0000000..57168db
--- /dev/null
+++ b/drivers/staging/mei/Makefile
@@ -0,0 +1,11 @@
+#
+# Makefile - Intel Management Engine Interface (Intel MEI) Linux driver
+# Copyright (c) 2010-2011, Intel Corporation.
+#
+obj-$(CONFIG_INTEL_MEI) += mei.o
+mei-objs := init.o
+mei-objs += interrupt.o
+mei-objs += interface.o
+mei-objs += iorw.o
+mei-objs += main.o
+mei-objs += wd.o
diff --git a/drivers/staging/mei/TODO b/drivers/staging/mei/TODO
new file mode 100644
index 0000000..3b6a667
--- /dev/null
+++ b/drivers/staging/mei/TODO
@@ -0,0 +1,17 @@
+TODO:
+ - Create in-kernel Client API. Examples of in-kernel clients are watchdog and AMTHI.
+ - ME Watchdog Driver to expose standard Linux watchdog interface
+ - Rewrite AMTHI to use in-kernel client interface
+ - Cleanup init and probe functions
+ - Review BUG/BUG_ON usage
+ - Cleanup and reorganize header files
+ - Rewrite client data structure
+ - Make state machine more readable
+ - Add mei.txt with driver explanation and it's driver
+ - Fix Kconfig
+ - Cleanup and split the timer function
+Upon Unstaging:
+ - move mei.h to include/linux/mei.h
+ - Documentation/ioctl/ioctl-number.txt
+ - drop mei_version.h
+ - Updated MAINTAINERS
diff --git a/drivers/staging/mei/hw.h b/drivers/staging/mei/hw.h
new file mode 100644
index 0000000..9b9008c
--- /dev/null
+++ b/drivers/staging/mei/hw.h
@@ -0,0 +1,333 @@
+/*
+ *
+ * Intel Management Engine Interface (Intel MEI) Linux driver
+ * Copyright (c) 2003-2011, Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#ifndef _MEI_HW_TYPES_H_
+#define _MEI_HW_TYPES_H_
+
+#include <linux/uuid.h>
+
+/*
+ * Timeouts
+ */
+#define MEI_INTEROP_TIMEOUT (HZ * 7)
+#define MEI_CONNECT_TIMEOUT 3 /* at least 2 seconds */
+
+#define CONNECT_TIMEOUT 15 /* HPS definition */
+#define INIT_CLIENTS_TIMEOUT 15 /* HPS definition */
+
+#define IAMTHIF_STALL_TIMER 12 /* seconds */
+#define IAMTHIF_READ_TIMER 10000 /* ms */
+
+/*
+ * Internal Clients Number
+ */
+#define MEI_WD_HOST_CLIENT_ID 1
+#define MEI_IAMTHIF_HOST_CLIENT_ID 2
+
+/*
+ * MEI device IDs
+ */
+#define MEI_DEV_ID_82946GZ 0x2974 /* 82946GZ/GL */
+#define MEI_DEV_ID_82G35 0x2984 /* 82G35 Express */
+#define MEI_DEV_ID_82Q965 0x2994 /* 82Q963/Q965 */
+#define MEI_DEV_ID_82G965 0x29A4 /* 82P965/G965 */
+
+#define MEI_DEV_ID_82GM965 0x2A04 /* Mobile PM965/GM965 */
+#define MEI_DEV_ID_82GME965 0x2A14 /* Mobile GME965/GLE960 */
+
+#define MEI_DEV_ID_ICH9_82Q35 0x29B4 /* 82Q35 Express */
+#define MEI_DEV_ID_ICH9_82G33 0x29C4 /* 82G33/G31/P35/P31 Express */
+#define MEI_DEV_ID_ICH9_82Q33 0x29D4 /* 82Q33 Express */
+#define MEI_DEV_ID_ICH9_82X38 0x29E4 /* 82X38/X48 Express */
+#define MEI_DEV_ID_ICH9_3200 0x29F4 /* 3200/3210 Server */
+
+#define MEI_DEV_ID_ICH9_6 0x28B4 /* Bearlake */
+#define MEI_DEV_ID_ICH9_7 0x28C4 /* Bearlake */
+#define MEI_DEV_ID_ICH9_8 0x28D4 /* Bearlake */
+#define MEI_DEV_ID_ICH9_9 0x28E4 /* Bearlake */
+#define MEI_DEV_ID_ICH9_10 0x28F4 /* Bearlake */
+
+#define MEI_DEV_ID_ICH9M_1 0x2A44 /* Cantiga */
+#define MEI_DEV_ID_ICH9M_2 0x2A54 /* Cantiga */
+#define MEI_DEV_ID_ICH9M_3 0x2A64 /* Cantiga */
+#define MEI_DEV_ID_ICH9M_4 0x2A74 /* Cantiga */
+
+#define MEI_DEV_ID_ICH10_1 0x2E04 /* Eaglelake */
+#define MEI_DEV_ID_ICH10_2 0x2E14 /* Eaglelake */
+#define MEI_DEV_ID_ICH10_3 0x2E24 /* Eaglelake */
+#define MEI_DEV_ID_ICH10_4 0x2E34 /* Eaglelake */
+
+#define MEI_DEV_ID_IBXPK_1 0x3B64 /* Calpella */
+#define MEI_DEV_ID_IBXPK_2 0x3B65 /* Calpella */
+
+#define MEI_DEV_ID_CPT_1 0x1C3A /* Cougerpoint */
+#define MEI_DEV_ID_PBG_1 0x1D3A /* PBG */
+
+#define MEI_DEV_ID_PPT_1 0x1E3A /* Pantherpoint PPT */
+#define MEI_DEV_ID_PPT_2 0x1CBA /* Pantherpoint PPT */
+#define MEI_DEV_ID_PPT_3 0x1DBA /* Pantherpoint PPT */
+
+
+/*
+ * MEI HW Section
+ */
+
+/* MEI registers */
+/* H_CB_WW - Host Circular Buffer (CB) Write Window register */
+#define H_CB_WW 0
+/* H_CSR - Host Control Status register */
+#define H_CSR 4
+/* ME_CB_RW - ME Circular Buffer Read Window register (read only) */
+#define ME_CB_RW 8
+/* ME_CSR_HA - ME Control Status Host Access register (read only) */
+#define ME_CSR_HA 0xC
+
+
+/* register bits of H_CSR (Host Control Status register) */
+/* Host Circular Buffer Depth - maximum number of 32-bit entries in CB */
+#define H_CBD 0xFF000000
+/* Host Circular Buffer Write Pointer */
+#define H_CBWP 0x00FF0000
+/* Host Circular Buffer Read Pointer */
+#define H_CBRP 0x0000FF00
+/* Host Reset */
+#define H_RST 0x00000010
+/* Host Ready */
+#define H_RDY 0x00000008
+/* Host Interrupt Generate */
+#define H_IG 0x00000004
+/* Host Interrupt Status */
+#define H_IS 0x00000002
+/* Host Interrupt Enable */
+#define H_IE 0x00000001
+
+
+/* register bits of ME_CSR_HA (ME Control Status Host Access register) */
+/* ME CB (Circular Buffer) Depth HRA (Host Read Access) - host read only
+access to ME_CBD */
+#define ME_CBD_HRA 0xFF000000
+/* ME CB Write Pointer HRA - host read only access to ME_CBWP */
+#define ME_CBWP_HRA 0x00FF0000
+/* ME CB Read Pointer HRA - host read only access to ME_CBRP */
+#define ME_CBRP_HRA 0x0000FF00
+/* ME Reset HRA - host read only access to ME_RST */
+#define ME_RST_HRA 0x00000010
+/* ME Ready HRA - host read only access to ME_RDY */
+#define ME_RDY_HRA 0x00000008
+/* ME Interrupt Generate HRA - host read only access to ME_IG */
+#define ME_IG_HRA 0x00000004
+/* ME Interrupt Status HRA - host read only access to ME_IS */
+#define ME_IS_HRA 0x00000002
+/* ME Interrupt Enable HRA - host read only access to ME_IE */
+#define ME_IE_HRA 0x00000001
+
+/*
+ * MEI Version
+ */
+#define HBM_MINOR_VERSION 0
+#define HBM_MAJOR_VERSION 1
+#define HBM_TIMEOUT 1 /* 1 second */
+
+/*
+ * MEI Bus Message Command IDs
+ */
+#define HOST_START_REQ_CMD 0x01
+#define HOST_START_RES_CMD 0x81
+
+#define HOST_STOP_REQ_CMD 0x02
+#define HOST_STOP_RES_CMD 0x82
+
+#define ME_STOP_REQ_CMD 0x03
+
+#define HOST_ENUM_REQ_CMD 0x04
+#define HOST_ENUM_RES_CMD 0x84
+
+#define HOST_CLIENT_PROPERTIES_REQ_CMD 0x05
+#define HOST_CLIENT_PROPERTIES_RES_CMD 0x85
+
+#define CLIENT_CONNECT_REQ_CMD 0x06
+#define CLIENT_CONNECT_RES_CMD 0x86
+
+#define CLIENT_DISCONNECT_REQ_CMD 0x07
+#define CLIENT_DISCONNECT_RES_CMD 0x87
+
+#define MEI_FLOW_CONTROL_CMD 0x08
+
+/*
+ * MEI Stop Reason
+ * used by hbm_host_stop_request.reason
+ */
+enum mei_stop_reason_types {
+ DRIVER_STOP_REQUEST = 0x00,
+ DEVICE_D1_ENTRY = 0x01,
+ DEVICE_D2_ENTRY = 0x02,
+ DEVICE_D3_ENTRY = 0x03,
+ SYSTEM_S1_ENTRY = 0x04,
+ SYSTEM_S2_ENTRY = 0x05,
+ SYSTEM_S3_ENTRY = 0x06,
+ SYSTEM_S4_ENTRY = 0x07,
+ SYSTEM_S5_ENTRY = 0x08
+};
+
+/*
+ * Client Connect Status
+ * used by hbm_client_connect_response.status
+ */
+enum client_connect_status_types {
+ CCS_SUCCESS = 0x00,
+ CCS_NOT_FOUND = 0x01,
+ CCS_ALREADY_STARTED = 0x02,
+ CCS_OUT_OF_RESOURCES = 0x03,
+ CCS_MESSAGE_SMALL = 0x04
+};
+
+/*
+ * Client Disconnect Status
+ */
+enum client_disconnect_status_types {
+ CDS_SUCCESS = 0x00
+};
+
+/*
+ * MEI BUS Interface Section
+ */
+struct mei_msg_hdr {
+ u32 me_addr:8;
+ u32 host_addr:8;
+ u32 length:9;
+ u32 reserved:6;
+ u32 msg_complete:1;
+} __packed;
+
+
+struct hbm_cmd {
+ u8 cmd:7;
+ u8 is_response:1;
+} __packed;
+
+
+struct mei_bus_message {
+ struct hbm_cmd cmd;
+ u8 command_specific_data[];
+} __packed;
+
+struct hbm_version {
+ u8 minor_version;
+ u8 major_version;
+} __packed;
+
+struct hbm_host_version_request {
+ struct hbm_cmd cmd;
+ u8 reserved;
+ struct hbm_version host_version;
+} __packed;
+
+struct hbm_host_version_response {
+ struct hbm_cmd cmd;
+ int host_version_supported;
+ struct hbm_version me_max_version;
+} __packed;
+
+struct hbm_host_stop_request {
+ struct hbm_cmd cmd;
+ u8 reason;
+ u8 reserved[2];
+} __packed;
+
+struct hbm_host_stop_response {
+ struct hbm_cmd cmd;
+ u8 reserved[3];
+} __packed;
+
+struct hbm_me_stop_request {
+ struct hbm_cmd cmd;
+ u8 reason;
+ u8 reserved[2];
+} __packed;
+
+struct hbm_host_enum_request {
+ struct hbm_cmd cmd;
+ u8 reserved[3];
+} __packed;
+
+struct hbm_host_enum_response {
+ struct hbm_cmd cmd;
+ u8 reserved[3];
+ u8 valid_addresses[32];
+} __packed;
+
+struct mei_client_properties {
+ uuid_le protocol_name;
+ u8 protocol_version;
+ u8 max_number_of_connections;
+ u8 fixed_address;
+ u8 single_recv_buf;
+ u32 max_msg_length;
+} __packed;
+
+struct hbm_props_request {
+ struct hbm_cmd cmd;
+ u8 address;
+ u8 reserved[2];
+} __packed;
+
+
+struct hbm_props_response {
+ struct hbm_cmd cmd;
+ u8 address;
+ u8 status;
+ u8 reserved[1];
+ struct mei_client_properties client_properties;
+} __packed;
+
+struct hbm_client_connect_request {
+ struct hbm_cmd cmd;
+ u8 me_addr;
+ u8 host_addr;
+ u8 reserved;
+} __packed;
+
+struct hbm_client_connect_response {
+ struct hbm_cmd cmd;
+ u8 me_addr;
+ u8 host_addr;
+ u8 status;
+} __packed;
+
+struct hbm_client_disconnect_request {
+ struct hbm_cmd cmd;
+ u8 me_addr;
+ u8 host_addr;
+ u8 reserved[1];
+} __packed;
+
+#define MEI_FC_MESSAGE_RESERVED_LENGTH 5
+
+struct hbm_flow_control {
+ struct hbm_cmd cmd;
+ u8 me_addr;
+ u8 host_addr;
+ u8 reserved[MEI_FC_MESSAGE_RESERVED_LENGTH];
+} __packed;
+
+struct mei_me_client {
+ struct mei_client_properties props;
+ u8 client_id;
+ u8 mei_flow_ctrl_creds;
+} __packed;
+
+
+#endif
diff --git a/drivers/staging/mei/init.c b/drivers/staging/mei/init.c
new file mode 100644
index 0000000..2818851
--- /dev/null
+++ b/drivers/staging/mei/init.c
@@ -0,0 +1,770 @@
+/*
+ *
+ * Intel Management Engine Interface (Intel MEI) Linux driver
+ * Copyright (c) 2003-2011, Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#include <linux/pci.h>
+#include <linux/sched.h>
+#include <linux/wait.h>
+#include <linux/delay.h>
+
+#include "mei_dev.h"
+#include "hw.h"
+#include "interface.h"
+#include "mei.h"
+
+const uuid_le mei_amthi_guid = UUID_LE(0x12f80028, 0xb4b7, 0x4b2d, 0xac,
+ 0xa8, 0x46, 0xe0, 0xff, 0x65,
+ 0x81, 0x4c);
+
+/**
+ * mei_initialize_list - Sets up a queue list.
+ *
+ * @list: An instance of our list structure
+ * @dev: the device structure
+ */
+void mei_initialize_list(struct mei_io_list *list, struct mei_device *dev)
+{
+ /* initialize our queue list */
+ INIT_LIST_HEAD(&list->mei_cb.cb_list);
+ list->status = 0;
+ list->device_extension = dev;
+}
+
+/**
+ * mei_flush_queues - flushes queue lists belonging to cl.
+ *
+ * @dev: the device structure
+ * @cl: private data of the file object
+ */
+void mei_flush_queues(struct mei_device *dev, struct mei_cl *cl)
+{
+ int i;
+
+ if (!dev || !cl)
+ return;
+
+ for (i = 0; i < MEI_IO_LISTS_NUMBER; i++) {
+ dev_dbg(&dev->pdev->dev, "remove list entry belonging to cl\n");
+ mei_flush_list(dev->io_list_array[i], cl);
+ }
+}
+
+
+/**
+ * mei_flush_list - removes list entry belonging to cl.
+ *
+ * @list: An instance of our list structure
+ * @cl: private data of the file object
+ */
+void mei_flush_list(struct mei_io_list *list, struct mei_cl *cl)
+{
+ struct mei_cl *cl_tmp;
+ struct mei_cl_cb *cb_pos = NULL;
+ struct mei_cl_cb *cb_next = NULL;
+
+ if (!list || !cl)
+ return;
+
+ if (list->status != 0)
+ return;
+
+ if (list_empty(&list->mei_cb.cb_list))
+ return;
+
+ list_for_each_entry_safe(cb_pos, cb_next,
+ &list->mei_cb.cb_list, cb_list) {
+ if (cb_pos) {
+ cl_tmp = (struct mei_cl *)
+ cb_pos->file_private;
+ if (cl_tmp &&
+ mei_fe_same_id(cl, cl_tmp))
+ list_del(&cb_pos->cb_list);
+ }
+ }
+}
+
+/**
+ * mei_reset_iamthif_params - initializes mei device iamthif
+ *
+ * @dev: the device structure
+ */
+static void mei_reset_iamthif_params(struct mei_device *dev)
+{
+ /* reset iamthif parameters. */
+ dev->iamthif_current_cb = NULL;
+ dev->iamthif_msg_buf_size = 0;
+ dev->iamthif_msg_buf_index = 0;
+ dev->iamthif_canceled = 0;
+ dev->iamthif_ioctl = 0;
+ dev->iamthif_state = MEI_IAMTHIF_IDLE;
+ dev->iamthif_timer = 0;
+}
+
+/**
+ * init_mei_device - allocates and initializes the mei device structure
+ *
+ * @pdev: The pci device structure
+ *
+ * returns The mei_device_device pointer on success, NULL on failure.
+ */
+struct mei_device *init_mei_device(struct pci_dev *pdev)
+{
+ int i;
+ struct mei_device *dev;
+
+ dev = kzalloc(sizeof(struct mei_device), GFP_KERNEL);
+ if (!dev)
+ return NULL;
+
+ /* setup our list array */
+ dev->io_list_array[0] = &dev->read_list;
+ dev->io_list_array[1] = &dev->write_list;
+ dev->io_list_array[2] = &dev->write_waiting_list;
+ dev->io_list_array[3] = &dev->ctrl_wr_list;
+ dev->io_list_array[4] = &dev->ctrl_rd_list;
+ dev->io_list_array[5] = &dev->amthi_cmd_list;
+ dev->io_list_array[6] = &dev->amthi_read_complete_list;
+ INIT_LIST_HEAD(&dev->file_list);
+ INIT_LIST_HEAD(&dev->wd_cl.link);
+ INIT_LIST_HEAD(&dev->iamthif_cl.link);
+ mutex_init(&dev->device_lock);
+ init_waitqueue_head(&dev->wait_recvd_msg);
+ init_waitqueue_head(&dev->wait_stop_wd);
+ dev->mei_state = MEI_INITIALIZING;
+ dev->iamthif_state = MEI_IAMTHIF_IDLE;
+ for (i = 0; i < MEI_IO_LISTS_NUMBER; i++)
+ mei_initialize_list(dev->io_list_array[i], dev);
+ dev->pdev = pdev;
+ return dev;
+}
+
+/**
+ * mei_hw_init - initializes host and fw to start work.
+ *
+ * @dev: the device structure
+ *
+ * returns 0 on success, <0 on failure.
+ */
+int mei_hw_init(struct mei_device *dev)
+{
+ int err = 0;
+ int ret;
+
+ mutex_lock(&dev->device_lock);
+
+ dev->host_hw_state = mei_hcsr_read(dev);
+ dev->me_hw_state = mei_mecsr_read(dev);
+ dev_dbg(&dev->pdev->dev, "host_hw_state = 0x%08x, mestate = 0x%08x.\n",
+ dev->host_hw_state, dev->me_hw_state);
+
+ /* acknowledge interrupt and stop interupts */
+ if ((dev->host_hw_state & H_IS) == H_IS)
+ mei_reg_write(dev, H_CSR, dev->host_hw_state);
+
+ dev->recvd_msg = 0;
+ dev_dbg(&dev->pdev->dev, "reset in start the mei device.\n");
+
+ mei_reset(dev, 1);
+
+ dev_dbg(&dev->pdev->dev, "host_hw_state = 0x%08x, me_hw_state = 0x%08x.\n",
+ dev->host_hw_state, dev->me_hw_state);
+
+ /* wait for ME to turn on ME_RDY */
+ if (!dev->recvd_msg) {
+ mutex_unlock(&dev->device_lock);
+ err = wait_event_interruptible_timeout(dev->wait_recvd_msg,
+ dev->recvd_msg, MEI_INTEROP_TIMEOUT);
+ mutex_lock(&dev->device_lock);
+ }
+
+ if (!err && !dev->recvd_msg) {
+ dev->mei_state = MEI_DISABLED;
+ dev_dbg(&dev->pdev->dev,
+ "wait_event_interruptible_timeout failed"
+ "on wait for ME to turn on ME_RDY.\n");
+ ret = -ENODEV;
+ goto out;
+ }
+
+ if (!(((dev->host_hw_state & H_RDY) == H_RDY) &&
+ ((dev->me_hw_state & ME_RDY_HRA) == ME_RDY_HRA))) {
+ dev->mei_state = MEI_DISABLED;
+ dev_dbg(&dev->pdev->dev,
+ "host_hw_state = 0x%08x, me_hw_state = 0x%08x.\n",
+ dev->host_hw_state, dev->me_hw_state);
+
+ if (!(dev->host_hw_state & H_RDY) != H_RDY)
+ dev_dbg(&dev->pdev->dev, "host turn off H_RDY.\n");
+
+ if (!(dev->me_hw_state & ME_RDY_HRA) != ME_RDY_HRA)
+ dev_dbg(&dev->pdev->dev, "ME turn off ME_RDY.\n");
+
+ printk(KERN_ERR "mei: link layer initialization failed.\n");
+ ret = -ENODEV;
+ goto out;
+ }
+
+ if (dev->version.major_version != HBM_MAJOR_VERSION ||
+ dev->version.minor_version != HBM_MINOR_VERSION) {
+ dev_dbg(&dev->pdev->dev, "MEI start failed.\n");
+ ret = -ENODEV;
+ goto out;
+ }
+
+ dev->recvd_msg = 0;
+ dev_dbg(&dev->pdev->dev, "host_hw_state = 0x%08x, me_hw_state = 0x%08x.\n",
+ dev->host_hw_state, dev->me_hw_state);
+ dev_dbg(&dev->pdev->dev, "ME turn on ME_RDY and host turn on H_RDY.\n");
+ dev_dbg(&dev->pdev->dev, "link layer has been established.\n");
+ dev_dbg(&dev->pdev->dev, "MEI start success.\n");
+ ret = 0;
+
+out:
+ mutex_unlock(&dev->device_lock);
+ return ret;
+}
+
+/**
+ * mei_hw_reset - resets fw via mei csr register.
+ *
+ * @dev: the device structure
+ * @interrupts_enabled: if interrupt should be enabled after reset.
+ */
+static void mei_hw_reset(struct mei_device *dev, int interrupts_enabled)
+{
+ dev->host_hw_state |= (H_RST | H_IG);
+
+ if (interrupts_enabled)
+ mei_enable_interrupts(dev);
+ else
+ mei_disable_interrupts(dev);
+}
+
+/**
+ * mei_reset - resets host and fw.
+ *
+ * @dev: the device structure
+ * @interrupts_enabled: if interrupt should be enabled after reset.
+ */
+void mei_reset(struct mei_device *dev, int interrupts_enabled)
+{
+ struct mei_cl *cl_pos = NULL;
+ struct mei_cl *cl_next = NULL;
+ struct mei_cl_cb *cb_pos = NULL;
+ struct mei_cl_cb *cb_next = NULL;
+ bool unexpected;
+
+ if (dev->mei_state == MEI_RECOVERING_FROM_RESET) {
+ dev->need_reset = 1;
+ return;
+ }
+
+ unexpected = (dev->mei_state != MEI_INITIALIZING &&
+ dev->mei_state != MEI_DISABLED &&
+ dev->mei_state != MEI_POWER_DOWN &&
+ dev->mei_state != MEI_POWER_UP);
+
+ dev->host_hw_state = mei_hcsr_read(dev);
+
+ dev_dbg(&dev->pdev->dev, "before reset host_hw_state = 0x%08x.\n",
+ dev->host_hw_state);
+
+ mei_hw_reset(dev, interrupts_enabled);
+
+ dev->host_hw_state &= ~H_RST;
+ dev->host_hw_state |= H_IG;
+
+ mei_hcsr_set(dev);
+
+ dev_dbg(&dev->pdev->dev, "currently saved host_hw_state = 0x%08x.\n",
+ dev->host_hw_state);
+
+ dev->need_reset = 0;
+
+ if (dev->mei_state != MEI_INITIALIZING) {
+ if (dev->mei_state != MEI_DISABLED &&
+ dev->mei_state != MEI_POWER_DOWN)
+ dev->mei_state = MEI_RESETING;
+
+ list_for_each_entry_safe(cl_pos,
+ cl_next, &dev->file_list, link) {
+ cl_pos->state = MEI_FILE_DISCONNECTED;
+ cl_pos->mei_flow_ctrl_creds = 0;
+ cl_pos->read_cb = NULL;
+ cl_pos->timer_count = 0;
+ }
+ /* remove entry if already in list */
+ dev_dbg(&dev->pdev->dev, "list del iamthif and wd file list.\n");
+ mei_remove_client_from_file_list(dev,
+ dev->wd_cl.host_client_id);
+
+ mei_remove_client_from_file_list(dev,
+ dev->iamthif_cl.host_client_id);
+
+ mei_reset_iamthif_params(dev);
+ dev->wd_due_counter = 0;
+ dev->extra_write_index = 0;
+ }
+
+ dev->num_mei_me_clients = 0;
+ dev->rd_msg_hdr = 0;
+ dev->stop = 0;
+ dev->wd_pending = 0;
+
+ /* update the state of the registers after reset */
+ dev->host_hw_state = mei_hcsr_read(dev);
+ dev->me_hw_state = mei_mecsr_read(dev);
+
+ dev_dbg(&dev->pdev->dev, "after reset host_hw_state = 0x%08x, me_hw_state = 0x%08x.\n",
+ dev->host_hw_state, dev->me_hw_state);
+
+ if (unexpected)
+ dev_warn(&dev->pdev->dev, "unexpected reset.\n");
+
+ /* Wake up all readings so they can be interrupted */
+ list_for_each_entry_safe(cl_pos, cl_next, &dev->file_list, link) {
+ if (waitqueue_active(&cl_pos->rx_wait)) {
+ dev_dbg(&dev->pdev->dev, "Waking up client!\n");
+ wake_up_interruptible(&cl_pos->rx_wait);
+ }
+ }
+ /* remove all waiting requests */
+ if (dev->write_list.status == 0 &&
+ !list_empty(&dev->write_list.mei_cb.cb_list)) {
+ list_for_each_entry_safe(cb_pos, cb_next,
+ &dev->write_list.mei_cb.cb_list, cb_list) {
+ if (cb_pos) {
+ list_del(&cb_pos->cb_list);
+ mei_free_cb_private(cb_pos);
+ cb_pos = NULL;
+ }
+ }
+ }
+}
+
+
+
+/**
+ * host_start_message - mei host sends start message.
+ *
+ * @dev: the device structure
+ *
+ * returns none.
+ */
+void host_start_message(struct mei_device *dev)
+{
+ struct mei_msg_hdr *mei_hdr;
+ struct hbm_host_version_request *host_start_req;
+
+ /* host start message */
+ mei_hdr = (struct mei_msg_hdr *) &dev->wr_msg_buf[0];
+ mei_hdr->host_addr = 0;
+ mei_hdr->me_addr = 0;
+ mei_hdr->length = sizeof(struct hbm_host_version_request);
+ mei_hdr->msg_complete = 1;
+ mei_hdr->reserved = 0;
+
+ host_start_req =
+ (struct hbm_host_version_request *) &dev->wr_msg_buf[1];
+ memset(host_start_req, 0, sizeof(struct hbm_host_version_request));
+ host_start_req->cmd.cmd = HOST_START_REQ_CMD;
+ host_start_req->host_version.major_version = HBM_MAJOR_VERSION;
+ host_start_req->host_version.minor_version = HBM_MINOR_VERSION;
+ dev->recvd_msg = 0;
+ if (!mei_write_message(dev, mei_hdr,
+ (unsigned char *) (host_start_req),
+ mei_hdr->length)) {
+ dev_dbg(&dev->pdev->dev, "write send version message to FW fail.\n");
+ dev->mei_state = MEI_RESETING;
+ mei_reset(dev, 1);
+ }
+ dev->init_clients_state = MEI_START_MESSAGE;
+ dev->init_clients_timer = INIT_CLIENTS_TIMEOUT;
+ return ;
+}
+
+/**
+ * host_enum_clients_message - host sends enumeration client request message.
+ *
+ * @dev: the device structure
+ *
+ * returns none.
+ */
+void host_enum_clients_message(struct mei_device *dev)
+{
+ struct mei_msg_hdr *mei_hdr;
+ struct hbm_host_enum_request *host_enum_req;
+ mei_hdr = (struct mei_msg_hdr *) &dev->wr_msg_buf[0];
+ /* enumerate clients */
+ mei_hdr->host_addr = 0;
+ mei_hdr->me_addr = 0;
+ mei_hdr->length = sizeof(struct hbm_host_enum_request);
+ mei_hdr->msg_complete = 1;
+ mei_hdr->reserved = 0;
+
+ host_enum_req = (struct hbm_host_enum_request *) &dev->wr_msg_buf[1];
+ memset(host_enum_req, 0, sizeof(struct hbm_host_enum_request));
+ host_enum_req->cmd.cmd = HOST_ENUM_REQ_CMD;
+ if (!mei_write_message(dev, mei_hdr,
+ (unsigned char *) (host_enum_req),
+ mei_hdr->length)) {
+ dev->mei_state = MEI_RESETING;
+ dev_dbg(&dev->pdev->dev, "write send enumeration request message to FW fail.\n");
+ mei_reset(dev, 1);
+ }
+ dev->init_clients_state = MEI_ENUM_CLIENTS_MESSAGE;
+ dev->init_clients_timer = INIT_CLIENTS_TIMEOUT;
+ return ;
+}
+
+
+/**
+ * allocate_me_clients_storage - allocates storage for me clients
+ *
+ * @dev: the device structure
+ *
+ * returns none.
+ */
+void allocate_me_clients_storage(struct mei_device *dev)
+{
+ struct mei_me_client *clients;
+ int b;
+
+ /* count how many ME clients we have */
+ for_each_set_bit(b, dev->me_clients_map, MEI_CLIENTS_MAX)
+ dev->num_mei_me_clients++;
+
+ if (dev->num_mei_me_clients <= 0)
+ return ;
+
+
+ if (dev->me_clients != NULL) {
+ kfree(dev->me_clients);
+ dev->me_clients = NULL;
+ }
+ dev_dbg(&dev->pdev->dev, "memory allocation for ME clients size=%zd.\n",
+ dev->num_mei_me_clients * sizeof(struct mei_me_client));
+ /* allocate storage for ME clients representation */
+ clients = kcalloc(dev->num_mei_me_clients,
+ sizeof(struct mei_me_client), GFP_KERNEL);
+ if (!clients) {
+ dev_dbg(&dev->pdev->dev, "memory allocation for ME clients failed.\n");
+ dev->mei_state = MEI_RESETING;
+ mei_reset(dev, 1);
+ return ;
+ }
+ dev->me_clients = clients;
+ return ;
+}
+/**
+ * host_client_properties - reads properties for client
+ *
+ * @dev: the device structure
+ *
+ * returns none.
+ */
+void host_client_properties(struct mei_device *dev)
+{
+ struct mei_msg_hdr *mei_header;
+ struct hbm_props_request *host_cli_req;
+ int b;
+ u8 client_num = dev->me_client_presentation_num;
+
+ b = dev->me_client_index;
+ b = find_next_bit(dev->me_clients_map, MEI_CLIENTS_MAX, b);
+ if (b < MEI_CLIENTS_MAX) {
+ dev->me_clients[client_num].client_id = b;
+ dev->me_clients[client_num].mei_flow_ctrl_creds = 0;
+ mei_header = (struct mei_msg_hdr *)&dev->wr_msg_buf[0];
+ mei_header->host_addr = 0;
+ mei_header->me_addr = 0;
+ mei_header->length = sizeof(struct hbm_props_request);
+ mei_header->msg_complete = 1;
+ mei_header->reserved = 0;
+
+ host_cli_req = (struct hbm_props_request *)&dev->wr_msg_buf[1];
+
+ memset(host_cli_req, 0, sizeof(struct hbm_props_request));
+
+ host_cli_req->cmd.cmd = HOST_CLIENT_PROPERTIES_REQ_CMD;
+ host_cli_req->address = b;
+
+ if (!mei_write_message(dev, mei_header,
+ (unsigned char *)host_cli_req,
+ mei_header->length)) {
+ dev->mei_state = MEI_RESETING;
+ dev_dbg(&dev->pdev->dev, "write send enumeration request message to FW fail.\n");
+ mei_reset(dev, 1);
+ return;
+ }
+
+ dev->init_clients_timer = INIT_CLIENTS_TIMEOUT;
+ dev->me_client_index = b;
+ return;
+ }
+
+
+ /*
+ * Clear Map for indicating now ME clients
+ * with associated host client
+ */
+ bitmap_zero(dev->host_clients_map, MEI_CLIENTS_MAX);
+ dev->write_hang = -1;
+ dev->open_handle_count = 0;
+ bitmap_set(dev->host_clients_map, 0, 3);
+ dev->mei_state = MEI_ENABLED;
+
+ mei_wd_host_init(dev);
+ return;
+}
+
+/**
+ * mei_init_file_private - initializes private file structure.
+ *
+ * @priv: private file structure to be initialized
+ * @file: the file structure
+ */
+void mei_init_file_private(struct mei_cl *priv, struct mei_device *dev)
+{
+ memset(priv, 0, sizeof(struct mei_cl));
+ init_waitqueue_head(&priv->wait);
+ init_waitqueue_head(&priv->rx_wait);
+ init_waitqueue_head(&priv->tx_wait);
+ INIT_LIST_HEAD(&priv->link);
+ priv->reading_state = MEI_IDLE;
+ priv->writing_state = MEI_IDLE;
+ priv->dev = dev;
+}
+
+int mei_find_me_client_index(const struct mei_device *dev, uuid_le cuuid)
+{
+ int i, res = -1;
+
+ for (i = 0; i < dev->num_mei_me_clients; ++i)
+ if (uuid_le_cmp(cuuid,
+ dev->me_clients[i].props.protocol_name) == 0) {
+ res = i;
+ break;
+ }
+
+ return res;
+}
+
+
+/**
+ * mei_find_me_client_update_filext - searches for ME client guid
+ * sets client_id in mei_file_private if found
+ * @dev: the device structure
+ * @priv: private file structure to set client_id in
+ * @cguid: searched guid of ME client
+ * @client_id: id of host client to be set in file private structure
+ *
+ * returns ME client index
+ */
+u8 mei_find_me_client_update_filext(struct mei_device *dev, struct mei_cl *priv,
+ const uuid_le *cguid, u8 client_id)
+{
+ int i;
+
+ if (!dev || !priv || !cguid)
+ return 0;
+
+ /* check for valid client id */
+ i = mei_find_me_client_index(dev, *cguid);
+ if (i >= 0) {
+ priv->me_client_id = dev->me_clients[i].client_id;
+ priv->state = MEI_FILE_CONNECTING;
+ priv->host_client_id = client_id;
+
+ list_add_tail(&priv->link, &dev->file_list);
+ return (u8)i;
+ }
+
+ return 0;
+}
+
+/**
+ * host_init_iamthif - mei initialization iamthif client.
+ *
+ * @dev: the device structure
+ *
+ */
+void host_init_iamthif(struct mei_device *dev)
+{
+ u8 i;
+ unsigned char *msg_buf;
+
+ mei_init_file_private(&dev->iamthif_cl, dev);
+ dev->iamthif_cl.state = MEI_FILE_DISCONNECTED;
+
+ /* find ME amthi client */
+ i = mei_find_me_client_update_filext(dev, &dev->iamthif_cl,
+ &mei_amthi_guid, MEI_IAMTHIF_HOST_CLIENT_ID);
+ if (dev->iamthif_cl.state != MEI_FILE_CONNECTING) {
+ dev_dbg(&dev->pdev->dev, "failed to find iamthif client.\n");
+ return;
+ }
+
+ /* Do not render the system unusable when iamthif_mtu is not equal to
+ the value received from ME.
+ Assign iamthif_mtu to the value received from ME in order to solve the
+ hardware macro incompatibility. */
+
+ dev_dbg(&dev->pdev->dev, "[DEFAULT] IAMTHIF = %d\n", dev->iamthif_mtu);
+ dev->iamthif_mtu = dev->me_clients[i].props.max_msg_length;
+ dev_dbg(&dev->pdev->dev,
+ "IAMTHIF = %d\n",
+ dev->me_clients[i].props.max_msg_length);
+
+ kfree(dev->iamthif_msg_buf);
+ dev->iamthif_msg_buf = NULL;
+
+ /* allocate storage for ME message buffer */
+ msg_buf = kcalloc(dev->iamthif_mtu,
+ sizeof(unsigned char), GFP_KERNEL);
+ if (!msg_buf) {
+ dev_dbg(&dev->pdev->dev, "memory allocation for ME message buffer failed.\n");
+ return;
+ }
+
+ dev->iamthif_msg_buf = msg_buf;
+
+ if (!mei_connect(dev, &dev->iamthif_cl)) {
+ dev_dbg(&dev->pdev->dev, "Failed to connect to AMTHI client\n");
+ dev->iamthif_cl.state = MEI_FILE_DISCONNECTED;
+ dev->iamthif_cl.host_client_id = 0;
+ } else {
+ dev->iamthif_cl.timer_count = CONNECT_TIMEOUT;
+ }
+}
+
+/**
+ * mei_alloc_file_private - allocates a private file structure and sets it up.
+ * @file: the file structure
+ *
+ * returns The allocated file or NULL on failure
+ */
+struct mei_cl *mei_alloc_file_private(struct mei_device *dev)
+{
+ struct mei_cl *priv;
+
+ priv = kmalloc(sizeof(struct mei_cl), GFP_KERNEL);
+ if (!priv)
+ return NULL;
+
+ mei_init_file_private(priv, dev);
+
+ return priv;
+}
+
+
+
+/**
+ * mei_disconnect_host_client - sends disconnect message to fw from host client.
+ *
+ * @dev: the device structure
+ * @cl: private data of the file object
+ *
+ * Locking: called under "dev->device_lock" lock
+ *
+ * returns 0 on success, <0 on failure.
+ */
+int mei_disconnect_host_client(struct mei_device *dev, struct mei_cl *cl)
+{
+ int rets, err;
+ long timeout = 15; /* 15 seconds */
+ struct mei_cl_cb *cb;
+
+ if (!dev || !cl)
+ return -ENODEV;
+
+ if (cl->state != MEI_FILE_DISCONNECTING)
+ return 0;
+
+ cb = kzalloc(sizeof(struct mei_cl_cb), GFP_KERNEL);
+ if (!cb)
+ return -ENOMEM;
+
+ INIT_LIST_HEAD(&cb->cb_list);
+ cb->file_private = cl;
+ cb->major_file_operations = MEI_CLOSE;
+ if (dev->mei_host_buffer_is_empty) {
+ dev->mei_host_buffer_is_empty = 0;
+ if (mei_disconnect(dev, cl)) {
+ mdelay(10); /* Wait for hardware disconnection ready */
+ list_add_tail(&cb->cb_list,
+ &dev->ctrl_rd_list.mei_cb.cb_list);
+ } else {
+ rets = -ENODEV;
+ dev_dbg(&dev->pdev->dev, "failed to call mei_disconnect.\n");
+ goto free;
+ }
+ } else {
+ dev_dbg(&dev->pdev->dev, "add disconnect cb to control write list\n");
+ list_add_tail(&cb->cb_list,
+ &dev->ctrl_wr_list.mei_cb.cb_list);
+ }
+ mutex_unlock(&dev->device_lock);
+
+ err = wait_event_timeout(dev->wait_recvd_msg,
+ (MEI_FILE_DISCONNECTED == cl->state),
+ timeout * HZ);
+
+ mutex_lock(&dev->device_lock);
+ if (MEI_FILE_DISCONNECTED == cl->state) {
+ rets = 0;
+ dev_dbg(&dev->pdev->dev, "successfully disconnected from FW client.\n");
+ } else {
+ rets = -ENODEV;
+ if (MEI_FILE_DISCONNECTED != cl->state)
+ dev_dbg(&dev->pdev->dev, "wrong status client disconnect.\n");
+
+ if (err)
+ dev_dbg(&dev->pdev->dev,
+ "wait failed disconnect err=%08x\n",
+ err);
+
+ dev_dbg(&dev->pdev->dev, "failed to disconnect from FW client.\n");
+ }
+
+ mei_flush_list(&dev->ctrl_rd_list, cl);
+ mei_flush_list(&dev->ctrl_wr_list, cl);
+free:
+ mei_free_cb_private(cb);
+ return rets;
+}
+
+/**
+ * mei_remove_client_from_file_list -
+ * removes file private data from device file list
+ *
+ * @dev: the device structure
+ * @host_client_id: host client id to be removed
+ */
+void mei_remove_client_from_file_list(struct mei_device *dev,
+ u8 host_client_id)
+{
+ struct mei_cl *cl_pos = NULL;
+ struct mei_cl *cl_next = NULL;
+ list_for_each_entry_safe(cl_pos, cl_next, &dev->file_list, link) {
+ if (host_client_id == cl_pos->host_client_id) {
+ dev_dbg(&dev->pdev->dev, "remove host client = %d, ME client = %d\n",
+ cl_pos->host_client_id,
+ cl_pos->me_client_id);
+ list_del_init(&cl_pos->link);
+ break;
+ }
+ }
+}
diff --git a/drivers/staging/mei/interface.c b/drivers/staging/mei/interface.c
new file mode 100644
index 0000000..4959aae
--- /dev/null
+++ b/drivers/staging/mei/interface.c
@@ -0,0 +1,447 @@
+/*
+ *
+ * Intel Management Engine Interface (Intel MEI) Linux driver
+ * Copyright (c) 2003-2011, Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#include <linux/pci.h>
+#include "mei_dev.h"
+#include "mei.h"
+#include "interface.h"
+
+
+
+/**
+ * mei_set_csr_register - writes H_CSR register to the mei device,
+ * and ignores the H_IS bit for it is write-one-to-zero.
+ *
+ * @dev: the device structure
+ */
+void mei_hcsr_set(struct mei_device *dev)
+{
+ if ((dev->host_hw_state & H_IS) == H_IS)
+ dev->host_hw_state &= ~H_IS;
+ mei_reg_write(dev, H_CSR, dev->host_hw_state);
+ dev->host_hw_state = mei_hcsr_read(dev);
+}
+
+/**
+ * mei_csr_enable_interrupts - enables mei device interrupts
+ *
+ * @dev: the device structure
+ */
+void mei_enable_interrupts(struct mei_device *dev)
+{
+ dev->host_hw_state |= H_IE;
+ mei_hcsr_set(dev);
+}
+
+/**
+ * mei_csr_disable_interrupts - disables mei device interrupts
+ *
+ * @dev: the device structure
+ */
+void mei_disable_interrupts(struct mei_device *dev)
+{
+ dev->host_hw_state &= ~H_IE;
+ mei_hcsr_set(dev);
+}
+
+/**
+ * _host_get_filled_slots - gets number of device filled buffer slots
+ *
+ * @device: the device structure
+ *
+ * returns number of filled slots
+ */
+static unsigned char _host_get_filled_slots(const struct mei_device *dev)
+{
+ char read_ptr, write_ptr;
+
+ read_ptr = (char) ((dev->host_hw_state & H_CBRP) >> 8);
+ write_ptr = (char) ((dev->host_hw_state & H_CBWP) >> 16);
+
+ return (unsigned char) (write_ptr - read_ptr);
+}
+
+/**
+ * mei_host_buffer_is_empty - checks if host buffer is empty.
+ *
+ * @dev: the device structure
+ *
+ * returns 1 if empty, 0 - otherwise.
+ */
+int mei_host_buffer_is_empty(struct mei_device *dev)
+{
+ unsigned char filled_slots;
+
+ dev->host_hw_state = mei_hcsr_read(dev);
+ filled_slots = _host_get_filled_slots(dev);
+
+ if (filled_slots == 0)
+ return 1;
+
+ return 0;
+}
+
+/**
+ * mei_count_empty_write_slots - counts write empty slots.
+ *
+ * @dev: the device structure
+ *
+ * returns -1(ESLOTS_OVERFLOW) if overflow, otherwise empty slots count
+ */
+int mei_count_empty_write_slots(struct mei_device *dev)
+{
+ unsigned char buffer_depth, filled_slots, empty_slots;
+
+ dev->host_hw_state = mei_hcsr_read(dev);
+ buffer_depth = (unsigned char) ((dev->host_hw_state & H_CBD) >> 24);
+ filled_slots = _host_get_filled_slots(dev);
+ empty_slots = buffer_depth - filled_slots;
+
+ /* check for overflow */
+ if (filled_slots > buffer_depth)
+ return -EOVERFLOW;
+
+ return empty_slots;
+}
+
+/**
+ * mei_write_message - writes a message to mei device.
+ *
+ * @dev: the device structure
+ * @header: header of message
+ * @write_buffer: message buffer will be written
+ * @write_length: message size will be written
+ *
+ * returns 1 if success, 0 - otherwise.
+ */
+int mei_write_message(struct mei_device *dev,
+ struct mei_msg_hdr *header,
+ unsigned char *write_buffer,
+ unsigned long write_length)
+{
+ u32 temp_msg = 0;
+ unsigned long bytes_written = 0;
+ unsigned char buffer_depth, filled_slots, empty_slots;
+ unsigned long dw_to_write;
+
+ dev->host_hw_state = mei_hcsr_read(dev);
+
+ dev_dbg(&dev->pdev->dev,
+ "host_hw_state = 0x%08x.\n",
+ dev->host_hw_state);
+
+ dev_dbg(&dev->pdev->dev,
+ "mei_write_message header=%08x.\n",
+ *((u32 *) header));
+
+ buffer_depth = (unsigned char) ((dev->host_hw_state & H_CBD) >> 24);
+ filled_slots = _host_get_filled_slots(dev);
+ empty_slots = buffer_depth - filled_slots;
+ dev_dbg(&dev->pdev->dev,
+ "filled = %hu, empty = %hu.\n",
+ filled_slots, empty_slots);
+
+ dw_to_write = ((write_length + 3) / 4);
+
+ if (dw_to_write > empty_slots)
+ return 0;
+
+ mei_reg_write(dev, H_CB_WW, *((u32 *) header));
+
+ while (write_length >= 4) {
+ mei_reg_write(dev, H_CB_WW,
+ *(u32 *) (write_buffer + bytes_written));
+ bytes_written += 4;
+ write_length -= 4;
+ }
+
+ if (write_length > 0) {
+ memcpy(&temp_msg, &write_buffer[bytes_written], write_length);
+ mei_reg_write(dev, H_CB_WW, temp_msg);
+ }
+
+ dev->host_hw_state |= H_IG;
+ mei_hcsr_set(dev);
+ dev->me_hw_state = mei_mecsr_read(dev);
+ if ((dev->me_hw_state & ME_RDY_HRA) != ME_RDY_HRA)
+ return 0;
+
+ dev->write_hang = 0;
+ return 1;
+}
+
+/**
+ * mei_count_full_read_slots - counts read full slots.
+ *
+ * @dev: the device structure
+ *
+ * returns -1(ESLOTS_OVERFLOW) if overflow, otherwise filled slots count
+ */
+int mei_count_full_read_slots(struct mei_device *dev)
+{
+ char read_ptr, write_ptr;
+ unsigned char buffer_depth, filled_slots;
+
+ dev->me_hw_state = mei_mecsr_read(dev);
+ buffer_depth = (unsigned char)((dev->me_hw_state & ME_CBD_HRA) >> 24);
+ read_ptr = (char) ((dev->me_hw_state & ME_CBRP_HRA) >> 8);
+ write_ptr = (char) ((dev->me_hw_state & ME_CBWP_HRA) >> 16);
+ filled_slots = (unsigned char) (write_ptr - read_ptr);
+
+ /* check for overflow */
+ if (filled_slots > buffer_depth)
+ return -EOVERFLOW;
+
+ dev_dbg(&dev->pdev->dev, "filled_slots =%08x\n", filled_slots);
+ return (int)filled_slots;
+}
+
+/**
+ * mei_read_slots - reads a message from mei device.
+ *
+ * @dev: the device structure
+ * @buffer: message buffer will be written
+ * @buffer_length: message size will be read
+ */
+void mei_read_slots(struct mei_device *dev,
+ unsigned char *buffer, unsigned long buffer_length)
+{
+ u32 i = 0;
+ unsigned char temp_buf[sizeof(u32)];
+
+ while (buffer_length >= sizeof(u32)) {
+ ((u32 *) buffer)[i] = mei_mecbrw_read(dev);
+
+ dev_dbg(&dev->pdev->dev,
+ "buffer[%d]= %d\n",
+ i, ((u32 *) buffer)[i]);
+
+ i++;
+ buffer_length -= sizeof(u32);
+ }
+
+ if (buffer_length > 0) {
+ *((u32 *) &temp_buf) = mei_mecbrw_read(dev);
+ memcpy(&buffer[i * 4], temp_buf, buffer_length);
+ }
+
+ dev->host_hw_state |= H_IG;
+ mei_hcsr_set(dev);
+}
+
+/**
+ * mei_flow_ctrl_creds - checks flow_control credentials.
+ *
+ * @dev: the device structure
+ * @cl: private data of the file object
+ *
+ * returns 1 if mei_flow_ctrl_creds >0, 0 - otherwise.
+ * -ENOENT if mei_cl is not present
+ * -EINVAL if single_recv_buf == 0
+ */
+int mei_flow_ctrl_creds(struct mei_device *dev, struct mei_cl *cl)
+{
+ int i;
+
+ if (!dev->num_mei_me_clients)
+ return 0;
+
+ if (cl->mei_flow_ctrl_creds > 0)
+ return 1;
+
+ for (i = 0; i < dev->num_mei_me_clients; i++) {
+ struct mei_me_client *me_cl = &dev->me_clients[i];
+ if (me_cl->client_id == cl->me_client_id) {
+ if (me_cl->mei_flow_ctrl_creds) {
+ if (WARN_ON(me_cl->props.single_recv_buf == 0))
+ return -EINVAL;
+ return 1;
+ } else {
+ return 0;
+ }
+ }
+ }
+ return -ENOENT;
+}
+
+/**
+ * mei_flow_ctrl_reduce - reduces flow_control.
+ *
+ * @dev: the device structure
+ * @cl: private data of the file object
+ * @returns
+ * 0 on success
+ * -ENOENT when me client is not found
+ * -EINVAL wehn ctrl credits are <= 0
+ */
+int mei_flow_ctrl_reduce(struct mei_device *dev, struct mei_cl *cl)
+{
+ int i;
+
+ if (!dev->num_mei_me_clients)
+ return -ENOENT;
+
+ for (i = 0; i < dev->num_mei_me_clients; i++) {
+ struct mei_me_client *me_cl = &dev->me_clients[i];
+ if (me_cl->client_id == cl->me_client_id) {
+ if (me_cl->props.single_recv_buf != 0) {
+ if (WARN_ON(me_cl->mei_flow_ctrl_creds <= 0))
+ return -EINVAL;
+ dev->me_clients[i].mei_flow_ctrl_creds--;
+ } else {
+ if (WARN_ON(cl->mei_flow_ctrl_creds <= 0))
+ return -EINVAL;
+ cl->mei_flow_ctrl_creds--;
+ }
+ return 0;
+ }
+ }
+ return -ENOENT;
+}
+
+/**
+ * mei_send_flow_control - sends flow control to fw.
+ *
+ * @dev: the device structure
+ * @cl: private data of the file object
+ *
+ * returns 1 if success, 0 - otherwise.
+ */
+int mei_send_flow_control(struct mei_device *dev, struct mei_cl *cl)
+{
+ struct mei_msg_hdr *mei_hdr;
+ struct hbm_flow_control *mei_flow_control;
+
+ mei_hdr = (struct mei_msg_hdr *) &dev->wr_msg_buf[0];
+ mei_hdr->host_addr = 0;
+ mei_hdr->me_addr = 0;
+ mei_hdr->length = sizeof(struct hbm_flow_control);
+ mei_hdr->msg_complete = 1;
+ mei_hdr->reserved = 0;
+
+ mei_flow_control = (struct hbm_flow_control *) &dev->wr_msg_buf[1];
+ memset(mei_flow_control, 0, sizeof(mei_flow_control));
+ mei_flow_control->host_addr = cl->host_client_id;
+ mei_flow_control->me_addr = cl->me_client_id;
+ mei_flow_control->cmd.cmd = MEI_FLOW_CONTROL_CMD;
+ memset(mei_flow_control->reserved, 0,
+ sizeof(mei_flow_control->reserved));
+ dev_dbg(&dev->pdev->dev, "sending flow control host client = %d, ME client = %d\n",
+ cl->host_client_id, cl->me_client_id);
+ if (!mei_write_message(dev, mei_hdr,
+ (unsigned char *) mei_flow_control,
+ sizeof(struct hbm_flow_control)))
+ return 0;
+
+ return 1;
+
+}
+
+/**
+ * mei_other_client_is_connecting - checks if other
+ * client with the same client id is connected.
+ *
+ * @dev: the device structure
+ * @cl: private data of the file object
+ *
+ * returns 1 if other client is connected, 0 - otherwise.
+ */
+int mei_other_client_is_connecting(struct mei_device *dev,
+ struct mei_cl *cl)
+{
+ struct mei_cl *cl_pos = NULL;
+ struct mei_cl *cl_next = NULL;
+
+ list_for_each_entry_safe(cl_pos, cl_next, &dev->file_list, link) {
+ if ((cl_pos->state == MEI_FILE_CONNECTING) &&
+ (cl_pos != cl) &&
+ cl->me_client_id == cl_pos->me_client_id)
+ return 1;
+
+ }
+ return 0;
+}
+
+/**
+ * mei_disconnect - sends disconnect message to fw.
+ *
+ * @dev: the device structure
+ * @cl: private data of the file object
+ *
+ * returns 1 if success, 0 - otherwise.
+ */
+int mei_disconnect(struct mei_device *dev, struct mei_cl *cl)
+{
+ struct mei_msg_hdr *mei_hdr;
+ struct hbm_client_disconnect_request *mei_cli_disconnect;
+
+ mei_hdr = (struct mei_msg_hdr *) &dev->wr_msg_buf[0];
+ mei_hdr->host_addr = 0;
+ mei_hdr->me_addr = 0;
+ mei_hdr->length = sizeof(struct hbm_client_disconnect_request);
+ mei_hdr->msg_complete = 1;
+ mei_hdr->reserved = 0;
+
+ mei_cli_disconnect =
+ (struct hbm_client_disconnect_request *) &dev->wr_msg_buf[1];
+ memset(mei_cli_disconnect, 0, sizeof(mei_cli_disconnect));
+ mei_cli_disconnect->host_addr = cl->host_client_id;
+ mei_cli_disconnect->me_addr = cl->me_client_id;
+ mei_cli_disconnect->cmd.cmd = CLIENT_DISCONNECT_REQ_CMD;
+ mei_cli_disconnect->reserved[0] = 0;
+
+ if (!mei_write_message(dev, mei_hdr,
+ (unsigned char *) mei_cli_disconnect,
+ sizeof(struct hbm_client_disconnect_request)))
+ return 0;
+
+ return 1;
+}
+
+/**
+ * mei_connect - sends connect message to fw.
+ *
+ * @dev: the device structure
+ * @cl: private data of the file object
+ *
+ * returns 1 if success, 0 - otherwise.
+ */
+int mei_connect(struct mei_device *dev, struct mei_cl *cl)
+{
+ struct mei_msg_hdr *mei_hdr;
+ struct hbm_client_connect_request *mei_cli_connect;
+
+ mei_hdr = (struct mei_msg_hdr *) &dev->wr_msg_buf[0];
+ mei_hdr->host_addr = 0;
+ mei_hdr->me_addr = 0;
+ mei_hdr->length = sizeof(struct hbm_client_connect_request);
+ mei_hdr->msg_complete = 1;
+ mei_hdr->reserved = 0;
+
+ mei_cli_connect =
+ (struct hbm_client_connect_request *) &dev->wr_msg_buf[1];
+ mei_cli_connect->host_addr = cl->host_client_id;
+ mei_cli_connect->me_addr = cl->me_client_id;
+ mei_cli_connect->cmd.cmd = CLIENT_CONNECT_REQ_CMD;
+ mei_cli_connect->reserved = 0;
+
+ if (!mei_write_message(dev, mei_hdr,
+ (unsigned char *) mei_cli_connect,
+ sizeof(struct hbm_client_connect_request)))
+ return 0;
+
+ return 1;
+}
diff --git a/drivers/staging/mei/interface.h b/drivers/staging/mei/interface.h
new file mode 100644
index 0000000..d0bf5cf
--- /dev/null
+++ b/drivers/staging/mei/interface.h
@@ -0,0 +1,62 @@
+/*
+ *
+ * Intel Management Engine Interface (Intel MEI) Linux driver
+ * Copyright (c) 2003-2011, Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+
+
+
+#ifndef _MEI_INTERFACE_H_
+#define _MEI_INTERFACE_H_
+
+#include "mei.h"
+#include "mei_dev.h"
+
+
+#define AMT_WD_VALUE 120 /* seconds */
+
+#define MEI_WATCHDOG_DATA_SIZE 16
+#define MEI_START_WD_DATA_SIZE 20
+#define MEI_WD_PARAMS_SIZE 4
+
+
+void mei_read_slots(struct mei_device *dev,
+ unsigned char *buffer, unsigned long buffer_length);
+
+int mei_write_message(struct mei_device *dev,
+ struct mei_msg_hdr *header,
+ unsigned char *write_buffer,
+ unsigned long write_length);
+
+int mei_host_buffer_is_empty(struct mei_device *dev);
+
+int mei_count_full_read_slots(struct mei_device *dev);
+
+int mei_count_empty_write_slots(struct mei_device *dev);
+
+int mei_flow_ctrl_creds(struct mei_device *dev, struct mei_cl *cl);
+
+int mei_wd_send(struct mei_device *dev);
+int mei_wd_stop(struct mei_device *dev, bool preserve);
+void mei_wd_host_init(struct mei_device *dev);
+void mei_wd_start_setup(struct mei_device *dev);
+
+int mei_flow_ctrl_reduce(struct mei_device *dev, struct mei_cl *cl);
+
+int mei_send_flow_control(struct mei_device *dev, struct mei_cl *cl);
+
+int mei_disconnect(struct mei_device *dev, struct mei_cl *cl);
+int mei_other_client_is_connecting(struct mei_device *dev, struct mei_cl *cl);
+int mei_connect(struct mei_device *dev, struct mei_cl *cl);
+
+#endif /* _MEI_INTERFACE_H_ */
diff --git a/drivers/staging/mei/interrupt.c b/drivers/staging/mei/interrupt.c
new file mode 100644
index 0000000..d1b9214
--- /dev/null
+++ b/drivers/staging/mei/interrupt.c
@@ -0,0 +1,1624 @@
+/*
+ *
+ * Intel Management Engine Interface (Intel MEI) Linux driver
+ * Copyright (c) 2003-2011, Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+
+
+#include <linux/pci.h>
+#include <linux/kthread.h>
+#include <linux/interrupt.h>
+#include <linux/fs.h>
+#include <linux/jiffies.h>
+
+#include "mei_dev.h"
+#include "mei.h"
+#include "hw.h"
+#include "interface.h"
+
+
+/**
+ * mei_interrupt_quick_handler - The ISR of the MEI device
+ *
+ * @irq: The irq number
+ * @dev_id: pointer to the device structure
+ *
+ * returns irqreturn_t
+ */
+irqreturn_t mei_interrupt_quick_handler(int irq, void *dev_id)
+{
+ struct mei_device *dev = (struct mei_device *) dev_id;
+ u32 csr_reg = mei_hcsr_read(dev);
+
+ if ((csr_reg & H_IS) != H_IS)
+ return IRQ_NONE;
+
+ /* clear H_IS bit in H_CSR */
+ mei_reg_write(dev, H_CSR, csr_reg);
+
+ return IRQ_WAKE_THREAD;
+}
+
+/**
+ * _mei_cmpl - processes completed operation.
+ *
+ * @cl: private data of the file object.
+ * @cb_pos: callback block.
+ */
+static void _mei_cmpl(struct mei_cl *cl, struct mei_cl_cb *cb_pos)
+{
+ if (cb_pos->major_file_operations == MEI_WRITE) {
+ mei_free_cb_private(cb_pos);
+ cb_pos = NULL;
+ cl->writing_state = MEI_WRITE_COMPLETE;
+ if (waitqueue_active(&cl->tx_wait))
+ wake_up_interruptible(&cl->tx_wait);
+
+ } else if (cb_pos->major_file_operations == MEI_READ &&
+ MEI_READING == cl->reading_state) {
+ cl->reading_state = MEI_READ_COMPLETE;
+ if (waitqueue_active(&cl->rx_wait))
+ wake_up_interruptible(&cl->rx_wait);
+
+ }
+}
+
+/**
+ * _mei_cmpl_iamthif - processes completed iamthif operation.
+ *
+ * @dev: the device structure.
+ * @cb_pos: callback block.
+ */
+static void _mei_cmpl_iamthif(struct mei_device *dev, struct mei_cl_cb *cb_pos)
+{
+ if (dev->iamthif_canceled != 1) {
+ dev->iamthif_state = MEI_IAMTHIF_READ_COMPLETE;
+ dev->iamthif_stall_timer = 0;
+ memcpy(cb_pos->response_buffer.data,
+ dev->iamthif_msg_buf,
+ dev->iamthif_msg_buf_index);
+ list_add_tail(&cb_pos->cb_list,
+ &dev->amthi_read_complete_list.mei_cb.cb_list);
+ dev_dbg(&dev->pdev->dev, "amthi read completed.\n");
+ dev->iamthif_timer = jiffies;
+ dev_dbg(&dev->pdev->dev, "dev->iamthif_timer = %ld\n",
+ dev->iamthif_timer);
+ } else {
+ run_next_iamthif_cmd(dev);
+ }
+
+ dev_dbg(&dev->pdev->dev, "completing amthi call back.\n");
+ wake_up_interruptible(&dev->iamthif_cl.wait);
+}
+
+
+/**
+ * mei_irq_thread_read_amthi_message - bottom half read routine after ISR to
+ * handle the read amthi message data processing.
+ *
+ * @complete_list: An instance of our list structure
+ * @dev: the device structure
+ * @mei_hdr: header of amthi message
+ *
+ * returns 0 on success, <0 on failure.
+ */
+static int mei_irq_thread_read_amthi_message(struct mei_io_list *complete_list,
+ struct mei_device *dev,
+ struct mei_msg_hdr *mei_hdr)
+{
+ struct mei_cl *cl;
+ struct mei_cl_cb *cb;
+ unsigned char *buffer;
+
+ BUG_ON(mei_hdr->me_addr != dev->iamthif_cl.me_client_id);
+ BUG_ON(dev->iamthif_state != MEI_IAMTHIF_READING);
+
+ buffer = (unsigned char *) (dev->iamthif_msg_buf +
+ dev->iamthif_msg_buf_index);
+ BUG_ON(dev->iamthif_mtu < dev->iamthif_msg_buf_index + mei_hdr->length);
+
+ mei_read_slots(dev, buffer, mei_hdr->length);
+
+ dev->iamthif_msg_buf_index += mei_hdr->length;
+
+ if (!mei_hdr->msg_complete)
+ return 0;
+
+ dev_dbg(&dev->pdev->dev,
+ "amthi_message_buffer_index =%d\n",
+ mei_hdr->length);
+
+ dev_dbg(&dev->pdev->dev, "completed amthi read.\n ");
+ if (!dev->iamthif_current_cb)
+ return -ENODEV;
+
+ cb = dev->iamthif_current_cb;
+ dev->iamthif_current_cb = NULL;
+
+ cl = (struct mei_cl *)cb->file_private;
+ if (!cl)
+ return -ENODEV;
+
+ dev->iamthif_stall_timer = 0;
+ cb->information = dev->iamthif_msg_buf_index;
+ cb->read_time = jiffies;
+ if (dev->iamthif_ioctl && cl == &dev->iamthif_cl) {
+ /* found the iamthif cb */
+ dev_dbg(&dev->pdev->dev, "complete the amthi read cb.\n ");
+ dev_dbg(&dev->pdev->dev, "add the amthi read cb to complete.\n ");
+ list_add_tail(&cb->cb_list,
+ &complete_list->mei_cb.cb_list);
+ }
+ return 0;
+}
+
+/**
+ * _mei_irq_thread_state_ok - checks if mei header matches file private data
+ *
+ * @cl: private data of the file object
+ * @mei_hdr: header of mei client message
+ *
+ * returns !=0 if matches, 0 if no match.
+ */
+static int _mei_irq_thread_state_ok(struct mei_cl *cl,
+ struct mei_msg_hdr *mei_hdr)
+{
+ return (cl->host_client_id == mei_hdr->host_addr &&
+ cl->me_client_id == mei_hdr->me_addr &&
+ cl->state == MEI_FILE_CONNECTED &&
+ MEI_READ_COMPLETE != cl->reading_state);
+}
+
+/**
+ * mei_irq_thread_read_client_message - bottom half read routine after ISR to
+ * handle the read mei client message data processing.
+ *
+ * @complete_list: An instance of our list structure
+ * @dev: the device structure
+ * @mei_hdr: header of mei client message
+ *
+ * returns 0 on success, <0 on failure.
+ */
+static int mei_irq_thread_read_client_message(struct mei_io_list *complete_list,
+ struct mei_device *dev,
+ struct mei_msg_hdr *mei_hdr)
+{
+ struct mei_cl *cl;
+ struct mei_cl_cb *cb_pos = NULL, *cb_next = NULL;
+ unsigned char *buffer;
+
+ dev_dbg(&dev->pdev->dev, "start client msg\n");
+ if (!(dev->read_list.status == 0 &&
+ !list_empty(&dev->read_list.mei_cb.cb_list)))
+ goto quit;
+
+ list_for_each_entry_safe(cb_pos, cb_next,
+ &dev->read_list.mei_cb.cb_list, cb_list) {
+ cl = (struct mei_cl *)cb_pos->file_private;
+ if (cl && _mei_irq_thread_state_ok(cl, mei_hdr)) {
+ cl->reading_state = MEI_READING;
+ buffer = (unsigned char *)
+ (cb_pos->response_buffer.data +
+ cb_pos->information);
+ BUG_ON(cb_pos->response_buffer.size <
+ mei_hdr->length +
+ cb_pos->information);
+
+ if (cb_pos->response_buffer.size <
+ mei_hdr->length + cb_pos->information) {
+ dev_dbg(&dev->pdev->dev, "message overflow.\n");
+ list_del(&cb_pos->cb_list);
+ return -ENOMEM;
+ }
+ if (buffer)
+ mei_read_slots(dev, buffer, mei_hdr->length);
+
+ cb_pos->information += mei_hdr->length;
+ if (mei_hdr->msg_complete) {
+ cl->status = 0;
+ list_del(&cb_pos->cb_list);
+ dev_dbg(&dev->pdev->dev,
+ "completed read host client = %d,"
+ "ME client = %d, "
+ "data length = %lu\n",
+ cl->host_client_id,
+ cl->me_client_id,
+ cb_pos->information);
+
+ *(cb_pos->response_buffer.data +
+ cb_pos->information) = '\0';
+ dev_dbg(&dev->pdev->dev, "cb_pos->res_buffer - %s\n",
+ cb_pos->response_buffer.data);
+ list_add_tail(&cb_pos->cb_list,
+ &complete_list->mei_cb.cb_list);
+ }
+
+ break;
+ }
+
+ }
+
+quit:
+ dev_dbg(&dev->pdev->dev, "message read\n");
+ if (!buffer) {
+ mei_read_slots(dev, (unsigned char *) dev->rd_msg_buf,
+ mei_hdr->length);
+ dev_dbg(&dev->pdev->dev, "discarding message, header =%08x.\n",
+ *(u32 *) dev->rd_msg_buf);
+ }
+
+ return 0;
+}
+
+/**
+ * _mei_irq_thread_iamthif_read - prepares to read iamthif data.
+ *
+ * @dev: the device structure.
+ * @slots: free slots.
+ *
+ * returns 0, OK; otherwise, error.
+ */
+static int _mei_irq_thread_iamthif_read(struct mei_device *dev, s32 *slots)
+{
+
+ if (((*slots) * sizeof(u32)) >= (sizeof(struct mei_msg_hdr)
+ + sizeof(struct hbm_flow_control))) {
+ *slots -= (sizeof(struct mei_msg_hdr) +
+ sizeof(struct hbm_flow_control) + 3) / 4;
+ if (!mei_send_flow_control(dev, &dev->iamthif_cl)) {
+ dev_dbg(&dev->pdev->dev, "iamthif flow control failed\n");
+ } else {
+ dev_dbg(&dev->pdev->dev, "iamthif flow control success\n");
+ dev->iamthif_state = MEI_IAMTHIF_READING;
+ dev->iamthif_flow_control_pending = 0;
+ dev->iamthif_msg_buf_index = 0;
+ dev->iamthif_msg_buf_size = 0;
+ dev->iamthif_stall_timer = IAMTHIF_STALL_TIMER;
+ dev->mei_host_buffer_is_empty =
+ mei_host_buffer_is_empty(dev);
+ }
+ return 0;
+ } else {
+ return -EMSGSIZE;
+ }
+}
+
+/**
+ * _mei_irq_thread_close - processes close related operation.
+ *
+ * @dev: the device structure.
+ * @slots: free slots.
+ * @cb_pos: callback block.
+ * @cl: private data of the file object.
+ * @cmpl_list: complete list.
+ *
+ * returns 0, OK; otherwise, error.
+ */
+static int _mei_irq_thread_close(struct mei_device *dev, s32 *slots,
+ struct mei_cl_cb *cb_pos,
+ struct mei_cl *cl,
+ struct mei_io_list *cmpl_list)
+{
+ if ((*slots * sizeof(u32)) >= (sizeof(struct mei_msg_hdr) +
+ sizeof(struct hbm_client_disconnect_request))) {
+ *slots -= (sizeof(struct mei_msg_hdr) +
+ sizeof(struct hbm_client_disconnect_request) + 3) / 4;
+
+ if (!mei_disconnect(dev, cl)) {
+ cl->status = 0;
+ cb_pos->information = 0;
+ list_move_tail(&cb_pos->cb_list,
+ &cmpl_list->mei_cb.cb_list);
+ return -EMSGSIZE;
+ } else {
+ cl->state = MEI_FILE_DISCONNECTING;
+ cl->status = 0;
+ cb_pos->information = 0;
+ list_move_tail(&cb_pos->cb_list,
+ &dev->ctrl_rd_list.mei_cb.cb_list);
+ cl->timer_count = MEI_CONNECT_TIMEOUT;
+ }
+ } else {
+ /* return the cancel routine */
+ return -EBADMSG;
+ }
+
+ return 0;
+}
+
+/**
+ * is_treat_specially_client - checks if the message belongs
+ * to the file private data.
+ *
+ * @cl: private data of the file object
+ * @rs: connect response bus message
+ *
+ */
+static bool is_treat_specially_client(struct mei_cl *cl,
+ struct hbm_client_connect_response *rs)
+{
+
+ if (cl->host_client_id == rs->host_addr &&
+ cl->me_client_id == rs->me_addr) {
+ if (!rs->status) {
+ cl->state = MEI_FILE_CONNECTED;
+ cl->status = 0;
+
+ } else {
+ cl->state = MEI_FILE_DISCONNECTED;
+ cl->status = -ENODEV;
+ }
+ cl->timer_count = 0;
+
+ return true;
+ }
+ return false;
+}
+
+/**
+ * mei_client_connect_response - connects to response irq routine
+ *
+ * @dev: the device structure
+ * @rs: connect response bus message
+ */
+static void mei_client_connect_response(struct mei_device *dev,
+ struct hbm_client_connect_response *rs)
+{
+
+ struct mei_cl *cl;
+ struct mei_cl_cb *cb_pos = NULL, *cb_next = NULL;
+
+ dev_dbg(&dev->pdev->dev,
+ "connect_response:\n"
+ "ME Client = %d\n"
+ "Host Client = %d\n"
+ "Status = %d\n",
+ rs->me_addr,
+ rs->host_addr,
+ rs->status);
+
+ /* if WD or iamthif client treat specially */
+
+ if (is_treat_specially_client(&(dev->wd_cl), rs)) {
+ dev_dbg(&dev->pdev->dev, "dev->wd_timeout =%d.\n",
+ dev->wd_timeout);
+
+ dev->wd_due_counter = (dev->wd_timeout) ? 1 : 0;
+
+ dev_dbg(&dev->pdev->dev, "successfully connected to WD client.\n");
+ host_init_iamthif(dev);
+ return;
+ }
+
+ if (is_treat_specially_client(&(dev->iamthif_cl), rs)) {
+ dev->iamthif_state = MEI_IAMTHIF_IDLE;
+ return;
+ }
+ if (!dev->ctrl_rd_list.status &&
+ !list_empty(&dev->ctrl_rd_list.mei_cb.cb_list)) {
+ list_for_each_entry_safe(cb_pos, cb_next,
+ &dev->ctrl_rd_list.mei_cb.cb_list, cb_list) {
+ cl = (struct mei_cl *)cb_pos->file_private;
+ if (!cl) {
+ list_del(&cb_pos->cb_list);
+ return;
+ }
+ if (MEI_IOCTL == cb_pos->major_file_operations) {
+ if (is_treat_specially_client(cl, rs)) {
+ list_del(&cb_pos->cb_list);
+ cl->status = 0;
+ cl->timer_count = 0;
+ break;
+ }
+ }
+ }
+ }
+}
+
+/**
+ * mei_client_disconnect_response - disconnects from response irq routine
+ *
+ * @dev: the device structure
+ * @rs: disconnect response bus message
+ */
+static void mei_client_disconnect_response(struct mei_device *dev,
+ struct hbm_client_connect_response *rs)
+{
+ struct mei_cl *cl;
+ struct mei_cl_cb *cb_pos = NULL, *cb_next = NULL;
+
+ dev_dbg(&dev->pdev->dev,
+ "disconnect_response:\n"
+ "ME Client = %d\n"
+ "Host Client = %d\n"
+ "Status = %d\n",
+ rs->me_addr,
+ rs->host_addr,
+ rs->status);
+
+ if (!dev->ctrl_rd_list.status &&
+ !list_empty(&dev->ctrl_rd_list.mei_cb.cb_list)) {
+ list_for_each_entry_safe(cb_pos, cb_next,
+ &dev->ctrl_rd_list.mei_cb.cb_list, cb_list) {
+ cl = (struct mei_cl *)cb_pos->file_private;
+
+ if (!cl) {
+ list_del(&cb_pos->cb_list);
+ return;
+ }
+
+ dev_dbg(&dev->pdev->dev, "list_for_each_entry_safe in ctrl_rd_list.\n");
+ if (cl->host_client_id == rs->host_addr &&
+ cl->me_client_id == rs->me_addr) {
+
+ list_del(&cb_pos->cb_list);
+ if (!rs->status)
+ cl->state = MEI_FILE_DISCONNECTED;
+
+ cl->status = 0;
+ cl->timer_count = 0;
+ break;
+ }
+ }
+ }
+}
+
+/**
+ * same_flow_addr - tells if they have the same address.
+ *
+ * @file: private data of the file object.
+ * @flow: flow control.
+ *
+ * returns !=0, same; 0,not.
+ */
+static int same_flow_addr(struct mei_cl *cl, struct hbm_flow_control *flow)
+{
+ return (cl->host_client_id == flow->host_addr &&
+ cl->me_client_id == flow->me_addr);
+}
+
+/**
+ * add_single_flow_creds - adds single buffer credentials.
+ *
+ * @file: private data ot the file object.
+ * @flow: flow control.
+ */
+static void add_single_flow_creds(struct mei_device *dev,
+ struct hbm_flow_control *flow)
+{
+ struct mei_me_client *client;
+ int i;
+
+ for (i = 0; i < dev->num_mei_me_clients; i++) {
+ client = &dev->me_clients[i];
+ if (client && flow->me_addr == client->client_id) {
+ if (client->props.single_recv_buf) {
+ client->mei_flow_ctrl_creds++;
+ dev_dbg(&dev->pdev->dev, "recv flow ctrl msg ME %d (single).\n",
+ flow->me_addr);
+ dev_dbg(&dev->pdev->dev, "flow control credentials =%d.\n",
+ client->mei_flow_ctrl_creds);
+ } else {
+ BUG(); /* error in flow control */
+ }
+ }
+ }
+}
+
+/**
+ * mei_client_flow_control_response - flow control response irq routine
+ *
+ * @dev: the device structure
+ * @flow_control: flow control response bus message
+ */
+static void mei_client_flow_control_response(struct mei_device *dev,
+ struct hbm_flow_control *flow_control)
+{
+ struct mei_cl *cl_pos = NULL;
+ struct mei_cl *cl_next = NULL;
+
+ if (!flow_control->host_addr) {
+ /* single receive buffer */
+ add_single_flow_creds(dev, flow_control);
+ } else {
+ /* normal connection */
+ list_for_each_entry_safe(cl_pos, cl_next,
+ &dev->file_list, link) {
+ dev_dbg(&dev->pdev->dev, "list_for_each_entry_safe in file_list\n");
+
+ dev_dbg(&dev->pdev->dev, "cl of host client %d ME client %d.\n",
+ cl_pos->host_client_id,
+ cl_pos->me_client_id);
+ dev_dbg(&dev->pdev->dev, "flow ctrl msg for host %d ME %d.\n",
+ flow_control->host_addr,
+ flow_control->me_addr);
+ if (same_flow_addr(cl_pos, flow_control)) {
+ dev_dbg(&dev->pdev->dev, "recv ctrl msg for host %d ME %d.\n",
+ flow_control->host_addr,
+ flow_control->me_addr);
+ cl_pos->mei_flow_ctrl_creds++;
+ dev_dbg(&dev->pdev->dev, "flow control credentials = %d.\n",
+ cl_pos->mei_flow_ctrl_creds);
+ break;
+ }
+ }
+ }
+}
+
+/**
+ * same_disconn_addr - tells if they have the same address
+ *
+ * @file: private data of the file object.
+ * @disconn: disconnection request.
+ *
+ * returns !=0, same; 0,not.
+ */
+static int same_disconn_addr(struct mei_cl *cl,
+ struct hbm_client_disconnect_request *disconn)
+{
+ return (cl->host_client_id == disconn->host_addr &&
+ cl->me_client_id == disconn->me_addr);
+}
+
+/**
+ * mei_client_disconnect_request - disconnects from request irq routine
+ *
+ * @dev: the device structure.
+ * @disconnect_req: disconnect request bus message.
+ */
+static void mei_client_disconnect_request(struct mei_device *dev,
+ struct hbm_client_disconnect_request *disconnect_req)
+{
+ struct mei_msg_hdr *mei_hdr;
+ struct hbm_client_connect_response *disconnect_res;
+ struct mei_cl *cl_pos = NULL;
+ struct mei_cl *cl_next = NULL;
+
+ list_for_each_entry_safe(cl_pos, cl_next, &dev->file_list, link) {
+ if (same_disconn_addr(cl_pos, disconnect_req)) {
+ dev_dbg(&dev->pdev->dev, "disconnect request host client %d ME client %d.\n",
+ disconnect_req->host_addr,
+ disconnect_req->me_addr);
+ cl_pos->state = MEI_FILE_DISCONNECTED;
+ cl_pos->timer_count = 0;
+ if (cl_pos == &dev->wd_cl) {
+ dev->wd_due_counter = 0;
+ dev->wd_pending = 0;
+ } else if (cl_pos == &dev->iamthif_cl)
+ dev->iamthif_timer = 0;
+
+ /* prepare disconnect response */
+ mei_hdr =
+ (struct mei_msg_hdr *) &dev->ext_msg_buf[0];
+ mei_hdr->host_addr = 0;
+ mei_hdr->me_addr = 0;
+ mei_hdr->length =
+ sizeof(struct hbm_client_connect_response);
+ mei_hdr->msg_complete = 1;
+ mei_hdr->reserved = 0;
+
+ disconnect_res =
+ (struct hbm_client_connect_response *)
+ &dev->ext_msg_buf[1];
+ disconnect_res->host_addr = cl_pos->host_client_id;
+ disconnect_res->me_addr = cl_pos->me_client_id;
+ *(u8 *) (&disconnect_res->cmd) =
+ CLIENT_DISCONNECT_RES_CMD;
+ disconnect_res->status = 0;
+ dev->extra_write_index = 2;
+ break;
+ }
+ }
+}
+
+
+/**
+ * mei_irq_thread_read_bus_message - bottom half read routine after ISR to
+ * handle the read bus message cmd processing.
+ *
+ * @dev: the device structure
+ * @mei_hdr: header of bus message
+ */
+static void mei_irq_thread_read_bus_message(struct mei_device *dev,
+ struct mei_msg_hdr *mei_hdr)
+{
+ struct mei_bus_message *mei_msg;
+ struct hbm_host_version_response *version_res;
+ struct hbm_client_connect_response *connect_res;
+ struct hbm_client_connect_response *disconnect_res;
+ struct hbm_flow_control *flow_control;
+ struct hbm_props_response *props_res;
+ struct hbm_host_enum_response *enum_res;
+ struct hbm_client_disconnect_request *disconnect_req;
+ struct hbm_host_stop_request *host_stop_req;
+
+ unsigned char *buffer;
+
+ /* read the message to our buffer */
+ buffer = (unsigned char *) dev->rd_msg_buf;
+ BUG_ON(mei_hdr->length >= sizeof(dev->rd_msg_buf));
+ mei_read_slots(dev, buffer, mei_hdr->length);
+ mei_msg = (struct mei_bus_message *) buffer;
+
+ switch (*(u8 *) mei_msg) {
+ case HOST_START_RES_CMD:
+ version_res = (struct hbm_host_version_response *) mei_msg;
+ if (version_res->host_version_supported) {
+ dev->version.major_version = HBM_MAJOR_VERSION;
+ dev->version.minor_version = HBM_MINOR_VERSION;
+ if (dev->mei_state == MEI_INIT_CLIENTS &&
+ dev->init_clients_state == MEI_START_MESSAGE) {
+ dev->init_clients_timer = 0;
+ host_enum_clients_message(dev);
+ } else {
+ dev->recvd_msg = 0;
+ dev_dbg(&dev->pdev->dev, "IMEI reset due to received host start response bus message.\n");
+ mei_reset(dev, 1);
+ return;
+ }
+ } else {
+ dev->version = version_res->me_max_version;
+ /* send stop message */
+ mei_hdr->host_addr = 0;
+ mei_hdr->me_addr = 0;
+ mei_hdr->length = sizeof(struct hbm_host_stop_request);
+ mei_hdr->msg_complete = 1;
+ mei_hdr->reserved = 0;
+
+ host_stop_req = (struct hbm_host_stop_request *)
+ &dev->wr_msg_buf[1];
+
+ memset(host_stop_req,
+ 0,
+ sizeof(struct hbm_host_stop_request));
+ host_stop_req->cmd.cmd = HOST_STOP_REQ_CMD;
+ host_stop_req->reason = DRIVER_STOP_REQUEST;
+ mei_write_message(dev, mei_hdr,
+ (unsigned char *) (host_stop_req),
+ mei_hdr->length);
+ dev_dbg(&dev->pdev->dev, "version mismatch.\n");
+ return;
+ }
+
+ dev->recvd_msg = 1;
+ dev_dbg(&dev->pdev->dev, "host start response message received.\n");
+ break;
+
+ case CLIENT_CONNECT_RES_CMD:
+ connect_res =
+ (struct hbm_client_connect_response *) mei_msg;
+ mei_client_connect_response(dev, connect_res);
+ dev_dbg(&dev->pdev->dev, "client connect response message received.\n");
+ wake_up(&dev->wait_recvd_msg);
+ break;
+
+ case CLIENT_DISCONNECT_RES_CMD:
+ disconnect_res =
+ (struct hbm_client_connect_response *) mei_msg;
+ mei_client_disconnect_response(dev, disconnect_res);
+ dev_dbg(&dev->pdev->dev, "client disconnect response message received.\n");
+ wake_up(&dev->wait_recvd_msg);
+ break;
+
+ case MEI_FLOW_CONTROL_CMD:
+ flow_control = (struct hbm_flow_control *) mei_msg;
+ mei_client_flow_control_response(dev, flow_control);
+ dev_dbg(&dev->pdev->dev, "client flow control response message received.\n");
+ break;
+
+ case HOST_CLIENT_PROPERTIES_RES_CMD:
+ props_res = (struct hbm_props_response *)mei_msg;
+ if (props_res->status || !dev->me_clients) {
+ dev_dbg(&dev->pdev->dev, "reset due to received host client properties response bus message wrong status.\n");
+ mei_reset(dev, 1);
+ return;
+ }
+ if (dev->me_clients[dev->me_client_presentation_num]
+ .client_id == props_res->address) {
+
+ dev->me_clients[dev->me_client_presentation_num].props
+ = props_res->client_properties;
+
+ if (dev->mei_state == MEI_INIT_CLIENTS &&
+ dev->init_clients_state ==
+ MEI_CLIENT_PROPERTIES_MESSAGE) {
+ dev->me_client_index++;
+ dev->me_client_presentation_num++;
+ host_client_properties(dev);
+ } else {
+ dev_dbg(&dev->pdev->dev, "reset due to received host client properties response bus message");
+ mei_reset(dev, 1);
+ return;
+ }
+ } else {
+ dev_dbg(&dev->pdev->dev, "reset due to received host client properties response bus message for wrong client ID\n");
+ mei_reset(dev, 1);
+ return;
+ }
+ break;
+
+ case HOST_ENUM_RES_CMD:
+ enum_res = (struct hbm_host_enum_response *) mei_msg;
+ memcpy(dev->me_clients_map, enum_res->valid_addresses, 32);
+ if (dev->mei_state == MEI_INIT_CLIENTS &&
+ dev->init_clients_state == MEI_ENUM_CLIENTS_MESSAGE) {
+ dev->init_clients_timer = 0;
+ dev->me_client_presentation_num = 0;
+ dev->me_client_index = 0;
+ allocate_me_clients_storage(dev);
+ dev->init_clients_state =
+ MEI_CLIENT_PROPERTIES_MESSAGE;
+ host_client_properties(dev);
+ } else {
+ dev_dbg(&dev->pdev->dev, "reset due to received host enumeration clients response bus message.\n");
+ mei_reset(dev, 1);
+ return;
+ }
+ break;
+
+ case HOST_STOP_RES_CMD:
+ dev->mei_state = MEI_DISABLED;
+ dev_dbg(&dev->pdev->dev, "resetting because of FW stop response.\n");
+ mei_reset(dev, 1);
+ break;
+
+ case CLIENT_DISCONNECT_REQ_CMD:
+ /* search for client */
+ disconnect_req =
+ (struct hbm_client_disconnect_request *) mei_msg;
+ mei_client_disconnect_request(dev, disconnect_req);
+ break;
+
+ case ME_STOP_REQ_CMD:
+ /* prepare stop request */
+ mei_hdr = (struct mei_msg_hdr *) &dev->ext_msg_buf[0];
+ mei_hdr->host_addr = 0;
+ mei_hdr->me_addr = 0;
+ mei_hdr->length = sizeof(struct hbm_host_stop_request);
+ mei_hdr->msg_complete = 1;
+ mei_hdr->reserved = 0;
+ host_stop_req =
+ (struct hbm_host_stop_request *) &dev->ext_msg_buf[1];
+ memset(host_stop_req, 0, sizeof(struct hbm_host_stop_request));
+ host_stop_req->cmd.cmd = HOST_STOP_REQ_CMD;
+ host_stop_req->reason = DRIVER_STOP_REQUEST;
+ host_stop_req->reserved[0] = 0;
+ host_stop_req->reserved[1] = 0;
+ dev->extra_write_index = 2;
+ break;
+
+ default:
+ BUG();
+ break;
+
+ }
+}
+
+
+/**
+ * _mei_hb_read - processes read related operation.
+ *
+ * @dev: the device structure.
+ * @slots: free slots.
+ * @cb_pos: callback block.
+ * @cl: private data of the file object.
+ * @cmpl_list: complete list.
+ *
+ * returns 0, OK; otherwise, error.
+ */
+static int _mei_irq_thread_read(struct mei_device *dev, s32 *slots,
+ struct mei_cl_cb *cb_pos,
+ struct mei_cl *cl,
+ struct mei_io_list *cmpl_list)
+{
+ if ((*slots * sizeof(u32)) >= (sizeof(struct mei_msg_hdr) +
+ sizeof(struct hbm_flow_control))) {
+ *slots -= (sizeof(struct mei_msg_hdr) +
+ sizeof(struct hbm_flow_control) + 3) / 4;
+ if (!mei_send_flow_control(dev, cl)) {
+ cl->status = -ENODEV;
+ cb_pos->information = 0;
+ list_move_tail(&cb_pos->cb_list,
+ &cmpl_list->mei_cb.cb_list);
+ return -ENODEV;
+ } else {
+ list_move_tail(&cb_pos->cb_list,
+ &dev->read_list.mei_cb.cb_list);
+ }
+ } else {
+ /* return the cancel routine */
+ list_del(&cb_pos->cb_list);
+ return -EBADMSG;
+ }
+
+ return 0;
+}
+
+
+/**
+ * _mei_irq_thread_ioctl - processes ioctl related operation.
+ *
+ * @dev: the device structure.
+ * @slots: free slots.
+ * @cb_pos: callback block.
+ * @cl: private data of the file object.
+ * @cmpl_list: complete list.
+ *
+ * returns 0, OK; otherwise, error.
+ */
+static int _mei_irq_thread_ioctl(struct mei_device *dev, s32 *slots,
+ struct mei_cl_cb *cb_pos,
+ struct mei_cl *cl,
+ struct mei_io_list *cmpl_list)
+{
+ if ((*slots * sizeof(u32)) >= (sizeof(struct mei_msg_hdr) +
+ sizeof(struct hbm_client_connect_request))) {
+ cl->state = MEI_FILE_CONNECTING;
+ *slots -= (sizeof(struct mei_msg_hdr) +
+ sizeof(struct hbm_client_connect_request) + 3) / 4;
+ if (!mei_connect(dev, cl)) {
+ cl->status = -ENODEV;
+ cb_pos->information = 0;
+ list_del(&cb_pos->cb_list);
+ return -ENODEV;
+ } else {
+ list_move_tail(&cb_pos->cb_list,
+ &dev->ctrl_rd_list.mei_cb.cb_list);
+ cl->timer_count = MEI_CONNECT_TIMEOUT;
+ }
+ } else {
+ /* return the cancel routine */
+ list_del(&cb_pos->cb_list);
+ return -EBADMSG;
+ }
+
+ return 0;
+}
+
+/**
+ * _mei_irq_thread_cmpl - processes completed and no-iamthif operation.
+ *
+ * @dev: the device structure.
+ * @slots: free slots.
+ * @cb_pos: callback block.
+ * @cl: private data of the file object.
+ * @cmpl_list: complete list.
+ *
+ * returns 0, OK; otherwise, error.
+ */
+static int _mei_irq_thread_cmpl(struct mei_device *dev, s32 *slots,
+ struct mei_cl_cb *cb_pos,
+ struct mei_cl *cl,
+ struct mei_io_list *cmpl_list)
+{
+ struct mei_msg_hdr *mei_hdr;
+
+ if ((*slots * sizeof(u32)) >= (sizeof(struct mei_msg_hdr) +
+ (cb_pos->request_buffer.size -
+ cb_pos->information))) {
+ mei_hdr = (struct mei_msg_hdr *) &dev->wr_msg_buf[0];
+ mei_hdr->host_addr = cl->host_client_id;
+ mei_hdr->me_addr = cl->me_client_id;
+ mei_hdr->length = cb_pos->request_buffer.size -
+ cb_pos->information;
+ mei_hdr->msg_complete = 1;
+ mei_hdr->reserved = 0;
+ dev_dbg(&dev->pdev->dev, "cb_pos->request_buffer.size =%d"
+ "mei_hdr->msg_complete = %d\n",
+ cb_pos->request_buffer.size,
+ mei_hdr->msg_complete);
+ dev_dbg(&dev->pdev->dev, "cb_pos->information =%lu\n",
+ cb_pos->information);
+ dev_dbg(&dev->pdev->dev, "mei_hdr->length =%d\n",
+ mei_hdr->length);
+ *slots -= (sizeof(struct mei_msg_hdr) +
+ mei_hdr->length + 3) / 4;
+ if (!mei_write_message(dev, mei_hdr,
+ (unsigned char *)
+ (cb_pos->request_buffer.data +
+ cb_pos->information),
+ mei_hdr->length)) {
+ cl->status = -ENODEV;
+ list_move_tail(&cb_pos->cb_list,
+ &cmpl_list->mei_cb.cb_list);
+ return -ENODEV;
+ } else {
+ if (mei_flow_ctrl_reduce(dev, cl))
+ return -ENODEV;
+ cl->status = 0;
+ cb_pos->information += mei_hdr->length;
+ list_move_tail(&cb_pos->cb_list,
+ &dev->write_waiting_list.mei_cb.cb_list);
+ }
+ } else if (*slots == ((dev->host_hw_state & H_CBD) >> 24)) {
+ /* buffer is still empty */
+ mei_hdr = (struct mei_msg_hdr *) &dev->wr_msg_buf[0];
+ mei_hdr->host_addr = cl->host_client_id;
+ mei_hdr->me_addr = cl->me_client_id;
+ mei_hdr->length =
+ (*slots * sizeof(u32)) - sizeof(struct mei_msg_hdr);
+ mei_hdr->msg_complete = 0;
+ mei_hdr->reserved = 0;
+
+ (*slots) -= (sizeof(struct mei_msg_hdr) +
+ mei_hdr->length + 3) / 4;
+ if (!mei_write_message(dev, mei_hdr,
+ (unsigned char *)
+ (cb_pos->request_buffer.data +
+ cb_pos->information),
+ mei_hdr->length)) {
+ cl->status = -ENODEV;
+ list_move_tail(&cb_pos->cb_list,
+ &cmpl_list->mei_cb.cb_list);
+ return -ENODEV;
+ } else {
+ cb_pos->information += mei_hdr->length;
+ dev_dbg(&dev->pdev->dev,
+ "cb_pos->request_buffer.size =%d"
+ " mei_hdr->msg_complete = %d\n",
+ cb_pos->request_buffer.size,
+ mei_hdr->msg_complete);
+ dev_dbg(&dev->pdev->dev, "cb_pos->information =%lu\n",
+ cb_pos->information);
+ dev_dbg(&dev->pdev->dev, "mei_hdr->length =%d\n",
+ mei_hdr->length);
+ }
+ return -EMSGSIZE;
+ } else {
+ return -EBADMSG;
+ }
+
+ return 0;
+}
+
+/**
+ * _mei_irq_thread_cmpl_iamthif - processes completed iamthif operation.
+ *
+ * @dev: the device structure.
+ * @slots: free slots.
+ * @cb_pos: callback block.
+ * @cl: private data of the file object.
+ * @cmpl_list: complete list.
+ *
+ * returns 0, OK; otherwise, error.
+ */
+static int _mei_irq_thread_cmpl_iamthif(struct mei_device *dev, s32 *slots,
+ struct mei_cl_cb *cb_pos,
+ struct mei_cl *cl,
+ struct mei_io_list *cmpl_list)
+{
+ struct mei_msg_hdr *mei_hdr;
+
+ if ((*slots * sizeof(u32)) >= (sizeof(struct mei_msg_hdr) +
+ dev->iamthif_msg_buf_size -
+ dev->iamthif_msg_buf_index)) {
+ mei_hdr = (struct mei_msg_hdr *) &dev->wr_msg_buf[0];
+ mei_hdr->host_addr = cl->host_client_id;
+ mei_hdr->me_addr = cl->me_client_id;
+ mei_hdr->length = dev->iamthif_msg_buf_size -
+ dev->iamthif_msg_buf_index;
+ mei_hdr->msg_complete = 1;
+ mei_hdr->reserved = 0;
+
+ *slots -= (sizeof(struct mei_msg_hdr) +
+ mei_hdr->length + 3) / 4;
+
+ if (!mei_write_message(dev, mei_hdr,
+ (dev->iamthif_msg_buf +
+ dev->iamthif_msg_buf_index),
+ mei_hdr->length)) {
+ dev->iamthif_state = MEI_IAMTHIF_IDLE;
+ cl->status = -ENODEV;
+ list_del(&cb_pos->cb_list);
+ return -ENODEV;
+ } else {
+ if (mei_flow_ctrl_reduce(dev, cl))
+ return -ENODEV;
+ dev->iamthif_msg_buf_index += mei_hdr->length;
+ cb_pos->information = dev->iamthif_msg_buf_index;
+ cl->status = 0;
+ dev->iamthif_state = MEI_IAMTHIF_FLOW_CONTROL;
+ dev->iamthif_flow_control_pending = 1;
+ /* save iamthif cb sent to amthi client */
+ dev->iamthif_current_cb = cb_pos;
+ list_move_tail(&cb_pos->cb_list,
+ &dev->write_waiting_list.mei_cb.cb_list);
+
+ }
+ } else if (*slots == ((dev->host_hw_state & H_CBD) >> 24)) {
+ /* buffer is still empty */
+ mei_hdr = (struct mei_msg_hdr *) &dev->wr_msg_buf[0];
+ mei_hdr->host_addr = cl->host_client_id;
+ mei_hdr->me_addr = cl->me_client_id;
+ mei_hdr->length =
+ (*slots * sizeof(u32)) - sizeof(struct mei_msg_hdr);
+ mei_hdr->msg_complete = 0;
+ mei_hdr->reserved = 0;
+
+ *slots -= (sizeof(struct mei_msg_hdr) +
+ mei_hdr->length + 3) / 4;
+
+ if (!mei_write_message(dev, mei_hdr,
+ (dev->iamthif_msg_buf +
+ dev->iamthif_msg_buf_index),
+ mei_hdr->length)) {
+ cl->status = -ENODEV;
+ list_del(&cb_pos->cb_list);
+ } else {
+ dev->iamthif_msg_buf_index += mei_hdr->length;
+ }
+ return -EMSGSIZE;
+ } else {
+ return -EBADMSG;
+ }
+
+ return 0;
+}
+
+/**
+ * mei_irq_thread_read_handler - bottom half read routine after ISR to
+ * handle the read processing.
+ *
+ * @cmpl_list: An instance of our list structure
+ * @dev: the device structure
+ * @slots: slots to read.
+ *
+ * returns 0 on success, <0 on failure.
+ */
+static int mei_irq_thread_read_handler(struct mei_io_list *cmpl_list,
+ struct mei_device *dev,
+ s32 *slots)
+{
+ struct mei_msg_hdr *mei_hdr;
+ struct mei_cl *cl_pos = NULL;
+ struct mei_cl *cl_next = NULL;
+ int ret = 0;
+
+ if (!dev->rd_msg_hdr) {
+ dev->rd_msg_hdr = mei_mecbrw_read(dev);
+ dev_dbg(&dev->pdev->dev, "slots =%08x.\n", *slots);
+ (*slots)--;
+ dev_dbg(&dev->pdev->dev, "slots =%08x.\n", *slots);
+ }
+ mei_hdr = (struct mei_msg_hdr *) &dev->rd_msg_hdr;
+ dev_dbg(&dev->pdev->dev, "mei_hdr->length =%d\n", mei_hdr->length);
+
+ if (mei_hdr->reserved || !dev->rd_msg_hdr) {
+ dev_dbg(&dev->pdev->dev, "corrupted message header.\n");
+ ret = -EBADMSG;
+ goto end;
+ }
+
+ if (mei_hdr->host_addr || mei_hdr->me_addr) {
+ list_for_each_entry_safe(cl_pos, cl_next,
+ &dev->file_list, link) {
+ dev_dbg(&dev->pdev->dev,
+ "list_for_each_entry_safe read host"
+ " client = %d, ME client = %d\n",
+ cl_pos->host_client_id,
+ cl_pos->me_client_id);
+ if (cl_pos->host_client_id == mei_hdr->host_addr &&
+ cl_pos->me_client_id == mei_hdr->me_addr)
+ break;
+ }
+
+ if (&cl_pos->link == &dev->file_list) {
+ dev_dbg(&dev->pdev->dev, "corrupted message header\n");
+ ret = -EBADMSG;
+ goto end;
+ }
+ }
+ if (((*slots) * sizeof(u32)) < mei_hdr->length) {
+ dev_dbg(&dev->pdev->dev,
+ "we can't read the message slots =%08x.\n",
+ *slots);
+ /* we can't read the message */
+ ret = -ERANGE;
+ goto end;
+ }
+
+ /* decide where to read the message too */
+ if (!mei_hdr->host_addr) {
+ dev_dbg(&dev->pdev->dev, "call mei_irq_thread_read_bus_message.\n");
+ mei_irq_thread_read_bus_message(dev, mei_hdr);
+ dev_dbg(&dev->pdev->dev, "end mei_irq_thread_read_bus_message.\n");
+ } else if (mei_hdr->host_addr == dev->iamthif_cl.host_client_id &&
+ (MEI_FILE_CONNECTED == dev->iamthif_cl.state) &&
+ (dev->iamthif_state == MEI_IAMTHIF_READING)) {
+ dev_dbg(&dev->pdev->dev, "call mei_irq_thread_read_iamthif_message.\n");
+ dev_dbg(&dev->pdev->dev, "mei_hdr->length =%d\n",
+ mei_hdr->length);
+ ret = mei_irq_thread_read_amthi_message(cmpl_list,
+ dev, mei_hdr);
+ if (ret)
+ goto end;
+
+ } else {
+ dev_dbg(&dev->pdev->dev, "call mei_irq_thread_read_client_message.\n");
+ ret = mei_irq_thread_read_client_message(cmpl_list,
+ dev, mei_hdr);
+ if (ret)
+ goto end;
+
+ }
+
+ /* reset the number of slots and header */
+ *slots = mei_count_full_read_slots(dev);
+ dev->rd_msg_hdr = 0;
+
+ if (*slots == -EOVERFLOW) {
+ /* overflow - reset */
+ dev_dbg(&dev->pdev->dev, "resetting due to slots overflow.\n");
+ /* set the event since message has been read */
+ ret = -ERANGE;
+ goto end;
+ }
+end:
+ return ret;
+}
+
+
+/**
+ * mei_irq_thread_write_handler - bottom half write routine after
+ * ISR to handle the write processing.
+ *
+ * @cmpl_list: An instance of our list structure
+ * @dev: the device structure
+ * @slots: slots to write.
+ *
+ * returns 0 on success, <0 on failure.
+ */
+static int mei_irq_thread_write_handler(struct mei_io_list *cmpl_list,
+ struct mei_device *dev,
+ s32 *slots)
+{
+
+ struct mei_cl *cl;
+ struct mei_cl_cb *cb_pos = NULL, *cb_next = NULL;
+ struct mei_io_list *list;
+ int ret;
+
+ if (!mei_host_buffer_is_empty(dev)) {
+ dev_dbg(&dev->pdev->dev, "host buffer is not empty.\n");
+ return 0;
+ }
+ dev->write_hang = -1;
+ *slots = mei_count_empty_write_slots(dev);
+ /* complete all waiting for write CB */
+ dev_dbg(&dev->pdev->dev, "complete all waiting for write cb.\n");
+
+ list = &dev->write_waiting_list;
+ if (!list->status && !list_empty(&list->mei_cb.cb_list)) {
+ list_for_each_entry_safe(cb_pos, cb_next,
+ &list->mei_cb.cb_list, cb_list) {
+ cl = (struct mei_cl *)cb_pos->file_private;
+ if (cl) {
+ cl->status = 0;
+ list_del(&cb_pos->cb_list);
+ if (MEI_WRITING == cl->writing_state &&
+ (cb_pos->major_file_operations ==
+ MEI_WRITE) &&
+ (cl != &dev->iamthif_cl)) {
+ dev_dbg(&dev->pdev->dev,
+ "MEI WRITE COMPLETE\n");
+ cl->writing_state =
+ MEI_WRITE_COMPLETE;
+ list_add_tail(&cb_pos->cb_list,
+ &cmpl_list->mei_cb.cb_list);
+ }
+ if (cl == &dev->iamthif_cl) {
+ dev_dbg(&dev->pdev->dev, "check iamthif flow control.\n");
+ if (dev->iamthif_flow_control_pending) {
+ ret =
+ _mei_irq_thread_iamthif_read(
+ dev, slots);
+ if (ret)
+ return ret;
+ }
+ }
+ }
+
+ }
+ }
+
+ if (dev->stop && !dev->wd_pending) {
+ dev->wd_stopped = 1;
+ wake_up_interruptible(&dev->wait_stop_wd);
+ return 0;
+ }
+
+ if (dev->extra_write_index) {
+ dev_dbg(&dev->pdev->dev, "extra_write_index =%d.\n",
+ dev->extra_write_index);
+ mei_write_message(dev,
+ (struct mei_msg_hdr *) &dev->ext_msg_buf[0],
+ (unsigned char *) &dev->ext_msg_buf[1],
+ (dev->extra_write_index - 1) * sizeof(u32));
+ *slots -= dev->extra_write_index;
+ dev->extra_write_index = 0;
+ }
+ if (dev->mei_state == MEI_ENABLED) {
+ if (dev->wd_pending &&
+ mei_flow_ctrl_creds(dev, &dev->wd_cl) > 0) {
+ if (mei_wd_send(dev))
+ dev_dbg(&dev->pdev->dev, "wd send failed.\n");
+ else
+ if (mei_flow_ctrl_reduce(dev, &dev->wd_cl))
+ return -ENODEV;
+
+ dev->wd_pending = 0;
+
+ if (dev->wd_timeout) {
+ *slots -= (sizeof(struct mei_msg_hdr) +
+ MEI_START_WD_DATA_SIZE + 3) / 4;
+ dev->wd_due_counter = 2;
+ } else {
+ *slots -= (sizeof(struct mei_msg_hdr) +
+ MEI_WD_PARAMS_SIZE + 3) / 4;
+ dev->wd_due_counter = 0;
+ }
+
+ }
+ }
+ if (dev->stop)
+ return ~ENODEV;
+
+ /* complete control write list CB */
+ if (!dev->ctrl_wr_list.status) {
+ /* complete control write list CB */
+ dev_dbg(&dev->pdev->dev, "complete control write list cb.\n");
+ list_for_each_entry_safe(cb_pos, cb_next,
+ &dev->ctrl_wr_list.mei_cb.cb_list, cb_list) {
+ cl = (struct mei_cl *)
+ cb_pos->file_private;
+ if (!cl) {
+ list_del(&cb_pos->cb_list);
+ return -ENODEV;
+ }
+ switch (cb_pos->major_file_operations) {
+ case MEI_CLOSE:
+ /* send disconnect message */
+ ret = _mei_irq_thread_close(dev, slots,
+ cb_pos, cl, cmpl_list);
+ if (ret)
+ return ret;
+
+ break;
+ case MEI_READ:
+ /* send flow control message */
+ ret = _mei_irq_thread_read(dev, slots,
+ cb_pos, cl, cmpl_list);
+ if (ret)
+ return ret;
+
+ break;
+ case MEI_IOCTL:
+ /* connect message */
+ if (!mei_other_client_is_connecting(dev,
+ cl))
+ continue;
+ ret = _mei_irq_thread_ioctl(dev, slots,
+ cb_pos, cl, cmpl_list);
+ if (ret)
+ return ret;
+
+ break;
+
+ default:
+ BUG();
+ }
+
+ }
+ }
+ /* complete write list CB */
+ if (!dev->write_list.status &&
+ !list_empty(&dev->write_list.mei_cb.cb_list)) {
+ dev_dbg(&dev->pdev->dev, "complete write list cb.\n");
+ list_for_each_entry_safe(cb_pos, cb_next,
+ &dev->write_list.mei_cb.cb_list, cb_list) {
+ cl = (struct mei_cl *)cb_pos->file_private;
+
+ if (cl) {
+ if (cl != &dev->iamthif_cl) {
+ if (!mei_flow_ctrl_creds(dev,
+ cl)) {
+ dev_dbg(&dev->pdev->dev,
+ "No flow control"
+ " credentials for client"
+ " %d, not sending.\n",
+ cl->host_client_id);
+ continue;
+ }
+ ret = _mei_irq_thread_cmpl(dev, slots,
+ cb_pos,
+ cl, cmpl_list);
+ if (ret)
+ return ret;
+
+ } else if (cl == &dev->iamthif_cl) {
+ /* IAMTHIF IOCTL */
+ dev_dbg(&dev->pdev->dev, "complete amthi write cb.\n");
+ if (!mei_flow_ctrl_creds(dev,
+ cl)) {
+ dev_dbg(&dev->pdev->dev,
+ "No flow control"
+ " credentials for amthi"
+ " client %d.\n",
+ cl->host_client_id);
+ continue;
+ }
+ ret = _mei_irq_thread_cmpl_iamthif(dev,
+ slots,
+ cb_pos,
+ cl,
+ cmpl_list);
+ if (ret)
+ return ret;
+
+ }
+ }
+
+ }
+ }
+ return 0;
+}
+
+
+
+/**
+ * mei_timer - timer function.
+ *
+ * @work: pointer to the work_struct structure
+ *
+ * NOTE: This function is called by timer interrupt work
+ */
+void mei_wd_timer(struct work_struct *work)
+{
+ unsigned long timeout;
+ struct mei_cl *cl_pos = NULL;
+ struct mei_cl *cl_next = NULL;
+ struct list_head *amthi_complete_list = NULL;
+ struct mei_cl_cb *cb_pos = NULL;
+ struct mei_cl_cb *cb_next = NULL;
+
+ struct mei_device *dev = container_of(work,
+ struct mei_device, wd_work.work);
+
+
+ mutex_lock(&dev->device_lock);
+ if (dev->mei_state != MEI_ENABLED) {
+ if (dev->mei_state == MEI_INIT_CLIENTS) {
+ if (dev->init_clients_timer) {
+ if (--dev->init_clients_timer == 0) {
+ dev_dbg(&dev->pdev->dev, "IMEI reset due to init clients timeout ,init clients state = %d.\n",
+ dev->init_clients_state);
+ mei_reset(dev, 1);
+ }
+ }
+ }
+ goto out;
+ }
+ /*** connect/disconnect timeouts ***/
+ list_for_each_entry_safe(cl_pos, cl_next, &dev->file_list, link) {
+ if (cl_pos->timer_count) {
+ if (--cl_pos->timer_count == 0) {
+ dev_dbg(&dev->pdev->dev, "HECI reset due to connect/disconnect timeout.\n");
+ mei_reset(dev, 1);
+ goto out;
+ }
+ }
+ }
+
+ if (dev->wd_cl.state != MEI_FILE_CONNECTED)
+ goto out;
+
+ /* Watchdog */
+ if (dev->wd_due_counter && !dev->wd_bypass) {
+ if (--dev->wd_due_counter == 0) {
+ if (dev->mei_host_buffer_is_empty &&
+ mei_flow_ctrl_creds(dev, &dev->wd_cl) > 0) {
+ dev->mei_host_buffer_is_empty = 0;
+ dev_dbg(&dev->pdev->dev, "send watchdog.\n");
+
+ if (mei_wd_send(dev))
+ dev_dbg(&dev->pdev->dev, "wd send failed.\n");
+ else
+ if (mei_flow_ctrl_reduce(dev, &dev->wd_cl))
+ goto out;
+
+ if (dev->wd_timeout)
+ dev->wd_due_counter = 2;
+ else
+ dev->wd_due_counter = 0;
+
+ } else
+ dev->wd_pending = 1;
+
+ }
+ }
+ if (dev->iamthif_stall_timer) {
+ if (--dev->iamthif_stall_timer == 0) {
+ dev_dbg(&dev->pdev->dev, "reseting because of hang to amthi.\n");
+ mei_reset(dev, 1);
+ dev->iamthif_msg_buf_size = 0;
+ dev->iamthif_msg_buf_index = 0;
+ dev->iamthif_canceled = 0;
+ dev->iamthif_ioctl = 1;
+ dev->iamthif_state = MEI_IAMTHIF_IDLE;
+ dev->iamthif_timer = 0;
+
+ if (dev->iamthif_current_cb)
+ mei_free_cb_private(dev->iamthif_current_cb);
+
+ dev->iamthif_file_object = NULL;
+ dev->iamthif_current_cb = NULL;
+ run_next_iamthif_cmd(dev);
+ }
+ }
+
+ if (dev->iamthif_timer) {
+
+ timeout = dev->iamthif_timer +
+ msecs_to_jiffies(IAMTHIF_READ_TIMER);
+
+ dev_dbg(&dev->pdev->dev, "dev->iamthif_timer = %ld\n",
+ dev->iamthif_timer);
+ dev_dbg(&dev->pdev->dev, "timeout = %ld\n", timeout);
+ dev_dbg(&dev->pdev->dev, "jiffies = %ld\n", jiffies);
+ if (time_after(jiffies, timeout)) {
+ /*
+ * User didn't read the AMTHI data on time (15sec)
+ * freeing AMTHI for other requests
+ */
+
+ dev_dbg(&dev->pdev->dev, "freeing AMTHI for other requests\n");
+
+ amthi_complete_list = &dev->amthi_read_complete_list.
+ mei_cb.cb_list;
+
+ if (!list_empty(amthi_complete_list)) {
+
+ list_for_each_entry_safe(cb_pos, cb_next,
+ amthi_complete_list,
+ cb_list) {
+
+ cl_pos = cb_pos->file_object->private_data;
+
+ /* Finding the AMTHI entry. */
+ if (cl_pos == &dev->iamthif_cl)
+ list_del(&cb_pos->cb_list);
+ }
+ }
+ if (dev->iamthif_current_cb)
+ mei_free_cb_private(dev->iamthif_current_cb);
+
+ dev->iamthif_file_object->private_data = NULL;
+ dev->iamthif_file_object = NULL;
+ dev->iamthif_current_cb = NULL;
+ dev->iamthif_timer = 0;
+ run_next_iamthif_cmd(dev);
+
+ }
+ }
+out:
+ schedule_delayed_work(&dev->wd_work, 2 * HZ);
+ mutex_unlock(&dev->device_lock);
+}
+
+/**
+ * mei_interrupt_thread_handler - function called after ISR to handle the interrupt
+ * processing.
+ *
+ * @irq: The irq number
+ * @dev_id: pointer to the device structure
+ *
+ * returns irqreturn_t
+ *
+ */
+irqreturn_t mei_interrupt_thread_handler(int irq, void *dev_id)
+{
+ struct mei_device *dev = (struct mei_device *) dev_id;
+ struct mei_io_list complete_list;
+ struct mei_cl_cb *cb_pos = NULL, *cb_next = NULL;
+ struct mei_cl *cl;
+ s32 slots;
+ int rets;
+ bool bus_message_received;
+
+
+ dev_dbg(&dev->pdev->dev, "function called after ISR to handle the interrupt processing.\n");
+ /* initialize our complete list */
+ mutex_lock(&dev->device_lock);
+ mei_initialize_list(&complete_list, dev);
+ dev->host_hw_state = mei_hcsr_read(dev);
+ dev->me_hw_state = mei_mecsr_read(dev);
+
+ /* check if ME wants a reset */
+ if ((dev->me_hw_state & ME_RDY_HRA) == 0 &&
+ dev->mei_state != MEI_RESETING &&
+ dev->mei_state != MEI_INITIALIZING) {
+ dev_dbg(&dev->pdev->dev, "FW not ready.\n");
+ mei_reset(dev, 1);
+ mutex_unlock(&dev->device_lock);
+ return IRQ_HANDLED;
+ }
+
+ /* check if we need to start the dev */
+ if ((dev->host_hw_state & H_RDY) == 0) {
+ if ((dev->me_hw_state & ME_RDY_HRA) == ME_RDY_HRA) {
+ dev_dbg(&dev->pdev->dev, "we need to start the dev.\n");
+ dev->host_hw_state |= (H_IE | H_IG | H_RDY);
+ mei_hcsr_set(dev);
+ dev->mei_state = MEI_INIT_CLIENTS;
+ dev_dbg(&dev->pdev->dev, "link is established start sending messages.\n");
+ /* link is established
+ * start sending messages.
+ */
+ host_start_message(dev);
+ mutex_unlock(&dev->device_lock);
+ return IRQ_HANDLED;
+ } else {
+ dev_dbg(&dev->pdev->dev, "FW not ready.\n");
+ mutex_unlock(&dev->device_lock);
+ return IRQ_HANDLED;
+ }
+ }
+ /* check slots avalable for reading */
+ slots = mei_count_full_read_slots(dev);
+ dev_dbg(&dev->pdev->dev, "slots =%08x extra_write_index =%08x.\n",
+ slots, dev->extra_write_index);
+ while (slots > 0 && !dev->extra_write_index) {
+ dev_dbg(&dev->pdev->dev, "slots =%08x extra_write_index =%08x.\n",
+ slots, dev->extra_write_index);
+ dev_dbg(&dev->pdev->dev, "call mei_irq_thread_read_handler.\n");
+ rets = mei_irq_thread_read_handler(&complete_list, dev, &slots);
+ if (rets)
+ goto end;
+ }
+ rets = mei_irq_thread_write_handler(&complete_list, dev, &slots);
+end:
+ dev_dbg(&dev->pdev->dev, "end of bottom half function.\n");
+ dev->host_hw_state = mei_hcsr_read(dev);
+ dev->mei_host_buffer_is_empty = mei_host_buffer_is_empty(dev);
+
+ bus_message_received = false;
+ if (dev->recvd_msg && waitqueue_active(&dev->wait_recvd_msg)) {
+ dev_dbg(&dev->pdev->dev, "received waiting bus message\n");
+ bus_message_received = true;
+ }
+ mutex_unlock(&dev->device_lock);
+ if (bus_message_received) {
+ dev_dbg(&dev->pdev->dev, "wake up dev->wait_recvd_msg\n");
+ wake_up_interruptible(&dev->wait_recvd_msg);
+ bus_message_received = false;
+ }
+ if (complete_list.status || list_empty(&complete_list.mei_cb.cb_list))
+ return IRQ_HANDLED;
+
+
+ list_for_each_entry_safe(cb_pos, cb_next,
+ &complete_list.mei_cb.cb_list, cb_list) {
+ cl = (struct mei_cl *)cb_pos->file_private;
+ list_del(&cb_pos->cb_list);
+ if (cl) {
+ if (cl != &dev->iamthif_cl) {
+ dev_dbg(&dev->pdev->dev, "completing call back.\n");
+ _mei_cmpl(cl, cb_pos);
+ cb_pos = NULL;
+ } else if (cl == &dev->iamthif_cl) {
+ _mei_cmpl_iamthif(dev, cb_pos);
+ }
+ }
+ }
+ return IRQ_HANDLED;
+}
diff --git a/drivers/staging/mei/iorw.c b/drivers/staging/mei/iorw.c
new file mode 100644
index 0000000..697a277
--- /dev/null
+++ b/drivers/staging/mei/iorw.c
@@ -0,0 +1,604 @@
+/*
+ *
+ * Intel Management Engine Interface (Intel MEI) Linux driver
+ * Copyright (c) 2003-2011, Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+
+
+#include <linux/kernel.h>
+#include <linux/fs.h>
+#include <linux/errno.h>
+#include <linux/types.h>
+#include <linux/fcntl.h>
+#include <linux/aio.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <linux/ioctl.h>
+#include <linux/cdev.h>
+#include <linux/list.h>
+#include <linux/delay.h>
+#include <linux/sched.h>
+#include <linux/uuid.h>
+#include <linux/jiffies.h>
+#include <linux/uaccess.h>
+
+
+#include "mei_dev.h"
+#include "hw.h"
+#include "mei.h"
+#include "interface.h"
+#include "mei_version.h"
+
+
+
+/**
+ * mei_ioctl_connect_client - the connect to fw client IOCTL function
+ *
+ * @dev: the device structure
+ * @data: IOCTL connect data, input and output parameters
+ * @file: private data of the file object
+ *
+ * Locking: called under "dev->device_lock" lock
+ *
+ * returns 0 on success, <0 on failure.
+ */
+int mei_ioctl_connect_client(struct file *file,
+ struct mei_connect_client_data *data)
+{
+ struct mei_device *dev;
+ struct mei_cl_cb *cb;
+ struct mei_client *client;
+ struct mei_cl *cl;
+ struct mei_cl *cl_pos = NULL;
+ struct mei_cl *cl_next = NULL;
+ long timeout = CONNECT_TIMEOUT;
+ int i;
+ int err;
+ int rets;
+
+ cl = file->private_data;
+ if (WARN_ON(!cl || !cl->dev))
+ return -ENODEV;
+
+ dev = cl->dev;
+
+ dev_dbg(&dev->pdev->dev, "mei_ioctl_connect_client() Entry\n");
+
+
+ /* buffered ioctl cb */
+ cb = kzalloc(sizeof(struct mei_cl_cb), GFP_KERNEL);
+ if (!cb) {
+ rets = -ENOMEM;
+ goto end;
+ }
+ INIT_LIST_HEAD(&cb->cb_list);
+
+ cb->major_file_operations = MEI_IOCTL;
+
+ if (dev->mei_state != MEI_ENABLED) {
+ rets = -ENODEV;
+ goto end;
+ }
+ if (cl->state != MEI_FILE_INITIALIZING &&
+ cl->state != MEI_FILE_DISCONNECTED) {
+ rets = -EBUSY;
+ goto end;
+ }
+
+ /* find ME client we're trying to connect to */
+ i = mei_find_me_client_index(dev, data->in_client_uuid);
+ if (i >= 0 && !dev->me_clients[i].props.fixed_address) {
+ cl->me_client_id = dev->me_clients[i].client_id;
+ cl->state = MEI_FILE_CONNECTING;
+ }
+
+ dev_dbg(&dev->pdev->dev, "Connect to FW Client ID = %d\n",
+ cl->me_client_id);
+ dev_dbg(&dev->pdev->dev, "FW Client - Protocol Version = %d\n",
+ dev->me_clients[i].props.protocol_version);
+ dev_dbg(&dev->pdev->dev, "FW Client - Max Msg Len = %d\n",
+ dev->me_clients[i].props.max_msg_length);
+
+ /* if we're connecting to amthi client so we will use the exist
+ * connection
+ */
+ if (uuid_le_cmp(data->in_client_uuid, mei_amthi_guid) == 0) {
+ dev_dbg(&dev->pdev->dev, "FW Client is amthi\n");
+ if (dev->iamthif_cl.state != MEI_FILE_CONNECTED) {
+ rets = -ENODEV;
+ goto end;
+ }
+ clear_bit(cl->host_client_id, dev->host_clients_map);
+ list_for_each_entry_safe(cl_pos, cl_next,
+ &dev->file_list, link) {
+ if (mei_fe_same_id(cl, cl_pos)) {
+ dev_dbg(&dev->pdev->dev,
+ "remove file private data node host"
+ " client = %d, ME client = %d.\n",
+ cl_pos->host_client_id,
+ cl_pos->me_client_id);
+ list_del(&cl_pos->link);
+ }
+
+ }
+ dev_dbg(&dev->pdev->dev, "free file private data memory.\n");
+ kfree(cl);
+
+ cl = NULL;
+ file->private_data = &dev->iamthif_cl;
+
+ client = &data->out_client_properties;
+ client->max_msg_length =
+ dev->me_clients[i].props.max_msg_length;
+ client->protocol_version =
+ dev->me_clients[i].props.protocol_version;
+ rets = dev->iamthif_cl.status;
+
+ goto end;
+ }
+
+ if (cl->state != MEI_FILE_CONNECTING) {
+ rets = -ENODEV;
+ goto end;
+ }
+
+
+ /* prepare the output buffer */
+ client = &data->out_client_properties;
+ client->max_msg_length = dev->me_clients[i].props.max_msg_length;
+ client->protocol_version = dev->me_clients[i].props.protocol_version;
+ dev_dbg(&dev->pdev->dev, "Can connect?\n");
+ if (dev->mei_host_buffer_is_empty
+ && !mei_other_client_is_connecting(dev, cl)) {
+ dev_dbg(&dev->pdev->dev, "Sending Connect Message\n");
+ dev->mei_host_buffer_is_empty = 0;
+ if (!mei_connect(dev, cl)) {
+ dev_dbg(&dev->pdev->dev, "Sending connect message - failed\n");
+ rets = -ENODEV;
+ goto end;
+ } else {
+ dev_dbg(&dev->pdev->dev, "Sending connect message - succeeded\n");
+ cl->timer_count = MEI_CONNECT_TIMEOUT;
+ cb->file_private = cl;
+ list_add_tail(&cb->cb_list,
+ &dev->ctrl_rd_list.mei_cb.
+ cb_list);
+ }
+
+
+ } else {
+ dev_dbg(&dev->pdev->dev, "Queuing the connect request due to device busy\n");
+ cb->file_private = cl;
+ dev_dbg(&dev->pdev->dev, "add connect cb to control write list.\n");
+ list_add_tail(&cb->cb_list,
+ &dev->ctrl_wr_list.mei_cb.cb_list);
+ }
+ mutex_unlock(&dev->device_lock);
+ err = wait_event_timeout(dev->wait_recvd_msg,
+ (MEI_FILE_CONNECTED == cl->state ||
+ MEI_FILE_DISCONNECTED == cl->state),
+ timeout * HZ);
+
+ mutex_lock(&dev->device_lock);
+ if (MEI_FILE_CONNECTED == cl->state) {
+ dev_dbg(&dev->pdev->dev, "successfully connected to FW client.\n");
+ rets = cl->status;
+ goto end;
+ } else {
+ dev_dbg(&dev->pdev->dev, "failed to connect to FW client.cl->state = %d.\n",
+ cl->state);
+ if (!err) {
+ dev_dbg(&dev->pdev->dev,
+ "wait_event_interruptible_timeout failed on client"
+ " connect message fw response message.\n");
+ }
+ rets = -EFAULT;
+
+ mei_flush_list(&dev->ctrl_rd_list, cl);
+ mei_flush_list(&dev->ctrl_wr_list, cl);
+ goto end;
+ }
+ rets = 0;
+end:
+ dev_dbg(&dev->pdev->dev, "free connect cb memory.");
+ kfree(cb);
+ return rets;
+}
+
+/**
+ * find_amthi_read_list_entry - finds a amthilist entry for current file
+ *
+ * @dev: the device structure
+ * @file: pointer to file object
+ *
+ * returns returned a list entry on success, NULL on failure.
+ */
+struct mei_cl_cb *find_amthi_read_list_entry(
+ struct mei_device *dev,
+ struct file *file)
+{
+ struct mei_cl *cl_temp;
+ struct mei_cl_cb *cb_pos = NULL;
+ struct mei_cl_cb *cb_next = NULL;
+
+ if (!dev->amthi_read_complete_list.status &&
+ !list_empty(&dev->amthi_read_complete_list.mei_cb.cb_list)) {
+ list_for_each_entry_safe(cb_pos, cb_next,
+ &dev->amthi_read_complete_list.mei_cb.cb_list, cb_list) {
+ cl_temp = (struct mei_cl *)cb_pos->file_private;
+ if (cl_temp && cl_temp == &dev->iamthif_cl &&
+ cb_pos->file_object == file)
+ return cb_pos;
+ }
+ }
+ return NULL;
+}
+
+/**
+ * amthi_read - read data from AMTHI client
+ *
+ * @dev: the device structure
+ * @if_num: minor number
+ * @file: pointer to file object
+ * @*ubuf: pointer to user data in user space
+ * @length: data length to read
+ * @offset: data read offset
+ *
+ * Locking: called under "dev->device_lock" lock
+ *
+ * returns
+ * returned data length on success,
+ * zero if no data to read,
+ * negative on failure.
+ */
+int amthi_read(struct mei_device *dev, struct file *file,
+ char __user *ubuf, size_t length, loff_t *offset)
+{
+ int rets;
+ int wait_ret;
+ struct mei_cl_cb *cb = NULL;
+ struct mei_cl *cl = file->private_data;
+ unsigned long timeout;
+ int i;
+
+ /* Only Posible if we are in timeout */
+ if (!cl || cl != &dev->iamthif_cl) {
+ dev_dbg(&dev->pdev->dev, "bad file ext.\n");
+ return -ETIMEDOUT;
+ }
+
+ for (i = 0; i < dev->num_mei_me_clients; i++) {
+ if (dev->me_clients[i].client_id ==
+ dev->iamthif_cl.me_client_id)
+ break;
+ }
+
+ if (i == dev->num_mei_me_clients) {
+ dev_dbg(&dev->pdev->dev, "amthi client not found.\n");
+ return -ENODEV;
+ }
+ if (WARN_ON(dev->me_clients[i].client_id != cl->me_client_id))
+ return -ENODEV;
+
+ dev_dbg(&dev->pdev->dev, "checking amthi data\n");
+ cb = find_amthi_read_list_entry(dev, file);
+
+ /* Check for if we can block or not*/
+ if (cb == NULL && file->f_flags & O_NONBLOCK)
+ return -EAGAIN;
+
+
+ dev_dbg(&dev->pdev->dev, "waiting for amthi data\n");
+ while (cb == NULL) {
+ /* unlock the Mutex */
+ mutex_unlock(&dev->device_lock);
+
+ wait_ret = wait_event_interruptible(dev->iamthif_cl.wait,
+ (cb = find_amthi_read_list_entry(dev, file)));
+
+ if (wait_ret)
+ return -ERESTARTSYS;
+
+ dev_dbg(&dev->pdev->dev, "woke up from sleep\n");
+
+ /* Locking again the Mutex */
+ mutex_lock(&dev->device_lock);
+ }
+
+
+ dev_dbg(&dev->pdev->dev, "Got amthi data\n");
+ dev->iamthif_timer = 0;
+
+ if (cb) {
+ timeout = cb->read_time +
+ msecs_to_jiffies(IAMTHIF_READ_TIMER);
+ dev_dbg(&dev->pdev->dev, "amthi timeout = %lud\n",
+ timeout);
+
+ if (time_after(jiffies, timeout)) {
+ dev_dbg(&dev->pdev->dev, "amthi Time out\n");
+ /* 15 sec for the message has expired */
+ list_del(&cb->cb_list);
+ rets = -ETIMEDOUT;
+ goto free;
+ }
+ }
+ /* if the whole message will fit remove it from the list */
+ if (cb->information >= *offset &&
+ length >= (cb->information - *offset))
+ list_del(&cb->cb_list);
+ else if (cb->information > 0 && cb->information <= *offset) {
+ /* end of the message has been reached */
+ list_del(&cb->cb_list);
+ rets = 0;
+ goto free;
+ }
+ /* else means that not full buffer will be read and do not
+ * remove message from deletion list
+ */
+
+ dev_dbg(&dev->pdev->dev, "amthi cb->response_buffer size - %d\n",
+ cb->response_buffer.size);
+ dev_dbg(&dev->pdev->dev, "amthi cb->information - %lu\n",
+ cb->information);
+
+ /* length is being turncated to PAGE_SIZE, however,
+ * the information may be longer */
+ length = min_t(size_t, length, (cb->information - *offset));
+
+ if (copy_to_user(ubuf,
+ cb->response_buffer.data + *offset,
+ length))
+ rets = -EFAULT;
+ else {
+ rets = length;
+ if ((*offset + length) < cb->information) {
+ *offset += length;
+ goto out;
+ }
+ }
+free:
+ dev_dbg(&dev->pdev->dev, "free amthi cb memory.\n");
+ *offset = 0;
+ mei_free_cb_private(cb);
+out:
+ return rets;
+}
+
+/**
+ * mei_start_read - the start read client message function.
+ *
+ * @dev: the device structure
+ * @if_num: minor number
+ * @cl: private data of the file object
+ *
+ * returns 0 on success, <0 on failure.
+ */
+int mei_start_read(struct mei_device *dev, struct mei_cl *cl)
+{
+ struct mei_cl_cb *cb;
+ int rets = 0;
+ int i;
+
+ if (cl->state != MEI_FILE_CONNECTED)
+ return -ENODEV;
+
+ if (dev->mei_state != MEI_ENABLED)
+ return -ENODEV;
+
+ dev_dbg(&dev->pdev->dev, "check if read is pending.\n");
+ if (cl->read_pending || cl->read_cb) {
+ dev_dbg(&dev->pdev->dev, "read is pending.\n");
+ return -EBUSY;
+ }
+
+ cb = kzalloc(sizeof(struct mei_cl_cb), GFP_KERNEL);
+ if (!cb)
+ return -ENOMEM;
+
+ dev_dbg(&dev->pdev->dev, "allocation call back successful. host client = %d, ME client = %d\n",
+ cl->host_client_id, cl->me_client_id);
+
+ for (i = 0; i < dev->num_mei_me_clients; i++) {
+ if (dev->me_clients[i].client_id == cl->me_client_id)
+ break;
+
+ }
+
+ if (WARN_ON(dev->me_clients[i].client_id != cl->me_client_id)) {
+ rets = -ENODEV;
+ goto unlock;
+ }
+
+ if (i == dev->num_mei_me_clients) {
+ rets = -ENODEV;
+ goto unlock;
+ }
+
+ cb->response_buffer.size = dev->me_clients[i].props.max_msg_length;
+ cb->response_buffer.data =
+ kmalloc(cb->response_buffer.size, GFP_KERNEL);
+ if (!cb->response_buffer.data) {
+ rets = -ENOMEM;
+ goto unlock;
+ }
+ dev_dbg(&dev->pdev->dev, "allocation call back data success.\n");
+ cb->major_file_operations = MEI_READ;
+ /* make sure information is zero before we start */
+ cb->information = 0;
+ cb->file_private = (void *) cl;
+ cl->read_cb = cb;
+ if (dev->mei_host_buffer_is_empty) {
+ dev->mei_host_buffer_is_empty = 0;
+ if (!mei_send_flow_control(dev, cl)) {
+ rets = -ENODEV;
+ goto unlock;
+ } else {
+ list_add_tail(&cb->cb_list,
+ &dev->read_list.mei_cb.cb_list);
+ }
+ } else {
+ list_add_tail(&cb->cb_list,
+ &dev->ctrl_wr_list.mei_cb.cb_list);
+ }
+ return rets;
+unlock:
+ mei_free_cb_private(cb);
+ return rets;
+}
+
+/**
+ * amthi_write - write iamthif data to amthi client
+ *
+ * @dev: the device structure
+ * @cb: mei call back struct
+ *
+ * returns 0 on success, <0 on failure.
+ */
+int amthi_write(struct mei_device *dev, struct mei_cl_cb *cb)
+{
+ struct mei_msg_hdr mei_hdr;
+ int ret;
+
+ if (!dev || !cb)
+ return -ENODEV;
+
+ dev_dbg(&dev->pdev->dev, "write data to amthi client.\n");
+
+ dev->iamthif_state = MEI_IAMTHIF_WRITING;
+ dev->iamthif_current_cb = cb;
+ dev->iamthif_file_object = cb->file_object;
+ dev->iamthif_canceled = 0;
+ dev->iamthif_ioctl = 1;
+ dev->iamthif_msg_buf_size = cb->request_buffer.size;
+ memcpy(dev->iamthif_msg_buf, cb->request_buffer.data,
+ cb->request_buffer.size);
+
+ ret = mei_flow_ctrl_creds(dev, &dev->iamthif_cl);
+ if (ret < 0)
+ return ret;
+
+ if (ret && dev->mei_host_buffer_is_empty) {
+ ret = 0;
+ dev->mei_host_buffer_is_empty = 0;
+ if (cb->request_buffer.size >
+ (((dev->host_hw_state & H_CBD) >> 24) * sizeof(u32))
+ -sizeof(struct mei_msg_hdr)) {
+ mei_hdr.length =
+ (((dev->host_hw_state & H_CBD) >> 24) *
+ sizeof(u32)) - sizeof(struct mei_msg_hdr);
+ mei_hdr.msg_complete = 0;
+ } else {
+ mei_hdr.length = cb->request_buffer.size;
+ mei_hdr.msg_complete = 1;
+ }
+
+ mei_hdr.host_addr = dev->iamthif_cl.host_client_id;
+ mei_hdr.me_addr = dev->iamthif_cl.me_client_id;
+ mei_hdr.reserved = 0;
+ dev->iamthif_msg_buf_index += mei_hdr.length;
+ if (!mei_write_message(dev, &mei_hdr,
+ (unsigned char *)(dev->iamthif_msg_buf),
+ mei_hdr.length))
+ return -ENODEV;
+
+ if (mei_hdr.msg_complete) {
+ if (mei_flow_ctrl_reduce(dev, &dev->iamthif_cl))
+ return -ENODEV;
+ dev->iamthif_flow_control_pending = 1;
+ dev->iamthif_state = MEI_IAMTHIF_FLOW_CONTROL;
+ dev_dbg(&dev->pdev->dev, "add amthi cb to write waiting list\n");
+ dev->iamthif_current_cb = cb;
+ dev->iamthif_file_object = cb->file_object;
+ list_add_tail(&cb->cb_list,
+ &dev->write_waiting_list.mei_cb.cb_list);
+ } else {
+ dev_dbg(&dev->pdev->dev, "message does not complete, "
+ "so add amthi cb to write list.\n");
+ list_add_tail(&cb->cb_list,
+ &dev->write_list.mei_cb.cb_list);
+ }
+ } else {
+ if (!(dev->mei_host_buffer_is_empty))
+ dev_dbg(&dev->pdev->dev, "host buffer is not empty");
+
+ dev_dbg(&dev->pdev->dev, "No flow control credentials, "
+ "so add iamthif cb to write list.\n");
+ list_add_tail(&cb->cb_list,
+ &dev->write_list.mei_cb.cb_list);
+ }
+ return 0;
+}
+
+/**
+ * iamthif_ioctl_send_msg - send cmd data to amthi client
+ *
+ * @dev: the device structure
+ *
+ * returns 0 on success, <0 on failure.
+ */
+void run_next_iamthif_cmd(struct mei_device *dev)
+{
+ struct mei_cl *cl_tmp;
+ struct mei_cl_cb *cb_pos = NULL;
+ struct mei_cl_cb *cb_next = NULL;
+ int status;
+
+ if (!dev)
+ return;
+
+ dev->iamthif_msg_buf_size = 0;
+ dev->iamthif_msg_buf_index = 0;
+ dev->iamthif_canceled = 0;
+ dev->iamthif_ioctl = 1;
+ dev->iamthif_state = MEI_IAMTHIF_IDLE;
+ dev->iamthif_timer = 0;
+ dev->iamthif_file_object = NULL;
+
+ if (dev->amthi_cmd_list.status == 0 &&
+ !list_empty(&dev->amthi_cmd_list.mei_cb.cb_list)) {
+ dev_dbg(&dev->pdev->dev, "complete amthi cmd_list cb.\n");
+
+ list_for_each_entry_safe(cb_pos, cb_next,
+ &dev->amthi_cmd_list.mei_cb.cb_list, cb_list) {
+ list_del(&cb_pos->cb_list);
+ cl_tmp = (struct mei_cl *)cb_pos->file_private;
+
+ if (cl_tmp && cl_tmp == &dev->iamthif_cl) {
+ status = amthi_write(dev, cb_pos);
+ if (status) {
+ dev_dbg(&dev->pdev->dev,
+ "amthi write failed status = %d\n",
+ status);
+ return;
+ }
+ break;
+ }
+ }
+ }
+}
+
+/**
+ * mei_free_cb_private - free mei_cb_private related memory
+ *
+ * @cb: mei callback struct
+ */
+void mei_free_cb_private(struct mei_cl_cb *cb)
+{
+ if (cb == NULL)
+ return;
+
+ kfree(cb->request_buffer.data);
+ kfree(cb->response_buffer.data);
+ kfree(cb);
+}
diff --git a/drivers/staging/mei/main.c b/drivers/staging/mei/main.c
new file mode 100644
index 0000000..bfd1b46
--- /dev/null
+++ b/drivers/staging/mei/main.c
@@ -0,0 +1,1349 @@
+/*
+ *
+ * Intel Management Engine Interface (Intel MEI) Linux driver
+ * Copyright (c) 2003-2011, Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+
+
+
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/kernel.h>
+#include <linux/device.h>
+#include <linux/fs.h>
+#include <linux/errno.h>
+#include <linux/types.h>
+#include <linux/fcntl.h>
+#include <linux/aio.h>
+#include <linux/pci.h>
+#include <linux/poll.h>
+#include <linux/init.h>
+#include <linux/ioctl.h>
+#include <linux/cdev.h>
+#include <linux/version.h>
+#include <linux/sched.h>
+#include <linux/uuid.h>
+#include <linux/compat.h>
+#include <linux/jiffies.h>
+#include <linux/interrupt.h>
+
+#include "mei_dev.h"
+#include "mei.h"
+#include "interface.h"
+#include "mei_version.h"
+
+
+#define MEI_READ_TIMEOUT 45
+#define MEI_DRIVER_NAME "mei"
+#define MEI_DEV_NAME "mei"
+
+/*
+ * mei driver strings
+ */
+static char mei_driver_name[] = MEI_DRIVER_NAME;
+static const char mei_driver_string[] = "Intel(R) Management Engine Interface";
+static const char mei_driver_version[] = MEI_DRIVER_VERSION;
+
+/* mei char device for registration */
+static struct cdev mei_cdev;
+
+/* major number for device */
+static int mei_major;
+/* The device pointer */
+/* Currently this driver works as long as there is only a single AMT device. */
+static struct pci_dev *mei_device;
+
+static struct class *mei_class;
+
+
+/* mei_pci_tbl - PCI Device ID Table */
+static DEFINE_PCI_DEVICE_TABLE(mei_pci_tbl) = {
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_82946GZ)},
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_82G35)},
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_82Q965)},
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_82G965)},
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_82GM965)},
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_82GME965)},
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_82Q35)},
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_82G33)},
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_82Q33)},
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_82X38)},
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_3200)},
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_6)},
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_7)},
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_8)},
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_9)},
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9_10)},
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9M_1)},
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9M_2)},
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9M_3)},
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH9M_4)},
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH10_1)},
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH10_2)},
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH10_3)},
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_ICH10_4)},
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_IBXPK_1)},
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_IBXPK_2)},
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_CPT_1)},
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_PBG_1)},
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_PPT_1)},
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_PPT_2)},
+ {PCI_DEVICE(PCI_VENDOR_ID_INTEL, MEI_DEV_ID_PPT_3)},
+
+ /* required last entry */
+ {0, }
+};
+
+MODULE_DEVICE_TABLE(pci, mei_pci_tbl);
+
+static DEFINE_MUTEX(mei_mutex);
+
+/**
+ * mei_probe - Device Initialization Routine
+ *
+ * @pdev: PCI device structure
+ * @ent: entry in kcs_pci_tbl
+ *
+ * returns 0 on success, <0 on failure.
+ */
+static int __devinit mei_probe(struct pci_dev *pdev,
+ const struct pci_device_id *ent)
+{
+ struct mei_device *dev;
+ int err;
+
+ mutex_lock(&mei_mutex);
+ if (mei_device) {
+ err = -EEXIST;
+ goto end;
+ }
+ /* enable pci dev */
+ err = pci_enable_device(pdev);
+ if (err) {
+ printk(KERN_ERR "mei: Failed to enable pci device.\n");
+ goto end;
+ }
+ /* set PCI host mastering */
+ pci_set_master(pdev);
+ /* pci request regions for mei driver */
+ err = pci_request_regions(pdev, mei_driver_name);
+ if (err) {
+ printk(KERN_ERR "mei: Failed to get pci regions.\n");
+ goto disable_device;
+ }
+ /* allocates and initializes the mei dev structure */
+ dev = init_mei_device(pdev);
+ if (!dev) {
+ err = -ENOMEM;
+ goto release_regions;
+ }
+ /* mapping IO device memory */
+ dev->mem_addr = pci_iomap(pdev, 0, 0);
+ if (!dev->mem_addr) {
+ printk(KERN_ERR "mei: mapping I/O device memory failure.\n");
+ err = -ENOMEM;
+ goto free_device;
+ }
+ /* request and enable interrupt */
+ err = request_threaded_irq(pdev->irq,
+ mei_interrupt_quick_handler,
+ mei_interrupt_thread_handler,
+ IRQF_SHARED, mei_driver_name, dev);
+ if (err) {
+ printk(KERN_ERR "mei: request_threaded_irq failure. irq = %d\n",
+ pdev->irq);
+ goto unmap_memory;
+ }
+ INIT_DELAYED_WORK(&dev->wd_work, mei_wd_timer);
+ if (mei_hw_init(dev)) {
+ printk(KERN_ERR "mei: Init hw failure.\n");
+ err = -ENODEV;
+ goto release_irq;
+ }
+ mei_device = pdev;
+ pci_set_drvdata(pdev, dev);
+ schedule_delayed_work(&dev->wd_work, HZ);
+
+ mutex_unlock(&mei_mutex);
+
+ pr_debug("mei: Driver initialization successful.\n");
+
+ return 0;
+
+release_irq:
+ /* disable interrupts */
+ dev->host_hw_state = mei_hcsr_read(dev);
+ mei_disable_interrupts(dev);
+ flush_scheduled_work();
+ free_irq(pdev->irq, dev);
+unmap_memory:
+ pci_iounmap(pdev, dev->mem_addr);
+free_device:
+ kfree(dev);
+release_regions:
+ pci_release_regions(pdev);
+disable_device:
+ pci_disable_device(pdev);
+end:
+ mutex_unlock(&mei_mutex);
+ printk(KERN_ERR "mei: Driver initialization failed.\n");
+ return err;
+}
+
+/**
+ * mei_remove - Device Removal Routine
+ *
+ * @pdev: PCI device structure
+ *
+ * mei_remove is called by the PCI subsystem to alert the driver
+ * that it should release a PCI device.
+ */
+static void __devexit mei_remove(struct pci_dev *pdev)
+{
+ struct mei_device *dev;
+
+ if (mei_device != pdev)
+ return;
+
+ dev = pci_get_drvdata(pdev);
+ if (!dev)
+ return;
+
+ mutex_lock(&dev->device_lock);
+
+ mei_wd_stop(dev, false);
+
+ mei_device = NULL;
+
+ if (dev->iamthif_cl.state == MEI_FILE_CONNECTED) {
+ dev->iamthif_cl.state = MEI_FILE_DISCONNECTING;
+ mei_disconnect_host_client(dev, &dev->iamthif_cl);
+ }
+ if (dev->wd_cl.state == MEI_FILE_CONNECTED) {
+ dev->wd_cl.state = MEI_FILE_DISCONNECTING;
+ mei_disconnect_host_client(dev, &dev->wd_cl);
+ }
+
+ /* remove entry if already in list */
+ dev_dbg(&pdev->dev, "list del iamthif and wd file list.\n");
+ mei_remove_client_from_file_list(dev, dev->wd_cl.host_client_id);
+ mei_remove_client_from_file_list(dev, dev->iamthif_cl.host_client_id);
+
+ dev->iamthif_current_cb = NULL;
+ dev->num_mei_me_clients = 0;
+
+ mutex_unlock(&dev->device_lock);
+
+ flush_scheduled_work();
+
+ /* disable interrupts */
+ mei_disable_interrupts(dev);
+
+ free_irq(pdev->irq, dev);
+ pci_set_drvdata(pdev, NULL);
+
+ if (dev->mem_addr)
+ pci_iounmap(pdev, dev->mem_addr);
+
+ kfree(dev);
+
+ pci_release_regions(pdev);
+ pci_disable_device(pdev);
+}
+
+/**
+ * mei_clear_list - removes all callbacks associated with file
+ * from mei_cb_list
+ *
+ * @dev: device structure.
+ * @file: file structure
+ * @mei_cb_list: callbacks list
+ *
+ * mei_clear_list is called to clear resources associated with file
+ * when application calls close function or Ctrl-C was pressed
+ *
+ * returns true if callback removed from the list, false otherwise
+ */
+static bool mei_clear_list(struct mei_device *dev,
+ struct file *file, struct list_head *mei_cb_list)
+{
+ struct mei_cl_cb *cb_pos = NULL;
+ struct mei_cl_cb *cb_next = NULL;
+ struct file *file_temp;
+ bool removed = false;
+
+ /* list all list member */
+ list_for_each_entry_safe(cb_pos, cb_next, mei_cb_list, cb_list) {
+ file_temp = (struct file *)cb_pos->file_object;
+ /* check if list member associated with a file */
+ if (file_temp == file) {
+ /* remove member from the list */
+ list_del(&cb_pos->cb_list);
+ /* check if cb equal to current iamthif cb */
+ if (dev->iamthif_current_cb == cb_pos) {
+ dev->iamthif_current_cb = NULL;
+ /* send flow control to iamthif client */
+ mei_send_flow_control(dev, &dev->iamthif_cl);
+ }
+ /* free all allocated buffers */
+ mei_free_cb_private(cb_pos);
+ cb_pos = NULL;
+ removed = true;
+ }
+ }
+ return removed;
+}
+
+/**
+ * mei_clear_lists - removes all callbacks associated with file
+ *
+ * @dev: device structure
+ * @file: file structure
+ *
+ * mei_clear_lists is called to clear resources associated with file
+ * when application calls close function or Ctrl-C was pressed
+ *
+ * returns true if callback removed from the list, false otherwise
+ */
+static bool mei_clear_lists(struct mei_device *dev, struct file *file)
+{
+ bool removed = false;
+
+ /* remove callbacks associated with a file */
+ mei_clear_list(dev, file, &dev->amthi_cmd_list.mei_cb.cb_list);
+ if (mei_clear_list(dev, file,
+ &dev->amthi_read_complete_list.mei_cb.cb_list))
+ removed = true;
+
+ mei_clear_list(dev, file, &dev->ctrl_rd_list.mei_cb.cb_list);
+
+ if (mei_clear_list(dev, file, &dev->ctrl_wr_list.mei_cb.cb_list))
+ removed = true;
+
+ if (mei_clear_list(dev, file, &dev->write_waiting_list.mei_cb.cb_list))
+ removed = true;
+
+ if (mei_clear_list(dev, file, &dev->write_list.mei_cb.cb_list))
+ removed = true;
+
+ /* check if iamthif_current_cb not NULL */
+ if (dev->iamthif_current_cb && !removed) {
+ /* check file and iamthif current cb association */
+ if (dev->iamthif_current_cb->file_object == file) {
+ /* remove cb */
+ mei_free_cb_private(dev->iamthif_current_cb);
+ dev->iamthif_current_cb = NULL;
+ removed = true;
+ }
+ }
+ return removed;
+}
+/**
+ * find_read_list_entry - find read list entry
+ *
+ * @dev: device structure
+ * @file: pointer to file structure
+ *
+ * returns cb on success, NULL on error
+ */
+static struct mei_cl_cb *find_read_list_entry(
+ struct mei_device *dev,
+ struct mei_cl *cl)
+{
+ struct mei_cl_cb *cb_pos = NULL;
+ struct mei_cl_cb *cb_next = NULL;
+ struct mei_cl *cl_list_temp;
+
+ if (!dev->read_list.status &&
+ !list_empty(&dev->read_list.mei_cb.cb_list)) {
+
+ dev_dbg(&dev->pdev->dev, "remove read_list CB\n");
+ list_for_each_entry_safe(cb_pos, cb_next,
+ &dev->read_list.mei_cb.cb_list, cb_list) {
+
+ cl_list_temp = (struct mei_cl *)
+ cb_pos->file_private;
+
+ if (cl_list_temp &&
+ mei_fe_same_id(cl, cl_list_temp))
+ return cb_pos;
+
+ }
+ }
+ return NULL;
+}
+
+/**
+ * mei_open - the open function
+ *
+ * @inode: pointer to inode structure
+ * @file: pointer to file structure
+ *
+ * returns 0 on success, <0 on error
+ */
+static int mei_open(struct inode *inode, struct file *file)
+{
+ struct mei_cl *cl;
+ int if_num = iminor(inode), err;
+ struct mei_device *dev;
+
+ err = -ENODEV;
+ if (!mei_device)
+ goto out;
+
+ dev = pci_get_drvdata(mei_device);
+ if (if_num != MEI_MINOR_NUMBER || !dev)
+ goto out;
+
+ mutex_lock(&dev->device_lock);
+ err = -ENOMEM;
+ cl = mei_alloc_file_private(dev);
+ if (!cl)
+ goto out;
+
+ err = -ENODEV;
+ if (dev->mei_state != MEI_ENABLED) {
+ dev_dbg(&dev->pdev->dev, "mei_state != MEI_ENABLED mei_state= %d\n",
+ dev->mei_state);
+ goto out_unlock;
+ }
+ err = -EMFILE;
+ if (dev->open_handle_count >= MEI_MAX_OPEN_HANDLE_COUNT)
+ goto out_unlock;
+
+ cl->host_client_id = find_first_zero_bit(dev->host_clients_map,
+ MEI_CLIENTS_MAX);
+ if (cl->host_client_id > MEI_CLIENTS_MAX)
+ goto out_unlock;
+
+ dev_dbg(&dev->pdev->dev, "client_id = %d\n", cl->host_client_id);
+
+ dev->open_handle_count++;
+ list_add_tail(&cl->link, &dev->file_list);
+
+ set_bit(cl->host_client_id, dev->host_clients_map);
+ cl->state = MEI_FILE_INITIALIZING;
+ cl->sm_state = 0;
+
+ file->private_data = cl;
+ mutex_unlock(&dev->device_lock);
+
+ return 0;
+
+out_unlock:
+ mutex_unlock(&dev->device_lock);
+ kfree(cl);
+out:
+ return err;
+}
+
+/**
+ * mei_release - the release function
+ *
+ * @inode: pointer to inode structure
+ * @file: pointer to file structure
+ *
+ * returns 0 on success, <0 on error
+ */
+static int mei_release(struct inode *inode, struct file *file)
+{
+ struct mei_cl *cl = file->private_data;
+ struct mei_cl_cb *cb;
+ struct mei_device *dev;
+ int rets = 0;
+
+ if (WARN_ON(!cl || !cl->dev))
+ return -ENODEV;
+
+ dev = cl->dev;
+
+ mutex_lock(&dev->device_lock);
+ if (cl != &dev->iamthif_cl) {
+ if (cl->state == MEI_FILE_CONNECTED) {
+ cl->state = MEI_FILE_DISCONNECTING;
+ dev_dbg(&dev->pdev->dev,
+ "disconnecting client host client = %d, "
+ "ME client = %d\n",
+ cl->host_client_id,
+ cl->me_client_id);
+ rets = mei_disconnect_host_client(dev, cl);
+ }
+ mei_flush_queues(dev, cl);
+ dev_dbg(&dev->pdev->dev, "remove client host client = %d, ME client = %d\n",
+ cl->host_client_id,
+ cl->me_client_id);
+
+ if (dev->open_handle_count > 0) {
+ clear_bit(cl->host_client_id,
+ dev->host_clients_map);
+ dev->open_handle_count--;
+ }
+ mei_remove_client_from_file_list(dev, cl->host_client_id);
+
+ /* free read cb */
+ cb = NULL;
+ if (cl->read_cb) {
+ cb = find_read_list_entry(dev, cl);
+ /* Remove entry from read list */
+ if (cb)
+ list_del(&cb->cb_list);
+
+ cb = cl->read_cb;
+ cl->read_cb = NULL;
+ }
+
+ file->private_data = NULL;
+
+ if (cb) {
+ mei_free_cb_private(cb);
+ cb = NULL;
+ }
+
+ kfree(cl);
+ } else {
+ if (dev->open_handle_count > 0)
+ dev->open_handle_count--;
+
+ if (dev->iamthif_file_object == file &&
+ dev->iamthif_state != MEI_IAMTHIF_IDLE) {
+
+ dev_dbg(&dev->pdev->dev, "amthi canceled iamthif state %d\n",
+ dev->iamthif_state);
+ dev->iamthif_canceled = 1;
+ if (dev->iamthif_state == MEI_IAMTHIF_READ_COMPLETE) {
+ dev_dbg(&dev->pdev->dev, "run next amthi iamthif cb\n");
+ run_next_iamthif_cmd(dev);
+ }
+ }
+
+ if (mei_clear_lists(dev, file))
+ dev->iamthif_state = MEI_IAMTHIF_IDLE;
+
+ }
+ mutex_unlock(&dev->device_lock);
+ return rets;
+}
+
+
+/**
+ * mei_read - the read function.
+ *
+ * @file: pointer to file structure
+ * @ubuf: pointer to user buffer
+ * @length: buffer length
+ * @offset: data offset in buffer
+ *
+ * returns >=0 data length on success , <0 on error
+ */
+static ssize_t mei_read(struct file *file, char __user *ubuf,
+ size_t length, loff_t *offset)
+{
+ struct mei_cl *cl = file->private_data;
+ struct mei_cl_cb *cb_pos = NULL;
+ struct mei_cl_cb *cb = NULL;
+ struct mei_device *dev;
+ int i;
+ int rets;
+ int err;
+
+
+ if (WARN_ON(!cl || !cl->dev))
+ return -ENODEV;
+
+ dev = cl->dev;
+
+ mutex_lock(&dev->device_lock);
+ if (dev->mei_state != MEI_ENABLED) {
+ rets = -ENODEV;
+ goto out;
+ }
+
+ if ((cl->sm_state & MEI_WD_STATE_INDEPENDENCE_MSG_SENT) == 0) {
+ /* Do not allow to read watchdog client */
+ i = mei_find_me_client_index(dev, mei_wd_guid);
+ if (i >= 0) {
+ struct mei_me_client *me_client = &dev->me_clients[i];
+
+ if (cl->me_client_id == me_client->client_id) {
+ rets = -EBADF;
+ goto out;
+ }
+ }
+ } else {
+ cl->sm_state &= ~MEI_WD_STATE_INDEPENDENCE_MSG_SENT;
+ }
+
+ if (cl == &dev->iamthif_cl) {
+ rets = amthi_read(dev, file, ubuf, length, offset);
+ goto out;
+ }
+
+ if (cl->read_cb && cl->read_cb->information > *offset) {
+ cb = cl->read_cb;
+ goto copy_buffer;
+ } else if (cl->read_cb && cl->read_cb->information > 0 &&
+ cl->read_cb->information <= *offset) {
+ cb = cl->read_cb;
+ rets = 0;
+ goto free;
+ } else if ((!cl->read_cb || !cl->read_cb->information) &&
+ *offset > 0) {
+ /*Offset needs to be cleaned for contingous reads*/
+ *offset = 0;
+ rets = 0;
+ goto out;
+ }
+
+ err = mei_start_read(dev, cl);
+ if (err && err != -EBUSY) {
+ dev_dbg(&dev->pdev->dev,
+ "mei start read failure with status = %d\n", err);
+ rets = err;
+ goto out;
+ }
+
+ if (MEI_READ_COMPLETE != cl->reading_state &&
+ !waitqueue_active(&cl->rx_wait)) {
+ if (file->f_flags & O_NONBLOCK) {
+ rets = -EAGAIN;
+ goto out;
+ }
+
+ mutex_unlock(&dev->device_lock);
+
+ if (wait_event_interruptible(cl->rx_wait,
+ (MEI_READ_COMPLETE == cl->reading_state ||
+ MEI_FILE_INITIALIZING == cl->state ||
+ MEI_FILE_DISCONNECTED == cl->state ||
+ MEI_FILE_DISCONNECTING == cl->state))) {
+ if (signal_pending(current))
+ return -EINTR;
+ return -ERESTARTSYS;
+ }
+
+ mutex_lock(&dev->device_lock);
+ if (MEI_FILE_INITIALIZING == cl->state ||
+ MEI_FILE_DISCONNECTED == cl->state ||
+ MEI_FILE_DISCONNECTING == cl->state) {
+ rets = -EBUSY;
+ goto out;
+ }
+ }
+
+ cb = cl->read_cb;
+
+ if (!cb) {
+ rets = -ENODEV;
+ goto out;
+ }
+ if (cl->reading_state != MEI_READ_COMPLETE) {
+ rets = 0;
+ goto out;
+ }
+ /* now copy the data to user space */
+copy_buffer:
+ dev_dbg(&dev->pdev->dev, "cb->response_buffer size - %d\n",
+ cb->response_buffer.size);
+ dev_dbg(&dev->pdev->dev, "cb->information - %lu\n",
+ cb->information);
+ if (length == 0 || ubuf == NULL || *offset > cb->information) {
+ rets = -EMSGSIZE;
+ goto free;
+ }
+
+ /* length is being turncated to PAGE_SIZE, however, */
+ /* information size may be longer */
+ length = min_t(size_t, length, (cb->information - *offset));
+
+ if (copy_to_user(ubuf,
+ cb->response_buffer.data + *offset,
+ length)) {
+ rets = -EFAULT;
+ goto free;
+ }
+
+ rets = length;
+ *offset += length;
+ if ((unsigned long)*offset < cb->information)
+ goto out;
+
+free:
+ cb_pos = find_read_list_entry(dev, cl);
+ /* Remove entry from read list */
+ if (cb_pos)
+ list_del(&cb_pos->cb_list);
+ mei_free_cb_private(cb);
+ cl->reading_state = MEI_IDLE;
+ cl->read_cb = NULL;
+ cl->read_pending = 0;
+out:
+ dev_dbg(&dev->pdev->dev, "end mei read rets= %d\n", rets);
+ mutex_unlock(&dev->device_lock);
+ return rets;
+}
+
+/**
+ * mei_write - the write function.
+ *
+ * @file: pointer to file structure
+ * @ubuf: pointer to user buffer
+ * @length: buffer length
+ * @offset: data offset in buffer
+ *
+ * returns >=0 data length on success , <0 on error
+ */
+static ssize_t mei_write(struct file *file, const char __user *ubuf,
+ size_t length, loff_t *offset)
+{
+ struct mei_cl *cl = file->private_data;
+ struct mei_cl_cb *write_cb = NULL;
+ struct mei_msg_hdr mei_hdr;
+ struct mei_device *dev;
+ unsigned long timeout = 0;
+ int rets;
+ int i;
+
+ if (WARN_ON(!cl || !cl->dev))
+ return -ENODEV;
+
+ dev = cl->dev;
+
+ mutex_lock(&dev->device_lock);
+
+ if (dev->mei_state != MEI_ENABLED) {
+ mutex_unlock(&dev->device_lock);
+ return -ENODEV;
+ }
+
+ if (cl == &dev->iamthif_cl) {
+ write_cb = find_amthi_read_list_entry(dev, file);
+
+ if (write_cb) {
+ timeout = write_cb->read_time +
+ msecs_to_jiffies(IAMTHIF_READ_TIMER);
+
+ if (time_after(jiffies, timeout) ||
+ cl->reading_state == MEI_READ_COMPLETE) {
+ *offset = 0;
+ list_del(&write_cb->cb_list);
+ mei_free_cb_private(write_cb);
+ write_cb = NULL;
+ }
+ }
+ }
+
+ /* free entry used in read */
+ if (cl->reading_state == MEI_READ_COMPLETE) {
+ *offset = 0;
+ write_cb = find_read_list_entry(dev, cl);
+ if (write_cb) {
+ list_del(&write_cb->cb_list);
+ mei_free_cb_private(write_cb);
+ write_cb = NULL;
+ cl->reading_state = MEI_IDLE;
+ cl->read_cb = NULL;
+ cl->read_pending = 0;
+ }
+ } else if (cl->reading_state == MEI_IDLE &&
+ !cl->read_pending)
+ *offset = 0;
+
+
+ write_cb = kzalloc(sizeof(struct mei_cl_cb), GFP_KERNEL);
+ if (!write_cb) {
+ mutex_unlock(&dev->device_lock);
+ return -ENOMEM;
+ }
+
+ write_cb->file_object = file;
+ write_cb->file_private = cl;
+ write_cb->request_buffer.data = kmalloc(length, GFP_KERNEL);
+ rets = -ENOMEM;
+ if (!write_cb->request_buffer.data)
+ goto unlock_dev;
+
+ dev_dbg(&dev->pdev->dev, "length =%d\n", (int) length);
+
+ rets = -EFAULT;
+ if (copy_from_user(write_cb->request_buffer.data, ubuf, length))
+ goto unlock_dev;
+
+ cl->sm_state = 0;
+ if (length == 4 &&
+ ((memcmp(mei_wd_state_independence_msg[0],
+ write_cb->request_buffer.data, 4) == 0) ||
+ (memcmp(mei_wd_state_independence_msg[1],
+ write_cb->request_buffer.data, 4) == 0) ||
+ (memcmp(mei_wd_state_independence_msg[2],
+ write_cb->request_buffer.data, 4) == 0)))
+ cl->sm_state |= MEI_WD_STATE_INDEPENDENCE_MSG_SENT;
+
+ INIT_LIST_HEAD(&write_cb->cb_list);
+ if (cl == &dev->iamthif_cl) {
+ write_cb->response_buffer.data =
+ kmalloc(dev->iamthif_mtu, GFP_KERNEL);
+ if (!write_cb->response_buffer.data) {
+ rets = -ENOMEM;
+ goto unlock_dev;
+ }
+ if (dev->mei_state != MEI_ENABLED) {
+ rets = -ENODEV;
+ goto unlock_dev;
+ }
+ for (i = 0; i < dev->num_mei_me_clients; i++) {
+ if (dev->me_clients[i].client_id ==
+ dev->iamthif_cl.me_client_id)
+ break;
+ }
+
+ if (WARN_ON(dev->me_clients[i].client_id != cl->me_client_id)) {
+ rets = -ENODEV;
+ goto unlock_dev;
+ }
+ if (i == dev->num_mei_me_clients ||
+ (dev->me_clients[i].client_id !=
+ dev->iamthif_cl.me_client_id)) {
+ rets = -ENODEV;
+ goto unlock_dev;
+ } else if (length > dev->me_clients[i].props.max_msg_length ||
+ length <= 0) {
+ rets = -EMSGSIZE;
+ goto unlock_dev;
+ }
+
+ write_cb->response_buffer.size = dev->iamthif_mtu;
+ write_cb->major_file_operations = MEI_IOCTL;
+ write_cb->information = 0;
+ write_cb->request_buffer.size = length;
+ if (dev->iamthif_cl.state != MEI_FILE_CONNECTED) {
+ rets = -ENODEV;
+ goto unlock_dev;
+ }
+
+ if (!list_empty(&dev->amthi_cmd_list.mei_cb.cb_list) ||
+ dev->iamthif_state != MEI_IAMTHIF_IDLE) {
+ dev_dbg(&dev->pdev->dev, "amthi_state = %d\n",
+ (int) dev->iamthif_state);
+ dev_dbg(&dev->pdev->dev, "add amthi cb to amthi cmd waiting list\n");
+ list_add_tail(&write_cb->cb_list,
+ &dev->amthi_cmd_list.mei_cb.cb_list);
+ rets = length;
+ } else {
+ dev_dbg(&dev->pdev->dev, "call amthi write\n");
+ rets = amthi_write(dev, write_cb);
+
+ if (rets) {
+ dev_dbg(&dev->pdev->dev, "amthi write failed with status = %d\n",
+ rets);
+ goto unlock_dev;
+ }
+ rets = length;
+ }
+ mutex_unlock(&dev->device_lock);
+ return rets;
+ }
+
+ write_cb->major_file_operations = MEI_WRITE;
+ /* make sure information is zero before we start */
+
+ write_cb->information = 0;
+ write_cb->request_buffer.size = length;
+
+ dev_dbg(&dev->pdev->dev, "host client = %d, ME client = %d\n",
+ cl->host_client_id, cl->me_client_id);
+ if (cl->state != MEI_FILE_CONNECTED) {
+ rets = -ENODEV;
+ dev_dbg(&dev->pdev->dev, "host client = %d, is not connected to ME client = %d",
+ cl->host_client_id,
+ cl->me_client_id);
+ goto unlock_dev;
+ }
+ for (i = 0; i < dev->num_mei_me_clients; i++) {
+ if (dev->me_clients[i].client_id ==
+ cl->me_client_id)
+ break;
+ }
+ if (WARN_ON(dev->me_clients[i].client_id != cl->me_client_id)) {
+ rets = -ENODEV;
+ goto unlock_dev;
+ }
+ if (i == dev->num_mei_me_clients) {
+ rets = -ENODEV;
+ goto unlock_dev;
+ }
+ if (length > dev->me_clients[i].props.max_msg_length || length <= 0) {
+ rets = -EINVAL;
+ goto unlock_dev;
+ }
+ write_cb->file_private = cl;
+
+ rets = mei_flow_ctrl_creds(dev, cl);
+ if (rets < 0)
+ goto unlock_dev;
+
+ if (rets && dev->mei_host_buffer_is_empty) {
+ rets = 0;
+ dev->mei_host_buffer_is_empty = 0;
+ if (length > ((((dev->host_hw_state & H_CBD) >> 24) *
+ sizeof(u32)) - sizeof(struct mei_msg_hdr))) {
+
+ mei_hdr.length =
+ (((dev->host_hw_state & H_CBD) >> 24) *
+ sizeof(u32)) -
+ sizeof(struct mei_msg_hdr);
+ mei_hdr.msg_complete = 0;
+ } else {
+ mei_hdr.length = length;
+ mei_hdr.msg_complete = 1;
+ }
+ mei_hdr.host_addr = cl->host_client_id;
+ mei_hdr.me_addr = cl->me_client_id;
+ mei_hdr.reserved = 0;
+ dev_dbg(&dev->pdev->dev, "call mei_write_message header=%08x.\n",
+ *((u32 *) &mei_hdr));
+ if (!mei_write_message(dev, &mei_hdr,
+ (unsigned char *) (write_cb->request_buffer.data),
+ mei_hdr.length)) {
+ rets = -ENODEV;
+ goto unlock_dev;
+ }
+ cl->writing_state = MEI_WRITING;
+ write_cb->information = mei_hdr.length;
+ if (mei_hdr.msg_complete) {
+ if (mei_flow_ctrl_reduce(dev, cl)) {
+ rets = -ENODEV;
+ goto unlock_dev;
+ }
+ list_add_tail(&write_cb->cb_list,
+ &dev->write_waiting_list.mei_cb.cb_list);
+ } else {
+ list_add_tail(&write_cb->cb_list,
+ &dev->write_list.mei_cb.cb_list);
+ }
+
+ } else {
+
+ write_cb->information = 0;
+ cl->writing_state = MEI_WRITING;
+ list_add_tail(&write_cb->cb_list,
+ &dev->write_list.mei_cb.cb_list);
+ }
+ mutex_unlock(&dev->device_lock);
+ return length;
+
+unlock_dev:
+ mutex_unlock(&dev->device_lock);
+ mei_free_cb_private(write_cb);
+ return rets;
+}
+
+
+/**
+ * mei_ioctl - the IOCTL function
+ *
+ * @file: pointer to file structure
+ * @cmd: ioctl command
+ * @data: pointer to mei message structure
+ *
+ * returns 0 on success , <0 on error
+ */
+static long mei_ioctl(struct file *file, unsigned int cmd, unsigned long data)
+{
+ struct mei_device *dev;
+ struct mei_cl *cl = file->private_data;
+ struct mei_connect_client_data *connect_data = NULL;
+ int rets;
+
+ if (cmd != IOCTL_MEI_CONNECT_CLIENT)
+ return -EINVAL;
+
+ if (WARN_ON(!cl || !cl->dev))
+ return -ENODEV;
+
+ dev = cl->dev;
+
+ dev_dbg(&dev->pdev->dev, "IOCTL cmd = 0x%x", cmd);
+
+ mutex_lock(&dev->device_lock);
+ if (dev->mei_state != MEI_ENABLED) {
+ rets = -ENODEV;
+ goto out;
+ }
+
+ dev_dbg(&dev->pdev->dev, ": IOCTL_MEI_CONNECT_CLIENT.\n");
+
+ connect_data = kzalloc(sizeof(struct mei_connect_client_data),
+ GFP_KERNEL);
+ if (!connect_data) {
+ rets = -ENOMEM;
+ goto out;
+ }
+ dev_dbg(&dev->pdev->dev, "copy connect data from user\n");
+ if (copy_from_user(connect_data, (char __user *)data,
+ sizeof(struct mei_connect_client_data))) {
+ dev_dbg(&dev->pdev->dev, "failed to copy data from userland\n");
+ rets = -EFAULT;
+ goto out;
+ }
+ rets = mei_ioctl_connect_client(file, connect_data);
+
+ /* if all is ok, copying the data back to user. */
+ if (rets)
+ goto out;
+
+ dev_dbg(&dev->pdev->dev, "copy connect data to user\n");
+ if (copy_to_user((char __user *)data, connect_data,
+ sizeof(struct mei_connect_client_data))) {
+ dev_dbg(&dev->pdev->dev, "failed to copy data to userland\n");
+ rets = -EFAULT;
+ goto out;
+ }
+
+out:
+ kfree(connect_data);
+ mutex_unlock(&dev->device_lock);
+ return rets;
+}
+
+/**
+ * mei_compat_ioctl - the compat IOCTL function
+ *
+ * @file: pointer to file structure
+ * @cmd: ioctl command
+ * @data: pointer to mei message structure
+ *
+ * returns 0 on success , <0 on error
+ */
+#ifdef CONFIG_COMPAT
+static long mei_compat_ioctl(struct file *file,
+ unsigned int cmd, unsigned long data)
+{
+ return mei_ioctl(file, cmd, (unsigned long)compat_ptr(data));
+}
+#endif
+
+
+/**
+ * mei_poll - the poll function
+ *
+ * @file: pointer to file structure
+ * @wait: pointer to poll_table structure
+ *
+ * returns poll mask
+ */
+static unsigned int mei_poll(struct file *file, poll_table *wait)
+{
+ struct mei_cl *cl = file->private_data;
+ struct mei_device *dev;
+ unsigned int mask = 0;
+
+ if (WARN_ON(!cl || !cl->dev))
+ return mask;
+
+ dev = cl->dev;
+
+ mutex_lock(&dev->device_lock);
+
+ if (dev->mei_state != MEI_ENABLED)
+ goto out;
+
+
+ if (cl == &dev->iamthif_cl) {
+ mutex_unlock(&dev->device_lock);
+ poll_wait(file, &dev->iamthif_cl.wait, wait);
+ mutex_lock(&dev->device_lock);
+ if (dev->iamthif_state == MEI_IAMTHIF_READ_COMPLETE &&
+ dev->iamthif_file_object == file) {
+ mask |= (POLLIN | POLLRDNORM);
+ dev_dbg(&dev->pdev->dev, "run next amthi cb\n");
+ run_next_iamthif_cmd(dev);
+ }
+ goto out;
+ }
+
+ mutex_unlock(&dev->device_lock);
+ poll_wait(file, &cl->tx_wait, wait);
+ mutex_lock(&dev->device_lock);
+ if (MEI_WRITE_COMPLETE == cl->writing_state)
+ mask |= (POLLIN | POLLRDNORM);
+
+out:
+ mutex_unlock(&dev->device_lock);
+ return mask;
+}
+
+#ifdef CONFIG_PM
+static int mei_pci_suspend(struct device *device)
+{
+ struct pci_dev *pdev = to_pci_dev(device);
+ struct mei_device *dev = pci_get_drvdata(pdev);
+ int err;
+
+ if (!dev)
+ return -ENODEV;
+ mutex_lock(&dev->device_lock);
+ /* Stop watchdog if exists */
+ err = mei_wd_stop(dev, true);
+ /* Set new mei state */
+ if (dev->mei_state == MEI_ENABLED ||
+ dev->mei_state == MEI_RECOVERING_FROM_RESET) {
+ dev->mei_state = MEI_POWER_DOWN;
+ mei_reset(dev, 0);
+ }
+ mutex_unlock(&dev->device_lock);
+
+ free_irq(pdev->irq, dev);
+
+
+ return err;
+}
+
+static int mei_pci_resume(struct device *device)
+{
+ struct pci_dev *pdev = to_pci_dev(device);
+ struct mei_device *dev;
+ int err;
+
+ dev = pci_get_drvdata(pdev);
+ if (!dev)
+ return -ENODEV;
+
+ /* request and enable interrupt */
+ err = request_threaded_irq(pdev->irq,
+ mei_interrupt_quick_handler,
+ mei_interrupt_thread_handler,
+ IRQF_SHARED, mei_driver_name, dev);
+ if (err) {
+ printk(KERN_ERR "mei: Request_irq failure. irq = %d\n",
+ pdev->irq);
+ return err;
+ }
+
+ mutex_lock(&dev->device_lock);
+ dev->mei_state = MEI_POWER_UP;
+ mei_reset(dev, 1);
+ mutex_unlock(&dev->device_lock);
+
+ /* Start watchdog if stopped in suspend */
+ if (dev->wd_timeout) {
+ mei_wd_start_setup(dev);
+ dev->wd_due_counter = 1;
+ schedule_delayed_work(&dev->wd_work, HZ);
+ }
+ return err;
+}
+static SIMPLE_DEV_PM_OPS(mei_pm_ops, mei_pci_suspend, mei_pci_resume);
+#define MEI_PM_OPS (&mei_pm_ops)
+#else
+#define MEI_PM_OPS NULL
+#endif /* CONFIG_PM */
+/*
+ * PCI driver structure
+ */
+static struct pci_driver mei_driver = {
+ .name = mei_driver_name,
+ .id_table = mei_pci_tbl,
+ .probe = mei_probe,
+ .remove = __devexit_p(mei_remove),
+ .shutdown = __devexit_p(mei_remove),
+ .driver.pm = MEI_PM_OPS,
+};
+
+/*
+ * file operations structure will be used for mei char device.
+ */
+static const struct file_operations mei_fops = {
+ .owner = THIS_MODULE,
+ .read = mei_read,
+ .unlocked_ioctl = mei_ioctl,
+#ifdef CONFIG_COMPAT
+ .compat_ioctl = mei_compat_ioctl,
+#endif
+ .open = mei_open,
+ .release = mei_release,
+ .write = mei_write,
+ .poll = mei_poll,
+};
+
+/**
+ * mei_registration_cdev - sets up the cdev structure for mei device.
+ *
+ * @dev: char device struct
+ * @hminor: minor number for registration char device
+ * @fops: file operations structure
+ *
+ * returns 0 on success, <0 on failure.
+ */
+static int mei_registration_cdev(struct cdev *dev, int hminor,
+ const struct file_operations *fops)
+{
+ int ret, devno = MKDEV(mei_major, hminor);
+
+ cdev_init(dev, fops);
+ dev->owner = THIS_MODULE;
+ ret = cdev_add(dev, devno, 1);
+ /* Fail gracefully if need be */
+ if (ret)
+ printk(KERN_ERR "mei: Error %d registering mei device %d\n",
+ ret, hminor);
+ return ret;
+}
+
+/**
+ * mei_register_cdev - registers mei char device
+ *
+ * returns 0 on success, <0 on failure.
+ */
+static int mei_register_cdev(void)
+{
+ int ret;
+ dev_t dev;
+
+ /* registration of char devices */
+ ret = alloc_chrdev_region(&dev, MEI_MINORS_BASE, MEI_MINORS_COUNT,
+ MEI_DRIVER_NAME);
+ if (ret) {
+ printk(KERN_ERR "mei: Error allocating char device region.\n");
+ return ret;
+ }
+
+ mei_major = MAJOR(dev);
+
+ ret = mei_registration_cdev(&mei_cdev, MEI_MINOR_NUMBER,
+ &mei_fops);
+ if (ret)
+ unregister_chrdev_region(MKDEV(mei_major, MEI_MINORS_BASE),
+ MEI_MINORS_COUNT);
+
+ return ret;
+}
+
+/**
+ * mei_unregister_cdev - unregisters mei char device
+ */
+static void mei_unregister_cdev(void)
+{
+ cdev_del(&mei_cdev);
+ unregister_chrdev_region(MKDEV(mei_major, MEI_MINORS_BASE),
+ MEI_MINORS_COUNT);
+}
+
+/**
+ * mei_sysfs_device_create - adds device entry to sysfs
+ *
+ * returns 0 on success, <0 on failure.
+ */
+static int mei_sysfs_device_create(void)
+{
+ struct class *class;
+ void *tmphdev;
+ int err;
+
+ class = class_create(THIS_MODULE, MEI_DRIVER_NAME);
+ if (IS_ERR(class)) {
+ err = PTR_ERR(class);
+ printk(KERN_ERR "mei: Error creating mei class.\n");
+ goto err_out;
+ }
+
+ tmphdev = device_create(class, NULL, mei_cdev.dev, NULL,
+ MEI_DEV_NAME);
+ if (IS_ERR(tmphdev)) {
+ err = PTR_ERR(tmphdev);
+ goto err_destroy;
+ }
+
+ mei_class = class;
+ return 0;
+
+err_destroy:
+ class_destroy(class);
+err_out:
+ return err;
+}
+
+/**
+ * mei_sysfs_device_remove - unregisters the device entry on sysfs
+ */
+static void mei_sysfs_device_remove(void)
+{
+ if (IS_ERR_OR_NULL(mei_class))
+ return;
+
+ device_destroy(mei_class, mei_cdev.dev);
+ class_destroy(mei_class);
+}
+
+/**
+ * mei_init_module - Driver Registration Routine
+ *
+ * mei_init_module is the first routine called when the driver is
+ * loaded. All it does is to register with the PCI subsystem.
+ *
+ * returns 0 on success, <0 on failure.
+ */
+static int __init mei_init_module(void)
+{
+ int ret;
+
+ pr_debug("mei: %s - version %s\n",
+ mei_driver_string, mei_driver_version);
+ /* init pci module */
+ ret = pci_register_driver(&mei_driver);
+ if (ret < 0) {
+ printk(KERN_ERR "mei: Error registering driver.\n");
+ goto end;
+ }
+
+ ret = mei_register_cdev();
+ if (ret)
+ goto unregister_pci;
+
+ ret = mei_sysfs_device_create();
+ if (ret)
+ goto unregister_cdev;
+
+ return ret;
+
+unregister_cdev:
+ mei_unregister_cdev();
+unregister_pci:
+ pci_unregister_driver(&mei_driver);
+end:
+ return ret;
+}
+
+module_init(mei_init_module);
+
+/**
+ * mei_exit_module - Driver Exit Cleanup Routine
+ *
+ * mei_exit_module is called just before the driver is removed
+ * from memory.
+ */
+static void __exit mei_exit_module(void)
+{
+ pci_unregister_driver(&mei_driver);
+ mei_sysfs_device_remove();
+ mei_unregister_cdev();
+
+ pr_debug("mei: Driver unloaded successfully.\n");
+}
+
+module_exit(mei_exit_module);
+
+
+MODULE_AUTHOR("Intel Corporation");
+MODULE_DESCRIPTION("Intel(R) Management Engine Interface");
+MODULE_LICENSE("GPL v2");
+MODULE_VERSION(MEI_DRIVER_VERSION);
diff --git a/drivers/staging/mei/mei.h b/drivers/staging/mei/mei.h
new file mode 100644
index 0000000..6da7c4f
--- /dev/null
+++ b/drivers/staging/mei/mei.h
@@ -0,0 +1,105 @@
+/*
+
+ Intel Management Engine Interface (Intel MEI) Linux driver
+ Intel MEI Interface Header
+
+ This file is provided under a dual BSD/GPLv2 license. When using or
+ redistributing this file, you may do so under either license.
+
+ GPL LICENSE SUMMARY
+
+ Copyright(c) 2003-2011 Intel Corporation. All rights reserved.
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of version 2 of the GNU General Public License as
+ published by the Free Software Foundation.
+
+ This program is distributed in the hope that it will be useful, but
+ WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ General Public License for more details.
+
+ Contact Information:
+ Intel Corporation.
+ linux-mei@linux.intel.com
+ http://www.intel.com
+
+
+ BSD LICENSE
+
+ Copyright(c) 2003-2011 Intel Corporation. All rights reserved.
+ All rights reserved.
+
+ Redistribution and use in source and binary forms, with or without
+ modification, are permitted provided that the following conditions
+ are met:
+
+ * Redistributions of source code must retain the above copyright
+ notice, this list of conditions and the following disclaimer.
+ * Redistributions in binary form must reproduce the above copyright
+ notice, this list of conditions and the following disclaimer in
+ the documentation and/or other materials provided with the
+ distribution.
+ * Neither the name of Intel Corporation nor the names of its
+ contributors may be used to endorse or promote products derived
+ from this software without specific prior written permission.
+
+ THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+*/
+
+
+#ifndef _LINUX_MEI_H
+#define _LINUX_MEI_H
+
+#include <linux/uuid.h>
+
+/*
+ * This IOCTL is used to associate the current file descriptor with a
+ * FW Client (given by UUID). This opens a communication channel
+ * between a host client and a FW client. From this point every read and write
+ * will communicate with the associated FW client.
+ * Only in close() (file_operation release()) the communication between
+ * the clients is disconnected
+ *
+ * The IOCTL argument is a struct with a union the contains
+ * the input parameter and the output parameter for this IOCTL.
+ *
+ * The input parameter is UUID of the FW Client.
+ * The output parameter is the properties of the FW client
+ * (FW protocol version and max message size).
+ *
+ */
+#define IOCTL_MEI_CONNECT_CLIENT \
+ _IOWR('H' , 0x01, struct mei_connect_client_data)
+
+/*
+ * Intel MEI client information struct
+ */
+struct mei_client {
+ __u32 max_msg_length;
+ __u8 protocol_version;
+ __u8 reserved[3];
+};
+
+/*
+ * IOCTL Connect Client Data structure
+ */
+struct mei_connect_client_data {
+ union {
+ uuid_le in_client_uuid;
+ struct mei_client out_client_properties;
+ };
+};
+
+#endif /* _LINUX_MEI_H */
diff --git a/drivers/staging/mei/mei.txt b/drivers/staging/mei/mei.txt
new file mode 100644
index 0000000..17302ad
--- /dev/null
+++ b/drivers/staging/mei/mei.txt
@@ -0,0 +1,189 @@
+Intel MEI
+=======================
+
+Introduction
+=======================
+
+The Intel Management Engine (Intel ME) is an isolated and
+protected computing resource (Coprocessor) residing inside
+Intel chipsets. The Intel ME provides support for computer/IT
+management features.
+The Feature set depends on the Intel chipset SKU.
+
+The Intel Management Engine Interface (Intel MEI, previously known
+as HECI) is the interface between the Host and Intel ME.
+This interface is exposed to the host as a PCI device.
+The Intel MEI Driver is in charge of the communication channel
+between a host application and the ME feature.
+
+Each Intel ME feature (Intel ME Client) is addressed by
+GUID/UUID and each feature defines its own protocol.
+The protocol is message-based with a header and payload up to
+512 bytes.
+
+[place holder to URL to protocol definitions]
+
+Prominent usage of the Interface is to communicate with
+Intel Active Management Technology (Intel AMT)
+implemented in firmware running on the Intel ME.
+
+Intel AMT provides the ability to manage a host remotely out-of-band (OOB)
+even when the host processor has crashed or is in a sleep state.
+
+Some examples of Intel AMT usage are:
+ - Monitoring hardware state and platform components
+ - Remote power off/on (useful for green computing or overnight IT maintenance)
+ - OS updates
+ - Storage of useful platform information such as software assets
+ - built-in hardware KVM
+ - selective network isolation of Ethernet and IP protocol flows based on
+ policies set by a remote management console
+ - IDE device redirection from remote management console
+
+Intel AMT (OOB) communication is based on SOAP (deprecated
+starting with Release 6.0) over HTTP/HTTPS or WS-Management protocol
+over HTTP and HTTPS that are received from a remote
+management console application.
+
+For more information about Intel AMT:
+http://software.intel.com/sites/manageability/AMT_Implementation_and_Reference_Guide/WordDocuments/aboutintelamt.htm
+
+
+MEI Driver
+=======================
+
+The driver exposes a character device called /dev/mei.
+
+An application maintains communication with an ME feature while
+/dev/mei is open. The binding to a specific features is performed
+by calling MEI_CONNECT_CLIENT_IOCTL, which passes the desired UUID.
+The number of instances of an ME feature that can be opened
+at the same time depends on the ME feature, but most of the
+features allow only a single instance.
+
+
+The Intel AMT Host Interface (AMTHI) feature requires multiple
+simultaneous user applications, therefore the MEI driver handles
+this internally by maintaining request queues for the applications.
+
+The driver is oblivious to data that are passed between
+
+Because some of the ME features can change the system
+configuration, the driver by default allows only privileged
+user to access it.
+
+A Code snippet for application communicating with AMTHI client:
+ struct mei_connect_client_data data;
+ fd = open(MEI_DEVICE);
+
+ data.d.in_client_uuid = AMTHI_UUID;
+
+ ioctl(fd, IOCTL_MEI_CONNECT_CLIENT, &data);
+
+ printf(“Ver=%d, MaxLen=%ld\n”,
+ data.d.in_client_uuid.protocol_version,
+ data.d.in_client_uuid.max_msg_length);
+
+ [...]
+
+ write(fd, amthi_req_data, amthi_req_data_len);
+
+ [...]
+
+ read(fd, &amthi_res_data, amthi_res_data_len);
+
+ [...]
+ close(fd);
+
+ME Applications:
+==============
+
+1) Intel Local Management Service (Intel LMS)
+ Applications running locally on the platform communicate with
+ Intel AMT Release 2.0 and later releases in the same way
+ that network applications do via SOAP over HTTP (deprecated
+ starting with Release 6.0) or with WS-Management over SOAP over
+ HTTP. which means that some Intel AMT feature can be access
+ from a local application using same Network interface as for
+ remote application.
+
+ When a local application sends a message addressed to the local
+ Intel AMT host name, the Local Manageability Service (LMS),
+ which listens for traffic directed to the host name, intercepts
+ the message and routes it to the Intel Management Engine Interface.
+ For more information:
+ http://software.intel.com/sites/manageability/AMT_Implementation_and_
+ Reference_Guide/WordDocuments/localaccess1.htm
+
+ The LMS opens a connection using the MEI driver to the LMS
+ FW feature using a defined UUID and then communicates with the
+ feature using a protocol
+ called Intel(R) AMT Port Forwarding Protocol (APF protocol).
+ The protocol is used to maintain multiple sessions with
+ Intel AMT from a single application.
+ See the protocol specification in
+ the Intel(R) AMT Implementation and Reference Guide
+ http://software.intel.com/sites/manageability/AMT_Implementation_and_Reference_Guide/HTMLDocuments/MPSDocuments/Intel%20AMT%20Port%20Forwarding%20Protocol%20Reference%20Manual.pdf
+
+ 2) Intel AMT Remote configuration using a Local Agent:
+ A Local Agent enables IT personnel to configure Intel AMT out-of-the-box
+ without requiring installing additional data to enable setup.
+ The remote configuration process may involve an ISV-developed remote
+ configuration agent that runs on the host.
+ For more information:
+ http://software.intel.com/sites/manageability/AMT_Implementation_and_Reference_Guide/WordDocuments/remoteconfigurationwithalocalagent.htm
+
+ How the Local Agent Works (including Command structs):
+ http://software.intel.com/sites/manageability/AMT_Implementation_and_Reference_Guide/WordDocuments/howthelocalagentsampleworks.htm
+
+Intel AMT OS Health Watchdog:
+=============================
+The Intel AMT Watchdog is an OS Health (Hang/Crash) watchdog.
+Whenever the OS hangs or crashes, Intel AMT will send an event
+to whoever subscribed to this event. This mechanism means that
+IT knows when a platform crashes even when there is a hard failure
+on the host.
+The AMT Watchdog is composed of two parts:
+ 1) FW Feature - that receives the heartbeats
+ and sends an event when the heartbeats stop.
+ 2) MEI driver – connects to the watchdog (WD) feature,
+ configures the watchdog and sends the heartbeats.
+
+The MEI driver configures the Watchdog to expire by default
+every 120sec unless set by the user using module parameters.
+The Driver then sends heartbeats every 2sec.
+
+If WD feature does not exist (i.e. the connection failed),
+the MEI driver will disable the sending of heartbeats.
+
+Module Parameters
+=================
+watchdog_timeout - the user can use this module parameter
+to change the watchdog timeout setting.
+
+This value sets the Intel AMT watchdog timeout interval in seconds;
+the default value is 120sec.
+in order to disable the watchdog activites set the value to 0.
+Normal values should be between 120 and 65535
+
+Supported Chipsets:
+==================
+7 Series Chipset Family
+6 Series Chipset Family
+5 Series Chipset Family
+4 Series Chipset Family
+Mobile 4 Series Chipset Family
+ICH9
+82946GZ/GL
+82G35 Express
+82Q963/Q965
+82P965/G965
+Mobile PM965/GM965
+Mobile GME965/GLE960
+82Q35 Express
+82G33/G31/P35/P31 Express
+82Q33 Express
+82X38/X48 Express
+
+---
+linux-mei@linux.intel.com
diff --git a/drivers/staging/mei/mei_dev.h b/drivers/staging/mei/mei_dev.h
new file mode 100644
index 0000000..6f3ec068
--- /dev/null
+++ b/drivers/staging/mei/mei_dev.h
@@ -0,0 +1,422 @@
+/*
+ *
+ * Intel Management Engine Interface (Intel MEI) Linux driver
+ * Copyright (c) 2003-2011, Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+
+#ifndef _MEI_DEV_H_
+#define _MEI_DEV_H_
+
+#include <linux/types.h>
+#include "mei.h"
+#include "hw.h"
+
+/*
+ * MEI Char Driver Minors
+ */
+#define MEI_MINORS_BASE 1
+#define MEI_MINORS_COUNT 1
+#define MEI_MINOR_NUMBER 1
+
+/*
+ * watch dog definition
+ */
+#define MEI_WATCHDOG_DATA_SIZE 16
+#define MEI_START_WD_DATA_SIZE 20
+#define MEI_WD_PARAMS_SIZE 4
+#define MEI_WD_STATE_INDEPENDENCE_MSG_SENT (1 << 0)
+
+/*
+ * AMTHI Client UUID
+ */
+extern const uuid_le mei_amthi_guid;
+
+/*
+ * Watchdog Client UUID
+ */
+extern const uuid_le mei_wd_guid;
+
+/*
+ * Watchdog independence state message
+ */
+extern const u8 mei_wd_state_independence_msg[3][4];
+
+/*
+ * Number of File descriptors/handles
+ * that can be opened to the driver.
+ *
+ * Limit to 253: 255 Total Clients
+ * minus internal client for AMTHI
+ * minus internal client for Watchdog
+ */
+#define MEI_MAX_OPEN_HANDLE_COUNT 253
+
+/*
+ * Number of queue lists used by this driver
+ */
+#define MEI_IO_LISTS_NUMBER 7
+
+/*
+ * Number of Maximum MEI Clients
+ */
+#define MEI_CLIENTS_MAX 255
+
+/* File state */
+enum file_state {
+ MEI_FILE_INITIALIZING = 0,
+ MEI_FILE_CONNECTING,
+ MEI_FILE_CONNECTED,
+ MEI_FILE_DISCONNECTING,
+ MEI_FILE_DISCONNECTED
+};
+
+/* MEI device states */
+enum mei_states {
+ MEI_INITIALIZING = 0,
+ MEI_INIT_CLIENTS,
+ MEI_ENABLED,
+ MEI_RESETING,
+ MEI_DISABLED,
+ MEI_RECOVERING_FROM_RESET,
+ MEI_POWER_DOWN,
+ MEI_POWER_UP
+};
+
+/* init clients states*/
+enum mei_init_clients_states {
+ MEI_START_MESSAGE = 0,
+ MEI_ENUM_CLIENTS_MESSAGE,
+ MEI_CLIENT_PROPERTIES_MESSAGE
+};
+
+enum iamthif_states {
+ MEI_IAMTHIF_IDLE,
+ MEI_IAMTHIF_WRITING,
+ MEI_IAMTHIF_FLOW_CONTROL,
+ MEI_IAMTHIF_READING,
+ MEI_IAMTHIF_READ_COMPLETE
+};
+
+enum mei_file_transaction_states {
+ MEI_IDLE,
+ MEI_WRITING,
+ MEI_WRITE_COMPLETE,
+ MEI_FLOW_CONTROL,
+ MEI_READING,
+ MEI_READ_COMPLETE
+};
+
+/* MEI CB */
+enum mei_cb_major_types {
+ MEI_READ = 0,
+ MEI_WRITE,
+ MEI_IOCTL,
+ MEI_OPEN,
+ MEI_CLOSE
+};
+
+/*
+ * Intel MEI message data struct
+ */
+struct mei_message_data {
+ u32 size;
+ char *data;
+} __packed;
+
+
+struct mei_cl_cb {
+ struct list_head cb_list;
+ enum mei_cb_major_types major_file_operations;
+ void *file_private;
+ struct mei_message_data request_buffer;
+ struct mei_message_data response_buffer;
+ unsigned long information;
+ unsigned long read_time;
+ struct file *file_object;
+};
+
+/* MEI client instance carried as file->pirvate_data*/
+struct mei_cl {
+ struct list_head link;
+ struct mei_device *dev;
+ enum file_state state;
+ wait_queue_head_t tx_wait;
+ wait_queue_head_t rx_wait;
+ wait_queue_head_t wait;
+ int read_pending;
+ int status;
+ /* ID of client connected */
+ u8 host_client_id;
+ u8 me_client_id;
+ u8 mei_flow_ctrl_creds;
+ u8 timer_count;
+ enum mei_file_transaction_states reading_state;
+ enum mei_file_transaction_states writing_state;
+ int sm_state;
+ struct mei_cl_cb *read_cb;
+};
+
+struct mei_io_list {
+ struct mei_cl_cb mei_cb;
+ int status;
+ struct mei_device *device_extension;
+};
+
+/* MEI private device struct */
+struct mei_device {
+ struct pci_dev *pdev; /* pointer to pci device struct */
+ /*
+ * lists of queues
+ */
+ /* array of pointers to aio lists */
+ struct mei_io_list *io_list_array[MEI_IO_LISTS_NUMBER];
+ struct mei_io_list read_list; /* driver read queue */
+ struct mei_io_list write_list; /* driver write queue */
+ struct mei_io_list write_waiting_list; /* write waiting queue */
+ struct mei_io_list ctrl_wr_list; /* managed write IOCTL list */
+ struct mei_io_list ctrl_rd_list; /* managed read IOCTL list */
+ struct mei_io_list amthi_cmd_list; /* amthi list for cmd waiting */
+
+ /* driver managed amthi list for reading completed amthi cmd data */
+ struct mei_io_list amthi_read_complete_list;
+ /*
+ * list of files
+ */
+ struct list_head file_list;
+ /*
+ * memory of device
+ */
+ unsigned int mem_base;
+ unsigned int mem_length;
+ void __iomem *mem_addr;
+ /*
+ * lock for the device
+ */
+ struct mutex device_lock; /* device lock */
+ int recvd_msg;
+ struct delayed_work wd_work; /* watch dog deleye work */
+ /*
+ * hw states of host and fw(ME)
+ */
+ u32 host_hw_state;
+ u32 me_hw_state;
+ /*
+ * waiting queue for receive message from FW
+ */
+ wait_queue_head_t wait_recvd_msg;
+ wait_queue_head_t wait_stop_wd;
+
+ /*
+ * mei device states
+ */
+ enum mei_states mei_state;
+ enum mei_init_clients_states init_clients_state;
+ u16 init_clients_timer;
+ int stop;
+
+ u32 extra_write_index;
+ u32 rd_msg_buf[128]; /* used for control messages */
+ u32 wr_msg_buf[128]; /* used for control messages */
+ u32 ext_msg_buf[8]; /* for control responses */
+ u32 rd_msg_hdr;
+
+ struct hbm_version version;
+
+ int mei_host_buffer_is_empty;
+ struct mei_cl wd_cl;
+ struct mei_me_client *me_clients; /* Note: memory has to be allocated */
+ DECLARE_BITMAP(me_clients_map, MEI_CLIENTS_MAX);
+ DECLARE_BITMAP(host_clients_map, MEI_CLIENTS_MAX);
+ u8 num_mei_me_clients;
+ u8 me_client_presentation_num;
+ u8 me_client_index;
+
+ int wd_pending;
+ int wd_stopped;
+ u16 wd_timeout; /* seconds ((wd_data[1] << 8) + wd_data[0]) */
+ unsigned char wd_data[MEI_START_WD_DATA_SIZE];
+
+
+ u16 wd_due_counter;
+ bool wd_bypass; /* if false, don't refresh watchdog ME client */
+
+ struct file *iamthif_file_object;
+ struct mei_cl iamthif_cl;
+ int iamthif_ioctl;
+ int iamthif_canceled;
+ int iamthif_mtu;
+ unsigned long iamthif_timer;
+ u32 iamthif_stall_timer;
+ unsigned char *iamthif_msg_buf; /* Note: memory has to be allocated */
+ u32 iamthif_msg_buf_size;
+ u32 iamthif_msg_buf_index;
+ int iamthif_flow_control_pending;
+ enum iamthif_states iamthif_state;
+ struct mei_cl_cb *iamthif_current_cb;
+ u8 write_hang;
+ int need_reset;
+ long open_handle_count;
+
+};
+
+
+/*
+ * mei init function prototypes
+ */
+struct mei_device *init_mei_device(struct pci_dev *pdev);
+void mei_reset(struct mei_device *dev, int interrupts);
+int mei_hw_init(struct mei_device *dev);
+int mei_task_initialize_clients(void *data);
+int mei_initialize_clients(struct mei_device *dev);
+struct mei_cl *mei_alloc_file_private(struct mei_device *dev);
+int mei_disconnect_host_client(struct mei_device *dev, struct mei_cl *cl);
+void mei_initialize_list(struct mei_io_list *list,
+ struct mei_device *dev);
+void mei_flush_list(struct mei_io_list *list, struct mei_cl *cl);
+void mei_flush_queues(struct mei_device *dev, struct mei_cl *cl);
+void mei_remove_client_from_file_list(struct mei_device *dev,
+ u8 host_client_id);
+void host_init_iamthif(struct mei_device *dev);
+void mei_init_file_private(struct mei_cl *priv, struct mei_device *dev);
+void allocate_me_clients_storage(struct mei_device *dev);
+
+void host_start_message(struct mei_device *dev);
+void host_enum_clients_message(struct mei_device *dev);
+void host_client_properties(struct mei_device *dev);
+
+u8 mei_find_me_client_update_filext(struct mei_device *dev,
+ struct mei_cl *priv,
+ const uuid_le *cguid, u8 client_id);
+
+/*
+ * interrupt functions prototype
+ */
+irqreturn_t mei_interrupt_quick_handler(int irq, void *dev_id);
+irqreturn_t mei_interrupt_thread_handler(int irq, void *dev_id);
+void mei_wd_timer(struct work_struct *work);
+
+/*
+ * input output function prototype
+ */
+int mei_ioctl_connect_client(struct file *file,
+ struct mei_connect_client_data *data);
+
+int mei_start_read(struct mei_device *dev, struct mei_cl *cl);
+
+int amthi_write(struct mei_device *dev, struct mei_cl_cb *priv_cb);
+
+int amthi_read(struct mei_device *dev, struct file *file,
+ char __user *ubuf, size_t length, loff_t *offset);
+
+struct mei_cl_cb *find_amthi_read_list_entry(struct mei_device *dev,
+ struct file *file);
+
+void run_next_iamthif_cmd(struct mei_device *dev);
+
+void mei_free_cb_private(struct mei_cl_cb *priv_cb);
+
+int mei_find_me_client_index(const struct mei_device *dev, uuid_le cuuid);
+
+/*
+ * Register Access Function
+ */
+
+/**
+ * mei_reg_read - Reads 32bit data from the mei device
+ *
+ * @dev: the device structure
+ * @offset: offset from which to read the data
+ *
+ * returns the byte read.
+ */
+static inline u32 mei_reg_read(struct mei_device *dev,
+ unsigned long offset)
+{
+ return ioread32(dev->mem_addr + offset);
+}
+
+/**
+ * mei_reg_write - Writes 32bit data to the mei device
+ *
+ * @dev: the device structure
+ * @offset: offset from which to write the data
+ * @value: the byte to write
+ */
+static inline void mei_reg_write(struct mei_device *dev,
+ unsigned long offset, u32 value)
+{
+ iowrite32(value, dev->mem_addr + offset);
+}
+
+/**
+ * mei_hcsr_read - Reads 32bit data from the host CSR
+ *
+ * @dev: the device structure
+ *
+ * returns the byte read.
+ */
+static inline u32 mei_hcsr_read(struct mei_device *dev)
+{
+ return mei_reg_read(dev, H_CSR);
+}
+
+/**
+ * mei_mecsr_read - Reads 32bit data from the ME CSR
+ *
+ * @dev: the device structure
+ *
+ * returns ME_CSR_HA register value (u32)
+ */
+static inline u32 mei_mecsr_read(struct mei_device *dev)
+{
+ return mei_reg_read(dev, ME_CSR_HA);
+}
+
+/**
+ * get_me_cb_rw - Reads 32bit data from the mei ME_CB_RW register
+ *
+ * @dev: the device structure
+ *
+ * returns ME_CB_RW register value (u32)
+ */
+static inline u32 mei_mecbrw_read(struct mei_device *dev)
+{
+ return mei_reg_read(dev, ME_CB_RW);
+}
+
+
+/*
+ * mei interface function prototypes
+ */
+void mei_hcsr_set(struct mei_device *dev);
+void mei_csr_clear_his(struct mei_device *dev);
+
+void mei_enable_interrupts(struct mei_device *dev);
+void mei_disable_interrupts(struct mei_device *dev);
+
+/**
+ * mei_fe_same_id - tells if file private data have same id
+ *
+ * @fe1: private data of 1. file object
+ * @fe2: private data of 2. file object
+ *
+ * returns !=0 - if ids are the same, 0 - if differ.
+ */
+static inline int mei_fe_same_id(const struct mei_cl *fe1,
+ const struct mei_cl *fe2)
+{
+ return ((fe1->host_client_id == fe2->host_client_id) &&
+ (fe1->me_client_id == fe2->me_client_id));
+}
+
+#endif
diff --git a/drivers/staging/mei/mei_version.h b/drivers/staging/mei/mei_version.h
new file mode 100644
index 0000000..075bad8
--- /dev/null
+++ b/drivers/staging/mei/mei_version.h
@@ -0,0 +1,31 @@
+/*
+ *
+ * Intel Management Engine Interface (Intel MEI) Linux driver
+ * Copyright (c) 2003-2011, Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+
+
+#ifndef MEI_VERSION_H
+#define MEI_VERSION_H
+
+#define MAJOR_VERSION 7
+#define MINOR_VERSION 1
+#define QUICK_FIX_NUMBER 20
+#define VER_BUILD 1
+
+#define MEI_DRV_VER1 __stringify(MAJOR_VERSION) "." __stringify(MINOR_VERSION)
+#define MEI_DRV_VER2 __stringify(QUICK_FIX_NUMBER) "." __stringify(VER_BUILD)
+
+#define MEI_DRIVER_VERSION MEI_DRV_VER1 "." MEI_DRV_VER2
+
+#endif
diff --git a/drivers/staging/mei/wd.c b/drivers/staging/mei/wd.c
new file mode 100644
index 0000000..2564b03
--- /dev/null
+++ b/drivers/staging/mei/wd.c
@@ -0,0 +1,183 @@
+/*
+ *
+ * Intel Management Engine Interface (Intel MEI) Linux driver
+ * Copyright (c) 2003-2011, Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/device.h>
+#include <linux/pci.h>
+#include <linux/sched.h>
+
+#include "mei_dev.h"
+#include "hw.h"
+#include "interface.h"
+#include "mei.h"
+
+/*
+ * MEI Watchdog Module Parameters
+ */
+static u16 watchdog_timeout = AMT_WD_VALUE;
+module_param(watchdog_timeout, ushort, 0);
+MODULE_PARM_DESC(watchdog_timeout,
+ "Intel(R) AMT Watchdog timeout value in seconds. (default="
+ __MODULE_STRING(AMT_WD_VALUE)
+ ", disable=0)");
+
+static const u8 mei_start_wd_params[] = { 0x02, 0x12, 0x13, 0x10 };
+static const u8 mei_stop_wd_params[] = { 0x02, 0x02, 0x14, 0x10 };
+
+const u8 mei_wd_state_independence_msg[3][4] = {
+ {0x05, 0x02, 0x51, 0x10},
+ {0x05, 0x02, 0x52, 0x10},
+ {0x07, 0x02, 0x01, 0x10}
+};
+
+/* UUIDs for AMT F/W clients */
+const uuid_le mei_wd_guid = UUID_LE(0x05B79A6F, 0x4628, 0x4D7F, 0x89,
+ 0x9D, 0xA9, 0x15, 0x14, 0xCB,
+ 0x32, 0xAB);
+
+
+void mei_wd_start_setup(struct mei_device *dev)
+{
+ dev_dbg(&dev->pdev->dev, "dev->wd_timeout=%d.\n", dev->wd_timeout);
+ memcpy(dev->wd_data, mei_start_wd_params, MEI_WD_PARAMS_SIZE);
+ memcpy(dev->wd_data + MEI_WD_PARAMS_SIZE,
+ &dev->wd_timeout, sizeof(u16));
+}
+
+/**
+ * host_init_wd - mei initialization wd.
+ *
+ * @dev: the device structure
+ */
+void mei_wd_host_init(struct mei_device *dev)
+{
+ mei_init_file_private(&dev->wd_cl, dev);
+
+ /* look for WD client and connect to it */
+ dev->wd_cl.state = MEI_FILE_DISCONNECTED;
+ dev->wd_timeout = watchdog_timeout;
+
+ if (dev->wd_timeout > 0) {
+ mei_wd_start_setup(dev);
+ /* find ME WD client */
+ mei_find_me_client_update_filext(dev, &dev->wd_cl,
+ &mei_wd_guid, MEI_WD_HOST_CLIENT_ID);
+
+ dev_dbg(&dev->pdev->dev, "check wd_cl\n");
+ if (MEI_FILE_CONNECTING == dev->wd_cl.state) {
+ if (!mei_connect(dev, &dev->wd_cl)) {
+ dev_dbg(&dev->pdev->dev, "Failed to connect to WD client\n");
+ dev->wd_cl.state = MEI_FILE_DISCONNECTED;
+ dev->wd_cl.host_client_id = 0;
+ host_init_iamthif(dev) ;
+ } else {
+ dev->wd_cl.timer_count = CONNECT_TIMEOUT;
+ }
+ } else {
+ dev_dbg(&dev->pdev->dev, "Failed to find WD client\n");
+ host_init_iamthif(dev) ;
+ }
+ } else {
+ dev->wd_bypass = true;
+ dev_dbg(&dev->pdev->dev, "WD requested to be disabled\n");
+ host_init_iamthif(dev) ;
+ }
+}
+
+/**
+ * mei_wd_send - sends watch dog message to fw.
+ *
+ * @dev: the device structure
+ *
+ * returns 0 if success,
+ * -EIO when message send fails
+ * -EINVAL when invalid message is to be sent
+ */
+int mei_wd_send(struct mei_device *dev)
+{
+ struct mei_msg_hdr *mei_hdr;
+
+ mei_hdr = (struct mei_msg_hdr *) &dev->wr_msg_buf[0];
+ mei_hdr->host_addr = dev->wd_cl.host_client_id;
+ mei_hdr->me_addr = dev->wd_cl.me_client_id;
+ mei_hdr->msg_complete = 1;
+ mei_hdr->reserved = 0;
+
+ if (!memcmp(dev->wd_data, mei_start_wd_params, MEI_WD_PARAMS_SIZE))
+ mei_hdr->length = MEI_START_WD_DATA_SIZE;
+ else if (!memcmp(dev->wd_data, mei_stop_wd_params, MEI_WD_PARAMS_SIZE))
+ mei_hdr->length = MEI_WD_PARAMS_SIZE;
+ else
+ return -EINVAL;
+
+ if (mei_write_message(dev, mei_hdr, dev->wd_data, mei_hdr->length))
+ return 0;
+ return -EIO;
+}
+
+int mei_wd_stop(struct mei_device *dev, bool preserve)
+{
+ int ret;
+ u16 wd_timeout = dev->wd_timeout;
+
+ cancel_delayed_work(&dev->wd_work);
+ if (dev->wd_cl.state != MEI_FILE_CONNECTED || !dev->wd_timeout)
+ return 0;
+
+ dev->wd_timeout = 0;
+ dev->wd_due_counter = 0;
+ memcpy(dev->wd_data, mei_stop_wd_params, MEI_WD_PARAMS_SIZE);
+ dev->stop = 1;
+
+ ret = mei_flow_ctrl_creds(dev, &dev->wd_cl);
+ if (ret < 0)
+ goto out;
+
+ if (ret && dev->mei_host_buffer_is_empty) {
+ ret = 0;
+ dev->mei_host_buffer_is_empty = 0;
+
+ if (!mei_wd_send(dev)) {
+ ret = mei_flow_ctrl_reduce(dev, &dev->wd_cl);
+ if (ret)
+ goto out;
+ } else {
+ dev_dbg(&dev->pdev->dev, "send stop WD failed\n");
+ }
+
+ dev->wd_pending = 0;
+ } else {
+ dev->wd_pending = 1;
+ }
+ dev->wd_stopped = 0;
+ mutex_unlock(&dev->device_lock);
+
+ ret = wait_event_interruptible_timeout(dev->wait_stop_wd,
+ dev->wd_stopped, 10 * HZ);
+ mutex_lock(&dev->device_lock);
+ if (!dev->wd_stopped)
+ dev_dbg(&dev->pdev->dev, "stop wd failed to complete.\n");
+ else
+ dev_dbg(&dev->pdev->dev, "stop wd complete.\n");
+
+ if (preserve)
+ dev->wd_timeout = wd_timeout;
+
+out:
+ return ret;
+}
+
diff --git a/drivers/staging/nvec/Kconfig b/drivers/staging/nvec/Kconfig
new file mode 100644
index 0000000..987ad48
--- /dev/null
+++ b/drivers/staging/nvec/Kconfig
@@ -0,0 +1,27 @@
+config MFD_NVEC
+ bool "NV Tegra Embedded Controller SMBus Interface"
+ depends on I2C && GPIOLIB && ARCH_TEGRA
+ help
+ Say Y here to enable support for a nVidia compliant embedded
+ controller.
+
+config KEYBOARD_NVEC
+ bool "Keyboard on nVidia compliant EC"
+ depends on MFD_NVEC
+ help
+ Say Y here to enable support for a keyboard connected to
+ a nVidia compliant embedded controller.
+
+config SERIO_NVEC_PS2
+ bool "PS2 on nVidia EC"
+ depends on MFD_NVEC
+ help
+ Say Y here to enable support for a Touchpad / Mouse connected
+ to a nVidia compliant embedded controller.
+
+config NVEC_POWER
+ bool "NVEC charger and battery"
+ depends on MFD_NVEC
+ help
+ Say Y to enable support for battery and charger interface for
+ nVidia compliant embedded controllers.
diff --git a/drivers/staging/nvec/Makefile b/drivers/staging/nvec/Makefile
new file mode 100644
index 0000000..4b5fcec1
--- /dev/null
+++ b/drivers/staging/nvec/Makefile
@@ -0,0 +1,4 @@
+obj-$(CONFIG_SERIO_NVEC_PS2) += nvec_ps2.o
+obj-$(CONFIG_MFD_NVEC) += nvec.o
+obj-$(CONFIG_NVEC_POWER) += nvec_power.o
+obj-$(CONFIG_KEYBOARD_NVEC) += nvec_kbd.o
diff --git a/drivers/staging/nvec/README b/drivers/staging/nvec/README
new file mode 100644
index 0000000..9a320b7
--- /dev/null
+++ b/drivers/staging/nvec/README
@@ -0,0 +1,14 @@
+NVEC: An NVidia compliant Embedded Controller Protocol Implemenation
+
+This is an implementation of the NVEC protocol used to communicate with an
+embedded controller (EC) via I2C bus. The EC is an I2C master while the host
+processor is the I2C slave. Requests from the host processor to the EC are
+started by triggering a gpio line.
+
+There is no written documentation of the protocol available to the public,
+but the source code[1] of the published nvec reference drivers can be a guide.
+This driver is currently only used by the AC100 project[2], but it is likely,
+that other Tegra boards (not yet mainlined, if ever) also use it.
+
+[1] e.g. http://nv-tegra.nvidia.com/gitweb/?p=linux-2.6.git;a=tree;f=arch/arm/mach-tegra/nvec;hb=android-tegra-2.6.32
+[2] http://gitorious.org/ac100, http://launchpad.net/ac100
diff --git a/drivers/staging/nvec/TODO b/drivers/staging/nvec/TODO
new file mode 100644
index 0000000..77b47f7
--- /dev/null
+++ b/drivers/staging/nvec/TODO
@@ -0,0 +1,8 @@
+ToDo list (incomplete, unordered)
+ - convert mouse, keyboard, and power to platform devices
+ - add copyright / driver author / license
+ - add compile as module support
+ - move nvec devices to mfd cells?
+ - adjust to kernel style
+
+
diff --git a/drivers/staging/nvec/nvec-keytable.h b/drivers/staging/nvec/nvec-keytable.h
new file mode 100644
index 0000000..6a1c4f7
--- /dev/null
+++ b/drivers/staging/nvec/nvec-keytable.h
@@ -0,0 +1,266 @@
+/*
+ * drivers/input/keyboard/tegra-nvec.c
+ *
+ * Keyboard class input driver for keyboards connected to an NvEc compliant
+ * embedded controller
+ *
+ * Copyright (c) 2009, NVIDIA Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ */
+
+static unsigned short code_tab_102us[] = {
+ KEY_GRAVE, // 0x00
+ KEY_ESC,
+ KEY_1,
+ KEY_2,
+ KEY_3,
+ KEY_4,
+ KEY_5,
+ KEY_6,
+ KEY_7,
+ KEY_8,
+ KEY_9,
+ KEY_0,
+ KEY_MINUS,
+ KEY_EQUAL,
+ KEY_BACKSPACE,
+ KEY_TAB,
+ KEY_Q, // 0x10
+ KEY_W,
+ KEY_E,
+ KEY_R,
+ KEY_T,
+ KEY_Y,
+ KEY_U,
+ KEY_I,
+ KEY_O,
+ KEY_P,
+ KEY_LEFTBRACE,
+ KEY_RIGHTBRACE,
+ KEY_ENTER,
+ KEY_LEFTCTRL,
+ KEY_A,
+ KEY_S,
+ KEY_D, // 0x20
+ KEY_F,
+ KEY_G,
+ KEY_H,
+ KEY_J,
+ KEY_K,
+ KEY_L,
+ KEY_SEMICOLON,
+ KEY_APOSTROPHE,
+ KEY_GRAVE,
+ KEY_LEFTSHIFT,
+ KEY_BACKSLASH,
+ KEY_Z,
+ KEY_X,
+ KEY_C,
+ KEY_V,
+ KEY_B, // 0x30
+ KEY_N,
+ KEY_M,
+ KEY_COMMA,
+ KEY_DOT,
+ KEY_SLASH,
+ KEY_RIGHTSHIFT,
+ KEY_KPASTERISK,
+ KEY_LEFTALT,
+ KEY_SPACE,
+ KEY_CAPSLOCK,
+ KEY_F1,
+ KEY_F2,
+ KEY_F3,
+ KEY_F4,
+ KEY_F5,
+ KEY_F6, // 0x40
+ KEY_F7,
+ KEY_F8,
+ KEY_F9,
+ KEY_F10,
+ KEY_FN,
+ 0, //VK_SCROLL
+ KEY_KP7,
+ KEY_KP8,
+ KEY_KP9,
+ KEY_KPMINUS,
+ KEY_KP4,
+ KEY_KP5,
+ KEY_KP6,
+ KEY_KPPLUS,
+ KEY_KP1,
+ KEY_KP2, // 0x50
+ KEY_KP3,
+ KEY_KP0,
+ KEY_KPDOT,
+ KEY_MENU, //VK_SNAPSHOT
+ KEY_POWER,
+ KEY_102ND, //VK_OEM_102 henry+ 0x2B (43) BACKSLASH have been used,change to use 0X56 (86)
+ KEY_F11, //VK_F11
+ KEY_F12, //VK_F12
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0, // 60
+ 0,
+ 0,
+ KEY_SEARCH, // add search key map
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0, // 70
+ 0,
+ 0,
+ KEY_KP5, //73 for JP keyboard '\' key, report 0x4c
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ KEY_KP9, //7d for JP keyboard '|' key, report 0x49
+};
+
+static unsigned short extcode_tab_us102[] = {
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0, // 0xE0 0x10
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0, //VK_MEDIA_NEXT_TRACK,
+ 0,
+ 0,
+ 0, //VK_RETURN,
+ KEY_RIGHTCTRL, //VK_RCONTROL,
+ 0,
+ 0,
+ KEY_MUTE, // 0xE0 0x20
+ 0, //VK_LAUNCH_APP1
+ 0, //VK_MEDIA_PLAY_PAUSE
+ 0,
+ 0, //VK_MEDIA_STOP
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ KEY_VOLUMEUP, // 0xE0 0x30
+ 0,
+ 0, //VK_BROWSER_HOME
+ 0,
+ 0,
+ KEY_KPSLASH, //VK_DIVIDE
+ 0,
+ KEY_SYSRQ, //VK_SNAPSHOT
+ KEY_RIGHTALT, //VK_RMENU
+ 0, //VK_OEM_NV_BACKLIGHT_UP
+ 0, //VK_OEM_NV_BACKLIGHT_DN
+ 0, //VK_OEM_NV_BACKLIGHT_AUTOTOGGLE
+ 0, //VK_OEM_NV_POWER_INFO
+ 0, //VK_OEM_NV_WIFI_TOGGLE
+ 0, //VK_OEM_NV_DISPLAY_SELECT
+ 0, //VK_OEM_NV_AIRPLANE_TOGGLE
+ 0, //0xE0 0x40
+ KEY_LEFT, //VK_OEM_NV_RESERVED henry+ for JP keyboard
+ 0, //VK_OEM_NV_RESERVED
+ 0, //VK_OEM_NV_RESERVED
+ 0, //VK_OEM_NV_RESERVED
+ 0, //VK_OEM_NV_RESERVED
+ KEY_CANCEL,
+ KEY_HOME,
+ KEY_UP,
+ KEY_PAGEUP, //VK_PRIOR
+ 0,
+ KEY_LEFT,
+ 0,
+ KEY_RIGHT,
+ 0,
+ KEY_END,
+ KEY_DOWN, // 0xE0 0x50
+ KEY_PAGEDOWN, //VK_NEXT
+ KEY_INSERT,
+ KEY_DELETE,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ KEY_LEFTMETA, //VK_LWIN
+ 0, //VK_RWIN
+ KEY_ESC, //VK_APPS
+ KEY_KPMINUS, //for power button workaround
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0,
+ 0, //VK_BROWSER_SEARCH
+ 0, //VK_BROWSER_FAVORITES
+ 0, //VK_BROWSER_REFRESH
+ 0, //VK_BROWSER_STOP
+ 0, //VK_BROWSER_FORWARD
+ 0, //VK_BROWSER_BACK
+ 0, //VK_LAUNCH_APP2
+ 0, //VK_LAUNCH_MAIL
+ 0, //VK_LAUNCH_MEDIA_SELECT
+};
+
+static unsigned short* code_tabs[] = {code_tab_102us, extcode_tab_us102 };
diff --git a/drivers/staging/nvec/nvec.c b/drivers/staging/nvec/nvec.c
new file mode 100644
index 0000000..1a94364
--- /dev/null
+++ b/drivers/staging/nvec/nvec.c
@@ -0,0 +1,468 @@
+// #define DEBUG
+
+/* ToDo list (incomplete, unorderd)
+ - convert mouse, keyboard, and power to platform devices
+*/
+
+#include <asm/io.h>
+#include <asm/irq.h>
+#include <linux/completion.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/slab.h>
+#include <linux/gpio.h>
+#include <linux/serio.h>
+#include <linux/delay.h>
+#include <linux/input.h>
+#include <linux/workqueue.h>
+#include <linux/clk.h>
+#include <mach/iomap.h>
+#include <mach/clk.h>
+#include <linux/semaphore.h>
+#include <linux/list.h>
+#include <linux/notifier.h>
+#include <linux/workqueue.h>
+#include <linux/platform_device.h>
+#include "nvec.h"
+
+static unsigned char EC_DISABLE_EVENT_REPORTING[] = {'\x04','\x00','\x00'};
+static unsigned char EC_ENABLE_EVENT_REPORTING[] = {'\x04','\x00','\x01'};
+static unsigned char EC_GET_FIRMWARE_VERSION[] = {'\x07','\x15'};
+
+static struct nvec_chip *nvec_power_handle;
+
+int nvec_register_notifier(struct nvec_chip *nvec, struct notifier_block *nb,
+ unsigned int events)
+{
+ return atomic_notifier_chain_register(&nvec->notifier_list, nb);
+}
+EXPORT_SYMBOL_GPL(nvec_register_notifier);
+
+static int nvec_status_notifier(struct notifier_block *nb, unsigned long event_type,
+ void *data)
+{
+ unsigned char *msg = (unsigned char *)data;
+ int i;
+
+ if(event_type != NVEC_CNTL)
+ return NOTIFY_DONE;
+
+ printk("unhandled msg type %ld, payload: ", event_type);
+ for (i = 0; i < msg[1]; i++)
+ printk("%0x ", msg[i+2]);
+ printk("\n");
+
+ return NOTIFY_OK;
+}
+
+void nvec_write_async(struct nvec_chip *nvec, unsigned char *data, short size)
+{
+ struct nvec_msg *msg = kzalloc(sizeof(struct nvec_msg), GFP_NOWAIT);
+
+ msg->data = kzalloc(size, GFP_NOWAIT);
+ msg->data[0] = size;
+ memcpy(msg->data + 1, data, size);
+ msg->size = size + 1;
+ msg->pos = 0;
+ INIT_LIST_HEAD(&msg->node);
+
+ list_add_tail(&msg->node, &nvec->tx_data);
+
+ gpio_set_value(nvec->gpio, 0);
+}
+EXPORT_SYMBOL(nvec_write_async);
+
+static void nvec_request_master(struct work_struct *work)
+{
+ struct nvec_chip *nvec = container_of(work, struct nvec_chip, tx_work);
+
+ if(!list_empty(&nvec->tx_data)) {
+ gpio_set_value(nvec->gpio, 0);
+ }
+}
+
+static int parse_msg(struct nvec_chip *nvec, struct nvec_msg *msg)
+{
+ int i;
+
+ if((msg->data[0] & 1<<7) == 0 && msg->data[3]) {
+ dev_err(nvec->dev, "ec responded %02x %02x %02x %02x\n", msg->data[0],
+ msg->data[1], msg->data[2], msg->data[3]);
+ return -EINVAL;
+ }
+
+ if ((msg->data[0] >> 7 ) == 1 && (msg->data[0] & 0x0f) == 5)
+ {
+ dev_warn(nvec->dev, "ec system event ");
+ for (i=0; i < msg->data[1]; i++)
+ dev_warn(nvec->dev, "%02x ", msg->data[2+i]);
+ dev_warn(nvec->dev, "\n");
+ }
+
+ atomic_notifier_call_chain(&nvec->notifier_list, msg->data[0] & 0x8f, msg->data);
+
+ return 0;
+}
+
+static struct nvec_msg *nvec_write_sync(struct nvec_chip *nvec, unsigned char *data, short size)
+{
+ down(&nvec->sync_write_mutex);
+
+ nvec->sync_write_pending = (data[1] << 8) + data[0];
+ nvec_write_async(nvec, data, size);
+
+ dev_dbg(nvec->dev, "nvec_sync_write: 0x%04x\n", nvec->sync_write_pending);
+ wait_for_completion(&nvec->sync_write);
+ dev_dbg(nvec->dev, "nvec_sync_write: pong!\n");
+
+ up(&nvec->sync_write_mutex);
+
+ return nvec->last_sync_msg;
+}
+
+/* RX worker */
+static void nvec_dispatch(struct work_struct *work)
+{
+ struct nvec_chip *nvec = container_of(work, struct nvec_chip, rx_work);
+ struct nvec_msg *msg;
+
+ while(!list_empty(&nvec->rx_data))
+ {
+ msg = list_first_entry(&nvec->rx_data, struct nvec_msg, node);
+ list_del_init(&msg->node);
+
+ if(nvec->sync_write_pending == (msg->data[2] << 8) + msg->data[0])
+ {
+ dev_dbg(nvec->dev, "sync write completed!\n");
+ nvec->sync_write_pending = 0;
+ nvec->last_sync_msg = msg;
+ complete(&nvec->sync_write);
+ } else {
+ parse_msg(nvec, msg);
+ if((!msg) || (!msg->data))
+ dev_warn(nvec->dev, "attempt access zero pointer");
+ else {
+ kfree(msg->data);
+ kfree(msg);
+ }
+ }
+ }
+}
+
+static irqreturn_t i2c_interrupt(int irq, void *dev)
+{
+ unsigned long status;
+ unsigned long received;
+ unsigned char to_send;
+ struct nvec_msg *msg;
+ struct nvec_chip *nvec = (struct nvec_chip *)dev;
+ unsigned char *i2c_regs = nvec->i2c_regs;
+
+ status = readl(i2c_regs + I2C_SL_STATUS);
+
+ if(!(status & I2C_SL_IRQ))
+ {
+ dev_warn(nvec->dev, "nvec Spurious IRQ\n");
+ //Yup, handled. ahum.
+ goto handled;
+ }
+ if(status & END_TRANS && !(status & RCVD))
+ {
+ //Reenable IRQ only when even has been sent
+ //printk("Write sequence ended !\n");
+ //parse_msg(nvec);
+ nvec->state = NVEC_WAIT;
+ if(nvec->rx->size > 1)
+ {
+ list_add_tail(&nvec->rx->node, &nvec->rx_data);
+ schedule_work(&nvec->rx_work);
+ } else {
+ kfree(nvec->rx->data);
+ kfree(nvec->rx);
+ }
+ return IRQ_HANDLED;
+ } else if(status & RNW)
+ {
+ // Work around for AP20 New Slave Hw Bug. Give 1us extra.
+ // nvec/smbus/nvec_i2c_transport.c in NV`s crap for reference
+ if(status & RCVD)
+ udelay(3);
+
+ if(status & RCVD)
+ {
+ nvec->state = NVEC_WRITE;
+ //Master wants something from us. New communication
+// dev_dbg(nvec->dev, "New read comm!\n");
+ } else {
+ //Master wants something from us from a communication we've already started
+// dev_dbg(nvec->dev, "Read comm cont !\n");
+ }
+ //if(msg_pos<msg_size) {
+ if(list_empty(&nvec->tx_data))
+ {
+ dev_err(nvec->dev, "nvec empty tx - sending no-op\n");
+ to_send = 0x8a;
+ nvec_write_async(nvec, "\x07\x02", 2);
+// to_send = 0x01;
+ } else {
+ msg = list_first_entry(&nvec->tx_data, struct nvec_msg, node);
+ if(msg->pos < msg->size) {
+ to_send = msg->data[msg->pos];
+ msg->pos++;
+ } else {
+ dev_err(nvec->dev, "nvec crap! %d\n", msg->size);
+ to_send = 0x01;
+ }
+
+ if(msg->pos >= msg->size)
+ {
+ list_del_init(&msg->node);
+ kfree(msg->data);
+ kfree(msg);
+ schedule_work(&nvec->tx_work);
+ nvec->state = NVEC_WAIT;
+ }
+ }
+ writel(to_send, i2c_regs + I2C_SL_RCVD);
+
+ gpio_set_value(nvec->gpio, 1);
+
+ dev_dbg(nvec->dev, "nvec sent %x\n", to_send);
+
+ goto handled;
+ } else {
+ received = readl(i2c_regs + I2C_SL_RCVD);
+ //Workaround?
+ if(status & RCVD) {
+ writel(0, i2c_regs + I2C_SL_RCVD);
+ goto handled;
+ }
+
+ if (nvec->state == NVEC_WAIT)
+ {
+ nvec->state = NVEC_READ;
+ msg = kzalloc(sizeof(struct nvec_msg), GFP_NOWAIT);
+ msg->data = kzalloc(32, GFP_NOWAIT);
+ INIT_LIST_HEAD(&msg->node);
+ nvec->rx = msg;
+ } else
+ msg = nvec->rx;
+
+ BUG_ON(msg->pos > 32);
+
+ msg->data[msg->pos] = received;
+ msg->pos++;
+ msg->size = msg->pos;
+ dev_dbg(nvec->dev, "Got %02lx from Master (pos: %d)!\n", received, msg->pos);
+ }
+handled:
+ return IRQ_HANDLED;
+}
+
+static int __devinit nvec_add_subdev(struct nvec_chip *nvec, struct nvec_subdev *subdev)
+{
+ struct platform_device *pdev;
+
+ pdev = platform_device_alloc(subdev->name, subdev->id);
+ pdev->dev.parent = nvec->dev;
+ pdev->dev.platform_data = subdev->platform_data;
+
+ return platform_device_add(pdev);
+}
+
+static void tegra_init_i2c_slave(struct nvec_platform_data *pdata, unsigned char *i2c_regs,
+ struct clk *i2c_clk)
+{
+ u32 val;
+
+ clk_enable(i2c_clk);
+ tegra_periph_reset_assert(i2c_clk);
+ udelay(2);
+ tegra_periph_reset_deassert(i2c_clk);
+
+ writel(pdata->i2c_addr>>1, i2c_regs + I2C_SL_ADDR1);
+ writel(0, i2c_regs + I2C_SL_ADDR2);
+
+ writel(0x1E, i2c_regs + I2C_SL_DELAY_COUNT);
+ val = I2C_CNFG_NEW_MASTER_SFM | I2C_CNFG_PACKET_MODE_EN |
+ (0x2 << I2C_CNFG_DEBOUNCE_CNT_SHIFT);
+ writel(val, i2c_regs + I2C_CNFG);
+ writel(I2C_SL_NEWL, i2c_regs + I2C_SL_CNFG);
+
+ clk_disable(i2c_clk);
+}
+
+static void nvec_power_off(void)
+{
+ nvec_write_async(nvec_power_handle, EC_DISABLE_EVENT_REPORTING, 3);
+ nvec_write_async(nvec_power_handle, "\x04\x01", 2);
+}
+
+static int __devinit tegra_nvec_probe(struct platform_device *pdev)
+{
+ int err, i, ret;
+ struct clk *i2c_clk;
+ struct nvec_platform_data *pdata = pdev->dev.platform_data;
+ struct nvec_chip *nvec;
+ struct nvec_msg *msg;
+ unsigned char *i2c_regs;
+
+ nvec = kzalloc(sizeof(struct nvec_chip), GFP_KERNEL);
+ if(nvec == NULL) {
+ dev_err(&pdev->dev, "failed to reserve memory\n");
+ return -ENOMEM;
+ }
+ platform_set_drvdata(pdev, nvec);
+ nvec->dev = &pdev->dev;
+ nvec->gpio = pdata->gpio;
+ nvec->irq = pdata->irq;
+
+/*
+ i2c_clk=clk_get_sys(NULL, "i2c");
+ if(IS_ERR_OR_NULL(i2c_clk))
+ printk(KERN_ERR"No such clock tegra-i2c.2\n");
+ else
+ clk_enable(i2c_clk);
+*/
+ i2c_regs = ioremap(pdata->base, pdata->size);
+ if(!i2c_regs) {
+ dev_err(nvec->dev, "failed to ioremap registers\n");
+ goto failed;
+ }
+
+ nvec->i2c_regs = i2c_regs;
+
+ i2c_clk = clk_get_sys(pdata->clock, NULL);
+ if(IS_ERR_OR_NULL(i2c_clk)) {
+ dev_err(nvec->dev, "failed to get clock tegra-i2c.2\n");
+ goto failed;
+ }
+
+ tegra_init_i2c_slave(pdata, i2c_regs, i2c_clk);
+
+ err = request_irq(nvec->irq, i2c_interrupt, IRQF_DISABLED, "nvec", nvec);
+ if(err) {
+ dev_err(nvec->dev, "couldn't request irq");
+ goto failed;
+ }
+
+ clk_enable(i2c_clk);
+ clk_set_rate(i2c_clk, 8*80000);
+
+ /* Set the gpio to low when we've got something to say */
+ err = gpio_request(nvec->gpio, "nvec gpio");
+ if(err < 0)
+ dev_err(nvec->dev, "couldn't request gpio\n");
+
+ tegra_gpio_enable(nvec->gpio);
+ gpio_direction_output(nvec->gpio, 1);
+ gpio_set_value(nvec->gpio, 1);
+
+ ATOMIC_INIT_NOTIFIER_HEAD(&nvec->notifier_list);
+
+ init_completion(&nvec->sync_write);
+ sema_init(&nvec->sync_write_mutex, 1);
+ INIT_LIST_HEAD(&nvec->tx_data);
+ INIT_LIST_HEAD(&nvec->rx_data);
+ INIT_WORK(&nvec->rx_work, nvec_dispatch);
+ INIT_WORK(&nvec->tx_work, nvec_request_master);
+
+ /* enable event reporting */
+ nvec_write_async(nvec, EC_ENABLE_EVENT_REPORTING,
+ sizeof(EC_ENABLE_EVENT_REPORTING));
+
+ nvec_kbd_init(nvec);
+#ifdef CONFIG_SERIO_NVEC_PS2
+ nvec_ps2(nvec);
+#endif
+
+ /* setup subdevs */
+ for (i = 0; i < pdata->num_subdevs; i++) {
+ ret = nvec_add_subdev(nvec, &pdata->subdevs[i]);
+ }
+
+ nvec->nvec_status_notifier.notifier_call = nvec_status_notifier;
+ nvec_register_notifier(nvec, &nvec->nvec_status_notifier, 0);
+
+ nvec_power_handle = nvec;
+ pm_power_off = nvec_power_off;
+
+ /* Get Firmware Version */
+ msg = nvec_write_sync(nvec, EC_GET_FIRMWARE_VERSION,
+ sizeof(EC_GET_FIRMWARE_VERSION));
+
+ dev_warn(nvec->dev, "ec firmware version %02x.%02x.%02x / %02x\n",
+ msg->data[4], msg->data[5], msg->data[6], msg->data[7]);
+
+ kfree(msg->data);
+ kfree(msg);
+
+ /* unmute speakers? */
+ nvec_write_async(nvec, "\x0d\x10\x59\x94", 4);
+
+ /* enable lid switch event */
+ nvec_write_async(nvec, "\x01\x01\x01\x00\x00\x02\x00", 7);
+
+ /* enable power button event */
+ nvec_write_async(nvec, "\x01\x01\x01\x00\x00\x80\x00", 7);
+
+ return 0;
+
+failed:
+ kfree(nvec);
+ return -ENOMEM;
+}
+
+static int __devexit tegra_nvec_remove(struct platform_device *pdev)
+{
+ // TODO: unregister
+ return 0;
+}
+
+#ifdef CONFIG_PM
+
+static int tegra_nvec_suspend(struct platform_device *pdev, pm_message_t state)
+{
+ struct nvec_chip *nvec = platform_get_drvdata(pdev);
+
+ dev_dbg(nvec->dev, "suspending\n");
+ nvec_write_async(nvec, EC_DISABLE_EVENT_REPORTING, 3);
+ nvec_write_async(nvec, "\x04\x02", 2);
+
+ return 0;
+}
+
+static int tegra_nvec_resume(struct platform_device *pdev) {
+
+ struct nvec_chip *nvec = platform_get_drvdata(pdev);
+
+ dev_dbg(nvec->dev, "resuming\n");
+ nvec_write_async(nvec, EC_ENABLE_EVENT_REPORTING, 3);
+
+ return 0;
+}
+
+#else
+#define tegra_nvec_suspend NULL
+#define tegra_nvec_resume NULL
+#endif
+
+static struct platform_driver nvec_device_driver =
+{
+ .probe = tegra_nvec_probe,
+ .remove = __devexit_p(tegra_nvec_remove),
+ .suspend = tegra_nvec_suspend,
+ .resume = tegra_nvec_resume,
+ .driver = {
+ .name = "nvec",
+ .owner = THIS_MODULE,
+ }
+};
+
+static int __init tegra_nvec_init(void)
+{
+ return platform_driver_register(&nvec_device_driver);
+}
+
+module_init(tegra_nvec_init);
+MODULE_ALIAS("platform:nvec");
diff --git a/drivers/staging/nvec/nvec.h b/drivers/staging/nvec/nvec.h
new file mode 100644
index 0000000..a2d82dc
--- /dev/null
+++ b/drivers/staging/nvec/nvec.h
@@ -0,0 +1,110 @@
+#ifndef __LINUX_MFD_NVEC
+#define __LINUX_MFD_NVEC
+
+#include <linux/semaphore.h>
+
+typedef enum {
+ NVEC_2BYTES,
+ NVEC_3BYTES,
+ NVEC_VAR_SIZE
+} nvec_size;
+
+typedef enum {
+ NOT_REALLY,
+ YES,
+ NOT_AT_ALL,
+} how_care;
+
+typedef enum {
+ NVEC_SYS=1,
+ NVEC_BAT,
+ NVEC_KBD = 5,
+ NVEC_PS2,
+ NVEC_CNTL,
+ NVEC_KB_EVT = 0x80,
+ NVEC_PS2_EVT
+} nvec_event;
+
+typedef enum {
+ NVEC_WAIT,
+ NVEC_READ,
+ NVEC_WRITE
+} nvec_state;
+
+struct nvec_msg {
+ unsigned char *data;
+ unsigned short size;
+ unsigned short pos;
+ struct list_head node;
+};
+
+struct nvec_subdev {
+ const char *name;
+ void *platform_data;
+ int id;
+};
+
+struct nvec_platform_data {
+ int num_subdevs;
+ int i2c_addr;
+ int gpio;
+ int irq;
+ int base;
+ int size;
+ char clock[16];
+ struct nvec_subdev *subdevs;
+};
+
+struct nvec_chip {
+ struct device *dev;
+ int gpio;
+ int irq;
+ unsigned char *i2c_regs;
+ nvec_state state;
+ struct atomic_notifier_head notifier_list;
+ struct list_head rx_data, tx_data;
+ struct notifier_block nvec_status_notifier;
+ struct work_struct rx_work, tx_work;
+ struct nvec_msg *rx, *tx;
+
+/* sync write stuff */
+ struct semaphore sync_write_mutex;
+ struct completion sync_write;
+ u16 sync_write_pending;
+ struct nvec_msg *last_sync_msg;
+};
+
+extern void nvec_write_async(struct nvec_chip *nvec, unsigned char *data, short size);
+
+extern int nvec_register_notifier(struct nvec_chip *nvec,
+ struct notifier_block *nb, unsigned int events);
+
+extern int nvec_unregister_notifier(struct device *dev,
+ struct notifier_block *nb, unsigned int events);
+
+const char *nvec_send_msg(unsigned char *src, unsigned char *dst_size, how_care care_resp, void (*rt_handler)(unsigned char *data));
+
+extern int nvec_ps2(struct nvec_chip *nvec);
+extern int nvec_kbd_init(struct nvec_chip *nvec);
+
+#define I2C_CNFG 0x00
+#define I2C_CNFG_PACKET_MODE_EN (1<<10)
+#define I2C_CNFG_NEW_MASTER_SFM (1<<11)
+#define I2C_CNFG_DEBOUNCE_CNT_SHIFT 12
+
+#define I2C_SL_CNFG 0x20
+#define I2C_SL_NEWL (1<<2)
+#define I2C_SL_NACK (1<<1)
+#define I2C_SL_RESP (1<<0)
+#define I2C_SL_IRQ (1<<3)
+#define END_TRANS (1<<4)
+#define RCVD (1<<2)
+#define RNW (1<<1)
+
+#define I2C_SL_RCVD 0x24
+#define I2C_SL_STATUS 0x28
+#define I2C_SL_ADDR1 0x2c
+#define I2C_SL_ADDR2 0x30
+#define I2C_SL_DELAY_COUNT 0x3c
+
+#endif
diff --git a/drivers/staging/nvec/nvec_kbd.c b/drivers/staging/nvec/nvec_kbd.c
new file mode 100644
index 0000000..9a98507
--- /dev/null
+++ b/drivers/staging/nvec/nvec_kbd.c
@@ -0,0 +1,122 @@
+#include <linux/slab.h>
+#include <linux/input.h>
+#include <linux/delay.h>
+#include "nvec-keytable.h"
+#include "nvec.h"
+
+#define ACK_KBD_EVENT {'\x05','\xed','\x01'}
+
+static unsigned char keycodes[ARRAY_SIZE(code_tab_102us)
+ + ARRAY_SIZE(extcode_tab_us102)];
+
+struct nvec_keys {
+ struct input_dev *input;
+ struct notifier_block notifier;
+ struct nvec_chip *nvec;
+};
+
+static struct nvec_keys keys_dev;
+
+static int nvec_keys_notifier(struct notifier_block *nb,
+ unsigned long event_type, void *data)
+{
+ int code, state;
+ unsigned char *msg = (unsigned char *)data;
+
+ if (event_type == NVEC_KB_EVT) {
+ nvec_size _size = (msg[0] & (3 << 5)) >> 5;
+
+/* power on/off button */
+ if(_size == NVEC_VAR_SIZE)
+ return NOTIFY_STOP;
+
+ if(_size == NVEC_3BYTES)
+ msg++;
+
+ code = msg[1] & 0x7f;
+ state = msg[1] & 0x80;
+
+ input_report_key(keys_dev.input, code_tabs[_size][code], !state);
+ input_sync(keys_dev.input);
+
+ return NOTIFY_STOP;
+ }
+
+ return NOTIFY_DONE;
+}
+
+static int nvec_kbd_event(struct input_dev *dev, unsigned int type,
+ unsigned int code, int value)
+{
+ unsigned char buf[] = ACK_KBD_EVENT;
+ struct nvec_chip *nvec = keys_dev.nvec;
+
+ if(type==EV_REP)
+ return 0;
+
+ if(type!=EV_LED)
+ return -1;
+
+ if(code!=LED_CAPSL)
+ return -1;
+
+ buf[2] = !!value;
+ nvec_write_async(nvec, buf, sizeof(buf));
+
+ return 0;
+}
+
+int __init nvec_kbd_init(struct nvec_chip *nvec)
+{
+ int i, j, err;
+ struct input_dev *idev;
+
+ j = 0;
+
+ for(i = 0; i < ARRAY_SIZE(code_tab_102us); ++i)
+ keycodes[j++] = code_tab_102us[i];
+
+ for(i = 0; i < ARRAY_SIZE(extcode_tab_us102); ++i)
+ keycodes[j++]=extcode_tab_us102[i];
+
+ idev = input_allocate_device();
+ idev->name = "Tegra nvec keyboard";
+ idev->phys = "i2c3_slave/nvec";
+ idev->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_REP) | BIT_MASK(EV_LED);
+ idev->ledbit[0] = BIT_MASK(LED_CAPSL);
+ idev->event = nvec_kbd_event;
+ idev->keycode = keycodes;
+ idev->keycodesize = sizeof(unsigned char);
+ idev->keycodemax = ARRAY_SIZE(keycodes);
+
+ for( i = 0; i < ARRAY_SIZE(keycodes); ++i)
+ set_bit(keycodes[i], idev->keybit);
+
+ clear_bit(0, idev->keybit);
+ err = input_register_device(idev);
+ if(err)
+ goto fail;
+
+ keys_dev.input = idev;
+ keys_dev.notifier.notifier_call = nvec_keys_notifier;
+ keys_dev.nvec = nvec;
+ nvec_register_notifier(nvec, &keys_dev.notifier, 0);
+
+ /* Enable keyboard */
+ nvec_write_async(nvec, "\x05\xf4", 2);
+
+ /* keyboard reset? */
+ nvec_write_async(nvec, "\x05\x03\x01\x01", 4);
+ nvec_write_async(nvec, "\x05\x04\x01", 3);
+ nvec_write_async(nvec, "\x06\x01\xff\x03", 4);
+/* FIXME
+ wait until keyboard reset is finished
+ or until we have a sync write */
+ mdelay(1000);
+
+ return 0;
+
+fail:
+ input_free_device(idev);
+ return err;
+}
diff --git a/drivers/staging/nvec/nvec_power.c b/drivers/staging/nvec/nvec_power.c
new file mode 100644
index 0000000..df164ad
--- /dev/null
+++ b/drivers/staging/nvec/nvec_power.c
@@ -0,0 +1,418 @@
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/err.h>
+#include <linux/power_supply.h>
+#include <linux/slab.h>
+#include <linux/workqueue.h>
+#include <linux/delay.h>
+#include "nvec.h"
+
+struct nvec_power
+{
+ struct notifier_block notifier;
+ struct delayed_work poller;
+ struct nvec_chip *nvec;
+ int on;
+ int bat_present;
+ int bat_status;
+ int bat_voltage_now;
+ int bat_current_now;
+ int bat_current_avg;
+ int time_remain;
+ int charge_full_design;
+ int charge_last_full;
+ int critical_capacity;
+ int capacity_remain;
+ int bat_temperature;
+ int bat_cap;
+ int bat_type_enum;
+ char bat_manu[30];
+ char bat_model[30];
+ char bat_type[30];
+};
+
+enum {
+ SLOT_STATUS,
+ VOLTAGE,
+ TIME_REMAINING,
+ CURRENT,
+ AVERAGE_CURRENT,
+ AVERAGING_TIME_INTERVAL,
+ CAPACITY_REMAINING,
+ LAST_FULL_CHARGE_CAPACITY,
+ DESIGN_CAPACITY,
+ CRITICAL_CAPACITY,
+ TEMPERATURE,
+ MANUFACTURER,
+ MODEL,
+ TYPE,
+};
+
+enum {
+ AC,
+ BAT,
+};
+
+struct bat_response {
+ u8 event_type;
+ u8 length;
+ u8 sub_type;
+ u8 status;
+ union { /* payload */
+ char plc[30];
+ u16 plu;
+ s16 pls;
+ };
+};
+
+static struct power_supply nvec_bat_psy;
+static struct power_supply nvec_psy;
+
+static int nvec_power_notifier(struct notifier_block *nb,
+ unsigned long event_type, void *data)
+{
+ struct nvec_power *power = container_of(nb, struct nvec_power, notifier);
+ struct bat_response *res = (struct bat_response *)data;
+
+ if (event_type != NVEC_SYS)
+ return NOTIFY_DONE;
+
+ if(res->sub_type == 0)
+ {
+ if (power->on != res->plu)
+ {
+ power->on = res->plu;
+ power_supply_changed(&nvec_psy);
+ }
+ return NOTIFY_STOP;
+ }
+ return NOTIFY_OK;
+}
+
+static const int bat_init[] =
+{
+ LAST_FULL_CHARGE_CAPACITY, DESIGN_CAPACITY, CRITICAL_CAPACITY,
+ MANUFACTURER, MODEL, TYPE,
+};
+
+static void get_bat_mfg_data(struct nvec_power *power)
+{
+ int i;
+ char buf[] = { '\x02', '\x00' };
+
+ for (i = 0; i < ARRAY_SIZE(bat_init); i++)
+ {
+ buf[1] = bat_init[i];
+ nvec_write_async(power->nvec, buf, 2);
+ }
+}
+
+static int nvec_power_bat_notifier(struct notifier_block *nb,
+ unsigned long event_type, void *data)
+{
+ struct nvec_power *power = container_of(nb, struct nvec_power, notifier);
+ struct bat_response *res = (struct bat_response *)data;
+ int status_changed = 0;
+
+ if (event_type != NVEC_BAT)
+ return NOTIFY_DONE;
+
+ switch(res->sub_type)
+ {
+ case SLOT_STATUS:
+ if (res->plc[0] & 1)
+ {
+ if (power->bat_present == 0)
+ {
+ status_changed = 1;
+ get_bat_mfg_data(power);
+ }
+
+ power->bat_present = 1;
+
+ switch ((res->plc[0] >> 1) & 3)
+ {
+ case 0:
+ power->bat_status = POWER_SUPPLY_STATUS_NOT_CHARGING;
+ break;
+ case 1:
+ power->bat_status = POWER_SUPPLY_STATUS_CHARGING;
+ break;
+ case 2:
+ power->bat_status = POWER_SUPPLY_STATUS_DISCHARGING;
+ break;
+ default:
+ power->bat_status = POWER_SUPPLY_STATUS_UNKNOWN;
+ }
+ } else {
+ if (power->bat_present == 1)
+ status_changed = 1;
+
+ power->bat_present = 0;
+ power->bat_status = POWER_SUPPLY_STATUS_UNKNOWN;
+ }
+ power->bat_cap = res->plc[1];
+ if (status_changed)
+ power_supply_changed(&nvec_bat_psy);
+ break;
+ case VOLTAGE:
+ power->bat_voltage_now = res->plu * 1000;
+ break;
+ case TIME_REMAINING:
+ power->time_remain = res->plu * 3600;
+ break;
+ case CURRENT:
+ power->bat_current_now = res->pls * 1000;
+ break;
+ case AVERAGE_CURRENT:
+ power->bat_current_avg = res->pls * 1000;
+ break;
+ case CAPACITY_REMAINING:
+ power->capacity_remain = res->plu * 1000;
+ break;
+ case LAST_FULL_CHARGE_CAPACITY:
+ power->charge_last_full = res->plu * 1000;
+ break;
+ case DESIGN_CAPACITY:
+ power->charge_full_design = res->plu * 1000;
+ break;
+ case CRITICAL_CAPACITY:
+ power->critical_capacity = res->plu * 1000;
+ break;
+ case TEMPERATURE:
+ power->bat_temperature = res->plu - 2732;
+ break;
+ case MANUFACTURER:
+ memcpy(power->bat_manu, &res->plc, res->length-2);
+ power->bat_model[res->length-2] = '\0';
+ break;
+ case MODEL:
+ memcpy(power->bat_model, &res->plc, res->length-2);
+ power->bat_model[res->length-2] = '\0';
+ break;
+ case TYPE:
+ memcpy(power->bat_type, &res->plc, res->length-2);
+ power->bat_type[res->length-2] = '\0';
+ /* this differs a little from the spec
+ fill in more if you find some */
+ if (!strncmp(power->bat_type, "Li", 30))
+ power->bat_type_enum = POWER_SUPPLY_TECHNOLOGY_LION;
+ else
+ power->bat_type_enum = POWER_SUPPLY_TECHNOLOGY_UNKNOWN;
+ break;
+ default:
+ return NOTIFY_STOP;
+ }
+
+ return NOTIFY_STOP;
+}
+
+static int nvec_power_get_property(struct power_supply *psy,
+ enum power_supply_property psp,
+ union power_supply_propval *val)
+{
+ struct nvec_power *power = dev_get_drvdata(psy->dev->parent);
+ switch (psp) {
+ case POWER_SUPPLY_PROP_ONLINE:
+ val->intval = power->on;
+ break;
+ default:
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static int nvec_battery_get_property(struct power_supply *psy,
+ enum power_supply_property psp,
+ union power_supply_propval *val)
+{
+ struct nvec_power *power = dev_get_drvdata(psy->dev->parent);
+
+ switch(psp)
+ {
+ case POWER_SUPPLY_PROP_STATUS:
+ val->intval = power->bat_status;
+ break;
+ case POWER_SUPPLY_PROP_CAPACITY:
+ val->intval = power->bat_cap;
+ break;
+ case POWER_SUPPLY_PROP_PRESENT:
+ val->intval = power->bat_present;
+ break;
+ case POWER_SUPPLY_PROP_VOLTAGE_NOW:
+ val->intval = power->bat_voltage_now;
+ break;
+ case POWER_SUPPLY_PROP_CURRENT_NOW:
+ val->intval = power->bat_current_now;
+ break;
+ case POWER_SUPPLY_PROP_CURRENT_AVG:
+ val->intval = power->bat_current_avg;
+ break;
+ case POWER_SUPPLY_PROP_TIME_TO_EMPTY_NOW:
+ val->intval = power->time_remain;
+ break;
+ case POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN:
+ val->intval = power->charge_full_design;
+ break;
+ case POWER_SUPPLY_PROP_CHARGE_FULL:
+ val->intval = power->charge_last_full;
+ break;
+ case POWER_SUPPLY_PROP_CHARGE_EMPTY:
+ val->intval = power->critical_capacity;
+ break;
+ case POWER_SUPPLY_PROP_CHARGE_NOW:
+ val->intval = power->capacity_remain;
+ break;
+ case POWER_SUPPLY_PROP_TEMP:
+ val->intval = power->bat_temperature;
+ break;
+ case POWER_SUPPLY_PROP_MANUFACTURER:
+ val->strval = power->bat_manu;
+ break;
+ case POWER_SUPPLY_PROP_MODEL_NAME:
+ val->strval = power->bat_model;
+ break;
+ case POWER_SUPPLY_PROP_TECHNOLOGY:
+ val->intval = power->bat_type_enum;
+ break;
+ default:
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static enum power_supply_property nvec_power_props[] = {
+ POWER_SUPPLY_PROP_ONLINE,
+};
+
+static enum power_supply_property nvec_battery_props[] = {
+ POWER_SUPPLY_PROP_STATUS,
+ POWER_SUPPLY_PROP_PRESENT,
+ POWER_SUPPLY_PROP_CAPACITY,
+ POWER_SUPPLY_PROP_VOLTAGE_NOW,
+ POWER_SUPPLY_PROP_CURRENT_NOW,
+#ifdef EC_FULL_DIAG
+ POWER_SUPPLY_PROP_CURRENT_AVG,
+ POWER_SUPPLY_PROP_TEMP,
+ POWER_SUPPLY_PROP_TIME_TO_EMPTY_NOW,
+#endif
+ POWER_SUPPLY_PROP_CHARGE_FULL_DESIGN,
+ POWER_SUPPLY_PROP_CHARGE_FULL,
+ POWER_SUPPLY_PROP_CHARGE_EMPTY,
+ POWER_SUPPLY_PROP_CHARGE_NOW,
+ POWER_SUPPLY_PROP_MANUFACTURER,
+ POWER_SUPPLY_PROP_MODEL_NAME,
+ POWER_SUPPLY_PROP_TECHNOLOGY,
+};
+
+static char *nvec_power_supplied_to[] = {
+ "battery",
+};
+
+static struct power_supply nvec_bat_psy = {
+ .name = "battery",
+ .type = POWER_SUPPLY_TYPE_BATTERY,
+ .properties = nvec_battery_props,
+ .num_properties = ARRAY_SIZE(nvec_battery_props),
+ .get_property = nvec_battery_get_property,
+};
+
+static struct power_supply nvec_psy = {
+ .name = "ac",
+ .type = POWER_SUPPLY_TYPE_MAINS,
+ .supplied_to = nvec_power_supplied_to,
+ .num_supplicants = ARRAY_SIZE(nvec_power_supplied_to),
+ .properties = nvec_power_props,
+ .num_properties = ARRAY_SIZE(nvec_power_props),
+ .get_property = nvec_power_get_property,
+};
+
+static int counter = 0;
+static int const bat_iter[] =
+{
+ SLOT_STATUS, VOLTAGE, CURRENT, CAPACITY_REMAINING,
+#ifdef EC_FULL_DIAG
+ AVERAGE_CURRENT, TEMPERATURE, TIME_REMAINING,
+#endif
+};
+
+static void nvec_power_poll(struct work_struct *work)
+{
+ char buf[] = { '\x01', '\x00' };
+ struct nvec_power *power = container_of(work, struct nvec_power,
+ poller.work);
+
+ if (counter >= ARRAY_SIZE(bat_iter))
+ counter = 0;
+
+/* AC status via sys req */
+ nvec_write_async(power->nvec, buf, 2);
+ msleep(100);
+
+/* select a battery request function via round robin
+ doing it all at once seems to overload the power supply */
+ buf[0] = '\x02'; /* battery */
+ buf[1] = bat_iter[counter++];
+ nvec_write_async(power->nvec, buf, 2);
+
+// printk("%02x %02x\n", buf[0], buf[1]);
+
+ schedule_delayed_work(to_delayed_work(work), msecs_to_jiffies(5000));
+};
+
+static int __devinit nvec_power_probe(struct platform_device *pdev)
+{
+ struct power_supply *psy;
+ struct nvec_power *power = kzalloc(sizeof(struct nvec_power), GFP_NOWAIT);
+ struct nvec_chip *nvec = dev_get_drvdata(pdev->dev.parent);
+
+ dev_set_drvdata(&pdev->dev, power);
+ power->nvec = nvec;
+
+ switch (pdev->id) {
+ case AC:
+ psy = &nvec_psy;
+
+ power->notifier.notifier_call = nvec_power_notifier;
+
+ INIT_DELAYED_WORK(&power->poller, nvec_power_poll);
+ schedule_delayed_work(&power->poller, msecs_to_jiffies(5000));
+ break;
+ case BAT:
+ psy = &nvec_bat_psy;
+
+ power->notifier.notifier_call = nvec_power_bat_notifier;
+ break;
+ default:
+ kfree(power);
+ return -ENODEV;
+ }
+
+ nvec_register_notifier(nvec, &power->notifier, NVEC_SYS);
+
+ if (pdev->id == BAT)
+ get_bat_mfg_data(power);
+
+ return power_supply_register(&pdev->dev, psy);
+}
+
+static struct platform_driver nvec_power_driver = {
+ .probe = nvec_power_probe,
+// .remove = __devexit_p(nvec_power_remove),
+ .driver = {
+ .name = "nvec-power",
+ .owner = THIS_MODULE,
+ }
+};
+
+static int __init nvec_power_init(void)
+{
+ return platform_driver_register(&nvec_power_driver);
+}
+
+module_init(nvec_power_init);
+
+MODULE_AUTHOR("Ilya Petrov <ilya.muromec@gmail.com>");
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("NVEC battery and AC driver");
+MODULE_ALIAS("platform:nvec-power");
diff --git a/drivers/staging/nvec/nvec_ps2.c b/drivers/staging/nvec/nvec_ps2.c
new file mode 100644
index 0000000..6bb9430
--- /dev/null
+++ b/drivers/staging/nvec/nvec_ps2.c
@@ -0,0 +1,103 @@
+#include <linux/slab.h>
+#include <linux/serio.h>
+#include <linux/delay.h>
+#include "nvec.h"
+
+#define START_STREAMING {'\x06','\x03','\x01'}
+#define STOP_STREAMING {'\x06','\x04'}
+#define SEND_COMMAND {'\x06','\x01','\xf4','\x01'}
+
+struct nvec_ps2
+{
+ struct serio *ser_dev;
+ struct notifier_block notifier;
+ struct nvec_chip *nvec;
+};
+
+static struct nvec_ps2 ps2_dev;
+
+static int ps2_startstreaming(struct serio *ser_dev)
+{
+ unsigned char buf[] = START_STREAMING;
+ nvec_write_async(ps2_dev.nvec, buf, sizeof(buf));
+ return 0;
+}
+
+static void ps2_stopstreaming(struct serio *ser_dev)
+{
+ unsigned char buf[] = STOP_STREAMING;
+ nvec_write_async(ps2_dev.nvec, buf, sizeof(buf));
+}
+
+/* is this really needed?
+static void nvec_resp_handler(unsigned char *data) {
+ serio_interrupt(ser_dev, data[4], 0);
+}
+*/
+
+static int ps2_sendcommand(struct serio *ser_dev, unsigned char cmd)
+{
+ unsigned char buf[] = SEND_COMMAND;
+
+ buf[2] = cmd & 0xff;
+
+ dev_dbg(&ser_dev->dev, "Sending ps2 cmd %02x\n", cmd);
+ nvec_write_async(ps2_dev.nvec, buf, sizeof(buf));
+
+ return 0;
+}
+
+static int nvec_ps2_notifier(struct notifier_block *nb,
+ unsigned long event_type, void *data)
+{
+ int i;
+ unsigned char *msg = (unsigned char *)data;
+
+ switch (event_type) {
+ case NVEC_PS2_EVT:
+ serio_interrupt(ps2_dev.ser_dev, msg[2], 0);
+ return NOTIFY_STOP;
+
+ case NVEC_PS2:
+ if (msg[2] == 1)
+ for(i = 0; i < (msg[1] - 2); i++)
+ serio_interrupt(ps2_dev.ser_dev, msg[i+4], 0);
+ else if (msg[1] != 2) /* !ack */
+ {
+ printk("nvec_ps2: unhandled mouse event ");
+ for(i = 0; i <= (msg[1]+1); i++)
+ printk("%02x ", msg[i]);
+ printk(".\n");
+ }
+
+ return NOTIFY_STOP;
+ }
+
+ return NOTIFY_DONE;
+}
+
+
+int __init nvec_ps2(struct nvec_chip *nvec)
+{
+ struct serio *ser_dev = kzalloc(sizeof(struct serio), GFP_KERNEL);
+
+ ser_dev->id.type=SERIO_8042;
+ ser_dev->write=ps2_sendcommand;
+ ser_dev->open=ps2_startstreaming;
+ ser_dev->close=ps2_stopstreaming;
+
+ strlcpy(ser_dev->name, "NVEC PS2", sizeof(ser_dev->name));
+ strlcpy(ser_dev->phys, "NVEC I2C slave", sizeof(ser_dev->phys));
+
+ ps2_dev.ser_dev = ser_dev;
+ ps2_dev.notifier.notifier_call = nvec_ps2_notifier;
+ ps2_dev.nvec = nvec;
+ nvec_register_notifier(nvec, &ps2_dev.notifier, 0);
+
+ serio_register_port(ser_dev);
+
+ /* mouse reset */
+ nvec_write_async(nvec, "\x06\x01\xff\x03", 4);
+
+ return 0;
+}
diff --git a/drivers/staging/octeon/ethernet-mdio.c b/drivers/staging/octeon/ethernet-mdio.c
index 10a82ef..8a11ffc 100644
--- a/drivers/staging/octeon/ethernet-mdio.c
+++ b/drivers/staging/octeon/ethernet-mdio.c
@@ -91,8 +91,6 @@
.set_settings = cvm_oct_set_settings,
.nway_reset = cvm_oct_nway_reset,
.get_link = ethtool_op_get_link,
- .get_sg = ethtool_op_get_sg,
- .get_tx_csum = ethtool_op_get_tx_csum,
};
/**
diff --git a/drivers/staging/olpc_dcon/olpc_dcon_xo_1.c b/drivers/staging/olpc_dcon/olpc_dcon_xo_1.c
index 22c04ea..2245213 100644
--- a/drivers/staging/olpc_dcon/olpc_dcon_xo_1.c
+++ b/drivers/staging/olpc_dcon/olpc_dcon_xo_1.c
@@ -153,7 +153,7 @@
* According to the cs5536 spec, to set GPIO14 to SMB_CLK we must
* simultaneously set AUX1 IN/OUT to GPIO14; ditto for SMB_DATA and
* GPIO15.
- */
+ */
cs5535_gpio_set(OLPC_GPIO_SMB_CLK, GPIO_OUTPUT_VAL);
cs5535_gpio_set(OLPC_GPIO_SMB_DATA, GPIO_OUTPUT_VAL);
cs5535_gpio_set(OLPC_GPIO_SMB_CLK, GPIO_OUTPUT_ENABLE);
diff --git a/drivers/staging/olpc_dcon/olpc_dcon_xo_1_5.c b/drivers/staging/olpc_dcon/olpc_dcon_xo_1_5.c
index 7aa9b1a..a6a6cf2 100644
--- a/drivers/staging/olpc_dcon/olpc_dcon_xo_1_5.c
+++ b/drivers/staging/olpc_dcon/olpc_dcon_xo_1_5.c
@@ -24,9 +24,8 @@
#include "olpc_dcon.h"
/* Hardware setup on the XO 1.5:
- * DCONLOAD connects to
- * VX855_GPIO1 (not SMBCK2)
- * DCONBLANK connects to VX855_GPIO8 (not SSPICLK) unused in driver
+ * DCONLOAD connects to VX855_GPIO1 (not SMBCK2)
+ * DCONBLANK connects to VX855_GPIO8 (not SSPICLK) unused in driver
* DCONSTAT0 connects to VX855_GPI10 (not SSPISDI)
* DCONSTAT1 connects to VX855_GPI11 (not nSSPISS)
* DCONIRQ connects to VX855_GPIO12
@@ -34,9 +33,9 @@
* DCONSMBCLK connects to VX855 graphics CRTSPCLK
*/
-#define VX855_GENL_PURPOSE_OUTPUT 0x44c // PMIO_Rx4c-4f
-#define VX855_GPI_STATUS_CHG 0x450 // PMIO_Rx50
-#define VX855_GPI_SCI_SMI 0x452 // PMIO_Rx52
+#define VX855_GENL_PURPOSE_OUTPUT 0x44c /* PMIO_Rx4c-4f */
+#define VX855_GPI_STATUS_CHG 0x450 /* PMIO_Rx50 */
+#define VX855_GPI_SCI_SMI 0x452 /* PMIO_Rx52 */
#define BIT_GPIO12 0x40
#define PREFIX "OLPC DCON:"
@@ -63,8 +62,7 @@
unsigned int irq;
u_int8_t tmp;
struct pci_dev *pdev;
-
-
+
pdev = pci_get_device(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VX855, NULL);
if (!pdev) {
@@ -149,7 +147,7 @@
* state machine to reset to a (sane) initial state. Mitch Bradley
* did some testing and discovered that holding for 16 SMB_CLK cycles
* worked a lot more reliably, so that's what we do here.
- */
+ */
set_i2c_line(1, 1);
for (x = 0; x < 16; x++) {
@@ -172,13 +170,13 @@
static u8 dcon_read_status_xo_1_5(void)
{
u8 status;
-
+
if (!dcon_was_irq())
return -1;
- // i believe this is the same as "inb(0x44b) & 3"
+ /* i believe this is the same as "inb(0x44b) & 3" */
status = gpio_get_value(VX855_GPI(10));
- status |= gpio_get_value(VX855_GPI(11)) << 1;
+ status |= gpio_get_value(VX855_GPI(11)) << 1;
dcon_clear_irq();
diff --git a/drivers/staging/rt2860/Kconfig b/drivers/staging/rt2860/Kconfig
deleted file mode 100644
index f3a7e47..0000000
--- a/drivers/staging/rt2860/Kconfig
+++ /dev/null
@@ -1,10 +0,0 @@
-config RT2860
- tristate "Ralink 2860/3090 wireless support"
- depends on PCI && X86 && WLAN
- select WIRELESS_EXT
- select WEXT_PRIV
- select CRC_CCITT
- select FW_LOADER
- ---help---
- This is an experimental driver for the Ralink 2860 and 3090
- wireless chips.
diff --git a/drivers/staging/rt2860/Makefile b/drivers/staging/rt2860/Makefile
deleted file mode 100644
index 6dd0aa5..0000000
--- a/drivers/staging/rt2860/Makefile
+++ /dev/null
@@ -1,52 +0,0 @@
-obj-$(CONFIG_RT2860) += rt2860sta.o
-
-# TODO: all of these should be removed
-ccflags-y := -DLINUX -DAGGREGATION_SUPPORT -DPIGGYBACK_SUPPORT -DWMM_SUPPORT
-ccflags-y += -DRTMP_MAC_PCI -DRTMP_PCI_SUPPORT -DRT2860
-ccflags-y += -DRTMP_RF_RW_SUPPORT -DRTMP_EFUSE_SUPPORT -DRT30xx -DRT3090
-ccflags-y += -DDBG
-
-rt2860sta-y := \
- common/crypt_md5.o \
- common/crypt_sha2.o \
- common/crypt_hmac.o \
- common/mlme.o \
- common/cmm_wep.o \
- common/action.o \
- common/cmm_data.o \
- common/rtmp_init.o \
- common/cmm_tkip.o \
- common/cmm_aes.o \
- common/cmm_sync.o \
- common/eeprom.o \
- common/cmm_sanity.o \
- common/cmm_info.o \
- common/cmm_cfg.o \
- common/cmm_wpa.o \
- common/dfs.o \
- common/spectrum.o \
- common/rtmp_timer.o \
- common/rt_channel.o \
- common/cmm_asic.o \
- sta/assoc.o \
- sta/auth.o \
- sta/auth_rsp.o \
- sta/sync.o \
- sta/sanity.o \
- sta/rtmp_data.o \
- sta/connect.o \
- sta/wpa.o \
- rt_linux.o \
- rt_main_dev.o \
- sta_ioctl.o \
- common/ba_action.o \
- pci_main_dev.o \
- rt_pci_rbus.o \
- common/cmm_mac_pci.o \
- common/cmm_data_pci.o \
- common/ee_prom.o \
- common/rtmp_mcu.o \
- common/ee_efuse.o \
- chips/rt30xx.o \
- common/rt_rf.o \
- chips/rt3090.o
diff --git a/drivers/staging/rt2860/TODO b/drivers/staging/rt2860/TODO
deleted file mode 100644
index 8e2f6ee..0000000
--- a/drivers/staging/rt2860/TODO
+++ /dev/null
@@ -1,16 +0,0 @@
-I'm hesitant to add a TODO file here, as the wireless developers would
-really have people help them out on the "clean" rt2860 driver that can
-be found at the http://rt2x00.serialmonkey.com/ site.
-
-But, if you wish to clean up this driver instead, here's a short list of
-things that need to be done to get it into a more mergable shape:
-
-TODO:
- - checkpatch.pl clean
- - sparse clean
- - port to in-kernel 80211 stack and common rt2x00 infrastructure
- - review by the wireless developer community
-
-Please send any patches or complaints about this driver to Greg
-Kroah-Hartman <greg@kroah.com> and don't bother the upstream wireless
-kernel developers about it, they want nothing to do with it.
diff --git a/drivers/staging/rt2860/ap.h b/drivers/staging/rt2860/ap.h
deleted file mode 100644
index 2737c0c..0000000
--- a/drivers/staging/rt2860/ap.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
-Module Name:
-ap.h
-
-Abstract:
-Miniport generic portion header file
-
-Revision History:
-Who When What
--------- ---------- ----------------------------------------------
-Paul Lin 08-01-2002 created
-James Tan 09-06-2002 modified (Revise NTCRegTable)
-John Chang 12-22-2004 modified for RT2561/2661. merge with STA driver
-*/
-#ifndef __AP_H__
-#define __AP_H__
-
-/* ap_wpa.c */
-void WpaStateMachineInit(struct rt_rtmp_adapter *pAd,
- struct rt_state_machine *Sm,
- OUT STATE_MACHINE_FUNC Trans[]);
-
-#ifdef RTMP_MAC_USB
-void BeaconUpdateExec(void *SystemSpecific1,
- void *FunctionContext,
- void *SystemSpecific2, void *SystemSpecific3);
-#endif /* RTMP_MAC_USB // */
-
-void RTMPSetPiggyBack(struct rt_rtmp_adapter *pAd, IN BOOLEAN bPiggyBack);
-
-void MacTableReset(struct rt_rtmp_adapter *pAd);
-
-struct rt_mac_table_entry *MacTableInsertEntry(struct rt_rtmp_adapter *pAd,
- u8 *pAddr,
- u8 apidx, IN BOOLEAN CleanAll);
-
-BOOLEAN MacTableDeleteEntry(struct rt_rtmp_adapter *pAd,
- u16 wcid, u8 *pAddr);
-
-struct rt_mac_table_entry *MacTableLookup(struct rt_rtmp_adapter *pAd,
- u8 *pAddr);
-
-#endif /* __AP_H__ */
diff --git a/drivers/staging/rt2860/chip/mac_pci.h b/drivers/staging/rt2860/chip/mac_pci.h
deleted file mode 100644
index b8868a5..0000000
--- a/drivers/staging/rt2860/chip/mac_pci.h
+++ /dev/null
@@ -1,355 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- mac_pci.h
-
- Abstract:
-
- Revision History:
- Who When What
- Justin P. Mattock 11/07/2010 Fix some typos
- --------- ---------- ----------------------------------------------
- */
-
-#ifndef __MAC_PCI_H__
-#define __MAC_PCI_H__
-
-#include "../rtmp_type.h"
-#include "rtmp_mac.h"
-#include "rtmp_phy.h"
-#include "../rtmp_iface.h"
-#include "../rtmp_dot11.h"
-
-/* */
-/* Device ID & Vendor ID related definitions, */
-/* NOTE: you should not add the new VendorID/DeviceID here unless you know for sure what chip it belongs too. */
-/* */
-#define NIC_PCI_VENDOR_ID 0x1814
-#define PCIBUS_INTEL_VENDOR 0x8086
-
-#if !defined(PCI_CAP_ID_EXP)
-#define PCI_CAP_ID_EXP 0x10
-#endif
-#if !defined(PCI_EXP_LNKCTL)
-#define PCI_EXP_LNKCTL 0x10
-#endif
-#if !defined(PCI_CLASS_BRIDGE_PCI)
-#define PCI_CLASS_BRIDGE_PCI 0x0604
-#endif
-
-#define TXINFO_SIZE 0
-#define RTMP_PKT_TAIL_PADDING 0
-#define fRTMP_ADAPTER_NEED_STOP_TX 0
-
-#define AUX_CTRL 0x10c
-
-/* */
-/* TX descriptor format, Tx ring, Mgmt Ring */
-/* */
-struct PACKED rt_txd {
- /* Word 0 */
- u32 SDPtr0;
- /* Word 1 */
- u32 SDLen1:14;
- u32 LastSec1:1;
- u32 Burst:1;
- u32 SDLen0:14;
- u32 LastSec0:1;
- u32 DMADONE:1;
- /*Word2 */
- u32 SDPtr1;
- /*Word3 */
- u32 rsv2:24;
- u32 WIV:1; /* Wireless Info Valid. 1 if Driver already fill WI, o if DMA needs to copy WI to correct position */
- u32 QSEL:2; /* select on-chip FIFO ID for 2nd-stage output scheduler.0:MGMT, 1:HCCA 2:EDCA */
- u32 rsv:2;
- u32 TCO:1; /* */
- u32 UCO:1; /* */
- u32 ICO:1; /* */
-};
-
-/* */
-/* Rx descriptor format, Rx Ring */
-/* */
-typedef struct PACKED rt_rxd {
- /* Word 0 */
- u32 SDP0;
- /* Word 1 */
- u32 SDL1:14;
- u32 Rsv:2;
- u32 SDL0:14;
- u32 LS0:1;
- u32 DDONE:1;
- /* Word 2 */
- u32 SDP1;
- /* Word 3 */
- u32 BA:1;
- u32 DATA:1;
- u32 NULLDATA:1;
- u32 FRAG:1;
- u32 U2M:1; /* 1: this RX frame is unicast to me */
- u32 Mcast:1; /* 1: this is a multicast frame */
- u32 Bcast:1; /* 1: this is a broadcast frame */
- u32 MyBss:1; /* 1: this frame belongs to the same BSSID */
- u32 Crc:1; /* 1: CRC error */
- u32 CipherErr:2; /* 0: decryption okay, 1:ICV error, 2:MIC error, 3:KEY not valid */
- u32 AMSDU:1; /* rx with 802.3 header, not 802.11 header. */
- u32 HTC:1;
- u32 RSSI:1;
- u32 L2PAD:1;
- u32 AMPDU:1;
- u32 Decrypted:1; /* this frame is being decrypted. */
- u32 PlcpSignal:1; /* To be moved */
- u32 PlcpRssil:1; /* To be moved */
- u32 Rsv1:13;
-} RT28XX_RXD_STRUC, *PRT28XX_RXD_STRUC;
-
-typedef union _TX_ATTENUATION_CTRL_STRUC {
- struct {
- unsigned long RF_ISOLATION_ENABLE:1;
- unsigned long Reserve2:7;
- unsigned long PCIE_PHY_TX_ATTEN_VALUE:3;
- unsigned long PCIE_PHY_TX_ATTEN_EN:1;
- unsigned long Reserve1:20;
- } field;
-
- unsigned long word;
-} TX_ATTENUATION_CTRL_STRUC, *PTX_ATTENUATION_CTRL_STRUC;
-
-/* ----------------- EEPROM Related MACRO ----------------- */
-
-/* 8051 firmware image for RT2860 - base address = 0x4000 */
-#define FIRMWARE_IMAGE_BASE 0x2000
-#define MAX_FIRMWARE_IMAGE_SIZE 0x2000 /* 8kbyte */
-
-/* ----------------- Frimware Related MACRO ----------------- */
-#define RTMP_WRITE_FIRMWARE(_pAd, _pFwImage, _FwLen) \
- do { \
- unsigned long _i, _firm; \
- RTMP_IO_WRITE32(_pAd, PBF_SYS_CTRL, 0x10000); \
- \
- for (_i = 0; _i < _FwLen; _i += 4) { \
- _firm = _pFwImage[_i] + \
- (_pFwImage[_i+3] << 24) + \
- (_pFwImage[_i+2] << 16) + \
- (_pFwImage[_i+1] << 8); \
- RTMP_IO_WRITE32(_pAd, FIRMWARE_IMAGE_BASE + _i, _firm); \
- } \
- RTMP_IO_WRITE32(_pAd, PBF_SYS_CTRL, 0x00000); \
- RTMP_IO_WRITE32(_pAd, PBF_SYS_CTRL, 0x00001); \
- \
- /* initialize BBP R/W access agent */ \
- RTMP_IO_WRITE32(_pAd, H2M_BBP_AGENT, 0); \
- RTMP_IO_WRITE32(_pAd, H2M_MAILBOX_CSR, 0); \
- } while (0)
-
-/* ----------------- TX Related MACRO ----------------- */
-#define RTMP_START_DEQUEUE(pAd, QueIdx, irqFlags) do {} while (0)
-#define RTMP_STOP_DEQUEUE(pAd, QueIdx, irqFlags) do {} while (0)
-
-#define RTMP_HAS_ENOUGH_FREE_DESC(pAd, pTxBlk, freeNum, pPacket) \
- ((freeNum) >= (unsigned long)(pTxBlk->TotalFragNum + RTMP_GET_PACKET_FRAGMENTS(pPacket) + 3)) /* rough estimate we will use 3 more descriptor. */
-#define RTMP_RELEASE_DESC_RESOURCE(pAd, QueIdx) do {} while (0)
-
-#define NEED_QUEUE_BACK_FOR_AGG(pAd, QueIdx, freeNum, _TxFrameType) \
- (((freeNum != (TX_RING_SIZE-1)) && \
- (pAd->TxSwQueue[QueIdx].Number == 0)) || (freeNum < 3))
-
-#define HAL_KickOutMgmtTx(_pAd, _QueIdx, _pPacket, _pSrcBufVA, _SrcBufLen) \
- RtmpPCIMgmtKickOut(_pAd, _QueIdx, _pPacket, _pSrcBufVA, _SrcBufLen)
-
-#define HAL_WriteSubTxResource(pAd, pTxBlk, bIsLast, pFreeNumber) \
- /* RtmpPCI_WriteSubTxResource(pAd, pTxBlk, bIsLast, pFreeNumber) */
-
-#define HAL_WriteTxResource(pAd, pTxBlk, bIsLast, pFreeNumber) \
- RtmpPCI_WriteSingleTxResource(pAd, pTxBlk, bIsLast, pFreeNumber)
-
-#define HAL_WriteFragTxResource(pAd, pTxBlk, fragNum, pFreeNumber) \
- RtmpPCI_WriteFragTxResource(pAd, pTxBlk, fragNum, pFreeNumber)
-
-#define HAL_WriteMultiTxResource(pAd, pTxBlk, frameNum, pFreeNumber) \
- RtmpPCI_WriteMultiTxResource(pAd, pTxBlk, frameNum, pFreeNumber)
-
-#define HAL_FinalWriteTxResource(_pAd, _pTxBlk, _TotalMPDUSize, _FirstTxIdx) \
- RtmpPCI_FinalWriteTxResource(_pAd, _pTxBlk, _TotalMPDUSize, _FirstTxIdx)
-
-#define HAL_LastTxIdx(_pAd, _QueIdx, _LastTxIdx) \
- /*RtmpPCIDataLastTxIdx(_pAd, _QueIdx,_LastTxIdx) */
-
-#define HAL_KickOutTx(_pAd, _pTxBlk, _QueIdx) \
- RTMP_IO_WRITE32((_pAd), TX_CTX_IDX0+((_QueIdx)*0x10), (_pAd)->TxRing[(_QueIdx)].TxCpuIdx)
-/* RtmpPCIDataKickOut(_pAd, _pTxBlk, _QueIdx)*/
-
-#define HAL_KickOutNullFrameTx(_pAd, _QueIdx, _pNullFrame, _frameLen) \
- MiniportMMRequest(_pAd, _QueIdx, _pNullFrame, _frameLen)
-
-#define GET_TXRING_FREENO(_pAd, _QueIdx) \
- (_pAd->TxRing[_QueIdx].TxSwFreeIdx > _pAd->TxRing[_QueIdx].TxCpuIdx) ? \
- (_pAd->TxRing[_QueIdx].TxSwFreeIdx - _pAd->TxRing[_QueIdx].TxCpuIdx - 1) \
- : \
- (_pAd->TxRing[_QueIdx].TxSwFreeIdx + TX_RING_SIZE - _pAd->TxRing[_QueIdx].TxCpuIdx - 1);
-
-#define GET_MGMTRING_FREENO(_pAd) \
- (_pAd->MgmtRing.TxSwFreeIdx > _pAd->MgmtRing.TxCpuIdx) ? \
- (_pAd->MgmtRing.TxSwFreeIdx - _pAd->MgmtRing.TxCpuIdx - 1) \
- : \
- (_pAd->MgmtRing.TxSwFreeIdx + MGMT_RING_SIZE - _pAd->MgmtRing.TxCpuIdx - 1);
-
-/* ----------------- RX Related MACRO ----------------- */
-
-/* ----------------- ASIC Related MACRO ----------------- */
-/* reset MAC of a station entry to 0x000000000000 */
-#define RTMP_STA_ENTRY_MAC_RESET(pAd, Wcid) \
- AsicDelWcidTab(pAd, Wcid);
-
-/* add this entry into ASIC RX WCID search table */
-#define RTMP_STA_ENTRY_ADD(pAd, pEntry) \
- AsicUpdateRxWCIDTable(pAd, pEntry->Aid, pEntry->Addr);
-
-/* add by johnli, fix "in_interrupt" error when call "MacTableDeleteEntry" in Rx tasklet */
-/* Set MAC register value according operation mode */
-#define RTMP_UPDATE_PROTECT(pAd) \
- AsicUpdateProtect(pAd, 0, (ALLN_SETPROTECT), TRUE, 0);
-/* end johnli */
-
-/* remove Pair-wise key material from ASIC */
-#define RTMP_STA_ENTRY_KEY_DEL(pAd, BssIdx, Wcid) \
- AsicRemovePairwiseKeyEntry(pAd, BssIdx, (u8)Wcid);
-
-/* add Client security information into ASIC WCID table and IVEIV table */
-#define RTMP_STA_SECURITY_INFO_ADD(pAd, apidx, KeyID, pEntry) \
- RTMPAddWcidAttributeEntry(pAd, apidx, KeyID, \
- pAd->SharedKey[apidx][KeyID].CipherAlg, pEntry);
-
-#define RTMP_SECURITY_KEY_ADD(pAd, apidx, KeyID, pEntry) \
- { /* update pairwise key information to ASIC Shared Key Table */ \
- AsicAddSharedKeyEntry(pAd, apidx, KeyID, \
- pAd->SharedKey[apidx][KeyID].CipherAlg, \
- pAd->SharedKey[apidx][KeyID].Key, \
- pAd->SharedKey[apidx][KeyID].TxMic, \
- pAd->SharedKey[apidx][KeyID].RxMic); \
- /* update ASIC WCID attribute table and IVEIV table */ \
- RTMPAddWcidAttributeEntry(pAd, apidx, KeyID, \
- pAd->SharedKey[apidx][KeyID].CipherAlg, \
- pEntry); }
-
-/* Insert the BA bitmap to ASIC for the Wcid entry */
-#define RTMP_ADD_BA_SESSION_TO_ASIC(_pAd, _Aid, _TID) \
- do { \
- u32 _Value = 0, _Offset; \
- _Offset = MAC_WCID_BASE + (_Aid) * HW_WCID_ENTRY_SIZE + 4; \
- RTMP_IO_READ32((_pAd), _Offset, &_Value);\
- _Value |= (0x10000<<(_TID)); \
- RTMP_IO_WRITE32((_pAd), _Offset, _Value);\
- } while (0)
-
-/* Remove the BA bitmap from ASIC for the Wcid entry */
-/* bitmap field starts at 0x10000 in ASIC WCID table */
-#define RTMP_DEL_BA_SESSION_FROM_ASIC(_pAd, _Wcid, _TID) \
- do { \
- u32 _Value = 0, _Offset; \
- _Offset = MAC_WCID_BASE + (_Wcid) * HW_WCID_ENTRY_SIZE + 4; \
- RTMP_IO_READ32((_pAd), _Offset, &_Value); \
- _Value &= (~(0x10000 << (_TID))); \
- RTMP_IO_WRITE32((_pAd), _Offset, _Value); \
- } while (0)
-
-/* ----------------- Interface Related MACRO ----------------- */
-
-/* */
-/* Enable & Disable NIC interrupt via writing interrupt mask register */
-/* Since it use ADAPTER structure, it have to be put after structure definition. */
-/* */
-#define RTMP_ASIC_INTERRUPT_DISABLE(_pAd) \
- do { \
- RTMP_IO_WRITE32((_pAd), INT_MASK_CSR, 0x0); /* 0: disable */ \
- RTMP_CLEAR_FLAG((_pAd), fRTMP_ADAPTER_INTERRUPT_ACTIVE); \
- } while (0)
-
-#define RTMP_ASIC_INTERRUPT_ENABLE(_pAd)\
- do { \
- RTMP_IO_WRITE32((_pAd), INT_MASK_CSR, (_pAd)->int_enable_reg /*DELAYINTMASK*/); /* 1:enable */ \
- RTMP_SET_FLAG((_pAd), fRTMP_ADAPTER_INTERRUPT_ACTIVE); \
- } while (0)
-
-#define RTMP_IRQ_INIT(pAd) \
- { pAd->int_enable_reg = ((DELAYINTMASK) | \
- (RxINT|TxDataInt|TxMgmtInt)) & ~(0x03); \
- pAd->int_disable_mask = 0; \
- pAd->int_pending = 0; }
-
-#define RTMP_IRQ_ENABLE(pAd) \
- { /* clear garbage ints */ \
- RTMP_IO_WRITE32(pAd, INT_SOURCE_CSR, 0xffffffff);\
- RTMP_ASIC_INTERRUPT_ENABLE(pAd); }
-
-/* ----------------- MLME Related MACRO ----------------- */
-#define RTMP_MLME_HANDLER(pAd) MlmeHandler(pAd)
-
-#define RTMP_MLME_PRE_SANITY_CHECK(pAd)
-
-#define RTMP_MLME_STA_QUICK_RSP_WAKE_UP(pAd) \
- RTMPSetTimer(&pAd->StaCfg.StaQuickResponeForRateUpTimer, 100);
-
-#define RTMP_MLME_RESET_STATE_MACHINE(pAd) \
- MlmeRestartStateMachine(pAd)
-
-#define RTMP_HANDLE_COUNTER_MEASURE(_pAd, _pEntry)\
- HandleCounterMeasure(_pAd, _pEntry)
-
-/* ----------------- Power Save Related MACRO ----------------- */
-#define RTMP_PS_POLL_ENQUEUE(pAd) EnqueuePsPoll(pAd)
-
-/* For RTMPPCIePowerLinkCtrlRestore () function */
-#define RESTORE_HALT 1
-#define RESTORE_WAKEUP 2
-#define RESTORE_CLOSE 3
-
-#define PowerSafeCID 1
-#define PowerRadioOffCID 2
-#define PowerWakeCID 3
-#define CID0MASK 0x000000ff
-#define CID1MASK 0x0000ff00
-#define CID2MASK 0x00ff0000
-#define CID3MASK 0xff000000
-
-#define RTMP_STA_FORCE_WAKEUP(pAd, bFromTx) \
- RT28xxPciStaAsicForceWakeup(pAd, bFromTx);
-
-#define RTMP_STA_SLEEP_THEN_AUTO_WAKEUP(pAd, TbttNumToNextWakeUp) \
- RT28xxPciStaAsicSleepThenAutoWakeup(pAd, TbttNumToNextWakeUp);
-
-#define RTMP_SET_PSM_BIT(_pAd, _val) \
- MlmeSetPsmBit(_pAd, _val);
-
-#define RTMP_MLME_RADIO_ON(pAd) \
- RT28xxPciMlmeRadioOn(pAd);
-
-#define RTMP_MLME_RADIO_OFF(pAd) \
- RT28xxPciMlmeRadioOFF(pAd);
-
-#endif /*__MAC_PCI_H__ // */
diff --git a/drivers/staging/rt2860/chip/mac_usb.h b/drivers/staging/rt2860/chip/mac_usb.h
deleted file mode 100644
index e8158fb..0000000
--- a/drivers/staging/rt2860/chip/mac_usb.h
+++ /dev/null
@@ -1,345 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- mac_usb.h
-
- Abstract:
-
- Revision History:
- Who When What
- Justin P. Mattock 11/07/2010 Fix a typo
- --------- ---------- ----------------------------------------------
- */
-
-#ifndef __MAC_USB_H__
-#define __MAC_USB_H__
-
-#include "../rtmp_type.h"
-#include "rtmp_mac.h"
-#include "rtmp_phy.h"
-#include "../rtmp_iface.h"
-#include "../rtmp_dot11.h"
-
-#define USB_CYC_CFG 0x02a4
-
-#define BEACON_RING_SIZE 2
-#define MGMTPIPEIDX 0 /* EP6 is highest priority */
-
-#define RTMP_PKT_TAIL_PADDING 11 /* 3(max 4 byte padding) + 4 (last packet padding) + 4 (MaxBulkOutsize align padding) */
-
-#define fRTMP_ADAPTER_NEED_STOP_TX \
- (fRTMP_ADAPTER_NIC_NOT_EXIST | fRTMP_ADAPTER_HALT_IN_PROGRESS | \
- fRTMP_ADAPTER_RESET_IN_PROGRESS | fRTMP_ADAPTER_BULKOUT_RESET | \
- fRTMP_ADAPTER_RADIO_OFF | fRTMP_ADAPTER_REMOVE_IN_PROGRESS)
-
-/* */
-/* RXINFO appends at the end of each rx packet. */
-/* */
-#define RXINFO_SIZE 4
-#define RT2870_RXDMALEN_FIELD_SIZE 4
-
-typedef struct PACKED rt_rxinfo {
- u32 BA:1;
- u32 DATA:1;
- u32 NULLDATA:1;
- u32 FRAG:1;
- u32 U2M:1; /* 1: this RX frame is unicast to me */
- u32 Mcast:1; /* 1: this is a multicast frame */
- u32 Bcast:1; /* 1: this is a broadcast frame */
- u32 MyBss:1; /* 1: this frame belongs to the same BSSID */
- u32 Crc:1; /* 1: CRC error */
- u32 CipherErr:2; /* 0: decryption okay, 1:ICV error, 2:MIC error, 3:KEY not valid */
- u32 AMSDU:1; /* rx with 802.3 header, not 802.11 header. */
- u32 HTC:1;
- u32 RSSI:1;
- u32 L2PAD:1;
- u32 AMPDU:1; /* To be moved */
- u32 Decrypted:1;
- u32 PlcpRssil:1;
- u32 CipherAlg:1;
- u32 LastAMSDU:1;
- u32 PlcpSignal:12;
-} RT28XX_RXD_STRUC, *PRT28XX_RXD_STRUC;
-
-/* */
-/* TXINFO */
-/* */
-#define TXINFO_SIZE 4
-
-struct rt_txinfo {
- /* Word 0 */
- u32 USBDMATxPktLen:16; /*used ONLY in USB bulk Aggregation, Total byte counts of all sub-frame. */
- u32 rsv:8;
- u32 WIV:1; /* Wireless Info Valid. 1 if Driver already fill WI, o if DMA needs to copy WI to correct position */
- u32 QSEL:2; /* select on-chip FIFO ID for 2nd-stage output scheduler.0:MGMT, 1:HCCA 2:EDCA */
- u32 SwUseLastRound:1; /* Software use. */
- u32 rsv2:2; /* Software use. */
- u32 USBDMANextVLD:1; /*used ONLY in USB bulk Aggregation, NextValid */
- u32 USBDMATxburst:1; /*used ONLY in USB bulk Aggre. Force USB DMA transmit frame from current selected endpoint */
-};
-
-/* */
-/* Management ring buffer format */
-/* */
-struct rt_mgmt {
- BOOLEAN Valid;
- u8 *pBuffer;
- unsigned long Length;
-};
-
-/*////////////////////////////////////////////////////////////////////////// */
-/* The struct rt_tx_buffer structure forms the transmitted USB packet to the device */
-/*////////////////////////////////////////////////////////////////////////// */
-struct rt_tx_buffer {
- union {
- u8 WirelessPacket[TX_BUFFER_NORMSIZE];
- struct rt_header_802_11 NullFrame;
- struct rt_pspoll_frame PsPollPacket;
- struct rt_rts_frame RTSFrame;
- } field;
- u8 Aggregation[4]; /*Buffer for save Aggregation size. */
-};
-
-struct rt_httx_buffer {
- union {
- u8 WirelessPacket[MAX_TXBULK_SIZE];
- struct rt_header_802_11 NullFrame;
- struct rt_pspoll_frame PsPollPacket;
- struct rt_rts_frame RTSFrame;
- } field;
- u8 Aggregation[4]; /*Buffer for save Aggregation size. */
-};
-
-/* used to track driver-generated write irps */
-struct rt_tx_context {
- void *pAd; /*Initialized in MiniportInitialize */
- PURB pUrb; /*Initialized in MiniportInitialize */
- PIRP pIrp; /*used to cancel pending bulk out. */
- /*Initialized in MiniportInitialize */
- struct rt_tx_buffer *TransferBuffer; /*Initialized in MiniportInitialize */
- unsigned long BulkOutSize;
- u8 BulkOutPipeId;
- u8 SelfIdx;
- BOOLEAN InUse;
- BOOLEAN bWaitingBulkOut; /* at least one packet is in this TxContext, ready for making IRP anytime. */
- BOOLEAN bFullForBulkOut; /* all tx buffer are full , so waiting for tx bulkout. */
- BOOLEAN IRPPending;
- BOOLEAN LastOne;
- BOOLEAN bAggregatible;
- u8 Header_802_3[LENGTH_802_3];
- u8 Rsv[2];
- unsigned long DataOffset;
- u32 TxRate;
- dma_addr_t data_dma; /* urb dma on linux */
-
-};
-
-/* used to track driver-generated write irps */
-struct rt_ht_tx_context {
- void *pAd; /*Initialized in MiniportInitialize */
- PURB pUrb; /*Initialized in MiniportInitialize */
- PIRP pIrp; /*used to cancel pending bulk out. */
- /*Initialized in MiniportInitialize */
- struct rt_httx_buffer *TransferBuffer; /*Initialized in MiniportInitialize */
- unsigned long BulkOutSize; /* Indicate the total bulk-out size in bytes in one bulk-transmission */
- u8 BulkOutPipeId;
- BOOLEAN IRPPending;
- BOOLEAN LastOne;
- BOOLEAN bCurWriting;
- BOOLEAN bRingEmpty;
- BOOLEAN bCopySavePad;
- u8 SavedPad[8];
- u8 Header_802_3[LENGTH_802_3];
- unsigned long CurWritePosition; /* Indicate the buffer offset which packet will be inserted start from. */
- unsigned long CurWriteRealPos; /* Indicate the buffer offset which packet now are writing to. */
- unsigned long NextBulkOutPosition; /* Indicate the buffer start offset of a bulk-transmission */
- unsigned long ENextBulkOutPosition; /* Indicate the buffer end offset of a bulk-transmission */
- u32 TxRate;
- dma_addr_t data_dma; /* urb dma on linux */
-};
-
-/* */
-/* Structure to keep track of receive packets and buffers to indicate */
-/* receive data to the protocol. */
-/* */
-struct rt_rx_context {
- u8 *TransferBuffer;
- void *pAd;
- PIRP pIrp; /*used to cancel pending bulk in. */
- PURB pUrb;
- /*These 2 Boolean shouldn't both be 1 at the same time. */
- unsigned long BulkInOffset; /* number of packets waiting for reordering . */
-/* BOOLEAN ReorderInUse; // At least one packet in this buffer are in reordering buffer and wait for receive indication */
- BOOLEAN bRxHandling; /* Notify this packet is being process now. */
- BOOLEAN InUse; /* USB Hardware Occupied. Wait for USB HW to put packet. */
- BOOLEAN Readable; /* Receive Complete back. OK for driver to indicate receiving packet. */
- BOOLEAN IRPPending; /* TODO: To be removed */
- atomic_t IrpLock;
- spinlock_t RxContextLock;
- dma_addr_t data_dma; /* urb dma on linux */
-};
-
-/******************************************************************************
-
- USB Frimware Related MACRO
-
-******************************************************************************/
-/* 8051 firmware image for usb - use last-half base address = 0x3000 */
-#define FIRMWARE_IMAGE_BASE 0x3000
-#define MAX_FIRMWARE_IMAGE_SIZE 0x1000 /* 4kbyte */
-
-#define RTMP_WRITE_FIRMWARE(_pAd, _pFwImage, _FwLen) \
- RTUSBFirmwareWrite(_pAd, _pFwImage, _FwLen)
-
-/******************************************************************************
-
- USB TX Related MACRO
-
-******************************************************************************/
-#define RTMP_START_DEQUEUE(pAd, QueIdx, irqFlags) \
- do { \
- RTMP_IRQ_LOCK(&pAd->DeQueueLock[QueIdx], irqFlags); \
- if (pAd->DeQueueRunning[QueIdx]) { \
- RTMP_IRQ_UNLOCK(&pAd->DeQueueLock[QueIdx], irqFlags); \
- DBGPRINT(RT_DEBUG_OFF, ("DeQueueRunning[%d]= TRUE!\n", QueIdx)); \
- continue; \
- } else { \
- pAd->DeQueueRunning[QueIdx] = TRUE; \
- RTMP_IRQ_UNLOCK(&pAd->DeQueueLock[QueIdx], irqFlags);\
- } \
- } while (0)
-
-#define RTMP_STOP_DEQUEUE(pAd, QueIdx, irqFlags) \
- do { \
- RTMP_IRQ_LOCK(&pAd->DeQueueLock[QueIdx], irqFlags); \
- pAd->DeQueueRunning[QueIdx] = FALSE; \
- RTMP_IRQ_UNLOCK(&pAd->DeQueueLock[QueIdx], irqFlags); \
- } while (0)
-
-#define RTMP_HAS_ENOUGH_FREE_DESC(pAd, pTxBlk, freeNum, pPacket) \
- (RTUSBFreeDescriptorRequest(pAd, pTxBlk->QueIdx, (pTxBlk->TotalFrameLen + GET_OS_PKT_LEN(pPacket))) == NDIS_STATUS_SUCCESS)
-
-#define RTMP_RELEASE_DESC_RESOURCE(pAd, QueIdx) \
- do {} while (0)
-
-#define NEED_QUEUE_BACK_FOR_AGG(_pAd, _QueIdx, _freeNum, _TxFrameType) \
- ((_TxFrameType == TX_RALINK_FRAME) && \
- (RTUSBNeedQueueBackForAgg(_pAd, _QueIdx)))
-
-#define HAL_WriteSubTxResource(pAd, pTxBlk, bIsLast, pFreeNumber) \
- RtmpUSB_WriteSubTxResource(pAd, pTxBlk, bIsLast, pFreeNumber)
-
-#define HAL_WriteTxResource(pAd, pTxBlk, bIsLast, pFreeNumber) \
- RtmpUSB_WriteSingleTxResource(pAd, pTxBlk, bIsLast, pFreeNumber)
-
-#define HAL_WriteFragTxResource(pAd, pTxBlk, fragNum, pFreeNumber) \
- RtmpUSB_WriteFragTxResource(pAd, pTxBlk, fragNum, pFreeNumber)
-
-#define HAL_WriteMultiTxResource(pAd, pTxBlk, frameNum, pFreeNumber) \
- RtmpUSB_WriteMultiTxResource(pAd, pTxBlk, frameNum, pFreeNumber)
-
-#define HAL_FinalWriteTxResource(pAd, pTxBlk, totalMPDUSize, TxIdx) \
- RtmpUSB_FinalWriteTxResource(pAd, pTxBlk, totalMPDUSize, TxIdx)
-
-#define HAL_LastTxIdx(pAd, QueIdx, TxIdx) \
- /*RtmpUSBDataLastTxIdx(pAd, QueIdx,TxIdx) */
-
-#define HAL_KickOutTx(pAd, pTxBlk, QueIdx) \
- RtmpUSBDataKickOut(pAd, pTxBlk, QueIdx)
-
-#define HAL_KickOutMgmtTx(pAd, QueIdx, pPacket, pSrcBufVA, SrcBufLen) \
- RtmpUSBMgmtKickOut(pAd, QueIdx, pPacket, pSrcBufVA, SrcBufLen)
-
-#define HAL_KickOutNullFrameTx(_pAd, _QueIdx, _pNullFrame, _frameLen) \
- RtmpUSBNullFrameKickOut(_pAd, _QueIdx, _pNullFrame, _frameLen)
-
-#define GET_TXRING_FREENO(_pAd, _QueIdx) (_QueIdx) /*(_pAd->TxRing[_QueIdx].TxSwFreeIdx) */
-#define GET_MGMTRING_FREENO(_pAd) (_pAd->MgmtRing.TxSwFreeIdx)
-
-/* ----------------- RX Related MACRO ----------------- */
-
-/*
- * Device Hardware Interface Related MACRO
- */
-#define RTMP_IRQ_INIT(pAd) do {} while (0)
-#define RTMP_IRQ_ENABLE(pAd) do {} while (0)
-
-/*
- * MLME Related MACRO
- */
-#define RTMP_MLME_HANDLER(pAd) RTUSBMlmeUp(pAd)
-
-#define RTMP_MLME_PRE_SANITY_CHECK(pAd) \
- { if ((pAd->CommonCfg.bHardwareRadio == TRUE) && \
- (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST)) && \
- (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS))) { \
- RTUSBEnqueueInternalCmd(pAd, CMDTHREAD_CHECK_GPIO, NULL, 0); } }
-
-#define RTMP_MLME_STA_QUICK_RSP_WAKE_UP(pAd) \
- { RTUSBEnqueueInternalCmd(pAd, CMDTHREAD_QKERIODIC_EXECUT, NULL, 0); \
- RTUSBMlmeUp(pAd); }
-
-#define RTMP_MLME_RESET_STATE_MACHINE(pAd) \
- { MlmeEnqueue(pAd, MLME_CNTL_STATE_MACHINE, MT2_RESET_CONF, 0, NULL); \
- RTUSBMlmeUp(pAd); }
-
-#define RTMP_HANDLE_COUNTER_MEASURE(_pAd, _pEntry) \
- { RTUSBEnqueueInternalCmd(_pAd, CMDTHREAD_802_11_COUNTER_MEASURE, _pEntry, sizeof(struct rt_mac_table_entry)); \
- RTUSBMlmeUp(_pAd); \
- }
-
-/*
- * Power Save Related MACRO
- */
-#define RTMP_PS_POLL_ENQUEUE(pAd) \
- { RTUSB_SET_BULK_FLAG(pAd, fRTUSB_BULK_OUT_PSPOLL); \
- RTUSBKickBulkOut(pAd); }
-
-#define RTMP_STA_FORCE_WAKEUP(_pAd, bFromTx) \
- RT28xxUsbStaAsicForceWakeup(_pAd, bFromTx);
-
-#define RTMP_STA_SLEEP_THEN_AUTO_WAKEUP(pAd, TbttNumToNextWakeUp) \
- RT28xxUsbStaAsicSleepThenAutoWakeup(pAd, TbttNumToNextWakeUp);
-
-#define RTMP_SET_PSM_BIT(_pAd, _val) \
- {\
- if ((_pAd)->StaCfg.WindowsPowerMode == Ndis802_11PowerModeFast_PSP) \
- MlmeSetPsmBit(_pAd, _val);\
- else { \
- u16 _psm_val; \
- _psm_val = _val; \
- RTUSBEnqueueInternalCmd(_pAd, CMDTHREAD_SET_PSM_BIT, &(_psm_val), sizeof(u16)); \
- } \
- }
-
-#define RTMP_MLME_RADIO_ON(pAd) \
- RT28xxUsbMlmeRadioOn(pAd);
-
-#define RTMP_MLME_RADIO_OFF(pAd) \
- RT28xxUsbMlmeRadioOFF(pAd);
-
-#endif /*__MAC_USB_H__ // */
diff --git a/drivers/staging/rt2860/chip/rt2860.h b/drivers/staging/rt2860/chip/rt2860.h
deleted file mode 100644
index f30b808..0000000
--- a/drivers/staging/rt2860/chip/rt2860.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
- */
-
-#ifndef __RT2860_H__
-#define __RT2860_H__
-
-#include "mac_pci.h"
-
-#ifndef RTMP_PCI_SUPPORT
-#error "For RT2860, you should define the compile flag -DRTMP_PCI_SUPPORT"
-#endif
-
-#ifndef RTMP_MAC_PCI
-#error "For RT2880, you should define the compile flag -DRTMP_MAC_PCI"
-#endif
-
-/* */
-/* Device ID & Vendor ID, these values should match EEPROM value */
-/* */
-#define NIC2860_PCI_DEVICE_ID 0x0601
-#define NIC2860_PCIe_DEVICE_ID 0x0681
-#define NIC2760_PCI_DEVICE_ID 0x0701 /* 1T/2R Cardbus ??? */
-#define NIC2790_PCIe_DEVICE_ID 0x0781 /* 1T/2R miniCard */
-
-#define VEN_AWT_PCIe_DEVICE_ID 0x1059
-#define VEN_AWT_PCI_VENDOR_ID 0x1A3B
-
-#define EDIMAX_PCI_VENDOR_ID 0x1432
-
-#endif /*__RT2860_H__ // */
diff --git a/drivers/staging/rt2860/chip/rt2870.h b/drivers/staging/rt2860/chip/rt2870.h
deleted file mode 100644
index 8263f1b..0000000
--- a/drivers/staging/rt2860/chip/rt2870.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
- */
-#ifndef __RT2870_H__
-#define __RT2870_H__
-
-#ifdef RT2870
-
-#ifndef RTMP_USB_SUPPORT
-#error "For RT2870, you should define the compile flag -DRTMP_USB_SUPPORT"
-#endif
-
-#ifndef RTMP_MAC_USB
-#error "For RT2870, you should define the compile flag -DRTMP_MAC_USB"
-#endif
-
-#include "../rtmp_type.h"
-#include "mac_usb.h"
-
-/*#define RTMP_CHIP_NAME "RT2870" */
-
-#endif /* RT2870 // */
-#endif /*__RT2870_H__ // */
diff --git a/drivers/staging/rt2860/chip/rt3070.h b/drivers/staging/rt2860/chip/rt3070.h
deleted file mode 100644
index 172ce70..0000000
--- a/drivers/staging/rt2860/chip/rt3070.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- rt3070.h
-
- Abstract:
-
- Revision History:
- Who When What
- --------- ---------- ----------------------------------------------
- */
-
-#ifndef __RT3070_H__
-#define __RT3070_H__
-
-#ifdef RT3070
-
-#ifndef RTMP_USB_SUPPORT
-#error "For RT3070, you should define the compile flag -DRTMP_USB_SUPPORT"
-#endif
-
-#ifndef RTMP_MAC_USB
-#error "For RT3070, you should define the compile flag -DRTMP_MAC_USB"
-#endif
-
-#ifndef RTMP_RF_RW_SUPPORT
-#error "For RT3070, you should define the compile flag -DRTMP_RF_RW_SUPPORT"
-#endif
-
-#ifndef RT30xx
-#error "For RT3070, you should define the compile flag -DRT30xx"
-#endif
-
-#include "mac_usb.h"
-#include "rt30xx.h"
-
-/* */
-/* Device ID & Vendor ID, these values should match EEPROM value */
-/* */
-
-#endif /* RT3070 // */
-
-#endif /*__RT3070_H__ // */
diff --git a/drivers/staging/rt2860/chip/rt3090.h b/drivers/staging/rt2860/chip/rt3090.h
deleted file mode 100644
index 102b938..0000000
--- a/drivers/staging/rt2860/chip/rt3090.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- rt3090.h
-
- Abstract:
-
- Revision History:
- Who When What
- --------- ---------- ----------------------------------------------
- */
-
-#ifndef __RT3090_H__
-#define __RT3090_H__
-
-#ifdef RT3090
-
-#ifndef RTMP_PCI_SUPPORT
-#error "For RT3090, you should define the compile flag -DRTMP_PCI_SUPPORT"
-#endif
-
-#ifndef RTMP_MAC_PCI
-#error "For RT3090, you should define the compile flag -DRTMP_MAC_PCI"
-#endif
-
-#ifndef RTMP_RF_RW_SUPPORT
-#error "For RT3090, you should define the compile flag -DRTMP_RF_RW_SUPPORT"
-#endif
-
-#ifndef RT30xx
-#error "For RT3090, you should define the compile flag -DRT30xx"
-#endif
-
-#define PCIE_PS_SUPPORT
-
-#include "mac_pci.h"
-#include "rt30xx.h"
-
-/* */
-/* Device ID & Vendor ID, these values should match EEPROM value */
-/* */
-#define NIC3090_PCIe_DEVICE_ID 0x3090 /* 1T/1R miniCard */
-#define NIC3091_PCIe_DEVICE_ID 0x3091 /* 1T/2R miniCard */
-#define NIC3092_PCIe_DEVICE_ID 0x3092 /* 2T/2R miniCard */
-
-#endif /* RT3090 // */
-
-#endif /*__RT3090_H__ // */
diff --git a/drivers/staging/rt2860/chip/rt30xx.h b/drivers/staging/rt2860/chip/rt30xx.h
deleted file mode 100644
index 02e1d72..0000000
--- a/drivers/staging/rt2860/chip/rt30xx.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- rt30xx.h
-
- Abstract:
-
- Revision History:
- Who When What
- --------- ---------- ----------------------------------------------
- */
-
-#ifndef __RT30XX_H__
-#define __RT30XX_H__
-
-#ifdef RT30xx
-
-extern struct rt_reg_pair RT30xx_RFRegTable[];
-extern u8 NUM_RF_REG_PARMS;
-
-#endif /* RT30xx // */
-
-#endif /*__RT30XX_H__ // */
diff --git a/drivers/staging/rt2860/chip/rtmp_mac.h b/drivers/staging/rt2860/chip/rtmp_mac.h
deleted file mode 100644
index 3d1e491..0000000
--- a/drivers/staging/rt2860/chip/rtmp_mac.h
+++ /dev/null
@@ -1,1308 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- rtmp_mac.h
-
- Abstract:
- Ralink Wireless Chip MAC related definition & structures
-
- Revision History:
- Who When What
- Justin P. Mattock 11/07/2010 Fix a comments, and typos
- -------- ---------- ----------------------------------------------
-*/
-
-#ifndef __RTMP_MAC_H__
-#define __RTMP_MAC_H__
-
-/* ================================================================================= */
-/* TX / RX ring descriptor format */
-/* ================================================================================= */
-
-/* the first 24-byte in TXD is called TXINFO and will be DMAed to MAC block through TXFIFO. */
-/* MAC block uses this TXINFO to control the transmission behavior of this frame. */
-#define FIFO_MGMT 0
-#define FIFO_HCCA 1
-#define FIFO_EDCA 2
-
-/* */
-/* TXD Wireless Information format for Tx ring and Mgmt Ring */
-/* */
-/*txop : for txop mode */
-/* 0:txop for the MPDU frame will be handles by ASIC by register */
-/* 1/2/3:the MPDU frame is send after PIFS/backoff/SIFS */
-struct PACKED rt_txwi {
- /* Word 0 */
- /* ex: 00 03 00 40 means txop = 3, PHYMODE = 1 */
- u32 FRAG:1; /* 1 to inform TKIP engine this is a fragment. */
- u32 MIMOps:1; /* the remote peer is in dynamic MIMO-PS mode */
- u32 CFACK:1;
- u32 TS:1;
-
- u32 AMPDU:1;
- u32 MpduDensity:3;
- u32 txop:2; /*FOR "THIS" frame. 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs only when previous frame exchange is successful. */
- u32 rsv:6;
-
- u32 MCS:7;
- u32 BW:1; /*channel bandwidth 20MHz or 40 MHz */
- u32 ShortGI:1;
- u32 STBC:2; /* 1: STBC support MCS =0-7, 2,3 : RESERVE */
- u32 Ifs:1; /* */
-/* u32 rsv2:2; //channel bandwidth 20MHz or 40 MHz */
- u32 rsv2:1;
- u32 TxBF:1; /* 3*3 */
- u32 PHYMODE:2;
- /* Word1 */
- /* ex: 1c ff 38 00 means ACK=0, BAWinSize=7, MPDUtotalByteCount = 0x38 */
- u32 ACK:1;
- u32 NSEQ:1;
- u32 BAWinSize:6;
- u32 WirelessCliID:8;
- u32 MPDUtotalByteCount:12;
- u32 PacketId:4;
- /*Word2 */
- u32 IV;
- /*Word3 */
- u32 EIV;
-};
-
-/* */
-/* RXWI wireless information format, in PBF. invisible in driver. */
-/* */
-struct PACKED rt_rxwi {
- /* Word 0 */
- u32 WirelessCliID:8;
- u32 KeyIndex:2;
- u32 BSSID:3;
- u32 UDF:3;
- u32 MPDUtotalByteCount:12;
- u32 TID:4;
- /* Word 1 */
- u32 FRAG:4;
- u32 SEQUENCE:12;
- u32 MCS:7;
- u32 BW:1;
- u32 ShortGI:1;
- u32 STBC:2;
- u32 rsv:3;
- u32 PHYMODE:2; /* 1: this RX frame is unicast to me */
- /*Word2 */
- u32 RSSI0:8;
- u32 RSSI1:8;
- u32 RSSI2:8;
- u32 rsv1:8;
- /*Word3 */
- u32 SNR0:8;
- u32 SNR1:8;
- u32 FOFFSET:8; /* RT35xx */
- u32 rsv2:8;
- /*u32 rsv2:16; */
-};
-
-/* ================================================================================= */
-/* Register format */
-/* ================================================================================= */
-
-/* */
-/* SCH/DMA registers - base address 0x0200 */
-/* */
-/* INT_SOURCE_CSR: Interrupt source register. Write one to clear corresponding bit */
-/* */
-#define DMA_CSR0 0x200
-#define INT_SOURCE_CSR 0x200
-typedef union _INT_SOURCE_CSR_STRUC {
- struct {
- u32 RxDelayINT:1;
- u32 TxDelayINT:1;
- u32 RxDone:1;
- u32 Ac0DmaDone:1; /*4 */
- u32 Ac1DmaDone:1;
- u32 Ac2DmaDone:1;
- u32 Ac3DmaDone:1;
- u32 HccaDmaDone:1; /* bit7 */
- u32 MgmtDmaDone:1;
- u32 MCUCommandINT:1; /*bit 9 */
- u32 RxTxCoherent:1;
- u32 TBTTInt:1;
- u32 PreTBTT:1;
- u32 TXFifoStatusInt:1; /*FIFO Statistics is full, sw should read 0x171c */
- u32 AutoWakeup:1; /*bit14 */
- u32 GPTimer:1;
- u32 RxCoherent:1; /*bit16 */
- u32 TxCoherent:1;
- u32: 14;
- } field;
- u32 word;
-} INT_SOURCE_CSR_STRUC, *PINT_SOURCE_CSR_STRUC;
-
-/* */
-/* INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF */
-/* */
-#define INT_MASK_CSR 0x204
-typedef union _INT_MASK_CSR_STRUC {
- struct {
- u32 RXDelay_INT_MSK:1;
- u32 TxDelay:1;
- u32 RxDone:1;
- u32 Ac0DmaDone:1;
- u32 Ac1DmaDone:1;
- u32 Ac2DmaDone:1;
- u32 Ac3DmaDone:1;
- u32 HccaDmaDone:1;
- u32 MgmtDmaDone:1;
- u32 MCUCommandINT:1;
- u32: 20;
- u32 RxCoherent:1;
- u32 TxCoherent:1;
- } field;
- u32 word;
-} INT_MASK_CSR_STRUC, *PINT_MASK_CSR_STRUC;
-
-#define WPDMA_GLO_CFG 0x208
-typedef union _WPDMA_GLO_CFG_STRUC {
- struct {
- u32 EnableTxDMA:1;
- u32 TxDMABusy:1;
- u32 EnableRxDMA:1;
- u32 RxDMABusy:1;
- u32 WPDMABurstSIZE:2;
- u32 EnTXWriteBackDDONE:1;
- u32 BigEndian:1;
- u32 RXHdrScater:8;
- u32 HDR_SEG_LEN:16;
- } field;
- u32 word;
-} WPDMA_GLO_CFG_STRUC, *PWPDMA_GLO_CFG_STRUC;
-
-#define WPDMA_RST_IDX 0x20c
-typedef union _WPDMA_RST_IDX_STRUC {
- struct {
- u32 RST_DTX_IDX0:1;
- u32 RST_DTX_IDX1:1;
- u32 RST_DTX_IDX2:1;
- u32 RST_DTX_IDX3:1;
- u32 RST_DTX_IDX4:1;
- u32 RST_DTX_IDX5:1;
- u32 rsv:10;
- u32 RST_DRX_IDX0:1;
- u32: 15;
- } field;
- u32 word;
-} WPDMA_RST_IDX_STRUC, *PWPDMA_RST_IDX_STRUC;
-#define DELAY_INT_CFG 0x0210
-typedef union _DELAY_INT_CFG_STRUC {
- struct {
- u32 RXMAX_PTIME:8;
- u32 RXMAX_PINT:7;
- u32 RXDLY_INT_EN:1;
- u32 TXMAX_PTIME:8;
- u32 TXMAX_PINT:7;
- u32 TXDLY_INT_EN:1;
- } field;
- u32 word;
-} DELAY_INT_CFG_STRUC, *PDELAY_INT_CFG_STRUC;
-#define WMM_AIFSN_CFG 0x0214
-typedef union _AIFSN_CSR_STRUC {
- struct {
- u32 Aifsn0:4; /* for AC_BE */
- u32 Aifsn1:4; /* for AC_BK */
- u32 Aifsn2:4; /* for AC_VI */
- u32 Aifsn3:4; /* for AC_VO */
- u32 Rsv:16;
- } field;
- u32 word;
-} AIFSN_CSR_STRUC, *PAIFSN_CSR_STRUC;
-/* */
-/* CWMIN_CSR: CWmin for each EDCA AC */
-/* */
-#define WMM_CWMIN_CFG 0x0218
-typedef union _CWMIN_CSR_STRUC {
- struct {
- u32 Cwmin0:4; /* for AC_BE */
- u32 Cwmin1:4; /* for AC_BK */
- u32 Cwmin2:4; /* for AC_VI */
- u32 Cwmin3:4; /* for AC_VO */
- u32 Rsv:16;
- } field;
- u32 word;
-} CWMIN_CSR_STRUC, *PCWMIN_CSR_STRUC;
-
-/* */
-/* CWMAX_CSR: CWmin for each EDCA AC */
-/* */
-#define WMM_CWMAX_CFG 0x021c
-typedef union _CWMAX_CSR_STRUC {
- struct {
- u32 Cwmax0:4; /* for AC_BE */
- u32 Cwmax1:4; /* for AC_BK */
- u32 Cwmax2:4; /* for AC_VI */
- u32 Cwmax3:4; /* for AC_VO */
- u32 Rsv:16;
- } field;
- u32 word;
-} CWMAX_CSR_STRUC, *PCWMAX_CSR_STRUC;
-
-/* */
-/* AC_TXOP_CSR0: AC_BK/AC_BE TXOP register */
-/* */
-#define WMM_TXOP0_CFG 0x0220
-typedef union _AC_TXOP_CSR0_STRUC {
- struct {
- u16 Ac0Txop; /* for AC_BK, in unit of 32us */
- u16 Ac1Txop; /* for AC_BE, in unit of 32us */
- } field;
- u32 word;
-} AC_TXOP_CSR0_STRUC, *PAC_TXOP_CSR0_STRUC;
-
-/* */
-/* AC_TXOP_CSR1: AC_VO/AC_VI TXOP register */
-/* */
-#define WMM_TXOP1_CFG 0x0224
-typedef union _AC_TXOP_CSR1_STRUC {
- struct {
- u16 Ac2Txop; /* for AC_VI, in unit of 32us */
- u16 Ac3Txop; /* for AC_VO, in unit of 32us */
- } field;
- u32 word;
-} AC_TXOP_CSR1_STRUC, *PAC_TXOP_CSR1_STRUC;
-
-#define RINGREG_DIFF 0x10
-#define GPIO_CTRL_CFG 0x0228 /*MAC_CSR13 */
-#define MCU_CMD_CFG 0x022c
-#define TX_BASE_PTR0 0x0230 /*AC_BK base address */
-#define TX_MAX_CNT0 0x0234
-#define TX_CTX_IDX0 0x0238
-#define TX_DTX_IDX0 0x023c
-#define TX_BASE_PTR1 0x0240 /*AC_BE base address */
-#define TX_MAX_CNT1 0x0244
-#define TX_CTX_IDX1 0x0248
-#define TX_DTX_IDX1 0x024c
-#define TX_BASE_PTR2 0x0250 /*AC_VI base address */
-#define TX_MAX_CNT2 0x0254
-#define TX_CTX_IDX2 0x0258
-#define TX_DTX_IDX2 0x025c
-#define TX_BASE_PTR3 0x0260 /*AC_VO base address */
-#define TX_MAX_CNT3 0x0264
-#define TX_CTX_IDX3 0x0268
-#define TX_DTX_IDX3 0x026c
-#define TX_BASE_PTR4 0x0270 /*HCCA base address */
-#define TX_MAX_CNT4 0x0274
-#define TX_CTX_IDX4 0x0278
-#define TX_DTX_IDX4 0x027c
-#define TX_BASE_PTR5 0x0280 /*MGMT base address */
-#define TX_MAX_CNT5 0x0284
-#define TX_CTX_IDX5 0x0288
-#define TX_DTX_IDX5 0x028c
-#define TX_MGMTMAX_CNT TX_MAX_CNT5
-#define TX_MGMTCTX_IDX TX_CTX_IDX5
-#define TX_MGMTDTX_IDX TX_DTX_IDX5
-#define RX_BASE_PTR 0x0290 /*RX base address */
-#define RX_MAX_CNT 0x0294
-#define RX_CRX_IDX 0x0298
-#define RX_DRX_IDX 0x029c
-
-#define USB_DMA_CFG 0x02a0
-typedef union _USB_DMA_CFG_STRUC {
- struct {
- u32 RxBulkAggTOut:8; /*Rx Bulk Aggregation TimeOut in unit of 33ns */
- u32 RxBulkAggLmt:8; /*Rx Bulk Aggregation Limit in unit of 256 bytes */
- u32 phyclear:1; /*phy watch dog enable. write 1 */
- u32 rsv:2;
- u32 TxClear:1; /*Clear USB DMA TX path */
- u32 TxopHalt:1; /*Halt TXOP count down when TX buffer is full. */
- u32 RxBulkAggEn:1; /*Enable Rx Bulk Aggregation */
- u32 RxBulkEn:1; /*Enable USB DMA Rx */
- u32 TxBulkEn:1; /*Enable USB DMA Tx */
- u32 EpoutValid:6; /*OUT endpoint data valid */
- u32 RxBusy:1; /*USB DMA RX FSM busy */
- u32 TxBusy:1; /*USB DMA TX FSM busy */
- } field;
- u32 word;
-} USB_DMA_CFG_STRUC, *PUSB_DMA_CFG_STRUC;
-
-/* */
-/* 3 PBF registers */
-/* */
-/* */
-/* Most are for debug. Driver doesn't touch PBF register. */
-#define PBF_SYS_CTRL 0x0400
-#define PBF_CFG 0x0408
-#define PBF_MAX_PCNT 0x040C
-#define PBF_CTRL 0x0410
-#define PBF_INT_STA 0x0414
-#define PBF_INT_ENA 0x0418
-#define TXRXQ_PCNT 0x0438
-#define PBF_DBG 0x043c
-#define PBF_CAP_CTRL 0x0440
-
-#ifdef RT30xx
-#ifdef RTMP_EFUSE_SUPPORT
-/* eFuse registers */
-#define EFUSE_CTRL 0x0580
-#define EFUSE_DATA0 0x0590
-#define EFUSE_DATA1 0x0594
-#define EFUSE_DATA2 0x0598
-#define EFUSE_DATA3 0x059c
-#endif /* RTMP_EFUSE_SUPPORT // */
-#endif /* RT30xx // */
-
-#define OSC_CTRL 0x5a4
-#define PCIE_PHY_TX_ATTENUATION_CTRL 0x05C8
-#define LDO_CFG0 0x05d4
-#define GPIO_SWITCH 0x05dc
-
-/* */
-/* 4 MAC registers */
-/* */
-/* */
-/* 4.1 MAC SYSTEM configuration registers (offset:0x1000) */
-/* */
-#define MAC_CSR0 0x1000
-typedef union _ASIC_VER_ID_STRUC {
- struct {
- u16 ASICRev; /* reversion : 0 */
- u16 ASICVer; /* version : 2860 */
- } field;
- u32 word;
-} ASIC_VER_ID_STRUC, *PASIC_VER_ID_STRUC;
-#define MAC_SYS_CTRL 0x1004 /*MAC_CSR1 */
-#define MAC_ADDR_DW0 0x1008 /* MAC ADDR DW0 */
-#define MAC_ADDR_DW1 0x100c /* MAC ADDR DW1 */
-/* */
-/* MAC_CSR2: STA MAC register 0 */
-/* */
-typedef union _MAC_DW0_STRUC {
- struct {
- u8 Byte0; /* MAC address byte 0 */
- u8 Byte1; /* MAC address byte 1 */
- u8 Byte2; /* MAC address byte 2 */
- u8 Byte3; /* MAC address byte 3 */
- } field;
- u32 word;
-} MAC_DW0_STRUC, *PMAC_DW0_STRUC;
-
-/* */
-/* MAC_CSR3: STA MAC register 1 */
-/* */
-typedef union _MAC_DW1_STRUC {
- struct {
- u8 Byte4; /* MAC address byte 4 */
- u8 Byte5; /* MAC address byte 5 */
- u8 U2MeMask;
- u8 Rsvd1;
- } field;
- u32 word;
-} MAC_DW1_STRUC, *PMAC_DW1_STRUC;
-
-#define MAC_BSSID_DW0 0x1010 /* MAC BSSID DW0 */
-#define MAC_BSSID_DW1 0x1014 /* MAC BSSID DW1 */
-
-/* */
-/* MAC_CSR5: BSSID register 1 */
-/* */
-typedef union _MAC_CSR5_STRUC {
- struct {
- u8 Byte4; /* BSSID byte 4 */
- u8 Byte5; /* BSSID byte 5 */
- u16 BssIdMask:2; /* 0: one BSSID, 10: 4 BSSID, 01: 2 BSSID , 11: 8BSSID */
- u16 MBssBcnNum:3;
- u16 Rsvd:11;
- } field;
- u32 word;
-} MAC_CSR5_STRUC, *PMAC_CSR5_STRUC;
-
-#define MAX_LEN_CFG 0x1018 /* rt2860b max 16k bytes. bit12:13 Maximum PSDU length (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16 */
-#define BBP_CSR_CFG 0x101c /* */
-/* */
-/* BBP_CSR_CFG: BBP serial control register */
-/* */
-typedef union _BBP_CSR_CFG_STRUC {
- struct {
- u32 Value:8; /* Register value to program into BBP */
- u32 RegNum:8; /* Selected BBP register */
- u32 fRead:1; /* 0: Write BBP, 1: Read BBP */
- u32 Busy:1; /* 1: ASIC is busy execute BBP programming. */
- u32 BBP_PAR_DUR:1; /* 0: 4 MAC clock cycles 1: 8 MAC clock cycles */
- u32 BBP_RW_MODE:1; /* 0: use serial mode 1:parallel */
- u32: 12;
- } field;
- u32 word;
-} BBP_CSR_CFG_STRUC, *PBBP_CSR_CFG_STRUC;
-#define RF_CSR_CFG0 0x1020
-/* */
-/* RF_CSR_CFG: RF control register */
-/* */
-typedef union _RF_CSR_CFG0_STRUC {
- struct {
- u32 RegIdAndContent:24; /* Register value to program into BBP */
- u32 bitwidth:5; /* Selected BBP register */
- u32 StandbyMode:1; /* 0: high when stand by 1: low when standby */
- u32 Sel:1; /* 0:RF_LE0 activate 1:RF_LE1 activate */
- u32 Busy:1; /* 0: idle 1: 8busy */
- } field;
- u32 word;
-} RF_CSR_CFG0_STRUC, *PRF_CSR_CFG0_STRUC;
-#define RF_CSR_CFG1 0x1024
-typedef union _RF_CSR_CFG1_STRUC {
- struct {
- u32 RegIdAndContent:24; /* Register value to program into BBP */
- u32 RFGap:5; /* Gap between BB_CONTROL_RF and RF_LE. 0: 3 system clock cycle (37.5usec) 1: 5 system clock cycle (62.5usec) */
- u32 rsv:7; /* 0: idle 1: 8busy */
- } field;
- u32 word;
-} RF_CSR_CFG1_STRUC, *PRF_CSR_CFG1_STRUC;
-#define RF_CSR_CFG2 0x1028 /* */
-typedef union _RF_CSR_CFG2_STRUC {
- struct {
- u32 RegIdAndContent:24; /* Register value to program into BBP */
- u32 rsv:8; /* 0: idle 1: 8busy */
- } field;
- u32 word;
-} RF_CSR_CFG2_STRUC, *PRF_CSR_CFG2_STRUC;
-#define LED_CFG 0x102c /* MAC_CSR14 */
-typedef union _LED_CFG_STRUC {
- struct {
- u32 OnPeriod:8; /* blinking on period unit 1ms */
- u32 OffPeriod:8; /* blinking off period unit 1ms */
- u32 SlowBlinkPeriod:6; /* slow blinking period. unit:1ms */
- u32 rsv:2;
- u32 RLedMode:2; /* red Led Mode 0: off1: blinking upon TX2: periodic slow blinking3: always on */
- u32 GLedMode:2; /* green Led Mode */
- u32 YLedMode:2; /* yellow Led Mode */
- u32 LedPolar:1; /* Led Polarity. 0: active low1: active high */
- u32: 1;
- } field;
- u32 word;
-} LED_CFG_STRUC, *PLED_CFG_STRUC;
-/* */
-/* 4.2 MAC TIMING configuration registers (offset:0x1100) */
-/* */
-#define XIFS_TIME_CFG 0x1100 /* MAC_CSR8 MAC_CSR9 */
-typedef union _IFS_SLOT_CFG_STRUC {
- struct {
- u32 CckmSifsTime:8; /* unit 1us. Applied after CCK RX/TX */
- u32 OfdmSifsTime:8; /* unit 1us. Applied after OFDM RX/TX */
- u32 OfdmXifsTime:4; /*OFDM SIFS. unit 1us. Applied after OFDM RX when MAC doesn't reference BBP signal BBRXEND */
- u32 EIFS:9; /* unit 1us */
- u32 BBRxendEnable:1; /* reference RXEND signal to begin XIFS defer */
- u32 rsv:2;
- } field;
- u32 word;
-} IFS_SLOT_CFG_STRUC, *PIFS_SLOT_CFG_STRUC;
-
-#define BKOFF_SLOT_CFG 0x1104 /* mac_csr9 last 8 bits */
-#define NAV_TIME_CFG 0x1108 /* NAV (MAC_CSR15) */
-#define CH_TIME_CFG 0x110C /* Count as channel busy */
-#define PBF_LIFE_TIMER 0x1110 /*TX/RX MPDU timestamp timer (free run)Unit: 1us */
-#define BCN_TIME_CFG 0x1114 /* TXRX_CSR9 */
-
-#define BCN_OFFSET0 0x042C
-#define BCN_OFFSET1 0x0430
-
-/* */
-/* BCN_TIME_CFG : Synchronization control register */
-/* */
-typedef union _BCN_TIME_CFG_STRUC {
- struct {
- u32 BeaconInterval:16; /* in unit of 1/16 TU */
- u32 bTsfTicking:1; /* Enable TSF auto counting */
- u32 TsfSyncMode:2; /* Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode */
- u32 bTBTTEnable:1;
- u32 bBeaconGen:1; /* Enable beacon generator */
- u32: 3;
- u32 TxTimestampCompensate:8;
- } field;
- u32 word;
-} BCN_TIME_CFG_STRUC, *PBCN_TIME_CFG_STRUC;
-#define TBTT_SYNC_CFG 0x1118 /* txrx_csr10 */
-#define TSF_TIMER_DW0 0x111C /* Local TSF timer lsb 32 bits. Read-only */
-#define TSF_TIMER_DW1 0x1120 /* msb 32 bits. Read-only. */
-#define TBTT_TIMER 0x1124 /* TImer remains till next TBTT. Read-only. TXRX_CSR14 */
-#define INT_TIMER_CFG 0x1128 /* */
-#define INT_TIMER_EN 0x112c /* GP-timer and pre-tbtt Int enable */
-#define CH_IDLE_STA 0x1130 /* channel idle time */
-#define CH_BUSY_STA 0x1134 /* channle busy time */
-/* */
-/* 4.2 MAC POWER configuration registers (offset:0x1200) */
-/* */
-#define MAC_STATUS_CFG 0x1200 /* old MAC_CSR12 */
-#define PWR_PIN_CFG 0x1204 /* old MAC_CSR12 */
-#define AUTO_WAKEUP_CFG 0x1208 /* old MAC_CSR10 */
-/* */
-/* AUTO_WAKEUP_CFG: Manual power control / status register */
-/* */
-typedef union _AUTO_WAKEUP_STRUC {
- struct {
- u32 AutoLeadTime:8;
- u32 NumofSleepingTbtt:7; /* ForceWake has high privilege than PutToSleep when both set */
- u32 EnableAutoWakeup:1; /* 0:sleep, 1:awake */
- u32: 16;
- } field;
- u32 word;
-} AUTO_WAKEUP_STRUC, *PAUTO_WAKEUP_STRUC;
-/* */
-/* 4.3 MAC TX configuration registers (offset:0x1300) */
-/* */
-
-#define EDCA_AC0_CFG 0x1300 /*AC_TXOP_CSR0 0x3474 */
-#define EDCA_AC1_CFG 0x1304
-#define EDCA_AC2_CFG 0x1308
-#define EDCA_AC3_CFG 0x130c
-typedef union _EDCA_AC_CFG_STRUC {
- struct {
- u32 AcTxop:8; /* in unit of 32us */
- u32 Aifsn:4; /* # of slot time */
- u32 Cwmin:4; /* */
- u32 Cwmax:4; /*unit power of 2 */
- u32: 12; /* */
- } field;
- u32 word;
-} EDCA_AC_CFG_STRUC, *PEDCA_AC_CFG_STRUC;
-
-#define EDCA_TID_AC_MAP 0x1310
-#define TX_PWR_CFG_0 0x1314
-#define TX_PWR_CFG_1 0x1318
-#define TX_PWR_CFG_2 0x131C
-#define TX_PWR_CFG_3 0x1320
-#define TX_PWR_CFG_4 0x1324
-#define TX_PIN_CFG 0x1328
-#define TX_BAND_CFG 0x132c /* 0x1 use upper 20MHz. 0 juse lower 20MHz */
-#define TX_SW_CFG0 0x1330
-#define TX_SW_CFG1 0x1334
-#define TX_SW_CFG2 0x1338
-#define TXOP_THRES_CFG 0x133c
-#define TXOP_CTRL_CFG 0x1340
-#define TX_RTS_CFG 0x1344
-
-typedef union _TX_RTS_CFG_STRUC {
- struct {
- u32 AutoRtsRetryLimit:8;
- u32 RtsThres:16; /* unit:byte */
- u32 RtsFbkEn:1; /* enable rts rate fallback */
- u32 rsv:7; /* 1: HT non-STBC control frame enable */
- } field;
- u32 word;
-} TX_RTS_CFG_STRUC, *PTX_RTS_CFG_STRUC;
-#define TX_TIMEOUT_CFG 0x1348
-typedef union _TX_TIMEOUT_CFG_STRUC {
- struct {
- u32 rsv:4;
- u32 MpduLifeTime:4; /* expiration time = 2^(9+MPDU LIFE TIME) us */
- u32 RxAckTimeout:8; /* unit:slot. Used for TX precedure */
- u32 TxopTimeout:8; /*TXOP timeout value for TXOP truncation. It is recommended that (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT) */
- u32 rsv2:8; /* 1: HT non-STBC control frame enable */
- } field;
- u32 word;
-} TX_TIMEOUT_CFG_STRUC, *PTX_TIMEOUT_CFG_STRUC;
-#define TX_RTY_CFG 0x134c
-typedef union PACKED _TX_RTY_CFG_STRUC {
- struct {
- u32 ShortRtyLimit:8; /* short retry limit */
- u32 LongRtyLimit:8; /* long retry limit */
- u32 LongRtyThre:12; /* Long retry threshold */
- u32 NonAggRtyMode:1; /* Non-Aggregate MPDU retry mode. 0:expired by retry limit, 1: expired by mpdu life timer */
- u32 AggRtyMode:1; /* Aggregate MPDU retry mode. 0:expired by retry limit, 1: expired by mpdu life timer */
- u32 TxautoFBEnable:1; /* Tx retry PHY rate auto fallback enable */
- u32 rsv:1; /* 1: HT non-STBC control frame enable */
- } field;
- u32 word;
-} TX_RTY_CFG_STRUC, *PTX_RTY_CFG_STRUC;
-#define TX_LINK_CFG 0x1350
-typedef union PACKED _TX_LINK_CFG_STRUC {
- struct PACKED {
- u32 RemoteMFBLifeTime:8; /*remote MFB life time. unit : 32us */
- u32 MFBEnable:1; /* TX apply remote MFB 1:enable */
- u32 RemoteUMFSEnable:1; /* remote unsolicit MFB enable. 0: not apply remote remote unsolicit (MFS=7) */
- u32 TxMRQEn:1; /* MCS request TX enable */
- u32 TxRDGEn:1; /* RDG TX enable */
- u32 TxCFAckEn:1; /* Piggyback CF-ACK enable */
- u32 rsv:3; /* */
- u32 RemotMFB:8; /* remote MCS feedback */
- u32 RemotMFS:8; /*remote MCS feedback sequence number */
- } field;
- u32 word;
-} TX_LINK_CFG_STRUC, *PTX_LINK_CFG_STRUC;
-#define HT_FBK_CFG0 0x1354
-typedef union PACKED _HT_FBK_CFG0_STRUC {
- struct {
- u32 HTMCS0FBK:4;
- u32 HTMCS1FBK:4;
- u32 HTMCS2FBK:4;
- u32 HTMCS3FBK:4;
- u32 HTMCS4FBK:4;
- u32 HTMCS5FBK:4;
- u32 HTMCS6FBK:4;
- u32 HTMCS7FBK:4;
- } field;
- u32 word;
-} HT_FBK_CFG0_STRUC, *PHT_FBK_CFG0_STRUC;
-#define HT_FBK_CFG1 0x1358
-typedef union _HT_FBK_CFG1_STRUC {
- struct {
- u32 HTMCS8FBK:4;
- u32 HTMCS9FBK:4;
- u32 HTMCS10FBK:4;
- u32 HTMCS11FBK:4;
- u32 HTMCS12FBK:4;
- u32 HTMCS13FBK:4;
- u32 HTMCS14FBK:4;
- u32 HTMCS15FBK:4;
- } field;
- u32 word;
-} HT_FBK_CFG1_STRUC, *PHT_FBK_CFG1_STRUC;
-#define LG_FBK_CFG0 0x135c
-typedef union _LG_FBK_CFG0_STRUC {
- struct {
- u32 OFDMMCS0FBK:4; /*initial value is 0 */
- u32 OFDMMCS1FBK:4; /*initial value is 0 */
- u32 OFDMMCS2FBK:4; /*initial value is 1 */
- u32 OFDMMCS3FBK:4; /*initial value is 2 */
- u32 OFDMMCS4FBK:4; /*initial value is 3 */
- u32 OFDMMCS5FBK:4; /*initial value is 4 */
- u32 OFDMMCS6FBK:4; /*initial value is 5 */
- u32 OFDMMCS7FBK:4; /*initial value is 6 */
- } field;
- u32 word;
-} LG_FBK_CFG0_STRUC, *PLG_FBK_CFG0_STRUC;
-#define LG_FBK_CFG1 0x1360
-typedef union _LG_FBK_CFG1_STRUC {
- struct {
- u32 CCKMCS0FBK:4; /*initial value is 0 */
- u32 CCKMCS1FBK:4; /*initial value is 0 */
- u32 CCKMCS2FBK:4; /*initial value is 1 */
- u32 CCKMCS3FBK:4; /*initial value is 2 */
- u32 rsv:16;
- } field;
- u32 word;
-} LG_FBK_CFG1_STRUC, *PLG_FBK_CFG1_STRUC;
-
-/*======================================================= */
-/*================ Protection Paramater================================ */
-/*======================================================= */
-#define CCK_PROT_CFG 0x1364 /*CCK Protection */
-#define ASIC_SHORTNAV 1
-#define ASIC_longNAV 2
-#define ASIC_RTS 1
-#define ASIC_CTS 2
-typedef union _PROT_CFG_STRUC {
- struct {
- u32 ProtectRate:16; /*Protection control frame rate for CCK TX(RTS/CTS/CFEnd). */
- u32 ProtectCtrl:2; /*Protection control frame type for CCK TX. 1:RTS/CTS, 2:CTS-to-self, 0:None, 3:rsv */
- u32 ProtectNav:2; /*TXOP protection type for CCK TX. 0:None, 1:ShortNAVprotect, 2:LongNAVProtect, 3:rsv */
- u32 TxopAllowCck:1; /*CCK TXOP allowance.0:disallow. */
- u32 TxopAllowOfdm:1; /*CCK TXOP allowance.0:disallow. */
- u32 TxopAllowMM20:1; /*CCK TXOP allowance. 0:disallow. */
- u32 TxopAllowMM40:1; /*CCK TXOP allowance.0:disallow. */
- u32 TxopAllowGF20:1; /*CCK TXOP allowance.0:disallow. */
- u32 TxopAllowGF40:1; /*CCK TXOP allowance.0:disallow. */
- u32 RTSThEn:1; /*RTS threshold enable on CCK TX */
- u32 rsv:5;
- } field;
- u32 word;
-} PROT_CFG_STRUC, *PPROT_CFG_STRUC;
-
-#define OFDM_PROT_CFG 0x1368 /*OFDM Protection */
-#define MM20_PROT_CFG 0x136C /*MM20 Protection */
-#define MM40_PROT_CFG 0x1370 /*MM40 Protection */
-#define GF20_PROT_CFG 0x1374 /*GF20 Protection */
-#define GF40_PROT_CFG 0x1378 /*GR40 Protection */
-#define EXP_CTS_TIME 0x137C /* */
-#define EXP_ACK_TIME 0x1380 /* */
-
-/* */
-/* 4.4 MAC RX configuration registers (offset:0x1400) */
-/* */
-#define RX_FILTR_CFG 0x1400 /*TXRX_CSR0 */
-#define AUTO_RSP_CFG 0x1404 /*TXRX_CSR4 */
-/* */
-/* TXRX_CSR4: Auto-Responder/ */
-/* */
-typedef union _AUTO_RSP_CFG_STRUC {
- struct {
- u32 AutoResponderEnable:1;
- u32 BACAckPolicyEnable:1; /* 0:long, 1:short preamble */
- u32 CTS40MMode:1; /* Response CTS 40MHz duplicate mode */
- u32 CTS40MRef:1; /* Response CTS 40MHz duplicate mode */
- u32 AutoResponderPreamble:1; /* 0:long, 1:short preamble */
- u32 rsv:1; /* Power bit value in conrtrol frame */
- u32 DualCTSEn:1; /* Power bit value in conrtrol frame */
- u32 AckCtsPsmBit:1; /* Power bit value in conrtrol frame */
- u32: 24;
- } field;
- u32 word;
-} AUTO_RSP_CFG_STRUC, *PAUTO_RSP_CFG_STRUC;
-
-#define LEGACY_BASIC_RATE 0x1408 /* TXRX_CSR5 0x3054 */
-#define HT_BASIC_RATE 0x140c
-#define HT_CTRL_CFG 0x1410
-#define SIFS_COST_CFG 0x1414
-#define RX_PARSER_CFG 0x1418 /*Set NAV for all received frames */
-
-/* */
-/* 4.5 MAC Security configuration (offset:0x1500) */
-/* */
-#define TX_SEC_CNT0 0x1500 /* */
-#define RX_SEC_CNT0 0x1504 /* */
-#define CCMP_FC_MUTE 0x1508 /* */
-/* */
-/* 4.6 HCCA/PSMP (offset:0x1600) */
-/* */
-#define TXOP_HLDR_ADDR0 0x1600
-#define TXOP_HLDR_ADDR1 0x1604
-#define TXOP_HLDR_ET 0x1608
-#define QOS_CFPOLL_RA_DW0 0x160c
-#define QOS_CFPOLL_A1_DW1 0x1610
-#define QOS_CFPOLL_QC 0x1614
-/* */
-/* 4.7 MAC Statistis registers (offset:0x1700) */
-/* */
-#define RX_STA_CNT0 0x1700 /* */
-#define RX_STA_CNT1 0x1704 /* */
-#define RX_STA_CNT2 0x1708 /* */
-
-/* */
-/* RX_STA_CNT0_STRUC: RX PLCP error count & RX CRC error count */
-/* */
-typedef union _RX_STA_CNT0_STRUC {
- struct {
- u16 CrcErr;
- u16 PhyErr;
- } field;
- u32 word;
-} RX_STA_CNT0_STRUC, *PRX_STA_CNT0_STRUC;
-
-/* */
-/* RX_STA_CNT1_STRUC: RX False CCA count & RX long frame count */
-/* */
-typedef union _RX_STA_CNT1_STRUC {
- struct {
- u16 FalseCca;
- u16 PlcpErr;
- } field;
- u32 word;
-} RX_STA_CNT1_STRUC, *PRX_STA_CNT1_STRUC;
-
-/* */
-/* RX_STA_CNT2_STRUC: */
-/* */
-typedef union _RX_STA_CNT2_STRUC {
- struct {
- u16 RxDupliCount;
- u16 RxFifoOverflowCount;
- } field;
- u32 word;
-} RX_STA_CNT2_STRUC, *PRX_STA_CNT2_STRUC;
-#define TX_STA_CNT0 0x170C /* */
-/* */
-/* STA_CSR3: TX Beacon count */
-/* */
-typedef union _TX_STA_CNT0_STRUC {
- struct {
- u16 TxFailCount;
- u16 TxBeaconCount;
- } field;
- u32 word;
-} TX_STA_CNT0_STRUC, *PTX_STA_CNT0_STRUC;
-#define TX_STA_CNT1 0x1710 /* */
-/* */
-/* TX_STA_CNT1: TX tx count */
-/* */
-typedef union _TX_STA_CNT1_STRUC {
- struct {
- u16 TxSuccess;
- u16 TxRetransmit;
- } field;
- u32 word;
-} TX_STA_CNT1_STRUC, *PTX_STA_CNT1_STRUC;
-#define TX_STA_CNT2 0x1714 /* */
-/* */
-/* TX_STA_CNT2: TX tx count */
-/* */
-typedef union _TX_STA_CNT2_STRUC {
- struct {
- u16 TxZeroLenCount;
- u16 TxUnderFlowCount;
- } field;
- u32 word;
-} TX_STA_CNT2_STRUC, *PTX_STA_CNT2_STRUC;
-#define TX_STA_FIFO 0x1718 /* */
-/* */
-/* TX_STA_FIFO_STRUC: TX Result for specific PID status fifo register */
-/* */
-typedef union PACKED _TX_STA_FIFO_STRUC {
- struct {
- u32 bValid:1; /* 1:This register contains a valid TX result */
- u32 PidType:4;
- u32 TxSuccess:1; /* Tx No retry success */
- u32 TxAggre:1; /* Tx Retry Success */
- u32 TxAckRequired:1; /* Tx fail */
- u32 wcid:8; /*wireless client index */
-/* u32 SuccessRate:16; //include MCS, mode ,shortGI, BW settingSame format as TXWI Word 0 Bit 31-16. */
- u32 SuccessRate:13; /*include MCS, mode ,shortGI, BW settingSame format as TXWI Word 0 Bit 31-16. */
- u32 TxBF:1;
- u32 Reserve:2;
- } field;
- u32 word;
-} TX_STA_FIFO_STRUC, *PTX_STA_FIFO_STRUC;
-/* Debug counter */
-#define TX_AGG_CNT 0x171c
-typedef union _TX_AGG_CNT_STRUC {
- struct {
- u16 NonAggTxCount;
- u16 AggTxCount;
- } field;
- u32 word;
-} TX_AGG_CNT_STRUC, *PTX_AGG_CNT_STRUC;
-/* Debug counter */
-#define TX_AGG_CNT0 0x1720
-typedef union _TX_AGG_CNT0_STRUC {
- struct {
- u16 AggSize1Count;
- u16 AggSize2Count;
- } field;
- u32 word;
-} TX_AGG_CNT0_STRUC, *PTX_AGG_CNT0_STRUC;
-/* Debug counter */
-#define TX_AGG_CNT1 0x1724
-typedef union _TX_AGG_CNT1_STRUC {
- struct {
- u16 AggSize3Count;
- u16 AggSize4Count;
- } field;
- u32 word;
-} TX_AGG_CNT1_STRUC, *PTX_AGG_CNT1_STRUC;
-#define TX_AGG_CNT2 0x1728
-typedef union _TX_AGG_CNT2_STRUC {
- struct {
- u16 AggSize5Count;
- u16 AggSize6Count;
- } field;
- u32 word;
-} TX_AGG_CNT2_STRUC, *PTX_AGG_CNT2_STRUC;
-/* Debug counter */
-#define TX_AGG_CNT3 0x172c
-typedef union _TX_AGG_CNT3_STRUC {
- struct {
- u16 AggSize7Count;
- u16 AggSize8Count;
- } field;
- u32 word;
-} TX_AGG_CNT3_STRUC, *PTX_AGG_CNT3_STRUC;
-/* Debug counter */
-#define TX_AGG_CNT4 0x1730
-typedef union _TX_AGG_CNT4_STRUC {
- struct {
- u16 AggSize9Count;
- u16 AggSize10Count;
- } field;
- u32 word;
-} TX_AGG_CNT4_STRUC, *PTX_AGG_CNT4_STRUC;
-#define TX_AGG_CNT5 0x1734
-typedef union _TX_AGG_CNT5_STRUC {
- struct {
- u16 AggSize11Count;
- u16 AggSize12Count;
- } field;
- u32 word;
-} TX_AGG_CNT5_STRUC, *PTX_AGG_CNT5_STRUC;
-#define TX_AGG_CNT6 0x1738
-typedef union _TX_AGG_CNT6_STRUC {
- struct {
- u16 AggSize13Count;
- u16 AggSize14Count;
- } field;
- u32 word;
-} TX_AGG_CNT6_STRUC, *PTX_AGG_CNT6_STRUC;
-#define TX_AGG_CNT7 0x173c
-typedef union _TX_AGG_CNT7_STRUC {
- struct {
- u16 AggSize15Count;
- u16 AggSize16Count;
- } field;
- u32 word;
-} TX_AGG_CNT7_STRUC, *PTX_AGG_CNT7_STRUC;
-#define MPDU_DENSITY_CNT 0x1740
-typedef union _MPDU_DEN_CNT_STRUC {
- struct {
- u16 TXZeroDelCount; /*TX zero length delimiter count */
- u16 RXZeroDelCount; /*RX zero length delimiter count */
- } field;
- u32 word;
-} MPDU_DEN_CNT_STRUC, *PMPDU_DEN_CNT_STRUC;
-/* */
-/* TXRX control registers - base address 0x3000 */
-/* */
-/* rt2860b UNKNOWN reg use R/O Reg Addr 0x77d0 first.. */
-#define TXRX_CSR1 0x77d0
-
-/* */
-/* Security key table memory, base address = 0x1000 */
-/* */
-#define MAC_WCID_BASE 0x1800 /*8-bytes(use only 6-bytes) * 256 entry = */
-#define HW_WCID_ENTRY_SIZE 8
-#define PAIRWISE_KEY_TABLE_BASE 0x4000 /* 32-byte * 256-entry = -byte */
-#define HW_KEY_ENTRY_SIZE 0x20
-#define PAIRWISE_IVEIV_TABLE_BASE 0x6000 /* 8-byte * 256-entry = -byte */
-#define MAC_IVEIV_TABLE_BASE 0x6000 /* 8-byte * 256-entry = -byte */
-#define HW_IVEIV_ENTRY_SIZE 8
-#define MAC_WCID_ATTRIBUTE_BASE 0x6800 /* 4-byte * 256-entry = -byte */
-#define HW_WCID_ATTRI_SIZE 4
-#define WCID_RESERVED 0x6bfc
-#define SHARED_KEY_TABLE_BASE 0x6c00 /* 32-byte * 16-entry = 512-byte */
-#define SHARED_KEY_MODE_BASE 0x7000 /* 32-byte * 16-entry = 512-byte */
-#define HW_SHARED_KEY_MODE_SIZE 4
-#define SHAREDKEYTABLE 0
-#define PAIRWISEKEYTABLE 1
-
-typedef union _SHAREDKEY_MODE_STRUC {
- struct {
- u32 Bss0Key0CipherAlg:3;
- u32: 1;
- u32 Bss0Key1CipherAlg:3;
- u32: 1;
- u32 Bss0Key2CipherAlg:3;
- u32: 1;
- u32 Bss0Key3CipherAlg:3;
- u32: 1;
- u32 Bss1Key0CipherAlg:3;
- u32: 1;
- u32 Bss1Key1CipherAlg:3;
- u32: 1;
- u32 Bss1Key2CipherAlg:3;
- u32: 1;
- u32 Bss1Key3CipherAlg:3;
- u32: 1;
- } field;
- u32 word;
-} SHAREDKEY_MODE_STRUC, *PSHAREDKEY_MODE_STRUC;
-
-/* 8-byte per entry, 64-entry for pairwise key table */
-struct rt_hw_wcid_entry {
- u8 Address[6];
- u8 Rsv[2];
-};
-
-/* ================================================================================= */
-/* WCID format */
-/* ================================================================================= */
-/*7.1 WCID ENTRY format : 8bytes */
-struct rt_wcid_entry {
- u8 RXBABitmap7; /* bit0 for TID8, bit7 for TID 15 */
- u8 RXBABitmap0; /* bit0 for TID0, bit7 for TID 7 */
- u8 MAC[6]; /* 0 for shared key table. 1 for pairwise key table */
-};
-
-/*8.1.1 SECURITY KEY format : 8DW */
-/* 32-byte per entry, total 16-entry for shared key table, 64-entry for pairwise key table */
-struct rt_hw_key_entry {
- u8 Key[16];
- u8 TxMic[8];
- u8 RxMic[8];
-};
-
-/*8.1.2 IV/EIV format : 2DW */
-
-/*8.1.3 RX attribute entry format : 1DW */
-struct rt_mac_attribute {
- u32 KeyTab:1; /* 0 for shared key table. 1 for pairwise key table */
- u32 PairKeyMode:3;
- u32 BSSIDIdx:3; /*multipleBSS index for the WCID */
- u32 RXWIUDF:3;
- u32 rsv:22;
-};
-
-/* ================================================================================= */
-/* HOST-MCU communication data structure */
-/* ================================================================================= */
-
-/* */
-/* H2M_MAILBOX_CSR: Host-to-MCU Mailbox */
-/* */
-typedef union _H2M_MAILBOX_STRUC {
- struct {
- u32 LowByte:8;
- u32 HighByte:8;
- u32 CmdToken:8;
- u32 Owner:8;
- } field;
- u32 word;
-} H2M_MAILBOX_STRUC, *PH2M_MAILBOX_STRUC;
-
-/* */
-/* M2H_CMD_DONE_CSR: MCU-to-Host command complete indication */
-/* */
-typedef union _M2H_CMD_DONE_STRUC {
- struct {
- u32 CmdToken0;
- u32 CmdToken1;
- u32 CmdToken2;
- u32 CmdToken3;
- } field;
- u32 word;
-} M2H_CMD_DONE_STRUC, *PM2H_CMD_DONE_STRUC;
-
-/*NAV_TIME_CFG :NAV */
-typedef union _NAV_TIME_CFG_STRUC {
- struct {
- u8 Sifs; /* in unit of 1-us */
- u8 SlotTime; /* in unit of 1-us */
- u16 Eifs:9; /* in unit of 1-us */
- u16 ZeroSifs:1; /* Applied zero SIFS timer after OFDM RX 0: disable */
- u16 rsv:6;
- } field;
- u32 word;
-} NAV_TIME_CFG_STRUC, *PNAV_TIME_CFG_STRUC;
-
-/* */
-/* RX_FILTR_CFG: /RX configuration register */
-/* */
-typedef union _RX_FILTR_CFG_STRUC {
- struct {
- u32 DropCRCErr:1; /* Drop CRC error */
- u32 DropPhyErr:1; /* Drop physical error */
- u32 DropNotToMe:1; /* Drop not to me unicast frame */
- u32 DropNotMyBSSID:1; /* Drop fram ToDs bit is true */
-
- u32 DropVerErr:1; /* Drop version error frame */
- u32 DropMcast:1; /* Drop multicast frames */
- u32 DropBcast:1; /* Drop broadcast frames */
- u32 DropDuplicate:1; /* Drop duplicate frame */
-
- u32 DropCFEndAck:1; /* Drop Ps-Poll */
- u32 DropCFEnd:1; /* Drop Ps-Poll */
- u32 DropAck:1; /* Drop Ps-Poll */
- u32 DropCts:1; /* Drop Ps-Poll */
-
- u32 DropRts:1; /* Drop Ps-Poll */
- u32 DropPsPoll:1; /* Drop Ps-Poll */
- u32 DropBA:1; /* */
- u32 DropBAR:1; /* */
-
- u32 DropRsvCntlType:1;
- u32: 15;
- } field;
- u32 word;
-} RX_FILTR_CFG_STRUC, *PRX_FILTR_CFG_STRUC;
-
-/* */
-/* PHY_CSR4: RF serial control register */
-/* */
-typedef union _PHY_CSR4_STRUC {
- struct {
- u32 RFRegValue:24; /* Register value (include register id) serial out to RF/IF chip. */
- u32 NumberOfBits:5; /* Number of bits used in RFRegValue (I:20, RFMD:22) */
- u32 IFSelect:1; /* 1: select IF to program, 0: select RF to program */
- u32 PLL_LD:1; /* RF PLL_LD status */
- u32 Busy:1; /* 1: ASIC is busy execute RF programming. */
- } field;
- u32 word;
-} PHY_CSR4_STRUC, *PPHY_CSR4_STRUC;
-
-/* */
-/* SEC_CSR5: shared key table security mode register */
-/* */
-typedef union _SEC_CSR5_STRUC {
- struct {
- u32 Bss2Key0CipherAlg:3;
- u32: 1;
- u32 Bss2Key1CipherAlg:3;
- u32: 1;
- u32 Bss2Key2CipherAlg:3;
- u32: 1;
- u32 Bss2Key3CipherAlg:3;
- u32: 1;
- u32 Bss3Key0CipherAlg:3;
- u32: 1;
- u32 Bss3Key1CipherAlg:3;
- u32: 1;
- u32 Bss3Key2CipherAlg:3;
- u32: 1;
- u32 Bss3Key3CipherAlg:3;
- u32: 1;
- } field;
- u32 word;
-} SEC_CSR5_STRUC, *PSEC_CSR5_STRUC;
-
-/* */
-/* HOST_CMD_CSR: For HOST to interrupt embedded processor */
-/* */
-typedef union _HOST_CMD_CSR_STRUC {
- struct {
- u32 HostCommand:8;
- u32 Rsv:24;
- } field;
- u32 word;
-} HOST_CMD_CSR_STRUC, *PHOST_CMD_CSR_STRUC;
-
-/* */
-/* AIFSN_CSR: AIFSN for each EDCA AC */
-/* */
-
-/* */
-/* E2PROM_CSR: EEPROM control register */
-/* */
-typedef union _E2PROM_CSR_STRUC {
- struct {
- u32 Reload:1; /* Reload EEPROM content, write one to reload, self-cleared. */
- u32 EepromSK:1;
- u32 EepromCS:1;
- u32 EepromDI:1;
- u32 EepromDO:1;
- u32 Type:1; /* 1: 93C46, 0:93C66 */
- u32 LoadStatus:1; /* 1:loading, 0:done */
- u32 Rsvd:25;
- } field;
- u32 word;
-} E2PROM_CSR_STRUC, *PE2PROM_CSR_STRUC;
-
-/* */
-/* QOS_CSR0: TXOP holder address0 register */
-/* */
-typedef union _QOS_CSR0_STRUC {
- struct {
- u8 Byte0; /* MAC address byte 0 */
- u8 Byte1; /* MAC address byte 1 */
- u8 Byte2; /* MAC address byte 2 */
- u8 Byte3; /* MAC address byte 3 */
- } field;
- u32 word;
-} QOS_CSR0_STRUC, *PQOS_CSR0_STRUC;
-
-/* */
-/* QOS_CSR1: TXOP holder address1 register */
-/* */
-typedef union _QOS_CSR1_STRUC {
- struct {
- u8 Byte4; /* MAC address byte 4 */
- u8 Byte5; /* MAC address byte 5 */
- u8 Rsvd0;
- u8 Rsvd1;
- } field;
- u32 word;
-} QOS_CSR1_STRUC, *PQOS_CSR1_STRUC;
-
-#define RF_CSR_CFG 0x500
-typedef union _RF_CSR_CFG_STRUC {
- struct {
- u32 RF_CSR_DATA:8; /* DATA */
- u32 TESTCSR_RFACC_REGNUM:5; /* RF register ID */
- u32 Rsvd2:3; /* Reserved */
- u32 RF_CSR_WR:1; /* 0: read 1: write */
- u32 RF_CSR_KICK:1; /* kick RF register read/write */
- u32 Rsvd1:14; /* Reserved */
- } field;
- u32 word;
-} RF_CSR_CFG_STRUC, *PRF_CSR_CFG_STRUC;
-
-/* */
-/* Other on-chip shared memory space, base = 0x2000 */
-/* */
-
-/* CIS space - base address = 0x2000 */
-#define HW_CIS_BASE 0x2000
-
-/* Carrier-sense CTS frame base address. It's where mac stores carrier-sense frame for carrier-sense function. */
-#define HW_CS_CTS_BASE 0x7700
-/* DFS CTS frame base address. It's where mac stores CTS frame for DFS. */
-#define HW_DFS_CTS_BASE 0x7780
-#define HW_CTS_FRAME_SIZE 0x80
-
-/* 2004-11-08 john - since NULL frame won't be that long (256 byte). We steal 16 tail bytes */
-/* to save debugging settings */
-#define HW_DEBUG_SETTING_BASE 0x77f0 /* 0x77f0~0x77ff total 16 bytes */
-#define HW_DEBUG_SETTING_BASE2 0x7770 /* 0x77f0~0x77ff total 16 bytes */
-
-/* In order to support maximum 8 MBSS and its maximum length is 512 for each beacon */
-/* Three section discontinue memory segments will be used. */
-/* 1. The original region for BCN 0~3 */
-/* 2. Extract memory from FCE table for BCN 4~5 */
-/* 3. Extract memory from Pair-wise key table for BCN 6~7 */
-/* It occupied those memory of wcid 238~253 for BCN 6 */
-/* and wcid 222~237 for BCN 7 */
-#define HW_BEACON_MAX_SIZE 0x1000 /* unit: byte */
-#define HW_BEACON_BASE0 0x7800
-#define HW_BEACON_BASE1 0x7A00
-#define HW_BEACON_BASE2 0x7C00
-#define HW_BEACON_BASE3 0x7E00
-#define HW_BEACON_BASE4 0x7200
-#define HW_BEACON_BASE5 0x7400
-#define HW_BEACON_BASE6 0x5DC0
-#define HW_BEACON_BASE7 0x5BC0
-
-#define HW_BEACON_MAX_COUNT 8
-#define HW_BEACON_OFFSET 0x0200
-#define HW_BEACON_CONTENT_LEN (HW_BEACON_OFFSET - TXWI_SIZE)
-
-/* HOST-MCU shared memory - base address = 0x2100 */
-#define HOST_CMD_CSR 0x404
-#define H2M_MAILBOX_CSR 0x7010
-#define H2M_MAILBOX_CID 0x7014
-#define H2M_MAILBOX_STATUS 0x701c
-#define H2M_INT_SRC 0x7024
-#define H2M_BBP_AGENT 0x7028
-#define M2H_CMD_DONE_CSR 0x000c
-#define MCU_TXOP_ARRAY_BASE 0x000c /* TODO: to be provided by Albert */
-#define MCU_TXOP_ENTRY_SIZE 32 /* TODO: to be provided by Albert */
-#define MAX_NUM_OF_TXOP_ENTRY 16 /* TODO: must be same with 8051 firmware */
-#define MCU_MBOX_VERSION 0x01 /* TODO: to be confirmed by Albert */
-#define MCU_MBOX_VERSION_OFFSET 5 /* TODO: to be provided by Albert */
-
-/* */
-/* Host DMA registers - base address 0x200 . TX0-3=EDCAQid0-3, TX4=HCCA, TX5=MGMT, */
-/* */
-/* */
-/* DMA RING DESCRIPTOR */
-/* */
-#define E2PROM_CSR 0x0004
-#define IO_CNTL_CSR 0x77d0
-
-/* ================================================================ */
-/* Tx / Rx / Mgmt ring descriptor definition */
-/* ================================================================ */
-
-/* the following PID values are used to mark outgoing frame type in TXD->PID so that */
-/* proper TX statistics can be collected based on these categories */
-/* b3-2 of PID field - */
-#define PID_MGMT 0x05
-#define PID_BEACON 0x0c
-#define PID_DATA_NORMALUCAST 0x02
-#define PID_DATA_AMPDU 0x04
-#define PID_DATA_NO_ACK 0x08
-#define PID_DATA_NOT_NORM_ACK 0x03
-/* value domain of pTxD->HostQId (4-bit: 0~15) */
-#define QID_AC_BK 1 /* meet ACI definition in 802.11e */
-#define QID_AC_BE 0 /* meet ACI definition in 802.11e */
-#define QID_AC_VI 2
-#define QID_AC_VO 3
-#define QID_HCCA 4
-#define NUM_OF_TX_RING 4
-#define QID_MGMT 13
-#define QID_RX 14
-#define QID_OTHER 15
-
-#endif /* __RTMP_MAC_H__ // */
diff --git a/drivers/staging/rt2860/chip/rtmp_phy.h b/drivers/staging/rt2860/chip/rtmp_phy.h
deleted file mode 100644
index a52221f..0000000
--- a/drivers/staging/rt2860/chip/rtmp_phy.h
+++ /dev/null
@@ -1,516 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- rtmp_phy.h
-
- Abstract:
- Ralink Wireless Chip PHY(BBP/RF) related definition & structures
-
- Revision History:
- Who When What
- -------- ---------- ----------------------------------------------
-*/
-
-#ifndef __RTMP_PHY_H__
-#define __RTMP_PHY_H__
-
-/*
- RF sections
-*/
-#define RF_R00 0
-#define RF_R01 1
-#define RF_R02 2
-#define RF_R03 3
-#define RF_R04 4
-#define RF_R05 5
-#define RF_R06 6
-#define RF_R07 7
-#define RF_R08 8
-#define RF_R09 9
-#define RF_R10 10
-#define RF_R11 11
-#define RF_R12 12
-#define RF_R13 13
-#define RF_R14 14
-#define RF_R15 15
-#define RF_R16 16
-#define RF_R17 17
-#define RF_R18 18
-#define RF_R19 19
-#define RF_R20 20
-#define RF_R21 21
-#define RF_R22 22
-#define RF_R23 23
-#define RF_R24 24
-#define RF_R25 25
-#define RF_R26 26
-#define RF_R27 27
-#define RF_R28 28
-#define RF_R29 29
-#define RF_R30 30
-#define RF_R31 31
-
-/* value domain of pAd->RfIcType */
-#define RFIC_2820 1 /* 2.4G 2T3R */
-#define RFIC_2850 2 /* 2.4G/5G 2T3R */
-#define RFIC_2720 3 /* 2.4G 1T2R */
-#define RFIC_2750 4 /* 2.4G/5G 1T2R */
-#define RFIC_3020 5 /* 2.4G 1T1R */
-#define RFIC_2020 6 /* 2.4G B/G */
-#define RFIC_3021 7 /* 2.4G 1T2R */
-#define RFIC_3022 8 /* 2.4G 2T2R */
-#define RFIC_3052 9 /* 2.4G/5G 2T2R */
-
-/*
- BBP sections
-*/
-#define BBP_R0 0 /* version */
-#define BBP_R1 1 /* TSSI */
-#define BBP_R2 2 /* TX configure */
-#define BBP_R3 3
-#define BBP_R4 4
-#define BBP_R5 5
-#define BBP_R6 6
-#define BBP_R14 14 /* RX configure */
-#define BBP_R16 16
-#define BBP_R17 17 /* RX sensibility */
-#define BBP_R18 18
-#define BBP_R21 21
-#define BBP_R22 22
-#define BBP_R24 24
-#define BBP_R25 25
-#define BBP_R26 26
-#define BBP_R27 27
-#define BBP_R31 31
-#define BBP_R49 49 /*TSSI */
-#define BBP_R50 50
-#define BBP_R51 51
-#define BBP_R52 52
-#define BBP_R55 55
-#define BBP_R62 62 /* Rx SQ0 Threshold HIGH */
-#define BBP_R63 63
-#define BBP_R64 64
-#define BBP_R65 65
-#define BBP_R66 66
-#define BBP_R67 67
-#define BBP_R68 68
-#define BBP_R69 69
-#define BBP_R70 70 /* Rx AGC SQ CCK Xcorr threshold */
-#define BBP_R73 73
-#define BBP_R75 75
-#define BBP_R77 77
-#define BBP_R78 78
-#define BBP_R79 79
-#define BBP_R80 80
-#define BBP_R81 81
-#define BBP_R82 82
-#define BBP_R83 83
-#define BBP_R84 84
-#define BBP_R86 86
-#define BBP_R91 91
-#define BBP_R92 92
-#define BBP_R94 94 /* Tx Gain Control */
-#define BBP_R103 103
-#define BBP_R105 105
-#define BBP_R106 106
-#define BBP_R113 113
-#define BBP_R114 114
-#define BBP_R115 115
-#define BBP_R116 116
-#define BBP_R117 117
-#define BBP_R118 118
-#define BBP_R119 119
-#define BBP_R120 120
-#define BBP_R121 121
-#define BBP_R122 122
-#define BBP_R123 123
-#ifdef RT30xx
-#define BBP_R138 138 /* add by johnli, RF power sequence setup, ADC dynamic on/off control */
-#endif /* RT30xx // */
-
-#define BBPR94_DEFAULT 0x06 /* Add 1 value will gain 1db */
-
-/* */
-/* BBP & RF are using indirect access. Before write any value into it. */
-/* We have to make sure there is no outstanding command pending via checking busy bit. */
-/* */
-#define MAX_BUSY_COUNT 100 /* Number of retry before failing access BBP & RF indirect register */
-
-/*#define PHY_TR_SWITCH_TIME 5 // usec */
-
-/*#define BBP_R17_LOW_SENSIBILITY 0x50 */
-/*#define BBP_R17_MID_SENSIBILITY 0x41 */
-/*#define BBP_R17_DYNAMIC_UP_BOUND 0x40 */
-
-#define RSSI_FOR_VERY_LOW_SENSIBILITY -35
-#define RSSI_FOR_LOW_SENSIBILITY -58
-#define RSSI_FOR_MID_LOW_SENSIBILITY -80
-#define RSSI_FOR_MID_SENSIBILITY -90
-
-/*****************************************************************************
- RF register Read/Write marco definition
- *****************************************************************************/
-#ifdef RTMP_MAC_PCI
-#define RTMP_RF_IO_WRITE32(_A, _V) \
-{ \
- if ((_A)->bPCIclkOff == FALSE) { \
- PHY_CSR4_STRUC _value; \
- unsigned long _busyCnt = 0; \
- \
- do { \
- RTMP_IO_READ32((_A), RF_CSR_CFG0, &_value.word); \
- if (_value.field.Busy == IDLE) \
- break; \
- _busyCnt++; \
- } while (_busyCnt < MAX_BUSY_COUNT); \
- if (_busyCnt < MAX_BUSY_COUNT) { \
- RTMP_IO_WRITE32((_A), RF_CSR_CFG0, (_V)); \
- } \
- } \
-}
-#endif /* RTMP_MAC_PCI // */
-#ifdef RTMP_MAC_USB
-#define RTMP_RF_IO_WRITE32(_A, _V) RTUSBWriteRFRegister(_A, _V)
-#endif /* RTMP_MAC_USB // */
-
-#ifdef RT30xx
-#define RTMP_RF_IO_READ8_BY_REG_ID(_A, _I, _pV) RT30xxReadRFRegister(_A, _I, _pV)
-#define RTMP_RF_IO_WRITE8_BY_REG_ID(_A, _I, _V) RT30xxWriteRFRegister(_A, _I, _V)
-#endif /* RT30xx // */
-
-/*****************************************************************************
- BBP register Read/Write marco definitions.
- we read/write the bbp value by register's ID.
- Generate PER to test BA
- *****************************************************************************/
-#ifdef RTMP_MAC_PCI
-/*
- basic marco for BBP read operation.
- _pAd: the data structure pointer of struct rt_rtmp_adapter
- _bbpID : the bbp register ID
- _pV: data pointer used to save the value of queried bbp register.
- _bViaMCU: if we need access the bbp via the MCU.
-*/
-#define RTMP_BBP_IO_READ8(_pAd, _bbpID, _pV, _bViaMCU) \
- do { \
- BBP_CSR_CFG_STRUC BbpCsr; \
- int _busyCnt, _secCnt, _regID; \
- \
- _regID = ((_bViaMCU) == TRUE ? H2M_BBP_AGENT : BBP_CSR_CFG); \
- for (_busyCnt = 0; _busyCnt < MAX_BUSY_COUNT; _busyCnt++) { \
- RTMP_IO_READ32(_pAd, _regID, &BbpCsr.word); \
- if (BbpCsr.field.Busy == BUSY) \
- continue; \
- BbpCsr.word = 0; \
- BbpCsr.field.fRead = 1; \
- BbpCsr.field.BBP_RW_MODE = 1; \
- BbpCsr.field.Busy = 1; \
- BbpCsr.field.RegNum = _bbpID; \
- RTMP_IO_WRITE32(_pAd, _regID, BbpCsr.word); \
- if ((_bViaMCU) == TRUE) { \
- AsicSendCommandToMcu(_pAd, 0x80, 0xff, 0x0, 0x0); \
- RTMPusecDelay(1000); \
- } \
- for (_secCnt = 0; _secCnt < MAX_BUSY_COUNT; _secCnt++) { \
- RTMP_IO_READ32(_pAd, _regID, &BbpCsr.word); \
- if (BbpCsr.field.Busy == IDLE) \
- break; \
- } \
- if ((BbpCsr.field.Busy == IDLE) && \
- (BbpCsr.field.RegNum == _bbpID)) { \
- *(_pV) = (u8)BbpCsr.field.Value; \
- break; \
- } \
- } \
- if (BbpCsr.field.Busy == BUSY) { \
- DBGPRINT_ERR("BBP(viaMCU=%d) read R%d fail\n", (_bViaMCU), _bbpID); \
- *(_pV) = (_pAd)->BbpWriteLatch[_bbpID]; \
- if ((_bViaMCU) == TRUE) { \
- RTMP_IO_READ32(_pAd, _regID, &BbpCsr.word); \
- BbpCsr.field.Busy = 0; \
- RTMP_IO_WRITE32(_pAd, _regID, BbpCsr.word); \
- } \
- } \
- } while (0)
-
-/*
- This marco used for the BBP read operation which didn't need via MCU.
-*/
-#define BBP_IO_READ8_BY_REG_ID(_A, _I, _pV) \
- RTMP_BBP_IO_READ8((_A), (_I), (_pV), FALSE)
-
-/*
- This marco used for the BBP read operation which need via MCU.
- But for some chipset which didn't have mcu (e.g., RBUS based chipset), we
- will use this function too and didn't access the bbp register via the MCU.
-*/
-/* Read BBP register by register's ID. Generate PER to test BA */
-#define RTMP_BBP_IO_READ8_BY_REG_ID(_A, _I, _pV) \
-{ \
- BBP_CSR_CFG_STRUC BbpCsr; \
- int i, k; \
- BOOLEAN brc; \
- BbpCsr.field.Busy = IDLE; \
- if ((IS_RT3090((_A)) || IS_RT3572((_A)) || IS_RT3390((_A))) \
- && ((_A)->StaCfg.PSControl.field.rt30xxPowerMode == 3) \
- && ((_A)->StaCfg.PSControl.field.EnableNewPS == TRUE) \
- && ((_A)->bPCIclkOff == FALSE) \
- && ((_A)->brt30xxBanMcuCmd == FALSE)) { \
- for (i = 0; i < MAX_BUSY_COUNT; i++) { \
- RTMP_IO_READ32(_A, H2M_BBP_AGENT, &BbpCsr.word); \
- if (BbpCsr.field.Busy == BUSY) { \
- continue; \
- } \
- BbpCsr.word = 0; \
- BbpCsr.field.fRead = 1; \
- BbpCsr.field.BBP_RW_MODE = 1; \
- BbpCsr.field.Busy = 1; \
- BbpCsr.field.RegNum = _I; \
- RTMP_IO_WRITE32(_A, H2M_BBP_AGENT, BbpCsr.word); \
- brc = AsicSendCommandToMcu(_A, 0x80, 0xff, 0x0, 0x0); \
- if (brc == TRUE) { \
- for (k = 0; k < MAX_BUSY_COUNT; k++) { \
- RTMP_IO_READ32(_A, H2M_BBP_AGENT, &BbpCsr.word); \
- if (BbpCsr.field.Busy == IDLE) \
- break; \
- } \
- if ((BbpCsr.field.Busy == IDLE) && \
- (BbpCsr.field.RegNum == _I)) { \
- *(_pV) = (u8)BbpCsr.field.Value; \
- break; \
- } \
- } else { \
- BbpCsr.field.Busy = 0; \
- RTMP_IO_WRITE32(_A, H2M_BBP_AGENT, BbpCsr.word); \
- } \
- } \
- } \
- else if (!((IS_RT3090((_A)) || IS_RT3572((_A)) || IS_RT3390((_A))) && ((_A)->StaCfg.PSControl.field.rt30xxPowerMode == 3) \
- && ((_A)->StaCfg.PSControl.field.EnableNewPS == TRUE)) \
- && ((_A)->bPCIclkOff == FALSE)) { \
- for (i = 0; i < MAX_BUSY_COUNT; i++) { \
- RTMP_IO_READ32(_A, H2M_BBP_AGENT, &BbpCsr.word); \
- if (BbpCsr.field.Busy == BUSY) { \
- continue; \
- } \
- BbpCsr.word = 0; \
- BbpCsr.field.fRead = 1; \
- BbpCsr.field.BBP_RW_MODE = 1; \
- BbpCsr.field.Busy = 1; \
- BbpCsr.field.RegNum = _I; \
- RTMP_IO_WRITE32(_A, H2M_BBP_AGENT, BbpCsr.word); \
- AsicSendCommandToMcu(_A, 0x80, 0xff, 0x0, 0x0); \
- for (k = 0; k < MAX_BUSY_COUNT; k++) { \
- RTMP_IO_READ32(_A, H2M_BBP_AGENT, &BbpCsr.word); \
- if (BbpCsr.field.Busy == IDLE) \
- break; \
- } \
- if ((BbpCsr.field.Busy == IDLE) && \
- (BbpCsr.field.RegNum == _I)) { \
- *(_pV) = (u8)BbpCsr.field.Value; \
- break; \
- } \
- } \
- } else { \
- DBGPRINT_ERR(" , brt30xxBanMcuCmd = %d, Read BBP %d \n", (_A)->brt30xxBanMcuCmd, (_I)); \
- *(_pV) = (_A)->BbpWriteLatch[_I]; \
- } \
- if ((BbpCsr.field.Busy == BUSY) || ((_A)->bPCIclkOff == TRUE)) { \
- DBGPRINT_ERR("BBP read R%d=0x%x fail\n", _I, BbpCsr.word); \
- *(_pV) = (_A)->BbpWriteLatch[_I]; \
- } \
-}
-
-/*
- basic marco for BBP write operation.
- _pAd: the data structure pointer of struct rt_rtmp_adapter
- _bbpID : the bbp register ID
- _pV: data used to save the value of queried bbp register.
- _bViaMCU: if we need access the bbp via the MCU.
-*/
-#define RTMP_BBP_IO_WRITE8(_pAd, _bbpID, _pV, _bViaMCU) \
- do { \
- BBP_CSR_CFG_STRUC BbpCsr; \
- int _busyCnt, _regID; \
- \
- _regID = ((_bViaMCU) == TRUE ? H2M_BBP_AGENT : BBP_CSR_CFG); \
- for (_busyCnt = 0; _busyCnt < MAX_BUSY_COUNT; _busyCnt++) { \
- RTMP_IO_READ32((_pAd), BBP_CSR_CFG, &BbpCsr.word); \
- if (BbpCsr.field.Busy == BUSY) \
- continue; \
- BbpCsr.word = 0; \
- BbpCsr.field.fRead = 0; \
- BbpCsr.field.BBP_RW_MODE = 1; \
- BbpCsr.field.Busy = 1; \
- BbpCsr.field.Value = _pV; \
- BbpCsr.field.RegNum = _bbpID; \
- RTMP_IO_WRITE32((_pAd), BBP_CSR_CFG, BbpCsr.word); \
- if ((_bViaMCU) == TRUE) { \
- AsicSendCommandToMcu(_pAd, 0x80, 0xff, 0x0, 0x0); \
- if ((_pAd)->OpMode == OPMODE_AP) \
- RTMPusecDelay(1000); \
- } \
- (_pAd)->BbpWriteLatch[_bbpID] = _pV; \
- break; \
- } \
- if (_busyCnt == MAX_BUSY_COUNT) { \
- DBGPRINT_ERR("BBP write R%d fail\n", _bbpID); \
- if ((_bViaMCU) == TRUE) { \
- RTMP_IO_READ32(_pAd, H2M_BBP_AGENT, &BbpCsr.word); \
- BbpCsr.field.Busy = 0; \
- RTMP_IO_WRITE32(_pAd, H2M_BBP_AGENT, BbpCsr.word); \
- } \
- } \
- } while (0)
-
-/*
- This marco used for the BBP write operation which didn't need via MCU.
-*/
-#define BBP_IO_WRITE8_BY_REG_ID(_A, _I, _pV) \
- RTMP_BBP_IO_WRITE8((_A), (_I), (_pV), FALSE)
-
-/*
- This marco used for the BBP write operation which need via MCU.
- But for some chipset which didn't have mcu (e.g., RBUS based chipset), we
- will use this function too and didn't access the bbp register via the MCU.
-*/
-/* Write BBP register by register's ID & value */
-#define RTMP_BBP_IO_WRITE8_BY_REG_ID(_A, _I, _V) \
-{ \
- BBP_CSR_CFG_STRUC BbpCsr; \
- int BusyCnt = 0; \
- BOOLEAN brc; \
- if (_I < MAX_NUM_OF_BBP_LATCH) { \
- if ((IS_RT3090((_A)) || IS_RT3572((_A)) || IS_RT3390((_A))) \
- && ((_A)->StaCfg.PSControl.field.rt30xxPowerMode == 3) \
- && ((_A)->StaCfg.PSControl.field.EnableNewPS == TRUE) \
- && ((_A)->bPCIclkOff == FALSE) \
- && ((_A)->brt30xxBanMcuCmd == FALSE)) { \
- if (_A->AccessBBPFailCount > 20) { \
- AsicResetBBPAgent(_A); \
- _A->AccessBBPFailCount = 0; \
- } \
- for (BusyCnt = 0; BusyCnt < MAX_BUSY_COUNT; BusyCnt++) { \
- RTMP_IO_READ32(_A, H2M_BBP_AGENT, &BbpCsr.word); \
- if (BbpCsr.field.Busy == BUSY) \
- continue; \
- BbpCsr.word = 0; \
- BbpCsr.field.fRead = 0; \
- BbpCsr.field.BBP_RW_MODE = 1; \
- BbpCsr.field.Busy = 1; \
- BbpCsr.field.Value = _V; \
- BbpCsr.field.RegNum = _I; \
- RTMP_IO_WRITE32(_A, H2M_BBP_AGENT, BbpCsr.word); \
- brc = AsicSendCommandToMcu(_A, 0x80, 0xff, 0x0, 0x0); \
- if (brc == TRUE) { \
- (_A)->BbpWriteLatch[_I] = _V; \
- } else { \
- BbpCsr.field.Busy = 0; \
- RTMP_IO_WRITE32(_A, H2M_BBP_AGENT, BbpCsr.word); \
- } \
- break; \
- } \
- } \
- else if (!((IS_RT3090((_A)) || IS_RT3572((_A)) || IS_RT3390((_A))) \
- && ((_A)->StaCfg.PSControl.field.rt30xxPowerMode == 3) \
- && ((_A)->StaCfg.PSControl.field.EnableNewPS == TRUE)) \
- && ((_A)->bPCIclkOff == FALSE)) { \
- if (_A->AccessBBPFailCount > 20) { \
- AsicResetBBPAgent(_A); \
- _A->AccessBBPFailCount = 0; \
- } \
- for (BusyCnt = 0; BusyCnt < MAX_BUSY_COUNT; BusyCnt++) { \
- RTMP_IO_READ32(_A, H2M_BBP_AGENT, &BbpCsr.word); \
- if (BbpCsr.field.Busy == BUSY) \
- continue; \
- BbpCsr.word = 0; \
- BbpCsr.field.fRead = 0; \
- BbpCsr.field.BBP_RW_MODE = 1; \
- BbpCsr.field.Busy = 1; \
- BbpCsr.field.Value = _V; \
- BbpCsr.field.RegNum = _I; \
- RTMP_IO_WRITE32(_A, H2M_BBP_AGENT, BbpCsr.word); \
- AsicSendCommandToMcu(_A, 0x80, 0xff, 0x0, 0x0); \
- (_A)->BbpWriteLatch[_I] = _V; \
- break; \
- } \
- } else { \
- DBGPRINT_ERR(" brt30xxBanMcuCmd = %d. Write BBP %d \n", (_A)->brt30xxBanMcuCmd, (_I)); \
- } \
- if ((BusyCnt == MAX_BUSY_COUNT) || ((_A)->bPCIclkOff == TRUE)) { \
- if (BusyCnt == MAX_BUSY_COUNT) \
- (_A)->AccessBBPFailCount++; \
- DBGPRINT_ERR("BBP write R%d=0x%x fail. BusyCnt= %d.bPCIclkOff = %d. \n", _I, BbpCsr.word, BusyCnt, (_A)->bPCIclkOff); \
- } \
- } else { \
- DBGPRINT_ERR("****** BBP_Write_Latch Buffer exceeds max boundary ****** \n"); \
- } \
-}
-#endif /* RTMP_MAC_PCI // */
-
-#ifdef RTMP_MAC_USB
-#define RTMP_BBP_IO_READ8_BY_REG_ID(_A, _I, _pV) RTUSBReadBBPRegister(_A, _I, _pV)
-#define RTMP_BBP_IO_WRITE8_BY_REG_ID(_A, _I, _V) RTUSBWriteBBPRegister(_A, _I, _V)
-
-#define BBP_IO_WRITE8_BY_REG_ID(_A, _I, _V) RTUSBWriteBBPRegister(_A, _I, _V)
-#define BBP_IO_READ8_BY_REG_ID(_A, _I, _pV) RTUSBReadBBPRegister(_A, _I, _pV)
-#endif /* RTMP_MAC_USB // */
-
-#ifdef RT30xx
-#define RTMP_ASIC_MMPS_DISABLE(_pAd) \
- do { \
- u32 _macData; \
- u8 _bbpData = 0; \
- /* disable MMPS BBP control register */ \
- RTMP_BBP_IO_READ8_BY_REG_ID(_pAd, BBP_R3, &_bbpData); \
- _bbpData &= ~(0x04); /*bit 2*/ \
- RTMP_BBP_IO_WRITE8_BY_REG_ID(_pAd, BBP_R3, _bbpData); \
- \
- /* disable MMPS MAC control register */ \
- RTMP_IO_READ32(_pAd, 0x1210, &_macData); \
- _macData &= ~(0x09); /*bit 0, 3*/ \
- RTMP_IO_WRITE32(_pAd, 0x1210, _macData); \
- } while (0)
-
-#define RTMP_ASIC_MMPS_ENABLE(_pAd) \
- do { \
- u32 _macData; \
- u8 _bbpData = 0; \
- /* enable MMPS BBP control register */ \
- RTMP_BBP_IO_READ8_BY_REG_ID(_pAd, BBP_R3, &_bbpData); \
- _bbpData |= (0x04); /*bit 2*/ \
- RTMP_BBP_IO_WRITE8_BY_REG_ID(_pAd, BBP_R3, _bbpData); \
- \
- /* enable MMPS MAC control register */ \
- RTMP_IO_READ32(_pAd, 0x1210, &_macData); \
- _macData |= (0x09); /*bit 0, 3*/ \
- RTMP_IO_WRITE32(_pAd, 0x1210, _macData); \
- } while (0)
-
-#endif /* RT30xx // */
-
-#endif /* __RTMP_PHY_H__ // */
diff --git a/drivers/staging/rt2860/chips/rt3070.c b/drivers/staging/rt2860/chips/rt3070.c
deleted file mode 100644
index 3a17fd1..0000000
--- a/drivers/staging/rt2860/chips/rt3070.c
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- rt3070.c
-
- Abstract:
- Specific funcitons and variables for RT3070
-
- Revision History:
- Who When What
- -------- ---------- ----------------------------------------------
-*/
-
-#ifdef RT3070
-
-#include "../rt_config.h"
-
-#ifndef RTMP_RF_RW_SUPPORT
-#error "You Should Enable compile flag RTMP_RF_RW_SUPPORT for this chip"
-#endif /* RTMP_RF_RW_SUPPORT // */
-
-void NICInitRT3070RFRegisters(struct rt_rtmp_adapter *pAd)
-{
- int i;
- u8 RFValue;
-
- /* Driver must read EEPROM to get RfIcType before initial RF registers */
- /* Initialize RF register to default value */
- if (IS_RT3070(pAd) || IS_RT3071(pAd)) {
- /* Init RF calibration */
- /* Driver should toggle RF R30 bit7 before init RF registers */
- u32 RfReg = 0;
- u32 data;
-
- RT30xxReadRFRegister(pAd, RF_R30, (u8 *)&RfReg);
- RfReg |= 0x80;
- RT30xxWriteRFRegister(pAd, RF_R30, (u8)RfReg);
- RTMPusecDelay(1000);
- RfReg &= 0x7F;
- RT30xxWriteRFRegister(pAd, RF_R30, (u8)RfReg);
-
- /* Initialize RF register to default value */
- for (i = 0; i < NUM_RF_REG_PARMS; i++) {
- RT30xxWriteRFRegister(pAd,
- RT30xx_RFRegTable[i].Register,
- RT30xx_RFRegTable[i].Value);
- }
-
- /* add by johnli */
- if (IS_RT3070(pAd)) {
- /* */
- /* The DAC issue(LDO_CFG0) has been fixed in RT3070(F). */
- /* The voltage raising patch is no longer needed for RT3070(F) */
- /* */
- if ((pAd->MACVersion & 0xffff) < 0x0201) {
- /* Update MAC 0x05D4 from 01xxxxxx to 0Dxxxxxx (voltage 1.2V to 1.35V) for RT3070 to improve yield rate */
- RTUSBReadMACRegister(pAd, LDO_CFG0, &data);
- data = ((data & 0xF0FFFFFF) | 0x0D000000);
- RTUSBWriteMACRegister(pAd, LDO_CFG0, data);
- }
- } else if (IS_RT3071(pAd)) {
- /* Driver should set RF R6 bit6 on before init RF registers */
- RT30xxReadRFRegister(pAd, RF_R06, (u8 *)&RfReg);
- RfReg |= 0x40;
- RT30xxWriteRFRegister(pAd, RF_R06, (u8)RfReg);
-
- /* init R31 */
- RT30xxWriteRFRegister(pAd, RF_R31, 0x14);
-
- /* RT3071 version E has fixed this issue */
- if ((pAd->NicConfig2.field.DACTestBit == 1)
- && ((pAd->MACVersion & 0xffff) < 0x0211)) {
- /* patch tx EVM issue temporarily */
- RTUSBReadMACRegister(pAd, LDO_CFG0, &data);
- data = ((data & 0xE0FFFFFF) | 0x0D000000);
- RTUSBWriteMACRegister(pAd, LDO_CFG0, data);
- } else {
- RTMP_IO_READ32(pAd, LDO_CFG0, &data);
- data = ((data & 0xE0FFFFFF) | 0x01000000);
- RTMP_IO_WRITE32(pAd, LDO_CFG0, data);
- }
-
- /* patch LNA_PE_G1 failed issue */
- RTUSBReadMACRegister(pAd, GPIO_SWITCH, &data);
- data &= ~(0x20);
- RTUSBWriteMACRegister(pAd, GPIO_SWITCH, data);
- }
- /*For RF filter Calibration */
- RTMPFilterCalibration(pAd);
-
- /* Initialize RF R27 register, set RF R27 must be behind RTMPFilterCalibration() */
- /* */
- /* TX to RX IQ glitch(RF_R27) has been fixed in RT3070(F). */
- /* Raising RF voltage is no longer needed for RT3070(F) */
- /* */
- if ((IS_RT3070(pAd)) && ((pAd->MACVersion & 0xffff) < 0x0201)) {
- RT30xxWriteRFRegister(pAd, RF_R27, 0x3);
- } else if ((IS_RT3071(pAd))
- && ((pAd->MACVersion & 0xffff) < 0x0211)) {
- RT30xxWriteRFRegister(pAd, RF_R27, 0x3);
- }
- /* set led open drain enable */
- RTUSBReadMACRegister(pAd, OPT_14, &data);
- data |= 0x01;
- RTUSBWriteMACRegister(pAd, OPT_14, data);
-
- /* move from RT30xxLoadRFNormalModeSetup because it's needed for both RT3070 and RT3071 */
- /* TX_LO1_en, RF R17 register Bit 3 to 0 */
- RT30xxReadRFRegister(pAd, RF_R17, &RFValue);
- RFValue &= (~0x08);
- /* to fix rx long range issue */
- if (pAd->NicConfig2.field.ExternalLNAForG == 0) {
- if ((IS_RT3071(pAd)
- && ((pAd->MACVersion & 0xffff) >= 0x0211))
- || IS_RT3070(pAd)) {
- RFValue |= 0x20;
- }
- }
- /* set RF_R17_bit[2:0] equal to EEPROM setting at 0x48h */
- if (pAd->TxMixerGain24G >= 1) {
- RFValue &= (~0x7); /* clean bit [2:0] */
- RFValue |= pAd->TxMixerGain24G;
- }
- RT30xxWriteRFRegister(pAd, RF_R17, RFValue);
-
- if (IS_RT3071(pAd)) {
- /* add by johnli, RF power sequence setup, load RF normal operation-mode setup */
- RT30xxLoadRFNormalModeSetup(pAd);
- } else if (IS_RT3070(pAd)) {
- /* add by johnli, reset RF_R27 when interface down & up to fix throughput problem */
- /* LDORF_VC, RF R27 register Bit 2 to 0 */
- RT30xxReadRFRegister(pAd, RF_R27, &RFValue);
- /* TX to RX IQ glitch(RF_R27) has been fixed in RT3070(F). */
- /* Raising RF voltage is no longer needed for RT3070(F) */
- if ((pAd->MACVersion & 0xffff) < 0x0201)
- RFValue = (RFValue & (~0x77)) | 0x3;
- else
- RFValue = (RFValue & (~0x77));
- RT30xxWriteRFRegister(pAd, RF_R27, RFValue);
- /* end johnli */
- }
- }
-
-}
-#endif /* RT3070 // */
diff --git a/drivers/staging/rt2860/chips/rt3090.c b/drivers/staging/rt2860/chips/rt3090.c
deleted file mode 100644
index 334720e..0000000
--- a/drivers/staging/rt2860/chips/rt3090.c
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- rt3090.c
-
- Abstract:
- Specific functions and variables for RT3070
-
- Revision History:
- Who When What
- Justin P. Mattock 11/07/2010 Fix a typo
- -------- ---------- ----------------------------------------------
-*/
-
-#ifdef RT3090
-
-#include "../rt_config.h"
-
-#ifndef RTMP_RF_RW_SUPPORT
-#error "You Should Enable compile flag RTMP_RF_RW_SUPPORT for this chip"
-#endif /* RTMP_RF_RW_SUPPORT // */
-
-void NICInitRT3090RFRegisters(struct rt_rtmp_adapter *pAd)
-{
- int i;
- /* Driver must read EEPROM to get RfIcType before initial RF registers */
- /* Initialize RF register to default value */
- if (IS_RT3090(pAd)) {
- /* Init RF calibration */
- /* Driver should toggle RF R30 bit7 before init RF registers */
- u8 RfReg;
- u32 data;
-
- RT30xxReadRFRegister(pAd, RF_R30, (u8 *)&RfReg);
- RfReg |= 0x80;
- RT30xxWriteRFRegister(pAd, RF_R30, (u8)RfReg);
- RTMPusecDelay(1000);
- RfReg &= 0x7F;
- RT30xxWriteRFRegister(pAd, RF_R30, (u8)RfReg);
-
- /* init R24, R31 */
- RT30xxWriteRFRegister(pAd, RF_R24, 0x0F);
- RT30xxWriteRFRegister(pAd, RF_R31, 0x0F);
-
- /* RT309x version E has fixed this issue */
- if ((pAd->NicConfig2.field.DACTestBit == 1)
- && ((pAd->MACVersion & 0xffff) < 0x0211)) {
- /* patch tx EVM issue temporarily */
- RTMP_IO_READ32(pAd, LDO_CFG0, &data);
- data = ((data & 0xE0FFFFFF) | 0x0D000000);
- RTMP_IO_WRITE32(pAd, LDO_CFG0, data);
- } else {
- RTMP_IO_READ32(pAd, LDO_CFG0, &data);
- data = ((data & 0xE0FFFFFF) | 0x01000000);
- RTMP_IO_WRITE32(pAd, LDO_CFG0, data);
- }
-
- /* patch LNA_PE_G1 failed issue */
- RTMP_IO_READ32(pAd, GPIO_SWITCH, &data);
- data &= ~(0x20);
- RTMP_IO_WRITE32(pAd, GPIO_SWITCH, data);
-
- /* Initialize RF register to default value */
- for (i = 0; i < NUM_RF_REG_PARMS; i++) {
- RT30xxWriteRFRegister(pAd,
- RT30xx_RFRegTable[i].Register,
- RT30xx_RFRegTable[i].Value);
- }
-
- /* Driver should set RF R6 bit6 on before calibration */
- RT30xxReadRFRegister(pAd, RF_R06, (u8 *)&RfReg);
- RfReg |= 0x40;
- RT30xxWriteRFRegister(pAd, RF_R06, (u8)RfReg);
-
- /*For RF filter Calibration */
- RTMPFilterCalibration(pAd);
-
- /* Initialize RF R27 register, set RF R27 must be behind RTMPFilterCalibration() */
- if ((pAd->MACVersion & 0xffff) < 0x0211)
- RT30xxWriteRFRegister(pAd, RF_R27, 0x3);
-
- /* set led open drain enable */
- RTMP_IO_READ32(pAd, OPT_14, &data);
- data |= 0x01;
- RTMP_IO_WRITE32(pAd, OPT_14, data);
-
- /* set default antenna as main */
- if (pAd->RfIcType == RFIC_3020)
- AsicSetRxAnt(pAd, pAd->RxAnt.Pair1PrimaryRxAnt);
-
- /* add by johnli, RF power sequence setup, load RF normal operation-mode setup */
- RT30xxLoadRFNormalModeSetup(pAd);
- }
-
-}
-
-#endif /* RT3090 // */
diff --git a/drivers/staging/rt2860/chips/rt30xx.c b/drivers/staging/rt2860/chips/rt30xx.c
deleted file mode 100644
index 354debf..0000000
--- a/drivers/staging/rt2860/chips/rt30xx.c
+++ /dev/null
@@ -1,516 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- rt30xx.c
-
- Abstract:
- Specific functions and variables for RT30xx.
-
- Revision History:
- Who When What
- Justin P. Mattock 11/07/2010 Fix some typos
- -------- ---------- ----------------------------------------------
-*/
-
-#ifdef RT30xx
-
-#ifndef RTMP_RF_RW_SUPPORT
-#error "You Should Enable compile flag RTMP_RF_RW_SUPPORT for this chip"
-#endif /* RTMP_RF_RW_SUPPORT // */
-
-#include "../rt_config.h"
-
-/* */
-/* RF register initialization set */
-/* */
-struct rt_reg_pair RT30xx_RFRegTable[] = {
- {RF_R04, 0x40}
- ,
- {RF_R05, 0x03}
- ,
- {RF_R06, 0x02}
- ,
- {RF_R07, 0x60}
- ,
- {RF_R09, 0x0F}
- ,
- {RF_R10, 0x41}
- ,
- {RF_R11, 0x21}
- ,
- {RF_R12, 0x7B}
- ,
- {RF_R14, 0x90}
- ,
- {RF_R15, 0x58}
- ,
- {RF_R16, 0xB3}
- ,
- {RF_R17, 0x92}
- ,
- {RF_R18, 0x2C}
- ,
- {RF_R19, 0x02}
- ,
- {RF_R20, 0xBA}
- ,
- {RF_R21, 0xDB}
- ,
- {RF_R24, 0x16}
- ,
- {RF_R25, 0x01}
- ,
- {RF_R29, 0x1F}
- ,
-};
-
-u8 NUM_RF_REG_PARMS = (sizeof(RT30xx_RFRegTable) / sizeof(struct rt_reg_pair));
-
-/* Antenna diversity use GPIO3 and EESK pin for control */
-/* Antenna and EEPROM access are both using EESK pin, */
-/* Therefor we should avoid accessing EESK at the same time */
-/* Then restore antenna after EEPROM access */
-/* The original name of this function is AsicSetRxAnt(), now change to */
-/*void AsicSetRxAnt( */
-void RT30xxSetRxAnt(struct rt_rtmp_adapter *pAd, u8 Ant)
-{
- u32 Value;
-#ifdef RTMP_MAC_PCI
- u32 x;
-#endif
-
- if ((pAd->EepromAccess) ||
- (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_RESET_IN_PROGRESS)) ||
- (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS)) ||
- (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_RADIO_OFF)) ||
- (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST))) {
- return;
- }
- /* the antenna selection is through firmware and MAC register(GPIO3) */
- if (Ant == 0) {
- /* Main antenna */
-#ifdef RTMP_MAC_PCI
- RTMP_IO_READ32(pAd, E2PROM_CSR, &x);
- x |= (EESK);
- RTMP_IO_WRITE32(pAd, E2PROM_CSR, x);
-#else
- AsicSendCommandToMcu(pAd, 0x73, 0xFF, 0x1, 0x0);
-#endif /* RTMP_MAC_PCI // */
-
- RTMP_IO_READ32(pAd, GPIO_CTRL_CFG, &Value);
- Value &= ~(0x0808);
- RTMP_IO_WRITE32(pAd, GPIO_CTRL_CFG, Value);
- DBGPRINT_RAW(RT_DEBUG_TRACE,
- ("AsicSetRxAnt, switch to main antenna\n"));
- } else {
- /* Aux antenna */
-#ifdef RTMP_MAC_PCI
- RTMP_IO_READ32(pAd, E2PROM_CSR, &x);
- x &= ~(EESK);
- RTMP_IO_WRITE32(pAd, E2PROM_CSR, x);
-#else
- AsicSendCommandToMcu(pAd, 0x73, 0xFF, 0x0, 0x0);
-#endif /* RTMP_MAC_PCI // */
- RTMP_IO_READ32(pAd, GPIO_CTRL_CFG, &Value);
- Value &= ~(0x0808);
- Value |= 0x08;
- RTMP_IO_WRITE32(pAd, GPIO_CTRL_CFG, Value);
- DBGPRINT_RAW(RT_DEBUG_TRACE,
- ("AsicSetRxAnt, switch to aux antenna\n"));
- }
-}
-
-/*
- ========================================================================
-
- Routine Description:
- For RF filter calibration purpose
-
- Arguments:
- pAd Pointer to our adapter
-
- Return Value:
- None
-
- IRQL = PASSIVE_LEVEL
-
- ========================================================================
-*/
-void RTMPFilterCalibration(struct rt_rtmp_adapter *pAd)
-{
- u8 R55x = 0, value, FilterTarget = 0x1E, BBPValue = 0;
- u32 loop = 0, count = 0, loopcnt = 0, ReTry = 0;
- u8 RF_R24_Value = 0;
-
- /* Give bbp filter initial value */
- pAd->Mlme.CaliBW20RfR24 = 0x1F;
- pAd->Mlme.CaliBW40RfR24 = 0x2F; /*Bit[5] must be 1 for BW 40 */
-
- do {
- if (loop == 1) { /*BandWidth = 40 MHz */
- /* Write 0x27 to RF_R24 to program filter */
- RF_R24_Value = 0x27;
- RT30xxWriteRFRegister(pAd, RF_R24, RF_R24_Value);
- if (IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd))
- FilterTarget = 0x15;
- else
- FilterTarget = 0x19;
-
- /* when calibrate BW40, BBP mask must set to BW40. */
- RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &BBPValue);
- BBPValue &= (~0x18);
- BBPValue |= (0x10);
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, BBPValue);
-
- /* set to BW40 */
- RT30xxReadRFRegister(pAd, RF_R31, &value);
- value |= 0x20;
- RT30xxWriteRFRegister(pAd, RF_R31, value);
- } else { /*BandWidth = 20 MHz */
- /* Write 0x07 to RF_R24 to program filter */
- RF_R24_Value = 0x07;
- RT30xxWriteRFRegister(pAd, RF_R24, RF_R24_Value);
- if (IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd))
- FilterTarget = 0x13;
- else
- FilterTarget = 0x16;
-
- /* set to BW20 */
- RT30xxReadRFRegister(pAd, RF_R31, &value);
- value &= (~0x20);
- RT30xxWriteRFRegister(pAd, RF_R31, value);
- }
-
- /* Write 0x01 to RF_R22 to enable baseband loopback mode */
- RT30xxReadRFRegister(pAd, RF_R22, &value);
- value |= 0x01;
- RT30xxWriteRFRegister(pAd, RF_R22, value);
-
- /* Write 0x00 to BBP_R24 to set power & frequency of passband test tone */
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R24, 0);
-
- do {
- /* Write 0x90 to BBP_R25 to transmit test tone */
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R25, 0x90);
-
- RTMPusecDelay(1000);
- /* Read BBP_R55[6:0] for received power, set R55x = BBP_R55[6:0] */
- RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R55, &value);
- R55x = value & 0xFF;
-
- } while ((ReTry++ < 100) && (R55x == 0));
-
- /* Write 0x06 to BBP_R24 to set power & frequency of stopband test tone */
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R24, 0x06);
-
- while (TRUE) {
- /* Write 0x90 to BBP_R25 to transmit test tone */
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R25, 0x90);
-
- /*We need to wait for calibration */
- RTMPusecDelay(1000);
- RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R55, &value);
- value &= 0xFF;
- if ((R55x - value) < FilterTarget) {
- RF_R24_Value++;
- } else if ((R55x - value) == FilterTarget) {
- RF_R24_Value++;
- count++;
- } else {
- break;
- }
-
- /* prevent infinite loop; causes driver hang. */
- if (loopcnt++ > 100) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("RTMPFilterCalibration - can't find a valid value, loopcnt=%d stop calibrating",
- loopcnt));
- break;
- }
- /* Write RF_R24 to program filter */
- RT30xxWriteRFRegister(pAd, RF_R24, RF_R24_Value);
- }
-
- if (count > 0) {
- RF_R24_Value = RF_R24_Value - ((count) ? (1) : (0));
- }
- /* Store for future usage */
- if (loopcnt < 100) {
- if (loop++ == 0) {
- /*BandWidth = 20 MHz */
- pAd->Mlme.CaliBW20RfR24 = (u8)RF_R24_Value;
- } else {
- /*BandWidth = 40 MHz */
- pAd->Mlme.CaliBW40RfR24 = (u8)RF_R24_Value;
- break;
- }
- } else
- break;
-
- RT30xxWriteRFRegister(pAd, RF_R24, RF_R24_Value);
-
- /* reset count */
- count = 0;
- } while (TRUE);
-
- /* */
- /* Set back to initial state */
- /* */
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R24, 0);
-
- RT30xxReadRFRegister(pAd, RF_R22, &value);
- value &= ~(0x01);
- RT30xxWriteRFRegister(pAd, RF_R22, value);
-
- /* set BBP back to BW20 */
- RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &BBPValue);
- BBPValue &= (~0x18);
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, BBPValue);
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("RTMPFilterCalibration - CaliBW20RfR24=0x%x, CaliBW40RfR24=0x%x\n",
- pAd->Mlme.CaliBW20RfR24, pAd->Mlme.CaliBW40RfR24));
-}
-
-/* add by johnli, RF power sequence setup */
-/*
- ==========================================================================
- Description:
-
- Load RF normal operation-mode setup
-
- ==========================================================================
- */
-void RT30xxLoadRFNormalModeSetup(struct rt_rtmp_adapter *pAd)
-{
- u8 RFValue;
-
- /* RX0_PD & TX0_PD, RF R1 register Bit 2 & Bit 3 to 0 and RF_BLOCK_en,RX1_PD & TX1_PD, Bit0, Bit 4 & Bit5 to 1 */
- RT30xxReadRFRegister(pAd, RF_R01, &RFValue);
- RFValue = (RFValue & (~0x0C)) | 0x31;
- RT30xxWriteRFRegister(pAd, RF_R01, RFValue);
-
- /* TX_LO2_en, RF R15 register Bit 3 to 0 */
- RT30xxReadRFRegister(pAd, RF_R15, &RFValue);
- RFValue &= (~0x08);
- RT30xxWriteRFRegister(pAd, RF_R15, RFValue);
-
- /* move to NICInitRT30xxRFRegisters
- // TX_LO1_en, RF R17 register Bit 3 to 0
- RT30xxReadRFRegister(pAd, RF_R17, &RFValue);
- RFValue &= (~0x08);
- // to fix rx long range issue
- if (((pAd->MACVersion & 0xffff) >= 0x0211) && (pAd->NicConfig2.field.ExternalLNAForG == 0))
- {
- RFValue |= 0x20;
- }
- // set RF_R17_bit[2:0] equal to EEPROM setting at 0x48h
- if (pAd->TxMixerGain24G >= 2)
- {
- RFValue &= (~0x7); // clean bit [2:0]
- RFValue |= pAd->TxMixerGain24G;
- }
- RT30xxWriteRFRegister(pAd, RF_R17, RFValue);
- */
-
- /* RX_LO1_en, RF R20 register Bit 3 to 0 */
- RT30xxReadRFRegister(pAd, RF_R20, &RFValue);
- RFValue &= (~0x08);
- RT30xxWriteRFRegister(pAd, RF_R20, RFValue);
-
- /* RX_LO2_en, RF R21 register Bit 3 to 0 */
- RT30xxReadRFRegister(pAd, RF_R21, &RFValue);
- RFValue &= (~0x08);
- RT30xxWriteRFRegister(pAd, RF_R21, RFValue);
-
- /* add by johnli, reset RF_R27 when interface down & up to fix throughput problem */
- /* LDORF_VC, RF R27 register Bit 2 to 0 */
- RT30xxReadRFRegister(pAd, RF_R27, &RFValue);
- /* TX to RX IQ glitch(RF_R27) has been fixed in RT3070(F). */
- /* Raising RF voltage is no longer needed for RT3070(F) */
- if (IS_RT3090(pAd)) { /* RT309x and RT3071/72 */
- if ((pAd->MACVersion & 0xffff) < 0x0211)
- RFValue = (RFValue & (~0x77)) | 0x3;
- else
- RFValue = (RFValue & (~0x77));
- RT30xxWriteRFRegister(pAd, RF_R27, RFValue);
- }
- /* end johnli */
-}
-
-/*
- ==========================================================================
- Description:
-
- Load RF sleep-mode setup
-
- ==========================================================================
- */
-void RT30xxLoadRFSleepModeSetup(struct rt_rtmp_adapter *pAd)
-{
- u8 RFValue;
- u32 MACValue;
-
-#ifdef RTMP_MAC_USB
- if (!IS_RT3572(pAd))
-#endif /* RTMP_MAC_USB // */
- {
- /* RF_BLOCK_en. RF R1 register Bit 0 to 0 */
- RT30xxReadRFRegister(pAd, RF_R01, &RFValue);
- RFValue &= (~0x01);
- RT30xxWriteRFRegister(pAd, RF_R01, RFValue);
-
- /* VCO_IC, RF R7 register Bit 4 & Bit 5 to 0 */
- RT30xxReadRFRegister(pAd, RF_R07, &RFValue);
- RFValue &= (~0x30);
- RT30xxWriteRFRegister(pAd, RF_R07, RFValue);
-
- /* Idoh, RF R9 register Bit 1, Bit 2 & Bit 3 to 0 */
- RT30xxReadRFRegister(pAd, RF_R09, &RFValue);
- RFValue &= (~0x0E);
- RT30xxWriteRFRegister(pAd, RF_R09, RFValue);
-
- /* RX_CTB_en, RF R21 register Bit 7 to 0 */
- RT30xxReadRFRegister(pAd, RF_R21, &RFValue);
- RFValue &= (~0x80);
- RT30xxWriteRFRegister(pAd, RF_R21, RFValue);
- }
-
- if (IS_RT3090(pAd) || /* IS_RT3090 including RT309x and RT3071/72 */
- IS_RT3572(pAd) ||
- (IS_RT3070(pAd) && ((pAd->MACVersion & 0xffff) < 0x0201))) {
-#ifdef RTMP_MAC_USB
- if (!IS_RT3572(pAd))
-#endif /* RTMP_MAC_USB // */
- {
- RT30xxReadRFRegister(pAd, RF_R27, &RFValue);
- RFValue |= 0x77;
- RT30xxWriteRFRegister(pAd, RF_R27, RFValue);
- }
-
- RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue);
- MACValue |= 0x1D000000;
- RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue);
- }
-}
-
-/*
- ==========================================================================
- Description:
-
- Reverse RF sleep-mode setup
-
- ==========================================================================
- */
-void RT30xxReverseRFSleepModeSetup(struct rt_rtmp_adapter *pAd)
-{
- u8 RFValue;
- u32 MACValue;
-
-#ifdef RTMP_MAC_USB
- if (!IS_RT3572(pAd))
-#endif /* RTMP_MAC_USB // */
- {
- /* RF_BLOCK_en, RF R1 register Bit 0 to 1 */
- RT30xxReadRFRegister(pAd, RF_R01, &RFValue);
- RFValue |= 0x01;
- RT30xxWriteRFRegister(pAd, RF_R01, RFValue);
-
- /* VCO_IC, RF R7 register Bit 4 & Bit 5 to 1 */
- RT30xxReadRFRegister(pAd, RF_R07, &RFValue);
- RFValue |= 0x20;
- RT30xxWriteRFRegister(pAd, RF_R07, RFValue);
-
- /* Idoh, RF R9 register Bit 1, Bit 2 & Bit 3 to 1 */
- RT30xxReadRFRegister(pAd, RF_R09, &RFValue);
- RFValue |= 0x0E;
- RT30xxWriteRFRegister(pAd, RF_R09, RFValue);
-
- /* RX_CTB_en, RF R21 register Bit 7 to 1 */
- RT30xxReadRFRegister(pAd, RF_R21, &RFValue);
- RFValue |= 0x80;
- RT30xxWriteRFRegister(pAd, RF_R21, RFValue);
- }
-
- if (IS_RT3090(pAd) || /* IS_RT3090 including RT309x and RT3071/72 */
- IS_RT3572(pAd) ||
- IS_RT3390(pAd) ||
- (IS_RT3070(pAd) && ((pAd->MACVersion & 0xffff) < 0x0201))) {
-#ifdef RTMP_MAC_USB
- if (!IS_RT3572(pAd))
-#endif /* RTMP_MAC_USB // */
- {
- RT30xxReadRFRegister(pAd, RF_R27, &RFValue);
- if ((pAd->MACVersion & 0xffff) < 0x0211)
- RFValue = (RFValue & (~0x77)) | 0x3;
- else
- RFValue = (RFValue & (~0x77));
- RT30xxWriteRFRegister(pAd, RF_R27, RFValue);
- }
- /* RT3071 version E has fixed this issue */
- if ((pAd->NicConfig2.field.DACTestBit == 1)
- && ((pAd->MACVersion & 0xffff) < 0x0211)) {
- /* patch tx EVM issue temporarily */
- RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue);
- MACValue = ((MACValue & 0xE0FFFFFF) | 0x0D000000);
- RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue);
- } else {
- RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue);
- MACValue = ((MACValue & 0xE0FFFFFF) | 0x01000000);
- RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue);
- }
- }
-
- if (IS_RT3572(pAd))
- RT30xxWriteRFRegister(pAd, RF_R08, 0x80);
-}
-
-/* end johnli */
-
-void RT30xxHaltAction(struct rt_rtmp_adapter *pAd)
-{
- u32 TxPinCfg = 0x00050F0F;
-
- /* */
- /* Turn off LNA_PE or TRSW_POL */
- /* */
- if (IS_RT3070(pAd) || IS_RT3071(pAd) || IS_RT3572(pAd)) {
- if ((IS_RT3071(pAd) || IS_RT3572(pAd))
-#ifdef RTMP_EFUSE_SUPPORT
- && (pAd->bUseEfuse)
-#endif /* RTMP_EFUSE_SUPPORT // */
- ) {
- TxPinCfg &= 0xFFFBF0F0; /* bit18 off */
- } else {
- TxPinCfg &= 0xFFFFF0F0;
- }
-
- RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg);
- }
-}
-
-#endif /* RT30xx // */
diff --git a/drivers/staging/rt2860/chlist.h b/drivers/staging/rt2860/chlist.h
deleted file mode 100644
index 1231e69..0000000
--- a/drivers/staging/rt2860/chlist.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- chlist.c
-
- Abstract:
-
- Revision History:
- Who When What
- -------- ---------- ----------------------------------------------
- Fonchi Wu 2007-12-19 created
-*/
-
-#ifndef __CHLIST_H__
-#define __CHLIST_H__
-
-#include "rtmp_type.h"
-#include "rtmp_def.h"
-
-#define ODOR 0
-#define IDOR 1
-#define BOTH 2
-
-#define BAND_5G 0
-#define BAND_24G 1
-#define BAND_BOTH 2
-
-struct rt_ch_desp {
- u8 FirstChannel;
- u8 NumOfCh;
- char MaxTxPwr; /* dBm */
- u8 Geography; /* 0:out door, 1:in door, 2:both */
- BOOLEAN DfsReq; /* Dfs require, 0: No, 1: yes. */
-};
-
-struct rt_ch_region {
- u8 CountReg[3];
- u8 DfsType; /* 0: CE, 1: FCC, 2: JAP, 3:JAP_W53, JAP_W56 */
- struct rt_ch_desp ChDesp[10];
-};
-
-extern struct rt_ch_region ChRegion[];
-
-struct rt_ch_freq_map {
- u16 channel;
- u16 freqKHz;
-};
-
-extern struct rt_ch_freq_map CH_HZ_ID_MAP[];
-extern int CH_HZ_ID_MAP_NUM;
-
-#define MAP_CHANNEL_ID_TO_KHZ(_ch, _khz) \
- do { \
- int _chIdx; \
- for (_chIdx = 0; _chIdx < CH_HZ_ID_MAP_NUM; _chIdx++) {\
- if ((_ch) == CH_HZ_ID_MAP[_chIdx].channel) { \
- (_khz) = CH_HZ_ID_MAP[_chIdx].freqKHz * 1000;\
- break; \
- } \
- } \
- if (_chIdx == CH_HZ_ID_MAP_NUM) \
- (_khz) = 2412000; \
- } while (0)
-
-#define MAP_KHZ_TO_CHANNEL_ID(_khz, _ch) \
- do { \
- int _chIdx; \
- for (_chIdx = 0; _chIdx < CH_HZ_ID_MAP_NUM; _chIdx++) {\
- if ((_khz) == CH_HZ_ID_MAP[_chIdx].freqKHz) {\
- (_ch) = CH_HZ_ID_MAP[_chIdx].channel; \
- break; \
- } \
- } \
- if (_chIdx == CH_HZ_ID_MAP_NUM) \
- (_ch) = 1; \
- } while (0)
-
-void BuildChannelListEx(struct rt_rtmp_adapter *pAd);
-
-void BuildBeaconChList(struct rt_rtmp_adapter *pAd,
- u8 *pBuf, unsigned long *pBufLen);
-
-void N_ChannelCheck(struct rt_rtmp_adapter *pAd);
-
-void N_SetCenCh(struct rt_rtmp_adapter *pAd);
-
-u8 GetCuntryMaxTxPwr(struct rt_rtmp_adapter *pAd, u8 channel);
-
-#endif /* __CHLIST_H__ */
diff --git a/drivers/staging/rt2860/common/action.c b/drivers/staging/rt2860/common/action.c
deleted file mode 100644
index 56ad236..0000000
--- a/drivers/staging/rt2860/common/action.c
+++ /dev/null
@@ -1,606 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- action.c
-
- Abstract:
- Handle association related requests either from WSTA or from local MLME
-
- Revision History:
- Who When What
- -------- ---------- ----------------------------------------------
- Jan Lee 2006 created for rt2860
- */
-
-#include "../rt_config.h"
-#include "action.h"
-
-static void ReservedAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem);
-
-/*
- ==========================================================================
- Description:
- association state machine init, including state transition and timer init
- Parameters:
- S - pointer to the association state machine
- Note:
- The state machine looks like the following
-
- ASSOC_IDLE
- MT2_MLME_DISASSOC_REQ mlme_disassoc_req_action
- MT2_PEER_DISASSOC_REQ peer_disassoc_action
- MT2_PEER_ASSOC_REQ drop
- MT2_PEER_REASSOC_REQ drop
- MT2_CLS3ERR cls3err_action
- ==========================================================================
- */
-void ActionStateMachineInit(struct rt_rtmp_adapter *pAd,
- struct rt_state_machine *S,
- OUT STATE_MACHINE_FUNC Trans[])
-{
- StateMachineInit(S, (STATE_MACHINE_FUNC *) Trans, MAX_ACT_STATE,
- MAX_ACT_MSG, (STATE_MACHINE_FUNC) Drop, ACT_IDLE,
- ACT_MACHINE_BASE);
-
- StateMachineSetAction(S, ACT_IDLE, MT2_PEER_SPECTRUM_CATE,
- (STATE_MACHINE_FUNC) PeerSpectrumAction);
- StateMachineSetAction(S, ACT_IDLE, MT2_PEER_QOS_CATE,
- (STATE_MACHINE_FUNC) PeerQOSAction);
-
- StateMachineSetAction(S, ACT_IDLE, MT2_PEER_DLS_CATE,
- (STATE_MACHINE_FUNC) ReservedAction);
-
- StateMachineSetAction(S, ACT_IDLE, MT2_PEER_BA_CATE,
- (STATE_MACHINE_FUNC) PeerBAAction);
- StateMachineSetAction(S, ACT_IDLE, MT2_PEER_HT_CATE,
- (STATE_MACHINE_FUNC) PeerHTAction);
- StateMachineSetAction(S, ACT_IDLE, MT2_MLME_ADD_BA_CATE,
- (STATE_MACHINE_FUNC) MlmeADDBAAction);
- StateMachineSetAction(S, ACT_IDLE, MT2_MLME_ORI_DELBA_CATE,
- (STATE_MACHINE_FUNC) MlmeDELBAAction);
- StateMachineSetAction(S, ACT_IDLE, MT2_MLME_REC_DELBA_CATE,
- (STATE_MACHINE_FUNC) MlmeDELBAAction);
-
- StateMachineSetAction(S, ACT_IDLE, MT2_PEER_PUBLIC_CATE,
- (STATE_MACHINE_FUNC) PeerPublicAction);
- StateMachineSetAction(S, ACT_IDLE, MT2_PEER_RM_CATE,
- (STATE_MACHINE_FUNC) PeerRMAction);
-
- StateMachineSetAction(S, ACT_IDLE, MT2_MLME_QOS_CATE,
- (STATE_MACHINE_FUNC) MlmeQOSAction);
- StateMachineSetAction(S, ACT_IDLE, MT2_MLME_DLS_CATE,
- (STATE_MACHINE_FUNC) MlmeDLSAction);
- StateMachineSetAction(S, ACT_IDLE, MT2_ACT_INVALID,
- (STATE_MACHINE_FUNC) MlmeInvalidAction);
-}
-
-void MlmeADDBAAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
- struct rt_mlme_addba_req *pInfo;
- u8 Addr[6];
- u8 *pOutBuffer = NULL;
- int NStatus;
- unsigned long Idx;
- struct rt_frame_addba_req Frame;
- unsigned long FrameLen;
- struct rt_ba_ori_entry *pBAEntry = NULL;
-
- pInfo = (struct rt_mlme_addba_req *)Elem->Msg;
- NdisZeroMemory(&Frame, sizeof(struct rt_frame_addba_req));
-
- if (MlmeAddBAReqSanity(pAd, Elem->Msg, Elem->MsgLen, Addr)) {
- NStatus = MlmeAllocateMemory(pAd, &pOutBuffer); /*Get an unused nonpaged memory */
- if (NStatus != NDIS_STATUS_SUCCESS) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("BA - MlmeADDBAAction() allocate memory failed \n"));
- return;
- }
- /* 1. find entry */
- Idx =
- pAd->MacTab.Content[pInfo->Wcid].BAOriWcidArray[pInfo->TID];
- if (Idx == 0) {
- MlmeFreeMemory(pAd, pOutBuffer);
- DBGPRINT(RT_DEBUG_ERROR,
- ("BA - MlmeADDBAAction() can't find BAOriEntry \n"));
- return;
- } else {
- pBAEntry = &pAd->BATable.BAOriEntry[Idx];
- }
-
- {
- if (ADHOC_ON(pAd))
- ActHeaderInit(pAd, &Frame.Hdr, pInfo->pAddr,
- pAd->CurrentAddress,
- pAd->CommonCfg.Bssid);
- else
- ActHeaderInit(pAd, &Frame.Hdr,
- pAd->CommonCfg.Bssid,
- pAd->CurrentAddress,
- pInfo->pAddr);
- }
-
- Frame.Category = CATEGORY_BA;
- Frame.Action = ADDBA_REQ;
- Frame.BaParm.AMSDUSupported = 0;
- Frame.BaParm.BAPolicy = IMMED_BA;
- Frame.BaParm.TID = pInfo->TID;
- Frame.BaParm.BufSize = pInfo->BaBufSize;
- Frame.Token = pInfo->Token;
- Frame.TimeOutValue = pInfo->TimeOutValue;
- Frame.BaStartSeq.field.FragNum = 0;
- Frame.BaStartSeq.field.StartSeq =
- pAd->MacTab.Content[pInfo->Wcid].TxSeq[pInfo->TID];
-
- *(u16 *) (&Frame.BaParm) =
- cpu2le16(*(u16 *) (&Frame.BaParm));
- Frame.TimeOutValue = cpu2le16(Frame.TimeOutValue);
- Frame.BaStartSeq.word = cpu2le16(Frame.BaStartSeq.word);
-
- MakeOutgoingFrame(pOutBuffer, &FrameLen,
- sizeof(struct rt_frame_addba_req), &Frame, END_OF_ARGS);
-
- MiniportMMRequest(pAd,
- (MGMT_USE_QUEUE_FLAG |
- MapUserPriorityToAccessCategory[pInfo->TID]),
- pOutBuffer, FrameLen);
-
- MlmeFreeMemory(pAd, pOutBuffer);
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("BA - Send ADDBA request. StartSeq = %x, FrameLen = %ld. BufSize = %d\n",
- Frame.BaStartSeq.field.StartSeq, FrameLen,
- Frame.BaParm.BufSize));
- }
-}
-
-/*
- ==========================================================================
- Description:
- send DELBA and delete BaEntry if any
- Parametrs:
- Elem - MLME message struct rt_mlme_delba_req
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
- */
-void MlmeDELBAAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
- struct rt_mlme_delba_req *pInfo;
- u8 *pOutBuffer = NULL;
- u8 *pOutBuffer2 = NULL;
- int NStatus;
- unsigned long Idx;
- struct rt_frame_delba_req Frame;
- unsigned long FrameLen;
- struct rt_frame_bar FrameBar;
-
- pInfo = (struct rt_mlme_delba_req *)Elem->Msg;
- /* must send back DELBA */
- NdisZeroMemory(&Frame, sizeof(struct rt_frame_delba_req));
- DBGPRINT(RT_DEBUG_TRACE,
- ("==> MlmeDELBAAction(), Initiator(%d) \n", pInfo->Initiator));
-
- if (MlmeDelBAReqSanity(pAd, Elem->Msg, Elem->MsgLen)) {
- NStatus = MlmeAllocateMemory(pAd, &pOutBuffer); /*Get an unused nonpaged memory */
- if (NStatus != NDIS_STATUS_SUCCESS) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("BA - MlmeDELBAAction() allocate memory failed 1. \n"));
- return;
- }
-
- NStatus = MlmeAllocateMemory(pAd, &pOutBuffer2); /*Get an unused nonpaged memory */
- if (NStatus != NDIS_STATUS_SUCCESS) {
- MlmeFreeMemory(pAd, pOutBuffer);
- DBGPRINT(RT_DEBUG_ERROR,
- ("BA - MlmeDELBAAction() allocate memory failed 2. \n"));
- return;
- }
- /* SEND BAR (Send BAR to refresh peer reordering buffer.) */
- Idx =
- pAd->MacTab.Content[pInfo->Wcid].BAOriWcidArray[pInfo->TID];
-
- BarHeaderInit(pAd, &FrameBar,
- pAd->MacTab.Content[pInfo->Wcid].Addr,
- pAd->CurrentAddress);
-
- FrameBar.StartingSeq.field.FragNum = 0; /* make sure sequence not clear in DEL funciton. */
- FrameBar.StartingSeq.field.StartSeq = pAd->MacTab.Content[pInfo->Wcid].TxSeq[pInfo->TID]; /* make sure sequence not clear in DEL funciton. */
- FrameBar.BarControl.TID = pInfo->TID; /* make sure sequence not clear in DEL funciton. */
- FrameBar.BarControl.ACKPolicy = IMMED_BA; /* make sure sequence not clear in DEL funciton. */
- FrameBar.BarControl.Compressed = 1; /* make sure sequence not clear in DEL funciton. */
- FrameBar.BarControl.MTID = 0; /* make sure sequence not clear in DEL funciton. */
-
- MakeOutgoingFrame(pOutBuffer2, &FrameLen,
- sizeof(struct rt_frame_bar), &FrameBar, END_OF_ARGS);
- MiniportMMRequest(pAd, QID_AC_BE, pOutBuffer2, FrameLen);
- MlmeFreeMemory(pAd, pOutBuffer2);
- DBGPRINT(RT_DEBUG_TRACE,
- ("BA - MlmeDELBAAction() . Send BAR to refresh peer reordering buffer \n"));
-
- /* SEND DELBA FRAME */
- FrameLen = 0;
-
- {
- if (ADHOC_ON(pAd))
- ActHeaderInit(pAd, &Frame.Hdr,
- pAd->MacTab.Content[pInfo->Wcid].
- Addr, pAd->CurrentAddress,
- pAd->CommonCfg.Bssid);
- else
- ActHeaderInit(pAd, &Frame.Hdr,
- pAd->CommonCfg.Bssid,
- pAd->CurrentAddress,
- pAd->MacTab.Content[pInfo->Wcid].
- Addr);
- }
-
- Frame.Category = CATEGORY_BA;
- Frame.Action = DELBA;
- Frame.DelbaParm.Initiator = pInfo->Initiator;
- Frame.DelbaParm.TID = pInfo->TID;
- Frame.ReasonCode = 39; /* Time Out */
- *(u16 *) (&Frame.DelbaParm) =
- cpu2le16(*(u16 *) (&Frame.DelbaParm));
- Frame.ReasonCode = cpu2le16(Frame.ReasonCode);
-
- MakeOutgoingFrame(pOutBuffer, &FrameLen,
- sizeof(struct rt_frame_delba_req), &Frame, END_OF_ARGS);
- MiniportMMRequest(pAd, QID_AC_BE, pOutBuffer, FrameLen);
- MlmeFreeMemory(pAd, pOutBuffer);
- DBGPRINT(RT_DEBUG_TRACE,
- ("BA - MlmeDELBAAction() . 3 DELBA sent. Initiator(%d)\n",
- pInfo->Initiator));
- }
-}
-
-void MlmeQOSAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
-}
-
-void MlmeDLSAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
-}
-
-void MlmeInvalidAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
- /*u8 * pOutBuffer = NULL; */
- /*Return the receiving frame except the MSB of category filed set to 1. 7.3.1.11 */
-}
-
-void PeerQOSAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
-}
-
-void PeerBAAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
- u8 Action = Elem->Msg[LENGTH_802_11 + 1];
-
- switch (Action) {
- case ADDBA_REQ:
- PeerAddBAReqAction(pAd, Elem);
- break;
- case ADDBA_RESP:
- PeerAddBARspAction(pAd, Elem);
- break;
- case DELBA:
- PeerDelBAAction(pAd, Elem);
- break;
- }
-}
-
-void PeerPublicAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
- if (Elem->Wcid >= MAX_LEN_OF_MAC_TABLE)
- return;
-}
-
-static void ReservedAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
- u8 Category;
-
- if (Elem->MsgLen <= LENGTH_802_11) {
- return;
- }
-
- Category = Elem->Msg[LENGTH_802_11];
- DBGPRINT(RT_DEBUG_TRACE,
- ("Rcv reserved category(%d) Action Frame\n", Category));
- hex_dump("Reserved Action Frame", &Elem->Msg[0], Elem->MsgLen);
-}
-
-void PeerRMAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
- return;
-}
-
-static void respond_ht_information_exchange_action(struct rt_rtmp_adapter *pAd,
- struct rt_mlme_queue_elem *Elem)
-{
- u8 *pOutBuffer = NULL;
- int NStatus;
- unsigned long FrameLen;
- struct rt_frame_ht_info HTINFOframe, *pFrame;
- u8 *pAddr;
-
- /* 2. Always send back ADDBA Response */
- NStatus = MlmeAllocateMemory(pAd, &pOutBuffer); /*Get an unused nonpaged memory */
-
- if (NStatus != NDIS_STATUS_SUCCESS) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("ACTION - respond_ht_information_exchange_action() allocate memory failed \n"));
- return;
- }
- /* get RA */
- pFrame = (struct rt_frame_ht_info *) & Elem->Msg[0];
- pAddr = pFrame->Hdr.Addr2;
-
- NdisZeroMemory(&HTINFOframe, sizeof(struct rt_frame_ht_info));
- /* 2-1. Prepare ADDBA Response frame. */
- {
- if (ADHOC_ON(pAd))
- ActHeaderInit(pAd, &HTINFOframe.Hdr, pAddr,
- pAd->CurrentAddress,
- pAd->CommonCfg.Bssid);
- else
- ActHeaderInit(pAd, &HTINFOframe.Hdr,
- pAd->CommonCfg.Bssid, pAd->CurrentAddress,
- pAddr);
- }
-
- HTINFOframe.Category = CATEGORY_HT;
- HTINFOframe.Action = HT_INFO_EXCHANGE;
- HTINFOframe.HT_Info.Request = 0;
- HTINFOframe.HT_Info.Forty_MHz_Intolerant =
- pAd->CommonCfg.HtCapability.HtCapInfo.Forty_Mhz_Intolerant;
- HTINFOframe.HT_Info.STA_Channel_Width =
- pAd->CommonCfg.AddHTInfo.AddHtInfo.RecomWidth;
-
- MakeOutgoingFrame(pOutBuffer, &FrameLen,
- sizeof(struct rt_frame_ht_info), &HTINFOframe, END_OF_ARGS);
-
- MiniportMMRequest(pAd, QID_AC_BE, pOutBuffer, FrameLen);
- MlmeFreeMemory(pAd, pOutBuffer);
-}
-
-void PeerHTAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
- u8 Action = Elem->Msg[LENGTH_802_11 + 1];
-
- if (Elem->Wcid >= MAX_LEN_OF_MAC_TABLE)
- return;
-
- switch (Action) {
- case NOTIFY_BW_ACTION:
- DBGPRINT(RT_DEBUG_TRACE,
- ("ACTION - HT Notify Channel bandwidth action----> \n"));
-
- if (pAd->StaActive.SupportedPhyInfo.bHtEnable == FALSE) {
- /* Note, this is to patch DIR-1353 AP. When the AP set to Wep, it will use legacy mode. But AP still keeps */
- /* sending BW_Notify Action frame, and cause us to linkup and linkdown. */
- /* In legacy mode, don't need to parse HT action frame. */
- DBGPRINT(RT_DEBUG_TRACE,
- ("ACTION -Ignore HT Notify Channel BW when link as legacy mode. BW = %d---> \n",
- Elem->Msg[LENGTH_802_11 + 2]));
- break;
- }
-
- if (Elem->Msg[LENGTH_802_11 + 2] == 0) /* 7.4.8.2. if value is 1, keep the same as supported channel bandwidth. */
- pAd->MacTab.Content[Elem->Wcid].HTPhyMode.field.BW = 0;
-
- break;
- case SMPS_ACTION:
- /* 7.3.1.25 */
- DBGPRINT(RT_DEBUG_TRACE, ("ACTION - SMPS action----> \n"));
- if (((Elem->Msg[LENGTH_802_11 + 2] & 0x1) == 0)) {
- pAd->MacTab.Content[Elem->Wcid].MmpsMode = MMPS_ENABLE;
- } else if (((Elem->Msg[LENGTH_802_11 + 2] & 0x2) == 0)) {
- pAd->MacTab.Content[Elem->Wcid].MmpsMode = MMPS_STATIC;
- } else {
- pAd->MacTab.Content[Elem->Wcid].MmpsMode = MMPS_DYNAMIC;
- }
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("Aid(%d) MIMO PS = %d\n", Elem->Wcid,
- pAd->MacTab.Content[Elem->Wcid].MmpsMode));
- /* rt2860c : add something for smps change. */
- break;
-
- case SETPCO_ACTION:
- break;
- case MIMO_CHA_MEASURE_ACTION:
- break;
- case HT_INFO_EXCHANGE:
- {
- struct rt_ht_information_octet *pHT_info;
-
- pHT_info =
- (struct rt_ht_information_octet *) & Elem->Msg[LENGTH_802_11 +
- 2];
- /* 7.4.8.10 */
- DBGPRINT(RT_DEBUG_TRACE,
- ("ACTION - HT Information Exchange action----> \n"));
- if (pHT_info->Request) {
- respond_ht_information_exchange_action(pAd,
- Elem);
- }
- }
- break;
- }
-}
-
-/*
- ==========================================================================
- Description:
- Retry sending ADDBA Reqest.
-
- IRQL = DISPATCH_LEVEL
-
- Parametrs:
- p8023Header: if this is already 802.3 format, p8023Header is NULL
-
- Return : TRUE if put into rx reordering buffer, shouldn't indicaterxhere.
- FALSE , then continue indicaterx at this moment.
- ==========================================================================
- */
-void ORIBATimerTimeout(struct rt_rtmp_adapter *pAd)
-{
- struct rt_mac_table_entry *pEntry;
- int i, total;
- u8 TID;
-
- total = pAd->MacTab.Size * NUM_OF_TID;
-
- for (i = 1; ((i < MAX_LEN_OF_BA_ORI_TABLE) && (total > 0)); i++) {
- if (pAd->BATable.BAOriEntry[i].ORI_BA_Status == Originator_Done) {
- pEntry =
- &pAd->MacTab.Content[pAd->BATable.BAOriEntry[i].
- Wcid];
- TID = pAd->BATable.BAOriEntry[i].TID;
-
- ASSERT(pAd->BATable.BAOriEntry[i].Wcid <
- MAX_LEN_OF_MAC_TABLE);
- }
- total--;
- }
-}
-
-void SendRefreshBAR(struct rt_rtmp_adapter *pAd, struct rt_mac_table_entry *pEntry)
-{
- struct rt_frame_bar FrameBar;
- unsigned long FrameLen;
- int NStatus;
- u8 *pOutBuffer = NULL;
- u16 Sequence;
- u8 i, TID;
- u16 idx;
- struct rt_ba_ori_entry *pBAEntry;
-
- for (i = 0; i < NUM_OF_TID; i++) {
- idx = pEntry->BAOriWcidArray[i];
- if (idx == 0) {
- continue;
- }
- pBAEntry = &pAd->BATable.BAOriEntry[idx];
-
- if (pBAEntry->ORI_BA_Status == Originator_Done) {
- TID = pBAEntry->TID;
-
- ASSERT(pBAEntry->Wcid < MAX_LEN_OF_MAC_TABLE);
-
- NStatus = MlmeAllocateMemory(pAd, &pOutBuffer); /*Get an unused nonpaged memory */
- if (NStatus != NDIS_STATUS_SUCCESS) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("BA - MlmeADDBAAction() allocate memory failed \n"));
- return;
- }
-
- Sequence = pEntry->TxSeq[TID];
-
- BarHeaderInit(pAd, &FrameBar, pEntry->Addr,
- pAd->CurrentAddress);
-
- FrameBar.StartingSeq.field.FragNum = 0; /* make sure sequence not clear in DEL function. */
- FrameBar.StartingSeq.field.StartSeq = Sequence; /* make sure sequence not clear in DEL funciton. */
- FrameBar.BarControl.TID = TID; /* make sure sequence not clear in DEL funciton. */
-
- MakeOutgoingFrame(pOutBuffer, &FrameLen,
- sizeof(struct rt_frame_bar), &FrameBar,
- END_OF_ARGS);
- /*if (!(CLIENT_STATUS_TEST_FLAG(pEntry, fCLIENT_STATUS_RALINK_CHIPSET))) */
- if (1) /* Now we always send BAR. */
- {
- /*MiniportMMRequestUnlock(pAd, 0, pOutBuffer, FrameLen); */
- MiniportMMRequest(pAd,
- (MGMT_USE_QUEUE_FLAG |
- MapUserPriorityToAccessCategory
- [TID]), pOutBuffer,
- FrameLen);
-
- }
- MlmeFreeMemory(pAd, pOutBuffer);
- }
- }
-}
-
-void ActHeaderInit(struct rt_rtmp_adapter *pAd,
- struct rt_header_802_11 * pHdr80211,
- u8 *Addr1, u8 *Addr2, u8 *Addr3)
-{
- NdisZeroMemory(pHdr80211, sizeof(struct rt_header_802_11));
- pHdr80211->FC.Type = BTYPE_MGMT;
- pHdr80211->FC.SubType = SUBTYPE_ACTION;
-
- COPY_MAC_ADDR(pHdr80211->Addr1, Addr1);
- COPY_MAC_ADDR(pHdr80211->Addr2, Addr2);
- COPY_MAC_ADDR(pHdr80211->Addr3, Addr3);
-}
-
-void BarHeaderInit(struct rt_rtmp_adapter *pAd,
- struct rt_frame_bar * pCntlBar, u8 *pDA, u8 *pSA)
-{
- NdisZeroMemory(pCntlBar, sizeof(struct rt_frame_bar));
- pCntlBar->FC.Type = BTYPE_CNTL;
- pCntlBar->FC.SubType = SUBTYPE_BLOCK_ACK_REQ;
- pCntlBar->BarControl.MTID = 0;
- pCntlBar->BarControl.Compressed = 1;
- pCntlBar->BarControl.ACKPolicy = 0;
-
- pCntlBar->Duration =
- 16 + RTMPCalcDuration(pAd, RATE_1, sizeof(struct rt_frame_ba));
-
- COPY_MAC_ADDR(pCntlBar->Addr1, pDA);
- COPY_MAC_ADDR(pCntlBar->Addr2, pSA);
-}
-
-/*
- ==========================================================================
- Description:
- Insert Category and action code into the action frame.
-
- Parametrs:
- 1. frame buffer pointer.
- 2. frame length.
- 3. category code of the frame.
- 4. action code of the frame.
-
- Return : None.
- ==========================================================================
- */
-void InsertActField(struct rt_rtmp_adapter *pAd,
- u8 *pFrameBuf,
- unsigned long *pFrameLen, u8 Category, u8 ActCode)
-{
- unsigned long TempLen;
-
- MakeOutgoingFrame(pFrameBuf, &TempLen,
- 1, &Category, 1, &ActCode, END_OF_ARGS);
-
- *pFrameLen = *pFrameLen + TempLen;
-
- return;
-}
diff --git a/drivers/staging/rt2860/common/action.h b/drivers/staging/rt2860/common/action.h
deleted file mode 100644
index 974f8b8..0000000
--- a/drivers/staging/rt2860/common/action.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- aironet.h
-
- Abstract:
-
- Revision History:
- Who When What
- -------- ---------- ----------------------------------------------
- Name Date Modification logs
- Paul Lin 04-06-15 Initial
-*/
-
-#ifndef __ACTION_H__
-#define __ACTION_H__
-
-struct PACKED rt_ht_information_octet {
- u8 Request:1;
- u8 Forty_MHz_Intolerant:1;
- u8 STA_Channel_Width:1;
- u8 Reserved:5;
-};
-
-struct PACKED rt_frame_ht_info {
- struct rt_header_802_11 Hdr;
- u8 Category;
- u8 Action;
- struct rt_ht_information_octet HT_Info;
-};
-
-#endif /* __ACTION_H__ */
diff --git a/drivers/staging/rt2860/common/ba_action.c b/drivers/staging/rt2860/common/ba_action.c
deleted file mode 100644
index 133bc1b..0000000
--- a/drivers/staging/rt2860/common/ba_action.c
+++ /dev/null
@@ -1,1650 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
- */
-
-#include "../rt_config.h"
-#include <linux/kernel.h>
-
-#define BA_ORI_INIT_SEQ (pEntry->TxSeq[TID]) /*1 // initial sequence number of BA session */
-
-#define ORI_SESSION_MAX_RETRY 8
-#define ORI_BA_SESSION_TIMEOUT (2000) /* ms */
-#define REC_BA_SESSION_IDLE_TIMEOUT (1000) /* ms */
-
-#define REORDERING_PACKET_TIMEOUT ((100 * OS_HZ)/1000) /* system ticks -- 100 ms */
-#define MAX_REORDERING_PACKET_TIMEOUT ((3000 * OS_HZ)/1000) /* system ticks -- 100 ms */
-
-#define RESET_RCV_SEQ (0xFFFF)
-
-static void ba_mpdu_blk_free(struct rt_rtmp_adapter *pAd,
- struct reordering_mpdu *mpdu_blk);
-
-struct rt_ba_ori_entry *BATableAllocOriEntry(struct rt_rtmp_adapter *pAd, u16 * Idx);
-
-struct rt_ba_rec_entry *BATableAllocRecEntry(struct rt_rtmp_adapter *pAd, u16 * Idx);
-
-void BAOriSessionSetupTimeout(void *SystemSpecific1,
- void *FunctionContext,
- void *SystemSpecific2,
- void *SystemSpecific3);
-
-void BARecSessionIdleTimeout(void *SystemSpecific1,
- void *FunctionContext,
- void *SystemSpecific2,
- void *SystemSpecific3);
-
-BUILD_TIMER_FUNCTION(BAOriSessionSetupTimeout);
-BUILD_TIMER_FUNCTION(BARecSessionIdleTimeout);
-
-#define ANNOUNCE_REORDERING_PACKET(_pAd, _mpdu_blk) \
- Announce_Reordering_Packet(_pAd, _mpdu_blk);
-
-void BA_MaxWinSizeReasign(struct rt_rtmp_adapter *pAd,
- struct rt_mac_table_entry *pEntryPeer, u8 * pWinSize)
-{
- u8 MaxSize;
-
- if (pAd->MACVersion >= RALINK_2883_VERSION) /* 3*3 */
- {
- if (pAd->MACVersion >= RALINK_3070_VERSION) {
- if (pEntryPeer->WepStatus !=
- Ndis802_11EncryptionDisabled)
- MaxSize = 7; /* for non-open mode */
- else
- MaxSize = 13;
- } else
- MaxSize = 31;
- } else if (pAd->MACVersion >= RALINK_2880E_VERSION) /* 2880 e */
- {
- if (pEntryPeer->WepStatus != Ndis802_11EncryptionDisabled)
- MaxSize = 7; /* for non-open mode */
- else
- MaxSize = 13;
- } else
- MaxSize = 7;
-
- DBGPRINT(RT_DEBUG_TRACE, ("ba> Win Size = %d, Max Size = %d\n",
- *pWinSize, MaxSize));
-
- if ((*pWinSize) > MaxSize) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("ba> reassign max win size from %d to %d\n",
- *pWinSize, MaxSize));
-
- *pWinSize = MaxSize;
- }
-}
-
-void Announce_Reordering_Packet(struct rt_rtmp_adapter *pAd,
- IN struct reordering_mpdu *mpdu)
-{
- void *pPacket;
-
- pPacket = mpdu->pPacket;
-
- if (mpdu->bAMSDU) {
- ASSERT(0);
- BA_Reorder_AMSDU_Announce(pAd, pPacket);
- } else {
- /* */
- /* pass this 802.3 packet to upper layer or forward this packet to WM directly */
- /* */
-
- ANNOUNCE_OR_FORWARD_802_3_PACKET(pAd, pPacket,
- RTMP_GET_PACKET_IF(pPacket));
- }
-}
-
-/*
- * Insert a reordering mpdu into sorted linked list by sequence no.
- */
-BOOLEAN ba_reordering_mpdu_insertsorted(struct reordering_list *list,
- struct reordering_mpdu *mpdu)
-{
-
- struct reordering_mpdu **ppScan = &list->next;
-
- while (*ppScan != NULL) {
- if (SEQ_SMALLER((*ppScan)->Sequence, mpdu->Sequence, MAXSEQ)) {
- ppScan = &(*ppScan)->next;
- } else if ((*ppScan)->Sequence == mpdu->Sequence) {
- /* give up this duplicated frame */
- return (FALSE);
- } else {
- /* find position */
- break;
- }
- }
-
- mpdu->next = *ppScan;
- *ppScan = mpdu;
- list->qlen++;
- return TRUE;
-}
-
-/*
- * caller lock critical section if necessary
- */
-static inline void ba_enqueue(struct reordering_list *list,
- struct reordering_mpdu *mpdu_blk)
-{
- list->qlen++;
- mpdu_blk->next = list->next;
- list->next = mpdu_blk;
-}
-
-/*
- * caller lock critical section if necessary
- */
-static inline struct reordering_mpdu *ba_dequeue(struct reordering_list *list)
-{
- struct reordering_mpdu *mpdu_blk = NULL;
-
- ASSERT(list);
-
- if (list->qlen) {
- list->qlen--;
- mpdu_blk = list->next;
- if (mpdu_blk) {
- list->next = mpdu_blk->next;
- mpdu_blk->next = NULL;
- }
- }
- return mpdu_blk;
-}
-
-static inline struct reordering_mpdu *ba_reordering_mpdu_dequeue(struct
- reordering_list
- *list)
-{
- return (ba_dequeue(list));
-}
-
-static inline struct reordering_mpdu *ba_reordering_mpdu_probe(struct
- reordering_list
- *list)
-{
- ASSERT(list);
-
- return (list->next);
-}
-
-/*
- * free all resource for reordering mechanism
- */
-void ba_reordering_resource_release(struct rt_rtmp_adapter *pAd)
-{
- struct rt_ba_table *Tab;
- struct rt_ba_rec_entry *pBAEntry;
- struct reordering_mpdu *mpdu_blk;
- int i;
-
- Tab = &pAd->BATable;
-
- /* I. release all pending reordering packet */
- NdisAcquireSpinLock(&pAd->BATabLock);
- for (i = 0; i < MAX_LEN_OF_BA_REC_TABLE; i++) {
- pBAEntry = &Tab->BARecEntry[i];
- if (pBAEntry->REC_BA_Status != Recipient_NONE) {
- while ((mpdu_blk =
- ba_reordering_mpdu_dequeue(&pBAEntry->list))) {
- ASSERT(mpdu_blk->pPacket);
- RELEASE_NDIS_PACKET(pAd, mpdu_blk->pPacket,
- NDIS_STATUS_FAILURE);
- ba_mpdu_blk_free(pAd, mpdu_blk);
- }
- }
- }
- NdisReleaseSpinLock(&pAd->BATabLock);
-
- ASSERT(pBAEntry->list.qlen == 0);
- /* II. free memory of reordering mpdu table */
- NdisAcquireSpinLock(&pAd->mpdu_blk_pool.lock);
- os_free_mem(pAd, pAd->mpdu_blk_pool.mem);
- NdisReleaseSpinLock(&pAd->mpdu_blk_pool.lock);
-}
-
-/*
- * Allocate all resource for reordering mechanism
- */
-BOOLEAN ba_reordering_resource_init(struct rt_rtmp_adapter *pAd, int num)
-{
- int i;
- u8 *mem;
- struct reordering_mpdu *mpdu_blk;
- struct reordering_list *freelist;
-
- /* allocate spinlock */
- NdisAllocateSpinLock(&pAd->mpdu_blk_pool.lock);
-
- /* initialize freelist */
- freelist = &pAd->mpdu_blk_pool.freelist;
- freelist->next = NULL;
- freelist->qlen = 0;
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("Allocate %d memory for BA reordering\n",
- (u32)(num * sizeof(struct reordering_mpdu))));
-
- /* allocate number of mpdu_blk memory */
- os_alloc_mem(pAd, (u8 **) & mem,
- (num * sizeof(struct reordering_mpdu)));
-
- pAd->mpdu_blk_pool.mem = mem;
-
- if (mem == NULL) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("Can't Allocate Memory for BA Reordering\n"));
- return (FALSE);
- }
-
- /* build mpdu_blk free list */
- for (i = 0; i < num; i++) {
- /* get mpdu_blk */
- mpdu_blk = (struct reordering_mpdu *)mem;
- /* initial mpdu_blk */
- NdisZeroMemory(mpdu_blk, sizeof(struct reordering_mpdu));
- /* next mpdu_blk */
- mem += sizeof(struct reordering_mpdu);
- /* insert mpdu_blk into freelist */
- ba_enqueue(freelist, mpdu_blk);
- }
-
- return (TRUE);
-}
-
-/*static int blk_count=0; // sample take off, no use */
-
-static struct reordering_mpdu *ba_mpdu_blk_alloc(struct rt_rtmp_adapter *pAd)
-{
- struct reordering_mpdu *mpdu_blk;
-
- NdisAcquireSpinLock(&pAd->mpdu_blk_pool.lock);
- mpdu_blk = ba_dequeue(&pAd->mpdu_blk_pool.freelist);
- if (mpdu_blk) {
-/* blk_count++; */
- /* reset mpdu_blk */
- NdisZeroMemory(mpdu_blk, sizeof(struct reordering_mpdu));
- }
- NdisReleaseSpinLock(&pAd->mpdu_blk_pool.lock);
- return mpdu_blk;
-}
-
-static void ba_mpdu_blk_free(struct rt_rtmp_adapter *pAd,
- struct reordering_mpdu *mpdu_blk)
-{
- ASSERT(mpdu_blk);
-
- NdisAcquireSpinLock(&pAd->mpdu_blk_pool.lock);
-/* blk_count--; */
- ba_enqueue(&pAd->mpdu_blk_pool.freelist, mpdu_blk);
- NdisReleaseSpinLock(&pAd->mpdu_blk_pool.lock);
-}
-
-static u16 ba_indicate_reordering_mpdus_in_order(struct rt_rtmp_adapter *pAd,
- struct rt_ba_rec_entry *pBAEntry,
- u16 StartSeq)
-{
- struct reordering_mpdu *mpdu_blk;
- u16 LastIndSeq = RESET_RCV_SEQ;
-
- NdisAcquireSpinLock(&pBAEntry->RxReRingLock);
-
- while ((mpdu_blk = ba_reordering_mpdu_probe(&pBAEntry->list))) {
- /* find in-order frame */
- if (!SEQ_STEPONE(mpdu_blk->Sequence, StartSeq, MAXSEQ)) {
- break;
- }
- /* dequeue in-order frame from reodering list */
- mpdu_blk = ba_reordering_mpdu_dequeue(&pBAEntry->list);
- /* pass this frame up */
- ANNOUNCE_REORDERING_PACKET(pAd, mpdu_blk);
- /* move to next sequence */
- StartSeq = mpdu_blk->Sequence;
- LastIndSeq = StartSeq;
- /* free mpdu_blk */
- ba_mpdu_blk_free(pAd, mpdu_blk);
- }
-
- NdisReleaseSpinLock(&pBAEntry->RxReRingLock);
-
- /* update last indicated sequence */
- return LastIndSeq;
-}
-
-static void ba_indicate_reordering_mpdus_le_seq(struct rt_rtmp_adapter *pAd,
- struct rt_ba_rec_entry *pBAEntry,
- u16 Sequence)
-{
- struct reordering_mpdu *mpdu_blk;
-
- NdisAcquireSpinLock(&pBAEntry->RxReRingLock);
- while ((mpdu_blk = ba_reordering_mpdu_probe(&pBAEntry->list))) {
- /* find in-order frame */
- if ((mpdu_blk->Sequence == Sequence)
- || SEQ_SMALLER(mpdu_blk->Sequence, Sequence, MAXSEQ)) {
- /* dequeue in-order frame from reodering list */
- mpdu_blk = ba_reordering_mpdu_dequeue(&pBAEntry->list);
- /* pass this frame up */
- ANNOUNCE_REORDERING_PACKET(pAd, mpdu_blk);
- /* free mpdu_blk */
- ba_mpdu_blk_free(pAd, mpdu_blk);
- } else {
- break;
- }
- }
- NdisReleaseSpinLock(&pBAEntry->RxReRingLock);
-}
-
-static void ba_refresh_reordering_mpdus(struct rt_rtmp_adapter *pAd,
- struct rt_ba_rec_entry *pBAEntry)
-{
- struct reordering_mpdu *mpdu_blk;
-
- NdisAcquireSpinLock(&pBAEntry->RxReRingLock);
-
- /* dequeue in-order frame from reodering list */
- while ((mpdu_blk = ba_reordering_mpdu_dequeue(&pBAEntry->list))) {
- /* pass this frame up */
- ANNOUNCE_REORDERING_PACKET(pAd, mpdu_blk);
-
- pBAEntry->LastIndSeq = mpdu_blk->Sequence;
- ba_mpdu_blk_free(pAd, mpdu_blk);
-
- /* update last indicated sequence */
- }
- ASSERT(pBAEntry->list.qlen == 0);
- pBAEntry->LastIndSeq = RESET_RCV_SEQ;
- NdisReleaseSpinLock(&pBAEntry->RxReRingLock);
-}
-
-/*static */
-void ba_flush_reordering_timeout_mpdus(struct rt_rtmp_adapter *pAd,
- struct rt_ba_rec_entry *pBAEntry,
- unsigned long Now32)
-{
- u16 Sequence;
-
-/* if ((RTMP_TIME_AFTER((unsigned long)Now32, (unsigned long)(pBAEntry->LastIndSeqAtTimer+REORDERING_PACKET_TIMEOUT)) && */
-/* (pBAEntry->list.qlen > ((pBAEntry->BAWinSize*7)/8))) //|| */
-/* (RTMP_TIME_AFTER((unsigned long)Now32, (unsigned long)(pBAEntry->LastIndSeqAtTimer+(10*REORDERING_PACKET_TIMEOUT))) && */
-/* (pBAEntry->list.qlen > (pBAEntry->BAWinSize/8))) */
- if (RTMP_TIME_AFTER
- ((unsigned long)Now32,
- (unsigned long)(pBAEntry->LastIndSeqAtTimer +
- (MAX_REORDERING_PACKET_TIMEOUT / 6)))
- && (pBAEntry->list.qlen > 1)
- ) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("timeout[%d] (%08lx-%08lx = %d > %d): %x, flush all!\n ",
- pBAEntry->list.qlen, Now32,
- (pBAEntry->LastIndSeqAtTimer),
- (int)((long)Now32 -
- (long)(pBAEntry->LastIndSeqAtTimer)),
- MAX_REORDERING_PACKET_TIMEOUT, pBAEntry->LastIndSeq));
- ba_refresh_reordering_mpdus(pAd, pBAEntry);
- pBAEntry->LastIndSeqAtTimer = Now32;
- } else
- if (RTMP_TIME_AFTER
- ((unsigned long)Now32,
- (unsigned long)(pBAEntry->LastIndSeqAtTimer +
- (REORDERING_PACKET_TIMEOUT)))
- && (pBAEntry->list.qlen > 0)
- ) {
- /* */
- /* force LastIndSeq to shift to LastIndSeq+1 */
- /* */
- Sequence = (pBAEntry->LastIndSeq + 1) & MAXSEQ;
- ba_indicate_reordering_mpdus_le_seq(pAd, pBAEntry, Sequence);
- pBAEntry->LastIndSeqAtTimer = Now32;
- pBAEntry->LastIndSeq = Sequence;
- /* */
- /* indicate in-order mpdus */
- /* */
- Sequence =
- ba_indicate_reordering_mpdus_in_order(pAd, pBAEntry,
- Sequence);
- if (Sequence != RESET_RCV_SEQ) {
- pBAEntry->LastIndSeq = Sequence;
- }
-
- DBGPRINT(RT_DEBUG_OFF,
- ("%x, flush one!\n", pBAEntry->LastIndSeq));
-
- }
-}
-
-/*
- * generate ADDBA request to
- * set up BA agreement
- */
-void BAOriSessionSetUp(struct rt_rtmp_adapter *pAd,
- struct rt_mac_table_entry *pEntry,
- u8 TID,
- u16 TimeOut,
- unsigned long DelayTime, IN BOOLEAN isForced)
-{
- /*struct rt_mlme_addba_req AddbaReq; */
- struct rt_ba_ori_entry *pBAEntry = NULL;
- u16 Idx;
- BOOLEAN Cancelled;
-
- if ((pAd->CommonCfg.BACapability.field.AutoBA != TRUE)
- && (isForced == FALSE))
- return;
-
- /* if this entry is limited to use legacy tx mode, it doesn't generate BA. */
- if (RTMPStaFixedTxMode(pAd, pEntry) != FIXED_TXMODE_HT)
- return;
-
- if ((pEntry->BADeclineBitmap & (1 << TID)) && (isForced == FALSE)) {
- /* try again after 3 secs */
- DelayTime = 3000;
-/* DBGPRINT(RT_DEBUG_TRACE, ("DeCline BA from Peer\n")); */
-/* return; */
- }
-
- Idx = pEntry->BAOriWcidArray[TID];
- if (Idx == 0) {
- /* allocate a BA session */
- pBAEntry = BATableAllocOriEntry(pAd, &Idx);
- if (pBAEntry == NULL) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("ADDBA - MlmeADDBAAction() allocate BA session failed \n"));
- return;
- }
- } else {
- pBAEntry = &pAd->BATable.BAOriEntry[Idx];
- }
-
- if (pBAEntry->ORI_BA_Status >= Originator_WaitRes) {
- return;
- }
-
- pEntry->BAOriWcidArray[TID] = Idx;
-
- /* Initialize BA session */
- pBAEntry->ORI_BA_Status = Originator_WaitRes;
- pBAEntry->Wcid = pEntry->Aid;
- pBAEntry->BAWinSize = pAd->CommonCfg.BACapability.field.RxBAWinLimit;
- pBAEntry->Sequence = BA_ORI_INIT_SEQ;
- pBAEntry->Token = 1; /* (2008-01-21) Jan Lee recommends it - this token can't be 0 */
- pBAEntry->TID = TID;
- pBAEntry->TimeOutValue = TimeOut;
- pBAEntry->pAdapter = pAd;
-
- if (!(pEntry->TXBAbitmap & (1 << TID))) {
- RTMPInitTimer(pAd, &pBAEntry->ORIBATimer,
- GET_TIMER_FUNCTION(BAOriSessionSetupTimeout),
- pBAEntry, FALSE);
- } else
- RTMPCancelTimer(&pBAEntry->ORIBATimer, &Cancelled);
-
- /* set timer to send ADDBA request */
- RTMPSetTimer(&pBAEntry->ORIBATimer, DelayTime);
-}
-
-void BAOriSessionAdd(struct rt_rtmp_adapter *pAd,
- struct rt_mac_table_entry *pEntry, struct rt_frame_addba_rsp * pFrame)
-{
- struct rt_ba_ori_entry *pBAEntry = NULL;
- BOOLEAN Cancelled;
- u8 TID;
- u16 Idx;
- u8 *pOutBuffer2 = NULL;
- int NStatus;
- unsigned long FrameLen;
- struct rt_frame_bar FrameBar;
-
- TID = pFrame->BaParm.TID;
- Idx = pEntry->BAOriWcidArray[TID];
- pBAEntry = &pAd->BATable.BAOriEntry[Idx];
-
- /* Start fill in parameters. */
- if ((Idx != 0) && (pBAEntry->TID == TID)
- && (pBAEntry->ORI_BA_Status == Originator_WaitRes)) {
- pBAEntry->BAWinSize =
- min(pBAEntry->BAWinSize, ((u8)pFrame->BaParm.BufSize));
- BA_MaxWinSizeReasign(pAd, pEntry, &pBAEntry->BAWinSize);
-
- pBAEntry->TimeOutValue = pFrame->TimeOutValue;
- pBAEntry->ORI_BA_Status = Originator_Done;
- pAd->BATable.numDoneOriginator++;
-
- /* reset sequence number */
- pBAEntry->Sequence = BA_ORI_INIT_SEQ;
- /* Set Bitmap flag. */
- pEntry->TXBAbitmap |= (1 << TID);
- RTMPCancelTimer(&pBAEntry->ORIBATimer, &Cancelled);
-
- pBAEntry->ORIBATimer.TimerValue = 0; /*pFrame->TimeOutValue; */
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("%s : TXBAbitmap = %x, BAWinSize = %d, TimeOut = %ld\n",
- __func__, pEntry->TXBAbitmap, pBAEntry->BAWinSize,
- pBAEntry->ORIBATimer.TimerValue));
-
- /* SEND BAR ; */
- NStatus = MlmeAllocateMemory(pAd, &pOutBuffer2); /*Get an unused nonpaged memory */
- if (NStatus != NDIS_STATUS_SUCCESS) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("BA - BAOriSessionAdd() allocate memory failed \n"));
- return;
- }
-
- BarHeaderInit(pAd, &FrameBar,
- pAd->MacTab.Content[pBAEntry->Wcid].Addr,
- pAd->CurrentAddress);
-
- FrameBar.StartingSeq.field.FragNum = 0; /* make sure sequence not clear in DEL function. */
- FrameBar.StartingSeq.field.StartSeq = pBAEntry->Sequence; /* make sure sequence not clear in DEL funciton. */
- FrameBar.BarControl.TID = pBAEntry->TID; /* make sure sequence not clear in DEL funciton. */
- MakeOutgoingFrame(pOutBuffer2, &FrameLen,
- sizeof(struct rt_frame_bar), &FrameBar, END_OF_ARGS);
- MiniportMMRequest(pAd, QID_AC_BE, pOutBuffer2, FrameLen);
- MlmeFreeMemory(pAd, pOutBuffer2);
-
- if (pBAEntry->ORIBATimer.TimerValue)
- RTMPSetTimer(&pBAEntry->ORIBATimer, pBAEntry->ORIBATimer.TimerValue); /* in mSec */
- }
-}
-
-BOOLEAN BARecSessionAdd(struct rt_rtmp_adapter *pAd,
- struct rt_mac_table_entry *pEntry, struct rt_frame_addba_req * pFrame)
-{
- struct rt_ba_rec_entry *pBAEntry = NULL;
- BOOLEAN Status = TRUE;
- BOOLEAN Cancelled;
- u16 Idx;
- u8 TID;
- u8 BAWinSize;
- /*u32 Value; */
- /*u32 offset; */
-
- ASSERT(pEntry);
-
- /* find TID */
- TID = pFrame->BaParm.TID;
-
- BAWinSize =
- min(((u8)pFrame->BaParm.BufSize),
- (u8)pAd->CommonCfg.BACapability.field.RxBAWinLimit);
-
- /* Intel patch */
- if (BAWinSize == 0) {
- BAWinSize = 64;
- }
-
- Idx = pEntry->BARecWcidArray[TID];
-
- if (Idx == 0) {
- pBAEntry = BATableAllocRecEntry(pAd, &Idx);
- } else {
- pBAEntry = &pAd->BATable.BARecEntry[Idx];
- /* flush all pending reordering mpdus */
- ba_refresh_reordering_mpdus(pAd, pBAEntry);
- }
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("%s(%ld): Idx = %d, BAWinSize(req %d) = %d\n", __func__,
- pAd->BATable.numAsRecipient, Idx, pFrame->BaParm.BufSize,
- BAWinSize));
-
- /* Start fill in parameters. */
- if (pBAEntry != NULL) {
- ASSERT(pBAEntry->list.qlen == 0);
-
- pBAEntry->REC_BA_Status = Recipient_HandleRes;
- pBAEntry->BAWinSize = BAWinSize;
- pBAEntry->Wcid = pEntry->Aid;
- pBAEntry->TID = TID;
- pBAEntry->TimeOutValue = pFrame->TimeOutValue;
- pBAEntry->REC_BA_Status = Recipient_Accept;
- /* initial sequence number */
- pBAEntry->LastIndSeq = RESET_RCV_SEQ; /*pFrame->BaStartSeq.field.StartSeq; */
-
- DBGPRINT(RT_DEBUG_OFF,
- ("Start Seq = %08x\n",
- pFrame->BaStartSeq.field.StartSeq));
-
- if (pEntry->RXBAbitmap & (1 << TID)) {
- RTMPCancelTimer(&pBAEntry->RECBATimer, &Cancelled);
- } else {
- RTMPInitTimer(pAd, &pBAEntry->RECBATimer,
- GET_TIMER_FUNCTION
- (BARecSessionIdleTimeout), pBAEntry,
- TRUE);
- }
-
- /* Set Bitmap flag. */
- pEntry->RXBAbitmap |= (1 << TID);
- pEntry->BARecWcidArray[TID] = Idx;
-
- pEntry->BADeclineBitmap &= ~(1 << TID);
-
- /* Set BA session mask in WCID table. */
- RTMP_ADD_BA_SESSION_TO_ASIC(pAd, pEntry->Aid, TID);
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("MACEntry[%d]RXBAbitmap = 0x%x. BARecWcidArray=%d\n",
- pEntry->Aid, pEntry->RXBAbitmap,
- pEntry->BARecWcidArray[TID]));
- } else {
- Status = FALSE;
- DBGPRINT(RT_DEBUG_TRACE,
- ("Can't Accept ADDBA for %pM TID = %d\n",
- pEntry->Addr, TID));
- }
- return (Status);
-}
-
-struct rt_ba_rec_entry *BATableAllocRecEntry(struct rt_rtmp_adapter *pAd, u16 * Idx)
-{
- int i;
- struct rt_ba_rec_entry *pBAEntry = NULL;
-
- NdisAcquireSpinLock(&pAd->BATabLock);
-
- if (pAd->BATable.numAsRecipient >= MAX_BARECI_SESSION) {
- DBGPRINT(RT_DEBUG_OFF, ("BA Recipeint Session (%ld) > %d\n",
- pAd->BATable.numAsRecipient,
- MAX_BARECI_SESSION));
- goto done;
- }
- /* reserve idx 0 to identify BAWcidArray[TID] as empty */
- for (i = 1; i < MAX_LEN_OF_BA_REC_TABLE; i++) {
- pBAEntry = &pAd->BATable.BARecEntry[i];
- if ((pBAEntry->REC_BA_Status == Recipient_NONE)) {
- /* get one */
- pAd->BATable.numAsRecipient++;
- pBAEntry->REC_BA_Status = Recipient_USED;
- *Idx = i;
- break;
- }
- }
-
-done:
- NdisReleaseSpinLock(&pAd->BATabLock);
- return pBAEntry;
-}
-
-struct rt_ba_ori_entry *BATableAllocOriEntry(struct rt_rtmp_adapter *pAd, u16 * Idx)
-{
- int i;
- struct rt_ba_ori_entry *pBAEntry = NULL;
-
- NdisAcquireSpinLock(&pAd->BATabLock);
-
- if (pAd->BATable.numAsOriginator >= (MAX_LEN_OF_BA_ORI_TABLE)) {
- goto done;
- }
- /* reserve idx 0 to identify BAWcidArray[TID] as empty */
- for (i = 1; i < MAX_LEN_OF_BA_ORI_TABLE; i++) {
- pBAEntry = &pAd->BATable.BAOriEntry[i];
- if ((pBAEntry->ORI_BA_Status == Originator_NONE)) {
- /* get one */
- pAd->BATable.numAsOriginator++;
- pBAEntry->ORI_BA_Status = Originator_USED;
- pBAEntry->pAdapter = pAd;
- *Idx = i;
- break;
- }
- }
-
-done:
- NdisReleaseSpinLock(&pAd->BATabLock);
- return pBAEntry;
-}
-
-void BATableFreeOriEntry(struct rt_rtmp_adapter *pAd, unsigned long Idx)
-{
- struct rt_ba_ori_entry *pBAEntry = NULL;
- struct rt_mac_table_entry *pEntry;
-
- if ((Idx == 0) || (Idx >= MAX_LEN_OF_BA_ORI_TABLE))
- return;
-
- pBAEntry = &pAd->BATable.BAOriEntry[Idx];
-
- if (pBAEntry->ORI_BA_Status != Originator_NONE) {
- pEntry = &pAd->MacTab.Content[pBAEntry->Wcid];
- pEntry->BAOriWcidArray[pBAEntry->TID] = 0;
-
- NdisAcquireSpinLock(&pAd->BATabLock);
- if (pBAEntry->ORI_BA_Status == Originator_Done) {
- pAd->BATable.numDoneOriginator -= 1;
- pEntry->TXBAbitmap &= (~(1 << (pBAEntry->TID)));
- DBGPRINT(RT_DEBUG_TRACE,
- ("BATableFreeOriEntry numAsOriginator= %ld\n",
- pAd->BATable.numAsRecipient));
- /* Erase Bitmap flag. */
- }
-
- ASSERT(pAd->BATable.numAsOriginator != 0);
-
- pAd->BATable.numAsOriginator -= 1;
-
- pBAEntry->ORI_BA_Status = Originator_NONE;
- pBAEntry->Token = 0;
- NdisReleaseSpinLock(&pAd->BATabLock);
- }
-}
-
-void BATableFreeRecEntry(struct rt_rtmp_adapter *pAd, unsigned long Idx)
-{
- struct rt_ba_rec_entry *pBAEntry = NULL;
- struct rt_mac_table_entry *pEntry;
-
- if ((Idx == 0) || (Idx >= MAX_LEN_OF_BA_REC_TABLE))
- return;
-
- pBAEntry = &pAd->BATable.BARecEntry[Idx];
-
- if (pBAEntry->REC_BA_Status != Recipient_NONE) {
- pEntry = &pAd->MacTab.Content[pBAEntry->Wcid];
- pEntry->BARecWcidArray[pBAEntry->TID] = 0;
-
- NdisAcquireSpinLock(&pAd->BATabLock);
-
- ASSERT(pAd->BATable.numAsRecipient != 0);
-
- pAd->BATable.numAsRecipient -= 1;
-
- pBAEntry->REC_BA_Status = Recipient_NONE;
- NdisReleaseSpinLock(&pAd->BATabLock);
- }
-}
-
-void BAOriSessionTearDown(struct rt_rtmp_adapter *pAd,
- u8 Wcid,
- u8 TID,
- IN BOOLEAN bPassive, IN BOOLEAN bForceSend)
-{
- unsigned long Idx = 0;
- struct rt_ba_ori_entry *pBAEntry;
- BOOLEAN Cancelled;
-
- if (Wcid >= MAX_LEN_OF_MAC_TABLE) {
- return;
- }
- /* */
- /* Locate corresponding BA Originator Entry in BA Table with the (pAddr,TID). */
- /* */
- Idx = pAd->MacTab.Content[Wcid].BAOriWcidArray[TID];
- if ((Idx == 0) || (Idx >= MAX_LEN_OF_BA_ORI_TABLE)) {
- if (bForceSend == TRUE) {
- /* force send specified TID DelBA */
- struct rt_mlme_delba_req DelbaReq;
- struct rt_mlme_queue_elem *Elem =
- kmalloc(sizeof(struct rt_mlme_queue_elem),
- MEM_ALLOC_FLAG);
- if (Elem != NULL) {
- NdisZeroMemory(&DelbaReq, sizeof(DelbaReq));
- NdisZeroMemory(Elem, sizeof(struct rt_mlme_queue_elem));
-
- COPY_MAC_ADDR(DelbaReq.Addr,
- pAd->MacTab.Content[Wcid].Addr);
- DelbaReq.Wcid = Wcid;
- DelbaReq.TID = TID;
- DelbaReq.Initiator = ORIGINATOR;
- Elem->MsgLen = sizeof(DelbaReq);
- NdisMoveMemory(Elem->Msg, &DelbaReq,
- sizeof(DelbaReq));
- MlmeDELBAAction(pAd, Elem);
- kfree(Elem);
- } else {
- DBGPRINT(RT_DEBUG_ERROR,
- ("%s(bForceSend):alloc memory failed!\n",
- __func__));
- }
- }
-
- return;
- }
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("%s===>Wcid=%d.TID=%d \n", __func__, Wcid, TID));
-
- pBAEntry = &pAd->BATable.BAOriEntry[Idx];
- DBGPRINT(RT_DEBUG_TRACE,
- ("\t===>Idx = %ld, Wcid=%d.TID=%d, ORI_BA_Status = %d \n", Idx,
- Wcid, TID, pBAEntry->ORI_BA_Status));
- /* */
- /* Prepare DelBA action frame and send to the peer. */
- /* */
- if ((bPassive == FALSE) && (TID == pBAEntry->TID)
- && (pBAEntry->ORI_BA_Status == Originator_Done)) {
- struct rt_mlme_delba_req DelbaReq;
- struct rt_mlme_queue_elem *Elem =
- kmalloc(sizeof(struct rt_mlme_queue_elem),
- MEM_ALLOC_FLAG);
- if (Elem != NULL) {
- NdisZeroMemory(&DelbaReq, sizeof(DelbaReq));
- NdisZeroMemory(Elem, sizeof(struct rt_mlme_queue_elem));
-
- COPY_MAC_ADDR(DelbaReq.Addr,
- pAd->MacTab.Content[Wcid].Addr);
- DelbaReq.Wcid = Wcid;
- DelbaReq.TID = pBAEntry->TID;
- DelbaReq.Initiator = ORIGINATOR;
- Elem->MsgLen = sizeof(DelbaReq);
- NdisMoveMemory(Elem->Msg, &DelbaReq, sizeof(DelbaReq));
- MlmeDELBAAction(pAd, Elem);
- kfree(Elem);
- } else {
- DBGPRINT(RT_DEBUG_ERROR,
- ("%s():alloc memory failed!\n", __func__));
- return;
- }
- }
- RTMPCancelTimer(&pBAEntry->ORIBATimer, &Cancelled);
- BATableFreeOriEntry(pAd, Idx);
-
- if (bPassive) {
- /*BAOriSessionSetUp(pAd, &pAd->MacTab.Content[Wcid], TID, 0, 10000, TRUE); */
- }
-}
-
-void BARecSessionTearDown(struct rt_rtmp_adapter *pAd,
- u8 Wcid, u8 TID, IN BOOLEAN bPassive)
-{
- unsigned long Idx = 0;
- struct rt_ba_rec_entry *pBAEntry;
-
- if (Wcid >= MAX_LEN_OF_MAC_TABLE) {
- return;
- }
- /* */
- /* Locate corresponding BA Originator Entry in BA Table with the (pAddr,TID). */
- /* */
- Idx = pAd->MacTab.Content[Wcid].BARecWcidArray[TID];
- if (Idx == 0)
- return;
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("%s===>Wcid=%d.TID=%d \n", __func__, Wcid, TID));
-
- pBAEntry = &pAd->BATable.BARecEntry[Idx];
- DBGPRINT(RT_DEBUG_TRACE,
- ("\t===>Idx = %ld, Wcid=%d.TID=%d, REC_BA_Status = %d \n", Idx,
- Wcid, TID, pBAEntry->REC_BA_Status));
- /* */
- /* Prepare DelBA action frame and send to the peer. */
- /* */
- if ((TID == pBAEntry->TID)
- && (pBAEntry->REC_BA_Status == Recipient_Accept)) {
- struct rt_mlme_delba_req DelbaReq;
- BOOLEAN Cancelled;
- /*unsigned long offset; */
- /*u32 VALUE; */
-
- RTMPCancelTimer(&pBAEntry->RECBATimer, &Cancelled);
-
- /* */
- /* 1. Send DELBA Action Frame */
- /* */
- if (bPassive == FALSE) {
- struct rt_mlme_queue_elem *Elem =
- kmalloc(sizeof(struct rt_mlme_queue_elem),
- MEM_ALLOC_FLAG);
- if (Elem != NULL) {
- NdisZeroMemory(&DelbaReq, sizeof(DelbaReq));
- NdisZeroMemory(Elem, sizeof(struct rt_mlme_queue_elem));
-
- COPY_MAC_ADDR(DelbaReq.Addr,
- pAd->MacTab.Content[Wcid].Addr);
- DelbaReq.Wcid = Wcid;
- DelbaReq.TID = TID;
- DelbaReq.Initiator = RECIPIENT;
- Elem->MsgLen = sizeof(DelbaReq);
- NdisMoveMemory(Elem->Msg, &DelbaReq,
- sizeof(DelbaReq));
- MlmeDELBAAction(pAd, Elem);
- kfree(Elem);
- } else {
- DBGPRINT(RT_DEBUG_ERROR,
- ("%s():alloc memory failed!\n",
- __func__));
- return;
- }
- }
-
- /* */
- /* 2. Free resource of BA session */
- /* */
- /* flush all pending reordering mpdus */
- ba_refresh_reordering_mpdus(pAd, pBAEntry);
-
- NdisAcquireSpinLock(&pAd->BATabLock);
-
- /* Erase Bitmap flag. */
- pBAEntry->LastIndSeq = RESET_RCV_SEQ;
- pBAEntry->BAWinSize = 0;
- /* Erase Bitmap flag at software mactable */
- pAd->MacTab.Content[Wcid].RXBAbitmap &=
- (~(1 << (pBAEntry->TID)));
- pAd->MacTab.Content[Wcid].BARecWcidArray[TID] = 0;
-
- RTMP_DEL_BA_SESSION_FROM_ASIC(pAd, Wcid, TID);
-
- NdisReleaseSpinLock(&pAd->BATabLock);
-
- }
-
- BATableFreeRecEntry(pAd, Idx);
-}
-
-void BASessionTearDownALL(struct rt_rtmp_adapter *pAd, u8 Wcid)
-{
- int i;
-
- for (i = 0; i < NUM_OF_TID; i++) {
- BAOriSessionTearDown(pAd, Wcid, i, FALSE, FALSE);
- BARecSessionTearDown(pAd, Wcid, i, FALSE);
- }
-}
-
-/*
- ==========================================================================
- Description:
- Retry sending ADDBA Reqest.
-
- IRQL = DISPATCH_LEVEL
-
- Parametrs:
- p8023Header: if this is already 802.3 format, p8023Header is NULL
-
- Return : TRUE if put into rx reordering buffer, shouldn't indicaterxhere.
- FALSE , then continue indicaterx at this moment.
- ==========================================================================
- */
-void BAOriSessionSetupTimeout(void *SystemSpecific1,
- void *FunctionContext,
- void *SystemSpecific2,
- void *SystemSpecific3)
-{
- struct rt_ba_ori_entry *pBAEntry = (struct rt_ba_ori_entry *)FunctionContext;
- struct rt_mac_table_entry *pEntry;
- struct rt_rtmp_adapter *pAd;
-
- if (pBAEntry == NULL)
- return;
-
- pAd = pBAEntry->pAdapter;
-
- {
- /* Do nothing if monitor mode is on */
- if (MONITOR_ON(pAd))
- return;
- }
-
- pEntry = &pAd->MacTab.Content[pBAEntry->Wcid];
-
- if ((pBAEntry->ORI_BA_Status == Originator_WaitRes)
- && (pBAEntry->Token < ORI_SESSION_MAX_RETRY)) {
- struct rt_mlme_addba_req AddbaReq;
-
- NdisZeroMemory(&AddbaReq, sizeof(AddbaReq));
- COPY_MAC_ADDR(AddbaReq.pAddr, pEntry->Addr);
- AddbaReq.Wcid = (u8)(pEntry->Aid);
- AddbaReq.TID = pBAEntry->TID;
- AddbaReq.BaBufSize =
- pAd->CommonCfg.BACapability.field.RxBAWinLimit;
- AddbaReq.TimeOutValue = 0;
- AddbaReq.Token = pBAEntry->Token;
- MlmeEnqueue(pAd, ACTION_STATE_MACHINE, MT2_MLME_ADD_BA_CATE,
- sizeof(struct rt_mlme_addba_req), (void *)& AddbaReq);
- RTMP_MLME_HANDLER(pAd);
- DBGPRINT(RT_DEBUG_TRACE,
- ("BA Ori Session Timeout(%d) : Send ADD BA again\n",
- pBAEntry->Token));
-
- pBAEntry->Token++;
- RTMPSetTimer(&pBAEntry->ORIBATimer, ORI_BA_SESSION_TIMEOUT);
- } else {
- BATableFreeOriEntry(pAd, pEntry->BAOriWcidArray[pBAEntry->TID]);
- }
-}
-
-/*
- ==========================================================================
- Description:
- Retry sending ADDBA Reqest.
-
- IRQL = DISPATCH_LEVEL
-
- Parametrs:
- p8023Header: if this is already 802.3 format, p8023Header is NULL
-
- Return : TRUE if put into rx reordering buffer, shouldn't indicaterxhere.
- FALSE , then continue indicaterx at this moment.
- ==========================================================================
- */
-void BARecSessionIdleTimeout(void *SystemSpecific1,
- void *FunctionContext,
- void *SystemSpecific2, void *SystemSpecific3)
-{
-
- struct rt_ba_rec_entry *pBAEntry = (struct rt_ba_rec_entry *)FunctionContext;
- struct rt_rtmp_adapter *pAd;
- unsigned long Now32;
-
- if (pBAEntry == NULL)
- return;
-
- if ((pBAEntry->REC_BA_Status == Recipient_Accept)) {
- NdisGetSystemUpTime(&Now32);
-
- if (RTMP_TIME_AFTER
- ((unsigned long)Now32,
- (unsigned long)(pBAEntry->LastIndSeqAtTimer +
- REC_BA_SESSION_IDLE_TIMEOUT))) {
- pAd = pBAEntry->pAdapter;
- /* flush all pending reordering mpdus */
- ba_refresh_reordering_mpdus(pAd, pBAEntry);
- DBGPRINT(RT_DEBUG_OFF,
- ("%ld: REC BA session Timeout\n", Now32));
- }
- }
-}
-
-void PeerAddBAReqAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
- /* 7.4.4.1 */
- /*unsigned long Idx; */
- u8 Status = 1;
- u8 pAddr[6];
- struct rt_frame_addba_rsp ADDframe;
- u8 *pOutBuffer = NULL;
- int NStatus;
- struct rt_frame_addba_req * pAddreqFrame = NULL;
- /*u8 BufSize; */
- unsigned long FrameLen;
- unsigned long *ptemp;
- struct rt_mac_table_entry *pMacEntry;
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("%s ==> (Wcid = %d)\n", __func__, Elem->Wcid));
-
- /*hex_dump("AddBAReq", Elem->Msg, Elem->MsgLen); */
-
- /*ADDBA Request from unknown peer, ignore this. */
- if (Elem->Wcid >= MAX_LEN_OF_MAC_TABLE)
- return;
-
- pMacEntry = &pAd->MacTab.Content[Elem->Wcid];
- DBGPRINT(RT_DEBUG_TRACE, ("BA - PeerAddBAReqAction----> \n"));
- ptemp = (unsigned long *)Elem->Msg;
- /*DBGPRINT_RAW(RT_DEBUG_EMU, ("%08x:: %08x:: %08x:: %08x:: %08x:: %08x:: %08x:: %08x:: %08x\n", *(ptemp), *(ptemp+1), *(ptemp+2), *(ptemp+3), *(ptemp+4), *(ptemp+5), *(ptemp+6), *(ptemp+7), *(ptemp+8))); */
-
- if (PeerAddBAReqActionSanity(pAd, Elem->Msg, Elem->MsgLen, pAddr)) {
-
- if ((pAd->CommonCfg.bBADecline == FALSE)
- && IS_HT_STA(pMacEntry)) {
- pAddreqFrame = (struct rt_frame_addba_req *) (&Elem->Msg[0]);
- DBGPRINT(RT_DEBUG_OFF,
- ("Rcv Wcid(%d) AddBAReq\n", Elem->Wcid));
- if (BARecSessionAdd
- (pAd, &pAd->MacTab.Content[Elem->Wcid],
- pAddreqFrame))
- Status = 0;
- else
- Status = 38; /* more parameters have invalid values */
- } else {
- Status = 37; /* the request has been declined. */
- }
- }
-
- if (pAd->MacTab.Content[Elem->Wcid].ValidAsCLI)
- ASSERT(pAd->MacTab.Content[Elem->Wcid].Sst == SST_ASSOC);
-
- pAddreqFrame = (struct rt_frame_addba_req *) (&Elem->Msg[0]);
- /* 2. Always send back ADDBA Response */
- NStatus = MlmeAllocateMemory(pAd, &pOutBuffer); /*Get an unused nonpaged memory */
- if (NStatus != NDIS_STATUS_SUCCESS) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("ACTION - PeerBAAction() allocate memory failed \n"));
- return;
- }
-
- NdisZeroMemory(&ADDframe, sizeof(struct rt_frame_addba_rsp));
-
- /* 2-1. Prepare ADDBA Response frame. */
- {
- if (ADHOC_ON(pAd))
- ActHeaderInit(pAd, &ADDframe.Hdr, pAddr,
- pAd->CurrentAddress,
- pAd->CommonCfg.Bssid);
- else
- ActHeaderInit(pAd, &ADDframe.Hdr, pAd->CommonCfg.Bssid,
- pAd->CurrentAddress, pAddr);
- }
-
- ADDframe.Category = CATEGORY_BA;
- ADDframe.Action = ADDBA_RESP;
- ADDframe.Token = pAddreqFrame->Token;
- /* What is the Status code?? need to check. */
- ADDframe.StatusCode = Status;
- ADDframe.BaParm.BAPolicy = IMMED_BA;
- ADDframe.BaParm.AMSDUSupported = 0;
- ADDframe.BaParm.TID = pAddreqFrame->BaParm.TID;
- ADDframe.BaParm.BufSize =
- min(((u8)pAddreqFrame->BaParm.BufSize),
- (u8)pAd->CommonCfg.BACapability.field.RxBAWinLimit);
- if (ADDframe.BaParm.BufSize == 0) {
- ADDframe.BaParm.BufSize = 64;
- }
- ADDframe.TimeOutValue = 0; /*pAddreqFrame->TimeOutValue; */
-
- *(u16 *) (&ADDframe.BaParm) =
- cpu2le16(*(u16 *) (&ADDframe.BaParm));
- ADDframe.StatusCode = cpu2le16(ADDframe.StatusCode);
- ADDframe.TimeOutValue = cpu2le16(ADDframe.TimeOutValue);
-
- MakeOutgoingFrame(pOutBuffer, &FrameLen,
- sizeof(struct rt_frame_addba_rsp), &ADDframe, END_OF_ARGS);
- MiniportMMRequest(pAd, QID_AC_BE, pOutBuffer, FrameLen);
- MlmeFreeMemory(pAd, pOutBuffer);
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("%s(%d): TID(%d), BufSize(%d) <== \n", __func__, Elem->Wcid,
- ADDframe.BaParm.TID, ADDframe.BaParm.BufSize));
-}
-
-void PeerAddBARspAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
- /*u8 Idx, i; */
- /*u8 * pOutBuffer = NULL; */
- struct rt_frame_addba_rsp * pFrame = NULL;
- /*struct rt_ba_ori_entry *pBAEntry; */
-
- /*ADDBA Response from unknown peer, ignore this. */
- if (Elem->Wcid >= MAX_LEN_OF_MAC_TABLE)
- return;
-
- DBGPRINT(RT_DEBUG_TRACE, ("%s ==> Wcid(%d)\n", __func__, Elem->Wcid));
-
- /*hex_dump("PeerAddBARspAction()", Elem->Msg, Elem->MsgLen); */
-
- if (PeerAddBARspActionSanity(pAd, Elem->Msg, Elem->MsgLen)) {
- pFrame = (struct rt_frame_addba_rsp *) (&Elem->Msg[0]);
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("\t\t StatusCode = %d\n", pFrame->StatusCode));
- switch (pFrame->StatusCode) {
- case 0:
- /* I want a BAsession with this peer as an originator. */
- BAOriSessionAdd(pAd, &pAd->MacTab.Content[Elem->Wcid],
- pFrame);
- break;
- default:
- /* check status == USED ??? */
- BAOriSessionTearDown(pAd, Elem->Wcid,
- pFrame->BaParm.TID, TRUE, FALSE);
- break;
- }
- /* Rcv Decline StatusCode */
- if ((pFrame->StatusCode == 37)
- || ((pAd->OpMode == OPMODE_STA) && STA_TGN_WIFI_ON(pAd)
- && (pFrame->StatusCode != 0))
- ) {
- pAd->MacTab.Content[Elem->Wcid].BADeclineBitmap |=
- 1 << pFrame->BaParm.TID;
- }
- }
-}
-
-void PeerDelBAAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
- /*u8 Idx; */
- /*u8 * pOutBuffer = NULL; */
- struct rt_frame_delba_req * pDelFrame = NULL;
-
- DBGPRINT(RT_DEBUG_TRACE, ("%s ==>\n", __func__));
- /*DELBA Request from unknown peer, ignore this. */
- if (PeerDelBAActionSanity(pAd, Elem->Wcid, Elem->Msg, Elem->MsgLen)) {
- pDelFrame = (struct rt_frame_delba_req *) (&Elem->Msg[0]);
- if (pDelFrame->DelbaParm.Initiator == ORIGINATOR) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("BA - PeerDelBAAction----> ORIGINATOR\n"));
- BARecSessionTearDown(pAd, Elem->Wcid,
- pDelFrame->DelbaParm.TID, TRUE);
- } else {
- DBGPRINT(RT_DEBUG_TRACE,
- ("BA - PeerDelBAAction----> RECIPIENT, Reason = %d\n",
- pDelFrame->ReasonCode));
- /*hex_dump("DelBA Frame", pDelFrame, Elem->MsgLen); */
- BAOriSessionTearDown(pAd, Elem->Wcid,
- pDelFrame->DelbaParm.TID, TRUE,
- FALSE);
- }
- }
-}
-
-BOOLEAN CntlEnqueueForRecv(struct rt_rtmp_adapter *pAd,
- unsigned long Wcid,
- unsigned long MsgLen, struct rt_frame_ba_req * pMsg)
-{
- struct rt_frame_ba_req * pFrame = pMsg;
- /*PRTMP_REORDERBUF pBuffer; */
- /*PRTMP_REORDERBUF pDmaBuf; */
- struct rt_ba_rec_entry *pBAEntry;
- /*BOOLEAN Result; */
- unsigned long Idx;
- /*u8 NumRxPkt; */
- u8 TID; /*, i; */
-
- TID = (u8)pFrame->BARControl.TID;
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("%s(): BAR-Wcid(%ld), Tid (%d)\n", __func__, Wcid, TID));
- /*hex_dump("BAR", (char *)pFrame, MsgLen); */
- /* Do nothing if the driver is starting halt state. */
- /* This might happen when timer already been fired before cancel timer with mlmehalt */
- if (RTMP_TEST_FLAG
- (pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS | fRTMP_ADAPTER_NIC_NOT_EXIST))
- return FALSE;
-
- /* First check the size, it MUST not exceed the mlme queue size */
- if (MsgLen > MGMT_DMA_BUFFER_SIZE) {
- DBGPRINT_ERR("CntlEnqueueForRecv: frame too large, size = %ld \n", MsgLen);
- return FALSE;
- } else if (MsgLen != sizeof(struct rt_frame_ba_req)) {
- DBGPRINT_ERR("CntlEnqueueForRecv: BlockAck Request frame length size = %ld incorrect\n", MsgLen);
- return FALSE;
- } else if (MsgLen != sizeof(struct rt_frame_ba_req)) {
- DBGPRINT_ERR("CntlEnqueueForRecv: BlockAck Request frame length size = %ld incorrect\n", MsgLen);
- return FALSE;
- }
-
- if ((Wcid < MAX_LEN_OF_MAC_TABLE) && (TID < 8)) {
- /* if this receiving packet is from SA that is in our OriEntry. Since WCID <9 has direct mapping. no need search. */
- Idx = pAd->MacTab.Content[Wcid].BARecWcidArray[TID];
- pBAEntry = &pAd->BATable.BARecEntry[Idx];
- } else {
- return FALSE;
- }
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("BAR(%ld) : Tid (%d) - %04x:%04x\n", Wcid, TID,
- pFrame->BAStartingSeq.field.StartSeq, pBAEntry->LastIndSeq));
-
- if (SEQ_SMALLER
- (pBAEntry->LastIndSeq, pFrame->BAStartingSeq.field.StartSeq,
- MAXSEQ)) {
- /*DBGPRINT(RT_DEBUG_TRACE, ("BAR Seq = %x, LastIndSeq = %x\n", pFrame->BAStartingSeq.field.StartSeq, pBAEntry->LastIndSeq)); */
- ba_indicate_reordering_mpdus_le_seq(pAd, pBAEntry,
- pFrame->BAStartingSeq.field.
- StartSeq);
- pBAEntry->LastIndSeq =
- (pFrame->BAStartingSeq.field.StartSeq ==
- 0) ? MAXSEQ : (pFrame->BAStartingSeq.field.StartSeq - 1);
- }
- /*ba_refresh_reordering_mpdus(pAd, pBAEntry); */
- return TRUE;
-}
-
-/*
-Description : Send PSMP Action frame If PSMP mode switches.
-*/
-void SendPSMPAction(struct rt_rtmp_adapter *pAd, u8 Wcid, u8 Psmp)
-{
- u8 *pOutBuffer = NULL;
- int NStatus;
- /*unsigned long Idx; */
- struct rt_frame_psmp_action Frame;
- unsigned long FrameLen;
-
- NStatus = MlmeAllocateMemory(pAd, &pOutBuffer); /*Get an unused nonpaged memory */
- if (NStatus != NDIS_STATUS_SUCCESS) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("BA - MlmeADDBAAction() allocate memory failed \n"));
- return;
- }
-
- ActHeaderInit(pAd, &Frame.Hdr, pAd->CommonCfg.Bssid,
- pAd->CurrentAddress, pAd->MacTab.Content[Wcid].Addr);
-
- Frame.Category = CATEGORY_HT;
- Frame.Action = SMPS_ACTION;
- switch (Psmp) {
- case MMPS_ENABLE:
-#ifdef RT30xx
- if (IS_RT30xx(pAd)
- && (pAd->Antenna.field.RxPath > 1
- || pAd->Antenna.field.TxPath > 1)) {
- RTMP_ASIC_MMPS_DISABLE(pAd);
- }
-#endif /* RT30xx // */
- Frame.Psmp = 0;
- break;
- case MMPS_DYNAMIC:
- Frame.Psmp = 3;
- break;
- case MMPS_STATIC:
-#ifdef RT30xx
- if (IS_RT30xx(pAd)
- && (pAd->Antenna.field.RxPath > 1
- || pAd->Antenna.field.TxPath > 1)) {
- RTMP_ASIC_MMPS_ENABLE(pAd);
- }
-#endif /* RT30xx // */
- Frame.Psmp = 1;
- break;
- }
- MakeOutgoingFrame(pOutBuffer, &FrameLen,
- sizeof(struct rt_frame_psmp_action), &Frame, END_OF_ARGS);
- MiniportMMRequest(pAd, QID_AC_BE, pOutBuffer, FrameLen);
- MlmeFreeMemory(pAd, pOutBuffer);
- DBGPRINT(RT_DEBUG_ERROR, ("HT - SendPSMPAction( %d ) \n", Frame.Psmp));
-}
-
-#define RADIO_MEASUREMENT_REQUEST_ACTION 0
-
-struct PACKED rt_beacon_request {
- u8 RegulatoryClass;
- u8 ChannelNumber;
- u16 RandomInterval;
- u16 MeasurementDuration;
- u8 MeasurementMode;
- u8 BSSID[MAC_ADDR_LEN];
- u8 ReportingCondition;
- u8 Threshold;
- u8 SSIDIE[2]; /* 2 byte */
-};
-
-struct PACKED rt_measurement_req {
- u8 ID;
- u8 Length;
- u8 Token;
- u8 RequestMode;
- u8 Type;
-};
-
-void convert_reordering_packet_to_preAMSDU_or_802_3_packet(struct rt_rtmp_adapter *pAd,
- struct rt_rx_blk *pRxBlk,
- u8
- FromWhichBSSID)
-{
- void *pRxPkt;
- u8 Header802_3[LENGTH_802_3];
-
- /* 1. get 802.3 Header */
- /* 2. remove LLC */
- /* a. pointer pRxBlk->pData to payload */
- /* b. modify pRxBlk->DataSize */
-
- RTMP_802_11_REMOVE_LLC_AND_CONVERT_TO_802_3(pRxBlk, Header802_3);
-
- ASSERT(pRxBlk->pRxPacket);
- pRxPkt = RTPKT_TO_OSPKT(pRxBlk->pRxPacket);
-
- SET_OS_PKT_NETDEV(pRxPkt, get_netdev_from_bssid(pAd, FromWhichBSSID));
- SET_OS_PKT_DATAPTR(pRxPkt, pRxBlk->pData);
- SET_OS_PKT_LEN(pRxPkt, pRxBlk->DataSize);
- SET_OS_PKT_DATATAIL(pRxPkt, pRxBlk->pData, pRxBlk->DataSize);
-
- /* */
- /* copy 802.3 header, if necessary */
- /* */
- if (!RX_BLK_TEST_FLAG(pRxBlk, fRX_AMSDU)) {
- {
-#ifdef LINUX
- NdisMoveMemory(skb_push(pRxPkt, LENGTH_802_3),
- Header802_3, LENGTH_802_3);
-#endif
- }
- }
-}
-
-#define INDICATE_LEGACY_OR_AMSDU(_pAd, _pRxBlk, _fromWhichBSSID) \
- do \
- { \
- if (RX_BLK_TEST_FLAG(_pRxBlk, fRX_AMSDU)) \
- { \
- Indicate_AMSDU_Packet(_pAd, _pRxBlk, _fromWhichBSSID); \
- } \
- else if (RX_BLK_TEST_FLAG(_pRxBlk, fRX_EAP)) \
- { \
- Indicate_EAPOL_Packet(_pAd, _pRxBlk, _fromWhichBSSID); \
- } \
- else \
- { \
- Indicate_Legacy_Packet(_pAd, _pRxBlk, _fromWhichBSSID); \
- } \
- } while (0);
-
-static void ba_enqueue_reordering_packet(struct rt_rtmp_adapter *pAd,
- struct rt_ba_rec_entry *pBAEntry,
- struct rt_rx_blk *pRxBlk,
- u8 FromWhichBSSID)
-{
- struct reordering_mpdu *mpdu_blk;
- u16 Sequence = (u16)pRxBlk->pHeader->Sequence;
-
- mpdu_blk = ba_mpdu_blk_alloc(pAd);
- if ((mpdu_blk != NULL) && (!RX_BLK_TEST_FLAG(pRxBlk, fRX_EAP))) {
- /* Write RxD buffer address & allocated buffer length */
- NdisAcquireSpinLock(&pBAEntry->RxReRingLock);
-
- mpdu_blk->Sequence = Sequence;
-
- mpdu_blk->bAMSDU = RX_BLK_TEST_FLAG(pRxBlk, fRX_AMSDU);
-
- convert_reordering_packet_to_preAMSDU_or_802_3_packet(pAd,
- pRxBlk,
- FromWhichBSSID);
-
- STATS_INC_RX_PACKETS(pAd, FromWhichBSSID);
-
- /* */
- /* it is necessary for reordering packet to record */
- /* which BSS it come from */
- /* */
- RTMP_SET_PACKET_IF(pRxBlk->pRxPacket, FromWhichBSSID);
-
- mpdu_blk->pPacket = pRxBlk->pRxPacket;
-
- if (ba_reordering_mpdu_insertsorted(&pBAEntry->list, mpdu_blk)
- == FALSE) {
- /* had been already within reordering list */
- /* don't indicate */
- RELEASE_NDIS_PACKET(pAd, pRxBlk->pRxPacket,
- NDIS_STATUS_SUCCESS);
- ba_mpdu_blk_free(pAd, mpdu_blk);
- }
-
- ASSERT((0 <= pBAEntry->list.qlen)
- && (pBAEntry->list.qlen <= pBAEntry->BAWinSize));
- NdisReleaseSpinLock(&pBAEntry->RxReRingLock);
- } else {
- DBGPRINT(RT_DEBUG_ERROR,
- (" (%d) Can't allocate reordering mpdu blk\n",
- pBAEntry->list.qlen));
-
- /*
- * flush all pending reordering mpdus
- * and receiving mpdu to upper layer
- * make tcp/ip to take care reordering mechanism
- */
- /*ba_refresh_reordering_mpdus(pAd, pBAEntry); */
- ba_indicate_reordering_mpdus_le_seq(pAd, pBAEntry, Sequence);
-
- pBAEntry->LastIndSeq = Sequence;
- INDICATE_LEGACY_OR_AMSDU(pAd, pRxBlk, FromWhichBSSID);
- }
-}
-
-/*
- ==========================================================================
- Description:
- Indicate this packet to upper layer or put it into reordering buffer
-
- Parametrs:
- pRxBlk : carry necessary packet info 802.11 format
- FromWhichBSSID : the packet received from which BSS
-
- Return :
- none
-
- Note :
- the packet queued into reordering buffer need to cover to 802.3 format
- or pre_AMSDU format
- ==========================================================================
- */
-
-void Indicate_AMPDU_Packet(struct rt_rtmp_adapter *pAd,
- struct rt_rx_blk *pRxBlk, u8 FromWhichBSSID)
-{
- u16 Idx;
- struct rt_ba_rec_entry *pBAEntry = NULL;
- u16 Sequence = pRxBlk->pHeader->Sequence;
- unsigned long Now32;
- u8 Wcid = pRxBlk->pRxWI->WirelessCliID;
- u8 TID = pRxBlk->pRxWI->TID;
-
- if (!RX_BLK_TEST_FLAG(pRxBlk, fRX_AMSDU)
- && (pRxBlk->DataSize > MAX_RX_PKT_LEN)) {
- /* release packet */
- RELEASE_NDIS_PACKET(pAd, pRxBlk->pRxPacket,
- NDIS_STATUS_FAILURE);
- return;
- }
-
- if (Wcid < MAX_LEN_OF_MAC_TABLE) {
- Idx = pAd->MacTab.Content[Wcid].BARecWcidArray[TID];
- if (Idx == 0) {
- /* Rec BA Session had been torn down */
- INDICATE_LEGACY_OR_AMSDU(pAd, pRxBlk, FromWhichBSSID);
- return;
- }
- pBAEntry = &pAd->BATable.BARecEntry[Idx];
- } else {
- /* impossible ! */
- ASSERT(0);
- /* release packet */
- RELEASE_NDIS_PACKET(pAd, pRxBlk->pRxPacket,
- NDIS_STATUS_FAILURE);
- return;
- }
-
- ASSERT(pBAEntry);
-
- /* update last rx time */
- NdisGetSystemUpTime(&Now32);
-
- pBAEntry->rcvSeq = Sequence;
-
- ba_flush_reordering_timeout_mpdus(pAd, pBAEntry, Now32);
- pBAEntry->LastIndSeqAtTimer = Now32;
-
- /* */
- /* Reset Last Indicate Sequence */
- /* */
- if (pBAEntry->LastIndSeq == RESET_RCV_SEQ) {
- ASSERT((pBAEntry->list.qlen == 0)
- && (pBAEntry->list.next == NULL));
-
- /* reset rcv sequence of BA session */
- pBAEntry->LastIndSeq = Sequence;
- pBAEntry->LastIndSeqAtTimer = Now32;
- INDICATE_LEGACY_OR_AMSDU(pAd, pRxBlk, FromWhichBSSID);
- return;
- }
-
- /* */
- /* I. Check if in order. */
- /* */
- if (SEQ_STEPONE(Sequence, pBAEntry->LastIndSeq, MAXSEQ)) {
- u16 LastIndSeq;
-
- pBAEntry->LastIndSeq = Sequence;
- INDICATE_LEGACY_OR_AMSDU(pAd, pRxBlk, FromWhichBSSID);
- LastIndSeq =
- ba_indicate_reordering_mpdus_in_order(pAd, pBAEntry,
- pBAEntry->LastIndSeq);
- if (LastIndSeq != RESET_RCV_SEQ) {
- pBAEntry->LastIndSeq = LastIndSeq;
- }
- pBAEntry->LastIndSeqAtTimer = Now32;
- }
- /* */
- /* II. Drop Duplicated Packet */
- /* */
- else if (Sequence == pBAEntry->LastIndSeq) {
-
- /* drop and release packet */
- pBAEntry->nDropPacket++;
- RELEASE_NDIS_PACKET(pAd, pRxBlk->pRxPacket,
- NDIS_STATUS_FAILURE);
- }
- /* */
- /* III. Drop Old Received Packet */
- /* */
- else if (SEQ_SMALLER(Sequence, pBAEntry->LastIndSeq, MAXSEQ)) {
-
- /* drop and release packet */
- pBAEntry->nDropPacket++;
- RELEASE_NDIS_PACKET(pAd, pRxBlk->pRxPacket,
- NDIS_STATUS_FAILURE);
- }
- /* */
- /* IV. Receive Sequence within Window Size */
- /* */
- else if (SEQ_SMALLER
- (Sequence,
- (((pBAEntry->LastIndSeq + pBAEntry->BAWinSize + 1)) & MAXSEQ),
- MAXSEQ)) {
- ba_enqueue_reordering_packet(pAd, pBAEntry, pRxBlk,
- FromWhichBSSID);
- }
- /* */
- /* V. Receive seq surpasses Win(lastseq + nMSDU). So refresh all reorder buffer */
- /* */
- else {
- long WinStartSeq, TmpSeq;
-
- TmpSeq = Sequence - (pBAEntry->BAWinSize) - 1;
- if (TmpSeq < 0) {
- TmpSeq = (MAXSEQ + 1) + TmpSeq;
- }
- WinStartSeq = (TmpSeq + 1) & MAXSEQ;
- ba_indicate_reordering_mpdus_le_seq(pAd, pBAEntry, WinStartSeq);
- pBAEntry->LastIndSeq = WinStartSeq; /*TmpSeq; */
-
- pBAEntry->LastIndSeqAtTimer = Now32;
-
- ba_enqueue_reordering_packet(pAd, pBAEntry, pRxBlk,
- FromWhichBSSID);
-
- TmpSeq =
- ba_indicate_reordering_mpdus_in_order(pAd, pBAEntry,
- pBAEntry->LastIndSeq);
- if (TmpSeq != RESET_RCV_SEQ) {
- pBAEntry->LastIndSeq = TmpSeq;
- }
- }
-}
diff --git a/drivers/staging/rt2860/common/cmm_aes.c b/drivers/staging/rt2860/common/cmm_aes.c
deleted file mode 100644
index d70d229..0000000
--- a/drivers/staging/rt2860/common/cmm_aes.c
+++ /dev/null
@@ -1,1311 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- cmm_aes.c
-
- Abstract:
-
- Revision History:
- Who When What
- -------- ---------- ----------------------------------------------
- Paul Wu 02-25-02 Initial
-*/
-
-#include "../rt_config.h"
-
-struct aes_context {
- u32 erk[64]; /* encryption round keys */
- u32 drk[64]; /* decryption round keys */
- int nr; /* number of rounds */
-};
-
-/*****************************/
-/******** SBOX Table *********/
-/*****************************/
-
-u8 SboxTable[256] = {
- 0x63, 0x7c, 0x77, 0x7b, 0xf2, 0x6b, 0x6f, 0xc5,
- 0x30, 0x01, 0x67, 0x2b, 0xfe, 0xd7, 0xab, 0x76,
- 0xca, 0x82, 0xc9, 0x7d, 0xfa, 0x59, 0x47, 0xf0,
- 0xad, 0xd4, 0xa2, 0xaf, 0x9c, 0xa4, 0x72, 0xc0,
- 0xb7, 0xfd, 0x93, 0x26, 0x36, 0x3f, 0xf7, 0xcc,
- 0x34, 0xa5, 0xe5, 0xf1, 0x71, 0xd8, 0x31, 0x15,
- 0x04, 0xc7, 0x23, 0xc3, 0x18, 0x96, 0x05, 0x9a,
- 0x07, 0x12, 0x80, 0xe2, 0xeb, 0x27, 0xb2, 0x75,
- 0x09, 0x83, 0x2c, 0x1a, 0x1b, 0x6e, 0x5a, 0xa0,
- 0x52, 0x3b, 0xd6, 0xb3, 0x29, 0xe3, 0x2f, 0x84,
- 0x53, 0xd1, 0x00, 0xed, 0x20, 0xfc, 0xb1, 0x5b,
- 0x6a, 0xcb, 0xbe, 0x39, 0x4a, 0x4c, 0x58, 0xcf,
- 0xd0, 0xef, 0xaa, 0xfb, 0x43, 0x4d, 0x33, 0x85,
- 0x45, 0xf9, 0x02, 0x7f, 0x50, 0x3c, 0x9f, 0xa8,
- 0x51, 0xa3, 0x40, 0x8f, 0x92, 0x9d, 0x38, 0xf5,
- 0xbc, 0xb6, 0xda, 0x21, 0x10, 0xff, 0xf3, 0xd2,
- 0xcd, 0x0c, 0x13, 0xec, 0x5f, 0x97, 0x44, 0x17,
- 0xc4, 0xa7, 0x7e, 0x3d, 0x64, 0x5d, 0x19, 0x73,
- 0x60, 0x81, 0x4f, 0xdc, 0x22, 0x2a, 0x90, 0x88,
- 0x46, 0xee, 0xb8, 0x14, 0xde, 0x5e, 0x0b, 0xdb,
- 0xe0, 0x32, 0x3a, 0x0a, 0x49, 0x06, 0x24, 0x5c,
- 0xc2, 0xd3, 0xac, 0x62, 0x91, 0x95, 0xe4, 0x79,
- 0xe7, 0xc8, 0x37, 0x6d, 0x8d, 0xd5, 0x4e, 0xa9,
- 0x6c, 0x56, 0xf4, 0xea, 0x65, 0x7a, 0xae, 0x08,
- 0xba, 0x78, 0x25, 0x2e, 0x1c, 0xa6, 0xb4, 0xc6,
- 0xe8, 0xdd, 0x74, 0x1f, 0x4b, 0xbd, 0x8b, 0x8a,
- 0x70, 0x3e, 0xb5, 0x66, 0x48, 0x03, 0xf6, 0x0e,
- 0x61, 0x35, 0x57, 0xb9, 0x86, 0xc1, 0x1d, 0x9e,
- 0xe1, 0xf8, 0x98, 0x11, 0x69, 0xd9, 0x8e, 0x94,
- 0x9b, 0x1e, 0x87, 0xe9, 0xce, 0x55, 0x28, 0xdf,
- 0x8c, 0xa1, 0x89, 0x0d, 0xbf, 0xe6, 0x42, 0x68,
- 0x41, 0x99, 0x2d, 0x0f, 0xb0, 0x54, 0xbb, 0x16
-};
-
-void xor_32(u8 *a, u8 *b, u8 *out)
-{
- int i;
-
- for (i = 0; i < 4; i++) {
- out[i] = a[i] ^ b[i];
- }
-}
-
-void xor_128(u8 *a, u8 *b, u8 *out)
-{
- int i;
-
- for (i = 0; i < 16; i++) {
- out[i] = a[i] ^ b[i];
- }
-}
-
-u8 RTMPCkipSbox(u8 a)
-{
- return SboxTable[(int)a];
-}
-
-void next_key(u8 *key, int round)
-{
- u8 rcon;
- u8 sbox_key[4];
- u8 rcon_table[12] = {
- 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80,
- 0x1b, 0x36, 0x36, 0x36
- };
-
- sbox_key[0] = RTMPCkipSbox(key[13]);
- sbox_key[1] = RTMPCkipSbox(key[14]);
- sbox_key[2] = RTMPCkipSbox(key[15]);
- sbox_key[3] = RTMPCkipSbox(key[12]);
-
- rcon = rcon_table[round];
-
- xor_32(&key[0], sbox_key, &key[0]);
- key[0] = key[0] ^ rcon;
-
- xor_32(&key[4], &key[0], &key[4]);
- xor_32(&key[8], &key[4], &key[8]);
- xor_32(&key[12], &key[8], &key[12]);
-}
-
-void byte_sub(u8 *in, u8 *out)
-{
- int i;
-
- for (i = 0; i < 16; i++) {
- out[i] = RTMPCkipSbox(in[i]);
- }
-}
-
-/************************************/
-/* bitwise_xor() */
-/* A 128 bit, bitwise exclusive or */
-/************************************/
-
-void bitwise_xor(unsigned char *ina, unsigned char *inb, unsigned char *out)
-{
- int i;
- for (i = 0; i < 16; i++) {
- out[i] = ina[i] ^ inb[i];
- }
-}
-
-void shift_row(u8 *in, u8 *out)
-{
- out[0] = in[0];
- out[1] = in[5];
- out[2] = in[10];
- out[3] = in[15];
- out[4] = in[4];
- out[5] = in[9];
- out[6] = in[14];
- out[7] = in[3];
- out[8] = in[8];
- out[9] = in[13];
- out[10] = in[2];
- out[11] = in[7];
- out[12] = in[12];
- out[13] = in[1];
- out[14] = in[6];
- out[15] = in[11];
-}
-
-void mix_column(u8 *in, u8 *out)
-{
- int i;
- u8 add1b[4];
- u8 add1bf7[4];
- u8 rotl[4];
- u8 swap_halfs[4];
- u8 andf7[4];
- u8 rotr[4];
- u8 temp[4];
- u8 tempb[4];
-
- for (i = 0; i < 4; i++) {
- if ((in[i] & 0x80) == 0x80)
- add1b[i] = 0x1b;
- else
- add1b[i] = 0x00;
- }
-
- swap_halfs[0] = in[2]; /* Swap halfs */
- swap_halfs[1] = in[3];
- swap_halfs[2] = in[0];
- swap_halfs[3] = in[1];
-
- rotl[0] = in[3]; /* Rotate left 8 bits */
- rotl[1] = in[0];
- rotl[2] = in[1];
- rotl[3] = in[2];
-
- andf7[0] = in[0] & 0x7f;
- andf7[1] = in[1] & 0x7f;
- andf7[2] = in[2] & 0x7f;
- andf7[3] = in[3] & 0x7f;
-
- for (i = 3; i > 0; i--) { /* logical shift left 1 bit */
- andf7[i] = andf7[i] << 1;
- if ((andf7[i - 1] & 0x80) == 0x80) {
- andf7[i] = (andf7[i] | 0x01);
- }
- }
- andf7[0] = andf7[0] << 1;
- andf7[0] = andf7[0] & 0xfe;
-
- xor_32(add1b, andf7, add1bf7);
-
- xor_32(in, add1bf7, rotr);
-
- temp[0] = rotr[0]; /* Rotate right 8 bits */
- rotr[0] = rotr[1];
- rotr[1] = rotr[2];
- rotr[2] = rotr[3];
- rotr[3] = temp[0];
-
- xor_32(add1bf7, rotr, temp);
- xor_32(swap_halfs, rotl, tempb);
- xor_32(temp, tempb, out);
-}
-
-/************************************************/
-/* construct_mic_header1() */
-/* Builds the first MIC header block from */
-/* header fields. */
-/************************************************/
-
-void construct_mic_header1(unsigned char *mic_header1,
- int header_length, unsigned char *mpdu)
-{
- mic_header1[0] = (unsigned char)((header_length - 2) / 256);
- mic_header1[1] = (unsigned char)((header_length - 2) % 256);
- mic_header1[2] = mpdu[0] & 0xcf; /* Mute CF poll & CF ack bits */
- mic_header1[3] = mpdu[1] & 0xc7; /* Mute retry, more data and pwr mgt bits */
- mic_header1[4] = mpdu[4]; /* A1 */
- mic_header1[5] = mpdu[5];
- mic_header1[6] = mpdu[6];
- mic_header1[7] = mpdu[7];
- mic_header1[8] = mpdu[8];
- mic_header1[9] = mpdu[9];
- mic_header1[10] = mpdu[10]; /* A2 */
- mic_header1[11] = mpdu[11];
- mic_header1[12] = mpdu[12];
- mic_header1[13] = mpdu[13];
- mic_header1[14] = mpdu[14];
- mic_header1[15] = mpdu[15];
-}
-
-/************************************************/
-/* construct_mic_header2() */
-/* Builds the last MIC header block from */
-/* header fields. */
-/************************************************/
-
-void construct_mic_header2(unsigned char *mic_header2,
- unsigned char *mpdu, int a4_exists, int qc_exists)
-{
- int i;
-
- for (i = 0; i < 16; i++)
- mic_header2[i] = 0x00;
-
- mic_header2[0] = mpdu[16]; /* A3 */
- mic_header2[1] = mpdu[17];
- mic_header2[2] = mpdu[18];
- mic_header2[3] = mpdu[19];
- mic_header2[4] = mpdu[20];
- mic_header2[5] = mpdu[21];
-
- /* In Sequence Control field, mute sequence numer bits (12-bit) */
- mic_header2[6] = mpdu[22] & 0x0f; /* SC */
- mic_header2[7] = 0x00; /* mpdu[23]; */
-
- if ((!qc_exists) && a4_exists) {
- for (i = 0; i < 6; i++)
- mic_header2[8 + i] = mpdu[24 + i]; /* A4 */
-
- }
-
- if (qc_exists && (!a4_exists)) {
- mic_header2[8] = mpdu[24] & 0x0f; /* mute bits 15 - 4 */
- mic_header2[9] = mpdu[25] & 0x00;
- }
-
- if (qc_exists && a4_exists) {
- for (i = 0; i < 6; i++)
- mic_header2[8 + i] = mpdu[24 + i]; /* A4 */
-
- mic_header2[14] = mpdu[30] & 0x0f;
- mic_header2[15] = mpdu[31] & 0x00;
- }
-}
-
-/************************************************/
-/* construct_mic_iv() */
-/* Builds the MIC IV from header fields and PN */
-/************************************************/
-
-void construct_mic_iv(unsigned char *mic_iv,
- int qc_exists,
- int a4_exists,
- unsigned char *mpdu,
- unsigned int payload_length, unsigned char *pn_vector)
-{
- int i;
-
- mic_iv[0] = 0x59;
- if (qc_exists && a4_exists)
- mic_iv[1] = mpdu[30] & 0x0f; /* QoS_TC */
- if (qc_exists && !a4_exists)
- mic_iv[1] = mpdu[24] & 0x0f; /* mute bits 7-4 */
- if (!qc_exists)
- mic_iv[1] = 0x00;
- for (i = 2; i < 8; i++)
- mic_iv[i] = mpdu[i + 8]; /* mic_iv[2:7] = A2[0:5] = mpdu[10:15] */
-#ifdef CONSISTENT_PN_ORDER
- for (i = 8; i < 14; i++)
- mic_iv[i] = pn_vector[i - 8]; /* mic_iv[8:13] = PN[0:5] */
-#else
- for (i = 8; i < 14; i++)
- mic_iv[i] = pn_vector[13 - i]; /* mic_iv[8:13] = PN[5:0] */
-#endif
- mic_iv[14] = (unsigned char)(payload_length / 256);
- mic_iv[15] = (unsigned char)(payload_length % 256);
-
-}
-
-/****************************************/
-/* aes128k128d() */
-/* Performs a 128 bit AES encrypt with */
-/* 128 bit data. */
-/****************************************/
-void aes128k128d(unsigned char *key, unsigned char *data,
- unsigned char *ciphertext)
-{
- int round;
- int i;
- unsigned char intermediatea[16];
- unsigned char intermediateb[16];
- unsigned char round_key[16];
-
- for (i = 0; i < 16; i++)
- round_key[i] = key[i];
-
- for (round = 0; round < 11; round++) {
- if (round == 0) {
- xor_128(round_key, data, ciphertext);
- next_key(round_key, round);
- } else if (round == 10) {
- byte_sub(ciphertext, intermediatea);
- shift_row(intermediatea, intermediateb);
- xor_128(intermediateb, round_key, ciphertext);
- } else { /* 1 - 9 */
-
- byte_sub(ciphertext, intermediatea);
- shift_row(intermediatea, intermediateb);
- mix_column(&intermediateb[0], &intermediatea[0]);
- mix_column(&intermediateb[4], &intermediatea[4]);
- mix_column(&intermediateb[8], &intermediatea[8]);
- mix_column(&intermediateb[12], &intermediatea[12]);
- xor_128(intermediatea, round_key, ciphertext);
- next_key(round_key, round);
- }
- }
-
-}
-
-void construct_ctr_preload(unsigned char *ctr_preload,
- int a4_exists,
- int qc_exists,
- unsigned char *mpdu, unsigned char *pn_vector, int c)
-{
-
- int i = 0;
- for (i = 0; i < 16; i++)
- ctr_preload[i] = 0x00;
- i = 0;
-
- ctr_preload[0] = 0x01; /* flag */
- if (qc_exists && a4_exists)
- ctr_preload[1] = mpdu[30] & 0x0f; /* QoC_Control */
- if (qc_exists && !a4_exists)
- ctr_preload[1] = mpdu[24] & 0x0f;
-
- for (i = 2; i < 8; i++)
- ctr_preload[i] = mpdu[i + 8]; /* ctr_preload[2:7] = A2[0:5] = mpdu[10:15] */
-#ifdef CONSISTENT_PN_ORDER
- for (i = 8; i < 14; i++)
- ctr_preload[i] = pn_vector[i - 8]; /* ctr_preload[8:13] = PN[0:5] */
-#else
- for (i = 8; i < 14; i++)
- ctr_preload[i] = pn_vector[13 - i]; /* ctr_preload[8:13] = PN[5:0] */
-#endif
- ctr_preload[14] = (unsigned char)(c / 256); /* Ctr */
- ctr_preload[15] = (unsigned char)(c % 256);
-
-}
-
-BOOLEAN RTMPSoftDecryptAES(struct rt_rtmp_adapter *pAd,
- u8 *pData,
- unsigned long DataByteCnt, struct rt_cipher_key *pWpaKey)
-{
- u8 KeyID;
- u32 HeaderLen;
- u8 PN[6];
- u32 payload_len;
- u32 num_blocks;
- u32 payload_remainder;
- u16 fc;
- u8 fc0;
- u8 fc1;
- u32 frame_type;
- u32 frame_subtype;
- u32 from_ds;
- u32 to_ds;
- int a4_exists;
- int qc_exists;
- u8 aes_out[16];
- int payload_index;
- u32 i;
- u8 ctr_preload[16];
- u8 chain_buffer[16];
- u8 padded_buffer[16];
- u8 mic_iv[16];
- u8 mic_header1[16];
- u8 mic_header2[16];
- u8 MIC[8];
- u8 TrailMIC[8];
-
- fc0 = *pData;
- fc1 = *(pData + 1);
-
- fc = *((u16 *)pData);
-
- frame_type = ((fc0 >> 2) & 0x03);
- frame_subtype = ((fc0 >> 4) & 0x0f);
-
- from_ds = (fc1 & 0x2) >> 1;
- to_ds = (fc1 & 0x1);
-
- a4_exists = (from_ds & to_ds);
- qc_exists = ((frame_subtype == 0x08) || /* Assumed QoS subtypes */
- (frame_subtype == 0x09) || /* Likely to change. */
- (frame_subtype == 0x0a) || (frame_subtype == 0x0b)
- );
-
- HeaderLen = 24;
- if (a4_exists)
- HeaderLen += 6;
-
- KeyID = *((u8 *)(pData + HeaderLen + 3));
- KeyID = KeyID >> 6;
-
- if (pWpaKey[KeyID].KeyLen == 0) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("RTMPSoftDecryptAES failed!(KeyID[%d] Length can not be 0)\n",
- KeyID));
- return FALSE;
- }
-
- PN[0] = *(pData + HeaderLen);
- PN[1] = *(pData + HeaderLen + 1);
- PN[2] = *(pData + HeaderLen + 4);
- PN[3] = *(pData + HeaderLen + 5);
- PN[4] = *(pData + HeaderLen + 6);
- PN[5] = *(pData + HeaderLen + 7);
-
- payload_len = DataByteCnt - HeaderLen - 8 - 8; /* 8 bytes for CCMP header , 8 bytes for MIC */
- payload_remainder = (payload_len) % 16;
- num_blocks = (payload_len) / 16;
-
- /* Find start of payload */
- payload_index = HeaderLen + 8; /*IV+EIV */
-
- for (i = 0; i < num_blocks; i++) {
- construct_ctr_preload(ctr_preload,
- a4_exists, qc_exists, pData, PN, i + 1);
-
- aes128k128d(pWpaKey[KeyID].Key, ctr_preload, aes_out);
-
- bitwise_xor(aes_out, pData + payload_index, chain_buffer);
- NdisMoveMemory(pData + payload_index - 8, chain_buffer, 16);
- payload_index += 16;
- }
-
- /* */
- /* If there is a short final block, then pad it */
- /* encrypt it and copy the unpadded part back */
- /* */
- if (payload_remainder > 0) {
- construct_ctr_preload(ctr_preload,
- a4_exists,
- qc_exists, pData, PN, num_blocks + 1);
-
- NdisZeroMemory(padded_buffer, 16);
- NdisMoveMemory(padded_buffer, pData + payload_index,
- payload_remainder);
-
- aes128k128d(pWpaKey[KeyID].Key, ctr_preload, aes_out);
-
- bitwise_xor(aes_out, padded_buffer, chain_buffer);
- NdisMoveMemory(pData + payload_index - 8, chain_buffer,
- payload_remainder);
- payload_index += payload_remainder;
- }
- /* */
- /* Descrypt the MIC */
- /* */
- construct_ctr_preload(ctr_preload, a4_exists, qc_exists, pData, PN, 0);
- NdisZeroMemory(padded_buffer, 16);
- NdisMoveMemory(padded_buffer, pData + payload_index, 8);
-
- aes128k128d(pWpaKey[KeyID].Key, ctr_preload, aes_out);
-
- bitwise_xor(aes_out, padded_buffer, chain_buffer);
-
- NdisMoveMemory(TrailMIC, chain_buffer, 8);
-
- /* */
- /* Calculate MIC */
- /* */
-
- /*Force the protected frame bit on */
- *(pData + 1) = *(pData + 1) | 0x40;
-
- /* Find start of payload */
- /* Because the CCMP header has been removed */
- payload_index = HeaderLen;
-
- construct_mic_iv(mic_iv, qc_exists, a4_exists, pData, payload_len, PN);
-
- construct_mic_header1(mic_header1, HeaderLen, pData);
-
- construct_mic_header2(mic_header2, pData, a4_exists, qc_exists);
-
- aes128k128d(pWpaKey[KeyID].Key, mic_iv, aes_out);
- bitwise_xor(aes_out, mic_header1, chain_buffer);
- aes128k128d(pWpaKey[KeyID].Key, chain_buffer, aes_out);
- bitwise_xor(aes_out, mic_header2, chain_buffer);
- aes128k128d(pWpaKey[KeyID].Key, chain_buffer, aes_out);
-
- /* iterate through each 16 byte payload block */
- for (i = 0; i < num_blocks; i++) {
- bitwise_xor(aes_out, pData + payload_index, chain_buffer);
- payload_index += 16;
- aes128k128d(pWpaKey[KeyID].Key, chain_buffer, aes_out);
- }
-
- /* Add on the final payload block if it needs padding */
- if (payload_remainder > 0) {
- NdisZeroMemory(padded_buffer, 16);
- NdisMoveMemory(padded_buffer, pData + payload_index,
- payload_remainder);
-
- bitwise_xor(aes_out, padded_buffer, chain_buffer);
- aes128k128d(pWpaKey[KeyID].Key, chain_buffer, aes_out);
- }
- /* aes_out contains padded mic, discard most significant */
- /* 8 bytes to generate 64 bit MIC */
- for (i = 0; i < 8; i++)
- MIC[i] = aes_out[i];
-
- if (!NdisEqualMemory(MIC, TrailMIC, 8)) {
- DBGPRINT(RT_DEBUG_ERROR, ("RTMPSoftDecryptAES, MIC Error !\n")); /*MIC error. */
- return FALSE;
- }
-
- return TRUE;
-}
-
-/* ========================= AES En/Decryption ========================== */
-#ifndef uint8
-#define uint8 unsigned char
-#endif
-
-#ifndef uint32
-#define uint32 unsigned int
-#endif
-
-/* forward S-box */
-static uint32 FSb[256] = {
- 0x63, 0x7C, 0x77, 0x7B, 0xF2, 0x6B, 0x6F, 0xC5,
- 0x30, 0x01, 0x67, 0x2B, 0xFE, 0xD7, 0xAB, 0x76,
- 0xCA, 0x82, 0xC9, 0x7D, 0xFA, 0x59, 0x47, 0xF0,
- 0xAD, 0xD4, 0xA2, 0xAF, 0x9C, 0xA4, 0x72, 0xC0,
- 0xB7, 0xFD, 0x93, 0x26, 0x36, 0x3F, 0xF7, 0xCC,
- 0x34, 0xA5, 0xE5, 0xF1, 0x71, 0xD8, 0x31, 0x15,
- 0x04, 0xC7, 0x23, 0xC3, 0x18, 0x96, 0x05, 0x9A,
- 0x07, 0x12, 0x80, 0xE2, 0xEB, 0x27, 0xB2, 0x75,
- 0x09, 0x83, 0x2C, 0x1A, 0x1B, 0x6E, 0x5A, 0xA0,
- 0x52, 0x3B, 0xD6, 0xB3, 0x29, 0xE3, 0x2F, 0x84,
- 0x53, 0xD1, 0x00, 0xED, 0x20, 0xFC, 0xB1, 0x5B,
- 0x6A, 0xCB, 0xBE, 0x39, 0x4A, 0x4C, 0x58, 0xCF,
- 0xD0, 0xEF, 0xAA, 0xFB, 0x43, 0x4D, 0x33, 0x85,
- 0x45, 0xF9, 0x02, 0x7F, 0x50, 0x3C, 0x9F, 0xA8,
- 0x51, 0xA3, 0x40, 0x8F, 0x92, 0x9D, 0x38, 0xF5,
- 0xBC, 0xB6, 0xDA, 0x21, 0x10, 0xFF, 0xF3, 0xD2,
- 0xCD, 0x0C, 0x13, 0xEC, 0x5F, 0x97, 0x44, 0x17,
- 0xC4, 0xA7, 0x7E, 0x3D, 0x64, 0x5D, 0x19, 0x73,
- 0x60, 0x81, 0x4F, 0xDC, 0x22, 0x2A, 0x90, 0x88,
- 0x46, 0xEE, 0xB8, 0x14, 0xDE, 0x5E, 0x0B, 0xDB,
- 0xE0, 0x32, 0x3A, 0x0A, 0x49, 0x06, 0x24, 0x5C,
- 0xC2, 0xD3, 0xAC, 0x62, 0x91, 0x95, 0xE4, 0x79,
- 0xE7, 0xC8, 0x37, 0x6D, 0x8D, 0xD5, 0x4E, 0xA9,
- 0x6C, 0x56, 0xF4, 0xEA, 0x65, 0x7A, 0xAE, 0x08,
- 0xBA, 0x78, 0x25, 0x2E, 0x1C, 0xA6, 0xB4, 0xC6,
- 0xE8, 0xDD, 0x74, 0x1F, 0x4B, 0xBD, 0x8B, 0x8A,
- 0x70, 0x3E, 0xB5, 0x66, 0x48, 0x03, 0xF6, 0x0E,
- 0x61, 0x35, 0x57, 0xB9, 0x86, 0xC1, 0x1D, 0x9E,
- 0xE1, 0xF8, 0x98, 0x11, 0x69, 0xD9, 0x8E, 0x94,
- 0x9B, 0x1E, 0x87, 0xE9, 0xCE, 0x55, 0x28, 0xDF,
- 0x8C, 0xA1, 0x89, 0x0D, 0xBF, 0xE6, 0x42, 0x68,
- 0x41, 0x99, 0x2D, 0x0F, 0xB0, 0x54, 0xBB, 0x16
-};
-
-/* forward table */
-#define FT \
-\
- V(C6,63,63,A5), V(F8,7C,7C,84), V(EE,77,77,99), V(F6,7B,7B,8D), \
- V(FF,F2,F2,0D), V(D6,6B,6B,BD), V(DE,6F,6F,B1), V(91,C5,C5,54), \
- V(60,30,30,50), V(02,01,01,03), V(CE,67,67,A9), V(56,2B,2B,7D), \
- V(E7,FE,FE,19), V(B5,D7,D7,62), V(4D,AB,AB,E6), V(EC,76,76,9A), \
- V(8F,CA,CA,45), V(1F,82,82,9D), V(89,C9,C9,40), V(FA,7D,7D,87), \
- V(EF,FA,FA,15), V(B2,59,59,EB), V(8E,47,47,C9), V(FB,F0,F0,0B), \
- V(41,AD,AD,EC), V(B3,D4,D4,67), V(5F,A2,A2,FD), V(45,AF,AF,EA), \
- V(23,9C,9C,BF), V(53,A4,A4,F7), V(E4,72,72,96), V(9B,C0,C0,5B), \
- V(75,B7,B7,C2), V(E1,FD,FD,1C), V(3D,93,93,AE), V(4C,26,26,6A), \
- V(6C,36,36,5A), V(7E,3F,3F,41), V(F5,F7,F7,02), V(83,CC,CC,4F), \
- V(68,34,34,5C), V(51,A5,A5,F4), V(D1,E5,E5,34), V(F9,F1,F1,08), \
- V(E2,71,71,93), V(AB,D8,D8,73), V(62,31,31,53), V(2A,15,15,3F), \
- V(08,04,04,0C), V(95,C7,C7,52), V(46,23,23,65), V(9D,C3,C3,5E), \
- V(30,18,18,28), V(37,96,96,A1), V(0A,05,05,0F), V(2F,9A,9A,B5), \
- V(0E,07,07,09), V(24,12,12,36), V(1B,80,80,9B), V(DF,E2,E2,3D), \
- V(CD,EB,EB,26), V(4E,27,27,69), V(7F,B2,B2,CD), V(EA,75,75,9F), \
- V(12,09,09,1B), V(1D,83,83,9E), V(58,2C,2C,74), V(34,1A,1A,2E), \
- V(36,1B,1B,2D), V(DC,6E,6E,B2), V(B4,5A,5A,EE), V(5B,A0,A0,FB), \
- V(A4,52,52,F6), V(76,3B,3B,4D), V(B7,D6,D6,61), V(7D,B3,B3,CE), \
- V(52,29,29,7B), V(DD,E3,E3,3E), V(5E,2F,2F,71), V(13,84,84,97), \
- V(A6,53,53,F5), V(B9,D1,D1,68), V(00,00,00,00), V(C1,ED,ED,2C), \
- V(40,20,20,60), V(E3,FC,FC,1F), V(79,B1,B1,C8), V(B6,5B,5B,ED), \
- V(D4,6A,6A,BE), V(8D,CB,CB,46), V(67,BE,BE,D9), V(72,39,39,4B), \
- V(94,4A,4A,DE), V(98,4C,4C,D4), V(B0,58,58,E8), V(85,CF,CF,4A), \
- V(BB,D0,D0,6B), V(C5,EF,EF,2A), V(4F,AA,AA,E5), V(ED,FB,FB,16), \
- V(86,43,43,C5), V(9A,4D,4D,D7), V(66,33,33,55), V(11,85,85,94), \
- V(8A,45,45,CF), V(E9,F9,F9,10), V(04,02,02,06), V(FE,7F,7F,81), \
- V(A0,50,50,F0), V(78,3C,3C,44), V(25,9F,9F,BA), V(4B,A8,A8,E3), \
- V(A2,51,51,F3), V(5D,A3,A3,FE), V(80,40,40,C0), V(05,8F,8F,8A), \
- V(3F,92,92,AD), V(21,9D,9D,BC), V(70,38,38,48), V(F1,F5,F5,04), \
- V(63,BC,BC,DF), V(77,B6,B6,C1), V(AF,DA,DA,75), V(42,21,21,63), \
- V(20,10,10,30), V(E5,FF,FF,1A), V(FD,F3,F3,0E), V(BF,D2,D2,6D), \
- V(81,CD,CD,4C), V(18,0C,0C,14), V(26,13,13,35), V(C3,EC,EC,2F), \
- V(BE,5F,5F,E1), V(35,97,97,A2), V(88,44,44,CC), V(2E,17,17,39), \
- V(93,C4,C4,57), V(55,A7,A7,F2), V(FC,7E,7E,82), V(7A,3D,3D,47), \
- V(C8,64,64,AC), V(BA,5D,5D,E7), V(32,19,19,2B), V(E6,73,73,95), \
- V(C0,60,60,A0), V(19,81,81,98), V(9E,4F,4F,D1), V(A3,DC,DC,7F), \
- V(44,22,22,66), V(54,2A,2A,7E), V(3B,90,90,AB), V(0B,88,88,83), \
- V(8C,46,46,CA), V(C7,EE,EE,29), V(6B,B8,B8,D3), V(28,14,14,3C), \
- V(A7,DE,DE,79), V(BC,5E,5E,E2), V(16,0B,0B,1D), V(AD,DB,DB,76), \
- V(DB,E0,E0,3B), V(64,32,32,56), V(74,3A,3A,4E), V(14,0A,0A,1E), \
- V(92,49,49,DB), V(0C,06,06,0A), V(48,24,24,6C), V(B8,5C,5C,E4), \
- V(9F,C2,C2,5D), V(BD,D3,D3,6E), V(43,AC,AC,EF), V(C4,62,62,A6), \
- V(39,91,91,A8), V(31,95,95,A4), V(D3,E4,E4,37), V(F2,79,79,8B), \
- V(D5,E7,E7,32), V(8B,C8,C8,43), V(6E,37,37,59), V(DA,6D,6D,B7), \
- V(01,8D,8D,8C), V(B1,D5,D5,64), V(9C,4E,4E,D2), V(49,A9,A9,E0), \
- V(D8,6C,6C,B4), V(AC,56,56,FA), V(F3,F4,F4,07), V(CF,EA,EA,25), \
- V(CA,65,65,AF), V(F4,7A,7A,8E), V(47,AE,AE,E9), V(10,08,08,18), \
- V(6F,BA,BA,D5), V(F0,78,78,88), V(4A,25,25,6F), V(5C,2E,2E,72), \
- V(38,1C,1C,24), V(57,A6,A6,F1), V(73,B4,B4,C7), V(97,C6,C6,51), \
- V(CB,E8,E8,23), V(A1,DD,DD,7C), V(E8,74,74,9C), V(3E,1F,1F,21), \
- V(96,4B,4B,DD), V(61,BD,BD,DC), V(0D,8B,8B,86), V(0F,8A,8A,85), \
- V(E0,70,70,90), V(7C,3E,3E,42), V(71,B5,B5,C4), V(CC,66,66,AA), \
- V(90,48,48,D8), V(06,03,03,05), V(F7,F6,F6,01), V(1C,0E,0E,12), \
- V(C2,61,61,A3), V(6A,35,35,5F), V(AE,57,57,F9), V(69,B9,B9,D0), \
- V(17,86,86,91), V(99,C1,C1,58), V(3A,1D,1D,27), V(27,9E,9E,B9), \
- V(D9,E1,E1,38), V(EB,F8,F8,13), V(2B,98,98,B3), V(22,11,11,33), \
- V(D2,69,69,BB), V(A9,D9,D9,70), V(07,8E,8E,89), V(33,94,94,A7), \
- V(2D,9B,9B,B6), V(3C,1E,1E,22), V(15,87,87,92), V(C9,E9,E9,20), \
- V(87,CE,CE,49), V(AA,55,55,FF), V(50,28,28,78), V(A5,DF,DF,7A), \
- V(03,8C,8C,8F), V(59,A1,A1,F8), V(09,89,89,80), V(1A,0D,0D,17), \
- V(65,BF,BF,DA), V(D7,E6,E6,31), V(84,42,42,C6), V(D0,68,68,B8), \
- V(82,41,41,C3), V(29,99,99,B0), V(5A,2D,2D,77), V(1E,0F,0F,11), \
- V(7B,B0,B0,CB), V(A8,54,54,FC), V(6D,BB,BB,D6), V(2C,16,16,3A)
-
-#define V(a,b,c,d) 0x##a##b##c##d
-static uint32 FT0[256] = { FT };
-
-#undef V
-
-#define V(a,b,c,d) 0x##d##a##b##c
-static uint32 FT1[256] = { FT };
-
-#undef V
-
-#define V(a,b,c,d) 0x##c##d##a##b
-static uint32 FT2[256] = { FT };
-
-#undef V
-
-#define V(a,b,c,d) 0x##b##c##d##a
-static uint32 FT3[256] = { FT };
-
-#undef V
-
-#undef FT
-
-/* reverse S-box */
-
-static uint32 RSb[256] = {
- 0x52, 0x09, 0x6A, 0xD5, 0x30, 0x36, 0xA5, 0x38,
- 0xBF, 0x40, 0xA3, 0x9E, 0x81, 0xF3, 0xD7, 0xFB,
- 0x7C, 0xE3, 0x39, 0x82, 0x9B, 0x2F, 0xFF, 0x87,
- 0x34, 0x8E, 0x43, 0x44, 0xC4, 0xDE, 0xE9, 0xCB,
- 0x54, 0x7B, 0x94, 0x32, 0xA6, 0xC2, 0x23, 0x3D,
- 0xEE, 0x4C, 0x95, 0x0B, 0x42, 0xFA, 0xC3, 0x4E,
- 0x08, 0x2E, 0xA1, 0x66, 0x28, 0xD9, 0x24, 0xB2,
- 0x76, 0x5B, 0xA2, 0x49, 0x6D, 0x8B, 0xD1, 0x25,
- 0x72, 0xF8, 0xF6, 0x64, 0x86, 0x68, 0x98, 0x16,
- 0xD4, 0xA4, 0x5C, 0xCC, 0x5D, 0x65, 0xB6, 0x92,
- 0x6C, 0x70, 0x48, 0x50, 0xFD, 0xED, 0xB9, 0xDA,
- 0x5E, 0x15, 0x46, 0x57, 0xA7, 0x8D, 0x9D, 0x84,
- 0x90, 0xD8, 0xAB, 0x00, 0x8C, 0xBC, 0xD3, 0x0A,
- 0xF7, 0xE4, 0x58, 0x05, 0xB8, 0xB3, 0x45, 0x06,
- 0xD0, 0x2C, 0x1E, 0x8F, 0xCA, 0x3F, 0x0F, 0x02,
- 0xC1, 0xAF, 0xBD, 0x03, 0x01, 0x13, 0x8A, 0x6B,
- 0x3A, 0x91, 0x11, 0x41, 0x4F, 0x67, 0xDC, 0xEA,
- 0x97, 0xF2, 0xCF, 0xCE, 0xF0, 0xB4, 0xE6, 0x73,
- 0x96, 0xAC, 0x74, 0x22, 0xE7, 0xAD, 0x35, 0x85,
- 0xE2, 0xF9, 0x37, 0xE8, 0x1C, 0x75, 0xDF, 0x6E,
- 0x47, 0xF1, 0x1A, 0x71, 0x1D, 0x29, 0xC5, 0x89,
- 0x6F, 0xB7, 0x62, 0x0E, 0xAA, 0x18, 0xBE, 0x1B,
- 0xFC, 0x56, 0x3E, 0x4B, 0xC6, 0xD2, 0x79, 0x20,
- 0x9A, 0xDB, 0xC0, 0xFE, 0x78, 0xCD, 0x5A, 0xF4,
- 0x1F, 0xDD, 0xA8, 0x33, 0x88, 0x07, 0xC7, 0x31,
- 0xB1, 0x12, 0x10, 0x59, 0x27, 0x80, 0xEC, 0x5F,
- 0x60, 0x51, 0x7F, 0xA9, 0x19, 0xB5, 0x4A, 0x0D,
- 0x2D, 0xE5, 0x7A, 0x9F, 0x93, 0xC9, 0x9C, 0xEF,
- 0xA0, 0xE0, 0x3B, 0x4D, 0xAE, 0x2A, 0xF5, 0xB0,
- 0xC8, 0xEB, 0xBB, 0x3C, 0x83, 0x53, 0x99, 0x61,
- 0x17, 0x2B, 0x04, 0x7E, 0xBA, 0x77, 0xD6, 0x26,
- 0xE1, 0x69, 0x14, 0x63, 0x55, 0x21, 0x0C, 0x7D
-};
-
-/* reverse table */
-
-#define RT \
-\
- V(51,F4,A7,50), V(7E,41,65,53), V(1A,17,A4,C3), V(3A,27,5E,96), \
- V(3B,AB,6B,CB), V(1F,9D,45,F1), V(AC,FA,58,AB), V(4B,E3,03,93), \
- V(20,30,FA,55), V(AD,76,6D,F6), V(88,CC,76,91), V(F5,02,4C,25), \
- V(4F,E5,D7,FC), V(C5,2A,CB,D7), V(26,35,44,80), V(B5,62,A3,8F), \
- V(DE,B1,5A,49), V(25,BA,1B,67), V(45,EA,0E,98), V(5D,FE,C0,E1), \
- V(C3,2F,75,02), V(81,4C,F0,12), V(8D,46,97,A3), V(6B,D3,F9,C6), \
- V(03,8F,5F,E7), V(15,92,9C,95), V(BF,6D,7A,EB), V(95,52,59,DA), \
- V(D4,BE,83,2D), V(58,74,21,D3), V(49,E0,69,29), V(8E,C9,C8,44), \
- V(75,C2,89,6A), V(F4,8E,79,78), V(99,58,3E,6B), V(27,B9,71,DD), \
- V(BE,E1,4F,B6), V(F0,88,AD,17), V(C9,20,AC,66), V(7D,CE,3A,B4), \
- V(63,DF,4A,18), V(E5,1A,31,82), V(97,51,33,60), V(62,53,7F,45), \
- V(B1,64,77,E0), V(BB,6B,AE,84), V(FE,81,A0,1C), V(F9,08,2B,94), \
- V(70,48,68,58), V(8F,45,FD,19), V(94,DE,6C,87), V(52,7B,F8,B7), \
- V(AB,73,D3,23), V(72,4B,02,E2), V(E3,1F,8F,57), V(66,55,AB,2A), \
- V(B2,EB,28,07), V(2F,B5,C2,03), V(86,C5,7B,9A), V(D3,37,08,A5), \
- V(30,28,87,F2), V(23,BF,A5,B2), V(02,03,6A,BA), V(ED,16,82,5C), \
- V(8A,CF,1C,2B), V(A7,79,B4,92), V(F3,07,F2,F0), V(4E,69,E2,A1), \
- V(65,DA,F4,CD), V(06,05,BE,D5), V(D1,34,62,1F), V(C4,A6,FE,8A), \
- V(34,2E,53,9D), V(A2,F3,55,A0), V(05,8A,E1,32), V(A4,F6,EB,75), \
- V(0B,83,EC,39), V(40,60,EF,AA), V(5E,71,9F,06), V(BD,6E,10,51), \
- V(3E,21,8A,F9), V(96,DD,06,3D), V(DD,3E,05,AE), V(4D,E6,BD,46), \
- V(91,54,8D,B5), V(71,C4,5D,05), V(04,06,D4,6F), V(60,50,15,FF), \
- V(19,98,FB,24), V(D6,BD,E9,97), V(89,40,43,CC), V(67,D9,9E,77), \
- V(B0,E8,42,BD), V(07,89,8B,88), V(E7,19,5B,38), V(79,C8,EE,DB), \
- V(A1,7C,0A,47), V(7C,42,0F,E9), V(F8,84,1E,C9), V(00,00,00,00), \
- V(09,80,86,83), V(32,2B,ED,48), V(1E,11,70,AC), V(6C,5A,72,4E), \
- V(FD,0E,FF,FB), V(0F,85,38,56), V(3D,AE,D5,1E), V(36,2D,39,27), \
- V(0A,0F,D9,64), V(68,5C,A6,21), V(9B,5B,54,D1), V(24,36,2E,3A), \
- V(0C,0A,67,B1), V(93,57,E7,0F), V(B4,EE,96,D2), V(1B,9B,91,9E), \
- V(80,C0,C5,4F), V(61,DC,20,A2), V(5A,77,4B,69), V(1C,12,1A,16), \
- V(E2,93,BA,0A), V(C0,A0,2A,E5), V(3C,22,E0,43), V(12,1B,17,1D), \
- V(0E,09,0D,0B), V(F2,8B,C7,AD), V(2D,B6,A8,B9), V(14,1E,A9,C8), \
- V(57,F1,19,85), V(AF,75,07,4C), V(EE,99,DD,BB), V(A3,7F,60,FD), \
- V(F7,01,26,9F), V(5C,72,F5,BC), V(44,66,3B,C5), V(5B,FB,7E,34), \
- V(8B,43,29,76), V(CB,23,C6,DC), V(B6,ED,FC,68), V(B8,E4,F1,63), \
- V(D7,31,DC,CA), V(42,63,85,10), V(13,97,22,40), V(84,C6,11,20), \
- V(85,4A,24,7D), V(D2,BB,3D,F8), V(AE,F9,32,11), V(C7,29,A1,6D), \
- V(1D,9E,2F,4B), V(DC,B2,30,F3), V(0D,86,52,EC), V(77,C1,E3,D0), \
- V(2B,B3,16,6C), V(A9,70,B9,99), V(11,94,48,FA), V(47,E9,64,22), \
- V(A8,FC,8C,C4), V(A0,F0,3F,1A), V(56,7D,2C,D8), V(22,33,90,EF), \
- V(87,49,4E,C7), V(D9,38,D1,C1), V(8C,CA,A2,FE), V(98,D4,0B,36), \
- V(A6,F5,81,CF), V(A5,7A,DE,28), V(DA,B7,8E,26), V(3F,AD,BF,A4), \
- V(2C,3A,9D,E4), V(50,78,92,0D), V(6A,5F,CC,9B), V(54,7E,46,62), \
- V(F6,8D,13,C2), V(90,D8,B8,E8), V(2E,39,F7,5E), V(82,C3,AF,F5), \
- V(9F,5D,80,BE), V(69,D0,93,7C), V(6F,D5,2D,A9), V(CF,25,12,B3), \
- V(C8,AC,99,3B), V(10,18,7D,A7), V(E8,9C,63,6E), V(DB,3B,BB,7B), \
- V(CD,26,78,09), V(6E,59,18,F4), V(EC,9A,B7,01), V(83,4F,9A,A8), \
- V(E6,95,6E,65), V(AA,FF,E6,7E), V(21,BC,CF,08), V(EF,15,E8,E6), \
- V(BA,E7,9B,D9), V(4A,6F,36,CE), V(EA,9F,09,D4), V(29,B0,7C,D6), \
- V(31,A4,B2,AF), V(2A,3F,23,31), V(C6,A5,94,30), V(35,A2,66,C0), \
- V(74,4E,BC,37), V(FC,82,CA,A6), V(E0,90,D0,B0), V(33,A7,D8,15), \
- V(F1,04,98,4A), V(41,EC,DA,F7), V(7F,CD,50,0E), V(17,91,F6,2F), \
- V(76,4D,D6,8D), V(43,EF,B0,4D), V(CC,AA,4D,54), V(E4,96,04,DF), \
- V(9E,D1,B5,E3), V(4C,6A,88,1B), V(C1,2C,1F,B8), V(46,65,51,7F), \
- V(9D,5E,EA,04), V(01,8C,35,5D), V(FA,87,74,73), V(FB,0B,41,2E), \
- V(B3,67,1D,5A), V(92,DB,D2,52), V(E9,10,56,33), V(6D,D6,47,13), \
- V(9A,D7,61,8C), V(37,A1,0C,7A), V(59,F8,14,8E), V(EB,13,3C,89), \
- V(CE,A9,27,EE), V(B7,61,C9,35), V(E1,1C,E5,ED), V(7A,47,B1,3C), \
- V(9C,D2,DF,59), V(55,F2,73,3F), V(18,14,CE,79), V(73,C7,37,BF), \
- V(53,F7,CD,EA), V(5F,FD,AA,5B), V(DF,3D,6F,14), V(78,44,DB,86), \
- V(CA,AF,F3,81), V(B9,68,C4,3E), V(38,24,34,2C), V(C2,A3,40,5F), \
- V(16,1D,C3,72), V(BC,E2,25,0C), V(28,3C,49,8B), V(FF,0D,95,41), \
- V(39,A8,01,71), V(08,0C,B3,DE), V(D8,B4,E4,9C), V(64,56,C1,90), \
- V(7B,CB,84,61), V(D5,32,B6,70), V(48,6C,5C,74), V(D0,B8,57,42)
-
-#define V(a,b,c,d) 0x##a##b##c##d
-static uint32 RT0[256] = { RT };
-
-#undef V
-
-#define V(a,b,c,d) 0x##d##a##b##c
-static uint32 RT1[256] = { RT };
-
-#undef V
-
-#define V(a,b,c,d) 0x##c##d##a##b
-static uint32 RT2[256] = { RT };
-
-#undef V
-
-#define V(a,b,c,d) 0x##b##c##d##a
-static uint32 RT3[256] = { RT };
-
-#undef V
-
-#undef RT
-
-/* round constants */
-
-static uint32 RCON[10] = {
- 0x01000000, 0x02000000, 0x04000000, 0x08000000,
- 0x10000000, 0x20000000, 0x40000000, 0x80000000,
- 0x1B000000, 0x36000000
-};
-
-/* key schedule tables */
-
-static int KT_init = 1;
-
-static uint32 KT0[256];
-static uint32 KT1[256];
-static uint32 KT2[256];
-static uint32 KT3[256];
-
-/* platform-independent 32-bit integer manipulation macros */
-
-#define GET_UINT32(n,b,i) \
-{ \
- (n) = ( (uint32) (b)[(i) ] << 24 ) \
- | ( (uint32) (b)[(i) + 1] << 16 ) \
- | ( (uint32) (b)[(i) + 2] << 8 ) \
- | ( (uint32) (b)[(i) + 3] ); \
-}
-
-#define PUT_UINT32(n,b,i) \
-{ \
- (b)[(i) ] = (uint8) ( (n) >> 24 ); \
- (b)[(i) + 1] = (uint8) ( (n) >> 16 ); \
- (b)[(i) + 2] = (uint8) ( (n) >> 8 ); \
- (b)[(i) + 3] = (uint8) ( (n) ); \
-}
-
-int rt_aes_set_key(struct aes_context * ctx, uint8 * key, int nbits)
-{
- int i;
- uint32 *RK, *SK;
-
- switch (nbits) {
- case 128:
- ctx->nr = 10;
- break;
- case 192:
- ctx->nr = 12;
- break;
- case 256:
- ctx->nr = 14;
- break;
- default:
- return (1);
- }
-
- RK = (uint32 *) ctx->erk;
-
- for (i = 0; i < (nbits >> 5); i++) {
- GET_UINT32(RK[i], key, i * 4);
- }
-
- /* setup encryption round keys */
-
- switch (nbits) {
- case 128:
-
- for (i = 0; i < 10; i++, RK += 4) {
- RK[4] = RK[0] ^ RCON[i] ^
- (FSb[(uint8) (RK[3] >> 16)] << 24) ^
- (FSb[(uint8) (RK[3] >> 8)] << 16) ^
- (FSb[(uint8) (RK[3])] << 8) ^
- (FSb[(uint8) (RK[3] >> 24)]);
-
- RK[5] = RK[1] ^ RK[4];
- RK[6] = RK[2] ^ RK[5];
- RK[7] = RK[3] ^ RK[6];
- }
- break;
-
- case 192:
-
- for (i = 0; i < 8; i++, RK += 6) {
- RK[6] = RK[0] ^ RCON[i] ^
- (FSb[(uint8) (RK[5] >> 16)] << 24) ^
- (FSb[(uint8) (RK[5] >> 8)] << 16) ^
- (FSb[(uint8) (RK[5])] << 8) ^
- (FSb[(uint8) (RK[5] >> 24)]);
-
- RK[7] = RK[1] ^ RK[6];
- RK[8] = RK[2] ^ RK[7];
- RK[9] = RK[3] ^ RK[8];
- RK[10] = RK[4] ^ RK[9];
- RK[11] = RK[5] ^ RK[10];
- }
- break;
-
- case 256:
-
- for (i = 0; i < 7; i++, RK += 8) {
- RK[8] = RK[0] ^ RCON[i] ^
- (FSb[(uint8) (RK[7] >> 16)] << 24) ^
- (FSb[(uint8) (RK[7] >> 8)] << 16) ^
- (FSb[(uint8) (RK[7])] << 8) ^
- (FSb[(uint8) (RK[7] >> 24)]);
-
- RK[9] = RK[1] ^ RK[8];
- RK[10] = RK[2] ^ RK[9];
- RK[11] = RK[3] ^ RK[10];
-
- RK[12] = RK[4] ^
- (FSb[(uint8) (RK[11] >> 24)] << 24) ^
- (FSb[(uint8) (RK[11] >> 16)] << 16) ^
- (FSb[(uint8) (RK[11] >> 8)] << 8) ^
- (FSb[(uint8) (RK[11])]);
-
- RK[13] = RK[5] ^ RK[12];
- RK[14] = RK[6] ^ RK[13];
- RK[15] = RK[7] ^ RK[14];
- }
- break;
- }
-
- /* setup decryption round keys */
-
- if (KT_init) {
- for (i = 0; i < 256; i++) {
- KT0[i] = RT0[FSb[i]];
- KT1[i] = RT1[FSb[i]];
- KT2[i] = RT2[FSb[i]];
- KT3[i] = RT3[FSb[i]];
- }
-
- KT_init = 0;
- }
-
- SK = (uint32 *) ctx->drk;
-
- *SK++ = *RK++;
- *SK++ = *RK++;
- *SK++ = *RK++;
- *SK++ = *RK++;
-
- for (i = 1; i < ctx->nr; i++) {
- RK -= 8;
-
- *SK++ = KT0[(uint8) (*RK >> 24)] ^
- KT1[(uint8) (*RK >> 16)] ^
- KT2[(uint8) (*RK >> 8)] ^ KT3[(uint8) (*RK)];
- RK++;
-
- *SK++ = KT0[(uint8) (*RK >> 24)] ^
- KT1[(uint8) (*RK >> 16)] ^
- KT2[(uint8) (*RK >> 8)] ^ KT3[(uint8) (*RK)];
- RK++;
-
- *SK++ = KT0[(uint8) (*RK >> 24)] ^
- KT1[(uint8) (*RK >> 16)] ^
- KT2[(uint8) (*RK >> 8)] ^ KT3[(uint8) (*RK)];
- RK++;
-
- *SK++ = KT0[(uint8) (*RK >> 24)] ^
- KT1[(uint8) (*RK >> 16)] ^
- KT2[(uint8) (*RK >> 8)] ^ KT3[(uint8) (*RK)];
- RK++;
- }
-
- RK -= 8;
-
- *SK++ = *RK++;
- *SK++ = *RK++;
- *SK++ = *RK++;
- *SK++ = *RK++;
-
- return (0);
-}
-
-/* AES 128-bit block encryption routine */
-
-void rt_aes_encrypt(struct aes_context * ctx, uint8 input[16], uint8 output[16])
-{
- uint32 *RK, X0, X1, X2, X3, Y0, Y1, Y2, Y3;
-
- RK = (uint32 *) ctx->erk;
- GET_UINT32(X0, input, 0);
- X0 ^= RK[0];
- GET_UINT32(X1, input, 4);
- X1 ^= RK[1];
- GET_UINT32(X2, input, 8);
- X2 ^= RK[2];
- GET_UINT32(X3, input, 12);
- X3 ^= RK[3];
-
-#define AES_FROUND(X0,X1,X2,X3,Y0,Y1,Y2,Y3) \
-{ \
- RK += 4; \
- \
- X0 = RK[0] ^ FT0[ (uint8) ( Y0 >> 24 ) ] ^ \
- FT1[ (uint8) ( Y1 >> 16 ) ] ^ \
- FT2[ (uint8) ( Y2 >> 8 ) ] ^ \
- FT3[ (uint8) ( Y3 ) ]; \
- \
- X1 = RK[1] ^ FT0[ (uint8) ( Y1 >> 24 ) ] ^ \
- FT1[ (uint8) ( Y2 >> 16 ) ] ^ \
- FT2[ (uint8) ( Y3 >> 8 ) ] ^ \
- FT3[ (uint8) ( Y0 ) ]; \
- \
- X2 = RK[2] ^ FT0[ (uint8) ( Y2 >> 24 ) ] ^ \
- FT1[ (uint8) ( Y3 >> 16 ) ] ^ \
- FT2[ (uint8) ( Y0 >> 8 ) ] ^ \
- FT3[ (uint8) ( Y1 ) ]; \
- \
- X3 = RK[3] ^ FT0[ (uint8) ( Y3 >> 24 ) ] ^ \
- FT1[ (uint8) ( Y0 >> 16 ) ] ^ \
- FT2[ (uint8) ( Y1 >> 8 ) ] ^ \
- FT3[ (uint8) ( Y2 ) ]; \
-}
-
- AES_FROUND(Y0, Y1, Y2, Y3, X0, X1, X2, X3); /* round 1 */
- AES_FROUND(X0, X1, X2, X3, Y0, Y1, Y2, Y3); /* round 2 */
- AES_FROUND(Y0, Y1, Y2, Y3, X0, X1, X2, X3); /* round 3 */
- AES_FROUND(X0, X1, X2, X3, Y0, Y1, Y2, Y3); /* round 4 */
- AES_FROUND(Y0, Y1, Y2, Y3, X0, X1, X2, X3); /* round 5 */
- AES_FROUND(X0, X1, X2, X3, Y0, Y1, Y2, Y3); /* round 6 */
- AES_FROUND(Y0, Y1, Y2, Y3, X0, X1, X2, X3); /* round 7 */
- AES_FROUND(X0, X1, X2, X3, Y0, Y1, Y2, Y3); /* round 8 */
- AES_FROUND(Y0, Y1, Y2, Y3, X0, X1, X2, X3); /* round 9 */
-
- if (ctx->nr > 10) {
- AES_FROUND(X0, X1, X2, X3, Y0, Y1, Y2, Y3); /* round 10 */
- AES_FROUND(Y0, Y1, Y2, Y3, X0, X1, X2, X3); /* round 11 */
- }
-
- if (ctx->nr > 12) {
- AES_FROUND(X0, X1, X2, X3, Y0, Y1, Y2, Y3); /* round 12 */
- AES_FROUND(Y0, Y1, Y2, Y3, X0, X1, X2, X3); /* round 13 */
- }
-
- /* last round */
-
- RK += 4;
-
- X0 = RK[0] ^ (FSb[(uint8) (Y0 >> 24)] << 24) ^
- (FSb[(uint8) (Y1 >> 16)] << 16) ^
- (FSb[(uint8) (Y2 >> 8)] << 8) ^ (FSb[(uint8) (Y3)]);
-
- X1 = RK[1] ^ (FSb[(uint8) (Y1 >> 24)] << 24) ^
- (FSb[(uint8) (Y2 >> 16)] << 16) ^
- (FSb[(uint8) (Y3 >> 8)] << 8) ^ (FSb[(uint8) (Y0)]);
-
- X2 = RK[2] ^ (FSb[(uint8) (Y2 >> 24)] << 24) ^
- (FSb[(uint8) (Y3 >> 16)] << 16) ^
- (FSb[(uint8) (Y0 >> 8)] << 8) ^ (FSb[(uint8) (Y1)]);
-
- X3 = RK[3] ^ (FSb[(uint8) (Y3 >> 24)] << 24) ^
- (FSb[(uint8) (Y0 >> 16)] << 16) ^
- (FSb[(uint8) (Y1 >> 8)] << 8) ^ (FSb[(uint8) (Y2)]);
-
- PUT_UINT32(X0, output, 0);
- PUT_UINT32(X1, output, 4);
- PUT_UINT32(X2, output, 8);
- PUT_UINT32(X3, output, 12);
-}
-
-/* AES 128-bit block decryption routine */
-
-void rt_aes_decrypt(struct aes_context * ctx, uint8 input[16], uint8 output[16])
-{
- uint32 *RK, X0, X1, X2, X3, Y0, Y1, Y2, Y3;
-
- RK = (uint32 *) ctx->drk;
-
- GET_UINT32(X0, input, 0);
- X0 ^= RK[0];
- GET_UINT32(X1, input, 4);
- X1 ^= RK[1];
- GET_UINT32(X2, input, 8);
- X2 ^= RK[2];
- GET_UINT32(X3, input, 12);
- X3 ^= RK[3];
-
-#define AES_RROUND(X0,X1,X2,X3,Y0,Y1,Y2,Y3) \
-{ \
- RK += 4; \
- \
- X0 = RK[0] ^ RT0[ (uint8) ( Y0 >> 24 ) ] ^ \
- RT1[ (uint8) ( Y3 >> 16 ) ] ^ \
- RT2[ (uint8) ( Y2 >> 8 ) ] ^ \
- RT3[ (uint8) ( Y1 ) ]; \
- \
- X1 = RK[1] ^ RT0[ (uint8) ( Y1 >> 24 ) ] ^ \
- RT1[ (uint8) ( Y0 >> 16 ) ] ^ \
- RT2[ (uint8) ( Y3 >> 8 ) ] ^ \
- RT3[ (uint8) ( Y2 ) ]; \
- \
- X2 = RK[2] ^ RT0[ (uint8) ( Y2 >> 24 ) ] ^ \
- RT1[ (uint8) ( Y1 >> 16 ) ] ^ \
- RT2[ (uint8) ( Y0 >> 8 ) ] ^ \
- RT3[ (uint8) ( Y3 ) ]; \
- \
- X3 = RK[3] ^ RT0[ (uint8) ( Y3 >> 24 ) ] ^ \
- RT1[ (uint8) ( Y2 >> 16 ) ] ^ \
- RT2[ (uint8) ( Y1 >> 8 ) ] ^ \
- RT3[ (uint8) ( Y0 ) ]; \
-}
-
- AES_RROUND(Y0, Y1, Y2, Y3, X0, X1, X2, X3); /* round 1 */
- AES_RROUND(X0, X1, X2, X3, Y0, Y1, Y2, Y3); /* round 2 */
- AES_RROUND(Y0, Y1, Y2, Y3, X0, X1, X2, X3); /* round 3 */
- AES_RROUND(X0, X1, X2, X3, Y0, Y1, Y2, Y3); /* round 4 */
- AES_RROUND(Y0, Y1, Y2, Y3, X0, X1, X2, X3); /* round 5 */
- AES_RROUND(X0, X1, X2, X3, Y0, Y1, Y2, Y3); /* round 6 */
- AES_RROUND(Y0, Y1, Y2, Y3, X0, X1, X2, X3); /* round 7 */
- AES_RROUND(X0, X1, X2, X3, Y0, Y1, Y2, Y3); /* round 8 */
- AES_RROUND(Y0, Y1, Y2, Y3, X0, X1, X2, X3); /* round 9 */
-
- if (ctx->nr > 10) {
- AES_RROUND(X0, X1, X2, X3, Y0, Y1, Y2, Y3); /* round 10 */
- AES_RROUND(Y0, Y1, Y2, Y3, X0, X1, X2, X3); /* round 11 */
- }
-
- if (ctx->nr > 12) {
- AES_RROUND(X0, X1, X2, X3, Y0, Y1, Y2, Y3); /* round 12 */
- AES_RROUND(Y0, Y1, Y2, Y3, X0, X1, X2, X3); /* round 13 */
- }
-
- /* last round */
-
- RK += 4;
-
- X0 = RK[0] ^ (RSb[(uint8) (Y0 >> 24)] << 24) ^
- (RSb[(uint8) (Y3 >> 16)] << 16) ^
- (RSb[(uint8) (Y2 >> 8)] << 8) ^ (RSb[(uint8) (Y1)]);
-
- X1 = RK[1] ^ (RSb[(uint8) (Y1 >> 24)] << 24) ^
- (RSb[(uint8) (Y0 >> 16)] << 16) ^
- (RSb[(uint8) (Y3 >> 8)] << 8) ^ (RSb[(uint8) (Y2)]);
-
- X2 = RK[2] ^ (RSb[(uint8) (Y2 >> 24)] << 24) ^
- (RSb[(uint8) (Y1 >> 16)] << 16) ^
- (RSb[(uint8) (Y0 >> 8)] << 8) ^ (RSb[(uint8) (Y3)]);
-
- X3 = RK[3] ^ (RSb[(uint8) (Y3 >> 24)] << 24) ^
- (RSb[(uint8) (Y2 >> 16)] << 16) ^
- (RSb[(uint8) (Y1 >> 8)] << 8) ^ (RSb[(uint8) (Y0)]);
-
- PUT_UINT32(X0, output, 0);
- PUT_UINT32(X1, output, 4);
- PUT_UINT32(X2, output, 8);
- PUT_UINT32(X3, output, 12);
-}
-
-/*
- ==========================================================================
- Description:
- ENCRYPT AES GTK before sending in EAPOL frame.
- AES GTK length = 128 bit, so fix blocks for aes-key-wrap as 2 in this function.
- This function references to RFC 3394 for aes key wrap algorithm.
- Return:
- ==========================================================================
-*/
-void AES_GTK_KEY_WRAP(u8 * key,
- u8 * plaintext,
- u32 p_len, u8 * ciphertext)
-{
- u8 A[8], BIN[16], BOUT[16];
- u8 R[512];
- int num_blocks = p_len / 8; /* unit:64bits */
- int i, j;
- struct aes_context aesctx;
- u8 xor;
-
- rt_aes_set_key(&aesctx, key, 128);
-
- /* Init IA */
- for (i = 0; i < 8; i++)
- A[i] = 0xa6;
-
- /*Input plaintext */
- for (i = 0; i < num_blocks; i++) {
- for (j = 0; j < 8; j++)
- R[8 * (i + 1) + j] = plaintext[8 * i + j];
- }
-
- /* Key Mix */
- for (j = 0; j < 6; j++) {
- for (i = 1; i <= num_blocks; i++) {
- /*phase 1 */
- NdisMoveMemory(BIN, A, 8);
- NdisMoveMemory(&BIN[8], &R[8 * i], 8);
- rt_aes_encrypt(&aesctx, BIN, BOUT);
-
- NdisMoveMemory(A, &BOUT[0], 8);
- xor = num_blocks * j + i;
- A[7] = BOUT[7] ^ xor;
- NdisMoveMemory(&R[8 * i], &BOUT[8], 8);
- }
- }
-
- /* Output ciphertext */
- NdisMoveMemory(ciphertext, A, 8);
-
- for (i = 1; i <= num_blocks; i++) {
- for (j = 0; j < 8; j++)
- ciphertext[8 * i + j] = R[8 * i + j];
- }
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Misc function to decrypt AES body
-
- Arguments:
-
- Return Value:
-
- Note:
- This function references to RFC 3394 for aes key unwrap algorithm.
-
- ========================================================================
-*/
-void AES_GTK_KEY_UNWRAP(u8 * key,
- u8 * plaintext,
- u32 c_len, u8 * ciphertext)
-{
- u8 A[8], BIN[16], BOUT[16];
- u8 xor;
- int i, j;
- struct aes_context aesctx;
- u8 *R;
- int num_blocks = c_len / 8; /* unit:64bits */
-
- os_alloc_mem(NULL, (u8 **) & R, 512);
-
- if (R == NULL) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("AES_GTK_KEY_UNWRAP: no memory!\n"));
- return;
- }
- /* End of if */
- /* Initialize */
- NdisMoveMemory(A, ciphertext, 8);
- /*Input plaintext */
- for (i = 0; i < (c_len - 8); i++) {
- R[i] = ciphertext[i + 8];
- }
-
- rt_aes_set_key(&aesctx, key, 128);
-
- for (j = 5; j >= 0; j--) {
- for (i = (num_blocks - 1); i > 0; i--) {
- xor = (num_blocks - 1) * j + i;
- NdisMoveMemory(BIN, A, 8);
- BIN[7] = A[7] ^ xor;
- NdisMoveMemory(&BIN[8], &R[(i - 1) * 8], 8);
- rt_aes_decrypt(&aesctx, BIN, BOUT);
- NdisMoveMemory(A, &BOUT[0], 8);
- NdisMoveMemory(&R[(i - 1) * 8], &BOUT[8], 8);
- }
- }
-
- /* OUTPUT */
- for (i = 0; i < c_len; i++) {
- plaintext[i] = R[i];
- }
-
- os_free_mem(NULL, R);
-}
diff --git a/drivers/staging/rt2860/common/cmm_asic.c b/drivers/staging/rt2860/common/cmm_asic.c
deleted file mode 100644
index 4d77e83..0000000
--- a/drivers/staging/rt2860/common/cmm_asic.c
+++ /dev/null
@@ -1,2565 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- cmm_asic.c
-
- Abstract:
- Functions used to communicate with ASIC
-
- Revision History:
- Who When What
- -------- ---------- ----------------------------------------------
-*/
-
-#include "../rt_config.h"
-
-/* Reset the RFIC setting to new series */
-struct rt_rtmp_rf_regs RF2850RegTable[] = {
-/* ch R1 R2 R3(TX0~4=0) R4 */
- {1, 0x98402ecc, 0x984c0786, 0x9816b455, 0x9800510b}
- ,
- {2, 0x98402ecc, 0x984c0786, 0x98168a55, 0x9800519f}
- ,
- {3, 0x98402ecc, 0x984c078a, 0x98168a55, 0x9800518b}
- ,
- {4, 0x98402ecc, 0x984c078a, 0x98168a55, 0x9800519f}
- ,
- {5, 0x98402ecc, 0x984c078e, 0x98168a55, 0x9800518b}
- ,
- {6, 0x98402ecc, 0x984c078e, 0x98168a55, 0x9800519f}
- ,
- {7, 0x98402ecc, 0x984c0792, 0x98168a55, 0x9800518b}
- ,
- {8, 0x98402ecc, 0x984c0792, 0x98168a55, 0x9800519f}
- ,
- {9, 0x98402ecc, 0x984c0796, 0x98168a55, 0x9800518b}
- ,
- {10, 0x98402ecc, 0x984c0796, 0x98168a55, 0x9800519f}
- ,
- {11, 0x98402ecc, 0x984c079a, 0x98168a55, 0x9800518b}
- ,
- {12, 0x98402ecc, 0x984c079a, 0x98168a55, 0x9800519f}
- ,
- {13, 0x98402ecc, 0x984c079e, 0x98168a55, 0x9800518b}
- ,
- {14, 0x98402ecc, 0x984c07a2, 0x98168a55, 0x98005193}
- ,
-
- /* 802.11 UNI / HyperLan 2 */
- {36, 0x98402ecc, 0x984c099a, 0x98158a55, 0x980ed1a3}
- ,
- {38, 0x98402ecc, 0x984c099e, 0x98158a55, 0x980ed193}
- ,
- {40, 0x98402ec8, 0x984c0682, 0x98158a55, 0x980ed183}
- ,
- {44, 0x98402ec8, 0x984c0682, 0x98158a55, 0x980ed1a3}
- ,
- {46, 0x98402ec8, 0x984c0686, 0x98158a55, 0x980ed18b}
- ,
- {48, 0x98402ec8, 0x984c0686, 0x98158a55, 0x980ed19b}
- ,
- {52, 0x98402ec8, 0x984c068a, 0x98158a55, 0x980ed193}
- ,
- {54, 0x98402ec8, 0x984c068a, 0x98158a55, 0x980ed1a3}
- ,
- {56, 0x98402ec8, 0x984c068e, 0x98158a55, 0x980ed18b}
- ,
- {60, 0x98402ec8, 0x984c0692, 0x98158a55, 0x980ed183}
- ,
- {62, 0x98402ec8, 0x984c0692, 0x98158a55, 0x980ed193}
- ,
- {64, 0x98402ec8, 0x984c0692, 0x98158a55, 0x980ed1a3}
- , /* Plugfest#4, Day4, change RFR3 left4th 9->5. */
-
- /* 802.11 HyperLan 2 */
- {100, 0x98402ec8, 0x984c06b2, 0x98178a55, 0x980ed783}
- ,
-
- /* 2008.04.30 modified */
- /* The system team has AN to improve the EVM value */
- /* for channel 102 to 108 for the RT2850/RT2750 dual band solution. */
- {102, 0x98402ec8, 0x985c06b2, 0x98578a55, 0x980ed793}
- ,
- {104, 0x98402ec8, 0x985c06b2, 0x98578a55, 0x980ed1a3}
- ,
- {108, 0x98402ecc, 0x985c0a32, 0x98578a55, 0x980ed193}
- ,
-
- {110, 0x98402ecc, 0x984c0a36, 0x98178a55, 0x980ed183}
- ,
- {112, 0x98402ecc, 0x984c0a36, 0x98178a55, 0x980ed19b}
- ,
- {116, 0x98402ecc, 0x984c0a3a, 0x98178a55, 0x980ed1a3}
- ,
- {118, 0x98402ecc, 0x984c0a3e, 0x98178a55, 0x980ed193}
- ,
- {120, 0x98402ec4, 0x984c0382, 0x98178a55, 0x980ed183}
- ,
- {124, 0x98402ec4, 0x984c0382, 0x98178a55, 0x980ed193}
- ,
- {126, 0x98402ec4, 0x984c0382, 0x98178a55, 0x980ed15b}
- , /* 0x980ed1bb->0x980ed15b required by Rory 20070927 */
- {128, 0x98402ec4, 0x984c0382, 0x98178a55, 0x980ed1a3}
- ,
- {132, 0x98402ec4, 0x984c0386, 0x98178a55, 0x980ed18b}
- ,
- {134, 0x98402ec4, 0x984c0386, 0x98178a55, 0x980ed193}
- ,
- {136, 0x98402ec4, 0x984c0386, 0x98178a55, 0x980ed19b}
- ,
- {140, 0x98402ec4, 0x984c038a, 0x98178a55, 0x980ed183}
- ,
-
- /* 802.11 UNII */
- {149, 0x98402ec4, 0x984c038a, 0x98178a55, 0x980ed1a7}
- ,
- {151, 0x98402ec4, 0x984c038e, 0x98178a55, 0x980ed187}
- ,
- {153, 0x98402ec4, 0x984c038e, 0x98178a55, 0x980ed18f}
- ,
- {157, 0x98402ec4, 0x984c038e, 0x98178a55, 0x980ed19f}
- ,
- {159, 0x98402ec4, 0x984c038e, 0x98178a55, 0x980ed1a7}
- ,
- {161, 0x98402ec4, 0x984c0392, 0x98178a55, 0x980ed187}
- ,
- {165, 0x98402ec4, 0x984c0392, 0x98178a55, 0x980ed197}
- ,
- {167, 0x98402ec4, 0x984c03d2, 0x98179855, 0x9815531f}
- ,
- {169, 0x98402ec4, 0x984c03d2, 0x98179855, 0x98155327}
- ,
- {171, 0x98402ec4, 0x984c03d6, 0x98179855, 0x98155307}
- ,
- {173, 0x98402ec4, 0x984c03d6, 0x98179855, 0x9815530f}
- ,
-
- /* Japan */
- {184, 0x95002ccc, 0x9500491e, 0x9509be55, 0x950c0a0b}
- ,
- {188, 0x95002ccc, 0x95004922, 0x9509be55, 0x950c0a13}
- ,
- {192, 0x95002ccc, 0x95004926, 0x9509be55, 0x950c0a1b}
- ,
- {196, 0x95002ccc, 0x9500492a, 0x9509be55, 0x950c0a23}
- ,
- {208, 0x95002ccc, 0x9500493a, 0x9509be55, 0x950c0a13}
- ,
- {212, 0x95002ccc, 0x9500493e, 0x9509be55, 0x950c0a1b}
- ,
- {216, 0x95002ccc, 0x95004982, 0x9509be55, 0x950c0a23}
- ,
-
- /* still lack of MMAC(Japan) ch 34,38,42,46 */
-};
-
-u8 NUM_OF_2850_CHNL = (sizeof(RF2850RegTable) / sizeof(struct rt_rtmp_rf_regs));
-
-struct rt_frequency_item FreqItems3020[] = {
- /**************************************************/
- /* ISM : 2.4 to 2.483 GHz // */
- /**************************************************/
- /* 11g */
- /**************************************************/
- /*-CH---N-------R---K----------- */
- {1, 241, 2, 2}
- ,
- {2, 241, 2, 7}
- ,
- {3, 242, 2, 2}
- ,
- {4, 242, 2, 7}
- ,
- {5, 243, 2, 2}
- ,
- {6, 243, 2, 7}
- ,
- {7, 244, 2, 2}
- ,
- {8, 244, 2, 7}
- ,
- {9, 245, 2, 2}
- ,
- {10, 245, 2, 7}
- ,
- {11, 246, 2, 2}
- ,
- {12, 246, 2, 7}
- ,
- {13, 247, 2, 2}
- ,
- {14, 248, 2, 4}
- ,
-};
-
-u8 NUM_OF_3020_CHNL = (sizeof(FreqItems3020) / sizeof(struct rt_frequency_item));
-
-void AsicUpdateAutoFallBackTable(struct rt_rtmp_adapter *pAd, u8 *pRateTable)
-{
- u8 i;
- HT_FBK_CFG0_STRUC HtCfg0;
- HT_FBK_CFG1_STRUC HtCfg1;
- LG_FBK_CFG0_STRUC LgCfg0;
- LG_FBK_CFG1_STRUC LgCfg1;
- struct rt_rtmp_tx_rate_switch *pCurrTxRate, *pNextTxRate;
-
- /* set to initial value */
- HtCfg0.word = 0x65432100;
- HtCfg1.word = 0xedcba988;
- LgCfg0.word = 0xedcba988;
- LgCfg1.word = 0x00002100;
-
- pNextTxRate = (struct rt_rtmp_tx_rate_switch *) pRateTable + 1;
- for (i = 1; i < *((u8 *)pRateTable); i++) {
- pCurrTxRate = (struct rt_rtmp_tx_rate_switch *) pRateTable + 1 + i;
- switch (pCurrTxRate->Mode) {
- case 0: /*CCK */
- break;
- case 1: /*OFDM */
- {
- switch (pCurrTxRate->CurrMCS) {
- case 0:
- LgCfg0.field.OFDMMCS0FBK =
- (pNextTxRate->Mode ==
- MODE_OFDM) ? (pNextTxRate->
- CurrMCS +
- 8) : pNextTxRate->
- CurrMCS;
- break;
- case 1:
- LgCfg0.field.OFDMMCS1FBK =
- (pNextTxRate->Mode ==
- MODE_OFDM) ? (pNextTxRate->
- CurrMCS +
- 8) : pNextTxRate->
- CurrMCS;
- break;
- case 2:
- LgCfg0.field.OFDMMCS2FBK =
- (pNextTxRate->Mode ==
- MODE_OFDM) ? (pNextTxRate->
- CurrMCS +
- 8) : pNextTxRate->
- CurrMCS;
- break;
- case 3:
- LgCfg0.field.OFDMMCS3FBK =
- (pNextTxRate->Mode ==
- MODE_OFDM) ? (pNextTxRate->
- CurrMCS +
- 8) : pNextTxRate->
- CurrMCS;
- break;
- case 4:
- LgCfg0.field.OFDMMCS4FBK =
- (pNextTxRate->Mode ==
- MODE_OFDM) ? (pNextTxRate->
- CurrMCS +
- 8) : pNextTxRate->
- CurrMCS;
- break;
- case 5:
- LgCfg0.field.OFDMMCS5FBK =
- (pNextTxRate->Mode ==
- MODE_OFDM) ? (pNextTxRate->
- CurrMCS +
- 8) : pNextTxRate->
- CurrMCS;
- break;
- case 6:
- LgCfg0.field.OFDMMCS6FBK =
- (pNextTxRate->Mode ==
- MODE_OFDM) ? (pNextTxRate->
- CurrMCS +
- 8) : pNextTxRate->
- CurrMCS;
- break;
- case 7:
- LgCfg0.field.OFDMMCS7FBK =
- (pNextTxRate->Mode ==
- MODE_OFDM) ? (pNextTxRate->
- CurrMCS +
- 8) : pNextTxRate->
- CurrMCS;
- break;
- }
- }
- break;
- case 2: /*HT-MIX */
- case 3: /*HT-GF */
- {
- if ((pNextTxRate->Mode >= MODE_HTMIX)
- && (pCurrTxRate->CurrMCS !=
- pNextTxRate->CurrMCS)) {
- switch (pCurrTxRate->CurrMCS) {
- case 0:
- HtCfg0.field.HTMCS0FBK =
- pNextTxRate->CurrMCS;
- break;
- case 1:
- HtCfg0.field.HTMCS1FBK =
- pNextTxRate->CurrMCS;
- break;
- case 2:
- HtCfg0.field.HTMCS2FBK =
- pNextTxRate->CurrMCS;
- break;
- case 3:
- HtCfg0.field.HTMCS3FBK =
- pNextTxRate->CurrMCS;
- break;
- case 4:
- HtCfg0.field.HTMCS4FBK =
- pNextTxRate->CurrMCS;
- break;
- case 5:
- HtCfg0.field.HTMCS5FBK =
- pNextTxRate->CurrMCS;
- break;
- case 6:
- HtCfg0.field.HTMCS6FBK =
- pNextTxRate->CurrMCS;
- break;
- case 7:
- HtCfg0.field.HTMCS7FBK =
- pNextTxRate->CurrMCS;
- break;
- case 8:
- HtCfg1.field.HTMCS8FBK =
- pNextTxRate->CurrMCS;
- break;
- case 9:
- HtCfg1.field.HTMCS9FBK =
- pNextTxRate->CurrMCS;
- break;
- case 10:
- HtCfg1.field.HTMCS10FBK =
- pNextTxRate->CurrMCS;
- break;
- case 11:
- HtCfg1.field.HTMCS11FBK =
- pNextTxRate->CurrMCS;
- break;
- case 12:
- HtCfg1.field.HTMCS12FBK =
- pNextTxRate->CurrMCS;
- break;
- case 13:
- HtCfg1.field.HTMCS13FBK =
- pNextTxRate->CurrMCS;
- break;
- case 14:
- HtCfg1.field.HTMCS14FBK =
- pNextTxRate->CurrMCS;
- break;
- case 15:
- HtCfg1.field.HTMCS15FBK =
- pNextTxRate->CurrMCS;
- break;
- default:
- DBGPRINT(RT_DEBUG_ERROR,
- ("AsicUpdateAutoFallBackTable: not support CurrMCS=%d\n",
- pCurrTxRate->
- CurrMCS));
- }
- }
- }
- break;
- }
-
- pNextTxRate = pCurrTxRate;
- }
-
- RTMP_IO_WRITE32(pAd, HT_FBK_CFG0, HtCfg0.word);
- RTMP_IO_WRITE32(pAd, HT_FBK_CFG1, HtCfg1.word);
- RTMP_IO_WRITE32(pAd, LG_FBK_CFG0, LgCfg0.word);
- RTMP_IO_WRITE32(pAd, LG_FBK_CFG1, LgCfg1.word);
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Set MAC register value according operation mode.
- OperationMode AND bNonGFExist are for MM and GF Proteciton.
- If MM or GF mask is not set, those passing argument doesn't not take effect.
-
- Operation mode meaning:
- = 0 : Pure HT, no preotection.
- = 0x01; there may be non-HT devices in both the control and extension channel, protection is optional in BSS.
- = 0x10: No Transmission in 40M is protected.
- = 0x11: Transmission in both 40M and 20M shall be protected
- if (bNonGFExist)
- we should choose not to use GF. But still set correct ASIC registers.
- ========================================================================
-*/
-void AsicUpdateProtect(struct rt_rtmp_adapter *pAd,
- u16 OperationMode,
- u8 SetMask,
- IN BOOLEAN bDisableBGProtect, IN BOOLEAN bNonGFExist)
-{
- PROT_CFG_STRUC ProtCfg, ProtCfg4;
- u32 Protect[6];
- u16 offset;
- u8 i;
- u32 MacReg = 0;
-
- if (!(pAd->CommonCfg.bHTProtect) && (OperationMode != 8)) {
- return;
- }
-
- if (pAd->BATable.numDoneOriginator) {
- /* */
- /* enable the RTS/CTS to avoid channel collision */
- /* */
- SetMask = ALLN_SETPROTECT;
- OperationMode = 8;
- }
- /* Config ASIC RTS threshold register */
- RTMP_IO_READ32(pAd, TX_RTS_CFG, &MacReg);
- MacReg &= 0xFF0000FF;
- /* If the user want disable RtsThreshold and enable Amsdu/Ralink-Aggregation, set the RtsThreshold as 4096 */
- if (((pAd->CommonCfg.BACapability.field.AmsduEnable) ||
- (pAd->CommonCfg.bAggregationCapable == TRUE))
- && pAd->CommonCfg.RtsThreshold == MAX_RTS_THRESHOLD) {
- MacReg |= (0x1000 << 8);
- } else {
- MacReg |= (pAd->CommonCfg.RtsThreshold << 8);
- }
-
- RTMP_IO_WRITE32(pAd, TX_RTS_CFG, MacReg);
-
- /* Initial common protection settings */
- RTMPZeroMemory(Protect, sizeof(Protect));
- ProtCfg4.word = 0;
- ProtCfg.word = 0;
- ProtCfg.field.TxopAllowGF40 = 1;
- ProtCfg.field.TxopAllowGF20 = 1;
- ProtCfg.field.TxopAllowMM40 = 1;
- ProtCfg.field.TxopAllowMM20 = 1;
- ProtCfg.field.TxopAllowOfdm = 1;
- ProtCfg.field.TxopAllowCck = 1;
- ProtCfg.field.RTSThEn = 1;
- ProtCfg.field.ProtectNav = ASIC_SHORTNAV;
-
- /* update PHY mode and rate */
- if (pAd->CommonCfg.Channel > 14)
- ProtCfg.field.ProtectRate = 0x4000;
- ProtCfg.field.ProtectRate |= pAd->CommonCfg.RtsRate;
-
- /* Handle legacy(B/G) protection */
- if (bDisableBGProtect) {
- /*ProtCfg.field.ProtectRate = pAd->CommonCfg.RtsRate; */
- ProtCfg.field.ProtectCtrl = 0;
- Protect[0] = ProtCfg.word;
- Protect[1] = ProtCfg.word;
- pAd->FlgCtsEnabled = 0; /* CTS-self is not used */
- } else {
- /*ProtCfg.field.ProtectRate = pAd->CommonCfg.RtsRate; */
- ProtCfg.field.ProtectCtrl = 0; /* CCK do not need to be protected */
- Protect[0] = ProtCfg.word;
- ProtCfg.field.ProtectCtrl = ASIC_CTS; /* OFDM needs using CCK to protect */
- Protect[1] = ProtCfg.word;
- pAd->FlgCtsEnabled = 1; /* CTS-self is used */
- }
-
- /* Decide HT frame protection. */
- if ((SetMask & ALLN_SETPROTECT) != 0) {
- switch (OperationMode) {
- case 0x0:
- /* NO PROTECT */
- /* 1.All STAs in the BSS are 20/40 MHz HT */
- /* 2. in ai 20/40MHz BSS */
- /* 3. all STAs are 20MHz in a 20MHz BSS */
- /* Pure HT. no protection. */
-
- /* MM20_PROT_CFG */
- /* Reserved (31:27) */
- /* PROT_TXOP(25:20) -- 010111 */
- /* PROT_NAV(19:18) -- 01 (Short NAV protection) */
- /* PROT_CTRL(17:16) -- 00 (None) */
- /* PROT_RATE(15:0) -- 0x4004 (OFDM 24M) */
- Protect[2] = 0x01744004;
-
- /* MM40_PROT_CFG */
- /* Reserved (31:27) */
- /* PROT_TXOP(25:20) -- 111111 */
- /* PROT_NAV(19:18) -- 01 (Short NAV protection) */
- /* PROT_CTRL(17:16) -- 00 (None) */
- /* PROT_RATE(15:0) -- 0x4084 (duplicate OFDM 24M) */
- Protect[3] = 0x03f44084;
-
- /* CF20_PROT_CFG */
- /* Reserved (31:27) */
- /* PROT_TXOP(25:20) -- 010111 */
- /* PROT_NAV(19:18) -- 01 (Short NAV protection) */
- /* PROT_CTRL(17:16) -- 00 (None) */
- /* PROT_RATE(15:0) -- 0x4004 (OFDM 24M) */
- Protect[4] = 0x01744004;
-
- /* CF40_PROT_CFG */
- /* Reserved (31:27) */
- /* PROT_TXOP(25:20) -- 111111 */
- /* PROT_NAV(19:18) -- 01 (Short NAV protection) */
- /* PROT_CTRL(17:16) -- 00 (None) */
- /* PROT_RATE(15:0) -- 0x4084 (duplicate OFDM 24M) */
- Protect[5] = 0x03f44084;
-
- if (bNonGFExist) {
- /* PROT_NAV(19:18) -- 01 (Short NAV protectiion) */
- /* PROT_CTRL(17:16) -- 01 (RTS/CTS) */
- Protect[4] = 0x01754004;
- Protect[5] = 0x03f54084;
- }
- pAd->CommonCfg.IOTestParm.bRTSLongProtOn = FALSE;
- break;
-
- case 1:
- /* This is "HT non-member protection mode." */
- /* If there may be non-HT STAs my BSS */
- ProtCfg.word = 0x01744004; /* PROT_CTRL(17:16) : 0 (None) */
- ProtCfg4.word = 0x03f44084; /* duplicaet legacy 24M. BW set 1. */
- if (OPSTATUS_TEST_FLAG
- (pAd, fOP_STATUS_BG_PROTECTION_INUSED)) {
- ProtCfg.word = 0x01740003; /*ERP use Protection bit is set, use protection rate at Clause 18.. */
- ProtCfg4.word = 0x03f40003; /* Don't duplicate RTS/CTS in CCK mode. 0x03f40083; */
- }
- /*Assign Protection method for 20&40 MHz packets */
- ProtCfg.field.ProtectCtrl = ASIC_RTS;
- ProtCfg.field.ProtectNav = ASIC_SHORTNAV;
- ProtCfg4.field.ProtectCtrl = ASIC_RTS;
- ProtCfg4.field.ProtectNav = ASIC_SHORTNAV;
- Protect[2] = ProtCfg.word;
- Protect[3] = ProtCfg4.word;
- Protect[4] = ProtCfg.word;
- Protect[5] = ProtCfg4.word;
- pAd->CommonCfg.IOTestParm.bRTSLongProtOn = TRUE;
- break;
-
- case 2:
- /* If only HT STAs are in BSS. at least one is 20MHz. Only protect 40MHz packets */
- ProtCfg.word = 0x01744004; /* PROT_CTRL(17:16) : 0 (None) */
- ProtCfg4.word = 0x03f44084; /* duplicaet legacy 24M. BW set 1. */
-
- /*Assign Protection method for 40MHz packets */
- ProtCfg4.field.ProtectCtrl = ASIC_RTS;
- ProtCfg4.field.ProtectNav = ASIC_SHORTNAV;
- Protect[2] = ProtCfg.word;
- Protect[3] = ProtCfg4.word;
- if (bNonGFExist) {
- ProtCfg.field.ProtectCtrl = ASIC_RTS;
- ProtCfg.field.ProtectNav = ASIC_SHORTNAV;
- }
- Protect[4] = ProtCfg.word;
- Protect[5] = ProtCfg4.word;
-
- pAd->CommonCfg.IOTestParm.bRTSLongProtOn = FALSE;
- break;
-
- case 3:
- /* HT mixed mode. PROTECT ALL! */
- /* Assign Rate */
- ProtCfg.word = 0x01744004; /*duplicaet legacy 24M. BW set 1. */
- ProtCfg4.word = 0x03f44084;
- /* both 20MHz and 40MHz are protected. Whether use RTS or CTS-to-self depends on the */
- if (OPSTATUS_TEST_FLAG
- (pAd, fOP_STATUS_BG_PROTECTION_INUSED)) {
- ProtCfg.word = 0x01740003; /*ERP use Protection bit is set, use protection rate at Clause 18.. */
- ProtCfg4.word = 0x03f40003; /* Don't duplicate RTS/CTS in CCK mode. 0x03f40083 */
- }
- /*Assign Protection method for 20&40 MHz packets */
- ProtCfg.field.ProtectCtrl = ASIC_RTS;
- ProtCfg.field.ProtectNav = ASIC_SHORTNAV;
- ProtCfg4.field.ProtectCtrl = ASIC_RTS;
- ProtCfg4.field.ProtectNav = ASIC_SHORTNAV;
- Protect[2] = ProtCfg.word;
- Protect[3] = ProtCfg4.word;
- Protect[4] = ProtCfg.word;
- Protect[5] = ProtCfg4.word;
- pAd->CommonCfg.IOTestParm.bRTSLongProtOn = TRUE;
- break;
-
- case 8:
- /* Special on for Atheros problem n chip. */
- Protect[2] = 0x01754004;
- Protect[3] = 0x03f54084;
- Protect[4] = 0x01754004;
- Protect[5] = 0x03f54084;
- pAd->CommonCfg.IOTestParm.bRTSLongProtOn = TRUE;
- break;
- }
- }
-
- offset = CCK_PROT_CFG;
- for (i = 0; i < 6; i++) {
- if ((SetMask & (1 << i))) {
- RTMP_IO_WRITE32(pAd, offset + i * 4, Protect[i]);
- }
- }
-}
-
-/*
- ==========================================================================
- Description:
-
- IRQL = PASSIVE_LEVEL
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
- */
-void AsicSwitchChannel(struct rt_rtmp_adapter *pAd, u8 Channel, IN BOOLEAN bScan)
-{
- unsigned long R2 = 0, R3 = DEFAULT_RF_TX_POWER, R4 = 0;
- char TxPwer = 0, TxPwer2 = DEFAULT_RF_TX_POWER; /*Bbp94 = BBPR94_DEFAULT, TxPwer2 = DEFAULT_RF_TX_POWER; */
- u8 index;
- u32 Value = 0; /*BbpReg, Value; */
- struct rt_rtmp_rf_regs *RFRegTable;
- u8 RFValue;
-
- RFValue = 0;
- /* Search Tx power value */
- /* We can't use ChannelList to search channel, since some central channl's txpowr doesn't list */
- /* in ChannelList, so use TxPower array instead. */
- /* */
- for (index = 0; index < MAX_NUM_OF_CHANNELS; index++) {
- if (Channel == pAd->TxPower[index].Channel) {
- TxPwer = pAd->TxPower[index].Power;
- TxPwer2 = pAd->TxPower[index].Power2;
- break;
- }
- }
-
- if (index == MAX_NUM_OF_CHANNELS) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("AsicSwitchChannel: Can't find the Channel#%d \n",
- Channel));
- }
-#ifdef RT30xx
- /* The RF programming sequence is difference between 3xxx and 2xxx */
- if ((IS_RT3070(pAd) || IS_RT3090(pAd) || IS_RT3390(pAd))
- && ((pAd->RfIcType == RFIC_3020) || (pAd->RfIcType == RFIC_2020)
- || (pAd->RfIcType == RFIC_3021)
- || (pAd->RfIcType == RFIC_3022))) {
- /* modify by WY for Read RF Reg. error */
-
- for (index = 0; index < NUM_OF_3020_CHNL; index++) {
- if (Channel == FreqItems3020[index].Channel) {
- /* Programming channel parameters */
- RT30xxWriteRFRegister(pAd, RF_R02,
- FreqItems3020[index].N);
- RT30xxWriteRFRegister(pAd, RF_R03,
- FreqItems3020[index].K);
- RT30xxReadRFRegister(pAd, RF_R06, &RFValue);
- RFValue =
- (RFValue & 0xFC) | FreqItems3020[index].R;
- RT30xxWriteRFRegister(pAd, RF_R06, RFValue);
-
- /* Set Tx0 Power */
- RT30xxReadRFRegister(pAd, RF_R12, &RFValue);
- RFValue = (RFValue & 0xE0) | TxPwer;
- RT30xxWriteRFRegister(pAd, RF_R12, RFValue);
-
- /* Set Tx1 Power */
- RT30xxReadRFRegister(pAd, RF_R13, &RFValue);
- RFValue = (RFValue & 0xE0) | TxPwer2;
- RT30xxWriteRFRegister(pAd, RF_R13, RFValue);
-
- /* Tx/Rx Stream setting */
- RT30xxReadRFRegister(pAd, RF_R01, &RFValue);
- /*if (IS_RT3090(pAd)) */
- /* RFValue |= 0x01; // Enable RF block. */
- RFValue &= 0x03; /*clear bit[7~2] */
- if (pAd->Antenna.field.TxPath == 1)
- RFValue |= 0xA0;
- else if (pAd->Antenna.field.TxPath == 2)
- RFValue |= 0x80;
- if (pAd->Antenna.field.RxPath == 1)
- RFValue |= 0x50;
- else if (pAd->Antenna.field.RxPath == 2)
- RFValue |= 0x40;
- RT30xxWriteRFRegister(pAd, RF_R01, RFValue);
-
- /* Set RF offset */
- RT30xxReadRFRegister(pAd, RF_R23, &RFValue);
- RFValue = (RFValue & 0x80) | pAd->RfFreqOffset;
- RT30xxWriteRFRegister(pAd, RF_R23, RFValue);
-
- /* Set BW */
- if (!bScan
- && (pAd->CommonCfg.BBPCurrentBW == BW_40)) {
- RFValue = pAd->Mlme.CaliBW40RfR24;
- /*DISABLE_11N_CHECK(pAd); */
- } else {
- RFValue = pAd->Mlme.CaliBW20RfR24;
- }
- RT30xxWriteRFRegister(pAd, RF_R24, RFValue);
- RT30xxWriteRFRegister(pAd, RF_R31, RFValue);
-
- /* Enable RF tuning */
- RT30xxReadRFRegister(pAd, RF_R07, &RFValue);
- RFValue = RFValue | 0x1;
- RT30xxWriteRFRegister(pAd, RF_R07, RFValue);
-
- /* latch channel for future usage. */
- pAd->LatchRfRegs.Channel = Channel;
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("SwitchChannel#%d(RF=%d, Pwr0=%d, Pwr1=%d, %dT), N=0x%02X, K=0x%02X, R=0x%02X\n",
- Channel, pAd->RfIcType, TxPwer,
- TxPwer2, pAd->Antenna.field.TxPath,
- FreqItems3020[index].N,
- FreqItems3020[index].K,
- FreqItems3020[index].R));
-
- break;
- }
- }
- } else
-#endif /* RT30xx // */
- {
- RFRegTable = RF2850RegTable;
- switch (pAd->RfIcType) {
- case RFIC_2820:
- case RFIC_2850:
- case RFIC_2720:
- case RFIC_2750:
-
- for (index = 0; index < NUM_OF_2850_CHNL; index++) {
- if (Channel == RFRegTable[index].Channel) {
- R2 = RFRegTable[index].R2;
- if (pAd->Antenna.field.TxPath == 1) {
- R2 |= 0x4000; /* If TXpath is 1, bit 14 = 1; */
- }
-
- if (pAd->Antenna.field.RxPath == 2) {
- R2 |= 0x40; /* write 1 to off Rxpath. */
- } else if (pAd->Antenna.field.RxPath ==
- 1) {
- R2 |= 0x20040; /* write 1 to off RxPath */
- }
-
- if (Channel > 14) {
- /* initialize R3, R4 */
- R3 = (RFRegTable[index].
- R3 & 0xffffc1ff);
- R4 = (RFRegTable[index].
- R4 & (~0x001f87c0)) |
- (pAd->RfFreqOffset << 15);
-
- /* 5G band power range: 0xF9~0X0F, TX0 Reg3 bit9/TX1 Reg4 bit6="0" means the TX power reduce 7dB */
- /* R3 */
- if ((TxPwer >= -7)
- && (TxPwer < 0)) {
- TxPwer = (7 + TxPwer);
- TxPwer =
- (TxPwer >
- 0xF) ? (0xF)
- : (TxPwer);
- R3 |= (TxPwer << 10);
- DBGPRINT(RT_DEBUG_ERROR,
- ("AsicSwitchChannel: TxPwer=%d \n",
- TxPwer));
- } else {
- TxPwer =
- (TxPwer >
- 0xF) ? (0xF)
- : (TxPwer);
- R3 |=
- (TxPwer << 10) | (1
- <<
- 9);
- }
-
- /* R4 */
- if ((TxPwer2 >= -7)
- && (TxPwer2 < 0)) {
- TxPwer2 = (7 + TxPwer2);
- TxPwer2 =
- (TxPwer2 >
- 0xF) ? (0xF)
- : (TxPwer2);
- R4 |= (TxPwer2 << 7);
- DBGPRINT(RT_DEBUG_ERROR,
- ("AsicSwitchChannel: TxPwer2=%d \n",
- TxPwer2));
- } else {
- TxPwer2 =
- (TxPwer2 >
- 0xF) ? (0xF)
- : (TxPwer2);
- R4 |=
- (TxPwer2 << 7) | (1
- <<
- 6);
- }
- } else {
- R3 = (RFRegTable[index].R3 & 0xffffc1ff) | (TxPwer << 9); /* set TX power0 */
- R4 = (RFRegTable[index].R4 & (~0x001f87c0)) | (pAd->RfFreqOffset << 15) | (TxPwer2 << 6); /* Set freq Offset & TxPwr1 */
- }
-
- /* Based on BBP current mode before changing RF channel. */
- if (!bScan
- && (pAd->CommonCfg.BBPCurrentBW ==
- BW_40)) {
- R4 |= 0x200000;
- }
- /* Update variables */
- pAd->LatchRfRegs.Channel = Channel;
- pAd->LatchRfRegs.R1 =
- RFRegTable[index].R1;
- pAd->LatchRfRegs.R2 = R2;
- pAd->LatchRfRegs.R3 = R3;
- pAd->LatchRfRegs.R4 = R4;
-
- /* Set RF value 1's set R3[bit2] = [0] */
- RTMP_RF_IO_WRITE32(pAd,
- pAd->LatchRfRegs.R1);
- RTMP_RF_IO_WRITE32(pAd,
- pAd->LatchRfRegs.R2);
- RTMP_RF_IO_WRITE32(pAd,
- (pAd->LatchRfRegs.
- R3 & (~0x04)));
- RTMP_RF_IO_WRITE32(pAd,
- pAd->LatchRfRegs.R4);
-
- RTMPusecDelay(200);
-
- /* Set RF value 2's set R3[bit2] = [1] */
- RTMP_RF_IO_WRITE32(pAd,
- pAd->LatchRfRegs.R1);
- RTMP_RF_IO_WRITE32(pAd,
- pAd->LatchRfRegs.R2);
- RTMP_RF_IO_WRITE32(pAd,
- (pAd->LatchRfRegs.
- R3 | 0x04));
- RTMP_RF_IO_WRITE32(pAd,
- pAd->LatchRfRegs.R4);
-
- RTMPusecDelay(200);
-
- /* Set RF value 3's set R3[bit2] = [0] */
- RTMP_RF_IO_WRITE32(pAd,
- pAd->LatchRfRegs.R1);
- RTMP_RF_IO_WRITE32(pAd,
- pAd->LatchRfRegs.R2);
- RTMP_RF_IO_WRITE32(pAd,
- (pAd->LatchRfRegs.
- R3 & (~0x04)));
- RTMP_RF_IO_WRITE32(pAd,
- pAd->LatchRfRegs.R4);
-
- break;
- }
- }
- break;
-
- default:
- break;
- }
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("SwitchChannel#%d(RF=%d, Pwr0=%lu, Pwr1=%lu, %dT) to , R1=0x%08lx, R2=0x%08lx, R3=0x%08lx, R4=0x%08lx\n",
- Channel, pAd->RfIcType, (R3 & 0x00003e00) >> 9,
- (R4 & 0x000007c0) >> 6, pAd->Antenna.field.TxPath,
- pAd->LatchRfRegs.R1, pAd->LatchRfRegs.R2,
- pAd->LatchRfRegs.R3, pAd->LatchRfRegs.R4));
- }
-
- /* Change BBP setting during siwtch from a->g, g->a */
- if (Channel <= 14) {
- unsigned long TxPinCfg = 0x00050F0A; /*Gary 2007/08/09 0x050A0A */
-
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62,
- (0x37 - GET_LNA_GAIN(pAd)));
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63,
- (0x37 - GET_LNA_GAIN(pAd)));
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64,
- (0x37 - GET_LNA_GAIN(pAd)));
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0); /*(0x44 - GET_LNA_GAIN(pAd))); // According the Rory's suggestion to solve the middle range issue. */
- /*RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0x62); */
-
- /* Rx High power VGA offset for LNA select */
- if (pAd->NicConfig2.field.ExternalLNAForG) {
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0x62);
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x46);
- } else {
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0x84);
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x50);
- }
-
- /* 5G band selection PIN, bit1 and bit2 are complement */
- RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value);
- Value &= (~0x6);
- Value |= (0x04);
- RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value);
-
- /* Turn off unused PA or LNA when only 1T or 1R */
- if (pAd->Antenna.field.TxPath == 1) {
- TxPinCfg &= 0xFFFFFFF3;
- }
- if (pAd->Antenna.field.RxPath == 1) {
- TxPinCfg &= 0xFFFFF3FF;
- }
-
- RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg);
-
-#if defined(RT3090) || defined(RT3390)
- /* PCIe PHY Transmit attenuation adjustment */
- if (IS_RT3090A(pAd) || IS_RT3390(pAd)) {
- TX_ATTENUATION_CTRL_STRUC TxAttenuationCtrl = {
- .word = 0};
-
- RTMP_IO_READ32(pAd, PCIE_PHY_TX_ATTENUATION_CTRL,
- &TxAttenuationCtrl.word);
-
- if (Channel == 14) /* Channel #14 */
- {
- TxAttenuationCtrl.field.PCIE_PHY_TX_ATTEN_EN = 1; /* Enable PCIe PHY Tx attenuation */
- TxAttenuationCtrl.field.PCIE_PHY_TX_ATTEN_VALUE = 4; /* 9/16 full drive level */
- } else /* Channel #1~#13 */
- {
- TxAttenuationCtrl.field.PCIE_PHY_TX_ATTEN_EN = 0; /* Disable PCIe PHY Tx attenuation */
- TxAttenuationCtrl.field.PCIE_PHY_TX_ATTEN_VALUE = 0; /* n/a */
- }
-
- RTMP_IO_WRITE32(pAd, PCIE_PHY_TX_ATTENUATION_CTRL,
- TxAttenuationCtrl.word);
- }
-#endif
- } else {
- unsigned long TxPinCfg = 0x00050F05; /*Gary 2007/8/9 0x050505 */
-
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62,
- (0x37 - GET_LNA_GAIN(pAd)));
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63,
- (0x37 - GET_LNA_GAIN(pAd)));
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64,
- (0x37 - GET_LNA_GAIN(pAd)));
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0); /*(0x44 - GET_LNA_GAIN(pAd))); // According the Rory's suggestion to solve the middle range issue. */
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0xF2);
-
- /* Rx High power VGA offset for LNA select */
- if (pAd->NicConfig2.field.ExternalLNAForA) {
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x46);
- } else {
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x50);
- }
-
- /* 5G band selection PIN, bit1 and bit2 are complement */
- RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value);
- Value &= (~0x6);
- Value |= (0x02);
- RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value);
-
- /* Turn off unused PA or LNA when only 1T or 1R */
- if (pAd->Antenna.field.TxPath == 1) {
- TxPinCfg &= 0xFFFFFFF3;
- }
- if (pAd->Antenna.field.RxPath == 1) {
- TxPinCfg &= 0xFFFFF3FF;
- }
-
- RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg);
-
- }
-
- /* R66 should be set according to Channel and use 20MHz when scanning */
- /*RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, (0x2E + GET_LNA_GAIN(pAd))); */
- if (bScan)
- RTMPSetAGCInitValue(pAd, BW_20);
- else
- RTMPSetAGCInitValue(pAd, pAd->CommonCfg.BBPCurrentBW);
-
- /* */
- /* On 11A, We should delay and wait RF/BBP to be stable */
- /* and the appropriate time should be 1000 micro seconds */
- /* 2005/06/05 - On 11G, We also need this delay time. Otherwise it's difficult to pass the WHQL. */
- /* */
- RTMPusecDelay(1000);
-}
-
-void AsicResetBBPAgent(struct rt_rtmp_adapter *pAd)
-{
- BBP_CSR_CFG_STRUC BbpCsr;
- DBGPRINT(RT_DEBUG_ERROR, ("Reset BBP Agent busy bit!\n"));
- /* Still need to find why BBP agent keeps busy, but in fact, hardware still function ok. Now clear busy first. */
- RTMP_IO_READ32(pAd, H2M_BBP_AGENT, &BbpCsr.word);
- BbpCsr.field.Busy = 0;
- RTMP_IO_WRITE32(pAd, H2M_BBP_AGENT, BbpCsr.word);
-}
-
-/*
- ==========================================================================
- Description:
- This function is required for 2421 only, and should not be used during
- site survey. It's only required after NIC decided to stay at a channel
- for a longer period.
- When this function is called, it's always after AsicSwitchChannel().
-
- IRQL = PASSIVE_LEVEL
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
- */
-void AsicLockChannel(struct rt_rtmp_adapter *pAd, u8 Channel)
-{
-}
-
-void AsicRfTuningExec(void *SystemSpecific1,
- void *FunctionContext,
- void *SystemSpecific2, void *SystemSpecific3)
-{
-}
-
-/*
- ==========================================================================
- Description:
- Gives CCK TX rate 2 more dB TX power.
- This routine works only in LINK UP in INFRASTRUCTURE mode.
-
- calculate desired Tx power in RF R3.Tx0~5, should consider -
- 0. if current radio is a noisy environment (pAd->DrsCounters.fNoisyEnvironment)
- 1. TxPowerPercentage
- 2. auto calibration based on TSSI feedback
- 3. extra 2 db for CCK
- 4. -10 db upon very-short distance (AvgRSSI >= -40db) to AP
-
- NOTE: Since this routine requires the value of (pAd->DrsCounters.fNoisyEnvironment),
- it should be called AFTER MlmeDynamicTxRatSwitching()
- ==========================================================================
- */
-void AsicAdjustTxPower(struct rt_rtmp_adapter *pAd)
-{
- int i, j;
- char DeltaPwr = 0;
- BOOLEAN bAutoTxAgc = FALSE;
- u8 TssiRef, *pTssiMinusBoundary, *pTssiPlusBoundary, TxAgcStep;
- u8 BbpR1 = 0, BbpR49 = 0, idx;
- char *pTxAgcCompensate;
- unsigned long TxPwr[5];
- char Value;
- char Rssi = -127;
-
- if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_DOZE) ||
-#ifdef RTMP_MAC_PCI
- (pAd->bPCIclkOff == TRUE) ||
-#endif /* RTMP_MAC_PCI // */
- RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_IDLE_RADIO_OFF) ||
- RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_BSS_SCAN_IN_PROGRESS))
- return;
-
- Rssi = RTMPMaxRssi(pAd,
- pAd->StaCfg.RssiSample.AvgRssi0,
- pAd->StaCfg.RssiSample.AvgRssi1,
- pAd->StaCfg.RssiSample.AvgRssi2);
-
- if (pAd->CommonCfg.BBPCurrentBW == BW_40) {
- if (pAd->CommonCfg.CentralChannel > 14) {
- TxPwr[0] = pAd->Tx40MPwrCfgABand[0];
- TxPwr[1] = pAd->Tx40MPwrCfgABand[1];
- TxPwr[2] = pAd->Tx40MPwrCfgABand[2];
- TxPwr[3] = pAd->Tx40MPwrCfgABand[3];
- TxPwr[4] = pAd->Tx40MPwrCfgABand[4];
- } else {
- TxPwr[0] = pAd->Tx40MPwrCfgGBand[0];
- TxPwr[1] = pAd->Tx40MPwrCfgGBand[1];
- TxPwr[2] = pAd->Tx40MPwrCfgGBand[2];
- TxPwr[3] = pAd->Tx40MPwrCfgGBand[3];
- TxPwr[4] = pAd->Tx40MPwrCfgGBand[4];
- }
- } else {
- if (pAd->CommonCfg.Channel > 14) {
- TxPwr[0] = pAd->Tx20MPwrCfgABand[0];
- TxPwr[1] = pAd->Tx20MPwrCfgABand[1];
- TxPwr[2] = pAd->Tx20MPwrCfgABand[2];
- TxPwr[3] = pAd->Tx20MPwrCfgABand[3];
- TxPwr[4] = pAd->Tx20MPwrCfgABand[4];
- } else {
- TxPwr[0] = pAd->Tx20MPwrCfgGBand[0];
- TxPwr[1] = pAd->Tx20MPwrCfgGBand[1];
- TxPwr[2] = pAd->Tx20MPwrCfgGBand[2];
- TxPwr[3] = pAd->Tx20MPwrCfgGBand[3];
- TxPwr[4] = pAd->Tx20MPwrCfgGBand[4];
- }
- }
-
- /* TX power compensation for temperature variation based on TSSI. try every 4 second */
- if (pAd->Mlme.OneSecPeriodicRound % 4 == 0) {
- if (pAd->CommonCfg.Channel <= 14) {
- /* bg channel */
- bAutoTxAgc = pAd->bAutoTxAgcG;
- TssiRef = pAd->TssiRefG;
- pTssiMinusBoundary = &pAd->TssiMinusBoundaryG[0];
- pTssiPlusBoundary = &pAd->TssiPlusBoundaryG[0];
- TxAgcStep = pAd->TxAgcStepG;
- pTxAgcCompensate = &pAd->TxAgcCompensateG;
- } else {
- /* a channel */
- bAutoTxAgc = pAd->bAutoTxAgcA;
- TssiRef = pAd->TssiRefA;
- pTssiMinusBoundary = &pAd->TssiMinusBoundaryA[0];
- pTssiPlusBoundary = &pAd->TssiPlusBoundaryA[0];
- TxAgcStep = pAd->TxAgcStepA;
- pTxAgcCompensate = &pAd->TxAgcCompensateA;
- }
-
- if (bAutoTxAgc) {
- /* BbpR1 is unsigned char */
- RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R49, &BbpR49);
-
- /* (p) TssiPlusBoundaryG[0] = 0 = (m) TssiMinusBoundaryG[0] */
- /* compensate: +4 +3 +2 +1 0 -1 -2 -3 -4 * steps */
- /* step value is defined in pAd->TxAgcStepG for tx power value */
-
- /* [4]+1+[4] p4 p3 p2 p1 o1 m1 m2 m3 m4 */
- /* ex: 0x00 0x15 0x25 0x45 0x88 0xA0 0xB5 0xD0 0xF0
- above value are examined in mass factory production */
- /* [4] [3] [2] [1] [0] [1] [2] [3] [4] */
-
- /* plus (+) is 0x00 ~ 0x45, minus (-) is 0xa0 ~ 0xf0 */
- /* if value is between p1 ~ o1 or o1 ~ s1, no need to adjust tx power */
- /* if value is 0xa5, tx power will be -= TxAgcStep*(2-1) */
-
- if (BbpR49 > pTssiMinusBoundary[1]) {
- /* Reading is larger than the reference value */
- /* check for how large we need to decrease the Tx power */
- for (idx = 1; idx < 5; idx++) {
- if (BbpR49 <= pTssiMinusBoundary[idx]) /* Found the range */
- break;
- }
- /* The index is the step we should decrease, idx = 0 means there is nothing to compensate */
-/* if (R3 > (unsigned long)(TxAgcStep * (idx-1))) */
- *pTxAgcCompensate = -(TxAgcStep * (idx - 1));
-/* else */
-/* *pTxAgcCompensate = -((u8)R3); */
-
- DeltaPwr += (*pTxAgcCompensate);
- DBGPRINT(RT_DEBUG_TRACE,
- ("-- Tx Power, BBP R1=%x, TssiRef=%x, TxAgcStep=%x, step = -%d\n",
- BbpR49, TssiRef, TxAgcStep, idx - 1));
- } else if (BbpR49 < pTssiPlusBoundary[1]) {
- /* Reading is smaller than the reference value */
- /* check for how large we need to increase the Tx power */
- for (idx = 1; idx < 5; idx++) {
- if (BbpR49 >= pTssiPlusBoundary[idx]) /* Found the range */
- break;
- }
- /* The index is the step we should increase, idx = 0 means there is nothing to compensate */
- *pTxAgcCompensate = TxAgcStep * (idx - 1);
- DeltaPwr += (*pTxAgcCompensate);
- DBGPRINT(RT_DEBUG_TRACE,
- ("++ Tx Power, BBP R1=%x, TssiRef=%x, TxAgcStep=%x, step = +%d\n",
- BbpR49, TssiRef, TxAgcStep, idx - 1));
- } else {
- *pTxAgcCompensate = 0;
- DBGPRINT(RT_DEBUG_TRACE,
- (" Tx Power, BBP R49=%x, TssiRef=%x, TxAgcStep=%x, step = +%d\n",
- BbpR49, TssiRef, TxAgcStep, 0));
- }
- }
- } else {
- if (pAd->CommonCfg.Channel <= 14) {
- bAutoTxAgc = pAd->bAutoTxAgcG;
- pTxAgcCompensate = &pAd->TxAgcCompensateG;
- } else {
- bAutoTxAgc = pAd->bAutoTxAgcA;
- pTxAgcCompensate = &pAd->TxAgcCompensateA;
- }
-
- if (bAutoTxAgc)
- DeltaPwr += (*pTxAgcCompensate);
- }
-
- RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R1, &BbpR1);
- BbpR1 &= 0xFC;
-
- /* calculate delta power based on the percentage specified from UI */
- /* E2PROM setting is calibrated for maximum TX power (i.e. 100%) */
- /* We lower TX power here according to the percentage specified from UI */
- if (pAd->CommonCfg.TxPowerPercentage == 0xffffffff) /* AUTO TX POWER control */
- {
- {
- /* to patch high power issue with some APs, like Belkin N1. */
- if (Rssi > -35) {
- BbpR1 |= 0x02; /* DeltaPwr -= 12; */
- } else if (Rssi > -40) {
- BbpR1 |= 0x01; /* DeltaPwr -= 6; */
- } else;
- }
- } else if (pAd->CommonCfg.TxPowerPercentage > 90) /* 91 ~ 100% & AUTO, treat as 100% in terms of mW */
- ;
- else if (pAd->CommonCfg.TxPowerPercentage > 60) /* 61 ~ 90%, treat as 75% in terms of mW // DeltaPwr -= 1; */
- {
- DeltaPwr -= 1;
- } else if (pAd->CommonCfg.TxPowerPercentage > 30) /* 31 ~ 60%, treat as 50% in terms of mW // DeltaPwr -= 3; */
- {
- DeltaPwr -= 3;
- } else if (pAd->CommonCfg.TxPowerPercentage > 15) /* 16 ~ 30%, treat as 25% in terms of mW // DeltaPwr -= 6; */
- {
- BbpR1 |= 0x01;
- } else if (pAd->CommonCfg.TxPowerPercentage > 9) /* 10 ~ 15%, treat as 12.5% in terms of mW // DeltaPwr -= 9; */
- {
- BbpR1 |= 0x01;
- DeltaPwr -= 3;
- } else /* 0 ~ 9 %, treat as MIN(~3%) in terms of mW // DeltaPwr -= 12; */
- {
- BbpR1 |= 0x02;
- }
-
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R1, BbpR1);
-
- /* reset different new tx power for different TX rate */
- for (i = 0; i < 5; i++) {
- if (TxPwr[i] != 0xffffffff) {
- for (j = 0; j < 8; j++) {
- Value = (char)((TxPwr[i] >> j * 4) & 0x0F); /* 0 ~ 15 */
-
- if ((Value + DeltaPwr) < 0) {
- Value = 0; /* min */
- } else if ((Value + DeltaPwr) > 0xF) {
- Value = 0xF; /* max */
- } else {
- Value += DeltaPwr; /* temperature compensation */
- }
-
- /* fill new value to CSR offset */
- TxPwr[i] =
- (TxPwr[i] & ~(0x0000000F << j * 4)) | (Value
- << j
- * 4);
- }
-
- /* write tx power value to CSR */
- /* TX_PWR_CFG_0 (8 tx rate) for TX power for OFDM 12M/18M
- TX power for OFDM 6M/9M
- TX power for CCK5.5M/11M
- TX power for CCK1M/2M */
- /* TX_PWR_CFG_1 ~ TX_PWR_CFG_4 */
- RTMP_IO_WRITE32(pAd, TX_PWR_CFG_0 + i * 4, TxPwr[i]);
- }
- }
-
-}
-
-/*
- ==========================================================================
- Description:
- put PHY to sleep here, and set next wakeup timer. PHY doesn't not wakeup
- automatically. Instead, MCU will issue a TwakeUpInterrupt to host after
- the wakeup timer timeout. Driver has to issue a separate command to wake
- PHY up.
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
- */
-void AsicSleepThenAutoWakeup(struct rt_rtmp_adapter *pAd,
- u16 TbttNumToNextWakeUp)
-{
- RTMP_STA_SLEEP_THEN_AUTO_WAKEUP(pAd, TbttNumToNextWakeUp);
-}
-
-/*
- ==========================================================================
- Description:
- AsicForceWakeup() is used whenever manual wakeup is required
- AsicForceSleep() should only be used when not in INFRA BSS. When
- in INFRA BSS, we should use AsicSleepThenAutoWakeup() instead.
- ==========================================================================
- */
-void AsicForceSleep(struct rt_rtmp_adapter *pAd)
-{
-
-}
-
-/*
- ==========================================================================
- Description:
- AsicForceWakeup() is used whenever Twakeup timer (set via AsicSleepThenAutoWakeup)
- expired.
-
- IRQL = PASSIVE_LEVEL
- IRQL = DISPATCH_LEVEL
- ==========================================================================
- */
-void AsicForceWakeup(struct rt_rtmp_adapter *pAd, IN BOOLEAN bFromTx)
-{
- DBGPRINT(RT_DEBUG_INFO, ("--> AsicForceWakeup \n"));
- RTMP_STA_FORCE_WAKEUP(pAd, bFromTx);
-}
-
-/*
- ==========================================================================
- Description:
- Set My BSSID
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
- */
-void AsicSetBssid(struct rt_rtmp_adapter *pAd, u8 *pBssid)
-{
- unsigned long Addr4;
- DBGPRINT(RT_DEBUG_TRACE,
- ("==============> AsicSetBssid %x:%x:%x:%x:%x:%x\n", pBssid[0],
- pBssid[1], pBssid[2], pBssid[3], pBssid[4], pBssid[5]));
-
- Addr4 = (unsigned long)(pBssid[0]) |
- (unsigned long)(pBssid[1] << 8) |
- (unsigned long)(pBssid[2] << 16) | (unsigned long)(pBssid[3] << 24);
- RTMP_IO_WRITE32(pAd, MAC_BSSID_DW0, Addr4);
-
- Addr4 = 0;
- /* always one BSSID in STA mode */
- Addr4 = (unsigned long)(pBssid[4]) | (unsigned long)(pBssid[5] << 8);
-
- RTMP_IO_WRITE32(pAd, MAC_BSSID_DW1, Addr4);
-}
-
-void AsicSetMcastWC(struct rt_rtmp_adapter *pAd)
-{
- struct rt_mac_table_entry *pEntry = &pAd->MacTab.Content[MCAST_WCID];
- u16 offset;
-
- pEntry->Sst = SST_ASSOC;
- pEntry->Aid = MCAST_WCID; /* Softap supports 1 BSSID and use WCID=0 as multicast Wcid index */
- pEntry->PsMode = PWR_ACTIVE;
- pEntry->CurrTxRate = pAd->CommonCfg.MlmeRate;
- offset = MAC_WCID_BASE + BSS0Mcast_WCID * HW_WCID_ENTRY_SIZE;
-}
-
-/*
- ==========================================================================
- Description:
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
- */
-void AsicDelWcidTab(struct rt_rtmp_adapter *pAd, u8 Wcid)
-{
- unsigned long Addr0 = 0x0, Addr1 = 0x0;
- unsigned long offset;
-
- DBGPRINT(RT_DEBUG_TRACE, ("AsicDelWcidTab==>Wcid = 0x%x\n", Wcid));
- offset = MAC_WCID_BASE + Wcid * HW_WCID_ENTRY_SIZE;
- RTMP_IO_WRITE32(pAd, offset, Addr0);
- offset += 4;
- RTMP_IO_WRITE32(pAd, offset, Addr1);
-}
-
-/*
- ==========================================================================
- Description:
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
- */
-void AsicEnableRDG(struct rt_rtmp_adapter *pAd)
-{
- TX_LINK_CFG_STRUC TxLinkCfg;
- u32 Data = 0;
-
- RTMP_IO_READ32(pAd, TX_LINK_CFG, &TxLinkCfg.word);
- TxLinkCfg.field.TxRDGEn = 1;
- RTMP_IO_WRITE32(pAd, TX_LINK_CFG, TxLinkCfg.word);
-
- RTMP_IO_READ32(pAd, EDCA_AC0_CFG, &Data);
- Data &= 0xFFFFFF00;
- Data |= 0x80;
- RTMP_IO_WRITE32(pAd, EDCA_AC0_CFG, Data);
-
- /*OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_AGGREGATION_INUSED); */
-}
-
-/*
- ==========================================================================
- Description:
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
- */
-void AsicDisableRDG(struct rt_rtmp_adapter *pAd)
-{
- TX_LINK_CFG_STRUC TxLinkCfg;
- u32 Data = 0;
-
- RTMP_IO_READ32(pAd, TX_LINK_CFG, &TxLinkCfg.word);
- TxLinkCfg.field.TxRDGEn = 0;
- RTMP_IO_WRITE32(pAd, TX_LINK_CFG, TxLinkCfg.word);
-
- RTMP_IO_READ32(pAd, EDCA_AC0_CFG, &Data);
-
- Data &= 0xFFFFFF00;
- /*Data |= 0x20; */
-#ifndef WIFI_TEST
- /*if ( pAd->CommonCfg.bEnableTxBurst ) */
- /* Data |= 0x60; // for performance issue not set the TXOP to 0 */
-#endif
- if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_DYNAMIC_BE_TXOP_ACTIVE)
- && (pAd->MacTab.fAnyStationMIMOPSDynamic == FALSE)
- ) {
- /* For CWC test, change txop from 0x30 to 0x20 in TxBurst mode */
- if (pAd->CommonCfg.bEnableTxBurst)
- Data |= 0x20;
- }
- RTMP_IO_WRITE32(pAd, EDCA_AC0_CFG, Data);
-}
-
-/*
- ==========================================================================
- Description:
-
- IRQL = PASSIVE_LEVEL
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
- */
-void AsicDisableSync(struct rt_rtmp_adapter *pAd)
-{
- BCN_TIME_CFG_STRUC csr;
-
- DBGPRINT(RT_DEBUG_TRACE, ("--->Disable TSF synchronization\n"));
-
- /* 2003-12-20 disable TSF and TBTT while NIC in power-saving have side effect */
- /* that NIC will never wakes up because TSF stops and no more */
- /* TBTT interrupts */
- pAd->TbttTickCount = 0;
- RTMP_IO_READ32(pAd, BCN_TIME_CFG, &csr.word);
- csr.field.bBeaconGen = 0;
- csr.field.bTBTTEnable = 0;
- csr.field.TsfSyncMode = 0;
- csr.field.bTsfTicking = 0;
- RTMP_IO_WRITE32(pAd, BCN_TIME_CFG, csr.word);
-
-}
-
-/*
- ==========================================================================
- Description:
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
- */
-void AsicEnableBssSync(struct rt_rtmp_adapter *pAd)
-{
- BCN_TIME_CFG_STRUC csr;
-
- DBGPRINT(RT_DEBUG_TRACE, ("--->AsicEnableBssSync(INFRA mode)\n"));
-
- RTMP_IO_READ32(pAd, BCN_TIME_CFG, &csr.word);
-/* RTMP_IO_WRITE32(pAd, BCN_TIME_CFG, 0x00000000); */
- {
- csr.field.BeaconInterval = pAd->CommonCfg.BeaconPeriod << 4; /* ASIC register in units of 1/16 TU */
- csr.field.bTsfTicking = 1;
- csr.field.TsfSyncMode = 1; /* sync TSF in INFRASTRUCTURE mode */
- csr.field.bBeaconGen = 0; /* do NOT generate BEACON */
- csr.field.bTBTTEnable = 1;
- }
- RTMP_IO_WRITE32(pAd, BCN_TIME_CFG, csr.word);
-}
-
-/*
- ==========================================================================
- Description:
- Note:
- BEACON frame in shared memory should be built ok before this routine
- can be called. Otherwise, a garbage frame maybe transmitted out every
- Beacon period.
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
- */
-void AsicEnableIbssSync(struct rt_rtmp_adapter *pAd)
-{
- BCN_TIME_CFG_STRUC csr9;
- u8 *ptr;
- u32 i;
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("--->AsicEnableIbssSync(ADHOC mode. MPDUtotalByteCount = %d)\n",
- pAd->BeaconTxWI.MPDUtotalByteCount));
-
- RTMP_IO_READ32(pAd, BCN_TIME_CFG, &csr9.word);
- csr9.field.bBeaconGen = 0;
- csr9.field.bTBTTEnable = 0;
- csr9.field.bTsfTicking = 0;
- RTMP_IO_WRITE32(pAd, BCN_TIME_CFG, csr9.word);
-
-#ifdef RTMP_MAC_PCI
- /* move BEACON TXD and frame content to on-chip memory */
- ptr = (u8 *)& pAd->BeaconTxWI;
- for (i = 0; i < TXWI_SIZE; i += 4) /* 16-byte TXWI field */
- {
- u32 longptr =
- *ptr + (*(ptr + 1) << 8) + (*(ptr + 2) << 16) +
- (*(ptr + 3) << 24);
- RTMP_IO_WRITE32(pAd, HW_BEACON_BASE0 + i, longptr);
- ptr += 4;
- }
-
- /* start right after the 16-byte TXWI field */
- ptr = pAd->BeaconBuf;
- for (i = 0; i < pAd->BeaconTxWI.MPDUtotalByteCount; i += 4) {
- u32 longptr =
- *ptr + (*(ptr + 1) << 8) + (*(ptr + 2) << 16) +
- (*(ptr + 3) << 24);
- RTMP_IO_WRITE32(pAd, HW_BEACON_BASE0 + TXWI_SIZE + i, longptr);
- ptr += 4;
- }
-#endif /* RTMP_MAC_PCI // */
-#ifdef RTMP_MAC_USB
- /* move BEACON TXD and frame content to on-chip memory */
- ptr = (u8 *)& pAd->BeaconTxWI;
- for (i = 0; i < TXWI_SIZE; i += 2) /* 16-byte TXWI field */
- {
- /*u32 longptr = *ptr + (*(ptr+1)<<8) + (*(ptr+2)<<16) + (*(ptr+3)<<24); */
- /*RTMP_IO_WRITE32(pAd, HW_BEACON_BASE0 + i, longptr); */
- RTUSBMultiWrite(pAd, HW_BEACON_BASE0 + i, ptr, 2);
- ptr += 2;
- }
-
- /* start right after the 16-byte TXWI field */
- ptr = pAd->BeaconBuf;
- for (i = 0; i < pAd->BeaconTxWI.MPDUtotalByteCount; i += 2) {
- /*u32 longptr = *ptr + (*(ptr+1)<<8) + (*(ptr+2)<<16) + (*(ptr+3)<<24); */
- /*RTMP_IO_WRITE32(pAd, HW_BEACON_BASE0 + TXWI_SIZE + i, longptr); */
- RTUSBMultiWrite(pAd, HW_BEACON_BASE0 + TXWI_SIZE + i, ptr, 2);
- ptr += 2;
- }
-#endif /* RTMP_MAC_USB // */
-
- /* */
- /* For Wi-Fi faily generated beacons between participating stations. */
- /* Set TBTT phase adaptive adjustment step to 8us (default 16us) */
- /* don't change settings 2006-5- by Jerry */
- /*RTMP_IO_WRITE32(pAd, TBTT_SYNC_CFG, 0x00001010); */
-
- /* start sending BEACON */
- csr9.field.BeaconInterval = pAd->CommonCfg.BeaconPeriod << 4; /* ASIC register in units of 1/16 TU */
- csr9.field.bTsfTicking = 1;
- csr9.field.TsfSyncMode = 2; /* sync TSF in IBSS mode */
- csr9.field.bTBTTEnable = 1;
- csr9.field.bBeaconGen = 1;
- RTMP_IO_WRITE32(pAd, BCN_TIME_CFG, csr9.word);
-}
-
-/*
- ==========================================================================
- Description:
-
- IRQL = PASSIVE_LEVEL
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
- */
-void AsicSetEdcaParm(struct rt_rtmp_adapter *pAd, struct rt_edca_parm *pEdcaParm)
-{
- EDCA_AC_CFG_STRUC Ac0Cfg, Ac1Cfg, Ac2Cfg, Ac3Cfg;
- AC_TXOP_CSR0_STRUC csr0;
- AC_TXOP_CSR1_STRUC csr1;
- AIFSN_CSR_STRUC AifsnCsr;
- CWMIN_CSR_STRUC CwminCsr;
- CWMAX_CSR_STRUC CwmaxCsr;
- int i;
-
- Ac0Cfg.word = 0;
- Ac1Cfg.word = 0;
- Ac2Cfg.word = 0;
- Ac3Cfg.word = 0;
- if ((pEdcaParm == NULL) || (pEdcaParm->bValid == FALSE)) {
- DBGPRINT(RT_DEBUG_TRACE, ("AsicSetEdcaParm\n"));
- OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_WMM_INUSED);
- for (i = 0; i < MAX_LEN_OF_MAC_TABLE; i++) {
- if (pAd->MacTab.Content[i].ValidAsCLI
- || pAd->MacTab.Content[i].ValidAsApCli)
- CLIENT_STATUS_CLEAR_FLAG(&pAd->MacTab.
- Content[i],
- fCLIENT_STATUS_WMM_CAPABLE);
- }
-
- /*======================================================== */
- /* MAC Register has a copy . */
- /*======================================================== */
-/*#ifndef WIFI_TEST */
- if (pAd->CommonCfg.bEnableTxBurst) {
- /* For CWC test, change txop from 0x30 to 0x20 in TxBurst mode */
- Ac0Cfg.field.AcTxop = 0x20; /* Suggest by John for TxBurst in HT Mode */
- } else
- Ac0Cfg.field.AcTxop = 0; /* QID_AC_BE */
-/*#else */
-/* Ac0Cfg.field.AcTxop = 0; // QID_AC_BE */
-/*#endif */
- Ac0Cfg.field.Cwmin = CW_MIN_IN_BITS;
- Ac0Cfg.field.Cwmax = CW_MAX_IN_BITS;
- Ac0Cfg.field.Aifsn = 2;
- RTMP_IO_WRITE32(pAd, EDCA_AC0_CFG, Ac0Cfg.word);
-
- Ac1Cfg.field.AcTxop = 0; /* QID_AC_BK */
- Ac1Cfg.field.Cwmin = CW_MIN_IN_BITS;
- Ac1Cfg.field.Cwmax = CW_MAX_IN_BITS;
- Ac1Cfg.field.Aifsn = 2;
- RTMP_IO_WRITE32(pAd, EDCA_AC1_CFG, Ac1Cfg.word);
-
- if (pAd->CommonCfg.PhyMode == PHY_11B) {
- Ac2Cfg.field.AcTxop = 192; /* AC_VI: 192*32us ~= 6ms */
- Ac3Cfg.field.AcTxop = 96; /* AC_VO: 96*32us ~= 3ms */
- } else {
- Ac2Cfg.field.AcTxop = 96; /* AC_VI: 96*32us ~= 3ms */
- Ac3Cfg.field.AcTxop = 48; /* AC_VO: 48*32us ~= 1.5ms */
- }
- Ac2Cfg.field.Cwmin = CW_MIN_IN_BITS;
- Ac2Cfg.field.Cwmax = CW_MAX_IN_BITS;
- Ac2Cfg.field.Aifsn = 2;
- RTMP_IO_WRITE32(pAd, EDCA_AC2_CFG, Ac2Cfg.word);
- Ac3Cfg.field.Cwmin = CW_MIN_IN_BITS;
- Ac3Cfg.field.Cwmax = CW_MAX_IN_BITS;
- Ac3Cfg.field.Aifsn = 2;
- RTMP_IO_WRITE32(pAd, EDCA_AC3_CFG, Ac3Cfg.word);
-
- /*======================================================== */
- /* DMA Register has a copy too. */
- /*======================================================== */
- csr0.field.Ac0Txop = 0; /* QID_AC_BE */
- csr0.field.Ac1Txop = 0; /* QID_AC_BK */
- RTMP_IO_WRITE32(pAd, WMM_TXOP0_CFG, csr0.word);
- if (pAd->CommonCfg.PhyMode == PHY_11B) {
- csr1.field.Ac2Txop = 192; /* AC_VI: 192*32us ~= 6ms */
- csr1.field.Ac3Txop = 96; /* AC_VO: 96*32us ~= 3ms */
- } else {
- csr1.field.Ac2Txop = 96; /* AC_VI: 96*32us ~= 3ms */
- csr1.field.Ac3Txop = 48; /* AC_VO: 48*32us ~= 1.5ms */
- }
- RTMP_IO_WRITE32(pAd, WMM_TXOP1_CFG, csr1.word);
-
- CwminCsr.word = 0;
- CwminCsr.field.Cwmin0 = CW_MIN_IN_BITS;
- CwminCsr.field.Cwmin1 = CW_MIN_IN_BITS;
- CwminCsr.field.Cwmin2 = CW_MIN_IN_BITS;
- CwminCsr.field.Cwmin3 = CW_MIN_IN_BITS;
- RTMP_IO_WRITE32(pAd, WMM_CWMIN_CFG, CwminCsr.word);
-
- CwmaxCsr.word = 0;
- CwmaxCsr.field.Cwmax0 = CW_MAX_IN_BITS;
- CwmaxCsr.field.Cwmax1 = CW_MAX_IN_BITS;
- CwmaxCsr.field.Cwmax2 = CW_MAX_IN_BITS;
- CwmaxCsr.field.Cwmax3 = CW_MAX_IN_BITS;
- RTMP_IO_WRITE32(pAd, WMM_CWMAX_CFG, CwmaxCsr.word);
-
- RTMP_IO_WRITE32(pAd, WMM_AIFSN_CFG, 0x00002222);
-
- NdisZeroMemory(&pAd->CommonCfg.APEdcaParm, sizeof(struct rt_edca_parm));
- } else {
- OPSTATUS_SET_FLAG(pAd, fOP_STATUS_WMM_INUSED);
- /*======================================================== */
- /* MAC Register has a copy. */
- /*======================================================== */
- /* */
- /* Modify Cwmin/Cwmax/Txop on queue[QID_AC_VI], Recommend by Jerry 2005/07/27 */
- /* To degrade our VIDO Queue's throughput for WiFi WMM S3T07 Issue. */
- /* */
- /*pEdcaParm->Txop[QID_AC_VI] = pEdcaParm->Txop[QID_AC_VI] * 7 / 10; // rt2860c need this */
-
- Ac0Cfg.field.AcTxop = pEdcaParm->Txop[QID_AC_BE];
- Ac0Cfg.field.Cwmin = pEdcaParm->Cwmin[QID_AC_BE];
- Ac0Cfg.field.Cwmax = pEdcaParm->Cwmax[QID_AC_BE];
- Ac0Cfg.field.Aifsn = pEdcaParm->Aifsn[QID_AC_BE]; /*+1; */
-
- Ac1Cfg.field.AcTxop = pEdcaParm->Txop[QID_AC_BK];
- Ac1Cfg.field.Cwmin = pEdcaParm->Cwmin[QID_AC_BK]; /*+2; */
- Ac1Cfg.field.Cwmax = pEdcaParm->Cwmax[QID_AC_BK];
- Ac1Cfg.field.Aifsn = pEdcaParm->Aifsn[QID_AC_BK]; /*+1; */
-
- Ac2Cfg.field.AcTxop = (pEdcaParm->Txop[QID_AC_VI] * 6) / 10;
- if (pAd->Antenna.field.TxPath == 1) {
- Ac2Cfg.field.Cwmin = pEdcaParm->Cwmin[QID_AC_VI] + 1;
- Ac2Cfg.field.Cwmax = pEdcaParm->Cwmax[QID_AC_VI] + 1;
- } else {
- Ac2Cfg.field.Cwmin = pEdcaParm->Cwmin[QID_AC_VI];
- Ac2Cfg.field.Cwmax = pEdcaParm->Cwmax[QID_AC_VI];
- }
- Ac2Cfg.field.Aifsn = pEdcaParm->Aifsn[QID_AC_VI] + 1;
-#ifdef RTMP_MAC_USB
- Ac2Cfg.field.Aifsn = pEdcaParm->Aifsn[QID_AC_VI] + 3;
-#endif /* RTMP_MAC_USB // */
-
- {
- /* Tuning for Wi-Fi WMM S06 */
- if (pAd->CommonCfg.bWiFiTest &&
- pEdcaParm->Aifsn[QID_AC_VI] == 10)
- Ac2Cfg.field.Aifsn -= 1;
-
- /* Tuning for TGn Wi-Fi 5.2.32 */
- /* STA TestBed changes in this item: conexant legacy sta ==> broadcom 11n sta */
- if (STA_TGN_WIFI_ON(pAd) &&
- pEdcaParm->Aifsn[QID_AC_VI] == 10) {
- Ac0Cfg.field.Aifsn = 3;
- Ac2Cfg.field.AcTxop = 5;
- }
-#ifdef RT30xx
- if (pAd->RfIcType == RFIC_3020
- || pAd->RfIcType == RFIC_2020) {
- /* Tuning for WiFi WMM S3-T07: connexant legacy sta ==> broadcom 11n sta. */
- Ac2Cfg.field.Aifsn = 5;
- }
-#endif /* RT30xx // */
- }
-
- Ac3Cfg.field.AcTxop = pEdcaParm->Txop[QID_AC_VO];
- Ac3Cfg.field.Cwmin = pEdcaParm->Cwmin[QID_AC_VO];
- Ac3Cfg.field.Cwmax = pEdcaParm->Cwmax[QID_AC_VO];
- Ac3Cfg.field.Aifsn = pEdcaParm->Aifsn[QID_AC_VO];
-
-/*#ifdef WIFI_TEST */
- if (pAd->CommonCfg.bWiFiTest) {
- if (Ac3Cfg.field.AcTxop == 102) {
- Ac0Cfg.field.AcTxop =
- pEdcaParm->Txop[QID_AC_BE] ? pEdcaParm->
- Txop[QID_AC_BE] : 10;
- Ac0Cfg.field.Aifsn = pEdcaParm->Aifsn[QID_AC_BE] - 1; /* AIFSN must >= 1 */
- Ac1Cfg.field.AcTxop =
- pEdcaParm->Txop[QID_AC_BK];
- Ac1Cfg.field.Aifsn =
- pEdcaParm->Aifsn[QID_AC_BK];
- Ac2Cfg.field.AcTxop =
- pEdcaParm->Txop[QID_AC_VI];
- } /* End of if */
- }
-/*#endif // WIFI_TEST // */
-
- RTMP_IO_WRITE32(pAd, EDCA_AC0_CFG, Ac0Cfg.word);
- RTMP_IO_WRITE32(pAd, EDCA_AC1_CFG, Ac1Cfg.word);
- RTMP_IO_WRITE32(pAd, EDCA_AC2_CFG, Ac2Cfg.word);
- RTMP_IO_WRITE32(pAd, EDCA_AC3_CFG, Ac3Cfg.word);
-
- /*======================================================== */
- /* DMA Register has a copy too. */
- /*======================================================== */
- csr0.field.Ac0Txop = Ac0Cfg.field.AcTxop;
- csr0.field.Ac1Txop = Ac1Cfg.field.AcTxop;
- RTMP_IO_WRITE32(pAd, WMM_TXOP0_CFG, csr0.word);
-
- csr1.field.Ac2Txop = Ac2Cfg.field.AcTxop;
- csr1.field.Ac3Txop = Ac3Cfg.field.AcTxop;
- RTMP_IO_WRITE32(pAd, WMM_TXOP1_CFG, csr1.word);
-
- CwminCsr.word = 0;
- CwminCsr.field.Cwmin0 = pEdcaParm->Cwmin[QID_AC_BE];
- CwminCsr.field.Cwmin1 = pEdcaParm->Cwmin[QID_AC_BK];
- CwminCsr.field.Cwmin2 = pEdcaParm->Cwmin[QID_AC_VI];
- CwminCsr.field.Cwmin3 = pEdcaParm->Cwmin[QID_AC_VO] - 1; /*for TGn wifi test */
- RTMP_IO_WRITE32(pAd, WMM_CWMIN_CFG, CwminCsr.word);
-
- CwmaxCsr.word = 0;
- CwmaxCsr.field.Cwmax0 = pEdcaParm->Cwmax[QID_AC_BE];
- CwmaxCsr.field.Cwmax1 = pEdcaParm->Cwmax[QID_AC_BK];
- CwmaxCsr.field.Cwmax2 = pEdcaParm->Cwmax[QID_AC_VI];
- CwmaxCsr.field.Cwmax3 = pEdcaParm->Cwmax[QID_AC_VO];
- RTMP_IO_WRITE32(pAd, WMM_CWMAX_CFG, CwmaxCsr.word);
-
- AifsnCsr.word = 0;
- AifsnCsr.field.Aifsn0 = Ac0Cfg.field.Aifsn; /*pEdcaParm->Aifsn[QID_AC_BE]; */
- AifsnCsr.field.Aifsn1 = Ac1Cfg.field.Aifsn; /*pEdcaParm->Aifsn[QID_AC_BK]; */
- AifsnCsr.field.Aifsn2 = Ac2Cfg.field.Aifsn; /*pEdcaParm->Aifsn[QID_AC_VI]; */
-
- {
- /* Tuning for Wi-Fi WMM S06 */
- if (pAd->CommonCfg.bWiFiTest &&
- pEdcaParm->Aifsn[QID_AC_VI] == 10)
- AifsnCsr.field.Aifsn2 = Ac2Cfg.field.Aifsn - 4;
-
- /* Tuning for TGn Wi-Fi 5.2.32 */
- /* STA TestBed changes in this item: connexant legacy sta ==> broadcom 11n sta */
- if (STA_TGN_WIFI_ON(pAd) &&
- pEdcaParm->Aifsn[QID_AC_VI] == 10) {
- AifsnCsr.field.Aifsn0 = 3;
- AifsnCsr.field.Aifsn2 = 7;
- }
-
- if (INFRA_ON(pAd))
- CLIENT_STATUS_SET_FLAG(&pAd->MacTab.
- Content[BSSID_WCID],
- fCLIENT_STATUS_WMM_CAPABLE);
- }
-
- {
- AifsnCsr.field.Aifsn3 = Ac3Cfg.field.Aifsn - 1; /*pEdcaParm->Aifsn[QID_AC_VO]; //for TGn wifi test */
-#ifdef RT30xx
- /* TODO: Shiang, this modification also suitable for RT3052/RT3050 ??? */
- if (pAd->RfIcType == RFIC_3020
- || pAd->RfIcType == RFIC_2020) {
- AifsnCsr.field.Aifsn2 = 0x2; /*pEdcaParm->Aifsn[QID_AC_VI]; //for WiFi WMM S4-T04. */
- }
-#endif /* RT30xx // */
- }
- RTMP_IO_WRITE32(pAd, WMM_AIFSN_CFG, AifsnCsr.word);
-
- NdisMoveMemory(&pAd->CommonCfg.APEdcaParm, pEdcaParm,
- sizeof(struct rt_edca_parm));
- if (!ADHOC_ON(pAd)) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("EDCA [#%d]: AIFSN CWmin CWmax TXOP(us) ACM\n",
- pEdcaParm->EdcaUpdateCount));
- DBGPRINT(RT_DEBUG_TRACE,
- (" AC_BE %2d %2d %2d %4d %d\n",
- pEdcaParm->Aifsn[0], pEdcaParm->Cwmin[0],
- pEdcaParm->Cwmax[0], pEdcaParm->Txop[0] << 5,
- pEdcaParm->bACM[0]));
- DBGPRINT(RT_DEBUG_TRACE,
- (" AC_BK %2d %2d %2d %4d %d\n",
- pEdcaParm->Aifsn[1], pEdcaParm->Cwmin[1],
- pEdcaParm->Cwmax[1], pEdcaParm->Txop[1] << 5,
- pEdcaParm->bACM[1]));
- DBGPRINT(RT_DEBUG_TRACE,
- (" AC_VI %2d %2d %2d %4d %d\n",
- pEdcaParm->Aifsn[2], pEdcaParm->Cwmin[2],
- pEdcaParm->Cwmax[2], pEdcaParm->Txop[2] << 5,
- pEdcaParm->bACM[2]));
- DBGPRINT(RT_DEBUG_TRACE,
- (" AC_VO %2d %2d %2d %4d %d\n",
- pEdcaParm->Aifsn[3], pEdcaParm->Cwmin[3],
- pEdcaParm->Cwmax[3], pEdcaParm->Txop[3] << 5,
- pEdcaParm->bACM[3]));
- }
- }
-
-}
-
-/*
- ==========================================================================
- Description:
-
- IRQL = PASSIVE_LEVEL
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
- */
-void AsicSetSlotTime(struct rt_rtmp_adapter *pAd, IN BOOLEAN bUseShortSlotTime)
-{
- unsigned long SlotTime;
- u32 RegValue = 0;
-
- if (pAd->CommonCfg.Channel > 14)
- bUseShortSlotTime = TRUE;
-
- if (bUseShortSlotTime
- && OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_SHORT_SLOT_INUSED))
- return;
- else if ((!bUseShortSlotTime)
- && (!OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_SHORT_SLOT_INUSED)))
- return;
-
- if (bUseShortSlotTime)
- OPSTATUS_SET_FLAG(pAd, fOP_STATUS_SHORT_SLOT_INUSED);
- else
- OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_SHORT_SLOT_INUSED);
-
- SlotTime = (bUseShortSlotTime) ? 9 : 20;
-
- {
- /* force using short SLOT time for FAE to demo performance when TxBurst is ON */
- if (((pAd->StaActive.SupportedPhyInfo.bHtEnable == FALSE)
- && (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_WMM_INUSED)))
- || ((pAd->StaActive.SupportedPhyInfo.bHtEnable == TRUE)
- && (pAd->CommonCfg.BACapability.field.Policy ==
- BA_NOTUSE))
- ) {
- /* In this case, we will think it is doing Wi-Fi test */
- /* And we will not set to short slot when bEnableTxBurst is TRUE. */
- } else if (pAd->CommonCfg.bEnableTxBurst) {
- OPSTATUS_SET_FLAG(pAd, fOP_STATUS_SHORT_SLOT_INUSED);
- SlotTime = 9;
- }
- }
-
- /* */
- /* For some reasons, always set it to short slot time. */
- /* */
- /* ToDo: Should consider capability with 11B */
- /* */
- {
- if (pAd->StaCfg.BssType == BSS_ADHOC) {
- OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_SHORT_SLOT_INUSED);
- SlotTime = 20;
- }
- }
-
- RTMP_IO_READ32(pAd, BKOFF_SLOT_CFG, &RegValue);
- RegValue = RegValue & 0xFFFFFF00;
-
- RegValue |= SlotTime;
-
- RTMP_IO_WRITE32(pAd, BKOFF_SLOT_CFG, RegValue);
-}
-
-/*
- ========================================================================
- Description:
- Add Shared key information into ASIC.
- Update shared key, TxMic and RxMic to Asic Shared key table
- Update its cipherAlg to Asic Shared key Mode.
-
- Return:
- ========================================================================
-*/
-void AsicAddSharedKeyEntry(struct rt_rtmp_adapter *pAd,
- u8 BssIndex,
- u8 KeyIdx,
- u8 CipherAlg,
- u8 *pKey, u8 *pTxMic, u8 *pRxMic)
-{
- unsigned long offset; /*, csr0; */
- SHAREDKEY_MODE_STRUC csr1;
-#ifdef RTMP_MAC_PCI
- int i;
-#endif /* RTMP_MAC_PCI // */
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("AsicAddSharedKeyEntry BssIndex=%d, KeyIdx=%d\n", BssIndex,
- KeyIdx));
-/*============================================================================================ */
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("AsicAddSharedKeyEntry: %s key #%d\n", CipherName[CipherAlg],
- BssIndex * 4 + KeyIdx));
- DBGPRINT_RAW(RT_DEBUG_TRACE,
- (" Key = %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n",
- pKey[0], pKey[1], pKey[2], pKey[3], pKey[4],
- pKey[5], pKey[6], pKey[7], pKey[8], pKey[9],
- pKey[10], pKey[11], pKey[12], pKey[13], pKey[14],
- pKey[15]));
- if (pRxMic) {
- DBGPRINT_RAW(RT_DEBUG_TRACE,
- (" Rx MIC Key = %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n",
- pRxMic[0], pRxMic[1], pRxMic[2], pRxMic[3],
- pRxMic[4], pRxMic[5], pRxMic[6], pRxMic[7]));
- }
- if (pTxMic) {
- DBGPRINT_RAW(RT_DEBUG_TRACE,
- (" Tx MIC Key = %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n",
- pTxMic[0], pTxMic[1], pTxMic[2], pTxMic[3],
- pTxMic[4], pTxMic[5], pTxMic[6], pTxMic[7]));
- }
-/*============================================================================================ */
- /* */
- /* fill key material - key + TX MIC + RX MIC */
- /* */
-#ifdef RTMP_MAC_PCI
- offset =
- SHARED_KEY_TABLE_BASE + (4 * BssIndex + KeyIdx) * HW_KEY_ENTRY_SIZE;
- for (i = 0; i < MAX_LEN_OF_SHARE_KEY; i++) {
- RTMP_IO_WRITE8(pAd, offset + i, pKey[i]);
- }
-
- offset += MAX_LEN_OF_SHARE_KEY;
- if (pTxMic) {
- for (i = 0; i < 8; i++) {
- RTMP_IO_WRITE8(pAd, offset + i, pTxMic[i]);
- }
- }
-
- offset += 8;
- if (pRxMic) {
- for (i = 0; i < 8; i++) {
- RTMP_IO_WRITE8(pAd, offset + i, pRxMic[i]);
- }
- }
-#endif /* RTMP_MAC_PCI // */
-#ifdef RTMP_MAC_USB
- {
- offset =
- SHARED_KEY_TABLE_BASE + (4 * BssIndex +
- KeyIdx) * HW_KEY_ENTRY_SIZE;
- RTUSBMultiWrite(pAd, offset, pKey, MAX_LEN_OF_SHARE_KEY);
-
- offset += MAX_LEN_OF_SHARE_KEY;
- if (pTxMic) {
- RTUSBMultiWrite(pAd, offset, pTxMic, 8);
- }
-
- offset += 8;
- if (pRxMic) {
- RTUSBMultiWrite(pAd, offset, pRxMic, 8);
- }
- }
-#endif /* RTMP_MAC_USB // */
-
- /* */
- /* Update cipher algorithm. WSTA always use BSS0 */
- /* */
- RTMP_IO_READ32(pAd, SHARED_KEY_MODE_BASE + 4 * (BssIndex / 2),
- &csr1.word);
- DBGPRINT(RT_DEBUG_TRACE,
- ("Read: SHARED_KEY_MODE_BASE at this Bss[%d] KeyIdx[%d]= 0x%x \n",
- BssIndex, KeyIdx, csr1.word));
- if ((BssIndex % 2) == 0) {
- if (KeyIdx == 0)
- csr1.field.Bss0Key0CipherAlg = CipherAlg;
- else if (KeyIdx == 1)
- csr1.field.Bss0Key1CipherAlg = CipherAlg;
- else if (KeyIdx == 2)
- csr1.field.Bss0Key2CipherAlg = CipherAlg;
- else
- csr1.field.Bss0Key3CipherAlg = CipherAlg;
- } else {
- if (KeyIdx == 0)
- csr1.field.Bss1Key0CipherAlg = CipherAlg;
- else if (KeyIdx == 1)
- csr1.field.Bss1Key1CipherAlg = CipherAlg;
- else if (KeyIdx == 2)
- csr1.field.Bss1Key2CipherAlg = CipherAlg;
- else
- csr1.field.Bss1Key3CipherAlg = CipherAlg;
- }
- DBGPRINT(RT_DEBUG_TRACE,
- ("Write: SHARED_KEY_MODE_BASE at this Bss[%d] = 0x%x \n",
- BssIndex, csr1.word));
- RTMP_IO_WRITE32(pAd, SHARED_KEY_MODE_BASE + 4 * (BssIndex / 2),
- csr1.word);
-
-}
-
-/* IRQL = DISPATCH_LEVEL */
-void AsicRemoveSharedKeyEntry(struct rt_rtmp_adapter *pAd,
- u8 BssIndex, u8 KeyIdx)
-{
- /*unsigned long SecCsr0; */
- SHAREDKEY_MODE_STRUC csr1;
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("AsicRemoveSharedKeyEntry: #%d \n", BssIndex * 4 + KeyIdx));
-
- RTMP_IO_READ32(pAd, SHARED_KEY_MODE_BASE + 4 * (BssIndex / 2),
- &csr1.word);
- if ((BssIndex % 2) == 0) {
- if (KeyIdx == 0)
- csr1.field.Bss0Key0CipherAlg = 0;
- else if (KeyIdx == 1)
- csr1.field.Bss0Key1CipherAlg = 0;
- else if (KeyIdx == 2)
- csr1.field.Bss0Key2CipherAlg = 0;
- else
- csr1.field.Bss0Key3CipherAlg = 0;
- } else {
- if (KeyIdx == 0)
- csr1.field.Bss1Key0CipherAlg = 0;
- else if (KeyIdx == 1)
- csr1.field.Bss1Key1CipherAlg = 0;
- else if (KeyIdx == 2)
- csr1.field.Bss1Key2CipherAlg = 0;
- else
- csr1.field.Bss1Key3CipherAlg = 0;
- }
- DBGPRINT(RT_DEBUG_TRACE,
- ("Write: SHARED_KEY_MODE_BASE at this Bss[%d] = 0x%x \n",
- BssIndex, csr1.word));
- RTMP_IO_WRITE32(pAd, SHARED_KEY_MODE_BASE + 4 * (BssIndex / 2),
- csr1.word);
- ASSERT(BssIndex < 4);
- ASSERT(KeyIdx < 4);
-
-}
-
-void AsicUpdateWCIDAttribute(struct rt_rtmp_adapter *pAd,
- u16 WCID,
- u8 BssIndex,
- u8 CipherAlg,
- IN BOOLEAN bUsePairewiseKeyTable)
-{
- unsigned long WCIDAttri = 0, offset;
-
- /* */
- /* Update WCID attribute. */
- /* Only TxKey could update WCID attribute. */
- /* */
- offset = MAC_WCID_ATTRIBUTE_BASE + (WCID * HW_WCID_ATTRI_SIZE);
- WCIDAttri =
- (BssIndex << 4) | (CipherAlg << 1) | (bUsePairewiseKeyTable);
- RTMP_IO_WRITE32(pAd, offset, WCIDAttri);
-}
-
-void AsicUpdateWCIDIVEIV(struct rt_rtmp_adapter *pAd,
- u16 WCID, unsigned long uIV, unsigned long uEIV)
-{
- unsigned long offset;
-
- offset = MAC_IVEIV_TABLE_BASE + (WCID * HW_IVEIV_ENTRY_SIZE);
-
- RTMP_IO_WRITE32(pAd, offset, uIV);
- RTMP_IO_WRITE32(pAd, offset + 4, uEIV);
-}
-
-void AsicUpdateRxWCIDTable(struct rt_rtmp_adapter *pAd,
- u16 WCID, u8 *pAddr)
-{
- unsigned long offset;
- unsigned long Addr;
-
- offset = MAC_WCID_BASE + (WCID * HW_WCID_ENTRY_SIZE);
- Addr = pAddr[0] + (pAddr[1] << 8) + (pAddr[2] << 16) + (pAddr[3] << 24);
- RTMP_IO_WRITE32(pAd, offset, Addr);
- Addr = pAddr[4] + (pAddr[5] << 8);
- RTMP_IO_WRITE32(pAd, offset + 4, Addr);
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Set Cipher Key, Cipher algorithm, IV/EIV to Asic
-
- Arguments:
- pAd Pointer to our adapter
- WCID WCID Entry number.
- BssIndex BSSID index, station or none multiple BSSID support
- this value should be 0.
- KeyIdx This KeyIdx will set to IV's KeyID if bTxKey enabled
- pCipherKey Pointer to Cipher Key.
- bUsePairewiseKeyTable TRUE means saved the key in SharedKey table,
- otherwise PairewiseKey table
- bTxKey This is the transmit key if enabled.
-
- Return Value:
- None
-
- Note:
- This routine will set the relative key stuff to Asic including WCID attribute,
- Cipher Key, Cipher algorithm and IV/EIV.
-
- IV/EIV will be update if this CipherKey is the transmission key because
- ASIC will base on IV's KeyID value to select Cipher Key.
-
- If bTxKey sets to FALSE, this is not the TX key, but it could be
- RX key
-
- For AP mode bTxKey must be always set to TRUE.
- ========================================================================
-*/
-void AsicAddKeyEntry(struct rt_rtmp_adapter *pAd,
- u16 WCID,
- u8 BssIndex,
- u8 KeyIdx,
- struct rt_cipher_key *pCipherKey,
- IN BOOLEAN bUsePairewiseKeyTable, IN BOOLEAN bTxKey)
-{
- unsigned long offset;
-/* unsigned long WCIDAttri = 0; */
- u8 IV4 = 0;
- u8 *pKey = pCipherKey->Key;
-/* unsigned long KeyLen = pCipherKey->KeyLen; */
- u8 *pTxMic = pCipherKey->TxMic;
- u8 *pRxMic = pCipherKey->RxMic;
- u8 *pTxtsc = pCipherKey->TxTsc;
- u8 CipherAlg = pCipherKey->CipherAlg;
- SHAREDKEY_MODE_STRUC csr1;
-#ifdef RTMP_MAC_PCI
- u8 i;
-#endif /* RTMP_MAC_PCI // */
-
-/* ASSERT(KeyLen <= MAX_LEN_OF_PEER_KEY); */
-
- DBGPRINT(RT_DEBUG_TRACE, ("==> AsicAddKeyEntry\n"));
- /* */
- /* 1.) decide key table offset */
- /* */
- if (bUsePairewiseKeyTable)
- offset = PAIRWISE_KEY_TABLE_BASE + (WCID * HW_KEY_ENTRY_SIZE);
- else
- offset =
- SHARED_KEY_TABLE_BASE + (4 * BssIndex +
- KeyIdx) * HW_KEY_ENTRY_SIZE;
-
- /* */
- /* 2.) Set Key to Asic */
- /* */
- /*for (i = 0; i < KeyLen; i++) */
-#ifdef RTMP_MAC_PCI
- for (i = 0; i < MAX_LEN_OF_PEER_KEY; i++) {
- RTMP_IO_WRITE8(pAd, offset + i, pKey[i]);
- }
- offset += MAX_LEN_OF_PEER_KEY;
-
- /* */
- /* 3.) Set MIC key if available */
- /* */
- if (pTxMic) {
- for (i = 0; i < 8; i++) {
- RTMP_IO_WRITE8(pAd, offset + i, pTxMic[i]);
- }
- }
- offset += LEN_TKIP_TXMICK;
-
- if (pRxMic) {
- for (i = 0; i < 8; i++) {
- RTMP_IO_WRITE8(pAd, offset + i, pRxMic[i]);
- }
- }
-#endif /* RTMP_MAC_PCI // */
-#ifdef RTMP_MAC_USB
- RTUSBMultiWrite(pAd, offset, pKey, MAX_LEN_OF_PEER_KEY);
- offset += MAX_LEN_OF_PEER_KEY;
-
- /* */
- /* 3.) Set MIC key if available */
- /* */
- if (pTxMic) {
- RTUSBMultiWrite(pAd, offset, pTxMic, 8);
- }
- offset += LEN_TKIP_TXMICK;
-
- if (pRxMic) {
- RTUSBMultiWrite(pAd, offset, pRxMic, 8);
- }
-#endif /* RTMP_MAC_USB // */
-
- /* */
- /* 4.) Modify IV/EIV if needs */
- /* This will force Asic to use this key ID by setting IV. */
- /* */
- if (bTxKey) {
-#ifdef RTMP_MAC_PCI
- offset = MAC_IVEIV_TABLE_BASE + (WCID * HW_IVEIV_ENTRY_SIZE);
- /* */
- /* Write IV */
- /* */
- RTMP_IO_WRITE8(pAd, offset, pTxtsc[1]);
- RTMP_IO_WRITE8(pAd, offset + 1, ((pTxtsc[1] | 0x20) & 0x7f));
- RTMP_IO_WRITE8(pAd, offset + 2, pTxtsc[0]);
-
- IV4 = (KeyIdx << 6);
- if ((CipherAlg == CIPHER_TKIP)
- || (CipherAlg == CIPHER_TKIP_NO_MIC)
- || (CipherAlg == CIPHER_AES))
- IV4 |= 0x20; /* turn on extension bit means EIV existence */
-
- RTMP_IO_WRITE8(pAd, offset + 3, IV4);
-
- /* */
- /* Write EIV */
- /* */
- offset += 4;
- for (i = 0; i < 4; i++) {
- RTMP_IO_WRITE8(pAd, offset + i, pTxtsc[i + 2]);
- }
-#endif /* RTMP_MAC_PCI // */
-#ifdef RTMP_MAC_USB
- u32 tmpVal;
-
- /* */
- /* Write IV */
- /* */
- IV4 = (KeyIdx << 6);
- if ((CipherAlg == CIPHER_TKIP)
- || (CipherAlg == CIPHER_TKIP_NO_MIC)
- || (CipherAlg == CIPHER_AES))
- IV4 |= 0x20; /* turn on extension bit means EIV existence */
-
- tmpVal =
- pTxtsc[1] + (((pTxtsc[1] | 0x20) & 0x7f) << 8) +
- (pTxtsc[0] << 16) + (IV4 << 24);
- RTMP_IO_WRITE32(pAd, offset, tmpVal);
-
- /* */
- /* Write EIV */
- /* */
- offset += 4;
- RTMP_IO_WRITE32(pAd, offset, *(u32 *)& pCipherKey->TxTsc[2]);
-#endif /* RTMP_MAC_USB // */
-
- AsicUpdateWCIDAttribute(pAd, WCID, BssIndex, CipherAlg,
- bUsePairewiseKeyTable);
- }
-
- if (!bUsePairewiseKeyTable) {
- /* */
- /* Only update the shared key security mode */
- /* */
- RTMP_IO_READ32(pAd, SHARED_KEY_MODE_BASE + 4 * (BssIndex / 2),
- &csr1.word);
- if ((BssIndex % 2) == 0) {
- if (KeyIdx == 0)
- csr1.field.Bss0Key0CipherAlg = CipherAlg;
- else if (KeyIdx == 1)
- csr1.field.Bss0Key1CipherAlg = CipherAlg;
- else if (KeyIdx == 2)
- csr1.field.Bss0Key2CipherAlg = CipherAlg;
- else
- csr1.field.Bss0Key3CipherAlg = CipherAlg;
- } else {
- if (KeyIdx == 0)
- csr1.field.Bss1Key0CipherAlg = CipherAlg;
- else if (KeyIdx == 1)
- csr1.field.Bss1Key1CipherAlg = CipherAlg;
- else if (KeyIdx == 2)
- csr1.field.Bss1Key2CipherAlg = CipherAlg;
- else
- csr1.field.Bss1Key3CipherAlg = CipherAlg;
- }
- RTMP_IO_WRITE32(pAd, SHARED_KEY_MODE_BASE + 4 * (BssIndex / 2),
- csr1.word);
- }
-
- DBGPRINT(RT_DEBUG_TRACE, ("<== AsicAddKeyEntry\n"));
-}
-
-/*
- ========================================================================
- Description:
- Add Pair-wise key material into ASIC.
- Update pairwise key, TxMic and RxMic to Asic Pair-wise key table
-
- Return:
- ========================================================================
-*/
-void AsicAddPairwiseKeyEntry(struct rt_rtmp_adapter *pAd,
- u8 *pAddr,
- u8 WCID, struct rt_cipher_key *pCipherKey)
-{
- int i;
- unsigned long offset;
- u8 *pKey = pCipherKey->Key;
- u8 *pTxMic = pCipherKey->TxMic;
- u8 *pRxMic = pCipherKey->RxMic;
-#ifdef DBG
- u8 CipherAlg = pCipherKey->CipherAlg;
-#endif /* DBG // */
-
- /* EKEY */
- offset = PAIRWISE_KEY_TABLE_BASE + (WCID * HW_KEY_ENTRY_SIZE);
-#ifdef RTMP_MAC_PCI
- for (i = 0; i < MAX_LEN_OF_PEER_KEY; i++) {
- RTMP_IO_WRITE8(pAd, offset + i, pKey[i]);
- }
-#endif /* RTMP_MAC_PCI // */
-#ifdef RTMP_MAC_USB
- RTUSBMultiWrite(pAd, offset, &pCipherKey->Key[0], MAX_LEN_OF_PEER_KEY);
-#endif /* RTMP_MAC_USB // */
- for (i = 0; i < MAX_LEN_OF_PEER_KEY; i += 4) {
- u32 Value;
- RTMP_IO_READ32(pAd, offset + i, &Value);
- }
-
- offset += MAX_LEN_OF_PEER_KEY;
-
- /* MIC KEY */
- if (pTxMic) {
-#ifdef RTMP_MAC_PCI
- for (i = 0; i < 8; i++) {
- RTMP_IO_WRITE8(pAd, offset + i, pTxMic[i]);
- }
-#endif /* RTMP_MAC_PCI // */
-#ifdef RTMP_MAC_USB
- RTUSBMultiWrite(pAd, offset, &pCipherKey->TxMic[0], 8);
-#endif /* RTMP_MAC_USB // */
- }
- offset += 8;
- if (pRxMic) {
-#ifdef RTMP_MAC_PCI
- for (i = 0; i < 8; i++) {
- RTMP_IO_WRITE8(pAd, offset + i, pRxMic[i]);
- }
-#endif /* RTMP_MAC_PCI // */
-#ifdef RTMP_MAC_USB
- RTUSBMultiWrite(pAd, offset, &pCipherKey->RxMic[0], 8);
-#endif /* RTMP_MAC_USB // */
- }
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("AsicAddPairwiseKeyEntry: WCID #%d Alg=%s\n", WCID,
- CipherName[CipherAlg]));
- DBGPRINT(RT_DEBUG_TRACE,
- (" Key = %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n",
- pKey[0], pKey[1], pKey[2], pKey[3], pKey[4], pKey[5],
- pKey[6], pKey[7], pKey[8], pKey[9], pKey[10], pKey[11],
- pKey[12], pKey[13], pKey[14], pKey[15]));
- if (pRxMic) {
- DBGPRINT(RT_DEBUG_TRACE,
- (" Rx MIC Key = %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n",
- pRxMic[0], pRxMic[1], pRxMic[2], pRxMic[3],
- pRxMic[4], pRxMic[5], pRxMic[6], pRxMic[7]));
- }
- if (pTxMic) {
- DBGPRINT(RT_DEBUG_TRACE,
- (" Tx MIC Key = %02x:%02x:%02x:%02x:%02x:%02x:%02x:%02x\n",
- pTxMic[0], pTxMic[1], pTxMic[2], pTxMic[3],
- pTxMic[4], pTxMic[5], pTxMic[6], pTxMic[7]));
- }
-}
-
-/*
- ========================================================================
- Description:
- Remove Pair-wise key material from ASIC.
-
- Return:
- ========================================================================
-*/
-void AsicRemovePairwiseKeyEntry(struct rt_rtmp_adapter *pAd,
- u8 BssIdx, u8 Wcid)
-{
- unsigned long WCIDAttri;
- u16 offset;
-
- /* re-set the entry's WCID attribute as OPEN-NONE. */
- offset = MAC_WCID_ATTRIBUTE_BASE + (Wcid * HW_WCID_ATTRI_SIZE);
- WCIDAttri = (BssIdx << 4) | PAIRWISEKEYTABLE;
- RTMP_IO_WRITE32(pAd, offset, WCIDAttri);
-}
-
-BOOLEAN AsicSendCommandToMcu(struct rt_rtmp_adapter *pAd,
- u8 Command,
- u8 Token, u8 Arg0, u8 Arg1)
-{
-
- if (pAd->chipOps.sendCommandToMcu)
- pAd->chipOps.sendCommandToMcu(pAd, Command, Token, Arg0, Arg1);
-
- return TRUE;
-}
-
-void AsicSetRxAnt(struct rt_rtmp_adapter *pAd, u8 Ant)
-{
-#ifdef RT30xx
- /* RT3572 ATE need not to do this. */
- RT30xxSetRxAnt(pAd, Ant);
-#endif /* RT30xx // */
-}
-
-void AsicTurnOffRFClk(struct rt_rtmp_adapter *pAd, u8 Channel)
-{
- if (pAd->chipOps.AsicRfTurnOff) {
- pAd->chipOps.AsicRfTurnOff(pAd);
- } else {
- /* RF R2 bit 18 = 0 */
- u32 R1 = 0, R2 = 0, R3 = 0;
- u8 index;
- struct rt_rtmp_rf_regs *RFRegTable;
-
- RFRegTable = RF2850RegTable;
-
- switch (pAd->RfIcType) {
- case RFIC_2820:
- case RFIC_2850:
- case RFIC_2720:
- case RFIC_2750:
-
- for (index = 0; index < NUM_OF_2850_CHNL; index++) {
- if (Channel == RFRegTable[index].Channel) {
- R1 = RFRegTable[index].R1 & 0xffffdfff;
- R2 = RFRegTable[index].R2 & 0xfffbffff;
- R3 = RFRegTable[index].R3 & 0xfff3ffff;
-
- RTMP_RF_IO_WRITE32(pAd, R1);
- RTMP_RF_IO_WRITE32(pAd, R2);
-
- /* Program R1b13 to 1, R3/b18,19 to 0, R2b18 to 0. */
- /* Set RF R2 bit18=0, R3 bit[18:19]=0 */
- /*if (pAd->StaCfg.bRadio == FALSE) */
- if (1) {
- RTMP_RF_IO_WRITE32(pAd, R3);
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("AsicTurnOffRFClk#%d(RF=%d, ) , R2=0x%08x, R3 = 0x%08x \n",
- Channel,
- pAd->RfIcType, R2,
- R3));
- } else
- DBGPRINT(RT_DEBUG_TRACE,
- ("AsicTurnOffRFClk#%d(RF=%d, ) , R2=0x%08x \n",
- Channel,
- pAd->RfIcType, R2));
- break;
- }
- }
- break;
-
- default:
- break;
- }
- }
-}
-
-void AsicTurnOnRFClk(struct rt_rtmp_adapter *pAd, u8 Channel)
-{
- /* RF R2 bit 18 = 0 */
- u32 R1 = 0, R2 = 0, R3 = 0;
- u8 index;
- struct rt_rtmp_rf_regs *RFRegTable;
-
-#ifdef PCIE_PS_SUPPORT
- /* The RF programming sequence is difference between 3xxx and 2xxx */
- if ((IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd))) {
- return;
- }
-#endif /* PCIE_PS_SUPPORT // */
-
- RFRegTable = RF2850RegTable;
-
- switch (pAd->RfIcType) {
- case RFIC_2820:
- case RFIC_2850:
- case RFIC_2720:
- case RFIC_2750:
-
- for (index = 0; index < NUM_OF_2850_CHNL; index++) {
- if (Channel == RFRegTable[index].Channel) {
- R3 = pAd->LatchRfRegs.R3;
- R3 &= 0xfff3ffff;
- R3 |= 0x00080000;
- RTMP_RF_IO_WRITE32(pAd, R3);
-
- R1 = RFRegTable[index].R1;
- RTMP_RF_IO_WRITE32(pAd, R1);
-
- R2 = RFRegTable[index].R2;
- if (pAd->Antenna.field.TxPath == 1) {
- R2 |= 0x4000; /* If TXpath is 1, bit 14 = 1; */
- }
-
- if (pAd->Antenna.field.RxPath == 2) {
- R2 |= 0x40; /* write 1 to off Rxpath. */
- } else if (pAd->Antenna.field.RxPath == 1) {
- R2 |= 0x20040; /* write 1 to off RxPath */
- }
- RTMP_RF_IO_WRITE32(pAd, R2);
-
- break;
- }
- }
- break;
-
- default:
- break;
- }
-
- DBGPRINT(RT_DEBUG_TRACE, ("AsicTurnOnRFClk#%d(RF=%d, ) , R2=0x%08x\n",
- Channel, pAd->RfIcType, R2));
-}
diff --git a/drivers/staging/rt2860/common/cmm_cfg.c b/drivers/staging/rt2860/common/cmm_cfg.c
deleted file mode 100644
index 727f799..0000000
--- a/drivers/staging/rt2860/common/cmm_cfg.c
+++ /dev/null
@@ -1,258 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- cmm_cfg.c
-
- Abstract:
- Ralink WiFi Driver configuration related subroutines
-
- Revision History:
- Who When What
- --------- ---------- ----------------------------------------------
-*/
-
-#include "../rt_config.h"
-
-char *GetPhyMode(int Mode)
-{
- switch (Mode) {
- case MODE_CCK:
- return "CCK";
-
- case MODE_OFDM:
- return "OFDM";
- case MODE_HTMIX:
- return "HTMIX";
-
- case MODE_HTGREENFIELD:
- return "GREEN";
- default:
- return "N/A";
- }
-}
-
-char *GetBW(int BW)
-{
- switch (BW) {
- case BW_10:
- return "10M";
-
- case BW_20:
- return "20M";
- case BW_40:
- return "40M";
- default:
- return "N/A";
- }
-}
-
-/*
- ==========================================================================
- Description:
- Set Country Region to pAd->CommonCfg.CountryRegion.
- This command will not work, if the field of CountryRegion in eeprom is programmed.
-
- Return:
- TRUE if all parameters are OK, FALSE otherwise
- ==========================================================================
-*/
-int RT_CfgSetCountryRegion(struct rt_rtmp_adapter *pAd, char *arg, int band)
-{
- long region, regionMax;
- u8 *pCountryRegion;
-
- region = simple_strtol(arg, 0, 10);
-
- if (band == BAND_24G) {
- pCountryRegion = &pAd->CommonCfg.CountryRegion;
- regionMax = REGION_MAXIMUM_BG_BAND;
- } else {
- pCountryRegion = &pAd->CommonCfg.CountryRegionForABand;
- regionMax = REGION_MAXIMUM_A_BAND;
- }
-
- /* TODO: Is it neccesay for following check??? */
- /* Country can be set only when EEPROM not programmed */
- if (*pCountryRegion & 0x80) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("CfgSetCountryRegion():CountryRegion in eeprom was programmed\n"));
- return FALSE;
- }
-
- if ((region >= 0) && (region <= REGION_MAXIMUM_BG_BAND)) {
- *pCountryRegion = (u8)region;
- } else if ((region == REGION_31_BG_BAND) && (band == BAND_24G)) {
- *pCountryRegion = (u8)region;
- } else {
- DBGPRINT(RT_DEBUG_ERROR,
- ("CfgSetCountryRegion():region(%ld) out of range!\n",
- region));
- return FALSE;
- }
-
- return TRUE;
-
-}
-
-/*
- ==========================================================================
- Description:
- Set Wireless Mode
- Return:
- TRUE if all parameters are OK, FALSE otherwise
- ==========================================================================
-*/
-int RT_CfgSetWirelessMode(struct rt_rtmp_adapter *pAd, char *arg)
-{
- int MaxPhyMode = PHY_11G;
- long WirelessMode;
-
- MaxPhyMode = PHY_11N_5G;
-
- WirelessMode = simple_strtol(arg, 0, 10);
- if (WirelessMode <= MaxPhyMode) {
- pAd->CommonCfg.PhyMode = WirelessMode;
- return TRUE;
- }
-
- return FALSE;
-
-}
-
-int RT_CfgSetShortSlot(struct rt_rtmp_adapter *pAd, char *arg)
-{
- long ShortSlot;
-
- ShortSlot = simple_strtol(arg, 0, 10);
-
- if (ShortSlot == 1)
- pAd->CommonCfg.bUseShortSlotTime = TRUE;
- else if (ShortSlot == 0)
- pAd->CommonCfg.bUseShortSlotTime = FALSE;
- else
- return FALSE; /*Invalid argument */
-
- return TRUE;
-}
-
-/*
- ==========================================================================
- Description:
- Set WEP KEY base on KeyIdx
- Return:
- TRUE if all parameters are OK, FALSE otherwise
- ==========================================================================
-*/
-int RT_CfgSetWepKey(struct rt_rtmp_adapter *pAd,
- char *keyString,
- struct rt_cipher_key *pSharedKey, int keyIdx)
-{
- int KeyLen;
- int i;
- u8 CipherAlg = CIPHER_NONE;
- BOOLEAN bKeyIsHex = FALSE;
-
- /* TODO: Shall we do memset for the original key info?? */
- memset(pSharedKey, 0, sizeof(struct rt_cipher_key));
- KeyLen = strlen(keyString);
- switch (KeyLen) {
- case 5: /*wep 40 Ascii type */
- case 13: /*wep 104 Ascii type */
- bKeyIsHex = FALSE;
- pSharedKey->KeyLen = KeyLen;
- NdisMoveMemory(pSharedKey->Key, keyString, KeyLen);
- break;
-
- case 10: /*wep 40 Hex type */
- case 26: /*wep 104 Hex type */
- for (i = 0; i < KeyLen; i++) {
- if (!isxdigit(*(keyString + i)))
- return FALSE; /*Not Hex value; */
- }
- bKeyIsHex = TRUE;
- pSharedKey->KeyLen = KeyLen / 2;
- AtoH(keyString, pSharedKey->Key, pSharedKey->KeyLen);
- break;
-
- default: /*Invalid argument */
- DBGPRINT(RT_DEBUG_TRACE,
- ("RT_CfgSetWepKey(keyIdx=%d):Invalid argument (arg=%s)\n",
- keyIdx, keyString));
- return FALSE;
- }
-
- pSharedKey->CipherAlg = ((KeyLen % 5) ? CIPHER_WEP128 : CIPHER_WEP64);
- DBGPRINT(RT_DEBUG_TRACE,
- ("RT_CfgSetWepKey:(KeyIdx=%d,type=%s, Alg=%s)\n", keyIdx,
- (bKeyIsHex == FALSE ? "Ascii" : "Hex"),
- CipherName[CipherAlg]));
-
- return TRUE;
-}
-
-/*
- ==========================================================================
- Description:
- Set WPA PSK key
-
- Arguments:
- pAdapter Pointer to our adapter
- keyString WPA pre-shared key string
- pHashStr String used for password hash function
- hashStrLen Length of the hash string
- pPMKBuf Output buffer of WPAPSK key
-
- Return:
- TRUE if all parameters are OK, FALSE otherwise
- ==========================================================================
-*/
-int RT_CfgSetWPAPSKKey(struct rt_rtmp_adapter *pAd,
- char *keyString,
- u8 * pHashStr,
- int hashStrLen, u8 *pPMKBuf)
-{
- int keyLen;
- u8 keyMaterial[40];
-
- keyLen = strlen(keyString);
- if ((keyLen < 8) || (keyLen > 64)) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("WPAPSK Key length(%d) error, required 8 ~ 64 characters!(keyStr=%s)\n",
- keyLen, keyString));
- return FALSE;
- }
-
- memset(pPMKBuf, 0, 32);
- if (keyLen == 64) {
- AtoH(keyString, pPMKBuf, 32);
- } else {
- PasswordHash(keyString, pHashStr, hashStrLen, keyMaterial);
- NdisMoveMemory(pPMKBuf, keyMaterial, 32);
- }
-
- return TRUE;
-}
diff --git a/drivers/staging/rt2860/common/cmm_data.c b/drivers/staging/rt2860/common/cmm_data.c
deleted file mode 100644
index 33799e1..0000000
--- a/drivers/staging/rt2860/common/cmm_data.c
+++ /dev/null
@@ -1,2361 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-*/
-
-#include "../rt_config.h"
-
-u8 SNAP_802_1H[] = { 0xaa, 0xaa, 0x03, 0x00, 0x00, 0x00 };
-u8 SNAP_BRIDGE_TUNNEL[] = { 0xaa, 0xaa, 0x03, 0x00, 0x00, 0xf8 };
-
-/* Add Cisco Aironet SNAP heade for CCX2 support */
-u8 SNAP_AIRONET[] = { 0xaa, 0xaa, 0x03, 0x00, 0x40, 0x96, 0x00, 0x00 };
-u8 CKIP_LLC_SNAP[] = { 0xaa, 0xaa, 0x03, 0x00, 0x40, 0x96, 0x00, 0x02 };
-u8 EAPOL_LLC_SNAP[] = { 0xaa, 0xaa, 0x03, 0x00, 0x00, 0x00, 0x88, 0x8e };
-u8 EAPOL[] = { 0x88, 0x8e };
-u8 TPID[] = { 0x81, 0x00 }; /* VLAN related */
-
-u8 IPX[] = { 0x81, 0x37 };
-u8 APPLE_TALK[] = { 0x80, 0xf3 };
-
-u8 RateIdToPlcpSignal[12] = {
- 0, /* RATE_1 */ 1, /* RATE_2 */ 2, /* RATE_5_5 */ 3, /* RATE_11 *//* see BBP spec */
- 11, /* RATE_6 */ 15, /* RATE_9 */ 10, /* RATE_12 */ 14, /* RATE_18 *//* see IEEE802.11a-1999 p.14 */
- 9, /* RATE_24 */ 13, /* RATE_36 */ 8, /* RATE_48 */ 12 /* RATE_54 */
-}; /* see IEEE802.11a-1999 p.14 */
-
-u8 OfdmSignalToRateId[16] = {
- RATE_54, RATE_54, RATE_54, RATE_54, /* OFDM PLCP Signal = 0, 1, 2, 3 respectively */
- RATE_54, RATE_54, RATE_54, RATE_54, /* OFDM PLCP Signal = 4, 5, 6, 7 respectively */
- RATE_48, RATE_24, RATE_12, RATE_6, /* OFDM PLCP Signal = 8, 9, 10, 11 respectively */
- RATE_54, RATE_36, RATE_18, RATE_9, /* OFDM PLCP Signal = 12, 13, 14, 15 respectively */
-};
-
-u8 OfdmRateToRxwiMCS[12] = {
- 0, 0, 0, 0,
- 0, 1, 2, 3, /* OFDM rate 6,9,12,18 = rxwi mcs 0,1,2,3 */
- 4, 5, 6, 7, /* OFDM rate 24,36,48,54 = rxwi mcs 4,5,6,7 */
-};
-
-u8 RxwiMCSToOfdmRate[12] = {
- RATE_6, RATE_9, RATE_12, RATE_18,
- RATE_24, RATE_36, RATE_48, RATE_54, /* OFDM rate 6,9,12,18 = rxwi mcs 0,1,2,3 */
- 4, 5, 6, 7, /* OFDM rate 24,36,48,54 = rxwi mcs 4,5,6,7 */
-};
-
-char *MCSToMbps[] =
- { "1Mbps", "2Mbps", "5.5Mbps", "11Mbps", "06Mbps", "09Mbps", "12Mbps",
-"18Mbps", "24Mbps", "36Mbps", "48Mbps", "54Mbps", "MM-0", "MM-1", "MM-2", "MM-3",
-"MM-4", "MM-5", "MM-6", "MM-7", "MM-8", "MM-9", "MM-10", "MM-11", "MM-12", "MM-13",
-"MM-14", "MM-15", "MM-32", "ee1", "ee2", "ee3" };
-
-u8 default_cwmin[] =
- { CW_MIN_IN_BITS, CW_MIN_IN_BITS, CW_MIN_IN_BITS - 1, CW_MIN_IN_BITS - 2 };
-/*u8 default_cwmax[]={CW_MAX_IN_BITS, CW_MAX_IN_BITS, CW_MIN_IN_BITS, CW_MIN_IN_BITS-1}; */
-u8 default_sta_aifsn[] = { 3, 7, 2, 2 };
-
-u8 MapUserPriorityToAccessCategory[8] =
- { QID_AC_BE, QID_AC_BK, QID_AC_BK, QID_AC_BE, QID_AC_VI, QID_AC_VI,
-QID_AC_VO, QID_AC_VO };
-
-/*
- ========================================================================
-
- Routine Description:
- API for MLME to transmit management frame to AP (BSS Mode)
- or station (IBSS Mode)
-
- Arguments:
- pAd Pointer to our adapter
- pData Pointer to the outgoing 802.11 frame
- Length Size of outgoing management frame
-
- Return Value:
- NDIS_STATUS_FAILURE
- NDIS_STATUS_PENDING
- NDIS_STATUS_SUCCESS
-
- IRQL = PASSIVE_LEVEL
- IRQL = DISPATCH_LEVEL
-
- Note:
-
- ========================================================================
-*/
-int MiniportMMRequest(struct rt_rtmp_adapter *pAd,
- u8 QueIdx, u8 *pData, u32 Length)
-{
- void *pPacket;
- int Status = NDIS_STATUS_SUCCESS;
- unsigned long FreeNum;
- u8 rtmpHwHdr[TXINFO_SIZE + TXWI_SIZE]; /*RTMP_HW_HDR_LEN]; */
-#ifdef RTMP_MAC_PCI
- unsigned long IrqFlags = 0;
- u8 IrqState;
-#endif /* RTMP_MAC_PCI // */
- BOOLEAN bUseDataQ = FALSE;
- int retryCnt = 0;
-
- ASSERT(Length <= MGMT_DMA_BUFFER_SIZE);
-
- if ((QueIdx & MGMT_USE_QUEUE_FLAG) == MGMT_USE_QUEUE_FLAG) {
- bUseDataQ = TRUE;
- QueIdx &= (~MGMT_USE_QUEUE_FLAG);
- }
-#ifdef RTMP_MAC_PCI
- /* 2860C use Tx Ring */
- IrqState = pAd->irq_disabled;
- if (pAd->MACVersion == 0x28600100) {
- QueIdx = (bUseDataQ == TRUE ? QueIdx : 3);
- bUseDataQ = TRUE;
- }
- if (bUseDataQ && (!IrqState))
- RTMP_IRQ_LOCK(&pAd->irq_lock, IrqFlags);
-#endif /* RTMP_MAC_PCI // */
-
- do {
- /* Reset is in progress, stop immediately */
- if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_RESET_IN_PROGRESS) ||
- RTMP_TEST_FLAG(pAd,
- fRTMP_ADAPTER_HALT_IN_PROGRESS |
- fRTMP_ADAPTER_NIC_NOT_EXIST)
- || !RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_START_UP)) {
- Status = NDIS_STATUS_FAILURE;
- break;
- }
- /* Check Free priority queue */
- /* Since we use PBF Queue2 for management frame. Its corresponding DMA ring should be using TxRing. */
-#ifdef RTMP_MAC_PCI
- if (bUseDataQ) {
- retryCnt = MAX_DATAMM_RETRY;
- /* free Tx(QueIdx) resources */
- RTMPFreeTXDUponTxDmaDone(pAd, QueIdx);
- FreeNum = GET_TXRING_FREENO(pAd, QueIdx);
- } else
-#endif /* RTMP_MAC_PCI // */
- {
- FreeNum = GET_MGMTRING_FREENO(pAd);
- }
-
- if ((FreeNum > 0)) {
- /* We need to reserve space for rtmp hardware header. i.e., TxWI for RT2860 and TxInfo+TxWI for RT2870 */
- NdisZeroMemory(&rtmpHwHdr, (TXINFO_SIZE + TXWI_SIZE));
- Status =
- RTMPAllocateNdisPacket(pAd, &pPacket,
- (u8 *)& rtmpHwHdr,
- (TXINFO_SIZE + TXWI_SIZE),
- pData, Length);
- if (Status != NDIS_STATUS_SUCCESS) {
- DBGPRINT(RT_DEBUG_WARN,
- ("MiniportMMRequest (error:: can't allocate NDIS PACKET)\n"));
- break;
- }
- /*pAd->CommonCfg.MlmeTransmit.field.MODE = MODE_CCK; */
- /*pAd->CommonCfg.MlmeRate = RATE_2; */
-
-#ifdef RTMP_MAC_PCI
- if (bUseDataQ) {
- Status =
- MlmeDataHardTransmit(pAd, QueIdx, pPacket);
- retryCnt--;
- } else
-#endif /* RTMP_MAC_PCI // */
- Status = MlmeHardTransmit(pAd, QueIdx, pPacket);
- if (Status == NDIS_STATUS_SUCCESS)
- retryCnt = 0;
- else
- RTMPFreeNdisPacket(pAd, pPacket);
- } else {
- pAd->RalinkCounters.MgmtRingFullCount++;
-#ifdef RTMP_MAC_PCI
- if (bUseDataQ) {
- retryCnt--;
- DBGPRINT(RT_DEBUG_TRACE,
- ("retryCnt %d\n", retryCnt));
- if (retryCnt == 0) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("Qidx(%d), not enough space in DataRing, MgmtRingFullCount=%ld!\n",
- QueIdx,
- pAd->RalinkCounters.
- MgmtRingFullCount));
- }
- }
-#endif /* RTMP_MAC_PCI // */
- DBGPRINT(RT_DEBUG_ERROR,
- ("Qidx(%d), not enough space in MgmtRing, MgmtRingFullCount=%ld!\n",
- QueIdx,
- pAd->RalinkCounters.MgmtRingFullCount));
- }
- } while (retryCnt > 0);
-
-#ifdef RTMP_MAC_PCI
- if (bUseDataQ && (!IrqState))
- RTMP_IRQ_UNLOCK(&pAd->irq_lock, IrqFlags);
-#endif /* RTMP_MAC_PCI // */
-
- return Status;
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Copy frame from waiting queue into relative ring buffer and set
- appropriate ASIC register to kick hardware transmit function
-
- Arguments:
- pAd Pointer to our adapter
- pBuffer Pointer to memory of outgoing frame
- Length Size of outgoing management frame
-
- Return Value:
- NDIS_STATUS_FAILURE
- NDIS_STATUS_PENDING
- NDIS_STATUS_SUCCESS
-
- IRQL = PASSIVE_LEVEL
- IRQL = DISPATCH_LEVEL
-
- Note:
-
- ========================================================================
-*/
-int MlmeHardTransmit(struct rt_rtmp_adapter *pAd,
- u8 QueIdx, void *pPacket)
-{
- struct rt_packet_info PacketInfo;
- u8 *pSrcBufVA;
- u32 SrcBufLen;
- struct rt_header_802_11 * pHeader_802_11;
-
- if ((pAd->CommonCfg.RadarDetect.RDMode != RD_NORMAL_MODE)
- ) {
- return NDIS_STATUS_FAILURE;
- }
-
- RTMP_QueryPacketInfo(pPacket, &PacketInfo, &pSrcBufVA, &SrcBufLen);
- if (pSrcBufVA == NULL)
- return NDIS_STATUS_FAILURE;
-
- pHeader_802_11 = (struct rt_header_802_11 *) (pSrcBufVA + TXINFO_SIZE + TXWI_SIZE);
-
-#ifdef RTMP_MAC_PCI
- if (pAd->MACVersion == 0x28600100)
- return MlmeHardTransmitTxRing(pAd, QueIdx, pPacket);
- else
-#endif /* RTMP_MAC_PCI // */
- return MlmeHardTransmitMgmtRing(pAd, QueIdx, pPacket);
-
-}
-
-int MlmeHardTransmitMgmtRing(struct rt_rtmp_adapter *pAd,
- u8 QueIdx, void *pPacket)
-{
- struct rt_packet_info PacketInfo;
- u8 *pSrcBufVA;
- u32 SrcBufLen;
- struct rt_header_802_11 * pHeader_802_11;
- BOOLEAN bAckRequired, bInsertTimestamp;
- u8 MlmeRate;
- struct rt_txwi * pFirstTxWI;
- struct rt_mac_table_entry *pMacEntry = NULL;
- u8 PID;
-
- RTMP_QueryPacketInfo(pPacket, &PacketInfo, &pSrcBufVA, &SrcBufLen);
-
- /* Make sure MGMT ring resource won't be used by other threads */
- RTMP_SEM_LOCK(&pAd->MgmtRingLock);
- if (pSrcBufVA == NULL) {
- /* The buffer shouldn't be NULL */
- RTMP_SEM_UNLOCK(&pAd->MgmtRingLock);
- return NDIS_STATUS_FAILURE;
- }
-
- {
- /* outgoing frame always wakeup PHY to prevent frame lost */
- if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_DOZE))
- AsicForceWakeup(pAd, TRUE);
- }
-
- pFirstTxWI = (struct rt_txwi *) (pSrcBufVA + TXINFO_SIZE);
- pHeader_802_11 = (struct rt_header_802_11 *) (pSrcBufVA + TXINFO_SIZE + TXWI_SIZE); /*TXWI_SIZE); */
-
- if (pHeader_802_11->Addr1[0] & 0x01) {
- MlmeRate = pAd->CommonCfg.BasicMlmeRate;
- } else {
- MlmeRate = pAd->CommonCfg.MlmeRate;
- }
-
- /* Verify Mlme rate for a / g bands. */
- if ((pAd->LatchRfRegs.Channel > 14) && (MlmeRate < RATE_6)) /* 11A band */
- MlmeRate = RATE_6;
-
- if ((pHeader_802_11->FC.Type == BTYPE_DATA) &&
- (pHeader_802_11->FC.SubType == SUBTYPE_QOS_NULL)) {
- pMacEntry = MacTableLookup(pAd, pHeader_802_11->Addr1);
- }
-
- {
- /* Fixed W52 with Activity scan issue in ABG_MIXED and ABGN_MIXED mode. */
- if (pAd->CommonCfg.PhyMode == PHY_11ABG_MIXED
- || pAd->CommonCfg.PhyMode == PHY_11ABGN_MIXED) {
- if (pAd->LatchRfRegs.Channel > 14)
- pAd->CommonCfg.MlmeTransmit.field.MODE = 1;
- else
- pAd->CommonCfg.MlmeTransmit.field.MODE = 0;
- }
- }
-
- /* */
- /* Should not be hard code to set PwrMgmt to 0 (PWR_ACTIVE) */
- /* Snice it's been set to 0 while on MgtMacHeaderInit */
- /* By the way this will cause frame to be send on PWR_SAVE failed. */
- /* */
- pHeader_802_11->FC.PwrMgmt = PWR_ACTIVE; /* (pAd->StaCfg.Psm == PWR_SAVE); */
-
- /* */
- /* In WMM-UAPSD, mlme frame should be set psm as power saving but probe request frame */
- /* Data-Null packets also pass through MMRequest in RT2860, however, we hope control the psm bit to pass APSD */
-/* if ((pHeader_802_11->FC.Type != BTYPE_DATA) && (pHeader_802_11->FC.Type != BTYPE_CNTL)) */
- {
- if ((pHeader_802_11->FC.SubType == SUBTYPE_ACTION) ||
- ((pHeader_802_11->FC.Type == BTYPE_DATA) &&
- ((pHeader_802_11->FC.SubType == SUBTYPE_QOS_NULL) ||
- (pHeader_802_11->FC.SubType == SUBTYPE_NULL_FUNC)))) {
- if (pAd->StaCfg.Psm == PWR_SAVE)
- pHeader_802_11->FC.PwrMgmt = PWR_SAVE;
- else
- pHeader_802_11->FC.PwrMgmt =
- pAd->CommonCfg.bAPSDForcePowerSave;
- }
- }
-
- bInsertTimestamp = FALSE;
- if (pHeader_802_11->FC.Type == BTYPE_CNTL) /* must be PS-POLL */
- {
- /*Set PM bit in ps-poll, to fix WLK 1.2 PowerSaveMode_ext failure issue. */
- if ((pAd->OpMode == OPMODE_STA)
- && (pHeader_802_11->FC.SubType == SUBTYPE_PS_POLL)) {
- pHeader_802_11->FC.PwrMgmt = PWR_SAVE;
- }
- bAckRequired = FALSE;
- } else /* BTYPE_MGMT or BTYPE_DATA(must be NULL frame) */
- {
- /*pAd->Sequence++; */
- /*pHeader_802_11->Sequence = pAd->Sequence; */
-
- if (pHeader_802_11->Addr1[0] & 0x01) /* MULTICAST, BROADCAST */
- {
- bAckRequired = FALSE;
- pHeader_802_11->Duration = 0;
- } else {
- bAckRequired = TRUE;
- pHeader_802_11->Duration =
- RTMPCalcDuration(pAd, MlmeRate, 14);
- if ((pHeader_802_11->FC.SubType == SUBTYPE_PROBE_RSP)
- && (pHeader_802_11->FC.Type == BTYPE_MGMT)) {
- bInsertTimestamp = TRUE;
- bAckRequired = FALSE; /* Disable ACK to prevent retry 0x1f for Probe Response */
- } else
- if ((pHeader_802_11->FC.SubType ==
- SUBTYPE_PROBE_REQ)
- && (pHeader_802_11->FC.Type == BTYPE_MGMT)) {
- bAckRequired = FALSE; /* Disable ACK to prevent retry 0x1f for Probe Request */
- }
- }
- }
-
- pHeader_802_11->Sequence = pAd->Sequence++;
- if (pAd->Sequence > 0xfff)
- pAd->Sequence = 0;
-
- /* Before radar detection done, mgmt frame can not be sent but probe req */
- /* Because we need to use probe req to trigger driver to send probe req in passive scan */
- if ((pHeader_802_11->FC.SubType != SUBTYPE_PROBE_REQ)
- && (pAd->CommonCfg.bIEEE80211H == 1)
- && (pAd->CommonCfg.RadarDetect.RDMode != RD_NORMAL_MODE)) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("MlmeHardTransmit --> radar detect not in normal mode!\n"));
-/* if (!IrqState) */
- RTMP_SEM_UNLOCK(&pAd->MgmtRingLock);
- return (NDIS_STATUS_FAILURE);
- }
-
- /* */
- /* fill scatter-and-gather buffer list into TXD. Internally created NDIS PACKET */
- /* should always has only one physical buffer, and the whole frame size equals */
- /* to the first scatter buffer size */
- /* */
-
- /* Initialize TX Descriptor */
- /* For inter-frame gap, the number is for this frame and next frame */
- /* For MLME rate, we will fix as 2Mb to match other vendor's implement */
-/* pAd->CommonCfg.MlmeTransmit.field.MODE = 1; */
-
-/* management frame doesn't need encryption. so use RESERVED_WCID no matter u are sending to specific wcid or not. */
- PID = PID_MGMT;
-
- if (pMacEntry == NULL) {
- RTMPWriteTxWI(pAd, pFirstTxWI, FALSE, FALSE, bInsertTimestamp,
- FALSE, bAckRequired, FALSE, 0, RESERVED_WCID,
- (SrcBufLen - TXINFO_SIZE - TXWI_SIZE), PID, 0,
- (u8)pAd->CommonCfg.MlmeTransmit.field.MCS,
- IFS_BACKOFF, FALSE, &pAd->CommonCfg.MlmeTransmit);
- } else {
- /* dont use low rate to send QoS Null data frame */
- RTMPWriteTxWI(pAd, pFirstTxWI, FALSE, FALSE,
- bInsertTimestamp, FALSE, bAckRequired, FALSE,
- 0, pMacEntry->Aid,
- (SrcBufLen - TXINFO_SIZE - TXWI_SIZE),
- pMacEntry->MaxHTPhyMode.field.MCS, 0,
- (u8)pMacEntry->MaxHTPhyMode.field.MCS,
- IFS_BACKOFF, FALSE, &pMacEntry->MaxHTPhyMode);
- }
-
- /* Now do hardware-depened kick out. */
- HAL_KickOutMgmtTx(pAd, QueIdx, pPacket, pSrcBufVA, SrcBufLen);
-
- /* Make sure to release MGMT ring resource */
-/* if (!IrqState) */
- RTMP_SEM_UNLOCK(&pAd->MgmtRingLock);
- return NDIS_STATUS_SUCCESS;
-}
-
-/********************************************************************************
-
- New DeQueue Procedures.
-
- ********************************************************************************/
-
-#define DEQUEUE_LOCK(lock, bIntContext, IrqFlags) \
- do{ \
- if (bIntContext == FALSE) \
- RTMP_IRQ_LOCK((lock), IrqFlags); \
- }while(0)
-
-#define DEQUEUE_UNLOCK(lock, bIntContext, IrqFlags) \
- do{ \
- if (bIntContext == FALSE) \
- RTMP_IRQ_UNLOCK((lock), IrqFlags); \
- }while(0)
-
-/*
- ========================================================================
- Tx Path design algorithm:
- Basically, we divide the packets into four types, Broadcast/Multicast, 11N Rate(AMPDU, AMSDU, Normal), B/G Rate(ARALINK, Normal),
- Specific Packet Type. Following show the classification rule and policy for each kinds of packets.
- Classification Rule=>
- Multicast: (*addr1 & 0x01) == 0x01
- Specific : bDHCPFrame, bARPFrame, bEAPOLFrame, etc.
- 11N Rate : If peer support HT
- (1).AMPDU -- If TXBA is negotiated.
- (2).AMSDU -- If AMSDU is capable for both peer and ourself.
- *). AMSDU can embedded in a AMPDU, but now we didn't support it.
- (3).Normal -- Other packets which send as 11n rate.
-
- B/G Rate : If peer is b/g only.
- (1).ARALINK-- If both of peer/us supprot Ralink proprietary Aggregation and the TxRate is large than RATE_6
- (2).Normal -- Other packets which send as b/g rate.
- Fragment:
- The packet must be unicast, NOT A-RALINK, NOT A-MSDU, NOT 11n, then can consider about fragment.
-
- Classified Packet Handle Rule=>
- Multicast:
- No ACK, //pTxBlk->bAckRequired = FALSE;
- No WMM, //pTxBlk->bWMM = FALSE;
- No piggyback, //pTxBlk->bPiggyBack = FALSE;
- Force LowRate, //pTxBlk->bForceLowRate = TRUE;
- Specific : Basically, for specific packet, we should handle it specifically, but now all specific packets are use
- the same policy to handle it.
- Force LowRate, //pTxBlk->bForceLowRate = TRUE;
-
- 11N Rate :
- No piggyback, //pTxBlk->bPiggyBack = FALSE;
-
- (1).AMSDU
- pTxBlk->bWMM = TRUE;
- (2).AMPDU
- pTxBlk->bWMM = TRUE;
- (3).Normal
-
- B/G Rate :
- (1).ARALINK
-
- (2).Normal
- ========================================================================
-*/
-static u8 TxPktClassification(struct rt_rtmp_adapter *pAd, void *pPacket)
-{
- u8 TxFrameType = TX_UNKOWN_FRAME;
- u8 Wcid;
- struct rt_mac_table_entry *pMacEntry = NULL;
- BOOLEAN bHTRate = FALSE;
-
- Wcid = RTMP_GET_PACKET_WCID(pPacket);
- if (Wcid == MCAST_WCID) { /* Handle for RA is Broadcast/Multicast Address. */
- return TX_MCAST_FRAME;
- }
- /* Handle for unicast packets */
- pMacEntry = &pAd->MacTab.Content[Wcid];
- if (RTMP_GET_PACKET_LOWRATE(pPacket)) { /* It's a specific packet need to force low rate, i.e., bDHCPFrame, bEAPOLFrame, bWAIFrame */
- TxFrameType = TX_LEGACY_FRAME;
- } else if (IS_HT_RATE(pMacEntry)) { /* it's a 11n capable packet */
-
- /* Depends on HTPhyMode to check if the peer support the HTRate transmission. */
- /* Currently didn't support A-MSDU embedded in A-MPDU */
- bHTRate = TRUE;
- if (RTMP_GET_PACKET_MOREDATA(pPacket)
- || (pMacEntry->PsMode == PWR_SAVE))
- TxFrameType = TX_LEGACY_FRAME;
- else if ((pMacEntry->
- TXBAbitmap & (1 << (RTMP_GET_PACKET_UP(pPacket)))) !=
- 0)
- return TX_AMPDU_FRAME;
- else if (CLIENT_STATUS_TEST_FLAG
- (pMacEntry, fCLIENT_STATUS_AMSDU_INUSED))
- return TX_AMSDU_FRAME;
- else
- TxFrameType = TX_LEGACY_FRAME;
- } else { /* it's a legacy b/g packet. */
- if ((CLIENT_STATUS_TEST_FLAG(pMacEntry, fCLIENT_STATUS_AGGREGATION_CAPABLE) && pAd->CommonCfg.bAggregationCapable) && (RTMP_GET_PACKET_TXRATE(pPacket) >= RATE_6) && (!(OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_WMM_INUSED) && CLIENT_STATUS_TEST_FLAG(pMacEntry, fCLIENT_STATUS_WMM_CAPABLE)))) { /* if peer support Ralink Aggregation, we use it. */
- TxFrameType = TX_RALINK_FRAME;
- } else {
- TxFrameType = TX_LEGACY_FRAME;
- }
- }
-
- /* Currently, our fragment only support when a unicast packet send as NOT-ARALINK, NOT-AMSDU and NOT-AMPDU. */
- if ((RTMP_GET_PACKET_FRAGMENTS(pPacket) > 1)
- && (TxFrameType == TX_LEGACY_FRAME))
- TxFrameType = TX_FRAG_FRAME;
-
- return TxFrameType;
-}
-
-BOOLEAN RTMP_FillTxBlkInfo(struct rt_rtmp_adapter *pAd, struct rt_tx_blk *pTxBlk)
-{
- struct rt_packet_info PacketInfo;
- void *pPacket;
- struct rt_mac_table_entry *pMacEntry = NULL;
-
- pPacket = pTxBlk->pPacket;
- RTMP_QueryPacketInfo(pPacket, &PacketInfo, &pTxBlk->pSrcBufHeader,
- &pTxBlk->SrcBufLen);
-
- pTxBlk->Wcid = RTMP_GET_PACKET_WCID(pPacket);
- pTxBlk->apidx = RTMP_GET_PACKET_IF(pPacket);
- pTxBlk->UserPriority = RTMP_GET_PACKET_UP(pPacket);
- pTxBlk->FrameGap = IFS_HTTXOP; /* ASIC determine Frame Gap */
-
- if (RTMP_GET_PACKET_CLEAR_EAP_FRAME(pTxBlk->pPacket))
- TX_BLK_SET_FLAG(pTxBlk, fTX_bClearEAPFrame);
- else
- TX_BLK_CLEAR_FLAG(pTxBlk, fTX_bClearEAPFrame);
-
- /* Default to clear this flag */
- TX_BLK_CLEAR_FLAG(pTxBlk, fTX_bForceNonQoS);
-
- if (pTxBlk->Wcid == MCAST_WCID) {
- pTxBlk->pMacEntry = NULL;
- {
- pTxBlk->pTransmit =
- &pAd->MacTab.Content[MCAST_WCID].HTPhyMode;
- }
-
- TX_BLK_CLEAR_FLAG(pTxBlk, fTX_bAckRequired); /* AckRequired = FALSE, when broadcast packet in Adhoc mode. */
- /*TX_BLK_SET_FLAG(pTxBlk, fTX_bForceLowRate); */
- TX_BLK_CLEAR_FLAG(pTxBlk, fTX_bAllowFrag);
- TX_BLK_CLEAR_FLAG(pTxBlk, fTX_bWMM);
- if (RTMP_GET_PACKET_MOREDATA(pPacket)) {
- TX_BLK_SET_FLAG(pTxBlk, fTX_bMoreData);
- }
-
- } else {
- pTxBlk->pMacEntry = &pAd->MacTab.Content[pTxBlk->Wcid];
- pTxBlk->pTransmit = &pTxBlk->pMacEntry->HTPhyMode;
-
- pMacEntry = pTxBlk->pMacEntry;
-
- /* For all unicast packets, need Ack unless the Ack Policy is not set as NORMAL_ACK. */
- if (pAd->CommonCfg.AckPolicy[pTxBlk->QueIdx] != NORMAL_ACK)
- TX_BLK_CLEAR_FLAG(pTxBlk, fTX_bAckRequired);
- else
- TX_BLK_SET_FLAG(pTxBlk, fTX_bAckRequired);
-
- if ((pAd->OpMode == OPMODE_STA) &&
- (ADHOC_ON(pAd)) &&
- (RX_FILTER_TEST_FLAG(pAd, fRX_FILTER_ACCEPT_PROMISCUOUS))) {
- if (pAd->CommonCfg.PSPXlink)
- TX_BLK_CLEAR_FLAG(pTxBlk, fTX_bAckRequired);
- }
-
- {
- {
-
- /* If support WMM, enable it. */
- if (OPSTATUS_TEST_FLAG
- (pAd, fOP_STATUS_WMM_INUSED)
- && CLIENT_STATUS_TEST_FLAG(pMacEntry,
- fCLIENT_STATUS_WMM_CAPABLE))
- TX_BLK_SET_FLAG(pTxBlk, fTX_bWMM);
-
-/* if (pAd->StaCfg.bAutoTxRateSwitch) */
-/* TX_BLK_SET_FLAG(pTxBlk, fTX_AutoRateSwitch); */
- }
- }
-
- if (pTxBlk->TxFrameType == TX_LEGACY_FRAME) {
- if ((RTMP_GET_PACKET_LOWRATE(pPacket)) || ((pAd->OpMode == OPMODE_AP) && (pMacEntry->MaxHTPhyMode.field.MODE == MODE_CCK) && (pMacEntry->MaxHTPhyMode.field.MCS == RATE_1))) { /* Specific packet, i.e., bDHCPFrame, bEAPOLFrame, bWAIFrame, need force low rate. */
- pTxBlk->pTransmit =
- &pAd->MacTab.Content[MCAST_WCID].HTPhyMode;
-
- /* Modify the WMM bit for ICV issue. If we have a packet with EOSP field need to set as 1, how to handle it??? */
- if (IS_HT_STA(pTxBlk->pMacEntry) &&
- (CLIENT_STATUS_TEST_FLAG
- (pMacEntry, fCLIENT_STATUS_RALINK_CHIPSET))
- && ((pAd->CommonCfg.bRdg == TRUE)
- && CLIENT_STATUS_TEST_FLAG(pMacEntry,
- fCLIENT_STATUS_RDG_CAPABLE)))
- {
- TX_BLK_CLEAR_FLAG(pTxBlk, fTX_bWMM);
- TX_BLK_SET_FLAG(pTxBlk,
- fTX_bForceNonQoS);
- }
- }
-
- if ((IS_HT_RATE(pMacEntry) == FALSE) && (CLIENT_STATUS_TEST_FLAG(pMacEntry, fCLIENT_STATUS_PIGGYBACK_CAPABLE))) { /* Currently piggy-back only support when peer is operate in b/g mode. */
- TX_BLK_SET_FLAG(pTxBlk, fTX_bPiggyBack);
- }
-
- if (RTMP_GET_PACKET_MOREDATA(pPacket)) {
- TX_BLK_SET_FLAG(pTxBlk, fTX_bMoreData);
- }
- } else if (pTxBlk->TxFrameType == TX_FRAG_FRAME) {
- TX_BLK_SET_FLAG(pTxBlk, fTX_bAllowFrag);
- }
-
- pMacEntry->DebugTxCount++;
- }
-
- return TRUE;
-}
-
-BOOLEAN CanDoAggregateTransmit(struct rt_rtmp_adapter *pAd,
- char * pPacket, struct rt_tx_blk *pTxBlk)
-{
-
- /*DBGPRINT(RT_DEBUG_TRACE, ("Check if can do aggregation! TxFrameType=%d!\n", pTxBlk->TxFrameType)); */
-
- if (RTMP_GET_PACKET_WCID(pPacket) == MCAST_WCID)
- return FALSE;
-
- if (RTMP_GET_PACKET_DHCP(pPacket) ||
- RTMP_GET_PACKET_EAPOL(pPacket) || RTMP_GET_PACKET_WAI(pPacket))
- return FALSE;
-
- if ((pTxBlk->TxFrameType == TX_AMSDU_FRAME) && ((pTxBlk->TotalFrameLen + GET_OS_PKT_LEN(pPacket)) > (RX_BUFFER_AGGRESIZE - 100))) { /* For AMSDU, allow the packets with total length < max-amsdu size */
- return FALSE;
- }
-
- if ((pTxBlk->TxFrameType == TX_RALINK_FRAME) && (pTxBlk->TxPacketList.Number == 2)) { /* For RALINK-Aggregation, allow two frames in one batch. */
- return FALSE;
- }
-
- if ((INFRA_ON(pAd)) && (pAd->OpMode == OPMODE_STA)) /* must be unicast to AP */
- return TRUE;
- else
- return FALSE;
-
-}
-
-/*
- ========================================================================
-
- Routine Description:
- To do the enqueue operation and extract the first item of waiting
- list. If a number of available shared memory segments could meet
- the request of extracted item, the extracted item will be fragmented
- into shared memory segments.
-
- Arguments:
- pAd Pointer to our adapter
- pQueue Pointer to Waiting Queue
-
- Return Value:
- None
-
- IRQL = DISPATCH_LEVEL
-
- Note:
-
- ========================================================================
-*/
-void RTMPDeQueuePacket(struct rt_rtmp_adapter *pAd, IN BOOLEAN bIntContext, u8 QIdx, /* BulkOutPipeId */
- u8 Max_Tx_Packets)
-{
- struct rt_queue_entry *pEntry = NULL;
- void *pPacket;
- int Status = NDIS_STATUS_SUCCESS;
- u8 Count = 0;
- struct rt_queue_header *pQueue;
- unsigned long FreeNumber[NUM_OF_TX_RING];
- u8 QueIdx, sQIdx, eQIdx;
- unsigned long IrqFlags = 0;
- BOOLEAN hasTxDesc = FALSE;
- struct rt_tx_blk TxBlk;
- struct rt_tx_blk *pTxBlk;
-
- if (QIdx == NUM_OF_TX_RING) {
- sQIdx = 0;
- eQIdx = 3; /* 4 ACs, start from 0. */
- } else {
- sQIdx = eQIdx = QIdx;
- }
-
- for (QueIdx = sQIdx; QueIdx <= eQIdx; QueIdx++) {
- Count = 0;
-
- RTMP_START_DEQUEUE(pAd, QueIdx, IrqFlags);
-
- while (1) {
- if ((RTMP_TEST_FLAG
- (pAd,
- (fRTMP_ADAPTER_BSS_SCAN_IN_PROGRESS |
- fRTMP_ADAPTER_RADIO_OFF |
- fRTMP_ADAPTER_RESET_IN_PROGRESS |
- fRTMP_ADAPTER_HALT_IN_PROGRESS |
- fRTMP_ADAPTER_NIC_NOT_EXIST)))) {
- RTMP_STOP_DEQUEUE(pAd, QueIdx, IrqFlags);
- return;
- }
-
- if (Count >= Max_Tx_Packets)
- break;
-
- DEQUEUE_LOCK(&pAd->irq_lock, bIntContext, IrqFlags);
- if (&pAd->TxSwQueue[QueIdx] == NULL) {
- DEQUEUE_UNLOCK(&pAd->irq_lock, bIntContext,
- IrqFlags);
- break;
- }
-#ifdef RTMP_MAC_PCI
- FreeNumber[QueIdx] = GET_TXRING_FREENO(pAd, QueIdx);
-
- if (FreeNumber[QueIdx] <= 5) {
- /* free Tx(QueIdx) resources */
- RTMPFreeTXDUponTxDmaDone(pAd, QueIdx);
- FreeNumber[QueIdx] =
- GET_TXRING_FREENO(pAd, QueIdx);
- }
-#endif /* RTMP_MAC_PCI // */
-
- /* probe the Queue Head */
- pQueue = &pAd->TxSwQueue[QueIdx];
- pEntry = pQueue->Head;
- if (pEntry == NULL) {
- DEQUEUE_UNLOCK(&pAd->irq_lock, bIntContext,
- IrqFlags);
- break;
- }
-
- pTxBlk = &TxBlk;
- NdisZeroMemory((u8 *)pTxBlk, sizeof(struct rt_tx_blk));
- /*InitializeQueueHeader(&pTxBlk->TxPacketList); // Didn't need it because we already memzero it. */
- pTxBlk->QueIdx = QueIdx;
-
- pPacket = QUEUE_ENTRY_TO_PACKET(pEntry);
-
- /* Early check to make sure we have enoguh Tx Resource. */
- hasTxDesc =
- RTMP_HAS_ENOUGH_FREE_DESC(pAd, pTxBlk,
- FreeNumber[QueIdx],
- pPacket);
- if (!hasTxDesc) {
- pAd->PrivateInfo.TxRingFullCnt++;
-
- DEQUEUE_UNLOCK(&pAd->irq_lock, bIntContext,
- IrqFlags);
-
- break;
- }
-
- pTxBlk->TxFrameType = TxPktClassification(pAd, pPacket);
- pEntry = RemoveHeadQueue(pQueue);
- pTxBlk->TotalFrameNum++;
- pTxBlk->TotalFragNum += RTMP_GET_PACKET_FRAGMENTS(pPacket); /* The real fragment number maybe vary */
- pTxBlk->TotalFrameLen += GET_OS_PKT_LEN(pPacket);
- pTxBlk->pPacket = pPacket;
- InsertTailQueue(&pTxBlk->TxPacketList,
- PACKET_TO_QUEUE_ENTRY(pPacket));
-
- if (pTxBlk->TxFrameType == TX_RALINK_FRAME
- || pTxBlk->TxFrameType == TX_AMSDU_FRAME) {
- /* Enhance SW Aggregation Mechanism */
- if (NEED_QUEUE_BACK_FOR_AGG
- (pAd, QueIdx, FreeNumber[QueIdx],
- pTxBlk->TxFrameType)) {
- InsertHeadQueue(pQueue,
- PACKET_TO_QUEUE_ENTRY
- (pPacket));
- DEQUEUE_UNLOCK(&pAd->irq_lock,
- bIntContext, IrqFlags);
- break;
- }
-
- do {
- pEntry = pQueue->Head;
- if (pEntry == NULL)
- break;
-
- /* For TX_AMSDU_FRAME/TX_RALINK_FRAME, Need to check if next pakcet can do aggregation. */
- pPacket = QUEUE_ENTRY_TO_PACKET(pEntry);
- FreeNumber[QueIdx] =
- GET_TXRING_FREENO(pAd, QueIdx);
- hasTxDesc =
- RTMP_HAS_ENOUGH_FREE_DESC(pAd,
- pTxBlk,
- FreeNumber
- [QueIdx],
- pPacket);
- if ((hasTxDesc == FALSE)
- ||
- (CanDoAggregateTransmit
- (pAd, pPacket, pTxBlk) == FALSE))
- break;
-
- /*Remove the packet from the TxSwQueue and insert into pTxBlk */
- pEntry = RemoveHeadQueue(pQueue);
- ASSERT(pEntry);
- pPacket = QUEUE_ENTRY_TO_PACKET(pEntry);
- pTxBlk->TotalFrameNum++;
- pTxBlk->TotalFragNum += RTMP_GET_PACKET_FRAGMENTS(pPacket); /* The real fragment number maybe vary */
- pTxBlk->TotalFrameLen +=
- GET_OS_PKT_LEN(pPacket);
- InsertTailQueue(&pTxBlk->TxPacketList,
- PACKET_TO_QUEUE_ENTRY
- (pPacket));
- } while (1);
-
- if (pTxBlk->TxPacketList.Number == 1)
- pTxBlk->TxFrameType = TX_LEGACY_FRAME;
- }
-#ifdef RTMP_MAC_USB
- DEQUEUE_UNLOCK(&pAd->irq_lock, bIntContext, IrqFlags);
-#endif /* RTMP_MAC_USB // */
- Count += pTxBlk->TxPacketList.Number;
-
- /* Do HardTransmit now. */
- Status = STAHardTransmit(pAd, pTxBlk, QueIdx);
-
-#ifdef RTMP_MAC_PCI
- DEQUEUE_UNLOCK(&pAd->irq_lock, bIntContext, IrqFlags);
- /* static rate also need NICUpdateFifoStaCounters() function. */
- /*if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_TX_RATE_SWITCH_ENABLED)) */
- NICUpdateFifoStaCounters(pAd);
-#endif /* RTMP_MAC_PCI // */
-
- }
-
- RTMP_STOP_DEQUEUE(pAd, QueIdx, IrqFlags);
-
-#ifdef RTMP_MAC_USB
- if (!hasTxDesc)
- RTUSBKickBulkOut(pAd);
-#endif /* RTMP_MAC_USB // */
- }
-
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Calculates the duration which is required to transmit out frames
- with given size and specified rate.
-
- Arguments:
- pAd Pointer to our adapter
- Rate Transmit rate
- Size Frame size in units of byte
-
- Return Value:
- Duration number in units of usec
-
- IRQL = PASSIVE_LEVEL
- IRQL = DISPATCH_LEVEL
-
- Note:
-
- ========================================================================
-*/
-u16 RTMPCalcDuration(struct rt_rtmp_adapter *pAd, u8 Rate, unsigned long Size)
-{
- unsigned long Duration = 0;
-
- if (Rate < RATE_FIRST_OFDM_RATE) /* CCK */
- {
- if ((Rate > RATE_1)
- && OPSTATUS_TEST_FLAG(pAd,
- fOP_STATUS_SHORT_PREAMBLE_INUSED))
- Duration = 96; /* 72+24 preamble+plcp */
- else
- Duration = 192; /* 144+48 preamble+plcp */
-
- Duration += (u16)((Size << 4) / RateIdTo500Kbps[Rate]);
- if ((Size << 4) % RateIdTo500Kbps[Rate])
- Duration++;
- } else if (Rate <= RATE_LAST_OFDM_RATE) /* OFDM rates */
- {
- Duration = 20 + 6; /* 16+4 preamble+plcp + Signal Extension */
- Duration +=
- 4 * (u16)((11 + Size * 4) / RateIdTo500Kbps[Rate]);
- if ((11 + Size * 4) % RateIdTo500Kbps[Rate])
- Duration += 4;
- } else /*mimo rate */
- {
- Duration = 20 + 6; /* 16+4 preamble+plcp + Signal Extension */
- }
-
- return (u16)Duration;
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Calculates the duration which is required to transmit out frames
- with given size and specified rate.
-
- Arguments:
- pTxWI Pointer to head of each MPDU to HW.
- Ack Setting for Ack requirement bit
- Fragment Setting for Fragment bit
- RetryMode Setting for retry mode
- Ifs Setting for IFS gap
- Rate Setting for transmit rate
- Service Setting for service
- Length Frame length
- TxPreamble Short or Long preamble when using CCK rates
- QueIdx - 0-3, according to 802.11e/d4.4 June/2003
-
- Return Value:
- None
-
- IRQL = PASSIVE_LEVEL
- IRQL = DISPATCH_LEVEL
-
- See also : BASmartHardTransmit() !
-
- ========================================================================
-*/
-void RTMPWriteTxWI(struct rt_rtmp_adapter *pAd, struct rt_txwi * pOutTxWI, IN BOOLEAN FRAG, IN BOOLEAN CFACK, IN BOOLEAN InsTimestamp, IN BOOLEAN AMPDU, IN BOOLEAN Ack, IN BOOLEAN NSeq, /* HW new a sequence. */
- u8 BASize,
- u8 WCID,
- unsigned long Length,
- u8 PID,
- u8 TID,
- u8 TxRate,
- u8 Txopmode,
- IN BOOLEAN CfAck, IN HTTRANSMIT_SETTING * pTransmit)
-{
- struct rt_mac_table_entry *pMac = NULL;
- struct rt_txwi TxWI;
- struct rt_txwi * pTxWI;
-
- if (WCID < MAX_LEN_OF_MAC_TABLE)
- pMac = &pAd->MacTab.Content[WCID];
-
- /* */
- /* Always use Long preamble before verifiation short preamble functionality works well. */
- /* Todo: remove the following line if short preamble functionality works */
- /* */
- OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_SHORT_PREAMBLE_INUSED);
- NdisZeroMemory(&TxWI, TXWI_SIZE);
- pTxWI = &TxWI;
-
- pTxWI->FRAG = FRAG;
-
- pTxWI->CFACK = CFACK;
- pTxWI->TS = InsTimestamp;
- pTxWI->AMPDU = AMPDU;
- pTxWI->ACK = Ack;
- pTxWI->txop = Txopmode;
-
- pTxWI->NSEQ = NSeq;
- /* John tune the performace with Intel Client in 20 MHz performance */
- BASize = pAd->CommonCfg.TxBASize;
- if (pAd->MACVersion == 0x28720200) {
- if (BASize > 13)
- BASize = 13;
- } else {
- if (BASize > 7)
- BASize = 7;
- }
- pTxWI->BAWinSize = BASize;
- pTxWI->ShortGI = pTransmit->field.ShortGI;
- pTxWI->STBC = pTransmit->field.STBC;
-
- pTxWI->WirelessCliID = WCID;
- pTxWI->MPDUtotalByteCount = Length;
- pTxWI->PacketId = PID;
-
- /* If CCK or OFDM, BW must be 20 */
- pTxWI->BW =
- (pTransmit->field.MODE <=
- MODE_OFDM) ? (BW_20) : (pTransmit->field.BW);
-
- pTxWI->MCS = pTransmit->field.MCS;
- pTxWI->PHYMODE = pTransmit->field.MODE;
- pTxWI->CFACK = CfAck;
-
- if (pMac) {
- if (pAd->CommonCfg.bMIMOPSEnable) {
- if ((pMac->MmpsMode == MMPS_DYNAMIC)
- && (pTransmit->field.MCS > 7)) {
- /* Dynamic MIMO Power Save Mode */
- pTxWI->MIMOps = 1;
- } else if (pMac->MmpsMode == MMPS_STATIC) {
- /* Static MIMO Power Save Mode */
- if (pTransmit->field.MODE >= MODE_HTMIX
- && pTransmit->field.MCS > 7) {
- pTxWI->MCS = 7;
- pTxWI->MIMOps = 0;
- }
- }
- }
- /*pTxWI->MIMOps = (pMac->PsMode == PWR_MMPS)? 1:0; */
- if (pMac->bIAmBadAtheros
- && (pMac->WepStatus != Ndis802_11WEPDisabled)) {
- pTxWI->MpduDensity = 7;
- } else {
- pTxWI->MpduDensity = pMac->MpduDensity;
- }
- }
-
- pTxWI->PacketId = pTxWI->MCS;
- NdisMoveMemory(pOutTxWI, &TxWI, sizeof(struct rt_txwi));
-}
-
-void RTMPWriteTxWI_Data(struct rt_rtmp_adapter *pAd,
- struct rt_txwi * pTxWI, struct rt_tx_blk *pTxBlk)
-{
- HTTRANSMIT_SETTING *pTransmit;
- struct rt_mac_table_entry *pMacEntry;
- u8 BASize;
-
- ASSERT(pTxWI);
-
- pTransmit = pTxBlk->pTransmit;
- pMacEntry = pTxBlk->pMacEntry;
-
- /* */
- /* Always use Long preamble before verifiation short preamble functionality works well. */
- /* Todo: remove the following line if short preamble functionality works */
- /* */
- OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_SHORT_PREAMBLE_INUSED);
- NdisZeroMemory(pTxWI, TXWI_SIZE);
-
- pTxWI->FRAG = TX_BLK_TEST_FLAG(pTxBlk, fTX_bAllowFrag);
- pTxWI->ACK = TX_BLK_TEST_FLAG(pTxBlk, fTX_bAckRequired);
- pTxWI->txop = pTxBlk->FrameGap;
-
- pTxWI->WirelessCliID = pTxBlk->Wcid;
-
- pTxWI->MPDUtotalByteCount = pTxBlk->MpduHeaderLen + pTxBlk->SrcBufLen;
- pTxWI->CFACK = TX_BLK_TEST_FLAG(pTxBlk, fTX_bPiggyBack);
-
- /* If CCK or OFDM, BW must be 20 */
- pTxWI->BW =
- (pTransmit->field.MODE <=
- MODE_OFDM) ? (BW_20) : (pTransmit->field.BW);
- pTxWI->AMPDU = ((pTxBlk->TxFrameType == TX_AMPDU_FRAME) ? TRUE : FALSE);
-
- /* John tune the performace with Intel Client in 20 MHz performance */
- BASize = pAd->CommonCfg.TxBASize;
- if ((pTxBlk->TxFrameType == TX_AMPDU_FRAME) && (pMacEntry)) {
- u8 RABAOriIdx = 0; /*The RA's BA Originator table index. */
-
- RABAOriIdx =
- pTxBlk->pMacEntry->BAOriWcidArray[pTxBlk->UserPriority];
- BASize = pAd->BATable.BAOriEntry[RABAOriIdx].BAWinSize;
- }
-
- pTxWI->TxBF = pTransmit->field.TxBF;
- pTxWI->BAWinSize = BASize;
- pTxWI->ShortGI = pTransmit->field.ShortGI;
- pTxWI->STBC = pTransmit->field.STBC;
-
- pTxWI->MCS = pTransmit->field.MCS;
- pTxWI->PHYMODE = pTransmit->field.MODE;
-
- if (pMacEntry) {
- if ((pMacEntry->MmpsMode == MMPS_DYNAMIC)
- && (pTransmit->field.MCS > 7)) {
- /* Dynamic MIMO Power Save Mode */
- pTxWI->MIMOps = 1;
- } else if (pMacEntry->MmpsMode == MMPS_STATIC) {
- /* Static MIMO Power Save Mode */
- if (pTransmit->field.MODE >= MODE_HTMIX
- && pTransmit->field.MCS > 7) {
- pTxWI->MCS = 7;
- pTxWI->MIMOps = 0;
- }
- }
-
- if (pMacEntry->bIAmBadAtheros
- && (pMacEntry->WepStatus != Ndis802_11WEPDisabled)) {
- pTxWI->MpduDensity = 7;
- } else {
- pTxWI->MpduDensity = pMacEntry->MpduDensity;
- }
- }
-
- /* for rate adapation */
- pTxWI->PacketId = pTxWI->MCS;
-}
-
-void RTMPWriteTxWI_Cache(struct rt_rtmp_adapter *pAd,
- struct rt_txwi * pTxWI, struct rt_tx_blk *pTxBlk)
-{
- PHTTRANSMIT_SETTING /*pTxHTPhyMode, */ pTransmit;
- struct rt_mac_table_entry *pMacEntry;
-
- /* */
- /* update TXWI */
- /* */
- pMacEntry = pTxBlk->pMacEntry;
- pTransmit = pTxBlk->pTransmit;
-
- /*if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_TX_RATE_SWITCH_ENABLED)) */
- /*if (RTMPCheckEntryEnableAutoRateSwitch(pAd, pMacEntry)) */
- /*if (TX_BLK_TEST_FLAG(pTxBlk, fTX_AutoRateSwitch)) */
- if (pMacEntry->bAutoTxRateSwitch) {
- pTxWI->txop = IFS_HTTXOP;
-
- /* If CCK or OFDM, BW must be 20 */
- pTxWI->BW =
- (pTransmit->field.MODE <=
- MODE_OFDM) ? (BW_20) : (pTransmit->field.BW);
- pTxWI->ShortGI = pTransmit->field.ShortGI;
- pTxWI->STBC = pTransmit->field.STBC;
-
- pTxWI->MCS = pTransmit->field.MCS;
- pTxWI->PHYMODE = pTransmit->field.MODE;
-
- /* set PID for TxRateSwitching */
- pTxWI->PacketId = pTransmit->field.MCS;
- }
-
- pTxWI->AMPDU = ((pMacEntry->NoBADataCountDown == 0) ? TRUE : FALSE);
- pTxWI->MIMOps = 0;
-
- if (pAd->CommonCfg.bMIMOPSEnable) {
- /* MIMO Power Save Mode */
- if ((pMacEntry->MmpsMode == MMPS_DYNAMIC)
- && (pTransmit->field.MCS > 7)) {
- /* Dynamic MIMO Power Save Mode */
- pTxWI->MIMOps = 1;
- } else if (pMacEntry->MmpsMode == MMPS_STATIC) {
- /* Static MIMO Power Save Mode */
- if ((pTransmit->field.MODE >= MODE_HTMIX)
- && (pTransmit->field.MCS > 7)) {
- pTxWI->MCS = 7;
- pTxWI->MIMOps = 0;
- }
- }
- }
-
- pTxWI->MPDUtotalByteCount = pTxBlk->MpduHeaderLen + pTxBlk->SrcBufLen;
-
-}
-
-/* should be called only when - */
-/* 1. MEADIA_CONNECTED */
-/* 2. AGGREGATION_IN_USED */
-/* 3. Fragmentation not in used */
-/* 4. either no previous frame (pPrevAddr1=NULL) .OR. previoud frame is aggregatible */
-BOOLEAN TxFrameIsAggregatible(struct rt_rtmp_adapter *pAd,
- u8 *pPrevAddr1, u8 *p8023hdr)
-{
-
- /* can't aggregate EAPOL (802.1x) frame */
- if ((p8023hdr[12] == 0x88) && (p8023hdr[13] == 0x8e))
- return FALSE;
-
- /* can't aggregate multicast/broadcast frame */
- if (p8023hdr[0] & 0x01)
- return FALSE;
-
- if (INFRA_ON(pAd)) /* must be unicast to AP */
- return TRUE;
- else if ((pPrevAddr1 == NULL) || MAC_ADDR_EQUAL(pPrevAddr1, p8023hdr)) /* unicast to same STA */
- return TRUE;
- else
- return FALSE;
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Check the MSDU Aggregation policy
- 1.HT aggregation is A-MSDU
- 2.legaacy rate aggregation is software aggregation by Ralink.
-
- Arguments:
-
- Return Value:
-
- Note:
-
- ========================================================================
-*/
-BOOLEAN PeerIsAggreOn(struct rt_rtmp_adapter *pAd,
- unsigned long TxRate, struct rt_mac_table_entry *pMacEntry)
-{
- unsigned long AFlags =
- (fCLIENT_STATUS_AMSDU_INUSED | fCLIENT_STATUS_AGGREGATION_CAPABLE);
-
- if (pMacEntry != NULL && CLIENT_STATUS_TEST_FLAG(pMacEntry, AFlags)) {
- if (pMacEntry->HTPhyMode.field.MODE >= MODE_HTMIX) {
- return TRUE;
- }
-#ifdef AGGREGATION_SUPPORT
- if (TxRate >= RATE_6 && pAd->CommonCfg.bAggregationCapable && (!(OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_WMM_INUSED) && CLIENT_STATUS_TEST_FLAG(pMacEntry, fCLIENT_STATUS_WMM_CAPABLE)))) { /* legacy Ralink Aggregation support */
- return TRUE;
- }
-#endif /* AGGREGATION_SUPPORT // */
- }
-
- return FALSE;
-
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Check and fine the packet waiting in SW queue with highest priority
-
- Arguments:
- pAd Pointer to our adapter
-
- Return Value:
- pQueue Pointer to Waiting Queue
-
- IRQL = DISPATCH_LEVEL
-
- Note:
-
- ========================================================================
-*/
-struct rt_queue_header *RTMPCheckTxSwQueue(struct rt_rtmp_adapter *pAd, u8 *pQueIdx)
-{
-
- unsigned long Number;
- /* 2004-11-15 to be removed. test aggregation only */
-/* if ((OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_AGGREGATION_INUSED)) && (*pNumber < 2)) */
-/* return NULL; */
-
- Number = pAd->TxSwQueue[QID_AC_BK].Number
- + pAd->TxSwQueue[QID_AC_BE].Number
- + pAd->TxSwQueue[QID_AC_VI].Number
- + pAd->TxSwQueue[QID_AC_VO].Number;
-
- if (pAd->TxSwQueue[QID_AC_VO].Head != NULL) {
- *pQueIdx = QID_AC_VO;
- return (&pAd->TxSwQueue[QID_AC_VO]);
- } else if (pAd->TxSwQueue[QID_AC_VI].Head != NULL) {
- *pQueIdx = QID_AC_VI;
- return (&pAd->TxSwQueue[QID_AC_VI]);
- } else if (pAd->TxSwQueue[QID_AC_BE].Head != NULL) {
- *pQueIdx = QID_AC_BE;
- return (&pAd->TxSwQueue[QID_AC_BE]);
- } else if (pAd->TxSwQueue[QID_AC_BK].Head != NULL) {
- *pQueIdx = QID_AC_BK;
- return (&pAd->TxSwQueue[QID_AC_BK]);
- }
- /* No packet pending in Tx Sw queue */
- *pQueIdx = QID_AC_BK;
-
- return (NULL);
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Suspend MSDU transmission
-
- Arguments:
- pAd Pointer to our adapter
-
- Return Value:
- None
-
- Note:
-
- ========================================================================
-*/
-void RTMPSuspendMsduTransmission(struct rt_rtmp_adapter *pAd)
-{
- DBGPRINT(RT_DEBUG_TRACE, ("SCANNING, suspend MSDU transmission ...\n"));
-
- /* */
- /* Before BSS_SCAN_IN_PROGRESS, we need to keep Current R66 value and */
- /* use Lowbound as R66 value on ScanNextChannel(...) */
- /* */
- RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R66,
- &pAd->BbpTuning.R66CurrentValue);
-
- /* set BBP_R66 to 0x30/0x40 when scanning (AsicSwitchChannel will set R66 according to channel when scanning) */
- /*RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, (0x26 + GET_LNA_GAIN(pAd))); */
- RTMPSetAGCInitValue(pAd, BW_20);
-
- RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_BSS_SCAN_IN_PROGRESS);
- /*RTMP_IO_WRITE32(pAd, TX_CNTL_CSR, 0x000f0000); // abort all TX rings */
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Resume MSDU transmission
-
- Arguments:
- pAd Pointer to our adapter
-
- Return Value:
- None
-
- IRQL = DISPATCH_LEVEL
-
- Note:
-
- ========================================================================
-*/
-void RTMPResumeMsduTransmission(struct rt_rtmp_adapter *pAd)
-{
-/* u8 IrqState; */
-
- DBGPRINT(RT_DEBUG_TRACE, ("SCAN done, resume MSDU transmission ...\n"));
-
- /* After finish BSS_SCAN_IN_PROGRESS, we need to restore Current R66 value */
- /* R66 should not be 0 */
- if (pAd->BbpTuning.R66CurrentValue == 0) {
- pAd->BbpTuning.R66CurrentValue = 0x38;
- DBGPRINT_ERR("RTMPResumeMsduTransmission, R66CurrentValue=0...\n");
- }
-
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66,
- pAd->BbpTuning.R66CurrentValue);
-
- RTMP_CLEAR_FLAG(pAd, fRTMP_ADAPTER_BSS_SCAN_IN_PROGRESS);
-/* sample, for IRQ LOCK to SEM LOCK */
-/* IrqState = pAd->irq_disabled; */
-/* if (IrqState) */
-/* RTMPDeQueuePacket(pAd, TRUE, NUM_OF_TX_RING, MAX_TX_PROCESS); */
-/* else */
- RTMPDeQueuePacket(pAd, FALSE, NUM_OF_TX_RING, MAX_TX_PROCESS);
-}
-
-u32 deaggregate_AMSDU_announce(struct rt_rtmp_adapter *pAd,
- void *pPacket,
- u8 *pData, unsigned long DataSize)
-{
- u16 PayloadSize;
- u16 SubFrameSize;
- struct rt_header_802_3 * pAMSDUsubheader;
- u32 nMSDU;
- u8 Header802_3[14];
-
- u8 *pPayload, *pDA, *pSA, *pRemovedLLCSNAP;
- void *pClonePacket;
-
- nMSDU = 0;
-
- while (DataSize > LENGTH_802_3) {
-
- nMSDU++;
-
- /*hex_dump("subheader", pData, 64); */
- pAMSDUsubheader = (struct rt_header_802_3 *) pData;
- /*pData += LENGTH_802_3; */
- PayloadSize =
- pAMSDUsubheader->Octet[1] +
- (pAMSDUsubheader->Octet[0] << 8);
- SubFrameSize = PayloadSize + LENGTH_802_3;
-
- if ((DataSize < SubFrameSize) || (PayloadSize > 1518)) {
- break;
- }
- /*DBGPRINT(RT_DEBUG_TRACE,("%d subframe: Size = %d\n", nMSDU, PayloadSize)); */
-
- pPayload = pData + LENGTH_802_3;
- pDA = pData;
- pSA = pData + MAC_ADDR_LEN;
-
- /* convert to 802.3 header */
- CONVERT_TO_802_3(Header802_3, pDA, pSA, pPayload, PayloadSize,
- pRemovedLLCSNAP);
-
- if ((Header802_3[12] == 0x88) && (Header802_3[13] == 0x8E)) {
- /* avoid local heap overflow, use dyanamic allocation */
- struct rt_mlme_queue_elem *Elem =
- kmalloc(sizeof(struct rt_mlme_queue_elem),
- MEM_ALLOC_FLAG);
- if (Elem != NULL) {
- memmove(Elem->Msg +
- (LENGTH_802_11 + LENGTH_802_1_H),
- pPayload, PayloadSize);
- Elem->MsgLen =
- LENGTH_802_11 + LENGTH_802_1_H +
- PayloadSize;
- /*WpaEAPOLKeyAction(pAd, Elem); */
- REPORT_MGMT_FRAME_TO_MLME(pAd, BSSID_WCID,
- Elem->Msg,
- Elem->MsgLen, 0, 0, 0,
- 0);
- kfree(Elem);
- }
- }
-
- {
- if (pRemovedLLCSNAP) {
- pPayload -= LENGTH_802_3;
- PayloadSize += LENGTH_802_3;
- NdisMoveMemory(pPayload, &Header802_3[0],
- LENGTH_802_3);
- }
- }
-
- pClonePacket = ClonePacket(pAd, pPacket, pPayload, PayloadSize);
- if (pClonePacket) {
- ANNOUNCE_OR_FORWARD_802_3_PACKET(pAd, pClonePacket,
- RTMP_GET_PACKET_IF
- (pPacket));
- }
-
- /* A-MSDU has padding to multiple of 4 including subframe header. */
- /* align SubFrameSize up to multiple of 4 */
- SubFrameSize = (SubFrameSize + 3) & (~0x3);
-
- if (SubFrameSize > 1528 || SubFrameSize < 32) {
- break;
- }
-
- if (DataSize > SubFrameSize) {
- pData += SubFrameSize;
- DataSize -= SubFrameSize;
- } else {
- /* end of A-MSDU */
- DataSize = 0;
- }
- }
-
- /* finally release original rx packet */
- RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_SUCCESS);
-
- return nMSDU;
-}
-
-u32 BA_Reorder_AMSDU_Announce(struct rt_rtmp_adapter *pAd, void *pPacket)
-{
- u8 *pData;
- u16 DataSize;
- u32 nMSDU = 0;
-
- pData = (u8 *)GET_OS_PKT_DATAPTR(pPacket);
- DataSize = (u16)GET_OS_PKT_LEN(pPacket);
-
- nMSDU = deaggregate_AMSDU_announce(pAd, pPacket, pData, DataSize);
-
- return nMSDU;
-}
-
-/*
- ==========================================================================
- Description:
- Look up the MAC address in the MAC table. Return NULL if not found.
- Return:
- pEntry - pointer to the MAC entry; NULL is not found
- ==========================================================================
-*/
-struct rt_mac_table_entry *MacTableLookup(struct rt_rtmp_adapter *pAd, u8 *pAddr)
-{
- unsigned long HashIdx;
- struct rt_mac_table_entry *pEntry = NULL;
-
- HashIdx = MAC_ADDR_HASH_INDEX(pAddr);
- pEntry = pAd->MacTab.Hash[HashIdx];
-
- while (pEntry
- && (pEntry->ValidAsCLI || pEntry->ValidAsWDS
- || pEntry->ValidAsApCli || pEntry->ValidAsMesh)) {
- if (MAC_ADDR_EQUAL(pEntry->Addr, pAddr)) {
- break;
- } else
- pEntry = pEntry->pNext;
- }
-
- return pEntry;
-}
-
-struct rt_mac_table_entry *MacTableInsertEntry(struct rt_rtmp_adapter *pAd,
- u8 *pAddr,
- u8 apidx, IN BOOLEAN CleanAll)
-{
- u8 HashIdx;
- int i, FirstWcid;
- struct rt_mac_table_entry *pEntry = NULL, *pCurrEntry;
-/* u16 offset; */
-/* unsigned long addr; */
-
- /* if FULL, return */
- if (pAd->MacTab.Size >= MAX_LEN_OF_MAC_TABLE)
- return NULL;
-
- FirstWcid = 1;
-
- if (pAd->StaCfg.BssType == BSS_INFRA)
- FirstWcid = 2;
-
- /* allocate one MAC entry */
- NdisAcquireSpinLock(&pAd->MacTabLock);
- for (i = FirstWcid; i < MAX_LEN_OF_MAC_TABLE; i++) /* skip entry#0 so that "entry index == AID" for fast lookup */
- {
- /* pick up the first available vacancy */
- if ((pAd->MacTab.Content[i].ValidAsCLI == FALSE) &&
- (pAd->MacTab.Content[i].ValidAsWDS == FALSE) &&
- (pAd->MacTab.Content[i].ValidAsApCli == FALSE) &&
- (pAd->MacTab.Content[i].ValidAsMesh == FALSE)
- ) {
- pEntry = &pAd->MacTab.Content[i];
- if (CleanAll == TRUE) {
- pEntry->MaxSupportedRate = RATE_11;
- pEntry->CurrTxRate = RATE_11;
- NdisZeroMemory(pEntry, sizeof(struct rt_mac_table_entry));
- pEntry->PairwiseKey.KeyLen = 0;
- pEntry->PairwiseKey.CipherAlg = CIPHER_NONE;
- }
- {
- {
- pEntry->ValidAsCLI = TRUE;
- pEntry->ValidAsWDS = FALSE;
- pEntry->ValidAsApCli = FALSE;
- pEntry->ValidAsMesh = FALSE;
- pEntry->ValidAsDls = FALSE;
- }
- }
-
- pEntry->bIAmBadAtheros = FALSE;
- pEntry->pAd = pAd;
- pEntry->CMTimerRunning = FALSE;
- pEntry->EnqueueEapolStartTimerRunning =
- EAPOL_START_DISABLE;
- pEntry->RSNIE_Len = 0;
- NdisZeroMemory(pEntry->R_Counter,
- sizeof(pEntry->R_Counter));
- pEntry->ReTryCounter = PEER_MSG1_RETRY_TIMER_CTR;
-
- if (pEntry->ValidAsMesh)
- pEntry->apidx =
- (apidx - MIN_NET_DEVICE_FOR_MESH);
- else if (pEntry->ValidAsApCli)
- pEntry->apidx =
- (apidx - MIN_NET_DEVICE_FOR_APCLI);
- else if (pEntry->ValidAsWDS)
- pEntry->apidx =
- (apidx - MIN_NET_DEVICE_FOR_WDS);
- else
- pEntry->apidx = apidx;
-
- {
- {
- pEntry->AuthMode = pAd->StaCfg.AuthMode;
- pEntry->WepStatus =
- pAd->StaCfg.WepStatus;
- pEntry->PrivacyFilter =
- Ndis802_11PrivFilterAcceptAll;
-#ifdef RTMP_MAC_PCI
- AsicRemovePairwiseKeyEntry(pAd,
- pEntry->
- apidx,
- (u8)i);
-#endif /* RTMP_MAC_PCI // */
- }
- }
-
- pEntry->GTKState = REKEY_NEGOTIATING;
- pEntry->PairwiseKey.KeyLen = 0;
- pEntry->PairwiseKey.CipherAlg = CIPHER_NONE;
- pEntry->PortSecured = WPA_802_1X_PORT_NOT_SECURED;
-
- pEntry->PMKID_CacheIdx = ENTRY_NOT_FOUND;
- COPY_MAC_ADDR(pEntry->Addr, pAddr);
- pEntry->Sst = SST_NOT_AUTH;
- pEntry->AuthState = AS_NOT_AUTH;
- pEntry->Aid = (u16)i; /*0; */
- pEntry->CapabilityInfo = 0;
- pEntry->PsMode = PWR_ACTIVE;
- pEntry->PsQIdleCount = 0;
- pEntry->NoDataIdleCount = 0;
- pEntry->AssocDeadLine = MAC_TABLE_ASSOC_TIMEOUT;
- pEntry->ContinueTxFailCnt = 0;
- InitializeQueueHeader(&pEntry->PsQueue);
-
- pAd->MacTab.Size++;
- /* Add this entry into ASIC RX WCID search table */
- RTMP_STA_ENTRY_ADD(pAd, pEntry);
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("MacTableInsertEntry - allocate entry #%d, Total= %d\n",
- i, pAd->MacTab.Size));
- break;
- }
- }
-
- /* add this MAC entry into HASH table */
- if (pEntry) {
- HashIdx = MAC_ADDR_HASH_INDEX(pAddr);
- if (pAd->MacTab.Hash[HashIdx] == NULL) {
- pAd->MacTab.Hash[HashIdx] = pEntry;
- } else {
- pCurrEntry = pAd->MacTab.Hash[HashIdx];
- while (pCurrEntry->pNext != NULL)
- pCurrEntry = pCurrEntry->pNext;
- pCurrEntry->pNext = pEntry;
- }
- }
-
- NdisReleaseSpinLock(&pAd->MacTabLock);
- return pEntry;
-}
-
-/*
- ==========================================================================
- Description:
- Delete a specified client from MAC table
- ==========================================================================
- */
-BOOLEAN MacTableDeleteEntry(struct rt_rtmp_adapter *pAd,
- u16 wcid, u8 *pAddr)
-{
- u16 HashIdx;
- struct rt_mac_table_entry *pEntry, *pPrevEntry, *pProbeEntry;
- BOOLEAN Cancelled;
- /*u16 offset; // unused variable */
- /*u8 j; // unused variable */
-
- if (wcid >= MAX_LEN_OF_MAC_TABLE)
- return FALSE;
-
- NdisAcquireSpinLock(&pAd->MacTabLock);
-
- HashIdx = MAC_ADDR_HASH_INDEX(pAddr);
- /*pEntry = pAd->MacTab.Hash[HashIdx]; */
- pEntry = &pAd->MacTab.Content[wcid];
-
- if (pEntry
- && (pEntry->ValidAsCLI || pEntry->ValidAsApCli || pEntry->ValidAsWDS
- || pEntry->ValidAsMesh)) {
- if (MAC_ADDR_EQUAL(pEntry->Addr, pAddr)) {
-
- /* Delete this entry from ASIC on-chip WCID Table */
- RTMP_STA_ENTRY_MAC_RESET(pAd, wcid);
-
- /* free resources of BA */
- BASessionTearDownALL(pAd, pEntry->Aid);
-
- pPrevEntry = NULL;
- pProbeEntry = pAd->MacTab.Hash[HashIdx];
- ASSERT(pProbeEntry);
-
- /* update Hash list */
- do {
- if (pProbeEntry == pEntry) {
- if (pPrevEntry == NULL) {
- pAd->MacTab.Hash[HashIdx] =
- pEntry->pNext;
- } else {
- pPrevEntry->pNext =
- pEntry->pNext;
- }
- break;
- }
-
- pPrevEntry = pProbeEntry;
- pProbeEntry = pProbeEntry->pNext;
- } while (pProbeEntry);
-
- /* not found ! */
- ASSERT(pProbeEntry != NULL);
-
- RTMP_STA_ENTRY_KEY_DEL(pAd, BSS0, wcid);
-
- if (pEntry->EnqueueEapolStartTimerRunning !=
- EAPOL_START_DISABLE) {
- RTMPCancelTimer(&pEntry->
- EnqueueStartForPSKTimer,
- &Cancelled);
- pEntry->EnqueueEapolStartTimerRunning =
- EAPOL_START_DISABLE;
- }
-
- NdisZeroMemory(pEntry, sizeof(struct rt_mac_table_entry));
- pAd->MacTab.Size--;
- DBGPRINT(RT_DEBUG_TRACE,
- ("MacTableDeleteEntry1 - Total= %d\n",
- pAd->MacTab.Size));
- } else {
- DBGPRINT(RT_DEBUG_OFF,
- ("\n%s: Impossible Wcid = %d !\n",
- __func__, wcid));
- }
- }
-
- NdisReleaseSpinLock(&pAd->MacTabLock);
-
- /*Reset operating mode when no Sta. */
- if (pAd->MacTab.Size == 0) {
- pAd->CommonCfg.AddHTInfo.AddHtInfo2.OperaionMode = 0;
- RTMP_UPDATE_PROTECT(pAd); /* edit by johnli, fix "in_interrupt" error when call "MacTableDeleteEntry" in Rx tasklet */
- }
-
- return TRUE;
-}
-
-/*
- ==========================================================================
- Description:
- This routine reset the entire MAC table. All packets pending in
- the power-saving queues are freed here.
- ==========================================================================
- */
-void MacTableReset(struct rt_rtmp_adapter *pAd)
-{
- int i;
-
- DBGPRINT(RT_DEBUG_TRACE, ("MacTableReset\n"));
- /*NdisAcquireSpinLock(&pAd->MacTabLock); */
-
- for (i = 1; i < MAX_LEN_OF_MAC_TABLE; i++) {
-#ifdef RTMP_MAC_PCI
- RTMP_STA_ENTRY_MAC_RESET(pAd, i);
-#endif /* RTMP_MAC_PCI // */
- if (pAd->MacTab.Content[i].ValidAsCLI == TRUE) {
-
- /* free resources of BA */
- BASessionTearDownALL(pAd, i);
-
- pAd->MacTab.Content[i].ValidAsCLI = FALSE;
-
-#ifdef RTMP_MAC_USB
- NdisZeroMemory(pAd->MacTab.Content[i].Addr, 6);
- RTMP_STA_ENTRY_MAC_RESET(pAd, i);
-#endif /* RTMP_MAC_USB // */
-
- /*AsicDelWcidTab(pAd, i); */
- }
- }
-
- return;
-}
-
-/*
- ==========================================================================
- Description:
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
-*/
-void AssocParmFill(struct rt_rtmp_adapter *pAd,
- struct rt_mlme_assoc_req *AssocReq,
- u8 *pAddr,
- u16 CapabilityInfo,
- unsigned long Timeout, u16 ListenIntv)
-{
- COPY_MAC_ADDR(AssocReq->Addr, pAddr);
- /* Add mask to support 802.11b mode only */
- AssocReq->CapabilityInfo = CapabilityInfo & SUPPORTED_CAPABILITY_INFO; /* not cf-pollable, not cf-poll-request */
- AssocReq->Timeout = Timeout;
- AssocReq->ListenIntv = ListenIntv;
-}
-
-/*
- ==========================================================================
- Description:
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
-*/
-void DisassocParmFill(struct rt_rtmp_adapter *pAd,
- struct rt_mlme_disassoc_req *DisassocReq,
- u8 *pAddr, u16 Reason)
-{
- COPY_MAC_ADDR(DisassocReq->Addr, pAddr);
- DisassocReq->Reason = Reason;
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Check the out going frame, if this is an DHCP or ARP datagram
- will be duplicate another frame at low data rate transmit.
-
- Arguments:
- pAd Pointer to our adapter
- pPacket Pointer to outgoing Ndis frame
-
- Return Value:
- TRUE To be duplicate at Low data rate transmit. (1mb)
- FALSE Do nothing.
-
- IRQL = DISPATCH_LEVEL
-
- Note:
-
- MAC header + IP Header + UDP Header
- 14 Bytes 20 Bytes
-
- UDP Header
- 00|01|02|03|04|05|06|07|08|09|10|11|12|13|14|15|
- Source Port
- 16|17|18|19|20|21|22|23|24|25|26|27|28|29|30|31|
- Destination Port
-
- port 0x43 means Bootstrap Protocol, server.
- Port 0x44 means Bootstrap Protocol, client.
-
- ========================================================================
-*/
-
-BOOLEAN RTMPCheckDHCPFrame(struct rt_rtmp_adapter *pAd, void *pPacket)
-{
- struct rt_packet_info PacketInfo;
- unsigned long NumberOfBytesRead = 0;
- unsigned long CurrentOffset = 0;
- void *pVirtualAddress = NULL;
- u32 NdisBufferLength;
- u8 *pSrc;
- u16 Protocol;
- u8 ByteOffset36 = 0;
- u8 ByteOffset38 = 0;
- BOOLEAN ReadFirstParm = TRUE;
-
- RTMP_QueryPacketInfo(pPacket, &PacketInfo, (u8 **) & pVirtualAddress,
- &NdisBufferLength);
-
- NumberOfBytesRead += NdisBufferLength;
- pSrc = (u8 *)pVirtualAddress;
- Protocol = *(pSrc + 12) * 256 + *(pSrc + 13);
-
- /* */
- /* Check DHCP & BOOTP protocol */
- /* */
- while (NumberOfBytesRead <= PacketInfo.TotalPacketLength) {
- if ((NumberOfBytesRead >= 35) && (ReadFirstParm == TRUE)) {
- CurrentOffset =
- 35 - (NumberOfBytesRead - NdisBufferLength);
- ByteOffset36 = *(pSrc + CurrentOffset);
- ReadFirstParm = FALSE;
- }
-
- if (NumberOfBytesRead >= 37) {
- CurrentOffset =
- 37 - (NumberOfBytesRead - NdisBufferLength);
- ByteOffset38 = *(pSrc + CurrentOffset);
- /*End of Read */
- break;
- }
- return FALSE;
- }
-
- /* Check for DHCP & BOOTP protocol */
- if ((ByteOffset36 != 0x44) || (ByteOffset38 != 0x43)) {
- /* */
- /* 2054 (hex 0806) for ARP datagrams */
- /* if this packet is not ARP datagrams, then do nothing */
- /* ARP datagrams will also be duplicate at 1mb broadcast frames */
- /* */
- if (Protocol != 0x0806)
- return FALSE;
- }
-
- return TRUE;
-}
-
-BOOLEAN RTMPCheckEtherType(struct rt_rtmp_adapter *pAd, void *pPacket)
-{
- u16 TypeLen;
- u8 Byte0, Byte1;
- u8 *pSrcBuf;
- u32 pktLen;
- u16 srcPort, dstPort;
- BOOLEAN status = TRUE;
-
- pSrcBuf = GET_OS_PKT_DATAPTR(pPacket);
- pktLen = GET_OS_PKT_LEN(pPacket);
-
- ASSERT(pSrcBuf);
-
- RTMP_SET_PACKET_SPECIFIC(pPacket, 0);
-
- /* get Ethernet protocol field */
- TypeLen = (pSrcBuf[12] << 8) | pSrcBuf[13];
-
- pSrcBuf += LENGTH_802_3; /* Skip the Ethernet Header. */
-
- if (TypeLen <= 1500) { /* 802.3, 802.3 LLC */
- /*
- DestMAC(6) + SrcMAC(6) + Length(2) +
- DSAP(1) + SSAP(1) + Control(1) +
- if the DSAP = 0xAA, SSAP=0xAA, Contorl = 0x03, it has a 5-bytes SNAP header.
- => + SNAP (5, OriginationID(3) + etherType(2))
- */
- if (pSrcBuf[0] == 0xAA && pSrcBuf[1] == 0xAA
- && pSrcBuf[2] == 0x03) {
- Sniff2BytesFromNdisBuffer((char *)pSrcBuf, 6,
- &Byte0, &Byte1);
- RTMP_SET_PACKET_LLCSNAP(pPacket, 1);
- TypeLen = (u16)((Byte0 << 8) + Byte1);
- pSrcBuf += 8; /* Skip this LLC/SNAP header */
- } else {
- /*It just has 3-byte LLC header, maybe a legacy ether type frame. we didn't handle it. */
- }
- }
- /* If it's a VLAN packet, get the real Type/Length field. */
- if (TypeLen == 0x8100) {
- /* 0x8100 means VLAN packets */
-
- /* Dest. MAC Address (6-bytes) +
- Source MAC Address (6-bytes) +
- Length/Type = 802.1Q Tag Type (2-byte) +
- Tag Control Information (2-bytes) +
- Length / Type (2-bytes) +
- data payload (0-n bytes) +
- Pad (0-p bytes) +
- Frame Check Sequence (4-bytes) */
-
- RTMP_SET_PACKET_VLAN(pPacket, 1);
- Sniff2BytesFromNdisBuffer((char *)pSrcBuf, 2, &Byte0,
- &Byte1);
- TypeLen = (u16)((Byte0 << 8) + Byte1);
-
- pSrcBuf += 4; /* Skip the VLAN Header. */
- }
-
- switch (TypeLen) {
- case 0x0800:
- {
- ASSERT((pktLen > 34));
- if (*(pSrcBuf + 9) == 0x11) { /* udp packet */
- ASSERT((pktLen > 34)); /* 14 for ethernet header, 20 for IP header */
-
- pSrcBuf += 20; /* Skip the IP header */
- srcPort =
- OS_NTOHS(get_unaligned
- ((u16 *)(pSrcBuf)));
- dstPort =
- OS_NTOHS(get_unaligned
- ((u16 *)(pSrcBuf + 2)));
-
- if ((srcPort == 0x44 && dstPort == 0x43) || (srcPort == 0x43 && dstPort == 0x44)) { /*It's a BOOTP/DHCP packet */
- RTMP_SET_PACKET_DHCP(pPacket, 1);
- }
- }
- }
- break;
- case 0x0806:
- {
- /*ARP Packet. */
- RTMP_SET_PACKET_DHCP(pPacket, 1);
- }
- break;
- case 0x888e:
- {
- /* EAPOL Packet. */
- RTMP_SET_PACKET_EAPOL(pPacket, 1);
- }
- break;
- default:
- status = FALSE;
- break;
- }
-
- return status;
-
-}
-
-void Update_Rssi_Sample(struct rt_rtmp_adapter *pAd,
- struct rt_rssi_sample *pRssi, struct rt_rxwi * pRxWI)
-{
- char rssi0 = pRxWI->RSSI0;
- char rssi1 = pRxWI->RSSI1;
- char rssi2 = pRxWI->RSSI2;
-
- if (rssi0 != 0) {
- pRssi->LastRssi0 = ConvertToRssi(pAd, (char)rssi0, RSSI_0);
- pRssi->AvgRssi0X8 =
- (pRssi->AvgRssi0X8 - pRssi->AvgRssi0) + pRssi->LastRssi0;
- pRssi->AvgRssi0 = pRssi->AvgRssi0X8 >> 3;
- }
-
- if (rssi1 != 0) {
- pRssi->LastRssi1 = ConvertToRssi(pAd, (char)rssi1, RSSI_1);
- pRssi->AvgRssi1X8 =
- (pRssi->AvgRssi1X8 - pRssi->AvgRssi1) + pRssi->LastRssi1;
- pRssi->AvgRssi1 = pRssi->AvgRssi1X8 >> 3;
- }
-
- if (rssi2 != 0) {
- pRssi->LastRssi2 = ConvertToRssi(pAd, (char)rssi2, RSSI_2);
- pRssi->AvgRssi2X8 =
- (pRssi->AvgRssi2X8 - pRssi->AvgRssi2) + pRssi->LastRssi2;
- pRssi->AvgRssi2 = pRssi->AvgRssi2X8 >> 3;
- }
-}
-
-/* Normal legacy Rx packet indication */
-void Indicate_Legacy_Packet(struct rt_rtmp_adapter *pAd,
- struct rt_rx_blk *pRxBlk, u8 FromWhichBSSID)
-{
- void *pRxPacket = pRxBlk->pRxPacket;
- u8 Header802_3[LENGTH_802_3];
-
- /* 1. get 802.3 Header */
- /* 2. remove LLC */
- /* a. pointer pRxBlk->pData to payload */
- /* b. modify pRxBlk->DataSize */
- RTMP_802_11_REMOVE_LLC_AND_CONVERT_TO_802_3(pRxBlk, Header802_3);
-
- if (pRxBlk->DataSize > MAX_RX_PKT_LEN) {
-
- /* release packet */
- RELEASE_NDIS_PACKET(pAd, pRxPacket, NDIS_STATUS_FAILURE);
- return;
- }
-
- STATS_INC_RX_PACKETS(pAd, FromWhichBSSID);
-
-#ifdef RTMP_MAC_USB
- if (pAd->CommonCfg.bDisableReordering == 0) {
- struct rt_ba_rec_entry *pBAEntry;
- unsigned long Now32;
- u8 Wcid = pRxBlk->pRxWI->WirelessCliID;
- u8 TID = pRxBlk->pRxWI->TID;
- u16 Idx;
-
-#define REORDERING_PACKET_TIMEOUT ((100 * OS_HZ)/1000) /* system ticks -- 100 ms */
-
- if (Wcid < MAX_LEN_OF_MAC_TABLE) {
- Idx = pAd->MacTab.Content[Wcid].BARecWcidArray[TID];
- if (Idx != 0) {
- pBAEntry = &pAd->BATable.BARecEntry[Idx];
- /* update last rx time */
- NdisGetSystemUpTime(&Now32);
- if ((pBAEntry->list.qlen > 0) &&
- RTMP_TIME_AFTER((unsigned long)Now32,
- (unsigned long)(pBAEntry->
- LastIndSeqAtTimer
- +
- (REORDERING_PACKET_TIMEOUT)))
- ) {
- DBGPRINT(RT_DEBUG_OFF,
- ("Indicate_Legacy_Packet():flush reordering_timeout_mpdus! RxWI->Flags=%d, pRxWI.TID=%d, RxD->AMPDU=%d!\n",
- pRxBlk->Flags,
- pRxBlk->pRxWI->TID,
- pRxBlk->RxD.AMPDU));
- hex_dump("Dump the legacy Packet:",
- GET_OS_PKT_DATAPTR(pRxBlk->
- pRxPacket),
- 64);
- ba_flush_reordering_timeout_mpdus(pAd,
- pBAEntry,
- Now32);
- }
- }
- }
- }
-#endif /* RTMP_MAC_USB // */
-
- wlan_802_11_to_802_3_packet(pAd, pRxBlk, Header802_3, FromWhichBSSID);
-
- /* */
- /* pass this 802.3 packet to upper layer or forward this packet to WM directly */
- /* */
- ANNOUNCE_OR_FORWARD_802_3_PACKET(pAd, pRxPacket, FromWhichBSSID);
-}
-
-/* Normal, AMPDU or AMSDU */
-void CmmRxnonRalinkFrameIndicate(struct rt_rtmp_adapter *pAd,
- struct rt_rx_blk *pRxBlk, u8 FromWhichBSSID)
-{
- if (RX_BLK_TEST_FLAG(pRxBlk, fRX_AMPDU)
- && (pAd->CommonCfg.bDisableReordering == 0)) {
- Indicate_AMPDU_Packet(pAd, pRxBlk, FromWhichBSSID);
- } else {
- if (RX_BLK_TEST_FLAG(pRxBlk, fRX_AMSDU)) {
- /* handle A-MSDU */
- Indicate_AMSDU_Packet(pAd, pRxBlk, FromWhichBSSID);
- } else {
- Indicate_Legacy_Packet(pAd, pRxBlk, FromWhichBSSID);
- }
- }
-}
-
-void CmmRxRalinkFrameIndicate(struct rt_rtmp_adapter *pAd,
- struct rt_mac_table_entry *pEntry,
- struct rt_rx_blk *pRxBlk, u8 FromWhichBSSID)
-{
- u8 Header802_3[LENGTH_802_3];
- u16 Msdu2Size;
- u16 Payload1Size, Payload2Size;
- u8 *pData2;
- void *pPacket2 = NULL;
-
- Msdu2Size = *(pRxBlk->pData) + (*(pRxBlk->pData + 1) << 8);
-
- if ((Msdu2Size <= 1536) && (Msdu2Size < pRxBlk->DataSize)) {
- /* skip two byte MSDU2 len */
- pRxBlk->pData += 2;
- pRxBlk->DataSize -= 2;
- } else {
- /* release packet */
- RELEASE_NDIS_PACKET(pAd, pRxBlk->pRxPacket,
- NDIS_STATUS_FAILURE);
- return;
- }
-
- /* get 802.3 Header and remove LLC */
- RTMP_802_11_REMOVE_LLC_AND_CONVERT_TO_802_3(pRxBlk, Header802_3);
-
- ASSERT(pRxBlk->pRxPacket);
-
- /* Ralink Aggregation frame */
- pAd->RalinkCounters.OneSecRxAggregationCount++;
- Payload1Size = pRxBlk->DataSize - Msdu2Size;
- Payload2Size = Msdu2Size - LENGTH_802_3;
-
- pData2 = pRxBlk->pData + Payload1Size + LENGTH_802_3;
-
- pPacket2 =
- duplicate_pkt(pAd, (pData2 - LENGTH_802_3), LENGTH_802_3, pData2,
- Payload2Size, FromWhichBSSID);
-
- if (!pPacket2) {
- /* release packet */
- RELEASE_NDIS_PACKET(pAd, pRxBlk->pRxPacket,
- NDIS_STATUS_FAILURE);
- return;
- }
- /* update payload size of 1st packet */
- pRxBlk->DataSize = Payload1Size;
- wlan_802_11_to_802_3_packet(pAd, pRxBlk, Header802_3, FromWhichBSSID);
-
- ANNOUNCE_OR_FORWARD_802_3_PACKET(pAd, pRxBlk->pRxPacket,
- FromWhichBSSID);
-
- if (pPacket2) {
- ANNOUNCE_OR_FORWARD_802_3_PACKET(pAd, pPacket2, FromWhichBSSID);
- }
-}
-
-#define RESET_FRAGFRAME(_fragFrame) \
- { \
- _fragFrame.RxSize = 0; \
- _fragFrame.Sequence = 0; \
- _fragFrame.LastFrag = 0; \
- _fragFrame.Flags = 0; \
- }
-
-void *RTMPDeFragmentDataFrame(struct rt_rtmp_adapter *pAd, struct rt_rx_blk *pRxBlk)
-{
- struct rt_header_802_11 * pHeader = pRxBlk->pHeader;
- void *pRxPacket = pRxBlk->pRxPacket;
- u8 *pData = pRxBlk->pData;
- u16 DataSize = pRxBlk->DataSize;
- void *pRetPacket = NULL;
- u8 *pFragBuffer = NULL;
- BOOLEAN bReassDone = FALSE;
- u8 HeaderRoom = 0;
-
- ASSERT(pHeader);
-
- HeaderRoom = pData - (u8 *) pHeader;
-
- /* Re-assemble the fragmented packets */
- if (pHeader->Frag == 0) /* Frag. Number is 0 : First frag or only one pkt */
- {
- /* the first pkt of fragment, record it. */
- if (pHeader->FC.MoreFrag) {
- ASSERT(pAd->FragFrame.pFragPacket);
- pFragBuffer =
- GET_OS_PKT_DATAPTR(pAd->FragFrame.pFragPacket);
- pAd->FragFrame.RxSize = DataSize + HeaderRoom;
- NdisMoveMemory(pFragBuffer, pHeader,
- pAd->FragFrame.RxSize);
- pAd->FragFrame.Sequence = pHeader->Sequence;
- pAd->FragFrame.LastFrag = pHeader->Frag; /* Should be 0 */
- ASSERT(pAd->FragFrame.LastFrag == 0);
- goto done; /* end of processing this frame */
- }
- } else /*Middle & End of fragment */
- {
- if ((pHeader->Sequence != pAd->FragFrame.Sequence) ||
- (pHeader->Frag != (pAd->FragFrame.LastFrag + 1))) {
- /* Fragment is not the same sequence or out of fragment number order */
- /* Reset Fragment control blk */
- RESET_FRAGFRAME(pAd->FragFrame);
- DBGPRINT(RT_DEBUG_ERROR,
- ("Fragment is not the same sequence or out of fragment number order.\n"));
- goto done; /* give up this frame */
- } else if ((pAd->FragFrame.RxSize + DataSize) > MAX_FRAME_SIZE) {
- /* Fragment frame is too large, it exeeds the maximum frame size. */
- /* Reset Fragment control blk */
- RESET_FRAGFRAME(pAd->FragFrame);
- DBGPRINT(RT_DEBUG_ERROR,
- ("Fragment frame is too large, it exeeds the maximum frame size.\n"));
- goto done; /* give up this frame */
- }
- /* */
- /* Broadcom AP(BCM94704AGR) will send out LLC in fragment's packet, LLC only can accpet at first fragment. */
- /* In this case, we will dropt it. */
- /* */
- if (NdisEqualMemory(pData, SNAP_802_1H, sizeof(SNAP_802_1H))) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("Find another LLC at Middle or End fragment(SN=%d, Frag=%d)\n",
- pHeader->Sequence, pHeader->Frag));
- goto done; /* give up this frame */
- }
-
- pFragBuffer = GET_OS_PKT_DATAPTR(pAd->FragFrame.pFragPacket);
-
- /* concatenate this fragment into the re-assembly buffer */
- NdisMoveMemory((pFragBuffer + pAd->FragFrame.RxSize), pData,
- DataSize);
- pAd->FragFrame.RxSize += DataSize;
- pAd->FragFrame.LastFrag = pHeader->Frag; /* Update fragment number */
-
- /* Last fragment */
- if (pHeader->FC.MoreFrag == FALSE) {
- bReassDone = TRUE;
- }
- }
-
-done:
- /* always release rx fragmented packet */
- RELEASE_NDIS_PACKET(pAd, pRxPacket, NDIS_STATUS_FAILURE);
-
- /* return defragmented packet if packet is reassembled completely */
- /* otherwise return NULL */
- if (bReassDone) {
- void *pNewFragPacket;
-
- /* allocate a new packet buffer for fragment */
- pNewFragPacket =
- RTMP_AllocateFragPacketBuffer(pAd, RX_BUFFER_NORMSIZE);
- if (pNewFragPacket) {
- /* update RxBlk */
- pRetPacket = pAd->FragFrame.pFragPacket;
- pAd->FragFrame.pFragPacket = pNewFragPacket;
- pRxBlk->pHeader =
- (struct rt_header_802_11 *) GET_OS_PKT_DATAPTR(pRetPacket);
- pRxBlk->pData = (u8 *) pRxBlk->pHeader + HeaderRoom;
- pRxBlk->DataSize = pAd->FragFrame.RxSize - HeaderRoom;
- pRxBlk->pRxPacket = pRetPacket;
- } else {
- RESET_FRAGFRAME(pAd->FragFrame);
- }
- }
-
- return pRetPacket;
-}
-
-void Indicate_AMSDU_Packet(struct rt_rtmp_adapter *pAd,
- struct rt_rx_blk *pRxBlk, u8 FromWhichBSSID)
-{
- u32 nMSDU;
-
- update_os_packet_info(pAd, pRxBlk, FromWhichBSSID);
- RTMP_SET_PACKET_IF(pRxBlk->pRxPacket, FromWhichBSSID);
- nMSDU =
- deaggregate_AMSDU_announce(pAd, pRxBlk->pRxPacket, pRxBlk->pData,
- pRxBlk->DataSize);
-}
-
-void Indicate_EAPOL_Packet(struct rt_rtmp_adapter *pAd,
- struct rt_rx_blk *pRxBlk, u8 FromWhichBSSID)
-{
- struct rt_mac_table_entry *pEntry = NULL;
-
- {
- pEntry = &pAd->MacTab.Content[BSSID_WCID];
- STARxEAPOLFrameIndicate(pAd, pEntry, pRxBlk, FromWhichBSSID);
- return;
- }
-
- if (pEntry == NULL) {
- DBGPRINT(RT_DEBUG_WARN,
- ("Indicate_EAPOL_Packet: drop and release the invalid packet.\n"));
- /* release packet */
- RELEASE_NDIS_PACKET(pAd, pRxBlk->pRxPacket,
- NDIS_STATUS_FAILURE);
- return;
- }
-}
-
-#define BCN_TBTT_OFFSET 64 /*defer 64 us */
-void ReSyncBeaconTime(struct rt_rtmp_adapter *pAd)
-{
-
- u32 Offset;
-
- Offset = (pAd->TbttTickCount) % (BCN_TBTT_OFFSET);
-
- pAd->TbttTickCount++;
-
- /* */
- /* The updated BeaconInterval Value will affect Beacon Interval after two TBTT */
- /* beacasue the original BeaconInterval had been loaded into next TBTT_TIMER */
- /* */
- if (Offset == (BCN_TBTT_OFFSET - 2)) {
- BCN_TIME_CFG_STRUC csr;
- RTMP_IO_READ32(pAd, BCN_TIME_CFG, &csr.word);
- csr.field.BeaconInterval = (pAd->CommonCfg.BeaconPeriod << 4) - 1; /* ASIC register in units of 1/16 TU = 64us */
- RTMP_IO_WRITE32(pAd, BCN_TIME_CFG, csr.word);
- } else {
- if (Offset == (BCN_TBTT_OFFSET - 1)) {
- BCN_TIME_CFG_STRUC csr;
-
- RTMP_IO_READ32(pAd, BCN_TIME_CFG, &csr.word);
- csr.field.BeaconInterval = (pAd->CommonCfg.BeaconPeriod) << 4; /* ASIC register in units of 1/16 TU */
- RTMP_IO_WRITE32(pAd, BCN_TIME_CFG, csr.word);
- }
- }
-}
diff --git a/drivers/staging/rt2860/common/cmm_data_pci.c b/drivers/staging/rt2860/common/cmm_data_pci.c
deleted file mode 100644
index f01a51c..0000000
--- a/drivers/staging/rt2860/common/cmm_data_pci.c
+++ /dev/null
@@ -1,1096 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
- */
-
-/*
- All functions in this file must be PCI-depended, or you should out your function
- in other files.
-
-*/
-#include "../rt_config.h"
-
-u16 RtmpPCI_WriteTxResource(struct rt_rtmp_adapter *pAd,
- struct rt_tx_blk *pTxBlk,
- IN BOOLEAN bIsLast, u16 * FreeNumber)
-{
-
- u8 *pDMAHeaderBufVA;
- u16 TxIdx, RetTxIdx;
- struct rt_txd * pTxD;
- u32 BufBasePaLow;
- struct rt_rtmp_tx_ring *pTxRing;
- u16 hwHeaderLen;
-
- /* */
- /* get Tx Ring Resource */
- /* */
- pTxRing = &pAd->TxRing[pTxBlk->QueIdx];
- TxIdx = pAd->TxRing[pTxBlk->QueIdx].TxCpuIdx;
- pDMAHeaderBufVA = (u8 *)pTxRing->Cell[TxIdx].DmaBuf.AllocVa;
- BufBasePaLow =
- RTMP_GetPhysicalAddressLow(pTxRing->Cell[TxIdx].DmaBuf.AllocPa);
-
- /* copy TXINFO + TXWI + WLAN Header + LLC into DMA Header Buffer */
- if (pTxBlk->TxFrameType == TX_AMSDU_FRAME) {
- /*hwHeaderLen = ROUND_UP(pTxBlk->MpduHeaderLen-LENGTH_AMSDU_SUBFRAMEHEAD, 4)+LENGTH_AMSDU_SUBFRAMEHEAD; */
- hwHeaderLen =
- pTxBlk->MpduHeaderLen - LENGTH_AMSDU_SUBFRAMEHEAD +
- pTxBlk->HdrPadLen + LENGTH_AMSDU_SUBFRAMEHEAD;
- } else {
- /*hwHeaderLen = ROUND_UP(pTxBlk->MpduHeaderLen, 4); */
- hwHeaderLen = pTxBlk->MpduHeaderLen + pTxBlk->HdrPadLen;
- }
- NdisMoveMemory(pDMAHeaderBufVA, pTxBlk->HeaderBuf,
- TXINFO_SIZE + TXWI_SIZE + hwHeaderLen);
-
- pTxRing->Cell[TxIdx].pNdisPacket = pTxBlk->pPacket;
- pTxRing->Cell[TxIdx].pNextNdisPacket = NULL;
-
- /* */
- /* build Tx Descriptor */
- /* */
-
- pTxD = (struct rt_txd *) pTxRing->Cell[TxIdx].AllocVa;
- NdisZeroMemory(pTxD, TXD_SIZE);
-
- pTxD->SDPtr0 = BufBasePaLow;
- pTxD->SDLen0 = TXINFO_SIZE + TXWI_SIZE + hwHeaderLen; /* include padding */
- pTxD->SDPtr1 = PCI_MAP_SINGLE(pAd, pTxBlk, 0, 1, PCI_DMA_TODEVICE);
- pTxD->SDLen1 = pTxBlk->SrcBufLen;
- pTxD->LastSec0 = 0;
- pTxD->LastSec1 = (bIsLast) ? 1 : 0;
-
- RTMPWriteTxDescriptor(pAd, pTxD, FALSE, FIFO_EDCA);
-
- RetTxIdx = TxIdx;
- /* */
- /* Update Tx index */
- /* */
- INC_RING_INDEX(TxIdx, TX_RING_SIZE);
- pTxRing->TxCpuIdx = TxIdx;
-
- *FreeNumber -= 1;
-
- return RetTxIdx;
-}
-
-u16 RtmpPCI_WriteSingleTxResource(struct rt_rtmp_adapter *pAd,
- struct rt_tx_blk *pTxBlk,
- IN BOOLEAN bIsLast,
- u16 * FreeNumber)
-{
-
- u8 *pDMAHeaderBufVA;
- u16 TxIdx, RetTxIdx;
- struct rt_txd * pTxD;
- u32 BufBasePaLow;
- struct rt_rtmp_tx_ring *pTxRing;
- u16 hwHeaderLen;
-
- /* */
- /* get Tx Ring Resource */
- /* */
- pTxRing = &pAd->TxRing[pTxBlk->QueIdx];
- TxIdx = pAd->TxRing[pTxBlk->QueIdx].TxCpuIdx;
- pDMAHeaderBufVA = (u8 *)pTxRing->Cell[TxIdx].DmaBuf.AllocVa;
- BufBasePaLow =
- RTMP_GetPhysicalAddressLow(pTxRing->Cell[TxIdx].DmaBuf.AllocPa);
-
- /* copy TXINFO + TXWI + WLAN Header + LLC into DMA Header Buffer */
- /*hwHeaderLen = ROUND_UP(pTxBlk->MpduHeaderLen, 4); */
- hwHeaderLen = pTxBlk->MpduHeaderLen + pTxBlk->HdrPadLen;
-
- NdisMoveMemory(pDMAHeaderBufVA, pTxBlk->HeaderBuf,
- TXINFO_SIZE + TXWI_SIZE + hwHeaderLen);
-
- pTxRing->Cell[TxIdx].pNdisPacket = pTxBlk->pPacket;
- pTxRing->Cell[TxIdx].pNextNdisPacket = NULL;
-
- /* */
- /* build Tx Descriptor */
- /* */
- pTxD = (struct rt_txd *) pTxRing->Cell[TxIdx].AllocVa;
- NdisZeroMemory(pTxD, TXD_SIZE);
-
- pTxD->SDPtr0 = BufBasePaLow;
- pTxD->SDLen0 = TXINFO_SIZE + TXWI_SIZE + hwHeaderLen; /* include padding */
- pTxD->SDPtr1 = PCI_MAP_SINGLE(pAd, pTxBlk, 0, 1, PCI_DMA_TODEVICE);
- pTxD->SDLen1 = pTxBlk->SrcBufLen;
- pTxD->LastSec0 = 0;
- pTxD->LastSec1 = (bIsLast) ? 1 : 0;
-
- RTMPWriteTxDescriptor(pAd, pTxD, FALSE, FIFO_EDCA);
-
- RetTxIdx = TxIdx;
- /* */
- /* Update Tx index */
- /* */
- INC_RING_INDEX(TxIdx, TX_RING_SIZE);
- pTxRing->TxCpuIdx = TxIdx;
-
- *FreeNumber -= 1;
-
- return RetTxIdx;
-}
-
-u16 RtmpPCI_WriteMultiTxResource(struct rt_rtmp_adapter *pAd,
- struct rt_tx_blk *pTxBlk,
- u8 frameNum, u16 * FreeNumber)
-{
- BOOLEAN bIsLast;
- u8 *pDMAHeaderBufVA;
- u16 TxIdx, RetTxIdx;
- struct rt_txd * pTxD;
- u32 BufBasePaLow;
- struct rt_rtmp_tx_ring *pTxRing;
- u16 hwHdrLen;
- u32 firstDMALen;
-
- bIsLast = ((frameNum == (pTxBlk->TotalFrameNum - 1)) ? 1 : 0);
-
- /* */
- /* get Tx Ring Resource */
- /* */
- pTxRing = &pAd->TxRing[pTxBlk->QueIdx];
- TxIdx = pAd->TxRing[pTxBlk->QueIdx].TxCpuIdx;
- pDMAHeaderBufVA = (u8 *)pTxRing->Cell[TxIdx].DmaBuf.AllocVa;
- BufBasePaLow =
- RTMP_GetPhysicalAddressLow(pTxRing->Cell[TxIdx].DmaBuf.AllocPa);
-
- if (frameNum == 0) {
- /* copy TXINFO + TXWI + WLAN Header + LLC into DMA Header Buffer */
- if (pTxBlk->TxFrameType == TX_AMSDU_FRAME)
- /*hwHdrLen = ROUND_UP(pTxBlk->MpduHeaderLen-LENGTH_AMSDU_SUBFRAMEHEAD, 4)+LENGTH_AMSDU_SUBFRAMEHEAD; */
- hwHdrLen =
- pTxBlk->MpduHeaderLen - LENGTH_AMSDU_SUBFRAMEHEAD +
- pTxBlk->HdrPadLen + LENGTH_AMSDU_SUBFRAMEHEAD;
- else if (pTxBlk->TxFrameType == TX_RALINK_FRAME)
- /*hwHdrLen = ROUND_UP(pTxBlk->MpduHeaderLen-LENGTH_ARALINK_HEADER_FIELD, 4)+LENGTH_ARALINK_HEADER_FIELD; */
- hwHdrLen =
- pTxBlk->MpduHeaderLen -
- LENGTH_ARALINK_HEADER_FIELD + pTxBlk->HdrPadLen +
- LENGTH_ARALINK_HEADER_FIELD;
- else
- /*hwHdrLen = ROUND_UP(pTxBlk->MpduHeaderLen, 4); */
- hwHdrLen = pTxBlk->MpduHeaderLen + pTxBlk->HdrPadLen;
-
- firstDMALen = TXINFO_SIZE + TXWI_SIZE + hwHdrLen;
- } else {
- firstDMALen = pTxBlk->MpduHeaderLen;
- }
-
- NdisMoveMemory(pDMAHeaderBufVA, pTxBlk->HeaderBuf, firstDMALen);
-
- pTxRing->Cell[TxIdx].pNdisPacket = pTxBlk->pPacket;
- pTxRing->Cell[TxIdx].pNextNdisPacket = NULL;
-
- /* */
- /* build Tx Descriptor */
- /* */
- pTxD = (struct rt_txd *) pTxRing->Cell[TxIdx].AllocVa;
- NdisZeroMemory(pTxD, TXD_SIZE);
-
- pTxD->SDPtr0 = BufBasePaLow;
- pTxD->SDLen0 = firstDMALen; /* include padding */
- pTxD->SDPtr1 = PCI_MAP_SINGLE(pAd, pTxBlk, 0, 1, PCI_DMA_TODEVICE);
- pTxD->SDLen1 = pTxBlk->SrcBufLen;
- pTxD->LastSec0 = 0;
- pTxD->LastSec1 = (bIsLast) ? 1 : 0;
-
- RTMPWriteTxDescriptor(pAd, pTxD, FALSE, FIFO_EDCA);
-
- RetTxIdx = TxIdx;
- /* */
- /* Update Tx index */
- /* */
- INC_RING_INDEX(TxIdx, TX_RING_SIZE);
- pTxRing->TxCpuIdx = TxIdx;
-
- *FreeNumber -= 1;
-
- return RetTxIdx;
-
-}
-
-void RtmpPCI_FinalWriteTxResource(struct rt_rtmp_adapter *pAd,
- struct rt_tx_blk *pTxBlk,
- u16 totalMPDUSize, u16 FirstTxIdx)
-{
-
- struct rt_txwi * pTxWI;
- struct rt_rtmp_tx_ring *pTxRing;
-
- /* */
- /* get Tx Ring Resource */
- /* */
- pTxRing = &pAd->TxRing[pTxBlk->QueIdx];
- pTxWI = (struct rt_txwi *) pTxRing->Cell[FirstTxIdx].DmaBuf.AllocVa;
- pTxWI->MPDUtotalByteCount = totalMPDUSize;
-
-}
-
-void RtmpPCIDataLastTxIdx(struct rt_rtmp_adapter *pAd,
- u8 QueIdx, u16 LastTxIdx)
-{
- struct rt_txd * pTxD;
- struct rt_rtmp_tx_ring *pTxRing;
-
- /* */
- /* get Tx Ring Resource */
- /* */
- pTxRing = &pAd->TxRing[QueIdx];
-
- /* */
- /* build Tx Descriptor */
- /* */
- pTxD = (struct rt_txd *) pTxRing->Cell[LastTxIdx].AllocVa;
-
- pTxD->LastSec1 = 1;
-
-}
-
-u16 RtmpPCI_WriteFragTxResource(struct rt_rtmp_adapter *pAd,
- struct rt_tx_blk *pTxBlk,
- u8 fragNum, u16 * FreeNumber)
-{
- u8 *pDMAHeaderBufVA;
- u16 TxIdx, RetTxIdx;
- struct rt_txd * pTxD;
- u32 BufBasePaLow;
- struct rt_rtmp_tx_ring *pTxRing;
- u16 hwHeaderLen;
- u32 firstDMALen;
-
- /* */
- /* Get Tx Ring Resource */
- /* */
- pTxRing = &pAd->TxRing[pTxBlk->QueIdx];
- TxIdx = pAd->TxRing[pTxBlk->QueIdx].TxCpuIdx;
- pDMAHeaderBufVA = (u8 *)pTxRing->Cell[TxIdx].DmaBuf.AllocVa;
- BufBasePaLow =
- RTMP_GetPhysicalAddressLow(pTxRing->Cell[TxIdx].DmaBuf.AllocPa);
-
- /* */
- /* Copy TXINFO + TXWI + WLAN Header + LLC into DMA Header Buffer */
- /* */
- /*hwHeaderLen = ROUND_UP(pTxBlk->MpduHeaderLen, 4); */
- hwHeaderLen = pTxBlk->MpduHeaderLen + pTxBlk->HdrPadLen;
-
- firstDMALen = TXINFO_SIZE + TXWI_SIZE + hwHeaderLen;
- NdisMoveMemory(pDMAHeaderBufVA, pTxBlk->HeaderBuf, firstDMALen);
-
- /* */
- /* Build Tx Descriptor */
- /* */
- pTxD = (struct rt_txd *) pTxRing->Cell[TxIdx].AllocVa;
- NdisZeroMemory(pTxD, TXD_SIZE);
-
- if (fragNum == pTxBlk->TotalFragNum) {
- pTxRing->Cell[TxIdx].pNdisPacket = pTxBlk->pPacket;
- pTxRing->Cell[TxIdx].pNextNdisPacket = NULL;
- }
-
- pTxD->SDPtr0 = BufBasePaLow;
- pTxD->SDLen0 = firstDMALen; /* include padding */
- pTxD->SDPtr1 = PCI_MAP_SINGLE(pAd, pTxBlk, 0, 1, PCI_DMA_TODEVICE);
- pTxD->SDLen1 = pTxBlk->SrcBufLen;
- pTxD->LastSec0 = 0;
- pTxD->LastSec1 = 1;
-
- RTMPWriteTxDescriptor(pAd, pTxD, FALSE, FIFO_EDCA);
-
- RetTxIdx = TxIdx;
- pTxBlk->Priv += pTxBlk->SrcBufLen;
-
- /* */
- /* Update Tx index */
- /* */
- INC_RING_INDEX(TxIdx, TX_RING_SIZE);
- pTxRing->TxCpuIdx = TxIdx;
-
- *FreeNumber -= 1;
-
- return RetTxIdx;
-
-}
-
-/*
- Must be run in Interrupt context
- This function handle PCI specific TxDesc and cpu index update and kick the packet out.
- */
-int RtmpPCIMgmtKickOut(struct rt_rtmp_adapter *pAd,
- u8 QueIdx,
- void *pPacket,
- u8 *pSrcBufVA, u32 SrcBufLen)
-{
- struct rt_txd * pTxD;
- unsigned long SwIdx = pAd->MgmtRing.TxCpuIdx;
-
- pTxD = (struct rt_txd *) pAd->MgmtRing.Cell[SwIdx].AllocVa;
-
- pAd->MgmtRing.Cell[SwIdx].pNdisPacket = pPacket;
- pAd->MgmtRing.Cell[SwIdx].pNextNdisPacket = NULL;
-
- RTMPWriteTxDescriptor(pAd, pTxD, TRUE, FIFO_MGMT);
- pTxD->LastSec0 = 1;
- pTxD->LastSec1 = 1;
- pTxD->DMADONE = 0;
- pTxD->SDLen1 = 0;
- pTxD->SDPtr0 =
- PCI_MAP_SINGLE(pAd, pSrcBufVA, SrcBufLen, 0, PCI_DMA_TODEVICE);
- pTxD->SDLen0 = SrcBufLen;
-
-/*================================================================== */
-/* DBGPRINT_RAW(RT_DEBUG_TRACE, ("MLMEHardTransmit\n"));
- for (i = 0; i < (TXWI_SIZE+24); i++)
- {
-
- DBGPRINT_RAW(RT_DEBUG_TRACE, ("%x:", *(pSrcBufVA+i)));
- if ( i%4 == 3)
- DBGPRINT_RAW(RT_DEBUG_TRACE, (" :: "));
- if ( i%16 == 15)
- DBGPRINT_RAW(RT_DEBUG_TRACE, ("\n "));
- }
- DBGPRINT_RAW(RT_DEBUG_TRACE, ("\n "));*/
-/*======================================================================= */
-
- pAd->RalinkCounters.KickTxCount++;
- pAd->RalinkCounters.OneSecTxDoneCount++;
-
- /* Increase TX_CTX_IDX, but write to register later. */
- INC_RING_INDEX(pAd->MgmtRing.TxCpuIdx, MGMT_RING_SIZE);
-
- RTMP_IO_WRITE32(pAd, TX_MGMTCTX_IDX, pAd->MgmtRing.TxCpuIdx);
-
- return 0;
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Check Rx descriptor, return NDIS_STATUS_FAILURE if any error dound
-
- Arguments:
- pRxD Pointer to the Rx descriptor
-
- Return Value:
- NDIS_STATUS_SUCCESS No err
- NDIS_STATUS_FAILURE Error
-
- Note:
-
- ========================================================================
-*/
-int RTMPCheckRxError(struct rt_rtmp_adapter *pAd,
- struct rt_header_802_11 * pHeader,
- struct rt_rxwi * pRxWI, IN PRT28XX_RXD_STRUC pRxD)
-{
- struct rt_cipher_key *pWpaKey;
- int dBm;
-
- /* Phy errors & CRC errors */
- if ( /*(pRxD->PhyErr) || */ (pRxD->Crc)) {
- /* Check RSSI for Noise Hist statistic collection. */
- dBm = (int)(pRxWI->RSSI0) - pAd->BbpRssiToDbmDelta;
- if (dBm <= -87)
- pAd->StaCfg.RPIDensity[0] += 1;
- else if (dBm <= -82)
- pAd->StaCfg.RPIDensity[1] += 1;
- else if (dBm <= -77)
- pAd->StaCfg.RPIDensity[2] += 1;
- else if (dBm <= -72)
- pAd->StaCfg.RPIDensity[3] += 1;
- else if (dBm <= -67)
- pAd->StaCfg.RPIDensity[4] += 1;
- else if (dBm <= -62)
- pAd->StaCfg.RPIDensity[5] += 1;
- else if (dBm <= -57)
- pAd->StaCfg.RPIDensity[6] += 1;
- else if (dBm > -57)
- pAd->StaCfg.RPIDensity[7] += 1;
-
- return (NDIS_STATUS_FAILURE);
- }
- /* Add Rx size to channel load counter, we should ignore error counts */
- pAd->StaCfg.CLBusyBytes += (pRxD->SDL0 + 14);
-
- /* Drop ToDs promiscuous frame, it is opened due to CCX 2 channel load statistics */
- if (pHeader != NULL) {
- if (pHeader->FC.ToDs) {
- return (NDIS_STATUS_FAILURE);
- }
- }
- /* Drop not U2M frames, can't drop here because we will drop beacon in this case */
- /* I am kind of doubting the U2M bit operation */
- /* if (pRxD->U2M == 0) */
- /* return(NDIS_STATUS_FAILURE); */
-
- /* drop decyption fail frame */
- if (pRxD->CipherErr) {
- if (pRxD->CipherErr == 2) {
- DBGPRINT_RAW(RT_DEBUG_TRACE,
- ("pRxD ERROR: ICV ok but MICErr "));
- } else if (pRxD->CipherErr == 1) {
- DBGPRINT_RAW(RT_DEBUG_TRACE, ("pRxD ERROR: ICV Err "));
- } else if (pRxD->CipherErr == 3)
- DBGPRINT_RAW(RT_DEBUG_TRACE,
- ("pRxD ERROR: Key not valid "));
-
- if (((pRxD->CipherErr & 1) == 1)
- && pAd->CommonCfg.bWirelessEvent && INFRA_ON(pAd))
- RTMPSendWirelessEvent(pAd, IW_ICV_ERROR_EVENT_FLAG,
- pAd->MacTab.Content[BSSID_WCID].
- Addr, BSS0, 0);
-
- DBGPRINT_RAW(RT_DEBUG_TRACE,
- (" %d (len=%d, Mcast=%d, MyBss=%d, Wcid=%d, KeyId=%d)\n",
- pRxD->CipherErr, pRxD->SDL0,
- pRxD->Mcast | pRxD->Bcast, pRxD->MyBss,
- pRxWI->WirelessCliID,
-/* CipherName[pRxD->CipherAlg], */
- pRxWI->KeyIndex));
-
- /* */
- /* MIC Error */
- /* */
- if (pRxD->CipherErr == 2) {
- pWpaKey = &pAd->SharedKey[BSS0][pRxWI->KeyIndex];
- if (pAd->StaCfg.WpaSupplicantUP)
- WpaSendMicFailureToWpaSupplicant(pAd,
- (pWpaKey->
- Type ==
- PAIRWISEKEY) ?
- TRUE : FALSE);
- else
- RTMPReportMicError(pAd, pWpaKey);
-
- if (((pRxD->CipherErr & 2) == 2)
- && pAd->CommonCfg.bWirelessEvent && INFRA_ON(pAd))
- RTMPSendWirelessEvent(pAd,
- IW_MIC_ERROR_EVENT_FLAG,
- pAd->MacTab.
- Content[BSSID_WCID].Addr,
- BSS0, 0);
-
- DBGPRINT_RAW(RT_DEBUG_ERROR, ("Rx MIC Value error\n"));
- }
-
- if (pHeader == NULL)
- return (NDIS_STATUS_SUCCESS);
- /*if ((pRxD->CipherAlg == CIPHER_AES) &&
- (pHeader->Sequence == pAd->FragFrame.Sequence))
- {
- //
- // Acceptable since the First FragFrame no CipherErr problem.
- //
- return(NDIS_STATUS_SUCCESS);
- } */
-
- return (NDIS_STATUS_FAILURE);
- }
-
- return (NDIS_STATUS_SUCCESS);
-}
-
-BOOLEAN RTMPFreeTXDUponTxDmaDone(struct rt_rtmp_adapter *pAd, u8 QueIdx)
-{
- struct rt_rtmp_tx_ring *pTxRing;
- struct rt_txd * pTxD;
- void *pPacket;
- u8 FREE = 0;
- struct rt_txd TxD, *pOriTxD;
- /*unsigned long IrqFlags; */
- BOOLEAN bReschedule = FALSE;
-
- ASSERT(QueIdx < NUM_OF_TX_RING);
- pTxRing = &pAd->TxRing[QueIdx];
-
- RTMP_IO_READ32(pAd, TX_DTX_IDX0 + QueIdx * RINGREG_DIFF,
- &pTxRing->TxDmaIdx);
- while (pTxRing->TxSwFreeIdx != pTxRing->TxDmaIdx) {
-/* RTMP_IRQ_LOCK(&pAd->irq_lock, IrqFlags); */
-
- /* static rate also need NICUpdateFifoStaCounters() function. */
- /*if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_TX_RATE_SWITCH_ENABLED)) */
- NICUpdateFifoStaCounters(pAd);
-
- /* Note : If (pAd->ate.bQATxStart == TRUE), we will never reach here. */
- FREE++;
- pTxD =
- (struct rt_txd *) (pTxRing->Cell[pTxRing->TxSwFreeIdx].AllocVa);
- pOriTxD = pTxD;
- NdisMoveMemory(&TxD, pTxD, sizeof(struct rt_txd));
- pTxD = &TxD;
-
- pTxD->DMADONE = 0;
-
- {
- pPacket =
- pTxRing->Cell[pTxRing->TxSwFreeIdx].pNdisPacket;
- if (pPacket) {
- PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr1,
- pTxD->SDLen1,
- PCI_DMA_TODEVICE);
- RELEASE_NDIS_PACKET(pAd, pPacket,
- NDIS_STATUS_SUCCESS);
- }
- /*Always assign pNdisPacket as NULL after clear */
- pTxRing->Cell[pTxRing->TxSwFreeIdx].pNdisPacket = NULL;
-
- pPacket =
- pTxRing->Cell[pTxRing->TxSwFreeIdx].pNextNdisPacket;
-
- ASSERT(pPacket == NULL);
- if (pPacket) {
- PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr1,
- pTxD->SDLen1,
- PCI_DMA_TODEVICE);
- RELEASE_NDIS_PACKET(pAd, pPacket,
- NDIS_STATUS_SUCCESS);
- }
- /*Always assign pNextNdisPacket as NULL after clear */
- pTxRing->Cell[pTxRing->TxSwFreeIdx].pNextNdisPacket =
- NULL;
- }
-
- pAd->RalinkCounters.TransmittedByteCount +=
- (pTxD->SDLen1 + pTxD->SDLen0);
- pAd->RalinkCounters.OneSecDmaDoneCount[QueIdx]++;
- INC_RING_INDEX(pTxRing->TxSwFreeIdx, TX_RING_SIZE);
- /* get tx_tdx_idx again */
- RTMP_IO_READ32(pAd, TX_DTX_IDX0 + QueIdx * RINGREG_DIFF,
- &pTxRing->TxDmaIdx);
- NdisMoveMemory(pOriTxD, pTxD, sizeof(struct rt_txd));
-
-/* RTMP_IRQ_UNLOCK(&pAd->irq_lock, IrqFlags); */
- }
-
- return bReschedule;
-
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Process TX Rings DMA Done interrupt, running in DPC level
-
- Arguments:
- Adapter Pointer to our adapter
-
- Return Value:
- None
-
- IRQL = DISPATCH_LEVEL
-
- ========================================================================
-*/
-BOOLEAN RTMPHandleTxRingDmaDoneInterrupt(struct rt_rtmp_adapter *pAd,
- INT_SOURCE_CSR_STRUC TxRingBitmap)
-{
-/* u8 Count = 0; */
- unsigned long IrqFlags;
- BOOLEAN bReschedule = FALSE;
-
- /* Make sure Tx ring resource won't be used by other threads */
- /*NdisAcquireSpinLock(&pAd->TxRingLock); */
-
- RTMP_IRQ_LOCK(&pAd->irq_lock, IrqFlags);
-
- if (TxRingBitmap.field.Ac0DmaDone)
- bReschedule = RTMPFreeTXDUponTxDmaDone(pAd, QID_AC_BE);
-
- if (TxRingBitmap.field.Ac3DmaDone)
- bReschedule |= RTMPFreeTXDUponTxDmaDone(pAd, QID_AC_VO);
-
- if (TxRingBitmap.field.Ac2DmaDone)
- bReschedule |= RTMPFreeTXDUponTxDmaDone(pAd, QID_AC_VI);
-
- if (TxRingBitmap.field.Ac1DmaDone)
- bReschedule |= RTMPFreeTXDUponTxDmaDone(pAd, QID_AC_BK);
-
- /* Make sure to release Tx ring resource */
- /*NdisReleaseSpinLock(&pAd->TxRingLock); */
- RTMP_IRQ_UNLOCK(&pAd->irq_lock, IrqFlags);
-
- /* Dequeue outgoing frames from TxSwQueue[] and process it */
- RTMPDeQueuePacket(pAd, FALSE, NUM_OF_TX_RING, MAX_TX_PROCESS);
-
- return bReschedule;
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Process MGMT ring DMA done interrupt, running in DPC level
-
- Arguments:
- pAd Pointer to our adapter
-
- Return Value:
- None
-
- IRQL = DISPATCH_LEVEL
-
- Note:
-
- ========================================================================
-*/
-void RTMPHandleMgmtRingDmaDoneInterrupt(struct rt_rtmp_adapter *pAd)
-{
- struct rt_txd * pTxD;
- void *pPacket;
-/* int i; */
- u8 FREE = 0;
- struct rt_rtmp_mgmt_ring *pMgmtRing = &pAd->MgmtRing;
-
- NdisAcquireSpinLock(&pAd->MgmtRingLock);
-
- RTMP_IO_READ32(pAd, TX_MGMTDTX_IDX, &pMgmtRing->TxDmaIdx);
- while (pMgmtRing->TxSwFreeIdx != pMgmtRing->TxDmaIdx) {
- FREE++;
- pTxD =
- (struct rt_txd *) (pMgmtRing->Cell[pAd->MgmtRing.TxSwFreeIdx].
- AllocVa);
- pTxD->DMADONE = 0;
- pPacket = pMgmtRing->Cell[pMgmtRing->TxSwFreeIdx].pNdisPacket;
-
- if (pPacket) {
- PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr0, pTxD->SDLen0,
- PCI_DMA_TODEVICE);
- RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_SUCCESS);
- }
- pMgmtRing->Cell[pMgmtRing->TxSwFreeIdx].pNdisPacket = NULL;
-
- pPacket =
- pMgmtRing->Cell[pMgmtRing->TxSwFreeIdx].pNextNdisPacket;
- if (pPacket) {
- PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr1, pTxD->SDLen1,
- PCI_DMA_TODEVICE);
- RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_SUCCESS);
- }
- pMgmtRing->Cell[pMgmtRing->TxSwFreeIdx].pNextNdisPacket = NULL;
- INC_RING_INDEX(pMgmtRing->TxSwFreeIdx, MGMT_RING_SIZE);
-
- }
- NdisReleaseSpinLock(&pAd->MgmtRingLock);
-
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Arguments:
- Adapter Pointer to our adapter. Dequeue all power safe delayed braodcast frames after beacon.
-
- IRQL = DISPATCH_LEVEL
-
- ========================================================================
-*/
-void RTMPHandleTBTTInterrupt(struct rt_rtmp_adapter *pAd)
-{
- {
- if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_DOZE)) {
- }
- }
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Arguments:
- pAd Pointer to our adapter. Rewrite beacon content before next send-out.
-
- IRQL = DISPATCH_LEVEL
-
- ========================================================================
-*/
-void RTMPHandlePreTBTTInterrupt(struct rt_rtmp_adapter *pAd)
-{
- {
- if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_DOZE)) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("RTMPHandlePreTBTTInterrupt...\n"));
- }
- }
-
-}
-
-void RTMPHandleRxCoherentInterrupt(struct rt_rtmp_adapter *pAd)
-{
- WPDMA_GLO_CFG_STRUC GloCfg;
-
- if (pAd == NULL) {
- DBGPRINT(RT_DEBUG_TRACE, ("====> pAd is NULL, return.\n"));
- return;
- }
-
- DBGPRINT(RT_DEBUG_TRACE, ("==> RTMPHandleRxCoherentInterrupt \n"));
-
- RTMP_IO_READ32(pAd, WPDMA_GLO_CFG, &GloCfg.word);
-
- GloCfg.field.EnTXWriteBackDDONE = 0;
- GloCfg.field.EnableRxDMA = 0;
- GloCfg.field.EnableTxDMA = 0;
- RTMP_IO_WRITE32(pAd, WPDMA_GLO_CFG, GloCfg.word);
-
- RTMPRingCleanUp(pAd, QID_AC_BE);
- RTMPRingCleanUp(pAd, QID_AC_BK);
- RTMPRingCleanUp(pAd, QID_AC_VI);
- RTMPRingCleanUp(pAd, QID_AC_VO);
- RTMPRingCleanUp(pAd, QID_MGMT);
- RTMPRingCleanUp(pAd, QID_RX);
-
- RTMPEnableRxTx(pAd);
-
- DBGPRINT(RT_DEBUG_TRACE, ("<== RTMPHandleRxCoherentInterrupt \n"));
-}
-
-void *GetPacketFromRxRing(struct rt_rtmp_adapter *pAd,
- OUT PRT28XX_RXD_STRUC pSaveRxD,
- OUT BOOLEAN * pbReschedule,
- IN u32 * pRxPending)
-{
- struct rt_rxd * pRxD;
- void *pRxPacket = NULL;
- void *pNewPacket;
- void *AllocVa;
- dma_addr_t AllocPa;
- BOOLEAN bReschedule = FALSE;
- struct rt_rtmp_dmacb *pRxCell;
-
- RTMP_SEM_LOCK(&pAd->RxRingLock);
-
- if (*pRxPending == 0) {
- /* Get how may packets had been received */
- RTMP_IO_READ32(pAd, RX_DRX_IDX, &pAd->RxRing.RxDmaIdx);
-
- if (pAd->RxRing.RxSwReadIdx == pAd->RxRing.RxDmaIdx) {
- /* no more rx packets */
- bReschedule = FALSE;
- goto done;
- }
- /* get rx pending count */
- if (pAd->RxRing.RxDmaIdx > pAd->RxRing.RxSwReadIdx)
- *pRxPending =
- pAd->RxRing.RxDmaIdx - pAd->RxRing.RxSwReadIdx;
- else
- *pRxPending =
- pAd->RxRing.RxDmaIdx + RX_RING_SIZE -
- pAd->RxRing.RxSwReadIdx;
-
- }
-
- pRxCell = &pAd->RxRing.Cell[pAd->RxRing.RxSwReadIdx];
-
- /* Point to Rx indexed rx ring descriptor */
- pRxD = (struct rt_rxd *) pRxCell->AllocVa;
-
- if (pRxD->DDONE == 0) {
- *pRxPending = 0;
- /* DMAIndx had done but DDONE bit not ready */
- bReschedule = TRUE;
- goto done;
- }
-
- /* return rx descriptor */
- NdisMoveMemory(pSaveRxD, pRxD, RXD_SIZE);
-
- pNewPacket =
- RTMP_AllocateRxPacketBuffer(pAd, RX_BUFFER_AGGRESIZE, FALSE,
- &AllocVa, &AllocPa);
-
- if (pNewPacket) {
- /* unmap the rx buffer */
- PCI_UNMAP_SINGLE(pAd, pRxCell->DmaBuf.AllocPa,
- pRxCell->DmaBuf.AllocSize, PCI_DMA_FROMDEVICE);
- pRxPacket = pRxCell->pNdisPacket;
-
- pRxCell->DmaBuf.AllocSize = RX_BUFFER_AGGRESIZE;
- pRxCell->pNdisPacket = (void *)pNewPacket;
- pRxCell->DmaBuf.AllocVa = AllocVa;
- pRxCell->DmaBuf.AllocPa = AllocPa;
- /* update SDP0 to new buffer of rx packet */
- pRxD->SDP0 = AllocPa;
- } else {
- /*DBGPRINT(RT_DEBUG_TRACE,("No Rx Buffer\n")); */
- pRxPacket = NULL;
- bReschedule = TRUE;
- }
-
- pRxD->DDONE = 0;
-
- /* had handled one rx packet */
- *pRxPending = *pRxPending - 1;
-
- /* update rx descriptor and kick rx */
- INC_RING_INDEX(pAd->RxRing.RxSwReadIdx, RX_RING_SIZE);
-
- pAd->RxRing.RxCpuIdx =
- (pAd->RxRing.RxSwReadIdx ==
- 0) ? (RX_RING_SIZE - 1) : (pAd->RxRing.RxSwReadIdx - 1);
- RTMP_IO_WRITE32(pAd, RX_CRX_IDX, pAd->RxRing.RxCpuIdx);
-
-done:
- RTMP_SEM_UNLOCK(&pAd->RxRingLock);
- *pbReschedule = bReschedule;
- return pRxPacket;
-}
-
-int MlmeHardTransmitTxRing(struct rt_rtmp_adapter *pAd,
- u8 QueIdx, void *pPacket)
-{
- struct rt_packet_info PacketInfo;
- u8 *pSrcBufVA;
- u32 SrcBufLen;
- struct rt_txd * pTxD;
- struct rt_header_802_11 * pHeader_802_11;
- BOOLEAN bAckRequired, bInsertTimestamp;
- unsigned long SrcBufPA;
- /*u8 TxBufIdx; */
- u8 MlmeRate;
- unsigned long SwIdx = pAd->TxRing[QueIdx].TxCpuIdx;
- struct rt_txwi * pFirstTxWI;
- /*unsigned long i; */
- /*HTTRANSMIT_SETTING MlmeTransmit; //Rate for this MGMT frame. */
- unsigned long FreeNum;
- struct rt_mac_table_entry *pMacEntry = NULL;
-
- RTMP_QueryPacketInfo(pPacket, &PacketInfo, &pSrcBufVA, &SrcBufLen);
-
- if (pSrcBufVA == NULL) {
- /* The buffer shouldn't be NULL */
- return NDIS_STATUS_FAILURE;
- }
- /* Make sure MGMT ring resource won't be used by other threads */
- /*NdisAcquireSpinLock(&pAd->TxRingLock); */
-
- FreeNum = GET_TXRING_FREENO(pAd, QueIdx);
-
- if (FreeNum == 0) {
- /*NdisReleaseSpinLock(&pAd->TxRingLock); */
- return NDIS_STATUS_FAILURE;
- }
-
- SwIdx = pAd->TxRing[QueIdx].TxCpuIdx;
-
- pTxD = (struct rt_txd *) pAd->TxRing[QueIdx].Cell[SwIdx].AllocVa;
-
- if (pAd->TxRing[QueIdx].Cell[SwIdx].pNdisPacket) {
- DBGPRINT(RT_DEBUG_OFF, ("MlmeHardTransmit Error\n"));
- /*NdisReleaseSpinLock(&pAd->TxRingLock); */
- return NDIS_STATUS_FAILURE;
- }
-
- {
- /* outgoing frame always wakeup PHY to prevent frame lost */
- /* if (pAd->StaCfg.Psm == PWR_SAVE) */
- if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_DOZE))
- AsicForceWakeup(pAd, TRUE);
- }
- pFirstTxWI = (struct rt_txwi *) pSrcBufVA;
-
- pHeader_802_11 = (struct rt_header_802_11 *) (pSrcBufVA + TXWI_SIZE);
- if (pHeader_802_11->Addr1[0] & 0x01) {
- MlmeRate = pAd->CommonCfg.BasicMlmeRate;
- } else {
- MlmeRate = pAd->CommonCfg.MlmeRate;
- }
-
- if ((pHeader_802_11->FC.Type == BTYPE_DATA) &&
- (pHeader_802_11->FC.SubType == SUBTYPE_QOS_NULL)) {
- pMacEntry = MacTableLookup(pAd, pHeader_802_11->Addr1);
- }
- /* Verify Mlme rate for a / g bands. */
- if ((pAd->LatchRfRegs.Channel > 14) && (MlmeRate < RATE_6)) /* 11A band */
- MlmeRate = RATE_6;
-
- /* */
- /* Should not be hard code to set PwrMgmt to 0 (PWR_ACTIVE) */
- /* Snice it's been set to 0 while on MgtMacHeaderInit */
- /* By the way this will cause frame to be send on PWR_SAVE failed. */
- /* */
- /* */
- /* In WMM-UAPSD, mlme frame should be set psm as power saving but probe request frame */
- /* Data-Null packets also pass through MMRequest in RT2860, however, we hope control the psm bit to pass APSD */
- if (pHeader_802_11->FC.Type != BTYPE_DATA) {
- if ((pHeader_802_11->FC.SubType == SUBTYPE_PROBE_REQ)
- || !(pAd->CommonCfg.bAPSDCapable
- && pAd->CommonCfg.APEdcaParm.bAPSDCapable)) {
- pHeader_802_11->FC.PwrMgmt = PWR_ACTIVE;
- } else {
- pHeader_802_11->FC.PwrMgmt =
- pAd->CommonCfg.bAPSDForcePowerSave;
- }
- }
-
- bInsertTimestamp = FALSE;
- if (pHeader_802_11->FC.Type == BTYPE_CNTL) /* must be PS-POLL */
- {
- bAckRequired = FALSE;
- } else /* BTYPE_MGMT or BTYPE_DATA(must be NULL frame) */
- {
- if (pHeader_802_11->Addr1[0] & 0x01) /* MULTICAST, BROADCAST */
- {
- bAckRequired = FALSE;
- pHeader_802_11->Duration = 0;
- } else {
- bAckRequired = TRUE;
- pHeader_802_11->Duration =
- RTMPCalcDuration(pAd, MlmeRate, 14);
- if (pHeader_802_11->FC.SubType == SUBTYPE_PROBE_RSP) {
- bInsertTimestamp = TRUE;
- }
- }
- }
- pHeader_802_11->Sequence = pAd->Sequence++;
- if (pAd->Sequence > 0xfff)
- pAd->Sequence = 0;
- /* Before radar detection done, mgmt frame can not be sent but probe req */
- /* Because we need to use probe req to trigger driver to send probe req in passive scan */
- if ((pHeader_802_11->FC.SubType != SUBTYPE_PROBE_REQ)
- && (pAd->CommonCfg.bIEEE80211H == 1)
- && (pAd->CommonCfg.RadarDetect.RDMode != RD_NORMAL_MODE)) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("MlmeHardTransmit --> radar detect not in normal mode!\n"));
- /*NdisReleaseSpinLock(&pAd->TxRingLock); */
- return (NDIS_STATUS_FAILURE);
- }
- /* */
- /* fill scatter-and-gather buffer list into TXD. Internally created NDIS PACKET */
- /* should always has only one ohysical buffer, and the whole frame size equals */
- /* to the first scatter buffer size */
- /* */
-
- /* Initialize TX Descriptor */
- /* For inter-frame gap, the number is for this frame and next frame */
- /* For MLME rate, we will fix as 2Mb to match other vendor's implement */
-/* pAd->CommonCfg.MlmeTransmit.field.MODE = 1; */
-
-/* management frame doesn't need encryption. so use RESERVED_WCID no matter u are sending to specific wcid or not. */
- /* Only beacon use Nseq=TRUE. So here we use Nseq=FALSE. */
- if (pMacEntry == NULL) {
- RTMPWriteTxWI(pAd, pFirstTxWI, FALSE, FALSE, bInsertTimestamp,
- FALSE, bAckRequired, FALSE, 0, RESERVED_WCID,
- (SrcBufLen - TXWI_SIZE), PID_MGMT, 0,
- (u8)pAd->CommonCfg.MlmeTransmit.field.MCS,
- IFS_BACKOFF, FALSE, &pAd->CommonCfg.MlmeTransmit);
- } else {
- RTMPWriteTxWI(pAd, pFirstTxWI, FALSE, FALSE,
- bInsertTimestamp, FALSE, bAckRequired, FALSE,
- 0, pMacEntry->Aid, (SrcBufLen - TXWI_SIZE),
- pMacEntry->MaxHTPhyMode.field.MCS, 0,
- (u8)pMacEntry->MaxHTPhyMode.field.MCS,
- IFS_BACKOFF, FALSE, &pMacEntry->MaxHTPhyMode);
- }
-
- pAd->TxRing[QueIdx].Cell[SwIdx].pNdisPacket = pPacket;
- pAd->TxRing[QueIdx].Cell[SwIdx].pNextNdisPacket = NULL;
-/* pFirstTxWI->MPDUtotalByteCount = SrcBufLen - TXWI_SIZE; */
- SrcBufPA =
- PCI_MAP_SINGLE(pAd, pSrcBufVA, SrcBufLen, 0, PCI_DMA_TODEVICE);
-
- RTMPWriteTxDescriptor(pAd, pTxD, TRUE, FIFO_EDCA);
- pTxD->LastSec0 = 1;
- pTxD->LastSec1 = 1;
- pTxD->SDLen0 = SrcBufLen;
- pTxD->SDLen1 = 0;
- pTxD->SDPtr0 = SrcBufPA;
- pTxD->DMADONE = 0;
-
- pAd->RalinkCounters.KickTxCount++;
- pAd->RalinkCounters.OneSecTxDoneCount++;
-
- /* Increase TX_CTX_IDX, but write to register later. */
- INC_RING_INDEX(pAd->TxRing[QueIdx].TxCpuIdx, TX_RING_SIZE);
-
- RTMP_IO_WRITE32(pAd, TX_CTX_IDX0 + QueIdx * 0x10,
- pAd->TxRing[QueIdx].TxCpuIdx);
-
- /* Make sure to release MGMT ring resource */
-/* NdisReleaseSpinLock(&pAd->TxRingLock); */
-
- return NDIS_STATUS_SUCCESS;
-}
-
-int MlmeDataHardTransmit(struct rt_rtmp_adapter *pAd,
- u8 QueIdx, void *pPacket)
-{
- if ((pAd->CommonCfg.RadarDetect.RDMode != RD_NORMAL_MODE)
- ) {
- return NDIS_STATUS_FAILURE;
- }
-
- return MlmeHardTransmitTxRing(pAd, QueIdx, pPacket);
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Calculates the duration which is required to transmit out frames
- with given size and specified rate.
-
- Arguments:
- pTxD Pointer to transmit descriptor
- Ack Setting for Ack requirement bit
- Fragment Setting for Fragment bit
- RetryMode Setting for retry mode
- Ifs Setting for IFS gap
- Rate Setting for transmit rate
- Service Setting for service
- Length Frame length
- TxPreamble Short or Long preamble when using CCK rates
- QueIdx - 0-3, according to 802.11e/d4.4 June/2003
-
- Return Value:
- None
-
- IRQL = PASSIVE_LEVEL
- IRQL = DISPATCH_LEVEL
-
- ========================================================================
-*/
-void RTMPWriteTxDescriptor(struct rt_rtmp_adapter *pAd,
- struct rt_txd * pTxD,
- IN BOOLEAN bWIV, u8 QueueSEL)
-{
- /* */
- /* Always use Long preamble before verifiation short preamble functionality works well. */
- /* Todo: remove the following line if short preamble functionality works */
- /* */
- OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_SHORT_PREAMBLE_INUSED);
-
- pTxD->WIV = (bWIV) ? 1 : 0;
- pTxD->QSEL = (QueueSEL);
- /*RT2860c?? fixed using EDCA queue for test... We doubt Queue1 has problem. 2006-09-26 Jan */
- /*pTxD->QSEL= FIFO_EDCA; */
- pTxD->DMADONE = 0;
-}
diff --git a/drivers/staging/rt2860/common/cmm_data_usb.c b/drivers/staging/rt2860/common/cmm_data_usb.c
deleted file mode 100644
index 83a62fa..0000000
--- a/drivers/staging/rt2860/common/cmm_data_usb.c
+++ /dev/null
@@ -1,951 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-*/
-
-/*
- All functions in this file must be USB-depended, or you should out your function
- in other files.
-
-*/
-
-#ifdef RTMP_MAC_USB
-
-#include "../rt_config.h"
-
-/*
- We can do copy the frame into pTxContext when match following conditions.
- =>
- =>
- =>
-*/
-static inline int RtmpUSBCanDoWrite(struct rt_rtmp_adapter *pAd,
- u8 QueIdx,
- struct rt_ht_tx_context *pHTTXContext)
-{
- int canWrite = NDIS_STATUS_RESOURCES;
-
- if (((pHTTXContext->CurWritePosition) <
- pHTTXContext->NextBulkOutPosition)
- && (pHTTXContext->CurWritePosition + LOCAL_TXBUF_SIZE) >
- pHTTXContext->NextBulkOutPosition) {
- DBGPRINT(RT_DEBUG_ERROR, ("RtmpUSBCanDoWrite c1!\n"));
- RTUSB_SET_BULK_FLAG(pAd,
- (fRTUSB_BULK_OUT_DATA_NORMAL << QueIdx));
- } else if ((pHTTXContext->CurWritePosition == 8)
- && (pHTTXContext->NextBulkOutPosition < LOCAL_TXBUF_SIZE)) {
- DBGPRINT(RT_DEBUG_ERROR, ("RtmpUSBCanDoWrite c2!\n"));
- RTUSB_SET_BULK_FLAG(pAd,
- (fRTUSB_BULK_OUT_DATA_NORMAL << QueIdx));
- } else if (pHTTXContext->bCurWriting == TRUE) {
- DBGPRINT(RT_DEBUG_ERROR, ("RtmpUSBCanDoWrite c3!\n"));
- } else {
- canWrite = NDIS_STATUS_SUCCESS;
- }
-
- return canWrite;
-}
-
-u16 RtmpUSB_WriteSubTxResource(struct rt_rtmp_adapter *pAd,
- struct rt_tx_blk *pTxBlk,
- IN BOOLEAN bIsLast, u16 * FreeNumber)
-{
-
- /* Dummy function. Should be removed in the future. */
- return 0;
-
-}
-
-u16 RtmpUSB_WriteFragTxResource(struct rt_rtmp_adapter *pAd,
- struct rt_tx_blk *pTxBlk,
- u8 fragNum, u16 * FreeNumber)
-{
- struct rt_ht_tx_context *pHTTXContext;
- u16 hwHdrLen; /* The hwHdrLen consist of 802.11 header length plus the header padding length. */
- u32 fillOffset;
- struct rt_txinfo *pTxInfo;
- struct rt_txwi *pTxWI;
- u8 *pWirelessPacket = NULL;
- u8 QueIdx;
- int Status;
- unsigned long IrqFlags;
- u32 USBDMApktLen = 0, DMAHdrLen, padding;
- BOOLEAN TxQLastRound = FALSE;
-
- /* */
- /* get Tx Ring Resource & Dma Buffer address */
- /* */
- QueIdx = pTxBlk->QueIdx;
- pHTTXContext = &pAd->TxContext[QueIdx];
-
- RTMP_IRQ_LOCK(&pAd->TxContextQueueLock[QueIdx], IrqFlags);
-
- pHTTXContext = &pAd->TxContext[QueIdx];
- fillOffset = pHTTXContext->CurWritePosition;
-
- if (fragNum == 0) {
- /* Check if we have enough space for this bulk-out batch. */
- Status = RtmpUSBCanDoWrite(pAd, QueIdx, pHTTXContext);
- if (Status == NDIS_STATUS_SUCCESS) {
- pHTTXContext->bCurWriting = TRUE;
-
- /* Reserve space for 8 bytes padding. */
- if ((pHTTXContext->ENextBulkOutPosition ==
- pHTTXContext->CurWritePosition)) {
- pHTTXContext->ENextBulkOutPosition += 8;
- pHTTXContext->CurWritePosition += 8;
- fillOffset += 8;
- }
- pTxBlk->Priv = 0;
- pHTTXContext->CurWriteRealPos =
- pHTTXContext->CurWritePosition;
- } else {
- RTMP_IRQ_UNLOCK(&pAd->TxContextQueueLock[QueIdx],
- IrqFlags);
-
- RELEASE_NDIS_PACKET(pAd, pTxBlk->pPacket,
- NDIS_STATUS_FAILURE);
- return (Status);
- }
- } else {
- /* For sub-sequent frames of this bulk-out batch. Just copy it to our bulk-out buffer. */
- Status =
- ((pHTTXContext->bCurWriting ==
- TRUE) ? NDIS_STATUS_SUCCESS : NDIS_STATUS_FAILURE);
- if (Status == NDIS_STATUS_SUCCESS) {
- fillOffset += pTxBlk->Priv;
- } else {
- RTMP_IRQ_UNLOCK(&pAd->TxContextQueueLock[QueIdx],
- IrqFlags);
-
- RELEASE_NDIS_PACKET(pAd, pTxBlk->pPacket,
- NDIS_STATUS_FAILURE);
- return (Status);
- }
- }
-
- NdisZeroMemory((u8 *)(&pTxBlk->HeaderBuf[0]), TXINFO_SIZE);
- pTxInfo = (struct rt_txinfo *)(&pTxBlk->HeaderBuf[0]);
- pTxWI = (struct rt_txwi *) (&pTxBlk->HeaderBuf[TXINFO_SIZE]);
-
- pWirelessPacket =
- &pHTTXContext->TransferBuffer->field.WirelessPacket[fillOffset];
-
- /* copy TXWI + WLAN Header + LLC into DMA Header Buffer */
- /*hwHdrLen = ROUND_UP(pTxBlk->MpduHeaderLen, 4); */
- hwHdrLen = pTxBlk->MpduHeaderLen + pTxBlk->HdrPadLen;
-
- /* Build our URB for USBD */
- DMAHdrLen = TXWI_SIZE + hwHdrLen;
- USBDMApktLen = DMAHdrLen + pTxBlk->SrcBufLen;
- padding = (4 - (USBDMApktLen % 4)) & 0x03; /* round up to 4 byte alignment */
- USBDMApktLen += padding;
-
- pTxBlk->Priv += (TXINFO_SIZE + USBDMApktLen);
-
- /* For TxInfo, the length of USBDMApktLen = TXWI_SIZE + 802.11 header + payload */
- RTMPWriteTxInfo(pAd, pTxInfo, (u16)(USBDMApktLen), FALSE, FIFO_EDCA,
- FALSE /*NextValid */ , FALSE);
-
- if (fragNum == pTxBlk->TotalFragNum) {
- pTxInfo->USBDMATxburst = 0;
- if ((pHTTXContext->CurWritePosition + pTxBlk->Priv + 3906) >
- MAX_TXBULK_LIMIT) {
- pTxInfo->SwUseLastRound = 1;
- TxQLastRound = TRUE;
- }
- } else {
- pTxInfo->USBDMATxburst = 1;
- }
-
- NdisMoveMemory(pWirelessPacket, pTxBlk->HeaderBuf,
- TXINFO_SIZE + TXWI_SIZE + hwHdrLen);
- pWirelessPacket += (TXINFO_SIZE + TXWI_SIZE + hwHdrLen);
- pHTTXContext->CurWriteRealPos += (TXINFO_SIZE + TXWI_SIZE + hwHdrLen);
-
- RTMP_IRQ_UNLOCK(&pAd->TxContextQueueLock[QueIdx], IrqFlags);
-
- NdisMoveMemory(pWirelessPacket, pTxBlk->pSrcBufData, pTxBlk->SrcBufLen);
-
- /* Zero the last padding. */
- pWirelessPacket += pTxBlk->SrcBufLen;
- NdisZeroMemory(pWirelessPacket, padding + 8);
-
- if (fragNum == pTxBlk->TotalFragNum) {
- RTMP_IRQ_LOCK(&pAd->TxContextQueueLock[QueIdx], IrqFlags);
-
- /* Update the pHTTXContext->CurWritePosition. 3906 used to prevent the NextBulkOut is a A-RALINK/A-MSDU Frame. */
- pHTTXContext->CurWritePosition += pTxBlk->Priv;
- if (TxQLastRound == TRUE)
- pHTTXContext->CurWritePosition = 8;
- pHTTXContext->CurWriteRealPos = pHTTXContext->CurWritePosition;
-
- /* Finally, set bCurWriting as FALSE */
- pHTTXContext->bCurWriting = FALSE;
-
- RTMP_IRQ_UNLOCK(&pAd->TxContextQueueLock[QueIdx], IrqFlags);
-
- /* succeed and release the skb buffer */
- RELEASE_NDIS_PACKET(pAd, pTxBlk->pPacket, NDIS_STATUS_SUCCESS);
- }
-
- return (Status);
-
-}
-
-u16 RtmpUSB_WriteSingleTxResource(struct rt_rtmp_adapter *pAd,
- struct rt_tx_blk *pTxBlk,
- IN BOOLEAN bIsLast,
- u16 * FreeNumber)
-{
- struct rt_ht_tx_context *pHTTXContext;
- u16 hwHdrLen;
- u32 fillOffset;
- struct rt_txinfo *pTxInfo;
- struct rt_txwi *pTxWI;
- u8 *pWirelessPacket;
- u8 QueIdx;
- unsigned long IrqFlags;
- int Status;
- u32 USBDMApktLen = 0, DMAHdrLen, padding;
- BOOLEAN bTxQLastRound = FALSE;
-
- /* For USB, didn't need PCI_MAP_SINGLE() */
- /*SrcBufPA = PCI_MAP_SINGLE(pAd, (char *) pTxBlk->pSrcBufData, pTxBlk->SrcBufLen, PCI_DMA_TODEVICE); */
-
- /* */
- /* get Tx Ring Resource & Dma Buffer address */
- /* */
- QueIdx = pTxBlk->QueIdx;
-
- RTMP_IRQ_LOCK(&pAd->TxContextQueueLock[QueIdx], IrqFlags);
- pHTTXContext = &pAd->TxContext[QueIdx];
- fillOffset = pHTTXContext->CurWritePosition;
-
- /* Check ring full. */
- Status = RtmpUSBCanDoWrite(pAd, QueIdx, pHTTXContext);
- if (Status == NDIS_STATUS_SUCCESS) {
- pHTTXContext->bCurWriting = TRUE;
-
- pTxInfo = (struct rt_txinfo *)(&pTxBlk->HeaderBuf[0]);
- pTxWI = (struct rt_txwi *) (&pTxBlk->HeaderBuf[TXINFO_SIZE]);
-
- /* Reserve space for 8 bytes padding. */
- if ((pHTTXContext->ENextBulkOutPosition ==
- pHTTXContext->CurWritePosition)) {
- pHTTXContext->ENextBulkOutPosition += 8;
- pHTTXContext->CurWritePosition += 8;
- fillOffset += 8;
- }
- pHTTXContext->CurWriteRealPos = pHTTXContext->CurWritePosition;
-
- pWirelessPacket =
- &pHTTXContext->TransferBuffer->field.
- WirelessPacket[fillOffset];
-
- /* copy TXWI + WLAN Header + LLC into DMA Header Buffer */
- /*hwHdrLen = ROUND_UP(pTxBlk->MpduHeaderLen, 4); */
- hwHdrLen = pTxBlk->MpduHeaderLen + pTxBlk->HdrPadLen;
-
- /* Build our URB for USBD */
- DMAHdrLen = TXWI_SIZE + hwHdrLen;
- USBDMApktLen = DMAHdrLen + pTxBlk->SrcBufLen;
- padding = (4 - (USBDMApktLen % 4)) & 0x03; /* round up to 4 byte alignment */
- USBDMApktLen += padding;
-
- pTxBlk->Priv = (TXINFO_SIZE + USBDMApktLen);
-
- /* For TxInfo, the length of USBDMApktLen = TXWI_SIZE + 802.11 header + payload */
- RTMPWriteTxInfo(pAd, pTxInfo, (u16)(USBDMApktLen), FALSE,
- FIFO_EDCA, FALSE /*NextValid */ , FALSE);
-
- if ((pHTTXContext->CurWritePosition + 3906 + pTxBlk->Priv) >
- MAX_TXBULK_LIMIT) {
- pTxInfo->SwUseLastRound = 1;
- bTxQLastRound = TRUE;
- }
- NdisMoveMemory(pWirelessPacket, pTxBlk->HeaderBuf,
- TXINFO_SIZE + TXWI_SIZE + hwHdrLen);
- pWirelessPacket += (TXINFO_SIZE + TXWI_SIZE + hwHdrLen);
-
- /* We unlock it here to prevent the first 8 bytes maybe over-writed issue. */
- /* 1. First we got CurWritePosition but the first 8 bytes still not write to the pTxcontext. */
- /* 2. An interrupt break our routine and handle bulk-out complete. */
- /* 3. In the bulk-out compllete, it need to do another bulk-out, */
- /* if the ENextBulkOutPosition is just the same as CurWritePosition, it will save the first 8 bytes from CurWritePosition, */
- /* but the payload still not copyed. the pTxContext->SavedPad[] will save as allzero. and set the bCopyPad = TRUE. */
- /* 4. Interrupt complete. */
- /* 5. Our interrupted routine go back and fill the first 8 bytes to pTxContext. */
- /* 6. Next time when do bulk-out, it found the bCopyPad==TRUE and will copy the SavedPad[] to pTxContext->NextBulkOutPosition. */
- /* and the packet will wrong. */
- pHTTXContext->CurWriteRealPos +=
- (TXINFO_SIZE + TXWI_SIZE + hwHdrLen);
- RTMP_IRQ_UNLOCK(&pAd->TxContextQueueLock[QueIdx], IrqFlags);
-
- NdisMoveMemory(pWirelessPacket, pTxBlk->pSrcBufData,
- pTxBlk->SrcBufLen);
- pWirelessPacket += pTxBlk->SrcBufLen;
- NdisZeroMemory(pWirelessPacket, padding + 8);
-
- RTMP_IRQ_LOCK(&pAd->TxContextQueueLock[QueIdx], IrqFlags);
-
- pHTTXContext->CurWritePosition += pTxBlk->Priv;
- if (bTxQLastRound)
- pHTTXContext->CurWritePosition = 8;
- pHTTXContext->CurWriteRealPos = pHTTXContext->CurWritePosition;
-
- pHTTXContext->bCurWriting = FALSE;
- }
-
- RTMP_IRQ_UNLOCK(&pAd->TxContextQueueLock[QueIdx], IrqFlags);
-
- /* succeed and release the skb buffer */
- RELEASE_NDIS_PACKET(pAd, pTxBlk->pPacket, NDIS_STATUS_SUCCESS);
-
- return (Status);
-
-}
-
-u16 RtmpUSB_WriteMultiTxResource(struct rt_rtmp_adapter *pAd,
- struct rt_tx_blk *pTxBlk,
- u8 frameNum, u16 * FreeNumber)
-{
- struct rt_ht_tx_context *pHTTXContext;
- u16 hwHdrLen; /* The hwHdrLen consist of 802.11 header length plus the header padding length. */
- u32 fillOffset;
- struct rt_txinfo *pTxInfo;
- struct rt_txwi *pTxWI;
- u8 *pWirelessPacket = NULL;
- u8 QueIdx;
- int Status;
- unsigned long IrqFlags;
- /*u32 USBDMApktLen = 0, DMAHdrLen, padding; */
-
- /* */
- /* get Tx Ring Resource & Dma Buffer address */
- /* */
- QueIdx = pTxBlk->QueIdx;
- pHTTXContext = &pAd->TxContext[QueIdx];
-
- RTMP_IRQ_LOCK(&pAd->TxContextQueueLock[QueIdx], IrqFlags);
-
- if (frameNum == 0) {
- /* Check if we have enough space for this bulk-out batch. */
- Status = RtmpUSBCanDoWrite(pAd, QueIdx, pHTTXContext);
- if (Status == NDIS_STATUS_SUCCESS) {
- pHTTXContext->bCurWriting = TRUE;
-
- pTxInfo = (struct rt_txinfo *)(&pTxBlk->HeaderBuf[0]);
- pTxWI = (struct rt_txwi *) (&pTxBlk->HeaderBuf[TXINFO_SIZE]);
-
- /* Reserve space for 8 bytes padding. */
- if ((pHTTXContext->ENextBulkOutPosition ==
- pHTTXContext->CurWritePosition)) {
-
- pHTTXContext->CurWritePosition += 8;
- pHTTXContext->ENextBulkOutPosition += 8;
- }
- fillOffset = pHTTXContext->CurWritePosition;
- pHTTXContext->CurWriteRealPos =
- pHTTXContext->CurWritePosition;
-
- pWirelessPacket =
- &pHTTXContext->TransferBuffer->field.
- WirelessPacket[fillOffset];
-
- /* */
- /* Copy TXINFO + TXWI + WLAN Header + LLC into DMA Header Buffer */
- /* */
- if (pTxBlk->TxFrameType == TX_AMSDU_FRAME)
- /*hwHdrLen = ROUND_UP(pTxBlk->MpduHeaderLen-LENGTH_AMSDU_SUBFRAMEHEAD, 4)+LENGTH_AMSDU_SUBFRAMEHEAD; */
- hwHdrLen =
- pTxBlk->MpduHeaderLen -
- LENGTH_AMSDU_SUBFRAMEHEAD +
- pTxBlk->HdrPadLen +
- LENGTH_AMSDU_SUBFRAMEHEAD;
- else if (pTxBlk->TxFrameType == TX_RALINK_FRAME)
- /*hwHdrLen = ROUND_UP(pTxBlk->MpduHeaderLen-LENGTH_ARALINK_HEADER_FIELD, 4)+LENGTH_ARALINK_HEADER_FIELD; */
- hwHdrLen =
- pTxBlk->MpduHeaderLen -
- LENGTH_ARALINK_HEADER_FIELD +
- pTxBlk->HdrPadLen +
- LENGTH_ARALINK_HEADER_FIELD;
- else
- /*hwHdrLen = ROUND_UP(pTxBlk->MpduHeaderLen, 4); */
- hwHdrLen =
- pTxBlk->MpduHeaderLen + pTxBlk->HdrPadLen;
-
- /* Update the pTxBlk->Priv. */
- pTxBlk->Priv = TXINFO_SIZE + TXWI_SIZE + hwHdrLen;
-
- /* pTxInfo->USBDMApktLen now just a temp value and will to correct latter. */
- RTMPWriteTxInfo(pAd, pTxInfo, (u16)(pTxBlk->Priv),
- FALSE, FIFO_EDCA, FALSE /*NextValid */ ,
- FALSE);
-
- /* Copy it. */
- NdisMoveMemory(pWirelessPacket, pTxBlk->HeaderBuf,
- pTxBlk->Priv);
- pHTTXContext->CurWriteRealPos += pTxBlk->Priv;
- pWirelessPacket += pTxBlk->Priv;
- }
- } else { /* For sub-sequent frames of this bulk-out batch. Just copy it to our bulk-out buffer. */
-
- Status =
- ((pHTTXContext->bCurWriting ==
- TRUE) ? NDIS_STATUS_SUCCESS : NDIS_STATUS_FAILURE);
- if (Status == NDIS_STATUS_SUCCESS) {
- fillOffset =
- (pHTTXContext->CurWritePosition + pTxBlk->Priv);
- pWirelessPacket =
- &pHTTXContext->TransferBuffer->field.
- WirelessPacket[fillOffset];
-
- /*hwHdrLen = pTxBlk->MpduHeaderLen; */
- NdisMoveMemory(pWirelessPacket, pTxBlk->HeaderBuf,
- pTxBlk->MpduHeaderLen);
- pWirelessPacket += (pTxBlk->MpduHeaderLen);
- pTxBlk->Priv += pTxBlk->MpduHeaderLen;
- } else { /* It should not happened now unless we are going to shutdown. */
- DBGPRINT(RT_DEBUG_ERROR,
- ("WriteMultiTxResource():bCurWriting is FALSE when handle sub-sequent frames.\n"));
- Status = NDIS_STATUS_FAILURE;
- }
- }
-
- /* We unlock it here to prevent the first 8 bytes maybe over-write issue. */
- /* 1. First we got CurWritePosition but the first 8 bytes still not write to the pTxContext. */
- /* 2. An interrupt break our routine and handle bulk-out complete. */
- /* 3. In the bulk-out compllete, it need to do another bulk-out, */
- /* if the ENextBulkOutPosition is just the same as CurWritePosition, it will save the first 8 bytes from CurWritePosition, */
- /* but the payload still not copyed. the pTxContext->SavedPad[] will save as allzero. and set the bCopyPad = TRUE. */
- /* 4. Interrupt complete. */
- /* 5. Our interrupted routine go back and fill the first 8 bytes to pTxContext. */
- /* 6. Next time when do bulk-out, it found the bCopyPad==TRUE and will copy the SavedPad[] to pTxContext->NextBulkOutPosition. */
- /* and the packet will wrong. */
- RTMP_IRQ_UNLOCK(&pAd->TxContextQueueLock[QueIdx], IrqFlags);
-
- if (Status != NDIS_STATUS_SUCCESS) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("WriteMultiTxResource: CWPos = %ld, NBOutPos = %ld.\n",
- pHTTXContext->CurWritePosition,
- pHTTXContext->NextBulkOutPosition));
- goto done;
- }
- /* Copy the frame content into DMA buffer and update the pTxBlk->Priv */
- NdisMoveMemory(pWirelessPacket, pTxBlk->pSrcBufData, pTxBlk->SrcBufLen);
- pWirelessPacket += pTxBlk->SrcBufLen;
- pTxBlk->Priv += pTxBlk->SrcBufLen;
-
-done:
- /* Release the skb buffer here */
- RELEASE_NDIS_PACKET(pAd, pTxBlk->pPacket, NDIS_STATUS_SUCCESS);
-
- return (Status);
-
-}
-
-void RtmpUSB_FinalWriteTxResource(struct rt_rtmp_adapter *pAd,
- struct rt_tx_blk *pTxBlk,
- u16 totalMPDUSize, u16 TxIdx)
-{
- u8 QueIdx;
- struct rt_ht_tx_context *pHTTXContext;
- u32 fillOffset;
- struct rt_txinfo *pTxInfo;
- struct rt_txwi *pTxWI;
- u32 USBDMApktLen, padding;
- unsigned long IrqFlags;
- u8 *pWirelessPacket;
-
- QueIdx = pTxBlk->QueIdx;
- pHTTXContext = &pAd->TxContext[QueIdx];
-
- RTMP_IRQ_LOCK(&pAd->TxContextQueueLock[QueIdx], IrqFlags);
-
- if (pHTTXContext->bCurWriting == TRUE) {
- fillOffset = pHTTXContext->CurWritePosition;
- if (((pHTTXContext->ENextBulkOutPosition ==
- pHTTXContext->CurWritePosition)
- || ((pHTTXContext->ENextBulkOutPosition - 8) ==
- pHTTXContext->CurWritePosition))
- && (pHTTXContext->bCopySavePad == TRUE))
- pWirelessPacket = (u8 *)(&pHTTXContext->SavedPad[0]);
- else
- pWirelessPacket =
- (u8 *)(&pHTTXContext->TransferBuffer->field.
- WirelessPacket[fillOffset]);
-
- /* */
- /* Update TxInfo->USBDMApktLen , */
- /* the length = TXWI_SIZE + 802.11_hdr + 802.11_hdr_pad + payload_of_all_batch_frames + Bulk-Out-padding */
- /* */
- pTxInfo = (struct rt_txinfo *)(pWirelessPacket);
-
- /* Calculate the bulk-out padding */
- USBDMApktLen = pTxBlk->Priv - TXINFO_SIZE;
- padding = (4 - (USBDMApktLen % 4)) & 0x03; /* round up to 4 byte alignment */
- USBDMApktLen += padding;
-
- pTxInfo->USBDMATxPktLen = USBDMApktLen;
-
- /* */
- /* Update TXWI->MPDUtotalByteCount , */
- /* the length = 802.11 header + payload_of_all_batch_frames */
- pTxWI = (struct rt_txwi *) (pWirelessPacket + TXINFO_SIZE);
- pTxWI->MPDUtotalByteCount = totalMPDUSize;
-
- /* */
- /* Update the pHTTXContext->CurWritePosition */
- /* */
- pHTTXContext->CurWritePosition += (TXINFO_SIZE + USBDMApktLen);
- if ((pHTTXContext->CurWritePosition + 3906) > MAX_TXBULK_LIMIT) { /* Add 3906 for prevent the NextBulkOut packet size is a A-RALINK/A-MSDU Frame. */
- pHTTXContext->CurWritePosition = 8;
- pTxInfo->SwUseLastRound = 1;
- }
- pHTTXContext->CurWriteRealPos = pHTTXContext->CurWritePosition;
-
- /* */
- /* Zero the last padding. */
- /* */
- pWirelessPacket =
- (&pHTTXContext->TransferBuffer->field.
- WirelessPacket[fillOffset + pTxBlk->Priv]);
- NdisZeroMemory(pWirelessPacket, padding + 8);
-
- /* Finally, set bCurWriting as FALSE */
- pHTTXContext->bCurWriting = FALSE;
-
- } else { /* It should not happened now unless we are going to shutdown. */
- DBGPRINT(RT_DEBUG_ERROR,
- ("FinalWriteTxResource():bCurWriting is FALSE when handle last frames.\n"));
- }
-
- RTMP_IRQ_UNLOCK(&pAd->TxContextQueueLock[QueIdx], IrqFlags);
-
-}
-
-void RtmpUSBDataLastTxIdx(struct rt_rtmp_adapter *pAd,
- u8 QueIdx, u16 TxIdx)
-{
- /* DO nothing for USB. */
-}
-
-/*
- When can do bulk-out:
- 1. TxSwFreeIdx < TX_RING_SIZE;
- It means has at least one Ring entity is ready for bulk-out, kick it out.
- 2. If TxSwFreeIdx == TX_RING_SIZE
- Check if the CurWriting flag is FALSE, if it's FALSE, we can do kick out.
-
-*/
-void RtmpUSBDataKickOut(struct rt_rtmp_adapter *pAd,
- struct rt_tx_blk *pTxBlk, u8 QueIdx)
-{
- RTUSB_SET_BULK_FLAG(pAd, (fRTUSB_BULK_OUT_DATA_NORMAL << QueIdx));
- RTUSBKickBulkOut(pAd);
-
-}
-
-/*
- Must be run in Interrupt context
- This function handle RT2870 specific TxDesc and cpu index update and kick the packet out.
- */
-int RtmpUSBMgmtKickOut(struct rt_rtmp_adapter *pAd,
- u8 QueIdx,
- void *pPacket,
- u8 *pSrcBufVA, u32 SrcBufLen)
-{
- struct rt_txinfo *pTxInfo;
- unsigned long BulkOutSize;
- u8 padLen;
- u8 *pDest;
- unsigned long SwIdx = pAd->MgmtRing.TxCpuIdx;
- struct rt_tx_context *pMLMEContext =
- (struct rt_tx_context *)pAd->MgmtRing.Cell[SwIdx].AllocVa;
- unsigned long IrqFlags;
-
- pTxInfo = (struct rt_txinfo *)(pSrcBufVA);
-
- /* Build our URB for USBD */
- BulkOutSize = SrcBufLen;
- BulkOutSize = (BulkOutSize + 3) & (~3);
- RTMPWriteTxInfo(pAd, pTxInfo, (u16)(BulkOutSize - TXINFO_SIZE),
- TRUE, EpToQueue[MGMTPIPEIDX], FALSE, FALSE);
-
- BulkOutSize += 4; /* Always add 4 extra bytes at every packet. */
-
- /* If BulkOutSize is multiple of BulkOutMaxPacketSize, add extra 4 bytes again. */
- if ((BulkOutSize % pAd->BulkOutMaxPacketSize) == 0)
- BulkOutSize += 4;
-
- padLen = BulkOutSize - SrcBufLen;
- ASSERT((padLen <= RTMP_PKT_TAIL_PADDING));
-
- /* Now memzero all extra padding bytes. */
- pDest = (u8 *)(pSrcBufVA + SrcBufLen);
- skb_put(GET_OS_PKT_TYPE(pPacket), padLen);
- NdisZeroMemory(pDest, padLen);
-
- RTMP_IRQ_LOCK(&pAd->MLMEBulkOutLock, IrqFlags);
-
- pAd->MgmtRing.Cell[pAd->MgmtRing.TxCpuIdx].pNdisPacket = pPacket;
- pMLMEContext->TransferBuffer =
- (struct rt_tx_buffer *)(GET_OS_PKT_DATAPTR(pPacket));
-
- /* Length in TxInfo should be 8 less than bulkout size. */
- pMLMEContext->BulkOutSize = BulkOutSize;
- pMLMEContext->InUse = TRUE;
- pMLMEContext->bWaitingBulkOut = TRUE;
-
- /*for debug */
- /*hex_dump("RtmpUSBMgmtKickOut", &pMLMEContext->TransferBuffer->field.WirelessPacket[0], (pMLMEContext->BulkOutSize > 16 ? 16 : pMLMEContext->BulkOutSize)); */
-
- /*pAd->RalinkCounters.KickTxCount++; */
- /*pAd->RalinkCounters.OneSecTxDoneCount++; */
-
- /*if (pAd->MgmtRing.TxSwFreeIdx == MGMT_RING_SIZE) */
- /* needKickOut = TRUE; */
-
- /* Decrease the TxSwFreeIdx and Increase the TX_CTX_IDX */
- pAd->MgmtRing.TxSwFreeIdx--;
- INC_RING_INDEX(pAd->MgmtRing.TxCpuIdx, MGMT_RING_SIZE);
-
- RTMP_IRQ_UNLOCK(&pAd->MLMEBulkOutLock, IrqFlags);
-
- RTUSB_SET_BULK_FLAG(pAd, fRTUSB_BULK_OUT_MLME);
- /*if (needKickOut) */
- RTUSBKickBulkOut(pAd);
-
- return 0;
-}
-
-void RtmpUSBNullFrameKickOut(struct rt_rtmp_adapter *pAd,
- u8 QueIdx,
- u8 * pNullFrame, u32 frameLen)
-{
- if (pAd->NullContext.InUse == FALSE) {
- struct rt_tx_context *pNullContext;
- struct rt_txinfo *pTxInfo;
- struct rt_txwi * pTxWI;
- u8 *pWirelessPkt;
-
- pNullContext = &(pAd->NullContext);
-
- /* Set the in use bit */
- pNullContext->InUse = TRUE;
- pWirelessPkt =
- (u8 *)& pNullContext->TransferBuffer->field.
- WirelessPacket[0];
-
- RTMPZeroMemory(&pWirelessPkt[0], 100);
- pTxInfo = (struct rt_txinfo *)& pWirelessPkt[0];
- RTMPWriteTxInfo(pAd, pTxInfo,
- (u16)(sizeof(struct rt_header_802_11) + TXWI_SIZE),
- TRUE, EpToQueue[MGMTPIPEIDX], FALSE, FALSE);
- pTxInfo->QSEL = FIFO_EDCA;
- pTxWI = (struct rt_txwi *) & pWirelessPkt[TXINFO_SIZE];
- RTMPWriteTxWI(pAd, pTxWI, FALSE, FALSE, FALSE, FALSE, TRUE,
- FALSE, 0, BSSID_WCID, (sizeof(struct rt_header_802_11)), 0,
- 0, (u8)pAd->CommonCfg.MlmeTransmit.field.MCS,
- IFS_HTTXOP, FALSE, &pAd->CommonCfg.MlmeTransmit);
-
- RTMPMoveMemory(&pWirelessPkt[TXWI_SIZE + TXINFO_SIZE],
- &pAd->NullFrame, sizeof(struct rt_header_802_11));
- pAd->NullContext.BulkOutSize =
- TXINFO_SIZE + TXWI_SIZE + sizeof(pAd->NullFrame) + 4;
-
- /* Fill out frame length information for global Bulk out arbitor */
- /*pNullContext->BulkOutSize = TransferBufferLength; */
- DBGPRINT(RT_DEBUG_TRACE,
- ("SYNC - send NULL Frame @%d Mbps...\n",
- RateIdToMbps[pAd->CommonCfg.TxRate]));
- RTUSB_SET_BULK_FLAG(pAd, fRTUSB_BULK_OUT_DATA_NULL);
-
- /* Kick bulk out */
- RTUSBKickBulkOut(pAd);
- }
-
-}
-
-/*
-========================================================================
-Routine Description:
- Get a received packet.
-
-Arguments:
- pAd device control block
- pSaveRxD receive descriptor information
- *pbReschedule need reschedule flag
- *pRxPending pending received packet flag
-
-Return Value:
- the received packet
-
-Note:
-========================================================================
-*/
-void *GetPacketFromRxRing(struct rt_rtmp_adapter *pAd,
- OUT PRT28XX_RXD_STRUC pSaveRxD,
- OUT BOOLEAN * pbReschedule,
- IN u32 * pRxPending)
-{
- struct rt_rx_context *pRxContext;
- void *pSkb;
- u8 *pData;
- unsigned long ThisFrameLen;
- unsigned long RxBufferLength;
- struct rt_rxwi * pRxWI;
-
- pRxContext = &pAd->RxContext[pAd->NextRxBulkInReadIndex];
- if ((pRxContext->Readable == FALSE) || (pRxContext->InUse == TRUE))
- return NULL;
-
- RxBufferLength = pRxContext->BulkInOffset - pAd->ReadPosition;
- if (RxBufferLength <
- (RT2870_RXDMALEN_FIELD_SIZE + sizeof(struct rt_rxwi) +
- sizeof(struct rt_rxinfo))) {
- goto label_null;
- }
-
- pData = &pRxContext->TransferBuffer[pAd->ReadPosition]; /* 4KB */
- /* The RXDMA field is 4 bytes, now just use the first 2 bytes. The Length including the (RXWI + MSDU + Padding) */
- ThisFrameLen = *pData + (*(pData + 1) << 8);
- if (ThisFrameLen == 0) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("BIRIdx(%d): RXDMALen is zero.[%ld], BulkInBufLen = %ld)\n",
- pAd->NextRxBulkInReadIndex, ThisFrameLen,
- pRxContext->BulkInOffset));
- goto label_null;
- }
- if ((ThisFrameLen & 0x3) != 0) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("BIRIdx(%d): RXDMALen not multiple of 4.[%ld], BulkInBufLen = %ld)\n",
- pAd->NextRxBulkInReadIndex, ThisFrameLen,
- pRxContext->BulkInOffset));
- goto label_null;
- }
-
- if ((ThisFrameLen + 8) > RxBufferLength) /* 8 for (RT2870_RXDMALEN_FIELD_SIZE + sizeof(struct rt_rxinfo)) */
- {
- DBGPRINT(RT_DEBUG_TRACE,
- ("BIRIdx(%d):FrameLen(0x%lx) outranges. BulkInLen=0x%lx, remaining RxBufLen=0x%lx, ReadPos=0x%lx\n",
- pAd->NextRxBulkInReadIndex, ThisFrameLen,
- pRxContext->BulkInOffset, RxBufferLength,
- pAd->ReadPosition));
-
- /* error frame. finish this loop */
- goto label_null;
- }
- /* skip USB frame length field */
- pData += RT2870_RXDMALEN_FIELD_SIZE;
- pRxWI = (struct rt_rxwi *) pData;
- if (pRxWI->MPDUtotalByteCount > ThisFrameLen) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("%s():pRxWIMPDUtotalByteCount(%d) large than RxDMALen(%ld)\n",
- __FUNCTION__, pRxWI->MPDUtotalByteCount,
- ThisFrameLen));
- goto label_null;
- }
- /* allocate a rx packet */
- pSkb = dev_alloc_skb(ThisFrameLen);
- if (pSkb == NULL) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("%s():Cannot Allocate sk buffer for this Bulk-In buffer!\n",
- __FUNCTION__));
- goto label_null;
- }
- /* copy the rx packet */
- memcpy(skb_put(pSkb, ThisFrameLen), pData, ThisFrameLen);
- RTPKT_TO_OSPKT(pSkb)->dev = get_netdev_from_bssid(pAd, BSS0);
- RTMP_SET_PACKET_SOURCE(OSPKT_TO_RTPKT(pSkb), PKTSRC_NDIS);
-
- /* copy RxD */
- *pSaveRxD = *(struct rt_rxinfo *) (pData + ThisFrameLen);
-
- /* update next packet read position. */
- pAd->ReadPosition += (ThisFrameLen + RT2870_RXDMALEN_FIELD_SIZE + RXINFO_SIZE); /* 8 for (RT2870_RXDMALEN_FIELD_SIZE + sizeof(struct rt_rxinfo)) */
-
- return pSkb;
-
-label_null:
-
- return NULL;
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Check Rx descriptor, return NDIS_STATUS_FAILURE if any error dound
-
- Arguments:
- pRxD Pointer to the Rx descriptor
-
- Return Value:
- NDIS_STATUS_SUCCESS No err
- NDIS_STATUS_FAILURE Error
-
- Note:
-
- ========================================================================
-*/
-int RTMPCheckRxError(struct rt_rtmp_adapter *pAd,
- struct rt_header_802_11 * pHeader,
- struct rt_rxwi * pRxWI, IN PRT28XX_RXD_STRUC pRxINFO)
-{
- struct rt_cipher_key *pWpaKey;
- int dBm;
-
- if (pAd->bPromiscuous == TRUE)
- return (NDIS_STATUS_SUCCESS);
- if (pRxINFO == NULL)
- return (NDIS_STATUS_FAILURE);
-
- /* Phy errors & CRC errors */
- if (pRxINFO->Crc) {
- /* Check RSSI for Noise Hist statistic collection. */
- dBm = (int)(pRxWI->RSSI0) - pAd->BbpRssiToDbmDelta;
- if (dBm <= -87)
- pAd->StaCfg.RPIDensity[0] += 1;
- else if (dBm <= -82)
- pAd->StaCfg.RPIDensity[1] += 1;
- else if (dBm <= -77)
- pAd->StaCfg.RPIDensity[2] += 1;
- else if (dBm <= -72)
- pAd->StaCfg.RPIDensity[3] += 1;
- else if (dBm <= -67)
- pAd->StaCfg.RPIDensity[4] += 1;
- else if (dBm <= -62)
- pAd->StaCfg.RPIDensity[5] += 1;
- else if (dBm <= -57)
- pAd->StaCfg.RPIDensity[6] += 1;
- else if (dBm > -57)
- pAd->StaCfg.RPIDensity[7] += 1;
-
- return (NDIS_STATUS_FAILURE);
- }
- /* Add Rx size to channel load counter, we should ignore error counts */
- pAd->StaCfg.CLBusyBytes += (pRxWI->MPDUtotalByteCount + 14);
-
- /* Drop ToDs promiscuous frame, it is opened due to CCX 2 channel load statistics */
- if (pHeader->FC.ToDs) {
- DBGPRINT_RAW(RT_DEBUG_ERROR, ("Err;FC.ToDs\n"));
- return NDIS_STATUS_FAILURE;
- }
- /* Paul 04-03 for OFDM Rx length issue */
- if (pRxWI->MPDUtotalByteCount > MAX_AGGREGATION_SIZE) {
- DBGPRINT_RAW(RT_DEBUG_ERROR, ("received packet too long\n"));
- return NDIS_STATUS_FAILURE;
- }
- /* Drop not U2M frames, can't drop here because we will drop beacon in this case */
- /* I am kind of doubting the U2M bit operation */
- /* if (pRxD->U2M == 0) */
- /* return(NDIS_STATUS_FAILURE); */
-
- /* drop decyption fail frame */
- if (pRxINFO->Decrypted && pRxINFO->CipherErr) {
-
- if (((pRxINFO->CipherErr & 1) == 1)
- && pAd->CommonCfg.bWirelessEvent && INFRA_ON(pAd))
- RTMPSendWirelessEvent(pAd, IW_ICV_ERROR_EVENT_FLAG,
- pAd->MacTab.Content[BSSID_WCID].
- Addr, BSS0, 0);
-
- if (((pRxINFO->CipherErr & 2) == 2)
- && pAd->CommonCfg.bWirelessEvent && INFRA_ON(pAd))
- RTMPSendWirelessEvent(pAd, IW_MIC_ERROR_EVENT_FLAG,
- pAd->MacTab.Content[BSSID_WCID].
- Addr, BSS0, 0);
- /* */
- /* MIC Error */
- /* */
- if ((pRxINFO->CipherErr == 2) && pRxINFO->MyBss) {
- pWpaKey = &pAd->SharedKey[BSS0][pRxWI->KeyIndex];
- RTMPReportMicError(pAd, pWpaKey);
- DBGPRINT_RAW(RT_DEBUG_ERROR, ("Rx MIC Value error\n"));
- }
-
- if (pRxINFO->Decrypted &&
- (pAd->SharedKey[BSS0][pRxWI->KeyIndex].CipherAlg ==
- CIPHER_AES)
- && (pHeader->Sequence == pAd->FragFrame.Sequence)) {
- /* */
- /* Acceptable since the First FragFrame no CipherErr problem. */
- /* */
- return (NDIS_STATUS_SUCCESS);
- }
-
- return (NDIS_STATUS_FAILURE);
- }
-
- return (NDIS_STATUS_SUCCESS);
-}
-
-void RtmpUsbStaAsicForceWakeupTimeout(void *SystemSpecific1,
- void *FunctionContext,
- void *SystemSpecific2,
- void *SystemSpecific3)
-{
- struct rt_rtmp_adapter *pAd = (struct rt_rtmp_adapter *)FunctionContext;
-
- if (pAd && pAd->Mlme.AutoWakeupTimerRunning) {
- AsicSendCommandToMcu(pAd, 0x31, 0xff, 0x00, 0x02);
-
- OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_DOZE);
- pAd->Mlme.AutoWakeupTimerRunning = FALSE;
- }
-}
-
-void RT28xxUsbStaAsicForceWakeup(struct rt_rtmp_adapter *pAd, IN BOOLEAN bFromTx)
-{
- BOOLEAN Canceled;
-
- if (pAd->Mlme.AutoWakeupTimerRunning)
- RTMPCancelTimer(&pAd->Mlme.AutoWakeupTimer, &Canceled);
-
- AsicSendCommandToMcu(pAd, 0x31, 0xff, 0x00, 0x02);
-
- OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_DOZE);
-}
-
-void RT28xxUsbStaAsicSleepThenAutoWakeup(struct rt_rtmp_adapter *pAd,
- u16 TbttNumToNextWakeUp)
-{
-
- /* we have decided to SLEEP, so at least do it for a BEACON period. */
- if (TbttNumToNextWakeUp == 0)
- TbttNumToNextWakeUp = 1;
-
- RTMPSetTimer(&pAd->Mlme.AutoWakeupTimer, AUTO_WAKEUP_TIMEOUT);
- pAd->Mlme.AutoWakeupTimerRunning = TRUE;
-
- AsicSendCommandToMcu(pAd, 0x30, 0xff, 0xff, 0x02); /* send POWER-SAVE command to MCU. Timeout 40us. */
-
- OPSTATUS_SET_FLAG(pAd, fOP_STATUS_DOZE);
-
-}
-
-#endif /* RTMP_MAC_USB // */
diff --git a/drivers/staging/rt2860/common/cmm_info.c b/drivers/staging/rt2860/common/cmm_info.c
deleted file mode 100644
index 25302e8..0000000
--- a/drivers/staging/rt2860/common/cmm_info.c
+++ /dev/null
@@ -1,955 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
- */
-
-#include <linux/sched.h>
-#include "../rt_config.h"
-
-/*
- ========================================================================
-
- Routine Description:
- Remove WPA Key process
-
- Arguments:
- pAd Pointer to our adapter
- pBuf Pointer to the where the key stored
-
- Return Value:
- NDIS_SUCCESS Add key successfully
-
- IRQL = DISPATCH_LEVEL
-
- Note:
-
- ========================================================================
-*/
-void RTMPSetDesiredRates(struct rt_rtmp_adapter *pAdapter, long Rates)
-{
- NDIS_802_11_RATES aryRates;
-
- memset(&aryRates, 0x00, sizeof(NDIS_802_11_RATES));
- switch (pAdapter->CommonCfg.PhyMode) {
- case PHY_11A: /* A only */
- switch (Rates) {
- case 6000000: /*6M */
- aryRates[0] = 0x0c; /* 6M */
- pAdapter->StaCfg.DesiredTransmitSetting.field.MCS =
- MCS_0;
- break;
- case 9000000: /*9M */
- aryRates[0] = 0x12; /* 9M */
- pAdapter->StaCfg.DesiredTransmitSetting.field.MCS =
- MCS_1;
- break;
- case 12000000: /*12M */
- aryRates[0] = 0x18; /* 12M */
- pAdapter->StaCfg.DesiredTransmitSetting.field.MCS =
- MCS_2;
- break;
- case 18000000: /*18M */
- aryRates[0] = 0x24; /* 18M */
- pAdapter->StaCfg.DesiredTransmitSetting.field.MCS =
- MCS_3;
- break;
- case 24000000: /*24M */
- aryRates[0] = 0x30; /* 24M */
- pAdapter->StaCfg.DesiredTransmitSetting.field.MCS =
- MCS_4;
- break;
- case 36000000: /*36M */
- aryRates[0] = 0x48; /* 36M */
- pAdapter->StaCfg.DesiredTransmitSetting.field.MCS =
- MCS_5;
- break;
- case 48000000: /*48M */
- aryRates[0] = 0x60; /* 48M */
- pAdapter->StaCfg.DesiredTransmitSetting.field.MCS =
- MCS_6;
- break;
- case 54000000: /*54M */
- aryRates[0] = 0x6c; /* 54M */
- pAdapter->StaCfg.DesiredTransmitSetting.field.MCS =
- MCS_7;
- break;
- case -1: /*Auto */
- default:
- aryRates[0] = 0x6c; /* 54Mbps */
- aryRates[1] = 0x60; /* 48Mbps */
- aryRates[2] = 0x48; /* 36Mbps */
- aryRates[3] = 0x30; /* 24Mbps */
- aryRates[4] = 0x24; /* 18M */
- aryRates[5] = 0x18; /* 12M */
- aryRates[6] = 0x12; /* 9M */
- aryRates[7] = 0x0c; /* 6M */
- pAdapter->StaCfg.DesiredTransmitSetting.field.MCS =
- MCS_AUTO;
- break;
- }
- break;
- case PHY_11BG_MIXED: /* B/G Mixed */
- case PHY_11B: /* B only */
- case PHY_11ABG_MIXED: /* A/B/G Mixed */
- default:
- switch (Rates) {
- case 1000000: /*1M */
- aryRates[0] = 0x02;
- pAdapter->StaCfg.DesiredTransmitSetting.field.MCS =
- MCS_0;
- break;
- case 2000000: /*2M */
- aryRates[0] = 0x04;
- pAdapter->StaCfg.DesiredTransmitSetting.field.MCS =
- MCS_1;
- break;
- case 5000000: /*5.5M */
- aryRates[0] = 0x0b; /* 5.5M */
- pAdapter->StaCfg.DesiredTransmitSetting.field.MCS =
- MCS_2;
- break;
- case 11000000: /*11M */
- aryRates[0] = 0x16; /* 11M */
- pAdapter->StaCfg.DesiredTransmitSetting.field.MCS =
- MCS_3;
- break;
- case 6000000: /*6M */
- aryRates[0] = 0x0c; /* 6M */
- pAdapter->StaCfg.DesiredTransmitSetting.field.MCS =
- MCS_0;
- break;
- case 9000000: /*9M */
- aryRates[0] = 0x12; /* 9M */
- pAdapter->StaCfg.DesiredTransmitSetting.field.MCS =
- MCS_1;
- break;
- case 12000000: /*12M */
- aryRates[0] = 0x18; /* 12M */
- pAdapter->StaCfg.DesiredTransmitSetting.field.MCS =
- MCS_2;
- break;
- case 18000000: /*18M */
- aryRates[0] = 0x24; /* 18M */
- pAdapter->StaCfg.DesiredTransmitSetting.field.MCS =
- MCS_3;
- break;
- case 24000000: /*24M */
- aryRates[0] = 0x30; /* 24M */
- pAdapter->StaCfg.DesiredTransmitSetting.field.MCS =
- MCS_4;
- break;
- case 36000000: /*36M */
- aryRates[0] = 0x48; /* 36M */
- pAdapter->StaCfg.DesiredTransmitSetting.field.MCS =
- MCS_5;
- break;
- case 48000000: /*48M */
- aryRates[0] = 0x60; /* 48M */
- pAdapter->StaCfg.DesiredTransmitSetting.field.MCS =
- MCS_6;
- break;
- case 54000000: /*54M */
- aryRates[0] = 0x6c; /* 54M */
- pAdapter->StaCfg.DesiredTransmitSetting.field.MCS =
- MCS_7;
- break;
- case -1: /*Auto */
- default:
- if (pAdapter->CommonCfg.PhyMode == PHY_11B) { /*B Only */
- aryRates[0] = 0x16; /* 11Mbps */
- aryRates[1] = 0x0b; /* 5.5Mbps */
- aryRates[2] = 0x04; /* 2Mbps */
- aryRates[3] = 0x02; /* 1Mbps */
- } else { /*(B/G) Mixed or (A/B/G) Mixed */
- aryRates[0] = 0x6c; /* 54Mbps */
- aryRates[1] = 0x60; /* 48Mbps */
- aryRates[2] = 0x48; /* 36Mbps */
- aryRates[3] = 0x30; /* 24Mbps */
- aryRates[4] = 0x16; /* 11Mbps */
- aryRates[5] = 0x0b; /* 5.5Mbps */
- aryRates[6] = 0x04; /* 2Mbps */
- aryRates[7] = 0x02; /* 1Mbps */
- }
- pAdapter->StaCfg.DesiredTransmitSetting.field.MCS =
- MCS_AUTO;
- break;
- }
- break;
- }
-
- NdisZeroMemory(pAdapter->CommonCfg.DesireRate,
- MAX_LEN_OF_SUPPORTED_RATES);
- NdisMoveMemory(pAdapter->CommonCfg.DesireRate, &aryRates,
- sizeof(NDIS_802_11_RATES));
- DBGPRINT(RT_DEBUG_TRACE,
- (" RTMPSetDesiredRates (%02x,%02x,%02x,%02x,%02x,%02x,%02x,%02x)\n",
- pAdapter->CommonCfg.DesireRate[0],
- pAdapter->CommonCfg.DesireRate[1],
- pAdapter->CommonCfg.DesireRate[2],
- pAdapter->CommonCfg.DesireRate[3],
- pAdapter->CommonCfg.DesireRate[4],
- pAdapter->CommonCfg.DesireRate[5],
- pAdapter->CommonCfg.DesireRate[6],
- pAdapter->CommonCfg.DesireRate[7]));
- /* Changing DesiredRate may affect the MAX TX rate we used to TX frames out */
- MlmeUpdateTxRates(pAdapter, FALSE, 0);
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Remove All WPA Keys
-
- Arguments:
- pAd Pointer to our adapter
-
- Return Value:
- None
-
- IRQL = DISPATCH_LEVEL
-
- Note:
-
- ========================================================================
-*/
-void RTMPWPARemoveAllKeys(struct rt_rtmp_adapter *pAd)
-{
-
- u8 i;
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("RTMPWPARemoveAllKeys(AuthMode=%d, WepStatus=%d)\n",
- pAd->StaCfg.AuthMode, pAd->StaCfg.WepStatus));
- RTMP_CLEAR_PSFLAG(pAd, fRTMP_PS_CAN_GO_SLEEP);
- /* For WEP/CKIP, there is no need to remove it, since WinXP won't set it again after */
- /* Link up. And it will be replaced if user changed it. */
- if (pAd->StaCfg.AuthMode < Ndis802_11AuthModeWPA)
- return;
-
- /* For WPA-None, there is no need to remove it, since WinXP won't set it again after */
- /* Link up. And it will be replaced if user changed it. */
- if (pAd->StaCfg.AuthMode == Ndis802_11AuthModeWPANone)
- return;
-
- /* set BSSID wcid entry of the Pair-wise Key table as no-security mode */
- AsicRemovePairwiseKeyEntry(pAd, BSS0, BSSID_WCID);
-
- /* set all shared key mode as no-security. */
- for (i = 0; i < SHARE_KEY_NUM; i++) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("remove %s key #%d\n",
- CipherName[pAd->SharedKey[BSS0][i].CipherAlg], i));
- NdisZeroMemory(&pAd->SharedKey[BSS0][i], sizeof(struct rt_cipher_key));
-
- AsicRemoveSharedKeyEntry(pAd, BSS0, i);
- }
- RTMP_SET_PSFLAG(pAd, fRTMP_PS_CAN_GO_SLEEP);
-}
-
-/*
- ========================================================================
-
- Routine Description:
- As STA's BSSID is a WC too, it uses shared key table.
- This function write correct unicast TX key to ASIC WCID.
- And we still make a copy in our MacTab.Content[BSSID_WCID].PairwiseKey.
- Caller guarantee TKIP/AES always has keyidx = 0. (pairwise key)
- Caller guarantee WEP calls this function when set Txkey, default key index=0~3.
-
- Arguments:
- pAd Pointer to our adapter
- pKey Pointer to the where the key stored
-
- Return Value:
- NDIS_SUCCESS Add key successfully
-
- IRQL = DISPATCH_LEVEL
-
- Note:
-
- ========================================================================
-*/
-/*
- ========================================================================
- Routine Description:
- Change NIC PHY mode. Re-association may be necessary. possible settings
- include - PHY_11B, PHY_11BG_MIXED, PHY_11A, and PHY_11ABG_MIXED
-
- Arguments:
- pAd - Pointer to our adapter
- phymode -
-
- IRQL = PASSIVE_LEVEL
- IRQL = DISPATCH_LEVEL
-
- ========================================================================
-*/
-void RTMPSetPhyMode(struct rt_rtmp_adapter *pAd, unsigned long phymode)
-{
- int i;
- /* the selected phymode must be supported by the RF IC encoded in E2PROM */
-
- /* if no change, do nothing */
- /* bug fix
- if (pAd->CommonCfg.PhyMode == phymode)
- return;
- */
- pAd->CommonCfg.PhyMode = (u8)phymode;
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("RTMPSetPhyMode : PhyMode=%d, channel=%d \n",
- pAd->CommonCfg.PhyMode, pAd->CommonCfg.Channel));
-
- BuildChannelList(pAd);
-
- /* sanity check user setting */
- for (i = 0; i < pAd->ChannelListNum; i++) {
- if (pAd->CommonCfg.Channel == pAd->ChannelList[i].Channel)
- break;
- }
-
- if (i == pAd->ChannelListNum) {
- pAd->CommonCfg.Channel = FirstChannel(pAd);
- DBGPRINT(RT_DEBUG_ERROR,
- ("RTMPSetPhyMode: channel is out of range, use first channel=%d \n",
- pAd->CommonCfg.Channel));
- }
-
- NdisZeroMemory(pAd->CommonCfg.SupRate, MAX_LEN_OF_SUPPORTED_RATES);
- NdisZeroMemory(pAd->CommonCfg.ExtRate, MAX_LEN_OF_SUPPORTED_RATES);
- NdisZeroMemory(pAd->CommonCfg.DesireRate, MAX_LEN_OF_SUPPORTED_RATES);
- switch (phymode) {
- case PHY_11B:
- pAd->CommonCfg.SupRate[0] = 0x82; /* 1 mbps, in units of 0.5 Mbps, basic rate */
- pAd->CommonCfg.SupRate[1] = 0x84; /* 2 mbps, in units of 0.5 Mbps, basic rate */
- pAd->CommonCfg.SupRate[2] = 0x8B; /* 5.5 mbps, in units of 0.5 Mbps, basic rate */
- pAd->CommonCfg.SupRate[3] = 0x96; /* 11 mbps, in units of 0.5 Mbps, basic rate */
- pAd->CommonCfg.SupRateLen = 4;
- pAd->CommonCfg.ExtRateLen = 0;
- pAd->CommonCfg.DesireRate[0] = 2; /* 1 mbps, in units of 0.5 Mbps */
- pAd->CommonCfg.DesireRate[1] = 4; /* 2 mbps, in units of 0.5 Mbps */
- pAd->CommonCfg.DesireRate[2] = 11; /* 5.5 mbps, in units of 0.5 Mbps */
- pAd->CommonCfg.DesireRate[3] = 22; /* 11 mbps, in units of 0.5 Mbps */
- /*pAd->CommonCfg.HTPhyMode.field.MODE = MODE_CCK; // This MODE is only FYI. not use */
- break;
-
- case PHY_11G:
- case PHY_11BG_MIXED:
- case PHY_11ABG_MIXED:
- case PHY_11N_2_4G:
- case PHY_11ABGN_MIXED:
- case PHY_11BGN_MIXED:
- case PHY_11GN_MIXED:
- pAd->CommonCfg.SupRate[0] = 0x82; /* 1 mbps, in units of 0.5 Mbps, basic rate */
- pAd->CommonCfg.SupRate[1] = 0x84; /* 2 mbps, in units of 0.5 Mbps, basic rate */
- pAd->CommonCfg.SupRate[2] = 0x8B; /* 5.5 mbps, in units of 0.5 Mbps, basic rate */
- pAd->CommonCfg.SupRate[3] = 0x96; /* 11 mbps, in units of 0.5 Mbps, basic rate */
- pAd->CommonCfg.SupRate[4] = 0x12; /* 9 mbps, in units of 0.5 Mbps */
- pAd->CommonCfg.SupRate[5] = 0x24; /* 18 mbps, in units of 0.5 Mbps */
- pAd->CommonCfg.SupRate[6] = 0x48; /* 36 mbps, in units of 0.5 Mbps */
- pAd->CommonCfg.SupRate[7] = 0x6c; /* 54 mbps, in units of 0.5 Mbps */
- pAd->CommonCfg.SupRateLen = 8;
- pAd->CommonCfg.ExtRate[0] = 0x0C; /* 6 mbps, in units of 0.5 Mbps */
- pAd->CommonCfg.ExtRate[1] = 0x18; /* 12 mbps, in units of 0.5 Mbps */
- pAd->CommonCfg.ExtRate[2] = 0x30; /* 24 mbps, in units of 0.5 Mbps */
- pAd->CommonCfg.ExtRate[3] = 0x60; /* 48 mbps, in units of 0.5 Mbps */
- pAd->CommonCfg.ExtRateLen = 4;
- pAd->CommonCfg.DesireRate[0] = 2; /* 1 mbps, in units of 0.5 Mbps */
- pAd->CommonCfg.DesireRate[1] = 4; /* 2 mbps, in units of 0.5 Mbps */
- pAd->CommonCfg.DesireRate[2] = 11; /* 5.5 mbps, in units of 0.5 Mbps */
- pAd->CommonCfg.DesireRate[3] = 22; /* 11 mbps, in units of 0.5 Mbps */
- pAd->CommonCfg.DesireRate[4] = 12; /* 6 mbps, in units of 0.5 Mbps */
- pAd->CommonCfg.DesireRate[5] = 18; /* 9 mbps, in units of 0.5 Mbps */
- pAd->CommonCfg.DesireRate[6] = 24; /* 12 mbps, in units of 0.5 Mbps */
- pAd->CommonCfg.DesireRate[7] = 36; /* 18 mbps, in units of 0.5 Mbps */
- pAd->CommonCfg.DesireRate[8] = 48; /* 24 mbps, in units of 0.5 Mbps */
- pAd->CommonCfg.DesireRate[9] = 72; /* 36 mbps, in units of 0.5 Mbps */
- pAd->CommonCfg.DesireRate[10] = 96; /* 48 mbps, in units of 0.5 Mbps */
- pAd->CommonCfg.DesireRate[11] = 108; /* 54 mbps, in units of 0.5 Mbps */
- break;
-
- case PHY_11A:
- case PHY_11AN_MIXED:
- case PHY_11AGN_MIXED:
- case PHY_11N_5G:
- pAd->CommonCfg.SupRate[0] = 0x8C; /* 6 mbps, in units of 0.5 Mbps, basic rate */
- pAd->CommonCfg.SupRate[1] = 0x12; /* 9 mbps, in units of 0.5 Mbps */
- pAd->CommonCfg.SupRate[2] = 0x98; /* 12 mbps, in units of 0.5 Mbps, basic rate */
- pAd->CommonCfg.SupRate[3] = 0x24; /* 18 mbps, in units of 0.5 Mbps */
- pAd->CommonCfg.SupRate[4] = 0xb0; /* 24 mbps, in units of 0.5 Mbps, basic rate */
- pAd->CommonCfg.SupRate[5] = 0x48; /* 36 mbps, in units of 0.5 Mbps */
- pAd->CommonCfg.SupRate[6] = 0x60; /* 48 mbps, in units of 0.5 Mbps */
- pAd->CommonCfg.SupRate[7] = 0x6c; /* 54 mbps, in units of 0.5 Mbps */
- pAd->CommonCfg.SupRateLen = 8;
- pAd->CommonCfg.ExtRateLen = 0;
- pAd->CommonCfg.DesireRate[0] = 12; /* 6 mbps, in units of 0.5 Mbps */
- pAd->CommonCfg.DesireRate[1] = 18; /* 9 mbps, in units of 0.5 Mbps */
- pAd->CommonCfg.DesireRate[2] = 24; /* 12 mbps, in units of 0.5 Mbps */
- pAd->CommonCfg.DesireRate[3] = 36; /* 18 mbps, in units of 0.5 Mbps */
- pAd->CommonCfg.DesireRate[4] = 48; /* 24 mbps, in units of 0.5 Mbps */
- pAd->CommonCfg.DesireRate[5] = 72; /* 36 mbps, in units of 0.5 Mbps */
- pAd->CommonCfg.DesireRate[6] = 96; /* 48 mbps, in units of 0.5 Mbps */
- pAd->CommonCfg.DesireRate[7] = 108; /* 54 mbps, in units of 0.5 Mbps */
- /*pAd->CommonCfg.HTPhyMode.field.MODE = MODE_OFDM; // This MODE is only FYI. not use */
- break;
-
- default:
- break;
- }
-
- pAd->CommonCfg.BandState = UNKNOWN_BAND;
-}
-
-/*
- ========================================================================
- Routine Description:
- Caller ensures we has 802.11n support.
- Calls at setting HT from AP/STASetinformation
-
- Arguments:
- pAd - Pointer to our adapter
- phymode -
-
- ========================================================================
-*/
-void RTMPSetHT(struct rt_rtmp_adapter *pAd, struct rt_oid_set_ht_phymode *pHTPhyMode)
-{
- /*unsigned long *pmcs; */
- u32 Value = 0;
- u8 BBPValue = 0;
- u8 BBP3Value = 0;
- u8 RxStream = pAd->CommonCfg.RxStream;
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("RTMPSetHT : HT_mode(%d), ExtOffset(%d), MCS(%d), BW(%d), STBC(%d), SHORTGI(%d)\n",
- pHTPhyMode->HtMode, pHTPhyMode->ExtOffset, pHTPhyMode->MCS,
- pHTPhyMode->BW, pHTPhyMode->STBC, pHTPhyMode->SHORTGI));
-
- /* Don't zero supportedHyPhy structure. */
- RTMPZeroMemory(&pAd->CommonCfg.HtCapability,
- sizeof(pAd->CommonCfg.HtCapability));
- RTMPZeroMemory(&pAd->CommonCfg.AddHTInfo,
- sizeof(pAd->CommonCfg.AddHTInfo));
- RTMPZeroMemory(&pAd->CommonCfg.NewExtChanOffset,
- sizeof(pAd->CommonCfg.NewExtChanOffset));
- RTMPZeroMemory(&pAd->CommonCfg.DesiredHtPhy,
- sizeof(pAd->CommonCfg.DesiredHtPhy));
-
- if (pAd->CommonCfg.bRdg) {
- pAd->CommonCfg.HtCapability.ExtHtCapInfo.PlusHTC = 1;
- pAd->CommonCfg.HtCapability.ExtHtCapInfo.RDGSupport = 1;
- } else {
- pAd->CommonCfg.HtCapability.ExtHtCapInfo.PlusHTC = 0;
- pAd->CommonCfg.HtCapability.ExtHtCapInfo.RDGSupport = 0;
- }
-
- pAd->CommonCfg.HtCapability.HtCapParm.MaxRAmpduFactor = 3;
- pAd->CommonCfg.DesiredHtPhy.MaxRAmpduFactor = 3;
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("RTMPSetHT : RxBAWinLimit = %d\n",
- pAd->CommonCfg.BACapability.field.RxBAWinLimit));
-
- /* Mimo power save, A-MSDU size, */
- pAd->CommonCfg.DesiredHtPhy.AmsduEnable =
- (u16)pAd->CommonCfg.BACapability.field.AmsduEnable;
- pAd->CommonCfg.DesiredHtPhy.AmsduSize =
- (u8)pAd->CommonCfg.BACapability.field.AmsduSize;
- pAd->CommonCfg.DesiredHtPhy.MimoPs =
- (u8)pAd->CommonCfg.BACapability.field.MMPSmode;
- pAd->CommonCfg.DesiredHtPhy.MpduDensity =
- (u8)pAd->CommonCfg.BACapability.field.MpduDensity;
-
- pAd->CommonCfg.HtCapability.HtCapInfo.AMsduSize =
- (u16)pAd->CommonCfg.BACapability.field.AmsduSize;
- pAd->CommonCfg.HtCapability.HtCapInfo.MimoPs =
- (u16)pAd->CommonCfg.BACapability.field.MMPSmode;
- pAd->CommonCfg.HtCapability.HtCapParm.MpduDensity =
- (u8)pAd->CommonCfg.BACapability.field.MpduDensity;
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("RTMPSetHT : AMsduSize = %d, MimoPs = %d, MpduDensity = %d, MaxRAmpduFactor = %d\n",
- pAd->CommonCfg.DesiredHtPhy.AmsduSize,
- pAd->CommonCfg.DesiredHtPhy.MimoPs,
- pAd->CommonCfg.DesiredHtPhy.MpduDensity,
- pAd->CommonCfg.DesiredHtPhy.MaxRAmpduFactor));
-
- if (pHTPhyMode->HtMode == HTMODE_GF) {
- pAd->CommonCfg.HtCapability.HtCapInfo.GF = 1;
- pAd->CommonCfg.DesiredHtPhy.GF = 1;
- } else
- pAd->CommonCfg.DesiredHtPhy.GF = 0;
-
- /* Decide Rx MCSSet */
- switch (RxStream) {
- case 1:
- pAd->CommonCfg.HtCapability.MCSSet[0] = 0xff;
- pAd->CommonCfg.HtCapability.MCSSet[1] = 0x00;
- break;
-
- case 2:
- pAd->CommonCfg.HtCapability.MCSSet[0] = 0xff;
- pAd->CommonCfg.HtCapability.MCSSet[1] = 0xff;
- break;
-
- case 3: /* 3*3 */
- pAd->CommonCfg.HtCapability.MCSSet[0] = 0xff;
- pAd->CommonCfg.HtCapability.MCSSet[1] = 0xff;
- pAd->CommonCfg.HtCapability.MCSSet[2] = 0xff;
- break;
- }
-
- if (pAd->CommonCfg.bForty_Mhz_Intolerant
- && (pAd->CommonCfg.Channel <= 14) && (pHTPhyMode->BW == BW_40)) {
- pHTPhyMode->BW = BW_20;
- pAd->CommonCfg.HtCapability.HtCapInfo.Forty_Mhz_Intolerant = 1;
- }
-
- if (pHTPhyMode->BW == BW_40) {
- pAd->CommonCfg.HtCapability.MCSSet[4] = 0x1; /* MCS 32 */
- pAd->CommonCfg.HtCapability.HtCapInfo.ChannelWidth = 1;
- if (pAd->CommonCfg.Channel <= 14)
- pAd->CommonCfg.HtCapability.HtCapInfo.CCKmodein40 = 1;
-
- pAd->CommonCfg.DesiredHtPhy.ChannelWidth = 1;
- pAd->CommonCfg.AddHTInfo.AddHtInfo.RecomWidth = 1;
- pAd->CommonCfg.AddHTInfo.AddHtInfo.ExtChanOffset =
- (pHTPhyMode->ExtOffset ==
- EXTCHA_BELOW) ? (EXTCHA_BELOW) : EXTCHA_ABOVE;
- /* Set Regsiter for extension channel position. */
- RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value);
- RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &BBP3Value);
- if ((pHTPhyMode->ExtOffset == EXTCHA_BELOW)) {
- Value |= 0x1;
- BBP3Value |= (0x20);
- RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value);
- } else if ((pHTPhyMode->ExtOffset == EXTCHA_ABOVE)) {
- Value &= 0xfe;
- BBP3Value &= (~0x20);
- RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value);
- }
- /* Turn on BBP 40MHz mode now only as AP . */
- /* Sta can turn on BBP 40MHz after connection with 40MHz AP. Sta only broadcast 40MHz capability before connection. */
- if ((pAd->OpMode == OPMODE_AP) || INFRA_ON(pAd) || ADHOC_ON(pAd)
- ) {
- RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &BBPValue);
- BBPValue &= (~0x18);
- BBPValue |= 0x10;
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, BBPValue);
-
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BBP3Value);
- pAd->CommonCfg.BBPCurrentBW = BW_40;
- }
- } else {
- pAd->CommonCfg.HtCapability.HtCapInfo.ChannelWidth = 0;
- pAd->CommonCfg.DesiredHtPhy.ChannelWidth = 0;
- pAd->CommonCfg.AddHTInfo.AddHtInfo.RecomWidth = 0;
- pAd->CommonCfg.AddHTInfo.AddHtInfo.ExtChanOffset = EXTCHA_NONE;
- pAd->CommonCfg.CentralChannel = pAd->CommonCfg.Channel;
- /* Turn on BBP 20MHz mode by request here. */
- {
- RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &BBPValue);
- BBPValue &= (~0x18);
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, BBPValue);
- pAd->CommonCfg.BBPCurrentBW = BW_20;
- }
- }
-
- if (pHTPhyMode->STBC == STBC_USE) {
- pAd->CommonCfg.HtCapability.HtCapInfo.TxSTBC = 1;
- pAd->CommonCfg.DesiredHtPhy.TxSTBC = 1;
- pAd->CommonCfg.HtCapability.HtCapInfo.RxSTBC = 1;
- pAd->CommonCfg.DesiredHtPhy.RxSTBC = 1;
- } else {
- pAd->CommonCfg.DesiredHtPhy.TxSTBC = 0;
- pAd->CommonCfg.DesiredHtPhy.RxSTBC = 0;
- }
-
- if (pHTPhyMode->SHORTGI == GI_400) {
- pAd->CommonCfg.HtCapability.HtCapInfo.ShortGIfor20 = 1;
- pAd->CommonCfg.HtCapability.HtCapInfo.ShortGIfor40 = 1;
- pAd->CommonCfg.DesiredHtPhy.ShortGIfor20 = 1;
- pAd->CommonCfg.DesiredHtPhy.ShortGIfor40 = 1;
- } else {
- pAd->CommonCfg.HtCapability.HtCapInfo.ShortGIfor20 = 0;
- pAd->CommonCfg.HtCapability.HtCapInfo.ShortGIfor40 = 0;
- pAd->CommonCfg.DesiredHtPhy.ShortGIfor20 = 0;
- pAd->CommonCfg.DesiredHtPhy.ShortGIfor40 = 0;
- }
-
- /* We support link adaptation for unsolicit MCS feedback, set to 2. */
- pAd->CommonCfg.HtCapability.ExtHtCapInfo.MCSFeedback = MCSFBK_NONE; /*MCSFBK_UNSOLICIT; */
- pAd->CommonCfg.AddHTInfo.ControlChan = pAd->CommonCfg.Channel;
- /* 1, the extension channel above the control channel. */
-
- /* EDCA parameters used for AP's own transmission */
- if (pAd->CommonCfg.APEdcaParm.bValid == FALSE) {
- pAd->CommonCfg.APEdcaParm.bValid = TRUE;
- pAd->CommonCfg.APEdcaParm.Aifsn[0] = 3;
- pAd->CommonCfg.APEdcaParm.Aifsn[1] = 7;
- pAd->CommonCfg.APEdcaParm.Aifsn[2] = 1;
- pAd->CommonCfg.APEdcaParm.Aifsn[3] = 1;
-
- pAd->CommonCfg.APEdcaParm.Cwmin[0] = 4;
- pAd->CommonCfg.APEdcaParm.Cwmin[1] = 4;
- pAd->CommonCfg.APEdcaParm.Cwmin[2] = 3;
- pAd->CommonCfg.APEdcaParm.Cwmin[3] = 2;
-
- pAd->CommonCfg.APEdcaParm.Cwmax[0] = 6;
- pAd->CommonCfg.APEdcaParm.Cwmax[1] = 10;
- pAd->CommonCfg.APEdcaParm.Cwmax[2] = 4;
- pAd->CommonCfg.APEdcaParm.Cwmax[3] = 3;
-
- pAd->CommonCfg.APEdcaParm.Txop[0] = 0;
- pAd->CommonCfg.APEdcaParm.Txop[1] = 0;
- pAd->CommonCfg.APEdcaParm.Txop[2] = 94;
- pAd->CommonCfg.APEdcaParm.Txop[3] = 47;
- }
- AsicSetEdcaParm(pAd, &pAd->CommonCfg.APEdcaParm);
-
- {
- RTMPSetIndividualHT(pAd, 0);
- }
-
-}
-
-/*
- ========================================================================
- Routine Description:
- Caller ensures we has 802.11n support.
- Calls at setting HT from AP/STASetinformation
-
- Arguments:
- pAd - Pointer to our adapter
- phymode -
-
- ========================================================================
-*/
-void RTMPSetIndividualHT(struct rt_rtmp_adapter *pAd, u8 apidx)
-{
- struct rt_ht_phy_info *pDesired_ht_phy = NULL;
- u8 TxStream = pAd->CommonCfg.TxStream;
- u8 DesiredMcs = MCS_AUTO;
-
- do {
- {
- pDesired_ht_phy = &pAd->StaCfg.DesiredHtPhyInfo;
- DesiredMcs =
- pAd->StaCfg.DesiredTransmitSetting.field.MCS;
- /*pAd->StaCfg.bAutoTxRateSwitch = (DesiredMcs == MCS_AUTO) ? TRUE : FALSE; */
- break;
- }
- } while (FALSE);
-
- if (pDesired_ht_phy == NULL) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("RTMPSetIndividualHT: invalid apidx(%d)\n", apidx));
- return;
- }
- RTMPZeroMemory(pDesired_ht_phy, sizeof(struct rt_ht_phy_info));
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("RTMPSetIndividualHT : Desired MCS = %d\n", DesiredMcs));
- /* Check the validity of MCS */
- if ((TxStream == 1)
- && ((DesiredMcs >= MCS_8) && (DesiredMcs <= MCS_15))) {
- DBGPRINT(RT_DEBUG_WARN,
- ("RTMPSetIndividualHT: MCS(%d) is invalid in 1S, reset it as MCS_7\n",
- DesiredMcs));
- DesiredMcs = MCS_7;
- }
-
- if ((pAd->CommonCfg.DesiredHtPhy.ChannelWidth == BW_20)
- && (DesiredMcs == MCS_32)) {
- DBGPRINT(RT_DEBUG_WARN,
- ("RTMPSetIndividualHT: MCS_32 is only supported in 40-MHz, reset it as MCS_0\n"));
- DesiredMcs = MCS_0;
- }
-
- pDesired_ht_phy->bHtEnable = TRUE;
-
- /* Decide desired Tx MCS */
- switch (TxStream) {
- case 1:
- if (DesiredMcs == MCS_AUTO) {
- pDesired_ht_phy->MCSSet[0] = 0xff;
- pDesired_ht_phy->MCSSet[1] = 0x00;
- } else if (DesiredMcs <= MCS_7) {
- pDesired_ht_phy->MCSSet[0] = 1 << DesiredMcs;
- pDesired_ht_phy->MCSSet[1] = 0x00;
- }
- break;
-
- case 2:
- if (DesiredMcs == MCS_AUTO) {
- pDesired_ht_phy->MCSSet[0] = 0xff;
- pDesired_ht_phy->MCSSet[1] = 0xff;
- } else if (DesiredMcs <= MCS_15) {
- unsigned long mode;
-
- mode = DesiredMcs / 8;
- if (mode < 2)
- pDesired_ht_phy->MCSSet[mode] =
- (1 << (DesiredMcs - mode * 8));
- }
- break;
-
- case 3: /* 3*3 */
- if (DesiredMcs == MCS_AUTO) {
- /* MCS0 ~ MCS23, 3 bytes */
- pDesired_ht_phy->MCSSet[0] = 0xff;
- pDesired_ht_phy->MCSSet[1] = 0xff;
- pDesired_ht_phy->MCSSet[2] = 0xff;
- } else if (DesiredMcs <= MCS_23) {
- unsigned long mode;
-
- mode = DesiredMcs / 8;
- if (mode < 3)
- pDesired_ht_phy->MCSSet[mode] =
- (1 << (DesiredMcs - mode * 8));
- }
- break;
- }
-
- if (pAd->CommonCfg.DesiredHtPhy.ChannelWidth == BW_40) {
- if (DesiredMcs == MCS_AUTO || DesiredMcs == MCS_32)
- pDesired_ht_phy->MCSSet[4] = 0x1;
- }
- /* update HT Rate setting */
- if (pAd->OpMode == OPMODE_STA)
- MlmeUpdateHtTxRates(pAd, BSS0);
- else
- MlmeUpdateHtTxRates(pAd, apidx);
-}
-
-/*
- ========================================================================
- Routine Description:
- Update HT IE from our capability.
-
- Arguments:
- Send all HT IE in beacon/probe rsp/assoc rsp/action frame.
-
- ========================================================================
-*/
-void RTMPUpdateHTIE(struct rt_ht_capability *pRtHt,
- u8 * pMcsSet,
- struct rt_ht_capability_ie * pHtCapability,
- struct rt_add_ht_info_ie * pAddHtInfo)
-{
- RTMPZeroMemory(pHtCapability, sizeof(struct rt_ht_capability_ie));
- RTMPZeroMemory(pAddHtInfo, sizeof(struct rt_add_ht_info_ie));
-
- pHtCapability->HtCapInfo.ChannelWidth = pRtHt->ChannelWidth;
- pHtCapability->HtCapInfo.MimoPs = pRtHt->MimoPs;
- pHtCapability->HtCapInfo.GF = pRtHt->GF;
- pHtCapability->HtCapInfo.ShortGIfor20 = pRtHt->ShortGIfor20;
- pHtCapability->HtCapInfo.ShortGIfor40 = pRtHt->ShortGIfor40;
- pHtCapability->HtCapInfo.TxSTBC = pRtHt->TxSTBC;
- pHtCapability->HtCapInfo.RxSTBC = pRtHt->RxSTBC;
- pHtCapability->HtCapInfo.AMsduSize = pRtHt->AmsduSize;
- pHtCapability->HtCapParm.MaxRAmpduFactor = pRtHt->MaxRAmpduFactor;
- pHtCapability->HtCapParm.MpduDensity = pRtHt->MpduDensity;
-
- pAddHtInfo->AddHtInfo.ExtChanOffset = pRtHt->ExtChanOffset;
- pAddHtInfo->AddHtInfo.RecomWidth = pRtHt->RecomWidth;
- pAddHtInfo->AddHtInfo2.OperaionMode = pRtHt->OperaionMode;
- pAddHtInfo->AddHtInfo2.NonGfPresent = pRtHt->NonGfPresent;
- RTMPMoveMemory(pAddHtInfo->MCSSet, /*pRtHt->MCSSet */ pMcsSet, 4); /* rt2860 only support MCS max=32, no need to copy all 16 uchar. */
-
- DBGPRINT(RT_DEBUG_TRACE, ("RTMPUpdateHTIE <== \n"));
-}
-
-/*
- ========================================================================
- Description:
- Add Client security information into ASIC WCID table and IVEIV table.
- Return:
- ========================================================================
-*/
-void RTMPAddWcidAttributeEntry(struct rt_rtmp_adapter *pAd,
- u8 BssIdx,
- u8 KeyIdx,
- u8 CipherAlg, struct rt_mac_table_entry *pEntry)
-{
- u32 WCIDAttri = 0;
- u16 offset;
- u8 IVEIV = 0;
- u16 Wcid = 0;
-
- {
- {
- if (BssIdx > BSS0) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("RTMPAddWcidAttributeEntry: The BSS-index(%d) is out of range for Infra link. \n",
- BssIdx));
- return;
- }
- /* 1. In ADHOC mode, the AID is wcid number. And NO mesh link exists. */
- /* 2. In Infra mode, the AID:1 MUST be wcid of infra STA. */
- /* the AID:2~ assign to mesh link entry. */
- if (pEntry)
- Wcid = pEntry->Aid;
- else
- Wcid = MCAST_WCID;
- }
- }
-
- /* Update WCID attribute table */
- offset = MAC_WCID_ATTRIBUTE_BASE + (Wcid * HW_WCID_ATTRI_SIZE);
-
- {
- if (pEntry && pEntry->ValidAsMesh)
- WCIDAttri = (CipherAlg << 1) | PAIRWISEKEYTABLE;
- else
- WCIDAttri = (CipherAlg << 1) | SHAREDKEYTABLE;
- }
-
- RTMP_IO_WRITE32(pAd, offset, WCIDAttri);
-
- /* Update IV/EIV table */
- offset = MAC_IVEIV_TABLE_BASE + (Wcid * HW_IVEIV_ENTRY_SIZE);
-
- /* WPA mode */
- if ((CipherAlg == CIPHER_TKIP) || (CipherAlg == CIPHER_TKIP_NO_MIC)
- || (CipherAlg == CIPHER_AES)) {
- /* Eiv bit on. keyid always is 0 for pairwise key */
- IVEIV = (KeyIdx << 6) | 0x20;
- } else {
- /* WEP KeyIdx is default tx key. */
- IVEIV = (KeyIdx << 6);
- }
-
- /* For key index and ext IV bit, so only need to update the position(offset+3). */
-#ifdef RTMP_MAC_PCI
- RTMP_IO_WRITE8(pAd, offset + 3, IVEIV);
-#endif /* RTMP_MAC_PCI // */
-#ifdef RTMP_MAC_USB
- RTUSBMultiWrite_OneByte(pAd, offset + 3, &IVEIV);
-#endif /* RTMP_MAC_USB // */
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("RTMPAddWcidAttributeEntry: WCID #%d, KeyIndex #%d, Alg=%s\n",
- Wcid, KeyIdx, CipherName[CipherAlg]));
- DBGPRINT(RT_DEBUG_TRACE, (" WCIDAttri = 0x%x \n", WCIDAttri));
-
-}
-
-/*
- ==========================================================================
- Description:
- Parse encryption type
-Arguments:
- pAdapter Pointer to our adapter
- wrq Pointer to the ioctl argument
-
- Return Value:
- None
-
- Note:
- ==========================================================================
-*/
-char *GetEncryptType(char enc)
-{
- if (enc == Ndis802_11WEPDisabled)
- return "NONE";
- if (enc == Ndis802_11WEPEnabled)
- return "WEP";
- if (enc == Ndis802_11Encryption2Enabled)
- return "TKIP";
- if (enc == Ndis802_11Encryption3Enabled)
- return "AES";
- if (enc == Ndis802_11Encryption4Enabled)
- return "TKIPAES";
- else
- return "UNKNOW";
-}
-
-char *GetAuthMode(char auth)
-{
- if (auth == Ndis802_11AuthModeOpen)
- return "OPEN";
- if (auth == Ndis802_11AuthModeShared)
- return "SHARED";
- if (auth == Ndis802_11AuthModeAutoSwitch)
- return "AUTOWEP";
- if (auth == Ndis802_11AuthModeWPA)
- return "WPA";
- if (auth == Ndis802_11AuthModeWPAPSK)
- return "WPAPSK";
- if (auth == Ndis802_11AuthModeWPANone)
- return "WPANONE";
- if (auth == Ndis802_11AuthModeWPA2)
- return "WPA2";
- if (auth == Ndis802_11AuthModeWPA2PSK)
- return "WPA2PSK";
- if (auth == Ndis802_11AuthModeWPA1WPA2)
- return "WPA1WPA2";
- if (auth == Ndis802_11AuthModeWPA1PSKWPA2PSK)
- return "WPA1PSKWPA2PSK";
-
- return "UNKNOW";
-}
-
-int SetCommonHT(struct rt_rtmp_adapter *pAd)
-{
- struct rt_oid_set_ht_phymode SetHT;
-
- if (pAd->CommonCfg.PhyMode < PHY_11ABGN_MIXED)
- return FALSE;
-
- SetHT.PhyMode = pAd->CommonCfg.PhyMode;
- SetHT.TransmitNo = ((u8)pAd->Antenna.field.TxPath);
- SetHT.HtMode = (u8)pAd->CommonCfg.RegTransmitSetting.field.HTMODE;
- SetHT.ExtOffset =
- (u8)pAd->CommonCfg.RegTransmitSetting.field.EXTCHA;
- SetHT.MCS = MCS_AUTO;
- SetHT.BW = (u8)pAd->CommonCfg.RegTransmitSetting.field.BW;
- SetHT.STBC = (u8)pAd->CommonCfg.RegTransmitSetting.field.STBC;
- SetHT.SHORTGI = (u8)pAd->CommonCfg.RegTransmitSetting.field.ShortGI;
-
- RTMPSetHT(pAd, &SetHT);
-
- return TRUE;
-}
-
-char *RTMPGetRalinkEncryModeStr(u16 encryMode)
-{
- switch (encryMode) {
- case Ndis802_11WEPDisabled:
- return "NONE";
- case Ndis802_11WEPEnabled:
- return "WEP";
- case Ndis802_11Encryption2Enabled:
- return "TKIP";
- case Ndis802_11Encryption3Enabled:
- return "AES";
- case Ndis802_11Encryption4Enabled:
- return "TKIPAES";
- default:
- return "UNKNOW";
- }
-}
diff --git a/drivers/staging/rt2860/common/cmm_mac_pci.c b/drivers/staging/rt2860/common/cmm_mac_pci.c
deleted file mode 100644
index d06f0a6..0000000
--- a/drivers/staging/rt2860/common/cmm_mac_pci.c
+++ /dev/null
@@ -1,1661 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-*/
-
-#ifdef RTMP_MAC_PCI
-#include "../rt_config.h"
-
-/*
- ========================================================================
-
- Routine Description:
- Allocate DMA memory blocks for send, receive
-
- Arguments:
- Adapter Pointer to our adapter
-
- Return Value:
- NDIS_STATUS_SUCCESS
- NDIS_STATUS_FAILURE
- NDIS_STATUS_RESOURCES
-
- IRQL = PASSIVE_LEVEL
-
- Note:
-
- ========================================================================
-*/
-int RTMPAllocTxRxRingMemory(struct rt_rtmp_adapter *pAd)
-{
- int Status = NDIS_STATUS_SUCCESS;
- unsigned long RingBasePaHigh;
- unsigned long RingBasePaLow;
- void *RingBaseVa;
- int index, num;
- struct rt_txd * pTxD;
- struct rt_rxd * pRxD;
- unsigned long ErrorValue = 0;
- struct rt_rtmp_tx_ring *pTxRing;
- struct rt_rtmp_dmabuf *pDmaBuf;
- void *pPacket;
-/* PRTMP_REORDERBUF pReorderBuf; */
-
- DBGPRINT(RT_DEBUG_TRACE, ("--> RTMPAllocTxRxRingMemory\n"));
- do {
- /* */
- /* Allocate all ring descriptors, include TxD, RxD, MgmtD. */
- /* Although each size is different, to prevent cacheline and alignment */
- /* issue, I intentional set them all to 64 bytes. */
- /* */
- for (num = 0; num < NUM_OF_TX_RING; num++) {
- unsigned long BufBasePaHigh;
- unsigned long BufBasePaLow;
- void *BufBaseVa;
-
- /* */
- /* Allocate Tx ring descriptor's memory (5 TX rings = 4 ACs + 1 HCCA) */
- /* */
- pAd->TxDescRing[num].AllocSize =
- TX_RING_SIZE * TXD_SIZE;
- RTMP_AllocateTxDescMemory(pAd, num,
- pAd->TxDescRing[num].
- AllocSize, FALSE,
- &pAd->TxDescRing[num].AllocVa,
- &pAd->TxDescRing[num].
- AllocPa);
-
- if (pAd->TxDescRing[num].AllocVa == NULL) {
- ErrorValue = ERRLOG_OUT_OF_SHARED_MEMORY;
- DBGPRINT_ERR("Failed to allocate a big buffer\n");
- Status = NDIS_STATUS_RESOURCES;
- break;
- }
- /* Zero init this memory block */
- NdisZeroMemory(pAd->TxDescRing[num].AllocVa,
- pAd->TxDescRing[num].AllocSize);
-
- /* Save PA & VA for further operation */
- RingBasePaHigh =
- RTMP_GetPhysicalAddressHigh(pAd->TxDescRing[num].
- AllocPa);
- RingBasePaLow =
- RTMP_GetPhysicalAddressLow(pAd->TxDescRing[num].
- AllocPa);
- RingBaseVa = pAd->TxDescRing[num].AllocVa;
-
- /* */
- /* Allocate all 1st TXBuf's memory for this TxRing */
- /* */
- pAd->TxBufSpace[num].AllocSize =
- TX_RING_SIZE * TX_DMA_1ST_BUFFER_SIZE;
- RTMP_AllocateFirstTxBuffer(pAd, num,
- pAd->TxBufSpace[num].
- AllocSize, FALSE,
- &pAd->TxBufSpace[num].
- AllocVa,
- &pAd->TxBufSpace[num].
- AllocPa);
-
- if (pAd->TxBufSpace[num].AllocVa == NULL) {
- ErrorValue = ERRLOG_OUT_OF_SHARED_MEMORY;
- DBGPRINT_ERR("Failed to allocate a big buffer\n");
- Status = NDIS_STATUS_RESOURCES;
- break;
- }
- /* Zero init this memory block */
- NdisZeroMemory(pAd->TxBufSpace[num].AllocVa,
- pAd->TxBufSpace[num].AllocSize);
-
- /* Save PA & VA for further operation */
- BufBasePaHigh =
- RTMP_GetPhysicalAddressHigh(pAd->TxBufSpace[num].
- AllocPa);
- BufBasePaLow =
- RTMP_GetPhysicalAddressLow(pAd->TxBufSpace[num].
- AllocPa);
- BufBaseVa = pAd->TxBufSpace[num].AllocVa;
-
- /* */
- /* Initialize Tx Ring Descriptor and associated buffer memory */
- /* */
- pTxRing = &pAd->TxRing[num];
- for (index = 0; index < TX_RING_SIZE; index++) {
- pTxRing->Cell[index].pNdisPacket = NULL;
- pTxRing->Cell[index].pNextNdisPacket = NULL;
- /* Init Tx Ring Size, Va, Pa variables */
- pTxRing->Cell[index].AllocSize = TXD_SIZE;
- pTxRing->Cell[index].AllocVa = RingBaseVa;
- RTMP_SetPhysicalAddressHigh(pTxRing->
- Cell[index].AllocPa,
- RingBasePaHigh);
- RTMP_SetPhysicalAddressLow(pTxRing->Cell[index].
- AllocPa,
- RingBasePaLow);
-
- /* Setup Tx Buffer size & address. only 802.11 header will store in this space */
- pDmaBuf = &pTxRing->Cell[index].DmaBuf;
- pDmaBuf->AllocSize = TX_DMA_1ST_BUFFER_SIZE;
- pDmaBuf->AllocVa = BufBaseVa;
- RTMP_SetPhysicalAddressHigh(pDmaBuf->AllocPa,
- BufBasePaHigh);
- RTMP_SetPhysicalAddressLow(pDmaBuf->AllocPa,
- BufBasePaLow);
-
- /* link the pre-allocated TxBuf to TXD */
- pTxD =
- (struct rt_txd *) pTxRing->Cell[index].AllocVa;
- pTxD->SDPtr0 = BufBasePaLow;
- /* advance to next ring descriptor address */
- pTxD->DMADONE = 1;
- RingBasePaLow += TXD_SIZE;
- RingBaseVa = (u8 *)RingBaseVa + TXD_SIZE;
-
- /* advance to next TxBuf address */
- BufBasePaLow += TX_DMA_1ST_BUFFER_SIZE;
- BufBaseVa =
- (u8 *)BufBaseVa + TX_DMA_1ST_BUFFER_SIZE;
- }
- DBGPRINT(RT_DEBUG_TRACE,
- ("TxRing[%d]: total %d entry allocated\n", num,
- index));
- }
- if (Status == NDIS_STATUS_RESOURCES)
- break;
-
- /* */
- /* Allocate MGMT ring descriptor's memory except Tx ring which allocated eariler */
- /* */
- pAd->MgmtDescRing.AllocSize = MGMT_RING_SIZE * TXD_SIZE;
- RTMP_AllocateMgmtDescMemory(pAd,
- pAd->MgmtDescRing.AllocSize,
- FALSE,
- &pAd->MgmtDescRing.AllocVa,
- &pAd->MgmtDescRing.AllocPa);
-
- if (pAd->MgmtDescRing.AllocVa == NULL) {
- ErrorValue = ERRLOG_OUT_OF_SHARED_MEMORY;
- DBGPRINT_ERR("Failed to allocate a big buffer\n");
- Status = NDIS_STATUS_RESOURCES;
- break;
- }
- /* Zero init this memory block */
- NdisZeroMemory(pAd->MgmtDescRing.AllocVa,
- pAd->MgmtDescRing.AllocSize);
-
- /* Save PA & VA for further operation */
- RingBasePaHigh =
- RTMP_GetPhysicalAddressHigh(pAd->MgmtDescRing.AllocPa);
- RingBasePaLow =
- RTMP_GetPhysicalAddressLow(pAd->MgmtDescRing.AllocPa);
- RingBaseVa = pAd->MgmtDescRing.AllocVa;
-
- /* */
- /* Initialize MGMT Ring and associated buffer memory */
- /* */
- for (index = 0; index < MGMT_RING_SIZE; index++) {
- pAd->MgmtRing.Cell[index].pNdisPacket = NULL;
- pAd->MgmtRing.Cell[index].pNextNdisPacket = NULL;
- /* Init MGMT Ring Size, Va, Pa variables */
- pAd->MgmtRing.Cell[index].AllocSize = TXD_SIZE;
- pAd->MgmtRing.Cell[index].AllocVa = RingBaseVa;
- RTMP_SetPhysicalAddressHigh(pAd->MgmtRing.Cell[index].
- AllocPa, RingBasePaHigh);
- RTMP_SetPhysicalAddressLow(pAd->MgmtRing.Cell[index].
- AllocPa, RingBasePaLow);
-
- /* Offset to next ring descriptor address */
- RingBasePaLow += TXD_SIZE;
- RingBaseVa = (u8 *)RingBaseVa + TXD_SIZE;
-
- /* link the pre-allocated TxBuf to TXD */
- pTxD = (struct rt_txd *) pAd->MgmtRing.Cell[index].AllocVa;
- pTxD->DMADONE = 1;
-
- /* no pre-allocated buffer required in MgmtRing for scatter-gather case */
- }
- DBGPRINT(RT_DEBUG_TRACE,
- ("MGMT Ring: total %d entry allocated\n", index));
-
- /* */
- /* Allocate RX ring descriptor's memory except Tx ring which allocated eariler */
- /* */
- pAd->RxDescRing.AllocSize = RX_RING_SIZE * RXD_SIZE;
- RTMP_AllocateRxDescMemory(pAd,
- pAd->RxDescRing.AllocSize,
- FALSE,
- &pAd->RxDescRing.AllocVa,
- &pAd->RxDescRing.AllocPa);
-
- if (pAd->RxDescRing.AllocVa == NULL) {
- ErrorValue = ERRLOG_OUT_OF_SHARED_MEMORY;
- DBGPRINT_ERR("Failed to allocate a big buffer\n");
- Status = NDIS_STATUS_RESOURCES;
- break;
- }
- /* Zero init this memory block */
- NdisZeroMemory(pAd->RxDescRing.AllocVa,
- pAd->RxDescRing.AllocSize);
-
- DBGPRINT(RT_DEBUG_OFF,
- ("RX DESC %p size = %ld\n", pAd->RxDescRing.AllocVa,
- pAd->RxDescRing.AllocSize));
-
- /* Save PA & VA for further operation */
- RingBasePaHigh =
- RTMP_GetPhysicalAddressHigh(pAd->RxDescRing.AllocPa);
- RingBasePaLow =
- RTMP_GetPhysicalAddressLow(pAd->RxDescRing.AllocPa);
- RingBaseVa = pAd->RxDescRing.AllocVa;
-
- /* */
- /* Initialize Rx Ring and associated buffer memory */
- /* */
- for (index = 0; index < RX_RING_SIZE; index++) {
- /* Init RX Ring Size, Va, Pa variables */
- pAd->RxRing.Cell[index].AllocSize = RXD_SIZE;
- pAd->RxRing.Cell[index].AllocVa = RingBaseVa;
- RTMP_SetPhysicalAddressHigh(pAd->RxRing.Cell[index].
- AllocPa, RingBasePaHigh);
- RTMP_SetPhysicalAddressLow(pAd->RxRing.Cell[index].
- AllocPa, RingBasePaLow);
-
- /*NdisZeroMemory(RingBaseVa, RXD_SIZE); */
-
- /* Offset to next ring descriptor address */
- RingBasePaLow += RXD_SIZE;
- RingBaseVa = (u8 *)RingBaseVa + RXD_SIZE;
-
- /* Setup Rx associated Buffer size & allocate share memory */
- pDmaBuf = &pAd->RxRing.Cell[index].DmaBuf;
- pDmaBuf->AllocSize = RX_BUFFER_AGGRESIZE;
- pPacket = RTMP_AllocateRxPacketBuffer(pAd,
- pDmaBuf->
- AllocSize, FALSE,
- &pDmaBuf->AllocVa,
- &pDmaBuf->
- AllocPa);
-
- /* keep allocated rx packet */
- pAd->RxRing.Cell[index].pNdisPacket = pPacket;
-
- /* Error handling */
- if (pDmaBuf->AllocVa == NULL) {
- ErrorValue = ERRLOG_OUT_OF_SHARED_MEMORY;
- DBGPRINT_ERR("Failed to allocate RxRing's 1st buffer\n");
- Status = NDIS_STATUS_RESOURCES;
- break;
- }
- /* Zero init this memory block */
- NdisZeroMemory(pDmaBuf->AllocVa, pDmaBuf->AllocSize);
-
- /* Write RxD buffer address & allocated buffer length */
- pRxD = (struct rt_rxd *) pAd->RxRing.Cell[index].AllocVa;
- pRxD->SDP0 =
- RTMP_GetPhysicalAddressLow(pDmaBuf->AllocPa);
- pRxD->DDONE = 0;
-
- }
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("Rx Ring: total %d entry allocated\n", index));
-
- } while (FALSE);
-
- NdisZeroMemory(&pAd->FragFrame, sizeof(struct rt_fragment_frame));
- pAd->FragFrame.pFragPacket =
- RTMP_AllocateFragPacketBuffer(pAd, RX_BUFFER_NORMSIZE);
-
- if (pAd->FragFrame.pFragPacket == NULL) {
- Status = NDIS_STATUS_RESOURCES;
- }
-
- if (Status != NDIS_STATUS_SUCCESS) {
- /* Log error inforamtion */
- NdisWriteErrorLogEntry(pAd->AdapterHandle,
- NDIS_ERROR_CODE_OUT_OF_RESOURCES,
- 1, ErrorValue);
- }
- /* Following code segment get from original func:NICInitTxRxRingAndBacklogQueue(), now should integrate it to here. */
- {
- DBGPRINT(RT_DEBUG_TRACE,
- ("--> NICInitTxRxRingAndBacklogQueue\n"));
-
-/*
- // Disable DMA.
- RTMP_IO_READ32(pAd, WPDMA_GLO_CFG, &GloCfg.word);
- GloCfg.word &= 0xff0;
- GloCfg.field.EnTXWriteBackDDONE =1;
- RTMP_IO_WRITE32(pAd, WPDMA_GLO_CFG, GloCfg.word);
-*/
-
- /* Initialize all transmit related software queues */
- for (index = 0; index < NUM_OF_TX_RING; index++) {
- InitializeQueueHeader(&pAd->TxSwQueue[index]);
- /* Init TX rings index pointer */
- pAd->TxRing[index].TxSwFreeIdx = 0;
- pAd->TxRing[index].TxCpuIdx = 0;
- /*RTMP_IO_WRITE32(pAd, (TX_CTX_IDX0 + i * 0x10) , pAd->TxRing[i].TX_CTX_IDX); */
- }
-
- /* Init RX Ring index pointer */
- pAd->RxRing.RxSwReadIdx = 0;
- pAd->RxRing.RxCpuIdx = RX_RING_SIZE - 1;
- /*RTMP_IO_WRITE32(pAd, RX_CRX_IDX, pAd->RxRing.RX_CRX_IDX0); */
-
- /* init MGMT ring index pointer */
- pAd->MgmtRing.TxSwFreeIdx = 0;
- pAd->MgmtRing.TxCpuIdx = 0;
-
- pAd->PrivateInfo.TxRingFullCnt = 0;
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("<-- NICInitTxRxRingAndBacklogQueue\n"));
- }
-
- DBGPRINT_S(Status,
- ("<-- RTMPAllocTxRxRingMemory, Status=%x\n", Status));
- return Status;
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Reset NIC Asics. Call after rest DMA. So reset TX_CTX_IDX to zero.
-
- Arguments:
- Adapter Pointer to our adapter
-
- Return Value:
- None
-
- IRQL = PASSIVE_LEVEL
- IRQL = DISPATCH_LEVEL
-
- Note:
- Reset NIC to initial state AS IS system boot up time.
-
- ========================================================================
-*/
-void RTMPRingCleanUp(struct rt_rtmp_adapter *pAd, u8 RingType)
-{
- struct rt_txd * pTxD;
- struct rt_rxd * pRxD;
- struct rt_queue_entry *pEntry;
- void *pPacket;
- int i;
- struct rt_rtmp_tx_ring *pTxRing;
- unsigned long IrqFlags;
- /*u32 RxSwReadIdx; */
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("RTMPRingCleanUp(RingIdx=%d, Pending-NDIS=%ld)\n", RingType,
- pAd->RalinkCounters.PendingNdisPacketCount));
- switch (RingType) {
- case QID_AC_BK:
- case QID_AC_BE:
- case QID_AC_VI:
- case QID_AC_VO:
-
- pTxRing = &pAd->TxRing[RingType];
-
- RTMP_IRQ_LOCK(&pAd->irq_lock, IrqFlags);
- /* We have to clean all descriptors in case some error happened with reset */
- for (i = 0; i < TX_RING_SIZE; i++) /* We have to scan all TX ring */
- {
- pTxD = (struct rt_txd *) pTxRing->Cell[i].AllocVa;
-
- pPacket = (void *)pTxRing->Cell[i].pNdisPacket;
- /* release scatter-and-gather char */
- if (pPacket) {
- RELEASE_NDIS_PACKET(pAd, pPacket,
- NDIS_STATUS_FAILURE);
- pTxRing->Cell[i].pNdisPacket = NULL;
- }
-
- pPacket =
- (void *)pTxRing->Cell[i].pNextNdisPacket;
- /* release scatter-and-gather char */
- if (pPacket) {
- RELEASE_NDIS_PACKET(pAd, pPacket,
- NDIS_STATUS_FAILURE);
- pTxRing->Cell[i].pNextNdisPacket = NULL;
- }
- }
-
- RTMP_IO_READ32(pAd, TX_DTX_IDX0 + RingType * 0x10,
- &pTxRing->TxDmaIdx);
- pTxRing->TxSwFreeIdx = pTxRing->TxDmaIdx;
- pTxRing->TxCpuIdx = pTxRing->TxDmaIdx;
- RTMP_IO_WRITE32(pAd, TX_CTX_IDX0 + RingType * 0x10,
- pTxRing->TxCpuIdx);
-
- RTMP_IRQ_UNLOCK(&pAd->irq_lock, IrqFlags);
-
- RTMP_IRQ_LOCK(&pAd->irq_lock, IrqFlags);
- while (pAd->TxSwQueue[RingType].Head != NULL) {
- pEntry = RemoveHeadQueue(&pAd->TxSwQueue[RingType]);
- pPacket = QUEUE_ENTRY_TO_PACKET(pEntry);
- RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_FAILURE);
- DBGPRINT(RT_DEBUG_TRACE,
- ("Release 1 NDIS packet from s/w backlog queue\n"));
- }
- RTMP_IRQ_UNLOCK(&pAd->irq_lock, IrqFlags);
- break;
-
- case QID_MGMT:
- /* We have to clean all descriptors in case some error happened with reset */
- NdisAcquireSpinLock(&pAd->MgmtRingLock);
-
- for (i = 0; i < MGMT_RING_SIZE; i++) {
- pTxD = (struct rt_txd *) pAd->MgmtRing.Cell[i].AllocVa;
-
- pPacket =
- (void *)pAd->MgmtRing.Cell[i].pNdisPacket;
- /* rlease scatter-and-gather char */
- if (pPacket) {
- PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr0,
- pTxD->SDLen0,
- PCI_DMA_TODEVICE);
- RELEASE_NDIS_PACKET(pAd, pPacket,
- NDIS_STATUS_FAILURE);
- }
- pAd->MgmtRing.Cell[i].pNdisPacket = NULL;
-
- pPacket =
- (void *)pAd->MgmtRing.Cell[i].
- pNextNdisPacket;
- /* release scatter-and-gather char */
- if (pPacket) {
- PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr1,
- pTxD->SDLen1,
- PCI_DMA_TODEVICE);
- RELEASE_NDIS_PACKET(pAd, pPacket,
- NDIS_STATUS_FAILURE);
- }
- pAd->MgmtRing.Cell[i].pNextNdisPacket = NULL;
-
- }
-
- RTMP_IO_READ32(pAd, TX_MGMTDTX_IDX, &pAd->MgmtRing.TxDmaIdx);
- pAd->MgmtRing.TxSwFreeIdx = pAd->MgmtRing.TxDmaIdx;
- pAd->MgmtRing.TxCpuIdx = pAd->MgmtRing.TxDmaIdx;
- RTMP_IO_WRITE32(pAd, TX_MGMTCTX_IDX, pAd->MgmtRing.TxCpuIdx);
-
- NdisReleaseSpinLock(&pAd->MgmtRingLock);
- pAd->RalinkCounters.MgmtRingFullCount = 0;
- break;
-
- case QID_RX:
- /* We have to clean all descriptors in case some error happened with reset */
- NdisAcquireSpinLock(&pAd->RxRingLock);
-
- for (i = 0; i < RX_RING_SIZE; i++) {
- pRxD = (struct rt_rxd *) pAd->RxRing.Cell[i].AllocVa;
- pRxD->DDONE = 0;
- }
-
- RTMP_IO_READ32(pAd, RX_DRX_IDX, &pAd->RxRing.RxDmaIdx);
- pAd->RxRing.RxSwReadIdx = pAd->RxRing.RxDmaIdx;
- pAd->RxRing.RxCpuIdx =
- ((pAd->RxRing.RxDmaIdx ==
- 0) ? (RX_RING_SIZE - 1) : (pAd->RxRing.RxDmaIdx - 1));
- RTMP_IO_WRITE32(pAd, RX_CRX_IDX, pAd->RxRing.RxCpuIdx);
-
- NdisReleaseSpinLock(&pAd->RxRingLock);
- break;
-
- default:
- break;
- }
-}
-
-void RTMPFreeTxRxRingMemory(struct rt_rtmp_adapter *pAd)
-{
- int index, num, j;
- struct rt_rtmp_tx_ring *pTxRing;
- struct rt_txd * pTxD;
- void *pPacket;
- unsigned int IrqFlags;
-
- /*struct os_cookie *pObj =(struct os_cookie *)pAd->OS_Cookie; */
-
- DBGPRINT(RT_DEBUG_TRACE, ("--> RTMPFreeTxRxRingMemory\n"));
-
- /* Free TxSwQueue Packet */
- for (index = 0; index < NUM_OF_TX_RING; index++) {
- struct rt_queue_entry *pEntry;
- void *pPacket;
- struct rt_queue_header *pQueue;
-
- RTMP_IRQ_LOCK(&pAd->irq_lock, IrqFlags);
- pQueue = &pAd->TxSwQueue[index];
- while (pQueue->Head) {
- pEntry = RemoveHeadQueue(pQueue);
- pPacket = QUEUE_ENTRY_TO_PACKET(pEntry);
- RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_FAILURE);
- }
- RTMP_IRQ_UNLOCK(&pAd->irq_lock, IrqFlags);
- }
-
- /* Free Tx Ring Packet */
- for (index = 0; index < NUM_OF_TX_RING; index++) {
- pTxRing = &pAd->TxRing[index];
-
- for (j = 0; j < TX_RING_SIZE; j++) {
- pTxD = (struct rt_txd *) (pTxRing->Cell[j].AllocVa);
- pPacket = pTxRing->Cell[j].pNdisPacket;
-
- if (pPacket) {
- PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr0,
- pTxD->SDLen0,
- PCI_DMA_TODEVICE);
- RELEASE_NDIS_PACKET(pAd, pPacket,
- NDIS_STATUS_SUCCESS);
- }
- /*Always assign pNdisPacket as NULL after clear */
- pTxRing->Cell[j].pNdisPacket = NULL;
-
- pPacket = pTxRing->Cell[j].pNextNdisPacket;
-
- if (pPacket) {
- PCI_UNMAP_SINGLE(pAd, pTxD->SDPtr1,
- pTxD->SDLen1,
- PCI_DMA_TODEVICE);
- RELEASE_NDIS_PACKET(pAd, pPacket,
- NDIS_STATUS_SUCCESS);
- }
- /*Always assign pNextNdisPacket as NULL after clear */
- pTxRing->Cell[pTxRing->TxSwFreeIdx].pNextNdisPacket =
- NULL;
-
- }
- }
-
- for (index = RX_RING_SIZE - 1; index >= 0; index--) {
- if ((pAd->RxRing.Cell[index].DmaBuf.AllocVa)
- && (pAd->RxRing.Cell[index].pNdisPacket)) {
- PCI_UNMAP_SINGLE(pAd,
- pAd->RxRing.Cell[index].DmaBuf.AllocPa,
- pAd->RxRing.Cell[index].DmaBuf.
- AllocSize, PCI_DMA_FROMDEVICE);
- RELEASE_NDIS_PACKET(pAd,
- pAd->RxRing.Cell[index].pNdisPacket,
- NDIS_STATUS_SUCCESS);
- }
- }
- NdisZeroMemory(pAd->RxRing.Cell, RX_RING_SIZE * sizeof(struct rt_rtmp_dmacb));
-
- if (pAd->RxDescRing.AllocVa) {
- RTMP_FreeDescMemory(pAd, pAd->RxDescRing.AllocSize,
- pAd->RxDescRing.AllocVa,
- pAd->RxDescRing.AllocPa);
- }
- NdisZeroMemory(&pAd->RxDescRing, sizeof(struct rt_rtmp_dmabuf));
-
- if (pAd->MgmtDescRing.AllocVa) {
- RTMP_FreeDescMemory(pAd, pAd->MgmtDescRing.AllocSize,
- pAd->MgmtDescRing.AllocVa,
- pAd->MgmtDescRing.AllocPa);
- }
- NdisZeroMemory(&pAd->MgmtDescRing, sizeof(struct rt_rtmp_dmabuf));
-
- for (num = 0; num < NUM_OF_TX_RING; num++) {
- if (pAd->TxBufSpace[num].AllocVa) {
- RTMP_FreeFirstTxBuffer(pAd,
- pAd->TxBufSpace[num].AllocSize,
- FALSE,
- pAd->TxBufSpace[num].AllocVa,
- pAd->TxBufSpace[num].AllocPa);
- }
- NdisZeroMemory(&pAd->TxBufSpace[num], sizeof(struct rt_rtmp_dmabuf));
-
- if (pAd->TxDescRing[num].AllocVa) {
- RTMP_FreeDescMemory(pAd, pAd->TxDescRing[num].AllocSize,
- pAd->TxDescRing[num].AllocVa,
- pAd->TxDescRing[num].AllocPa);
- }
- NdisZeroMemory(&pAd->TxDescRing[num], sizeof(struct rt_rtmp_dmabuf));
- }
-
- if (pAd->FragFrame.pFragPacket)
- RELEASE_NDIS_PACKET(pAd, pAd->FragFrame.pFragPacket,
- NDIS_STATUS_SUCCESS);
-
- DBGPRINT(RT_DEBUG_TRACE, ("<-- RTMPFreeTxRxRingMemory\n"));
-}
-
-/***************************************************************************
- *
- * register related procedures.
- *
- **************************************************************************/
-/*
-========================================================================
-Routine Description:
- Disable DMA.
-
-Arguments:
- *pAd the raxx interface data pointer
-
-Return Value:
- None
-
-Note:
-========================================================================
-*/
-void RT28XXDMADisable(struct rt_rtmp_adapter *pAd)
-{
- WPDMA_GLO_CFG_STRUC GloCfg;
-
- RTMP_IO_READ32(pAd, WPDMA_GLO_CFG, &GloCfg.word);
- GloCfg.word &= 0xff0;
- GloCfg.field.EnTXWriteBackDDONE = 1;
- RTMP_IO_WRITE32(pAd, WPDMA_GLO_CFG, GloCfg.word);
-}
-
-/*
-========================================================================
-Routine Description:
- Enable DMA.
-
-Arguments:
- *pAd the raxx interface data pointer
-
-Return Value:
- None
-
-Note:
-========================================================================
-*/
-void RT28XXDMAEnable(struct rt_rtmp_adapter *pAd)
-{
- WPDMA_GLO_CFG_STRUC GloCfg;
- int i = 0;
-
- RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, 0x4);
- do {
- RTMP_IO_READ32(pAd, WPDMA_GLO_CFG, &GloCfg.word);
- if ((GloCfg.field.TxDMABusy == 0)
- && (GloCfg.field.RxDMABusy == 0))
- break;
-
- DBGPRINT(RT_DEBUG_TRACE, ("==> DMABusy\n"));
- RTMPusecDelay(1000);
- i++;
- } while (i < 200);
-
- RTMPusecDelay(50);
-
- GloCfg.field.EnTXWriteBackDDONE = 1;
- GloCfg.field.WPDMABurstSIZE = 2;
- GloCfg.field.EnableRxDMA = 1;
- GloCfg.field.EnableTxDMA = 1;
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("<== WRITE DMA offset 0x208 = 0x%x\n", GloCfg.word));
- RTMP_IO_WRITE32(pAd, WPDMA_GLO_CFG, GloCfg.word);
-
-}
-
-BOOLEAN AsicCheckCommanOk(struct rt_rtmp_adapter *pAd, u8 Command)
-{
- u32 CmdStatus = 0, CID = 0, i;
- u32 ThisCIDMask = 0;
-
- i = 0;
- do {
- RTMP_IO_READ32(pAd, H2M_MAILBOX_CID, &CID);
- /* Find where the command is. Because this is randomly specified by firmware. */
- if ((CID & CID0MASK) == Command) {
- ThisCIDMask = CID0MASK;
- break;
- } else if ((((CID & CID1MASK) >> 8) & 0xff) == Command) {
- ThisCIDMask = CID1MASK;
- break;
- } else if ((((CID & CID2MASK) >> 16) & 0xff) == Command) {
- ThisCIDMask = CID2MASK;
- break;
- } else if ((((CID & CID3MASK) >> 24) & 0xff) == Command) {
- ThisCIDMask = CID3MASK;
- break;
- }
-
- RTMPusecDelay(100);
- i++;
- } while (i < 200);
-
- /* Get CommandStatus Value */
- RTMP_IO_READ32(pAd, H2M_MAILBOX_STATUS, &CmdStatus);
-
- /* This command's status is at the same position as command. So AND command position's bitmask to read status. */
- if (i < 200) {
- /* If Status is 1, the command is success. */
- if (((CmdStatus & ThisCIDMask) == 0x1)
- || ((CmdStatus & ThisCIDMask) == 0x100)
- || ((CmdStatus & ThisCIDMask) == 0x10000)
- || ((CmdStatus & ThisCIDMask) == 0x1000000)) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("--> AsicCheckCommanOk CID = 0x%x, CmdStatus= 0x%x \n",
- CID, CmdStatus));
- RTMP_IO_WRITE32(pAd, H2M_MAILBOX_STATUS, 0xffffffff);
- RTMP_IO_WRITE32(pAd, H2M_MAILBOX_CID, 0xffffffff);
- return TRUE;
- }
- DBGPRINT(RT_DEBUG_TRACE,
- ("--> AsicCheckCommanFail1 CID = 0x%x, CmdStatus= 0x%x \n",
- CID, CmdStatus));
- } else {
- DBGPRINT(RT_DEBUG_TRACE,
- ("--> AsicCheckCommanFail2 Timeout Command = %d, CmdStatus= 0x%x \n",
- Command, CmdStatus));
- }
- /* Clear Command and Status. */
- RTMP_IO_WRITE32(pAd, H2M_MAILBOX_STATUS, 0xffffffff);
- RTMP_IO_WRITE32(pAd, H2M_MAILBOX_CID, 0xffffffff);
-
- return FALSE;
-}
-
-/*
-========================================================================
-Routine Description:
- Write Beacon buffer to Asic.
-
-Arguments:
- *pAd the raxx interface data pointer
-
-Return Value:
- None
-
-Note:
-========================================================================
-*/
-void RT28xx_UpdateBeaconToAsic(struct rt_rtmp_adapter *pAd,
- int apidx,
- unsigned long FrameLen, unsigned long UpdatePos)
-{
- unsigned long CapInfoPos = 0;
- u8 *ptr, *ptr_update, *ptr_capinfo;
- u32 i;
- BOOLEAN bBcnReq = FALSE;
- u8 bcn_idx = 0;
-
- {
- DBGPRINT(RT_DEBUG_ERROR,
- ("%s() : No valid Interface be found.\n", __func__));
- return;
- }
-
- /*if ((pAd->WdsTab.Mode == WDS_BRIDGE_MODE) */
- /* || ((pAd->ApCfg.MBSSID[apidx].MSSIDDev == NULL) */
- /* || !(pAd->ApCfg.MBSSID[apidx].MSSIDDev->flags & IFF_UP)) */
- /* ) */
- if (bBcnReq == FALSE) {
- /* when the ra interface is down, do not send its beacon frame */
- /* clear all zero */
- for (i = 0; i < TXWI_SIZE; i += 4)
- RTMP_IO_WRITE32(pAd, pAd->BeaconOffset[bcn_idx] + i,
- 0x00);
- } else {
- ptr = (u8 *)& pAd->BeaconTxWI;
- for (i = 0; i < TXWI_SIZE; i += 4) /* 16-byte TXWI field */
- {
- u32 longptr =
- *ptr + (*(ptr + 1) << 8) + (*(ptr + 2) << 16) +
- (*(ptr + 3) << 24);
- RTMP_IO_WRITE32(pAd, pAd->BeaconOffset[bcn_idx] + i,
- longptr);
- ptr += 4;
- }
-
- /* Update CapabilityInfo in Beacon */
- for (i = CapInfoPos; i < (CapInfoPos + 2); i++) {
- RTMP_IO_WRITE8(pAd,
- pAd->BeaconOffset[bcn_idx] + TXWI_SIZE +
- i, *ptr_capinfo);
- ptr_capinfo++;
- }
-
- if (FrameLen > UpdatePos) {
- for (i = UpdatePos; i < (FrameLen); i++) {
- RTMP_IO_WRITE8(pAd,
- pAd->BeaconOffset[bcn_idx] +
- TXWI_SIZE + i, *ptr_update);
- ptr_update++;
- }
- }
-
- }
-
-}
-
-void RT28xxPciStaAsicForceWakeup(struct rt_rtmp_adapter *pAd, IN BOOLEAN bFromTx)
-{
- AUTO_WAKEUP_STRUC AutoWakeupCfg;
-
- if (!OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_DOZE))
- return;
-
- if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_WAKEUP_NOW)) {
- DBGPRINT(RT_DEBUG_TRACE, ("waking up now!\n"));
- return;
- }
-
- OPSTATUS_SET_FLAG(pAd, fOP_STATUS_WAKEUP_NOW);
-
- RTMP_CLEAR_PSFLAG(pAd, fRTMP_PS_GO_TO_SLEEP_NOW);
-
- if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_PCIE_DEVICE)
- && pAd->StaCfg.PSControl.field.EnableNewPS == TRUE) {
- /* Support PCIe Advance Power Save */
- if (bFromTx == TRUE && (pAd->Mlme.bPsPollTimerRunning == TRUE)) {
- pAd->Mlme.bPsPollTimerRunning = FALSE;
- RTMPPCIeLinkCtrlValueRestore(pAd, RESTORE_WAKEUP);
- RTMPusecDelay(3000);
- DBGPRINT(RT_DEBUG_TRACE,
- ("=======AsicForceWakeup===bFromTx\n"));
- }
-
- AutoWakeupCfg.word = 0;
- RTMP_IO_WRITE32(pAd, AUTO_WAKEUP_CFG, AutoWakeupCfg.word);
-
- if (RT28xxPciAsicRadioOn(pAd, DOT11POWERSAVE)) {
-#ifdef PCIE_PS_SUPPORT
- /* add by johnli, RF power sequence setup, load RF normal operation-mode setup */
- if ((IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd))
- && IS_VERSION_AFTER_F(pAd)) {
- struct rt_rtmp_chip_op *pChipOps = &pAd->chipOps;
-
- if (pChipOps->AsicReverseRfFromSleepMode)
- pChipOps->
- AsicReverseRfFromSleepMode(pAd);
- } else
-#endif /* PCIE_PS_SUPPORT // */
- {
- /* end johnli */
- /* In Radio Off, we turn off RF clk, So now need to call ASICSwitchChannel again. */
- if (INFRA_ON(pAd)
- && (pAd->CommonCfg.CentralChannel !=
- pAd->CommonCfg.Channel)
- && (pAd->MlmeAux.HtCapability.HtCapInfo.
- ChannelWidth == BW_40)) {
- /* Must using 40MHz. */
- AsicSwitchChannel(pAd,
- pAd->CommonCfg.
- CentralChannel,
- FALSE);
- AsicLockChannel(pAd,
- pAd->CommonCfg.
- CentralChannel);
- } else {
- /* Must using 20MHz. */
- AsicSwitchChannel(pAd,
- pAd->CommonCfg.
- Channel, FALSE);
- AsicLockChannel(pAd,
- pAd->CommonCfg.Channel);
- }
- }
- }
-#ifdef PCIE_PS_SUPPORT
- /* 3090 MCU Wakeup command needs more time to be stable. */
- /* Before stable, don't issue other MCU command to prevent from firmware error. */
- if (((IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd))
- && IS_VERSION_AFTER_F(pAd)) && IS_VERSION_AFTER_F(pAd)
- && (pAd->StaCfg.PSControl.field.rt30xxPowerMode == 3)
- && (pAd->StaCfg.PSControl.field.EnableNewPS == TRUE)) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("<==RT28xxPciStaAsicForceWakeup::Release the MCU Lock(3090)\n"));
- RTMP_SEM_LOCK(&pAd->McuCmdLock);
- pAd->brt30xxBanMcuCmd = FALSE;
- RTMP_SEM_UNLOCK(&pAd->McuCmdLock);
- }
-#endif /* PCIE_PS_SUPPORT // */
- } else {
- /* PCI, 2860-PCIe */
- DBGPRINT(RT_DEBUG_TRACE,
- ("<==RT28xxPciStaAsicForceWakeup::Original PCI Power Saving\n"));
- AsicSendCommandToMcu(pAd, 0x31, 0xff, 0x00, 0x02);
- AutoWakeupCfg.word = 0;
- RTMP_IO_WRITE32(pAd, AUTO_WAKEUP_CFG, AutoWakeupCfg.word);
- }
-
- OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_DOZE);
- OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_WAKEUP_NOW);
- DBGPRINT(RT_DEBUG_TRACE, ("<=======RT28xxPciStaAsicForceWakeup\n"));
-}
-
-void RT28xxPciStaAsicSleepThenAutoWakeup(struct rt_rtmp_adapter *pAd,
- u16 TbttNumToNextWakeUp)
-{
- BOOLEAN brc;
-
- if (pAd->StaCfg.bRadio == FALSE) {
- OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_DOZE);
- return;
- }
- if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_PCIE_DEVICE)
- && pAd->StaCfg.PSControl.field.EnableNewPS == TRUE) {
- unsigned long Now = 0;
- if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_WAKEUP_NOW)) {
- DBGPRINT(RT_DEBUG_TRACE, ("waking up now!\n"));
- OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_DOZE);
- return;
- }
-
- NdisGetSystemUpTime(&Now);
- /* If last send NULL fram time is too close to this receiving beacon (within 8ms), don't go to sleep for this DTM. */
- /* Because Some AP can't queuing outgoing frames immediately. */
- if (((pAd->Mlme.LastSendNULLpsmTime + 8) >= Now)
- && (pAd->Mlme.LastSendNULLpsmTime <= Now)) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("Now = %lu, LastSendNULLpsmTime=%lu : RxCountSinceLastNULL = %lu. \n",
- Now, pAd->Mlme.LastSendNULLpsmTime,
- pAd->RalinkCounters.RxCountSinceLastNULL));
- return;
- } else if ((pAd->RalinkCounters.RxCountSinceLastNULL > 0)
- &&
- ((pAd->Mlme.LastSendNULLpsmTime +
- pAd->CommonCfg.BeaconPeriod) >= Now)) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("Now = %lu, LastSendNULLpsmTime=%lu: RxCountSinceLastNULL = %lu > 0 \n",
- Now, pAd->Mlme.LastSendNULLpsmTime,
- pAd->RalinkCounters.RxCountSinceLastNULL));
- return;
- }
-
- brc =
- RT28xxPciAsicRadioOff(pAd, DOT11POWERSAVE,
- TbttNumToNextWakeUp);
- if (brc == TRUE)
- OPSTATUS_SET_FLAG(pAd, fOP_STATUS_DOZE);
- } else {
- AUTO_WAKEUP_STRUC AutoWakeupCfg;
- /* we have decided to SLEEP, so at least do it for a BEACON period. */
- if (TbttNumToNextWakeUp == 0)
- TbttNumToNextWakeUp = 1;
-
- /*RTMP_IO_WRITE32(pAd, INT_MASK_CSR, AutoWakeupInt); */
-
- AutoWakeupCfg.word = 0;
- RTMP_IO_WRITE32(pAd, AUTO_WAKEUP_CFG, AutoWakeupCfg.word);
- AutoWakeupCfg.field.NumofSleepingTbtt = TbttNumToNextWakeUp - 1;
- AutoWakeupCfg.field.EnableAutoWakeup = 1;
- AutoWakeupCfg.field.AutoLeadTime = 5;
- RTMP_IO_WRITE32(pAd, AUTO_WAKEUP_CFG, AutoWakeupCfg.word);
- AsicSendCommandToMcu(pAd, 0x30, 0xff, 0xff, 0x00); /* send POWER-SAVE command to MCU. Timeout 40us. */
- OPSTATUS_SET_FLAG(pAd, fOP_STATUS_DOZE);
- DBGPRINT(RT_DEBUG_TRACE,
- ("<-- %s, TbttNumToNextWakeUp=%d \n", __func__,
- TbttNumToNextWakeUp));
- }
-
-}
-
-void PsPollWakeExec(void *SystemSpecific1,
- void *FunctionContext,
- void *SystemSpecific2, void *SystemSpecific3)
-{
- struct rt_rtmp_adapter *pAd = (struct rt_rtmp_adapter *)FunctionContext;
- unsigned long flags;
-
- DBGPRINT(RT_DEBUG_TRACE, ("-->PsPollWakeExec \n"));
- RTMP_INT_LOCK(&pAd->irq_lock, flags);
- if (pAd->Mlme.bPsPollTimerRunning) {
- RTMPPCIeLinkCtrlValueRestore(pAd, RESTORE_WAKEUP);
- }
- pAd->Mlme.bPsPollTimerRunning = FALSE;
- RTMP_INT_UNLOCK(&pAd->irq_lock, flags);
-#ifdef PCIE_PS_SUPPORT
- /* For rt30xx power solution 3, Use software timer to wake up in psm. So call */
- /* AsicForceWakeup here instead of handling twakeup interrupt. */
- if (((IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd))
- && IS_VERSION_AFTER_F(pAd))
- && (pAd->StaCfg.PSControl.field.rt30xxPowerMode == 3)
- && (pAd->StaCfg.PSControl.field.EnableNewPS == TRUE)) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("<--PsPollWakeExec::3090 calls AsicForceWakeup(pAd, DOT11POWERSAVE) in advance \n"));
- AsicForceWakeup(pAd, DOT11POWERSAVE);
- }
-#endif /* PCIE_PS_SUPPORT // */
-}
-
-void RadioOnExec(void *SystemSpecific1,
- void *FunctionContext,
- void *SystemSpecific2, void *SystemSpecific3)
-{
- struct rt_rtmp_adapter *pAd = (struct rt_rtmp_adapter *)FunctionContext;
- struct rt_rtmp_chip_op *pChipOps = &pAd->chipOps;
- WPDMA_GLO_CFG_STRUC DmaCfg;
- BOOLEAN Cancelled;
-
- if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_DOZE)) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("-->RadioOnExec() return on fOP_STATUS_DOZE == TRUE; \n"));
-/*KH Debug: Add the compile flag "RT2860 and condition */
-#ifdef RTMP_PCI_SUPPORT
- if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_PCIE_DEVICE)
- && pAd->StaCfg.PSControl.field.EnableNewPS == TRUE)
- RTMPSetTimer(&pAd->Mlme.RadioOnOffTimer, 10);
-#endif /* RTMP_PCI_SUPPORT // */
- return;
- }
-
- if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_BSS_SCAN_IN_PROGRESS)) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("-->RadioOnExec() return on SCAN_IN_PROGRESS; \n"));
-#ifdef RTMP_PCI_SUPPORT
- if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_PCIE_DEVICE)
- && pAd->StaCfg.PSControl.field.EnableNewPS == TRUE)
- RTMPSetTimer(&pAd->Mlme.RadioOnOffTimer, 10);
-#endif /* RTMP_PCI_SUPPORT // */
- return;
- }
-/*KH Debug: need to check. I add the compile flag "CONFIG_STA_SUPPORT" to enclose the following codes. */
-#ifdef RTMP_PCI_SUPPORT
- if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_PCIE_DEVICE)
- && pAd->StaCfg.PSControl.field.EnableNewPS == TRUE) {
- pAd->Mlme.bPsPollTimerRunning = FALSE;
- RTMPCancelTimer(&pAd->Mlme.PsPollTimer, &Cancelled);
- }
-#endif /* RTMP_PCI_SUPPORT // */
- if (pAd->StaCfg.bRadio == TRUE) {
- pAd->bPCIclkOff = FALSE;
- RTMPRingCleanUp(pAd, QID_AC_BK);
- RTMPRingCleanUp(pAd, QID_AC_BE);
- RTMPRingCleanUp(pAd, QID_AC_VI);
- RTMPRingCleanUp(pAd, QID_AC_VO);
- RTMPRingCleanUp(pAd, QID_MGMT);
- RTMPRingCleanUp(pAd, QID_RX);
-
- /* 2. Send wake up command. */
- AsicSendCommandToMcu(pAd, 0x31, PowerWakeCID, 0x00, 0x02);
- /* 2-1. wait command ok. */
- AsicCheckCommanOk(pAd, PowerWakeCID);
-
- /* When PCI clock is off, don't want to service interrupt. So when back to clock on, enable interrupt. */
- /*RTMP_IO_WRITE32(pAd, INT_MASK_CSR, (DELAYINTMASK|RxINT)); */
- RTMP_ASIC_INTERRUPT_ENABLE(pAd);
-
- /* 3. Enable Tx DMA. */
- RTMP_IO_READ32(pAd, WPDMA_GLO_CFG, &DmaCfg.word);
- DmaCfg.field.EnableTxDMA = 1;
- RTMP_IO_WRITE32(pAd, WPDMA_GLO_CFG, DmaCfg.word);
-
- /* In Radio Off, we turn off RF clk, So now need to call ASICSwitchChannel again. */
- if (INFRA_ON(pAd)
- && (pAd->CommonCfg.CentralChannel != pAd->CommonCfg.Channel)
- && (pAd->MlmeAux.HtCapability.HtCapInfo.ChannelWidth ==
- BW_40)) {
- /* Must using 40MHz. */
- AsicSwitchChannel(pAd, pAd->CommonCfg.CentralChannel,
- FALSE);
- AsicLockChannel(pAd, pAd->CommonCfg.CentralChannel);
- } else {
- /* Must using 20MHz. */
- AsicSwitchChannel(pAd, pAd->CommonCfg.Channel, FALSE);
- AsicLockChannel(pAd, pAd->CommonCfg.Channel);
- }
-
-/*KH Debug:The following codes should be enclosed by RT3090 compile flag */
- if (pChipOps->AsicReverseRfFromSleepMode)
- pChipOps->AsicReverseRfFromSleepMode(pAd);
-
-#ifdef PCIE_PS_SUPPORT
-/* 3090 MCU Wakeup command needs more time to be stable. */
-/* Before stable, don't issue other MCU command to prevent from firmware error. */
- if ((IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd))
- && IS_VERSION_AFTER_F(pAd)
- && (pAd->StaCfg.PSControl.field.rt30xxPowerMode == 3)
- && (pAd->StaCfg.PSControl.field.EnableNewPS == TRUE)) {
- RTMP_SEM_LOCK(&pAd->McuCmdLock);
- pAd->brt30xxBanMcuCmd = FALSE;
- RTMP_SEM_UNLOCK(&pAd->McuCmdLock);
- }
-#endif /* PCIE_PS_SUPPORT // */
-
- /* Clear Radio off flag */
- RTMP_CLEAR_FLAG(pAd, fRTMP_ADAPTER_RADIO_OFF);
-
- /* Set LED */
- RTMPSetLED(pAd, LED_RADIO_ON);
-
- if (pAd->StaCfg.Psm == PWR_ACTIVE) {
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3,
- pAd->StaCfg.BBPR3);
- }
- } else {
- RT28xxPciAsicRadioOff(pAd, GUIRADIO_OFF, 0);
- }
-}
-
-/*
- ==========================================================================
- Description:
- This routine sends command to firmware and turn our chip to wake up mode from power save mode.
- Both RadioOn and .11 power save function needs to call this routine.
- Input:
- Level = GUIRADIO_OFF : call this function is from Radio Off to Radio On. Need to restore PCI host value.
- Level = other value : normal wake up function.
-
- ==========================================================================
- */
-BOOLEAN RT28xxPciAsicRadioOn(struct rt_rtmp_adapter *pAd, u8 Level)
-{
- /*WPDMA_GLO_CFG_STRUC DmaCfg; */
- BOOLEAN Cancelled;
- /*u32 MACValue; */
-
- if (pAd->OpMode == OPMODE_AP && Level == DOT11POWERSAVE)
- return FALSE;
-
- if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_PCIE_DEVICE)) {
- if (pAd->StaCfg.PSControl.field.EnableNewPS == TRUE) {
- pAd->Mlme.bPsPollTimerRunning = FALSE;
- RTMPCancelTimer(&pAd->Mlme.PsPollTimer, &Cancelled);
- }
- if ((pAd->StaCfg.PSControl.field.EnableNewPS == TRUE &&
- (Level == GUIRADIO_OFF || Level == GUI_IDLE_POWER_SAVE)) ||
- RTMP_TEST_PSFLAG(pAd, fRTMP_PS_SET_PCI_CLK_OFF_COMMAND)) {
- /* Some chips don't need to delay 6ms, so copy RTMPPCIePowerLinkCtrlRestore */
- /* return condition here. */
- /*
- if (((pAd->MACVersion&0xffff0000) != 0x28600000)
- && ((pAd->DeviceID == NIC2860_PCIe_DEVICE_ID)
- ||(pAd->DeviceID == NIC2790_PCIe_DEVICE_ID)))
- */
- {
- DBGPRINT(RT_DEBUG_TRACE,
- ("RT28xxPciAsicRadioOn ()\n"));
- /* 1. Set PCI Link Control in Configuration Space. */
- RTMPPCIeLinkCtrlValueRestore(pAd,
- RESTORE_WAKEUP);
- RTMPusecDelay(6000);
- }
- }
- }
-#ifdef PCIE_PS_SUPPORT
- if (!
- (((IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd))
- && IS_VERSION_AFTER_F(pAd)
- && (pAd->StaCfg.PSControl.field.rt30xxPowerMode == 3)
- && (pAd->StaCfg.PSControl.field.EnableNewPS == TRUE))))
-#endif /* PCIE_PS_SUPPORT // */
- {
- pAd->bPCIclkOff = FALSE;
- DBGPRINT(RT_DEBUG_TRACE,
- ("PSM :309xbPCIclkOff == %d\n", pAd->bPCIclkOff));
- }
- /* 2. Send wake up command. */
- AsicSendCommandToMcu(pAd, 0x31, PowerWakeCID, 0x00, 0x02);
- pAd->bPCIclkOff = FALSE;
- /* 2-1. wait command ok. */
- AsicCheckCommanOk(pAd, PowerWakeCID);
- RTMP_ASIC_INTERRUPT_ENABLE(pAd);
-
- RTMP_CLEAR_FLAG(pAd, fRTMP_ADAPTER_IDLE_RADIO_OFF);
- if (Level == GUI_IDLE_POWER_SAVE) {
-#ifdef PCIE_PS_SUPPORT
-
- /* add by johnli, RF power sequence setup, load RF normal operation-mode setup */
- if ((IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd))) {
- struct rt_rtmp_chip_op *pChipOps = &pAd->chipOps;
-
- if (pChipOps->AsicReverseRfFromSleepMode)
- pChipOps->AsicReverseRfFromSleepMode(pAd);
- /* 3090 MCU Wakeup command needs more time to be stable. */
- /* Before stable, don't issue other MCU command to prevent from firmware error. */
- if ((IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd))
- && IS_VERSION_AFTER_F(pAd)
- && (pAd->StaCfg.PSControl.field.rt30xxPowerMode ==
- 3)
- && (pAd->StaCfg.PSControl.field.EnableNewPS ==
- TRUE)) {
- RTMP_SEM_LOCK(&pAd->McuCmdLock);
- pAd->brt30xxBanMcuCmd = FALSE;
- RTMP_SEM_UNLOCK(&pAd->McuCmdLock);
- }
- } else
- /* end johnli */
-#endif /* PCIE_PS_SUPPORT // */
- {
- /* In Radio Off, we turn off RF clk, So now need to call ASICSwitchChannel again. */
- {
- if (INFRA_ON(pAd)
- && (pAd->CommonCfg.CentralChannel !=
- pAd->CommonCfg.Channel)
- && (pAd->MlmeAux.HtCapability.HtCapInfo.
- ChannelWidth == BW_40)) {
- /* Must using 40MHz. */
- AsicSwitchChannel(pAd,
- pAd->CommonCfg.
- CentralChannel,
- FALSE);
- AsicLockChannel(pAd,
- pAd->CommonCfg.
- CentralChannel);
- } else {
- /* Must using 20MHz. */
- AsicSwitchChannel(pAd,
- pAd->CommonCfg.
- Channel, FALSE);
- AsicLockChannel(pAd,
- pAd->CommonCfg.Channel);
- }
- }
-
- }
- }
- return TRUE;
-
-}
-
-/*
- ==========================================================================
- Description:
- This routine sends command to firmware and turn our chip to power save mode.
- Both RadioOff and .11 power save function needs to call this routine.
- Input:
- Level = GUIRADIO_OFF : GUI Radio Off mode
- Level = DOT11POWERSAVE : 802.11 power save mode
- Level = RTMP_HALT : When Disable device.
-
- ==========================================================================
- */
-BOOLEAN RT28xxPciAsicRadioOff(struct rt_rtmp_adapter *pAd,
- u8 Level, u16 TbttNumToNextWakeUp)
-{
- WPDMA_GLO_CFG_STRUC DmaCfg;
- u8 i, tempBBP_R3 = 0;
- BOOLEAN brc = FALSE, Cancelled;
- u32 TbTTTime = 0;
- u32 PsPollTime = 0 /*, MACValue */ ;
- unsigned long BeaconPeriodTime;
- u32 RxDmaIdx, RxCpuIdx;
- DBGPRINT(RT_DEBUG_TRACE,
- ("AsicRadioOff ===> Lv= %d, TxCpuIdx = %d, TxDmaIdx = %d. RxCpuIdx = %d, RxDmaIdx = %d.\n",
- Level, pAd->TxRing[0].TxCpuIdx, pAd->TxRing[0].TxDmaIdx,
- pAd->RxRing.RxCpuIdx, pAd->RxRing.RxDmaIdx));
-
- if (pAd->OpMode == OPMODE_AP && Level == DOT11POWERSAVE)
- return FALSE;
-
- /* Check Rx DMA busy status, if more than half is occupied, give up this radio off. */
- RTMP_IO_READ32(pAd, RX_DRX_IDX, &RxDmaIdx);
- RTMP_IO_READ32(pAd, RX_CRX_IDX, &RxCpuIdx);
- if ((RxDmaIdx > RxCpuIdx) && ((RxDmaIdx - RxCpuIdx) > RX_RING_SIZE / 3)) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("AsicRadioOff ===> return1. RxDmaIdx = %d , RxCpuIdx = %d. \n",
- RxDmaIdx, RxCpuIdx));
- return FALSE;
- } else if ((RxCpuIdx >= RxDmaIdx)
- && ((RxCpuIdx - RxDmaIdx) < RX_RING_SIZE / 3)) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("AsicRadioOff ===> return2. RxCpuIdx = %d. RxDmaIdx = %d , \n",
- RxCpuIdx, RxDmaIdx));
- return FALSE;
- }
- /* Once go into this function, disable tx because don't want too many packets in queue to prevent HW stops. */
- /*pAd->bPCIclkOffDisableTx = TRUE; */
- RTMP_SET_PSFLAG(pAd, fRTMP_PS_DISABLE_TX);
- if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_PCIE_DEVICE)
- && pAd->OpMode == OPMODE_STA
- && pAd->StaCfg.PSControl.field.EnableNewPS == TRUE) {
- RTMPCancelTimer(&pAd->Mlme.RadioOnOffTimer, &Cancelled);
- RTMPCancelTimer(&pAd->Mlme.PsPollTimer, &Cancelled);
-
- if (Level == DOT11POWERSAVE) {
- RTMP_IO_READ32(pAd, TBTT_TIMER, &TbTTTime);
- TbTTTime &= 0x1ffff;
- /* 00. check if need to do sleep in this DTIM period. If next beacon will arrive within 30ms , ...doesn't necessarily sleep. */
- /* TbTTTime uint = 64us, LEAD_TIME unit = 1024us, PsPollTime unit = 1ms */
- if (((64 * TbTTTime) < ((LEAD_TIME * 1024) + 40000))
- && (TbttNumToNextWakeUp == 0)) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("TbTTTime = 0x%x , give up this sleep. \n",
- TbTTTime));
- OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_DOZE);
- /*pAd->bPCIclkOffDisableTx = FALSE; */
- RTMP_CLEAR_PSFLAG(pAd, fRTMP_PS_DISABLE_TX);
- return FALSE;
- } else {
- PsPollTime =
- (64 * TbTTTime - LEAD_TIME * 1024) / 1000;
-#ifdef PCIE_PS_SUPPORT
- if ((IS_RT3090(pAd) || IS_RT3572(pAd)
- || IS_RT3390(pAd))
- && IS_VERSION_AFTER_F(pAd)
- && (pAd->StaCfg.PSControl.field.
- rt30xxPowerMode == 3)
- && (pAd->StaCfg.PSControl.field.
- EnableNewPS == TRUE)) {
- PsPollTime -= 5;
- } else
-#endif /* PCIE_PS_SUPPORT // */
- PsPollTime -= 3;
-
- BeaconPeriodTime =
- pAd->CommonCfg.BeaconPeriod * 102 / 100;
- if (TbttNumToNextWakeUp > 0)
- PsPollTime +=
- ((TbttNumToNextWakeUp -
- 1) * BeaconPeriodTime);
-
- pAd->Mlme.bPsPollTimerRunning = TRUE;
- RTMPSetTimer(&pAd->Mlme.PsPollTimer,
- PsPollTime);
- }
- }
- } else {
- DBGPRINT(RT_DEBUG_TRACE,
- ("RT28xxPciAsicRadioOff::Level!=DOT11POWERSAVE \n"));
- }
-
- pAd->bPCIclkOffDisableTx = FALSE;
-
- RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_IDLE_RADIO_OFF);
-
- /* Set to 1R. */
- if (pAd->Antenna.field.RxPath > 1 && pAd->OpMode == OPMODE_STA) {
- tempBBP_R3 = (pAd->StaCfg.BBPR3 & 0xE7);
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, tempBBP_R3);
- }
- /* In Radio Off, we turn off RF clk, So now need to call ASICSwitchChannel again. */
- if ((INFRA_ON(pAd) || pAd->OpMode == OPMODE_AP)
- && (pAd->CommonCfg.CentralChannel != pAd->CommonCfg.Channel)
- && (pAd->MlmeAux.HtCapability.HtCapInfo.ChannelWidth == BW_40)) {
- /* Must using 40MHz. */
- AsicTurnOffRFClk(pAd, pAd->CommonCfg.CentralChannel);
- } else {
- /* Must using 20MHz. */
- AsicTurnOffRFClk(pAd, pAd->CommonCfg.Channel);
- }
-
- if (Level != RTMP_HALT) {
- /* Change Interrupt bitmask. */
- /* When PCI clock is off, don't want to service interrupt. */
- RTMP_IO_WRITE32(pAd, INT_MASK_CSR, AutoWakeupInt);
- } else {
- RTMP_ASIC_INTERRUPT_DISABLE(pAd);
- }
-
- RTMP_IO_WRITE32(pAd, RX_CRX_IDX, pAd->RxRing.RxCpuIdx);
- /* 2. Send Sleep command */
- RTMP_IO_WRITE32(pAd, H2M_MAILBOX_STATUS, 0xffffffff);
- RTMP_IO_WRITE32(pAd, H2M_MAILBOX_CID, 0xffffffff);
- /* send POWER-SAVE command to MCU. high-byte = 1 save power as much as possible. high byte = 0 save less power */
- AsicSendCommandToMcu(pAd, 0x30, PowerSafeCID, 0xff, 0x1);
- /* 2-1. Wait command success */
- /* Status = 1 : success, Status = 2, already sleep, Status = 3, Maybe MAC is busy so can't finish this task. */
- brc = AsicCheckCommanOk(pAd, PowerSafeCID);
-
- /* 3. After 0x30 command is ok, send radio off command. lowbyte = 0 for power safe. */
- /* If 0x30 command is not ok this time, we can ignore 0x35 command. It will make sure not cause firmware'r problem. */
- if ((Level == DOT11POWERSAVE) && (brc == TRUE)) {
- AsicSendCommandToMcu(pAd, 0x35, PowerRadioOffCID, 0, 0x00); /* lowbyte = 0 means to do power safe, NOT turn off radio. */
- /* 3-1. Wait command success */
- AsicCheckCommanOk(pAd, PowerRadioOffCID);
- } else if (brc == TRUE) {
- AsicSendCommandToMcu(pAd, 0x35, PowerRadioOffCID, 1, 0x00); /* lowbyte = 0 means to do power safe, NOT turn off radio. */
- /* 3-1. Wait command success */
- AsicCheckCommanOk(pAd, PowerRadioOffCID);
- }
- /* 1. Wait DMA not busy */
- i = 0;
- do {
- RTMP_IO_READ32(pAd, WPDMA_GLO_CFG, &DmaCfg.word);
- if ((DmaCfg.field.RxDMABusy == 0)
- && (DmaCfg.field.TxDMABusy == 0))
- break;
- RTMPusecDelay(20);
- i++;
- } while (i < 50);
-
- /*
- if (i >= 50)
- {
- pAd->CheckDmaBusyCount++;
- DBGPRINT(RT_DEBUG_TRACE, ("DMA Rx keeps busy. return on AsicRadioOff () CheckDmaBusyCount = %d \n", pAd->CheckDmaBusyCount));
- }
- else
- {
- pAd->CheckDmaBusyCount = 0;
- }
- */
-/*KH Debug:My original codes have the following codes, but currecnt codes do not have it. */
-/* Disable for stability. If PCIE Link Control is modified for advance power save, re-covery this code segment. */
- RTMP_IO_WRITE32(pAd, PBF_SYS_CTRL, 0x1280);
-/*OPSTATUS_SET_FLAG(pAd, fOP_STATUS_CLKSELECT_40MHZ); */
-
-#ifdef PCIE_PS_SUPPORT
- if ((IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd))
- && IS_VERSION_AFTER_F(pAd)
- && (pAd->StaCfg.PSControl.field.rt30xxPowerMode == 3)
- && (pAd->StaCfg.PSControl.field.EnableNewPS == TRUE)) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("RT28xxPciAsicRadioOff::3090 return to skip the following TbttNumToNextWakeUp setting for 279x\n"));
- pAd->bPCIclkOff = TRUE;
- RTMP_CLEAR_PSFLAG(pAd, fRTMP_PS_DISABLE_TX);
- /* For this case, doesn't need to below actions, so return here. */
- return brc;
- }
-#endif /* PCIE_PS_SUPPORT // */
-
- if (Level == DOT11POWERSAVE) {
- AUTO_WAKEUP_STRUC AutoWakeupCfg;
- /*RTMPSetTimer(&pAd->Mlme.PsPollTimer, 90); */
-
- /* we have decided to SLEEP, so at least do it for a BEACON period. */
- if (TbttNumToNextWakeUp == 0)
- TbttNumToNextWakeUp = 1;
-
- AutoWakeupCfg.word = 0;
- RTMP_IO_WRITE32(pAd, AUTO_WAKEUP_CFG, AutoWakeupCfg.word);
-
- /* 1. Set auto wake up timer. */
- AutoWakeupCfg.field.NumofSleepingTbtt = TbttNumToNextWakeUp - 1;
- AutoWakeupCfg.field.EnableAutoWakeup = 1;
- AutoWakeupCfg.field.AutoLeadTime = LEAD_TIME;
- RTMP_IO_WRITE32(pAd, AUTO_WAKEUP_CFG, AutoWakeupCfg.word);
- }
- /* 4-1. If it's to disable our device. Need to restore PCI Configuration Space to its original value. */
- if (Level == RTMP_HALT && pAd->OpMode == OPMODE_STA) {
- if ((brc == TRUE) && (i < 50))
- RTMPPCIeLinkCtrlSetting(pAd, 1);
- }
- /* 4. Set PCI configuration Space Link Comtrol fields. Only Radio Off needs to call this function */
- else if (pAd->OpMode == OPMODE_STA) {
- if ((brc == TRUE) && (i < 50))
- RTMPPCIeLinkCtrlSetting(pAd, 3);
- }
- /*pAd->bPCIclkOffDisableTx = FALSE; */
- RTMP_CLEAR_PSFLAG(pAd, fRTMP_PS_DISABLE_TX);
- return TRUE;
-}
-
-void RT28xxPciMlmeRadioOn(struct rt_rtmp_adapter *pAd)
-{
- if (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_RADIO_OFF))
- return;
-
- DBGPRINT(RT_DEBUG_TRACE, ("%s===>\n", __func__));
-
- if ((pAd->OpMode == OPMODE_AP) || ((pAd->OpMode == OPMODE_STA)
- &&
- (!OPSTATUS_TEST_FLAG
- (pAd, fOP_STATUS_PCIE_DEVICE)
- || pAd->StaCfg.PSControl.field.
- EnableNewPS == FALSE))) {
- RT28xxPciAsicRadioOn(pAd, GUI_IDLE_POWER_SAVE);
- /*NICResetFromError(pAd); */
-
- RTMPRingCleanUp(pAd, QID_AC_BK);
- RTMPRingCleanUp(pAd, QID_AC_BE);
- RTMPRingCleanUp(pAd, QID_AC_VI);
- RTMPRingCleanUp(pAd, QID_AC_VO);
- RTMPRingCleanUp(pAd, QID_MGMT);
- RTMPRingCleanUp(pAd, QID_RX);
-
- /* Enable Tx/Rx */
- RTMPEnableRxTx(pAd);
-
- /* Clear Radio off flag */
- RTMP_CLEAR_FLAG(pAd, fRTMP_ADAPTER_RADIO_OFF);
-
- RTMP_CLEAR_FLAG(pAd, fRTMP_ADAPTER_IDLE_RADIO_OFF);
-
- /* Set LED */
- RTMPSetLED(pAd, LED_RADIO_ON);
- }
-
- if ((pAd->OpMode == OPMODE_STA) &&
- (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_PCIE_DEVICE))
- && (pAd->StaCfg.PSControl.field.EnableNewPS == TRUE)) {
- BOOLEAN Cancelled;
-
- RTMPPCIeLinkCtrlValueRestore(pAd, RESTORE_WAKEUP);
-
- pAd->Mlme.bPsPollTimerRunning = FALSE;
- RTMPCancelTimer(&pAd->Mlme.PsPollTimer, &Cancelled);
- RTMPCancelTimer(&pAd->Mlme.RadioOnOffTimer, &Cancelled);
- RTMPSetTimer(&pAd->Mlme.RadioOnOffTimer, 40);
- }
-}
-
-void RT28xxPciMlmeRadioOFF(struct rt_rtmp_adapter *pAd)
-{
- BOOLEAN brc = TRUE;
-
- if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_RADIO_OFF))
- return;
-
- /* Link down first if any association exists */
- if (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST)) {
- if (INFRA_ON(pAd) || ADHOC_ON(pAd)) {
- struct rt_mlme_disassoc_req DisReq;
- struct rt_mlme_queue_elem *pMsgElem =
- kmalloc(sizeof(struct rt_mlme_queue_elem),
- MEM_ALLOC_FLAG);
-
- if (pMsgElem) {
- COPY_MAC_ADDR(&DisReq.Addr,
- pAd->CommonCfg.Bssid);
- DisReq.Reason = REASON_DISASSOC_STA_LEAVING;
-
- pMsgElem->Machine = ASSOC_STATE_MACHINE;
- pMsgElem->MsgType = MT2_MLME_DISASSOC_REQ;
- pMsgElem->MsgLen =
- sizeof(struct rt_mlme_disassoc_req);
- NdisMoveMemory(pMsgElem->Msg, &DisReq,
- sizeof
- (struct rt_mlme_disassoc_req));
-
- MlmeDisassocReqAction(pAd, pMsgElem);
- kfree(pMsgElem);
-
- RTMPusecDelay(1000);
- }
- }
- }
-
- DBGPRINT(RT_DEBUG_TRACE, ("%s===>\n", __func__));
-
- /* Set Radio off flag */
- RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_RADIO_OFF);
-
- {
- BOOLEAN Cancelled;
- if (pAd->StaCfg.PSControl.field.EnableNewPS == TRUE) {
- if (RTMP_TEST_FLAG
- (pAd, fRTMP_ADAPTER_BSS_SCAN_IN_PROGRESS)) {
- RTMPCancelTimer(&pAd->MlmeAux.ScanTimer,
- &Cancelled);
- RTMP_CLEAR_FLAG(pAd,
- fRTMP_ADAPTER_BSS_SCAN_IN_PROGRESS);
- }
- /* If during power safe mode. */
- if (pAd->StaCfg.bRadio == TRUE) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("-->MlmeRadioOff() return on bRadio == TRUE; \n"));
- return;
- }
- /* Always radio on since the NIC needs to set the MCU command (LED_RADIO_OFF). */
- if (IDLE_ON(pAd) &&
- (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_IDLE_RADIO_OFF)))
- {
- RT28xxPciAsicRadioOn(pAd, GUI_IDLE_POWER_SAVE);
- }
- if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_PCIE_DEVICE)) {
- BOOLEAN Cancelled;
- pAd->Mlme.bPsPollTimerRunning = FALSE;
- RTMPCancelTimer(&pAd->Mlme.PsPollTimer,
- &Cancelled);
- RTMPCancelTimer(&pAd->Mlme.RadioOnOffTimer,
- &Cancelled);
- }
- }
- /* Link down first if any association exists */
- if (INFRA_ON(pAd) || ADHOC_ON(pAd))
- LinkDown(pAd, FALSE);
- RTMPusecDelay(10000);
- /*========================================== */
- /* Clean up old bss table */
- BssTableInit(&pAd->ScanTab);
-
- /*
- if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_PCIE_DEVICE))
- {
- RTMPSetTimer(&pAd->Mlme.RadioOnOffTimer, 10);
- return;
- }
- */
- }
-
- /* Set LED.Move to here for fixing LED bug. This flag must be called after LinkDown */
- RTMPSetLED(pAd, LED_RADIO_OFF);
-
-/*KH Debug:All PCIe devices need to use timer to execute radio off function, or the PCIe&&EnableNewPS needs. */
-/*KH Ans:It is right, because only when the PCIe and EnableNewPs is true, we need to delay the RadioOffTimer */
-/*to avoid the deadlock with PCIe Power saving function. */
- if (pAd->OpMode == OPMODE_STA &&
- OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_PCIE_DEVICE) &&
- pAd->StaCfg.PSControl.field.EnableNewPS == TRUE) {
- RTMPSetTimer(&pAd->Mlme.RadioOnOffTimer, 10);
- } else {
- brc = RT28xxPciAsicRadioOff(pAd, GUIRADIO_OFF, 0);
-
- if (brc == FALSE) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("%s call RT28xxPciAsicRadioOff fail!\n",
- __func__));
- }
- }
-/*
-*/
-}
-
-#endif /* RTMP_MAC_PCI // */
diff --git a/drivers/staging/rt2860/common/cmm_mac_usb.c b/drivers/staging/rt2860/common/cmm_mac_usb.c
deleted file mode 100644
index 64a65a4..0000000
--- a/drivers/staging/rt2860/common/cmm_mac_usb.c
+++ /dev/null
@@ -1,1162 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-*/
-
-#ifdef RTMP_MAC_USB
-
-#include "../rt_config.h"
-
-/*
-========================================================================
-Routine Description:
- Initialize receive data structures.
-
-Arguments:
- pAd Pointer to our adapter
-
-Return Value:
- NDIS_STATUS_SUCCESS
- NDIS_STATUS_RESOURCES
-
-Note:
- Initialize all receive releated private buffer, include those define
- in struct rt_rtmp_adapter structure and all private data structures. The mahor
- work is to allocate buffer for each packet and chain buffer to
- NDIS packet descriptor.
-========================================================================
-*/
-int NICInitRecv(struct rt_rtmp_adapter *pAd)
-{
- u8 i;
- int Status = NDIS_STATUS_SUCCESS;
- struct os_cookie *pObj = (struct os_cookie *)pAd->OS_Cookie;
-
- DBGPRINT(RT_DEBUG_TRACE, ("--> NICInitRecv\n"));
- pObj = pObj;
-
- /*InterlockedExchange(&pAd->PendingRx, 0); */
- pAd->PendingRx = 0;
- pAd->NextRxBulkInReadIndex = 0; /* Next Rx Read index */
- pAd->NextRxBulkInIndex = 0; /*RX_RING_SIZE -1; // Rx Bulk pointer */
- pAd->NextRxBulkInPosition = 0;
-
- for (i = 0; i < (RX_RING_SIZE); i++) {
- struct rt_rx_context *pRxContext = &(pAd->RxContext[i]);
-
- /*Allocate URB */
- pRxContext->pUrb = RTUSB_ALLOC_URB(0);
- if (pRxContext->pUrb == NULL) {
- Status = NDIS_STATUS_RESOURCES;
- goto out1;
- }
- /* Allocate transfer buffer */
- pRxContext->TransferBuffer =
- RTUSB_URB_ALLOC_BUFFER(pObj->pUsb_Dev, MAX_RXBULK_SIZE,
- &pRxContext->data_dma);
- if (pRxContext->TransferBuffer == NULL) {
- Status = NDIS_STATUS_RESOURCES;
- goto out1;
- }
-
- NdisZeroMemory(pRxContext->TransferBuffer, MAX_RXBULK_SIZE);
-
- pRxContext->pAd = pAd;
- pRxContext->pIrp = NULL;
- pRxContext->InUse = FALSE;
- pRxContext->IRPPending = FALSE;
- pRxContext->Readable = FALSE;
- /*pRxContext->ReorderInUse = FALSE; */
- pRxContext->bRxHandling = FALSE;
- pRxContext->BulkInOffset = 0;
- }
-
- DBGPRINT(RT_DEBUG_TRACE, ("<-- NICInitRecv(Status=%d)\n", Status));
- return Status;
-
-out1:
- for (i = 0; i < (RX_RING_SIZE); i++) {
- struct rt_rx_context *pRxContext = &(pAd->RxContext[i]);
-
- if (NULL != pRxContext->TransferBuffer) {
- RTUSB_URB_FREE_BUFFER(pObj->pUsb_Dev, MAX_RXBULK_SIZE,
- pRxContext->TransferBuffer,
- pRxContext->data_dma);
- pRxContext->TransferBuffer = NULL;
- }
-
- if (NULL != pRxContext->pUrb) {
- RTUSB_UNLINK_URB(pRxContext->pUrb);
- RTUSB_FREE_URB(pRxContext->pUrb);
- pRxContext->pUrb = NULL;
- }
- }
-
- return Status;
-}
-
-/*
-========================================================================
-Routine Description:
- Initialize transmit data structures.
-
-Arguments:
- pAd Pointer to our adapter
-
-Return Value:
- NDIS_STATUS_SUCCESS
- NDIS_STATUS_RESOURCES
-
-Note:
-========================================================================
-*/
-int NICInitTransmit(struct rt_rtmp_adapter *pAd)
-{
-#define LM_USB_ALLOC(pObj, Context, TB_Type, BufferSize, Status, msg1, err1, msg2, err2) \
- Context->pUrb = RTUSB_ALLOC_URB(0); \
- if (Context->pUrb == NULL) { \
- DBGPRINT(RT_DEBUG_ERROR, msg1); \
- Status = NDIS_STATUS_RESOURCES; \
- goto err1; } \
- \
- Context->TransferBuffer = \
- (TB_Type)RTUSB_URB_ALLOC_BUFFER(pObj->pUsb_Dev, BufferSize, &Context->data_dma); \
- if (Context->TransferBuffer == NULL) { \
- DBGPRINT(RT_DEBUG_ERROR, msg2); \
- Status = NDIS_STATUS_RESOURCES; \
- goto err2; }
-
-#define LM_URB_FREE(pObj, Context, BufferSize) \
- if (NULL != Context->pUrb) { \
- RTUSB_UNLINK_URB(Context->pUrb); \
- RTUSB_FREE_URB(Context->pUrb); \
- Context->pUrb = NULL; } \
- if (NULL != Context->TransferBuffer) { \
- RTUSB_URB_FREE_BUFFER(pObj->pUsb_Dev, BufferSize, \
- Context->TransferBuffer, \
- Context->data_dma); \
- Context->TransferBuffer = NULL; }
-
- u8 i, acidx;
- int Status = NDIS_STATUS_SUCCESS;
- struct rt_tx_context *pNullContext = &(pAd->NullContext);
- struct rt_tx_context *pPsPollContext = &(pAd->PsPollContext);
- struct rt_tx_context *pRTSContext = &(pAd->RTSContext);
- struct rt_tx_context *pMLMEContext = NULL;
-/* struct rt_ht_tx_context *pHTTXContext = NULL; */
- struct os_cookie *pObj = (struct os_cookie *)pAd->OS_Cookie;
- void *RingBaseVa;
-/* struct rt_rtmp_tx_ring *pTxRing; */
- struct rt_rtmp_mgmt_ring *pMgmtRing;
-
- DBGPRINT(RT_DEBUG_TRACE, ("--> NICInitTransmit\n"));
- pObj = pObj;
-
- /* Init 4 set of Tx parameters */
- for (acidx = 0; acidx < NUM_OF_TX_RING; acidx++) {
- /* Initialize all Transmit releated queues */
- InitializeQueueHeader(&pAd->TxSwQueue[acidx]);
-
- /* Next Local tx ring pointer waiting for buck out */
- pAd->NextBulkOutIndex[acidx] = acidx;
- pAd->BulkOutPending[acidx] = FALSE; /* Buck Out control flag */
- /*pAd->DataBulkDoneIdx[acidx] = 0; */
- }
-
- /*pAd->NextMLMEIndex = 0; */
- /*pAd->PushMgmtIndex = 0; */
- /*pAd->PopMgmtIndex = 0; */
- /*InterlockedExchange(&pAd->MgmtQueueSize, 0); */
- /*InterlockedExchange(&pAd->TxCount, 0); */
-
- /*pAd->PrioRingFirstIndex = 0; */
- /*pAd->PrioRingTxCnt = 0; */
-
- do {
- /* */
- /* TX_RING_SIZE, 4 ACs */
- /* */
- for (acidx = 0; acidx < 4; acidx++) {
- struct rt_ht_tx_context *pHTTXContext = &(pAd->TxContext[acidx]);
-
- NdisZeroMemory(pHTTXContext, sizeof(struct rt_ht_tx_context));
- /*Allocate URB */
- LM_USB_ALLOC(pObj, pHTTXContext, struct rt_httx_buffer *,
- sizeof(struct rt_httx_buffer), Status,
- ("<-- ERROR in Alloc TX TxContext[%d] urb!\n",
- acidx), done,
- ("<-- ERROR in Alloc TX TxContext[%d] struct rt_httx_buffer!\n",
- acidx), out1);
-
- NdisZeroMemory(pHTTXContext->TransferBuffer->
- Aggregation, 4);
- pHTTXContext->pAd = pAd;
- pHTTXContext->pIrp = NULL;
- pHTTXContext->IRPPending = FALSE;
- pHTTXContext->NextBulkOutPosition = 0;
- pHTTXContext->ENextBulkOutPosition = 0;
- pHTTXContext->CurWritePosition = 0;
- pHTTXContext->CurWriteRealPos = 0;
- pHTTXContext->BulkOutSize = 0;
- pHTTXContext->BulkOutPipeId = acidx;
- pHTTXContext->bRingEmpty = TRUE;
- pHTTXContext->bCopySavePad = FALSE;
- pAd->BulkOutPending[acidx] = FALSE;
- }
-
- /* */
- /* MGMT_RING_SIZE */
- /* */
-
- /* Allocate MGMT ring descriptor's memory */
- pAd->MgmtDescRing.AllocSize =
- MGMT_RING_SIZE * sizeof(struct rt_tx_context);
- os_alloc_mem(pAd, (u8 **) (&pAd->MgmtDescRing.AllocVa),
- pAd->MgmtDescRing.AllocSize);
- if (pAd->MgmtDescRing.AllocVa == NULL) {
- DBGPRINT_ERR("Failed to allocate a big buffer for MgmtDescRing!\n");
- Status = NDIS_STATUS_RESOURCES;
- goto out1;
- }
- NdisZeroMemory(pAd->MgmtDescRing.AllocVa,
- pAd->MgmtDescRing.AllocSize);
- RingBaseVa = pAd->MgmtDescRing.AllocVa;
-
- /* Initialize MGMT Ring and associated buffer memory */
- pMgmtRing = &pAd->MgmtRing;
- for (i = 0; i < MGMT_RING_SIZE; i++) {
- /* link the pre-allocated Mgmt buffer to MgmtRing.Cell */
- pMgmtRing->Cell[i].AllocSize = sizeof(struct rt_tx_context);
- pMgmtRing->Cell[i].AllocVa = RingBaseVa;
- pMgmtRing->Cell[i].pNdisPacket = NULL;
- pMgmtRing->Cell[i].pNextNdisPacket = NULL;
-
- /*Allocate URB for MLMEContext */
- pMLMEContext =
- (struct rt_tx_context *)pAd->MgmtRing.Cell[i].AllocVa;
- pMLMEContext->pUrb = RTUSB_ALLOC_URB(0);
- if (pMLMEContext->pUrb == NULL) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("<-- ERROR in Alloc TX MLMEContext[%d] urb!\n",
- i));
- Status = NDIS_STATUS_RESOURCES;
- goto out2;
- }
- pMLMEContext->pAd = pAd;
- pMLMEContext->pIrp = NULL;
- pMLMEContext->TransferBuffer = NULL;
- pMLMEContext->InUse = FALSE;
- pMLMEContext->IRPPending = FALSE;
- pMLMEContext->bWaitingBulkOut = FALSE;
- pMLMEContext->BulkOutSize = 0;
- pMLMEContext->SelfIdx = i;
-
- /* Offset to next ring descriptor address */
- RingBaseVa = (u8 *)RingBaseVa + sizeof(struct rt_tx_context);
- }
- DBGPRINT(RT_DEBUG_TRACE,
- ("MGMT Ring: total %d entry allocated\n", i));
-
- /*pAd->MgmtRing.TxSwFreeIdx = (MGMT_RING_SIZE - 1); */
- pAd->MgmtRing.TxSwFreeIdx = MGMT_RING_SIZE;
- pAd->MgmtRing.TxCpuIdx = 0;
- pAd->MgmtRing.TxDmaIdx = 0;
-
- /* */
- /* BEACON_RING_SIZE */
- /* */
- for (i = 0; i < BEACON_RING_SIZE; i++) /* 2 */
- {
- struct rt_tx_context *pBeaconContext = &(pAd->BeaconContext[i]);
-
- NdisZeroMemory(pBeaconContext, sizeof(struct rt_tx_context));
-
- /*Allocate URB */
- LM_USB_ALLOC(pObj, pBeaconContext, struct rt_tx_buffer *,
- sizeof(struct rt_tx_buffer), Status,
- ("<-- ERROR in Alloc TX BeaconContext[%d] urb!\n",
- i), out2,
- ("<-- ERROR in Alloc TX BeaconContext[%d] struct rt_tx_buffer!\n",
- i), out3);
-
- pBeaconContext->pAd = pAd;
- pBeaconContext->pIrp = NULL;
- pBeaconContext->InUse = FALSE;
- pBeaconContext->IRPPending = FALSE;
- }
-
- /* */
- /* NullContext */
- /* */
- NdisZeroMemory(pNullContext, sizeof(struct rt_tx_context));
-
- /*Allocate URB */
- LM_USB_ALLOC(pObj, pNullContext, struct rt_tx_buffer *, sizeof(struct rt_tx_buffer),
- Status,
- ("<-- ERROR in Alloc TX NullContext urb!\n"),
- out3,
- ("<-- ERROR in Alloc TX NullContext struct rt_tx_buffer!\n"),
- out4);
-
- pNullContext->pAd = pAd;
- pNullContext->pIrp = NULL;
- pNullContext->InUse = FALSE;
- pNullContext->IRPPending = FALSE;
-
- /* */
- /* RTSContext */
- /* */
- NdisZeroMemory(pRTSContext, sizeof(struct rt_tx_context));
-
- /*Allocate URB */
- LM_USB_ALLOC(pObj, pRTSContext, struct rt_tx_buffer *, sizeof(struct rt_tx_buffer),
- Status,
- ("<-- ERROR in Alloc TX RTSContext urb!\n"),
- out4,
- ("<-- ERROR in Alloc TX RTSContext struct rt_tx_buffer!\n"),
- out5);
-
- pRTSContext->pAd = pAd;
- pRTSContext->pIrp = NULL;
- pRTSContext->InUse = FALSE;
- pRTSContext->IRPPending = FALSE;
-
- /* */
- /* PsPollContext */
- /* */
- /*NdisZeroMemory(pPsPollContext, sizeof(struct rt_tx_context)); */
- /*Allocate URB */
- LM_USB_ALLOC(pObj, pPsPollContext, struct rt_tx_buffer *,
- sizeof(struct rt_tx_buffer), Status,
- ("<-- ERROR in Alloc TX PsPollContext urb!\n"),
- out5,
- ("<-- ERROR in Alloc TX PsPollContext struct rt_tx_buffer!\n"),
- out6);
-
- pPsPollContext->pAd = pAd;
- pPsPollContext->pIrp = NULL;
- pPsPollContext->InUse = FALSE;
- pPsPollContext->IRPPending = FALSE;
- pPsPollContext->bAggregatible = FALSE;
- pPsPollContext->LastOne = TRUE;
-
- } while (FALSE);
-
-done:
- DBGPRINT(RT_DEBUG_TRACE, ("<-- NICInitTransmit(Status=%d)\n", Status));
-
- return Status;
-
- /* --------------------------- ERROR HANDLE --------------------------- */
-out6:
- LM_URB_FREE(pObj, pPsPollContext, sizeof(struct rt_tx_buffer));
-
-out5:
- LM_URB_FREE(pObj, pRTSContext, sizeof(struct rt_tx_buffer));
-
-out4:
- LM_URB_FREE(pObj, pNullContext, sizeof(struct rt_tx_buffer));
-
-out3:
- for (i = 0; i < BEACON_RING_SIZE; i++) {
- struct rt_tx_context *pBeaconContext = &(pAd->BeaconContext[i]);
- if (pBeaconContext)
- LM_URB_FREE(pObj, pBeaconContext, sizeof(struct rt_tx_buffer));
- }
-
-out2:
- if (pAd->MgmtDescRing.AllocVa) {
- pMgmtRing = &pAd->MgmtRing;
- for (i = 0; i < MGMT_RING_SIZE; i++) {
- pMLMEContext =
- (struct rt_tx_context *)pAd->MgmtRing.Cell[i].AllocVa;
- if (pMLMEContext)
- LM_URB_FREE(pObj, pMLMEContext,
- sizeof(struct rt_tx_buffer));
- }
- os_free_mem(pAd, pAd->MgmtDescRing.AllocVa);
- pAd->MgmtDescRing.AllocVa = NULL;
- }
-
-out1:
- for (acidx = 0; acidx < 4; acidx++) {
- struct rt_ht_tx_context *pTxContext = &(pAd->TxContext[acidx]);
- if (pTxContext)
- LM_URB_FREE(pObj, pTxContext, sizeof(struct rt_httx_buffer));
- }
-
- /* Here we didn't have any pre-allocated memory need to free. */
-
- return Status;
-}
-
-/*
-========================================================================
-Routine Description:
- Allocate DMA memory blocks for send, receive.
-
-Arguments:
- pAd Pointer to our adapter
-
-Return Value:
- NDIS_STATUS_SUCCESS
- NDIS_STATUS_FAILURE
- NDIS_STATUS_RESOURCES
-
-Note:
-========================================================================
-*/
-int RTMPAllocTxRxRingMemory(struct rt_rtmp_adapter *pAd)
-{
-/* struct rt_counter_802_11 pCounter = &pAd->WlanCounters; */
- int Status;
- int num;
-
- DBGPRINT(RT_DEBUG_TRACE, ("--> RTMPAllocTxRxRingMemory\n"));
-
- do {
- /* Init the struct rt_cmdq and CmdQLock */
- NdisAllocateSpinLock(&pAd->CmdQLock);
- NdisAcquireSpinLock(&pAd->CmdQLock);
- RTUSBInitializeCmdQ(&pAd->CmdQ);
- NdisReleaseSpinLock(&pAd->CmdQLock);
-
- NdisAllocateSpinLock(&pAd->MLMEBulkOutLock);
- /*NdisAllocateSpinLock(&pAd->MLMEWaitQueueLock); */
- NdisAllocateSpinLock(&pAd->BulkOutLock[0]);
- NdisAllocateSpinLock(&pAd->BulkOutLock[1]);
- NdisAllocateSpinLock(&pAd->BulkOutLock[2]);
- NdisAllocateSpinLock(&pAd->BulkOutLock[3]);
- NdisAllocateSpinLock(&pAd->BulkOutLock[4]);
- NdisAllocateSpinLock(&pAd->BulkOutLock[5]);
- NdisAllocateSpinLock(&pAd->BulkInLock);
-
- for (num = 0; num < NUM_OF_TX_RING; num++) {
- NdisAllocateSpinLock(&pAd->TxContextQueueLock[num]);
- }
-
-/* NdisAllocateSpinLock(&pAd->MemLock); // Not used in RT28XX */
-
-/* NdisAllocateSpinLock(&pAd->MacTabLock); // init it in UserCfgInit() */
-/* NdisAllocateSpinLock(&pAd->BATabLock); // init it in BATableInit() */
-
-/* for(num=0; num<MAX_LEN_OF_BA_REC_TABLE; num++) */
-/* { */
-/* NdisAllocateSpinLock(&pAd->BATable.BARecEntry[num].RxReRingLock); */
-/* } */
-
- /* */
- /* Init Mac Table */
- /* */
-/* MacTableInitialize(pAd); */
-
- /* */
- /* Init send data structures and related parameters */
- /* */
- Status = NICInitTransmit(pAd);
- if (Status != NDIS_STATUS_SUCCESS)
- break;
-
- /* */
- /* Init receive data structures and related parameters */
- /* */
- Status = NICInitRecv(pAd);
- if (Status != NDIS_STATUS_SUCCESS)
- break;
-
- pAd->PendingIoCount = 1;
-
- } while (FALSE);
-
- NdisZeroMemory(&pAd->FragFrame, sizeof(struct rt_fragment_frame));
- pAd->FragFrame.pFragPacket =
- RTMP_AllocateFragPacketBuffer(pAd, RX_BUFFER_NORMSIZE);
-
- if (pAd->FragFrame.pFragPacket == NULL) {
- Status = NDIS_STATUS_RESOURCES;
- }
-
- DBGPRINT_S(Status,
- ("<-- RTMPAllocTxRxRingMemory, Status=%x\n", Status));
- return Status;
-}
-
-/*
-========================================================================
-Routine Description:
- Calls USB_InterfaceStop and frees memory allocated for the URBs
- calls NdisMDeregisterDevice and frees the memory
- allocated in VNetInitialize for the Adapter Object
-
-Arguments:
- *pAd the raxx interface data pointer
-
-Return Value:
- None
-
-Note:
-========================================================================
-*/
-void RTMPFreeTxRxRingMemory(struct rt_rtmp_adapter *pAd)
-{
-#define LM_URB_FREE(pObj, Context, BufferSize) \
- if (NULL != Context->pUrb) { \
- RTUSB_UNLINK_URB(Context->pUrb); \
- RTUSB_FREE_URB(Context->pUrb); \
- Context->pUrb = NULL; } \
- if (NULL != Context->TransferBuffer) { \
- RTUSB_URB_FREE_BUFFER(pObj->pUsb_Dev, BufferSize, \
- Context->TransferBuffer, \
- Context->data_dma); \
- Context->TransferBuffer = NULL; }
-
- u32 i, acidx;
- struct rt_tx_context *pNullContext = &pAd->NullContext;
- struct rt_tx_context *pPsPollContext = &pAd->PsPollContext;
- struct rt_tx_context *pRTSContext = &pAd->RTSContext;
-/* struct rt_ht_tx_context *pHTTXContext; */
- /*PRTMP_REORDERBUF pReorderBuf; */
- struct os_cookie *pObj = (struct os_cookie *)pAd->OS_Cookie;
-/* struct rt_rtmp_tx_ring *pTxRing; */
-
- DBGPRINT(RT_DEBUG_ERROR, ("---> RTMPFreeTxRxRingMemory\n"));
- pObj = pObj;
-
- /* Free all resources for the RECEIVE buffer queue. */
- for (i = 0; i < (RX_RING_SIZE); i++) {
- struct rt_rx_context *pRxContext = &(pAd->RxContext[i]);
- if (pRxContext)
- LM_URB_FREE(pObj, pRxContext, MAX_RXBULK_SIZE);
- }
-
- /* Free PsPoll frame resource */
- LM_URB_FREE(pObj, pPsPollContext, sizeof(struct rt_tx_buffer));
-
- /* Free NULL frame resource */
- LM_URB_FREE(pObj, pNullContext, sizeof(struct rt_tx_buffer));
-
- /* Free RTS frame resource */
- LM_URB_FREE(pObj, pRTSContext, sizeof(struct rt_tx_buffer));
-
- /* Free beacon frame resource */
- for (i = 0; i < BEACON_RING_SIZE; i++) {
- struct rt_tx_context *pBeaconContext = &(pAd->BeaconContext[i]);
- if (pBeaconContext)
- LM_URB_FREE(pObj, pBeaconContext, sizeof(struct rt_tx_buffer));
- }
-
- /* Free mgmt frame resource */
- for (i = 0; i < MGMT_RING_SIZE; i++) {
- struct rt_tx_context *pMLMEContext =
- (struct rt_tx_context *)pAd->MgmtRing.Cell[i].AllocVa;
- /*LM_URB_FREE(pObj, pMLMEContext, sizeof(struct rt_tx_buffer)); */
- if (NULL != pAd->MgmtRing.Cell[i].pNdisPacket) {
- RTMPFreeNdisPacket(pAd,
- pAd->MgmtRing.Cell[i].pNdisPacket);
- pAd->MgmtRing.Cell[i].pNdisPacket = NULL;
- pMLMEContext->TransferBuffer = NULL;
- }
-
- if (pMLMEContext) {
- if (NULL != pMLMEContext->pUrb) {
- RTUSB_UNLINK_URB(pMLMEContext->pUrb);
- RTUSB_FREE_URB(pMLMEContext->pUrb);
- pMLMEContext->pUrb = NULL;
- }
- }
- }
- if (pAd->MgmtDescRing.AllocVa)
- os_free_mem(pAd, pAd->MgmtDescRing.AllocVa);
-
- /* Free Tx frame resource */
- for (acidx = 0; acidx < 4; acidx++) {
- struct rt_ht_tx_context *pHTTXContext = &(pAd->TxContext[acidx]);
- if (pHTTXContext)
- LM_URB_FREE(pObj, pHTTXContext, sizeof(struct rt_httx_buffer));
- }
-
- if (pAd->FragFrame.pFragPacket)
- RELEASE_NDIS_PACKET(pAd, pAd->FragFrame.pFragPacket,
- NDIS_STATUS_SUCCESS);
-
- for (i = 0; i < 6; i++) {
- NdisFreeSpinLock(&pAd->BulkOutLock[i]);
- }
-
- NdisFreeSpinLock(&pAd->BulkInLock);
- NdisFreeSpinLock(&pAd->MLMEBulkOutLock);
-
- NdisFreeSpinLock(&pAd->CmdQLock);
- /* Clear all pending bulk-out request flags. */
- RTUSB_CLEAR_BULK_FLAG(pAd, 0xffffffff);
-
-/* NdisFreeSpinLock(&pAd->MacTabLock); */
-
-/* for(i=0; i<MAX_LEN_OF_BA_REC_TABLE; i++) */
-/* { */
-/* NdisFreeSpinLock(&pAd->BATable.BARecEntry[i].RxReRingLock); */
-/* } */
-
- DBGPRINT(RT_DEBUG_ERROR, ("<--- RTMPFreeTxRxRingMemory\n"));
-}
-
-/*
-========================================================================
-Routine Description:
- Write WLAN MAC address to USB 2870.
-
-Arguments:
- pAd Pointer to our adapter
-
-Return Value:
- NDIS_STATUS_SUCCESS
-
-Note:
-========================================================================
-*/
-int RTUSBWriteHWMACAddress(struct rt_rtmp_adapter *pAd)
-{
- MAC_DW0_STRUC StaMacReg0;
- MAC_DW1_STRUC StaMacReg1;
- int Status = NDIS_STATUS_SUCCESS;
- LARGE_INTEGER NOW;
-
- /* initialize the random number generator */
- RTMP_GetCurrentSystemTime(&NOW);
-
- if (pAd->bLocalAdminMAC != TRUE) {
- pAd->CurrentAddress[0] = pAd->PermanentAddress[0];
- pAd->CurrentAddress[1] = pAd->PermanentAddress[1];
- pAd->CurrentAddress[2] = pAd->PermanentAddress[2];
- pAd->CurrentAddress[3] = pAd->PermanentAddress[3];
- pAd->CurrentAddress[4] = pAd->PermanentAddress[4];
- pAd->CurrentAddress[5] = pAd->PermanentAddress[5];
- }
- /* Write New MAC address to MAC_CSR2 & MAC_CSR3 & let ASIC know our new MAC */
- StaMacReg0.field.Byte0 = pAd->CurrentAddress[0];
- StaMacReg0.field.Byte1 = pAd->CurrentAddress[1];
- StaMacReg0.field.Byte2 = pAd->CurrentAddress[2];
- StaMacReg0.field.Byte3 = pAd->CurrentAddress[3];
- StaMacReg1.field.Byte4 = pAd->CurrentAddress[4];
- StaMacReg1.field.Byte5 = pAd->CurrentAddress[5];
- StaMacReg1.field.U2MeMask = 0xff;
- DBGPRINT_RAW(RT_DEBUG_TRACE,
- ("Local MAC = %pM\n", pAd->CurrentAddress));
-
- RTUSBWriteMACRegister(pAd, MAC_ADDR_DW0, StaMacReg0.word);
- RTUSBWriteMACRegister(pAd, MAC_ADDR_DW1, StaMacReg1.word);
- return Status;
-}
-
-/*
-========================================================================
-Routine Description:
- Disable DMA.
-
-Arguments:
- *pAd the raxx interface data pointer
-
-Return Value:
- None
-
-Note:
-========================================================================
-*/
-void RT28XXDMADisable(struct rt_rtmp_adapter *pAd)
-{
- /* no use */
-}
-
-/*
-========================================================================
-Routine Description:
- Enable DMA.
-
-Arguments:
- *pAd the raxx interface data pointer
-
-Return Value:
- None
-
-Note:
-========================================================================
-*/
-void RT28XXDMAEnable(struct rt_rtmp_adapter *pAd)
-{
- WPDMA_GLO_CFG_STRUC GloCfg;
- USB_DMA_CFG_STRUC UsbCfg;
- int i = 0;
-
- RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, 0x4);
- do {
- RTMP_IO_READ32(pAd, WPDMA_GLO_CFG, &GloCfg.word);
- if ((GloCfg.field.TxDMABusy == 0)
- && (GloCfg.field.RxDMABusy == 0))
- break;
-
- DBGPRINT(RT_DEBUG_TRACE, ("==> DMABusy\n"));
- RTMPusecDelay(1000);
- i++;
- } while (i < 200);
-
- RTMPusecDelay(50);
- GloCfg.field.EnTXWriteBackDDONE = 1;
- GloCfg.field.EnableRxDMA = 1;
- GloCfg.field.EnableTxDMA = 1;
- DBGPRINT(RT_DEBUG_TRACE,
- ("<== WRITE DMA offset 0x208 = 0x%x\n", GloCfg.word));
- RTMP_IO_WRITE32(pAd, WPDMA_GLO_CFG, GloCfg.word);
-
- UsbCfg.word = 0;
- UsbCfg.field.phyclear = 0;
- /* usb version is 1.1,do not use bulk in aggregation */
- if (pAd->BulkInMaxPacketSize == 512)
- UsbCfg.field.RxBulkAggEn = 1;
- /* for last packet, PBF might use more than limited, so minus 2 to prevent from error */
- UsbCfg.field.RxBulkAggLmt = (MAX_RXBULK_SIZE / 1024) - 3;
- UsbCfg.field.RxBulkAggTOut = 0x80; /* 2006-10-18 */
- UsbCfg.field.RxBulkEn = 1;
- UsbCfg.field.TxBulkEn = 1;
-
- RTUSBWriteMACRegister(pAd, USB_DMA_CFG, UsbCfg.word);
-
-}
-
-/********************************************************************
- *
- * 2870 Beacon Update Related functions.
- *
- ********************************************************************/
-
-/*
-========================================================================
-Routine Description:
- Write Beacon buffer to Asic.
-
-Arguments:
- *pAd the raxx interface data pointer
-
-Return Value:
- None
-
-Note:
-========================================================================
-*/
-void RT28xx_UpdateBeaconToAsic(struct rt_rtmp_adapter *pAd,
- int apidx,
- unsigned long FrameLen, unsigned long UpdatePos)
-{
- u8 *pBeaconFrame = NULL;
- u8 *ptr;
- u32 i, padding;
- struct rt_beacon_sync *pBeaconSync = pAd->CommonCfg.pBeaconSync;
- u32 longValue;
-/* u16 shortValue; */
- BOOLEAN bBcnReq = FALSE;
- u8 bcn_idx = 0;
-
- if (pBeaconFrame == NULL) {
- DBGPRINT(RT_DEBUG_ERROR, ("pBeaconFrame is NULL!\n"));
- return;
- }
-
- if (pBeaconSync == NULL) {
- DBGPRINT(RT_DEBUG_ERROR, ("pBeaconSync is NULL!\n"));
- return;
- }
- /*if ((pAd->WdsTab.Mode == WDS_BRIDGE_MODE) || */
- /* ((pAd->ApCfg.MBSSID[apidx].MSSIDDev == NULL) || !(pAd->ApCfg.MBSSID[apidx].MSSIDDev->flags & IFF_UP)) */
- /* ) */
- if (bBcnReq == FALSE) {
- /* when the ra interface is down, do not send its beacon frame */
- /* clear all zero */
- for (i = 0; i < TXWI_SIZE; i += 4) {
- RTMP_IO_WRITE32(pAd, pAd->BeaconOffset[bcn_idx] + i,
- 0x00);
- }
- pBeaconSync->BeaconBitMap &=
- (~(BEACON_BITMAP_MASK & (1 << bcn_idx)));
- NdisZeroMemory(pBeaconSync->BeaconTxWI[bcn_idx], TXWI_SIZE);
- } else {
- ptr = (u8 *)& pAd->BeaconTxWI;
- if (NdisEqualMemory(pBeaconSync->BeaconTxWI[bcn_idx], &pAd->BeaconTxWI, TXWI_SIZE) == FALSE) { /* If BeaconTxWI changed, we need to rewrite the TxWI for the Beacon frames. */
- pBeaconSync->BeaconBitMap &=
- (~(BEACON_BITMAP_MASK & (1 << bcn_idx)));
- NdisMoveMemory(pBeaconSync->BeaconTxWI[bcn_idx],
- &pAd->BeaconTxWI, TXWI_SIZE);
- }
-
- if ((pBeaconSync->BeaconBitMap & (1 << bcn_idx)) !=
- (1 << bcn_idx)) {
- for (i = 0; i < TXWI_SIZE; i += 4) /* 16-byte TXWI field */
- {
- longValue =
- *ptr + (*(ptr + 1) << 8) +
- (*(ptr + 2) << 16) + (*(ptr + 3) << 24);
- RTMP_IO_WRITE32(pAd,
- pAd->BeaconOffset[bcn_idx] + i,
- longValue);
- ptr += 4;
- }
- }
-
- ptr = pBeaconSync->BeaconBuf[bcn_idx];
- padding = (FrameLen & 0x01);
- NdisZeroMemory((u8 *)(pBeaconFrame + FrameLen), padding);
- FrameLen += padding;
- for (i = 0; i < FrameLen /*HW_BEACON_OFFSET */ ; i += 2) {
- if (NdisEqualMemory(ptr, pBeaconFrame, 2) == FALSE) {
- NdisMoveMemory(ptr, pBeaconFrame, 2);
- /*shortValue = *ptr + (*(ptr+1)<<8); */
- /*RTMP_IO_WRITE8(pAd, pAd->BeaconOffset[bcn_idx] + TXWI_SIZE + i, shortValue); */
- RTUSBMultiWrite(pAd,
- pAd->BeaconOffset[bcn_idx] +
- TXWI_SIZE + i, ptr, 2);
- }
- ptr += 2;
- pBeaconFrame += 2;
- }
-
- pBeaconSync->BeaconBitMap |= (1 << bcn_idx);
-
- /* For AP interface, set the DtimBitOn so that we can send Bcast/Mcast frame out after this beacon frame. */
- }
-
-}
-
-void RTUSBBssBeaconStop(struct rt_rtmp_adapter *pAd)
-{
- struct rt_beacon_sync *pBeaconSync;
- int i, offset;
- BOOLEAN Cancelled = TRUE;
-
- pBeaconSync = pAd->CommonCfg.pBeaconSync;
- if (pBeaconSync && pBeaconSync->EnableBeacon) {
- int NumOfBcn;
-
- {
- NumOfBcn = MAX_MESH_NUM;
- }
-
- RTMPCancelTimer(&pAd->CommonCfg.BeaconUpdateTimer, &Cancelled);
-
- for (i = 0; i < NumOfBcn; i++) {
- NdisZeroMemory(pBeaconSync->BeaconBuf[i],
- HW_BEACON_OFFSET);
- NdisZeroMemory(pBeaconSync->BeaconTxWI[i], TXWI_SIZE);
-
- for (offset = 0; offset < HW_BEACON_OFFSET; offset += 4)
- RTMP_IO_WRITE32(pAd,
- pAd->BeaconOffset[i] + offset,
- 0x00);
-
- pBeaconSync->CapabilityInfoLocationInBeacon[i] = 0;
- pBeaconSync->TimIELocationInBeacon[i] = 0;
- }
- pBeaconSync->BeaconBitMap = 0;
- pBeaconSync->DtimBitOn = 0;
- }
-}
-
-void RTUSBBssBeaconStart(struct rt_rtmp_adapter *pAd)
-{
- int apidx;
- struct rt_beacon_sync *pBeaconSync;
-/* LARGE_INTEGER tsfTime, deltaTime; */
-
- pBeaconSync = pAd->CommonCfg.pBeaconSync;
- if (pBeaconSync && pBeaconSync->EnableBeacon) {
- int NumOfBcn;
-
- {
- NumOfBcn = MAX_MESH_NUM;
- }
-
- for (apidx = 0; apidx < NumOfBcn; apidx++) {
- u8 CapabilityInfoLocationInBeacon = 0;
- u8 TimIELocationInBeacon = 0;
-
- NdisZeroMemory(pBeaconSync->BeaconBuf[apidx],
- HW_BEACON_OFFSET);
- pBeaconSync->CapabilityInfoLocationInBeacon[apidx] =
- CapabilityInfoLocationInBeacon;
- pBeaconSync->TimIELocationInBeacon[apidx] =
- TimIELocationInBeacon;
- NdisZeroMemory(pBeaconSync->BeaconTxWI[apidx],
- TXWI_SIZE);
- }
- pBeaconSync->BeaconBitMap = 0;
- pBeaconSync->DtimBitOn = 0;
- pAd->CommonCfg.BeaconUpdateTimer.Repeat = TRUE;
-
- pAd->CommonCfg.BeaconAdjust = 0;
- pAd->CommonCfg.BeaconFactor =
- 0xffffffff / (pAd->CommonCfg.BeaconPeriod << 10);
- pAd->CommonCfg.BeaconRemain =
- (0xffffffff % (pAd->CommonCfg.BeaconPeriod << 10)) + 1;
- DBGPRINT(RT_DEBUG_TRACE,
- ("RTUSBBssBeaconStart:BeaconFactor=%d, BeaconRemain=%d!\n",
- pAd->CommonCfg.BeaconFactor,
- pAd->CommonCfg.BeaconRemain));
- RTMPSetTimer(&pAd->CommonCfg.BeaconUpdateTimer,
- 10 /*pAd->CommonCfg.BeaconPeriod */ );
-
- }
-}
-
-void RTUSBBssBeaconInit(struct rt_rtmp_adapter *pAd)
-{
- struct rt_beacon_sync *pBeaconSync;
- int i;
-
- os_alloc_mem(pAd, (u8 **) (&pAd->CommonCfg.pBeaconSync),
- sizeof(struct rt_beacon_sync));
- /*NdisAllocMemory(pAd->CommonCfg.pBeaconSync, sizeof(struct rt_beacon_sync), MEM_ALLOC_FLAG); */
- if (pAd->CommonCfg.pBeaconSync) {
- pBeaconSync = pAd->CommonCfg.pBeaconSync;
- NdisZeroMemory(pBeaconSync, sizeof(struct rt_beacon_sync));
- for (i = 0; i < HW_BEACON_MAX_COUNT; i++) {
- NdisZeroMemory(pBeaconSync->BeaconBuf[i],
- HW_BEACON_OFFSET);
- pBeaconSync->CapabilityInfoLocationInBeacon[i] = 0;
- pBeaconSync->TimIELocationInBeacon[i] = 0;
- NdisZeroMemory(pBeaconSync->BeaconTxWI[i], TXWI_SIZE);
- }
- pBeaconSync->BeaconBitMap = 0;
-
- /*RTMPInitTimer(pAd, &pAd->CommonCfg.BeaconUpdateTimer, GET_TIMER_FUNCTION(BeaconUpdateExec), pAd, TRUE); */
- pBeaconSync->EnableBeacon = TRUE;
- }
-}
-
-void RTUSBBssBeaconExit(struct rt_rtmp_adapter *pAd)
-{
- struct rt_beacon_sync *pBeaconSync;
- BOOLEAN Cancelled = TRUE;
- int i;
-
- if (pAd->CommonCfg.pBeaconSync) {
- pBeaconSync = pAd->CommonCfg.pBeaconSync;
- pBeaconSync->EnableBeacon = FALSE;
- RTMPCancelTimer(&pAd->CommonCfg.BeaconUpdateTimer, &Cancelled);
- pBeaconSync->BeaconBitMap = 0;
-
- for (i = 0; i < HW_BEACON_MAX_COUNT; i++) {
- NdisZeroMemory(pBeaconSync->BeaconBuf[i],
- HW_BEACON_OFFSET);
- pBeaconSync->CapabilityInfoLocationInBeacon[i] = 0;
- pBeaconSync->TimIELocationInBeacon[i] = 0;
- NdisZeroMemory(pBeaconSync->BeaconTxWI[i], TXWI_SIZE);
- }
-
- os_free_mem(pAd, pAd->CommonCfg.pBeaconSync);
- pAd->CommonCfg.pBeaconSync = NULL;
- }
-}
-
-/*
- ========================================================================
- Routine Description:
- For device work as AP mode but didn't have TBTT interrupt event, we need a mechanism
- to update the beacon context in each Beacon interval. Here we use a periodical timer
- to simulate the TBTT interrupt to handle the beacon context update.
-
- Arguments:
- SystemSpecific1 - Not used.
- FunctionContext - Pointer to our Adapter context.
- SystemSpecific2 - Not used.
- SystemSpecific3 - Not used.
-
- Return Value:
- None
-
- ========================================================================
-*/
-void BeaconUpdateExec(void *SystemSpecific1,
- void *FunctionContext,
- void *SystemSpecific2, void *SystemSpecific3)
-{
- struct rt_rtmp_adapter *pAd = (struct rt_rtmp_adapter *)FunctionContext;
- LARGE_INTEGER tsfTime_a; /*, tsfTime_b, deltaTime_exp, deltaTime_ab; */
- u32 delta, delta2MS, period2US, remain, remain_low, remain_high;
-/* BOOLEAN positive; */
-
- if (pAd->CommonCfg.IsUpdateBeacon == TRUE) {
- ReSyncBeaconTime(pAd);
-
- }
-
- RTMP_IO_READ32(pAd, TSF_TIMER_DW0, &tsfTime_a.u.LowPart);
- RTMP_IO_READ32(pAd, TSF_TIMER_DW1, &tsfTime_a.u.HighPart);
-
- /*positive=getDeltaTime(tsfTime_a, expectedTime, &deltaTime_exp); */
- period2US = (pAd->CommonCfg.BeaconPeriod << 10);
- remain_high = pAd->CommonCfg.BeaconRemain * tsfTime_a.u.HighPart;
- remain_low = tsfTime_a.u.LowPart % (pAd->CommonCfg.BeaconPeriod << 10);
- remain =
- (remain_high + remain_low) % (pAd->CommonCfg.BeaconPeriod << 10);
- delta = (pAd->CommonCfg.BeaconPeriod << 10) - remain;
-
- delta2MS = (delta >> 10);
- if (delta2MS > 150) {
- pAd->CommonCfg.BeaconUpdateTimer.TimerValue = 100;
- pAd->CommonCfg.IsUpdateBeacon = FALSE;
- } else {
- pAd->CommonCfg.BeaconUpdateTimer.TimerValue = delta2MS + 10;
- pAd->CommonCfg.IsUpdateBeacon = TRUE;
- }
-
-}
-
-/********************************************************************
- *
- * 2870 Radio on/off Related functions.
- *
- ********************************************************************/
-void RT28xxUsbMlmeRadioOn(struct rt_rtmp_adapter *pAd)
-{
- struct rt_rtmp_chip_op *pChipOps = &pAd->chipOps;
-
- DBGPRINT(RT_DEBUG_TRACE, ("RT28xxUsbMlmeRadioOn()\n"));
-
- if (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_RADIO_OFF))
- return;
-
- {
- AsicSendCommandToMcu(pAd, 0x31, 0xff, 0x00, 0x02);
- RTMPusecDelay(10000);
- }
- /*NICResetFromError(pAd); */
-
- /* Enable Tx/Rx */
- RTMPEnableRxTx(pAd);
-
- if (pChipOps->AsicReverseRfFromSleepMode)
- pChipOps->AsicReverseRfFromSleepMode(pAd);
-
- /* Clear Radio off flag */
- RTMP_CLEAR_FLAG(pAd, fRTMP_ADAPTER_RADIO_OFF);
-
- RTUSBBulkReceive(pAd);
-
- /* Set LED */
- RTMPSetLED(pAd, LED_RADIO_ON);
-}
-
-void RT28xxUsbMlmeRadioOFF(struct rt_rtmp_adapter *pAd)
-{
- WPDMA_GLO_CFG_STRUC GloCfg;
- u32 Value, i;
-
- DBGPRINT(RT_DEBUG_TRACE, ("RT28xxUsbMlmeRadioOFF()\n"));
-
- if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_RADIO_OFF))
- return;
-
- /* Clear PMKID cache. */
- pAd->StaCfg.SavedPMKNum = 0;
- RTMPZeroMemory(pAd->StaCfg.SavedPMK, (PMKID_NO * sizeof(struct rt_bssid_info)));
-
- /* Link down first if any association exists */
- if (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST)) {
- if (INFRA_ON(pAd) || ADHOC_ON(pAd)) {
- struct rt_mlme_disassoc_req DisReq;
- struct rt_mlme_queue_elem *pMsgElem =
- kmalloc(sizeof(struct rt_mlme_queue_elem),
- MEM_ALLOC_FLAG);
-
- if (pMsgElem) {
- COPY_MAC_ADDR(&DisReq.Addr,
- pAd->CommonCfg.Bssid);
- DisReq.Reason = REASON_DISASSOC_STA_LEAVING;
-
- pMsgElem->Machine = ASSOC_STATE_MACHINE;
- pMsgElem->MsgType = MT2_MLME_DISASSOC_REQ;
- pMsgElem->MsgLen =
- sizeof(struct rt_mlme_disassoc_req);
- NdisMoveMemory(pMsgElem->Msg, &DisReq,
- sizeof
- (struct rt_mlme_disassoc_req));
-
- MlmeDisassocReqAction(pAd, pMsgElem);
- kfree(pMsgElem);
-
- RTMPusecDelay(1000);
- }
- }
- }
- /* Set Radio off flag */
- RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_RADIO_OFF);
-
- {
- /* Link down first if any association exists */
- if (INFRA_ON(pAd) || ADHOC_ON(pAd))
- LinkDown(pAd, FALSE);
- RTMPusecDelay(10000);
-
- /*========================================== */
- /* Clean up old bss table */
- BssTableInit(&pAd->ScanTab);
- }
-
- /* Set LED */
- RTMPSetLED(pAd, LED_RADIO_OFF);
-
- if (pAd->CommonCfg.BBPCurrentBW == BW_40) {
- /* Must using 40MHz. */
- AsicTurnOffRFClk(pAd, pAd->CommonCfg.CentralChannel);
- } else {
- /* Must using 20MHz. */
- AsicTurnOffRFClk(pAd, pAd->CommonCfg.Channel);
- }
-
- /* Disable Tx/Rx DMA */
- RTUSBReadMACRegister(pAd, WPDMA_GLO_CFG, &GloCfg.word); /* disable DMA */
- GloCfg.field.EnableTxDMA = 0;
- GloCfg.field.EnableRxDMA = 0;
- RTUSBWriteMACRegister(pAd, WPDMA_GLO_CFG, GloCfg.word); /* abort all TX rings */
-
- /* Waiting for DMA idle */
- i = 0;
- do {
- RTMP_IO_READ32(pAd, WPDMA_GLO_CFG, &GloCfg.word);
- if ((GloCfg.field.TxDMABusy == 0)
- && (GloCfg.field.RxDMABusy == 0))
- break;
-
- RTMPusecDelay(1000);
- } while (i++ < 100);
-
- /* Disable MAC Tx/Rx */
- RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value);
- Value &= (0xfffffff3);
- RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value);
-
- {
- AsicSendCommandToMcu(pAd, 0x30, 0xff, 0xff, 0x02);
- }
-}
-
-#endif /* RTMP_MAC_USB // */
diff --git a/drivers/staging/rt2860/common/cmm_sanity.c b/drivers/staging/rt2860/common/cmm_sanity.c
deleted file mode 100644
index 3bfb4ad..0000000
--- a/drivers/staging/rt2860/common/cmm_sanity.c
+++ /dev/null
@@ -1,1205 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- sanity.c
-
- Abstract:
-
- Revision History:
- Who When What
- -------- ---------- ----------------------------------------------
- John Chang 2004-09-01 add WMM support
-*/
-#include "../rt_config.h"
-
-extern u8 CISCO_OUI[];
-
-extern u8 WPA_OUI[];
-extern u8 RSN_OUI[];
-extern u8 WME_INFO_ELEM[];
-extern u8 WME_PARM_ELEM[];
-extern u8 Ccx2QosInfo[];
-extern u8 RALINK_OUI[];
-extern u8 BROADCOM_OUI[];
-extern u8 WPS_OUI[];
-
-/*
- ==========================================================================
- Description:
- MLME message sanity check
- Return:
- TRUE if all parameters are OK, FALSE otherwise
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
- */
-BOOLEAN MlmeAddBAReqSanity(struct rt_rtmp_adapter *pAd,
- void * Msg, unsigned long MsgLen, u8 *pAddr2)
-{
- struct rt_mlme_addba_req *pInfo;
-
- pInfo = (struct rt_mlme_addba_req *)Msg;
-
- if ((MsgLen != sizeof(struct rt_mlme_addba_req))) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("MlmeAddBAReqSanity fail - message length not correct.\n"));
- return FALSE;
- }
-
- if ((pInfo->Wcid >= MAX_LEN_OF_MAC_TABLE)) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("MlmeAddBAReqSanity fail - The peer Mac is not associated yet.\n"));
- return FALSE;
- }
-
- if ((pInfo->pAddr[0] & 0x01) == 0x01) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("MlmeAddBAReqSanity fail - broadcast address not support BA\n"));
- return FALSE;
- }
-
- return TRUE;
-}
-
-/*
- ==========================================================================
- Description:
- MLME message sanity check
- Return:
- TRUE if all parameters are OK, FALSE otherwise
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
- */
-BOOLEAN MlmeDelBAReqSanity(struct rt_rtmp_adapter *pAd, void * Msg, unsigned long MsgLen)
-{
- struct rt_mlme_delba_req *pInfo;
- pInfo = (struct rt_mlme_delba_req *)Msg;
-
- if ((MsgLen != sizeof(struct rt_mlme_delba_req))) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("MlmeDelBAReqSanity fail - message length not correct.\n"));
- return FALSE;
- }
-
- if ((pInfo->Wcid >= MAX_LEN_OF_MAC_TABLE)) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("MlmeDelBAReqSanity fail - The peer Mac is not associated yet.\n"));
- return FALSE;
- }
-
- if ((pInfo->TID & 0xf0)) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("MlmeDelBAReqSanity fail - The peer TID is incorrect.\n"));
- return FALSE;
- }
-
- if (NdisEqualMemory
- (pAd->MacTab.Content[pInfo->Wcid].Addr, pInfo->Addr,
- MAC_ADDR_LEN) == 0) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("MlmeDelBAReqSanity fail - the peer addr dosen't exist.\n"));
- return FALSE;
- }
-
- return TRUE;
-}
-
-BOOLEAN PeerAddBAReqActionSanity(struct rt_rtmp_adapter *pAd,
- void * pMsg,
- unsigned long MsgLen, u8 *pAddr2)
-{
- struct rt_frame_802_11 * pFrame = (struct rt_frame_802_11 *) pMsg;
- struct rt_frame_addba_req * pAddFrame;
- pAddFrame = (struct rt_frame_addba_req *) (pMsg);
- if (MsgLen < (sizeof(struct rt_frame_addba_req))) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("PeerAddBAReqActionSanity: ADDBA Request frame length size = %ld incorrect\n",
- MsgLen));
- return FALSE;
- }
- /* we support immediate BA. */
- *(u16 *) (&pAddFrame->BaParm) =
- cpu2le16(*(u16 *) (&pAddFrame->BaParm));
- pAddFrame->TimeOutValue = cpu2le16(pAddFrame->TimeOutValue);
- pAddFrame->BaStartSeq.word = cpu2le16(pAddFrame->BaStartSeq.word);
-
- if (pAddFrame->BaParm.BAPolicy != IMMED_BA) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("PeerAddBAReqActionSanity: ADDBA Request Ba Policy[%d] not support\n",
- pAddFrame->BaParm.BAPolicy));
- DBGPRINT(RT_DEBUG_ERROR,
- ("ADDBA Request. tid=%x, Bufsize=%x, AMSDUSupported=%x \n",
- pAddFrame->BaParm.TID, pAddFrame->BaParm.BufSize,
- pAddFrame->BaParm.AMSDUSupported));
- return FALSE;
- }
- /* we support immediate BA. */
- if (pAddFrame->BaParm.TID & 0xfff0) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("PeerAddBAReqActionSanity: ADDBA Request incorrect TID = %d\n",
- pAddFrame->BaParm.TID));
- return FALSE;
- }
- COPY_MAC_ADDR(pAddr2, pFrame->Hdr.Addr2);
- return TRUE;
-}
-
-BOOLEAN PeerAddBARspActionSanity(struct rt_rtmp_adapter *pAd,
- void * pMsg, unsigned long MsgLen)
-{
- struct rt_frame_addba_rsp * pAddFrame;
-
- pAddFrame = (struct rt_frame_addba_rsp *) (pMsg);
- if (MsgLen < (sizeof(struct rt_frame_addba_rsp))) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("PeerAddBARspActionSanity: ADDBA Response frame length size = %ld incorrect\n",
- MsgLen));
- return FALSE;
- }
- /* we support immediate BA. */
- *(u16 *) (&pAddFrame->BaParm) =
- cpu2le16(*(u16 *) (&pAddFrame->BaParm));
- pAddFrame->StatusCode = cpu2le16(pAddFrame->StatusCode);
- pAddFrame->TimeOutValue = cpu2le16(pAddFrame->TimeOutValue);
-
- if (pAddFrame->BaParm.BAPolicy != IMMED_BA) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("PeerAddBAReqActionSanity: ADDBA Response Ba Policy[%d] not support\n",
- pAddFrame->BaParm.BAPolicy));
- return FALSE;
- }
- /* we support immediate BA. */
- if (pAddFrame->BaParm.TID & 0xfff0) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("PeerAddBARspActionSanity: ADDBA Response incorrect TID = %d\n",
- pAddFrame->BaParm.TID));
- return FALSE;
- }
- return TRUE;
-
-}
-
-BOOLEAN PeerDelBAActionSanity(struct rt_rtmp_adapter *pAd,
- u8 Wcid, void * pMsg, unsigned long MsgLen)
-{
- /*struct rt_frame_802_11 * pFrame = (struct rt_frame_802_11 *)pMsg; */
- struct rt_frame_delba_req * pDelFrame;
- if (MsgLen != (sizeof(struct rt_frame_delba_req)))
- return FALSE;
-
- if (Wcid >= MAX_LEN_OF_MAC_TABLE)
- return FALSE;
-
- pDelFrame = (struct rt_frame_delba_req *) (pMsg);
-
- *(u16 *) (&pDelFrame->DelbaParm) =
- cpu2le16(*(u16 *) (&pDelFrame->DelbaParm));
- pDelFrame->ReasonCode = cpu2le16(pDelFrame->ReasonCode);
-
- if (pDelFrame->DelbaParm.TID & 0xfff0)
- return FALSE;
-
- return TRUE;
-}
-
-/*
- ==========================================================================
- Description:
- MLME message sanity check
- Return:
- TRUE if all parameters are OK, FALSE otherwise
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
- */
-BOOLEAN PeerBeaconAndProbeRspSanity(struct rt_rtmp_adapter *pAd, void * Msg, unsigned long MsgLen, u8 MsgChannel, u8 *pAddr2, u8 *pBssid, char Ssid[], u8 * pSsidLen, u8 * pBssType, u16 * pBeaconPeriod, u8 * pChannel, u8 * pNewChannel, OUT LARGE_INTEGER * pTimestamp, struct rt_cf_parm * pCfParm, u16 * pAtimWin, u16 * pCapabilityInfo, u8 * pErp, u8 * pDtimCount, u8 * pDtimPeriod, u8 * pBcastFlag, u8 * pMessageToMe, u8 SupRate[], u8 * pSupRateLen, u8 ExtRate[], u8 * pExtRateLen, u8 * pCkipFlag, u8 * pAironetCellPowerLimit, struct rt_edca_parm *pEdcaParm, struct rt_qbss_load_parm *pQbssLoad, struct rt_qos_capability_parm *pQosCapability, unsigned long * pRalinkIe, u8 * pHtCapabilityLen, u8 * pPreNHtCapabilityLen, struct rt_ht_capability_ie * pHtCapability, u8 * AddHtInfoLen, struct rt_add_ht_info_ie * AddHtInfo, u8 * NewExtChannelOffset, /* Ht extension channel offset(above or below) */
- u16 * LengthVIE,
- struct rt_ndis_802_11_variable_ies *pVIE)
-{
- u8 *Ptr;
- u8 TimLen;
- struct rt_frame_802_11 * pFrame;
- struct rt_eid * pEid;
- u8 SubType;
- u8 Sanity;
- /*u8 ECWMin, ECWMax; */
- /*MAC_CSR9_STRUC Csr9; */
- unsigned long Length = 0;
-
- /* For some 11a AP which didn't have DS_IE, we use two conditions to decide the channel */
- /* 1. If the AP is 11n enabled, then check the control channel. */
- /* 2. If the AP didn't have any info about channel, use the channel we received this frame as the channel. (May inaccuracy!) */
- u8 CtrlChannel = 0;
-
- /* Add for 3 necessary EID field check */
- Sanity = 0;
-
- *pAtimWin = 0;
- *pErp = 0;
- *pDtimCount = 0;
- *pDtimPeriod = 0;
- *pBcastFlag = 0;
- *pMessageToMe = 0;
- *pExtRateLen = 0;
- *pCkipFlag = 0; /* Default of CkipFlag is 0 */
- *pAironetCellPowerLimit = 0xFF; /* Default of AironetCellPowerLimit is 0xFF */
- *LengthVIE = 0; /* Set the length of VIE to init value 0 */
- *pHtCapabilityLen = 0; /* Set the length of VIE to init value 0 */
- if (pAd->OpMode == OPMODE_STA)
- *pPreNHtCapabilityLen = 0; /* Set the length of VIE to init value 0 */
- *AddHtInfoLen = 0; /* Set the length of VIE to init value 0 */
- *pRalinkIe = 0;
- *pNewChannel = 0;
- *NewExtChannelOffset = 0xff; /*Default 0xff means no such IE */
- pCfParm->bValid = FALSE; /* default: no IE_CF found */
- pQbssLoad->bValid = FALSE; /* default: no IE_QBSS_LOAD found */
- pEdcaParm->bValid = FALSE; /* default: no IE_EDCA_PARAMETER found */
- pQosCapability->bValid = FALSE; /* default: no IE_QOS_CAPABILITY found */
-
- pFrame = (struct rt_frame_802_11 *) Msg;
-
- /* get subtype from header */
- SubType = (u8)pFrame->Hdr.FC.SubType;
-
- /* get Addr2 and BSSID from header */
- COPY_MAC_ADDR(pAddr2, pFrame->Hdr.Addr2);
- COPY_MAC_ADDR(pBssid, pFrame->Hdr.Addr3);
-
- Ptr = pFrame->Octet;
- Length += LENGTH_802_11;
-
- /* get timestamp from payload and advance the pointer */
- NdisMoveMemory(pTimestamp, Ptr, TIMESTAMP_LEN);
-
- pTimestamp->u.LowPart = cpu2le32(pTimestamp->u.LowPart);
- pTimestamp->u.HighPart = cpu2le32(pTimestamp->u.HighPart);
-
- Ptr += TIMESTAMP_LEN;
- Length += TIMESTAMP_LEN;
-
- /* get beacon interval from payload and advance the pointer */
- NdisMoveMemory(pBeaconPeriod, Ptr, 2);
- Ptr += 2;
- Length += 2;
-
- /* get capability info from payload and advance the pointer */
- NdisMoveMemory(pCapabilityInfo, Ptr, 2);
- Ptr += 2;
- Length += 2;
-
- if (CAP_IS_ESS_ON(*pCapabilityInfo))
- *pBssType = BSS_INFRA;
- else
- *pBssType = BSS_ADHOC;
-
- pEid = (struct rt_eid *) Ptr;
-
- /* get variable fields from payload and advance the pointer */
- while ((Length + 2 + pEid->Len) <= MsgLen) {
- /* */
- /* Secure copy VIE to VarIE[MAX_VIE_LEN] didn't overflow. */
- /* */
- if ((*LengthVIE + pEid->Len + 2) >= MAX_VIE_LEN) {
- DBGPRINT(RT_DEBUG_WARN,
- ("PeerBeaconAndProbeRspSanity - Variable IEs out of resource [len(=%d) > MAX_VIE_LEN(=%d)]\n",
- (*LengthVIE + pEid->Len + 2), MAX_VIE_LEN));
- break;
- }
-
- switch (pEid->Eid) {
- case IE_SSID:
- /* Already has one SSID EID in this beacon, ignore the second one */
- if (Sanity & 0x1)
- break;
- if (pEid->Len <= MAX_LEN_OF_SSID) {
- NdisMoveMemory(Ssid, pEid->Octet, pEid->Len);
- *pSsidLen = pEid->Len;
- Sanity |= 0x1;
- } else {
- DBGPRINT(RT_DEBUG_TRACE,
- ("PeerBeaconAndProbeRspSanity - wrong IE_SSID (len=%d)\n",
- pEid->Len));
- return FALSE;
- }
- break;
-
- case IE_SUPP_RATES:
- if (pEid->Len <= MAX_LEN_OF_SUPPORTED_RATES) {
- Sanity |= 0x2;
- NdisMoveMemory(SupRate, pEid->Octet, pEid->Len);
- *pSupRateLen = pEid->Len;
-
- /* TODO: 2004-09-14 not a good design here, cause it exclude extra rates */
- /* from ScanTab. We should report as is. And filter out unsupported */
- /* rates in MlmeAux. */
- /* Check against the supported rates */
- /* RTMPCheckRates(pAd, SupRate, pSupRateLen); */
- } else {
- DBGPRINT(RT_DEBUG_TRACE,
- ("PeerBeaconAndProbeRspSanity - wrong IE_SUPP_RATES (len=%d)\n",
- pEid->Len));
- return FALSE;
- }
- break;
-
- case IE_HT_CAP:
- if (pEid->Len >= SIZE_HT_CAP_IE) /*Note: allow extension! */
- {
- NdisMoveMemory(pHtCapability, pEid->Octet,
- sizeof(struct rt_ht_capability_ie));
- *pHtCapabilityLen = SIZE_HT_CAP_IE; /* Nnow we only support 26 bytes. */
-
- *(u16 *) (&pHtCapability->HtCapInfo) =
- cpu2le16(*(u16 *)
- (&pHtCapability->HtCapInfo));
- *(u16 *) (&pHtCapability->ExtHtCapInfo) =
- cpu2le16(*(u16 *)
- (&pHtCapability->ExtHtCapInfo));
-
- {
- *pPreNHtCapabilityLen = 0; /* Nnow we only support 26 bytes. */
-
- Ptr = (u8 *)pVIE;
- NdisMoveMemory(Ptr + *LengthVIE,
- &pEid->Eid,
- pEid->Len + 2);
- *LengthVIE += (pEid->Len + 2);
- }
- } else {
- DBGPRINT(RT_DEBUG_WARN,
- ("PeerBeaconAndProbeRspSanity - wrong IE_HT_CAP. pEid->Len = %d\n",
- pEid->Len));
- }
-
- break;
- case IE_ADD_HT:
- if (pEid->Len >= sizeof(struct rt_add_ht_info_ie)) {
- /* This IE allows extension, but we can ignore extra bytes beyond our knowledge , so only */
- /* copy first sizeof(struct rt_add_ht_info_ie) */
- NdisMoveMemory(AddHtInfo, pEid->Octet,
- sizeof(struct rt_add_ht_info_ie));
- *AddHtInfoLen = SIZE_ADD_HT_INFO_IE;
-
- CtrlChannel = AddHtInfo->ControlChan;
-
- *(u16 *) (&AddHtInfo->AddHtInfo2) =
- cpu2le16(*(u16 *)
- (&AddHtInfo->AddHtInfo2));
- *(u16 *) (&AddHtInfo->AddHtInfo3) =
- cpu2le16(*(u16 *)
- (&AddHtInfo->AddHtInfo3));
-
- {
- Ptr = (u8 *)pVIE;
- NdisMoveMemory(Ptr + *LengthVIE,
- &pEid->Eid,
- pEid->Len + 2);
- *LengthVIE += (pEid->Len + 2);
- }
- } else {
- DBGPRINT(RT_DEBUG_WARN,
- ("PeerBeaconAndProbeRspSanity - wrong IE_ADD_HT. \n"));
- }
-
- break;
- case IE_SECONDARY_CH_OFFSET:
- if (pEid->Len == 1) {
- *NewExtChannelOffset = pEid->Octet[0];
- } else {
- DBGPRINT(RT_DEBUG_WARN,
- ("PeerBeaconAndProbeRspSanity - wrong IE_SECONDARY_CH_OFFSET. \n"));
- }
-
- break;
- case IE_FH_PARM:
- DBGPRINT(RT_DEBUG_TRACE,
- ("PeerBeaconAndProbeRspSanity(IE_FH_PARM) \n"));
- break;
-
- case IE_DS_PARM:
- if (pEid->Len == 1) {
- *pChannel = *pEid->Octet;
-
- {
- if (ChannelSanity(pAd, *pChannel) == 0) {
-
- return FALSE;
- }
- }
-
- Sanity |= 0x4;
- } else {
- DBGPRINT(RT_DEBUG_TRACE,
- ("PeerBeaconAndProbeRspSanity - wrong IE_DS_PARM (len=%d)\n",
- pEid->Len));
- return FALSE;
- }
- break;
-
- case IE_CF_PARM:
- if (pEid->Len == 6) {
- pCfParm->bValid = TRUE;
- pCfParm->CfpCount = pEid->Octet[0];
- pCfParm->CfpPeriod = pEid->Octet[1];
- pCfParm->CfpMaxDuration =
- pEid->Octet[2] + 256 * pEid->Octet[3];
- pCfParm->CfpDurRemaining =
- pEid->Octet[4] + 256 * pEid->Octet[5];
- } else {
- DBGPRINT(RT_DEBUG_TRACE,
- ("PeerBeaconAndProbeRspSanity - wrong IE_CF_PARM\n"));
- return FALSE;
- }
- break;
-
- case IE_IBSS_PARM:
- if (pEid->Len == 2) {
- NdisMoveMemory(pAtimWin, pEid->Octet,
- pEid->Len);
- } else {
- DBGPRINT(RT_DEBUG_TRACE,
- ("PeerBeaconAndProbeRspSanity - wrong IE_IBSS_PARM\n"));
- return FALSE;
- }
- break;
-
- case IE_TIM:
- if (INFRA_ON(pAd) && SubType == SUBTYPE_BEACON) {
- GetTimBit((char *)pEid, pAd->StaActive.Aid,
- &TimLen, pBcastFlag, pDtimCount,
- pDtimPeriod, pMessageToMe);
- }
- break;
- case IE_CHANNEL_SWITCH_ANNOUNCEMENT:
- if (pEid->Len == 3) {
- *pNewChannel = pEid->Octet[1]; /*extract new channel number */
- }
- break;
-
- /* New for WPA */
- /* CCX v2 has the same IE, we need to parse that too */
- /* Wifi WMM use the same IE vale, need to parse that too */
- /* case IE_WPA: */
- case IE_VENDOR_SPECIFIC:
- /* Check Broadcom/Atheros 802.11n OUI version, for HT Capability IE. */
- /* This HT IE is before IEEE draft set HT IE value.2006-09-28 by Jan. */
- /*if (NdisEqualMemory(pEid->Octet, BROADCOM_OUI, 3) && (pEid->Len >= 4))
- {
- if ((pEid->Octet[3] == OUI_BROADCOM_HT) && (pEid->Len >= 30))
- {
- {
- NdisMoveMemory(pHtCapability, &pEid->Octet[4], sizeof(struct rt_ht_capability_ie));
- *pHtCapabilityLen = SIZE_HT_CAP_IE; // Nnow we only support 26 bytes.
- }
- }
- if ((pEid->Octet[3] == OUI_BROADCOM_HT) && (pEid->Len >= 26))
- {
- {
- NdisMoveMemory(AddHtInfo, &pEid->Octet[4], sizeof(struct rt_add_ht_info_ie));
- *AddHtInfoLen = SIZE_ADD_HT_INFO_IE; // Nnow we only support 26 bytes.
- }
- }
- }
- */
- /* Check the OUI version, filter out non-standard usage */
- if (NdisEqualMemory(pEid->Octet, RALINK_OUI, 3)
- && (pEid->Len == 7)) {
- /**pRalinkIe = pEid->Octet[3]; */
- if (pEid->Octet[3] != 0)
- *pRalinkIe = pEid->Octet[3];
- else
- *pRalinkIe = 0xf0000000; /* Set to non-zero value (can't set bit0-2) to represent this is Ralink Chip. So at linkup, we will set ralinkchip flag. */
- }
- /* This HT IE is before IEEE draft set HT IE value.2006-09-28 by Jan. */
-
- /* Other vendors had production before IE_HT_CAP value is assigned. To backward support those old-firmware AP, */
- /* Check broadcom-defiend pre-802.11nD1.0 OUI for HT related IE, including HT Capatilities IE and HT Information IE */
- else if ((*pHtCapabilityLen == 0)
- && NdisEqualMemory(pEid->Octet, PRE_N_HT_OUI,
- 3) && (pEid->Len >= 4)
- && (pAd->OpMode == OPMODE_STA)) {
- if ((pEid->Octet[3] == OUI_PREN_HT_CAP)
- && (pEid->Len >= 30)
- && (*pHtCapabilityLen == 0)) {
- NdisMoveMemory(pHtCapability,
- &pEid->Octet[4],
- sizeof
- (struct rt_ht_capability_ie));
- *pPreNHtCapabilityLen = SIZE_HT_CAP_IE;
- }
-
- if ((pEid->Octet[3] == OUI_PREN_ADD_HT)
- && (pEid->Len >= 26)) {
- NdisMoveMemory(AddHtInfo,
- &pEid->Octet[4],
- sizeof(struct rt_add_ht_info_ie));
- *AddHtInfoLen = SIZE_ADD_HT_INFO_IE;
- }
- } else if (NdisEqualMemory(pEid->Octet, WPA_OUI, 4)) {
- /* Copy to pVIE which will report to microsoft bssid list. */
- Ptr = (u8 *)pVIE;
- NdisMoveMemory(Ptr + *LengthVIE, &pEid->Eid,
- pEid->Len + 2);
- *LengthVIE += (pEid->Len + 2);
- } else
- if (NdisEqualMemory(pEid->Octet, WME_PARM_ELEM, 6)
- && (pEid->Len == 24)) {
- u8 *ptr;
- int i;
-
- /* parsing EDCA parameters */
- pEdcaParm->bValid = TRUE;
- pEdcaParm->bQAck = FALSE; /* pEid->Octet[0] & 0x10; */
- pEdcaParm->bQueueRequest = FALSE; /* pEid->Octet[0] & 0x20; */
- pEdcaParm->bTxopRequest = FALSE; /* pEid->Octet[0] & 0x40; */
- pEdcaParm->EdcaUpdateCount =
- pEid->Octet[6] & 0x0f;
- pEdcaParm->bAPSDCapable =
- (pEid->Octet[6] & 0x80) ? 1 : 0;
- ptr = &pEid->Octet[8];
- for (i = 0; i < 4; i++) {
- u8 aci = (*ptr & 0x60) >> 5; /* b5~6 is AC INDEX */
- pEdcaParm->bACM[aci] = (((*ptr) & 0x10) == 0x10); /* b5 is ACM */
- pEdcaParm->Aifsn[aci] = (*ptr) & 0x0f; /* b0~3 is AIFSN */
- pEdcaParm->Cwmin[aci] = *(ptr + 1) & 0x0f; /* b0~4 is Cwmin */
- pEdcaParm->Cwmax[aci] = *(ptr + 1) >> 4; /* b5~8 is Cwmax */
- pEdcaParm->Txop[aci] = *(ptr + 2) + 256 * (*(ptr + 3)); /* in unit of 32-us */
- ptr += 4; /* point to next AC */
- }
- } else
- if (NdisEqualMemory(pEid->Octet, WME_INFO_ELEM, 6)
- && (pEid->Len == 7)) {
- /* parsing EDCA parameters */
- pEdcaParm->bValid = TRUE;
- pEdcaParm->bQAck = FALSE; /* pEid->Octet[0] & 0x10; */
- pEdcaParm->bQueueRequest = FALSE; /* pEid->Octet[0] & 0x20; */
- pEdcaParm->bTxopRequest = FALSE; /* pEid->Octet[0] & 0x40; */
- pEdcaParm->EdcaUpdateCount =
- pEid->Octet[6] & 0x0f;
- pEdcaParm->bAPSDCapable =
- (pEid->Octet[6] & 0x80) ? 1 : 0;
-
- /* use default EDCA parameter */
- pEdcaParm->bACM[QID_AC_BE] = 0;
- pEdcaParm->Aifsn[QID_AC_BE] = 3;
- pEdcaParm->Cwmin[QID_AC_BE] = CW_MIN_IN_BITS;
- pEdcaParm->Cwmax[QID_AC_BE] = CW_MAX_IN_BITS;
- pEdcaParm->Txop[QID_AC_BE] = 0;
-
- pEdcaParm->bACM[QID_AC_BK] = 0;
- pEdcaParm->Aifsn[QID_AC_BK] = 7;
- pEdcaParm->Cwmin[QID_AC_BK] = CW_MIN_IN_BITS;
- pEdcaParm->Cwmax[QID_AC_BK] = CW_MAX_IN_BITS;
- pEdcaParm->Txop[QID_AC_BK] = 0;
-
- pEdcaParm->bACM[QID_AC_VI] = 0;
- pEdcaParm->Aifsn[QID_AC_VI] = 2;
- pEdcaParm->Cwmin[QID_AC_VI] =
- CW_MIN_IN_BITS - 1;
- pEdcaParm->Cwmax[QID_AC_VI] = CW_MAX_IN_BITS;
- pEdcaParm->Txop[QID_AC_VI] = 96; /* AC_VI: 96*32us ~= 3ms */
-
- pEdcaParm->bACM[QID_AC_VO] = 0;
- pEdcaParm->Aifsn[QID_AC_VO] = 2;
- pEdcaParm->Cwmin[QID_AC_VO] =
- CW_MIN_IN_BITS - 2;
- pEdcaParm->Cwmax[QID_AC_VO] =
- CW_MAX_IN_BITS - 1;
- pEdcaParm->Txop[QID_AC_VO] = 48; /* AC_VO: 48*32us ~= 1.5ms */
- }
-
- break;
-
- case IE_EXT_SUPP_RATES:
- if (pEid->Len <= MAX_LEN_OF_SUPPORTED_RATES) {
- NdisMoveMemory(ExtRate, pEid->Octet, pEid->Len);
- *pExtRateLen = pEid->Len;
-
- /* TODO: 2004-09-14 not a good design here, cause it exclude extra rates */
- /* from ScanTab. We should report as is. And filter out unsupported */
- /* rates in MlmeAux. */
- /* Check against the supported rates */
- /* RTMPCheckRates(pAd, ExtRate, pExtRateLen); */
- }
- break;
-
- case IE_ERP:
- if (pEid->Len == 1) {
- *pErp = (u8)pEid->Octet[0];
- }
- break;
-
- case IE_AIRONET_CKIP:
- /* 0. Check Aironet IE length, it must be larger or equal to 28 */
- /* Cisco AP350 used length as 28 */
- /* Cisco AP12XX used length as 30 */
- if (pEid->Len < (CKIP_NEGOTIATION_LENGTH - 2))
- break;
-
- /* 1. Copy CKIP flag byte to buffer for process */
- *pCkipFlag = *(pEid->Octet + 8);
- break;
-
- case IE_AP_TX_POWER:
- /* AP Control of Client Transmit Power */
- /*0. Check Aironet IE length, it must be 6 */
- if (pEid->Len != 0x06)
- break;
-
- /* Get cell power limit in dBm */
- if (NdisEqualMemory(pEid->Octet, CISCO_OUI, 3) == 1)
- *pAironetCellPowerLimit = *(pEid->Octet + 4);
- break;
-
- /* WPA2 & 802.11i RSN */
- case IE_RSN:
- /* There is no OUI for version anymore, check the group cipher OUI before copying */
- if (RTMPEqualMemory(pEid->Octet + 2, RSN_OUI, 3)) {
- /* Copy to pVIE which will report to microsoft bssid list. */
- Ptr = (u8 *)pVIE;
- NdisMoveMemory(Ptr + *LengthVIE, &pEid->Eid,
- pEid->Len + 2);
- *LengthVIE += (pEid->Len + 2);
- }
- break;
-
- default:
- break;
- }
-
- Length = Length + 2 + pEid->Len; /* Eid[1] + Len[1]+ content[Len] */
- pEid = (struct rt_eid *) ((u8 *) pEid + 2 + pEid->Len);
- }
-
- /* For some 11a AP. it did not have the channel EID, patch here */
- {
- u8 LatchRfChannel = MsgChannel;
- if ((pAd->LatchRfRegs.Channel > 14) && ((Sanity & 0x4) == 0)) {
- if (CtrlChannel != 0)
- *pChannel = CtrlChannel;
- else
- *pChannel = LatchRfChannel;
- Sanity |= 0x4;
- }
- }
-
- if (Sanity != 0x7) {
- DBGPRINT(RT_DEBUG_LOUD,
- ("PeerBeaconAndProbeRspSanity - missing field, Sanity=0x%02x\n",
- Sanity));
- return FALSE;
- } else {
- return TRUE;
- }
-
-}
-
-/*
- ==========================================================================
- Description:
- MLME message sanity check
- Return:
- TRUE if all parameters are OK, FALSE otherwise
- ==========================================================================
- */
-BOOLEAN MlmeScanReqSanity(struct rt_rtmp_adapter *pAd,
- void * Msg,
- unsigned long MsgLen,
- u8 * pBssType,
- char Ssid[],
- u8 * pSsidLen, u8 * pScanType)
-{
- struct rt_mlme_scan_req *Info;
-
- Info = (struct rt_mlme_scan_req *)(Msg);
- *pBssType = Info->BssType;
- *pSsidLen = Info->SsidLen;
- NdisMoveMemory(Ssid, Info->Ssid, *pSsidLen);
- *pScanType = Info->ScanType;
-
- if ((*pBssType == BSS_INFRA || *pBssType == BSS_ADHOC
- || *pBssType == BSS_ANY)
- && (*pScanType == SCAN_ACTIVE || *pScanType == SCAN_PASSIVE)) {
- return TRUE;
- } else {
- DBGPRINT(RT_DEBUG_TRACE,
- ("MlmeScanReqSanity fail - wrong BssType or ScanType\n"));
- return FALSE;
- }
-}
-
-/* IRQL = DISPATCH_LEVEL */
-u8 ChannelSanity(struct rt_rtmp_adapter *pAd, u8 channel)
-{
- int i;
-
- for (i = 0; i < pAd->ChannelListNum; i++) {
- if (channel == pAd->ChannelList[i].Channel)
- return 1;
- }
- return 0;
-}
-
-/*
- ==========================================================================
- Description:
- MLME message sanity check
- Return:
- TRUE if all parameters are OK, FALSE otherwise
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
- */
-BOOLEAN PeerDeauthSanity(struct rt_rtmp_adapter *pAd,
- void * Msg,
- unsigned long MsgLen,
- u8 *pAddr2, u16 * pReason)
-{
- struct rt_frame_802_11 * pFrame = (struct rt_frame_802_11 *) Msg;
-
- COPY_MAC_ADDR(pAddr2, pFrame->Hdr.Addr2);
- NdisMoveMemory(pReason, &pFrame->Octet[0], 2);
-
- return TRUE;
-}
-
-/*
- ==========================================================================
- Description:
- MLME message sanity check
- Return:
- TRUE if all parameters are OK, FALSE otherwise
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
- */
-BOOLEAN PeerAuthSanity(struct rt_rtmp_adapter *pAd,
- void * Msg,
- unsigned long MsgLen,
- u8 *pAddr,
- u16 * pAlg,
- u16 * pSeq,
- u16 * pStatus, char * pChlgText)
-{
- struct rt_frame_802_11 * pFrame = (struct rt_frame_802_11 *) Msg;
-
- COPY_MAC_ADDR(pAddr, pFrame->Hdr.Addr2);
- NdisMoveMemory(pAlg, &pFrame->Octet[0], 2);
- NdisMoveMemory(pSeq, &pFrame->Octet[2], 2);
- NdisMoveMemory(pStatus, &pFrame->Octet[4], 2);
-
- if (*pAlg == AUTH_MODE_OPEN) {
- if (*pSeq == 1 || *pSeq == 2) {
- return TRUE;
- } else {
- DBGPRINT(RT_DEBUG_TRACE,
- ("PeerAuthSanity fail - wrong Seg#\n"));
- return FALSE;
- }
- } else if (*pAlg == AUTH_MODE_KEY) {
- if (*pSeq == 1 || *pSeq == 4) {
- return TRUE;
- } else if (*pSeq == 2 || *pSeq == 3) {
- NdisMoveMemory(pChlgText, &pFrame->Octet[8],
- CIPHER_TEXT_LEN);
- return TRUE;
- } else {
- DBGPRINT(RT_DEBUG_TRACE,
- ("PeerAuthSanity fail - wrong Seg#\n"));
- return FALSE;
- }
- } else {
- DBGPRINT(RT_DEBUG_TRACE,
- ("PeerAuthSanity fail - wrong algorithm\n"));
- return FALSE;
- }
-}
-
-/*
- ==========================================================================
- Description:
- MLME message sanity check
- Return:
- TRUE if all parameters are OK, FALSE otherwise
- ==========================================================================
- */
-BOOLEAN MlmeAuthReqSanity(struct rt_rtmp_adapter *pAd,
- void * Msg,
- unsigned long MsgLen,
- u8 *pAddr,
- unsigned long * pTimeout, u16 * pAlg)
-{
- struct rt_mlme_auth_req *pInfo;
-
- pInfo = (struct rt_mlme_auth_req *)Msg;
- COPY_MAC_ADDR(pAddr, pInfo->Addr);
- *pTimeout = pInfo->Timeout;
- *pAlg = pInfo->Alg;
-
- if (((*pAlg == AUTH_MODE_KEY) || (*pAlg == AUTH_MODE_OPEN)
- ) && ((*pAddr & 0x01) == 0)) {
- return TRUE;
- } else {
- DBGPRINT(RT_DEBUG_TRACE,
- ("MlmeAuthReqSanity fail - wrong algorithm\n"));
- return FALSE;
- }
-}
-
-/*
- ==========================================================================
- Description:
- MLME message sanity check
- Return:
- TRUE if all parameters are OK, FALSE otherwise
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
- */
-BOOLEAN MlmeAssocReqSanity(struct rt_rtmp_adapter *pAd,
- void * Msg,
- unsigned long MsgLen,
- u8 *pApAddr,
- u16 * pCapabilityInfo,
- unsigned long * pTimeout, u16 * pListenIntv)
-{
- struct rt_mlme_assoc_req *pInfo;
-
- pInfo = (struct rt_mlme_assoc_req *)Msg;
- *pTimeout = pInfo->Timeout; /* timeout */
- COPY_MAC_ADDR(pApAddr, pInfo->Addr); /* AP address */
- *pCapabilityInfo = pInfo->CapabilityInfo; /* capability info */
- *pListenIntv = pInfo->ListenIntv;
-
- return TRUE;
-}
-
-/*
- ==========================================================================
- Description:
- MLME message sanity check
- Return:
- TRUE if all parameters are OK, FALSE otherwise
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
- */
-BOOLEAN PeerDisassocSanity(struct rt_rtmp_adapter *pAd,
- void * Msg,
- unsigned long MsgLen,
- u8 *pAddr2, u16 * pReason)
-{
- struct rt_frame_802_11 * pFrame = (struct rt_frame_802_11 *) Msg;
-
- COPY_MAC_ADDR(pAddr2, pFrame->Hdr.Addr2);
- NdisMoveMemory(pReason, &pFrame->Octet[0], 2);
-
- return TRUE;
-}
-
-/*
- ========================================================================
- Routine Description:
- Sanity check NetworkType (11b, 11g or 11a)
-
- Arguments:
- pBss - Pointer to BSS table.
-
- Return Value:
- Ndis802_11DS .......(11b)
- Ndis802_11OFDM24....(11g)
- Ndis802_11OFDM5.....(11a)
-
- IRQL = DISPATCH_LEVEL
-
- ========================================================================
-*/
-NDIS_802_11_NETWORK_TYPE NetworkTypeInUseSanity(struct rt_bss_entry *pBss)
-{
- NDIS_802_11_NETWORK_TYPE NetWorkType;
- u8 rate, i;
-
- NetWorkType = Ndis802_11DS;
-
- if (pBss->Channel <= 14) {
- /* */
- /* First check support Rate. */
- /* */
- for (i = 0; i < pBss->SupRateLen; i++) {
- rate = pBss->SupRate[i] & 0x7f; /* Mask out basic rate set bit */
- if ((rate == 2) || (rate == 4) || (rate == 11)
- || (rate == 22)) {
- continue;
- } else {
- /* */
- /* Otherwise (even rate > 108) means Ndis802_11OFDM24 */
- /* */
- NetWorkType = Ndis802_11OFDM24;
- break;
- }
- }
-
- /* */
- /* Second check Extend Rate. */
- /* */
- if (NetWorkType != Ndis802_11OFDM24) {
- for (i = 0; i < pBss->ExtRateLen; i++) {
- rate = pBss->SupRate[i] & 0x7f; /* Mask out basic rate set bit */
- if ((rate == 2) || (rate == 4) || (rate == 11)
- || (rate == 22)) {
- continue;
- } else {
- /* */
- /* Otherwise (even rate > 108) means Ndis802_11OFDM24 */
- /* */
- NetWorkType = Ndis802_11OFDM24;
- break;
- }
- }
- }
- } else {
- NetWorkType = Ndis802_11OFDM5;
- }
-
- if (pBss->HtCapabilityLen != 0) {
- if (NetWorkType == Ndis802_11OFDM5)
- NetWorkType = Ndis802_11OFDM5_N;
- else
- NetWorkType = Ndis802_11OFDM24_N;
- }
-
- return NetWorkType;
-}
-
-/*
- ==========================================================================
- Description:
- Check the validity of the received EAPoL frame
- Return:
- TRUE if all parameters are OK,
- FALSE otherwise
- ==========================================================================
- */
-BOOLEAN PeerWpaMessageSanity(struct rt_rtmp_adapter *pAd,
- struct rt_eapol_packet * pMsg,
- unsigned long MsgLen,
- u8 MsgType, struct rt_mac_table_entry *pEntry)
-{
- u8 mic[LEN_KEY_DESC_MIC], digest[80], KEYDATA[MAX_LEN_OF_RSNIE];
- BOOLEAN bReplayDiff = FALSE;
- BOOLEAN bWPA2 = FALSE;
- struct rt_key_info EapolKeyInfo;
- u8 GroupKeyIndex = 0;
-
- NdisZeroMemory(mic, sizeof(mic));
- NdisZeroMemory(digest, sizeof(digest));
- NdisZeroMemory(KEYDATA, sizeof(KEYDATA));
- NdisZeroMemory((u8 *)& EapolKeyInfo, sizeof(EapolKeyInfo));
-
- NdisMoveMemory((u8 *)& EapolKeyInfo,
- (u8 *)& pMsg->KeyDesc.KeyInfo, sizeof(struct rt_key_info));
-
- *((u16 *) & EapolKeyInfo) = cpu2le16(*((u16 *) & EapolKeyInfo));
-
- /* Choose WPA2 or not */
- if ((pEntry->AuthMode == Ndis802_11AuthModeWPA2)
- || (pEntry->AuthMode == Ndis802_11AuthModeWPA2PSK))
- bWPA2 = TRUE;
-
- /* 0. Check MsgType */
- if ((MsgType > EAPOL_GROUP_MSG_2) || (MsgType < EAPOL_PAIR_MSG_1)) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("The message type is invalid(%d)! \n", MsgType));
- return FALSE;
- }
- /* 1. Replay counter check */
- if (MsgType == EAPOL_PAIR_MSG_1 || MsgType == EAPOL_PAIR_MSG_3 || MsgType == EAPOL_GROUP_MSG_1) /* For supplicant */
- {
- /* First validate replay counter, only accept message with larger replay counter. */
- /* Let equal pass, some AP start with all zero replay counter */
- u8 ZeroReplay[LEN_KEY_DESC_REPLAY];
-
- NdisZeroMemory(ZeroReplay, LEN_KEY_DESC_REPLAY);
- if ((RTMPCompareMemory
- (pMsg->KeyDesc.ReplayCounter, pEntry->R_Counter,
- LEN_KEY_DESC_REPLAY) != 1)
- &&
- (RTMPCompareMemory
- (pMsg->KeyDesc.ReplayCounter, ZeroReplay,
- LEN_KEY_DESC_REPLAY) != 0)) {
- bReplayDiff = TRUE;
- }
- } else if (MsgType == EAPOL_PAIR_MSG_2 || MsgType == EAPOL_PAIR_MSG_4 || MsgType == EAPOL_GROUP_MSG_2) /* For authenticator */
- {
- /* check Replay Counter coresponds to MSG from authenticator, otherwise discard */
- if (!NdisEqualMemory
- (pMsg->KeyDesc.ReplayCounter, pEntry->R_Counter,
- LEN_KEY_DESC_REPLAY)) {
- bReplayDiff = TRUE;
- }
- }
- /* Replay Counter different condition */
- if (bReplayDiff) {
- /* send wireless event - for replay counter different */
- if (pAd->CommonCfg.bWirelessEvent)
- RTMPSendWirelessEvent(pAd,
- IW_REPLAY_COUNTER_DIFF_EVENT_FLAG,
- pEntry->Addr, pEntry->apidx, 0);
-
- if (MsgType < EAPOL_GROUP_MSG_1) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("Replay Counter Different in pairwise msg %d of 4-way handshake!\n",
- MsgType));
- } else {
- DBGPRINT(RT_DEBUG_ERROR,
- ("Replay Counter Different in group msg %d of 2-way handshake!\n",
- (MsgType - EAPOL_PAIR_MSG_4)));
- }
-
- hex_dump("Receive replay counter ", pMsg->KeyDesc.ReplayCounter,
- LEN_KEY_DESC_REPLAY);
- hex_dump("Current replay counter ", pEntry->R_Counter,
- LEN_KEY_DESC_REPLAY);
- return FALSE;
- }
- /* 2. Verify MIC except Pairwise Msg1 */
- if (MsgType != EAPOL_PAIR_MSG_1) {
- u8 rcvd_mic[LEN_KEY_DESC_MIC];
-
- /* Record the received MIC for check later */
- NdisMoveMemory(rcvd_mic, pMsg->KeyDesc.KeyMic,
- LEN_KEY_DESC_MIC);
- NdisZeroMemory(pMsg->KeyDesc.KeyMic, LEN_KEY_DESC_MIC);
-
- if (EapolKeyInfo.KeyDescVer == DESC_TYPE_TKIP) /* TKIP */
- {
- HMAC_MD5(pEntry->PTK, LEN_EAP_MICK, (u8 *)pMsg,
- MsgLen, mic, MD5_DIGEST_SIZE);
- } else if (EapolKeyInfo.KeyDescVer == DESC_TYPE_AES) /* AES */
- {
- HMAC_SHA1(pEntry->PTK, LEN_EAP_MICK, (u8 *)pMsg,
- MsgLen, digest, SHA1_DIGEST_SIZE);
- NdisMoveMemory(mic, digest, LEN_KEY_DESC_MIC);
- }
-
- if (!NdisEqualMemory(rcvd_mic, mic, LEN_KEY_DESC_MIC)) {
- /* send wireless event - for MIC different */
- if (pAd->CommonCfg.bWirelessEvent)
- RTMPSendWirelessEvent(pAd,
- IW_MIC_DIFF_EVENT_FLAG,
- pEntry->Addr,
- pEntry->apidx, 0);
-
- if (MsgType < EAPOL_GROUP_MSG_1) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("MIC Different in pairwise msg %d of 4-way handshake!\n",
- MsgType));
- } else {
- DBGPRINT(RT_DEBUG_ERROR,
- ("MIC Different in group msg %d of 2-way handshake!\n",
- (MsgType - EAPOL_PAIR_MSG_4)));
- }
-
- hex_dump("Received MIC", rcvd_mic, LEN_KEY_DESC_MIC);
- hex_dump("Desired MIC", mic, LEN_KEY_DESC_MIC);
-
- return FALSE;
- }
- }
- /* 1. Decrypt the Key Data field if GTK is included. */
- /* 2. Extract the context of the Key Data field if it exist. */
- /* The field in pairwise_msg_2_WPA1(WPA2) & pairwise_msg_3_WPA1 is clear. */
- /* The field in group_msg_1_WPA1(WPA2) & pairwise_msg_3_WPA2 is encrypted. */
- if (CONV_ARRARY_TO_u16(pMsg->KeyDesc.KeyDataLen) > 0) {
- /* Decrypt this field */
- if ((MsgType == EAPOL_PAIR_MSG_3 && bWPA2)
- || (MsgType == EAPOL_GROUP_MSG_1)) {
- if ((EapolKeyInfo.KeyDescVer == DESC_TYPE_AES)) {
- /* AES */
- AES_GTK_KEY_UNWRAP(&pEntry->PTK[16], KEYDATA,
- CONV_ARRARY_TO_u16(pMsg->
- KeyDesc.
- KeyDataLen),
- pMsg->KeyDesc.KeyData);
- } else {
- int i;
- u8 Key[32];
- /* Decrypt TKIP GTK */
- /* Construct 32 bytes RC4 Key */
- NdisMoveMemory(Key, pMsg->KeyDesc.KeyIv, 16);
- NdisMoveMemory(&Key[16], &pEntry->PTK[16], 16);
- ARCFOUR_INIT(&pAd->PrivateInfo.WEPCONTEXT, Key,
- 32);
- /*discard first 256 bytes */
- for (i = 0; i < 256; i++)
- ARCFOUR_BYTE(&pAd->PrivateInfo.
- WEPCONTEXT);
- /* Decrypt GTK. Becareful, there is no ICV to check the result is correct or not */
- ARCFOUR_DECRYPT(&pAd->PrivateInfo.WEPCONTEXT,
- KEYDATA, pMsg->KeyDesc.KeyData,
- CONV_ARRARY_TO_u16(pMsg->
- KeyDesc.
- KeyDataLen));
- }
-
- if (!bWPA2 && (MsgType == EAPOL_GROUP_MSG_1))
- GroupKeyIndex = EapolKeyInfo.KeyIndex;
-
- } else if ((MsgType == EAPOL_PAIR_MSG_2)
- || (MsgType == EAPOL_PAIR_MSG_3 && !bWPA2)) {
- NdisMoveMemory(KEYDATA, pMsg->KeyDesc.KeyData,
- CONV_ARRARY_TO_u16(pMsg->KeyDesc.
- KeyDataLen));
- } else {
-
- return TRUE;
- }
-
- /* Parse Key Data field to */
- /* 1. verify RSN IE for pairwise_msg_2_WPA1(WPA2) ,pairwise_msg_3_WPA1(WPA2) */
- /* 2. verify KDE format for pairwise_msg_3_WPA2, group_msg_1_WPA2 */
- /* 3. update shared key for pairwise_msg_3_WPA2, group_msg_1_WPA1(WPA2) */
- if (!RTMPParseEapolKeyData(pAd, KEYDATA,
- CONV_ARRARY_TO_u16(pMsg->KeyDesc.
- KeyDataLen),
- GroupKeyIndex, MsgType, bWPA2,
- pEntry)) {
- return FALSE;
- }
- }
-
- return TRUE;
-
-}
diff --git a/drivers/staging/rt2860/common/cmm_sync.c b/drivers/staging/rt2860/common/cmm_sync.c
deleted file mode 100644
index aefe1b7..0000000
--- a/drivers/staging/rt2860/common/cmm_sync.c
+++ /dev/null
@@ -1,718 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- cmm_sync.c
-
- Abstract:
-
- Revision History:
- Who When What
- -------- ---------- ----------------------------------------------
- John Chang 2004-09-01 modified for rt2561/2661
-*/
-#include "../rt_config.h"
-
-/* 2.4 Ghz channel plan index in the TxPower arrays. */
-#define BG_BAND_REGION_0_START 0 /* 1,2,3,4,5,6,7,8,9,10,11 */
-#define BG_BAND_REGION_0_SIZE 11
-#define BG_BAND_REGION_1_START 0 /* 1,2,3,4,5,6,7,8,9,10,11,12,13 */
-#define BG_BAND_REGION_1_SIZE 13
-#define BG_BAND_REGION_2_START 9 /* 10,11 */
-#define BG_BAND_REGION_2_SIZE 2
-#define BG_BAND_REGION_3_START 9 /* 10,11,12,13 */
-#define BG_BAND_REGION_3_SIZE 4
-#define BG_BAND_REGION_4_START 13 /* 14 */
-#define BG_BAND_REGION_4_SIZE 1
-#define BG_BAND_REGION_5_START 0 /* 1,2,3,4,5,6,7,8,9,10,11,12,13,14 */
-#define BG_BAND_REGION_5_SIZE 14
-#define BG_BAND_REGION_6_START 2 /* 3,4,5,6,7,8,9 */
-#define BG_BAND_REGION_6_SIZE 7
-#define BG_BAND_REGION_7_START 4 /* 5,6,7,8,9,10,11,12,13 */
-#define BG_BAND_REGION_7_SIZE 9
-#define BG_BAND_REGION_31_START 0 /* 1,2,3,4,5,6,7,8,9,10,11,12,13,14 */
-#define BG_BAND_REGION_31_SIZE 14
-
-/* 5 Ghz channel plan index in the TxPower arrays. */
-u8 A_BAND_REGION_0_CHANNEL_LIST[] =
- { 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165 };
-u8 A_BAND_REGION_1_CHANNEL_LIST[] =
- { 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128,
-132, 136, 140 };
-u8 A_BAND_REGION_2_CHANNEL_LIST[] = { 36, 40, 44, 48, 52, 56, 60, 64 };
-u8 A_BAND_REGION_3_CHANNEL_LIST[] = { 52, 56, 60, 64, 149, 153, 157, 161 };
-u8 A_BAND_REGION_4_CHANNEL_LIST[] = { 149, 153, 157, 161, 165 };
-u8 A_BAND_REGION_5_CHANNEL_LIST[] = { 149, 153, 157, 161 };
-u8 A_BAND_REGION_6_CHANNEL_LIST[] = { 36, 40, 44, 48 };
-u8 A_BAND_REGION_7_CHANNEL_LIST[] =
- { 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128,
-132, 136, 140, 149, 153, 157, 161, 165, 169, 173 };
-u8 A_BAND_REGION_8_CHANNEL_LIST[] = { 52, 56, 60, 64 };
-u8 A_BAND_REGION_9_CHANNEL_LIST[] =
- { 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140,
-149, 153, 157, 161, 165 };
-u8 A_BAND_REGION_10_CHANNEL_LIST[] =
- { 36, 40, 44, 48, 149, 153, 157, 161, 165 };
-u8 A_BAND_REGION_11_CHANNEL_LIST[] =
- { 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 149, 153,
-157, 161 };
-u8 A_BAND_REGION_12_CHANNEL_LIST[] =
- { 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128,
-132, 136, 140 };
-u8 A_BAND_REGION_13_CHANNEL_LIST[] =
- { 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140,
-149, 153, 157, 161 };
-u8 A_BAND_REGION_14_CHANNEL_LIST[] =
- { 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 136, 140, 149,
-153, 157, 161, 165 };
-u8 A_BAND_REGION_15_CHANNEL_LIST[] = { 149, 153, 157, 161, 165, 169, 173 };
-
-/*BaSizeArray follows the 802.11n definition as MaxRxFactor. 2^(13+factor) bytes. When factor =0, it's about Ba buffer size =8. */
-u8 BaSizeArray[4] = { 8, 16, 32, 64 };
-
-/*
- ==========================================================================
- Description:
- Update StaCfg->ChannelList[] according to 1) Country Region 2) RF IC type,
- and 3) PHY-mode user selected.
- The outcome is used by driver when doing site survey.
-
- IRQL = PASSIVE_LEVEL
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
- */
-void BuildChannelList(struct rt_rtmp_adapter *pAd)
-{
- u8 i, j, index = 0, num = 0;
- u8 *pChannelList = NULL;
-
- NdisZeroMemory(pAd->ChannelList,
- MAX_NUM_OF_CHANNELS * sizeof(struct rt_channel_tx_power));
-
- /* if not 11a-only mode, channel list starts from 2.4Ghz band */
- if ((pAd->CommonCfg.PhyMode != PHY_11A)
- && (pAd->CommonCfg.PhyMode != PHY_11AN_MIXED)
- && (pAd->CommonCfg.PhyMode != PHY_11N_5G)
- ) {
- switch (pAd->CommonCfg.CountryRegion & 0x7f) {
- case REGION_0_BG_BAND: /* 1 -11 */
- NdisMoveMemory(&pAd->ChannelList[index],
- &pAd->TxPower[BG_BAND_REGION_0_START],
- sizeof(struct rt_channel_tx_power) *
- BG_BAND_REGION_0_SIZE);
- index += BG_BAND_REGION_0_SIZE;
- break;
- case REGION_1_BG_BAND: /* 1 - 13 */
- NdisMoveMemory(&pAd->ChannelList[index],
- &pAd->TxPower[BG_BAND_REGION_1_START],
- sizeof(struct rt_channel_tx_power) *
- BG_BAND_REGION_1_SIZE);
- index += BG_BAND_REGION_1_SIZE;
- break;
- case REGION_2_BG_BAND: /* 10 - 11 */
- NdisMoveMemory(&pAd->ChannelList[index],
- &pAd->TxPower[BG_BAND_REGION_2_START],
- sizeof(struct rt_channel_tx_power) *
- BG_BAND_REGION_2_SIZE);
- index += BG_BAND_REGION_2_SIZE;
- break;
- case REGION_3_BG_BAND: /* 10 - 13 */
- NdisMoveMemory(&pAd->ChannelList[index],
- &pAd->TxPower[BG_BAND_REGION_3_START],
- sizeof(struct rt_channel_tx_power) *
- BG_BAND_REGION_3_SIZE);
- index += BG_BAND_REGION_3_SIZE;
- break;
- case REGION_4_BG_BAND: /* 14 */
- NdisMoveMemory(&pAd->ChannelList[index],
- &pAd->TxPower[BG_BAND_REGION_4_START],
- sizeof(struct rt_channel_tx_power) *
- BG_BAND_REGION_4_SIZE);
- index += BG_BAND_REGION_4_SIZE;
- break;
- case REGION_5_BG_BAND: /* 1 - 14 */
- NdisMoveMemory(&pAd->ChannelList[index],
- &pAd->TxPower[BG_BAND_REGION_5_START],
- sizeof(struct rt_channel_tx_power) *
- BG_BAND_REGION_5_SIZE);
- index += BG_BAND_REGION_5_SIZE;
- break;
- case REGION_6_BG_BAND: /* 3 - 9 */
- NdisMoveMemory(&pAd->ChannelList[index],
- &pAd->TxPower[BG_BAND_REGION_6_START],
- sizeof(struct rt_channel_tx_power) *
- BG_BAND_REGION_6_SIZE);
- index += BG_BAND_REGION_6_SIZE;
- break;
- case REGION_7_BG_BAND: /* 5 - 13 */
- NdisMoveMemory(&pAd->ChannelList[index],
- &pAd->TxPower[BG_BAND_REGION_7_START],
- sizeof(struct rt_channel_tx_power) *
- BG_BAND_REGION_7_SIZE);
- index += BG_BAND_REGION_7_SIZE;
- break;
- case REGION_31_BG_BAND: /* 1 - 14 */
- NdisMoveMemory(&pAd->ChannelList[index],
- &pAd->TxPower[BG_BAND_REGION_31_START],
- sizeof(struct rt_channel_tx_power) *
- BG_BAND_REGION_31_SIZE);
- index += BG_BAND_REGION_31_SIZE;
- break;
- default: /* Error. should never happen */
- break;
- }
- for (i = 0; i < index; i++)
- pAd->ChannelList[i].MaxTxPwr = 20;
- }
-
- if ((pAd->CommonCfg.PhyMode == PHY_11A)
- || (pAd->CommonCfg.PhyMode == PHY_11ABG_MIXED)
- || (pAd->CommonCfg.PhyMode == PHY_11ABGN_MIXED)
- || (pAd->CommonCfg.PhyMode == PHY_11AN_MIXED)
- || (pAd->CommonCfg.PhyMode == PHY_11AGN_MIXED)
- || (pAd->CommonCfg.PhyMode == PHY_11N_5G)
- ) {
- switch (pAd->CommonCfg.CountryRegionForABand & 0x7f) {
- case REGION_0_A_BAND:
- num =
- sizeof(A_BAND_REGION_0_CHANNEL_LIST) /
- sizeof(u8);
- pChannelList = A_BAND_REGION_0_CHANNEL_LIST;
- break;
- case REGION_1_A_BAND:
- num =
- sizeof(A_BAND_REGION_1_CHANNEL_LIST) /
- sizeof(u8);
- pChannelList = A_BAND_REGION_1_CHANNEL_LIST;
- break;
- case REGION_2_A_BAND:
- num =
- sizeof(A_BAND_REGION_2_CHANNEL_LIST) /
- sizeof(u8);
- pChannelList = A_BAND_REGION_2_CHANNEL_LIST;
- break;
- case REGION_3_A_BAND:
- num =
- sizeof(A_BAND_REGION_3_CHANNEL_LIST) /
- sizeof(u8);
- pChannelList = A_BAND_REGION_3_CHANNEL_LIST;
- break;
- case REGION_4_A_BAND:
- num =
- sizeof(A_BAND_REGION_4_CHANNEL_LIST) /
- sizeof(u8);
- pChannelList = A_BAND_REGION_4_CHANNEL_LIST;
- break;
- case REGION_5_A_BAND:
- num =
- sizeof(A_BAND_REGION_5_CHANNEL_LIST) /
- sizeof(u8);
- pChannelList = A_BAND_REGION_5_CHANNEL_LIST;
- break;
- case REGION_6_A_BAND:
- num =
- sizeof(A_BAND_REGION_6_CHANNEL_LIST) /
- sizeof(u8);
- pChannelList = A_BAND_REGION_6_CHANNEL_LIST;
- break;
- case REGION_7_A_BAND:
- num =
- sizeof(A_BAND_REGION_7_CHANNEL_LIST) /
- sizeof(u8);
- pChannelList = A_BAND_REGION_7_CHANNEL_LIST;
- break;
- case REGION_8_A_BAND:
- num =
- sizeof(A_BAND_REGION_8_CHANNEL_LIST) /
- sizeof(u8);
- pChannelList = A_BAND_REGION_8_CHANNEL_LIST;
- break;
- case REGION_9_A_BAND:
- num =
- sizeof(A_BAND_REGION_9_CHANNEL_LIST) /
- sizeof(u8);
- pChannelList = A_BAND_REGION_9_CHANNEL_LIST;
- break;
-
- case REGION_10_A_BAND:
- num =
- sizeof(A_BAND_REGION_10_CHANNEL_LIST) /
- sizeof(u8);
- pChannelList = A_BAND_REGION_10_CHANNEL_LIST;
- break;
-
- case REGION_11_A_BAND:
- num =
- sizeof(A_BAND_REGION_11_CHANNEL_LIST) /
- sizeof(u8);
- pChannelList = A_BAND_REGION_11_CHANNEL_LIST;
- break;
- case REGION_12_A_BAND:
- num =
- sizeof(A_BAND_REGION_12_CHANNEL_LIST) /
- sizeof(u8);
- pChannelList = A_BAND_REGION_12_CHANNEL_LIST;
- break;
- case REGION_13_A_BAND:
- num =
- sizeof(A_BAND_REGION_13_CHANNEL_LIST) /
- sizeof(u8);
- pChannelList = A_BAND_REGION_13_CHANNEL_LIST;
- break;
- case REGION_14_A_BAND:
- num =
- sizeof(A_BAND_REGION_14_CHANNEL_LIST) /
- sizeof(u8);
- pChannelList = A_BAND_REGION_14_CHANNEL_LIST;
- break;
- case REGION_15_A_BAND:
- num =
- sizeof(A_BAND_REGION_15_CHANNEL_LIST) /
- sizeof(u8);
- pChannelList = A_BAND_REGION_15_CHANNEL_LIST;
- break;
- default: /* Error. should never happen */
- DBGPRINT(RT_DEBUG_WARN,
- ("countryregion=%d not support",
- pAd->CommonCfg.CountryRegionForABand));
- break;
- }
-
- if (num != 0) {
- u8 RadarCh[15] =
- { 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124,
- 128, 132, 136, 140 };
- for (i = 0; i < num; i++) {
- for (j = 0; j < MAX_NUM_OF_CHANNELS; j++) {
- if (pChannelList[i] ==
- pAd->TxPower[j].Channel)
- NdisMoveMemory(&pAd->
- ChannelList[index
- + i],
- &pAd->TxPower[j],
- sizeof
- (struct rt_channel_tx_power));
- }
- for (j = 0; j < 15; j++) {
- if (pChannelList[i] == RadarCh[j])
- pAd->ChannelList[index +
- i].DfsReq =
- TRUE;
- }
- pAd->ChannelList[index + i].MaxTxPwr = 20;
- }
- index += num;
- }
- }
-
- pAd->ChannelListNum = index;
- DBGPRINT(RT_DEBUG_TRACE,
- ("country code=%d/%d, RFIC=%d, PHY mode=%d, support %d channels\n",
- pAd->CommonCfg.CountryRegion,
- pAd->CommonCfg.CountryRegionForABand, pAd->RfIcType,
- pAd->CommonCfg.PhyMode, pAd->ChannelListNum));
-#ifdef DBG
- for (i = 0; i < pAd->ChannelListNum; i++) {
- DBGPRINT_RAW(RT_DEBUG_TRACE,
- ("BuildChannel # %d :: Pwr0 = %d, Pwr1 =%d, \n ",
- pAd->ChannelList[i].Channel,
- pAd->ChannelList[i].Power,
- pAd->ChannelList[i].Power2));
- }
-#endif
-}
-
-/*
- ==========================================================================
- Description:
- This routine return the first channel number according to the country
- code selection and RF IC selection (signal band or dual band). It is called
- whenever driver need to start a site survey of all supported channels.
- Return:
- ch - the first channel number of current country code setting
-
- IRQL = PASSIVE_LEVEL
-
- ==========================================================================
- */
-u8 FirstChannel(struct rt_rtmp_adapter *pAd)
-{
- return pAd->ChannelList[0].Channel;
-}
-
-/*
- ==========================================================================
- Description:
- This routine returns the next channel number. This routine is called
- during driver need to start a site survey of all supported channels.
- Return:
- next_channel - the next channel number valid in current country code setting.
- Note:
- return 0 if no more next channel
- ==========================================================================
- */
-u8 NextChannel(struct rt_rtmp_adapter *pAd, u8 channel)
-{
- int i;
- u8 next_channel = 0;
-
- for (i = 0; i < (pAd->ChannelListNum - 1); i++)
- if (channel == pAd->ChannelList[i].Channel) {
- next_channel = pAd->ChannelList[i + 1].Channel;
- break;
- }
- return next_channel;
-}
-
-/*
- ==========================================================================
- Description:
- This routine is for Cisco Compatible Extensions 2.X
- Spec31. AP Control of Client Transmit Power
- Return:
- None
- Note:
- Required by Aironet dBm(mW)
- 0dBm(1mW), 1dBm(5mW), 13dBm(20mW), 15dBm(30mW),
- 17dBm(50mw), 20dBm(100mW)
-
- We supported
- 3dBm(Lowest), 6dBm(10%), 9dBm(25%), 12dBm(50%),
- 14dBm(75%), 15dBm(100%)
-
- The client station's actual transmit power shall be within +/- 5dB of
- the minimum value or next lower value.
- ==========================================================================
- */
-void ChangeToCellPowerLimit(struct rt_rtmp_adapter *pAd,
- u8 AironetCellPowerLimit)
-{
- /*valud 0xFF means that hasn't found power limit information */
- /*from the AP's Beacon/Probe response. */
- if (AironetCellPowerLimit == 0xFF)
- return;
-
- if (AironetCellPowerLimit < 6) /*Used Lowest Power Percentage. */
- pAd->CommonCfg.TxPowerPercentage = 6;
- else if (AironetCellPowerLimit < 9)
- pAd->CommonCfg.TxPowerPercentage = 10;
- else if (AironetCellPowerLimit < 12)
- pAd->CommonCfg.TxPowerPercentage = 25;
- else if (AironetCellPowerLimit < 14)
- pAd->CommonCfg.TxPowerPercentage = 50;
- else if (AironetCellPowerLimit < 15)
- pAd->CommonCfg.TxPowerPercentage = 75;
- else
- pAd->CommonCfg.TxPowerPercentage = 100; /*else used maximum */
-
- if (pAd->CommonCfg.TxPowerPercentage > pAd->CommonCfg.TxPowerDefault)
- pAd->CommonCfg.TxPowerPercentage =
- pAd->CommonCfg.TxPowerDefault;
-
-}
-
-char ConvertToRssi(struct rt_rtmp_adapter *pAd, char Rssi, u8 RssiNumber)
-{
- u8 RssiOffset, LNAGain;
-
- /* Rssi equals to zero should be an invalid value */
- if (Rssi == 0)
- return -99;
-
- LNAGain = GET_LNA_GAIN(pAd);
- if (pAd->LatchRfRegs.Channel > 14) {
- if (RssiNumber == 0)
- RssiOffset = pAd->ARssiOffset0;
- else if (RssiNumber == 1)
- RssiOffset = pAd->ARssiOffset1;
- else
- RssiOffset = pAd->ARssiOffset2;
- } else {
- if (RssiNumber == 0)
- RssiOffset = pAd->BGRssiOffset0;
- else if (RssiNumber == 1)
- RssiOffset = pAd->BGRssiOffset1;
- else
- RssiOffset = pAd->BGRssiOffset2;
- }
-
- return (-12 - RssiOffset - LNAGain - Rssi);
-}
-
-/*
- ==========================================================================
- Description:
- Scan next channel
- ==========================================================================
- */
-void ScanNextChannel(struct rt_rtmp_adapter *pAd)
-{
- struct rt_header_802_11 Hdr80211;
- u8 *pOutBuffer = NULL;
- int NStatus;
- unsigned long FrameLen = 0;
- u8 SsidLen = 0, ScanType = pAd->MlmeAux.ScanType, BBPValue = 0;
- u16 Status;
- struct rt_header_802_11 * pHdr80211;
- u32 ScanTimeIn5gChannel = SHORT_CHANNEL_TIME;
-
- {
- if (MONITOR_ON(pAd))
- return;
- }
-
- if (pAd->MlmeAux.Channel == 0) {
- if ((pAd->CommonCfg.BBPCurrentBW == BW_40)
- && (INFRA_ON(pAd)
- || (pAd->OpMode == OPMODE_AP))
- ) {
- AsicSwitchChannel(pAd, pAd->CommonCfg.CentralChannel,
- FALSE);
- AsicLockChannel(pAd, pAd->CommonCfg.CentralChannel);
- RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &BBPValue);
- BBPValue &= (~0x18);
- BBPValue |= 0x10;
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, BBPValue);
- DBGPRINT(RT_DEBUG_TRACE,
- ("SYNC - End of SCAN, restore to 40MHz channel %d, Total BSS[%02d]\n",
- pAd->CommonCfg.CentralChannel,
- pAd->ScanTab.BssNr));
- } else {
- AsicSwitchChannel(pAd, pAd->CommonCfg.Channel, FALSE);
- AsicLockChannel(pAd, pAd->CommonCfg.Channel);
- DBGPRINT(RT_DEBUG_TRACE,
- ("SYNC - End of SCAN, restore to channel %d, Total BSS[%02d]\n",
- pAd->CommonCfg.Channel, pAd->ScanTab.BssNr));
- }
-
- {
- /* */
- /* To prevent data lost. */
- /* Send an NULL data with turned PSM bit on to current associated AP before SCAN progress. */
- /* Now, we need to send an NULL data with turned PSM bit off to AP, when scan progress done */
- /* */
- if (OPSTATUS_TEST_FLAG
- (pAd, fOP_STATUS_MEDIA_STATE_CONNECTED)
- && (INFRA_ON(pAd))) {
- NStatus =
- MlmeAllocateMemory(pAd,
- (void *)& pOutBuffer);
- if (NStatus == NDIS_STATUS_SUCCESS) {
- pHdr80211 = (struct rt_header_802_11 *) pOutBuffer;
- MgtMacHeaderInit(pAd, pHdr80211,
- SUBTYPE_NULL_FUNC, 1,
- pAd->CommonCfg.Bssid,
- pAd->CommonCfg.Bssid);
- pHdr80211->Duration = 0;
- pHdr80211->FC.Type = BTYPE_DATA;
- pHdr80211->FC.PwrMgmt =
- (pAd->StaCfg.Psm == PWR_SAVE);
-
- /* Send using priority queue */
- MiniportMMRequest(pAd, 0, pOutBuffer,
- sizeof
- (struct rt_header_802_11));
- DBGPRINT(RT_DEBUG_TRACE,
- ("MlmeScanReqAction -- Send PSM Data frame\n"));
- MlmeFreeMemory(pAd, pOutBuffer);
- RTMPusecDelay(5000);
- }
- }
-
- pAd->Mlme.SyncMachine.CurrState = SYNC_IDLE;
- Status = MLME_SUCCESS;
- MlmeEnqueue(pAd, MLME_CNTL_STATE_MACHINE, MT2_SCAN_CONF,
- 2, &Status);
- }
-
- RTMP_CLEAR_FLAG(pAd, fRTMP_ADAPTER_BSS_SCAN_IN_PROGRESS);
- }
-#ifdef RTMP_MAC_USB
- else if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST)
- && (pAd->OpMode == OPMODE_STA)) {
- pAd->Mlme.SyncMachine.CurrState = SYNC_IDLE;
- MlmeCntlConfirm(pAd, MT2_SCAN_CONF, MLME_FAIL_NO_RESOURCE);
- }
-#endif /* RTMP_MAC_USB // */
- else {
- {
- /* BBP and RF are not accessible in PS mode, we has to wake them up first */
- if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_DOZE))
- AsicForceWakeup(pAd, TRUE);
-
- /* leave PSM during scanning. otherwise we may lost ProbeRsp & BEACON */
- if (pAd->StaCfg.Psm == PWR_SAVE)
- RTMP_SET_PSM_BIT(pAd, PWR_ACTIVE);
- }
-
- AsicSwitchChannel(pAd, pAd->MlmeAux.Channel, TRUE);
- AsicLockChannel(pAd, pAd->MlmeAux.Channel);
-
- {
- if (pAd->MlmeAux.Channel > 14) {
- if ((pAd->CommonCfg.bIEEE80211H == 1)
- && RadarChannelCheck(pAd,
- pAd->MlmeAux.
- Channel)) {
- ScanType = SCAN_PASSIVE;
- ScanTimeIn5gChannel = MIN_CHANNEL_TIME;
- }
- }
- }
-
- /*Global country domain(ch1-11:active scan, ch12-14 passive scan) */
- if ((pAd->MlmeAux.Channel <= 14) && (pAd->MlmeAux.Channel >= 12)
- && ((pAd->CommonCfg.CountryRegion & 0x7f) ==
- REGION_31_BG_BAND)) {
- ScanType = SCAN_PASSIVE;
- }
- /* We need to shorten active scan time in order for WZC connect issue */
- /* Chnage the channel scan time for CISCO stuff based on its IAPP announcement */
- if (ScanType == FAST_SCAN_ACTIVE)
- RTMPSetTimer(&pAd->MlmeAux.ScanTimer,
- FAST_ACTIVE_SCAN_TIME);
- else /* must be SCAN_PASSIVE or SCAN_ACTIVE */
- {
- if ((pAd->CommonCfg.PhyMode == PHY_11ABG_MIXED)
- || (pAd->CommonCfg.PhyMode == PHY_11ABGN_MIXED)
- || (pAd->CommonCfg.PhyMode == PHY_11AGN_MIXED)
- ) {
- if (pAd->MlmeAux.Channel > 14)
- RTMPSetTimer(&pAd->MlmeAux.ScanTimer,
- ScanTimeIn5gChannel);
- else
- RTMPSetTimer(&pAd->MlmeAux.ScanTimer,
- MIN_CHANNEL_TIME);
- } else
- RTMPSetTimer(&pAd->MlmeAux.ScanTimer,
- MAX_CHANNEL_TIME);
- }
-
- if ((ScanType == SCAN_ACTIVE)
- || (ScanType == FAST_SCAN_ACTIVE)
- ) {
- NStatus = MlmeAllocateMemory(pAd, &pOutBuffer); /*Get an unused nonpaged memory */
- if (NStatus != NDIS_STATUS_SUCCESS) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("SYNC - ScanNextChannel() allocate memory fail\n"));
-
- {
- pAd->Mlme.SyncMachine.CurrState =
- SYNC_IDLE;
- Status = MLME_FAIL_NO_RESOURCE;
- MlmeEnqueue(pAd,
- MLME_CNTL_STATE_MACHINE,
- MT2_SCAN_CONF, 2, &Status);
- }
-
- return;
- }
- /* There is no need to send broadcast probe request if active scan is in effect. */
- if ((ScanType == SCAN_ACTIVE)
- || (ScanType == FAST_SCAN_ACTIVE)
- )
- SsidLen = pAd->MlmeAux.SsidLen;
- else
- SsidLen = 0;
-
- MgtMacHeaderInit(pAd, &Hdr80211, SUBTYPE_PROBE_REQ, 0,
- BROADCAST_ADDR, BROADCAST_ADDR);
- MakeOutgoingFrame(pOutBuffer, &FrameLen,
- sizeof(struct rt_header_802_11), &Hdr80211, 1,
- &SsidIe, 1, &SsidLen, SsidLen,
- pAd->MlmeAux.Ssid, 1, &SupRateIe, 1,
- &pAd->CommonCfg.SupRateLen,
- pAd->CommonCfg.SupRateLen,
- pAd->CommonCfg.SupRate, END_OF_ARGS);
-
- if (pAd->CommonCfg.ExtRateLen) {
- unsigned long Tmp;
- MakeOutgoingFrame(pOutBuffer + FrameLen, &Tmp,
- 1, &ExtRateIe,
- 1, &pAd->CommonCfg.ExtRateLen,
- pAd->CommonCfg.ExtRateLen,
- pAd->CommonCfg.ExtRate,
- END_OF_ARGS);
- FrameLen += Tmp;
- }
-
- if (pAd->CommonCfg.PhyMode >= PHY_11ABGN_MIXED) {
- unsigned long Tmp;
- u8 HtLen;
- u8 BROADCOM[4] = { 0x0, 0x90, 0x4c, 0x33 };
-
- if (pAd->bBroadComHT == TRUE) {
- HtLen =
- pAd->MlmeAux.HtCapabilityLen + 4;
-
- MakeOutgoingFrame(pOutBuffer + FrameLen,
- &Tmp, 1, &WpaIe, 1,
- &HtLen, 4,
- &BROADCOM[0],
- pAd->MlmeAux.
- HtCapabilityLen,
- &pAd->MlmeAux.
- HtCapability,
- END_OF_ARGS);
- } else {
- HtLen = pAd->MlmeAux.HtCapabilityLen;
-
- MakeOutgoingFrame(pOutBuffer + FrameLen,
- &Tmp, 1, &HtCapIe, 1,
- &HtLen, HtLen,
- &pAd->CommonCfg.
- HtCapability,
- END_OF_ARGS);
- }
- FrameLen += Tmp;
- }
-
- MiniportMMRequest(pAd, 0, pOutBuffer, FrameLen);
- MlmeFreeMemory(pAd, pOutBuffer);
- }
- /* For SCAN_CISCO_PASSIVE, do nothing and silently wait for beacon or other probe response */
-
- pAd->Mlme.SyncMachine.CurrState = SCAN_LISTEN;
- }
-}
-
-void MgtProbReqMacHeaderInit(struct rt_rtmp_adapter *pAd,
- struct rt_header_802_11 * pHdr80211,
- u8 SubType,
- u8 ToDs, u8 *pDA, u8 *pBssid)
-{
- NdisZeroMemory(pHdr80211, sizeof(struct rt_header_802_11));
-
- pHdr80211->FC.Type = BTYPE_MGMT;
- pHdr80211->FC.SubType = SubType;
- if (SubType == SUBTYPE_ACK)
- pHdr80211->FC.Type = BTYPE_CNTL;
- pHdr80211->FC.ToDs = ToDs;
- COPY_MAC_ADDR(pHdr80211->Addr1, pDA);
- COPY_MAC_ADDR(pHdr80211->Addr2, pAd->CurrentAddress);
- COPY_MAC_ADDR(pHdr80211->Addr3, pBssid);
-}
diff --git a/drivers/staging/rt2860/common/cmm_tkip.c b/drivers/staging/rt2860/common/cmm_tkip.c
deleted file mode 100644
index 4881ef9..0000000
--- a/drivers/staging/rt2860/common/cmm_tkip.c
+++ /dev/null
@@ -1,833 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- cmm_tkip.c
-
- Abstract:
-
- Revision History:
- Who When What
- -------- ---------- ----------------------------------------------
- Paul Wu 02-25-02 Initial
-*/
-
-#include "../rt_config.h"
-
-/* Rotation functions on 32 bit values */
-#define ROL32( A, n ) \
- ( ((A) << (n)) | ( ((A)>>(32-(n))) & ( (1UL << (n)) - 1 ) ) )
-#define ROR32( A, n ) ROL32( (A), 32-(n) )
-
-u32 Tkip_Sbox_Lower[256] = {
- 0xA5, 0x84, 0x99, 0x8D, 0x0D, 0xBD, 0xB1, 0x54,
- 0x50, 0x03, 0xA9, 0x7D, 0x19, 0x62, 0xE6, 0x9A,
- 0x45, 0x9D, 0x40, 0x87, 0x15, 0xEB, 0xC9, 0x0B,
- 0xEC, 0x67, 0xFD, 0xEA, 0xBF, 0xF7, 0x96, 0x5B,
- 0xC2, 0x1C, 0xAE, 0x6A, 0x5A, 0x41, 0x02, 0x4F,
- 0x5C, 0xF4, 0x34, 0x08, 0x93, 0x73, 0x53, 0x3F,
- 0x0C, 0x52, 0x65, 0x5E, 0x28, 0xA1, 0x0F, 0xB5,
- 0x09, 0x36, 0x9B, 0x3D, 0x26, 0x69, 0xCD, 0x9F,
- 0x1B, 0x9E, 0x74, 0x2E, 0x2D, 0xB2, 0xEE, 0xFB,
- 0xF6, 0x4D, 0x61, 0xCE, 0x7B, 0x3E, 0x71, 0x97,
- 0xF5, 0x68, 0x00, 0x2C, 0x60, 0x1F, 0xC8, 0xED,
- 0xBE, 0x46, 0xD9, 0x4B, 0xDE, 0xD4, 0xE8, 0x4A,
- 0x6B, 0x2A, 0xE5, 0x16, 0xC5, 0xD7, 0x55, 0x94,
- 0xCF, 0x10, 0x06, 0x81, 0xF0, 0x44, 0xBA, 0xE3,
- 0xF3, 0xFE, 0xC0, 0x8A, 0xAD, 0xBC, 0x48, 0x04,
- 0xDF, 0xC1, 0x75, 0x63, 0x30, 0x1A, 0x0E, 0x6D,
- 0x4C, 0x14, 0x35, 0x2F, 0xE1, 0xA2, 0xCC, 0x39,
- 0x57, 0xF2, 0x82, 0x47, 0xAC, 0xE7, 0x2B, 0x95,
- 0xA0, 0x98, 0xD1, 0x7F, 0x66, 0x7E, 0xAB, 0x83,
- 0xCA, 0x29, 0xD3, 0x3C, 0x79, 0xE2, 0x1D, 0x76,
- 0x3B, 0x56, 0x4E, 0x1E, 0xDB, 0x0A, 0x6C, 0xE4,
- 0x5D, 0x6E, 0xEF, 0xA6, 0xA8, 0xA4, 0x37, 0x8B,
- 0x32, 0x43, 0x59, 0xB7, 0x8C, 0x64, 0xD2, 0xE0,
- 0xB4, 0xFA, 0x07, 0x25, 0xAF, 0x8E, 0xE9, 0x18,
- 0xD5, 0x88, 0x6F, 0x72, 0x24, 0xF1, 0xC7, 0x51,
- 0x23, 0x7C, 0x9C, 0x21, 0xDD, 0xDC, 0x86, 0x85,
- 0x90, 0x42, 0xC4, 0xAA, 0xD8, 0x05, 0x01, 0x12,
- 0xA3, 0x5F, 0xF9, 0xD0, 0x91, 0x58, 0x27, 0xB9,
- 0x38, 0x13, 0xB3, 0x33, 0xBB, 0x70, 0x89, 0xA7,
- 0xB6, 0x22, 0x92, 0x20, 0x49, 0xFF, 0x78, 0x7A,
- 0x8F, 0xF8, 0x80, 0x17, 0xDA, 0x31, 0xC6, 0xB8,
- 0xC3, 0xB0, 0x77, 0x11, 0xCB, 0xFC, 0xD6, 0x3A
-};
-
-u32 Tkip_Sbox_Upper[256] = {
- 0xC6, 0xF8, 0xEE, 0xF6, 0xFF, 0xD6, 0xDE, 0x91,
- 0x60, 0x02, 0xCE, 0x56, 0xE7, 0xB5, 0x4D, 0xEC,
- 0x8F, 0x1F, 0x89, 0xFA, 0xEF, 0xB2, 0x8E, 0xFB,
- 0x41, 0xB3, 0x5F, 0x45, 0x23, 0x53, 0xE4, 0x9B,
- 0x75, 0xE1, 0x3D, 0x4C, 0x6C, 0x7E, 0xF5, 0x83,
- 0x68, 0x51, 0xD1, 0xF9, 0xE2, 0xAB, 0x62, 0x2A,
- 0x08, 0x95, 0x46, 0x9D, 0x30, 0x37, 0x0A, 0x2F,
- 0x0E, 0x24, 0x1B, 0xDF, 0xCD, 0x4E, 0x7F, 0xEA,
- 0x12, 0x1D, 0x58, 0x34, 0x36, 0xDC, 0xB4, 0x5B,
- 0xA4, 0x76, 0xB7, 0x7D, 0x52, 0xDD, 0x5E, 0x13,
- 0xA6, 0xB9, 0x00, 0xC1, 0x40, 0xE3, 0x79, 0xB6,
- 0xD4, 0x8D, 0x67, 0x72, 0x94, 0x98, 0xB0, 0x85,
- 0xBB, 0xC5, 0x4F, 0xED, 0x86, 0x9A, 0x66, 0x11,
- 0x8A, 0xE9, 0x04, 0xFE, 0xA0, 0x78, 0x25, 0x4B,
- 0xA2, 0x5D, 0x80, 0x05, 0x3F, 0x21, 0x70, 0xF1,
- 0x63, 0x77, 0xAF, 0x42, 0x20, 0xE5, 0xFD, 0xBF,
- 0x81, 0x18, 0x26, 0xC3, 0xBE, 0x35, 0x88, 0x2E,
- 0x93, 0x55, 0xFC, 0x7A, 0xC8, 0xBA, 0x32, 0xE6,
- 0xC0, 0x19, 0x9E, 0xA3, 0x44, 0x54, 0x3B, 0x0B,
- 0x8C, 0xC7, 0x6B, 0x28, 0xA7, 0xBC, 0x16, 0xAD,
- 0xDB, 0x64, 0x74, 0x14, 0x92, 0x0C, 0x48, 0xB8,
- 0x9F, 0xBD, 0x43, 0xC4, 0x39, 0x31, 0xD3, 0xF2,
- 0xD5, 0x8B, 0x6E, 0xDA, 0x01, 0xB1, 0x9C, 0x49,
- 0xD8, 0xAC, 0xF3, 0xCF, 0xCA, 0xF4, 0x47, 0x10,
- 0x6F, 0xF0, 0x4A, 0x5C, 0x38, 0x57, 0x73, 0x97,
- 0xCB, 0xA1, 0xE8, 0x3E, 0x96, 0x61, 0x0D, 0x0F,
- 0xE0, 0x7C, 0x71, 0xCC, 0x90, 0x06, 0xF7, 0x1C,
- 0xC2, 0x6A, 0xAE, 0x69, 0x17, 0x99, 0x3A, 0x27,
- 0xD9, 0xEB, 0x2B, 0x22, 0xD2, 0xA9, 0x07, 0x33,
- 0x2D, 0x3C, 0x15, 0xC9, 0x87, 0xAA, 0x50, 0xA5,
- 0x03, 0x59, 0x09, 0x1A, 0x65, 0xD7, 0x84, 0xD0,
- 0x82, 0x29, 0x5A, 0x1E, 0x7B, 0xA8, 0x6D, 0x2C
-};
-
-/* */
-/* Expanded IV for TKIP function. */
-/* */
-struct PACKED rt_tkip_iv {
- union PACKED {
- struct PACKED {
- u8 rc0;
- u8 rc1;
- u8 rc2;
-
- union PACKED {
- struct PACKED {
- u8 Rsvd:5;
- u8 ExtIV:1;
- u8 KeyID:2;
- } field;
- u8 Byte;
- } CONTROL;
- } field;
-
- unsigned long word;
- } IV16;
-
- unsigned long IV32;
-};
-
-/*
- ========================================================================
-
- Routine Description:
- Convert from u8[] to unsigned long in a portable way
-
- Arguments:
- pMICKey pointer to MIC Key
-
- Return Value:
- None
-
- Note:
-
- ========================================================================
-*/
-unsigned long RTMPTkipGetUInt32(u8 *pMICKey)
-{
- unsigned long res = 0;
- int i;
-
- for (i = 0; i < 4; i++) {
- res |= (*pMICKey++) << (8 * i);
- }
-
- return res;
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Convert from unsigned long to u8[] in a portable way
-
- Arguments:
- pDst pointer to destination for convert unsigned long to u8[]
- val the value for convert
-
- Return Value:
- None
-
- IRQL = DISPATCH_LEVEL
-
- Note:
-
- ========================================================================
-*/
-void RTMPTkipPutUInt32(IN u8 *pDst, unsigned long val)
-{
- int i;
-
- for (i = 0; i < 4; i++) {
- *pDst++ = (u8)(val & 0xff);
- val >>= 8;
- }
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Set the MIC Key.
-
- Arguments:
- pAd Pointer to our adapter
- pMICKey pointer to MIC Key
-
- Return Value:
- None
-
- IRQL = DISPATCH_LEVEL
-
- Note:
-
- ========================================================================
-*/
-void RTMPTkipSetMICKey(struct rt_tkip_key_info *pTkip, u8 *pMICKey)
-{
- /* Set the key */
- pTkip->K0 = RTMPTkipGetUInt32(pMICKey);
- pTkip->K1 = RTMPTkipGetUInt32(pMICKey + 4);
- /* and reset the message */
- pTkip->L = pTkip->K0;
- pTkip->R = pTkip->K1;
- pTkip->nBytesInM = 0;
- pTkip->M = 0;
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Calculate the MIC Value.
-
- Arguments:
- pAd Pointer to our adapter
- uChar Append this uChar
-
- Return Value:
- None
-
- IRQL = DISPATCH_LEVEL
-
- Note:
-
- ========================================================================
-*/
-void RTMPTkipAppendByte(struct rt_tkip_key_info *pTkip, u8 uChar)
-{
- /* Append the byte to our word-sized buffer */
- pTkip->M |= (uChar << (8 * pTkip->nBytesInM));
- pTkip->nBytesInM++;
- /* Process the word if it is full. */
- if (pTkip->nBytesInM >= 4) {
- pTkip->L ^= pTkip->M;
- pTkip->R ^= ROL32(pTkip->L, 17);
- pTkip->L += pTkip->R;
- pTkip->R ^=
- ((pTkip->L & 0xff00ff00) >> 8) | ((pTkip->
- L & 0x00ff00ff) << 8);
- pTkip->L += pTkip->R;
- pTkip->R ^= ROL32(pTkip->L, 3);
- pTkip->L += pTkip->R;
- pTkip->R ^= ROR32(pTkip->L, 2);
- pTkip->L += pTkip->R;
- /* Clear the buffer */
- pTkip->M = 0;
- pTkip->nBytesInM = 0;
- }
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Calculate the MIC Value.
-
- Arguments:
- pAd Pointer to our adapter
- pSrc Pointer to source data for Calculate MIC Value
- Len Indicate the length of the source data
-
- Return Value:
- None
-
- IRQL = DISPATCH_LEVEL
-
- Note:
-
- ========================================================================
-*/
-void RTMPTkipAppend(struct rt_tkip_key_info *pTkip, u8 *pSrc, u32 nBytes)
-{
- /* This is simple */
- while (nBytes > 0) {
- RTMPTkipAppendByte(pTkip, *pSrc++);
- nBytes--;
- }
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Get the MIC Value.
-
- Arguments:
- pAd Pointer to our adapter
-
- Return Value:
- None
-
- IRQL = DISPATCH_LEVEL
-
- Note:
- the MIC Value is store in pAd->PrivateInfo.MIC
- ========================================================================
-*/
-void RTMPTkipGetMIC(struct rt_tkip_key_info *pTkip)
-{
- /* Append the minimum padding */
- RTMPTkipAppendByte(pTkip, 0x5a);
- RTMPTkipAppendByte(pTkip, 0);
- RTMPTkipAppendByte(pTkip, 0);
- RTMPTkipAppendByte(pTkip, 0);
- RTMPTkipAppendByte(pTkip, 0);
- /* and then zeroes until the length is a multiple of 4 */
- while (pTkip->nBytesInM != 0) {
- RTMPTkipAppendByte(pTkip, 0);
- }
- /* The appendByte function has already computed the result. */
- RTMPTkipPutUInt32(pTkip->MIC, pTkip->L);
- RTMPTkipPutUInt32(pTkip->MIC + 4, pTkip->R);
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Init Tkip function.
-
- Arguments:
- pAd Pointer to our adapter
- pTKey Pointer to the Temporal Key (TK), TK shall be 128bits.
- KeyId TK Key ID
- pTA Pointer to transmitter address
- pMICKey pointer to MIC Key
-
- Return Value:
- None
-
- IRQL = DISPATCH_LEVEL
-
- Note:
-
- ========================================================================
-*/
-void RTMPInitTkipEngine(struct rt_rtmp_adapter *pAd,
- u8 *pKey,
- u8 KeyId,
- u8 *pTA,
- u8 *pMICKey,
- u8 *pTSC, unsigned long *pIV16, unsigned long *pIV32)
-{
- struct rt_tkip_iv tkipIv;
-
- /* Prepare 8 bytes TKIP encapsulation for MPDU */
- NdisZeroMemory(&tkipIv, sizeof(struct rt_tkip_iv));
- tkipIv.IV16.field.rc0 = *(pTSC + 1);
- tkipIv.IV16.field.rc1 = (tkipIv.IV16.field.rc0 | 0x20) & 0x7f;
- tkipIv.IV16.field.rc2 = *pTSC;
- tkipIv.IV16.field.CONTROL.field.ExtIV = 1; /* 0: non-extended IV, 1: an extended IV */
- tkipIv.IV16.field.CONTROL.field.KeyID = KeyId;
-/* tkipIv.IV32 = *(unsigned long *)(pTSC + 2); */
- NdisMoveMemory(&tkipIv.IV32, (pTSC + 2), 4); /* Copy IV */
-
- *pIV16 = tkipIv.IV16.word;
- *pIV32 = tkipIv.IV32;
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Init MIC Value calculation function which include set MIC key &
- calculate first 16 bytes (DA + SA + priority + 0)
-
- Arguments:
- pAd Pointer to our adapter
- pTKey Pointer to the Temporal Key (TK), TK shall be 128bits.
- pDA Pointer to DA address
- pSA Pointer to SA address
- pMICKey pointer to MIC Key
-
- Return Value:
- None
-
- Note:
-
- ========================================================================
-*/
-void RTMPInitMICEngine(struct rt_rtmp_adapter *pAd,
- u8 *pKey,
- u8 *pDA,
- u8 *pSA, u8 UserPriority, u8 *pMICKey)
-{
- unsigned long Priority = UserPriority;
-
- /* Init MIC value calculation */
- RTMPTkipSetMICKey(&pAd->PrivateInfo.Tx, pMICKey);
- /* DA */
- RTMPTkipAppend(&pAd->PrivateInfo.Tx, pDA, MAC_ADDR_LEN);
- /* SA */
- RTMPTkipAppend(&pAd->PrivateInfo.Tx, pSA, MAC_ADDR_LEN);
- /* Priority + 3 bytes of 0 */
- RTMPTkipAppend(&pAd->PrivateInfo.Tx, (u8 *)& Priority, 4);
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Compare MIC value of received MSDU
-
- Arguments:
- pAd Pointer to our adapter
- pSrc Pointer to the received Plain text data
- pDA Pointer to DA address
- pSA Pointer to SA address
- pMICKey pointer to MIC Key
- Len the length of the received plain text data exclude MIC value
-
- Return Value:
- TRUE MIC value matched
- FALSE MIC value mismatched
-
- IRQL = DISPATCH_LEVEL
-
- Note:
-
- ========================================================================
-*/
-BOOLEAN RTMPTkipCompareMICValue(struct rt_rtmp_adapter *pAd,
- u8 *pSrc,
- u8 *pDA,
- u8 *pSA,
- u8 *pMICKey,
- u8 UserPriority, u32 Len)
-{
- u8 OldMic[8];
- unsigned long Priority = UserPriority;
-
- /* Init MIC value calculation */
- RTMPTkipSetMICKey(&pAd->PrivateInfo.Rx, pMICKey);
- /* DA */
- RTMPTkipAppend(&pAd->PrivateInfo.Rx, pDA, MAC_ADDR_LEN);
- /* SA */
- RTMPTkipAppend(&pAd->PrivateInfo.Rx, pSA, MAC_ADDR_LEN);
- /* Priority + 3 bytes of 0 */
- RTMPTkipAppend(&pAd->PrivateInfo.Rx, (u8 *)& Priority, 4);
-
- /* Calculate MIC value from plain text data */
- RTMPTkipAppend(&pAd->PrivateInfo.Rx, pSrc, Len);
-
- /* Get MIC valude from received frame */
- NdisMoveMemory(OldMic, pSrc + Len, 8);
-
- /* Get MIC value from decrypted plain data */
- RTMPTkipGetMIC(&pAd->PrivateInfo.Rx);
-
- /* Move MIC value from MSDU, this steps should move to data path. */
- /* Since the MIC value might cross MPDUs. */
- if (!NdisEqualMemory(pAd->PrivateInfo.Rx.MIC, OldMic, 8)) {
- DBGPRINT_RAW(RT_DEBUG_ERROR, ("RTMPTkipCompareMICValue(): TKIP MIC Error !\n")); /*MIC error. */
-
- return (FALSE);
- }
- return (TRUE);
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Copy frame from waiting queue into relative ring buffer and set
- appropriate ASIC register to kick hardware transmit function
-
- Arguments:
- pAd Pointer to our adapter
- void * Pointer to Ndis Packet for MIC calculation
- pEncap Pointer to LLC encap data
- LenEncap Total encap length, might be 0 which indicates no encap
-
- Return Value:
- None
-
- IRQL = DISPATCH_LEVEL
-
- Note:
-
- ========================================================================
-*/
-void RTMPCalculateMICValue(struct rt_rtmp_adapter *pAd,
- void *pPacket,
- u8 *pEncap,
- struct rt_cipher_key *pKey, u8 apidx)
-{
- struct rt_packet_info PacketInfo;
- u8 *pSrcBufVA;
- u32 SrcBufLen;
- u8 *pSrc;
- u8 UserPriority;
- u8 vlan_offset = 0;
-
- RTMP_QueryPacketInfo(pPacket, &PacketInfo, &pSrcBufVA, &SrcBufLen);
-
- UserPriority = RTMP_GET_PACKET_UP(pPacket);
- pSrc = pSrcBufVA;
-
- /* determine if this is a vlan packet */
- if (((*(pSrc + 12) << 8) + *(pSrc + 13)) == 0x8100)
- vlan_offset = 4;
-
- {
- RTMPInitMICEngine(pAd,
- pKey->Key,
- pSrc, pSrc + 6, UserPriority, pKey->TxMic);
- }
-
- if (pEncap != NULL) {
- /* LLC encapsulation */
- RTMPTkipAppend(&pAd->PrivateInfo.Tx, pEncap, 6);
- /* Protocol Type */
- RTMPTkipAppend(&pAd->PrivateInfo.Tx, pSrc + 12 + vlan_offset,
- 2);
- }
- SrcBufLen -= (14 + vlan_offset);
- pSrc += (14 + vlan_offset);
- do {
- if (SrcBufLen > 0) {
- RTMPTkipAppend(&pAd->PrivateInfo.Tx, pSrc, SrcBufLen);
- }
-
- break; /* No need handle next packet */
-
- } while (TRUE); /* End of copying payload */
-
- /* Compute the final MIC Value */
- RTMPTkipGetMIC(&pAd->PrivateInfo.Tx);
-}
-
-/************************************************************/
-/* tkip_sbox() */
-/* Returns a 16 bit value from a 64K entry table. The Table */
-/* is synthesized from two 256 entry byte wide tables. */
-/************************************************************/
-
-u32 tkip_sbox(u32 index)
-{
- u32 index_low;
- u32 index_high;
- u32 left, right;
-
- index_low = (index % 256);
- index_high = ((index >> 8) % 256);
-
- left = Tkip_Sbox_Lower[index_low] + (Tkip_Sbox_Upper[index_low] * 256);
- right =
- Tkip_Sbox_Upper[index_high] + (Tkip_Sbox_Lower[index_high] * 256);
-
- return (left ^ right);
-}
-
-u32 rotr1(u32 a)
-{
- unsigned int b;
-
- if ((a & 0x01) == 0x01) {
- b = (a >> 1) | 0x8000;
- } else {
- b = (a >> 1) & 0x7fff;
- }
- b = b % 65536;
- return b;
-}
-
-void RTMPTkipMixKey(u8 * key, u8 * ta, unsigned long pnl, /* Least significant 16 bits of PN */
- unsigned long pnh, /* Most significant 32 bits of PN */
- u8 * rc4key, u32 * p1k)
-{
-
- u32 tsc0;
- u32 tsc1;
- u32 tsc2;
-
- u32 ppk0;
- u32 ppk1;
- u32 ppk2;
- u32 ppk3;
- u32 ppk4;
- u32 ppk5;
-
- int i;
- int j;
-
- tsc0 = (unsigned int)((pnh >> 16) % 65536); /* msb */
- tsc1 = (unsigned int)(pnh % 65536);
- tsc2 = (unsigned int)(pnl % 65536); /* lsb */
-
- /* Phase 1, step 1 */
- p1k[0] = tsc1;
- p1k[1] = tsc0;
- p1k[2] = (u32)(ta[0] + (ta[1] * 256));
- p1k[3] = (u32)(ta[2] + (ta[3] * 256));
- p1k[4] = (u32)(ta[4] + (ta[5] * 256));
-
- /* Phase 1, step 2 */
- for (i = 0; i < 8; i++) {
- j = 2 * (i & 1);
- p1k[0] =
- (p1k[0] +
- tkip_sbox((p1k[4] ^ ((256 * key[1 + j]) + key[j])) %
- 65536)) % 65536;
- p1k[1] =
- (p1k[1] +
- tkip_sbox((p1k[0] ^ ((256 * key[5 + j]) + key[4 + j])) %
- 65536)) % 65536;
- p1k[2] =
- (p1k[2] +
- tkip_sbox((p1k[1] ^ ((256 * key[9 + j]) + key[8 + j])) %
- 65536)) % 65536;
- p1k[3] =
- (p1k[3] +
- tkip_sbox((p1k[2] ^ ((256 * key[13 + j]) + key[12 + j])) %
- 65536)) % 65536;
- p1k[4] =
- (p1k[4] +
- tkip_sbox((p1k[3] ^ (((256 * key[1 + j]) + key[j]))) %
- 65536)) % 65536;
- p1k[4] = (p1k[4] + i) % 65536;
- }
-
- /* Phase 2, Step 1 */
- ppk0 = p1k[0];
- ppk1 = p1k[1];
- ppk2 = p1k[2];
- ppk3 = p1k[3];
- ppk4 = p1k[4];
- ppk5 = (p1k[4] + tsc2) % 65536;
-
- /* Phase2, Step 2 */
- ppk0 = ppk0 + tkip_sbox((ppk5 ^ ((256 * key[1]) + key[0])) % 65536);
- ppk1 = ppk1 + tkip_sbox((ppk0 ^ ((256 * key[3]) + key[2])) % 65536);
- ppk2 = ppk2 + tkip_sbox((ppk1 ^ ((256 * key[5]) + key[4])) % 65536);
- ppk3 = ppk3 + tkip_sbox((ppk2 ^ ((256 * key[7]) + key[6])) % 65536);
- ppk4 = ppk4 + tkip_sbox((ppk3 ^ ((256 * key[9]) + key[8])) % 65536);
- ppk5 = ppk5 + tkip_sbox((ppk4 ^ ((256 * key[11]) + key[10])) % 65536);
-
- ppk0 = ppk0 + rotr1(ppk5 ^ ((256 * key[13]) + key[12]));
- ppk1 = ppk1 + rotr1(ppk0 ^ ((256 * key[15]) + key[14]));
- ppk2 = ppk2 + rotr1(ppk1);
- ppk3 = ppk3 + rotr1(ppk2);
- ppk4 = ppk4 + rotr1(ppk3);
- ppk5 = ppk5 + rotr1(ppk4);
-
- /* Phase 2, Step 3 */
- /* Phase 2, Step 3 */
-
- tsc0 = (unsigned int)((pnh >> 16) % 65536); /* msb */
- tsc1 = (unsigned int)(pnh % 65536);
- tsc2 = (unsigned int)(pnl % 65536); /* lsb */
-
- rc4key[0] = (tsc2 >> 8) % 256;
- rc4key[1] = (((tsc2 >> 8) % 256) | 0x20) & 0x7f;
- rc4key[2] = tsc2 % 256;
- rc4key[3] = ((ppk5 ^ ((256 * key[1]) + key[0])) >> 1) % 256;
-
- rc4key[4] = ppk0 % 256;
- rc4key[5] = (ppk0 >> 8) % 256;
-
- rc4key[6] = ppk1 % 256;
- rc4key[7] = (ppk1 >> 8) % 256;
-
- rc4key[8] = ppk2 % 256;
- rc4key[9] = (ppk2 >> 8) % 256;
-
- rc4key[10] = ppk3 % 256;
- rc4key[11] = (ppk3 >> 8) % 256;
-
- rc4key[12] = ppk4 % 256;
- rc4key[13] = (ppk4 >> 8) % 256;
-
- rc4key[14] = ppk5 % 256;
- rc4key[15] = (ppk5 >> 8) % 256;
-}
-
-/* */
-/* TRUE: Success! */
-/* FALSE: Decrypt Error! */
-/* */
-BOOLEAN RTMPSoftDecryptTKIP(struct rt_rtmp_adapter *pAd,
- u8 *pData,
- unsigned long DataByteCnt,
- u8 UserPriority, struct rt_cipher_key *pWpaKey)
-{
- u8 KeyID;
- u32 HeaderLen;
- u8 fc0;
- u8 fc1;
- u16 fc;
- u32 frame_type;
- u32 frame_subtype;
- u32 from_ds;
- u32 to_ds;
- int a4_exists;
- int qc_exists;
- u16 duration;
- u16 seq_control;
- u16 qos_control;
- u8 TA[MAC_ADDR_LEN];
- u8 DA[MAC_ADDR_LEN];
- u8 SA[MAC_ADDR_LEN];
- u8 RC4Key[16];
- u32 p1k[5]; /*for mix_key; */
- unsigned long pnl; /* Least significant 16 bits of PN */
- unsigned long pnh; /* Most significant 32 bits of PN */
- u32 num_blocks;
- u32 payload_remainder;
- struct rt_arcfourcontext ArcFourContext;
- u32 crc32 = 0;
- u32 trailfcs = 0;
- u8 MIC[8];
- u8 TrailMIC[8];
-
- fc0 = *pData;
- fc1 = *(pData + 1);
-
- fc = *((u16 *)pData);
-
- frame_type = ((fc0 >> 2) & 0x03);
- frame_subtype = ((fc0 >> 4) & 0x0f);
-
- from_ds = (fc1 & 0x2) >> 1;
- to_ds = (fc1 & 0x1);
-
- a4_exists = (from_ds & to_ds);
- qc_exists = ((frame_subtype == 0x08) || /* Assumed QoS subtypes */
- (frame_subtype == 0x09) || /* Likely to change. */
- (frame_subtype == 0x0a) || (frame_subtype == 0x0b)
- );
-
- HeaderLen = 24;
- if (a4_exists)
- HeaderLen += 6;
-
- KeyID = *((u8 *)(pData + HeaderLen + 3));
- KeyID = KeyID >> 6;
-
- if (pWpaKey[KeyID].KeyLen == 0) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("RTMPSoftDecryptTKIP failed!(KeyID[%d] Length can not be 0)\n",
- KeyID));
- return FALSE;
- }
-
- duration = *((u16 *)(pData + 2));
-
- seq_control = *((u16 *)(pData + 22));
-
- if (qc_exists) {
- if (a4_exists) {
- qos_control = *((u16 *)(pData + 30));
- } else {
- qos_control = *((u16 *)(pData + 24));
- }
- }
-
- if (to_ds == 0 && from_ds == 1) {
- NdisMoveMemory(DA, pData + 4, MAC_ADDR_LEN);
- NdisMoveMemory(SA, pData + 16, MAC_ADDR_LEN);
- NdisMoveMemory(TA, pData + 10, MAC_ADDR_LEN); /*BSSID */
- } else if (to_ds == 0 && from_ds == 0) {
- NdisMoveMemory(TA, pData + 10, MAC_ADDR_LEN);
- NdisMoveMemory(DA, pData + 4, MAC_ADDR_LEN);
- NdisMoveMemory(SA, pData + 10, MAC_ADDR_LEN);
- } else if (to_ds == 1 && from_ds == 0) {
- NdisMoveMemory(SA, pData + 10, MAC_ADDR_LEN);
- NdisMoveMemory(TA, pData + 10, MAC_ADDR_LEN);
- NdisMoveMemory(DA, pData + 16, MAC_ADDR_LEN);
- } else if (to_ds == 1 && from_ds == 1) {
- NdisMoveMemory(TA, pData + 10, MAC_ADDR_LEN);
- NdisMoveMemory(DA, pData + 16, MAC_ADDR_LEN);
- NdisMoveMemory(SA, pData + 22, MAC_ADDR_LEN);
- }
-
- num_blocks = (DataByteCnt - 16) / 16;
- payload_remainder = (DataByteCnt - 16) % 16;
-
- pnl = (*(pData + HeaderLen)) * 256 + *(pData + HeaderLen + 2);
- pnh = *((unsigned long *)(pData + HeaderLen + 4));
- pnh = cpu2le32(pnh);
- RTMPTkipMixKey(pWpaKey[KeyID].Key, TA, pnl, pnh, RC4Key, p1k);
-
- ARCFOUR_INIT(&ArcFourContext, RC4Key, 16);
-
- ARCFOUR_DECRYPT(&ArcFourContext, pData + HeaderLen,
- pData + HeaderLen + 8, DataByteCnt - HeaderLen - 8);
- NdisMoveMemory(&trailfcs, pData + DataByteCnt - 8 - 4, 4);
- crc32 = RTMP_CALC_FCS32(PPPINITFCS32, pData + HeaderLen, DataByteCnt - HeaderLen - 8 - 4); /*Skip IV+EIV 8 bytes & Skip last 4 bytes(FCS). */
- crc32 ^= 0xffffffff; /* complement */
-
- if (crc32 != cpu2le32(trailfcs)) {
- DBGPRINT(RT_DEBUG_TRACE, ("RTMPSoftDecryptTKIP, WEP Data ICV Error !\n")); /*ICV error. */
-
- return (FALSE);
- }
-
- NdisMoveMemory(TrailMIC, pData + DataByteCnt - 8 - 8 - 4, 8);
- RTMPInitMICEngine(pAd, pWpaKey[KeyID].Key, DA, SA, UserPriority,
- pWpaKey[KeyID].RxMic);
- RTMPTkipAppend(&pAd->PrivateInfo.Tx, pData + HeaderLen,
- DataByteCnt - HeaderLen - 8 - 12);
- RTMPTkipGetMIC(&pAd->PrivateInfo.Tx);
- NdisMoveMemory(MIC, pAd->PrivateInfo.Tx.MIC, 8);
-
- if (!NdisEqualMemory(MIC, TrailMIC, 8)) {
- DBGPRINT(RT_DEBUG_ERROR, ("RTMPSoftDecryptTKIP, WEP Data MIC Error !\n")); /*MIC error. */
- /*RTMPReportMicError(pAd, &pWpaKey[KeyID]); // marked by AlbertY @ 20060630 */
- return (FALSE);
- }
- /*DBGPRINT(RT_DEBUG_TRACE, "RTMPSoftDecryptTKIP Decript done!\n"); */
- return TRUE;
-}
diff --git a/drivers/staging/rt2860/common/cmm_wep.c b/drivers/staging/rt2860/common/cmm_wep.c
deleted file mode 100644
index 76f880c..0000000
--- a/drivers/staging/rt2860/common/cmm_wep.c
+++ /dev/null
@@ -1,473 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- rtmp_wep.c
-
- Abstract:
-
- Revision History:
- Who When What
- -------- ---------- ----------------------------------------------
- Paul Wu 10-28-02 Initial
-*/
-
-#include "../rt_config.h"
-
-u32 FCSTAB_32[256] = {
- 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba,
- 0x076dc419, 0x706af48f, 0xe963a535, 0x9e6495a3,
- 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988,
- 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91,
- 0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de,
- 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7,
- 0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec,
- 0x14015c4f, 0x63066cd9, 0xfa0f3d63, 0x8d080df5,
- 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172,
- 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b,
- 0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940,
- 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59,
- 0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116,
- 0x21b4f4b5, 0x56b3c423, 0xcfba9599, 0xb8bda50f,
- 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924,
- 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d,
- 0x76dc4190, 0x01db7106, 0x98d220bc, 0xefd5102a,
- 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433,
- 0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818,
- 0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01,
- 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e,
- 0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457,
- 0x65b0d9c6, 0x12b7e950, 0x8bbeb8ea, 0xfcb9887c,
- 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65,
- 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2,
- 0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb,
- 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0,
- 0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9,
- 0x5005713c, 0x270241aa, 0xbe0b1010, 0xc90c2086,
- 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f,
- 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4,
- 0x59b33d17, 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad,
- 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a,
- 0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683,
- 0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8,
- 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1,
- 0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe,
- 0xf762575d, 0x806567cb, 0x196c3671, 0x6e6b06e7,
- 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc,
- 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5,
- 0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252,
- 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b,
- 0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60,
- 0xdf60efc3, 0xa867df55, 0x316e8eef, 0x4669be79,
- 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236,
- 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f,
- 0xc5ba3bbe, 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04,
- 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d,
- 0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a,
- 0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713,
- 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38,
- 0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21,
- 0x86d3d2d4, 0xf1d4e242, 0x68ddb3f8, 0x1fda836e,
- 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777,
- 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c,
- 0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45,
- 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2,
- 0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db,
- 0xaed16a4a, 0xd9d65adc, 0x40df0b66, 0x37d83bf0,
- 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9,
- 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6,
- 0xbad03605, 0xcdd70693, 0x54de5729, 0x23d967bf,
- 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94,
- 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d
-};
-
-/*
-u8 WEPKEY[] = {
- //IV
- 0x00, 0x11, 0x22,
- //WEP KEY
- 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88, 0x99, 0xAA, 0xBB, 0xCC
- };
- */
-
-/*
- ========================================================================
-
- Routine Description:
- Init WEP function.
-
- Arguments:
- pAd Pointer to our adapter
- pKey Pointer to the WEP KEY
- KeyId WEP Key ID
- KeyLen the length of WEP KEY
- pDest Pointer to the destination which Encryption data will store in.
-
- Return Value:
- None
-
- IRQL = DISPATCH_LEVEL
-
- Note:
-
- ========================================================================
-*/
-void RTMPInitWepEngine(struct rt_rtmp_adapter *pAd,
- u8 *pKey,
- u8 KeyId, u8 KeyLen, IN u8 *pDest)
-{
- u32 i;
- u8 WEPKEY[] = {
- /*IV */
- 0x00, 0x11, 0x22,
- /*WEP KEY */
- 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88, 0x99,
- 0xAA, 0xBB, 0xCC
- };
-
- pAd->PrivateInfo.FCSCRC32 = PPPINITFCS32; /*Init crc32. */
-
- {
- NdisMoveMemory(WEPKEY + 3, pKey, KeyLen);
-
- for (i = 0; i < 3; i++)
- WEPKEY[i] = RandomByte(pAd); /*Call mlme RandomByte() function. */
- ARCFOUR_INIT(&pAd->PrivateInfo.WEPCONTEXT, WEPKEY, KeyLen + 3); /*INIT SBOX, KEYLEN+3(IV) */
-
- NdisMoveMemory(pDest, WEPKEY, 3); /*Append Init Vector */
- }
- *(pDest + 3) = (KeyId << 6); /*Append KEYID */
-
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Encrypt transimitted data
-
- Arguments:
- pAd Pointer to our adapter
- pSrc Pointer to the transimitted source data that will be encrypt
- pDest Pointer to the destination where entryption data will be store in.
- Len Indicate the length of the source data
-
- Return Value:
- None
-
- IRQL = DISPATCH_LEVEL
-
- Note:
-
- ========================================================================
-*/
-void RTMPEncryptData(struct rt_rtmp_adapter *pAd,
- u8 *pSrc, u8 *pDest, u32 Len)
-{
- pAd->PrivateInfo.FCSCRC32 =
- RTMP_CALC_FCS32(pAd->PrivateInfo.FCSCRC32, pSrc, Len);
- ARCFOUR_ENCRYPT(&pAd->PrivateInfo.WEPCONTEXT, pDest, pSrc, Len);
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Decrypt received WEP data
-
- Arguments:
- pAdapter Pointer to our adapter
- pSrc Pointer to the received data
- Len the length of the received data
-
- Return Value:
- TRUE Decrypt WEP data success
- FALSE Decrypt WEP data failed
-
- Note:
-
- ========================================================================
-*/
-BOOLEAN RTMPSoftDecryptWEP(struct rt_rtmp_adapter *pAd,
- u8 *pData,
- unsigned long DataByteCnt, struct rt_cipher_key *pGroupKey)
-{
- u32 trailfcs;
- u32 crc32;
- u8 KeyIdx;
- u8 WEPKEY[] = {
- /*IV */
- 0x00, 0x11, 0x22,
- /*WEP KEY */
- 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, 0x88, 0x99,
- 0xAA, 0xBB, 0xCC
- };
- u8 *pPayload = (u8 *) pData + LENGTH_802_11;
- unsigned long payload_len = DataByteCnt - LENGTH_802_11;
-
- NdisMoveMemory(WEPKEY, pPayload, 3); /*Get WEP IV */
-
- KeyIdx = (*(pPayload + 3) & 0xc0) >> 6;
- if (pGroupKey[KeyIdx].KeyLen == 0)
- return (FALSE);
-
- NdisMoveMemory(WEPKEY + 3, pGroupKey[KeyIdx].Key,
- pGroupKey[KeyIdx].KeyLen);
- ARCFOUR_INIT(&pAd->PrivateInfo.WEPCONTEXT, WEPKEY,
- pGroupKey[KeyIdx].KeyLen + 3);
- ARCFOUR_DECRYPT(&pAd->PrivateInfo.WEPCONTEXT, pPayload, pPayload + 4,
- payload_len - 4);
- NdisMoveMemory(&trailfcs, pPayload + payload_len - 8, 4);
- crc32 = RTMP_CALC_FCS32(PPPINITFCS32, pPayload, payload_len - 8); /*Skip last 4 bytes(FCS). */
- crc32 ^= 0xffffffff; /* complement */
-
- if (crc32 != cpu2le32(trailfcs)) {
- DBGPRINT(RT_DEBUG_TRACE, ("WEP Data CRC Error!\n")); /*CRC error. */
- return (FALSE);
- }
- return (TRUE);
-}
-
-/*
- ========================================================================
-
- Routine Description:
- The Stream Cipher Encryption Algorithm "struct rt_arcfour" initialize
-
- Arguments:
- Ctx Pointer to struct rt_arcfour CONTEXT (SBOX)
- pKey Pointer to the WEP KEY
- KeyLen Indicate the length fo the WEP KEY
-
- Return Value:
- None
-
- IRQL = DISPATCH_LEVEL
-
- Note:
-
- ========================================================================
-*/
-void ARCFOUR_INIT(struct rt_arcfourcontext *Ctx, u8 *pKey, u32 KeyLen)
-{
- u8 t, u;
- u32 keyindex;
- u32 stateindex;
- u8 *state;
- u32 counter;
-
- state = Ctx->STATE;
- Ctx->X = 0;
- Ctx->Y = 0;
- for (counter = 0; counter < 256; counter++)
- state[counter] = (u8)counter;
- keyindex = 0;
- stateindex = 0;
- for (counter = 0; counter < 256; counter++) {
- t = state[counter];
- stateindex = (stateindex + pKey[keyindex] + t) & 0xff;
- u = state[stateindex];
- state[stateindex] = t;
- state[counter] = u;
- if (++keyindex >= KeyLen)
- keyindex = 0;
- }
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Get bytes from struct rt_arcfour CONTEXT (S-BOX)
-
- Arguments:
- Ctx Pointer to struct rt_arcfour CONTEXT (SBOX)
-
- Return Value:
- u8 - the value of the struct rt_arcfour CONTEXT (S-BOX)
-
- Note:
-
- ========================================================================
-*/
-u8 ARCFOUR_BYTE(struct rt_arcfourcontext *Ctx)
-{
- u32 x;
- u32 y;
- u8 sx, sy;
- u8 *state;
-
- state = Ctx->STATE;
- x = (Ctx->X + 1) & 0xff;
- sx = state[x];
- y = (sx + Ctx->Y) & 0xff;
- sy = state[y];
- Ctx->X = x;
- Ctx->Y = y;
- state[y] = sx;
- state[x] = sy;
-
- return (state[(sx + sy) & 0xff]);
-
-}
-
-/*
- ========================================================================
-
- Routine Description:
- The Stream Cipher Decryption Algorithm
-
- Arguments:
- Ctx Pointer to struct rt_arcfour CONTEXT (SBOX)
- pDest Pointer to the Destination
- pSrc Pointer to the Source data
- Len Indicate the length of the Source data
-
- Return Value:
- None
-
- Note:
-
- ========================================================================
-*/
-void ARCFOUR_DECRYPT(struct rt_arcfourcontext *Ctx,
- u8 *pDest, u8 *pSrc, u32 Len)
-{
- u32 i;
-
- for (i = 0; i < Len; i++)
- pDest[i] = pSrc[i] ^ ARCFOUR_BYTE(Ctx);
-}
-
-/*
- ========================================================================
-
- Routine Description:
- The Stream Cipher Encryption Algorithm
-
- Arguments:
- Ctx Pointer to struct rt_arcfour CONTEXT (SBOX)
- pDest Pointer to the Destination
- pSrc Pointer to the Source data
- Len Indicate the length of the Source dta
-
- Return Value:
- None
-
- IRQL = DISPATCH_LEVEL
-
- Note:
-
- ========================================================================
-*/
-void ARCFOUR_ENCRYPT(struct rt_arcfourcontext *Ctx,
- u8 *pDest, u8 *pSrc, u32 Len)
-{
- u32 i;
-
- for (i = 0; i < Len; i++)
- pDest[i] = pSrc[i] ^ ARCFOUR_BYTE(Ctx);
-}
-
-/*
- ========================================================================
-
- Routine Description:
- The Stream Cipher Encryption Algorithm which conform to the special requirement to encrypt GTK.
-
- Arguments:
- Ctx Pointer to struct rt_arcfour CONTEXT (SBOX)
- pDest Pointer to the Destination
- pSrc Pointer to the Source data
- Len Indicate the length of the Source dta
-
- ========================================================================
-*/
-
-void WPAARCFOUR_ENCRYPT(struct rt_arcfourcontext *Ctx,
- u8 *pDest, u8 *pSrc, u32 Len)
-{
- u32 i;
- /*discard first 256 bytes */
- for (i = 0; i < 256; i++)
- ARCFOUR_BYTE(Ctx);
-
- for (i = 0; i < Len; i++)
- pDest[i] = pSrc[i] ^ ARCFOUR_BYTE(Ctx);
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Calculate a new FCS given the current FCS and the new data.
-
- Arguments:
- Fcs the original FCS value
- Cp pointer to the data which will be calculate the FCS
- Len the length of the data
-
- Return Value:
- u32 - FCS 32 bits
-
- IRQL = DISPATCH_LEVEL
-
- Note:
-
- ========================================================================
-*/
-u32 RTMP_CALC_FCS32(u32 Fcs, u8 *Cp, int Len)
-{
- while (Len--)
- Fcs = (((Fcs) >> 8) ^ FCSTAB_32[((Fcs) ^ (*Cp++)) & 0xff]);
-
- return (Fcs);
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Get last FCS and encrypt it to the destination
-
- Arguments:
- pDest Pointer to the Destination
-
- Return Value:
- None
-
- Note:
-
- ========================================================================
-*/
-void RTMPSetICV(struct rt_rtmp_adapter *pAd, u8 *pDest)
-{
- pAd->PrivateInfo.FCSCRC32 ^= 0xffffffff; /* complement */
- pAd->PrivateInfo.FCSCRC32 = cpu2le32(pAd->PrivateInfo.FCSCRC32);
-
- ARCFOUR_ENCRYPT(&pAd->PrivateInfo.WEPCONTEXT, pDest,
- (u8 *)& pAd->PrivateInfo.FCSCRC32, 4);
-}
diff --git a/drivers/staging/rt2860/common/cmm_wpa.c b/drivers/staging/rt2860/common/cmm_wpa.c
deleted file mode 100644
index 616ebec..0000000
--- a/drivers/staging/rt2860/common/cmm_wpa.c
+++ /dev/null
@@ -1,3010 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- wpa.c
-
- Abstract:
-
- Revision History:
- Who When What
- -------- ---------- ----------------------------------------------
- Jan Lee 03-07-22 Initial
- Paul Lin 03-11-28 Modify for supplicant
-*/
-#include "../rt_config.h"
-/* WPA OUI */
-u8 OUI_WPA_NONE_AKM[4] = { 0x00, 0x50, 0xF2, 0x00 };
-u8 OUI_WPA_VERSION[4] = { 0x00, 0x50, 0xF2, 0x01 };
-u8 OUI_WPA_WEP40[4] = { 0x00, 0x50, 0xF2, 0x01 };
-u8 OUI_WPA_TKIP[4] = { 0x00, 0x50, 0xF2, 0x02 };
-u8 OUI_WPA_CCMP[4] = { 0x00, 0x50, 0xF2, 0x04 };
-u8 OUI_WPA_WEP104[4] = { 0x00, 0x50, 0xF2, 0x05 };
-u8 OUI_WPA_8021X_AKM[4] = { 0x00, 0x50, 0xF2, 0x01 };
-u8 OUI_WPA_PSK_AKM[4] = { 0x00, 0x50, 0xF2, 0x02 };
-
-/* WPA2 OUI */
-u8 OUI_WPA2_WEP40[4] = { 0x00, 0x0F, 0xAC, 0x01 };
-u8 OUI_WPA2_TKIP[4] = { 0x00, 0x0F, 0xAC, 0x02 };
-u8 OUI_WPA2_CCMP[4] = { 0x00, 0x0F, 0xAC, 0x04 };
-u8 OUI_WPA2_8021X_AKM[4] = { 0x00, 0x0F, 0xAC, 0x01 };
-u8 OUI_WPA2_PSK_AKM[4] = { 0x00, 0x0F, 0xAC, 0x02 };
-u8 OUI_WPA2_WEP104[4] = { 0x00, 0x0F, 0xAC, 0x05 };
-
-static void ConstructEapolKeyData(struct rt_mac_table_entry *pEntry,
- u8 GroupKeyWepStatus,
- u8 keyDescVer,
- u8 MsgType,
- u8 DefaultKeyIdx,
- u8 * GTK,
- u8 * RSNIE,
- u8 RSNIE_LEN, struct rt_eapol_packet * pMsg);
-
-static void CalculateMIC(u8 KeyDescVer,
- u8 * PTK, struct rt_eapol_packet * pMsg);
-
-static void WpaEAPPacketAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem);
-
-static void WpaEAPOLASFAlertAction(struct rt_rtmp_adapter *pAd,
- struct rt_mlme_queue_elem *Elem);
-
-static void WpaEAPOLLogoffAction(struct rt_rtmp_adapter *pAd,
- struct rt_mlme_queue_elem *Elem);
-
-static void WpaEAPOLStartAction(struct rt_rtmp_adapter *pAd,
- struct rt_mlme_queue_elem *Elem);
-
-static void WpaEAPOLKeyAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem);
-
-/*
- ==========================================================================
- Description:
- association state machine init, including state transition and timer init
- Parameters:
- S - pointer to the association state machine
- ==========================================================================
- */
-void WpaStateMachineInit(struct rt_rtmp_adapter *pAd,
- struct rt_state_machine *S, OUT STATE_MACHINE_FUNC Trans[])
-{
- StateMachineInit(S, (STATE_MACHINE_FUNC *) Trans, MAX_WPA_PTK_STATE,
- MAX_WPA_MSG, (STATE_MACHINE_FUNC) Drop, WPA_PTK,
- WPA_MACHINE_BASE);
-
- StateMachineSetAction(S, WPA_PTK, MT2_EAPPacket,
- (STATE_MACHINE_FUNC) WpaEAPPacketAction);
- StateMachineSetAction(S, WPA_PTK, MT2_EAPOLStart,
- (STATE_MACHINE_FUNC) WpaEAPOLStartAction);
- StateMachineSetAction(S, WPA_PTK, MT2_EAPOLLogoff,
- (STATE_MACHINE_FUNC) WpaEAPOLLogoffAction);
- StateMachineSetAction(S, WPA_PTK, MT2_EAPOLKey,
- (STATE_MACHINE_FUNC) WpaEAPOLKeyAction);
- StateMachineSetAction(S, WPA_PTK, MT2_EAPOLASFAlert,
- (STATE_MACHINE_FUNC) WpaEAPOLASFAlertAction);
-}
-
-/*
- ==========================================================================
- Description:
- this is state machine function.
- When receiving EAP packets which is for 802.1x authentication use.
- Not use in PSK case
- Return:
- ==========================================================================
-*/
-void WpaEAPPacketAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
-}
-
-void WpaEAPOLASFAlertAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
-}
-
-void WpaEAPOLLogoffAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
-}
-
-/*
- ==========================================================================
- Description:
- Start 4-way HS when rcv EAPOL_START which may create by our driver in assoc.c
- Return:
- ==========================================================================
-*/
-void WpaEAPOLStartAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
- struct rt_mac_table_entry *pEntry;
- struct rt_header_802_11 * pHeader;
-
- DBGPRINT(RT_DEBUG_TRACE, ("WpaEAPOLStartAction ===> \n"));
-
- pHeader = (struct rt_header_802_11 *) Elem->Msg;
-
- /*For normaol PSK, we enqueue an EAPOL-Start command to trigger the process. */
- if (Elem->MsgLen == 6)
- pEntry = MacTableLookup(pAd, Elem->Msg);
- else {
- pEntry = MacTableLookup(pAd, pHeader->Addr2);
- }
-
- if (pEntry) {
- DBGPRINT(RT_DEBUG_TRACE,
- (" PortSecured(%d), WpaState(%d), AuthMode(%d), PMKID_CacheIdx(%d) \n",
- pEntry->PortSecured, pEntry->WpaState,
- pEntry->AuthMode, pEntry->PMKID_CacheIdx));
-
- if ((pEntry->PortSecured == WPA_802_1X_PORT_NOT_SECURED)
- && (pEntry->WpaState < AS_PTKSTART)
- && ((pEntry->AuthMode == Ndis802_11AuthModeWPAPSK)
- || (pEntry->AuthMode == Ndis802_11AuthModeWPA2PSK)
- || ((pEntry->AuthMode == Ndis802_11AuthModeWPA2)
- && (pEntry->PMKID_CacheIdx != ENTRY_NOT_FOUND)))) {
- pEntry->PrivacyFilter = Ndis802_11PrivFilter8021xWEP;
- pEntry->WpaState = AS_INITPSK;
- pEntry->PortSecured = WPA_802_1X_PORT_NOT_SECURED;
- NdisZeroMemory(pEntry->R_Counter,
- sizeof(pEntry->R_Counter));
- pEntry->ReTryCounter = PEER_MSG1_RETRY_TIMER_CTR;
-
- WPAStart4WayHS(pAd, pEntry, PEER_MSG1_RETRY_EXEC_INTV);
- }
- }
-}
-
-/*
- ==========================================================================
- Description:
- This is state machine function.
- When receiving EAPOL packets which is for 802.1x key management.
- Use both in WPA, and WPAPSK case.
- In this function, further dispatch to different functions according to the received packet. 3 categories are :
- 1. normal 4-way pairwisekey and 2-way groupkey handshake
- 2. MIC error (Countermeasures attack) report packet from STA.
- 3. Request for pairwise/group key update from STA
- Return:
- ==========================================================================
-*/
-void WpaEAPOLKeyAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
- struct rt_mac_table_entry *pEntry;
- struct rt_header_802_11 * pHeader;
- struct rt_eapol_packet * pEapol_packet;
- struct rt_key_info peerKeyInfo;
-
- DBGPRINT(RT_DEBUG_TRACE, ("WpaEAPOLKeyAction ===>\n"));
-
- pHeader = (struct rt_header_802_11 *) Elem->Msg;
- pEapol_packet =
- (struct rt_eapol_packet *) & Elem->Msg[LENGTH_802_11 + LENGTH_802_1_H];
-
- NdisZeroMemory((u8 *)& peerKeyInfo, sizeof(peerKeyInfo));
- NdisMoveMemory((u8 *)& peerKeyInfo,
- (u8 *)& pEapol_packet->KeyDesc.KeyInfo,
- sizeof(struct rt_key_info));
-
- hex_dump("Received Eapol frame", (unsigned char *)pEapol_packet,
- (Elem->MsgLen - LENGTH_802_11 - LENGTH_802_1_H));
-
- *((u16 *) & peerKeyInfo) = cpu2le16(*((u16 *) & peerKeyInfo));
-
- do {
- pEntry = MacTableLookup(pAd, pHeader->Addr2);
-
- if (!pEntry
- || ((!pEntry->ValidAsCLI) && (!pEntry->ValidAsApCli)))
- break;
-
- if (pEntry->AuthMode < Ndis802_11AuthModeWPA)
- break;
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("Receive EAPoL-Key frame from STA %pMF\n",
- pEntry->Addr));
-
- if (((pEapol_packet->ProVer != EAPOL_VER)
- && (pEapol_packet->ProVer != EAPOL_VER2))
- || ((pEapol_packet->KeyDesc.Type != WPA1_KEY_DESC)
- && (pEapol_packet->KeyDesc.Type != WPA2_KEY_DESC))) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("Key descripter does not match with WPA rule\n"));
- break;
- }
- /* The value 1 shall be used for all EAPOL-Key frames to and from a STA when */
- /* neither the group nor pairwise ciphers are CCMP for Key Descriptor 1. */
- if ((pEntry->WepStatus == Ndis802_11Encryption2Enabled)
- && (peerKeyInfo.KeyDescVer != DESC_TYPE_TKIP)) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("Key descripter version not match(TKIP) \n"));
- break;
- }
- /* The value 2 shall be used for all EAPOL-Key frames to and from a STA when */
- /* either the pairwise or the group cipher is AES-CCMP for Key Descriptor 2. */
- else if ((pEntry->WepStatus == Ndis802_11Encryption3Enabled)
- && (peerKeyInfo.KeyDescVer != DESC_TYPE_AES)) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("Key descripter version not match(AES) \n"));
- break;
- }
- /* Check if this STA is in class 3 state and the WPA state is started */
- if ((pEntry->Sst == SST_ASSOC)
- && (pEntry->WpaState >= AS_INITPSK)) {
- /* Check the Key Ack (bit 7) of the Key Information to determine the Authenticator */
- /* or not. */
- /* An EAPOL-Key frame that is sent by the Supplicant in response to an EAPOL- */
- /* Key frame from the Authenticator must not have the Ack bit set. */
- if (peerKeyInfo.KeyAck == 1) {
- /* The frame is snet by Authenticator. */
- /* So the Supplicant side shall handle this. */
-
- if ((peerKeyInfo.Secure == 0)
- && (peerKeyInfo.Request == 0)
- && (peerKeyInfo.Error == 0)
- && (peerKeyInfo.KeyType == PAIRWISEKEY)) {
- /* Process 1. the message 1 of 4-way HS in WPA or WPA2 */
- /* EAPOL-Key(0,0,1,0,P,0,0,ANonce,0,DataKD_M1) */
- /* 2. the message 3 of 4-way HS in WPA */
- /* EAPOL-Key(0,1,1,1,P,0,KeyRSC,ANonce,MIC,DataKD_M3) */
- if (peerKeyInfo.KeyMic == 0)
- PeerPairMsg1Action(pAd, pEntry,
- Elem);
- else
- PeerPairMsg3Action(pAd, pEntry,
- Elem);
- } else if ((peerKeyInfo.Secure == 1)
- && (peerKeyInfo.KeyMic == 1)
- && (peerKeyInfo.Request == 0)
- && (peerKeyInfo.Error == 0)) {
- /* Process 1. the message 3 of 4-way HS in WPA2 */
- /* EAPOL-Key(1,1,1,1,P,0,KeyRSC,ANonce,MIC,DataKD_M3) */
- /* 2. the message 1 of group KS in WPA or WPA2 */
- /* EAPOL-Key(1,1,1,0,G,0,Key RSC,0, MIC,GTK[N]) */
- if (peerKeyInfo.KeyType == PAIRWISEKEY)
- PeerPairMsg3Action(pAd, pEntry,
- Elem);
- else
- PeerGroupMsg1Action(pAd, pEntry,
- Elem);
- }
- } else {
- /* The frame is snet by Supplicant. */
- /* So the Authenticator side shall handle this. */
- if ((peerKeyInfo.Request == 0) &&
- (peerKeyInfo.Error == 0) &&
- (peerKeyInfo.KeyMic == 1)) {
- if (peerKeyInfo.Secure == 0
- && peerKeyInfo.KeyType ==
- PAIRWISEKEY) {
- /* EAPOL-Key(0,1,0,0,P,0,0,SNonce,MIC,Data) */
- /* Process 1. message 2 of 4-way HS in WPA or WPA2 */
- /* 2. message 4 of 4-way HS in WPA */
- if (CONV_ARRARY_TO_u16
- (pEapol_packet->KeyDesc.
- KeyDataLen) == 0) {
- PeerPairMsg4Action(pAd,
- pEntry,
- Elem);
- } else {
- PeerPairMsg2Action(pAd,
- pEntry,
- Elem);
- }
- } else if (peerKeyInfo.Secure == 1
- && peerKeyInfo.KeyType ==
- PAIRWISEKEY) {
- /* EAPOL-Key(1,1,0,0,P,0,0,0,MIC,0) */
- /* Process message 4 of 4-way HS in WPA2 */
- PeerPairMsg4Action(pAd, pEntry,
- Elem);
- } else if (peerKeyInfo.Secure == 1
- && peerKeyInfo.KeyType ==
- GROUPKEY) {
- /* EAPOL-Key(1,1,0,0,G,0,0,0,MIC,0) */
- /* Process message 2 of Group key HS in WPA or WPA2 */
- PeerGroupMsg2Action(pAd, pEntry,
- &Elem->
- Msg
- [LENGTH_802_11],
- (Elem->
- MsgLen -
- LENGTH_802_11));
- }
- }
- }
- }
- } while (FALSE);
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Copy frame from waiting queue into relative ring buffer and set
- appropriate ASIC register to kick hardware encryption before really
- sent out to air.
-
- Arguments:
- pAd Pointer to our adapter
- void * Pointer to outgoing Ndis frame
- NumberOfFrag Number of fragment required
-
- Return Value:
- None
-
- Note:
-
- ========================================================================
-*/
-void RTMPToWirelessSta(struct rt_rtmp_adapter *pAd,
- struct rt_mac_table_entry *pEntry,
- u8 *pHeader802_3,
- u32 HdrLen,
- u8 *pData, u32 DataLen, IN BOOLEAN bClearFrame)
-{
- void *pPacket;
- int Status;
-
- if ((!pEntry) || ((!pEntry->ValidAsCLI) && (!pEntry->ValidAsApCli)))
- return;
-
- do {
- /* build a NDIS packet */
- Status =
- RTMPAllocateNdisPacket(pAd, &pPacket, pHeader802_3, HdrLen,
- pData, DataLen);
- if (Status != NDIS_STATUS_SUCCESS)
- break;
-
- if (bClearFrame)
- RTMP_SET_PACKET_CLEAR_EAP_FRAME(pPacket, 1);
- else
- RTMP_SET_PACKET_CLEAR_EAP_FRAME(pPacket, 0);
- {
- RTMP_SET_PACKET_SOURCE(pPacket, PKTSRC_NDIS);
-
- RTMP_SET_PACKET_NET_DEVICE_MBSSID(pPacket, MAIN_MBSSID); /* set a default value */
- if (pEntry->apidx != 0)
- RTMP_SET_PACKET_NET_DEVICE_MBSSID(pPacket,
- pEntry->
- apidx);
-
- RTMP_SET_PACKET_WCID(pPacket, (u8)pEntry->Aid);
- RTMP_SET_PACKET_MOREDATA(pPacket, FALSE);
- }
-
- {
- /* send out the packet */
- Status = STASendPacket(pAd, pPacket);
- if (Status == NDIS_STATUS_SUCCESS) {
- u8 Index;
-
- /* Dequeue one frame from TxSwQueue0..3 queue and process it */
- /* There are three place calling dequeue for TX ring. */
- /* 1. Here, right after queueing the frame. */
- /* 2. At the end of TxRingTxDone service routine. */
- /* 3. Upon NDIS call RTMPSendPackets */
- if ((!RTMP_TEST_FLAG
- (pAd, fRTMP_ADAPTER_BSS_SCAN_IN_PROGRESS))
- &&
- (!RTMP_TEST_FLAG
- (pAd, fRTMP_ADAPTER_RESET_IN_PROGRESS))) {
- for (Index = 0; Index < 5; Index++)
- if (pAd->TxSwQueue[Index].
- Number > 0)
- RTMPDeQueuePacket(pAd,
- FALSE,
- Index,
- MAX_TX_PROCESS);
- }
- }
- }
-
- } while (FALSE);
-}
-
-/*
- ==========================================================================
- Description:
- This is a function to initialize 4-way handshake
-
- Return:
-
- ==========================================================================
-*/
-void WPAStart4WayHS(struct rt_rtmp_adapter *pAd,
- struct rt_mac_table_entry *pEntry, unsigned long TimeInterval)
-{
- u8 Header802_3[14];
- struct rt_eapol_packet EAPOLPKT;
- u8 *pBssid = NULL;
- u8 group_cipher = Ndis802_11WEPDisabled;
-
- DBGPRINT(RT_DEBUG_TRACE, ("===> WPAStart4WayHS\n"));
-
- if (RTMP_TEST_FLAG
- (pAd,
- fRTMP_ADAPTER_RESET_IN_PROGRESS | fRTMP_ADAPTER_HALT_IN_PROGRESS))
- {
- DBGPRINT(RT_DEBUG_ERROR,
- ("[ERROR]WPAStart4WayHS : The interface is closed...\n"));
- return;
- }
-
- if (pBssid == NULL) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("[ERROR]WPAStart4WayHS : No corresponding Authenticator.\n"));
- return;
- }
- /* Check the status */
- if ((pEntry->WpaState > AS_PTKSTART) || (pEntry->WpaState < AS_INITPMK)) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("[ERROR]WPAStart4WayHS : Not expect calling\n"));
- return;
- }
-
- /* Increment replay counter by 1 */
- ADD_ONE_To_64BIT_VAR(pEntry->R_Counter);
-
- /* Randomly generate ANonce */
- GenRandom(pAd, (u8 *) pBssid, pEntry->ANonce);
-
- /* Construct EAPoL message - Pairwise Msg 1 */
- /* EAPOL-Key(0,0,1,0,P,0,0,ANonce,0,DataKD_M1) */
- NdisZeroMemory(&EAPOLPKT, sizeof(struct rt_eapol_packet));
- ConstructEapolMsg(pEntry, group_cipher, EAPOL_PAIR_MSG_1, 0, /* Default key index */
- pEntry->ANonce, NULL, /* TxRSC */
- NULL, /* GTK */
- NULL, /* RSNIE */
- 0, /* RSNIE length */
- &EAPOLPKT);
-
- /* Make outgoing frame */
- MAKE_802_3_HEADER(Header802_3, pEntry->Addr, pBssid, EAPOL);
- RTMPToWirelessSta(pAd, pEntry, Header802_3,
- LENGTH_802_3, (u8 *)& EAPOLPKT,
- CONV_ARRARY_TO_u16(EAPOLPKT.Body_Len) + 4,
- (pEntry->PortSecured ==
- WPA_802_1X_PORT_SECURED) ? FALSE : TRUE);
-
- /* Trigger Retry Timer */
- RTMPModTimer(&pEntry->RetryTimer, TimeInterval);
-
- /* Update State */
- pEntry->WpaState = AS_PTKSTART;
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("<=== WPAStart4WayHS: send Msg1 of 4-way \n"));
-
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Process Pairwise key Msg-1 of 4-way handshaking and send Msg-2
-
- Arguments:
- pAd Pointer to our adapter
- Elem Message body
-
- Return Value:
- None
-
- Note:
-
- ========================================================================
-*/
-void PeerPairMsg1Action(struct rt_rtmp_adapter *pAd,
- struct rt_mac_table_entry *pEntry, struct rt_mlme_queue_elem *Elem)
-{
- u8 PTK[80];
- u8 Header802_3[14];
- struct rt_eapol_packet * pMsg1;
- u32 MsgLen;
- struct rt_eapol_packet EAPOLPKT;
- u8 *pCurrentAddr = NULL;
- u8 *pmk_ptr = NULL;
- u8 group_cipher = Ndis802_11WEPDisabled;
- u8 *rsnie_ptr = NULL;
- u8 rsnie_len = 0;
-
- DBGPRINT(RT_DEBUG_TRACE, ("===> PeerPairMsg1Action \n"));
-
- if ((!pEntry) || ((!pEntry->ValidAsCLI) && (!pEntry->ValidAsApCli)))
- return;
-
- if (Elem->MsgLen <
- (LENGTH_802_11 + LENGTH_802_1_H + LENGTH_EAPOL_H +
- sizeof(struct rt_key_descripter) - MAX_LEN_OF_RSNIE - 2))
- return;
-
- {
- pCurrentAddr = pAd->CurrentAddress;
- pmk_ptr = pAd->StaCfg.PMK;
- group_cipher = pAd->StaCfg.GroupCipher;
- rsnie_ptr = pAd->StaCfg.RSN_IE;
- rsnie_len = pAd->StaCfg.RSNIE_Len;
- }
-
- /* Store the received frame */
- pMsg1 = (struct rt_eapol_packet *) & Elem->Msg[LENGTH_802_11 + LENGTH_802_1_H];
- MsgLen = Elem->MsgLen - LENGTH_802_11 - LENGTH_802_1_H;
-
- /* Sanity Check peer Pairwise message 1 - Replay Counter */
- if (PeerWpaMessageSanity(pAd, pMsg1, MsgLen, EAPOL_PAIR_MSG_1, pEntry)
- == FALSE)
- return;
-
- /* Store Replay counter, it will use to verify message 3 and construct message 2 */
- NdisMoveMemory(pEntry->R_Counter, pMsg1->KeyDesc.ReplayCounter,
- LEN_KEY_DESC_REPLAY);
-
- /* Store ANonce */
- NdisMoveMemory(pEntry->ANonce, pMsg1->KeyDesc.KeyNonce,
- LEN_KEY_DESC_NONCE);
-
- /* Generate random SNonce */
- GenRandom(pAd, (u8 *) pCurrentAddr, pEntry->SNonce);
-
- {
- /* Calculate PTK(ANonce, SNonce) */
- WpaDerivePTK(pAd,
- pmk_ptr,
- pEntry->ANonce,
- pEntry->Addr,
- pEntry->SNonce, pCurrentAddr, PTK, LEN_PTK);
-
- /* Save key to PTK entry */
- NdisMoveMemory(pEntry->PTK, PTK, LEN_PTK);
- }
-
- /* Update WpaState */
- pEntry->WpaState = AS_PTKINIT_NEGOTIATING;
-
- /* Construct EAPoL message - Pairwise Msg 2 */
- /* EAPOL-Key(0,1,0,0,P,0,0,SNonce,MIC,DataKD_M2) */
- NdisZeroMemory(&EAPOLPKT, sizeof(struct rt_eapol_packet));
- ConstructEapolMsg(pEntry, group_cipher, EAPOL_PAIR_MSG_2, 0, /* DefaultKeyIdx */
- pEntry->SNonce, NULL, /* TxRsc */
- NULL, /* GTK */
- (u8 *) rsnie_ptr, rsnie_len, &EAPOLPKT);
-
- /* Make outgoing frame */
- MAKE_802_3_HEADER(Header802_3, pEntry->Addr, pCurrentAddr, EAPOL);
-
- RTMPToWirelessSta(pAd, pEntry,
- Header802_3, sizeof(Header802_3), (u8 *)& EAPOLPKT,
- CONV_ARRARY_TO_u16(EAPOLPKT.Body_Len) + 4, TRUE);
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("<=== PeerPairMsg1Action: send Msg2 of 4-way \n"));
-}
-
-/*
- ==========================================================================
- Description:
- When receiving the second packet of 4-way pairwisekey handshake.
- Return:
- ==========================================================================
-*/
-void PeerPairMsg2Action(struct rt_rtmp_adapter *pAd,
- struct rt_mac_table_entry *pEntry, struct rt_mlme_queue_elem *Elem)
-{
- u8 PTK[80];
- BOOLEAN Cancelled;
- struct rt_header_802_11 * pHeader;
- struct rt_eapol_packet EAPOLPKT;
- struct rt_eapol_packet * pMsg2;
- u32 MsgLen;
- u8 Header802_3[LENGTH_802_3];
- u8 TxTsc[6];
- u8 *pBssid = NULL;
- u8 *pmk_ptr = NULL;
- u8 *gtk_ptr = NULL;
- u8 default_key = 0;
- u8 group_cipher = Ndis802_11WEPDisabled;
- u8 *rsnie_ptr = NULL;
- u8 rsnie_len = 0;
-
- DBGPRINT(RT_DEBUG_TRACE, ("===> PeerPairMsg2Action \n"));
-
- if ((!pEntry) || (!pEntry->ValidAsCLI))
- return;
-
- if (Elem->MsgLen <
- (LENGTH_802_11 + LENGTH_802_1_H + LENGTH_EAPOL_H +
- sizeof(struct rt_key_descripter) - MAX_LEN_OF_RSNIE - 2))
- return;
-
- /* check Entry in valid State */
- if (pEntry->WpaState < AS_PTKSTART)
- return;
-
- /* pointer to 802.11 header */
- pHeader = (struct rt_header_802_11 *) Elem->Msg;
-
- /* skip 802.11_header(24-byte) and LLC_header(8) */
- pMsg2 = (struct rt_eapol_packet *) & Elem->Msg[LENGTH_802_11 + LENGTH_802_1_H];
- MsgLen = Elem->MsgLen - LENGTH_802_11 - LENGTH_802_1_H;
-
- /* Store SNonce */
- NdisMoveMemory(pEntry->SNonce, pMsg2->KeyDesc.KeyNonce,
- LEN_KEY_DESC_NONCE);
-
- {
- /* Derive PTK */
- WpaDerivePTK(pAd, (u8 *) pmk_ptr, pEntry->ANonce, /* ANONCE */
- (u8 *) pBssid, pEntry->SNonce, /* SNONCE */
- pEntry->Addr, PTK, LEN_PTK);
-
- NdisMoveMemory(pEntry->PTK, PTK, LEN_PTK);
- }
-
- /* Sanity Check peer Pairwise message 2 - Replay Counter, MIC, RSNIE */
- if (PeerWpaMessageSanity(pAd, pMsg2, MsgLen, EAPOL_PAIR_MSG_2, pEntry)
- == FALSE)
- return;
-
- do {
- /* delete retry timer */
- RTMPCancelTimer(&pEntry->RetryTimer, &Cancelled);
-
- /* Change state */
- pEntry->WpaState = AS_PTKINIT_NEGOTIATING;
-
- /* Increment replay counter by 1 */
- ADD_ONE_To_64BIT_VAR(pEntry->R_Counter);
-
- /* Construct EAPoL message - Pairwise Msg 3 */
- NdisZeroMemory(&EAPOLPKT, sizeof(struct rt_eapol_packet));
- ConstructEapolMsg(pEntry,
- group_cipher,
- EAPOL_PAIR_MSG_3,
- default_key,
- pEntry->ANonce,
- TxTsc,
- (u8 *) gtk_ptr,
- (u8 *) rsnie_ptr, rsnie_len, &EAPOLPKT);
-
- /* Make outgoing frame */
- MAKE_802_3_HEADER(Header802_3, pEntry->Addr, pBssid, EAPOL);
- RTMPToWirelessSta(pAd, pEntry, Header802_3, LENGTH_802_3,
- (u8 *)& EAPOLPKT,
- CONV_ARRARY_TO_u16(EAPOLPKT.Body_Len) + 4,
- (pEntry->PortSecured ==
- WPA_802_1X_PORT_SECURED) ? FALSE : TRUE);
-
- pEntry->ReTryCounter = PEER_MSG3_RETRY_TIMER_CTR;
- RTMPSetTimer(&pEntry->RetryTimer, PEER_MSG3_RETRY_EXEC_INTV);
-
- /* Update State */
- pEntry->WpaState = AS_PTKINIT_NEGOTIATING;
- } while (FALSE);
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("<=== PeerPairMsg2Action: send Msg3 of 4-way \n"));
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Process Pairwise key Msg 3 of 4-way handshaking and send Msg 4
-
- Arguments:
- pAd Pointer to our adapter
- Elem Message body
-
- Return Value:
- None
-
- Note:
-
- ========================================================================
-*/
-void PeerPairMsg3Action(struct rt_rtmp_adapter *pAd,
- struct rt_mac_table_entry *pEntry, struct rt_mlme_queue_elem *Elem)
-{
- struct rt_header_802_11 * pHeader;
- u8 Header802_3[14];
- struct rt_eapol_packet EAPOLPKT;
- struct rt_eapol_packet * pMsg3;
- u32 MsgLen;
- u8 *pCurrentAddr = NULL;
- u8 group_cipher = Ndis802_11WEPDisabled;
-
- DBGPRINT(RT_DEBUG_TRACE, ("===> PeerPairMsg3Action \n"));
-
- if ((!pEntry) || ((!pEntry->ValidAsCLI) && (!pEntry->ValidAsApCli)))
- return;
-
- if (Elem->MsgLen <
- (LENGTH_802_11 + LENGTH_802_1_H + LENGTH_EAPOL_H +
- sizeof(struct rt_key_descripter) - MAX_LEN_OF_RSNIE - 2))
- return;
-
- {
- pCurrentAddr = pAd->CurrentAddress;
- group_cipher = pAd->StaCfg.GroupCipher;
-
- }
-
- /* Record 802.11 header & the received EAPOL packet Msg3 */
- pHeader = (struct rt_header_802_11 *) Elem->Msg;
- pMsg3 = (struct rt_eapol_packet *) & Elem->Msg[LENGTH_802_11 + LENGTH_802_1_H];
- MsgLen = Elem->MsgLen - LENGTH_802_11 - LENGTH_802_1_H;
-
- /* Sanity Check peer Pairwise message 3 - Replay Counter, MIC, RSNIE */
- if (PeerWpaMessageSanity(pAd, pMsg3, MsgLen, EAPOL_PAIR_MSG_3, pEntry)
- == FALSE)
- return;
-
- /* Save Replay counter, it will use construct message 4 */
- NdisMoveMemory(pEntry->R_Counter, pMsg3->KeyDesc.ReplayCounter,
- LEN_KEY_DESC_REPLAY);
-
- /* Double check ANonce */
- if (!NdisEqualMemory
- (pEntry->ANonce, pMsg3->KeyDesc.KeyNonce, LEN_KEY_DESC_NONCE)) {
- return;
- }
- /* Construct EAPoL message - Pairwise Msg 4 */
- NdisZeroMemory(&EAPOLPKT, sizeof(struct rt_eapol_packet));
- ConstructEapolMsg(pEntry, group_cipher, EAPOL_PAIR_MSG_4, 0, /* group key index not used in message 4 */
- NULL, /* Nonce not used in message 4 */
- NULL, /* TxRSC not used in message 4 */
- NULL, /* GTK not used in message 4 */
- NULL, /* RSN IE not used in message 4 */
- 0, &EAPOLPKT);
-
- /* Update WpaState */
- pEntry->WpaState = AS_PTKINITDONE;
-
- /* Update pairwise key */
- {
- struct rt_cipher_key *pSharedKey;
-
- pSharedKey = &pAd->SharedKey[BSS0][0];
-
- NdisMoveMemory(pAd->StaCfg.PTK, pEntry->PTK, LEN_PTK);
-
- /* Prepare pair-wise key information into shared key table */
- NdisZeroMemory(pSharedKey, sizeof(struct rt_cipher_key));
- pSharedKey->KeyLen = LEN_TKIP_EK;
- NdisMoveMemory(pSharedKey->Key, &pAd->StaCfg.PTK[32],
- LEN_TKIP_EK);
- NdisMoveMemory(pSharedKey->RxMic, &pAd->StaCfg.PTK[48],
- LEN_TKIP_RXMICK);
- NdisMoveMemory(pSharedKey->TxMic,
- &pAd->StaCfg.PTK[48 + LEN_TKIP_RXMICK],
- LEN_TKIP_TXMICK);
-
- /* Decide its ChiperAlg */
- if (pAd->StaCfg.PairCipher == Ndis802_11Encryption2Enabled)
- pSharedKey->CipherAlg = CIPHER_TKIP;
- else if (pAd->StaCfg.PairCipher == Ndis802_11Encryption3Enabled)
- pSharedKey->CipherAlg = CIPHER_AES;
- else
- pSharedKey->CipherAlg = CIPHER_NONE;
-
- /* Update these related information to struct rt_mac_table_entry */
- pEntry = &pAd->MacTab.Content[BSSID_WCID];
- NdisMoveMemory(pEntry->PairwiseKey.Key, &pAd->StaCfg.PTK[32],
- LEN_TKIP_EK);
- NdisMoveMemory(pEntry->PairwiseKey.RxMic, &pAd->StaCfg.PTK[48],
- LEN_TKIP_RXMICK);
- NdisMoveMemory(pEntry->PairwiseKey.TxMic,
- &pAd->StaCfg.PTK[48 + LEN_TKIP_RXMICK],
- LEN_TKIP_TXMICK);
- pEntry->PairwiseKey.CipherAlg = pSharedKey->CipherAlg;
-
- /* Update pairwise key information to ASIC Shared Key Table */
- AsicAddSharedKeyEntry(pAd,
- BSS0,
- 0,
- pSharedKey->CipherAlg,
- pSharedKey->Key,
- pSharedKey->TxMic, pSharedKey->RxMic);
-
- /* Update ASIC WCID attribute table and IVEIV table */
- RTMPAddWcidAttributeEntry(pAd,
- BSS0,
- 0, pSharedKey->CipherAlg, pEntry);
-
- }
-
- /* open 802.1x port control and privacy filter */
- if (pEntry->AuthMode == Ndis802_11AuthModeWPA2PSK ||
- pEntry->AuthMode == Ndis802_11AuthModeWPA2) {
- pEntry->PortSecured = WPA_802_1X_PORT_SECURED;
- pEntry->PrivacyFilter = Ndis802_11PrivFilterAcceptAll;
-
- STA_PORT_SECURED(pAd);
- /* Indicate Connected for GUI */
- pAd->IndicateMediaState = NdisMediaStateConnected;
- DBGPRINT(RT_DEBUG_TRACE,
- ("PeerPairMsg3Action: AuthMode(%s) PairwiseCipher(%s) GroupCipher(%s) \n",
- GetAuthMode(pEntry->AuthMode),
- GetEncryptType(pEntry->WepStatus),
- GetEncryptType(group_cipher)));
- } else {
- }
-
- /* Init 802.3 header and send out */
- MAKE_802_3_HEADER(Header802_3, pEntry->Addr, pCurrentAddr, EAPOL);
- RTMPToWirelessSta(pAd, pEntry,
- Header802_3, sizeof(Header802_3),
- (u8 *)& EAPOLPKT,
- CONV_ARRARY_TO_u16(EAPOLPKT.Body_Len) + 4, TRUE);
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("<=== PeerPairMsg3Action: send Msg4 of 4-way \n"));
-}
-
-/*
- ==========================================================================
- Description:
- When receiving the last packet of 4-way pairwisekey handshake.
- Initialize 2-way groupkey handshake following.
- Return:
- ==========================================================================
-*/
-void PeerPairMsg4Action(struct rt_rtmp_adapter *pAd,
- struct rt_mac_table_entry *pEntry, struct rt_mlme_queue_elem *Elem)
-{
- struct rt_eapol_packet * pMsg4;
- struct rt_header_802_11 * pHeader;
- u32 MsgLen;
- BOOLEAN Cancelled;
- u8 group_cipher = Ndis802_11WEPDisabled;
-
- DBGPRINT(RT_DEBUG_TRACE, ("===> PeerPairMsg4Action\n"));
-
- do {
- if ((!pEntry) || (!pEntry->ValidAsCLI))
- break;
-
- if (Elem->MsgLen <
- (LENGTH_802_11 + LENGTH_802_1_H + LENGTH_EAPOL_H +
- sizeof(struct rt_key_descripter) - MAX_LEN_OF_RSNIE - 2))
- break;
-
- if (pEntry->WpaState < AS_PTKINIT_NEGOTIATING)
- break;
-
- /* pointer to 802.11 header */
- pHeader = (struct rt_header_802_11 *) Elem->Msg;
-
- /* skip 802.11_header(24-byte) and LLC_header(8) */
- pMsg4 =
- (struct rt_eapol_packet *) & Elem->Msg[LENGTH_802_11 + LENGTH_802_1_H];
- MsgLen = Elem->MsgLen - LENGTH_802_11 - LENGTH_802_1_H;
-
- /* Sanity Check peer Pairwise message 4 - Replay Counter, MIC */
- if (PeerWpaMessageSanity
- (pAd, pMsg4, MsgLen, EAPOL_PAIR_MSG_4, pEntry) == FALSE)
- break;
-
- /* 3. uses the MLME.SETKEYS.request to configure PTK into MAC */
- NdisZeroMemory(&pEntry->PairwiseKey, sizeof(struct rt_cipher_key));
-
- /* reset IVEIV in Asic */
- AsicUpdateWCIDIVEIV(pAd, pEntry->Aid, 1, 0);
-
- pEntry->PairwiseKey.KeyLen = LEN_TKIP_EK;
- NdisMoveMemory(pEntry->PairwiseKey.Key, &pEntry->PTK[32],
- LEN_TKIP_EK);
- NdisMoveMemory(pEntry->PairwiseKey.RxMic,
- &pEntry->PTK[TKIP_AP_RXMICK_OFFSET],
- LEN_TKIP_RXMICK);
- NdisMoveMemory(pEntry->PairwiseKey.TxMic,
- &pEntry->PTK[TKIP_AP_TXMICK_OFFSET],
- LEN_TKIP_TXMICK);
-
- /* Set pairwise key to Asic */
- {
- pEntry->PairwiseKey.CipherAlg = CIPHER_NONE;
- if (pEntry->WepStatus == Ndis802_11Encryption2Enabled)
- pEntry->PairwiseKey.CipherAlg = CIPHER_TKIP;
- else if (pEntry->WepStatus ==
- Ndis802_11Encryption3Enabled)
- pEntry->PairwiseKey.CipherAlg = CIPHER_AES;
-
- /* Add Pair-wise key to Asic */
- AsicAddPairwiseKeyEntry(pAd,
- pEntry->Addr,
- (u8)pEntry->Aid,
- &pEntry->PairwiseKey);
-
- /* update WCID attribute table and IVEIV table for this entry */
- RTMPAddWcidAttributeEntry(pAd,
- pEntry->apidx,
- 0,
- pEntry->PairwiseKey.CipherAlg,
- pEntry);
- }
-
- /* 4. upgrade state */
- pEntry->PrivacyFilter = Ndis802_11PrivFilterAcceptAll;
- pEntry->WpaState = AS_PTKINITDONE;
- pEntry->PortSecured = WPA_802_1X_PORT_SECURED;
-
- if (pEntry->AuthMode == Ndis802_11AuthModeWPA2 ||
- pEntry->AuthMode == Ndis802_11AuthModeWPA2PSK) {
- pEntry->GTKState = REKEY_ESTABLISHED;
- RTMPCancelTimer(&pEntry->RetryTimer, &Cancelled);
-
- /* send wireless event - for set key done WPA2 */
- if (pAd->CommonCfg.bWirelessEvent)
- RTMPSendWirelessEvent(pAd,
- IW_SET_KEY_DONE_WPA2_EVENT_FLAG,
- pEntry->Addr,
- pEntry->apidx, 0);
-
- DBGPRINT(RT_DEBUG_OFF,
- ("AP SETKEYS DONE - WPA2, AuthMode(%d)=%s, WepStatus(%d)=%s, GroupWepStatus(%d)=%s\n\n",
- pEntry->AuthMode,
- GetAuthMode(pEntry->AuthMode),
- pEntry->WepStatus,
- GetEncryptType(pEntry->WepStatus),
- group_cipher, GetEncryptType(group_cipher)));
- } else {
- /* 5. init Group 2-way handshake if necessary. */
- WPAStart2WayGroupHS(pAd, pEntry);
-
- pEntry->ReTryCounter = GROUP_MSG1_RETRY_TIMER_CTR;
- RTMPModTimer(&pEntry->RetryTimer,
- PEER_MSG3_RETRY_EXEC_INTV);
- }
- } while (FALSE);
-
-}
-
-/*
- ==========================================================================
- Description:
- This is a function to send the first packet of 2-way groupkey handshake
- Return:
-
- ==========================================================================
-*/
-void WPAStart2WayGroupHS(struct rt_rtmp_adapter *pAd, struct rt_mac_table_entry *pEntry)
-{
- u8 Header802_3[14];
- u8 TxTsc[6];
- struct rt_eapol_packet EAPOLPKT;
- u8 group_cipher = Ndis802_11WEPDisabled;
- u8 default_key = 0;
- u8 *gnonce_ptr = NULL;
- u8 *gtk_ptr = NULL;
- u8 *pBssid = NULL;
-
- DBGPRINT(RT_DEBUG_TRACE, ("===> WPAStart2WayGroupHS\n"));
-
- if ((!pEntry) || (!pEntry->ValidAsCLI))
- return;
-
- do {
- /* Increment replay counter by 1 */
- ADD_ONE_To_64BIT_VAR(pEntry->R_Counter);
-
- /* Construct EAPoL message - Group Msg 1 */
- NdisZeroMemory(&EAPOLPKT, sizeof(struct rt_eapol_packet));
- ConstructEapolMsg(pEntry,
- group_cipher,
- EAPOL_GROUP_MSG_1,
- default_key,
- (u8 *) gnonce_ptr,
- TxTsc, (u8 *) gtk_ptr, NULL, 0, &EAPOLPKT);
-
- /* Make outgoing frame */
- MAKE_802_3_HEADER(Header802_3, pEntry->Addr, pBssid, EAPOL);
- RTMPToWirelessSta(pAd, pEntry,
- Header802_3, LENGTH_802_3,
- (u8 *)& EAPOLPKT,
- CONV_ARRARY_TO_u16(EAPOLPKT.Body_Len) + 4,
- FALSE);
-
- } while (FALSE);
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("<=== WPAStart2WayGroupHS : send out Group Message 1 \n"));
-
- return;
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Process Group key 2-way handshaking
-
- Arguments:
- pAd Pointer to our adapter
- Elem Message body
-
- Return Value:
- None
-
- Note:
-
- ========================================================================
-*/
-void PeerGroupMsg1Action(struct rt_rtmp_adapter *pAd,
- struct rt_mac_table_entry *pEntry, struct rt_mlme_queue_elem *Elem)
-{
- u8 Header802_3[14];
- struct rt_eapol_packet EAPOLPKT;
- struct rt_eapol_packet * pGroup;
- u32 MsgLen;
- BOOLEAN Cancelled;
- u8 default_key = 0;
- u8 group_cipher = Ndis802_11WEPDisabled;
- u8 *pCurrentAddr = NULL;
-
- DBGPRINT(RT_DEBUG_TRACE, ("===> PeerGroupMsg1Action \n"));
-
- if ((!pEntry) || ((!pEntry->ValidAsCLI) && (!pEntry->ValidAsApCli)))
- return;
-
- {
- pCurrentAddr = pAd->CurrentAddress;
- group_cipher = pAd->StaCfg.GroupCipher;
- default_key = pAd->StaCfg.DefaultKeyId;
- }
-
- /* Process Group Message 1 frame. skip 802.11 header(24) & LLC_SNAP header(8) */
- pGroup = (struct rt_eapol_packet *) & Elem->Msg[LENGTH_802_11 + LENGTH_802_1_H];
- MsgLen = Elem->MsgLen - LENGTH_802_11 - LENGTH_802_1_H;
-
- /* Sanity Check peer group message 1 - Replay Counter, MIC, RSNIE */
- if (PeerWpaMessageSanity(pAd, pGroup, MsgLen, EAPOL_GROUP_MSG_1, pEntry)
- == FALSE)
- return;
-
- /* delete retry timer */
- RTMPCancelTimer(&pEntry->RetryTimer, &Cancelled);
-
- /* Save Replay counter, it will use to construct message 2 */
- NdisMoveMemory(pEntry->R_Counter, pGroup->KeyDesc.ReplayCounter,
- LEN_KEY_DESC_REPLAY);
-
- /* Construct EAPoL message - Group Msg 2 */
- NdisZeroMemory(&EAPOLPKT, sizeof(struct rt_eapol_packet));
- ConstructEapolMsg(pEntry, group_cipher, EAPOL_GROUP_MSG_2, default_key, NULL, /* Nonce not used */
- NULL, /* TxRSC not used */
- NULL, /* GTK not used */
- NULL, /* RSN IE not used */
- 0, &EAPOLPKT);
-
- /* open 802.1x port control and privacy filter */
- pEntry->PortSecured = WPA_802_1X_PORT_SECURED;
- pEntry->PrivacyFilter = Ndis802_11PrivFilterAcceptAll;
-
- STA_PORT_SECURED(pAd);
- /* Indicate Connected for GUI */
- pAd->IndicateMediaState = NdisMediaStateConnected;
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("PeerGroupMsg1Action: AuthMode(%s) PairwiseCipher(%s) GroupCipher(%s) \n",
- GetAuthMode(pEntry->AuthMode),
- GetEncryptType(pEntry->WepStatus),
- GetEncryptType(group_cipher)));
-
- /* init header and Fill Packet and send Msg 2 to authenticator */
- MAKE_802_3_HEADER(Header802_3, pEntry->Addr, pCurrentAddr, EAPOL);
- RTMPToWirelessSta(pAd, pEntry,
- Header802_3, sizeof(Header802_3),
- (u8 *)& EAPOLPKT,
- CONV_ARRARY_TO_u16(EAPOLPKT.Body_Len) + 4, FALSE);
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("<=== PeerGroupMsg1Action: sned group message 2\n"));
-}
-
-/*
- ==========================================================================
- Description:
- When receiving the last packet of 2-way groupkey handshake.
- Return:
- ==========================================================================
-*/
-void PeerGroupMsg2Action(struct rt_rtmp_adapter *pAd,
- struct rt_mac_table_entry *pEntry,
- void * Msg, u32 MsgLen)
-{
- u32 Len;
- u8 *pData;
- BOOLEAN Cancelled;
- struct rt_eapol_packet * pMsg2;
- u8 group_cipher = Ndis802_11WEPDisabled;
-
- DBGPRINT(RT_DEBUG_TRACE, ("===> PeerGroupMsg2Action \n"));
-
- do {
- if ((!pEntry) || (!pEntry->ValidAsCLI))
- break;
-
- if (MsgLen <
- (LENGTH_802_1_H + LENGTH_EAPOL_H + sizeof(struct rt_key_descripter) -
- MAX_LEN_OF_RSNIE - 2))
- break;
-
- if (pEntry->WpaState != AS_PTKINITDONE)
- break;
-
- pData = (u8 *)Msg;
- pMsg2 = (struct rt_eapol_packet *) (pData + LENGTH_802_1_H);
- Len = MsgLen - LENGTH_802_1_H;
-
- /* Sanity Check peer group message 2 - Replay Counter, MIC */
- if (PeerWpaMessageSanity
- (pAd, pMsg2, Len, EAPOL_GROUP_MSG_2, pEntry) == FALSE)
- break;
-
- /* 3. upgrade state */
-
- RTMPCancelTimer(&pEntry->RetryTimer, &Cancelled);
- pEntry->GTKState = REKEY_ESTABLISHED;
-
- if ((pEntry->AuthMode == Ndis802_11AuthModeWPA2)
- || (pEntry->AuthMode == Ndis802_11AuthModeWPA2PSK)) {
- /* send wireless event - for set key done WPA2 */
- if (pAd->CommonCfg.bWirelessEvent)
- RTMPSendWirelessEvent(pAd,
- IW_SET_KEY_DONE_WPA2_EVENT_FLAG,
- pEntry->Addr,
- pEntry->apidx, 0);
-
- DBGPRINT(RT_DEBUG_OFF,
- ("AP SETKEYS DONE - WPA2, AuthMode(%d)=%s, WepStatus(%d)=%s, GroupWepStatus(%d)=%s\n\n",
- pEntry->AuthMode,
- GetAuthMode(pEntry->AuthMode),
- pEntry->WepStatus,
- GetEncryptType(pEntry->WepStatus),
- group_cipher, GetEncryptType(group_cipher)));
- } else {
- /* send wireless event - for set key done WPA */
- if (pAd->CommonCfg.bWirelessEvent)
- RTMPSendWirelessEvent(pAd,
- IW_SET_KEY_DONE_WPA1_EVENT_FLAG,
- pEntry->Addr,
- pEntry->apidx, 0);
-
- DBGPRINT(RT_DEBUG_OFF,
- ("AP SETKEYS DONE - WPA1, AuthMode(%d)=%s, WepStatus(%d)=%s, GroupWepStatus(%d)=%s\n\n",
- pEntry->AuthMode,
- GetAuthMode(pEntry->AuthMode),
- pEntry->WepStatus,
- GetEncryptType(pEntry->WepStatus),
- group_cipher, GetEncryptType(group_cipher)));
- }
- } while (FALSE);
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Classify WPA EAP message type
-
- Arguments:
- EAPType Value of EAP message type
- MsgType Internal Message definition for MLME state machine
-
- Return Value:
- TRUE Found appropriate message type
- FALSE No appropriate message type
-
- IRQL = DISPATCH_LEVEL
-
- Note:
- All these constants are defined in wpa.h
- For supplicant, there is only EAPOL Key message available
-
- ========================================================================
-*/
-BOOLEAN WpaMsgTypeSubst(u8 EAPType, int * MsgType)
-{
- switch (EAPType) {
- case EAPPacket:
- *MsgType = MT2_EAPPacket;
- break;
- case EAPOLStart:
- *MsgType = MT2_EAPOLStart;
- break;
- case EAPOLLogoff:
- *MsgType = MT2_EAPOLLogoff;
- break;
- case EAPOLKey:
- *MsgType = MT2_EAPOLKey;
- break;
- case EAPOLASFAlert:
- *MsgType = MT2_EAPOLASFAlert;
- break;
- default:
- return FALSE;
- }
- return TRUE;
-}
-
-/*
- ========================================================================
-
- Routine Description:
- The pseudo-random function(PRF) that hashes various inputs to
- derive a pseudo-random value. To add liveness to the pseudo-random
- value, a nonce should be one of the inputs.
-
- It is used to generate PTK, GTK or some specific random value.
-
- Arguments:
- u8 *key, - the key material for HMAC_SHA1 use
- int key_len - the length of key
- u8 *prefix - a prefix label
- int prefix_len - the length of the label
- u8 *data - a specific data with variable length
- int data_len - the length of a specific data
- int len - the output length
-
- Return Value:
- u8 *output - the calculated result
-
- Note:
- 802.11i-2004 Annex H.3
-
- ========================================================================
-*/
-void PRF(u8 * key,
- int key_len,
- u8 * prefix,
- int prefix_len,
- u8 * data, int data_len, u8 * output, int len)
-{
- int i;
- u8 *input;
- int currentindex = 0;
- int total_len;
-
- /* Allocate memory for input */
- os_alloc_mem(NULL, (u8 **) & input, 1024);
-
- if (input == NULL) {
- DBGPRINT(RT_DEBUG_ERROR, ("PRF: no memory!\n"));
- return;
- }
- /* Generate concatenation input */
- NdisMoveMemory(input, prefix, prefix_len);
-
- /* Concatenate a single octet containing 0 */
- input[prefix_len] = 0;
-
- /* Concatenate specific data */
- NdisMoveMemory(&input[prefix_len + 1], data, data_len);
- total_len = prefix_len + 1 + data_len;
-
- /* Concatenate a single octet containing 0 */
- /* This octet shall be update later */
- input[total_len] = 0;
- total_len++;
-
- /* Iterate to calculate the result by hmac-sha-1 */
- /* Then concatenate to last result */
- for (i = 0; i < (len + 19) / 20; i++) {
- HMAC_SHA1(key, key_len, input, total_len, &output[currentindex],
- SHA1_DIGEST_SIZE);
- currentindex += 20;
-
- /* update the last octet */
- input[total_len - 1]++;
- }
- os_free_mem(NULL, input);
-}
-
-/*
-* F(P, S, c, i) = U1 xor U2 xor ... Uc
-* U1 = PRF(P, S || Int(i))
-* U2 = PRF(P, U1)
-* Uc = PRF(P, Uc-1)
-*/
-
-static void F(char *password, unsigned char *ssid, int ssidlength,
- int iterations, int count, unsigned char *output)
-{
- unsigned char digest[36], digest1[SHA1_DIGEST_SIZE];
- int i, j;
-
- /* U1 = PRF(P, S || int(i)) */
- memcpy(digest, ssid, ssidlength);
- digest[ssidlength] = (unsigned char)((count >> 24) & 0xff);
- digest[ssidlength + 1] = (unsigned char)((count >> 16) & 0xff);
- digest[ssidlength + 2] = (unsigned char)((count >> 8) & 0xff);
- digest[ssidlength + 3] = (unsigned char)(count & 0xff);
- HMAC_SHA1((unsigned char *)password, (int)strlen(password), digest, ssidlength + 4, digest1, SHA1_DIGEST_SIZE); /* for WPA update */
-
- /* output = U1 */
- memcpy(output, digest1, SHA1_DIGEST_SIZE);
-
- for (i = 1; i < iterations; i++) {
- /* Un = PRF(P, Un-1) */
- HMAC_SHA1((unsigned char *)password, (int)strlen(password), digest1, SHA1_DIGEST_SIZE, digest, SHA1_DIGEST_SIZE); /* for WPA update */
- memcpy(digest1, digest, SHA1_DIGEST_SIZE);
-
- /* output = output xor Un */
- for (j = 0; j < SHA1_DIGEST_SIZE; j++) {
- output[j] ^= digest[j];
- }
- }
-}
-
-/*
-* password - ascii string up to 63 characters in length
-* ssid - octet string up to 32 octets
-* ssidlength - length of ssid in octets
-* output must be 40 octets in length and outputs 256 bits of key
-*/
-int PasswordHash(char *password, u8 *ssid, int ssidlength, u8 *output)
-{
- if ((strlen(password) > 63) || (ssidlength > 32))
- return 0;
-
- F(password, ssid, ssidlength, 4096, 1, output);
- F(password, ssid, ssidlength, 4096, 2, &output[SHA1_DIGEST_SIZE]);
- return 1;
-}
-
-/*
- ========================================================================
-
- Routine Description:
- It utilizes PRF-384 or PRF-512 to derive session-specific keys from a PMK.
- It shall be called by 4-way handshake processing.
-
- Arguments:
- pAd - pointer to our pAdapter context
- PMK - pointer to PMK
- ANonce - pointer to ANonce
- AA - pointer to Authenticator Address
- SNonce - pointer to SNonce
- SA - pointer to Supplicant Address
- len - indicate the length of PTK (octet)
-
- Return Value:
- Output pointer to the PTK
-
- Note:
- Refer to IEEE 802.11i-2004 8.5.1.2
-
- ========================================================================
-*/
-void WpaDerivePTK(struct rt_rtmp_adapter *pAd,
- u8 * PMK,
- u8 * ANonce,
- u8 * AA,
- u8 * SNonce,
- u8 * SA, u8 * output, u32 len)
-{
- u8 concatenation[76];
- u32 CurrPos = 0;
- u8 temp[32];
- u8 Prefix[] =
- { 'P', 'a', 'i', 'r', 'w', 'i', 's', 'e', ' ', 'k', 'e', 'y', ' ',
- 'e', 'x', 'p', 'a', 'n', 's', 'i', 'o', 'n'
- };
-
- /* initiate the concatenation input */
- NdisZeroMemory(temp, sizeof(temp));
- NdisZeroMemory(concatenation, 76);
-
- /* Get smaller address */
- if (RTMPCompareMemory(SA, AA, 6) == 1)
- NdisMoveMemory(concatenation, AA, 6);
- else
- NdisMoveMemory(concatenation, SA, 6);
- CurrPos += 6;
-
- /* Get larger address */
- if (RTMPCompareMemory(SA, AA, 6) == 1)
- NdisMoveMemory(&concatenation[CurrPos], SA, 6);
- else
- NdisMoveMemory(&concatenation[CurrPos], AA, 6);
-
- /* store the larger mac address for backward compatible of */
- /* ralink proprietary STA-key issue */
- NdisMoveMemory(temp, &concatenation[CurrPos], MAC_ADDR_LEN);
- CurrPos += 6;
-
- /* Get smaller Nonce */
- if (RTMPCompareMemory(ANonce, SNonce, 32) == 0)
- NdisMoveMemory(&concatenation[CurrPos], temp, 32); /* patch for ralink proprietary STA-key issue */
- else if (RTMPCompareMemory(ANonce, SNonce, 32) == 1)
- NdisMoveMemory(&concatenation[CurrPos], SNonce, 32);
- else
- NdisMoveMemory(&concatenation[CurrPos], ANonce, 32);
- CurrPos += 32;
-
- /* Get larger Nonce */
- if (RTMPCompareMemory(ANonce, SNonce, 32) == 0)
- NdisMoveMemory(&concatenation[CurrPos], temp, 32); /* patch for ralink proprietary STA-key issue */
- else if (RTMPCompareMemory(ANonce, SNonce, 32) == 1)
- NdisMoveMemory(&concatenation[CurrPos], ANonce, 32);
- else
- NdisMoveMemory(&concatenation[CurrPos], SNonce, 32);
- CurrPos += 32;
-
- hex_dump("concatenation=", concatenation, 76);
-
- /* Use PRF to generate PTK */
- PRF(PMK, LEN_MASTER_KEY, Prefix, 22, concatenation, 76, output, len);
-
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Generate random number by software.
-
- Arguments:
- pAd - pointer to our pAdapter context
- macAddr - pointer to local MAC address
-
- Return Value:
-
- Note:
- 802.1ii-2004 Annex H.5
-
- ========================================================================
-*/
-void GenRandom(struct rt_rtmp_adapter *pAd, u8 * macAddr, u8 * random)
-{
- int i, curr;
- u8 local[80], KeyCounter[32];
- u8 result[80];
- unsigned long CurrentTime;
- u8 prefix[] =
- { 'I', 'n', 'i', 't', ' ', 'C', 'o', 'u', 'n', 't', 'e', 'r' };
-
- /* Zero the related information */
- NdisZeroMemory(result, 80);
- NdisZeroMemory(local, 80);
- NdisZeroMemory(KeyCounter, 32);
-
- for (i = 0; i < 32; i++) {
- /* copy the local MAC address */
- COPY_MAC_ADDR(local, macAddr);
- curr = MAC_ADDR_LEN;
-
- /* concatenate the current time */
- NdisGetSystemUpTime(&CurrentTime);
- NdisMoveMemory(&local[curr], &CurrentTime, sizeof(CurrentTime));
- curr += sizeof(CurrentTime);
-
- /* concatenate the last result */
- NdisMoveMemory(&local[curr], result, 32);
- curr += 32;
-
- /* concatenate a variable */
- NdisMoveMemory(&local[curr], &i, 2);
- curr += 2;
-
- /* calculate the result */
- PRF(KeyCounter, 32, prefix, 12, local, curr, result, 32);
- }
-
- NdisMoveMemory(random, result, 32);
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Build cipher suite in RSN-IE.
- It only shall be called by RTMPMakeRSNIE.
-
- Arguments:
- pAd - pointer to our pAdapter context
- ElementID - indicate the WPA1 or WPA2
- WepStatus - indicate the encryption type
- bMixCipher - a boolean to indicate the pairwise cipher and group
- cipher are the same or not
-
- Return Value:
-
- Note:
-
- ========================================================================
-*/
-static void RTMPMakeRsnIeCipher(struct rt_rtmp_adapter *pAd,
- u8 ElementID,
- u32 WepStatus,
- IN BOOLEAN bMixCipher,
- u8 FlexibleCipher,
- u8 *pRsnIe, u8 * rsn_len)
-{
- u8 PairwiseCnt;
-
- *rsn_len = 0;
-
- /* decide WPA2 or WPA1 */
- if (ElementID == Wpa2Ie) {
- struct rt_rsnie2 *pRsnie_cipher = (struct rt_rsnie2 *)pRsnIe;
-
- /* Assign the verson as 1 */
- pRsnie_cipher->version = 1;
-
- switch (WepStatus) {
- /* TKIP mode */
- case Ndis802_11Encryption2Enabled:
- NdisMoveMemory(pRsnie_cipher->mcast, OUI_WPA2_TKIP, 4);
- pRsnie_cipher->ucount = 1;
- NdisMoveMemory(pRsnie_cipher->ucast[0].oui,
- OUI_WPA2_TKIP, 4);
- *rsn_len = sizeof(struct rt_rsnie2);
- break;
-
- /* AES mode */
- case Ndis802_11Encryption3Enabled:
- if (bMixCipher)
- NdisMoveMemory(pRsnie_cipher->mcast,
- OUI_WPA2_TKIP, 4);
- else
- NdisMoveMemory(pRsnie_cipher->mcast,
- OUI_WPA2_CCMP, 4);
- pRsnie_cipher->ucount = 1;
- NdisMoveMemory(pRsnie_cipher->ucast[0].oui,
- OUI_WPA2_CCMP, 4);
- *rsn_len = sizeof(struct rt_rsnie2);
- break;
-
- /* TKIP-AES mix mode */
- case Ndis802_11Encryption4Enabled:
- NdisMoveMemory(pRsnie_cipher->mcast, OUI_WPA2_TKIP, 4);
-
- PairwiseCnt = 1;
- /* Insert WPA2 TKIP as the first pairwise cipher */
- if (MIX_CIPHER_WPA2_TKIP_ON(FlexibleCipher)) {
- NdisMoveMemory(pRsnie_cipher->ucast[0].oui,
- OUI_WPA2_TKIP, 4);
- /* Insert WPA2 AES as the secondary pairwise cipher */
- if (MIX_CIPHER_WPA2_AES_ON(FlexibleCipher)) {
- NdisMoveMemory(pRsnie_cipher->ucast[0].
- oui + 4, OUI_WPA2_CCMP,
- 4);
- PairwiseCnt = 2;
- }
- } else {
- /* Insert WPA2 AES as the first pairwise cipher */
- NdisMoveMemory(pRsnie_cipher->ucast[0].oui,
- OUI_WPA2_CCMP, 4);
- }
-
- pRsnie_cipher->ucount = PairwiseCnt;
- *rsn_len = sizeof(struct rt_rsnie2) + (4 * (PairwiseCnt - 1));
- break;
- }
-
- if ((pAd->OpMode == OPMODE_STA) &&
- (pAd->StaCfg.GroupCipher != Ndis802_11Encryption2Enabled) &&
- (pAd->StaCfg.GroupCipher != Ndis802_11Encryption3Enabled)) {
- u32 GroupCipher = pAd->StaCfg.GroupCipher;
- switch (GroupCipher) {
- case Ndis802_11GroupWEP40Enabled:
- NdisMoveMemory(pRsnie_cipher->mcast,
- OUI_WPA2_WEP40, 4);
- break;
- case Ndis802_11GroupWEP104Enabled:
- NdisMoveMemory(pRsnie_cipher->mcast,
- OUI_WPA2_WEP104, 4);
- break;
- }
- }
- /* swap for big-endian platform */
- pRsnie_cipher->version = cpu2le16(pRsnie_cipher->version);
- pRsnie_cipher->ucount = cpu2le16(pRsnie_cipher->ucount);
- } else {
- struct rt_rsnie *pRsnie_cipher = (struct rt_rsnie *)pRsnIe;
-
- /* Assign OUI and version */
- NdisMoveMemory(pRsnie_cipher->oui, OUI_WPA_VERSION, 4);
- pRsnie_cipher->version = 1;
-
- switch (WepStatus) {
- /* TKIP mode */
- case Ndis802_11Encryption2Enabled:
- NdisMoveMemory(pRsnie_cipher->mcast, OUI_WPA_TKIP, 4);
- pRsnie_cipher->ucount = 1;
- NdisMoveMemory(pRsnie_cipher->ucast[0].oui,
- OUI_WPA_TKIP, 4);
- *rsn_len = sizeof(struct rt_rsnie);
- break;
-
- /* AES mode */
- case Ndis802_11Encryption3Enabled:
- if (bMixCipher)
- NdisMoveMemory(pRsnie_cipher->mcast,
- OUI_WPA_TKIP, 4);
- else
- NdisMoveMemory(pRsnie_cipher->mcast,
- OUI_WPA_CCMP, 4);
- pRsnie_cipher->ucount = 1;
- NdisMoveMemory(pRsnie_cipher->ucast[0].oui,
- OUI_WPA_CCMP, 4);
- *rsn_len = sizeof(struct rt_rsnie);
- break;
-
- /* TKIP-AES mix mode */
- case Ndis802_11Encryption4Enabled:
- NdisMoveMemory(pRsnie_cipher->mcast, OUI_WPA_TKIP, 4);
-
- PairwiseCnt = 1;
- /* Insert WPA TKIP as the first pairwise cipher */
- if (MIX_CIPHER_WPA_TKIP_ON(FlexibleCipher)) {
- NdisMoveMemory(pRsnie_cipher->ucast[0].oui,
- OUI_WPA_TKIP, 4);
- /* Insert WPA AES as the secondary pairwise cipher */
- if (MIX_CIPHER_WPA_AES_ON(FlexibleCipher)) {
- NdisMoveMemory(pRsnie_cipher->ucast[0].
- oui + 4, OUI_WPA_CCMP,
- 4);
- PairwiseCnt = 2;
- }
- } else {
- /* Insert WPA AES as the first pairwise cipher */
- NdisMoveMemory(pRsnie_cipher->ucast[0].oui,
- OUI_WPA_CCMP, 4);
- }
-
- pRsnie_cipher->ucount = PairwiseCnt;
- *rsn_len = sizeof(struct rt_rsnie) + (4 * (PairwiseCnt - 1));
- break;
- }
-
- if ((pAd->OpMode == OPMODE_STA) &&
- (pAd->StaCfg.GroupCipher != Ndis802_11Encryption2Enabled) &&
- (pAd->StaCfg.GroupCipher != Ndis802_11Encryption3Enabled)) {
- u32 GroupCipher = pAd->StaCfg.GroupCipher;
- switch (GroupCipher) {
- case Ndis802_11GroupWEP40Enabled:
- NdisMoveMemory(pRsnie_cipher->mcast,
- OUI_WPA_WEP40, 4);
- break;
- case Ndis802_11GroupWEP104Enabled:
- NdisMoveMemory(pRsnie_cipher->mcast,
- OUI_WPA_WEP104, 4);
- break;
- }
- }
- /* swap for big-endian platform */
- pRsnie_cipher->version = cpu2le16(pRsnie_cipher->version);
- pRsnie_cipher->ucount = cpu2le16(pRsnie_cipher->ucount);
- }
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Build AKM suite in RSN-IE.
- It only shall be called by RTMPMakeRSNIE.
-
- Arguments:
- pAd - pointer to our pAdapter context
- ElementID - indicate the WPA1 or WPA2
- AuthMode - indicate the authentication mode
- apidx - indicate the interface index
-
- Return Value:
-
- Note:
-
- ========================================================================
-*/
-static void RTMPMakeRsnIeAKM(struct rt_rtmp_adapter *pAd,
- u8 ElementID,
- u32 AuthMode,
- u8 apidx,
- u8 *pRsnIe, u8 * rsn_len)
-{
- struct rt_rsnie_auth *pRsnie_auth;
- u8 AkmCnt = 1; /* default as 1 */
-
- pRsnie_auth = (struct rt_rsnie_auth *) (pRsnIe + (*rsn_len));
-
- /* decide WPA2 or WPA1 */
- if (ElementID == Wpa2Ie) {
-
- switch (AuthMode) {
- case Ndis802_11AuthModeWPA2:
- case Ndis802_11AuthModeWPA1WPA2:
- NdisMoveMemory(pRsnie_auth->auth[0].oui,
- OUI_WPA2_8021X_AKM, 4);
- break;
-
- case Ndis802_11AuthModeWPA2PSK:
- case Ndis802_11AuthModeWPA1PSKWPA2PSK:
- NdisMoveMemory(pRsnie_auth->auth[0].oui,
- OUI_WPA2_PSK_AKM, 4);
- break;
- default:
- AkmCnt = 0;
- break;
-
- }
- } else {
- switch (AuthMode) {
- case Ndis802_11AuthModeWPA:
- case Ndis802_11AuthModeWPA1WPA2:
- NdisMoveMemory(pRsnie_auth->auth[0].oui,
- OUI_WPA_8021X_AKM, 4);
- break;
-
- case Ndis802_11AuthModeWPAPSK:
- case Ndis802_11AuthModeWPA1PSKWPA2PSK:
- NdisMoveMemory(pRsnie_auth->auth[0].oui,
- OUI_WPA_PSK_AKM, 4);
- break;
-
- case Ndis802_11AuthModeWPANone:
- NdisMoveMemory(pRsnie_auth->auth[0].oui,
- OUI_WPA_NONE_AKM, 4);
- break;
- default:
- AkmCnt = 0;
- break;
- }
- }
-
- pRsnie_auth->acount = AkmCnt;
- pRsnie_auth->acount = cpu2le16(pRsnie_auth->acount);
-
- /* update current RSNIE length */
- (*rsn_len) += (sizeof(struct rt_rsnie_auth) + (4 * (AkmCnt - 1)));
-
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Build capability in RSN-IE.
- It only shall be called by RTMPMakeRSNIE.
-
- Arguments:
- pAd - pointer to our pAdapter context
- ElementID - indicate the WPA1 or WPA2
- apidx - indicate the interface index
-
- Return Value:
-
- Note:
-
- ========================================================================
-*/
-static void RTMPMakeRsnIeCap(struct rt_rtmp_adapter *pAd,
- u8 ElementID,
- u8 apidx,
- u8 *pRsnIe, u8 * rsn_len)
-{
- RSN_CAPABILITIES *pRSN_Cap;
-
- /* it could be ignored in WPA1 mode */
- if (ElementID == WpaIe)
- return;
-
- pRSN_Cap = (RSN_CAPABILITIES *) (pRsnIe + (*rsn_len));
-
- pRSN_Cap->word = cpu2le16(pRSN_Cap->word);
-
- (*rsn_len) += sizeof(RSN_CAPABILITIES); /* update current RSNIE length */
-
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Build RSN IE context. It is not included element-ID and length.
-
- Arguments:
- pAd - pointer to our pAdapter context
- AuthMode - indicate the authentication mode
- WepStatus - indicate the encryption type
- apidx - indicate the interface index
-
- Return Value:
-
- Note:
-
- ========================================================================
-*/
-void RTMPMakeRSNIE(struct rt_rtmp_adapter *pAd,
- u32 AuthMode, u32 WepStatus, u8 apidx)
-{
- u8 *pRsnIe = NULL; /* primary RSNIE */
- u8 *rsnielen_cur_p = 0; /* the length of the primary RSNIE */
- u8 *rsnielen_ex_cur_p = 0; /* the length of the secondary RSNIE */
- u8 PrimaryRsnie;
- BOOLEAN bMixCipher = FALSE; /* indicate the pairwise and group cipher are different */
- u8 p_offset;
- WPA_MIX_PAIR_CIPHER FlexibleCipher = WPA_TKIPAES_WPA2_TKIPAES; /* it provide the more flexible cipher combination in WPA-WPA2 and TKIPAES mode */
-
- rsnielen_cur_p = NULL;
- rsnielen_ex_cur_p = NULL;
-
- {
- {
- if (pAd->StaCfg.WpaSupplicantUP !=
- WPA_SUPPLICANT_DISABLE) {
- if (AuthMode < Ndis802_11AuthModeWPA)
- return;
- } else {
- /* Support WPAPSK or WPA2PSK in STA-Infra mode */
- /* Support WPANone in STA-Adhoc mode */
- if ((AuthMode != Ndis802_11AuthModeWPAPSK) &&
- (AuthMode != Ndis802_11AuthModeWPA2PSK) &&
- (AuthMode != Ndis802_11AuthModeWPANone)
- )
- return;
- }
-
- DBGPRINT(RT_DEBUG_TRACE, ("==> RTMPMakeRSNIE(STA)\n"));
-
- /* Zero RSNIE context */
- pAd->StaCfg.RSNIE_Len = 0;
- NdisZeroMemory(pAd->StaCfg.RSN_IE, MAX_LEN_OF_RSNIE);
-
- /* Pointer to RSNIE */
- rsnielen_cur_p = &pAd->StaCfg.RSNIE_Len;
- pRsnIe = pAd->StaCfg.RSN_IE;
-
- bMixCipher = pAd->StaCfg.bMixCipher;
- }
- }
-
- /* indicate primary RSNIE as WPA or WPA2 */
- if ((AuthMode == Ndis802_11AuthModeWPA) ||
- (AuthMode == Ndis802_11AuthModeWPAPSK) ||
- (AuthMode == Ndis802_11AuthModeWPANone) ||
- (AuthMode == Ndis802_11AuthModeWPA1WPA2) ||
- (AuthMode == Ndis802_11AuthModeWPA1PSKWPA2PSK))
- PrimaryRsnie = WpaIe;
- else
- PrimaryRsnie = Wpa2Ie;
-
- {
- /* Build the primary RSNIE */
- /* 1. insert cipher suite */
- RTMPMakeRsnIeCipher(pAd, PrimaryRsnie, WepStatus, bMixCipher,
- FlexibleCipher, pRsnIe, &p_offset);
-
- /* 2. insert AKM */
- RTMPMakeRsnIeAKM(pAd, PrimaryRsnie, AuthMode, apidx, pRsnIe,
- &p_offset);
-
- /* 3. insert capability */
- RTMPMakeRsnIeCap(pAd, PrimaryRsnie, apidx, pRsnIe, &p_offset);
- }
-
- /* 4. update the RSNIE length */
- *rsnielen_cur_p = p_offset;
-
- hex_dump("The primary RSNIE", pRsnIe, (*rsnielen_cur_p));
-
-}
-
-/*
- ==========================================================================
- Description:
- Check whether the received frame is EAP frame.
-
- Arguments:
- pAd - pointer to our pAdapter context
- pEntry - pointer to active entry
- pData - the received frame
- DataByteCount - the received frame's length
- FromWhichBSSID - indicate the interface index
-
- Return:
- TRUE - This frame is EAP frame
- FALSE - otherwise
- ==========================================================================
-*/
-BOOLEAN RTMPCheckWPAframe(struct rt_rtmp_adapter *pAd,
- struct rt_mac_table_entry *pEntry,
- u8 *pData,
- unsigned long DataByteCount, u8 FromWhichBSSID)
-{
- unsigned long Body_len;
- BOOLEAN Cancelled;
-
- if (DataByteCount < (LENGTH_802_1_H + LENGTH_EAPOL_H))
- return FALSE;
-
- /* Skip LLC header */
- if (NdisEqualMemory(SNAP_802_1H, pData, 6) ||
- /* Cisco 1200 AP may send packet with SNAP_BRIDGE_TUNNEL */
- NdisEqualMemory(SNAP_BRIDGE_TUNNEL, pData, 6)) {
- pData += 6;
- }
- /* Skip 2-bytes EAPoL type */
- if (NdisEqualMemory(EAPOL, pData, 2)) {
- pData += 2;
- } else
- return FALSE;
-
- switch (*(pData + 1)) {
- case EAPPacket:
- Body_len = (*(pData + 2) << 8) | (*(pData + 3));
- DBGPRINT(RT_DEBUG_TRACE,
- ("Receive EAP-Packet frame, TYPE = 0, Length = %ld\n",
- Body_len));
- break;
- case EAPOLStart:
- DBGPRINT(RT_DEBUG_TRACE,
- ("Receive EAPOL-Start frame, TYPE = 1 \n"));
- if (pEntry->EnqueueEapolStartTimerRunning !=
- EAPOL_START_DISABLE) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("Cancel the EnqueueEapolStartTimerRunning \n"));
- RTMPCancelTimer(&pEntry->EnqueueStartForPSKTimer,
- &Cancelled);
- pEntry->EnqueueEapolStartTimerRunning =
- EAPOL_START_DISABLE;
- }
- break;
- case EAPOLLogoff:
- DBGPRINT(RT_DEBUG_TRACE,
- ("Receive EAPOLLogoff frame, TYPE = 2 \n"));
- break;
- case EAPOLKey:
- Body_len = (*(pData + 2) << 8) | (*(pData + 3));
- DBGPRINT(RT_DEBUG_TRACE,
- ("Receive EAPOL-Key frame, TYPE = 3, Length = %ld\n",
- Body_len));
- break;
- case EAPOLASFAlert:
- DBGPRINT(RT_DEBUG_TRACE,
- ("Receive EAPOLASFAlert frame, TYPE = 4 \n"));
- break;
- default:
- return FALSE;
-
- }
- return TRUE;
-}
-
-/*
- ==========================================================================
- Description:
- Report the EAP message type
-
- Arguments:
- msg - EAPOL_PAIR_MSG_1
- EAPOL_PAIR_MSG_2
- EAPOL_PAIR_MSG_3
- EAPOL_PAIR_MSG_4
- EAPOL_GROUP_MSG_1
- EAPOL_GROUP_MSG_2
-
- Return:
- message type string
-
- ==========================================================================
-*/
-char *GetEapolMsgType(char msg)
-{
- if (msg == EAPOL_PAIR_MSG_1)
- return "Pairwise Message 1";
- else if (msg == EAPOL_PAIR_MSG_2)
- return "Pairwise Message 2";
- else if (msg == EAPOL_PAIR_MSG_3)
- return "Pairwise Message 3";
- else if (msg == EAPOL_PAIR_MSG_4)
- return "Pairwise Message 4";
- else if (msg == EAPOL_GROUP_MSG_1)
- return "Group Message 1";
- else if (msg == EAPOL_GROUP_MSG_2)
- return "Group Message 2";
- else
- return "Invalid Message";
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Check Sanity RSN IE of EAPoL message
-
- Arguments:
-
- Return Value:
-
- ========================================================================
-*/
-BOOLEAN RTMPCheckRSNIE(struct rt_rtmp_adapter *pAd,
- u8 *pData,
- u8 DataLen,
- struct rt_mac_table_entry *pEntry, u8 * Offset)
-{
- u8 *pVIE;
- u8 len;
- struct rt_eid * pEid;
- BOOLEAN result = FALSE;
-
- pVIE = pData;
- len = DataLen;
- *Offset = 0;
-
- while (len > sizeof(struct rt_rsnie2)) {
- pEid = (struct rt_eid *) pVIE;
- /* WPA RSN IE */
- if ((pEid->Eid == IE_WPA)
- && (NdisEqualMemory(pEid->Octet, WPA_OUI, 4))) {
- if ((pEntry->AuthMode == Ndis802_11AuthModeWPA
- || pEntry->AuthMode == Ndis802_11AuthModeWPAPSK)
- &&
- (NdisEqualMemory
- (pVIE, pEntry->RSN_IE, pEntry->RSNIE_Len))
- && (pEntry->RSNIE_Len == (pEid->Len + 2))) {
- result = TRUE;
- }
-
- *Offset += (pEid->Len + 2);
- }
- /* WPA2 RSN IE */
- else if ((pEid->Eid == IE_RSN)
- && (NdisEqualMemory(pEid->Octet + 2, RSN_OUI, 3))) {
- if ((pEntry->AuthMode == Ndis802_11AuthModeWPA2
- || pEntry->AuthMode == Ndis802_11AuthModeWPA2PSK)
- && (pEid->Eid == pEntry->RSN_IE[0])
- && ((pEid->Len + 2) >= pEntry->RSNIE_Len)
- &&
- (NdisEqualMemory
- (pEid->Octet, &pEntry->RSN_IE[2],
- pEntry->RSNIE_Len - 2))) {
-
- result = TRUE;
- }
-
- *Offset += (pEid->Len + 2);
- } else {
- break;
- }
-
- pVIE += (pEid->Len + 2);
- len -= (pEid->Len + 2);
- }
-
- return result;
-
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Parse KEYDATA field. KEYDATA[] May contain 2 RSN IE and optionally GTK.
- GTK is encaptulated in KDE format at p.83 802.11i D10
-
- Arguments:
-
- Return Value:
-
- Note:
- 802.11i D10
-
- ========================================================================
-*/
-BOOLEAN RTMPParseEapolKeyData(struct rt_rtmp_adapter *pAd,
- u8 *pKeyData,
- u8 KeyDataLen,
- u8 GroupKeyIndex,
- u8 MsgType,
- IN BOOLEAN bWPA2, struct rt_mac_table_entry *pEntry)
-{
- struct rt_kde_encap * pKDE = NULL;
- u8 *pMyKeyData = pKeyData;
- u8 KeyDataLength = KeyDataLen;
- u8 GTKLEN = 0;
- u8 DefaultIdx = 0;
- u8 skip_offset;
-
- /* Verify The RSN IE contained in pairewise_msg_2 && pairewise_msg_3 and skip it */
- if (MsgType == EAPOL_PAIR_MSG_2 || MsgType == EAPOL_PAIR_MSG_3) {
- /* Check RSN IE whether it is WPA2/WPA2PSK */
- if (!RTMPCheckRSNIE
- (pAd, pKeyData, KeyDataLen, pEntry, &skip_offset)) {
- /* send wireless event - for RSN IE different */
- if (pAd->CommonCfg.bWirelessEvent)
- RTMPSendWirelessEvent(pAd,
- IW_RSNIE_DIFF_EVENT_FLAG,
- pEntry->Addr,
- pEntry->apidx, 0);
-
- DBGPRINT(RT_DEBUG_ERROR,
- ("RSN_IE Different in msg %d of 4-way handshake!\n",
- MsgType));
- hex_dump("Receive RSN_IE ", pKeyData, KeyDataLen);
- hex_dump("Desired RSN_IE ", pEntry->RSN_IE,
- pEntry->RSNIE_Len);
-
- return FALSE;
- } else {
- if (bWPA2 && MsgType == EAPOL_PAIR_MSG_3) {
- WpaShowAllsuite(pMyKeyData, skip_offset);
-
- /* skip RSN IE */
- pMyKeyData += skip_offset;
- KeyDataLength -= skip_offset;
- DBGPRINT(RT_DEBUG_TRACE,
- ("RTMPParseEapolKeyData ==> WPA2/WPA2PSK RSN IE matched in Msg 3, Length(%d) \n",
- skip_offset));
- } else
- return TRUE;
- }
- }
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("RTMPParseEapolKeyData ==> KeyDataLength %d without RSN_IE \n",
- KeyDataLength));
- /*hex_dump("remain data", pMyKeyData, KeyDataLength); */
-
- /* Parse EKD format in pairwise_msg_3_WPA2 && group_msg_1_WPA2 */
- if (bWPA2
- && (MsgType == EAPOL_PAIR_MSG_3 || MsgType == EAPOL_GROUP_MSG_1)) {
- if (KeyDataLength >= 8) /* KDE format exclude GTK length */
- {
- pKDE = (struct rt_kde_encap *) pMyKeyData;
-
- DefaultIdx = pKDE->GTKEncap.Kid;
-
- /* Sanity check - KED length */
- if (KeyDataLength < (pKDE->Len + 2)) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("ERROR: The len from KDE is too short \n"));
- return FALSE;
- }
- /* Get GTK length - refer to IEEE 802.11i-2004 p.82 */
- GTKLEN = pKDE->Len - 6;
- if (GTKLEN < LEN_AES_KEY) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("ERROR: GTK Key length is too short (%d) \n",
- GTKLEN));
- return FALSE;
- }
-
- } else {
- DBGPRINT(RT_DEBUG_ERROR,
- ("ERROR: KDE format length is too short \n"));
- return FALSE;
- }
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("GTK in KDE format ,DefaultKeyID=%d, KeyLen=%d \n",
- DefaultIdx, GTKLEN));
- /* skip it */
- pMyKeyData += 8;
- KeyDataLength -= 8;
-
- } else if (!bWPA2 && MsgType == EAPOL_GROUP_MSG_1) {
- DefaultIdx = GroupKeyIndex;
- DBGPRINT(RT_DEBUG_TRACE,
- ("GTK DefaultKeyID=%d \n", DefaultIdx));
- }
- /* Sanity check - shared key index must be 1 ~ 3 */
- if (DefaultIdx < 1 || DefaultIdx > 3) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("ERROR: GTK Key index(%d) is invalid in %s %s \n",
- DefaultIdx, ((bWPA2) ? "WPA2" : "WPA"),
- GetEapolMsgType(MsgType)));
- return FALSE;
- }
-
- {
- struct rt_cipher_key *pSharedKey;
-
- /* set key material, TxMic and RxMic */
- NdisMoveMemory(pAd->StaCfg.GTK, pMyKeyData, 32);
- pAd->StaCfg.DefaultKeyId = DefaultIdx;
-
- pSharedKey = &pAd->SharedKey[BSS0][pAd->StaCfg.DefaultKeyId];
-
- /* Prepare pair-wise key information into shared key table */
- NdisZeroMemory(pSharedKey, sizeof(struct rt_cipher_key));
- pSharedKey->KeyLen = LEN_TKIP_EK;
- NdisMoveMemory(pSharedKey->Key, pAd->StaCfg.GTK, LEN_TKIP_EK);
- NdisMoveMemory(pSharedKey->RxMic, &pAd->StaCfg.GTK[16],
- LEN_TKIP_RXMICK);
- NdisMoveMemory(pSharedKey->TxMic, &pAd->StaCfg.GTK[24],
- LEN_TKIP_TXMICK);
-
- /* Update Shared Key CipherAlg */
- pSharedKey->CipherAlg = CIPHER_NONE;
- if (pAd->StaCfg.GroupCipher == Ndis802_11Encryption2Enabled)
- pSharedKey->CipherAlg = CIPHER_TKIP;
- else if (pAd->StaCfg.GroupCipher ==
- Ndis802_11Encryption3Enabled)
- pSharedKey->CipherAlg = CIPHER_AES;
- else if (pAd->StaCfg.GroupCipher == Ndis802_11GroupWEP40Enabled)
- pSharedKey->CipherAlg = CIPHER_WEP64;
- else if (pAd->StaCfg.GroupCipher ==
- Ndis802_11GroupWEP104Enabled)
- pSharedKey->CipherAlg = CIPHER_WEP128;
-
- /* Update group key information to ASIC Shared Key Table */
- AsicAddSharedKeyEntry(pAd,
- BSS0,
- pAd->StaCfg.DefaultKeyId,
- pSharedKey->CipherAlg,
- pSharedKey->Key,
- pSharedKey->TxMic, pSharedKey->RxMic);
-
- /* Update ASIC WCID attribute table and IVEIV table */
- RTMPAddWcidAttributeEntry(pAd,
- BSS0,
- pAd->StaCfg.DefaultKeyId,
- pSharedKey->CipherAlg, NULL);
- }
-
- return TRUE;
-
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Construct EAPoL message for WPA handshaking
- Its format is below,
-
- +--------------------+
- | Protocol Version | 1 octet
- +--------------------+
- | Protocol Type | 1 octet
- +--------------------+
- | Body Length | 2 octets
- +--------------------+
- | Descriptor Type | 1 octet
- +--------------------+
- | Key Information | 2 octets
- +--------------------+
- | Key Length | 1 octet
- +--------------------+
- | Key Repaly Counter | 8 octets
- +--------------------+
- | Key Nonce | 32 octets
- +--------------------+
- | Key IV | 16 octets
- +--------------------+
- | Key RSC | 8 octets
- +--------------------+
- | Key ID or Reserved | 8 octets
- +--------------------+
- | Key MIC | 16 octets
- +--------------------+
- | Key Data Length | 2 octets
- +--------------------+
- | Key Data | n octets
- +--------------------+
-
- Arguments:
- pAd Pointer to our adapter
-
- Return Value:
- None
-
- Note:
-
- ========================================================================
-*/
-void ConstructEapolMsg(struct rt_mac_table_entry *pEntry,
- u8 GroupKeyWepStatus,
- u8 MsgType,
- u8 DefaultKeyIdx,
- u8 * KeyNonce,
- u8 * TxRSC,
- u8 * GTK,
- u8 * RSNIE,
- u8 RSNIE_Len, struct rt_eapol_packet * pMsg)
-{
- BOOLEAN bWPA2 = FALSE;
- u8 KeyDescVer;
-
- /* Choose WPA2 or not */
- if ((pEntry->AuthMode == Ndis802_11AuthModeWPA2) ||
- (pEntry->AuthMode == Ndis802_11AuthModeWPA2PSK))
- bWPA2 = TRUE;
-
- /* Init Packet and Fill header */
- pMsg->ProVer = EAPOL_VER;
- pMsg->ProType = EAPOLKey;
-
- /* Default 95 bytes, the EAPoL-Key descriptor exclude Key-data field */
- SET_u16_TO_ARRARY(pMsg->Body_Len, LEN_EAPOL_KEY_MSG);
-
- /* Fill in EAPoL descriptor */
- if (bWPA2)
- pMsg->KeyDesc.Type = WPA2_KEY_DESC;
- else
- pMsg->KeyDesc.Type = WPA1_KEY_DESC;
-
- /* Key Descriptor Version (bits 0-2) specifies the key descriptor version type */
- {
- /* Fill in Key information, refer to IEEE Std 802.11i-2004 page 78 */
- /* When either the pairwise or the group cipher is AES, the DESC_TYPE_AES(2) shall be used. */
- KeyDescVer =
- (((pEntry->WepStatus == Ndis802_11Encryption3Enabled)
- || (GroupKeyWepStatus ==
- Ndis802_11Encryption3Enabled)) ? (DESC_TYPE_AES)
- : (DESC_TYPE_TKIP));
- }
-
- pMsg->KeyDesc.KeyInfo.KeyDescVer = KeyDescVer;
-
- /* Specify Key Type as Group(0) or Pairwise(1) */
- if (MsgType >= EAPOL_GROUP_MSG_1)
- pMsg->KeyDesc.KeyInfo.KeyType = GROUPKEY;
- else
- pMsg->KeyDesc.KeyInfo.KeyType = PAIRWISEKEY;
-
- /* Specify Key Index, only group_msg1_WPA1 */
- if (!bWPA2 && (MsgType >= EAPOL_GROUP_MSG_1))
- pMsg->KeyDesc.KeyInfo.KeyIndex = DefaultKeyIdx;
-
- if (MsgType == EAPOL_PAIR_MSG_3)
- pMsg->KeyDesc.KeyInfo.Install = 1;
-
- if ((MsgType == EAPOL_PAIR_MSG_1) || (MsgType == EAPOL_PAIR_MSG_3)
- || (MsgType == EAPOL_GROUP_MSG_1))
- pMsg->KeyDesc.KeyInfo.KeyAck = 1;
-
- if (MsgType != EAPOL_PAIR_MSG_1)
- pMsg->KeyDesc.KeyInfo.KeyMic = 1;
-
- if ((bWPA2 && (MsgType >= EAPOL_PAIR_MSG_3)) ||
- (!bWPA2 && (MsgType >= EAPOL_GROUP_MSG_1))) {
- pMsg->KeyDesc.KeyInfo.Secure = 1;
- }
-
- if (bWPA2 && ((MsgType == EAPOL_PAIR_MSG_3) ||
- (MsgType == EAPOL_GROUP_MSG_1))) {
- pMsg->KeyDesc.KeyInfo.EKD_DL = 1;
- }
- /* key Information element has done. */
- *(u16 *) (&pMsg->KeyDesc.KeyInfo) =
- cpu2le16(*(u16 *) (&pMsg->KeyDesc.KeyInfo));
-
- /* Fill in Key Length */
- {
- if (MsgType >= EAPOL_GROUP_MSG_1) {
- /* the length of group key cipher */
- pMsg->KeyDesc.KeyLength[1] =
- ((GroupKeyWepStatus ==
- Ndis802_11Encryption2Enabled) ? TKIP_GTK_LENGTH :
- LEN_AES_KEY);
- } else {
- /* the length of pairwise key cipher */
- pMsg->KeyDesc.KeyLength[1] =
- ((pEntry->WepStatus ==
- Ndis802_11Encryption2Enabled) ? LEN_TKIP_KEY :
- LEN_AES_KEY);
- }
- }
-
- /* Fill in replay counter */
- NdisMoveMemory(pMsg->KeyDesc.ReplayCounter, pEntry->R_Counter,
- LEN_KEY_DESC_REPLAY);
-
- /* Fill Key Nonce field */
- /* ANonce : pairwise_msg1 & pairwise_msg3 */
- /* SNonce : pairwise_msg2 */
- /* GNonce : group_msg1_wpa1 */
- if ((MsgType <= EAPOL_PAIR_MSG_3)
- || ((!bWPA2 && (MsgType == EAPOL_GROUP_MSG_1))))
- NdisMoveMemory(pMsg->KeyDesc.KeyNonce, KeyNonce,
- LEN_KEY_DESC_NONCE);
-
- /* Fill key IV - WPA2 as 0, WPA1 as random */
- if (!bWPA2 && (MsgType == EAPOL_GROUP_MSG_1)) {
- /* Suggest IV be random number plus some number, */
- NdisMoveMemory(pMsg->KeyDesc.KeyIv, &KeyNonce[16],
- LEN_KEY_DESC_IV);
- pMsg->KeyDesc.KeyIv[15] += 2;
- }
- /* Fill Key RSC field */
- /* It contains the RSC for the GTK being installed. */
- if ((MsgType == EAPOL_PAIR_MSG_3 && bWPA2)
- || (MsgType == EAPOL_GROUP_MSG_1)) {
- NdisMoveMemory(pMsg->KeyDesc.KeyRsc, TxRSC, 6);
- }
- /* Clear Key MIC field for MIC calculation later */
- NdisZeroMemory(pMsg->KeyDesc.KeyMic, LEN_KEY_DESC_MIC);
-
- ConstructEapolKeyData(pEntry,
- GroupKeyWepStatus,
- KeyDescVer,
- MsgType,
- DefaultKeyIdx, GTK, RSNIE, RSNIE_Len, pMsg);
-
- /* Calculate MIC and fill in KeyMic Field except Pairwise Msg 1. */
- if (MsgType != EAPOL_PAIR_MSG_1) {
- CalculateMIC(KeyDescVer, pEntry->PTK, pMsg);
- }
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("===> ConstructEapolMsg for %s %s\n",
- ((bWPA2) ? "WPA2" : "WPA"), GetEapolMsgType(MsgType)));
- DBGPRINT(RT_DEBUG_TRACE,
- (" Body length = %d \n",
- CONV_ARRARY_TO_u16(pMsg->Body_Len)));
- DBGPRINT(RT_DEBUG_TRACE,
- (" Key length = %d \n",
- CONV_ARRARY_TO_u16(pMsg->KeyDesc.KeyLength)));
-
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Construct the Key Data field of EAPoL message
-
- Arguments:
- pAd Pointer to our adapter
- Elem Message body
-
- Return Value:
- None
-
- Note:
-
- ========================================================================
-*/
-void ConstructEapolKeyData(struct rt_mac_table_entry *pEntry,
- u8 GroupKeyWepStatus,
- u8 keyDescVer,
- u8 MsgType,
- u8 DefaultKeyIdx,
- u8 * GTK,
- u8 * RSNIE,
- u8 RSNIE_LEN, struct rt_eapol_packet * pMsg)
-{
- u8 *mpool, *Key_Data, *Rc4GTK;
- u8 ekey[(LEN_KEY_DESC_IV + LEN_EAP_EK)];
- unsigned long data_offset;
- BOOLEAN bWPA2Capable = FALSE;
- struct rt_rtmp_adapter *pAd = pEntry->pAd;
- BOOLEAN GTK_Included = FALSE;
-
- /* Choose WPA2 or not */
- if ((pEntry->AuthMode == Ndis802_11AuthModeWPA2) ||
- (pEntry->AuthMode == Ndis802_11AuthModeWPA2PSK))
- bWPA2Capable = TRUE;
-
- if (MsgType == EAPOL_PAIR_MSG_1 ||
- MsgType == EAPOL_PAIR_MSG_4 || MsgType == EAPOL_GROUP_MSG_2)
- return;
-
- /* allocate memory pool */
- os_alloc_mem(NULL, (u8 **) & mpool, 1500);
-
- if (mpool == NULL)
- return;
-
- /* Rc4GTK Len = 512 */
- Rc4GTK = (u8 *) ROUND_UP(mpool, 4);
- /* Key_Data Len = 512 */
- Key_Data = (u8 *) ROUND_UP(Rc4GTK + 512, 4);
-
- NdisZeroMemory(Key_Data, 512);
- SET_u16_TO_ARRARY(pMsg->KeyDesc.KeyDataLen, 0);
- data_offset = 0;
-
- /* Encapsulate RSNIE in pairwise_msg2 & pairwise_msg3 */
- if (RSNIE_LEN
- && ((MsgType == EAPOL_PAIR_MSG_2)
- || (MsgType == EAPOL_PAIR_MSG_3))) {
- u8 *pmkid_ptr = NULL;
- u8 pmkid_len = 0;
-
- RTMPInsertRSNIE(&Key_Data[data_offset],
- &data_offset,
- RSNIE, RSNIE_LEN, pmkid_ptr, pmkid_len);
- }
-
- /* Encapsulate KDE format in pairwise_msg3_WPA2 & group_msg1_WPA2 */
- if (bWPA2Capable
- && ((MsgType == EAPOL_PAIR_MSG_3)
- || (MsgType == EAPOL_GROUP_MSG_1))) {
- /* Key Data Encapsulation (KDE) format - 802.11i-2004 Figure-43w and Table-20h */
- Key_Data[data_offset + 0] = 0xDD;
-
- if (GroupKeyWepStatus == Ndis802_11Encryption3Enabled) {
- Key_Data[data_offset + 1] = 0x16; /* 4+2+16(OUI+DataType+DataField) */
- } else {
- Key_Data[data_offset + 1] = 0x26; /* 4+2+32(OUI+DataType+DataField) */
- }
-
- Key_Data[data_offset + 2] = 0x00;
- Key_Data[data_offset + 3] = 0x0F;
- Key_Data[data_offset + 4] = 0xAC;
- Key_Data[data_offset + 5] = 0x01;
-
- /* GTK KDE format - 802.11i-2004 Figure-43x */
- Key_Data[data_offset + 6] = (DefaultKeyIdx & 0x03);
- Key_Data[data_offset + 7] = 0x00; /* Reserved Byte */
-
- data_offset += 8;
- }
-
- /* Encapsulate GTK */
- /* Only for pairwise_msg3_WPA2 and group_msg1 */
- if ((MsgType == EAPOL_PAIR_MSG_3 && bWPA2Capable)
- || (MsgType == EAPOL_GROUP_MSG_1)) {
- /* Fill in GTK */
- if (GroupKeyWepStatus == Ndis802_11Encryption3Enabled) {
- NdisMoveMemory(&Key_Data[data_offset], GTK,
- LEN_AES_KEY);
- data_offset += LEN_AES_KEY;
- } else {
- NdisMoveMemory(&Key_Data[data_offset], GTK,
- TKIP_GTK_LENGTH);
- data_offset += TKIP_GTK_LENGTH;
- }
-
- GTK_Included = TRUE;
- }
-
- /* This whole key-data field shall be encrypted if a GTK is included. */
- /* Encrypt the data material in key data field with KEK */
- if (GTK_Included) {
- /*hex_dump("GTK_Included", Key_Data, data_offset); */
-
- if ((keyDescVer == DESC_TYPE_AES)) {
- u8 remainder = 0;
- u8 pad_len = 0;
-
- /* Key Descriptor Version 2 or 3: AES key wrap, defined in IETF RFC 3394, */
- /* shall be used to encrypt the Key Data field using the KEK field from */
- /* the derived PTK. */
-
- /* If the Key Data field uses the NIST AES key wrap, then the Key Data field */
- /* shall be padded before encrypting if the key data length is less than 16 */
- /* octets or if it is not a multiple of 8. The padding consists of appending */
- /* a single octet 0xdd followed by zero or more 0x00 octets. */
- if ((remainder = data_offset & 0x07) != 0) {
- int i;
-
- pad_len = (8 - remainder);
- Key_Data[data_offset] = 0xDD;
- for (i = 1; i < pad_len; i++)
- Key_Data[data_offset + i] = 0;
-
- data_offset += pad_len;
- }
-
- AES_GTK_KEY_WRAP(&pEntry->PTK[16], Key_Data,
- data_offset, Rc4GTK);
- /* AES wrap function will grow 8 bytes in length */
- data_offset += 8;
- } else {
- /* Key Descriptor Version 1: ARC4 is used to encrypt the Key Data field
- using the KEK field from the derived PTK. */
-
- /* PREPARE Encrypted "Key DATA" field. (Encrypt GTK with RC4, usinf PTK[16]->[31] as Key, IV-field as IV) */
- /* put TxTsc in Key RSC field */
- pAd->PrivateInfo.FCSCRC32 = PPPINITFCS32; /*Init crc32. */
-
- /* ekey is the contanetion of IV-field, and PTK[16]->PTK[31] */
- NdisMoveMemory(ekey, pMsg->KeyDesc.KeyIv,
- LEN_KEY_DESC_IV);
- NdisMoveMemory(&ekey[LEN_KEY_DESC_IV], &pEntry->PTK[16],
- LEN_EAP_EK);
- ARCFOUR_INIT(&pAd->PrivateInfo.WEPCONTEXT, ekey, sizeof(ekey)); /*INIT SBOX, KEYLEN+3(IV) */
- pAd->PrivateInfo.FCSCRC32 =
- RTMP_CALC_FCS32(pAd->PrivateInfo.FCSCRC32, Key_Data,
- data_offset);
- WPAARCFOUR_ENCRYPT(&pAd->PrivateInfo.WEPCONTEXT, Rc4GTK,
- Key_Data, data_offset);
- }
-
- NdisMoveMemory(pMsg->KeyDesc.KeyData, Rc4GTK, data_offset);
- } else {
- NdisMoveMemory(pMsg->KeyDesc.KeyData, Key_Data, data_offset);
- }
-
- /* Update key data length field and total body length */
- SET_u16_TO_ARRARY(pMsg->KeyDesc.KeyDataLen, data_offset);
- INC_u16_TO_ARRARY(pMsg->Body_Len, data_offset);
-
- os_free_mem(NULL, mpool);
-
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Calcaulate MIC. It is used during 4-ways handsharking.
-
- Arguments:
- pAd - pointer to our pAdapter context
- PeerWepStatus - indicate the encryption type
-
- Return Value:
-
- Note:
-
- ========================================================================
-*/
-static void CalculateMIC(u8 KeyDescVer,
- u8 * PTK, struct rt_eapol_packet * pMsg)
-{
- u8 *OutBuffer;
- unsigned long FrameLen = 0;
- u8 mic[LEN_KEY_DESC_MIC];
- u8 digest[80];
-
- /* allocate memory for MIC calculation */
- os_alloc_mem(NULL, (u8 **) & OutBuffer, 512);
-
- if (OutBuffer == NULL) {
- DBGPRINT(RT_DEBUG_ERROR, ("CalculateMIC: no memory!\n"));
- return;
- }
- /* make a frame for calculating MIC. */
- MakeOutgoingFrame(OutBuffer, &FrameLen,
- CONV_ARRARY_TO_u16(pMsg->Body_Len) + 4, pMsg,
- END_OF_ARGS);
-
- NdisZeroMemory(mic, sizeof(mic));
-
- /* Calculate MIC */
- if (KeyDescVer == DESC_TYPE_AES) {
- HMAC_SHA1(PTK, LEN_EAP_MICK, OutBuffer, FrameLen, digest,
- SHA1_DIGEST_SIZE);
- NdisMoveMemory(mic, digest, LEN_KEY_DESC_MIC);
- } else {
- HMAC_MD5(PTK, LEN_EAP_MICK, OutBuffer, FrameLen, mic,
- MD5_DIGEST_SIZE);
- }
-
- /* store the calculated MIC */
- NdisMoveMemory(pMsg->KeyDesc.KeyMic, mic, LEN_KEY_DESC_MIC);
-
- os_free_mem(NULL, OutBuffer);
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Some received frames can't decrypt by Asic, so decrypt them by software.
-
- Arguments:
- pAd - pointer to our pAdapter context
- PeerWepStatus - indicate the encryption type
-
- Return Value:
- NDIS_STATUS_SUCCESS - decryption successful
- NDIS_STATUS_FAILURE - decryption failure
-
- ========================================================================
-*/
-int RTMPSoftDecryptBroadCastData(struct rt_rtmp_adapter *pAd,
- struct rt_rx_blk *pRxBlk,
- IN NDIS_802_11_ENCRYPTION_STATUS
- GroupCipher, struct rt_cipher_key *pShard_key)
-{
- struct rt_rxwi * pRxWI = pRxBlk->pRxWI;
-
- /* handle WEP decryption */
- if (GroupCipher == Ndis802_11Encryption1Enabled) {
- if (RTMPSoftDecryptWEP
- (pAd, pRxBlk->pData, pRxWI->MPDUtotalByteCount,
- pShard_key)) {
-
- /*Minus IV[4] & ICV[4] */
- pRxWI->MPDUtotalByteCount -= 8;
- } else {
- DBGPRINT(RT_DEBUG_ERROR,
- ("ERROR : Software decrypt WEP data fails.\n"));
- /* give up this frame */
- return NDIS_STATUS_FAILURE;
- }
- }
- /* handle TKIP decryption */
- else if (GroupCipher == Ndis802_11Encryption2Enabled) {
- if (RTMPSoftDecryptTKIP
- (pAd, pRxBlk->pData, pRxWI->MPDUtotalByteCount, 0,
- pShard_key)) {
-
- /*Minus 8 bytes MIC, 8 bytes IV/EIV, 4 bytes ICV */
- pRxWI->MPDUtotalByteCount -= 20;
- } else {
- DBGPRINT(RT_DEBUG_ERROR,
- ("ERROR : RTMPSoftDecryptTKIP Failed\n"));
- /* give up this frame */
- return NDIS_STATUS_FAILURE;
- }
- }
- /* handle AES decryption */
- else if (GroupCipher == Ndis802_11Encryption3Enabled) {
- if (RTMPSoftDecryptAES
- (pAd, pRxBlk->pData, pRxWI->MPDUtotalByteCount,
- pShard_key)) {
-
- /*8 bytes MIC, 8 bytes IV/EIV (CCMP Header) */
- pRxWI->MPDUtotalByteCount -= 16;
- } else {
- DBGPRINT(RT_DEBUG_ERROR,
- ("ERROR : RTMPSoftDecryptAES Failed\n"));
- /* give up this frame */
- return NDIS_STATUS_FAILURE;
- }
- } else {
- /* give up this frame */
- return NDIS_STATUS_FAILURE;
- }
-
- return NDIS_STATUS_SUCCESS;
-
-}
-
-u8 *GetSuiteFromRSNIE(u8 *rsnie,
- u32 rsnie_len, u8 type, u8 * count)
-{
- struct rt_eid * pEid;
- int len;
- u8 *pBuf;
- int offset = 0;
- struct rt_rsnie_auth *pAkm;
- u16 acount;
- BOOLEAN isWPA2 = FALSE;
-
- pEid = (struct rt_eid *) rsnie;
- len = rsnie_len - 2; /* exclude IE and length */
- pBuf = (u8 *)& pEid->Octet[0];
-
- /* set default value */
- *count = 0;
-
- /* Check length */
- if ((len <= 0) || (pEid->Len != len)) {
- DBGPRINT_ERR("%s : The length is invalid\n", __func__);
- return NULL;
- }
- /* Check WPA or WPA2 */
- if (pEid->Eid == IE_WPA) {
- struct rt_rsnie *pRsnie = (struct rt_rsnie *)pBuf;
- u16 ucount;
-
- if (len < sizeof(struct rt_rsnie)) {
- DBGPRINT_ERR("%s : The length is too short for WPA\n", __func__);
- return NULL;
- }
- /* Get the count of pairwise cipher */
- ucount = cpu2le16(pRsnie->ucount);
- if (ucount > 2) {
- DBGPRINT_ERR("%s : The count(%d) of pairwise cipher is invlaid\n", __func__, ucount);
- return NULL;
- }
- /* Get the group cipher */
- if (type == GROUP_SUITE) {
- *count = 1;
- return pRsnie->mcast;
- }
- /* Get the pairwise cipher suite */
- else if (type == PAIRWISE_SUITE) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("%s : The count of pairwise cipher is %d\n",
- __func__, ucount));
- *count = ucount;
- return pRsnie->ucast[0].oui;
- }
-
- offset = sizeof(struct rt_rsnie) + (4 * (ucount - 1));
-
- } else if (pEid->Eid == IE_RSN) {
- struct rt_rsnie2 *pRsnie = (struct rt_rsnie2 *)pBuf;
- u16 ucount;
-
- isWPA2 = TRUE;
-
- if (len < sizeof(struct rt_rsnie2)) {
- DBGPRINT_ERR("%s : The length is too short for WPA2\n", __func__);
- return NULL;
- }
- /* Get the count of pairwise cipher */
- ucount = cpu2le16(pRsnie->ucount);
- if (ucount > 2) {
- DBGPRINT_ERR("%s : The count(%d) of pairwise cipher is invlaid\n", __func__, ucount);
- return NULL;
- }
- /* Get the group cipher */
- if (type == GROUP_SUITE) {
- *count = 1;
- return pRsnie->mcast;
- }
- /* Get the pairwise cipher suite */
- else if (type == PAIRWISE_SUITE) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("%s : The count of pairwise cipher is %d\n",
- __func__, ucount));
- *count = ucount;
- return pRsnie->ucast[0].oui;
- }
-
- offset = sizeof(struct rt_rsnie2) + (4 * (ucount - 1));
-
- } else {
- DBGPRINT_ERR("%s : Unknown IE (%d)\n", __func__, pEid->Eid);
- return NULL;
- }
-
- /* skip group cipher and pairwise cipher suite */
- pBuf += offset;
- len -= offset;
-
- if (len < sizeof(struct rt_rsnie_auth)) {
- DBGPRINT_ERR("%s : The length of RSNIE is too short\n", __func__);
- return NULL;
- }
- /* pointer to AKM count */
- pAkm = (struct rt_rsnie_auth *)pBuf;
-
- /* Get the count of pairwise cipher */
- acount = cpu2le16(pAkm->acount);
- if (acount > 2) {
- DBGPRINT_ERR("%s : The count(%d) of AKM is invlaid\n", __func__, acount);
- return NULL;
- }
- /* Get the AKM suite */
- if (type == AKM_SUITE) {
- DBGPRINT(RT_DEBUG_TRACE, ("%s : The count of AKM is %d\n",
- __func__, acount));
- *count = acount;
- return pAkm->auth[0].oui;
- }
- offset = sizeof(struct rt_rsnie_auth) + (4 * (acount - 1));
-
- pBuf += offset;
- len -= offset;
-
- /* The remaining length must larger than (RSN-Capability(2) + PMKID-Count(2) + PMKID(16~)) */
- if (len >= (sizeof(RSN_CAPABILITIES) + 2 + LEN_PMKID)) {
- /* Skip RSN capability and PMKID-Count */
- pBuf += (sizeof(RSN_CAPABILITIES) + 2);
- len -= (sizeof(RSN_CAPABILITIES) + 2);
-
- /* Get PMKID */
- if (type == PMKID_LIST) {
- *count = 1;
- return pBuf;
- }
- } else {
- DBGPRINT_ERR("%s : it can't get any more information beyond AKM \n", __func__);
- return NULL;
- }
-
- *count = 0;
- /*DBGPRINT_ERR(("%s : The type(%d) doesn't support \n", __func__, type)); */
- return NULL;
-
-}
-
-void WpaShowAllsuite(u8 *rsnie, u32 rsnie_len)
-{
- u8 *pSuite = NULL;
- u8 count;
-
- hex_dump("RSNIE", rsnie, rsnie_len);
-
- /* group cipher */
- pSuite = GetSuiteFromRSNIE(rsnie, rsnie_len, GROUP_SUITE, &count);
- if (pSuite != NULL) {
- hex_dump("group cipher", pSuite, 4 * count);
- }
- /* pairwise cipher */
- pSuite = GetSuiteFromRSNIE(rsnie, rsnie_len, PAIRWISE_SUITE, &count);
- if (pSuite != NULL) {
- hex_dump("pairwise cipher", pSuite, 4 * count);
- }
- /* AKM */
- pSuite = GetSuiteFromRSNIE(rsnie, rsnie_len, AKM_SUITE, &count);
- if (pSuite != NULL) {
- hex_dump("AKM suite", pSuite, 4 * count);
- }
- /* PMKID */
- pSuite = GetSuiteFromRSNIE(rsnie, rsnie_len, PMKID_LIST, &count);
- if (pSuite != NULL) {
- hex_dump("PMKID", pSuite, LEN_PMKID);
- }
-
-}
-
-void RTMPInsertRSNIE(u8 *pFrameBuf,
- unsigned long *pFrameLen,
- u8 *rsnie_ptr,
- u8 rsnie_len,
- u8 *pmkid_ptr, u8 pmkid_len)
-{
- u8 *pTmpBuf;
- unsigned long TempLen = 0;
- u8 extra_len = 0;
- u16 pmk_count = 0;
- u8 ie_num;
- u8 total_len = 0;
- u8 WPA2_OUI[3] = { 0x00, 0x0F, 0xAC };
-
- pTmpBuf = pFrameBuf;
-
- /* PMKID-List Must larger than 0 and the multiple of 16. */
- if (pmkid_len > 0 && ((pmkid_len & 0x0f) == 0)) {
- extra_len = sizeof(u16)+ pmkid_len;
-
- pmk_count = (pmkid_len >> 4);
- pmk_count = cpu2le16(pmk_count);
- } else {
- DBGPRINT(RT_DEBUG_WARN,
- ("%s : The length is PMKID-List is invalid (%d), so don't insert it.\n",
- __func__, pmkid_len));
- }
-
- if (rsnie_len != 0) {
- ie_num = IE_WPA;
- total_len = rsnie_len;
-
- if (NdisEqualMemory(rsnie_ptr + 2, WPA2_OUI, sizeof(WPA2_OUI))) {
- ie_num = IE_RSN;
- total_len += extra_len;
- }
-
- /* construct RSNIE body */
- MakeOutgoingFrame(pTmpBuf, &TempLen,
- 1, &ie_num,
- 1, &total_len,
- rsnie_len, rsnie_ptr, END_OF_ARGS);
-
- pTmpBuf += TempLen;
- *pFrameLen = *pFrameLen + TempLen;
-
- if (ie_num == IE_RSN) {
- /* Insert PMKID-List field */
- if (extra_len > 0) {
- MakeOutgoingFrame(pTmpBuf, &TempLen,
- 2, &pmk_count,
- pmkid_len, pmkid_ptr,
- END_OF_ARGS);
-
- pTmpBuf += TempLen;
- *pFrameLen = *pFrameLen + TempLen;
- }
- }
- }
-
- return;
-}
diff --git a/drivers/staging/rt2860/common/crypt_hmac.c b/drivers/staging/rt2860/common/crypt_hmac.c
deleted file mode 100644
index d7ab08e..0000000
--- a/drivers/staging/rt2860/common/crypt_hmac.c
+++ /dev/null
@@ -1,187 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************/
-
-#include "../crypt_hmac.h"
-
-#ifdef HMAC_SHA1_SUPPORT
-/*
-========================================================================
-Routine Description:
- HMAC using SHA1 hash function
-
-Arguments:
- key Secret key
- key_len The length of the key in bytes
- message Message context
- message_len The length of message in bytes
- macLen Request the length of message authentication code
-
-Return Value:
- mac Message authentication code
-
-Note:
- None
-========================================================================
-*/
-void HMAC_SHA1(IN const u8 Key[],
- u32 KeyLen,
- IN const u8 Message[],
- u32 MessageLen, u8 MAC[], u32 MACLen)
-{
- struct rt_sha1_ctx sha_ctx1;
- struct rt_sha1_ctx sha_ctx2;
- u8 K0[SHA1_BLOCK_SIZE];
- u8 Digest[SHA1_DIGEST_SIZE];
- u32 index;
-
- NdisZeroMemory(&sha_ctx1, sizeof(struct rt_sha1_ctx));
- NdisZeroMemory(&sha_ctx2, sizeof(struct rt_sha1_ctx));
- /*
- * If the length of K = B(Block size): K0 = K.
- * If the length of K > B: hash K to obtain an L byte string,
- * then append (B-L) zeros to create a B-byte string K0 (i.e., K0 = H(K) || 00...00).
- * If the length of K < B: append zeros to the end of K to create a B-byte string K0
- */
- NdisZeroMemory(K0, SHA1_BLOCK_SIZE);
- if (KeyLen <= SHA1_BLOCK_SIZE)
- NdisMoveMemory(K0, Key, KeyLen);
- else
- RT_SHA1(Key, KeyLen, K0);
- /* End of if */
-
- /* Exclusive-Or K0 with ipad */
- /* ipad: Inner pad; the byte x¡¦36¡¦ repeated B times. */
- for (index = 0; index < SHA1_BLOCK_SIZE; index++)
- K0[index] ^= 0x36;
- /* End of for */
-
- RT_SHA1_Init(&sha_ctx1);
- /* H(K0^ipad) */
- SHA1_Append(&sha_ctx1, K0, sizeof(K0));
- /* H((K0^ipad)||text) */
- SHA1_Append(&sha_ctx1, Message, MessageLen);
- SHA1_End(&sha_ctx1, Digest);
-
- /* Exclusive-Or K0 with opad and remove ipad */
- /* opad: Outer pad; the byte x¡¦5c¡¦ repeated B times. */
- for (index = 0; index < SHA1_BLOCK_SIZE; index++)
- K0[index] ^= 0x36 ^ 0x5c;
- /* End of for */
-
- RT_SHA1_Init(&sha_ctx2);
- /* H(K0^opad) */
- SHA1_Append(&sha_ctx2, K0, sizeof(K0));
- /* H( (K0^opad) || H((K0^ipad)||text) ) */
- SHA1_Append(&sha_ctx2, Digest, SHA1_DIGEST_SIZE);
- SHA1_End(&sha_ctx2, Digest);
-
- if (MACLen > SHA1_DIGEST_SIZE)
- NdisMoveMemory(MAC, Digest, SHA1_DIGEST_SIZE);
- else
- NdisMoveMemory(MAC, Digest, MACLen);
-} /* End of HMAC_SHA1 */
-#endif /* HMAC_SHA1_SUPPORT */
-
-#ifdef HMAC_MD5_SUPPORT
-/*
-========================================================================
-Routine Description:
- HMAC using MD5 hash function
-
-Arguments:
- key Secret key
- key_len The length of the key in bytes
- message Message context
- message_len The length of message in bytes
- macLen Request the length of message authentication code
-
-Return Value:
- mac Message authentication code
-
-Note:
- None
-========================================================================
-*/
-void HMAC_MD5(IN const u8 Key[],
- u32 KeyLen,
- IN const u8 Message[],
- u32 MessageLen, u8 MAC[], u32 MACLen)
-{
- struct rt_md5_ctx_struc md5_ctx1;
- struct rt_md5_ctx_struc md5_ctx2;
- u8 K0[MD5_BLOCK_SIZE];
- u8 Digest[MD5_DIGEST_SIZE];
- u32 index;
-
- NdisZeroMemory(&md5_ctx1, sizeof(struct rt_md5_ctx_struc));
- NdisZeroMemory(&md5_ctx2, sizeof(struct rt_md5_ctx_struc));
- /*
- * If the length of K = B(Block size): K0 = K.
- * If the length of K > B: hash K to obtain an L byte string,
- * then append (B-L) zeros to create a B-byte string K0 (i.e., K0 = H(K) || 00...00).
- * If the length of K < B: append zeros to the end of K to create a B-byte string K0
- */
- NdisZeroMemory(K0, MD5_BLOCK_SIZE);
- if (KeyLen <= MD5_BLOCK_SIZE) {
- NdisMoveMemory(K0, Key, KeyLen);
- } else {
- RT_MD5(Key, KeyLen, K0);
- }
-
- /* Exclusive-Or K0 with ipad */
- /* ipad: Inner pad; the byte x¡¦36¡¦ repeated B times. */
- for (index = 0; index < MD5_BLOCK_SIZE; index++)
- K0[index] ^= 0x36;
- /* End of for */
-
- MD5_Init(&md5_ctx1);
- /* H(K0^ipad) */
- MD5_Append(&md5_ctx1, K0, sizeof(K0));
- /* H((K0^ipad)||text) */
- MD5_Append(&md5_ctx1, Message, MessageLen);
- MD5_End(&md5_ctx1, Digest);
-
- /* Exclusive-Or K0 with opad and remove ipad */
- /* opad: Outer pad; the byte x¡¦5c¡¦ repeated B times. */
- for (index = 0; index < MD5_BLOCK_SIZE; index++)
- K0[index] ^= 0x36 ^ 0x5c;
- /* End of for */
-
- MD5_Init(&md5_ctx2);
- /* H(K0^opad) */
- MD5_Append(&md5_ctx2, K0, sizeof(K0));
- /* H( (K0^opad) || H((K0^ipad)||text) ) */
- MD5_Append(&md5_ctx2, Digest, MD5_DIGEST_SIZE);
- MD5_End(&md5_ctx2, Digest);
-
- if (MACLen > MD5_DIGEST_SIZE)
- NdisMoveMemory(MAC, Digest, MD5_DIGEST_SIZE);
- else
- NdisMoveMemory(MAC, Digest, MACLen);
-} /* End of HMAC_SHA256 */
-#endif /* HMAC_MD5_SUPPORT */
-
-/* End of crypt_hmac.c */
diff --git a/drivers/staging/rt2860/common/crypt_md5.c b/drivers/staging/rt2860/common/crypt_md5.c
deleted file mode 100644
index 6deab65..0000000
--- a/drivers/staging/rt2860/common/crypt_md5.c
+++ /dev/null
@@ -1,339 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************/
-
-#include "../crypt_md5.h"
-
-#ifdef MD5_SUPPORT
-/*
- * F, G, H and I are basic MD5 functions.
- */
-#define F(x, y, z) (((x) & (y)) | ((~x) & (z)))
-#define G(x, y, z) (((x) & (z)) | ((y) & (~z)))
-#define H(x, y, z) ((x) ^ (y) ^ (z))
-#define I(x, y, z) ((y) ^ ((x) | (~z)))
-
-#define ROTL(x,n,w) ((x << n) | (x >> (w - n)))
-#define ROTL32(x,n) ROTL(x,n,32) /* 32 bits word */
-
-#define ROUND1(a, b, c, d, x, s, ac) { \
- (a) += F((b),(c),(d)) + (x) + (u32)(ac); \
- (a) = ROTL32((a),(s)); \
- (a) += (b); \
-}
-#define ROUND2(a, b, c, d, x, s, ac) { \
- (a) += G((b),(c),(d)) + (x) + (u32)(ac); \
- (a) = ROTL32((a),(s)); \
- (a) += (b); \
-}
-#define ROUND3(a, b, c, d, x, s, ac) { \
- (a) += H((b),(c),(d)) + (x) + (u32)(ac); \
- (a) = ROTL32((a),(s)); \
- (a) += (b); \
-}
-#define ROUND4(a, b, c, d, x, s, ac) { \
- (a) += I((b),(c),(d)) + (x) + (u32)(ac); \
- (a) = ROTL32((a),(s)); \
- (a) += (b); \
-}
-static const u32 MD5_DefaultHashValue[4] = {
- 0x67452301UL, 0xefcdab89UL, 0x98badcfeUL, 0x10325476UL
-};
-#endif /* MD5_SUPPORT */
-
-#ifdef MD5_SUPPORT
-/*
-========================================================================
-Routine Description:
- Initial Md5_CTX_STRUC
-
-Arguments:
- pMD5_CTX Pointer to Md5_CTX_STRUC
-
-Return Value:
- None
-
-Note:
- None
-========================================================================
-*/
-void MD5_Init(struct rt_md5_ctx_struc *pMD5_CTX)
-{
- NdisMoveMemory(pMD5_CTX->HashValue, MD5_DefaultHashValue,
- sizeof(MD5_DefaultHashValue));
- NdisZeroMemory(pMD5_CTX->Block, MD5_BLOCK_SIZE);
- pMD5_CTX->BlockLen = 0;
- pMD5_CTX->MessageLen = 0;
-} /* End of MD5_Init */
-
-/*
-========================================================================
-Routine Description:
- MD5 computation for one block (512 bits)
-
-Arguments:
- pMD5_CTX Pointer to Md5_CTX_STRUC
-
-Return Value:
- None
-
-Note:
- T[i] := floor(abs(sin(i + 1)) * (2 pow 32)), i is number of round
-========================================================================
-*/
-void MD5_Hash(struct rt_md5_ctx_struc *pMD5_CTX)
-{
- u32 X_i;
- u32 X[16];
- u32 a, b, c, d;
-
- /* Prepare the message schedule, {X_i} */
- NdisMoveMemory(X, pMD5_CTX->Block, MD5_BLOCK_SIZE);
- for (X_i = 0; X_i < 16; X_i++)
- X[X_i] = cpu2le32(X[X_i]); /* Endian Swap */
- /* End of for */
-
- /* MD5 hash computation */
- /* Initialize the working variables */
- a = pMD5_CTX->HashValue[0];
- b = pMD5_CTX->HashValue[1];
- c = pMD5_CTX->HashValue[2];
- d = pMD5_CTX->HashValue[3];
-
- /*
- * Round 1
- * Let [abcd k s i] denote the operation
- * a = b + ((a + F(b,c,d) + X[k] + T[i]) <<< s)
- */
- ROUND1(a, b, c, d, X[0], 7, 0xd76aa478); /* 1 */
- ROUND1(d, a, b, c, X[1], 12, 0xe8c7b756); /* 2 */
- ROUND1(c, d, a, b, X[2], 17, 0x242070db); /* 3 */
- ROUND1(b, c, d, a, X[3], 22, 0xc1bdceee); /* 4 */
- ROUND1(a, b, c, d, X[4], 7, 0xf57c0faf); /* 5 */
- ROUND1(d, a, b, c, X[5], 12, 0x4787c62a); /* 6 */
- ROUND1(c, d, a, b, X[6], 17, 0xa8304613); /* 7 */
- ROUND1(b, c, d, a, X[7], 22, 0xfd469501); /* 8 */
- ROUND1(a, b, c, d, X[8], 7, 0x698098d8); /* 9 */
- ROUND1(d, a, b, c, X[9], 12, 0x8b44f7af); /* 10 */
- ROUND1(c, d, a, b, X[10], 17, 0xffff5bb1); /* 11 */
- ROUND1(b, c, d, a, X[11], 22, 0x895cd7be); /* 12 */
- ROUND1(a, b, c, d, X[12], 7, 0x6b901122); /* 13 */
- ROUND1(d, a, b, c, X[13], 12, 0xfd987193); /* 14 */
- ROUND1(c, d, a, b, X[14], 17, 0xa679438e); /* 15 */
- ROUND1(b, c, d, a, X[15], 22, 0x49b40821); /* 16 */
-
- /*
- * Round 2
- * Let [abcd k s i] denote the operation
- * a = b + ((a + G(b,c,d) + X[k] + T[i]) <<< s)
- */
- ROUND2(a, b, c, d, X[1], 5, 0xf61e2562); /* 17 */
- ROUND2(d, a, b, c, X[6], 9, 0xc040b340); /* 18 */
- ROUND2(c, d, a, b, X[11], 14, 0x265e5a51); /* 19 */
- ROUND2(b, c, d, a, X[0], 20, 0xe9b6c7aa); /* 20 */
- ROUND2(a, b, c, d, X[5], 5, 0xd62f105d); /* 21 */
- ROUND2(d, a, b, c, X[10], 9, 0x2441453); /* 22 */
- ROUND2(c, d, a, b, X[15], 14, 0xd8a1e681); /* 23 */
- ROUND2(b, c, d, a, X[4], 20, 0xe7d3fbc8); /* 24 */
- ROUND2(a, b, c, d, X[9], 5, 0x21e1cde6); /* 25 */
- ROUND2(d, a, b, c, X[14], 9, 0xc33707d6); /* 26 */
- ROUND2(c, d, a, b, X[3], 14, 0xf4d50d87); /* 27 */
- ROUND2(b, c, d, a, X[8], 20, 0x455a14ed); /* 28 */
- ROUND2(a, b, c, d, X[13], 5, 0xa9e3e905); /* 29 */
- ROUND2(d, a, b, c, X[2], 9, 0xfcefa3f8); /* 30 */
- ROUND2(c, d, a, b, X[7], 14, 0x676f02d9); /* 31 */
- ROUND2(b, c, d, a, X[12], 20, 0x8d2a4c8a); /* 32 */
-
- /*
- * Round 3
- * Let [abcd k s t] denote the operation
- * a = b + ((a + H(b,c,d) + X[k] + T[i]) <<< s)
- */
- ROUND3(a, b, c, d, X[5], 4, 0xfffa3942); /* 33 */
- ROUND3(d, a, b, c, X[8], 11, 0x8771f681); /* 34 */
- ROUND3(c, d, a, b, X[11], 16, 0x6d9d6122); /* 35 */
- ROUND3(b, c, d, a, X[14], 23, 0xfde5380c); /* 36 */
- ROUND3(a, b, c, d, X[1], 4, 0xa4beea44); /* 37 */
- ROUND3(d, a, b, c, X[4], 11, 0x4bdecfa9); /* 38 */
- ROUND3(c, d, a, b, X[7], 16, 0xf6bb4b60); /* 39 */
- ROUND3(b, c, d, a, X[10], 23, 0xbebfbc70); /* 40 */
- ROUND3(a, b, c, d, X[13], 4, 0x289b7ec6); /* 41 */
- ROUND3(d, a, b, c, X[0], 11, 0xeaa127fa); /* 42 */
- ROUND3(c, d, a, b, X[3], 16, 0xd4ef3085); /* 43 */
- ROUND3(b, c, d, a, X[6], 23, 0x4881d05); /* 44 */
- ROUND3(a, b, c, d, X[9], 4, 0xd9d4d039); /* 45 */
- ROUND3(d, a, b, c, X[12], 11, 0xe6db99e5); /* 46 */
- ROUND3(c, d, a, b, X[15], 16, 0x1fa27cf8); /* 47 */
- ROUND3(b, c, d, a, X[2], 23, 0xc4ac5665); /* 48 */
-
- /*
- * Round 4
- * Let [abcd k s t] denote the operation
- * a = b + ((a + I(b,c,d) + X[k] + T[i]) <<< s)
- */
- ROUND4(a, b, c, d, X[0], 6, 0xf4292244); /* 49 */
- ROUND4(d, a, b, c, X[7], 10, 0x432aff97); /* 50 */
- ROUND4(c, d, a, b, X[14], 15, 0xab9423a7); /* 51 */
- ROUND4(b, c, d, a, X[5], 21, 0xfc93a039); /* 52 */
- ROUND4(a, b, c, d, X[12], 6, 0x655b59c3); /* 53 */
- ROUND4(d, a, b, c, X[3], 10, 0x8f0ccc92); /* 54 */
- ROUND4(c, d, a, b, X[10], 15, 0xffeff47d); /* 55 */
- ROUND4(b, c, d, a, X[1], 21, 0x85845dd1); /* 56 */
- ROUND4(a, b, c, d, X[8], 6, 0x6fa87e4f); /* 57 */
- ROUND4(d, a, b, c, X[15], 10, 0xfe2ce6e0); /* 58 */
- ROUND4(c, d, a, b, X[6], 15, 0xa3014314); /* 59 */
- ROUND4(b, c, d, a, X[13], 21, 0x4e0811a1); /* 60 */
- ROUND4(a, b, c, d, X[4], 6, 0xf7537e82); /* 61 */
- ROUND4(d, a, b, c, X[11], 10, 0xbd3af235); /* 62 */
- ROUND4(c, d, a, b, X[2], 15, 0x2ad7d2bb); /* 63 */
- ROUND4(b, c, d, a, X[9], 21, 0xeb86d391); /* 64 */
-
- /* Compute the i^th intermediate hash value H^(i) */
- pMD5_CTX->HashValue[0] += a;
- pMD5_CTX->HashValue[1] += b;
- pMD5_CTX->HashValue[2] += c;
- pMD5_CTX->HashValue[3] += d;
-
- NdisZeroMemory(pMD5_CTX->Block, MD5_BLOCK_SIZE);
- pMD5_CTX->BlockLen = 0;
-} /* End of MD5_Hash */
-
-/*
-========================================================================
-Routine Description:
- The message is appended to block. If block size > 64 bytes, the MD5_Hash
-will be called.
-
-Arguments:
- pMD5_CTX Pointer to struct rt_md5_ctx_struc
- message Message context
- messageLen The length of message in bytes
-
-Return Value:
- None
-
-Note:
- None
-========================================================================
-*/
-void MD5_Append(struct rt_md5_ctx_struc *pMD5_CTX,
- IN const u8 Message[], u32 MessageLen)
-{
- u32 appendLen = 0;
- u32 diffLen = 0;
-
- while (appendLen != MessageLen) {
- diffLen = MessageLen - appendLen;
- if ((pMD5_CTX->BlockLen + diffLen) < MD5_BLOCK_SIZE) {
- NdisMoveMemory(pMD5_CTX->Block + pMD5_CTX->BlockLen,
- Message + appendLen, diffLen);
- pMD5_CTX->BlockLen += diffLen;
- appendLen += diffLen;
- } else {
- NdisMoveMemory(pMD5_CTX->Block + pMD5_CTX->BlockLen,
- Message + appendLen,
- MD5_BLOCK_SIZE - pMD5_CTX->BlockLen);
- appendLen += (MD5_BLOCK_SIZE - pMD5_CTX->BlockLen);
- pMD5_CTX->BlockLen = MD5_BLOCK_SIZE;
- MD5_Hash(pMD5_CTX);
- } /* End of if */
- } /* End of while */
- pMD5_CTX->MessageLen += MessageLen;
-} /* End of MD5_Append */
-
-/*
-========================================================================
-Routine Description:
- 1. Append bit 1 to end of the message
- 2. Append the length of message in rightmost 64 bits
- 3. Transform the Hash Value to digest message
-
-Arguments:
- pMD5_CTX Pointer to struct rt_md5_ctx_struc
-
-Return Value:
- digestMessage Digest message
-
-Note:
- None
-========================================================================
-*/
-void MD5_End(struct rt_md5_ctx_struc *pMD5_CTX, u8 DigestMessage[])
-{
- u32 index;
- u64 message_length_bits;
-
- /* append 1 bits to end of the message */
- NdisFillMemory(pMD5_CTX->Block + pMD5_CTX->BlockLen, 1, 0x80);
-
- /* 55 = 64 - 8 - 1: append 1 bit(1 byte) and message length (8 bytes) */
- if (pMD5_CTX->BlockLen > 55)
- MD5_Hash(pMD5_CTX);
- /* End of if */
-
- /* Append the length of message in rightmost 64 bits */
- message_length_bits = pMD5_CTX->MessageLen * 8;
- message_length_bits = cpu2le64(message_length_bits);
- NdisMoveMemory(&pMD5_CTX->Block[56], &message_length_bits, 8);
- MD5_Hash(pMD5_CTX);
-
- /* Return message digest, transform the u32 hash value to bytes */
- for (index = 0; index < 4; index++)
- pMD5_CTX->HashValue[index] =
- cpu2le32(pMD5_CTX->HashValue[index]);
- /* End of for */
- NdisMoveMemory(DigestMessage, pMD5_CTX->HashValue, MD5_DIGEST_SIZE);
-} /* End of MD5_End */
-
-/*
-========================================================================
-Routine Description:
- MD5 algorithm
-
-Arguments:
- message Message context
- messageLen The length of message in bytes
-
-Return Value:
- digestMessage Digest message
-
-Note:
- None
-========================================================================
-*/
-void RT_MD5(IN const u8 Message[],
- u32 MessageLen, u8 DigestMessage[])
-{
- struct rt_md5_ctx_struc md5_ctx;
-
- NdisZeroMemory(&md5_ctx, sizeof(struct rt_md5_ctx_struc));
- MD5_Init(&md5_ctx);
- MD5_Append(&md5_ctx, Message, MessageLen);
- MD5_End(&md5_ctx, DigestMessage);
-} /* End of RT_MD5 */
-
-#endif /* MD5_SUPPORT */
-
-/* End of crypt_md5.c */
diff --git a/drivers/staging/rt2860/common/crypt_sha2.c b/drivers/staging/rt2860/common/crypt_sha2.c
deleted file mode 100644
index fa83fb2..0000000
--- a/drivers/staging/rt2860/common/crypt_sha2.c
+++ /dev/null
@@ -1,269 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************/
-
-#include "../crypt_sha2.h"
-
-/* Basic operations */
-#define SHR(x,n) (x >> n) /* SHR(x)^n, right shift n bits , x is w-bit word, 0 <= n <= w */
-#define ROTR(x,n,w) ((x >> n) | (x << (w - n))) /* ROTR(x)^n, circular right shift n bits , x is w-bit word, 0 <= n <= w */
-#define ROTL(x,n,w) ((x << n) | (x >> (w - n))) /* ROTL(x)^n, circular left shift n bits , x is w-bit word, 0 <= n <= w */
-#define ROTR32(x,n) ROTR(x,n,32) /* 32 bits word */
-#define ROTL32(x,n) ROTL(x,n,32) /* 32 bits word */
-
-/* Basic functions */
-#define Ch(x,y,z) ((x & y) ^ ((~x) & z))
-#define Maj(x,y,z) ((x & y) ^ (x & z) ^ (y & z))
-#define Parity(x,y,z) (x ^ y ^ z)
-
-#ifdef SHA1_SUPPORT
-/* SHA1 constants */
-#define SHA1_MASK 0x0000000f
-static const u32 SHA1_K[4] = {
- 0x5a827999UL, 0x6ed9eba1UL, 0x8f1bbcdcUL, 0xca62c1d6UL
-};
-
-static const u32 SHA1_DefaultHashValue[5] = {
- 0x67452301UL, 0xefcdab89UL, 0x98badcfeUL, 0x10325476UL, 0xc3d2e1f0UL
-};
-
-/*
-========================================================================
-Routine Description:
- Initial struct rt_sha1_ctx
-
-Arguments:
- pSHA_CTX Pointer to struct rt_sha1_ctx
-
-Return Value:
- None
-
-Note:
- None
-========================================================================
-*/
-void RT_SHA1_Init(struct rt_sha1_ctx *pSHA_CTX)
-{
- NdisMoveMemory(pSHA_CTX->HashValue, SHA1_DefaultHashValue,
- sizeof(SHA1_DefaultHashValue));
- NdisZeroMemory(pSHA_CTX->Block, SHA1_BLOCK_SIZE);
- pSHA_CTX->MessageLen = 0;
- pSHA_CTX->BlockLen = 0;
-} /* End of RT_SHA1_Init */
-
-/*
-========================================================================
-Routine Description:
- SHA1 computation for one block (512 bits)
-
-Arguments:
- pSHA_CTX Pointer to struct rt_sha1_ctx
-
-Return Value:
- None
-
-Note:
- None
-========================================================================
-*/
-void SHA1_Hash(struct rt_sha1_ctx *pSHA_CTX)
-{
- u32 W_i, t, s;
- u32 W[16];
- u32 a, b, c, d, e, T, f_t = 0;
-
- /* Prepare the message schedule, {W_i}, 0 < t < 15 */
- NdisMoveMemory(W, pSHA_CTX->Block, SHA1_BLOCK_SIZE);
- for (W_i = 0; W_i < 16; W_i++)
- W[W_i] = cpu2be32(W[W_i]); /* Endian Swap */
- /* End of for */
-
- /* SHA256 hash computation */
- /* Initialize the working variables */
- a = pSHA_CTX->HashValue[0];
- b = pSHA_CTX->HashValue[1];
- c = pSHA_CTX->HashValue[2];
- d = pSHA_CTX->HashValue[3];
- e = pSHA_CTX->HashValue[4];
-
- /* 80 rounds */
- for (t = 0; t < 80; t++) {
- s = t & SHA1_MASK;
- if (t > 15) { /* Prepare the message schedule, {W_i}, 16 < t < 79 */
- W[s] =
- (W[(s + 13) & SHA1_MASK]) ^ (W[(s + 8) & SHA1_MASK])
- ^ (W[(s + 2) & SHA1_MASK]) ^ W[s];
- W[s] = ROTL32(W[s], 1);
- } /* End of if */
- switch (t / 20) {
- case 0:
- f_t = Ch(b, c, d);
- break;
- case 1:
- f_t = Parity(b, c, d);
- break;
- case 2:
- f_t = Maj(b, c, d);
- break;
- case 3:
- f_t = Parity(b, c, d);
- break;
- } /* End of switch */
- T = ROTL32(a, 5) + f_t + e + SHA1_K[t / 20] + W[s];
- e = d;
- d = c;
- c = ROTL32(b, 30);
- b = a;
- a = T;
- } /* End of for */
-
- /* Compute the i^th intermediate hash value H^(i) */
- pSHA_CTX->HashValue[0] += a;
- pSHA_CTX->HashValue[1] += b;
- pSHA_CTX->HashValue[2] += c;
- pSHA_CTX->HashValue[3] += d;
- pSHA_CTX->HashValue[4] += e;
-
- NdisZeroMemory(pSHA_CTX->Block, SHA1_BLOCK_SIZE);
- pSHA_CTX->BlockLen = 0;
-} /* End of SHA1_Hash */
-
-/*
-========================================================================
-Routine Description:
- The message is appended to block. If block size > 64 bytes, the SHA1_Hash
-will be called.
-
-Arguments:
- pSHA_CTX Pointer to struct rt_sha1_ctx
- message Message context
- messageLen The length of message in bytes
-
-Return Value:
- None
-
-Note:
- None
-========================================================================
-*/
-void SHA1_Append(struct rt_sha1_ctx *pSHA_CTX,
- IN const u8 Message[], u32 MessageLen)
-{
- u32 appendLen = 0;
- u32 diffLen = 0;
-
- while (appendLen != MessageLen) {
- diffLen = MessageLen - appendLen;
- if ((pSHA_CTX->BlockLen + diffLen) < SHA1_BLOCK_SIZE) {
- NdisMoveMemory(pSHA_CTX->Block + pSHA_CTX->BlockLen,
- Message + appendLen, diffLen);
- pSHA_CTX->BlockLen += diffLen;
- appendLen += diffLen;
- } else {
- NdisMoveMemory(pSHA_CTX->Block + pSHA_CTX->BlockLen,
- Message + appendLen,
- SHA1_BLOCK_SIZE - pSHA_CTX->BlockLen);
- appendLen += (SHA1_BLOCK_SIZE - pSHA_CTX->BlockLen);
- pSHA_CTX->BlockLen = SHA1_BLOCK_SIZE;
- SHA1_Hash(pSHA_CTX);
- } /* End of if */
- } /* End of while */
- pSHA_CTX->MessageLen += MessageLen;
-} /* End of SHA1_Append */
-
-/*
-========================================================================
-Routine Description:
- 1. Append bit 1 to end of the message
- 2. Append the length of message in rightmost 64 bits
- 3. Transform the Hash Value to digest message
-
-Arguments:
- pSHA_CTX Pointer to struct rt_sha1_ctx
-
-Return Value:
- digestMessage Digest message
-
-Note:
- None
-========================================================================
-*/
-void SHA1_End(struct rt_sha1_ctx *pSHA_CTX, u8 DigestMessage[])
-{
- u32 index;
- u64 message_length_bits;
-
- /* Append bit 1 to end of the message */
- NdisFillMemory(pSHA_CTX->Block + pSHA_CTX->BlockLen, 1, 0x80);
-
- /* 55 = 64 - 8 - 1: append 1 bit(1 byte) and message length (8 bytes) */
- if (pSHA_CTX->BlockLen > 55)
- SHA1_Hash(pSHA_CTX);
- /* End of if */
-
- /* Append the length of message in rightmost 64 bits */
- message_length_bits = pSHA_CTX->MessageLen * 8;
- message_length_bits = cpu2be64(message_length_bits);
- NdisMoveMemory(&pSHA_CTX->Block[56], &message_length_bits, 8);
- SHA1_Hash(pSHA_CTX);
-
- /* Return message digest, transform the u32 hash value to bytes */
- for (index = 0; index < 5; index++)
- pSHA_CTX->HashValue[index] =
- cpu2be32(pSHA_CTX->HashValue[index]);
- /* End of for */
- NdisMoveMemory(DigestMessage, pSHA_CTX->HashValue, SHA1_DIGEST_SIZE);
-} /* End of SHA1_End */
-
-/*
-========================================================================
-Routine Description:
- SHA1 algorithm
-
-Arguments:
- message Message context
- messageLen The length of message in bytes
-
-Return Value:
- digestMessage Digest message
-
-Note:
- None
-========================================================================
-*/
-void RT_SHA1(IN const u8 Message[],
- u32 MessageLen, u8 DigestMessage[])
-{
-
- struct rt_sha1_ctx sha_ctx;
-
- NdisZeroMemory(&sha_ctx, sizeof(struct rt_sha1_ctx));
- RT_SHA1_Init(&sha_ctx);
- SHA1_Append(&sha_ctx, Message, MessageLen);
- SHA1_End(&sha_ctx, DigestMessage);
-} /* End of RT_SHA1 */
-#endif /* SHA1_SUPPORT */
-
-/* End of crypt_sha2.c */
diff --git a/drivers/staging/rt2860/common/dfs.c b/drivers/staging/rt2860/common/dfs.c
deleted file mode 100644
index 71cbb26..0000000
--- a/drivers/staging/rt2860/common/dfs.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- ap_dfs.c
-
- Abstract:
- Support DFS function.
-
- Revision History:
- Who When What
- -------- ---------- ----------------------------------------------
-*/
-
-#include "../rt_config.h"
-
-/*
- ========================================================================
-
- Routine Description:
- Radar channel check routine
-
- Arguments:
- pAd Pointer to our adapter
-
- Return Value:
- TRUE need to do radar detect
- FALSE need not to do radar detect
-
- ========================================================================
-*/
-BOOLEAN RadarChannelCheck(struct rt_rtmp_adapter *pAd, u8 Ch)
-{
- int i;
- BOOLEAN result = FALSE;
-
- for (i = 0; i < pAd->ChannelListNum; i++) {
- if (Ch == pAd->ChannelList[i].Channel) {
- result = pAd->ChannelList[i].DfsReq;
- break;
- }
- }
-
- return result;
-}
diff --git a/drivers/staging/rt2860/common/ee_efuse.c b/drivers/staging/rt2860/common/ee_efuse.c
deleted file mode 100644
index fed0ba4..0000000
--- a/drivers/staging/rt2860/common/ee_efuse.c
+++ /dev/null
@@ -1,351 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- ee_efuse.c
-
- Abstract:
- Miniport generic portion header file
-
- Revision History:
- Who When What
- -------- ---------- ----------------------------------------------
-*/
-
-#include "../rt_config.h"
-
-#define EFUSE_USAGE_MAP_START 0x2d0
-#define EFUSE_USAGE_MAP_END 0x2fc
-#define EFUSE_USAGE_MAP_SIZE 45
-
-#define EFUSE_EEPROM_DEFULT_FILE "RT30xxEEPROM.bin"
-#define MAX_EEPROM_BIN_FILE_SIZE 1024
-
-#define EFUSE_TAG 0x2fe
-
-typedef union _EFUSE_CTRL_STRUC {
- struct {
- u32 EFSROM_AOUT:6;
- u32 EFSROM_MODE:2;
- u32 EFSROM_LDO_OFF_TIME:6;
- u32 EFSROM_LDO_ON_TIME:2;
- u32 EFSROM_AIN:10;
- u32 RESERVED:4;
- u32 EFSROM_KICK:1;
- u32 SEL_EFUSE:1;
- } field;
- u32 word;
-} EFUSE_CTRL_STRUC, *PEFUSE_CTRL_STRUC;
-
-/*
-========================================================================
-
- Routine Description:
-
- Arguments:
-
- Return Value:
-
- Note:
-
-========================================================================
-*/
-u8 eFuseReadRegisters(struct rt_rtmp_adapter *pAd,
- u16 Offset, u16 Length, u16 * pData)
-{
- EFUSE_CTRL_STRUC eFuseCtrlStruc;
- int i;
- u16 efuseDataOffset;
- u32 data;
-
- RTMP_IO_READ32(pAd, EFUSE_CTRL, &eFuseCtrlStruc.word);
-
- /*Step0. Write 10-bit of address to EFSROM_AIN (0x580, bit25:bit16). The address must be 16-byte alignment. */
- /*Use the eeprom logical address and covert to address to block number */
- eFuseCtrlStruc.field.EFSROM_AIN = Offset & 0xfff0;
-
- /*Step1. Write EFSROM_MODE (0x580, bit7:bit6) to 0. */
- eFuseCtrlStruc.field.EFSROM_MODE = 0;
-
- /*Step2. Write EFSROM_KICK (0x580, bit30) to 1 to kick-off physical read procedure. */
- eFuseCtrlStruc.field.EFSROM_KICK = 1;
-
- NdisMoveMemory(&data, &eFuseCtrlStruc, 4);
- RTMP_IO_WRITE32(pAd, EFUSE_CTRL, data);
-
- /*Step3. Polling EFSROM_KICK(0x580, bit30) until it become 0 again. */
- i = 0;
- while (i < 500) {
- /*rtmp.HwMemoryReadDword(EFUSE_CTRL, (DWORD *) &eFuseCtrlStruc, 4); */
- RTMP_IO_READ32(pAd, EFUSE_CTRL, &eFuseCtrlStruc.word);
- if (eFuseCtrlStruc.field.EFSROM_KICK == 0) {
- break;
- }
- RTMPusecDelay(2);
- i++;
- }
-
- /*if EFSROM_AOUT is not found in physical address, write 0xffff */
- if (eFuseCtrlStruc.field.EFSROM_AOUT == 0x3f) {
- for (i = 0; i < Length / 2; i++)
- *(pData + 2 * i) = 0xffff;
- } else {
- /*Step4. Read 16-byte of data from EFUSE_DATA0-3 (0x590-0x59C) */
- efuseDataOffset = EFUSE_DATA3 - (Offset & 0xC);
- /*data hold 4 bytes data. */
- /*In RTMP_IO_READ32 will automatically execute 32-bytes swapping */
- RTMP_IO_READ32(pAd, efuseDataOffset, &data);
- /*Decide the upper 2 bytes or the bottom 2 bytes. */
- /* Little-endian S | S Big-endian */
- /* addr 3 2 1 0 | 0 1 2 3 */
- /* Ori-V D C B A | A B C D */
- /*After swapping */
- /* D C B A | D C B A */
- /*Return 2-bytes */
- /*The return byte statrs from S. Therefore, the little-endian will return BA, the Big-endian will return DC. */
- /*For returning the bottom 2 bytes, the Big-endian should shift right 2-bytes. */
- data = data >> (8 * (Offset & 0x3));
-
- NdisMoveMemory(pData, &data, Length);
- }
-
- return (u8)eFuseCtrlStruc.field.EFSROM_AOUT;
-
-}
-
-/*
-========================================================================
-
- Routine Description:
-
- Arguments:
-
- Return Value:
-
- Note:
-
-========================================================================
-*/
-void eFusePhysicalReadRegisters(struct rt_rtmp_adapter *pAd,
- u16 Offset,
- u16 Length, u16 * pData)
-{
- EFUSE_CTRL_STRUC eFuseCtrlStruc;
- int i;
- u16 efuseDataOffset;
- u32 data;
-
- RTMP_IO_READ32(pAd, EFUSE_CTRL, &eFuseCtrlStruc.word);
-
- /*Step0. Write 10-bit of address to EFSROM_AIN (0x580, bit25:bit16). The address must be 16-byte alignment. */
- eFuseCtrlStruc.field.EFSROM_AIN = Offset & 0xfff0;
-
- /*Step1. Write EFSROM_MODE (0x580, bit7:bit6) to 1. */
- /*Read in physical view */
- eFuseCtrlStruc.field.EFSROM_MODE = 1;
-
- /*Step2. Write EFSROM_KICK (0x580, bit30) to 1 to kick-off physical read procedure. */
- eFuseCtrlStruc.field.EFSROM_KICK = 1;
-
- NdisMoveMemory(&data, &eFuseCtrlStruc, 4);
- RTMP_IO_WRITE32(pAd, EFUSE_CTRL, data);
-
- /*Step3. Polling EFSROM_KICK(0x580, bit30) until it become 0 again. */
- i = 0;
- while (i < 500) {
- RTMP_IO_READ32(pAd, EFUSE_CTRL, &eFuseCtrlStruc.word);
- if (eFuseCtrlStruc.field.EFSROM_KICK == 0)
- break;
- RTMPusecDelay(2);
- i++;
- }
-
- /*Step4. Read 16-byte of data from EFUSE_DATA0-3 (0x59C-0x590) */
- /*Because the size of each EFUSE_DATA is 4 Bytes, the size of address of each is 2 bits. */
- /*The previous 2 bits is the EFUSE_DATA number, the last 2 bits is used to decide which bytes */
- /*Decide which EFUSE_DATA to read */
- /*590:F E D C */
- /*594:B A 9 8 */
- /*598:7 6 5 4 */
- /*59C:3 2 1 0 */
- efuseDataOffset = EFUSE_DATA3 - (Offset & 0xC);
-
- RTMP_IO_READ32(pAd, efuseDataOffset, &data);
-
- data = data >> (8 * (Offset & 0x3));
-
- NdisMoveMemory(pData, &data, Length);
-
-}
-
-/*
-========================================================================
-
- Routine Description:
-
- Arguments:
-
- Return Value:
-
- Note:
-
-========================================================================
-*/
-static void eFuseReadPhysical(struct rt_rtmp_adapter *pAd,
- u16 *lpInBuffer,
- unsigned long nInBufferSize,
- u16 *lpOutBuffer, unsigned long nOutBufferSize)
-{
- u16 *pInBuf = (u16 *) lpInBuffer;
- u16 *pOutBuf = (u16 *) lpOutBuffer;
-
- u16 Offset = pInBuf[0]; /*addr */
- u16 Length = pInBuf[1]; /*length */
- int i;
-
- for (i = 0; i < Length; i += 2) {
- eFusePhysicalReadRegisters(pAd, Offset + i, 2, &pOutBuf[i / 2]);
- }
-}
-
-/*
-========================================================================
-
- Routine Description:
-
- Arguments:
-
- Return Value:
-
- Note:
-
-========================================================================
-*/
-int set_eFuseGetFreeBlockCount_Proc(struct rt_rtmp_adapter *pAd, char *arg)
-{
- u16 i;
- u16 LogicalAddress;
- u16 efusefreenum = 0;
- if (!pAd->bUseEfuse)
- return FALSE;
- for (i = EFUSE_USAGE_MAP_START; i <= EFUSE_USAGE_MAP_END; i += 2) {
- eFusePhysicalReadRegisters(pAd, i, 2, &LogicalAddress);
- if ((LogicalAddress & 0xff) == 0) {
- efusefreenum = (u8)(EFUSE_USAGE_MAP_END - i + 1);
- break;
- } else if (((LogicalAddress >> 8) & 0xff) == 0) {
- efusefreenum = (u8)(EFUSE_USAGE_MAP_END - i);
- break;
- }
-
- if (i == EFUSE_USAGE_MAP_END)
- efusefreenum = 0;
- }
- printk(KERN_DEBUG "efuseFreeNumber is %d\n", efusefreenum);
- return TRUE;
-}
-
-int set_eFusedump_Proc(struct rt_rtmp_adapter *pAd, char *arg)
-{
- u16 InBuf[3];
- int i = 0;
- if (!pAd->bUseEfuse)
- return FALSE;
-
- printk(KERN_DEBUG "Block 0: ");
-
- for (i = 0; i < EFUSE_USAGE_MAP_END / 2; i++) {
- InBuf[0] = 2 * i;
- InBuf[1] = 2;
- InBuf[2] = 0x0;
-
- eFuseReadPhysical(pAd, &InBuf[0], 4, &InBuf[2], 2);
- if (i && i % 4 == 0) {
- printk(KERN_CONT "\n");
- printk(KERN_DEBUG "Block %x:", i / 8);
- }
- printk(KERN_CONT "%04x ", InBuf[2]);
- }
- printk(KERN_CONT "\n");
-
- return TRUE;
-}
-
-int rtmp_ee_efuse_read16(struct rt_rtmp_adapter *pAd,
- u16 Offset, u16 * pValue)
-{
- eFuseReadRegisters(pAd, Offset, 2, pValue);
- return (*pValue);
-}
-
-int RtmpEfuseSupportCheck(struct rt_rtmp_adapter *pAd)
-{
- u16 value;
-
- if (IS_RT30xx(pAd)) {
- eFusePhysicalReadRegisters(pAd, EFUSE_TAG, 2, &value);
- pAd->EFuseTag = (value & 0xff);
- }
- return 0;
-}
-
-void eFuseGetFreeBlockCount(struct rt_rtmp_adapter *pAd, u32 *EfuseFreeBlock)
-{
- u16 i;
- u16 LogicalAddress;
- if (!pAd->bUseEfuse) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("eFuseGetFreeBlockCount Only supports efuse Mode\n"));
- return;
- }
- for (i = EFUSE_USAGE_MAP_START; i <= EFUSE_USAGE_MAP_END; i += 2) {
- eFusePhysicalReadRegisters(pAd, i, 2, &LogicalAddress);
- if ((LogicalAddress & 0xff) == 0) {
- *EfuseFreeBlock = (u8)(EFUSE_USAGE_MAP_END - i + 1);
- break;
- } else if (((LogicalAddress >> 8) & 0xff) == 0) {
- *EfuseFreeBlock = (u8)(EFUSE_USAGE_MAP_END - i);
- break;
- }
-
- if (i == EFUSE_USAGE_MAP_END)
- *EfuseFreeBlock = 0;
- }
- DBGPRINT(RT_DEBUG_TRACE,
- ("eFuseGetFreeBlockCount is 0x%x\n", *EfuseFreeBlock));
-}
-
-int eFuse_init(struct rt_rtmp_adapter *pAd)
-{
- u32 EfuseFreeBlock = 0;
- DBGPRINT(RT_DEBUG_ERROR,
- ("NVM is Efuse and its size =%x[%x-%x] \n",
- EFUSE_USAGE_MAP_SIZE, EFUSE_USAGE_MAP_START,
- EFUSE_USAGE_MAP_END));
- eFuseGetFreeBlockCount(pAd, &EfuseFreeBlock);
-
- return 0;
-}
diff --git a/drivers/staging/rt2860/common/ee_prom.c b/drivers/staging/rt2860/common/ee_prom.c
deleted file mode 100644
index 2083740..0000000
--- a/drivers/staging/rt2860/common/ee_prom.c
+++ /dev/null
@@ -1,197 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- ee_prom.c
-
- Abstract:
- Miniport generic portion header file
-
- Revision History:
- Who When What
- -------- ---------- ----------------------------------------------
-*/
-
-#include "../rt_config.h"
-
-/* IRQL = PASSIVE_LEVEL */
-static inline void RaiseClock(struct rt_rtmp_adapter *pAd, u32 * x)
-{
- *x = *x | EESK;
- RTMP_IO_WRITE32(pAd, E2PROM_CSR, *x);
- RTMPusecDelay(1); /* Max frequency = 1MHz in Spec. definition */
-}
-
-/* IRQL = PASSIVE_LEVEL */
-static inline void LowerClock(struct rt_rtmp_adapter *pAd, u32 * x)
-{
- *x = *x & ~EESK;
- RTMP_IO_WRITE32(pAd, E2PROM_CSR, *x);
- RTMPusecDelay(1);
-}
-
-/* IRQL = PASSIVE_LEVEL */
-static inline u16 ShiftInBits(struct rt_rtmp_adapter *pAd)
-{
- u32 x, i;
- u16 data = 0;
-
- RTMP_IO_READ32(pAd, E2PROM_CSR, &x);
-
- x &= ~(EEDO | EEDI);
-
- for (i = 0; i < 16; i++) {
- data = data << 1;
- RaiseClock(pAd, &x);
-
- RTMP_IO_READ32(pAd, E2PROM_CSR, &x);
- LowerClock(pAd, &x); /*prevent read failed */
-
- x &= ~(EEDI);
- if (x & EEDO)
- data |= 1;
- }
-
- return data;
-}
-
-/* IRQL = PASSIVE_LEVEL */
-static inline void ShiftOutBits(struct rt_rtmp_adapter *pAd,
- u16 data, u16 count)
-{
- u32 x, mask;
-
- mask = 0x01 << (count - 1);
- RTMP_IO_READ32(pAd, E2PROM_CSR, &x);
-
- x &= ~(EEDO | EEDI);
-
- do {
- x &= ~EEDI;
- if (data & mask)
- x |= EEDI;
-
- RTMP_IO_WRITE32(pAd, E2PROM_CSR, x);
-
- RaiseClock(pAd, &x);
- LowerClock(pAd, &x);
-
- mask = mask >> 1;
- } while (mask);
-
- x &= ~EEDI;
- RTMP_IO_WRITE32(pAd, E2PROM_CSR, x);
-}
-
-/* IRQL = PASSIVE_LEVEL */
-static inline void EEpromCleanup(struct rt_rtmp_adapter *pAd)
-{
- u32 x;
-
- RTMP_IO_READ32(pAd, E2PROM_CSR, &x);
-
- x &= ~(EECS | EEDI);
- RTMP_IO_WRITE32(pAd, E2PROM_CSR, x);
-
- RaiseClock(pAd, &x);
- LowerClock(pAd, &x);
-}
-
-static inline void EWEN(struct rt_rtmp_adapter *pAd)
-{
- u32 x;
-
- /* reset bits and set EECS */
- RTMP_IO_READ32(pAd, E2PROM_CSR, &x);
- x &= ~(EEDI | EEDO | EESK);
- x |= EECS;
- RTMP_IO_WRITE32(pAd, E2PROM_CSR, x);
-
- /* kick a pulse */
- RaiseClock(pAd, &x);
- LowerClock(pAd, &x);
-
- /* output the read_opcode and six pulse in that order */
- ShiftOutBits(pAd, EEPROM_EWEN_OPCODE, 5);
- ShiftOutBits(pAd, 0, 6);
-
- EEpromCleanup(pAd);
-}
-
-static inline void EWDS(struct rt_rtmp_adapter *pAd)
-{
- u32 x;
-
- /* reset bits and set EECS */
- RTMP_IO_READ32(pAd, E2PROM_CSR, &x);
- x &= ~(EEDI | EEDO | EESK);
- x |= EECS;
- RTMP_IO_WRITE32(pAd, E2PROM_CSR, x);
-
- /* kick a pulse */
- RaiseClock(pAd, &x);
- LowerClock(pAd, &x);
-
- /* output the read_opcode and six pulse in that order */
- ShiftOutBits(pAd, EEPROM_EWDS_OPCODE, 5);
- ShiftOutBits(pAd, 0, 6);
-
- EEpromCleanup(pAd);
-}
-
-/* IRQL = PASSIVE_LEVEL */
-int rtmp_ee_prom_read16(struct rt_rtmp_adapter *pAd,
- u16 Offset, u16 * pValue)
-{
- u32 x;
- u16 data;
-
- Offset /= 2;
- /* reset bits and set EECS */
- RTMP_IO_READ32(pAd, E2PROM_CSR, &x);
- x &= ~(EEDI | EEDO | EESK);
- x |= EECS;
- RTMP_IO_WRITE32(pAd, E2PROM_CSR, x);
-
- /* patch can not access e-Fuse issue */
- if (!(IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd))) {
- /* kick a pulse */
- RaiseClock(pAd, &x);
- LowerClock(pAd, &x);
- }
- /* output the read_opcode and register number in that order */
- ShiftOutBits(pAd, EEPROM_READ_OPCODE, 3);
- ShiftOutBits(pAd, Offset, pAd->EEPROMAddressNum);
-
- /* Now read the data (16 bits) in from the selected EEPROM word */
- data = ShiftInBits(pAd);
-
- EEpromCleanup(pAd);
-
- *pValue = data;
-
- return NDIS_STATUS_SUCCESS;
-}
diff --git a/drivers/staging/rt2860/common/eeprom.c b/drivers/staging/rt2860/common/eeprom.c
deleted file mode 100644
index 9467007..0000000
--- a/drivers/staging/rt2860/common/eeprom.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- eeprom.c
-
- Abstract:
-
- Revision History:
- Who When What
- -------- ---------- ----------------------------------------------
- Name Date Modification logs
-*/
-#include "../rt_config.h"
-
-int RtmpChipOpsEepromHook(struct rt_rtmp_adapter *pAd, int infType)
-{
- struct rt_rtmp_chip_op *pChipOps = &pAd->chipOps;
-#ifdef RT30xx
-#ifdef RTMP_EFUSE_SUPPORT
- u32 eFuseCtrl, MacCsr0;
- int index;
-
- index = 0;
- do {
- RTMP_IO_READ32(pAd, MAC_CSR0, &MacCsr0);
- pAd->MACVersion = MacCsr0;
-
- if ((pAd->MACVersion != 0x00)
- && (pAd->MACVersion != 0xFFFFFFFF))
- break;
-
- RTMPusecDelay(10);
- } while (index++ < 100);
-
- pAd->bUseEfuse = FALSE;
- RTMP_IO_READ32(pAd, EFUSE_CTRL, &eFuseCtrl);
- pAd->bUseEfuse = ((eFuseCtrl & 0x80000000) == 0x80000000) ? 1 : 0;
- if (pAd->bUseEfuse) {
- pChipOps->eeinit = eFuse_init;
- pChipOps->eeread = rtmp_ee_efuse_read16;
- return 0;
- } else
- DBGPRINT(RT_DEBUG_TRACE, ("NVM is EEPROM\n"));
-#endif /* RTMP_EFUSE_SUPPORT // */
-#endif /* RT30xx // */
-
- switch (infType) {
-#ifdef RTMP_PCI_SUPPORT
- case RTMP_DEV_INF_PCI:
- pChipOps->eeinit = NULL;
- pChipOps->eeread = rtmp_ee_prom_read16;
- break;
-#endif /* RTMP_PCI_SUPPORT // */
-#ifdef RTMP_USB_SUPPORT
- case RTMP_DEV_INF_USB:
- pChipOps->eeinit = NULL;
- pChipOps->eeread = RTUSBReadEEPROM16;
- break;
-#endif /* RTMP_USB_SUPPORT // */
-
- default:
- DBGPRINT(RT_DEBUG_ERROR, ("RtmpChipOpsEepromHook() failed!\n"));
- break;
- }
-
- return 0;
-}
diff --git a/drivers/staging/rt2860/common/mlme.c b/drivers/staging/rt2860/common/mlme.c
deleted file mode 100644
index e48eac0..0000000
--- a/drivers/staging/rt2860/common/mlme.c
+++ /dev/null
@@ -1,6068 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- mlme.c
-
- Abstract:
-
- Revision History:
- Who When What
- -------- ---------- ----------------------------------------------
- John Chang 2004-08-25 Modify from RT2500 code base
- John Chang 2004-09-06 modified for RT2600
-*/
-
-#include "../rt_config.h"
-#include <stdarg.h>
-#include <linux/kernel.h>
-
-u8 CISCO_OUI[] = { 0x00, 0x40, 0x96 };
-
-u8 WPA_OUI[] = { 0x00, 0x50, 0xf2, 0x01 };
-u8 RSN_OUI[] = { 0x00, 0x0f, 0xac };
-u8 WME_INFO_ELEM[] = { 0x00, 0x50, 0xf2, 0x02, 0x00, 0x01 };
-u8 WME_PARM_ELEM[] = { 0x00, 0x50, 0xf2, 0x02, 0x01, 0x01 };
-u8 Ccx2QosInfo[] = { 0x00, 0x40, 0x96, 0x04 };
-u8 RALINK_OUI[] = { 0x00, 0x0c, 0x43 };
-u8 BROADCOM_OUI[] = { 0x00, 0x90, 0x4c };
-u8 WPS_OUI[] = { 0x00, 0x50, 0xf2, 0x04 };
-u8 PRE_N_HT_OUI[] = { 0x00, 0x90, 0x4c };
-
-u8 RateSwitchTable[] = {
-/* Item No. Mode Curr-MCS TrainUp TrainDown // Mode- Bit0: STBC, Bit1: Short GI, Bit4,5: Mode(0:CCK, 1:OFDM, 2:HT Mix, 3:HT GF) */
- 0x11, 0x00, 0, 0, 0, /* Initial used item after association */
- 0x00, 0x00, 0, 40, 101,
- 0x01, 0x00, 1, 40, 50,
- 0x02, 0x00, 2, 35, 45,
- 0x03, 0x00, 3, 20, 45,
- 0x04, 0x21, 0, 30, 50,
- 0x05, 0x21, 1, 20, 50,
- 0x06, 0x21, 2, 20, 50,
- 0x07, 0x21, 3, 15, 50,
- 0x08, 0x21, 4, 15, 30,
- 0x09, 0x21, 5, 10, 25,
- 0x0a, 0x21, 6, 8, 25,
- 0x0b, 0x21, 7, 8, 25,
- 0x0c, 0x20, 12, 15, 30,
- 0x0d, 0x20, 13, 8, 20,
- 0x0e, 0x20, 14, 8, 20,
- 0x0f, 0x20, 15, 8, 25,
- 0x10, 0x22, 15, 8, 25,
- 0x11, 0x00, 0, 0, 0,
- 0x12, 0x00, 0, 0, 0,
- 0x13, 0x00, 0, 0, 0,
- 0x14, 0x00, 0, 0, 0,
- 0x15, 0x00, 0, 0, 0,
- 0x16, 0x00, 0, 0, 0,
- 0x17, 0x00, 0, 0, 0,
- 0x18, 0x00, 0, 0, 0,
- 0x19, 0x00, 0, 0, 0,
- 0x1a, 0x00, 0, 0, 0,
- 0x1b, 0x00, 0, 0, 0,
- 0x1c, 0x00, 0, 0, 0,
- 0x1d, 0x00, 0, 0, 0,
- 0x1e, 0x00, 0, 0, 0,
- 0x1f, 0x00, 0, 0, 0,
-};
-
-u8 RateSwitchTable11B[] = {
-/* Item No. Mode Curr-MCS TrainUp TrainDown // Mode- Bit0: STBC, Bit1: Short GI, Bit4,5: Mode(0:CCK, 1:OFDM, 2:HT Mix, 3:HT GF) */
- 0x04, 0x03, 0, 0, 0, /* Initial used item after association */
- 0x00, 0x00, 0, 40, 101,
- 0x01, 0x00, 1, 40, 50,
- 0x02, 0x00, 2, 35, 45,
- 0x03, 0x00, 3, 20, 45,
-};
-
-u8 RateSwitchTable11BG[] = {
-/* Item No. Mode Curr-MCS TrainUp TrainDown // Mode- Bit0: STBC, Bit1: Short GI, Bit4,5: Mode(0:CCK, 1:OFDM, 2:HT Mix, 3:HT GF) */
- 0x0a, 0x00, 0, 0, 0, /* Initial used item after association */
- 0x00, 0x00, 0, 40, 101,
- 0x01, 0x00, 1, 40, 50,
- 0x02, 0x00, 2, 35, 45,
- 0x03, 0x00, 3, 20, 45,
- 0x04, 0x10, 2, 20, 35,
- 0x05, 0x10, 3, 16, 35,
- 0x06, 0x10, 4, 10, 25,
- 0x07, 0x10, 5, 16, 25,
- 0x08, 0x10, 6, 10, 25,
- 0x09, 0x10, 7, 10, 13,
-};
-
-u8 RateSwitchTable11G[] = {
-/* Item No. Mode Curr-MCS TrainUp TrainDown // Mode- Bit0: STBC, Bit1: Short GI, Bit4,5: Mode(0:CCK, 1:OFDM, 2:HT Mix, 3:HT GF) */
- 0x08, 0x00, 0, 0, 0, /* Initial used item after association */
- 0x00, 0x10, 0, 20, 101,
- 0x01, 0x10, 1, 20, 35,
- 0x02, 0x10, 2, 20, 35,
- 0x03, 0x10, 3, 16, 35,
- 0x04, 0x10, 4, 10, 25,
- 0x05, 0x10, 5, 16, 25,
- 0x06, 0x10, 6, 10, 25,
- 0x07, 0x10, 7, 10, 13,
-};
-
-u8 RateSwitchTable11N1S[] = {
-/* Item No. Mode Curr-MCS TrainUp TrainDown // Mode- Bit0: STBC, Bit1: Short GI, Bit4,5: Mode(0:CCK, 1:OFDM, 2:HT Mix, 3:HT GF) */
- 0x0c, 0x0a, 0, 0, 0, /* Initial used item after association */
- 0x00, 0x00, 0, 40, 101,
- 0x01, 0x00, 1, 40, 50,
- 0x02, 0x00, 2, 25, 45,
- 0x03, 0x21, 0, 20, 35,
- 0x04, 0x21, 1, 20, 35,
- 0x05, 0x21, 2, 20, 35,
- 0x06, 0x21, 3, 15, 35,
- 0x07, 0x21, 4, 15, 30,
- 0x08, 0x21, 5, 10, 25,
- 0x09, 0x21, 6, 8, 14,
- 0x0a, 0x21, 7, 8, 14,
- 0x0b, 0x23, 7, 8, 14,
-};
-
-u8 RateSwitchTable11N2S[] = {
-/* Item No. Mode Curr-MCS TrainUp TrainDown // Mode- Bit0: STBC, Bit1: Short GI, Bit4,5: Mode(0:CCK, 1:OFDM, 2:HT Mix, 3:HT GF) */
- 0x0e, 0x0c, 0, 0, 0, /* Initial used item after association */
- 0x00, 0x00, 0, 40, 101,
- 0x01, 0x00, 1, 40, 50,
- 0x02, 0x00, 2, 25, 45,
- 0x03, 0x21, 0, 20, 35,
- 0x04, 0x21, 1, 20, 35,
- 0x05, 0x21, 2, 20, 35,
- 0x06, 0x21, 3, 15, 35,
- 0x07, 0x21, 4, 15, 30,
- 0x08, 0x20, 11, 15, 30,
- 0x09, 0x20, 12, 15, 30,
- 0x0a, 0x20, 13, 8, 20,
- 0x0b, 0x20, 14, 8, 20,
- 0x0c, 0x20, 15, 8, 25,
- 0x0d, 0x22, 15, 8, 15,
-};
-
-u8 RateSwitchTable11N3S[] = {
-/* Item No. Mode Curr-MCS TrainUp TrainDown // Mode- Bit0: STBC, Bit1: Short GI, Bit4,5: Mode(0:CCK, 1:OFDM, 2:HT Mix, 3:HT GF) */
- 0x0b, 0x00, 0, 0, 0, /* 0x0a, 0x00, 0, 0, 0, // Initial used item after association */
- 0x00, 0x21, 0, 30, 101,
- 0x01, 0x21, 1, 20, 50,
- 0x02, 0x21, 2, 20, 50,
- 0x03, 0x21, 3, 15, 50,
- 0x04, 0x21, 4, 15, 30,
- 0x05, 0x20, 11, 15, 30, /* Required by System-Alan @ 20080812 */
- 0x06, 0x20, 12, 15, 30, /* 0x05, 0x20, 12, 15, 30, */
- 0x07, 0x20, 13, 8, 20, /* 0x06, 0x20, 13, 8, 20, */
- 0x08, 0x20, 14, 8, 20, /* 0x07, 0x20, 14, 8, 20, */
- 0x09, 0x20, 15, 8, 25, /* 0x08, 0x20, 15, 8, 25, */
- 0x0a, 0x22, 15, 8, 25, /* 0x09, 0x22, 15, 8, 25, */
-};
-
-u8 RateSwitchTable11N2SForABand[] = {
-/* Item No. Mode Curr-MCS TrainUp TrainDown // Mode- Bit0: STBC, Bit1: Short GI, Bit4,5: Mode(0:CCK, 1:OFDM, 2:HT Mix, 3:HT GF) */
- 0x0b, 0x09, 0, 0, 0, /* Initial used item after association */
- 0x00, 0x21, 0, 30, 101,
- 0x01, 0x21, 1, 20, 50,
- 0x02, 0x21, 2, 20, 50,
- 0x03, 0x21, 3, 15, 50,
- 0x04, 0x21, 4, 15, 30,
- 0x05, 0x21, 5, 15, 30,
- 0x06, 0x20, 12, 15, 30,
- 0x07, 0x20, 13, 8, 20,
- 0x08, 0x20, 14, 8, 20,
- 0x09, 0x20, 15, 8, 25,
- 0x0a, 0x22, 15, 8, 25,
-};
-
-u8 RateSwitchTable11N3SForABand[] = { /* 3*3 */
-/* Item No. Mode Curr-MCS TrainUp TrainDown // Mode- Bit0: STBC, Bit1: Short GI, Bit4,5: Mode(0:CCK, 1:OFDM, 2:HT Mix, 3:HT GF) */
- 0x0b, 0x09, 0, 0, 0, /* Initial used item after association */
- 0x00, 0x21, 0, 30, 101,
- 0x01, 0x21, 1, 20, 50,
- 0x02, 0x21, 2, 20, 50,
- 0x03, 0x21, 3, 15, 50,
- 0x04, 0x21, 4, 15, 30,
- 0x05, 0x21, 5, 15, 30,
- 0x06, 0x20, 12, 15, 30,
- 0x07, 0x20, 13, 8, 20,
- 0x08, 0x20, 14, 8, 20,
- 0x09, 0x20, 15, 8, 25,
- 0x0a, 0x22, 15, 8, 25,
-};
-
-u8 RateSwitchTable11BGN1S[] = {
-/* Item No. Mode Curr-MCS TrainUp TrainDown // Mode- Bit0: STBC, Bit1: Short GI, Bit4,5: Mode(0:CCK, 1:OFDM, 2:HT Mix, 3:HT GF) */
- 0x0c, 0x0a, 0, 0, 0, /* Initial used item after association */
- 0x00, 0x00, 0, 40, 101,
- 0x01, 0x00, 1, 40, 50,
- 0x02, 0x00, 2, 25, 45,
- 0x03, 0x21, 0, 20, 35,
- 0x04, 0x21, 1, 20, 35,
- 0x05, 0x21, 2, 20, 35,
- 0x06, 0x21, 3, 15, 35,
- 0x07, 0x21, 4, 15, 30,
- 0x08, 0x21, 5, 10, 25,
- 0x09, 0x21, 6, 8, 14,
- 0x0a, 0x21, 7, 8, 14,
- 0x0b, 0x23, 7, 8, 14,
-};
-
-u8 RateSwitchTable11BGN2S[] = {
-/* Item No. Mode Curr-MCS TrainUp TrainDown // Mode- Bit0: STBC, Bit1: Short GI, Bit4,5: Mode(0:CCK, 1:OFDM, 2:HT Mix, 3:HT GF) */
- 0x0e, 0x0c, 0, 0, 0, /* Initial used item after association */
- 0x00, 0x00, 0, 40, 101,
- 0x01, 0x00, 1, 40, 50,
- 0x02, 0x00, 2, 25, 45,
- 0x03, 0x21, 0, 20, 35,
- 0x04, 0x21, 1, 20, 35,
- 0x05, 0x21, 2, 20, 35,
- 0x06, 0x21, 3, 15, 35,
- 0x07, 0x21, 4, 15, 30,
- 0x08, 0x20, 11, 15, 30,
- 0x09, 0x20, 12, 15, 30,
- 0x0a, 0x20, 13, 8, 20,
- 0x0b, 0x20, 14, 8, 20,
- 0x0c, 0x20, 15, 8, 25,
- 0x0d, 0x22, 15, 8, 15,
-};
-
-u8 RateSwitchTable11BGN3S[] = { /* 3*3 */
-/* Item No. Mode Curr-MCS TrainUp TrainDown // Mode- Bit0: STBC, Bit1: Short GI, Bit4,5: Mode(0:CCK, 1:OFDM, 2:HT Mix, 3:HT GF) */
- 0x0a, 0x00, 0, 0, 0, /* Initial used item after association */
- 0x00, 0x21, 0, 30, 101, /*50 */
- 0x01, 0x21, 1, 20, 50,
- 0x02, 0x21, 2, 20, 50,
- 0x03, 0x21, 3, 20, 50,
- 0x04, 0x21, 4, 15, 50,
- 0x05, 0x20, 20, 15, 30,
- 0x06, 0x20, 21, 8, 20,
- 0x07, 0x20, 22, 8, 20,
- 0x08, 0x20, 23, 8, 25,
- 0x09, 0x22, 23, 8, 25,
-};
-
-u8 RateSwitchTable11BGN2SForABand[] = {
-/* Item No. Mode Curr-MCS TrainUp TrainDown // Mode- Bit0: STBC, Bit1: Short GI, Bit4,5: Mode(0:CCK, 1:OFDM, 2:HT Mix, 3:HT GF) */
- 0x0b, 0x09, 0, 0, 0, /* Initial used item after association */
- 0x00, 0x21, 0, 30, 101, /*50 */
- 0x01, 0x21, 1, 20, 50,
- 0x02, 0x21, 2, 20, 50,
- 0x03, 0x21, 3, 15, 50,
- 0x04, 0x21, 4, 15, 30,
- 0x05, 0x21, 5, 15, 30,
- 0x06, 0x20, 12, 15, 30,
- 0x07, 0x20, 13, 8, 20,
- 0x08, 0x20, 14, 8, 20,
- 0x09, 0x20, 15, 8, 25,
- 0x0a, 0x22, 15, 8, 25,
-};
-
-u8 RateSwitchTable11BGN3SForABand[] = { /* 3*3 */
-/* Item No. Mode Curr-MCS TrainUp TrainDown // Mode- Bit0: STBC, Bit1: Short GI, Bit4,5: Mode(0:CCK, 1:OFDM, 2:HT Mix, 3:HT GF) */
- 0x0c, 0x09, 0, 0, 0, /* Initial used item after association */
- 0x00, 0x21, 0, 30, 101, /*50 */
- 0x01, 0x21, 1, 20, 50,
- 0x02, 0x21, 2, 20, 50,
- 0x03, 0x21, 3, 15, 50,
- 0x04, 0x21, 4, 15, 30,
- 0x05, 0x21, 5, 15, 30,
- 0x06, 0x21, 12, 15, 30,
- 0x07, 0x20, 20, 15, 30,
- 0x08, 0x20, 21, 8, 20,
- 0x09, 0x20, 22, 8, 20,
- 0x0a, 0x20, 23, 8, 25,
- 0x0b, 0x22, 23, 8, 25,
-};
-
-extern u8 OfdmRateToRxwiMCS[];
-/* since RT61 has better RX sensibility, we have to limit TX ACK rate not to exceed our normal data TX rate. */
-/* otherwise the WLAN peer may not be able to receive the ACK thus downgrade its data TX rate */
-unsigned long BasicRateMask[12] =
- { 0xfffff001 /* 1-Mbps */ , 0xfffff003 /* 2 Mbps */ , 0xfffff007 /* 5.5 */ ,
-0xfffff00f /* 11 */ ,
- 0xfffff01f /* 6 */ , 0xfffff03f /* 9 */ , 0xfffff07f /* 12 */ ,
- 0xfffff0ff /* 18 */ ,
- 0xfffff1ff /* 24 */ , 0xfffff3ff /* 36 */ , 0xfffff7ff /* 48 */ ,
- 0xffffffff /* 54 */
-};
-
-u8 BROADCAST_ADDR[MAC_ADDR_LEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
-u8 ZERO_MAC_ADDR[MAC_ADDR_LEN] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
-
-/* e.g. RssiSafeLevelForTxRate[RATE_36]" means if the current RSSI is greater than */
-/* this value, then it's quaranteed capable of operating in 36 mbps TX rate in */
-/* clean environment. */
-/* TxRate: 1 2 5.5 11 6 9 12 18 24 36 48 54 72 100 */
-char RssiSafeLevelForTxRate[] =
- { -92, -91, -90, -87, -88, -86, -85, -83, -81, -78, -72, -71, -40, -40 };
-
-u8 RateIdToMbps[] = { 1, 2, 5, 11, 6, 9, 12, 18, 24, 36, 48, 54, 72, 100 };
-u16 RateIdTo500Kbps[] =
- { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108, 144, 200 };
-
-u8 SsidIe = IE_SSID;
-u8 SupRateIe = IE_SUPP_RATES;
-u8 ExtRateIe = IE_EXT_SUPP_RATES;
-u8 HtCapIe = IE_HT_CAP;
-u8 AddHtInfoIe = IE_ADD_HT;
-u8 NewExtChanIe = IE_SECONDARY_CH_OFFSET;
-u8 ErpIe = IE_ERP;
-u8 DsIe = IE_DS_PARM;
-u8 TimIe = IE_TIM;
-u8 WpaIe = IE_WPA;
-u8 Wpa2Ie = IE_WPA2;
-u8 IbssIe = IE_IBSS_PARM;
-
-extern u8 WPA_OUI[];
-
-u8 SES_OUI[] = { 0x00, 0x90, 0x4c };
-
-u8 ZeroSsid[32] =
- { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x00, 0x00, 0x00, 0x00
-};
-
-/*
- ==========================================================================
- Description:
- initialize the MLME task and its data structure (queue, spinlock,
- timer, state machines).
-
- IRQL = PASSIVE_LEVEL
-
- Return:
- always return NDIS_STATUS_SUCCESS
-
- ==========================================================================
-*/
-int MlmeInit(struct rt_rtmp_adapter *pAd)
-{
- int Status = NDIS_STATUS_SUCCESS;
-
- DBGPRINT(RT_DEBUG_TRACE, ("--> MLME Initialize\n"));
-
- do {
- Status = MlmeQueueInit(&pAd->Mlme.Queue);
- if (Status != NDIS_STATUS_SUCCESS)
- break;
-
- pAd->Mlme.bRunning = FALSE;
- NdisAllocateSpinLock(&pAd->Mlme.TaskLock);
-
- {
- BssTableInit(&pAd->ScanTab);
-
- /* init STA state machines */
- AssocStateMachineInit(pAd, &pAd->Mlme.AssocMachine,
- pAd->Mlme.AssocFunc);
- AuthStateMachineInit(pAd, &pAd->Mlme.AuthMachine,
- pAd->Mlme.AuthFunc);
- AuthRspStateMachineInit(pAd, &pAd->Mlme.AuthRspMachine,
- pAd->Mlme.AuthRspFunc);
- SyncStateMachineInit(pAd, &pAd->Mlme.SyncMachine,
- pAd->Mlme.SyncFunc);
-
- /* Since we are using switch/case to implement it, the init is different from the above */
- /* state machine init */
- MlmeCntlInit(pAd, &pAd->Mlme.CntlMachine, NULL);
- }
-
- WpaStateMachineInit(pAd, &pAd->Mlme.WpaMachine,
- pAd->Mlme.WpaFunc);
-
- ActionStateMachineInit(pAd, &pAd->Mlme.ActMachine,
- pAd->Mlme.ActFunc);
-
- /* Init mlme periodic timer */
- RTMPInitTimer(pAd, &pAd->Mlme.PeriodicTimer,
- GET_TIMER_FUNCTION(MlmePeriodicExec), pAd, TRUE);
-
- /* Set mlme periodic timer */
- RTMPSetTimer(&pAd->Mlme.PeriodicTimer, MLME_TASK_EXEC_INTV);
-
- /* software-based RX Antenna diversity */
- RTMPInitTimer(pAd, &pAd->Mlme.RxAntEvalTimer,
- GET_TIMER_FUNCTION(AsicRxAntEvalTimeout), pAd,
- FALSE);
-
- {
-#ifdef RTMP_PCI_SUPPORT
- if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_PCIE_DEVICE)) {
- /* only PCIe cards need these two timers */
- RTMPInitTimer(pAd, &pAd->Mlme.PsPollTimer,
- GET_TIMER_FUNCTION
- (PsPollWakeExec), pAd, FALSE);
- RTMPInitTimer(pAd, &pAd->Mlme.RadioOnOffTimer,
- GET_TIMER_FUNCTION(RadioOnExec),
- pAd, FALSE);
- }
-#endif /* RTMP_PCI_SUPPORT // */
-
- RTMPInitTimer(pAd, &pAd->Mlme.LinkDownTimer,
- GET_TIMER_FUNCTION(LinkDownExec), pAd,
- FALSE);
-
-#ifdef RTMP_MAC_USB
- RTMPInitTimer(pAd, &pAd->Mlme.AutoWakeupTimer,
- GET_TIMER_FUNCTION
- (RtmpUsbStaAsicForceWakeupTimeout), pAd,
- FALSE);
- pAd->Mlme.AutoWakeupTimerRunning = FALSE;
-#endif /* RTMP_MAC_USB // */
- }
-
- } while (FALSE);
-
- DBGPRINT(RT_DEBUG_TRACE, ("<-- MLME Initialize\n"));
-
- return Status;
-}
-
-/*
- ==========================================================================
- Description:
- main loop of the MLME
- Pre:
- Mlme has to be initialized, and there are something inside the queue
- Note:
- This function is invoked from MPSetInformation and MPReceive;
- This task guarantee only one MlmeHandler will run.
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
- */
-void MlmeHandler(struct rt_rtmp_adapter *pAd)
-{
- struct rt_mlme_queue_elem *Elem = NULL;
-
- /* Only accept MLME and Frame from peer side, no other (control/data) frame should */
- /* get into this state machine */
-
- NdisAcquireSpinLock(&pAd->Mlme.TaskLock);
- if (pAd->Mlme.bRunning) {
- NdisReleaseSpinLock(&pAd->Mlme.TaskLock);
- return;
- } else {
- pAd->Mlme.bRunning = TRUE;
- }
- NdisReleaseSpinLock(&pAd->Mlme.TaskLock);
-
- while (!MlmeQueueEmpty(&pAd->Mlme.Queue)) {
- if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_MLME_RESET_IN_PROGRESS) ||
- RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS) ||
- RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST)) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("Device Halted or Removed or MlmeRest, exit MlmeHandler! (queue num = %ld)\n",
- pAd->Mlme.Queue.Num));
- break;
- }
- /*From message type, determine which state machine I should drive */
- if (MlmeDequeue(&pAd->Mlme.Queue, &Elem)) {
-#ifdef RTMP_MAC_USB
- if (Elem->MsgType == MT2_RESET_CONF) {
- DBGPRINT_RAW(RT_DEBUG_TRACE,
- ("reset MLME state machine!\n"));
- MlmeRestartStateMachine(pAd);
- Elem->Occupied = FALSE;
- Elem->MsgLen = 0;
- continue;
- }
-#endif /* RTMP_MAC_USB // */
-
- /* if dequeue success */
- switch (Elem->Machine) {
- /* STA state machines */
- case ASSOC_STATE_MACHINE:
- StateMachinePerformAction(pAd,
- &pAd->Mlme.
- AssocMachine, Elem);
- break;
- case AUTH_STATE_MACHINE:
- StateMachinePerformAction(pAd,
- &pAd->Mlme.
- AuthMachine, Elem);
- break;
- case AUTH_RSP_STATE_MACHINE:
- StateMachinePerformAction(pAd,
- &pAd->Mlme.
- AuthRspMachine, Elem);
- break;
- case SYNC_STATE_MACHINE:
- StateMachinePerformAction(pAd,
- &pAd->Mlme.
- SyncMachine, Elem);
- break;
- case MLME_CNTL_STATE_MACHINE:
- MlmeCntlMachinePerformAction(pAd,
- &pAd->Mlme.
- CntlMachine, Elem);
- break;
- case WPA_PSK_STATE_MACHINE:
- StateMachinePerformAction(pAd,
- &pAd->Mlme.
- WpaPskMachine, Elem);
- break;
-
- case ACTION_STATE_MACHINE:
- StateMachinePerformAction(pAd,
- &pAd->Mlme.ActMachine,
- Elem);
- break;
-
- case WPA_STATE_MACHINE:
- StateMachinePerformAction(pAd,
- &pAd->Mlme.WpaMachine,
- Elem);
- break;
-
- default:
- DBGPRINT(RT_DEBUG_TRACE,
- ("ERROR: Illegal machine %ld in MlmeHandler()\n",
- Elem->Machine));
- break;
- } /* end of switch */
-
- /* free MLME element */
- Elem->Occupied = FALSE;
- Elem->MsgLen = 0;
-
- } else {
- DBGPRINT_ERR("MlmeHandler: MlmeQueue empty\n");
- }
- }
-
- NdisAcquireSpinLock(&pAd->Mlme.TaskLock);
- pAd->Mlme.bRunning = FALSE;
- NdisReleaseSpinLock(&pAd->Mlme.TaskLock);
-}
-
-/*
- ==========================================================================
- Description:
- Destructor of MLME (Destroy queue, state machine, spin lock and timer)
- Parameters:
- Adapter - NIC Adapter pointer
- Post:
- The MLME task will no longer work properly
-
- IRQL = PASSIVE_LEVEL
-
- ==========================================================================
- */
-void MlmeHalt(struct rt_rtmp_adapter *pAd)
-{
- BOOLEAN Cancelled;
-
- DBGPRINT(RT_DEBUG_TRACE, ("==> MlmeHalt\n"));
-
- if (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST)) {
- /* disable BEACON generation and other BEACON related hardware timers */
- AsicDisableSync(pAd);
- }
-
- {
- /* Cancel pending timers */
- RTMPCancelTimer(&pAd->MlmeAux.AssocTimer, &Cancelled);
- RTMPCancelTimer(&pAd->MlmeAux.ReassocTimer, &Cancelled);
- RTMPCancelTimer(&pAd->MlmeAux.DisassocTimer, &Cancelled);
- RTMPCancelTimer(&pAd->MlmeAux.AuthTimer, &Cancelled);
- RTMPCancelTimer(&pAd->MlmeAux.BeaconTimer, &Cancelled);
- RTMPCancelTimer(&pAd->MlmeAux.ScanTimer, &Cancelled);
-
-#ifdef RTMP_MAC_PCI
- if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_PCIE_DEVICE)
- && (pAd->StaCfg.PSControl.field.EnableNewPS == TRUE)) {
- RTMPCancelTimer(&pAd->Mlme.PsPollTimer, &Cancelled);
- RTMPCancelTimer(&pAd->Mlme.RadioOnOffTimer, &Cancelled);
- }
-#endif /* RTMP_MAC_PCI // */
-
- RTMPCancelTimer(&pAd->Mlme.LinkDownTimer, &Cancelled);
-
-#ifdef RTMP_MAC_USB
- RTMPCancelTimer(&pAd->Mlme.AutoWakeupTimer, &Cancelled);
-#endif /* RTMP_MAC_USB // */
- }
-
- RTMPCancelTimer(&pAd->Mlme.PeriodicTimer, &Cancelled);
- RTMPCancelTimer(&pAd->Mlme.RxAntEvalTimer, &Cancelled);
-
- if (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST)) {
- struct rt_rtmp_chip_op *pChipOps = &pAd->chipOps;
-
- /* Set LED */
- RTMPSetLED(pAd, LED_HALT);
- RTMPSetSignalLED(pAd, -100); /* Force signal strength Led to be turned off, firmware is not done it. */
-#ifdef RTMP_MAC_USB
- {
- LED_CFG_STRUC LedCfg;
- RTMP_IO_READ32(pAd, LED_CFG, &LedCfg.word);
- LedCfg.field.LedPolar = 0;
- LedCfg.field.RLedMode = 0;
- LedCfg.field.GLedMode = 0;
- LedCfg.field.YLedMode = 0;
- RTMP_IO_WRITE32(pAd, LED_CFG, LedCfg.word);
- }
-#endif /* RTMP_MAC_USB // */
-
- if (pChipOps->AsicHaltAction)
- pChipOps->AsicHaltAction(pAd);
- }
-
- RTMPusecDelay(5000); /* 5 msec to guarantee Ant Diversity timer canceled */
-
- MlmeQueueDestroy(&pAd->Mlme.Queue);
- NdisFreeSpinLock(&pAd->Mlme.TaskLock);
-
- DBGPRINT(RT_DEBUG_TRACE, ("<== MlmeHalt\n"));
-}
-
-void MlmeResetRalinkCounters(struct rt_rtmp_adapter *pAd)
-{
- pAd->RalinkCounters.LastOneSecRxOkDataCnt =
- pAd->RalinkCounters.OneSecRxOkDataCnt;
- /* clear all OneSecxxx counters. */
- pAd->RalinkCounters.OneSecBeaconSentCnt = 0;
- pAd->RalinkCounters.OneSecFalseCCACnt = 0;
- pAd->RalinkCounters.OneSecRxFcsErrCnt = 0;
- pAd->RalinkCounters.OneSecRxOkCnt = 0;
- pAd->RalinkCounters.OneSecTxFailCount = 0;
- pAd->RalinkCounters.OneSecTxNoRetryOkCount = 0;
- pAd->RalinkCounters.OneSecTxRetryOkCount = 0;
- pAd->RalinkCounters.OneSecRxOkDataCnt = 0;
- pAd->RalinkCounters.OneSecReceivedByteCount = 0;
- pAd->RalinkCounters.OneSecTransmittedByteCount = 0;
-
- /* TODO: for debug only. to be removed */
- pAd->RalinkCounters.OneSecOsTxCount[QID_AC_BE] = 0;
- pAd->RalinkCounters.OneSecOsTxCount[QID_AC_BK] = 0;
- pAd->RalinkCounters.OneSecOsTxCount[QID_AC_VI] = 0;
- pAd->RalinkCounters.OneSecOsTxCount[QID_AC_VO] = 0;
- pAd->RalinkCounters.OneSecDmaDoneCount[QID_AC_BE] = 0;
- pAd->RalinkCounters.OneSecDmaDoneCount[QID_AC_BK] = 0;
- pAd->RalinkCounters.OneSecDmaDoneCount[QID_AC_VI] = 0;
- pAd->RalinkCounters.OneSecDmaDoneCount[QID_AC_VO] = 0;
- pAd->RalinkCounters.OneSecTxDoneCount = 0;
- pAd->RalinkCounters.OneSecRxCount = 0;
- pAd->RalinkCounters.OneSecTxAggregationCount = 0;
- pAd->RalinkCounters.OneSecRxAggregationCount = 0;
-
- return;
-}
-
-/*
- ==========================================================================
- Description:
- This routine is executed periodically to -
- 1. Decide if it's a right time to turn on PwrMgmt bit of all
- outgoiing frames
- 2. Calculate ChannelQuality based on statistics of the last
- period, so that TX rate won't toggling very frequently between a
- successful TX and a failed TX.
- 3. If the calculated ChannelQuality indicated current connection not
- healthy, then a ROAMing attempt is tried here.
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
- */
-#define ADHOC_BEACON_LOST_TIME (8*OS_HZ) /* 8 sec */
-void MlmePeriodicExec(void *SystemSpecific1,
- void *FunctionContext,
- void *SystemSpecific2, void *SystemSpecific3)
-{
- unsigned long TxTotalCnt;
- struct rt_rtmp_adapter *pAd = (struct rt_rtmp_adapter *)FunctionContext;
-
-#ifdef RTMP_MAC_PCI
- {
- /* If Hardware controlled Radio enabled, we have to check GPIO pin2 every 2 second. */
- /* Move code to here, because following code will return when radio is off */
- if ((pAd->Mlme.PeriodicRound % (MLME_TASK_EXEC_MULTIPLE * 2) ==
- 0) && (pAd->StaCfg.bHardwareRadio == TRUE)
- && (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST))
- && (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS))
- /*&&(pAd->bPCIclkOff == FALSE) */
- ) {
- u32 data = 0;
-
- /* Read GPIO pin2 as Hardware controlled radio state */
-#ifndef RT3090
- RTMP_IO_READ32(pAd, GPIO_CTRL_CFG, &data);
-#endif /* RT3090 // */
-/*KH(PCIE PS):Added based on Jane<-- */
-#ifdef RT3090
-/* Read GPIO pin2 as Hardware controlled radio state */
-/* We need to Read GPIO if HW said so no mater what advance power saving */
- if ((pAd->OpMode == OPMODE_STA) && (IDLE_ON(pAd))
- &&
- (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_IDLE_RADIO_OFF))
- && (pAd->StaCfg.PSControl.field.EnablePSinIdle ==
- TRUE)) {
- /* Want to make sure device goes to L0 state before reading register. */
- RTMPPCIeLinkCtrlValueRestore(pAd, 0);
- RTMP_IO_FORCE_READ32(pAd, GPIO_CTRL_CFG, &data);
- RTMPPCIeLinkCtrlSetting(pAd, 3);
- } else
- RTMP_IO_FORCE_READ32(pAd, GPIO_CTRL_CFG, &data);
-#endif /* RT3090 // */
-/*KH(PCIE PS):Added based on Jane--> */
-
- if (data & 0x04) {
- pAd->StaCfg.bHwRadio = TRUE;
- } else {
- pAd->StaCfg.bHwRadio = FALSE;
- }
- if (pAd->StaCfg.bRadio !=
- (pAd->StaCfg.bHwRadio && pAd->StaCfg.bSwRadio)) {
- pAd->StaCfg.bRadio = (pAd->StaCfg.bHwRadio
- && pAd->StaCfg.bSwRadio);
- if (pAd->StaCfg.bRadio == TRUE) {
- MlmeRadioOn(pAd);
- /* Update extra information */
- pAd->ExtraInfo = EXTRA_INFO_CLEAR;
- } else {
- MlmeRadioOff(pAd);
- /* Update extra information */
- pAd->ExtraInfo = HW_RADIO_OFF;
- }
- }
- }
- }
-#endif /* RTMP_MAC_PCI // */
-
- /* Do nothing if the driver is starting halt state. */
- /* This might happen when timer already been fired before cancel timer with mlmehalt */
- if ((RTMP_TEST_FLAG(pAd, (fRTMP_ADAPTER_HALT_IN_PROGRESS |
- fRTMP_ADAPTER_RADIO_OFF |
- fRTMP_ADAPTER_RADIO_MEASUREMENT |
- fRTMP_ADAPTER_RESET_IN_PROGRESS))))
- return;
-
- RTMP_MLME_PRE_SANITY_CHECK(pAd);
-
- {
- /* Do nothing if monitor mode is on */
- if (MONITOR_ON(pAd))
- return;
-
- if (pAd->Mlme.PeriodicRound & 0x1) {
- /* This is the fix for wifi 11n extension channel overlapping test case. for 2860D */
- if (((pAd->MACVersion & 0xffff) == 0x0101) &&
- (STA_TGN_WIFI_ON(pAd)) &&
- (pAd->CommonCfg.IOTestParm.bToggle == FALSE))
- {
- RTMP_IO_WRITE32(pAd, TXOP_CTRL_CFG, 0x24Bf);
- pAd->CommonCfg.IOTestParm.bToggle = TRUE;
- } else if ((STA_TGN_WIFI_ON(pAd)) &&
- ((pAd->MACVersion & 0xffff) == 0x0101)) {
- RTMP_IO_WRITE32(pAd, TXOP_CTRL_CFG, 0x243f);
- pAd->CommonCfg.IOTestParm.bToggle = FALSE;
- }
- }
- }
-
- pAd->bUpdateBcnCntDone = FALSE;
-
-/* RECBATimerTimeout(SystemSpecific1,FunctionContext,SystemSpecific2,SystemSpecific3); */
- pAd->Mlme.PeriodicRound++;
-
-#ifdef RTMP_MAC_USB
- /* execute every 100ms, update the Tx FIFO Cnt for update Tx Rate. */
- NICUpdateFifoStaCounters(pAd);
-#endif /* RTMP_MAC_USB // */
-
- /* execute every 500ms */
- if ((pAd->Mlme.PeriodicRound % 5 == 0)
- && RTMPAutoRateSwitchCheck(pAd)
- /*(OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_TX_RATE_SWITCH_ENABLED)) */ )
- {
- /* perform dynamic tx rate switching based on past TX history */
- {
- if ((OPSTATUS_TEST_FLAG
- (pAd, fOP_STATUS_MEDIA_STATE_CONNECTED)
- )
- && (!OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_DOZE)))
- MlmeDynamicTxRateSwitching(pAd);
- }
- }
- /* Normal 1 second Mlme PeriodicExec. */
- if (pAd->Mlme.PeriodicRound % MLME_TASK_EXEC_MULTIPLE == 0) {
- pAd->Mlme.OneSecPeriodicRound++;
-
- /*ORIBATimerTimeout(pAd); */
-
- /* Media status changed, report to NDIS */
- if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_MEDIA_STATE_CHANGE)) {
- RTMP_CLEAR_FLAG(pAd, fRTMP_ADAPTER_MEDIA_STATE_CHANGE);
- if (OPSTATUS_TEST_FLAG
- (pAd, fOP_STATUS_MEDIA_STATE_CONNECTED)) {
- pAd->IndicateMediaState =
- NdisMediaStateConnected;
- RTMP_IndicateMediaState(pAd);
-
- } else {
- pAd->IndicateMediaState =
- NdisMediaStateDisconnected;
- RTMP_IndicateMediaState(pAd);
- }
- }
-
- NdisGetSystemUpTime(&pAd->Mlme.Now32);
-
- /* add the most up-to-date h/w raw counters into software variable, so that */
- /* the dynamic tuning mechanism below are based on most up-to-date information */
- NICUpdateRawCounters(pAd);
-
-#ifdef RTMP_MAC_USB
- RTUSBWatchDog(pAd);
-#endif /* RTMP_MAC_USB // */
-
- /* Need statistics after read counter. So put after NICUpdateRawCounters */
- ORIBATimerTimeout(pAd);
-
- /* if MGMT RING is full more than twice within 1 second, we consider there's */
- /* a hardware problem stucking the TX path. In this case, try a hardware reset */
- /* to recover the system */
- /* if (pAd->RalinkCounters.MgmtRingFullCount >= 2) */
- /* RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_HARDWARE_ERROR); */
- /* else */
- /* pAd->RalinkCounters.MgmtRingFullCount = 0; */
-
- /* The time period for checking antenna is according to traffic */
- {
- if (pAd->Mlme.bEnableAutoAntennaCheck) {
- TxTotalCnt =
- pAd->RalinkCounters.OneSecTxNoRetryOkCount +
- pAd->RalinkCounters.OneSecTxRetryOkCount +
- pAd->RalinkCounters.OneSecTxFailCount;
-
- /* dynamic adjust antenna evaluation period according to the traffic */
- if (TxTotalCnt > 50) {
- if (pAd->Mlme.OneSecPeriodicRound %
- 10 == 0) {
- AsicEvaluateRxAnt(pAd);
- }
- } else {
- if (pAd->Mlme.OneSecPeriodicRound % 3 ==
- 0) {
- AsicEvaluateRxAnt(pAd);
- }
- }
- }
- }
-
- STAMlmePeriodicExec(pAd);
-
- MlmeResetRalinkCounters(pAd);
-
- {
-#ifdef RTMP_MAC_PCI
- if (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST)
- && (pAd->bPCIclkOff == FALSE))
-#endif /* RTMP_MAC_PCI // */
- {
- /* When Adhoc beacon is enabled and RTS/CTS is enabled, there is a chance that hardware MAC FSM will run into a deadlock */
- /* and sending CTS-to-self over and over. */
- /* Software Patch Solution: */
- /* 1. Polling debug state register 0x10F4 every one second. */
- /* 2. If in 0x10F4 the ((bit29==1) && (bit7==1)) OR ((bit29==1) && (bit5==1)), it means the deadlock has occurred. */
- /* 3. If the deadlock occurred, reset MAC/BBP by setting 0x1004 to 0x0001 for a while then setting it back to 0x000C again. */
-
- u32 MacReg = 0;
-
- RTMP_IO_READ32(pAd, 0x10F4, &MacReg);
- if (((MacReg & 0x20000000) && (MacReg & 0x80))
- || ((MacReg & 0x20000000)
- && (MacReg & 0x20))) {
- RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, 0x1);
- RTMPusecDelay(1);
- RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, 0xC);
-
- DBGPRINT(RT_DEBUG_WARN,
- ("Warning, MAC specific condition occurs \n"));
- }
- }
- }
-
- RTMP_MLME_HANDLER(pAd);
- }
-
- pAd->bUpdateBcnCntDone = FALSE;
-}
-
-/*
- ==========================================================================
- Validate SSID for connection try and rescan purpose
- Valid SSID will have visible chars only.
- The valid length is from 0 to 32.
- IRQL = DISPATCH_LEVEL
- ==========================================================================
- */
-BOOLEAN MlmeValidateSSID(u8 *pSsid, u8 SsidLen)
-{
- int index;
-
- if (SsidLen > MAX_LEN_OF_SSID)
- return (FALSE);
-
- /* Check each character value */
- for (index = 0; index < SsidLen; index++) {
- if (pSsid[index] < 0x20)
- return (FALSE);
- }
-
- /* All checked */
- return (TRUE);
-}
-
-void MlmeSelectTxRateTable(struct rt_rtmp_adapter *pAd,
- struct rt_mac_table_entry *pEntry,
- u8 ** ppTable,
- u8 *pTableSize, u8 *pInitTxRateIdx)
-{
- do {
- /* decide the rate table for tuning */
- if (pAd->CommonCfg.TxRateTableSize > 0) {
- *ppTable = RateSwitchTable;
- *pTableSize = RateSwitchTable[0];
- *pInitTxRateIdx = RateSwitchTable[1];
-
- break;
- }
-
- if ((pAd->OpMode == OPMODE_STA) && ADHOC_ON(pAd)) {
- if ((pAd->CommonCfg.PhyMode >= PHY_11ABGN_MIXED) && (pEntry->HTCapability.MCSSet[0] == 0xff) && ((pEntry->HTCapability.MCSSet[1] == 0x00) || (pAd->Antenna.field.TxPath == 1))) { /* 11N 1S Adhoc */
- *ppTable = RateSwitchTable11N1S;
- *pTableSize = RateSwitchTable11N1S[0];
- *pInitTxRateIdx = RateSwitchTable11N1S[1];
-
- } else if ((pAd->CommonCfg.PhyMode >= PHY_11ABGN_MIXED) && (pEntry->HTCapability.MCSSet[0] == 0xff) && (pEntry->HTCapability.MCSSet[1] == 0xff) && (pAd->Antenna.field.TxPath == 2)) { /* 11N 2S Adhoc */
- if (pAd->LatchRfRegs.Channel <= 14) {
- *ppTable = RateSwitchTable11N2S;
- *pTableSize = RateSwitchTable11N2S[0];
- *pInitTxRateIdx =
- RateSwitchTable11N2S[1];
- } else {
- *ppTable = RateSwitchTable11N2SForABand;
- *pTableSize =
- RateSwitchTable11N2SForABand[0];
- *pInitTxRateIdx =
- RateSwitchTable11N2SForABand[1];
- }
-
- } else if ((pEntry->RateLen == 4)
- && (pEntry->HTCapability.MCSSet[0] == 0)
- && (pEntry->HTCapability.MCSSet[1] == 0)
- ) {
- *ppTable = RateSwitchTable11B;
- *pTableSize = RateSwitchTable11B[0];
- *pInitTxRateIdx = RateSwitchTable11B[1];
-
- } else if (pAd->LatchRfRegs.Channel <= 14) {
- *ppTable = RateSwitchTable11BG;
- *pTableSize = RateSwitchTable11BG[0];
- *pInitTxRateIdx = RateSwitchTable11BG[1];
-
- } else {
- *ppTable = RateSwitchTable11G;
- *pTableSize = RateSwitchTable11G[0];
- *pInitTxRateIdx = RateSwitchTable11G[1];
-
- }
- break;
- }
- /*if ((pAd->StaActive.SupRateLen + pAd->StaActive.ExtRateLen == 12) && (pAd->StaActive.SupportedPhyInfo.MCSSet[0] == 0xff) && */
- /* ((pAd->StaActive.SupportedPhyInfo.MCSSet[1] == 0x00) || (pAd->Antenna.field.TxPath == 1))) */
- if (((pEntry->RateLen == 12) || (pAd->OpMode == OPMODE_STA)) && (pEntry->HTCapability.MCSSet[0] == 0xff) && ((pEntry->HTCapability.MCSSet[1] == 0x00) || (pAd->CommonCfg.TxStream == 1))) { /* 11BGN 1S AP */
- *ppTable = RateSwitchTable11BGN1S;
- *pTableSize = RateSwitchTable11BGN1S[0];
- *pInitTxRateIdx = RateSwitchTable11BGN1S[1];
-
- break;
- }
- /*else if ((pAd->StaActive.SupRateLen + pAd->StaActive.ExtRateLen == 12) && (pAd->StaActive.SupportedPhyInfo.MCSSet[0] == 0xff) && */
- /* (pAd->StaActive.SupportedPhyInfo.MCSSet[1] == 0xff) && (pAd->Antenna.field.TxPath == 2)) */
- if (((pEntry->RateLen == 12) || (pAd->OpMode == OPMODE_STA)) && (pEntry->HTCapability.MCSSet[0] == 0xff) && (pEntry->HTCapability.MCSSet[1] == 0xff) && (pAd->CommonCfg.TxStream == 2)) { /* 11BGN 2S AP */
- if (pAd->LatchRfRegs.Channel <= 14) {
- *ppTable = RateSwitchTable11BGN2S;
- *pTableSize = RateSwitchTable11BGN2S[0];
- *pInitTxRateIdx = RateSwitchTable11BGN2S[1];
-
- } else {
- *ppTable = RateSwitchTable11BGN2SForABand;
- *pTableSize = RateSwitchTable11BGN2SForABand[0];
- *pInitTxRateIdx =
- RateSwitchTable11BGN2SForABand[1];
-
- }
- break;
- }
- /*else if ((pAd->StaActive.SupportedPhyInfo.MCSSet[0] == 0xff) && ((pAd->StaActive.SupportedPhyInfo.MCSSet[1] == 0x00) || (pAd->Antenna.field.TxPath == 1))) */
- if ((pEntry->HTCapability.MCSSet[0] == 0xff) && ((pEntry->HTCapability.MCSSet[1] == 0x00) || (pAd->CommonCfg.TxStream == 1))) { /* 11N 1S AP */
- *ppTable = RateSwitchTable11N1S;
- *pTableSize = RateSwitchTable11N1S[0];
- *pInitTxRateIdx = RateSwitchTable11N1S[1];
-
- break;
- }
- /*else if ((pAd->StaActive.SupportedPhyInfo.MCSSet[0] == 0xff) && (pAd->StaActive.SupportedPhyInfo.MCSSet[1] == 0xff) && (pAd->Antenna.field.TxPath == 2)) */
- if ((pEntry->HTCapability.MCSSet[0] == 0xff) && (pEntry->HTCapability.MCSSet[1] == 0xff) && (pAd->CommonCfg.TxStream == 2)) { /* 11N 2S AP */
- if (pAd->LatchRfRegs.Channel <= 14) {
- *ppTable = RateSwitchTable11N2S;
- *pTableSize = RateSwitchTable11N2S[0];
- *pInitTxRateIdx = RateSwitchTable11N2S[1];
- } else {
- *ppTable = RateSwitchTable11N2SForABand;
- *pTableSize = RateSwitchTable11N2SForABand[0];
- *pInitTxRateIdx =
- RateSwitchTable11N2SForABand[1];
- }
-
- break;
- }
- /*else if ((pAd->StaActive.SupRateLen == 4) && (pAd->StaActive.ExtRateLen == 0) && (pAd->StaActive.SupportedPhyInfo.MCSSet[0] == 0) && (pAd->StaActive.SupportedPhyInfo.MCSSet[1] == 0)) */
- if ((pEntry->RateLen == 4 || pAd->CommonCfg.PhyMode == PHY_11B)
- /*Iverson mark for Adhoc b mode,sta will use rate 54 Mbps when connect with sta b/g/n mode */
- /* && (pEntry->HTCapability.MCSSet[0] == 0) && (pEntry->HTCapability.MCSSet[1] == 0) */
- ) { /* B only AP */
- *ppTable = RateSwitchTable11B;
- *pTableSize = RateSwitchTable11B[0];
- *pInitTxRateIdx = RateSwitchTable11B[1];
-
- break;
- }
- /*else if ((pAd->StaActive.SupRateLen + pAd->StaActive.ExtRateLen > 8) && (pAd->StaActive.SupportedPhyInfo.MCSSet[0] == 0) && (pAd->StaActive.SupportedPhyInfo.MCSSet[1] == 0)) */
- if ((pEntry->RateLen > 8)
- && (pEntry->HTCapability.MCSSet[0] == 0)
- && (pEntry->HTCapability.MCSSet[1] == 0)
- ) { /* B/G mixed AP */
- *ppTable = RateSwitchTable11BG;
- *pTableSize = RateSwitchTable11BG[0];
- *pInitTxRateIdx = RateSwitchTable11BG[1];
-
- break;
- }
- /*else if ((pAd->StaActive.SupRateLen + pAd->StaActive.ExtRateLen == 8) && (pAd->StaActive.SupportedPhyInfo.MCSSet[0] == 0) && (pAd->StaActive.SupportedPhyInfo.MCSSet[1] == 0)) */
- if ((pEntry->RateLen == 8)
- && (pEntry->HTCapability.MCSSet[0] == 0)
- && (pEntry->HTCapability.MCSSet[1] == 0)
- ) { /* G only AP */
- *ppTable = RateSwitchTable11G;
- *pTableSize = RateSwitchTable11G[0];
- *pInitTxRateIdx = RateSwitchTable11G[1];
-
- break;
- }
-
- {
- /*else if ((pAd->StaActive.SupportedPhyInfo.MCSSet[0] == 0) && (pAd->StaActive.SupportedPhyInfo.MCSSet[1] == 0)) */
- if ((pEntry->HTCapability.MCSSet[0] == 0) && (pEntry->HTCapability.MCSSet[1] == 0)) { /* Legacy mode */
- if (pAd->CommonCfg.MaxTxRate <= RATE_11) {
- *ppTable = RateSwitchTable11B;
- *pTableSize = RateSwitchTable11B[0];
- *pInitTxRateIdx = RateSwitchTable11B[1];
- } else if ((pAd->CommonCfg.MaxTxRate > RATE_11)
- && (pAd->CommonCfg.MinTxRate >
- RATE_11)) {
- *ppTable = RateSwitchTable11G;
- *pTableSize = RateSwitchTable11G[0];
- *pInitTxRateIdx = RateSwitchTable11G[1];
-
- } else {
- *ppTable = RateSwitchTable11BG;
- *pTableSize = RateSwitchTable11BG[0];
- *pInitTxRateIdx =
- RateSwitchTable11BG[1];
- }
- break;
- }
- if (pAd->LatchRfRegs.Channel <= 14) {
- if (pAd->CommonCfg.TxStream == 1) {
- *ppTable = RateSwitchTable11N1S;
- *pTableSize = RateSwitchTable11N1S[0];
- *pInitTxRateIdx =
- RateSwitchTable11N1S[1];
- DBGPRINT_RAW(RT_DEBUG_ERROR,
- ("DRS: unknown mode,default use 11N 1S AP \n"));
- } else {
- *ppTable = RateSwitchTable11N2S;
- *pTableSize = RateSwitchTable11N2S[0];
- *pInitTxRateIdx =
- RateSwitchTable11N2S[1];
- DBGPRINT_RAW(RT_DEBUG_ERROR,
- ("DRS: unknown mode,default use 11N 2S AP \n"));
- }
- } else {
- if (pAd->CommonCfg.TxStream == 1) {
- *ppTable = RateSwitchTable11N1S;
- *pTableSize = RateSwitchTable11N1S[0];
- *pInitTxRateIdx =
- RateSwitchTable11N1S[1];
- DBGPRINT_RAW(RT_DEBUG_ERROR,
- ("DRS: unknown mode,default use 11N 1S AP \n"));
- } else {
- *ppTable = RateSwitchTable11N2SForABand;
- *pTableSize =
- RateSwitchTable11N2SForABand[0];
- *pInitTxRateIdx =
- RateSwitchTable11N2SForABand[1];
- DBGPRINT_RAW(RT_DEBUG_ERROR,
- ("DRS: unknown mode,default use 11N 2S AP \n"));
- }
- }
- DBGPRINT_RAW(RT_DEBUG_ERROR,
- ("DRS: unknown mode (SupRateLen=%d, ExtRateLen=%d, MCSSet[0]=0x%x, MCSSet[1]=0x%x)\n",
- pAd->StaActive.SupRateLen,
- pAd->StaActive.ExtRateLen,
- pAd->StaActive.SupportedPhyInfo.MCSSet[0],
- pAd->StaActive.SupportedPhyInfo.
- MCSSet[1]));
- }
- } while (FALSE);
-}
-
-void STAMlmePeriodicExec(struct rt_rtmp_adapter *pAd)
-{
- unsigned long TxTotalCnt;
- int i;
-
- /*
- We return here in ATE mode, because the statistics
- that ATE need are not collected via this routine.
- */
-#if defined(RT305x)||defined(RT3070)
- /* request by Gary, if Rssi0 > -42, BBP 82 need to be changed from 0x62 to 0x42, , bbp 67 need to be changed from 0x20 to 0x18 */
- if (!pAd->CommonCfg.HighPowerPatchDisabled) {
-#ifdef RT3070
- if ((IS_RT3070(pAd) && ((pAd->MACVersion & 0xffff) < 0x0201)))
-#endif /* RT3070 // */
- {
- if ((pAd->StaCfg.RssiSample.AvgRssi0 != 0)
- && (pAd->StaCfg.RssiSample.AvgRssi0 >
- (pAd->BbpRssiToDbmDelta - 35))) {
- RT30xxWriteRFRegister(pAd, RF_R27, 0x20);
- } else {
- RT30xxWriteRFRegister(pAd, RF_R27, 0x23);
- }
- }
- }
-#endif
-#ifdef PCIE_PS_SUPPORT
-/* don't perform idle-power-save mechanism within 3 min after driver initialization. */
-/* This can make rebooter test more robust */
- if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_PCIE_DEVICE)) {
- if ((pAd->OpMode == OPMODE_STA) && (IDLE_ON(pAd))
- && (pAd->Mlme.SyncMachine.CurrState == SYNC_IDLE)
- && (pAd->Mlme.CntlMachine.CurrState == CNTL_IDLE)
- && (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_IDLE_RADIO_OFF))) {
- if (IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd)) {
- if (pAd->StaCfg.PSControl.field.EnableNewPS ==
- TRUE) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("%s\n", __func__));
- RT28xxPciAsicRadioOff(pAd,
- GUI_IDLE_POWER_SAVE,
- 0);
- } else {
- AsicSendCommandToMcu(pAd, 0x30,
- PowerSafeCID, 0xff,
- 0x2);
- /* Wait command success */
- AsicCheckCommanOk(pAd, PowerSafeCID);
- RTMP_SET_FLAG(pAd,
- fRTMP_ADAPTER_IDLE_RADIO_OFF);
- DBGPRINT(RT_DEBUG_TRACE,
- ("PSM - rt30xx Issue Sleep command)\n"));
- }
- } else if (pAd->Mlme.OneSecPeriodicRound > 180) {
- if (pAd->StaCfg.PSControl.field.EnableNewPS ==
- TRUE) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("%s\n", __func__));
- RT28xxPciAsicRadioOff(pAd,
- GUI_IDLE_POWER_SAVE,
- 0);
- } else {
- AsicSendCommandToMcu(pAd, 0x30,
- PowerSafeCID, 0xff,
- 0x02);
- /* Wait command success */
- AsicCheckCommanOk(pAd, PowerSafeCID);
- RTMP_SET_FLAG(pAd,
- fRTMP_ADAPTER_IDLE_RADIO_OFF);
- DBGPRINT(RT_DEBUG_TRACE,
- ("PSM - rt28xx Issue Sleep command)\n"));
- }
- }
- } else {
- DBGPRINT(RT_DEBUG_TRACE,
- ("STAMlmePeriodicExec MMCHK - CommonCfg.Ssid[%d]=%c%c%c%c... MlmeAux.Ssid[%d]=%c%c%c%c...\n",
- pAd->CommonCfg.SsidLen,
- pAd->CommonCfg.Ssid[0],
- pAd->CommonCfg.Ssid[1],
- pAd->CommonCfg.Ssid[2],
- pAd->CommonCfg.Ssid[3], pAd->MlmeAux.SsidLen,
- pAd->MlmeAux.Ssid[0], pAd->MlmeAux.Ssid[1],
- pAd->MlmeAux.Ssid[2], pAd->MlmeAux.Ssid[3]));
- }
- }
-#endif /* PCIE_PS_SUPPORT // */
-
- if (pAd->StaCfg.WpaSupplicantUP == WPA_SUPPLICANT_DISABLE) {
- /* WPA MIC error should block association attempt for 60 seconds */
- if (pAd->StaCfg.bBlockAssoc &&
- RTMP_TIME_AFTER(pAd->Mlme.Now32,
- pAd->StaCfg.LastMicErrorTime +
- (60 * OS_HZ)))
- pAd->StaCfg.bBlockAssoc = FALSE;
- }
-
- if ((pAd->PreMediaState != pAd->IndicateMediaState)
- && (pAd->CommonCfg.bWirelessEvent)) {
- if (pAd->IndicateMediaState == NdisMediaStateConnected) {
- RTMPSendWirelessEvent(pAd, IW_STA_LINKUP_EVENT_FLAG,
- pAd->MacTab.Content[BSSID_WCID].
- Addr, BSS0, 0);
- }
- pAd->PreMediaState = pAd->IndicateMediaState;
- }
-
- if (pAd->CommonCfg.PSPXlink && ADHOC_ON(pAd)) {
- } else {
- AsicStaBbpTuning(pAd);
- }
-
- TxTotalCnt = pAd->RalinkCounters.OneSecTxNoRetryOkCount +
- pAd->RalinkCounters.OneSecTxRetryOkCount +
- pAd->RalinkCounters.OneSecTxFailCount;
-
- if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_MEDIA_STATE_CONNECTED)) {
- /* update channel quality for Roaming and UI LinkQuality display */
- MlmeCalculateChannelQuality(pAd, NULL, pAd->Mlme.Now32);
- }
- /* must be AFTER MlmeDynamicTxRateSwitching() because it needs to know if */
- /* Radio is currently in noisy environment */
- if (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_BSS_SCAN_IN_PROGRESS))
- AsicAdjustTxPower(pAd);
-
- if (INFRA_ON(pAd)) {
-
- /* Is PSM bit consistent with user power management policy? */
- /* This is the only place that will set PSM bit ON. */
- if (!OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_DOZE))
- MlmeCheckPsmChange(pAd, pAd->Mlme.Now32);
-
- pAd->RalinkCounters.LastOneSecTotalTxCount = TxTotalCnt;
-
- if ((RTMP_TIME_AFTER
- (pAd->Mlme.Now32,
- pAd->StaCfg.LastBeaconRxTime + (1 * OS_HZ)))
- &&
- (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_BSS_SCAN_IN_PROGRESS))
- &&
- (((TxTotalCnt + pAd->RalinkCounters.OneSecRxOkCnt) <
- 600))) {
- RTMPSetAGCInitValue(pAd, BW_20);
- DBGPRINT(RT_DEBUG_TRACE,
- ("MMCHK - No BEACON. restore R66 to the low bound(%d) \n",
- (0x2E + GET_LNA_GAIN(pAd))));
- }
- /*if ((pAd->RalinkCounters.OneSecTxNoRetryOkCount == 0) && */
- /* (pAd->RalinkCounters.OneSecTxRetryOkCount == 0)) */
- {
- if (pAd->CommonCfg.bAPSDCapable
- && pAd->CommonCfg.APEdcaParm.bAPSDCapable) {
- /* When APSD is enabled, the period changes as 20 sec */
- if ((pAd->Mlme.OneSecPeriodicRound % 20) == 8)
- RTMPSendNullFrame(pAd,
- pAd->CommonCfg.TxRate,
- TRUE);
- } else {
- /* Send out a NULL frame every 10 sec to inform AP that STA is still alive (Avoid being age out) */
- if ((pAd->Mlme.OneSecPeriodicRound % 10) == 8) {
- if (pAd->CommonCfg.bWmmCapable)
- RTMPSendNullFrame(pAd,
- pAd->
- CommonCfg.
- TxRate, TRUE);
- else
- RTMPSendNullFrame(pAd,
- pAd->
- CommonCfg.
- TxRate,
- FALSE);
- }
- }
- }
-
- if (CQI_IS_DEAD(pAd->Mlme.ChannelQuality)) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("MMCHK - No BEACON. Dead CQI. Auto Recovery attempt #%ld\n",
- pAd->RalinkCounters.BadCQIAutoRecoveryCount));
-
- /* Lost AP, send disconnect & link down event */
- LinkDown(pAd, FALSE);
-
- RtmpOSWrielessEventSend(pAd, SIOCGIWAP, -1, NULL, NULL,
- 0);
-
- /* RTMPPatchMacBbpBug(pAd); */
- MlmeAutoReconnectLastSSID(pAd);
- } else if (CQI_IS_BAD(pAd->Mlme.ChannelQuality)) {
- pAd->RalinkCounters.BadCQIAutoRecoveryCount++;
- DBGPRINT(RT_DEBUG_TRACE,
- ("MMCHK - Bad CQI. Auto Recovery attempt #%ld\n",
- pAd->RalinkCounters.BadCQIAutoRecoveryCount));
- MlmeAutoReconnectLastSSID(pAd);
- }
-
- if (pAd->StaCfg.bAutoRoaming) {
- BOOLEAN rv = FALSE;
- char dBmToRoam = pAd->StaCfg.dBmToRoam;
- char MaxRssi = RTMPMaxRssi(pAd,
- pAd->StaCfg.RssiSample.
- LastRssi0,
- pAd->StaCfg.RssiSample.
- LastRssi1,
- pAd->StaCfg.RssiSample.
- LastRssi2);
-
- /* Scanning, ignore Roaming */
- if (!RTMP_TEST_FLAG
- (pAd, fRTMP_ADAPTER_BSS_SCAN_IN_PROGRESS)
- && (pAd->Mlme.SyncMachine.CurrState == SYNC_IDLE)
- && (MaxRssi <= dBmToRoam)) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("Rssi=%d, dBmToRoam=%d\n", MaxRssi,
- (char)dBmToRoam));
-
- /* Add auto seamless roaming */
- if (rv == FALSE)
- rv = MlmeCheckForFastRoaming(pAd);
-
- if (rv == FALSE) {
- if ((pAd->StaCfg.LastScanTime +
- 10 * OS_HZ) < pAd->Mlme.Now32) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("MMCHK - Roaming, No eligible entry, try new scan!\n"));
- pAd->StaCfg.ScanCnt = 2;
- pAd->StaCfg.LastScanTime =
- pAd->Mlme.Now32;
- MlmeAutoScan(pAd);
- }
- }
- }
- }
- } else if (ADHOC_ON(pAd)) {
- /* If all peers leave, and this STA becomes the last one in this IBSS, then change MediaState */
- /* to DISCONNECTED. But still holding this IBSS (i.e. sending BEACON) so that other STAs can */
- /* join later. */
- if (RTMP_TIME_AFTER
- (pAd->Mlme.Now32,
- pAd->StaCfg.LastBeaconRxTime + ADHOC_BEACON_LOST_TIME)
- && OPSTATUS_TEST_FLAG(pAd,
- fOP_STATUS_MEDIA_STATE_CONNECTED)) {
- struct rt_mlme_start_req StartReq;
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("MMCHK - excessive BEACON lost, last STA in this IBSS, MediaState=Disconnected\n"));
- LinkDown(pAd, FALSE);
-
- StartParmFill(pAd, &StartReq,
- (char *) pAd->MlmeAux.Ssid,
- pAd->MlmeAux.SsidLen);
- MlmeEnqueue(pAd, SYNC_STATE_MACHINE, MT2_MLME_START_REQ,
- sizeof(struct rt_mlme_start_req), &StartReq);
- pAd->Mlme.CntlMachine.CurrState = CNTL_WAIT_START;
- }
-
- for (i = 1; i < MAX_LEN_OF_MAC_TABLE; i++) {
- struct rt_mac_table_entry *pEntry = &pAd->MacTab.Content[i];
-
- if (pEntry->ValidAsCLI == FALSE)
- continue;
-
- if (RTMP_TIME_AFTER
- (pAd->Mlme.Now32,
- pEntry->LastBeaconRxTime + ADHOC_BEACON_LOST_TIME))
- MacTableDeleteEntry(pAd, pEntry->Aid,
- pEntry->Addr);
- }
- } else /* no INFRA nor ADHOC connection */
- {
-
- if (pAd->StaCfg.bScanReqIsFromWebUI &&
- RTMP_TIME_BEFORE(pAd->Mlme.Now32,
- pAd->StaCfg.LastScanTime + (30 * OS_HZ)))
- goto SKIP_AUTO_SCAN_CONN;
- else
- pAd->StaCfg.bScanReqIsFromWebUI = FALSE;
-
- if ((pAd->StaCfg.bAutoReconnect == TRUE)
- && RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_START_UP)
- &&
- (MlmeValidateSSID
- (pAd->MlmeAux.AutoReconnectSsid,
- pAd->MlmeAux.AutoReconnectSsidLen) == TRUE)) {
- if ((pAd->ScanTab.BssNr == 0)
- && (pAd->Mlme.CntlMachine.CurrState == CNTL_IDLE)) {
- struct rt_mlme_scan_req ScanReq;
-
- if (RTMP_TIME_AFTER
- (pAd->Mlme.Now32,
- pAd->StaCfg.LastScanTime + (10 * OS_HZ))) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("STAMlmePeriodicExec():CNTL - ScanTab.BssNr==0, start a new ACTIVE scan SSID[%s]\n",
- pAd->MlmeAux.
- AutoReconnectSsid));
- ScanParmFill(pAd, &ScanReq,
- (char *)pAd->MlmeAux.
- AutoReconnectSsid,
- pAd->MlmeAux.
- AutoReconnectSsidLen,
- BSS_ANY, SCAN_ACTIVE);
- MlmeEnqueue(pAd, SYNC_STATE_MACHINE,
- MT2_MLME_SCAN_REQ,
- sizeof
- (struct rt_mlme_scan_req),
- &ScanReq);
- pAd->Mlme.CntlMachine.CurrState =
- CNTL_WAIT_OID_LIST_SCAN;
- /* Reset Missed scan number */
- pAd->StaCfg.LastScanTime =
- pAd->Mlme.Now32;
- } else if (pAd->StaCfg.BssType == BSS_ADHOC) /* Quit the forever scan when in a very clean room */
- MlmeAutoReconnectLastSSID(pAd);
- } else if (pAd->Mlme.CntlMachine.CurrState == CNTL_IDLE) {
- if ((pAd->Mlme.OneSecPeriodicRound % 7) == 0) {
- MlmeAutoScan(pAd);
- pAd->StaCfg.LastScanTime =
- pAd->Mlme.Now32;
- } else {
- MlmeAutoReconnectLastSSID(pAd);
- }
- }
- }
- }
-
-SKIP_AUTO_SCAN_CONN:
-
- if ((pAd->MacTab.Content[BSSID_WCID].TXBAbitmap != 0)
- && (pAd->MacTab.fAnyBASession == FALSE)) {
- pAd->MacTab.fAnyBASession = TRUE;
- AsicUpdateProtect(pAd, HT_FORCERTSCTS, ALLN_SETPROTECT, FALSE,
- FALSE);
- } else if ((pAd->MacTab.Content[BSSID_WCID].TXBAbitmap == 0)
- && (pAd->MacTab.fAnyBASession == TRUE)) {
- pAd->MacTab.fAnyBASession = FALSE;
- AsicUpdateProtect(pAd,
- pAd->MlmeAux.AddHtInfo.AddHtInfo2.
- OperaionMode, ALLN_SETPROTECT, FALSE, FALSE);
- }
-
- return;
-}
-
-/* Link down report */
-void LinkDownExec(void *SystemSpecific1,
- void *FunctionContext,
- void *SystemSpecific2, void *SystemSpecific3)
-{
- struct rt_rtmp_adapter *pAd = (struct rt_rtmp_adapter *)FunctionContext;
-
- if (pAd != NULL) {
- struct rt_mlme_disassoc_req DisassocReq;
-
- if ((pAd->StaCfg.PortSecured == WPA_802_1X_PORT_NOT_SECURED) &&
- (INFRA_ON(pAd))) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("LinkDownExec(): disassociate with current AP...\n"));
- DisassocParmFill(pAd, &DisassocReq,
- pAd->CommonCfg.Bssid,
- REASON_DISASSOC_STA_LEAVING);
- MlmeEnqueue(pAd, ASSOC_STATE_MACHINE,
- MT2_MLME_DISASSOC_REQ,
- sizeof(struct rt_mlme_disassoc_req),
- &DisassocReq);
- pAd->Mlme.CntlMachine.CurrState = CNTL_WAIT_DISASSOC;
-
- pAd->IndicateMediaState = NdisMediaStateDisconnected;
- RTMP_IndicateMediaState(pAd);
- pAd->ExtraInfo = GENERAL_LINK_DOWN;
- }
- }
-}
-
-/* IRQL = DISPATCH_LEVEL */
-void MlmeAutoScan(struct rt_rtmp_adapter *pAd)
-{
- /* check CntlMachine.CurrState to avoid collision with NDIS SetOID request */
- if (pAd->Mlme.CntlMachine.CurrState == CNTL_IDLE) {
- DBGPRINT(RT_DEBUG_TRACE, ("MMCHK - Driver auto scan\n"));
- MlmeEnqueue(pAd,
- MLME_CNTL_STATE_MACHINE,
- OID_802_11_BSSID_LIST_SCAN,
- pAd->MlmeAux.AutoReconnectSsidLen,
- pAd->MlmeAux.AutoReconnectSsid);
- RTMP_MLME_HANDLER(pAd);
- }
-}
-
-/* IRQL = DISPATCH_LEVEL */
-void MlmeAutoReconnectLastSSID(struct rt_rtmp_adapter *pAd)
-{
- if (pAd->StaCfg.bAutoConnectByBssid) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("Driver auto reconnect to last OID_802_11_BSSID "
- "setting - %pM\n", pAd->MlmeAux.Bssid));
-
- pAd->MlmeAux.Channel = pAd->CommonCfg.Channel;
- MlmeEnqueue(pAd,
- MLME_CNTL_STATE_MACHINE,
- OID_802_11_BSSID, MAC_ADDR_LEN, pAd->MlmeAux.Bssid);
-
- pAd->Mlme.CntlMachine.CurrState = CNTL_IDLE;
-
- RTMP_MLME_HANDLER(pAd);
- }
- /* check CntlMachine.CurrState to avoid collision with NDIS SetOID request */
- else if ((pAd->Mlme.CntlMachine.CurrState == CNTL_IDLE) &&
- (MlmeValidateSSID
- (pAd->MlmeAux.AutoReconnectSsid,
- pAd->MlmeAux.AutoReconnectSsidLen) == TRUE)) {
- struct rt_ndis_802_11_ssid OidSsid;
- OidSsid.SsidLength = pAd->MlmeAux.AutoReconnectSsidLen;
- NdisMoveMemory(OidSsid.Ssid, pAd->MlmeAux.AutoReconnectSsid,
- pAd->MlmeAux.AutoReconnectSsidLen);
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("Driver auto reconnect to last OID_802_11_SSID setting - %s, len - %d\n",
- pAd->MlmeAux.AutoReconnectSsid,
- pAd->MlmeAux.AutoReconnectSsidLen));
- MlmeEnqueue(pAd, MLME_CNTL_STATE_MACHINE, OID_802_11_SSID,
- sizeof(struct rt_ndis_802_11_ssid), &OidSsid);
- RTMP_MLME_HANDLER(pAd);
- }
-}
-
-/*
- ==========================================================================
- Description:
- This routine checks if there're other APs out there capable for
- roaming. Caller should call this routine only when Link up in INFRA mode
- and channel quality is below CQI_GOOD_THRESHOLD.
-
- IRQL = DISPATCH_LEVEL
-
- Output:
- ==========================================================================
- */
-void MlmeCheckForRoaming(struct rt_rtmp_adapter *pAd, unsigned long Now32)
-{
- u16 i;
- struct rt_bss_table *pRoamTab = &pAd->MlmeAux.RoamTab;
- struct rt_bss_entry *pBss;
-
- DBGPRINT(RT_DEBUG_TRACE, ("==> MlmeCheckForRoaming\n"));
- /* put all roaming candidates into RoamTab, and sort in RSSI order */
- BssTableInit(pRoamTab);
- for (i = 0; i < pAd->ScanTab.BssNr; i++) {
- pBss = &pAd->ScanTab.BssEntry[i];
-
- if ((pBss->LastBeaconRxTime + pAd->StaCfg.BeaconLostTime) <
- Now32)
- continue; /* AP disappear */
- if (pBss->Rssi <= RSSI_THRESHOLD_FOR_ROAMING)
- continue; /* RSSI too weak. forget it. */
- if (MAC_ADDR_EQUAL(pBss->Bssid, pAd->CommonCfg.Bssid))
- continue; /* skip current AP */
- if (pBss->Rssi <
- (pAd->StaCfg.RssiSample.LastRssi0 + RSSI_DELTA))
- continue; /* only AP with stronger RSSI is eligible for roaming */
-
- /* AP passing all above rules is put into roaming candidate table */
- NdisMoveMemory(&pRoamTab->BssEntry[pRoamTab->BssNr], pBss,
- sizeof(struct rt_bss_entry));
- pRoamTab->BssNr += 1;
- }
-
- if (pRoamTab->BssNr > 0) {
- /* check CntlMachine.CurrState to avoid collision with NDIS SetOID request */
- if (pAd->Mlme.CntlMachine.CurrState == CNTL_IDLE) {
- pAd->RalinkCounters.PoorCQIRoamingCount++;
- DBGPRINT(RT_DEBUG_TRACE,
- ("MMCHK - Roaming attempt #%ld\n",
- pAd->RalinkCounters.PoorCQIRoamingCount));
- MlmeEnqueue(pAd, MLME_CNTL_STATE_MACHINE,
- MT2_MLME_ROAMING_REQ, 0, NULL);
- RTMP_MLME_HANDLER(pAd);
- }
- }
- DBGPRINT(RT_DEBUG_TRACE,
- ("<== MlmeCheckForRoaming(# of candidate= %d)\n",
- pRoamTab->BssNr));
-}
-
-/*
- ==========================================================================
- Description:
- This routine checks if there're other APs out there capable for
- roaming. Caller should call this routine only when link up in INFRA mode
- and channel quality is below CQI_GOOD_THRESHOLD.
-
- IRQL = DISPATCH_LEVEL
-
- Output:
- ==========================================================================
- */
-BOOLEAN MlmeCheckForFastRoaming(struct rt_rtmp_adapter *pAd)
-{
- u16 i;
- struct rt_bss_table *pRoamTab = &pAd->MlmeAux.RoamTab;
- struct rt_bss_entry *pBss;
-
- DBGPRINT(RT_DEBUG_TRACE, ("==> MlmeCheckForFastRoaming\n"));
- /* put all roaming candidates into RoamTab, and sort in RSSI order */
- BssTableInit(pRoamTab);
- for (i = 0; i < pAd->ScanTab.BssNr; i++) {
- pBss = &pAd->ScanTab.BssEntry[i];
-
- if ((pBss->Rssi <= -50)
- && (pBss->Channel == pAd->CommonCfg.Channel))
- continue; /* RSSI too weak. forget it. */
- if (MAC_ADDR_EQUAL(pBss->Bssid, pAd->CommonCfg.Bssid))
- continue; /* skip current AP */
- if (!SSID_EQUAL
- (pBss->Ssid, pBss->SsidLen, pAd->CommonCfg.Ssid,
- pAd->CommonCfg.SsidLen))
- continue; /* skip different SSID */
- if (pBss->Rssi <
- (RTMPMaxRssi
- (pAd, pAd->StaCfg.RssiSample.LastRssi0,
- pAd->StaCfg.RssiSample.LastRssi1,
- pAd->StaCfg.RssiSample.LastRssi2) + RSSI_DELTA))
- continue; /* skip AP without better RSSI */
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("LastRssi0 = %d, pBss->Rssi = %d\n",
- RTMPMaxRssi(pAd, pAd->StaCfg.RssiSample.LastRssi0,
- pAd->StaCfg.RssiSample.LastRssi1,
- pAd->StaCfg.RssiSample.LastRssi2),
- pBss->Rssi));
- /* AP passing all above rules is put into roaming candidate table */
- NdisMoveMemory(&pRoamTab->BssEntry[pRoamTab->BssNr], pBss,
- sizeof(struct rt_bss_entry));
- pRoamTab->BssNr += 1;
- }
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("<== MlmeCheckForFastRoaming (BssNr=%d)\n", pRoamTab->BssNr));
- if (pRoamTab->BssNr > 0) {
- /* check CntlMachine.CurrState to avoid collision with NDIS SetOID request */
- if (pAd->Mlme.CntlMachine.CurrState == CNTL_IDLE) {
- pAd->RalinkCounters.PoorCQIRoamingCount++;
- DBGPRINT(RT_DEBUG_TRACE,
- ("MMCHK - Roaming attempt #%ld\n",
- pAd->RalinkCounters.PoorCQIRoamingCount));
- MlmeEnqueue(pAd, MLME_CNTL_STATE_MACHINE,
- MT2_MLME_ROAMING_REQ, 0, NULL);
- RTMP_MLME_HANDLER(pAd);
- return TRUE;
- }
- }
-
- return FALSE;
-}
-
-void MlmeSetTxRate(struct rt_rtmp_adapter *pAd,
- struct rt_mac_table_entry *pEntry, struct rt_rtmp_tx_rate_switch * pTxRate)
-{
- u8 MaxMode = MODE_OFDM;
-
- MaxMode = MODE_HTGREENFIELD;
-
- if (pTxRate->STBC && (pAd->StaCfg.MaxHTPhyMode.field.STBC)
- && (pAd->Antenna.field.TxPath == 2))
- pAd->StaCfg.HTPhyMode.field.STBC = STBC_USE;
- else
- pAd->StaCfg.HTPhyMode.field.STBC = STBC_NONE;
-
- if (pTxRate->CurrMCS < MCS_AUTO)
- pAd->StaCfg.HTPhyMode.field.MCS = pTxRate->CurrMCS;
-
- if (pAd->StaCfg.HTPhyMode.field.MCS > 7)
- pAd->StaCfg.HTPhyMode.field.STBC = STBC_NONE;
-
- if (ADHOC_ON(pAd)) {
- /* If peer adhoc is b-only mode, we can't send 11g rate. */
- pAd->StaCfg.HTPhyMode.field.ShortGI = GI_800;
- pEntry->HTPhyMode.field.STBC = STBC_NONE;
-
- /* */
- /* For Adhoc MODE_CCK, driver will use AdhocBOnlyJoined flag to roll back to B only if necessary */
- /* */
- pEntry->HTPhyMode.field.MODE = pTxRate->Mode;
- pEntry->HTPhyMode.field.ShortGI =
- pAd->StaCfg.HTPhyMode.field.ShortGI;
- pEntry->HTPhyMode.field.MCS = pAd->StaCfg.HTPhyMode.field.MCS;
-
- /* Patch speed error in status page */
- pAd->StaCfg.HTPhyMode.field.MODE = pEntry->HTPhyMode.field.MODE;
- } else {
- if (pTxRate->Mode <= MaxMode)
- pAd->StaCfg.HTPhyMode.field.MODE = pTxRate->Mode;
-
- if (pTxRate->ShortGI
- && (pAd->StaCfg.MaxHTPhyMode.field.ShortGI))
- pAd->StaCfg.HTPhyMode.field.ShortGI = GI_400;
- else
- pAd->StaCfg.HTPhyMode.field.ShortGI = GI_800;
-
- /* Reexam each bandwidth's SGI support. */
- if (pAd->StaCfg.HTPhyMode.field.ShortGI == GI_400) {
- if ((pEntry->HTPhyMode.field.BW == BW_20)
- &&
- (!CLIENT_STATUS_TEST_FLAG
- (pEntry, fCLIENT_STATUS_SGI20_CAPABLE)))
- pAd->StaCfg.HTPhyMode.field.ShortGI = GI_800;
- if ((pEntry->HTPhyMode.field.BW == BW_40)
- &&
- (!CLIENT_STATUS_TEST_FLAG
- (pEntry, fCLIENT_STATUS_SGI40_CAPABLE)))
- pAd->StaCfg.HTPhyMode.field.ShortGI = GI_800;
- }
- /* Turn RTS/CTS rate to 6Mbps. */
- if ((pEntry->HTPhyMode.field.MCS == 0)
- && (pAd->StaCfg.HTPhyMode.field.MCS != 0)) {
- pEntry->HTPhyMode.field.MCS =
- pAd->StaCfg.HTPhyMode.field.MCS;
- if (pAd->MacTab.fAnyBASession) {
- AsicUpdateProtect(pAd, HT_FORCERTSCTS,
- ALLN_SETPROTECT, TRUE,
- (BOOLEAN) pAd->MlmeAux.
- AddHtInfo.AddHtInfo2.
- NonGfPresent);
- } else {
- AsicUpdateProtect(pAd,
- pAd->MlmeAux.AddHtInfo.
- AddHtInfo2.OperaionMode,
- ALLN_SETPROTECT, TRUE,
- (BOOLEAN) pAd->MlmeAux.
- AddHtInfo.AddHtInfo2.
- NonGfPresent);
- }
- } else if ((pEntry->HTPhyMode.field.MCS == 8)
- && (pAd->StaCfg.HTPhyMode.field.MCS != 8)) {
- pEntry->HTPhyMode.field.MCS =
- pAd->StaCfg.HTPhyMode.field.MCS;
- if (pAd->MacTab.fAnyBASession) {
- AsicUpdateProtect(pAd, HT_FORCERTSCTS,
- ALLN_SETPROTECT, TRUE,
- (BOOLEAN) pAd->MlmeAux.
- AddHtInfo.AddHtInfo2.
- NonGfPresent);
- } else {
- AsicUpdateProtect(pAd,
- pAd->MlmeAux.AddHtInfo.
- AddHtInfo2.OperaionMode,
- ALLN_SETPROTECT, TRUE,
- (BOOLEAN) pAd->MlmeAux.
- AddHtInfo.AddHtInfo2.
- NonGfPresent);
- }
- } else if ((pEntry->HTPhyMode.field.MCS != 0)
- && (pAd->StaCfg.HTPhyMode.field.MCS == 0)) {
- AsicUpdateProtect(pAd, HT_RTSCTS_6M, ALLN_SETPROTECT,
- TRUE,
- (BOOLEAN) pAd->MlmeAux.AddHtInfo.
- AddHtInfo2.NonGfPresent);
-
- } else if ((pEntry->HTPhyMode.field.MCS != 8)
- && (pAd->StaCfg.HTPhyMode.field.MCS == 8)) {
- AsicUpdateProtect(pAd, HT_RTSCTS_6M, ALLN_SETPROTECT,
- TRUE,
- (BOOLEAN) pAd->MlmeAux.AddHtInfo.
- AddHtInfo2.NonGfPresent);
- }
-
- pEntry->HTPhyMode.field.STBC = pAd->StaCfg.HTPhyMode.field.STBC;
- pEntry->HTPhyMode.field.ShortGI =
- pAd->StaCfg.HTPhyMode.field.ShortGI;
- pEntry->HTPhyMode.field.MCS = pAd->StaCfg.HTPhyMode.field.MCS;
- pEntry->HTPhyMode.field.MODE = pAd->StaCfg.HTPhyMode.field.MODE;
- if ((pAd->StaCfg.MaxHTPhyMode.field.MODE == MODE_HTGREENFIELD)
- && pAd->WIFItestbed.bGreenField)
- pEntry->HTPhyMode.field.MODE = MODE_HTGREENFIELD;
- }
-
- pAd->LastTxRate = (u16)(pEntry->HTPhyMode.word);
-}
-
-/*
- ==========================================================================
- Description:
- This routine calculates the acumulated TxPER of eaxh TxRate. And
- according to the calculation result, change CommonCfg.TxRate which
- is the stable TX Rate we expect the Radio situation could sustained.
-
- CommonCfg.TxRate will change dynamically within {RATE_1/RATE_6, MaxTxRate}
- Output:
- CommonCfg.TxRate -
-
- IRQL = DISPATCH_LEVEL
-
- NOTE:
- call this routine every second
- ==========================================================================
- */
-void MlmeDynamicTxRateSwitching(struct rt_rtmp_adapter *pAd)
-{
- u8 UpRateIdx = 0, DownRateIdx = 0, CurrRateIdx;
- unsigned long i, AccuTxTotalCnt = 0, TxTotalCnt;
- unsigned long TxErrorRatio = 0;
- BOOLEAN bTxRateChanged = FALSE, bUpgradeQuality = FALSE;
- struct rt_rtmp_tx_rate_switch *pCurrTxRate, *pNextTxRate = NULL;
- u8 *pTable;
- u8 TableSize = 0;
- u8 InitTxRateIdx = 0, TrainUp, TrainDown;
- char Rssi, RssiOffset = 0;
- TX_STA_CNT1_STRUC StaTx1;
- TX_STA_CNT0_STRUC TxStaCnt0;
- unsigned long TxRetransmit = 0, TxSuccess = 0, TxFailCount = 0;
- struct rt_mac_table_entry *pEntry;
- struct rt_rssi_sample *pRssi = &pAd->StaCfg.RssiSample;
-
- /* */
- /* walk through MAC table, see if need to change AP's TX rate toward each entry */
- /* */
- for (i = 1; i < MAX_LEN_OF_MAC_TABLE; i++) {
- pEntry = &pAd->MacTab.Content[i];
-
- /* check if this entry need to switch rate automatically */
- if (RTMPCheckEntryEnableAutoRateSwitch(pAd, pEntry) == FALSE)
- continue;
-
- if ((pAd->MacTab.Size == 1) || (pEntry->ValidAsDls)) {
- Rssi = RTMPMaxRssi(pAd,
- pRssi->AvgRssi0,
- pRssi->AvgRssi1, pRssi->AvgRssi2);
-
- /* Update statistic counter */
- RTMP_IO_READ32(pAd, TX_STA_CNT0, &TxStaCnt0.word);
- RTMP_IO_READ32(pAd, TX_STA_CNT1, &StaTx1.word);
- pAd->bUpdateBcnCntDone = TRUE;
- TxRetransmit = StaTx1.field.TxRetransmit;
- TxSuccess = StaTx1.field.TxSuccess;
- TxFailCount = TxStaCnt0.field.TxFailCount;
- TxTotalCnt = TxRetransmit + TxSuccess + TxFailCount;
-
- pAd->RalinkCounters.OneSecTxRetryOkCount +=
- StaTx1.field.TxRetransmit;
- pAd->RalinkCounters.OneSecTxNoRetryOkCount +=
- StaTx1.field.TxSuccess;
- pAd->RalinkCounters.OneSecTxFailCount +=
- TxStaCnt0.field.TxFailCount;
- pAd->WlanCounters.TransmittedFragmentCount.u.LowPart +=
- StaTx1.field.TxSuccess;
- pAd->WlanCounters.RetryCount.u.LowPart +=
- StaTx1.field.TxRetransmit;
- pAd->WlanCounters.FailedCount.u.LowPart +=
- TxStaCnt0.field.TxFailCount;
-
- /* if no traffic in the past 1-sec period, don't change TX rate, */
- /* but clear all bad history. because the bad history may affect the next */
- /* Chariot throughput test */
- AccuTxTotalCnt =
- pAd->RalinkCounters.OneSecTxNoRetryOkCount +
- pAd->RalinkCounters.OneSecTxRetryOkCount +
- pAd->RalinkCounters.OneSecTxFailCount;
-
- if (TxTotalCnt)
- TxErrorRatio =
- ((TxRetransmit +
- TxFailCount) * 100) / TxTotalCnt;
- } else {
- if (INFRA_ON(pAd) && (i == 1))
- Rssi = RTMPMaxRssi(pAd,
- pRssi->AvgRssi0,
- pRssi->AvgRssi1,
- pRssi->AvgRssi2);
- else
- Rssi = RTMPMaxRssi(pAd,
- pEntry->RssiSample.AvgRssi0,
- pEntry->RssiSample.AvgRssi1,
- pEntry->RssiSample.AvgRssi2);
-
- TxTotalCnt = pEntry->OneSecTxNoRetryOkCount +
- pEntry->OneSecTxRetryOkCount +
- pEntry->OneSecTxFailCount;
-
- if (TxTotalCnt)
- TxErrorRatio =
- ((pEntry->OneSecTxRetryOkCount +
- pEntry->OneSecTxFailCount) * 100) /
- TxTotalCnt;
- }
-
- if (TxTotalCnt) {
- /*
- Three AdHoc connections can not work normally if one AdHoc connection is disappeared from a heavy traffic environment generated by ping tool
- We force to set LongRtyLimit and ShortRtyLimit to 0 to stop retransmitting packet, after a while, resoring original settings
- */
- if (TxErrorRatio == 100) {
- TX_RTY_CFG_STRUC TxRtyCfg, TxRtyCfgtmp;
- unsigned long Index;
- unsigned long MACValue;
-
- RTMP_IO_READ32(pAd, TX_RTY_CFG, &TxRtyCfg.word);
- TxRtyCfgtmp.word = TxRtyCfg.word;
- TxRtyCfg.field.LongRtyLimit = 0x0;
- TxRtyCfg.field.ShortRtyLimit = 0x0;
- RTMP_IO_WRITE32(pAd, TX_RTY_CFG, TxRtyCfg.word);
-
- RTMPusecDelay(1);
-
- Index = 0;
- MACValue = 0;
- do {
- RTMP_IO_READ32(pAd, TXRXQ_PCNT,
- &MACValue);
- if ((MACValue & 0xffffff) == 0)
- break;
- Index++;
- RTMPusecDelay(1000);
- } while ((Index < 330)
- &&
- (!RTMP_TEST_FLAG
- (pAd,
- fRTMP_ADAPTER_HALT_IN_PROGRESS)));
-
- RTMP_IO_READ32(pAd, TX_RTY_CFG, &TxRtyCfg.word);
- TxRtyCfg.field.LongRtyLimit =
- TxRtyCfgtmp.field.LongRtyLimit;
- TxRtyCfg.field.ShortRtyLimit =
- TxRtyCfgtmp.field.ShortRtyLimit;
- RTMP_IO_WRITE32(pAd, TX_RTY_CFG, TxRtyCfg.word);
- }
- }
-
- CurrRateIdx = pEntry->CurrTxRateIndex;
-
- MlmeSelectTxRateTable(pAd, pEntry, &pTable, &TableSize,
- &InitTxRateIdx);
-
- if (CurrRateIdx >= TableSize) {
- CurrRateIdx = TableSize - 1;
- }
- /* When switch from Fixed rate -> auto rate, the REAL TX rate might be different from pAd->CommonCfg.TxRateIndex. */
- /* So need to sync here. */
- pCurrTxRate =
- (struct rt_rtmp_tx_rate_switch *) & pTable[(CurrRateIdx + 1) * 5];
- if ((pEntry->HTPhyMode.field.MCS != pCurrTxRate->CurrMCS)
- /*&& (pAd->StaCfg.bAutoTxRateSwitch == TRUE) */
- ) {
-
- /* Need to sync Real Tx rate and our record. */
- /* Then return for next DRS. */
- pCurrTxRate =
- (struct rt_rtmp_tx_rate_switch *) & pTable[(InitTxRateIdx + 1)
- * 5];
- pEntry->CurrTxRateIndex = InitTxRateIdx;
- MlmeSetTxRate(pAd, pEntry, pCurrTxRate);
-
- /* reset all OneSecTx counters */
- RESET_ONE_SEC_TX_CNT(pEntry);
- continue;
- }
- /* decide the next upgrade rate and downgrade rate, if any */
- if ((CurrRateIdx > 0) && (CurrRateIdx < (TableSize - 1))) {
- UpRateIdx = CurrRateIdx + 1;
- DownRateIdx = CurrRateIdx - 1;
- } else if (CurrRateIdx == 0) {
- UpRateIdx = CurrRateIdx + 1;
- DownRateIdx = CurrRateIdx;
- } else if (CurrRateIdx == (TableSize - 1)) {
- UpRateIdx = CurrRateIdx;
- DownRateIdx = CurrRateIdx - 1;
- }
-
- pCurrTxRate =
- (struct rt_rtmp_tx_rate_switch *) & pTable[(CurrRateIdx + 1) * 5];
-
- if ((Rssi > -65) && (pCurrTxRate->Mode >= MODE_HTMIX)) {
- TrainUp =
- (pCurrTxRate->TrainUp +
- (pCurrTxRate->TrainUp >> 1));
- TrainDown =
- (pCurrTxRate->TrainDown +
- (pCurrTxRate->TrainDown >> 1));
- } else {
- TrainUp = pCurrTxRate->TrainUp;
- TrainDown = pCurrTxRate->TrainDown;
- }
-
- /*pAd->DrsCounters.LastTimeTxRateChangeAction = pAd->DrsCounters.LastSecTxRateChangeAction; */
-
- /* */
- /* Keep the last time TxRateChangeAction status. */
- /* */
- pEntry->LastTimeTxRateChangeAction =
- pEntry->LastSecTxRateChangeAction;
-
- /* */
- /* CASE 1. when TX samples are fewer than 15, then decide TX rate solely on RSSI */
- /* (criteria copied from RT2500 for Netopia case) */
- /* */
- if (TxTotalCnt <= 15) {
- char idx = 0;
- u8 TxRateIdx;
- u8 MCS0 = 0, MCS1 = 0, MCS2 = 0, MCS3 = 0, MCS4 =
- 0, MCS5 = 0, MCS6 = 0, MCS7 = 0;
- u8 MCS12 = 0, MCS13 = 0, MCS14 = 0, MCS15 = 0;
- u8 MCS20 = 0, MCS21 = 0, MCS22 = 0, MCS23 = 0; /* 3*3 */
-
- /* check the existence and index of each needed MCS */
- while (idx < pTable[0]) {
- pCurrTxRate =
- (struct rt_rtmp_tx_rate_switch *) & pTable[(idx + 1) *
- 5];
-
- if (pCurrTxRate->CurrMCS == MCS_0) {
- MCS0 = idx;
- } else if (pCurrTxRate->CurrMCS == MCS_1) {
- MCS1 = idx;
- } else if (pCurrTxRate->CurrMCS == MCS_2) {
- MCS2 = idx;
- } else if (pCurrTxRate->CurrMCS == MCS_3) {
- MCS3 = idx;
- } else if (pCurrTxRate->CurrMCS == MCS_4) {
- MCS4 = idx;
- } else if (pCurrTxRate->CurrMCS == MCS_5) {
- MCS5 = idx;
- } else if (pCurrTxRate->CurrMCS == MCS_6) {
- MCS6 = idx;
- }
- /*else if (pCurrTxRate->CurrMCS == MCS_7) */
- else if ((pCurrTxRate->CurrMCS == MCS_7) && (pCurrTxRate->ShortGI == GI_800)) /* prevent the highest MCS using short GI when 1T and low throughput */
- {
- MCS7 = idx;
- } else if (pCurrTxRate->CurrMCS == MCS_12) {
- MCS12 = idx;
- } else if (pCurrTxRate->CurrMCS == MCS_13) {
- MCS13 = idx;
- } else if (pCurrTxRate->CurrMCS == MCS_14) {
- MCS14 = idx;
- }
- else if ((pCurrTxRate->CurrMCS == MCS_15) && (pCurrTxRate->ShortGI == GI_800)) /*we hope to use ShortGI as initial rate, however Atheros's chip has bugs when short GI */
- {
- MCS15 = idx;
- } else if (pCurrTxRate->CurrMCS == MCS_20) /* 3*3 */
- {
- MCS20 = idx;
- } else if (pCurrTxRate->CurrMCS == MCS_21) {
- MCS21 = idx;
- } else if (pCurrTxRate->CurrMCS == MCS_22) {
- MCS22 = idx;
- } else if (pCurrTxRate->CurrMCS == MCS_23) {
- MCS23 = idx;
- }
- idx++;
- }
-
- if (pAd->LatchRfRegs.Channel <= 14) {
- if (pAd->NicConfig2.field.ExternalLNAForG) {
- RssiOffset = 2;
- } else {
- RssiOffset = 5;
- }
- } else {
- if (pAd->NicConfig2.field.ExternalLNAForA) {
- RssiOffset = 5;
- } else {
- RssiOffset = 8;
- }
- }
-
- /*if (MCS15) */
- if ((pTable == RateSwitchTable11BGN3S) || (pTable == RateSwitchTable11N3S) || (pTable == RateSwitchTable)) { /* N mode with 3 stream // 3*3 */
- if (MCS23 && (Rssi >= -70))
- TxRateIdx = MCS23;
- else if (MCS22 && (Rssi >= -72))
- TxRateIdx = MCS22;
- else if (MCS21 && (Rssi >= -76))
- TxRateIdx = MCS21;
- else if (MCS20 && (Rssi >= -78))
- TxRateIdx = MCS20;
- else if (MCS4 && (Rssi >= -82))
- TxRateIdx = MCS4;
- else if (MCS3 && (Rssi >= -84))
- TxRateIdx = MCS3;
- else if (MCS2 && (Rssi >= -86))
- TxRateIdx = MCS2;
- else if (MCS1 && (Rssi >= -88))
- TxRateIdx = MCS1;
- else
- TxRateIdx = MCS0;
- }
-/* else if ((pTable == RateSwitchTable11BGN2S) || (pTable == RateSwitchTable11BGN2SForABand) ||(pTable == RateSwitchTable11N2S) ||(pTable == RateSwitchTable11N2SForABand) || (pTable == RateSwitchTable)) */
- else if ((pTable == RateSwitchTable11BGN2S) || (pTable == RateSwitchTable11BGN2SForABand) || (pTable == RateSwitchTable11N2S) || (pTable == RateSwitchTable11N2SForABand)) /* 3*3 */
- { /* N mode with 2 stream */
- if (MCS15 && (Rssi >= (-70 + RssiOffset)))
- TxRateIdx = MCS15;
- else if (MCS14 && (Rssi >= (-72 + RssiOffset)))
- TxRateIdx = MCS14;
- else if (MCS13 && (Rssi >= (-76 + RssiOffset)))
- TxRateIdx = MCS13;
- else if (MCS12 && (Rssi >= (-78 + RssiOffset)))
- TxRateIdx = MCS12;
- else if (MCS4 && (Rssi >= (-82 + RssiOffset)))
- TxRateIdx = MCS4;
- else if (MCS3 && (Rssi >= (-84 + RssiOffset)))
- TxRateIdx = MCS3;
- else if (MCS2 && (Rssi >= (-86 + RssiOffset)))
- TxRateIdx = MCS2;
- else if (MCS1 && (Rssi >= (-88 + RssiOffset)))
- TxRateIdx = MCS1;
- else
- TxRateIdx = MCS0;
- } else if ((pTable == RateSwitchTable11BGN1S) || (pTable == RateSwitchTable11N1S)) { /* N mode with 1 stream */
- if (MCS7 && (Rssi > (-72 + RssiOffset)))
- TxRateIdx = MCS7;
- else if (MCS6 && (Rssi > (-74 + RssiOffset)))
- TxRateIdx = MCS6;
- else if (MCS5 && (Rssi > (-77 + RssiOffset)))
- TxRateIdx = MCS5;
- else if (MCS4 && (Rssi > (-79 + RssiOffset)))
- TxRateIdx = MCS4;
- else if (MCS3 && (Rssi > (-81 + RssiOffset)))
- TxRateIdx = MCS3;
- else if (MCS2 && (Rssi > (-83 + RssiOffset)))
- TxRateIdx = MCS2;
- else if (MCS1 && (Rssi > (-86 + RssiOffset)))
- TxRateIdx = MCS1;
- else
- TxRateIdx = MCS0;
- } else { /* Legacy mode */
- if (MCS7 && (Rssi > -70))
- TxRateIdx = MCS7;
- else if (MCS6 && (Rssi > -74))
- TxRateIdx = MCS6;
- else if (MCS5 && (Rssi > -78))
- TxRateIdx = MCS5;
- else if (MCS4 && (Rssi > -82))
- TxRateIdx = MCS4;
- else if (MCS4 == 0) /* for B-only mode */
- TxRateIdx = MCS3;
- else if (MCS3 && (Rssi > -85))
- TxRateIdx = MCS3;
- else if (MCS2 && (Rssi > -87))
- TxRateIdx = MCS2;
- else if (MCS1 && (Rssi > -90))
- TxRateIdx = MCS1;
- else
- TxRateIdx = MCS0;
- }
-
- /* if (TxRateIdx != pAd->CommonCfg.TxRateIndex) */
- {
- pEntry->CurrTxRateIndex = TxRateIdx;
- pNextTxRate =
- (struct rt_rtmp_tx_rate_switch *) &
- pTable[(pEntry->CurrTxRateIndex + 1) * 5];
- MlmeSetTxRate(pAd, pEntry, pNextTxRate);
- }
-
- NdisZeroMemory(pEntry->TxQuality,
- sizeof(u16)*
- MAX_STEP_OF_TX_RATE_SWITCH);
- NdisZeroMemory(pEntry->PER,
- sizeof(u8)*
- MAX_STEP_OF_TX_RATE_SWITCH);
- pEntry->fLastSecAccordingRSSI = TRUE;
- /* reset all OneSecTx counters */
- RESET_ONE_SEC_TX_CNT(pEntry);
-
- continue;
- }
-
- if (pEntry->fLastSecAccordingRSSI == TRUE) {
- pEntry->fLastSecAccordingRSSI = FALSE;
- pEntry->LastSecTxRateChangeAction = 0;
- /* reset all OneSecTx counters */
- RESET_ONE_SEC_TX_CNT(pEntry);
-
- continue;
- }
-
- do {
- BOOLEAN bTrainUpDown = FALSE;
-
- pEntry->CurrTxRateStableTime++;
-
- /* downgrade TX quality if PER >= Rate-Down threshold */
- if (TxErrorRatio >= TrainDown) {
- bTrainUpDown = TRUE;
- pEntry->TxQuality[CurrRateIdx] =
- DRS_TX_QUALITY_WORST_BOUND;
- }
- /* upgrade TX quality if PER <= Rate-Up threshold */
- else if (TxErrorRatio <= TrainUp) {
- bTrainUpDown = TRUE;
- bUpgradeQuality = TRUE;
- if (pEntry->TxQuality[CurrRateIdx])
- pEntry->TxQuality[CurrRateIdx]--; /* quality very good in CurrRate */
-
- if (pEntry->TxRateUpPenalty)
- pEntry->TxRateUpPenalty--;
- else if (pEntry->TxQuality[UpRateIdx])
- pEntry->TxQuality[UpRateIdx]--; /* may improve next UP rate's quality */
- }
-
- pEntry->PER[CurrRateIdx] = (u8)TxErrorRatio;
-
- if (bTrainUpDown) {
- /* perform DRS - consider TxRate Down first, then rate up. */
- if ((CurrRateIdx != DownRateIdx)
- && (pEntry->TxQuality[CurrRateIdx] >=
- DRS_TX_QUALITY_WORST_BOUND)) {
- pEntry->CurrTxRateIndex = DownRateIdx;
- } else if ((CurrRateIdx != UpRateIdx)
- && (pEntry->TxQuality[UpRateIdx] <=
- 0)) {
- pEntry->CurrTxRateIndex = UpRateIdx;
- }
- }
- } while (FALSE);
-
- /* if rate-up happen, clear all bad history of all TX rates */
- if (pEntry->CurrTxRateIndex > CurrRateIdx) {
- pEntry->CurrTxRateStableTime = 0;
- pEntry->TxRateUpPenalty = 0;
- pEntry->LastSecTxRateChangeAction = 1; /* rate UP */
- NdisZeroMemory(pEntry->TxQuality,
- sizeof(u16)*
- MAX_STEP_OF_TX_RATE_SWITCH);
- NdisZeroMemory(pEntry->PER,
- sizeof(u8)*
- MAX_STEP_OF_TX_RATE_SWITCH);
-
- /* */
- /* For TxRate fast train up */
- /* */
- if (!pAd->StaCfg.StaQuickResponeForRateUpTimerRunning) {
- RTMPSetTimer(&pAd->StaCfg.
- StaQuickResponeForRateUpTimer,
- 100);
-
- pAd->StaCfg.
- StaQuickResponeForRateUpTimerRunning = TRUE;
- }
- bTxRateChanged = TRUE;
- }
- /* if rate-down happen, only clear DownRate's bad history */
- else if (pEntry->CurrTxRateIndex < CurrRateIdx) {
- pEntry->CurrTxRateStableTime = 0;
- pEntry->TxRateUpPenalty = 0; /* no penalty */
- pEntry->LastSecTxRateChangeAction = 2; /* rate DOWN */
- pEntry->TxQuality[pEntry->CurrTxRateIndex] = 0;
- pEntry->PER[pEntry->CurrTxRateIndex] = 0;
-
- /* */
- /* For TxRate fast train down */
- /* */
- if (!pAd->StaCfg.StaQuickResponeForRateUpTimerRunning) {
- RTMPSetTimer(&pAd->StaCfg.
- StaQuickResponeForRateUpTimer,
- 100);
-
- pAd->StaCfg.
- StaQuickResponeForRateUpTimerRunning = TRUE;
- }
- bTxRateChanged = TRUE;
- } else {
- pEntry->LastSecTxRateChangeAction = 0; /* rate no change */
- bTxRateChanged = FALSE;
- }
-
- pEntry->LastTxOkCount = TxSuccess;
- {
- u8 tmpTxRate;
-
- /* to fix tcp ack issue */
- if (!bTxRateChanged
- && (pAd->RalinkCounters.OneSecReceivedByteCount >
- (pAd->RalinkCounters.
- OneSecTransmittedByteCount * 5))) {
- tmpTxRate = DownRateIdx;
- DBGPRINT_RAW(RT_DEBUG_TRACE,
- ("DRS: Rx(%d) is 5 times larger than Tx(%d), use low rate (curr=%d, tmp=%d)\n",
- pAd->RalinkCounters.
- OneSecReceivedByteCount,
- pAd->RalinkCounters.
- OneSecTransmittedByteCount,
- pEntry->CurrTxRateIndex,
- tmpTxRate));
- } else {
- tmpTxRate = pEntry->CurrTxRateIndex;
- }
-
- pNextTxRate =
- (struct rt_rtmp_tx_rate_switch *) & pTable[(tmpTxRate + 1) *
- 5];
- }
- if (bTxRateChanged && pNextTxRate) {
- MlmeSetTxRate(pAd, pEntry, pNextTxRate);
- }
- /* reset all OneSecTx counters */
- RESET_ONE_SEC_TX_CNT(pEntry);
- }
-}
-
-/*
- ========================================================================
- Routine Description:
- Station side, Auto TxRate faster train up timer call back function.
-
- Arguments:
- SystemSpecific1 - Not used.
- FunctionContext - Pointer to our Adapter context.
- SystemSpecific2 - Not used.
- SystemSpecific3 - Not used.
-
- Return Value:
- None
-
- ========================================================================
-*/
-void StaQuickResponeForRateUpExec(void *SystemSpecific1,
- void *FunctionContext,
- void *SystemSpecific2,
- void *SystemSpecific3)
-{
- struct rt_rtmp_adapter *pAd = (struct rt_rtmp_adapter *)FunctionContext;
- u8 UpRateIdx = 0, DownRateIdx = 0, CurrRateIdx = 0;
- unsigned long TxTotalCnt;
- unsigned long TxErrorRatio = 0;
- BOOLEAN bTxRateChanged; /*, bUpgradeQuality = FALSE; */
- struct rt_rtmp_tx_rate_switch *pCurrTxRate, *pNextTxRate = NULL;
- u8 *pTable;
- u8 TableSize = 0;
- u8 InitTxRateIdx = 0, TrainUp, TrainDown;
- TX_STA_CNT1_STRUC StaTx1;
- TX_STA_CNT0_STRUC TxStaCnt0;
- char Rssi, ratio;
- unsigned long TxRetransmit = 0, TxSuccess = 0, TxFailCount = 0;
- struct rt_mac_table_entry *pEntry;
- unsigned long i;
-
- pAd->StaCfg.StaQuickResponeForRateUpTimerRunning = FALSE;
-
- /* */
- /* walk through MAC table, see if need to change AP's TX rate toward each entry */
- /* */
- for (i = 1; i < MAX_LEN_OF_MAC_TABLE; i++) {
- pEntry = &pAd->MacTab.Content[i];
-
- /* check if this entry need to switch rate automatically */
- if (RTMPCheckEntryEnableAutoRateSwitch(pAd, pEntry) == FALSE)
- continue;
-
- if (INFRA_ON(pAd) && (i == 1))
- Rssi = RTMPMaxRssi(pAd,
- pAd->StaCfg.RssiSample.AvgRssi0,
- pAd->StaCfg.RssiSample.AvgRssi1,
- pAd->StaCfg.RssiSample.AvgRssi2);
- else
- Rssi = RTMPMaxRssi(pAd,
- pEntry->RssiSample.AvgRssi0,
- pEntry->RssiSample.AvgRssi1,
- pEntry->RssiSample.AvgRssi2);
-
- CurrRateIdx = pAd->CommonCfg.TxRateIndex;
-
- MlmeSelectTxRateTable(pAd, pEntry, &pTable, &TableSize,
- &InitTxRateIdx);
-
- /* decide the next upgrade rate and downgrade rate, if any */
- if ((CurrRateIdx > 0) && (CurrRateIdx < (TableSize - 1))) {
- UpRateIdx = CurrRateIdx + 1;
- DownRateIdx = CurrRateIdx - 1;
- } else if (CurrRateIdx == 0) {
- UpRateIdx = CurrRateIdx + 1;
- DownRateIdx = CurrRateIdx;
- } else if (CurrRateIdx == (TableSize - 1)) {
- UpRateIdx = CurrRateIdx;
- DownRateIdx = CurrRateIdx - 1;
- }
-
- pCurrTxRate =
- (struct rt_rtmp_tx_rate_switch *) & pTable[(CurrRateIdx + 1) * 5];
-
- if ((Rssi > -65) && (pCurrTxRate->Mode >= MODE_HTMIX)) {
- TrainUp =
- (pCurrTxRate->TrainUp +
- (pCurrTxRate->TrainUp >> 1));
- TrainDown =
- (pCurrTxRate->TrainDown +
- (pCurrTxRate->TrainDown >> 1));
- } else {
- TrainUp = pCurrTxRate->TrainUp;
- TrainDown = pCurrTxRate->TrainDown;
- }
-
- if (pAd->MacTab.Size == 1) {
- /* Update statistic counter */
- RTMP_IO_READ32(pAd, TX_STA_CNT0, &TxStaCnt0.word);
- RTMP_IO_READ32(pAd, TX_STA_CNT1, &StaTx1.word);
-
- TxRetransmit = StaTx1.field.TxRetransmit;
- TxSuccess = StaTx1.field.TxSuccess;
- TxFailCount = TxStaCnt0.field.TxFailCount;
- TxTotalCnt = TxRetransmit + TxSuccess + TxFailCount;
-
- pAd->RalinkCounters.OneSecTxRetryOkCount +=
- StaTx1.field.TxRetransmit;
- pAd->RalinkCounters.OneSecTxNoRetryOkCount +=
- StaTx1.field.TxSuccess;
- pAd->RalinkCounters.OneSecTxFailCount +=
- TxStaCnt0.field.TxFailCount;
- pAd->WlanCounters.TransmittedFragmentCount.u.LowPart +=
- StaTx1.field.TxSuccess;
- pAd->WlanCounters.RetryCount.u.LowPart +=
- StaTx1.field.TxRetransmit;
- pAd->WlanCounters.FailedCount.u.LowPart +=
- TxStaCnt0.field.TxFailCount;
-
- if (TxTotalCnt)
- TxErrorRatio =
- ((TxRetransmit +
- TxFailCount) * 100) / TxTotalCnt;
- } else {
- TxTotalCnt = pEntry->OneSecTxNoRetryOkCount +
- pEntry->OneSecTxRetryOkCount +
- pEntry->OneSecTxFailCount;
-
- if (TxTotalCnt)
- TxErrorRatio =
- ((pEntry->OneSecTxRetryOkCount +
- pEntry->OneSecTxFailCount) * 100) /
- TxTotalCnt;
- }
-
- /* */
- /* CASE 1. when TX samples are fewer than 15, then decide TX rate solely on RSSI */
- /* (criteria copied from RT2500 for Netopia case) */
- /* */
- if (TxTotalCnt <= 12) {
- NdisZeroMemory(pAd->DrsCounters.TxQuality,
- sizeof(u16)*
- MAX_STEP_OF_TX_RATE_SWITCH);
- NdisZeroMemory(pAd->DrsCounters.PER,
- sizeof(u8)*
- MAX_STEP_OF_TX_RATE_SWITCH);
-
- if ((pAd->DrsCounters.LastSecTxRateChangeAction == 1)
- && (CurrRateIdx != DownRateIdx)) {
- pAd->CommonCfg.TxRateIndex = DownRateIdx;
- pAd->DrsCounters.TxQuality[CurrRateIdx] =
- DRS_TX_QUALITY_WORST_BOUND;
- } else
- if ((pAd->DrsCounters.LastSecTxRateChangeAction ==
- 2) && (CurrRateIdx != UpRateIdx)) {
- pAd->CommonCfg.TxRateIndex = UpRateIdx;
- }
-
- DBGPRINT_RAW(RT_DEBUG_TRACE,
- ("QuickDRS: TxTotalCnt <= 15, train back to original rate \n"));
- return;
- }
-
- do {
- unsigned long OneSecTxNoRetryOKRationCount;
-
- if (pAd->DrsCounters.LastTimeTxRateChangeAction == 0)
- ratio = 5;
- else
- ratio = 4;
-
- /* downgrade TX quality if PER >= Rate-Down threshold */
- if (TxErrorRatio >= TrainDown) {
- pAd->DrsCounters.TxQuality[CurrRateIdx] =
- DRS_TX_QUALITY_WORST_BOUND;
- }
-
- pAd->DrsCounters.PER[CurrRateIdx] =
- (u8)TxErrorRatio;
-
- OneSecTxNoRetryOKRationCount = (TxSuccess * ratio);
-
- /* perform DRS - consider TxRate Down first, then rate up. */
- if ((pAd->DrsCounters.LastSecTxRateChangeAction == 1)
- && (CurrRateIdx != DownRateIdx)) {
- if ((pAd->DrsCounters.LastTxOkCount + 2) >=
- OneSecTxNoRetryOKRationCount) {
- pAd->CommonCfg.TxRateIndex =
- DownRateIdx;
- pAd->DrsCounters.
- TxQuality[CurrRateIdx] =
- DRS_TX_QUALITY_WORST_BOUND;
-
- }
-
- } else
- if ((pAd->DrsCounters.LastSecTxRateChangeAction ==
- 2) && (CurrRateIdx != UpRateIdx)) {
- if ((TxErrorRatio >= 50)
- || (TxErrorRatio >= TrainDown)) {
-
- } else if ((pAd->DrsCounters.LastTxOkCount + 2)
- >= OneSecTxNoRetryOKRationCount) {
- pAd->CommonCfg.TxRateIndex = UpRateIdx;
- }
- }
- } while (FALSE);
-
- /* if rate-up happen, clear all bad history of all TX rates */
- if (pAd->CommonCfg.TxRateIndex > CurrRateIdx) {
- pAd->DrsCounters.TxRateUpPenalty = 0;
- NdisZeroMemory(pAd->DrsCounters.TxQuality,
- sizeof(u16)*
- MAX_STEP_OF_TX_RATE_SWITCH);
- NdisZeroMemory(pAd->DrsCounters.PER,
- sizeof(u8)*
- MAX_STEP_OF_TX_RATE_SWITCH);
- bTxRateChanged = TRUE;
- }
- /* if rate-down happen, only clear DownRate's bad history */
- else if (pAd->CommonCfg.TxRateIndex < CurrRateIdx) {
- DBGPRINT_RAW(RT_DEBUG_TRACE,
- ("QuickDRS: --TX rate from %d to %d \n",
- CurrRateIdx, pAd->CommonCfg.TxRateIndex));
-
- pAd->DrsCounters.TxRateUpPenalty = 0; /* no penalty */
- pAd->DrsCounters.TxQuality[pAd->CommonCfg.TxRateIndex] =
- 0;
- pAd->DrsCounters.PER[pAd->CommonCfg.TxRateIndex] = 0;
- bTxRateChanged = TRUE;
- } else {
- bTxRateChanged = FALSE;
- }
-
- pNextTxRate =
- (struct rt_rtmp_tx_rate_switch *) &
- pTable[(pAd->CommonCfg.TxRateIndex + 1) * 5];
- if (bTxRateChanged && pNextTxRate) {
- MlmeSetTxRate(pAd, pEntry, pNextTxRate);
- }
- }
-}
-
-/*
- ==========================================================================
- Description:
- This routine is executed periodically inside MlmePeriodicExec() after
- association with an AP.
- It checks if StaCfg.Psm is consistent with user policy (recorded in
- StaCfg.WindowsPowerMode). If not, enforce user policy. However,
- there're some conditions to consider:
- 1. we don't support power-saving in ADHOC mode, so Psm=PWR_ACTIVE all
- the time when Mibss==TRUE
- 2. When link up in INFRA mode, Psm should not be switch to PWR_SAVE
- if outgoing traffic available in TxRing or MgmtRing.
- Output:
- 1. change pAd->StaCfg.Psm to PWR_SAVE or leave it untouched
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
- */
-void MlmeCheckPsmChange(struct rt_rtmp_adapter *pAd, unsigned long Now32)
-{
- unsigned long PowerMode;
-
- /* condition - */
- /* 1. Psm maybe ON only happen in INFRASTRUCTURE mode */
- /* 2. user wants either MAX_PSP or FAST_PSP */
- /* 3. but current psm is not in PWR_SAVE */
- /* 4. CNTL state machine is not doing SCANning */
- /* 5. no TX SUCCESS event for the past 1-sec period */
- PowerMode = pAd->StaCfg.WindowsPowerMode;
-
- if (INFRA_ON(pAd) &&
- (PowerMode != Ndis802_11PowerModeCAM) &&
- (pAd->StaCfg.Psm == PWR_ACTIVE) &&
-/* (! RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_BSS_SCAN_IN_PROGRESS)) */
- (pAd->Mlme.CntlMachine.CurrState == CNTL_IDLE) &&
- RTMP_TEST_PSFLAG(pAd, fRTMP_PS_CAN_GO_SLEEP)
- /*&&
- (pAd->RalinkCounters.OneSecTxNoRetryOkCount == 0) &&
- (pAd->RalinkCounters.OneSecTxRetryOkCount == 0) */
- ) {
- NdisGetSystemUpTime(&pAd->Mlme.LastSendNULLpsmTime);
- pAd->RalinkCounters.RxCountSinceLastNULL = 0;
- RTMP_SET_PSM_BIT(pAd, PWR_SAVE);
- if (!
- (pAd->CommonCfg.bAPSDCapable
- && pAd->CommonCfg.APEdcaParm.bAPSDCapable)) {
- RTMPSendNullFrame(pAd, pAd->CommonCfg.TxRate, FALSE);
- } else {
- RTMPSendNullFrame(pAd, pAd->CommonCfg.TxRate, TRUE);
- }
- }
-}
-
-/* IRQL = PASSIVE_LEVEL */
-/* IRQL = DISPATCH_LEVEL */
-void MlmeSetPsmBit(struct rt_rtmp_adapter *pAd, u16 psm)
-{
- AUTO_RSP_CFG_STRUC csr4;
-
- pAd->StaCfg.Psm = psm;
- RTMP_IO_READ32(pAd, AUTO_RSP_CFG, &csr4.word);
- csr4.field.AckCtsPsmBit = (psm == PWR_SAVE) ? 1 : 0;
- RTMP_IO_WRITE32(pAd, AUTO_RSP_CFG, csr4.word);
-
- DBGPRINT(RT_DEBUG_TRACE, ("MlmeSetPsmBit = %d\n", psm));
-}
-
-/*
- ==========================================================================
- Description:
- This routine calculates TxPER, RxPER of the past N-sec period. And
- according to the calculation result, ChannelQuality is calculated here
- to decide if current AP is still doing the job.
-
- If ChannelQuality is not good, a ROAMing attempt may be tried later.
- Output:
- StaCfg.ChannelQuality - 0..100
-
- IRQL = DISPATCH_LEVEL
-
- NOTE: This routine decide channle quality based on RX CRC error ratio.
- Caller should make sure a function call to NICUpdateRawCounters(pAd)
- is performed right before this routine, so that this routine can decide
- channel quality based on the most up-to-date information
- ==========================================================================
- */
-void MlmeCalculateChannelQuality(struct rt_rtmp_adapter *pAd,
- struct rt_mac_table_entry *pMacEntry, unsigned long Now32)
-{
- unsigned long TxOkCnt, TxCnt, TxPER, TxPRR;
- unsigned long RxCnt, RxPER;
- u8 NorRssi;
- char MaxRssi;
- struct rt_rssi_sample *pRssiSample = NULL;
- u32 OneSecTxNoRetryOkCount = 0;
- u32 OneSecTxRetryOkCount = 0;
- u32 OneSecTxFailCount = 0;
- u32 OneSecRxOkCnt = 0;
- u32 OneSecRxFcsErrCnt = 0;
- unsigned long ChannelQuality = 0; /* 0..100, Channel Quality Indication for Roaming */
- unsigned long BeaconLostTime = pAd->StaCfg.BeaconLostTime;
-
- if (pAd->OpMode == OPMODE_STA) {
- pRssiSample = &pAd->StaCfg.RssiSample;
- OneSecTxNoRetryOkCount =
- pAd->RalinkCounters.OneSecTxNoRetryOkCount;
- OneSecTxRetryOkCount = pAd->RalinkCounters.OneSecTxRetryOkCount;
- OneSecTxFailCount = pAd->RalinkCounters.OneSecTxFailCount;
- OneSecRxOkCnt = pAd->RalinkCounters.OneSecRxOkCnt;
- OneSecRxFcsErrCnt = pAd->RalinkCounters.OneSecRxFcsErrCnt;
- }
-
- MaxRssi = RTMPMaxRssi(pAd, pRssiSample->LastRssi0,
- pRssiSample->LastRssi1, pRssiSample->LastRssi2);
-
- /* */
- /* calculate TX packet error ratio and TX retry ratio - if too few TX samples, skip TX related statistics */
- /* */
- TxOkCnt = OneSecTxNoRetryOkCount + OneSecTxRetryOkCount;
- TxCnt = TxOkCnt + OneSecTxFailCount;
- if (TxCnt < 5) {
- TxPER = 0;
- TxPRR = 0;
- } else {
- TxPER = (OneSecTxFailCount * 100) / TxCnt;
- TxPRR = ((TxCnt - OneSecTxNoRetryOkCount) * 100) / TxCnt;
- }
-
- /* */
- /* calculate RX PER - don't take RxPER into consideration if too few sample */
- /* */
- RxCnt = OneSecRxOkCnt + OneSecRxFcsErrCnt;
- if (RxCnt < 5)
- RxPER = 0;
- else
- RxPER = (OneSecRxFcsErrCnt * 100) / RxCnt;
-
- /* */
- /* decide ChannelQuality based on: 1)last BEACON received time, 2)last RSSI, 3)TxPER, and 4)RxPER */
- /* */
- if ((pAd->OpMode == OPMODE_STA) && INFRA_ON(pAd) && (OneSecTxNoRetryOkCount < 2) && /* no heavy traffic */
- ((pAd->StaCfg.LastBeaconRxTime + BeaconLostTime) < Now32)) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("BEACON lost > %ld msec with TxOkCnt=%ld -> CQI=0\n",
- BeaconLostTime, TxOkCnt));
- ChannelQuality = 0;
- } else {
- /* Normalize Rssi */
- if (MaxRssi > -40)
- NorRssi = 100;
- else if (MaxRssi < -90)
- NorRssi = 0;
- else
- NorRssi = (MaxRssi + 90) * 2;
-
- /* ChannelQuality = W1*RSSI + W2*TxPRR + W3*RxPER (RSSI 0..100), (TxPER 100..0), (RxPER 100..0) */
- ChannelQuality = (RSSI_WEIGHTING * NorRssi +
- TX_WEIGHTING * (100 - TxPRR) +
- RX_WEIGHTING * (100 - RxPER)) / 100;
- }
-
- if (pAd->OpMode == OPMODE_STA)
- pAd->Mlme.ChannelQuality =
- (ChannelQuality > 100) ? 100 : ChannelQuality;
-
-}
-
-/* IRQL = DISPATCH_LEVEL */
-void MlmeSetTxPreamble(struct rt_rtmp_adapter *pAd, u16 TxPreamble)
-{
- AUTO_RSP_CFG_STRUC csr4;
-
- /* */
- /* Always use Long preamble before verifiation short preamble functionality works well. */
- /* Todo: remove the following line if short preamble functionality works */
- /* */
- /*TxPreamble = Rt802_11PreambleLong; */
-
- RTMP_IO_READ32(pAd, AUTO_RSP_CFG, &csr4.word);
- if (TxPreamble == Rt802_11PreambleLong) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("MlmeSetTxPreamble (= long PREAMBLE)\n"));
- OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_SHORT_PREAMBLE_INUSED);
- csr4.field.AutoResponderPreamble = 0;
- } else {
- /* NOTE: 1Mbps should always use long preamble */
- DBGPRINT(RT_DEBUG_TRACE,
- ("MlmeSetTxPreamble (= short PREAMBLE)\n"));
- OPSTATUS_SET_FLAG(pAd, fOP_STATUS_SHORT_PREAMBLE_INUSED);
- csr4.field.AutoResponderPreamble = 1;
- }
-
- RTMP_IO_WRITE32(pAd, AUTO_RSP_CFG, csr4.word);
-}
-
-/*
- ==========================================================================
- Description:
- Update basic rate bitmap
- ==========================================================================
- */
-
-void UpdateBasicRateBitmap(struct rt_rtmp_adapter *pAdapter)
-{
- int i, j;
- /* 1 2 5.5, 11, 6, 9, 12, 18, 24, 36, 48, 54 */
- u8 rate[] = { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108 };
- u8 *sup_p = pAdapter->CommonCfg.SupRate;
- u8 *ext_p = pAdapter->CommonCfg.ExtRate;
- unsigned long bitmap = pAdapter->CommonCfg.BasicRateBitmap;
-
- /* if A mode, always use fix BasicRateBitMap */
- /*if (pAdapter->CommonCfg.Channel == PHY_11A) */
- if (pAdapter->CommonCfg.Channel > 14)
- pAdapter->CommonCfg.BasicRateBitmap = 0x150; /* 6, 12, 24M */
- /* End of if */
-
- if (pAdapter->CommonCfg.BasicRateBitmap > 4095) {
- /* (2 ^ MAX_LEN_OF_SUPPORTED_RATES) -1 */
- return;
- }
- /* End of if */
- for (i = 0; i < MAX_LEN_OF_SUPPORTED_RATES; i++) {
- sup_p[i] &= 0x7f;
- ext_p[i] &= 0x7f;
- } /* End of for */
-
- for (i = 0; i < MAX_LEN_OF_SUPPORTED_RATES; i++) {
- if (bitmap & (1 << i)) {
- for (j = 0; j < MAX_LEN_OF_SUPPORTED_RATES; j++) {
- if (sup_p[j] == rate[i])
- sup_p[j] |= 0x80;
- /* End of if */
- } /* End of for */
-
- for (j = 0; j < MAX_LEN_OF_SUPPORTED_RATES; j++) {
- if (ext_p[j] == rate[i])
- ext_p[j] |= 0x80;
- /* End of if */
- } /* End of for */
- } /* End of if */
- } /* End of for */
-} /* End of UpdateBasicRateBitmap */
-
-/* IRQL = PASSIVE_LEVEL */
-/* IRQL = DISPATCH_LEVEL */
-/* bLinkUp is to identify the initial link speed. */
-/* TRUE indicates the rate update at linkup, we should not try to set the rate at 54Mbps. */
-void MlmeUpdateTxRates(struct rt_rtmp_adapter *pAd, IN BOOLEAN bLinkUp, u8 apidx)
-{
- int i, num;
- u8 Rate = RATE_6, MaxDesire = RATE_1, MaxSupport = RATE_1;
- u8 MinSupport = RATE_54;
- unsigned long BasicRateBitmap = 0;
- u8 CurrBasicRate = RATE_1;
- u8 *pSupRate, SupRateLen, *pExtRate, ExtRateLen;
- PHTTRANSMIT_SETTING pHtPhy = NULL;
- PHTTRANSMIT_SETTING pMaxHtPhy = NULL;
- PHTTRANSMIT_SETTING pMinHtPhy = NULL;
- BOOLEAN *auto_rate_cur_p;
- u8 HtMcs = MCS_AUTO;
-
- /* find max desired rate */
- UpdateBasicRateBitmap(pAd);
-
- num = 0;
- auto_rate_cur_p = NULL;
- for (i = 0; i < MAX_LEN_OF_SUPPORTED_RATES; i++) {
- switch (pAd->CommonCfg.DesireRate[i] & 0x7f) {
- case 2:
- Rate = RATE_1;
- num++;
- break;
- case 4:
- Rate = RATE_2;
- num++;
- break;
- case 11:
- Rate = RATE_5_5;
- num++;
- break;
- case 22:
- Rate = RATE_11;
- num++;
- break;
- case 12:
- Rate = RATE_6;
- num++;
- break;
- case 18:
- Rate = RATE_9;
- num++;
- break;
- case 24:
- Rate = RATE_12;
- num++;
- break;
- case 36:
- Rate = RATE_18;
- num++;
- break;
- case 48:
- Rate = RATE_24;
- num++;
- break;
- case 72:
- Rate = RATE_36;
- num++;
- break;
- case 96:
- Rate = RATE_48;
- num++;
- break;
- case 108:
- Rate = RATE_54;
- num++;
- break;
- /*default: Rate = RATE_1; break; */
- }
- if (MaxDesire < Rate)
- MaxDesire = Rate;
- }
-
-/*=========================================================================== */
-/*=========================================================================== */
- {
- pHtPhy = &pAd->StaCfg.HTPhyMode;
- pMaxHtPhy = &pAd->StaCfg.MaxHTPhyMode;
- pMinHtPhy = &pAd->StaCfg.MinHTPhyMode;
-
- auto_rate_cur_p = &pAd->StaCfg.bAutoTxRateSwitch;
- HtMcs = pAd->StaCfg.DesiredTransmitSetting.field.MCS;
-
- if ((pAd->StaCfg.BssType == BSS_ADHOC) &&
- (pAd->CommonCfg.PhyMode == PHY_11B) &&
- (MaxDesire > RATE_11)) {
- MaxDesire = RATE_11;
- }
- }
-
- pAd->CommonCfg.MaxDesiredRate = MaxDesire;
- pMinHtPhy->word = 0;
- pMaxHtPhy->word = 0;
- pHtPhy->word = 0;
-
- /* Auto rate switching is enabled only if more than one DESIRED RATES are */
- /* specified; otherwise disabled */
- if (num <= 1) {
- /*OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_TX_RATE_SWITCH_ENABLED); */
- /*pAd->CommonCfg.bAutoTxRateSwitch = FALSE; */
- *auto_rate_cur_p = FALSE;
- } else {
- /*OPSTATUS_SET_FLAG(pAd, fOP_STATUS_TX_RATE_SWITCH_ENABLED); */
- /*pAd->CommonCfg.bAutoTxRateSwitch = TRUE; */
- *auto_rate_cur_p = TRUE;
- }
-
- if (HtMcs != MCS_AUTO) {
- /*OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_TX_RATE_SWITCH_ENABLED); */
- /*pAd->CommonCfg.bAutoTxRateSwitch = FALSE; */
- *auto_rate_cur_p = FALSE;
- } else {
- /*OPSTATUS_SET_FLAG(pAd, fOP_STATUS_TX_RATE_SWITCH_ENABLED); */
- /*pAd->CommonCfg.bAutoTxRateSwitch = TRUE; */
- *auto_rate_cur_p = TRUE;
- }
-
- if ((ADHOC_ON(pAd) || INFRA_ON(pAd)) && (pAd->OpMode == OPMODE_STA)) {
- pSupRate = &pAd->StaActive.SupRate[0];
- pExtRate = &pAd->StaActive.ExtRate[0];
- SupRateLen = pAd->StaActive.SupRateLen;
- ExtRateLen = pAd->StaActive.ExtRateLen;
- } else {
- pSupRate = &pAd->CommonCfg.SupRate[0];
- pExtRate = &pAd->CommonCfg.ExtRate[0];
- SupRateLen = pAd->CommonCfg.SupRateLen;
- ExtRateLen = pAd->CommonCfg.ExtRateLen;
- }
-
- /* find max supported rate */
- for (i = 0; i < SupRateLen; i++) {
- switch (pSupRate[i] & 0x7f) {
- case 2:
- Rate = RATE_1;
- if (pSupRate[i] & 0x80)
- BasicRateBitmap |= 0x0001;
- break;
- case 4:
- Rate = RATE_2;
- if (pSupRate[i] & 0x80)
- BasicRateBitmap |= 0x0002;
- break;
- case 11:
- Rate = RATE_5_5;
- if (pSupRate[i] & 0x80)
- BasicRateBitmap |= 0x0004;
- break;
- case 22:
- Rate = RATE_11;
- if (pSupRate[i] & 0x80)
- BasicRateBitmap |= 0x0008;
- break;
- case 12:
- Rate = RATE_6; /*if (pSupRate[i] & 0x80) */
- BasicRateBitmap |= 0x0010;
- break;
- case 18:
- Rate = RATE_9;
- if (pSupRate[i] & 0x80)
- BasicRateBitmap |= 0x0020;
- break;
- case 24:
- Rate = RATE_12; /*if (pSupRate[i] & 0x80) */
- BasicRateBitmap |= 0x0040;
- break;
- case 36:
- Rate = RATE_18;
- if (pSupRate[i] & 0x80)
- BasicRateBitmap |= 0x0080;
- break;
- case 48:
- Rate = RATE_24; /*if (pSupRate[i] & 0x80) */
- BasicRateBitmap |= 0x0100;
- break;
- case 72:
- Rate = RATE_36;
- if (pSupRate[i] & 0x80)
- BasicRateBitmap |= 0x0200;
- break;
- case 96:
- Rate = RATE_48;
- if (pSupRate[i] & 0x80)
- BasicRateBitmap |= 0x0400;
- break;
- case 108:
- Rate = RATE_54;
- if (pSupRate[i] & 0x80)
- BasicRateBitmap |= 0x0800;
- break;
- default:
- Rate = RATE_1;
- break;
- }
- if (MaxSupport < Rate)
- MaxSupport = Rate;
-
- if (MinSupport > Rate)
- MinSupport = Rate;
- }
-
- for (i = 0; i < ExtRateLen; i++) {
- switch (pExtRate[i] & 0x7f) {
- case 2:
- Rate = RATE_1;
- if (pExtRate[i] & 0x80)
- BasicRateBitmap |= 0x0001;
- break;
- case 4:
- Rate = RATE_2;
- if (pExtRate[i] & 0x80)
- BasicRateBitmap |= 0x0002;
- break;
- case 11:
- Rate = RATE_5_5;
- if (pExtRate[i] & 0x80)
- BasicRateBitmap |= 0x0004;
- break;
- case 22:
- Rate = RATE_11;
- if (pExtRate[i] & 0x80)
- BasicRateBitmap |= 0x0008;
- break;
- case 12:
- Rate = RATE_6; /*if (pExtRate[i] & 0x80) */
- BasicRateBitmap |= 0x0010;
- break;
- case 18:
- Rate = RATE_9;
- if (pExtRate[i] & 0x80)
- BasicRateBitmap |= 0x0020;
- break;
- case 24:
- Rate = RATE_12; /*if (pExtRate[i] & 0x80) */
- BasicRateBitmap |= 0x0040;
- break;
- case 36:
- Rate = RATE_18;
- if (pExtRate[i] & 0x80)
- BasicRateBitmap |= 0x0080;
- break;
- case 48:
- Rate = RATE_24; /*if (pExtRate[i] & 0x80) */
- BasicRateBitmap |= 0x0100;
- break;
- case 72:
- Rate = RATE_36;
- if (pExtRate[i] & 0x80)
- BasicRateBitmap |= 0x0200;
- break;
- case 96:
- Rate = RATE_48;
- if (pExtRate[i] & 0x80)
- BasicRateBitmap |= 0x0400;
- break;
- case 108:
- Rate = RATE_54;
- if (pExtRate[i] & 0x80)
- BasicRateBitmap |= 0x0800;
- break;
- default:
- Rate = RATE_1;
- break;
- }
- if (MaxSupport < Rate)
- MaxSupport = Rate;
-
- if (MinSupport > Rate)
- MinSupport = Rate;
- }
-
- RTMP_IO_WRITE32(pAd, LEGACY_BASIC_RATE, BasicRateBitmap);
-
- /* bug fix */
- /* pAd->CommonCfg.BasicRateBitmap = BasicRateBitmap; */
-
- /* calculate the exptected ACK rate for each TX rate. This info is used to caculate */
- /* the DURATION field of outgoing uniicast DATA/MGMT frame */
- for (i = 0; i < MAX_LEN_OF_SUPPORTED_RATES; i++) {
- if (BasicRateBitmap & (0x01 << i))
- CurrBasicRate = (u8)i;
- pAd->CommonCfg.ExpectedACKRate[i] = CurrBasicRate;
- }
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("MlmeUpdateTxRates[MaxSupport = %d] = MaxDesire %d Mbps\n",
- RateIdToMbps[MaxSupport], RateIdToMbps[MaxDesire]));
- /* max tx rate = min {max desire rate, max supported rate} */
- if (MaxSupport < MaxDesire)
- pAd->CommonCfg.MaxTxRate = MaxSupport;
- else
- pAd->CommonCfg.MaxTxRate = MaxDesire;
-
- pAd->CommonCfg.MinTxRate = MinSupport;
- /* 2003-07-31 john - 2500 doesn't have good sensitivity at high OFDM rates. to increase the success */
- /* ratio of initial DHCP packet exchange, TX rate starts from a lower rate depending */
- /* on average RSSI */
- /* 1. RSSI >= -70db, start at 54 Mbps (short distance) */
- /* 2. -70 > RSSI >= -75, start at 24 Mbps (mid distance) */
- /* 3. -75 > RSSI, start at 11 Mbps (long distance) */
- if (*auto_rate_cur_p) {
- short dbm = 0;
-
- dbm = pAd->StaCfg.RssiSample.AvgRssi0 - pAd->BbpRssiToDbmDelta;
-
- if (bLinkUp == TRUE)
- pAd->CommonCfg.TxRate = RATE_24;
- else
- pAd->CommonCfg.TxRate = pAd->CommonCfg.MaxTxRate;
-
- if (dbm < -75)
- pAd->CommonCfg.TxRate = RATE_11;
- else if (dbm < -70)
- pAd->CommonCfg.TxRate = RATE_24;
-
- /* should never exceed MaxTxRate (consider 11B-only mode) */
- if (pAd->CommonCfg.TxRate > pAd->CommonCfg.MaxTxRate)
- pAd->CommonCfg.TxRate = pAd->CommonCfg.MaxTxRate;
-
- pAd->CommonCfg.TxRateIndex = 0;
- } else {
- pAd->CommonCfg.TxRate = pAd->CommonCfg.MaxTxRate;
- pHtPhy->field.MCS =
- (pAd->CommonCfg.MaxTxRate >
- 3) ? (pAd->CommonCfg.MaxTxRate -
- 4) : pAd->CommonCfg.MaxTxRate;
- pHtPhy->field.MODE =
- (pAd->CommonCfg.MaxTxRate > 3) ? MODE_OFDM : MODE_CCK;
-
- pAd->MacTab.Content[BSSID_WCID].HTPhyMode.field.STBC =
- pHtPhy->field.STBC;
- pAd->MacTab.Content[BSSID_WCID].HTPhyMode.field.ShortGI =
- pHtPhy->field.ShortGI;
- pAd->MacTab.Content[BSSID_WCID].HTPhyMode.field.MCS =
- pHtPhy->field.MCS;
- pAd->MacTab.Content[BSSID_WCID].HTPhyMode.field.MODE =
- pHtPhy->field.MODE;
- }
-
- if (pAd->CommonCfg.TxRate <= RATE_11) {
- pMaxHtPhy->field.MODE = MODE_CCK;
- pMaxHtPhy->field.MCS = pAd->CommonCfg.TxRate;
- pMinHtPhy->field.MCS = pAd->CommonCfg.MinTxRate;
- } else {
- pMaxHtPhy->field.MODE = MODE_OFDM;
- pMaxHtPhy->field.MCS = OfdmRateToRxwiMCS[pAd->CommonCfg.TxRate];
- if (pAd->CommonCfg.MinTxRate >= RATE_6
- && (pAd->CommonCfg.MinTxRate <= RATE_54)) {
- pMinHtPhy->field.MCS =
- OfdmRateToRxwiMCS[pAd->CommonCfg.MinTxRate];
- } else {
- pMinHtPhy->field.MCS = pAd->CommonCfg.MinTxRate;
- }
- }
-
- pHtPhy->word = (pMaxHtPhy->word);
- if (bLinkUp && (pAd->OpMode == OPMODE_STA)) {
- pAd->MacTab.Content[BSSID_WCID].HTPhyMode.word = pHtPhy->word;
- pAd->MacTab.Content[BSSID_WCID].MaxHTPhyMode.word =
- pMaxHtPhy->word;
- pAd->MacTab.Content[BSSID_WCID].MinHTPhyMode.word =
- pMinHtPhy->word;
- } else {
- switch (pAd->CommonCfg.PhyMode) {
- case PHY_11BG_MIXED:
- case PHY_11B:
- case PHY_11BGN_MIXED:
- pAd->CommonCfg.MlmeRate = RATE_1;
- pAd->CommonCfg.MlmeTransmit.field.MODE = MODE_CCK;
- pAd->CommonCfg.MlmeTransmit.field.MCS = RATE_1;
-
-/*#ifdef WIFI_TEST */
- pAd->CommonCfg.RtsRate = RATE_11;
-/*#else */
-/* pAd->CommonCfg.RtsRate = RATE_1; */
-/*#endif */
- break;
- case PHY_11G:
- case PHY_11A:
- case PHY_11AGN_MIXED:
- case PHY_11GN_MIXED:
- case PHY_11N_2_4G:
- case PHY_11AN_MIXED:
- case PHY_11N_5G:
- pAd->CommonCfg.MlmeRate = RATE_6;
- pAd->CommonCfg.RtsRate = RATE_6;
- pAd->CommonCfg.MlmeTransmit.field.MODE = MODE_OFDM;
- pAd->CommonCfg.MlmeTransmit.field.MCS =
- OfdmRateToRxwiMCS[pAd->CommonCfg.MlmeRate];
- break;
- case PHY_11ABG_MIXED:
- case PHY_11ABGN_MIXED:
- if (pAd->CommonCfg.Channel <= 14) {
- pAd->CommonCfg.MlmeRate = RATE_1;
- pAd->CommonCfg.RtsRate = RATE_1;
- pAd->CommonCfg.MlmeTransmit.field.MODE =
- MODE_CCK;
- pAd->CommonCfg.MlmeTransmit.field.MCS = RATE_1;
- } else {
- pAd->CommonCfg.MlmeRate = RATE_6;
- pAd->CommonCfg.RtsRate = RATE_6;
- pAd->CommonCfg.MlmeTransmit.field.MODE =
- MODE_OFDM;
- pAd->CommonCfg.MlmeTransmit.field.MCS =
- OfdmRateToRxwiMCS[pAd->CommonCfg.MlmeRate];
- }
- break;
- default: /* error */
- pAd->CommonCfg.MlmeRate = RATE_6;
- pAd->CommonCfg.MlmeTransmit.field.MODE = MODE_OFDM;
- pAd->CommonCfg.MlmeTransmit.field.MCS =
- OfdmRateToRxwiMCS[pAd->CommonCfg.MlmeRate];
- pAd->CommonCfg.RtsRate = RATE_1;
- break;
- }
- /* */
- /* Keep Basic Mlme Rate. */
- /* */
- pAd->MacTab.Content[MCAST_WCID].HTPhyMode.word =
- pAd->CommonCfg.MlmeTransmit.word;
- if (pAd->CommonCfg.MlmeTransmit.field.MODE == MODE_OFDM)
- pAd->MacTab.Content[MCAST_WCID].HTPhyMode.field.MCS =
- OfdmRateToRxwiMCS[RATE_24];
- else
- pAd->MacTab.Content[MCAST_WCID].HTPhyMode.field.MCS =
- RATE_1;
- pAd->CommonCfg.BasicMlmeRate = pAd->CommonCfg.MlmeRate;
- }
-
- DBGPRINT(RT_DEBUG_TRACE,
- (" MlmeUpdateTxRates (MaxDesire=%d, MaxSupport=%d, MaxTxRate=%d, MinRate=%d, Rate Switching =%d)\n",
- RateIdToMbps[MaxDesire], RateIdToMbps[MaxSupport],
- RateIdToMbps[pAd->CommonCfg.MaxTxRate],
- RateIdToMbps[pAd->CommonCfg.MinTxRate],
- /*OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_TX_RATE_SWITCH_ENABLED) */
- *auto_rate_cur_p));
- DBGPRINT(RT_DEBUG_TRACE,
- (" MlmeUpdateTxRates (TxRate=%d, RtsRate=%d, BasicRateBitmap=0x%04lx)\n",
- RateIdToMbps[pAd->CommonCfg.TxRate],
- RateIdToMbps[pAd->CommonCfg.RtsRate], BasicRateBitmap));
- DBGPRINT(RT_DEBUG_TRACE,
- ("MlmeUpdateTxRates (MlmeTransmit=0x%x, MinHTPhyMode=%x, MaxHTPhyMode=0x%x, HTPhyMode=0x%x)\n",
- pAd->CommonCfg.MlmeTransmit.word,
- pAd->MacTab.Content[BSSID_WCID].MinHTPhyMode.word,
- pAd->MacTab.Content[BSSID_WCID].MaxHTPhyMode.word,
- pAd->MacTab.Content[BSSID_WCID].HTPhyMode.word));
-}
-
-/*
- ==========================================================================
- Description:
- This function update HT Rate setting.
- Input Wcid value is valid for 2 case :
- 1. it's used for Station in infra mode that copy AP rate to Mactable.
- 2. OR Station in adhoc mode to copy peer's HT rate to Mactable.
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
- */
-void MlmeUpdateHtTxRates(struct rt_rtmp_adapter *pAd, u8 apidx)
-{
- u8 StbcMcs; /*j, StbcMcs, bitmask; */
- char i; /* 3*3 */
- struct rt_ht_capability *pRtHtCap = NULL;
- struct rt_ht_phy_info *pActiveHtPhy = NULL;
- unsigned long BasicMCS;
- u8 j, bitmask;
- struct rt_ht_phy_info *pDesireHtPhy = NULL;
- PHTTRANSMIT_SETTING pHtPhy = NULL;
- PHTTRANSMIT_SETTING pMaxHtPhy = NULL;
- PHTTRANSMIT_SETTING pMinHtPhy = NULL;
- BOOLEAN *auto_rate_cur_p;
-
- DBGPRINT(RT_DEBUG_TRACE, ("MlmeUpdateHtTxRates===> \n"));
-
- auto_rate_cur_p = NULL;
-
- {
- pDesireHtPhy = &pAd->StaCfg.DesiredHtPhyInfo;
- pActiveHtPhy = &pAd->StaCfg.DesiredHtPhyInfo;
- pHtPhy = &pAd->StaCfg.HTPhyMode;
- pMaxHtPhy = &pAd->StaCfg.MaxHTPhyMode;
- pMinHtPhy = &pAd->StaCfg.MinHTPhyMode;
-
- auto_rate_cur_p = &pAd->StaCfg.bAutoTxRateSwitch;
- }
-
- if ((ADHOC_ON(pAd) || INFRA_ON(pAd)) && (pAd->OpMode == OPMODE_STA)) {
- if (pAd->StaActive.SupportedPhyInfo.bHtEnable == FALSE)
- return;
-
- pRtHtCap = &pAd->StaActive.SupportedHtPhy;
- pActiveHtPhy = &pAd->StaActive.SupportedPhyInfo;
- StbcMcs = (u8)pAd->MlmeAux.AddHtInfo.AddHtInfo3.StbcMcs;
- BasicMCS =
- pAd->MlmeAux.AddHtInfo.MCSSet[0] +
- (pAd->MlmeAux.AddHtInfo.MCSSet[1] << 8) + (StbcMcs << 16);
- if ((pAd->CommonCfg.DesiredHtPhy.TxSTBC) && (pRtHtCap->RxSTBC)
- && (pAd->Antenna.field.TxPath == 2))
- pMaxHtPhy->field.STBC = STBC_USE;
- else
- pMaxHtPhy->field.STBC = STBC_NONE;
- } else {
- if (pDesireHtPhy->bHtEnable == FALSE)
- return;
-
- pRtHtCap = &pAd->CommonCfg.DesiredHtPhy;
- StbcMcs = (u8)pAd->CommonCfg.AddHTInfo.AddHtInfo3.StbcMcs;
- BasicMCS =
- pAd->CommonCfg.AddHTInfo.MCSSet[0] +
- (pAd->CommonCfg.AddHTInfo.MCSSet[1] << 8) + (StbcMcs << 16);
- if ((pAd->CommonCfg.DesiredHtPhy.TxSTBC) && (pRtHtCap->RxSTBC)
- && (pAd->Antenna.field.TxPath == 2))
- pMaxHtPhy->field.STBC = STBC_USE;
- else
- pMaxHtPhy->field.STBC = STBC_NONE;
- }
-
- /* Decide MAX ht rate. */
- if ((pRtHtCap->GF) && (pAd->CommonCfg.DesiredHtPhy.GF))
- pMaxHtPhy->field.MODE = MODE_HTGREENFIELD;
- else
- pMaxHtPhy->field.MODE = MODE_HTMIX;
-
- if ((pAd->CommonCfg.DesiredHtPhy.ChannelWidth)
- && (pRtHtCap->ChannelWidth))
- pMaxHtPhy->field.BW = BW_40;
- else
- pMaxHtPhy->field.BW = BW_20;
-
- if (pMaxHtPhy->field.BW == BW_20)
- pMaxHtPhy->field.ShortGI =
- (pAd->CommonCfg.DesiredHtPhy.ShortGIfor20 & pRtHtCap->
- ShortGIfor20);
- else
- pMaxHtPhy->field.ShortGI =
- (pAd->CommonCfg.DesiredHtPhy.ShortGIfor40 & pRtHtCap->
- ShortGIfor40);
-
- if (pDesireHtPhy->MCSSet[4] != 0) {
- pMaxHtPhy->field.MCS = 32;
- }
-
- for (i = 23; i >= 0; i--) /* 3*3 */
- {
- j = i / 8;
- bitmask = (1 << (i - (j * 8)));
-
- if ((pActiveHtPhy->MCSSet[j] & bitmask)
- && (pDesireHtPhy->MCSSet[j] & bitmask)) {
- pMaxHtPhy->field.MCS = i;
- break;
- }
-
- if (i == 0)
- break;
- }
-
- /* Copy MIN ht rate. rt2860??? */
- pMinHtPhy->field.BW = BW_20;
- pMinHtPhy->field.MCS = 0;
- pMinHtPhy->field.STBC = 0;
- pMinHtPhy->field.ShortGI = 0;
- /*If STA assigns fixed rate. update to fixed here. */
- if ((pAd->OpMode == OPMODE_STA) && (pDesireHtPhy->MCSSet[0] != 0xff)) {
- if (pDesireHtPhy->MCSSet[4] != 0) {
- pMaxHtPhy->field.MCS = 32;
- pMinHtPhy->field.MCS = 32;
- DBGPRINT(RT_DEBUG_TRACE,
- ("MlmeUpdateHtTxRates<=== Use Fixed MCS = %d\n",
- pMinHtPhy->field.MCS));
- }
-
- for (i = 23; (char)i >= 0; i--) /* 3*3 */
- {
- j = i / 8;
- bitmask = (1 << (i - (j * 8)));
- if ((pDesireHtPhy->MCSSet[j] & bitmask)
- && (pActiveHtPhy->MCSSet[j] & bitmask)) {
- pMaxHtPhy->field.MCS = i;
- pMinHtPhy->field.MCS = i;
- break;
- }
- if (i == 0)
- break;
- }
- }
-
- /* Decide ht rate */
- pHtPhy->field.STBC = pMaxHtPhy->field.STBC;
- pHtPhy->field.BW = pMaxHtPhy->field.BW;
- pHtPhy->field.MODE = pMaxHtPhy->field.MODE;
- pHtPhy->field.MCS = pMaxHtPhy->field.MCS;
- pHtPhy->field.ShortGI = pMaxHtPhy->field.ShortGI;
-
- /* use default now. rt2860 */
- if (pDesireHtPhy->MCSSet[0] != 0xff)
- *auto_rate_cur_p = FALSE;
- else
- *auto_rate_cur_p = TRUE;
-
- DBGPRINT(RT_DEBUG_TRACE,
- (" MlmeUpdateHtTxRates<---.AMsduSize = %d \n",
- pAd->CommonCfg.DesiredHtPhy.AmsduSize));
- DBGPRINT(RT_DEBUG_TRACE,
- ("TX: MCS[0] = %x (choose %d), BW = %d, ShortGI = %d, MODE = %d, \n",
- pActiveHtPhy->MCSSet[0], pHtPhy->field.MCS, pHtPhy->field.BW,
- pHtPhy->field.ShortGI, pHtPhy->field.MODE));
- DBGPRINT(RT_DEBUG_TRACE, ("MlmeUpdateHtTxRates<=== \n"));
-}
-
-void BATableInit(struct rt_rtmp_adapter *pAd, struct rt_ba_table *Tab)
-{
- int i;
-
- Tab->numAsOriginator = 0;
- Tab->numAsRecipient = 0;
- Tab->numDoneOriginator = 0;
- NdisAllocateSpinLock(&pAd->BATabLock);
- for (i = 0; i < MAX_LEN_OF_BA_REC_TABLE; i++) {
- Tab->BARecEntry[i].REC_BA_Status = Recipient_NONE;
- NdisAllocateSpinLock(&(Tab->BARecEntry[i].RxReRingLock));
- }
- for (i = 0; i < MAX_LEN_OF_BA_ORI_TABLE; i++) {
- Tab->BAOriEntry[i].ORI_BA_Status = Originator_NONE;
- }
-}
-
-/* IRQL = DISPATCH_LEVEL */
-void MlmeRadioOff(struct rt_rtmp_adapter *pAd)
-{
- RTMP_MLME_RADIO_OFF(pAd);
-}
-
-/* IRQL = DISPATCH_LEVEL */
-void MlmeRadioOn(struct rt_rtmp_adapter *pAd)
-{
- RTMP_MLME_RADIO_ON(pAd);
-}
-
-/* =========================================================================================== */
-/* bss_table.c */
-/* =========================================================================================== */
-
-/*! \brief initialize BSS table
- * \param p_tab pointer to the table
- * \return none
- * \pre
- * \post
-
- IRQL = PASSIVE_LEVEL
- IRQL = DISPATCH_LEVEL
-
- */
-void BssTableInit(struct rt_bss_table *Tab)
-{
- int i;
-
- Tab->BssNr = 0;
- Tab->BssOverlapNr = 0;
- for (i = 0; i < MAX_LEN_OF_BSS_TABLE; i++) {
- NdisZeroMemory(&Tab->BssEntry[i], sizeof(struct rt_bss_entry));
- Tab->BssEntry[i].Rssi = -127; /* initial the rssi as a minimum value */
- }
-}
-
-/*! \brief search the BSS table by SSID
- * \param p_tab pointer to the bss table
- * \param ssid SSID string
- * \return index of the table, BSS_NOT_FOUND if not in the table
- * \pre
- * \post
- * \note search by sequential search
-
- IRQL = DISPATCH_LEVEL
-
- */
-unsigned long BssTableSearch(struct rt_bss_table *Tab, u8 *pBssid, u8 Channel)
-{
- u8 i;
-
- for (i = 0; i < Tab->BssNr; i++) {
- /* */
- /* Some AP that support A/B/G mode that may used the same BSSID on 11A and 11B/G. */
- /* We should distinguish this case. */
- /* */
- if ((((Tab->BssEntry[i].Channel <= 14) && (Channel <= 14)) ||
- ((Tab->BssEntry[i].Channel > 14) && (Channel > 14))) &&
- MAC_ADDR_EQUAL(Tab->BssEntry[i].Bssid, pBssid)) {
- return i;
- }
- }
- return (unsigned long)BSS_NOT_FOUND;
-}
-
-unsigned long BssSsidTableSearch(struct rt_bss_table *Tab,
- u8 *pBssid,
- u8 *pSsid, u8 SsidLen, u8 Channel)
-{
- u8 i;
-
- for (i = 0; i < Tab->BssNr; i++) {
- /* */
- /* Some AP that support A/B/G mode that may used the same BSSID on 11A and 11B/G. */
- /* We should distinguish this case. */
- /* */
- if ((((Tab->BssEntry[i].Channel <= 14) && (Channel <= 14)) ||
- ((Tab->BssEntry[i].Channel > 14) && (Channel > 14))) &&
- MAC_ADDR_EQUAL(Tab->BssEntry[i].Bssid, pBssid) &&
- SSID_EQUAL(pSsid, SsidLen, Tab->BssEntry[i].Ssid,
- Tab->BssEntry[i].SsidLen)) {
- return i;
- }
- }
- return (unsigned long)BSS_NOT_FOUND;
-}
-
-unsigned long BssTableSearchWithSSID(struct rt_bss_table *Tab,
- u8 *Bssid,
- u8 *pSsid,
- u8 SsidLen, u8 Channel)
-{
- u8 i;
-
- for (i = 0; i < Tab->BssNr; i++) {
- if ((((Tab->BssEntry[i].Channel <= 14) && (Channel <= 14)) ||
- ((Tab->BssEntry[i].Channel > 14) && (Channel > 14))) &&
- MAC_ADDR_EQUAL(&(Tab->BssEntry[i].Bssid), Bssid) &&
- (SSID_EQUAL
- (pSsid, SsidLen, Tab->BssEntry[i].Ssid,
- Tab->BssEntry[i].SsidLen)
- || (NdisEqualMemory(pSsid, ZeroSsid, SsidLen))
- ||
- (NdisEqualMemory
- (Tab->BssEntry[i].Ssid, ZeroSsid,
- Tab->BssEntry[i].SsidLen)))) {
- return i;
- }
- }
- return (unsigned long)BSS_NOT_FOUND;
-}
-
-unsigned long BssSsidTableSearchBySSID(struct rt_bss_table *Tab,
- u8 *pSsid, u8 SsidLen)
-{
- u8 i;
-
- for (i = 0; i < Tab->BssNr; i++) {
- if (SSID_EQUAL
- (pSsid, SsidLen, Tab->BssEntry[i].Ssid,
- Tab->BssEntry[i].SsidLen)) {
- return i;
- }
- }
- return (unsigned long)BSS_NOT_FOUND;
-}
-
-/* IRQL = DISPATCH_LEVEL */
-void BssTableDeleteEntry(struct rt_bss_table *Tab,
- u8 *pBssid, u8 Channel)
-{
- u8 i, j;
-
- for (i = 0; i < Tab->BssNr; i++) {
- if ((Tab->BssEntry[i].Channel == Channel) &&
- (MAC_ADDR_EQUAL(Tab->BssEntry[i].Bssid, pBssid))) {
- for (j = i; j < Tab->BssNr - 1; j++) {
- NdisMoveMemory(&(Tab->BssEntry[j]),
- &(Tab->BssEntry[j + 1]),
- sizeof(struct rt_bss_entry));
- }
- NdisZeroMemory(&(Tab->BssEntry[Tab->BssNr - 1]),
- sizeof(struct rt_bss_entry));
- Tab->BssNr -= 1;
- return;
- }
- }
-}
-
-/*
- ========================================================================
- Routine Description:
- Delete the Originator Entry in BAtable. Or decrease numAs Originator by 1 if needed.
-
- Arguments:
- // IRQL = DISPATCH_LEVEL
- ========================================================================
-*/
-void BATableDeleteORIEntry(struct rt_rtmp_adapter *pAd,
- struct rt_ba_ori_entry *pBAORIEntry)
-{
-
- if (pBAORIEntry->ORI_BA_Status != Originator_NONE) {
- NdisAcquireSpinLock(&pAd->BATabLock);
- if (pBAORIEntry->ORI_BA_Status == Originator_Done) {
- pAd->BATable.numAsOriginator -= 1;
- DBGPRINT(RT_DEBUG_TRACE,
- ("BATableDeleteORIEntry numAsOriginator= %ld\n",
- pAd->BATable.numAsRecipient));
- /* Erase Bitmap flag. */
- }
- pAd->MacTab.Content[pBAORIEntry->Wcid].TXBAbitmap &= (~(1 << (pBAORIEntry->TID))); /* If STA mode, erase flag here */
- pAd->MacTab.Content[pBAORIEntry->Wcid].BAOriWcidArray[pBAORIEntry->TID] = 0; /* If STA mode, erase flag here */
- pBAORIEntry->ORI_BA_Status = Originator_NONE;
- pBAORIEntry->Token = 1;
- /* Not clear Sequence here. */
- NdisReleaseSpinLock(&pAd->BATabLock);
- }
-}
-
-/*! \brief
- * \param
- * \return
- * \pre
- * \post
-
- IRQL = DISPATCH_LEVEL
-
- */
-void BssEntrySet(struct rt_rtmp_adapter *pAd, struct rt_bss_entry *pBss, u8 *pBssid, char Ssid[], u8 SsidLen, u8 BssType, u16 BeaconPeriod, struct rt_cf_parm * pCfParm, u16 AtimWin, u16 CapabilityInfo, u8 SupRate[], u8 SupRateLen, u8 ExtRate[], u8 ExtRateLen, struct rt_ht_capability_ie * pHtCapability, struct rt_add_ht_info_ie * pAddHtInfo, /* AP might use this additional ht info IE */
- u8 HtCapabilityLen,
- u8 AddHtInfoLen,
- u8 NewExtChanOffset,
- u8 Channel,
- char Rssi,
- IN LARGE_INTEGER TimeStamp,
- u8 CkipFlag,
- struct rt_edca_parm *pEdcaParm,
- struct rt_qos_capability_parm *pQosCapability,
- struct rt_qbss_load_parm *pQbssLoad,
- u16 LengthVIE, struct rt_ndis_802_11_variable_ies *pVIE)
-{
- COPY_MAC_ADDR(pBss->Bssid, pBssid);
- /* Default Hidden SSID to be TRUE, it will be turned to FALSE after coping SSID */
- pBss->Hidden = 1;
- if (SsidLen > 0) {
- /* For hidden SSID AP, it might send beacon with SSID len equal to 0 */
- /* Or send beacon /probe response with SSID len matching real SSID length, */
- /* but SSID is all zero. such as "00-00-00-00" with length 4. */
- /* We have to prevent this case overwrite correct table */
- if (NdisEqualMemory(Ssid, ZeroSsid, SsidLen) == 0) {
- NdisZeroMemory(pBss->Ssid, MAX_LEN_OF_SSID);
- NdisMoveMemory(pBss->Ssid, Ssid, SsidLen);
- pBss->SsidLen = SsidLen;
- pBss->Hidden = 0;
- }
- } else
- pBss->SsidLen = 0;
- pBss->BssType = BssType;
- pBss->BeaconPeriod = BeaconPeriod;
- if (BssType == BSS_INFRA) {
- if (pCfParm->bValid) {
- pBss->CfpCount = pCfParm->CfpCount;
- pBss->CfpPeriod = pCfParm->CfpPeriod;
- pBss->CfpMaxDuration = pCfParm->CfpMaxDuration;
- pBss->CfpDurRemaining = pCfParm->CfpDurRemaining;
- }
- } else {
- pBss->AtimWin = AtimWin;
- }
-
- pBss->CapabilityInfo = CapabilityInfo;
- /* The privacy bit indicate security is ON, it maight be WEP, TKIP or AES */
- /* Combine with AuthMode, they will decide the connection methods. */
- pBss->Privacy = CAP_IS_PRIVACY_ON(pBss->CapabilityInfo);
- ASSERT(SupRateLen <= MAX_LEN_OF_SUPPORTED_RATES);
- if (SupRateLen <= MAX_LEN_OF_SUPPORTED_RATES)
- NdisMoveMemory(pBss->SupRate, SupRate, SupRateLen);
- else
- NdisMoveMemory(pBss->SupRate, SupRate,
- MAX_LEN_OF_SUPPORTED_RATES);
- pBss->SupRateLen = SupRateLen;
- ASSERT(ExtRateLen <= MAX_LEN_OF_SUPPORTED_RATES);
- NdisMoveMemory(pBss->ExtRate, ExtRate, ExtRateLen);
- pBss->NewExtChanOffset = NewExtChanOffset;
- pBss->ExtRateLen = ExtRateLen;
- pBss->Channel = Channel;
- pBss->CentralChannel = Channel;
- pBss->Rssi = Rssi;
- /* Update CkipFlag. if not exists, the value is 0x0 */
- pBss->CkipFlag = CkipFlag;
-
- /* New for microsoft Fixed IEs */
- NdisMoveMemory(pBss->FixIEs.Timestamp, &TimeStamp, 8);
- pBss->FixIEs.BeaconInterval = BeaconPeriod;
- pBss->FixIEs.Capabilities = CapabilityInfo;
-
- /* New for microsoft Variable IEs */
- if (LengthVIE != 0) {
- pBss->VarIELen = LengthVIE;
- NdisMoveMemory(pBss->VarIEs, pVIE, pBss->VarIELen);
- } else {
- pBss->VarIELen = 0;
- }
-
- pBss->AddHtInfoLen = 0;
- pBss->HtCapabilityLen = 0;
- if (HtCapabilityLen > 0) {
- pBss->HtCapabilityLen = HtCapabilityLen;
- NdisMoveMemory(&pBss->HtCapability, pHtCapability,
- HtCapabilityLen);
- if (AddHtInfoLen > 0) {
- pBss->AddHtInfoLen = AddHtInfoLen;
- NdisMoveMemory(&pBss->AddHtInfo, pAddHtInfo,
- AddHtInfoLen);
-
- if ((pAddHtInfo->ControlChan > 2)
- && (pAddHtInfo->AddHtInfo.ExtChanOffset ==
- EXTCHA_BELOW)
- && (pHtCapability->HtCapInfo.ChannelWidth ==
- BW_40)) {
- pBss->CentralChannel =
- pAddHtInfo->ControlChan - 2;
- } else
- if ((pAddHtInfo->AddHtInfo.ExtChanOffset ==
- EXTCHA_ABOVE)
- && (pHtCapability->HtCapInfo.ChannelWidth ==
- BW_40)) {
- pBss->CentralChannel =
- pAddHtInfo->ControlChan + 2;
- }
- }
- }
-
- BssCipherParse(pBss);
-
- /* new for QOS */
- if (pEdcaParm)
- NdisMoveMemory(&pBss->EdcaParm, pEdcaParm, sizeof(struct rt_edca_parm));
- else
- pBss->EdcaParm.bValid = FALSE;
- if (pQosCapability)
- NdisMoveMemory(&pBss->QosCapability, pQosCapability,
- sizeof(struct rt_qos_capability_parm));
- else
- pBss->QosCapability.bValid = FALSE;
- if (pQbssLoad)
- NdisMoveMemory(&pBss->QbssLoad, pQbssLoad,
- sizeof(struct rt_qbss_load_parm));
- else
- pBss->QbssLoad.bValid = FALSE;
-
- {
- struct rt_eid * pEid;
- u16 Length = 0;
-
- NdisZeroMemory(&pBss->WpaIE.IE[0], MAX_CUSTOM_LEN);
- NdisZeroMemory(&pBss->RsnIE.IE[0], MAX_CUSTOM_LEN);
- pEid = (struct rt_eid *) pVIE;
- while ((Length + 2 + (u16)pEid->Len) <= LengthVIE) {
- switch (pEid->Eid) {
- case IE_WPA:
- if (NdisEqualMemory(pEid->Octet, WPA_OUI, 4)) {
- if ((pEid->Len + 2) > MAX_CUSTOM_LEN) {
- pBss->WpaIE.IELen = 0;
- break;
- }
- pBss->WpaIE.IELen = pEid->Len + 2;
- NdisMoveMemory(pBss->WpaIE.IE, pEid,
- pBss->WpaIE.IELen);
- }
- break;
- case IE_RSN:
- if (NdisEqualMemory
- (pEid->Octet + 2, RSN_OUI, 3)) {
- if ((pEid->Len + 2) > MAX_CUSTOM_LEN) {
- pBss->RsnIE.IELen = 0;
- break;
- }
- pBss->RsnIE.IELen = pEid->Len + 2;
- NdisMoveMemory(pBss->RsnIE.IE, pEid,
- pBss->RsnIE.IELen);
- }
- break;
- }
- Length = Length + 2 + (u16)pEid->Len; /* Eid[1] + Len[1]+ content[Len] */
- pEid = (struct rt_eid *) ((u8 *) pEid + 2 + pEid->Len);
- }
- }
-}
-
-/*!
- * \brief insert an entry into the bss table
- * \param p_tab The BSS table
- * \param Bssid BSSID
- * \param ssid SSID
- * \param ssid_len Length of SSID
- * \param bss_type
- * \param beacon_period
- * \param timestamp
- * \param p_cf
- * \param atim_win
- * \param cap
- * \param rates
- * \param rates_len
- * \param channel_idx
- * \return none
- * \pre
- * \post
- * \note If SSID is identical, the old entry will be replaced by the new one
-
- IRQL = DISPATCH_LEVEL
-
- */
-unsigned long BssTableSetEntry(struct rt_rtmp_adapter *pAd, struct rt_bss_table *Tab, u8 *pBssid, char Ssid[], u8 SsidLen, u8 BssType, u16 BeaconPeriod, struct rt_cf_parm * CfParm, u16 AtimWin, u16 CapabilityInfo, u8 SupRate[], u8 SupRateLen, u8 ExtRate[], u8 ExtRateLen, struct rt_ht_capability_ie * pHtCapability, struct rt_add_ht_info_ie * pAddHtInfo, /* AP might use this additional ht info IE */
- u8 HtCapabilityLen,
- u8 AddHtInfoLen,
- u8 NewExtChanOffset,
- u8 ChannelNo,
- char Rssi,
- IN LARGE_INTEGER TimeStamp,
- u8 CkipFlag,
- struct rt_edca_parm *pEdcaParm,
- struct rt_qos_capability_parm *pQosCapability,
- struct rt_qbss_load_parm *pQbssLoad,
- u16 LengthVIE, struct rt_ndis_802_11_variable_ies *pVIE)
-{
- unsigned long Idx;
-
- Idx =
- BssTableSearchWithSSID(Tab, pBssid, (u8 *) Ssid, SsidLen,
- ChannelNo);
- if (Idx == BSS_NOT_FOUND) {
- if (Tab->BssNr >= MAX_LEN_OF_BSS_TABLE) {
- /* */
- /* It may happen when BSS Table was full. */
- /* The desired AP will not be added into BSS Table */
- /* In this case, if we found the desired AP then overwrite BSS Table. */
- /* */
- if (!OPSTATUS_TEST_FLAG
- (pAd, fOP_STATUS_MEDIA_STATE_CONNECTED)) {
- if (MAC_ADDR_EQUAL(pAd->MlmeAux.Bssid, pBssid)
- || SSID_EQUAL(pAd->MlmeAux.Ssid,
- pAd->MlmeAux.SsidLen, Ssid,
- SsidLen)) {
- Idx = Tab->BssOverlapNr;
- BssEntrySet(pAd, &Tab->BssEntry[Idx],
- pBssid, Ssid, SsidLen,
- BssType, BeaconPeriod,
- CfParm, AtimWin,
- CapabilityInfo, SupRate,
- SupRateLen, ExtRate,
- ExtRateLen, pHtCapability,
- pAddHtInfo, HtCapabilityLen,
- AddHtInfoLen,
- NewExtChanOffset, ChannelNo,
- Rssi, TimeStamp, CkipFlag,
- pEdcaParm, pQosCapability,
- pQbssLoad, LengthVIE, pVIE);
- Tab->BssOverlapNr =
- (Tab->BssOverlapNr++) %
- MAX_LEN_OF_BSS_TABLE;
- }
- return Idx;
- } else {
- return BSS_NOT_FOUND;
- }
- }
- Idx = Tab->BssNr;
- BssEntrySet(pAd, &Tab->BssEntry[Idx], pBssid, Ssid, SsidLen,
- BssType, BeaconPeriod, CfParm, AtimWin,
- CapabilityInfo, SupRate, SupRateLen, ExtRate,
- ExtRateLen, pHtCapability, pAddHtInfo,
- HtCapabilityLen, AddHtInfoLen, NewExtChanOffset,
- ChannelNo, Rssi, TimeStamp, CkipFlag, pEdcaParm,
- pQosCapability, pQbssLoad, LengthVIE, pVIE);
- Tab->BssNr++;
- } else {
- /* avoid Hidden SSID form beacon to overwirite correct SSID from probe response */
- if ((SSID_EQUAL
- (Ssid, SsidLen, Tab->BssEntry[Idx].Ssid,
- Tab->BssEntry[Idx].SsidLen))
- ||
- (NdisEqualMemory
- (Tab->BssEntry[Idx].Ssid, ZeroSsid,
- Tab->BssEntry[Idx].SsidLen))) {
- BssEntrySet(pAd, &Tab->BssEntry[Idx], pBssid, Ssid,
- SsidLen, BssType, BeaconPeriod, CfParm,
- AtimWin, CapabilityInfo, SupRate,
- SupRateLen, ExtRate, ExtRateLen,
- pHtCapability, pAddHtInfo, HtCapabilityLen,
- AddHtInfoLen, NewExtChanOffset, ChannelNo,
- Rssi, TimeStamp, CkipFlag, pEdcaParm,
- pQosCapability, pQbssLoad, LengthVIE, pVIE);
- }
- }
-
- return Idx;
-}
-
-/* IRQL = DISPATCH_LEVEL */
-void BssTableSsidSort(struct rt_rtmp_adapter *pAd,
- struct rt_bss_table *OutTab, char Ssid[], u8 SsidLen)
-{
- int i;
- BssTableInit(OutTab);
-
- for (i = 0; i < pAd->ScanTab.BssNr; i++) {
- struct rt_bss_entry *pInBss = &pAd->ScanTab.BssEntry[i];
- BOOLEAN bIsHiddenApIncluded = FALSE;
-
- if (((pAd->CommonCfg.bIEEE80211H == 1) &&
- (pAd->MlmeAux.Channel > 14) &&
- RadarChannelCheck(pAd, pInBss->Channel))
- ) {
- if (pInBss->Hidden)
- bIsHiddenApIncluded = TRUE;
- }
-
- if ((pInBss->BssType == pAd->StaCfg.BssType) &&
- (SSID_EQUAL(Ssid, SsidLen, pInBss->Ssid, pInBss->SsidLen)
- || bIsHiddenApIncluded)) {
- struct rt_bss_entry *pOutBss = &OutTab->BssEntry[OutTab->BssNr];
-
- /* 2.4G/5G N only mode */
- if ((pInBss->HtCapabilityLen == 0) &&
- ((pAd->CommonCfg.PhyMode == PHY_11N_2_4G)
- || (pAd->CommonCfg.PhyMode == PHY_11N_5G))) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("STA is in N-only Mode, this AP don't have Ht capability in Beacon.\n"));
- continue;
- }
- /* New for WPA2 */
- /* Check the Authmode first */
- if (pAd->StaCfg.AuthMode >= Ndis802_11AuthModeWPA) {
- /* Check AuthMode and AuthModeAux for matching, in case AP support dual-mode */
- if ((pAd->StaCfg.AuthMode != pInBss->AuthMode)
- && (pAd->StaCfg.AuthMode !=
- pInBss->AuthModeAux))
- /* None matched */
- continue;
-
- /* Check cipher suite, AP must have more secured cipher than station setting */
- if ((pAd->StaCfg.AuthMode ==
- Ndis802_11AuthModeWPA)
- || (pAd->StaCfg.AuthMode ==
- Ndis802_11AuthModeWPAPSK)) {
- /* If it's not mixed mode, we should only let BSS pass with the same encryption */
- if (pInBss->WPA.bMixMode == FALSE)
- if (pAd->StaCfg.WepStatus !=
- pInBss->WPA.GroupCipher)
- continue;
-
- /* check group cipher */
- if ((pAd->StaCfg.WepStatus <
- pInBss->WPA.GroupCipher)
- && (pInBss->WPA.GroupCipher !=
- Ndis802_11GroupWEP40Enabled)
- && (pInBss->WPA.GroupCipher !=
- Ndis802_11GroupWEP104Enabled))
- continue;
-
- /* check pairwise cipher, skip if none matched */
- /* If profile set to AES, let it pass without question. */
- /* If profile set to TKIP, we must find one mateched */
- if ((pAd->StaCfg.WepStatus ==
- Ndis802_11Encryption2Enabled)
- && (pAd->StaCfg.WepStatus !=
- pInBss->WPA.PairCipher)
- && (pAd->StaCfg.WepStatus !=
- pInBss->WPA.PairCipherAux))
- continue;
- } else
- if ((pAd->StaCfg.AuthMode ==
- Ndis802_11AuthModeWPA2)
- || (pAd->StaCfg.AuthMode ==
- Ndis802_11AuthModeWPA2PSK)) {
- /* If it's not mixed mode, we should only let BSS pass with the same encryption */
- if (pInBss->WPA2.bMixMode == FALSE)
- if (pAd->StaCfg.WepStatus !=
- pInBss->WPA2.GroupCipher)
- continue;
-
- /* check group cipher */
- if ((pAd->StaCfg.WepStatus <
- pInBss->WPA.GroupCipher)
- && (pInBss->WPA2.GroupCipher !=
- Ndis802_11GroupWEP40Enabled)
- && (pInBss->WPA2.GroupCipher !=
- Ndis802_11GroupWEP104Enabled))
- continue;
-
- /* check pairwise cipher, skip if none matched */
- /* If profile set to AES, let it pass without question. */
- /* If profile set to TKIP, we must find one mateched */
- if ((pAd->StaCfg.WepStatus ==
- Ndis802_11Encryption2Enabled)
- && (pAd->StaCfg.WepStatus !=
- pInBss->WPA2.PairCipher)
- && (pAd->StaCfg.WepStatus !=
- pInBss->WPA2.PairCipherAux))
- continue;
- }
- }
- /* Bss Type matched, SSID matched. */
- /* We will check wepstatus for qualification Bss */
- else if (pAd->StaCfg.WepStatus != pInBss->WepStatus) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("StaCfg.WepStatus=%d, while pInBss->WepStatus=%d\n",
- pAd->StaCfg.WepStatus,
- pInBss->WepStatus));
- /* */
- /* For the SESv2 case, we will not qualify WepStatus. */
- /* */
- if (!pInBss->bSES)
- continue;
- }
- /* Since the AP is using hidden SSID, and we are trying to connect to ANY */
- /* It definitely will fail. So, skip it. */
- /* CCX also require not even try to connect it! */
- if (SsidLen == 0)
- continue;
-
- /* If both station and AP use 40MHz, still need to check if the 40MHZ band's legality in my country region */
- /* If this 40MHz wideband is not allowed in my country list, use bandwidth 20MHZ instead, */
- if ((pInBss->CentralChannel != pInBss->Channel) &&
- (pAd->CommonCfg.RegTransmitSetting.field.BW ==
- BW_40)) {
- if (RTMPCheckChannel
- (pAd, pInBss->CentralChannel,
- pInBss->Channel) == FALSE) {
- pAd->CommonCfg.RegTransmitSetting.field.
- BW = BW_20;
- SetCommonHT(pAd);
- pAd->CommonCfg.RegTransmitSetting.field.
- BW = BW_40;
- } else {
- if (pAd->CommonCfg.DesiredHtPhy.
- ChannelWidth == BAND_WIDTH_20) {
- SetCommonHT(pAd);
- }
- }
- }
- /* copy matching BSS from InTab to OutTab */
- NdisMoveMemory(pOutBss, pInBss, sizeof(struct rt_bss_entry));
-
- OutTab->BssNr++;
- } else if ((pInBss->BssType == pAd->StaCfg.BssType)
- && (SsidLen == 0)) {
- struct rt_bss_entry *pOutBss = &OutTab->BssEntry[OutTab->BssNr];
-
- /* 2.4G/5G N only mode */
- if ((pInBss->HtCapabilityLen == 0) &&
- ((pAd->CommonCfg.PhyMode == PHY_11N_2_4G)
- || (pAd->CommonCfg.PhyMode == PHY_11N_5G))) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("STA is in N-only Mode, this AP don't have Ht capability in Beacon.\n"));
- continue;
- }
- /* New for WPA2 */
- /* Check the Authmode first */
- if (pAd->StaCfg.AuthMode >= Ndis802_11AuthModeWPA) {
- /* Check AuthMode and AuthModeAux for matching, in case AP support dual-mode */
- if ((pAd->StaCfg.AuthMode != pInBss->AuthMode)
- && (pAd->StaCfg.AuthMode !=
- pInBss->AuthModeAux))
- /* None matched */
- continue;
-
- /* Check cipher suite, AP must have more secured cipher than station setting */
- if ((pAd->StaCfg.AuthMode ==
- Ndis802_11AuthModeWPA)
- || (pAd->StaCfg.AuthMode ==
- Ndis802_11AuthModeWPAPSK)) {
- /* If it's not mixed mode, we should only let BSS pass with the same encryption */
- if (pInBss->WPA.bMixMode == FALSE)
- if (pAd->StaCfg.WepStatus !=
- pInBss->WPA.GroupCipher)
- continue;
-
- /* check group cipher */
- if (pAd->StaCfg.WepStatus <
- pInBss->WPA.GroupCipher)
- continue;
-
- /* check pairwise cipher, skip if none matched */
- /* If profile set to AES, let it pass without question. */
- /* If profile set to TKIP, we must find one mateched */
- if ((pAd->StaCfg.WepStatus ==
- Ndis802_11Encryption2Enabled)
- && (pAd->StaCfg.WepStatus !=
- pInBss->WPA.PairCipher)
- && (pAd->StaCfg.WepStatus !=
- pInBss->WPA.PairCipherAux))
- continue;
- } else
- if ((pAd->StaCfg.AuthMode ==
- Ndis802_11AuthModeWPA2)
- || (pAd->StaCfg.AuthMode ==
- Ndis802_11AuthModeWPA2PSK)) {
- /* If it's not mixed mode, we should only let BSS pass with the same encryption */
- if (pInBss->WPA2.bMixMode == FALSE)
- if (pAd->StaCfg.WepStatus !=
- pInBss->WPA2.GroupCipher)
- continue;
-
- /* check group cipher */
- if (pAd->StaCfg.WepStatus <
- pInBss->WPA2.GroupCipher)
- continue;
-
- /* check pairwise cipher, skip if none matched */
- /* If profile set to AES, let it pass without question. */
- /* If profile set to TKIP, we must find one mateched */
- if ((pAd->StaCfg.WepStatus ==
- Ndis802_11Encryption2Enabled)
- && (pAd->StaCfg.WepStatus !=
- pInBss->WPA2.PairCipher)
- && (pAd->StaCfg.WepStatus !=
- pInBss->WPA2.PairCipherAux))
- continue;
- }
- }
- /* Bss Type matched, SSID matched. */
- /* We will check wepstatus for qualification Bss */
- else if (pAd->StaCfg.WepStatus != pInBss->WepStatus)
- continue;
-
- /* If both station and AP use 40MHz, still need to check if the 40MHZ band's legality in my country region */
- /* If this 40MHz wideband is not allowed in my country list, use bandwidth 20MHZ instead, */
- if ((pInBss->CentralChannel != pInBss->Channel) &&
- (pAd->CommonCfg.RegTransmitSetting.field.BW ==
- BW_40)) {
- if (RTMPCheckChannel
- (pAd, pInBss->CentralChannel,
- pInBss->Channel) == FALSE) {
- pAd->CommonCfg.RegTransmitSetting.field.
- BW = BW_20;
- SetCommonHT(pAd);
- pAd->CommonCfg.RegTransmitSetting.field.
- BW = BW_40;
- }
- }
- /* copy matching BSS from InTab to OutTab */
- NdisMoveMemory(pOutBss, pInBss, sizeof(struct rt_bss_entry));
-
- OutTab->BssNr++;
- }
-
- if (OutTab->BssNr >= MAX_LEN_OF_BSS_TABLE)
- break;
- }
-
- BssTableSortByRssi(OutTab);
-}
-
-/* IRQL = DISPATCH_LEVEL */
-void BssTableSortByRssi(struct rt_bss_table *OutTab)
-{
- int i, j;
- struct rt_bss_entry TmpBss;
-
- for (i = 0; i < OutTab->BssNr - 1; i++) {
- for (j = i + 1; j < OutTab->BssNr; j++) {
- if (OutTab->BssEntry[j].Rssi > OutTab->BssEntry[i].Rssi) {
- NdisMoveMemory(&TmpBss, &OutTab->BssEntry[j],
- sizeof(struct rt_bss_entry));
- NdisMoveMemory(&OutTab->BssEntry[j],
- &OutTab->BssEntry[i],
- sizeof(struct rt_bss_entry));
- NdisMoveMemory(&OutTab->BssEntry[i], &TmpBss,
- sizeof(struct rt_bss_entry));
- }
- }
- }
-}
-
-void BssCipherParse(struct rt_bss_entry *pBss)
-{
- struct rt_eid * pEid;
- u8 *pTmp;
- struct rt_rsn_ie_header * pRsnHeader;
- struct rt_cipher_suite_struct * pCipher;
- struct rt_akm_suite * pAKM;
- u16 Count;
- int Length;
- NDIS_802_11_ENCRYPTION_STATUS TmpCipher;
-
- /* */
- /* WepStatus will be reset later, if AP announce TKIP or AES on the beacon frame. */
- /* */
- if (pBss->Privacy) {
- pBss->WepStatus = Ndis802_11WEPEnabled;
- } else {
- pBss->WepStatus = Ndis802_11WEPDisabled;
- }
- /* Set default to disable & open authentication before parsing variable IE */
- pBss->AuthMode = Ndis802_11AuthModeOpen;
- pBss->AuthModeAux = Ndis802_11AuthModeOpen;
-
- /* Init WPA setting */
- pBss->WPA.PairCipher = Ndis802_11WEPDisabled;
- pBss->WPA.PairCipherAux = Ndis802_11WEPDisabled;
- pBss->WPA.GroupCipher = Ndis802_11WEPDisabled;
- pBss->WPA.RsnCapability = 0;
- pBss->WPA.bMixMode = FALSE;
-
- /* Init WPA2 setting */
- pBss->WPA2.PairCipher = Ndis802_11WEPDisabled;
- pBss->WPA2.PairCipherAux = Ndis802_11WEPDisabled;
- pBss->WPA2.GroupCipher = Ndis802_11WEPDisabled;
- pBss->WPA2.RsnCapability = 0;
- pBss->WPA2.bMixMode = FALSE;
-
- Length = (int)pBss->VarIELen;
-
- while (Length > 0) {
- /* Parse cipher suite base on WPA1 & WPA2, they should be parsed differently */
- pTmp = ((u8 *)pBss->VarIEs) + pBss->VarIELen - Length;
- pEid = (struct rt_eid *) pTmp;
- switch (pEid->Eid) {
- case IE_WPA:
- if (NdisEqualMemory(pEid->Octet, SES_OUI, 3)
- && (pEid->Len == 7)) {
- pBss->bSES = TRUE;
- break;
- } else if (NdisEqualMemory(pEid->Octet, WPA_OUI, 4) !=
- 1) {
- /* if unsupported vendor specific IE */
- break;
- }
- /* Skip OUI, version, and multicast suite */
- /* This part should be improved in the future when AP supported multiple cipher suite. */
- /* For now, it's OK since almost all APs have fixed cipher suite supported. */
- /* pTmp = (u8 *)pEid->Octet; */
- pTmp += 11;
-
- /* Cipher Suite Selectors from Spec P802.11i/D3.2 P26. */
- /* Value Meaning */
- /* 0 None */
- /* 1 WEP-40 */
- /* 2 Tkip */
- /* 3 WRAP */
- /* 4 AES */
- /* 5 WEP-104 */
- /* Parse group cipher */
- switch (*pTmp) {
- case 1:
- pBss->WPA.GroupCipher =
- Ndis802_11GroupWEP40Enabled;
- break;
- case 5:
- pBss->WPA.GroupCipher =
- Ndis802_11GroupWEP104Enabled;
- break;
- case 2:
- pBss->WPA.GroupCipher =
- Ndis802_11Encryption2Enabled;
- break;
- case 4:
- pBss->WPA.GroupCipher =
- Ndis802_11Encryption3Enabled;
- break;
- default:
- break;
- }
- /* number of unicast suite */
- pTmp += 1;
-
- /* skip all unicast cipher suites */
- /*Count = *(u16 *)pTmp; */
- Count = (pTmp[1] << 8) + pTmp[0];
- pTmp += sizeof(u16);
-
- /* Parsing all unicast cipher suite */
- while (Count > 0) {
- /* Skip OUI */
- pTmp += 3;
- TmpCipher = Ndis802_11WEPDisabled;
- switch (*pTmp) {
- case 1:
- case 5: /* Although WEP is not allowed in WPA related auth mode, we parse it anyway */
- TmpCipher =
- Ndis802_11Encryption1Enabled;
- break;
- case 2:
- TmpCipher =
- Ndis802_11Encryption2Enabled;
- break;
- case 4:
- TmpCipher =
- Ndis802_11Encryption3Enabled;
- break;
- default:
- break;
- }
- if (TmpCipher > pBss->WPA.PairCipher) {
- /* Move the lower cipher suite to PairCipherAux */
- pBss->WPA.PairCipherAux =
- pBss->WPA.PairCipher;
- pBss->WPA.PairCipher = TmpCipher;
- } else {
- pBss->WPA.PairCipherAux = TmpCipher;
- }
- pTmp++;
- Count--;
- }
-
- /* 4. get AKM suite counts */
- /*Count = *(u16 *)pTmp; */
- Count = (pTmp[1] << 8) + pTmp[0];
- pTmp += sizeof(u16);
- pTmp += 3;
-
- switch (*pTmp) {
- case 1:
- /* Set AP support WPA-enterprise mode */
- if (pBss->AuthMode == Ndis802_11AuthModeOpen)
- pBss->AuthMode = Ndis802_11AuthModeWPA;
- else
- pBss->AuthModeAux =
- Ndis802_11AuthModeWPA;
- break;
- case 2:
- /* Set AP support WPA-PSK mode */
- if (pBss->AuthMode == Ndis802_11AuthModeOpen)
- pBss->AuthMode =
- Ndis802_11AuthModeWPAPSK;
- else
- pBss->AuthModeAux =
- Ndis802_11AuthModeWPAPSK;
- break;
- default:
- break;
- }
- pTmp += 1;
-
- /* Fixed for WPA-None */
- if (pBss->BssType == BSS_ADHOC) {
- pBss->AuthMode = Ndis802_11AuthModeWPANone;
- pBss->AuthModeAux = Ndis802_11AuthModeWPANone;
- pBss->WepStatus = pBss->WPA.GroupCipher;
- /* Patched bugs for old driver */
- if (pBss->WPA.PairCipherAux ==
- Ndis802_11WEPDisabled)
- pBss->WPA.PairCipherAux =
- pBss->WPA.GroupCipher;
- } else
- pBss->WepStatus = pBss->WPA.PairCipher;
-
- /* Check the Pair & Group, if different, turn on mixed mode flag */
- if (pBss->WPA.GroupCipher != pBss->WPA.PairCipher)
- pBss->WPA.bMixMode = TRUE;
-
- break;
-
- case IE_RSN:
- pRsnHeader = (struct rt_rsn_ie_header *) pTmp;
-
- /* 0. Version must be 1 */
- if (le2cpu16(pRsnHeader->Version) != 1)
- break;
- pTmp += sizeof(struct rt_rsn_ie_header);
-
- /* 1. Check group cipher */
- pCipher = (struct rt_cipher_suite_struct *) pTmp;
- if (!RTMPEqualMemory(pTmp, RSN_OUI, 3))
- break;
-
- /* Parse group cipher */
- switch (pCipher->Type) {
- case 1:
- pBss->WPA2.GroupCipher =
- Ndis802_11GroupWEP40Enabled;
- break;
- case 5:
- pBss->WPA2.GroupCipher =
- Ndis802_11GroupWEP104Enabled;
- break;
- case 2:
- pBss->WPA2.GroupCipher =
- Ndis802_11Encryption2Enabled;
- break;
- case 4:
- pBss->WPA2.GroupCipher =
- Ndis802_11Encryption3Enabled;
- break;
- default:
- break;
- }
- /* set to correct offset for next parsing */
- pTmp += sizeof(struct rt_cipher_suite_struct);
-
- /* 2. Get pairwise cipher counts */
- /*Count = *(u16 *)pTmp; */
- Count = (pTmp[1] << 8) + pTmp[0];
- pTmp += sizeof(u16);
-
- /* 3. Get pairwise cipher */
- /* Parsing all unicast cipher suite */
- while (Count > 0) {
- /* Skip OUI */
- pCipher = (struct rt_cipher_suite_struct *) pTmp;
- TmpCipher = Ndis802_11WEPDisabled;
- switch (pCipher->Type) {
- case 1:
- case 5: /* Although WEP is not allowed in WPA related auth mode, we parse it anyway */
- TmpCipher =
- Ndis802_11Encryption1Enabled;
- break;
- case 2:
- TmpCipher =
- Ndis802_11Encryption2Enabled;
- break;
- case 4:
- TmpCipher =
- Ndis802_11Encryption3Enabled;
- break;
- default:
- break;
- }
- if (TmpCipher > pBss->WPA2.PairCipher) {
- /* Move the lower cipher suite to PairCipherAux */
- pBss->WPA2.PairCipherAux =
- pBss->WPA2.PairCipher;
- pBss->WPA2.PairCipher = TmpCipher;
- } else {
- pBss->WPA2.PairCipherAux = TmpCipher;
- }
- pTmp += sizeof(struct rt_cipher_suite_struct);
- Count--;
- }
-
- /* 4. get AKM suite counts */
- /*Count = *(u16 *)pTmp; */
- Count = (pTmp[1] << 8) + pTmp[0];
- pTmp += sizeof(u16);
-
- /* 5. Get AKM ciphers */
- /* Parsing all AKM ciphers */
- while (Count > 0) {
- pAKM = (struct rt_akm_suite *) pTmp;
- if (!RTMPEqualMemory(pTmp, RSN_OUI, 3))
- break;
-
- switch (pAKM->Type) {
- case 1:
- /* Set AP support WPA-enterprise mode */
- if (pBss->AuthMode ==
- Ndis802_11AuthModeOpen)
- pBss->AuthMode =
- Ndis802_11AuthModeWPA2;
- else
- pBss->AuthModeAux =
- Ndis802_11AuthModeWPA2;
- break;
- case 2:
- /* Set AP support WPA-PSK mode */
- if (pBss->AuthMode ==
- Ndis802_11AuthModeOpen)
- pBss->AuthMode =
- Ndis802_11AuthModeWPA2PSK;
- else
- pBss->AuthModeAux =
- Ndis802_11AuthModeWPA2PSK;
- break;
- default:
- if (pBss->AuthMode ==
- Ndis802_11AuthModeOpen)
- pBss->AuthMode =
- Ndis802_11AuthModeMax;
- else
- pBss->AuthModeAux =
- Ndis802_11AuthModeMax;
- break;
- }
- pTmp += (Count * sizeof(struct rt_akm_suite));
- Count--;
- }
-
- /* Fixed for WPA-None */
- if (pBss->BssType == BSS_ADHOC) {
- pBss->AuthMode = Ndis802_11AuthModeWPANone;
- pBss->AuthModeAux = Ndis802_11AuthModeWPANone;
- pBss->WPA.PairCipherAux =
- pBss->WPA2.PairCipherAux;
- pBss->WPA.GroupCipher = pBss->WPA2.GroupCipher;
- pBss->WepStatus = pBss->WPA.GroupCipher;
- /* Patched bugs for old driver */
- if (pBss->WPA.PairCipherAux ==
- Ndis802_11WEPDisabled)
- pBss->WPA.PairCipherAux =
- pBss->WPA.GroupCipher;
- }
- pBss->WepStatus = pBss->WPA2.PairCipher;
-
- /* 6. Get RSN capability */
- /*pBss->WPA2.RsnCapability = *(u16 *)pTmp; */
- pBss->WPA2.RsnCapability = (pTmp[1] << 8) + pTmp[0];
- pTmp += sizeof(u16);
-
- /* Check the Pair & Group, if different, turn on mixed mode flag */
- if (pBss->WPA2.GroupCipher != pBss->WPA2.PairCipher)
- pBss->WPA2.bMixMode = TRUE;
-
- break;
- default:
- break;
- }
- Length -= (pEid->Len + 2);
- }
-}
-
-/* =========================================================================================== */
-/* mac_table.c */
-/* =========================================================================================== */
-
-/*! \brief generates a random mac address value for IBSS BSSID
- * \param Addr the bssid location
- * \return none
- * \pre
- * \post
- */
-void MacAddrRandomBssid(struct rt_rtmp_adapter *pAd, u8 *pAddr)
-{
- int i;
-
- for (i = 0; i < MAC_ADDR_LEN; i++) {
- pAddr[i] = RandomByte(pAd);
- }
-
- pAddr[0] = (pAddr[0] & 0xfe) | 0x02; /* the first 2 bits must be 01xxxxxxxx */
-}
-
-/*! \brief init the management mac frame header
- * \param p_hdr mac header
- * \param subtype subtype of the frame
- * \param p_ds destination address, don't care if it is a broadcast address
- * \return none
- * \pre the station has the following information in the pAd->StaCfg
- * - bssid
- * - station address
- * \post
- * \note this function initializes the following field
-
- IRQL = PASSIVE_LEVEL
- IRQL = DISPATCH_LEVEL
-
- */
-void MgtMacHeaderInit(struct rt_rtmp_adapter *pAd,
- struct rt_header_802_11 * pHdr80211,
- u8 SubType,
- u8 ToDs, u8 *pDA, u8 *pBssid)
-{
- NdisZeroMemory(pHdr80211, sizeof(struct rt_header_802_11));
-
- pHdr80211->FC.Type = BTYPE_MGMT;
- pHdr80211->FC.SubType = SubType;
-/* if (SubType == SUBTYPE_ACK) // sample, no use, it will conflict with ACTION frame sub type */
-/* pHdr80211->FC.Type = BTYPE_CNTL; */
- pHdr80211->FC.ToDs = ToDs;
- COPY_MAC_ADDR(pHdr80211->Addr1, pDA);
- COPY_MAC_ADDR(pHdr80211->Addr2, pAd->CurrentAddress);
- COPY_MAC_ADDR(pHdr80211->Addr3, pBssid);
-}
-
-/* =========================================================================================== */
-/* mem_mgmt.c */
-/* =========================================================================================== */
-
-/*!***************************************************************************
- * This routine build an outgoing frame, and fill all information specified
- * in argument list to the frame body. The actual frame size is the summation
- * of all arguments.
- * input params:
- * Buffer - pointer to a pre-allocated memory segment
- * args - a list of <int arg_size, arg> pairs.
- * NOTE NOTE NOTE! the last argument must be NULL, otherwise this
- * function will FAIL!
- * return:
- * Size of the buffer
- * usage:
- * MakeOutgoingFrame(Buffer, output_length, 2, &fc, 2, &dur, 6, p_addr1, 6,p_addr2, END_OF_ARGS);
-
- IRQL = PASSIVE_LEVEL
- IRQL = DISPATCH_LEVEL
-
- ****************************************************************************/
-unsigned long MakeOutgoingFrame(u8 * Buffer, unsigned long * FrameLen, ...)
-{
- u8 *p;
- int leng;
- unsigned long TotLeng;
- va_list Args;
-
- /* calculates the total length */
- TotLeng = 0;
- va_start(Args, FrameLen);
- do {
- leng = va_arg(Args, int);
- if (leng == END_OF_ARGS) {
- break;
- }
- p = va_arg(Args, void *);
- NdisMoveMemory(&Buffer[TotLeng], p, leng);
- TotLeng = TotLeng + leng;
- } while (TRUE);
-
- va_end(Args); /* clean up */
- *FrameLen = TotLeng;
- return TotLeng;
-}
-
-/* =========================================================================================== */
-/* mlme_queue.c */
-/* =========================================================================================== */
-
-/*! \brief Initialize The MLME Queue, used by MLME Functions
- * \param *Queue The MLME Queue
- * \return Always Return NDIS_STATE_SUCCESS in this implementation
- * \pre
- * \post
- * \note Because this is done only once (at the init stage), no need to be locked
-
- IRQL = PASSIVE_LEVEL
-
- */
-int MlmeQueueInit(struct rt_mlme_queue *Queue)
-{
- int i;
-
- NdisAllocateSpinLock(&Queue->Lock);
-
- Queue->Num = 0;
- Queue->Head = 0;
- Queue->Tail = 0;
-
- for (i = 0; i < MAX_LEN_OF_MLME_QUEUE; i++) {
- Queue->Entry[i].Occupied = FALSE;
- Queue->Entry[i].MsgLen = 0;
- NdisZeroMemory(Queue->Entry[i].Msg, MGMT_DMA_BUFFER_SIZE);
- }
-
- return NDIS_STATUS_SUCCESS;
-}
-
-/*! \brief Enqueue a message for other threads, if they want to send messages to MLME thread
- * \param *Queue The MLME Queue
- * \param Machine The State Machine Id
- * \param MsgType The Message Type
- * \param MsgLen The Message length
- * \param *Msg The message pointer
- * \return TRUE if enqueue is successful, FALSE if the queue is full
- * \pre
- * \post
- * \note The message has to be initialized
-
- IRQL = PASSIVE_LEVEL
- IRQL = DISPATCH_LEVEL
-
- */
-BOOLEAN MlmeEnqueue(struct rt_rtmp_adapter *pAd,
- unsigned long Machine,
- unsigned long MsgType, unsigned long MsgLen, void * Msg)
-{
- int Tail;
- struct rt_mlme_queue *Queue = (struct rt_mlme_queue *)& pAd->Mlme.Queue;
-
- /* Do nothing if the driver is starting halt state. */
- /* This might happen when timer already been fired before cancel timer with mlmehalt */
- if (RTMP_TEST_FLAG
- (pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS | fRTMP_ADAPTER_NIC_NOT_EXIST))
- return FALSE;
-
- /* First check the size, it MUST not exceed the mlme queue size */
- if (MsgLen > MGMT_DMA_BUFFER_SIZE) {
- DBGPRINT_ERR("MlmeEnqueue: msg too large, size = %ld \n", MsgLen);
- return FALSE;
- }
-
- if (MlmeQueueFull(Queue)) {
- return FALSE;
- }
-
- NdisAcquireSpinLock(&(Queue->Lock));
- Tail = Queue->Tail;
- Queue->Tail++;
- Queue->Num++;
- if (Queue->Tail == MAX_LEN_OF_MLME_QUEUE) {
- Queue->Tail = 0;
- }
-
- Queue->Entry[Tail].Wcid = RESERVED_WCID;
- Queue->Entry[Tail].Occupied = TRUE;
- Queue->Entry[Tail].Machine = Machine;
- Queue->Entry[Tail].MsgType = MsgType;
- Queue->Entry[Tail].MsgLen = MsgLen;
-
- if (Msg != NULL) {
- NdisMoveMemory(Queue->Entry[Tail].Msg, Msg, MsgLen);
- }
-
- NdisReleaseSpinLock(&(Queue->Lock));
- return TRUE;
-}
-
-/*! \brief This function is used when Recv gets a MLME message
- * \param *Queue The MLME Queue
- * \param TimeStampHigh The upper 32 bit of timestamp
- * \param TimeStampLow The lower 32 bit of timestamp
- * \param Rssi The receiving RSSI strength
- * \param MsgLen The length of the message
- * \param *Msg The message pointer
- * \return TRUE if everything ok, FALSE otherwise (like Queue Full)
- * \pre
- * \post
-
- IRQL = DISPATCH_LEVEL
-
- */
-BOOLEAN MlmeEnqueueForRecv(struct rt_rtmp_adapter *pAd,
- unsigned long Wcid,
- unsigned long TimeStampHigh,
- unsigned long TimeStampLow,
- u8 Rssi0,
- u8 Rssi1,
- u8 Rssi2,
- unsigned long MsgLen, void * Msg, u8 Signal)
-{
- int Tail, Machine;
- struct rt_frame_802_11 * pFrame = (struct rt_frame_802_11 *) Msg;
- int MsgType;
- struct rt_mlme_queue *Queue = (struct rt_mlme_queue *)& pAd->Mlme.Queue;
-
- /* Do nothing if the driver is starting halt state. */
- /* This might happen when timer already been fired before cancel timer with mlmehalt */
- if (RTMP_TEST_FLAG
- (pAd,
- fRTMP_ADAPTER_HALT_IN_PROGRESS | fRTMP_ADAPTER_NIC_NOT_EXIST)) {
- DBGPRINT_ERR("MlmeEnqueueForRecv: fRTMP_ADAPTER_HALT_IN_PROGRESS\n");
- return FALSE;
- }
- /* First check the size, it MUST not exceed the mlme queue size */
- if (MsgLen > MGMT_DMA_BUFFER_SIZE) {
- DBGPRINT_ERR("MlmeEnqueueForRecv: frame too large, size = %ld \n", MsgLen);
- return FALSE;
- }
-
- if (MlmeQueueFull(Queue)) {
- return FALSE;
- }
-
- {
- if (!MsgTypeSubst(pAd, pFrame, &Machine, &MsgType)) {
- DBGPRINT_ERR("MlmeEnqueueForRecv: un-recongnized mgmt->subtype=%d\n", pFrame->Hdr.FC.SubType);
- return FALSE;
- }
- }
-
- /* OK, we got all the informations, it is time to put things into queue */
- NdisAcquireSpinLock(&(Queue->Lock));
- Tail = Queue->Tail;
- Queue->Tail++;
- Queue->Num++;
- if (Queue->Tail == MAX_LEN_OF_MLME_QUEUE) {
- Queue->Tail = 0;
- }
- Queue->Entry[Tail].Occupied = TRUE;
- Queue->Entry[Tail].Machine = Machine;
- Queue->Entry[Tail].MsgType = MsgType;
- Queue->Entry[Tail].MsgLen = MsgLen;
- Queue->Entry[Tail].TimeStamp.u.LowPart = TimeStampLow;
- Queue->Entry[Tail].TimeStamp.u.HighPart = TimeStampHigh;
- Queue->Entry[Tail].Rssi0 = Rssi0;
- Queue->Entry[Tail].Rssi1 = Rssi1;
- Queue->Entry[Tail].Rssi2 = Rssi2;
- Queue->Entry[Tail].Signal = Signal;
- Queue->Entry[Tail].Wcid = (u8)Wcid;
-
- Queue->Entry[Tail].Channel = pAd->LatchRfRegs.Channel;
-
- if (Msg != NULL) {
- NdisMoveMemory(Queue->Entry[Tail].Msg, Msg, MsgLen);
- }
-
- NdisReleaseSpinLock(&(Queue->Lock));
-
- RTMP_MLME_HANDLER(pAd);
-
- return TRUE;
-}
-
-/*! \brief Dequeue a message from the MLME Queue
- * \param *Queue The MLME Queue
- * \param *Elem The message dequeued from MLME Queue
- * \return TRUE if the Elem contains something, FALSE otherwise
- * \pre
- * \post
-
- IRQL = DISPATCH_LEVEL
-
- */
-BOOLEAN MlmeDequeue(struct rt_mlme_queue *Queue, struct rt_mlme_queue_elem ** Elem)
-{
- NdisAcquireSpinLock(&(Queue->Lock));
- *Elem = &(Queue->Entry[Queue->Head]);
- Queue->Num--;
- Queue->Head++;
- if (Queue->Head == MAX_LEN_OF_MLME_QUEUE) {
- Queue->Head = 0;
- }
- NdisReleaseSpinLock(&(Queue->Lock));
- return TRUE;
-}
-
-/* IRQL = DISPATCH_LEVEL */
-void MlmeRestartStateMachine(struct rt_rtmp_adapter *pAd)
-{
-#ifdef RTMP_MAC_PCI
- struct rt_mlme_queue_elem *Elem = NULL;
-#endif /* RTMP_MAC_PCI // */
- BOOLEAN Cancelled;
-
- DBGPRINT(RT_DEBUG_TRACE, ("MlmeRestartStateMachine \n"));
-
-#ifdef RTMP_MAC_PCI
- NdisAcquireSpinLock(&pAd->Mlme.TaskLock);
- if (pAd->Mlme.bRunning) {
- NdisReleaseSpinLock(&pAd->Mlme.TaskLock);
- return;
- } else {
- pAd->Mlme.bRunning = TRUE;
- }
- NdisReleaseSpinLock(&pAd->Mlme.TaskLock);
-
- /* Remove all Mlme queues elements */
- while (!MlmeQueueEmpty(&pAd->Mlme.Queue)) {
- /*From message type, determine which state machine I should drive */
- if (MlmeDequeue(&pAd->Mlme.Queue, &Elem)) {
- /* free MLME element */
- Elem->Occupied = FALSE;
- Elem->MsgLen = 0;
-
- } else {
- DBGPRINT_ERR("MlmeRestartStateMachine: MlmeQueue empty\n");
- }
- }
-#endif /* RTMP_MAC_PCI // */
-
- {
- /* Cancel all timer events */
- /* Be careful to cancel new added timer */
- RTMPCancelTimer(&pAd->MlmeAux.AssocTimer, &Cancelled);
- RTMPCancelTimer(&pAd->MlmeAux.ReassocTimer, &Cancelled);
- RTMPCancelTimer(&pAd->MlmeAux.DisassocTimer, &Cancelled);
- RTMPCancelTimer(&pAd->MlmeAux.AuthTimer, &Cancelled);
- RTMPCancelTimer(&pAd->MlmeAux.BeaconTimer, &Cancelled);
- RTMPCancelTimer(&pAd->MlmeAux.ScanTimer, &Cancelled);
-
- }
-
- /* Change back to original channel in case of doing scan */
- AsicSwitchChannel(pAd, pAd->CommonCfg.Channel, FALSE);
- AsicLockChannel(pAd, pAd->CommonCfg.Channel);
-
- /* Resume MSDU which is turned off durning scan */
- RTMPResumeMsduTransmission(pAd);
-
- {
- /* Set all state machines back IDLE */
- pAd->Mlme.CntlMachine.CurrState = CNTL_IDLE;
- pAd->Mlme.AssocMachine.CurrState = ASSOC_IDLE;
- pAd->Mlme.AuthMachine.CurrState = AUTH_REQ_IDLE;
- pAd->Mlme.AuthRspMachine.CurrState = AUTH_RSP_IDLE;
- pAd->Mlme.SyncMachine.CurrState = SYNC_IDLE;
- pAd->Mlme.ActMachine.CurrState = ACT_IDLE;
- }
-
-#ifdef RTMP_MAC_PCI
- /* Remove running state */
- NdisAcquireSpinLock(&pAd->Mlme.TaskLock);
- pAd->Mlme.bRunning = FALSE;
- NdisReleaseSpinLock(&pAd->Mlme.TaskLock);
-#endif /* RTMP_MAC_PCI // */
-}
-
-/*! \brief test if the MLME Queue is empty
- * \param *Queue The MLME Queue
- * \return TRUE if the Queue is empty, FALSE otherwise
- * \pre
- * \post
-
- IRQL = DISPATCH_LEVEL
-
- */
-BOOLEAN MlmeQueueEmpty(struct rt_mlme_queue *Queue)
-{
- BOOLEAN Ans;
-
- NdisAcquireSpinLock(&(Queue->Lock));
- Ans = (Queue->Num == 0);
- NdisReleaseSpinLock(&(Queue->Lock));
-
- return Ans;
-}
-
-/*! \brief test if the MLME Queue is full
- * \param *Queue The MLME Queue
- * \return TRUE if the Queue is empty, FALSE otherwise
- * \pre
- * \post
-
- IRQL = PASSIVE_LEVEL
- IRQL = DISPATCH_LEVEL
-
- */
-BOOLEAN MlmeQueueFull(struct rt_mlme_queue *Queue)
-{
- BOOLEAN Ans;
-
- NdisAcquireSpinLock(&(Queue->Lock));
- Ans = (Queue->Num == MAX_LEN_OF_MLME_QUEUE
- || Queue->Entry[Queue->Tail].Occupied);
- NdisReleaseSpinLock(&(Queue->Lock));
-
- return Ans;
-}
-
-/*! \brief The destructor of MLME Queue
- * \param
- * \return
- * \pre
- * \post
- * \note Clear Mlme Queue, Set Queue->Num to Zero.
-
- IRQL = PASSIVE_LEVEL
-
- */
-void MlmeQueueDestroy(struct rt_mlme_queue *pQueue)
-{
- NdisAcquireSpinLock(&(pQueue->Lock));
- pQueue->Num = 0;
- pQueue->Head = 0;
- pQueue->Tail = 0;
- NdisReleaseSpinLock(&(pQueue->Lock));
- NdisFreeSpinLock(&(pQueue->Lock));
-}
-
-/*! \brief To substitute the message type if the message is coming from external
- * \param pFrame The frame received
- * \param *Machine The state machine
- * \param *MsgType the message type for the state machine
- * \return TRUE if the substitution is successful, FALSE otherwise
- * \pre
- * \post
-
- IRQL = DISPATCH_LEVEL
-
- */
-BOOLEAN MsgTypeSubst(struct rt_rtmp_adapter *pAd,
- struct rt_frame_802_11 * pFrame,
- int * Machine, int * MsgType)
-{
- u16 Seq, Alg;
- u8 EAPType;
- u8 *pData;
-
- /* Pointer to start of data frames including SNAP header */
- pData = (u8 *)pFrame + LENGTH_802_11;
-
- /* The only data type will pass to this function is EAPOL frame */
- if (pFrame->Hdr.FC.Type == BTYPE_DATA) {
- {
- *Machine = WPA_STATE_MACHINE;
- EAPType =
- *((u8 *) pFrame + LENGTH_802_11 +
- LENGTH_802_1_H + 1);
- return (WpaMsgTypeSubst(EAPType, (int *) MsgType));
- }
- }
-
- switch (pFrame->Hdr.FC.SubType) {
- case SUBTYPE_ASSOC_REQ:
- *Machine = ASSOC_STATE_MACHINE;
- *MsgType = MT2_PEER_ASSOC_REQ;
- break;
- case SUBTYPE_ASSOC_RSP:
- *Machine = ASSOC_STATE_MACHINE;
- *MsgType = MT2_PEER_ASSOC_RSP;
- break;
- case SUBTYPE_REASSOC_REQ:
- *Machine = ASSOC_STATE_MACHINE;
- *MsgType = MT2_PEER_REASSOC_REQ;
- break;
- case SUBTYPE_REASSOC_RSP:
- *Machine = ASSOC_STATE_MACHINE;
- *MsgType = MT2_PEER_REASSOC_RSP;
- break;
- case SUBTYPE_PROBE_REQ:
- *Machine = SYNC_STATE_MACHINE;
- *MsgType = MT2_PEER_PROBE_REQ;
- break;
- case SUBTYPE_PROBE_RSP:
- *Machine = SYNC_STATE_MACHINE;
- *MsgType = MT2_PEER_PROBE_RSP;
- break;
- case SUBTYPE_BEACON:
- *Machine = SYNC_STATE_MACHINE;
- *MsgType = MT2_PEER_BEACON;
- break;
- case SUBTYPE_ATIM:
- *Machine = SYNC_STATE_MACHINE;
- *MsgType = MT2_PEER_ATIM;
- break;
- case SUBTYPE_DISASSOC:
- *Machine = ASSOC_STATE_MACHINE;
- *MsgType = MT2_PEER_DISASSOC_REQ;
- break;
- case SUBTYPE_AUTH:
- /* get the sequence number from payload 24 Mac Header + 2 bytes algorithm */
- NdisMoveMemory(&Seq, &pFrame->Octet[2], sizeof(u16));
- NdisMoveMemory(&Alg, &pFrame->Octet[0], sizeof(u16));
- if (Seq == 1 || Seq == 3) {
- *Machine = AUTH_RSP_STATE_MACHINE;
- *MsgType = MT2_PEER_AUTH_ODD;
- } else if (Seq == 2 || Seq == 4) {
- if (Alg == AUTH_MODE_OPEN || Alg == AUTH_MODE_KEY) {
- *Machine = AUTH_STATE_MACHINE;
- *MsgType = MT2_PEER_AUTH_EVEN;
- }
- } else {
- return FALSE;
- }
- break;
- case SUBTYPE_DEAUTH:
- *Machine = AUTH_RSP_STATE_MACHINE;
- *MsgType = MT2_PEER_DEAUTH;
- break;
- case SUBTYPE_ACTION:
- *Machine = ACTION_STATE_MACHINE;
- /* Sometimes Sta will return with category bytes with MSB = 1, if they receive catogory out of their support */
- if ((pFrame->Octet[0] & 0x7F) > MAX_PEER_CATE_MSG) {
- *MsgType = MT2_ACT_INVALID;
- } else {
- *MsgType = (pFrame->Octet[0] & 0x7F);
- }
- break;
- default:
- return FALSE;
- break;
- }
-
- return TRUE;
-}
-
-/* =========================================================================================== */
-/* state_machine.c */
-/* =========================================================================================== */
-
-/*! \brief Initialize the state machine.
- * \param *S pointer to the state machine
- * \param Trans State machine transition function
- * \param StNr number of states
- * \param MsgNr number of messages
- * \param DefFunc default function, when there is invalid state/message combination
- * \param InitState initial state of the state machine
- * \param Base StateMachine base, internal use only
- * \pre p_sm should be a legal pointer
- * \post
-
- IRQL = PASSIVE_LEVEL
-
- */
-void StateMachineInit(struct rt_state_machine *S,
- IN STATE_MACHINE_FUNC Trans[],
- unsigned long StNr,
- unsigned long MsgNr,
- IN STATE_MACHINE_FUNC DefFunc,
- unsigned long InitState, unsigned long Base)
-{
- unsigned long i, j;
-
- /* set number of states and messages */
- S->NrState = StNr;
- S->NrMsg = MsgNr;
- S->Base = Base;
-
- S->TransFunc = Trans;
-
- /* init all state transition to default function */
- for (i = 0; i < StNr; i++) {
- for (j = 0; j < MsgNr; j++) {
- S->TransFunc[i * MsgNr + j] = DefFunc;
- }
- }
-
- /* set the starting state */
- S->CurrState = InitState;
-}
-
-/*! \brief This function fills in the function pointer into the cell in the state machine
- * \param *S pointer to the state machine
- * \param St state
- * \param Msg incoming message
- * \param f the function to be executed when (state, message) combination occurs at the state machine
- * \pre *S should be a legal pointer to the state machine, st, msg, should be all within the range, Base should be set in the initial state
- * \post
-
- IRQL = PASSIVE_LEVEL
-
- */
-void StateMachineSetAction(struct rt_state_machine *S,
- unsigned long St,
- unsigned long Msg, IN STATE_MACHINE_FUNC Func)
-{
- unsigned long MsgIdx;
-
- MsgIdx = Msg - S->Base;
-
- if (St < S->NrState && MsgIdx < S->NrMsg) {
- /* boundary checking before setting the action */
- S->TransFunc[St * S->NrMsg + MsgIdx] = Func;
- }
-}
-
-/*! \brief This function does the state transition
- * \param *Adapter the NIC adapter pointer
- * \param *S the state machine
- * \param *Elem the message to be executed
- * \return None
-
- IRQL = DISPATCH_LEVEL
-
- */
-void StateMachinePerformAction(struct rt_rtmp_adapter *pAd,
- struct rt_state_machine *S, struct rt_mlme_queue_elem *Elem)
-{
- (*(S->TransFunc[S->CurrState * S->NrMsg + Elem->MsgType - S->Base]))
- (pAd, Elem);
-}
-
-/*
- ==========================================================================
- Description:
- The drop function, when machine executes this, the message is simply
- ignored. This function does nothing, the message is freed in
- StateMachinePerformAction()
- ==========================================================================
- */
-void Drop(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
-}
-
-/* =========================================================================================== */
-/* lfsr.c */
-/* =========================================================================================== */
-
-/*
- ==========================================================================
- Description:
-
- IRQL = PASSIVE_LEVEL
-
- ==========================================================================
- */
-void LfsrInit(struct rt_rtmp_adapter *pAd, unsigned long Seed)
-{
- if (Seed == 0)
- pAd->Mlme.ShiftReg = 1;
- else
- pAd->Mlme.ShiftReg = Seed;
-}
-
-/*
- ==========================================================================
- Description:
- ==========================================================================
- */
-u8 RandomByte(struct rt_rtmp_adapter *pAd)
-{
- unsigned long i;
- u8 R, Result;
-
- R = 0;
-
- if (pAd->Mlme.ShiftReg == 0)
- NdisGetSystemUpTime((unsigned long *) & pAd->Mlme.ShiftReg);
-
- for (i = 0; i < 8; i++) {
- if (pAd->Mlme.ShiftReg & 0x00000001) {
- pAd->Mlme.ShiftReg =
- ((pAd->Mlme.
- ShiftReg ^ LFSR_MASK) >> 1) | 0x80000000;
- Result = 1;
- } else {
- pAd->Mlme.ShiftReg = pAd->Mlme.ShiftReg >> 1;
- Result = 0;
- }
- R = (R << 1) | Result;
- }
-
- return R;
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Verify the support rate for different PHY type
-
- Arguments:
- pAd Pointer to our adapter
-
- Return Value:
- None
-
- IRQL = PASSIVE_LEVEL
-
- ========================================================================
-*/
-void RTMPCheckRates(struct rt_rtmp_adapter *pAd,
- IN u8 SupRate[], IN u8 * SupRateLen)
-{
- u8 RateIdx, i, j;
- u8 NewRate[12], NewRateLen;
-
- NewRateLen = 0;
-
- if (pAd->CommonCfg.PhyMode == PHY_11B)
- RateIdx = 4;
- else
- RateIdx = 12;
-
- /* Check for support rates exclude basic rate bit */
- for (i = 0; i < *SupRateLen; i++)
- for (j = 0; j < RateIdx; j++)
- if ((SupRate[i] & 0x7f) == RateIdTo500Kbps[j])
- NewRate[NewRateLen++] = SupRate[i];
-
- *SupRateLen = NewRateLen;
- NdisMoveMemory(SupRate, NewRate, NewRateLen);
-}
-
-BOOLEAN RTMPCheckChannel(struct rt_rtmp_adapter *pAd,
- u8 CentralChannel, u8 Channel)
-{
- u8 k;
- u8 UpperChannel = 0, LowerChannel = 0;
- u8 NoEffectChannelinList = 0;
-
- /* Find upper and lower channel according to 40MHz current operation. */
- if (CentralChannel < Channel) {
- UpperChannel = Channel;
- if (CentralChannel > 2)
- LowerChannel = CentralChannel - 2;
- else
- return FALSE;
- } else if (CentralChannel > Channel) {
- UpperChannel = CentralChannel + 2;
- LowerChannel = Channel;
- }
-
- for (k = 0; k < pAd->ChannelListNum; k++) {
- if (pAd->ChannelList[k].Channel == UpperChannel) {
- NoEffectChannelinList++;
- }
- if (pAd->ChannelList[k].Channel == LowerChannel) {
- NoEffectChannelinList++;
- }
- }
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("Total Channel in Channel List = [%d]\n",
- NoEffectChannelinList));
- if (NoEffectChannelinList == 2)
- return TRUE;
- else
- return FALSE;
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Verify the support rate for HT phy type
-
- Arguments:
- pAd Pointer to our adapter
-
- Return Value:
- FALSE if pAd->CommonCfg.SupportedHtPhy doesn't accept the pHtCapability. (AP Mode)
-
- IRQL = PASSIVE_LEVEL
-
- ========================================================================
-*/
-BOOLEAN RTMPCheckHt(struct rt_rtmp_adapter *pAd,
- u8 Wcid,
- struct rt_ht_capability_ie * pHtCapability,
- struct rt_add_ht_info_ie * pAddHtInfo)
-{
- if (Wcid >= MAX_LEN_OF_MAC_TABLE)
- return FALSE;
-
- /* If use AMSDU, set flag. */
- if (pAd->CommonCfg.DesiredHtPhy.AmsduEnable)
- CLIENT_STATUS_SET_FLAG(&pAd->MacTab.Content[Wcid],
- fCLIENT_STATUS_AMSDU_INUSED);
- /* Save Peer Capability */
- if (pHtCapability->HtCapInfo.ShortGIfor20)
- CLIENT_STATUS_SET_FLAG(&pAd->MacTab.Content[Wcid],
- fCLIENT_STATUS_SGI20_CAPABLE);
- if (pHtCapability->HtCapInfo.ShortGIfor40)
- CLIENT_STATUS_SET_FLAG(&pAd->MacTab.Content[Wcid],
- fCLIENT_STATUS_SGI40_CAPABLE);
- if (pHtCapability->HtCapInfo.TxSTBC)
- CLIENT_STATUS_SET_FLAG(&pAd->MacTab.Content[Wcid],
- fCLIENT_STATUS_TxSTBC_CAPABLE);
- if (pHtCapability->HtCapInfo.RxSTBC)
- CLIENT_STATUS_SET_FLAG(&pAd->MacTab.Content[Wcid],
- fCLIENT_STATUS_RxSTBC_CAPABLE);
- if (pAd->CommonCfg.bRdg && pHtCapability->ExtHtCapInfo.RDGSupport) {
- CLIENT_STATUS_SET_FLAG(&pAd->MacTab.Content[Wcid],
- fCLIENT_STATUS_RDG_CAPABLE);
- }
-
- if (Wcid < MAX_LEN_OF_MAC_TABLE) {
- pAd->MacTab.Content[Wcid].MpduDensity =
- pHtCapability->HtCapParm.MpduDensity;
- }
- /* Will check ChannelWidth for MCSSet[4] below */
- pAd->MlmeAux.HtCapability.MCSSet[4] = 0x1;
- switch (pAd->CommonCfg.RxStream) {
- case 1:
- pAd->MlmeAux.HtCapability.MCSSet[0] = 0xff;
- pAd->MlmeAux.HtCapability.MCSSet[1] = 0x00;
- pAd->MlmeAux.HtCapability.MCSSet[2] = 0x00;
- pAd->MlmeAux.HtCapability.MCSSet[3] = 0x00;
- break;
- case 2:
- pAd->MlmeAux.HtCapability.MCSSet[0] = 0xff;
- pAd->MlmeAux.HtCapability.MCSSet[1] = 0xff;
- pAd->MlmeAux.HtCapability.MCSSet[2] = 0x00;
- pAd->MlmeAux.HtCapability.MCSSet[3] = 0x00;
- break;
- case 3:
- pAd->MlmeAux.HtCapability.MCSSet[0] = 0xff;
- pAd->MlmeAux.HtCapability.MCSSet[1] = 0xff;
- pAd->MlmeAux.HtCapability.MCSSet[2] = 0xff;
- pAd->MlmeAux.HtCapability.MCSSet[3] = 0x00;
- break;
- }
-
- pAd->MlmeAux.HtCapability.HtCapInfo.ChannelWidth =
- pAddHtInfo->AddHtInfo.RecomWidth & pAd->CommonCfg.DesiredHtPhy.
- ChannelWidth;
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("RTMPCheckHt:: HtCapInfo.ChannelWidth=%d, RecomWidth=%d, DesiredHtPhy.ChannelWidth=%d, BW40MAvailForA/G=%d/%d, PhyMode=%d \n",
- pAd->MlmeAux.HtCapability.HtCapInfo.ChannelWidth,
- pAddHtInfo->AddHtInfo.RecomWidth,
- pAd->CommonCfg.DesiredHtPhy.ChannelWidth,
- pAd->NicConfig2.field.BW40MAvailForA,
- pAd->NicConfig2.field.BW40MAvailForG,
- pAd->CommonCfg.PhyMode));
-
- pAd->MlmeAux.HtCapability.HtCapInfo.GF =
- pHtCapability->HtCapInfo.GF & pAd->CommonCfg.DesiredHtPhy.GF;
-
- /* Send Assoc Req with my HT capability. */
- pAd->MlmeAux.HtCapability.HtCapInfo.AMsduSize =
- pAd->CommonCfg.DesiredHtPhy.AmsduSize;
- pAd->MlmeAux.HtCapability.HtCapInfo.MimoPs =
- pAd->CommonCfg.DesiredHtPhy.MimoPs;
- pAd->MlmeAux.HtCapability.HtCapInfo.ShortGIfor20 =
- (pAd->CommonCfg.DesiredHtPhy.ShortGIfor20) & (pHtCapability->
- HtCapInfo.
- ShortGIfor20);
- pAd->MlmeAux.HtCapability.HtCapInfo.ShortGIfor40 =
- (pAd->CommonCfg.DesiredHtPhy.ShortGIfor40) & (pHtCapability->
- HtCapInfo.
- ShortGIfor40);
- pAd->MlmeAux.HtCapability.HtCapInfo.TxSTBC =
- (pAd->CommonCfg.DesiredHtPhy.TxSTBC) & (pHtCapability->HtCapInfo.
- RxSTBC);
- pAd->MlmeAux.HtCapability.HtCapInfo.RxSTBC =
- (pAd->CommonCfg.DesiredHtPhy.RxSTBC) & (pHtCapability->HtCapInfo.
- TxSTBC);
- pAd->MlmeAux.HtCapability.HtCapParm.MaxRAmpduFactor =
- pAd->CommonCfg.DesiredHtPhy.MaxRAmpduFactor;
- pAd->MlmeAux.HtCapability.HtCapParm.MpduDensity =
- pAd->CommonCfg.HtCapability.HtCapParm.MpduDensity;
- pAd->MlmeAux.HtCapability.ExtHtCapInfo.PlusHTC =
- pHtCapability->ExtHtCapInfo.PlusHTC;
- pAd->MacTab.Content[Wcid].HTCapability.ExtHtCapInfo.PlusHTC =
- pHtCapability->ExtHtCapInfo.PlusHTC;
- if (pAd->CommonCfg.bRdg) {
- pAd->MlmeAux.HtCapability.ExtHtCapInfo.RDGSupport =
- pHtCapability->ExtHtCapInfo.RDGSupport;
- pAd->MlmeAux.HtCapability.ExtHtCapInfo.PlusHTC = 1;
- }
-
- if (pAd->MlmeAux.HtCapability.HtCapInfo.ChannelWidth == BW_20)
- pAd->MlmeAux.HtCapability.MCSSet[4] = 0x0; /* BW20 can't transmit MCS32 */
-
- COPY_AP_HTSETTINGS_FROM_BEACON(pAd, pHtCapability);
- return TRUE;
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Verify the support rate for different PHY type
-
- Arguments:
- pAd Pointer to our adapter
-
- Return Value:
- None
-
- IRQL = PASSIVE_LEVEL
-
- ========================================================================
-*/
-void RTMPUpdateMlmeRate(struct rt_rtmp_adapter *pAd)
-{
- u8 MinimumRate;
- u8 ProperMlmeRate; /*= RATE_54; */
- u8 i, j, RateIdx = 12; /*1, 2, 5.5, 11, 6, 9, 12, 18, 24, 36, 48, 54 */
- BOOLEAN bMatch = FALSE;
-
- switch (pAd->CommonCfg.PhyMode) {
- case PHY_11B:
- ProperMlmeRate = RATE_11;
- MinimumRate = RATE_1;
- break;
- case PHY_11BG_MIXED:
- case PHY_11ABGN_MIXED:
- case PHY_11BGN_MIXED:
- if ((pAd->MlmeAux.SupRateLen == 4) &&
- (pAd->MlmeAux.ExtRateLen == 0))
- /* B only AP */
- ProperMlmeRate = RATE_11;
- else
- ProperMlmeRate = RATE_24;
-
- if (pAd->MlmeAux.Channel <= 14)
- MinimumRate = RATE_1;
- else
- MinimumRate = RATE_6;
- break;
- case PHY_11A:
- case PHY_11N_2_4G: /* rt2860 need to check mlmerate for 802.11n */
- case PHY_11GN_MIXED:
- case PHY_11AGN_MIXED:
- case PHY_11AN_MIXED:
- case PHY_11N_5G:
- ProperMlmeRate = RATE_24;
- MinimumRate = RATE_6;
- break;
- case PHY_11ABG_MIXED:
- ProperMlmeRate = RATE_24;
- if (pAd->MlmeAux.Channel <= 14)
- MinimumRate = RATE_1;
- else
- MinimumRate = RATE_6;
- break;
- default: /* error */
- ProperMlmeRate = RATE_1;
- MinimumRate = RATE_1;
- break;
- }
-
- for (i = 0; i < pAd->MlmeAux.SupRateLen; i++) {
- for (j = 0; j < RateIdx; j++) {
- if ((pAd->MlmeAux.SupRate[i] & 0x7f) ==
- RateIdTo500Kbps[j]) {
- if (j == ProperMlmeRate) {
- bMatch = TRUE;
- break;
- }
- }
- }
-
- if (bMatch)
- break;
- }
-
- if (bMatch == FALSE) {
- for (i = 0; i < pAd->MlmeAux.ExtRateLen; i++) {
- for (j = 0; j < RateIdx; j++) {
- if ((pAd->MlmeAux.ExtRate[i] & 0x7f) ==
- RateIdTo500Kbps[j]) {
- if (j == ProperMlmeRate) {
- bMatch = TRUE;
- break;
- }
- }
- }
-
- if (bMatch)
- break;
- }
- }
-
- if (bMatch == FALSE) {
- ProperMlmeRate = MinimumRate;
- }
-
- pAd->CommonCfg.MlmeRate = MinimumRate;
- pAd->CommonCfg.RtsRate = ProperMlmeRate;
- if (pAd->CommonCfg.MlmeRate >= RATE_6) {
- pAd->CommonCfg.MlmeTransmit.field.MODE = MODE_OFDM;
- pAd->CommonCfg.MlmeTransmit.field.MCS =
- OfdmRateToRxwiMCS[pAd->CommonCfg.MlmeRate];
- pAd->MacTab.Content[BSS0Mcast_WCID].HTPhyMode.field.MODE =
- MODE_OFDM;
- pAd->MacTab.Content[BSS0Mcast_WCID].HTPhyMode.field.MCS =
- OfdmRateToRxwiMCS[pAd->CommonCfg.MlmeRate];
- } else {
- pAd->CommonCfg.MlmeTransmit.field.MODE = MODE_CCK;
- pAd->CommonCfg.MlmeTransmit.field.MCS = pAd->CommonCfg.MlmeRate;
- pAd->MacTab.Content[BSS0Mcast_WCID].HTPhyMode.field.MODE =
- MODE_CCK;
- pAd->MacTab.Content[BSS0Mcast_WCID].HTPhyMode.field.MCS =
- pAd->CommonCfg.MlmeRate;
- }
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("RTMPUpdateMlmeRate ==> MlmeTransmit = 0x%x \n",
- pAd->CommonCfg.MlmeTransmit.word));
-}
-
-char RTMPMaxRssi(struct rt_rtmp_adapter *pAd,
- char Rssi0, char Rssi1, char Rssi2)
-{
- char larger = -127;
-
- if ((pAd->Antenna.field.RxPath == 1) && (Rssi0 != 0)) {
- larger = Rssi0;
- }
-
- if ((pAd->Antenna.field.RxPath >= 2) && (Rssi1 != 0)) {
- larger = max(Rssi0, Rssi1);
- }
-
- if ((pAd->Antenna.field.RxPath == 3) && (Rssi2 != 0)) {
- larger = max(larger, Rssi2);
- }
-
- if (larger == -127)
- larger = 0;
-
- return larger;
-}
-
-/*
- ========================================================================
- Routine Description:
- Periodic evaluate antenna link status
-
- Arguments:
- pAd - Adapter pointer
-
- Return Value:
- None
-
- ========================================================================
-*/
-void AsicEvaluateRxAnt(struct rt_rtmp_adapter *pAd)
-{
- u8 BBPR3 = 0;
-
- if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_RESET_IN_PROGRESS |
- fRTMP_ADAPTER_HALT_IN_PROGRESS |
- fRTMP_ADAPTER_RADIO_OFF |
- fRTMP_ADAPTER_NIC_NOT_EXIST |
- fRTMP_ADAPTER_BSS_SCAN_IN_PROGRESS) ||
- OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_DOZE)
-#ifdef RT30xx
- || (pAd->EepromAccess)
-#endif /* RT30xx // */
-#ifdef RT3090
- || (pAd->bPCIclkOff == TRUE)
-#endif /* RT3090 // */
- )
- return;
-
- {
- /*if (pAd->StaCfg.Psm == PWR_SAVE) */
- /* return; */
-
- {
-
- if (pAd->StaCfg.Psm == PWR_SAVE)
- return;
-
- RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &BBPR3);
- BBPR3 &= (~0x18);
- if (pAd->Antenna.field.RxPath == 3) {
- BBPR3 |= (0x10);
- } else if (pAd->Antenna.field.RxPath == 2) {
- BBPR3 |= (0x8);
- } else if (pAd->Antenna.field.RxPath == 1) {
- BBPR3 |= (0x0);
- }
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BBPR3);
-#ifdef RTMP_MAC_PCI
- pAd->StaCfg.BBPR3 = BBPR3;
-#endif /* RTMP_MAC_PCI // */
- if (OPSTATUS_TEST_FLAG
- (pAd, fOP_STATUS_MEDIA_STATE_CONNECTED)
- ) {
- unsigned long TxTotalCnt =
- pAd->RalinkCounters.OneSecTxNoRetryOkCount +
- pAd->RalinkCounters.OneSecTxRetryOkCount +
- pAd->RalinkCounters.OneSecTxFailCount;
-
- /* dynamic adjust antenna evaluation period according to the traffic */
- if (TxTotalCnt > 50) {
- RTMPSetTimer(&pAd->Mlme.RxAntEvalTimer,
- 20);
- pAd->Mlme.bLowThroughput = FALSE;
- } else {
- RTMPSetTimer(&pAd->Mlme.RxAntEvalTimer,
- 300);
- pAd->Mlme.bLowThroughput = TRUE;
- }
- }
- }
-
- }
-
-}
-
-/*
- ========================================================================
- Routine Description:
- After evaluation, check antenna link status
-
- Arguments:
- pAd - Adapter pointer
-
- Return Value:
- None
-
- ========================================================================
-*/
-void AsicRxAntEvalTimeout(void *SystemSpecific1,
- void *FunctionContext,
- void *SystemSpecific2, void *SystemSpecific3)
-{
- struct rt_rtmp_adapter *pAd = (struct rt_rtmp_adapter *)FunctionContext;
- u8 BBPR3 = 0;
- char larger = -127, rssi0, rssi1, rssi2;
-
- if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_RESET_IN_PROGRESS |
- fRTMP_ADAPTER_HALT_IN_PROGRESS |
- fRTMP_ADAPTER_RADIO_OFF |
- fRTMP_ADAPTER_NIC_NOT_EXIST) ||
- OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_DOZE)
-#ifdef RT30xx
- || (pAd->EepromAccess)
-#endif /* RT30xx // */
-#ifdef RT3090
- || (pAd->bPCIclkOff == TRUE)
-#endif /* RT3090 // */
- )
- return;
-
- {
- /*if (pAd->StaCfg.Psm == PWR_SAVE) */
- /* return; */
- {
- if (pAd->StaCfg.Psm == PWR_SAVE)
- return;
-
- /* if the traffic is low, use average rssi as the criteria */
- if (pAd->Mlme.bLowThroughput == TRUE) {
- rssi0 = pAd->StaCfg.RssiSample.LastRssi0;
- rssi1 = pAd->StaCfg.RssiSample.LastRssi1;
- rssi2 = pAd->StaCfg.RssiSample.LastRssi2;
- } else {
- rssi0 = pAd->StaCfg.RssiSample.AvgRssi0;
- rssi1 = pAd->StaCfg.RssiSample.AvgRssi1;
- rssi2 = pAd->StaCfg.RssiSample.AvgRssi2;
- }
-
- if (pAd->Antenna.field.RxPath == 3) {
- larger = max(rssi0, rssi1);
-
- if (larger > (rssi2 + 20))
- pAd->Mlme.RealRxPath = 2;
- else
- pAd->Mlme.RealRxPath = 3;
- } else if (pAd->Antenna.field.RxPath == 2) {
- if (rssi0 > (rssi1 + 20))
- pAd->Mlme.RealRxPath = 1;
- else
- pAd->Mlme.RealRxPath = 2;
- }
-
- RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &BBPR3);
- BBPR3 &= (~0x18);
- if (pAd->Mlme.RealRxPath == 3) {
- BBPR3 |= (0x10);
- } else if (pAd->Mlme.RealRxPath == 2) {
- BBPR3 |= (0x8);
- } else if (pAd->Mlme.RealRxPath == 1) {
- BBPR3 |= (0x0);
- }
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BBPR3);
-#ifdef RTMP_MAC_PCI
- pAd->StaCfg.BBPR3 = BBPR3;
-#endif /* RTMP_MAC_PCI // */
- }
- }
-
-}
-
-void APSDPeriodicExec(void *SystemSpecific1,
- void *FunctionContext,
- void *SystemSpecific2, void *SystemSpecific3)
-{
- struct rt_rtmp_adapter *pAd = (struct rt_rtmp_adapter *)FunctionContext;
-
- if (!OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_MEDIA_STATE_CONNECTED))
- return;
-
- pAd->CommonCfg.TriggerTimerCount++;
-
-/* Driver should not send trigger frame, it should be send by application layer */
-/*
- if (pAd->CommonCfg.bAPSDCapable && pAd->CommonCfg.APEdcaParm.bAPSDCapable
- && (pAd->CommonCfg.bNeedSendTriggerFrame ||
- (((pAd->CommonCfg.TriggerTimerCount%20) == 19) && (!pAd->CommonCfg.bAPSDAC_BE || !pAd->CommonCfg.bAPSDAC_BK || !pAd->CommonCfg.bAPSDAC_VI || !pAd->CommonCfg.bAPSDAC_VO))))
- {
- DBGPRINT(RT_DEBUG_TRACE,("Sending trigger frame and enter service period when support APSD\n"));
- RTMPSendNullFrame(pAd, pAd->CommonCfg.TxRate, TRUE);
- pAd->CommonCfg.bNeedSendTriggerFrame = FALSE;
- pAd->CommonCfg.TriggerTimerCount = 0;
- pAd->CommonCfg.bInServicePeriod = TRUE;
- }*/
-}
-
-/*
- ========================================================================
- Routine Description:
- Set/reset MAC registers according to bPiggyBack parameter
-
- Arguments:
- pAd - Adapter pointer
- bPiggyBack - Enable / Disable Piggy-Back
-
- Return Value:
- None
-
- ========================================================================
-*/
-void RTMPSetPiggyBack(struct rt_rtmp_adapter *pAd, IN BOOLEAN bPiggyBack)
-{
- TX_LINK_CFG_STRUC TxLinkCfg;
-
- RTMP_IO_READ32(pAd, TX_LINK_CFG, &TxLinkCfg.word);
-
- TxLinkCfg.field.TxCFAckEn = bPiggyBack;
- RTMP_IO_WRITE32(pAd, TX_LINK_CFG, TxLinkCfg.word);
-}
-
-/*
- ========================================================================
- Routine Description:
- check if this entry need to switch rate automatically
-
- Arguments:
- pAd
- pEntry
-
- Return Value:
- TURE
- FALSE
-
- ========================================================================
-*/
-BOOLEAN RTMPCheckEntryEnableAutoRateSwitch(struct rt_rtmp_adapter *pAd,
- struct rt_mac_table_entry *pEntry)
-{
- BOOLEAN result = TRUE;
-
- {
- /* only associated STA counts */
- if (pEntry && (pEntry->ValidAsCLI)
- && (pEntry->Sst == SST_ASSOC)) {
- result = pAd->StaCfg.bAutoTxRateSwitch;
- } else
- result = FALSE;
- }
-
- return result;
-}
-
-BOOLEAN RTMPAutoRateSwitchCheck(struct rt_rtmp_adapter *pAd)
-{
- {
- if (pAd->StaCfg.bAutoTxRateSwitch)
- return TRUE;
- }
- return FALSE;
-}
-
-/*
- ========================================================================
- Routine Description:
- check if this entry need to fix tx legacy rate
-
- Arguments:
- pAd
- pEntry
-
- Return Value:
- TURE
- FALSE
-
- ========================================================================
-*/
-u8 RTMPStaFixedTxMode(struct rt_rtmp_adapter *pAd, struct rt_mac_table_entry *pEntry)
-{
- u8 tx_mode = FIXED_TXMODE_HT;
-
- {
- tx_mode =
- (u8)pAd->StaCfg.DesiredTransmitSetting.field.
- FixedTxMode;
- }
-
- return tx_mode;
-}
-
-/*
- ========================================================================
- Routine Description:
- Overwrite HT Tx Mode by Fixed Legency Tx Mode, if specified.
-
- Arguments:
- pAd
- pEntry
-
- Return Value:
- TURE
- FALSE
-
- ========================================================================
-*/
-void RTMPUpdateLegacyTxSetting(u8 fixed_tx_mode, struct rt_mac_table_entry *pEntry)
-{
- HTTRANSMIT_SETTING TransmitSetting;
-
- if (fixed_tx_mode == FIXED_TXMODE_HT)
- return;
-
- TransmitSetting.word = 0;
-
- TransmitSetting.field.MODE = pEntry->HTPhyMode.field.MODE;
- TransmitSetting.field.MCS = pEntry->HTPhyMode.field.MCS;
-
- if (fixed_tx_mode == FIXED_TXMODE_CCK) {
- TransmitSetting.field.MODE = MODE_CCK;
- /* CCK mode allow MCS 0~3 */
- if (TransmitSetting.field.MCS > MCS_3)
- TransmitSetting.field.MCS = MCS_3;
- } else {
- TransmitSetting.field.MODE = MODE_OFDM;
- /* OFDM mode allow MCS 0~7 */
- if (TransmitSetting.field.MCS > MCS_7)
- TransmitSetting.field.MCS = MCS_7;
- }
-
- if (pEntry->HTPhyMode.field.MODE >= TransmitSetting.field.MODE) {
- pEntry->HTPhyMode.word = TransmitSetting.word;
- DBGPRINT(RT_DEBUG_TRACE,
- ("RTMPUpdateLegacyTxSetting : wcid-%d, MODE=%s, MCS=%d \n",
- pEntry->Aid, GetPhyMode(pEntry->HTPhyMode.field.MODE),
- pEntry->HTPhyMode.field.MCS));
- }
-}
-
-/*
- ==========================================================================
- Description:
- dynamic tune BBP R66 to find a balance between sensibility and
- noise isolation
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
- */
-void AsicStaBbpTuning(struct rt_rtmp_adapter *pAd)
-{
- u8 OrigR66Value = 0, R66; /*, R66UpperBound = 0x30, R66LowerBound = 0x30; */
- char Rssi;
-
- /* 2860C did not support Fase CCA, therefore can't tune */
- if (pAd->MACVersion == 0x28600100)
- return;
-
- /* */
- /* work as a STA */
- /* */
- if (pAd->Mlme.CntlMachine.CurrState != CNTL_IDLE) /* no R66 tuning when SCANNING */
- return;
-
- if ((pAd->OpMode == OPMODE_STA)
- && (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_MEDIA_STATE_CONNECTED)
- )
- && !(OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_DOZE))
-#ifdef RTMP_MAC_PCI
- && (pAd->bPCIclkOff == FALSE)
-#endif /* RTMP_MAC_PCI // */
- ) {
- RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R66, &OrigR66Value);
- R66 = OrigR66Value;
-
- if (pAd->Antenna.field.RxPath > 1)
- Rssi =
- (pAd->StaCfg.RssiSample.AvgRssi0 +
- pAd->StaCfg.RssiSample.AvgRssi1) >> 1;
- else
- Rssi = pAd->StaCfg.RssiSample.AvgRssi0;
-
- if (pAd->LatchRfRegs.Channel <= 14) { /*BG band */
-#ifdef RT30xx
- /* RT3070 is a no LNA solution, it should have different control regarding to AGC gain control */
- /* Otherwise, it will have some throughput side effect when low RSSI */
-
- if (IS_RT3070(pAd) || IS_RT3090(pAd) || IS_RT3572(pAd)
- || IS_RT3390(pAd)) {
- if (Rssi > RSSI_FOR_MID_LOW_SENSIBILITY) {
- R66 =
- 0x1C + 2 * GET_LNA_GAIN(pAd) + 0x20;
- if (OrigR66Value != R66) {
- RTMP_BBP_IO_WRITE8_BY_REG_ID
- (pAd, BBP_R66, R66);
- }
- } else {
- R66 = 0x1C + 2 * GET_LNA_GAIN(pAd);
- if (OrigR66Value != R66) {
- RTMP_BBP_IO_WRITE8_BY_REG_ID
- (pAd, BBP_R66, R66);
- }
- }
- } else
-#endif /* RT30xx // */
- {
- if (Rssi > RSSI_FOR_MID_LOW_SENSIBILITY) {
- R66 = (0x2E + GET_LNA_GAIN(pAd)) + 0x10;
- if (OrigR66Value != R66) {
- RTMP_BBP_IO_WRITE8_BY_REG_ID
- (pAd, BBP_R66, R66);
- }
- } else {
- R66 = 0x2E + GET_LNA_GAIN(pAd);
- if (OrigR66Value != R66) {
- RTMP_BBP_IO_WRITE8_BY_REG_ID
- (pAd, BBP_R66, R66);
- }
- }
- }
- } else { /*A band */
- if (pAd->CommonCfg.BBPCurrentBW == BW_20) {
- if (Rssi > RSSI_FOR_MID_LOW_SENSIBILITY) {
- R66 =
- 0x32 + (GET_LNA_GAIN(pAd) * 5) / 3 +
- 0x10;
- if (OrigR66Value != R66) {
- RTMP_BBP_IO_WRITE8_BY_REG_ID
- (pAd, BBP_R66, R66);
- }
- } else {
- R66 =
- 0x32 + (GET_LNA_GAIN(pAd) * 5) / 3;
- if (OrigR66Value != R66) {
- RTMP_BBP_IO_WRITE8_BY_REG_ID
- (pAd, BBP_R66, R66);
- }
- }
- } else {
- if (Rssi > RSSI_FOR_MID_LOW_SENSIBILITY) {
- R66 =
- 0x3A + (GET_LNA_GAIN(pAd) * 5) / 3 +
- 0x10;
- if (OrigR66Value != R66) {
- RTMP_BBP_IO_WRITE8_BY_REG_ID
- (pAd, BBP_R66, R66);
- }
- } else {
- R66 =
- 0x3A + (GET_LNA_GAIN(pAd) * 5) / 3;
- if (OrigR66Value != R66) {
- RTMP_BBP_IO_WRITE8_BY_REG_ID
- (pAd, BBP_R66, R66);
- }
- }
- }
- }
-
- }
-}
-
-void RTMPSetAGCInitValue(struct rt_rtmp_adapter *pAd, u8 BandWidth)
-{
- u8 R66 = 0x30;
-
- if (pAd->LatchRfRegs.Channel <= 14) { /* BG band */
-#ifdef RT30xx
- /* Gary was verified Amazon AP and find that RT307x has BBP_R66 invalid default value */
-
- if (IS_RT3070(pAd) || IS_RT3090(pAd) || IS_RT3572(pAd)
- || IS_RT3390(pAd)) {
- R66 = 0x1C + 2 * GET_LNA_GAIN(pAd);
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, R66);
- } else
-#endif /* RT30xx // */
- {
- R66 = 0x2E + GET_LNA_GAIN(pAd);
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, R66);
- }
- } else { /*A band */
- {
- if (BandWidth == BW_20) {
- R66 =
- (u8)(0x32 +
- (GET_LNA_GAIN(pAd) * 5) / 3);
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, R66);
- } else {
- R66 =
- (u8)(0x3A +
- (GET_LNA_GAIN(pAd) * 5) / 3);
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, R66);
- }
- }
- }
-
-}
diff --git a/drivers/staging/rt2860/common/rt_channel.c b/drivers/staging/rt2860/common/rt_channel.c
deleted file mode 100644
index 5387989..0000000
--- a/drivers/staging/rt2860/common/rt_channel.c
+++ /dev/null
@@ -1,1705 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-*/
-#include "../rt_config.h"
-
-struct rt_ch_freq_map CH_HZ_ID_MAP[] = {
- {1, 2412}
- ,
- {2, 2417}
- ,
- {3, 2422}
- ,
- {4, 2427}
- ,
- {5, 2432}
- ,
- {6, 2437}
- ,
- {7, 2442}
- ,
- {8, 2447}
- ,
- {9, 2452}
- ,
- {10, 2457}
- ,
- {11, 2462}
- ,
- {12, 2467}
- ,
- {13, 2472}
- ,
- {14, 2484}
- ,
-
- /* UNII */
- {36, 5180}
- ,
- {40, 5200}
- ,
- {44, 5220}
- ,
- {48, 5240}
- ,
- {52, 5260}
- ,
- {56, 5280}
- ,
- {60, 5300}
- ,
- {64, 5320}
- ,
- {149, 5745}
- ,
- {153, 5765}
- ,
- {157, 5785}
- ,
- {161, 5805}
- ,
- {165, 5825}
- ,
- {167, 5835}
- ,
- {169, 5845}
- ,
- {171, 5855}
- ,
- {173, 5865}
- ,
-
- /* HiperLAN2 */
- {100, 5500}
- ,
- {104, 5520}
- ,
- {108, 5540}
- ,
- {112, 5560}
- ,
- {116, 5580}
- ,
- {120, 5600}
- ,
- {124, 5620}
- ,
- {128, 5640}
- ,
- {132, 5660}
- ,
- {136, 5680}
- ,
- {140, 5700}
- ,
-
- /* Japan MMAC */
- {34, 5170}
- ,
- {38, 5190}
- ,
- {42, 5210}
- ,
- {46, 5230}
- ,
-
- /* Japan */
- {184, 4920}
- ,
- {188, 4940}
- ,
- {192, 4960}
- ,
- {196, 4980}
- ,
-
- {208, 5040}
- , /* Japan, means J08 */
- {212, 5060}
- , /* Japan, means J12 */
- {216, 5080}
- , /* Japan, means J16 */
-};
-
-int CH_HZ_ID_MAP_NUM = (sizeof(CH_HZ_ID_MAP) / sizeof(struct rt_ch_freq_map));
-
-struct rt_ch_region ChRegion[] = {
- { /* Antigua and Berbuda */
- "AG",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~13 */
- {36, 4, 23, BOTH, FALSE}
- , /* 5G, ch 36~48 */
- {52, 4, 23, BOTH, FALSE}
- , /* 5G, ch 52~64 */
- {100, 11, 30, BOTH, FALSE}
- , /* 5G, ch 100~140 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Argentina */
- "AR",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~13 */
- {52, 4, 24, BOTH, FALSE}
- , /* 5G, ch 52~64 */
- {149, 4, 30, BOTH, FALSE}
- , /* 5G, ch 149~161 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Aruba */
- "AW",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~13 */
- {36, 4, 23, BOTH, FALSE}
- , /* 5G, ch 36~48 */
- {52, 4, 23, BOTH, FALSE}
- , /* 5G, ch 52~64 */
- {100, 11, 30, BOTH, FALSE}
- , /* 5G, ch 100~140 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Australia */
- "AU",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~13 */
- {36, 4, 23, BOTH, FALSE}
- , /* 5G, ch 36~48 */
- {52, 4, 24, BOTH, FALSE}
- , /* 5G, ch 52~64 */
- {149, 5, 30, BOTH, FALSE}
- , /* 5G, ch 149~165 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Austria */
- "AT",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~13 */
- {36, 4, 23, IDOR, TRUE}
- , /* 5G, ch 36~48 */
- {52, 4, 23, IDOR, TRUE}
- , /* 5G, ch 52~64 */
- {100, 11, 30, BOTH, TRUE}
- , /* 5G, ch 100~140 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Bahamas */
- "BS",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~13 */
- {36, 4, 23, BOTH, FALSE}
- , /* 5G, ch 36~48 */
- {52, 4, 24, BOTH, FALSE}
- , /* 5G, ch 52~64 */
- {149, 5, 30, BOTH, FALSE}
- , /* 5G, ch 149~165 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Barbados */
- "BB",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~13 */
- {36, 4, 23, BOTH, FALSE}
- , /* 5G, ch 36~48 */
- {52, 4, 24, BOTH, FALSE}
- , /* 5G, ch 52~64 */
- {100, 11, 30, BOTH, FALSE}
- , /* 5G, ch 100~140 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Bermuda */
- "BM",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~13 */
- {36, 4, 23, BOTH, FALSE}
- , /* 5G, ch 36~48 */
- {52, 4, 24, BOTH, FALSE}
- , /* 5G, ch 52~64 */
- {100, 11, 30, BOTH, FALSE}
- , /* 5G, ch 100~140 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Brazil */
- "BR",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~13 */
- {36, 4, 23, BOTH, FALSE}
- , /* 5G, ch 36~48 */
- {52, 4, 24, BOTH, FALSE}
- , /* 5G, ch 52~64 */
- {100, 11, 24, BOTH, FALSE}
- , /* 5G, ch 100~140 */
- {149, 5, 30, BOTH, FALSE}
- , /* 5G, ch 100~140 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Belgium */
- "BE",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~13 */
- {36, 4, 18, IDOR, FALSE}
- , /* 5G, ch 36~48 */
- {52, 4, 18, IDOR, FALSE}
- , /* 5G, ch 52~64 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Bulgaria */
- "BG",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~13 */
- {36, 4, 23, IDOR, FALSE}
- , /* 5G, ch 36~48 */
- {52, 4, 23, IDOR, TRUE}
- , /* 5G, ch 52~64 */
- {100, 11, 30, ODOR, TRUE}
- , /* 5G, ch 100~140 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Canada */
- "CA",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~13 */
- {36, 4, 23, BOTH, FALSE}
- , /* 5G, ch 36~48 */
- {52, 4, 23, BOTH, FALSE}
- , /* 5G, ch 52~64 */
- {149, 5, 30, BOTH, FALSE}
- , /* 5G, ch 149~165 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Cayman IsLands */
- "KY",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~13 */
- {36, 4, 23, BOTH, FALSE}
- , /* 5G, ch 36~48 */
- {52, 4, 24, BOTH, FALSE}
- , /* 5G, ch 52~64 */
- {100, 11, 30, BOTH, FALSE}
- , /* 5G, ch 100~140 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Chile */
- "CL",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~13 */
- {36, 4, 20, BOTH, FALSE}
- , /* 5G, ch 36~48 */
- {52, 4, 20, BOTH, FALSE}
- , /* 5G, ch 52~64 */
- {149, 5, 20, BOTH, FALSE}
- , /* 5G, ch 149~165 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* China */
- "CN",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~13 */
- {149, 4, 27, BOTH, FALSE}
- , /* 5G, ch 149~161 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Colombia */
- "CO",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~13 */
- {36, 4, 17, BOTH, FALSE}
- , /* 5G, ch 36~48 */
- {52, 4, 24, BOTH, FALSE}
- , /* 5G, ch 52~64 */
- {100, 11, 30, BOTH, FALSE}
- , /* 5G, ch 100~140 */
- {149, 5, 30, BOTH, FALSE}
- , /* 5G, ch 149~165 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Costa Rica */
- "CR",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~13 */
- {36, 4, 17, BOTH, FALSE}
- , /* 5G, ch 36~48 */
- {52, 4, 24, BOTH, FALSE}
- , /* 5G, ch 52~64 */
- {149, 4, 30, BOTH, FALSE}
- , /* 5G, ch 149~161 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Cyprus */
- "CY",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~13 */
- {36, 4, 23, IDOR, FALSE}
- , /* 5G, ch 36~48 */
- {52, 4, 24, IDOR, TRUE}
- , /* 5G, ch 52~64 */
- {100, 11, 30, BOTH, TRUE}
- , /* 5G, ch 100~140 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Czech_Republic */
- "CZ",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~13 */
- {36, 4, 23, IDOR, FALSE}
- , /* 5G, ch 36~48 */
- {52, 4, 23, IDOR, TRUE}
- , /* 5G, ch 52~64 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Denmark */
- "DK",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~13 */
- {36, 4, 23, IDOR, FALSE}
- , /* 5G, ch 36~48 */
- {52, 4, 23, IDOR, TRUE}
- , /* 5G, ch 52~64 */
- {100, 11, 30, BOTH, TRUE}
- , /* 5G, ch 100~140 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Dominican Republic */
- "DO",
- CE,
- {
- {1, 0, 20, BOTH, FALSE}
- , /* 2.4 G, ch 0 */
- {149, 4, 20, BOTH, FALSE}
- , /* 5G, ch 149~161 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Equador */
- "EC",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~13 */
- {100, 11, 27, BOTH, FALSE}
- , /* 5G, ch 100~140 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* El Salvador */
- "SV",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~13 */
- {36, 4, 23, IDOR, FALSE}
- , /* 5G, ch 36~48 */
- {52, 4, 30, BOTH, TRUE}
- , /* 5G, ch 52~64 */
- {149, 4, 36, BOTH, TRUE}
- , /* 5G, ch 149~165 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Finland */
- "FI",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~13 */
- {36, 4, 23, IDOR, FALSE}
- , /* 5G, ch 36~48 */
- {52, 4, 23, IDOR, TRUE}
- , /* 5G, ch 52~64 */
- {100, 11, 30, BOTH, TRUE}
- , /* 5G, ch 100~140 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* France */
- "FR",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~13 */
- {36, 4, 23, IDOR, FALSE}
- , /* 5G, ch 36~48 */
- {52, 4, 23, IDOR, TRUE}
- , /* 5G, ch 52~64 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Germany */
- "DE",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~13 */
- {36, 4, 23, IDOR, FALSE}
- , /* 5G, ch 36~48 */
- {52, 4, 23, IDOR, TRUE}
- , /* 5G, ch 52~64 */
- {100, 11, 30, BOTH, TRUE}
- , /* 5G, ch 100~140 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Greece */
- "GR",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~13 */
- {36, 4, 23, IDOR, FALSE}
- , /* 5G, ch 36~48 */
- {52, 4, 23, IDOR, TRUE}
- , /* 5G, ch 52~64 */
- {100, 11, 30, ODOR, TRUE}
- , /* 5G, ch 100~140 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Guam */
- "GU",
- CE,
- {
- {1, 11, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~11 */
- {36, 4, 17, BOTH, FALSE}
- , /* 5G, ch 36~48 */
- {52, 4, 24, BOTH, FALSE}
- , /* 5G, ch 52~64 */
- {100, 11, 30, BOTH, FALSE}
- , /* 5G, ch 100~140 */
- {149, 5, 30, BOTH, FALSE}
- , /* 5G, ch 149~165 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Guatemala */
- "GT",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~13 */
- {36, 4, 17, BOTH, FALSE}
- , /* 5G, ch 36~48 */
- {52, 4, 24, BOTH, FALSE}
- , /* 5G, ch 52~64 */
- {149, 4, 30, BOTH, FALSE}
- , /* 5G, ch 149~161 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Haiti */
- "HT",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~13 */
- {36, 4, 17, BOTH, FALSE}
- , /* 5G, ch 36~48 */
- {52, 4, 24, BOTH, FALSE}
- , /* 5G, ch 52~64 */
- {149, 4, 30, BOTH, FALSE}
- , /* 5G, ch 149~161 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Honduras */
- "HN",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~13 */
- {149, 4, 27, BOTH, FALSE}
- , /* 5G, ch 149~161 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Hong Kong */
- "HK",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~13 */
- {36, 4, 23, IDOR, FALSE}
- , /* 5G, ch 36~48 */
- {52, 4, 23, IDOR, FALSE}
- , /* 5G, ch 52~64 */
- {149, 4, 30, BOTH, FALSE}
- , /* 5G, ch 149~161 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Hungary */
- "HU",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~13 */
- {36, 4, 23, IDOR, FALSE}
- , /* 5G, ch 36~48 */
- {52, 4, 23, IDOR, TRUE}
- , /* 5G, ch 52~64 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Iceland */
- "IS",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~13 */
- {36, 4, 23, IDOR, FALSE}
- , /* 5G, ch 36~48 */
- {52, 4, 23, IDOR, TRUE}
- , /* 5G, ch 52~64 */
- {100, 11, 30, BOTH, TRUE}
- , /* 5G, ch 100~140 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* India */
- "IN",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~13 */
- {149, 4, 24, IDOR, FALSE}
- , /* 5G, ch 149~161 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Indonesia */
- "ID",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~13 */
- {149, 4, 27, BOTH, FALSE}
- , /* 5G, ch 149~161 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Ireland */
- "IE",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~13 */
- {36, 4, 23, IDOR, FALSE}
- , /* 5G, ch 36~48 */
- {52, 4, 23, IDOR, TRUE}
- , /* 5G, ch 52~64 */
- {100, 11, 30, ODOR, TRUE}
- , /* 5G, ch 100~140 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Israel */
- "IL",
- CE,
- {
- {1, 3, 20, IDOR, FALSE}
- , /* 2.4 G, ch 1~3 */
- {4, 6, 20, BOTH, FALSE}
- , /* 2.4 G, ch 4~9 */
- {10, 4, 20, IDOR, FALSE}
- , /* 2.4 G, ch 10~13 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Italy */
- "IT",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~13 */
- {36, 4, 23, IDOR, FALSE}
- , /* 5G, ch 36~48 */
- {52, 4, 23, IDOR, TRUE}
- , /* 5G, ch 52~64 */
- {100, 11, 30, ODOR, TRUE}
- , /* 5G, ch 100~140 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Japan */
- "JP",
- JAP,
- {
- {1, 14, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~14 */
- {36, 4, 23, IDOR, FALSE}
- , /* 5G, ch 36~48 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Jordan */
- "JO",
- CE,
- {
- {1, 13, 20, IDOR, FALSE}
- , /* 2.4 G, ch 1~13 */
- {36, 4, 23, IDOR, FALSE}
- , /* 5G, ch 36~48 */
- {149, 4, 23, IDOR, FALSE}
- , /* 5G, ch 149~161 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Latvia */
- "LV",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~13 */
- {36, 4, 23, IDOR, FALSE}
- , /* 5G, ch 36~48 */
- {52, 4, 23, IDOR, TRUE}
- , /* 5G, ch 52~64 */
- {100, 11, 30, BOTH, TRUE}
- , /* 5G, ch 100~140 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Liechtenstein */
- "LI",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~13 */
- {52, 4, 23, IDOR, TRUE}
- , /* 5G, ch 52~64 */
- {100, 11, 30, BOTH, TRUE}
- , /* 5G, ch 100~140 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Lithuania */
- "LT",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~13 */
- {36, 4, 23, IDOR, FALSE}
- , /* 5G, ch 36~48 */
- {52, 4, 23, IDOR, TRUE}
- , /* 5G, ch 52~64 */
- {100, 11, 30, BOTH, TRUE}
- , /* 5G, ch 100~140 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Luxemburg */
- "LU",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~13 */
- {36, 4, 23, IDOR, FALSE}
- , /* 5G, ch 36~48 */
- {52, 4, 23, IDOR, TRUE}
- , /* 5G, ch 52~64 */
- {100, 11, 30, BOTH, TRUE}
- , /* 5G, ch 100~140 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Malaysia */
- "MY",
- CE,
- {
- {36, 4, 23, BOTH, FALSE}
- , /* 5G, ch 36~48 */
- {52, 4, 23, BOTH, FALSE}
- , /* 5G, ch 52~64 */
- {149, 5, 20, BOTH, FALSE}
- , /* 5G, ch 149~165 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Malta */
- "MT",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~13 */
- {36, 4, 23, IDOR, FALSE}
- , /* 5G, ch 36~48 */
- {52, 4, 23, IDOR, TRUE}
- , /* 5G, ch 52~64 */
- {100, 11, 30, BOTH, TRUE}
- , /* 5G, ch 100~140 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Marocco */
- "MA",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~13 */
- {36, 4, 24, IDOR, FALSE}
- , /* 5G, ch 36~48 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Mexico */
- "MX",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~13 */
- {36, 4, 23, BOTH, FALSE}
- , /* 5G, ch 36~48 */
- {52, 4, 24, BOTH, FALSE}
- , /* 5G, ch 52~64 */
- {149, 5, 30, IDOR, FALSE}
- , /* 5G, ch 149~165 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Netherlands */
- "NL",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~13 */
- {36, 4, 23, IDOR, FALSE}
- , /* 5G, ch 36~48 */
- {52, 4, 24, IDOR, TRUE}
- , /* 5G, ch 52~64 */
- {100, 11, 30, BOTH, TRUE}
- , /* 5G, ch 100~140 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* New Zealand */
- "NZ",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~13 */
- {36, 4, 24, BOTH, FALSE}
- , /* 5G, ch 36~48 */
- {52, 4, 24, BOTH, FALSE}
- , /* 5G, ch 52~64 */
- {149, 4, 30, BOTH, FALSE}
- , /* 5G, ch 149~161 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Norway */
- "NO",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~13 */
- {36, 4, 24, IDOR, FALSE}
- , /* 5G, ch 36~48 */
- {52, 4, 24, IDOR, TRUE}
- , /* 5G, ch 52~64 */
- {100, 11, 30, BOTH, TRUE}
- , /* 5G, ch 149~161 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Peru */
- "PE",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~13 */
- {149, 4, 27, BOTH, FALSE}
- , /* 5G, ch 149~161 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Portugal */
- "PT",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~13 */
- {36, 4, 23, IDOR, FALSE}
- , /* 5G, ch 36~48 */
- {52, 4, 23, IDOR, TRUE}
- , /* 5G, ch 52~64 */
- {100, 11, 30, BOTH, TRUE}
- , /* 5G, ch 100~140 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Poland */
- "PL",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~13 */
- {36, 4, 23, IDOR, FALSE}
- , /* 5G, ch 36~48 */
- {52, 4, 23, IDOR, TRUE}
- , /* 5G, ch 52~64 */
- {100, 11, 30, BOTH, TRUE}
- , /* 5G, ch 100~140 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Romania */
- "RO",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~13 */
- {36, 4, 23, IDOR, FALSE}
- , /* 5G, ch 36~48 */
- {52, 4, 23, IDOR, TRUE}
- , /* 5G, ch 52~64 */
- {100, 11, 30, BOTH, TRUE}
- , /* 5G, ch 100~140 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Russia */
- "RU",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~13 */
- {149, 4, 20, IDOR, FALSE}
- , /* 5G, ch 149~161 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Saudi Arabia */
- "SA",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~13 */
- {36, 4, 23, BOTH, FALSE}
- , /* 5G, ch 36~48 */
- {52, 4, 23, BOTH, FALSE}
- , /* 5G, ch 52~64 */
- {149, 4, 23, BOTH, FALSE}
- , /* 5G, ch 149~161 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Serbia_and_Montenegro */
- "CS",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~13 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Singapore */
- "SG",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~13 */
- {36, 4, 23, BOTH, FALSE}
- , /* 5G, ch 36~48 */
- {52, 4, 23, BOTH, FALSE}
- , /* 5G, ch 52~64 */
- {149, 4, 20, BOTH, FALSE}
- , /* 5G, ch 149~161 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Slovakia */
- "SK",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~13 */
- {36, 4, 23, IDOR, FALSE}
- , /* 5G, ch 36~48 */
- {52, 4, 23, IDOR, TRUE}
- , /* 5G, ch 52~64 */
- {100, 11, 30, BOTH, TRUE}
- , /* 5G, ch 100~140 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Slovenia */
- "SI",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~13 */
- {36, 4, 23, IDOR, FALSE}
- , /* 5G, ch 36~48 */
- {52, 4, 23, IDOR, TRUE}
- , /* 5G, ch 52~64 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* South Africa */
- "ZA",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~13 */
- {36, 4, 23, BOTH, FALSE}
- , /* 5G, ch 36~48 */
- {52, 4, 23, IDOR, FALSE}
- , /* 5G, ch 52~64 */
- {100, 11, 30, BOTH, TRUE}
- , /* 5G, ch 100~140 */
- {149, 4, 30, BOTH, FALSE}
- , /* 5G, ch 149~161 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* South Korea */
- "KR",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~13 */
- {36, 4, 20, BOTH, FALSE}
- , /* 5G, ch 36~48 */
- {52, 4, 20, BOTH, FALSE}
- , /* 5G, ch 52~64 */
- {100, 8, 20, BOTH, FALSE}
- , /* 5G, ch 100~128 */
- {149, 4, 20, BOTH, FALSE}
- , /* 5G, ch 149~161 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Spain */
- "ES",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~13 */
- {36, 4, 17, IDOR, FALSE}
- , /* 5G, ch 36~48 */
- {52, 4, 23, IDOR, TRUE}
- , /* 5G, ch 52~64 */
- {100, 11, 30, BOTH, TRUE}
- , /* 5G, ch 100~140 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Sweden */
- "SE",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~13 */
- {36, 4, 23, IDOR, FALSE}
- , /* 5G, ch 36~48 */
- {52, 4, 23, IDOR, TRUE}
- , /* 5G, ch 52~64 */
- {100, 11, 30, BOTH, TRUE}
- , /* 5G, ch 100~140 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Switzerland */
- "CH",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~13 */
- {36, 4, 23, IDOR, TRUE}
- , /* 5G, ch 36~48 */
- {52, 4, 23, IDOR, TRUE}
- , /* 5G, ch 52~64 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Taiwan */
- "TW",
- CE,
- {
- {1, 11, 30, BOTH, FALSE}
- , /* 2.4 G, ch 1~11 */
- {52, 4, 23, IDOR, FALSE}
- , /* 5G, ch 52~64 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Turkey */
- "TR",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~11 */
- {36, 4, 23, BOTH, FALSE}
- , /* 5G, ch 36~48 */
- {52, 4, 23, BOTH, FALSE}
- , /* 5G, ch 52~64 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* UK */
- "GB",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~11 */
- {36, 4, 23, IDOR, FALSE}
- , /* 5G, ch 52~64 */
- {52, 4, 23, IDOR, TRUE}
- , /* 5G, ch 52~64 */
- {100, 11, 30, BOTH, TRUE}
- , /* 5G, ch 100~140 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Ukraine */
- "UA",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~11 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* United_Arab_Emirates */
- "AE",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~11 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* United_States */
- "US",
- CE,
- {
- {1, 11, 30, BOTH, FALSE}
- , /* 2.4 G, ch 1~11 */
- {36, 4, 17, IDOR, FALSE}
- , /* 5G, ch 52~64 */
- {52, 4, 24, BOTH, TRUE}
- , /* 5G, ch 52~64 */
- {100, 11, 30, BOTH, TRUE}
- , /* 5G, ch 100~140 */
- {149, 5, 30, BOTH, FALSE}
- , /* 5G, ch 149~165 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Venezuela */
- "VE",
- CE,
- {
- {1, 13, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~11 */
- {149, 4, 27, BOTH, FALSE}
- , /* 5G, ch 149~161 */
- {0}
- , /* end */
- }
- }
- ,
-
- { /* Default */
- "",
- CE,
- {
- {1, 11, 20, BOTH, FALSE}
- , /* 2.4 G, ch 1~11 */
- {36, 4, 20, BOTH, FALSE}
- , /* 5G, ch 52~64 */
- {52, 4, 20, BOTH, FALSE}
- , /* 5G, ch 52~64 */
- {100, 11, 20, BOTH, FALSE}
- , /* 5G, ch 100~140 */
- {149, 5, 20, BOTH, FALSE}
- , /* 5G, ch 149~165 */
- {0}
- , /* end */
- }
- }
- ,
-};
-
-static struct rt_ch_region *GetChRegion(u8 *CntryCode)
-{
- int loop = 0;
- struct rt_ch_region *pChRegion = NULL;
-
- while (strcmp((char *)ChRegion[loop].CountReg, "") != 0) {
- if (strncmp
- ((char *)ChRegion[loop].CountReg, (char *)CntryCode,
- 2) == 0) {
- pChRegion = &ChRegion[loop];
- break;
- }
- loop++;
- }
-
- if (pChRegion == NULL)
- pChRegion = &ChRegion[loop];
- return pChRegion;
-}
-
-static void ChBandCheck(u8 PhyMode, u8 *pChType)
-{
- switch (PhyMode) {
- case PHY_11A:
- case PHY_11AN_MIXED:
- *pChType = BAND_5G;
- break;
- case PHY_11ABG_MIXED:
- case PHY_11AGN_MIXED:
- case PHY_11ABGN_MIXED:
- *pChType = BAND_BOTH;
- break;
-
- default:
- *pChType = BAND_24G;
- break;
- }
-}
-
-static u8 FillChList(struct rt_rtmp_adapter *pAd,
- struct rt_ch_desp *pChDesp,
- u8 Offset, u8 increment)
-{
- int i, j, l;
- u8 channel;
-
- j = Offset;
- for (i = 0; i < pChDesp->NumOfCh; i++) {
- channel = pChDesp->FirstChannel + i * increment;
- for (l = 0; l < MAX_NUM_OF_CHANNELS; l++) {
- if (channel == pAd->TxPower[l].Channel) {
- pAd->ChannelList[j].Power =
- pAd->TxPower[l].Power;
- pAd->ChannelList[j].Power2 =
- pAd->TxPower[l].Power2;
- break;
- }
- }
- if (l == MAX_NUM_OF_CHANNELS)
- continue;
-
- pAd->ChannelList[j].Channel =
- pChDesp->FirstChannel + i * increment;
- pAd->ChannelList[j].MaxTxPwr = pChDesp->MaxTxPwr;
- pAd->ChannelList[j].DfsReq = pChDesp->DfsReq;
- j++;
- }
- pAd->ChannelListNum = j;
-
- return j;
-}
-
-static inline void CreateChList(struct rt_rtmp_adapter *pAd,
- struct rt_ch_region *pChRegion, u8 Geography)
-{
- int i;
- u8 offset = 0;
- struct rt_ch_desp *pChDesp;
- u8 ChType;
- u8 increment;
-
- if (pChRegion == NULL)
- return;
-
- ChBandCheck(pAd->CommonCfg.PhyMode, &ChType);
-
- for (i = 0; i < 10; i++) {
- pChDesp = &pChRegion->ChDesp[i];
- if (pChDesp->FirstChannel == 0)
- break;
-
- if (ChType == BAND_5G) {
- if (pChDesp->FirstChannel <= 14)
- continue;
- } else if (ChType == BAND_24G) {
- if (pChDesp->FirstChannel > 14)
- continue;
- }
-
- if ((pChDesp->Geography == BOTH)
- || (pChDesp->Geography == Geography)) {
- if (pChDesp->FirstChannel > 14)
- increment = 4;
- else
- increment = 1;
- offset = FillChList(pAd, pChDesp, offset, increment);
- }
- }
-}
-
-void BuildChannelListEx(struct rt_rtmp_adapter *pAd)
-{
- struct rt_ch_region *pChReg;
-
- pChReg = GetChRegion(pAd->CommonCfg.CountryCode);
- CreateChList(pAd, pChReg, pAd->CommonCfg.Geography);
-}
-
-void BuildBeaconChList(struct rt_rtmp_adapter *pAd,
- u8 *pBuf, unsigned long *pBufLen)
-{
- int i;
- unsigned long TmpLen;
- struct rt_ch_region *pChRegion;
- struct rt_ch_desp *pChDesp;
- u8 ChType;
-
- pChRegion = GetChRegion(pAd->CommonCfg.CountryCode);
-
- if (pChRegion == NULL)
- return;
-
- ChBandCheck(pAd->CommonCfg.PhyMode, &ChType);
- *pBufLen = 0;
-
- for (i = 0; i < 10; i++) {
- pChDesp = &pChRegion->ChDesp[i];
- if (pChDesp->FirstChannel == 0)
- break;
-
- if (ChType == BAND_5G) {
- if (pChDesp->FirstChannel <= 14)
- continue;
- } else if (ChType == BAND_24G) {
- if (pChDesp->FirstChannel > 14)
- continue;
- }
-
- if ((pChDesp->Geography == BOTH)
- || (pChDesp->Geography == pAd->CommonCfg.Geography)) {
- MakeOutgoingFrame(pBuf + *pBufLen, &TmpLen,
- 1, &pChDesp->FirstChannel,
- 1, &pChDesp->NumOfCh,
- 1, &pChDesp->MaxTxPwr, END_OF_ARGS);
- *pBufLen += TmpLen;
- }
- }
-}
-
-static BOOLEAN IsValidChannel(struct rt_rtmp_adapter *pAd, u8 channel)
-{
- int i;
-
- for (i = 0; i < pAd->ChannelListNum; i++) {
- if (pAd->ChannelList[i].Channel == channel)
- break;
- }
-
- if (i == pAd->ChannelListNum)
- return FALSE;
- else
- return TRUE;
-}
-
-static u8 GetExtCh(u8 Channel, u8 Direction)
-{
- char ExtCh;
-
- if (Direction == EXTCHA_ABOVE)
- ExtCh = Channel + 4;
- else
- ExtCh = (Channel - 4) > 0 ? (Channel - 4) : 0;
-
- return ExtCh;
-}
-
-void N_ChannelCheck(struct rt_rtmp_adapter *pAd)
-{
- /*u8 ChannelNum = pAd->ChannelListNum; */
- u8 Channel = pAd->CommonCfg.Channel;
-
- if ((pAd->CommonCfg.PhyMode >= PHY_11ABGN_MIXED)
- && (pAd->CommonCfg.RegTransmitSetting.field.BW == BW_40)) {
- if (Channel > 14) {
- if ((Channel == 36) || (Channel == 44)
- || (Channel == 52) || (Channel == 60)
- || (Channel == 100) || (Channel == 108)
- || (Channel == 116) || (Channel == 124)
- || (Channel == 132) || (Channel == 149)
- || (Channel == 157)) {
- pAd->CommonCfg.RegTransmitSetting.field.EXTCHA =
- EXTCHA_ABOVE;
- } else if ((Channel == 40) || (Channel == 48)
- || (Channel == 56) || (Channel == 64)
- || (Channel == 104) || (Channel == 112)
- || (Channel == 120) || (Channel == 128)
- || (Channel == 136) || (Channel == 153)
- || (Channel == 161)) {
- pAd->CommonCfg.RegTransmitSetting.field.EXTCHA =
- EXTCHA_BELOW;
- } else {
- pAd->CommonCfg.RegTransmitSetting.field.BW =
- BW_20;
- }
- } else {
- do {
- u8 ExtCh;
- u8 Dir =
- pAd->CommonCfg.RegTransmitSetting.field.
- EXTCHA;
- ExtCh = GetExtCh(Channel, Dir);
- if (IsValidChannel(pAd, ExtCh))
- break;
-
- Dir =
- (Dir ==
- EXTCHA_ABOVE) ? EXTCHA_BELOW :
- EXTCHA_ABOVE;
- ExtCh = GetExtCh(Channel, Dir);
- if (IsValidChannel(pAd, ExtCh)) {
- pAd->CommonCfg.RegTransmitSetting.field.
- EXTCHA = Dir;
- break;
- }
- pAd->CommonCfg.RegTransmitSetting.field.BW =
- BW_20;
- } while (FALSE);
-
- if (Channel == 14) {
- pAd->CommonCfg.RegTransmitSetting.field.BW =
- BW_20;
- /*pAd->CommonCfg.RegTransmitSetting.field.EXTCHA = EXTCHA_NONE; // We didn't set the ExtCh as NONE due to it'll set in RTMPSetHT() */
- }
- }
- }
-
-}
-
-void N_SetCenCh(struct rt_rtmp_adapter *pAd)
-{
- if (pAd->CommonCfg.RegTransmitSetting.field.BW == BW_40) {
- if (pAd->CommonCfg.RegTransmitSetting.field.EXTCHA ==
- EXTCHA_ABOVE) {
- pAd->CommonCfg.CentralChannel =
- pAd->CommonCfg.Channel + 2;
- } else {
- if (pAd->CommonCfg.Channel == 14)
- pAd->CommonCfg.CentralChannel =
- pAd->CommonCfg.Channel - 1;
- else
- pAd->CommonCfg.CentralChannel =
- pAd->CommonCfg.Channel - 2;
- }
- } else {
- pAd->CommonCfg.CentralChannel = pAd->CommonCfg.Channel;
- }
-}
-
-u8 GetCuntryMaxTxPwr(struct rt_rtmp_adapter *pAd, u8 channel)
-{
- int i;
- for (i = 0; i < pAd->ChannelListNum; i++) {
- if (pAd->ChannelList[i].Channel == channel)
- break;
- }
-
- if (i == pAd->ChannelListNum)
- return 0xff;
- else
- return pAd->ChannelList[i].MaxTxPwr;
-}
diff --git a/drivers/staging/rt2860/common/rt_rf.c b/drivers/staging/rt2860/common/rt_rf.c
deleted file mode 100644
index 2895447..0000000
--- a/drivers/staging/rt2860/common/rt_rf.c
+++ /dev/null
@@ -1,187 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- rt_rf.c
-
- Abstract:
- Ralink Wireless driver RF related functions
-
- Revision History:
- Who When What
- -------- ---------- ----------------------------------------------
-*/
-
-#include "../rt_config.h"
-
-#ifdef RTMP_RF_RW_SUPPORT
-/*
- ========================================================================
-
- Routine Description: Write RT30xx RF register through MAC
-
- Arguments:
-
- Return Value:
-
- IRQL =
-
- Note:
-
- ========================================================================
-*/
-int RT30xxWriteRFRegister(struct rt_rtmp_adapter *pAd,
- u8 regID, u8 value)
-{
- RF_CSR_CFG_STRUC rfcsr;
- u32 i = 0;
-
- do {
- RTMP_IO_READ32(pAd, RF_CSR_CFG, &rfcsr.word);
-
- if (!rfcsr.field.RF_CSR_KICK)
- break;
- i++;
- }
- while ((i < RETRY_LIMIT)
- && (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST)));
-
- if ((i == RETRY_LIMIT)
- || (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST))) {
- DBGPRINT_RAW(RT_DEBUG_ERROR,
- ("Retry count exhausted or device removed!\n"));
- return STATUS_UNSUCCESSFUL;
- }
-
- rfcsr.field.RF_CSR_WR = 1;
- rfcsr.field.RF_CSR_KICK = 1;
- rfcsr.field.TESTCSR_RFACC_REGNUM = regID;
- rfcsr.field.RF_CSR_DATA = value;
-
- RTMP_IO_WRITE32(pAd, RF_CSR_CFG, rfcsr.word);
-
- return NDIS_STATUS_SUCCESS;
-}
-
-/*
- ========================================================================
-
- Routine Description: Read RT30xx RF register through MAC
-
- Arguments:
-
- Return Value:
-
- IRQL =
-
- Note:
-
- ========================================================================
-*/
-int RT30xxReadRFRegister(struct rt_rtmp_adapter *pAd,
- u8 regID, u8 *pValue)
-{
- RF_CSR_CFG_STRUC rfcsr;
- u32 i = 0, k = 0;
-
- for (i = 0; i < MAX_BUSY_COUNT; i++) {
- RTMP_IO_READ32(pAd, RF_CSR_CFG, &rfcsr.word);
-
- if (rfcsr.field.RF_CSR_KICK == BUSY) {
- continue;
- }
- rfcsr.word = 0;
- rfcsr.field.RF_CSR_WR = 0;
- rfcsr.field.RF_CSR_KICK = 1;
- rfcsr.field.TESTCSR_RFACC_REGNUM = regID;
- RTMP_IO_WRITE32(pAd, RF_CSR_CFG, rfcsr.word);
- for (k = 0; k < MAX_BUSY_COUNT; k++) {
- RTMP_IO_READ32(pAd, RF_CSR_CFG, &rfcsr.word);
-
- if (rfcsr.field.RF_CSR_KICK == IDLE)
- break;
- }
- if ((rfcsr.field.RF_CSR_KICK == IDLE) &&
- (rfcsr.field.TESTCSR_RFACC_REGNUM == regID)) {
- *pValue = (u8)rfcsr.field.RF_CSR_DATA;
- break;
- }
- }
- if (rfcsr.field.RF_CSR_KICK == BUSY) {
- DBGPRINT_ERR("RF read R%d=0x%x fail, i[%d], k[%d]\n", regID, rfcsr.word, i, k);
- return STATUS_UNSUCCESSFUL;
- }
-
- return STATUS_SUCCESS;
-}
-
-void NICInitRFRegisters(struct rt_rtmp_adapter *pAd)
-{
- if (pAd->chipOps.AsicRfInit)
- pAd->chipOps.AsicRfInit(pAd);
-}
-
-void RtmpChipOpsRFHook(struct rt_rtmp_adapter *pAd)
-{
- struct rt_rtmp_chip_op *pChipOps = &pAd->chipOps;
-
- pChipOps->pRFRegTable = NULL;
- pChipOps->AsicRfInit = NULL;
- pChipOps->AsicRfTurnOn = NULL;
- pChipOps->AsicRfTurnOff = NULL;
- pChipOps->AsicReverseRfFromSleepMode = NULL;
- pChipOps->AsicHaltAction = NULL;
- /* We depends on RfICType and MACVersion to assign the corresponding operation callbacks. */
-
-#ifdef RT30xx
- if (IS_RT30xx(pAd)) {
- pChipOps->pRFRegTable = RT30xx_RFRegTable;
- pChipOps->AsicHaltAction = RT30xxHaltAction;
-#ifdef RT3070
- if ((IS_RT3070(pAd) || IS_RT3071(pAd))
- && (pAd->infType == RTMP_DEV_INF_USB)) {
- pChipOps->AsicRfInit = NICInitRT3070RFRegisters;
- if (IS_RT3071(pAd)) {
- pChipOps->AsicRfTurnOff =
- RT30xxLoadRFSleepModeSetup;
- pChipOps->AsicReverseRfFromSleepMode =
- RT30xxReverseRFSleepModeSetup;
- }
- }
-#endif /* RT3070 // */
-#ifdef RT3090
- if (IS_RT3090(pAd) && (pAd->infType == RTMP_DEV_INF_PCI)) {
- pChipOps->AsicRfTurnOff = RT30xxLoadRFSleepModeSetup;
- pChipOps->AsicRfInit = NICInitRT3090RFRegisters;
- pChipOps->AsicReverseRfFromSleepMode =
- RT30xxReverseRFSleepModeSetup;
- }
-#endif /* RT3090 // */
- }
-#endif /* RT30xx // */
-}
-
-#endif /* RTMP_RF_RW_SUPPORT // */
diff --git a/drivers/staging/rt2860/common/rtmp_init.c b/drivers/staging/rt2860/common/rtmp_init.c
deleted file mode 100644
index 5fa193e..0000000
--- a/drivers/staging/rt2860/common/rtmp_init.c
+++ /dev/null
@@ -1,3536 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- rtmp_init.c
-
- Abstract:
- Miniport generic portion header file
-
- Revision History:
- Who When What
- -------- ---------- ----------------------------------------------
-*/
-#include "../rt_config.h"
-
-u8 BIT8[] = { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 };
-char *CipherName[] =
- { "none", "wep64", "wep128", "TKIP", "AES", "CKIP64", "CKIP128" };
-
-/* */
-/* BBP register initialization set */
-/* */
-struct rt_reg_pair BBPRegTable[] = {
- {BBP_R65, 0x2C}, /* fix rssi issue */
- {BBP_R66, 0x38}, /* Also set this default value to pAd->BbpTuning.R66CurrentValue at initial */
- {BBP_R69, 0x12},
- {BBP_R70, 0xa}, /* BBP_R70 will change to 0x8 in ApStartUp and LinkUp for rt2860C, otherwise value is 0xa */
- {BBP_R73, 0x10},
- {BBP_R81, 0x37},
- {BBP_R82, 0x62},
- {BBP_R83, 0x6A},
- {BBP_R84, 0x99}, /* 0x19 is for rt2860E and after. This is for extension channel overlapping IOT. 0x99 is for rt2860D and before */
- {BBP_R86, 0x00}, /* middle range issue, Rory @2008-01-28 */
- {BBP_R91, 0x04}, /* middle range issue, Rory @2008-01-28 */
- {BBP_R92, 0x00}, /* middle range issue, Rory @2008-01-28 */
- {BBP_R103, 0x00}, /* near range high-power issue, requested from Gary @2008-0528 */
- {BBP_R105, 0x05}, /* 0x05 is for rt2860E to turn on FEQ control. It is safe for rt2860D and before, because Bit 7:2 are reserved in rt2860D and before. */
- {BBP_R106, 0x35}, /* for ShortGI throughput */
-};
-
-#define NUM_BBP_REG_PARMS (sizeof(BBPRegTable) / sizeof(struct rt_reg_pair))
-
-/* */
-/* ASIC register initialization sets */
-/* */
-
-struct rt_rtmp_reg_pair MACRegTable[] = {
-#if defined(HW_BEACON_OFFSET) && (HW_BEACON_OFFSET == 0x200)
- {BCN_OFFSET0, 0xf8f0e8e0}, /* 0x3800(e0), 0x3A00(e8), 0x3C00(f0), 0x3E00(f8), 512B for each beacon */
- {BCN_OFFSET1, 0x6f77d0c8}, /* 0x3200(c8), 0x3400(d0), 0x1DC0(77), 0x1BC0(6f), 512B for each beacon */
-#elif defined(HW_BEACON_OFFSET) && (HW_BEACON_OFFSET == 0x100)
- {BCN_OFFSET0, 0xece8e4e0}, /* 0x3800, 0x3A00, 0x3C00, 0x3E00, 512B for each beacon */
- {BCN_OFFSET1, 0xfcf8f4f0}, /* 0x3800, 0x3A00, 0x3C00, 0x3E00, 512B for each beacon */
-#else
-#error You must re-calculate new value for BCN_OFFSET0 & BCN_OFFSET1 in MACRegTable[]!
-#endif /* HW_BEACON_OFFSET // */
-
- {LEGACY_BASIC_RATE, 0x0000013f}, /* Basic rate set bitmap */
- {HT_BASIC_RATE, 0x00008003}, /* Basic HT rate set , 20M, MCS=3, MM. Format is the same as in TXWI. */
- {MAC_SYS_CTRL, 0x00}, /* 0x1004, , default Disable RX */
- {RX_FILTR_CFG, 0x17f97}, /*0x1400 , RX filter control, */
- {BKOFF_SLOT_CFG, 0x209}, /* default set short slot time, CC_DELAY_TIME should be 2 */
- /*{TX_SW_CFG0, 0x40a06}, // Gary,2006-08-23 */
- {TX_SW_CFG0, 0x0}, /* Gary,2008-05-21 for CWC test */
- {TX_SW_CFG1, 0x80606}, /* Gary,2006-08-23 */
- {TX_LINK_CFG, 0x1020}, /* Gary,2006-08-23 */
- /*{TX_TIMEOUT_CFG, 0x00182090}, // CCK has some problem. So increase timieout value. 2006-10-09// MArvek RT */
- {TX_TIMEOUT_CFG, 0x000a2090}, /* CCK has some problem. So increase timieout value. 2006-10-09// MArvek RT , Modify for 2860E ,2007-08-01 */
- {MAX_LEN_CFG, MAX_AGGREGATION_SIZE | 0x00001000}, /* 0x3018, MAX frame length. Max PSDU = 16kbytes. */
- {LED_CFG, 0x7f031e46}, /* Gary, 2006-08-23 */
-
- {PBF_MAX_PCNT, 0x1F3FBF9F}, /*0x1F3f7f9f}, //Jan, 2006/04/20 */
-
- {TX_RTY_CFG, 0x47d01f0f}, /* Jan, 2006/11/16, Set TxWI->ACK =0 in Probe Rsp Modify for 2860E ,2007-08-03 */
-
- {AUTO_RSP_CFG, 0x00000013}, /* Initial Auto_Responder, because QA will turn off Auto-Responder */
- {CCK_PROT_CFG, 0x05740003 /*0x01740003 */ }, /* Initial Auto_Responder, because QA will turn off Auto-Responder. And RTS threshold is enabled. */
- {OFDM_PROT_CFG, 0x05740003 /*0x01740003 */ }, /* Initial Auto_Responder, because QA will turn off Auto-Responder. And RTS threshold is enabled. */
-#ifdef RTMP_MAC_USB
- {PBF_CFG, 0xf40006}, /* Only enable Queue 2 */
- {MM40_PROT_CFG, 0x3F44084}, /* Initial Auto_Responder, because QA will turn off Auto-Responder */
- {WPDMA_GLO_CFG, 0x00000030},
-#endif /* RTMP_MAC_USB // */
- {GF20_PROT_CFG, 0x01744004}, /* set 19:18 --> Short NAV for MIMO PS */
- {GF40_PROT_CFG, 0x03F44084},
- {MM20_PROT_CFG, 0x01744004},
-#ifdef RTMP_MAC_PCI
- {MM40_PROT_CFG, 0x03F54084},
-#endif /* RTMP_MAC_PCI // */
- {TXOP_CTRL_CFG, 0x0000583f, /*0x0000243f *//*0x000024bf */ }, /*Extension channel backoff. */
- {TX_RTS_CFG, 0x00092b20},
- {EXP_ACK_TIME, 0x002400ca}, /* default value */
-
- {TXOP_HLDR_ET, 0x00000002},
-
- /* Jerry comments 2008/01/16: we use SIFS = 10us in CCK defaultly, but it seems that 10us
- is too small for INTEL 2200bg card, so in MBSS mode, the delta time between beacon0
- and beacon1 is SIFS (10us), so if INTEL 2200bg card connects to BSS0, the ping
- will always lost. So we change the SIFS of CCK from 10us to 16us. */
- {XIFS_TIME_CFG, 0x33a41010},
- {PWR_PIN_CFG, 0x00000003}, /* patch for 2880-E */
-};
-
-struct rt_rtmp_reg_pair STAMACRegTable[] = {
- {WMM_AIFSN_CFG, 0x00002273},
- {WMM_CWMIN_CFG, 0x00002344},
- {WMM_CWMAX_CFG, 0x000034aa},
-};
-
-#define NUM_MAC_REG_PARMS (sizeof(MACRegTable) / sizeof(struct rt_rtmp_reg_pair))
-#define NUM_STA_MAC_REG_PARMS (sizeof(STAMACRegTable) / sizeof(struct rt_rtmp_reg_pair))
-
-/*
- ========================================================================
-
- Routine Description:
- Allocate struct rt_rtmp_adapter data block and do some initialization
-
- Arguments:
- Adapter Pointer to our adapter
-
- Return Value:
- NDIS_STATUS_SUCCESS
- NDIS_STATUS_FAILURE
-
- IRQL = PASSIVE_LEVEL
-
- Note:
-
- ========================================================================
-*/
-int RTMPAllocAdapterBlock(void *handle,
- struct rt_rtmp_adapter * * ppAdapter)
-{
- struct rt_rtmp_adapter *pAd;
- int Status;
- int index;
- u8 *pBeaconBuf = NULL;
-
- DBGPRINT(RT_DEBUG_TRACE, ("--> RTMPAllocAdapterBlock\n"));
-
- *ppAdapter = NULL;
-
- do {
- /* Allocate struct rt_rtmp_adapter memory block */
- pBeaconBuf = kmalloc(MAX_BEACON_SIZE, MEM_ALLOC_FLAG);
- if (pBeaconBuf == NULL) {
- Status = NDIS_STATUS_FAILURE;
- DBGPRINT_ERR("Failed to allocate memory - BeaconBuf!\n");
- break;
- }
- NdisZeroMemory(pBeaconBuf, MAX_BEACON_SIZE);
-
- Status = AdapterBlockAllocateMemory(handle, (void **) & pAd);
- if (Status != NDIS_STATUS_SUCCESS) {
- DBGPRINT_ERR("Failed to allocate memory - ADAPTER\n");
- break;
- }
- pAd->BeaconBuf = pBeaconBuf;
- DBGPRINT(RT_DEBUG_OFF,
- ("=== pAd = %p, size = %d ===\n", pAd,
- (u32)sizeof(struct rt_rtmp_adapter)));
-
- /* Init spin locks */
- NdisAllocateSpinLock(&pAd->MgmtRingLock);
-#ifdef RTMP_MAC_PCI
- NdisAllocateSpinLock(&pAd->RxRingLock);
-#ifdef RT3090
- NdisAllocateSpinLock(&pAd->McuCmdLock);
-#endif /* RT3090 // */
-#endif /* RTMP_MAC_PCI // */
-
- for (index = 0; index < NUM_OF_TX_RING; index++) {
- NdisAllocateSpinLock(&pAd->TxSwQueueLock[index]);
- NdisAllocateSpinLock(&pAd->DeQueueLock[index]);
- pAd->DeQueueRunning[index] = FALSE;
- }
-
- NdisAllocateSpinLock(&pAd->irq_lock);
-
- } while (FALSE);
-
- if ((Status != NDIS_STATUS_SUCCESS) && (pBeaconBuf))
- kfree(pBeaconBuf);
-
- *ppAdapter = pAd;
-
- DBGPRINT_S(Status, ("<-- RTMPAllocAdapterBlock, Status=%x\n", Status));
- return Status;
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Read initial Tx power per MCS and BW from EEPROM
-
- Arguments:
- Adapter Pointer to our adapter
-
- Return Value:
- None
-
- IRQL = PASSIVE_LEVEL
-
- Note:
-
- ========================================================================
-*/
-void RTMPReadTxPwrPerRate(struct rt_rtmp_adapter *pAd)
-{
- unsigned long data, Adata, Gdata;
- u16 i, value, value2;
- int Apwrdelta, Gpwrdelta;
- u8 t1, t2, t3, t4;
- BOOLEAN bApwrdeltaMinus = TRUE, bGpwrdeltaMinus = TRUE;
-
- /* */
- /* Get power delta for 20MHz and 40MHz. */
- /* */
- DBGPRINT(RT_DEBUG_TRACE, ("Txpower per Rate\n"));
- RT28xx_EEPROM_READ16(pAd, EEPROM_TXPOWER_DELTA, value2);
- Apwrdelta = 0;
- Gpwrdelta = 0;
-
- if ((value2 & 0xff) != 0xff) {
- if ((value2 & 0x80))
- Gpwrdelta = (value2 & 0xf);
-
- if ((value2 & 0x40))
- bGpwrdeltaMinus = FALSE;
- else
- bGpwrdeltaMinus = TRUE;
- }
- if ((value2 & 0xff00) != 0xff00) {
- if ((value2 & 0x8000))
- Apwrdelta = ((value2 & 0xf00) >> 8);
-
- if ((value2 & 0x4000))
- bApwrdeltaMinus = FALSE;
- else
- bApwrdeltaMinus = TRUE;
- }
- DBGPRINT(RT_DEBUG_TRACE,
- ("Gpwrdelta = %x, Apwrdelta = %x .\n", Gpwrdelta, Apwrdelta));
-
- /* */
- /* Get Txpower per MCS for 20MHz in 2.4G. */
- /* */
- for (i = 0; i < 5; i++) {
- RT28xx_EEPROM_READ16(pAd,
- EEPROM_TXPOWER_BYRATE_20MHZ_2_4G + i * 4,
- value);
- data = value;
- if (bApwrdeltaMinus == FALSE) {
- t1 = (value & 0xf) + (Apwrdelta);
- if (t1 > 0xf)
- t1 = 0xf;
- t2 = ((value & 0xf0) >> 4) + (Apwrdelta);
- if (t2 > 0xf)
- t2 = 0xf;
- t3 = ((value & 0xf00) >> 8) + (Apwrdelta);
- if (t3 > 0xf)
- t3 = 0xf;
- t4 = ((value & 0xf000) >> 12) + (Apwrdelta);
- if (t4 > 0xf)
- t4 = 0xf;
- } else {
- if ((value & 0xf) > Apwrdelta)
- t1 = (value & 0xf) - (Apwrdelta);
- else
- t1 = 0;
- if (((value & 0xf0) >> 4) > Apwrdelta)
- t2 = ((value & 0xf0) >> 4) - (Apwrdelta);
- else
- t2 = 0;
- if (((value & 0xf00) >> 8) > Apwrdelta)
- t3 = ((value & 0xf00) >> 8) - (Apwrdelta);
- else
- t3 = 0;
- if (((value & 0xf000) >> 12) > Apwrdelta)
- t4 = ((value & 0xf000) >> 12) - (Apwrdelta);
- else
- t4 = 0;
- }
- Adata = t1 + (t2 << 4) + (t3 << 8) + (t4 << 12);
- if (bGpwrdeltaMinus == FALSE) {
- t1 = (value & 0xf) + (Gpwrdelta);
- if (t1 > 0xf)
- t1 = 0xf;
- t2 = ((value & 0xf0) >> 4) + (Gpwrdelta);
- if (t2 > 0xf)
- t2 = 0xf;
- t3 = ((value & 0xf00) >> 8) + (Gpwrdelta);
- if (t3 > 0xf)
- t3 = 0xf;
- t4 = ((value & 0xf000) >> 12) + (Gpwrdelta);
- if (t4 > 0xf)
- t4 = 0xf;
- } else {
- if ((value & 0xf) > Gpwrdelta)
- t1 = (value & 0xf) - (Gpwrdelta);
- else
- t1 = 0;
- if (((value & 0xf0) >> 4) > Gpwrdelta)
- t2 = ((value & 0xf0) >> 4) - (Gpwrdelta);
- else
- t2 = 0;
- if (((value & 0xf00) >> 8) > Gpwrdelta)
- t3 = ((value & 0xf00) >> 8) - (Gpwrdelta);
- else
- t3 = 0;
- if (((value & 0xf000) >> 12) > Gpwrdelta)
- t4 = ((value & 0xf000) >> 12) - (Gpwrdelta);
- else
- t4 = 0;
- }
- Gdata = t1 + (t2 << 4) + (t3 << 8) + (t4 << 12);
-
- RT28xx_EEPROM_READ16(pAd,
- EEPROM_TXPOWER_BYRATE_20MHZ_2_4G + i * 4 +
- 2, value);
- if (bApwrdeltaMinus == FALSE) {
- t1 = (value & 0xf) + (Apwrdelta);
- if (t1 > 0xf)
- t1 = 0xf;
- t2 = ((value & 0xf0) >> 4) + (Apwrdelta);
- if (t2 > 0xf)
- t2 = 0xf;
- t3 = ((value & 0xf00) >> 8) + (Apwrdelta);
- if (t3 > 0xf)
- t3 = 0xf;
- t4 = ((value & 0xf000) >> 12) + (Apwrdelta);
- if (t4 > 0xf)
- t4 = 0xf;
- } else {
- if ((value & 0xf) > Apwrdelta)
- t1 = (value & 0xf) - (Apwrdelta);
- else
- t1 = 0;
- if (((value & 0xf0) >> 4) > Apwrdelta)
- t2 = ((value & 0xf0) >> 4) - (Apwrdelta);
- else
- t2 = 0;
- if (((value & 0xf00) >> 8) > Apwrdelta)
- t3 = ((value & 0xf00) >> 8) - (Apwrdelta);
- else
- t3 = 0;
- if (((value & 0xf000) >> 12) > Apwrdelta)
- t4 = ((value & 0xf000) >> 12) - (Apwrdelta);
- else
- t4 = 0;
- }
- Adata |= ((t1 << 16) + (t2 << 20) + (t3 << 24) + (t4 << 28));
- if (bGpwrdeltaMinus == FALSE) {
- t1 = (value & 0xf) + (Gpwrdelta);
- if (t1 > 0xf)
- t1 = 0xf;
- t2 = ((value & 0xf0) >> 4) + (Gpwrdelta);
- if (t2 > 0xf)
- t2 = 0xf;
- t3 = ((value & 0xf00) >> 8) + (Gpwrdelta);
- if (t3 > 0xf)
- t3 = 0xf;
- t4 = ((value & 0xf000) >> 12) + (Gpwrdelta);
- if (t4 > 0xf)
- t4 = 0xf;
- } else {
- if ((value & 0xf) > Gpwrdelta)
- t1 = (value & 0xf) - (Gpwrdelta);
- else
- t1 = 0;
- if (((value & 0xf0) >> 4) > Gpwrdelta)
- t2 = ((value & 0xf0) >> 4) - (Gpwrdelta);
- else
- t2 = 0;
- if (((value & 0xf00) >> 8) > Gpwrdelta)
- t3 = ((value & 0xf00) >> 8) - (Gpwrdelta);
- else
- t3 = 0;
- if (((value & 0xf000) >> 12) > Gpwrdelta)
- t4 = ((value & 0xf000) >> 12) - (Gpwrdelta);
- else
- t4 = 0;
- }
- Gdata |= ((t1 << 16) + (t2 << 20) + (t3 << 24) + (t4 << 28));
- data |= (value << 16);
-
- /* For 20M/40M Power Delta issue */
- pAd->Tx20MPwrCfgABand[i] = data;
- pAd->Tx20MPwrCfgGBand[i] = data;
- pAd->Tx40MPwrCfgABand[i] = Adata;
- pAd->Tx40MPwrCfgGBand[i] = Gdata;
-
- if (data != 0xffffffff)
- RTMP_IO_WRITE32(pAd, TX_PWR_CFG_0 + i * 4, data);
- DBGPRINT_RAW(RT_DEBUG_TRACE,
- ("20MHz BW, 2.4G band-%lx, Adata = %lx, Gdata = %lx \n",
- data, Adata, Gdata));
- }
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Read initial channel power parameters from EEPROM
-
- Arguments:
- Adapter Pointer to our adapter
-
- Return Value:
- None
-
- IRQL = PASSIVE_LEVEL
-
- Note:
-
- ========================================================================
-*/
-void RTMPReadChannelPwr(struct rt_rtmp_adapter *pAd)
-{
- u8 i, choffset;
- EEPROM_TX_PWR_STRUC Power;
- EEPROM_TX_PWR_STRUC Power2;
-
- /* Read Tx power value for all channels */
- /* Value from 1 - 0x7f. Default value is 24. */
- /* Power value : 2.4G 0x00 (0) ~ 0x1F (31) */
- /* : 5.5G 0xF9 (-7) ~ 0x0F (15) */
-
- /* 0. 11b/g, ch1 - ch 14 */
- for (i = 0; i < 7; i++) {
- RT28xx_EEPROM_READ16(pAd, EEPROM_G_TX_PWR_OFFSET + i * 2,
- Power.word);
- RT28xx_EEPROM_READ16(pAd, EEPROM_G_TX2_PWR_OFFSET + i * 2,
- Power2.word);
- pAd->TxPower[i * 2].Channel = i * 2 + 1;
- pAd->TxPower[i * 2 + 1].Channel = i * 2 + 2;
-
- if ((Power.field.Byte0 > 31) || (Power.field.Byte0 < 0))
- pAd->TxPower[i * 2].Power = DEFAULT_RF_TX_POWER;
- else
- pAd->TxPower[i * 2].Power = Power.field.Byte0;
-
- if ((Power.field.Byte1 > 31) || (Power.field.Byte1 < 0))
- pAd->TxPower[i * 2 + 1].Power = DEFAULT_RF_TX_POWER;
- else
- pAd->TxPower[i * 2 + 1].Power = Power.field.Byte1;
-
- if ((Power2.field.Byte0 > 31) || (Power2.field.Byte0 < 0))
- pAd->TxPower[i * 2].Power2 = DEFAULT_RF_TX_POWER;
- else
- pAd->TxPower[i * 2].Power2 = Power2.field.Byte0;
-
- if ((Power2.field.Byte1 > 31) || (Power2.field.Byte1 < 0))
- pAd->TxPower[i * 2 + 1].Power2 = DEFAULT_RF_TX_POWER;
- else
- pAd->TxPower[i * 2 + 1].Power2 = Power2.field.Byte1;
- }
-
- /* 1. U-NII lower/middle band: 36, 38, 40; 44, 46, 48; 52, 54, 56; 60, 62, 64 (including central frequency in BW 40MHz) */
- /* 1.1 Fill up channel */
- choffset = 14;
- for (i = 0; i < 4; i++) {
- pAd->TxPower[3 * i + choffset + 0].Channel = 36 + i * 8 + 0;
- pAd->TxPower[3 * i + choffset + 0].Power = DEFAULT_RF_TX_POWER;
- pAd->TxPower[3 * i + choffset + 0].Power2 = DEFAULT_RF_TX_POWER;
-
- pAd->TxPower[3 * i + choffset + 1].Channel = 36 + i * 8 + 2;
- pAd->TxPower[3 * i + choffset + 1].Power = DEFAULT_RF_TX_POWER;
- pAd->TxPower[3 * i + choffset + 1].Power2 = DEFAULT_RF_TX_POWER;
-
- pAd->TxPower[3 * i + choffset + 2].Channel = 36 + i * 8 + 4;
- pAd->TxPower[3 * i + choffset + 2].Power = DEFAULT_RF_TX_POWER;
- pAd->TxPower[3 * i + choffset + 2].Power2 = DEFAULT_RF_TX_POWER;
- }
-
- /* 1.2 Fill up power */
- for (i = 0; i < 6; i++) {
- RT28xx_EEPROM_READ16(pAd, EEPROM_A_TX_PWR_OFFSET + i * 2,
- Power.word);
- RT28xx_EEPROM_READ16(pAd, EEPROM_A_TX2_PWR_OFFSET + i * 2,
- Power2.word);
-
- if ((Power.field.Byte0 < 16) && (Power.field.Byte0 >= -7))
- pAd->TxPower[i * 2 + choffset + 0].Power =
- Power.field.Byte0;
-
- if ((Power.field.Byte1 < 16) && (Power.field.Byte1 >= -7))
- pAd->TxPower[i * 2 + choffset + 1].Power =
- Power.field.Byte1;
-
- if ((Power2.field.Byte0 < 16) && (Power2.field.Byte0 >= -7))
- pAd->TxPower[i * 2 + choffset + 0].Power2 =
- Power2.field.Byte0;
-
- if ((Power2.field.Byte1 < 16) && (Power2.field.Byte1 >= -7))
- pAd->TxPower[i * 2 + choffset + 1].Power2 =
- Power2.field.Byte1;
- }
-
- /* 2. HipperLAN 2 100, 102 ,104; 108, 110, 112; 116, 118, 120; 124, 126, 128; 132, 134, 136; 140 (including central frequency in BW 40MHz) */
- /* 2.1 Fill up channel */
- choffset = 14 + 12;
- for (i = 0; i < 5; i++) {
- pAd->TxPower[3 * i + choffset + 0].Channel = 100 + i * 8 + 0;
- pAd->TxPower[3 * i + choffset + 0].Power = DEFAULT_RF_TX_POWER;
- pAd->TxPower[3 * i + choffset + 0].Power2 = DEFAULT_RF_TX_POWER;
-
- pAd->TxPower[3 * i + choffset + 1].Channel = 100 + i * 8 + 2;
- pAd->TxPower[3 * i + choffset + 1].Power = DEFAULT_RF_TX_POWER;
- pAd->TxPower[3 * i + choffset + 1].Power2 = DEFAULT_RF_TX_POWER;
-
- pAd->TxPower[3 * i + choffset + 2].Channel = 100 + i * 8 + 4;
- pAd->TxPower[3 * i + choffset + 2].Power = DEFAULT_RF_TX_POWER;
- pAd->TxPower[3 * i + choffset + 2].Power2 = DEFAULT_RF_TX_POWER;
- }
- pAd->TxPower[3 * 5 + choffset + 0].Channel = 140;
- pAd->TxPower[3 * 5 + choffset + 0].Power = DEFAULT_RF_TX_POWER;
- pAd->TxPower[3 * 5 + choffset + 0].Power2 = DEFAULT_RF_TX_POWER;
-
- /* 2.2 Fill up power */
- for (i = 0; i < 8; i++) {
- RT28xx_EEPROM_READ16(pAd,
- EEPROM_A_TX_PWR_OFFSET + (choffset - 14) +
- i * 2, Power.word);
- RT28xx_EEPROM_READ16(pAd,
- EEPROM_A_TX2_PWR_OFFSET + (choffset - 14) +
- i * 2, Power2.word);
-
- if ((Power.field.Byte0 < 16) && (Power.field.Byte0 >= -7))
- pAd->TxPower[i * 2 + choffset + 0].Power =
- Power.field.Byte0;
-
- if ((Power.field.Byte1 < 16) && (Power.field.Byte1 >= -7))
- pAd->TxPower[i * 2 + choffset + 1].Power =
- Power.field.Byte1;
-
- if ((Power2.field.Byte0 < 16) && (Power2.field.Byte0 >= -7))
- pAd->TxPower[i * 2 + choffset + 0].Power2 =
- Power2.field.Byte0;
-
- if ((Power2.field.Byte1 < 16) && (Power2.field.Byte1 >= -7))
- pAd->TxPower[i * 2 + choffset + 1].Power2 =
- Power2.field.Byte1;
- }
-
- /* 3. U-NII upper band: 149, 151, 153; 157, 159, 161; 165, 167, 169; 171, 173 (including central frequency in BW 40MHz) */
- /* 3.1 Fill up channel */
- choffset = 14 + 12 + 16;
- /*for (i = 0; i < 2; i++) */
- for (i = 0; i < 3; i++) {
- pAd->TxPower[3 * i + choffset + 0].Channel = 149 + i * 8 + 0;
- pAd->TxPower[3 * i + choffset + 0].Power = DEFAULT_RF_TX_POWER;
- pAd->TxPower[3 * i + choffset + 0].Power2 = DEFAULT_RF_TX_POWER;
-
- pAd->TxPower[3 * i + choffset + 1].Channel = 149 + i * 8 + 2;
- pAd->TxPower[3 * i + choffset + 1].Power = DEFAULT_RF_TX_POWER;
- pAd->TxPower[3 * i + choffset + 1].Power2 = DEFAULT_RF_TX_POWER;
-
- pAd->TxPower[3 * i + choffset + 2].Channel = 149 + i * 8 + 4;
- pAd->TxPower[3 * i + choffset + 2].Power = DEFAULT_RF_TX_POWER;
- pAd->TxPower[3 * i + choffset + 2].Power2 = DEFAULT_RF_TX_POWER;
- }
- pAd->TxPower[3 * 3 + choffset + 0].Channel = 171;
- pAd->TxPower[3 * 3 + choffset + 0].Power = DEFAULT_RF_TX_POWER;
- pAd->TxPower[3 * 3 + choffset + 0].Power2 = DEFAULT_RF_TX_POWER;
-
- pAd->TxPower[3 * 3 + choffset + 1].Channel = 173;
- pAd->TxPower[3 * 3 + choffset + 1].Power = DEFAULT_RF_TX_POWER;
- pAd->TxPower[3 * 3 + choffset + 1].Power2 = DEFAULT_RF_TX_POWER;
-
- /* 3.2 Fill up power */
- /*for (i = 0; i < 4; i++) */
- for (i = 0; i < 6; i++) {
- RT28xx_EEPROM_READ16(pAd,
- EEPROM_A_TX_PWR_OFFSET + (choffset - 14) +
- i * 2, Power.word);
- RT28xx_EEPROM_READ16(pAd,
- EEPROM_A_TX2_PWR_OFFSET + (choffset - 14) +
- i * 2, Power2.word);
-
- if ((Power.field.Byte0 < 16) && (Power.field.Byte0 >= -7))
- pAd->TxPower[i * 2 + choffset + 0].Power =
- Power.field.Byte0;
-
- if ((Power.field.Byte1 < 16) && (Power.field.Byte1 >= -7))
- pAd->TxPower[i * 2 + choffset + 1].Power =
- Power.field.Byte1;
-
- if ((Power2.field.Byte0 < 16) && (Power2.field.Byte0 >= -7))
- pAd->TxPower[i * 2 + choffset + 0].Power2 =
- Power2.field.Byte0;
-
- if ((Power2.field.Byte1 < 16) && (Power2.field.Byte1 >= -7))
- pAd->TxPower[i * 2 + choffset + 1].Power2 =
- Power2.field.Byte1;
- }
-
- /* 4. Print and Debug */
- /*choffset = 14 + 12 + 16 + 7; */
- choffset = 14 + 12 + 16 + 11;
-
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Read the following from the registry
- 1. All the parameters
- 2. NetworkAddres
-
- Arguments:
- Adapter Pointer to our adapter
- WrapperConfigurationContext For use by NdisOpenConfiguration
-
- Return Value:
- NDIS_STATUS_SUCCESS
- NDIS_STATUS_FAILURE
- NDIS_STATUS_RESOURCES
-
- IRQL = PASSIVE_LEVEL
-
- Note:
-
- ========================================================================
-*/
-int NICReadRegParameters(struct rt_rtmp_adapter *pAd,
- void *WrapperConfigurationContext)
-{
- int Status = NDIS_STATUS_SUCCESS;
- DBGPRINT_S(Status, ("<-- NICReadRegParameters, Status=%x\n", Status));
- return Status;
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Read initial parameters from EEPROM
-
- Arguments:
- Adapter Pointer to our adapter
-
- Return Value:
- None
-
- IRQL = PASSIVE_LEVEL
-
- Note:
-
- ========================================================================
-*/
-void NICReadEEPROMParameters(struct rt_rtmp_adapter *pAd, u8 *mac_addr)
-{
- u32 data = 0;
- u16 i, value, value2;
- u8 TmpPhy;
- EEPROM_TX_PWR_STRUC Power;
- EEPROM_VERSION_STRUC Version;
- EEPROM_ANTENNA_STRUC Antenna;
- EEPROM_NIC_CONFIG2_STRUC NicConfig2;
-
- DBGPRINT(RT_DEBUG_TRACE, ("--> NICReadEEPROMParameters\n"));
-
- if (pAd->chipOps.eeinit)
- pAd->chipOps.eeinit(pAd);
-
- /* Init EEPROM Address Number, before access EEPROM; if 93c46, EEPROMAddressNum=6, else if 93c66, EEPROMAddressNum=8 */
- RTMP_IO_READ32(pAd, E2PROM_CSR, &data);
- DBGPRINT(RT_DEBUG_TRACE, ("--> E2PROM_CSR = 0x%x\n", data));
-
- if ((data & 0x30) == 0)
- pAd->EEPROMAddressNum = 6; /* 93C46 */
- else if ((data & 0x30) == 0x10)
- pAd->EEPROMAddressNum = 8; /* 93C66 */
- else
- pAd->EEPROMAddressNum = 8; /* 93C86 */
- DBGPRINT(RT_DEBUG_TRACE,
- ("--> EEPROMAddressNum = %d\n", pAd->EEPROMAddressNum));
-
- /* RT2860 MAC no longer auto load MAC address from E2PROM. Driver has to initialize */
- /* MAC address registers according to E2PROM setting */
- if (mac_addr == NULL ||
- strlen((char *)mac_addr) != 17 ||
- mac_addr[2] != ':' || mac_addr[5] != ':' || mac_addr[8] != ':' ||
- mac_addr[11] != ':' || mac_addr[14] != ':') {
- u16 Addr01, Addr23, Addr45;
-
- RT28xx_EEPROM_READ16(pAd, 0x04, Addr01);
- RT28xx_EEPROM_READ16(pAd, 0x06, Addr23);
- RT28xx_EEPROM_READ16(pAd, 0x08, Addr45);
-
- pAd->PermanentAddress[0] = (u8)(Addr01 & 0xff);
- pAd->PermanentAddress[1] = (u8)(Addr01 >> 8);
- pAd->PermanentAddress[2] = (u8)(Addr23 & 0xff);
- pAd->PermanentAddress[3] = (u8)(Addr23 >> 8);
- pAd->PermanentAddress[4] = (u8)(Addr45 & 0xff);
- pAd->PermanentAddress[5] = (u8)(Addr45 >> 8);
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("Initialize MAC Address from E2PROM \n"));
- } else {
- int j;
- char *macptr;
-
- macptr = (char *)mac_addr;
-
- for (j = 0; j < MAC_ADDR_LEN; j++) {
- AtoH(macptr, &pAd->PermanentAddress[j], 1);
- macptr = macptr + 3;
- }
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("Initialize MAC Address from module parameter \n"));
- }
-
- {
- /*more conveninet to test mbssid, so ap's bssid &0xf1 */
- if (pAd->PermanentAddress[0] == 0xff)
- pAd->PermanentAddress[0] = RandomByte(pAd) & 0xf8;
-
- /*if (pAd->PermanentAddress[5] == 0xff) */
- /* pAd->PermanentAddress[5] = RandomByte(pAd)&0xf8; */
-
- DBGPRINT_RAW(RT_DEBUG_TRACE,
- ("E2PROM MAC: =%pM\n", pAd->PermanentAddress));
- if (pAd->bLocalAdminMAC == FALSE) {
- MAC_DW0_STRUC csr2;
- MAC_DW1_STRUC csr3;
- COPY_MAC_ADDR(pAd->CurrentAddress,
- pAd->PermanentAddress);
- csr2.field.Byte0 = pAd->CurrentAddress[0];
- csr2.field.Byte1 = pAd->CurrentAddress[1];
- csr2.field.Byte2 = pAd->CurrentAddress[2];
- csr2.field.Byte3 = pAd->CurrentAddress[3];
- RTMP_IO_WRITE32(pAd, MAC_ADDR_DW0, csr2.word);
- csr3.word = 0;
- csr3.field.Byte4 = pAd->CurrentAddress[4];
- csr3.field.Byte5 = pAd->CurrentAddress[5];
- csr3.field.U2MeMask = 0xff;
- RTMP_IO_WRITE32(pAd, MAC_ADDR_DW1, csr3.word);
- DBGPRINT_RAW(RT_DEBUG_TRACE,
- ("E2PROM MAC: =%pM\n",
- pAd->PermanentAddress));
- }
- }
-
- /* if not return early. cause fail at emulation. */
- /* Init the channel number for TX channel power */
- RTMPReadChannelPwr(pAd);
-
- /* if E2PROM version mismatch with driver's expectation, then skip */
- /* all subsequent E2RPOM retieval and set a system error bit to notify GUI */
- RT28xx_EEPROM_READ16(pAd, EEPROM_VERSION_OFFSET, Version.word);
- pAd->EepromVersion =
- Version.field.Version + Version.field.FaeReleaseNumber * 256;
- DBGPRINT(RT_DEBUG_TRACE,
- ("E2PROM: Version = %d, FAE release #%d\n",
- Version.field.Version, Version.field.FaeReleaseNumber));
-
- if (Version.field.Version > VALID_EEPROM_VERSION) {
- DBGPRINT_ERR("E2PROM: WRONG VERSION 0x%x, should be %d\n", Version.field.Version, VALID_EEPROM_VERSION);
- /*pAd->SystemErrorBitmap |= 0x00000001;
-
- // hard-code default value when no proper E2PROM installed
- pAd->bAutoTxAgcA = FALSE;
- pAd->bAutoTxAgcG = FALSE;
-
- // Default the channel power
- for (i = 0; i < MAX_NUM_OF_CHANNELS; i++)
- pAd->TxPower[i].Power = DEFAULT_RF_TX_POWER;
-
- // Default the channel power
- for (i = 0; i < MAX_NUM_OF_11JCHANNELS; i++)
- pAd->TxPower11J[i].Power = DEFAULT_RF_TX_POWER;
-
- for(i = 0; i < NUM_EEPROM_BBP_PARMS; i++)
- pAd->EEPROMDefaultValue[i] = 0xffff;
- return; */
- }
- /* Read BBP default value from EEPROM and store to array(EEPROMDefaultValue) in pAd */
- RT28xx_EEPROM_READ16(pAd, EEPROM_NIC1_OFFSET, value);
- pAd->EEPROMDefaultValue[0] = value;
-
- RT28xx_EEPROM_READ16(pAd, EEPROM_NIC2_OFFSET, value);
- pAd->EEPROMDefaultValue[1] = value;
-
- RT28xx_EEPROM_READ16(pAd, 0x38, value); /* Country Region */
- pAd->EEPROMDefaultValue[2] = value;
-
- for (i = 0; i < 8; i++) {
- RT28xx_EEPROM_READ16(pAd, EEPROM_BBP_BASE_OFFSET + i * 2,
- value);
- pAd->EEPROMDefaultValue[i + 3] = value;
- }
-
- /* We have to parse NIC configuration 0 at here. */
- /* If TSSI did not have preloaded value, it should reset the TxAutoAgc to false */
- /* Therefore, we have to read TxAutoAgc control beforehand. */
- /* Read Tx AGC control bit */
- Antenna.word = pAd->EEPROMDefaultValue[0];
- if (Antenna.word == 0xFFFF) {
-#ifdef RT30xx
- if (IS_RT3090(pAd) || IS_RT3390(pAd)) {
- Antenna.word = 0;
- Antenna.field.RfIcType = RFIC_3020;
- Antenna.field.TxPath = 1;
- Antenna.field.RxPath = 1;
- } else
-#endif /* RT30xx // */
- {
-
- Antenna.word = 0;
- Antenna.field.RfIcType = RFIC_2820;
- Antenna.field.TxPath = 1;
- Antenna.field.RxPath = 2;
- DBGPRINT(RT_DEBUG_WARN,
- ("E2PROM error, hard code as 0x%04x\n",
- Antenna.word));
- }
- }
- /* Choose the desired Tx&Rx stream. */
- if ((pAd->CommonCfg.TxStream == 0)
- || (pAd->CommonCfg.TxStream > Antenna.field.TxPath))
- pAd->CommonCfg.TxStream = Antenna.field.TxPath;
-
- if ((pAd->CommonCfg.RxStream == 0)
- || (pAd->CommonCfg.RxStream > Antenna.field.RxPath)) {
- pAd->CommonCfg.RxStream = Antenna.field.RxPath;
-
- if ((pAd->MACVersion < RALINK_2883_VERSION) &&
- (pAd->CommonCfg.RxStream > 2)) {
- /* only 2 Rx streams for RT2860 series */
- pAd->CommonCfg.RxStream = 2;
- }
- }
- /* 3*3 */
- /* read value from EEPROM and set them to CSR174 ~ 177 in chain0 ~ chain2 */
- /* yet implement */
- for (i = 0; i < 3; i++) {
- }
-
- NicConfig2.word = pAd->EEPROMDefaultValue[1];
-
- {
- if ((NicConfig2.word & 0x00ff) == 0xff) {
- NicConfig2.word &= 0xff00;
- }
-
- if ((NicConfig2.word >> 8) == 0xff) {
- NicConfig2.word &= 0x00ff;
- }
- }
-
- if (NicConfig2.field.DynamicTxAgcControl == 1)
- pAd->bAutoTxAgcA = pAd->bAutoTxAgcG = TRUE;
- else
- pAd->bAutoTxAgcA = pAd->bAutoTxAgcG = FALSE;
-
- DBGPRINT_RAW(RT_DEBUG_TRACE,
- ("NICReadEEPROMParameters: RxPath = %d, TxPath = %d\n",
- Antenna.field.RxPath, Antenna.field.TxPath));
-
- /* Save the antenna for future use */
- pAd->Antenna.word = Antenna.word;
-
- /* Set the RfICType here, then we can initialize RFIC related operation callbacks */
- pAd->Mlme.RealRxPath = (u8)Antenna.field.RxPath;
- pAd->RfIcType = (u8)Antenna.field.RfIcType;
-
-#ifdef RTMP_RF_RW_SUPPORT
- RtmpChipOpsRFHook(pAd);
-#endif /* RTMP_RF_RW_SUPPORT // */
-
-#ifdef RTMP_MAC_PCI
- sprintf((char *)pAd->nickname, "RT2860STA");
-#endif /* RTMP_MAC_PCI // */
-
- /* */
- /* Reset PhyMode if we don't support 802.11a */
- /* Only RFIC_2850 & RFIC_2750 support 802.11a */
- /* */
- if ((Antenna.field.RfIcType != RFIC_2850)
- && (Antenna.field.RfIcType != RFIC_2750)
- && (Antenna.field.RfIcType != RFIC_3052)) {
- if ((pAd->CommonCfg.PhyMode == PHY_11ABG_MIXED) ||
- (pAd->CommonCfg.PhyMode == PHY_11A))
- pAd->CommonCfg.PhyMode = PHY_11BG_MIXED;
- else if ((pAd->CommonCfg.PhyMode == PHY_11ABGN_MIXED) ||
- (pAd->CommonCfg.PhyMode == PHY_11AN_MIXED) ||
- (pAd->CommonCfg.PhyMode == PHY_11AGN_MIXED) ||
- (pAd->CommonCfg.PhyMode == PHY_11N_5G))
- pAd->CommonCfg.PhyMode = PHY_11BGN_MIXED;
- }
- /* Read TSSI reference and TSSI boundary for temperature compensation. This is ugly */
- /* 0. 11b/g */
- {
- /* these are tempature reference value (0x00 ~ 0xFE)
- ex: 0x00 0x15 0x25 0x45 0x88 0xA0 0xB5 0xD0 0xF0
- TssiPlusBoundaryG [4] [3] [2] [1] [0] (smaller) +
- TssiMinusBoundaryG[0] [1] [2] [3] [4] (larger) */
- RT28xx_EEPROM_READ16(pAd, 0x6E, Power.word);
- pAd->TssiMinusBoundaryG[4] = Power.field.Byte0;
- pAd->TssiMinusBoundaryG[3] = Power.field.Byte1;
- RT28xx_EEPROM_READ16(pAd, 0x70, Power.word);
- pAd->TssiMinusBoundaryG[2] = Power.field.Byte0;
- pAd->TssiMinusBoundaryG[1] = Power.field.Byte1;
- RT28xx_EEPROM_READ16(pAd, 0x72, Power.word);
- pAd->TssiRefG = Power.field.Byte0; /* reference value [0] */
- pAd->TssiPlusBoundaryG[1] = Power.field.Byte1;
- RT28xx_EEPROM_READ16(pAd, 0x74, Power.word);
- pAd->TssiPlusBoundaryG[2] = Power.field.Byte0;
- pAd->TssiPlusBoundaryG[3] = Power.field.Byte1;
- RT28xx_EEPROM_READ16(pAd, 0x76, Power.word);
- pAd->TssiPlusBoundaryG[4] = Power.field.Byte0;
- pAd->TxAgcStepG = Power.field.Byte1;
- pAd->TxAgcCompensateG = 0;
- pAd->TssiMinusBoundaryG[0] = pAd->TssiRefG;
- pAd->TssiPlusBoundaryG[0] = pAd->TssiRefG;
-
- /* Disable TxAgc if the based value is not right */
- if (pAd->TssiRefG == 0xff)
- pAd->bAutoTxAgcG = FALSE;
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("E2PROM: G Tssi[-4 .. +4] = %d %d %d %d - %d -%d %d %d %d, step=%d, tuning=%d\n",
- pAd->TssiMinusBoundaryG[4],
- pAd->TssiMinusBoundaryG[3],
- pAd->TssiMinusBoundaryG[2],
- pAd->TssiMinusBoundaryG[1], pAd->TssiRefG,
- pAd->TssiPlusBoundaryG[1], pAd->TssiPlusBoundaryG[2],
- pAd->TssiPlusBoundaryG[3], pAd->TssiPlusBoundaryG[4],
- pAd->TxAgcStepG, pAd->bAutoTxAgcG));
- }
- /* 1. 11a */
- {
- RT28xx_EEPROM_READ16(pAd, 0xD4, Power.word);
- pAd->TssiMinusBoundaryA[4] = Power.field.Byte0;
- pAd->TssiMinusBoundaryA[3] = Power.field.Byte1;
- RT28xx_EEPROM_READ16(pAd, 0xD6, Power.word);
- pAd->TssiMinusBoundaryA[2] = Power.field.Byte0;
- pAd->TssiMinusBoundaryA[1] = Power.field.Byte1;
- RT28xx_EEPROM_READ16(pAd, 0xD8, Power.word);
- pAd->TssiRefA = Power.field.Byte0;
- pAd->TssiPlusBoundaryA[1] = Power.field.Byte1;
- RT28xx_EEPROM_READ16(pAd, 0xDA, Power.word);
- pAd->TssiPlusBoundaryA[2] = Power.field.Byte0;
- pAd->TssiPlusBoundaryA[3] = Power.field.Byte1;
- RT28xx_EEPROM_READ16(pAd, 0xDC, Power.word);
- pAd->TssiPlusBoundaryA[4] = Power.field.Byte0;
- pAd->TxAgcStepA = Power.field.Byte1;
- pAd->TxAgcCompensateA = 0;
- pAd->TssiMinusBoundaryA[0] = pAd->TssiRefA;
- pAd->TssiPlusBoundaryA[0] = pAd->TssiRefA;
-
- /* Disable TxAgc if the based value is not right */
- if (pAd->TssiRefA == 0xff)
- pAd->bAutoTxAgcA = FALSE;
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("E2PROM: A Tssi[-4 .. +4] = %d %d %d %d - %d -%d %d %d %d, step=%d, tuning=%d\n",
- pAd->TssiMinusBoundaryA[4],
- pAd->TssiMinusBoundaryA[3],
- pAd->TssiMinusBoundaryA[2],
- pAd->TssiMinusBoundaryA[1], pAd->TssiRefA,
- pAd->TssiPlusBoundaryA[1], pAd->TssiPlusBoundaryA[2],
- pAd->TssiPlusBoundaryA[3], pAd->TssiPlusBoundaryA[4],
- pAd->TxAgcStepA, pAd->bAutoTxAgcA));
- }
- pAd->BbpRssiToDbmDelta = 0x0;
-
- /* Read frequency offset setting for RF */
- RT28xx_EEPROM_READ16(pAd, EEPROM_FREQ_OFFSET, value);
- if ((value & 0x00FF) != 0x00FF)
- pAd->RfFreqOffset = (unsigned long)(value & 0x00FF);
- else
- pAd->RfFreqOffset = 0;
- DBGPRINT(RT_DEBUG_TRACE,
- ("E2PROM: RF FreqOffset=0x%lx \n", pAd->RfFreqOffset));
-
- /*CountryRegion byte offset (38h) */
- value = pAd->EEPROMDefaultValue[2] >> 8; /* 2.4G band */
- value2 = pAd->EEPROMDefaultValue[2] & 0x00FF; /* 5G band */
-
- if ((value <= REGION_MAXIMUM_BG_BAND)
- && (value2 <= REGION_MAXIMUM_A_BAND)) {
- pAd->CommonCfg.CountryRegion = ((u8)value) | 0x80;
- pAd->CommonCfg.CountryRegionForABand = ((u8)value2) | 0x80;
- TmpPhy = pAd->CommonCfg.PhyMode;
- pAd->CommonCfg.PhyMode = 0xff;
- RTMPSetPhyMode(pAd, TmpPhy);
- SetCommonHT(pAd);
- }
- /* */
- /* Get RSSI Offset on EEPROM 0x9Ah & 0x9Ch. */
- /* The valid value are (-10 ~ 10) */
- /* */
- RT28xx_EEPROM_READ16(pAd, EEPROM_RSSI_BG_OFFSET, value);
- pAd->BGRssiOffset0 = value & 0x00ff;
- pAd->BGRssiOffset1 = (value >> 8);
- RT28xx_EEPROM_READ16(pAd, EEPROM_RSSI_BG_OFFSET + 2, value);
- pAd->BGRssiOffset2 = value & 0x00ff;
- pAd->ALNAGain1 = (value >> 8);
- RT28xx_EEPROM_READ16(pAd, EEPROM_LNA_OFFSET, value);
- pAd->BLNAGain = value & 0x00ff;
- pAd->ALNAGain0 = (value >> 8);
-
- /* Validate 11b/g RSSI_0 offset. */
- if ((pAd->BGRssiOffset0 < -10) || (pAd->BGRssiOffset0 > 10))
- pAd->BGRssiOffset0 = 0;
-
- /* Validate 11b/g RSSI_1 offset. */
- if ((pAd->BGRssiOffset1 < -10) || (pAd->BGRssiOffset1 > 10))
- pAd->BGRssiOffset1 = 0;
-
- /* Validate 11b/g RSSI_2 offset. */
- if ((pAd->BGRssiOffset2 < -10) || (pAd->BGRssiOffset2 > 10))
- pAd->BGRssiOffset2 = 0;
-
- RT28xx_EEPROM_READ16(pAd, EEPROM_RSSI_A_OFFSET, value);
- pAd->ARssiOffset0 = value & 0x00ff;
- pAd->ARssiOffset1 = (value >> 8);
- RT28xx_EEPROM_READ16(pAd, (EEPROM_RSSI_A_OFFSET + 2), value);
- pAd->ARssiOffset2 = value & 0x00ff;
- pAd->ALNAGain2 = (value >> 8);
-
- if (((u8)pAd->ALNAGain1 == 0xFF) || (pAd->ALNAGain1 == 0x00))
- pAd->ALNAGain1 = pAd->ALNAGain0;
- if (((u8)pAd->ALNAGain2 == 0xFF) || (pAd->ALNAGain2 == 0x00))
- pAd->ALNAGain2 = pAd->ALNAGain0;
-
- /* Validate 11a RSSI_0 offset. */
- if ((pAd->ARssiOffset0 < -10) || (pAd->ARssiOffset0 > 10))
- pAd->ARssiOffset0 = 0;
-
- /* Validate 11a RSSI_1 offset. */
- if ((pAd->ARssiOffset1 < -10) || (pAd->ARssiOffset1 > 10))
- pAd->ARssiOffset1 = 0;
-
- /*Validate 11a RSSI_2 offset. */
- if ((pAd->ARssiOffset2 < -10) || (pAd->ARssiOffset2 > 10))
- pAd->ARssiOffset2 = 0;
-
-#ifdef RT30xx
- /* */
- /* Get TX mixer gain setting */
- /* 0xff are invalid value */
- /* Note: RT30xX default value is 0x00 and will program to RF_R17 only when this value is not zero. */
- /* RT359X default value is 0x02 */
- /* */
- if (IS_RT30xx(pAd) || IS_RT3572(pAd)) {
- RT28xx_EEPROM_READ16(pAd, EEPROM_TXMIXER_GAIN_2_4G, value);
- pAd->TxMixerGain24G = 0;
- value &= 0x00ff;
- if (value != 0xff) {
- value &= 0x07;
- pAd->TxMixerGain24G = (u8)value;
- }
- }
-#endif /* RT30xx // */
-
- /* */
- /* Get LED Setting. */
- /* */
- RT28xx_EEPROM_READ16(pAd, 0x3a, value);
- pAd->LedCntl.word = (value >> 8);
- RT28xx_EEPROM_READ16(pAd, EEPROM_LED1_OFFSET, value);
- pAd->Led1 = value;
- RT28xx_EEPROM_READ16(pAd, EEPROM_LED2_OFFSET, value);
- pAd->Led2 = value;
- RT28xx_EEPROM_READ16(pAd, EEPROM_LED3_OFFSET, value);
- pAd->Led3 = value;
-
- RTMPReadTxPwrPerRate(pAd);
-
-#ifdef RT30xx
-#ifdef RTMP_EFUSE_SUPPORT
- RtmpEfuseSupportCheck(pAd);
-#endif /* RTMP_EFUSE_SUPPORT // */
-#endif /* RT30xx // */
-
- DBGPRINT(RT_DEBUG_TRACE, ("<-- NICReadEEPROMParameters\n"));
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Set default value from EEPROM
-
- Arguments:
- Adapter Pointer to our adapter
-
- Return Value:
- None
-
- IRQL = PASSIVE_LEVEL
-
- Note:
-
- ========================================================================
-*/
-void NICInitAsicFromEEPROM(struct rt_rtmp_adapter *pAd)
-{
- u32 data = 0;
- u8 BBPR1 = 0;
- u16 i;
-/* EEPROM_ANTENNA_STRUC Antenna; */
- EEPROM_NIC_CONFIG2_STRUC NicConfig2;
- u8 BBPR3 = 0;
-
- DBGPRINT(RT_DEBUG_TRACE, ("--> NICInitAsicFromEEPROM\n"));
- for (i = 3; i < NUM_EEPROM_BBP_PARMS; i++) {
- u8 BbpRegIdx, BbpValue;
-
- if ((pAd->EEPROMDefaultValue[i] != 0xFFFF)
- && (pAd->EEPROMDefaultValue[i] != 0)) {
- BbpRegIdx = (u8)(pAd->EEPROMDefaultValue[i] >> 8);
- BbpValue = (u8)(pAd->EEPROMDefaultValue[i] & 0xff);
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BbpRegIdx, BbpValue);
- }
- }
-
- NicConfig2.word = pAd->EEPROMDefaultValue[1];
-
- {
- if ((NicConfig2.word & 0x00ff) == 0xff) {
- NicConfig2.word &= 0xff00;
- }
-
- if ((NicConfig2.word >> 8) == 0xff) {
- NicConfig2.word &= 0x00ff;
- }
- }
-
- /* Save the antenna for future use */
- pAd->NicConfig2.word = NicConfig2.word;
-
-#ifdef RT30xx
- /* set default antenna as main */
- if (pAd->RfIcType == RFIC_3020)
- AsicSetRxAnt(pAd, pAd->RxAnt.Pair1PrimaryRxAnt);
-#endif /* RT30xx // */
-
- /* */
- /* Send LED Setting to MCU. */
- /* */
- if (pAd->LedCntl.word == 0xFF) {
- pAd->LedCntl.word = 0x01;
- pAd->Led1 = 0x5555;
- pAd->Led2 = 0x2221;
-
-#ifdef RTMP_MAC_PCI
- pAd->Led3 = 0xA9F8;
-#endif /* RTMP_MAC_PCI // */
-#ifdef RTMP_MAC_USB
- pAd->Led3 = 0x5627;
-#endif /* RTMP_MAC_USB // */
- }
-
- AsicSendCommandToMcu(pAd, 0x52, 0xff, (u8)pAd->Led1,
- (u8)(pAd->Led1 >> 8));
- AsicSendCommandToMcu(pAd, 0x53, 0xff, (u8)pAd->Led2,
- (u8)(pAd->Led2 >> 8));
- AsicSendCommandToMcu(pAd, 0x54, 0xff, (u8)pAd->Led3,
- (u8)(pAd->Led3 >> 8));
- AsicSendCommandToMcu(pAd, 0x51, 0xff, 0, pAd->LedCntl.field.Polarity);
-
- pAd->LedIndicatorStrength = 0xFF;
- RTMPSetSignalLED(pAd, -100); /* Force signal strength Led to be turned off, before link up */
-
- {
- /* Read Hardware controlled Radio state enable bit */
- if (NicConfig2.field.HardwareRadioControl == 1) {
- pAd->StaCfg.bHardwareRadio = TRUE;
-
- /* Read GPIO pin2 as Hardware controlled radio state */
- RTMP_IO_READ32(pAd, GPIO_CTRL_CFG, &data);
- if ((data & 0x04) == 0) {
- pAd->StaCfg.bHwRadio = FALSE;
- pAd->StaCfg.bRadio = FALSE;
-/* RTMP_IO_WRITE32(pAd, PWR_PIN_CFG, 0x00001818); */
- RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_RADIO_OFF);
- }
- } else
- pAd->StaCfg.bHardwareRadio = FALSE;
-
- if (pAd->StaCfg.bRadio == FALSE) {
- RTMPSetLED(pAd, LED_RADIO_OFF);
- } else {
- RTMPSetLED(pAd, LED_RADIO_ON);
-#ifdef RTMP_MAC_PCI
-#ifdef RT3090
- AsicSendCommandToMcu(pAd, 0x30, PowerRadioOffCID, 0xff,
- 0x02);
- AsicCheckCommanOk(pAd, PowerRadioOffCID);
-#endif /* RT3090 // */
-#ifndef RT3090
- AsicSendCommandToMcu(pAd, 0x30, 0xff, 0xff, 0x02);
-#endif /* RT3090 // */
- AsicSendCommandToMcu(pAd, 0x31, PowerWakeCID, 0x00,
- 0x00);
- /* 2-1. wait command ok. */
- AsicCheckCommanOk(pAd, PowerWakeCID);
-#endif /* RTMP_MAC_PCI // */
- }
- }
-
-#ifdef RTMP_MAC_PCI
-#ifdef RT30xx
- if (IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd)) {
- struct rt_rtmp_chip_op *pChipOps = &pAd->chipOps;
- if (pChipOps->AsicReverseRfFromSleepMode)
- pChipOps->AsicReverseRfFromSleepMode(pAd);
- }
- /* 3090 MCU Wakeup command needs more time to be stable. */
- /* Before stable, don't issue other MCU command to prevent from firmware error. */
-
- if ((IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd))
- && IS_VERSION_AFTER_F(pAd)
- && (pAd->StaCfg.PSControl.field.rt30xxPowerMode == 3)
- && (pAd->StaCfg.PSControl.field.EnableNewPS == TRUE)) {
- DBGPRINT(RT_DEBUG_TRACE, ("%s, release Mcu Lock\n", __func__));
- RTMP_SEM_LOCK(&pAd->McuCmdLock);
- pAd->brt30xxBanMcuCmd = FALSE;
- RTMP_SEM_UNLOCK(&pAd->McuCmdLock);
- }
-#endif /* RT30xx // */
-#endif /* RTMP_MAC_PCI // */
-
- /* Turn off patching for cardbus controller */
- if (NicConfig2.field.CardbusAcceleration == 1) {
-/* pAd->bTest1 = TRUE; */
- }
-
- if (NicConfig2.field.DynamicTxAgcControl == 1)
- pAd->bAutoTxAgcA = pAd->bAutoTxAgcG = TRUE;
- else
- pAd->bAutoTxAgcA = pAd->bAutoTxAgcG = FALSE;
- /* */
- /* Since BBP has been progamed, to make sure BBP setting will be */
- /* upate inside of AsicAntennaSelect, so reset to UNKNOWN_BAND! */
- /* */
- pAd->CommonCfg.BandState = UNKNOWN_BAND;
-
- RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &BBPR3);
- BBPR3 &= (~0x18);
- if (pAd->Antenna.field.RxPath == 3) {
- BBPR3 |= (0x10);
- } else if (pAd->Antenna.field.RxPath == 2) {
- BBPR3 |= (0x8);
- } else if (pAd->Antenna.field.RxPath == 1) {
- BBPR3 |= (0x0);
- }
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, BBPR3);
-
- {
- /* Handle the difference when 1T */
- RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R1, &BBPR1);
- if (pAd->Antenna.field.TxPath == 1) {
- BBPR1 &= (~0x18);
- }
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R1, BBPR1);
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("Use Hw Radio Control Pin=%d; if used Pin=%d;\n",
- pAd->CommonCfg.bHardwareRadio,
- pAd->CommonCfg.bHardwareRadio));
- }
-
-#ifdef RTMP_MAC_USB
-#ifdef RT30xx
- /* update registers from EEPROM for RT3071 or later(3572/3592). */
-
- if (IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd)) {
- u8 RegIdx, RegValue;
- u16 value;
-
- /* after RT3071, write BBP from EEPROM 0xF0 to 0x102 */
- for (i = 0xF0; i <= 0x102; i = i + 2) {
- value = 0xFFFF;
- RT28xx_EEPROM_READ16(pAd, i, value);
- if ((value != 0xFFFF) && (value != 0)) {
- RegIdx = (u8)(value >> 8);
- RegValue = (u8)(value & 0xff);
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, RegIdx,
- RegValue);
- DBGPRINT(RT_DEBUG_TRACE,
- ("Update BBP Registers from EEPROM(0x%0x), BBP(0x%x) = 0x%x\n",
- i, RegIdx, RegValue));
- }
- }
-
- /* after RT3071, write RF from EEPROM 0x104 to 0x116 */
- for (i = 0x104; i <= 0x116; i = i + 2) {
- value = 0xFFFF;
- RT28xx_EEPROM_READ16(pAd, i, value);
- if ((value != 0xFFFF) && (value != 0)) {
- RegIdx = (u8)(value >> 8);
- RegValue = (u8)(value & 0xff);
- RT30xxWriteRFRegister(pAd, RegIdx, RegValue);
- DBGPRINT(RT_DEBUG_TRACE,
- ("Update RF Registers from EEPROM0x%x), BBP(0x%x) = 0x%x\n",
- i, RegIdx, RegValue));
- }
- }
- }
-#endif /* RT30xx // */
-#endif /* RTMP_MAC_USB // */
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("TxPath = %d, RxPath = %d, RFIC=%d, Polar+LED mode=%x\n",
- pAd->Antenna.field.TxPath, pAd->Antenna.field.RxPath,
- pAd->RfIcType, pAd->LedCntl.word));
- DBGPRINT(RT_DEBUG_TRACE, ("<-- NICInitAsicFromEEPROM\n"));
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Initialize NIC hardware
-
- Arguments:
- Adapter Pointer to our adapter
-
- Return Value:
- None
-
- IRQL = PASSIVE_LEVEL
-
- Note:
-
- ========================================================================
-*/
-int NICInitializeAdapter(struct rt_rtmp_adapter *pAd, IN BOOLEAN bHardReset)
-{
- int Status = NDIS_STATUS_SUCCESS;
- WPDMA_GLO_CFG_STRUC GloCfg;
-#ifdef RTMP_MAC_PCI
- u32 Value;
- DELAY_INT_CFG_STRUC IntCfg;
-#endif /* RTMP_MAC_PCI // */
-/* INT_MASK_CSR_STRUC IntMask; */
- unsigned long i = 0, j = 0;
- AC_TXOP_CSR0_STRUC csr0;
-
- DBGPRINT(RT_DEBUG_TRACE, ("--> NICInitializeAdapter\n"));
-
- /* 3. Set DMA global configuration except TX_DMA_EN and RX_DMA_EN bits: */
-retry:
- i = 0;
- do {
- RTMP_IO_READ32(pAd, WPDMA_GLO_CFG, &GloCfg.word);
- if ((GloCfg.field.TxDMABusy == 0)
- && (GloCfg.field.RxDMABusy == 0))
- break;
-
- RTMPusecDelay(1000);
- i++;
- } while (i < 100);
- DBGPRINT(RT_DEBUG_TRACE,
- ("<== DMA offset 0x208 = 0x%x\n", GloCfg.word));
- GloCfg.word &= 0xff0;
- GloCfg.field.EnTXWriteBackDDONE = 1;
- RTMP_IO_WRITE32(pAd, WPDMA_GLO_CFG, GloCfg.word);
-
- /* Record HW Beacon offset */
- pAd->BeaconOffset[0] = HW_BEACON_BASE0;
- pAd->BeaconOffset[1] = HW_BEACON_BASE1;
- pAd->BeaconOffset[2] = HW_BEACON_BASE2;
- pAd->BeaconOffset[3] = HW_BEACON_BASE3;
- pAd->BeaconOffset[4] = HW_BEACON_BASE4;
- pAd->BeaconOffset[5] = HW_BEACON_BASE5;
- pAd->BeaconOffset[6] = HW_BEACON_BASE6;
- pAd->BeaconOffset[7] = HW_BEACON_BASE7;
-
- /* */
- /* write all shared Ring's base address into ASIC */
- /* */
-
- /* asic simulation sequence put this ahead before loading firmware. */
- /* pbf hardware reset */
-#ifdef RTMP_MAC_PCI
- RTMP_IO_WRITE32(pAd, WPDMA_RST_IDX, 0x1003f); /* 0x10000 for reset rx, 0x3f resets all 6 tx rings. */
- RTMP_IO_WRITE32(pAd, PBF_SYS_CTRL, 0xe1f);
- RTMP_IO_WRITE32(pAd, PBF_SYS_CTRL, 0xe00);
-#endif /* RTMP_MAC_PCI // */
-
- /* Initialze ASIC for TX & Rx operation */
- if (NICInitializeAsic(pAd, bHardReset) != NDIS_STATUS_SUCCESS) {
- if (j++ == 0) {
- NICLoadFirmware(pAd);
- goto retry;
- }
- return NDIS_STATUS_FAILURE;
- }
-
-#ifdef RTMP_MAC_PCI
- /* Write AC_BK base address register */
- Value =
- RTMP_GetPhysicalAddressLow(pAd->TxRing[QID_AC_BK].Cell[0].AllocPa);
- RTMP_IO_WRITE32(pAd, TX_BASE_PTR1, Value);
- DBGPRINT(RT_DEBUG_TRACE, ("--> TX_BASE_PTR1 : 0x%x\n", Value));
-
- /* Write AC_BE base address register */
- Value =
- RTMP_GetPhysicalAddressLow(pAd->TxRing[QID_AC_BE].Cell[0].AllocPa);
- RTMP_IO_WRITE32(pAd, TX_BASE_PTR0, Value);
- DBGPRINT(RT_DEBUG_TRACE, ("--> TX_BASE_PTR0 : 0x%x\n", Value));
-
- /* Write AC_VI base address register */
- Value =
- RTMP_GetPhysicalAddressLow(pAd->TxRing[QID_AC_VI].Cell[0].AllocPa);
- RTMP_IO_WRITE32(pAd, TX_BASE_PTR2, Value);
- DBGPRINT(RT_DEBUG_TRACE, ("--> TX_BASE_PTR2 : 0x%x\n", Value));
-
- /* Write AC_VO base address register */
- Value =
- RTMP_GetPhysicalAddressLow(pAd->TxRing[QID_AC_VO].Cell[0].AllocPa);
- RTMP_IO_WRITE32(pAd, TX_BASE_PTR3, Value);
- DBGPRINT(RT_DEBUG_TRACE, ("--> TX_BASE_PTR3 : 0x%x\n", Value));
-
- /* Write MGMT_BASE_CSR register */
- Value = RTMP_GetPhysicalAddressLow(pAd->MgmtRing.Cell[0].AllocPa);
- RTMP_IO_WRITE32(pAd, TX_BASE_PTR5, Value);
- DBGPRINT(RT_DEBUG_TRACE, ("--> TX_BASE_PTR5 : 0x%x\n", Value));
-
- /* Write RX_BASE_CSR register */
- Value = RTMP_GetPhysicalAddressLow(pAd->RxRing.Cell[0].AllocPa);
- RTMP_IO_WRITE32(pAd, RX_BASE_PTR, Value);
- DBGPRINT(RT_DEBUG_TRACE, ("--> RX_BASE_PTR : 0x%x\n", Value));
-
- /* Init RX Ring index pointer */
- pAd->RxRing.RxSwReadIdx = 0;
- pAd->RxRing.RxCpuIdx = RX_RING_SIZE - 1;
- RTMP_IO_WRITE32(pAd, RX_CRX_IDX, pAd->RxRing.RxCpuIdx);
-
- /* Init TX rings index pointer */
- {
- for (i = 0; i < NUM_OF_TX_RING; i++) {
- pAd->TxRing[i].TxSwFreeIdx = 0;
- pAd->TxRing[i].TxCpuIdx = 0;
- RTMP_IO_WRITE32(pAd, (TX_CTX_IDX0 + i * 0x10),
- pAd->TxRing[i].TxCpuIdx);
- }
- }
-
- /* init MGMT ring index pointer */
- pAd->MgmtRing.TxSwFreeIdx = 0;
- pAd->MgmtRing.TxCpuIdx = 0;
- RTMP_IO_WRITE32(pAd, TX_MGMTCTX_IDX, pAd->MgmtRing.TxCpuIdx);
-
- /* */
- /* set each Ring's SIZE into ASIC. Descriptor Size is fixed by design. */
- /* */
-
- /* Write TX_RING_CSR0 register */
- Value = TX_RING_SIZE;
- RTMP_IO_WRITE32(pAd, TX_MAX_CNT0, Value);
- RTMP_IO_WRITE32(pAd, TX_MAX_CNT1, Value);
- RTMP_IO_WRITE32(pAd, TX_MAX_CNT2, Value);
- RTMP_IO_WRITE32(pAd, TX_MAX_CNT3, Value);
- RTMP_IO_WRITE32(pAd, TX_MAX_CNT4, Value);
- Value = MGMT_RING_SIZE;
- RTMP_IO_WRITE32(pAd, TX_MGMTMAX_CNT, Value);
-
- /* Write RX_RING_CSR register */
- Value = RX_RING_SIZE;
- RTMP_IO_WRITE32(pAd, RX_MAX_CNT, Value);
-#endif /* RTMP_MAC_PCI // */
-
- /* WMM parameter */
- csr0.word = 0;
- RTMP_IO_WRITE32(pAd, WMM_TXOP0_CFG, csr0.word);
- if (pAd->CommonCfg.PhyMode == PHY_11B) {
- csr0.field.Ac0Txop = 192; /* AC_VI: 192*32us ~= 6ms */
- csr0.field.Ac1Txop = 96; /* AC_VO: 96*32us ~= 3ms */
- } else {
- csr0.field.Ac0Txop = 96; /* AC_VI: 96*32us ~= 3ms */
- csr0.field.Ac1Txop = 48; /* AC_VO: 48*32us ~= 1.5ms */
- }
- RTMP_IO_WRITE32(pAd, WMM_TXOP1_CFG, csr0.word);
-
-#ifdef RTMP_MAC_PCI
- /* 3. Set DMA global configuration except TX_DMA_EN and RX_DMA_EN bits: */
- i = 0;
- do {
- RTMP_IO_READ32(pAd, WPDMA_GLO_CFG, &GloCfg.word);
- if ((GloCfg.field.TxDMABusy == 0)
- && (GloCfg.field.RxDMABusy == 0))
- break;
-
- RTMPusecDelay(1000);
- i++;
- } while (i < 100);
-
- GloCfg.word &= 0xff0;
- GloCfg.field.EnTXWriteBackDDONE = 1;
- RTMP_IO_WRITE32(pAd, WPDMA_GLO_CFG, GloCfg.word);
-
- IntCfg.word = 0;
- RTMP_IO_WRITE32(pAd, DELAY_INT_CFG, IntCfg.word);
-#endif /* RTMP_MAC_PCI // */
-
- /* reset action */
- /* Load firmware */
- /* Status = NICLoadFirmware(pAd); */
-
- DBGPRINT(RT_DEBUG_TRACE, ("<-- NICInitializeAdapter\n"));
- return Status;
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Initialize ASIC
-
- Arguments:
- Adapter Pointer to our adapter
-
- Return Value:
- None
-
- IRQL = PASSIVE_LEVEL
-
- Note:
-
- ========================================================================
-*/
-int NICInitializeAsic(struct rt_rtmp_adapter *pAd, IN BOOLEAN bHardReset)
-{
- unsigned long Index = 0;
- u8 R0 = 0xff;
- u32 MacCsr12 = 0, Counter = 0;
-#ifdef RTMP_MAC_USB
- u32 MacCsr0 = 0;
- int Status;
- u8 Value = 0xff;
-#endif /* RTMP_MAC_USB // */
-#ifdef RT30xx
- u8 bbpreg = 0;
- u8 RFValue = 0;
-#endif /* RT30xx // */
- u16 KeyIdx;
- int i, apidx;
-
- DBGPRINT(RT_DEBUG_TRACE, ("--> NICInitializeAsic\n"));
-
-#ifdef RTMP_MAC_PCI
- RTMP_IO_WRITE32(pAd, PWR_PIN_CFG, 0x3); /* To fix driver disable/enable hang issue when radio off */
- if (bHardReset == TRUE) {
- RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, 0x3);
- } else
- RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, 0x1);
-
- RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, 0x0);
- /* Initialize MAC register to default value */
- for (Index = 0; Index < NUM_MAC_REG_PARMS; Index++) {
- RTMP_IO_WRITE32(pAd, MACRegTable[Index].Register,
- MACRegTable[Index].Value);
- }
-
- {
- for (Index = 0; Index < NUM_STA_MAC_REG_PARMS; Index++) {
- RTMP_IO_WRITE32(pAd, STAMACRegTable[Index].Register,
- STAMACRegTable[Index].Value);
- }
- }
-#endif /* RTMP_MAC_PCI // */
-#ifdef RTMP_MAC_USB
- /* */
- /* Make sure MAC gets ready after NICLoadFirmware(). */
- /* */
- Index = 0;
-
- /*To avoid hang-on issue when interface up in kernel 2.4, */
- /*we use a local variable "MacCsr0" instead of using "pAd->MACVersion" directly. */
- do {
- RTMP_IO_READ32(pAd, MAC_CSR0, &MacCsr0);
-
- if ((MacCsr0 != 0x00) && (MacCsr0 != 0xFFFFFFFF))
- break;
-
- RTMPusecDelay(10);
- } while (Index++ < 100);
-
- pAd->MACVersion = MacCsr0;
- DBGPRINT(RT_DEBUG_TRACE,
- ("MAC_CSR0 [ Ver:Rev=0x%08x]\n", pAd->MACVersion));
- /* turn on bit13 (set to zero) after rt2860D. This is to solve high-current issue. */
- RTMP_IO_READ32(pAd, PBF_SYS_CTRL, &MacCsr12);
- MacCsr12 &= (~0x2000);
- RTMP_IO_WRITE32(pAd, PBF_SYS_CTRL, MacCsr12);
-
- RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, 0x3);
- RTMP_IO_WRITE32(pAd, USB_DMA_CFG, 0x0);
- Status = RTUSBVenderReset(pAd);
-
- RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, 0x0);
-
- /* Initialize MAC register to default value */
- for (Index = 0; Index < NUM_MAC_REG_PARMS; Index++) {
-#ifdef RT30xx
- if ((MACRegTable[Index].Register == TX_SW_CFG0)
- && (IS_RT3070(pAd) || IS_RT3071(pAd) || IS_RT3572(pAd)
- || IS_RT3090(pAd) || IS_RT3390(pAd))) {
- MACRegTable[Index].Value = 0x00000400;
- }
-#endif /* RT30xx // */
- RTMP_IO_WRITE32(pAd, (u16)MACRegTable[Index].Register,
- MACRegTable[Index].Value);
- }
-
- {
- for (Index = 0; Index < NUM_STA_MAC_REG_PARMS; Index++) {
- RTMP_IO_WRITE32(pAd,
- (u16)STAMACRegTable[Index].Register,
- STAMACRegTable[Index].Value);
- }
- }
-#endif /* RTMP_MAC_USB // */
-
-#ifdef RT30xx
- /* Initialize RT3070 serial MAC registers which is different from RT2870 serial */
- if (IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd)) {
- RTMP_IO_WRITE32(pAd, TX_SW_CFG1, 0);
-
- /* RT3071 version E has fixed this issue */
- if ((pAd->MACVersion & 0xffff) < 0x0211) {
- if (pAd->NicConfig2.field.DACTestBit == 1) {
- RTMP_IO_WRITE32(pAd, TX_SW_CFG2, 0x2C); /* To fix throughput drop drastically */
- } else {
- RTMP_IO_WRITE32(pAd, TX_SW_CFG2, 0x0F); /* To fix throughput drop drastically */
- }
- } else {
- RTMP_IO_WRITE32(pAd, TX_SW_CFG2, 0x0);
- }
- } else if (IS_RT3070(pAd)) {
- if (((pAd->MACVersion & 0xffff) < 0x0201)) {
- RTMP_IO_WRITE32(pAd, TX_SW_CFG1, 0);
- RTMP_IO_WRITE32(pAd, TX_SW_CFG2, 0x2C); /* To fix throughput drop drastically */
- } else {
- RTMP_IO_WRITE32(pAd, TX_SW_CFG2, 0);
- }
- }
-#endif /* RT30xx // */
-
- /* */
- /* Before program BBP, we need to wait BBP/RF get wake up. */
- /* */
- Index = 0;
- do {
- RTMP_IO_READ32(pAd, MAC_STATUS_CFG, &MacCsr12);
-
- if ((MacCsr12 & 0x03) == 0) /* if BB.RF is stable */
- break;
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("Check MAC_STATUS_CFG = Busy = %x\n", MacCsr12));
- RTMPusecDelay(1000);
- } while (Index++ < 100);
-
- /* The commands to firmware should be after these commands, these commands will init firmware */
- /* PCI and USB are not the same because PCI driver needs to wait for PCI bus ready */
- RTMP_IO_WRITE32(pAd, H2M_BBP_AGENT, 0); /* initialize BBP R/W access agent */
- RTMP_IO_WRITE32(pAd, H2M_MAILBOX_CSR, 0);
-#ifdef RT3090
- /*2008/11/28:KH add to fix the dead rf frequency offset bug<-- */
- AsicSendCommandToMcu(pAd, 0x72, 0, 0, 0);
- /*2008/11/28:KH add to fix the dead rf frequency offset bug--> */
-#endif /* RT3090 // */
- RTMPusecDelay(1000);
-
- /* Read BBP register, make sure BBP is up and running before write new data */
- Index = 0;
- do {
- RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R0, &R0);
- DBGPRINT(RT_DEBUG_TRACE, ("BBP version = %x\n", R0));
- } while ((++Index < 20) && ((R0 == 0xff) || (R0 == 0x00)));
- /*ASSERT(Index < 20); //this will cause BSOD on Check-build driver */
-
- if ((R0 == 0xff) || (R0 == 0x00))
- return NDIS_STATUS_FAILURE;
-
- /* Initialize BBP register to default value */
- for (Index = 0; Index < NUM_BBP_REG_PARMS; Index++) {
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBPRegTable[Index].Register,
- BBPRegTable[Index].Value);
- }
-
-#ifdef RTMP_MAC_PCI
- /* TODO: shiang, check MACVersion, currently, rbus-based chip use this. */
- if (pAd->MACVersion == 0x28720200) {
- /*u8 value; */
- unsigned long value2;
-
- /*disable MLD by Bruce 20080704 */
- /*BBP_IO_READ8_BY_REG_ID(pAd, BBP_R105, &value); */
- /*BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R105, value | 4); */
-
- /*Maximum PSDU length from 16K to 32K bytes */
- RTMP_IO_READ32(pAd, MAX_LEN_CFG, &value2);
- value2 &= ~(0x3 << 12);
- value2 |= (0x2 << 12);
- RTMP_IO_WRITE32(pAd, MAX_LEN_CFG, value2);
- }
-#endif /* RTMP_MAC_PCI // */
-
- /* for rt2860E and after, init BBP_R84 with 0x19. This is for extension channel overlapping IOT. */
- /* RT3090 should not program BBP R84 to 0x19, otherwise TX will block. */
- /*3070/71/72,3090,3090A( are included in RT30xx),3572,3390 */
- if (((pAd->MACVersion & 0xffff) != 0x0101)
- && !(IS_RT30xx(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd)))
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R84, 0x19);
-
-#ifdef RT30xx
-/* add by johnli, RF power sequence setup */
- if (IS_RT30xx(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd)) { /*update for RT3070/71/72/90/91/92,3572,3390. */
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R79, 0x13);
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R80, 0x05);
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R81, 0x33);
- }
-
- if (IS_RT3090(pAd) || IS_RT3390(pAd)) /* RT309x, RT3071/72 */
- {
- /* enable DC filter */
- if ((pAd->MACVersion & 0xffff) >= 0x0211) {
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R103, 0xc0);
- }
- /* improve power consumption */
- RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R138, &bbpreg);
- if (pAd->Antenna.field.TxPath == 1) {
- /* turn off tx DAC_1 */
- bbpreg = (bbpreg | 0x20);
- }
-
- if (pAd->Antenna.field.RxPath == 1) {
- /* turn off tx ADC_1 */
- bbpreg &= (~0x2);
- }
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R138, bbpreg);
-
- /* improve power consumption in RT3071 Ver.E */
- if ((pAd->MACVersion & 0xffff) >= 0x0211) {
- RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R31, &bbpreg);
- bbpreg &= (~0x3);
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R31, bbpreg);
- }
- } else if (IS_RT3070(pAd)) {
- if ((pAd->MACVersion & 0xffff) >= 0x0201) {
- /* enable DC filter */
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R103, 0xc0);
-
- /* improve power consumption in RT3070 Ver.F */
- RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R31, &bbpreg);
- bbpreg &= (~0x3);
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R31, bbpreg);
- }
- /* TX_LO1_en, RF R17 register Bit 3 to 0 */
- RT30xxReadRFRegister(pAd, RF_R17, &RFValue);
- RFValue &= (~0x08);
- /* to fix rx long range issue */
- if (pAd->NicConfig2.field.ExternalLNAForG == 0) {
- RFValue |= 0x20;
- }
- /* set RF_R17_bit[2:0] equal to EEPROM setting at 0x48h */
- if (pAd->TxMixerGain24G >= 1) {
- RFValue &= (~0x7); /* clean bit [2:0] */
- RFValue |= pAd->TxMixerGain24G;
- }
- RT30xxWriteRFRegister(pAd, RF_R17, RFValue);
- }
-/* end johnli */
-#endif /* RT30xx // */
-
- if (pAd->MACVersion == 0x28600100) {
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x16);
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, 0x12);
- }
-
- if (pAd->MACVersion >= RALINK_2880E_VERSION && pAd->MACVersion < RALINK_3070_VERSION) /* 3*3 */
- {
- /* enlarge MAX_LEN_CFG */
- u32 csr;
- RTMP_IO_READ32(pAd, MAX_LEN_CFG, &csr);
- csr &= 0xFFF;
- csr |= 0x2000;
- RTMP_IO_WRITE32(pAd, MAX_LEN_CFG, csr);
- }
-#ifdef RTMP_MAC_USB
- {
- u8 MAC_Value[] =
- { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0, 0 };
-
- /*Initialize WCID table */
- Value = 0xff;
- for (Index = 0; Index < 254; Index++) {
- RTUSBMultiWrite(pAd,
- (u16)(MAC_WCID_BASE + Index * 8),
- MAC_Value, 8);
- }
- }
-#endif /* RTMP_MAC_USB // */
-
- /* Add radio off control */
- {
- if (pAd->StaCfg.bRadio == FALSE) {
-/* RTMP_IO_WRITE32(pAd, PWR_PIN_CFG, 0x00001818); */
- RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_RADIO_OFF);
- DBGPRINT(RT_DEBUG_TRACE, ("Set Radio Off\n"));
- }
- }
-
- /* Clear raw counters */
- RTMP_IO_READ32(pAd, RX_STA_CNT0, &Counter);
- RTMP_IO_READ32(pAd, RX_STA_CNT1, &Counter);
- RTMP_IO_READ32(pAd, RX_STA_CNT2, &Counter);
- RTMP_IO_READ32(pAd, TX_STA_CNT0, &Counter);
- RTMP_IO_READ32(pAd, TX_STA_CNT1, &Counter);
- RTMP_IO_READ32(pAd, TX_STA_CNT2, &Counter);
-
- /* ASIC will keep garbage value after boot */
- /* Clear all shared key table when initial */
- /* This routine can be ignored in radio-ON/OFF operation. */
- if (bHardReset) {
- for (KeyIdx = 0; KeyIdx < 4; KeyIdx++) {
- RTMP_IO_WRITE32(pAd, SHARED_KEY_MODE_BASE + 4 * KeyIdx,
- 0);
- }
-
- /* Clear all pairwise key table when initial */
- for (KeyIdx = 0; KeyIdx < 256; KeyIdx++) {
- RTMP_IO_WRITE32(pAd,
- MAC_WCID_ATTRIBUTE_BASE +
- (KeyIdx * HW_WCID_ATTRI_SIZE), 1);
- }
- }
- /* assert HOST ready bit */
-/* RTMP_IO_WRITE32(pAd, MAC_CSR1, 0x0); // 2004-09-14 asked by Mark */
-/* RTMP_IO_WRITE32(pAd, MAC_CSR1, 0x4); */
-
- /* It isn't necessary to clear this space when not hard reset. */
- if (bHardReset == TRUE) {
- /* clear all on-chip BEACON frame space */
- for (apidx = 0; apidx < HW_BEACON_MAX_COUNT; apidx++) {
- for (i = 0; i < HW_BEACON_OFFSET >> 2; i += 4)
- RTMP_IO_WRITE32(pAd,
- pAd->BeaconOffset[apidx] + i,
- 0x00);
- }
- }
-#ifdef RTMP_MAC_USB
- AsicDisableSync(pAd);
- /* Clear raw counters */
- RTMP_IO_READ32(pAd, RX_STA_CNT0, &Counter);
- RTMP_IO_READ32(pAd, RX_STA_CNT1, &Counter);
- RTMP_IO_READ32(pAd, RX_STA_CNT2, &Counter);
- RTMP_IO_READ32(pAd, TX_STA_CNT0, &Counter);
- RTMP_IO_READ32(pAd, TX_STA_CNT1, &Counter);
- RTMP_IO_READ32(pAd, TX_STA_CNT2, &Counter);
- /* Default PCI clock cycle per ms is different as default setting, which is based on PCI. */
- RTMP_IO_READ32(pAd, USB_CYC_CFG, &Counter);
- Counter &= 0xffffff00;
- Counter |= 0x000001e;
- RTMP_IO_WRITE32(pAd, USB_CYC_CFG, Counter);
-#endif /* RTMP_MAC_USB // */
-
- {
- /* for rt2860E and after, init TXOP_CTRL_CFG with 0x583f. This is for extension channel overlapping IOT. */
- if ((pAd->MACVersion & 0xffff) != 0x0101)
- RTMP_IO_WRITE32(pAd, TXOP_CTRL_CFG, 0x583f);
- }
-
- DBGPRINT(RT_DEBUG_TRACE, ("<-- NICInitializeAsic\n"));
- return NDIS_STATUS_SUCCESS;
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Reset NIC Asics
-
- Arguments:
- Adapter Pointer to our adapter
-
- Return Value:
- None
-
- IRQL = PASSIVE_LEVEL
-
- Note:
- Reset NIC to initial state AS IS system boot up time.
-
- ========================================================================
-*/
-void NICIssueReset(struct rt_rtmp_adapter *pAd)
-{
- u32 Value = 0;
- DBGPRINT(RT_DEBUG_TRACE, ("--> NICIssueReset\n"));
-
- /* Abort Tx, prevent ASIC from writing to Host memory */
- /*RTMP_IO_WRITE32(pAd, TX_CNTL_CSR, 0x001f0000); */
-
- /* Disable Rx, register value supposed will remain after reset */
- RTMP_IO_READ32(pAd, MAC_SYS_CTRL, &Value);
- Value &= (0xfffffff3);
- RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, Value);
-
- /* Issue reset and clear from reset state */
- RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, 0x03); /* 2004-09-17 change from 0x01 */
- RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, 0x00);
-
- DBGPRINT(RT_DEBUG_TRACE, ("<-- NICIssueReset\n"));
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Check ASIC registers and find any reason the system might hang
-
- Arguments:
- Adapter Pointer to our adapter
-
- Return Value:
- None
-
- IRQL = DISPATCH_LEVEL
-
- ========================================================================
-*/
-BOOLEAN NICCheckForHang(struct rt_rtmp_adapter *pAd)
-{
- return (FALSE);
-}
-
-void NICUpdateFifoStaCounters(struct rt_rtmp_adapter *pAd)
-{
- TX_STA_FIFO_STRUC StaFifo;
- struct rt_mac_table_entry *pEntry;
- u8 i = 0;
- u8 pid = 0, wcid = 0;
- char reTry;
- u8 succMCS;
-
- do {
- RTMP_IO_READ32(pAd, TX_STA_FIFO, &StaFifo.word);
-
- if (StaFifo.field.bValid == 0)
- break;
-
- wcid = (u8)StaFifo.field.wcid;
-
- /* ignore NoACK and MGMT frame use 0xFF as WCID */
- if ((StaFifo.field.TxAckRequired == 0)
- || (wcid >= MAX_LEN_OF_MAC_TABLE)) {
- i++;
- continue;
- }
-
- /* PID store Tx MCS Rate */
- pid = (u8)StaFifo.field.PidType;
-
- pEntry = &pAd->MacTab.Content[wcid];
-
- pEntry->DebugFIFOCount++;
-
- if (StaFifo.field.TxBF) /* 3*3 */
- pEntry->TxBFCount++;
-
- if (!StaFifo.field.TxSuccess) {
- pEntry->FIFOCount++;
- pEntry->OneSecTxFailCount++;
-
- if (pEntry->FIFOCount >= 1) {
- DBGPRINT(RT_DEBUG_TRACE, ("#"));
- pEntry->NoBADataCountDown = 64;
-
- if (pEntry->PsMode == PWR_ACTIVE) {
- int tid;
- for (tid = 0; tid < NUM_OF_TID; tid++) {
- BAOriSessionTearDown(pAd,
- pEntry->
- Aid, tid,
- FALSE,
- FALSE);
- }
-
- /* Update the continuous transmission counter except PS mode */
- pEntry->ContinueTxFailCnt++;
- } else {
- /* Clear the FIFOCount when sta in Power Save mode. Basically we assume */
- /* this tx error happened due to sta just go to sleep. */
- pEntry->FIFOCount = 0;
- pEntry->ContinueTxFailCnt = 0;
- }
- /*pEntry->FIFOCount = 0; */
- }
- /*pEntry->bSendBAR = TRUE; */
- } else {
- if ((pEntry->PsMode != PWR_SAVE)
- && (pEntry->NoBADataCountDown > 0)) {
- pEntry->NoBADataCountDown--;
- if (pEntry->NoBADataCountDown == 0) {
- DBGPRINT(RT_DEBUG_TRACE, ("@\n"));
- }
- }
-
- pEntry->FIFOCount = 0;
- pEntry->OneSecTxNoRetryOkCount++;
- /* update NoDataIdleCount when successful send packet to STA. */
- pEntry->NoDataIdleCount = 0;
- pEntry->ContinueTxFailCnt = 0;
- }
-
- succMCS = StaFifo.field.SuccessRate & 0x7F;
-
- reTry = pid - succMCS;
-
- if (StaFifo.field.TxSuccess) {
- pEntry->TXMCSExpected[pid]++;
- if (pid == succMCS) {
- pEntry->TXMCSSuccessful[pid]++;
- } else {
- pEntry->TXMCSAutoFallBack[pid][succMCS]++;
- }
- } else {
- pEntry->TXMCSFailed[pid]++;
- }
-
- if (reTry > 0) {
- if ((pid >= 12) && succMCS <= 7) {
- reTry -= 4;
- }
- pEntry->OneSecTxRetryOkCount += reTry;
- }
-
- i++;
- /* ASIC store 16 stack */
- } while (i < (2 * TX_RING_SIZE));
-
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Read statistical counters from hardware registers and record them
- in software variables for later on query
-
- Arguments:
- pAd Pointer to our adapter
-
- Return Value:
- None
-
- IRQL = DISPATCH_LEVEL
-
- ========================================================================
-*/
-void NICUpdateRawCounters(struct rt_rtmp_adapter *pAd)
-{
- u32 OldValue; /*, Value2; */
- /*unsigned long PageSum, OneSecTransmitCount; */
- /*unsigned long TxErrorRatio, Retry, Fail; */
- RX_STA_CNT0_STRUC RxStaCnt0;
- RX_STA_CNT1_STRUC RxStaCnt1;
- RX_STA_CNT2_STRUC RxStaCnt2;
- TX_STA_CNT0_STRUC TxStaCnt0;
- TX_STA_CNT1_STRUC StaTx1;
- TX_STA_CNT2_STRUC StaTx2;
- TX_AGG_CNT_STRUC TxAggCnt;
- TX_AGG_CNT0_STRUC TxAggCnt0;
- TX_AGG_CNT1_STRUC TxAggCnt1;
- TX_AGG_CNT2_STRUC TxAggCnt2;
- TX_AGG_CNT3_STRUC TxAggCnt3;
- TX_AGG_CNT4_STRUC TxAggCnt4;
- TX_AGG_CNT5_STRUC TxAggCnt5;
- TX_AGG_CNT6_STRUC TxAggCnt6;
- TX_AGG_CNT7_STRUC TxAggCnt7;
- struct rt_counter_ralink *pRalinkCounters;
-
- pRalinkCounters = &pAd->RalinkCounters;
-
- RTMP_IO_READ32(pAd, RX_STA_CNT0, &RxStaCnt0.word);
- RTMP_IO_READ32(pAd, RX_STA_CNT2, &RxStaCnt2.word);
-
- {
- RTMP_IO_READ32(pAd, RX_STA_CNT1, &RxStaCnt1.word);
- /* Update RX PLCP error counter */
- pAd->PrivateInfo.PhyRxErrCnt += RxStaCnt1.field.PlcpErr;
- /* Update False CCA counter */
- pAd->RalinkCounters.OneSecFalseCCACnt +=
- RxStaCnt1.field.FalseCca;
- }
-
- /* Update FCS counters */
- OldValue = pAd->WlanCounters.FCSErrorCount.u.LowPart;
- pAd->WlanCounters.FCSErrorCount.u.LowPart += (RxStaCnt0.field.CrcErr); /* >> 7); */
- if (pAd->WlanCounters.FCSErrorCount.u.LowPart < OldValue)
- pAd->WlanCounters.FCSErrorCount.u.HighPart++;
-
- /* Add FCS error count to private counters */
- pRalinkCounters->OneSecRxFcsErrCnt += RxStaCnt0.field.CrcErr;
- OldValue = pRalinkCounters->RealFcsErrCount.u.LowPart;
- pRalinkCounters->RealFcsErrCount.u.LowPart += RxStaCnt0.field.CrcErr;
- if (pRalinkCounters->RealFcsErrCount.u.LowPart < OldValue)
- pRalinkCounters->RealFcsErrCount.u.HighPart++;
-
- /* Update Duplicate Rcv check */
- pRalinkCounters->DuplicateRcv += RxStaCnt2.field.RxDupliCount;
- pAd->WlanCounters.FrameDuplicateCount.u.LowPart +=
- RxStaCnt2.field.RxDupliCount;
- /* Update RX Overflow counter */
- pAd->Counters8023.RxNoBuffer += (RxStaCnt2.field.RxFifoOverflowCount);
-
- /*pAd->RalinkCounters.RxCount = 0; */
-#ifdef RTMP_MAC_USB
- if (pRalinkCounters->RxCount != pAd->watchDogRxCnt) {
- pAd->watchDogRxCnt = pRalinkCounters->RxCount;
- pAd->watchDogRxOverFlowCnt = 0;
- } else {
- if (RxStaCnt2.field.RxFifoOverflowCount)
- pAd->watchDogRxOverFlowCnt++;
- else
- pAd->watchDogRxOverFlowCnt = 0;
- }
-#endif /* RTMP_MAC_USB // */
-
- /*if (!OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_TX_RATE_SWITCH_ENABLED) || */
- /* (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_TX_RATE_SWITCH_ENABLED) && (pAd->MacTab.Size != 1))) */
- if (!pAd->bUpdateBcnCntDone) {
- /* Update BEACON sent count */
- RTMP_IO_READ32(pAd, TX_STA_CNT0, &TxStaCnt0.word);
- RTMP_IO_READ32(pAd, TX_STA_CNT1, &StaTx1.word);
- RTMP_IO_READ32(pAd, TX_STA_CNT2, &StaTx2.word);
- pRalinkCounters->OneSecBeaconSentCnt +=
- TxStaCnt0.field.TxBeaconCount;
- pRalinkCounters->OneSecTxRetryOkCount +=
- StaTx1.field.TxRetransmit;
- pRalinkCounters->OneSecTxNoRetryOkCount +=
- StaTx1.field.TxSuccess;
- pRalinkCounters->OneSecTxFailCount +=
- TxStaCnt0.field.TxFailCount;
- pAd->WlanCounters.TransmittedFragmentCount.u.LowPart +=
- StaTx1.field.TxSuccess;
- pAd->WlanCounters.RetryCount.u.LowPart +=
- StaTx1.field.TxRetransmit;
- pAd->WlanCounters.FailedCount.u.LowPart +=
- TxStaCnt0.field.TxFailCount;
- }
-
- /*if (pAd->bStaFifoTest == TRUE) */
- {
- RTMP_IO_READ32(pAd, TX_AGG_CNT, &TxAggCnt.word);
- RTMP_IO_READ32(pAd, TX_AGG_CNT0, &TxAggCnt0.word);
- RTMP_IO_READ32(pAd, TX_AGG_CNT1, &TxAggCnt1.word);
- RTMP_IO_READ32(pAd, TX_AGG_CNT2, &TxAggCnt2.word);
- RTMP_IO_READ32(pAd, TX_AGG_CNT3, &TxAggCnt3.word);
- RTMP_IO_READ32(pAd, TX_AGG_CNT4, &TxAggCnt4.word);
- RTMP_IO_READ32(pAd, TX_AGG_CNT5, &TxAggCnt5.word);
- RTMP_IO_READ32(pAd, TX_AGG_CNT6, &TxAggCnt6.word);
- RTMP_IO_READ32(pAd, TX_AGG_CNT7, &TxAggCnt7.word);
- pRalinkCounters->TxAggCount += TxAggCnt.field.AggTxCount;
- pRalinkCounters->TxNonAggCount += TxAggCnt.field.NonAggTxCount;
- pRalinkCounters->TxAgg1MPDUCount +=
- TxAggCnt0.field.AggSize1Count;
- pRalinkCounters->TxAgg2MPDUCount +=
- TxAggCnt0.field.AggSize2Count;
-
- pRalinkCounters->TxAgg3MPDUCount +=
- TxAggCnt1.field.AggSize3Count;
- pRalinkCounters->TxAgg4MPDUCount +=
- TxAggCnt1.field.AggSize4Count;
- pRalinkCounters->TxAgg5MPDUCount +=
- TxAggCnt2.field.AggSize5Count;
- pRalinkCounters->TxAgg6MPDUCount +=
- TxAggCnt2.field.AggSize6Count;
-
- pRalinkCounters->TxAgg7MPDUCount +=
- TxAggCnt3.field.AggSize7Count;
- pRalinkCounters->TxAgg8MPDUCount +=
- TxAggCnt3.field.AggSize8Count;
- pRalinkCounters->TxAgg9MPDUCount +=
- TxAggCnt4.field.AggSize9Count;
- pRalinkCounters->TxAgg10MPDUCount +=
- TxAggCnt4.field.AggSize10Count;
-
- pRalinkCounters->TxAgg11MPDUCount +=
- TxAggCnt5.field.AggSize11Count;
- pRalinkCounters->TxAgg12MPDUCount +=
- TxAggCnt5.field.AggSize12Count;
- pRalinkCounters->TxAgg13MPDUCount +=
- TxAggCnt6.field.AggSize13Count;
- pRalinkCounters->TxAgg14MPDUCount +=
- TxAggCnt6.field.AggSize14Count;
-
- pRalinkCounters->TxAgg15MPDUCount +=
- TxAggCnt7.field.AggSize15Count;
- pRalinkCounters->TxAgg16MPDUCount +=
- TxAggCnt7.field.AggSize16Count;
-
- /* Calculate the transmitted A-MPDU count */
- pRalinkCounters->TransmittedAMPDUCount.u.LowPart +=
- TxAggCnt0.field.AggSize1Count;
- pRalinkCounters->TransmittedAMPDUCount.u.LowPart +=
- (TxAggCnt0.field.AggSize2Count / 2);
-
- pRalinkCounters->TransmittedAMPDUCount.u.LowPart +=
- (TxAggCnt1.field.AggSize3Count / 3);
- pRalinkCounters->TransmittedAMPDUCount.u.LowPart +=
- (TxAggCnt1.field.AggSize4Count / 4);
-
- pRalinkCounters->TransmittedAMPDUCount.u.LowPart +=
- (TxAggCnt2.field.AggSize5Count / 5);
- pRalinkCounters->TransmittedAMPDUCount.u.LowPart +=
- (TxAggCnt2.field.AggSize6Count / 6);
-
- pRalinkCounters->TransmittedAMPDUCount.u.LowPart +=
- (TxAggCnt3.field.AggSize7Count / 7);
- pRalinkCounters->TransmittedAMPDUCount.u.LowPart +=
- (TxAggCnt3.field.AggSize8Count / 8);
-
- pRalinkCounters->TransmittedAMPDUCount.u.LowPart +=
- (TxAggCnt4.field.AggSize9Count / 9);
- pRalinkCounters->TransmittedAMPDUCount.u.LowPart +=
- (TxAggCnt4.field.AggSize10Count / 10);
-
- pRalinkCounters->TransmittedAMPDUCount.u.LowPart +=
- (TxAggCnt5.field.AggSize11Count / 11);
- pRalinkCounters->TransmittedAMPDUCount.u.LowPart +=
- (TxAggCnt5.field.AggSize12Count / 12);
-
- pRalinkCounters->TransmittedAMPDUCount.u.LowPart +=
- (TxAggCnt6.field.AggSize13Count / 13);
- pRalinkCounters->TransmittedAMPDUCount.u.LowPart +=
- (TxAggCnt6.field.AggSize14Count / 14);
-
- pRalinkCounters->TransmittedAMPDUCount.u.LowPart +=
- (TxAggCnt7.field.AggSize15Count / 15);
- pRalinkCounters->TransmittedAMPDUCount.u.LowPart +=
- (TxAggCnt7.field.AggSize16Count / 16);
- }
-
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Reset NIC from error
-
- Arguments:
- Adapter Pointer to our adapter
-
- Return Value:
- None
-
- IRQL = PASSIVE_LEVEL
-
- Note:
- Reset NIC from error state
-
- ========================================================================
-*/
-void NICResetFromError(struct rt_rtmp_adapter *pAd)
-{
- /* Reset BBP (according to alex, reset ASIC will force reset BBP */
- /* Therefore, skip the reset BBP */
- /* RTMP_IO_WRITE32(pAd, MAC_CSR1, 0x2); */
-
- RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, 0x1);
- /* Remove ASIC from reset state */
- RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, 0x0);
-
- NICInitializeAdapter(pAd, FALSE);
- NICInitAsicFromEEPROM(pAd);
-
- /* Switch to current channel, since during reset process, the connection should remains on. */
- AsicSwitchChannel(pAd, pAd->CommonCfg.CentralChannel, FALSE);
- AsicLockChannel(pAd, pAd->CommonCfg.CentralChannel);
-}
-
-int NICLoadFirmware(struct rt_rtmp_adapter *pAd)
-{
- int status = NDIS_STATUS_SUCCESS;
- if (pAd->chipOps.loadFirmware)
- status = pAd->chipOps.loadFirmware(pAd);
-
- return status;
-}
-
-/*
- ========================================================================
-
- Routine Description:
- erase 8051 firmware image in MAC ASIC
-
- Arguments:
- Adapter Pointer to our adapter
-
- IRQL = PASSIVE_LEVEL
-
- ========================================================================
-*/
-void NICEraseFirmware(struct rt_rtmp_adapter *pAd)
-{
- if (pAd->chipOps.eraseFirmware)
- pAd->chipOps.eraseFirmware(pAd);
-
-} /* End of NICEraseFirmware */
-
-/*
- ========================================================================
-
- Routine Description:
- Load Tx rate switching parameters
-
- Arguments:
- Adapter Pointer to our adapter
-
- Return Value:
- NDIS_STATUS_SUCCESS firmware image load ok
- NDIS_STATUS_FAILURE image not found
-
- IRQL = PASSIVE_LEVEL
-
- Rate Table Format:
- 1. (B0: Valid Item number) (B1:Initial item from zero)
- 2. Item Number(Dec) Mode(Hex) Current MCS(Dec) TrainUp(Dec) TrainDown(Dec)
-
- ========================================================================
-*/
-int NICLoadRateSwitchingParams(struct rt_rtmp_adapter *pAd)
-{
- return NDIS_STATUS_SUCCESS;
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Compare two memory block
-
- Arguments:
- pSrc1 Pointer to first memory address
- pSrc2 Pointer to second memory address
-
- Return Value:
- 0: memory is equal
- 1: pSrc1 memory is larger
- 2: pSrc2 memory is larger
-
- IRQL = DISPATCH_LEVEL
-
- Note:
-
- ========================================================================
-*/
-unsigned long RTMPCompareMemory(void *pSrc1, void *pSrc2, unsigned long Length)
-{
- u8 *pMem1;
- u8 *pMem2;
- unsigned long Index = 0;
-
- pMem1 = (u8 *)pSrc1;
- pMem2 = (u8 *)pSrc2;
-
- for (Index = 0; Index < Length; Index++) {
- if (pMem1[Index] > pMem2[Index])
- return (1);
- else if (pMem1[Index] < pMem2[Index])
- return (2);
- }
-
- /* Equal */
- return (0);
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Zero out memory block
-
- Arguments:
- pSrc1 Pointer to memory address
- Length Size
-
- Return Value:
- None
-
- IRQL = PASSIVE_LEVEL
- IRQL = DISPATCH_LEVEL
-
- Note:
-
- ========================================================================
-*/
-void RTMPZeroMemory(void *pSrc, unsigned long Length)
-{
- u8 *pMem;
- unsigned long Index = 0;
-
- pMem = (u8 *)pSrc;
-
- for (Index = 0; Index < Length; Index++) {
- pMem[Index] = 0x00;
- }
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Copy data from memory block 1 to memory block 2
-
- Arguments:
- pDest Pointer to destination memory address
- pSrc Pointer to source memory address
- Length Copy size
-
- Return Value:
- None
-
- IRQL = PASSIVE_LEVEL
- IRQL = DISPATCH_LEVEL
-
- Note:
-
- ========================================================================
-*/
-void RTMPMoveMemory(void *pDest, void *pSrc, unsigned long Length)
-{
- u8 *pMem1;
- u8 *pMem2;
- u32 Index;
-
- ASSERT((Length == 0) || (pDest && pSrc));
-
- pMem1 = (u8 *)pDest;
- pMem2 = (u8 *)pSrc;
-
- for (Index = 0; Index < Length; Index++) {
- pMem1[Index] = pMem2[Index];
- }
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Initialize port configuration structure
-
- Arguments:
- Adapter Pointer to our adapter
-
- Return Value:
- None
-
- IRQL = PASSIVE_LEVEL
-
- Note:
-
- ========================================================================
-*/
-void UserCfgInit(struct rt_rtmp_adapter *pAd)
-{
- u32 key_index, bss_index;
-
- DBGPRINT(RT_DEBUG_TRACE, ("--> UserCfgInit\n"));
-
- /* */
- /* part I. initialize common configuration */
- /* */
-#ifdef RTMP_MAC_USB
- pAd->BulkOutReq = 0;
-
- pAd->BulkOutComplete = 0;
- pAd->BulkOutCompleteOther = 0;
- pAd->BulkOutCompleteCancel = 0;
- pAd->BulkInReq = 0;
- pAd->BulkInComplete = 0;
- pAd->BulkInCompleteFail = 0;
-
- /*pAd->QuickTimerP = 100; */
- /*pAd->TurnAggrBulkInCount = 0; */
- pAd->bUsbTxBulkAggre = 0;
-
- /* init as unused value to ensure driver will set to MCU once. */
- pAd->LedIndicatorStrength = 0xFF;
-
- pAd->CommonCfg.MaxPktOneTxBulk = 2;
- pAd->CommonCfg.TxBulkFactor = 1;
- pAd->CommonCfg.RxBulkFactor = 1;
-
- pAd->CommonCfg.TxPower = 100; /*mW */
-
- NdisZeroMemory(&pAd->CommonCfg.IOTestParm,
- sizeof(pAd->CommonCfg.IOTestParm));
-#endif /* RTMP_MAC_USB // */
-
- for (key_index = 0; key_index < SHARE_KEY_NUM; key_index++) {
- for (bss_index = 0; bss_index < MAX_MBSSID_NUM; bss_index++) {
- pAd->SharedKey[bss_index][key_index].KeyLen = 0;
- pAd->SharedKey[bss_index][key_index].CipherAlg =
- CIPHER_NONE;
- }
- }
-
- pAd->EepromAccess = FALSE;
-
- pAd->Antenna.word = 0;
- pAd->CommonCfg.BBPCurrentBW = BW_20;
-
- pAd->LedCntl.word = 0;
-#ifdef RTMP_MAC_PCI
- pAd->LedIndicatorStrength = 0;
- pAd->RLnkCtrlOffset = 0;
- pAd->HostLnkCtrlOffset = 0;
- pAd->StaCfg.PSControl.field.EnableNewPS = TRUE;
- pAd->CheckDmaBusyCount = 0;
-#endif /* RTMP_MAC_PCI // */
-
- pAd->bAutoTxAgcA = FALSE; /* Default is OFF */
- pAd->bAutoTxAgcG = FALSE; /* Default is OFF */
- pAd->RfIcType = RFIC_2820;
-
- /* Init timer for reset complete event */
- pAd->CommonCfg.CentralChannel = 1;
- pAd->bForcePrintTX = FALSE;
- pAd->bForcePrintRX = FALSE;
- pAd->bStaFifoTest = FALSE;
- pAd->bProtectionTest = FALSE;
- pAd->CommonCfg.Dsifs = 10; /* in units of usec */
- pAd->CommonCfg.TxPower = 100; /*mW */
- pAd->CommonCfg.TxPowerPercentage = 0xffffffff; /* AUTO */
- pAd->CommonCfg.TxPowerDefault = 0xffffffff; /* AUTO */
- pAd->CommonCfg.TxPreamble = Rt802_11PreambleAuto; /* use Long preamble on TX by defaut */
- pAd->CommonCfg.bUseZeroToDisableFragment = FALSE;
- pAd->CommonCfg.RtsThreshold = 2347;
- pAd->CommonCfg.FragmentThreshold = 2346;
- pAd->CommonCfg.UseBGProtection = 0; /* 0: AUTO */
- pAd->CommonCfg.bEnableTxBurst = TRUE; /*0; */
- pAd->CommonCfg.PhyMode = 0xff; /* unknown */
- pAd->CommonCfg.BandState = UNKNOWN_BAND;
- pAd->CommonCfg.RadarDetect.CSPeriod = 10;
- pAd->CommonCfg.RadarDetect.CSCount = 0;
- pAd->CommonCfg.RadarDetect.RDMode = RD_NORMAL_MODE;
-
- pAd->CommonCfg.RadarDetect.ChMovingTime = 65;
- pAd->CommonCfg.RadarDetect.LongPulseRadarTh = 3;
- pAd->CommonCfg.bAPSDCapable = FALSE;
- pAd->CommonCfg.bNeedSendTriggerFrame = FALSE;
- pAd->CommonCfg.TriggerTimerCount = 0;
- pAd->CommonCfg.bAPSDForcePowerSave = FALSE;
- pAd->CommonCfg.bCountryFlag = FALSE;
- pAd->CommonCfg.TxStream = 0;
- pAd->CommonCfg.RxStream = 0;
-
- NdisZeroMemory(&pAd->BeaconTxWI, sizeof(pAd->BeaconTxWI));
-
- NdisZeroMemory(&pAd->CommonCfg.HtCapability,
- sizeof(pAd->CommonCfg.HtCapability));
- pAd->HTCEnable = FALSE;
- pAd->bBroadComHT = FALSE;
- pAd->CommonCfg.bRdg = FALSE;
-
- NdisZeroMemory(&pAd->CommonCfg.AddHTInfo,
- sizeof(pAd->CommonCfg.AddHTInfo));
- pAd->CommonCfg.BACapability.field.MMPSmode = MMPS_ENABLE;
- pAd->CommonCfg.BACapability.field.MpduDensity = 0;
- pAd->CommonCfg.BACapability.field.Policy = IMMED_BA;
- pAd->CommonCfg.BACapability.field.RxBAWinLimit = 64; /*32; */
- pAd->CommonCfg.BACapability.field.TxBAWinLimit = 64; /*32; */
- DBGPRINT(RT_DEBUG_TRACE,
- ("--> UserCfgInit. BACapability = 0x%x\n",
- pAd->CommonCfg.BACapability.word));
-
- pAd->CommonCfg.BACapability.field.AutoBA = FALSE;
- BATableInit(pAd, &pAd->BATable);
-
- pAd->CommonCfg.bExtChannelSwitchAnnouncement = 1;
- pAd->CommonCfg.bHTProtect = 1;
- pAd->CommonCfg.bMIMOPSEnable = TRUE;
- /*2008/11/05:KH add to support Antenna power-saving of AP<-- */
- pAd->CommonCfg.bGreenAPEnable = FALSE;
- /*2008/11/05:KH add to support Antenna power-saving of AP--> */
- pAd->CommonCfg.bBADecline = FALSE;
- pAd->CommonCfg.bDisableReordering = FALSE;
-
- if (pAd->MACVersion == 0x28720200) {
- pAd->CommonCfg.TxBASize = 13; /*by Jerry recommend */
- } else {
- pAd->CommonCfg.TxBASize = 7;
- }
-
- pAd->CommonCfg.REGBACapability.word = pAd->CommonCfg.BACapability.word;
-
- /*pAd->CommonCfg.HTPhyMode.field.BW = BW_20; */
- /*pAd->CommonCfg.HTPhyMode.field.MCS = MCS_AUTO; */
- /*pAd->CommonCfg.HTPhyMode.field.ShortGI = GI_800; */
- /*pAd->CommonCfg.HTPhyMode.field.STBC = STBC_NONE; */
- pAd->CommonCfg.TxRate = RATE_6;
-
- pAd->CommonCfg.MlmeTransmit.field.MCS = MCS_RATE_6;
- pAd->CommonCfg.MlmeTransmit.field.BW = BW_20;
- pAd->CommonCfg.MlmeTransmit.field.MODE = MODE_OFDM;
-
- pAd->CommonCfg.BeaconPeriod = 100; /* in mSec */
-
- /* */
- /* part II. initialize STA specific configuration */
- /* */
- {
- RX_FILTER_SET_FLAG(pAd, fRX_FILTER_ACCEPT_DIRECT);
- RX_FILTER_CLEAR_FLAG(pAd, fRX_FILTER_ACCEPT_MULTICAST);
- RX_FILTER_SET_FLAG(pAd, fRX_FILTER_ACCEPT_BROADCAST);
- RX_FILTER_SET_FLAG(pAd, fRX_FILTER_ACCEPT_ALL_MULTICAST);
-
- pAd->StaCfg.Psm = PWR_ACTIVE;
-
- pAd->StaCfg.OrigWepStatus = Ndis802_11EncryptionDisabled;
- pAd->StaCfg.PairCipher = Ndis802_11EncryptionDisabled;
- pAd->StaCfg.GroupCipher = Ndis802_11EncryptionDisabled;
- pAd->StaCfg.bMixCipher = FALSE;
- pAd->StaCfg.DefaultKeyId = 0;
-
- /* 802.1x port control */
- pAd->StaCfg.PrivacyFilter = Ndis802_11PrivFilter8021xWEP;
- pAd->StaCfg.PortSecured = WPA_802_1X_PORT_NOT_SECURED;
- pAd->StaCfg.LastMicErrorTime = 0;
- pAd->StaCfg.MicErrCnt = 0;
- pAd->StaCfg.bBlockAssoc = FALSE;
- pAd->StaCfg.WpaState = SS_NOTUSE;
-
- pAd->CommonCfg.NdisRadioStateOff = FALSE; /* New to support microsoft disable radio with OID command */
-
- pAd->StaCfg.RssiTrigger = 0;
- NdisZeroMemory(&pAd->StaCfg.RssiSample, sizeof(struct rt_rssi_sample));
- pAd->StaCfg.RssiTriggerMode =
- RSSI_TRIGGERED_UPON_BELOW_THRESHOLD;
- pAd->StaCfg.AtimWin = 0;
- pAd->StaCfg.DefaultListenCount = 3; /*default listen count; */
- pAd->StaCfg.BssType = BSS_INFRA; /* BSS_INFRA or BSS_ADHOC or BSS_MONITOR */
- pAd->StaCfg.bScanReqIsFromWebUI = FALSE;
- OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_DOZE);
- OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_WAKEUP_NOW);
-
- pAd->StaCfg.bAutoTxRateSwitch = TRUE;
- pAd->StaCfg.DesiredTransmitSetting.field.MCS = MCS_AUTO;
- }
-
-#ifdef PCIE_PS_SUPPORT
- pAd->brt30xxBanMcuCmd = FALSE;
- pAd->b3090ESpecialChip = FALSE;
-/*KH Debug:the following must be removed */
- pAd->StaCfg.PSControl.field.rt30xxPowerMode = 3;
- pAd->StaCfg.PSControl.field.rt30xxForceASPMTest = 0;
- pAd->StaCfg.PSControl.field.rt30xxFollowHostASPM = 1;
-#endif /* PCIE_PS_SUPPORT // */
-
- /* global variables mXXXX used in MAC protocol state machines */
- OPSTATUS_SET_FLAG(pAd, fOP_STATUS_RECEIVE_DTIM);
- OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_ADHOC_ON);
- OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_INFRA_ON);
-
- /* PHY specification */
- pAd->CommonCfg.PhyMode = PHY_11BG_MIXED; /* default PHY mode */
- OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_SHORT_PREAMBLE_INUSED); /* CCK use long preamble */
-
- {
- /* user desired power mode */
- pAd->StaCfg.WindowsPowerMode = Ndis802_11PowerModeCAM;
- pAd->StaCfg.WindowsBatteryPowerMode = Ndis802_11PowerModeCAM;
- pAd->StaCfg.bWindowsACCAMEnable = FALSE;
-
- RTMPInitTimer(pAd, &pAd->StaCfg.StaQuickResponeForRateUpTimer,
- GET_TIMER_FUNCTION(StaQuickResponeForRateUpExec),
- pAd, FALSE);
- pAd->StaCfg.StaQuickResponeForRateUpTimerRunning = FALSE;
-
- /* Patch for Ndtest */
- pAd->StaCfg.ScanCnt = 0;
-
- pAd->StaCfg.bHwRadio = TRUE; /* Default Hardware Radio status is On */
- pAd->StaCfg.bSwRadio = TRUE; /* Default Software Radio status is On */
- pAd->StaCfg.bRadio = TRUE; /* bHwRadio && bSwRadio */
- pAd->StaCfg.bHardwareRadio = FALSE; /* Default is OFF */
- pAd->StaCfg.bShowHiddenSSID = FALSE; /* Default no show */
-
- /* Nitro mode control */
- pAd->StaCfg.bAutoReconnect = TRUE;
-
- /* Save the init time as last scan time, the system should do scan after 2 seconds. */
- /* This patch is for driver wake up from standby mode, system will do scan right away. */
- NdisGetSystemUpTime(&pAd->StaCfg.LastScanTime);
- if (pAd->StaCfg.LastScanTime > 10 * OS_HZ)
- pAd->StaCfg.LastScanTime -= (10 * OS_HZ);
-
- NdisZeroMemory(pAd->nickname, IW_ESSID_MAX_SIZE + 1);
-#ifdef RTMP_MAC_PCI
- sprintf((char *)pAd->nickname, "RT2860STA");
-#endif /* RTMP_MAC_PCI // */
-#ifdef RTMP_MAC_USB
- sprintf((char *)pAd->nickname, "RT2870STA");
-#endif /* RTMP_MAC_USB // */
- RTMPInitTimer(pAd, &pAd->StaCfg.WpaDisassocAndBlockAssocTimer,
- GET_TIMER_FUNCTION(WpaDisassocApAndBlockAssoc),
- pAd, FALSE);
- pAd->StaCfg.IEEE8021X = FALSE;
- pAd->StaCfg.IEEE8021x_required_keys = FALSE;
- pAd->StaCfg.WpaSupplicantUP = WPA_SUPPLICANT_DISABLE;
- pAd->StaCfg.bRSN_IE_FromWpaSupplicant = FALSE;
- pAd->StaCfg.WpaSupplicantUP = WPA_SUPPLICANT_ENABLE;
-
- NdisZeroMemory(pAd->StaCfg.ReplayCounter, 8);
-
- pAd->StaCfg.bAutoConnectByBssid = FALSE;
- pAd->StaCfg.BeaconLostTime = BEACON_LOST_TIME;
- NdisZeroMemory(pAd->StaCfg.WpaPassPhrase, 64);
- pAd->StaCfg.WpaPassPhraseLen = 0;
- pAd->StaCfg.bAutoRoaming = FALSE;
- pAd->StaCfg.bForceTxBurst = FALSE;
- }
-
- /* Default for extra information is not valid */
- pAd->ExtraInfo = EXTRA_INFO_CLEAR;
-
- /* Default Config change flag */
- pAd->bConfigChanged = FALSE;
-
- /* */
- /* part III. AP configurations */
- /* */
-
- /* */
- /* part IV. others */
- /* */
- /* dynamic BBP R66:sensibity tuning to overcome background noise */
- pAd->BbpTuning.bEnable = TRUE;
- pAd->BbpTuning.FalseCcaLowerThreshold = 100;
- pAd->BbpTuning.FalseCcaUpperThreshold = 512;
- pAd->BbpTuning.R66Delta = 4;
- pAd->Mlme.bEnableAutoAntennaCheck = TRUE;
-
- /* */
- /* Also initial R66CurrentValue, RTUSBResumeMsduTransmission might use this value. */
- /* if not initial this value, the default value will be 0. */
- /* */
- pAd->BbpTuning.R66CurrentValue = 0x38;
-
- pAd->Bbp94 = BBPR94_DEFAULT;
- pAd->BbpForCCK = FALSE;
-
- /* Default is FALSE for test bit 1 */
- /*pAd->bTest1 = FALSE; */
-
- /* initialize MAC table and allocate spin lock */
- NdisZeroMemory(&pAd->MacTab, sizeof(struct rt_mac_table));
- InitializeQueueHeader(&pAd->MacTab.McastPsQueue);
- NdisAllocateSpinLock(&pAd->MacTabLock);
-
- /*RTMPInitTimer(pAd, &pAd->RECBATimer, RECBATimerTimeout, pAd, TRUE); */
- /*RTMPSetTimer(&pAd->RECBATimer, REORDER_EXEC_INTV); */
-
- pAd->CommonCfg.bWiFiTest = FALSE;
-#ifdef RTMP_MAC_PCI
- pAd->bPCIclkOff = FALSE;
-#endif /* RTMP_MAC_PCI // */
-
- RTMP_SET_PSFLAG(pAd, fRTMP_PS_CAN_GO_SLEEP);
- DBGPRINT(RT_DEBUG_TRACE, ("<-- UserCfgInit\n"));
-}
-
-/* IRQL = PASSIVE_LEVEL */
-/* */
-/* FUNCTION: AtoH(char *, u8 *, int) */
-/* */
-/* PURPOSE: Converts ascii string to network order hex */
-/* */
-/* PARAMETERS: */
-/* src - pointer to input ascii string */
-/* dest - pointer to output hex */
-/* destlen - size of dest */
-/* */
-/* COMMENTS: */
-/* */
-/* 2 ascii bytes make a hex byte so must put 1st ascii byte of pair */
-/* into upper nibble and 2nd ascii byte of pair into lower nibble. */
-/* */
-/* IRQL = PASSIVE_LEVEL */
-
-void AtoH(char *src, u8 *dest, int destlen)
-{
- char *srcptr;
- u8 *destTemp;
-
- srcptr = src;
- destTemp = (u8 *)dest;
-
- while (destlen--) {
- *destTemp = hex_to_bin(*srcptr++) << 4; /* Put 1st ascii byte in upper nibble. */
- *destTemp += hex_to_bin(*srcptr++); /* Add 2nd ascii byte to above. */
- destTemp++;
- }
-}
-
-/*+++Mark by shiang, not use now, need to remove after confirm */
-/*---Mark by shiang, not use now, need to remove after confirm */
-
-/*
- ========================================================================
-
- Routine Description:
- Init timer objects
-
- Arguments:
- pAd Pointer to our adapter
- pTimer Timer structure
- pTimerFunc Function to execute when timer expired
- Repeat Ture for period timer
-
- Return Value:
- None
-
- Note:
-
- ========================================================================
-*/
-void RTMPInitTimer(struct rt_rtmp_adapter *pAd,
- struct rt_ralink_timer *pTimer,
- void *pTimerFunc, void *pData, IN BOOLEAN Repeat)
-{
- /* */
- /* Set Valid to TRUE for later used. */
- /* It will crash if we cancel a timer or set a timer */
- /* that we haven't initialize before. */
- /* */
- pTimer->Valid = TRUE;
-
- pTimer->PeriodicType = Repeat;
- pTimer->State = FALSE;
- pTimer->cookie = (unsigned long)pData;
-
-#ifdef RTMP_TIMER_TASK_SUPPORT
- pTimer->pAd = pAd;
-#endif /* RTMP_TIMER_TASK_SUPPORT // */
-
- RTMP_OS_Init_Timer(pAd, &pTimer->TimerObj, pTimerFunc, (void *)pTimer);
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Init timer objects
-
- Arguments:
- pTimer Timer structure
- Value Timer value in milliseconds
-
- Return Value:
- None
-
- Note:
- To use this routine, must call RTMPInitTimer before.
-
- ========================================================================
-*/
-void RTMPSetTimer(struct rt_ralink_timer *pTimer, unsigned long Value)
-{
- if (pTimer->Valid) {
- pTimer->TimerValue = Value;
- pTimer->State = FALSE;
- if (pTimer->PeriodicType == TRUE) {
- pTimer->Repeat = TRUE;
- RTMP_SetPeriodicTimer(&pTimer->TimerObj, Value);
- } else {
- pTimer->Repeat = FALSE;
- RTMP_OS_Add_Timer(&pTimer->TimerObj, Value);
- }
- } else {
- DBGPRINT_ERR("RTMPSetTimer failed, Timer hasn't been initialize!\n");
- }
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Init timer objects
-
- Arguments:
- pTimer Timer structure
- Value Timer value in milliseconds
-
- Return Value:
- None
-
- Note:
- To use this routine, must call RTMPInitTimer before.
-
- ========================================================================
-*/
-void RTMPModTimer(struct rt_ralink_timer *pTimer, unsigned long Value)
-{
- BOOLEAN Cancel;
-
- if (pTimer->Valid) {
- pTimer->TimerValue = Value;
- pTimer->State = FALSE;
- if (pTimer->PeriodicType == TRUE) {
- RTMPCancelTimer(pTimer, &Cancel);
- RTMPSetTimer(pTimer, Value);
- } else {
- RTMP_OS_Mod_Timer(&pTimer->TimerObj, Value);
- }
- } else {
- DBGPRINT_ERR("RTMPModTimer failed, Timer hasn't been initialize!\n");
- }
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Cancel timer objects
-
- Arguments:
- Adapter Pointer to our adapter
-
- Return Value:
- None
-
- IRQL = PASSIVE_LEVEL
- IRQL = DISPATCH_LEVEL
-
- Note:
- 1.) To use this routine, must call RTMPInitTimer before.
- 2.) Reset NIC to initial state AS IS system boot up time.
-
- ========================================================================
-*/
-void RTMPCancelTimer(struct rt_ralink_timer *pTimer, OUT BOOLEAN * pCancelled)
-{
- if (pTimer->Valid) {
- if (pTimer->State == FALSE)
- pTimer->Repeat = FALSE;
-
- RTMP_OS_Del_Timer(&pTimer->TimerObj, pCancelled);
-
- if (*pCancelled == TRUE)
- pTimer->State = TRUE;
-
-#ifdef RTMP_TIMER_TASK_SUPPORT
- /* We need to go-through the TimerQ to findout this timer handler and remove it if */
- /* it's still waiting for execution. */
- RtmpTimerQRemove(pTimer->pAd, pTimer);
-#endif /* RTMP_TIMER_TASK_SUPPORT // */
- } else {
- DBGPRINT_ERR("RTMPCancelTimer failed, Timer hasn't been initialize!\n");
- }
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Set LED Status
-
- Arguments:
- pAd Pointer to our adapter
- Status LED Status
-
- Return Value:
- None
-
- IRQL = PASSIVE_LEVEL
- IRQL = DISPATCH_LEVEL
-
- Note:
-
- ========================================================================
-*/
-void RTMPSetLED(struct rt_rtmp_adapter *pAd, u8 Status)
-{
- /*unsigned long data; */
- u8 HighByte = 0;
- u8 LowByte;
-
- LowByte = pAd->LedCntl.field.LedMode & 0x7f;
- switch (Status) {
- case LED_LINK_DOWN:
- HighByte = 0x20;
- AsicSendCommandToMcu(pAd, 0x50, 0xff, LowByte, HighByte);
- pAd->LedIndicatorStrength = 0;
- break;
- case LED_LINK_UP:
- if (pAd->CommonCfg.Channel > 14)
- HighByte = 0xa0;
- else
- HighByte = 0x60;
- AsicSendCommandToMcu(pAd, 0x50, 0xff, LowByte, HighByte);
- break;
- case LED_RADIO_ON:
- HighByte = 0x20;
- AsicSendCommandToMcu(pAd, 0x50, 0xff, LowByte, HighByte);
- break;
- case LED_HALT:
- LowByte = 0; /* Driver sets MAC register and MAC controls LED */
- case LED_RADIO_OFF:
- HighByte = 0;
- AsicSendCommandToMcu(pAd, 0x50, 0xff, LowByte, HighByte);
- break;
- case LED_WPS:
- HighByte = 0x10;
- AsicSendCommandToMcu(pAd, 0x50, 0xff, LowByte, HighByte);
- break;
- case LED_ON_SITE_SURVEY:
- HighByte = 0x08;
- AsicSendCommandToMcu(pAd, 0x50, 0xff, LowByte, HighByte);
- break;
- case LED_POWER_UP:
- HighByte = 0x04;
- AsicSendCommandToMcu(pAd, 0x50, 0xff, LowByte, HighByte);
- break;
- default:
- DBGPRINT(RT_DEBUG_WARN,
- ("RTMPSetLED::Unknown Status %d\n", Status));
- break;
- }
-
- /* */
- /* Keep LED status for LED SiteSurvey mode. */
- /* After SiteSurvey, we will set the LED mode to previous status. */
- /* */
- if ((Status != LED_ON_SITE_SURVEY) && (Status != LED_POWER_UP))
- pAd->LedStatus = Status;
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("RTMPSetLED::Mode=%d,HighByte=0x%02x,LowByte=0x%02x\n",
- pAd->LedCntl.field.LedMode, HighByte, LowByte));
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Set LED Signal Strength
-
- Arguments:
- pAd Pointer to our adapter
- Dbm Signal Strength
-
- Return Value:
- None
-
- IRQL = PASSIVE_LEVEL
-
- Note:
- Can be run on any IRQL level.
-
- According to Microsoft Zero Config Wireless Signal Strength definition as belows.
- <= -90 No Signal
- <= -81 Very Low
- <= -71 Low
- <= -67 Good
- <= -57 Very Good
- > -57 Excellent
- ========================================================================
-*/
-void RTMPSetSignalLED(struct rt_rtmp_adapter *pAd, IN NDIS_802_11_RSSI Dbm)
-{
- u8 nLed = 0;
-
- if (pAd->LedCntl.field.LedMode == LED_MODE_SIGNAL_STREGTH) {
- if (Dbm <= -90)
- nLed = 0;
- else if (Dbm <= -81)
- nLed = 1;
- else if (Dbm <= -71)
- nLed = 3;
- else if (Dbm <= -67)
- nLed = 7;
- else if (Dbm <= -57)
- nLed = 15;
- else
- nLed = 31;
-
- /* */
- /* Update Signal Strength to firmware if changed. */
- /* */
- if (pAd->LedIndicatorStrength != nLed) {
- AsicSendCommandToMcu(pAd, 0x51, 0xff, nLed,
- pAd->LedCntl.field.Polarity);
- pAd->LedIndicatorStrength = nLed;
- }
- }
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Enable RX
-
- Arguments:
- pAd Pointer to our adapter
-
- Return Value:
- None
-
- IRQL <= DISPATCH_LEVEL
-
- Note:
- Before Enable RX, make sure you have enabled Interrupt.
- ========================================================================
-*/
-void RTMPEnableRxTx(struct rt_rtmp_adapter *pAd)
-{
-/* WPDMA_GLO_CFG_STRUC GloCfg; */
-/* unsigned long i = 0; */
- u32 rx_filter_flag;
-
- DBGPRINT(RT_DEBUG_TRACE, ("==> RTMPEnableRxTx\n"));
-
- /* Enable Rx DMA. */
- RT28XXDMAEnable(pAd);
-
- /* enable RX of MAC block */
- if (pAd->OpMode == OPMODE_AP) {
- rx_filter_flag = APNORMAL;
-
- RTMP_IO_WRITE32(pAd, RX_FILTR_CFG, rx_filter_flag); /* enable RX of DMA block */
- } else {
- if (pAd->CommonCfg.PSPXlink)
- rx_filter_flag = PSPXLINK;
- else
- rx_filter_flag = STANORMAL; /* Station not drop control frame will fail WiFi Certification. */
- RTMP_IO_WRITE32(pAd, RX_FILTR_CFG, rx_filter_flag);
- }
-
- RTMP_IO_WRITE32(pAd, MAC_SYS_CTRL, 0xc);
- DBGPRINT(RT_DEBUG_TRACE, ("<== RTMPEnableRxTx\n"));
-}
-
-/*+++Add by shiang, move from os/linux/rt_main_dev.c */
-void CfgInitHook(struct rt_rtmp_adapter *pAd)
-{
- pAd->bBroadComHT = TRUE;
-}
-
-int rt28xx_init(struct rt_rtmp_adapter *pAd,
- char *pDefaultMac, char *pHostName)
-{
- u32 index;
- u8 TmpPhy;
- int Status;
- u32 MacCsr0 = 0;
-
-#ifdef RTMP_MAC_PCI
- {
- /* If dirver doesn't wake up firmware here, */
- /* NICLoadFirmware will hang forever when interface is up again. */
- /* RT2860 PCI */
- if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_DOZE) &&
- OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_PCIE_DEVICE)) {
- AUTO_WAKEUP_STRUC AutoWakeupCfg;
- AsicForceWakeup(pAd, TRUE);
- AutoWakeupCfg.word = 0;
- RTMP_IO_WRITE32(pAd, AUTO_WAKEUP_CFG,
- AutoWakeupCfg.word);
- OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_DOZE);
- }
- }
-#endif /* RTMP_MAC_PCI // */
-
- /* reset Adapter flags */
- RTMP_CLEAR_FLAGS(pAd);
-
- /* Init BssTab & ChannelInfo tabbles for auto channel select. */
-
- /* Allocate BA Reordering memory */
- ba_reordering_resource_init(pAd, MAX_REORDERING_MPDU_NUM);
-
- /* Make sure MAC gets ready. */
- index = 0;
- do {
- RTMP_IO_READ32(pAd, MAC_CSR0, &MacCsr0);
- pAd->MACVersion = MacCsr0;
-
- if ((pAd->MACVersion != 0x00)
- && (pAd->MACVersion != 0xFFFFFFFF))
- break;
-
- RTMPusecDelay(10);
- } while (index++ < 100);
- DBGPRINT(RT_DEBUG_TRACE,
- ("MAC_CSR0 [ Ver:Rev=0x%08x]\n", pAd->MACVersion));
-
-#ifdef RTMP_MAC_PCI
-#ifdef PCIE_PS_SUPPORT
- /*Iverson patch PCIE L1 issue to make sure that driver can be read,write ,BBP and RF register at pcie L.1 level */
- if ((IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd))
- && OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_PCIE_DEVICE)) {
- RTMP_IO_READ32(pAd, AUX_CTRL, &MacCsr0);
- MacCsr0 |= 0x402;
- RTMP_IO_WRITE32(pAd, AUX_CTRL, MacCsr0);
- DBGPRINT(RT_DEBUG_TRACE, ("AUX_CTRL = 0x%x\n", MacCsr0));
- }
-#endif /* PCIE_PS_SUPPORT // */
-
- /* To fix driver disable/enable hang issue when radio off */
- RTMP_IO_WRITE32(pAd, PWR_PIN_CFG, 0x2);
-#endif /* RTMP_MAC_PCI // */
-
- /* Disable DMA */
- RT28XXDMADisable(pAd);
-
- /* Load 8051 firmware */
- Status = NICLoadFirmware(pAd);
- if (Status != NDIS_STATUS_SUCCESS) {
- DBGPRINT_ERR("NICLoadFirmware failed, Status[=0x%08x]\n", Status);
- goto err1;
- }
-
- NICLoadRateSwitchingParams(pAd);
-
- /* Disable interrupts here which is as soon as possible */
- /* This statement should never be true. We might consider to remove it later */
-#ifdef RTMP_MAC_PCI
- if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_ACTIVE)) {
- RTMP_ASIC_INTERRUPT_DISABLE(pAd);
- }
-#endif /* RTMP_MAC_PCI // */
-
- Status = RTMPAllocTxRxRingMemory(pAd);
- if (Status != NDIS_STATUS_SUCCESS) {
- DBGPRINT_ERR("RTMPAllocDMAMemory failed, Status[=0x%08x]\n", Status);
- goto err1;
- }
-
- RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_IN_USE);
-
- /* initialize MLME */
- /* */
-
- Status = RtmpMgmtTaskInit(pAd);
- if (Status != NDIS_STATUS_SUCCESS)
- goto err2;
-
- Status = MlmeInit(pAd);
- if (Status != NDIS_STATUS_SUCCESS) {
- DBGPRINT_ERR("MlmeInit failed, Status[=0x%08x]\n", Status);
- goto err2;
- }
- /* Initialize pAd->StaCfg, pAd->ApCfg, pAd->CommonCfg to manufacture default */
- /* */
- UserCfgInit(pAd);
- Status = RtmpNetTaskInit(pAd);
- if (Status != NDIS_STATUS_SUCCESS)
- goto err3;
-
-/* COPY_MAC_ADDR(pAd->ApCfg.MBSSID[apidx].Bssid, netif->hwaddr); */
-/* pAd->bForcePrintTX = TRUE; */
-
- CfgInitHook(pAd);
-
- NdisAllocateSpinLock(&pAd->MacTabLock);
-
- MeasureReqTabInit(pAd);
- TpcReqTabInit(pAd);
-
- /* */
- /* Init the hardware, we need to init asic before read registry, otherwise mac register will be reset */
- /* */
- Status = NICInitializeAdapter(pAd, TRUE);
- if (Status != NDIS_STATUS_SUCCESS) {
- DBGPRINT_ERR("NICInitializeAdapter failed, Status[=0x%08x]\n", Status);
- if (Status != NDIS_STATUS_SUCCESS)
- goto err3;
- }
-
- DBGPRINT(RT_DEBUG_OFF, ("1. Phy Mode = %d\n", pAd->CommonCfg.PhyMode));
-
-#ifdef RTMP_MAC_USB
- pAd->CommonCfg.bMultipleIRP = FALSE;
-
- if (pAd->CommonCfg.bMultipleIRP)
- pAd->CommonCfg.NumOfBulkInIRP = RX_RING_SIZE;
- else
- pAd->CommonCfg.NumOfBulkInIRP = 1;
-#endif /* RTMP_MAC_USB // */
-
- /*Init Ba Capability parameters. */
-/* RT28XX_BA_INIT(pAd); */
- pAd->CommonCfg.DesiredHtPhy.MpduDensity =
- (u8)pAd->CommonCfg.BACapability.field.MpduDensity;
- pAd->CommonCfg.DesiredHtPhy.AmsduEnable =
- (u16)pAd->CommonCfg.BACapability.field.AmsduEnable;
- pAd->CommonCfg.DesiredHtPhy.AmsduSize =
- (u16)pAd->CommonCfg.BACapability.field.AmsduSize;
- pAd->CommonCfg.DesiredHtPhy.MimoPs =
- (u16)pAd->CommonCfg.BACapability.field.MMPSmode;
- /* UPdata to HT IE */
- pAd->CommonCfg.HtCapability.HtCapInfo.MimoPs =
- (u16)pAd->CommonCfg.BACapability.field.MMPSmode;
- pAd->CommonCfg.HtCapability.HtCapInfo.AMsduSize =
- (u16)pAd->CommonCfg.BACapability.field.AmsduSize;
- pAd->CommonCfg.HtCapability.HtCapParm.MpduDensity =
- (u8)pAd->CommonCfg.BACapability.field.MpduDensity;
-
- /* after reading Registry, we now know if in AP mode or STA mode */
-
- /* Load 8051 firmware; crash when FW image not existent */
- /* Status = NICLoadFirmware(pAd); */
- /* if (Status != NDIS_STATUS_SUCCESS) */
- /* break; */
-
- DBGPRINT(RT_DEBUG_OFF, ("2. Phy Mode = %d\n", pAd->CommonCfg.PhyMode));
-
- /* We should read EEPROM for all cases. rt2860b */
- NICReadEEPROMParameters(pAd, (u8 *)pDefaultMac);
-
- DBGPRINT(RT_DEBUG_OFF, ("3. Phy Mode = %d\n", pAd->CommonCfg.PhyMode));
-
- NICInitAsicFromEEPROM(pAd); /*rt2860b */
-
- /* Set PHY to appropriate mode */
- TmpPhy = pAd->CommonCfg.PhyMode;
- pAd->CommonCfg.PhyMode = 0xff;
- RTMPSetPhyMode(pAd, TmpPhy);
- SetCommonHT(pAd);
-
- /* No valid channels. */
- if (pAd->ChannelListNum == 0) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("Wrong configuration. No valid channel found. Check \"ContryCode\" and \"ChannelGeography\" setting.\n"));
- goto err4;
- }
-
- DBGPRINT(RT_DEBUG_OFF,
- ("MCS Set = %02x %02x %02x %02x %02x\n",
- pAd->CommonCfg.HtCapability.MCSSet[0],
- pAd->CommonCfg.HtCapability.MCSSet[1],
- pAd->CommonCfg.HtCapability.MCSSet[2],
- pAd->CommonCfg.HtCapability.MCSSet[3],
- pAd->CommonCfg.HtCapability.MCSSet[4]));
-
-#ifdef RTMP_RF_RW_SUPPORT
- /*Init RT30xx RFRegisters after read RFIC type from EEPROM */
- NICInitRFRegisters(pAd);
-#endif /* RTMP_RF_RW_SUPPORT // */
-
-/* APInitialize(pAd); */
-
- /* */
- /* Initialize RF register to default value */
- /* */
- AsicSwitchChannel(pAd, pAd->CommonCfg.Channel, FALSE);
- AsicLockChannel(pAd, pAd->CommonCfg.Channel);
-
- /* 8051 firmware require the signal during booting time. */
- /*2008/11/28:KH marked the following codes to patch Frequency offset bug */
- /*AsicSendCommandToMcu(pAd, 0x72, 0xFF, 0x00, 0x00); */
-
- if (pAd && (Status != NDIS_STATUS_SUCCESS)) {
- /* */
- /* Undo everything if it failed */
- /* */
- if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_IN_USE)) {
-/* NdisMDeregisterInterrupt(&pAd->Interrupt); */
- RTMP_CLEAR_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_IN_USE);
- }
-/* RTMPFreeAdapter(pAd); // we will free it in disconnect() */
- } else if (pAd) {
- /* Microsoft HCT require driver send a disconnect event after driver initialization. */
- OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_MEDIA_STATE_CONNECTED);
-/* pAd->IndicateMediaState = NdisMediaStateDisconnected; */
- RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_MEDIA_STATE_CHANGE);
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("NDIS_STATUS_MEDIA_DISCONNECT Event B!\n"));
-
-#ifdef RTMP_MAC_USB
- RTMP_CLEAR_FLAG(pAd, fRTMP_ADAPTER_RESET_IN_PROGRESS);
- RTMP_CLEAR_FLAG(pAd, fRTMP_ADAPTER_REMOVE_IN_PROGRESS);
-
- /* */
- /* Support multiple BulkIn IRP, */
- /* the value on pAd->CommonCfg.NumOfBulkInIRP may be large than 1. */
- /* */
- for (index = 0; index < pAd->CommonCfg.NumOfBulkInIRP; index++) {
- RTUSBBulkReceive(pAd);
- DBGPRINT(RT_DEBUG_TRACE, ("RTUSBBulkReceive!\n"));
- }
-#endif /* RTMP_MAC_USB // */
- } /* end of else */
-
- /* Set up the Mac address */
- RtmpOSNetDevAddrSet(pAd->net_dev, &pAd->CurrentAddress[0]);
-
- DBGPRINT_S(Status, ("<==== rt28xx_init, Status=%x\n", Status));
-
- return TRUE;
-
-err4:
-err3:
- MlmeHalt(pAd);
-err2:
- RTMPFreeTxRxRingMemory(pAd);
-err1:
-
- os_free_mem(pAd, pAd->mpdu_blk_pool.mem); /* free BA pool */
-
- /* shall not set priv to NULL here because the priv didn't been free yet. */
- /*net_dev->ml_priv = 0; */
-#ifdef ST
-err0:
-#endif /* ST // */
-
- DBGPRINT(RT_DEBUG_ERROR, ("rt28xx Initialized fail!\n"));
- return FALSE;
-}
-
-/*---Add by shiang, move from os/linux/rt_main_dev.c */
-
-static int RtmpChipOpsRegister(struct rt_rtmp_adapter *pAd, int infType)
-{
- struct rt_rtmp_chip_op *pChipOps = &pAd->chipOps;
- int status;
-
- memset(pChipOps, 0, sizeof(struct rt_rtmp_chip_op));
-
- /* set eeprom related hook functions */
- status = RtmpChipOpsEepromHook(pAd, infType);
-
- /* set mcu related hook functions */
- switch (infType) {
-#ifdef RTMP_PCI_SUPPORT
- case RTMP_DEV_INF_PCI:
- pChipOps->loadFirmware = RtmpAsicLoadFirmware;
- pChipOps->eraseFirmware = RtmpAsicEraseFirmware;
- pChipOps->sendCommandToMcu = RtmpAsicSendCommandToMcu;
- break;
-#endif /* RTMP_PCI_SUPPORT // */
-#ifdef RTMP_USB_SUPPORT
- case RTMP_DEV_INF_USB:
- pChipOps->loadFirmware = RtmpAsicLoadFirmware;
- pChipOps->sendCommandToMcu = RtmpAsicSendCommandToMcu;
- break;
-#endif /* RTMP_USB_SUPPORT // */
- default:
- break;
- }
-
- return status;
-}
-
-int RtmpRaDevCtrlInit(struct rt_rtmp_adapter *pAd, IN RTMP_INF_TYPE infType)
-{
- /*void *handle; */
-
- /* Assign the interface type. We need use it when do register/EEPROM access. */
- pAd->infType = infType;
-
- pAd->OpMode = OPMODE_STA;
- DBGPRINT(RT_DEBUG_TRACE,
- ("STA Driver version-%s\n", STA_DRIVER_VERSION));
-
-#ifdef RTMP_MAC_USB
- sema_init(&(pAd->UsbVendorReq_semaphore), 1);
- os_alloc_mem(pAd, (u8 **) & pAd->UsbVendorReqBuf,
- MAX_PARAM_BUFFER_SIZE - 1);
- if (pAd->UsbVendorReqBuf == NULL) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("Allocate vendor request temp buffer failed!\n"));
- return FALSE;
- }
-#endif /* RTMP_MAC_USB // */
-
- RtmpChipOpsRegister(pAd, infType);
-
- return 0;
-}
-
-BOOLEAN RtmpRaDevCtrlExit(struct rt_rtmp_adapter *pAd)
-{
-
- RTMPFreeAdapter(pAd);
-
- return TRUE;
-}
-
-/* not yet support MBSS */
-struct net_device *get_netdev_from_bssid(struct rt_rtmp_adapter *pAd, u8 FromWhichBSSID)
-{
- struct net_device *dev_p = NULL;
-
- {
- dev_p = pAd->net_dev;
- }
-
- ASSERT(dev_p);
- return dev_p; /* return one of MBSS */
-}
diff --git a/drivers/staging/rt2860/common/rtmp_mcu.c b/drivers/staging/rt2860/common/rtmp_mcu.c
deleted file mode 100644
index 80fa416..0000000
--- a/drivers/staging/rt2860/common/rtmp_mcu.c
+++ /dev/null
@@ -1,336 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- rtmp_mcu.c
-
- Abstract:
- Miniport generic portion header file
-
- Revision History:
- Who When What
- -------- ---------- ----------------------------------------------
-*/
-
-#include "../rt_config.h"
-
-#include <linux/crc-ccitt.h>
-#include <linux/firmware.h>
-
-#ifdef RTMP_MAC_USB
-
-#define FIRMWAREIMAGE_LENGTH 0x1000
-
-#define FIRMWARE_2870_MIN_VERSION 12
-#define FIRMWARE_2870_FILENAME "rt2870.bin"
-MODULE_FIRMWARE(FIRMWARE_2870_FILENAME);
-
-#define FIRMWARE_3070_MIN_VERSION 17
-#define FIRMWARE_3070_FILENAME "rt3070.bin"
-MODULE_FIRMWARE(FIRMWARE_3070_FILENAME);
-
-#define FIRMWARE_3071_MIN_VERSION 17
-#define FIRMWARE_3071_FILENAME "rt3071.bin" /* for RT3071/RT3072 */
-MODULE_FIRMWARE(FIRMWARE_3071_FILENAME);
-
-#else /* RTMP_MAC_PCI */
-
-#define FIRMWAREIMAGE_LENGTH 0x2000
-
-#define FIRMWARE_2860_MIN_VERSION 11
-#define FIRMWARE_2860_FILENAME "rt2860.bin"
-MODULE_FIRMWARE(FIRMWARE_2860_FILENAME);
-
-#define FIRMWARE_3090_MIN_VERSION 19
-#define FIRMWARE_3090_FILENAME "rt3090.bin" /* for RT3090/RT3390 */
-MODULE_FIRMWARE(FIRMWARE_3090_FILENAME);
-
-#endif
-
-/*
- ========================================================================
-
- Routine Description:
- erase 8051 firmware image in MAC ASIC
-
- Arguments:
- Adapter Pointer to our adapter
-
- IRQL = PASSIVE_LEVEL
-
- ========================================================================
-*/
-int RtmpAsicEraseFirmware(struct rt_rtmp_adapter *pAd)
-{
- unsigned long i;
-
- for (i = 0; i < MAX_FIRMWARE_IMAGE_SIZE; i += 4)
- RTMP_IO_WRITE32(pAd, FIRMWARE_IMAGE_BASE + i, 0);
-
- return 0;
-}
-
-static const struct firmware *rtmp_get_firmware(struct rt_rtmp_adapter *adapter)
-{
- const char *name;
- const struct firmware *fw = NULL;
- u8 min_version;
- struct device *dev;
- int err;
-
- if (adapter->firmware)
- return adapter->firmware;
-
-#ifdef RTMP_MAC_USB
- if (IS_RT3071(adapter)) {
- name = FIRMWARE_3071_FILENAME;
- min_version = FIRMWARE_3071_MIN_VERSION;
- } else if (IS_RT3070(adapter)) {
- name = FIRMWARE_3070_FILENAME;
- min_version = FIRMWARE_3070_MIN_VERSION;
- } else {
- name = FIRMWARE_2870_FILENAME;
- min_version = FIRMWARE_2870_MIN_VERSION;
- }
- dev = &((struct os_cookie *)adapter->OS_Cookie)->pUsb_Dev->dev;
-#else /* RTMP_MAC_PCI */
- if (IS_RT3090(adapter) || IS_RT3390(adapter)) {
- name = FIRMWARE_3090_FILENAME;
- min_version = FIRMWARE_3090_MIN_VERSION;
- } else {
- name = FIRMWARE_2860_FILENAME;
- min_version = FIRMWARE_2860_MIN_VERSION;
- }
- dev = &((struct os_cookie *)adapter->OS_Cookie)->pci_dev->dev;
-#endif
-
- err = request_firmware(&fw, name, dev);
- if (err) {
- dev_err(dev, "firmware file %s request failed (%d)\n",
- name, err);
- return NULL;
- }
-
- if (fw->size < FIRMWAREIMAGE_LENGTH) {
- dev_err(dev, "firmware file %s size is invalid\n", name);
- goto invalid;
- }
-
- /* is it new enough? */
- adapter->FirmwareVersion = fw->data[FIRMWAREIMAGE_LENGTH - 3];
- if (adapter->FirmwareVersion < min_version) {
- dev_err(dev,
- "firmware file %s is too old;"
- " driver requires v%d or later\n",
- name, min_version);
- goto invalid;
- }
-
- /* is the internal CRC correct? */
- if (crc_ccitt(0xffff, fw->data, FIRMWAREIMAGE_LENGTH - 2) !=
- (fw->data[FIRMWAREIMAGE_LENGTH - 2] |
- (fw->data[FIRMWAREIMAGE_LENGTH - 1] << 8))) {
- dev_err(dev, "firmware file %s failed internal CRC\n", name);
- goto invalid;
- }
-
- adapter->firmware = fw;
- return fw;
-
-invalid:
- release_firmware(fw);
- return NULL;
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Load 8051 firmware file into MAC ASIC
-
- Arguments:
- Adapter Pointer to our adapter
-
- Return Value:
- NDIS_STATUS_SUCCESS firmware image load ok
- NDIS_STATUS_FAILURE image not found
-
- IRQL = PASSIVE_LEVEL
-
- ========================================================================
-*/
-int RtmpAsicLoadFirmware(struct rt_rtmp_adapter *pAd)
-{
- const struct firmware *fw;
- int Status = NDIS_STATUS_SUCCESS;
- unsigned long Index;
- u32 MacReg = 0;
-
- fw = rtmp_get_firmware(pAd);
- if (!fw)
- return NDIS_STATUS_FAILURE;
-
- RTMP_WRITE_FIRMWARE(pAd, fw->data, FIRMWAREIMAGE_LENGTH);
-
- /* check if MCU is ready */
- Index = 0;
- do {
- RTMP_IO_READ32(pAd, PBF_SYS_CTRL, &MacReg);
-
- if (MacReg & 0x80)
- break;
-
- RTMPusecDelay(1000);
- } while (Index++ < 1000);
-
- if (Index > 1000) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("NICLoadFirmware: MCU is not ready\n"));
- Status = NDIS_STATUS_FAILURE;
- }
-
- DBGPRINT(RT_DEBUG_TRACE, ("<=== %s (status=%d)\n", __func__, Status));
-
- return Status;
-}
-
-int RtmpAsicSendCommandToMcu(struct rt_rtmp_adapter *pAd,
- u8 Command,
- u8 Token, u8 Arg0, u8 Arg1)
-{
- HOST_CMD_CSR_STRUC H2MCmd;
- H2M_MAILBOX_STRUC H2MMailbox;
- unsigned long i = 0;
-
-#ifdef PCIE_PS_SUPPORT
- /* 3090F power solution 3 has hw limitation that needs to ban all mcu command */
- /* when firmware is in radio state. For other chip doesn't have this limitation. */
- if (((IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd))
- && IS_VERSION_AFTER_F(pAd)) && IS_VERSION_AFTER_F(pAd)
- && (pAd->StaCfg.PSControl.field.rt30xxPowerMode == 3)
- && (pAd->StaCfg.PSControl.field.EnableNewPS == TRUE)) {
- RTMP_SEM_LOCK(&pAd->McuCmdLock);
- if ((pAd->brt30xxBanMcuCmd == TRUE)
- && (Command != WAKE_MCU_CMD) && (Command != RFOFF_MCU_CMD)) {
- RTMP_SEM_UNLOCK(&pAd->McuCmdLock);
- DBGPRINT(RT_DEBUG_TRACE,
- (" Ban Mcu Cmd %x in sleep mode\n", Command));
- return FALSE;
- } else if ((Command == SLEEP_MCU_CMD)
- || (Command == RFOFF_MCU_CMD)) {
- pAd->brt30xxBanMcuCmd = TRUE;
- } else if (Command != WAKE_MCU_CMD) {
- pAd->brt30xxBanMcuCmd = FALSE;
- }
-
- RTMP_SEM_UNLOCK(&pAd->McuCmdLock);
-
- }
- if (((IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd))
- && IS_VERSION_AFTER_F(pAd)) && IS_VERSION_AFTER_F(pAd)
- && (pAd->StaCfg.PSControl.field.rt30xxPowerMode == 3)
- && (pAd->StaCfg.PSControl.field.EnableNewPS == TRUE)
- && (Command == WAKE_MCU_CMD)) {
-
- do {
- RTMP_IO_FORCE_READ32(pAd, H2M_MAILBOX_CSR,
- &H2MMailbox.word);
- if (H2MMailbox.field.Owner == 0)
- break;
-
- RTMPusecDelay(2);
- DBGPRINT(RT_DEBUG_INFO,
- ("AsicSendCommanToMcu::Mail box is busy\n"));
- } while (i++ < 100);
-
- if (i > 100) {
- DBGPRINT_ERR("H2M_MAILBOX still hold by MCU. command fail\n");
- return FALSE;
- }
-
- H2MMailbox.field.Owner = 1; /* pass ownership to MCU */
- H2MMailbox.field.CmdToken = Token;
- H2MMailbox.field.HighByte = Arg1;
- H2MMailbox.field.LowByte = Arg0;
- RTMP_IO_FORCE_WRITE32(pAd, H2M_MAILBOX_CSR, H2MMailbox.word);
-
- H2MCmd.word = 0;
- H2MCmd.field.HostCommand = Command;
- RTMP_IO_FORCE_WRITE32(pAd, HOST_CMD_CSR, H2MCmd.word);
-
- } else
-#endif /* PCIE_PS_SUPPORT // */
- {
- do {
- RTMP_IO_READ32(pAd, H2M_MAILBOX_CSR, &H2MMailbox.word);
- if (H2MMailbox.field.Owner == 0)
- break;
-
- RTMPusecDelay(2);
- } while (i++ < 100);
-
- if (i > 100) {
-#ifdef RTMP_MAC_PCI
-#endif /* RTMP_MAC_PCI // */
- {
- DBGPRINT_ERR("H2M_MAILBOX still hold by MCU. command fail\n");
- }
- return FALSE;
- }
-#ifdef RTMP_MAC_PCI
-#endif /* RTMP_MAC_PCI // */
-
- H2MMailbox.field.Owner = 1; /* pass ownership to MCU */
- H2MMailbox.field.CmdToken = Token;
- H2MMailbox.field.HighByte = Arg1;
- H2MMailbox.field.LowByte = Arg0;
- RTMP_IO_WRITE32(pAd, H2M_MAILBOX_CSR, H2MMailbox.word);
-
- H2MCmd.word = 0;
- H2MCmd.field.HostCommand = Command;
- RTMP_IO_WRITE32(pAd, HOST_CMD_CSR, H2MCmd.word);
-
- if (Command != 0x80) {
- }
- }
-#ifdef PCIE_PS_SUPPORT
- /* 3090 MCU Wakeup command needs more time to be stable. */
- /* Before stable, don't issue other MCU command to prevent from firmware error. */
- if (((IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd))
- && IS_VERSION_AFTER_F(pAd)) && IS_VERSION_AFTER_F(pAd)
- && (pAd->StaCfg.PSControl.field.rt30xxPowerMode == 3)
- && (pAd->StaCfg.PSControl.field.EnableNewPS == TRUE)
- && (Command == WAKE_MCU_CMD)) {
- RTMPusecDelay(2000);
- /*Put this is after RF programming. */
- /*NdisAcquireSpinLock(&pAd->McuCmdLock); */
- /*pAd->brt30xxBanMcuCmd = FALSE; */
- /*NdisReleaseSpinLock(&pAd->McuCmdLock); */
- }
-#endif /* PCIE_PS_SUPPORT // */
-
- return TRUE;
-}
diff --git a/drivers/staging/rt2860/common/rtmp_timer.c b/drivers/staging/rt2860/common/rtmp_timer.c
deleted file mode 100644
index ab52090..0000000
--- a/drivers/staging/rt2860/common/rtmp_timer.c
+++ /dev/null
@@ -1,302 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- rtmp_timer.c
-
- Abstract:
- task for timer handling
-
- Revision History:
- Who When What
- -------- ---------- ----------------------------------------------
- Name Date Modification logs
- Shiang Tu 08-28-2008 init version
-
-*/
-
-#include "../rt_config.h"
-
-BUILD_TIMER_FUNCTION(MlmePeriodicExec);
-/*BUILD_TIMER_FUNCTION(MlmeRssiReportExec); */
-BUILD_TIMER_FUNCTION(AsicRxAntEvalTimeout);
-BUILD_TIMER_FUNCTION(APSDPeriodicExec);
-BUILD_TIMER_FUNCTION(AsicRfTuningExec);
-#ifdef RTMP_MAC_USB
-BUILD_TIMER_FUNCTION(BeaconUpdateExec);
-#endif /* RTMP_MAC_USB // */
-
-BUILD_TIMER_FUNCTION(BeaconTimeout);
-BUILD_TIMER_FUNCTION(ScanTimeout);
-BUILD_TIMER_FUNCTION(AuthTimeout);
-BUILD_TIMER_FUNCTION(AssocTimeout);
-BUILD_TIMER_FUNCTION(ReassocTimeout);
-BUILD_TIMER_FUNCTION(DisassocTimeout);
-BUILD_TIMER_FUNCTION(LinkDownExec);
-BUILD_TIMER_FUNCTION(StaQuickResponeForRateUpExec);
-BUILD_TIMER_FUNCTION(WpaDisassocApAndBlockAssoc);
-#ifdef RTMP_MAC_PCI
-BUILD_TIMER_FUNCTION(PsPollWakeExec);
-BUILD_TIMER_FUNCTION(RadioOnExec);
-#endif /* RTMP_MAC_PCI // */
-#ifdef RTMP_MAC_USB
-BUILD_TIMER_FUNCTION(RtmpUsbStaAsicForceWakeupTimeout);
-#endif /* RTMP_MAC_USB // */
-
-#if defined(AP_LED) || defined(STA_LED)
-extern void LedCtrlMain(void *SystemSpecific1,
- void *FunctionContext,
- void *SystemSpecific2, void *SystemSpecific3);
-BUILD_TIMER_FUNCTION(LedCtrlMain);
-#endif
-
-#ifdef RTMP_TIMER_TASK_SUPPORT
-static void RtmpTimerQHandle(struct rt_rtmp_adapter *pAd)
-{
-#ifndef KTHREAD_SUPPORT
- int status;
-#endif
- struct rt_ralink_timer *pTimer;
- struct rt_rtmp_timer_task_entry *pEntry;
- unsigned long irqFlag;
- struct rt_rtmp_os_task *pTask;
-
- pTask = &pAd->timerTask;
- while (!pTask->task_killed) {
- pTimer = NULL;
-
-#ifdef KTHREAD_SUPPORT
- RTMP_WAIT_EVENT_INTERRUPTIBLE(pAd, pTask);
-#else
- RTMP_SEM_EVENT_WAIT(&(pTask->taskSema), status);
-#endif
-
- if (pAd->TimerQ.status == RTMP_TASK_STAT_STOPED)
- break;
-
- /* event happened. */
- while (pAd->TimerQ.pQHead) {
- RTMP_INT_LOCK(&pAd->TimerQLock, irqFlag);
- pEntry = pAd->TimerQ.pQHead;
- if (pEntry) {
- pTimer = pEntry->pRaTimer;
-
- /* update pQHead */
- pAd->TimerQ.pQHead = pEntry->pNext;
- if (pEntry == pAd->TimerQ.pQTail)
- pAd->TimerQ.pQTail = NULL;
-
- /* return this queue entry to timerQFreeList. */
- pEntry->pNext = pAd->TimerQ.pQPollFreeList;
- pAd->TimerQ.pQPollFreeList = pEntry;
- }
- RTMP_INT_UNLOCK(&pAd->TimerQLock, irqFlag);
-
- if (pTimer) {
- if ((pTimer->handle != NULL)
- && (!pAd->PM_FlgSuspend))
- pTimer->handle(NULL,
- (void *)pTimer->cookie,
- NULL, pTimer);
- if ((pTimer->Repeat)
- && (pTimer->State == FALSE))
- RTMP_OS_Add_Timer(&pTimer->TimerObj,
- pTimer->TimerValue);
- }
- }
-
-#ifndef KTHREAD_SUPPORT
- if (status != 0) {
- pAd->TimerQ.status = RTMP_TASK_STAT_STOPED;
- RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS);
- break;
- }
-#endif
- }
-}
-
-int RtmpTimerQThread(IN void *Context)
-{
- struct rt_rtmp_os_task *pTask;
- struct rt_rtmp_adapter *pAd;
-
- pTask = Context;
- pAd = pTask->priv;
-
- RtmpOSTaskCustomize(pTask);
-
- RtmpTimerQHandle(pAd);
-
- DBGPRINT(RT_DEBUG_TRACE, ("<---%s\n", __func__));
-#ifndef KTHREAD_SUPPORT
- pTask->taskPID = THREAD_PID_INIT_VALUE;
-#endif
- /* notify the exit routine that we're actually exiting now
- *
- * complete()/wait_for_completion() is similar to up()/down(),
- * except that complete() is safe in the case where the structure
- * is getting deleted in a parallel mode of execution (i.e. just
- * after the down() -- that's necessary for the thread-shutdown
- * case.
- *
- * complete_and_exit() goes even further than this -- it is safe in
- * the case that the thread of the caller is going away (not just
- * the structure) -- this is necessary for the module-remove case.
- * This is important in preemption kernels, which transfer the flow
- * of execution immediately upon a complete().
- */
- RtmpOSTaskNotifyToExit(pTask);
-
- return 0;
-
-}
-
-struct rt_rtmp_timer_task_entry *RtmpTimerQInsert(struct rt_rtmp_adapter *pAd,
- struct rt_ralink_timer *pTimer)
-{
- struct rt_rtmp_timer_task_entry *pQNode = NULL, *pQTail;
- unsigned long irqFlags;
- struct rt_rtmp_os_task *pTask = &pAd->timerTask;
-
- RTMP_INT_LOCK(&pAd->TimerQLock, irqFlags);
- if (pAd->TimerQ.status & RTMP_TASK_CAN_DO_INSERT) {
- if (pAd->TimerQ.pQPollFreeList) {
- pQNode = pAd->TimerQ.pQPollFreeList;
- pAd->TimerQ.pQPollFreeList = pQNode->pNext;
-
- pQNode->pRaTimer = pTimer;
- pQNode->pNext = NULL;
-
- pQTail = pAd->TimerQ.pQTail;
- if (pAd->TimerQ.pQTail != NULL)
- pQTail->pNext = pQNode;
- pAd->TimerQ.pQTail = pQNode;
- if (pAd->TimerQ.pQHead == NULL)
- pAd->TimerQ.pQHead = pQNode;
- }
- }
- RTMP_INT_UNLOCK(&pAd->TimerQLock, irqFlags);
-
- if (pQNode) {
-#ifdef KTHREAD_SUPPORT
- WAKE_UP(pTask);
-#else
- RTMP_SEM_EVENT_UP(&pTask->taskSema);
-#endif
- }
-
- return pQNode;
-}
-
-BOOLEAN RtmpTimerQRemove(struct rt_rtmp_adapter *pAd, struct rt_ralink_timer *pTimer)
-{
- struct rt_rtmp_timer_task_entry *pNode, *pPrev = NULL;
- unsigned long irqFlags;
-
- RTMP_INT_LOCK(&pAd->TimerQLock, irqFlags);
- if (pAd->TimerQ.status >= RTMP_TASK_STAT_INITED) {
- pNode = pAd->TimerQ.pQHead;
- while (pNode) {
- if (pNode->pRaTimer == pTimer)
- break;
- pPrev = pNode;
- pNode = pNode->pNext;
- }
-
- /* Now move it to freeList queue. */
- if (pNode) {
- if (pNode == pAd->TimerQ.pQHead)
- pAd->TimerQ.pQHead = pNode->pNext;
- if (pNode == pAd->TimerQ.pQTail)
- pAd->TimerQ.pQTail = pPrev;
- if (pPrev != NULL)
- pPrev->pNext = pNode->pNext;
-
- /* return this queue entry to timerQFreeList. */
- pNode->pNext = pAd->TimerQ.pQPollFreeList;
- pAd->TimerQ.pQPollFreeList = pNode;
- }
- }
- RTMP_INT_UNLOCK(&pAd->TimerQLock, irqFlags);
-
- return TRUE;
-}
-
-void RtmpTimerQExit(struct rt_rtmp_adapter *pAd)
-{
- struct rt_rtmp_timer_task_entry *pTimerQ;
- unsigned long irqFlags;
-
- RTMP_INT_LOCK(&pAd->TimerQLock, irqFlags);
- while (pAd->TimerQ.pQHead) {
- pTimerQ = pAd->TimerQ.pQHead;
- pAd->TimerQ.pQHead = pTimerQ->pNext;
- /* remove the timeQ */
- }
- pAd->TimerQ.pQPollFreeList = NULL;
- os_free_mem(pAd, pAd->TimerQ.pTimerQPoll);
- pAd->TimerQ.pQTail = NULL;
- pAd->TimerQ.pQHead = NULL;
-#ifndef KTHREAD_SUPPORT
- pAd->TimerQ.status = RTMP_TASK_STAT_STOPED;
-#endif
- RTMP_INT_UNLOCK(&pAd->TimerQLock, irqFlags);
-
-}
-
-void RtmpTimerQInit(struct rt_rtmp_adapter *pAd)
-{
- int i;
- struct rt_rtmp_timer_task_entry *pQNode, *pEntry;
- unsigned long irqFlags;
-
- NdisAllocateSpinLock(&pAd->TimerQLock);
-
- NdisZeroMemory(&pAd->TimerQ, sizeof(pAd->TimerQ));
-
- os_alloc_mem(pAd, &pAd->TimerQ.pTimerQPoll,
- sizeof(struct rt_rtmp_timer_task_entry) * TIMER_QUEUE_SIZE_MAX);
- if (pAd->TimerQ.pTimerQPoll) {
- pEntry = NULL;
- pQNode = (struct rt_rtmp_timer_task_entry *)pAd->TimerQ.pTimerQPoll;
- NdisZeroMemory(pAd->TimerQ.pTimerQPoll,
- sizeof(struct rt_rtmp_timer_task_entry) *
- TIMER_QUEUE_SIZE_MAX);
-
- RTMP_INT_LOCK(&pAd->TimerQLock, irqFlags);
- for (i = 0; i < TIMER_QUEUE_SIZE_MAX; i++) {
- pQNode->pNext = pEntry;
- pEntry = pQNode;
- pQNode++;
- }
- pAd->TimerQ.pQPollFreeList = pEntry;
- pAd->TimerQ.pQHead = NULL;
- pAd->TimerQ.pQTail = NULL;
- pAd->TimerQ.status = RTMP_TASK_STAT_INITED;
- RTMP_INT_UNLOCK(&pAd->TimerQLock, irqFlags);
- }
-}
-#endif /* RTMP_TIMER_TASK_SUPPORT // */
diff --git a/drivers/staging/rt2860/common/spectrum.c b/drivers/staging/rt2860/common/spectrum.c
deleted file mode 100644
index ceb622d..0000000
--- a/drivers/staging/rt2860/common/spectrum.c
+++ /dev/null
@@ -1,2205 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- action.c
-
- Abstract:
- Handle association related requests either from WSTA or from local MLME
-
- Revision History:
- Who When What
- --------- ---------- ----------------------------------------------
- Fonchi Wu 2008 created for 802.11h
- */
-
-#include "../rt_config.h"
-#include "action.h"
-
-/* The regulatory information in the USA (US) */
-struct rt_dot11_regulatory_information USARegulatoryInfo[] = {
-/* "regulatory class" "number of channels" "Max Tx Pwr" "channel list" */
- {0, {0, 0, {0}
- }
- }
- , /* Invlid entry */
- {1, {4, 16, {36, 40, 44, 48}
- }
- }
- ,
- {2, {4, 23, {52, 56, 60, 64}
- }
- }
- ,
- {3, {4, 29, {149, 153, 157, 161}
- }
- }
- ,
- {4, {11, 23, {100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140}
- }
- }
- ,
- {5, {5, 30, {149, 153, 157, 161, 165}
- }
- }
- ,
- {6, {10, 14, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10}
- }
- }
- ,
- {7, {10, 27, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10}
- }
- }
- ,
- {8, {5, 17, {11, 13, 15, 17, 19}
- }
- }
- ,
- {9, {5, 30, {11, 13, 15, 17, 19}
- }
- }
- ,
- {10, {2, 20, {21, 25}
- }
- }
- ,
- {11, {2, 33, {21, 25}
- }
- }
- ,
- {12, {11, 30, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11}
- }
- }
-};
-
-#define USA_REGULATORY_INFO_SIZE (sizeof(USARegulatoryInfo) / sizeof(struct rt_dot11_regulatory_information))
-
-/* The regulatory information in Europe */
-struct rt_dot11_regulatory_information EuropeRegulatoryInfo[] = {
-/* "regulatory class" "number of channels" "Max Tx Pwr" "channel list" */
- {0, {0, 0, {0}
- }
- }
- , /* Invalid entry */
- {1, {4, 20, {36, 40, 44, 48}
- }
- }
- ,
- {2, {4, 20, {52, 56, 60, 64}
- }
- }
- ,
- {3, {11, 30, {100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140}
- }
- }
- ,
- {4, {13, 20, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}
- }
- }
-};
-
-#define EU_REGULATORY_INFO_SIZE (sizeof(EuropeRegulatoryInfo) / sizeof(struct rt_dot11_regulatory_information))
-
-/* The regulatory information in Japan */
-struct rt_dot11_regulatory_information JapanRegulatoryInfo[] = {
-/* "regulatory class" "number of channels" "Max Tx Pwr" "channel list" */
- {0, {0, 0, {0}
- }
- }
- , /* Invalid entry */
- {1, {4, 22, {34, 38, 42, 46}
- }
- }
- ,
- {2, {3, 24, {8, 12, 16}
- }
- }
- ,
- {3, {3, 24, {8, 12, 16}
- }
- }
- ,
- {4, {3, 24, {8, 12, 16}
- }
- }
- ,
- {5, {3, 24, {8, 12, 16}
- }
- }
- ,
- {6, {3, 22, {8, 12, 16}
- }
- }
- ,
- {7, {4, 24, {184, 188, 192, 196}
- }
- }
- ,
- {8, {4, 24, {184, 188, 192, 196}
- }
- }
- ,
- {9, {4, 24, {184, 188, 192, 196}
- }
- }
- ,
- {10, {4, 24, {184, 188, 192, 196}
- }
- }
- ,
- {11, {4, 22, {184, 188, 192, 196}
- }
- }
- ,
- {12, {4, 24, {7, 8, 9, 11}
- }
- }
- ,
- {13, {4, 24, {7, 8, 9, 11}
- }
- }
- ,
- {14, {4, 24, {7, 8, 9, 11}
- }
- }
- ,
- {15, {4, 24, {7, 8, 9, 11}
- }
- }
- ,
- {16, {6, 24, {183, 184, 185, 187, 188, 189}
- }
- }
- ,
- {17, {6, 24, {183, 184, 185, 187, 188, 189}
- }
- }
- ,
- {18, {6, 24, {183, 184, 185, 187, 188, 189}
- }
- }
- ,
- {19, {6, 24, {183, 184, 185, 187, 188, 189}
- }
- }
- ,
- {20, {6, 17, {183, 184, 185, 187, 188, 189}
- }
- }
- ,
- {21, {6, 24, {6, 7, 8, 9, 10, 11}
- }
- }
- ,
- {22, {6, 24, {6, 7, 8, 9, 10, 11}
- }
- }
- ,
- {23, {6, 24, {6, 7, 8, 9, 10, 11}
- }
- }
- ,
- {24, {6, 24, {6, 7, 8, 9, 10, 11}
- }
- }
- ,
- {25, {8, 24, {182, 183, 184, 185, 186, 187, 188, 189}
- }
- }
- ,
- {26, {8, 24, {182, 183, 184, 185, 186, 187, 188, 189}
- }
- }
- ,
- {27, {8, 24, {182, 183, 184, 185, 186, 187, 188, 189}
- }
- }
- ,
- {28, {8, 24, {182, 183, 184, 185, 186, 187, 188, 189}
- }
- }
- ,
- {29, {8, 17, {182, 183, 184, 185, 186, 187, 188, 189}
- }
- }
- ,
- {30, {13, 23, {1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13}
- }
- }
- ,
- {31, {1, 23, {14}
- }
- }
- ,
- {32, {4, 22, {52, 56, 60, 64}
- }
- }
-};
-
-#define JP_REGULATORY_INFO_SIZE (sizeof(JapanRegulatoryInfo) / sizeof(struct rt_dot11_regulatory_information))
-
-char RTMP_GetTxPwr(struct rt_rtmp_adapter *pAd, IN HTTRANSMIT_SETTING HTTxMode)
-{
- struct tx_pwr_cfg {
- u8 Mode;
- u8 MCS;
- u16 req;
- u8 shift;
- u32 BitMask;
- };
-
- u32 Value;
- int Idx;
- u8 PhyMode;
- char CurTxPwr;
- u8 TxPwrRef = 0;
- char DaltaPwr;
- unsigned long TxPwr[5];
-
- struct tx_pwr_cfg TxPwrCfg[] = {
- {MODE_CCK, 0, 0, 4, 0x000000f0},
- {MODE_CCK, 1, 0, 0, 0x0000000f},
- {MODE_CCK, 2, 0, 12, 0x0000f000},
- {MODE_CCK, 3, 0, 8, 0x00000f00},
-
- {MODE_OFDM, 0, 0, 20, 0x00f00000},
- {MODE_OFDM, 1, 0, 16, 0x000f0000},
- {MODE_OFDM, 2, 0, 28, 0xf0000000},
- {MODE_OFDM, 3, 0, 24, 0x0f000000},
- {MODE_OFDM, 4, 1, 4, 0x000000f0},
- {MODE_OFDM, 5, 1, 0, 0x0000000f},
- {MODE_OFDM, 6, 1, 12, 0x0000f000},
- {MODE_OFDM, 7, 1, 8, 0x00000f00}
- , {MODE_HTMIX, 0, 1, 20, 0x00f00000},
- {MODE_HTMIX, 1, 1, 16, 0x000f0000},
- {MODE_HTMIX, 2, 1, 28, 0xf0000000},
- {MODE_HTMIX, 3, 1, 24, 0x0f000000},
- {MODE_HTMIX, 4, 2, 4, 0x000000f0},
- {MODE_HTMIX, 5, 2, 0, 0x0000000f},
- {MODE_HTMIX, 6, 2, 12, 0x0000f000},
- {MODE_HTMIX, 7, 2, 8, 0x00000f00},
- {MODE_HTMIX, 8, 2, 20, 0x00f00000},
- {MODE_HTMIX, 9, 2, 16, 0x000f0000},
- {MODE_HTMIX, 10, 2, 28, 0xf0000000},
- {MODE_HTMIX, 11, 2, 24, 0x0f000000},
- {MODE_HTMIX, 12, 3, 4, 0x000000f0},
- {MODE_HTMIX, 13, 3, 0, 0x0000000f},
- {MODE_HTMIX, 14, 3, 12, 0x0000f000},
- {MODE_HTMIX, 15, 3, 8, 0x00000f00}
- };
-#define MAX_TXPWR_TAB_SIZE (sizeof(TxPwrCfg) / sizeof(struct tx_pwr_cfg))
-
- CurTxPwr = 19;
-
- /* check Tx Power setting from UI. */
- if (pAd->CommonCfg.TxPowerPercentage > 90) ;
- else if (pAd->CommonCfg.TxPowerPercentage > 60) /* reduce Pwr for 1 dB. */
- CurTxPwr -= 1;
- else if (pAd->CommonCfg.TxPowerPercentage > 30) /* reduce Pwr for 3 dB. */
- CurTxPwr -= 3;
- else if (pAd->CommonCfg.TxPowerPercentage > 15) /* reduce Pwr for 6 dB. */
- CurTxPwr -= 6;
- else if (pAd->CommonCfg.TxPowerPercentage > 9) /* reduce Pwr for 9 dB. */
- CurTxPwr -= 9;
- else /* reduce Pwr for 12 dB. */
- CurTxPwr -= 12;
-
- if (pAd->CommonCfg.BBPCurrentBW == BW_40) {
- if (pAd->CommonCfg.CentralChannel > 14) {
- TxPwr[0] = pAd->Tx40MPwrCfgABand[0];
- TxPwr[1] = pAd->Tx40MPwrCfgABand[1];
- TxPwr[2] = pAd->Tx40MPwrCfgABand[2];
- TxPwr[3] = pAd->Tx40MPwrCfgABand[3];
- TxPwr[4] = pAd->Tx40MPwrCfgABand[4];
- } else {
- TxPwr[0] = pAd->Tx40MPwrCfgGBand[0];
- TxPwr[1] = pAd->Tx40MPwrCfgGBand[1];
- TxPwr[2] = pAd->Tx40MPwrCfgGBand[2];
- TxPwr[3] = pAd->Tx40MPwrCfgGBand[3];
- TxPwr[4] = pAd->Tx40MPwrCfgGBand[4];
- }
- } else {
- if (pAd->CommonCfg.Channel > 14) {
- TxPwr[0] = pAd->Tx20MPwrCfgABand[0];
- TxPwr[1] = pAd->Tx20MPwrCfgABand[1];
- TxPwr[2] = pAd->Tx20MPwrCfgABand[2];
- TxPwr[3] = pAd->Tx20MPwrCfgABand[3];
- TxPwr[4] = pAd->Tx20MPwrCfgABand[4];
- } else {
- TxPwr[0] = pAd->Tx20MPwrCfgGBand[0];
- TxPwr[1] = pAd->Tx20MPwrCfgGBand[1];
- TxPwr[2] = pAd->Tx20MPwrCfgGBand[2];
- TxPwr[3] = pAd->Tx20MPwrCfgGBand[3];
- TxPwr[4] = pAd->Tx20MPwrCfgGBand[4];
- }
- }
-
- switch (HTTxMode.field.MODE) {
- case MODE_CCK:
- case MODE_OFDM:
- Value = TxPwr[1];
- TxPwrRef = (Value & 0x00000f00) >> 8;
-
- break;
-
- case MODE_HTMIX:
- case MODE_HTGREENFIELD:
- if (pAd->CommonCfg.TxStream == 1) {
- Value = TxPwr[2];
- TxPwrRef = (Value & 0x00000f00) >> 8;
- } else if (pAd->CommonCfg.TxStream == 2) {
- Value = TxPwr[3];
- TxPwrRef = (Value & 0x00000f00) >> 8;
- }
- break;
- }
-
- PhyMode = (HTTxMode.field.MODE == MODE_HTGREENFIELD)
- ? MODE_HTMIX : HTTxMode.field.MODE;
-
- for (Idx = 0; Idx < MAX_TXPWR_TAB_SIZE; Idx++) {
- if ((TxPwrCfg[Idx].Mode == PhyMode)
- && (TxPwrCfg[Idx].MCS == HTTxMode.field.MCS)) {
- Value = TxPwr[TxPwrCfg[Idx].req];
- DaltaPwr =
- TxPwrRef - (char)((Value & TxPwrCfg[Idx].BitMask)
- >> TxPwrCfg[Idx].shift);
- CurTxPwr -= DaltaPwr;
- break;
- }
- }
-
- return CurTxPwr;
-}
-
-void MeasureReqTabInit(struct rt_rtmp_adapter *pAd)
-{
- NdisAllocateSpinLock(&pAd->CommonCfg.MeasureReqTabLock);
-
- pAd->CommonCfg.pMeasureReqTab =
- kmalloc(sizeof(struct rt_measure_req_tab), GFP_ATOMIC);
- if (pAd->CommonCfg.pMeasureReqTab)
- NdisZeroMemory(pAd->CommonCfg.pMeasureReqTab,
- sizeof(struct rt_measure_req_tab));
- else
- DBGPRINT(RT_DEBUG_ERROR,
- ("%s Fail to alloc memory for pAd->CommonCfg.pMeasureReqTab.\n",
- __func__));
-
- return;
-}
-
-void MeasureReqTabExit(struct rt_rtmp_adapter *pAd)
-{
- NdisFreeSpinLock(&pAd->CommonCfg.MeasureReqTabLock);
-
- kfree(pAd->CommonCfg.pMeasureReqTab);
- pAd->CommonCfg.pMeasureReqTab = NULL;
-
- return;
-}
-
-struct rt_measure_req_entry *MeasureReqLookUp(struct rt_rtmp_adapter *pAd, u8 DialogToken)
-{
- u32 HashIdx;
- struct rt_measure_req_tab *pTab = pAd->CommonCfg.pMeasureReqTab;
- struct rt_measure_req_entry *pEntry = NULL;
- struct rt_measure_req_entry *pPrevEntry = NULL;
-
- if (pTab == NULL) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("%s: pMeasureReqTab doesn't exist.\n", __func__));
- return NULL;
- }
-
- RTMP_SEM_LOCK(&pAd->CommonCfg.MeasureReqTabLock);
-
- HashIdx = MQ_DIALOGTOKEN_HASH_INDEX(DialogToken);
- pEntry = pTab->Hash[HashIdx];
-
- while (pEntry) {
- if (pEntry->DialogToken == DialogToken)
- break;
- else {
- pPrevEntry = pEntry;
- pEntry = pEntry->pNext;
- }
- }
-
- RTMP_SEM_UNLOCK(&pAd->CommonCfg.MeasureReqTabLock);
-
- return pEntry;
-}
-
-struct rt_measure_req_entry *MeasureReqInsert(struct rt_rtmp_adapter *pAd, u8 DialogToken)
-{
- int i;
- unsigned long HashIdx;
- struct rt_measure_req_tab *pTab = pAd->CommonCfg.pMeasureReqTab;
- struct rt_measure_req_entry *pEntry = NULL, *pCurrEntry;
- unsigned long Now;
-
- if (pTab == NULL) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("%s: pMeasureReqTab doesn't exist.\n", __func__));
- return NULL;
- }
-
- pEntry = MeasureReqLookUp(pAd, DialogToken);
- if (pEntry == NULL) {
- RTMP_SEM_LOCK(&pAd->CommonCfg.MeasureReqTabLock);
- for (i = 0; i < MAX_MEASURE_REQ_TAB_SIZE; i++) {
- NdisGetSystemUpTime(&Now);
- pEntry = &pTab->Content[i];
-
- if ((pEntry->Valid == TRUE)
- && RTMP_TIME_AFTER((unsigned long)Now,
- (unsigned long)(pEntry->
- lastTime +
- MQ_REQ_AGE_OUT)))
- {
- struct rt_measure_req_entry *pPrevEntry = NULL;
- unsigned long HashIdx =
- MQ_DIALOGTOKEN_HASH_INDEX(pEntry->
- DialogToken);
- struct rt_measure_req_entry *pProbeEntry =
- pTab->Hash[HashIdx];
-
- /* update Hash list */
- do {
- if (pProbeEntry == pEntry) {
- if (pPrevEntry == NULL) {
- pTab->Hash[HashIdx] =
- pEntry->pNext;
- } else {
- pPrevEntry->pNext =
- pEntry->pNext;
- }
- break;
- }
-
- pPrevEntry = pProbeEntry;
- pProbeEntry = pProbeEntry->pNext;
- } while (pProbeEntry);
-
- NdisZeroMemory(pEntry,
- sizeof(struct rt_measure_req_entry));
- pTab->Size--;
-
- break;
- }
-
- if (pEntry->Valid == FALSE)
- break;
- }
-
- if (i < MAX_MEASURE_REQ_TAB_SIZE) {
- NdisGetSystemUpTime(&Now);
- pEntry->lastTime = Now;
- pEntry->Valid = TRUE;
- pEntry->DialogToken = DialogToken;
- pTab->Size++;
- } else {
- pEntry = NULL;
- DBGPRINT(RT_DEBUG_ERROR,
- ("%s: pMeasureReqTab tab full.\n", __func__));
- }
-
- /* add this Neighbor entry into HASH table */
- if (pEntry) {
- HashIdx = MQ_DIALOGTOKEN_HASH_INDEX(DialogToken);
- if (pTab->Hash[HashIdx] == NULL) {
- pTab->Hash[HashIdx] = pEntry;
- } else {
- pCurrEntry = pTab->Hash[HashIdx];
- while (pCurrEntry->pNext != NULL)
- pCurrEntry = pCurrEntry->pNext;
- pCurrEntry->pNext = pEntry;
- }
- }
-
- RTMP_SEM_UNLOCK(&pAd->CommonCfg.MeasureReqTabLock);
- }
-
- return pEntry;
-}
-
-void MeasureReqDelete(struct rt_rtmp_adapter *pAd, u8 DialogToken)
-{
- struct rt_measure_req_tab *pTab = pAd->CommonCfg.pMeasureReqTab;
- struct rt_measure_req_entry *pEntry = NULL;
-
- if (pTab == NULL) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("%s: pMeasureReqTab doesn't exist.\n", __func__));
- return;
- }
- /* if empty, return */
- if (pTab->Size == 0) {
- DBGPRINT(RT_DEBUG_ERROR, ("pMeasureReqTab empty.\n"));
- return;
- }
-
- pEntry = MeasureReqLookUp(pAd, DialogToken);
- if (pEntry != NULL) {
- struct rt_measure_req_entry *pPrevEntry = NULL;
- unsigned long HashIdx = MQ_DIALOGTOKEN_HASH_INDEX(pEntry->DialogToken);
- struct rt_measure_req_entry *pProbeEntry = pTab->Hash[HashIdx];
-
- RTMP_SEM_LOCK(&pAd->CommonCfg.MeasureReqTabLock);
- /* update Hash list */
- do {
- if (pProbeEntry == pEntry) {
- if (pPrevEntry == NULL) {
- pTab->Hash[HashIdx] = pEntry->pNext;
- } else {
- pPrevEntry->pNext = pEntry->pNext;
- }
- break;
- }
-
- pPrevEntry = pProbeEntry;
- pProbeEntry = pProbeEntry->pNext;
- } while (pProbeEntry);
-
- NdisZeroMemory(pEntry, sizeof(struct rt_measure_req_entry));
- pTab->Size--;
-
- RTMP_SEM_UNLOCK(&pAd->CommonCfg.MeasureReqTabLock);
- }
-
- return;
-}
-
-void TpcReqTabInit(struct rt_rtmp_adapter *pAd)
-{
- NdisAllocateSpinLock(&pAd->CommonCfg.TpcReqTabLock);
-
- pAd->CommonCfg.pTpcReqTab = kmalloc(sizeof(struct rt_tpc_req_tab), GFP_ATOMIC);
- if (pAd->CommonCfg.pTpcReqTab)
- NdisZeroMemory(pAd->CommonCfg.pTpcReqTab, sizeof(struct rt_tpc_req_tab));
- else
- DBGPRINT(RT_DEBUG_ERROR,
- ("%s Fail to alloc memory for pAd->CommonCfg.pTpcReqTab.\n",
- __func__));
-
- return;
-}
-
-void TpcReqTabExit(struct rt_rtmp_adapter *pAd)
-{
- NdisFreeSpinLock(&pAd->CommonCfg.TpcReqTabLock);
-
- kfree(pAd->CommonCfg.pTpcReqTab);
- pAd->CommonCfg.pTpcReqTab = NULL;
-
- return;
-}
-
-static struct rt_tpc_req_entry *TpcReqLookUp(struct rt_rtmp_adapter *pAd, u8 DialogToken)
-{
- u32 HashIdx;
- struct rt_tpc_req_tab *pTab = pAd->CommonCfg.pTpcReqTab;
- struct rt_tpc_req_entry *pEntry = NULL;
- struct rt_tpc_req_entry *pPrevEntry = NULL;
-
- if (pTab == NULL) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("%s: pTpcReqTab doesn't exist.\n", __func__));
- return NULL;
- }
-
- RTMP_SEM_LOCK(&pAd->CommonCfg.TpcReqTabLock);
-
- HashIdx = TPC_DIALOGTOKEN_HASH_INDEX(DialogToken);
- pEntry = pTab->Hash[HashIdx];
-
- while (pEntry) {
- if (pEntry->DialogToken == DialogToken)
- break;
- else {
- pPrevEntry = pEntry;
- pEntry = pEntry->pNext;
- }
- }
-
- RTMP_SEM_UNLOCK(&pAd->CommonCfg.TpcReqTabLock);
-
- return pEntry;
-}
-
-static struct rt_tpc_req_entry *TpcReqInsert(struct rt_rtmp_adapter *pAd, u8 DialogToken)
-{
- int i;
- unsigned long HashIdx;
- struct rt_tpc_req_tab *pTab = pAd->CommonCfg.pTpcReqTab;
- struct rt_tpc_req_entry *pEntry = NULL, *pCurrEntry;
- unsigned long Now;
-
- if (pTab == NULL) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("%s: pTpcReqTab doesn't exist.\n", __func__));
- return NULL;
- }
-
- pEntry = TpcReqLookUp(pAd, DialogToken);
- if (pEntry == NULL) {
- RTMP_SEM_LOCK(&pAd->CommonCfg.TpcReqTabLock);
- for (i = 0; i < MAX_TPC_REQ_TAB_SIZE; i++) {
- NdisGetSystemUpTime(&Now);
- pEntry = &pTab->Content[i];
-
- if ((pEntry->Valid == TRUE)
- && RTMP_TIME_AFTER((unsigned long)Now,
- (unsigned long)(pEntry->
- lastTime +
- TPC_REQ_AGE_OUT)))
- {
- struct rt_tpc_req_entry *pPrevEntry = NULL;
- unsigned long HashIdx =
- TPC_DIALOGTOKEN_HASH_INDEX(pEntry->
- DialogToken);
- struct rt_tpc_req_entry *pProbeEntry =
- pTab->Hash[HashIdx];
-
- /* update Hash list */
- do {
- if (pProbeEntry == pEntry) {
- if (pPrevEntry == NULL) {
- pTab->Hash[HashIdx] =
- pEntry->pNext;
- } else {
- pPrevEntry->pNext =
- pEntry->pNext;
- }
- break;
- }
-
- pPrevEntry = pProbeEntry;
- pProbeEntry = pProbeEntry->pNext;
- } while (pProbeEntry);
-
- NdisZeroMemory(pEntry, sizeof(struct rt_tpc_req_entry));
- pTab->Size--;
-
- break;
- }
-
- if (pEntry->Valid == FALSE)
- break;
- }
-
- if (i < MAX_TPC_REQ_TAB_SIZE) {
- NdisGetSystemUpTime(&Now);
- pEntry->lastTime = Now;
- pEntry->Valid = TRUE;
- pEntry->DialogToken = DialogToken;
- pTab->Size++;
- } else {
- pEntry = NULL;
- DBGPRINT(RT_DEBUG_ERROR,
- ("%s: pTpcReqTab tab full.\n", __func__));
- }
-
- /* add this Neighbor entry into HASH table */
- if (pEntry) {
- HashIdx = TPC_DIALOGTOKEN_HASH_INDEX(DialogToken);
- if (pTab->Hash[HashIdx] == NULL) {
- pTab->Hash[HashIdx] = pEntry;
- } else {
- pCurrEntry = pTab->Hash[HashIdx];
- while (pCurrEntry->pNext != NULL)
- pCurrEntry = pCurrEntry->pNext;
- pCurrEntry->pNext = pEntry;
- }
- }
-
- RTMP_SEM_UNLOCK(&pAd->CommonCfg.TpcReqTabLock);
- }
-
- return pEntry;
-}
-
-static void TpcReqDelete(struct rt_rtmp_adapter *pAd, u8 DialogToken)
-{
- struct rt_tpc_req_tab *pTab = pAd->CommonCfg.pTpcReqTab;
- struct rt_tpc_req_entry *pEntry = NULL;
-
- if (pTab == NULL) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("%s: pTpcReqTab doesn't exist.\n", __func__));
- return;
- }
- /* if empty, return */
- if (pTab->Size == 0) {
- DBGPRINT(RT_DEBUG_ERROR, ("pTpcReqTab empty.\n"));
- return;
- }
-
- pEntry = TpcReqLookUp(pAd, DialogToken);
- if (pEntry != NULL) {
- struct rt_tpc_req_entry *pPrevEntry = NULL;
- unsigned long HashIdx = TPC_DIALOGTOKEN_HASH_INDEX(pEntry->DialogToken);
- struct rt_tpc_req_entry *pProbeEntry = pTab->Hash[HashIdx];
-
- RTMP_SEM_LOCK(&pAd->CommonCfg.TpcReqTabLock);
- /* update Hash list */
- do {
- if (pProbeEntry == pEntry) {
- if (pPrevEntry == NULL) {
- pTab->Hash[HashIdx] = pEntry->pNext;
- } else {
- pPrevEntry->pNext = pEntry->pNext;
- }
- break;
- }
-
- pPrevEntry = pProbeEntry;
- pProbeEntry = pProbeEntry->pNext;
- } while (pProbeEntry);
-
- NdisZeroMemory(pEntry, sizeof(struct rt_tpc_req_entry));
- pTab->Size--;
-
- RTMP_SEM_UNLOCK(&pAd->CommonCfg.TpcReqTabLock);
- }
-
- return;
-}
-
-/*
- ==========================================================================
- Description:
- Get Current TimeS tamp.
-
- Parametrs:
-
- Return : Current Time Stamp.
- ==========================================================================
- */
-static u64 GetCurrentTimeStamp(struct rt_rtmp_adapter *pAd)
-{
- /* get current time stamp. */
- return 0;
-}
-
-/*
- ==========================================================================
- Description:
- Get Current Transmit Power.
-
- Parametrs:
-
- Return : Current Time Stamp.
- ==========================================================================
- */
-static u8 GetCurTxPwr(struct rt_rtmp_adapter *pAd, u8 Wcid)
-{
- return 16; /* 16 dBm */
-}
-
-/*
- ==========================================================================
- Description:
- Get Current Transmit Power.
-
- Parametrs:
-
- Return : Current Time Stamp.
- ==========================================================================
- */
-void InsertChannelRepIE(struct rt_rtmp_adapter *pAd,
- u8 *pFrameBuf,
- unsigned long *pFrameLen,
- char *pCountry, u8 RegulatoryClass)
-{
- unsigned long TempLen;
- u8 Len;
- u8 IEId = IE_AP_CHANNEL_REPORT;
- u8 *pChListPtr = NULL;
-
- Len = 1;
- if (strncmp(pCountry, "US", 2) == 0) {
- if (RegulatoryClass >= USA_REGULATORY_INFO_SIZE) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("%s: USA Unknow Requlatory class (%d)\n",
- __func__, RegulatoryClass));
- return;
- }
-
- Len +=
- USARegulatoryInfo[RegulatoryClass].ChannelSet.
- NumberOfChannels;
- pChListPtr =
- USARegulatoryInfo[RegulatoryClass].ChannelSet.ChannelList;
- } else if (strncmp(pCountry, "JP", 2) == 0) {
- if (RegulatoryClass >= JP_REGULATORY_INFO_SIZE) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("%s: JP Unknow Requlatory class (%d)\n",
- __func__, RegulatoryClass));
- return;
- }
-
- Len +=
- JapanRegulatoryInfo[RegulatoryClass].ChannelSet.
- NumberOfChannels;
- pChListPtr =
- JapanRegulatoryInfo[RegulatoryClass].ChannelSet.ChannelList;
- } else {
- DBGPRINT(RT_DEBUG_ERROR, ("%s: Unknow Country (%s)\n",
- __func__, pCountry));
- return;
- }
-
- MakeOutgoingFrame(pFrameBuf, &TempLen,
- 1, &IEId,
- 1, &Len,
- 1, &RegulatoryClass,
- Len - 1, pChListPtr, END_OF_ARGS);
-
- *pFrameLen = *pFrameLen + TempLen;
-
- return;
-}
-
-/*
- ==========================================================================
- Description:
- Insert Dialog Token into frame.
-
- Parametrs:
- 1. frame buffer pointer.
- 2. frame length.
- 3. Dialog token.
-
- Return : None.
- ==========================================================================
- */
-void InsertDialogToken(struct rt_rtmp_adapter *pAd,
- u8 *pFrameBuf,
- unsigned long *pFrameLen, u8 DialogToken)
-{
- unsigned long TempLen;
- MakeOutgoingFrame(pFrameBuf, &TempLen, 1, &DialogToken, END_OF_ARGS);
-
- *pFrameLen = *pFrameLen + TempLen;
-
- return;
-}
-
-/*
- ==========================================================================
- Description:
- Insert TPC Request IE into frame.
-
- Parametrs:
- 1. frame buffer pointer.
- 2. frame length.
-
- Return : None.
- ==========================================================================
- */
-static void InsertTpcReqIE(struct rt_rtmp_adapter *pAd,
- u8 *pFrameBuf, unsigned long *pFrameLen)
-{
- unsigned long TempLen;
- unsigned long Len = 0;
- u8 ElementID = IE_TPC_REQUEST;
-
- MakeOutgoingFrame(pFrameBuf, &TempLen,
- 1, &ElementID, 1, &Len, END_OF_ARGS);
-
- *pFrameLen = *pFrameLen + TempLen;
-
- return;
-}
-
-/*
- ==========================================================================
- Description:
- Insert TPC Report IE into frame.
-
- Parametrs:
- 1. frame buffer pointer.
- 2. frame length.
- 3. Transmit Power.
- 4. Link Margin.
-
- Return : None.
- ==========================================================================
- */
-void InsertTpcReportIE(struct rt_rtmp_adapter *pAd,
- u8 *pFrameBuf,
- unsigned long *pFrameLen,
- u8 TxPwr, u8 LinkMargin)
-{
- unsigned long TempLen;
- unsigned long Len = sizeof(struct rt_tpc_report_info);
- u8 ElementID = IE_TPC_REPORT;
- struct rt_tpc_report_info TpcReportIE;
-
- TpcReportIE.TxPwr = TxPwr;
- TpcReportIE.LinkMargin = LinkMargin;
-
- MakeOutgoingFrame(pFrameBuf, &TempLen,
- 1, &ElementID,
- 1, &Len, Len, &TpcReportIE, END_OF_ARGS);
-
- *pFrameLen = *pFrameLen + TempLen;
-
- return;
-}
-
-/*
- ==========================================================================
- Description:
- Insert Channel Switch Announcement IE into frame.
-
- Parametrs:
- 1. frame buffer pointer.
- 2. frame length.
- 3. channel switch announcement mode.
- 4. new selected channel.
- 5. channel switch announcement count.
-
- Return : None.
- ==========================================================================
- */
-static void InsertChSwAnnIE(struct rt_rtmp_adapter *pAd,
- u8 *pFrameBuf,
- unsigned long *pFrameLen,
- u8 ChSwMode,
- u8 NewChannel, u8 ChSwCnt)
-{
- unsigned long TempLen;
- unsigned long Len = sizeof(struct rt_ch_sw_ann_info);
- u8 ElementID = IE_CHANNEL_SWITCH_ANNOUNCEMENT;
- struct rt_ch_sw_ann_info ChSwAnnIE;
-
- ChSwAnnIE.ChSwMode = ChSwMode;
- ChSwAnnIE.Channel = NewChannel;
- ChSwAnnIE.ChSwCnt = ChSwCnt;
-
- MakeOutgoingFrame(pFrameBuf, &TempLen,
- 1, &ElementID, 1, &Len, Len, &ChSwAnnIE, END_OF_ARGS);
-
- *pFrameLen = *pFrameLen + TempLen;
-
- return;
-}
-
-/*
- ==========================================================================
- Description:
- Insert Measure Request IE into frame.
-
- Parametrs:
- 1. frame buffer pointer.
- 2. frame length.
- 3. Measure Token.
- 4. Measure Request Mode.
- 5. Measure Request Type.
- 6. Measure Channel.
- 7. Measure Start time.
- 8. Measure Duration.
-
- Return : None.
- ==========================================================================
- */
-static void InsertMeasureReqIE(struct rt_rtmp_adapter *pAd,
- u8 *pFrameBuf,
- unsigned long *pFrameLen,
- u8 Len, struct rt_measure_req_info * pMeasureReqIE)
-{
- unsigned long TempLen;
- u8 ElementID = IE_MEASUREMENT_REQUEST;
-
- MakeOutgoingFrame(pFrameBuf, &TempLen,
- 1, &ElementID,
- 1, &Len,
- sizeof(struct rt_measure_req_info), pMeasureReqIE, END_OF_ARGS);
-
- *pFrameLen = *pFrameLen + TempLen;
-
- return;
-}
-
-/*
- ==========================================================================
- Description:
- Insert Measure Report IE into frame.
-
- Parametrs:
- 1. frame buffer pointer.
- 2. frame length.
- 3. Measure Token.
- 4. Measure Request Mode.
- 5. Measure Request Type.
- 6. Length of Report Information
- 7. Pointer of Report Information Buffer.
-
- Return : None.
- ==========================================================================
- */
-static void InsertMeasureReportIE(struct rt_rtmp_adapter *pAd,
- u8 *pFrameBuf,
- unsigned long *pFrameLen,
- struct rt_measure_report_info * pMeasureReportIE,
- u8 ReportLnfoLen, u8 *pReportInfo)
-{
- unsigned long TempLen;
- unsigned long Len;
- u8 ElementID = IE_MEASUREMENT_REPORT;
-
- Len = sizeof(struct rt_measure_report_info) + ReportLnfoLen;
-
- MakeOutgoingFrame(pFrameBuf, &TempLen,
- 1, &ElementID,
- 1, &Len, Len, pMeasureReportIE, END_OF_ARGS);
-
- *pFrameLen = *pFrameLen + TempLen;
-
- if ((ReportLnfoLen > 0) && (pReportInfo != NULL)) {
- MakeOutgoingFrame(pFrameBuf + *pFrameLen, &TempLen,
- ReportLnfoLen, pReportInfo, END_OF_ARGS);
-
- *pFrameLen = *pFrameLen + TempLen;
- }
- return;
-}
-
-/*
- ==========================================================================
- Description:
- Prepare Measurement request action frame and enqueue it into
- management queue waiting for transmition.
-
- Parametrs:
- 1. the destination mac address of the frame.
-
- Return : None.
- ==========================================================================
- */
-void MakeMeasurementReqFrame(struct rt_rtmp_adapter *pAd,
- u8 *pOutBuffer,
- unsigned long *pFrameLen,
- u8 TotalLen,
- u8 Category,
- u8 Action,
- u8 MeasureToken,
- u8 MeasureReqMode,
- u8 MeasureReqType, u8 NumOfRepetitions)
-{
- unsigned long TempLen;
- struct rt_measure_req_info MeasureReqIE;
-
- InsertActField(pAd, (pOutBuffer + *pFrameLen), pFrameLen, Category,
- Action);
-
- /* fill Dialog Token */
- InsertDialogToken(pAd, (pOutBuffer + *pFrameLen), pFrameLen,
- MeasureToken);
-
- /* fill Number of repetitions. */
- if (Category == CATEGORY_RM) {
- MakeOutgoingFrame((pOutBuffer + *pFrameLen), &TempLen,
- 2, &NumOfRepetitions, END_OF_ARGS);
-
- *pFrameLen += TempLen;
- }
- /* prepare Measurement IE. */
- NdisZeroMemory(&MeasureReqIE, sizeof(struct rt_measure_req_info));
- MeasureReqIE.Token = MeasureToken;
- MeasureReqIE.ReqMode.word = MeasureReqMode;
- MeasureReqIE.ReqType = MeasureReqType;
- InsertMeasureReqIE(pAd, (pOutBuffer + *pFrameLen), pFrameLen,
- TotalLen, &MeasureReqIE);
-
- return;
-}
-
-/*
- ==========================================================================
- Description:
- Prepare Measurement report action frame and enqueue it into
- management queue waiting for transmition.
-
- Parametrs:
- 1. the destination mac address of the frame.
-
- Return : None.
- ==========================================================================
- */
-void EnqueueMeasurementRep(struct rt_rtmp_adapter *pAd,
- u8 *pDA,
- u8 DialogToken,
- u8 MeasureToken,
- u8 MeasureReqMode,
- u8 MeasureReqType,
- u8 ReportInfoLen, u8 *pReportInfo)
-{
- u8 *pOutBuffer = NULL;
- int NStatus;
- unsigned long FrameLen;
- struct rt_header_802_11 ActHdr;
- struct rt_measure_report_info MeasureRepIE;
-
- /* build action frame header. */
- MgtMacHeaderInit(pAd, &ActHdr, SUBTYPE_ACTION, 0, pDA,
- pAd->CurrentAddress);
-
- NStatus = MlmeAllocateMemory(pAd, (void *)& pOutBuffer); /*Get an unused nonpaged memory */
- if (NStatus != NDIS_STATUS_SUCCESS) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("%s() allocate memory failed \n", __func__));
- return;
- }
- NdisMoveMemory(pOutBuffer, (char *)& ActHdr, sizeof(struct rt_header_802_11));
- FrameLen = sizeof(struct rt_header_802_11);
-
- InsertActField(pAd, (pOutBuffer + FrameLen), &FrameLen,
- CATEGORY_SPECTRUM, SPEC_MRP);
-
- /* fill Dialog Token */
- InsertDialogToken(pAd, (pOutBuffer + FrameLen), &FrameLen, DialogToken);
-
- /* prepare Measurement IE. */
- NdisZeroMemory(&MeasureRepIE, sizeof(struct rt_measure_report_info));
- MeasureRepIE.Token = MeasureToken;
- MeasureRepIE.ReportMode = MeasureReqMode;
- MeasureRepIE.ReportType = MeasureReqType;
- InsertMeasureReportIE(pAd, (pOutBuffer + FrameLen), &FrameLen,
- &MeasureRepIE, ReportInfoLen, pReportInfo);
-
- MiniportMMRequest(pAd, QID_AC_BE, pOutBuffer, FrameLen);
- MlmeFreeMemory(pAd, pOutBuffer);
-
- return;
-}
-
-/*
- ==========================================================================
- Description:
- Prepare TPC Request action frame and enqueue it into
- management queue waiting for transmition.
-
- Parametrs:
- 1. the destination mac address of the frame.
-
- Return : None.
- ==========================================================================
- */
-void EnqueueTPCReq(struct rt_rtmp_adapter *pAd, u8 *pDA, u8 DialogToken)
-{
- u8 *pOutBuffer = NULL;
- int NStatus;
- unsigned long FrameLen;
-
- struct rt_header_802_11 ActHdr;
-
- /* build action frame header. */
- MgtMacHeaderInit(pAd, &ActHdr, SUBTYPE_ACTION, 0, pDA,
- pAd->CurrentAddress);
-
- NStatus = MlmeAllocateMemory(pAd, (void *)& pOutBuffer); /*Get an unused nonpaged memory */
- if (NStatus != NDIS_STATUS_SUCCESS) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("%s() allocate memory failed \n", __func__));
- return;
- }
- NdisMoveMemory(pOutBuffer, (char *)& ActHdr, sizeof(struct rt_header_802_11));
- FrameLen = sizeof(struct rt_header_802_11);
-
- InsertActField(pAd, (pOutBuffer + FrameLen), &FrameLen,
- CATEGORY_SPECTRUM, SPEC_TPCRQ);
-
- /* fill Dialog Token */
- InsertDialogToken(pAd, (pOutBuffer + FrameLen), &FrameLen, DialogToken);
-
- /* Insert TPC Request IE. */
- InsertTpcReqIE(pAd, (pOutBuffer + FrameLen), &FrameLen);
-
- MiniportMMRequest(pAd, QID_AC_BE, pOutBuffer, FrameLen);
- MlmeFreeMemory(pAd, pOutBuffer);
-
- return;
-}
-
-/*
- ==========================================================================
- Description:
- Prepare TPC Report action frame and enqueue it into
- management queue waiting for transmition.
-
- Parametrs:
- 1. the destination mac address of the frame.
-
- Return : None.
- ==========================================================================
- */
-void EnqueueTPCRep(struct rt_rtmp_adapter *pAd,
- u8 *pDA,
- u8 DialogToken, u8 TxPwr, u8 LinkMargin)
-{
- u8 *pOutBuffer = NULL;
- int NStatus;
- unsigned long FrameLen;
-
- struct rt_header_802_11 ActHdr;
-
- /* build action frame header. */
- MgtMacHeaderInit(pAd, &ActHdr, SUBTYPE_ACTION, 0, pDA,
- pAd->CurrentAddress);
-
- NStatus = MlmeAllocateMemory(pAd, (void *)& pOutBuffer); /*Get an unused nonpaged memory */
- if (NStatus != NDIS_STATUS_SUCCESS) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("%s() allocate memory failed \n", __func__));
- return;
- }
- NdisMoveMemory(pOutBuffer, (char *)& ActHdr, sizeof(struct rt_header_802_11));
- FrameLen = sizeof(struct rt_header_802_11);
-
- InsertActField(pAd, (pOutBuffer + FrameLen), &FrameLen,
- CATEGORY_SPECTRUM, SPEC_TPCRP);
-
- /* fill Dialog Token */
- InsertDialogToken(pAd, (pOutBuffer + FrameLen), &FrameLen, DialogToken);
-
- /* Insert TPC Request IE. */
- InsertTpcReportIE(pAd, (pOutBuffer + FrameLen), &FrameLen, TxPwr,
- LinkMargin);
-
- MiniportMMRequest(pAd, QID_AC_BE, pOutBuffer, FrameLen);
- MlmeFreeMemory(pAd, pOutBuffer);
-
- return;
-}
-
-/*
- ==========================================================================
- Description:
- Prepare Channel Switch Announcement action frame and enqueue it into
- management queue waiting for transmition.
-
- Parametrs:
- 1. the destination mac address of the frame.
- 2. Channel switch announcement mode.
- 2. a New selected channel.
-
- Return : None.
- ==========================================================================
- */
-void EnqueueChSwAnn(struct rt_rtmp_adapter *pAd,
- u8 *pDA, u8 ChSwMode, u8 NewCh)
-{
- u8 *pOutBuffer = NULL;
- int NStatus;
- unsigned long FrameLen;
-
- struct rt_header_802_11 ActHdr;
-
- /* build action frame header. */
- MgtMacHeaderInit(pAd, &ActHdr, SUBTYPE_ACTION, 0, pDA,
- pAd->CurrentAddress);
-
- NStatus = MlmeAllocateMemory(pAd, (void *)& pOutBuffer); /*Get an unused nonpaged memory */
- if (NStatus != NDIS_STATUS_SUCCESS) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("%s() allocate memory failed \n", __func__));
- return;
- }
- NdisMoveMemory(pOutBuffer, (char *)& ActHdr, sizeof(struct rt_header_802_11));
- FrameLen = sizeof(struct rt_header_802_11);
-
- InsertActField(pAd, (pOutBuffer + FrameLen), &FrameLen,
- CATEGORY_SPECTRUM, SPEC_CHANNEL_SWITCH);
-
- InsertChSwAnnIE(pAd, (pOutBuffer + FrameLen), &FrameLen, ChSwMode,
- NewCh, 0);
-
- MiniportMMRequest(pAd, QID_AC_BE, pOutBuffer, FrameLen);
- MlmeFreeMemory(pAd, pOutBuffer);
-
- return;
-}
-
-static BOOLEAN DfsRequirementCheck(struct rt_rtmp_adapter *pAd, u8 Channel)
-{
- BOOLEAN Result = FALSE;
- int i;
-
- do {
- /* check DFS procedure is running. */
- /* make sure DFS procedure won't start twice. */
- if (pAd->CommonCfg.RadarDetect.RDMode != RD_NORMAL_MODE) {
- Result = FALSE;
- break;
- }
- /* check the new channel carried from Channel Switch Announcemnet is valid. */
- for (i = 0; i < pAd->ChannelListNum; i++) {
- if ((Channel == pAd->ChannelList[i].Channel)
- && (pAd->ChannelList[i].RemainingTimeForUse == 0)) {
- /* found radar signal in the channel. the channel can't use at least for 30 minutes. */
- pAd->ChannelList[i].RemainingTimeForUse = 1800; /*30 min = 1800 sec */
- Result = TRUE;
- break;
- }
- }
- } while (FALSE);
-
- return Result;
-}
-
-void NotifyChSwAnnToPeerAPs(struct rt_rtmp_adapter *pAd,
- u8 *pRA,
- u8 *pTA, u8 ChSwMode, u8 Channel)
-{
-}
-
-static void StartDFSProcedure(struct rt_rtmp_adapter *pAd,
- u8 Channel, u8 ChSwMode)
-{
- /* start DFS procedure */
- pAd->CommonCfg.Channel = Channel;
-
- N_ChannelCheck(pAd);
-
- pAd->CommonCfg.RadarDetect.RDMode = RD_SWITCHING_MODE;
- pAd->CommonCfg.RadarDetect.CSCount = 0;
-}
-
-/*
- ==========================================================================
- Description:
- Channel Switch Announcement action frame sanity check.
-
- Parametrs:
- 1. MLME message containing the received frame
- 2. message length.
- 3. Channel switch announcement information buffer.
-
- Return : None.
- ==========================================================================
- */
-
-/*
- Channel Switch Announcement IE.
- +----+-----+-----------+------------+-----------+
- | ID | Len |Ch Sw Mode | New Ch Num | Ch Sw Cnt |
- +----+-----+-----------+------------+-----------+
- 1 1 1 1 1
-*/
-static BOOLEAN PeerChSwAnnSanity(struct rt_rtmp_adapter *pAd,
- void * pMsg,
- unsigned long MsgLen,
- struct rt_ch_sw_ann_info * pChSwAnnInfo)
-{
- struct rt_frame_802_11 * Fr = (struct rt_frame_802_11 *) pMsg;
- u8 *pFramePtr = Fr->Octet;
- BOOLEAN result = FALSE;
- struct rt_eid * eid_ptr;
-
- /* skip 802.11 header. */
- MsgLen -= sizeof(struct rt_header_802_11);
-
- /* skip category and action code. */
- pFramePtr += 2;
- MsgLen -= 2;
-
- if (pChSwAnnInfo == NULL)
- return result;
-
- eid_ptr = (struct rt_eid *) pFramePtr;
- while (((u8 *) eid_ptr + eid_ptr->Len + 1) <
- ((u8 *)pFramePtr + MsgLen)) {
- switch (eid_ptr->Eid) {
- case IE_CHANNEL_SWITCH_ANNOUNCEMENT:
- NdisMoveMemory(&pChSwAnnInfo->ChSwMode, eid_ptr->Octet,
- 1);
- NdisMoveMemory(&pChSwAnnInfo->Channel,
- eid_ptr->Octet + 1, 1);
- NdisMoveMemory(&pChSwAnnInfo->ChSwCnt,
- eid_ptr->Octet + 2, 1);
-
- result = TRUE;
- break;
-
- default:
- break;
- }
- eid_ptr = (struct rt_eid *) ((u8 *) eid_ptr + 2 + eid_ptr->Len);
- }
-
- return result;
-}
-
-/*
- ==========================================================================
- Description:
- Measurement request action frame sanity check.
-
- Parametrs:
- 1. MLME message containing the received frame
- 2. message length.
- 3. Measurement request information buffer.
-
- Return : None.
- ==========================================================================
- */
-static BOOLEAN PeerMeasureReqSanity(struct rt_rtmp_adapter *pAd,
- void * pMsg,
- unsigned long MsgLen,
- u8 *pDialogToken,
- struct rt_measure_req_info * pMeasureReqInfo,
- struct rt_measure_req * pMeasureReq)
-{
- struct rt_frame_802_11 * Fr = (struct rt_frame_802_11 *) pMsg;
- u8 *pFramePtr = Fr->Octet;
- BOOLEAN result = FALSE;
- struct rt_eid * eid_ptr;
- u8 *ptr;
- u64 MeasureStartTime;
- u16 MeasureDuration;
-
- /* skip 802.11 header. */
- MsgLen -= sizeof(struct rt_header_802_11);
-
- /* skip category and action code. */
- pFramePtr += 2;
- MsgLen -= 2;
-
- if (pMeasureReqInfo == NULL)
- return result;
-
- NdisMoveMemory(pDialogToken, pFramePtr, 1);
- pFramePtr += 1;
- MsgLen -= 1;
-
- eid_ptr = (struct rt_eid *) pFramePtr;
- while (((u8 *) eid_ptr + eid_ptr->Len + 1) <
- ((u8 *)pFramePtr + MsgLen)) {
- switch (eid_ptr->Eid) {
- case IE_MEASUREMENT_REQUEST:
- NdisMoveMemory(&pMeasureReqInfo->Token, eid_ptr->Octet,
- 1);
- NdisMoveMemory(&pMeasureReqInfo->ReqMode.word,
- eid_ptr->Octet + 1, 1);
- NdisMoveMemory(&pMeasureReqInfo->ReqType,
- eid_ptr->Octet + 2, 1);
- ptr = (u8 *)(eid_ptr->Octet + 3);
- NdisMoveMemory(&pMeasureReq->ChNum, ptr, 1);
- NdisMoveMemory(&MeasureStartTime, ptr + 1, 8);
- pMeasureReq->MeasureStartTime =
- SWAP64(MeasureStartTime);
- NdisMoveMemory(&MeasureDuration, ptr + 9, 2);
- pMeasureReq->MeasureDuration = SWAP16(MeasureDuration);
-
- result = TRUE;
- break;
-
- default:
- break;
- }
- eid_ptr = (struct rt_eid *) ((u8 *) eid_ptr + 2 + eid_ptr->Len);
- }
-
- return result;
-}
-
-/*
- ==========================================================================
- Description:
- Measurement report action frame sanity check.
-
- Parametrs:
- 1. MLME message containing the received frame
- 2. message length.
- 3. Measurement report information buffer.
- 4. basic report information buffer.
-
- Return : None.
- ==========================================================================
- */
-
-/*
- Measurement Report IE.
- +----+-----+-------+-------------+--------------+----------------+
- | ID | Len | Token | Report Mode | Measure Type | Measure Report |
- +----+-----+-------+-------------+--------------+----------------+
- 1 1 1 1 1 variable
-
- Basic Report.
- +--------+------------+----------+-----+
- | Ch Num | Start Time | Duration | Map |
- +--------+------------+----------+-----+
- 1 8 2 1
-
- Map Field Bit Format.
- +-----+---------------+---------------------+-------+------------+----------+
- | Bss | OFDM Preamble | Unidentified signal | Radar | Unmeasured | Reserved |
- +-----+---------------+---------------------+-------+------------+----------+
- 0 1 2 3 4 5-7
-*/
-static BOOLEAN PeerMeasureReportSanity(struct rt_rtmp_adapter *pAd,
- void * pMsg,
- unsigned long MsgLen,
- u8 *pDialogToken,
- struct rt_measure_report_info *
- pMeasureReportInfo,
- u8 *pReportBuf)
-{
- struct rt_frame_802_11 * Fr = (struct rt_frame_802_11 *) pMsg;
- u8 *pFramePtr = Fr->Octet;
- BOOLEAN result = FALSE;
- struct rt_eid * eid_ptr;
- u8 *ptr;
-
- /* skip 802.11 header. */
- MsgLen -= sizeof(struct rt_header_802_11);
-
- /* skip category and action code. */
- pFramePtr += 2;
- MsgLen -= 2;
-
- if (pMeasureReportInfo == NULL)
- return result;
-
- NdisMoveMemory(pDialogToken, pFramePtr, 1);
- pFramePtr += 1;
- MsgLen -= 1;
-
- eid_ptr = (struct rt_eid *) pFramePtr;
- while (((u8 *) eid_ptr + eid_ptr->Len + 1) <
- ((u8 *)pFramePtr + MsgLen)) {
- switch (eid_ptr->Eid) {
- case IE_MEASUREMENT_REPORT:
- NdisMoveMemory(&pMeasureReportInfo->Token,
- eid_ptr->Octet, 1);
- NdisMoveMemory(&pMeasureReportInfo->ReportMode,
- eid_ptr->Octet + 1, 1);
- NdisMoveMemory(&pMeasureReportInfo->ReportType,
- eid_ptr->Octet + 2, 1);
- if (pMeasureReportInfo->ReportType == RM_BASIC) {
- struct rt_measure_basic_report * pReport =
- (struct rt_measure_basic_report *) pReportBuf;
- ptr = (u8 *)(eid_ptr->Octet + 3);
- NdisMoveMemory(&pReport->ChNum, ptr, 1);
- NdisMoveMemory(&pReport->MeasureStartTime,
- ptr + 1, 8);
- NdisMoveMemory(&pReport->MeasureDuration,
- ptr + 9, 2);
- NdisMoveMemory(&pReport->Map, ptr + 11, 1);
-
- } else if (pMeasureReportInfo->ReportType == RM_CCA) {
- struct rt_measure_cca_report * pReport =
- (struct rt_measure_cca_report *) pReportBuf;
- ptr = (u8 *)(eid_ptr->Octet + 3);
- NdisMoveMemory(&pReport->ChNum, ptr, 1);
- NdisMoveMemory(&pReport->MeasureStartTime,
- ptr + 1, 8);
- NdisMoveMemory(&pReport->MeasureDuration,
- ptr + 9, 2);
- NdisMoveMemory(&pReport->CCA_Busy_Fraction,
- ptr + 11, 1);
-
- } else if (pMeasureReportInfo->ReportType ==
- RM_RPI_HISTOGRAM) {
- struct rt_measure_rpi_report * pReport =
- (struct rt_measure_rpi_report *) pReportBuf;
- ptr = (u8 *)(eid_ptr->Octet + 3);
- NdisMoveMemory(&pReport->ChNum, ptr, 1);
- NdisMoveMemory(&pReport->MeasureStartTime,
- ptr + 1, 8);
- NdisMoveMemory(&pReport->MeasureDuration,
- ptr + 9, 2);
- NdisMoveMemory(&pReport->RPI_Density, ptr + 11,
- 8);
- }
- result = TRUE;
- break;
-
- default:
- break;
- }
- eid_ptr = (struct rt_eid *) ((u8 *) eid_ptr + 2 + eid_ptr->Len);
- }
-
- return result;
-}
-
-/*
- ==========================================================================
- Description:
- TPC Request action frame sanity check.
-
- Parametrs:
- 1. MLME message containing the received frame
- 2. message length.
- 3. Dialog Token.
-
- Return : None.
- ==========================================================================
- */
-static BOOLEAN PeerTpcReqSanity(struct rt_rtmp_adapter *pAd,
- void * pMsg,
- unsigned long MsgLen, u8 *pDialogToken)
-{
- struct rt_frame_802_11 * Fr = (struct rt_frame_802_11 *) pMsg;
- u8 *pFramePtr = Fr->Octet;
- BOOLEAN result = FALSE;
- struct rt_eid * eid_ptr;
-
- MsgLen -= sizeof(struct rt_header_802_11);
-
- /* skip category and action code. */
- pFramePtr += 2;
- MsgLen -= 2;
-
- if (pDialogToken == NULL)
- return result;
-
- NdisMoveMemory(pDialogToken, pFramePtr, 1);
- pFramePtr += 1;
- MsgLen -= 1;
-
- eid_ptr = (struct rt_eid *) pFramePtr;
- while (((u8 *) eid_ptr + eid_ptr->Len + 1) <
- ((u8 *)pFramePtr + MsgLen)) {
- switch (eid_ptr->Eid) {
- case IE_TPC_REQUEST:
- result = TRUE;
- break;
-
- default:
- break;
- }
- eid_ptr = (struct rt_eid *) ((u8 *) eid_ptr + 2 + eid_ptr->Len);
- }
-
- return result;
-}
-
-/*
- ==========================================================================
- Description:
- TPC Report action frame sanity check.
-
- Parametrs:
- 1. MLME message containing the received frame
- 2. message length.
- 3. Dialog Token.
- 4. TPC Report IE.
-
- Return : None.
- ==========================================================================
- */
-static BOOLEAN PeerTpcRepSanity(struct rt_rtmp_adapter *pAd,
- void * pMsg,
- unsigned long MsgLen,
- u8 *pDialogToken,
- struct rt_tpc_report_info * pTpcRepInfo)
-{
- struct rt_frame_802_11 * Fr = (struct rt_frame_802_11 *) pMsg;
- u8 *pFramePtr = Fr->Octet;
- BOOLEAN result = FALSE;
- struct rt_eid * eid_ptr;
-
- MsgLen -= sizeof(struct rt_header_802_11);
-
- /* skip category and action code. */
- pFramePtr += 2;
- MsgLen -= 2;
-
- if (pDialogToken == NULL)
- return result;
-
- NdisMoveMemory(pDialogToken, pFramePtr, 1);
- pFramePtr += 1;
- MsgLen -= 1;
-
- eid_ptr = (struct rt_eid *) pFramePtr;
- while (((u8 *) eid_ptr + eid_ptr->Len + 1) <
- ((u8 *)pFramePtr + MsgLen)) {
- switch (eid_ptr->Eid) {
- case IE_TPC_REPORT:
- NdisMoveMemory(&pTpcRepInfo->TxPwr, eid_ptr->Octet, 1);
- NdisMoveMemory(&pTpcRepInfo->LinkMargin,
- eid_ptr->Octet + 1, 1);
- result = TRUE;
- break;
-
- default:
- break;
- }
- eid_ptr = (struct rt_eid *) ((u8 *) eid_ptr + 2 + eid_ptr->Len);
- }
-
- return result;
-}
-
-/*
- ==========================================================================
- Description:
- Channel Switch Announcement action frame handler.
-
- Parametrs:
- Elme - MLME message containing the received frame
-
- Return : None.
- ==========================================================================
- */
-static void PeerChSwAnnAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
- struct rt_ch_sw_ann_info ChSwAnnInfo;
- struct rt_frame_802_11 * pFr = (struct rt_frame_802_11 *) Elem->Msg;
- u8 index = 0, Channel = 0, NewChannel = 0;
- unsigned long Bssidx = 0;
-
- NdisZeroMemory(&ChSwAnnInfo, sizeof(struct rt_ch_sw_ann_info));
- if (!PeerChSwAnnSanity(pAd, Elem->Msg, Elem->MsgLen, &ChSwAnnInfo)) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("Invalid Channel Switch Action Frame.\n"));
- return;
- }
-
- if (pAd->OpMode == OPMODE_STA) {
- Bssidx =
- BssTableSearch(&pAd->ScanTab, pFr->Hdr.Addr3,
- pAd->CommonCfg.Channel);
- if (Bssidx == BSS_NOT_FOUND) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("PeerChSwAnnAction - Bssidx is not found\n"));
- return;
- }
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("\n****Bssidx is %d, Channel = %d\n", index,
- pAd->ScanTab.BssEntry[Bssidx].Channel));
- hex_dump("SSID", pAd->ScanTab.BssEntry[Bssidx].Bssid, 6);
-
- Channel = pAd->CommonCfg.Channel;
- NewChannel = ChSwAnnInfo.Channel;
-
- if ((pAd->CommonCfg.bIEEE80211H == 1) && (NewChannel != 0)
- && (Channel != NewChannel)) {
- /* Switching to channel 1 can prevent from rescanning the current channel immediately (by auto reconnection). */
- /* In addition, clear the MLME queue and the scan table to discard the RX packets and previous scanning results. */
- AsicSwitchChannel(pAd, 1, FALSE);
- AsicLockChannel(pAd, 1);
- LinkDown(pAd, FALSE);
- MlmeQueueInit(&pAd->Mlme.Queue);
- BssTableInit(&pAd->ScanTab);
- RTMPusecDelay(1000000); /* use delay to prevent STA do reassoc */
-
- /* channel sanity check */
- for (index = 0; index < pAd->ChannelListNum; index++) {
- if (pAd->ChannelList[index].Channel ==
- NewChannel) {
- pAd->ScanTab.BssEntry[Bssidx].Channel =
- NewChannel;
- pAd->CommonCfg.Channel = NewChannel;
- AsicSwitchChannel(pAd,
- pAd->CommonCfg.
- Channel, FALSE);
- AsicLockChannel(pAd,
- pAd->CommonCfg.Channel);
- DBGPRINT(RT_DEBUG_TRACE,
- ("&&&&&&&&&&&&&&&&PeerChSwAnnAction - STA receive channel switch announcement IE (New Channel =%d)\n",
- NewChannel));
- break;
- }
- }
-
- if (index >= pAd->ChannelListNum) {
- DBGPRINT_ERR("&&&&&&&&&&&&&&&&&&&&&&&&&&PeerChSwAnnAction(can not find New Channel=%d in ChannelList[%d]\n", pAd->CommonCfg.Channel, pAd->ChannelListNum);
- }
- }
- }
-
- return;
-}
-
-/*
- ==========================================================================
- Description:
- Measurement Request action frame handler.
-
- Parametrs:
- Elme - MLME message containing the received frame
-
- Return : None.
- ==========================================================================
- */
-static void PeerMeasureReqAction(struct rt_rtmp_adapter *pAd,
- struct rt_mlme_queue_elem *Elem)
-{
- struct rt_frame_802_11 * pFr = (struct rt_frame_802_11 *) Elem->Msg;
- u8 DialogToken;
- struct rt_measure_req_info MeasureReqInfo;
- struct rt_measure_req MeasureReq;
- MEASURE_REPORT_MODE ReportMode;
-
- if (PeerMeasureReqSanity
- (pAd, Elem->Msg, Elem->MsgLen, &DialogToken, &MeasureReqInfo,
- &MeasureReq)) {
- ReportMode.word = 0;
- ReportMode.field.Incapable = 1;
- EnqueueMeasurementRep(pAd, pFr->Hdr.Addr2, DialogToken,
- MeasureReqInfo.Token, ReportMode.word,
- MeasureReqInfo.ReqType, 0, NULL);
- }
-
- return;
-}
-
-/*
- ==========================================================================
- Description:
- Measurement Report action frame handler.
-
- Parametrs:
- Elme - MLME message containing the received frame
-
- Return : None.
- ==========================================================================
- */
-static void PeerMeasureReportAction(struct rt_rtmp_adapter *pAd,
- struct rt_mlme_queue_elem *Elem)
-{
- struct rt_measure_report_info MeasureReportInfo;
- struct rt_frame_802_11 * pFr = (struct rt_frame_802_11 *) Elem->Msg;
- u8 DialogToken;
- u8 *pMeasureReportInfo;
-
-/* if (pAd->CommonCfg.bIEEE80211H != TRUE) */
-/* return; */
-
- pMeasureReportInfo = kmalloc(sizeof(struct rt_measure_rpi_report), GFP_ATOMIC);
- if (pMeasureReportInfo == NULL) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("%s unable to alloc memory for measure report buffer (size=%zu).\n",
- __func__, sizeof(struct rt_measure_rpi_report)));
- return;
- }
-
- NdisZeroMemory(&MeasureReportInfo, sizeof(struct rt_measure_report_info));
- NdisZeroMemory(pMeasureReportInfo, sizeof(struct rt_measure_rpi_report));
- if (PeerMeasureReportSanity
- (pAd, Elem->Msg, Elem->MsgLen, &DialogToken, &MeasureReportInfo,
- pMeasureReportInfo)) {
- do {
- struct rt_measure_req_entry *pEntry = NULL;
-
- /* Not a autonomous measure report. */
- /* check the dialog token field. drop it if the dialog token doesn't match. */
- if ((DialogToken != 0)
- && ((pEntry = MeasureReqLookUp(pAd, DialogToken)) ==
- NULL))
- break;
-
- if (pEntry != NULL)
- MeasureReqDelete(pAd, pEntry->DialogToken);
-
- if (MeasureReportInfo.ReportType == RM_BASIC) {
- struct rt_measure_basic_report * pBasicReport =
- (struct rt_measure_basic_report *) pMeasureReportInfo;
- if ((pBasicReport->Map.field.Radar)
- &&
- (DfsRequirementCheck
- (pAd, pBasicReport->ChNum) == TRUE)) {
- NotifyChSwAnnToPeerAPs(pAd,
- pFr->Hdr.Addr1,
- pFr->Hdr.Addr2,
- 1,
- pBasicReport->
- ChNum);
- StartDFSProcedure(pAd,
- pBasicReport->ChNum,
- 1);
- }
- }
- } while (FALSE);
- } else
- DBGPRINT(RT_DEBUG_TRACE,
- ("Invalid Measurement Report Frame.\n"));
-
- kfree(pMeasureReportInfo);
-
- return;
-}
-
-/*
- ==========================================================================
- Description:
- TPC Request action frame handler.
-
- Parametrs:
- Elme - MLME message containing the received frame
-
- Return : None.
- ==========================================================================
- */
-static void PeerTpcReqAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
- struct rt_frame_802_11 * pFr = (struct rt_frame_802_11 *) Elem->Msg;
- u8 *pFramePtr = pFr->Octet;
- u8 DialogToken;
- u8 TxPwr = GetCurTxPwr(pAd, Elem->Wcid);
- u8 LinkMargin = 0;
- char RealRssi;
-
- /* link margin: Ratio of the received signal power to the minimum desired by the station (STA). The */
- /* STA may incorporate rate information and channel conditions, including interference, into its computation */
- /* of link margin. */
-
- RealRssi = RTMPMaxRssi(pAd, ConvertToRssi(pAd, Elem->Rssi0, RSSI_0),
- ConvertToRssi(pAd, Elem->Rssi1, RSSI_1),
- ConvertToRssi(pAd, Elem->Rssi2, RSSI_2));
-
- /* skip Category and action code. */
- pFramePtr += 2;
-
- /* Dialog token. */
- NdisMoveMemory(&DialogToken, pFramePtr, 1);
-
- LinkMargin = (RealRssi / MIN_RCV_PWR);
- if (PeerTpcReqSanity(pAd, Elem->Msg, Elem->MsgLen, &DialogToken))
- EnqueueTPCRep(pAd, pFr->Hdr.Addr2, DialogToken, TxPwr,
- LinkMargin);
-
- return;
-}
-
-/*
- ==========================================================================
- Description:
- TPC Report action frame handler.
-
- Parametrs:
- Elme - MLME message containing the received frame
-
- Return : None.
- ==========================================================================
- */
-static void PeerTpcRepAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
- u8 DialogToken;
- struct rt_tpc_report_info TpcRepInfo;
- struct rt_tpc_req_entry *pEntry = NULL;
-
- NdisZeroMemory(&TpcRepInfo, sizeof(struct rt_tpc_report_info));
- if (PeerTpcRepSanity
- (pAd, Elem->Msg, Elem->MsgLen, &DialogToken, &TpcRepInfo)) {
- pEntry = TpcReqLookUp(pAd, DialogToken);
- if (pEntry != NULL) {
- TpcReqDelete(pAd, pEntry->DialogToken);
- DBGPRINT(RT_DEBUG_TRACE,
- ("%s: DialogToken=%x, TxPwr=%d, LinkMargin=%d\n",
- __func__, DialogToken, TpcRepInfo.TxPwr,
- TpcRepInfo.LinkMargin));
- }
- }
-
- return;
-}
-
-/*
- ==========================================================================
- Description:
- Spectrun action frames Handler such as channel switch annoucement,
- measurement report, measurement request actions frames.
-
- Parametrs:
- Elme - MLME message containing the received frame
-
- Return : None.
- ==========================================================================
- */
-void PeerSpectrumAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
-
- u8 Action = Elem->Msg[LENGTH_802_11 + 1];
-
- if (pAd->CommonCfg.bIEEE80211H != TRUE)
- return;
-
- switch (Action) {
- case SPEC_MRQ:
- /* current rt2860 unable do such measure specified in Measurement Request. */
- /* reject all measurement request. */
- PeerMeasureReqAction(pAd, Elem);
- break;
-
- case SPEC_MRP:
- PeerMeasureReportAction(pAd, Elem);
- break;
-
- case SPEC_TPCRQ:
- PeerTpcReqAction(pAd, Elem);
- break;
-
- case SPEC_TPCRP:
- PeerTpcRepAction(pAd, Elem);
- break;
-
- case SPEC_CHANNEL_SWITCH:
-
- PeerChSwAnnAction(pAd, Elem);
- break;
- }
-
- return;
-}
-
-/*
- ==========================================================================
- Description:
-
- Parametrs:
-
- Return : None.
- ==========================================================================
- */
-int Set_MeasureReq_Proc(struct rt_rtmp_adapter *pAd, char *arg)
-{
- u32 Aid = 1;
- u32 ArgIdx;
- char *thisChar;
-
- MEASURE_REQ_MODE MeasureReqMode;
- u8 MeasureReqToken = RandomByte(pAd);
- u8 MeasureReqType = RM_BASIC;
- u8 MeasureCh = 1;
- u64 MeasureStartTime = GetCurrentTimeStamp(pAd);
- struct rt_measure_req MeasureReq;
- u8 TotalLen;
-
- struct rt_header_802_11 ActHdr;
- u8 *pOutBuffer = NULL;
- int NStatus;
- unsigned long FrameLen;
-
- NStatus = MlmeAllocateMemory(pAd, (void *)& pOutBuffer); /*Get an unused nonpaged memory */
- if (NStatus != NDIS_STATUS_SUCCESS) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("%s() allocate memory failed \n", __func__));
- goto END_OF_MEASURE_REQ;
- }
-
- ArgIdx = 1;
- while ((thisChar = strsep((char **)&arg, "-")) != NULL) {
- switch (ArgIdx) {
- case 1: /* Aid. */
- Aid = (u8)simple_strtol(thisChar, 0, 16);
- break;
-
- case 2: /* Measurement Request Type. */
- MeasureReqType = simple_strtol(thisChar, 0, 16);
- if (MeasureReqType > 3) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("%s: unknow MeasureReqType(%d)\n",
- __func__, MeasureReqType));
- goto END_OF_MEASURE_REQ;
- }
- break;
-
- case 3: /* Measurement channel. */
- MeasureCh = (u8)simple_strtol(thisChar, 0, 16);
- break;
- }
- ArgIdx++;
- }
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("%s::Aid = %d, MeasureReqType=%d MeasureCh=%d\n", __func__,
- Aid, MeasureReqType, MeasureCh));
- if (!VALID_WCID(Aid)) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("%s: unknow sta of Aid(%d)\n", __func__, Aid));
- goto END_OF_MEASURE_REQ;
- }
-
- MeasureReqMode.word = 0;
- MeasureReqMode.field.Enable = 1;
-
- MeasureReqInsert(pAd, MeasureReqToken);
-
- /* build action frame header. */
- MgtMacHeaderInit(pAd, &ActHdr, SUBTYPE_ACTION, 0,
- pAd->MacTab.Content[Aid].Addr, pAd->CurrentAddress);
-
- NdisMoveMemory(pOutBuffer, (char *)& ActHdr, sizeof(struct rt_header_802_11));
- FrameLen = sizeof(struct rt_header_802_11);
-
- TotalLen = sizeof(struct rt_measure_req_info) + sizeof(struct rt_measure_req);
-
- MakeMeasurementReqFrame(pAd, pOutBuffer, &FrameLen,
- sizeof(struct rt_measure_req_info), CATEGORY_RM, RM_BASIC,
- MeasureReqToken, MeasureReqMode.word,
- MeasureReqType, 0);
-
- MeasureReq.ChNum = MeasureCh;
- MeasureReq.MeasureStartTime = cpu2le64(MeasureStartTime);
- MeasureReq.MeasureDuration = cpu2le16(2000);
-
- {
- unsigned long TempLen;
- MakeOutgoingFrame(pOutBuffer + FrameLen, &TempLen,
- sizeof(struct rt_measure_req), &MeasureReq,
- END_OF_ARGS);
- FrameLen += TempLen;
- }
-
- MiniportMMRequest(pAd, QID_AC_BE, pOutBuffer, (u32)FrameLen);
-
-END_OF_MEASURE_REQ:
- MlmeFreeMemory(pAd, pOutBuffer);
-
- return TRUE;
-}
-
-int Set_TpcReq_Proc(struct rt_rtmp_adapter *pAd, char *arg)
-{
- u32 Aid;
-
- u8 TpcReqToken = RandomByte(pAd);
-
- Aid = (u32)simple_strtol(arg, 0, 16);
-
- DBGPRINT(RT_DEBUG_TRACE, ("%s::Aid = %d\n", __func__, Aid));
- if (!VALID_WCID(Aid)) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("%s: unknow sta of Aid(%d)\n", __func__, Aid));
- return TRUE;
- }
-
- TpcReqInsert(pAd, TpcReqToken);
-
- EnqueueTPCReq(pAd, pAd->MacTab.Content[Aid].Addr, TpcReqToken);
-
- return TRUE;
-}
diff --git a/drivers/staging/rt2860/crypt_hmac.h b/drivers/staging/rt2860/crypt_hmac.h
deleted file mode 100644
index 7a56515..0000000
--- a/drivers/staging/rt2860/crypt_hmac.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
- */
-
-/****************************************************************************
- Module Name:
- HMAC
-
- Abstract:
- FIPS 198: The Keyed-Hash Message Authentication Code (HMAC)
-
- Revision History:
- Who When What
- -------- ---------- ------------------------------------------
- Eddy 2008/11/24 Create HMAC-SHA1, HMAC-SHA256
-***************************************************************************/
-#ifndef __CRYPT_HMAC_H__
-#define __CRYPT_HMAC_H__
-
-#ifdef CRYPT_TESTPLAN
-#include "crypt_testplan.h"
-#else
-#include "rt_config.h"
-#endif /* CRYPT_TESTPLAN */
-
-#ifdef SHA1_SUPPORT
-#define HMAC_SHA1_SUPPORT
-void HMAC_SHA1(IN const u8 Key[],
- u32 KeyLen,
- IN const u8 Message[],
- u32 MessageLen, u8 MAC[], u32 MACLen);
-#endif /* SHA1_SUPPORT */
-
-#ifdef MD5_SUPPORT
-#define HMAC_MD5_SUPPORT
-void HMAC_MD5(IN const u8 Key[],
- u32 KeyLen,
- IN const u8 Message[],
- u32 MessageLen, u8 MAC[], u32 MACLen);
-#endif /* MD5_SUPPORT */
-
-#endif /* __CRYPT_HMAC_H__ */
diff --git a/drivers/staging/rt2860/crypt_md5.h b/drivers/staging/rt2860/crypt_md5.h
deleted file mode 100644
index 26f9745..0000000
--- a/drivers/staging/rt2860/crypt_md5.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
- */
-
-/****************************************************************************
- Module Name:
- MD5
-
- Abstract:
- RFC1321: The MD5 Message-Digest Algorithm
-
- Revision History:
- Who When What
- -------- ---------- ------------------------------------------
- Eddy 2008/11/24 Create md5
-***************************************************************************/
-
-#ifndef __CRYPT_MD5_H__
-#define __CRYPT_MD5_H__
-
-#ifdef CRYPT_TESTPLAN
-#include "crypt_testplan.h"
-#else
-#include "rt_config.h"
-#endif /* CRYPT_TESTPLAN */
-
-/* Algorithm options */
-#define MD5_SUPPORT
-
-#ifdef MD5_SUPPORT
-#define MD5_BLOCK_SIZE 64 /* 512 bits = 64 bytes */
-#define MD5_DIGEST_SIZE 16 /* 128 bits = 16 bytes */
-
-struct rt_md5_ctx_struc {
- u32 HashValue[4];
- u64 MessageLen;
- u8 Block[MD5_BLOCK_SIZE];
- u32 BlockLen;
-};
-
-void MD5_Init(struct rt_md5_ctx_struc *pMD5_CTX);
-void MD5_Hash(struct rt_md5_ctx_struc *pMD5_CTX);
-void MD5_Append(struct rt_md5_ctx_struc *pMD5_CTX,
- IN const u8 Message[], u32 MessageLen);
-void MD5_End(struct rt_md5_ctx_struc *pMD5_CTX, u8 DigestMessage[]);
-void RT_MD5(IN const u8 Message[],
- u32 MessageLen, u8 DigestMessage[]);
-#endif /* MD5_SUPPORT */
-
-#endif /* __CRYPT_MD5_H__ */
diff --git a/drivers/staging/rt2860/crypt_sha2.h b/drivers/staging/rt2860/crypt_sha2.h
deleted file mode 100644
index 20d11ab..0000000
--- a/drivers/staging/rt2860/crypt_sha2.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
- */
-
-/****************************************************************************
- Module Name:
- SHA2
-
- Abstract:
- FIPS 180-2: Secure Hash Standard (SHS)
-
- Revision History:
- Who When What
- -------- ---------- ------------------------------------------
- Eddy 2008/11/24 Create SHA1
- Eddy 2008/07/23 Create SHA256
-***************************************************************************/
-
-#ifndef __CRYPT_SHA2_H__
-#define __CRYPT_SHA2_H__
-
-#ifdef CRYPT_TESTPLAN
-#include "crypt_testplan.h"
-#else
-#include "rt_config.h"
-#endif /* CRYPT_TESTPLAN */
-
-/* Algorithm options */
-#define SHA1_SUPPORT
-
-#ifdef SHA1_SUPPORT
-#define SHA1_BLOCK_SIZE 64 /* 512 bits = 64 bytes */
-#define SHA1_DIGEST_SIZE 20 /* 160 bits = 20 bytes */
-struct rt_sha1_ctx {
- u32 HashValue[5]; /* 5 = (SHA1_DIGEST_SIZE / 32) */
- u64 MessageLen; /* total size */
- u8 Block[SHA1_BLOCK_SIZE];
- u32 BlockLen;
-};
-
-void RT_SHA1_Init(struct rt_sha1_ctx *pSHA_CTX);
-void SHA1_Hash(struct rt_sha1_ctx *pSHA_CTX);
-void SHA1_Append(struct rt_sha1_ctx *pSHA_CTX,
- IN const u8 Message[], u32 MessageLen);
-void SHA1_End(struct rt_sha1_ctx *pSHA_CTX, u8 DigestMessage[]);
-void RT_SHA1(IN const u8 Message[],
- u32 MessageLen, u8 DigestMessage[]);
-#endif /* SHA1_SUPPORT */
-
-#endif /* __CRYPT_SHA2_H__ */
diff --git a/drivers/staging/rt2860/dfs.h b/drivers/staging/rt2860/dfs.h
deleted file mode 100644
index 5fbab25..0000000
--- a/drivers/staging/rt2860/dfs.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- dfs.h
-
- Abstract:
- Support DFS function.
-
- Revision History:
- Who When What
- -------- ---------- ----------------------------------------------
- Fonchi 03-12-2007 created
-*/
-
-BOOLEAN RadarChannelCheck(struct rt_rtmp_adapter *pAd, u8 Ch);
diff --git a/drivers/staging/rt2860/eeprom.h b/drivers/staging/rt2860/eeprom.h
deleted file mode 100644
index 72c8fb9..0000000
--- a/drivers/staging/rt2860/eeprom.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- eeprom.h
-
- Abstract:
- Miniport header file for eeprom related information
-
- Revision History:
- Who When What
- -------- ---------- ----------------------------------------------
-*/
-#ifndef __EEPROM_H__
-#define __EEPROM_H__
-
-#ifdef RTMP_PCI_SUPPORT
-/*************************************************************************
- * Public function declarations for prom-based chipset
- ************************************************************************/
-int rtmp_ee_prom_read16(struct rt_rtmp_adapter *pAd,
- u16 Offset, u16 *pValue);
-#endif /* RTMP_PCI_SUPPORT // */
-#ifdef RTMP_USB_SUPPORT
-/*************************************************************************
- * Public function declarations for usb-based prom chipset
- ************************************************************************/
-int RTUSBReadEEPROM16(struct rt_rtmp_adapter *pAd,
- u16 offset, u16 *pData);
-#endif /* RTMP_USB_SUPPORT // */
-
-#ifdef RT30xx
-#ifdef RTMP_EFUSE_SUPPORT
-int rtmp_ee_efuse_read16(struct rt_rtmp_adapter *pAd,
- u16 Offset, u16 *pValue);
-#endif /* RTMP_EFUSE_SUPPORT // */
-#endif /* RT30xx // */
-
-/*************************************************************************
- * Public function declarations for prom operation callback functions setting
- ************************************************************************/
-int RtmpChipOpsEepromHook(struct rt_rtmp_adapter *pAd, int infType);
-
-#endif /* __EEPROM_H__ // */
diff --git a/drivers/staging/rt2860/iface/rtmp_pci.h b/drivers/staging/rt2860/iface/rtmp_pci.h
deleted file mode 100644
index 3d66e38..0000000
--- a/drivers/staging/rt2860/iface/rtmp_pci.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-*/
-
-#ifndef __RTMP_PCI_H__
-#define __RTMP_PCI_H__
-
-#define RT28XX_HANDLE_DEV_ASSIGN(handle, dev_p) \
- ((struct os_cookie *)handle)->pci_dev = dev_p;
-
-#ifdef LINUX
-/* set driver data */
-#define RT28XX_DRVDATA_SET(_a) pci_set_drvdata(_a, net_dev);
-
-#define RT28XX_PUT_DEVICE(dev_p)
-
-#define SA_SHIRQ IRQF_SHARED
-
-#ifdef PCI_MSI_SUPPORT
-#define RTMP_MSI_ENABLE(_pAd) \
- { struct os_cookie *_pObj = (struct os_cookie *)(_pAd->OS_Cookie); \
- (_pAd)->HaveMsi = pci_enable_msi(_pObj->pci_dev) \
- == 0 ? TRUE : FALSE; \
- }
-
-#define RTMP_MSI_DISABLE(_pAd) \
- { struct os_cookie *_pObj = (struct os_cookie *)(_pAd->OS_Cookie); \
- if (_pAd->HaveMsi == TRUE) \
- pci_disable_msi(_pObj->pci_dev); \
- _pAd->HaveMsi = FALSE; \
- }
-#else
-#define RTMP_MSI_ENABLE(_pAd) do {} while (0)
-#define RTMP_MSI_DISABLE(_pAd) do {} while (0)
-#endif /* PCI_MSI_SUPPORT */
-
-#define RTMP_PCI_DEV_UNMAP() \
-{ if (net_dev->base_addr) { \
- iounmap((void *)(net_dev->base_addr)); \
- release_mem_region(pci_resource_start(dev_p, 0), \
- pci_resource_len(dev_p, 0)); } \
- if (net_dev->irq) \
- pci_release_regions(dev_p); }
-
-#define PCI_REG_READ_WORD(pci_dev, offset, Configuration) {\
- if (pci_read_config_word(pci_dev, offset, ®16) == 0) \
- Configuration = le2cpu16(reg16); \
- else \
- Configuration = 0; }
-
-#define PCI_REG_WIRTE_WORD(pci_dev, offset, Configuration) {\
- reg16 = cpu2le16(Configuration); \
- pci_write_config_word(pci_dev, offset, reg16); }
-
-#endif /* LINUX */
-
-#endif /* __RTMP_PCI_H__ */
diff --git a/drivers/staging/rt2860/iface/rtmp_usb.h b/drivers/staging/rt2860/iface/rtmp_usb.h
deleted file mode 100644
index 5712896..0000000
--- a/drivers/staging/rt2860/iface/rtmp_usb.h
+++ /dev/null
@@ -1,196 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-*/
-
-#ifndef __RTMP_USB_H__
-#define __RTMP_USB_H__
-
-#include "../rtusb_io.h"
-
-#ifdef LINUX
-#include <linux/usb.h>
-#endif /* LINUX */
-
-extern u8 EpToQueue[6];
-
-#define RXBULKAGGRE_ZISE 12
-#define MAX_TXBULK_LIMIT (LOCAL_TXBUF_SIZE*(BULKAGGRE_ZISE-1))
-#define MAX_TXBULK_SIZE (LOCAL_TXBUF_SIZE*BULKAGGRE_ZISE)
-#define MAX_RXBULK_SIZE (LOCAL_TXBUF_SIZE*RXBULKAGGRE_ZISE)
-#define MAX_MLME_HANDLER_MEMORY 20
-
-/* Flags for Bulkflags control for bulk out data */
-#define fRTUSB_BULK_OUT_DATA_NULL 0x00000001
-#define fRTUSB_BULK_OUT_RTS 0x00000002
-#define fRTUSB_BULK_OUT_MLME 0x00000004
-
-#define fRTUSB_BULK_OUT_PSPOLL 0x00000010
-#define fRTUSB_BULK_OUT_DATA_FRAG 0x00000020
-#define fRTUSB_BULK_OUT_DATA_FRAG_2 0x00000040
-#define fRTUSB_BULK_OUT_DATA_FRAG_3 0x00000080
-#define fRTUSB_BULK_OUT_DATA_FRAG_4 0x00000100
-
-#define fRTUSB_BULK_OUT_DATA_NORMAL 0x00010000
-#define fRTUSB_BULK_OUT_DATA_NORMAL_2 0x00020000
-#define fRTUSB_BULK_OUT_DATA_NORMAL_3 0x00040000
-#define fRTUSB_BULK_OUT_DATA_NORMAL_4 0x00080000
-
-/* TODO:move to ./ate/include/iface/ate_usb.h */
-
-#define FREE_HTTX_RING(_pCookie, _pipeId, _txContext) \
-{ \
- if ((_txContext)->ENextBulkOutPosition == \
- (_txContext)->CurWritePosition) {\
- (_txContext)->bRingEmpty = TRUE; \
- } \
- /*NdisInterlockedDecrement(&(_p)->TxCount); */\
-}
-
-/******************************************************************************
-
- USB Bulk operation related definitions
-
-******************************************************************************/
-
-#ifdef LINUX
-#define BULKAGGRE_ZISE 100
-#define RT28XX_PUT_DEVICE usb_put_dev
-#define RTUSB_ALLOC_URB(iso) usb_alloc_urb(iso, GFP_ATOMIC)
-#define RTUSB_SUBMIT_URB(pUrb) usb_submit_urb(pUrb, \
- GFP_ATOMIC)
-#define RTUSB_URB_ALLOC_BUFFER(pUsb_Dev, \
- BufSize, \
- pDma_addr) \
- usb_alloc_coherent(\
- pUsb_Dev, \
- BufSize, \
- GFP_ATOMIC, \
- pDma_addr)
-#define RTUSB_URB_FREE_BUFFER(pUsb_Dev, \
- BufSize, \
- pTransferBuf, \
- Dma_addr) \
- usb_free_coherent( \
- pUsb_Dev, \
- BufSize, \
- pTransferBuf, \
- Dma_addr)
-
-#define RTUSB_FREE_URB(pUrb) usb_free_urb(pUrb)
-
-/* unlink urb */
-#define RTUSB_UNLINK_URB(pUrb) usb_kill_urb(pUrb)
-
-extern void dump_urb(struct urb *purb);
-
-#define InterlockedIncrement atomic_inc
-#define NdisInterlockedIncrement atomic_inc
-#define InterlockedDecrement atomic_dec
-#define NdisInterlockedDecrement atomic_dec
-#define InterlockedExchange atomic_set
-
-#endif /* LINUX */
-
-#define NT_SUCCESS(status) (((status) >= 0) ? (TRUE) : (FALSE))
-
-#define USBD_TRANSFER_DIRECTION_OUT 0
-#define USBD_TRANSFER_DIRECTION_IN 0
-#define USBD_SHORT_TRANSFER_OK 0
-#define PURB struct urb *
-
-#define PIRP void *
-#define NDIS_OID u32
-#ifndef USB_ST_NOERROR
-#define USB_ST_NOERROR 0
-#endif
-
-/* vendor-specific control operations */
-#define CONTROL_TIMEOUT_JIFFIES ((100 * OS_HZ) / 1000)
-#define UNLINK_TIMEOUT_MS 3
-
-void RTUSBBulkOutDataPacketComplete(struct urb *purb, struct pt_regs *pt_regs);
-void RTUSBBulkOutMLMEPacketComplete(struct urb *pUrb, struct pt_regs *pt_regs);
-void RTUSBBulkOutNullFrameComplete(struct urb *pUrb, struct pt_regs *pt_regs);
-void RTUSBBulkOutRTSFrameComplete(struct urb *pUrb, struct pt_regs *pt_regs);
-void RTUSBBulkOutPsPollComplete(struct urb *pUrb, struct pt_regs *pt_regs);
-void RTUSBBulkRxComplete(struct urb *pUrb, struct pt_regs *pt_regs);
-
-#ifdef KTHREAD_SUPPORT
-#define RTUSBMlmeUp(pAd) \
- do { \
- struct rt_rtmp_os_task *_pTask = &((pAd)->mlmeTask);\
- if (_pTask->kthread_task) {\
- _pTask->kthread_running = TRUE; \
- wake_up(&_pTask->kthread_q); \
- } \
- } while (0)
-#else
-#define RTUSBMlmeUp(pAd) \
- do { \
- struct rt_rtmp_os_task *_pTask = &((pAd)->mlmeTask);\
- CHECK_PID_LEGALITY(_pTask->taskPID) \
- { \
- RTMP_SEM_EVENT_UP(&(_pTask->taskSema)); \
- } \
- } while (0)
-#endif
-
-#ifdef KTHREAD_SUPPORT
-#define RTUSBCMDUp(pAd) \
- do { \
- struct rt_rtmp_os_task *_pTask = &((pAd)->cmdQTask); \
- { \
- _pTask->kthread_running = TRUE; \
- wake_up(&_pTask->kthread_q); \
- } \
- } while (0)
-
-#else
-#define RTUSBCMDUp(pAd) \
- do { \
- struct rt_rtmp_os_task *_pTask = &((pAd)->cmdQTask); \
- CHECK_PID_LEGALITY(_pTask->taskPID) \
- {\
- RTMP_SEM_EVENT_UP(&(_pTask->taskSema)); \
- } \
- } while (0)
-#endif
-
-#define DEVICE_VENDOR_REQUEST_OUT 0x40
-#define DEVICE_VENDOR_REQUEST_IN 0xc0
-/*#define INTERFACE_VENDOR_REQUEST_OUT 0x41*/
-/*#define INTERFACE_VENDOR_REQUEST_IN 0xc1*/
-
-#define BULKOUT_MGMT_RESET_FLAG 0x80
-
-#define RTUSB_SET_BULK_FLAG(_M, _F) ((_M)->BulkFlags |= (_F))
-#define RTUSB_CLEAR_BULK_FLAG(_M, _F) ((_M)->BulkFlags &= ~(_F))
-#define RTUSB_TEST_BULK_FLAG(_M, _F) (((_M)->BulkFlags & (_F)) != 0)
-
-#define RTMP_IRQ_REQUEST(net_dev) do {} while (0)
-#define RTMP_IRQ_RELEASE(net_dev) do {} while (0)
-
-#endif /* __RTMP_USB_H__ */
diff --git a/drivers/staging/rt2860/mlme.h b/drivers/staging/rt2860/mlme.h
deleted file mode 100644
index a285851..0000000
--- a/drivers/staging/rt2860/mlme.h
+++ /dev/null
@@ -1,1050 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- mlme.h
-
- Abstract:
-
- Revision History:
- Who When What
- -------- ---------- ------------------------------
- John Chang 2003-08-28 Created
- John Chang 2004-09-06 modified for RT2600
- Justin P. Mattock 11/07/2010 Fix typos in comments
-
-*/
-#ifndef __MLME_H__
-#define __MLME_H__
-
-#include "rtmp_dot11.h"
-
-/* maximum supported capability information */
-/* ESS, IBSS, Privacy, Short Preamble, Spectrum mgmt, Short Slot */
-#define SUPPORTED_CAPABILITY_INFO 0x0533
-
-#define END_OF_ARGS -1
-#define LFSR_MASK 0x80000057
-#define MLME_TASK_EXEC_INTV 100/*200*/ /* */
-#define LEAD_TIME 5
-#define MLME_TASK_EXEC_MULTIPLE 10 /*5*/ /* MLME_TASK_EXEC_MULTIPLE * MLME_TASK_EXEC_INTV = 1 sec */
-#define REORDER_EXEC_INTV 100 /* 0.1 sec */
-
-/* The definition of Radar detection duration region */
-#define CE 0
-#define FCC 1
-#define JAP 2
-#define JAP_W53 3
-#define JAP_W56 4
-#define MAX_RD_REGION 5
-
-#define BEACON_LOST_TIME (4 * OS_HZ) /* 2048 msec = 2 sec */
-
-#define DLS_TIMEOUT 1200 /* unit: msec */
-#define AUTH_TIMEOUT 300 /* unit: msec */
-#define ASSOC_TIMEOUT 300 /* unit: msec */
-#define JOIN_TIMEOUT 2000 /* unit: msec */
-#define SHORT_CHANNEL_TIME 90 /* unit: msec */
-#define MIN_CHANNEL_TIME 110 /* unit: msec, for dual band scan */
-#define MAX_CHANNEL_TIME 140 /* unit: msec, for single band scan */
-#define FAST_ACTIVE_SCAN_TIME 30 /* Active scan waiting for probe response time */
-#define CW_MIN_IN_BITS 4 /* actual CwMin = 2^CW_MIN_IN_BITS - 1 */
-#define LINK_DOWN_TIMEOUT 20000 /* unit: msec */
-#define AUTO_WAKEUP_TIMEOUT 70 /*unit: msec */
-
-#define CW_MAX_IN_BITS 10 /* actual CwMax = 2^CW_MAX_IN_BITS - 1 */
-
-/* Note: RSSI_TO_DBM_OFFSET has been changed to variable for new RF (2004-0720). */
-/* Should not refer to this constant anymore */
-/*#define RSSI_TO_DBM_OFFSET 120 // for RT2530 RSSI-115 = dBm */
-#define RSSI_FOR_MID_TX_POWER -55 /* -55 db is considered mid-distance */
-#define RSSI_FOR_LOW_TX_POWER -45 /* -45 db is considered very short distance and */
- /* eligible to use a lower TX power */
-#define RSSI_FOR_LOWEST_TX_POWER -30
-/*#define MID_TX_POWER_DELTA 0 // 0 db from full TX power upon mid-distance to AP */
-#define LOW_TX_POWER_DELTA 6 /* -3 db from full TX power upon very short distance. 1 grade is 0.5 db */
-#define LOWEST_TX_POWER_DELTA 16 /* -8 db from full TX power upon shortest distance. 1 grade is 0.5 db */
-
-#define RSSI_TRIGGERED_UPON_BELOW_THRESHOLD 0
-#define RSSI_TRIGGERED_UPON_EXCCEED_THRESHOLD 1
-#define RSSI_THRESHOLD_FOR_ROAMING 25
-#define RSSI_DELTA 5
-
-/* Channel Quality Indication */
-#define CQI_IS_GOOD(cqi) ((cqi) >= 50)
-/*#define CQI_IS_FAIR(cqi) (((cqi) >= 20) && ((cqi) < 50)) */
-#define CQI_IS_POOR(cqi) (cqi < 50) /*(((cqi) >= 5) && ((cqi) < 20)) */
-#define CQI_IS_BAD(cqi) (cqi < 5)
-#define CQI_IS_DEAD(cqi) (cqi == 0)
-
-/* weighting factor to calculate Channel quality, total should be 100% */
-#define RSSI_WEIGHTING 50
-#define TX_WEIGHTING 30
-#define RX_WEIGHTING 20
-
-#define BSS_NOT_FOUND 0xFFFFFFFF
-
-#define MAX_LEN_OF_MLME_QUEUE 40 /*10 */
-
-#define SCAN_PASSIVE 18 /* scan with no probe request, only wait beacon and probe response */
-#define SCAN_ACTIVE 19 /* scan with probe request, and wait beacon and probe response */
-#define SCAN_CISCO_PASSIVE 20 /* Single channel passive scan */
-#define SCAN_CISCO_ACTIVE 21 /* Single channel active scan */
-#define SCAN_CISCO_NOISE 22 /* Single channel passive scan for noise histogram collection */
-#define SCAN_CISCO_CHANNEL_LOAD 23 /* Single channel passive scan for channel load collection */
-#define FAST_SCAN_ACTIVE 24 /* scan with probe request, and wait beacon and probe response */
-
-#define MAC_ADDR_IS_GROUP(Addr) (((Addr[0]) & 0x01))
-#define MAC_ADDR_HASH(Addr) (Addr[0] ^ Addr[1] ^ Addr[2] ^ Addr[3] ^ Addr[4] ^ Addr[5])
-#define MAC_ADDR_HASH_INDEX(Addr) (MAC_ADDR_HASH(Addr) % HASH_TABLE_SIZE)
-#define TID_MAC_HASH(Addr, TID) (TID^Addr[0] ^ Addr[1] ^ Addr[2] ^ Addr[3] ^ Addr[4] ^ Addr[5])
-#define TID_MAC_HASH_INDEX(Addr, TID) (TID_MAC_HASH(Addr, TID) % HASH_TABLE_SIZE)
-
-/* LED Control */
-/* association ON. one LED ON. another blinking when TX, OFF when idle */
-/* no association, both LED off */
-#define ASIC_LED_ACT_ON(pAd) RTMP_IO_WRITE32(pAd, MAC_CSR14, 0x00031e46)
-#define ASIC_LED_ACT_OFF(pAd) RTMP_IO_WRITE32(pAd, MAC_CSR14, 0x00001e46)
-
-/* bit definition of the 2-byte pBEACON->Capability field */
-#define CAP_IS_ESS_ON(x) (((x) & 0x0001) != 0)
-#define CAP_IS_IBSS_ON(x) (((x) & 0x0002) != 0)
-#define CAP_IS_CF_POLLABLE_ON(x) (((x) & 0x0004) != 0)
-#define CAP_IS_CF_POLL_REQ_ON(x) (((x) & 0x0008) != 0)
-#define CAP_IS_PRIVACY_ON(x) (((x) & 0x0010) != 0)
-#define CAP_IS_SHORT_PREAMBLE_ON(x) (((x) & 0x0020) != 0)
-#define CAP_IS_PBCC_ON(x) (((x) & 0x0040) != 0)
-#define CAP_IS_AGILITY_ON(x) (((x) & 0x0080) != 0)
-#define CAP_IS_SPECTRUM_MGMT(x) (((x) & 0x0100) != 0) /* 802.11e d9 */
-#define CAP_IS_QOS(x) (((x) & 0x0200) != 0) /* 802.11e d9 */
-#define CAP_IS_SHORT_SLOT(x) (((x) & 0x0400) != 0)
-#define CAP_IS_APSD(x) (((x) & 0x0800) != 0) /* 802.11e d9 */
-#define CAP_IS_IMMED_BA(x) (((x) & 0x1000) != 0) /* 802.11e d9 */
-#define CAP_IS_DSSS_OFDM(x) (((x) & 0x2000) != 0)
-#define CAP_IS_DELAY_BA(x) (((x) & 0x4000) != 0) /* 802.11e d9 */
-
-#define CAP_GENERATE(ess, ibss, priv, s_pre, s_slot, spectrum) (((ess) ? 0x0001 : 0x0000) | ((ibss) ? 0x0002 : 0x0000) | ((priv) ? 0x0010 : 0x0000) | ((s_pre) ? 0x0020 : 0x0000) | ((s_slot) ? 0x0400 : 0x0000) | ((spectrum) ? 0x0100 : 0x0000))
-
-#define ERP_IS_NON_ERP_PRESENT(x) (((x) & 0x01) != 0) /* 802.11g */
-#define ERP_IS_USE_PROTECTION(x) (((x) & 0x02) != 0) /* 802.11g */
-#define ERP_IS_USE_BARKER_PREAMBLE(x) (((x) & 0x04) != 0) /* 802.11g */
-
-#define DRS_TX_QUALITY_WORST_BOUND 8 /* 3 // just test by gary */
-#define DRS_PENALTY 8
-
-#define BA_NOTUSE 2
-/*BA Policy subfiled value in ADDBA frame */
-#define IMMED_BA 1
-#define DELAY_BA 0
-
-/* BA Initiator subfield in DELBA frame */
-#define ORIGINATOR 1
-#define RECIPIENT 0
-
-/* ADDBA Status Code */
-#define ADDBA_RESULTCODE_SUCCESS 0
-#define ADDBA_RESULTCODE_REFUSED 37
-#define ADDBA_RESULTCODE_INVALID_PARAMETERS 38
-
-/* DELBA Reason Code */
-#define DELBA_REASONCODE_QSTA_LEAVING 36
-#define DELBA_REASONCODE_END_BA 37
-#define DELBA_REASONCODE_UNKNOWN_BA 38
-#define DELBA_REASONCODE_TIMEOUT 39
-
-/* reset all OneSecTx counters */
-#define RESET_ONE_SEC_TX_CNT(__pEntry) \
-if (((__pEntry)) != NULL) { \
- (__pEntry)->OneSecTxRetryOkCount = 0; \
- (__pEntry)->OneSecTxFailCount = 0; \
- (__pEntry)->OneSecTxNoRetryOkCount = 0; \
-}
-
-/* */
-/* 802.11 frame formats */
-/* */
-/* HT Capability INFO field in HT Cap IE . */
-struct PACKED rt_ht_cap_info {
- u16 AdvCoding:1;
- u16 ChannelWidth:1;
- u16 MimoPs:2; /*momi power safe */
- u16 GF:1; /*green field */
- u16 ShortGIfor20:1;
- u16 ShortGIfor40:1; /*for40MHz */
- u16 TxSTBC:1;
- u16 RxSTBC:2;
- u16 DelayedBA:1; /*rt2860c not support */
- u16 AMsduSize:1; /* only support as zero */
- u16 CCKmodein40:1;
- u16 PSMP:1;
- u16 Forty_Mhz_Intolerant:1;
- u16 LSIGTxopProSup:1;
-};
-
-/* HT Capability INFO field in HT Cap IE . */
-struct PACKED rt_ht_cap_parm {
- u8 MaxRAmpduFactor:2;
- u8 MpduDensity:3;
- u8 rsv:3; /*momi power safe */
-};
-
-/* HT Capability INFO field in HT Cap IE . */
-struct PACKED rt_ht_mcs_set {
- u8 MCSSet[10];
- u8 SupRate[2]; /* unit : 1Mbps */
- u8 TxMCSSetDefined:1;
- u8 TxRxNotEqual:1;
- u8 TxStream:2;
- u8 MpduDensity:1;
- u8 rsv:3;
- u8 rsv3[3];
-};
-
-/* HT Capability INFO field in HT Cap IE . */
-struct PACKED rt_ext_ht_cap_info {
- u16 Pco:1;
- u16 TranTime:2;
- u16 rsv:5; /*momi power safe */
- u16 MCSFeedback:2; /*0:no MCS feedback, 2:unsolicited MCS feedback, 3:Full MCS feedback, 1:rsv. */
- u16 PlusHTC:1; /*+HTC control field support */
- u16 RDGSupport:1; /*reverse Direction Grant support */
- u16 rsv2:4;
-};
-
-/* HT Beamforming field in HT Cap IE . */
-struct PACKED rt_ht_bf_cap {
- unsigned long TxBFRecCapable:1;
- unsigned long RxSoundCapable:1;
- unsigned long TxSoundCapable:1;
- unsigned long RxNDPCapable:1;
- unsigned long TxNDPCapable:1;
- unsigned long ImpTxBFCapable:1;
- unsigned long Calibration:2;
- unsigned long ExpCSICapable:1;
- unsigned long ExpNoComSteerCapable:1;
- unsigned long ExpComSteerCapable:1;
- unsigned long ExpCSIFbk:2;
- unsigned long ExpNoComBF:2;
- unsigned long ExpComBF:2;
- unsigned long MinGrouping:2;
- unsigned long CSIBFAntSup:2;
- unsigned long NoComSteerBFAntSup:2;
- unsigned long ComSteerBFAntSup:2;
- unsigned long CSIRowBFSup:2;
- unsigned long ChanEstimation:2;
- unsigned long rsv:3;
-};
-
-/* HT antenna selection field in HT Cap IE . */
-struct PACKED rt_ht_as_cap {
- u8 AntSelect:1;
- u8 ExpCSIFbkTxASEL:1;
- u8 AntIndFbkTxASEL:1;
- u8 ExpCSIFbk:1;
- u8 AntIndFbk:1;
- u8 RxASel:1;
- u8 TxSoundPPDU:1;
- u8 rsv:1;
-};
-
-/* Draft 1.0 set IE length 26, but is extensible.. */
-#define SIZE_HT_CAP_IE 26
-/* The structure for HT Capability IE. */
-struct PACKED rt_ht_capability_ie {
- struct rt_ht_cap_info HtCapInfo;
- struct rt_ht_cap_parm HtCapParm;
-/* struct rt_ht_mcs_set HtMCSSet; */
- u8 MCSSet[16];
- struct rt_ext_ht_cap_info ExtHtCapInfo;
- struct rt_ht_bf_cap TxBFCap; /* beamforming cap. rt2860c not support beamforming. */
- struct rt_ht_as_cap ASCap; /*antenna selection. */
-};
-
-/* 802.11n draft3 related structure definitions. */
-/* 7.3.2.60 */
-#define dot11OBSSScanPassiveDwell 20 /* in TU. min amount of time that the STA continuously scans each channel when performing an active OBSS scan. */
-#define dot11OBSSScanActiveDwell 10 /* in TU.min amount of time that the STA continuously scans each channel when performing an passive OBSS scan. */
-#define dot11BSSWidthTriggerScanInterval 300 /* in sec. max interval between scan operations to be performed to detect BSS channel width trigger events. */
-#define dot11OBSSScanPassiveTotalPerChannel 200 /* in TU. min total amount of time that the STA scans each channel when performing a passive OBSS scan. */
-#define dot11OBSSScanActiveTotalPerChannel 20 /*in TU. min total amount of time that the STA scans each channel when performing a active OBSS scan */
-#define dot11BSSWidthChannelTransactionDelayFactor 5 /* min ratio between the delay time in performing a switch from 20MHz BSS to 20/40 BSS operation and the maximum */
- /* interval between overlapping BSS scan operations. */
-#define dot11BSSScanActivityThreshold 25 /* in %%, max total time that a STA may be active on the medium during a period of */
- /* (dot11BSSWidthChannelTransactionDelayFactor * dot11BSSWidthTriggerScanInterval) seconds without */
- /* being obligated to perform OBSS Scan operations. default is 25(== 0.25%) */
-
-struct PACKED rt_overlap_bss_scan_ie {
- u16 ScanPassiveDwell;
- u16 ScanActiveDwell;
- u16 TriggerScanInt; /* Trigger scan interval */
- u16 PassiveTalPerChannel; /* passive total per channel */
- u16 ActiveTalPerChannel; /* active total per channel */
- u16 DelayFactor; /* BSS width channel transition delay factor */
- u16 ScanActThre; /* Scan Activity threshold */
-};
-
-/* 7.3.2.56. 20/40 Coexistence element used in Element ID = 72 = IE_2040_BSS_COEXIST */
-typedef union PACKED _BSS_2040_COEXIST_IE {
- struct PACKED {
- u8 InfoReq:1;
- u8 Intolerant40:1; /* Inter-BSS. set 1 when prohibits a receiving BSS from operating as a 20/40 Mhz BSS. */
- u8 BSS20WidthReq:1; /* Intra-BSS set 1 when prohibits a receiving AP from operating its BSS as a 20/40MHz BSS. */
- u8 rsv:5;
- } field;
- u8 word;
-} BSS_2040_COEXIST_IE, *PBSS_2040_COEXIST_IE;
-
-struct rt_trigger_eventa {
- BOOLEAN bValid;
- u8 BSSID[6];
- u8 RegClass; /* Regulatory Class */
- u16 Channel;
- unsigned long CDCounter; /* Maintain a separate count down counter for each Event A. */
-};
-
-/* 20/40 trigger event table */
-/* If one Event (A) is deleted or created, or if Event (B) is detected or not detected, STA should send 2040BSSCoexistence to AP. */
-#define MAX_TRIGGER_EVENT 64
-struct rt_trigger_event_tab {
- u8 EventANo;
- struct rt_trigger_eventa EventA[MAX_TRIGGER_EVENT];
- unsigned long EventBCountDown; /* Count down counter for Event B. */
-};
-
-/* 7.3.27 20/40 Bss Coexistence Mgmt capability used in extended capabilities information IE( ID = 127 = IE_EXT_CAPABILITY). */
-/* This is the first octet and was defined in 802.11n D3.03 and 802.11yD9.0 */
-struct PACKED rt_ext_cap_info_element {
- u8 BssCoexistMgmtSupport:1;
- u8 rsv:1;
- u8 ExtendChannelSwitch:1;
- u8 rsv2:5;
-};
-
-/* 802.11n 7.3.2.61 */
-struct PACKED rt_bss_2040_coexist_element {
- u8 ElementID; /* ID = IE_2040_BSS_COEXIST = 72 */
- u8 Len;
- BSS_2040_COEXIST_IE BssCoexistIe;
-};
-
-/*802.11n 7.3.2.59 */
-struct PACKED rt_bss_2040_intolerant_ch_report {
- u8 ElementID; /* ID = IE_2040_BSS_INTOLERANT_REPORT = 73 */
- u8 Len;
- u8 RegulatoryClass;
- u8 ChList[0];
-};
-
-/* The structure for channel switch announcement IE. This is in 802.11n D3.03 */
-struct PACKED rt_cha_switch_announce_ie {
- u8 SwitchMode; /*channel switch mode */
- u8 NewChannel; /* */
- u8 SwitchCount; /* */
-};
-
-/* The structure for channel switch announcement IE. This is in 802.11n D3.03 */
-struct PACKED rt_sec_cha_offset_ie {
- u8 SecondaryChannelOffset; /* 1: Secondary above, 3: Secondary below, 0: no Secondary */
-};
-
-/* This structure is extracted from struct struct rt_ht_capability */
-struct rt_ht_phy_info {
- BOOLEAN bHtEnable; /* If we should use ht rate. */
- BOOLEAN bPreNHt; /* If we should use ht rate. */
- /*Subtract from HT Capability IE */
- u8 MCSSet[16];
-};
-
-/*This structure subtracts ralink supports from all 802.11n-related features. */
-/*Features not listed here but contained in 802.11n spec are not supported in rt2860. */
-struct rt_ht_capability {
- u16 ChannelWidth:1;
- u16 MimoPs:2; /*mimo power safe MMPS_ */
- u16 GF:1; /*green field */
- u16 ShortGIfor20:1;
- u16 ShortGIfor40:1; /*for40MHz */
- u16 TxSTBC:1;
- u16 RxSTBC:2; /* 2 bits */
- u16 AmsduEnable:1; /* Enable to transmit A-MSDU. Suggest disable. We should use A-MPDU to gain best benefit of 802.11n */
- u16 AmsduSize:1; /* Max receiving A-MSDU size */
- u16 rsv:5;
-
- /*Subtract from Addiont HT INFO IE */
- u8 MaxRAmpduFactor:2;
- u8 MpduDensity:3;
- u8 ExtChanOffset:2; /* Please note the difference with following u8 NewExtChannelOffset; from 802.11n */
- u8 RecomWidth:1;
-
- u16 OperaionMode:2;
- u16 NonGfPresent:1;
- u16 rsv3:1;
- u16 OBSS_NonHTExist:1;
- u16 rsv2:11;
-
- /* New Extension Channel Offset IE */
- u8 NewExtChannelOffset;
- /* Extension Capability IE = 127 */
- u8 BSSCoexist2040;
-};
-
-/* field in Additional HT Information IE . */
-struct PACKED rt_add_htinfo {
- u8 ExtChanOffset:2;
- u8 RecomWidth:1;
- u8 RifsMode:1;
- u8 S_PSMPSup:1; /*Indicate support for scheduled PSMP */
- u8 SerInterGranu:3; /*service interval granularity */
-};
-
-struct PACKED rt_add_htinfo2 {
- u16 OperaionMode:2;
- u16 NonGfPresent:1;
- u16 rsv:1;
- u16 OBSS_NonHTExist:1;
- u16 rsv2:11;
-};
-
-/* TODO: Need sync with spec about the definition of StbcMcs. In Draft 3.03, it's reserved. */
-struct PACKED rt_add_htinfo3 {
- u16 StbcMcs:6;
- u16 DualBeacon:1;
- u16 DualCTSProtect:1;
- u16 STBCBeacon:1;
- u16 LsigTxopProt:1; /* L-SIG TXOP protection full support */
- u16 PcoActive:1;
- u16 PcoPhase:1;
- u16 rsv:4;
-};
-
-#define SIZE_ADD_HT_INFO_IE 22
-struct PACKED rt_add_ht_info_ie {
- u8 ControlChan;
- struct rt_add_htinfo AddHtInfo;
- struct rt_add_htinfo2 AddHtInfo2;
- struct rt_add_htinfo3 AddHtInfo3;
- u8 MCSSet[16]; /* Basic MCS set */
-};
-
-struct PACKED rt_new_ext_chan_ie {
- u8 NewExtChanOffset;
-};
-
-struct PACKED rt_frame_802_11 {
- struct rt_header_802_11 Hdr;
- u8 Octet[1];
-};
-
-/* QoSNull embedding of management action. When HT Control MA field set to 1. */
-struct PACKED rt_ma_body {
- u8 Category;
- u8 Action;
- u8 Octet[1];
-};
-
-struct PACKED rt_header_802_3 {
- u8 DAAddr1[MAC_ADDR_LEN];
- u8 SAAddr2[MAC_ADDR_LEN];
- u8 Octet[2];
-};
-/*//Block ACK related format */
-/* 2-byte BA Parameter field in DELBA frames to terminate an already set up bA */
-struct PACKED rt_delba_parm {
- u16 Rsv:11; /* always set to 0 */
- u16 Initiator:1; /* 1: originator 0:recipient */
- u16 TID:4; /* value of TC os TS */
-};
-
-/* 2-byte BA Parameter Set field in ADDBA frames to signal parm for setting up a BA */
-struct PACKED rt_ba_parm {
- u16 AMSDUSupported:1; /* 0: not permitted 1: permitted */
- u16 BAPolicy:1; /* 1: immediately BA 0:delayed BA */
- u16 TID:4; /* value of TC os TS */
- u16 BufSize:10; /* number of buffer of size 2304 octetsr */
-};
-
-/* 2-byte BA Starting Seq CONTROL field */
-typedef union PACKED _BASEQ_CONTROL {
- struct PACKED {
- u16 FragNum:4; /* always set to 0 */
- u16 StartSeq:12; /* sequence number of the 1st MSDU for which this BAR is sent */
- } field;
- u16 word;
-} BASEQ_CONTROL, *PBASEQ_CONTROL;
-
-/*BAControl and BARControl are the same */
-/* 2-byte BA CONTROL field in BA frame */
-struct PACKED rt_ba_control {
- u16 ACKPolicy:1; /* only related to N-Delayed BA. But not support in RT2860b. 0:NormalACK 1:No ACK */
- u16 MTID:1; /*EWC V1.24 */
- u16 Compressed:1;
- u16 Rsv:9;
- u16 TID:4;
-};
-
-/* 2-byte BAR CONTROL field in BAR frame */
-struct PACKED rt_bar_control {
- u16 ACKPolicy:1; /* 0:normal ack, 1:no ack. */
- u16 MTID:1; /*if this bit1, use struct rt_frame_mtba_req, if 0, use struct rt_frame_ba_req */
- u16 Compressed:1;
- u16 Rsv1:9;
- u16 TID:4;
-};
-
-/* BARControl in MTBAR frame */
-struct PACKED rt_mtbar_control {
- u16 ACKPolicy:1;
- u16 MTID:1;
- u16 Compressed:1;
- u16 Rsv1:9;
- u16 NumTID:4;
-};
-
-struct PACKED rt_per_tid_info {
- u16 Rsv1:12;
- u16 TID:4;
-};
-
-struct rt_each_tid {
- struct rt_per_tid_info PerTID;
- BASEQ_CONTROL BAStartingSeq;
-};
-
-/* BAREQ AND MTBAREQ have the same subtype BAR, 802.11n BAR use compressed bitmap. */
-struct PACKED rt_frame_ba_req {
- struct rt_frame_control FC;
- u16 Duration;
- u8 Addr1[MAC_ADDR_LEN];
- u8 Addr2[MAC_ADDR_LEN];
- struct rt_bar_control BARControl;
- BASEQ_CONTROL BAStartingSeq;
-};
-
-struct PACKED rt_frame_mtba_req {
- struct rt_frame_control FC;
- u16 Duration;
- u8 Addr1[MAC_ADDR_LEN];
- u8 Addr2[MAC_ADDR_LEN];
- struct rt_mtbar_control MTBARControl;
- struct rt_per_tid_info PerTIDInfo;
- BASEQ_CONTROL BAStartingSeq;
-};
-
-/* Compressed format is mandatory in HT STA */
-struct PACKED rt_frame_mtba {
- struct rt_frame_control FC;
- u16 Duration;
- u8 Addr1[MAC_ADDR_LEN];
- u8 Addr2[MAC_ADDR_LEN];
- struct rt_ba_control BAControl;
- BASEQ_CONTROL BAStartingSeq;
- u8 BitMap[8];
-};
-
-struct PACKED rt_frame_psmp_action {
- struct rt_header_802_11 Hdr;
- u8 Category;
- u8 Action;
- u8 Psmp; /* 7.3.1.25 */
-};
-
-struct PACKED rt_frame_action_hdr {
- struct rt_header_802_11 Hdr;
- u8 Category;
- u8 Action;
-};
-
-/*Action Frame */
-/*Action Frame Category:Spectrum, Action:Channel Switch. 7.3.2.20 */
-struct PACKED rt_chan_switch_announce {
- u8 ElementID; /* ID = IE_CHANNEL_SWITCH_ANNOUNCEMENT = 37 */
- u8 Len;
- struct rt_cha_switch_announce_ie CSAnnounceIe;
-};
-
-/*802.11n : 7.3.2.20a */
-struct PACKED rt_second_chan_offset {
- u8 ElementID; /* ID = IE_SECONDARY_CH_OFFSET = 62 */
- u8 Len;
- struct rt_sec_cha_offset_ie SecChOffsetIe;
-};
-
-struct PACKED rt_frame_spetrum_cs {
- struct rt_header_802_11 Hdr;
- u8 Category;
- u8 Action;
- struct rt_chan_switch_announce CSAnnounce;
- struct rt_second_chan_offset SecondChannel;
-};
-
-struct PACKED rt_frame_addba_req {
- struct rt_header_802_11 Hdr;
- u8 Category;
- u8 Action;
- u8 Token; /* 1 */
- struct rt_ba_parm BaParm; /* 2 - 10 */
- u16 TimeOutValue; /* 0 - 0 */
- BASEQ_CONTROL BaStartSeq; /* 0-0 */
-};
-
-struct PACKED rt_frame_addba_rsp {
- struct rt_header_802_11 Hdr;
- u8 Category;
- u8 Action;
- u8 Token;
- u16 StatusCode;
- struct rt_ba_parm BaParm; /*0 - 2 */
- u16 TimeOutValue;
-};
-
-struct PACKED rt_frame_delba_req {
- struct rt_header_802_11 Hdr;
- u8 Category;
- u8 Action;
- struct rt_delba_parm DelbaParm;
- u16 ReasonCode;
-};
-
-/*7.2.1.7 */
-struct PACKED rt_frame_bar {
- struct rt_frame_control FC;
- u16 Duration;
- u8 Addr1[MAC_ADDR_LEN];
- u8 Addr2[MAC_ADDR_LEN];
- struct rt_bar_control BarControl;
- BASEQ_CONTROL StartingSeq;
-};
-
-/*7.2.1.7 */
-struct PACKED rt_frame_ba {
- struct rt_frame_control FC;
- u16 Duration;
- u8 Addr1[MAC_ADDR_LEN];
- u8 Addr2[MAC_ADDR_LEN];
- struct rt_bar_control BarControl;
- BASEQ_CONTROL StartingSeq;
- u8 bitmask[8];
-};
-
-/* Radio Measurement Request Frame Format */
-struct PACKED rt_frame_rm_req_action {
- struct rt_header_802_11 Hdr;
- u8 Category;
- u8 Action;
- u8 Token;
- u16 Repetition;
- u8 data[0];
-};
-
-struct PACKED rt_ht_ext_channel_switch_announcement_ie {
- u8 ID;
- u8 Length;
- u8 ChannelSwitchMode;
- u8 NewRegClass;
- u8 NewChannelNum;
- u8 ChannelSwitchCount;
-};
-
-/* */
-/* _Limit must be the 2**n - 1 */
-/* _SEQ1 , _SEQ2 must be within 0 ~ _Limit */
-/* */
-#define SEQ_STEPONE(_SEQ1, _SEQ2, _Limit) ((_SEQ1 == ((_SEQ2+1) & _Limit)))
-#define SEQ_SMALLER(_SEQ1, _SEQ2, _Limit) (((_SEQ1-_SEQ2) & ((_Limit+1)>>1)))
-#define SEQ_LARGER(_SEQ1, _SEQ2, _Limit) ((_SEQ1 != _SEQ2) && !(((_SEQ1-_SEQ2) & ((_Limit+1)>>1))))
-#define SEQ_WITHIN_WIN(_SEQ1, _SEQ2, _WIN, _Limit) (SEQ_LARGER(_SEQ1, _SEQ2, _Limit) && \
- SEQ_SMALLER(_SEQ1, ((_SEQ2+_WIN+1)&_Limit), _Limit))
-
-/* */
-/* Contention-free parameter (without ID and Length) */
-/* */
-struct PACKED rt_cf_parm {
- BOOLEAN bValid; /* 1: variable contains valid value */
- u8 CfpCount;
- u8 CfpPeriod;
- u16 CfpMaxDuration;
- u16 CfpDurRemaining;
-};
-
-struct rt_cipher_suite {
- NDIS_802_11_ENCRYPTION_STATUS PairCipher; /* Unicast cipher 1, this one has more secured cipher suite */
- NDIS_802_11_ENCRYPTION_STATUS PairCipherAux; /* Unicast cipher 2 if AP announce two unicast cipher suite */
- NDIS_802_11_ENCRYPTION_STATUS GroupCipher; /* Group cipher */
- u16 RsnCapability; /* RSN capability from beacon */
- BOOLEAN bMixMode; /* Indicate Pair & Group cipher might be different */
-};
-
-/* EDCA configuration from AP's BEACON/ProbeRsp */
-struct rt_edca_parm {
- BOOLEAN bValid; /* 1: variable contains valid value */
- BOOLEAN bAdd; /* 1: variable contains valid value */
- BOOLEAN bQAck;
- BOOLEAN bQueueRequest;
- BOOLEAN bTxopRequest;
- BOOLEAN bAPSDCapable;
-/* BOOLEAN bMoreDataAck; */
- u8 EdcaUpdateCount;
- u8 Aifsn[4]; /* 0:AC_BK, 1:AC_BE, 2:AC_VI, 3:AC_VO */
- u8 Cwmin[4];
- u8 Cwmax[4];
- u16 Txop[4]; /* in unit of 32-us */
- BOOLEAN bACM[4]; /* 1: Admission Control of AC_BK is mandatory */
-};
-
-/* QBSS LOAD information from QAP's BEACON/ProbeRsp */
-struct rt_qbss_load_parm {
- BOOLEAN bValid; /* 1: variable contains valid value */
- u16 StaNum;
- u8 ChannelUtilization;
- u16 RemainingAdmissionControl; /* in unit of 32-us */
-};
-
-/* QBSS Info field in QSTA's assoc req */
-struct PACKED rt_qbss_sta_info_parm {
- u8 UAPSD_AC_VO:1;
- u8 UAPSD_AC_VI:1;
- u8 UAPSD_AC_BK:1;
- u8 UAPSD_AC_BE:1;
- u8 Rsv1:1;
- u8 MaxSPLength:2;
- u8 Rsv2:1;
-};
-
-/* QBSS Info field in QAP's Beacon/ProbeRsp */
-struct PACKED rt_qbss_ap_info_parm {
- u8 ParamSetCount:4;
- u8 Rsv:3;
- u8 UAPSD:1;
-};
-
-/* QOS Capability reported in QAP's BEACON/ProbeRsp */
-/* QOS Capability sent out in QSTA's AssociateReq/ReAssociateReq */
-struct rt_qos_capability_parm {
- BOOLEAN bValid; /* 1: variable contains valid value */
- BOOLEAN bQAck;
- BOOLEAN bQueueRequest;
- BOOLEAN bTxopRequest;
-/* BOOLEAN bMoreDataAck; */
- u8 EdcaUpdateCount;
-};
-
-struct rt_wpa_ie {
- u8 IELen;
- u8 IE[MAX_CUSTOM_LEN];
-};
-
-struct rt_bss_entry {
- u8 Bssid[MAC_ADDR_LEN];
- u8 Channel;
- u8 CentralChannel; /*Store the wide-band central channel for 40MHz. used in 40MHz AP. Or this is the same as Channel. */
- u8 BssType;
- u16 AtimWin;
- u16 BeaconPeriod;
-
- u8 SupRate[MAX_LEN_OF_SUPPORTED_RATES];
- u8 SupRateLen;
- u8 ExtRate[MAX_LEN_OF_SUPPORTED_RATES];
- u8 ExtRateLen;
- struct rt_ht_capability_ie HtCapability;
- u8 HtCapabilityLen;
- struct rt_add_ht_info_ie AddHtInfo; /* AP might use this additional ht info IE */
- u8 AddHtInfoLen;
- u8 NewExtChanOffset;
- char Rssi;
- u8 Privacy; /* Indicate security function ON/OFF. Don't mess up with auth mode. */
- u8 Hidden;
-
- u16 DtimPeriod;
- u16 CapabilityInfo;
-
- u16 CfpCount;
- u16 CfpPeriod;
- u16 CfpMaxDuration;
- u16 CfpDurRemaining;
- u8 SsidLen;
- char Ssid[MAX_LEN_OF_SSID];
-
- unsigned long LastBeaconRxTime; /* OS's timestamp */
-
- BOOLEAN bSES;
-
- /* New for WPA2 */
- struct rt_cipher_suite WPA; /* AP announced WPA cipher suite */
- struct rt_cipher_suite WPA2; /* AP announced WPA2 cipher suite */
-
- /* New for microsoft WPA support */
- struct rt_ndis_802_11_fixed_ies FixIEs;
- NDIS_802_11_AUTHENTICATION_MODE AuthModeAux; /* Addition mode for WPA2 / WPA capable AP */
- NDIS_802_11_AUTHENTICATION_MODE AuthMode;
- NDIS_802_11_WEP_STATUS WepStatus; /* Unicast Encryption Algorithm extract from VAR_IE */
- u16 VarIELen; /* Length of next VIE include EID & Length */
- u8 VarIEs[MAX_VIE_LEN];
-
- /* CCX Ckip information */
- u8 CkipFlag;
-
- /* CCX 2 TSF */
- u8 PTSF[4]; /* Parent TSF */
- u8 TTSF[8]; /* Target TSF */
-
- /* 802.11e d9, and WMM */
- struct rt_edca_parm EdcaParm;
- struct rt_qos_capability_parm QosCapability;
- struct rt_qbss_load_parm QbssLoad;
- struct rt_wpa_ie WpaIE;
- struct rt_wpa_ie RsnIE;
-};
-
-struct rt_bss_table {
- u8 BssNr;
- u8 BssOverlapNr;
- struct rt_bss_entry BssEntry[MAX_LEN_OF_BSS_TABLE];
-};
-
-struct rt_mlme_queue_elem {
- unsigned long Machine;
- unsigned long MsgType;
- unsigned long MsgLen;
- u8 Msg[MGMT_DMA_BUFFER_SIZE];
- LARGE_INTEGER TimeStamp;
- u8 Rssi0;
- u8 Rssi1;
- u8 Rssi2;
- u8 Signal;
- u8 Channel;
- u8 Wcid;
- BOOLEAN Occupied;
-};
-
-struct rt_mlme_queue {
- unsigned long Num;
- unsigned long Head;
- unsigned long Tail;
- spinlock_t Lock;
- struct rt_mlme_queue_elem Entry[MAX_LEN_OF_MLME_QUEUE];
-};
-
-typedef void(*STATE_MACHINE_FUNC) (void *Adaptor, struct rt_mlme_queue_elem *Elem);
-
-struct rt_state_machine {
- unsigned long Base;
- unsigned long NrState;
- unsigned long NrMsg;
- unsigned long CurrState;
- STATE_MACHINE_FUNC *TransFunc;
-};
-
-/* MLME AUX data structure that holds temporarliy settings during a connection attempt. */
-/* Once this attempt succeeds, all settings will be copy to pAd->StaActive. */
-/* A connection attempt (user set OID, roaming, CCX fast roaming,..) consists of */
-/* several steps (JOIN, AUTH, ASSOC or REASSOC) and may fail at any step. We purposely */
-/* separate this under-trial settings away from pAd->StaActive so that once */
-/* this new attempt failed, driver can auto-recover back to the active settings. */
-struct rt_mlme_aux {
- u8 BssType;
- u8 Ssid[MAX_LEN_OF_SSID];
- u8 SsidLen;
- u8 Bssid[MAC_ADDR_LEN];
- u8 AutoReconnectSsid[MAX_LEN_OF_SSID];
- u8 AutoReconnectSsidLen;
- u16 Alg;
- u8 ScanType;
- u8 Channel;
- u8 CentralChannel;
- u16 Aid;
- u16 CapabilityInfo;
- u16 BeaconPeriod;
- u16 CfpMaxDuration;
- u16 CfpPeriod;
- u16 AtimWin;
-
- /* Copy supported rate from desired AP's beacon. We are trying to match */
- /* AP's supported and extended rate settings. */
- u8 SupRate[MAX_LEN_OF_SUPPORTED_RATES];
- u8 ExtRate[MAX_LEN_OF_SUPPORTED_RATES];
- u8 SupRateLen;
- u8 ExtRateLen;
- struct rt_ht_capability_ie HtCapability;
- u8 HtCapabilityLen;
- struct rt_add_ht_info_ie AddHtInfo; /* AP might use this additional ht info IE */
- u8 NewExtChannelOffset;
- /*struct rt_ht_capability SupportedHtPhy; */
-
- /* new for QOS */
- struct rt_qos_capability_parm APQosCapability; /* QOS capability of the current associated AP */
- struct rt_edca_parm APEdcaParm; /* EDCA parameters of the current associated AP */
- struct rt_qbss_load_parm APQbssLoad; /* QBSS load of the current associated AP */
-
- /* new to keep Ralink specific feature */
- unsigned long APRalinkIe;
-
- struct rt_bss_table SsidBssTab; /* AP list for the same SSID */
- struct rt_bss_table RoamTab; /* AP list eligible for roaming */
- unsigned long BssIdx;
- unsigned long RoamIdx;
-
- BOOLEAN CurrReqIsFromNdis;
-
- struct rt_ralink_timer BeaconTimer, ScanTimer;
- struct rt_ralink_timer AuthTimer;
- struct rt_ralink_timer AssocTimer, ReassocTimer, DisassocTimer;
-};
-
-struct rt_mlme_addba_req {
- u8 Wcid; /* */
- u8 pAddr[MAC_ADDR_LEN];
- u8 BaBufSize;
- u16 TimeOutValue;
- u8 TID;
- u8 Token;
- u16 BaStartSeq;
-};
-
-struct rt_mlme_delba_req {
- u8 Wcid; /* */
- u8 Addr[MAC_ADDR_LEN];
- u8 TID;
- u8 Initiator;
-};
-
-/* assoc struct is equal to reassoc */
-struct rt_mlme_assoc_req {
- u8 Addr[MAC_ADDR_LEN];
- u16 CapabilityInfo;
- u16 ListenIntv;
- unsigned long Timeout;
-};
-
-struct rt_mlme_disassoc_req {
- u8 Addr[MAC_ADDR_LEN];
- u16 Reason;
-};
-
-struct rt_mlme_auth_req {
- u8 Addr[MAC_ADDR_LEN];
- u16 Alg;
- unsigned long Timeout;
-};
-
-struct rt_mlme_deauth_req {
- u8 Addr[MAC_ADDR_LEN];
- u16 Reason;
-};
-
-struct rt_mlme_join_req {
- unsigned long BssIdx;
-};
-
-struct rt_mlme_scan_req {
- u8 Bssid[MAC_ADDR_LEN];
- u8 BssType;
- u8 ScanType;
- u8 SsidLen;
- char Ssid[MAX_LEN_OF_SSID];
-};
-
-struct rt_mlme_start_req {
- char Ssid[MAX_LEN_OF_SSID];
- u8 SsidLen;
-};
-
-struct PACKED rt_eid {
- u8 Eid;
- u8 Len;
- u8 Octet[1];
-};
-
-struct PACKED rt_rtmp_tx_rate_switch {
- u8 ItemNo;
- u8 STBC:1;
- u8 ShortGI:1;
- u8 BW:1;
- u8 Rsv1:1;
- u8 Mode:2;
- u8 Rsv2:2;
- u8 CurrMCS;
- u8 TrainUp;
- u8 TrainDown;
-};
-
-/* ========================== AP mlme.h =============================== */
-#define TBTT_PRELOAD_TIME 384 /* usec. LomgPreamble + 24-byte at 1Mbps */
-#define DEFAULT_DTIM_PERIOD 1
-
-#define MAC_TABLE_AGEOUT_TIME 300 /* unit: sec */
-#define MAC_TABLE_ASSOC_TIMEOUT 5 /* unit: sec */
-#define MAC_TABLE_FULL(Tab) ((Tab).size == MAX_LEN_OF_MAC_TABLE)
-
-/* AP shall drop the sta if continue Tx fail count reach it. */
-#define MAC_ENTRY_LIFE_CHECK_CNT 20 /* packet cnt. */
-
-/* Value domain of pMacEntry->Sst */
-typedef enum _Sst {
- SST_NOT_AUTH, /* 0: equivalent to IEEE 802.11/1999 state 1 */
- SST_AUTH, /* 1: equivalent to IEEE 802.11/1999 state 2 */
- SST_ASSOC /* 2: equivalent to IEEE 802.11/1999 state 3 */
-} SST;
-
-/* value domain of pMacEntry->AuthState */
-typedef enum _AuthState {
- AS_NOT_AUTH,
- AS_AUTH_OPEN, /* STA has been authenticated using OPEN SYSTEM */
- AS_AUTH_KEY, /* STA has been authenticated using SHARED KEY */
- AS_AUTHENTICATING /* STA is waiting for AUTH seq#3 using SHARED KEY */
-} AUTH_STATE;
-
-/*for-wpa value domain of pMacEntry->WpaState 802.1i D3 p.114 */
-typedef enum _ApWpaState {
- AS_NOTUSE, /* 0 */
- AS_DISCONNECT, /* 1 */
- AS_DISCONNECTED, /* 2 */
- AS_INITIALIZE, /* 3 */
- AS_AUTHENTICATION, /* 4 */
- AS_AUTHENTICATION2, /* 5 */
- AS_INITPMK, /* 6 */
- AS_INITPSK, /* 7 */
- AS_PTKSTART, /* 8 */
- AS_PTKINIT_NEGOTIATING, /* 9 */
- AS_PTKINITDONE, /* 10 */
- AS_UPDATEKEYS, /* 11 */
- AS_INTEGRITY_FAILURE, /* 12 */
- AS_KEYUPDATE, /* 13 */
-} AP_WPA_STATE;
-
-/* for-wpa value domain of pMacEntry->WpaState 802.1i D3 p.114 */
-typedef enum _GTKState {
- REKEY_NEGOTIATING,
- REKEY_ESTABLISHED,
- KEYERROR,
-} GTK_STATE;
-
-/* for-wpa value domain of pMacEntry->WpaState 802.1i D3 p.114 */
-typedef enum _WpaGTKState {
- SETKEYS,
- SETKEYS_DONE,
-} WPA_GTK_STATE;
-/* ====================== end of AP mlme.h ============================ */
-
-#endif /* MLME_H__ */
diff --git a/drivers/staging/rt2860/oid.h b/drivers/staging/rt2860/oid.h
deleted file mode 100644
index 5a25f0d..0000000
--- a/drivers/staging/rt2860/oid.h
+++ /dev/null
@@ -1,779 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- oid.h
-
- Abstract:
-
- Revision History:
- Who When What
- -------- ---------- ----------------------------------------------
- Name Date Modification logs
- Justin P. Mattock 11/07/2010 Fix typos in comments
-*/
-#ifndef _OID_H_
-#define _OID_H_
-
-/*#include <linux/wireless.h> */
-
-#ifndef TRUE
-#define TRUE 1
-#endif
-#ifndef FALSE
-#define FALSE 0
-#endif
-/* */
-/* IEEE 802.11 Structures and definitions */
-/* */
-#define MAX_TX_POWER_LEVEL 100 /* mW */
-#define MAX_RSSI_TRIGGER -10 /* dBm */
-#define MIN_RSSI_TRIGGER -200 /* dBm */
-#define MAX_FRAG_THRESHOLD 2346 /* byte count */
-#define MIN_FRAG_THRESHOLD 256 /* byte count */
-#define MAX_RTS_THRESHOLD 2347 /* byte count */
-
-/* new types for Media Specific Indications */
-/* Extension channel offset */
-#define EXTCHA_NONE 0
-#define EXTCHA_ABOVE 0x1
-#define EXTCHA_BELOW 0x3
-
-/* BW */
-#define BAND_WIDTH_20 0
-#define BAND_WIDTH_40 1
-#define BAND_WIDTH_BOTH 2
-#define BAND_WIDTH_10 3 /* 802.11j has 10MHz. This definition is for internal usage. doesn't fill in the IE or other field. */
-/* SHORTGI */
-#define GAP_INTERVAL_400 1 /* only support in HT mode */
-#define GAP_INTERVAL_800 0
-#define GAP_INTERVAL_BOTH 2
-
-#define NdisMediaStateConnected 1
-#define NdisMediaStateDisconnected 0
-
-#define NDIS_802_11_LENGTH_SSID 32
-#define NDIS_802_11_LENGTH_RATES 8
-#define NDIS_802_11_LENGTH_RATES_EX 16
-#define MAC_ADDR_LENGTH 6
-/*#define MAX_NUM_OF_CHS 49 // 14 channels @2.4G + 12@UNII + 4 @MMAC + 11 @HiperLAN2 + 7 @Japan + 1 as NULL termination */
-#define MAX_NUM_OF_CHS 54 /* 14 channels @2.4G + 12@UNII(lower/middle) + 16@HiperLAN2 + 11@UNII(upper) + 0 @Japan + 1 as NULL termination */
-#define MAX_NUMBER_OF_EVENT 10 /* entry # in EVENT table */
-#define MAX_NUMBER_OF_MAC 32 /* if MAX_MBSSID_NUM is 8, this value can't be larger than 211 */
-#define MAX_NUMBER_OF_ACL 64
-#define MAX_LENGTH_OF_SUPPORT_RATES 12 /* 1, 2, 5.5, 11, 6, 9, 12, 18, 24, 36, 48, 54 */
-#define MAX_NUMBER_OF_DLS_ENTRY 4
-
-#define RT_QUERY_SIGNAL_CONTEXT 0x0402
-#define RT_SET_IAPP_PID 0x0404
-#define RT_SET_APD_PID 0x0405
-#define RT_SET_DEL_MAC_ENTRY 0x0406
-#define RT_QUERY_EVENT_TABLE 0x0407
-/* */
-/* IEEE 802.11 OIDs */
-/* */
-#define OID_GET_SET_TOGGLE 0x8000
-#define OID_GET_SET_FROM_UI 0x4000
-
-#define OID_802_11_ADD_WEP 0x0112
-#define OID_802_11_DISASSOCIATE 0x0114
-#define OID_802_11_BSSID_LIST_SCAN 0x0508
-#define OID_802_11_SSID 0x0509
-#define OID_802_11_BSSID 0x050A
-#define OID_802_11_MIC_FAILURE_REPORT_FRAME 0x0528
-
-#define RT_OID_DEVICE_NAME 0x0607
-#define RT_OID_VERSION_INFO 0x0608
-#define OID_802_11_BSSID_LIST 0x0609
-#define OID_802_3_CURRENT_ADDRESS 0x060A
-#define OID_GEN_MEDIA_CONNECT_STATUS 0x060B
-#define RT_OID_802_11_QUERY_LINK_STATUS 0x060C
-#define OID_802_11_RSSI 0x060D
-#define OID_802_11_STATISTICS 0x060E
-#define OID_GEN_RCV_OK 0x060F
-#define OID_GEN_RCV_NO_BUFFER 0x0610
-#define RT_OID_802_11_QUERY_EEPROM_VERSION 0x0611
-#define RT_OID_802_11_QUERY_FIRMWARE_VERSION 0x0612
-#define RT_OID_802_11_QUERY_LAST_RX_RATE 0x0613
-#define RT_OID_802_11_TX_POWER_LEVEL_1 0x0614
-#define RT_OID_802_11_QUERY_PIDVID 0x0615
-/*for WPA_SUPPLICANT_SUPPORT */
-#define OID_SET_COUNTERMEASURES 0x0616
-#define RT_OID_WPA_SUPPLICANT_SUPPORT 0x0621
-#define RT_OID_WE_VERSION_COMPILED 0x0622
-#define RT_OID_NEW_DRIVER 0x0623
-
-#define RT_OID_DRIVER_DEVICE_NAME 0x0645
-#define RT_OID_QUERY_MULTIPLE_CARD_SUPPORT 0x0647
-
-typedef enum _NDIS_802_11_STATUS_TYPE {
- Ndis802_11StatusType_Authentication,
- Ndis802_11StatusType_MediaStreamMode,
- Ndis802_11StatusType_PMKID_CandidateList,
- Ndis802_11StatusTypeMax /* not a real type, defined as an upper bound */
-} NDIS_802_11_STATUS_TYPE, *PNDIS_802_11_STATUS_TYPE;
-
-typedef u8 NDIS_802_11_MAC_ADDRESS[6];
-
-struct rt_ndis_802_11_status_indication {
- NDIS_802_11_STATUS_TYPE StatusType;
-};
-
-/* mask for authentication/integrity fields */
-#define NDIS_802_11_AUTH_REQUEST_AUTH_FIELDS 0x0f
-
-#define NDIS_802_11_AUTH_REQUEST_REAUTH 0x01
-#define NDIS_802_11_AUTH_REQUEST_KEYUPDATE 0x02
-#define NDIS_802_11_AUTH_REQUEST_PAIRWISE_ERROR 0x06
-#define NDIS_802_11_AUTH_REQUEST_GROUP_ERROR 0x0E
-
-struct rt_ndis_802_11_authentication_request {
- unsigned long Length; /* Length of structure */
- NDIS_802_11_MAC_ADDRESS Bssid;
- unsigned long Flags;
-};
-
-/*Added new types for PMKID Candidate lists. */
-struct rt_pmkid_candidate {
- NDIS_802_11_MAC_ADDRESS BSSID;
- unsigned long Flags;
-};
-
-struct rt_ndis_802_11_pmkid_candidate_list {
- unsigned long Version; /* Version of the structure */
- unsigned long NumCandidates; /* No. of pmkid candidates */
- struct rt_pmkid_candidate CandidateList[1];
-};
-
-/*Flags for PMKID Candidate list structure */
-#define NDIS_802_11_PMKID_CANDIDATE_PREAUTH_ENABLED 0x01
-
-/* Added new types for OFDM 5G and 2.4G */
-typedef enum _NDIS_802_11_NETWORK_TYPE {
- Ndis802_11FH,
- Ndis802_11DS,
- Ndis802_11OFDM5,
- Ndis802_11OFDM24,
- Ndis802_11Automode,
- Ndis802_11OFDM5_N,
- Ndis802_11OFDM24_N,
- Ndis802_11NetworkTypeMax /* not a real type, defined as an upper bound */
-} NDIS_802_11_NETWORK_TYPE, *PNDIS_802_11_NETWORK_TYPE;
-
-struct rt_ndis_802_11_network_type_list {
- u32 NumberOfItems; /* in list below, at least 1 */
- NDIS_802_11_NETWORK_TYPE NetworkType[1];
-};
-
-typedef enum _NDIS_802_11_POWER_MODE {
- Ndis802_11PowerModeCAM,
- Ndis802_11PowerModeMAX_PSP,
- Ndis802_11PowerModeFast_PSP,
- Ndis802_11PowerModeLegacy_PSP,
- Ndis802_11PowerModeMax /* not a real mode, defined as an upper bound */
-} NDIS_802_11_POWER_MODE, *PNDIS_802_11_POWER_MODE;
-
-typedef unsigned long NDIS_802_11_TX_POWER_LEVEL; /* in milliwatts */
-
-/* */
-/* Received Signal Strength Indication */
-/* */
-typedef long NDIS_802_11_RSSI; /* in dBm */
-
-struct rt_ndis_802_11_configuration_fh {
- unsigned long Length; /* Length of structure */
- unsigned long HopPattern; /* As defined by 802.11, MSB set */
- unsigned long HopSet; /* to one if non-802.11 */
- unsigned long DwellTime; /* units are Kusec */
-};
-
-struct rt_ndis_802_11_configuration {
- unsigned long Length; /* Length of structure */
- unsigned long BeaconPeriod; /* units are Kusec */
- unsigned long ATIMWindow; /* units are Kusec */
- unsigned long DSConfig; /* Frequency, units are kHz */
- struct rt_ndis_802_11_configuration_fh FHConfig;
-};
-
-struct rt_ndis_802_11_statistics {
- unsigned long Length; /* Length of structure */
- LARGE_INTEGER TransmittedFragmentCount;
- LARGE_INTEGER MulticastTransmittedFrameCount;
- LARGE_INTEGER FailedCount;
- LARGE_INTEGER RetryCount;
- LARGE_INTEGER MultipleRetryCount;
- LARGE_INTEGER RTSSuccessCount;
- LARGE_INTEGER RTSFailureCount;
- LARGE_INTEGER ACKFailureCount;
- LARGE_INTEGER FrameDuplicateCount;
- LARGE_INTEGER ReceivedFragmentCount;
- LARGE_INTEGER MulticastReceivedFrameCount;
- LARGE_INTEGER FCSErrorCount;
- LARGE_INTEGER TKIPLocalMICFailures;
- LARGE_INTEGER TKIPRemoteMICErrors;
- LARGE_INTEGER TKIPICVErrors;
- LARGE_INTEGER TKIPCounterMeasuresInvoked;
- LARGE_INTEGER TKIPReplays;
- LARGE_INTEGER CCMPFormatErrors;
- LARGE_INTEGER CCMPReplays;
- LARGE_INTEGER CCMPDecryptErrors;
- LARGE_INTEGER FourWayHandshakeFailures;
-};
-
-typedef unsigned long NDIS_802_11_KEY_INDEX;
-typedef unsigned long long NDIS_802_11_KEY_RSC;
-
-#define MAX_RADIUS_SRV_NUM 2 /* 802.1x failover number */
-
-struct PACKED rt_radius_srv_info {
- u32 radius_ip;
- u32 radius_port;
- u8 radius_key[64];
- u8 radius_key_len;
-};
-
-struct PACKED rt_radius_key_info {
- u8 radius_srv_num;
- struct rt_radius_srv_info radius_srv_info[MAX_RADIUS_SRV_NUM];
- u8 ieee8021xWEP; /* dynamic WEP */
- u8 key_index;
- u8 key_length; /* length of key in bytes */
- u8 key_material[13];
-};
-
-/* It's used by 802.1x daemon to require relative configuration */
-struct PACKED rt_radius_conf {
- u32 Length; /* Length of this structure */
- u8 mbss_num; /* indicate multiple BSS number */
- u32 own_ip_addr;
- u32 retry_interval;
- u32 session_timeout_interval;
- u8 EAPifname[8][IFNAMSIZ];
- u8 EAPifname_len[8];
- u8 PreAuthifname[8][IFNAMSIZ];
- u8 PreAuthifname_len[8];
- struct rt_radius_key_info RadiusInfo[8];
-};
-
-/* Key mapping keys require a BSSID */
-struct rt_ndis_802_11_key {
- u32 Length; /* Length of this structure */
- u32 KeyIndex;
- u32 KeyLength; /* length of key in bytes */
- NDIS_802_11_MAC_ADDRESS BSSID;
- NDIS_802_11_KEY_RSC KeyRSC;
- u8 KeyMaterial[1]; /* variable length depending on above field */
-};
-
-struct rt_ndis_802_11_passphrase {
- u32 KeyLength; /* length of key in bytes */
- NDIS_802_11_MAC_ADDRESS BSSID;
- u8 KeyMaterial[1]; /* variable length depending on above field */
-};
-
-struct rt_ndis_802_11_remove_key {
- u32 Length; /* Length of this structure */
- u32 KeyIndex;
- NDIS_802_11_MAC_ADDRESS BSSID;
-};
-
-struct rt_ndis_802_11_wep {
- u32 Length; /* Length of this structure */
- u32 KeyIndex; /* 0 is the per-client key, 1-N are the */
- /* global keys */
- u32 KeyLength; /* length of key in bytes */
- u8 KeyMaterial[1]; /* variable length depending on above field */
-};
-
-typedef enum _NDIS_802_11_NETWORK_INFRASTRUCTURE {
- Ndis802_11IBSS,
- Ndis802_11Infrastructure,
- Ndis802_11AutoUnknown,
- Ndis802_11Monitor,
- Ndis802_11InfrastructureMax /* Not a real value, defined as upper bound */
-} NDIS_802_11_NETWORK_INFRASTRUCTURE, *PNDIS_802_11_NETWORK_INFRASTRUCTURE;
-
-/* Add new authentication modes */
-typedef enum _NDIS_802_11_AUTHENTICATION_MODE {
- Ndis802_11AuthModeOpen,
- Ndis802_11AuthModeShared,
- Ndis802_11AuthModeAutoSwitch,
- Ndis802_11AuthModeWPA,
- Ndis802_11AuthModeWPAPSK,
- Ndis802_11AuthModeWPANone,
- Ndis802_11AuthModeWPA2,
- Ndis802_11AuthModeWPA2PSK,
- Ndis802_11AuthModeWPA1WPA2,
- Ndis802_11AuthModeWPA1PSKWPA2PSK,
- Ndis802_11AuthModeMax /* Not a real mode, defined as upper bound */
-} NDIS_802_11_AUTHENTICATION_MODE, *PNDIS_802_11_AUTHENTICATION_MODE;
-
-typedef u8 NDIS_802_11_RATES[NDIS_802_11_LENGTH_RATES]; /* Set of 8 data rates */
-typedef u8 NDIS_802_11_RATES_EX[NDIS_802_11_LENGTH_RATES_EX]; /* Set of 16 data rates */
-
-struct PACKED rt_ndis_802_11_ssid {
- u32 SsidLength; /* length of SSID field below, in bytes; */
- /* this can be zero. */
- u8 Ssid[NDIS_802_11_LENGTH_SSID]; /* SSID information field */
-};
-
-struct PACKED rt_ndis_wlan_bssid {
- unsigned long Length; /* Length of this structure */
- NDIS_802_11_MAC_ADDRESS MacAddress; /* BSSID */
- u8 Reserved[2];
- struct rt_ndis_802_11_ssid Ssid; /* SSID */
- unsigned long Privacy; /* WEP encryption requirement */
- NDIS_802_11_RSSI Rssi; /* receive signal strength in dBm */
- NDIS_802_11_NETWORK_TYPE NetworkTypeInUse;
- struct rt_ndis_802_11_configuration Configuration;
- NDIS_802_11_NETWORK_INFRASTRUCTURE InfrastructureMode;
- NDIS_802_11_RATES SupportedRates;
-};
-
-struct PACKED rt_ndis_802_11_bssid_list {
- u32 NumberOfItems; /* in list below, at least 1 */
- struct rt_ndis_wlan_bssid Bssid[1];
-};
-
-/* Added Capabilities, IELength and IEs for each BSSID */
-struct PACKED rt_ndis_wlan_bssid_ex {
- unsigned long Length; /* Length of this structure */
- NDIS_802_11_MAC_ADDRESS MacAddress; /* BSSID */
- u8 Reserved[2];
- struct rt_ndis_802_11_ssid Ssid; /* SSID */
- u32 Privacy; /* WEP encryption requirement */
- NDIS_802_11_RSSI Rssi; /* receive signal */
- /* strength in dBm */
- NDIS_802_11_NETWORK_TYPE NetworkTypeInUse;
- struct rt_ndis_802_11_configuration Configuration;
- NDIS_802_11_NETWORK_INFRASTRUCTURE InfrastructureMode;
- NDIS_802_11_RATES_EX SupportedRates;
- unsigned long IELength;
- u8 IEs[1];
-};
-
-struct PACKED rt_ndis_802_11_bssid_list_ex {
- u32 NumberOfItems; /* in list below, at least 1 */
- struct rt_ndis_wlan_bssid_ex Bssid[1];
-};
-
-struct PACKED rt_ndis_802_11_fixed_ies {
- u8 Timestamp[8];
- u16 BeaconInterval;
- u16 Capabilities;
-};
-
-struct rt_ndis_802_11_variable_ies {
- u8 ElementID;
- u8 Length; /* Number of bytes in data field */
- u8 data[1];
-};
-
-typedef unsigned long NDIS_802_11_FRAGMENTATION_THRESHOLD;
-
-typedef unsigned long NDIS_802_11_RTS_THRESHOLD;
-
-typedef unsigned long NDIS_802_11_ANTENNA;
-
-typedef enum _NDIS_802_11_PRIVACY_FILTER {
- Ndis802_11PrivFilterAcceptAll,
- Ndis802_11PrivFilter8021xWEP
-} NDIS_802_11_PRIVACY_FILTER, *PNDIS_802_11_PRIVACY_FILTER;
-
-/* Added new encryption types */
-/* Also aliased typedef to new name */
-typedef enum _NDIS_802_11_WEP_STATUS {
- Ndis802_11WEPEnabled,
- Ndis802_11Encryption1Enabled = Ndis802_11WEPEnabled,
- Ndis802_11WEPDisabled,
- Ndis802_11EncryptionDisabled = Ndis802_11WEPDisabled,
- Ndis802_11WEPKeyAbsent,
- Ndis802_11Encryption1KeyAbsent = Ndis802_11WEPKeyAbsent,
- Ndis802_11WEPNotSupported,
- Ndis802_11EncryptionNotSupported = Ndis802_11WEPNotSupported,
- Ndis802_11Encryption2Enabled,
- Ndis802_11Encryption2KeyAbsent,
- Ndis802_11Encryption3Enabled,
- Ndis802_11Encryption3KeyAbsent,
- Ndis802_11Encryption4Enabled, /* TKIP or AES mix */
- Ndis802_11Encryption4KeyAbsent,
- Ndis802_11GroupWEP40Enabled,
- Ndis802_11GroupWEP104Enabled,
-} NDIS_802_11_WEP_STATUS, *PNDIS_802_11_WEP_STATUS,
- NDIS_802_11_ENCRYPTION_STATUS, *PNDIS_802_11_ENCRYPTION_STATUS;
-
-typedef enum _NDIS_802_11_RELOAD_DEFAULTS {
- Ndis802_11ReloadWEPKeys
-} NDIS_802_11_RELOAD_DEFAULTS, *PNDIS_802_11_RELOAD_DEFAULTS;
-
-#define NDIS_802_11_AI_REQFI_CAPABILITIES 1
-#define NDIS_802_11_AI_REQFI_LISTENINTERVAL 2
-#define NDIS_802_11_AI_REQFI_CURRENTAPADDRESS 4
-
-#define NDIS_802_11_AI_RESFI_CAPABILITIES 1
-#define NDIS_802_11_AI_RESFI_STATUSCODE 2
-#define NDIS_802_11_AI_RESFI_ASSOCIATIONID 4
-
-struct rt_ndis_802_11_ai_reqfi {
- u16 Capabilities;
- u16 ListenInterval;
- NDIS_802_11_MAC_ADDRESS CurrentAPAddress;
-};
-
-struct rt_ndis_802_11_ai_resfi {
- u16 Capabilities;
- u16 StatusCode;
- u16 AssociationId;
-};
-
-struct rt_ndis_802_11_association_information {
- unsigned long Length;
- u16 AvailableRequestFixedIEs;
- struct rt_ndis_802_11_ai_reqfi RequestFixedIEs;
- unsigned long RequestIELength;
- unsigned long OffsetRequestIEs;
- u16 AvailableResponseFixedIEs;
- struct rt_ndis_802_11_ai_resfi ResponseFixedIEs;
- unsigned long ResponseIELength;
- unsigned long OffsetResponseIEs;
-};
-
-struct rt_ndis_802_11_authentication_event {
- struct rt_ndis_802_11_status_indication Status;
- struct rt_ndis_802_11_authentication_request Request[1];
-};
-
-/* 802.11 Media stream constraints, associated with OID_802_11_MEDIA_STREAM_MODE */
-typedef enum _NDIS_802_11_MEDIA_STREAM_MODE {
- Ndis802_11MediaStreamOff,
- Ndis802_11MediaStreamOn,
-} NDIS_802_11_MEDIA_STREAM_MODE, *PNDIS_802_11_MEDIA_STREAM_MODE;
-
-/* PMKID Structures */
-typedef u8 NDIS_802_11_PMKID_VALUE[16];
-
-struct rt_bssid_info {
- NDIS_802_11_MAC_ADDRESS BSSID;
- NDIS_802_11_PMKID_VALUE PMKID;
-};
-
-struct rt_ndis_802_11_pmkid {
- u32 Length;
- u32 BSSIDInfoCount;
- struct rt_bssid_info BSSIDInfo[1];
-};
-
-struct rt_ndis_802_11_authentication_encryption {
- NDIS_802_11_AUTHENTICATION_MODE AuthModeSupported;
- NDIS_802_11_ENCRYPTION_STATUS EncryptStatusSupported;
-};
-
-struct rt_ndis_802_11_capability {
- unsigned long Length;
- unsigned long Version;
- unsigned long NoOfPMKIDs;
- unsigned long NoOfAuthEncryptPairsSupported;
- struct rt_ndis_802_11_authentication_encryption
- AuthenticationEncryptionSupported[1];
-};
-
-#define RT_PRIV_IOCTL (SIOCIWFIRSTPRIV + 0x01) /* Sync. with AP for wsc upnp daemon */
-#define RTPRIV_IOCTL_SET (SIOCIWFIRSTPRIV + 0x02)
-
-#define RTPRIV_IOCTL_STATISTICS (SIOCIWFIRSTPRIV + 0x09)
-#define RTPRIV_IOCTL_ADD_PMKID_CACHE (SIOCIWFIRSTPRIV + 0x0A)
-#define RTPRIV_IOCTL_RADIUS_DATA (SIOCIWFIRSTPRIV + 0x0C)
-#define RTPRIV_IOCTL_GSITESURVEY (SIOCIWFIRSTPRIV + 0x0D)
-#define RT_PRIV_IOCTL_EXT (SIOCIWFIRSTPRIV + 0x0E) /* Sync. with RT61 (for wpa_supplicant) */
-#define RTPRIV_IOCTL_GET_MAC_TABLE (SIOCIWFIRSTPRIV + 0x0F)
-
-#define RTPRIV_IOCTL_SHOW (SIOCIWFIRSTPRIV + 0x11)
-enum {
- SHOW_CONN_STATUS = 4,
- SHOW_DRVIER_VERION = 5,
- SHOW_BA_INFO = 6,
- SHOW_DESC_INFO = 7,
-#ifdef RTMP_MAC_USB
- SHOW_RXBULK_INFO = 8,
- SHOW_TXBULK_INFO = 9,
-#endif /* RTMP_MAC_USB // */
- RAIO_OFF = 10,
- RAIO_ON = 11,
- SHOW_CFG_VALUE = 20,
- SHOW_ADHOC_ENTRY_INFO = 21,
-};
-
-#define OID_802_11_BUILD_CHANNEL_EX 0x0714
-#define OID_802_11_GET_CH_LIST 0x0715
-#define OID_802_11_GET_COUNTRY_CODE 0x0716
-#define OID_802_11_GET_CHANNEL_GEOGRAPHY 0x0717
-
-#define RT_OID_WSC_SET_PASSPHRASE 0x0740 /* passphrase for wpa(2)-psk */
-#define RT_OID_WSC_DRIVER_AUTO_CONNECT 0x0741
-#define RT_OID_WSC_QUERY_DEFAULT_PROFILE 0x0742
-#define RT_OID_WSC_SET_CONN_BY_PROFILE_INDEX 0x0743
-#define RT_OID_WSC_SET_ACTION 0x0744
-#define RT_OID_WSC_SET_SSID 0x0745
-#define RT_OID_WSC_SET_PIN_CODE 0x0746
-#define RT_OID_WSC_SET_MODE 0x0747 /* PIN or PBC */
-#define RT_OID_WSC_SET_CONF_MODE 0x0748 /* Enrollee or Registrar */
-#define RT_OID_WSC_SET_PROFILE 0x0749
-#define RT_OID_WSC_CONFIG_STATUS 0x074F
-#define RT_OID_802_11_WSC_QUERY_PROFILE 0x0750
-/* for consistency with RT61 */
-#define RT_OID_WSC_QUERY_STATUS 0x0751
-#define RT_OID_WSC_PIN_CODE 0x0752
-#define RT_OID_WSC_UUID 0x0753
-#define RT_OID_WSC_SET_SELECTED_REGISTRAR 0x0754
-#define RT_OID_WSC_EAPMSG 0x0755
-#define RT_OID_WSC_MANUFACTURER 0x0756
-#define RT_OID_WSC_MODEL_NAME 0x0757
-#define RT_OID_WSC_MODEL_NO 0x0758
-#define RT_OID_WSC_SERIAL_NO 0x0759
-#define RT_OID_WSC_MAC_ADDRESS 0x0760
-
-/* New for MeetingHouse Api support */
-#define OID_MH_802_1X_SUPPORTED 0xFFEDC100
-
-/* MIMO Tx parameter, ShortGI, MCS, STBC, etc. these are fields in TXWI. Don't change this definition! */
-typedef union _HTTRANSMIT_SETTING {
- struct {
- u16 MCS:7; /* MCS */
- u16 BW:1; /*channel bandwidth 20MHz or 40 MHz */
- u16 ShortGI:1;
- u16 STBC:2; /*SPACE */
-/* u16 rsv:3; */
- u16 rsv:2;
- u16 TxBF:1;
- u16 MODE:2; /* Use definition MODE_xxx. */
- } field;
- u16 word;
-} HTTRANSMIT_SETTING, *PHTTRANSMIT_SETTING;
-
-typedef enum _RT_802_11_PREAMBLE {
- Rt802_11PreambleLong,
- Rt802_11PreambleShort,
- Rt802_11PreambleAuto
-} RT_802_11_PREAMBLE, *PRT_802_11_PREAMBLE;
-
-typedef enum _RT_802_11_PHY_MODE {
- PHY_11BG_MIXED = 0,
- PHY_11B,
- PHY_11A,
- PHY_11ABG_MIXED,
- PHY_11G,
- PHY_11ABGN_MIXED, /* both band 5 */
- PHY_11N_2_4G, /* 11n-only with 2.4G band 6 */
- PHY_11GN_MIXED, /* 2.4G band 7 */
- PHY_11AN_MIXED, /* 5G band 8 */
- PHY_11BGN_MIXED, /* if check 802.11b. 9 */
- PHY_11AGN_MIXED, /* if check 802.11b. 10 */
- PHY_11N_5G, /* 11n-only with 5G band 11 */
-} RT_802_11_PHY_MODE;
-
-/* put all proprietery for-query objects here to reduce # of Query_OID */
-struct rt_802_11_link_status {
- unsigned long CurrTxRate; /* in units of 0.5Mbps */
- unsigned long ChannelQuality; /* 0..100 % */
- unsigned long TxByteCount; /* both ok and fail */
- unsigned long RxByteCount; /* both ok and fail */
- unsigned long CentralChannel; /* 40MHz central channel number */
-};
-
-struct rt_802_11_event_log {
- LARGE_INTEGER SystemTime; /* timestammp via NdisGetCurrentSystemTime() */
- u8 Addr[MAC_ADDR_LENGTH];
- u16 Event; /* EVENT_xxx */
-};
-
-struct rt_802_11_event_table {
- unsigned long Num;
- unsigned long Rsv; /* to align Log[] at LARGE_INTEGER boundary */
- struct rt_802_11_event_log Log[MAX_NUMBER_OF_EVENT];
-};
-
-/* MIMO Tx parameter, ShortGI, MCS, STBC, etc. these are fields in TXWI. Don't change this definition! */
-typedef union _MACHTTRANSMIT_SETTING {
- struct {
- u16 MCS:7; /* MCS */
- u16 BW:1; /*channel bandwidth 20MHz or 40 MHz */
- u16 ShortGI:1;
- u16 STBC:2; /*SPACE */
- u16 rsv:3;
- u16 MODE:2; /* Use definition MODE_xxx. */
- } field;
- u16 word;
-} MACHTTRANSMIT_SETTING, *PMACHTTRANSMIT_SETTING;
-
-struct rt_802_11_mac_entry {
- u8 Addr[MAC_ADDR_LENGTH];
- u8 Aid;
- u8 Psm; /* 0:PWR_ACTIVE, 1:PWR_SAVE */
- u8 MimoPs; /* 0:MMPS_STATIC, 1:MMPS_DYNAMIC, 3:MMPS_Enabled */
- char AvgRssi0;
- char AvgRssi1;
- char AvgRssi2;
- u32 ConnectedTime;
- MACHTTRANSMIT_SETTING TxRate;
-};
-
-struct rt_802_11_mac_table {
- unsigned long Num;
- struct rt_802_11_mac_entry Entry[MAX_NUMBER_OF_MAC];
-};
-
-/* structure for query/set hardware register - MAC, BBP, RF register */
-struct rt_802_11_hardware_register {
- unsigned long HardwareType; /* 0:MAC, 1:BBP, 2:RF register, 3:EEPROM */
- unsigned long Offset; /* Q/S register offset addr */
- unsigned long Data; /* R/W data buffer */
-};
-
-struct rt_802_11_ap_config {
- unsigned long EnableTxBurst; /* 0-disable, 1-enable */
- unsigned long EnableTurboRate; /* 0-disable, 1-enable 72/100mbps turbo rate */
- unsigned long IsolateInterStaTraffic; /* 0-disable, 1-enable isolation */
- unsigned long HideSsid; /* 0-disable, 1-enable hiding */
- unsigned long UseBGProtection; /* 0-AUTO, 1-always ON, 2-always OFF */
- unsigned long UseShortSlotTime; /* 0-no use, 1-use 9-us short slot time */
- unsigned long Rsv1; /* must be 0 */
- unsigned long SystemErrorBitmap; /* ignore upon SET, return system error upon QUERY */
-};
-
-/* structure to query/set STA_CONFIG */
-struct rt_802_11_sta_config {
- unsigned long EnableTxBurst; /* 0-disable, 1-enable */
- unsigned long EnableTurboRate; /* 0-disable, 1-enable 72/100mbps turbo rate */
- unsigned long UseBGProtection; /* 0-AUTO, 1-always ON, 2-always OFF */
- unsigned long UseShortSlotTime; /* 0-no use, 1-use 9-us short slot time when applicable */
- unsigned long AdhocMode; /* 0-11b rates only (WIFI spec), 1 - b/g mixed, 2 - g only */
- unsigned long HwRadioStatus; /* 0-OFF, 1-ON, default is 1, Read-Only */
- unsigned long Rsv1; /* must be 0 */
- unsigned long SystemErrorBitmap; /* ignore upon SET, return system error upon QUERY */
-};
-
-/* */
-/* For OID Query or Set about BA structure */
-/* */
-struct rt_oid_bacap {
- u8 RxBAWinLimit;
- u8 TxBAWinLimit;
- u8 Policy; /* 0: DELAY_BA 1:IMMED_BA (//BA Policy subfiled value in ADDBA frame) 2:BA-not use. other value invalid */
- u8 MpduDensity; /* 0: DELAY_BA 1:IMMED_BA (//BA Policy subfiled value in ADDBA frame) 2:BA-not use. other value invalid */
- u8 AmsduEnable; /*Enable AMSDU transmisstion */
- u8 AmsduSize; /* 0:3839, 1:7935 bytes. u32 MSDUSizeToBytes[] = { 3839, 7935}; */
- u8 MMPSmode; /* MIMO power save more, 0:static, 1:dynamic, 2:rsv, 3:mimo enable */
- BOOLEAN AutoBA; /* Auto BA will automatically */
-};
-
-struct rt_802_11_acl_entry {
- u8 Addr[MAC_ADDR_LENGTH];
- u16 Rsv;
-};
-
-struct PACKED rt_rt_802_11_acl {
- unsigned long Policy; /* 0-disable, 1-positive list, 2-negative list */
- unsigned long Num;
- struct rt_802_11_acl_entry Entry[MAX_NUMBER_OF_ACL];
-};
-
-struct rt_802_11_wds {
- unsigned long Num;
- NDIS_802_11_MAC_ADDRESS Entry[24 /*MAX_NUM_OF_WDS_LINK */];
- unsigned long KeyLength;
- u8 KeyMaterial[32];
-};
-
-struct rt_802_11_tx_rates {
- u8 SupRateLen;
- u8 SupRate[MAX_LENGTH_OF_SUPPORT_RATES];
- u8 ExtRateLen;
- u8 ExtRate[MAX_LENGTH_OF_SUPPORT_RATES];
-};
-
-/* Definition of extra information code */
-#define GENERAL_LINK_UP 0x0 /* Link is Up */
-#define GENERAL_LINK_DOWN 0x1 /* Link is Down */
-#define HW_RADIO_OFF 0x2 /* Hardware radio off */
-#define SW_RADIO_OFF 0x3 /* Software radio off */
-#define AUTH_FAIL 0x4 /* Open authentication fail */
-#define AUTH_FAIL_KEYS 0x5 /* Shared authentication fail */
-#define ASSOC_FAIL 0x6 /* Association failed */
-#define EAP_MIC_FAILURE 0x7 /* Deauthentication because MIC failure */
-#define EAP_4WAY_TIMEOUT 0x8 /* Deauthentication on 4-way handshake timeout */
-#define EAP_GROUP_KEY_TIMEOUT 0x9 /* Deauthentication on group key handshake timeout */
-#define EAP_SUCCESS 0xa /* EAP succeed */
-#define DETECT_RADAR_SIGNAL 0xb /* Radar signal occur in current channel */
-#define EXTRA_INFO_MAX 0xb /* Indicate Last OID */
-
-#define EXTRA_INFO_CLEAR 0xffffffff
-
-/* This is OID setting structure. So only GF or MM as Mode. This is valid when our wirelss mode has 802.11n in use. */
-struct rt_oid_set_ht_phymode {
- RT_802_11_PHY_MODE PhyMode; /* */
- u8 TransmitNo;
- u8 HtMode; /*HTMODE_GF or HTMODE_MM */
- u8 ExtOffset; /*extension channel above or below */
- u8 MCS;
- u8 BW;
- u8 STBC;
- u8 SHORTGI;
- u8 rsv;
-};
-
-#define MAX_CUSTOM_LEN 128
-
-typedef enum _RT_802_11_D_CLIENT_MODE {
- Rt802_11_D_None,
- Rt802_11_D_Flexible,
- Rt802_11_D_Strict,
-} RT_802_11_D_CLIENT_MODE, *PRT_802_11_D_CLIENT_MODE;
-
-struct rt_channel_list_info {
- u8 ChannelList[MAX_NUM_OF_CHS]; /* list all supported channels for site survey */
- u8 ChannelListNum; /* number of channel in ChannelList[] */
-};
-
-/* WSC configured credential */
-struct rt_wsc_credential {
- struct rt_ndis_802_11_ssid SSID; /* mandatory */
- u16 AuthType; /* mandatory, 1: open, 2: wpa-psk, 4: shared, 8:wpa, 0x10: wpa2, 0x20: wpa2-psk */
- u16 EncrType; /* mandatory, 1: none, 2: wep, 4: tkip, 8: aes */
- u8 Key[64]; /* mandatory, Maximum 64 byte */
- u16 KeyLength;
- u8 MacAddr[6]; /* mandatory, AP MAC address */
- u8 KeyIndex; /* optional, default is 1 */
- u8 Rsvd[3]; /* Make alignment */
-};
-
-/* WSC configured profiles */
-struct rt_wsc_profile {
- u32 ProfileCnt;
- u32 ApplyProfileIdx; /* add by johnli, fix WPS test plan 5.1.1 */
- struct rt_wsc_credential Profile[8]; /* Support up to 8 profiles */
-};
-
-#endif /* _OID_H_ */
diff --git a/drivers/staging/rt2860/pci_main_dev.c b/drivers/staging/rt2860/pci_main_dev.c
deleted file mode 100644
index 25fbb18..0000000
--- a/drivers/staging/rt2860/pci_main_dev.c
+++ /dev/null
@@ -1,1192 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- pci_main_dev.c
-
- Abstract:
- Create and register network interface for PCI based chipsets in Linux platform.
-
- Revision History:
- Who When What
- Justin P. Mattock 11/07/2010 Fix typos in some comments
- -------- ---------- ----------------------------------------------
-*/
-
-#include "rt_config.h"
-#include <linux/pci.h>
-#include <linux/slab.h>
-
-/* Following information will be show when you run 'modinfo' */
-/* If you have a solution for a bug in current version of driver, please e-mail me. */
-/* Otherwise post to forum in ralinktech's web site(www.ralinktech.com) and let all users help you. */
-MODULE_AUTHOR("Jett Chen <jett_chen@ralinktech.com>");
-MODULE_DESCRIPTION("RT2860/RT3090 Wireless Lan Linux Driver");
-MODULE_LICENSE("GPL");
-MODULE_ALIAS("rt3090sta");
-
-/* */
-/* Function declarations */
-/* */
-static void __devexit rt2860_remove_one(struct pci_dev *pci_dev);
-static int __devinit rt2860_probe(struct pci_dev *pci_dev,
- const struct pci_device_id *ent);
-static void __exit rt2860_cleanup_module(void);
-static int __init rt2860_init_module(void);
-
-static void RTMPInitPCIeDevice(IN struct pci_dev *pci_dev,
- struct rt_rtmp_adapter *pAd);
-
-#ifdef CONFIG_PM
-static int rt2860_suspend(struct pci_dev *pci_dev, pm_message_t state);
-static int rt2860_resume(struct pci_dev *pci_dev);
-#endif /* CONFIG_PM // */
-
-/* */
-/* Ralink PCI device table, include all supported chipsets */
-/* */
-static struct pci_device_id rt2860_pci_tbl[] __devinitdata = {
-#ifdef RT2860
- {PCI_DEVICE(NIC_PCI_VENDOR_ID, NIC2860_PCI_DEVICE_ID)}, /*RT28602.4G */
- {PCI_DEVICE(NIC_PCI_VENDOR_ID, NIC2860_PCIe_DEVICE_ID)},
- {PCI_DEVICE(NIC_PCI_VENDOR_ID, NIC2760_PCI_DEVICE_ID)},
- {PCI_DEVICE(NIC_PCI_VENDOR_ID, NIC2790_PCIe_DEVICE_ID)},
- {PCI_DEVICE(VEN_AWT_PCI_VENDOR_ID, VEN_AWT_PCIe_DEVICE_ID)},
- {PCI_DEVICE(EDIMAX_PCI_VENDOR_ID, 0x7708)},
- {PCI_DEVICE(EDIMAX_PCI_VENDOR_ID, 0x7728)},
- {PCI_DEVICE(EDIMAX_PCI_VENDOR_ID, 0x7758)},
- {PCI_DEVICE(EDIMAX_PCI_VENDOR_ID, 0x7727)},
- {PCI_DEVICE(EDIMAX_PCI_VENDOR_ID, 0x7738)},
- {PCI_DEVICE(EDIMAX_PCI_VENDOR_ID, 0x7748)},
- {PCI_DEVICE(EDIMAX_PCI_VENDOR_ID, 0x7768)},
-#endif
-#ifdef RT3090
- {PCI_DEVICE(NIC_PCI_VENDOR_ID, NIC3090_PCIe_DEVICE_ID)},
- {PCI_DEVICE(NIC_PCI_VENDOR_ID, NIC3091_PCIe_DEVICE_ID)},
- {PCI_DEVICE(NIC_PCI_VENDOR_ID, NIC3092_PCIe_DEVICE_ID)},
-#endif /* RT3090 // */
-#ifdef RT3390
- {PCI_DEVICE(NIC_PCI_VENDOR_ID, NIC3390_PCIe_DEVICE_ID)},
- {PCI_DEVICE(NIC_PCI_VENDOR_ID, NIC3391_PCIe_DEVICE_ID)},
- {PCI_DEVICE(NIC_PCI_VENDOR_ID, NIC3392_PCIe_DEVICE_ID)},
-#endif /* RT3390 // */
- {0,} /* terminate list */
-};
-
-MODULE_DEVICE_TABLE(pci, rt2860_pci_tbl);
-#ifdef MODULE_VERSION
-MODULE_VERSION(STA_DRIVER_VERSION);
-#endif
-
-/* */
-/* Our PCI driver structure */
-/* */
-static struct pci_driver rt2860_driver = {
-name: "rt2860",
-id_table : rt2860_pci_tbl,
-probe : rt2860_probe,
-remove : __devexit_p(rt2860_remove_one),
-#ifdef CONFIG_PM
-suspend : rt2860_suspend,
-resume : rt2860_resume,
-#endif
-};
-
-/***************************************************************************
- *
- * PCI device initialization related procedures.
- *
- ***************************************************************************/
-#ifdef CONFIG_PM
-
-void RT2860RejectPendingPackets(struct rt_rtmp_adapter *pAd)
-{
- /* clear PS packets */
- /* clear TxSw packets */
-}
-
-static int rt2860_suspend(struct pci_dev *pci_dev, pm_message_t state)
-{
- struct net_device *net_dev = pci_get_drvdata(pci_dev);
- struct rt_rtmp_adapter *pAd = (struct rt_rtmp_adapter *)NULL;
- int retval = 0;
-
- DBGPRINT(RT_DEBUG_TRACE, ("===> rt2860_suspend()\n"));
-
- if (net_dev == NULL) {
- DBGPRINT(RT_DEBUG_ERROR, ("net_dev == NULL!\n"));
- } else {
- GET_PAD_FROM_NET_DEV(pAd, net_dev);
-
- /* we can not use IFF_UP because ra0 down but ra1 up */
- /* and 1 suspend/resume function for 1 module, not for each interface */
- /* so Linux will call suspend/resume function once */
- if (VIRTUAL_IF_NUM(pAd) > 0) {
- /* avoid users do suspend after interface is down */
-
- /* stop interface */
- netif_carrier_off(net_dev);
- netif_stop_queue(net_dev);
-
- /* mark device as removed from system and therefore no longer available */
- netif_device_detach(net_dev);
-
- /* mark halt flag */
- RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS);
- RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_RADIO_OFF);
-
- /* take down the device */
- rt28xx_close((struct net_device *)net_dev);
-
- RT_MOD_DEC_USE_COUNT();
- }
- }
-
- /* reference to http://vovo2000.com/type-lab/linux/kernel-api/linux-kernel-api.html */
- /* enable device to generate PME# when suspended */
- /* pci_choose_state(): Choose the power state of a PCI device to be suspended */
- retval = pci_enable_wake(pci_dev, pci_choose_state(pci_dev, state), 1);
- /* save the PCI configuration space of a device before suspending */
- pci_save_state(pci_dev);
- /* disable PCI device after use */
- pci_disable_device(pci_dev);
-
- retval = pci_set_power_state(pci_dev, pci_choose_state(pci_dev, state));
-
- DBGPRINT(RT_DEBUG_TRACE, ("<=== rt2860_suspend()\n"));
- return retval;
-}
-
-static int rt2860_resume(struct pci_dev *pci_dev)
-{
- struct net_device *net_dev = pci_get_drvdata(pci_dev);
- struct rt_rtmp_adapter *pAd = (struct rt_rtmp_adapter *)NULL;
- int retval;
-
- /* set the power state of a PCI device */
- /* PCI has 4 power states, DO (normal) ~ D3(less power) */
- /* in include/linux/pci.h, you can find that */
- /* #define PCI_D0 ((pci_power_t __force) 0) */
- /* #define PCI_D1 ((pci_power_t __force) 1) */
- /* #define PCI_D2 ((pci_power_t __force) 2) */
- /* #define PCI_D3hot ((pci_power_t __force) 3) */
- /* #define PCI_D3cold ((pci_power_t __force) 4) */
- /* #define PCI_UNKNOWN ((pci_power_t __force) 5) */
- /* #define PCI_POWER_ERROR ((pci_power_t __force) -1) */
- retval = pci_set_power_state(pci_dev, PCI_D0);
-
- /* restore the saved state of a PCI device */
- pci_restore_state(pci_dev);
-
- /* initialize device before it's used by a driver */
- if (pci_enable_device(pci_dev)) {
- printk(KERN_ERR "rt2860: pci enable fail!\n");
- return 0;
- }
-
- DBGPRINT(RT_DEBUG_TRACE, ("===> rt2860_resume()\n"));
-
- if (net_dev == NULL)
- DBGPRINT(RT_DEBUG_ERROR, ("net_dev == NULL!\n"));
- else
- GET_PAD_FROM_NET_DEV(pAd, net_dev);
-
- if (pAd != NULL) {
- /* we can not use IFF_UP because ra0 down but ra1 up */
- /* and 1 suspend/resume function for 1 module, not for each interface */
- /* so Linux will call suspend/resume function once */
- if (VIRTUAL_IF_NUM(pAd) > 0) {
- /* mark device as attached from system and restart if needed */
- netif_device_attach(net_dev);
-
- if (rt28xx_open((struct net_device *)net_dev) != 0) {
- /* open fail */
- DBGPRINT(RT_DEBUG_TRACE,
- ("<=== rt2860_resume()\n"));
- return 0;
- }
- /* increase MODULE use count */
- RT_MOD_INC_USE_COUNT();
-
- RTMP_CLEAR_FLAG(pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS);
- RTMP_CLEAR_FLAG(pAd, fRTMP_ADAPTER_RADIO_OFF);
-
- netif_start_queue(net_dev);
- netif_carrier_on(net_dev);
- netif_wake_queue(net_dev);
- }
- }
-
- DBGPRINT(RT_DEBUG_TRACE, ("<=== rt2860_resume()\n"));
- return 0;
-}
-#endif /* CONFIG_PM // */
-
-static int __init rt2860_init_module(void)
-{
- return pci_register_driver(&rt2860_driver);
-}
-
-/* */
-/* Driver module unload function */
-/* */
-static void __exit rt2860_cleanup_module(void)
-{
- pci_unregister_driver(&rt2860_driver);
-}
-
-module_init(rt2860_init_module);
-module_exit(rt2860_cleanup_module);
-
-/* */
-/* PCI device probe & initialization function */
-/* */
-static int __devinit rt2860_probe(IN struct pci_dev *pci_dev,
- IN const struct pci_device_id *pci_id)
-{
- struct rt_rtmp_adapter *pAd = (struct rt_rtmp_adapter *)NULL;
- struct net_device *net_dev;
- void *handle;
- char *print_name;
- unsigned long csr_addr;
- int rv = 0;
- struct rt_rtmp_os_netdev_op_hook netDevHook;
-
- DBGPRINT(RT_DEBUG_TRACE, ("===> rt2860_probe\n"));
-
-/*PCIDevInit============================================== */
- /* wake up and enable device */
- rv = pci_enable_device(pci_dev);
-
- if (rv != 0) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("Enable PCI device failed, errno=%d!\n", rv));
- return rv;
- }
-
- print_name = (char *)pci_name(pci_dev);
-
- rv = pci_request_regions(pci_dev, print_name);
-
- if (rv != 0) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("Request PCI resource failed, errno=%d!\n", rv));
- goto err_out;
- }
- /* map physical address to virtual address for accessing register */
- csr_addr =
- (unsigned long)ioremap(pci_resource_start(pci_dev, 0),
- pci_resource_len(pci_dev, 0));
- if (!csr_addr) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("ioremap failed for device %s, region 0x%lX @ 0x%lX\n",
- print_name, (unsigned long)pci_resource_len(pci_dev, 0),
- (unsigned long)pci_resource_start(pci_dev, 0)));
- goto err_out_free_res;
- } else {
- DBGPRINT(RT_DEBUG_TRACE,
- ("%s: at 0x%lx, VA 0x%lx, IRQ %d. \n", print_name,
- (unsigned long)pci_resource_start(pci_dev, 0),
- (unsigned long)csr_addr, pci_dev->irq));
- }
-
- /* Set DMA master */
- pci_set_master(pci_dev);
-
-/*RtmpDevInit============================================== */
- /* Allocate struct rt_rtmp_adapter adapter structure */
- handle = kmalloc(sizeof(struct os_cookie), GFP_KERNEL);
- if (handle == NULL) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("%s(): Allocate memory for os handle failed!\n",
- __func__));
- goto err_out_iounmap;
- }
-
- ((struct os_cookie *)handle)->pci_dev = pci_dev;
-
- rv = RTMPAllocAdapterBlock(handle, &pAd); /*shiang: we may need the pci_dev for allocate structure of "struct rt_rtmp_adapter" */
- if (rv != NDIS_STATUS_SUCCESS)
- goto err_out_iounmap;
- /* Here are the struct rt_rtmp_adapter structure with pci-bus specific parameters. */
- pAd->CSRBaseAddress = (u8 *)csr_addr;
- DBGPRINT(RT_DEBUG_ERROR,
- ("pAd->CSRBaseAddress =0x%lx, csr_addr=0x%lx!\n",
- (unsigned long)pAd->CSRBaseAddress, csr_addr));
- RtmpRaDevCtrlInit(pAd, RTMP_DEV_INF_PCI);
-
-/*NetDevInit============================================== */
- net_dev = RtmpPhyNetDevInit(pAd, &netDevHook);
- if (net_dev == NULL)
- goto err_out_free_radev;
-
- /* Here are the net_device structure with pci-bus specific parameters. */
- net_dev->irq = pci_dev->irq; /* Interrupt IRQ number */
- net_dev->base_addr = csr_addr; /* Save CSR virtual address and irq to device structure */
- pci_set_drvdata(pci_dev, net_dev); /* Set driver data */
-
-/* for supporting Network Manager */
- /* Set the sysfs physical device reference for the network logical device
- * if set prior to registration will cause a symlink during initialization.
- */
- SET_NETDEV_DEV(net_dev, &(pci_dev->dev));
-
-/*All done, it's time to register the net device to linux kernel. */
- /* Register this device */
- rv = RtmpOSNetDevAttach(net_dev, &netDevHook);
- if (rv)
- goto err_out_free_netdev;
-
- pAd->StaCfg.OriDevType = net_dev->type;
- RTMPInitPCIeDevice(pci_dev, pAd);
-
- DBGPRINT(RT_DEBUG_TRACE, ("<=== rt2860_probe\n"));
-
- return 0; /* probe ok */
-
- /* --------------------------- ERROR HANDLE --------------------------- */
-err_out_free_netdev:
- RtmpOSNetDevFree(net_dev);
-
-err_out_free_radev:
- /* free struct rt_rtmp_adapter strcuture and os_cookie */
- RTMPFreeAdapter(pAd);
-
-err_out_iounmap:
- iounmap((void *)(csr_addr));
- release_mem_region(pci_resource_start(pci_dev, 0),
- pci_resource_len(pci_dev, 0));
-
-err_out_free_res:
- pci_release_regions(pci_dev);
-
-err_out:
- pci_disable_device(pci_dev);
-
- DBGPRINT(RT_DEBUG_ERROR,
- ("<=== rt2860_probe failed with rv = %d!\n", rv));
-
- return -ENODEV; /* probe fail */
-}
-
-static void __devexit rt2860_remove_one(IN struct pci_dev *pci_dev)
-{
- struct net_device *net_dev = pci_get_drvdata(pci_dev);
- struct rt_rtmp_adapter *pAd = NULL;
- unsigned long csr_addr = net_dev->base_addr; /* pAd->CSRBaseAddress; */
-
- GET_PAD_FROM_NET_DEV(pAd, net_dev);
-
- DBGPRINT(RT_DEBUG_TRACE, ("===> rt2860_remove_one\n"));
-
- if (pAd != NULL) {
- /* Unregister/Free all allocated net_device. */
- RtmpPhyNetDevExit(pAd, net_dev);
-
- /* Unmap CSR base address */
- iounmap((char *)(csr_addr));
-
- /* release memory region */
- release_mem_region(pci_resource_start(pci_dev, 0),
- pci_resource_len(pci_dev, 0));
-
- /* Free struct rt_rtmp_adapter related structures. */
- RtmpRaDevCtrlExit(pAd);
-
- } else {
- /* Unregister network device */
- RtmpOSNetDevDetach(net_dev);
-
- /* Unmap CSR base address */
- iounmap((char *)(net_dev->base_addr));
-
- /* release memory region */
- release_mem_region(pci_resource_start(pci_dev, 0),
- pci_resource_len(pci_dev, 0));
- }
-
- /* Free the root net_device */
- RtmpOSNetDevFree(net_dev);
-
-}
-
-/*
-========================================================================
-Routine Description:
- Check the chipset vendor/product ID.
-
-Arguments:
- _dev_p Point to the PCI or USB device
-
-Return Value:
- TRUE Check ok
- FALSE Check fail
-
-Note:
-========================================================================
-*/
-BOOLEAN RT28XXChipsetCheck(IN void *_dev_p)
-{
- /* always TRUE */
- return TRUE;
-}
-
-/***************************************************************************
- *
- * PCIe device initialization related procedures.
- *
- ***************************************************************************/
-static void RTMPInitPCIeDevice(struct pci_dev *pci_dev, struct rt_rtmp_adapter *pAd)
-{
- u16 device_id;
- struct os_cookie *pObj;
-
- pObj = (struct os_cookie *)pAd->OS_Cookie;
- pci_read_config_word(pci_dev, PCI_DEVICE_ID, &device_id);
- device_id = le2cpu16(device_id);
- pObj->DeviceID = device_id;
- if (
-#ifdef RT2860
- (device_id == NIC2860_PCIe_DEVICE_ID) ||
- (device_id == NIC2790_PCIe_DEVICE_ID) ||
- (device_id == VEN_AWT_PCIe_DEVICE_ID) ||
-#endif
-#ifdef RT3090
- (device_id == NIC3090_PCIe_DEVICE_ID) ||
- (device_id == NIC3091_PCIe_DEVICE_ID) ||
- (device_id == NIC3092_PCIe_DEVICE_ID) ||
-#endif /* RT3090 // */
- 0) {
- u32 MacCsr0 = 0, Index = 0;
- do {
- RTMP_IO_READ32(pAd, MAC_CSR0, &MacCsr0);
-
- if ((MacCsr0 != 0x00) && (MacCsr0 != 0xFFFFFFFF))
- break;
-
- RTMPusecDelay(10);
- } while (Index++ < 100);
-
- /* Support advanced power save after 2892/2790. */
- /* MAC version at offset 0x1000 is 0x2872XXXX/0x2870XXXX(PCIe, USB, SDIO). */
- if ((MacCsr0 & 0xffff0000) != 0x28600000)
- OPSTATUS_SET_FLAG(pAd, fOP_STATUS_PCIE_DEVICE);
- }
-}
-
-void RTMPInitPCIeLinkCtrlValue(struct rt_rtmp_adapter *pAd)
-{
- int pos;
- u16 reg16, data2, PCIePowerSaveLevel, Configuration;
- u32 MacValue;
- BOOLEAN bFindIntel = FALSE;
- struct os_cookie *pObj;
-
- pObj = (struct os_cookie *)pAd->OS_Cookie;
-
- if (!OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_PCIE_DEVICE))
- return;
-
- DBGPRINT(RT_DEBUG_TRACE, ("%s.===>\n", __func__));
- /* Init EEPROM, and save settings */
- if (!(IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd))) {
- RT28xx_EEPROM_READ16(pAd, 0x22, PCIePowerSaveLevel);
- pAd->PCIePowerSaveLevel = PCIePowerSaveLevel & 0xff;
-
- pAd->LnkCtrlBitMask = 0;
- if ((PCIePowerSaveLevel & 0xff) == 0xff) {
- OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_PCIE_DEVICE);
- DBGPRINT(RT_DEBUG_TRACE,
- ("====> PCIePowerSaveLevel = 0x%x.\n",
- PCIePowerSaveLevel));
- return;
- } else {
- PCIePowerSaveLevel &= 0x3;
- RT28xx_EEPROM_READ16(pAd, 0x24, data2);
-
- if (!
- (((data2 & 0xff00) == 0x9200)
- && ((data2 & 0x80) != 0))) {
- if (PCIePowerSaveLevel > 1)
- PCIePowerSaveLevel = 1;
- }
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("====> Write 0x83 = 0x%x.\n",
- PCIePowerSaveLevel));
- AsicSendCommandToMcu(pAd, 0x83, 0xff,
- (u8)PCIePowerSaveLevel, 0x00);
- RT28xx_EEPROM_READ16(pAd, 0x22, PCIePowerSaveLevel);
- PCIePowerSaveLevel &= 0xff;
- PCIePowerSaveLevel = PCIePowerSaveLevel >> 6;
- switch (PCIePowerSaveLevel) {
- case 0: /* Only support L0 */
- pAd->LnkCtrlBitMask = 0;
- break;
- case 1: /* Only enable L0s */
- pAd->LnkCtrlBitMask = 1;
- break;
- case 2: /* enable L1, L0s */
- pAd->LnkCtrlBitMask = 3;
- break;
- case 3: /* sync with host clk and enable L1, L0s */
- pAd->LnkCtrlBitMask = 0x103;
- break;
- }
- RT28xx_EEPROM_READ16(pAd, 0x24, data2);
- if ((PCIePowerSaveLevel & 0xff) != 0xff) {
- PCIePowerSaveLevel &= 0x3;
-
- if (!
- (((data2 & 0xff00) == 0x9200)
- && ((data2 & 0x80) != 0))) {
- if (PCIePowerSaveLevel > 1)
- PCIePowerSaveLevel = 1;
- }
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("====> rt28xx Write 0x83 Command = 0x%x.\n",
- PCIePowerSaveLevel));
-
- AsicSendCommandToMcu(pAd, 0x83, 0xff,
- (u8)PCIePowerSaveLevel,
- 0x00);
- }
- DBGPRINT(RT_DEBUG_TRACE,
- ("====> LnkCtrlBitMask = 0x%x.\n",
- pAd->LnkCtrlBitMask));
- }
- } else if (IS_RT3090(pAd) || IS_RT3572(pAd) || IS_RT3390(pAd)) {
- u8 LinkCtrlSetting = 0;
-
- /* Check 3090E special setting chip. */
- RT28xx_EEPROM_READ16(pAd, 0x24, data2);
- if ((data2 == 0x9280) && ((pAd->MACVersion & 0xffff) == 0x0211)) {
- pAd->b3090ESpecialChip = TRUE;
- DBGPRINT_RAW(RT_DEBUG_ERROR, ("Special 3090E chip \n"));
- }
-
- RTMP_IO_READ32(pAd, AUX_CTRL, &MacValue);
- /*enable WAKE_PCIE function, which forces to enable PCIE clock when mpu interrupt asserting. */
- /*Force PCIE 125MHz CLK to toggle */
- MacValue |= 0x402;
- RTMP_IO_WRITE32(pAd, AUX_CTRL, MacValue);
- DBGPRINT_RAW(RT_DEBUG_ERROR,
- (" AUX_CTRL = 0x%32x\n", MacValue));
-
- /* for RT30xx F and after, PCIe interface, and for power solution 3 */
- if ((IS_VERSION_AFTER_F(pAd))
- && (pAd->StaCfg.PSControl.field.rt30xxPowerMode >= 2)
- && (pAd->StaCfg.PSControl.field.rt30xxPowerMode <= 3)) {
- RTMP_IO_READ32(pAd, AUX_CTRL, &MacValue);
- DBGPRINT_RAW(RT_DEBUG_ERROR,
- (" Read AUX_CTRL = 0x%x\n", MacValue));
- /* turn on bit 12. */
- /*enable 32KHz clock mode for power saving */
- MacValue |= 0x1000;
- if (MacValue != 0xffffffff) {
- RTMP_IO_WRITE32(pAd, AUX_CTRL, MacValue);
- DBGPRINT_RAW(RT_DEBUG_ERROR,
- (" Write AUX_CTRL = 0x%x\n",
- MacValue));
- /* 1. if use PCIePowerSetting is 2 or 3, need to program OSC_CTRL to 0x3ff11. */
- MacValue = 0x3ff11;
- RTMP_IO_WRITE32(pAd, OSC_CTRL, MacValue);
- DBGPRINT_RAW(RT_DEBUG_ERROR,
- (" OSC_CTRL = 0x%x\n", MacValue));
- /* 2. Write PCI register Clk ref bit */
- RTMPrt3xSetPCIePowerLinkCtrl(pAd);
- } else {
- /* Error read Aux_Ctrl value. Force to use solution 1 */
- DBGPRINT(RT_DEBUG_ERROR,
- (" Error Value in AUX_CTRL = 0x%x\n",
- MacValue));
- pAd->StaCfg.PSControl.field.rt30xxPowerMode = 1;
- DBGPRINT(RT_DEBUG_ERROR,
- (" Force to use power solution1 \n"));
- }
- }
- /* 1. read setting from inf file. */
-
- PCIePowerSaveLevel =
- (u16)pAd->StaCfg.PSControl.field.rt30xxPowerMode;
- DBGPRINT(RT_DEBUG_ERROR,
- ("====> rt30xx Read PowerLevelMode = 0x%x.\n",
- PCIePowerSaveLevel));
- /* 2. Check EnableNewPS. */
- if (pAd->StaCfg.PSControl.field.EnableNewPS == FALSE)
- PCIePowerSaveLevel = 1;
-
- if (IS_VERSION_BEFORE_F(pAd)
- && (pAd->b3090ESpecialChip == FALSE)) {
- /* Chip Version E only allow 1, So force set 1. */
- PCIePowerSaveLevel &= 0x1;
- pAd->PCIePowerSaveLevel = (u16)PCIePowerSaveLevel;
- DBGPRINT(RT_DEBUG_TRACE,
- ("====> rt30xx E Write 0x83 Command = 0x%x.\n",
- PCIePowerSaveLevel));
-
- AsicSendCommandToMcu(pAd, 0x83, 0xff,
- (u8)PCIePowerSaveLevel, 0x00);
- } else {
- /* Chip Version F and after only allow 1 or 2 or 3. This might be modified after new chip version come out. */
- if (!
- ((PCIePowerSaveLevel == 1)
- || (PCIePowerSaveLevel == 3)))
- PCIePowerSaveLevel = 1;
- DBGPRINT(RT_DEBUG_ERROR,
- ("====> rt30xx F Write 0x83 Command = 0x%x.\n",
- PCIePowerSaveLevel));
- pAd->PCIePowerSaveLevel = (u16)PCIePowerSaveLevel;
- /* for 3090F , we need to add high-byte arg for 0x83 command to indicate the link control setting in */
- /* PCI Configuration Space. Because firmware can't read PCI Configuration Space */
- if ((pAd->Rt3xxRalinkLinkCtrl & 0x2)
- && (pAd->Rt3xxHostLinkCtrl & 0x2)) {
- LinkCtrlSetting = 1;
- }
- DBGPRINT(RT_DEBUG_TRACE,
- ("====> rt30xxF LinkCtrlSetting = 0x%x.\n",
- LinkCtrlSetting));
- AsicSendCommandToMcu(pAd, 0x83, 0xff,
- (u8)PCIePowerSaveLevel,
- LinkCtrlSetting);
- }
- }
- /* Find Ralink PCIe Device's Express Capability Offset */
- pos = pci_find_capability(pObj->pci_dev, PCI_CAP_ID_EXP);
-
- if (pos != 0) {
- /* Ralink PCIe Device's Link Control Register Offset */
- pAd->RLnkCtrlOffset = pos + PCI_EXP_LNKCTL;
- pci_read_config_word(pObj->pci_dev, pAd->RLnkCtrlOffset,
- ®16);
- Configuration = le2cpu16(reg16);
- DBGPRINT(RT_DEBUG_TRACE,
- ("Read (Ralink PCIe Link Control Register) offset 0x%x = 0x%x\n",
- pAd->RLnkCtrlOffset, Configuration));
- pAd->RLnkCtrlConfiguration = (Configuration & 0x103);
- Configuration &= 0xfefc;
- Configuration |= (0x0);
-#ifdef RT2860
- if ((pObj->DeviceID == NIC2860_PCIe_DEVICE_ID)
- || (pObj->DeviceID == NIC2790_PCIe_DEVICE_ID)) {
- reg16 = cpu2le16(Configuration);
- pci_write_config_word(pObj->pci_dev,
- pAd->RLnkCtrlOffset, reg16);
- DBGPRINT(RT_DEBUG_TRACE,
- ("Write (Ralink PCIe Link Control Register) offset 0x%x = 0x%x\n",
- pos + PCI_EXP_LNKCTL, Configuration));
- }
-#endif /* RT2860 // */
-
- RTMPFindHostPCIDev(pAd);
- if (pObj->parent_pci_dev) {
- u16 vendor_id;
-
- pci_read_config_word(pObj->parent_pci_dev,
- PCI_VENDOR_ID, &vendor_id);
- vendor_id = le2cpu16(vendor_id);
- if (vendor_id == PCIBUS_INTEL_VENDOR) {
- bFindIntel = TRUE;
- RTMP_SET_PSFLAG(pAd, fRTMP_PS_TOGGLE_L1);
- }
- /* Find PCI-to-PCI Bridge Express Capability Offset */
- pos =
- pci_find_capability(pObj->parent_pci_dev,
- PCI_CAP_ID_EXP);
-
- if (pos != 0) {
- BOOLEAN bChange = FALSE;
- /* PCI-to-PCI Bridge Link Control Register Offset */
- pAd->HostLnkCtrlOffset = pos + PCI_EXP_LNKCTL;
- pci_read_config_word(pObj->parent_pci_dev,
- pAd->HostLnkCtrlOffset,
- ®16);
- Configuration = le2cpu16(reg16);
- DBGPRINT(RT_DEBUG_TRACE,
- ("Read (Host PCI-to-PCI Bridge Link Control Register) offset 0x%x = 0x%x\n",
- pAd->HostLnkCtrlOffset,
- Configuration));
- pAd->HostLnkCtrlConfiguration =
- (Configuration & 0x103);
- Configuration &= 0xfefc;
- Configuration |= (0x0);
-
- switch (pObj->DeviceID) {
-#ifdef RT2860
- case NIC2860_PCIe_DEVICE_ID:
- case NIC2790_PCIe_DEVICE_ID:
- bChange = TRUE;
- break;
-#endif /* RT2860 // */
-#ifdef RT3090
- case NIC3090_PCIe_DEVICE_ID:
- case NIC3091_PCIe_DEVICE_ID:
- case NIC3092_PCIe_DEVICE_ID:
- if (bFindIntel == FALSE)
- bChange = TRUE;
- break;
-#endif /* RT3090 // */
- default:
- break;
- }
-
- if (bChange) {
- reg16 = cpu2le16(Configuration);
- pci_write_config_word(pObj->
- parent_pci_dev,
- pAd->
- HostLnkCtrlOffset,
- reg16);
- DBGPRINT(RT_DEBUG_TRACE,
- ("Write (Host PCI-to-PCI Bridge Link Control Register) offset 0x%x = 0x%x\n",
- pAd->HostLnkCtrlOffset,
- Configuration));
- }
- } else {
- pAd->HostLnkCtrlOffset = 0;
- DBGPRINT(RT_DEBUG_ERROR,
- ("%s: cannot find PCI-to-PCI Bridge PCI Express Capability!\n",
- __func__));
- }
- }
- } else {
- pAd->RLnkCtrlOffset = 0;
- pAd->HostLnkCtrlOffset = 0;
- DBGPRINT(RT_DEBUG_ERROR,
- ("%s: cannot find Ralink PCIe Device's PCI Express Capability!\n",
- __func__));
- }
-
- if (bFindIntel == FALSE) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("Doesn't find Intel PCI host controller. \n"));
- /* Doesn't switch L0, L1, So set PCIePowerSaveLevel to 0xff */
- pAd->PCIePowerSaveLevel = 0xff;
- if ((pAd->RLnkCtrlOffset != 0)
-#ifdef RT3090
- && ((pObj->DeviceID == NIC3090_PCIe_DEVICE_ID)
- || (pObj->DeviceID == NIC3091_PCIe_DEVICE_ID)
- || (pObj->DeviceID == NIC3092_PCIe_DEVICE_ID))
-#endif /* RT3090 // */
- ) {
- pci_read_config_word(pObj->pci_dev, pAd->RLnkCtrlOffset,
- ®16);
- Configuration = le2cpu16(reg16);
- DBGPRINT(RT_DEBUG_TRACE,
- ("Read (Ralink 30xx PCIe Link Control Register) offset 0x%x = 0x%x\n",
- pAd->RLnkCtrlOffset, Configuration));
- pAd->RLnkCtrlConfiguration = (Configuration & 0x103);
- Configuration &= 0xfefc;
- Configuration |= (0x0);
- reg16 = cpu2le16(Configuration);
- pci_write_config_word(pObj->pci_dev,
- pAd->RLnkCtrlOffset, reg16);
- DBGPRINT(RT_DEBUG_TRACE,
- ("Write (Ralink PCIe Link Control Register) offset 0x%x = 0x%x\n",
- pos + PCI_EXP_LNKCTL, Configuration));
- }
- }
-}
-
-void RTMPFindHostPCIDev(struct rt_rtmp_adapter *pAd)
-{
- u16 reg16;
- u8 reg8;
- u32 DevFn;
- struct pci_dev *pPci_dev;
- struct os_cookie *pObj;
-
- pObj = (struct os_cookie *)pAd->OS_Cookie;
-
- if (!OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_PCIE_DEVICE))
- return;
-
- DBGPRINT(RT_DEBUG_TRACE, ("%s.===>\n", __func__));
-
- pObj->parent_pci_dev = NULL;
- if (pObj->pci_dev->bus->parent) {
- for (DevFn = 0; DevFn < 255; DevFn++) {
- pPci_dev =
- pci_get_slot(pObj->pci_dev->bus->parent, DevFn);
- if (pPci_dev) {
- pci_read_config_word(pPci_dev, PCI_CLASS_DEVICE,
- ®16);
- reg16 = le2cpu16(reg16);
- pci_read_config_byte(pPci_dev, PCI_CB_CARD_BUS,
- ®8);
- if ((reg16 == PCI_CLASS_BRIDGE_PCI)
- && (reg8 == pObj->pci_dev->bus->number)) {
- pObj->parent_pci_dev = pPci_dev;
- }
- }
- }
- }
-}
-
-/*
- ========================================================================
-
- Routine Description:
-
- Arguments:
- Level = RESTORE_HALT : Restore PCI host and Ralink PCIe Link Control field to its default value.
- Level = Other Value : Restore from dot11 power save or radio off status. And force PCI host Link Control fields to 0x1
-
- ========================================================================
-*/
-void RTMPPCIeLinkCtrlValueRestore(struct rt_rtmp_adapter *pAd, u8 Level)
-{
- u16 PCIePowerSaveLevel, reg16;
- u16 Configuration;
- struct os_cookie *pObj;
-
- pObj = (struct os_cookie *)pAd->OS_Cookie;
-
- if (!OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_PCIE_DEVICE))
- return;
-
-#ifdef RT2860
- if (!((pObj->DeviceID == NIC2860_PCIe_DEVICE_ID)
- || (pObj->DeviceID == NIC2790_PCIe_DEVICE_ID)))
- return;
-#endif /* RT2860 // */
- /* Check PSControl Configuration */
- if (pAd->StaCfg.PSControl.field.EnableNewPS == FALSE)
- return;
-
- /*3090 will not execute the following codes. */
- /* Check interface : If not PCIe interface, return. */
-
-#ifdef RT3090
- if ((pObj->DeviceID == NIC3090_PCIe_DEVICE_ID)
- || (pObj->DeviceID == NIC3091_PCIe_DEVICE_ID)
- || (pObj->DeviceID == NIC3092_PCIe_DEVICE_ID))
- return;
-#endif /* RT3090 // */
-
- DBGPRINT(RT_DEBUG_TRACE, ("%s.===>\n", __func__));
- PCIePowerSaveLevel = pAd->PCIePowerSaveLevel;
- if ((PCIePowerSaveLevel & 0xff) == 0xff) {
- DBGPRINT(RT_DEBUG_TRACE, ("return \n"));
- return;
- }
-
- if (pObj->parent_pci_dev && (pAd->HostLnkCtrlOffset != 0)) {
- PCI_REG_READ_WORD(pObj->parent_pci_dev, pAd->HostLnkCtrlOffset,
- Configuration);
- if ((Configuration != 0) && (Configuration != 0xFFFF)) {
- Configuration &= 0xfefc;
- /* If call from interface down, restore to original setting. */
- if (Level == RESTORE_CLOSE)
- Configuration |= pAd->HostLnkCtrlConfiguration;
- else
- Configuration |= 0x0;
- PCI_REG_WIRTE_WORD(pObj->parent_pci_dev,
- pAd->HostLnkCtrlOffset,
- Configuration);
- DBGPRINT(RT_DEBUG_TRACE,
- ("Restore PCI host : offset 0x%x = 0x%x\n",
- pAd->HostLnkCtrlOffset, Configuration));
- } else
- DBGPRINT(RT_DEBUG_ERROR,
- ("Restore PCI host : PCI_REG_READ_WORD failed (Configuration = 0x%x)\n",
- Configuration));
- }
-
- if (pObj->pci_dev && (pAd->RLnkCtrlOffset != 0)) {
- PCI_REG_READ_WORD(pObj->pci_dev, pAd->RLnkCtrlOffset,
- Configuration);
- if ((Configuration != 0) && (Configuration != 0xFFFF)) {
- Configuration &= 0xfefc;
- /* If call from interface down, restore to original setting. */
- if (Level == RESTORE_CLOSE)
- Configuration |= pAd->RLnkCtrlConfiguration;
- else
- Configuration |= 0x0;
- PCI_REG_WIRTE_WORD(pObj->pci_dev, pAd->RLnkCtrlOffset,
- Configuration);
- DBGPRINT(RT_DEBUG_TRACE,
- ("Restore Ralink : offset 0x%x = 0x%x\n",
- pAd->RLnkCtrlOffset, Configuration));
- } else
- DBGPRINT(RT_DEBUG_ERROR,
- ("Restore Ralink : PCI_REG_READ_WORD failed (Configuration = 0x%x)\n",
- Configuration));
- }
-
- DBGPRINT(RT_DEBUG_TRACE, ("%s <===\n", __func__));
-}
-
-/*
- ========================================================================
-
- Routine Description:
-
- Arguments:
- Max : limit Host PCI and Ralink PCIe device's LINK CONTROL field's value.
- Because now frequently set our device to mode 1 or mode 3 will cause problem.
-
- ========================================================================
-*/
-void RTMPPCIeLinkCtrlSetting(struct rt_rtmp_adapter *pAd, u16 Max)
-{
- u16 PCIePowerSaveLevel, reg16;
- u16 Configuration;
- struct os_cookie *pObj;
-
- pObj = (struct os_cookie *)pAd->OS_Cookie;
-
- if (!OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_PCIE_DEVICE))
- return;
-
-#ifdef RT2860
- if (!((pObj->DeviceID == NIC2860_PCIe_DEVICE_ID)
- || (pObj->DeviceID == NIC2790_PCIe_DEVICE_ID)))
- return;
-#endif /* RT2860 // */
- /* Check PSControl Configuration */
- if (pAd->StaCfg.PSControl.field.EnableNewPS == FALSE)
- return;
-
- /* Check interface : If not PCIe interface, return. */
- /*Block 3090 to enter the following function */
-
-#ifdef RT3090
- if ((pObj->DeviceID == NIC3090_PCIe_DEVICE_ID)
- || (pObj->DeviceID == NIC3091_PCIe_DEVICE_ID)
- || (pObj->DeviceID == NIC3092_PCIe_DEVICE_ID))
- return;
-#endif /* RT3090 // */
- if (!RTMP_TEST_PSFLAG(pAd, fRTMP_PS_CAN_GO_SLEEP)) {
- DBGPRINT(RT_DEBUG_INFO,
- ("RTMPPCIePowerLinkCtrl return on fRTMP_PS_CAN_GO_SLEEP flag\n"));
- return;
- }
-
- DBGPRINT(RT_DEBUG_TRACE, ("%s===>\n", __func__));
- PCIePowerSaveLevel = pAd->PCIePowerSaveLevel;
- if ((PCIePowerSaveLevel & 0xff) == 0xff) {
- DBGPRINT(RT_DEBUG_TRACE, ("return \n"));
- return;
- }
- PCIePowerSaveLevel = PCIePowerSaveLevel >> 6;
-
- /* Skip non-exist deice right away */
- if (pObj->parent_pci_dev && (pAd->HostLnkCtrlOffset != 0)) {
- PCI_REG_READ_WORD(pObj->parent_pci_dev, pAd->HostLnkCtrlOffset,
- Configuration);
- switch (PCIePowerSaveLevel) {
- case 0:
- /* Set b0 and b1 of LinkControl (both 2892 and PCIe bridge) to 00 */
- Configuration &= 0xfefc;
- break;
- case 1:
- /* Set b0 and b1 of LinkControl (both 2892 and PCIe bridge) to 01 */
- Configuration &= 0xfefc;
- Configuration |= 0x1;
- break;
- case 2:
- /* Set b0 and b1 of LinkControl (both 2892 and PCIe bridge) to 11 */
- Configuration &= 0xfefc;
- Configuration |= 0x3;
- break;
- case 3:
- /* Set b0 and b1 of LinkControl (both 2892 and PCIe bridge) to 11 and bit 8 of LinkControl of 2892 to 1 */
- Configuration &= 0xfefc;
- Configuration |= 0x103;
- break;
- }
- PCI_REG_WIRTE_WORD(pObj->parent_pci_dev, pAd->HostLnkCtrlOffset,
- Configuration);
- DBGPRINT(RT_DEBUG_TRACE,
- ("Write PCI host offset 0x%x = 0x%x\n",
- pAd->HostLnkCtrlOffset, Configuration));
- }
-
- if (pObj->pci_dev && (pAd->RLnkCtrlOffset != 0)) {
- /* first 2892 chip not allow to frequently set mode 3. will cause hang problem. */
- if (PCIePowerSaveLevel > Max)
- PCIePowerSaveLevel = Max;
-
- PCI_REG_READ_WORD(pObj->pci_dev, pAd->RLnkCtrlOffset,
- Configuration);
- switch (PCIePowerSaveLevel) {
- case 0:
- /* No PCI power safe */
- /* Set b0 and b1 of LinkControl (both 2892 and PCIe bridge) to 00 . */
- Configuration &= 0xfefc;
- break;
- case 1:
- /* L0 */
- /* Set b0 and b1 of LinkControl (both 2892 and PCIe bridge) to 01 . */
- Configuration &= 0xfefc;
- Configuration |= 0x1;
- break;
- case 2:
- /* L0 and L1 */
- /* Set b0 and b1 of LinkControl (both 2892 and PCIe bridge) to 11 */
- Configuration &= 0xfefc;
- Configuration |= 0x3;
- break;
- case 3:
- /* L0 , L1 and clock management. */
- /* Set b0 and b1 of LinkControl (both 2892 and PCIe bridge) to 11 and bit 8 of LinkControl of 2892 to 1 */
- Configuration &= 0xfefc;
- Configuration |= 0x103;
- pAd->bPCIclkOff = TRUE;
- break;
- }
- PCI_REG_WIRTE_WORD(pObj->pci_dev, pAd->RLnkCtrlOffset,
- Configuration);
- DBGPRINT(RT_DEBUG_TRACE,
- ("Write Ralink device : offset 0x%x = 0x%x\n",
- pAd->RLnkCtrlOffset, Configuration));
- }
-
- DBGPRINT(RT_DEBUG_TRACE, ("RTMPPCIePowerLinkCtrl <==============\n"));
-}
-
-/*
- ========================================================================
-
- Routine Description:
- 1. Write a PCI register for rt30xx power solution 3
-
- ========================================================================
-*/
-void RTMPrt3xSetPCIePowerLinkCtrl(struct rt_rtmp_adapter *pAd)
-{
-
- unsigned long HostConfiguration = 0;
- unsigned long Configuration;
- struct os_cookie *pObj;
- int pos;
- u16 reg16;
-
- pObj = (struct os_cookie *)pAd->OS_Cookie;
-
- DBGPRINT(RT_DEBUG_INFO,
- ("RTMPrt3xSetPCIePowerLinkCtrl.===> %lx\n",
- pAd->StaCfg.PSControl.word));
-
- /* Check PSControl Configuration */
- if (pAd->StaCfg.PSControl.field.EnableNewPS == FALSE)
- return;
- RTMPFindHostPCIDev(pAd);
- if (pObj->parent_pci_dev) {
- /* Find PCI-to-PCI Bridge Express Capability Offset */
- pos = pci_find_capability(pObj->parent_pci_dev, PCI_CAP_ID_EXP);
-
- if (pos != 0)
- pAd->HostLnkCtrlOffset = pos + PCI_EXP_LNKCTL;
-
- /* If configured to turn on L1. */
- HostConfiguration = 0;
- if (pAd->StaCfg.PSControl.field.rt30xxForceASPMTest == 1) {
- DBGPRINT(RT_DEBUG_TRACE, ("Enter,PSM : Force ASPM\n"));
-
- /* Skip non-exist device right away */
- if ((pAd->HostLnkCtrlOffset != 0)) {
- PCI_REG_READ_WORD(pObj->parent_pci_dev,
- pAd->HostLnkCtrlOffset,
- HostConfiguration);
- /* Prepare Configuration to write to Host */
- HostConfiguration |= 0x3;
- PCI_REG_WIRTE_WORD(pObj->parent_pci_dev,
- pAd->HostLnkCtrlOffset,
- HostConfiguration);
- pAd->Rt3xxHostLinkCtrl = HostConfiguration;
- /* Because in rt30xxForceASPMTest Mode, Force turn on L0s, L1. */
- /* Fix HostConfiguration bit0:1 = 0x3 for later use. */
- HostConfiguration = 0x3;
- DBGPRINT(RT_DEBUG_TRACE,
- ("PSM : Force ASPM : "
- "Host device L1/L0s Value = 0x%lx\n",
- HostConfiguration));
- }
- } else if (pAd->StaCfg.PSControl.field.rt30xxFollowHostASPM ==
- 1) {
-
- /* Skip non-exist deice right away */
- if ((pAd->HostLnkCtrlOffset != 0)) {
- PCI_REG_READ_WORD(pObj->parent_pci_dev,
- pAd->HostLnkCtrlOffset,
- HostConfiguration);
- pAd->Rt3xxHostLinkCtrl = HostConfiguration;
- HostConfiguration &= 0x3;
- DBGPRINT(RT_DEBUG_TRACE,
- ("PSM : Follow Host ASPM : "
- "Host device L1/L0s Value = 0x%lx\n",
- HostConfiguration));
- }
- }
- }
- /* Prepare to write Ralink setting. */
- /* Find Ralink PCIe Device's Express Capability Offset */
- pos = pci_find_capability(pObj->pci_dev, PCI_CAP_ID_EXP);
-
- if (pos != 0) {
- /* Ralink PCIe Device's Link Control Register Offset */
- pAd->RLnkCtrlOffset = pos + PCI_EXP_LNKCTL;
- pci_read_config_word(pObj->pci_dev, pAd->RLnkCtrlOffset,
- ®16);
- Configuration = le2cpu16(reg16);
- DBGPRINT(RT_DEBUG_TRACE,
- ("Read (Ralink PCIe Link Control Register) "
- "offset 0x%x = 0x%lx\n",
- pAd->RLnkCtrlOffset, Configuration));
- Configuration |= 0x100;
- if ((pAd->StaCfg.PSControl.field.rt30xxFollowHostASPM == 1)
- || (pAd->StaCfg.PSControl.field.rt30xxForceASPMTest == 1)) {
- switch (HostConfiguration) {
- case 0:
- Configuration &= 0xffffffc;
- break;
- case 1:
- Configuration &= 0xffffffc;
- Configuration |= 0x1;
- break;
- case 2:
- Configuration &= 0xffffffc;
- Configuration |= 0x2;
- break;
- case 3:
- Configuration |= 0x3;
- break;
- }
- }
- reg16 = cpu2le16(Configuration);
- pci_write_config_word(pObj->pci_dev, pAd->RLnkCtrlOffset,
- reg16);
- pAd->Rt3xxRalinkLinkCtrl = Configuration;
- DBGPRINT(RT_DEBUG_TRACE,
- ("PSM :Write Ralink device L1/L0s Value = 0x%lx\n",
- Configuration));
- }
- DBGPRINT(RT_DEBUG_INFO,
- ("PSM :RTMPrt3xSetPCIePowerLinkCtrl <==============\n"));
-}
diff --git a/drivers/staging/rt2860/rt_config.h b/drivers/staging/rt2860/rt_config.h
deleted file mode 100644
index d1adef8..0000000
--- a/drivers/staging/rt2860/rt_config.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- rt_config.h
-
- Abstract:
- Central header file to maintain all include files for all NDIS
- miniport driver routines.
-
- Revision History:
- Who When What
- -------- ---------- ----------------------------------------------
- Paul Lin 08-01-2002 created
-
-*/
-#ifndef __RT_CONFIG_H__
-#define __RT_CONFIG_H__
-
-#include "rtmp_type.h"
-#include "rtmp_os.h"
-
-#include "rtmp_def.h"
-#include "rtmp_chip.h"
-#include "rtmp_timer.h"
-
-#include "oid.h"
-#include "mlme.h"
-#include "wpa.h"
-#include "crypt_md5.h"
-#include "crypt_sha2.h"
-#include "crypt_hmac.h"
-#include "rtmp.h"
-#include "ap.h"
-#include "dfs.h"
-#include "chlist.h"
-#include "spectrum.h"
-
-#include "eeprom.h"
-#if defined(RTMP_PCI_SUPPORT) || defined(RTMP_USB_SUPPORT)
-#include "rtmp_mcu.h"
-#endif
-
-#ifdef IGMP_SNOOP_SUPPORT
-#include "igmp_snoop.h"
-#endif /* IGMP_SNOOP_SUPPORT // */
-
-#endif /* __RT_CONFIG_H__ */
diff --git a/drivers/staging/rt2860/rt_linux.c b/drivers/staging/rt2860/rt_linux.c
deleted file mode 100644
index 1583347..0000000
--- a/drivers/staging/rt2860/rt_linux.c
+++ /dev/null
@@ -1,1367 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
- */
-
-#include <linux/firmware.h>
-#include <linux/sched.h>
-#include <linux/slab.h>
-#include "rt_config.h"
-
-unsigned long RTDebugLevel = RT_DEBUG_ERROR;
-
-/* for wireless system event message */
-char const *pWirelessSysEventText[IW_SYS_EVENT_TYPE_NUM] = {
- /* system status event */
- "had associated successfully", /* IW_ASSOC_EVENT_FLAG */
- "had disassociated", /* IW_DISASSOC_EVENT_FLAG */
- "had deauthenticated", /* IW_DEAUTH_EVENT_FLAG */
- "had been aged-out and disassociated", /* IW_AGEOUT_EVENT_FLAG */
- "occurred CounterMeasures attack", /* IW_COUNTER_MEASURES_EVENT_FLAG */
- "occurred replay counter different in Key Handshaking", /* IW_REPLAY_COUNTER_DIFF_EVENT_FLAG */
- "occurred RSNIE different in Key Handshaking", /* IW_RSNIE_DIFF_EVENT_FLAG */
- "occurred MIC different in Key Handshaking", /* IW_MIC_DIFF_EVENT_FLAG */
- "occurred ICV error in RX", /* IW_ICV_ERROR_EVENT_FLAG */
- "occurred MIC error in RX", /* IW_MIC_ERROR_EVENT_FLAG */
- "Group Key Handshaking timeout", /* IW_GROUP_HS_TIMEOUT_EVENT_FLAG */
- "Pairwise Key Handshaking timeout", /* IW_PAIRWISE_HS_TIMEOUT_EVENT_FLAG */
- "RSN IE sanity check failure", /* IW_RSNIE_SANITY_FAIL_EVENT_FLAG */
- "set key done in WPA/WPAPSK", /* IW_SET_KEY_DONE_WPA1_EVENT_FLAG */
- "set key done in WPA2/WPA2PSK", /* IW_SET_KEY_DONE_WPA2_EVENT_FLAG */
- "connects with our wireless client", /* IW_STA_LINKUP_EVENT_FLAG */
- "disconnects with our wireless client", /* IW_STA_LINKDOWN_EVENT_FLAG */
- "scan completed" /* IW_SCAN_COMPLETED_EVENT_FLAG */
- "scan terminate! Busy! Enqueue fail!" /* IW_SCAN_ENQUEUE_FAIL_EVENT_FLAG */
-};
-
-/* for wireless IDS_spoof_attack event message */
-char const *pWirelessSpoofEventText[IW_SPOOF_EVENT_TYPE_NUM] = {
- "detected conflict SSID", /* IW_CONFLICT_SSID_EVENT_FLAG */
- "detected spoofed association response", /* IW_SPOOF_ASSOC_RESP_EVENT_FLAG */
- "detected spoofed reassociation responses", /* IW_SPOOF_REASSOC_RESP_EVENT_FLAG */
- "detected spoofed probe response", /* IW_SPOOF_PROBE_RESP_EVENT_FLAG */
- "detected spoofed beacon", /* IW_SPOOF_BEACON_EVENT_FLAG */
- "detected spoofed disassociation", /* IW_SPOOF_DISASSOC_EVENT_FLAG */
- "detected spoofed authentication", /* IW_SPOOF_AUTH_EVENT_FLAG */
- "detected spoofed deauthentication", /* IW_SPOOF_DEAUTH_EVENT_FLAG */
- "detected spoofed unknown management frame", /* IW_SPOOF_UNKNOWN_MGMT_EVENT_FLAG */
- "detected replay attack" /* IW_REPLAY_ATTACK_EVENT_FLAG */
-};
-
-/* for wireless IDS_flooding_attack event message */
-char const *pWirelessFloodEventText[IW_FLOOD_EVENT_TYPE_NUM] = {
- "detected authentication flooding", /* IW_FLOOD_AUTH_EVENT_FLAG */
- "detected association request flooding", /* IW_FLOOD_ASSOC_REQ_EVENT_FLAG */
- "detected reassociation request flooding", /* IW_FLOOD_REASSOC_REQ_EVENT_FLAG */
- "detected probe request flooding", /* IW_FLOOD_PROBE_REQ_EVENT_FLAG */
- "detected disassociation flooding", /* IW_FLOOD_DISASSOC_EVENT_FLAG */
- "detected deauthentication flooding", /* IW_FLOOD_DEAUTH_EVENT_FLAG */
- "detected 802.1x eap-request flooding" /* IW_FLOOD_EAP_REQ_EVENT_FLAG */
-};
-
-/* timeout -- ms */
-void RTMP_SetPeriodicTimer(struct timer_list *pTimer,
- IN unsigned long timeout)
-{
- timeout = ((timeout * OS_HZ) / 1000);
- pTimer->expires = jiffies + timeout;
- add_timer(pTimer);
-}
-
-/* convert NdisMInitializeTimer --> RTMP_OS_Init_Timer */
-void RTMP_OS_Init_Timer(struct rt_rtmp_adapter *pAd,
- struct timer_list *pTimer,
- IN TIMER_FUNCTION function, void *data)
-{
- init_timer(pTimer);
- pTimer->data = (unsigned long)data;
- pTimer->function = function;
-}
-
-void RTMP_OS_Add_Timer(struct timer_list *pTimer,
- IN unsigned long timeout)
-{
- if (timer_pending(pTimer))
- return;
-
- timeout = ((timeout * OS_HZ) / 1000);
- pTimer->expires = jiffies + timeout;
- add_timer(pTimer);
-}
-
-void RTMP_OS_Mod_Timer(struct timer_list *pTimer,
- IN unsigned long timeout)
-{
- timeout = ((timeout * OS_HZ) / 1000);
- mod_timer(pTimer, jiffies + timeout);
-}
-
-void RTMP_OS_Del_Timer(struct timer_list *pTimer, OUT BOOLEAN *pCancelled)
-{
- if (timer_pending(pTimer)) {
- *pCancelled = del_timer_sync(pTimer);
- } else {
- *pCancelled = TRUE;
- }
-
-}
-
-void RTMP_OS_Release_Packet(struct rt_rtmp_adapter *pAd, struct rt_queue_entry *pEntry)
-{
- /*RTMPFreeNdisPacket(pAd, (struct sk_buff *)pEntry); */
-}
-
-/* Unify all delay routine by using udelay */
-void RTMPusecDelay(unsigned long usec)
-{
- unsigned long i;
-
- for (i = 0; i < (usec / 50); i++)
- udelay(50);
-
- if (usec % 50)
- udelay(usec % 50);
-}
-
-void RTMP_GetCurrentSystemTime(LARGE_INTEGER *time)
-{
- time->u.LowPart = jiffies;
-}
-
-/* pAd MUST allow to be NULL */
-int os_alloc_mem(struct rt_rtmp_adapter *pAd, u8 ** mem, unsigned long size)
-{
- *mem = kmalloc(size, GFP_ATOMIC);
- if (*mem)
- return NDIS_STATUS_SUCCESS;
- else
- return NDIS_STATUS_FAILURE;
-}
-
-/* pAd MUST allow to be NULL */
-int os_free_mem(struct rt_rtmp_adapter *pAd, void *mem)
-{
-
- ASSERT(mem);
- kfree(mem);
- return NDIS_STATUS_SUCCESS;
-}
-
-void *RtmpOSNetPktAlloc(struct rt_rtmp_adapter *pAd, IN int size)
-{
- struct sk_buff *skb;
- /* Add 2 more bytes for ip header alignment */
- skb = dev_alloc_skb(size + 2);
-
- return (void *)skb;
-}
-
-void *RTMP_AllocateFragPacketBuffer(struct rt_rtmp_adapter *pAd,
- unsigned long Length)
-{
- struct sk_buff *pkt;
-
- pkt = dev_alloc_skb(Length);
-
- if (pkt == NULL) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("can't allocate frag rx %ld size packet\n", Length));
- }
-
- if (pkt) {
- RTMP_SET_PACKET_SOURCE(OSPKT_TO_RTPKT(pkt), PKTSRC_NDIS);
- }
-
- return (void *)pkt;
-}
-
-void *RTMP_AllocateTxPacketBuffer(struct rt_rtmp_adapter *pAd,
- unsigned long Length,
- IN BOOLEAN Cached,
- void **VirtualAddress)
-{
- struct sk_buff *pkt;
-
- pkt = dev_alloc_skb(Length);
-
- if (pkt == NULL) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("can't allocate tx %ld size packet\n", Length));
- }
-
- if (pkt) {
- RTMP_SET_PACKET_SOURCE(OSPKT_TO_RTPKT(pkt), PKTSRC_NDIS);
- *VirtualAddress = (void *)pkt->data;
- } else {
- *VirtualAddress = (void *)NULL;
- }
-
- return (void *)pkt;
-}
-
-void build_tx_packet(struct rt_rtmp_adapter *pAd,
- void *pPacket,
- u8 *pFrame, unsigned long FrameLen)
-{
-
- struct sk_buff *pTxPkt;
-
- ASSERT(pPacket);
- pTxPkt = RTPKT_TO_OSPKT(pPacket);
-
- NdisMoveMemory(skb_put(pTxPkt, FrameLen), pFrame, FrameLen);
-}
-
-void RTMPFreeAdapter(struct rt_rtmp_adapter *pAd)
-{
- struct os_cookie *os_cookie;
- int index;
-
- os_cookie = (struct os_cookie *)pAd->OS_Cookie;
-
- kfree(pAd->BeaconBuf);
-
- NdisFreeSpinLock(&pAd->MgmtRingLock);
-
-#ifdef RTMP_MAC_PCI
- NdisFreeSpinLock(&pAd->RxRingLock);
-#ifdef RT3090
- NdisFreeSpinLock(&pAd->McuCmdLock);
-#endif /* RT3090 // */
-#endif /* RTMP_MAC_PCI // */
-
- for (index = 0; index < NUM_OF_TX_RING; index++) {
- NdisFreeSpinLock(&pAd->TxSwQueueLock[index]);
- NdisFreeSpinLock(&pAd->DeQueueLock[index]);
- pAd->DeQueueRunning[index] = FALSE;
- }
-
- NdisFreeSpinLock(&pAd->irq_lock);
-
- release_firmware(pAd->firmware);
-
- vfree(pAd); /* pci_free_consistent(os_cookie->pci_dev,sizeof(struct rt_rtmp_adapter),pAd,os_cookie->pAd_pa); */
- kfree(os_cookie);
-}
-
-BOOLEAN OS_Need_Clone_Packet(void)
-{
- return FALSE;
-}
-
-/*
- ========================================================================
-
- Routine Description:
- clone an input NDIS PACKET to another one. The new internally created NDIS PACKET
- must have only one NDIS BUFFER
- return - byte copied. 0 means can't create NDIS PACKET
- NOTE: internally created char should be destroyed by RTMPFreeNdisPacket
-
- Arguments:
- pAd Pointer to our adapter
- pInsAMSDUHdr EWC A-MSDU format has extra 14-bytes header. if TRUE, insert this 14-byte hdr in front of MSDU.
- *pSrcTotalLen return total packet length. This length is calculated with 802.3 format packet.
-
- Return Value:
- NDIS_STATUS_SUCCESS
- NDIS_STATUS_FAILURE
-
- Note:
-
- ========================================================================
-*/
-int RTMPCloneNdisPacket(struct rt_rtmp_adapter *pAd,
- IN BOOLEAN pInsAMSDUHdr,
- void *pInPacket,
- void **ppOutPacket)
-{
-
- struct sk_buff *pkt;
-
- ASSERT(pInPacket);
- ASSERT(ppOutPacket);
-
- /* 1. Allocate a packet */
- pkt = dev_alloc_skb(2048);
-
- if (pkt == NULL) {
- return NDIS_STATUS_FAILURE;
- }
-
- skb_put(pkt, GET_OS_PKT_LEN(pInPacket));
- NdisMoveMemory(pkt->data, GET_OS_PKT_DATAPTR(pInPacket),
- GET_OS_PKT_LEN(pInPacket));
- *ppOutPacket = OSPKT_TO_RTPKT(pkt);
-
- RTMP_SET_PACKET_SOURCE(OSPKT_TO_RTPKT(pkt), PKTSRC_NDIS);
-
- printk(KERN_DEBUG "###Clone###\n");
-
- return NDIS_STATUS_SUCCESS;
-}
-
-/* the allocated NDIS PACKET must be freed via RTMPFreeNdisPacket() */
-int RTMPAllocateNdisPacket(struct rt_rtmp_adapter *pAd,
- void **ppPacket,
- u8 *pHeader,
- u32 HeaderLen,
- u8 *pData, u32 DataLen)
-{
- void *pPacket;
- ASSERT(pData);
- ASSERT(DataLen);
-
- /* 1. Allocate a packet */
- pPacket =
- (void **) dev_alloc_skb(HeaderLen + DataLen +
- RTMP_PKT_TAIL_PADDING);
- if (pPacket == NULL) {
- *ppPacket = NULL;
- pr_devel("RTMPAllocateNdisPacket Fail\n");
-
- return NDIS_STATUS_FAILURE;
- }
- /* 2. clone the frame content */
- if (HeaderLen > 0)
- NdisMoveMemory(GET_OS_PKT_DATAPTR(pPacket), pHeader, HeaderLen);
- if (DataLen > 0)
- NdisMoveMemory(GET_OS_PKT_DATAPTR(pPacket) + HeaderLen, pData,
- DataLen);
-
- /* 3. update length of packet */
- skb_put(GET_OS_PKT_TYPE(pPacket), HeaderLen + DataLen);
-
- RTMP_SET_PACKET_SOURCE(pPacket, PKTSRC_NDIS);
-/* printk("%s : pPacket = %p, len = %d\n", __func__, pPacket, GET_OS_PKT_LEN(pPacket)); */
- *ppPacket = pPacket;
- return NDIS_STATUS_SUCCESS;
-}
-
-/*
- ========================================================================
- Description:
- This routine frees a miniport internally allocated char and its
- corresponding NDIS_BUFFER and allocated memory.
- ========================================================================
-*/
-void RTMPFreeNdisPacket(struct rt_rtmp_adapter *pAd, void *pPacket)
-{
- dev_kfree_skb_any(RTPKT_TO_OSPKT(pPacket));
-}
-
-/* IRQL = DISPATCH_LEVEL */
-/* NOTE: we do have an assumption here, that Byte0 and Byte1 always reasid at the same */
-/* scatter gather buffer */
-int Sniff2BytesFromNdisBuffer(char *pFirstBuffer,
- u8 DesiredOffset,
- u8 *pByte0, u8 *pByte1)
-{
- *pByte0 = *(u8 *)(pFirstBuffer + DesiredOffset);
- *pByte1 = *(u8 *)(pFirstBuffer + DesiredOffset + 1);
-
- return NDIS_STATUS_SUCCESS;
-}
-
-void RTMP_QueryPacketInfo(void *pPacket,
- struct rt_packet_info *pPacketInfo,
- u8 **pSrcBufVA, u32 * pSrcBufLen)
-{
- pPacketInfo->BufferCount = 1;
- pPacketInfo->pFirstBuffer = (char *)GET_OS_PKT_DATAPTR(pPacket);
- pPacketInfo->PhysicalBufferCount = 1;
- pPacketInfo->TotalPacketLength = GET_OS_PKT_LEN(pPacket);
-
- *pSrcBufVA = GET_OS_PKT_DATAPTR(pPacket);
- *pSrcBufLen = GET_OS_PKT_LEN(pPacket);
-}
-
-void RTMP_QueryNextPacketInfo(void **ppPacket,
- struct rt_packet_info *pPacketInfo,
- u8 **pSrcBufVA, u32 * pSrcBufLen)
-{
- void *pPacket = NULL;
-
- if (*ppPacket)
- pPacket = GET_OS_PKT_NEXT(*ppPacket);
-
- if (pPacket) {
- pPacketInfo->BufferCount = 1;
- pPacketInfo->pFirstBuffer =
- (char *)GET_OS_PKT_DATAPTR(pPacket);
- pPacketInfo->PhysicalBufferCount = 1;
- pPacketInfo->TotalPacketLength = GET_OS_PKT_LEN(pPacket);
-
- *pSrcBufVA = GET_OS_PKT_DATAPTR(pPacket);
- *pSrcBufLen = GET_OS_PKT_LEN(pPacket);
- *ppPacket = GET_OS_PKT_NEXT(pPacket);
- } else {
- pPacketInfo->BufferCount = 0;
- pPacketInfo->pFirstBuffer = NULL;
- pPacketInfo->PhysicalBufferCount = 0;
- pPacketInfo->TotalPacketLength = 0;
-
- *pSrcBufVA = NULL;
- *pSrcBufLen = 0;
- *ppPacket = NULL;
- }
-}
-
-void *DuplicatePacket(struct rt_rtmp_adapter *pAd,
- void *pPacket, u8 FromWhichBSSID)
-{
- struct sk_buff *skb;
- void *pRetPacket = NULL;
- u16 DataSize;
- u8 *pData;
-
- DataSize = (u16)GET_OS_PKT_LEN(pPacket);
- pData = (u8 *)GET_OS_PKT_DATAPTR(pPacket);
-
- skb = skb_clone(RTPKT_TO_OSPKT(pPacket), MEM_ALLOC_FLAG);
- if (skb) {
- skb->dev = get_netdev_from_bssid(pAd, FromWhichBSSID);
- pRetPacket = OSPKT_TO_RTPKT(skb);
- }
-
- return pRetPacket;
-
-}
-
-void *duplicate_pkt(struct rt_rtmp_adapter *pAd,
- u8 *pHeader802_3,
- u32 HdrLen,
- u8 *pData,
- unsigned long DataSize, u8 FromWhichBSSID)
-{
- struct sk_buff *skb;
- void *pPacket = NULL;
-
- skb = __dev_alloc_skb(HdrLen + DataSize + 2, MEM_ALLOC_FLAG);
- if (skb != NULL) {
- skb_reserve(skb, 2);
- NdisMoveMemory(skb_tail_pointer(skb), pHeader802_3, HdrLen);
- skb_put(skb, HdrLen);
- NdisMoveMemory(skb_tail_pointer(skb), pData, DataSize);
- skb_put(skb, DataSize);
- skb->dev = get_netdev_from_bssid(pAd, FromWhichBSSID);
- pPacket = OSPKT_TO_RTPKT(skb);
- }
-
- return pPacket;
-}
-
-#define TKIP_TX_MIC_SIZE 8
-void *duplicate_pkt_with_TKIP_MIC(struct rt_rtmp_adapter *pAd,
- void *pPacket)
-{
- struct sk_buff *skb, *newskb;
-
- skb = RTPKT_TO_OSPKT(pPacket);
- if (skb_tailroom(skb) < TKIP_TX_MIC_SIZE) {
- /* alloc a new skb and copy the packet */
- newskb =
- skb_copy_expand(skb, skb_headroom(skb), TKIP_TX_MIC_SIZE,
- GFP_ATOMIC);
- dev_kfree_skb_any(skb);
- if (newskb == NULL) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("Extend Tx.MIC for packet failed!, dropping packet!\n"));
- return NULL;
- }
- skb = newskb;
- }
-
- return OSPKT_TO_RTPKT(skb);
-}
-
-void *ClonePacket(struct rt_rtmp_adapter *pAd,
- void *pPacket,
- u8 *pData, unsigned long DataSize)
-{
- struct sk_buff *pRxPkt;
- struct sk_buff *pClonedPkt;
-
- ASSERT(pPacket);
- pRxPkt = RTPKT_TO_OSPKT(pPacket);
-
- /* clone the packet */
- pClonedPkt = skb_clone(pRxPkt, MEM_ALLOC_FLAG);
-
- if (pClonedPkt) {
- /* set the correct dataptr and data len */
- pClonedPkt->dev = pRxPkt->dev;
- pClonedPkt->data = pData;
- pClonedPkt->len = DataSize;
- skb_set_tail_pointer(pClonedPkt, DataSize)
- ASSERT(DataSize < 1530);
- }
- return pClonedPkt;
-}
-
-/* */
-/* change OS packet DataPtr and DataLen */
-/* */
-void update_os_packet_info(struct rt_rtmp_adapter *pAd,
- struct rt_rx_blk *pRxBlk, u8 FromWhichBSSID)
-{
- struct sk_buff *pOSPkt;
-
- ASSERT(pRxBlk->pRxPacket);
- pOSPkt = RTPKT_TO_OSPKT(pRxBlk->pRxPacket);
-
- pOSPkt->dev = get_netdev_from_bssid(pAd, FromWhichBSSID);
- pOSPkt->data = pRxBlk->pData;
- pOSPkt->len = pRxBlk->DataSize;
- skb_set_tail_pointer(pOSPkt, pOSPkt->len);
-}
-
-void wlan_802_11_to_802_3_packet(struct rt_rtmp_adapter *pAd,
- struct rt_rx_blk *pRxBlk,
- u8 *pHeader802_3,
- u8 FromWhichBSSID)
-{
- struct sk_buff *pOSPkt;
-
- ASSERT(pRxBlk->pRxPacket);
- ASSERT(pHeader802_3);
-
- pOSPkt = RTPKT_TO_OSPKT(pRxBlk->pRxPacket);
-
- pOSPkt->dev = get_netdev_from_bssid(pAd, FromWhichBSSID);
- pOSPkt->data = pRxBlk->pData;
- pOSPkt->len = pRxBlk->DataSize;
- skb_set_tail_pointer(pOSPkt, pOSPkt->len);
-
- /* */
- /* copy 802.3 header */
- /* */
- /* */
-
- NdisMoveMemory(skb_push(pOSPkt, LENGTH_802_3), pHeader802_3,
- LENGTH_802_3);
-}
-
-void announce_802_3_packet(struct rt_rtmp_adapter *pAd, void *pPacket)
-{
-
- struct sk_buff *pRxPkt;
-
- ASSERT(pPacket);
-
- pRxPkt = RTPKT_TO_OSPKT(pPacket);
-
- /* Push up the protocol stack */
- pRxPkt->protocol = eth_type_trans(pRxPkt, pRxPkt->dev);
-
- netif_rx(pRxPkt);
-}
-
-struct rt_rtmp_sg_list *
-rt_get_sg_list_from_packet(void *pPacket, struct rt_rtmp_sg_list *sg)
-{
- sg->NumberOfElements = 1;
- sg->Elements[0].Address = GET_OS_PKT_DATAPTR(pPacket);
- sg->Elements[0].Length = GET_OS_PKT_LEN(pPacket);
- return sg;
-}
-
-void hex_dump(char *str, unsigned char *pSrcBufVA, unsigned int SrcBufLen)
-{
- unsigned char *pt;
- int x;
-
- if (RTDebugLevel < RT_DEBUG_TRACE)
- return;
-
- pt = pSrcBufVA;
- printk(KERN_DEBUG "%s: %p, len = %d\n", str, pSrcBufVA, SrcBufLen);
- for (x = 0; x < SrcBufLen; x++) {
- if (x % 16 == 0)
- printk(KERN_DEBUG "0x%04x : ", x);
- printk(KERN_DEBUG "%02x ", ((unsigned char)pt[x]));
- if (x % 16 == 15)
- printk(KERN_DEBUG "\n");
- }
- printk(KERN_DEBUG "\n");
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Send log message through wireless event
-
- Support standard iw_event with IWEVCUSTOM. It is used below.
-
- iwreq_data.data.flags is used to store event_flag that is defined by user.
- iwreq_data.data.length is the length of the event log.
-
- The format of the event log is composed of the entry's MAC address and
- the desired log message (refer to pWirelessEventText).
-
- ex: 11:22:33:44:55:66 has associated successfully
-
- p.s. The requirement of Wireless Extension is v15 or newer.
-
- ========================================================================
-*/
-void RTMPSendWirelessEvent(struct rt_rtmp_adapter *pAd,
- u16 Event_flag,
- u8 *pAddr, u8 BssIdx, char Rssi)
-{
-
- /*union iwreq_data wrqu; */
- char *pBuf = NULL, *pBufPtr = NULL;
- u16 event, type, BufLen;
- u8 event_table_len = 0;
-
- type = Event_flag & 0xFF00;
- event = Event_flag & 0x00FF;
-
- switch (type) {
- case IW_SYS_EVENT_FLAG_START:
- event_table_len = IW_SYS_EVENT_TYPE_NUM;
- break;
-
- case IW_SPOOF_EVENT_FLAG_START:
- event_table_len = IW_SPOOF_EVENT_TYPE_NUM;
- break;
-
- case IW_FLOOD_EVENT_FLAG_START:
- event_table_len = IW_FLOOD_EVENT_TYPE_NUM;
- break;
- }
-
- if (event_table_len == 0) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("%s : The type(%0x02x) is not valid.\n", __func__,
- type));
- return;
- }
-
- if (event >= event_table_len) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("%s : The event(%0x02x) is not valid.\n", __func__,
- event));
- return;
- }
- /*Allocate memory and copy the msg. */
- pBuf = kmalloc(IW_CUSTOM_MAX_LEN, GFP_ATOMIC);
- if (pBuf != NULL) {
- /*Prepare the payload */
- memset(pBuf, 0, IW_CUSTOM_MAX_LEN);
-
- pBufPtr = pBuf;
-
- if (pAddr)
- pBufPtr +=
- sprintf(pBufPtr, "(RT2860) STA(%pM) ", pAddr);
- else if (BssIdx < MAX_MBSSID_NUM)
- pBufPtr +=
- sprintf(pBufPtr, "(RT2860) BSS(wlan%d) ", BssIdx);
- else
- pBufPtr += sprintf(pBufPtr, "(RT2860) ");
-
- if (type == IW_SYS_EVENT_FLAG_START)
- pBufPtr +=
- sprintf(pBufPtr, "%s",
- pWirelessSysEventText[event]);
- else if (type == IW_SPOOF_EVENT_FLAG_START)
- pBufPtr +=
- sprintf(pBufPtr, "%s (RSSI=%d)",
- pWirelessSpoofEventText[event], Rssi);
- else if (type == IW_FLOOD_EVENT_FLAG_START)
- pBufPtr +=
- sprintf(pBufPtr, "%s",
- pWirelessFloodEventText[event]);
- else
- pBufPtr += sprintf(pBufPtr, "%s", "unknown event");
-
- pBufPtr[pBufPtr - pBuf] = '\0';
- BufLen = pBufPtr - pBuf;
-
- RtmpOSWrielessEventSend(pAd, IWEVCUSTOM, Event_flag, NULL,
- (u8 *)pBuf, BufLen);
- /*DBGPRINT(RT_DEBUG_TRACE, ("%s : %s\n", __func__, pBuf)); */
-
- kfree(pBuf);
- } else
- DBGPRINT(RT_DEBUG_ERROR,
- ("%s : Can't allocate memory for wireless event.\n",
- __func__));
-}
-
-void send_monitor_packets(struct rt_rtmp_adapter *pAd, struct rt_rx_blk *pRxBlk)
-{
- struct sk_buff *pOSPkt;
- struct rt_wlan_ng_prism2_header *ph;
- int rate_index = 0;
- u16 header_len = 0;
- u8 temp_header[40] = { 0 };
-
- u_int32_t ralinkrate[256] = { 2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108, 109, 110, 111, 112, 13, 26, 39, 52, 78, 104, 117, 130, 26, 52, 78, 104, 156, 208, 234, 260, 27, 54, 81, 108, 162, 216, 243, 270, /* Last 38 */
- 54, 108, 162, 216, 324, 432, 486, 540, 14, 29, 43, 57, 87, 115,
- 130, 144, 29, 59, 87, 115, 173, 230, 260, 288, 30, 60, 90,
- 120, 180, 240, 270, 300, 60, 120, 180, 240, 360, 480, 540,
- 600, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
- 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26,
- 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41,
- 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56,
- 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71,
- 72, 73, 74, 75, 76, 77, 78, 79, 80
- };
-
- ASSERT(pRxBlk->pRxPacket);
- if (pRxBlk->DataSize < 10) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("%s : Size is too small! (%d)\n", __func__,
- pRxBlk->DataSize));
- goto err_free_sk_buff;
- }
-
- if (pRxBlk->DataSize + sizeof(struct rt_wlan_ng_prism2_header) >
- RX_BUFFER_AGGRESIZE) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("%s : Size is too large! (%zu)\n", __func__,
- pRxBlk->DataSize + sizeof(struct rt_wlan_ng_prism2_header)));
- goto err_free_sk_buff;
- }
-
- pOSPkt = RTPKT_TO_OSPKT(pRxBlk->pRxPacket);
- pOSPkt->dev = get_netdev_from_bssid(pAd, BSS0);
- if (pRxBlk->pHeader->FC.Type == BTYPE_DATA) {
- pRxBlk->DataSize -= LENGTH_802_11;
- if ((pRxBlk->pHeader->FC.ToDs == 1) &&
- (pRxBlk->pHeader->FC.FrDs == 1))
- header_len = LENGTH_802_11_WITH_ADDR4;
- else
- header_len = LENGTH_802_11;
-
- /* QOS */
- if (pRxBlk->pHeader->FC.SubType & 0x08) {
- header_len += 2;
- /* Data skip QOS control field */
- pRxBlk->DataSize -= 2;
- }
- /* Order bit: A-Ralink or HTC+ */
- if (pRxBlk->pHeader->FC.Order) {
- header_len += 4;
- /* Data skip HTC control field */
- pRxBlk->DataSize -= 4;
- }
- /* Copy Header */
- if (header_len <= 40)
- NdisMoveMemory(temp_header, pRxBlk->pData, header_len);
-
- /* skip HW padding */
- if (pRxBlk->RxD.L2PAD)
- pRxBlk->pData += (header_len + 2);
- else
- pRxBlk->pData += header_len;
- } /*end if */
-
- if (pRxBlk->DataSize < pOSPkt->len) {
- skb_trim(pOSPkt, pRxBlk->DataSize);
- } else {
- skb_put(pOSPkt, (pRxBlk->DataSize - pOSPkt->len));
- } /*end if */
-
- if ((pRxBlk->pData - pOSPkt->data) > 0) {
- skb_put(pOSPkt, (pRxBlk->pData - pOSPkt->data));
- skb_pull(pOSPkt, (pRxBlk->pData - pOSPkt->data));
- } /*end if */
-
- if (skb_headroom(pOSPkt) < (sizeof(struct rt_wlan_ng_prism2_header) + header_len)) {
- if (pskb_expand_head
- (pOSPkt, (sizeof(struct rt_wlan_ng_prism2_header) + header_len), 0,
- GFP_ATOMIC)) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("%s : Reallocate header size of sk_buff fail!\n",
- __func__));
- goto err_free_sk_buff;
- } /*end if */
- } /*end if */
-
- if (header_len > 0)
- NdisMoveMemory(skb_push(pOSPkt, header_len), temp_header,
- header_len);
-
- ph = (struct rt_wlan_ng_prism2_header *)skb_push(pOSPkt,
- sizeof(struct rt_wlan_ng_prism2_header));
- NdisZeroMemory(ph, sizeof(struct rt_wlan_ng_prism2_header));
-
- ph->msgcode = DIDmsg_lnxind_wlansniffrm;
- ph->msglen = sizeof(struct rt_wlan_ng_prism2_header);
- strcpy((char *)ph->devname, (char *)pAd->net_dev->name);
-
- ph->hosttime.did = DIDmsg_lnxind_wlansniffrm_hosttime;
- ph->hosttime.status = 0;
- ph->hosttime.len = 4;
- ph->hosttime.data = jiffies;
-
- ph->mactime.did = DIDmsg_lnxind_wlansniffrm_mactime;
- ph->mactime.status = 0;
- ph->mactime.len = 0;
- ph->mactime.data = 0;
-
- ph->istx.did = DIDmsg_lnxind_wlansniffrm_istx;
- ph->istx.status = 0;
- ph->istx.len = 0;
- ph->istx.data = 0;
-
- ph->channel.did = DIDmsg_lnxind_wlansniffrm_channel;
- ph->channel.status = 0;
- ph->channel.len = 4;
-
- ph->channel.data = (u_int32_t) pAd->CommonCfg.Channel;
-
- ph->rssi.did = DIDmsg_lnxind_wlansniffrm_rssi;
- ph->rssi.status = 0;
- ph->rssi.len = 4;
- ph->rssi.data =
- (u_int32_t) RTMPMaxRssi(pAd,
- ConvertToRssi(pAd, pRxBlk->pRxWI->RSSI0,
- RSSI_0), ConvertToRssi(pAd,
- pRxBlk->
- pRxWI->
- RSSI1,
- RSSI_1),
- ConvertToRssi(pAd, pRxBlk->pRxWI->RSSI2,
- RSSI_2));
-
- ph->signal.did = DIDmsg_lnxind_wlansniffrm_signal;
- ph->signal.status = 0;
- ph->signal.len = 4;
- ph->signal.data = 0; /*rssi + noise; */
-
- ph->noise.did = DIDmsg_lnxind_wlansniffrm_noise;
- ph->noise.status = 0;
- ph->noise.len = 4;
- ph->noise.data = 0;
-
- if (pRxBlk->pRxWI->PHYMODE >= MODE_HTMIX) {
- rate_index =
- 16 + ((u8)pRxBlk->pRxWI->BW * 16) +
- ((u8)pRxBlk->pRxWI->ShortGI * 32) +
- ((u8)pRxBlk->pRxWI->MCS);
- } else if (pRxBlk->pRxWI->PHYMODE == MODE_OFDM)
- rate_index = (u8)(pRxBlk->pRxWI->MCS) + 4;
- else
- rate_index = (u8)(pRxBlk->pRxWI->MCS);
- if (rate_index < 0)
- rate_index = 0;
- if (rate_index > 255)
- rate_index = 255;
-
- ph->rate.did = DIDmsg_lnxind_wlansniffrm_rate;
- ph->rate.status = 0;
- ph->rate.len = 4;
- ph->rate.data = ralinkrate[rate_index];
-
- ph->frmlen.did = DIDmsg_lnxind_wlansniffrm_frmlen;
- ph->frmlen.status = 0;
- ph->frmlen.len = 4;
- ph->frmlen.data = (u_int32_t) pRxBlk->DataSize;
-
- pOSPkt->pkt_type = PACKET_OTHERHOST;
- pOSPkt->protocol = eth_type_trans(pOSPkt, pOSPkt->dev);
- pOSPkt->ip_summed = CHECKSUM_NONE;
- netif_rx(pOSPkt);
-
- return;
-
-err_free_sk_buff:
- RELEASE_NDIS_PACKET(pAd, pRxBlk->pRxPacket, NDIS_STATUS_FAILURE);
- return;
-
-}
-
-/*******************************************************************************
-
- Device IRQ related functions.
-
- *******************************************************************************/
-int RtmpOSIRQRequest(struct net_device *pNetDev)
-{
-#ifdef RTMP_PCI_SUPPORT
- struct net_device *net_dev = pNetDev;
- struct rt_rtmp_adapter *pAd = NULL;
- int retval = 0;
-
- GET_PAD_FROM_NET_DEV(pAd, pNetDev);
-
- ASSERT(pAd);
-
- if (pAd->infType == RTMP_DEV_INF_PCI) {
- struct os_cookie *_pObj = (struct os_cookie *)(pAd->OS_Cookie);
- RTMP_MSI_ENABLE(pAd);
- retval =
- request_irq(_pObj->pci_dev->irq, rt2860_interrupt, SA_SHIRQ,
- (net_dev)->name, (net_dev));
- if (retval != 0)
- printk(KERN_ERR "rt2860: request_irq ERROR(%d)\n", retval);
- }
-
- return retval;
-#else
- return 0;
-#endif
-}
-
-int RtmpOSIRQRelease(struct net_device *pNetDev)
-{
- struct net_device *net_dev = pNetDev;
- struct rt_rtmp_adapter *pAd = NULL;
-
- GET_PAD_FROM_NET_DEV(pAd, net_dev);
-
- ASSERT(pAd);
-
-#ifdef RTMP_PCI_SUPPORT
- if (pAd->infType == RTMP_DEV_INF_PCI) {
- struct os_cookie *pObj = (struct os_cookie *)(pAd->OS_Cookie);
- synchronize_irq(pObj->pci_dev->irq);
- free_irq(pObj->pci_dev->irq, (net_dev));
- RTMP_MSI_DISABLE(pAd);
- }
-#endif /* RTMP_PCI_SUPPORT // */
-
- return 0;
-}
-
-/*******************************************************************************
-
- File open/close related functions.
-
- *******************************************************************************/
-struct file *RtmpOSFileOpen(char *pPath, int flag, int mode)
-{
- struct file *filePtr;
-
- filePtr = filp_open(pPath, flag, 0);
- if (IS_ERR(filePtr)) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("%s(): Error %ld opening %s\n", __func__,
- -PTR_ERR(filePtr), pPath));
- }
-
- return (struct file *)filePtr;
-}
-
-int RtmpOSFileClose(struct file *osfd)
-{
- filp_close(osfd, NULL);
- return 0;
-}
-
-void RtmpOSFileSeek(struct file *osfd, int offset)
-{
- osfd->f_pos = offset;
-}
-
-int RtmpOSFileRead(struct file *osfd, char *pDataPtr, int readLen)
-{
- /* The object must have a read method */
- if (osfd->f_op && osfd->f_op->read) {
- return osfd->f_op->read(osfd, pDataPtr, readLen, &osfd->f_pos);
- } else {
- DBGPRINT(RT_DEBUG_ERROR, ("no file read method\n"));
- return -1;
- }
-}
-
-int RtmpOSFileWrite(struct file *osfd, char *pDataPtr, int writeLen)
-{
- return osfd->f_op->write(osfd, pDataPtr, (size_t) writeLen,
- &osfd->f_pos);
-}
-
-/*******************************************************************************
-
- Task create/management/kill related functions.
-
- *******************************************************************************/
-int RtmpOSTaskKill(struct rt_rtmp_os_task *pTask)
-{
- struct rt_rtmp_adapter *pAd;
- int ret = NDIS_STATUS_FAILURE;
-
- pAd = pTask->priv;
-
-#ifdef KTHREAD_SUPPORT
- if (pTask->kthread_task) {
- kthread_stop(pTask->kthread_task);
- ret = NDIS_STATUS_SUCCESS;
- }
-#else
- CHECK_PID_LEGALITY(pTask->taskPID) {
- printk(KERN_INFO "Terminate the task(%s) with pid(%d)!\n",
- pTask->taskName, GET_PID_NUMBER(pTask->taskPID));
- mb();
- pTask->task_killed = 1;
- mb();
- ret = KILL_THREAD_PID(pTask->taskPID, SIGTERM, 1);
- if (ret) {
- printk(KERN_WARNING
- "kill task(%s) with pid(%d) failed(retVal=%d)!\n",
- pTask->taskName, GET_PID_NUMBER(pTask->taskPID),
- ret);
- } else {
- wait_for_completion(&pTask->taskComplete);
- pTask->taskPID = THREAD_PID_INIT_VALUE;
- pTask->task_killed = 0;
- ret = NDIS_STATUS_SUCCESS;
- }
- }
-#endif
-
- return ret;
-
-}
-
-int RtmpOSTaskNotifyToExit(struct rt_rtmp_os_task *pTask)
-{
-
-#ifndef KTHREAD_SUPPORT
- complete_and_exit(&pTask->taskComplete, 0);
-#endif
-
- return 0;
-}
-
-void RtmpOSTaskCustomize(struct rt_rtmp_os_task *pTask)
-{
-
-#ifndef KTHREAD_SUPPORT
-
- daemonize((char *)&pTask->taskName[0] /*"%s",pAd->net_dev->name */);
-
- allow_signal(SIGTERM);
- allow_signal(SIGKILL);
- current->flags |= PF_NOFREEZE;
-
- /* signal that we've started the thread */
- complete(&pTask->taskComplete);
-
-#endif
-}
-
-int RtmpOSTaskAttach(struct rt_rtmp_os_task *pTask,
- IN int (*fn) (void *), IN void *arg)
-{
- int status = NDIS_STATUS_SUCCESS;
-
-#ifdef KTHREAD_SUPPORT
- pTask->task_killed = 0;
- pTask->kthread_task = NULL;
- pTask->kthread_task = kthread_run(fn, arg, pTask->taskName);
- if (IS_ERR(pTask->kthread_task))
- status = NDIS_STATUS_FAILURE;
-#else
- pid_number = kernel_thread(fn, arg, RTMP_OS_MGMT_TASK_FLAGS);
- if (pid_number < 0) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("Attach task(%s) failed!\n", pTask->taskName));
- status = NDIS_STATUS_FAILURE;
- } else {
- pTask->taskPID = GET_PID(pid_number);
-
- /* Wait for the thread to start */
- wait_for_completion(&pTask->taskComplete);
- status = NDIS_STATUS_SUCCESS;
- }
-#endif
- return status;
-}
-
-int RtmpOSTaskInit(struct rt_rtmp_os_task *pTask,
- char *pTaskName, void * pPriv)
-{
- int len;
-
- ASSERT(pTask);
-
-#ifndef KTHREAD_SUPPORT
- NdisZeroMemory((u8 *)(pTask), sizeof(struct rt_rtmp_os_task));
-#endif
-
- len = strlen(pTaskName);
- len =
- len >
- (RTMP_OS_TASK_NAME_LEN - 1) ? (RTMP_OS_TASK_NAME_LEN - 1) : len;
- NdisMoveMemory(&pTask->taskName[0], pTaskName, len);
- pTask->priv = pPriv;
-
-#ifndef KTHREAD_SUPPORT
- RTMP_SEM_EVENT_INIT_LOCKED(&(pTask->taskSema));
- pTask->taskPID = THREAD_PID_INIT_VALUE;
-
- init_completion(&pTask->taskComplete);
-#endif
-
- return NDIS_STATUS_SUCCESS;
-}
-
-void RTMP_IndicateMediaState(struct rt_rtmp_adapter *pAd)
-{
- if (pAd->CommonCfg.bWirelessEvent) {
- if (pAd->IndicateMediaState == NdisMediaStateConnected) {
- RTMPSendWirelessEvent(pAd, IW_STA_LINKUP_EVENT_FLAG,
- pAd->MacTab.Content[BSSID_WCID].
- Addr, BSS0, 0);
- } else {
- RTMPSendWirelessEvent(pAd, IW_STA_LINKDOWN_EVENT_FLAG,
- pAd->MacTab.Content[BSSID_WCID].
- Addr, BSS0, 0);
- }
- }
-}
-
-int RtmpOSWrielessEventSend(struct rt_rtmp_adapter *pAd,
- u32 eventType,
- int flags,
- u8 *pSrcMac,
- u8 *pData, u32 dataLen)
-{
- union iwreq_data wrqu;
-
- memset(&wrqu, 0, sizeof(wrqu));
-
- if (flags > -1)
- wrqu.data.flags = flags;
-
- if (pSrcMac)
- memcpy(wrqu.ap_addr.sa_data, pSrcMac, MAC_ADDR_LEN);
-
- if ((pData != NULL) && (dataLen > 0))
- wrqu.data.length = dataLen;
-
- wireless_send_event(pAd->net_dev, eventType, &wrqu, (char *)pData);
- return 0;
-}
-
-int RtmpOSNetDevAddrSet(struct net_device *pNetDev, u8 *pMacAddr)
-{
- struct net_device *net_dev;
- struct rt_rtmp_adapter *pAd;
-
- net_dev = pNetDev;
- GET_PAD_FROM_NET_DEV(pAd, net_dev);
-
- /* work-around for SuSE, due to them having their own interface name management system. */
- {
- NdisZeroMemory(pAd->StaCfg.dev_name, 16);
- NdisMoveMemory(pAd->StaCfg.dev_name, net_dev->name,
- strlen(net_dev->name));
- }
-
- NdisMoveMemory(net_dev->dev_addr, pMacAddr, 6);
-
- return 0;
-}
-
-/*
- * Assign the network dev name for created Ralink WiFi interface.
- */
-static int RtmpOSNetDevRequestName(struct rt_rtmp_adapter *pAd,
- struct net_device *dev,
- char *pPrefixStr, int devIdx)
-{
- struct net_device *existNetDev;
- char suffixName[IFNAMSIZ];
- char desiredName[IFNAMSIZ];
- int ifNameIdx, prefixLen, slotNameLen;
- int Status;
-
- prefixLen = strlen(pPrefixStr);
- ASSERT((prefixLen < IFNAMSIZ));
-
- for (ifNameIdx = devIdx; ifNameIdx < 32; ifNameIdx++) {
- memset(suffixName, 0, IFNAMSIZ);
- memset(desiredName, 0, IFNAMSIZ);
- strncpy(&desiredName[0], pPrefixStr, prefixLen);
-
- sprintf(suffixName, "%d", ifNameIdx);
-
- slotNameLen = strlen(suffixName);
- ASSERT(((slotNameLen + prefixLen) < IFNAMSIZ));
- strcat(desiredName, suffixName);
-
- existNetDev = RtmpOSNetDevGetByName(dev, &desiredName[0]);
- if (existNetDev == NULL)
- break;
- else
- RtmpOSNetDeviceRefPut(existNetDev);
- }
-
- if (ifNameIdx < 32) {
- strcpy(&dev->name[0], &desiredName[0]);
- Status = NDIS_STATUS_SUCCESS;
- } else {
- DBGPRINT(RT_DEBUG_ERROR,
- ("Cannot request DevName with preifx(%s) and in range(0~32) as suffix from OS!\n",
- pPrefixStr));
- Status = NDIS_STATUS_FAILURE;
- }
-
- return Status;
-}
-
-void RtmpOSNetDevClose(struct net_device *pNetDev)
-{
- dev_close(pNetDev);
-}
-
-void RtmpOSNetDevFree(struct net_device *pNetDev)
-{
- ASSERT(pNetDev);
-
- free_netdev(pNetDev);
-}
-
-int RtmpOSNetDevAlloc(struct net_device **new_dev_p, u32 privDataSize)
-{
- /* assign it as null first. */
- *new_dev_p = NULL;
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("Allocate a net device with private data size=%d!\n",
- privDataSize));
- *new_dev_p = alloc_etherdev(privDataSize);
- if (*new_dev_p)
- return NDIS_STATUS_SUCCESS;
- else
- return NDIS_STATUS_FAILURE;
-}
-
-struct net_device *RtmpOSNetDevGetByName(struct net_device *pNetDev, char *pDevName)
-{
- struct net_device *pTargetNetDev = NULL;
-
- pTargetNetDev = dev_get_by_name(dev_net(pNetDev), pDevName);
-
- return pTargetNetDev;
-}
-
-void RtmpOSNetDeviceRefPut(struct net_device *pNetDev)
-{
- /*
- every time dev_get_by_name is called, and it has returned a valid struct
- net_device*, dev_put should be called afterwards, because otherwise the
- machine hangs when the device is unregistered (since dev->refcnt > 1).
- */
- if (pNetDev)
- dev_put(pNetDev);
-}
-
-int RtmpOSNetDevDestory(struct rt_rtmp_adapter *pAd, struct net_device *pNetDev)
-{
-
- /* TODO: Need to fix this */
- printk("WARNING: This function(%s) not implement yet!\n", __func__);
- return 0;
-}
-
-void RtmpOSNetDevDetach(struct net_device *pNetDev)
-{
- unregister_netdev(pNetDev);
-}
-
-int RtmpOSNetDevAttach(struct net_device *pNetDev,
- struct rt_rtmp_os_netdev_op_hook *pDevOpHook)
-{
- int ret, rtnl_locked = FALSE;
-
- DBGPRINT(RT_DEBUG_TRACE, ("RtmpOSNetDevAttach()--->\n"));
- /* If we need hook some callback function to the net device structure, now do it. */
- if (pDevOpHook) {
- struct rt_rtmp_adapter *pAd = NULL;
-
- GET_PAD_FROM_NET_DEV(pAd, pNetDev);
-
- pNetDev->netdev_ops = pDevOpHook->netdev_ops;
-
- /* OS specific flags, here we used to indicate if we are virtual interface */
- pNetDev->priv_flags = pDevOpHook->priv_flags;
-
- if (pAd->OpMode == OPMODE_STA)
- pNetDev->wireless_handlers = &rt28xx_iw_handler_def;
-
- /* copy the net device mac address to the net_device structure. */
- NdisMoveMemory(pNetDev->dev_addr, &pDevOpHook->devAddr[0],
- MAC_ADDR_LEN);
-
- rtnl_locked = pDevOpHook->needProtcted;
- }
-
- if (rtnl_locked)
- ret = register_netdevice(pNetDev);
- else
- ret = register_netdev(pNetDev);
-
- DBGPRINT(RT_DEBUG_TRACE, ("<---RtmpOSNetDevAttach(), ret=%d\n", ret));
- if (ret == 0)
- return NDIS_STATUS_SUCCESS;
- else
- return NDIS_STATUS_FAILURE;
-}
-
-struct net_device *RtmpOSNetDevCreate(struct rt_rtmp_adapter *pAd,
- int devType,
- int devNum,
- int privMemSize, char *pNamePrefix)
-{
- struct net_device *pNetDev = NULL;
- int status;
-
- /* allocate a new network device */
- status = RtmpOSNetDevAlloc(&pNetDev, 0 /*privMemSize */);
- if (status != NDIS_STATUS_SUCCESS) {
- /* allocation fail, exit */
- DBGPRINT(RT_DEBUG_ERROR,
- ("Allocate network device fail (%s)...\n",
- pNamePrefix));
- return NULL;
- }
-
- /* find an available interface name, max 32 interfaces */
- status = RtmpOSNetDevRequestName(pAd, pNetDev, pNamePrefix, devNum);
- if (status != NDIS_STATUS_SUCCESS) {
- /* error! no available ra name can be used! */
- DBGPRINT(RT_DEBUG_ERROR,
- ("Assign interface name (%s with suffix 0~32) failed...\n",
- pNamePrefix));
- RtmpOSNetDevFree(pNetDev);
-
- return NULL;
- } else {
- DBGPRINT(RT_DEBUG_TRACE,
- ("The name of the new %s interface is %s...\n",
- pNamePrefix, pNetDev->name));
- }
-
- return pNetDev;
-}
diff --git a/drivers/staging/rt2860/rt_linux.h b/drivers/staging/rt2860/rt_linux.h
deleted file mode 100644
index 3efb88f..0000000
--- a/drivers/staging/rt2860/rt_linux.h
+++ /dev/null
@@ -1,835 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- rt_linux.h
-
- Abstract:
-
- Revision History:
- Who When What
- Justin P. Mattock 11/07/2010 Fix typo in a comment
- --------- ---------- ----------------------------------------------
-*/
-
-#ifndef __RT_LINUX_H__
-#define __RT_LINUX_H__
-
-#include <linux/module.h>
-#include <linux/kernel.h>
-#include <linux/spinlock.h>
-#include <linux/init.h>
-#include <linux/string.h>
-#include <linux/timer.h>
-#include <linux/errno.h>
-#include <linux/slab.h>
-#include <linux/interrupt.h>
-#include <linux/pci.h>
-#include <linux/netdevice.h>
-#include <linux/etherdevice.h>
-#include <linux/skbuff.h>
-#include <linux/ethtool.h>
-#include <linux/wireless.h>
-#include <linux/proc_fs.h>
-#include <linux/delay.h>
-#include <linux/if_arp.h>
-#include <linux/ctype.h>
-#include <linux/vmalloc.h>
-
-#include <net/iw_handler.h>
-
-/* load firmware */
-#define __KERNEL_SYSCALLS__
-#include <linux/unistd.h>
-#include <asm/uaccess.h>
-#include <asm/types.h>
-#include <asm/unaligned.h> /* for get_unaligned() */
-
-#define KTHREAD_SUPPORT 1
-/* RT2870 2.1.0.0 has it disabled */
-
-#ifdef KTHREAD_SUPPORT
-#include <linux/err.h>
-#include <linux/kthread.h>
-#endif /* KTHREAD_SUPPORT // */
-
-/***********************************************************************************
- * Profile related sections
- ***********************************************************************************/
-
-#ifdef RTMP_MAC_PCI
-#define STA_DRIVER_VERSION "2.1.0.0"
-#endif /* RTMP_MAC_PCI // */
-#ifdef RTMP_MAC_USB
-#define STA_DRIVER_VERSION "2.1.0.0"
-/* RT3070 version: 2.1.1.0 */
-#endif /* RTMP_MAC_USB // */
-
-extern const struct iw_handler_def rt28xx_iw_handler_def;
-
-/***********************************************************************************
- * Compiler related definitions
- ***********************************************************************************/
-#undef __inline
-#define __inline static inline
-#define IN
-#define OUT
-#define INOUT
-
-/***********************************************************************************
- * OS Specific definitions and data structures
- ***********************************************************************************/
-typedef int (*HARD_START_XMIT_FUNC) (struct sk_buff *skb,
- struct net_device *net_dev);
-
-#ifdef RTMP_MAC_PCI
-#ifndef PCI_DEVICE
-#define PCI_DEVICE(vend,dev) \
- .vendor = (vend), .device = (dev), \
- .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
-#endif /* PCI_DEVICE // */
-#endif /* RTMP_MAC_PCI // */
-
-#define RT_MOD_INC_USE_COUNT() \
- if (!try_module_get(THIS_MODULE)) \
- { \
- DBGPRINT(RT_DEBUG_ERROR, ("%s: cannot reserve module\n", __func__)); \
- return -1; \
- }
-
-#define RT_MOD_DEC_USE_COUNT() module_put(THIS_MODULE);
-
-#define RTMP_INC_REF(_A) 0
-#define RTMP_DEC_REF(_A) 0
-#define RTMP_GET_REF(_A) 0
-
-/* This function will be called when query /proc */
-struct iw_statistics *rt28xx_get_wireless_stats(IN struct net_device *net_dev);
-
-/***********************************************************************************
- * Network related constant definitions
- ***********************************************************************************/
-#ifndef IFNAMSIZ
-#define IFNAMSIZ 16
-#endif
-
-#define ETH_LENGTH_OF_ADDRESS 6
-
-#define NDIS_STATUS_SUCCESS 0x00
-#define NDIS_STATUS_FAILURE 0x01
-#define NDIS_STATUS_INVALID_DATA 0x02
-#define NDIS_STATUS_RESOURCES 0x03
-
-#define NDIS_SET_PACKET_STATUS(_p, _status) do{} while(0)
-#define NdisWriteErrorLogEntry(_a, _b, _c, _d) do{} while(0)
-
-/* statistics counter */
-#define STATS_INC_RX_PACKETS(_pAd, _dev)
-#define STATS_INC_TX_PACKETS(_pAd, _dev)
-
-#define STATS_INC_RX_BYTESS(_pAd, _dev, len)
-#define STATS_INC_TX_BYTESS(_pAd, _dev, len)
-
-#define STATS_INC_RX_ERRORS(_pAd, _dev)
-#define STATS_INC_TX_ERRORS(_pAd, _dev)
-
-#define STATS_INC_RX_DROPPED(_pAd, _dev)
-#define STATS_INC_TX_DROPPED(_pAd, _dev)
-
-/***********************************************************************************
- * Ralink Specific network related constant definitions
- ***********************************************************************************/
-#define MIN_NET_DEVICE_FOR_AID 0x00 /*0x00~0x3f */
-#define MIN_NET_DEVICE_FOR_MBSSID 0x00 /*0x00,0x10,0x20,0x30 */
-#define MIN_NET_DEVICE_FOR_WDS 0x10 /*0x40,0x50,0x60,0x70 */
-#define MIN_NET_DEVICE_FOR_APCLI 0x20
-#define MIN_NET_DEVICE_FOR_MESH 0x30
-#define MIN_NET_DEVICE_FOR_DLS 0x40
-#define NET_DEVICE_REAL_IDX_MASK 0x0f /* for each operation mode, we maximum support 15 entities. */
-
-#define NDIS_PACKET_TYPE_DIRECTED 0
-#define NDIS_PACKET_TYPE_MULTICAST 1
-#define NDIS_PACKET_TYPE_BROADCAST 2
-#define NDIS_PACKET_TYPE_ALL_MULTICAST 3
-#define NDIS_PACKET_TYPE_PROMISCUOUS 4
-
-/***********************************************************************************
- * OS signaling related constant definitions
- ***********************************************************************************/
-
-/***********************************************************************************
- * OS file operation related data structure definitions
- ***********************************************************************************/
-struct rt_rtmp_os_fs_info {
- int fsuid;
- int fsgid;
- mm_segment_t fs;
-};
-
-#define IS_FILE_OPEN_ERR(_fd) IS_ERR((_fd))
-
-/***********************************************************************************
- * OS semaphore related data structure and definitions
- ***********************************************************************************/
-struct os_lock {
- spinlock_t lock;
- unsigned long flags;
-};
-
-/* */
-/* spin_lock enhanced for Nested spin lock */
-/* */
-#define NdisAllocateSpinLock(__lock) \
-{ \
- spin_lock_init((spinlock_t *)(__lock)); \
-}
-
-#define NdisFreeSpinLock(lock) \
- do{}while(0)
-
-#define RTMP_SEM_LOCK(__lock) \
-{ \
- spin_lock_bh((spinlock_t *)(__lock)); \
-}
-
-#define RTMP_SEM_UNLOCK(__lock) \
-{ \
- spin_unlock_bh((spinlock_t *)(__lock)); \
-}
-
-/* sample, use semaphore lock to replace IRQ lock, 2007/11/15 */
-#define RTMP_IRQ_LOCK(__lock, __irqflags) \
-{ \
- __irqflags = 0; \
- spin_lock_bh((spinlock_t *)(__lock)); \
- pAd->irq_disabled |= 1; \
-}
-
-#define RTMP_IRQ_UNLOCK(__lock, __irqflag) \
-{ \
- pAd->irq_disabled &= 0; \
- spin_unlock_bh((spinlock_t *)(__lock)); \
-}
-
-#define RTMP_INT_LOCK(__lock, __irqflags) \
-{ \
- spin_lock_irqsave((spinlock_t *)__lock, __irqflags); \
-}
-
-#define RTMP_INT_UNLOCK(__lock, __irqflag) \
-{ \
- spin_unlock_irqrestore((spinlock_t *)(__lock), ((unsigned long)__irqflag)); \
-}
-
-#define NdisAcquireSpinLock RTMP_SEM_LOCK
-#define NdisReleaseSpinLock RTMP_SEM_UNLOCK
-
-#ifndef wait_event_interruptible_timeout
-#define __wait_event_interruptible_timeout(wq, condition, ret) \
-do { \
- wait_queue_t __wait; \
- init_waitqueue_entry(&__wait, current); \
- add_wait_queue(&wq, &__wait); \
- for (;;) { \
- set_current_state(TASK_INTERRUPTIBLE); \
- if (condition) \
- break; \
- if (!signal_pending(current)) { \
- ret = schedule_timeout(ret); \
- if (!ret) \
- break; \
- continue; \
- } \
- ret = -ERESTARTSYS; \
- break; \
- } \
- current->state = TASK_RUNNING; \
- remove_wait_queue(&wq, &__wait); \
-} while (0)
-
-#define wait_event_interruptible_timeout(wq, condition, timeout) \
-({ \
- long __ret = timeout; \
- if (!(condition)) \
- __wait_event_interruptible_timeout(wq, condition, __ret); \
- __ret; \
-})
-#endif
-
-#define RTMP_SEM_EVENT_INIT_LOCKED(_pSema) sema_init((_pSema), 0)
-#define RTMP_SEM_EVENT_INIT(_pSema) sema_init((_pSema), 1)
-#define RTMP_SEM_EVENT_WAIT(_pSema, _status) ((_status) = down_interruptible((_pSema)))
-#define RTMP_SEM_EVENT_UP(_pSema) up(_pSema)
-
-#ifdef KTHREAD_SUPPORT
-#define RTMP_WAIT_EVENT_INTERRUPTIBLE(_pAd, _pTask) \
-{ \
- wait_event_interruptible(_pTask->kthread_q, \
- _pTask->kthread_running || kthread_should_stop()); \
- _pTask->kthread_running = FALSE; \
- if (kthread_should_stop()) \
- { \
- RTMP_SET_FLAG(_pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS); \
- break; \
- } \
-}
-#endif
-
-#ifdef KTHREAD_SUPPORT
-#define WAKE_UP(_pTask) \
- do{ \
- if ((_pTask)->kthread_task) \
- { \
- (_pTask)->kthread_running = TRUE; \
- wake_up(&(_pTask)->kthread_q); \
- } \
- }while(0)
-#endif
-
-/***********************************************************************************
- * OS Memory Access related data structure and definitions
- ***********************************************************************************/
-#define MEM_ALLOC_FLAG (GFP_ATOMIC) /*(GFP_DMA | GFP_ATOMIC) */
-
-#define NdisMoveMemory(Destination, Source, Length) memmove(Destination, Source, Length)
-#define NdisCopyMemory(Destination, Source, Length) memcpy(Destination, Source, Length)
-#define NdisZeroMemory(Destination, Length) memset(Destination, 0, Length)
-#define NdisFillMemory(Destination, Length, Fill) memset(Destination, Fill, Length)
-#define NdisCmpMemory(Destination, Source, Length) memcmp(Destination, Source, Length)
-#define NdisEqualMemory(Source1, Source2, Length) (!memcmp(Source1, Source2, Length))
-#define RTMPEqualMemory(Source1, Source2, Length) (!memcmp(Source1, Source2, Length))
-
-#define MlmeAllocateMemory(_pAd, _ppVA) os_alloc_mem(_pAd, _ppVA, MGMT_DMA_BUFFER_SIZE)
-#define MlmeFreeMemory(_pAd, _pVA) os_free_mem(_pAd, _pVA)
-
-#define COPY_MAC_ADDR(Addr1, Addr2) memcpy((Addr1), (Addr2), MAC_ADDR_LEN)
-
-/***********************************************************************************
- * OS task related data structure and definitions
- ***********************************************************************************/
-#define RTMP_OS_MGMT_TASK_FLAGS CLONE_VM
-
-#define THREAD_PID_INIT_VALUE NULL
-#define GET_PID(_v) find_get_pid((_v))
-#define GET_PID_NUMBER(_v) pid_nr((_v))
-#define CHECK_PID_LEGALITY(_pid) if (pid_nr((_pid)) > 0)
-#define KILL_THREAD_PID(_A, _B, _C) kill_pid((_A), (_B), (_C))
-
-/***********************************************************************************
- * Timer related definitions and data structures.
- **********************************************************************************/
-#define OS_HZ HZ
-
-typedef void (*TIMER_FUNCTION) (unsigned long);
-
-#define OS_WAIT(_time) \
-{ int _i; \
- long _loop = ((_time)/(1000/OS_HZ)) > 0 ? ((_time)/(1000/OS_HZ)) : 1;\
- wait_queue_head_t _wait; \
- init_waitqueue_head(&_wait); \
- for (_i=0; _i<(_loop); _i++) \
- wait_event_interruptible_timeout(_wait, 0, ONE_TICK); }
-
-#define RTMP_TIME_AFTER(a,b) \
- (typecheck(unsigned long, (unsigned long)a) && \
- typecheck(unsigned long, (unsigned long)b) && \
- ((long)(b) - (long)(a) < 0))
-
-#define RTMP_TIME_AFTER_EQ(a,b) \
- (typecheck(unsigned long, (unsigned long)a) && \
- typecheck(unsigned long, (unsigned long)b) && \
- ((long)(a) - (long)(b) >= 0))
-#define RTMP_TIME_BEFORE(a,b) RTMP_TIME_AFTER_EQ(b,a)
-
-#define ONE_TICK 1
-
-static inline void NdisGetSystemUpTime(unsigned long *time)
-{
- *time = jiffies;
-}
-
-/***********************************************************************************
- * OS specific cookie data structure binding to struct rt_rtmp_adapter
- ***********************************************************************************/
-
-struct os_cookie {
-#ifdef RTMP_MAC_PCI
- struct pci_dev *pci_dev;
- struct pci_dev *parent_pci_dev;
- u16 DeviceID;
- dma_addr_t pAd_pa;
-#endif /* RTMP_MAC_PCI // */
-#ifdef RTMP_MAC_USB
- struct usb_device *pUsb_Dev;
-#endif /* RTMP_MAC_USB // */
-
- struct tasklet_struct rx_done_task;
- struct tasklet_struct mgmt_dma_done_task;
- struct tasklet_struct ac0_dma_done_task;
- struct tasklet_struct ac1_dma_done_task;
- struct tasklet_struct ac2_dma_done_task;
- struct tasklet_struct ac3_dma_done_task;
- struct tasklet_struct tbtt_task;
-#ifdef RTMP_MAC_PCI
- struct tasklet_struct fifo_statistic_full_task;
-#endif /* RTMP_MAC_PCI // */
-#ifdef RTMP_MAC_USB
- struct tasklet_struct null_frame_complete_task;
- struct tasklet_struct rts_frame_complete_task;
- struct tasklet_struct pspoll_frame_complete_task;
-#endif /* RTMP_MAC_USB // */
-
- unsigned long apd_pid; /*802.1x daemon pid */
- int ioctl_if_type;
- int ioctl_if;
-};
-
-/***********************************************************************************
- * OS debugging and printing related definitions and data structure
- ***********************************************************************************/
-#ifdef DBG
-extern unsigned long RTDebugLevel;
-
-#define DBGPRINT_RAW(Level, Fmt) \
-do{ \
- if (Level <= RTDebugLevel) \
- { \
- printk Fmt; \
- } \
-}while(0)
-
-#define DBGPRINT(Level, Fmt) DBGPRINT_RAW(Level, Fmt)
-
-#define DBGPRINT_ERR(fmt, args...) printk(KERN_ERR fmt, ##args)
-
-#define DBGPRINT_S(Status, Fmt) \
-{ \
- printk Fmt; \
-}
-
-#else
-#define DBGPRINT(Level, Fmt)
-#define DBGPRINT_RAW(Level, Fmt)
-#define DBGPRINT_S(Status, Fmt)
-#define DBGPRINT_ERR(Fmt)
-#endif
-
-#define ASSERT(x)
-
-void hex_dump(char *str, unsigned char *pSrcBufVA, unsigned int SrcBufLen);
-
-/*********************************************************************************************************
- The following code are not revised, temporary put it here.
- *********************************************************************************************************/
-
-/***********************************************************************************
- * Device DMA Access related definitions and data structures.
- **********************************************************************************/
-#ifdef RTMP_MAC_PCI
-struct rt_rtmp_adapter;
-dma_addr_t linux_pci_map_single(struct rt_rtmp_adapter *pAd, void *ptr,
- size_t size, int sd_idx, int direction);
-void linux_pci_unmap_single(struct rt_rtmp_adapter *pAd, dma_addr_t dma_addr,
- size_t size, int direction);
-
-#define PCI_MAP_SINGLE(_handle, _ptr, _size, _sd_idx, _dir) \
- linux_pci_map_single(_handle, _ptr, _size, _sd_idx, _dir)
-
-#define PCI_UNMAP_SINGLE(_handle, _ptr, _size, _dir) \
- linux_pci_unmap_single(_handle, _ptr, _size, _dir)
-
-#define PCI_ALLOC_CONSISTENT(_pci_dev, _size, _ptr) \
- pci_alloc_consistent(_pci_dev, _size, _ptr)
-
-#define PCI_FREE_CONSISTENT(_pci_dev, _size, _virtual_addr, _physical_addr) \
- pci_free_consistent(_pci_dev, _size, _virtual_addr, _physical_addr)
-
-#define DEV_ALLOC_SKB(_length) \
- dev_alloc_skb(_length)
-#endif /* RTMP_MAC_PCI // */
-
-/*
- * unsigned long
- * RTMP_GetPhysicalAddressLow(
- * dma_addr_t PhysicalAddress);
- */
-#define RTMP_GetPhysicalAddressLow(PhysicalAddress) (PhysicalAddress)
-
-/*
- * unsigned long
- * RTMP_GetPhysicalAddressHigh(
- * dma_addr_t PhysicalAddress);
- */
-#define RTMP_GetPhysicalAddressHigh(PhysicalAddress) (0)
-
-/*
- * void
- * RTMP_SetPhysicalAddressLow(
- * dma_addr_t PhysicalAddress,
- * unsigned long Value);
- */
-#define RTMP_SetPhysicalAddressLow(PhysicalAddress, Value) \
- PhysicalAddress = Value;
-
-/*
- * void
- * RTMP_SetPhysicalAddressHigh(
- * dma_addr_t PhysicalAddress,
- * unsigned long Value);
- */
-#define RTMP_SetPhysicalAddressHigh(PhysicalAddress, Value)
-
-#define NdisMIndicateStatus(_w, _x, _y, _z)
-
-/***********************************************************************************
- * Device Register I/O Access related definitions and data structures.
- **********************************************************************************/
-#ifdef RTMP_MAC_PCI
-/*Patch for ASIC turst read/write bug, needs to remove after metel fix */
-#define RTMP_IO_READ32(_A, _R, _pV) \
-{ \
- if ((_A)->bPCIclkOff == FALSE) \
- { \
- (*_pV = readl((void *)((_A)->CSRBaseAddress + MAC_CSR0))); \
- (*_pV = readl((void *)((_A)->CSRBaseAddress + (_R)))); \
- } \
- else \
- *_pV = 0; \
-}
-
-#define RTMP_IO_FORCE_READ32(_A, _R, _pV) \
-{ \
- (*_pV = readl((void *)((_A)->CSRBaseAddress + MAC_CSR0))); \
- (*_pV = readl((void *)((_A)->CSRBaseAddress + (_R)))); \
-}
-
-#define RTMP_IO_READ8(_A, _R, _pV) \
-{ \
- (*_pV = readl((void *)((_A)->CSRBaseAddress + MAC_CSR0))); \
- (*_pV = readb((void *)((_A)->CSRBaseAddress + (_R)))); \
-}
-#define RTMP_IO_WRITE32(_A, _R, _V) \
-{ \
- if ((_A)->bPCIclkOff == FALSE) \
- { \
- u32 Val; \
- Val = readl((void *)((_A)->CSRBaseAddress + MAC_CSR0)); \
- writel((_V), (void *)((_A)->CSRBaseAddress + (_R))); \
- } \
-}
-
-#define RTMP_IO_FORCE_WRITE32(_A, _R, _V) \
-{ \
- u32 Val; \
- Val = readl((void *)((_A)->CSRBaseAddress + MAC_CSR0)); \
- writel(_V, (void *)((_A)->CSRBaseAddress + (_R))); \
-}
-
-#if defined(RALINK_2880) || defined(RALINK_3052)
-#define RTMP_IO_WRITE8(_A, _R, _V) \
-{ \
- unsigned long Val; \
- u8 _i; \
- _i = ((_R) & 0x3); \
- Val = readl((void *)((_A)->CSRBaseAddress + ((_R) - _i))); \
- Val = Val & (~(0x000000ff << ((_i)*8))); \
- Val = Val | ((unsigned long)(_V) << ((_i)*8)); \
- writel((Val), (void *)((_A)->CSRBaseAddress + ((_R) - _i))); \
-}
-#else
-#define RTMP_IO_WRITE8(_A, _R, _V) \
-{ \
- u32 Val; \
- Val = readl((void *)((_A)->CSRBaseAddress + MAC_CSR0)); \
- writeb((_V), (u8 *)((_A)->CSRBaseAddress + (_R))); \
-}
-#endif /* #if defined(BRCM_6358) || defined(RALINK_2880) // */
-
-#define RTMP_IO_WRITE16(_A, _R, _V) \
-{ \
- u32 Val; \
- Val = readl((void *)((_A)->CSRBaseAddress + MAC_CSR0)); \
- writew((_V), (u16 *)((_A)->CSRBaseAddress + (_R))); \
-}
-#endif /* RTMP_MAC_PCI // */
-#ifdef RTMP_MAC_USB
-/*Patch for ASIC turst read/write bug, needs to remove after metel fix */
-#define RTMP_IO_READ32(_A, _R, _pV) \
- RTUSBReadMACRegister((_A), (_R), (u32 *)(_pV))
-
-#define RTMP_IO_READ8(_A, _R, _pV) \
-{ \
-}
-
-#define RTMP_IO_WRITE32(_A, _R, _V) \
- RTUSBWriteMACRegister((_A), (_R), (u32)(_V))
-
-#define RTMP_IO_WRITE8(_A, _R, _V) \
-{ \
- u16 _Val = _V; \
- RTUSBSingleWrite((_A), (_R), (u16)(_Val)); \
-}
-
-#define RTMP_IO_WRITE16(_A, _R, _V) \
-{ \
- RTUSBSingleWrite((_A), (_R), (u16)(_V)); \
-}
-#endif /* RTMP_MAC_USB // */
-
-/***********************************************************************************
- * Network Related data structure and marco definitions
- ***********************************************************************************/
-#define PKTSRC_NDIS 0x7f
-#define PKTSRC_DRIVER 0x0f
-
-#define RTMP_OS_NETDEV_SET_PRIV(_pNetDev, _pPriv) ((_pNetDev)->ml_priv = (_pPriv))
-#define RTMP_OS_NETDEV_GET_PRIV(_pNetDev) ((_pNetDev)->ml_priv)
-#define RTMP_OS_NETDEV_GET_DEVNAME(_pNetDev) ((_pNetDev)->name)
-#define RTMP_OS_NETDEV_GET_PHYADDR(_PNETDEV) ((_PNETDEV)->dev_addr)
-
-#define RTMP_OS_NETDEV_START_QUEUE(_pNetDev) netif_start_queue((_pNetDev))
-#define RTMP_OS_NETDEV_STOP_QUEUE(_pNetDev) netif_stop_queue((_pNetDev))
-#define RTMP_OS_NETDEV_WAKE_QUEUE(_pNetDev) netif_wake_queue((_pNetDev))
-#define RTMP_OS_NETDEV_CARRIER_OFF(_pNetDev) netif_carrier_off((_pNetDev))
-
-#define QUEUE_ENTRY_TO_PACKET(pEntry) \
- (void *)(pEntry)
-
-#define PACKET_TO_QUEUE_ENTRY(pPacket) \
- (struct rt_queue_entry *)(pPacket)
-
-#define GET_SG_LIST_FROM_PACKET(_p, _sc) \
- rt_get_sg_list_from_packet(_p, _sc)
-
-#define RELEASE_NDIS_PACKET(_pAd, _pPacket, _Status) \
-{ \
- RTMPFreeNdisPacket(_pAd, _pPacket); \
-}
-
-/*
- * packet helper
- * - convert internal rt packet to os packet or
- * os packet to rt packet
- */
-#define RTPKT_TO_OSPKT(_p) ((struct sk_buff *)(_p))
-#define OSPKT_TO_RTPKT(_p) ((void *)(_p))
-
-#define GET_OS_PKT_DATAPTR(_pkt) \
- (RTPKT_TO_OSPKT(_pkt)->data)
-#define SET_OS_PKT_DATAPTR(_pkt, _dataPtr) \
- (RTPKT_TO_OSPKT(_pkt)->data) = (_dataPtr)
-
-#define GET_OS_PKT_LEN(_pkt) \
- (RTPKT_TO_OSPKT(_pkt)->len)
-#define SET_OS_PKT_LEN(_pkt, _len) \
- (RTPKT_TO_OSPKT(_pkt)->len) = (_len)
-
-#define GET_OS_PKT_DATATAIL(_pkt) \
- (skb_tail_pointer(RTPKT_TO_OSPKT(_pkt))
-#define SET_OS_PKT_DATATAIL(_pkt, _start, _len) \
- (skb_set_tail_pointer(RTPKT_TO_OSPKT(_pkt), _len))
-
-#define GET_OS_PKT_HEAD(_pkt) \
- (RTPKT_TO_OSPKT(_pkt)->head)
-
-#define GET_OS_PKT_END(_pkt) \
- (RTPKT_TO_OSPKT(_pkt)->end)
-
-#define GET_OS_PKT_NETDEV(_pkt) \
- (RTPKT_TO_OSPKT(_pkt)->dev)
-#define SET_OS_PKT_NETDEV(_pkt, _pNetDev) \
- (RTPKT_TO_OSPKT(_pkt)->dev) = (_pNetDev)
-
-#define GET_OS_PKT_TYPE(_pkt) \
- (RTPKT_TO_OSPKT(_pkt))
-
-#define GET_OS_PKT_NEXT(_pkt) \
- (RTPKT_TO_OSPKT(_pkt)->next)
-
-#define OS_PKT_CLONED(_pkt) skb_cloned(RTPKT_TO_OSPKT(_pkt))
-
-#define OS_NTOHS(_Val) \
- (ntohs(_Val))
-#define OS_HTONS(_Val) \
- (htons(_Val))
-#define OS_NTOHL(_Val) \
- (ntohl(_Val))
-#define OS_HTONL(_Val) \
- (htonl(_Val))
-
-#define CB_OFF 10
-
-/* User Priority */
-#define RTMP_SET_PACKET_UP(_p, _prio) (RTPKT_TO_OSPKT(_p)->cb[CB_OFF+0] = _prio)
-#define RTMP_GET_PACKET_UP(_p) (RTPKT_TO_OSPKT(_p)->cb[CB_OFF+0])
-
-/* Fragment # */
-#define RTMP_SET_PACKET_FRAGMENTS(_p, _num) (RTPKT_TO_OSPKT(_p)->cb[CB_OFF+1] = _num)
-#define RTMP_GET_PACKET_FRAGMENTS(_p) (RTPKT_TO_OSPKT(_p)->cb[CB_OFF+1])
-
-/* 0x0 ~0x7f: TX to AP's own BSS which has the specified AID. if AID>127, set bit 7 in RTMP_SET_PACKET_EMACTAB too. */
-/*(this value also as MAC(on-chip WCID) table index) */
-/* 0x80~0xff: TX to a WDS link. b0~6: WDS index */
-#define RTMP_SET_PACKET_WCID(_p, _wdsidx) (RTPKT_TO_OSPKT(_p)->cb[CB_OFF+2] = _wdsidx)
-#define RTMP_GET_PACKET_WCID(_p) ((u8)(RTPKT_TO_OSPKT(_p)->cb[CB_OFF+2]))
-
-/* 0xff: PKTSRC_NDIS, others: local TX buffer index. This value affects how to a packet */
-#define RTMP_SET_PACKET_SOURCE(_p, _pktsrc) (RTPKT_TO_OSPKT(_p)->cb[CB_OFF+3] = _pktsrc)
-#define RTMP_GET_PACKET_SOURCE(_p) (RTPKT_TO_OSPKT(_p)->cb[CB_OFF+3])
-
-/* RTS/CTS-to-self protection method */
-#define RTMP_SET_PACKET_RTS(_p, _num) (RTPKT_TO_OSPKT(_p)->cb[CB_OFF+4] = _num)
-#define RTMP_GET_PACKET_RTS(_p) (RTPKT_TO_OSPKT(_p)->cb[CB_OFF+4])
-/* see RTMP_S(G)ET_PACKET_EMACTAB */
-
-/* TX rate index */
-#define RTMP_SET_PACKET_TXRATE(_p, _rate) (RTPKT_TO_OSPKT(_p)->cb[CB_OFF+5] = _rate)
-#define RTMP_GET_PACKET_TXRATE(_p) (RTPKT_TO_OSPKT(_p)->cb[CB_OFF+5])
-
-/* From which Interface */
-#define RTMP_SET_PACKET_IF(_p, _ifdx) (RTPKT_TO_OSPKT(_p)->cb[CB_OFF+6] = _ifdx)
-#define RTMP_GET_PACKET_IF(_p) (RTPKT_TO_OSPKT(_p)->cb[CB_OFF+6])
-#define RTMP_SET_PACKET_NET_DEVICE_MBSSID(_p, _bss) RTMP_SET_PACKET_IF((_p), (_bss))
-#define RTMP_SET_PACKET_NET_DEVICE_WDS(_p, _bss) RTMP_SET_PACKET_IF((_p), ((_bss) + MIN_NET_DEVICE_FOR_WDS))
-#define RTMP_SET_PACKET_NET_DEVICE_APCLI(_p, _idx) RTMP_SET_PACKET_IF((_p), ((_idx) + MIN_NET_DEVICE_FOR_APCLI))
-#define RTMP_SET_PACKET_NET_DEVICE_MESH(_p, _idx) RTMP_SET_PACKET_IF((_p), ((_idx) + MIN_NET_DEVICE_FOR_MESH))
-#define RTMP_GET_PACKET_NET_DEVICE_MBSSID(_p) RTMP_GET_PACKET_IF((_p))
-#define RTMP_GET_PACKET_NET_DEVICE(_p) RTMP_GET_PACKET_IF((_p))
-
-#define RTMP_SET_PACKET_MOREDATA(_p, _morebit) (RTPKT_TO_OSPKT(_p)->cb[CB_OFF+7] = _morebit)
-#define RTMP_GET_PACKET_MOREDATA(_p) (RTPKT_TO_OSPKT(_p)->cb[CB_OFF+7])
-
-/* */
-/* Specific Packet Type definition */
-/* */
-#define RTMP_PACKET_SPECIFIC_CB_OFFSET 11
-
-#define RTMP_PACKET_SPECIFIC_DHCP 0x01
-#define RTMP_PACKET_SPECIFIC_EAPOL 0x02
-#define RTMP_PACKET_SPECIFIC_IPV4 0x04
-#define RTMP_PACKET_SPECIFIC_WAI 0x08
-#define RTMP_PACKET_SPECIFIC_VLAN 0x10
-#define RTMP_PACKET_SPECIFIC_LLCSNAP 0x20
-
-/*Specific */
-#define RTMP_SET_PACKET_SPECIFIC(_p, _flg) (RTPKT_TO_OSPKT(_p)->cb[CB_OFF+11] = _flg)
-
-/*DHCP */
-#define RTMP_SET_PACKET_DHCP(_p, _flg) \
- do{ \
- if (_flg) \
- (RTPKT_TO_OSPKT(_p)->cb[CB_OFF+11]) |= (RTMP_PACKET_SPECIFIC_DHCP); \
- else \
- (RTPKT_TO_OSPKT(_p)->cb[CB_OFF+11]) &= (!RTMP_PACKET_SPECIFIC_DHCP); \
- }while(0)
-#define RTMP_GET_PACKET_DHCP(_p) (RTPKT_TO_OSPKT(_p)->cb[CB_OFF+11] & RTMP_PACKET_SPECIFIC_DHCP)
-
-/*EAPOL */
-#define RTMP_SET_PACKET_EAPOL(_p, _flg) \
- do{ \
- if (_flg) \
- (RTPKT_TO_OSPKT(_p)->cb[CB_OFF+11]) |= (RTMP_PACKET_SPECIFIC_EAPOL); \
- else \
- (RTPKT_TO_OSPKT(_p)->cb[CB_OFF+11]) &= (!RTMP_PACKET_SPECIFIC_EAPOL); \
- }while(0)
-#define RTMP_GET_PACKET_EAPOL(_p) (RTPKT_TO_OSPKT(_p)->cb[CB_OFF+11] & RTMP_PACKET_SPECIFIC_EAPOL)
-
-/*WAI */
-#define RTMP_SET_PACKET_WAI(_p, _flg) \
- do{ \
- if (_flg) \
- (RTPKT_TO_OSPKT(_p)->cb[CB_OFF+11]) |= (RTMP_PACKET_SPECIFIC_WAI); \
- else \
- (RTPKT_TO_OSPKT(_p)->cb[CB_OFF+11]) &= (!RTMP_PACKET_SPECIFIC_WAI); \
- }while(0)
-#define RTMP_GET_PACKET_WAI(_p) (RTPKT_TO_OSPKT(_p)->cb[CB_OFF+11] & RTMP_PACKET_SPECIFIC_WAI)
-
-#define RTMP_GET_PACKET_LOWRATE(_p) (RTPKT_TO_OSPKT(_p)->cb[CB_OFF+11] & (RTMP_PACKET_SPECIFIC_EAPOL | RTMP_PACKET_SPECIFIC_DHCP | RTMP_PACKET_SPECIFIC_WAI))
-
-/*VLAN */
-#define RTMP_SET_PACKET_VLAN(_p, _flg) \
- do{ \
- if (_flg) \
- (RTPKT_TO_OSPKT(_p)->cb[CB_OFF+11]) |= (RTMP_PACKET_SPECIFIC_VLAN); \
- else \
- (RTPKT_TO_OSPKT(_p)->cb[CB_OFF+11]) &= (!RTMP_PACKET_SPECIFIC_VLAN); \
- }while(0)
-#define RTMP_GET_PACKET_VLAN(_p) (RTPKT_TO_OSPKT(_p)->cb[CB_OFF+11] & RTMP_PACKET_SPECIFIC_VLAN)
-
-/*LLC/SNAP */
-#define RTMP_SET_PACKET_LLCSNAP(_p, _flg) \
- do{ \
- if (_flg) \
- (RTPKT_TO_OSPKT(_p)->cb[CB_OFF+11]) |= (RTMP_PACKET_SPECIFIC_LLCSNAP); \
- else \
- (RTPKT_TO_OSPKT(_p)->cb[CB_OFF+11]) &= (!RTMP_PACKET_SPECIFIC_LLCSNAP); \
- }while(0)
-
-#define RTMP_GET_PACKET_LLCSNAP(_p) (RTPKT_TO_OSPKT(_p)->cb[CB_OFF+11] & RTMP_PACKET_SPECIFIC_LLCSNAP)
-
-/* IP */
-#define RTMP_SET_PACKET_IPV4(_p, _flg) \
- do{ \
- if (_flg) \
- (RTPKT_TO_OSPKT(_p)->cb[CB_OFF+11]) |= (RTMP_PACKET_SPECIFIC_IPV4); \
- else \
- (RTPKT_TO_OSPKT(_p)->cb[CB_OFF+11]) &= (!RTMP_PACKET_SPECIFIC_IPV4); \
- }while(0)
-
-#define RTMP_GET_PACKET_IPV4(_p) (RTPKT_TO_OSPKT(_p)->cb[CB_OFF+11] & RTMP_PACKET_SPECIFIC_IPV4)
-
-/* If this flag is set, it indicates that this EAPoL frame MUST be clear. */
-#define RTMP_SET_PACKET_CLEAR_EAP_FRAME(_p, _flg) (RTPKT_TO_OSPKT(_p)->cb[CB_OFF+12] = _flg)
-#define RTMP_GET_PACKET_CLEAR_EAP_FRAME(_p) (RTPKT_TO_OSPKT(_p)->cb[CB_OFF+12])
-
-/* use bit3 of cb[CB_OFF+16] */
-
-#define RTMP_SET_PACKET_5VT(_p, _flg) (RTPKT_TO_OSPKT(_p)->cb[CB_OFF+22] = _flg)
-#define RTMP_GET_PACKET_5VT(_p) (RTPKT_TO_OSPKT(_p)->cb[CB_OFF+22])
-
-/* Max skb->cb = 48B = [CB_OFF+38] */
-
-/***********************************************************************************
- * Other function prototypes definitions
- ***********************************************************************************/
-void RTMP_GetCurrentSystemTime(LARGE_INTEGER *time);
-int rt28xx_packet_xmit(struct sk_buff *skb);
-
-#ifdef RTMP_MAC_PCI
-/* function declarations */
-#define IRQ_HANDLE_TYPE irqreturn_t
-
-IRQ_HANDLE_TYPE rt2860_interrupt(int irq, void *dev_instance);
-#endif /* RTMP_MAC_PCI // */
-
-int rt28xx_sta_ioctl(struct net_device *net_dev, IN OUT struct ifreq *rq, int cmd);
-
-extern int ra_mtd_write(int num, loff_t to, size_t len, const u_char *buf);
-extern int ra_mtd_read(int num, loff_t from, size_t len, u_char *buf);
-
-#define GET_PAD_FROM_NET_DEV(_pAd, _net_dev) (_pAd) = (struct rt_rtmp_adapter *)(_net_dev)->ml_priv;
-
-#endif /* __RT_LINUX_H__ // */
diff --git a/drivers/staging/rt2860/rt_main_dev.c b/drivers/staging/rt2860/rt_main_dev.c
deleted file mode 100644
index 236dd36..0000000
--- a/drivers/staging/rt2860/rt_main_dev.c
+++ /dev/null
@@ -1,736 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- rt_main_dev.c
-
- Abstract:
- Create and register network interface.
-
- Revision History:
- Who When What
- Justin P. Mattock 11/07/2010 Fix typos in comments
- -------- ---------- ----------------------------------------------
-*/
-
-#include "rt_config.h"
-
-/*---------------------------------------------------------------------*/
-/* Private Variables Used */
-/*---------------------------------------------------------------------*/
-
-char *mac = ""; /* default 00:00:00:00:00:00 */
-char *hostname = ""; /* default CMPC */
-module_param(mac, charp, 0);
-MODULE_PARM_DESC(mac, "rt28xx: wireless mac addr");
-
-/*---------------------------------------------------------------------*/
-/* Prototypes of Functions Used */
-/*---------------------------------------------------------------------*/
-
-/* public function prototype */
-int rt28xx_close(IN struct net_device *net_dev);
-int rt28xx_open(struct net_device *net_dev);
-
-/* private function prototype */
-static int rt28xx_send_packets(IN struct sk_buff *skb_p,
- IN struct net_device *net_dev);
-
-static struct net_device_stats *RT28xx_get_ether_stats(IN struct net_device
- *net_dev);
-
-/*
-========================================================================
-Routine Description:
- Close raxx interface.
-
-Arguments:
- *net_dev the raxx interface pointer
-
-Return Value:
- 0 Open OK
- otherwise Open Fail
-
-Note:
- 1. if open fail, kernel will not call the close function.
- 2. Free memory for
- (1) Mlme Memory Handler: MlmeHalt()
- (2) TX & RX: RTMPFreeTxRxRingMemory()
- (3) BA Reordering: ba_reordering_resource_release()
-========================================================================
-*/
-int MainVirtualIF_close(IN struct net_device *net_dev)
-{
- struct rt_rtmp_adapter *pAd = NULL;
-
- GET_PAD_FROM_NET_DEV(pAd, net_dev);
-
- /* Sanity check for pAd */
- if (pAd == NULL)
- return 0; /* close ok */
-
- netif_carrier_off(pAd->net_dev);
- netif_stop_queue(pAd->net_dev);
-
- {
- BOOLEAN Cancelled;
-
- if (INFRA_ON(pAd) &&
- (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST))) {
- struct rt_mlme_disassoc_req DisReq;
- struct rt_mlme_queue_elem *MsgElem =
- kmalloc(sizeof(struct rt_mlme_queue_elem),
- MEM_ALLOC_FLAG);
-
- if (MsgElem) {
- COPY_MAC_ADDR(DisReq.Addr,
- pAd->CommonCfg.Bssid);
- DisReq.Reason = REASON_DEAUTH_STA_LEAVING;
-
- MsgElem->Machine = ASSOC_STATE_MACHINE;
- MsgElem->MsgType = MT2_MLME_DISASSOC_REQ;
- MsgElem->MsgLen =
- sizeof(struct rt_mlme_disassoc_req);
- NdisMoveMemory(MsgElem->Msg, &DisReq,
- sizeof
- (struct rt_mlme_disassoc_req));
-
- /* Prevent to connect AP again in STAMlmePeriodicExec */
- pAd->MlmeAux.AutoReconnectSsidLen = 32;
- NdisZeroMemory(pAd->MlmeAux.AutoReconnectSsid,
- pAd->MlmeAux.
- AutoReconnectSsidLen);
-
- pAd->Mlme.CntlMachine.CurrState =
- CNTL_WAIT_OID_DISASSOC;
- MlmeDisassocReqAction(pAd, MsgElem);
- kfree(MsgElem);
- }
-
- RTMPusecDelay(1000);
- }
-
- RTMPCancelTimer(&pAd->StaCfg.StaQuickResponeForRateUpTimer,
- &Cancelled);
- RTMPCancelTimer(&pAd->StaCfg.WpaDisassocAndBlockAssocTimer,
- &Cancelled);
- }
-
- VIRTUAL_IF_DOWN(pAd);
-
- RT_MOD_DEC_USE_COUNT();
-
- return 0; /* close ok */
-}
-
-/*
-========================================================================
-Routine Description:
- Open raxx interface.
-
-Arguments:
- *net_dev the raxx interface pointer
-
-Return Value:
- 0 Open OK
- otherwise Open Fail
-
-Note:
- 1. if open fail, kernel will not call the close function.
- 2. Free memory for
- (1) Mlme Memory Handler: MlmeHalt()
- (2) TX & RX: RTMPFreeTxRxRingMemory()
- (3) BA Reordering: ba_reordering_resource_release()
-========================================================================
-*/
-int MainVirtualIF_open(IN struct net_device *net_dev)
-{
- struct rt_rtmp_adapter *pAd = NULL;
-
- GET_PAD_FROM_NET_DEV(pAd, net_dev);
-
- /* Sanity check for pAd */
- if (pAd == NULL)
- return 0; /* close ok */
-
- if (VIRTUAL_IF_UP(pAd) != 0)
- return -1;
-
- /* increase MODULE use count */
- RT_MOD_INC_USE_COUNT();
-
- netif_start_queue(net_dev);
- netif_carrier_on(net_dev);
- netif_wake_queue(net_dev);
-
- return 0;
-}
-
-/*
-========================================================================
-Routine Description:
- Close raxx interface.
-
-Arguments:
- *net_dev the raxx interface pointer
-
-Return Value:
- 0 Open OK
- otherwise Open Fail
-
-Note:
- 1. if open fail, kernel will not call the close function.
- 2. Free memory for
- (1) Mlme Memory Handler: MlmeHalt()
- (2) TX & RX: RTMPFreeTxRxRingMemory()
- (3) BA Reordering: ba_reordering_resource_release()
-========================================================================
-*/
-int rt28xx_close(struct net_device *dev)
-{
- struct net_device *net_dev = (struct net_device *)dev;
- struct rt_rtmp_adapter *pAd = NULL;
- BOOLEAN Cancelled;
- u32 i = 0;
-
-#ifdef RTMP_MAC_USB
- DECLARE_WAIT_QUEUE_HEAD_ONSTACK(unlink_wakeup);
- DECLARE_WAITQUEUE(wait, current);
-#endif /* RTMP_MAC_USB // */
-
- GET_PAD_FROM_NET_DEV(pAd, net_dev);
-
- DBGPRINT(RT_DEBUG_TRACE, ("===> rt28xx_close\n"));
-
- Cancelled = FALSE;
- /* Sanity check for pAd */
- if (pAd == NULL)
- return 0; /* close ok */
-
- {
-#ifdef RTMP_MAC_PCI
- RTMPPCIeLinkCtrlValueRestore(pAd, RESTORE_CLOSE);
-#endif /* RTMP_MAC_PCI // */
-
- /* If driver doesn't wake up firmware here, */
- /* NICLoadFirmware will hang forever when interface is up again. */
- if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_DOZE)) {
- AsicForceWakeup(pAd, TRUE);
- }
-#ifdef RTMP_MAC_USB
- RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_REMOVE_IN_PROGRESS);
-#endif /* RTMP_MAC_USB // */
-
- MlmeRadioOff(pAd);
-#ifdef RTMP_MAC_PCI
- pAd->bPCIclkOff = FALSE;
-#endif /* RTMP_MAC_PCI // */
- }
-
- RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS);
-
- for (i = 0; i < NUM_OF_TX_RING; i++) {
- while (pAd->DeQueueRunning[i] == TRUE) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("Waiting for TxQueue[%d] done..........\n",
- i));
- RTMPusecDelay(1000);
- }
- }
-
-#ifdef RTMP_MAC_USB
- /* ensure there are no more active urbs. */
- add_wait_queue(&unlink_wakeup, &wait);
- pAd->wait = &unlink_wakeup;
-
- /* maybe wait for deletions to finish. */
- i = 0;
- /*while((i < 25) && atomic_read(&pAd->PendingRx) > 0) */
- while (i < 25) {
- unsigned long IrqFlags;
-
- RTMP_IRQ_LOCK(&pAd->BulkInLock, IrqFlags);
- if (pAd->PendingRx == 0) {
- RTMP_IRQ_UNLOCK(&pAd->BulkInLock, IrqFlags);
- break;
- }
- RTMP_IRQ_UNLOCK(&pAd->BulkInLock, IrqFlags);
-
- msleep(UNLINK_TIMEOUT_MS); /*Time in millisecond */
- i++;
- }
- pAd->wait = NULL;
- remove_wait_queue(&unlink_wakeup, &wait);
-#endif /* RTMP_MAC_USB // */
-
- /* Stop Mlme state machine */
- MlmeHalt(pAd);
-
- /* Close net tasklets */
- RtmpNetTaskExit(pAd);
-
- {
- MacTableReset(pAd);
- }
-
- MeasureReqTabExit(pAd);
- TpcReqTabExit(pAd);
-
- /* Close kernel threads */
- RtmpMgmtTaskExit(pAd);
-
-#ifdef RTMP_MAC_PCI
- {
- BOOLEAN brc;
- /* unsigned long Value; */
-
- if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_ACTIVE)) {
- RTMP_ASIC_INTERRUPT_DISABLE(pAd);
- }
- /* Receive packets to clear DMA index after disable interrupt. */
- /* RTMPHandleRxDoneInterrupt(pAd); */
- /* put radio off to save power when driver unloads. After radiooff, can't write/read register, so need to finish all. */
- /* register access before Radio off. */
-
- brc = RT28xxPciAsicRadioOff(pAd, RTMP_HALT, 0);
-
-/*In solution 3 of 3090F, the bPCIclkOff will be set to TRUE after calling RT28xxPciAsicRadioOff */
- pAd->bPCIclkOff = FALSE;
-
- if (brc == FALSE) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("%s call RT28xxPciAsicRadioOff fail!\n",
- __func__));
- }
- }
-
-/*
- if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_ACTIVE))
- {
- RTMP_ASIC_INTERRUPT_DISABLE(pAd);
- }
-
- // Disable Rx, register value supposed will remain after reset
- NICIssueReset(pAd);
-*/
-#endif /* RTMP_MAC_PCI // */
-
- /* Free IRQ */
- if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_IN_USE)) {
-#ifdef RTMP_MAC_PCI
- /* Deregister interrupt function */
- RtmpOSIRQRelease(net_dev);
-#endif /* RTMP_MAC_PCI // */
- RTMP_CLEAR_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_IN_USE);
- }
- /* Free Ring or USB buffers */
- RTMPFreeTxRxRingMemory(pAd);
-
- RTMP_CLEAR_FLAG(pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS);
-
- /* Free BA reorder resource */
- ba_reordering_resource_release(pAd);
-
- RTMP_CLEAR_FLAG(pAd, fRTMP_ADAPTER_START_UP);
-
-/*+++Modify by woody to solve the bulk fail+++*/
- {
- }
-
- DBGPRINT(RT_DEBUG_TRACE, ("<=== rt28xx_close\n"));
- return 0; /* close ok */
-} /* End of rt28xx_close */
-
-/*
-========================================================================
-Routine Description:
- Open raxx interface.
-
-Arguments:
- *net_dev the raxx interface pointer
-
-Return Value:
- 0 Open OK
- otherwise Open Fail
-
-Note:
-========================================================================
-*/
-int rt28xx_open(struct net_device *dev)
-{
- struct net_device *net_dev = (struct net_device *)dev;
- struct rt_rtmp_adapter *pAd = NULL;
- int retval = 0;
- /*struct os_cookie *pObj; */
-
- GET_PAD_FROM_NET_DEV(pAd, net_dev);
-
- /* Sanity check for pAd */
- if (pAd == NULL) {
- /* if 1st open fail, pAd will be free;
- So the net_dev->ml_priv will be NULL in 2rd open */
- return -1;
- }
-
- if (net_dev->priv_flags == INT_MAIN) {
- if (pAd->OpMode == OPMODE_STA)
- net_dev->wireless_handlers =
- (struct iw_handler_def *)&rt28xx_iw_handler_def;
- }
- /* Request interrupt service routine for PCI device */
- /* register the interrupt routine with the os */
- RtmpOSIRQRequest(net_dev);
-
- /* Init IRQ parameters stored in pAd */
- RTMP_IRQ_INIT(pAd);
-
- /* Chip & other init */
- if (rt28xx_init(pAd, mac, hostname) == FALSE)
- goto err;
-
- /* Enable Interrupt */
- RTMP_IRQ_ENABLE(pAd);
-
- /* Now Enable RxTx */
- RTMPEnableRxTx(pAd);
- RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_START_UP);
-
- {
- u32 reg = 0;
- RTMP_IO_READ32(pAd, 0x1300, ®); /* clear garbage interrupts */
- printk(KERN_DEBUG "0x1300 = %08x\n", reg);
- }
-
- {
-/* u32 reg; */
-/* u8 byte; */
-/* u16 tmp; */
-
-/* RTMP_IO_READ32(pAd, XIFS_TIME_CFG, ®); */
-
-/* tmp = 0x0805; */
-/* reg = (reg & 0xffff0000) | tmp; */
-/* RTMP_IO_WRITE32(pAd, XIFS_TIME_CFG, reg); */
-
- }
-#ifdef RTMP_MAC_PCI
- RTMPInitPCIeLinkCtrlValue(pAd);
-#endif /* RTMP_MAC_PCI // */
-
- return retval;
-
-err:
-/*+++Add by shiang, move from rt28xx_init() to here. */
- RtmpOSIRQRelease(net_dev);
-/*---Add by shiang, move from rt28xx_init() to here. */
- return -1;
-} /* End of rt28xx_open */
-
-static const struct net_device_ops rt2860_netdev_ops = {
- .ndo_open = MainVirtualIF_open,
- .ndo_stop = MainVirtualIF_close,
- .ndo_do_ioctl = rt28xx_sta_ioctl,
- .ndo_get_stats = RT28xx_get_ether_stats,
- .ndo_validate_addr = NULL,
- .ndo_set_mac_address = eth_mac_addr,
- .ndo_change_mtu = eth_change_mtu,
- .ndo_start_xmit = rt28xx_send_packets,
-};
-
-struct net_device *RtmpPhyNetDevInit(struct rt_rtmp_adapter *pAd,
- struct rt_rtmp_os_netdev_op_hook *pNetDevHook)
-{
- struct net_device *net_dev = NULL;
-/* int Status; */
-
- net_dev =
- RtmpOSNetDevCreate(pAd, INT_MAIN, 0, sizeof(struct rt_rtmp_adapter *),
- INF_MAIN_DEV_NAME);
- if (net_dev == NULL) {
- printk
- ("RtmpPhyNetDevInit(): creation failed for main physical net device!\n");
- return NULL;
- }
-
- NdisZeroMemory((unsigned char *)pNetDevHook,
- sizeof(struct rt_rtmp_os_netdev_op_hook));
- pNetDevHook->netdev_ops = &rt2860_netdev_ops;
- pNetDevHook->priv_flags = INT_MAIN;
- pNetDevHook->needProtcted = FALSE;
-
- net_dev->ml_priv = (void *)pAd;
- pAd->net_dev = net_dev;
-
- return net_dev;
-
-}
-
-/*
-========================================================================
-Routine Description:
- The entry point for Linux kernel sent packet to our driver.
-
-Arguments:
- sk_buff *skb the pointer refer to a sk_buffer.
-
-Return Value:
- 0
-
-Note:
- This function is the entry point of Tx Path for Os delivery packet to
- our driver. You only can put OS-depened & STA/AP common handle procedures
- in here.
-========================================================================
-*/
-int rt28xx_packet_xmit(struct sk_buff *skb)
-{
- struct net_device *net_dev = skb->dev;
- struct rt_rtmp_adapter *pAd = NULL;
- int status = NETDEV_TX_OK;
- void *pPacket = (void *)skb;
-
- GET_PAD_FROM_NET_DEV(pAd, net_dev);
-
- /* RT2870STA does this in RTMPSendPackets() */
-
- {
- /* Drop send request since we are in monitor mode */
- if (MONITOR_ON(pAd)) {
- RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_FAILURE);
- goto done;
- }
- }
-
- /* EapolStart size is 18 */
- if (skb->len < 14) {
- /*printk("bad packet size: %d\n", pkt->len); */
- hex_dump("bad packet", skb->data, skb->len);
- RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_FAILURE);
- goto done;
- }
-
- RTMP_SET_PACKET_5VT(pPacket, 0);
- STASendPackets((void *)pAd, (void **)&pPacket, 1);
-
- status = NETDEV_TX_OK;
-done:
-
- return status;
-}
-
-/*
-========================================================================
-Routine Description:
- Send a packet to WLAN.
-
-Arguments:
- skb_p points to our adapter
- dev_p which WLAN network interface
-
-Return Value:
- 0: transmit successfully
- otherwise: transmit fail
-
-Note:
-========================================================================
-*/
-static int rt28xx_send_packets(IN struct sk_buff *skb_p,
- IN struct net_device *net_dev)
-{
- struct rt_rtmp_adapter *pAd = NULL;
-
- GET_PAD_FROM_NET_DEV(pAd, net_dev);
-
- if (!(net_dev->flags & IFF_UP)) {
- RELEASE_NDIS_PACKET(pAd, (void *)skb_p,
- NDIS_STATUS_FAILURE);
- return NETDEV_TX_OK;
- }
-
- NdisZeroMemory((u8 *)&skb_p->cb[CB_OFF], 15);
- RTMP_SET_PACKET_NET_DEVICE_MBSSID(skb_p, MAIN_MBSSID);
-
- return rt28xx_packet_xmit(skb_p);
-}
-
-/* This function will be called when query /proc */
-struct iw_statistics *rt28xx_get_wireless_stats(IN struct net_device *net_dev)
-{
- struct rt_rtmp_adapter *pAd = NULL;
-
- GET_PAD_FROM_NET_DEV(pAd, net_dev);
-
- DBGPRINT(RT_DEBUG_TRACE, ("rt28xx_get_wireless_stats --->\n"));
-
- pAd->iw_stats.status = 0; /* Status - device dependent for now */
-
- /* link quality */
- if (pAd->OpMode == OPMODE_STA)
- pAd->iw_stats.qual.qual =
- ((pAd->Mlme.ChannelQuality * 12) / 10 + 10);
-
- if (pAd->iw_stats.qual.qual > 100)
- pAd->iw_stats.qual.qual = 100;
-
- if (pAd->OpMode == OPMODE_STA) {
- pAd->iw_stats.qual.level =
- RTMPMaxRssi(pAd, pAd->StaCfg.RssiSample.LastRssi0,
- pAd->StaCfg.RssiSample.LastRssi1,
- pAd->StaCfg.RssiSample.LastRssi2);
- }
-
- pAd->iw_stats.qual.noise = pAd->BbpWriteLatch[66]; /* noise level (dBm) */
-
- pAd->iw_stats.qual.noise += 256 - 143;
- pAd->iw_stats.qual.updated = 1; /* Flags to know if updated */
-#ifdef IW_QUAL_DBM
- pAd->iw_stats.qual.updated |= IW_QUAL_DBM; /* Level + Noise are dBm */
-#endif /* IW_QUAL_DBM // */
-
- pAd->iw_stats.discard.nwid = 0; /* Rx : Wrong nwid/essid */
- pAd->iw_stats.miss.beacon = 0; /* Missed beacons/superframe */
-
- DBGPRINT(RT_DEBUG_TRACE, ("<--- rt28xx_get_wireless_stats\n"));
- return &pAd->iw_stats;
-}
-
-void tbtt_tasklet(unsigned long data)
-{
-/*#define MAX_TX_IN_TBTT (16) */
-
-}
-
-/*
- ========================================================================
-
- Routine Description:
- return ethernet statistics counter
-
- Arguments:
- net_dev Pointer to net_device
-
- Return Value:
- net_device_stats*
-
- Note:
-
- ========================================================================
-*/
-static struct net_device_stats *RT28xx_get_ether_stats(IN struct net_device
- *net_dev)
-{
- struct rt_rtmp_adapter *pAd = NULL;
-
- if (net_dev)
- GET_PAD_FROM_NET_DEV(pAd, net_dev);
-
- if (pAd) {
-
- pAd->stats.rx_packets =
- pAd->WlanCounters.ReceivedFragmentCount.QuadPart;
- pAd->stats.tx_packets =
- pAd->WlanCounters.TransmittedFragmentCount.QuadPart;
-
- pAd->stats.rx_bytes = pAd->RalinkCounters.ReceivedByteCount;
- pAd->stats.tx_bytes = pAd->RalinkCounters.TransmittedByteCount;
-
- pAd->stats.rx_errors = pAd->Counters8023.RxErrors;
- pAd->stats.tx_errors = pAd->Counters8023.TxErrors;
-
- pAd->stats.rx_dropped = 0;
- pAd->stats.tx_dropped = 0;
-
- pAd->stats.multicast = pAd->WlanCounters.MulticastReceivedFrameCount.QuadPart; /* multicast packets received */
- pAd->stats.collisions = pAd->Counters8023.OneCollision + pAd->Counters8023.MoreCollisions; /* Collision packets */
-
- pAd->stats.rx_length_errors = 0;
- pAd->stats.rx_over_errors = pAd->Counters8023.RxNoBuffer; /* receiver ring buff overflow */
- pAd->stats.rx_crc_errors = 0; /*pAd->WlanCounters.FCSErrorCount; // recved pkt with crc error */
- pAd->stats.rx_frame_errors = pAd->Counters8023.RcvAlignmentErrors; /* recv'd frame alignment error */
- pAd->stats.rx_fifo_errors = pAd->Counters8023.RxNoBuffer; /* recv'r fifo overrun */
- pAd->stats.rx_missed_errors = 0; /* receiver missed packet */
-
- /* detailed tx_errors */
- pAd->stats.tx_aborted_errors = 0;
- pAd->stats.tx_carrier_errors = 0;
- pAd->stats.tx_fifo_errors = 0;
- pAd->stats.tx_heartbeat_errors = 0;
- pAd->stats.tx_window_errors = 0;
-
- /* for cslip etc */
- pAd->stats.rx_compressed = 0;
- pAd->stats.tx_compressed = 0;
-
- return &pAd->stats;
- } else
- return NULL;
-}
-
-BOOLEAN RtmpPhyNetDevExit(struct rt_rtmp_adapter *pAd, struct net_device *net_dev)
-{
-
- /* Unregister network device */
- if (net_dev != NULL) {
- printk
- ("RtmpOSNetDevDetach(): RtmpOSNetDeviceDetach(), dev->name=%s!\n",
- net_dev->name);
- RtmpOSNetDevDetach(net_dev);
- }
-
- return TRUE;
-
-}
-
-/*
-========================================================================
-Routine Description:
- Allocate memory for adapter control block.
-
-Arguments:
- pAd Pointer to our adapter
-
-Return Value:
- NDIS_STATUS_SUCCESS
- NDIS_STATUS_FAILURE
- NDIS_STATUS_RESOURCES
-
-Note:
-========================================================================
-*/
-int AdapterBlockAllocateMemory(void *handle, void ** ppAd)
-{
-
- *ppAd = vmalloc(sizeof(struct rt_rtmp_adapter));
- /* pci_alloc_consistent(pci_dev, sizeof(struct rt_rtmp_adapter), phy_addr); */
-
- if (*ppAd) {
- NdisZeroMemory(*ppAd, sizeof(struct rt_rtmp_adapter));
- ((struct rt_rtmp_adapter *)*ppAd)->OS_Cookie = handle;
- return NDIS_STATUS_SUCCESS;
- } else {
- return NDIS_STATUS_FAILURE;
- }
-}
diff --git a/drivers/staging/rt2860/rt_pci_rbus.c b/drivers/staging/rt2860/rt_pci_rbus.c
deleted file mode 100644
index f80ab4e..0000000
--- a/drivers/staging/rt2860/rt_pci_rbus.c
+++ /dev/null
@@ -1,837 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- rt_pci_rbus.c
-
- Abstract:
- Create and register network interface.
-
- Revision History:
- Who When What
- Justin P. Mattock 11/07/2010 Fix a typo
- -------- ---------- ----------------------------------------------
-*/
-
-#include "rt_config.h"
-#include <linux/pci.h>
-
-IRQ_HANDLE_TYPE rt2860_interrupt(int irq, void *dev_instance);
-
-static void rx_done_tasklet(unsigned long data);
-static void mgmt_dma_done_tasklet(unsigned long data);
-static void ac0_dma_done_tasklet(unsigned long data);
-static void ac1_dma_done_tasklet(unsigned long data);
-static void ac2_dma_done_tasklet(unsigned long data);
-static void ac3_dma_done_tasklet(unsigned long data);
-static void fifo_statistic_full_tasklet(unsigned long data);
-
-/*---------------------------------------------------------------------*/
-/* Symbol & Macro Definitions */
-/*---------------------------------------------------------------------*/
-#define RT2860_INT_RX_DLY (1<<0) /* bit 0 */
-#define RT2860_INT_TX_DLY (1<<1) /* bit 1 */
-#define RT2860_INT_RX_DONE (1<<2) /* bit 2 */
-#define RT2860_INT_AC0_DMA_DONE (1<<3) /* bit 3 */
-#define RT2860_INT_AC1_DMA_DONE (1<<4) /* bit 4 */
-#define RT2860_INT_AC2_DMA_DONE (1<<5) /* bit 5 */
-#define RT2860_INT_AC3_DMA_DONE (1<<6) /* bit 6 */
-#define RT2860_INT_HCCA_DMA_DONE (1<<7) /* bit 7 */
-#define RT2860_INT_MGMT_DONE (1<<8) /* bit 8 */
-
-#define INT_RX RT2860_INT_RX_DONE
-
-#define INT_AC0_DLY (RT2860_INT_AC0_DMA_DONE) /*| RT2860_INT_TX_DLY) */
-#define INT_AC1_DLY (RT2860_INT_AC1_DMA_DONE) /*| RT2860_INT_TX_DLY) */
-#define INT_AC2_DLY (RT2860_INT_AC2_DMA_DONE) /*| RT2860_INT_TX_DLY) */
-#define INT_AC3_DLY (RT2860_INT_AC3_DMA_DONE) /*| RT2860_INT_TX_DLY) */
-#define INT_HCCA_DLY (RT2860_INT_HCCA_DMA_DONE) /*| RT2860_INT_TX_DLY) */
-#define INT_MGMT_DLY RT2860_INT_MGMT_DONE
-
-/***************************************************************************
- *
- * Interface-depended memory allocation/Free related procedures.
- * Mainly for Hardware TxDesc/RxDesc/MgmtDesc, DMA Memory for TxData/RxData, etc.,
- *
- **************************************************************************/
-/* Function for TxDesc Memory allocation. */
-void RTMP_AllocateTxDescMemory(struct rt_rtmp_adapter *pAd,
- u32 Index,
- unsigned long Length,
- IN BOOLEAN Cached,
- void **VirtualAddress,
- dma_addr_t *PhysicalAddress)
-{
- struct os_cookie *pObj = (struct os_cookie *)pAd->OS_Cookie;
-
- *VirtualAddress =
- (void *)pci_alloc_consistent(pObj->pci_dev, sizeof(char) * Length,
- PhysicalAddress);
-
-}
-
-/* Function for MgmtDesc Memory allocation. */
-void RTMP_AllocateMgmtDescMemory(struct rt_rtmp_adapter *pAd,
- unsigned long Length,
- IN BOOLEAN Cached,
- void **VirtualAddress,
- dma_addr_t *PhysicalAddress)
-{
- struct os_cookie *pObj = (struct os_cookie *)pAd->OS_Cookie;
-
- *VirtualAddress =
- (void *)pci_alloc_consistent(pObj->pci_dev, sizeof(char) * Length,
- PhysicalAddress);
-
-}
-
-/* Function for RxDesc Memory allocation. */
-void RTMP_AllocateRxDescMemory(struct rt_rtmp_adapter *pAd,
- unsigned long Length,
- IN BOOLEAN Cached,
- void **VirtualAddress,
- dma_addr_t *PhysicalAddress)
-{
- struct os_cookie *pObj = (struct os_cookie *)pAd->OS_Cookie;
-
- *VirtualAddress =
- (void *)pci_alloc_consistent(pObj->pci_dev, sizeof(char) * Length,
- PhysicalAddress);
-
-}
-
-/* Function for free allocated Desc Memory. */
-void RTMP_FreeDescMemory(struct rt_rtmp_adapter *pAd,
- unsigned long Length,
- void *VirtualAddress,
- dma_addr_t PhysicalAddress)
-{
- struct os_cookie *pObj = (struct os_cookie *)pAd->OS_Cookie;
-
- pci_free_consistent(pObj->pci_dev, Length, VirtualAddress,
- PhysicalAddress);
-}
-
-/* Function for TxData DMA Memory allocation. */
-void RTMP_AllocateFirstTxBuffer(struct rt_rtmp_adapter *pAd,
- u32 Index,
- unsigned long Length,
- IN BOOLEAN Cached,
- void **VirtualAddress,
- dma_addr_t *PhysicalAddress)
-{
- struct os_cookie *pObj = (struct os_cookie *)pAd->OS_Cookie;
-
- *VirtualAddress =
- (void *)pci_alloc_consistent(pObj->pci_dev, sizeof(char) * Length,
- PhysicalAddress);
-}
-
-void RTMP_FreeFirstTxBuffer(struct rt_rtmp_adapter *pAd,
- unsigned long Length,
- IN BOOLEAN Cached,
- void *VirtualAddress,
- dma_addr_t PhysicalAddress)
-{
- struct os_cookie *pObj = (struct os_cookie *)pAd->OS_Cookie;
-
- pci_free_consistent(pObj->pci_dev, Length, VirtualAddress,
- PhysicalAddress);
-}
-
-/*
- * FUNCTION: Allocate a common buffer for DMA
- * ARGUMENTS:
- * AdapterHandle: AdapterHandle
- * Length: Number of bytes to allocate
- * Cached: Whether or not the memory can be cached
- * VirtualAddress: Pointer to memory is returned here
- * PhysicalAddress: Physical address corresponding to virtual address
- */
-void RTMP_AllocateSharedMemory(struct rt_rtmp_adapter *pAd,
- unsigned long Length,
- IN BOOLEAN Cached,
- void **VirtualAddress,
- dma_addr_t *PhysicalAddress)
-{
- struct os_cookie *pObj = (struct os_cookie *)pAd->OS_Cookie;
-
- *VirtualAddress =
- (void *)pci_alloc_consistent(pObj->pci_dev, sizeof(char) * Length,
- PhysicalAddress);
-}
-
-/*
- * FUNCTION: Allocate a packet buffer for DMA
- * ARGUMENTS:
- * AdapterHandle: AdapterHandle
- * Length: Number of bytes to allocate
- * Cached: Whether or not the memory can be cached
- * VirtualAddress: Pointer to memory is returned here
- * PhysicalAddress: Physical address corresponding to virtual address
- * Notes:
- * Cached is ignored: always cached memory
- */
-void *RTMP_AllocateRxPacketBuffer(struct rt_rtmp_adapter *pAd,
- unsigned long Length,
- IN BOOLEAN Cached,
- void **VirtualAddress,
- OUT dma_addr_t *
- PhysicalAddress)
-{
- struct sk_buff *pkt;
-
- pkt = dev_alloc_skb(Length);
-
- if (pkt == NULL) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("can't allocate rx %ld size packet\n", Length));
- }
-
- if (pkt) {
- RTMP_SET_PACKET_SOURCE(OSPKT_TO_RTPKT(pkt), PKTSRC_NDIS);
- *VirtualAddress = (void *)pkt->data;
- *PhysicalAddress =
- PCI_MAP_SINGLE(pAd, *VirtualAddress, Length, -1,
- PCI_DMA_FROMDEVICE);
- } else {
- *VirtualAddress = (void *)NULL;
- *PhysicalAddress = (dma_addr_t)NULL;
- }
-
- return (void *)pkt;
-}
-
-void Invalid_Remaining_Packet(struct rt_rtmp_adapter *pAd, unsigned long VirtualAddress)
-{
- dma_addr_t PhysicalAddress;
-
- PhysicalAddress =
- PCI_MAP_SINGLE(pAd, (void *)(VirtualAddress + 1600),
- RX_BUFFER_NORMSIZE - 1600, -1, PCI_DMA_FROMDEVICE);
-}
-
-int RtmpNetTaskInit(struct rt_rtmp_adapter *pAd)
-{
- struct os_cookie *pObj;
-
- pObj = (struct os_cookie *)pAd->OS_Cookie;
-
- tasklet_init(&pObj->rx_done_task, rx_done_tasklet, (unsigned long)pAd);
- tasklet_init(&pObj->mgmt_dma_done_task, mgmt_dma_done_tasklet,
- (unsigned long)pAd);
- tasklet_init(&pObj->ac0_dma_done_task, ac0_dma_done_tasklet,
- (unsigned long)pAd);
- tasklet_init(&pObj->ac1_dma_done_task, ac1_dma_done_tasklet,
- (unsigned long)pAd);
- tasklet_init(&pObj->ac2_dma_done_task, ac2_dma_done_tasklet,
- (unsigned long)pAd);
- tasklet_init(&pObj->ac3_dma_done_task, ac3_dma_done_tasklet,
- (unsigned long)pAd);
- tasklet_init(&pObj->tbtt_task, tbtt_tasklet, (unsigned long)pAd);
- tasklet_init(&pObj->fifo_statistic_full_task,
- fifo_statistic_full_tasklet, (unsigned long)pAd);
-
- return NDIS_STATUS_SUCCESS;
-}
-
-void RtmpNetTaskExit(struct rt_rtmp_adapter *pAd)
-{
- struct os_cookie *pObj;
-
- pObj = (struct os_cookie *)pAd->OS_Cookie;
-
- tasklet_kill(&pObj->rx_done_task);
- tasklet_kill(&pObj->mgmt_dma_done_task);
- tasklet_kill(&pObj->ac0_dma_done_task);
- tasklet_kill(&pObj->ac1_dma_done_task);
- tasklet_kill(&pObj->ac2_dma_done_task);
- tasklet_kill(&pObj->ac3_dma_done_task);
- tasklet_kill(&pObj->tbtt_task);
- tasklet_kill(&pObj->fifo_statistic_full_task);
-}
-
-int RtmpMgmtTaskInit(struct rt_rtmp_adapter *pAd)
-{
-
- return NDIS_STATUS_SUCCESS;
-}
-
-/*
-========================================================================
-Routine Description:
- Close kernel threads.
-
-Arguments:
- *pAd the raxx interface data pointer
-
-Return Value:
- NONE
-
-Note:
-========================================================================
-*/
-void RtmpMgmtTaskExit(struct rt_rtmp_adapter *pAd)
-{
-
- return;
-}
-
-static inline void rt2860_int_enable(struct rt_rtmp_adapter *pAd, unsigned int mode)
-{
- u32 regValue;
-
- pAd->int_disable_mask &= ~(mode);
- regValue = pAd->int_enable_reg & ~(pAd->int_disable_mask);
- /*if (!OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_DOZE)) */
- {
- RTMP_IO_WRITE32(pAd, INT_MASK_CSR, regValue); /* 1:enable */
- }
- /*else */
- /* DBGPRINT(RT_DEBUG_TRACE, ("fOP_STATUS_DOZE !\n")); */
-
- if (regValue != 0)
- RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_ACTIVE);
-}
-
-static inline void rt2860_int_disable(struct rt_rtmp_adapter *pAd, unsigned int mode)
-{
- u32 regValue;
-
- pAd->int_disable_mask |= mode;
- regValue = pAd->int_enable_reg & ~(pAd->int_disable_mask);
- RTMP_IO_WRITE32(pAd, INT_MASK_CSR, regValue); /* 0: disable */
-
- if (regValue == 0) {
- RTMP_CLEAR_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_ACTIVE);
- }
-}
-
-/***************************************************************************
- *
- * tasklet related procedures.
- *
- **************************************************************************/
-static void mgmt_dma_done_tasklet(unsigned long data)
-{
- unsigned long flags;
- struct rt_rtmp_adapter *pAd = (struct rt_rtmp_adapter *)data;
- INT_SOURCE_CSR_STRUC IntSource;
- struct os_cookie *pObj;
-
- /* Do nothing if the driver is starting halt state. */
- /* This might happen when timer already been fired before cancel timer with mlmehalt */
- if (RTMP_TEST_FLAG
- (pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS | fRTMP_ADAPTER_NIC_NOT_EXIST))
- return;
-
- pObj = (struct os_cookie *)pAd->OS_Cookie;
-
-/* printk("mgmt_dma_done_process\n"); */
- IntSource.word = 0;
- IntSource.field.MgmtDmaDone = 1;
- pAd->int_pending &= ~INT_MGMT_DLY;
-
- RTMPHandleMgmtRingDmaDoneInterrupt(pAd);
-
- /* if you use RTMP_SEM_LOCK, sometimes kernel will hang up, without any */
- /* bug report output */
- RTMP_INT_LOCK(&pAd->irq_lock, flags);
- /*
- * double check to avoid lose of interrupts
- */
- if (pAd->int_pending & INT_MGMT_DLY) {
- tasklet_hi_schedule(&pObj->mgmt_dma_done_task);
- RTMP_INT_UNLOCK(&pAd->irq_lock, flags);
- return;
- }
-
- /* enable TxDataInt again */
- rt2860_int_enable(pAd, INT_MGMT_DLY);
- RTMP_INT_UNLOCK(&pAd->irq_lock, flags);
-}
-
-static void rx_done_tasklet(unsigned long data)
-{
- unsigned long flags;
- struct rt_rtmp_adapter *pAd = (struct rt_rtmp_adapter *)data;
- BOOLEAN bReschedule = 0;
- struct os_cookie *pObj;
-
- /* Do nothing if the driver is starting halt state. */
- /* This might happen when timer already been fired before cancel timer with mlmehalt */
- if (RTMP_TEST_FLAG
- (pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS | fRTMP_ADAPTER_NIC_NOT_EXIST))
- return;
-
- pObj = (struct os_cookie *)pAd->OS_Cookie;
-
- pAd->int_pending &= ~(INT_RX);
- bReschedule = STARxDoneInterruptHandle(pAd, 0);
-
- RTMP_INT_LOCK(&pAd->irq_lock, flags);
- /*
- * double check to avoid rotting packet
- */
- if (pAd->int_pending & INT_RX || bReschedule) {
- tasklet_hi_schedule(&pObj->rx_done_task);
- RTMP_INT_UNLOCK(&pAd->irq_lock, flags);
- return;
- }
-
- /* enable Rxint again */
- rt2860_int_enable(pAd, INT_RX);
- RTMP_INT_UNLOCK(&pAd->irq_lock, flags);
-
-}
-
-void fifo_statistic_full_tasklet(unsigned long data)
-{
- unsigned long flags;
- struct rt_rtmp_adapter *pAd = (struct rt_rtmp_adapter *)data;
- struct os_cookie *pObj;
-
- /* Do nothing if the driver is starting halt state. */
- /* This might happen when timer already been fired before cancel timer with mlmehalt */
- if (RTMP_TEST_FLAG
- (pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS | fRTMP_ADAPTER_NIC_NOT_EXIST))
- return;
-
- pObj = (struct os_cookie *)pAd->OS_Cookie;
-
- pAd->int_pending &= ~(FifoStaFullInt);
- NICUpdateFifoStaCounters(pAd);
-
- RTMP_INT_LOCK(&pAd->irq_lock, flags);
- /*
- * double check to avoid rotting packet
- */
- if (pAd->int_pending & FifoStaFullInt) {
- tasklet_hi_schedule(&pObj->fifo_statistic_full_task);
- RTMP_INT_UNLOCK(&pAd->irq_lock, flags);
- return;
- }
-
- /* enable Rxint again */
-
- rt2860_int_enable(pAd, FifoStaFullInt);
- RTMP_INT_UNLOCK(&pAd->irq_lock, flags);
-
-}
-
-static void ac3_dma_done_tasklet(unsigned long data)
-{
- unsigned long flags;
- struct rt_rtmp_adapter *pAd = (struct rt_rtmp_adapter *)data;
- INT_SOURCE_CSR_STRUC IntSource;
- struct os_cookie *pObj;
- BOOLEAN bReschedule = 0;
-
- /* Do nothing if the driver is starting halt state. */
- /* This might happen when timer already been fired before cancel timer with mlmehalt */
- if (RTMP_TEST_FLAG
- (pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS | fRTMP_ADAPTER_NIC_NOT_EXIST))
- return;
-
- pObj = (struct os_cookie *)pAd->OS_Cookie;
-
-/* printk("ac0_dma_done_process\n"); */
- IntSource.word = 0;
- IntSource.field.Ac3DmaDone = 1;
- pAd->int_pending &= ~INT_AC3_DLY;
-
- bReschedule = RTMPHandleTxRingDmaDoneInterrupt(pAd, IntSource);
-
- RTMP_INT_LOCK(&pAd->irq_lock, flags);
- /*
- * double check to avoid lose of interrupts
- */
- if ((pAd->int_pending & INT_AC3_DLY) || bReschedule) {
- tasklet_hi_schedule(&pObj->ac3_dma_done_task);
- RTMP_INT_UNLOCK(&pAd->irq_lock, flags);
- return;
- }
-
- /* enable TxDataInt again */
- rt2860_int_enable(pAd, INT_AC3_DLY);
- RTMP_INT_UNLOCK(&pAd->irq_lock, flags);
-}
-
-static void ac2_dma_done_tasklet(unsigned long data)
-{
- unsigned long flags;
- struct rt_rtmp_adapter *pAd = (struct rt_rtmp_adapter *)data;
- INT_SOURCE_CSR_STRUC IntSource;
- struct os_cookie *pObj;
- BOOLEAN bReschedule = 0;
-
- /* Do nothing if the driver is starting halt state. */
- /* This might happen when timer already been fired before cancel timer with mlmehalt */
- if (RTMP_TEST_FLAG
- (pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS | fRTMP_ADAPTER_NIC_NOT_EXIST))
- return;
-
- pObj = (struct os_cookie *)pAd->OS_Cookie;
-
- IntSource.word = 0;
- IntSource.field.Ac2DmaDone = 1;
- pAd->int_pending &= ~INT_AC2_DLY;
-
- bReschedule = RTMPHandleTxRingDmaDoneInterrupt(pAd, IntSource);
-
- RTMP_INT_LOCK(&pAd->irq_lock, flags);
-
- /*
- * double check to avoid lose of interrupts
- */
- if ((pAd->int_pending & INT_AC2_DLY) || bReschedule) {
- tasklet_hi_schedule(&pObj->ac2_dma_done_task);
- RTMP_INT_UNLOCK(&pAd->irq_lock, flags);
- return;
- }
-
- /* enable TxDataInt again */
- rt2860_int_enable(pAd, INT_AC2_DLY);
- RTMP_INT_UNLOCK(&pAd->irq_lock, flags);
-}
-
-static void ac1_dma_done_tasklet(unsigned long data)
-{
- unsigned long flags;
- struct rt_rtmp_adapter *pAd = (struct rt_rtmp_adapter *)data;
- INT_SOURCE_CSR_STRUC IntSource;
- struct os_cookie *pObj;
- BOOLEAN bReschedule = 0;
-
- /* Do nothing if the driver is starting halt state. */
- /* This might happen when timer already been fired before cancel timer with mlmehalt */
- if (RTMP_TEST_FLAG
- (pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS | fRTMP_ADAPTER_NIC_NOT_EXIST))
- return;
-
- pObj = (struct os_cookie *)pAd->OS_Cookie;
-
-/* printk("ac0_dma_done_process\n"); */
- IntSource.word = 0;
- IntSource.field.Ac1DmaDone = 1;
- pAd->int_pending &= ~INT_AC1_DLY;
-
- bReschedule = RTMPHandleTxRingDmaDoneInterrupt(pAd, IntSource);
-
- RTMP_INT_LOCK(&pAd->irq_lock, flags);
- /*
- * double check to avoid lose of interrupts
- */
- if ((pAd->int_pending & INT_AC1_DLY) || bReschedule) {
- tasklet_hi_schedule(&pObj->ac1_dma_done_task);
- RTMP_INT_UNLOCK(&pAd->irq_lock, flags);
- return;
- }
-
- /* enable TxDataInt again */
- rt2860_int_enable(pAd, INT_AC1_DLY);
- RTMP_INT_UNLOCK(&pAd->irq_lock, flags);
-}
-
-static void ac0_dma_done_tasklet(unsigned long data)
-{
- unsigned long flags;
- struct rt_rtmp_adapter *pAd = (struct rt_rtmp_adapter *)data;
- INT_SOURCE_CSR_STRUC IntSource;
- struct os_cookie *pObj;
- BOOLEAN bReschedule = 0;
-
- /* Do nothing if the driver is starting halt state. */
- /* This might happen when timer already been fired before cancel timer with mlmehalt */
- if (RTMP_TEST_FLAG
- (pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS | fRTMP_ADAPTER_NIC_NOT_EXIST))
- return;
-
- pObj = (struct os_cookie *)pAd->OS_Cookie;
-
-/* printk("ac0_dma_done_process\n"); */
- IntSource.word = 0;
- IntSource.field.Ac0DmaDone = 1;
- pAd->int_pending &= ~INT_AC0_DLY;
-
-/* RTMPHandleMgmtRingDmaDoneInterrupt(pAd); */
- bReschedule = RTMPHandleTxRingDmaDoneInterrupt(pAd, IntSource);
-
- RTMP_INT_LOCK(&pAd->irq_lock, flags);
- /*
- * double check to avoid lose of interrupts
- */
- if ((pAd->int_pending & INT_AC0_DLY) || bReschedule) {
- tasklet_hi_schedule(&pObj->ac0_dma_done_task);
- RTMP_INT_UNLOCK(&pAd->irq_lock, flags);
- return;
- }
-
- /* enable TxDataInt again */
- rt2860_int_enable(pAd, INT_AC0_DLY);
- RTMP_INT_UNLOCK(&pAd->irq_lock, flags);
-}
-
-/***************************************************************************
- *
- * interrupt handler related procedures.
- *
- **************************************************************************/
-int print_int_count;
-
-IRQ_HANDLE_TYPE rt2860_interrupt(int irq, void *dev_instance)
-{
- struct net_device *net_dev = (struct net_device *)dev_instance;
- struct rt_rtmp_adapter *pAd = NULL;
- INT_SOURCE_CSR_STRUC IntSource;
- struct os_cookie *pObj;
-
- GET_PAD_FROM_NET_DEV(pAd, net_dev);
-
- pObj = (struct os_cookie *)pAd->OS_Cookie;
-
- /* Note 03312008: we can not return here before
- RTMP_IO_READ32(pAd, INT_SOURCE_CSR, &IntSource.word);
- RTMP_IO_WRITE32(pAd, INT_SOURCE_CSR, IntSource.word);
- Or kernel will panic after ifconfig ra0 down sometimes */
-
- /* */
- /* Initial the Interrupt source. */
- /* */
- IntSource.word = 0x00000000L;
-/* McuIntSource.word = 0x00000000L; */
-
- /* */
- /* Get the interrupt sources & saved to local variable */
- /* */
- /*RTMP_IO_READ32(pAd, where, &McuIntSource.word); */
- /*RTMP_IO_WRITE32(pAd, , McuIntSource.word); */
-
- /* */
- /* Flag fOP_STATUS_DOZE On, means ASIC put to sleep, elase means ASICK WakeUp */
- /* And at the same time, clock maybe turned off that say there is no DMA service. */
- /* when ASIC get to sleep. */
- /* To prevent system hang on power saving. */
- /* We need to check it before handle the INT_SOURCE_CSR, ASIC must be wake up. */
- /* */
- /* RT2661 => when ASIC is sleeping, MAC register cannot be read and written. */
- /* RT2860 => when ASIC is sleeping, MAC register can be read and written. */
-/* if (!OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_DOZE)) */
- {
- RTMP_IO_READ32(pAd, INT_SOURCE_CSR, &IntSource.word);
- RTMP_IO_WRITE32(pAd, INT_SOURCE_CSR, IntSource.word); /* write 1 to clear */
- }
-/* else */
-/* DBGPRINT(RT_DEBUG_TRACE, (">>>fOP_STATUS_DOZE<<<\n")); */
-
-/* RTMP_IO_READ32(pAd, INT_SOURCE_CSR, &IsrAfterClear); */
-/* RTMP_IO_READ32(pAd, MCU_INT_SOURCE_CSR, &McuIsrAfterClear); */
-/* DBGPRINT(RT_DEBUG_INFO, ("====> RTMPHandleInterrupt(ISR=%08x,Mcu ISR=%08x, After clear ISR=%08x, MCU ISR=%08x)\n", */
-/* IntSource.word, McuIntSource.word, IsrAfterClear, McuIsrAfterClear)); */
-
- /* Do nothing if Reset in progress */
- if (RTMP_TEST_FLAG
- (pAd,
- (fRTMP_ADAPTER_RESET_IN_PROGRESS |
- fRTMP_ADAPTER_HALT_IN_PROGRESS))) {
- return IRQ_HANDLED;
- }
- /* */
- /* Handle interrupt, walk through all bits */
- /* Should start from highest priority interrupt */
- /* The priority can be adjust by altering processing if statement */
- /* */
-
-#ifdef DBG
-
-#endif
-
- pAd->bPCIclkOff = FALSE;
-
- /* If required spinlock, each interrupt service routine has to acquire */
- /* and release itself. */
- /* */
-
- /* Do nothing if NIC doesn't exist */
- if (IntSource.word == 0xffffffff) {
- RTMP_SET_FLAG(pAd,
- (fRTMP_ADAPTER_NIC_NOT_EXIST |
- fRTMP_ADAPTER_HALT_IN_PROGRESS));
- return IRQ_HANDLED;
- }
-
- if (IntSource.word & TxCoherent) {
- DBGPRINT(RT_DEBUG_ERROR, (">>>TxCoherent<<<\n"));
- RTMPHandleRxCoherentInterrupt(pAd);
- }
-
- if (IntSource.word & RxCoherent) {
- DBGPRINT(RT_DEBUG_ERROR, (">>>RxCoherent<<<\n"));
- RTMPHandleRxCoherentInterrupt(pAd);
- }
-
- if (IntSource.word & FifoStaFullInt) {
- if ((pAd->int_disable_mask & FifoStaFullInt) == 0) {
- /* mask FifoStaFullInt */
- rt2860_int_disable(pAd, FifoStaFullInt);
- tasklet_hi_schedule(&pObj->fifo_statistic_full_task);
- }
- pAd->int_pending |= FifoStaFullInt;
- }
-
- if (IntSource.word & INT_MGMT_DLY) {
- if ((pAd->int_disable_mask & INT_MGMT_DLY) == 0) {
- rt2860_int_disable(pAd, INT_MGMT_DLY);
- tasklet_hi_schedule(&pObj->mgmt_dma_done_task);
- }
- pAd->int_pending |= INT_MGMT_DLY;
- }
-
- if (IntSource.word & INT_RX) {
- if ((pAd->int_disable_mask & INT_RX) == 0) {
-
- /* mask Rxint */
- rt2860_int_disable(pAd, INT_RX);
- tasklet_hi_schedule(&pObj->rx_done_task);
- }
- pAd->int_pending |= INT_RX;
- }
-
- if (IntSource.word & INT_AC3_DLY) {
-
- if ((pAd->int_disable_mask & INT_AC3_DLY) == 0) {
- /* mask TxDataInt */
- rt2860_int_disable(pAd, INT_AC3_DLY);
- tasklet_hi_schedule(&pObj->ac3_dma_done_task);
- }
- pAd->int_pending |= INT_AC3_DLY;
- }
-
- if (IntSource.word & INT_AC2_DLY) {
-
- if ((pAd->int_disable_mask & INT_AC2_DLY) == 0) {
- /* mask TxDataInt */
- rt2860_int_disable(pAd, INT_AC2_DLY);
- tasklet_hi_schedule(&pObj->ac2_dma_done_task);
- }
- pAd->int_pending |= INT_AC2_DLY;
- }
-
- if (IntSource.word & INT_AC1_DLY) {
-
- pAd->int_pending |= INT_AC1_DLY;
-
- if ((pAd->int_disable_mask & INT_AC1_DLY) == 0) {
- /* mask TxDataInt */
- rt2860_int_disable(pAd, INT_AC1_DLY);
- tasklet_hi_schedule(&pObj->ac1_dma_done_task);
- }
-
- }
-
- if (IntSource.word & INT_AC0_DLY) {
-
-/*
- if (IntSource.word & 0x2) {
- u32 reg;
- RTMP_IO_READ32(pAd, DELAY_INT_CFG, ®);
- printk("IntSource.word = %08x, DELAY_REG = %08x\n", IntSource.word, reg);
- }
-*/
- pAd->int_pending |= INT_AC0_DLY;
-
- if ((pAd->int_disable_mask & INT_AC0_DLY) == 0) {
- /* mask TxDataInt */
- rt2860_int_disable(pAd, INT_AC0_DLY);
- tasklet_hi_schedule(&pObj->ac0_dma_done_task);
- }
-
- }
-
- if (IntSource.word & PreTBTTInt) {
- RTMPHandlePreTBTTInterrupt(pAd);
- }
-
- if (IntSource.word & TBTTInt) {
- RTMPHandleTBTTInterrupt(pAd);
- }
-
- {
- if (IntSource.word & AutoWakeupInt)
- RTMPHandleTwakeupInterrupt(pAd);
- }
-
- return IRQ_HANDLED;
-}
-
-/*
- * invalid or writeback cache
- * and convert virtual address to physical address
- */
-dma_addr_t linux_pci_map_single(struct rt_rtmp_adapter *pAd, void *ptr,
- size_t size, int sd_idx, int direction)
-{
- struct os_cookie *pObj;
-
- /*
- ------ Porting Information ------
- > For Tx Alloc:
- mgmt packets => sd_idx = 0
- SwIdx: pAd->MgmtRing.TxCpuIdx
- pTxD : pAd->MgmtRing.Cell[SwIdx].AllocVa;
-
- data packets => sd_idx = 1
- TxIdx : pAd->TxRing[pTxBlk->QueIdx].TxCpuIdx
- QueIdx: pTxBlk->QueIdx
- pTxD : pAd->TxRing[pTxBlk->QueIdx].Cell[TxIdx].AllocVa;
-
- > For Rx Alloc:
- sd_idx = -1
- */
-
- pObj = (struct os_cookie *)pAd->OS_Cookie;
-
- if (sd_idx == 1) {
- struct rt_tx_blk *pTxBlk;
- pTxBlk = (struct rt_tx_blk *)ptr;
- return pci_map_single(pObj->pci_dev, pTxBlk->pSrcBufData,
- pTxBlk->SrcBufLen, direction);
- } else {
- return pci_map_single(pObj->pci_dev, ptr, size, direction);
- }
-
-}
-
-void linux_pci_unmap_single(struct rt_rtmp_adapter *pAd, dma_addr_t dma_addr,
- size_t size, int direction)
-{
- struct os_cookie *pObj;
-
- pObj = (struct os_cookie *)pAd->OS_Cookie;
-
- pci_unmap_single(pObj->pci_dev, dma_addr, size, direction);
-
-}
diff --git a/drivers/staging/rt2860/rt_usb.c b/drivers/staging/rt2860/rt_usb.c
deleted file mode 100644
index eb037d2..0000000
--- a/drivers/staging/rt2860/rt_usb.c
+++ /dev/null
@@ -1,794 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- rtusb_bulk.c
-
- Abstract:
-
- Revision History:
- Who When What
- -------- ---------- ----------------------------------------------
- Name Date Modification logs
- Justin P. Mattock 11/07/2010 Fix some typos.
-
-*/
-
-#include "rt_config.h"
-
-void dump_urb(struct urb *purb)
-{
- printk(KERN_DEBUG "urb :0x%08lx\n", (unsigned long)purb);
- printk(KERN_DEBUG "\tdev :0x%08lx\n", (unsigned long)purb->dev);
- printk(KERN_DEBUG "\t\tdev->state :0x%d\n", purb->dev->state);
- printk(KERN_DEBUG "\tpipe :0x%08x\n", purb->pipe);
- printk(KERN_DEBUG "\tstatus :%d\n", purb->status);
- printk(KERN_DEBUG "\ttransfer_flags :0x%08x\n", purb->transfer_flags);
- printk(KERN_DEBUG "\ttransfer_buffer :0x%08lx\n",
- (unsigned long)purb->transfer_buffer);
- printk(KERN_DEBUG "\ttransfer_buffer_length:%d\n", purb->transfer_buffer_length);
- printk(KERN_DEBUG "\tactual_length :%d\n", purb->actual_length);
- printk(KERN_DEBUG "\tsetup_packet :0x%08lx\n",
- (unsigned long)purb->setup_packet);
- printk(KERN_DEBUG "\tstart_frame :%d\n", purb->start_frame);
- printk(KERN_DEBUG "\tnumber_of_packets :%d\n", purb->number_of_packets);
- printk(KERN_DEBUG "\tinterval :%d\n", purb->interval);
- printk(KERN_DEBUG "\terror_count :%d\n", purb->error_count);
- printk(KERN_DEBUG "\tcontext :0x%08lx\n",
- (unsigned long)purb->context);
- printk(KERN_DEBUG "\tcomplete :0x%08lx\n\n",
- (unsigned long)purb->complete);
-}
-
-/*
-========================================================================
-Routine Description:
- Create kernel threads & tasklets.
-
-Arguments:
- *net_dev Pointer to wireless net device interface
-
-Return Value:
- NDIS_STATUS_SUCCESS
- NDIS_STATUS_FAILURE
-
-Note:
-========================================================================
-*/
-int RtmpMgmtTaskInit(struct rt_rtmp_adapter *pAd)
-{
- struct rt_rtmp_os_task *pTask;
- int status;
-
- /*
- Creat TimerQ Thread, We need init timerQ related structure before create the timer thread.
- */
- RtmpTimerQInit(pAd);
-
- pTask = &pAd->timerTask;
- RtmpOSTaskInit(pTask, "RtmpTimerTask", pAd);
- status = RtmpOSTaskAttach(pTask, RtmpTimerQThread, pTask);
- if (status == NDIS_STATUS_FAILURE) {
- printk(KERN_WARNING "%s: unable to start RtmpTimerQThread\n",
- RTMP_OS_NETDEV_GET_DEVNAME(pAd->net_dev));
- return NDIS_STATUS_FAILURE;
- }
-
- /* Creat MLME Thread */
- pTask = &pAd->mlmeTask;
- RtmpOSTaskInit(pTask, "RtmpMlmeTask", pAd);
- status = RtmpOSTaskAttach(pTask, MlmeThread, pTask);
- if (status == NDIS_STATUS_FAILURE) {
- printk(KERN_WARNING "%s: unable to start MlmeThread\n",
- RTMP_OS_NETDEV_GET_DEVNAME(pAd->net_dev));
- return NDIS_STATUS_FAILURE;
- }
-
- /* Creat Command Thread */
- pTask = &pAd->cmdQTask;
- RtmpOSTaskInit(pTask, "RtmpCmdQTask", pAd);
- status = RtmpOSTaskAttach(pTask, RTUSBCmdThread, pTask);
- if (status == NDIS_STATUS_FAILURE) {
- printk(KERN_WARNING "%s: unable to start RTUSBCmdThread\n",
- RTMP_OS_NETDEV_GET_DEVNAME(pAd->net_dev));
- return NDIS_STATUS_FAILURE;
- }
-
- return NDIS_STATUS_SUCCESS;
-}
-
-/*
-========================================================================
-Routine Description:
- Close kernel threads.
-
-Arguments:
- *pAd the raxx interface data pointer
-
-Return Value:
- NONE
-
-Note:
-========================================================================
-*/
-void RtmpMgmtTaskExit(struct rt_rtmp_adapter *pAd)
-{
- int ret;
- struct rt_rtmp_os_task *pTask;
-
- /* Sleep 50 milliseconds so pending io might finish normally */
- RTMPusecDelay(50000);
-
- /* We want to wait until all pending receives and sends to the */
- /* device object. We cancel any */
- /* irps. Wait until sends and receives have stopped. */
- RTUSBCancelPendingIRPs(pAd);
-
- /* We need clear timerQ related structure before exits of the timer thread. */
- RtmpTimerQExit(pAd);
-
- /* Terminate Mlme Thread */
- pTask = &pAd->mlmeTask;
- ret = RtmpOSTaskKill(pTask);
- if (ret == NDIS_STATUS_FAILURE) {
- DBGPRINT(RT_DEBUG_ERROR, ("%s: kill task(%s) failed!\n",
- RTMP_OS_NETDEV_GET_DEVNAME(pAd->
- net_dev),
- pTask->taskName));
- }
-
- /* Terminate cmdQ thread */
- pTask = &pAd->cmdQTask;
-#ifdef KTHREAD_SUPPORT
- if (pTask->kthread_task)
-#else
- CHECK_PID_LEGALITY(pTask->taskPID)
-#endif
- {
- mb();
- NdisAcquireSpinLock(&pAd->CmdQLock);
- pAd->CmdQ.CmdQState = RTMP_TASK_STAT_STOPED;
- NdisReleaseSpinLock(&pAd->CmdQLock);
- mb();
- /*RTUSBCMDUp(pAd); */
- ret = RtmpOSTaskKill(pTask);
- if (ret == NDIS_STATUS_FAILURE) {
- DBGPRINT(RT_DEBUG_ERROR, ("%s: kill task(%s) failed!\n",
- RTMP_OS_NETDEV_GET_DEVNAME
- (pAd->net_dev),
- pTask->taskName));
- }
- pAd->CmdQ.CmdQState = RTMP_TASK_STAT_UNKNOWN;
- }
-
- /* Terminate timer thread */
- pTask = &pAd->timerTask;
- ret = RtmpOSTaskKill(pTask);
- if (ret == NDIS_STATUS_FAILURE) {
- DBGPRINT(RT_DEBUG_ERROR, ("%s: kill task(%s) failed!\n",
- RTMP_OS_NETDEV_GET_DEVNAME(pAd->
- net_dev),
- pTask->taskName));
- }
-
-}
-
-static void rtusb_dataout_complete(unsigned long data)
-{
- struct rt_rtmp_adapter *pAd;
- struct urb *pUrb;
- struct os_cookie *pObj;
- struct rt_ht_tx_context *pHTTXContext;
- u8 BulkOutPipeId;
- int Status;
- unsigned long IrqFlags;
-
- pUrb = (struct urb *)data;
- pHTTXContext = (struct rt_ht_tx_context *)pUrb->context;
- pAd = pHTTXContext->pAd;
- pObj = (struct os_cookie *)pAd->OS_Cookie;
- Status = pUrb->status;
-
- /* Store BulkOut PipeId */
- BulkOutPipeId = pHTTXContext->BulkOutPipeId;
- pAd->BulkOutDataOneSecCount++;
-
- /*DBGPRINT(RT_DEBUG_LOUD, ("Done-B(%d):I=0x%lx, CWPos=%ld, NBPos=%ld, ENBPos=%ld, bCopy=%d!\n", BulkOutPipeId, in_interrupt(), pHTTXContext->CurWritePosition, */
- /* pHTTXContext->NextBulkOutPosition, pHTTXContext->ENextBulkOutPosition, pHTTXContext->bCopySavePad)); */
-
- RTMP_IRQ_LOCK(&pAd->BulkOutLock[BulkOutPipeId], IrqFlags);
- pAd->BulkOutPending[BulkOutPipeId] = FALSE;
- pHTTXContext->IRPPending = FALSE;
- pAd->watchDogTxPendingCnt[BulkOutPipeId] = 0;
-
- if (Status == USB_ST_NOERROR) {
- pAd->BulkOutComplete++;
-
- RTMP_IRQ_UNLOCK(&pAd->BulkOutLock[BulkOutPipeId], IrqFlags);
-
- pAd->Counters8023.GoodTransmits++;
- /*RTMP_IRQ_LOCK(&pAd->TxContextQueueLock[BulkOutPipeId], IrqFlags); */
- FREE_HTTX_RING(pAd, BulkOutPipeId, pHTTXContext);
- /*RTMP_IRQ_UNLOCK(&pAd->TxContextQueueLock[BulkOutPipeId], IrqFlags); */
-
- } else { /* STATUS_OTHER */
- u8 *pBuf;
-
- pAd->BulkOutCompleteOther++;
-
- pBuf =
- &pHTTXContext->TransferBuffer->field.
- WirelessPacket[pHTTXContext->NextBulkOutPosition];
-
- if (!RTMP_TEST_FLAG(pAd, (fRTMP_ADAPTER_RESET_IN_PROGRESS |
- fRTMP_ADAPTER_HALT_IN_PROGRESS |
- fRTMP_ADAPTER_NIC_NOT_EXIST |
- fRTMP_ADAPTER_BULKOUT_RESET))) {
- RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_BULKOUT_RESET);
- pAd->bulkResetPipeid = BulkOutPipeId;
- pAd->bulkResetReq[BulkOutPipeId] = pAd->BulkOutReq;
- }
- RTMP_IRQ_UNLOCK(&pAd->BulkOutLock[BulkOutPipeId], IrqFlags);
-
- DBGPRINT_RAW(RT_DEBUG_ERROR,
- ("BulkOutDataPacket failed: ReasonCode=%d!\n",
- Status));
- DBGPRINT_RAW(RT_DEBUG_ERROR,
- ("\t>>BulkOut Req=0x%lx, Complete=0x%lx, Other=0x%lx\n",
- pAd->BulkOutReq, pAd->BulkOutComplete,
- pAd->BulkOutCompleteOther));
- DBGPRINT_RAW(RT_DEBUG_ERROR,
- ("\t>>BulkOut Header:%x %x %x %x %x %x %x %x\n",
- pBuf[0], pBuf[1], pBuf[2], pBuf[3], pBuf[4],
- pBuf[5], pBuf[6], pBuf[7]));
- /*DBGPRINT_RAW(RT_DEBUG_ERROR, (">>BulkOutCompleteCancel=0x%x, BulkOutCompleteOther=0x%x\n", pAd->BulkOutCompleteCancel, pAd->BulkOutCompleteOther)); */
-
- }
-
- /* */
- /* bInUse = TRUE, means some process are filling TX data, after that must turn on bWaitingBulkOut */
- /* bWaitingBulkOut = TRUE, means the TX data are waiting for bulk out. */
- /* */
- /*RTMP_IRQ_LOCK(&pAd->TxContextQueueLock[BulkOutPipeId], IrqFlags); */
- if ((pHTTXContext->ENextBulkOutPosition !=
- pHTTXContext->CurWritePosition)
- && (pHTTXContext->ENextBulkOutPosition !=
- (pHTTXContext->CurWritePosition + 8))
- && !RTUSB_TEST_BULK_FLAG(pAd,
- (fRTUSB_BULK_OUT_DATA_FRAG <<
- BulkOutPipeId))) {
- /* Indicate There is data available */
- RTUSB_SET_BULK_FLAG(pAd,
- (fRTUSB_BULK_OUT_DATA_NORMAL <<
- BulkOutPipeId));
- }
- /*RTMP_IRQ_UNLOCK(&pAd->TxContextQueueLock[BulkOutPipeId], IrqFlags); */
-
- /* Always call Bulk routine, even reset bulk. */
- /* The protection of rest bulk should be in BulkOut routine */
- RTUSBKickBulkOut(pAd);
-}
-
-static void rtusb_null_frame_done_tasklet(unsigned long data)
-{
- struct rt_rtmp_adapter *pAd;
- struct rt_tx_context *pNullContext;
- struct urb *pUrb;
- int Status;
- unsigned long irqFlag;
-
- pUrb = (struct urb *)data;
- pNullContext = (struct rt_tx_context *)pUrb->context;
- pAd = pNullContext->pAd;
- Status = pUrb->status;
-
- /* Reset Null frame context flags */
- RTMP_IRQ_LOCK(&pAd->BulkOutLock[0], irqFlag);
- pNullContext->IRPPending = FALSE;
- pNullContext->InUse = FALSE;
- pAd->BulkOutPending[0] = FALSE;
- pAd->watchDogTxPendingCnt[0] = 0;
-
- if (Status == USB_ST_NOERROR) {
- RTMP_IRQ_UNLOCK(&pAd->BulkOutLock[0], irqFlag);
-
- RTMPDeQueuePacket(pAd, FALSE, NUM_OF_TX_RING, MAX_TX_PROCESS);
- } else { /* STATUS_OTHER */
- if ((!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_RESET_IN_PROGRESS)) &&
- (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS)) &&
- (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST)) &&
- (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_BULKOUT_RESET))) {
- DBGPRINT_RAW(RT_DEBUG_ERROR,
- ("Bulk Out Null Frame Failed, ReasonCode=%d!\n",
- Status));
- RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_BULKOUT_RESET);
- pAd->bulkResetPipeid =
- (MGMTPIPEIDX | BULKOUT_MGMT_RESET_FLAG);
- RTMP_IRQ_UNLOCK(&pAd->BulkOutLock[0], irqFlag);
- RTUSBEnqueueInternalCmd(pAd, CMDTHREAD_RESET_BULK_OUT,
- NULL, 0);
- } else {
- RTMP_IRQ_UNLOCK(&pAd->BulkOutLock[0], irqFlag);
- }
- }
-
- /* Always call Bulk routine, even reset bulk. */
- /* The protection of rest bulk should be in BulkOut routine */
- RTUSBKickBulkOut(pAd);
-}
-
-static void rtusb_rts_frame_done_tasklet(unsigned long data)
-{
- struct rt_rtmp_adapter *pAd;
- struct rt_tx_context *pRTSContext;
- struct urb *pUrb;
- int Status;
- unsigned long irqFlag;
-
- pUrb = (struct urb *)data;
- pRTSContext = (struct rt_tx_context *)pUrb->context;
- pAd = pRTSContext->pAd;
- Status = pUrb->status;
-
- /* Reset RTS frame context flags */
- RTMP_IRQ_LOCK(&pAd->BulkOutLock[0], irqFlag);
- pRTSContext->IRPPending = FALSE;
- pRTSContext->InUse = FALSE;
-
- if (Status == USB_ST_NOERROR) {
- RTMP_IRQ_UNLOCK(&pAd->BulkOutLock[0], irqFlag);
- RTMPDeQueuePacket(pAd, FALSE, NUM_OF_TX_RING, MAX_TX_PROCESS);
- } else { /* STATUS_OTHER */
- if ((!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_RESET_IN_PROGRESS)) &&
- (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS)) &&
- (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST)) &&
- (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_BULKOUT_RESET))) {
- DBGPRINT_RAW(RT_DEBUG_ERROR,
- ("Bulk Out RTS Frame Failed\n"));
- RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_BULKOUT_RESET);
- pAd->bulkResetPipeid =
- (MGMTPIPEIDX | BULKOUT_MGMT_RESET_FLAG);
- RTMP_IRQ_UNLOCK(&pAd->BulkOutLock[0], irqFlag);
- RTUSBEnqueueInternalCmd(pAd, CMDTHREAD_RESET_BULK_OUT,
- NULL, 0);
- } else {
- RTMP_IRQ_UNLOCK(&pAd->BulkOutLock[0], irqFlag);
- }
- }
-
- RTMP_SEM_LOCK(&pAd->BulkOutLock[pRTSContext->BulkOutPipeId]);
- pAd->BulkOutPending[pRTSContext->BulkOutPipeId] = FALSE;
- RTMP_SEM_UNLOCK(&pAd->BulkOutLock[pRTSContext->BulkOutPipeId]);
-
- /* Always call Bulk routine, even reset bulk. */
- /* The protection of rest bulk should be in BulkOut routine */
- RTUSBKickBulkOut(pAd);
-
-}
-
-static void rtusb_pspoll_frame_done_tasklet(unsigned long data)
-{
- struct rt_rtmp_adapter *pAd;
- struct rt_tx_context *pPsPollContext;
- struct urb *pUrb;
- int Status;
-
- pUrb = (struct urb *)data;
- pPsPollContext = (struct rt_tx_context *)pUrb->context;
- pAd = pPsPollContext->pAd;
- Status = pUrb->status;
-
- /* Reset PsPoll context flags */
- pPsPollContext->IRPPending = FALSE;
- pPsPollContext->InUse = FALSE;
- pAd->watchDogTxPendingCnt[0] = 0;
-
- if (Status == USB_ST_NOERROR) {
- RTMPDeQueuePacket(pAd, FALSE, NUM_OF_TX_RING, MAX_TX_PROCESS);
- } else { /* STATUS_OTHER */
- if ((!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_RESET_IN_PROGRESS)) &&
- (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS)) &&
- (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST)) &&
- (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_BULKOUT_RESET))) {
- DBGPRINT_RAW(RT_DEBUG_ERROR,
- ("Bulk Out PSPoll Failed\n"));
- RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_BULKOUT_RESET);
- pAd->bulkResetPipeid =
- (MGMTPIPEIDX | BULKOUT_MGMT_RESET_FLAG);
- RTUSBEnqueueInternalCmd(pAd, CMDTHREAD_RESET_BULK_OUT,
- NULL, 0);
- }
- }
-
- RTMP_SEM_LOCK(&pAd->BulkOutLock[0]);
- pAd->BulkOutPending[0] = FALSE;
- RTMP_SEM_UNLOCK(&pAd->BulkOutLock[0]);
-
- /* Always call Bulk routine, even reset bulk. */
- /* The protection of rest bulk should be in BulkOut routine */
- RTUSBKickBulkOut(pAd);
-
-}
-
-/*
-========================================================================
-Routine Description:
- Handle received packets.
-
-Arguments:
- data - URB information pointer
-
-Return Value:
- None
-
-Note:
-========================================================================
-*/
-static void rx_done_tasklet(unsigned long data)
-{
- struct urb *pUrb;
- struct rt_rx_context *pRxContext;
- struct rt_rtmp_adapter *pAd;
- int Status;
- unsigned int IrqFlags;
-
- pUrb = (struct urb *)data;
- pRxContext = (struct rt_rx_context *)pUrb->context;
- pAd = pRxContext->pAd;
- Status = pUrb->status;
-
- RTMP_IRQ_LOCK(&pAd->BulkInLock, IrqFlags);
- pRxContext->InUse = FALSE;
- pRxContext->IRPPending = FALSE;
- pRxContext->BulkInOffset += pUrb->actual_length;
- /*NdisInterlockedDecrement(&pAd->PendingRx); */
- pAd->PendingRx--;
-
- if (Status == USB_ST_NOERROR) {
- pAd->BulkInComplete++;
- pAd->NextRxBulkInPosition = 0;
- if (pRxContext->BulkInOffset) { /* As jan's comment, it may bulk-in success but size is zero. */
- pRxContext->Readable = TRUE;
- INC_RING_INDEX(pAd->NextRxBulkInIndex, RX_RING_SIZE);
- }
- RTMP_IRQ_UNLOCK(&pAd->BulkInLock, IrqFlags);
- } else { /* STATUS_OTHER */
- pAd->BulkInCompleteFail++;
- /* Still read this packet although it may comtain wrong bytes. */
- pRxContext->Readable = FALSE;
- RTMP_IRQ_UNLOCK(&pAd->BulkInLock, IrqFlags);
-
- /* Parsing all packets. because after reset, the index will reset to all zero. */
- if ((!RTMP_TEST_FLAG(pAd, (fRTMP_ADAPTER_RESET_IN_PROGRESS |
- fRTMP_ADAPTER_BULKIN_RESET |
- fRTMP_ADAPTER_HALT_IN_PROGRESS |
- fRTMP_ADAPTER_NIC_NOT_EXIST)))) {
-
- DBGPRINT_RAW(RT_DEBUG_ERROR,
- ("Bulk In Failed. Status=%d, BIIdx=0x%x, BIRIdx=0x%x, actual_length= 0x%x\n",
- Status, pAd->NextRxBulkInIndex,
- pAd->NextRxBulkInReadIndex,
- pRxContext->pUrb->actual_length));
-
- RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_BULKIN_RESET);
- RTUSBEnqueueInternalCmd(pAd, CMDTHREAD_RESET_BULK_IN,
- NULL, 0);
- }
- }
-
- ASSERT((pRxContext->InUse == pRxContext->IRPPending));
-
- RTUSBBulkReceive(pAd);
-
- return;
-
-}
-
-static void rtusb_mgmt_dma_done_tasklet(unsigned long data)
-{
- struct rt_rtmp_adapter *pAd;
- struct rt_tx_context *pMLMEContext;
- int index;
- void *pPacket;
- struct urb *pUrb;
- int Status;
- unsigned long IrqFlags;
-
- pUrb = (struct urb *)data;
- pMLMEContext = (struct rt_tx_context *)pUrb->context;
- pAd = pMLMEContext->pAd;
- Status = pUrb->status;
- index = pMLMEContext->SelfIdx;
-
- ASSERT((pAd->MgmtRing.TxDmaIdx == index));
-
- RTMP_IRQ_LOCK(&pAd->BulkOutLock[MGMTPIPEIDX], IrqFlags);
-
- if (Status != USB_ST_NOERROR) {
- /*Bulk-Out fail status handle */
- if ((!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_RESET_IN_PROGRESS)) &&
- (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS)) &&
- (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST)) &&
- (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_BULKOUT_RESET))) {
- DBGPRINT_RAW(RT_DEBUG_ERROR,
- ("Bulk Out MLME Failed, Status=%d!\n",
- Status));
- /* TODO: How to handle about the MLMEBulkOut failed issue. Need to resend the mgmt pkt? */
- RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_BULKOUT_RESET);
- pAd->bulkResetPipeid =
- (MGMTPIPEIDX | BULKOUT_MGMT_RESET_FLAG);
- }
- }
-
- pAd->BulkOutPending[MGMTPIPEIDX] = FALSE;
- RTMP_IRQ_UNLOCK(&pAd->BulkOutLock[MGMTPIPEIDX], IrqFlags);
-
- RTMP_IRQ_LOCK(&pAd->MLMEBulkOutLock, IrqFlags);
- /* Reset MLME context flags */
- pMLMEContext->IRPPending = FALSE;
- pMLMEContext->InUse = FALSE;
- pMLMEContext->bWaitingBulkOut = FALSE;
- pMLMEContext->BulkOutSize = 0;
-
- pPacket = pAd->MgmtRing.Cell[index].pNdisPacket;
- pAd->MgmtRing.Cell[index].pNdisPacket = NULL;
-
- /* Increase MgmtRing Index */
- INC_RING_INDEX(pAd->MgmtRing.TxDmaIdx, MGMT_RING_SIZE);
- pAd->MgmtRing.TxSwFreeIdx++;
- RTMP_IRQ_UNLOCK(&pAd->MLMEBulkOutLock, IrqFlags);
-
- /* No-matter success or fail, we free the mgmt packet. */
- if (pPacket)
- RTMPFreeNdisPacket(pAd, pPacket);
-
- if ((RTMP_TEST_FLAG(pAd, (fRTMP_ADAPTER_RESET_IN_PROGRESS |
- fRTMP_ADAPTER_HALT_IN_PROGRESS |
- fRTMP_ADAPTER_NIC_NOT_EXIST)))) {
- /* do nothing and return directly. */
- } else {
- if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_BULKOUT_RESET) && ((pAd->bulkResetPipeid & BULKOUT_MGMT_RESET_FLAG) == BULKOUT_MGMT_RESET_FLAG)) { /* For Mgmt Bulk-Out failed, ignore it now. */
- RTUSBEnqueueInternalCmd(pAd, CMDTHREAD_RESET_BULK_OUT,
- NULL, 0);
- } else {
-
- /* Always call Bulk routine, even reset bulk. */
- /* The protection of rest bulk should be in BulkOut routine */
- if (pAd->MgmtRing.TxSwFreeIdx <
- MGMT_RING_SIZE
- /* pMLMEContext->bWaitingBulkOut == TRUE */) {
- RTUSB_SET_BULK_FLAG(pAd, fRTUSB_BULK_OUT_MLME);
- }
- RTUSBKickBulkOut(pAd);
- }
- }
-
-}
-
-static void rtusb_ac3_dma_done_tasklet(unsigned long data)
-{
- struct rt_rtmp_adapter *pAd;
- struct rt_ht_tx_context *pHTTXContext;
- u8 BulkOutPipeId = 3;
- struct urb *pUrb;
-
- pUrb = (struct urb *)data;
- pHTTXContext = (struct rt_ht_tx_context *)pUrb->context;
- pAd = pHTTXContext->pAd;
-
- rtusb_dataout_complete((unsigned long)pUrb);
-
- if ((RTMP_TEST_FLAG(pAd, (fRTMP_ADAPTER_RESET_IN_PROGRESS |
- fRTMP_ADAPTER_HALT_IN_PROGRESS |
- fRTMP_ADAPTER_NIC_NOT_EXIST)))) {
- /* do nothing and return directly. */
- } else {
- if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_BULKOUT_RESET)) {
- RTUSBEnqueueInternalCmd(pAd, CMDTHREAD_RESET_BULK_OUT,
- NULL, 0);
- } else {
- pHTTXContext = &pAd->TxContext[BulkOutPipeId];
- if ((pAd->TxSwQueue[BulkOutPipeId].Number > 0) &&
- /*((pHTTXContext->CurWritePosition > (pHTTXContext->NextBulkOutPosition + 0x6000)) || (pHTTXContext->NextBulkOutPosition > pHTTXContext->CurWritePosition + 0x6000)) && */
- (pAd->DeQueueRunning[BulkOutPipeId] == FALSE) &&
- (pHTTXContext->bCurWriting == FALSE)) {
- RTMPDeQueuePacket(pAd, FALSE, BulkOutPipeId,
- MAX_TX_PROCESS);
- }
-
- RTUSB_SET_BULK_FLAG(pAd,
- fRTUSB_BULK_OUT_DATA_NORMAL << 3);
- RTUSBKickBulkOut(pAd);
- }
- }
-
- return;
-}
-
-static void rtusb_ac2_dma_done_tasklet(unsigned long data)
-{
- struct rt_rtmp_adapter *pAd;
- struct rt_ht_tx_context *pHTTXContext;
- u8 BulkOutPipeId = 2;
- struct urb *pUrb;
-
- pUrb = (struct urb *)data;
- pHTTXContext = (struct rt_ht_tx_context *)pUrb->context;
- pAd = pHTTXContext->pAd;
-
- rtusb_dataout_complete((unsigned long)pUrb);
-
- if ((RTMP_TEST_FLAG(pAd, (fRTMP_ADAPTER_RESET_IN_PROGRESS |
- fRTMP_ADAPTER_HALT_IN_PROGRESS |
- fRTMP_ADAPTER_NIC_NOT_EXIST)))) {
- /* do nothing and return directly. */
- } else {
- if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_BULKOUT_RESET)) {
- RTUSBEnqueueInternalCmd(pAd, CMDTHREAD_RESET_BULK_OUT,
- NULL, 0);
- } else {
- pHTTXContext = &pAd->TxContext[BulkOutPipeId];
- if ((pAd->TxSwQueue[BulkOutPipeId].Number > 0) &&
- /*((pHTTXContext->CurWritePosition > (pHTTXContext->NextBulkOutPosition + 0x6000)) || (pHTTXContext->NextBulkOutPosition > pHTTXContext->CurWritePosition + 0x6000)) && */
- (pAd->DeQueueRunning[BulkOutPipeId] == FALSE) &&
- (pHTTXContext->bCurWriting == FALSE)) {
- RTMPDeQueuePacket(pAd, FALSE, BulkOutPipeId,
- MAX_TX_PROCESS);
- }
-
- RTUSB_SET_BULK_FLAG(pAd,
- fRTUSB_BULK_OUT_DATA_NORMAL << 2);
- RTUSBKickBulkOut(pAd);
- }
- }
-
- return;
-}
-
-static void rtusb_ac1_dma_done_tasklet(unsigned long data)
-{
- struct rt_rtmp_adapter *pAd;
- struct rt_ht_tx_context *pHTTXContext;
- u8 BulkOutPipeId = 1;
- struct urb *pUrb;
-
- pUrb = (struct urb *)data;
- pHTTXContext = (struct rt_ht_tx_context *)pUrb->context;
- pAd = pHTTXContext->pAd;
-
- rtusb_dataout_complete((unsigned long)pUrb);
-
- if ((RTMP_TEST_FLAG(pAd, (fRTMP_ADAPTER_RESET_IN_PROGRESS |
- fRTMP_ADAPTER_HALT_IN_PROGRESS |
- fRTMP_ADAPTER_NIC_NOT_EXIST)))) {
- /* do nothing and return directly. */
- } else {
- if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_BULKOUT_RESET)) {
- RTUSBEnqueueInternalCmd(pAd, CMDTHREAD_RESET_BULK_OUT,
- NULL, 0);
- } else {
- pHTTXContext = &pAd->TxContext[BulkOutPipeId];
- if ((pAd->TxSwQueue[BulkOutPipeId].Number > 0) &&
- /*((pHTTXContext->CurWritePosition > (pHTTXContext->NextBulkOutPosition + 0x6000)) || (pHTTXContext->NextBulkOutPosition > pHTTXContext->CurWritePosition + 0x6000)) && */
- (pAd->DeQueueRunning[BulkOutPipeId] == FALSE) &&
- (pHTTXContext->bCurWriting == FALSE)) {
- RTMPDeQueuePacket(pAd, FALSE, BulkOutPipeId,
- MAX_TX_PROCESS);
- }
-
- RTUSB_SET_BULK_FLAG(pAd,
- fRTUSB_BULK_OUT_DATA_NORMAL << 1);
- RTUSBKickBulkOut(pAd);
- }
- }
- return;
-
-}
-
-static void rtusb_ac0_dma_done_tasklet(unsigned long data)
-{
- struct rt_rtmp_adapter *pAd;
- struct rt_ht_tx_context *pHTTXContext;
- u8 BulkOutPipeId = 0;
- struct urb *pUrb;
-
- pUrb = (struct urb *)data;
- pHTTXContext = (struct rt_ht_tx_context *)pUrb->context;
- pAd = pHTTXContext->pAd;
-
- rtusb_dataout_complete((unsigned long)pUrb);
-
- if ((RTMP_TEST_FLAG(pAd, (fRTMP_ADAPTER_RESET_IN_PROGRESS |
- fRTMP_ADAPTER_HALT_IN_PROGRESS |
- fRTMP_ADAPTER_NIC_NOT_EXIST)))) {
- /* do nothing and return directly. */
- } else {
- if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_BULKOUT_RESET)) {
- RTUSBEnqueueInternalCmd(pAd, CMDTHREAD_RESET_BULK_OUT,
- NULL, 0);
- } else {
- pHTTXContext = &pAd->TxContext[BulkOutPipeId];
- if ((pAd->TxSwQueue[BulkOutPipeId].Number > 0) &&
- /* ((pHTTXContext->CurWritePosition > (pHTTXContext->NextBulkOutPosition + 0x6000)) || (pHTTXContext->NextBulkOutPosition > pHTTXContext->CurWritePosition + 0x6000)) && */
- (pAd->DeQueueRunning[BulkOutPipeId] == FALSE) &&
- (pHTTXContext->bCurWriting == FALSE)) {
- RTMPDeQueuePacket(pAd, FALSE, BulkOutPipeId,
- MAX_TX_PROCESS);
- }
-
- RTUSB_SET_BULK_FLAG(pAd, fRTUSB_BULK_OUT_DATA_NORMAL);
- RTUSBKickBulkOut(pAd);
- }
- }
-
- return;
-
-}
-
-int RtmpNetTaskInit(struct rt_rtmp_adapter *pAd)
-{
- struct os_cookie *pObj = (struct os_cookie *)pAd->OS_Cookie;
-
- /* Create receive tasklet */
- tasklet_init(&pObj->rx_done_task, rx_done_tasklet, (unsigned long)pAd);
- tasklet_init(&pObj->mgmt_dma_done_task, rtusb_mgmt_dma_done_tasklet,
- (unsigned long)pAd);
- tasklet_init(&pObj->ac0_dma_done_task, rtusb_ac0_dma_done_tasklet,
- (unsigned long)pAd);
- tasklet_init(&pObj->ac1_dma_done_task, rtusb_ac1_dma_done_tasklet,
- (unsigned long)pAd);
- tasklet_init(&pObj->ac2_dma_done_task, rtusb_ac2_dma_done_tasklet,
- (unsigned long)pAd);
- tasklet_init(&pObj->ac3_dma_done_task, rtusb_ac3_dma_done_tasklet,
- (unsigned long)pAd);
- tasklet_init(&pObj->tbtt_task, tbtt_tasklet, (unsigned long)pAd);
- tasklet_init(&pObj->null_frame_complete_task,
- rtusb_null_frame_done_tasklet, (unsigned long)pAd);
- tasklet_init(&pObj->rts_frame_complete_task,
- rtusb_rts_frame_done_tasklet, (unsigned long)pAd);
- tasklet_init(&pObj->pspoll_frame_complete_task,
- rtusb_pspoll_frame_done_tasklet, (unsigned long)pAd);
-
- return NDIS_STATUS_SUCCESS;
-}
-
-void RtmpNetTaskExit(struct rt_rtmp_adapter *pAd)
-{
- struct os_cookie *pObj;
-
- pObj = (struct os_cookie *)pAd->OS_Cookie;
-
- tasklet_kill(&pObj->rx_done_task);
- tasklet_kill(&pObj->mgmt_dma_done_task);
- tasklet_kill(&pObj->ac0_dma_done_task);
- tasklet_kill(&pObj->ac1_dma_done_task);
- tasklet_kill(&pObj->ac2_dma_done_task);
- tasklet_kill(&pObj->ac3_dma_done_task);
- tasklet_kill(&pObj->tbtt_task);
- tasklet_kill(&pObj->null_frame_complete_task);
- tasklet_kill(&pObj->rts_frame_complete_task);
- tasklet_kill(&pObj->pspoll_frame_complete_task);
-}
diff --git a/drivers/staging/rt2860/rtmp.h b/drivers/staging/rt2860/rtmp.h
deleted file mode 100644
index 3c31340..0000000
--- a/drivers/staging/rt2860/rtmp.h
+++ /dev/null
@@ -1,4332 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- rtmp.h
-
- Abstract:
- Miniport generic portion header file
-
- Revision History:
- Who When What
- -------- ---------- ----------------------------------------------
- Paul Lin 2002-08-01 created
- James Tan 2002-09-06 modified (Revise NTCRegTable)
- John Chang 2004-09-06 modified for RT2600
- Justin P. Mattock 11/07/2010 Fix some typos
-*/
-#ifndef __RTMP_H__
-#define __RTMP_H__
-
-#include "spectrum_def.h"
-#include "rtmp_dot11.h"
-#include "rtmp_chip.h"
-
-struct rt_rtmp_adapter;
-
-/*#define DBG 1 */
-
-/*#define DBG_DIAGNOSE 1 */
-
-/*+++Add by shiang for merge MiniportMMRequest() and MiniportDataMMRequest() into one function */
-#define MAX_DATAMM_RETRY 3
-#define MGMT_USE_QUEUE_FLAG 0x80
-/*---Add by shiang for merge MiniportMMRequest() and MiniportDataMMRequest() into one function */
-
-#define MAXSEQ (0xFFF)
-
-extern unsigned char SNAP_AIRONET[];
-extern unsigned char CISCO_OUI[];
-extern u8 BaSizeArray[4];
-
-extern u8 BROADCAST_ADDR[MAC_ADDR_LEN];
-extern u8 ZERO_MAC_ADDR[MAC_ADDR_LEN];
-extern unsigned long BIT32[32];
-extern u8 BIT8[8];
-extern char *CipherName[];
-extern char *MCSToMbps[];
-extern u8 RxwiMCSToOfdmRate[12];
-extern u8 SNAP_802_1H[6];
-extern u8 SNAP_BRIDGE_TUNNEL[6];
-extern u8 SNAP_AIRONET[8];
-extern u8 CKIP_LLC_SNAP[8];
-extern u8 EAPOL_LLC_SNAP[8];
-extern u8 EAPOL[2];
-extern u8 IPX[2];
-extern u8 APPLE_TALK[2];
-extern u8 RateIdToPlcpSignal[12]; /* see IEEE802.11a-1999 p.14 */
-extern u8 OfdmRateToRxwiMCS[];
-extern u8 OfdmSignalToRateId[16];
-extern u8 default_cwmin[4];
-extern u8 default_cwmax[4];
-extern u8 default_sta_aifsn[4];
-extern u8 MapUserPriorityToAccessCategory[8];
-
-extern u16 RateUpPER[];
-extern u16 RateDownPER[];
-extern u8 Phy11BNextRateDownward[];
-extern u8 Phy11BNextRateUpward[];
-extern u8 Phy11BGNextRateDownward[];
-extern u8 Phy11BGNextRateUpward[];
-extern u8 Phy11ANextRateDownward[];
-extern u8 Phy11ANextRateUpward[];
-extern char RssiSafeLevelForTxRate[];
-extern u8 RateIdToMbps[];
-extern u16 RateIdTo500Kbps[];
-
-extern u8 CipherSuiteWpaNoneTkip[];
-extern u8 CipherSuiteWpaNoneTkipLen;
-
-extern u8 CipherSuiteWpaNoneAes[];
-extern u8 CipherSuiteWpaNoneAesLen;
-
-extern u8 SsidIe;
-extern u8 SupRateIe;
-extern u8 ExtRateIe;
-
-extern u8 HtCapIe;
-extern u8 AddHtInfoIe;
-extern u8 NewExtChanIe;
-
-extern u8 ErpIe;
-extern u8 DsIe;
-extern u8 TimIe;
-extern u8 WpaIe;
-extern u8 Wpa2Ie;
-extern u8 IbssIe;
-extern u8 Ccx2Ie;
-extern u8 WapiIe;
-
-extern u8 WPA_OUI[];
-extern u8 RSN_OUI[];
-extern u8 WAPI_OUI[];
-extern u8 WME_INFO_ELEM[];
-extern u8 WME_PARM_ELEM[];
-extern u8 Ccx2QosInfo[];
-extern u8 Ccx2IeInfo[];
-extern u8 RALINK_OUI[];
-extern u8 PowerConstraintIE[];
-
-extern u8 RateSwitchTable[];
-extern u8 RateSwitchTable11B[];
-extern u8 RateSwitchTable11G[];
-extern u8 RateSwitchTable11BG[];
-
-extern u8 RateSwitchTable11BGN1S[];
-extern u8 RateSwitchTable11BGN2S[];
-extern u8 RateSwitchTable11BGN2SForABand[];
-extern u8 RateSwitchTable11N1S[];
-extern u8 RateSwitchTable11N2S[];
-extern u8 RateSwitchTable11N2SForABand[];
-
-extern u8 PRE_N_HT_OUI[];
-
-struct rt_rssi_sample {
- char LastRssi0; /* last received RSSI */
- char LastRssi1; /* last received RSSI */
- char LastRssi2; /* last received RSSI */
- char AvgRssi0;
- char AvgRssi1;
- char AvgRssi2;
- short AvgRssi0X8;
- short AvgRssi1X8;
- short AvgRssi2X8;
-};
-
-/* */
-/* Queue structure and macros */
-/* */
-struct rt_queue_entry;
-
-struct rt_queue_entry {
- struct rt_queue_entry *Next;
-};
-
-/* Queue structure */
-struct rt_queue_header {
- struct rt_queue_entry *Head;
- struct rt_queue_entry *Tail;
- unsigned long Number;
-};
-
-#define InitializeQueueHeader(QueueHeader) \
-{ \
- (QueueHeader)->Head = (QueueHeader)->Tail = NULL; \
- (QueueHeader)->Number = 0; \
-}
-
-#define RemoveHeadQueue(QueueHeader) \
-(QueueHeader)->Head; \
-{ \
- struct rt_queue_entry *pNext; \
- if ((QueueHeader)->Head != NULL) { \
- pNext = (QueueHeader)->Head->Next; \
- (QueueHeader)->Head->Next = NULL; \
- (QueueHeader)->Head = pNext; \
- if (pNext == NULL) \
- (QueueHeader)->Tail = NULL; \
- (QueueHeader)->Number--; \
- } \
-}
-
-#define InsertHeadQueue(QueueHeader, QueueEntry) \
-{ \
- ((struct rt_queue_entry *)QueueEntry)->Next = (QueueHeader)->Head; \
- (QueueHeader)->Head = (struct rt_queue_entry *)(QueueEntry); \
- if ((QueueHeader)->Tail == NULL) \
- (QueueHeader)->Tail = (struct rt_queue_entry *)(QueueEntry); \
- (QueueHeader)->Number++; \
-}
-
-#define InsertTailQueue(QueueHeader, QueueEntry) \
-{ \
- ((struct rt_queue_entry *)QueueEntry)->Next = NULL; \
- if ((QueueHeader)->Tail) \
- (QueueHeader)->Tail->Next = (struct rt_queue_entry *)(QueueEntry); \
- else \
- (QueueHeader)->Head = (struct rt_queue_entry *)(QueueEntry); \
- (QueueHeader)->Tail = (struct rt_queue_entry *)(QueueEntry); \
- (QueueHeader)->Number++; \
-}
-
-#define InsertTailQueueAc(pAd, pEntry, QueueHeader, QueueEntry) \
-{ \
- ((struct rt_queue_entry *)QueueEntry)->Next = NULL; \
- if ((QueueHeader)->Tail) \
- (QueueHeader)->Tail->Next = (struct rt_queue_entry *)(QueueEntry); \
- else \
- (QueueHeader)->Head = (struct rt_queue_entry *)(QueueEntry); \
- (QueueHeader)->Tail = (struct rt_queue_entry *)(QueueEntry); \
- (QueueHeader)->Number++; \
-}
-
-/* */
-/* Macros for flag and ref count operations */
-/* */
-#define RTMP_SET_FLAG(_M, _F) ((_M)->Flags |= (_F))
-#define RTMP_CLEAR_FLAG(_M, _F) ((_M)->Flags &= ~(_F))
-#define RTMP_CLEAR_FLAGS(_M) ((_M)->Flags = 0)
-#define RTMP_TEST_FLAG(_M, _F) (((_M)->Flags & (_F)) != 0)
-#define RTMP_TEST_FLAGS(_M, _F) (((_M)->Flags & (_F)) == (_F))
-/* Macro for power save flag. */
-#define RTMP_SET_PSFLAG(_M, _F) ((_M)->PSFlags |= (_F))
-#define RTMP_CLEAR_PSFLAG(_M, _F) ((_M)->PSFlags &= ~(_F))
-#define RTMP_CLEAR_PSFLAGS(_M) ((_M)->PSFlags = 0)
-#define RTMP_TEST_PSFLAG(_M, _F) (((_M)->PSFlags & (_F)) != 0)
-#define RTMP_TEST_PSFLAGS(_M, _F) (((_M)->PSFlags & (_F)) == (_F))
-
-#define OPSTATUS_SET_FLAG(_pAd, _F) ((_pAd)->CommonCfg.OpStatusFlags |= (_F))
-#define OPSTATUS_CLEAR_FLAG(_pAd, _F) ((_pAd)->CommonCfg.OpStatusFlags &= ~(_F))
-#define OPSTATUS_TEST_FLAG(_pAd, _F) (((_pAd)->CommonCfg.OpStatusFlags & (_F)) != 0)
-
-#define CLIENT_STATUS_SET_FLAG(_pEntry, _F) ((_pEntry)->ClientStatusFlags |= (_F))
-#define CLIENT_STATUS_CLEAR_FLAG(_pEntry, _F) ((_pEntry)->ClientStatusFlags &= ~(_F))
-#define CLIENT_STATUS_TEST_FLAG(_pEntry, _F) (((_pEntry)->ClientStatusFlags & (_F)) != 0)
-
-#define RX_FILTER_SET_FLAG(_pAd, _F) ((_pAd)->CommonCfg.PacketFilter |= (_F))
-#define RX_FILTER_CLEAR_FLAG(_pAd, _F) ((_pAd)->CommonCfg.PacketFilter &= ~(_F))
-#define RX_FILTER_TEST_FLAG(_pAd, _F) (((_pAd)->CommonCfg.PacketFilter & (_F)) != 0)
-
-#define STA_NO_SECURITY_ON(_p) (_p->StaCfg.WepStatus == Ndis802_11EncryptionDisabled)
-#define STA_WEP_ON(_p) (_p->StaCfg.WepStatus == Ndis802_11Encryption1Enabled)
-#define STA_TKIP_ON(_p) (_p->StaCfg.WepStatus == Ndis802_11Encryption2Enabled)
-#define STA_AES_ON(_p) (_p->StaCfg.WepStatus == Ndis802_11Encryption3Enabled)
-
-#define STA_TGN_WIFI_ON(_p) (_p->StaCfg.bTGnWifiTest == TRUE)
-
-#define CKIP_KP_ON(_p) ((((_p)->StaCfg.CkipFlag) & 0x10) && ((_p)->StaCfg.bCkipCmicOn == TRUE))
-#define CKIP_CMIC_ON(_p) ((((_p)->StaCfg.CkipFlag) & 0x08) && ((_p)->StaCfg.bCkipCmicOn == TRUE))
-
-#define INC_RING_INDEX(_idx, _RingSize) \
-{ \
- (_idx) = (_idx+1) % (_RingSize); \
-}
-
-/* StaActive.SupportedHtPhy.MCSSet is copied from AP beacon. Don't need to update here. */
-#define COPY_HTSETTINGS_FROM_MLME_AUX_TO_ACTIVE_CFG(_pAd) \
-{ \
- _pAd->StaActive.SupportedHtPhy.ChannelWidth = _pAd->MlmeAux.HtCapability.HtCapInfo.ChannelWidth; \
- _pAd->StaActive.SupportedHtPhy.MimoPs = _pAd->MlmeAux.HtCapability.HtCapInfo.MimoPs; \
- _pAd->StaActive.SupportedHtPhy.GF = _pAd->MlmeAux.HtCapability.HtCapInfo.GF; \
- _pAd->StaActive.SupportedHtPhy.ShortGIfor20 = _pAd->MlmeAux.HtCapability.HtCapInfo.ShortGIfor20; \
- _pAd->StaActive.SupportedHtPhy.ShortGIfor40 = _pAd->MlmeAux.HtCapability.HtCapInfo.ShortGIfor40; \
- _pAd->StaActive.SupportedHtPhy.TxSTBC = _pAd->MlmeAux.HtCapability.HtCapInfo.TxSTBC; \
- _pAd->StaActive.SupportedHtPhy.RxSTBC = _pAd->MlmeAux.HtCapability.HtCapInfo.RxSTBC; \
- _pAd->StaActive.SupportedHtPhy.ExtChanOffset = _pAd->MlmeAux.AddHtInfo.AddHtInfo.ExtChanOffset; \
- _pAd->StaActive.SupportedHtPhy.RecomWidth = _pAd->MlmeAux.AddHtInfo.AddHtInfo.RecomWidth; \
- _pAd->StaActive.SupportedHtPhy.OperaionMode = _pAd->MlmeAux.AddHtInfo.AddHtInfo2.OperaionMode; \
- _pAd->StaActive.SupportedHtPhy.NonGfPresent = _pAd->MlmeAux.AddHtInfo.AddHtInfo2.NonGfPresent; \
- NdisMoveMemory((_pAd)->MacTab.Content[BSSID_WCID].HTCapability.MCSSet, (_pAd)->StaActive.SupportedPhyInfo.MCSSet, sizeof(u8) * 16);\
-}
-
-#define COPY_AP_HTSETTINGS_FROM_BEACON(_pAd, _pHtCapability) \
-{ \
- _pAd->MacTab.Content[BSSID_WCID].AMsduSize = (u8)(_pHtCapability->HtCapInfo.AMsduSize); \
- _pAd->MacTab.Content[BSSID_WCID].MmpsMode = (u8)(_pHtCapability->HtCapInfo.MimoPs); \
- _pAd->MacTab.Content[BSSID_WCID].MaxRAmpduFactor = (u8)(_pHtCapability->HtCapParm.MaxRAmpduFactor); \
-}
-
-/* */
-/* MACRO for 32-bit PCI register read / write */
-/* */
-/* Usage : RTMP_IO_READ32( */
-/* struct rt_rtmp_adapter *pAd, */
-/* unsigned long Register_Offset, */
-/* unsigned long * pValue) */
-/* */
-/* RTMP_IO_WRITE32( */
-/* struct rt_rtmp_adapter *pAd, */
-/* unsigned long Register_Offset, */
-/* unsigned long Value) */
-/* */
-
-/* */
-/* Common fragment list structure - Identical to the scatter gather frag list structure */
-/* */
-/*#define struct rt_rtmp_sg_element SCATTER_GATHER_ELEMENT */
-/*#define struct rt_rtmp_sg_element *PSCATTER_GATHER_ELEMENT */
-#define NIC_MAX_PHYS_BUF_COUNT 8
-
-struct rt_rtmp_sg_element {
- void *Address;
- unsigned long Length;
- unsigned long *Reserved;
-};
-
-struct rt_rtmp_sg_list {
- unsigned long NumberOfElements;
- unsigned long *Reserved;
- struct rt_rtmp_sg_element Elements[NIC_MAX_PHYS_BUF_COUNT];
-};
-
-/* */
-/* Some utility macros */
-/* */
-#define GET_LNA_GAIN(_pAd) ((_pAd->LatchRfRegs.Channel <= 14) ? (_pAd->BLNAGain) : ((_pAd->LatchRfRegs.Channel <= 64) ? (_pAd->ALNAGain0) : ((_pAd->LatchRfRegs.Channel <= 128) ? (_pAd->ALNAGain1) : (_pAd->ALNAGain2))))
-
-#define INC_COUNTER64(Val) (Val.QuadPart++)
-
-#define INFRA_ON(_p) (OPSTATUS_TEST_FLAG(_p, fOP_STATUS_INFRA_ON))
-#define ADHOC_ON(_p) (OPSTATUS_TEST_FLAG(_p, fOP_STATUS_ADHOC_ON))
-#define MONITOR_ON(_p) (((_p)->StaCfg.BssType) == BSS_MONITOR)
-#define IDLE_ON(_p) (!INFRA_ON(_p) && !ADHOC_ON(_p))
-
-/* Check LEAP & CCKM flags */
-#define LEAP_ON(_p) (((_p)->StaCfg.LeapAuthMode) == CISCO_AuthModeLEAP)
-#define LEAP_CCKM_ON(_p) ((((_p)->StaCfg.LeapAuthMode) == CISCO_AuthModeLEAP) && ((_p)->StaCfg.LeapAuthInfo.CCKM == TRUE))
-
-/* if original Ethernet frame contains no LLC/SNAP, then an extra LLC/SNAP encap is required */
-#define EXTRA_LLCSNAP_ENCAP_FROM_PKT_START(_pBufVA, _pExtraLlcSnapEncap) \
-{ \
- if (((*(_pBufVA + 12) << 8) + *(_pBufVA + 13)) > 1500) { \
- _pExtraLlcSnapEncap = SNAP_802_1H; \
- if (NdisEqualMemory(IPX, _pBufVA + 12, 2) || \
- NdisEqualMemory(APPLE_TALK, _pBufVA + 12, 2)) { \
- _pExtraLlcSnapEncap = SNAP_BRIDGE_TUNNEL; \
- } \
- } \
- else { \
- _pExtraLlcSnapEncap = NULL; \
- } \
-}
-
-/* New Define for new Tx Path. */
-#define EXTRA_LLCSNAP_ENCAP_FROM_PKT_OFFSET(_pBufVA, _pExtraLlcSnapEncap) \
-{ \
- if (((*(_pBufVA) << 8) + *(_pBufVA + 1)) > 1500) { \
- _pExtraLlcSnapEncap = SNAP_802_1H; \
- if (NdisEqualMemory(IPX, _pBufVA, 2) || \
- NdisEqualMemory(APPLE_TALK, _pBufVA, 2)) { \
- _pExtraLlcSnapEncap = SNAP_BRIDGE_TUNNEL; \
- } \
- } \
- else { \
- _pExtraLlcSnapEncap = NULL; \
- } \
-}
-
-#define MAKE_802_3_HEADER(_p, _pMac1, _pMac2, _pType) \
-{ \
- NdisMoveMemory(_p, _pMac1, MAC_ADDR_LEN); \
- NdisMoveMemory((_p + MAC_ADDR_LEN), _pMac2, MAC_ADDR_LEN); \
- NdisMoveMemory((_p + MAC_ADDR_LEN * 2), _pType, LENGTH_802_3_TYPE); \
-}
-
-/* if pData has no LLC/SNAP (neither RFC1042 nor Bridge tunnel), keep it that way. */
-/* else if the received frame is LLC/SNAP-encaped IPX or APPLETALK, preserve the LLC/SNAP field */
-/* else remove the LLC/SNAP field from the result Ethernet frame */
-/* Patch for WHQL only, which did not turn on Netbios but use IPX within its payload */
-/* Note: */
-/* _pData & _DataSize may be altered (remove 8-byte LLC/SNAP) by this MACRO */
-/* _pRemovedLLCSNAP: pointer to removed LLC/SNAP; NULL is not removed */
-#define CONVERT_TO_802_3(_p8023hdr, _pDA, _pSA, _pData, _DataSize, _pRemovedLLCSNAP) \
-{ \
- char LLC_Len[2]; \
- \
- _pRemovedLLCSNAP = NULL; \
- if (NdisEqualMemory(SNAP_802_1H, _pData, 6) || \
- NdisEqualMemory(SNAP_BRIDGE_TUNNEL, _pData, 6)) { \
- u8 *pProto = _pData + 6; \
- \
- if ((NdisEqualMemory(IPX, pProto, 2) || NdisEqualMemory(APPLE_TALK, pProto, 2)) && \
- NdisEqualMemory(SNAP_802_1H, _pData, 6)) { \
- LLC_Len[0] = (u8)(_DataSize / 256); \
- LLC_Len[1] = (u8)(_DataSize % 256); \
- MAKE_802_3_HEADER(_p8023hdr, _pDA, _pSA, LLC_Len); \
- } \
- else { \
- MAKE_802_3_HEADER(_p8023hdr, _pDA, _pSA, pProto); \
- _pRemovedLLCSNAP = _pData; \
- _DataSize -= LENGTH_802_1_H; \
- _pData += LENGTH_802_1_H; \
- } \
- } \
- else { \
- LLC_Len[0] = (u8)(_DataSize / 256); \
- LLC_Len[1] = (u8)(_DataSize % 256); \
- MAKE_802_3_HEADER(_p8023hdr, _pDA, _pSA, LLC_Len); \
- } \
-}
-
-/* Enqueue this frame to MLME engine */
-/* We need to enqueue the whole frame because MLME need to pass data type */
-/* information from 802.11 header */
-#ifdef RTMP_MAC_PCI
-#define REPORT_MGMT_FRAME_TO_MLME(_pAd, Wcid, _pFrame, _FrameSize, _Rssi0, _Rssi1, _Rssi2, _PlcpSignal) \
-{ \
- u32 High32TSF, Low32TSF; \
- RTMP_IO_READ32(_pAd, TSF_TIMER_DW1, &High32TSF); \
- RTMP_IO_READ32(_pAd, TSF_TIMER_DW0, &Low32TSF); \
- MlmeEnqueueForRecv(_pAd, Wcid, High32TSF, Low32TSF, (u8)_Rssi0, (u8)_Rssi1, (u8)_Rssi2, _FrameSize, _pFrame, (u8)_PlcpSignal); \
-}
-#endif /* RTMP_MAC_PCI // */
-#ifdef RTMP_MAC_USB
-#define REPORT_MGMT_FRAME_TO_MLME(_pAd, Wcid, _pFrame, _FrameSize, _Rssi0, _Rssi1, _Rssi2, _PlcpSignal) \
-{ \
- u32 High32TSF = 0, Low32TSF = 0; \
- MlmeEnqueueForRecv(_pAd, Wcid, High32TSF, Low32TSF, (u8)_Rssi0, (u8)_Rssi1, (u8)_Rssi2, _FrameSize, _pFrame, (u8)_PlcpSignal); \
-}
-#endif /* RTMP_MAC_USB // */
-
-#define MAC_ADDR_EQUAL(pAddr1, pAddr2) RTMPEqualMemory((void *)(pAddr1), (void *)(pAddr2), MAC_ADDR_LEN)
-#define SSID_EQUAL(ssid1, len1, ssid2, len2) ((len1 == len2) && (RTMPEqualMemory(ssid1, ssid2, len1)))
-
-/* */
-/* Check if it is Japan W53(ch52,56,60,64) channel. */
-/* */
-#define JapanChannelCheck(channel) ((channel == 52) || (channel == 56) || (channel == 60) || (channel == 64))
-
-#define STA_EXTRA_SETTING(_pAd)
-
-#define STA_PORT_SECURED(_pAd) \
-{ \
- BOOLEAN Cancelled; \
- (_pAd)->StaCfg.PortSecured = WPA_802_1X_PORT_SECURED; \
- NdisAcquireSpinLock(&((_pAd)->MacTabLock)); \
- (_pAd)->MacTab.Content[BSSID_WCID].PortSecured = (_pAd)->StaCfg.PortSecured; \
- (_pAd)->MacTab.Content[BSSID_WCID].PrivacyFilter = Ndis802_11PrivFilterAcceptAll;\
- NdisReleaseSpinLock(&(_pAd)->MacTabLock); \
- RTMPCancelTimer(&((_pAd)->Mlme.LinkDownTimer), &Cancelled);\
- STA_EXTRA_SETTING(_pAd); \
-}
-
-/* */
-/* Data buffer for DMA operation, the buffer must be contiguous physical memory */
-/* Both DMA to / from CPU use the same structure. */
-/* */
-struct rt_rtmp_dmabuf {
- unsigned long AllocSize;
- void *AllocVa; /* TxBuf virtual address */
- dma_addr_t AllocPa; /* TxBuf physical address */
-};
-
-/* */
-/* Control block (Descriptor) for all ring descriptor DMA operation, buffer must be */
-/* contiguous physical memory. char stored the binding Rx packet descriptor */
-/* which won't be released, driver has to wait until upper layer return the packet */
-/* before giving up this rx ring descriptor to ASIC. NDIS_BUFFER is associated pair */
-/* to describe the packet buffer. For Tx, char stored the tx packet descriptor */
-/* which driver should ACK upper layer when the tx is physically done or failed. */
-/* */
-struct rt_rtmp_dmacb {
- unsigned long AllocSize; /* Control block size */
- void *AllocVa; /* Control block virtual address */
- dma_addr_t AllocPa; /* Control block physical address */
- void *pNdisPacket;
- void *pNextNdisPacket;
-
- struct rt_rtmp_dmabuf DmaBuf; /* Associated DMA buffer structure */
-};
-
-struct rt_rtmp_tx_ring {
- struct rt_rtmp_dmacb Cell[TX_RING_SIZE];
- u32 TxCpuIdx;
- u32 TxDmaIdx;
- u32 TxSwFreeIdx; /* software next free tx index */
-};
-
-struct rt_rtmp_rx_ring {
- struct rt_rtmp_dmacb Cell[RX_RING_SIZE];
- u32 RxCpuIdx;
- u32 RxDmaIdx;
- int RxSwReadIdx; /* software next read index */
-};
-
-struct rt_rtmp_mgmt_ring {
- struct rt_rtmp_dmacb Cell[MGMT_RING_SIZE];
- u32 TxCpuIdx;
- u32 TxDmaIdx;
- u32 TxSwFreeIdx; /* software next free tx index */
-};
-
-/* */
-/* Statistic counter structure */
-/* */
-struct rt_counter_802_3 {
- /* General Stats */
- unsigned long GoodTransmits;
- unsigned long GoodReceives;
- unsigned long TxErrors;
- unsigned long RxErrors;
- unsigned long RxNoBuffer;
-
- /* Ethernet Stats */
- unsigned long RcvAlignmentErrors;
- unsigned long OneCollision;
- unsigned long MoreCollisions;
-
-};
-
-struct rt_counter_802_11 {
- unsigned long Length;
- LARGE_INTEGER LastTransmittedFragmentCount;
- LARGE_INTEGER TransmittedFragmentCount;
- LARGE_INTEGER MulticastTransmittedFrameCount;
- LARGE_INTEGER FailedCount;
- LARGE_INTEGER RetryCount;
- LARGE_INTEGER MultipleRetryCount;
- LARGE_INTEGER RTSSuccessCount;
- LARGE_INTEGER RTSFailureCount;
- LARGE_INTEGER ACKFailureCount;
- LARGE_INTEGER FrameDuplicateCount;
- LARGE_INTEGER ReceivedFragmentCount;
- LARGE_INTEGER MulticastReceivedFrameCount;
- LARGE_INTEGER FCSErrorCount;
-};
-
-struct rt_counter_ralink {
- unsigned long TransmittedByteCount; /* both successful and failure, used to calculate TX throughput */
- unsigned long ReceivedByteCount; /* both CRC okay and CRC error, used to calculate RX throughput */
- unsigned long BeenDisassociatedCount;
- unsigned long BadCQIAutoRecoveryCount;
- unsigned long PoorCQIRoamingCount;
- unsigned long MgmtRingFullCount;
- unsigned long RxCountSinceLastNULL;
- unsigned long RxCount;
- unsigned long RxRingErrCount;
- unsigned long KickTxCount;
- unsigned long TxRingErrCount;
- LARGE_INTEGER RealFcsErrCount;
- unsigned long PendingNdisPacketCount;
-
- unsigned long OneSecOsTxCount[NUM_OF_TX_RING];
- unsigned long OneSecDmaDoneCount[NUM_OF_TX_RING];
- u32 OneSecTxDoneCount;
- unsigned long OneSecRxCount;
- u32 OneSecTxAggregationCount;
- u32 OneSecRxAggregationCount;
- u32 OneSecReceivedByteCount;
- u32 OneSecFrameDuplicateCount;
-
- u32 OneSecTransmittedByteCount; /* both successful and failure, used to calculate TX throughput */
- u32 OneSecTxNoRetryOkCount;
- u32 OneSecTxRetryOkCount;
- u32 OneSecTxFailCount;
- u32 OneSecFalseCCACnt; /* CCA error count, for debug purpose, might move to global counter */
- u32 OneSecRxOkCnt; /* RX without error */
- u32 OneSecRxOkDataCnt; /* unicast-to-me DATA frame count */
- u32 OneSecRxFcsErrCnt; /* CRC error */
- u32 OneSecBeaconSentCnt;
- u32 LastOneSecTotalTxCount; /* OneSecTxNoRetryOkCount + OneSecTxRetryOkCount + OneSecTxFailCount */
- u32 LastOneSecRxOkDataCnt; /* OneSecRxOkDataCnt */
- unsigned long DuplicateRcv;
- unsigned long TxAggCount;
- unsigned long TxNonAggCount;
- unsigned long TxAgg1MPDUCount;
- unsigned long TxAgg2MPDUCount;
- unsigned long TxAgg3MPDUCount;
- unsigned long TxAgg4MPDUCount;
- unsigned long TxAgg5MPDUCount;
- unsigned long TxAgg6MPDUCount;
- unsigned long TxAgg7MPDUCount;
- unsigned long TxAgg8MPDUCount;
- unsigned long TxAgg9MPDUCount;
- unsigned long TxAgg10MPDUCount;
- unsigned long TxAgg11MPDUCount;
- unsigned long TxAgg12MPDUCount;
- unsigned long TxAgg13MPDUCount;
- unsigned long TxAgg14MPDUCount;
- unsigned long TxAgg15MPDUCount;
- unsigned long TxAgg16MPDUCount;
-
- LARGE_INTEGER TransmittedOctetsInAMSDU;
- LARGE_INTEGER TransmittedAMSDUCount;
- LARGE_INTEGER ReceivedOctesInAMSDUCount;
- LARGE_INTEGER ReceivedAMSDUCount;
- LARGE_INTEGER TransmittedAMPDUCount;
- LARGE_INTEGER TransmittedMPDUsInAMPDUCount;
- LARGE_INTEGER TransmittedOctetsInAMPDUCount;
- LARGE_INTEGER MPDUInReceivedAMPDUCount;
-};
-
-struct rt_counter_drs {
- /* record each TX rate's quality. 0 is best, the bigger the worse. */
- u16 TxQuality[MAX_STEP_OF_TX_RATE_SWITCH];
- u8 PER[MAX_STEP_OF_TX_RATE_SWITCH];
- u8 TxRateUpPenalty; /* extra # of second penalty due to last unstable condition */
- unsigned long CurrTxRateStableTime; /* # of second in current TX rate */
- BOOLEAN fNoisyEnvironment;
- BOOLEAN fLastSecAccordingRSSI;
- u8 LastSecTxRateChangeAction; /* 0: no change, 1:rate UP, 2:rate down */
- u8 LastTimeTxRateChangeAction; /*Keep last time value of LastSecTxRateChangeAction */
- unsigned long LastTxOkCount;
-};
-
-/***************************************************************************
- * security key related data structure
- **************************************************************************/
-struct rt_cipher_key {
- u8 Key[16]; /* right now we implement 4 keys, 128 bits max */
- u8 RxMic[8]; /* make alignment */
- u8 TxMic[8];
- u8 TxTsc[6]; /* 48bit TSC value */
- u8 RxTsc[6]; /* 48bit TSC value */
- u8 CipherAlg; /* 0-none, 1:WEP64, 2:WEP128, 3:TKIP, 4:AES, 5:CKIP64, 6:CKIP128 */
- u8 KeyLen;
- u8 BssId[6];
- /* Key length for each key, 0: entry is invalid */
- u8 Type; /* Indicate Pairwise/Group when reporting MIC error */
-};
-
-/* structure to define WPA Group Key Rekey Interval */
-struct PACKED rt_802_11_wpa_rekey {
- unsigned long ReKeyMethod; /* mechanism for rekeying: 0:disable, 1: time-based, 2: packet-based */
- unsigned long ReKeyInterval; /* time-based: seconds, packet-based: kilo-packets */
-};
-
-#ifdef RTMP_MAC_USB
-/***************************************************************************
- * RTUSB I/O related data structure
- **************************************************************************/
-struct rt_set_asic_wcid {
- unsigned long WCID; /* mechanism for rekeying: 0:disable, 1: time-based, 2: packet-based */
- unsigned long SetTid; /* time-based: seconds, packet-based: kilo-packets */
- unsigned long DeleteTid; /* time-based: seconds, packet-based: kilo-packets */
- u8 Addr[MAC_ADDR_LEN]; /* avoid in interrupt when write key */
-};
-
-struct rt_set_asic_wcid_attri {
- unsigned long WCID; /* mechanism for rekeying: 0:disable, 1: time-based, 2: packet-based */
- unsigned long Cipher; /* ASIC Cipher definition */
- u8 Addr[ETH_LENGTH_OF_ADDRESS];
-};
-
-/* for USB interface, avoid in interrupt when write key */
-struct rt_add_pairwise_key_entry {
- u8 MacAddr[6];
- u16 MacTabMatchWCID; /* ASIC */
- struct rt_cipher_key CipherKey;
-};
-
-/* Cipher suite type for mixed mode group cipher, P802.11i-2004 */
-typedef enum _RT_802_11_CIPHER_SUITE_TYPE {
- Cipher_Type_NONE,
- Cipher_Type_WEP40,
- Cipher_Type_TKIP,
- Cipher_Type_RSVD,
- Cipher_Type_CCMP,
- Cipher_Type_WEP104
-} RT_802_11_CIPHER_SUITE_TYPE, *PRT_802_11_CIPHER_SUITE_TYPE;
-#endif /* RTMP_MAC_USB // */
-
-struct rt_rogueap_entry {
- u8 Addr[MAC_ADDR_LEN];
- u8 ErrorCode[2]; /*00 01-Invalid authentication type */
- /*00 02-Authentication timeout */
- /*00 03-Challenge from AP failed */
- /*00 04-Challenge to AP failed */
- BOOLEAN Reported;
-};
-
-struct rt_rogueap_table {
- u8 RogueApNr;
- struct rt_rogueap_entry RogueApEntry[MAX_LEN_OF_BSS_TABLE];
-};
-
-/* */
-/* Cisco IAPP format */
-/* */
-struct rt_cisco_iapp_content {
- u16 Length; /*IAPP Length */
- u8 MessageType; /*IAPP type */
- u8 FunctionCode; /*IAPP function type */
- u8 DestinaionMAC[MAC_ADDR_LEN];
- u8 SourceMAC[MAC_ADDR_LEN];
- u16 Tag; /*Tag(element IE) - Adjacent AP report */
- u16 TagLength; /*Length of element not including 4 byte header */
- u8 OUI[4]; /*0x00, 0x40, 0x96, 0x00 */
- u8 PreviousAP[MAC_ADDR_LEN]; /*MAC Address of access point */
- u16 Channel;
- u16 SsidLen;
- u8 Ssid[MAX_LEN_OF_SSID];
- u16 Seconds; /*Seconds that the client has been disassociated. */
-};
-
-/*
- * Fragment Frame structure
- */
-struct rt_fragment_frame {
- void *pFragPacket;
- unsigned long RxSize;
- u16 Sequence;
- u16 LastFrag;
- unsigned long Flags; /* Some extra frame information. bit 0: LLC presented */
-};
-
-/* */
-/* Packet information for NdisQueryPacket */
-/* */
-struct rt_packet_info {
- u32 PhysicalBufferCount; /* Physical breaks of buffer descriptor chained */
- u32 BufferCount; /* Number of Buffer descriptor chained */
- u32 TotalPacketLength; /* Self explained */
- char *pFirstBuffer; /* Pointer to first buffer descriptor */
-};
-
-/* */
-/* Arcfour Structure Added by PaulWu */
-/* */
-struct rt_arcfourcontext {
- u32 X;
- u32 Y;
- u8 STATE[256];
-};
-
-/* */
-/* Tkip Key structure which RC4 key & MIC calculation */
-/* */
-struct rt_tkip_key_info {
- u32 nBytesInM; /* # bytes in M for MICKEY */
- unsigned long IV16;
- unsigned long IV32;
- unsigned long K0; /* for MICKEY Low */
- unsigned long K1; /* for MICKEY Hig */
- unsigned long L; /* Current state for MICKEY */
- unsigned long R; /* Current state for MICKEY */
- unsigned long M; /* Message accumulator for MICKEY */
- u8 RC4KEY[16];
- u8 MIC[8];
-};
-
-/* */
-/* Private / Misc data, counters for driver internal use */
-/* */
-struct rt_private {
- u32 SystemResetCnt; /* System reset counter */
- u32 TxRingFullCnt; /* Tx ring full occurrence number */
- u32 PhyRxErrCnt; /* PHY Rx error count, for debug purpose, might move to global counter */
- /* Variables for WEP encryption / decryption in rtmp_wep.c */
- u32 FCSCRC32;
- struct rt_arcfourcontext WEPCONTEXT;
- /* Tkip stuff */
- struct rt_tkip_key_info Tx;
- struct rt_tkip_key_info Rx;
-};
-
-/***************************************************************************
- * Channel and BBP related data structures
- **************************************************************************/
-/* structure to tune BBP R66 (BBP TUNING) */
-struct rt_bbp_r66_tuning {
- BOOLEAN bEnable;
- u16 FalseCcaLowerThreshold; /* default 100 */
- u16 FalseCcaUpperThreshold; /* default 512 */
- u8 R66Delta;
- u8 R66CurrentValue;
- BOOLEAN R66LowerUpperSelect; /*Before LinkUp, Used LowerBound or UpperBound as R66 value. */
-};
-
-/* structure to store channel TX power */
-struct rt_channel_tx_power {
- u16 RemainingTimeForUse; /*unit: sec */
- u8 Channel;
- char Power;
- char Power2;
- u8 MaxTxPwr;
- u8 DfsReq;
-};
-
-/* structure to store 802.11j channel TX power */
-struct rt_channel_11j_tx_power {
- u8 Channel;
- u8 BW; /* BW_10 or BW_20 */
- char Power;
- char Power2;
- u16 RemainingTimeForUse; /*unit: sec */
-};
-
-struct rt_soft_rx_ant_diversity {
- u8 EvaluatePeriod; /* 0:not evalute status, 1: evaluate status, 2: switching status */
- u8 EvaluateStableCnt;
- u8 Pair1PrimaryRxAnt; /* 0:Ant-E1, 1:Ant-E2 */
- u8 Pair1SecondaryRxAnt; /* 0:Ant-E1, 1:Ant-E2 */
- u8 Pair2PrimaryRxAnt; /* 0:Ant-E3, 1:Ant-E4 */
- u8 Pair2SecondaryRxAnt; /* 0:Ant-E3, 1:Ant-E4 */
- short Pair1AvgRssi[2]; /* AvgRssi[0]:E1, AvgRssi[1]:E2 */
- short Pair2AvgRssi[2]; /* AvgRssi[0]:E3, AvgRssi[1]:E4 */
- short Pair1LastAvgRssi; /* */
- short Pair2LastAvgRssi; /* */
- unsigned long RcvPktNumWhenEvaluate;
- BOOLEAN FirstPktArrivedWhenEvaluate;
- struct rt_ralink_timer RxAntDiversityTimer;
-};
-
-/***************************************************************************
- * structure for radar detection and channel switch
- **************************************************************************/
-struct rt_radar_detect {
- /*BOOLEAN IEEE80211H; // 0: disable, 1: enable IEEE802.11h */
- u8 CSCount; /*Channel switch counter */
- u8 CSPeriod; /*Channel switch period (beacon count) */
- u8 RDCount; /*Radar detection counter */
- u8 RDMode; /*Radar Detection mode */
- u8 RDDurRegion; /*Radar detection duration region */
- u8 BBPR16;
- u8 BBPR17;
- u8 BBPR18;
- u8 BBPR21;
- u8 BBPR22;
- u8 BBPR64;
- unsigned long InServiceMonitorCount; /* unit: sec */
- u8 DfsSessionTime;
- BOOLEAN bFastDfs;
- u8 ChMovingTime;
- u8 LongPulseRadarTh;
-};
-
-typedef enum _ABGBAND_STATE_ {
- UNKNOWN_BAND,
- BG_BAND,
- A_BAND,
-} ABGBAND_STATE;
-
-#ifdef RTMP_MAC_PCI
-/* Power save method control */
-typedef union _PS_CONTROL {
- struct {
- unsigned long EnablePSinIdle:1; /* Enable radio off when not connected to AP. radio on only when sitesurvey, */
- unsigned long EnableNewPS:1; /* Enable new Chip power save function . New method can only be applied in chip version after 2872. and PCIe. */
- unsigned long rt30xxPowerMode:2; /* Power Level Mode for rt30xx chip */
- unsigned long rt30xxFollowHostASPM:1; /* Card Follows Host's setting for rt30xx chip. */
- unsigned long rt30xxForceASPMTest:1; /* Force enable L1 for rt30xx chip. This has higher priority than rt30xxFollowHostASPM Mode. */
- unsigned long rsv:26; /* Radio Measurement Enable */
- } field;
- unsigned long word;
-} PS_CONTROL, *PPS_CONTROL;
-#endif /* RTMP_MAC_PCI // */
-
-/***************************************************************************
- * structure for MLME state machine
- **************************************************************************/
-struct rt_mlme {
- /* STA state machines */
- struct rt_state_machine CntlMachine;
- struct rt_state_machine AssocMachine;
- struct rt_state_machine AuthMachine;
- struct rt_state_machine AuthRspMachine;
- struct rt_state_machine SyncMachine;
- struct rt_state_machine WpaPskMachine;
- struct rt_state_machine LeapMachine;
- STATE_MACHINE_FUNC AssocFunc[ASSOC_FUNC_SIZE];
- STATE_MACHINE_FUNC AuthFunc[AUTH_FUNC_SIZE];
- STATE_MACHINE_FUNC AuthRspFunc[AUTH_RSP_FUNC_SIZE];
- STATE_MACHINE_FUNC SyncFunc[SYNC_FUNC_SIZE];
- STATE_MACHINE_FUNC ActFunc[ACT_FUNC_SIZE];
- /* Action */
- struct rt_state_machine ActMachine;
-
- /* common WPA state machine */
- struct rt_state_machine WpaMachine;
- STATE_MACHINE_FUNC WpaFunc[WPA_FUNC_SIZE];
-
- unsigned long ChannelQuality; /* 0..100, Channel Quality Indication for Roaming */
- unsigned long Now32; /* latch the value of NdisGetSystemUpTime() */
- unsigned long LastSendNULLpsmTime;
-
- BOOLEAN bRunning;
- spinlock_t TaskLock;
- struct rt_mlme_queue Queue;
-
- u32 ShiftReg;
-
- struct rt_ralink_timer PeriodicTimer;
- struct rt_ralink_timer APSDPeriodicTimer;
- struct rt_ralink_timer LinkDownTimer;
- struct rt_ralink_timer LinkUpTimer;
-#ifdef RTMP_MAC_PCI
- u8 bPsPollTimerRunning;
- struct rt_ralink_timer PsPollTimer;
- struct rt_ralink_timer RadioOnOffTimer;
-#endif /* RTMP_MAC_PCI // */
- unsigned long PeriodicRound;
- unsigned long OneSecPeriodicRound;
-
- u8 RealRxPath;
- BOOLEAN bLowThroughput;
- BOOLEAN bEnableAutoAntennaCheck;
- struct rt_ralink_timer RxAntEvalTimer;
-
-#ifdef RT30xx
- u8 CaliBW40RfR24;
- u8 CaliBW20RfR24;
-#endif /* RT30xx // */
-
-#ifdef RTMP_MAC_USB
- struct rt_ralink_timer AutoWakeupTimer;
- BOOLEAN AutoWakeupTimerRunning;
-#endif /* RTMP_MAC_USB // */
-};
-
-/***************************************************************************
- * 802.11 N related data structures
- **************************************************************************/
-struct reordering_mpdu {
- struct reordering_mpdu *next;
- void *pPacket; /* converted to 802.3 frame */
- int Sequence; /* sequence number of MPDU */
- BOOLEAN bAMSDU;
-};
-
-struct reordering_list {
- struct reordering_mpdu *next;
- int qlen;
-};
-
-struct reordering_mpdu_pool {
- void *mem;
- spinlock_t lock;
- struct reordering_list freelist;
-};
-
-typedef enum _REC_BLOCKACK_STATUS {
- Recipient_NONE = 0,
- Recipient_USED,
- Recipient_HandleRes,
- Recipient_Accept
-} REC_BLOCKACK_STATUS, *PREC_BLOCKACK_STATUS;
-
-typedef enum _ORI_BLOCKACK_STATUS {
- Originator_NONE = 0,
- Originator_USED,
- Originator_WaitRes,
- Originator_Done
-} ORI_BLOCKACK_STATUS, *PORI_BLOCKACK_STATUS;
-
-struct rt_ba_ori_entry {
- u8 Wcid;
- u8 TID;
- u8 BAWinSize;
- u8 Token;
-/* Sequence is to fill every outgoing QoS DATA frame's sequence field in 802.11 header. */
- u16 Sequence;
- u16 TimeOutValue;
- ORI_BLOCKACK_STATUS ORI_BA_Status;
- struct rt_ralink_timer ORIBATimer;
- void *pAdapter;
-};
-
-struct rt_ba_rec_entry {
- u8 Wcid;
- u8 TID;
- u8 BAWinSize; /* 7.3.1.14. each buffer is capable of holding a max AMSDU or MSDU. */
- /*u8 NumOfRxPkt; */
- /*u8 Curindidx; // the head in the RX reordering buffer */
- u16 LastIndSeq;
-/* u16 LastIndSeqAtTimer; */
- u16 TimeOutValue;
- struct rt_ralink_timer RECBATimer;
- unsigned long LastIndSeqAtTimer;
- unsigned long nDropPacket;
- unsigned long rcvSeq;
- REC_BLOCKACK_STATUS REC_BA_Status;
-/* u8 RxBufIdxUsed; */
- /* corresponding virtual address for RX reordering packet storage. */
- /*RTMP_REORDERDMABUF MAP_RXBuf[MAX_RX_REORDERBUF]; */
- spinlock_t RxReRingLock; /* Rx Ring spinlock */
-/* struct _BA_REC_ENTRY *pNext; */
- void *pAdapter;
- struct reordering_list list;
-};
-
-struct rt_ba_table {
- unsigned long numAsRecipient; /* I am recipient of numAsRecipient clients. These client are in the BARecEntry[] */
- unsigned long numAsOriginator; /* I am originator of numAsOriginator clients. These clients are in the BAOriEntry[] */
- unsigned long numDoneOriginator; /* count Done Originator sessions */
- struct rt_ba_ori_entry BAOriEntry[MAX_LEN_OF_BA_ORI_TABLE];
- struct rt_ba_rec_entry BARecEntry[MAX_LEN_OF_BA_REC_TABLE];
-};
-
-/*For QureyBATableOID use; */
-struct PACKED rt_oid_ba_rec_entry {
- u8 MACAddr[MAC_ADDR_LEN];
- u8 BaBitmap; /* if (BaBitmap&(1<<TID)), this session with{MACAddr, TID}exists, so read BufSize[TID] for BufferSize */
- u8 rsv;
- u8 BufSize[8];
- REC_BLOCKACK_STATUS REC_BA_Status[8];
-};
-
-/*For QureyBATableOID use; */
-struct PACKED rt_oid_ba_ori_entry {
- u8 MACAddr[MAC_ADDR_LEN];
- u8 BaBitmap; /* if (BaBitmap&(1<<TID)), this session with{MACAddr, TID}exists, so read BufSize[TID] for BufferSize, read ORI_BA_Status[TID] for status */
- u8 rsv;
- u8 BufSize[8];
- ORI_BLOCKACK_STATUS ORI_BA_Status[8];
-};
-
-struct rt_queryba_table {
- struct rt_oid_ba_ori_entry BAOriEntry[32];
- struct rt_oid_ba_rec_entry BARecEntry[32];
- u8 OriNum; /* Number of below BAOriEntry */
- u8 RecNum; /* Number of below BARecEntry */
-};
-
-typedef union _BACAP_STRUC {
- struct {
- u32 RxBAWinLimit:8;
- u32 TxBAWinLimit:8;
- u32 AutoBA:1; /* automatically BA */
- u32 Policy:2; /* 0: DELAY_BA 1:IMMED_BA (//BA Policy subfiled value in ADDBA frame) 2:BA-not use */
- u32 MpduDensity:3;
- u32 AmsduEnable:1; /*Enable AMSDU transmisstion */
- u32 AmsduSize:1; /* 0:3839, 1:7935 bytes. u32 MSDUSizeToBytes[] = { 3839, 7935}; */
- u32 MMPSmode:2; /* MIMO power save more, 0:static, 1:dynamic, 2:rsv, 3:mimo enable */
- u32 bHtAdhoc:1; /* adhoc can use ht rate. */
- u32 b2040CoexistScanSup:1; /*As Sta, support do 2040 coexistence scan for AP. As Ap, support monitor trigger event to check if can use BW 40MHz. */
- u32: 4;
- } field;
- u32 word;
-} BACAP_STRUC, *PBACAP_STRUC;
-
-struct rt_oid_add_ba_entry {
- BOOLEAN IsRecipient;
- u8 MACAddr[MAC_ADDR_LEN];
- u8 TID;
- u8 nMSDU;
- u16 TimeOut;
- BOOLEAN bAllTid; /* If True, delete all TID for BA sessions with this MACaddr. */
-};
-
-#define IS_HT_STA(_pMacEntry) \
- (_pMacEntry->MaxHTPhyMode.field.MODE >= MODE_HTMIX)
-
-#define IS_HT_RATE(_pMacEntry) \
- (_pMacEntry->HTPhyMode.field.MODE >= MODE_HTMIX)
-
-#define PEER_IS_HT_RATE(_pMacEntry) \
- (_pMacEntry->HTPhyMode.field.MODE >= MODE_HTMIX)
-
-/*This structure is for all 802.11n card InterOptibilityTest action. Reset all Num every n second. (Details see MLMEPeriodic) */
-struct rt_iot {
- u8 Threshold[2];
- u8 ReorderTimeOutNum[MAX_LEN_OF_BA_REC_TABLE]; /* compare with threshold[0] */
- u8 RefreshNum[MAX_LEN_OF_BA_REC_TABLE]; /* compare with threshold[1] */
- unsigned long OneSecInWindowCount;
- unsigned long OneSecFrameDuplicateCount;
- unsigned long OneSecOutWindowCount;
- u8 DelOriAct;
- u8 DelRecAct;
- u8 RTSShortProt;
- u8 RTSLongProt;
- BOOLEAN bRTSLongProtOn;
- BOOLEAN bLastAtheros;
- BOOLEAN bCurrentAtheros;
- BOOLEAN bNowAtherosBurstOn;
- BOOLEAN bNextDisableRxBA;
- BOOLEAN bToggle;
-};
-
-/* This is the registry setting for 802.11n transmit setting. Used in advanced page. */
-typedef union _REG_TRANSMIT_SETTING {
- struct {
- /*u32 PhyMode:4; */
- /*u32 MCS:7; // MCS */
- u32 rsv0:10;
- u32 TxBF:1;
- u32 BW:1; /*channel bandwidth 20MHz or 40 MHz */
- u32 ShortGI:1;
- u32 STBC:1; /*SPACE */
- u32 TRANSNO:2;
- u32 HTMODE:1;
- u32 EXTCHA:2;
- u32 rsv:13;
- } field;
- u32 word;
-} REG_TRANSMIT_SETTING, *PREG_TRANSMIT_SETTING;
-
-typedef union _DESIRED_TRANSMIT_SETTING {
- struct {
- u16 MCS:7; /* MCS */
- u16 PhyMode:4;
- u16 FixedTxMode:2; /* If MCS isn't AUTO, fix rate in CCK, OFDM or HT mode. */
- u16 rsv:3;
- } field;
- u16 word;
-} DESIRED_TRANSMIT_SETTING, *PDESIRED_TRANSMIT_SETTING;
-
-#ifdef RTMP_MAC_USB
-/***************************************************************************
- * USB-based chip Beacon related data structures
- **************************************************************************/
-#define BEACON_BITMAP_MASK 0xff
-struct rt_beacon_sync {
- u8 BeaconBuf[HW_BEACON_MAX_COUNT][HW_BEACON_OFFSET];
- u8 BeaconTxWI[HW_BEACON_MAX_COUNT][TXWI_SIZE];
- unsigned long TimIELocationInBeacon[HW_BEACON_MAX_COUNT];
- unsigned long CapabilityInfoLocationInBeacon[HW_BEACON_MAX_COUNT];
- BOOLEAN EnableBeacon; /* trigger to enable beacon transmission. */
- u8 BeaconBitMap; /* NOTE: If the MAX_MBSSID_NUM is larger than 8, this parameter needs to change. */
- u8 DtimBitOn; /* NOTE: If the MAX_MBSSID_NUM is larger than 8, this parameter needs to change. */
-};
-#endif /* RTMP_MAC_USB // */
-
-/***************************************************************************
- * Multiple SSID related data structures
- **************************************************************************/
-#define WLAN_MAX_NUM_OF_TIM ((MAX_LEN_OF_MAC_TABLE >> 3) + 1) /* /8 + 1 */
-#define WLAN_CT_TIM_BCMC_OFFSET 0 /* unit: 32B */
-
-/* clear bcmc TIM bit */
-#define WLAN_MR_TIM_BCMC_CLEAR(apidx) \
- pAd->ApCfg.MBSSID[apidx].TimBitmaps[WLAN_CT_TIM_BCMC_OFFSET] &= ~BIT8[0];
-
-/* set bcmc TIM bit */
-#define WLAN_MR_TIM_BCMC_SET(apidx) \
- pAd->ApCfg.MBSSID[apidx].TimBitmaps[WLAN_CT_TIM_BCMC_OFFSET] |= BIT8[0];
-
-/* clear a station PS TIM bit */
-#define WLAN_MR_TIM_BIT_CLEAR(ad_p, apidx, wcid) \
- { u8 tim_offset = wcid >> 3; \
- u8 bit_offset = wcid & 0x7; \
- ad_p->ApCfg.MBSSID[apidx].TimBitmaps[tim_offset] &= (~BIT8[bit_offset]); }
-
-/* set a station PS TIM bit */
-#define WLAN_MR_TIM_BIT_SET(ad_p, apidx, wcid) \
- { u8 tim_offset = wcid >> 3; \
- u8 bit_offset = wcid & 0x7; \
- ad_p->ApCfg.MBSSID[apidx].TimBitmaps[tim_offset] |= BIT8[bit_offset]; }
-
-/* configuration common to OPMODE_AP as well as OPMODE_STA */
-struct rt_common_config {
-
- BOOLEAN bCountryFlag;
- u8 CountryCode[3];
- u8 Geography;
- u8 CountryRegion; /* Enum of country region, 0:FCC, 1:IC, 2:ETSI, 3:SPAIN, 4:France, 5:MKK, 6:MKK1, 7:Israel */
- u8 CountryRegionForABand; /* Enum of country region for A band */
- u8 PhyMode; /* PHY_11A, PHY_11B, PHY_11BG_MIXED, PHY_ABG_MIXED */
- u16 Dsifs; /* in units of usec */
- unsigned long PacketFilter; /* Packet filter for receiving */
- u8 RegulatoryClass;
-
- char Ssid[MAX_LEN_OF_SSID]; /* NOT NULL-terminated */
- u8 SsidLen; /* the actual ssid length in used */
- u8 LastSsidLen; /* the actual ssid length in used */
- char LastSsid[MAX_LEN_OF_SSID]; /* NOT NULL-terminated */
- u8 LastBssid[MAC_ADDR_LEN];
-
- u8 Bssid[MAC_ADDR_LEN];
- u16 BeaconPeriod;
- u8 Channel;
- u8 CentralChannel; /* Central Channel when using 40MHz is indicating. not real channel. */
-
- u8 SupRate[MAX_LEN_OF_SUPPORTED_RATES];
- u8 SupRateLen;
- u8 ExtRate[MAX_LEN_OF_SUPPORTED_RATES];
- u8 ExtRateLen;
- u8 DesireRate[MAX_LEN_OF_SUPPORTED_RATES]; /* OID_802_11_DESIRED_RATES */
- u8 MaxDesiredRate;
- u8 ExpectedACKRate[MAX_LEN_OF_SUPPORTED_RATES];
-
- unsigned long BasicRateBitmap; /* backup basic ratebitmap */
-
- BOOLEAN bAPSDCapable;
- BOOLEAN bInServicePeriod;
- BOOLEAN bAPSDAC_BE;
- BOOLEAN bAPSDAC_BK;
- BOOLEAN bAPSDAC_VI;
- BOOLEAN bAPSDAC_VO;
-
- /* because TSPEC can modify the APSD flag, we need to keep the APSD flag
- requested in association stage from the station;
- we need to recover the APSD flag after the TSPEC is deleted. */
- BOOLEAN bACMAPSDBackup[4]; /* for delivery-enabled & trigger-enabled both */
- BOOLEAN bACMAPSDTr[4]; /* no use */
-
- BOOLEAN bNeedSendTriggerFrame;
- BOOLEAN bAPSDForcePowerSave; /* Force power save mode, should only use in APSD-STAUT */
- unsigned long TriggerTimerCount;
- u8 MaxSPLength;
- u8 BBPCurrentBW; /* BW_10, BW_20, BW_40 */
- /* move to MULTISSID_STRUCT for MBSS */
- /*HTTRANSMIT_SETTING HTPhyMode, MaxHTPhyMode, MinHTPhyMode;// For transmit phy setting in TXWI. */
- REG_TRANSMIT_SETTING RegTransmitSetting; /*registry transmit setting. this is for reading registry setting only. not useful. */
- /*u8 FixedTxMode; // Fixed Tx Mode (CCK, OFDM), for HT fixed tx mode (GF, MIX) , refer to RegTransmitSetting.field.HTMode */
- u8 TxRate; /* Same value to fill in TXD. TxRate is 6-bit */
- u8 MaxTxRate; /* RATE_1, RATE_2, RATE_5_5, RATE_11 */
- u8 TxRateIndex; /* Tx rate index in RateSwitchTable */
- u8 TxRateTableSize; /* Valid Tx rate table size in RateSwitchTable */
- /*BOOLEAN bAutoTxRateSwitch; */
- u8 MinTxRate; /* RATE_1, RATE_2, RATE_5_5, RATE_11 */
- u8 RtsRate; /* RATE_xxx */
- HTTRANSMIT_SETTING MlmeTransmit; /* MGMT frame PHY rate setting when operation at Ht rate. */
- u8 MlmeRate; /* RATE_xxx, used to send MLME frames */
- u8 BasicMlmeRate; /* Default Rate for sending MLME frames */
-
- u16 RtsThreshold; /* in unit of BYTE */
- u16 FragmentThreshold; /* in unit of BYTE */
-
- u8 TxPower; /* in unit of mW */
- unsigned long TxPowerPercentage; /* 0~100 % */
- unsigned long TxPowerDefault; /* keep for TxPowerPercentage */
- u8 PwrConstraint;
-
- BACAP_STRUC BACapability; /* NO USE = 0XFF ; IMMED_BA =1 ; DELAY_BA=0 */
- BACAP_STRUC REGBACapability; /* NO USE = 0XFF ; IMMED_BA =1 ; DELAY_BA=0 */
-
- struct rt_iot IOTestParm; /* 802.11n InterOpbility Test Parameter; */
- unsigned long TxPreamble; /* Rt802_11PreambleLong, Rt802_11PreambleShort, Rt802_11PreambleAuto */
- BOOLEAN bUseZeroToDisableFragment; /* Microsoft use 0 as disable */
- unsigned long UseBGProtection; /* 0: auto, 1: always use, 2: always not use */
- BOOLEAN bUseShortSlotTime; /* 0: disable, 1 - use short slot (9us) */
- BOOLEAN bEnableTxBurst; /* 1: enble TX PACKET BURST (when BA is established or AP is not a legacy WMM AP), 0: disable TX PACKET BURST */
- BOOLEAN bAggregationCapable; /* 1: enable TX aggregation when the peer supports it */
- BOOLEAN bPiggyBackCapable; /* 1: enable TX piggy-back according MAC's version */
- BOOLEAN bIEEE80211H; /* 1: enable IEEE802.11h spec. */
- unsigned long DisableOLBCDetect; /* 0: enable OLBC detect; 1 disable OLBC detect */
-
- BOOLEAN bRdg;
-
- BOOLEAN bWmmCapable; /* 0:disable WMM, 1:enable WMM */
- struct rt_qos_capability_parm APQosCapability; /* QOS capability of the current associated AP */
- struct rt_edca_parm APEdcaParm; /* EDCA parameters of the current associated AP */
- struct rt_qbss_load_parm APQbssLoad; /* QBSS load of the current associated AP */
- u8 AckPolicy[4]; /* ACK policy of the specified AC. see ACK_xxx */
- BOOLEAN bDLSCapable; /* 0:disable DLS, 1:enable DLS */
- /* a bitmap of BOOLEAN flags. each bit represent an operation status of a particular */
- /* BOOLEAN control, either ON or OFF. These flags should always be accessed via */
- /* OPSTATUS_TEST_FLAG(), OPSTATUS_SET_FLAG(), OP_STATUS_CLEAR_FLAG() macros. */
- /* see fOP_STATUS_xxx in RTMP_DEF.C for detail bit definition */
- unsigned long OpStatusFlags;
-
- BOOLEAN NdisRadioStateOff; /*For HCT 12.0, set this flag to TRUE instead of called MlmeRadioOff. */
- ABGBAND_STATE BandState; /* For setting BBP used on B/G or A mode. */
-
- /* IEEE802.11H--DFS. */
- struct rt_radar_detect RadarDetect;
-
- /* HT */
- u8 BASize; /* USer desired BAWindowSize. Should not exceed our max capability */
- /*struct rt_ht_capability SupportedHtPhy; */
- struct rt_ht_capability DesiredHtPhy;
- struct rt_ht_capability_ie HtCapability;
- struct rt_add_ht_info_ie AddHTInfo; /* Useful as AP. */
- /*This IE is used with channel switch announcement element when changing to a new 40MHz. */
- /*This IE is included in channel switch announcement frames 7.4.1.5, beacons, probe Rsp. */
- struct rt_new_ext_chan_ie NewExtChanOffset; /*7.3.2.20A, 1 if extension channel is above the control channel, 3 if below, 0 if not present */
-
- BOOLEAN bHTProtect;
- BOOLEAN bMIMOPSEnable;
- BOOLEAN bBADecline;
-/*2008/11/05: KH add to support Antenna power-saving of AP<-- */
- BOOLEAN bGreenAPEnable;
-/*2008/11/05: KH add to support Antenna power-saving of AP--> */
- BOOLEAN bDisableReordering;
- BOOLEAN bForty_Mhz_Intolerant;
- BOOLEAN bExtChannelSwitchAnnouncement;
- BOOLEAN bRcvBSSWidthTriggerEvents;
- unsigned long LastRcvBSSWidthTriggerEventsTime;
-
- u8 TxBASize;
-
- /* Enable wireless event */
- BOOLEAN bWirelessEvent;
- BOOLEAN bWiFiTest; /* Enable this parameter for WiFi test */
-
- /* Tx & Rx Stream number selection */
- u8 TxStream;
- u8 RxStream;
-
- BOOLEAN bHardwareRadio; /* Hardware controlled Radio enabled */
-
-#ifdef RTMP_MAC_USB
- BOOLEAN bMultipleIRP; /* Multiple Bulk IN flag */
- u8 NumOfBulkInIRP; /* if bMultipleIRP == TRUE, NumOfBulkInIRP will be 4 otherwise be 1 */
- struct rt_ht_capability SupportedHtPhy;
- unsigned long MaxPktOneTxBulk;
- u8 TxBulkFactor;
- u8 RxBulkFactor;
-
- BOOLEAN IsUpdateBeacon;
- struct rt_beacon_sync *pBeaconSync;
- struct rt_ralink_timer BeaconUpdateTimer;
- u32 BeaconAdjust;
- u32 BeaconFactor;
- u32 BeaconRemain;
-#endif /* RTMP_MAC_USB // */
-
- spinlock_t MeasureReqTabLock;
- struct rt_measure_req_tab *pMeasureReqTab;
-
- spinlock_t TpcReqTabLock;
- struct rt_tpc_req_tab *pTpcReqTab;
-
- BOOLEAN PSPXlink; /* 0: Disable. 1: Enable */
-
-#if defined(RT305x) || defined(RT30xx)
- /* request by Gary, for High Power issue */
- u8 HighPowerPatchDisabled;
-#endif
-
- BOOLEAN HT_DisallowTKIP; /* Restrict the encryption type in 11n HT mode */
-};
-
-/* Modified by Wu Xi-Kun 4/21/2006 */
-/* STA configuration and status */
-struct rt_sta_admin_config {
- /* GROUP 1 - */
- /* User configuration loaded from Registry, E2PROM or OID_xxx. These settings describe */
- /* the user intended configuration, but not necessary fully equal to the final */
- /* settings in ACTIVE BSS after negotiation/compromise with the BSS holder (either */
- /* AP or IBSS holder). */
- /* Once initialized, user configuration can only be changed via OID_xxx */
- u8 BssType; /* BSS_INFRA or BSS_ADHOC */
- u16 AtimWin; /* used when starting a new IBSS */
-
- /* GROUP 2 - */
- /* User configuration loaded from Registry, E2PROM or OID_xxx. These settings describe */
- /* the user intended configuration, and should be always applied to the final */
- /* settings in ACTIVE BSS without compromising with the BSS holder. */
- /* Once initialized, user configuration can only be changed via OID_xxx */
- u8 RssiTrigger;
- u8 RssiTriggerMode; /* RSSI_TRIGGERED_UPON_BELOW_THRESHOLD or RSSI_TRIGGERED_UPON_EXCCEED_THRESHOLD */
- u16 DefaultListenCount; /* default listen count; */
- unsigned long WindowsPowerMode; /* Power mode for AC power */
- unsigned long WindowsBatteryPowerMode; /* Power mode for battery if exists */
- BOOLEAN bWindowsACCAMEnable; /* Enable CAM power mode when AC on */
- BOOLEAN bAutoReconnect; /* Set to TRUE when setting OID_802_11_SSID with no matching BSSID */
- unsigned long WindowsPowerProfile; /* Windows power profile, for NDIS5.1 PnP */
-
- /* MIB:ieee802dot11.dot11smt(1).dot11StationConfigTable(1) */
- u16 Psm; /* power management mode (PWR_ACTIVE|PWR_SAVE) */
- u16 DisassocReason;
- u8 DisassocSta[MAC_ADDR_LEN];
- u16 DeauthReason;
- u8 DeauthSta[MAC_ADDR_LEN];
- u16 AuthFailReason;
- u8 AuthFailSta[MAC_ADDR_LEN];
-
- NDIS_802_11_PRIVACY_FILTER PrivacyFilter; /* PrivacyFilter enum for 802.1X */
- NDIS_802_11_AUTHENTICATION_MODE AuthMode; /* This should match to whatever microsoft defined */
- NDIS_802_11_WEP_STATUS WepStatus;
- NDIS_802_11_WEP_STATUS OrigWepStatus; /* Original wep status set from OID */
-
- /* Add to support different cipher suite for WPA2/WPA mode */
- NDIS_802_11_ENCRYPTION_STATUS GroupCipher; /* Multicast cipher suite */
- NDIS_802_11_ENCRYPTION_STATUS PairCipher; /* Unicast cipher suite */
- BOOLEAN bMixCipher; /* Indicate current Pair & Group use different cipher suites */
- u16 RsnCapability;
-
- NDIS_802_11_WEP_STATUS GroupKeyWepStatus;
-
- u8 WpaPassPhrase[64]; /* WPA PSK pass phrase */
- u32 WpaPassPhraseLen; /* the length of WPA PSK pass phrase */
- u8 PMK[32]; /* WPA PSK mode PMK */
- u8 PTK[64]; /* WPA PSK mode PTK */
- u8 GTK[32]; /* GTK from authenticator */
- struct rt_bssid_info SavedPMK[PMKID_NO];
- u32 SavedPMKNum; /* Saved PMKID number */
-
- u8 DefaultKeyId;
-
- /* WPA 802.1x port control, WPA_802_1X_PORT_SECURED, WPA_802_1X_PORT_NOT_SECURED */
- u8 PortSecured;
-
- /* For WPA countermeasures */
- unsigned long LastMicErrorTime; /* record last MIC error time */
- unsigned long MicErrCnt; /* Should be 0, 1, 2, then reset to zero (after disassociation). */
- BOOLEAN bBlockAssoc; /* Block associate attempt for 60 seconds after counter measure occurred. */
- /* For WPA-PSK supplicant state */
- WPA_STATE WpaState; /* Default is SS_NOTUSE and handled by microsoft 802.1x */
- u8 ReplayCounter[8];
- u8 ANonce[32]; /* ANonce for WPA-PSK from auhenticator */
- u8 SNonce[32]; /* SNonce for WPA-PSK */
-
- u8 LastSNR0; /* last received BEACON's SNR */
- u8 LastSNR1; /* last received BEACON's SNR for 2nd antenna */
- struct rt_rssi_sample RssiSample;
- unsigned long NumOfAvgRssiSample;
-
- unsigned long LastBeaconRxTime; /* OS's timestamp of the last BEACON RX time */
- unsigned long Last11bBeaconRxTime; /* OS's timestamp of the last 11B BEACON RX time */
- unsigned long Last11gBeaconRxTime; /* OS's timestamp of the last 11G BEACON RX time */
- unsigned long Last20NBeaconRxTime; /* OS's timestamp of the last 20MHz N BEACON RX time */
-
- unsigned long LastScanTime; /* Record last scan time for issue BSSID_SCAN_LIST */
- unsigned long ScanCnt; /* Scan counts since most recent SSID, BSSID, SCAN OID request */
- BOOLEAN bSwRadio; /* Software controlled Radio On/Off, TRUE: On */
- BOOLEAN bHwRadio; /* Hardware controlled Radio On/Off, TRUE: On */
- BOOLEAN bRadio; /* Radio state, And of Sw & Hw radio state */
- BOOLEAN bHardwareRadio; /* Hardware controlled Radio enabled */
- BOOLEAN bShowHiddenSSID; /* Show all known SSID in SSID list get operation */
-
- /* New for WPA, windows want us to keep association information and */
- /* Fixed IEs from last association response */
- struct rt_ndis_802_11_association_information AssocInfo;
- u16 ReqVarIELen; /* Length of next VIE include EID & Length */
- u8 ReqVarIEs[MAX_VIE_LEN]; /* The content saved here should be little-endian format. */
- u16 ResVarIELen; /* Length of next VIE include EID & Length */
- u8 ResVarIEs[MAX_VIE_LEN];
-
- u8 RSNIE_Len;
- u8 RSN_IE[MAX_LEN_OF_RSNIE]; /* The content saved here should be little-endian format. */
-
- unsigned long CLBusyBytes; /* Save the total bytes received during channel load scan time */
- u16 RPIDensity[8]; /* Array for RPI density collection */
-
- u8 RMReqCnt; /* Number of measurement request saved. */
- u8 CurrentRMReqIdx; /* Number of measurement request saved. */
- BOOLEAN ParallelReq; /* Parallel measurement, only one request performed, */
- /* It must be the same channel with maximum duration */
- u16 ParallelDuration; /* Maximum duration for parallel measurement */
- u8 ParallelChannel; /* Only one channel with parallel measurement */
- u16 IAPPToken; /* IAPP dialog token */
- /* Hack for channel load and noise histogram parameters */
- u8 NHFactor; /* Parameter for Noise histogram */
- u8 CLFactor; /* Parameter for channel load */
-
- struct rt_ralink_timer StaQuickResponeForRateUpTimer;
- BOOLEAN StaQuickResponeForRateUpTimerRunning;
-
- u8 DtimCount; /* 0.. DtimPeriod-1 */
- u8 DtimPeriod; /* default = 3 */
-
- /*////////////////////////////////////////////////////////////////////////////////////// */
- /* This is only for WHQL test. */
- BOOLEAN WhqlTest;
- /*////////////////////////////////////////////////////////////////////////////////////// */
-
- struct rt_ralink_timer WpaDisassocAndBlockAssocTimer;
- /* Fast Roaming */
- BOOLEAN bAutoRoaming; /* 0:disable auto roaming by RSSI, 1:enable auto roaming by RSSI */
- char dBmToRoam; /* the condition to roam when receiving Rssi less than this value. It's negative value. */
-
- BOOLEAN IEEE8021X;
- BOOLEAN IEEE8021x_required_keys;
- struct rt_cipher_key DesireSharedKey[4]; /* Record user desired WEP keys */
- u8 DesireSharedKeyId;
-
- /* 0: driver ignores wpa_supplicant */
- /* 1: wpa_supplicant initiates scanning and AP selection */
- /* 2: driver takes care of scanning, AP selection, and IEEE 802.11 association parameters */
- u8 WpaSupplicantUP;
- u8 WpaSupplicantScanCount;
- BOOLEAN bRSN_IE_FromWpaSupplicant;
-
- char dev_name[16];
- u16 OriDevType;
-
- BOOLEAN bTGnWifiTest;
- BOOLEAN bScanReqIsFromWebUI;
-
- HTTRANSMIT_SETTING HTPhyMode, MaxHTPhyMode, MinHTPhyMode; /* For transmit phy setting in TXWI. */
- DESIRED_TRANSMIT_SETTING DesiredTransmitSetting;
- struct rt_ht_phy_info DesiredHtPhyInfo;
- BOOLEAN bAutoTxRateSwitch;
-
-#ifdef RTMP_MAC_PCI
- u8 BBPR3;
- /* PS Control has 2 meanings for advanced power save function. */
- /* 1. EnablePSinIdle : When no connection, always radio off except need to do site survey. */
- /* 2. EnableNewPS : will save more current in sleep or radio off mode. */
- PS_CONTROL PSControl;
-#endif /* RTMP_MAC_PCI // */
-
- BOOLEAN bAutoConnectByBssid;
- unsigned long BeaconLostTime; /* seconds */
- BOOLEAN bForceTxBurst; /* 1: force enble TX PACKET BURST, 0: disable */
-};
-
-/* This data structure keeps the current active BSS/IBSS's configuration that this STA */
-/* had agreed upon joining the network. Which means these parameters are usually decided */
-/* by the BSS/IBSS creator instead of user configuration. Data in this data structure */
-/* is valid only when either ADHOC_ON(pAd) or INFRA_ON(pAd) is TRUE. */
-/* Normally, after SCAN or failed roaming attempts, we need to recover back to */
-/* the current active settings. */
-struct rt_sta_active_config {
- u16 Aid;
- u16 AtimWin; /* in kusec; IBSS parameter set element */
- u16 CapabilityInfo;
- u16 CfpMaxDuration;
- u16 CfpPeriod;
-
- /* Copy supported rate from desired AP's beacon. We are trying to match */
- /* AP's supported and extended rate settings. */
- u8 SupRate[MAX_LEN_OF_SUPPORTED_RATES];
- u8 ExtRate[MAX_LEN_OF_SUPPORTED_RATES];
- u8 SupRateLen;
- u8 ExtRateLen;
- /* Copy supported ht from desired AP's beacon. We are trying to match */
- struct rt_ht_phy_info SupportedPhyInfo;
- struct rt_ht_capability SupportedHtPhy;
-};
-
-struct rt_mac_table_entry;
-
-struct rt_mac_table_entry {
- /*Choose 1 from ValidAsWDS and ValidAsCLI to validize. */
- BOOLEAN ValidAsCLI; /* Sta mode, set this TRUE after Linkup,too. */
- BOOLEAN ValidAsWDS; /* This is WDS Entry. only for AP mode. */
- BOOLEAN ValidAsApCli; /* This is a AP-Client entry, only for AP mode which enable AP-Client functions. */
- BOOLEAN ValidAsMesh;
- BOOLEAN ValidAsDls; /* This is DLS Entry. only for STA mode. */
- BOOLEAN isCached;
- BOOLEAN bIAmBadAtheros; /* Flag if this is Atheros chip that has IOT problem. We need to turn on RTS/CTS protection. */
-
- u8 EnqueueEapolStartTimerRunning; /* Enqueue EAPoL-Start for triggering EAP SM */
- /*jan for wpa */
- /* record which entry revoke MIC Failure, if it leaves the BSS itself, AP won't update aMICFailTime MIB */
- u8 CMTimerRunning;
- u8 apidx; /* MBSS number */
- u8 RSNIE_Len;
- u8 RSN_IE[MAX_LEN_OF_RSNIE];
- u8 ANonce[LEN_KEY_DESC_NONCE];
- u8 SNonce[LEN_KEY_DESC_NONCE];
- u8 R_Counter[LEN_KEY_DESC_REPLAY];
- u8 PTK[64];
- u8 ReTryCounter;
- struct rt_ralink_timer RetryTimer;
- struct rt_ralink_timer EnqueueStartForPSKTimer; /* A timer which enqueue EAPoL-Start for triggering PSK SM */
- NDIS_802_11_AUTHENTICATION_MODE AuthMode; /* This should match to whatever microsoft defined */
- NDIS_802_11_WEP_STATUS WepStatus;
- NDIS_802_11_WEP_STATUS GroupKeyWepStatus;
- AP_WPA_STATE WpaState;
- GTK_STATE GTKState;
- u16 PortSecured;
- NDIS_802_11_PRIVACY_FILTER PrivacyFilter; /* PrivacyFilter enum for 802.1X */
- struct rt_cipher_key PairwiseKey;
- void *pAd;
- int PMKID_CacheIdx;
- u8 PMKID[LEN_PMKID];
-
- u8 Addr[MAC_ADDR_LEN];
- u8 PsMode;
- SST Sst;
- AUTH_STATE AuthState; /* for SHARED KEY authentication state machine used only */
- BOOLEAN IsReassocSta; /* Indicate whether this is a reassociation procedure */
- u16 Aid;
- u16 CapabilityInfo;
- u8 LastRssi;
- unsigned long NoDataIdleCount;
- u16 StationKeepAliveCount; /* unit: second */
- unsigned long PsQIdleCount;
- struct rt_queue_header PsQueue;
-
- u32 StaConnectTime; /* the live time of this station since associated with AP */
-
- BOOLEAN bSendBAR;
- u16 NoBADataCountDown;
-
- u32 CachedBuf[16]; /* u32 (4 bytes) for alignment */
- u32 TxBFCount; /* 3*3 */
- u32 FIFOCount;
- u32 DebugFIFOCount;
- u32 DebugTxCount;
- BOOLEAN bDlsInit;
-
-/*==================================================== */
-/*WDS entry needs these */
-/* if ValidAsWDS==TRUE, MatchWDSTabIdx is the index in WdsTab.MacTab */
- u32 MatchWDSTabIdx;
- u8 MaxSupportedRate;
- u8 CurrTxRate;
- u8 CurrTxRateIndex;
- /* to record the each TX rate's quality. 0 is best, the bigger the worse. */
- u16 TxQuality[MAX_STEP_OF_TX_RATE_SWITCH];
-/* u16 OneSecTxOkCount; */
- u32 OneSecTxNoRetryOkCount;
- u32 OneSecTxRetryOkCount;
- u32 OneSecTxFailCount;
- u32 ContinueTxFailCnt;
- u32 CurrTxRateStableTime; /* # of second in current TX rate */
- u8 TxRateUpPenalty; /* extra # of second penalty due to last unstable condition */
-/*==================================================== */
-
- BOOLEAN fNoisyEnvironment;
- BOOLEAN fLastSecAccordingRSSI;
- u8 LastSecTxRateChangeAction; /* 0: no change, 1:rate UP, 2:rate down */
- char LastTimeTxRateChangeAction; /*Keep last time value of LastSecTxRateChangeAction */
- unsigned long LastTxOkCount;
- u8 PER[MAX_STEP_OF_TX_RATE_SWITCH];
-
- /* a bitmap of BOOLEAN flags. each bit represent an operation status of a particular */
- /* BOOLEAN control, either ON or OFF. These flags should always be accessed via */
- /* CLIENT_STATUS_TEST_FLAG(), CLIENT_STATUS_SET_FLAG(), CLIENT_STATUS_CLEAR_FLAG() macros. */
- /* see fOP_STATUS_xxx in RTMP_DEF.C for detail bit definition. fCLIENT_STATUS_AMSDU_INUSED */
- unsigned long ClientStatusFlags;
-
- HTTRANSMIT_SETTING HTPhyMode, MaxHTPhyMode, MinHTPhyMode; /* For transmit phy setting in TXWI. */
-
- /* HT EWC MIMO-N used parameters */
- u16 RXBAbitmap; /* fill to on-chip RXWI_BA_BITMASK in 8.1.3RX attribute entry format */
- u16 TXBAbitmap; /* This bitmap as originator, only keep in software used to mark AMPDU bit in TXWI */
- u16 TXAutoBAbitmap;
- u16 BADeclineBitmap;
- u16 BARecWcidArray[NUM_OF_TID]; /* The mapping wcid of recipient session. if RXBAbitmap bit is masked */
- u16 BAOriWcidArray[NUM_OF_TID]; /* The mapping wcid of originator session. if TXBAbitmap bit is masked */
- u16 BAOriSequence[NUM_OF_TID]; /* The mapping wcid of originator session. if TXBAbitmap bit is masked */
-
- /* 802.11n features. */
- u8 MpduDensity;
- u8 MaxRAmpduFactor;
- u8 AMsduSize;
- u8 MmpsMode; /* MIMO power save more. */
-
- struct rt_ht_capability_ie HTCapability;
-
- BOOLEAN bAutoTxRateSwitch;
-
- u8 RateLen;
- struct rt_mac_table_entry *pNext;
- u16 TxSeq[NUM_OF_TID];
- u16 NonQosDataSeq;
-
- struct rt_rssi_sample RssiSample;
-
- u32 TXMCSExpected[16];
- u32 TXMCSSuccessful[16];
- u32 TXMCSFailed[16];
- u32 TXMCSAutoFallBack[16][16];
-
- unsigned long LastBeaconRxTime;
-
- unsigned long AssocDeadLine;
-};
-
-struct rt_mac_table {
- u16 Size;
- struct rt_mac_table_entry *Hash[HASH_TABLE_SIZE];
- struct rt_mac_table_entry Content[MAX_LEN_OF_MAC_TABLE];
- struct rt_queue_header McastPsQueue;
- unsigned long PsQIdleCount;
- BOOLEAN fAnyStationInPsm;
- BOOLEAN fAnyStationBadAtheros; /* Check if any Station is atheros 802.11n Chip. We need to use RTS/CTS with Atheros 802,.11n chip. */
- BOOLEAN fAnyTxOPForceDisable; /* Check if it is necessary to disable BE TxOP */
- BOOLEAN fAllStationAsRalink; /* Check if all stations are ralink-chipset */
- BOOLEAN fAnyStationIsLegacy; /* Check if I use legacy rate to transmit to my BSS Station/ */
- BOOLEAN fAnyStationNonGF; /* Check if any Station can't support GF. */
- BOOLEAN fAnyStation20Only; /* Check if any Station can't support GF. */
- BOOLEAN fAnyStationMIMOPSDynamic; /* Check if any Station is MIMO Dynamic */
- BOOLEAN fAnyBASession; /* Check if there is BA session. Force turn on RTS/CTS */
-/*2008/10/28: KH add to support Antenna power-saving of AP<-- */
-/*2008/10/28: KH add to support Antenna power-saving of AP--> */
-};
-
-struct wificonf {
- BOOLEAN bShortGI;
- BOOLEAN bGreenField;
-};
-
-struct rt_rtmp_dev_info {
- u8 chipName[16];
- RTMP_INF_TYPE infType;
-};
-
-struct rt_rtmp_chip_op {
- /* Calibration access related callback functions */
- int (*eeinit) (struct rt_rtmp_adapter *pAd); /* int (*eeinit)(struct rt_rtmp_adapter *pAd); */
- int (*eeread) (struct rt_rtmp_adapter *pAd, u16 offset, u16 *pValue); /* int (*eeread)(struct rt_rtmp_adapter *pAd, int offset, u16 *pValue); */
-
- /* MCU related callback functions */
- int (*loadFirmware) (struct rt_rtmp_adapter *pAd); /* int (*loadFirmware)(struct rt_rtmp_adapter *pAd); */
- int (*eraseFirmware) (struct rt_rtmp_adapter *pAd); /* int (*eraseFirmware)(struct rt_rtmp_adapter *pAd); */
- int (*sendCommandToMcu) (struct rt_rtmp_adapter *pAd, u8 cmd, u8 token, u8 arg0, u8 arg1);; /* int (*sendCommandToMcu)(struct rt_rtmp_adapter *pAd, u8 cmd, u8 token, u8 arg0, u8 arg1); */
-
- /* RF access related callback functions */
- struct rt_reg_pair *pRFRegTable;
- void (*AsicRfInit) (struct rt_rtmp_adapter *pAd);
- void (*AsicRfTurnOn) (struct rt_rtmp_adapter *pAd);
- void (*AsicRfTurnOff) (struct rt_rtmp_adapter *pAd);
- void (*AsicReverseRfFromSleepMode) (struct rt_rtmp_adapter *pAd);
- void (*AsicHaltAction) (struct rt_rtmp_adapter *pAd);
-};
-
-/* */
-/* The miniport adapter structure */
-/* */
-struct rt_rtmp_adapter {
- void *OS_Cookie; /* save specific structure relative to OS */
- struct net_device *net_dev;
- unsigned long VirtualIfCnt;
- const struct firmware *firmware;
-
- struct rt_rtmp_chip_op chipOps;
- u16 ThisTbttNumToNextWakeUp;
-
-#ifdef RTMP_MAC_PCI
-/*****************************************************************************************/
-/* PCI related parameters */
-/*****************************************************************************************/
- u8 *CSRBaseAddress; /* PCI MMIO Base Address, all access will use */
- unsigned int irq_num;
-
- u16 LnkCtrlBitMask;
- u16 RLnkCtrlConfiguration;
- u16 RLnkCtrlOffset;
- u16 HostLnkCtrlConfiguration;
- u16 HostLnkCtrlOffset;
- u16 PCIePowerSaveLevel;
- unsigned long Rt3xxHostLinkCtrl; /* USed for 3090F chip */
- unsigned long Rt3xxRalinkLinkCtrl; /* USed for 3090F chip */
- u16 DeviceID; /* Read from PCI config */
- unsigned long AccessBBPFailCount;
- BOOLEAN bPCIclkOff; /* flag that indicates if the PICE power status in Configuration Space.. */
- BOOLEAN bPCIclkOffDisableTx; /* */
-
- BOOLEAN brt30xxBanMcuCmd; /*when = 0xff means all commands are ok to set . */
- BOOLEAN b3090ESpecialChip; /*3090E special chip that write EEPROM 0x24=0x9280. */
- unsigned long CheckDmaBusyCount; /* Check Interrupt Status Register Count. */
-
- u32 int_enable_reg;
- u32 int_disable_mask;
- u32 int_pending;
-
- struct rt_rtmp_dmabuf TxBufSpace[NUM_OF_TX_RING]; /* Shared memory of all 1st pre-allocated TxBuf associated with each TXD */
- struct rt_rtmp_dmabuf RxDescRing; /* Shared memory for RX descriptors */
- struct rt_rtmp_dmabuf TxDescRing[NUM_OF_TX_RING]; /* Shared memory for Tx descriptors */
- struct rt_rtmp_tx_ring TxRing[NUM_OF_TX_RING]; /* AC0~4 + HCCA */
-#endif /* RTMP_MAC_PCI // */
-
- spinlock_t irq_lock;
- u8 irq_disabled;
-
-#ifdef RTMP_MAC_USB
-/*****************************************************************************************/
-/* USB related parameters */
-/*****************************************************************************************/
- struct usb_config_descriptor *config;
- u32 BulkInEpAddr; /* bulk-in endpoint address */
- u32 BulkOutEpAddr[6]; /* bulk-out endpoint address */
-
- u32 NumberOfPipes;
- u16 BulkOutMaxPacketSize;
- u16 BulkInMaxPacketSize;
-
- /*======Control Flags */
- long PendingIoCount;
- unsigned long BulkFlags;
- BOOLEAN bUsbTxBulkAggre; /* Flags for bulk out data priority */
-
- /*======Cmd Thread */
- struct rt_cmdq CmdQ;
- spinlock_t CmdQLock; /* CmdQLock spinlock */
- struct rt_rtmp_os_task cmdQTask;
-
- /*======Semaphores (event) */
- struct semaphore UsbVendorReq_semaphore;
- void *UsbVendorReqBuf;
- wait_queue_head_t *wait;
-#endif /* RTMP_MAC_USB // */
-
-/*****************************************************************************************/
-/* RBUS related parameters */
-/*****************************************************************************************/
-
-/*****************************************************************************************/
-/* Both PCI/USB related parameters */
-/*****************************************************************************************/
- /*struct rt_rtmp_dev_info chipInfo; */
- RTMP_INF_TYPE infType;
-
-/*****************************************************************************************/
-/* Driver Mgmt related parameters */
-/*****************************************************************************************/
- struct rt_rtmp_os_task mlmeTask;
-#ifdef RTMP_TIMER_TASK_SUPPORT
- /* If you want use timer task to handle the timer related jobs, enable this. */
- struct rt_rtmp_timer_task_queue TimerQ;
- spinlock_t TimerQLock;
- struct rt_rtmp_os_task timerTask;
-#endif /* RTMP_TIMER_TASK_SUPPORT // */
-
-/*****************************************************************************************/
-/* Tx related parameters */
-/*****************************************************************************************/
- BOOLEAN DeQueueRunning[NUM_OF_TX_RING]; /* for ensuring RTUSBDeQueuePacket get call once */
- spinlock_t DeQueueLock[NUM_OF_TX_RING];
-
-#ifdef RTMP_MAC_USB
- /* Data related context and AC specified, 4 AC supported */
- spinlock_t BulkOutLock[6]; /* BulkOut spinlock for 4 ACs */
- spinlock_t MLMEBulkOutLock; /* MLME BulkOut lock */
-
- struct rt_ht_tx_context TxContext[NUM_OF_TX_RING];
- spinlock_t TxContextQueueLock[NUM_OF_TX_RING]; /* TxContextQueue spinlock */
-
- /* 4 sets of Bulk Out index and pending flag */
- u8 NextBulkOutIndex[4]; /* only used for 4 EDCA bulkout pipe */
-
- BOOLEAN BulkOutPending[6]; /* used for total 6 bulkout pipe */
- u8 bulkResetPipeid;
- BOOLEAN MgmtBulkPending;
- unsigned long bulkResetReq[6];
-#endif /* RTMP_MAC_USB // */
-
- /* resource for software backlog queues */
- struct rt_queue_header TxSwQueue[NUM_OF_TX_RING]; /* 4 AC + 1 HCCA */
- spinlock_t TxSwQueueLock[NUM_OF_TX_RING]; /* TxSwQueue spinlock */
-
- struct rt_rtmp_dmabuf MgmtDescRing; /* Shared memory for MGMT descriptors */
- struct rt_rtmp_mgmt_ring MgmtRing;
- spinlock_t MgmtRingLock; /* Prio Ring spinlock */
-
-/*****************************************************************************************/
-/* Rx related parameters */
-/*****************************************************************************************/
-
-#ifdef RTMP_MAC_PCI
- struct rt_rtmp_rx_ring RxRing;
- spinlock_t RxRingLock; /* Rx Ring spinlock */
-#ifdef RT3090
- spinlock_t McuCmdLock; /*MCU Command Queue spinlock */
-#endif /* RT3090 // */
-#endif /* RTMP_MAC_PCI // */
-#ifdef RTMP_MAC_USB
- struct rt_rx_context RxContext[RX_RING_SIZE]; /* 1 for redundant multiple IRP bulk in. */
- spinlock_t BulkInLock; /* BulkIn spinlock for 4 ACs */
- u8 PendingRx; /* The Maximum pending Rx value should be RX_RING_SIZE. */
- u8 NextRxBulkInIndex; /* Indicate the current RxContext Index which hold by Host controller. */
- u8 NextRxBulkInReadIndex; /* Indicate the current RxContext Index which driver can read & process it. */
- unsigned long NextRxBulkInPosition; /* Want to contatenate 2 URB buffer while 1st is bulkin failed URB. This Position is 1st URB TransferLength. */
- unsigned long TransferBufferLength; /* current length of the packet buffer */
- unsigned long ReadPosition; /* current read position in a packet buffer */
-#endif /* RTMP_MAC_USB // */
-
-/*****************************************************************************************/
-/* ASIC related parameters */
-/*****************************************************************************************/
- u32 MACVersion; /* MAC version. Record rt2860C(0x28600100) or rt2860D (0x28600101).. */
-
- /* --------------------------- */
- /* E2PROM */
- /* --------------------------- */
- unsigned long EepromVersion; /* byte 0: version, byte 1: revision, byte 2~3: unused */
- unsigned long FirmwareVersion; /* byte 0: Minor version, byte 1: Major version, otherwise unused. */
- u16 EEPROMDefaultValue[NUM_EEPROM_BBP_PARMS];
- u8 EEPROMAddressNum; /* 93c46=6 93c66=8 */
- BOOLEAN EepromAccess;
- u8 EFuseTag;
-
- /* --------------------------- */
- /* BBP Control */
- /* --------------------------- */
- u8 BbpWriteLatch[140]; /* record last BBP register value written via BBP_IO_WRITE/BBP_IO_WRITE_VY_REG_ID */
- char BbpRssiToDbmDelta; /* change from u8 to char for high power */
- struct rt_bbp_r66_tuning BbpTuning;
-
- /* ---------------------------- */
- /* RFIC control */
- /* ---------------------------- */
- u8 RfIcType; /* RFIC_xxx */
- unsigned long RfFreqOffset; /* Frequency offset for channel switching */
- struct rt_rtmp_rf_regs LatchRfRegs; /* latch the latest RF programming value since RF IC doesn't support READ */
-
- EEPROM_ANTENNA_STRUC Antenna; /* Since Antenna definition is different for a & g. We need to save it for future reference. */
- EEPROM_NIC_CONFIG2_STRUC NicConfig2;
-
- /* This soft Rx Antenna Diversity mechanism is used only when user set */
- /* RX Antenna = DIVERSITY ON */
- struct rt_soft_rx_ant_diversity RxAnt;
-
- u8 RFProgSeq;
- struct rt_channel_tx_power TxPower[MAX_NUM_OF_CHANNELS]; /* Store Tx power value for all channels. */
- struct rt_channel_tx_power ChannelList[MAX_NUM_OF_CHANNELS]; /* list all supported channels for site survey */
- struct rt_channel_11j_tx_power TxPower11J[MAX_NUM_OF_11JCHANNELS]; /* 802.11j channel and bw */
- struct rt_channel_11j_tx_power ChannelList11J[MAX_NUM_OF_11JCHANNELS]; /* list all supported channels for site survey */
-
- u8 ChannelListNum; /* number of channel in ChannelList[] */
- u8 Bbp94;
- BOOLEAN BbpForCCK;
- unsigned long Tx20MPwrCfgABand[5];
- unsigned long Tx20MPwrCfgGBand[5];
- unsigned long Tx40MPwrCfgABand[5];
- unsigned long Tx40MPwrCfgGBand[5];
-
- BOOLEAN bAutoTxAgcA; /* Enable driver auto Tx Agc control */
- u8 TssiRefA; /* Store Tssi reference value as 25 temperature. */
- u8 TssiPlusBoundaryA[5]; /* Tssi boundary for increase Tx power to compensate. */
- u8 TssiMinusBoundaryA[5]; /* Tssi boundary for decrease Tx power to compensate. */
- u8 TxAgcStepA; /* Store Tx TSSI delta increment / decrement value */
- char TxAgcCompensateA; /* Store the compensation (TxAgcStep * (idx-1)) */
-
- BOOLEAN bAutoTxAgcG; /* Enable driver auto Tx Agc control */
- u8 TssiRefG; /* Store Tssi reference value as 25 temperature. */
- u8 TssiPlusBoundaryG[5]; /* Tssi boundary for increase Tx power to compensate. */
- u8 TssiMinusBoundaryG[5]; /* Tssi boundary for decrease Tx power to compensate. */
- u8 TxAgcStepG; /* Store Tx TSSI delta increment / decrement value */
- char TxAgcCompensateG; /* Store the compensation (TxAgcStep * (idx-1)) */
-
- char BGRssiOffset0; /* Store B/G RSSI#0 Offset value on EEPROM 0x46h */
- char BGRssiOffset1; /* Store B/G RSSI#1 Offset value */
- char BGRssiOffset2; /* Store B/G RSSI#2 Offset value */
-
- char ARssiOffset0; /* Store A RSSI#0 Offset value on EEPROM 0x4Ah */
- char ARssiOffset1; /* Store A RSSI#1 Offset value */
- char ARssiOffset2; /* Store A RSSI#2 Offset value */
-
- char BLNAGain; /* Store B/G external LNA#0 value on EEPROM 0x44h */
- char ALNAGain0; /* Store A external LNA#0 value for ch36~64 */
- char ALNAGain1; /* Store A external LNA#1 value for ch100~128 */
- char ALNAGain2; /* Store A external LNA#2 value for ch132~165 */
-#ifdef RT30xx
- /* for 3572 */
- u8 Bbp25;
- u8 Bbp26;
-
- u8 TxMixerGain24G; /* Tx mixer gain value from EEPROM to improve Tx EVM / Tx DAC, 2.4G */
- u8 TxMixerGain5G;
-#endif /* RT30xx // */
- /* ---------------------------- */
- /* LED control */
- /* ---------------------------- */
- MCU_LEDCS_STRUC LedCntl;
- u16 Led1; /* read from EEPROM 0x3c */
- u16 Led2; /* EEPROM 0x3e */
- u16 Led3; /* EEPROM 0x40 */
- u8 LedIndicatorStrength;
- u8 RssiSingalstrengthOffet;
- BOOLEAN bLedOnScanning;
- u8 LedStatus;
-
-/*****************************************************************************************/
-/* 802.11 related parameters */
-/*****************************************************************************************/
- /* outgoing BEACON frame buffer and corresponding TXD */
- struct rt_txwi BeaconTxWI;
- u8 *BeaconBuf;
- u16 BeaconOffset[HW_BEACON_MAX_COUNT];
-
- /* pre-build PS-POLL and NULL frame upon link up. for efficiency purpose. */
- struct rt_pspoll_frame PsPollFrame;
- struct rt_header_802_11 NullFrame;
-
-#ifdef RTMP_MAC_USB
- struct rt_tx_context BeaconContext[BEACON_RING_SIZE];
- struct rt_tx_context NullContext;
- struct rt_tx_context PsPollContext;
- struct rt_tx_context RTSContext;
-#endif /* RTMP_MAC_USB // */
-
-/*=========AP=========== */
-
-/*=======STA=========== */
- /* ----------------------------------------------- */
- /* STA specific configuration & operation status */
- /* used only when pAd->OpMode == OPMODE_STA */
- /* ----------------------------------------------- */
- struct rt_sta_admin_config StaCfg; /* user desired settings */
- struct rt_sta_active_config StaActive; /* valid only when ADHOC_ON(pAd) || INFRA_ON(pAd) */
- char nickname[IW_ESSID_MAX_SIZE + 1]; /* nickname, only used in the iwconfig i/f */
- int PreMediaState;
-
-/*=======Common=========== */
- /* OP mode: either AP or STA */
- u8 OpMode; /* OPMODE_STA, OPMODE_AP */
-
- int IndicateMediaState; /* Base on Indication state, default is NdisMediaStateDisConnected */
-
- /* MAT related parameters */
-
- /* configuration: read from Registry & E2PROM */
- BOOLEAN bLocalAdminMAC; /* Use user changed MAC */
- u8 PermanentAddress[MAC_ADDR_LEN]; /* Factory default MAC address */
- u8 CurrentAddress[MAC_ADDR_LEN]; /* User changed MAC address */
-
- /* ------------------------------------------------------ */
- /* common configuration to both OPMODE_STA and OPMODE_AP */
- /* ------------------------------------------------------ */
- struct rt_common_config CommonCfg;
- struct rt_mlme Mlme;
-
- /* AP needs those variables for site survey feature. */
- struct rt_mlme_aux MlmeAux; /* temporary settings used during MLME state machine */
- struct rt_bss_table ScanTab; /* store the latest SCAN result */
-
- /*About MacTab, the sta driver will use #0 and #1 for multicast and AP. */
- struct rt_mac_table MacTab; /* ASIC on-chip WCID entry table. At TX, ASIC always use key according to this on-chip table. */
- spinlock_t MacTabLock;
-
- struct rt_ba_table BATable;
-
- spinlock_t BATabLock;
- struct rt_ralink_timer RECBATimer;
-
- /* encryption/decryption KEY tables */
- struct rt_cipher_key SharedKey[MAX_MBSSID_NUM][4]; /* STA always use SharedKey[BSS0][0..3] */
-
- /* RX re-assembly buffer for fragmentation */
- struct rt_fragment_frame FragFrame; /* Frame storage for fragment frame */
-
- /* various Counters */
- struct rt_counter_802_3 Counters8023; /* 802.3 counters */
- struct rt_counter_802_11 WlanCounters; /* 802.11 MIB counters */
- struct rt_counter_ralink RalinkCounters; /* Ralink proprietary counters */
- struct rt_counter_drs DrsCounters; /* counters for Dynamic TX Rate Switching */
- struct rt_private PrivateInfo; /* Private information & counters */
-
- /* flags, see fRTMP_ADAPTER_xxx flags */
- unsigned long Flags; /* Represent current device status */
- unsigned long PSFlags; /* Power Save operation flag. */
-
- /* current TX sequence # */
- u16 Sequence;
-
- /* Control disconnect / connect event generation */
- /*+++Not used anymore */
- unsigned long LinkDownTime;
- /*--- */
- unsigned long LastRxRate;
- unsigned long LastTxRate;
- /*+++Used only for Station */
- BOOLEAN bConfigChanged; /* Config Change flag for the same SSID setting */
- /*--- */
-
- unsigned long ExtraInfo; /* Extra information for displaying status */
- unsigned long SystemErrorBitmap; /* b0: E2PROM version error */
-
- /*+++Not used anymore */
- unsigned long MacIcVersion; /* MAC/BBP serial interface issue solved after ver.D */
- /*--- */
-
- /* --------------------------- */
- /* System event log */
- /* --------------------------- */
- struct rt_802_11_event_table EventTab;
-
- BOOLEAN HTCEnable;
-
- /*****************************************************************************************/
- /* Statistic related parameters */
- /*****************************************************************************************/
-#ifdef RTMP_MAC_USB
- unsigned long BulkOutDataOneSecCount;
- unsigned long BulkInDataOneSecCount;
- unsigned long BulkLastOneSecCount; /* BulkOutDataOneSecCount + BulkInDataOneSecCount */
- unsigned long watchDogRxCnt;
- unsigned long watchDogRxOverFlowCnt;
- unsigned long watchDogTxPendingCnt[NUM_OF_TX_RING];
- int TransferedLength[NUM_OF_TX_RING];
-#endif /* RTMP_MAC_USB // */
-
- BOOLEAN bUpdateBcnCntDone;
- unsigned long watchDogMacDeadlock; /* prevent MAC/BBP into deadlock condition */
- /* ---------------------------- */
- /* DEBUG paramerts */
- /* ---------------------------- */
- /*unsigned long DebugSetting[4]; */
- BOOLEAN bBanAllBaSetup;
- BOOLEAN bPromiscuous;
-
- /* ---------------------------- */
- /* rt2860c emulation-use Parameters */
- /* ---------------------------- */
- /*unsigned long rtsaccu[30]; */
- /*unsigned long ctsaccu[30]; */
- /*unsigned long cfendaccu[30]; */
- /*unsigned long bacontent[16]; */
- /*unsigned long rxint[RX_RING_SIZE+1]; */
- /*u8 rcvba[60]; */
- BOOLEAN bLinkAdapt;
- BOOLEAN bForcePrintTX;
- BOOLEAN bForcePrintRX;
- /*BOOLEAN bDisablescanning; //defined in RT2870 USB */
- BOOLEAN bStaFifoTest;
- BOOLEAN bProtectionTest;
- BOOLEAN bBroadComHT;
- /*+++Following add from RT2870 USB. */
- unsigned long BulkOutReq;
- unsigned long BulkOutComplete;
- unsigned long BulkOutCompleteOther;
- unsigned long BulkOutCompleteCancel; /* seems not used now? */
- unsigned long BulkInReq;
- unsigned long BulkInComplete;
- unsigned long BulkInCompleteFail;
- /*--- */
-
- struct wificonf WIFItestbed;
-
- struct reordering_mpdu_pool mpdu_blk_pool;
-
- unsigned long OneSecondnonBEpackets; /* record non BE packets per second */
-
-#ifdef LINUX
- struct iw_statistics iw_stats;
-
- struct net_device_stats stats;
-#endif /* LINUX // */
-
- unsigned long TbttTickCount;
-#ifdef PCI_MSI_SUPPORT
- BOOLEAN HaveMsi;
-#endif /* PCI_MSI_SUPPORT // */
-
- u8 is_on;
-
-#define TIME_BASE (1000000/OS_HZ)
-#define TIME_ONE_SECOND (1000000/TIME_BASE)
- u8 flg_be_adjust;
- unsigned long be_adjust_last_time;
-
- u8 FlgCtsEnabled;
- u8 PM_FlgSuspend;
-
-#ifdef RT30xx
-#ifdef RTMP_EFUSE_SUPPORT
- BOOLEAN bUseEfuse;
- u8 EEPROMImage[1024];
-#endif /* RTMP_EFUSE_SUPPORT // */
-#endif /* RT30xx // */
-};
-
-#define DELAYINTMASK 0x0003fffb
-#define INTMASK 0x0003fffb
-#define IndMask 0x0003fffc
-#define RxINT 0x00000005 /* Delayed Rx or indivi rx */
-#define TxDataInt 0x000000fa /* Delayed Tx or indivi tx */
-#define TxMgmtInt 0x00000102 /* Delayed Tx or indivi tx */
-#define TxCoherent 0x00020000 /* tx coherent */
-#define RxCoherent 0x00010000 /* rx coherent */
-#define McuCommand 0x00000200 /* mcu */
-#define PreTBTTInt 0x00001000 /* Pre-TBTT interrupt */
-#define TBTTInt 0x00000800 /* TBTT interrupt */
-#define GPTimeOutInt 0x00008000 /* GPtimeout interrupt */
-#define AutoWakeupInt 0x00004000 /* AutoWakeupInt interrupt */
-#define FifoStaFullInt 0x00002000 /* fifo statistics full interrupt */
-
-/***************************************************************************
- * Rx Path software control block related data structures
- **************************************************************************/
-struct rt_rx_blk {
- RT28XX_RXD_STRUC RxD;
- struct rt_rxwi *pRxWI;
- struct rt_header_802_11 *pHeader;
- void *pRxPacket;
- u8 *pData;
- u16 DataSize;
- u16 Flags;
- u8 UserPriority; /* for calculate TKIP MIC using */
-};
-
-#define RX_BLK_SET_FLAG(_pRxBlk, _flag) (_pRxBlk->Flags |= _flag)
-#define RX_BLK_TEST_FLAG(_pRxBlk, _flag) (_pRxBlk->Flags & _flag)
-#define RX_BLK_CLEAR_FLAG(_pRxBlk, _flag) (_pRxBlk->Flags &= ~(_flag))
-
-#define fRX_WDS 0x0001
-#define fRX_AMSDU 0x0002
-#define fRX_ARALINK 0x0004
-#define fRX_HTC 0x0008
-#define fRX_PAD 0x0010
-#define fRX_AMPDU 0x0020
-#define fRX_QOS 0x0040
-#define fRX_INFRA 0x0080
-#define fRX_EAP 0x0100
-#define fRX_MESH 0x0200
-#define fRX_APCLI 0x0400
-#define fRX_DLS 0x0800
-#define fRX_WPI 0x1000
-
-#define LENGTH_AMSDU_SUBFRAMEHEAD 14
-#define LENGTH_ARALINK_SUBFRAMEHEAD 14
-#define LENGTH_ARALINK_HEADER_FIELD 2
-
-/***************************************************************************
- * Tx Path software control block related data structures
- **************************************************************************/
-#define TX_UNKOWN_FRAME 0x00
-#define TX_MCAST_FRAME 0x01
-#define TX_LEGACY_FRAME 0x02
-#define TX_AMPDU_FRAME 0x04
-#define TX_AMSDU_FRAME 0x08
-#define TX_RALINK_FRAME 0x10
-#define TX_FRAG_FRAME 0x20
-
-/* Currently the sizeof(struct rt_tx_blk) is 148 bytes. */
-struct rt_tx_blk {
- u8 QueIdx;
- u8 TxFrameType; /* Indicate the Transmission type of the all frames in one batch */
- u8 TotalFrameNum; /* Total frame number that wants to send-out in one batch */
- u16 TotalFragNum; /* Total frame fragments required in one batch */
- u16 TotalFrameLen; /* Total length of all frames that wants to send-out in one batch */
-
- struct rt_queue_header TxPacketList;
- struct rt_mac_table_entry *pMacEntry; /* NULL: packet with 802.11 RA field is multicast/broadcast address */
- HTTRANSMIT_SETTING *pTransmit;
-
- /* Following structure used for the characteristics of a specific packet. */
- void *pPacket;
- u8 *pSrcBufHeader; /* Reference to the head of sk_buff->data */
- u8 *pSrcBufData; /* Reference to the sk_buff->data, will change depending on the handling progresss */
- u32 SrcBufLen; /* Length of packet payload which not including Layer 2 header */
- u8 *pExtraLlcSnapEncap; /* NULL means no extra LLC/SNAP is required */
- u8 HeaderBuf[128]; /* TempBuffer for TX_INFO + TX_WI + 802.11 Header + padding + AMSDU SubHeader + LLC/SNAP */
- /*RT2870 2.1.0.0 uses only 80 bytes */
- /*RT3070 2.1.1.0 uses only 96 bytes */
- /*RT3090 2.1.0.0 uses only 96 bytes */
- u8 MpduHeaderLen; /* 802.11 header length NOT including the padding */
- u8 HdrPadLen; /* recording Header Padding Length; */
- u8 apidx; /* The interface associated to this packet */
- u8 Wcid; /* The MAC entry associated to this packet */
- u8 UserPriority; /* priority class of packet */
- u8 FrameGap; /* what kind of IFS does this packet use */
- u8 MpduReqNum; /* number of fragments of this frame */
- u8 TxRate; /* TODO: Obsoleted? Should change to MCS? */
- u8 CipherAlg; /* cipher alogrithm */
- struct rt_cipher_key *pKey;
-
- u16 Flags; /*See following definitions for detail. */
-
- /*YOU SHOULD NOT TOUCH IT! Following parameters are used for hardware-depended layer. */
- unsigned long Priv; /* Hardware specific value saved in here. */
-};
-
-#define fTX_bRtsRequired 0x0001 /* Indicate if need send RTS frame for protection. Not used in RT2860/RT2870. */
-#define fTX_bAckRequired 0x0002 /* the packet need ack response */
-#define fTX_bPiggyBack 0x0004 /* Legacy device use Piggback or not */
-#define fTX_bHTRate 0x0008 /* allow to use HT rate */
-#define fTX_bForceNonQoS 0x0010 /* force to transmit frame without WMM-QoS in HT mode */
-#define fTX_bAllowFrag 0x0020 /* allow to fragment the packet, A-MPDU, A-MSDU, A-Ralink is not allowed to fragment */
-#define fTX_bMoreData 0x0040 /* there are more data packets in PowerSave Queue */
-#define fTX_bWMM 0x0080 /* QOS Data */
-#define fTX_bClearEAPFrame 0x0100
-
-#define TX_BLK_SET_FLAG(_pTxBlk, _flag) (_pTxBlk->Flags |= _flag)
-#define TX_BLK_TEST_FLAG(_pTxBlk, _flag) (((_pTxBlk->Flags & _flag) == _flag) ? 1 : 0)
-#define TX_BLK_CLEAR_FLAG(_pTxBlk, _flag) (_pTxBlk->Flags &= ~(_flag))
-
-/***************************************************************************
- * Other static inline function definitions
- **************************************************************************/
-static inline void ConvertMulticastIP2MAC(u8 *pIpAddr,
- u8 **ppMacAddr,
- u16 ProtoType)
-{
- if (pIpAddr == NULL)
- return;
-
- if (ppMacAddr == NULL || *ppMacAddr == NULL)
- return;
-
- switch (ProtoType) {
- case ETH_P_IPV6:
-/* memset(*ppMacAddr, 0, ETH_LENGTH_OF_ADDRESS); */
- *(*ppMacAddr) = 0x33;
- *(*ppMacAddr + 1) = 0x33;
- *(*ppMacAddr + 2) = pIpAddr[12];
- *(*ppMacAddr + 3) = pIpAddr[13];
- *(*ppMacAddr + 4) = pIpAddr[14];
- *(*ppMacAddr + 5) = pIpAddr[15];
- break;
-
- case ETH_P_IP:
- default:
-/* memset(*ppMacAddr, 0, ETH_LENGTH_OF_ADDRESS); */
- *(*ppMacAddr) = 0x01;
- *(*ppMacAddr + 1) = 0x00;
- *(*ppMacAddr + 2) = 0x5e;
- *(*ppMacAddr + 3) = pIpAddr[1] & 0x7f;
- *(*ppMacAddr + 4) = pIpAddr[2];
- *(*ppMacAddr + 5) = pIpAddr[3];
- break;
- }
-
- return;
-}
-
-char *GetPhyMode(int Mode);
-char *GetBW(int BW);
-
-/* */
-/* Private routines in rtmp_init.c */
-/* */
-int RTMPAllocAdapterBlock(void *handle,
- struct rt_rtmp_adapter **ppAdapter);
-
-int RTMPAllocTxRxRingMemory(struct rt_rtmp_adapter *pAd);
-
-void RTMPFreeAdapter(struct rt_rtmp_adapter *pAd);
-
-int NICReadRegParameters(struct rt_rtmp_adapter *pAd,
- void *WrapperConfigurationContext);
-
-#ifdef RTMP_RF_RW_SUPPORT
-void NICInitRFRegisters(struct rt_rtmp_adapter *pAd);
-
-void RtmpChipOpsRFHook(struct rt_rtmp_adapter *pAd);
-
-int RT30xxWriteRFRegister(struct rt_rtmp_adapter *pAd,
- u8 regID, u8 value);
-
-int RT30xxReadRFRegister(struct rt_rtmp_adapter *pAd,
- u8 regID, u8 *pValue);
-#endif /* RTMP_RF_RW_SUPPORT // */
-
-void NICReadEEPROMParameters(struct rt_rtmp_adapter *pAd, u8 *mac_addr);
-
-void NICInitAsicFromEEPROM(struct rt_rtmp_adapter *pAd);
-
-int NICInitializeAdapter(struct rt_rtmp_adapter *pAd, IN BOOLEAN bHardReset);
-
-int NICInitializeAsic(struct rt_rtmp_adapter *pAd, IN BOOLEAN bHardReset);
-
-void NICIssueReset(struct rt_rtmp_adapter *pAd);
-
-void RTMPRingCleanUp(struct rt_rtmp_adapter *pAd, u8 RingType);
-
-void UserCfgInit(struct rt_rtmp_adapter *pAd);
-
-void NICResetFromError(struct rt_rtmp_adapter *pAd);
-
-int NICLoadFirmware(struct rt_rtmp_adapter *pAd);
-
-void NICEraseFirmware(struct rt_rtmp_adapter *pAd);
-
-int NICLoadRateSwitchingParams(struct rt_rtmp_adapter *pAd);
-
-BOOLEAN NICCheckForHang(struct rt_rtmp_adapter *pAd);
-
-void NICUpdateFifoStaCounters(struct rt_rtmp_adapter *pAd);
-
-void NICUpdateRawCounters(struct rt_rtmp_adapter *pAd);
-
-void RTMPZeroMemory(void *pSrc, unsigned long Length);
-
-unsigned long RTMPCompareMemory(void *pSrc1, void *pSrc2, unsigned long Length);
-
-void RTMPMoveMemory(void *pDest, void *pSrc, unsigned long Length);
-
-void AtoH(char *src, u8 *dest, int destlen);
-
-void RTMPPatchMacBbpBug(struct rt_rtmp_adapter *pAd);
-
-void RTMPInitTimer(struct rt_rtmp_adapter *pAd,
- struct rt_ralink_timer *pTimer,
- void *pTimerFunc, void *pData, IN BOOLEAN Repeat);
-
-void RTMPSetTimer(struct rt_ralink_timer *pTimer, unsigned long Value);
-
-void RTMPModTimer(struct rt_ralink_timer *pTimer, unsigned long Value);
-
-void RTMPCancelTimer(struct rt_ralink_timer *pTimer, OUT BOOLEAN * pCancelled);
-
-void RTMPSetLED(struct rt_rtmp_adapter *pAd, u8 Status);
-
-void RTMPSetSignalLED(struct rt_rtmp_adapter *pAd, IN NDIS_802_11_RSSI Dbm);
-
-void RTMPEnableRxTx(struct rt_rtmp_adapter *pAd);
-
-/* */
-/* prototype in action.c */
-/* */
-void ActionStateMachineInit(struct rt_rtmp_adapter *pAd,
- struct rt_state_machine *S,
- OUT STATE_MACHINE_FUNC Trans[]);
-
-void MlmeADDBAAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem);
-
-void MlmeDELBAAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem);
-
-void MlmeDLSAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem);
-
-void MlmeInvalidAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem);
-
-void MlmeQOSAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem);
-
-void PeerAddBAReqAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem);
-
-void PeerAddBARspAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem);
-
-void PeerDelBAAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem);
-
-void PeerBAAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem);
-
-void SendPSMPAction(struct rt_rtmp_adapter *pAd, u8 Wcid, u8 Psmp);
-
-void PeerRMAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem);
-
-void PeerPublicAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem);
-
-void PeerHTAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem);
-
-void PeerQOSAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem);
-
-void RECBATimerTimeout(void *SystemSpecific1,
- void *FunctionContext,
- void *SystemSpecific2, void *SystemSpecific3);
-
-void ORIBATimerTimeout(struct rt_rtmp_adapter *pAd);
-
-void SendRefreshBAR(struct rt_rtmp_adapter *pAd, struct rt_mac_table_entry *pEntry);
-
-void ActHeaderInit(struct rt_rtmp_adapter *pAd,
- struct rt_header_802_11 *pHdr80211,
- u8 *Addr1, u8 *Addr2, u8 *Addr3);
-
-void BarHeaderInit(struct rt_rtmp_adapter *pAd,
- struct rt_frame_bar *pCntlBar, u8 *pDA, u8 *pSA);
-
-void InsertActField(struct rt_rtmp_adapter *pAd,
- u8 *pFrameBuf,
- unsigned long *pFrameLen, u8 Category, u8 ActCode);
-
-BOOLEAN CntlEnqueueForRecv(struct rt_rtmp_adapter *pAd,
- unsigned long Wcid,
- unsigned long MsgLen, struct rt_frame_ba_req *pMsg);
-
-/* */
-/* Private routines in rtmp_data.c */
-/* */
-BOOLEAN RTMPHandleRxDoneInterrupt(struct rt_rtmp_adapter *pAd);
-
-BOOLEAN RTMPHandleTxRingDmaDoneInterrupt(struct rt_rtmp_adapter *pAd,
- INT_SOURCE_CSR_STRUC TxRingBitmap);
-
-void RTMPHandleMgmtRingDmaDoneInterrupt(struct rt_rtmp_adapter *pAd);
-
-void RTMPHandleTBTTInterrupt(struct rt_rtmp_adapter *pAd);
-
-void RTMPHandlePreTBTTInterrupt(struct rt_rtmp_adapter *pAd);
-
-void RTMPHandleTwakeupInterrupt(struct rt_rtmp_adapter *pAd);
-
-void RTMPHandleRxCoherentInterrupt(struct rt_rtmp_adapter *pAd);
-
-BOOLEAN TxFrameIsAggregatible(struct rt_rtmp_adapter *pAd,
- u8 *pPrevAddr1, u8 *p8023hdr);
-
-BOOLEAN PeerIsAggreOn(struct rt_rtmp_adapter *pAd,
- unsigned long TxRate, struct rt_mac_table_entry *pMacEntry);
-
-int Sniff2BytesFromNdisBuffer(char *pFirstBuffer,
- u8 DesiredOffset,
- u8 *pByte0, u8 *pByte1);
-
-int STASendPacket(struct rt_rtmp_adapter *pAd, void *pPacket);
-
-void STASendPackets(void *MiniportAdapterContext,
- void **ppPacketArray, u32 NumberOfPackets);
-
-void RTMPDeQueuePacket(struct rt_rtmp_adapter *pAd,
- IN BOOLEAN bIntContext,
- u8 QueIdx, u8 Max_Tx_Packets);
-
-int RTMPHardTransmit(struct rt_rtmp_adapter *pAd,
- void *pPacket,
- u8 QueIdx, unsigned long *pFreeTXDLeft);
-
-int STAHardTransmit(struct rt_rtmp_adapter *pAd,
- struct rt_tx_blk *pTxBlk, u8 QueIdx);
-
-void STARxEAPOLFrameIndicate(struct rt_rtmp_adapter *pAd,
- struct rt_mac_table_entry *pEntry,
- struct rt_rx_blk *pRxBlk, u8 FromWhichBSSID);
-
-int RTMPFreeTXDRequest(struct rt_rtmp_adapter *pAd,
- u8 RingType,
- u8 NumberRequired, u8 *FreeNumberIs);
-
-int MlmeHardTransmit(struct rt_rtmp_adapter *pAd,
- u8 QueIdx, void *pPacket);
-
-int MlmeHardTransmitMgmtRing(struct rt_rtmp_adapter *pAd,
- u8 QueIdx, void *pPacket);
-
-#ifdef RTMP_MAC_PCI
-int MlmeHardTransmitTxRing(struct rt_rtmp_adapter *pAd,
- u8 QueIdx, void *pPacket);
-
-int MlmeDataHardTransmit(struct rt_rtmp_adapter *pAd,
- u8 QueIdx, void *pPacket);
-
-void RTMPWriteTxDescriptor(struct rt_rtmp_adapter *pAd,
- struct rt_txd *pTxD, IN BOOLEAN bWIV, u8 QSEL);
-#endif /* RTMP_MAC_PCI // */
-
-u16 RTMPCalcDuration(struct rt_rtmp_adapter *pAd, u8 Rate, unsigned long Size);
-
-void RTMPWriteTxWI(struct rt_rtmp_adapter *pAd, struct rt_txwi * pTxWI, IN BOOLEAN FRAG, IN BOOLEAN CFACK, IN BOOLEAN InsTimestamp, IN BOOLEAN AMPDU, IN BOOLEAN Ack, IN BOOLEAN NSeq, /* HW new a sequence. */
- u8 BASize,
- u8 WCID,
- unsigned long Length,
- u8 PID,
- u8 TID,
- u8 TxRate,
- u8 Txopmode,
- IN BOOLEAN CfAck, IN HTTRANSMIT_SETTING *pTransmit);
-
-void RTMPWriteTxWI_Data(struct rt_rtmp_adapter *pAd,
- struct rt_txwi *pTxWI, struct rt_tx_blk *pTxBlk);
-
-void RTMPWriteTxWI_Cache(struct rt_rtmp_adapter *pAd,
- struct rt_txwi *pTxWI, struct rt_tx_blk *pTxBlk);
-
-void RTMPSuspendMsduTransmission(struct rt_rtmp_adapter *pAd);
-
-void RTMPResumeMsduTransmission(struct rt_rtmp_adapter *pAd);
-
-int MiniportMMRequest(struct rt_rtmp_adapter *pAd,
- u8 QueIdx, u8 *pData, u32 Length);
-
-/*+++mark by shiang, now this function merge to MiniportMMRequest() */
-/*---mark by shiang, now this function merge to MiniportMMRequest() */
-
-void RTMPSendNullFrame(struct rt_rtmp_adapter *pAd,
- u8 TxRate, IN BOOLEAN bQosNull);
-
-void RTMPSendDisassociationFrame(struct rt_rtmp_adapter *pAd);
-
-void RTMPSendRTSFrame(struct rt_rtmp_adapter *pAd,
- u8 *pDA,
- IN unsigned int NextMpduSize,
- u8 TxRate,
- u8 RTSRate,
- u16 AckDuration,
- u8 QueIdx, u8 FrameGap);
-
-struct rt_queue_header *RTMPCheckTxSwQueue(struct rt_rtmp_adapter *pAd, u8 * QueIdx);
-
-void RTMPReportMicError(struct rt_rtmp_adapter *pAd, struct rt_cipher_key *pWpaKey);
-
-void WpaMicFailureReportFrame(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem);
-
-void WpaDisassocApAndBlockAssoc(void *SystemSpecific1,
- void *FunctionContext,
- void *SystemSpecific2,
- void *SystemSpecific3);
-
-void WpaStaPairwiseKeySetting(struct rt_rtmp_adapter *pAd);
-
-void WpaStaGroupKeySetting(struct rt_rtmp_adapter *pAd);
-
-int RTMPCloneNdisPacket(struct rt_rtmp_adapter *pAd,
- IN BOOLEAN pInsAMSDUHdr,
- void *pInPacket,
- void **ppOutPacket);
-
-int RTMPAllocateNdisPacket(struct rt_rtmp_adapter *pAd,
- void **pPacket,
- u8 *pHeader,
- u32 HeaderLen,
- u8 *pData, u32 DataLen);
-
-void RTMPFreeNdisPacket(struct rt_rtmp_adapter *pAd, void *pPacket);
-
-BOOLEAN RTMPFreeTXDUponTxDmaDone(struct rt_rtmp_adapter *pAd, u8 QueIdx);
-
-BOOLEAN RTMPCheckDHCPFrame(struct rt_rtmp_adapter *pAd, void *pPacket);
-
-BOOLEAN RTMPCheckEtherType(struct rt_rtmp_adapter *pAd, void *pPacket);
-
-/* */
-/* Private routines in rtmp_wep.c */
-/* */
-void RTMPInitWepEngine(struct rt_rtmp_adapter *pAd,
- u8 *pKey,
- u8 KeyId, u8 KeyLen, u8 *pDest);
-
-void RTMPEncryptData(struct rt_rtmp_adapter *pAd,
- u8 *pSrc, u8 *pDest, u32 Len);
-
-BOOLEAN RTMPSoftDecryptWEP(struct rt_rtmp_adapter *pAd,
- u8 *pData,
- unsigned long DataByteCnt, struct rt_cipher_key *pGroupKey);
-
-void RTMPSetICV(struct rt_rtmp_adapter *pAd, u8 *pDest);
-
-void ARCFOUR_INIT(struct rt_arcfourcontext *Ctx, u8 *pKey, u32 KeyLen);
-
-u8 ARCFOUR_BYTE(struct rt_arcfourcontext *Ctx);
-
-void ARCFOUR_DECRYPT(struct rt_arcfourcontext *Ctx,
- u8 *pDest, u8 *pSrc, u32 Len);
-
-void ARCFOUR_ENCRYPT(struct rt_arcfourcontext *Ctx,
- u8 *pDest, u8 *pSrc, u32 Len);
-
-void WPAARCFOUR_ENCRYPT(struct rt_arcfourcontext *Ctx,
- u8 *pDest, u8 *pSrc, u32 Len);
-
-u32 RTMP_CALC_FCS32(u32 Fcs, u8 *Cp, int Len);
-
-/* */
-/* MLME routines */
-/* */
-
-/* Asic/RF/BBP related functions */
-
-void AsicAdjustTxPower(struct rt_rtmp_adapter *pAd);
-
-void AsicUpdateProtect(struct rt_rtmp_adapter *pAd,
- u16 OperaionMode,
- u8 SetMask,
- IN BOOLEAN bDisableBGProtect, IN BOOLEAN bNonGFExist);
-
-void AsicSwitchChannel(struct rt_rtmp_adapter *pAd,
- u8 Channel, IN BOOLEAN bScan);
-
-void AsicLockChannel(struct rt_rtmp_adapter *pAd, u8 Channel);
-
-void AsicRfTuningExec(void *SystemSpecific1,
- void *FunctionContext,
- void *SystemSpecific2, void *SystemSpecific3);
-
-void AsicResetBBPAgent(struct rt_rtmp_adapter *pAd);
-
-void AsicSleepThenAutoWakeup(struct rt_rtmp_adapter *pAd,
- u16 TbttNumToNextWakeUp);
-
-void AsicForceSleep(struct rt_rtmp_adapter *pAd);
-
-void AsicForceWakeup(struct rt_rtmp_adapter *pAd, IN BOOLEAN bFromTx);
-
-void AsicSetBssid(struct rt_rtmp_adapter *pAd, u8 *pBssid);
-
-void AsicSetMcastWC(struct rt_rtmp_adapter *pAd);
-
-void AsicDelWcidTab(struct rt_rtmp_adapter *pAd, u8 Wcid);
-
-void AsicEnableRDG(struct rt_rtmp_adapter *pAd);
-
-void AsicDisableRDG(struct rt_rtmp_adapter *pAd);
-
-void AsicDisableSync(struct rt_rtmp_adapter *pAd);
-
-void AsicEnableBssSync(struct rt_rtmp_adapter *pAd);
-
-void AsicEnableIbssSync(struct rt_rtmp_adapter *pAd);
-
-void AsicSetEdcaParm(struct rt_rtmp_adapter *pAd, struct rt_edca_parm *pEdcaParm);
-
-void AsicSetSlotTime(struct rt_rtmp_adapter *pAd, IN BOOLEAN bUseShortSlotTime);
-
-void AsicAddSharedKeyEntry(struct rt_rtmp_adapter *pAd,
- u8 BssIndex,
- u8 KeyIdx,
- u8 CipherAlg,
- u8 *pKey, u8 *pTxMic, u8 *pRxMic);
-
-void AsicRemoveSharedKeyEntry(struct rt_rtmp_adapter *pAd,
- u8 BssIndex, u8 KeyIdx);
-
-void AsicUpdateWCIDAttribute(struct rt_rtmp_adapter *pAd,
- u16 WCID,
- u8 BssIndex,
- u8 CipherAlg,
- IN BOOLEAN bUsePairewiseKeyTable);
-
-void AsicUpdateWCIDIVEIV(struct rt_rtmp_adapter *pAd,
- u16 WCID, unsigned long uIV, unsigned long uEIV);
-
-void AsicUpdateRxWCIDTable(struct rt_rtmp_adapter *pAd,
- u16 WCID, u8 *pAddr);
-
-void AsicAddKeyEntry(struct rt_rtmp_adapter *pAd,
- u16 WCID,
- u8 BssIndex,
- u8 KeyIdx,
- struct rt_cipher_key *pCipherKey,
- IN BOOLEAN bUsePairewiseKeyTable, IN BOOLEAN bTxKey);
-
-void AsicAddPairwiseKeyEntry(struct rt_rtmp_adapter *pAd,
- u8 *pAddr,
- u8 WCID, struct rt_cipher_key *pCipherKey);
-
-void AsicRemovePairwiseKeyEntry(struct rt_rtmp_adapter *pAd,
- u8 BssIdx, u8 Wcid);
-
-BOOLEAN AsicSendCommandToMcu(struct rt_rtmp_adapter *pAd,
- u8 Command,
- u8 Token, u8 Arg0, u8 Arg1);
-
-#ifdef RTMP_MAC_PCI
-BOOLEAN AsicCheckCommanOk(struct rt_rtmp_adapter *pAd, u8 Command);
-#endif /* RTMP_MAC_PCI // */
-
-void MacAddrRandomBssid(struct rt_rtmp_adapter *pAd, u8 *pAddr);
-
-void MgtMacHeaderInit(struct rt_rtmp_adapter *pAd,
- struct rt_header_802_11 *pHdr80211,
- u8 SubType,
- u8 ToDs, u8 *pDA, u8 *pBssid);
-
-void MlmeRadioOff(struct rt_rtmp_adapter *pAd);
-
-void MlmeRadioOn(struct rt_rtmp_adapter *pAd);
-
-void BssTableInit(struct rt_bss_table *Tab);
-
-void BATableInit(struct rt_rtmp_adapter *pAd, struct rt_ba_table *Tab);
-
-unsigned long BssTableSearch(struct rt_bss_table *Tab, u8 *pBssid, u8 Channel);
-
-unsigned long BssSsidTableSearch(struct rt_bss_table *Tab,
- u8 *pBssid,
- u8 *pSsid, u8 SsidLen, u8 Channel);
-
-unsigned long BssTableSearchWithSSID(struct rt_bss_table *Tab,
- u8 *Bssid,
- u8 *pSsid,
- u8 SsidLen, u8 Channel);
-
-unsigned long BssSsidTableSearchBySSID(struct rt_bss_table *Tab,
- u8 *pSsid, u8 SsidLen);
-
-void BssTableDeleteEntry(struct rt_bss_table *pTab,
- u8 *pBssid, u8 Channel);
-
-void BATableDeleteORIEntry(struct rt_rtmp_adapter *pAd,
- struct rt_ba_ori_entry *pBAORIEntry);
-
-void BssEntrySet(struct rt_rtmp_adapter *pAd, struct rt_bss_entry *pBss, u8 *pBssid, char Ssid[], u8 SsidLen, u8 BssType, u16 BeaconPeriod, struct rt_cf_parm * CfParm, u16 AtimWin, u16 CapabilityInfo, u8 SupRate[], u8 SupRateLen, u8 ExtRate[], u8 ExtRateLen, struct rt_ht_capability_ie * pHtCapability, struct rt_add_ht_info_ie * pAddHtInfo, /* AP might use this additional ht info IE */
- u8 HtCapabilityLen,
- u8 AddHtInfoLen,
- u8 NewExtChanOffset,
- u8 Channel,
- char Rssi,
- IN LARGE_INTEGER TimeStamp,
- u8 CkipFlag,
- struct rt_edca_parm *pEdcaParm,
- struct rt_qos_capability_parm *pQosCapability,
- struct rt_qbss_load_parm *pQbssLoad,
- u16 LengthVIE, struct rt_ndis_802_11_variable_ies *pVIE);
-
-unsigned long BssTableSetEntry(struct rt_rtmp_adapter *pAd, struct rt_bss_table *pTab, u8 *pBssid, char Ssid[], u8 SsidLen, u8 BssType, u16 BeaconPeriod, struct rt_cf_parm * CfParm, u16 AtimWin, u16 CapabilityInfo, u8 SupRate[], u8 SupRateLen, u8 ExtRate[], u8 ExtRateLen, struct rt_ht_capability_ie * pHtCapability, struct rt_add_ht_info_ie * pAddHtInfo, /* AP might use this additional ht info IE */
- u8 HtCapabilityLen,
- u8 AddHtInfoLen,
- u8 NewExtChanOffset,
- u8 Channel,
- char Rssi,
- IN LARGE_INTEGER TimeStamp,
- u8 CkipFlag,
- struct rt_edca_parm *pEdcaParm,
- struct rt_qos_capability_parm *pQosCapability,
- struct rt_qbss_load_parm *pQbssLoad,
- u16 LengthVIE, struct rt_ndis_802_11_variable_ies *pVIE);
-
-void BATableInsertEntry(struct rt_rtmp_adapter *pAd,
- u16 Aid,
- u16 TimeOutValue,
- u16 StartingSeq,
- u8 TID,
- u8 BAWinSize,
- u8 OriginatorStatus, IN BOOLEAN IsRecipient);
-
-void BssTableSsidSort(struct rt_rtmp_adapter *pAd,
- struct rt_bss_table *OutTab, char Ssid[], u8 SsidLen);
-
-void BssTableSortByRssi(struct rt_bss_table *OutTab);
-
-void BssCipherParse(struct rt_bss_entry *pBss);
-
-int MlmeQueueInit(struct rt_mlme_queue *Queue);
-
-void MlmeQueueDestroy(struct rt_mlme_queue *Queue);
-
-BOOLEAN MlmeEnqueue(struct rt_rtmp_adapter *pAd,
- unsigned long Machine,
- unsigned long MsgType, unsigned long MsgLen, void *Msg);
-
-BOOLEAN MlmeEnqueueForRecv(struct rt_rtmp_adapter *pAd,
- unsigned long Wcid,
- unsigned long TimeStampHigh,
- unsigned long TimeStampLow,
- u8 Rssi0,
- u8 Rssi1,
- u8 Rssi2,
- unsigned long MsgLen, void *Msg, u8 Signal);
-
-BOOLEAN MlmeDequeue(struct rt_mlme_queue *Queue, struct rt_mlme_queue_elem **Elem);
-
-void MlmeRestartStateMachine(struct rt_rtmp_adapter *pAd);
-
-BOOLEAN MlmeQueueEmpty(struct rt_mlme_queue *Queue);
-
-BOOLEAN MlmeQueueFull(struct rt_mlme_queue *Queue);
-
-BOOLEAN MsgTypeSubst(struct rt_rtmp_adapter *pAd,
- struct rt_frame_802_11 *pFrame,
- int *Machine, int *MsgType);
-
-void StateMachineInit(struct rt_state_machine *Sm,
- IN STATE_MACHINE_FUNC Trans[],
- unsigned long StNr,
- unsigned long MsgNr,
- IN STATE_MACHINE_FUNC DefFunc,
- unsigned long InitState, unsigned long Base);
-
-void StateMachineSetAction(struct rt_state_machine *S,
- unsigned long St, unsigned long Msg, IN STATE_MACHINE_FUNC F);
-
-void StateMachinePerformAction(struct rt_rtmp_adapter *pAd,
- struct rt_state_machine *S, struct rt_mlme_queue_elem *Elem);
-
-void Drop(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem);
-
-void AssocStateMachineInit(struct rt_rtmp_adapter *pAd,
- struct rt_state_machine *Sm,
- OUT STATE_MACHINE_FUNC Trans[]);
-
-void ReassocTimeout(void *SystemSpecific1,
- void *FunctionContext,
- void *SystemSpecific2, void *SystemSpecific3);
-
-void AssocTimeout(void *SystemSpecific1,
- void *FunctionContext,
- void *SystemSpecific2, void *SystemSpecific3);
-
-void DisassocTimeout(void *SystemSpecific1,
- void *FunctionContext,
- void *SystemSpecific2, void *SystemSpecific3);
-
-/*---------------------------------------------- */
-void MlmeAssocReqAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem);
-
-void MlmeReassocReqAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem);
-
-void MlmeDisassocReqAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem);
-
-void PeerAssocRspAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem);
-
-void PeerReassocRspAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem);
-
-void PeerDisassocAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem);
-
-void DisassocTimeoutAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem);
-
-void AssocTimeoutAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem);
-
-void ReassocTimeoutAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem);
-
-void Cls3errAction(struct rt_rtmp_adapter *pAd, u8 *pAddr);
-
-void InvalidStateWhenAssoc(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem);
-
-void InvalidStateWhenReassoc(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem);
-
-void InvalidStateWhenDisassociate(struct rt_rtmp_adapter *pAd,
- struct rt_mlme_queue_elem *Elem);
-
-#ifdef RTMP_MAC_USB
-void MlmeCntlConfirm(struct rt_rtmp_adapter *pAd, unsigned long MsgType, u16 Msg);
-#endif /* RTMP_MAC_USB // */
-
-void ComposePsPoll(struct rt_rtmp_adapter *pAd);
-
-void ComposeNullFrame(struct rt_rtmp_adapter *pAd);
-
-void AssocPostProc(struct rt_rtmp_adapter *pAd,
- u8 *pAddr2,
- u16 CapabilityInfo,
- u16 Aid,
- u8 SupRate[],
- u8 SupRateLen,
- u8 ExtRate[],
- u8 ExtRateLen,
- struct rt_edca_parm *pEdcaParm,
- struct rt_ht_capability_ie *pHtCapability,
- u8 HtCapabilityLen, struct rt_add_ht_info_ie *pAddHtInfo);
-
-void AuthStateMachineInit(struct rt_rtmp_adapter *pAd,
- struct rt_state_machine *sm, OUT STATE_MACHINE_FUNC Trans[]);
-
-void AuthTimeout(void *SystemSpecific1,
- void *FunctionContext,
- void *SystemSpecific2, void *SystemSpecific3);
-
-void MlmeAuthReqAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem);
-
-void PeerAuthRspAtSeq2Action(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem);
-
-void PeerAuthRspAtSeq4Action(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem);
-
-void AuthTimeoutAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem);
-
-void Cls2errAction(struct rt_rtmp_adapter *pAd, u8 *pAddr);
-
-void MlmeDeauthReqAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem);
-
-void InvalidStateWhenAuth(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem);
-
-/*============================================= */
-
-void AuthRspStateMachineInit(struct rt_rtmp_adapter *pAd,
- struct rt_state_machine *Sm,
- IN STATE_MACHINE_FUNC Trans[]);
-
-void PeerDeauthAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem);
-
-void PeerAuthSimpleRspGenAndSend(struct rt_rtmp_adapter *pAd,
- struct rt_header_802_11 *pHdr80211,
- u16 Alg,
- u16 Seq,
- u16 Reason, u16 Status);
-
-/* */
-/* Private routines in dls.c */
-/* */
-
-/*======================================== */
-
-void SyncStateMachineInit(struct rt_rtmp_adapter *pAd,
- struct rt_state_machine *Sm,
- OUT STATE_MACHINE_FUNC Trans[]);
-
-void BeaconTimeout(void *SystemSpecific1,
- void *FunctionContext,
- void *SystemSpecific2, void *SystemSpecific3);
-
-void ScanTimeout(void *SystemSpecific1,
- void *FunctionContext,
- void *SystemSpecific2, void *SystemSpecific3);
-
-void InvalidStateWhenScan(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem);
-
-void InvalidStateWhenJoin(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem);
-
-void InvalidStateWhenStart(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem);
-
-void EnqueueProbeRequest(struct rt_rtmp_adapter *pAd);
-
-BOOLEAN ScanRunning(struct rt_rtmp_adapter *pAd);
-/*========================================= */
-
-void MlmeCntlInit(struct rt_rtmp_adapter *pAd,
- struct rt_state_machine *S, OUT STATE_MACHINE_FUNC Trans[]);
-
-void MlmeCntlMachinePerformAction(struct rt_rtmp_adapter *pAd,
- struct rt_state_machine *S,
- struct rt_mlme_queue_elem *Elem);
-
-void CntlIdleProc(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem);
-
-void CntlOidScanProc(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem);
-
-void CntlOidSsidProc(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem);
-
-void CntlOidRTBssidProc(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem);
-
-void CntlMlmeRoamingProc(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem);
-
-void CntlWaitDisassocProc(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem);
-
-void CntlWaitJoinProc(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem);
-
-void CntlWaitReassocProc(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem);
-
-void CntlWaitStartProc(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem);
-
-void CntlWaitAuthProc(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem);
-
-void CntlWaitAuthProc2(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem);
-
-void CntlWaitAssocProc(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem);
-
-void LinkUp(struct rt_rtmp_adapter *pAd, u8 BssType);
-
-void LinkDown(struct rt_rtmp_adapter *pAd, IN BOOLEAN IsReqFromAP);
-
-void IterateOnBssTab(struct rt_rtmp_adapter *pAd);
-
-void IterateOnBssTab2(struct rt_rtmp_adapter *pAd);
-
-void JoinParmFill(struct rt_rtmp_adapter *pAd,
- struct rt_mlme_join_req *JoinReq, unsigned long BssIdx);
-
-void AssocParmFill(struct rt_rtmp_adapter *pAd,
- struct rt_mlme_assoc_req *AssocReq,
- u8 *pAddr,
- u16 CapabilityInfo,
- unsigned long Timeout, u16 ListenIntv);
-
-void ScanParmFill(struct rt_rtmp_adapter *pAd,
- struct rt_mlme_scan_req *ScanReq,
- char Ssid[],
- u8 SsidLen, u8 BssType, u8 ScanType);
-
-void DisassocParmFill(struct rt_rtmp_adapter *pAd,
- struct rt_mlme_disassoc_req *DisassocReq,
- u8 *pAddr, u16 Reason);
-
-void StartParmFill(struct rt_rtmp_adapter *pAd,
- struct rt_mlme_start_req *StartReq,
- char Ssid[], u8 SsidLen);
-
-void AuthParmFill(struct rt_rtmp_adapter *pAd,
- struct rt_mlme_auth_req *AuthReq,
- u8 *pAddr, u16 Alg);
-
-void EnqueuePsPoll(struct rt_rtmp_adapter *pAd);
-
-void EnqueueBeaconFrame(struct rt_rtmp_adapter *pAd);
-
-void MlmeJoinReqAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem);
-
-void MlmeScanReqAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem);
-
-void MlmeStartReqAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem);
-
-void ScanTimeoutAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem);
-
-void BeaconTimeoutAtJoinAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem);
-
-void PeerBeaconAtScanAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem);
-
-void PeerBeaconAtJoinAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem);
-
-void PeerBeacon(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem);
-
-void PeerProbeReqAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem);
-
-void ScanNextChannel(struct rt_rtmp_adapter *pAd);
-
-unsigned long MakeIbssBeacon(struct rt_rtmp_adapter *pAd);
-
-BOOLEAN MlmeScanReqSanity(struct rt_rtmp_adapter *pAd,
- void *Msg,
- unsigned long MsgLen,
- u8 *BssType,
- char ssid[],
- u8 *SsidLen, u8 *ScanType);
-
-BOOLEAN PeerBeaconAndProbeRspSanity(struct rt_rtmp_adapter *pAd,
- void *Msg,
- unsigned long MsgLen,
- u8 MsgChannel,
- u8 *pAddr2,
- u8 *pBssid,
- char Ssid[],
- u8 *pSsidLen,
- u8 *pBssType,
- u16 *pBeaconPeriod,
- u8 *pChannel,
- u8 *pNewChannel,
- OUT LARGE_INTEGER *pTimestamp,
- struct rt_cf_parm *pCfParm,
- u16 *pAtimWin,
- u16 *pCapabilityInfo,
- u8 *pErp,
- u8 *pDtimCount,
- u8 *pDtimPeriod,
- u8 *pBcastFlag,
- u8 *pMessageToMe,
- u8 SupRate[],
- u8 *pSupRateLen,
- u8 ExtRate[],
- u8 *pExtRateLen,
- u8 *pCkipFlag,
- u8 *pAironetCellPowerLimit,
- struct rt_edca_parm *pEdcaParm,
- struct rt_qbss_load_parm *pQbssLoad,
- struct rt_qos_capability_parm *pQosCapability,
- unsigned long *pRalinkIe,
- u8 *pHtCapabilityLen,
- u8 *pPreNHtCapabilityLen,
- struct rt_ht_capability_ie *pHtCapability,
- u8 *AddHtInfoLen,
- struct rt_add_ht_info_ie *AddHtInfo,
- u8 *NewExtChannel,
- u16 *LengthVIE,
- struct rt_ndis_802_11_variable_ies *pVIE);
-
-BOOLEAN PeerAddBAReqActionSanity(struct rt_rtmp_adapter *pAd,
- void *pMsg,
- unsigned long MsgLen, u8 *pAddr2);
-
-BOOLEAN PeerAddBARspActionSanity(struct rt_rtmp_adapter *pAd,
- void *pMsg, unsigned long MsgLen);
-
-BOOLEAN PeerDelBAActionSanity(struct rt_rtmp_adapter *pAd,
- u8 Wcid, void *pMsg, unsigned long MsgLen);
-
-BOOLEAN MlmeAssocReqSanity(struct rt_rtmp_adapter *pAd,
- void *Msg,
- unsigned long MsgLen,
- u8 *pApAddr,
- u16 *CapabilityInfo,
- unsigned long *Timeout, u16 *ListenIntv);
-
-BOOLEAN MlmeAuthReqSanity(struct rt_rtmp_adapter *pAd,
- void *Msg,
- unsigned long MsgLen,
- u8 *pAddr,
- unsigned long *Timeout, u16 *Alg);
-
-BOOLEAN MlmeStartReqSanity(struct rt_rtmp_adapter *pAd,
- void *Msg,
- unsigned long MsgLen,
- char Ssid[], u8 *Ssidlen);
-
-BOOLEAN PeerAuthSanity(struct rt_rtmp_adapter *pAd,
- void *Msg,
- unsigned long MsgLen,
- u8 *pAddr,
- u16 *Alg,
- u16 *Seq,
- u16 *Status, char ChlgText[]);
-
-BOOLEAN PeerAssocRspSanity(struct rt_rtmp_adapter *pAd, void *pMsg, unsigned long MsgLen, u8 *pAddr2, u16 *pCapabilityInfo, u16 *pStatus, u16 *pAid, u8 SupRate[], u8 *pSupRateLen, u8 ExtRate[], u8 *pExtRateLen, struct rt_ht_capability_ie *pHtCapability, struct rt_add_ht_info_ie *pAddHtInfo, /* AP might use this additional ht info IE */
- u8 *pHtCapabilityLen,
- u8 *pAddHtInfoLen,
- u8 *pNewExtChannelOffset,
- struct rt_edca_parm *pEdcaParm, u8 *pCkipFlag);
-
-BOOLEAN PeerDisassocSanity(struct rt_rtmp_adapter *pAd,
- void *Msg,
- unsigned long MsgLen,
- u8 *pAddr2, u16 *Reason);
-
-BOOLEAN PeerWpaMessageSanity(struct rt_rtmp_adapter *pAd,
- struct rt_eapol_packet *pMsg,
- unsigned long MsgLen,
- u8 MsgType, struct rt_mac_table_entry *pEntry);
-
-BOOLEAN PeerDeauthSanity(struct rt_rtmp_adapter *pAd,
- void *Msg,
- unsigned long MsgLen,
- u8 *pAddr2, u16 *Reason);
-
-BOOLEAN PeerProbeReqSanity(struct rt_rtmp_adapter *pAd,
- void *Msg,
- unsigned long MsgLen,
- u8 *pAddr2,
- char Ssid[], u8 *pSsidLen);
-
-BOOLEAN GetTimBit(char *Ptr,
- u16 Aid,
- u8 *TimLen,
- u8 *BcastFlag,
- u8 *DtimCount,
- u8 *DtimPeriod, u8 *MessageToMe);
-
-u8 ChannelSanity(struct rt_rtmp_adapter *pAd, u8 channel);
-
-NDIS_802_11_NETWORK_TYPE NetworkTypeInUseSanity(struct rt_bss_entry *pBss);
-
-BOOLEAN MlmeDelBAReqSanity(struct rt_rtmp_adapter *pAd,
- void *Msg, unsigned long MsgLen);
-
-BOOLEAN MlmeAddBAReqSanity(struct rt_rtmp_adapter *pAd,
- void *Msg, unsigned long MsgLen, u8 *pAddr2);
-
-unsigned long MakeOutgoingFrame(u8 *Buffer, unsigned long *Length, ...);
-
-void LfsrInit(struct rt_rtmp_adapter *pAd, unsigned long Seed);
-
-u8 RandomByte(struct rt_rtmp_adapter *pAd);
-
-void AsicUpdateAutoFallBackTable(struct rt_rtmp_adapter *pAd, u8 *pTxRate);
-
-void MlmePeriodicExec(void *SystemSpecific1,
- void *FunctionContext,
- void *SystemSpecific2, void *SystemSpecific3);
-
-void LinkDownExec(void *SystemSpecific1,
- void *FunctionContext,
- void *SystemSpecific2, void *SystemSpecific3);
-
-void STAMlmePeriodicExec(struct rt_rtmp_adapter *pAd);
-
-void MlmeAutoScan(struct rt_rtmp_adapter *pAd);
-
-void MlmeAutoReconnectLastSSID(struct rt_rtmp_adapter *pAd);
-
-BOOLEAN MlmeValidateSSID(u8 *pSsid, u8 SsidLen);
-
-void MlmeCheckForRoaming(struct rt_rtmp_adapter *pAd, unsigned long Now32);
-
-BOOLEAN MlmeCheckForFastRoaming(struct rt_rtmp_adapter *pAd);
-
-void MlmeDynamicTxRateSwitching(struct rt_rtmp_adapter *pAd);
-
-void MlmeSetTxRate(struct rt_rtmp_adapter *pAd,
- struct rt_mac_table_entry *pEntry, struct rt_rtmp_tx_rate_switch * pTxRate);
-
-void MlmeSelectTxRateTable(struct rt_rtmp_adapter *pAd,
- struct rt_mac_table_entry *pEntry,
- u8 **ppTable,
- u8 *pTableSize, u8 *pInitTxRateIdx);
-
-void MlmeCalculateChannelQuality(struct rt_rtmp_adapter *pAd,
- struct rt_mac_table_entry *pMacEntry, unsigned long Now);
-
-void MlmeCheckPsmChange(struct rt_rtmp_adapter *pAd, unsigned long Now32);
-
-void MlmeSetPsmBit(struct rt_rtmp_adapter *pAd, u16 psm);
-
-void MlmeSetTxPreamble(struct rt_rtmp_adapter *pAd, u16 TxPreamble);
-
-void UpdateBasicRateBitmap(struct rt_rtmp_adapter *pAd);
-
-void MlmeUpdateTxRates(struct rt_rtmp_adapter *pAd,
- IN BOOLEAN bLinkUp, u8 apidx);
-
-void MlmeUpdateHtTxRates(struct rt_rtmp_adapter *pAd, u8 apidx);
-
-void RTMPCheckRates(struct rt_rtmp_adapter *pAd,
- IN u8 SupRate[], IN u8 *SupRateLen);
-
-BOOLEAN RTMPCheckChannel(struct rt_rtmp_adapter *pAd,
- u8 CentralChannel, u8 Channel);
-
-BOOLEAN RTMPCheckHt(struct rt_rtmp_adapter *pAd,
- u8 Wcid,
- struct rt_ht_capability_ie *pHtCapability,
- struct rt_add_ht_info_ie *pAddHtInfo);
-
-void StaQuickResponeForRateUpExec(void *SystemSpecific1,
- void *FunctionContext,
- void *SystemSpecific2,
- void *SystemSpecific3);
-
-void RTMPUpdateMlmeRate(struct rt_rtmp_adapter *pAd);
-
-char RTMPMaxRssi(struct rt_rtmp_adapter *pAd,
- char Rssi0, char Rssi1, char Rssi2);
-
-#ifdef RT30xx
-void AsicSetRxAnt(struct rt_rtmp_adapter *pAd, u8 Ant);
-
-void RTMPFilterCalibration(struct rt_rtmp_adapter *pAd);
-
-#ifdef RTMP_EFUSE_SUPPORT
-/*2008/09/11:KH add to support efuse<-- */
-int set_eFuseGetFreeBlockCount_Proc(struct rt_rtmp_adapter *pAd, char *arg);
-
-int set_eFusedump_Proc(struct rt_rtmp_adapter *pAd, char *arg);
-
-void eFusePhysicalReadRegisters(struct rt_rtmp_adapter *pAd,
- u16 Offset,
- u16 Length, u16 *pData);
-
-int RtmpEfuseSupportCheck(struct rt_rtmp_adapter *pAd);
-
-void eFuseGetFreeBlockCount(struct rt_rtmp_adapter *pAd, u32 *EfuseFreeBlock);
-
-int eFuse_init(struct rt_rtmp_adapter *pAd);
-/*2008/09/11:KH add to support efuse--> */
-#endif /* RTMP_EFUSE_SUPPORT // */
-
-/* add by johnli, RF power sequence setup */
-void RT30xxLoadRFNormalModeSetup(struct rt_rtmp_adapter *pAd);
-
-void RT30xxLoadRFSleepModeSetup(struct rt_rtmp_adapter *pAd);
-
-void RT30xxReverseRFSleepModeSetup(struct rt_rtmp_adapter *pAd);
-/* end johnli */
-
-#ifdef RT3070
-void NICInitRT3070RFRegisters(struct rt_rtmp_adapter *pAd);
-#endif /* RT3070 // */
-#ifdef RT3090
-void NICInitRT3090RFRegisters(struct rt_rtmp_adapter *pAd);
-#endif /* RT3090 // */
-
-void RT30xxHaltAction(struct rt_rtmp_adapter *pAd);
-
-void RT30xxSetRxAnt(struct rt_rtmp_adapter *pAd, u8 Ant);
-#endif /* RT30xx // */
-
-void AsicEvaluateRxAnt(struct rt_rtmp_adapter *pAd);
-
-void AsicRxAntEvalTimeout(void *SystemSpecific1,
- void *FunctionContext,
- void *SystemSpecific2, void *SystemSpecific3);
-
-void APSDPeriodicExec(void *SystemSpecific1,
- void *FunctionContext,
- void *SystemSpecific2, void *SystemSpecific3);
-
-BOOLEAN RTMPCheckEntryEnableAutoRateSwitch(struct rt_rtmp_adapter *pAd,
- struct rt_mac_table_entry *pEntry);
-
-u8 RTMPStaFixedTxMode(struct rt_rtmp_adapter *pAd, struct rt_mac_table_entry *pEntry);
-
-void RTMPUpdateLegacyTxSetting(u8 fixed_tx_mode, struct rt_mac_table_entry *pEntry);
-
-BOOLEAN RTMPAutoRateSwitchCheck(struct rt_rtmp_adapter *pAd);
-
-int MlmeInit(struct rt_rtmp_adapter *pAd);
-
-void MlmeHandler(struct rt_rtmp_adapter *pAd);
-
-void MlmeHalt(struct rt_rtmp_adapter *pAd);
-
-void MlmeResetRalinkCounters(struct rt_rtmp_adapter *pAd);
-
-void BuildChannelList(struct rt_rtmp_adapter *pAd);
-
-u8 FirstChannel(struct rt_rtmp_adapter *pAd);
-
-u8 NextChannel(struct rt_rtmp_adapter *pAd, u8 channel);
-
-void ChangeToCellPowerLimit(struct rt_rtmp_adapter *pAd,
- u8 AironetCellPowerLimit);
-
-/* */
-/* Prototypes of function definition in rtmp_tkip.c */
-/* */
-void RTMPInitTkipEngine(struct rt_rtmp_adapter *pAd,
- u8 *pTKey,
- u8 KeyId,
- u8 *pTA,
- u8 *pMICKey,
- u8 *pTSC, unsigned long *pIV16, unsigned long *pIV32);
-
-void RTMPInitMICEngine(struct rt_rtmp_adapter *pAd,
- u8 *pKey,
- u8 *pDA,
- u8 *pSA, u8 UserPriority, u8 *pMICKey);
-
-BOOLEAN RTMPTkipCompareMICValue(struct rt_rtmp_adapter *pAd,
- u8 *pSrc,
- u8 *pDA,
- u8 *pSA,
- u8 *pMICKey,
- u8 UserPriority, u32 Len);
-
-void RTMPCalculateMICValue(struct rt_rtmp_adapter *pAd,
- void *pPacket,
- u8 *pEncap,
- struct rt_cipher_key *pKey, u8 apidx);
-
-void RTMPTkipAppendByte(struct rt_tkip_key_info *pTkip, u8 uChar);
-
-void RTMPTkipAppend(struct rt_tkip_key_info *pTkip, u8 *pSrc, u32 nBytes);
-
-void RTMPTkipGetMIC(struct rt_tkip_key_info *pTkip);
-
-BOOLEAN RTMPSoftDecryptTKIP(struct rt_rtmp_adapter *pAd,
- u8 *pData,
- unsigned long DataByteCnt,
- u8 UserPriority, struct rt_cipher_key *pWpaKey);
-
-BOOLEAN RTMPSoftDecryptAES(struct rt_rtmp_adapter *pAd,
- u8 *pData,
- unsigned long DataByteCnt, struct rt_cipher_key *pWpaKey);
-
-/* */
-/* Prototypes of function definition in cmm_info.c */
-/* */
-int RT_CfgSetCountryRegion(struct rt_rtmp_adapter *pAd, char *arg, int band);
-
-int RT_CfgSetWirelessMode(struct rt_rtmp_adapter *pAd, char *arg);
-
-int RT_CfgSetShortSlot(struct rt_rtmp_adapter *pAd, char *arg);
-
-int RT_CfgSetWepKey(struct rt_rtmp_adapter *pAd,
- char *keyString,
- struct rt_cipher_key *pSharedKey, int keyIdx);
-
-int RT_CfgSetWPAPSKKey(struct rt_rtmp_adapter *pAd,
- char *keyString,
- u8 *pHashStr,
- int hashStrLen, u8 *pPMKBuf);
-
-/* */
-/* Prototypes of function definition in cmm_info.c */
-/* */
-void RTMPWPARemoveAllKeys(struct rt_rtmp_adapter *pAd);
-
-void RTMPSetPhyMode(struct rt_rtmp_adapter *pAd, unsigned long phymode);
-
-void RTMPUpdateHTIE(struct rt_ht_capability *pRtHt,
- u8 *pMcsSet,
- struct rt_ht_capability_ie *pHtCapability,
- struct rt_add_ht_info_ie *pAddHtInfo);
-
-void RTMPAddWcidAttributeEntry(struct rt_rtmp_adapter *pAd,
- u8 BssIdx,
- u8 KeyIdx,
- u8 CipherAlg, struct rt_mac_table_entry *pEntry);
-
-char *GetEncryptType(char enc);
-
-char *GetAuthMode(char auth);
-
-void RTMPSetHT(struct rt_rtmp_adapter *pAd, struct rt_oid_set_ht_phymode *pHTPhyMode);
-
-void RTMPSetIndividualHT(struct rt_rtmp_adapter *pAd, u8 apidx);
-
-void RTMPSendWirelessEvent(struct rt_rtmp_adapter *pAd,
- u16 Event_flag,
- u8 *pAddr, u8 BssIdx, char Rssi);
-
-char ConvertToRssi(struct rt_rtmp_adapter *pAd, char Rssi, u8 RssiNumber);
-
-/*===================================
- Function prototype in cmm_wpa.c
- =================================== */
-void RTMPToWirelessSta(struct rt_rtmp_adapter *pAd,
- struct rt_mac_table_entry *pEntry,
- u8 *pHeader802_3,
- u32 HdrLen,
- u8 *pData,
- u32 DataLen, IN BOOLEAN bClearFrame);
-
-void WpaDerivePTK(struct rt_rtmp_adapter *pAd,
- u8 *PMK,
- u8 *ANonce,
- u8 *AA,
- u8 *SNonce,
- u8 *SA, u8 *output, u32 len);
-
-void GenRandom(struct rt_rtmp_adapter *pAd, u8 *macAddr, u8 *random);
-
-BOOLEAN RTMPCheckWPAframe(struct rt_rtmp_adapter *pAd,
- struct rt_mac_table_entry *pEntry,
- u8 *pData,
- unsigned long DataByteCount, u8 FromWhichBSSID);
-
-void AES_GTK_KEY_UNWRAP(u8 *key,
- u8 *plaintext,
- u32 c_len, u8 *ciphertext);
-
-BOOLEAN RTMPParseEapolKeyData(struct rt_rtmp_adapter *pAd,
- u8 *pKeyData,
- u8 KeyDataLen,
- u8 GroupKeyIndex,
- u8 MsgType,
- IN BOOLEAN bWPA2, struct rt_mac_table_entry *pEntry);
-
-void ConstructEapolMsg(struct rt_mac_table_entry *pEntry,
- u8 GroupKeyWepStatus,
- u8 MsgType,
- u8 DefaultKeyIdx,
- u8 *KeyNonce,
- u8 *TxRSC,
- u8 *GTK,
- u8 *RSNIE,
- u8 RSNIE_Len, struct rt_eapol_packet *pMsg);
-
-int RTMPSoftDecryptBroadCastData(struct rt_rtmp_adapter *pAd,
- struct rt_rx_blk *pRxBlk,
- IN NDIS_802_11_ENCRYPTION_STATUS
- GroupCipher,
- struct rt_cipher_key *pShard_key);
-
-void RTMPMakeRSNIE(struct rt_rtmp_adapter *pAd,
- u32 AuthMode, u32 WepStatus, u8 apidx);
-
-/* */
-/* function prototype in ap_wpa.c */
-/* */
-void RTMPGetTxTscFromAsic(struct rt_rtmp_adapter *pAd,
- u8 apidx, u8 *pTxTsc);
-
-void APInstallPairwiseKey(struct rt_rtmp_adapter *pAd, struct rt_mac_table_entry *pEntry);
-
-u32 APValidateRSNIE(struct rt_rtmp_adapter *pAd,
- struct rt_mac_table_entry *pEntry,
- u8 *pRsnIe, u8 rsnie_len);
-
-void HandleCounterMeasure(struct rt_rtmp_adapter *pAd, struct rt_mac_table_entry *pEntry);
-
-void WPAStart4WayHS(struct rt_rtmp_adapter *pAd,
- struct rt_mac_table_entry *pEntry, unsigned long TimeInterval);
-
-void WPAStart2WayGroupHS(struct rt_rtmp_adapter *pAd, struct rt_mac_table_entry *pEntry);
-
-void PeerPairMsg1Action(struct rt_rtmp_adapter *pAd,
- struct rt_mac_table_entry *pEntry, struct rt_mlme_queue_elem *Elem);
-
-void PeerPairMsg2Action(struct rt_rtmp_adapter *pAd,
- struct rt_mac_table_entry *pEntry, struct rt_mlme_queue_elem *Elem);
-
-void PeerPairMsg3Action(struct rt_rtmp_adapter *pAd,
- struct rt_mac_table_entry *pEntry, struct rt_mlme_queue_elem *Elem);
-
-void PeerPairMsg4Action(struct rt_rtmp_adapter *pAd,
- struct rt_mac_table_entry *pEntry, struct rt_mlme_queue_elem *Elem);
-
-void PeerGroupMsg1Action(struct rt_rtmp_adapter *pAd,
- struct rt_mac_table_entry *pEntry, struct rt_mlme_queue_elem *Elem);
-
-void PeerGroupMsg2Action(struct rt_rtmp_adapter *pAd,
- struct rt_mac_table_entry *pEntry,
- void *Msg, u32 MsgLen);
-
-void WpaDeriveGTK(u8 *PMK,
- u8 *GNonce,
- u8 *AA, u8 *output, u32 len);
-
-void AES_GTK_KEY_WRAP(u8 *key,
- u8 *plaintext,
- u32 p_len, u8 *ciphertext);
-
-/*typedef void (*TIMER_FUNCTION)(unsigned long); */
-
-/* timeout -- ms */
-void RTMP_SetPeriodicTimer(struct timer_list *pTimer,
- IN unsigned long timeout);
-
-void RTMP_OS_Init_Timer(struct rt_rtmp_adapter *pAd,
- struct timer_list *pTimer,
- IN TIMER_FUNCTION function, void *data);
-
-void RTMP_OS_Add_Timer(struct timer_list *pTimer,
- IN unsigned long timeout);
-
-void RTMP_OS_Mod_Timer(struct timer_list *pTimer,
- IN unsigned long timeout);
-
-void RTMP_OS_Del_Timer(struct timer_list *pTimer,
- OUT BOOLEAN *pCancelled);
-
-void RTMP_OS_Release_Packet(struct rt_rtmp_adapter *pAd, struct rt_queue_entry *pEntry);
-
-void RTMPusecDelay(unsigned long usec);
-
-int os_alloc_mem(struct rt_rtmp_adapter *pAd,
- u8 **mem, unsigned long size);
-
-int os_free_mem(struct rt_rtmp_adapter *pAd, void *mem);
-
-void RTMP_AllocateSharedMemory(struct rt_rtmp_adapter *pAd,
- unsigned long Length,
- IN BOOLEAN Cached,
- void **VirtualAddress,
- dma_addr_t *PhysicalAddress);
-
-void RTMPFreeTxRxRingMemory(struct rt_rtmp_adapter *pAd);
-
-int AdapterBlockAllocateMemory(void *handle, void **ppAd);
-
-void RTMP_AllocateTxDescMemory(struct rt_rtmp_adapter *pAd,
- u32 Index,
- unsigned long Length,
- IN BOOLEAN Cached,
- void **VirtualAddress,
- dma_addr_t *PhysicalAddress);
-
-void RTMP_AllocateFirstTxBuffer(struct rt_rtmp_adapter *pAd,
- u32 Index,
- unsigned long Length,
- IN BOOLEAN Cached,
- void **VirtualAddress,
- dma_addr_t *PhysicalAddress);
-
-void RTMP_FreeFirstTxBuffer(struct rt_rtmp_adapter *pAd,
- unsigned long Length,
- IN BOOLEAN Cached,
- void *VirtualAddress,
- dma_addr_t PhysicalAddress);
-
-void RTMP_AllocateMgmtDescMemory(struct rt_rtmp_adapter *pAd,
- unsigned long Length,
- IN BOOLEAN Cached,
- void **VirtualAddress,
- dma_addr_t *PhysicalAddress);
-
-void RTMP_AllocateRxDescMemory(struct rt_rtmp_adapter *pAd,
- unsigned long Length,
- IN BOOLEAN Cached,
- void **VirtualAddress,
- dma_addr_t *PhysicalAddress);
-
-void RTMP_FreeDescMemory(struct rt_rtmp_adapter *pAd,
- unsigned long Length,
- void *VirtualAddress,
- dma_addr_t PhysicalAddress);
-
-void *RtmpOSNetPktAlloc(struct rt_rtmp_adapter *pAd, IN int size);
-
-void *RTMP_AllocateRxPacketBuffer(struct rt_rtmp_adapter *pAd,
- unsigned long Length,
- IN BOOLEAN Cached,
- void **VirtualAddress,
- OUT dma_addr_t *PhysicalAddress);
-
-void *RTMP_AllocateTxPacketBuffer(struct rt_rtmp_adapter *pAd,
- unsigned long Length,
- IN BOOLEAN Cached,
- void **VirtualAddress);
-
-void *RTMP_AllocateFragPacketBuffer(struct rt_rtmp_adapter *pAd,
- unsigned long Length);
-
-void RTMP_QueryPacketInfo(void *pPacket,
- struct rt_packet_info *pPacketInfo,
- u8 **pSrcBufVA, u32 *pSrcBufLen);
-
-void RTMP_QueryNextPacketInfo(void **ppPacket,
- struct rt_packet_info *pPacketInfo,
- u8 **pSrcBufVA, u32 *pSrcBufLen);
-
-BOOLEAN RTMP_FillTxBlkInfo(struct rt_rtmp_adapter *pAd, struct rt_tx_blk *pTxBlk);
-
-struct rt_rtmp_sg_list *rt_get_sg_list_from_packet(void *pPacket,
- struct rt_rtmp_sg_list *sg);
-
-void announce_802_3_packet(struct rt_rtmp_adapter *pAd, void *pPacket);
-
-u32 BA_Reorder_AMSDU_Announce(struct rt_rtmp_adapter *pAd, void *pPacket);
-
-struct net_device *get_netdev_from_bssid(struct rt_rtmp_adapter *pAd, u8 FromWhichBSSID);
-
-void *duplicate_pkt(struct rt_rtmp_adapter *pAd,
- u8 *pHeader802_3,
- u32 HdrLen,
- u8 *pData,
- unsigned long DataSize, u8 FromWhichBSSID);
-
-void *duplicate_pkt_with_TKIP_MIC(struct rt_rtmp_adapter *pAd,
- void *pOldPkt);
-
-void ba_flush_reordering_timeout_mpdus(struct rt_rtmp_adapter *pAd,
- struct rt_ba_rec_entry *pBAEntry,
- unsigned long Now32);
-
-void BAOriSessionSetUp(struct rt_rtmp_adapter *pAd,
- struct rt_mac_table_entry *pEntry,
- u8 TID,
- u16 TimeOut,
- unsigned long DelayTime, IN BOOLEAN isForced);
-
-void BASessionTearDownALL(struct rt_rtmp_adapter *pAd, u8 Wcid);
-
-BOOLEAN OS_Need_Clone_Packet(void);
-
-void build_tx_packet(struct rt_rtmp_adapter *pAd,
- void *pPacket,
- u8 *pFrame, unsigned long FrameLen);
-
-void BAOriSessionTearDown(struct rt_rtmp_adapter *pAd,
- u8 Wcid,
- u8 TID,
- IN BOOLEAN bPassive, IN BOOLEAN bForceSend);
-
-void BARecSessionTearDown(struct rt_rtmp_adapter *pAd,
- u8 Wcid, u8 TID, IN BOOLEAN bPassive);
-
-BOOLEAN ba_reordering_resource_init(struct rt_rtmp_adapter *pAd, int num);
-void ba_reordering_resource_release(struct rt_rtmp_adapter *pAd);
-
-char *rstrtok(char *s, IN const char *ct);
-
-/*//////// common ioctl functions ////////// */
-int SetCommonHT(struct rt_rtmp_adapter *pAd);
-
-int WpaCheckEapCode(struct rt_rtmp_adapter *pAd,
- u8 *pFrame, u16 FrameLen, u16 OffSet);
-
-void WpaSendMicFailureToWpaSupplicant(struct rt_rtmp_adapter *pAd,
- IN BOOLEAN bUnicast);
-
-int wext_notify_event_assoc(struct rt_rtmp_adapter *pAd);
-
-BOOLEAN STARxDoneInterruptHandle(struct rt_rtmp_adapter *pAd, IN BOOLEAN argc);
-
-/* AMPDU packet indication */
-void Indicate_AMPDU_Packet(struct rt_rtmp_adapter *pAd,
- struct rt_rx_blk *pRxBlk, u8 FromWhichBSSID);
-
-/* AMSDU packet indication */
-void Indicate_AMSDU_Packet(struct rt_rtmp_adapter *pAd,
- struct rt_rx_blk *pRxBlk, u8 FromWhichBSSID);
-
-/* Normal legacy Rx packet indication */
-void Indicate_Legacy_Packet(struct rt_rtmp_adapter *pAd,
- struct rt_rx_blk *pRxBlk, u8 FromWhichBSSID);
-
-void Indicate_EAPOL_Packet(struct rt_rtmp_adapter *pAd,
- struct rt_rx_blk *pRxBlk, u8 FromWhichBSSID);
-
-void update_os_packet_info(struct rt_rtmp_adapter *pAd,
- struct rt_rx_blk *pRxBlk, u8 FromWhichBSSID);
-
-void wlan_802_11_to_802_3_packet(struct rt_rtmp_adapter *pAd,
- struct rt_rx_blk *pRxBlk,
- u8 *pHeader802_3,
- u8 FromWhichBSSID);
-
-/* remove LLC and get 802_3 Header */
-#define RTMP_802_11_REMOVE_LLC_AND_CONVERT_TO_802_3(_pRxBlk, _pHeader802_3) \
-{ \
- u8 *_pRemovedLLCSNAP = NULL, *_pDA, *_pSA; \
- \
- if (RX_BLK_TEST_FLAG(_pRxBlk, fRX_MESH)) { \
- _pDA = _pRxBlk->pHeader->Addr3; \
- _pSA = (u8 *)_pRxBlk->pHeader + sizeof(struct rt_header_802_11); \
- } \
- else {\
- if (RX_BLK_TEST_FLAG(_pRxBlk, fRX_INFRA)) {\
- _pDA = _pRxBlk->pHeader->Addr1; \
- if (RX_BLK_TEST_FLAG(_pRxBlk, fRX_DLS)) \
- _pSA = _pRxBlk->pHeader->Addr2; \
- else \
- _pSA = _pRxBlk->pHeader->Addr3; \
- } \
- else { \
- _pDA = _pRxBlk->pHeader->Addr1; \
- _pSA = _pRxBlk->pHeader->Addr2; \
- } \
- } \
- \
- CONVERT_TO_802_3(_pHeader802_3, _pDA, _pSA, _pRxBlk->pData, \
- _pRxBlk->DataSize, _pRemovedLLCSNAP); \
-}
-
-void Sta_Announce_or_Forward_802_3_Packet(struct rt_rtmp_adapter *pAd,
- void *pPacket,
- u8 FromWhichBSSID);
-
-#define ANNOUNCE_OR_FORWARD_802_3_PACKET(_pAd, _pPacket, _FromWhichBSS)\
- Sta_Announce_or_Forward_802_3_Packet(_pAd, _pPacket, _FromWhichBSS);
- /*announce_802_3_packet(_pAd, _pPacket); */
-
-void *DuplicatePacket(struct rt_rtmp_adapter *pAd,
- void *pPacket, u8 FromWhichBSSID);
-
-void *ClonePacket(struct rt_rtmp_adapter *pAd,
- void *pPacket,
- u8 *pData, unsigned long DataSize);
-
-/* Normal, AMPDU or AMSDU */
-void CmmRxnonRalinkFrameIndicate(struct rt_rtmp_adapter *pAd,
- struct rt_rx_blk *pRxBlk, u8 FromWhichBSSID);
-
-void CmmRxRalinkFrameIndicate(struct rt_rtmp_adapter *pAd,
- struct rt_mac_table_entry *pEntry,
- struct rt_rx_blk *pRxBlk, u8 FromWhichBSSID);
-
-void Update_Rssi_Sample(struct rt_rtmp_adapter *pAd,
- struct rt_rssi_sample *pRssi, struct rt_rxwi * pRxWI);
-
-void *GetPacketFromRxRing(struct rt_rtmp_adapter *pAd,
- OUT PRT28XX_RXD_STRUC pSaveRxD,
- OUT BOOLEAN *pbReschedule,
- IN u32 *pRxPending);
-
-void *RTMPDeFragmentDataFrame(struct rt_rtmp_adapter *pAd, struct rt_rx_blk *pRxBlk);
-
-enum {
- DIDmsg_lnxind_wlansniffrm = 0x00000044,
- DIDmsg_lnxind_wlansniffrm_hosttime = 0x00010044,
- DIDmsg_lnxind_wlansniffrm_mactime = 0x00020044,
- DIDmsg_lnxind_wlansniffrm_channel = 0x00030044,
- DIDmsg_lnxind_wlansniffrm_rssi = 0x00040044,
- DIDmsg_lnxind_wlansniffrm_sq = 0x00050044,
- DIDmsg_lnxind_wlansniffrm_signal = 0x00060044,
- DIDmsg_lnxind_wlansniffrm_noise = 0x00070044,
- DIDmsg_lnxind_wlansniffrm_rate = 0x00080044,
- DIDmsg_lnxind_wlansniffrm_istx = 0x00090044,
- DIDmsg_lnxind_wlansniffrm_frmlen = 0x000A0044
-};
-enum {
- P80211ENUM_msgitem_status_no_value = 0x00
-};
-enum {
- P80211ENUM_truth_false = 0x00,
- P80211ENUM_truth_true = 0x01
-};
-
-/* Definition from madwifi */
-struct rt_p80211item_uint32 {
- u32 did;
- u16 status;
- u16 len;
- u32 data;
-};
-
-struct rt_wlan_ng_prism2_header {
- u32 msgcode;
- u32 msglen;
-#define WLAN_DEVNAMELEN_MAX 16
- u8 devname[WLAN_DEVNAMELEN_MAX];
- struct rt_p80211item_uint32 hosttime;
- struct rt_p80211item_uint32 mactime;
- struct rt_p80211item_uint32 channel;
- struct rt_p80211item_uint32 rssi;
- struct rt_p80211item_uint32 sq;
- struct rt_p80211item_uint32 signal;
- struct rt_p80211item_uint32 noise;
- struct rt_p80211item_uint32 rate;
- struct rt_p80211item_uint32 istx;
- struct rt_p80211item_uint32 frmlen;
-};
-
-/* The radio capture header precedes the 802.11 header. */
-struct PACKED rt_ieee80211_radiotap_header {
- u8 it_version; /* Version 0. Only increases
- * for drastic changes,
- * introduction of compatible
- * new fields does not count.
- */
- u8 it_pad;
- u16 it_len; /* length of the whole
- * header in bytes, including
- * it_version, it_pad,
- * it_len, and data fields.
- */
- u32 it_present; /* A bitmap telling which
- * fields are present. Set bit 31
- * (0x80000000) to extend the
- * bitmap by another 32 bits.
- * Additional extensions are made
- * by setting bit 31.
- */
-};
-
-enum ieee80211_radiotap_type {
- IEEE80211_RADIOTAP_TSFT = 0,
- IEEE80211_RADIOTAP_FLAGS = 1,
- IEEE80211_RADIOTAP_RATE = 2,
- IEEE80211_RADIOTAP_CHANNEL = 3,
- IEEE80211_RADIOTAP_FHSS = 4,
- IEEE80211_RADIOTAP_DBM_ANTSIGNAL = 5,
- IEEE80211_RADIOTAP_DBM_ANTNOISE = 6,
- IEEE80211_RADIOTAP_LOCK_QUALITY = 7,
- IEEE80211_RADIOTAP_TX_ATTENUATION = 8,
- IEEE80211_RADIOTAP_DB_TX_ATTENUATION = 9,
- IEEE80211_RADIOTAP_DBM_TX_POWER = 10,
- IEEE80211_RADIOTAP_ANTENNA = 11,
- IEEE80211_RADIOTAP_DB_ANTSIGNAL = 12,
- IEEE80211_RADIOTAP_DB_ANTNOISE = 13
-};
-
-#define WLAN_RADIOTAP_PRESENT ( \
- (1 << IEEE80211_RADIOTAP_TSFT) | \
- (1 << IEEE80211_RADIOTAP_FLAGS) | \
- (1 << IEEE80211_RADIOTAP_RATE) | \
- 0)
-
-struct rt_wlan_radiotap_header {
- struct rt_ieee80211_radiotap_header wt_ihdr;
- long long wt_tsft;
- u8 wt_flags;
- u8 wt_rate;
-};
-/* Definition from madwifi */
-
-void send_monitor_packets(struct rt_rtmp_adapter *pAd, struct rt_rx_blk *pRxBlk);
-
-void RTMPSetDesiredRates(struct rt_rtmp_adapter *pAdapter, long Rates);
-
-int Set_FixedTxMode_Proc(struct rt_rtmp_adapter *pAd, char *arg);
-
-BOOLEAN RT28XXChipsetCheck(IN void *_dev_p);
-
-void RT28XXDMADisable(struct rt_rtmp_adapter *pAd);
-
-void RT28XXDMAEnable(struct rt_rtmp_adapter *pAd);
-
-void RT28xx_UpdateBeaconToAsic(struct rt_rtmp_adapter *pAd,
- int apidx,
- unsigned long BeaconLen, unsigned long UpdatePos);
-
-int rt28xx_init(struct rt_rtmp_adapter *pAd,
- char *pDefaultMac, char *pHostName);
-
-int RtmpNetTaskInit(struct rt_rtmp_adapter *pAd);
-
-void RtmpNetTaskExit(struct rt_rtmp_adapter *pAd);
-
-int RtmpMgmtTaskInit(struct rt_rtmp_adapter *pAd);
-
-void RtmpMgmtTaskExit(struct rt_rtmp_adapter *pAd);
-
-void tbtt_tasklet(unsigned long data);
-
-struct net_device *RtmpPhyNetDevInit(struct rt_rtmp_adapter *pAd,
- struct rt_rtmp_os_netdev_op_hook *pNetHook);
-
-BOOLEAN RtmpPhyNetDevExit(struct rt_rtmp_adapter *pAd, struct net_device *net_dev);
-
-int RtmpRaDevCtrlInit(struct rt_rtmp_adapter *pAd, IN RTMP_INF_TYPE infType);
-
-BOOLEAN RtmpRaDevCtrlExit(struct rt_rtmp_adapter *pAd);
-
-#ifdef RTMP_MAC_PCI
-/* */
-/* Function Prototype in cmm_data_pci.c */
-/* */
-u16 RtmpPCI_WriteTxResource(struct rt_rtmp_adapter *pAd,
- struct rt_tx_blk *pTxBlk,
- IN BOOLEAN bIsLast, u16 *FreeNumber);
-
-u16 RtmpPCI_WriteSingleTxResource(struct rt_rtmp_adapter *pAd,
- struct rt_tx_blk *pTxBlk,
- IN BOOLEAN bIsLast,
- u16 *FreeNumber);
-
-u16 RtmpPCI_WriteMultiTxResource(struct rt_rtmp_adapter *pAd,
- struct rt_tx_blk *pTxBlk,
- u8 frameNum, u16 *FreeNumber);
-
-u16 RtmpPCI_WriteFragTxResource(struct rt_rtmp_adapter *pAd,
- struct rt_tx_blk *pTxBlk,
- u8 fragNum, u16 *FreeNumber);
-
-u16 RtmpPCI_WriteSubTxResource(struct rt_rtmp_adapter *pAd,
- struct rt_tx_blk *pTxBlk,
- IN BOOLEAN bIsLast, u16 *FreeNumber);
-
-void RtmpPCI_FinalWriteTxResource(struct rt_rtmp_adapter *pAd,
- struct rt_tx_blk *pTxBlk,
- u16 totalMPDUSize,
- u16 FirstTxIdx);
-
-void RtmpPCIDataLastTxIdx(struct rt_rtmp_adapter *pAd,
- u8 QueIdx, u16 LastTxIdx);
-
-void RtmpPCIDataKickOut(struct rt_rtmp_adapter *pAd,
- struct rt_tx_blk *pTxBlk, u8 QueIdx);
-
-int RtmpPCIMgmtKickOut(struct rt_rtmp_adapter *pAd,
- u8 QueIdx,
- void *pPacket,
- u8 *pSrcBufVA, u32 SrcBufLen);
-
-int RTMPCheckRxError(struct rt_rtmp_adapter *pAd,
- struct rt_header_802_11 *pHeader,
- struct rt_rxwi *pRxWI, IN PRT28XX_RXD_STRUC pRxD);
-
-BOOLEAN RT28xxPciAsicRadioOff(struct rt_rtmp_adapter *pAd,
- u8 Level, u16 TbttNumToNextWakeUp);
-
-BOOLEAN RT28xxPciAsicRadioOn(struct rt_rtmp_adapter *pAd, u8 Level);
-
-void RTMPInitPCIeLinkCtrlValue(struct rt_rtmp_adapter *pAd);
-
-void RTMPFindHostPCIDev(struct rt_rtmp_adapter *pAd);
-
-void RTMPPCIeLinkCtrlValueRestore(struct rt_rtmp_adapter *pAd, u8 Level);
-
-void RTMPPCIeLinkCtrlSetting(struct rt_rtmp_adapter *pAd, u16 Max);
-
-void RTMPrt3xSetPCIePowerLinkCtrl(struct rt_rtmp_adapter *pAd);
-
-void PsPollWakeExec(void *SystemSpecific1,
- void *FunctionContext,
- void *SystemSpecific2, void *SystemSpecific3);
-
-void RadioOnExec(void *SystemSpecific1,
- void *FunctionContext,
- void *SystemSpecific2, void *SystemSpecific3);
-
-void RT28xxPciStaAsicForceWakeup(struct rt_rtmp_adapter *pAd, IN BOOLEAN bFromTx);
-
-void RT28xxPciStaAsicSleepThenAutoWakeup(struct rt_rtmp_adapter *pAd,
- u16 TbttNumToNextWakeUp);
-
-void RT28xxPciMlmeRadioOn(struct rt_rtmp_adapter *pAd);
-
-void RT28xxPciMlmeRadioOFF(struct rt_rtmp_adapter *pAd);
-#endif /* RTMP_MAC_PCI // */
-
-#ifdef RTMP_MAC_USB
-/* */
-/* Function Prototype in rtusb_bulk.c */
-/* */
-void RTUSBInitTxDesc(struct rt_rtmp_adapter *pAd,
- struct rt_tx_context *pTxContext,
- u8 BulkOutPipeId, IN usb_complete_t Func);
-
-void RTUSBInitHTTxDesc(struct rt_rtmp_adapter *pAd,
- struct rt_ht_tx_context *pTxContext,
- u8 BulkOutPipeId,
- unsigned long BulkOutSize, IN usb_complete_t Func);
-
-void RTUSBInitRxDesc(struct rt_rtmp_adapter *pAd, struct rt_rx_context *pRxContext);
-
-void RTUSBCleanUpDataBulkOutQueue(struct rt_rtmp_adapter *pAd);
-
-void RTUSBCancelPendingBulkOutIRP(struct rt_rtmp_adapter *pAd);
-
-void RTUSBBulkOutDataPacket(struct rt_rtmp_adapter *pAd,
- u8 BulkOutPipeId, u8 Index);
-
-void RTUSBBulkOutNullFrame(struct rt_rtmp_adapter *pAd);
-
-void RTUSBBulkOutRTSFrame(struct rt_rtmp_adapter *pAd);
-
-void RTUSBCancelPendingBulkInIRP(struct rt_rtmp_adapter *pAd);
-
-void RTUSBCancelPendingIRPs(struct rt_rtmp_adapter *pAd);
-
-void RTUSBBulkOutMLMEPacket(struct rt_rtmp_adapter *pAd, u8 Index);
-
-void RTUSBBulkOutPsPoll(struct rt_rtmp_adapter *pAd);
-
-void RTUSBCleanUpMLMEBulkOutQueue(struct rt_rtmp_adapter *pAd);
-
-void RTUSBKickBulkOut(struct rt_rtmp_adapter *pAd);
-
-void RTUSBBulkReceive(struct rt_rtmp_adapter *pAd);
-
-void DoBulkIn(struct rt_rtmp_adapter *pAd);
-
-void RTUSBInitRxDesc(struct rt_rtmp_adapter *pAd, struct rt_rx_context *pRxContext);
-
-void RTUSBBulkRxHandle(IN unsigned long data);
-
-/* */
-/* Function Prototype in rtusb_io.c */
-/* */
-int RTUSBMultiRead(struct rt_rtmp_adapter *pAd,
- u16 Offset, u8 *pData, u16 length);
-
-int RTUSBMultiWrite(struct rt_rtmp_adapter *pAd,
- u16 Offset, const u8 *pData, u16 length);
-
-int RTUSBMultiWrite_OneByte(struct rt_rtmp_adapter *pAd,
- u16 Offset, const u8 *pData);
-
-int RTUSBReadBBPRegister(struct rt_rtmp_adapter *pAd,
- u8 Id, u8 *pValue);
-
-int RTUSBWriteBBPRegister(struct rt_rtmp_adapter *pAd,
- u8 Id, u8 Value);
-
-int RTUSBWriteRFRegister(struct rt_rtmp_adapter *pAd, u32 Value);
-
-int RTUSB_VendorRequest(struct rt_rtmp_adapter *pAd,
- u32 TransferFlags,
- u8 ReservedBits,
- u8 Request,
- u16 Value,
- u16 Index,
- void *TransferBuffer,
- u32 TransferBufferLength);
-
-int RTUSBReadEEPROM(struct rt_rtmp_adapter *pAd,
- u16 Offset, u8 *pData, u16 length);
-
-int RTUSBWriteEEPROM(struct rt_rtmp_adapter *pAd,
- u16 Offset, u8 *pData, u16 length);
-
-void RTUSBPutToSleep(struct rt_rtmp_adapter *pAd);
-
-int RTUSBWakeUp(struct rt_rtmp_adapter *pAd);
-
-void RTUSBInitializeCmdQ(struct rt_cmdq *cmdq);
-
-int RTUSBEnqueueCmdFromNdis(struct rt_rtmp_adapter *pAd,
- IN NDIS_OID Oid,
- IN BOOLEAN SetInformation,
- void *pInformationBuffer,
- u32 InformationBufferLength);
-
-int RTUSBEnqueueInternalCmd(struct rt_rtmp_adapter *pAd,
- IN NDIS_OID Oid,
- void *pInformationBuffer,
- u32 InformationBufferLength);
-
-void RTUSBDequeueCmd(struct rt_cmdq *cmdq, struct rt_cmdqelmt * * pcmdqelmt);
-
-int RTUSBCmdThread(IN void *Context);
-
-void RTUSBBssBeaconExit(struct rt_rtmp_adapter *pAd);
-
-void RTUSBBssBeaconStop(struct rt_rtmp_adapter *pAd);
-
-void RTUSBBssBeaconStart(struct rt_rtmp_adapter *pAd);
-
-void RTUSBBssBeaconInit(struct rt_rtmp_adapter *pAd);
-
-void RTUSBWatchDog(struct rt_rtmp_adapter *pAd);
-
-int RTUSBWriteMACRegister(struct rt_rtmp_adapter *pAd,
- u16 Offset, u32 Value);
-
-int RTUSBReadMACRegister(struct rt_rtmp_adapter *pAd,
- u16 Offset, u32 *pValue);
-
-int RTUSBSingleWrite(struct rt_rtmp_adapter *pAd,
- u16 Offset, u16 Value);
-
-int RTUSBFirmwareWrite(struct rt_rtmp_adapter *pAd,
- const u8 *pFwImage, unsigned long FwLen);
-
-int RTUSBVenderReset(struct rt_rtmp_adapter *pAd);
-
-int RTUSBSetHardWareRegister(struct rt_rtmp_adapter *pAdapter, void *pBuf);
-
-int RTUSBQueryHardWareRegister(struct rt_rtmp_adapter *pAdapter,
- void *pBuf);
-
-void CMDHandler(struct rt_rtmp_adapter *pAd);
-
-int RTUSBWriteHWMACAddress(struct rt_rtmp_adapter *pAdapter);
-
-void MacTableInitialize(struct rt_rtmp_adapter *pAd);
-
-void MlmeSetPsm(struct rt_rtmp_adapter *pAd, u16 psm);
-
-int RTMPWPAAddKeyProc(struct rt_rtmp_adapter *pAd, void *pBuf);
-
-void AsicRxAntEvalAction(struct rt_rtmp_adapter *pAd);
-
-void append_pkt(struct rt_rtmp_adapter *pAd,
- u8 *pHeader802_3,
- u32 HdrLen,
- u8 *pData,
- unsigned long DataSize, void **ppPacket);
-
-u32 deaggregate_AMSDU_announce(struct rt_rtmp_adapter *pAd,
- void *pPacket,
- u8 *pData, unsigned long DataSize);
-
-int RTMPCheckRxError(struct rt_rtmp_adapter *pAd,
- struct rt_header_802_11 *pHeader,
- struct rt_rxwi *pRxWI,
- IN PRT28XX_RXD_STRUC pRxINFO);
-
-void RTUSBMlmeHardTransmit(struct rt_rtmp_adapter *pAd, struct rt_mgmt *pMgmt);
-
-int MlmeThread(void *Context);
-
-/* */
-/* Function Prototype in rtusb_data.c */
-/* */
-int RTUSBFreeDescriptorRequest(struct rt_rtmp_adapter *pAd,
- u8 BulkOutPipeId,
- u32 NumberRequired);
-
-BOOLEAN RTUSBNeedQueueBackForAgg(struct rt_rtmp_adapter *pAd, u8 BulkOutPipeId);
-
-void RTMPWriteTxInfo(struct rt_rtmp_adapter *pAd,
- struct rt_txinfo *pTxInfo,
- u16 USBDMApktLen,
- IN BOOLEAN bWiv,
- u8 QueueSel, u8 NextValid, u8 TxBurst);
-
-/* */
-/* Function Prototype in cmm_data_usb.c */
-/* */
-u16 RtmpUSB_WriteSubTxResource(struct rt_rtmp_adapter *pAd,
- struct rt_tx_blk *pTxBlk,
- IN BOOLEAN bIsLast, u16 *FreeNumber);
-
-u16 RtmpUSB_WriteSingleTxResource(struct rt_rtmp_adapter *pAd,
- struct rt_tx_blk *pTxBlk,
- IN BOOLEAN bIsLast,
- u16 *FreeNumber);
-
-u16 RtmpUSB_WriteFragTxResource(struct rt_rtmp_adapter *pAd,
- struct rt_tx_blk *pTxBlk,
- u8 fragNum, u16 *FreeNumber);
-
-u16 RtmpUSB_WriteMultiTxResource(struct rt_rtmp_adapter *pAd,
- struct rt_tx_blk *pTxBlk,
- u8 frameNum, u16 *FreeNumber);
-
-void RtmpUSB_FinalWriteTxResource(struct rt_rtmp_adapter *pAd,
- struct rt_tx_blk *pTxBlk,
- u16 totalMPDUSize, u16 TxIdx);
-
-void RtmpUSBDataLastTxIdx(struct rt_rtmp_adapter *pAd,
- u8 QueIdx, u16 TxIdx);
-
-void RtmpUSBDataKickOut(struct rt_rtmp_adapter *pAd,
- struct rt_tx_blk *pTxBlk, u8 QueIdx);
-
-int RtmpUSBMgmtKickOut(struct rt_rtmp_adapter *pAd,
- u8 QueIdx,
- void *pPacket,
- u8 *pSrcBufVA, u32 SrcBufLen);
-
-void RtmpUSBNullFrameKickOut(struct rt_rtmp_adapter *pAd,
- u8 QueIdx,
- u8 *pNullFrame, u32 frameLen);
-
-void RtmpUsbStaAsicForceWakeupTimeout(void *SystemSpecific1,
- void *FunctionContext,
- void *SystemSpecific2,
- void *SystemSpecific3);
-
-void RT28xxUsbStaAsicForceWakeup(struct rt_rtmp_adapter *pAd, IN BOOLEAN bFromTx);
-
-void RT28xxUsbStaAsicSleepThenAutoWakeup(struct rt_rtmp_adapter *pAd,
- u16 TbttNumToNextWakeUp);
-
-void RT28xxUsbMlmeRadioOn(struct rt_rtmp_adapter *pAd);
-
-void RT28xxUsbMlmeRadioOFF(struct rt_rtmp_adapter *pAd);
-#endif /* RTMP_MAC_USB // */
-
-void AsicTurnOffRFClk(struct rt_rtmp_adapter *pAd, u8 Channel);
-
-void AsicTurnOnRFClk(struct rt_rtmp_adapter *pAd, u8 Channel);
-
-#ifdef RTMP_TIMER_TASK_SUPPORT
-int RtmpTimerQThread(IN void *Context);
-
-struct rt_rtmp_timer_task_entry *RtmpTimerQInsert(struct rt_rtmp_adapter *pAd,
- struct rt_ralink_timer *pTimer);
-
-BOOLEAN RtmpTimerQRemove(struct rt_rtmp_adapter *pAd,
- struct rt_ralink_timer *pTimer);
-
-void RtmpTimerQExit(struct rt_rtmp_adapter *pAd);
-
-void RtmpTimerQInit(struct rt_rtmp_adapter *pAd);
-#endif /* RTMP_TIMER_TASK_SUPPORT // */
-
-void AsicStaBbpTuning(struct rt_rtmp_adapter *pAd);
-
-BOOLEAN StaAddMacTableEntry(struct rt_rtmp_adapter *pAd,
- struct rt_mac_table_entry *pEntry,
- u8 MaxSupportedRateIn500Kbps,
- struct rt_ht_capability_ie *pHtCapability,
- u8 HtCapabilityLen,
- struct rt_add_ht_info_ie *pAddHtInfo,
- u8 AddHtInfoLen, u16 CapabilityInfo);
-
-BOOLEAN AUTH_ReqSend(struct rt_rtmp_adapter *pAd,
- struct rt_mlme_queue_elem *pElem,
- struct rt_ralink_timer *pAuthTimer,
- char *pSMName,
- u16 SeqNo,
- u8 *pNewElement, unsigned long ElementLen);
-
-void RTMP_IndicateMediaState(struct rt_rtmp_adapter *pAd);
-
-void ReSyncBeaconTime(struct rt_rtmp_adapter *pAd);
-
-void RTMPSetAGCInitValue(struct rt_rtmp_adapter *pAd, u8 BandWidth);
-
-int rt28xx_close(struct net_device *dev);
-int rt28xx_open(struct net_device *dev);
-
-#define VIRTUAL_IF_INC(__pAd) ((__pAd)->VirtualIfCnt++)
-#define VIRTUAL_IF_DEC(__pAd) ((__pAd)->VirtualIfCnt--)
-#define VIRTUAL_IF_NUM(__pAd) ((__pAd)->VirtualIfCnt)
-
-#ifdef LINUX
-__inline int VIRTUAL_IF_UP(struct rt_rtmp_adapter *pAd)
-{
- if (VIRTUAL_IF_NUM(pAd) == 0) {
- if (rt28xx_open(pAd->net_dev) != 0) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("rt28xx_open return fail!\n"));
- return -1;
- }
- } else {
- }
- VIRTUAL_IF_INC(pAd);
- return 0;
-}
-
-__inline void VIRTUAL_IF_DOWN(struct rt_rtmp_adapter *pAd)
-{
- VIRTUAL_IF_DEC(pAd);
- if (VIRTUAL_IF_NUM(pAd) == 0)
- rt28xx_close(pAd->net_dev);
- return;
-}
-#endif /* LINUX // */
-
-/*
- OS Related funciton prototype definitions.
- TODO: Maybe we need to move these function prototypes to other proper place.
-*/
-int RtmpOSWrielessEventSend(struct rt_rtmp_adapter *pAd,
- u32 eventType,
- int flags,
- u8 *pSrcMac,
- u8 *pData, u32 dataLen);
-
-int RtmpOSNetDevAddrSet(struct net_device *pNetDev, u8 *pMacAddr);
-
-int RtmpOSNetDevAttach(struct net_device *pNetDev,
- struct rt_rtmp_os_netdev_op_hook *pDevOpHook);
-
-void RtmpOSNetDevClose(struct net_device *pNetDev);
-
-void RtmpOSNetDevDetach(struct net_device *pNetDev);
-
-int RtmpOSNetDevAlloc(struct net_device **pNewNetDev, u32 privDataSize);
-
-void RtmpOSNetDevFree(struct net_device *pNetDev);
-
-struct net_device *RtmpOSNetDevGetByName(struct net_device *pNetDev, char *pDevName);
-
-void RtmpOSNetDeviceRefPut(struct net_device *pNetDev);
-
-struct net_device *RtmpOSNetDevCreate(struct rt_rtmp_adapter *pAd,
- int devType,
- int devNum,
- int privMemSize, char *pNamePrefix);
-
-/*
- Task operation related function prototypes
-*/
-void RtmpOSTaskCustomize(struct rt_rtmp_os_task *pTask);
-
-int RtmpOSTaskNotifyToExit(struct rt_rtmp_os_task *pTask);
-
-int RtmpOSTaskKill(struct rt_rtmp_os_task *pTask);
-
-int RtmpOSTaskInit(struct rt_rtmp_os_task *pTask,
- char *pTaskName, void * pPriv);
-
-int RtmpOSTaskAttach(struct rt_rtmp_os_task *pTask,
- IN int (*fn) (void *), IN void *arg);
-
-/*
- File operation related function prototypes
-*/
-struct file *RtmpOSFileOpen(IN char *pPath, IN int flag, IN int mode);
-
-int RtmpOSFileClose(struct file *osfd);
-
-void RtmpOSFileSeek(struct file *osfd, IN int offset);
-
-int RtmpOSFileRead(struct file *osfd, IN char *pDataPtr, IN int readLen);
-
-int RtmpOSFileWrite(struct file *osfd, IN char *pDataPtr, IN int writeLen);
-
-#endif /* __RTMP_H__ */
diff --git a/drivers/staging/rt2860/rtmp_chip.h b/drivers/staging/rt2860/rtmp_chip.h
deleted file mode 100644
index 0adf2cd..0000000
--- a/drivers/staging/rt2860/rtmp_chip.h
+++ /dev/null
@@ -1,258 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- rtmp_chip.h
-
- Abstract:
- Ralink Wireless Chip related definition & structures
-
- Revision History:
- Who When What
- -------- ---------- ----------------------------------------------
-*/
-
-#ifndef __RTMP_CHIP_H__
-#define __RTMP_CHIP_H__
-
-#include "rtmp_type.h"
-
-#ifdef RT2860
-#include "chip/rt2860.h"
-#endif /* RT2860 // */
-#ifdef RT2870
-#include "chip/rt2870.h"
-#endif /* RT2870 // */
-#ifdef RT3070
-#include "chip/rt3070.h"
-#endif /* RT3070 // */
-#ifdef RT3090
-#include "chip/rt3090.h"
-#endif /* RT3090 // */
-
-/* We will have a cost down version which mac version is 0x3090xxxx */
-/* */
-/* RT3090A facts */
-/* */
-/* a) 2.4 GHz */
-/* b) Replacement for RT3090 */
-/* c) Internal LNA */
-/* d) Interference over channel #14 */
-/* e) New BBP features (e.g., SIG re-modulation) */
-/* */
-#define IS_RT3090A(_pAd) ((((_pAd)->MACVersion & 0xffff0000) == 0x30900000))
-
-/* We will have a cost down version which mac version is 0x3090xxxx */
-#define IS_RT3090(_pAd) ((((_pAd)->MACVersion & 0xffff0000) == 0x30710000) || (IS_RT3090A(_pAd)))
-
-#define IS_RT3070(_pAd) (((_pAd)->MACVersion & 0xffff0000) == 0x30700000)
-#define IS_RT3071(_pAd) (((_pAd)->MACVersion & 0xffff0000) == 0x30710000)
-#define IS_RT2070(_pAd) (((_pAd)->RfIcType == RFIC_2020) || ((_pAd)->EFuseTag == 0x27))
-
-#define IS_RT30xx(_pAd) (((_pAd)->MACVersion & 0xfff00000) == 0x30700000||IS_RT3090A(_pAd))
-/*#define IS_RT305X(_pAd) ((_pAd)->MACVersion == 0x28720200) */
-
-/* RT3572, 3592, 3562, 3062 share the same MAC version */
-#define IS_RT3572(_pAd) (((_pAd)->MACVersion & 0xffff0000) == 0x35720000)
-#define IS_VERSION_BEFORE_F(_pAd) (((_pAd)->MACVersion&0xffff) <= 0x0211)
-/* F version is 0x0212, E version is 0x0211. 309x can save more power after F version. */
-#define IS_VERSION_AFTER_F(_pAd) ((((_pAd)->MACVersion&0xffff) >= 0x0212) || (((_pAd)->b3090ESpecialChip == TRUE)))
-/* */
-/* RT3390 facts */
-/* */
-/* a) Base on RT3090 (RF IC: RT3020) */
-/* b) 2.4 GHz */
-/* c) 1x1 */
-/* d) Single chip */
-/* e) Internal components: PA and LNA */
-/* */
-/*RT3390,RT3370 */
-#define IS_RT3390(_pAd) (((_pAd)->MACVersion & 0xFFFF0000) == 0x33900000)
-
-/* ------------------------------------------------------ */
-/* PCI registers - base address 0x0000 */
-/* ------------------------------------------------------ */
-#define CHIP_PCI_CFG 0x0000
-#define CHIP_PCI_EECTRL 0x0004
-#define CHIP_PCI_MCUCTRL 0x0008
-
-#define OPT_14 0x114
-
-#define RETRY_LIMIT 10
-
-/* ------------------------------------------------------ */
-/* BBP & RF definition */
-/* ------------------------------------------------------ */
-#define BUSY 1
-#define IDLE 0
-
-/*------------------------------------------------------------------------- */
-/* EEPROM definition */
-/*------------------------------------------------------------------------- */
-#define EEDO 0x08
-#define EEDI 0x04
-#define EECS 0x02
-#define EESK 0x01
-#define EERL 0x80
-
-#define EEPROM_WRITE_OPCODE 0x05
-#define EEPROM_READ_OPCODE 0x06
-#define EEPROM_EWDS_OPCODE 0x10
-#define EEPROM_EWEN_OPCODE 0x13
-
-#define NUM_EEPROM_BBP_PARMS 19 /* Include NIC Config 0, 1, CR, TX ALC step, BBPs */
-#define NUM_EEPROM_TX_G_PARMS 7
-#define EEPROM_NIC1_OFFSET 0x34 /* The address is from NIC config 0, not BBP register ID */
-#define EEPROM_NIC2_OFFSET 0x36 /* The address is from NIC config 0, not BBP register ID */
-#define EEPROM_BBP_BASE_OFFSET 0xf0 /* The address is from NIC config 0, not BBP register ID */
-#define EEPROM_G_TX_PWR_OFFSET 0x52
-#define EEPROM_G_TX2_PWR_OFFSET 0x60
-#define EEPROM_LED1_OFFSET 0x3c
-#define EEPROM_LED2_OFFSET 0x3e
-#define EEPROM_LED3_OFFSET 0x40
-#define EEPROM_LNA_OFFSET 0x44
-#define EEPROM_RSSI_BG_OFFSET 0x46
-#define EEPROM_TXMIXER_GAIN_2_4G 0x48
-#define EEPROM_RSSI_A_OFFSET 0x4a
-#define EEPROM_TXMIXER_GAIN_5G 0x4c
-#define EEPROM_DEFINE_MAX_TXPWR 0x4e
-#define EEPROM_TXPOWER_BYRATE_20MHZ_2_4G 0xde /* 20MHZ 2.4G tx power. */
-#define EEPROM_TXPOWER_BYRATE_40MHZ_2_4G 0xee /* 40MHZ 2.4G tx power. */
-#define EEPROM_TXPOWER_BYRATE_20MHZ_5G 0xfa /* 20MHZ 5G tx power. */
-#define EEPROM_TXPOWER_BYRATE_40MHZ_5G 0x10a /* 40MHZ 5G tx power. */
-#define EEPROM_A_TX_PWR_OFFSET 0x78
-#define EEPROM_A_TX2_PWR_OFFSET 0xa6
-/*#define EEPROM_Japan_TX_PWR_OFFSET 0x90 // 802.11j */
-/*#define EEPROM_Japan_TX2_PWR_OFFSET 0xbe */
-/*#define EEPROM_TSSI_REF_OFFSET 0x54 */
-/*#define EEPROM_TSSI_DELTA_OFFSET 0x24 */
-/*#define EEPROM_CCK_TX_PWR_OFFSET 0x62 */
-/*#define EEPROM_CALIBRATE_OFFSET 0x7c */
-#define EEPROM_VERSION_OFFSET 0x02
-#define EEPROM_FREQ_OFFSET 0x3a
-#define EEPROM_TXPOWER_BYRATE 0xde /* 20MHZ power. */
-#define EEPROM_TXPOWER_DELTA 0x50 /* 20MHZ AND 40 MHZ use different power. This is delta in 40MHZ. */
-#define VALID_EEPROM_VERSION 1
-
-/*
- * EEPROM operation related marcos
- */
-#define RT28xx_EEPROM_READ16(_pAd, _offset, _value) \
- (_pAd)->chipOps.eeread((struct rt_rtmp_adapter *)(_pAd), (u16)(_offset), (u16 *)&(_value))
-
-/* ------------------------------------------------------------------- */
-/* E2PROM data layout */
-/* ------------------------------------------------------------------- */
-
-/* */
-/* MCU_LEDCS: MCU LED Control Setting. */
-/* */
-typedef union _MCU_LEDCS_STRUC {
- struct {
- u8 LedMode:7;
- u8 Polarity:1;
- } field;
- u8 word;
-} MCU_LEDCS_STRUC, *PMCU_LEDCS_STRUC;
-
-/* */
-/* EEPROM antenna select format */
-/* */
-typedef union _EEPROM_ANTENNA_STRUC {
- struct {
- u16 RxPath:4; /* 1: 1R, 2: 2R, 3: 3R */
- u16 TxPath:4; /* 1: 1T, 2: 2T */
- u16 RfIcType:4; /* see E2PROM document */
- u16 Rsv:4;
- } field;
- u16 word;
-} EEPROM_ANTENNA_STRUC, *PEEPROM_ANTENNA_STRUC;
-
-typedef union _EEPROM_NIC_CINFIG2_STRUC {
- struct {
- u16 HardwareRadioControl:1; /* 1:enable, 0:disable */
- u16 DynamicTxAgcControl:1; /* */
- u16 ExternalLNAForG:1; /* */
- u16 ExternalLNAForA:1; /* external LNA enable for 2.4G */
- u16 CardbusAcceleration:1; /* ! NOTE: 0 - enable, 1 - disable */
- u16 BW40MSidebandForG:1;
- u16 BW40MSidebandForA:1;
- u16 EnableWPSPBC:1; /* WPS PBC Control bit */
- u16 BW40MAvailForG:1; /* 0:enable, 1:disable */
- u16 BW40MAvailForA:1; /* 0:enable, 1:disable */
- u16 Rsv1:1; /* must be 0 */
- u16 AntDiversity:1; /* Antenna diversity */
- u16 Rsv2:3; /* must be 0 */
- u16 DACTestBit:1; /* control if driver should patch the DAC issue */
- } field;
- u16 word;
-} EEPROM_NIC_CONFIG2_STRUC, *PEEPROM_NIC_CONFIG2_STRUC;
-
-/* */
-/* TX_PWR Value valid range 0xFA(-6) ~ 0x24(36) */
-/* */
-typedef union _EEPROM_TX_PWR_STRUC {
- struct {
- char Byte0; /* Low Byte */
- char Byte1; /* High Byte */
- } field;
- u16 word;
-} EEPROM_TX_PWR_STRUC, *PEEPROM_TX_PWR_STRUC;
-
-typedef union _EEPROM_VERSION_STRUC {
- struct {
- u8 FaeReleaseNumber; /* Low Byte */
- u8 Version; /* High Byte */
- } field;
- u16 word;
-} EEPROM_VERSION_STRUC, *PEEPROM_VERSION_STRUC;
-
-typedef union _EEPROM_LED_STRUC {
- struct {
- u16 PolarityRDY_G:1; /* Polarity RDY_G setting. */
- u16 PolarityRDY_A:1; /* Polarity RDY_A setting. */
- u16 PolarityACT:1; /* Polarity ACT setting. */
- u16 PolarityGPIO_0:1; /* Polarity GPIO#0 setting. */
- u16 PolarityGPIO_1:1; /* Polarity GPIO#1 setting. */
- u16 PolarityGPIO_2:1; /* Polarity GPIO#2 setting. */
- u16 PolarityGPIO_3:1; /* Polarity GPIO#3 setting. */
- u16 PolarityGPIO_4:1; /* Polarity GPIO#4 setting. */
- u16 LedMode:5; /* Led mode. */
- u16 Rsvd:3; /* Reserved */
- } field;
- u16 word;
-} EEPROM_LED_STRUC, *PEEPROM_LED_STRUC;
-
-typedef union _EEPROM_TXPOWER_DELTA_STRUC {
- struct {
- u8 DeltaValue:6; /* Tx Power dalta value (MAX=4) */
- u8 Type:1; /* 1: plus the delta value, 0: minus the delta value */
- u8 TxPowerEnable:1; /* Enable */
- } field;
- u8 value;
-} EEPROM_TXPOWER_DELTA_STRUC, *PEEPROM_TXPOWER_DELTA_STRUC;
-
-#endif /* __RTMP_CHIP_H__ // */
diff --git a/drivers/staging/rt2860/rtmp_ckipmic.h b/drivers/staging/rt2860/rtmp_ckipmic.h
deleted file mode 100644
index 6ff935d..0000000
--- a/drivers/staging/rt2860/rtmp_ckipmic.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- rtmp_ckipmic.h
-
- Abstract:
-
- Revision History:
- Who When What
- -------- ---------- ----------------------------------------------
- Name Date Modification logs
-*/
-#ifndef __RTMP_CKIPMIC_H__
-#define __RTMP_CKIPMIC_H__
-
-struct rt_mic_context {
- /* --- MMH context */
- u8 CK[16]; /* the key */
- u8 coefficient[16]; /* current aes counter mode coefficients */
- unsigned long long accum; /* accumulated mic, reduced to u32 in final() */
- u32 position; /* current position (byte offset) in message */
- u8 part[4]; /* for conversion of message to u32 for mmh */
-};
-
-void xor_128(u8 *a, u8 *b, u8 *out);
-
-u8 RTMPCkipSbox(u8 a);
-
-void xor_32(u8 *a, u8 *b, u8 *out);
-
-void next_key(u8 *key, int round);
-
-void byte_sub(u8 *in, u8 *out);
-
-void shift_row(u8 *in, u8 *out);
-
-void mix_column(u8 *in, u8 *out);
-
-#endif /*__RTMP_CKIPMIC_H__ */
diff --git a/drivers/staging/rt2860/rtmp_def.h b/drivers/staging/rt2860/rtmp_def.h
deleted file mode 100644
index 6ac617e..0000000
--- a/drivers/staging/rt2860/rtmp_def.h
+++ /dev/null
@@ -1,1427 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- rtmp_def.h
-
- Abstract:
- Miniport related definition header
-
- Revision History:
- Who When What
- -------- ---------- ----------------------------------------------
- Paul Lin 08-01-2002 created
- John Chang 08-05-2003 add definition for 11g & other drafts
- Justin P. Mattock 11/07/2010 Fix some typos
-*/
-#ifndef __RTMP_DEF_H__
-#define __RTMP_DEF_H__
-
-#include "oid.h"
-
-/* */
-/* Debug information verbosity: lower values indicate higher urgency */
-/* */
-#define RT_DEBUG_OFF 0
-#define RT_DEBUG_ERROR 1
-#define RT_DEBUG_WARN 2
-#define RT_DEBUG_TRACE 3
-#define RT_DEBUG_INFO 4
-#define RT_DEBUG_LOUD 5
-
-#define NIC_TAG ((unsigned long)'0682')
-#define NIC_DBG_char ("**RT28xx**")
-
-#ifdef RTMP_MAC_USB
-#define TX_RING_SIZE 8 /* 1 */
-#define PRIO_RING_SIZE 8
-#define MGMT_RING_SIZE 32 /* PRIO_RING_SIZE */
-#define RX_RING_SIZE 8
-#define MAX_TX_PROCESS 4
-#define LOCAL_TXBUF_SIZE 2048
-#endif /* RTMP_MAC_USB // */
-
-/*#define PACKED */
-
-#define RALINK_2883_VERSION ((u32)0x28830300)
-#define RALINK_2880E_VERSION ((u32)0x28720200)
-#define RALINK_3070_VERSION ((u32)0x30700200)
-
-#define MAX_RX_PKT_LEN 1520
-
-/* */
-/* Entry number for each DMA descriptor ring */
-/* */
-
-#ifdef RTMP_MAC_PCI
-#define TX_RING_SIZE 64 /*64 */
-#define MGMT_RING_SIZE 128
-#define RX_RING_SIZE 128 /*64 */
-#define MAX_TX_PROCESS TX_RING_SIZE /*8 */
-#define MAX_DMA_DONE_PROCESS TX_RING_SIZE
-#define MAX_TX_DONE_PROCESS TX_RING_SIZE /*8 */
-#define LOCAL_TXBUF_SIZE 2
-#endif /* RTMP_MAC_PCI // */
-
-#define MAX_RX_PROCESS 128 /*64 //32 */
-#define NUM_OF_LOCAL_TXBUF 2
-#define TXD_SIZE 16
-#define TXWI_SIZE 16
-#define RXD_SIZE 16
-#define RXWI_SIZE 16
-/* TXINFO_SIZE + TXWI_SIZE + 802.11 Header Size + AMSDU sub frame header */
-#define TX_DMA_1ST_BUFFER_SIZE 96 /* only the 1st physical buffer is pre-allocated */
-#define MGMT_DMA_BUFFER_SIZE 1536 /*2048 */
-#define RX_BUFFER_AGGRESIZE 3840 /*3904 //3968 //4096 //2048 //4096 */
-#define RX_BUFFER_NORMSIZE 3840 /*3904 //3968 //4096 //2048 //4096 */
-#define TX_BUFFER_NORMSIZE RX_BUFFER_NORMSIZE
-#define MAX_FRAME_SIZE 2346 /* Maximum 802.11 frame size */
-#define MAX_AGGREGATION_SIZE 3840 /*3904 //3968 //4096 */
-#define MAX_NUM_OF_TUPLE_CACHE 2
-#define MAX_MCAST_LIST_SIZE 32
-#define MAX_LEN_OF_VENDOR_DESC 64
-/*#define MAX_SIZE_OF_MCAST_PSQ (NUM_OF_LOCAL_TXBUF >> 2) // AP won't spend more than 1/4 of total buffers on M/BCAST PSQ */
-#define MAX_SIZE_OF_MCAST_PSQ 32
-
-#define MAX_RX_PROCESS_CNT (RX_RING_SIZE)
-
-/*
- WMM Note: If memory of your system is not much, please reduce the definition;
- or when you do WMM test, the queue for low priority AC will be full, i.e.
- TX_RING_SIZE + MAX_PACKETS_IN_QUEUE packets for the AC will be buffered in
- WLAN, maybe no packet buffers can get into the Ethernet driver.
-
- Sometimes no packet buffer can be get into the Ethernet driver, the system will
- send flow control packet to the sender to slow down its sending rate.
- So no WMM can be seen in the air.
-*/
-
-/*
- Need to use 64 in vxworks for test case WMM A5-T07
- Two dnlink (10Mbps) from a WMM station to a non-WMM station.
- If use 256, queue is not enough.
- And in rt_main_end.c, clConfig.clNum = RX_RING_SIZE * 3; is changed to
- clConfig.clNum = RX_RING_SIZE * 4;
-*/
-/* TODO: For VxWorks the size is 256. Shall we change the value as 256 for all OS? */
-#define MAX_PACKETS_IN_QUEUE (512) /*(512) // to pass WMM A5-WPAPSK */
-
-#define MAX_PACKETS_IN_MCAST_PS_QUEUE 32
-#define MAX_PACKETS_IN_PS_QUEUE 128 /*32 */
-#define WMM_NUM_OF_AC 4 /* AC0, AC1, AC2, and AC3 */
-
-#ifdef RTMP_EFUSE_SUPPORT
-/*2008/09/11:KH add to support efuse<-- */
-#define MAX_EEPROM_BIN_FILE_SIZE 1024
-#define EFUSE_BUFFER_PATH "/tmp/RT30xxEEPROM.bin"
-/*2008/09/11:KH add to support efuse--> */
-#endif /* RTMP_EFUSE_SUPPORT // */
-
-/* RxFilter */
-#define STANORMAL 0x17f97
-#define APNORMAL 0x15f97
-#define PSPXLINK 0x17f93
-/* */
-/* struct rt_rtmp_adapter flags */
-/* */
-#define fRTMP_ADAPTER_MAP_REGISTER 0x00000001
-#define fRTMP_ADAPTER_INTERRUPT_IN_USE 0x00000002
-#define fRTMP_ADAPTER_HARDWARE_ERROR 0x00000004
-#define fRTMP_ADAPTER_SCATTER_GATHER 0x00000008
-#define fRTMP_ADAPTER_SEND_PACKET_ERROR 0x00000010
-#define fRTMP_ADAPTER_MLME_RESET_IN_PROGRESS 0x00000020
-#define fRTMP_ADAPTER_HALT_IN_PROGRESS 0x00000040
-#define fRTMP_ADAPTER_RESET_IN_PROGRESS 0x00000080
-#define fRTMP_ADAPTER_NIC_NOT_EXIST 0x00000100
-#define fRTMP_ADAPTER_TX_RING_ALLOCATED 0x00000200
-#define fRTMP_ADAPTER_REMOVE_IN_PROGRESS 0x00000400
-#define fRTMP_ADAPTER_MIMORATE_INUSED 0x00000800
-#define fRTMP_ADAPTER_RX_RING_ALLOCATED 0x00001000
-#define fRTMP_ADAPTER_INTERRUPT_ACTIVE 0x00002000
-#define fRTMP_ADAPTER_BSS_SCAN_IN_PROGRESS 0x00004000
-#define fRTMP_ADAPTER_REASSOC_IN_PROGRESS 0x00008000
-#define fRTMP_ADAPTER_MEDIA_STATE_PENDING 0x00010000
-#define fRTMP_ADAPTER_RADIO_OFF 0x00020000
-#define fRTMP_ADAPTER_BULKOUT_RESET 0x00040000
-#define fRTMP_ADAPTER_BULKIN_RESET 0x00080000
-#define fRTMP_ADAPTER_RDG_ACTIVE 0x00100000
-#define fRTMP_ADAPTER_DYNAMIC_BE_TXOP_ACTIVE 0x00200000
-#define fRTMP_ADAPTER_SCAN_2040 0x04000000
-#define fRTMP_ADAPTER_RADIO_MEASUREMENT 0x08000000
-
-#define fRTMP_ADAPTER_START_UP 0x10000000 /*Device already initialized and enabled Tx/Rx. */
-#define fRTMP_ADAPTER_MEDIA_STATE_CHANGE 0x20000000
-#define fRTMP_ADAPTER_IDLE_RADIO_OFF 0x40000000
-
-/* */
-/* STA operation status flags */
-/* */
-#define fOP_STATUS_INFRA_ON 0x00000001
-#define fOP_STATUS_ADHOC_ON 0x00000002
-#define fOP_STATUS_BG_PROTECTION_INUSED 0x00000004
-#define fOP_STATUS_SHORT_SLOT_INUSED 0x00000008
-#define fOP_STATUS_SHORT_PREAMBLE_INUSED 0x00000010
-#define fOP_STATUS_RECEIVE_DTIM 0x00000020
-#define fOP_STATUS_MEDIA_STATE_CONNECTED 0x00000080
-#define fOP_STATUS_WMM_INUSED 0x00000100
-#define fOP_STATUS_AGGREGATION_INUSED 0x00000200
-#define fOP_STATUS_DOZE 0x00000400 /* debug purpose */
-#define fOP_STATUS_PIGGYBACK_INUSED 0x00000800 /* piggy-back, and aggregation */
-#define fOP_STATUS_APSD_INUSED 0x00001000
-#define fOP_STATUS_TX_AMSDU_INUSED 0x00002000
-#define fOP_STATUS_MAX_RETRY_ENABLED 0x00004000
-#define fOP_STATUS_WAKEUP_NOW 0x00008000
-#define fOP_STATUS_PCIE_DEVICE 0x00020000
-#define fOP_STATUS_ADVANCE_POWER_SAVE_PCIE_DEVICE fOP_STATUS_PCIE_DEVICE
-
-/* */
-/* struct rt_rtmp_adapter PSFlags : related to advanced power save. */
-/* */
-/* Indicate whether driver can go to sleep mode from now. This flag is useful AFTER link up */
-#define fRTMP_PS_CAN_GO_SLEEP 0x00000001
-/* Indicate whether driver has issue a LinkControl command to PCIe L1 */
-#define fRTMP_PS_SET_PCI_CLK_OFF_COMMAND 0x00000002
-/* Indicate driver should disable kick off hardware to send packets from now. */
-#define fRTMP_PS_DISABLE_TX 0x00000004
-/* Indicate driver should IMMEDIATELY go to sleep after receiving AP's beacon in which doesn't indicate unicate nor multicast packets for me */
-/* This flag is used ONLY in RTMPHandleRxDoneInterrupt routine. */
-#define fRTMP_PS_GO_TO_SLEEP_NOW 0x00000008
-#define fRTMP_PS_TOGGLE_L1 0x00000010 /* Use Toggle L1 mechanism for rt28xx PCIe */
-
-#ifdef RT3090
-#define WAKE_MCU_CMD 0x31
-#define SLEEP_MCU_CMD 0x30
-#define RFOFF_MCU_CMD 0x35
-#endif /* RT3090 // */
-
-#define CCKSETPROTECT 0x1
-#define OFDMSETPROTECT 0x2
-#define MM20SETPROTECT 0x4
-#define MM40SETPROTECT 0x8
-#define GF20SETPROTECT 0x10
-#define GR40SETPROTECT 0x20
-#define ALLN_SETPROTECT (GR40SETPROTECT | GF20SETPROTECT | MM40SETPROTECT | MM20SETPROTECT)
-
-/* */
-/* AP's client table operation status flags */
-/* */
-#define fCLIENT_STATUS_WMM_CAPABLE 0x00000001 /* CLIENT can parse QOS DATA frame */
-#define fCLIENT_STATUS_AGGREGATION_CAPABLE 0x00000002 /* CLIENT can receive Ralink's proprietary TX aggregation frame */
-#define fCLIENT_STATUS_PIGGYBACK_CAPABLE 0x00000004 /* CLIENT support piggy-back */
-#define fCLIENT_STATUS_AMSDU_INUSED 0x00000008
-#define fCLIENT_STATUS_SGI20_CAPABLE 0x00000010
-#define fCLIENT_STATUS_SGI40_CAPABLE 0x00000020
-#define fCLIENT_STATUS_TxSTBC_CAPABLE 0x00000040
-#define fCLIENT_STATUS_RxSTBC_CAPABLE 0x00000080
-#define fCLIENT_STATUS_HTC_CAPABLE 0x00000100
-#define fCLIENT_STATUS_RDG_CAPABLE 0x00000200
-#define fCLIENT_STATUS_MCSFEEDBACK_CAPABLE 0x00000400
-#define fCLIENT_STATUS_APSD_CAPABLE 0x00000800 /* UAPSD STATION */
-
-#define fCLIENT_STATUS_RALINK_CHIPSET 0x00100000
-/* */
-/* STA configuration flags */
-/* */
-
-/* 802.11n Operating Mode Definition. 0-3 also used in ASICUPdateProtect switch case */
-#define HT_NO_PROTECT 0
-#define HT_LEGACY_PROTECT 1
-#define HT_40_PROTECT 2
-#define HT_2040_PROTECT 3
-#define HT_RTSCTS_6M 7
-/*following is our own definition in order to turn on our ASIC protection register in INFRASTRUCTURE. */
-#define HT_ATHEROS 8 /* rt2860c has problem with atheros chip. we need to turn on RTS/CTS . */
-#define HT_FORCERTSCTS 9 /* Force turn on RTS/CTS first. then go to evaluate if this force RTS is necessary. */
-
-/* */
-/* RX Packet Filter control flags. Apply on pAd->PacketFilter */
-/* */
-#define fRX_FILTER_ACCEPT_DIRECT NDIS_PACKET_TYPE_DIRECTED
-#define fRX_FILTER_ACCEPT_MULTICAST NDIS_PACKET_TYPE_MULTICAST
-#define fRX_FILTER_ACCEPT_BROADCAST NDIS_PACKET_TYPE_BROADCAST
-#define fRX_FILTER_ACCEPT_ALL_MULTICAST NDIS_PACKET_TYPE_ALL_MULTICAST
-#define fRX_FILTER_ACCEPT_PROMISCUOUS NDIS_PACKET_TYPE_PROMISCUOUS
-
-/* */
-/* Error code section */
-/* */
-/* NDIS_ERROR_CODE_ADAPTER_NOT_FOUND */
-#define ERRLOG_READ_PCI_SLOT_FAILED 0x00000101L
-#define ERRLOG_WRITE_PCI_SLOT_FAILED 0x00000102L
-#define ERRLOG_VENDOR_DEVICE_NOMATCH 0x00000103L
-
-/* NDIS_ERROR_CODE_ADAPTER_DISABLED */
-#define ERRLOG_BUS_MASTER_DISABLED 0x00000201L
-
-/* NDIS_ERROR_CODE_UNSUPPORTED_CONFIGURATION */
-#define ERRLOG_INVALID_SPEED_DUPLEX 0x00000301L
-#define ERRLOG_SET_SECONDARY_FAILED 0x00000302L
-
-/* NDIS_ERROR_CODE_OUT_OF_RESOURCES */
-#define ERRLOG_OUT_OF_MEMORY 0x00000401L
-#define ERRLOG_OUT_OF_SHARED_MEMORY 0x00000402L
-#define ERRLOG_OUT_OF_MAP_REGISTERS 0x00000403L
-#define ERRLOG_OUT_OF_BUFFER_POOL 0x00000404L
-#define ERRLOG_OUT_OF_NDIS_BUFFER 0x00000405L
-#define ERRLOG_OUT_OF_PACKET_POOL 0x00000406L
-#define ERRLOG_OUT_OF_NDIS_PACKET 0x00000407L
-#define ERRLOG_OUT_OF_LOOKASIDE_MEMORY 0x00000408L
-
-/* NDIS_ERROR_CODE_HARDWARE_FAILURE */
-#define ERRLOG_SELFTEST_FAILED 0x00000501L
-#define ERRLOG_INITIALIZE_ADAPTER 0x00000502L
-#define ERRLOG_REMOVE_MINIPORT 0x00000503L
-
-/* NDIS_ERROR_CODE_RESOURCE_CONFLICT */
-#define ERRLOG_MAP_IO_SPACE 0x00000601L
-#define ERRLOG_QUERY_ADAPTER_RESOURCES 0x00000602L
-#define ERRLOG_NO_IO_RESOURCE 0x00000603L
-#define ERRLOG_NO_INTERRUPT_RESOURCE 0x00000604L
-#define ERRLOG_NO_MEMORY_RESOURCE 0x00000605L
-
-/* WDS definition */
-#define MAX_WDS_ENTRY 4
-#define WDS_PAIRWISE_KEY_OFFSET 60 /* WDS links use pairwise key#60 ~ 63 in ASIC pairwise key table */
-
-#define WDS_DISABLE_MODE 0
-#define WDS_RESTRICT_MODE 1
-#define WDS_BRIDGE_MODE 2
-#define WDS_REPEATER_MODE 3
-#define WDS_LAZY_MODE 4
-
-#define MAX_MESH_NUM 0
-
-#define MAX_APCLI_NUM 0
-
-#define MAX_MBSSID_NUM 1
-#ifdef MBSS_SUPPORT
-#undef MAX_MBSSID_NUM
-#define MAX_MBSSID_NUM (8 - MAX_MESH_NUM - MAX_APCLI_NUM)
-#endif /* MBSS_SUPPORT // */
-
-/* sanity check for apidx */
-#define MBSS_MR_APIDX_SANITY_CHECK(apidx) \
- { if (apidx > MAX_MBSSID_NUM) { \
- DBGPRINT(RT_DEBUG_ERROR, ("%s> Error! apidx = %d > MAX_MBSSID_NUM!\n", __func__, apidx)); \
- apidx = MAIN_MBSSID; } }
-
-#define VALID_WCID(_wcid) ((_wcid) > 0 && (_wcid) < MAX_LEN_OF_MAC_TABLE )
-
-#define MAIN_MBSSID 0
-#define FIRST_MBSSID 1
-
-#define MAX_BEACON_SIZE 512
-/* If the MAX_MBSSID_NUM is larger than 6, */
-/* it shall reserve some WCID space(wcid 222~253) for beacon frames. */
-/* - these wcid 238~253 are reserved for beacon#6(ra6). */
-/* - these wcid 222~237 are reserved for beacon#7(ra7). */
-#if defined(MAX_MBSSID_NUM) && (MAX_MBSSID_NUM == 8)
-#define HW_RESERVED_WCID 222
-#elif defined(MAX_MBSSID_NUM) && (MAX_MBSSID_NUM == 7)
-#define HW_RESERVED_WCID 238
-#else
-#define HW_RESERVED_WCID 255
-#endif
-
-/* Then dedicate wcid of DFS and Carrier-Sense. */
-#define DFS_CTS_WCID (HW_RESERVED_WCID - 1)
-#define CS_CTS_WCID (HW_RESERVED_WCID - 2)
-#define LAST_SPECIFIC_WCID (HW_RESERVED_WCID - 2)
-
-/* If MAX_MBSSID_NUM is 8, the maximum available wcid for the associated STA is 211. */
-/* If MAX_MBSSID_NUM is 7, the maximum available wcid for the associated STA is 228. */
-#define MAX_AVAILABLE_CLIENT_WCID (LAST_SPECIFIC_WCID - MAX_MBSSID_NUM - 1)
-
-/* TX need WCID to find Cipher Key */
-/* these wcid 212 ~ 219 are reserved for bc/mc packets if MAX_MBSSID_NUM is 8. */
-#define GET_GroupKey_WCID(__wcid, __bssidx) \
- { \
- __wcid = LAST_SPECIFIC_WCID - (MAX_MBSSID_NUM) + __bssidx; \
- }
-
-#define IsGroupKeyWCID(__wcid) (((__wcid) < LAST_SPECIFIC_WCID) && ((__wcid) >= (LAST_SPECIFIC_WCID - (MAX_MBSSID_NUM))))
-
-/* definition to support multiple BSSID */
-#define BSS0 0
-#define BSS1 1
-#define BSS2 2
-#define BSS3 3
-#define BSS4 4
-#define BSS5 5
-#define BSS6 6
-#define BSS7 7
-
-/*============================================================ */
-/* Length definitions */
-#define PEER_KEY_NO 2
-#define MAC_ADDR_LEN 6
-#define TIMESTAMP_LEN 8
-#define MAX_LEN_OF_SUPPORTED_RATES MAX_LENGTH_OF_SUPPORT_RATES /* 1, 2, 5.5, 11, 6, 9, 12, 18, 24, 36, 48, 54 */
-#define MAX_LEN_OF_KEY 32 /* 32 octets == 256 bits, Redefine for WPA */
-#define MAX_NUM_OF_CHANNELS MAX_NUM_OF_CHS /* 14 channels @2.4G + 12@UNII + 4 @MMAC + 11 @HiperLAN2 + 7 @Japan + 1 as NULL termination */
-#define MAX_NUM_OF_11JCHANNELS 20 /* 14 channels @2.4G + 12@UNII + 4 @MMAC + 11 @HiperLAN2 + 7 @Japan + 1 as NULL termination */
-#define MAX_LEN_OF_SSID 32
-#define CIPHER_TEXT_LEN 128
-#define HASH_TABLE_SIZE 256
-#define MAX_VIE_LEN 1024 /* New for WPA cipher suite variable IE sizes. */
-#define MAX_SUPPORT_MCS 32
-#define MAX_NUM_OF_BBP_LATCH 140
-
-/*============================================================ */
-/* ASIC WCID Table definition. */
-/*============================================================ */
-#define BSSID_WCID 1 /* in infra mode, always put bssid with this WCID */
-#define MCAST_WCID 0x0
-#define BSS0Mcast_WCID 0x0
-#define BSS1Mcast_WCID 0xf8
-#define BSS2Mcast_WCID 0xf9
-#define BSS3Mcast_WCID 0xfa
-#define BSS4Mcast_WCID 0xfb
-#define BSS5Mcast_WCID 0xfc
-#define BSS6Mcast_WCID 0xfd
-#define BSS7Mcast_WCID 0xfe
-#define RESERVED_WCID 0xff
-
-#define MAX_NUM_OF_ACL_LIST MAX_NUMBER_OF_ACL
-
-#define MAX_LEN_OF_MAC_TABLE MAX_NUMBER_OF_MAC /* if MAX_MBSSID_NUM is 8, this value can't be larger than 211 */
-
-#if MAX_LEN_OF_MAC_TABLE>MAX_AVAILABLE_CLIENT_WCID
-#error MAX_LEN_OF_MAC_TABLE can not be larger than MAX_AVAILABLE_CLIENT_WCID!
-#endif
-
-#define MAX_NUM_OF_WDS_LINK_PERBSSID 3
-#define MAX_NUM_OF_WDS_LINK (MAX_NUM_OF_WDS_LINK_PERBSSID*MAX_MBSSID_NUM)
-#define MAX_NUM_OF_EVENT MAX_NUMBER_OF_EVENT
-#define WDS_LINK_START_WCID (MAX_LEN_OF_MAC_TABLE-1)
-
-#define NUM_OF_TID 8
-#define MAX_AID_BA 4
-#define MAX_LEN_OF_BA_REC_TABLE ((NUM_OF_TID * MAX_LEN_OF_MAC_TABLE)/2) /* (NUM_OF_TID*MAX_AID_BA + 32) //Block ACK recipient */
-#define MAX_LEN_OF_BA_ORI_TABLE ((NUM_OF_TID * MAX_LEN_OF_MAC_TABLE)/2) /* (NUM_OF_TID*MAX_AID_BA + 32) // Block ACK originator */
-#define MAX_LEN_OF_BSS_TABLE 64
-#define MAX_REORDERING_MPDU_NUM 512
-
-/* key related definitions */
-#define SHARE_KEY_NUM 4
-#define MAX_LEN_OF_SHARE_KEY 16 /* byte count */
-#define MAX_LEN_OF_PEER_KEY 16 /* byte count */
-#define PAIRWISE_KEY_NUM 64 /* in MAC ASIC pairwise key table */
-#define GROUP_KEY_NUM 4
-#define PMK_LEN 32
-#define WDS_PAIRWISE_KEY_OFFSET 60 /* WDS links uses pairwise key#60 ~ 63 in ASIC pairwise key table */
-#define PMKID_NO 4 /* Number of PMKID saved supported */
-#define MAX_LEN_OF_MLME_BUFFER 2048
-
-/* power status related definitions */
-#define PWR_ACTIVE 0
-#define PWR_SAVE 1
-#define PWR_MMPS 2 /*MIMO power save */
-
-/* Auth and Assoc mode related definitions */
-#define AUTH_MODE_OPEN 0x00
-#define AUTH_MODE_KEY 0x01
-
-/* BSS Type definitions */
-#define BSS_ADHOC 0 /* = Ndis802_11IBSS */
-#define BSS_INFRA 1 /* = Ndis802_11Infrastructure */
-#define BSS_ANY 2 /* = Ndis802_11AutoUnknown */
-#define BSS_MONITOR 3 /* = Ndis802_11Monitor */
-
-/* Reason code definitions */
-#define REASON_RESERVED 0
-#define REASON_UNSPECIFY 1
-#define REASON_NO_longER_VALID 2
-#define REASON_DEAUTH_STA_LEAVING 3
-#define REASON_DISASSOC_INACTIVE 4
-#define REASON_DISASSPC_AP_UNABLE 5
-#define REASON_CLS2ERR 6
-#define REASON_CLS3ERR 7
-#define REASON_DISASSOC_STA_LEAVING 8
-#define REASON_STA_REQ_ASSOC_NOT_AUTH 9
-#define REASON_INVALID_IE 13
-#define REASON_MIC_FAILURE 14
-#define REASON_4_WAY_TIMEOUT 15
-#define REASON_GROUP_KEY_HS_TIMEOUT 16
-#define REASON_IE_DIFFERENT 17
-#define REASON_MCIPHER_NOT_VALID 18
-#define REASON_UCIPHER_NOT_VALID 19
-#define REASON_AKMP_NOT_VALID 20
-#define REASON_UNSUPPORT_RSNE_VER 21
-#define REASON_INVALID_RSNE_CAP 22
-#define REASON_8021X_AUTH_FAIL 23
-#define REASON_CIPHER_SUITE_REJECTED 24
-#define REASON_DECLINED 37
-
-#define REASON_QOS_UNSPECIFY 32
-#define REASON_QOS_LACK_BANDWIDTH 33
-#define REASON_POOR_CHANNEL_CONDITION 34
-#define REASON_QOS_OUTSIDE_TXOP_LIMITION 35
-#define REASON_QOS_QSTA_LEAVING_QBSS 36
-#define REASON_QOS_UNWANTED_MECHANISM 37
-#define REASON_QOS_MECH_SETUP_REQUIRED 38
-#define REASON_QOS_REQUEST_TIMEOUT 39
-#define REASON_QOS_CIPHER_NOT_SUPPORT 45
-
-/* Status code definitions */
-#define MLME_SUCCESS 0
-#define MLME_UNSPECIFY_FAIL 1
-#define MLME_CANNOT_SUPPORT_CAP 10
-#define MLME_REASSOC_DENY_ASSOC_EXIST 11
-#define MLME_ASSOC_DENY_OUT_SCOPE 12
-#define MLME_ALG_NOT_SUPPORT 13
-#define MLME_SEQ_NR_OUT_OF_SEQUENCE 14
-#define MLME_REJ_CHALLENGE_FAILURE 15
-#define MLME_REJ_TIMEOUT 16
-#define MLME_ASSOC_REJ_UNABLE_HANDLE_STA 17
-#define MLME_ASSOC_REJ_DATA_RATE 18
-
-#define MLME_ASSOC_REJ_NO_EXT_RATE 22
-#define MLME_ASSOC_REJ_NO_EXT_RATE_PBCC 23
-#define MLME_ASSOC_REJ_NO_CCK_OFDM 24
-
-#define MLME_QOS_UNSPECIFY 32
-#define MLME_REQUEST_DECLINED 37
-#define MLME_REQUEST_WITH_INVALID_PARAM 38
-#define MLME_INVALID_GROUP_CIPHER 41
-#define MLME_INVALID_PAIRWISE_CIPHER 42
-#define MLME_INVALID_AKMP 43
-#define MLME_DLS_NOT_ALLOW_IN_QBSS 48
-#define MLME_DEST_STA_NOT_IN_QBSS 49
-#define MLME_DEST_STA_IS_NOT_A_QSTA 50
-
-#define MLME_INVALID_FORMAT 0x51
-#define MLME_FAIL_NO_RESOURCE 0x52
-#define MLME_STATE_MACHINE_REJECT 0x53
-#define MLME_MAC_TABLE_FAIL 0x54
-
-/* IE code */
-#define IE_SSID 0
-#define IE_SUPP_RATES 1
-#define IE_FH_PARM 2
-#define IE_DS_PARM 3
-#define IE_CF_PARM 4
-#define IE_TIM 5
-#define IE_IBSS_PARM 6
-#define IE_COUNTRY 7 /* 802.11d */
-#define IE_802_11D_REQUEST 10 /* 802.11d */
-#define IE_QBSS_LOAD 11 /* 802.11e d9 */
-#define IE_EDCA_PARAMETER 12 /* 802.11e d9 */
-#define IE_TSPEC 13 /* 802.11e d9 */
-#define IE_TCLAS 14 /* 802.11e d9 */
-#define IE_SCHEDULE 15 /* 802.11e d9 */
-#define IE_CHALLENGE_TEXT 16
-#define IE_POWER_CONSTRAint 32 /* 802.11h d3.3 */
-#define IE_POWER_CAPABILITY 33 /* 802.11h d3.3 */
-#define IE_TPC_REQUEST 34 /* 802.11h d3.3 */
-#define IE_TPC_REPORT 35 /* 802.11h d3.3 */
-#define IE_SUPP_CHANNELS 36 /* 802.11h d3.3 */
-#define IE_CHANNEL_SWITCH_ANNOUNCEMENT 37 /* 802.11h d3.3 */
-#define IE_MEASUREMENT_REQUEST 38 /* 802.11h d3.3 */
-#define IE_MEASUREMENT_REPORT 39 /* 802.11h d3.3 */
-#define IE_QUIET 40 /* 802.11h d3.3 */
-#define IE_IBSS_DFS 41 /* 802.11h d3.3 */
-#define IE_ERP 42 /* 802.11g */
-#define IE_TS_DELAY 43 /* 802.11e d9 */
-#define IE_TCLAS_PROCESSING 44 /* 802.11e d9 */
-#define IE_QOS_CAPABILITY 46 /* 802.11e d6 */
-#define IE_HT_CAP 45 /* 802.11n d1. HT CAPABILITY. ELEMENT ID TBD */
-#define IE_AP_CHANNEL_REPORT 51 /* 802.11k d6 */
-#define IE_HT_CAP2 52 /* 802.11n d1. HT CAPABILITY. ELEMENT ID TBD */
-#define IE_RSN 48 /* 802.11i d3.0 */
-#define IE_WPA2 48 /* WPA2 */
-#define IE_EXT_SUPP_RATES 50 /* 802.11g */
-#define IE_SUPP_REG_CLASS 59 /* 802.11y. Supported regulatory classes. */
-#define IE_EXT_CHANNEL_SWITCH_ANNOUNCEMENT 60 /* 802.11n */
-#define IE_ADD_HT 61 /* 802.11n d1. ADDITIONAL HT CAPABILITY. ELEMENT ID TBD */
-#define IE_ADD_HT2 53 /* 802.11n d1. ADDITIONAL HT CAPABILITY. ELEMENT ID TBD */
-
-/* For 802.11n D3.03 */
-/*#define IE_NEW_EXT_CHA_OFFSET 62 // 802.11n d1. New extension channel offset element */
-#define IE_SECONDARY_CH_OFFSET 62 /* 802.11n D3.03 Secondary Channel Offset element */
-#define IE_WAPI 68 /* WAPI information element */
-#define IE_2040_BSS_COEXIST 72 /* 802.11n D3.0.3 */
-#define IE_2040_BSS_INTOLERANT_REPORT 73 /* 802.11n D3.03 */
-#define IE_OVERLAPBSS_SCAN_PARM 74 /* 802.11n D3.03 */
-#define IE_EXT_CAPABILITY 127 /* 802.11n D3.03 */
-
-#define IE_WPA 221 /* WPA */
-#define IE_VENDOR_SPECIFIC 221 /* Wifi WMM (WME) */
-
-#define OUI_BROADCOM_HT 51 /* */
-#define OUI_BROADCOM_HTADD 52 /* */
-#define OUI_PREN_HT_CAP 51 /* */
-#define OUI_PREN_ADD_HT 52 /* */
-
-/* CCX information */
-#define IE_AIRONET_CKIP 133 /* CCX1.0 ID 85H for CKIP */
-#define IE_AP_TX_POWER 150 /* CCX 2.0 for AP transmit power */
-#define IE_MEASUREMENT_CAPABILITY 221 /* CCX 2.0 */
-#define IE_CCX_V2 221
-#define IE_AIRONET_IPADDRESS 149 /* CCX ID 95H for IP Address */
-#define IE_AIRONET_CCKMREASSOC 156 /* CCX ID 9CH for CCKM Reassociation Request element */
-#define CKIP_NEGOTIATION_LENGTH 30
-#define AIRONET_IPADDRESS_LENGTH 10
-#define AIRONET_CCKMREASSOC_LENGTH 24
-
-/* ======================================================== */
-/* MLME state machine definition */
-/* ======================================================== */
-
-/* STA MLME state mahcines */
-#define ASSOC_STATE_MACHINE 1
-#define AUTH_STATE_MACHINE 2
-#define AUTH_RSP_STATE_MACHINE 3
-#define SYNC_STATE_MACHINE 4
-#define MLME_CNTL_STATE_MACHINE 5
-#define WPA_PSK_STATE_MACHINE 6
-/*#define LEAP_STATE_MACHINE 7 */
-#define AIRONET_STATE_MACHINE 8
-#define ACTION_STATE_MACHINE 9
-
-/* AP MLME state machines */
-#define AP_ASSOC_STATE_MACHINE 11
-#define AP_AUTH_STATE_MACHINE 12
-#define AP_SYNC_STATE_MACHINE 14
-#define AP_CNTL_STATE_MACHINE 15
-#define WSC_STATE_MACHINE 17
-#define WSC_UPNP_STATE_MACHINE 18
-
-#define WPA_STATE_MACHINE 23
-
-/* */
-/* STA's CONTROL/CONNECT state machine: states, events, total function # */
-/* */
-#define CNTL_IDLE 0
-#define CNTL_WAIT_DISASSOC 1
-#define CNTL_WAIT_JOIN 2
-#define CNTL_WAIT_REASSOC 3
-#define CNTL_WAIT_START 4
-#define CNTL_WAIT_AUTH 5
-#define CNTL_WAIT_ASSOC 6
-#define CNTL_WAIT_AUTH2 7
-#define CNTL_WAIT_OID_LIST_SCAN 8
-#define CNTL_WAIT_OID_DISASSOC 9
-#ifdef RTMP_MAC_USB
-#define CNTL_WAIT_SCAN_FOR_CONNECT 10
-#endif /* RTMP_MAC_USB // */
-
-#define MT2_ASSOC_CONF 34
-#define MT2_AUTH_CONF 35
-#define MT2_DEAUTH_CONF 36
-#define MT2_DISASSOC_CONF 37
-#define MT2_REASSOC_CONF 38
-#define MT2_PWR_MGMT_CONF 39
-#define MT2_JOIN_CONF 40
-#define MT2_SCAN_CONF 41
-#define MT2_START_CONF 42
-#define MT2_GET_CONF 43
-#define MT2_SET_CONF 44
-#define MT2_RESET_CONF 45
-#define MT2_FT_OTD_CONF 46
-#define MT2_MLME_ROAMING_REQ 52
-
-#define CNTL_FUNC_SIZE 1
-
-/* */
-/* STA's ASSOC state machine: states, events, total function # */
-/* */
-#define ASSOC_IDLE 0
-#define ASSOC_WAIT_RSP 1
-#define REASSOC_WAIT_RSP 2
-#define DISASSOC_WAIT_RSP 3
-#define MAX_ASSOC_STATE 4
-
-#define ASSOC_MACHINE_BASE 0
-#define MT2_MLME_ASSOC_REQ 0
-#define MT2_MLME_REASSOC_REQ 1
-#define MT2_MLME_DISASSOC_REQ 2
-#define MT2_PEER_DISASSOC_REQ 3
-#define MT2_PEER_ASSOC_REQ 4
-#define MT2_PEER_ASSOC_RSP 5
-#define MT2_PEER_REASSOC_REQ 6
-#define MT2_PEER_REASSOC_RSP 7
-#define MT2_DISASSOC_TIMEOUT 8
-#define MT2_ASSOC_TIMEOUT 9
-#define MT2_REASSOC_TIMEOUT 10
-#define MAX_ASSOC_MSG 11
-
-#define ASSOC_FUNC_SIZE (MAX_ASSOC_STATE * MAX_ASSOC_MSG)
-
-/* */
-/* ACT state machine: states, events, total function # */
-/* */
-#define ACT_IDLE 0
-#define MAX_ACT_STATE 1
-
-#define ACT_MACHINE_BASE 0
-
-/*Those PEER_xx_CATE number is based on real Categary value in IEEE spec. Please do not modify it by your self. */
-/*Category */
-#define MT2_PEER_SPECTRUM_CATE 0
-#define MT2_PEER_QOS_CATE 1
-#define MT2_PEER_DLS_CATE 2
-#define MT2_PEER_BA_CATE 3
-#define MT2_PEER_PUBLIC_CATE 4
-#define MT2_PEER_RM_CATE 5
-/* "FT_CATEGORY_BSS_TRANSITION equal to 6" is defined file of "dot11r_ft.h" */
-#define MT2_PEER_HT_CATE 7 /* 7.4.7 */
-#define MAX_PEER_CATE_MSG 7
-
-#define MT2_MLME_ADD_BA_CATE 8
-#define MT2_MLME_ORI_DELBA_CATE 9
-#define MT2_MLME_REC_DELBA_CATE 10
-#define MT2_MLME_QOS_CATE 11
-#define MT2_MLME_DLS_CATE 12
-#define MT2_ACT_INVALID 13
-#define MAX_ACT_MSG 14
-
-/*Category field */
-#define CATEGORY_SPECTRUM 0
-#define CATEGORY_QOS 1
-#define CATEGORY_DLS 2
-#define CATEGORY_BA 3
-#define CATEGORY_PUBLIC 4
-#define CATEGORY_RM 5
-#define CATEGORY_HT 7
-
-/* DLS Action frame definition */
-#define ACTION_DLS_REQUEST 0
-#define ACTION_DLS_RESPONSE 1
-#define ACTION_DLS_TEARDOWN 2
-
-/*Spectrum Action field value 802.11h 7.4.1 */
-#define SPEC_MRQ 0 /* Request */
-#define SPEC_MRP 1 /*Report */
-#define SPEC_TPCRQ 2
-#define SPEC_TPCRP 3
-#define SPEC_CHANNEL_SWITCH 4
-
-/*BA Action field value */
-#define ADDBA_REQ 0
-#define ADDBA_RESP 1
-#define DELBA 2
-
-/*Public's Action field value in Public Category. Some in 802.11y and some in 11n */
-#define ACTION_BSS_2040_COEXIST 0 /* 11n */
-#define ACTION_DSE_ENABLEMENT 1 /* 11y D9.0 */
-#define ACTION_DSE_DEENABLEMENT 2 /* 11y D9.0 */
-#define ACTION_DSE_REG_LOCATION_ANNOUNCE 3 /* 11y D9.0 */
-#define ACTION_EXT_CH_SWITCH_ANNOUNCE 4 /* 11y D9.0 */
-#define ACTION_DSE_MEASUREMENT_REQ 5 /* 11y D9.0 */
-#define ACTION_DSE_MEASUREMENT_REPORT 6 /* 11y D9.0 */
-#define ACTION_MEASUREMENT_PILOT_ACTION 7 /* 11y D9.0 */
-#define ACTION_DSE_POWER_CONSTRAINT 8 /* 11y D9.0 */
-
-/*HT Action field value */
-#define NOTIFY_BW_ACTION 0
-#define SMPS_ACTION 1
-#define PSMP_ACTION 2
-#define SETPCO_ACTION 3
-#define MIMO_CHA_MEASURE_ACTION 4
-#define MIMO_N_BEACONFORM 5
-#define MIMO_BEACONFORM 6
-#define ANTENNA_SELECT 7
-#define HT_INFO_EXCHANGE 8
-
-#define ACT_FUNC_SIZE (MAX_ACT_STATE * MAX_ACT_MSG)
-/* */
-/* STA's AUTHENTICATION state machine: states, events, total function # */
-/* */
-#define AUTH_REQ_IDLE 0
-#define AUTH_WAIT_SEQ2 1
-#define AUTH_WAIT_SEQ4 2
-#define MAX_AUTH_STATE 3
-
-#define AUTH_MACHINE_BASE 0
-#define MT2_MLME_AUTH_REQ 0
-#define MT2_PEER_AUTH_EVEN 1
-#define MT2_AUTH_TIMEOUT 2
-#define MAX_AUTH_MSG 3
-
-#define AUTH_FUNC_SIZE (MAX_AUTH_STATE * MAX_AUTH_MSG)
-
-/* */
-/* STA's AUTH_RSP state machine: states, events, total function # */
-/* */
-#define AUTH_RSP_IDLE 0
-#define AUTH_RSP_WAIT_CHAL 1
-#define MAX_AUTH_RSP_STATE 2
-
-#define AUTH_RSP_MACHINE_BASE 0
-#define MT2_AUTH_CHALLENGE_TIMEOUT 0
-#define MT2_PEER_AUTH_ODD 1
-#define MT2_PEER_DEAUTH 2
-#define MAX_AUTH_RSP_MSG 3
-
-#define AUTH_RSP_FUNC_SIZE (MAX_AUTH_RSP_STATE * MAX_AUTH_RSP_MSG)
-
-/* */
-/* STA's SYNC state machine: states, events, total function # */
-/* */
-#define SYNC_IDLE 0 /* merge NO_BSS,IBSS_IDLE,IBSS_ACTIVE and BSS in to 1 state */
-#define JOIN_WAIT_BEACON 1
-#define SCAN_LISTEN 2
-#define MAX_SYNC_STATE 3
-
-#define SYNC_MACHINE_BASE 0
-#define MT2_MLME_SCAN_REQ 0
-#define MT2_MLME_JOIN_REQ 1
-#define MT2_MLME_START_REQ 2
-#define MT2_PEER_BEACON 3
-#define MT2_PEER_PROBE_RSP 4
-#define MT2_PEER_ATIM 5
-#define MT2_SCAN_TIMEOUT 6
-#define MT2_BEACON_TIMEOUT 7
-#define MT2_ATIM_TIMEOUT 8
-#define MT2_PEER_PROBE_REQ 9
-#define MAX_SYNC_MSG 10
-
-#define SYNC_FUNC_SIZE (MAX_SYNC_STATE * MAX_SYNC_MSG)
-
-/*Messages for the DLS state machine */
-#define DLS_IDLE 0
-#define MAX_DLS_STATE 1
-
-#define DLS_MACHINE_BASE 0
-#define MT2_MLME_DLS_REQ 0
-#define MT2_PEER_DLS_REQ 1
-#define MT2_PEER_DLS_RSP 2
-#define MT2_MLME_DLS_TEAR_DOWN 3
-#define MT2_PEER_DLS_TEAR_DOWN 4
-#define MAX_DLS_MSG 5
-
-#define DLS_FUNC_SIZE (MAX_DLS_STATE * MAX_DLS_MSG)
-
-/* */
-/* WSC State machine: states, events, total function # */
-/* */
-
-/* */
-/* AP's CONTROL/CONNECT state machine: states, events, total function # */
-/* */
-#define AP_CNTL_FUNC_SIZE 1
-
-/* */
-/* AP's ASSOC state machine: states, events, total function # */
-/* */
-#define AP_ASSOC_IDLE 0
-#define AP_MAX_ASSOC_STATE 1
-
-#define AP_ASSOC_MACHINE_BASE 0
-#define APMT2_MLME_DISASSOC_REQ 0
-#define APMT2_PEER_DISASSOC_REQ 1
-#define APMT2_PEER_ASSOC_REQ 2
-#define APMT2_PEER_REASSOC_REQ 3
-#define APMT2_CLS3ERR 4
-#define AP_MAX_ASSOC_MSG 5
-
-#define AP_ASSOC_FUNC_SIZE (AP_MAX_ASSOC_STATE * AP_MAX_ASSOC_MSG)
-
-/* */
-/* AP's AUTHENTICATION state machine: states, events, total function # */
-/* */
-#define AP_AUTH_REQ_IDLE 0
-#define AP_MAX_AUTH_STATE 1
-
-#define AP_AUTH_MACHINE_BASE 0
-#define APMT2_MLME_DEAUTH_REQ 0
-#define APMT2_CLS2ERR 1
-#define APMT2_PEER_DEAUTH 2
-#define APMT2_PEER_AUTH_REQ 3
-#define APMT2_PEER_AUTH_CONFIRM 4
-#define AP_MAX_AUTH_MSG 5
-
-#define AP_AUTH_FUNC_SIZE (AP_MAX_AUTH_STATE * AP_MAX_AUTH_MSG)
-
-/* */
-/* AP's SYNC state machine: states, events, total function # */
-/* */
-#define AP_SYNC_IDLE 0
-#define AP_SCAN_LISTEN 1
-#define AP_MAX_SYNC_STATE 2
-
-#define AP_SYNC_MACHINE_BASE 0
-#define APMT2_PEER_PROBE_REQ 0
-#define APMT2_PEER_BEACON 1
-#define APMT2_MLME_SCAN_REQ 2
-#define APMT2_PEER_PROBE_RSP 3
-#define APMT2_SCAN_TIMEOUT 4
-#define APMT2_MLME_SCAN_CNCL 5
-#define AP_MAX_SYNC_MSG 6
-
-#define AP_SYNC_FUNC_SIZE (AP_MAX_SYNC_STATE * AP_MAX_SYNC_MSG)
-
-/* */
-/* Common WPA state machine: states, events, total function # */
-/* */
-#define WPA_PTK 0
-#define MAX_WPA_PTK_STATE 1
-
-#define WPA_MACHINE_BASE 0
-#define MT2_EAPPacket 0
-#define MT2_EAPOLStart 1
-#define MT2_EAPOLLogoff 2
-#define MT2_EAPOLKey 3
-#define MT2_EAPOLASFAlert 4
-#define MAX_WPA_MSG 5
-
-#define WPA_FUNC_SIZE (MAX_WPA_PTK_STATE * MAX_WPA_MSG)
-
-/* ============================================================================= */
-
-/* value domain of 802.11 header FC.Tyte, which is b3..b2 of the 1st-byte of MAC header */
-#define BTYPE_MGMT 0
-#define BTYPE_CNTL 1
-#define BTYPE_DATA 2
-
-/* value domain of 802.11 MGMT frame's FC.subtype, which is b7..4 of the 1st-byte of MAC header */
-#define SUBTYPE_ASSOC_REQ 0
-#define SUBTYPE_ASSOC_RSP 1
-#define SUBTYPE_REASSOC_REQ 2
-#define SUBTYPE_REASSOC_RSP 3
-#define SUBTYPE_PROBE_REQ 4
-#define SUBTYPE_PROBE_RSP 5
-#define SUBTYPE_BEACON 8
-#define SUBTYPE_ATIM 9
-#define SUBTYPE_DISASSOC 10
-#define SUBTYPE_AUTH 11
-#define SUBTYPE_DEAUTH 12
-#define SUBTYPE_ACTION 13
-#define SUBTYPE_ACTION_NO_ACK 14
-
-/* value domain of 802.11 CNTL frame's FC.subtype, which is b7..4 of the 1st-byte of MAC header */
-#define SUBTYPE_WRAPPER 7
-#define SUBTYPE_BLOCK_ACK_REQ 8
-#define SUBTYPE_BLOCK_ACK 9
-#define SUBTYPE_PS_POLL 10
-#define SUBTYPE_RTS 11
-#define SUBTYPE_CTS 12
-#define SUBTYPE_ACK 13
-#define SUBTYPE_CFEND 14
-#define SUBTYPE_CFEND_CFACK 15
-
-/* value domain of 802.11 DATA frame's FC.subtype, which is b7..4 of the 1st-byte of MAC header */
-#define SUBTYPE_DATA 0
-#define SUBTYPE_DATA_CFACK 1
-#define SUBTYPE_DATA_CFPOLL 2
-#define SUBTYPE_DATA_CFACK_CFPOLL 3
-#define SUBTYPE_NULL_FUNC 4
-#define SUBTYPE_CFACK 5
-#define SUBTYPE_CFPOLL 6
-#define SUBTYPE_CFACK_CFPOLL 7
-#define SUBTYPE_QDATA 8
-#define SUBTYPE_QDATA_CFACK 9
-#define SUBTYPE_QDATA_CFPOLL 10
-#define SUBTYPE_QDATA_CFACK_CFPOLL 11
-#define SUBTYPE_QOS_NULL 12
-#define SUBTYPE_QOS_CFACK 13
-#define SUBTYPE_QOS_CFPOLL 14
-#define SUBTYPE_QOS_CFACK_CFPOLL 15
-
-/* ACK policy of QOS Control field bit 6:5 */
-#define NORMAL_ACK 0x00 /* b6:5 = 00 */
-#define NO_ACK 0x20 /* b6:5 = 01 */
-#define NO_EXPLICIT_ACK 0x40 /* b6:5 = 10 */
-#define BLOCK_ACK 0x60 /* b6:5 = 11 */
-
-/* */
-/* rtmp_data.c uses this definition */
-/* */
-#define LENGTH_802_11 24
-#define LENGTH_802_11_AND_H 30
-#define LENGTH_802_11_CRC_H 34
-#define LENGTH_802_11_CRC 28
-#define LENGTH_802_11_WITH_ADDR4 30
-#define LENGTH_802_3 14
-#define LENGTH_802_3_TYPE 2
-#define LENGTH_802_1_H 8
-#define LENGTH_EAPOL_H 4
-#define LENGTH_WMMQOS_H 2
-#define LENGTH_CRC 4
-#define MAX_SEQ_NUMBER 0x0fff
-#define LENGTH_802_3_NO_TYPE 12
-#define LENGTH_802_1Q 4 /* VLAN related */
-
-/* STA_CSR4.field.TxResult */
-#define TX_RESULT_SUCCESS 0
-#define TX_RESULT_ZERO_LENGTH 1
-#define TX_RESULT_UNDER_RUN 2
-#define TX_RESULT_OHY_ERROR 4
-#define TX_RESULT_RETRY_FAIL 6
-
-/* All PHY rate summary in TXD */
-/* Preamble MODE in TxD */
-#define MODE_CCK 0
-#define MODE_OFDM 1
-#define MODE_HTMIX 2
-#define MODE_HTGREENFIELD 3
-
-/* MCS for CCK. BW.SGI.STBC are reserved */
-#define MCS_longP_RATE_1 0 /* long preamble CCK 1Mbps */
-#define MCS_longP_RATE_2 1 /* long preamble CCK 1Mbps */
-#define MCS_longP_RATE_5_5 2
-#define MCS_longP_RATE_11 3
-#define MCS_SHORTP_RATE_1 4 /* long preamble CCK 1Mbps. short is forbidden in 1Mbps */
-#define MCS_SHORTP_RATE_2 5 /* short preamble CCK 2Mbps */
-#define MCS_SHORTP_RATE_5_5 6
-#define MCS_SHORTP_RATE_11 7
-/* To send duplicate legacy OFDM. set BW=BW_40. SGI.STBC are reserved */
-#define MCS_RATE_6 0 /* legacy OFDM */
-#define MCS_RATE_9 1 /* OFDM */
-#define MCS_RATE_12 2 /* OFDM */
-#define MCS_RATE_18 3 /* OFDM */
-#define MCS_RATE_24 4 /* OFDM */
-#define MCS_RATE_36 5 /* OFDM */
-#define MCS_RATE_48 6 /* OFDM */
-#define MCS_RATE_54 7 /* OFDM */
-/* HT */
-#define MCS_0 0 /* 1S */
-#define MCS_1 1
-#define MCS_2 2
-#define MCS_3 3
-#define MCS_4 4
-#define MCS_5 5
-#define MCS_6 6
-#define MCS_7 7
-#define MCS_8 8 /* 2S */
-#define MCS_9 9
-#define MCS_10 10
-#define MCS_11 11
-#define MCS_12 12
-#define MCS_13 13
-#define MCS_14 14
-#define MCS_15 15
-#define MCS_16 16 /* 3*3 */
-#define MCS_17 17
-#define MCS_18 18
-#define MCS_19 19
-#define MCS_20 20
-#define MCS_21 21
-#define MCS_22 22
-#define MCS_23 23
-#define MCS_32 32
-#define MCS_AUTO 33
-
-/* OID_HTPHYMODE */
-/* MODE */
-#define HTMODE_MM 0
-#define HTMODE_GF 1
-
-/* Fixed Tx MODE - HT, CCK or OFDM */
-#define FIXED_TXMODE_HT 0
-#define FIXED_TXMODE_CCK 1
-#define FIXED_TXMODE_OFDM 2
-/* BW */
-#define BW_20 BAND_WIDTH_20
-#define BW_40 BAND_WIDTH_40
-#define BW_BOTH BAND_WIDTH_BOTH
-#define BW_10 BAND_WIDTH_10 /* 802.11j has 10MHz. This definition is for internal usage. doesn't fill in the IE or other field. */
-
-/* SHORTGI */
-#define GI_400 GAP_INTERVAL_400 /* only support in HT mode */
-#define GI_BOTH GAP_INTERVAL_BOTH
-#define GI_800 GAP_INTERVAL_800
-/* STBC */
-#define STBC_NONE 0
-#define STBC_USE 1 /* limited use in rt2860b phy */
-#define RXSTBC_ONE 1 /* rx support of one spatial stream */
-#define RXSTBC_TWO 2 /* rx support of 1 and 2 spatial stream */
-#define RXSTBC_THR 3 /* rx support of 1~3 spatial stream */
-/* MCS FEEDBACK */
-#define MCSFBK_NONE 0 /* not support mcs feedback / */
-#define MCSFBK_RSV 1 /* reserved */
-#define MCSFBK_UNSOLICIT 2 /* only support unsolict mcs feedback */
-#define MCSFBK_MRQ 3 /* response to both MRQ and unsolict mcs feedback */
-
-/* MIMO power safe */
-#define MMPS_STATIC 0
-#define MMPS_DYNAMIC 1
-#define MMPS_RSV 2
-#define MMPS_ENABLE 3
-
-/* A-MSDU size */
-#define AMSDU_0 0
-#define AMSDU_1 1
-
-/* MCS use 7 bits */
-#define TXRATEMIMO 0x80
-#define TXRATEMCS 0x7F
-#define TXRATEOFDM 0x7F
-#define RATE_1 0
-#define RATE_2 1
-#define RATE_5_5 2
-#define RATE_11 3
-#define RATE_6 4 /* OFDM */
-#define RATE_9 5 /* OFDM */
-#define RATE_12 6 /* OFDM */
-#define RATE_18 7 /* OFDM */
-#define RATE_24 8 /* OFDM */
-#define RATE_36 9 /* OFDM */
-#define RATE_48 10 /* OFDM */
-#define RATE_54 11 /* OFDM */
-#define RATE_FIRST_OFDM_RATE RATE_6
-#define RATE_LAST_OFDM_RATE RATE_54
-#define RATE_6_5 12 /* HT mix */
-#define RATE_13 13 /* HT mix */
-#define RATE_19_5 14 /* HT mix */
-#define RATE_26 15 /* HT mix */
-#define RATE_39 16 /* HT mix */
-#define RATE_52 17 /* HT mix */
-#define RATE_58_5 18 /* HT mix */
-#define RATE_65 19 /* HT mix */
-#define RATE_78 20 /* HT mix */
-#define RATE_104 21 /* HT mix */
-#define RATE_117 22 /* HT mix */
-#define RATE_130 23 /* HT mix */
-/*#define RATE_AUTO_SWITCH 255 // for StaCfg.FixedTxRate only */
-#define HTRATE_0 12
-#define RATE_FIRST_MM_RATE HTRATE_0
-#define RATE_FIRST_HT_RATE HTRATE_0
-#define RATE_LAST_HT_RATE HTRATE_0
-
-/* pTxWI->txop */
-#define IFS_HTTXOP 0 /* The txop will be handles by ASIC. */
-#define IFS_PIFS 1
-#define IFS_SIFS 2
-#define IFS_BACKOFF 3
-
-/* pTxD->RetryMode */
-#define long_RETRY 1
-#define SHORT_RETRY 0
-
-/* Country Region definition */
-#define REGION_MINIMUM_BG_BAND 0
-#define REGION_0_BG_BAND 0 /* 1-11 */
-#define REGION_1_BG_BAND 1 /* 1-13 */
-#define REGION_2_BG_BAND 2 /* 10-11 */
-#define REGION_3_BG_BAND 3 /* 10-13 */
-#define REGION_4_BG_BAND 4 /* 14 */
-#define REGION_5_BG_BAND 5 /* 1-14 */
-#define REGION_6_BG_BAND 6 /* 3-9 */
-#define REGION_7_BG_BAND 7 /* 5-13 */
-#define REGION_31_BG_BAND 31 /* 5-13 */
-#define REGION_MAXIMUM_BG_BAND 7
-
-#define REGION_MINIMUM_A_BAND 0
-#define REGION_0_A_BAND 0 /* 36, 40, 44, 48, 52, 56, 60, 64, 149, 153, 157, 161, 165 */
-#define REGION_1_A_BAND 1 /* 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 */
-#define REGION_2_A_BAND 2 /* 36, 40, 44, 48, 52, 56, 60, 64 */
-#define REGION_3_A_BAND 3 /* 52, 56, 60, 64, 149, 153, 157, 161 */
-#define REGION_4_A_BAND 4 /* 149, 153, 157, 161, 165 */
-#define REGION_5_A_BAND 5 /* 149, 153, 157, 161 */
-#define REGION_6_A_BAND 6 /* 36, 40, 44, 48 */
-#define REGION_7_A_BAND 7 /* 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161, 165, 169, 173 */
-#define REGION_8_A_BAND 8 /* 52, 56, 60, 64 */
-#define REGION_9_A_BAND 9 /* 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 132, 136, 140, 149, 153, 157, 161, 165 */
-#define REGION_10_A_BAND 10 /* 36, 40, 44, 48, 149, 153, 157, 161, 165 */
-#define REGION_11_A_BAND 11 /* 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 149, 153, 157, 161 */
-#define REGION_12_A_BAND 12 /* 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 */
-#define REGION_13_A_BAND 13 /* 52, 56, 60, 64, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 149, 153, 157, 161 */
-#define REGION_14_A_BAND 14 /* 36, 40, 44, 48, 52, 56, 60, 64, 100, 104, 108, 112, 116, 136, 140, 149, 153, 157, 161, 165 */
-#define REGION_15_A_BAND 15 /* 149, 153, 157, 161, 165, 169, 173 */
-#define REGION_MAXIMUM_A_BAND 15
-
-/* pTxD->CipherAlg */
-#define CIPHER_NONE 0
-#define CIPHER_WEP64 1
-#define CIPHER_WEP128 2
-#define CIPHER_TKIP 3
-#define CIPHER_AES 4
-#define CIPHER_CKIP64 5
-#define CIPHER_CKIP128 6
-#define CIPHER_TKIP_NO_MIC 7 /* MIC appended by driver: not a valid value in hardware key table */
-#define CIPHER_SMS4 8
-
-/* LED Status. */
-#define LED_LINK_DOWN 0
-#define LED_LINK_UP 1
-#define LED_RADIO_OFF 2
-#define LED_RADIO_ON 3
-#define LED_HALT 4
-#define LED_WPS 5
-#define LED_ON_SITE_SURVEY 6
-#define LED_POWER_UP 7
-
-/* value domain of pAd->LedCntl.LedMode and E2PROM */
-#define LED_MODE_DEFAULT 0
-#define LED_MODE_TWO_LED 1
-/*#define LED_MODE_SIGNAL_STREGTH 8 // EEPROM define =8 */
-#define LED_MODE_SIGNAL_STREGTH 0x40 /* EEPROM define = 64 */
-
-/* RC4 init value, used fro WEP & TKIP */
-#define PPPINITFCS32 0xffffffff /* Initial FCS value */
-
-/* value domain of pAd->StaCfg.PortSecured. 802.1X controlled port definition */
-#define WPA_802_1X_PORT_SECURED 1
-#define WPA_802_1X_PORT_NOT_SECURED 2
-
-#define PAIRWISE_KEY 1
-#define GROUP_KEY 2
-
-/*definition of DRS */
-#define MAX_STEP_OF_TX_RATE_SWITCH 32
-
-/* pre-allocated free NDIS PACKET/BUFFER poll for internal usage */
-#define MAX_NUM_OF_FREE_NDIS_PACKET 128
-
-/*Block ACK */
-#define MAX_TX_REORDERBUF 64
-#define MAX_RX_REORDERBUF 64
-#define DEFAULT_TX_TIMEOUT 30
-#define DEFAULT_RX_TIMEOUT 30
-
-/* definition of Recipient or Originator */
-#define I_RECIPIENT TRUE
-#define I_ORIGINATOR FALSE
-
-#define DEFAULT_BBP_TX_POWER 0
-#define DEFAULT_RF_TX_POWER 5
-
-#define MAX_INI_BUFFER_SIZE 4096
-#define MAX_PARAM_BUFFER_SIZE (2048) /* enough for ACL (18*64) */
- /*18 : the length of Mac address acceptable format "01:02:03:04:05:06;") */
- /*64 : MAX_NUM_OF_ACL_LIST */
-/* definition of pAd->OpMode */
-#define OPMODE_STA 0
-#define OPMODE_AP 1
-/*#define OPMODE_L3_BRG 2 // as AP and STA at the same time */
-
-/* ========================= AP rtmp_def.h =========================== */
-/* value domain for pAd->EventTab.Log[].Event */
-#define EVENT_RESET_ACCESS_POint 0 /* Log = "hh:mm:ss Restart Access Point" */
-#define EVENT_ASSOCIATED 1 /* Log = "hh:mm:ss STA 00:01:02:03:04:05 associated" */
-#define EVENT_DISASSOCIATED 2 /* Log = "hh:mm:ss STA 00:01:02:03:04:05 left this BSS" */
-#define EVENT_AGED_OUT 3 /* Log = "hh:mm:ss STA 00:01:02:03:04:05 was aged-out and removed from this BSS" */
-#define EVENT_COUNTER_M 4
-#define EVENT_INVALID_PSK 5
-#define EVENT_MAX_EVENT_TYPE 6
-/* ==== end of AP rtmp_def.h ============ */
-
-/* definition RSSI Number */
-#define RSSI_0 0
-#define RSSI_1 1
-#define RSSI_2 2
-
-/* definition of radar detection */
-#define RD_NORMAL_MODE 0 /* Not found radar signal */
-#define RD_SWITCHING_MODE 1 /* Found radar signal, and doing channel switch */
-#define RD_SILENCE_MODE 2 /* After channel switch, need to be silence a while to ensure radar not found */
-
-/*Driver defined cid for mapping status and command. */
-#define SLEEPCID 0x11
-#define WAKECID 0x22
-#define QUERYPOWERCID 0x33
-#define OWNERMCU 0x1
-#define OWNERCPU 0x0
-
-/* MBSSID definition */
-#define ENTRY_NOT_FOUND 0xFF
-
-/* After Linux 2.6.9,
- * VLAN module use Private (from user) interface flags (netdevice->priv_flags).
- * #define IFF_802_1Q_VLAN 0x1 -- 802.1Q VLAN device. in if.h
- * ref to ip_sabotage_out() [ out->priv_flags & IFF_802_1Q_VLAN ] in br_netfilter.c
- *
- * For this reason, we MUST use EVEN value in priv_flags
- */
-#define INT_MAIN 0x0100
-#define INT_MBSSID 0x0200
-#define INT_WDS 0x0300
-#define INT_APCLI 0x0400
-#define INT_MESH 0x0500
-
-#define INF_MAIN_DEV_NAME "wlan"
-#define INF_MBSSID_DEV_NAME "ra"
-#define INF_WDS_DEV_NAME "wds"
-#define INF_APCLI_DEV_NAME "apcli"
-#define INF_MESH_DEV_NAME "mesh"
-
-/* WEP Key TYPE */
-#define WEP_HEXADECIMAL_TYPE 0
-#define WEP_ASCII_TYPE 1
-
-/* WIRELESS EVENTS definition */
-/* Max number of char in custom event, refer to wireless_tools.28/wireless.20.h */
-#define IW_CUSTOM_MAX_LEN 255 /* In bytes */
-
-/* For system event - start */
-#define IW_SYS_EVENT_FLAG_START 0x0200
-#define IW_ASSOC_EVENT_FLAG 0x0200
-#define IW_DISASSOC_EVENT_FLAG 0x0201
-#define IW_DEAUTH_EVENT_FLAG 0x0202
-#define IW_AGEOUT_EVENT_FLAG 0x0203
-#define IW_COUNTER_MEASURES_EVENT_FLAG 0x0204
-#define IW_REPLAY_COUNTER_DIFF_EVENT_FLAG 0x0205
-#define IW_RSNIE_DIFF_EVENT_FLAG 0x0206
-#define IW_MIC_DIFF_EVENT_FLAG 0x0207
-#define IW_ICV_ERROR_EVENT_FLAG 0x0208
-#define IW_MIC_ERROR_EVENT_FLAG 0x0209
-#define IW_GROUP_HS_TIMEOUT_EVENT_FLAG 0x020A
-#define IW_PAIRWISE_HS_TIMEOUT_EVENT_FLAG 0x020B
-#define IW_RSNIE_SANITY_FAIL_EVENT_FLAG 0x020C
-#define IW_SET_KEY_DONE_WPA1_EVENT_FLAG 0x020D
-#define IW_SET_KEY_DONE_WPA2_EVENT_FLAG 0x020E
-#define IW_STA_LINKUP_EVENT_FLAG 0x020F
-#define IW_STA_LINKDOWN_EVENT_FLAG 0x0210
-#define IW_SCAN_COMPLETED_EVENT_FLAG 0x0211
-#define IW_SCAN_ENQUEUE_FAIL_EVENT_FLAG 0x0212
-/* if add new system event flag, please update the IW_SYS_EVENT_FLAG_END */
-#define IW_SYS_EVENT_FLAG_END 0x0212
-#define IW_SYS_EVENT_TYPE_NUM (IW_SYS_EVENT_FLAG_END - IW_SYS_EVENT_FLAG_START + 1)
-/* For system event - end */
-
-/* For spoof attack event - start */
-#define IW_SPOOF_EVENT_FLAG_START 0x0300
-#define IW_CONFLICT_SSID_EVENT_FLAG 0x0300
-#define IW_SPOOF_ASSOC_RESP_EVENT_FLAG 0x0301
-#define IW_SPOOF_REASSOC_RESP_EVENT_FLAG 0x0302
-#define IW_SPOOF_PROBE_RESP_EVENT_FLAG 0x0303
-#define IW_SPOOF_BEACON_EVENT_FLAG 0x0304
-#define IW_SPOOF_DISASSOC_EVENT_FLAG 0x0305
-#define IW_SPOOF_AUTH_EVENT_FLAG 0x0306
-#define IW_SPOOF_DEAUTH_EVENT_FLAG 0x0307
-#define IW_SPOOF_UNKNOWN_MGMT_EVENT_FLAG 0x0308
-#define IW_REPLAY_ATTACK_EVENT_FLAG 0x0309
-/* if add new spoof attack event flag, please update the IW_SPOOF_EVENT_FLAG_END */
-#define IW_SPOOF_EVENT_FLAG_END 0x0309
-#define IW_SPOOF_EVENT_TYPE_NUM (IW_SPOOF_EVENT_FLAG_END - IW_SPOOF_EVENT_FLAG_START + 1)
-/* For spoof attack event - end */
-
-/* For flooding attack event - start */
-#define IW_FLOOD_EVENT_FLAG_START 0x0400
-#define IW_FLOOD_AUTH_EVENT_FLAG 0x0400
-#define IW_FLOOD_ASSOC_REQ_EVENT_FLAG 0x0401
-#define IW_FLOOD_REASSOC_REQ_EVENT_FLAG 0x0402
-#define IW_FLOOD_PROBE_REQ_EVENT_FLAG 0x0403
-#define IW_FLOOD_DISASSOC_EVENT_FLAG 0x0404
-#define IW_FLOOD_DEAUTH_EVENT_FLAG 0x0405
-#define IW_FLOOD_EAP_REQ_EVENT_FLAG 0x0406
-/* if add new flooding attack event flag, please update the IW_FLOOD_EVENT_FLAG_END */
-#define IW_FLOOD_EVENT_FLAG_END 0x0406
-#define IW_FLOOD_EVENT_TYPE_NUM (IW_FLOOD_EVENT_FLAG_END - IW_FLOOD_EVENT_FLAG_START + 1)
-/* For flooding attack - end */
-
-/* End - WIRELESS EVENTS definition */
-
-/* definition for DLS, kathy */
-#define MAX_NUM_OF_INIT_DLS_ENTRY 1
-#define MAX_NUM_OF_DLS_ENTRY MAX_NUMBER_OF_DLS_ENTRY
-
-/*Block ACK, kathy */
-#define MAX_TX_REORDERBUF 64
-#define MAX_RX_REORDERBUF 64
-#define DEFAULT_TX_TIMEOUT 30
-#define DEFAULT_RX_TIMEOUT 30
-#define MAX_BARECI_SESSION 8
-
-#ifndef IW_ESSID_MAX_SIZE
-/* Maximum size of the ESSID and pAd->nickname strings */
-#define IW_ESSID_MAX_SIZE 32
-#endif
-
-/* For AsicRadioOff/AsicRadioOn function */
-#define DOT11POWERSAVE 0
-#define GUIRADIO_OFF 1
-#define RTMP_HALT 2
-#define GUI_IDLE_POWER_SAVE 3
-/* -- */
-
-/* definition for WpaSupport flag */
-#define WPA_SUPPLICANT_DISABLE 0
-#define WPA_SUPPLICANT_ENABLE 1
-#define WPA_SUPPLICANT_ENABLE_WITH_WEB_UI 2
-
-/* Endian byte swapping codes */
-#define SWAP16(x) \
- ((u16)( \
- (((u16)(x) & (u16)0x00ffU) << 8) | \
- (((u16)(x) & (u16)0xff00U) >> 8) ))
-
-#define SWAP32(x) \
- ((u32)( \
- (((u32)(x) & (u32)0x000000ffUL) << 24) | \
- (((u32)(x) & (u32)0x0000ff00UL) << 8) | \
- (((u32)(x) & (u32)0x00ff0000UL) >> 8) | \
- (((u32)(x) & (u32)0xff000000UL) >> 24) ))
-
-#define SWAP64(x) \
- ((u64)( \
- (u64)(((u64)(x) & (u64)0x00000000000000ffULL) << 56) | \
- (u64)(((u64)(x) & (u64)0x000000000000ff00ULL) << 40) | \
- (u64)(((u64)(x) & (u64)0x0000000000ff0000ULL) << 24) | \
- (u64)(((u64)(x) & (u64)0x00000000ff000000ULL) << 8) | \
- (u64)(((u64)(x) & (u64)0x000000ff00000000ULL) >> 8) | \
- (u64)(((u64)(x) & (u64)0x0000ff0000000000ULL) >> 24) | \
- (u64)(((u64)(x) & (u64)0x00ff000000000000ULL) >> 40) | \
- (u64)(((u64)(x) & (u64)0xff00000000000000ULL) >> 56) ))
-
-#define cpu2le64(x) ((u64)(x))
-#define le2cpu64(x) ((u64)(x))
-#define cpu2le32(x) ((u32)(x))
-#define le2cpu32(x) ((u32)(x))
-#define cpu2le16(x) ((u16)(x))
-#define le2cpu16(x) ((u16)(x))
-#define cpu2be64(x) SWAP64((x))
-#define be2cpu64(x) SWAP64((x))
-#define cpu2be32(x) SWAP32((x))
-#define be2cpu32(x) SWAP32((x))
-#define cpu2be16(x) SWAP16((x))
-#define be2cpu16(x) SWAP16((x))
-
-#define ABS(_x, _y) ((_x) > (_y)) ? ((_x) -(_y)) : ((_y) -(_x))
-
-#define A2Dec(_X, _p) \
-{ \
- u8 *p; \
- _X = 0; \
- p = _p; \
- while (((*p >= '0') && (*p <= '9'))) \
- { \
- if ((*p >= '0') && (*p <= '9')) \
- _X = _X * 10 + *p - 48; \
- p++; \
- } \
-}
-
-#define A2Hex(_X, _p) \
-do{ \
- char *__p; \
- (_X) = 0; \
- __p = (char *)(_p); \
- while (((*__p >= 'a') && (*__p <= 'f')) || ((*__p >= 'A') && (*__p <= 'F')) || ((*__p >= '0') && (*__p <= '9'))) \
- { \
- if ((*__p >= 'a') && (*__p <= 'f')) \
- (_X) = (_X) * 16 + *__p - 87; \
- else if ((*__p >= 'A') && (*__p <= 'F')) \
- (_X) = (_X) * 16 + *__p - 55; \
- else if ((*__p >= '0') && (*__p <= '9')) \
- (_X) = (_X) * 16 + *__p - 48; \
- __p++; \
- } \
-}while(0)
-
-#endif /* __RTMP_DEF_H__ */
diff --git a/drivers/staging/rt2860/rtmp_dot11.h b/drivers/staging/rt2860/rtmp_dot11.h
deleted file mode 100644
index 4f8abd7..0000000
--- a/drivers/staging/rt2860/rtmp_dot11.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-*/
-
-#ifndef __DOT11_BASE_H__
-#define __DOT11_BASE_H__
-
-#include "rtmp_type.h"
-
-/* 4-byte HTC field. maybe included in any frame except non-QOS data frame. The Order bit must set 1. */
-struct PACKED rt_ht_control {
- u32 MA:1; /*management action payload exist in (QoS Null+HTC) */
- u32 TRQ:1; /*sounding request */
- u32 MRQ:1; /*MCS feedback. Request for a MCS feedback */
- u32 MRSorASI:3; /* MRQ Sequence identifier. unchanged during entire procedure. 0x000-0x110. */
- u32 MFS:3; /*SET to the received value of MRS. 0x111 for unsolicited MFB. */
- u32 MFBorASC:7; /*Link adaptation feedback containing recommended MCS. 0x7f for no feedback or not available */
- u32 CalPos:2; /* calibration position */
- u32 CalSeq:2; /*calibration sequence */
- u32 FBKReq:2; /*feedback request */
- u32 CSISTEERING:2; /*CSI/ STEERING */
- u32 ZLFAnnouce:1; /* ZLF announcement */
- u32 rsv:5; /*calibration sequence */
- u32 ACConstraint:1; /*feedback request */
- u32 RDG:1; /*RDG / More PPDU */
-};
-
-/* 2-byte QOS CONTROL field */
-struct PACKED rt_qos_control {
- u16 TID:4;
- u16 EOSP:1;
- u16 AckPolicy:2; /*0: normal ACK 1:No ACK 2:scheduled under MTBA/PSMP 3: BA */
- u16 AMsduPresent:1;
- u16 Txop_QueueSize:8;
-};
-
-/* 2-byte Frame control field */
-struct PACKED rt_frame_control {
- u16 Ver:2; /* Protocol version */
- u16 Type:2; /* MSDU type */
- u16 SubType:4; /* MSDU subtype */
- u16 ToDs:1; /* To DS indication */
- u16 FrDs:1; /* From DS indication */
- u16 MoreFrag:1; /* More fragment bit */
- u16 Retry:1; /* Retry status bit */
- u16 PwrMgmt:1; /* Power management bit */
- u16 MoreData:1; /* More data bit */
- u16 Wep:1; /* Wep data */
- u16 Order:1; /* Strict order expected */
-};
-
-struct PACKED rt_header_802_11 {
- struct rt_frame_control FC;
- u16 Duration;
- u8 Addr1[MAC_ADDR_LEN];
- u8 Addr2[MAC_ADDR_LEN];
- u8 Addr3[MAC_ADDR_LEN];
- u16 Frag:4;
- u16 Sequence:12;
- u8 Octet[0];
-};
-
-struct PACKED rt_pspoll_frame {
- struct rt_frame_control FC;
- u16 Aid;
- u8 Bssid[MAC_ADDR_LEN];
- u8 Ta[MAC_ADDR_LEN];
-};
-
-struct PACKED rt_rts_frame {
- struct rt_frame_control FC;
- u16 Duration;
- u8 Addr1[MAC_ADDR_LEN];
- u8 Addr2[MAC_ADDR_LEN];
-};
-
-#endif /* __DOT11_BASE_H__ // */
diff --git a/drivers/staging/rt2860/rtmp_iface.h b/drivers/staging/rt2860/rtmp_iface.h
deleted file mode 100644
index 808c055..0000000
--- a/drivers/staging/rt2860/rtmp_iface.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- rt_iface.h
-
- Abstract:
-
- Revision History:
- Who When What
- --------- ---------- ----------------------------------------------
- */
-
-#ifndef __RTMP_IFACE_H__
-#define __RTMP_IFACE_H__
-
-#ifdef RTMP_PCI_SUPPORT
-#include "iface/rtmp_pci.h"
-#endif /* RTMP_PCI_SUPPORT // */
-#ifdef RTMP_USB_SUPPORT
-#include "iface/rtmp_usb.h"
-#endif /* RTMP_USB_SUPPORT // */
-
-struct rt_inf_pci_config {
- unsigned long CSRBaseAddress; /* PCI MMIO Base Address, all access will use */
- unsigned int irq_num;
-};
-
-struct rt_inf_usb_config {
- u8 BulkInEpAddr; /* bulk-in endpoint address */
- u8 BulkOutEpAddr[6]; /* bulk-out endpoint address */
-};
-
-struct rt_inf_rbus_config {
- unsigned long csr_addr;
- unsigned int irq;
-};
-
-typedef enum _RTMP_INF_TYPE_ {
- RTMP_DEV_INF_UNKNOWN = 0,
- RTMP_DEV_INF_PCI = 1,
- RTMP_DEV_INF_USB = 2,
- RTMP_DEV_INF_RBUS = 4,
-} RTMP_INF_TYPE;
-
-typedef union _RTMP_INF_CONFIG_ {
- struct rt_inf_pci_config pciConfig;
- struct rt_inf_usb_config usbConfig;
- struct rt_inf_rbus_config rbusConfig;
-} RTMP_INF_CONFIG;
-
-#endif /* __RTMP_IFACE_H__ // */
diff --git a/drivers/staging/rt2860/rtmp_mcu.h b/drivers/staging/rt2860/rtmp_mcu.h
deleted file mode 100644
index d0987e5..0000000
--- a/drivers/staging/rt2860/rtmp_mcu.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- rtmp_mcu.h
-
- Abstract:
- Miniport header file for mcu related information
-
- Revision History:
- Who When What
- -------- ---------- ----------------------------------------------
-*/
-
-#ifndef __RTMP_MCU_H__
-#define __RTMP_MCU_H__
-
-int RtmpAsicEraseFirmware(struct rt_rtmp_adapter *pAd);
-
-int RtmpAsicLoadFirmware(struct rt_rtmp_adapter *pAd);
-
-int RtmpAsicSendCommandToMcu(struct rt_rtmp_adapter *pAd,
- u8 Command,
- u8 Token, u8 Arg0, u8 Arg1);
-
-#endif /* __RTMP_MCU_H__ // */
diff --git a/drivers/staging/rt2860/rtmp_os.h b/drivers/staging/rt2860/rtmp_os.h
deleted file mode 100644
index 94c30c8..0000000
--- a/drivers/staging/rt2860/rtmp_os.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- rtmp_os.h
-
- Abstract:
-
- Revision History:
- Who When What
- --------- ---------- ----------------------------------------------
- */
-
-#ifndef __RTMP_OS_H__
-#define __RTMP_OS_H__
-
-#ifdef LINUX
-#include "rt_linux.h"
-#endif /* LINUX // */
-
-/*
- This data structure mainly strip some callback function defined in
- "struct net_device" in kernel source "include/linux/netdevice.h".
-
- The definition of this data structure may various depends on different
- OS. Use it carefully.
-*/
-struct rt_rtmp_os_netdev_op_hook {
- const struct net_device_ops *netdev_ops;
- void *priv;
- int priv_flags;
- unsigned char devAddr[6];
- unsigned char devName[16];
- unsigned char needProtcted;
-};
-
-typedef enum _RTMP_TASK_STATUS_ {
- RTMP_TASK_STAT_UNKNOWN = 0,
- RTMP_TASK_STAT_INITED = 1,
- RTMP_TASK_STAT_RUNNING = 2,
- RTMP_TASK_STAT_STOPED = 4,
-} RTMP_TASK_STATUS;
-#define RTMP_TASK_CAN_DO_INSERT (RTMP_TASK_STAT_INITED |RTMP_TASK_STAT_RUNNING)
-
-#define RTMP_OS_TASK_NAME_LEN 16
-struct rt_rtmp_os_task {
- char taskName[RTMP_OS_TASK_NAME_LEN];
- void *priv;
- /*unsigned long taskFlags; */
- RTMP_TASK_STATUS taskStatus;
-#ifndef KTHREAD_SUPPORT
- struct semaphore taskSema;
- struct pid *taskPID;
- struct completion taskComplete;
-#endif
- unsigned char task_killed;
-#ifdef KTHREAD_SUPPORT
- struct task_struct *kthread_task;
- wait_queue_head_t kthread_q;
- BOOLEAN kthread_running;
-#endif
-};
-
-int RtmpOSIRQRequest(struct net_device *pNetDev);
-int RtmpOSIRQRelease(struct net_device *pNetDev);
-
-#endif /* __RMTP_OS_H__ // */
diff --git a/drivers/staging/rt2860/rtmp_timer.h b/drivers/staging/rt2860/rtmp_timer.h
deleted file mode 100644
index 15b6287..0000000
--- a/drivers/staging/rt2860/rtmp_timer.h
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- rtmp_timer.h
-
- Abstract:
- Ralink Wireless Driver timer related data structures and declarations
-
- Revision History:
- Who When What
- -------- ---------- ----------------------------------------------
- Name Date Modification logs
- Shiang Tu Aug-28-2008 init version
- Justin P. Mattock 11/07/2010 Fix a typo
-
-*/
-
-#ifndef __RTMP_TIMER_H__
-#define __RTMP_TIMER_H__
-
-#include "rtmp_os.h"
-
-#define DECLARE_TIMER_FUNCTION(_func) \
- void rtmp_timer_##_func(unsigned long data)
-
-#define GET_TIMER_FUNCTION(_func) \
- rtmp_timer_##_func
-
-/* ----------------- Timer Related MARCO ---------------*/
-/* In some os or chipset, we have a lot of timer functions and will read/write register, */
-/* it's not allowed in Linux USB sub-system to do it ( because of sleep issue when */
-/* submit to ctrl pipe). So we need a wrapper function to take care it. */
-
-#ifdef RTMP_TIMER_TASK_SUPPORT
-typedef void(*RTMP_TIMER_TASK_HANDLE) (void *SystemSpecific1,
- void *FunctionContext,
- void *SystemSpecific2,
- void *SystemSpecific3);
-#endif /* RTMP_TIMER_TASK_SUPPORT // */
-
-struct rt_ralink_timer {
- struct timer_list TimerObj; /* Ndis Timer object */
- BOOLEAN Valid; /* Set to True when call RTMPInitTimer */
- BOOLEAN State; /* True if timer cancelled */
- BOOLEAN PeriodicType; /* True if timer is periodic timer */
- BOOLEAN Repeat; /* True if periodic timer */
- unsigned long TimerValue; /* Timer value in milliseconds */
- unsigned long cookie; /* os specific object */
-#ifdef RTMP_TIMER_TASK_SUPPORT
- RTMP_TIMER_TASK_HANDLE handle;
- void *pAd;
-#endif /* RTMP_TIMER_TASK_SUPPORT // */
-};
-
-#ifdef RTMP_TIMER_TASK_SUPPORT
-struct rt_rtmp_timer_task_entry {
- struct rt_ralink_timer *pRaTimer;
- struct rt_rtmp_timer_task_entry *pNext;
-};
-
-#define TIMER_QUEUE_SIZE_MAX 128
-struct rt_rtmp_timer_task_queue {
- unsigned int status;
- unsigned char *pTimerQPoll;
- struct rt_rtmp_timer_task_entry *pQPollFreeList;
- struct rt_rtmp_timer_task_entry *pQHead;
- struct rt_rtmp_timer_task_entry *pQTail;
-};
-
-#define BUILD_TIMER_FUNCTION(_func) \
-void rtmp_timer_##_func(unsigned long data) \
-{ \
- struct rt_ralink_timer *_pTimer = (struct rt_ralink_timer *)data; \
- struct rt_rtmp_timer_task_entry *_pQNode; \
- struct rt_rtmp_adapter *_pAd; \
- \
- _pTimer->handle = _func; \
- _pAd = (struct rt_rtmp_adapter *)_pTimer->pAd; \
- _pQNode = RtmpTimerQInsert(_pAd, _pTimer); \
- if ((_pQNode == NULL) && (_pAd->TimerQ.status & RTMP_TASK_CAN_DO_INSERT)) \
- RTMP_OS_Add_Timer(&_pTimer->TimerObj, OS_HZ); \
-}
-#else
-#define BUILD_TIMER_FUNCTION(_func) \
-void rtmp_timer_##_func(unsigned long data) \
-{ \
- struct rt_ralink_timer *pTimer = (struct rt_ralink_timer *)data; \
- \
- _func(NULL, (void *)pTimer->cookie, NULL, pTimer); \
- if (pTimer->Repeat) \
- RTMP_OS_Add_Timer(&pTimer->TimerObj, pTimer->TimerValue); \
-}
-#endif /* RTMP_TIMER_TASK_SUPPORT // */
-
-DECLARE_TIMER_FUNCTION(MlmePeriodicExec);
-DECLARE_TIMER_FUNCTION(MlmeRssiReportExec);
-DECLARE_TIMER_FUNCTION(AsicRxAntEvalTimeout);
-DECLARE_TIMER_FUNCTION(APSDPeriodicExec);
-DECLARE_TIMER_FUNCTION(AsicRfTuningExec);
-#ifdef RTMP_MAC_USB
-DECLARE_TIMER_FUNCTION(BeaconUpdateExec);
-#endif /* RTMP_MAC_USB // */
-
-DECLARE_TIMER_FUNCTION(BeaconTimeout);
-DECLARE_TIMER_FUNCTION(ScanTimeout);
-DECLARE_TIMER_FUNCTION(AuthTimeout);
-DECLARE_TIMER_FUNCTION(AssocTimeout);
-DECLARE_TIMER_FUNCTION(ReassocTimeout);
-DECLARE_TIMER_FUNCTION(DisassocTimeout);
-DECLARE_TIMER_FUNCTION(LinkDownExec);
-DECLARE_TIMER_FUNCTION(StaQuickResponeForRateUpExec);
-DECLARE_TIMER_FUNCTION(WpaDisassocApAndBlockAssoc);
-DECLARE_TIMER_FUNCTION(PsPollWakeExec);
-DECLARE_TIMER_FUNCTION(RadioOnExec);
-
-#ifdef RTMP_MAC_USB
-DECLARE_TIMER_FUNCTION(RtmpUsbStaAsicForceWakeupTimeout);
-#endif /* RTMP_MAC_USB // */
-
-#if defined(AP_LED) || defined(STA_LED)
-DECLARE_TIMER_FUNCTION(LedCtrlMain);
-#endif
-
-#endif /* __RTMP_TIMER_H__ // */
diff --git a/drivers/staging/rt2860/rtmp_type.h b/drivers/staging/rt2860/rtmp_type.h
deleted file mode 100644
index d9bb2d6..0000000
--- a/drivers/staging/rt2860/rtmp_type.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- rtmp_type.h
-
- Abstract:
-
- Revision History:
- Who When What
- -------- ---------- ----------------------------------------------
- Name Date Modification logs
- Paul Lin 1-2-2004
-*/
-#ifndef __RTMP_TYPE_H__
-#define __RTMP_TYPE_H__
-
-#include <linux/types.h>
-
-#define PACKED __attribute__ ((packed))
-
-typedef unsigned char BOOLEAN;
-
-typedef union _LARGE_INTEGER {
- struct {
- u32 LowPart;
- int HighPart;
- } u;
- long long QuadPart;
-} LARGE_INTEGER;
-
-/* */
-/* Register set pair for initialzation register set definition */
-/* */
-struct rt_rtmp_reg_pair {
- unsigned long Register;
- unsigned long Value;
-};
-
-struct rt_reg_pair {
- u8 Register;
- u8 Value;
-};
-
-/* */
-/* Register set pair for initialzation register set definition */
-/* */
-struct rt_rtmp_rf_regs {
- u8 Channel;
- unsigned long R1;
- unsigned long R2;
- unsigned long R3;
- unsigned long R4;
-};
-
-struct rt_frequency_item {
- u8 Channel;
- u8 N;
- u8 R;
- u8 K;
-};
-
-#define STATUS_SUCCESS 0x00
-#define STATUS_UNSUCCESSFUL 0x01
-
-#endif /* __RTMP_TYPE_H__ // */
diff --git a/drivers/staging/rt2860/rtusb_io.h b/drivers/staging/rt2860/rtusb_io.h
deleted file mode 100644
index 64a2fe4..0000000
--- a/drivers/staging/rt2860/rtusb_io.h
+++ /dev/null
@@ -1,185 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-*/
-
-#ifndef __RTUSB_IO_H__
-#define __RTUSB_IO_H__
-
-#include "rtmp_type.h"
-
-/* New for MeetingHouse Api support */
-#define CMDTHREAD_VENDOR_RESET 0x0D730101 /* cmd */
-#define CMDTHREAD_VENDOR_UNPLUG 0x0D730102 /* cmd */
-#define CMDTHREAD_VENDOR_SWITCH_FUNCTION 0x0D730103 /* cmd */
-#define CMDTHREAD_MULTI_WRITE_MAC 0x0D730107 /* cmd */
-#define CMDTHREAD_MULTI_READ_MAC 0x0D730108 /* cmd */
-#define CMDTHREAD_VENDOR_EEPROM_WRITE 0x0D73010A /* cmd */
-#define CMDTHREAD_VENDOR_EEPROM_READ 0x0D73010B /* cmd */
-#define CMDTHREAD_VENDOR_ENTER_TESTMODE 0x0D73010C /* cmd */
-#define CMDTHREAD_VENDOR_EXIT_TESTMODE 0x0D73010D /* cmd */
-#define CMDTHREAD_VENDOR_WRITE_BBP 0x0D730119 /* cmd */
-#define CMDTHREAD_VENDOR_READ_BBP 0x0D730118 /* cmd */
-#define CMDTHREAD_VENDOR_WRITE_RF 0x0D73011A /* cmd */
-#define CMDTHREAD_VENDOR_FLIP_IQ 0x0D73011D /* cmd */
-#define CMDTHREAD_RESET_BULK_OUT 0x0D730210 /* cmd */
-#define CMDTHREAD_RESET_BULK_IN 0x0D730211 /* cmd */
-#define CMDTHREAD_SET_PSM_BIT 0x0D730212 /* cmd */
-#define CMDTHREAD_SET_RADIO 0x0D730214 /* cmd */
-#define CMDTHREAD_UPDATE_TX_RATE 0x0D730216 /* cmd */
-#define CMDTHREAD_802_11_ADD_KEY_WEP 0x0D730218 /* cmd */
-#define CMDTHREAD_RESET_FROM_ERROR 0x0D73021A /* cmd */
-#define CMDTHREAD_LINK_DOWN 0x0D73021B /* cmd */
-#define CMDTHREAD_RESET_FROM_NDIS 0x0D73021C /* cmd */
-#define CMDTHREAD_CHECK_GPIO 0x0D730215 /* cmd */
-#define CMDTHREAD_FORCE_WAKE_UP 0x0D730222 /* cmd */
-#define CMDTHREAD_SET_BW 0x0D730225 /* cmd */
-#define CMDTHREAD_SET_ASIC_WCID 0x0D730226 /* cmd */
-#define CMDTHREAD_SET_ASIC_WCID_CIPHER 0x0D730227 /* cmd */
-#define CMDTHREAD_QKERIODIC_EXECUT 0x0D73023D /* cmd */
-#define RT_CMD_SET_KEY_TABLE 0x0D730228 /* cmd */
-#define RT_CMD_SET_RX_WCID_TABLE 0x0D730229 /* cmd */
-#define CMDTHREAD_SET_CLIENT_MAC_ENTRY 0x0D73023E /* cmd */
-#define CMDTHREAD_SET_GROUP_KEY 0x0D73023F /* cmd */
-#define CMDTHREAD_SET_PAIRWISE_KEY 0x0D730240 /* cmd */
-
-#define CMDTHREAD_802_11_QUERY_HARDWARE_REGISTER 0x0D710105 /* cmd */
-#define CMDTHREAD_802_11_SET_PHY_MODE 0x0D79010C /* cmd */
-#define CMDTHREAD_802_11_SET_STA_CONFIG 0x0D790111 /* cmd */
-#define CMDTHREAD_802_11_SET_PREAMBLE 0x0D790101 /* cmd */
-#define CMDTHREAD_802_11_COUNTER_MEASURE 0x0D790102 /* cmd */
-/* add by johnli, fix "in_interrupt" error when call "MacTableDeleteEntry" in Rx tasklet */
-#define CMDTHREAD_UPDATE_PROTECT 0x0D790103 /* cmd */
-/* end johnli */
-
-/*CMDTHREAD_MULTI_READ_MAC */
-/*CMDTHREAD_MULTI_WRITE_MAC */
-/*CMDTHREAD_VENDOR_EEPROM_READ */
-/*CMDTHREAD_VENDOR_EEPROM_WRITE */
-struct rt_cmdhandler_tlv {
- u16 Offset;
- u16 Length;
- u8 DataFirst;
-};
-
-struct rt_cmdqelmt;
-
-struct rt_cmdqelmt {
- u32 command;
- void *buffer;
- unsigned long bufferlength;
- BOOLEAN CmdFromNdis;
- BOOLEAN SetOperation;
- struct rt_cmdqelmt *next;
-};
-
-struct rt_cmdq {
- u32 size;
- struct rt_cmdqelmt *head;
- struct rt_cmdqelmt *tail;
- u32 CmdQState;
-};
-
-#define EnqueueCmd(cmdq, cmdqelmt) \
-{ \
- if (cmdq->size == 0) \
- cmdq->head = cmdqelmt; \
- else \
- cmdq->tail->next = cmdqelmt; \
- cmdq->tail = cmdqelmt; \
- cmdqelmt->next = NULL; \
- cmdq->size++; \
-}
-
-/******************************************************************************
-
- USB Cmd to ASIC Related MACRO
-
-******************************************************************************/
-/* reset MAC of a station entry to 0xFFFFFFFFFFFF */
-#define RTMP_STA_ENTRY_MAC_RESET(pAd, Wcid) \
- { struct rt_set_asic_wcid SetAsicWcid; \
- SetAsicWcid.WCID = Wcid; \
- SetAsicWcid.SetTid = 0xffffffff; \
- SetAsicWcid.DeleteTid = 0xffffffff; \
- RTUSBEnqueueInternalCmd(pAd, CMDTHREAD_SET_ASIC_WCID, \
- &SetAsicWcid, sizeof(struct rt_set_asic_wcid)); }
-
-/* add this entry into ASIC RX WCID search table */
-#define RTMP_STA_ENTRY_ADD(pAd, pEntry) \
- RTUSBEnqueueInternalCmd(pAd, CMDTHREAD_SET_CLIENT_MAC_ENTRY, \
- pEntry, sizeof(struct rt_mac_table_entry));
-
-/* add by johnli, fix "in_interrupt" error when call "MacTableDeleteEntry" in Rx tasklet */
-/* Set MAC register value according operation mode */
-#define RTMP_UPDATE_PROTECT(pAd) \
- RTUSBEnqueueInternalCmd(pAd, CMDTHREAD_UPDATE_PROTECT, NULL, 0);
-/* end johnli */
-
-/* remove Pair-wise key material from ASIC */
-/* yet implement */
-#define RTMP_STA_ENTRY_KEY_DEL(pAd, BssIdx, Wcid)
-
-/* add Client security information into ASIC WCID table and IVEIV table */
-#define RTMP_STA_SECURITY_INFO_ADD(pAd, apidx, KeyID, pEntry) \
- { RTMP_STA_ENTRY_MAC_RESET(pAd, pEntry->Aid); \
- if (pEntry->Aid >= 1) { \
- struct rt_set_asic_wcid_attri SetAsicWcidAttri; \
- SetAsicWcidAttri.WCID = pEntry->Aid; \
- if ((pEntry->AuthMode <= Ndis802_11AuthModeAutoSwitch) && \
- (pEntry->WepStatus == Ndis802_11Encryption1Enabled)) \
- { \
- SetAsicWcidAttri.Cipher = pAd->SharedKey[apidx][KeyID].CipherAlg; \
- } \
- else if (pEntry->AuthMode == Ndis802_11AuthModeWPANone) \
- { \
- SetAsicWcidAttri.Cipher = pAd->SharedKey[apidx][KeyID].CipherAlg; \
- } \
- else SetAsicWcidAttri.Cipher = 0; \
- DBGPRINT(RT_DEBUG_TRACE, ("aid cipher = %ld\n",SetAsicWcidAttri.Cipher)); \
- RTUSBEnqueueInternalCmd(pAd, CMDTHREAD_SET_ASIC_WCID_CIPHER, \
- &SetAsicWcidAttri, sizeof(struct rt_set_asic_wcid_attri)); } }
-
-/* Insert the BA bitmap to ASIC for the Wcid entry */
-#define RTMP_ADD_BA_SESSION_TO_ASIC(_pAd, _Aid, _TID) \
- do{ \
- struct rt_set_asic_wcid SetAsicWcid; \
- SetAsicWcid.WCID = (_Aid); \
- SetAsicWcid.SetTid = (0x10000<<(_TID)); \
- SetAsicWcid.DeleteTid = 0xffffffff; \
- RTUSBEnqueueInternalCmd((_pAd), CMDTHREAD_SET_ASIC_WCID, &SetAsicWcid, sizeof(struct rt_set_asic_wcid)); \
- }while(0)
-
-/* Remove the BA bitmap from ASIC for the Wcid entry */
-#define RTMP_DEL_BA_SESSION_FROM_ASIC(_pAd, _Wcid, _TID) \
- do{ \
- struct rt_set_asic_wcid SetAsicWcid; \
- SetAsicWcid.WCID = (_Wcid); \
- SetAsicWcid.SetTid = (0xffffffff); \
- SetAsicWcid.DeleteTid = (0x10000<<(_TID) ); \
- RTUSBEnqueueInternalCmd((_pAd), CMDTHREAD_SET_ASIC_WCID, &SetAsicWcid, sizeof(struct rt_set_asic_wcid)); \
- }while(0)
-
-#endif /* __RTUSB_IO_H__ // */
diff --git a/drivers/staging/rt2860/spectrum.h b/drivers/staging/rt2860/spectrum.h
deleted file mode 100644
index 4c325ba..0000000
--- a/drivers/staging/rt2860/spectrum.h
+++ /dev/null
@@ -1,189 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
- */
-
-#ifndef __SPECTRUM_H__
-#define __SPECTRUM_H__
-
-#include "rtmp_type.h"
-#include "spectrum_def.h"
-
-char RTMP_GetTxPwr(struct rt_rtmp_adapter *pAd, IN HTTRANSMIT_SETTING HTTxMode);
-
-/*
- ==========================================================================
- Description:
- Prepare Measurement request action frame and enqueue it into
- management queue waiting for transmission.
-
- Parametrs:
- 1. the destination mac address of the frame.
-
- Return : None.
- ==========================================================================
- */
-void MakeMeasurementReqFrame(struct rt_rtmp_adapter *pAd,
- u8 *pOutBuffer,
- unsigned long *pFrameLen,
- u8 TotalLen,
- u8 Category,
- u8 Action,
- u8 MeasureToken,
- u8 MeasureReqMode,
- u8 MeasureReqType,
- u8 NumOfRepetitions);
-
-/*
- ==========================================================================
- Description:
- Prepare Measurement report action frame and enqueue it into
- management queue waiting for transmission.
-
- Parametrs:
- 1. the destination mac address of the frame.
-
- Return : None.
- ==========================================================================
- */
-void EnqueueMeasurementRep(struct rt_rtmp_adapter *pAd,
- u8 *pDA,
- u8 DialogToken,
- u8 MeasureToken,
- u8 MeasureReqMode,
- u8 MeasureReqType,
- u8 ReportInfoLen, u8 *pReportInfo);
-
-/*
- ==========================================================================
- Description:
- Prepare TPC Request action frame and enqueue it into
- management queue waiting for transmission.
-
- Parametrs:
- 1. the destination mac address of the frame.
-
- Return : None.
- ==========================================================================
- */
-void EnqueueTPCReq(struct rt_rtmp_adapter *pAd, u8 *pDA, u8 DialogToken);
-
-/*
- ==========================================================================
- Description:
- Prepare TPC Report action frame and enqueue it into
- management queue waiting for transmission.
-
- Parametrs:
- 1. the destination mac address of the frame.
-
- Return : None.
- ==========================================================================
- */
-void EnqueueTPCRep(struct rt_rtmp_adapter *pAd,
- u8 *pDA,
- u8 DialogToken, u8 TxPwr, u8 LinkMargin);
-
-/*
- ==========================================================================
- Description:
- Prepare Channel Switch Announcement action frame and enqueue it into
- management queue waiting for transmission.
-
- Parametrs:
- 1. the destination mac address of the frame.
- 2. Channel switch announcement mode.
- 2. a New selected channel.
-
- Return : None.
- ==========================================================================
- */
-void EnqueueChSwAnn(struct rt_rtmp_adapter *pAd,
- u8 *pDA, u8 ChSwMode, u8 NewCh);
-
-/*
- ==========================================================================
- Description:
- Spectrun action frames Handler such as channel switch announcement,
- measurement report, measurement request actions frames.
-
- Parametrs:
- Elme - MLME message containing the received frame
-
- Return : None.
- ==========================================================================
- */
-void PeerSpectrumAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem);
-
-/*
- ==========================================================================
- Description:
-
- Parametrs:
-
- Return : None.
- ==========================================================================
- */
-int Set_MeasureReq_Proc(struct rt_rtmp_adapter *pAd, char *arg);
-
-int Set_TpcReq_Proc(struct rt_rtmp_adapter *pAd, char *arg);
-
-int Set_PwrConstraint(struct rt_rtmp_adapter *pAd, char *arg);
-
-void MeasureReqTabInit(struct rt_rtmp_adapter *pAd);
-
-void MeasureReqTabExit(struct rt_rtmp_adapter *pAd);
-
-struct rt_measure_req_entry *MeasureReqLookUp(struct rt_rtmp_adapter *pAd, u8 DialogToken);
-
-struct rt_measure_req_entry *MeasureReqInsert(struct rt_rtmp_adapter *pAd, u8 DialogToken);
-
-void MeasureReqDelete(struct rt_rtmp_adapter *pAd, u8 DialogToken);
-
-void InsertChannelRepIE(struct rt_rtmp_adapter *pAd,
- u8 *pFrameBuf,
- unsigned long *pFrameLen,
- char *pCountry, u8 RegulatoryClass);
-
-void InsertTpcReportIE(struct rt_rtmp_adapter *pAd,
- u8 *pFrameBuf,
- unsigned long *pFrameLen,
- u8 TxPwr, u8 LinkMargin);
-
-void InsertDialogToken(struct rt_rtmp_adapter *pAd,
- u8 *pFrameBuf,
- unsigned long *pFrameLen, u8 DialogToken);
-
-void TpcReqTabInit(struct rt_rtmp_adapter *pAd);
-
-void TpcReqTabExit(struct rt_rtmp_adapter *pAd);
-
-void NotifyChSwAnnToPeerAPs(struct rt_rtmp_adapter *pAd,
- u8 *pRA,
- u8 *pTA, u8 ChSwMode, u8 Channel);
-
-void RguClass_BuildBcnChList(struct rt_rtmp_adapter *pAd,
- u8 *pBuf, unsigned long *pBufLen);
-#endif /* __SPECTRUM_H__ // */
diff --git a/drivers/staging/rt2860/spectrum_def.h b/drivers/staging/rt2860/spectrum_def.h
deleted file mode 100644
index 8ffcfb0d..0000000
--- a/drivers/staging/rt2860/spectrum_def.h
+++ /dev/null
@@ -1,202 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- spectrum_def.h
-
- Abstract:
- Handle association related requests either from WSTA or from local MLME
-
- Revision History:
- Who When What
- --------- ---------- ----------------------------------------------
- Fonchi Wu 2008 created for 802.11h
- */
-
-#ifndef __SPECTRUM_DEF_H__
-#define __SPECTRUM_DEF_H__
-
-#define MAX_MEASURE_REQ_TAB_SIZE 32
-#define MAX_HASH_MEASURE_REQ_TAB_SIZE MAX_MEASURE_REQ_TAB_SIZE
-
-#define MAX_TPC_REQ_TAB_SIZE 32
-#define MAX_HASH_TPC_REQ_TAB_SIZE MAX_TPC_REQ_TAB_SIZE
-
-#define MIN_RCV_PWR 100 /* Negative value ((dBm) */
-
-#define TPC_REQ_AGE_OUT 500 /* ms */
-#define MQ_REQ_AGE_OUT 500 /* ms */
-
-#define TPC_DIALOGTOKEN_HASH_INDEX(_DialogToken) ((_DialogToken) % MAX_HASH_TPC_REQ_TAB_SIZE)
-#define MQ_DIALOGTOKEN_HASH_INDEX(_DialogToken) ((_DialogToken) % MAX_MEASURE_REQ_TAB_SIZE)
-
-struct rt_measure_req_entry;
-
-struct rt_measure_req_entry {
- struct rt_measure_req_entry *pNext;
- unsigned long lastTime;
- BOOLEAN Valid;
- u8 DialogToken;
- u8 MeasureDialogToken[3]; /* 0:basic measure, 1: CCA measure, 2: RPI_Histogram measure. */
-};
-
-struct rt_measure_req_tab {
- u8 Size;
- struct rt_measure_req_entry *Hash[MAX_HASH_MEASURE_REQ_TAB_SIZE];
- struct rt_measure_req_entry Content[MAX_MEASURE_REQ_TAB_SIZE];
-};
-
-struct rt_tpc_req_entry;
-
-struct rt_tpc_req_entry {
- struct rt_tpc_req_entry *pNext;
- unsigned long lastTime;
- BOOLEAN Valid;
- u8 DialogToken;
-};
-
-struct rt_tpc_req_tab {
- u8 Size;
- struct rt_tpc_req_entry *Hash[MAX_HASH_TPC_REQ_TAB_SIZE];
- struct rt_tpc_req_entry Content[MAX_TPC_REQ_TAB_SIZE];
-};
-
-/* The regulatory information */
-struct rt_dot11_channel_set {
- u8 NumberOfChannels;
- u8 MaxTxPwr;
- u8 ChannelList[16];
-};
-
-struct rt_dot11_regulatory_information {
- u8 RegulatoryClass;
- struct rt_dot11_channel_set ChannelSet;
-};
-
-#define RM_TPC_REQ 0
-#define RM_MEASURE_REQ 1
-
-#define RM_BASIC 0
-#define RM_CCA 1
-#define RM_RPI_HISTOGRAM 2
-#define RM_CH_LOAD 3
-#define RM_NOISE_HISTOGRAM 4
-
-struct PACKED rt_tpc_report_info {
- u8 TxPwr;
- u8 LinkMargin;
-};
-
-struct PACKED rt_ch_sw_ann_info {
- u8 ChSwMode;
- u8 Channel;
- u8 ChSwCnt;
-};
-
-typedef union PACKED _MEASURE_REQ_MODE {
- struct PACKED {
- u8 Parallel:1;
- u8 Enable:1;
- u8 Request:1;
- u8 Report:1;
- u8 DurationMandatory:1;
- u8:3;
- } field;
- u8 word;
-} MEASURE_REQ_MODE, *PMEASURE_REQ_MODE;
-
-struct PACKED rt_measure_req {
- u8 ChNum;
- u64 MeasureStartTime;
- u16 MeasureDuration;
-};
-
-struct PACKED rt_measure_req_info {
- u8 Token;
- MEASURE_REQ_MODE ReqMode;
- u8 ReqType;
- u8 Oct[0];
-};
-
-typedef union PACKED _MEASURE_BASIC_REPORT_MAP {
- struct PACKED {
- u8 BSS:1;
-
- u8 OfdmPreamble:1;
- u8 UnidentifiedSignal:1;
- u8 Radar:1;
- u8 Unmeasure:1;
- u8 Rev:3;
- } field;
- u8 word;
-} MEASURE_BASIC_REPORT_MAP, *PMEASURE_BASIC_REPORT_MAP;
-
-struct PACKED rt_measure_basic_report {
- u8 ChNum;
- u64 MeasureStartTime;
- u16 MeasureDuration;
- MEASURE_BASIC_REPORT_MAP Map;
-};
-
-struct PACKED rt_measure_cca_report {
- u8 ChNum;
- u64 MeasureStartTime;
- u16 MeasureDuration;
- u8 CCA_Busy_Fraction;
-};
-
-struct PACKED rt_measure_rpi_report {
- u8 ChNum;
- u64 MeasureStartTime;
- u16 MeasureDuration;
- u8 RPI_Density[8];
-};
-
-typedef union PACKED _MEASURE_REPORT_MODE {
- struct PACKED {
- u8 Late:1;
- u8 Incapable:1;
- u8 Refused:1;
- u8 Rev:5;
- } field;
- u8 word;
-} MEASURE_REPORT_MODE, *PMEASURE_REPORT_MODE;
-
-struct PACKED rt_measure_report_info {
- u8 Token;
- u8 ReportMode;
- u8 ReportType;
- u8 Octect[0];
-};
-
-struct PACKED rt_quiet_info {
- u8 QuietCnt;
- u8 QuietPeriod;
- u16 QuietDuration;
- u16 QuietOffset;
-};
-
-#endif /* __SPECTRUM_DEF_H__ // */
diff --git a/drivers/staging/rt2860/sta/assoc.c b/drivers/staging/rt2860/sta/assoc.c
deleted file mode 100644
index 59e931c3..0000000
--- a/drivers/staging/rt2860/sta/assoc.c
+++ /dev/null
@@ -1,1602 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- assoc.c
-
- Abstract:
-
- Revision History:
- Who When What
- -------- ---------- ----------------------------------------------
- John 2004-9-3 porting from RT2500
- Justin P. Mattock 11/07/2010 Fix typos
-*/
-#include "../rt_config.h"
-
-u8 CipherWpaTemplate[] = {
- 0xdd, /* WPA IE */
- 0x16, /* Length */
- 0x00, 0x50, 0xf2, 0x01, /* oui */
- 0x01, 0x00, /* Version */
- 0x00, 0x50, 0xf2, 0x02, /* Multicast */
- 0x01, 0x00, /* Number of unicast */
- 0x00, 0x50, 0xf2, 0x02, /* unicast */
- 0x01, 0x00, /* number of authentication method */
- 0x00, 0x50, 0xf2, 0x01 /* authentication */
-};
-
-u8 CipherWpa2Template[] = {
- 0x30, /* RSN IE */
- 0x14, /* Length */
- 0x01, 0x00, /* Version */
- 0x00, 0x0f, 0xac, 0x02, /* group cipher, TKIP */
- 0x01, 0x00, /* number of pairwise */
- 0x00, 0x0f, 0xac, 0x02, /* unicast */
- 0x01, 0x00, /* number of authentication method */
- 0x00, 0x0f, 0xac, 0x02, /* authentication */
- 0x00, 0x00, /* RSN capability */
-};
-
-u8 Ccx2IeInfo[] = { 0x00, 0x40, 0x96, 0x03, 0x02 };
-
-/*
- ==========================================================================
- Description:
- association state machine init, including state transition and timer init
- Parameters:
- S - pointer to the association state machine
-
- IRQL = PASSIVE_LEVEL
-
- ==========================================================================
- */
-void AssocStateMachineInit(struct rt_rtmp_adapter *pAd,
- struct rt_state_machine *S, OUT STATE_MACHINE_FUNC Trans[])
-{
- StateMachineInit(S, Trans, MAX_ASSOC_STATE, MAX_ASSOC_MSG,
- (STATE_MACHINE_FUNC) Drop, ASSOC_IDLE,
- ASSOC_MACHINE_BASE);
-
- /* first column */
- StateMachineSetAction(S, ASSOC_IDLE, MT2_MLME_ASSOC_REQ,
- (STATE_MACHINE_FUNC) MlmeAssocReqAction);
- StateMachineSetAction(S, ASSOC_IDLE, MT2_MLME_REASSOC_REQ,
- (STATE_MACHINE_FUNC) MlmeReassocReqAction);
- StateMachineSetAction(S, ASSOC_IDLE, MT2_MLME_DISASSOC_REQ,
- (STATE_MACHINE_FUNC) MlmeDisassocReqAction);
- StateMachineSetAction(S, ASSOC_IDLE, MT2_PEER_DISASSOC_REQ,
- (STATE_MACHINE_FUNC) PeerDisassocAction);
-
- /* second column */
- StateMachineSetAction(S, ASSOC_WAIT_RSP, MT2_MLME_ASSOC_REQ,
- (STATE_MACHINE_FUNC) InvalidStateWhenAssoc);
- StateMachineSetAction(S, ASSOC_WAIT_RSP, MT2_MLME_REASSOC_REQ,
- (STATE_MACHINE_FUNC) InvalidStateWhenReassoc);
- StateMachineSetAction(S, ASSOC_WAIT_RSP, MT2_MLME_DISASSOC_REQ,
- (STATE_MACHINE_FUNC)
- InvalidStateWhenDisassociate);
- StateMachineSetAction(S, ASSOC_WAIT_RSP, MT2_PEER_DISASSOC_REQ,
- (STATE_MACHINE_FUNC) PeerDisassocAction);
- StateMachineSetAction(S, ASSOC_WAIT_RSP, MT2_PEER_ASSOC_RSP,
- (STATE_MACHINE_FUNC) PeerAssocRspAction);
- /* */
- /* Patch 3Com AP MOde:3CRWE454G72 */
- /* We send Assoc request frame to this AP, it always send Reassoc Rsp not Associate Rsp. */
- /* */
- StateMachineSetAction(S, ASSOC_WAIT_RSP, MT2_PEER_REASSOC_RSP,
- (STATE_MACHINE_FUNC) PeerAssocRspAction);
- StateMachineSetAction(S, ASSOC_WAIT_RSP, MT2_ASSOC_TIMEOUT,
- (STATE_MACHINE_FUNC) AssocTimeoutAction);
-
- /* third column */
- StateMachineSetAction(S, REASSOC_WAIT_RSP, MT2_MLME_ASSOC_REQ,
- (STATE_MACHINE_FUNC) InvalidStateWhenAssoc);
- StateMachineSetAction(S, REASSOC_WAIT_RSP, MT2_MLME_REASSOC_REQ,
- (STATE_MACHINE_FUNC) InvalidStateWhenReassoc);
- StateMachineSetAction(S, REASSOC_WAIT_RSP, MT2_MLME_DISASSOC_REQ,
- (STATE_MACHINE_FUNC)
- InvalidStateWhenDisassociate);
- StateMachineSetAction(S, REASSOC_WAIT_RSP, MT2_PEER_DISASSOC_REQ,
- (STATE_MACHINE_FUNC) PeerDisassocAction);
- StateMachineSetAction(S, REASSOC_WAIT_RSP, MT2_PEER_REASSOC_RSP,
- (STATE_MACHINE_FUNC) PeerReassocRspAction);
- /* */
- /* Patch, AP doesn't send Reassociate Rsp frame to Station. */
- /* */
- StateMachineSetAction(S, REASSOC_WAIT_RSP, MT2_PEER_ASSOC_RSP,
- (STATE_MACHINE_FUNC) PeerReassocRspAction);
- StateMachineSetAction(S, REASSOC_WAIT_RSP, MT2_REASSOC_TIMEOUT,
- (STATE_MACHINE_FUNC) ReassocTimeoutAction);
-
- /* fourth column */
- StateMachineSetAction(S, DISASSOC_WAIT_RSP, MT2_MLME_ASSOC_REQ,
- (STATE_MACHINE_FUNC) InvalidStateWhenAssoc);
- StateMachineSetAction(S, DISASSOC_WAIT_RSP, MT2_MLME_REASSOC_REQ,
- (STATE_MACHINE_FUNC) InvalidStateWhenReassoc);
- StateMachineSetAction(S, DISASSOC_WAIT_RSP, MT2_MLME_DISASSOC_REQ,
- (STATE_MACHINE_FUNC)
- InvalidStateWhenDisassociate);
- StateMachineSetAction(S, DISASSOC_WAIT_RSP, MT2_PEER_DISASSOC_REQ,
- (STATE_MACHINE_FUNC) PeerDisassocAction);
- StateMachineSetAction(S, DISASSOC_WAIT_RSP, MT2_DISASSOC_TIMEOUT,
- (STATE_MACHINE_FUNC) DisassocTimeoutAction);
-
- /* initialize the timer */
- RTMPInitTimer(pAd, &pAd->MlmeAux.AssocTimer,
- GET_TIMER_FUNCTION(AssocTimeout), pAd, FALSE);
- RTMPInitTimer(pAd, &pAd->MlmeAux.ReassocTimer,
- GET_TIMER_FUNCTION(ReassocTimeout), pAd, FALSE);
- RTMPInitTimer(pAd, &pAd->MlmeAux.DisassocTimer,
- GET_TIMER_FUNCTION(DisassocTimeout), pAd, FALSE);
-}
-
-/*
- ==========================================================================
- Description:
- Association timeout procedure. After association timeout, this function
- will be called and it will put a message into the MLME queue
- Parameters:
- Standard timer parameters
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
- */
-void AssocTimeout(void *SystemSpecific1,
- void *FunctionContext,
- void *SystemSpecific2, void *SystemSpecific3)
-{
- struct rt_rtmp_adapter *pAd = (struct rt_rtmp_adapter *)FunctionContext;
-
- /* Do nothing if the driver is starting halt state. */
- /* This might happen when timer already been fired before cancel timer with mlmehalt */
- if (RTMP_TEST_FLAG
- (pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS | fRTMP_ADAPTER_NIC_NOT_EXIST))
- return;
-
- MlmeEnqueue(pAd, ASSOC_STATE_MACHINE, MT2_ASSOC_TIMEOUT, 0, NULL);
- RTMP_MLME_HANDLER(pAd);
-}
-
-/*
- ==========================================================================
- Description:
- Reassociation timeout procedure. After reassociation timeout, this
- function will be called and put a message into the MLME queue
- Parameters:
- Standard timer parameters
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
- */
-void ReassocTimeout(void *SystemSpecific1,
- void *FunctionContext,
- void *SystemSpecific2, void *SystemSpecific3)
-{
- struct rt_rtmp_adapter *pAd = (struct rt_rtmp_adapter *)FunctionContext;
-
- /* Do nothing if the driver is starting halt state. */
- /* This might happen when timer already been fired before cancel timer with mlmehalt */
- if (RTMP_TEST_FLAG
- (pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS | fRTMP_ADAPTER_NIC_NOT_EXIST))
- return;
-
- MlmeEnqueue(pAd, ASSOC_STATE_MACHINE, MT2_REASSOC_TIMEOUT, 0, NULL);
- RTMP_MLME_HANDLER(pAd);
-}
-
-/*
- ==========================================================================
- Description:
- Disassociation timeout procedure. After disassociation timeout, this
- function will be called and put a message into the MLME queue
- Parameters:
- Standard timer parameters
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
- */
-void DisassocTimeout(void *SystemSpecific1,
- void *FunctionContext,
- void *SystemSpecific2, void *SystemSpecific3)
-{
- struct rt_rtmp_adapter *pAd = (struct rt_rtmp_adapter *)FunctionContext;
-
- /* Do nothing if the driver is starting halt state. */
- /* This might happen when timer already been fired before cancel timer with mlmehalt */
- if (RTMP_TEST_FLAG
- (pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS | fRTMP_ADAPTER_NIC_NOT_EXIST))
- return;
-
- MlmeEnqueue(pAd, ASSOC_STATE_MACHINE, MT2_DISASSOC_TIMEOUT, 0, NULL);
- RTMP_MLME_HANDLER(pAd);
-}
-
-/*
- ==========================================================================
- Description:
- mlme assoc req handling procedure
- Parameters:
- Adapter - Adapter pointer
- Elem - MLME Queue Element
- Pre:
- the station has been authenticated and the following information is stored in the config
- -# SSID
- -# supported rates and their length
- -# listen interval (Adapter->StaCfg.default_listen_count)
- -# Transmit power (Adapter->StaCfg.tx_power)
- Post :
- -# An association request frame is generated and sent to the air
- -# Association timer starts
- -# Association state -> ASSOC_WAIT_RSP
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
- */
-void MlmeAssocReqAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
- u8 ApAddr[6];
- struct rt_header_802_11 AssocHdr;
- u8 WmeIe[9] =
- { IE_VENDOR_SPECIFIC, 0x07, 0x00, 0x50, 0xf2, 0x02, 0x00, 0x01,
- 0x00 };
- u16 ListenIntv;
- unsigned long Timeout;
- u16 CapabilityInfo;
- BOOLEAN TimerCancelled;
- u8 *pOutBuffer = NULL;
- int NStatus;
- unsigned long FrameLen = 0;
- unsigned long tmp;
- u16 VarIesOffset;
- u16 Status;
-
- /* Block all authentication request during WPA block period */
- if (pAd->StaCfg.bBlockAssoc == TRUE) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("ASSOC - Block Assoc request during WPA block period!\n"));
- pAd->Mlme.AssocMachine.CurrState = ASSOC_IDLE;
- Status = MLME_STATE_MACHINE_REJECT;
- MlmeEnqueue(pAd, MLME_CNTL_STATE_MACHINE, MT2_ASSOC_CONF, 2,
- &Status);
- }
- /* check sanity first */
- else if (MlmeAssocReqSanity
- (pAd, Elem->Msg, Elem->MsgLen, ApAddr, &CapabilityInfo,
- &Timeout, &ListenIntv)) {
- RTMPCancelTimer(&pAd->MlmeAux.AssocTimer, &TimerCancelled);
- COPY_MAC_ADDR(pAd->MlmeAux.Bssid, ApAddr);
-
- /* Get an unused nonpaged memory */
- NStatus = MlmeAllocateMemory(pAd, &pOutBuffer);
- if (NStatus != NDIS_STATUS_SUCCESS) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("ASSOC - MlmeAssocReqAction() allocate memory failed \n"));
- pAd->Mlme.AssocMachine.CurrState = ASSOC_IDLE;
- Status = MLME_FAIL_NO_RESOURCE;
- MlmeEnqueue(pAd, MLME_CNTL_STATE_MACHINE,
- MT2_ASSOC_CONF, 2, &Status);
- return;
- }
- /* Add by James 03/06/27 */
- pAd->StaCfg.AssocInfo.Length =
- sizeof(struct rt_ndis_802_11_association_information);
- /* Association don't need to report MAC address */
- pAd->StaCfg.AssocInfo.AvailableRequestFixedIEs =
- NDIS_802_11_AI_REQFI_CAPABILITIES |
- NDIS_802_11_AI_REQFI_LISTENINTERVAL;
- pAd->StaCfg.AssocInfo.RequestFixedIEs.Capabilities =
- CapabilityInfo;
- pAd->StaCfg.AssocInfo.RequestFixedIEs.ListenInterval =
- ListenIntv;
- /* Only reassociate need this */
- /*COPY_MAC_ADDR(pAd->StaCfg.AssocInfo.RequestFixedIEs.CurrentAPAddress, ApAddr); */
- pAd->StaCfg.AssocInfo.OffsetRequestIEs =
- sizeof(struct rt_ndis_802_11_association_information);
-
- NdisZeroMemory(pAd->StaCfg.ReqVarIEs, MAX_VIE_LEN);
- /* First add SSID */
- VarIesOffset = 0;
- NdisMoveMemory(pAd->StaCfg.ReqVarIEs + VarIesOffset, &SsidIe,
- 1);
- VarIesOffset += 1;
- NdisMoveMemory(pAd->StaCfg.ReqVarIEs + VarIesOffset,
- &pAd->MlmeAux.SsidLen, 1);
- VarIesOffset += 1;
- NdisMoveMemory(pAd->StaCfg.ReqVarIEs + VarIesOffset,
- pAd->MlmeAux.Ssid, pAd->MlmeAux.SsidLen);
- VarIesOffset += pAd->MlmeAux.SsidLen;
-
- /* Second add Supported rates */
- NdisMoveMemory(pAd->StaCfg.ReqVarIEs + VarIesOffset, &SupRateIe,
- 1);
- VarIesOffset += 1;
- NdisMoveMemory(pAd->StaCfg.ReqVarIEs + VarIesOffset,
- &pAd->MlmeAux.SupRateLen, 1);
- VarIesOffset += 1;
- NdisMoveMemory(pAd->StaCfg.ReqVarIEs + VarIesOffset,
- pAd->MlmeAux.SupRate, pAd->MlmeAux.SupRateLen);
- VarIesOffset += pAd->MlmeAux.SupRateLen;
- /* End Add by James */
-
- if ((pAd->CommonCfg.Channel > 14) &&
- (pAd->CommonCfg.bIEEE80211H == TRUE))
- CapabilityInfo |= 0x0100;
-
- DBGPRINT(RT_DEBUG_TRACE, ("ASSOC - Send ASSOC request...\n"));
- MgtMacHeaderInit(pAd, &AssocHdr, SUBTYPE_ASSOC_REQ, 0, ApAddr,
- ApAddr);
-
- /* Build basic frame first */
- MakeOutgoingFrame(pOutBuffer, &FrameLen,
- sizeof(struct rt_header_802_11), &AssocHdr,
- 2, &CapabilityInfo,
- 2, &ListenIntv,
- 1, &SsidIe,
- 1, &pAd->MlmeAux.SsidLen,
- pAd->MlmeAux.SsidLen, pAd->MlmeAux.Ssid,
- 1, &SupRateIe,
- 1, &pAd->MlmeAux.SupRateLen,
- pAd->MlmeAux.SupRateLen, pAd->MlmeAux.SupRate,
- END_OF_ARGS);
-
- if (pAd->MlmeAux.ExtRateLen != 0) {
- MakeOutgoingFrame(pOutBuffer + FrameLen, &tmp,
- 1, &ExtRateIe,
- 1, &pAd->MlmeAux.ExtRateLen,
- pAd->MlmeAux.ExtRateLen,
- pAd->MlmeAux.ExtRate, END_OF_ARGS);
- FrameLen += tmp;
- }
- /* HT */
- if ((pAd->MlmeAux.HtCapabilityLen > 0)
- && (pAd->CommonCfg.PhyMode >= PHY_11ABGN_MIXED)) {
- unsigned long TmpLen;
- u8 HtLen;
- u8 BROADCOM[4] = { 0x0, 0x90, 0x4c, 0x33 };
- if (pAd->StaActive.SupportedPhyInfo.bPreNHt == TRUE) {
- HtLen = SIZE_HT_CAP_IE + 4;
- MakeOutgoingFrame(pOutBuffer + FrameLen,
- &TmpLen, 1, &WpaIe, 1, &HtLen,
- 4, &BROADCOM[0],
- pAd->MlmeAux.HtCapabilityLen,
- &pAd->MlmeAux.HtCapability,
- END_OF_ARGS);
- } else {
- MakeOutgoingFrame(pOutBuffer + FrameLen,
- &TmpLen, 1, &HtCapIe, 1,
- &pAd->MlmeAux.HtCapabilityLen,
- pAd->MlmeAux.HtCapabilityLen,
- &pAd->MlmeAux.HtCapability,
- END_OF_ARGS);
- }
- FrameLen += TmpLen;
- }
- /* add Ralink proprietary IE to inform AP this STA is going to use AGGREGATION or PIGGY-BACK+AGGREGATION */
- /* Case I: (Aggregation + Piggy-Back) */
- /* 1. user enable aggregation, AND */
- /* 2. Mac support piggy-back */
- /* 3. AP annouces it's PIGGY-BACK+AGGREGATION-capable in BEACON */
- /* Case II: (Aggregation) */
- /* 1. user enable aggregation, AND */
- /* 2. AP annouces it's AGGREGATION-capable in BEACON */
- if (pAd->CommonCfg.bAggregationCapable) {
- if ((pAd->CommonCfg.bPiggyBackCapable)
- && ((pAd->MlmeAux.APRalinkIe & 0x00000003) == 3)) {
- unsigned long TmpLen;
- u8 RalinkIe[9] =
- { IE_VENDOR_SPECIFIC, 7, 0x00, 0x0c, 0x43,
- 0x03, 0x00, 0x00, 0x00 };
- MakeOutgoingFrame(pOutBuffer + FrameLen,
- &TmpLen, 9, RalinkIe,
- END_OF_ARGS);
- FrameLen += TmpLen;
- } else if (pAd->MlmeAux.APRalinkIe & 0x00000001) {
- unsigned long TmpLen;
- u8 RalinkIe[9] =
- { IE_VENDOR_SPECIFIC, 7, 0x00, 0x0c, 0x43,
- 0x01, 0x00, 0x00, 0x00 };
- MakeOutgoingFrame(pOutBuffer + FrameLen,
- &TmpLen, 9, RalinkIe,
- END_OF_ARGS);
- FrameLen += TmpLen;
- }
- } else {
- unsigned long TmpLen;
- u8 RalinkIe[9] =
- { IE_VENDOR_SPECIFIC, 7, 0x00, 0x0c, 0x43, 0x06,
- 0x00, 0x00, 0x00 };
- MakeOutgoingFrame(pOutBuffer + FrameLen, &TmpLen, 9,
- RalinkIe, END_OF_ARGS);
- FrameLen += TmpLen;
- }
-
- if (pAd->MlmeAux.APEdcaParm.bValid) {
- if (pAd->CommonCfg.bAPSDCapable
- && pAd->MlmeAux.APEdcaParm.bAPSDCapable) {
- struct rt_qbss_sta_info_parm QosInfo;
-
- NdisZeroMemory(&QosInfo,
- sizeof(struct rt_qbss_sta_info_parm));
- QosInfo.UAPSD_AC_BE = pAd->CommonCfg.bAPSDAC_BE;
- QosInfo.UAPSD_AC_BK = pAd->CommonCfg.bAPSDAC_BK;
- QosInfo.UAPSD_AC_VI = pAd->CommonCfg.bAPSDAC_VI;
- QosInfo.UAPSD_AC_VO = pAd->CommonCfg.bAPSDAC_VO;
- QosInfo.MaxSPLength =
- pAd->CommonCfg.MaxSPLength;
- WmeIe[8] |= *(u8 *)& QosInfo;
- } else {
- /* The Parameter Set Count is set to ¡§0¡¨ in the association request frames */
- /* WmeIe[8] |= (pAd->MlmeAux.APEdcaParm.EdcaUpdateCount & 0x0f); */
- }
-
- MakeOutgoingFrame(pOutBuffer + FrameLen, &tmp,
- 9, &WmeIe[0], END_OF_ARGS);
- FrameLen += tmp;
- }
- /* */
- /* Let WPA(#221) Element ID on the end of this association frame. */
- /* Otherwise some AP will fail on parsing Element ID and set status fail on Assoc Rsp. */
- /* For example: Put Vendor Specific IE on the front of WPA IE. */
- /* This happens on AP (Model No:Linksys WRK54G) */
- /* */
- if (((pAd->StaCfg.AuthMode == Ndis802_11AuthModeWPAPSK) ||
- (pAd->StaCfg.AuthMode == Ndis802_11AuthModeWPA2PSK) ||
- (pAd->StaCfg.AuthMode == Ndis802_11AuthModeWPA) ||
- (pAd->StaCfg.AuthMode == Ndis802_11AuthModeWPA2)
- )
- ) {
- u8 RSNIe = IE_WPA;
-
- if ((pAd->StaCfg.AuthMode == Ndis802_11AuthModeWPA2PSK)
- || (pAd->StaCfg.AuthMode ==
- Ndis802_11AuthModeWPA2)) {
- RSNIe = IE_WPA2;
- }
-
- if ((pAd->StaCfg.WpaSupplicantUP !=
- WPA_SUPPLICANT_ENABLE)
- && (pAd->StaCfg.bRSN_IE_FromWpaSupplicant == FALSE))
- RTMPMakeRSNIE(pAd, pAd->StaCfg.AuthMode,
- pAd->StaCfg.WepStatus, BSS0);
-
- /* Check for WPA PMK cache list */
- if (pAd->StaCfg.AuthMode == Ndis802_11AuthModeWPA2) {
- int idx;
- BOOLEAN FoundPMK = FALSE;
- /* Search chched PMKID, append it if existed */
- for (idx = 0; idx < PMKID_NO; idx++) {
- if (NdisEqualMemory
- (ApAddr,
- &pAd->StaCfg.SavedPMK[idx].BSSID,
- 6)) {
- FoundPMK = TRUE;
- break;
- }
- }
- if (FoundPMK) {
- /* Set PMK number */
- *(u16 *)& pAd->StaCfg.RSN_IE[pAd->
- StaCfg.
- RSNIE_Len]
- = 1;
- NdisMoveMemory(&pAd->StaCfg.
- RSN_IE[pAd->StaCfg.
- RSNIE_Len + 2],
- &pAd->StaCfg.
- SavedPMK[idx].PMKID, 16);
- pAd->StaCfg.RSNIE_Len += 18;
- }
- }
-
- if ((pAd->StaCfg.WpaSupplicantUP ==
- WPA_SUPPLICANT_ENABLE)
- && (pAd->StaCfg.bRSN_IE_FromWpaSupplicant ==
- TRUE)) {
- MakeOutgoingFrame(pOutBuffer + FrameLen, &tmp,
- pAd->StaCfg.RSNIE_Len,
- pAd->StaCfg.RSN_IE,
- END_OF_ARGS);
- } else {
- MakeOutgoingFrame(pOutBuffer + FrameLen, &tmp,
- 1, &RSNIe,
- 1, &pAd->StaCfg.RSNIE_Len,
- pAd->StaCfg.RSNIE_Len,
- pAd->StaCfg.RSN_IE,
- END_OF_ARGS);
- }
-
- FrameLen += tmp;
-
- if ((pAd->StaCfg.WpaSupplicantUP !=
- WPA_SUPPLICANT_ENABLE)
- || (pAd->StaCfg.bRSN_IE_FromWpaSupplicant ==
- FALSE)) {
- /* Append Variable IE */
- NdisMoveMemory(pAd->StaCfg.ReqVarIEs +
- VarIesOffset, &RSNIe, 1);
- VarIesOffset += 1;
- NdisMoveMemory(pAd->StaCfg.ReqVarIEs +
- VarIesOffset,
- &pAd->StaCfg.RSNIE_Len, 1);
- VarIesOffset += 1;
- }
- NdisMoveMemory(pAd->StaCfg.ReqVarIEs + VarIesOffset,
- pAd->StaCfg.RSN_IE,
- pAd->StaCfg.RSNIE_Len);
- VarIesOffset += pAd->StaCfg.RSNIE_Len;
-
- /* Set Variable IEs Length */
- pAd->StaCfg.ReqVarIELen = VarIesOffset;
- }
-
- MiniportMMRequest(pAd, 0, pOutBuffer, FrameLen);
- MlmeFreeMemory(pAd, pOutBuffer);
-
- RTMPSetTimer(&pAd->MlmeAux.AssocTimer, Timeout);
- pAd->Mlme.AssocMachine.CurrState = ASSOC_WAIT_RSP;
- } else {
- DBGPRINT(RT_DEBUG_TRACE,
- ("ASSOC - MlmeAssocReqAction() sanity check failed. BUG!\n"));
- pAd->Mlme.AssocMachine.CurrState = ASSOC_IDLE;
- Status = MLME_INVALID_FORMAT;
- MlmeEnqueue(pAd, MLME_CNTL_STATE_MACHINE, MT2_ASSOC_CONF, 2,
- &Status);
- }
-
-}
-
-/*
- ==========================================================================
- Description:
- mlme reassoc req handling procedure
- Parameters:
- Elem -
- Pre:
- -# SSID (Adapter->StaCfg.ssid[])
- -# BSSID (AP address, Adapter->StaCfg.bssid)
- -# Supported rates (Adapter->StaCfg.supported_rates[])
- -# Supported rates length (Adapter->StaCfg.supported_rates_len)
- -# Tx power (Adapter->StaCfg.tx_power)
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
- */
-void MlmeReassocReqAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
- u8 ApAddr[6];
- struct rt_header_802_11 ReassocHdr;
- u8 WmeIe[9] =
- { IE_VENDOR_SPECIFIC, 0x07, 0x00, 0x50, 0xf2, 0x02, 0x00, 0x01,
- 0x00 };
- u16 CapabilityInfo, ListenIntv;
- unsigned long Timeout;
- unsigned long FrameLen = 0;
- BOOLEAN TimerCancelled;
- int NStatus;
- unsigned long tmp;
- u8 *pOutBuffer = NULL;
- u16 Status;
-
- /* Block all authentication request during WPA block period */
- if (pAd->StaCfg.bBlockAssoc == TRUE) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("ASSOC - Block ReAssoc request during WPA block period!\n"));
- pAd->Mlme.AssocMachine.CurrState = ASSOC_IDLE;
- Status = MLME_STATE_MACHINE_REJECT;
- MlmeEnqueue(pAd, MLME_CNTL_STATE_MACHINE, MT2_REASSOC_CONF, 2,
- &Status);
- }
- /* the parameters are the same as the association */
- else if (MlmeAssocReqSanity
- (pAd, Elem->Msg, Elem->MsgLen, ApAddr, &CapabilityInfo,
- &Timeout, &ListenIntv)) {
- RTMPCancelTimer(&pAd->MlmeAux.ReassocTimer, &TimerCancelled);
-
- NStatus = MlmeAllocateMemory(pAd, &pOutBuffer); /*Get an unused nonpaged memory */
- if (NStatus != NDIS_STATUS_SUCCESS) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("ASSOC - MlmeReassocReqAction() allocate memory failed \n"));
- pAd->Mlme.AssocMachine.CurrState = ASSOC_IDLE;
- Status = MLME_FAIL_NO_RESOURCE;
- MlmeEnqueue(pAd, MLME_CNTL_STATE_MACHINE,
- MT2_REASSOC_CONF, 2, &Status);
- return;
- }
-
- COPY_MAC_ADDR(pAd->MlmeAux.Bssid, ApAddr);
-
- /* make frame, use bssid as the AP address?? */
- DBGPRINT(RT_DEBUG_TRACE,
- ("ASSOC - Send RE-ASSOC request...\n"));
- MgtMacHeaderInit(pAd, &ReassocHdr, SUBTYPE_REASSOC_REQ, 0,
- ApAddr, ApAddr);
- MakeOutgoingFrame(pOutBuffer, &FrameLen, sizeof(struct rt_header_802_11),
- &ReassocHdr, 2, &CapabilityInfo, 2,
- &ListenIntv, MAC_ADDR_LEN, ApAddr, 1, &SsidIe,
- 1, &pAd->MlmeAux.SsidLen,
- pAd->MlmeAux.SsidLen, pAd->MlmeAux.Ssid, 1,
- &SupRateIe, 1, &pAd->MlmeAux.SupRateLen,
- pAd->MlmeAux.SupRateLen, pAd->MlmeAux.SupRate,
- END_OF_ARGS);
-
- if (pAd->MlmeAux.ExtRateLen != 0) {
- MakeOutgoingFrame(pOutBuffer + FrameLen, &tmp,
- 1, &ExtRateIe,
- 1, &pAd->MlmeAux.ExtRateLen,
- pAd->MlmeAux.ExtRateLen,
- pAd->MlmeAux.ExtRate, END_OF_ARGS);
- FrameLen += tmp;
- }
-
- if (pAd->MlmeAux.APEdcaParm.bValid) {
- if (pAd->CommonCfg.bAPSDCapable
- && pAd->MlmeAux.APEdcaParm.bAPSDCapable) {
- struct rt_qbss_sta_info_parm QosInfo;
-
- NdisZeroMemory(&QosInfo,
- sizeof(struct rt_qbss_sta_info_parm));
- QosInfo.UAPSD_AC_BE = pAd->CommonCfg.bAPSDAC_BE;
- QosInfo.UAPSD_AC_BK = pAd->CommonCfg.bAPSDAC_BK;
- QosInfo.UAPSD_AC_VI = pAd->CommonCfg.bAPSDAC_VI;
- QosInfo.UAPSD_AC_VO = pAd->CommonCfg.bAPSDAC_VO;
- QosInfo.MaxSPLength =
- pAd->CommonCfg.MaxSPLength;
- WmeIe[8] |= *(u8 *)& QosInfo;
- }
-
- MakeOutgoingFrame(pOutBuffer + FrameLen, &tmp,
- 9, &WmeIe[0], END_OF_ARGS);
- FrameLen += tmp;
- }
- /* HT */
- if ((pAd->MlmeAux.HtCapabilityLen > 0)
- && (pAd->CommonCfg.PhyMode >= PHY_11ABGN_MIXED)) {
- unsigned long TmpLen;
- u8 HtLen;
- u8 BROADCOM[4] = { 0x0, 0x90, 0x4c, 0x33 };
- if (pAd->StaActive.SupportedPhyInfo.bPreNHt == TRUE) {
- HtLen = SIZE_HT_CAP_IE + 4;
- MakeOutgoingFrame(pOutBuffer + FrameLen,
- &TmpLen, 1, &WpaIe, 1, &HtLen,
- 4, &BROADCOM[0],
- pAd->MlmeAux.HtCapabilityLen,
- &pAd->MlmeAux.HtCapability,
- END_OF_ARGS);
- } else {
- MakeOutgoingFrame(pOutBuffer + FrameLen,
- &TmpLen, 1, &HtCapIe, 1,
- &pAd->MlmeAux.HtCapabilityLen,
- pAd->MlmeAux.HtCapabilityLen,
- &pAd->MlmeAux.HtCapability,
- END_OF_ARGS);
- }
- FrameLen += TmpLen;
- }
- /* add Ralink proprietary IE to inform AP this STA is going to use AGGREGATION or PIGGY-BACK+AGGREGATION */
- /* Case I: (Aggregation + Piggy-Back) */
- /* 1. user enable aggregation, AND */
- /* 2. Mac support piggy-back */
- /* 3. AP annouces it's PIGGY-BACK+AGGREGATION-capable in BEACON */
- /* Case II: (Aggregation) */
- /* 1. user enable aggregation, AND */
- /* 2. AP annouces it's AGGREGATION-capable in BEACON */
- if (pAd->CommonCfg.bAggregationCapable) {
- if ((pAd->CommonCfg.bPiggyBackCapable)
- && ((pAd->MlmeAux.APRalinkIe & 0x00000003) == 3)) {
- unsigned long TmpLen;
- u8 RalinkIe[9] =
- { IE_VENDOR_SPECIFIC, 7, 0x00, 0x0c, 0x43,
- 0x03, 0x00, 0x00, 0x00 };
- MakeOutgoingFrame(pOutBuffer + FrameLen,
- &TmpLen, 9, RalinkIe,
- END_OF_ARGS);
- FrameLen += TmpLen;
- } else if (pAd->MlmeAux.APRalinkIe & 0x00000001) {
- unsigned long TmpLen;
- u8 RalinkIe[9] =
- { IE_VENDOR_SPECIFIC, 7, 0x00, 0x0c, 0x43,
- 0x01, 0x00, 0x00, 0x00 };
- MakeOutgoingFrame(pOutBuffer + FrameLen,
- &TmpLen, 9, RalinkIe,
- END_OF_ARGS);
- FrameLen += TmpLen;
- }
- } else {
- unsigned long TmpLen;
- u8 RalinkIe[9] =
- { IE_VENDOR_SPECIFIC, 7, 0x00, 0x0c, 0x43, 0x04,
- 0x00, 0x00, 0x00 };
- MakeOutgoingFrame(pOutBuffer + FrameLen, &TmpLen, 9,
- RalinkIe, END_OF_ARGS);
- FrameLen += TmpLen;
- }
-
- MiniportMMRequest(pAd, 0, pOutBuffer, FrameLen);
- MlmeFreeMemory(pAd, pOutBuffer);
-
- RTMPSetTimer(&pAd->MlmeAux.ReassocTimer, Timeout); /* in mSec */
- pAd->Mlme.AssocMachine.CurrState = REASSOC_WAIT_RSP;
- } else {
- DBGPRINT(RT_DEBUG_TRACE,
- ("ASSOC - MlmeReassocReqAction() sanity check failed. BUG!\n"));
- pAd->Mlme.AssocMachine.CurrState = ASSOC_IDLE;
- Status = MLME_INVALID_FORMAT;
- MlmeEnqueue(pAd, MLME_CNTL_STATE_MACHINE, MT2_REASSOC_CONF, 2,
- &Status);
- }
-}
-
-/*
- ==========================================================================
- Description:
- Upper layer issues disassoc request
- Parameters:
- Elem -
-
- IRQL = PASSIVE_LEVEL
-
- ==========================================================================
- */
-void MlmeDisassocReqAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
- struct rt_mlme_disassoc_req *pDisassocReq;
- struct rt_header_802_11 DisassocHdr;
- struct rt_header_802_11 * pDisassocHdr;
- u8 *pOutBuffer = NULL;
- unsigned long FrameLen = 0;
- int NStatus;
- BOOLEAN TimerCancelled;
- unsigned long Timeout = 500;
- u16 Status;
-
- /* skip sanity check */
- pDisassocReq = (struct rt_mlme_disassoc_req *)(Elem->Msg);
-
- NStatus = MlmeAllocateMemory(pAd, &pOutBuffer); /*Get an unused nonpaged memory */
- if (NStatus != NDIS_STATUS_SUCCESS) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("ASSOC - MlmeDisassocReqAction() allocate memory failed\n"));
- pAd->Mlme.AssocMachine.CurrState = ASSOC_IDLE;
- Status = MLME_FAIL_NO_RESOURCE;
- MlmeEnqueue(pAd, MLME_CNTL_STATE_MACHINE, MT2_DISASSOC_CONF, 2,
- &Status);
- return;
- }
-
- RTMPCancelTimer(&pAd->MlmeAux.DisassocTimer, &TimerCancelled);
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("ASSOC - Send DISASSOC request[BSSID::%pM (Reason=%d)\n",
- pDisassocReq->Addr, pDisassocReq->Reason));
- MgtMacHeaderInit(pAd, &DisassocHdr, SUBTYPE_DISASSOC, 0, pDisassocReq->Addr, pDisassocReq->Addr); /* patch peap ttls switching issue */
- MakeOutgoingFrame(pOutBuffer, &FrameLen,
- sizeof(struct rt_header_802_11), &DisassocHdr,
- 2, &pDisassocReq->Reason, END_OF_ARGS);
- MiniportMMRequest(pAd, 0, pOutBuffer, FrameLen);
-
- /* To patch Instance and Buffalo(N) AP */
- /* Driver has to send deauth to Instance AP, but Buffalo(N) needs to send disassoc to reset Authenticator's state machine */
- /* Therefore, we send both of them. */
- pDisassocHdr = (struct rt_header_802_11 *) pOutBuffer;
- pDisassocHdr->FC.SubType = SUBTYPE_DEAUTH;
- MiniportMMRequest(pAd, 0, pOutBuffer, FrameLen);
-
- MlmeFreeMemory(pAd, pOutBuffer);
-
- pAd->StaCfg.DisassocReason = REASON_DISASSOC_STA_LEAVING;
- COPY_MAC_ADDR(pAd->StaCfg.DisassocSta, pDisassocReq->Addr);
-
- RTMPSetTimer(&pAd->MlmeAux.DisassocTimer, Timeout); /* in mSec */
- pAd->Mlme.AssocMachine.CurrState = DISASSOC_WAIT_RSP;
-
- RtmpOSWrielessEventSend(pAd, SIOCGIWAP, -1, NULL, NULL, 0);
-
-}
-
-/*
- ==========================================================================
- Description:
- peer sends assoc rsp back
- Parameters:
- Elme - MLME message containing the received frame
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
- */
-void PeerAssocRspAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
- u16 CapabilityInfo, Status, Aid;
- u8 SupRate[MAX_LEN_OF_SUPPORTED_RATES], SupRateLen;
- u8 ExtRate[MAX_LEN_OF_SUPPORTED_RATES], ExtRateLen;
- u8 Addr2[MAC_ADDR_LEN];
- BOOLEAN TimerCancelled;
- u8 CkipFlag;
- struct rt_edca_parm EdcaParm;
- struct rt_ht_capability_ie HtCapability;
- struct rt_add_ht_info_ie AddHtInfo; /* AP might use this additional ht info IE */
- u8 HtCapabilityLen = 0;
- u8 AddHtInfoLen;
- u8 NewExtChannelOffset = 0xff;
-
- if (PeerAssocRspSanity
- (pAd, Elem->Msg, Elem->MsgLen, Addr2, &CapabilityInfo, &Status,
- &Aid, SupRate, &SupRateLen, ExtRate, &ExtRateLen, &HtCapability,
- &AddHtInfo, &HtCapabilityLen, &AddHtInfoLen, &NewExtChannelOffset,
- &EdcaParm, &CkipFlag)) {
- /* The frame is for me ? */
- if (MAC_ADDR_EQUAL(Addr2, pAd->MlmeAux.Bssid)) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("PeerAssocRspAction():ASSOC - receive ASSOC_RSP to me (status=%d)\n",
- Status));
- DBGPRINT(RT_DEBUG_TRACE,
- ("PeerAssocRspAction():MacTable [%d].AMsduSize = %d. ClientStatusFlags = 0x%lx \n",
- Elem->Wcid,
- pAd->MacTab.Content[BSSID_WCID].AMsduSize,
- pAd->MacTab.Content[BSSID_WCID].
- ClientStatusFlags));
- RTMPCancelTimer(&pAd->MlmeAux.AssocTimer,
- &TimerCancelled);
-
- if (Status == MLME_SUCCESS) {
- u8 MaxSupportedRateIn500Kbps = 0;
- u8 idx;
-
- /* supported rates array may not be sorted. sort it and find the maximum rate */
- for (idx = 0; idx < SupRateLen; idx++) {
- if (MaxSupportedRateIn500Kbps <
- (SupRate[idx] & 0x7f))
- MaxSupportedRateIn500Kbps =
- SupRate[idx] & 0x7f;
- }
-
- for (idx = 0; idx < ExtRateLen; idx++) {
- if (MaxSupportedRateIn500Kbps <
- (ExtRate[idx] & 0x7f))
- MaxSupportedRateIn500Kbps =
- ExtRate[idx] & 0x7f;
- }
- /* go to procedure listed on page 376 */
- AssocPostProc(pAd, Addr2, CapabilityInfo, Aid,
- SupRate, SupRateLen, ExtRate,
- ExtRateLen, &EdcaParm,
- &HtCapability, HtCapabilityLen,
- &AddHtInfo);
-
- StaAddMacTableEntry(pAd,
- &pAd->MacTab.
- Content[BSSID_WCID],
- MaxSupportedRateIn500Kbps,
- &HtCapability,
- HtCapabilityLen, &AddHtInfo,
- AddHtInfoLen,
- CapabilityInfo);
- }
- pAd->Mlme.AssocMachine.CurrState = ASSOC_IDLE;
- MlmeEnqueue(pAd, MLME_CNTL_STATE_MACHINE,
- MT2_ASSOC_CONF, 2, &Status);
- }
- } else {
- DBGPRINT(RT_DEBUG_TRACE,
- ("ASSOC - PeerAssocRspAction() sanity check fail\n"));
- }
-}
-
-/*
- ==========================================================================
- Description:
- peer sends reassoc rsp
- Parametrs:
- Elem - MLME message cntaining the received frame
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
- */
-void PeerReassocRspAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
- u16 CapabilityInfo;
- u16 Status;
- u16 Aid;
- u8 SupRate[MAX_LEN_OF_SUPPORTED_RATES], SupRateLen;
- u8 ExtRate[MAX_LEN_OF_SUPPORTED_RATES], ExtRateLen;
- u8 Addr2[MAC_ADDR_LEN];
- u8 CkipFlag;
- BOOLEAN TimerCancelled;
- struct rt_edca_parm EdcaParm;
- struct rt_ht_capability_ie HtCapability;
- struct rt_add_ht_info_ie AddHtInfo; /* AP might use this additional ht info IE */
- u8 HtCapabilityLen;
- u8 AddHtInfoLen;
- u8 NewExtChannelOffset = 0xff;
-
- if (PeerAssocRspSanity
- (pAd, Elem->Msg, Elem->MsgLen, Addr2, &CapabilityInfo, &Status,
- &Aid, SupRate, &SupRateLen, ExtRate, &ExtRateLen, &HtCapability,
- &AddHtInfo, &HtCapabilityLen, &AddHtInfoLen, &NewExtChannelOffset,
- &EdcaParm, &CkipFlag)) {
- if (MAC_ADDR_EQUAL(Addr2, pAd->MlmeAux.Bssid)) /* The frame is for me ? */
- {
- DBGPRINT(RT_DEBUG_TRACE,
- ("ASSOC - receive REASSOC_RSP to me (status=%d)\n",
- Status));
- RTMPCancelTimer(&pAd->MlmeAux.ReassocTimer,
- &TimerCancelled);
-
- if (Status == MLME_SUCCESS) {
- /* go to procedure listed on page 376 */
- AssocPostProc(pAd, Addr2, CapabilityInfo, Aid,
- SupRate, SupRateLen, ExtRate,
- ExtRateLen, &EdcaParm,
- &HtCapability, HtCapabilityLen,
- &AddHtInfo);
-
- {
- wext_notify_event_assoc(pAd);
- RtmpOSWrielessEventSend(pAd, SIOCGIWAP,
- -1,
- &pAd->MlmeAux.
- Bssid[0], NULL,
- 0);
- }
-
- }
- /* CkipFlag is no use for reassociate */
- pAd->Mlme.AssocMachine.CurrState = ASSOC_IDLE;
- MlmeEnqueue(pAd, MLME_CNTL_STATE_MACHINE,
- MT2_REASSOC_CONF, 2, &Status);
- }
- } else {
- DBGPRINT(RT_DEBUG_TRACE,
- ("ASSOC - PeerReassocRspAction() sanity check fail\n"));
- }
-
-}
-
-/*
- ==========================================================================
- Description:
- procedures on IEEE 802.11/1999 p.376
- Parametrs:
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
- */
-void AssocPostProc(struct rt_rtmp_adapter *pAd, u8 *pAddr2, u16 CapabilityInfo, u16 Aid, u8 SupRate[], u8 SupRateLen, u8 ExtRate[], u8 ExtRateLen, struct rt_edca_parm *pEdcaParm, struct rt_ht_capability_ie * pHtCapability, u8 HtCapabilityLen, struct rt_add_ht_info_ie * pAddHtInfo) /* AP might use this additional ht info IE */
-{
- unsigned long Idx;
-
- pAd->MlmeAux.BssType = BSS_INFRA;
- COPY_MAC_ADDR(pAd->MlmeAux.Bssid, pAddr2);
- pAd->MlmeAux.Aid = Aid;
- pAd->MlmeAux.CapabilityInfo =
- CapabilityInfo & SUPPORTED_CAPABILITY_INFO;
-
- /* Some HT AP might lost WMM IE. We add WMM ourselves. because HT requires QoS on. */
- if ((HtCapabilityLen > 0) && (pEdcaParm->bValid == FALSE)) {
- pEdcaParm->bValid = TRUE;
- pEdcaParm->Aifsn[0] = 3;
- pEdcaParm->Aifsn[1] = 7;
- pEdcaParm->Aifsn[2] = 2;
- pEdcaParm->Aifsn[3] = 2;
-
- pEdcaParm->Cwmin[0] = 4;
- pEdcaParm->Cwmin[1] = 4;
- pEdcaParm->Cwmin[2] = 3;
- pEdcaParm->Cwmin[3] = 2;
-
- pEdcaParm->Cwmax[0] = 10;
- pEdcaParm->Cwmax[1] = 10;
- pEdcaParm->Cwmax[2] = 4;
- pEdcaParm->Cwmax[3] = 3;
-
- pEdcaParm->Txop[0] = 0;
- pEdcaParm->Txop[1] = 0;
- pEdcaParm->Txop[2] = 96;
- pEdcaParm->Txop[3] = 48;
-
- }
-
- NdisMoveMemory(&pAd->MlmeAux.APEdcaParm, pEdcaParm, sizeof(struct rt_edca_parm));
-
- /* filter out un-supported rates */
- pAd->MlmeAux.SupRateLen = SupRateLen;
- NdisMoveMemory(pAd->MlmeAux.SupRate, SupRate, SupRateLen);
- RTMPCheckRates(pAd, pAd->MlmeAux.SupRate, &pAd->MlmeAux.SupRateLen);
-
- /* filter out un-supported rates */
- pAd->MlmeAux.ExtRateLen = ExtRateLen;
- NdisMoveMemory(pAd->MlmeAux.ExtRate, ExtRate, ExtRateLen);
- RTMPCheckRates(pAd, pAd->MlmeAux.ExtRate, &pAd->MlmeAux.ExtRateLen);
-
- if (HtCapabilityLen > 0) {
- RTMPCheckHt(pAd, BSSID_WCID, pHtCapability, pAddHtInfo);
- }
- DBGPRINT(RT_DEBUG_TRACE,
- ("AssocPostProc===> AP.AMsduSize = %d. ClientStatusFlags = 0x%lx \n",
- pAd->MacTab.Content[BSSID_WCID].AMsduSize,
- pAd->MacTab.Content[BSSID_WCID].ClientStatusFlags));
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("AssocPostProc===> (Mmps=%d, AmsduSize=%d, )\n",
- pAd->MacTab.Content[BSSID_WCID].MmpsMode,
- pAd->MacTab.Content[BSSID_WCID].AMsduSize));
-
- /* Set New WPA information */
- Idx = BssTableSearch(&pAd->ScanTab, pAddr2, pAd->MlmeAux.Channel);
- if (Idx == BSS_NOT_FOUND) {
- DBGPRINT_ERR("ASSOC - Can't find BSS after receiving Assoc response\n");
- } else {
- /* Init variable */
- pAd->MacTab.Content[BSSID_WCID].RSNIE_Len = 0;
- NdisZeroMemory(pAd->MacTab.Content[BSSID_WCID].RSN_IE,
- MAX_LEN_OF_RSNIE);
-
- /* Store appropriate RSN_IE for WPA SM negotiation later */
- if ((pAd->StaCfg.AuthMode >= Ndis802_11AuthModeWPA)
- && (pAd->ScanTab.BssEntry[Idx].VarIELen != 0)) {
- u8 *pVIE;
- u16 len;
- struct rt_eid * pEid;
-
- pVIE = pAd->ScanTab.BssEntry[Idx].VarIEs;
- len = pAd->ScanTab.BssEntry[Idx].VarIELen;
- /*KH need to check again */
- /* Don't allow to go to sleep mode if authmode is WPA-related. */
- /*This can make Authentication process more smoothly. */
- RTMP_CLEAR_PSFLAG(pAd, fRTMP_PS_CAN_GO_SLEEP);
-
- while (len > 0) {
- pEid = (struct rt_eid *) pVIE;
- /* For WPA/WPAPSK */
- if ((pEid->Eid == IE_WPA)
- &&
- (NdisEqualMemory(pEid->Octet, WPA_OUI, 4))
- && (pAd->StaCfg.AuthMode ==
- Ndis802_11AuthModeWPA
- || pAd->StaCfg.AuthMode ==
- Ndis802_11AuthModeWPAPSK)) {
- NdisMoveMemory(pAd->MacTab.
- Content[BSSID_WCID].
- RSN_IE, pVIE,
- (pEid->Len + 2));
- pAd->MacTab.Content[BSSID_WCID].
- RSNIE_Len = (pEid->Len + 2);
- DBGPRINT(RT_DEBUG_TRACE,
- ("AssocPostProc===> Store RSN_IE for WPA SM negotiation \n"));
- }
- /* For WPA2/WPA2PSK */
- else if ((pEid->Eid == IE_RSN)
- &&
- (NdisEqualMemory
- (pEid->Octet + 2, RSN_OUI, 3))
- && (pAd->StaCfg.AuthMode ==
- Ndis802_11AuthModeWPA2
- || pAd->StaCfg.AuthMode ==
- Ndis802_11AuthModeWPA2PSK)) {
- NdisMoveMemory(pAd->MacTab.
- Content[BSSID_WCID].
- RSN_IE, pVIE,
- (pEid->Len + 2));
- pAd->MacTab.Content[BSSID_WCID].
- RSNIE_Len = (pEid->Len + 2);
- DBGPRINT(RT_DEBUG_TRACE,
- ("AssocPostProc===> Store RSN_IE for WPA2 SM negotiation \n"));
- }
-
- pVIE += (pEid->Len + 2);
- len -= (pEid->Len + 2);
- }
-
- }
-
- if (pAd->MacTab.Content[BSSID_WCID].RSNIE_Len == 0) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("AssocPostProc===> no RSN_IE \n"));
- } else {
- hex_dump("RSN_IE",
- pAd->MacTab.Content[BSSID_WCID].RSN_IE,
- pAd->MacTab.Content[BSSID_WCID].RSNIE_Len);
- }
- }
-}
-
-/*
- ==========================================================================
- Description:
- left part of IEEE 802.11/1999 p.374
- Parameters:
- Elem - MLME message containing the received frame
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
- */
-void PeerDisassocAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
- u8 Addr2[MAC_ADDR_LEN];
- u16 Reason;
-
- DBGPRINT(RT_DEBUG_TRACE, ("ASSOC - PeerDisassocAction()\n"));
- if (PeerDisassocSanity(pAd, Elem->Msg, Elem->MsgLen, Addr2, &Reason)) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("ASSOC - PeerDisassocAction() Reason = %d\n",
- Reason));
- if (INFRA_ON(pAd)
- && MAC_ADDR_EQUAL(pAd->CommonCfg.Bssid, Addr2)) {
-
- if (pAd->CommonCfg.bWirelessEvent) {
- RTMPSendWirelessEvent(pAd,
- IW_DISASSOC_EVENT_FLAG,
- pAd->MacTab.
- Content[BSSID_WCID].Addr,
- BSS0, 0);
- }
-
- LinkDown(pAd, TRUE);
- pAd->Mlme.AssocMachine.CurrState = ASSOC_IDLE;
-
- RtmpOSWrielessEventSend(pAd, SIOCGIWAP, -1, NULL, NULL,
- 0);
- }
- } else {
- DBGPRINT(RT_DEBUG_TRACE,
- ("ASSOC - PeerDisassocAction() sanity check fail\n"));
- }
-
-}
-
-/*
- ==========================================================================
- Description:
- what the state machine will do after assoc timeout
- Parameters:
- Elme -
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
- */
-void AssocTimeoutAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
- u16 Status;
- DBGPRINT(RT_DEBUG_TRACE, ("ASSOC - AssocTimeoutAction\n"));
- pAd->Mlme.AssocMachine.CurrState = ASSOC_IDLE;
- Status = MLME_REJ_TIMEOUT;
- MlmeEnqueue(pAd, MLME_CNTL_STATE_MACHINE, MT2_ASSOC_CONF, 2, &Status);
-}
-
-/*
- ==========================================================================
- Description:
- what the state machine will do after reassoc timeout
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
- */
-void ReassocTimeoutAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
- u16 Status;
- DBGPRINT(RT_DEBUG_TRACE, ("ASSOC - ReassocTimeoutAction\n"));
- pAd->Mlme.AssocMachine.CurrState = ASSOC_IDLE;
- Status = MLME_REJ_TIMEOUT;
- MlmeEnqueue(pAd, MLME_CNTL_STATE_MACHINE, MT2_REASSOC_CONF, 2, &Status);
-}
-
-/*
- ==========================================================================
- Description:
- what the state machine will do after disassoc timeout
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
- */
-void DisassocTimeoutAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
- u16 Status;
- DBGPRINT(RT_DEBUG_TRACE, ("ASSOC - DisassocTimeoutAction\n"));
- pAd->Mlme.AssocMachine.CurrState = ASSOC_IDLE;
- Status = MLME_SUCCESS;
- MlmeEnqueue(pAd, MLME_CNTL_STATE_MACHINE, MT2_DISASSOC_CONF, 2,
- &Status);
-}
-
-void InvalidStateWhenAssoc(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
- u16 Status;
- DBGPRINT(RT_DEBUG_TRACE,
- ("ASSOC - InvalidStateWhenAssoc(state=%ld), reset ASSOC state machine\n",
- pAd->Mlme.AssocMachine.CurrState));
- pAd->Mlme.AssocMachine.CurrState = ASSOC_IDLE;
- Status = MLME_STATE_MACHINE_REJECT;
- MlmeEnqueue(pAd, MLME_CNTL_STATE_MACHINE, MT2_ASSOC_CONF, 2, &Status);
-}
-
-void InvalidStateWhenReassoc(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
- u16 Status;
- DBGPRINT(RT_DEBUG_TRACE,
- ("ASSOC - InvalidStateWhenReassoc(state=%ld), reset ASSOC state machine\n",
- pAd->Mlme.AssocMachine.CurrState));
- pAd->Mlme.AssocMachine.CurrState = ASSOC_IDLE;
- Status = MLME_STATE_MACHINE_REJECT;
- MlmeEnqueue(pAd, MLME_CNTL_STATE_MACHINE, MT2_REASSOC_CONF, 2, &Status);
-}
-
-void InvalidStateWhenDisassociate(struct rt_rtmp_adapter *pAd,
- struct rt_mlme_queue_elem *Elem)
-{
- u16 Status;
- DBGPRINT(RT_DEBUG_TRACE,
- ("ASSOC - InvalidStateWhenDisassoc(state=%ld), reset ASSOC state machine\n",
- pAd->Mlme.AssocMachine.CurrState));
- pAd->Mlme.AssocMachine.CurrState = ASSOC_IDLE;
- Status = MLME_STATE_MACHINE_REJECT;
- MlmeEnqueue(pAd, MLME_CNTL_STATE_MACHINE, MT2_DISASSOC_CONF, 2,
- &Status);
-}
-
-/*
- ==========================================================================
- Description:
- right part of IEEE 802.11/1999 page 374
- Note:
- This event should never cause ASSOC state machine perform state
- transition, and has no relationship with CNTL machine. So we separate
- this routine as a service outside of ASSOC state transition table.
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
- */
-void Cls3errAction(struct rt_rtmp_adapter *pAd, u8 *pAddr)
-{
- struct rt_header_802_11 DisassocHdr;
- struct rt_header_802_11 * pDisassocHdr;
- u8 *pOutBuffer = NULL;
- unsigned long FrameLen = 0;
- int NStatus;
- u16 Reason = REASON_CLS3ERR;
-
- NStatus = MlmeAllocateMemory(pAd, &pOutBuffer); /*Get an unused nonpaged memory */
- if (NStatus != NDIS_STATUS_SUCCESS)
- return;
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("ASSOC - Class 3 Error, Send DISASSOC frame\n"));
- MgtMacHeaderInit(pAd, &DisassocHdr, SUBTYPE_DISASSOC, 0, pAddr, pAd->CommonCfg.Bssid); /* patch peap ttls switching issue */
- MakeOutgoingFrame(pOutBuffer, &FrameLen,
- sizeof(struct rt_header_802_11), &DisassocHdr,
- 2, &Reason, END_OF_ARGS);
- MiniportMMRequest(pAd, 0, pOutBuffer, FrameLen);
-
- /* To patch Instance and Buffalo(N) AP */
- /* Driver has to send deauth to Instance AP, but Buffalo(N) needs to send disassoc to reset Authenticator's state machine */
- /* Therefore, we send both of them. */
- pDisassocHdr = (struct rt_header_802_11 *) pOutBuffer;
- pDisassocHdr->FC.SubType = SUBTYPE_DEAUTH;
- MiniportMMRequest(pAd, 0, pOutBuffer, FrameLen);
-
- MlmeFreeMemory(pAd, pOutBuffer);
-
- pAd->StaCfg.DisassocReason = REASON_CLS3ERR;
- COPY_MAC_ADDR(pAd->StaCfg.DisassocSta, pAddr);
-}
-
-int wext_notify_event_assoc(struct rt_rtmp_adapter *pAd)
-{
- char custom[IW_CUSTOM_MAX] = { 0 };
-
- if (pAd->StaCfg.ReqVarIELen <= IW_CUSTOM_MAX) {
- NdisMoveMemory(custom, pAd->StaCfg.ReqVarIEs,
- pAd->StaCfg.ReqVarIELen);
- RtmpOSWrielessEventSend(pAd, IWEVASSOCREQIE, -1, NULL, custom,
- pAd->StaCfg.ReqVarIELen);
- } else
- DBGPRINT(RT_DEBUG_TRACE,
- ("pAd->StaCfg.ReqVarIELen > MAX_CUSTOM_LEN\n"));
-
- return 0;
-
-}
-
-BOOLEAN StaAddMacTableEntry(struct rt_rtmp_adapter *pAd,
- struct rt_mac_table_entry *pEntry,
- u8 MaxSupportedRateIn500Kbps,
- struct rt_ht_capability_ie * pHtCapability,
- u8 HtCapabilityLen,
- struct rt_add_ht_info_ie * pAddHtInfo,
- u8 AddHtInfoLen, u16 CapabilityInfo)
-{
- u8 MaxSupportedRate = RATE_11;
-
- if (ADHOC_ON(pAd))
- CLIENT_STATUS_CLEAR_FLAG(pEntry, fCLIENT_STATUS_WMM_CAPABLE);
-
- switch (MaxSupportedRateIn500Kbps) {
- case 108:
- MaxSupportedRate = RATE_54;
- break;
- case 96:
- MaxSupportedRate = RATE_48;
- break;
- case 72:
- MaxSupportedRate = RATE_36;
- break;
- case 48:
- MaxSupportedRate = RATE_24;
- break;
- case 36:
- MaxSupportedRate = RATE_18;
- break;
- case 24:
- MaxSupportedRate = RATE_12;
- break;
- case 18:
- MaxSupportedRate = RATE_9;
- break;
- case 12:
- MaxSupportedRate = RATE_6;
- break;
- case 22:
- MaxSupportedRate = RATE_11;
- break;
- case 11:
- MaxSupportedRate = RATE_5_5;
- break;
- case 4:
- MaxSupportedRate = RATE_2;
- break;
- case 2:
- MaxSupportedRate = RATE_1;
- break;
- default:
- MaxSupportedRate = RATE_11;
- break;
- }
-
- if ((pAd->CommonCfg.PhyMode == PHY_11G)
- && (MaxSupportedRate < RATE_FIRST_OFDM_RATE))
- return FALSE;
-
- /* 11n only */
- if (((pAd->CommonCfg.PhyMode == PHY_11N_2_4G)
- || (pAd->CommonCfg.PhyMode == PHY_11N_5G))
- && (HtCapabilityLen == 0))
- return FALSE;
-
- if (!pEntry)
- return FALSE;
-
- NdisAcquireSpinLock(&pAd->MacTabLock);
- if (pEntry) {
- pEntry->PortSecured = WPA_802_1X_PORT_SECURED;
- if ((MaxSupportedRate < RATE_FIRST_OFDM_RATE) ||
- (pAd->CommonCfg.PhyMode == PHY_11B)) {
- pEntry->RateLen = 4;
- if (MaxSupportedRate >= RATE_FIRST_OFDM_RATE)
- MaxSupportedRate = RATE_11;
- } else
- pEntry->RateLen = 12;
-
- pEntry->MaxHTPhyMode.word = 0;
- pEntry->MinHTPhyMode.word = 0;
- pEntry->HTPhyMode.word = 0;
- pEntry->MaxSupportedRate = MaxSupportedRate;
- if (pEntry->MaxSupportedRate < RATE_FIRST_OFDM_RATE) {
- pEntry->MaxHTPhyMode.field.MODE = MODE_CCK;
- pEntry->MaxHTPhyMode.field.MCS =
- pEntry->MaxSupportedRate;
- pEntry->MinHTPhyMode.field.MODE = MODE_CCK;
- pEntry->MinHTPhyMode.field.MCS =
- pEntry->MaxSupportedRate;
- pEntry->HTPhyMode.field.MODE = MODE_CCK;
- pEntry->HTPhyMode.field.MCS = pEntry->MaxSupportedRate;
- } else {
- pEntry->MaxHTPhyMode.field.MODE = MODE_OFDM;
- pEntry->MaxHTPhyMode.field.MCS =
- OfdmRateToRxwiMCS[pEntry->MaxSupportedRate];
- pEntry->MinHTPhyMode.field.MODE = MODE_OFDM;
- pEntry->MinHTPhyMode.field.MCS =
- OfdmRateToRxwiMCS[pEntry->MaxSupportedRate];
- pEntry->HTPhyMode.field.MODE = MODE_OFDM;
- pEntry->HTPhyMode.field.MCS =
- OfdmRateToRxwiMCS[pEntry->MaxSupportedRate];
- }
- pEntry->CapabilityInfo = CapabilityInfo;
- CLIENT_STATUS_CLEAR_FLAG(pEntry,
- fCLIENT_STATUS_AGGREGATION_CAPABLE);
- CLIENT_STATUS_CLEAR_FLAG(pEntry,
- fCLIENT_STATUS_PIGGYBACK_CAPABLE);
- }
-
- NdisZeroMemory(&pEntry->HTCapability, sizeof(pEntry->HTCapability));
- /* If this Entry supports 802.11n, upgrade to HT rate. */
- if ((HtCapabilityLen != 0)
- && (pAd->CommonCfg.PhyMode >= PHY_11ABGN_MIXED)) {
- u8 j, bitmask; /*k,bitmask; */
- char i;
-
- if (ADHOC_ON(pAd))
- CLIENT_STATUS_SET_FLAG(pEntry,
- fCLIENT_STATUS_WMM_CAPABLE);
- if ((pHtCapability->HtCapInfo.GF)
- && (pAd->CommonCfg.DesiredHtPhy.GF)) {
- pEntry->MaxHTPhyMode.field.MODE = MODE_HTGREENFIELD;
- } else {
- pEntry->MaxHTPhyMode.field.MODE = MODE_HTMIX;
- pAd->MacTab.fAnyStationNonGF = TRUE;
- pAd->CommonCfg.AddHTInfo.AddHtInfo2.NonGfPresent = 1;
- }
-
- if ((pHtCapability->HtCapInfo.ChannelWidth) &&
- (pAd->CommonCfg.DesiredHtPhy.ChannelWidth) &&
- ((pAd->StaCfg.BssType == BSS_INFRA)
- || ((pAd->StaCfg.BssType == BSS_ADHOC)
- && (pAddHtInfo->AddHtInfo.ExtChanOffset ==
- pAd->CommonCfg.AddHTInfo.AddHtInfo.
- ExtChanOffset)))) {
- pEntry->MaxHTPhyMode.field.BW = BW_40;
- pEntry->MaxHTPhyMode.field.ShortGI =
- ((pAd->CommonCfg.DesiredHtPhy.
- ShortGIfor40) & (pHtCapability->HtCapInfo.
- ShortGIfor40));
- } else {
- pEntry->MaxHTPhyMode.field.BW = BW_20;
- pEntry->MaxHTPhyMode.field.ShortGI =
- ((pAd->CommonCfg.DesiredHtPhy.
- ShortGIfor20) & (pHtCapability->HtCapInfo.
- ShortGIfor20));
- pAd->MacTab.fAnyStation20Only = TRUE;
- }
-
- /* 3*3 */
- if (pAd->MACVersion >= RALINK_2883_VERSION
- && pAd->MACVersion < RALINK_3070_VERSION)
- pEntry->MaxHTPhyMode.field.TxBF =
- pAd->CommonCfg.RegTransmitSetting.field.TxBF;
-
- /* find max fixed rate */
- for (i = 23; i >= 0; i--) /* 3*3 */
- {
- j = i / 8;
- bitmask = (1 << (i - (j * 8)));
- if ((pAd->StaCfg.DesiredHtPhyInfo.MCSSet[j] & bitmask)
- && (pHtCapability->MCSSet[j] & bitmask)) {
- pEntry->MaxHTPhyMode.field.MCS = i;
- break;
- }
- if (i == 0)
- break;
- }
-
- if (pAd->StaCfg.DesiredTransmitSetting.field.MCS != MCS_AUTO) {
- if (pAd->StaCfg.DesiredTransmitSetting.field.MCS == 32) {
- /* Fix MCS as HT Duplicated Mode */
- pEntry->MaxHTPhyMode.field.BW = 1;
- pEntry->MaxHTPhyMode.field.MODE = MODE_HTMIX;
- pEntry->MaxHTPhyMode.field.STBC = 0;
- pEntry->MaxHTPhyMode.field.ShortGI = 0;
- pEntry->MaxHTPhyMode.field.MCS = 32;
- } else if (pEntry->MaxHTPhyMode.field.MCS >
- pAd->StaCfg.HTPhyMode.field.MCS) {
- /* STA supports fixed MCS */
- pEntry->MaxHTPhyMode.field.MCS =
- pAd->StaCfg.HTPhyMode.field.MCS;
- }
- }
-
- pEntry->MaxHTPhyMode.field.STBC =
- (pHtCapability->HtCapInfo.
- RxSTBC & (pAd->CommonCfg.DesiredHtPhy.TxSTBC));
- pEntry->MpduDensity = pHtCapability->HtCapParm.MpduDensity;
- pEntry->MaxRAmpduFactor =
- pHtCapability->HtCapParm.MaxRAmpduFactor;
- pEntry->MmpsMode = (u8)pHtCapability->HtCapInfo.MimoPs;
- pEntry->AMsduSize = (u8)pHtCapability->HtCapInfo.AMsduSize;
- pEntry->HTPhyMode.word = pEntry->MaxHTPhyMode.word;
-
- if (pAd->CommonCfg.DesiredHtPhy.AmsduEnable
- && (pAd->CommonCfg.REGBACapability.field.AutoBA == FALSE))
- CLIENT_STATUS_SET_FLAG(pEntry,
- fCLIENT_STATUS_AMSDU_INUSED);
- if (pHtCapability->HtCapInfo.ShortGIfor20)
- CLIENT_STATUS_SET_FLAG(pEntry,
- fCLIENT_STATUS_SGI20_CAPABLE);
- if (pHtCapability->HtCapInfo.ShortGIfor40)
- CLIENT_STATUS_SET_FLAG(pEntry,
- fCLIENT_STATUS_SGI40_CAPABLE);
- if (pHtCapability->HtCapInfo.TxSTBC)
- CLIENT_STATUS_SET_FLAG(pEntry,
- fCLIENT_STATUS_TxSTBC_CAPABLE);
- if (pHtCapability->HtCapInfo.RxSTBC)
- CLIENT_STATUS_SET_FLAG(pEntry,
- fCLIENT_STATUS_RxSTBC_CAPABLE);
- if (pHtCapability->ExtHtCapInfo.PlusHTC)
- CLIENT_STATUS_SET_FLAG(pEntry,
- fCLIENT_STATUS_HTC_CAPABLE);
- if (pAd->CommonCfg.bRdg
- && pHtCapability->ExtHtCapInfo.RDGSupport)
- CLIENT_STATUS_SET_FLAG(pEntry,
- fCLIENT_STATUS_RDG_CAPABLE);
- if (pHtCapability->ExtHtCapInfo.MCSFeedback == 0x03)
- CLIENT_STATUS_SET_FLAG(pEntry,
- fCLIENT_STATUS_MCSFEEDBACK_CAPABLE);
- NdisMoveMemory(&pEntry->HTCapability, pHtCapability,
- HtCapabilityLen);
- } else {
- pAd->MacTab.fAnyStationIsLegacy = TRUE;
- }
-
- pEntry->HTPhyMode.word = pEntry->MaxHTPhyMode.word;
- pEntry->CurrTxRate = pEntry->MaxSupportedRate;
-
- /* Set asic auto fall back */
- if (pAd->StaCfg.bAutoTxRateSwitch == TRUE) {
- u8 *pTable;
- u8 TableSize = 0;
-
- MlmeSelectTxRateTable(pAd, pEntry, &pTable, &TableSize,
- &pEntry->CurrTxRateIndex);
- pEntry->bAutoTxRateSwitch = TRUE;
- } else {
- pEntry->HTPhyMode.field.MODE = pAd->StaCfg.HTPhyMode.field.MODE;
- pEntry->HTPhyMode.field.MCS = pAd->StaCfg.HTPhyMode.field.MCS;
- pEntry->bAutoTxRateSwitch = FALSE;
-
- /* If the legacy mode is set, overwrite the transmit setting of this entry. */
- RTMPUpdateLegacyTxSetting((u8)pAd->StaCfg.
- DesiredTransmitSetting.field.
- FixedTxMode, pEntry);
- }
-
- pEntry->PortSecured = WPA_802_1X_PORT_SECURED;
- pEntry->Sst = SST_ASSOC;
- pEntry->AuthState = AS_AUTH_OPEN;
- pEntry->AuthMode = pAd->StaCfg.AuthMode;
- pEntry->WepStatus = pAd->StaCfg.WepStatus;
-
- NdisReleaseSpinLock(&pAd->MacTabLock);
-
- {
- union iwreq_data wrqu;
- wext_notify_event_assoc(pAd);
-
- memcpy(wrqu.ap_addr.sa_data, pAd->MlmeAux.Bssid, MAC_ADDR_LEN);
- wireless_send_event(pAd->net_dev, SIOCGIWAP, &wrqu, NULL);
-
- }
- return TRUE;
-}
diff --git a/drivers/staging/rt2860/sta/auth.c b/drivers/staging/rt2860/sta/auth.c
deleted file mode 100644
index 23ea00b..0000000
--- a/drivers/staging/rt2860/sta/auth.c
+++ /dev/null
@@ -1,517 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- auth.c
-
- Abstract:
-
- Revision History:
- Who When What
- -------- ---------- ----------------------------------------------
- John 2004-9-3 porting from RT2500
- Justin P. Mattock 11/07/2010 Fix typos
-*/
-#include "../rt_config.h"
-
-/*
- ==========================================================================
- Description:
- authenticate state machine init, including state transition and timer init
- Parameters:
- Sm - pointer to the auth state machine
- Note:
- The state machine looks like this
-
- AUTH_REQ_IDLE AUTH_WAIT_SEQ2 AUTH_WAIT_SEQ4
- MT2_MLME_AUTH_REQ mlme_auth_req_action invalid_state_when_auth invalid_state_when_auth
- MT2_PEER_AUTH_EVEN drop peer_auth_even_at_seq2_action peer_auth_even_at_seq4_action
- MT2_AUTH_TIMEOUT Drop auth_timeout_action auth_timeout_action
-
- IRQL = PASSIVE_LEVEL
-
- ==========================================================================
- */
-
-void AuthStateMachineInit(struct rt_rtmp_adapter *pAd,
- struct rt_state_machine *Sm, OUT STATE_MACHINE_FUNC Trans[])
-{
- StateMachineInit(Sm, Trans, MAX_AUTH_STATE, MAX_AUTH_MSG,
- (STATE_MACHINE_FUNC) Drop, AUTH_REQ_IDLE,
- AUTH_MACHINE_BASE);
-
- /* the first column */
- StateMachineSetAction(Sm, AUTH_REQ_IDLE, MT2_MLME_AUTH_REQ,
- (STATE_MACHINE_FUNC) MlmeAuthReqAction);
-
- /* the second column */
- StateMachineSetAction(Sm, AUTH_WAIT_SEQ2, MT2_MLME_AUTH_REQ,
- (STATE_MACHINE_FUNC) InvalidStateWhenAuth);
- StateMachineSetAction(Sm, AUTH_WAIT_SEQ2, MT2_PEER_AUTH_EVEN,
- (STATE_MACHINE_FUNC) PeerAuthRspAtSeq2Action);
- StateMachineSetAction(Sm, AUTH_WAIT_SEQ2, MT2_AUTH_TIMEOUT,
- (STATE_MACHINE_FUNC) AuthTimeoutAction);
-
- /* the third column */
- StateMachineSetAction(Sm, AUTH_WAIT_SEQ4, MT2_MLME_AUTH_REQ,
- (STATE_MACHINE_FUNC) InvalidStateWhenAuth);
- StateMachineSetAction(Sm, AUTH_WAIT_SEQ4, MT2_PEER_AUTH_EVEN,
- (STATE_MACHINE_FUNC) PeerAuthRspAtSeq4Action);
- StateMachineSetAction(Sm, AUTH_WAIT_SEQ4, MT2_AUTH_TIMEOUT,
- (STATE_MACHINE_FUNC) AuthTimeoutAction);
-
- RTMPInitTimer(pAd, &pAd->MlmeAux.AuthTimer,
- GET_TIMER_FUNCTION(AuthTimeout), pAd, FALSE);
-}
-
-/*
- ==========================================================================
- Description:
- function to be executed at timer thread when auth timer expires
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
- */
-void AuthTimeout(void *SystemSpecific1,
- void *FunctionContext,
- void *SystemSpecific2, void *SystemSpecific3)
-{
- struct rt_rtmp_adapter *pAd = (struct rt_rtmp_adapter *)FunctionContext;
-
- DBGPRINT(RT_DEBUG_TRACE, ("AUTH - AuthTimeout\n"));
-
- /* Do nothing if the driver is starting halt state. */
- /* This might happen when timer already been fired before cancel timer with mlmehalt */
- if (RTMP_TEST_FLAG
- (pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS | fRTMP_ADAPTER_NIC_NOT_EXIST))
- return;
-
- /* send a de-auth to reset AP's state machine (Patch AP-Dir635) */
- if (pAd->Mlme.AuthMachine.CurrState == AUTH_WAIT_SEQ2)
- Cls2errAction(pAd, pAd->MlmeAux.Bssid);
-
- MlmeEnqueue(pAd, AUTH_STATE_MACHINE, MT2_AUTH_TIMEOUT, 0, NULL);
- RTMP_MLME_HANDLER(pAd);
-}
-
-/*
- ==========================================================================
- Description:
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
- */
-void MlmeAuthReqAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
- if (AUTH_ReqSend
- (pAd, Elem, &pAd->MlmeAux.AuthTimer, "AUTH", 1, NULL, 0))
- pAd->Mlme.AuthMachine.CurrState = AUTH_WAIT_SEQ2;
- else {
- u16 Status;
-
- pAd->Mlme.AuthMachine.CurrState = AUTH_REQ_IDLE;
- Status = MLME_INVALID_FORMAT;
- MlmeEnqueue(pAd, MLME_CNTL_STATE_MACHINE, MT2_AUTH_CONF, 2,
- &Status);
- }
-}
-
-/*
- ==========================================================================
- Description:
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
- */
-void PeerAuthRspAtSeq2Action(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
- u8 Addr2[MAC_ADDR_LEN];
- u16 Seq, Status, RemoteStatus, Alg;
- u8 ChlgText[CIPHER_TEXT_LEN];
- u8 CyperChlgText[CIPHER_TEXT_LEN + 8 + 8];
- u8 Element[2];
- struct rt_header_802_11 AuthHdr;
- BOOLEAN TimerCancelled;
- u8 *pOutBuffer = NULL;
- int NStatus;
- unsigned long FrameLen = 0;
- u16 Status2;
-
- if (PeerAuthSanity
- (pAd, Elem->Msg, Elem->MsgLen, Addr2, &Alg, &Seq, &Status,
- (char *)ChlgText)) {
- if (MAC_ADDR_EQUAL(pAd->MlmeAux.Bssid, Addr2) && Seq == 2) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("AUTH - Receive AUTH_RSP seq#2 to me (Alg=%d, Status=%d)\n",
- Alg, Status));
- RTMPCancelTimer(&pAd->MlmeAux.AuthTimer,
- &TimerCancelled);
-
- if (Status == MLME_SUCCESS) {
- /* Authentication Mode "LEAP" has allow for CCX 1.X */
- if (pAd->MlmeAux.Alg == Ndis802_11AuthModeOpen) {
- pAd->Mlme.AuthMachine.CurrState =
- AUTH_REQ_IDLE;
- MlmeEnqueue(pAd,
- MLME_CNTL_STATE_MACHINE,
- MT2_AUTH_CONF, 2, &Status);
- } else {
- /* 2. shared key, need to be challenged */
- Seq++;
- RemoteStatus = MLME_SUCCESS;
-
- /* Get an unused nonpaged memory */
- NStatus =
- MlmeAllocateMemory(pAd,
- &pOutBuffer);
- if (NStatus != NDIS_STATUS_SUCCESS) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("AUTH - PeerAuthRspAtSeq2Action() allocate memory fail\n"));
- pAd->Mlme.AuthMachine.
- CurrState = AUTH_REQ_IDLE;
- Status2 = MLME_FAIL_NO_RESOURCE;
- MlmeEnqueue(pAd,
- MLME_CNTL_STATE_MACHINE,
- MT2_AUTH_CONF, 2,
- &Status2);
- return;
- }
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("AUTH - Send AUTH request seq#3...\n"));
- MgtMacHeaderInit(pAd, &AuthHdr,
- SUBTYPE_AUTH, 0, Addr2,
- pAd->MlmeAux.Bssid);
- AuthHdr.FC.Wep = 1;
- /* Encrypt challenge text & auth information */
- RTMPInitWepEngine(pAd,
- pAd->
- SharedKey[BSS0][pAd->
- StaCfg.
- DefaultKeyId].
- Key,
- pAd->StaCfg.
- DefaultKeyId,
- pAd->
- SharedKey[BSS0][pAd->
- StaCfg.
- DefaultKeyId].
- KeyLen,
- CyperChlgText);
-
- Alg = cpu2le16(*(u16 *) & Alg);
- Seq = cpu2le16(*(u16 *) & Seq);
- RemoteStatus =
- cpu2le16(*(u16 *) &
- RemoteStatus);
-
- RTMPEncryptData(pAd, (u8 *)& Alg,
- CyperChlgText + 4, 2);
- RTMPEncryptData(pAd, (u8 *)& Seq,
- CyperChlgText + 6, 2);
- RTMPEncryptData(pAd,
- (u8 *)& RemoteStatus,
- CyperChlgText + 8, 2);
- Element[0] = 16;
- Element[1] = 128;
- RTMPEncryptData(pAd, Element,
- CyperChlgText + 10, 2);
- RTMPEncryptData(pAd, ChlgText,
- CyperChlgText + 12,
- 128);
- RTMPSetICV(pAd, CyperChlgText + 140);
- MakeOutgoingFrame(pOutBuffer, &FrameLen,
- sizeof(struct rt_header_802_11),
- &AuthHdr,
- CIPHER_TEXT_LEN + 16,
- CyperChlgText,
- END_OF_ARGS);
- MiniportMMRequest(pAd, 0, pOutBuffer,
- FrameLen);
- MlmeFreeMemory(pAd, pOutBuffer);
-
- RTMPSetTimer(&pAd->MlmeAux.AuthTimer,
- AUTH_TIMEOUT);
- pAd->Mlme.AuthMachine.CurrState =
- AUTH_WAIT_SEQ4;
- }
- } else {
- pAd->StaCfg.AuthFailReason = Status;
- COPY_MAC_ADDR(pAd->StaCfg.AuthFailSta, Addr2);
- pAd->Mlme.AuthMachine.CurrState = AUTH_REQ_IDLE;
- MlmeEnqueue(pAd, MLME_CNTL_STATE_MACHINE,
- MT2_AUTH_CONF, 2, &Status);
- }
- }
- } else {
- DBGPRINT(RT_DEBUG_TRACE,
- ("AUTH - PeerAuthSanity() sanity check fail\n"));
- }
-}
-
-/*
- ==========================================================================
- Description:
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
- */
-void PeerAuthRspAtSeq4Action(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
- u8 Addr2[MAC_ADDR_LEN];
- u16 Alg, Seq, Status;
- char ChlgText[CIPHER_TEXT_LEN];
- BOOLEAN TimerCancelled;
-
- if (PeerAuthSanity
- (pAd, Elem->Msg, Elem->MsgLen, Addr2, &Alg, &Seq, &Status,
- ChlgText)) {
- if (MAC_ADDR_EQUAL(pAd->MlmeAux.Bssid, Addr2) && Seq == 4) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("AUTH - Receive AUTH_RSP seq#4 to me\n"));
- RTMPCancelTimer(&pAd->MlmeAux.AuthTimer,
- &TimerCancelled);
-
- if (Status != MLME_SUCCESS) {
- pAd->StaCfg.AuthFailReason = Status;
- COPY_MAC_ADDR(pAd->StaCfg.AuthFailSta, Addr2);
- }
-
- pAd->Mlme.AuthMachine.CurrState = AUTH_REQ_IDLE;
- MlmeEnqueue(pAd, MLME_CNTL_STATE_MACHINE, MT2_AUTH_CONF,
- 2, &Status);
- }
- } else {
- DBGPRINT(RT_DEBUG_TRACE,
- ("AUTH - PeerAuthRspAtSeq4Action() sanity check fail\n"));
- }
-}
-
-/*
- ==========================================================================
- Description:
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
- */
-void MlmeDeauthReqAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
- struct rt_mlme_deauth_req *pInfo;
- struct rt_header_802_11 DeauthHdr;
- u8 *pOutBuffer = NULL;
- int NStatus;
- unsigned long FrameLen = 0;
- u16 Status;
-
- pInfo = (struct rt_mlme_deauth_req *)Elem->Msg;
-
- NStatus = MlmeAllocateMemory(pAd, &pOutBuffer); /*Get an unused nonpaged memory */
- if (NStatus != NDIS_STATUS_SUCCESS) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("AUTH - MlmeDeauthReqAction() allocate memory fail\n"));
- pAd->Mlme.AuthMachine.CurrState = AUTH_REQ_IDLE;
- Status = MLME_FAIL_NO_RESOURCE;
- MlmeEnqueue(pAd, MLME_CNTL_STATE_MACHINE, MT2_DEAUTH_CONF, 2,
- &Status);
- return;
- }
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("AUTH - Send DE-AUTH request (Reason=%d)...\n",
- pInfo->Reason));
- MgtMacHeaderInit(pAd, &DeauthHdr, SUBTYPE_DEAUTH, 0, pInfo->Addr,
- pAd->MlmeAux.Bssid);
- MakeOutgoingFrame(pOutBuffer, &FrameLen, sizeof(struct rt_header_802_11),
- &DeauthHdr, 2, &pInfo->Reason, END_OF_ARGS);
- MiniportMMRequest(pAd, 0, pOutBuffer, FrameLen);
- MlmeFreeMemory(pAd, pOutBuffer);
-
- pAd->StaCfg.DeauthReason = pInfo->Reason;
- COPY_MAC_ADDR(pAd->StaCfg.DeauthSta, pInfo->Addr);
- pAd->Mlme.AuthMachine.CurrState = AUTH_REQ_IDLE;
- Status = MLME_SUCCESS;
- MlmeEnqueue(pAd, MLME_CNTL_STATE_MACHINE, MT2_DEAUTH_CONF, 2, &Status);
-
- /* send wireless event - for deauthentication */
- if (pAd->CommonCfg.bWirelessEvent)
- RTMPSendWirelessEvent(pAd, IW_DEAUTH_EVENT_FLAG,
- pAd->MacTab.Content[BSSID_WCID].Addr,
- BSS0, 0);
-}
-
-/*
- ==========================================================================
- Description:
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
- */
-void AuthTimeoutAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
- u16 Status;
- DBGPRINT(RT_DEBUG_TRACE, ("AUTH - AuthTimeoutAction\n"));
- pAd->Mlme.AuthMachine.CurrState = AUTH_REQ_IDLE;
- Status = MLME_REJ_TIMEOUT;
- MlmeEnqueue(pAd, MLME_CNTL_STATE_MACHINE, MT2_AUTH_CONF, 2, &Status);
-}
-
-/*
- ==========================================================================
- Description:
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
- */
-void InvalidStateWhenAuth(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
- u16 Status;
- DBGPRINT(RT_DEBUG_TRACE,
- ("AUTH - InvalidStateWhenAuth (state=%ld), reset AUTH state machine\n",
- pAd->Mlme.AuthMachine.CurrState));
- pAd->Mlme.AuthMachine.CurrState = AUTH_REQ_IDLE;
- Status = MLME_STATE_MACHINE_REJECT;
- MlmeEnqueue(pAd, MLME_CNTL_STATE_MACHINE, MT2_AUTH_CONF, 2, &Status);
-}
-
-/*
- ==========================================================================
- Description:
- Some STA/AP
- Note:
- This action should never trigger AUTH state transition, therefore we
- separate it from AUTH state machine, and make it as a standalone service
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
- */
-void Cls2errAction(struct rt_rtmp_adapter *pAd, u8 *pAddr)
-{
- struct rt_header_802_11 DeauthHdr;
- u8 *pOutBuffer = NULL;
- int NStatus;
- unsigned long FrameLen = 0;
- u16 Reason = REASON_CLS2ERR;
-
- NStatus = MlmeAllocateMemory(pAd, &pOutBuffer); /*Get an unused nonpaged memory */
- if (NStatus != NDIS_STATUS_SUCCESS)
- return;
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("AUTH - Class 2 error, Send DEAUTH frame...\n"));
- MgtMacHeaderInit(pAd, &DeauthHdr, SUBTYPE_DEAUTH, 0, pAddr,
- pAd->MlmeAux.Bssid);
- MakeOutgoingFrame(pOutBuffer, &FrameLen, sizeof(struct rt_header_802_11),
- &DeauthHdr, 2, &Reason, END_OF_ARGS);
- MiniportMMRequest(pAd, 0, pOutBuffer, FrameLen);
- MlmeFreeMemory(pAd, pOutBuffer);
-
- pAd->StaCfg.DeauthReason = Reason;
- COPY_MAC_ADDR(pAd->StaCfg.DeauthSta, pAddr);
-}
-
-BOOLEAN AUTH_ReqSend(struct rt_rtmp_adapter *pAd,
- struct rt_mlme_queue_elem *pElem,
- struct rt_ralink_timer *pAuthTimer,
- char *pSMName,
- u16 SeqNo,
- u8 *pNewElement, unsigned long ElementLen)
-{
- u16 Alg, Seq, Status;
- u8 Addr[6];
- unsigned long Timeout;
- struct rt_header_802_11 AuthHdr;
- BOOLEAN TimerCancelled;
- int NStatus;
- u8 *pOutBuffer = NULL;
- unsigned long FrameLen = 0, tmp = 0;
-
- /* Block all authentication request during WPA block period */
- if (pAd->StaCfg.bBlockAssoc == TRUE) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("%s - Block Auth request during WPA block period!\n",
- pSMName));
- pAd->Mlme.AuthMachine.CurrState = AUTH_REQ_IDLE;
- Status = MLME_STATE_MACHINE_REJECT;
- MlmeEnqueue(pAd, MLME_CNTL_STATE_MACHINE, MT2_AUTH_CONF, 2,
- &Status);
- } else
- if (MlmeAuthReqSanity
- (pAd, pElem->Msg, pElem->MsgLen, Addr, &Timeout, &Alg)) {
- /* reset timer */
- RTMPCancelTimer(pAuthTimer, &TimerCancelled);
-
- COPY_MAC_ADDR(pAd->MlmeAux.Bssid, Addr);
- pAd->MlmeAux.Alg = Alg;
- Seq = SeqNo;
- Status = MLME_SUCCESS;
-
- NStatus = MlmeAllocateMemory(pAd, &pOutBuffer); /*Get an unused nonpaged memory */
- if (NStatus != NDIS_STATUS_SUCCESS) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("%s - MlmeAuthReqAction(Alg:%d) allocate memory failed\n",
- pSMName, Alg));
- pAd->Mlme.AuthMachine.CurrState = AUTH_REQ_IDLE;
- Status = MLME_FAIL_NO_RESOURCE;
- MlmeEnqueue(pAd, MLME_CNTL_STATE_MACHINE, MT2_AUTH_CONF,
- 2, &Status);
- return FALSE;
- }
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("%s - Send AUTH request seq#1 (Alg=%d)...\n", pSMName,
- Alg));
- MgtMacHeaderInit(pAd, &AuthHdr, SUBTYPE_AUTH, 0, Addr,
- pAd->MlmeAux.Bssid);
- MakeOutgoingFrame(pOutBuffer, &FrameLen, sizeof(struct rt_header_802_11),
- &AuthHdr, 2, &Alg, 2, &Seq, 2, &Status,
- END_OF_ARGS);
-
- if (pNewElement && ElementLen) {
- MakeOutgoingFrame(pOutBuffer + FrameLen, &tmp,
- ElementLen, pNewElement, END_OF_ARGS);
- FrameLen += tmp;
- }
-
- MiniportMMRequest(pAd, 0, pOutBuffer, FrameLen);
- MlmeFreeMemory(pAd, pOutBuffer);
-
- RTMPSetTimer(pAuthTimer, Timeout);
- return TRUE;
- } else {
- DBGPRINT_ERR("%s - MlmeAuthReqAction() sanity check failed\n", pSMName);
- return FALSE;
- }
-
- return TRUE;
-}
diff --git a/drivers/staging/rt2860/sta/auth_rsp.c b/drivers/staging/rt2860/sta/auth_rsp.c
deleted file mode 100644
index 5b018b7..0000000
--- a/drivers/staging/rt2860/sta/auth_rsp.c
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- auth_rsp.c
-
- Abstract:
-
- Revision History:
- Who When What
- -------- ---------- ----------------------------------------------
- John 2004-10-1 copy from RT2560
-*/
-#include "../rt_config.h"
-
-/*
- ==========================================================================
- Description:
- authentication state machine init procedure
- Parameters:
- Sm - the state machine
-
- IRQL = PASSIVE_LEVEL
-
- ==========================================================================
- */
-void AuthRspStateMachineInit(struct rt_rtmp_adapter *pAd,
- struct rt_state_machine *Sm,
- IN STATE_MACHINE_FUNC Trans[])
-{
- StateMachineInit(Sm, Trans, MAX_AUTH_RSP_STATE, MAX_AUTH_RSP_MSG,
- (STATE_MACHINE_FUNC) Drop, AUTH_RSP_IDLE,
- AUTH_RSP_MACHINE_BASE);
-
- /* column 1 */
- StateMachineSetAction(Sm, AUTH_RSP_IDLE, MT2_PEER_DEAUTH,
- (STATE_MACHINE_FUNC) PeerDeauthAction);
-
- /* column 2 */
- StateMachineSetAction(Sm, AUTH_RSP_WAIT_CHAL, MT2_PEER_DEAUTH,
- (STATE_MACHINE_FUNC) PeerDeauthAction);
-
-}
-
-/*
- ==========================================================================
- Description:
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
-*/
-void PeerAuthSimpleRspGenAndSend(struct rt_rtmp_adapter *pAd,
- struct rt_header_802_11 * pHdr80211,
- u16 Alg,
- u16 Seq,
- u16 Reason, u16 Status)
-{
- struct rt_header_802_11 AuthHdr;
- unsigned long FrameLen = 0;
- u8 *pOutBuffer = NULL;
- int NStatus;
-
- if (Reason != MLME_SUCCESS) {
- DBGPRINT(RT_DEBUG_TRACE, ("Peer AUTH fail...\n"));
- return;
- }
- /*Get an unused nonpaged memory */
- NStatus = MlmeAllocateMemory(pAd, &pOutBuffer);
- if (NStatus != NDIS_STATUS_SUCCESS)
- return;
-
- DBGPRINT(RT_DEBUG_TRACE, ("Send AUTH response (seq#2)...\n"));
- MgtMacHeaderInit(pAd, &AuthHdr, SUBTYPE_AUTH, 0, pHdr80211->Addr2,
- pAd->MlmeAux.Bssid);
- MakeOutgoingFrame(pOutBuffer, &FrameLen, sizeof(struct rt_header_802_11),
- &AuthHdr, 2, &Alg, 2, &Seq, 2, &Reason, END_OF_ARGS);
- MiniportMMRequest(pAd, 0, pOutBuffer, FrameLen);
- MlmeFreeMemory(pAd, pOutBuffer);
-}
-
-/*
- ==========================================================================
- Description:
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
-*/
-void PeerDeauthAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
- u8 Addr2[MAC_ADDR_LEN];
- u16 Reason;
-
- if (PeerDeauthSanity(pAd, Elem->Msg, Elem->MsgLen, Addr2, &Reason)) {
- if (INFRA_ON(pAd)
- && MAC_ADDR_EQUAL(Addr2, pAd->CommonCfg.Bssid)
- ) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("AUTH_RSP - receive DE-AUTH from our AP (Reason=%d)\n",
- Reason));
-
- RtmpOSWrielessEventSend(pAd, SIOCGIWAP, -1, NULL, NULL,
- 0);
-
- /* send wireless event - for deauthentication */
- if (pAd->CommonCfg.bWirelessEvent)
- RTMPSendWirelessEvent(pAd, IW_DEAUTH_EVENT_FLAG,
- pAd->MacTab.
- Content[BSSID_WCID].Addr,
- BSS0, 0);
-
- LinkDown(pAd, TRUE);
- }
- } else {
- DBGPRINT(RT_DEBUG_TRACE,
- ("AUTH_RSP - PeerDeauthAction() sanity check fail\n"));
- }
-}
diff --git a/drivers/staging/rt2860/sta/connect.c b/drivers/staging/rt2860/sta/connect.c
deleted file mode 100644
index 4996258..0000000
--- a/drivers/staging/rt2860/sta/connect.c
+++ /dev/null
@@ -1,2613 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- connect.c
-
- Abstract:
-
- Revision History:
- Who When What
- -------- ---------- ----------------------------------------------
- John 2004-08-08 Major modification from RT2560
- Justin P. Mattock 11/07/2010 Fix typos
-*/
-#include "../rt_config.h"
-
-u8 CipherSuiteWpaNoneTkip[] = {
- 0x00, 0x50, 0xf2, 0x01, /* oui */
- 0x01, 0x00, /* Version */
- 0x00, 0x50, 0xf2, 0x02, /* Multicast */
- 0x01, 0x00, /* Number of unicast */
- 0x00, 0x50, 0xf2, 0x02, /* unicast */
- 0x01, 0x00, /* number of authentication method */
- 0x00, 0x50, 0xf2, 0x00 /* authentication */
-};
-
-u8 CipherSuiteWpaNoneTkipLen =
- (sizeof(CipherSuiteWpaNoneTkip) / sizeof(u8));
-
-u8 CipherSuiteWpaNoneAes[] = {
- 0x00, 0x50, 0xf2, 0x01, /* oui */
- 0x01, 0x00, /* Version */
- 0x00, 0x50, 0xf2, 0x04, /* Multicast */
- 0x01, 0x00, /* Number of unicast */
- 0x00, 0x50, 0xf2, 0x04, /* unicast */
- 0x01, 0x00, /* number of authentication method */
- 0x00, 0x50, 0xf2, 0x00 /* authentication */
-};
-
-u8 CipherSuiteWpaNoneAesLen =
- (sizeof(CipherSuiteWpaNoneAes) / sizeof(u8));
-
-/* The following MACRO is called after 1. starting an new IBSS, 2. successfully JOIN an IBSS, */
-/* or 3. successfully ASSOCIATE to a BSS, 4. successfully RE_ASSOCIATE to a BSS */
-/* All settings successfuly negotiated firing MLME state machines become final settings */
-/* and are copied to pAd->StaActive */
-#define COPY_SETTINGS_FROM_MLME_AUX_TO_ACTIVE_CFG(_pAd) \
-{ \
- NdisZeroMemory((_pAd)->CommonCfg.Ssid, MAX_LEN_OF_SSID); \
- (_pAd)->CommonCfg.SsidLen = (_pAd)->MlmeAux.SsidLen; \
- NdisMoveMemory((_pAd)->CommonCfg.Ssid, (_pAd)->MlmeAux.Ssid, (_pAd)->MlmeAux.SsidLen); \
- COPY_MAC_ADDR((_pAd)->CommonCfg.Bssid, (_pAd)->MlmeAux.Bssid); \
- (_pAd)->CommonCfg.Channel = (_pAd)->MlmeAux.Channel; \
- (_pAd)->CommonCfg.CentralChannel = (_pAd)->MlmeAux.CentralChannel; \
- (_pAd)->StaActive.Aid = (_pAd)->MlmeAux.Aid; \
- (_pAd)->StaActive.AtimWin = (_pAd)->MlmeAux.AtimWin; \
- (_pAd)->StaActive.CapabilityInfo = (_pAd)->MlmeAux.CapabilityInfo; \
- (_pAd)->CommonCfg.BeaconPeriod = (_pAd)->MlmeAux.BeaconPeriod; \
- (_pAd)->StaActive.CfpMaxDuration = (_pAd)->MlmeAux.CfpMaxDuration; \
- (_pAd)->StaActive.CfpPeriod = (_pAd)->MlmeAux.CfpPeriod; \
- (_pAd)->StaActive.SupRateLen = (_pAd)->MlmeAux.SupRateLen; \
- NdisMoveMemory((_pAd)->StaActive.SupRate, (_pAd)->MlmeAux.SupRate, (_pAd)->MlmeAux.SupRateLen);\
- (_pAd)->StaActive.ExtRateLen = (_pAd)->MlmeAux.ExtRateLen; \
- NdisMoveMemory((_pAd)->StaActive.ExtRate, (_pAd)->MlmeAux.ExtRate, (_pAd)->MlmeAux.ExtRateLen);\
- NdisMoveMemory(&(_pAd)->CommonCfg.APEdcaParm, &(_pAd)->MlmeAux.APEdcaParm, sizeof(struct rt_edca_parm));\
- NdisMoveMemory(&(_pAd)->CommonCfg.APQosCapability, &(_pAd)->MlmeAux.APQosCapability, sizeof(struct rt_qos_capability_parm));\
- NdisMoveMemory(&(_pAd)->CommonCfg.APQbssLoad, &(_pAd)->MlmeAux.APQbssLoad, sizeof(struct rt_qbss_load_parm));\
- COPY_MAC_ADDR((_pAd)->MacTab.Content[BSSID_WCID].Addr, (_pAd)->MlmeAux.Bssid); \
- (_pAd)->MacTab.Content[BSSID_WCID].Aid = (_pAd)->MlmeAux.Aid; \
- (_pAd)->MacTab.Content[BSSID_WCID].PairwiseKey.CipherAlg = (_pAd)->StaCfg.PairCipher;\
- COPY_MAC_ADDR((_pAd)->MacTab.Content[BSSID_WCID].PairwiseKey.BssId, (_pAd)->MlmeAux.Bssid);\
- (_pAd)->MacTab.Content[BSSID_WCID].RateLen = (_pAd)->StaActive.SupRateLen + (_pAd)->StaActive.ExtRateLen;\
-}
-
-/*
- ==========================================================================
- Description:
-
- IRQL = PASSIVE_LEVEL
-
- ==========================================================================
-*/
-void MlmeCntlInit(struct rt_rtmp_adapter *pAd,
- struct rt_state_machine *S, OUT STATE_MACHINE_FUNC Trans[])
-{
- /* Control state machine differs from other state machines, the interface */
- /* follows the standard interface */
- pAd->Mlme.CntlMachine.CurrState = CNTL_IDLE;
-}
-
-/*
- ==========================================================================
- Description:
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
-*/
-void MlmeCntlMachinePerformAction(struct rt_rtmp_adapter *pAd,
- struct rt_state_machine *S,
- struct rt_mlme_queue_elem *Elem)
-{
- switch (pAd->Mlme.CntlMachine.CurrState) {
- case CNTL_IDLE:
- CntlIdleProc(pAd, Elem);
- break;
- case CNTL_WAIT_DISASSOC:
- CntlWaitDisassocProc(pAd, Elem);
- break;
- case CNTL_WAIT_JOIN:
- CntlWaitJoinProc(pAd, Elem);
- break;
-
- /* CNTL_WAIT_REASSOC is the only state in CNTL machine that does */
- /* not triggered directly or indirectly by "RTMPSetInformation(OID_xxx)". */
- /* Therefore not protected by NDIS's "only one outstanding OID request" */
- /* rule. Which means NDIS may SET OID in the middle of ROAMing attempts. */
- /* Current approach is to block new SET request at RTMPSetInformation() */
- /* when CntlMachine.CurrState is not CNTL_IDLE */
- case CNTL_WAIT_REASSOC:
- CntlWaitReassocProc(pAd, Elem);
- break;
-
- case CNTL_WAIT_START:
- CntlWaitStartProc(pAd, Elem);
- break;
- case CNTL_WAIT_AUTH:
- CntlWaitAuthProc(pAd, Elem);
- break;
- case CNTL_WAIT_AUTH2:
- CntlWaitAuthProc2(pAd, Elem);
- break;
- case CNTL_WAIT_ASSOC:
- CntlWaitAssocProc(pAd, Elem);
- break;
-
- case CNTL_WAIT_OID_LIST_SCAN:
- if (Elem->MsgType == MT2_SCAN_CONF) {
- /* Resume TxRing after SCANING complete. We hope the out-of-service time */
- /* won't be too long to let upper layer time-out the waiting frames */
- RTMPResumeMsduTransmission(pAd);
-
- pAd->Mlme.CntlMachine.CurrState = CNTL_IDLE;
-
- /* */
- /* Set LED status to previous status. */
- /* */
- if (pAd->bLedOnScanning) {
- pAd->bLedOnScanning = FALSE;
- RTMPSetLED(pAd, pAd->LedStatus);
- }
- }
- break;
-
- case CNTL_WAIT_OID_DISASSOC:
- if (Elem->MsgType == MT2_DISASSOC_CONF) {
- LinkDown(pAd, FALSE);
- pAd->Mlme.CntlMachine.CurrState = CNTL_IDLE;
- }
- break;
-#ifdef RTMP_MAC_USB
- /* */
- /* This state is for that we want to connect to an AP but */
- /* it didn't find on BSS List table. So we need to scan the air first, */
- /* after that we can try to connect to the desired AP if available. */
- /* */
- case CNTL_WAIT_SCAN_FOR_CONNECT:
- if (Elem->MsgType == MT2_SCAN_CONF) {
- /* Resume TxRing after SCANING complete. We hope the out-of-service time */
- /* won't be too long to let upper layer time-out the waiting frames */
- RTMPResumeMsduTransmission(pAd);
-#ifdef CCX_SUPPORT
- if (pAd->StaCfg.CCXReqType != MSRN_TYPE_UNUSED) {
- /* Cisco scan request is finished, prepare beacon report */
- MlmeEnqueue(pAd, AIRONET_STATE_MACHINE,
- MT2_AIRONET_SCAN_DONE, 0, NULL);
- }
-#endif /* CCX_SUPPORT // */
- pAd->Mlme.CntlMachine.CurrState = CNTL_IDLE;
-
- /* */
- /* Check if we can connect to. */
- /* */
- BssTableSsidSort(pAd, &pAd->MlmeAux.SsidBssTab,
- (char *) pAd->MlmeAux.
- AutoReconnectSsid,
- pAd->MlmeAux.AutoReconnectSsidLen);
- if (pAd->MlmeAux.SsidBssTab.BssNr > 0) {
- MlmeAutoReconnectLastSSID(pAd);
- }
- }
- break;
-#endif /* RTMP_MAC_USB // */
- default:
- DBGPRINT_ERR("ERROR! CNTL - Illegal message type(=%ld)", Elem->MsgType);
- break;
- }
-}
-
-/*
- ==========================================================================
- Description:
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
-*/
-void CntlIdleProc(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
- struct rt_mlme_disassoc_req DisassocReq;
-
- if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_RADIO_OFF))
- return;
-
- switch (Elem->MsgType) {
- case OID_802_11_SSID:
- CntlOidSsidProc(pAd, Elem);
- break;
-
- case OID_802_11_BSSID:
- CntlOidRTBssidProc(pAd, Elem);
- break;
-
- case OID_802_11_BSSID_LIST_SCAN:
- CntlOidScanProc(pAd, Elem);
- break;
-
- case OID_802_11_DISASSOCIATE:
- DisassocParmFill(pAd, &DisassocReq, pAd->CommonCfg.Bssid,
- REASON_DISASSOC_STA_LEAVING);
- MlmeEnqueue(pAd, ASSOC_STATE_MACHINE, MT2_MLME_DISASSOC_REQ,
- sizeof(struct rt_mlme_disassoc_req), &DisassocReq);
- pAd->Mlme.CntlMachine.CurrState = CNTL_WAIT_OID_DISASSOC;
-
- if (pAd->StaCfg.WpaSupplicantUP !=
- WPA_SUPPLICANT_ENABLE_WITH_WEB_UI) {
- /* Set the AutoReconnectSsid to prevent it reconnect to old SSID */
- /* Since calling this indicate user don't want to connect to that SSID anymore. */
- pAd->MlmeAux.AutoReconnectSsidLen = 32;
- NdisZeroMemory(pAd->MlmeAux.AutoReconnectSsid,
- pAd->MlmeAux.AutoReconnectSsidLen);
- }
- break;
-
- case MT2_MLME_ROAMING_REQ:
- CntlMlmeRoamingProc(pAd, Elem);
- break;
-
- case OID_802_11_MIC_FAILURE_REPORT_FRAME:
- WpaMicFailureReportFrame(pAd, Elem);
- break;
-
- default:
- DBGPRINT(RT_DEBUG_TRACE,
- ("CNTL - Illegal message in CntlIdleProc(MsgType=%ld)\n",
- Elem->MsgType));
- break;
- }
-}
-
-void CntlOidScanProc(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
- struct rt_mlme_scan_req ScanReq;
- unsigned long BssIdx = BSS_NOT_FOUND;
- struct rt_bss_entry CurrBss;
-
- /* record current BSS if network is connected. */
- /* 2003-2-13 do not include current IBSS if this is the only STA in this IBSS. */
- if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_MEDIA_STATE_CONNECTED)) {
- BssIdx =
- BssSsidTableSearch(&pAd->ScanTab, pAd->CommonCfg.Bssid,
- (u8 *)pAd->CommonCfg.Ssid,
- pAd->CommonCfg.SsidLen,
- pAd->CommonCfg.Channel);
- if (BssIdx != BSS_NOT_FOUND) {
- NdisMoveMemory(&CurrBss, &pAd->ScanTab.BssEntry[BssIdx],
- sizeof(struct rt_bss_entry));
- }
- }
- /* clean up previous SCAN result, add current BSS back to table if any */
- BssTableInit(&pAd->ScanTab);
- if (BssIdx != BSS_NOT_FOUND) {
- /* DDK Note: If the NIC is associated with a particular BSSID and SSID */
- /* that are not contained in the list of BSSIDs generated by this scan, the */
- /* BSSID description of the currently associated BSSID and SSID should be */
- /* appended to the list of BSSIDs in the NIC's database. */
- /* To ensure this, we append this BSS as the first entry in SCAN result */
- NdisMoveMemory(&pAd->ScanTab.BssEntry[0], &CurrBss,
- sizeof(struct rt_bss_entry));
- pAd->ScanTab.BssNr = 1;
- }
-
- ScanParmFill(pAd, &ScanReq, (char *)Elem->Msg, Elem->MsgLen, BSS_ANY,
- SCAN_ACTIVE);
- MlmeEnqueue(pAd, SYNC_STATE_MACHINE, MT2_MLME_SCAN_REQ,
- sizeof(struct rt_mlme_scan_req), &ScanReq);
- pAd->Mlme.CntlMachine.CurrState = CNTL_WAIT_OID_LIST_SCAN;
-}
-
-/*
- ==========================================================================
- Description:
- Before calling this routine, user desired SSID should already been
- recorded in CommonCfg.Ssid[]
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
-*/
-void CntlOidSsidProc(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
- struct rt_ndis_802_11_ssid * pOidSsid = (struct rt_ndis_802_11_ssid *) Elem->Msg;
- struct rt_mlme_disassoc_req DisassocReq;
- unsigned long Now;
-
- /* Step 1. record the desired user settings to MlmeAux */
- NdisZeroMemory(pAd->MlmeAux.Ssid, MAX_LEN_OF_SSID);
- NdisMoveMemory(pAd->MlmeAux.Ssid, pOidSsid->Ssid, pOidSsid->SsidLength);
- pAd->MlmeAux.SsidLen = (u8)pOidSsid->SsidLength;
- NdisZeroMemory(pAd->MlmeAux.Bssid, MAC_ADDR_LEN);
- pAd->MlmeAux.BssType = pAd->StaCfg.BssType;
-
- pAd->StaCfg.bAutoConnectByBssid = FALSE;
-
- /* */
- /* Update Reconnect Ssid, that user desired to connect. */
- /* */
- NdisZeroMemory(pAd->MlmeAux.AutoReconnectSsid, MAX_LEN_OF_SSID);
- NdisMoveMemory(pAd->MlmeAux.AutoReconnectSsid, pAd->MlmeAux.Ssid,
- pAd->MlmeAux.SsidLen);
- pAd->MlmeAux.AutoReconnectSsidLen = pAd->MlmeAux.SsidLen;
-
- /* step 2. find all matching BSS in the lastest SCAN result (inBssTab) */
- /* & log them into MlmeAux.SsidBssTab for later-on iteration. Sort by RSSI order */
- BssTableSsidSort(pAd, &pAd->MlmeAux.SsidBssTab,
- (char *)pAd->MlmeAux.Ssid, pAd->MlmeAux.SsidLen);
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("CntlOidSsidProc():CNTL - %d BSS of %d BSS match the desire (%d)SSID - %s\n",
- pAd->MlmeAux.SsidBssTab.BssNr, pAd->ScanTab.BssNr,
- pAd->MlmeAux.SsidLen, pAd->MlmeAux.Ssid));
- NdisGetSystemUpTime(&Now);
-
- if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_MEDIA_STATE_CONNECTED) &&
- (pAd->CommonCfg.SsidLen ==
- pAd->MlmeAux.SsidBssTab.BssEntry[0].SsidLen)
- && NdisEqualMemory(pAd->CommonCfg.Ssid,
- pAd->MlmeAux.SsidBssTab.BssEntry[0].Ssid,
- pAd->CommonCfg.SsidLen)
- && MAC_ADDR_EQUAL(pAd->CommonCfg.Bssid,
- pAd->MlmeAux.SsidBssTab.BssEntry[0].Bssid)) {
- /* Case 1. already connected with an AP who has the desired SSID */
- /* with highest RSSI */
-
- /* Add checking Mode "LEAP" for CCX 1.0 */
- if (((pAd->StaCfg.AuthMode == Ndis802_11AuthModeWPA) ||
- (pAd->StaCfg.AuthMode == Ndis802_11AuthModeWPAPSK) ||
- (pAd->StaCfg.AuthMode == Ndis802_11AuthModeWPA2) ||
- (pAd->StaCfg.AuthMode == Ndis802_11AuthModeWPA2PSK)
- ) &&
- (pAd->StaCfg.PortSecured == WPA_802_1X_PORT_NOT_SECURED)) {
- /* case 1.1 For WPA, WPA-PSK, if the 1x port is not secured, we have to redo */
- /* connection process */
- DBGPRINT(RT_DEBUG_TRACE,
- ("CntlOidSsidProc():CNTL - disassociate with current AP...\n"));
- DisassocParmFill(pAd, &DisassocReq,
- pAd->CommonCfg.Bssid,
- REASON_DISASSOC_STA_LEAVING);
- MlmeEnqueue(pAd, ASSOC_STATE_MACHINE,
- MT2_MLME_DISASSOC_REQ,
- sizeof(struct rt_mlme_disassoc_req),
- &DisassocReq);
- pAd->Mlme.CntlMachine.CurrState = CNTL_WAIT_DISASSOC;
- } else if (pAd->bConfigChanged == TRUE) {
- /* case 1.2 Important Config has changed, we have to reconnect to the same AP */
- DBGPRINT(RT_DEBUG_TRACE,
- ("CntlOidSsidProc():CNTL - disassociate with current AP Because config changed...\n"));
- DisassocParmFill(pAd, &DisassocReq,
- pAd->CommonCfg.Bssid,
- REASON_DISASSOC_STA_LEAVING);
- MlmeEnqueue(pAd, ASSOC_STATE_MACHINE,
- MT2_MLME_DISASSOC_REQ,
- sizeof(struct rt_mlme_disassoc_req),
- &DisassocReq);
- pAd->Mlme.CntlMachine.CurrState = CNTL_WAIT_DISASSOC;
- } else {
- /* case 1.3. already connected to the SSID with highest RSSI. */
- DBGPRINT(RT_DEBUG_TRACE,
- ("CntlOidSsidProc():CNTL - already with this BSSID. ignore this SET_SSID request\n"));
- /* */
- /* (HCT 12.1) 1c_wlan_mediaevents required */
- /* media connect events are indicated when associating with the same AP */
- /* */
- if (INFRA_ON(pAd)) {
- /* */
- /* Since MediaState already is NdisMediaStateConnected */
- /* We just indicate the connect event again to meet the WHQL required. */
- /* */
- pAd->IndicateMediaState =
- NdisMediaStateConnected;
- RTMP_IndicateMediaState(pAd);
- pAd->ExtraInfo = GENERAL_LINK_UP; /* Update extra information to link is up */
- }
-
- pAd->Mlme.CntlMachine.CurrState = CNTL_IDLE;
- RtmpOSWrielessEventSend(pAd, SIOCGIWAP, -1,
- &pAd->MlmeAux.Bssid[0], NULL,
- 0);
- }
- } else if (INFRA_ON(pAd)) {
- /* */
- /* For RT61 */
- /* [88888] OID_802_11_SSID should have returned NDTEST_WEP_AP2(Returned: ) */
- /* RT61 may lost SSID, and not connect to NDTEST_WEP_AP2 and will connect to NDTEST_WEP_AP2 by Autoreconnect */
- /* But media status is connected, so the SSID not report correctly. */
- /* */
- if (!SSID_EQUAL
- (pAd->CommonCfg.Ssid, pAd->CommonCfg.SsidLen,
- pAd->MlmeAux.Ssid, pAd->MlmeAux.SsidLen)) {
- /* */
- /* Different SSID means not Roaming case, so we let LinkDown() to Indicate a disconnect event. */
- /* */
- pAd->MlmeAux.CurrReqIsFromNdis = TRUE;
- }
- /* case 2. active INFRA association existent */
- /* roaming is done within miniport driver, nothing to do with configuration */
- /* utility. so upon a new SET(OID_802_11_SSID) is received, we just */
- /* disassociate with the current associated AP, */
- /* then perform a new association with this new SSID, no matter the */
- /* new/old SSID are the same or not. */
- DBGPRINT(RT_DEBUG_TRACE,
- ("CntlOidSsidProc():CNTL - disassociate with current AP...\n"));
- DisassocParmFill(pAd, &DisassocReq, pAd->CommonCfg.Bssid,
- REASON_DISASSOC_STA_LEAVING);
- MlmeEnqueue(pAd, ASSOC_STATE_MACHINE, MT2_MLME_DISASSOC_REQ,
- sizeof(struct rt_mlme_disassoc_req), &DisassocReq);
- pAd->Mlme.CntlMachine.CurrState = CNTL_WAIT_DISASSOC;
- } else {
- if (ADHOC_ON(pAd)) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("CntlOidSsidProc():CNTL - drop current ADHOC\n"));
- LinkDown(pAd, FALSE);
- OPSTATUS_CLEAR_FLAG(pAd,
- fOP_STATUS_MEDIA_STATE_CONNECTED);
- pAd->IndicateMediaState = NdisMediaStateDisconnected;
- RTMP_IndicateMediaState(pAd);
- pAd->ExtraInfo = GENERAL_LINK_DOWN;
- DBGPRINT(RT_DEBUG_TRACE,
- ("CntlOidSsidProc():NDIS_STATUS_MEDIA_DISCONNECT Event C!\n"));
- }
-
- if ((pAd->MlmeAux.SsidBssTab.BssNr == 0) &&
- (pAd->StaCfg.bAutoReconnect == TRUE) &&
- (pAd->MlmeAux.BssType == BSS_INFRA) &&
- (MlmeValidateSSID(pAd->MlmeAux.Ssid, pAd->MlmeAux.SsidLen)
- == TRUE)
- ) {
- struct rt_mlme_scan_req ScanReq;
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("CntlOidSsidProc():CNTL - No matching BSS, start a new scan\n"));
- ScanParmFill(pAd, &ScanReq, (char *)pAd->MlmeAux.Ssid,
- pAd->MlmeAux.SsidLen, BSS_ANY,
- SCAN_ACTIVE);
- MlmeEnqueue(pAd, SYNC_STATE_MACHINE, MT2_MLME_SCAN_REQ,
- sizeof(struct rt_mlme_scan_req), &ScanReq);
- pAd->Mlme.CntlMachine.CurrState =
- CNTL_WAIT_OID_LIST_SCAN;
- /* Reset Missed scan number */
- pAd->StaCfg.LastScanTime = Now;
- } else {
- pAd->MlmeAux.BssIdx = 0;
- IterateOnBssTab(pAd);
- }
- }
-}
-
-/*
- ==========================================================================
- Description:
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
-*/
-void CntlOidRTBssidProc(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
- unsigned long BssIdx;
- u8 *pOidBssid = (u8 *)Elem->Msg;
- struct rt_mlme_disassoc_req DisassocReq;
- struct rt_mlme_join_req JoinReq;
-
- /* record user desired settings */
- COPY_MAC_ADDR(pAd->MlmeAux.Bssid, pOidBssid);
- pAd->MlmeAux.BssType = pAd->StaCfg.BssType;
-
- /* find the desired BSS in the latest SCAN result table */
- BssIdx = BssTableSearch(&pAd->ScanTab, pOidBssid, pAd->MlmeAux.Channel);
- if (BssIdx == BSS_NOT_FOUND) {
- struct rt_mlme_scan_req ScanReq;
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("CNTL - BSSID not found. reply NDIS_STATUS_NOT_ACCEPTED\n"));
- /*pAd->Mlme.CntlMachine.CurrState = CNTL_IDLE; */
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("CNTL - BSSID not found. start a new scan\n"));
- ScanParmFill(pAd, &ScanReq, (char *)pAd->MlmeAux.Ssid,
- pAd->MlmeAux.SsidLen, BSS_ANY, SCAN_ACTIVE);
- MlmeEnqueue(pAd, SYNC_STATE_MACHINE, MT2_MLME_SCAN_REQ,
- sizeof(struct rt_mlme_scan_req), &ScanReq);
- pAd->Mlme.CntlMachine.CurrState = CNTL_WAIT_OID_LIST_SCAN;
- /* Reset Missed scan number */
- NdisGetSystemUpTime(&pAd->StaCfg.LastScanTime);
- return;
- }
- /* */
- /* Update Reconnect Ssid, that user desired to connect. */
- /* */
- NdisZeroMemory(pAd->MlmeAux.AutoReconnectSsid, MAX_LEN_OF_SSID);
- pAd->MlmeAux.AutoReconnectSsidLen =
- pAd->ScanTab.BssEntry[BssIdx].SsidLen;
- NdisMoveMemory(pAd->MlmeAux.AutoReconnectSsid,
- pAd->ScanTab.BssEntry[BssIdx].Ssid,
- pAd->ScanTab.BssEntry[BssIdx].SsidLen);
-
- /* copy the matched BSS entry from ScanTab to MlmeAux.SsidBssTab. Why? */
- /* Because we need this entry to become the JOIN target in later on SYNC state machine */
- pAd->MlmeAux.BssIdx = 0;
- pAd->MlmeAux.SsidBssTab.BssNr = 1;
- NdisMoveMemory(&pAd->MlmeAux.SsidBssTab.BssEntry[0],
- &pAd->ScanTab.BssEntry[BssIdx], sizeof(struct rt_bss_entry));
-
- /* Add SSID into MlmeAux for site survey joining hidden SSID */
- pAd->MlmeAux.SsidLen = pAd->ScanTab.BssEntry[BssIdx].SsidLen;
- NdisMoveMemory(pAd->MlmeAux.Ssid, pAd->ScanTab.BssEntry[BssIdx].Ssid,
- pAd->MlmeAux.SsidLen);
-
- {
- if (INFRA_ON(pAd)) {
- /* disassoc from current AP first */
- DBGPRINT(RT_DEBUG_TRACE,
- ("CNTL - disassociate with current AP ...\n"));
- DisassocParmFill(pAd, &DisassocReq,
- pAd->CommonCfg.Bssid,
- REASON_DISASSOC_STA_LEAVING);
- MlmeEnqueue(pAd, ASSOC_STATE_MACHINE,
- MT2_MLME_DISASSOC_REQ,
- sizeof(struct rt_mlme_disassoc_req),
- &DisassocReq);
-
- pAd->Mlme.CntlMachine.CurrState = CNTL_WAIT_DISASSOC;
- } else {
- if (ADHOC_ON(pAd)) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("CNTL - drop current ADHOC\n"));
- LinkDown(pAd, FALSE);
- OPSTATUS_CLEAR_FLAG(pAd,
- fOP_STATUS_MEDIA_STATE_CONNECTED);
- pAd->IndicateMediaState =
- NdisMediaStateDisconnected;
- RTMP_IndicateMediaState(pAd);
- pAd->ExtraInfo = GENERAL_LINK_DOWN;
- DBGPRINT(RT_DEBUG_TRACE,
- ("NDIS_STATUS_MEDIA_DISCONNECT Event C!\n"));
- }
- /* Change the wepstatus to original wepstatus */
- pAd->StaCfg.WepStatus = pAd->StaCfg.OrigWepStatus;
- pAd->StaCfg.PairCipher = pAd->StaCfg.OrigWepStatus;
- pAd->StaCfg.GroupCipher = pAd->StaCfg.OrigWepStatus;
-
- /* Check cipher suite, AP must have more secured cipher than station setting */
- /* Set the Pairwise and Group cipher to match the intended AP setting */
- /* We can only connect to AP with less secured cipher setting */
- if ((pAd->StaCfg.AuthMode == Ndis802_11AuthModeWPA)
- || (pAd->StaCfg.AuthMode ==
- Ndis802_11AuthModeWPAPSK)) {
- pAd->StaCfg.GroupCipher =
- pAd->ScanTab.BssEntry[BssIdx].WPA.
- GroupCipher;
-
- if (pAd->StaCfg.WepStatus ==
- pAd->ScanTab.BssEntry[BssIdx].WPA.
- PairCipher)
- pAd->StaCfg.PairCipher =
- pAd->ScanTab.BssEntry[BssIdx].WPA.
- PairCipher;
- else if (pAd->ScanTab.BssEntry[BssIdx].WPA.
- PairCipherAux != Ndis802_11WEPDisabled)
- pAd->StaCfg.PairCipher =
- pAd->ScanTab.BssEntry[BssIdx].WPA.
- PairCipherAux;
- else /* There is no PairCipher Aux, downgrade our capability to TKIP */
- pAd->StaCfg.PairCipher =
- Ndis802_11Encryption2Enabled;
- } else
- if ((pAd->StaCfg.AuthMode == Ndis802_11AuthModeWPA2)
- || (pAd->StaCfg.AuthMode ==
- Ndis802_11AuthModeWPA2PSK)) {
- pAd->StaCfg.GroupCipher =
- pAd->ScanTab.BssEntry[BssIdx].WPA2.
- GroupCipher;
-
- if (pAd->StaCfg.WepStatus ==
- pAd->ScanTab.BssEntry[BssIdx].WPA2.
- PairCipher)
- pAd->StaCfg.PairCipher =
- pAd->ScanTab.BssEntry[BssIdx].WPA2.
- PairCipher;
- else if (pAd->ScanTab.BssEntry[BssIdx].WPA2.
- PairCipherAux != Ndis802_11WEPDisabled)
- pAd->StaCfg.PairCipher =
- pAd->ScanTab.BssEntry[BssIdx].WPA2.
- PairCipherAux;
- else /* There is no PairCipher Aux, downgrade our capability to TKIP */
- pAd->StaCfg.PairCipher =
- Ndis802_11Encryption2Enabled;
-
- /* RSN capability */
- pAd->StaCfg.RsnCapability =
- pAd->ScanTab.BssEntry[BssIdx].WPA2.
- RsnCapability;
- }
- /* Set Mix cipher flag */
- pAd->StaCfg.bMixCipher =
- (pAd->StaCfg.PairCipher ==
- pAd->StaCfg.GroupCipher) ? FALSE : TRUE;
- /*if (pAd->StaCfg.bMixCipher == TRUE)
- {
- // If mix cipher, re-build RSNIE
- RTMPMakeRSNIE(pAd, pAd->StaCfg.AuthMode, pAd->StaCfg.WepStatus, 0);
- } */
- /* No active association, join the BSS immediately */
- DBGPRINT(RT_DEBUG_TRACE, ("CNTL - joining %pM ...\n",
- pOidBssid));
-
- JoinParmFill(pAd, &JoinReq, pAd->MlmeAux.BssIdx);
- MlmeEnqueue(pAd, SYNC_STATE_MACHINE, MT2_MLME_JOIN_REQ,
- sizeof(struct rt_mlme_join_req), &JoinReq);
-
- pAd->Mlme.CntlMachine.CurrState = CNTL_WAIT_JOIN;
- }
- }
-}
-
-/* Roaming is the only external request triggering CNTL state machine */
-/* despite of other "SET OID" operation. All "SET OID" related operations */
-/* happen in sequence, because no other SET OID will be sent to this device */
-/* until the the previous SET operation is complete (successful o failed). */
-/* So, how do we quarantee this ROAMING request won't corrupt other "SET OID"? */
-/* or been corrupted by other "SET OID"? */
-/* */
-/* IRQL = DISPATCH_LEVEL */
-void CntlMlmeRoamingProc(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
- u8 BBPValue = 0;
-
- DBGPRINT(RT_DEBUG_TRACE, ("CNTL - Roaming in MlmeAux.RoamTab...\n"));
-
- {
- /*Let BBP register at 20MHz to do (fast) roaming. */
- RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &BBPValue);
- BBPValue &= (~0x18);
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, BBPValue);
-
- NdisMoveMemory(&pAd->MlmeAux.SsidBssTab, &pAd->MlmeAux.RoamTab,
- sizeof(pAd->MlmeAux.RoamTab));
- pAd->MlmeAux.SsidBssTab.BssNr = pAd->MlmeAux.RoamTab.BssNr;
-
- BssTableSortByRssi(&pAd->MlmeAux.SsidBssTab);
- pAd->MlmeAux.BssIdx = 0;
- IterateOnBssTab(pAd);
- }
-}
-
-/*
- ==========================================================================
- Description:
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
-*/
-void CntlWaitDisassocProc(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
- struct rt_mlme_start_req StartReq;
-
- if (Elem->MsgType == MT2_DISASSOC_CONF) {
- DBGPRINT(RT_DEBUG_TRACE, ("CNTL - Dis-associate successful\n"));
-
- if (pAd->CommonCfg.bWirelessEvent) {
- RTMPSendWirelessEvent(pAd, IW_DISASSOC_EVENT_FLAG,
- pAd->MacTab.Content[BSSID_WCID].
- Addr, BSS0, 0);
- }
-
- LinkDown(pAd, FALSE);
-
- /* case 1. no matching BSS, and user wants ADHOC, so we just start a new one */
- if ((pAd->MlmeAux.SsidBssTab.BssNr == 0)
- && (pAd->StaCfg.BssType == BSS_ADHOC)) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("CNTL - No matching BSS, start a new ADHOC (Ssid=%s)...\n",
- pAd->MlmeAux.Ssid));
- StartParmFill(pAd, &StartReq, (char *)pAd->MlmeAux.Ssid,
- pAd->MlmeAux.SsidLen);
- MlmeEnqueue(pAd, SYNC_STATE_MACHINE, MT2_MLME_START_REQ,
- sizeof(struct rt_mlme_start_req), &StartReq);
- pAd->Mlme.CntlMachine.CurrState = CNTL_WAIT_START;
- }
- /* case 2. try each matched BSS */
- else {
- pAd->MlmeAux.BssIdx = 0;
-
- IterateOnBssTab(pAd);
- }
- }
-}
-
-/*
- ==========================================================================
- Description:
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
-*/
-void CntlWaitJoinProc(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
- u16 Reason;
- struct rt_mlme_auth_req AuthReq;
-
- if (Elem->MsgType == MT2_JOIN_CONF) {
- NdisMoveMemory(&Reason, Elem->Msg, sizeof(u16));
- if (Reason == MLME_SUCCESS) {
- /* 1. joined an IBSS, we are pretty much done here */
- if (pAd->MlmeAux.BssType == BSS_ADHOC) {
- /* */
- /* 5G bands rules of Japan: */
- /* Ad hoc must be disabled in W53(ch52,56,60,64) channels. */
- /* */
- if ((pAd->CommonCfg.bIEEE80211H == 1) &&
- RadarChannelCheck(pAd,
- pAd->CommonCfg.Channel)
- ) {
- pAd->Mlme.CntlMachine.CurrState =
- CNTL_IDLE;
- DBGPRINT(RT_DEBUG_TRACE,
- ("CNTL - Channel=%d, Join adhoc on W53(52,56,60,64) Channels are not accepted\n",
- pAd->CommonCfg.Channel));
- return;
- }
-
- LinkUp(pAd, BSS_ADHOC);
- pAd->Mlme.CntlMachine.CurrState = CNTL_IDLE;
- DBGPRINT(RT_DEBUG_TRACE,
- ("CNTL - join the IBSS = %pM ...\n",
- pAd->CommonCfg.Bssid));
-
- pAd->IndicateMediaState =
- NdisMediaStateConnected;
- pAd->ExtraInfo = GENERAL_LINK_UP;
- }
- /* 2. joined a new INFRA network, start from authentication */
- else {
- {
- /* either Ndis802_11AuthModeShared or Ndis802_11AuthModeAutoSwitch, try shared key first */
- if ((pAd->StaCfg.AuthMode ==
- Ndis802_11AuthModeShared)
- || (pAd->StaCfg.AuthMode ==
- Ndis802_11AuthModeAutoSwitch)) {
- AuthParmFill(pAd, &AuthReq,
- pAd->MlmeAux.Bssid,
- AUTH_MODE_KEY);
- } else {
- AuthParmFill(pAd, &AuthReq,
- pAd->MlmeAux.Bssid,
- AUTH_MODE_OPEN);
- }
- MlmeEnqueue(pAd, AUTH_STATE_MACHINE,
- MT2_MLME_AUTH_REQ,
- sizeof
- (struct rt_mlme_auth_req),
- &AuthReq);
- }
-
- pAd->Mlme.CntlMachine.CurrState =
- CNTL_WAIT_AUTH;
- }
- } else {
- /* 3. failed, try next BSS */
- pAd->MlmeAux.BssIdx++;
- IterateOnBssTab(pAd);
- }
- }
-}
-
-/*
- ==========================================================================
- Description:
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
-*/
-void CntlWaitStartProc(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
- u16 Result;
-
- if (Elem->MsgType == MT2_START_CONF) {
- NdisMoveMemory(&Result, Elem->Msg, sizeof(u16));
- if (Result == MLME_SUCCESS) {
- /* */
- /* 5G bands rules of Japan: */
- /* Ad hoc must be disabled in W53(ch52,56,60,64) channels. */
- /* */
- if ((pAd->CommonCfg.bIEEE80211H == 1) &&
- RadarChannelCheck(pAd, pAd->CommonCfg.Channel)
- ) {
- pAd->Mlme.CntlMachine.CurrState = CNTL_IDLE;
- DBGPRINT(RT_DEBUG_TRACE,
- ("CNTL - Channel=%d, Start adhoc on W53(52,56,60,64) Channels are not accepted\n",
- pAd->CommonCfg.Channel));
- return;
- }
- NdisZeroMemory(&pAd->StaActive.SupportedPhyInfo.
- MCSSet[0], 16);
- if (pAd->CommonCfg.PhyMode >= PHY_11ABGN_MIXED) {
- N_ChannelCheck(pAd);
- SetCommonHT(pAd);
- NdisMoveMemory(&pAd->MlmeAux.AddHtInfo,
- &pAd->CommonCfg.AddHTInfo,
- sizeof(struct rt_add_ht_info_ie));
- RTMPCheckHt(pAd, BSSID_WCID,
- &pAd->CommonCfg.HtCapability,
- &pAd->CommonCfg.AddHTInfo);
- pAd->StaActive.SupportedPhyInfo.bHtEnable =
- TRUE;
- NdisMoveMemory(&pAd->StaActive.SupportedPhyInfo.
- MCSSet[0],
- &pAd->CommonCfg.HtCapability.
- MCSSet[0], 16);
- COPY_HTSETTINGS_FROM_MLME_AUX_TO_ACTIVE_CFG
- (pAd);
-
- if ((pAd->CommonCfg.HtCapability.HtCapInfo.
- ChannelWidth == BW_40)
- && (pAd->CommonCfg.AddHTInfo.AddHtInfo.
- ExtChanOffset == EXTCHA_ABOVE)) {
- pAd->MlmeAux.CentralChannel =
- pAd->CommonCfg.Channel + 2;
- } else
- if ((pAd->CommonCfg.HtCapability.HtCapInfo.
- ChannelWidth == BW_40)
- && (pAd->CommonCfg.AddHTInfo.AddHtInfo.
- ExtChanOffset == EXTCHA_BELOW)) {
- pAd->MlmeAux.CentralChannel =
- pAd->CommonCfg.Channel - 2;
- }
- } else {
- pAd->StaActive.SupportedPhyInfo.bHtEnable =
- FALSE;
- }
- LinkUp(pAd, BSS_ADHOC);
- pAd->Mlme.CntlMachine.CurrState = CNTL_IDLE;
- /* Before send beacon, driver need do radar detection */
- if ((pAd->CommonCfg.Channel > 14)
- && (pAd->CommonCfg.bIEEE80211H == 1)
- && RadarChannelCheck(pAd, pAd->CommonCfg.Channel)) {
- pAd->CommonCfg.RadarDetect.RDMode =
- RD_SILENCE_MODE;
- pAd->CommonCfg.RadarDetect.RDCount = 0;
- }
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("CNTL - start a new IBSS = %pM ...\n",
- pAd->CommonCfg.Bssid));
- } else {
- DBGPRINT(RT_DEBUG_TRACE,
- ("CNTL - Start IBSS fail. BUG!\n"));
- pAd->Mlme.CntlMachine.CurrState = CNTL_IDLE;
- }
- }
-}
-
-/*
- ==========================================================================
- Description:
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
-*/
-void CntlWaitAuthProc(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
- u16 Reason;
- struct rt_mlme_assoc_req AssocReq;
- struct rt_mlme_auth_req AuthReq;
-
- if (Elem->MsgType == MT2_AUTH_CONF) {
- NdisMoveMemory(&Reason, Elem->Msg, sizeof(u16));
- if (Reason == MLME_SUCCESS) {
- DBGPRINT(RT_DEBUG_TRACE, ("CNTL - AUTH OK\n"));
- AssocParmFill(pAd, &AssocReq, pAd->MlmeAux.Bssid,
- pAd->MlmeAux.CapabilityInfo,
- ASSOC_TIMEOUT,
- pAd->StaCfg.DefaultListenCount);
-
- {
- MlmeEnqueue(pAd, ASSOC_STATE_MACHINE,
- MT2_MLME_ASSOC_REQ,
- sizeof(struct rt_mlme_assoc_req),
- &AssocReq);
-
- pAd->Mlme.CntlMachine.CurrState =
- CNTL_WAIT_ASSOC;
- }
- } else {
- /* This fail may because of the AP already keep us in its MAC table without */
- /* ageing-out. The previous authentication attempt must have let it remove us. */
- /* so try Authentication again may help. For D-Link DWL-900AP+ compatibility. */
- DBGPRINT(RT_DEBUG_TRACE,
- ("CNTL - AUTH FAIL, try again...\n"));
-
- {
- if ((pAd->StaCfg.AuthMode ==
- Ndis802_11AuthModeShared)
- || (pAd->StaCfg.AuthMode ==
- Ndis802_11AuthModeAutoSwitch)) {
- /* either Ndis802_11AuthModeShared or Ndis802_11AuthModeAutoSwitch, try shared key first */
- AuthParmFill(pAd, &AuthReq,
- pAd->MlmeAux.Bssid,
- AUTH_MODE_KEY);
- } else {
- AuthParmFill(pAd, &AuthReq,
- pAd->MlmeAux.Bssid,
- AUTH_MODE_OPEN);
- }
- MlmeEnqueue(pAd, AUTH_STATE_MACHINE,
- MT2_MLME_AUTH_REQ,
- sizeof(struct rt_mlme_auth_req),
- &AuthReq);
-
- }
- pAd->Mlme.CntlMachine.CurrState = CNTL_WAIT_AUTH2;
- }
- }
-}
-
-/*
- ==========================================================================
- Description:
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
-*/
-void CntlWaitAuthProc2(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
- u16 Reason;
- struct rt_mlme_assoc_req AssocReq;
- struct rt_mlme_auth_req AuthReq;
-
- if (Elem->MsgType == MT2_AUTH_CONF) {
- NdisMoveMemory(&Reason, Elem->Msg, sizeof(u16));
- if (Reason == MLME_SUCCESS) {
- DBGPRINT(RT_DEBUG_TRACE, ("CNTL - AUTH OK\n"));
- AssocParmFill(pAd, &AssocReq, pAd->MlmeAux.Bssid,
- pAd->MlmeAux.CapabilityInfo,
- ASSOC_TIMEOUT,
- pAd->StaCfg.DefaultListenCount);
- {
- MlmeEnqueue(pAd, ASSOC_STATE_MACHINE,
- MT2_MLME_ASSOC_REQ,
- sizeof(struct rt_mlme_assoc_req),
- &AssocReq);
-
- pAd->Mlme.CntlMachine.CurrState =
- CNTL_WAIT_ASSOC;
- }
- } else {
- if ((pAd->StaCfg.AuthMode ==
- Ndis802_11AuthModeAutoSwitch)
- && (pAd->MlmeAux.Alg == Ndis802_11AuthModeShared)) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("CNTL - AUTH FAIL, try OPEN system...\n"));
- AuthParmFill(pAd, &AuthReq, pAd->MlmeAux.Bssid,
- Ndis802_11AuthModeOpen);
- MlmeEnqueue(pAd, AUTH_STATE_MACHINE,
- MT2_MLME_AUTH_REQ,
- sizeof(struct rt_mlme_auth_req),
- &AuthReq);
-
- pAd->Mlme.CntlMachine.CurrState =
- CNTL_WAIT_AUTH2;
- } else {
- /* not success, try next BSS */
- DBGPRINT(RT_DEBUG_TRACE,
- ("CNTL - AUTH FAIL, give up; try next BSS\n"));
- pAd->Mlme.CntlMachine.CurrState = CNTL_IDLE; /*??????? */
- pAd->MlmeAux.BssIdx++;
- IterateOnBssTab(pAd);
- }
- }
- }
-}
-
-/*
- ==========================================================================
- Description:
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
-*/
-void CntlWaitAssocProc(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
- u16 Reason;
-
- if (Elem->MsgType == MT2_ASSOC_CONF) {
- NdisMoveMemory(&Reason, Elem->Msg, sizeof(u16));
- if (Reason == MLME_SUCCESS) {
- if (pAd->CommonCfg.bWirelessEvent) {
- RTMPSendWirelessEvent(pAd, IW_ASSOC_EVENT_FLAG,
- pAd->MacTab.
- Content[BSSID_WCID].Addr,
- BSS0, 0);
- }
-
- LinkUp(pAd, BSS_INFRA);
- pAd->Mlme.CntlMachine.CurrState = CNTL_IDLE;
- DBGPRINT(RT_DEBUG_TRACE,
- ("CNTL - Association successful on BSS #%ld\n",
- pAd->MlmeAux.BssIdx));
- } else {
- /* not success, try next BSS */
- DBGPRINT(RT_DEBUG_TRACE,
- ("CNTL - Association fails on BSS #%ld\n",
- pAd->MlmeAux.BssIdx));
- pAd->MlmeAux.BssIdx++;
- IterateOnBssTab(pAd);
- }
- }
-}
-
-/*
- ==========================================================================
- Description:
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
-*/
-void CntlWaitReassocProc(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
- u16 Result;
-
- if (Elem->MsgType == MT2_REASSOC_CONF) {
- NdisMoveMemory(&Result, Elem->Msg, sizeof(u16));
- if (Result == MLME_SUCCESS) {
- /* send wireless event - for association */
- if (pAd->CommonCfg.bWirelessEvent)
- RTMPSendWirelessEvent(pAd, IW_ASSOC_EVENT_FLAG,
- pAd->MacTab.
- Content[BSSID_WCID].Addr,
- BSS0, 0);
-
- /* */
- /* NDIS requires a new Link UP indication but no Link Down for RE-ASSOC */
- /* */
- LinkUp(pAd, BSS_INFRA);
-
- pAd->Mlme.CntlMachine.CurrState = CNTL_IDLE;
- DBGPRINT(RT_DEBUG_TRACE,
- ("CNTL - Re-assocition successful on BSS #%ld\n",
- pAd->MlmeAux.RoamIdx));
- } else {
- /* reassoc failed, try to pick next BSS in the BSS Table */
- DBGPRINT(RT_DEBUG_TRACE,
- ("CNTL - Re-assocition fails on BSS #%ld\n",
- pAd->MlmeAux.RoamIdx));
- {
- pAd->MlmeAux.RoamIdx++;
- IterateOnBssTab2(pAd);
- }
- }
- }
-}
-
-void AdhocTurnOnQos(struct rt_rtmp_adapter *pAd)
-{
-#define AC0_DEF_TXOP 0
-#define AC1_DEF_TXOP 0
-#define AC2_DEF_TXOP 94
-#define AC3_DEF_TXOP 47
-
- /* Turn on QOs if use HT rate. */
- if (pAd->CommonCfg.APEdcaParm.bValid == FALSE) {
- pAd->CommonCfg.APEdcaParm.bValid = TRUE;
- pAd->CommonCfg.APEdcaParm.Aifsn[0] = 3;
- pAd->CommonCfg.APEdcaParm.Aifsn[1] = 7;
- pAd->CommonCfg.APEdcaParm.Aifsn[2] = 1;
- pAd->CommonCfg.APEdcaParm.Aifsn[3] = 1;
-
- pAd->CommonCfg.APEdcaParm.Cwmin[0] = 4;
- pAd->CommonCfg.APEdcaParm.Cwmin[1] = 4;
- pAd->CommonCfg.APEdcaParm.Cwmin[2] = 3;
- pAd->CommonCfg.APEdcaParm.Cwmin[3] = 2;
-
- pAd->CommonCfg.APEdcaParm.Cwmax[0] = 10;
- pAd->CommonCfg.APEdcaParm.Cwmax[1] = 6;
- pAd->CommonCfg.APEdcaParm.Cwmax[2] = 4;
- pAd->CommonCfg.APEdcaParm.Cwmax[3] = 3;
-
- pAd->CommonCfg.APEdcaParm.Txop[0] = 0;
- pAd->CommonCfg.APEdcaParm.Txop[1] = 0;
- pAd->CommonCfg.APEdcaParm.Txop[2] = AC2_DEF_TXOP;
- pAd->CommonCfg.APEdcaParm.Txop[3] = AC3_DEF_TXOP;
- }
- AsicSetEdcaParm(pAd, &pAd->CommonCfg.APEdcaParm);
-}
-
-/*
- ==========================================================================
- Description:
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
-*/
-void LinkUp(struct rt_rtmp_adapter *pAd, u8 BssType)
-{
- unsigned long Now;
- u32 Data;
- BOOLEAN Cancelled;
- u8 Value = 0, idx = 0, HashIdx = 0;
- struct rt_mac_table_entry *pEntry = NULL, *pCurrEntry = NULL;
-
- /* Init ChannelQuality to prevent DEAD_CQI at initial LinkUp */
- pAd->Mlme.ChannelQuality = 50;
-
- pEntry = MacTableLookup(pAd, pAd->CommonCfg.Bssid);
- if (pEntry) {
- MacTableDeleteEntry(pAd, pEntry->Aid, pEntry->Addr);
- pEntry = NULL;
- }
-
- pEntry = &pAd->MacTab.Content[BSSID_WCID];
-
- /* */
- /* ASSOC - DisassocTimeoutAction */
- /* CNTL - Dis-associate successful */
- /* ! LINK DOWN ! */
- /* [88888] OID_802_11_SSID should have returned NDTEST_WEP_AP2(Returned: ) */
- /* */
- /* To prevent DisassocTimeoutAction to call Link down after we link up, */
- /* cancel the DisassocTimer no matter what it start or not. */
- /* */
- RTMPCancelTimer(&pAd->MlmeAux.DisassocTimer, &Cancelled);
-
- COPY_SETTINGS_FROM_MLME_AUX_TO_ACTIVE_CFG(pAd);
-
- COPY_HTSETTINGS_FROM_MLME_AUX_TO_ACTIVE_CFG(pAd);
-
-#ifdef RTMP_MAC_PCI
- /* Before power save before link up function, We will force use 1R. */
- /* So after link up, check Rx antenna # again. */
- RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &Value);
- if (pAd->Antenna.field.RxPath == 3) {
- Value |= (0x10);
- } else if (pAd->Antenna.field.RxPath == 2) {
- Value |= (0x8);
- } else if (pAd->Antenna.field.RxPath == 1) {
- Value |= (0x0);
- }
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, Value);
- pAd->StaCfg.BBPR3 = Value;
-#endif /* RTMP_MAC_PCI // */
-
- if (BssType == BSS_ADHOC) {
- OPSTATUS_SET_FLAG(pAd, fOP_STATUS_ADHOC_ON);
- OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_INFRA_ON);
-
- if (pAd->CommonCfg.PhyMode >= PHY_11ABGN_MIXED)
- AdhocTurnOnQos(pAd);
-
- DBGPRINT(RT_DEBUG_TRACE, ("Adhoc LINK UP!\n"));
- } else {
- OPSTATUS_SET_FLAG(pAd, fOP_STATUS_INFRA_ON);
- OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_ADHOC_ON);
-
- DBGPRINT(RT_DEBUG_TRACE, ("Infra LINK UP!\n"));
- }
-
- /* 3*3 */
- /* reset Tx beamforming bit */
- RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &Value);
- Value &= (~0x01);
- Value |= pAd->CommonCfg.RegTransmitSetting.field.TxBF;
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, Value);
-
- /* Change to AP channel */
- if ((pAd->CommonCfg.CentralChannel > pAd->CommonCfg.Channel)
- && (pAd->MlmeAux.HtCapability.HtCapInfo.ChannelWidth == BW_40)) {
- /* Must use 40MHz. */
- pAd->CommonCfg.BBPCurrentBW = BW_40;
- AsicSwitchChannel(pAd, pAd->CommonCfg.CentralChannel, FALSE);
- AsicLockChannel(pAd, pAd->CommonCfg.CentralChannel);
-
- RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &Value);
- Value &= (~0x18);
- Value |= 0x10;
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, Value);
-
- /* RX : control channel at lower */
- RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &Value);
- Value &= (~0x20);
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, Value);
-#ifdef RTMP_MAC_PCI
- pAd->StaCfg.BBPR3 = Value;
-#endif /* RTMP_MAC_PCI // */
-
- RTMP_IO_READ32(pAd, TX_BAND_CFG, &Data);
- Data &= 0xfffffffe;
- RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Data);
-
- if (pAd->MACVersion == 0x28600100) {
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x1A);
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, 0x0A);
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, 0x16);
- DBGPRINT(RT_DEBUG_TRACE, ("rt2860C !\n"));
- }
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("40MHz Lower LINK UP! Control Channel at Below. Central = %d \n",
- pAd->CommonCfg.CentralChannel));
- } else if ((pAd->CommonCfg.CentralChannel < pAd->CommonCfg.Channel)
- && (pAd->MlmeAux.HtCapability.HtCapInfo.ChannelWidth ==
- BW_40)) {
- /* Must use 40MHz. */
- pAd->CommonCfg.BBPCurrentBW = BW_40;
- AsicSwitchChannel(pAd, pAd->CommonCfg.CentralChannel, FALSE);
- AsicLockChannel(pAd, pAd->CommonCfg.CentralChannel);
-
- RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &Value);
- Value &= (~0x18);
- Value |= 0x10;
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, Value);
-
- RTMP_IO_READ32(pAd, TX_BAND_CFG, &Data);
- Data |= 0x1;
- RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Data);
-
- RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &Value);
- Value |= (0x20);
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, Value);
-#ifdef RTMP_MAC_PCI
- pAd->StaCfg.BBPR3 = Value;
-#endif /* RTMP_MAC_PCI // */
-
- if (pAd->MACVersion == 0x28600100) {
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x1A);
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, 0x0A);
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, 0x16);
- DBGPRINT(RT_DEBUG_TRACE, ("rt2860C !\n"));
- }
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("40MHz Upper LINK UP! Control Channel at UpperCentral = %d \n",
- pAd->CommonCfg.CentralChannel));
- } else {
- pAd->CommonCfg.BBPCurrentBW = BW_20;
- pAd->CommonCfg.CentralChannel = pAd->CommonCfg.Channel;
- AsicSwitchChannel(pAd, pAd->CommonCfg.Channel, FALSE);
- AsicLockChannel(pAd, pAd->CommonCfg.Channel);
-
- RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &Value);
- Value &= (~0x18);
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, Value);
-
- RTMP_IO_READ32(pAd, TX_BAND_CFG, &Data);
- Data &= 0xfffffffe;
- RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Data);
-
- RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R3, &Value);
- Value &= (~0x20);
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R3, Value);
-#ifdef RTMP_MAC_PCI
- pAd->StaCfg.BBPR3 = Value;
-#endif /* RTMP_MAC_PCI // */
-
- if (pAd->MACVersion == 0x28600100) {
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R69, 0x16);
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R70, 0x08);
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R73, 0x11);
- DBGPRINT(RT_DEBUG_TRACE, ("rt2860C !\n"));
- }
-
- DBGPRINT(RT_DEBUG_TRACE, ("20MHz LINK UP!\n"));
- }
-
- RTMPSetAGCInitValue(pAd, pAd->CommonCfg.BBPCurrentBW);
-
- /* */
- /* Save BBP_R66 value, it will be used in RTUSBResumeMsduTransmission */
- /* */
- RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R66,
- &pAd->BbpTuning.R66CurrentValue);
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("LINK UP! (BssType=%d, AID=%d, ssid=%s, Channel=%d, CentralChannel = %d)\n",
- BssType, pAd->StaActive.Aid, pAd->CommonCfg.Ssid,
- pAd->CommonCfg.Channel, pAd->CommonCfg.CentralChannel));
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("LINK UP! (Density =%d, )\n",
- pAd->MacTab.Content[BSSID_WCID].MpduDensity));
-
- AsicSetBssid(pAd, pAd->CommonCfg.Bssid);
-
- AsicSetSlotTime(pAd, TRUE);
- AsicSetEdcaParm(pAd, &pAd->CommonCfg.APEdcaParm);
-
- /* Call this for RTS protection for legacy rate, we will always enable RTS threshold, but normally it will not hit */
- AsicUpdateProtect(pAd, 0, (OFDMSETPROTECT | CCKSETPROTECT), TRUE,
- FALSE);
-
- if ((pAd->StaActive.SupportedPhyInfo.bHtEnable == TRUE)) {
- /* Update HT protection for based on AP's operating mode. */
- if (pAd->MlmeAux.AddHtInfo.AddHtInfo2.NonGfPresent == 1) {
- AsicUpdateProtect(pAd,
- pAd->MlmeAux.AddHtInfo.AddHtInfo2.
- OperaionMode, ALLN_SETPROTECT, FALSE,
- TRUE);
- } else
- AsicUpdateProtect(pAd,
- pAd->MlmeAux.AddHtInfo.AddHtInfo2.
- OperaionMode, ALLN_SETPROTECT, FALSE,
- FALSE);
- }
-
- NdisZeroMemory(&pAd->DrsCounters, sizeof(struct rt_counter_drs));
-
- NdisGetSystemUpTime(&Now);
- pAd->StaCfg.LastBeaconRxTime = Now; /* last RX timestamp */
-
- if ((pAd->CommonCfg.TxPreamble != Rt802_11PreambleLong) &&
- CAP_IS_SHORT_PREAMBLE_ON(pAd->StaActive.CapabilityInfo)) {
- MlmeSetTxPreamble(pAd, Rt802_11PreambleShort);
- }
-
- OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_AGGREGATION_INUSED);
-
- if (pAd->CommonCfg.RadarDetect.RDMode == RD_SILENCE_MODE) {
- }
- pAd->CommonCfg.RadarDetect.RDMode = RD_NORMAL_MODE;
-
- if (BssType == BSS_ADHOC) {
- MakeIbssBeacon(pAd);
- if ((pAd->CommonCfg.Channel > 14)
- && (pAd->CommonCfg.bIEEE80211H == 1)
- && RadarChannelCheck(pAd, pAd->CommonCfg.Channel)) {
- ; /*Do nothing */
- } else {
- AsicEnableIbssSync(pAd);
- }
-
- /* In ad hoc mode, use MAC table from index 1. */
- /* p.s ASIC use all 0xff as termination of WCID table search.To prevent it's 0xff-ff-ff-ff-ff-ff, Write 0 here. */
- RTMP_IO_WRITE32(pAd, MAC_WCID_BASE, 0x00);
- RTMP_IO_WRITE32(pAd, 0x1808, 0x00);
-
- /* If WEP is enabled, add key material and cipherAlg into Asic */
- /* Fill in Shared Key Table(offset: 0x6c00) and Shared Key Mode(offset: 0x7000) */
-
- if (pAd->StaCfg.WepStatus == Ndis802_11WEPEnabled) {
- u8 *Key;
- u8 CipherAlg;
-
- for (idx = 0; idx < SHARE_KEY_NUM; idx++) {
- CipherAlg = pAd->SharedKey[BSS0][idx].CipherAlg;
- Key = pAd->SharedKey[BSS0][idx].Key;
-
- if (pAd->SharedKey[BSS0][idx].KeyLen > 0) {
- /* Set key material and cipherAlg to Asic */
- AsicAddSharedKeyEntry(pAd, BSS0, idx,
- CipherAlg, Key,
- NULL, NULL);
-
- if (idx == pAd->StaCfg.DefaultKeyId) {
- /* Update WCID attribute table and IVEIV table for this group key table */
- RTMPAddWcidAttributeEntry(pAd,
- BSS0,
- idx,
- CipherAlg,
- NULL);
- }
- }
-
- }
- }
- /* If WPANone is enabled, add key material and cipherAlg into Asic */
- /* Fill in Shared Key Table(offset: 0x6c00) and Shared Key Mode(offset: 0x7000) */
- else if (pAd->StaCfg.AuthMode == Ndis802_11AuthModeWPANone) {
- pAd->StaCfg.DefaultKeyId = 0; /* always be zero */
-
- NdisZeroMemory(&pAd->SharedKey[BSS0][0],
- sizeof(struct rt_cipher_key));
- pAd->SharedKey[BSS0][0].KeyLen = LEN_TKIP_EK;
- NdisMoveMemory(pAd->SharedKey[BSS0][0].Key,
- pAd->StaCfg.PMK, LEN_TKIP_EK);
-
- if (pAd->StaCfg.PairCipher ==
- Ndis802_11Encryption2Enabled) {
- NdisMoveMemory(pAd->SharedKey[BSS0][0].RxMic,
- &pAd->StaCfg.PMK[16],
- LEN_TKIP_RXMICK);
- NdisMoveMemory(pAd->SharedKey[BSS0][0].TxMic,
- &pAd->StaCfg.PMK[16],
- LEN_TKIP_TXMICK);
- }
- /* Decide its ChiperAlg */
- if (pAd->StaCfg.PairCipher ==
- Ndis802_11Encryption2Enabled)
- pAd->SharedKey[BSS0][0].CipherAlg = CIPHER_TKIP;
- else if (pAd->StaCfg.PairCipher ==
- Ndis802_11Encryption3Enabled)
- pAd->SharedKey[BSS0][0].CipherAlg = CIPHER_AES;
- else {
- DBGPRINT(RT_DEBUG_TRACE,
- ("Unknow Cipher (=%d), set Cipher to AES\n",
- pAd->StaCfg.PairCipher));
- pAd->SharedKey[BSS0][0].CipherAlg = CIPHER_AES;
- }
-
- /* Set key material and cipherAlg to Asic */
- AsicAddSharedKeyEntry(pAd,
- BSS0,
- 0,
- pAd->SharedKey[BSS0][0].CipherAlg,
- pAd->SharedKey[BSS0][0].Key,
- pAd->SharedKey[BSS0][0].TxMic,
- pAd->SharedKey[BSS0][0].RxMic);
-
- /* Update WCID attribute table and IVEIV table for this group key table */
- RTMPAddWcidAttributeEntry(pAd, BSS0, 0,
- pAd->SharedKey[BSS0][0].
- CipherAlg, NULL);
-
- }
-
- } else /* BSS_INFRA */
- {
- /* Check the new SSID with last SSID */
- while (Cancelled == TRUE) {
- if (pAd->CommonCfg.LastSsidLen ==
- pAd->CommonCfg.SsidLen) {
- if (RTMPCompareMemory
- (pAd->CommonCfg.LastSsid,
- pAd->CommonCfg.Ssid,
- pAd->CommonCfg.LastSsidLen) == 0) {
- /* Link to the old one no linkdown is required. */
- break;
- }
- }
- /* Send link down event before set to link up */
- pAd->IndicateMediaState = NdisMediaStateDisconnected;
- RTMP_IndicateMediaState(pAd);
- pAd->ExtraInfo = GENERAL_LINK_DOWN;
- DBGPRINT(RT_DEBUG_TRACE,
- ("NDIS_STATUS_MEDIA_DISCONNECT Event AA!\n"));
- break;
- }
-
- /* */
- /* On WPA mode, Remove All Keys if not connect to the last BSSID */
- /* Key will be set after 4-way handshake. */
- /* */
- if (pAd->StaCfg.AuthMode >= Ndis802_11AuthModeWPA) {
- unsigned long IV;
-
- /* Remove all WPA keys */
- RTMP_CLEAR_PSFLAG(pAd, fRTMP_PS_CAN_GO_SLEEP);
- RTMPWPARemoveAllKeys(pAd);
- pAd->StaCfg.PortSecured = WPA_802_1X_PORT_NOT_SECURED;
- pAd->StaCfg.PrivacyFilter =
- Ndis802_11PrivFilter8021xWEP;
-
- /* Fixed connection failed with Range Maximizer - 515 AP (Marvell Chip) when security is WPAPSK/TKIP */
- /* If IV related values are too large in GroupMsg2, AP would ignore this message. */
- IV = 1;
- IV |= (pAd->StaCfg.DefaultKeyId << 30);
- AsicUpdateWCIDIVEIV(pAd, BSSID_WCID, IV, 0);
- }
- /* NOTE: */
- /* the decision of using "short slot time" or not may change dynamically due to */
- /* new STA association to the AP. so we have to decide that upon parsing BEACON, not here */
-
- /* NOTE: */
- /* the decision to use "RTC/CTS" or "CTS-to-self" protection or not may change dynamically */
- /* due to new STA association to the AP. so we have to decide that upon parsing BEACON, not here */
-
- ComposePsPoll(pAd);
- ComposeNullFrame(pAd);
-
- AsicEnableBssSync(pAd);
-
- /* Add BSSID to WCID search table */
- AsicUpdateRxWCIDTable(pAd, BSSID_WCID, pAd->CommonCfg.Bssid);
-
- /* If WEP is enabled, add pairwise and shared key */
- if (((pAd->StaCfg.WpaSupplicantUP) &&
- (pAd->StaCfg.WepStatus == Ndis802_11WEPEnabled) &&
- (pAd->StaCfg.PortSecured == WPA_802_1X_PORT_SECURED)) ||
- ((pAd->StaCfg.WpaSupplicantUP == WPA_SUPPLICANT_DISABLE) &&
- (pAd->StaCfg.WepStatus == Ndis802_11WEPEnabled))) {
- u8 *Key;
- u8 CipherAlg;
-
- for (idx = 0; idx < SHARE_KEY_NUM; idx++) {
- CipherAlg = pAd->SharedKey[BSS0][idx].CipherAlg;
- Key = pAd->SharedKey[BSS0][idx].Key;
-
- if (pAd->SharedKey[BSS0][idx].KeyLen > 0) {
- /* Set key material and cipherAlg to Asic */
- AsicAddSharedKeyEntry(pAd, BSS0, idx,
- CipherAlg, Key,
- NULL, NULL);
-
- if (idx == pAd->StaCfg.DefaultKeyId) {
- /* Assign group key info */
- RTMPAddWcidAttributeEntry(pAd,
- BSS0,
- idx,
- CipherAlg,
- NULL);
-
- pEntry->Aid = BSSID_WCID;
- /* Assign pairwise key info */
- RTMPAddWcidAttributeEntry(pAd,
- BSS0,
- idx,
- CipherAlg,
- pEntry);
- }
- }
- }
- }
- /* only INFRASTRUCTURE mode need to indicate connectivity immediately; ADHOC mode */
- /* should wait until at least 2 active nodes in this BSSID. */
- OPSTATUS_SET_FLAG(pAd, fOP_STATUS_MEDIA_STATE_CONNECTED);
-
- /* For GUI ++ */
- if (pAd->StaCfg.AuthMode < Ndis802_11AuthModeWPA) {
- pAd->IndicateMediaState = NdisMediaStateConnected;
- pAd->ExtraInfo = GENERAL_LINK_UP;
- RTMP_IndicateMediaState(pAd);
- } else if ((pAd->StaCfg.AuthMode == Ndis802_11AuthModeWPAPSK) ||
- (pAd->StaCfg.AuthMode == Ndis802_11AuthModeWPA2PSK))
- {
- if (pAd->StaCfg.WpaSupplicantUP ==
- WPA_SUPPLICANT_DISABLE)
- RTMPSetTimer(&pAd->Mlme.LinkDownTimer,
- LINK_DOWN_TIMEOUT);
- }
- /* -- */
-
- /* Add BSSID in my MAC Table. */
- NdisAcquireSpinLock(&pAd->MacTabLock);
- /* add this MAC entry into HASH table */
- if (pEntry) {
- HashIdx = MAC_ADDR_HASH_INDEX(pAd->CommonCfg.Bssid);
- if (pAd->MacTab.Hash[HashIdx] == NULL) {
- pAd->MacTab.Hash[HashIdx] = pEntry;
- } else {
- pCurrEntry = pAd->MacTab.Hash[HashIdx];
- while (pCurrEntry->pNext != NULL) {
- pCurrEntry = pCurrEntry->pNext;
- }
- pCurrEntry->pNext = pEntry;
- }
- }
- RTMPMoveMemory(pEntry->Addr, pAd->CommonCfg.Bssid,
- MAC_ADDR_LEN);
- pEntry->Aid = BSSID_WCID;
- pEntry->pAd = pAd;
- pEntry->ValidAsCLI = TRUE; /*Although this is bssid..still set ValidAsCl */
- pAd->MacTab.Size = 1; /* infra mode always set MACtab size =1. */
- pEntry->Sst = SST_ASSOC;
- pEntry->AuthState = SST_ASSOC;
- pEntry->AuthMode = pAd->StaCfg.AuthMode;
- pEntry->WepStatus = pAd->StaCfg.WepStatus;
- if (pEntry->AuthMode < Ndis802_11AuthModeWPA) {
- pEntry->WpaState = AS_NOTUSE;
- pEntry->PrivacyFilter = Ndis802_11PrivFilterAcceptAll;
- } else {
- pEntry->WpaState = AS_PTKSTART;
- pEntry->PrivacyFilter = Ndis802_11PrivFilter8021xWEP;
- }
- NdisReleaseSpinLock(&pAd->MacTabLock);
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("LINK UP! ClientStatusFlags=%lx)\n",
- pAd->MacTab.Content[BSSID_WCID].ClientStatusFlags));
-
- MlmeUpdateTxRates(pAd, TRUE, BSS0);
- MlmeUpdateHtTxRates(pAd, BSS0);
- DBGPRINT(RT_DEBUG_TRACE,
- ("LINK UP! (StaActive.bHtEnable =%d, )\n",
- pAd->StaActive.SupportedPhyInfo.bHtEnable));
-
- if (pAd->CommonCfg.bAggregationCapable) {
- if ((pAd->CommonCfg.bPiggyBackCapable)
- && (pAd->MlmeAux.APRalinkIe & 0x00000003) == 3) {
- OPSTATUS_SET_FLAG(pAd,
- fOP_STATUS_PIGGYBACK_INUSED);
- OPSTATUS_SET_FLAG(pAd,
- fOP_STATUS_AGGREGATION_INUSED);
- CLIENT_STATUS_SET_FLAG(pEntry,
- fCLIENT_STATUS_AGGREGATION_CAPABLE);
- CLIENT_STATUS_SET_FLAG(pEntry,
- fCLIENT_STATUS_PIGGYBACK_CAPABLE);
- RTMPSetPiggyBack(pAd, TRUE);
- DBGPRINT(RT_DEBUG_TRACE,
- ("Turn on Piggy-Back\n"));
- } else if (pAd->MlmeAux.APRalinkIe & 0x00000001) {
- OPSTATUS_SET_FLAG(pAd,
- fOP_STATUS_AGGREGATION_INUSED);
- CLIENT_STATUS_SET_FLAG(pEntry,
- fCLIENT_STATUS_AGGREGATION_CAPABLE);
- DBGPRINT(RT_DEBUG_TRACE,
- ("Ralink Aggregation\n"));
- }
- }
-
- if (pAd->MlmeAux.APRalinkIe != 0x0) {
- if (CLIENT_STATUS_TEST_FLAG
- (pEntry, fCLIENT_STATUS_RDG_CAPABLE)) {
- AsicEnableRDG(pAd);
- }
- OPSTATUS_SET_FLAG(pAd, fCLIENT_STATUS_RALINK_CHIPSET);
- CLIENT_STATUS_SET_FLAG(pEntry,
- fCLIENT_STATUS_RALINK_CHIPSET);
- } else {
- OPSTATUS_CLEAR_FLAG(pAd, fCLIENT_STATUS_RALINK_CHIPSET);
- CLIENT_STATUS_CLEAR_FLAG(pEntry,
- fCLIENT_STATUS_RALINK_CHIPSET);
- }
- }
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("NDIS_STATUS_MEDIA_CONNECT Event B!.BACapability = %x. ClientStatusFlags = %lx\n",
- pAd->CommonCfg.BACapability.word,
- pAd->MacTab.Content[BSSID_WCID].ClientStatusFlags));
-
- /* Set LED */
- RTMPSetLED(pAd, LED_LINK_UP);
-
- pAd->Mlme.PeriodicRound = 0;
- pAd->Mlme.OneSecPeriodicRound = 0;
- pAd->bConfigChanged = FALSE; /* Reset config flag */
- pAd->ExtraInfo = GENERAL_LINK_UP; /* Update extra information after link is up */
-
- /* Set basic auto fall back */
- {
- u8 *pTable;
- u8 TableSize = 0;
-
- MlmeSelectTxRateTable(pAd, &pAd->MacTab.Content[BSSID_WCID],
- &pTable, &TableSize,
- &pAd->CommonCfg.TxRateIndex);
- AsicUpdateAutoFallBackTable(pAd, pTable);
- }
-
- NdisAcquireSpinLock(&pAd->MacTabLock);
- pEntry->HTPhyMode.word = pAd->StaCfg.HTPhyMode.word;
- pEntry->MaxHTPhyMode.word = pAd->StaCfg.HTPhyMode.word;
- if (pAd->StaCfg.bAutoTxRateSwitch == FALSE) {
- pEntry->bAutoTxRateSwitch = FALSE;
-
- if (pEntry->HTPhyMode.field.MCS == 32)
- pEntry->HTPhyMode.field.ShortGI = GI_800;
-
- if ((pEntry->HTPhyMode.field.MCS > MCS_7)
- || (pEntry->HTPhyMode.field.MCS == 32))
- pEntry->HTPhyMode.field.STBC = STBC_NONE;
-
- /* If the legacy mode is set, overwrite the transmit setting of this entry. */
- if (pEntry->HTPhyMode.field.MODE <= MODE_OFDM)
- RTMPUpdateLegacyTxSetting((u8)pAd->StaCfg.
- DesiredTransmitSetting.field.
- FixedTxMode, pEntry);
- } else
- pEntry->bAutoTxRateSwitch = TRUE;
- NdisReleaseSpinLock(&pAd->MacTabLock);
-
- /* Let Link Status Page display first initial rate. */
- pAd->LastTxRate = (u16)(pEntry->HTPhyMode.word);
- /* Select DAC according to HT or Legacy */
- if (pAd->StaActive.SupportedPhyInfo.MCSSet[0] != 0x00) {
- RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R1, &Value);
- Value &= (~0x18);
- if (pAd->Antenna.field.TxPath == 2) {
- Value |= 0x10;
- }
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R1, Value);
- } else {
- RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R1, &Value);
- Value &= (~0x18);
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R1, Value);
- }
-
- if (pAd->StaActive.SupportedPhyInfo.bHtEnable == FALSE) {
- } else if (pEntry->MaxRAmpduFactor == 0) {
- /* If HT AP doesn't support MaxRAmpduFactor = 1, we need to set max PSDU to 0. */
- /* Because our Init value is 1 at MACRegTable. */
- RTMP_IO_WRITE32(pAd, MAX_LEN_CFG, 0x0fff);
- }
- /* Patch for Marvel AP to gain high throughput */
- /* Need to set as following, */
- /* 1. Set txop in register-EDCA_AC0_CFG as 0x60 */
- /* 2. Set EnTXWriteBackDDONE in register-WPDMA_GLO_CFG as zero */
- /* 3. PBF_MAX_PCNT as 0x1F3FBF9F */
- /* 4. kick per two packets when dequeue */
- /* */
- /* Txop can only be modified when RDG is off, WMM is disable and TxBurst is enable */
- /* */
- /* if 1. Legacy AP WMM on, or 2. 11n AP, AMPDU disable. Force turn off burst no matter what bEnableTxBurst is. */
- if (!((pAd->CommonCfg.RxStream == 1) && (pAd->CommonCfg.TxStream == 1))
- && (pAd->StaCfg.bForceTxBurst == FALSE)
- &&
- (((pAd->StaActive.SupportedPhyInfo.bHtEnable == FALSE)
- && OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_WMM_INUSED))
- || ((pAd->StaActive.SupportedPhyInfo.bHtEnable == TRUE)
- && (pAd->CommonCfg.BACapability.field.Policy == BA_NOTUSE)))) {
- RTMP_IO_READ32(pAd, EDCA_AC0_CFG, &Data);
- Data &= 0xFFFFFF00;
- RTMP_IO_WRITE32(pAd, EDCA_AC0_CFG, Data);
-
- RTMP_IO_WRITE32(pAd, PBF_MAX_PCNT, 0x1F3F7F9F);
- DBGPRINT(RT_DEBUG_TRACE, ("Txburst 1\n"));
- } else if (pAd->CommonCfg.bEnableTxBurst) {
- RTMP_IO_READ32(pAd, EDCA_AC0_CFG, &Data);
- Data &= 0xFFFFFF00;
- Data |= 0x60;
- RTMP_IO_WRITE32(pAd, EDCA_AC0_CFG, Data);
- pAd->CommonCfg.IOTestParm.bNowAtherosBurstOn = TRUE;
-
- RTMP_IO_WRITE32(pAd, PBF_MAX_PCNT, 0x1F3FBF9F);
- DBGPRINT(RT_DEBUG_TRACE, ("Txburst 2\n"));
- } else {
- RTMP_IO_READ32(pAd, EDCA_AC0_CFG, &Data);
- Data &= 0xFFFFFF00;
- RTMP_IO_WRITE32(pAd, EDCA_AC0_CFG, Data);
-
- RTMP_IO_WRITE32(pAd, PBF_MAX_PCNT, 0x1F3F7F9F);
- DBGPRINT(RT_DEBUG_TRACE, ("Txburst 3\n"));
- }
-
- /* Re-check to turn on TX burst or not. */
- if ((pAd->CommonCfg.IOTestParm.bLastAtheros == TRUE)
- && ((STA_WEP_ON(pAd)) || (STA_TKIP_ON(pAd)))) {
- pAd->CommonCfg.IOTestParm.bNextDisableRxBA = TRUE;
- if (pAd->CommonCfg.bEnableTxBurst) {
- u32 MACValue = 0;
- /* Force disable TXOP value in this case. The same action in MLMEUpdateProtect too. */
- /* I didn't change PBF_MAX_PCNT setting. */
- RTMP_IO_READ32(pAd, EDCA_AC0_CFG, &MACValue);
- MACValue &= 0xFFFFFF00;
- RTMP_IO_WRITE32(pAd, EDCA_AC0_CFG, MACValue);
- pAd->CommonCfg.IOTestParm.bNowAtherosBurstOn = FALSE;
- }
- } else {
- pAd->CommonCfg.IOTestParm.bNextDisableRxBA = FALSE;
- }
-
- pAd->CommonCfg.IOTestParm.bLastAtheros = FALSE;
- COPY_MAC_ADDR(pAd->CommonCfg.LastBssid, pAd->CommonCfg.Bssid);
- DBGPRINT(RT_DEBUG_TRACE,
- ("pAd->bNextDisableRxBA= %d \n",
- pAd->CommonCfg.IOTestParm.bNextDisableRxBA));
- /* BSSID add in one MAC entry too. Because in Tx, ASIC need to check Cipher and IV/EIV, BAbitmap */
- /* Pther information in MACTab.Content[BSSID_WCID] is not necessary for driver. */
- /* Note: As STA, The MACTab.Content[BSSID_WCID]. PairwiseKey and Shared Key for BSS0 are the same. */
-
- if (pAd->StaCfg.WepStatus <= Ndis802_11WEPDisabled) {
- if (pAd->StaCfg.WpaSupplicantUP &&
- (pAd->StaCfg.WepStatus == Ndis802_11WEPEnabled) &&
- (pAd->StaCfg.IEEE8021X == TRUE)) ;
- else {
- pAd->StaCfg.PortSecured = WPA_802_1X_PORT_SECURED;
- pAd->StaCfg.PrivacyFilter =
- Ndis802_11PrivFilterAcceptAll;
- }
- }
-
- NdisAcquireSpinLock(&pAd->MacTabLock);
- pEntry->PortSecured = pAd->StaCfg.PortSecured;
- NdisReleaseSpinLock(&pAd->MacTabLock);
-
- /* */
- /* Patch Atheros AP TX will breakdown issue. */
- /* AP Model: DLink DWL-8200AP */
- /* */
- if (INFRA_ON(pAd) && OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_WMM_INUSED)
- && STA_TKIP_ON(pAd)) {
- RTMP_IO_WRITE32(pAd, RX_PARSER_CFG, 0x01);
- } else {
- RTMP_IO_WRITE32(pAd, RX_PARSER_CFG, 0x00);
- }
-
- RTMP_CLEAR_FLAG(pAd, fRTMP_ADAPTER_BSS_SCAN_IN_PROGRESS);
-
- RTMP_CLEAR_PSFLAG(pAd, fRTMP_PS_GO_TO_SLEEP_NOW);
-}
-
-/*
- ==========================================================================
-
- Routine Description:
- Disconnect current BSSID
-
- Arguments:
- pAd - Pointer to our adapter
- IsReqFromAP - Request from AP
-
- Return Value:
- None
-
- IRQL = DISPATCH_LEVEL
-
- Note:
- We need more information to know it's this requst from AP.
- If yes! we need to do extra handling, for example, remove the WPA key.
- Otherwise on 4-way handshaking will fail, since the WPA key didn't get
- removed while auto reconnect.
- Disconnect request from AP, it means we will start afresh 4-way handshaking
- on WPA mode.
-
- ==========================================================================
-*/
-void LinkDown(struct rt_rtmp_adapter *pAd, IN BOOLEAN IsReqFromAP)
-{
- u8 i, ByteValue = 0;
-
- /* Do nothing if monitor mode is on */
- if (MONITOR_ON(pAd))
- return;
-
- RTMP_CLEAR_PSFLAG(pAd, fRTMP_PS_GO_TO_SLEEP_NOW);
- /* Comment the codes, because the line 2291 call the same function. */
- /* RTMPCancelTimer(&pAd->Mlme.PsPollTimer, &Cancelled); */
- /* Not allowed go to sleep within the linkdown function. */
- RTMP_CLEAR_PSFLAG(pAd, fRTMP_PS_CAN_GO_SLEEP);
-
- if (pAd->CommonCfg.bWirelessEvent) {
- RTMPSendWirelessEvent(pAd, IW_STA_LINKDOWN_EVENT_FLAG,
- pAd->MacTab.Content[BSSID_WCID].Addr,
- BSS0, 0);
- }
-
- DBGPRINT(RT_DEBUG_TRACE, ("LINK DOWN!\n"));
- OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_AGGREGATION_INUSED);
-
-#ifdef RTMP_MAC_PCI
- if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_PCIE_DEVICE)) {
- BOOLEAN Cancelled;
- pAd->Mlme.bPsPollTimerRunning = FALSE;
- RTMPCancelTimer(&pAd->Mlme.PsPollTimer, &Cancelled);
- }
-
- pAd->bPCIclkOff = FALSE;
-#endif /* RTMP_MAC_PCI // */
-
- if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_DOZE)
- || RTMP_TEST_PSFLAG(pAd, fRTMP_PS_SET_PCI_CLK_OFF_COMMAND)
- || RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_IDLE_RADIO_OFF)) {
- AUTO_WAKEUP_STRUC AutoWakeupCfg;
- AsicForceWakeup(pAd, TRUE);
- AutoWakeupCfg.word = 0;
- RTMP_IO_WRITE32(pAd, AUTO_WAKEUP_CFG, AutoWakeupCfg.word);
- OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_DOZE);
- }
-#ifdef RTMP_MAC_PCI
- pAd->bPCIclkOff = FALSE;
-#endif /* RTMP_MAC_PCI // */
-
- if (ADHOC_ON(pAd)) /* Adhoc mode link down */
- {
- DBGPRINT(RT_DEBUG_TRACE, ("LINK DOWN 1!\n"));
-
- OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_ADHOC_ON);
- OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_MEDIA_STATE_CONNECTED);
- pAd->IndicateMediaState = NdisMediaStateDisconnected;
- RTMP_IndicateMediaState(pAd);
- pAd->ExtraInfo = GENERAL_LINK_DOWN;
- BssTableDeleteEntry(&pAd->ScanTab, pAd->CommonCfg.Bssid,
- pAd->CommonCfg.Channel);
- DBGPRINT(RT_DEBUG_TRACE,
- (" MacTab.Size=%d !\n", pAd->MacTab.Size));
- } else /* Infra structure mode */
- {
- DBGPRINT(RT_DEBUG_TRACE, ("LINK DOWN 2!\n"));
-
- OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_INFRA_ON);
- OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_MEDIA_STATE_CONNECTED);
-
- /* Saved last SSID for linkup comparison */
- pAd->CommonCfg.LastSsidLen = pAd->CommonCfg.SsidLen;
- NdisMoveMemory(pAd->CommonCfg.LastSsid, pAd->CommonCfg.Ssid,
- pAd->CommonCfg.LastSsidLen);
- COPY_MAC_ADDR(pAd->CommonCfg.LastBssid, pAd->CommonCfg.Bssid);
- if (pAd->MlmeAux.CurrReqIsFromNdis == TRUE) {
- pAd->IndicateMediaState = NdisMediaStateDisconnected;
- RTMP_IndicateMediaState(pAd);
- pAd->ExtraInfo = GENERAL_LINK_DOWN;
- DBGPRINT(RT_DEBUG_TRACE,
- ("NDIS_STATUS_MEDIA_DISCONNECT Event A!\n"));
- pAd->MlmeAux.CurrReqIsFromNdis = FALSE;
- } else {
- /* */
- /* If disassociation request is from NDIS, then we don't need to delete BSSID from entry. */
- /* Otherwise lost beacon or receive De-Authentication from AP, */
- /* then we should delete BSSID from BssTable. */
- /* If we don't delete from entry, roaming will fail. */
- /* */
- BssTableDeleteEntry(&pAd->ScanTab, pAd->CommonCfg.Bssid,
- pAd->CommonCfg.Channel);
- }
-
- /* restore back to - */
- /* 1. long slot (20 us) or short slot (9 us) time */
- /* 2. turn on/off RTS/CTS and/or CTS-to-self protection */
- /* 3. short preamble */
- OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_BG_PROTECTION_INUSED);
-
- }
-
- for (i = 1; i < MAX_LEN_OF_MAC_TABLE; i++) {
- if (pAd->MacTab.Content[i].ValidAsCLI == TRUE)
- MacTableDeleteEntry(pAd, pAd->MacTab.Content[i].Aid,
- pAd->MacTab.Content[i].Addr);
- }
-
- AsicSetSlotTime(pAd, TRUE); /*FALSE); */
- AsicSetEdcaParm(pAd, NULL);
-
- /* Set LED */
- RTMPSetLED(pAd, LED_LINK_DOWN);
- pAd->LedIndicatorStrength = 0xF0;
- RTMPSetSignalLED(pAd, -100); /* Force signal strength Led to be turned off, firmware has not done it. */
-
- AsicDisableSync(pAd);
-
- pAd->Mlme.PeriodicRound = 0;
- pAd->Mlme.OneSecPeriodicRound = 0;
-
- if (pAd->StaCfg.BssType == BSS_INFRA) {
- /* Remove StaCfg Information after link down */
- NdisZeroMemory(pAd->CommonCfg.Bssid, MAC_ADDR_LEN);
- NdisZeroMemory(pAd->CommonCfg.Ssid, MAX_LEN_OF_SSID);
- pAd->CommonCfg.SsidLen = 0;
- }
-
- NdisZeroMemory(&pAd->MlmeAux.HtCapability, sizeof(struct rt_ht_capability_ie));
- NdisZeroMemory(&pAd->MlmeAux.AddHtInfo, sizeof(struct rt_add_ht_info_ie));
- pAd->MlmeAux.HtCapabilityLen = 0;
- pAd->MlmeAux.NewExtChannelOffset = 0xff;
-
- /* Reset WPA-PSK state. Only reset when supplicant enabled */
- if (pAd->StaCfg.WpaState != SS_NOTUSE) {
- pAd->StaCfg.WpaState = SS_START;
- /* Clear Replay counter */
- NdisZeroMemory(pAd->StaCfg.ReplayCounter, 8);
-
- }
- /* */
- /* if link down come from AP, we need to remove all WPA keys on WPA mode. */
- /* otherwise will cause 4-way handshaking failed, since the WPA key not empty. */
- /* */
- if ((IsReqFromAP) && (pAd->StaCfg.AuthMode >= Ndis802_11AuthModeWPA)) {
- /* Remove all WPA keys */
- RTMPWPARemoveAllKeys(pAd);
- }
- /* 802.1x port control */
-
- /* Prevent clear PortSecured here with static WEP */
- /* NetworkManger set security policy first then set SSID to connect AP. */
- if (pAd->StaCfg.WpaSupplicantUP &&
- (pAd->StaCfg.WepStatus == Ndis802_11WEPEnabled) &&
- (pAd->StaCfg.IEEE8021X == FALSE)) {
- pAd->StaCfg.PortSecured = WPA_802_1X_PORT_SECURED;
- } else {
- pAd->StaCfg.PortSecured = WPA_802_1X_PORT_NOT_SECURED;
- pAd->StaCfg.PrivacyFilter = Ndis802_11PrivFilter8021xWEP;
- }
-
- NdisAcquireSpinLock(&pAd->MacTabLock);
- NdisZeroMemory(&pAd->MacTab, sizeof(struct rt_mac_table));
- pAd->MacTab.Content[BSSID_WCID].PortSecured = pAd->StaCfg.PortSecured;
- NdisReleaseSpinLock(&pAd->MacTabLock);
-
- pAd->StaCfg.MicErrCnt = 0;
-
- pAd->IndicateMediaState = NdisMediaStateDisconnected;
- /* Update extra information to link is up */
- pAd->ExtraInfo = GENERAL_LINK_DOWN;
-
- pAd->StaActive.SupportedPhyInfo.bHtEnable = FALSE;
-
-#ifdef RTMP_MAC_USB
- pAd->bUsbTxBulkAggre = FALSE;
-#endif /* RTMP_MAC_USB // */
-
- /* Clean association information */
- NdisZeroMemory(&pAd->StaCfg.AssocInfo,
- sizeof(struct rt_ndis_802_11_association_information));
- pAd->StaCfg.AssocInfo.Length =
- sizeof(struct rt_ndis_802_11_association_information);
- pAd->StaCfg.ReqVarIELen = 0;
- pAd->StaCfg.ResVarIELen = 0;
-
- /* */
- /* Reset RSSI value after link down */
- /* */
- pAd->StaCfg.RssiSample.AvgRssi0 = 0;
- pAd->StaCfg.RssiSample.AvgRssi0X8 = 0;
- pAd->StaCfg.RssiSample.AvgRssi1 = 0;
- pAd->StaCfg.RssiSample.AvgRssi1X8 = 0;
- pAd->StaCfg.RssiSample.AvgRssi2 = 0;
- pAd->StaCfg.RssiSample.AvgRssi2X8 = 0;
-
- /* Restore MlmeRate */
- pAd->CommonCfg.MlmeRate = pAd->CommonCfg.BasicMlmeRate;
- pAd->CommonCfg.RtsRate = pAd->CommonCfg.BasicMlmeRate;
-
- /* */
- /* After Link down, reset piggy-back setting in ASIC. Disable RDG. */
- /* */
- if (pAd->CommonCfg.BBPCurrentBW == BW_40) {
- pAd->CommonCfg.BBPCurrentBW = BW_20;
- RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &ByteValue);
- ByteValue &= (~0x18);
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, ByteValue);
- }
- /* Reset DAC */
- RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R1, &ByteValue);
- ByteValue &= (~0x18);
- if (pAd->Antenna.field.TxPath == 2) {
- ByteValue |= 0x10;
- }
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R1, ByteValue);
-
- RTMPSetPiggyBack(pAd, FALSE);
- OPSTATUS_CLEAR_FLAG(pAd, fOP_STATUS_PIGGYBACK_INUSED);
-
- pAd->CommonCfg.BACapability.word = pAd->CommonCfg.REGBACapability.word;
-
- /* Restore all settings in the following. */
- AsicUpdateProtect(pAd, 0,
- (ALLN_SETPROTECT | CCKSETPROTECT | OFDMSETPROTECT),
- TRUE, FALSE);
- AsicDisableRDG(pAd);
- pAd->CommonCfg.IOTestParm.bCurrentAtheros = FALSE;
- pAd->CommonCfg.IOTestParm.bNowAtherosBurstOn = FALSE;
-
- RTMP_IO_WRITE32(pAd, MAX_LEN_CFG, 0x1fff);
- RTMP_CLEAR_FLAG(pAd, fRTMP_ADAPTER_BSS_SCAN_IN_PROGRESS);
-
-/* Allow go to sleep after linkdown steps. */
- RTMP_SET_PSFLAG(pAd, fRTMP_PS_CAN_GO_SLEEP);
-
- RtmpOSWrielessEventSend(pAd, SIOCGIWAP, -1, NULL, NULL, 0);
-
-#ifdef RT30xx
- if ((IS_RT30xx(pAd) || IS_RT3090(pAd) || IS_RT3390(pAd))
- && (pAd->Antenna.field.RxPath > 1 || pAd->Antenna.field.TxPath > 1)) {
- RTMP_ASIC_MMPS_DISABLE(pAd);
- }
-#endif /* RT30xx // */
-}
-
-/*
- ==========================================================================
- Description:
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
-*/
-void IterateOnBssTab(struct rt_rtmp_adapter *pAd)
-{
- struct rt_mlme_start_req StartReq;
- struct rt_mlme_join_req JoinReq;
- unsigned long BssIdx;
-
- /* Change the wepstatus to original wepstatus */
- pAd->StaCfg.WepStatus = pAd->StaCfg.OrigWepStatus;
- pAd->StaCfg.PairCipher = pAd->StaCfg.OrigWepStatus;
- pAd->StaCfg.GroupCipher = pAd->StaCfg.OrigWepStatus;
-
- BssIdx = pAd->MlmeAux.BssIdx;
- if (BssIdx < pAd->MlmeAux.SsidBssTab.BssNr) {
- /* Check cipher suite, AP must have more secured cipher than station setting */
- /* Set the Pairwise and Group cipher to match the intended AP setting */
- /* We can only connect to AP with less secured cipher setting */
- if ((pAd->StaCfg.AuthMode == Ndis802_11AuthModeWPA)
- || (pAd->StaCfg.AuthMode == Ndis802_11AuthModeWPAPSK)) {
- pAd->StaCfg.GroupCipher =
- pAd->MlmeAux.SsidBssTab.BssEntry[BssIdx].WPA.
- GroupCipher;
-
- if (pAd->StaCfg.WepStatus ==
- pAd->MlmeAux.SsidBssTab.BssEntry[BssIdx].WPA.
- PairCipher)
- pAd->StaCfg.PairCipher =
- pAd->MlmeAux.SsidBssTab.BssEntry[BssIdx].
- WPA.PairCipher;
- else if (pAd->MlmeAux.SsidBssTab.BssEntry[BssIdx].WPA.
- PairCipherAux != Ndis802_11WEPDisabled)
- pAd->StaCfg.PairCipher =
- pAd->MlmeAux.SsidBssTab.BssEntry[BssIdx].
- WPA.PairCipherAux;
- else /* There is no PairCipher Aux, downgrade our capability to TKIP */
- pAd->StaCfg.PairCipher =
- Ndis802_11Encryption2Enabled;
- } else if ((pAd->StaCfg.AuthMode == Ndis802_11AuthModeWPA2)
- || (pAd->StaCfg.AuthMode ==
- Ndis802_11AuthModeWPA2PSK)) {
- pAd->StaCfg.GroupCipher =
- pAd->MlmeAux.SsidBssTab.BssEntry[BssIdx].WPA2.
- GroupCipher;
-
- if (pAd->StaCfg.WepStatus ==
- pAd->MlmeAux.SsidBssTab.BssEntry[BssIdx].WPA2.
- PairCipher)
- pAd->StaCfg.PairCipher =
- pAd->MlmeAux.SsidBssTab.BssEntry[BssIdx].
- WPA2.PairCipher;
- else if (pAd->MlmeAux.SsidBssTab.BssEntry[BssIdx].WPA2.
- PairCipherAux != Ndis802_11WEPDisabled)
- pAd->StaCfg.PairCipher =
- pAd->MlmeAux.SsidBssTab.BssEntry[BssIdx].
- WPA2.PairCipherAux;
- else /* There is no PairCipher Aux, downgrade our capability to TKIP */
- pAd->StaCfg.PairCipher =
- Ndis802_11Encryption2Enabled;
-
- /* RSN capability */
- pAd->StaCfg.RsnCapability =
- pAd->MlmeAux.SsidBssTab.BssEntry[BssIdx].WPA2.
- RsnCapability;
- }
- /* Set Mix cipher flag */
- pAd->StaCfg.bMixCipher =
- (pAd->StaCfg.PairCipher ==
- pAd->StaCfg.GroupCipher) ? FALSE : TRUE;
- /*if (pAd->StaCfg.bMixCipher == TRUE)
- {
- // If mix cipher, re-build RSNIE
- RTMPMakeRSNIE(pAd, pAd->StaCfg.AuthMode, pAd->StaCfg.WepStatus, 0);
- } */
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("CNTL - iterate BSS %ld of %d\n", BssIdx,
- pAd->MlmeAux.SsidBssTab.BssNr));
- JoinParmFill(pAd, &JoinReq, BssIdx);
- MlmeEnqueue(pAd, SYNC_STATE_MACHINE, MT2_MLME_JOIN_REQ,
- sizeof(struct rt_mlme_join_req), &JoinReq);
- pAd->Mlme.CntlMachine.CurrState = CNTL_WAIT_JOIN;
- } else if (pAd->StaCfg.BssType == BSS_ADHOC) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("CNTL - All BSS fail; start a new ADHOC (Ssid=%s)...\n",
- pAd->MlmeAux.Ssid));
- StartParmFill(pAd, &StartReq, (char *)pAd->MlmeAux.Ssid,
- pAd->MlmeAux.SsidLen);
- MlmeEnqueue(pAd, SYNC_STATE_MACHINE, MT2_MLME_START_REQ,
- sizeof(struct rt_mlme_start_req), &StartReq);
- pAd->Mlme.CntlMachine.CurrState = CNTL_WAIT_START;
- } else /* no more BSS */
- {
-
- {
- AsicSwitchChannel(pAd, pAd->CommonCfg.Channel, FALSE);
- AsicLockChannel(pAd, pAd->CommonCfg.Channel);
- DBGPRINT(RT_DEBUG_TRACE,
- ("CNTL - All roaming failed, restore to channel %d, Total BSS[%02d]\n",
- pAd->CommonCfg.Channel, pAd->ScanTab.BssNr));
- }
-
- pAd->Mlme.CntlMachine.CurrState = CNTL_IDLE;
- }
-}
-
-/* for re-association only */
-/* IRQL = DISPATCH_LEVEL */
-void IterateOnBssTab2(struct rt_rtmp_adapter *pAd)
-{
- struct rt_mlme_assoc_req ReassocReq;
- unsigned long BssIdx;
- struct rt_bss_entry *pBss;
-
- BssIdx = pAd->MlmeAux.RoamIdx;
- pBss = &pAd->MlmeAux.RoamTab.BssEntry[BssIdx];
-
- if (BssIdx < pAd->MlmeAux.RoamTab.BssNr) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("CNTL - iterate BSS %ld of %d\n", BssIdx,
- pAd->MlmeAux.RoamTab.BssNr));
-
- AsicSwitchChannel(pAd, pBss->Channel, FALSE);
- AsicLockChannel(pAd, pBss->Channel);
-
- /* reassociate message has the same structure as associate message */
- AssocParmFill(pAd, &ReassocReq, pBss->Bssid,
- pBss->CapabilityInfo, ASSOC_TIMEOUT,
- pAd->StaCfg.DefaultListenCount);
- MlmeEnqueue(pAd, ASSOC_STATE_MACHINE, MT2_MLME_REASSOC_REQ,
- sizeof(struct rt_mlme_assoc_req), &ReassocReq);
-
- pAd->Mlme.CntlMachine.CurrState = CNTL_WAIT_REASSOC;
- } else /* no more BSS */
- {
-
- {
- AsicSwitchChannel(pAd, pAd->CommonCfg.Channel, FALSE);
- AsicLockChannel(pAd, pAd->CommonCfg.Channel);
- DBGPRINT(RT_DEBUG_TRACE,
- ("CNTL - All roaming failed, restore to channel %d, Total BSS[%02d]\n",
- pAd->CommonCfg.Channel, pAd->ScanTab.BssNr));
- }
-
- pAd->Mlme.CntlMachine.CurrState = CNTL_IDLE;
- }
-}
-
-/*
- ==========================================================================
- Description:
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
-*/
-void JoinParmFill(struct rt_rtmp_adapter *pAd,
- struct rt_mlme_join_req *JoinReq, unsigned long BssIdx)
-{
- JoinReq->BssIdx = BssIdx;
-}
-
-/*
- ==========================================================================
- Description:
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
-*/
-void ScanParmFill(struct rt_rtmp_adapter *pAd,
- struct rt_mlme_scan_req *ScanReq,
- char Ssid[],
- u8 SsidLen, u8 BssType, u8 ScanType)
-{
- NdisZeroMemory(ScanReq->Ssid, MAX_LEN_OF_SSID);
- ScanReq->SsidLen = SsidLen;
- NdisMoveMemory(ScanReq->Ssid, Ssid, SsidLen);
- ScanReq->BssType = BssType;
- ScanReq->ScanType = ScanType;
-}
-
-/*
- ==========================================================================
- Description:
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
-*/
-void StartParmFill(struct rt_rtmp_adapter *pAd,
- struct rt_mlme_start_req *StartReq,
- char Ssid[], u8 SsidLen)
-{
- ASSERT(SsidLen <= MAX_LEN_OF_SSID);
- NdisMoveMemory(StartReq->Ssid, Ssid, SsidLen);
- StartReq->SsidLen = SsidLen;
-}
-
-/*
- ==========================================================================
- Description:
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
-*/
-void AuthParmFill(struct rt_rtmp_adapter *pAd,
- struct rt_mlme_auth_req *AuthReq,
- u8 *pAddr, u16 Alg)
-{
- COPY_MAC_ADDR(AuthReq->Addr, pAddr);
- AuthReq->Alg = Alg;
- AuthReq->Timeout = AUTH_TIMEOUT;
-}
-
-/*
- ==========================================================================
- Description:
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
- */
-#ifdef RTMP_MAC_PCI
-void ComposePsPoll(struct rt_rtmp_adapter *pAd)
-{
- NdisZeroMemory(&pAd->PsPollFrame, sizeof(struct rt_pspoll_frame));
- pAd->PsPollFrame.FC.Type = BTYPE_CNTL;
- pAd->PsPollFrame.FC.SubType = SUBTYPE_PS_POLL;
- pAd->PsPollFrame.Aid = pAd->StaActive.Aid | 0xC000;
- COPY_MAC_ADDR(pAd->PsPollFrame.Bssid, pAd->CommonCfg.Bssid);
- COPY_MAC_ADDR(pAd->PsPollFrame.Ta, pAd->CurrentAddress);
-}
-
-/* IRQL = DISPATCH_LEVEL */
-void ComposeNullFrame(struct rt_rtmp_adapter *pAd)
-{
- NdisZeroMemory(&pAd->NullFrame, sizeof(struct rt_header_802_11));
- pAd->NullFrame.FC.Type = BTYPE_DATA;
- pAd->NullFrame.FC.SubType = SUBTYPE_NULL_FUNC;
- pAd->NullFrame.FC.ToDs = 1;
- COPY_MAC_ADDR(pAd->NullFrame.Addr1, pAd->CommonCfg.Bssid);
- COPY_MAC_ADDR(pAd->NullFrame.Addr2, pAd->CurrentAddress);
- COPY_MAC_ADDR(pAd->NullFrame.Addr3, pAd->CommonCfg.Bssid);
-}
-#endif /* RTMP_MAC_PCI // */
-#ifdef RTMP_MAC_USB
-void MlmeCntlConfirm(struct rt_rtmp_adapter *pAd, unsigned long MsgType, u16 Msg)
-{
- MlmeEnqueue(pAd, MLME_CNTL_STATE_MACHINE, MsgType, sizeof(u16),
- &Msg);
-}
-
-void ComposePsPoll(struct rt_rtmp_adapter *pAd)
-{
- struct rt_txinfo *pTxInfo;
- struct rt_txwi * pTxWI;
-
- DBGPRINT(RT_DEBUG_TRACE, ("ComposePsPoll\n"));
- NdisZeroMemory(&pAd->PsPollFrame, sizeof(struct rt_pspoll_frame));
-
- pAd->PsPollFrame.FC.PwrMgmt = 0;
- pAd->PsPollFrame.FC.Type = BTYPE_CNTL;
- pAd->PsPollFrame.FC.SubType = SUBTYPE_PS_POLL;
- pAd->PsPollFrame.Aid = pAd->StaActive.Aid | 0xC000;
- COPY_MAC_ADDR(pAd->PsPollFrame.Bssid, pAd->CommonCfg.Bssid);
- COPY_MAC_ADDR(pAd->PsPollFrame.Ta, pAd->CurrentAddress);
-
- RTMPZeroMemory(&pAd->PsPollContext.TransferBuffer->field.
- WirelessPacket[0], 100);
- pTxInfo =
- (struct rt_txinfo *)& pAd->PsPollContext.TransferBuffer->field.
- WirelessPacket[0];
- RTMPWriteTxInfo(pAd, pTxInfo,
- (u16)(sizeof(struct rt_pspoll_frame) + TXWI_SIZE), TRUE,
- EpToQueue[MGMTPIPEIDX], FALSE, FALSE);
- pTxWI =
- (struct rt_txwi *) & pAd->PsPollContext.TransferBuffer->field.
- WirelessPacket[TXINFO_SIZE];
- RTMPWriteTxWI(pAd, pTxWI, FALSE, FALSE, FALSE, FALSE, TRUE, FALSE, 0,
- BSSID_WCID, (sizeof(struct rt_pspoll_frame)), 0, 0,
- (u8)pAd->CommonCfg.MlmeTransmit.field.MCS,
- IFS_BACKOFF, FALSE, &pAd->CommonCfg.MlmeTransmit);
- RTMPMoveMemory(&pAd->PsPollContext.TransferBuffer->field.
- WirelessPacket[TXWI_SIZE + TXINFO_SIZE],
- &pAd->PsPollFrame, sizeof(struct rt_pspoll_frame));
- /* Append 4 extra zero bytes. */
- pAd->PsPollContext.BulkOutSize =
- TXINFO_SIZE + TXWI_SIZE + sizeof(struct rt_pspoll_frame) + 4;
-}
-
-/* IRQL = DISPATCH_LEVEL */
-void ComposeNullFrame(struct rt_rtmp_adapter *pAd)
-{
- struct rt_txinfo *pTxInfo;
- struct rt_txwi * pTxWI;
-
- NdisZeroMemory(&pAd->NullFrame, sizeof(struct rt_header_802_11));
- pAd->NullFrame.FC.Type = BTYPE_DATA;
- pAd->NullFrame.FC.SubType = SUBTYPE_NULL_FUNC;
- pAd->NullFrame.FC.ToDs = 1;
- COPY_MAC_ADDR(pAd->NullFrame.Addr1, pAd->CommonCfg.Bssid);
- COPY_MAC_ADDR(pAd->NullFrame.Addr2, pAd->CurrentAddress);
- COPY_MAC_ADDR(pAd->NullFrame.Addr3, pAd->CommonCfg.Bssid);
- RTMPZeroMemory(&pAd->NullContext.TransferBuffer->field.
- WirelessPacket[0], 100);
- pTxInfo =
- (struct rt_txinfo *)& pAd->NullContext.TransferBuffer->field.
- WirelessPacket[0];
- RTMPWriteTxInfo(pAd, pTxInfo,
- (u16)(sizeof(struct rt_header_802_11) + TXWI_SIZE), TRUE,
- EpToQueue[MGMTPIPEIDX], FALSE, FALSE);
- pTxWI =
- (struct rt_txwi *) & pAd->NullContext.TransferBuffer->field.
- WirelessPacket[TXINFO_SIZE];
- RTMPWriteTxWI(pAd, pTxWI, FALSE, FALSE, FALSE, FALSE, TRUE, FALSE, 0,
- BSSID_WCID, (sizeof(struct rt_header_802_11)), 0, 0,
- (u8)pAd->CommonCfg.MlmeTransmit.field.MCS,
- IFS_BACKOFF, FALSE, &pAd->CommonCfg.MlmeTransmit);
- RTMPMoveMemory(&pAd->NullContext.TransferBuffer->field.
- WirelessPacket[TXWI_SIZE + TXINFO_SIZE], &pAd->NullFrame,
- sizeof(struct rt_header_802_11));
- pAd->NullContext.BulkOutSize =
- TXINFO_SIZE + TXWI_SIZE + sizeof(pAd->NullFrame) + 4;
-}
-#endif /* RTMP_MAC_USB // */
-
-/*
- ==========================================================================
- Description:
- Pre-build a BEACON frame in the shared memory
-
- IRQL = PASSIVE_LEVEL
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
-*/
-unsigned long MakeIbssBeacon(struct rt_rtmp_adapter *pAd)
-{
- u8 DsLen = 1, IbssLen = 2;
- u8 LocalErpIe[3] = { IE_ERP, 1, 0x04 };
- struct rt_header_802_11 BcnHdr;
- u16 CapabilityInfo;
- LARGE_INTEGER FakeTimestamp;
- unsigned long FrameLen = 0;
- struct rt_txwi * pTxWI = &pAd->BeaconTxWI;
- u8 *pBeaconFrame = pAd->BeaconBuf;
- BOOLEAN Privacy;
- u8 SupRate[MAX_LEN_OF_SUPPORTED_RATES];
- u8 SupRateLen = 0;
- u8 ExtRate[MAX_LEN_OF_SUPPORTED_RATES];
- u8 ExtRateLen = 0;
- u8 RSNIe = IE_WPA;
-
- if ((pAd->CommonCfg.PhyMode == PHY_11B)
- && (pAd->CommonCfg.Channel <= 14)) {
- SupRate[0] = 0x82; /* 1 mbps */
- SupRate[1] = 0x84; /* 2 mbps */
- SupRate[2] = 0x8b; /* 5.5 mbps */
- SupRate[3] = 0x96; /* 11 mbps */
- SupRateLen = 4;
- ExtRateLen = 0;
- } else if (pAd->CommonCfg.Channel > 14) {
- SupRate[0] = 0x8C; /* 6 mbps, in units of 0.5 Mbps, basic rate */
- SupRate[1] = 0x12; /* 9 mbps, in units of 0.5 Mbps */
- SupRate[2] = 0x98; /* 12 mbps, in units of 0.5 Mbps, basic rate */
- SupRate[3] = 0x24; /* 18 mbps, in units of 0.5 Mbps */
- SupRate[4] = 0xb0; /* 24 mbps, in units of 0.5 Mbps, basic rate */
- SupRate[5] = 0x48; /* 36 mbps, in units of 0.5 Mbps */
- SupRate[6] = 0x60; /* 48 mbps, in units of 0.5 Mbps */
- SupRate[7] = 0x6c; /* 54 mbps, in units of 0.5 Mbps */
- SupRateLen = 8;
- ExtRateLen = 0;
-
- /* */
- /* Also Update MlmeRate & RtsRate for G only & A only */
- /* */
- pAd->CommonCfg.MlmeRate = RATE_6;
- pAd->CommonCfg.RtsRate = RATE_6;
- pAd->CommonCfg.MlmeTransmit.field.MODE = MODE_OFDM;
- pAd->CommonCfg.MlmeTransmit.field.MCS =
- OfdmRateToRxwiMCS[pAd->CommonCfg.MlmeRate];
- pAd->MacTab.Content[BSS0Mcast_WCID].HTPhyMode.field.MODE =
- MODE_OFDM;
- pAd->MacTab.Content[BSS0Mcast_WCID].HTPhyMode.field.MCS =
- OfdmRateToRxwiMCS[pAd->CommonCfg.MlmeRate];
- } else {
- SupRate[0] = 0x82; /* 1 mbps */
- SupRate[1] = 0x84; /* 2 mbps */
- SupRate[2] = 0x8b; /* 5.5 mbps */
- SupRate[3] = 0x96; /* 11 mbps */
- SupRateLen = 4;
-
- ExtRate[0] = 0x0C; /* 6 mbps, in units of 0.5 Mbps, */
- ExtRate[1] = 0x12; /* 9 mbps, in units of 0.5 Mbps */
- ExtRate[2] = 0x18; /* 12 mbps, in units of 0.5 Mbps, */
- ExtRate[3] = 0x24; /* 18 mbps, in units of 0.5 Mbps */
- ExtRate[4] = 0x30; /* 24 mbps, in units of 0.5 Mbps, */
- ExtRate[5] = 0x48; /* 36 mbps, in units of 0.5 Mbps */
- ExtRate[6] = 0x60; /* 48 mbps, in units of 0.5 Mbps */
- ExtRate[7] = 0x6c; /* 54 mbps, in units of 0.5 Mbps */
- ExtRateLen = 8;
- }
-
- pAd->StaActive.SupRateLen = SupRateLen;
- NdisMoveMemory(pAd->StaActive.SupRate, SupRate, SupRateLen);
- pAd->StaActive.ExtRateLen = ExtRateLen;
- NdisMoveMemory(pAd->StaActive.ExtRate, ExtRate, ExtRateLen);
-
- /* compose IBSS beacon frame */
- MgtMacHeaderInit(pAd, &BcnHdr, SUBTYPE_BEACON, 0, BROADCAST_ADDR,
- pAd->CommonCfg.Bssid);
- Privacy = (pAd->StaCfg.WepStatus == Ndis802_11Encryption1Enabled)
- || (pAd->StaCfg.WepStatus == Ndis802_11Encryption2Enabled)
- || (pAd->StaCfg.WepStatus == Ndis802_11Encryption3Enabled);
- CapabilityInfo =
- CAP_GENERATE(0, 1, Privacy,
- (pAd->CommonCfg.TxPreamble == Rt802_11PreambleShort),
- 0, 0);
-
- MakeOutgoingFrame(pBeaconFrame, &FrameLen,
- sizeof(struct rt_header_802_11), &BcnHdr,
- TIMESTAMP_LEN, &FakeTimestamp,
- 2, &pAd->CommonCfg.BeaconPeriod,
- 2, &CapabilityInfo,
- 1, &SsidIe,
- 1, &pAd->CommonCfg.SsidLen,
- pAd->CommonCfg.SsidLen, pAd->CommonCfg.Ssid,
- 1, &SupRateIe,
- 1, &SupRateLen,
- SupRateLen, SupRate,
- 1, &DsIe,
- 1, &DsLen,
- 1, &pAd->CommonCfg.Channel,
- 1, &IbssIe,
- 1, &IbssLen, 2, &pAd->StaActive.AtimWin, END_OF_ARGS);
-
- /* add ERP_IE and EXT_RAE IE of in 802.11g */
- if (ExtRateLen) {
- unsigned long tmp;
-
- MakeOutgoingFrame(pBeaconFrame + FrameLen, &tmp,
- 3, LocalErpIe,
- 1, &ExtRateIe,
- 1, &ExtRateLen,
- ExtRateLen, ExtRate, END_OF_ARGS);
- FrameLen += tmp;
- }
- /* If adhoc secruity is set for WPA-None, append the cipher suite IE */
- if (pAd->StaCfg.AuthMode == Ndis802_11AuthModeWPANone) {
- unsigned long tmp;
- RTMPMakeRSNIE(pAd, pAd->StaCfg.AuthMode, pAd->StaCfg.WepStatus,
- BSS0);
-
- MakeOutgoingFrame(pBeaconFrame + FrameLen, &tmp,
- 1, &RSNIe,
- 1, &pAd->StaCfg.RSNIE_Len,
- pAd->StaCfg.RSNIE_Len, pAd->StaCfg.RSN_IE,
- END_OF_ARGS);
- FrameLen += tmp;
- }
-
- if ((pAd->CommonCfg.PhyMode >= PHY_11ABGN_MIXED)) {
- unsigned long TmpLen;
- u8 HtLen, HtLen1;
-
- /* add HT Capability IE */
- HtLen = sizeof(pAd->CommonCfg.HtCapability);
- HtLen1 = sizeof(pAd->CommonCfg.AddHTInfo);
-
- MakeOutgoingFrame(pBeaconFrame + FrameLen, &TmpLen,
- 1, &HtCapIe,
- 1, &HtLen,
- HtLen, &pAd->CommonCfg.HtCapability,
- 1, &AddHtInfoIe,
- 1, &HtLen1,
- HtLen1, &pAd->CommonCfg.AddHTInfo,
- END_OF_ARGS);
-
- FrameLen += TmpLen;
- }
- /*beacon use reserved WCID 0xff */
- if (pAd->CommonCfg.Channel > 14) {
- RTMPWriteTxWI(pAd, pTxWI, FALSE, FALSE, TRUE, FALSE, FALSE,
- TRUE, 0, 0xff, FrameLen, PID_MGMT, PID_BEACON,
- RATE_1, IFS_HTTXOP, FALSE,
- &pAd->CommonCfg.MlmeTransmit);
- } else {
- /* Set to use 1Mbps for Adhoc beacon. */
- HTTRANSMIT_SETTING Transmit;
- Transmit.word = 0;
- RTMPWriteTxWI(pAd, pTxWI, FALSE, FALSE, TRUE, FALSE, FALSE,
- TRUE, 0, 0xff, FrameLen, PID_MGMT, PID_BEACON,
- RATE_1, IFS_HTTXOP, FALSE, &Transmit);
- }
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("MakeIbssBeacon (len=%ld), SupRateLen=%d, ExtRateLen=%d, Channel=%d, PhyMode=%d\n",
- FrameLen, SupRateLen, ExtRateLen, pAd->CommonCfg.Channel,
- pAd->CommonCfg.PhyMode));
- return FrameLen;
-}
diff --git a/drivers/staging/rt2860/sta/rtmp_data.c b/drivers/staging/rt2860/sta/rtmp_data.c
deleted file mode 100644
index e82c6b6..0000000
--- a/drivers/staging/rt2860/sta/rtmp_data.c
+++ /dev/null
@@ -1,2552 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- rtmp_data.c
-
- Abstract:
- Data path subroutines
-
- Revision History:
- Who When What
- Justin P. Mattock 11/07/2010 Fix typos
- -------- ---------- ----------------------------------------------
-*/
-#include "../rt_config.h"
-#include <linux/kernel.h>
-
-void STARxEAPOLFrameIndicate(struct rt_rtmp_adapter *pAd,
- struct rt_mac_table_entry *pEntry,
- struct rt_rx_blk *pRxBlk, u8 FromWhichBSSID)
-{
- PRT28XX_RXD_STRUC pRxD = &(pRxBlk->RxD);
- struct rt_rxwi * pRxWI = pRxBlk->pRxWI;
- u8 *pTmpBuf;
-
- if (pAd->StaCfg.WpaSupplicantUP) {
- /* All EAPoL frames have to pass to upper layer (ex. WPA_SUPPLICANT daemon) */
- /* TBD : process fragmented EAPol frames */
- {
- /* In 802.1x mode, if the received frame is EAP-SUCCESS packet, turn on the PortSecured variable */
- if (pAd->StaCfg.IEEE8021X == TRUE &&
- (EAP_CODE_SUCCESS ==
- WpaCheckEapCode(pAd, pRxBlk->pData,
- pRxBlk->DataSize,
- LENGTH_802_1_H))) {
- u8 *Key;
- u8 CipherAlg;
- int idx = 0;
-
- DBGPRINT_RAW(RT_DEBUG_TRACE,
- ("Receive EAP-SUCCESS Packet\n"));
- /*pAd->StaCfg.PortSecured = WPA_802_1X_PORT_SECURED; */
- STA_PORT_SECURED(pAd);
-
- if (pAd->StaCfg.IEEE8021x_required_keys ==
- FALSE) {
- idx = pAd->StaCfg.DesireSharedKeyId;
- CipherAlg =
- pAd->StaCfg.DesireSharedKey[idx].
- CipherAlg;
- Key =
- pAd->StaCfg.DesireSharedKey[idx].
- Key;
-
- if (pAd->StaCfg.DesireSharedKey[idx].
- KeyLen > 0) {
-#ifdef RTMP_MAC_PCI
- struct rt_mac_table_entry *pEntry =
- &pAd->MacTab.
- Content[BSSID_WCID];
-
- /* Set key material and cipherAlg to Asic */
- AsicAddSharedKeyEntry(pAd, BSS0,
- idx,
- CipherAlg,
- Key, NULL,
- NULL);
-
- /* Assign group key info */
- RTMPAddWcidAttributeEntry(pAd,
- BSS0,
- idx,
- CipherAlg,
- NULL);
-
- /* Assign pairwise key info */
- RTMPAddWcidAttributeEntry(pAd,
- BSS0,
- idx,
- CipherAlg,
- pEntry);
-
- pAd->IndicateMediaState =
- NdisMediaStateConnected;
- pAd->ExtraInfo =
- GENERAL_LINK_UP;
-#endif /* RTMP_MAC_PCI // */
-#ifdef RTMP_MAC_USB
- union {
- char buf[sizeof
- (struct rt_ndis_802_11_wep)
- +
- MAX_LEN_OF_KEY
- - 1];
- struct rt_ndis_802_11_wep keyinfo;
- }
- WepKey;
- int len;
-
- NdisZeroMemory(&WepKey,
- sizeof(WepKey));
- len =
- pAd->StaCfg.
- DesireSharedKey[idx].KeyLen;
-
- NdisMoveMemory(WepKey.keyinfo.
- KeyMaterial,
- pAd->StaCfg.
- DesireSharedKey
- [idx].Key,
- pAd->StaCfg.
- DesireSharedKey
- [idx].KeyLen);
-
- WepKey.keyinfo.KeyIndex =
- 0x80000000 + idx;
- WepKey.keyinfo.KeyLength = len;
- pAd->SharedKey[BSS0][idx].
- KeyLen =
- (u8)(len <= 5 ? 5 : 13);
-
- pAd->IndicateMediaState =
- NdisMediaStateConnected;
- pAd->ExtraInfo =
- GENERAL_LINK_UP;
- /* need to enqueue cmd to thread */
- RTUSBEnqueueCmdFromNdis(pAd,
- OID_802_11_ADD_WEP,
- TRUE,
- &WepKey,
- sizeof
- (WepKey.
- keyinfo)
- + len -
- 1);
-#endif /* RTMP_MAC_USB // */
- /* For Preventing ShardKey Table is cleared by remove key procedure. */
- pAd->SharedKey[BSS0][idx].
- CipherAlg = CipherAlg;
- pAd->SharedKey[BSS0][idx].
- KeyLen =
- pAd->StaCfg.
- DesireSharedKey[idx].KeyLen;
- NdisMoveMemory(pAd->
- SharedKey[BSS0]
- [idx].Key,
- pAd->StaCfg.
- DesireSharedKey
- [idx].Key,
- pAd->StaCfg.
- DesireSharedKey
- [idx].KeyLen);
- }
- }
- }
-
- Indicate_Legacy_Packet(pAd, pRxBlk, FromWhichBSSID);
- return;
- }
- } else {
- /* Special DATA frame that has to pass to MLME */
- /* 1. Cisco Aironet frames for CCX2. We need pass it to MLME for special process */
- /* 2. EAPOL handshaking frames when driver supplicant enabled, pass to MLME for special process */
- {
- pTmpBuf = pRxBlk->pData - LENGTH_802_11;
- NdisMoveMemory(pTmpBuf, pRxBlk->pHeader, LENGTH_802_11);
- REPORT_MGMT_FRAME_TO_MLME(pAd, pRxWI->WirelessCliID,
- pTmpBuf,
- pRxBlk->DataSize +
- LENGTH_802_11, pRxWI->RSSI0,
- pRxWI->RSSI1, pRxWI->RSSI2,
- pRxD->PlcpSignal);
- DBGPRINT_RAW(RT_DEBUG_TRACE,
- ("report EAPOL/AIRONET DATA to MLME (len=%d) !\n",
- pRxBlk->DataSize));
- }
- }
-
- RELEASE_NDIS_PACKET(pAd, pRxBlk->pRxPacket, NDIS_STATUS_FAILURE);
- return;
-
-}
-
-void STARxDataFrameAnnounce(struct rt_rtmp_adapter *pAd,
- struct rt_mac_table_entry *pEntry,
- struct rt_rx_blk *pRxBlk, u8 FromWhichBSSID)
-{
-
- /* non-EAP frame */
- if (!RTMPCheckWPAframe
- (pAd, pEntry, pRxBlk->pData, pRxBlk->DataSize, FromWhichBSSID)) {
-
- {
- /* drop all non-EAP DATA frame before */
- /* this client's Port-Access-Control is secured */
- if (pRxBlk->pHeader->FC.Wep) {
- /* unsupported cipher suite */
- if (pAd->StaCfg.WepStatus ==
- Ndis802_11EncryptionDisabled) {
- /* release packet */
- RELEASE_NDIS_PACKET(pAd,
- pRxBlk->pRxPacket,
- NDIS_STATUS_FAILURE);
- return;
- }
- } else {
- /* encryption in-use but receive a non-EAPOL clear text frame, drop it */
- if ((pAd->StaCfg.WepStatus !=
- Ndis802_11EncryptionDisabled)
- && (pAd->StaCfg.PortSecured ==
- WPA_802_1X_PORT_NOT_SECURED)) {
- /* release packet */
- RELEASE_NDIS_PACKET(pAd,
- pRxBlk->pRxPacket,
- NDIS_STATUS_FAILURE);
- return;
- }
- }
- }
- RX_BLK_CLEAR_FLAG(pRxBlk, fRX_EAP);
- if (!RX_BLK_TEST_FLAG(pRxBlk, fRX_ARALINK)) {
- /* Normal legacy, AMPDU or AMSDU */
- CmmRxnonRalinkFrameIndicate(pAd, pRxBlk,
- FromWhichBSSID);
-
- } else {
- /* ARALINK */
- CmmRxRalinkFrameIndicate(pAd, pEntry, pRxBlk,
- FromWhichBSSID);
- }
- } else {
- RX_BLK_SET_FLAG(pRxBlk, fRX_EAP);
-
- if (RX_BLK_TEST_FLAG(pRxBlk, fRX_AMPDU)
- && (pAd->CommonCfg.bDisableReordering == 0)) {
- Indicate_AMPDU_Packet(pAd, pRxBlk, FromWhichBSSID);
- } else {
- /* Determine the destination of the EAP frame */
- /* to WPA state machine or upper layer */
- STARxEAPOLFrameIndicate(pAd, pEntry, pRxBlk,
- FromWhichBSSID);
- }
- }
-}
-
-/* For TKIP frame, calculate the MIC value */
-BOOLEAN STACheckTkipMICValue(struct rt_rtmp_adapter *pAd,
- struct rt_mac_table_entry *pEntry, struct rt_rx_blk *pRxBlk)
-{
- struct rt_header_802_11 * pHeader = pRxBlk->pHeader;
- u8 *pData = pRxBlk->pData;
- u16 DataSize = pRxBlk->DataSize;
- u8 UserPriority = pRxBlk->UserPriority;
- struct rt_cipher_key *pWpaKey;
- u8 *pDA, *pSA;
-
- pWpaKey = &pAd->SharedKey[BSS0][pRxBlk->pRxWI->KeyIndex];
-
- pDA = pHeader->Addr1;
- if (RX_BLK_TEST_FLAG(pRxBlk, fRX_INFRA)) {
- pSA = pHeader->Addr3;
- } else {
- pSA = pHeader->Addr2;
- }
-
- if (RTMPTkipCompareMICValue(pAd,
- pData,
- pDA,
- pSA,
- pWpaKey->RxMic,
- UserPriority, DataSize) == FALSE) {
- DBGPRINT_RAW(RT_DEBUG_ERROR, ("Rx MIC Value error 2\n"));
-
- if (pAd->StaCfg.WpaSupplicantUP) {
- WpaSendMicFailureToWpaSupplicant(pAd,
- (pWpaKey->Type ==
- PAIRWISEKEY) ? TRUE :
- FALSE);
- } else {
- RTMPReportMicError(pAd, pWpaKey);
- }
-
- /* release packet */
- RELEASE_NDIS_PACKET(pAd, pRxBlk->pRxPacket,
- NDIS_STATUS_FAILURE);
- return FALSE;
- }
-
- return TRUE;
-}
-
-/* */
-/* All Rx routines use struct rt_rx_blk structure to hande rx events */
-/* It is very important to build pRxBlk attributes */
-/* 1. pHeader pointer to 802.11 Header */
-/* 2. pData pointer to payload including LLC (just skip Header) */
-/* 3. set payload size including LLC to DataSize */
-/* 4. set some flags with RX_BLK_SET_FLAG() */
-/* */
-void STAHandleRxDataFrame(struct rt_rtmp_adapter *pAd, struct rt_rx_blk *pRxBlk)
-{
- PRT28XX_RXD_STRUC pRxD = &(pRxBlk->RxD);
- struct rt_rxwi * pRxWI = pRxBlk->pRxWI;
- struct rt_header_802_11 * pHeader = pRxBlk->pHeader;
- void *pRxPacket = pRxBlk->pRxPacket;
- BOOLEAN bFragment = FALSE;
- struct rt_mac_table_entry *pEntry = NULL;
- u8 FromWhichBSSID = BSS0;
- u8 UserPriority = 0;
-
- {
- /* before LINK UP, all DATA frames are rejected */
- if (!OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_MEDIA_STATE_CONNECTED)) {
- /* release packet */
- RELEASE_NDIS_PACKET(pAd, pRxPacket,
- NDIS_STATUS_FAILURE);
- return;
- }
- /* Drop not my BSS frames */
- if (pRxD->MyBss == 0) {
- {
- /* release packet */
- RELEASE_NDIS_PACKET(pAd, pRxPacket,
- NDIS_STATUS_FAILURE);
- return;
- }
- }
-
- pAd->RalinkCounters.RxCountSinceLastNULL++;
- if (pAd->CommonCfg.bAPSDCapable
- && pAd->CommonCfg.APEdcaParm.bAPSDCapable
- && (pHeader->FC.SubType & 0x08)) {
- u8 *pData;
- DBGPRINT(RT_DEBUG_INFO, ("bAPSDCapable\n"));
-
- /* Qos bit 4 */
- pData = (u8 *)pHeader + LENGTH_802_11;
- if ((*pData >> 4) & 0x01) {
- DBGPRINT(RT_DEBUG_INFO,
- ("RxDone- Rcv EOSP frame, driver may fall into sleep\n"));
- pAd->CommonCfg.bInServicePeriod = FALSE;
-
- /* Force driver to fall into sleep mode when rcv EOSP frame */
- if (!OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_DOZE)) {
- u16 TbttNumToNextWakeUp;
- u16 NextDtim =
- pAd->StaCfg.DtimPeriod;
- unsigned long Now;
-
- NdisGetSystemUpTime(&Now);
- NextDtim -=
- (u16)(Now -
- pAd->StaCfg.
- LastBeaconRxTime) /
- pAd->CommonCfg.BeaconPeriod;
-
- TbttNumToNextWakeUp =
- pAd->StaCfg.DefaultListenCount;
- if (OPSTATUS_TEST_FLAG
- (pAd, fOP_STATUS_RECEIVE_DTIM)
- && (TbttNumToNextWakeUp > NextDtim))
- TbttNumToNextWakeUp = NextDtim;
-
- RTMP_SET_PSM_BIT(pAd, PWR_SAVE);
- /* if WMM-APSD is failed, try to disable following line */
- AsicSleepThenAutoWakeup(pAd,
- TbttNumToNextWakeUp);
- }
- }
-
- if ((pHeader->FC.MoreData)
- && (pAd->CommonCfg.bInServicePeriod)) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("Sending another trigger frame when More Data bit is set to 1\n"));
- }
- }
- /* Drop NULL, CF-ACK(no data), CF-POLL(no data), and CF-ACK+CF-POLL(no data) data frame */
- if ((pHeader->FC.SubType & 0x04)) /* bit 2 : no DATA */
- {
- /* release packet */
- RELEASE_NDIS_PACKET(pAd, pRxPacket,
- NDIS_STATUS_FAILURE);
- return;
- }
- /* Drop not my BSS frame (we can not only check the MyBss bit in RxD) */
-
- if (INFRA_ON(pAd)) {
- /* Infrastructure mode, check address 2 for BSSID */
- if (!RTMPEqualMemory
- (&pHeader->Addr2, &pAd->CommonCfg.Bssid, 6)) {
- /* Receive frame not my BSSID */
- /* release packet */
- RELEASE_NDIS_PACKET(pAd, pRxPacket,
- NDIS_STATUS_FAILURE);
- return;
- }
- } else /* Ad-Hoc mode or Not associated */
- {
- /* Ad-Hoc mode, check address 3 for BSSID */
- if (!RTMPEqualMemory
- (&pHeader->Addr3, &pAd->CommonCfg.Bssid, 6)) {
- /* Receive frame not my BSSID */
- /* release packet */
- RELEASE_NDIS_PACKET(pAd, pRxPacket,
- NDIS_STATUS_FAILURE);
- return;
- }
- }
-
- /* */
- /* find pEntry */
- /* */
- if (pRxWI->WirelessCliID < MAX_LEN_OF_MAC_TABLE) {
- pEntry = &pAd->MacTab.Content[pRxWI->WirelessCliID];
- } else {
- /* 1. release packet if infra mode */
- /* 2. new a pEntry if ad-hoc mode */
- RELEASE_NDIS_PACKET(pAd, pRxPacket,
- NDIS_STATUS_FAILURE);
- return;
- }
-
- /* infra or ad-hoc */
- if (INFRA_ON(pAd)) {
- RX_BLK_SET_FLAG(pRxBlk, fRX_INFRA);
- ASSERT(pRxWI->WirelessCliID == BSSID_WCID);
- }
- /* check Atheros Client */
- if ((pEntry->bIAmBadAtheros == FALSE) && (pRxD->AMPDU == 1)
- && (pHeader->FC.Retry)) {
- pEntry->bIAmBadAtheros = TRUE;
- pAd->CommonCfg.IOTestParm.bCurrentAtheros = TRUE;
- pAd->CommonCfg.IOTestParm.bLastAtheros = TRUE;
- if (!STA_AES_ON(pAd)) {
- AsicUpdateProtect(pAd, 8, ALLN_SETPROTECT, TRUE,
- FALSE);
- }
- }
- }
-
- pRxBlk->pData = (u8 *) pHeader;
-
- /* */
- /* update RxBlk->pData, DataSize */
- /* 802.11 Header, QOS, HTC, Hw Padding */
- /* */
-
- /* 1. skip 802.11 HEADER */
- {
- pRxBlk->pData += LENGTH_802_11;
- pRxBlk->DataSize -= LENGTH_802_11;
- }
-
- /* 2. QOS */
- if (pHeader->FC.SubType & 0x08) {
- RX_BLK_SET_FLAG(pRxBlk, fRX_QOS);
- UserPriority = *(pRxBlk->pData) & 0x0f;
- /* bit 7 in QoS Control field signals the HT A-MSDU format */
- if ((*pRxBlk->pData) & 0x80) {
- RX_BLK_SET_FLAG(pRxBlk, fRX_AMSDU);
- }
- /* skip QOS contorl field */
- pRxBlk->pData += 2;
- pRxBlk->DataSize -= 2;
- }
- pRxBlk->UserPriority = UserPriority;
-
- /* check if need to resend PS Poll when received packet with MoreData = 1 */
- if ((pAd->StaCfg.Psm == PWR_SAVE) && (pHeader->FC.MoreData == 1)) {
- if ((((UserPriority == 0) || (UserPriority == 3)) &&
- pAd->CommonCfg.bAPSDAC_BE == 0) ||
- (((UserPriority == 1) || (UserPriority == 2)) &&
- pAd->CommonCfg.bAPSDAC_BK == 0) ||
- (((UserPriority == 4) || (UserPriority == 5)) &&
- pAd->CommonCfg.bAPSDAC_VI == 0) ||
- (((UserPriority == 6) || (UserPriority == 7)) &&
- pAd->CommonCfg.bAPSDAC_VO == 0)) {
- /* non-UAPSD delivery-enabled AC */
- RTMP_PS_POLL_ENQUEUE(pAd);
- }
- }
- /* 3. Order bit: A-Ralink or HTC+ */
- if (pHeader->FC.Order) {
-#ifdef AGGREGATION_SUPPORT
- if ((pRxWI->PHYMODE <= MODE_OFDM)
- && (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_AGGREGATION_INUSED)))
- {
- RX_BLK_SET_FLAG(pRxBlk, fRX_ARALINK);
- } else
-#endif /* AGGREGATION_SUPPORT // */
- {
- RX_BLK_SET_FLAG(pRxBlk, fRX_HTC);
- /* skip HTC contorl field */
- pRxBlk->pData += 4;
- pRxBlk->DataSize -= 4;
- }
- }
- /* 4. skip HW padding */
- if (pRxD->L2PAD) {
- /* just move pData pointer */
- /* because DataSize excluding HW padding */
- RX_BLK_SET_FLAG(pRxBlk, fRX_PAD);
- pRxBlk->pData += 2;
- }
-
- if (pRxD->BA) {
- RX_BLK_SET_FLAG(pRxBlk, fRX_AMPDU);
- }
- /* */
- /* Case I Process Broadcast & Multicast data frame */
- /* */
- if (pRxD->Bcast || pRxD->Mcast) {
- INC_COUNTER64(pAd->WlanCounters.MulticastReceivedFrameCount);
-
- /* Drop Mcast/Bcast frame with fragment bit on */
- if (pHeader->FC.MoreFrag) {
- /* release packet */
- RELEASE_NDIS_PACKET(pAd, pRxPacket,
- NDIS_STATUS_FAILURE);
- return;
- }
- /* Filter out Bcast frame which AP relayed for us */
- if (pHeader->FC.FrDs
- && MAC_ADDR_EQUAL(pHeader->Addr3, pAd->CurrentAddress)) {
- /* release packet */
- RELEASE_NDIS_PACKET(pAd, pRxPacket,
- NDIS_STATUS_FAILURE);
- return;
- }
-
- Indicate_Legacy_Packet(pAd, pRxBlk, FromWhichBSSID);
- return;
- } else if (pRxD->U2M) {
- pAd->LastRxRate =
- (u16)((pRxWI->MCS) + (pRxWI->BW << 7) +
- (pRxWI->ShortGI << 8) + (pRxWI->PHYMODE << 14));
-
- if (ADHOC_ON(pAd)) {
- pEntry = MacTableLookup(pAd, pHeader->Addr2);
- if (pEntry)
- Update_Rssi_Sample(pAd, &pEntry->RssiSample,
- pRxWI);
- }
-
- Update_Rssi_Sample(pAd, &pAd->StaCfg.RssiSample, pRxWI);
-
- pAd->StaCfg.LastSNR0 = (u8)(pRxWI->SNR0);
- pAd->StaCfg.LastSNR1 = (u8)(pRxWI->SNR1);
-
- pAd->RalinkCounters.OneSecRxOkDataCnt++;
-
- if (!((pHeader->Frag == 0) && (pHeader->FC.MoreFrag == 0))) {
- /* re-assemble the fragmented packets */
- /* return complete frame (pRxPacket) or NULL */
- bFragment = TRUE;
- pRxPacket = RTMPDeFragmentDataFrame(pAd, pRxBlk);
- }
-
- if (pRxPacket) {
- pEntry = &pAd->MacTab.Content[pRxWI->WirelessCliID];
-
- /* process complete frame */
- if (bFragment && (pRxD->Decrypted)
- && (pEntry->WepStatus ==
- Ndis802_11Encryption2Enabled)) {
- /* Minus MIC length */
- pRxBlk->DataSize -= 8;
-
- /* For TKIP frame, calculate the MIC value */
- if (STACheckTkipMICValue(pAd, pEntry, pRxBlk) ==
- FALSE) {
- return;
- }
- }
-
- STARxDataFrameAnnounce(pAd, pEntry, pRxBlk,
- FromWhichBSSID);
- return;
- } else {
- /* just return */
- /* because RTMPDeFragmentDataFrame() will release rx packet, */
- /* if packet is fragmented */
- return;
- }
- }
-
- ASSERT(0);
- /* release packet */
- RELEASE_NDIS_PACKET(pAd, pRxPacket, NDIS_STATUS_FAILURE);
-}
-
-void STAHandleRxMgmtFrame(struct rt_rtmp_adapter *pAd, struct rt_rx_blk *pRxBlk)
-{
- PRT28XX_RXD_STRUC pRxD = &(pRxBlk->RxD);
- struct rt_rxwi * pRxWI = pRxBlk->pRxWI;
- struct rt_header_802_11 * pHeader = pRxBlk->pHeader;
- void *pRxPacket = pRxBlk->pRxPacket;
-
- do {
-
- /* check if need to resend PS Poll when received packet with MoreData = 1 */
- if ((pAd->StaCfg.Psm == PWR_SAVE)
- && (pHeader->FC.MoreData == 1)) {
- /* for UAPSD, all management frames will be VO priority */
- if (pAd->CommonCfg.bAPSDAC_VO == 0) {
- /* non-UAPSD delivery-enabled AC */
- RTMP_PS_POLL_ENQUEUE(pAd);
- }
- }
-
- /* TODO: if MoreData == 0, station can go to sleep */
-
- /* We should collect RSSI not only U2M data but also my beacon */
- if ((pHeader->FC.SubType == SUBTYPE_BEACON)
- && (MAC_ADDR_EQUAL(&pAd->CommonCfg.Bssid, &pHeader->Addr2))
- && (pAd->RxAnt.EvaluatePeriod == 0)) {
- Update_Rssi_Sample(pAd, &pAd->StaCfg.RssiSample, pRxWI);
-
- pAd->StaCfg.LastSNR0 = (u8)(pRxWI->SNR0);
- pAd->StaCfg.LastSNR1 = (u8)(pRxWI->SNR1);
- }
-
- /* First check the size, it MUST not exceed the mlme queue size */
- if (pRxWI->MPDUtotalByteCount > MGMT_DMA_BUFFER_SIZE) {
- DBGPRINT_ERR("STAHandleRxMgmtFrame: frame too large, size = %d \n", pRxWI->MPDUtotalByteCount);
- break;
- }
-
- REPORT_MGMT_FRAME_TO_MLME(pAd, pRxWI->WirelessCliID, pHeader,
- pRxWI->MPDUtotalByteCount,
- pRxWI->RSSI0, pRxWI->RSSI1,
- pRxWI->RSSI2, pRxD->PlcpSignal);
- } while (FALSE);
-
- RELEASE_NDIS_PACKET(pAd, pRxPacket, NDIS_STATUS_SUCCESS);
-}
-
-void STAHandleRxControlFrame(struct rt_rtmp_adapter *pAd, struct rt_rx_blk *pRxBlk)
-{
- struct rt_rxwi * pRxWI = pRxBlk->pRxWI;
- struct rt_header_802_11 * pHeader = pRxBlk->pHeader;
- void *pRxPacket = pRxBlk->pRxPacket;
-
- switch (pHeader->FC.SubType) {
- case SUBTYPE_BLOCK_ACK_REQ:
- {
- CntlEnqueueForRecv(pAd, pRxWI->WirelessCliID,
- (pRxWI->MPDUtotalByteCount),
- (struct rt_frame_ba_req *) pHeader);
- }
- break;
- case SUBTYPE_BLOCK_ACK:
- case SUBTYPE_ACK:
- default:
- break;
- }
-
- RELEASE_NDIS_PACKET(pAd, pRxPacket, NDIS_STATUS_FAILURE);
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Process RxDone interrupt, running in DPC level
-
- Arguments:
- pAd Pointer to our adapter
-
- Return Value:
- None
-
- IRQL = DISPATCH_LEVEL
-
- Note:
- This routine has to maintain Rx ring read pointer.
- Need to consider QOS DATA format when converting to 802.3
- ========================================================================
-*/
-BOOLEAN STARxDoneInterruptHandle(struct rt_rtmp_adapter *pAd, IN BOOLEAN argc)
-{
- int Status;
- u32 RxProcessed, RxPending;
- BOOLEAN bReschedule = FALSE;
- PRT28XX_RXD_STRUC pRxD;
- u8 *pData;
- struct rt_rxwi * pRxWI;
- void *pRxPacket;
- struct rt_header_802_11 * pHeader;
- struct rt_rx_blk RxCell;
-
- RxProcessed = RxPending = 0;
-
- /* process whole rx ring */
- while (1) {
-
- if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_RADIO_OFF |
- fRTMP_ADAPTER_RESET_IN_PROGRESS |
- fRTMP_ADAPTER_HALT_IN_PROGRESS |
- fRTMP_ADAPTER_NIC_NOT_EXIST) ||
- !RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_START_UP)) {
- break;
- }
-#ifdef RTMP_MAC_PCI
- if (RxProcessed++ > MAX_RX_PROCESS_CNT) {
- /* need to reschedule rx handle */
- bReschedule = TRUE;
- break;
- }
-#endif /* RTMP_MAC_PCI // */
-
- RxProcessed++; /* test */
-
- /* 1. allocate a new data packet into rx ring to replace received packet */
- /* then processing the received packet */
- /* 2. the callee must take charge of release of packet */
- /* 3. As far as driver is concerned , */
- /* the rx packet must */
- /* a. be indicated to upper layer or */
- /* b. be released if it is discarded */
- pRxPacket =
- GetPacketFromRxRing(pAd, &(RxCell.RxD), &bReschedule,
- &RxPending);
- if (pRxPacket == NULL) {
- /* no more packet to process */
- break;
- }
- /* get rx ring descriptor */
- pRxD = &(RxCell.RxD);
- /* get rx data buffer */
- pData = GET_OS_PKT_DATAPTR(pRxPacket);
- pRxWI = (struct rt_rxwi *) pData;
- pHeader = (struct rt_header_802_11 *) (pData + RXWI_SIZE);
-
- /* build RxCell */
- RxCell.pRxWI = pRxWI;
- RxCell.pHeader = pHeader;
- RxCell.pRxPacket = pRxPacket;
- RxCell.pData = (u8 *) pHeader;
- RxCell.DataSize = pRxWI->MPDUtotalByteCount;
- RxCell.Flags = 0;
-
- /* Increase Total receive byte counter after real data received no mater any error or not */
- pAd->RalinkCounters.ReceivedByteCount +=
- pRxWI->MPDUtotalByteCount;
- pAd->RalinkCounters.OneSecReceivedByteCount +=
- pRxWI->MPDUtotalByteCount;
- pAd->RalinkCounters.RxCount++;
-
- INC_COUNTER64(pAd->WlanCounters.ReceivedFragmentCount);
-
- if (pRxWI->MPDUtotalByteCount < 14)
- Status = NDIS_STATUS_FAILURE;
-
- if (MONITOR_ON(pAd)) {
- send_monitor_packets(pAd, &RxCell);
- break;
- }
-
- /* STARxDoneInterruptHandle() is called in rtusb_bulk.c */
-
- /* Check for all RxD errors */
- Status = RTMPCheckRxError(pAd, pHeader, pRxWI, pRxD);
-
- /* Handle the received frame */
- if (Status == NDIS_STATUS_SUCCESS) {
- switch (pHeader->FC.Type) {
- /* CASE I, receive a DATA frame */
- case BTYPE_DATA:
- {
- /* process DATA frame */
- STAHandleRxDataFrame(pAd, &RxCell);
- }
- break;
- /* CASE II, receive a MGMT frame */
- case BTYPE_MGMT:
- {
- STAHandleRxMgmtFrame(pAd, &RxCell);
- }
- break;
- /* CASE III. receive a CNTL frame */
- case BTYPE_CNTL:
- {
- STAHandleRxControlFrame(pAd, &RxCell);
- }
- break;
- /* discard other type */
- default:
- RELEASE_NDIS_PACKET(pAd, pRxPacket,
- NDIS_STATUS_FAILURE);
- break;
- }
- } else {
- pAd->Counters8023.RxErrors++;
- /* discard this frame */
- RELEASE_NDIS_PACKET(pAd, pRxPacket,
- NDIS_STATUS_FAILURE);
- }
- }
-
- return bReschedule;
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Arguments:
- pAd Pointer to our adapter
-
- IRQL = DISPATCH_LEVEL
-
- ========================================================================
-*/
-void RTMPHandleTwakeupInterrupt(struct rt_rtmp_adapter *pAd)
-{
- AsicForceWakeup(pAd, FALSE);
-}
-
-/*
-========================================================================
-Routine Description:
- Early checking and OS-depened parsing for Tx packet send to our STA driver.
-
-Arguments:
- void * MiniportAdapterContext Pointer refer to the device handle, i.e., the pAd.
- void ** ppPacketArray The packet array need to do transmission.
- u32 NumberOfPackets Number of packet in packet array.
-
-Return Value:
- NONE
-
-Note:
- This function does early checking and classification for send-out packet.
- You only can put OS-depened & STA related code in here.
-========================================================================
-*/
-void STASendPackets(void *MiniportAdapterContext,
- void **ppPacketArray, u32 NumberOfPackets)
-{
- u32 Index;
- struct rt_rtmp_adapter *pAd = (struct rt_rtmp_adapter *)MiniportAdapterContext;
- void *pPacket;
- BOOLEAN allowToSend = FALSE;
-
- for (Index = 0; Index < NumberOfPackets; Index++) {
- pPacket = ppPacketArray[Index];
-
- do {
- if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_RESET_IN_PROGRESS)
- || RTMP_TEST_FLAG(pAd,
- fRTMP_ADAPTER_HALT_IN_PROGRESS)
- || RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_RADIO_OFF)) {
- /* Drop send request since hardware is in reset state */
- break;
- } else if (!INFRA_ON(pAd) && !ADHOC_ON(pAd)) {
- /* Drop send request since there are no physical connection yet */
- break;
- } else {
- /* Record that orignal packet source is from NDIS layer,so that */
- /* later on driver knows how to release this NDIS PACKET */
- RTMP_SET_PACKET_WCID(pPacket, 0); /* this field is useless when in STA mode */
- RTMP_SET_PACKET_SOURCE(pPacket, PKTSRC_NDIS);
- NDIS_SET_PACKET_STATUS(pPacket,
- NDIS_STATUS_PENDING);
- pAd->RalinkCounters.PendingNdisPacketCount++;
-
- allowToSend = TRUE;
- }
- } while (FALSE);
-
- if (allowToSend == TRUE)
- STASendPacket(pAd, pPacket);
- else
- RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_FAILURE);
- }
-
- /* Dequeue outgoing frames from TxSwQueue[] and process it */
- RTMPDeQueuePacket(pAd, FALSE, NUM_OF_TX_RING, MAX_TX_PROCESS);
-
-}
-
-/*
-========================================================================
-Routine Description:
- This routine is used to do packet parsing and classification for Tx packet
- to STA device, and it will en-queue packets to our TxSwQueue depends on AC
- class.
-
-Arguments:
- pAd Pointer to our adapter
- pPacket Pointer to send packet
-
-Return Value:
- NDIS_STATUS_SUCCESS If success to queue the packet into TxSwQueue.
- NDIS_STATUS_FAILURE If failed to do en-queue.
-
-Note:
- You only can put OS-indepened & STA related code in here.
-========================================================================
-*/
-int STASendPacket(struct rt_rtmp_adapter *pAd, void *pPacket)
-{
- struct rt_packet_info PacketInfo;
- u8 *pSrcBufVA;
- u32 SrcBufLen;
- u32 AllowFragSize;
- u8 NumberOfFrag;
- u8 RTSRequired;
- u8 QueIdx, UserPriority;
- struct rt_mac_table_entry *pEntry = NULL;
- unsigned int IrqFlags;
- u8 FlgIsIP = 0;
- u8 Rate;
-
- /* Prepare packet information structure for buffer descriptor */
- /* chained within a single NDIS packet. */
- RTMP_QueryPacketInfo(pPacket, &PacketInfo, &pSrcBufVA, &SrcBufLen);
-
- if (pSrcBufVA == NULL) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("STASendPacket --> pSrcBufVA == NULL !SrcBufLen=%x\n",
- SrcBufLen));
- /* Resource is low, system did not allocate virtual address */
- /* return NDIS_STATUS_FAILURE directly to upper layer */
- RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_FAILURE);
- return NDIS_STATUS_FAILURE;
- }
-
- if (SrcBufLen < 14) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("STASendPacket --> Ndis Packet buffer error!\n"));
- RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_FAILURE);
- return (NDIS_STATUS_FAILURE);
- }
- /* In HT rate adhoc mode, A-MPDU is often used. So need to lookup BA Table and MAC Entry. */
- /* Note multicast packets in adhoc also use BSSID_WCID index. */
- {
- if (INFRA_ON(pAd)) {
- {
- pEntry = &pAd->MacTab.Content[BSSID_WCID];
- RTMP_SET_PACKET_WCID(pPacket, BSSID_WCID);
- Rate = pAd->CommonCfg.TxRate;
- }
- } else if (ADHOC_ON(pAd)) {
- if (*pSrcBufVA & 0x01) {
- RTMP_SET_PACKET_WCID(pPacket, MCAST_WCID);
- pEntry = &pAd->MacTab.Content[MCAST_WCID];
- } else {
- pEntry = MacTableLookup(pAd, pSrcBufVA);
- }
- Rate = pAd->CommonCfg.TxRate;
- }
- }
-
- if (!pEntry) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("STASendPacket->Cannot find pEntry(%pM) in MacTab!\n",
- pSrcBufVA));
- /* Resource is low, system did not allocate virtual address */
- /* return NDIS_STATUS_FAILURE directly to upper layer */
- RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_FAILURE);
- return NDIS_STATUS_FAILURE;
- }
-
- if (ADHOC_ON(pAd)
- ) {
- RTMP_SET_PACKET_WCID(pPacket, (u8)pEntry->Aid);
- }
- /* */
- /* Check the Ethernet Frame type of this packet, and set the RTMP_SET_PACKET_SPECIFIC flags. */
- /* Here we set the PACKET_SPECIFIC flags(LLC, VLAN, DHCP/ARP, EAPOL). */
- RTMPCheckEtherType(pAd, pPacket);
-
- /* */
- /* WPA 802.1x secured port control - drop all non-802.1x frame before port secured */
- /* */
- if (((pAd->StaCfg.AuthMode == Ndis802_11AuthModeWPA) ||
- (pAd->StaCfg.AuthMode == Ndis802_11AuthModeWPAPSK) ||
- (pAd->StaCfg.AuthMode == Ndis802_11AuthModeWPA2) ||
- (pAd->StaCfg.AuthMode == Ndis802_11AuthModeWPA2PSK)
- || (pAd->StaCfg.IEEE8021X == TRUE)
- )
- && ((pAd->StaCfg.PortSecured == WPA_802_1X_PORT_NOT_SECURED)
- || (pAd->StaCfg.MicErrCnt >= 2))
- && (RTMP_GET_PACKET_EAPOL(pPacket) == FALSE)
- ) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("STASendPacket --> Drop packet before port secured!\n"));
- RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_FAILURE);
-
- return (NDIS_STATUS_FAILURE);
- }
-
- /* STEP 1. Decide number of fragments required to deliver this MSDU. */
- /* The estimation here is not very accurate because difficult to */
- /* take encryption overhead into consideration here. The result */
- /* "NumberOfFrag" is then just used to pre-check if enough free */
- /* TXD are available to hold this MSDU. */
-
- if (*pSrcBufVA & 0x01) /* fragmentation not allowed on multicast & broadcast */
- NumberOfFrag = 1;
- else if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_AGGREGATION_INUSED))
- NumberOfFrag = 1; /* Aggregation overwhelms fragmentation */
- else if (CLIENT_STATUS_TEST_FLAG(pEntry, fCLIENT_STATUS_AMSDU_INUSED))
- NumberOfFrag = 1; /* Aggregation overwhelms fragmentation */
- else if ((pAd->StaCfg.HTPhyMode.field.MODE == MODE_HTMIX)
- || (pAd->StaCfg.HTPhyMode.field.MODE == MODE_HTGREENFIELD))
- NumberOfFrag = 1; /* MIMO RATE overwhelms fragmentation */
- else {
- /* The calculated "NumberOfFrag" is a rough estimation because of various */
- /* encryption/encapsulation overhead not taken into consideration. This number is just */
- /* used to make sure enough free TXD are available before fragmentation takes place. */
- /* In case the actual required number of fragments of an NDIS packet */
- /* excceeds "NumberOfFrag"caculated here and not enough free TXD available, the */
- /* last fragment (i.e. last MPDU) will be dropped in RTMPHardTransmit() due to out of */
- /* resource, and the NDIS packet will be indicated NDIS_STATUS_FAILURE. This should */
- /* rarely happen and the penalty is just like a TX RETRY fail. Affordable. */
-
- AllowFragSize =
- (pAd->CommonCfg.FragmentThreshold) - LENGTH_802_11 -
- LENGTH_CRC;
- NumberOfFrag =
- ((PacketInfo.TotalPacketLength - LENGTH_802_3 +
- LENGTH_802_1_H) / AllowFragSize) + 1;
- /* To get accurate number of fragmentation, Minus 1 if the size just match to allowable fragment size */
- if (((PacketInfo.TotalPacketLength - LENGTH_802_3 +
- LENGTH_802_1_H) % AllowFragSize) == 0) {
- NumberOfFrag--;
- }
- }
-
- /* Save fragment number to Ndis packet reserved field */
- RTMP_SET_PACKET_FRAGMENTS(pPacket, NumberOfFrag);
-
- /* STEP 2. Check the requirement of RTS: */
- /* If multiple fragment required, RTS is required only for the first fragment */
- /* if the fragment size is larger than RTS threshold */
- /* For RT28xx, Let ASIC send RTS/CTS */
- /* RTMP_SET_PACKET_RTS(pPacket, 0); */
- if (NumberOfFrag > 1)
- RTSRequired =
- (pAd->CommonCfg.FragmentThreshold >
- pAd->CommonCfg.RtsThreshold) ? 1 : 0;
- else
- RTSRequired =
- (PacketInfo.TotalPacketLength >
- pAd->CommonCfg.RtsThreshold) ? 1 : 0;
-
- /* Save RTS requirement to Ndis packet reserved field */
- RTMP_SET_PACKET_RTS(pPacket, RTSRequired);
- RTMP_SET_PACKET_TXRATE(pPacket, pAd->CommonCfg.TxRate);
-
- /* */
- /* STEP 3. Traffic classification. outcome = <UserPriority, QueIdx> */
- /* */
- UserPriority = 0;
- QueIdx = QID_AC_BE;
- if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_WMM_INUSED) &&
- CLIENT_STATUS_TEST_FLAG(pEntry, fCLIENT_STATUS_WMM_CAPABLE)) {
- u16 Protocol;
- u8 LlcSnapLen = 0, Byte0, Byte1;
- do {
- /* get Ethernet protocol field */
- Protocol =
- (u16)((pSrcBufVA[12] << 8) + pSrcBufVA[13]);
- if (Protocol <= 1500) {
- /* get Ethernet protocol field from LLC/SNAP */
- if (Sniff2BytesFromNdisBuffer
- (PacketInfo.pFirstBuffer, LENGTH_802_3 + 6,
- &Byte0, &Byte1) != NDIS_STATUS_SUCCESS)
- break;
-
- Protocol = (u16)((Byte0 << 8) + Byte1);
- LlcSnapLen = 8;
- }
- /* always AC_BE for non-IP packet */
- if (Protocol != 0x0800)
- break;
-
- /* get IP header */
- if (Sniff2BytesFromNdisBuffer
- (PacketInfo.pFirstBuffer, LENGTH_802_3 + LlcSnapLen,
- &Byte0, &Byte1) != NDIS_STATUS_SUCCESS)
- break;
-
- /* return AC_BE if packet is not IPv4 */
- if ((Byte0 & 0xf0) != 0x40)
- break;
-
- FlgIsIP = 1;
- UserPriority = (Byte1 & 0xe0) >> 5;
- QueIdx = MapUserPriorityToAccessCategory[UserPriority];
-
- /* TODO: have to check ACM bit. apply TSPEC if ACM is ON */
- /* TODO: downgrade UP & QueIdx before passing ACM */
- /*
- Under WMM ACM control, we dont need to check the bit;
- Or when a TSPEC is built for VO but we will change to issue
- BA session for BE here, so we will not use BA to send VO packets.
- */
- if (pAd->CommonCfg.APEdcaParm.bACM[QueIdx]) {
- UserPriority = 0;
- QueIdx = QID_AC_BE;
- }
- } while (FALSE);
- }
-
- RTMP_SET_PACKET_UP(pPacket, UserPriority);
-
- /* Make sure SendTxWait queue resource won't be used by other threads */
- RTMP_IRQ_LOCK(&pAd->irq_lock, IrqFlags);
- if (pAd->TxSwQueue[QueIdx].Number >= MAX_PACKETS_IN_QUEUE) {
- RTMP_IRQ_UNLOCK(&pAd->irq_lock, IrqFlags);
- RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_FAILURE);
-
- return NDIS_STATUS_FAILURE;
- } else {
- InsertTailQueueAc(pAd, pEntry, &pAd->TxSwQueue[QueIdx],
- PACKET_TO_QUEUE_ENTRY(pPacket));
- }
- RTMP_IRQ_UNLOCK(&pAd->irq_lock, IrqFlags);
-
- if ((pAd->CommonCfg.BACapability.field.AutoBA == TRUE) &&
- IS_HT_STA(pEntry)) {
- /*struct rt_mac_table_entry *pMacEntry = &pAd->MacTab.Content[BSSID_WCID]; */
- if (((pEntry->TXBAbitmap & (1 << UserPriority)) == 0) &&
- ((pEntry->BADeclineBitmap & (1 << UserPriority)) == 0) &&
- (pEntry->PortSecured == WPA_802_1X_PORT_SECURED)
- /* For IOT compatibility, if */
- /* 1. It is Ralink chip or */
- /* 2. It is OPEN or AES mode, */
- /* then BA session can be bulit. */
- && ((pEntry->ValidAsCLI && pAd->MlmeAux.APRalinkIe != 0x0)
- || (pEntry->WepStatus != Ndis802_11WEPEnabled
- && pEntry->WepStatus !=
- Ndis802_11Encryption2Enabled))
- ) {
- BAOriSessionSetUp(pAd, pEntry, UserPriority, 0, 10,
- FALSE);
- }
- }
-
- pAd->RalinkCounters.OneSecOsTxCount[QueIdx]++; /* TODO: for debug only. to be removed */
- return NDIS_STATUS_SUCCESS;
-}
-
-/*
- ========================================================================
-
- Routine Description:
- This subroutine will scan through relative ring descriptor to find
- out available free ring descriptor and compare with request size.
-
- Arguments:
- pAd Pointer to our adapter
- QueIdx Selected TX Ring
-
- Return Value:
- NDIS_STATUS_FAILURE Not enough free descriptor
- NDIS_STATUS_SUCCESS Enough free descriptor
-
- IRQL = PASSIVE_LEVEL
- IRQL = DISPATCH_LEVEL
-
- Note:
-
- ========================================================================
-*/
-#ifdef RTMP_MAC_PCI
-int RTMPFreeTXDRequest(struct rt_rtmp_adapter *pAd,
- u8 QueIdx,
- u8 NumberRequired, u8 *FreeNumberIs)
-{
- unsigned long FreeNumber = 0;
- int Status = NDIS_STATUS_FAILURE;
-
- switch (QueIdx) {
- case QID_AC_BK:
- case QID_AC_BE:
- case QID_AC_VI:
- case QID_AC_VO:
- if (pAd->TxRing[QueIdx].TxSwFreeIdx >
- pAd->TxRing[QueIdx].TxCpuIdx)
- FreeNumber =
- pAd->TxRing[QueIdx].TxSwFreeIdx -
- pAd->TxRing[QueIdx].TxCpuIdx - 1;
- else
- FreeNumber =
- pAd->TxRing[QueIdx].TxSwFreeIdx + TX_RING_SIZE -
- pAd->TxRing[QueIdx].TxCpuIdx - 1;
-
- if (FreeNumber >= NumberRequired)
- Status = NDIS_STATUS_SUCCESS;
- break;
-
- case QID_MGMT:
- if (pAd->MgmtRing.TxSwFreeIdx > pAd->MgmtRing.TxCpuIdx)
- FreeNumber =
- pAd->MgmtRing.TxSwFreeIdx - pAd->MgmtRing.TxCpuIdx -
- 1;
- else
- FreeNumber =
- pAd->MgmtRing.TxSwFreeIdx + MGMT_RING_SIZE -
- pAd->MgmtRing.TxCpuIdx - 1;
-
- if (FreeNumber >= NumberRequired)
- Status = NDIS_STATUS_SUCCESS;
- break;
-
- default:
- DBGPRINT(RT_DEBUG_ERROR,
- ("RTMPFreeTXDRequest::Invalid QueIdx(=%d)\n", QueIdx));
- break;
- }
- *FreeNumberIs = (u8)FreeNumber;
-
- return (Status);
-}
-#endif /* RTMP_MAC_PCI // */
-#ifdef RTMP_MAC_USB
-/*
- Actually, this function used to check if the TxHardware Queue still has frame need to send.
- If no frame need to send, go to sleep, else, still wake up.
-*/
-int RTMPFreeTXDRequest(struct rt_rtmp_adapter *pAd,
- u8 QueIdx,
- u8 NumberRequired, u8 *FreeNumberIs)
-{
- /*unsigned long FreeNumber = 0; */
- int Status = NDIS_STATUS_FAILURE;
- unsigned long IrqFlags;
- struct rt_ht_tx_context *pHTTXContext;
-
- switch (QueIdx) {
- case QID_AC_BK:
- case QID_AC_BE:
- case QID_AC_VI:
- case QID_AC_VO:
- {
- pHTTXContext = &pAd->TxContext[QueIdx];
- RTMP_IRQ_LOCK(&pAd->TxContextQueueLock[QueIdx],
- IrqFlags);
- if ((pHTTXContext->CurWritePosition !=
- pHTTXContext->ENextBulkOutPosition)
- || (pHTTXContext->IRPPending == TRUE)) {
- Status = NDIS_STATUS_FAILURE;
- } else {
- Status = NDIS_STATUS_SUCCESS;
- }
- RTMP_IRQ_UNLOCK(&pAd->TxContextQueueLock[QueIdx],
- IrqFlags);
- }
- break;
- case QID_MGMT:
- if (pAd->MgmtRing.TxSwFreeIdx != MGMT_RING_SIZE)
- Status = NDIS_STATUS_FAILURE;
- else
- Status = NDIS_STATUS_SUCCESS;
- break;
- default:
- DBGPRINT(RT_DEBUG_ERROR,
- ("RTMPFreeTXDRequest::Invalid QueIdx(=%d)\n", QueIdx));
- break;
- }
-
- return (Status);
-}
-#endif /* RTMP_MAC_USB // */
-
-void RTMPSendDisassociationFrame(struct rt_rtmp_adapter *pAd)
-{
-}
-
-void RTMPSendNullFrame(struct rt_rtmp_adapter *pAd,
- u8 TxRate, IN BOOLEAN bQosNull)
-{
- u8 NullFrame[48];
- unsigned long Length;
- struct rt_header_802_11 * pHeader_802_11;
-
- /* WPA 802.1x secured port control */
- if (((pAd->StaCfg.AuthMode == Ndis802_11AuthModeWPA) ||
- (pAd->StaCfg.AuthMode == Ndis802_11AuthModeWPAPSK) ||
- (pAd->StaCfg.AuthMode == Ndis802_11AuthModeWPA2) ||
- (pAd->StaCfg.AuthMode == Ndis802_11AuthModeWPA2PSK)
- || (pAd->StaCfg.IEEE8021X == TRUE)
- ) && (pAd->StaCfg.PortSecured == WPA_802_1X_PORT_NOT_SECURED)) {
- return;
- }
-
- NdisZeroMemory(NullFrame, 48);
- Length = sizeof(struct rt_header_802_11);
-
- pHeader_802_11 = (struct rt_header_802_11 *) NullFrame;
-
- pHeader_802_11->FC.Type = BTYPE_DATA;
- pHeader_802_11->FC.SubType = SUBTYPE_NULL_FUNC;
- pHeader_802_11->FC.ToDs = 1;
- COPY_MAC_ADDR(pHeader_802_11->Addr1, pAd->CommonCfg.Bssid);
- COPY_MAC_ADDR(pHeader_802_11->Addr2, pAd->CurrentAddress);
- COPY_MAC_ADDR(pHeader_802_11->Addr3, pAd->CommonCfg.Bssid);
-
- if (pAd->CommonCfg.bAPSDForcePowerSave) {
- pHeader_802_11->FC.PwrMgmt = PWR_SAVE;
- } else {
- pHeader_802_11->FC.PwrMgmt =
- (pAd->StaCfg.Psm == PWR_SAVE) ? 1 : 0;
- }
- pHeader_802_11->Duration =
- pAd->CommonCfg.Dsifs + RTMPCalcDuration(pAd, TxRate, 14);
-
- pAd->Sequence++;
- pHeader_802_11->Sequence = pAd->Sequence;
-
- /* Prepare QosNull function frame */
- if (bQosNull) {
- pHeader_802_11->FC.SubType = SUBTYPE_QOS_NULL;
-
- /* copy QOS control bytes */
- NullFrame[Length] = 0;
- NullFrame[Length + 1] = 0;
- Length += 2; /* if pad with 2 bytes for alignment, APSD will fail */
- }
-
- HAL_KickOutNullFrameTx(pAd, 0, NullFrame, Length);
-
-}
-
-/* IRQL = DISPATCH_LEVEL */
-void RTMPSendRTSFrame(struct rt_rtmp_adapter *pAd,
- u8 *pDA,
- IN unsigned int NextMpduSize,
- u8 TxRate,
- u8 RTSRate,
- u16 AckDuration, u8 QueIdx, u8 FrameGap)
-{
-}
-
-/* -------------------------------------------------------- */
-/* FIND ENCRYPT KEY AND DECIDE CIPHER ALGORITHM */
-/* Find the WPA key, either Group or Pairwise Key */
-/* LEAP + TKIP also use WPA key. */
-/* -------------------------------------------------------- */
-/* Decide WEP bit and cipher suite to be used. Same cipher suite should be used for whole fragment burst */
-/* In Cisco CCX 2.0 Leap Authentication */
-/* WepStatus is Ndis802_11Encryption1Enabled but the key will use PairwiseKey */
-/* Instead of the SharedKey, SharedKey Length may be Zero. */
-void STAFindCipherAlgorithm(struct rt_rtmp_adapter *pAd, struct rt_tx_blk *pTxBlk)
-{
- NDIS_802_11_ENCRYPTION_STATUS Cipher; /* To indicate cipher used for this packet */
- u8 CipherAlg = CIPHER_NONE; /* cipher alogrithm */
- u8 KeyIdx = 0xff;
- u8 *pSrcBufVA;
- struct rt_cipher_key *pKey = NULL;
-
- pSrcBufVA = GET_OS_PKT_DATAPTR(pTxBlk->pPacket);
-
- {
- /* Select Cipher */
- if ((*pSrcBufVA & 0x01) && (ADHOC_ON(pAd)))
- Cipher = pAd->StaCfg.GroupCipher; /* Cipher for Multicast or Broadcast */
- else
- Cipher = pAd->StaCfg.PairCipher; /* Cipher for Unicast */
-
- if (RTMP_GET_PACKET_EAPOL(pTxBlk->pPacket)) {
- ASSERT(pAd->SharedKey[BSS0][0].CipherAlg <=
- CIPHER_CKIP128);
-
- /* 4-way handshaking frame must be clear */
- if (!(TX_BLK_TEST_FLAG(pTxBlk, fTX_bClearEAPFrame))
- && (pAd->SharedKey[BSS0][0].CipherAlg)
- && (pAd->SharedKey[BSS0][0].KeyLen)) {
- CipherAlg = pAd->SharedKey[BSS0][0].CipherAlg;
- KeyIdx = 0;
- }
- } else if (Cipher == Ndis802_11Encryption1Enabled) {
- KeyIdx = pAd->StaCfg.DefaultKeyId;
- } else if ((Cipher == Ndis802_11Encryption2Enabled) ||
- (Cipher == Ndis802_11Encryption3Enabled)) {
- if ((*pSrcBufVA & 0x01) && (ADHOC_ON(pAd))) /* multicast */
- KeyIdx = pAd->StaCfg.DefaultKeyId;
- else if (pAd->SharedKey[BSS0][0].KeyLen)
- KeyIdx = 0;
- else
- KeyIdx = pAd->StaCfg.DefaultKeyId;
- }
-
- if (KeyIdx == 0xff)
- CipherAlg = CIPHER_NONE;
- else if ((Cipher == Ndis802_11EncryptionDisabled)
- || (pAd->SharedKey[BSS0][KeyIdx].KeyLen == 0))
- CipherAlg = CIPHER_NONE;
- else if (pAd->StaCfg.WpaSupplicantUP &&
- (Cipher == Ndis802_11Encryption1Enabled) &&
- (pAd->StaCfg.IEEE8021X == TRUE) &&
- (pAd->StaCfg.PortSecured ==
- WPA_802_1X_PORT_NOT_SECURED))
- CipherAlg = CIPHER_NONE;
- else {
- /*Header_802_11.FC.Wep = 1; */
- CipherAlg = pAd->SharedKey[BSS0][KeyIdx].CipherAlg;
- pKey = &pAd->SharedKey[BSS0][KeyIdx];
- }
- }
-
- pTxBlk->CipherAlg = CipherAlg;
- pTxBlk->pKey = pKey;
-}
-
-void STABuildCommon802_11Header(struct rt_rtmp_adapter *pAd, struct rt_tx_blk *pTxBlk)
-{
- struct rt_header_802_11 *pHeader_802_11;
-
- /* */
- /* MAKE A COMMON 802.11 HEADER */
- /* */
-
- /* normal wlan header size : 24 octets */
- pTxBlk->MpduHeaderLen = sizeof(struct rt_header_802_11);
-
- pHeader_802_11 =
- (struct rt_header_802_11 *) & pTxBlk->HeaderBuf[TXINFO_SIZE + TXWI_SIZE];
-
- NdisZeroMemory(pHeader_802_11, sizeof(struct rt_header_802_11));
-
- pHeader_802_11->FC.FrDs = 0;
- pHeader_802_11->FC.Type = BTYPE_DATA;
- pHeader_802_11->FC.SubType =
- ((TX_BLK_TEST_FLAG(pTxBlk, fTX_bWMM)) ? SUBTYPE_QDATA :
- SUBTYPE_DATA);
-
- if (pTxBlk->pMacEntry) {
- if (TX_BLK_TEST_FLAG(pTxBlk, fTX_bForceNonQoS)) {
- pHeader_802_11->Sequence =
- pTxBlk->pMacEntry->NonQosDataSeq;
- pTxBlk->pMacEntry->NonQosDataSeq =
- (pTxBlk->pMacEntry->NonQosDataSeq + 1) & MAXSEQ;
- } else {
- {
- pHeader_802_11->Sequence =
- pTxBlk->pMacEntry->TxSeq[pTxBlk->
- UserPriority];
- pTxBlk->pMacEntry->TxSeq[pTxBlk->UserPriority] =
- (pTxBlk->pMacEntry->
- TxSeq[pTxBlk->UserPriority] + 1) & MAXSEQ;
- }
- }
- } else {
- pHeader_802_11->Sequence = pAd->Sequence;
- pAd->Sequence = (pAd->Sequence + 1) & MAXSEQ; /* next sequence */
- }
-
- pHeader_802_11->Frag = 0;
-
- pHeader_802_11->FC.MoreData = TX_BLK_TEST_FLAG(pTxBlk, fTX_bMoreData);
-
- {
- if (INFRA_ON(pAd)) {
- {
- COPY_MAC_ADDR(pHeader_802_11->Addr1,
- pAd->CommonCfg.Bssid);
- COPY_MAC_ADDR(pHeader_802_11->Addr2,
- pAd->CurrentAddress);
- COPY_MAC_ADDR(pHeader_802_11->Addr3,
- pTxBlk->pSrcBufHeader);
- pHeader_802_11->FC.ToDs = 1;
- }
- } else if (ADHOC_ON(pAd)) {
- COPY_MAC_ADDR(pHeader_802_11->Addr1,
- pTxBlk->pSrcBufHeader);
- COPY_MAC_ADDR(pHeader_802_11->Addr2,
- pAd->CurrentAddress);
- COPY_MAC_ADDR(pHeader_802_11->Addr3,
- pAd->CommonCfg.Bssid);
- pHeader_802_11->FC.ToDs = 0;
- }
- }
-
- if (pTxBlk->CipherAlg != CIPHER_NONE)
- pHeader_802_11->FC.Wep = 1;
-
- /* ----------------------------------------------------------------- */
- /* STEP 2. MAKE A COMMON 802.11 HEADER SHARED BY ENTIRE FRAGMENT BURST. Fill sequence later. */
- /* ----------------------------------------------------------------- */
- if (pAd->CommonCfg.bAPSDForcePowerSave)
- pHeader_802_11->FC.PwrMgmt = PWR_SAVE;
- else
- pHeader_802_11->FC.PwrMgmt = (pAd->StaCfg.Psm == PWR_SAVE);
-}
-
-void STABuildCache802_11Header(struct rt_rtmp_adapter *pAd,
- struct rt_tx_blk *pTxBlk, u8 * pHeader)
-{
- struct rt_mac_table_entry *pMacEntry;
- struct rt_header_802_11 * pHeader80211;
-
- pHeader80211 = (struct rt_header_802_11 *) pHeader;
- pMacEntry = pTxBlk->pMacEntry;
-
- /* */
- /* Update the cached 802.11 HEADER */
- /* */
-
- /* normal wlan header size : 24 octets */
- pTxBlk->MpduHeaderLen = sizeof(struct rt_header_802_11);
-
- /* More Bit */
- pHeader80211->FC.MoreData = TX_BLK_TEST_FLAG(pTxBlk, fTX_bMoreData);
-
- /* Sequence */
- pHeader80211->Sequence = pMacEntry->TxSeq[pTxBlk->UserPriority];
- pMacEntry->TxSeq[pTxBlk->UserPriority] =
- (pMacEntry->TxSeq[pTxBlk->UserPriority] + 1) & MAXSEQ;
-
- {
- /* Check if the frame can be sent through DLS direct link interface */
- /* If packet can be sent through DLS, then force aggregation disable. (Hard to determine peer STA's capability) */
-
- /* The addr3 of normal packet send from DS is Dest Mac address. */
- if (ADHOC_ON(pAd))
- COPY_MAC_ADDR(pHeader80211->Addr3,
- pAd->CommonCfg.Bssid);
- else
- COPY_MAC_ADDR(pHeader80211->Addr3,
- pTxBlk->pSrcBufHeader);
- }
-
- /* ----------------------------------------------------------------- */
- /* STEP 2. MAKE A COMMON 802.11 HEADER SHARED BY ENTIRE FRAGMENT BURST. Fill sequence later. */
- /* ----------------------------------------------------------------- */
- if (pAd->CommonCfg.bAPSDForcePowerSave)
- pHeader80211->FC.PwrMgmt = PWR_SAVE;
- else
- pHeader80211->FC.PwrMgmt = (pAd->StaCfg.Psm == PWR_SAVE);
-}
-
-static inline u8 *STA_Build_ARalink_Frame_Header(struct rt_rtmp_adapter *pAd,
- struct rt_tx_blk *pTxBlk)
-{
- u8 *pHeaderBufPtr;
- struct rt_header_802_11 *pHeader_802_11;
- void *pNextPacket;
- u32 nextBufLen;
- struct rt_queue_entry *pQEntry;
-
- STAFindCipherAlgorithm(pAd, pTxBlk);
- STABuildCommon802_11Header(pAd, pTxBlk);
-
- pHeaderBufPtr = &pTxBlk->HeaderBuf[TXINFO_SIZE + TXWI_SIZE];
- pHeader_802_11 = (struct rt_header_802_11 *) pHeaderBufPtr;
-
- /* steal "order" bit to mark "aggregation" */
- pHeader_802_11->FC.Order = 1;
-
- /* skip common header */
- pHeaderBufPtr += pTxBlk->MpduHeaderLen;
-
- if (TX_BLK_TEST_FLAG(pTxBlk, fTX_bWMM)) {
- /* */
- /* build QOS Control bytes */
- /* */
- *pHeaderBufPtr = (pTxBlk->UserPriority & 0x0F);
-
- *(pHeaderBufPtr + 1) = 0;
- pHeaderBufPtr += 2;
- pTxBlk->MpduHeaderLen += 2;
- }
- /* padding at front of LLC header. LLC header should at 4-bytes alignment. */
- pTxBlk->HdrPadLen = (unsigned long)pHeaderBufPtr;
- pHeaderBufPtr = (u8 *)ROUND_UP(pHeaderBufPtr, 4);
- pTxBlk->HdrPadLen = (unsigned long)(pHeaderBufPtr - pTxBlk->HdrPadLen);
-
- /* For RA Aggregation, */
- /* put the 2nd MSDU length(extra 2-byte field) after struct rt_qos_control in little endian format */
- pQEntry = pTxBlk->TxPacketList.Head;
- pNextPacket = QUEUE_ENTRY_TO_PACKET(pQEntry);
- nextBufLen = GET_OS_PKT_LEN(pNextPacket);
- if (RTMP_GET_PACKET_VLAN(pNextPacket))
- nextBufLen -= LENGTH_802_1Q;
-
- *pHeaderBufPtr = (u8)nextBufLen & 0xff;
- *(pHeaderBufPtr + 1) = (u8)(nextBufLen >> 8);
-
- pHeaderBufPtr += 2;
- pTxBlk->MpduHeaderLen += 2;
-
- return pHeaderBufPtr;
-
-}
-
-static inline u8 *STA_Build_AMSDU_Frame_Header(struct rt_rtmp_adapter *pAd,
- struct rt_tx_blk *pTxBlk)
-{
- u8 *pHeaderBufPtr; /*, pSaveBufPtr; */
- struct rt_header_802_11 *pHeader_802_11;
-
- STAFindCipherAlgorithm(pAd, pTxBlk);
- STABuildCommon802_11Header(pAd, pTxBlk);
-
- pHeaderBufPtr = &pTxBlk->HeaderBuf[TXINFO_SIZE + TXWI_SIZE];
- pHeader_802_11 = (struct rt_header_802_11 *) pHeaderBufPtr;
-
- /* skip common header */
- pHeaderBufPtr += pTxBlk->MpduHeaderLen;
-
- /* */
- /* build QOS Control bytes */
- /* */
- *pHeaderBufPtr = (pTxBlk->UserPriority & 0x0F);
-
- /* */
- /* A-MSDU packet */
- /* */
- *pHeaderBufPtr |= 0x80;
-
- *(pHeaderBufPtr + 1) = 0;
- pHeaderBufPtr += 2;
- pTxBlk->MpduHeaderLen += 2;
-
- /*pSaveBufPtr = pHeaderBufPtr; */
-
- /* */
- /* padding at front of LLC header */
- /* LLC header should locate at 4-octets aligment */
- /* */
- /* @@@ MpduHeaderLen excluding padding @@@ */
- /* */
- pTxBlk->HdrPadLen = (unsigned long)pHeaderBufPtr;
- pHeaderBufPtr = (u8 *)ROUND_UP(pHeaderBufPtr, 4);
- pTxBlk->HdrPadLen = (unsigned long)(pHeaderBufPtr - pTxBlk->HdrPadLen);
-
- return pHeaderBufPtr;
-
-}
-
-void STA_AMPDU_Frame_Tx(struct rt_rtmp_adapter *pAd, struct rt_tx_blk *pTxBlk)
-{
- struct rt_header_802_11 *pHeader_802_11;
- u8 *pHeaderBufPtr;
- u16 FreeNumber;
- struct rt_mac_table_entry *pMacEntry;
- BOOLEAN bVLANPkt;
- struct rt_queue_entry *pQEntry;
-
- ASSERT(pTxBlk);
-
- while (pTxBlk->TxPacketList.Head) {
- pQEntry = RemoveHeadQueue(&pTxBlk->TxPacketList);
- pTxBlk->pPacket = QUEUE_ENTRY_TO_PACKET(pQEntry);
- if (RTMP_FillTxBlkInfo(pAd, pTxBlk) != TRUE) {
- RELEASE_NDIS_PACKET(pAd, pTxBlk->pPacket,
- NDIS_STATUS_FAILURE);
- continue;
- }
-
- bVLANPkt =
- (RTMP_GET_PACKET_VLAN(pTxBlk->pPacket) ? TRUE : FALSE);
-
- pMacEntry = pTxBlk->pMacEntry;
- if (pMacEntry->isCached) {
- /* NOTE: Please make sure the size of pMacEntry->CachedBuf[] is smaller than pTxBlk->HeaderBuf[]! */
- NdisMoveMemory((u8 *)& pTxBlk->
- HeaderBuf[TXINFO_SIZE],
- (u8 *)& pMacEntry->CachedBuf[0],
- TXWI_SIZE + sizeof(struct rt_header_802_11));
- pHeaderBufPtr =
- (u8 *)(&pTxBlk->
- HeaderBuf[TXINFO_SIZE + TXWI_SIZE]);
- STABuildCache802_11Header(pAd, pTxBlk, pHeaderBufPtr);
- } else {
- STAFindCipherAlgorithm(pAd, pTxBlk);
- STABuildCommon802_11Header(pAd, pTxBlk);
-
- pHeaderBufPtr =
- &pTxBlk->HeaderBuf[TXINFO_SIZE + TXWI_SIZE];
- }
-
- pHeader_802_11 = (struct rt_header_802_11 *) pHeaderBufPtr;
-
- /* skip common header */
- pHeaderBufPtr += pTxBlk->MpduHeaderLen;
-
- /* */
- /* build QOS Control bytes */
- /* */
- *pHeaderBufPtr = (pTxBlk->UserPriority & 0x0F);
- *(pHeaderBufPtr + 1) = 0;
- pHeaderBufPtr += 2;
- pTxBlk->MpduHeaderLen += 2;
-
- /* */
- /* build HTC+ */
- /* HTC control filed following QoS field */
- /* */
- if ((pAd->CommonCfg.bRdg == TRUE)
- && CLIENT_STATUS_TEST_FLAG(pTxBlk->pMacEntry,
- fCLIENT_STATUS_RDG_CAPABLE)) {
- if (pMacEntry->isCached == FALSE) {
- /* mark HTC bit */
- pHeader_802_11->FC.Order = 1;
-
- NdisZeroMemory(pHeaderBufPtr, 4);
- *(pHeaderBufPtr + 3) |= 0x80;
- }
- pHeaderBufPtr += 4;
- pTxBlk->MpduHeaderLen += 4;
- }
- /*pTxBlk->MpduHeaderLen = pHeaderBufPtr - pTxBlk->HeaderBuf - TXWI_SIZE - TXINFO_SIZE; */
- ASSERT(pTxBlk->MpduHeaderLen >= 24);
-
- /* skip 802.3 header */
- pTxBlk->pSrcBufData = pTxBlk->pSrcBufHeader + LENGTH_802_3;
- pTxBlk->SrcBufLen -= LENGTH_802_3;
-
- /* skip vlan tag */
- if (bVLANPkt) {
- pTxBlk->pSrcBufData += LENGTH_802_1Q;
- pTxBlk->SrcBufLen -= LENGTH_802_1Q;
- }
- /* */
- /* padding at front of LLC header */
- /* LLC header should locate at 4-octets aligment */
- /* */
- /* @@@ MpduHeaderLen excluding padding @@@ */
- /* */
- pTxBlk->HdrPadLen = (unsigned long)pHeaderBufPtr;
- pHeaderBufPtr = (u8 *)ROUND_UP(pHeaderBufPtr, 4);
- pTxBlk->HdrPadLen = (unsigned long)(pHeaderBufPtr - pTxBlk->HdrPadLen);
-
- {
-
- /* */
- /* Insert LLC-SNAP encapsulation - 8 octets */
- /* */
- EXTRA_LLCSNAP_ENCAP_FROM_PKT_OFFSET(pTxBlk->
- pSrcBufData - 2,
- pTxBlk->
- pExtraLlcSnapEncap);
- if (pTxBlk->pExtraLlcSnapEncap) {
- NdisMoveMemory(pHeaderBufPtr,
- pTxBlk->pExtraLlcSnapEncap, 6);
- pHeaderBufPtr += 6;
- /* get 2 octets (TypeofLen) */
- NdisMoveMemory(pHeaderBufPtr,
- pTxBlk->pSrcBufData - 2, 2);
- pHeaderBufPtr += 2;
- pTxBlk->MpduHeaderLen += LENGTH_802_1_H;
- }
-
- }
-
- if (pMacEntry->isCached) {
- RTMPWriteTxWI_Cache(pAd,
- (struct rt_txwi *) (&pTxBlk->
- HeaderBuf
- [TXINFO_SIZE]),
- pTxBlk);
- } else {
- RTMPWriteTxWI_Data(pAd,
- (struct rt_txwi *) (&pTxBlk->
- HeaderBuf
- [TXINFO_SIZE]),
- pTxBlk);
-
- NdisZeroMemory((u8 *)(&pMacEntry->CachedBuf[0]),
- sizeof(pMacEntry->CachedBuf));
- NdisMoveMemory((u8 *)(&pMacEntry->CachedBuf[0]),
- (u8 *)(&pTxBlk->
- HeaderBuf[TXINFO_SIZE]),
- (pHeaderBufPtr -
- (u8 *)(&pTxBlk->
- HeaderBuf[TXINFO_SIZE])));
- pMacEntry->isCached = TRUE;
- }
-
- /* calculate Transmitted AMPDU count and ByteCount */
- {
- pAd->RalinkCounters.TransmittedMPDUsInAMPDUCount.u.
- LowPart++;
- pAd->RalinkCounters.TransmittedOctetsInAMPDUCount.
- QuadPart += pTxBlk->SrcBufLen;
- }
-
- /*FreeNumber = GET_TXRING_FREENO(pAd, QueIdx); */
-
- HAL_WriteTxResource(pAd, pTxBlk, TRUE, &FreeNumber);
-
- /* */
- /* Kick out Tx */
- /* */
- if (!RTMP_TEST_PSFLAG(pAd, fRTMP_PS_DISABLE_TX))
- HAL_KickOutTx(pAd, pTxBlk, pTxBlk->QueIdx);
-
- pAd->RalinkCounters.KickTxCount++;
- pAd->RalinkCounters.OneSecTxDoneCount++;
- }
-
-}
-
-void STA_AMSDU_Frame_Tx(struct rt_rtmp_adapter *pAd, struct rt_tx_blk *pTxBlk)
-{
- u8 *pHeaderBufPtr;
- u16 FreeNumber;
- u16 subFramePayloadLen = 0; /* AMSDU Subframe length without AMSDU-Header / Padding. */
- u16 totalMPDUSize = 0;
- u8 *subFrameHeader;
- u8 padding = 0;
- u16 FirstTx = 0, LastTxIdx = 0;
- BOOLEAN bVLANPkt;
- int frameNum = 0;
- struct rt_queue_entry *pQEntry;
-
- ASSERT(pTxBlk);
-
- ASSERT((pTxBlk->TxPacketList.Number > 1));
-
- while (pTxBlk->TxPacketList.Head) {
- pQEntry = RemoveHeadQueue(&pTxBlk->TxPacketList);
- pTxBlk->pPacket = QUEUE_ENTRY_TO_PACKET(pQEntry);
- if (RTMP_FillTxBlkInfo(pAd, pTxBlk) != TRUE) {
- RELEASE_NDIS_PACKET(pAd, pTxBlk->pPacket,
- NDIS_STATUS_FAILURE);
- continue;
- }
-
- bVLANPkt =
- (RTMP_GET_PACKET_VLAN(pTxBlk->pPacket) ? TRUE : FALSE);
-
- /* skip 802.3 header */
- pTxBlk->pSrcBufData = pTxBlk->pSrcBufHeader + LENGTH_802_3;
- pTxBlk->SrcBufLen -= LENGTH_802_3;
-
- /* skip vlan tag */
- if (bVLANPkt) {
- pTxBlk->pSrcBufData += LENGTH_802_1Q;
- pTxBlk->SrcBufLen -= LENGTH_802_1Q;
- }
-
- if (frameNum == 0) {
- pHeaderBufPtr =
- STA_Build_AMSDU_Frame_Header(pAd, pTxBlk);
-
- /* NOTE: TxWI->MPDUtotalByteCount will be updated after final frame was handled. */
- RTMPWriteTxWI_Data(pAd,
- (struct rt_txwi *) (&pTxBlk->
- HeaderBuf
- [TXINFO_SIZE]),
- pTxBlk);
- } else {
- pHeaderBufPtr = &pTxBlk->HeaderBuf[0];
- padding =
- ROUND_UP(LENGTH_AMSDU_SUBFRAMEHEAD +
- subFramePayloadLen,
- 4) - (LENGTH_AMSDU_SUBFRAMEHEAD +
- subFramePayloadLen);
- NdisZeroMemory(pHeaderBufPtr,
- padding + LENGTH_AMSDU_SUBFRAMEHEAD);
- pHeaderBufPtr += padding;
- pTxBlk->MpduHeaderLen = padding;
- }
-
- /* */
- /* A-MSDU subframe */
- /* DA(6)+SA(6)+Length(2) + LLC/SNAP Encap */
- /* */
- subFrameHeader = pHeaderBufPtr;
- subFramePayloadLen = pTxBlk->SrcBufLen;
-
- NdisMoveMemory(subFrameHeader, pTxBlk->pSrcBufHeader, 12);
-
- pHeaderBufPtr += LENGTH_AMSDU_SUBFRAMEHEAD;
- pTxBlk->MpduHeaderLen += LENGTH_AMSDU_SUBFRAMEHEAD;
-
- /* */
- /* Insert LLC-SNAP encapsulation - 8 octets */
- /* */
- EXTRA_LLCSNAP_ENCAP_FROM_PKT_OFFSET(pTxBlk->pSrcBufData - 2,
- pTxBlk->pExtraLlcSnapEncap);
-
- subFramePayloadLen = pTxBlk->SrcBufLen;
-
- if (pTxBlk->pExtraLlcSnapEncap) {
- NdisMoveMemory(pHeaderBufPtr,
- pTxBlk->pExtraLlcSnapEncap, 6);
- pHeaderBufPtr += 6;
- /* get 2 octets (TypeofLen) */
- NdisMoveMemory(pHeaderBufPtr, pTxBlk->pSrcBufData - 2,
- 2);
- pHeaderBufPtr += 2;
- pTxBlk->MpduHeaderLen += LENGTH_802_1_H;
- subFramePayloadLen += LENGTH_802_1_H;
- }
- /* update subFrame Length field */
- subFrameHeader[12] = (subFramePayloadLen & 0xFF00) >> 8;
- subFrameHeader[13] = subFramePayloadLen & 0xFF;
-
- totalMPDUSize += pTxBlk->MpduHeaderLen + pTxBlk->SrcBufLen;
-
- if (frameNum == 0)
- FirstTx =
- HAL_WriteMultiTxResource(pAd, pTxBlk, frameNum,
- &FreeNumber);
- else
- LastTxIdx =
- HAL_WriteMultiTxResource(pAd, pTxBlk, frameNum,
- &FreeNumber);
-
- frameNum++;
-
- pAd->RalinkCounters.KickTxCount++;
- pAd->RalinkCounters.OneSecTxDoneCount++;
-
- /* calculate Transmitted AMSDU Count and ByteCount */
- {
- pAd->RalinkCounters.TransmittedAMSDUCount.u.LowPart++;
- pAd->RalinkCounters.TransmittedOctetsInAMSDU.QuadPart +=
- totalMPDUSize;
- }
-
- }
-
- HAL_FinalWriteTxResource(pAd, pTxBlk, totalMPDUSize, FirstTx);
- HAL_LastTxIdx(pAd, pTxBlk->QueIdx, LastTxIdx);
-
- /* */
- /* Kick out Tx */
- /* */
- if (!RTMP_TEST_PSFLAG(pAd, fRTMP_PS_DISABLE_TX))
- HAL_KickOutTx(pAd, pTxBlk, pTxBlk->QueIdx);
-}
-
-void STA_Legacy_Frame_Tx(struct rt_rtmp_adapter *pAd, struct rt_tx_blk *pTxBlk)
-{
- struct rt_header_802_11 *pHeader_802_11;
- u8 *pHeaderBufPtr;
- u16 FreeNumber;
- BOOLEAN bVLANPkt;
- struct rt_queue_entry *pQEntry;
-
- ASSERT(pTxBlk);
-
- pQEntry = RemoveHeadQueue(&pTxBlk->TxPacketList);
- pTxBlk->pPacket = QUEUE_ENTRY_TO_PACKET(pQEntry);
- if (RTMP_FillTxBlkInfo(pAd, pTxBlk) != TRUE) {
- RELEASE_NDIS_PACKET(pAd, pTxBlk->pPacket, NDIS_STATUS_FAILURE);
- return;
- }
-
- if (pTxBlk->TxFrameType == TX_MCAST_FRAME) {
- INC_COUNTER64(pAd->WlanCounters.MulticastTransmittedFrameCount);
- }
-
- if (RTMP_GET_PACKET_RTS(pTxBlk->pPacket))
- TX_BLK_SET_FLAG(pTxBlk, fTX_bRtsRequired);
- else
- TX_BLK_CLEAR_FLAG(pTxBlk, fTX_bRtsRequired);
-
- bVLANPkt = (RTMP_GET_PACKET_VLAN(pTxBlk->pPacket) ? TRUE : FALSE);
-
- if (pTxBlk->TxRate < pAd->CommonCfg.MinTxRate)
- pTxBlk->TxRate = pAd->CommonCfg.MinTxRate;
-
- STAFindCipherAlgorithm(pAd, pTxBlk);
- STABuildCommon802_11Header(pAd, pTxBlk);
-
- /* skip 802.3 header */
- pTxBlk->pSrcBufData = pTxBlk->pSrcBufHeader + LENGTH_802_3;
- pTxBlk->SrcBufLen -= LENGTH_802_3;
-
- /* skip vlan tag */
- if (bVLANPkt) {
- pTxBlk->pSrcBufData += LENGTH_802_1Q;
- pTxBlk->SrcBufLen -= LENGTH_802_1Q;
- }
-
- pHeaderBufPtr = &pTxBlk->HeaderBuf[TXINFO_SIZE + TXWI_SIZE];
- pHeader_802_11 = (struct rt_header_802_11 *) pHeaderBufPtr;
-
- /* skip common header */
- pHeaderBufPtr += pTxBlk->MpduHeaderLen;
-
- if (TX_BLK_TEST_FLAG(pTxBlk, fTX_bWMM)) {
- /* */
- /* build QOS Control bytes */
- /* */
- *(pHeaderBufPtr) =
- ((pTxBlk->UserPriority & 0x0F) | (pAd->CommonCfg.
- AckPolicy[pTxBlk->
- QueIdx] << 5));
- *(pHeaderBufPtr + 1) = 0;
- pHeaderBufPtr += 2;
- pTxBlk->MpduHeaderLen += 2;
- }
- /* The remaining content of MPDU header should locate at 4-octets alignment */
- pTxBlk->HdrPadLen = (unsigned long)pHeaderBufPtr;
- pHeaderBufPtr = (u8 *)ROUND_UP(pHeaderBufPtr, 4);
- pTxBlk->HdrPadLen = (unsigned long)(pHeaderBufPtr - pTxBlk->HdrPadLen);
-
- {
-
- /* */
- /* Insert LLC-SNAP encapsulation - 8 octets */
- /* */
- /* */
- /* if original Ethernet frame contains no LLC/SNAP, */
- /* then an extra LLC/SNAP encap is required */
- /* */
- EXTRA_LLCSNAP_ENCAP_FROM_PKT_START(pTxBlk->pSrcBufHeader,
- pTxBlk->pExtraLlcSnapEncap);
- if (pTxBlk->pExtraLlcSnapEncap) {
- u8 vlan_size;
-
- NdisMoveMemory(pHeaderBufPtr,
- pTxBlk->pExtraLlcSnapEncap, 6);
- pHeaderBufPtr += 6;
- /* skip vlan tag */
- vlan_size = (bVLANPkt) ? LENGTH_802_1Q : 0;
- /* get 2 octets (TypeofLen) */
- NdisMoveMemory(pHeaderBufPtr,
- pTxBlk->pSrcBufHeader + 12 + vlan_size,
- 2);
- pHeaderBufPtr += 2;
- pTxBlk->MpduHeaderLen += LENGTH_802_1_H;
- }
-
- }
-
- /* */
- /* prepare for TXWI */
- /* use Wcid as Key Index */
- /* */
-
- RTMPWriteTxWI_Data(pAd, (struct rt_txwi *) (&pTxBlk->HeaderBuf[TXINFO_SIZE]),
- pTxBlk);
-
- /*FreeNumber = GET_TXRING_FREENO(pAd, QueIdx); */
-
- HAL_WriteTxResource(pAd, pTxBlk, TRUE, &FreeNumber);
-
- pAd->RalinkCounters.KickTxCount++;
- pAd->RalinkCounters.OneSecTxDoneCount++;
-
- /* */
- /* Kick out Tx */
- /* */
- if (!RTMP_TEST_PSFLAG(pAd, fRTMP_PS_DISABLE_TX))
- HAL_KickOutTx(pAd, pTxBlk, pTxBlk->QueIdx);
-}
-
-void STA_ARalink_Frame_Tx(struct rt_rtmp_adapter *pAd, struct rt_tx_blk *pTxBlk)
-{
- u8 *pHeaderBufPtr;
- u16 FreeNumber;
- u16 totalMPDUSize = 0;
- u16 FirstTx, LastTxIdx;
- int frameNum = 0;
- BOOLEAN bVLANPkt;
- struct rt_queue_entry *pQEntry;
-
- ASSERT(pTxBlk);
-
- ASSERT((pTxBlk->TxPacketList.Number == 2));
-
- FirstTx = LastTxIdx = 0; /* Is it ok init they as 0? */
- while (pTxBlk->TxPacketList.Head) {
- pQEntry = RemoveHeadQueue(&pTxBlk->TxPacketList);
- pTxBlk->pPacket = QUEUE_ENTRY_TO_PACKET(pQEntry);
-
- if (RTMP_FillTxBlkInfo(pAd, pTxBlk) != TRUE) {
- RELEASE_NDIS_PACKET(pAd, pTxBlk->pPacket,
- NDIS_STATUS_FAILURE);
- continue;
- }
-
- bVLANPkt =
- (RTMP_GET_PACKET_VLAN(pTxBlk->pPacket) ? TRUE : FALSE);
-
- /* skip 802.3 header */
- pTxBlk->pSrcBufData = pTxBlk->pSrcBufHeader + LENGTH_802_3;
- pTxBlk->SrcBufLen -= LENGTH_802_3;
-
- /* skip vlan tag */
- if (bVLANPkt) {
- pTxBlk->pSrcBufData += LENGTH_802_1Q;
- pTxBlk->SrcBufLen -= LENGTH_802_1Q;
- }
-
- if (frameNum == 0) { /* For first frame, we need to create the 802.11 header + padding(optional) + RA-AGG-LEN + SNAP Header */
-
- pHeaderBufPtr =
- STA_Build_ARalink_Frame_Header(pAd, pTxBlk);
-
- /* It's ok write the TxWI here, because the TxWI->MPDUtotalByteCount */
- /* will be updated after final frame was handled. */
- RTMPWriteTxWI_Data(pAd,
- (struct rt_txwi *) (&pTxBlk->
- HeaderBuf
- [TXINFO_SIZE]),
- pTxBlk);
-
- /* */
- /* Insert LLC-SNAP encapsulation - 8 octets */
- /* */
- EXTRA_LLCSNAP_ENCAP_FROM_PKT_OFFSET(pTxBlk->
- pSrcBufData - 2,
- pTxBlk->
- pExtraLlcSnapEncap);
-
- if (pTxBlk->pExtraLlcSnapEncap) {
- NdisMoveMemory(pHeaderBufPtr,
- pTxBlk->pExtraLlcSnapEncap, 6);
- pHeaderBufPtr += 6;
- /* get 2 octets (TypeofLen) */
- NdisMoveMemory(pHeaderBufPtr,
- pTxBlk->pSrcBufData - 2, 2);
- pHeaderBufPtr += 2;
- pTxBlk->MpduHeaderLen += LENGTH_802_1_H;
- }
- } else { /* For second aggregated frame, we need create the 802.3 header to headerBuf, because PCI will copy it to SDPtr0. */
-
- pHeaderBufPtr = &pTxBlk->HeaderBuf[0];
- pTxBlk->MpduHeaderLen = 0;
-
- /* A-Ralink sub-sequent frame header is the same as 802.3 header. */
- /* DA(6)+SA(6)+FrameType(2) */
- NdisMoveMemory(pHeaderBufPtr, pTxBlk->pSrcBufHeader,
- 12);
- pHeaderBufPtr += 12;
- /* get 2 octets (TypeofLen) */
- NdisMoveMemory(pHeaderBufPtr, pTxBlk->pSrcBufData - 2,
- 2);
- pHeaderBufPtr += 2;
- pTxBlk->MpduHeaderLen = LENGTH_ARALINK_SUBFRAMEHEAD;
- }
-
- totalMPDUSize += pTxBlk->MpduHeaderLen + pTxBlk->SrcBufLen;
-
- /*FreeNumber = GET_TXRING_FREENO(pAd, QueIdx); */
- if (frameNum == 0)
- FirstTx =
- HAL_WriteMultiTxResource(pAd, pTxBlk, frameNum,
- &FreeNumber);
- else
- LastTxIdx =
- HAL_WriteMultiTxResource(pAd, pTxBlk, frameNum,
- &FreeNumber);
-
- frameNum++;
-
- pAd->RalinkCounters.OneSecTxAggregationCount++;
- pAd->RalinkCounters.KickTxCount++;
- pAd->RalinkCounters.OneSecTxDoneCount++;
-
- }
-
- HAL_FinalWriteTxResource(pAd, pTxBlk, totalMPDUSize, FirstTx);
- HAL_LastTxIdx(pAd, pTxBlk->QueIdx, LastTxIdx);
-
- /* */
- /* Kick out Tx */
- /* */
- if (!RTMP_TEST_PSFLAG(pAd, fRTMP_PS_DISABLE_TX))
- HAL_KickOutTx(pAd, pTxBlk, pTxBlk->QueIdx);
-
-}
-
-void STA_Fragment_Frame_Tx(struct rt_rtmp_adapter *pAd, struct rt_tx_blk *pTxBlk)
-{
- struct rt_header_802_11 *pHeader_802_11;
- u8 *pHeaderBufPtr;
- u16 FreeNumber;
- u8 fragNum = 0;
- struct rt_packet_info PacketInfo;
- u16 EncryptionOverhead = 0;
- u32 FreeMpduSize, SrcRemainingBytes;
- u16 AckDuration;
- u32 NextMpduSize;
- BOOLEAN bVLANPkt;
- struct rt_queue_entry *pQEntry;
- HTTRANSMIT_SETTING *pTransmit;
-
- ASSERT(pTxBlk);
-
- pQEntry = RemoveHeadQueue(&pTxBlk->TxPacketList);
- pTxBlk->pPacket = QUEUE_ENTRY_TO_PACKET(pQEntry);
- if (RTMP_FillTxBlkInfo(pAd, pTxBlk) != TRUE) {
- RELEASE_NDIS_PACKET(pAd, pTxBlk->pPacket, NDIS_STATUS_FAILURE);
- return;
- }
-
- ASSERT(TX_BLK_TEST_FLAG(pTxBlk, fTX_bAllowFrag));
- bVLANPkt = (RTMP_GET_PACKET_VLAN(pTxBlk->pPacket) ? TRUE : FALSE);
-
- STAFindCipherAlgorithm(pAd, pTxBlk);
- STABuildCommon802_11Header(pAd, pTxBlk);
-
- if (pTxBlk->CipherAlg == CIPHER_TKIP) {
- pTxBlk->pPacket =
- duplicate_pkt_with_TKIP_MIC(pAd, pTxBlk->pPacket);
- if (pTxBlk->pPacket == NULL)
- return;
- RTMP_QueryPacketInfo(pTxBlk->pPacket, &PacketInfo,
- &pTxBlk->pSrcBufHeader,
- &pTxBlk->SrcBufLen);
- }
- /* skip 802.3 header */
- pTxBlk->pSrcBufData = pTxBlk->pSrcBufHeader + LENGTH_802_3;
- pTxBlk->SrcBufLen -= LENGTH_802_3;
-
- /* skip vlan tag */
- if (bVLANPkt) {
- pTxBlk->pSrcBufData += LENGTH_802_1Q;
- pTxBlk->SrcBufLen -= LENGTH_802_1Q;
- }
-
- pHeaderBufPtr = &pTxBlk->HeaderBuf[TXINFO_SIZE + TXWI_SIZE];
- pHeader_802_11 = (struct rt_header_802_11 *) pHeaderBufPtr;
-
- /* skip common header */
- pHeaderBufPtr += pTxBlk->MpduHeaderLen;
-
- if (TX_BLK_TEST_FLAG(pTxBlk, fTX_bWMM)) {
- /* */
- /* build QOS Control bytes */
- /* */
- *pHeaderBufPtr = (pTxBlk->UserPriority & 0x0F);
-
- *(pHeaderBufPtr + 1) = 0;
- pHeaderBufPtr += 2;
- pTxBlk->MpduHeaderLen += 2;
- }
- /* */
- /* padding at front of LLC header */
- /* LLC header should locate at 4-octets aligment */
- /* */
- pTxBlk->HdrPadLen = (unsigned long)pHeaderBufPtr;
- pHeaderBufPtr = (u8 *)ROUND_UP(pHeaderBufPtr, 4);
- pTxBlk->HdrPadLen = (unsigned long)(pHeaderBufPtr - pTxBlk->HdrPadLen);
-
- /* */
- /* Insert LLC-SNAP encapsulation - 8 octets */
- /* */
- /* */
- /* if original Ethernet frame contains no LLC/SNAP, */
- /* then an extra LLC/SNAP encap is required */
- /* */
- EXTRA_LLCSNAP_ENCAP_FROM_PKT_START(pTxBlk->pSrcBufHeader,
- pTxBlk->pExtraLlcSnapEncap);
- if (pTxBlk->pExtraLlcSnapEncap) {
- u8 vlan_size;
-
- NdisMoveMemory(pHeaderBufPtr, pTxBlk->pExtraLlcSnapEncap, 6);
- pHeaderBufPtr += 6;
- /* skip vlan tag */
- vlan_size = (bVLANPkt) ? LENGTH_802_1Q : 0;
- /* get 2 octets (TypeofLen) */
- NdisMoveMemory(pHeaderBufPtr,
- pTxBlk->pSrcBufHeader + 12 + vlan_size, 2);
- pHeaderBufPtr += 2;
- pTxBlk->MpduHeaderLen += LENGTH_802_1_H;
- }
-
- /* If TKIP is used and fragmentation is required. Driver has to */
- /* append TKIP MIC at tail of the scatter buffer */
- /* MAC ASIC will only perform IV/EIV/ICV insertion but no TKIP MIC */
- if (pTxBlk->CipherAlg == CIPHER_TKIP) {
- RTMPCalculateMICValue(pAd, pTxBlk->pPacket,
- pTxBlk->pExtraLlcSnapEncap, pTxBlk->pKey,
- 0);
-
- /* NOTE: DON'T refer the skb->len directly after following copy. Because the length is not adjusted */
- /* to correct length, refer to pTxBlk->SrcBufLen for the packet length in following progress. */
- NdisMoveMemory(pTxBlk->pSrcBufData + pTxBlk->SrcBufLen,
- &pAd->PrivateInfo.Tx.MIC[0], 8);
- /*skb_put((RTPKT_TO_OSPKT(pTxBlk->pPacket))->tail, 8); */
- pTxBlk->SrcBufLen += 8;
- pTxBlk->TotalFrameLen += 8;
- pTxBlk->CipherAlg = CIPHER_TKIP_NO_MIC;
- }
- /* */
- /* calculate the overhead bytes that encryption algorithm may add. This */
- /* affects the calculate of "duration" field */
- /* */
- if ((pTxBlk->CipherAlg == CIPHER_WEP64)
- || (pTxBlk->CipherAlg == CIPHER_WEP128))
- EncryptionOverhead = 8; /*WEP: IV[4] + ICV[4]; */
- else if (pTxBlk->CipherAlg == CIPHER_TKIP_NO_MIC)
- EncryptionOverhead = 12; /*TKIP: IV[4] + EIV[4] + ICV[4], MIC will be added to TotalPacketLength */
- else if (pTxBlk->CipherAlg == CIPHER_TKIP)
- EncryptionOverhead = 20; /*TKIP: IV[4] + EIV[4] + ICV[4] + MIC[8] */
- else if (pTxBlk->CipherAlg == CIPHER_AES)
- EncryptionOverhead = 16; /* AES: IV[4] + EIV[4] + MIC[8] */
- else
- EncryptionOverhead = 0;
-
- pTransmit = pTxBlk->pTransmit;
- /* Decide the TX rate */
- if (pTransmit->field.MODE == MODE_CCK)
- pTxBlk->TxRate = pTransmit->field.MCS;
- else if (pTransmit->field.MODE == MODE_OFDM)
- pTxBlk->TxRate = pTransmit->field.MCS + RATE_FIRST_OFDM_RATE;
- else
- pTxBlk->TxRate = RATE_6_5;
-
- /* decide how much time an ACK/CTS frame will consume in the air */
- if (pTxBlk->TxRate <= RATE_LAST_OFDM_RATE)
- AckDuration =
- RTMPCalcDuration(pAd,
- pAd->CommonCfg.ExpectedACKRate[pTxBlk->
- TxRate],
- 14);
- else
- AckDuration = RTMPCalcDuration(pAd, RATE_6_5, 14);
-
- /* Init the total payload length of this frame. */
- SrcRemainingBytes = pTxBlk->SrcBufLen;
-
- pTxBlk->TotalFragNum = 0xff;
-
- do {
-
- FreeMpduSize = pAd->CommonCfg.FragmentThreshold - LENGTH_CRC;
-
- FreeMpduSize -= pTxBlk->MpduHeaderLen;
-
- if (SrcRemainingBytes <= FreeMpduSize) { /* this is the last or only fragment */
-
- pTxBlk->SrcBufLen = SrcRemainingBytes;
-
- pHeader_802_11->FC.MoreFrag = 0;
- pHeader_802_11->Duration =
- pAd->CommonCfg.Dsifs + AckDuration;
-
- /* Indicate the lower layer that this's the last fragment. */
- pTxBlk->TotalFragNum = fragNum;
- } else { /* more fragment is required */
-
- pTxBlk->SrcBufLen = FreeMpduSize;
-
- NextMpduSize =
- min(((u32)SrcRemainingBytes - pTxBlk->SrcBufLen),
- ((u32)pAd->CommonCfg.FragmentThreshold));
- pHeader_802_11->FC.MoreFrag = 1;
- pHeader_802_11->Duration =
- (3 * pAd->CommonCfg.Dsifs) + (2 * AckDuration) +
- RTMPCalcDuration(pAd, pTxBlk->TxRate,
- NextMpduSize + EncryptionOverhead);
- }
-
- if (fragNum == 0)
- pTxBlk->FrameGap = IFS_HTTXOP;
- else
- pTxBlk->FrameGap = IFS_SIFS;
-
- RTMPWriteTxWI_Data(pAd,
- (struct rt_txwi *) (&pTxBlk->
- HeaderBuf[TXINFO_SIZE]),
- pTxBlk);
-
- HAL_WriteFragTxResource(pAd, pTxBlk, fragNum, &FreeNumber);
-
- pAd->RalinkCounters.KickTxCount++;
- pAd->RalinkCounters.OneSecTxDoneCount++;
-
- /* Update the frame number, remaining size of the NDIS packet payload. */
-
- /* space for 802.11 header. */
- if (fragNum == 0 && pTxBlk->pExtraLlcSnapEncap)
- pTxBlk->MpduHeaderLen -= LENGTH_802_1_H;
-
- fragNum++;
- SrcRemainingBytes -= pTxBlk->SrcBufLen;
- pTxBlk->pSrcBufData += pTxBlk->SrcBufLen;
-
- pHeader_802_11->Frag++; /* increase Frag # */
-
- } while (SrcRemainingBytes > 0);
-
- /* */
- /* Kick out Tx */
- /* */
- if (!RTMP_TEST_PSFLAG(pAd, fRTMP_PS_DISABLE_TX))
- HAL_KickOutTx(pAd, pTxBlk, pTxBlk->QueIdx);
-}
-
-#define RELEASE_FRAMES_OF_TXBLK(_pAd, _pTxBlk, _pQEntry, _Status) \
- while(_pTxBlk->TxPacketList.Head) \
- { \
- _pQEntry = RemoveHeadQueue(&_pTxBlk->TxPacketList); \
- RELEASE_NDIS_PACKET(_pAd, QUEUE_ENTRY_TO_PACKET(_pQEntry), _Status); \
- }
-
-/*
- ========================================================================
-
- Routine Description:
- Copy frame from waiting queue into relative ring buffer and set
- appropriate ASIC register to kick hardware encryption before really
- sent out to air.
-
- Arguments:
- pAd Pointer to our adapter
- void * Pointer to outgoing Ndis frame
- NumberOfFrag Number of fragment required
-
- Return Value:
- None
-
- IRQL = DISPATCH_LEVEL
-
- Note:
-
- ========================================================================
-*/
-int STAHardTransmit(struct rt_rtmp_adapter *pAd,
- struct rt_tx_blk *pTxBlk, u8 QueIdx)
-{
- char *pPacket;
- struct rt_queue_entry *pQEntry;
-
- /* --------------------------------------------- */
- /* STEP 0. DO SANITY CHECK AND SOME EARLY PREPARATION. */
- /* --------------------------------------------- */
- /* */
- ASSERT(pTxBlk->TxPacketList.Number);
- if (pTxBlk->TxPacketList.Head == NULL) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("pTxBlk->TotalFrameNum == %ld!\n",
- pTxBlk->TxPacketList.Number));
- return NDIS_STATUS_FAILURE;
- }
-
- pPacket = QUEUE_ENTRY_TO_PACKET(pTxBlk->TxPacketList.Head);
-
- /* ------------------------------------------------------------------ */
- /* STEP 1. WAKE UP PHY */
- /* outgoing frame always wakeup PHY to prevent frame lost and */
- /* turn off PSM bit to improve performance */
- /* ------------------------------------------------------------------ */
- /* not to change PSM bit, just send this frame out? */
- if ((pAd->StaCfg.Psm == PWR_SAVE)
- && OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_DOZE)) {
- DBGPRINT_RAW(RT_DEBUG_INFO, ("AsicForceWakeup At HardTx\n"));
-#ifdef RTMP_MAC_PCI
- AsicForceWakeup(pAd, TRUE);
-#endif /* RTMP_MAC_PCI // */
-#ifdef RTMP_MAC_USB
- RTUSBEnqueueInternalCmd(pAd, CMDTHREAD_FORCE_WAKE_UP, NULL, 0);
-#endif /* RTMP_MAC_USB // */
- }
- /* It should not change PSM bit, when APSD turn on. */
- if ((!
- (pAd->CommonCfg.bAPSDCapable
- && pAd->CommonCfg.APEdcaParm.bAPSDCapable)
- && (pAd->CommonCfg.bAPSDForcePowerSave == FALSE))
- || (RTMP_GET_PACKET_EAPOL(pTxBlk->pPacket))
- || (RTMP_GET_PACKET_WAI(pTxBlk->pPacket))) {
- if ((pAd->StaCfg.Psm == PWR_SAVE) &&
- (pAd->StaCfg.WindowsPowerMode ==
- Ndis802_11PowerModeFast_PSP))
- RTMP_SET_PSM_BIT(pAd, PWR_ACTIVE);
- }
-
- switch (pTxBlk->TxFrameType) {
- case TX_AMPDU_FRAME:
- STA_AMPDU_Frame_Tx(pAd, pTxBlk);
- break;
- case TX_AMSDU_FRAME:
- STA_AMSDU_Frame_Tx(pAd, pTxBlk);
- break;
- case TX_LEGACY_FRAME:
- STA_Legacy_Frame_Tx(pAd, pTxBlk);
- break;
- case TX_MCAST_FRAME:
- STA_Legacy_Frame_Tx(pAd, pTxBlk);
- break;
- case TX_RALINK_FRAME:
- STA_ARalink_Frame_Tx(pAd, pTxBlk);
- break;
- case TX_FRAG_FRAME:
- STA_Fragment_Frame_Tx(pAd, pTxBlk);
- break;
- default:
- {
- /* It should not happened! */
- DBGPRINT(RT_DEBUG_ERROR,
- ("Send a packet was not classified! It should not happen!\n"));
- while (pTxBlk->TxPacketList.Number) {
- pQEntry =
- RemoveHeadQueue(&pTxBlk->TxPacketList);
- pPacket = QUEUE_ENTRY_TO_PACKET(pQEntry);
- if (pPacket)
- RELEASE_NDIS_PACKET(pAd, pPacket,
- NDIS_STATUS_FAILURE);
- }
- }
- break;
- }
-
- return (NDIS_STATUS_SUCCESS);
-
-}
-
-unsigned long HashBytesPolynomial(u8 * value, unsigned int len)
-{
- unsigned char *word = value;
- unsigned int ret = 0;
- unsigned int i;
-
- for (i = 0; i < len; i++) {
- int mod = i % 32;
- ret ^= (unsigned int)(word[i]) << mod;
- ret ^= (unsigned int)(word[i]) >> (32 - mod);
- }
- return ret;
-}
-
-void Sta_Announce_or_Forward_802_3_Packet(struct rt_rtmp_adapter *pAd,
- void *pPacket,
- u8 FromWhichBSSID)
-{
- if (TRUE) {
- announce_802_3_packet(pAd, pPacket);
- } else {
- /* release packet */
- RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_FAILURE);
- }
-}
diff --git a/drivers/staging/rt2860/sta/sanity.c b/drivers/staging/rt2860/sta/sanity.c
deleted file mode 100644
index 0c32604..0000000
--- a/drivers/staging/rt2860/sta/sanity.c
+++ /dev/null
@@ -1,362 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- sanity.c
-
- Abstract:
-
- Revision History:
- Who When What
- -------- ---------- ----------------------------------------------
- John Chang 2004-09-01 add WMM support
- Justin P. Mattock 11/07/2010 Fix typos
-*/
-#include "../rt_config.h"
-
-extern u8 CISCO_OUI[];
-
-extern u8 WPA_OUI[];
-extern u8 RSN_OUI[];
-extern u8 WME_INFO_ELEM[];
-extern u8 WME_PARM_ELEM[];
-extern u8 Ccx2QosInfo[];
-extern u8 RALINK_OUI[];
-extern u8 BROADCOM_OUI[];
-
-/*
- ==========================================================================
- Description:
- MLME message sanity check
- Return:
- TRUE if all parameters are OK, FALSE otherwise
- ==========================================================================
- */
-BOOLEAN MlmeStartReqSanity(struct rt_rtmp_adapter *pAd,
- void * Msg,
- unsigned long MsgLen,
- char Ssid[], u8 * pSsidLen)
-{
- struct rt_mlme_start_req *Info;
-
- Info = (struct rt_mlme_start_req *)(Msg);
-
- if (Info->SsidLen > MAX_LEN_OF_SSID) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("MlmeStartReqSanity fail - wrong SSID length\n"));
- return FALSE;
- }
-
- *pSsidLen = Info->SsidLen;
- NdisMoveMemory(Ssid, Info->Ssid, *pSsidLen);
-
- return TRUE;
-}
-
-/*
- ==========================================================================
- Description:
- MLME message sanity check
- Return:
- TRUE if all parameters are OK, FALSE otherwise
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
- */
-BOOLEAN PeerAssocRspSanity(struct rt_rtmp_adapter *pAd, void * pMsg, unsigned long MsgLen, u8 *pAddr2, u16 * pCapabilityInfo, u16 * pStatus, u16 * pAid, u8 SupRate[], u8 * pSupRateLen, u8 ExtRate[], u8 * pExtRateLen, struct rt_ht_capability_ie * pHtCapability, struct rt_add_ht_info_ie * pAddHtInfo, /* AP might use this additional ht info IE */
- u8 * pHtCapabilityLen,
- u8 * pAddHtInfoLen,
- u8 * pNewExtChannelOffset,
- struct rt_edca_parm *pEdcaParm, u8 * pCkipFlag)
-{
- char IeType, *Ptr;
- struct rt_frame_802_11 * pFrame = (struct rt_frame_802_11 *) pMsg;
- struct rt_eid * pEid;
- unsigned long Length = 0;
-
- *pNewExtChannelOffset = 0xff;
- *pHtCapabilityLen = 0;
- *pAddHtInfoLen = 0;
- COPY_MAC_ADDR(pAddr2, pFrame->Hdr.Addr2);
- Ptr = (char *)pFrame->Octet;
- Length += LENGTH_802_11;
-
- NdisMoveMemory(pCapabilityInfo, &pFrame->Octet[0], 2);
- Length += 2;
- NdisMoveMemory(pStatus, &pFrame->Octet[2], 2);
- Length += 2;
- *pCkipFlag = 0;
- *pExtRateLen = 0;
- pEdcaParm->bValid = FALSE;
-
- if (*pStatus != MLME_SUCCESS)
- return TRUE;
-
- NdisMoveMemory(pAid, &pFrame->Octet[4], 2);
- Length += 2;
-
- /* Aid already swapped byte order in RTMPFrameEndianChange() for big endian platform */
- *pAid = (*pAid) & 0x3fff; /* AID is low 14-bit */
-
- /* -- get supported rates from payload and advance the pointer */
- IeType = pFrame->Octet[6];
- *pSupRateLen = pFrame->Octet[7];
- if ((IeType != IE_SUPP_RATES)
- || (*pSupRateLen > MAX_LEN_OF_SUPPORTED_RATES)) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("PeerAssocRspSanity fail - wrong SupportedRates IE\n"));
- return FALSE;
- } else
- NdisMoveMemory(SupRate, &pFrame->Octet[8], *pSupRateLen);
-
- Length = Length + 2 + *pSupRateLen;
-
- /* many AP implement proprietary IEs in non-standard order, we'd better */
- /* tolerate mis-ordered IEs to get best compatibility */
- pEid = (struct rt_eid *) & pFrame->Octet[8 + (*pSupRateLen)];
-
- /* get variable fields from payload and advance the pointer */
- while ((Length + 2 + pEid->Len) <= MsgLen) {
- switch (pEid->Eid) {
- case IE_EXT_SUPP_RATES:
- if (pEid->Len <= MAX_LEN_OF_SUPPORTED_RATES) {
- NdisMoveMemory(ExtRate, pEid->Octet, pEid->Len);
- *pExtRateLen = pEid->Len;
- }
- break;
-
- case IE_HT_CAP:
- case IE_HT_CAP2:
- if (pEid->Len >= SIZE_HT_CAP_IE) /*Note: allow extension! */
- {
- NdisMoveMemory(pHtCapability, pEid->Octet,
- SIZE_HT_CAP_IE);
-
- *(u16 *) (&pHtCapability->HtCapInfo) =
- cpu2le16(*(u16 *)
- (&pHtCapability->HtCapInfo));
- *(u16 *) (&pHtCapability->ExtHtCapInfo) =
- cpu2le16(*(u16 *)
- (&pHtCapability->ExtHtCapInfo));
-
- *pHtCapabilityLen = SIZE_HT_CAP_IE;
- } else {
- DBGPRINT(RT_DEBUG_WARN,
- ("PeerAssocRspSanity - wrong IE_HT_CAP. \n"));
- }
-
- break;
- case IE_ADD_HT:
- case IE_ADD_HT2:
- if (pEid->Len >= sizeof(struct rt_add_ht_info_ie)) {
- /* This IE allows extension, but we can ignore extra bytes beyond our knowledge , so only */
- /* copy first sizeof(struct rt_add_ht_info_ie) */
- NdisMoveMemory(pAddHtInfo, pEid->Octet,
- sizeof(struct rt_add_ht_info_ie));
-
- *(u16 *) (&pAddHtInfo->AddHtInfo2) =
- cpu2le16(*(u16 *)
- (&pAddHtInfo->AddHtInfo2));
- *(u16 *) (&pAddHtInfo->AddHtInfo3) =
- cpu2le16(*(u16 *)
- (&pAddHtInfo->AddHtInfo3));
-
- *pAddHtInfoLen = SIZE_ADD_HT_INFO_IE;
- } else {
- DBGPRINT(RT_DEBUG_WARN,
- ("PeerAssocRspSanity - wrong IE_ADD_HT. \n"));
- }
-
- break;
- case IE_SECONDARY_CH_OFFSET:
- if (pEid->Len == 1) {
- *pNewExtChannelOffset = pEid->Octet[0];
- } else {
- DBGPRINT(RT_DEBUG_WARN,
- ("PeerAssocRspSanity - wrong IE_SECONDARY_CH_OFFSET. \n"));
- }
- break;
-
- case IE_VENDOR_SPECIFIC:
- /* handle WME PARAMTER ELEMENT */
- if (NdisEqualMemory(pEid->Octet, WME_PARM_ELEM, 6)
- && (pEid->Len == 24)) {
- u8 *ptr;
- int i;
-
- /* parsing EDCA parameters */
- pEdcaParm->bValid = TRUE;
- pEdcaParm->bQAck = FALSE; /* pEid->Octet[0] & 0x10; */
- pEdcaParm->bQueueRequest = FALSE; /* pEid->Octet[0] & 0x20; */
- pEdcaParm->bTxopRequest = FALSE; /* pEid->Octet[0] & 0x40; */
- /*pEdcaParm->bMoreDataAck = FALSE; // pEid->Octet[0] & 0x80; */
- pEdcaParm->EdcaUpdateCount =
- pEid->Octet[6] & 0x0f;
- pEdcaParm->bAPSDCapable =
- (pEid->Octet[6] & 0x80) ? 1 : 0;
- ptr = (u8 *)& pEid->Octet[8];
- for (i = 0; i < 4; i++) {
- u8 aci = (*ptr & 0x60) >> 5; /* b5~6 is AC INDEX */
- pEdcaParm->bACM[aci] = (((*ptr) & 0x10) == 0x10); /* b5 is ACM */
- pEdcaParm->Aifsn[aci] = (*ptr) & 0x0f; /* b0~3 is AIFSN */
- pEdcaParm->Cwmin[aci] = *(ptr + 1) & 0x0f; /* b0~4 is Cwmin */
- pEdcaParm->Cwmax[aci] = *(ptr + 1) >> 4; /* b5~8 is Cwmax */
- pEdcaParm->Txop[aci] = *(ptr + 2) + 256 * (*(ptr + 3)); /* in unit of 32-us */
- ptr += 4; /* point to next AC */
- }
- }
- break;
- default:
- DBGPRINT(RT_DEBUG_TRACE,
- ("PeerAssocRspSanity - ignore unrecognized EID = %d\n",
- pEid->Eid));
- break;
- }
-
- Length = Length + 2 + pEid->Len;
- pEid = (struct rt_eid *) ((u8 *) pEid + 2 + pEid->Len);
- }
-
- return TRUE;
-}
-
-/*
- ==========================================================================
- Description:
- MLME message sanity check
- Return:
- TRUE if all parameters are OK, FALSE otherwise
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
- */
-BOOLEAN PeerProbeReqSanity(struct rt_rtmp_adapter *pAd,
- void * Msg,
- unsigned long MsgLen,
- u8 *pAddr2,
- char Ssid[], u8 * pSsidLen)
-{
- u8 Idx;
- u8 RateLen;
- char IeType;
- struct rt_frame_802_11 * pFrame = (struct rt_frame_802_11 *) Msg;
-
- COPY_MAC_ADDR(pAddr2, pFrame->Hdr.Addr2);
-
- if ((pFrame->Octet[0] != IE_SSID)
- || (pFrame->Octet[1] > MAX_LEN_OF_SSID)) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("PeerProbeReqSanity fail - wrong SSID IE(Type=%d,Len=%d)\n",
- pFrame->Octet[0], pFrame->Octet[1]));
- return FALSE;
- }
-
- *pSsidLen = pFrame->Octet[1];
- NdisMoveMemory(Ssid, &pFrame->Octet[2], *pSsidLen);
-
- Idx = *pSsidLen + 2;
-
- /* -- get supported rates from payload and advance the pointer */
- IeType = pFrame->Octet[Idx];
- RateLen = pFrame->Octet[Idx + 1];
- if (IeType != IE_SUPP_RATES) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("PeerProbeReqSanity fail - wrong SupportRates IE(Type=%d,Len=%d)\n",
- pFrame->Octet[Idx], pFrame->Octet[Idx + 1]));
- return FALSE;
- } else {
- if ((pAd->CommonCfg.PhyMode == PHY_11G) && (RateLen < 8))
- return (FALSE);
- }
-
- return TRUE;
-}
-
-/*
- ==========================================================================
- Description:
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
- */
-BOOLEAN GetTimBit(char * Ptr,
- u16 Aid,
- u8 * TimLen,
- u8 * BcastFlag,
- u8 * DtimCount,
- u8 * DtimPeriod, u8 * MessageToMe)
-{
- u8 BitCntl, N1, N2, MyByte, MyBit;
- char *IdxPtr;
-
- IdxPtr = Ptr;
-
- IdxPtr++;
- *TimLen = *IdxPtr;
-
- /* get DTIM Count from TIM element */
- IdxPtr++;
- *DtimCount = *IdxPtr;
-
- /* get DTIM Period from TIM element */
- IdxPtr++;
- *DtimPeriod = *IdxPtr;
-
- /* get Bitmap Control from TIM element */
- IdxPtr++;
- BitCntl = *IdxPtr;
-
- if ((*DtimCount == 0) && (BitCntl & 0x01))
- *BcastFlag = TRUE;
- else
- *BcastFlag = FALSE;
-
- /* Parse Partial Virtual Bitmap from TIM element */
- N1 = BitCntl & 0xfe; /* N1 is the first bitmap byte# */
- N2 = *TimLen - 4 + N1; /* N2 is the last bitmap byte# */
-
- if ((Aid < (N1 << 3)) || (Aid >= ((N2 + 1) << 3)))
- *MessageToMe = FALSE;
- else {
- MyByte = (Aid >> 3) - N1; /* my byte position in the bitmap byte-stream */
- MyBit = Aid % 16 - ((MyByte & 0x01) ? 8 : 0);
-
- IdxPtr += (MyByte + 1);
-
- /*if (*IdxPtr) */
- /* DBGPRINT(RT_DEBUG_WARN, ("TIM bitmap = 0x%02x\n", *IdxPtr)); */
-
- if (*IdxPtr & (0x01 << MyBit))
- *MessageToMe = TRUE;
- else
- *MessageToMe = FALSE;
- }
-
- return TRUE;
-}
diff --git a/drivers/staging/rt2860/sta/sync.c b/drivers/staging/rt2860/sta/sync.c
deleted file mode 100644
index 7054ba1..0000000
--- a/drivers/staging/rt2860/sta/sync.c
+++ /dev/null
@@ -1,1968 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- sync.c
-
- Abstract:
-
- Revision History:
- Who When What
- -------- ---------- ----------------------------------------------
- John Chang 2004-09-01 modified for rt2561/2661
- Jan Lee 2006-08-01 modified for rt2860 for 802.11n
- Justin P. Mattock 11/07/2010 Fix typos
-*/
-#include "../rt_config.h"
-
-#define ADHOC_ENTRY_BEACON_LOST_TIME (2*OS_HZ) /* 2 sec */
-
-/*
- ==========================================================================
- Description:
- The sync state machine,
- Parameters:
- Sm - pointer to the state machine
- Note:
- the state machine looks like the following
-
- ==========================================================================
- */
-void SyncStateMachineInit(struct rt_rtmp_adapter *pAd,
- struct rt_state_machine *Sm, OUT STATE_MACHINE_FUNC Trans[])
-{
- StateMachineInit(Sm, Trans, MAX_SYNC_STATE, MAX_SYNC_MSG,
- (STATE_MACHINE_FUNC) Drop, SYNC_IDLE,
- SYNC_MACHINE_BASE);
-
- /* column 1 */
- StateMachineSetAction(Sm, SYNC_IDLE, MT2_MLME_SCAN_REQ,
- (STATE_MACHINE_FUNC) MlmeScanReqAction);
- StateMachineSetAction(Sm, SYNC_IDLE, MT2_MLME_JOIN_REQ,
- (STATE_MACHINE_FUNC) MlmeJoinReqAction);
- StateMachineSetAction(Sm, SYNC_IDLE, MT2_MLME_START_REQ,
- (STATE_MACHINE_FUNC) MlmeStartReqAction);
- StateMachineSetAction(Sm, SYNC_IDLE, MT2_PEER_BEACON,
- (STATE_MACHINE_FUNC) PeerBeacon);
- StateMachineSetAction(Sm, SYNC_IDLE, MT2_PEER_PROBE_REQ,
- (STATE_MACHINE_FUNC) PeerProbeReqAction);
-
- /*column 2 */
- StateMachineSetAction(Sm, JOIN_WAIT_BEACON, MT2_MLME_SCAN_REQ,
- (STATE_MACHINE_FUNC) InvalidStateWhenScan);
- StateMachineSetAction(Sm, JOIN_WAIT_BEACON, MT2_MLME_JOIN_REQ,
- (STATE_MACHINE_FUNC) InvalidStateWhenJoin);
- StateMachineSetAction(Sm, JOIN_WAIT_BEACON, MT2_MLME_START_REQ,
- (STATE_MACHINE_FUNC) InvalidStateWhenStart);
- StateMachineSetAction(Sm, JOIN_WAIT_BEACON, MT2_PEER_BEACON,
- (STATE_MACHINE_FUNC) PeerBeaconAtJoinAction);
- StateMachineSetAction(Sm, JOIN_WAIT_BEACON, MT2_BEACON_TIMEOUT,
- (STATE_MACHINE_FUNC) BeaconTimeoutAtJoinAction);
-
- /* column 3 */
- StateMachineSetAction(Sm, SCAN_LISTEN, MT2_MLME_SCAN_REQ,
- (STATE_MACHINE_FUNC) InvalidStateWhenScan);
- StateMachineSetAction(Sm, SCAN_LISTEN, MT2_MLME_JOIN_REQ,
- (STATE_MACHINE_FUNC) InvalidStateWhenJoin);
- StateMachineSetAction(Sm, SCAN_LISTEN, MT2_MLME_START_REQ,
- (STATE_MACHINE_FUNC) InvalidStateWhenStart);
- StateMachineSetAction(Sm, SCAN_LISTEN, MT2_PEER_BEACON,
- (STATE_MACHINE_FUNC) PeerBeaconAtScanAction);
- StateMachineSetAction(Sm, SCAN_LISTEN, MT2_PEER_PROBE_RSP,
- (STATE_MACHINE_FUNC) PeerBeaconAtScanAction);
- StateMachineSetAction(Sm, SCAN_LISTEN, MT2_SCAN_TIMEOUT,
- (STATE_MACHINE_FUNC) ScanTimeoutAction);
-
- /* timer init */
- RTMPInitTimer(pAd, &pAd->MlmeAux.BeaconTimer,
- GET_TIMER_FUNCTION(BeaconTimeout), pAd, FALSE);
- RTMPInitTimer(pAd, &pAd->MlmeAux.ScanTimer,
- GET_TIMER_FUNCTION(ScanTimeout), pAd, FALSE);
-}
-
-/*
- ==========================================================================
- Description:
- Beacon timeout handler, executed in timer thread
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
- */
-void BeaconTimeout(void *SystemSpecific1,
- void *FunctionContext,
- void *SystemSpecific2, void *SystemSpecific3)
-{
- struct rt_rtmp_adapter *pAd = (struct rt_rtmp_adapter *)FunctionContext;
-
- DBGPRINT(RT_DEBUG_TRACE, ("SYNC - BeaconTimeout\n"));
-
- /* Do nothing if the driver is starting halt state. */
- /* This might happen when timer already been fired before cancel timer with mlmehalt */
- if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS))
- return;
-
- if ((pAd->CommonCfg.BBPCurrentBW == BW_40)
- ) {
- u8 BBPValue = 0;
- AsicSwitchChannel(pAd, pAd->CommonCfg.CentralChannel, FALSE);
- AsicLockChannel(pAd, pAd->CommonCfg.CentralChannel);
- RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &BBPValue);
- BBPValue &= (~0x18);
- BBPValue |= 0x10;
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, BBPValue);
- DBGPRINT(RT_DEBUG_TRACE,
- ("SYNC - End of SCAN, restore to 40MHz channel %d, Total BSS[%02d]\n",
- pAd->CommonCfg.CentralChannel, pAd->ScanTab.BssNr));
- }
-
- MlmeEnqueue(pAd, SYNC_STATE_MACHINE, MT2_BEACON_TIMEOUT, 0, NULL);
- RTMP_MLME_HANDLER(pAd);
-}
-
-/*
- ==========================================================================
- Description:
- Scan timeout handler, executed in timer thread
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
- */
-void ScanTimeout(void *SystemSpecific1,
- void *FunctionContext,
- void *SystemSpecific2, void *SystemSpecific3)
-{
- struct rt_rtmp_adapter *pAd = (struct rt_rtmp_adapter *)FunctionContext;
-
- /* Do nothing if the driver is starting halt state. */
- /* This might happen when timer already been fired before cancel timer with mlmehalt */
- if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS))
- return;
-
- if (MlmeEnqueue(pAd, SYNC_STATE_MACHINE, MT2_SCAN_TIMEOUT, 0, NULL)) {
- RTMP_MLME_HANDLER(pAd);
- } else {
- /* To prevent SyncMachine.CurrState is SCAN_LISTEN forever. */
- pAd->MlmeAux.Channel = 0;
- ScanNextChannel(pAd);
- if (pAd->CommonCfg.bWirelessEvent) {
- RTMPSendWirelessEvent(pAd,
- IW_SCAN_ENQUEUE_FAIL_EVENT_FLAG,
- pAd->MacTab.Content[BSSID_WCID].
- Addr, BSS0, 0);
- }
- }
-}
-
-/*
- ==========================================================================
- Description:
- MLME SCAN req state machine procedure
- ==========================================================================
- */
-void MlmeScanReqAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
- u8 Ssid[MAX_LEN_OF_SSID], SsidLen, ScanType, BssType, BBPValue = 0;
- BOOLEAN TimerCancelled;
- unsigned long Now;
- u16 Status;
- struct rt_header_802_11 * pHdr80211;
- u8 *pOutBuffer = NULL;
- int NStatus;
-
- /* Check the total scan tries for one single OID command */
- /* If this is the CCX 2.0 Case, skip that! */
- if (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_START_UP)) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("SYNC - MlmeScanReqAction before Startup\n"));
- return;
- }
- /* Increase the scan retry counters. */
- pAd->StaCfg.ScanCnt++;
-
-#ifdef RTMP_MAC_PCI
- if ((OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_PCIE_DEVICE)) &&
- (IDLE_ON(pAd)) &&
- (pAd->StaCfg.bRadio == TRUE) &&
- (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_IDLE_RADIO_OFF))) {
- if (pAd->StaCfg.PSControl.field.EnableNewPS == FALSE) {
- AsicSendCommandToMcu(pAd, 0x31, PowerWakeCID, 0x00,
- 0x02);
- AsicCheckCommanOk(pAd, PowerWakeCID);
- RTMP_CLEAR_FLAG(pAd, fRTMP_ADAPTER_IDLE_RADIO_OFF);
- DBGPRINT(RT_DEBUG_TRACE,
- ("PSM - Issue Wake up command \n"));
- } else {
- RT28xxPciAsicRadioOn(pAd, GUI_IDLE_POWER_SAVE);
- }
- }
-#endif /* RTMP_MAC_PCI // */
-
- /* first check the parameter sanity */
- if (MlmeScanReqSanity(pAd,
- Elem->Msg,
- Elem->MsgLen,
- &BssType, (char *)Ssid, &SsidLen, &ScanType)) {
-
- /* Check for channel load and noise hist request */
- /* Suspend MSDU only at scan request, not the last two mentioned */
- /* Suspend MSDU transmission here */
- RTMPSuspendMsduTransmission(pAd);
-
- /* */
- /* To prevent data loss. */
- /* Send a NULL data with turned PSM bit on to current associated AP before SCAN progress. */
- /* And should send a NULL data with turned PSM bit off to AP, when scan progress done */
- /* */
- if (OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_MEDIA_STATE_CONNECTED)
- && (INFRA_ON(pAd))) {
- NStatus = MlmeAllocateMemory(pAd, (void *)& pOutBuffer);
- if (NStatus == NDIS_STATUS_SUCCESS) {
- pHdr80211 = (struct rt_header_802_11 *) pOutBuffer;
- MgtMacHeaderInit(pAd, pHdr80211,
- SUBTYPE_NULL_FUNC, 1,
- pAd->CommonCfg.Bssid,
- pAd->CommonCfg.Bssid);
- pHdr80211->Duration = 0;
- pHdr80211->FC.Type = BTYPE_DATA;
- pHdr80211->FC.PwrMgmt = PWR_SAVE;
-
- /* Send using priority queue */
- MiniportMMRequest(pAd, 0, pOutBuffer,
- sizeof(struct rt_header_802_11));
- DBGPRINT(RT_DEBUG_TRACE,
- ("MlmeScanReqAction -- Send PSM Data frame for off channel RM\n"));
- MlmeFreeMemory(pAd, pOutBuffer);
- RTMPusecDelay(5000);
- }
- }
-
- NdisGetSystemUpTime(&Now);
- pAd->StaCfg.LastScanTime = Now;
- /* reset all the timers */
- RTMPCancelTimer(&pAd->MlmeAux.BeaconTimer, &TimerCancelled);
- RTMPCancelTimer(&pAd->MlmeAux.ScanTimer, &TimerCancelled);
-
- /* record desired BSS parameters */
- pAd->MlmeAux.BssType = BssType;
- pAd->MlmeAux.ScanType = ScanType;
- pAd->MlmeAux.SsidLen = SsidLen;
- NdisZeroMemory(pAd->MlmeAux.Ssid, MAX_LEN_OF_SSID);
- NdisMoveMemory(pAd->MlmeAux.Ssid, Ssid, SsidLen);
-
- /* start from the first channel */
- pAd->MlmeAux.Channel = FirstChannel(pAd);
-
- /* Let BBP register at 20MHz to do scan */
- RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &BBPValue);
- BBPValue &= (~0x18);
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, BBPValue);
- DBGPRINT(RT_DEBUG_TRACE, ("SYNC - BBP R4 to 20MHz.l\n"));
- ScanNextChannel(pAd);
- } else {
- DBGPRINT_ERR("SYNC - MlmeScanReqAction() sanity check fail\n");
- pAd->Mlme.SyncMachine.CurrState = SYNC_IDLE;
- Status = MLME_INVALID_FORMAT;
- MlmeEnqueue(pAd, MLME_CNTL_STATE_MACHINE, MT2_SCAN_CONF, 2,
- &Status);
- }
-}
-
-/*
- ==========================================================================
- Description:
- MLME JOIN req state machine procedure
- ==========================================================================
- */
-void MlmeJoinReqAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
- u8 BBPValue = 0;
- struct rt_bss_entry *pBss;
- BOOLEAN TimerCancelled;
- struct rt_header_802_11 Hdr80211;
- int NStatus;
- unsigned long FrameLen = 0;
- u8 *pOutBuffer = NULL;
- u8 *pSupRate = NULL;
- u8 SupRateLen;
- u8 *pExtRate = NULL;
- u8 ExtRateLen;
- u8 ASupRate[] = { 0x8C, 0x12, 0x98, 0x24, 0xb0, 0x48, 0x60, 0x6C };
- u8 ASupRateLen = sizeof(ASupRate) / sizeof(u8);
- struct rt_mlme_join_req *pInfo = (struct rt_mlme_join_req *)(Elem->Msg);
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("SYNC - MlmeJoinReqAction(BSS #%ld)\n", pInfo->BssIdx));
-
-#ifdef RTMP_MAC_PCI
- if ((OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_PCIE_DEVICE)) &&
- (IDLE_ON(pAd)) &&
- (pAd->StaCfg.bRadio == TRUE) &&
- (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_IDLE_RADIO_OFF))) {
- RT28xxPciAsicRadioOn(pAd, GUI_IDLE_POWER_SAVE);
- }
-#endif /* RTMP_MAC_PCI // */
-
- /* reset all the timers */
- RTMPCancelTimer(&pAd->MlmeAux.ScanTimer, &TimerCancelled);
- RTMPCancelTimer(&pAd->MlmeAux.BeaconTimer, &TimerCancelled);
-
- pBss = &pAd->MlmeAux.SsidBssTab.BssEntry[pInfo->BssIdx];
-
- /* record the desired SSID & BSSID we're waiting for */
- COPY_MAC_ADDR(pAd->MlmeAux.Bssid, pBss->Bssid);
-
- /* If AP's SSID is not hidden, it is OK for updating ssid to MlmeAux again. */
- if (pBss->Hidden == 0) {
- RTMPZeroMemory(pAd->MlmeAux.Ssid, MAX_LEN_OF_SSID);
- NdisMoveMemory(pAd->MlmeAux.Ssid, pBss->Ssid, pBss->SsidLen);
- pAd->MlmeAux.SsidLen = pBss->SsidLen;
- }
-
- pAd->MlmeAux.BssType = pBss->BssType;
- pAd->MlmeAux.Channel = pBss->Channel;
- pAd->MlmeAux.CentralChannel = pBss->CentralChannel;
-
- /* Let BBP register at 20MHz to do scan */
- RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &BBPValue);
- BBPValue &= (~0x18);
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, BBPValue);
-
- DBGPRINT(RT_DEBUG_TRACE, ("SYNC - BBP R4 to 20MHz.l\n"));
-
- /* switch channel and waiting for beacon timer */
- AsicSwitchChannel(pAd, pAd->MlmeAux.Channel, FALSE);
- AsicLockChannel(pAd, pAd->MlmeAux.Channel);
- RTMPSetTimer(&pAd->MlmeAux.BeaconTimer, JOIN_TIMEOUT);
-
- do {
- if (((pAd->CommonCfg.bIEEE80211H == 1) &&
- (pAd->MlmeAux.Channel > 14) &&
- RadarChannelCheck(pAd, pAd->MlmeAux.Channel))
- ) {
- /* */
- /* We can't send any Probe request frame to meet 802.11h. */
- /* */
- if (pBss->Hidden == 0)
- break;
- }
- /* */
- /* send probe request */
- /* */
- NStatus = MlmeAllocateMemory(pAd, &pOutBuffer);
- if (NStatus == NDIS_STATUS_SUCCESS) {
- if (pAd->MlmeAux.Channel <= 14) {
- pSupRate = pAd->CommonCfg.SupRate;
- SupRateLen = pAd->CommonCfg.SupRateLen;
- pExtRate = pAd->CommonCfg.ExtRate;
- ExtRateLen = pAd->CommonCfg.ExtRateLen;
- } else {
- /* */
- /* Overwrite Support Rate, CCK rate are not allowed */
- /* */
- pSupRate = ASupRate;
- SupRateLen = ASupRateLen;
- ExtRateLen = 0;
- }
-
- if (pAd->MlmeAux.BssType == BSS_INFRA)
- MgtMacHeaderInit(pAd, &Hdr80211,
- SUBTYPE_PROBE_REQ, 0,
- pAd->MlmeAux.Bssid,
- pAd->MlmeAux.Bssid);
- else
- MgtMacHeaderInit(pAd, &Hdr80211,
- SUBTYPE_PROBE_REQ, 0,
- BROADCAST_ADDR,
- BROADCAST_ADDR);
-
- MakeOutgoingFrame(pOutBuffer, &FrameLen,
- sizeof(struct rt_header_802_11), &Hdr80211,
- 1, &SsidIe,
- 1, &pAd->MlmeAux.SsidLen,
- pAd->MlmeAux.SsidLen,
- pAd->MlmeAux.Ssid, 1, &SupRateIe, 1,
- &SupRateLen, SupRateLen, pSupRate,
- END_OF_ARGS);
-
- if (ExtRateLen) {
- unsigned long Tmp;
- MakeOutgoingFrame(pOutBuffer + FrameLen, &Tmp,
- 1, &ExtRateIe,
- 1, &ExtRateLen,
- ExtRateLen, pExtRate,
- END_OF_ARGS);
- FrameLen += Tmp;
- }
-
- MiniportMMRequest(pAd, 0, pOutBuffer, FrameLen);
- MlmeFreeMemory(pAd, pOutBuffer);
- }
- } while (FALSE);
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("SYNC - Switch to ch %d, Wait BEACON from %pM\n",
- pBss->Channel, pBss->Bssid));
-
- pAd->Mlme.SyncMachine.CurrState = JOIN_WAIT_BEACON;
-}
-
-/*
- ==========================================================================
- Description:
- MLME START Request state machine procedure, starting an IBSS
- ==========================================================================
- */
-void MlmeStartReqAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
- u8 Ssid[MAX_LEN_OF_SSID], SsidLen;
- BOOLEAN TimerCancelled;
-
- /* New for WPA security suites */
- u8 VarIE[MAX_VIE_LEN]; /* Total VIE length = MAX_VIE_LEN - -5 */
- struct rt_ndis_802_11_variable_ies *pVIE = NULL;
- LARGE_INTEGER TimeStamp;
- BOOLEAN Privacy;
- u16 Status;
-
- /* Init Variable IE structure */
- pVIE = (struct rt_ndis_802_11_variable_ies *)VarIE;
- pVIE->Length = 0;
- TimeStamp.u.LowPart = 0;
- TimeStamp.u.HighPart = 0;
-
- if (MlmeStartReqSanity
- (pAd, Elem->Msg, Elem->MsgLen, (char *)Ssid, &SsidLen)) {
- /* reset all the timers */
- RTMPCancelTimer(&pAd->MlmeAux.ScanTimer, &TimerCancelled);
- RTMPCancelTimer(&pAd->MlmeAux.BeaconTimer, &TimerCancelled);
-
- /* */
- /* Start a new IBSS. All IBSS parameters are decided now.... */
- /* */
- DBGPRINT(RT_DEBUG_TRACE,
- ("MlmeStartReqAction - Start a new IBSS. All IBSS parameters are decided now.... \n"));
- pAd->MlmeAux.BssType = BSS_ADHOC;
- NdisMoveMemory(pAd->MlmeAux.Ssid, Ssid, SsidLen);
- pAd->MlmeAux.SsidLen = SsidLen;
-
- /* generate a radom number as BSSID */
- MacAddrRandomBssid(pAd, pAd->MlmeAux.Bssid);
- DBGPRINT(RT_DEBUG_TRACE,
- ("MlmeStartReqAction - generate a radom number as BSSID \n"));
-
- Privacy =
- (pAd->StaCfg.WepStatus == Ndis802_11Encryption1Enabled)
- || (pAd->StaCfg.WepStatus == Ndis802_11Encryption2Enabled)
- || (pAd->StaCfg.WepStatus == Ndis802_11Encryption3Enabled);
- pAd->MlmeAux.CapabilityInfo =
- CAP_GENERATE(0, 1, Privacy,
- (pAd->CommonCfg.TxPreamble ==
- Rt802_11PreambleShort), 1, 0);
- pAd->MlmeAux.BeaconPeriod = pAd->CommonCfg.BeaconPeriod;
- pAd->MlmeAux.AtimWin = pAd->StaCfg.AtimWin;
- pAd->MlmeAux.Channel = pAd->CommonCfg.Channel;
-
- pAd->CommonCfg.CentralChannel = pAd->CommonCfg.Channel;
- pAd->MlmeAux.CentralChannel = pAd->CommonCfg.CentralChannel;
-
- pAd->MlmeAux.SupRateLen = pAd->CommonCfg.SupRateLen;
- NdisMoveMemory(pAd->MlmeAux.SupRate, pAd->CommonCfg.SupRate,
- MAX_LEN_OF_SUPPORTED_RATES);
- RTMPCheckRates(pAd, pAd->MlmeAux.SupRate,
- &pAd->MlmeAux.SupRateLen);
- pAd->MlmeAux.ExtRateLen = pAd->CommonCfg.ExtRateLen;
- NdisMoveMemory(pAd->MlmeAux.ExtRate, pAd->CommonCfg.ExtRate,
- MAX_LEN_OF_SUPPORTED_RATES);
- RTMPCheckRates(pAd, pAd->MlmeAux.ExtRate,
- &pAd->MlmeAux.ExtRateLen);
-
- if (pAd->CommonCfg.PhyMode >= PHY_11ABGN_MIXED) {
- RTMPUpdateHTIE(&pAd->CommonCfg.DesiredHtPhy,
- &pAd->StaCfg.DesiredHtPhyInfo.MCSSet[0],
- &pAd->MlmeAux.HtCapability,
- &pAd->MlmeAux.AddHtInfo);
- pAd->MlmeAux.HtCapabilityLen = sizeof(struct rt_ht_capability_ie);
- /* Not turn pAd->StaActive.SupportedHtPhy.bHtEnable = TRUE here. */
- DBGPRINT(RT_DEBUG_TRACE,
- ("SYNC -pAd->StaActive.SupportedHtPhy.bHtEnable = TRUE\n"));
- } else {
- pAd->MlmeAux.HtCapabilityLen = 0;
- pAd->StaActive.SupportedPhyInfo.bHtEnable = FALSE;
- NdisZeroMemory(&pAd->StaActive.SupportedPhyInfo.
- MCSSet[0], 16);
- }
- /* temporarily not support QOS in IBSS */
- NdisZeroMemory(&pAd->MlmeAux.APEdcaParm, sizeof(struct rt_edca_parm));
- NdisZeroMemory(&pAd->MlmeAux.APQbssLoad,
- sizeof(struct rt_qbss_load_parm));
- NdisZeroMemory(&pAd->MlmeAux.APQosCapability,
- sizeof(struct rt_qos_capability_parm));
-
- AsicSwitchChannel(pAd, pAd->MlmeAux.Channel, FALSE);
- AsicLockChannel(pAd, pAd->MlmeAux.Channel);
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("SYNC - MlmeStartReqAction(ch= %d,sup rates= %d, ext rates=%d)\n",
- pAd->MlmeAux.Channel, pAd->MlmeAux.SupRateLen,
- pAd->MlmeAux.ExtRateLen));
-
- pAd->Mlme.SyncMachine.CurrState = SYNC_IDLE;
- Status = MLME_SUCCESS;
- MlmeEnqueue(pAd, MLME_CNTL_STATE_MACHINE, MT2_START_CONF, 2,
- &Status);
- } else {
- DBGPRINT_ERR("SYNC - MlmeStartReqAction() sanity check fail.\n");
- pAd->Mlme.SyncMachine.CurrState = SYNC_IDLE;
- Status = MLME_INVALID_FORMAT;
- MlmeEnqueue(pAd, MLME_CNTL_STATE_MACHINE, MT2_START_CONF, 2,
- &Status);
- }
-}
-
-/*
- ==========================================================================
- Description:
- peer sends beacon back when scanning
- ==========================================================================
- */
-void PeerBeaconAtScanAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
- u8 Bssid[MAC_ADDR_LEN], Addr2[MAC_ADDR_LEN];
- u8 Ssid[MAX_LEN_OF_SSID], BssType, Channel, NewChannel,
- SsidLen, DtimCount, DtimPeriod, BcastFlag, MessageToMe;
- struct rt_cf_parm CfParm;
- u16 BeaconPeriod, AtimWin, CapabilityInfo;
- struct rt_frame_802_11 * pFrame;
- LARGE_INTEGER TimeStamp;
- u8 Erp;
- u8 SupRate[MAX_LEN_OF_SUPPORTED_RATES],
- ExtRate[MAX_LEN_OF_SUPPORTED_RATES];
- u8 SupRateLen, ExtRateLen;
- u16 LenVIE;
- u8 CkipFlag;
- u8 AironetCellPowerLimit;
- struct rt_edca_parm EdcaParm;
- struct rt_qbss_load_parm QbssLoad;
- struct rt_qos_capability_parm QosCapability;
- unsigned long RalinkIe;
- u8 VarIE[MAX_VIE_LEN]; /* Total VIE length = MAX_VIE_LEN - -5 */
- struct rt_ndis_802_11_variable_ies *pVIE = NULL;
- struct rt_ht_capability_ie HtCapability;
- struct rt_add_ht_info_ie AddHtInfo; /* AP might use this additional ht info IE */
- u8 HtCapabilityLen = 0, PreNHtCapabilityLen = 0;
- u8 AddHtInfoLen;
- u8 NewExtChannelOffset = 0xff;
-
- /* NdisFillMemory(Ssid, MAX_LEN_OF_SSID, 0x00); */
- pFrame = (struct rt_frame_802_11 *) Elem->Msg;
- /* Init Variable IE structure */
- pVIE = (struct rt_ndis_802_11_variable_ies *)VarIE;
- pVIE->Length = 0;
-
- RTMPZeroMemory(&HtCapability, sizeof(HtCapability));
- RTMPZeroMemory(&AddHtInfo, sizeof(struct rt_add_ht_info_ie));
-
- if (PeerBeaconAndProbeRspSanity(pAd,
- Elem->Msg,
- Elem->MsgLen,
- Elem->Channel,
- Addr2,
- Bssid,
- (char *)Ssid,
- &SsidLen,
- &BssType,
- &BeaconPeriod,
- &Channel,
- &NewChannel,
- &TimeStamp,
- &CfParm,
- &AtimWin,
- &CapabilityInfo,
- &Erp,
- &DtimCount,
- &DtimPeriod,
- &BcastFlag,
- &MessageToMe,
- SupRate,
- &SupRateLen,
- ExtRate,
- &ExtRateLen,
- &CkipFlag,
- &AironetCellPowerLimit,
- &EdcaParm,
- &QbssLoad,
- &QosCapability,
- &RalinkIe,
- &HtCapabilityLen,
- &PreNHtCapabilityLen,
- &HtCapability,
- &AddHtInfoLen,
- &AddHtInfo,
- &NewExtChannelOffset, &LenVIE, pVIE)) {
- unsigned long Idx;
- char Rssi = 0;
-
- Idx = BssTableSearch(&pAd->ScanTab, Bssid, Channel);
- if (Idx != BSS_NOT_FOUND)
- Rssi = pAd->ScanTab.BssEntry[Idx].Rssi;
-
- Rssi =
- RTMPMaxRssi(pAd, ConvertToRssi(pAd, Elem->Rssi0, RSSI_0),
- ConvertToRssi(pAd, Elem->Rssi1, RSSI_1),
- ConvertToRssi(pAd, Elem->Rssi2, RSSI_2));
-
- if ((HtCapabilityLen > 0) || (PreNHtCapabilityLen > 0))
- HtCapabilityLen = SIZE_HT_CAP_IE;
-
- Idx =
- BssTableSetEntry(pAd, &pAd->ScanTab, Bssid, (char *)Ssid,
- SsidLen, BssType, BeaconPeriod, &CfParm,
- AtimWin, CapabilityInfo, SupRate,
- SupRateLen, ExtRate, ExtRateLen,
- &HtCapability, &AddHtInfo, HtCapabilityLen,
- AddHtInfoLen, NewExtChannelOffset, Channel,
- Rssi, TimeStamp, CkipFlag, &EdcaParm,
- &QosCapability, &QbssLoad, LenVIE, pVIE);
-
- if (Idx != BSS_NOT_FOUND) {
- NdisMoveMemory(pAd->ScanTab.BssEntry[Idx].PTSF,
- &Elem->Msg[24], 4);
- NdisMoveMemory(&pAd->ScanTab.BssEntry[Idx].TTSF[0],
- &Elem->TimeStamp.u.LowPart, 4);
- NdisMoveMemory(&pAd->ScanTab.BssEntry[Idx].TTSF[4],
- &Elem->TimeStamp.u.LowPart, 4);
- }
-
- }
- /* sanity check fail, ignored */
-}
-
-/*
- ==========================================================================
- Description:
- When waiting joining the (I)BSS, beacon received from external
- ==========================================================================
- */
-void PeerBeaconAtJoinAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
- u8 Bssid[MAC_ADDR_LEN], Addr2[MAC_ADDR_LEN];
- u8 Ssid[MAX_LEN_OF_SSID], SsidLen, BssType, Channel, MessageToMe,
- DtimCount, DtimPeriod, BcastFlag, NewChannel;
- LARGE_INTEGER TimeStamp;
- u16 BeaconPeriod, AtimWin, CapabilityInfo;
- struct rt_cf_parm Cf;
- BOOLEAN TimerCancelled;
- u8 Erp;
- u8 SupRate[MAX_LEN_OF_SUPPORTED_RATES],
- ExtRate[MAX_LEN_OF_SUPPORTED_RATES];
- u8 SupRateLen, ExtRateLen;
- u8 CkipFlag;
- u16 LenVIE;
- u8 AironetCellPowerLimit;
- struct rt_edca_parm EdcaParm;
- struct rt_qbss_load_parm QbssLoad;
- struct rt_qos_capability_parm QosCapability;
- u16 Status;
- u8 VarIE[MAX_VIE_LEN]; /* Total VIE length = MAX_VIE_LEN - -5 */
- struct rt_ndis_802_11_variable_ies *pVIE = NULL;
- unsigned long RalinkIe;
- unsigned long Idx;
- struct rt_ht_capability_ie HtCapability;
- struct rt_add_ht_info_ie AddHtInfo; /* AP might use this additional ht info IE */
- u8 HtCapabilityLen = 0, PreNHtCapabilityLen = 0;
- u8 AddHtInfoLen;
- u8 NewExtChannelOffset = 0xff;
- u8 CentralChannel;
- BOOLEAN bAllowNrate = FALSE;
-
- /* Init Variable IE structure */
- pVIE = (struct rt_ndis_802_11_variable_ies *)VarIE;
- pVIE->Length = 0;
- RTMPZeroMemory(&HtCapability, sizeof(HtCapability));
- RTMPZeroMemory(&AddHtInfo, sizeof(struct rt_add_ht_info_ie));
-
- if (PeerBeaconAndProbeRspSanity(pAd,
- Elem->Msg,
- Elem->MsgLen,
- Elem->Channel,
- Addr2,
- Bssid,
- (char *)Ssid,
- &SsidLen,
- &BssType,
- &BeaconPeriod,
- &Channel,
- &NewChannel,
- &TimeStamp,
- &Cf,
- &AtimWin,
- &CapabilityInfo,
- &Erp,
- &DtimCount,
- &DtimPeriod,
- &BcastFlag,
- &MessageToMe,
- SupRate,
- &SupRateLen,
- ExtRate,
- &ExtRateLen,
- &CkipFlag,
- &AironetCellPowerLimit,
- &EdcaParm,
- &QbssLoad,
- &QosCapability,
- &RalinkIe,
- &HtCapabilityLen,
- &PreNHtCapabilityLen,
- &HtCapability,
- &AddHtInfoLen,
- &AddHtInfo,
- &NewExtChannelOffset, &LenVIE, pVIE)) {
- /* Disqualify 11b only adhoc when we are in 11g only adhoc mode */
- if ((BssType == BSS_ADHOC)
- && (pAd->CommonCfg.PhyMode == PHY_11G)
- && ((SupRateLen + ExtRateLen) < 12))
- return;
-
- /* BEACON from desired BSS/IBSS found. We should be able to decide most */
- /* BSS parameters here. */
- /* Q. But what happen if this JOIN doesn't conclude a successful ASSOCIATION? */
- /* Do we need to recover back all parameters belonging to previous BSS? */
- /* A. Should be not. There's no back-door recover to previous AP. It still needs */
- /* a new JOIN-AUTH-ASSOC sequence. */
- if (MAC_ADDR_EQUAL(pAd->MlmeAux.Bssid, Bssid)) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("SYNC - receive desired BEACON at JoinWaitBeacon... Channel = %d\n",
- Channel));
- RTMPCancelTimer(&pAd->MlmeAux.BeaconTimer,
- &TimerCancelled);
-
- /* Update RSSI to prevent No signal display when cards first initialized */
- pAd->StaCfg.RssiSample.LastRssi0 =
- ConvertToRssi(pAd, Elem->Rssi0, RSSI_0);
- pAd->StaCfg.RssiSample.LastRssi1 =
- ConvertToRssi(pAd, Elem->Rssi1, RSSI_1);
- pAd->StaCfg.RssiSample.LastRssi2 =
- ConvertToRssi(pAd, Elem->Rssi2, RSSI_2);
- pAd->StaCfg.RssiSample.AvgRssi0 =
- pAd->StaCfg.RssiSample.LastRssi0;
- pAd->StaCfg.RssiSample.AvgRssi0X8 =
- pAd->StaCfg.RssiSample.AvgRssi0 << 3;
- pAd->StaCfg.RssiSample.AvgRssi1 =
- pAd->StaCfg.RssiSample.LastRssi1;
- pAd->StaCfg.RssiSample.AvgRssi1X8 =
- pAd->StaCfg.RssiSample.AvgRssi1 << 3;
- pAd->StaCfg.RssiSample.AvgRssi2 =
- pAd->StaCfg.RssiSample.LastRssi2;
- pAd->StaCfg.RssiSample.AvgRssi2X8 =
- pAd->StaCfg.RssiSample.AvgRssi2 << 3;
-
- /* */
- /* We need to check if SSID only set to any, then we can record the current SSID. */
- /* Otherwise will cause hidden SSID association failed. */
- /* */
- if (pAd->MlmeAux.SsidLen == 0) {
- NdisMoveMemory(pAd->MlmeAux.Ssid, Ssid,
- SsidLen);
- pAd->MlmeAux.SsidLen = SsidLen;
- } else {
- Idx =
- BssSsidTableSearch(&pAd->ScanTab, Bssid,
- pAd->MlmeAux.Ssid,
- pAd->MlmeAux.SsidLen,
- Channel);
-
- if (Idx == BSS_NOT_FOUND) {
- char Rssi = 0;
- Rssi =
- RTMPMaxRssi(pAd,
- ConvertToRssi(pAd,
- Elem->
- Rssi0,
- RSSI_0),
- ConvertToRssi(pAd,
- Elem->
- Rssi1,
- RSSI_1),
- ConvertToRssi(pAd,
- Elem->
- Rssi2,
- RSSI_2));
- Idx =
- BssTableSetEntry(pAd, &pAd->ScanTab,
- Bssid,
- (char *) Ssid,
- SsidLen, BssType,
- BeaconPeriod, &Cf,
- AtimWin,
- CapabilityInfo,
- SupRate,
- SupRateLen,
- ExtRate,
- ExtRateLen,
- &HtCapability,
- &AddHtInfo,
- HtCapabilityLen,
- AddHtInfoLen,
- NewExtChannelOffset,
- Channel, Rssi,
- TimeStamp,
- CkipFlag,
- &EdcaParm,
- &QosCapability,
- &QbssLoad, LenVIE,
- pVIE);
- if (Idx != BSS_NOT_FOUND) {
- NdisMoveMemory(pAd->ScanTab.
- BssEntry[Idx].
- PTSF,
- &Elem->Msg[24],
- 4);
- NdisMoveMemory(&pAd->ScanTab.
- BssEntry[Idx].
- TTSF[0],
- &Elem->TimeStamp.
- u.LowPart, 4);
- NdisMoveMemory(&pAd->ScanTab.
- BssEntry[Idx].
- TTSF[4],
- &Elem->TimeStamp.
- u.LowPart, 4);
- CapabilityInfo =
- pAd->ScanTab.BssEntry[Idx].
- CapabilityInfo;
- }
- } else {
- /* */
- /* Multiple SSID case, used correct CapabilityInfo */
- /* */
- CapabilityInfo =
- pAd->ScanTab.BssEntry[Idx].
- CapabilityInfo;
- }
- }
- NdisMoveMemory(pAd->MlmeAux.Bssid, Bssid, MAC_ADDR_LEN);
- pAd->MlmeAux.CapabilityInfo =
- CapabilityInfo & SUPPORTED_CAPABILITY_INFO;
- pAd->MlmeAux.BssType = BssType;
- pAd->MlmeAux.BeaconPeriod = BeaconPeriod;
- pAd->MlmeAux.Channel = Channel;
- pAd->MlmeAux.AtimWin = AtimWin;
- pAd->MlmeAux.CfpPeriod = Cf.CfpPeriod;
- pAd->MlmeAux.CfpMaxDuration = Cf.CfpMaxDuration;
- pAd->MlmeAux.APRalinkIe = RalinkIe;
-
- /* Copy AP's supported rate to MlmeAux for creating association request */
- /* Also filter out not supported rate */
- pAd->MlmeAux.SupRateLen = SupRateLen;
- NdisMoveMemory(pAd->MlmeAux.SupRate, SupRate,
- SupRateLen);
- RTMPCheckRates(pAd, pAd->MlmeAux.SupRate,
- &pAd->MlmeAux.SupRateLen);
- pAd->MlmeAux.ExtRateLen = ExtRateLen;
- NdisMoveMemory(pAd->MlmeAux.ExtRate, ExtRate,
- ExtRateLen);
- RTMPCheckRates(pAd, pAd->MlmeAux.ExtRate,
- &pAd->MlmeAux.ExtRateLen);
-
- NdisZeroMemory(pAd->StaActive.SupportedPhyInfo.MCSSet,
- 16);
-
- if (((pAd->StaCfg.WepStatus != Ndis802_11WEPEnabled)
- && (pAd->StaCfg.WepStatus !=
- Ndis802_11Encryption2Enabled))
- || (pAd->CommonCfg.HT_DisallowTKIP == FALSE)) {
- bAllowNrate = TRUE;
- }
-
- pAd->MlmeAux.NewExtChannelOffset = NewExtChannelOffset;
- pAd->MlmeAux.HtCapabilityLen = HtCapabilityLen;
-
- RTMPZeroMemory(&pAd->MlmeAux.HtCapability,
- SIZE_HT_CAP_IE);
- /* filter out un-supported ht rates */
- if (((HtCapabilityLen > 0) || (PreNHtCapabilityLen > 0))
- && ((pAd->CommonCfg.PhyMode >= PHY_11ABGN_MIXED)
- && (bAllowNrate))) {
- RTMPMoveMemory(&pAd->MlmeAux.AddHtInfo,
- &AddHtInfo, SIZE_ADD_HT_INFO_IE);
-
- /* StaActive.SupportedHtPhy.MCSSet stores Peer AP's 11n Rx capability */
- NdisMoveMemory(pAd->StaActive.SupportedPhyInfo.
- MCSSet, HtCapability.MCSSet, 16);
- pAd->MlmeAux.NewExtChannelOffset =
- NewExtChannelOffset;
- pAd->MlmeAux.HtCapabilityLen = SIZE_HT_CAP_IE;
- pAd->StaActive.SupportedPhyInfo.bHtEnable =
- TRUE;
- if (PreNHtCapabilityLen > 0)
- pAd->StaActive.SupportedPhyInfo.
- bPreNHt = TRUE;
- RTMPCheckHt(pAd, BSSID_WCID, &HtCapability,
- &AddHtInfo);
- /* Copy AP Parameter to StaActive. This is also in LinkUp. */
- DBGPRINT(RT_DEBUG_TRACE,
- ("PeerBeaconAtJoinAction! (MpduDensity=%d, MaxRAmpduFactor=%d, BW=%d)\n",
- pAd->StaActive.SupportedHtPhy.
- MpduDensity,
- pAd->StaActive.SupportedHtPhy.
- MaxRAmpduFactor,
- HtCapability.HtCapInfo.ChannelWidth));
-
- if (AddHtInfoLen > 0) {
- CentralChannel = AddHtInfo.ControlChan;
- /* Check again the Bandwidth capability of this AP. */
- if ((AddHtInfo.ControlChan > 2)
- && (AddHtInfo.AddHtInfo.
- ExtChanOffset == EXTCHA_BELOW)
- && (HtCapability.HtCapInfo.
- ChannelWidth == BW_40)) {
- CentralChannel =
- AddHtInfo.ControlChan - 2;
- } else
- if ((AddHtInfo.AddHtInfo.
- ExtChanOffset == EXTCHA_ABOVE)
- && (HtCapability.HtCapInfo.
- ChannelWidth == BW_40)) {
- CentralChannel =
- AddHtInfo.ControlChan + 2;
- }
- /* Check Error . */
- if (pAd->MlmeAux.CentralChannel !=
- CentralChannel)
- DBGPRINT(RT_DEBUG_ERROR,
- ("PeerBeaconAtJoinAction HT===>Beacon Central Channel = %d, Control Channel = %d. Mlmeaux CentralChannel = %d\n",
- CentralChannel,
- AddHtInfo.ControlChan,
- pAd->MlmeAux.
- CentralChannel));
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("PeerBeaconAtJoinAction HT===>Central Channel = %d, Control Channel = %d, .\n",
- CentralChannel,
- AddHtInfo.ControlChan));
-
- }
-
- } else {
- /* To prevent error, let legacy AP must have same CentralChannel and Channel. */
- if ((HtCapabilityLen == 0)
- && (PreNHtCapabilityLen == 0))
- pAd->MlmeAux.CentralChannel =
- pAd->MlmeAux.Channel;
-
- pAd->StaActive.SupportedPhyInfo.bHtEnable =
- FALSE;
- pAd->MlmeAux.NewExtChannelOffset = 0xff;
- RTMPZeroMemory(&pAd->MlmeAux.HtCapability,
- SIZE_HT_CAP_IE);
- pAd->MlmeAux.HtCapabilityLen = 0;
- RTMPZeroMemory(&pAd->MlmeAux.AddHtInfo,
- SIZE_ADD_HT_INFO_IE);
- }
-
- RTMPUpdateMlmeRate(pAd);
-
- /* copy QOS related information */
- if ((pAd->CommonCfg.bWmmCapable)
- || (pAd->CommonCfg.PhyMode >= PHY_11ABGN_MIXED)
- ) {
- NdisMoveMemory(&pAd->MlmeAux.APEdcaParm,
- &EdcaParm, sizeof(struct rt_edca_parm));
- NdisMoveMemory(&pAd->MlmeAux.APQbssLoad,
- &QbssLoad,
- sizeof(struct rt_qbss_load_parm));
- NdisMoveMemory(&pAd->MlmeAux.APQosCapability,
- &QosCapability,
- sizeof(struct rt_qos_capability_parm));
- } else {
- NdisZeroMemory(&pAd->MlmeAux.APEdcaParm,
- sizeof(struct rt_edca_parm));
- NdisZeroMemory(&pAd->MlmeAux.APQbssLoad,
- sizeof(struct rt_qbss_load_parm));
- NdisZeroMemory(&pAd->MlmeAux.APQosCapability,
- sizeof(struct rt_qos_capability_parm));
- }
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("SYNC - after JOIN, SupRateLen=%d, ExtRateLen=%d\n",
- pAd->MlmeAux.SupRateLen,
- pAd->MlmeAux.ExtRateLen));
-
- if (AironetCellPowerLimit != 0xFF) {
- /*We need to change our TxPower for CCX 2.0 AP Control of Client Transmit Power */
- ChangeToCellPowerLimit(pAd,
- AironetCellPowerLimit);
- } else /*Used the default TX Power Percentage. */
- pAd->CommonCfg.TxPowerPercentage =
- pAd->CommonCfg.TxPowerDefault;
-
- pAd->Mlme.SyncMachine.CurrState = SYNC_IDLE;
- Status = MLME_SUCCESS;
- MlmeEnqueue(pAd, MLME_CNTL_STATE_MACHINE, MT2_JOIN_CONF,
- 2, &Status);
- }
- /* not to me BEACON, ignored */
- }
- /* sanity check fail, ignore this frame */
-}
-
-/*
- ==========================================================================
- Description:
- receive BEACON from peer
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
- */
-void PeerBeacon(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
- u8 Bssid[MAC_ADDR_LEN], Addr2[MAC_ADDR_LEN];
- char Ssid[MAX_LEN_OF_SSID];
- struct rt_cf_parm CfParm;
- u8 SsidLen, MessageToMe = 0, BssType, Channel, NewChannel, index = 0;
- u8 DtimCount = 0, DtimPeriod = 0, BcastFlag = 0;
- u16 CapabilityInfo, AtimWin, BeaconPeriod;
- LARGE_INTEGER TimeStamp;
- u16 TbttNumToNextWakeUp;
- u8 Erp;
- u8 SupRate[MAX_LEN_OF_SUPPORTED_RATES],
- ExtRate[MAX_LEN_OF_SUPPORTED_RATES];
- u8 SupRateLen, ExtRateLen;
- u8 CkipFlag;
- u16 LenVIE;
- u8 AironetCellPowerLimit;
- struct rt_edca_parm EdcaParm;
- struct rt_qbss_load_parm QbssLoad;
- struct rt_qos_capability_parm QosCapability;
- unsigned long RalinkIe;
- /* New for WPA security suites */
- u8 VarIE[MAX_VIE_LEN]; /* Total VIE length = MAX_VIE_LEN - -5 */
- struct rt_ndis_802_11_variable_ies *pVIE = NULL;
- struct rt_ht_capability_ie HtCapability;
- struct rt_add_ht_info_ie AddHtInfo; /* AP might use this additional ht info IE */
- u8 HtCapabilityLen, PreNHtCapabilityLen;
- u8 AddHtInfoLen;
- u8 NewExtChannelOffset = 0xff;
-
- if (!(INFRA_ON(pAd) || ADHOC_ON(pAd)
- ))
- return;
-
- /* Init Variable IE structure */
- pVIE = (struct rt_ndis_802_11_variable_ies *)VarIE;
- pVIE->Length = 0;
- RTMPZeroMemory(&HtCapability, sizeof(HtCapability));
- RTMPZeroMemory(&AddHtInfo, sizeof(struct rt_add_ht_info_ie));
-
- if (PeerBeaconAndProbeRspSanity(pAd,
- Elem->Msg,
- Elem->MsgLen,
- Elem->Channel,
- Addr2,
- Bssid,
- Ssid,
- &SsidLen,
- &BssType,
- &BeaconPeriod,
- &Channel,
- &NewChannel,
- &TimeStamp,
- &CfParm,
- &AtimWin,
- &CapabilityInfo,
- &Erp,
- &DtimCount,
- &DtimPeriod,
- &BcastFlag,
- &MessageToMe,
- SupRate,
- &SupRateLen,
- ExtRate,
- &ExtRateLen,
- &CkipFlag,
- &AironetCellPowerLimit,
- &EdcaParm,
- &QbssLoad,
- &QosCapability,
- &RalinkIe,
- &HtCapabilityLen,
- &PreNHtCapabilityLen,
- &HtCapability,
- &AddHtInfoLen,
- &AddHtInfo,
- &NewExtChannelOffset, &LenVIE, pVIE)) {
- BOOLEAN is_my_bssid, is_my_ssid;
- unsigned long Bssidx, Now;
- struct rt_bss_entry *pBss;
- char RealRssi =
- RTMPMaxRssi(pAd, ConvertToRssi(pAd, Elem->Rssi0, RSSI_0),
- ConvertToRssi(pAd, Elem->Rssi1, RSSI_1),
- ConvertToRssi(pAd, Elem->Rssi2, RSSI_2));
-
- is_my_bssid =
- MAC_ADDR_EQUAL(Bssid, pAd->CommonCfg.Bssid) ? TRUE : FALSE;
- is_my_ssid =
- SSID_EQUAL(Ssid, SsidLen, pAd->CommonCfg.Ssid,
- pAd->CommonCfg.SsidLen) ? TRUE : FALSE;
-
- /* ignore BEACON not for my SSID */
- if ((!is_my_ssid) && (!is_my_bssid))
- return;
-
- /* It means STA waits disassoc completely from this AP, ignores this beacon. */
- if (pAd->Mlme.CntlMachine.CurrState == CNTL_WAIT_DISASSOC)
- return;
-
- /* Copy Control channel for this BSSID. */
- if (AddHtInfoLen != 0)
- Channel = AddHtInfo.ControlChan;
-
- if ((HtCapabilityLen > 0) || (PreNHtCapabilityLen > 0))
- HtCapabilityLen = SIZE_HT_CAP_IE;
-
- /* */
- /* Housekeeping "SsidBssTab" table for later-on ROAMing usage. */
- /* */
- Bssidx = BssTableSearch(&pAd->ScanTab, Bssid, Channel);
- if (Bssidx == BSS_NOT_FOUND) {
- /* discover new AP of this network, create BSS entry */
- Bssidx =
- BssTableSetEntry(pAd, &pAd->ScanTab, Bssid, Ssid,
- SsidLen, BssType, BeaconPeriod,
- &CfParm, AtimWin, CapabilityInfo,
- SupRate, SupRateLen, ExtRate,
- ExtRateLen, &HtCapability,
- &AddHtInfo, HtCapabilityLen,
- AddHtInfoLen, NewExtChannelOffset,
- Channel, RealRssi, TimeStamp,
- CkipFlag, &EdcaParm,
- &QosCapability, &QbssLoad, LenVIE,
- pVIE);
- if (Bssidx == BSS_NOT_FOUND) /* return if BSS table full */
- return;
-
- NdisMoveMemory(pAd->ScanTab.BssEntry[Bssidx].PTSF,
- &Elem->Msg[24], 4);
- NdisMoveMemory(&pAd->ScanTab.BssEntry[Bssidx].TTSF[0],
- &Elem->TimeStamp.u.LowPart, 4);
- NdisMoveMemory(&pAd->ScanTab.BssEntry[Bssidx].TTSF[4],
- &Elem->TimeStamp.u.LowPart, 4);
-
- }
-
- if ((pAd->CommonCfg.bIEEE80211H == 1) && (NewChannel != 0)
- && (Channel != NewChannel)) {
- /* Switching to channel 1 can prevent from rescanning the current channel immediately (by auto reconnection). */
- /* In addition, clear the MLME queue and the scan table to discard the RX packets and previous scanning results. */
- AsicSwitchChannel(pAd, 1, FALSE);
- AsicLockChannel(pAd, 1);
- LinkDown(pAd, FALSE);
- MlmeQueueInit(&pAd->Mlme.Queue);
- BssTableInit(&pAd->ScanTab);
- RTMPusecDelay(1000000); /* use delay to prevent STA do reassoc */
-
- /* channel sanity check */
- for (index = 0; index < pAd->ChannelListNum; index++) {
- if (pAd->ChannelList[index].Channel ==
- NewChannel) {
- pAd->ScanTab.BssEntry[Bssidx].Channel =
- NewChannel;
- pAd->CommonCfg.Channel = NewChannel;
- AsicSwitchChannel(pAd,
- pAd->CommonCfg.
- Channel, FALSE);
- AsicLockChannel(pAd,
- pAd->CommonCfg.Channel);
- DBGPRINT(RT_DEBUG_TRACE,
- ("PeerBeacon - STA receive channel switch announcement IE (New Channel =%d)\n",
- NewChannel));
- break;
- }
- }
-
- if (index >= pAd->ChannelListNum) {
- DBGPRINT_ERR("PeerBeacon(can not find New Channel=%d in ChannelList[%d]\n", pAd->CommonCfg.Channel, pAd->ChannelListNum);
- }
- }
- /* if the ssid matched & bssid unmatched, we should select the bssid with large value. */
- /* This might happened when two STA start at the same time */
- if ((!is_my_bssid) && ADHOC_ON(pAd)) {
- int i;
-
- /* Add the safeguard against the mismatch of adhoc wep status */
- if (pAd->StaCfg.WepStatus !=
- pAd->ScanTab.BssEntry[Bssidx].WepStatus) {
- return;
- }
- /* collapse into the ADHOC network which has bigger BSSID value. */
- for (i = 0; i < 6; i++) {
- if (Bssid[i] > pAd->CommonCfg.Bssid[i]) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("SYNC - merge to the IBSS "
- "with bigger BSSID="
- "%pM\n", Bssid));
- AsicDisableSync(pAd);
- COPY_MAC_ADDR(pAd->CommonCfg.Bssid,
- Bssid);
- AsicSetBssid(pAd, pAd->CommonCfg.Bssid);
- MakeIbssBeacon(pAd); /* re-build BEACON frame */
- AsicEnableIbssSync(pAd); /* copy BEACON frame to on-chip memory */
- is_my_bssid = TRUE;
- break;
- } else if (Bssid[i] < pAd->CommonCfg.Bssid[i])
- break;
- }
- }
-
- NdisGetSystemUpTime(&Now);
- pBss = &pAd->ScanTab.BssEntry[Bssidx];
- pBss->Rssi = RealRssi; /* lastest RSSI */
- pBss->LastBeaconRxTime = Now; /* last RX timestamp */
-
- /* */
- /* BEACON from my BSSID - either IBSS or INFRA network */
- /* */
- if (is_my_bssid) {
- struct rt_rxwi RxWI;
-
- pAd->StaCfg.DtimCount = DtimCount;
- pAd->StaCfg.DtimPeriod = DtimPeriod;
- pAd->StaCfg.LastBeaconRxTime = Now;
-
- RxWI.RSSI0 = Elem->Rssi0;
- RxWI.RSSI1 = Elem->Rssi1;
- RxWI.RSSI2 = Elem->Rssi2;
-
- Update_Rssi_Sample(pAd, &pAd->StaCfg.RssiSample, &RxWI);
- if (AironetCellPowerLimit != 0xFF) {
- /* */
- /* We get the Cisco (ccx) "TxPower Limit" required */
- /* Changed to appropriate TxPower Limit for Ciso Compatible Extensions */
- /* */
- ChangeToCellPowerLimit(pAd,
- AironetCellPowerLimit);
- } else {
- /* */
- /* AironetCellPowerLimit equal to 0xFF means the Cisco (ccx) "TxPower Limit" not exist. */
- /* Used the default TX Power Percentage, that set from UI. */
- /* */
- pAd->CommonCfg.TxPowerPercentage =
- pAd->CommonCfg.TxPowerDefault;
- }
-
- if (ADHOC_ON(pAd) && (CAP_IS_IBSS_ON(CapabilityInfo))) {
- u8 MaxSupportedRateIn500Kbps = 0;
- u8 idx;
- struct rt_mac_table_entry *pEntry;
-
- /* supported rates array may not be sorted. sort it and find the maximum rate */
- for (idx = 0; idx < SupRateLen; idx++) {
- if (MaxSupportedRateIn500Kbps <
- (SupRate[idx] & 0x7f))
- MaxSupportedRateIn500Kbps =
- SupRate[idx] & 0x7f;
- }
-
- for (idx = 0; idx < ExtRateLen; idx++) {
- if (MaxSupportedRateIn500Kbps <
- (ExtRate[idx] & 0x7f))
- MaxSupportedRateIn500Kbps =
- ExtRate[idx] & 0x7f;
- }
-
- /* look up the existing table */
- pEntry = MacTableLookup(pAd, Addr2);
-
- /* Ad-hoc mode is using MAC address as BA session. So we need to continuously find newly joined adhoc station by receiving beacon. */
- /* To prevent always check this, we use wcid == RESERVED_WCID to recognize it as newly joined adhoc station. */
- if ((ADHOC_ON(pAd)
- && (Elem->Wcid == RESERVED_WCID))
- || (pEntry
- &&
- ((pEntry->LastBeaconRxTime +
- ADHOC_ENTRY_BEACON_LOST_TIME) <
- Now))) {
- if (pEntry == NULL)
- /* Another adhoc joining, add to our MAC table. */
- pEntry =
- MacTableInsertEntry(pAd,
- Addr2,
- BSS0,
- FALSE);
-
- if (StaAddMacTableEntry(pAd,
- pEntry,
- MaxSupportedRateIn500Kbps,
- &HtCapability,
- HtCapabilityLen,
- &AddHtInfo,
- AddHtInfoLen,
- CapabilityInfo)
- == FALSE) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("ADHOC - Add Entry failed.\n"));
- return;
- }
-
- if (pEntry &&
- (Elem->Wcid == RESERVED_WCID)) {
- idx = pAd->StaCfg.DefaultKeyId;
- RTMP_STA_SECURITY_INFO_ADD(pAd,
- BSS0,
- idx,
- pEntry);
- }
- }
-
- if (pEntry && pEntry->ValidAsCLI)
- pEntry->LastBeaconRxTime = Now;
-
- /* At least another peer in this IBSS, declare MediaState as CONNECTED */
- if (!OPSTATUS_TEST_FLAG
- (pAd, fOP_STATUS_MEDIA_STATE_CONNECTED)) {
- OPSTATUS_SET_FLAG(pAd,
- fOP_STATUS_MEDIA_STATE_CONNECTED);
-
- pAd->IndicateMediaState =
- NdisMediaStateConnected;
- RTMP_IndicateMediaState(pAd);
- pAd->ExtraInfo = GENERAL_LINK_UP;
- AsicSetBssid(pAd, pAd->CommonCfg.Bssid);
-
- /* 2003/03/12 - john */
- /* Make sure this entry in "ScanTab" table, thus complies to Microsoft's policy that */
- /* "site survey" result should always include the current connected network. */
- /* */
- Bssidx =
- BssTableSearch(&pAd->ScanTab, Bssid,
- Channel);
- if (Bssidx == BSS_NOT_FOUND) {
- Bssidx =
- BssTableSetEntry(pAd,
- &pAd->
- ScanTab,
- Bssid,
- Ssid,
- SsidLen,
- BssType,
- BeaconPeriod,
- &CfParm,
- AtimWin,
- CapabilityInfo,
- SupRate,
- SupRateLen,
- ExtRate,
- ExtRateLen,
- &HtCapability,
- &AddHtInfo,
- HtCapabilityLen,
- AddHtInfoLen,
- NewExtChannelOffset,
- Channel,
- RealRssi,
- TimeStamp,
- 0,
- &EdcaParm,
- &QosCapability,
- &QbssLoad,
- LenVIE,
- pVIE);
- }
- DBGPRINT(RT_DEBUG_TRACE,
- ("ADHOC fOP_STATUS_MEDIA_STATE_CONNECTED.\n"));
- }
- }
-
- if (INFRA_ON(pAd)) {
- BOOLEAN bUseShortSlot, bUseBGProtection;
-
- /* decide to use/change to - */
- /* 1. long slot (20 us) or short slot (9 us) time */
- /* 2. turn on/off RTS/CTS and/or CTS-to-self protection */
- /* 3. short preamble */
-
- /*bUseShortSlot = pAd->CommonCfg.bUseShortSlotTime && CAP_IS_SHORT_SLOT(CapabilityInfo); */
- bUseShortSlot =
- CAP_IS_SHORT_SLOT(CapabilityInfo);
- if (bUseShortSlot !=
- OPSTATUS_TEST_FLAG(pAd,
- fOP_STATUS_SHORT_SLOT_INUSED))
- AsicSetSlotTime(pAd, bUseShortSlot);
-
- bUseBGProtection = (pAd->CommonCfg.UseBGProtection == 1) || /* always use */
- ((pAd->CommonCfg.UseBGProtection == 0)
- && ERP_IS_USE_PROTECTION(Erp));
-
- if (pAd->CommonCfg.Channel > 14) /* always no BG protection in A-band. falsely happened when switching A/G band to a dual-band AP */
- bUseBGProtection = FALSE;
-
- if (bUseBGProtection !=
- OPSTATUS_TEST_FLAG(pAd,
- fOP_STATUS_BG_PROTECTION_INUSED))
- {
- if (bUseBGProtection) {
- OPSTATUS_SET_FLAG(pAd,
- fOP_STATUS_BG_PROTECTION_INUSED);
- AsicUpdateProtect(pAd,
- pAd->MlmeAux.
- AddHtInfo.
- AddHtInfo2.
- OperaionMode,
- (OFDMSETPROTECT
- |
- CCKSETPROTECT
- |
- ALLN_SETPROTECT),
- FALSE,
- (pAd->MlmeAux.
- AddHtInfo.
- AddHtInfo2.
- NonGfPresent
- == 1));
- } else {
- OPSTATUS_CLEAR_FLAG(pAd,
- fOP_STATUS_BG_PROTECTION_INUSED);
- AsicUpdateProtect(pAd,
- pAd->MlmeAux.
- AddHtInfo.
- AddHtInfo2.
- OperaionMode,
- (OFDMSETPROTECT
- |
- CCKSETPROTECT
- |
- ALLN_SETPROTECT),
- TRUE,
- (pAd->MlmeAux.
- AddHtInfo.
- AddHtInfo2.
- NonGfPresent
- == 1));
- }
-
- DBGPRINT(RT_DEBUG_WARN,
- ("SYNC - AP changed B/G protection to %d\n",
- bUseBGProtection));
- }
- /* check Ht protection mode. and adhere to the Non-GF device indication by AP. */
- if ((AddHtInfoLen != 0) &&
- ((AddHtInfo.AddHtInfo2.OperaionMode !=
- pAd->MlmeAux.AddHtInfo.AddHtInfo2.
- OperaionMode)
- || (AddHtInfo.AddHtInfo2.NonGfPresent !=
- pAd->MlmeAux.AddHtInfo.AddHtInfo2.
- NonGfPresent))) {
- pAd->MlmeAux.AddHtInfo.AddHtInfo2.
- NonGfPresent =
- AddHtInfo.AddHtInfo2.NonGfPresent;
- pAd->MlmeAux.AddHtInfo.AddHtInfo2.
- OperaionMode =
- AddHtInfo.AddHtInfo2.OperaionMode;
- if (pAd->MlmeAux.AddHtInfo.AddHtInfo2.
- NonGfPresent == 1) {
- AsicUpdateProtect(pAd,
- pAd->MlmeAux.
- AddHtInfo.
- AddHtInfo2.
- OperaionMode,
- ALLN_SETPROTECT,
- FALSE, TRUE);
- } else
- AsicUpdateProtect(pAd,
- pAd->MlmeAux.
- AddHtInfo.
- AddHtInfo2.
- OperaionMode,
- ALLN_SETPROTECT,
- FALSE, FALSE);
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("SYNC - AP changed N OperaionMode to %d\n",
- pAd->MlmeAux.AddHtInfo.
- AddHtInfo2.OperaionMode));
- }
-
- if (OPSTATUS_TEST_FLAG
- (pAd, fOP_STATUS_SHORT_PREAMBLE_INUSED)
- && ERP_IS_USE_BARKER_PREAMBLE(Erp)) {
- MlmeSetTxPreamble(pAd,
- Rt802_11PreambleLong);
- DBGPRINT(RT_DEBUG_TRACE,
- ("SYNC - AP forced to use long preamble\n"));
- }
-
- if (OPSTATUS_TEST_FLAG
- (pAd, fOP_STATUS_WMM_INUSED)
- && (EdcaParm.bValid == TRUE)
- && (EdcaParm.EdcaUpdateCount !=
- pAd->CommonCfg.APEdcaParm.
- EdcaUpdateCount)) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("SYNC - AP change EDCA parameters(from %d to %d)\n",
- pAd->CommonCfg.APEdcaParm.
- EdcaUpdateCount,
- EdcaParm.EdcaUpdateCount));
- AsicSetEdcaParm(pAd, &EdcaParm);
- }
- /* copy QOS related information */
- NdisMoveMemory(&pAd->CommonCfg.APQbssLoad,
- &QbssLoad,
- sizeof(struct rt_qbss_load_parm));
- NdisMoveMemory(&pAd->CommonCfg.APQosCapability,
- &QosCapability,
- sizeof(struct rt_qos_capability_parm));
- }
- /* only INFRASTRUCTURE mode support power-saving feature */
- if ((INFRA_ON(pAd) && (pAd->StaCfg.Psm == PWR_SAVE))
- || (pAd->CommonCfg.bAPSDForcePowerSave)) {
- u8 FreeNumber;
- /* 1. AP has backlogged unicast-to-me frame, stay AWAKE, send PSPOLL */
- /* 2. AP has backlogged broadcast/multicast frame and we want those frames, stay AWAKE */
- /* 3. we have outgoing frames in TxRing or MgmtRing, better stay AWAKE */
- /* 4. Psm change to PWR_SAVE, but AP not been informed yet, we better stay AWAKE */
- /* 5. otherwise, put PHY back to sleep to save battery. */
- if (MessageToMe) {
-#ifdef RTMP_MAC_PCI
- if (OPSTATUS_TEST_FLAG
- (pAd, fOP_STATUS_PCIE_DEVICE)) {
- /* Restore to correct BBP R3 value */
- if (pAd->Antenna.field.RxPath >
- 1)
- RTMP_BBP_IO_WRITE8_BY_REG_ID
- (pAd, BBP_R3,
- pAd->StaCfg.BBPR3);
- /* Turn clk to 80Mhz. */
- }
-#endif /* RTMP_MAC_PCI // */
- if (pAd->CommonCfg.bAPSDCapable
- && pAd->CommonCfg.APEdcaParm.
- bAPSDCapable
- && pAd->CommonCfg.bAPSDAC_BE
- && pAd->CommonCfg.bAPSDAC_BK
- && pAd->CommonCfg.bAPSDAC_VI
- && pAd->CommonCfg.bAPSDAC_VO) {
- pAd->CommonCfg.
- bNeedSendTriggerFrame =
- TRUE;
- } else
- RTMP_PS_POLL_ENQUEUE(pAd);
- } else if (BcastFlag && (DtimCount == 0)
- && OPSTATUS_TEST_FLAG(pAd,
- fOP_STATUS_RECEIVE_DTIM))
- {
-#ifdef RTMP_MAC_PCI
- if (OPSTATUS_TEST_FLAG
- (pAd, fOP_STATUS_PCIE_DEVICE)) {
- if (pAd->Antenna.field.RxPath >
- 1)
- RTMP_BBP_IO_WRITE8_BY_REG_ID
- (pAd, BBP_R3,
- pAd->StaCfg.BBPR3);
- }
-#endif /* RTMP_MAC_PCI // */
- } else
- if ((pAd->TxSwQueue[QID_AC_BK].Number != 0)
- || (pAd->TxSwQueue[QID_AC_BE].Number !=
- 0)
- || (pAd->TxSwQueue[QID_AC_VI].Number !=
- 0)
- || (pAd->TxSwQueue[QID_AC_VO].Number !=
- 0)
- ||
- (RTMPFreeTXDRequest
- (pAd, QID_AC_BK, TX_RING_SIZE - 1,
- &FreeNumber) != NDIS_STATUS_SUCCESS)
- ||
- (RTMPFreeTXDRequest
- (pAd, QID_AC_BE, TX_RING_SIZE - 1,
- &FreeNumber) != NDIS_STATUS_SUCCESS)
- ||
- (RTMPFreeTXDRequest
- (pAd, QID_AC_VI, TX_RING_SIZE - 1,
- &FreeNumber) != NDIS_STATUS_SUCCESS)
- ||
- (RTMPFreeTXDRequest
- (pAd, QID_AC_VO, TX_RING_SIZE - 1,
- &FreeNumber) != NDIS_STATUS_SUCCESS)
- ||
- (RTMPFreeTXDRequest
- (pAd, QID_MGMT, MGMT_RING_SIZE - 1,
- &FreeNumber) !=
- NDIS_STATUS_SUCCESS)) {
- /* TODO: consider scheduled HCCA. might not be proper to use traditional DTIM-based power-saving scheme */
- /* can we cheat here (i.e. just check MGMT & AC_BE) for better performance? */
-#ifdef RTMP_MAC_PCI
- if (OPSTATUS_TEST_FLAG
- (pAd, fOP_STATUS_PCIE_DEVICE)) {
- if (pAd->Antenna.field.RxPath >
- 1)
- RTMP_BBP_IO_WRITE8_BY_REG_ID
- (pAd, BBP_R3,
- pAd->StaCfg.BBPR3);
- }
-#endif /* RTMP_MAC_PCI // */
- } else {
- if ((pAd->CommonCfg.
- bACMAPSDTr[QID_AC_VO])
- || (pAd->CommonCfg.
- bACMAPSDTr[QID_AC_VI])
- || (pAd->CommonCfg.
- bACMAPSDTr[QID_AC_BK])
- || (pAd->CommonCfg.
- bACMAPSDTr[QID_AC_BE])) {
- /*
- WMM Spec v1.0 3.6.2.4,
- The WMM STA shall remain awake until it receives a
- QoS Data or Null frame addressed to it, with the
- EOSP subfield in QoS Control field set to 1.
-
- So we can not sleep here or we will suffer a case:
-
- PS Management Frame -->
- Trigger frame -->
- Beacon (TIM=0) (Beacon is closer to Trig frame) -->
- Station goes to sleep -->
- AP delivery queued UAPSD packets -->
- Station can NOT receive the reply
-
- Maybe we need a timeout timer to avoid that we do
- NOT receive the EOSP frame.
-
- We can not use More Data to check if SP is ended
- due to MaxSPLength.
- */
- } else {
- u16 NextDtim = DtimCount;
-
- if (NextDtim == 0)
- NextDtim = DtimPeriod;
-
- TbttNumToNextWakeUp =
- pAd->StaCfg.
- DefaultListenCount;
- if (OPSTATUS_TEST_FLAG
- (pAd,
- fOP_STATUS_RECEIVE_DTIM)
- && (TbttNumToNextWakeUp >
- NextDtim))
- TbttNumToNextWakeUp =
- NextDtim;
-
- if (!OPSTATUS_TEST_FLAG
- (pAd, fOP_STATUS_DOZE)) {
- /* Set a flag to go to sleep . Then after parse this RxDoneInterrupt, will go to sleep mode. */
- pAd->
- ThisTbttNumToNextWakeUp
- =
- TbttNumToNextWakeUp;
- AsicSleepThenAutoWakeup
- (pAd,
- pAd->
- ThisTbttNumToNextWakeUp);
- }
- }
- }
- }
- }
- /* not my BSSID, ignore it */
- }
- /* sanity check fail, ignore this frame */
-}
-
-/*
- ==========================================================================
- Description:
- Receive PROBE REQ from remote peer when operating in IBSS mode
- ==========================================================================
- */
-void PeerProbeReqAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
- u8 Addr2[MAC_ADDR_LEN];
- char Ssid[MAX_LEN_OF_SSID];
- u8 SsidLen;
- u8 HtLen, AddHtLen, NewExtLen;
- struct rt_header_802_11 ProbeRspHdr;
- int NStatus;
- u8 *pOutBuffer = NULL;
- unsigned long FrameLen = 0;
- LARGE_INTEGER FakeTimestamp;
- u8 DsLen = 1, IbssLen = 2;
- u8 LocalErpIe[3] = { IE_ERP, 1, 0 };
- BOOLEAN Privacy;
- u16 CapabilityInfo;
- u8 RSNIe = IE_WPA;
-
- if (!ADHOC_ON(pAd))
- return;
-
- if (PeerProbeReqSanity
- (pAd, Elem->Msg, Elem->MsgLen, Addr2, Ssid, &SsidLen)) {
- if ((SsidLen == 0)
- || SSID_EQUAL(Ssid, SsidLen, pAd->CommonCfg.Ssid,
- pAd->CommonCfg.SsidLen)) {
- /* allocate and send out ProbeRsp frame */
- NStatus = MlmeAllocateMemory(pAd, &pOutBuffer); /*Get an unused nonpaged memory */
- if (NStatus != NDIS_STATUS_SUCCESS)
- return;
-
- /*pAd->StaCfg.AtimWin = 0; // ?????? */
-
- Privacy =
- (pAd->StaCfg.WepStatus ==
- Ndis802_11Encryption1Enabled)
- || (pAd->StaCfg.WepStatus ==
- Ndis802_11Encryption2Enabled)
- || (pAd->StaCfg.WepStatus ==
- Ndis802_11Encryption3Enabled);
- CapabilityInfo =
- CAP_GENERATE(0, 1, Privacy,
- (pAd->CommonCfg.TxPreamble ==
- Rt802_11PreambleShort), 0, 0);
-
- MakeOutgoingFrame(pOutBuffer, &FrameLen,
- sizeof(struct rt_header_802_11), &ProbeRspHdr,
- TIMESTAMP_LEN, &FakeTimestamp,
- 2, &pAd->CommonCfg.BeaconPeriod,
- 2, &CapabilityInfo,
- 1, &SsidIe,
- 1, &pAd->CommonCfg.SsidLen,
- pAd->CommonCfg.SsidLen,
- pAd->CommonCfg.Ssid, 1, &SupRateIe, 1,
- &pAd->StaActive.SupRateLen,
- pAd->StaActive.SupRateLen,
- pAd->StaActive.SupRate, 1, &DsIe, 1,
- &DsLen, 1, &pAd->CommonCfg.Channel, 1,
- &IbssIe, 1, &IbssLen, 2,
- &pAd->StaActive.AtimWin, END_OF_ARGS);
-
- if (pAd->StaActive.ExtRateLen) {
- unsigned long tmp;
- MakeOutgoingFrame(pOutBuffer + FrameLen, &tmp,
- 3, LocalErpIe,
- 1, &ExtRateIe,
- 1, &pAd->StaActive.ExtRateLen,
- pAd->StaActive.ExtRateLen,
- &pAd->StaActive.ExtRate,
- END_OF_ARGS);
- FrameLen += tmp;
- }
- /* If adhoc secruity is set for WPA-None, append the cipher suite IE */
- if (pAd->StaCfg.AuthMode == Ndis802_11AuthModeWPANone) {
- unsigned long tmp;
- MakeOutgoingFrame(pOutBuffer + FrameLen, &tmp,
- 1, &RSNIe,
- 1, &pAd->StaCfg.RSNIE_Len,
- pAd->StaCfg.RSNIE_Len,
- pAd->StaCfg.RSN_IE,
- END_OF_ARGS);
- FrameLen += tmp;
- }
-
- if (pAd->CommonCfg.PhyMode >= PHY_11ABGN_MIXED) {
- unsigned long TmpLen;
- u8 BROADCOM[4] = { 0x0, 0x90, 0x4c, 0x33 };
- HtLen = sizeof(pAd->CommonCfg.HtCapability);
- AddHtLen = sizeof(pAd->CommonCfg.AddHTInfo);
- NewExtLen = 1;
- /*New extension channel offset IE is included in Beacon, Probe Rsp or channel Switch Announcement Frame */
- if (pAd->bBroadComHT == TRUE) {
- MakeOutgoingFrame(pOutBuffer + FrameLen,
- &TmpLen, 1, &WpaIe, 4,
- &BROADCOM[0],
- pAd->MlmeAux.
- HtCapabilityLen,
- &pAd->MlmeAux.
- HtCapability,
- END_OF_ARGS);
- } else {
- MakeOutgoingFrame(pOutBuffer + FrameLen,
- &TmpLen, 1, &HtCapIe,
- 1, &HtLen,
- sizeof
- (struct rt_ht_capability_ie),
- &pAd->CommonCfg.
- HtCapability, 1,
- &AddHtInfoIe, 1,
- &AddHtLen,
- sizeof
- (struct rt_add_ht_info_ie),
- &pAd->CommonCfg.
- AddHTInfo, 1,
- &NewExtChanIe, 1,
- &NewExtLen,
- sizeof
- (struct rt_new_ext_chan_ie),
- &pAd->CommonCfg.
- NewExtChanOffset,
- END_OF_ARGS);
- }
- FrameLen += TmpLen;
- }
-
- MiniportMMRequest(pAd, 0, pOutBuffer, FrameLen);
- MlmeFreeMemory(pAd, pOutBuffer);
- }
- }
-}
-
-void BeaconTimeoutAtJoinAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
- u16 Status;
- DBGPRINT(RT_DEBUG_TRACE, ("SYNC - BeaconTimeoutAtJoinAction\n"));
- pAd->Mlme.SyncMachine.CurrState = SYNC_IDLE;
- Status = MLME_REJ_TIMEOUT;
- MlmeEnqueue(pAd, MLME_CNTL_STATE_MACHINE, MT2_JOIN_CONF, 2, &Status);
-}
-
-/*
- ==========================================================================
- Description:
- Scan timeout procedure. basically add channel index by 1 and rescan
- ==========================================================================
- */
-void ScanTimeoutAction(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
- pAd->MlmeAux.Channel = NextChannel(pAd, pAd->MlmeAux.Channel);
-
- /* Only one channel scanned for CISCO beacon request */
- if ((pAd->MlmeAux.ScanType == SCAN_CISCO_ACTIVE) ||
- (pAd->MlmeAux.ScanType == SCAN_CISCO_PASSIVE) ||
- (pAd->MlmeAux.ScanType == SCAN_CISCO_NOISE) ||
- (pAd->MlmeAux.ScanType == SCAN_CISCO_CHANNEL_LOAD))
- pAd->MlmeAux.Channel = 0;
-
- /* this routine will stop if pAd->MlmeAux.Channel == 0 */
- ScanNextChannel(pAd);
-}
-
-/*
- ==========================================================================
- Description:
- ==========================================================================
- */
-void InvalidStateWhenScan(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
- u16 Status;
- DBGPRINT(RT_DEBUG_TRACE,
- ("AYNC - InvalidStateWhenScan(state=%ld). Reset SYNC machine\n",
- pAd->Mlme.SyncMachine.CurrState));
- pAd->Mlme.SyncMachine.CurrState = SYNC_IDLE;
- Status = MLME_STATE_MACHINE_REJECT;
- MlmeEnqueue(pAd, MLME_CNTL_STATE_MACHINE, MT2_SCAN_CONF, 2, &Status);
-}
-
-/*
- ==========================================================================
- Description:
- ==========================================================================
- */
-void InvalidStateWhenJoin(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
- u16 Status;
- DBGPRINT(RT_DEBUG_TRACE,
- ("InvalidStateWhenJoin(state=%ld). Reset SYNC machine\n",
- pAd->Mlme.SyncMachine.CurrState));
- pAd->Mlme.SyncMachine.CurrState = SYNC_IDLE;
- Status = MLME_STATE_MACHINE_REJECT;
- MlmeEnqueue(pAd, MLME_CNTL_STATE_MACHINE, MT2_JOIN_CONF, 2, &Status);
-}
-
-/*
- ==========================================================================
- Description:
- ==========================================================================
- */
-void InvalidStateWhenStart(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
- u16 Status;
- DBGPRINT(RT_DEBUG_TRACE,
- ("InvalidStateWhenStart(state=%ld). Reset SYNC machine\n",
- pAd->Mlme.SyncMachine.CurrState));
- pAd->Mlme.SyncMachine.CurrState = SYNC_IDLE;
- Status = MLME_STATE_MACHINE_REJECT;
- MlmeEnqueue(pAd, MLME_CNTL_STATE_MACHINE, MT2_START_CONF, 2, &Status);
-}
-
-/*
- ==========================================================================
- Description:
-
- IRQL = DISPATCH_LEVEL
-
- ==========================================================================
- */
-void EnqueuePsPoll(struct rt_rtmp_adapter *pAd)
-{
-
- if (pAd->StaCfg.WindowsPowerMode == Ndis802_11PowerModeLegacy_PSP)
- pAd->PsPollFrame.FC.PwrMgmt = PWR_SAVE;
- MiniportMMRequest(pAd, 0, (u8 *)& pAd->PsPollFrame,
- sizeof(struct rt_pspoll_frame));
-}
-
-/*
- ==========================================================================
- Description:
- ==========================================================================
- */
-void EnqueueProbeRequest(struct rt_rtmp_adapter *pAd)
-{
- int NState;
- u8 *pOutBuffer;
- unsigned long FrameLen = 0;
- struct rt_header_802_11 Hdr80211;
-
- DBGPRINT(RT_DEBUG_TRACE, ("force out a ProbeRequest ...\n"));
-
- NState = MlmeAllocateMemory(pAd, &pOutBuffer); /*Get an unused nonpaged memory */
- if (NState == NDIS_STATUS_SUCCESS) {
- MgtMacHeaderInit(pAd, &Hdr80211, SUBTYPE_PROBE_REQ, 0,
- BROADCAST_ADDR, BROADCAST_ADDR);
-
- /* this ProbeRequest explicitly specify SSID to reduce unwanted ProbeResponse */
- MakeOutgoingFrame(pOutBuffer, &FrameLen,
- sizeof(struct rt_header_802_11), &Hdr80211,
- 1, &SsidIe,
- 1, &pAd->CommonCfg.SsidLen,
- pAd->CommonCfg.SsidLen, pAd->CommonCfg.Ssid,
- 1, &SupRateIe,
- 1, &pAd->StaActive.SupRateLen,
- pAd->StaActive.SupRateLen,
- pAd->StaActive.SupRate, END_OF_ARGS);
- MiniportMMRequest(pAd, 0, pOutBuffer, FrameLen);
- MlmeFreeMemory(pAd, pOutBuffer);
- }
-
-}
-
-BOOLEAN ScanRunning(struct rt_rtmp_adapter *pAd)
-{
- return (pAd->Mlme.SyncMachine.CurrState == SCAN_LISTEN) ? TRUE : FALSE;
-}
diff --git a/drivers/staging/rt2860/sta/wpa.c b/drivers/staging/rt2860/sta/wpa.c
deleted file mode 100644
index ff34832..0000000
--- a/drivers/staging/rt2860/sta/wpa.c
+++ /dev/null
@@ -1,374 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- wpa.c
-
- Abstract:
-
- Revision History:
- Who When What
- -------- ---------- ----------------------------------------------
- Jan Lee 03-07-22 Initial
- Paul Lin 03-11-28 Modify for supplicant
- Justin P. Mattock 11/07/2010 Fix typos
-*/
-#include "../rt_config.h"
-
-void inc_byte_array(u8 * counter, int len);
-
-/*
- ========================================================================
-
- Routine Description:
- Process MIC error indication and record MIC error timer.
-
- Arguments:
- pAd Pointer to our adapter
- pWpaKey Pointer to the WPA key structure
-
- Return Value:
- None
-
- IRQL = DISPATCH_LEVEL
-
- Note:
-
- ========================================================================
-*/
-void RTMPReportMicError(struct rt_rtmp_adapter *pAd, struct rt_cipher_key *pWpaKey)
-{
- unsigned long Now;
- u8 unicastKey = (pWpaKey->Type == PAIRWISE_KEY ? 1 : 0);
-
- /* Record Last MIC error time and count */
- NdisGetSystemUpTime(&Now);
- if (pAd->StaCfg.MicErrCnt == 0) {
- pAd->StaCfg.MicErrCnt++;
- pAd->StaCfg.LastMicErrorTime = Now;
- NdisZeroMemory(pAd->StaCfg.ReplayCounter, 8);
- } else if (pAd->StaCfg.MicErrCnt == 1) {
- if ((pAd->StaCfg.LastMicErrorTime + (60 * OS_HZ)) < Now) {
- /* Update Last MIC error time, this did not violate two MIC errors within 60 seconds */
- pAd->StaCfg.LastMicErrorTime = Now;
- } else {
-
- if (pAd->CommonCfg.bWirelessEvent)
- RTMPSendWirelessEvent(pAd,
- IW_COUNTER_MEASURES_EVENT_FLAG,
- pAd->MacTab.
- Content[BSSID_WCID].Addr,
- BSS0, 0);
-
- pAd->StaCfg.LastMicErrorTime = Now;
- /* Violate MIC error counts, MIC countermeasures kicks in */
- pAd->StaCfg.MicErrCnt++;
- /* We shall block all reception */
- /* We shall clean all Tx ring and disassociate from AP after next EAPOL frame */
- /* */
- /* No necessary to clean all Tx ring, on RTMPHardTransmit will stop sending non-802.1X EAPOL packets */
- /* if pAd->StaCfg.MicErrCnt greater than 2. */
- /* */
- /* RTMPRingCleanUp(pAd, QID_AC_BK); */
- /* RTMPRingCleanUp(pAd, QID_AC_BE); */
- /* RTMPRingCleanUp(pAd, QID_AC_VI); */
- /* RTMPRingCleanUp(pAd, QID_AC_VO); */
- /* RTMPRingCleanUp(pAd, QID_HCCA); */
- }
- } else {
- /* MIC error count >= 2 */
- /* This should not happen */
- ;
- }
- MlmeEnqueue(pAd,
- MLME_CNTL_STATE_MACHINE,
- OID_802_11_MIC_FAILURE_REPORT_FRAME, 1, &unicastKey);
-
- if (pAd->StaCfg.MicErrCnt == 2) {
- RTMPSetTimer(&pAd->StaCfg.WpaDisassocAndBlockAssocTimer, 100);
- }
-}
-
-#define LENGTH_EAP_H 4
-/* If the received frame is EAP-Packet ,find out its EAP-Code (Request(0x01), Response(0x02), Success(0x03), Failure(0x04)). */
-int WpaCheckEapCode(struct rt_rtmp_adapter *pAd,
- u8 *pFrame, u16 FrameLen, u16 OffSet)
-{
-
- u8 *pData;
- int result = 0;
-
- if (FrameLen < OffSet + LENGTH_EAPOL_H + LENGTH_EAP_H)
- return result;
-
- pData = pFrame + OffSet; /* skip offset bytes */
-
- if (*(pData + 1) == EAPPacket) /* 802.1x header - Packet Type */
- {
- result = *(pData + 4); /* EAP header - Code */
- }
-
- return result;
-}
-
-void WpaSendMicFailureToWpaSupplicant(struct rt_rtmp_adapter *pAd, IN BOOLEAN bUnicast)
-{
- char custom[IW_CUSTOM_MAX] = { 0 };
-
- sprintf(custom, "MLME-MICHAELMICFAILURE.indication");
- if (bUnicast)
- sprintf(custom, "%s unicast", custom);
-
- RtmpOSWrielessEventSend(pAd, IWEVCUSTOM, -1, NULL, (u8 *)custom,
- strlen(custom));
-
- return;
-}
-
-void WpaMicFailureReportFrame(struct rt_rtmp_adapter *pAd, struct rt_mlme_queue_elem *Elem)
-{
- u8 *pOutBuffer = NULL;
- u8 Header802_3[14];
- unsigned long FrameLen = 0;
- struct rt_eapol_packet Packet;
- u8 Mic[16];
- BOOLEAN bUnicast;
-
- DBGPRINT(RT_DEBUG_TRACE, ("WpaMicFailureReportFrame ----->\n"));
-
- bUnicast = (Elem->Msg[0] == 1 ? TRUE : FALSE);
- pAd->Sequence = ((pAd->Sequence) + 1) & (MAX_SEQ_NUMBER);
-
- /* init 802.3 header and Fill Packet */
- MAKE_802_3_HEADER(Header802_3, pAd->CommonCfg.Bssid,
- pAd->CurrentAddress, EAPOL);
-
- NdisZeroMemory(&Packet, sizeof(Packet));
- Packet.ProVer = EAPOL_VER;
- Packet.ProType = EAPOLKey;
-
- Packet.KeyDesc.Type = WPA1_KEY_DESC;
-
- /* Request field presented */
- Packet.KeyDesc.KeyInfo.Request = 1;
-
- if (pAd->StaCfg.WepStatus == Ndis802_11Encryption3Enabled) {
- Packet.KeyDesc.KeyInfo.KeyDescVer = 2;
- } else /* TKIP */
- {
- Packet.KeyDesc.KeyInfo.KeyDescVer = 1;
- }
-
- Packet.KeyDesc.KeyInfo.KeyType = (bUnicast ? PAIRWISEKEY : GROUPKEY);
-
- /* KeyMic field presented */
- Packet.KeyDesc.KeyInfo.KeyMic = 1;
-
- /* Error field presented */
- Packet.KeyDesc.KeyInfo.Error = 1;
-
- /* Update packet length after decide Key data payload */
- SET_u16_TO_ARRARY(Packet.Body_Len, LEN_EAPOL_KEY_MSG)
- /* Key Replay Count */
- NdisMoveMemory(Packet.KeyDesc.ReplayCounter,
- pAd->StaCfg.ReplayCounter, LEN_KEY_DESC_REPLAY);
- inc_byte_array(pAd->StaCfg.ReplayCounter, 8);
-
- /* Convert to little-endian format. */
- *((u16 *) & Packet.KeyDesc.KeyInfo) =
- cpu2le16(*((u16 *) & Packet.KeyDesc.KeyInfo));
-
- MlmeAllocateMemory(pAd, (u8 **) & pOutBuffer); /* allocate memory */
- if (pOutBuffer == NULL) {
- return;
- }
- /* Prepare EAPOL frame for MIC calculation */
- /* Be careful, only EAPOL frame is counted for MIC calculation */
- MakeOutgoingFrame(pOutBuffer, &FrameLen,
- CONV_ARRARY_TO_u16(Packet.Body_Len) + 4, &Packet,
- END_OF_ARGS);
-
- /* Prepare and Fill MIC value */
- NdisZeroMemory(Mic, sizeof(Mic));
- if (pAd->StaCfg.WepStatus == Ndis802_11Encryption3Enabled) { /* AES */
- u8 digest[20] = { 0 };
- HMAC_SHA1(pAd->StaCfg.PTK, LEN_EAP_MICK, pOutBuffer, FrameLen,
- digest, SHA1_DIGEST_SIZE);
- NdisMoveMemory(Mic, digest, LEN_KEY_DESC_MIC);
- } else { /* TKIP */
- HMAC_MD5(pAd->StaCfg.PTK, LEN_EAP_MICK, pOutBuffer, FrameLen,
- Mic, MD5_DIGEST_SIZE);
- }
- NdisMoveMemory(Packet.KeyDesc.KeyMic, Mic, LEN_KEY_DESC_MIC);
-
- /* copy frame to Tx ring and send MIC failure report frame to authenticator */
- RTMPToWirelessSta(pAd, &pAd->MacTab.Content[BSSID_WCID],
- Header802_3, LENGTH_802_3,
- (u8 *)& Packet,
- CONV_ARRARY_TO_u16(Packet.Body_Len) + 4, FALSE);
-
- MlmeFreeMemory(pAd, (u8 *)pOutBuffer);
-
- DBGPRINT(RT_DEBUG_TRACE, ("WpaMicFailureReportFrame <-----\n"));
-}
-
-/** from wpa_supplicant
- * inc_byte_array - Increment arbitrary length byte array by one
- * @counter: Pointer to byte array
- * @len: Length of the counter in bytes
- *
- * This function increments the last byte of the counter by one and continues
- * rolling over to more significant bytes if the byte was incremented from
- * 0xff to 0x00.
- */
-void inc_byte_array(u8 * counter, int len)
-{
- int pos = len - 1;
- while (pos >= 0) {
- counter[pos]++;
- if (counter[pos] != 0)
- break;
- pos--;
- }
-}
-
-void WpaDisassocApAndBlockAssoc(void *SystemSpecific1,
- void *FunctionContext,
- void *SystemSpecific2,
- void *SystemSpecific3)
-{
- struct rt_rtmp_adapter *pAd = (struct rt_rtmp_adapter *)FunctionContext;
- struct rt_mlme_disassoc_req DisassocReq;
-
- /* disassoc from current AP first */
- DBGPRINT(RT_DEBUG_TRACE,
- ("RTMPReportMicError - disassociate with current AP after sending second continuous EAPOL frame\n"));
- DisassocParmFill(pAd, &DisassocReq, pAd->CommonCfg.Bssid,
- REASON_MIC_FAILURE);
- MlmeEnqueue(pAd, ASSOC_STATE_MACHINE, MT2_MLME_DISASSOC_REQ,
- sizeof(struct rt_mlme_disassoc_req), &DisassocReq);
-
- pAd->Mlme.CntlMachine.CurrState = CNTL_WAIT_DISASSOC;
- pAd->StaCfg.bBlockAssoc = TRUE;
-}
-
-void WpaStaPairwiseKeySetting(struct rt_rtmp_adapter *pAd)
-{
- struct rt_cipher_key *pSharedKey;
- struct rt_mac_table_entry *pEntry;
-
- pEntry = &pAd->MacTab.Content[BSSID_WCID];
-
- /* Pairwise key shall use key#0 */
- pSharedKey = &pAd->SharedKey[BSS0][0];
-
- NdisMoveMemory(pAd->StaCfg.PTK, pEntry->PTK, LEN_PTK);
-
- /* Prepare pair-wise key information into shared key table */
- NdisZeroMemory(pSharedKey, sizeof(struct rt_cipher_key));
- pSharedKey->KeyLen = LEN_TKIP_EK;
- NdisMoveMemory(pSharedKey->Key, &pAd->StaCfg.PTK[32], LEN_TKIP_EK);
- NdisMoveMemory(pSharedKey->RxMic, &pAd->StaCfg.PTK[48],
- LEN_TKIP_RXMICK);
- NdisMoveMemory(pSharedKey->TxMic,
- &pAd->StaCfg.PTK[48 + LEN_TKIP_RXMICK], LEN_TKIP_TXMICK);
-
- /* Decide its ChiperAlg */
- if (pAd->StaCfg.PairCipher == Ndis802_11Encryption2Enabled)
- pSharedKey->CipherAlg = CIPHER_TKIP;
- else if (pAd->StaCfg.PairCipher == Ndis802_11Encryption3Enabled)
- pSharedKey->CipherAlg = CIPHER_AES;
- else
- pSharedKey->CipherAlg = CIPHER_NONE;
-
- /* Update these related information to struct rt_mac_table_entry */
- NdisMoveMemory(pEntry->PairwiseKey.Key, &pAd->StaCfg.PTK[32],
- LEN_TKIP_EK);
- NdisMoveMemory(pEntry->PairwiseKey.RxMic, &pAd->StaCfg.PTK[48],
- LEN_TKIP_RXMICK);
- NdisMoveMemory(pEntry->PairwiseKey.TxMic,
- &pAd->StaCfg.PTK[48 + LEN_TKIP_RXMICK], LEN_TKIP_TXMICK);
- pEntry->PairwiseKey.CipherAlg = pSharedKey->CipherAlg;
-
- /* Update pairwise key information to ASIC Shared Key Table */
- AsicAddSharedKeyEntry(pAd,
- BSS0,
- 0,
- pSharedKey->CipherAlg,
- pSharedKey->Key,
- pSharedKey->TxMic, pSharedKey->RxMic);
-
- /* Update ASIC WCID attribute table and IVEIV table */
- RTMPAddWcidAttributeEntry(pAd, BSS0, 0, pSharedKey->CipherAlg, pEntry);
- STA_PORT_SECURED(pAd);
- pAd->IndicateMediaState = NdisMediaStateConnected;
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("%s : AID(%d) port secured\n", __func__, pEntry->Aid));
-
-}
-
-void WpaStaGroupKeySetting(struct rt_rtmp_adapter *pAd)
-{
- struct rt_cipher_key *pSharedKey;
-
- pSharedKey = &pAd->SharedKey[BSS0][pAd->StaCfg.DefaultKeyId];
-
- /* Prepare pair-wise key information into shared key table */
- NdisZeroMemory(pSharedKey, sizeof(struct rt_cipher_key));
- pSharedKey->KeyLen = LEN_TKIP_EK;
- NdisMoveMemory(pSharedKey->Key, pAd->StaCfg.GTK, LEN_TKIP_EK);
- NdisMoveMemory(pSharedKey->RxMic, &pAd->StaCfg.GTK[16],
- LEN_TKIP_RXMICK);
- NdisMoveMemory(pSharedKey->TxMic, &pAd->StaCfg.GTK[24],
- LEN_TKIP_TXMICK);
-
- /* Update Shared Key CipherAlg */
- pSharedKey->CipherAlg = CIPHER_NONE;
- if (pAd->StaCfg.GroupCipher == Ndis802_11Encryption2Enabled)
- pSharedKey->CipherAlg = CIPHER_TKIP;
- else if (pAd->StaCfg.GroupCipher == Ndis802_11Encryption3Enabled)
- pSharedKey->CipherAlg = CIPHER_AES;
- else if (pAd->StaCfg.GroupCipher == Ndis802_11GroupWEP40Enabled)
- pSharedKey->CipherAlg = CIPHER_WEP64;
- else if (pAd->StaCfg.GroupCipher == Ndis802_11GroupWEP104Enabled)
- pSharedKey->CipherAlg = CIPHER_WEP128;
-
- /* Update group key information to ASIC Shared Key Table */
- AsicAddSharedKeyEntry(pAd,
- BSS0,
- pAd->StaCfg.DefaultKeyId,
- pSharedKey->CipherAlg,
- pSharedKey->Key,
- pSharedKey->TxMic, pSharedKey->RxMic);
-
- /* Update ASIC WCID attribute table and IVEIV table */
- RTMPAddWcidAttributeEntry(pAd,
- BSS0,
- pAd->StaCfg.DefaultKeyId,
- pSharedKey->CipherAlg, NULL);
-
-}
diff --git a/drivers/staging/rt2860/sta_ioctl.c b/drivers/staging/rt2860/sta_ioctl.c
deleted file mode 100644
index 49b1013..0000000
--- a/drivers/staging/rt2860/sta_ioctl.c
+++ /dev/null
@@ -1,2912 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- sta_ioctl.c
-
- Abstract:
- IOCTL related subroutines
-
- Revision History:
- Who When What
- -------- ---------- ----------------------------------------------
- Rory Chen 01-03-2003 created
- Rory Chen 02-14-2005 modify to support RT61
- Justin P. Mattock 11/07/2010 Fix typos
-*/
-
-#include "rt_config.h"
-
-#ifdef DBG
-extern unsigned long RTDebugLevel;
-#endif
-
-#define NR_WEP_KEYS 4
-#define WEP_SMALL_KEY_LEN (40/8)
-#define WEP_LARGE_KEY_LEN (104/8)
-
-#define GROUP_KEY_NO 4
-
-extern u8 CipherWpa2Template[];
-
-struct PACKED rt_version_info {
- u8 DriverVersionW;
- u8 DriverVersionX;
- u8 DriverVersionY;
- u8 DriverVersionZ;
- u32 DriverBuildYear;
- u32 DriverBuildMonth;
- u32 DriverBuildDay;
-};
-
-static __s32 ralinkrate[] = { 2, 4, 11, 22, /* CCK */
- 12, 18, 24, 36, 48, 72, 96, 108, /* OFDM */
- 13, 26, 39, 52, 78, 104, 117, 130, 26, 52, 78, 104, 156, 208, 234, 260, /* 20MHz, 800ns GI, MCS: 0 ~ 15 */
- 39, 78, 117, 156, 234, 312, 351, 390, /* 20MHz, 800ns GI, MCS: 16 ~ 23 */
- 27, 54, 81, 108, 162, 216, 243, 270, 54, 108, 162, 216, 324, 432, 486, 540, /* 40MHz, 800ns GI, MCS: 0 ~ 15 */
- 81, 162, 243, 324, 486, 648, 729, 810, /* 40MHz, 800ns GI, MCS: 16 ~ 23 */
- 14, 29, 43, 57, 87, 115, 130, 144, 29, 59, 87, 115, 173, 230, 260, 288, /* 20MHz, 400ns GI, MCS: 0 ~ 15 */
- 43, 87, 130, 173, 260, 317, 390, 433, /* 20MHz, 400ns GI, MCS: 16 ~ 23 */
- 30, 60, 90, 120, 180, 240, 270, 300, 60, 120, 180, 240, 360, 480, 540, 600, /* 40MHz, 400ns GI, MCS: 0 ~ 15 */
- 90, 180, 270, 360, 540, 720, 810, 900
-};
-
-int Set_SSID_Proc(struct rt_rtmp_adapter *pAdapter, char *arg);
-
-int Set_NetworkType_Proc(struct rt_rtmp_adapter *pAdapter, char *arg);
-
-void RTMPAddKey(struct rt_rtmp_adapter *pAd, struct rt_ndis_802_11_key *pKey)
-{
- unsigned long KeyIdx;
- struct rt_mac_table_entry *pEntry;
-
- DBGPRINT(RT_DEBUG_TRACE, ("RTMPAddKey ------>\n"));
-
- if (pAd->StaCfg.AuthMode >= Ndis802_11AuthModeWPA) {
- if (pKey->KeyIndex & 0x80000000) {
- if (pAd->StaCfg.AuthMode == Ndis802_11AuthModeWPANone) {
- NdisZeroMemory(pAd->StaCfg.PMK, 32);
- NdisMoveMemory(pAd->StaCfg.PMK,
- pKey->KeyMaterial,
- pKey->KeyLength);
- goto end;
- }
- /* Update PTK */
- NdisZeroMemory(&pAd->SharedKey[BSS0][0],
- sizeof(struct rt_cipher_key));
- pAd->SharedKey[BSS0][0].KeyLen = LEN_TKIP_EK;
- NdisMoveMemory(pAd->SharedKey[BSS0][0].Key,
- pKey->KeyMaterial, LEN_TKIP_EK);
-
- if (pAd->StaCfg.PairCipher ==
- Ndis802_11Encryption2Enabled) {
- NdisMoveMemory(pAd->SharedKey[BSS0][0].RxMic,
- pKey->KeyMaterial + LEN_TKIP_EK,
- LEN_TKIP_TXMICK);
- NdisMoveMemory(pAd->SharedKey[BSS0][0].TxMic,
- pKey->KeyMaterial + LEN_TKIP_EK +
- LEN_TKIP_TXMICK,
- LEN_TKIP_RXMICK);
- } else {
- NdisMoveMemory(pAd->SharedKey[BSS0][0].TxMic,
- pKey->KeyMaterial + LEN_TKIP_EK,
- LEN_TKIP_TXMICK);
- NdisMoveMemory(pAd->SharedKey[BSS0][0].RxMic,
- pKey->KeyMaterial + LEN_TKIP_EK +
- LEN_TKIP_TXMICK,
- LEN_TKIP_RXMICK);
- }
-
- /* Decide its ChiperAlg */
- if (pAd->StaCfg.PairCipher ==
- Ndis802_11Encryption2Enabled)
- pAd->SharedKey[BSS0][0].CipherAlg = CIPHER_TKIP;
- else if (pAd->StaCfg.PairCipher ==
- Ndis802_11Encryption3Enabled)
- pAd->SharedKey[BSS0][0].CipherAlg = CIPHER_AES;
- else
- pAd->SharedKey[BSS0][0].CipherAlg = CIPHER_NONE;
-
- /* Update these related information to struct rt_mac_table_entry */
- pEntry = &pAd->MacTab.Content[BSSID_WCID];
- NdisMoveMemory(pEntry->PairwiseKey.Key,
- pAd->SharedKey[BSS0][0].Key,
- LEN_TKIP_EK);
- NdisMoveMemory(pEntry->PairwiseKey.RxMic,
- pAd->SharedKey[BSS0][0].RxMic,
- LEN_TKIP_RXMICK);
- NdisMoveMemory(pEntry->PairwiseKey.TxMic,
- pAd->SharedKey[BSS0][0].TxMic,
- LEN_TKIP_TXMICK);
- pEntry->PairwiseKey.CipherAlg =
- pAd->SharedKey[BSS0][0].CipherAlg;
-
- /* Update pairwise key information to ASIC Shared Key Table */
- AsicAddSharedKeyEntry(pAd,
- BSS0,
- 0,
- pAd->SharedKey[BSS0][0].CipherAlg,
- pAd->SharedKey[BSS0][0].Key,
- pAd->SharedKey[BSS0][0].TxMic,
- pAd->SharedKey[BSS0][0].RxMic);
-
- /* Update ASIC WCID attribute table and IVEIV table */
- RTMPAddWcidAttributeEntry(pAd,
- BSS0,
- 0,
- pAd->SharedKey[BSS0][0].
- CipherAlg, pEntry);
-
- if (pAd->StaCfg.AuthMode >= Ndis802_11AuthModeWPA2) {
- /* set 802.1x port control */
- /*pAd->StaCfg.PortSecured = WPA_802_1X_PORT_SECURED; */
- STA_PORT_SECURED(pAd);
-
- /* Indicate Connected for GUI */
- pAd->IndicateMediaState =
- NdisMediaStateConnected;
- }
- } else {
- /* Update GTK */
- pAd->StaCfg.DefaultKeyId = (pKey->KeyIndex & 0xFF);
- NdisZeroMemory(&pAd->
- SharedKey[BSS0][pAd->StaCfg.
- DefaultKeyId],
- sizeof(struct rt_cipher_key));
- pAd->SharedKey[BSS0][pAd->StaCfg.DefaultKeyId].KeyLen =
- LEN_TKIP_EK;
- NdisMoveMemory(pAd->
- SharedKey[BSS0][pAd->StaCfg.
- DefaultKeyId].Key,
- pKey->KeyMaterial, LEN_TKIP_EK);
-
- if (pAd->StaCfg.GroupCipher ==
- Ndis802_11Encryption2Enabled) {
- NdisMoveMemory(pAd->
- SharedKey[BSS0][pAd->StaCfg.
- DefaultKeyId].
- RxMic,
- pKey->KeyMaterial + LEN_TKIP_EK,
- LEN_TKIP_TXMICK);
- NdisMoveMemory(pAd->
- SharedKey[BSS0][pAd->StaCfg.
- DefaultKeyId].
- TxMic,
- pKey->KeyMaterial + LEN_TKIP_EK +
- LEN_TKIP_TXMICK,
- LEN_TKIP_RXMICK);
- } else {
- NdisMoveMemory(pAd->
- SharedKey[BSS0][pAd->StaCfg.
- DefaultKeyId].
- TxMic,
- pKey->KeyMaterial + LEN_TKIP_EK,
- LEN_TKIP_TXMICK);
- NdisMoveMemory(pAd->
- SharedKey[BSS0][pAd->StaCfg.
- DefaultKeyId].
- RxMic,
- pKey->KeyMaterial + LEN_TKIP_EK +
- LEN_TKIP_TXMICK,
- LEN_TKIP_RXMICK);
- }
-
- /* Update Shared Key CipherAlg */
- pAd->SharedKey[BSS0][pAd->StaCfg.DefaultKeyId].
- CipherAlg = CIPHER_NONE;
- if (pAd->StaCfg.GroupCipher ==
- Ndis802_11Encryption2Enabled)
- pAd->SharedKey[BSS0][pAd->StaCfg.DefaultKeyId].
- CipherAlg = CIPHER_TKIP;
- else if (pAd->StaCfg.GroupCipher ==
- Ndis802_11Encryption3Enabled)
- pAd->SharedKey[BSS0][pAd->StaCfg.DefaultKeyId].
- CipherAlg = CIPHER_AES;
-
- /* Update group key information to ASIC Shared Key Table */
- AsicAddSharedKeyEntry(pAd,
- BSS0,
- pAd->StaCfg.DefaultKeyId,
- pAd->SharedKey[BSS0][pAd->StaCfg.
- DefaultKeyId].
- CipherAlg,
- pAd->SharedKey[BSS0][pAd->StaCfg.
- DefaultKeyId].
- Key,
- pAd->SharedKey[BSS0][pAd->StaCfg.
- DefaultKeyId].
- TxMic,
- pAd->SharedKey[BSS0][pAd->StaCfg.
- DefaultKeyId].
- RxMic);
-
- /* Update ASIC WCID attribute table and IVEIV table */
- RTMPAddWcidAttributeEntry(pAd,
- BSS0,
- pAd->StaCfg.DefaultKeyId,
- pAd->SharedKey[BSS0][pAd->
- StaCfg.
- DefaultKeyId].
- CipherAlg, NULL);
-
- /* set 802.1x port control */
- /*pAd->StaCfg.PortSecured = WPA_802_1X_PORT_SECURED; */
- STA_PORT_SECURED(pAd);
-
- /* Indicate Connected for GUI */
- pAd->IndicateMediaState = NdisMediaStateConnected;
- }
- } else /* dynamic WEP from wpa_supplicant */
- {
- u8 CipherAlg;
- u8 *Key;
-
- if (pKey->KeyLength == 32)
- goto end;
-
- KeyIdx = pKey->KeyIndex & 0x0fffffff;
-
- if (KeyIdx < 4) {
- /* it is a default shared key, for Pairwise key setting */
- if (pKey->KeyIndex & 0x80000000) {
- pEntry = MacTableLookup(pAd, pKey->BSSID);
-
- if (pEntry) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("RTMPAddKey: Set Pair-wise Key\n"));
-
- /* set key material and key length */
- pEntry->PairwiseKey.KeyLen =
- (u8)pKey->KeyLength;
- NdisMoveMemory(pEntry->PairwiseKey.Key,
- &pKey->KeyMaterial,
- pKey->KeyLength);
-
- /* set Cipher type */
- if (pKey->KeyLength == 5)
- pEntry->PairwiseKey.CipherAlg =
- CIPHER_WEP64;
- else
- pEntry->PairwiseKey.CipherAlg =
- CIPHER_WEP128;
-
- /* Add Pair-wise key to Asic */
- AsicAddPairwiseKeyEntry(pAd,
- pEntry->Addr,
- (u8)pEntry->
- Aid,
- &pEntry->
- PairwiseKey);
-
- /* update WCID attribute table and IVEIV table for this entry */
- RTMPAddWcidAttributeEntry(pAd, BSS0, KeyIdx, /* The value may be not zero */
- pEntry->
- PairwiseKey.
- CipherAlg,
- pEntry);
-
- }
- } else {
- /* Default key for tx (shared key) */
- pAd->StaCfg.DefaultKeyId = (u8)KeyIdx;
-
- /* set key material and key length */
- pAd->SharedKey[BSS0][KeyIdx].KeyLen =
- (u8)pKey->KeyLength;
- NdisMoveMemory(pAd->SharedKey[BSS0][KeyIdx].Key,
- &pKey->KeyMaterial,
- pKey->KeyLength);
-
- /* Set Ciper type */
- if (pKey->KeyLength == 5)
- pAd->SharedKey[BSS0][KeyIdx].CipherAlg =
- CIPHER_WEP64;
- else
- pAd->SharedKey[BSS0][KeyIdx].CipherAlg =
- CIPHER_WEP128;
-
- CipherAlg =
- pAd->SharedKey[BSS0][KeyIdx].CipherAlg;
- Key = pAd->SharedKey[BSS0][KeyIdx].Key;
-
- /* Set Group key material to Asic */
- AsicAddSharedKeyEntry(pAd, BSS0, KeyIdx,
- CipherAlg, Key, NULL,
- NULL);
-
- /* Update WCID attribute table and IVEIV table for this group key table */
- RTMPAddWcidAttributeEntry(pAd, BSS0, KeyIdx,
- CipherAlg, NULL);
-
- }
- }
- }
-end:
- return;
-}
-
-char *rtstrchr(const char *s, int c)
-{
- for (; *s != (char)c; ++s)
- if (*s == '\0')
- return NULL;
- return (char *)s;
-}
-
-/*
-This is required for LinEX2004/kernel2.6.7 to provide iwlist scanning function
-*/
-
-int
-rt_ioctl_giwname(struct net_device *dev,
- struct iw_request_info *info, char *name, char *extra)
-{
- strncpy(name, "Ralink STA", IFNAMSIZ);
- /* RT2870 2.1.0.0 uses "RT2870 Wireless" */
- /* RT3090 2.1.0.0 uses "RT2860 Wireless" */
- return 0;
-}
-
-int rt_ioctl_siwfreq(struct net_device *dev,
- struct iw_request_info *info,
- struct iw_freq *freq, char *extra)
-{
- struct rt_rtmp_adapter *pAdapter = NULL;
- int chan = -1;
-
- GET_PAD_FROM_NET_DEV(pAdapter, dev);
-
- /*check if the interface is down */
- if (!RTMP_TEST_FLAG(pAdapter, fRTMP_ADAPTER_INTERRUPT_IN_USE)) {
- DBGPRINT(RT_DEBUG_TRACE, ("INFO::Network is down!\n"));
- return -ENETDOWN;
- }
-
- if (freq->e > 1)
- return -EINVAL;
-
- if ((freq->e == 0) && (freq->m <= 1000))
- chan = freq->m; /* Setting by channel number */
- else
- MAP_KHZ_TO_CHANNEL_ID((freq->m / 100), chan); /* Setting by frequency - search the table , like 2.412G, 2.422G, */
-
- if (ChannelSanity(pAdapter, chan) == TRUE) {
- pAdapter->CommonCfg.Channel = chan;
- DBGPRINT(RT_DEBUG_ERROR,
- ("==>rt_ioctl_siwfreq::SIOCSIWFREQ[cmd=0x%x] (Channel=%d)\n",
- SIOCSIWFREQ, pAdapter->CommonCfg.Channel));
- } else
- return -EINVAL;
-
- return 0;
-}
-
-int rt_ioctl_giwfreq(struct net_device *dev,
- struct iw_request_info *info,
- struct iw_freq *freq, char *extra)
-{
- struct rt_rtmp_adapter *pAdapter = NULL;
- u8 ch;
- unsigned long m = 2412000;
-
- GET_PAD_FROM_NET_DEV(pAdapter, dev);
-
- ch = pAdapter->CommonCfg.Channel;
-
- DBGPRINT(RT_DEBUG_TRACE, ("==>rt_ioctl_giwfreq %d\n", ch));
-
- MAP_CHANNEL_ID_TO_KHZ(ch, m);
- freq->m = m * 100;
- freq->e = 1;
- return 0;
-}
-
-int rt_ioctl_siwmode(struct net_device *dev,
- struct iw_request_info *info, __u32 * mode, char *extra)
-{
- struct rt_rtmp_adapter *pAdapter = NULL;
-
- GET_PAD_FROM_NET_DEV(pAdapter, dev);
-
- /*check if the interface is down */
- if (!RTMP_TEST_FLAG(pAdapter, fRTMP_ADAPTER_INTERRUPT_IN_USE)) {
- DBGPRINT(RT_DEBUG_TRACE, ("INFO::Network is down!\n"));
- return -ENETDOWN;
- }
-
- switch (*mode) {
- case IW_MODE_ADHOC:
- Set_NetworkType_Proc(pAdapter, "Adhoc");
- break;
- case IW_MODE_INFRA:
- Set_NetworkType_Proc(pAdapter, "Infra");
- break;
- case IW_MODE_MONITOR:
- Set_NetworkType_Proc(pAdapter, "Monitor");
- break;
- default:
- DBGPRINT(RT_DEBUG_TRACE,
- ("===>rt_ioctl_siwmode::SIOCSIWMODE (unknown %d)\n",
- *mode));
- return -EINVAL;
- }
-
- /* Reset Ralink supplicant to not use, it will be set to start when UI set PMK key */
- pAdapter->StaCfg.WpaState = SS_NOTUSE;
-
- return 0;
-}
-
-int rt_ioctl_giwmode(struct net_device *dev,
- struct iw_request_info *info, __u32 * mode, char *extra)
-{
- struct rt_rtmp_adapter *pAdapter = NULL;
-
- GET_PAD_FROM_NET_DEV(pAdapter, dev);
-
- if (ADHOC_ON(pAdapter))
- *mode = IW_MODE_ADHOC;
- else if (INFRA_ON(pAdapter))
- *mode = IW_MODE_INFRA;
- else if (MONITOR_ON(pAdapter)) {
- *mode = IW_MODE_MONITOR;
- } else
- *mode = IW_MODE_AUTO;
-
- DBGPRINT(RT_DEBUG_TRACE, ("==>rt_ioctl_giwmode(mode=%d)\n", *mode));
- return 0;
-}
-
-int rt_ioctl_siwsens(struct net_device *dev,
- struct iw_request_info *info, char *name, char *extra)
-{
- struct rt_rtmp_adapter *pAdapter = NULL;
-
- GET_PAD_FROM_NET_DEV(pAdapter, dev);
-
- /*check if the interface is down */
- if (!RTMP_TEST_FLAG(pAdapter, fRTMP_ADAPTER_INTERRUPT_IN_USE)) {
- DBGPRINT(RT_DEBUG_TRACE, ("INFO::Network is down!\n"));
- return -ENETDOWN;
- }
-
- return 0;
-}
-
-int rt_ioctl_giwsens(struct net_device *dev,
- struct iw_request_info *info, char *name, char *extra)
-{
- return 0;
-}
-
-int rt_ioctl_giwrange(struct net_device *dev,
- struct iw_request_info *info,
- struct iw_point *data, char *extra)
-{
- struct rt_rtmp_adapter *pAdapter = NULL;
- struct iw_range *range = (struct iw_range *)extra;
- u16 val;
- int i;
-
- GET_PAD_FROM_NET_DEV(pAdapter, dev);
-
- DBGPRINT(RT_DEBUG_TRACE, ("===>rt_ioctl_giwrange\n"));
- data->length = sizeof(struct iw_range);
- memset(range, 0, sizeof(struct iw_range));
-
- range->txpower_capa = IW_TXPOW_DBM;
-
- if (INFRA_ON(pAdapter) || ADHOC_ON(pAdapter)) {
- range->min_pmp = 1 * 1024;
- range->max_pmp = 65535 * 1024;
- range->min_pmt = 1 * 1024;
- range->max_pmt = 1000 * 1024;
- range->pmp_flags = IW_POWER_PERIOD;
- range->pmt_flags = IW_POWER_TIMEOUT;
- range->pm_capa = IW_POWER_PERIOD | IW_POWER_TIMEOUT |
- IW_POWER_UNICAST_R | IW_POWER_ALL_R;
- }
-
- range->we_version_compiled = WIRELESS_EXT;
- range->we_version_source = 14;
-
- range->retry_capa = IW_RETRY_LIMIT;
- range->retry_flags = IW_RETRY_LIMIT;
- range->min_retry = 0;
- range->max_retry = 255;
-
- range->num_channels = pAdapter->ChannelListNum;
-
- val = 0;
- for (i = 1; i <= range->num_channels; i++) {
- u32 m = 2412000;
- range->freq[val].i = pAdapter->ChannelList[i - 1].Channel;
- MAP_CHANNEL_ID_TO_KHZ(pAdapter->ChannelList[i - 1].Channel, m);
- range->freq[val].m = m * 100; /* OS_HZ */
-
- range->freq[val].e = 1;
- val++;
- if (val == IW_MAX_FREQUENCIES)
- break;
- }
- range->num_frequency = val;
-
- range->max_qual.qual = 100; /* what is correct max? This was not
- * documented exactly. At least
- * 69 has been observed. */
- range->max_qual.level = 0; /* dB */
- range->max_qual.noise = 0; /* dB */
-
- /* What would be suitable values for "average/typical" qual? */
- range->avg_qual.qual = 20;
- range->avg_qual.level = -60;
- range->avg_qual.noise = -95;
- range->sensitivity = 3;
-
- range->max_encoding_tokens = NR_WEP_KEYS;
- range->num_encoding_sizes = 2;
- range->encoding_size[0] = 5;
- range->encoding_size[1] = 13;
-
- range->min_rts = 0;
- range->max_rts = 2347;
- range->min_frag = 256;
- range->max_frag = 2346;
-
- /* IW_ENC_CAPA_* bit field */
- range->enc_capa = IW_ENC_CAPA_WPA | IW_ENC_CAPA_WPA2 |
- IW_ENC_CAPA_CIPHER_TKIP | IW_ENC_CAPA_CIPHER_CCMP;
-
- return 0;
-}
-
-int rt_ioctl_siwap(struct net_device *dev,
- struct iw_request_info *info,
- struct sockaddr *ap_addr, char *extra)
-{
- struct rt_rtmp_adapter *pAdapter = NULL;
- NDIS_802_11_MAC_ADDRESS Bssid;
-
- GET_PAD_FROM_NET_DEV(pAdapter, dev);
-
- /*check if the interface is down */
- if (!RTMP_TEST_FLAG(pAdapter, fRTMP_ADAPTER_INTERRUPT_IN_USE)) {
- DBGPRINT(RT_DEBUG_TRACE, ("INFO::Network is down!\n"));
- return -ENETDOWN;
- }
-
- if (pAdapter->Mlme.CntlMachine.CurrState != CNTL_IDLE) {
- RTMP_MLME_RESET_STATE_MACHINE(pAdapter);
- DBGPRINT(RT_DEBUG_TRACE,
- ("MLME busy, reset MLME state machine!\n"));
- }
- /* tell CNTL state machine to call NdisMSetInformationComplete() after completing */
- /* this request, because this request is initiated by NDIS. */
- pAdapter->MlmeAux.CurrReqIsFromNdis = FALSE;
- /* Prevent to connect AP again in STAMlmePeriodicExec */
- pAdapter->MlmeAux.AutoReconnectSsidLen = 32;
-
- memcpy(Bssid, ap_addr->sa_data, MAC_ADDR_LEN);
- MlmeEnqueue(pAdapter,
- MLME_CNTL_STATE_MACHINE,
- OID_802_11_BSSID,
- sizeof(NDIS_802_11_MAC_ADDRESS), (void *) & Bssid);
-
- DBGPRINT(RT_DEBUG_TRACE, ("IOCTL::SIOCSIWAP %pM\n", Bssid));
-
- return 0;
-}
-
-int rt_ioctl_giwap(struct net_device *dev,
- struct iw_request_info *info,
- struct sockaddr *ap_addr, char *extra)
-{
- struct rt_rtmp_adapter *pAdapter = NULL;
-
- GET_PAD_FROM_NET_DEV(pAdapter, dev);
-
- if (INFRA_ON(pAdapter) || ADHOC_ON(pAdapter)) {
- ap_addr->sa_family = ARPHRD_ETHER;
- memcpy(ap_addr->sa_data, &pAdapter->CommonCfg.Bssid, ETH_ALEN);
- }
- /* Add for RT2870 */
- else if (pAdapter->StaCfg.WpaSupplicantUP != WPA_SUPPLICANT_DISABLE) {
- ap_addr->sa_family = ARPHRD_ETHER;
- memcpy(ap_addr->sa_data, &pAdapter->MlmeAux.Bssid, ETH_ALEN);
- } else {
- DBGPRINT(RT_DEBUG_TRACE, ("IOCTL::SIOCGIWAP(=EMPTY)\n"));
- return -ENOTCONN;
- }
-
- return 0;
-}
-
-/*
- * Units are in db above the noise floor. That means the
- * rssi values reported in the tx/rx descriptors in the
- * driver are the SNR expressed in db.
- *
- * If you assume that the noise floor is -95, which is an
- * excellent assumption 99.5 % of the time, then you can
- * derive the absolute signal level (i.e. -95 + rssi).
- * There are some other slight factors to take into account
- * depending on whether the rssi measurement is from 11b,
- * 11g, or 11a. These differences are at most 2db and
- * can be documented.
- *
- * NB: various calculations are based on the orinoco/wavelan
- * drivers for compatibility
- */
-static void set_quality(struct rt_rtmp_adapter *pAdapter,
- struct iw_quality *iq, signed char rssi)
-{
- __u8 ChannelQuality;
-
- /* Normalize Rssi */
- if (rssi >= -50)
- ChannelQuality = 100;
- else if (rssi >= -80) /* between -50 ~ -80dbm */
- ChannelQuality = (__u8) (24 + ((rssi + 80) * 26) / 10);
- else if (rssi >= -90) /* between -80 ~ -90dbm */
- ChannelQuality = (__u8) ((rssi + 90) * 26) / 10;
- else
- ChannelQuality = 0;
-
- iq->qual = (__u8) ChannelQuality;
-
- iq->level = (__u8) (rssi);
- iq->noise = (pAdapter->BbpWriteLatch[66] > pAdapter->BbpTuning.FalseCcaUpperThreshold) ? ((__u8) pAdapter->BbpTuning.FalseCcaUpperThreshold) : ((__u8) pAdapter->BbpWriteLatch[66]); /* noise level (dBm) */
- iq->noise += 256 - 143;
- iq->updated = pAdapter->iw_stats.qual.updated;
-}
-
-int rt_ioctl_iwaplist(struct net_device *dev,
- struct iw_request_info *info,
- struct iw_point *data, char *extra)
-{
- struct rt_rtmp_adapter *pAdapter = NULL;
-
- struct sockaddr addr[IW_MAX_AP];
- struct iw_quality qual[IW_MAX_AP];
- int i;
-
- GET_PAD_FROM_NET_DEV(pAdapter, dev);
-
- /*check if the interface is down */
- if (!RTMP_TEST_FLAG(pAdapter, fRTMP_ADAPTER_INTERRUPT_IN_USE)) {
- DBGPRINT(RT_DEBUG_TRACE, ("INFO::Network is down!\n"));
- data->length = 0;
- return 0;
- /*return -ENETDOWN; */
- }
-
- for (i = 0; i < IW_MAX_AP; i++) {
- if (i >= pAdapter->ScanTab.BssNr)
- break;
- addr[i].sa_family = ARPHRD_ETHER;
- memcpy(addr[i].sa_data, &pAdapter->ScanTab.BssEntry[i].Bssid,
- MAC_ADDR_LEN);
- set_quality(pAdapter, &qual[i],
- pAdapter->ScanTab.BssEntry[i].Rssi);
- }
- data->length = i;
- memcpy(extra, &addr, i * sizeof(addr[0]));
- data->flags = 1; /* signal quality present (sort of) */
- memcpy(extra + i * sizeof(addr[0]), &qual, i * sizeof(qual[i]));
-
- return 0;
-}
-
-int rt_ioctl_siwscan(struct net_device *dev,
- struct iw_request_info *info,
- struct iw_point *data, char *extra)
-{
- struct rt_rtmp_adapter *pAdapter = NULL;
-
- unsigned long Now;
- int Status = NDIS_STATUS_SUCCESS;
-
- GET_PAD_FROM_NET_DEV(pAdapter, dev);
-
- /*check if the interface is down */
- if (!RTMP_TEST_FLAG(pAdapter, fRTMP_ADAPTER_INTERRUPT_IN_USE)) {
- DBGPRINT(RT_DEBUG_TRACE, ("INFO::Network is down!\n"));
- return -ENETDOWN;
- }
-
- if (MONITOR_ON(pAdapter)) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("Driver is in Monitor Mode now!\n"));
- return -EINVAL;
- }
-
- if (pAdapter->StaCfg.WpaSupplicantUP == WPA_SUPPLICANT_ENABLE) {
- pAdapter->StaCfg.WpaSupplicantScanCount++;
- }
-
- pAdapter->StaCfg.bScanReqIsFromWebUI = TRUE;
- if (RTMP_TEST_FLAG(pAdapter, fRTMP_ADAPTER_BSS_SCAN_IN_PROGRESS))
- return NDIS_STATUS_SUCCESS;
- do {
- Now = jiffies;
-
- if ((pAdapter->StaCfg.WpaSupplicantUP == WPA_SUPPLICANT_ENABLE)
- && (pAdapter->StaCfg.WpaSupplicantScanCount > 3)) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("WpaSupplicantScanCount > 3\n"));
- Status = NDIS_STATUS_SUCCESS;
- break;
- }
-
- if ((OPSTATUS_TEST_FLAG
- (pAdapter, fOP_STATUS_MEDIA_STATE_CONNECTED))
- && ((pAdapter->StaCfg.AuthMode == Ndis802_11AuthModeWPA)
- || (pAdapter->StaCfg.AuthMode ==
- Ndis802_11AuthModeWPAPSK))
- && (pAdapter->StaCfg.PortSecured ==
- WPA_802_1X_PORT_NOT_SECURED)) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("Link UP, Port Not Secured! ignore this set::OID_802_11_BSSID_LIST_SCAN\n"));
- Status = NDIS_STATUS_SUCCESS;
- break;
- }
-
- if (pAdapter->Mlme.CntlMachine.CurrState != CNTL_IDLE) {
- RTMP_MLME_RESET_STATE_MACHINE(pAdapter);
- DBGPRINT(RT_DEBUG_TRACE,
- ("MLME busy, reset MLME state machine!\n"));
- }
- /* tell CNTL state machine to call NdisMSetInformationComplete() after completing */
- /* this request, because this request is initiated by NDIS. */
- pAdapter->MlmeAux.CurrReqIsFromNdis = FALSE;
- /* Reset allowed scan retries */
- pAdapter->StaCfg.ScanCnt = 0;
- pAdapter->StaCfg.LastScanTime = Now;
-
- MlmeEnqueue(pAdapter,
- MLME_CNTL_STATE_MACHINE,
- OID_802_11_BSSID_LIST_SCAN, 0, NULL);
-
- Status = NDIS_STATUS_SUCCESS;
- RTMP_MLME_HANDLER(pAdapter);
- } while (0);
- return NDIS_STATUS_SUCCESS;
-}
-
-int rt_ioctl_giwscan(struct net_device *dev,
- struct iw_request_info *info,
- struct iw_point *data, char *extra)
-{
- struct rt_rtmp_adapter *pAdapter = NULL;
- int i = 0;
- char *current_ev = extra, *previous_ev = extra;
- char *end_buf;
- char *current_val;
- char custom[MAX_CUSTOM_LEN] = { 0 };
- struct iw_event iwe;
-
- GET_PAD_FROM_NET_DEV(pAdapter, dev);
-
- if (RTMP_TEST_FLAG(pAdapter, fRTMP_ADAPTER_BSS_SCAN_IN_PROGRESS)) {
- /*
- * Still scanning, indicate the caller should try again.
- */
- return -EAGAIN;
- }
-
- if (pAdapter->StaCfg.WpaSupplicantUP == WPA_SUPPLICANT_ENABLE) {
- pAdapter->StaCfg.WpaSupplicantScanCount = 0;
- }
-
- if (pAdapter->ScanTab.BssNr == 0) {
- data->length = 0;
- return 0;
- }
-
- if (data->length > 0)
- end_buf = extra + data->length;
- else
- end_buf = extra + IW_SCAN_MAX_DATA;
-
- for (i = 0; i < pAdapter->ScanTab.BssNr; i++) {
- if (current_ev >= end_buf) {
- return -E2BIG;
- }
- /*MAC address */
- /*================================ */
- memset(&iwe, 0, sizeof(iwe));
- iwe.cmd = SIOCGIWAP;
- iwe.u.ap_addr.sa_family = ARPHRD_ETHER;
- memcpy(iwe.u.ap_addr.sa_data,
- &pAdapter->ScanTab.BssEntry[i].Bssid, ETH_ALEN);
-
- previous_ev = current_ev;
- current_ev =
- iwe_stream_add_event(info, current_ev, end_buf, &iwe,
- IW_EV_ADDR_LEN);
- if (current_ev == previous_ev)
- return -E2BIG;
-
- /*
- Protocol:
- it will show scanned AP's WirelessMode.
- it might be
- 802.11a
- 802.11a/n
- 802.11g/n
- 802.11b/g/n
- 802.11g
- 802.11b/g
- */
- memset(&iwe, 0, sizeof(iwe));
- iwe.cmd = SIOCGIWNAME;
-
- {
- struct rt_bss_entry *pBssEntry = &pAdapter->ScanTab.BssEntry[i];
- BOOLEAN isGonly = FALSE;
- int rateCnt = 0;
-
- if (pBssEntry->Channel > 14) {
- if (pBssEntry->HtCapabilityLen != 0)
- strcpy(iwe.u.name, "802.11a/n");
- else
- strcpy(iwe.u.name, "802.11a");
- } else {
- /*
- if one of non B mode rate is set supported rate, it means G only.
- */
- for (rateCnt = 0;
- rateCnt < pBssEntry->SupRateLen;
- rateCnt++) {
- /*
- 6Mbps(140) 9Mbps(146) and >=12Mbps(152) are supported rate, it means G only.
- */
- if (pBssEntry->SupRate[rateCnt] == 140
- || pBssEntry->SupRate[rateCnt] ==
- 146
- || pBssEntry->SupRate[rateCnt] >=
- 152)
- isGonly = TRUE;
- }
-
- for (rateCnt = 0;
- rateCnt < pBssEntry->ExtRateLen;
- rateCnt++) {
- if (pBssEntry->ExtRate[rateCnt] == 140
- || pBssEntry->ExtRate[rateCnt] ==
- 146
- || pBssEntry->ExtRate[rateCnt] >=
- 152)
- isGonly = TRUE;
- }
-
- if (pBssEntry->HtCapabilityLen != 0) {
- if (isGonly == TRUE)
- strcpy(iwe.u.name, "802.11g/n");
- else
- strcpy(iwe.u.name,
- "802.11b/g/n");
- } else {
- if (isGonly == TRUE)
- strcpy(iwe.u.name, "802.11g");
- else {
- if (pBssEntry->SupRateLen == 4
- && pBssEntry->ExtRateLen ==
- 0)
- strcpy(iwe.u.name,
- "802.11b");
- else
- strcpy(iwe.u.name,
- "802.11b/g");
- }
- }
- }
- }
-
- previous_ev = current_ev;
- current_ev =
- iwe_stream_add_event(info, current_ev, end_buf, &iwe,
- IW_EV_ADDR_LEN);
- if (current_ev == previous_ev)
- return -E2BIG;
-
- /*ESSID */
- /*================================ */
- memset(&iwe, 0, sizeof(iwe));
- iwe.cmd = SIOCGIWESSID;
- iwe.u.data.length = pAdapter->ScanTab.BssEntry[i].SsidLen;
- iwe.u.data.flags = 1;
-
- previous_ev = current_ev;
- current_ev =
- iwe_stream_add_point(info, current_ev, end_buf, &iwe,
- (char *)pAdapter->ScanTab.
- BssEntry[i].Ssid);
- if (current_ev == previous_ev)
- return -E2BIG;
-
- /*Network Type */
- /*================================ */
- memset(&iwe, 0, sizeof(iwe));
- iwe.cmd = SIOCGIWMODE;
- if (pAdapter->ScanTab.BssEntry[i].BssType == Ndis802_11IBSS) {
- iwe.u.mode = IW_MODE_ADHOC;
- } else if (pAdapter->ScanTab.BssEntry[i].BssType ==
- Ndis802_11Infrastructure) {
- iwe.u.mode = IW_MODE_INFRA;
- } else {
- iwe.u.mode = IW_MODE_AUTO;
- }
- iwe.len = IW_EV_UINT_LEN;
-
- previous_ev = current_ev;
- current_ev =
- iwe_stream_add_event(info, current_ev, end_buf, &iwe,
- IW_EV_UINT_LEN);
- if (current_ev == previous_ev)
- return -E2BIG;
-
- /*Channel and Frequency */
- /*================================ */
- memset(&iwe, 0, sizeof(iwe));
- iwe.cmd = SIOCGIWFREQ;
- iwe.u.freq.m = pAdapter->ScanTab.BssEntry[i].Channel;
- iwe.u.freq.e = 0;
- iwe.u.freq.i = 0;
-
- previous_ev = current_ev;
- current_ev =
- iwe_stream_add_event(info, current_ev, end_buf, &iwe,
- IW_EV_FREQ_LEN);
- if (current_ev == previous_ev)
- return -E2BIG;
-
- /*Add quality statistics */
- /*================================ */
- memset(&iwe, 0, sizeof(iwe));
- iwe.cmd = IWEVQUAL;
- iwe.u.qual.level = 0;
- iwe.u.qual.noise = 0;
- set_quality(pAdapter, &iwe.u.qual,
- pAdapter->ScanTab.BssEntry[i].Rssi);
- current_ev =
- iwe_stream_add_event(info, current_ev, end_buf, &iwe,
- IW_EV_QUAL_LEN);
- if (current_ev == previous_ev)
- return -E2BIG;
-
- /*Encyption key */
- /*================================ */
- memset(&iwe, 0, sizeof(iwe));
- iwe.cmd = SIOCGIWENCODE;
- if (CAP_IS_PRIVACY_ON
- (pAdapter->ScanTab.BssEntry[i].CapabilityInfo))
- iwe.u.data.flags = IW_ENCODE_ENABLED | IW_ENCODE_NOKEY;
- else
- iwe.u.data.flags = IW_ENCODE_DISABLED;
-
- previous_ev = current_ev;
- current_ev =
- iwe_stream_add_point(info, current_ev, end_buf, &iwe,
- (char *)pAdapter->
- SharedKey[BSS0][(iwe.u.data.
- flags &
- IW_ENCODE_INDEX) -
- 1].Key);
- if (current_ev == previous_ev)
- return -E2BIG;
-
- /*Bit Rate */
- /*================================ */
- if (pAdapter->ScanTab.BssEntry[i].SupRateLen) {
- u8 tmpRate =
- pAdapter->ScanTab.BssEntry[i].SupRate[pAdapter->
- ScanTab.
- BssEntry[i].
- SupRateLen -
- 1];
- memset(&iwe, 0, sizeof(iwe));
- iwe.cmd = SIOCGIWRATE;
- current_val = current_ev + IW_EV_LCP_LEN;
- if (tmpRate == 0x82)
- iwe.u.bitrate.value = 1 * 1000000;
- else if (tmpRate == 0x84)
- iwe.u.bitrate.value = 2 * 1000000;
- else if (tmpRate == 0x8B)
- iwe.u.bitrate.value = 5.5 * 1000000;
- else if (tmpRate == 0x96)
- iwe.u.bitrate.value = 11 * 1000000;
- else
- iwe.u.bitrate.value = (tmpRate / 2) * 1000000;
-
- if (tmpRate == 0x6c
- && pAdapter->ScanTab.BssEntry[i].HtCapabilityLen >
- 0) {
- int rate_count = ARRAY_SIZE(ralinkrate);
- struct rt_ht_cap_info capInfo =
- pAdapter->ScanTab.BssEntry[i].HtCapability.
- HtCapInfo;
- int shortGI =
- capInfo.ChannelWidth ? capInfo.
- ShortGIfor40 : capInfo.ShortGIfor20;
- int maxMCS =
- pAdapter->ScanTab.BssEntry[i].HtCapability.
- MCSSet[1] ? 15 : 7;
- int rate_index =
- 12 + ((u8)capInfo.ChannelWidth * 24) +
- ((u8)shortGI * 48) + ((u8)maxMCS);
-
- if (rate_index < 0)
- rate_index = 0;
- if (rate_index >= rate_count)
- rate_index = rate_count - 1;
- iwe.u.bitrate.value =
- ralinkrate[rate_index] * 500000;
- }
-
- iwe.u.bitrate.disabled = 0;
- current_val = iwe_stream_add_value(info, current_ev,
- current_val, end_buf,
- &iwe,
- IW_EV_PARAM_LEN);
-
- if ((current_val - current_ev) > IW_EV_LCP_LEN)
- current_ev = current_val;
- else
- return -E2BIG;
- }
- /*WPA IE */
- if (pAdapter->ScanTab.BssEntry[i].WpaIE.IELen > 0) {
- memset(&iwe, 0, sizeof(iwe));
- memset(&custom[0], 0, MAX_CUSTOM_LEN);
- memcpy(custom,
- &(pAdapter->ScanTab.BssEntry[i].WpaIE.IE[0]),
- pAdapter->ScanTab.BssEntry[i].WpaIE.IELen);
- iwe.cmd = IWEVGENIE;
- iwe.u.data.length =
- pAdapter->ScanTab.BssEntry[i].WpaIE.IELen;
- current_ev =
- iwe_stream_add_point(info, current_ev, end_buf,
- &iwe, custom);
- if (current_ev == previous_ev)
- return -E2BIG;
- }
- /*WPA2 IE */
- if (pAdapter->ScanTab.BssEntry[i].RsnIE.IELen > 0) {
- memset(&iwe, 0, sizeof(iwe));
- memset(&custom[0], 0, MAX_CUSTOM_LEN);
- memcpy(custom,
- &(pAdapter->ScanTab.BssEntry[i].RsnIE.IE[0]),
- pAdapter->ScanTab.BssEntry[i].RsnIE.IELen);
- iwe.cmd = IWEVGENIE;
- iwe.u.data.length =
- pAdapter->ScanTab.BssEntry[i].RsnIE.IELen;
- current_ev =
- iwe_stream_add_point(info, current_ev, end_buf,
- &iwe, custom);
- if (current_ev == previous_ev)
- return -E2BIG;
- }
- }
-
- data->length = current_ev - extra;
- pAdapter->StaCfg.bScanReqIsFromWebUI = FALSE;
- DBGPRINT(RT_DEBUG_ERROR,
- ("===>rt_ioctl_giwscan. %d(%d) BSS returned, data->length = %d\n",
- i, pAdapter->ScanTab.BssNr, data->length));
- return 0;
-}
-
-int rt_ioctl_siwessid(struct net_device *dev,
- struct iw_request_info *info,
- struct iw_point *data, char *essid)
-{
- struct rt_rtmp_adapter *pAdapter = NULL;
-
- GET_PAD_FROM_NET_DEV(pAdapter, dev);
-
- /*check if the interface is down */
- if (!RTMP_TEST_FLAG(pAdapter, fRTMP_ADAPTER_INTERRUPT_IN_USE)) {
- DBGPRINT(RT_DEBUG_TRACE, ("INFO::Network is down!\n"));
- return -ENETDOWN;
- }
-
- if (data->flags) {
- char *pSsidString = NULL;
-
- /* Includes null character. */
- if (data->length > (IW_ESSID_MAX_SIZE + 1))
- return -E2BIG;
-
- pSsidString = kmalloc(MAX_LEN_OF_SSID + 1, MEM_ALLOC_FLAG);
- if (pSsidString) {
- NdisZeroMemory(pSsidString, MAX_LEN_OF_SSID + 1);
- NdisMoveMemory(pSsidString, essid, data->length);
- if (Set_SSID_Proc(pAdapter, pSsidString) == FALSE)
- return -EINVAL;
- } else
- return -ENOMEM;
- } else {
- /* ANY ssid */
- if (Set_SSID_Proc(pAdapter, "") == FALSE)
- return -EINVAL;
- }
- return 0;
-}
-
-int rt_ioctl_giwessid(struct net_device *dev,
- struct iw_request_info *info,
- struct iw_point *data, char *essid)
-{
- struct rt_rtmp_adapter *pAdapter = NULL;
-
- GET_PAD_FROM_NET_DEV(pAdapter, dev);
-
- data->flags = 1;
- if (MONITOR_ON(pAdapter)) {
- data->length = 0;
- return 0;
- }
-
- if (OPSTATUS_TEST_FLAG(pAdapter, fOP_STATUS_MEDIA_STATE_CONNECTED)) {
- DBGPRINT(RT_DEBUG_TRACE, ("MediaState is connected\n"));
- data->length = pAdapter->CommonCfg.SsidLen;
- memcpy(essid, pAdapter->CommonCfg.Ssid,
- pAdapter->CommonCfg.SsidLen);
- }
-#ifdef RTMP_MAC_USB
- /* Add for RT2870 */
- else if (pAdapter->StaCfg.WpaSupplicantUP != WPA_SUPPLICANT_DISABLE) {
- data->length = pAdapter->CommonCfg.SsidLen;
- memcpy(essid, pAdapter->CommonCfg.Ssid,
- pAdapter->CommonCfg.SsidLen);
- }
-#endif /* RTMP_MAC_USB // */
- else { /*the ANY ssid was specified */
- data->length = 0;
- DBGPRINT(RT_DEBUG_TRACE,
- ("MediaState is not connected, ess\n"));
- }
-
- return 0;
-
-}
-
-int rt_ioctl_siwnickn(struct net_device *dev,
- struct iw_request_info *info,
- struct iw_point *data, char *nickname)
-{
- struct rt_rtmp_adapter *pAdapter = NULL;
-
- GET_PAD_FROM_NET_DEV(pAdapter, dev);
-
- /*check if the interface is down */
- if (!RTMP_TEST_FLAG(pAdapter, fRTMP_ADAPTER_INTERRUPT_IN_USE)) {
- DBGPRINT(RT_DEBUG_TRACE, ("INFO::Network is down!\n"));
- return -ENETDOWN;
- }
-
- if (data->length > IW_ESSID_MAX_SIZE)
- return -EINVAL;
-
- memset(pAdapter->nickname, 0, IW_ESSID_MAX_SIZE + 1);
- memcpy(pAdapter->nickname, nickname, data->length);
-
- return 0;
-}
-
-int rt_ioctl_giwnickn(struct net_device *dev,
- struct iw_request_info *info,
- struct iw_point *data, char *nickname)
-{
- struct rt_rtmp_adapter *pAdapter = NULL;
-
- GET_PAD_FROM_NET_DEV(pAdapter, dev);
-
- if (data->length > strlen((char *)pAdapter->nickname) + 1)
- data->length = strlen((char *)pAdapter->nickname) + 1;
- if (data->length > 0) {
- memcpy(nickname, pAdapter->nickname, data->length - 1);
- nickname[data->length - 1] = '\0';
- }
- return 0;
-}
-
-int rt_ioctl_siwrts(struct net_device *dev,
- struct iw_request_info *info,
- struct iw_param *rts, char *extra)
-{
- struct rt_rtmp_adapter *pAdapter = NULL;
- u16 val;
-
- GET_PAD_FROM_NET_DEV(pAdapter, dev);
-
- /*check if the interface is down */
- if (!RTMP_TEST_FLAG(pAdapter, fRTMP_ADAPTER_INTERRUPT_IN_USE)) {
- DBGPRINT(RT_DEBUG_TRACE, ("INFO::Network is down!\n"));
- return -ENETDOWN;
- }
-
- if (rts->disabled)
- val = MAX_RTS_THRESHOLD;
- else if (rts->value < 0 || rts->value > MAX_RTS_THRESHOLD)
- return -EINVAL;
- else if (rts->value == 0)
- val = MAX_RTS_THRESHOLD;
- else
- val = rts->value;
-
- if (val != pAdapter->CommonCfg.RtsThreshold)
- pAdapter->CommonCfg.RtsThreshold = val;
-
- return 0;
-}
-
-int rt_ioctl_giwrts(struct net_device *dev,
- struct iw_request_info *info,
- struct iw_param *rts, char *extra)
-{
- struct rt_rtmp_adapter *pAdapter = NULL;
-
- GET_PAD_FROM_NET_DEV(pAdapter, dev);
-
- /*check if the interface is down */
- if (!RTMP_TEST_FLAG(pAdapter, fRTMP_ADAPTER_INTERRUPT_IN_USE)) {
- DBGPRINT(RT_DEBUG_TRACE, ("INFO::Network is down!\n"));
- return -ENETDOWN;
- }
-
- rts->value = pAdapter->CommonCfg.RtsThreshold;
- rts->disabled = (rts->value == MAX_RTS_THRESHOLD);
- rts->fixed = 1;
-
- return 0;
-}
-
-int rt_ioctl_siwfrag(struct net_device *dev,
- struct iw_request_info *info,
- struct iw_param *frag, char *extra)
-{
- struct rt_rtmp_adapter *pAdapter = NULL;
- u16 val;
-
- GET_PAD_FROM_NET_DEV(pAdapter, dev);
-
- /*check if the interface is down */
- if (!RTMP_TEST_FLAG(pAdapter, fRTMP_ADAPTER_INTERRUPT_IN_USE)) {
- DBGPRINT(RT_DEBUG_TRACE, ("INFO::Network is down!\n"));
- return -ENETDOWN;
- }
-
- if (frag->disabled)
- val = MAX_FRAG_THRESHOLD;
- else if (frag->value >= MIN_FRAG_THRESHOLD
- && frag->value <= MAX_FRAG_THRESHOLD)
- val = __cpu_to_le16(frag->value & ~0x1); /* even numbers only */
- else if (frag->value == 0)
- val = MAX_FRAG_THRESHOLD;
- else
- return -EINVAL;
-
- pAdapter->CommonCfg.FragmentThreshold = val;
- return 0;
-}
-
-int rt_ioctl_giwfrag(struct net_device *dev,
- struct iw_request_info *info,
- struct iw_param *frag, char *extra)
-{
- struct rt_rtmp_adapter *pAdapter = NULL;
-
- GET_PAD_FROM_NET_DEV(pAdapter, dev);
-
- /*check if the interface is down */
- if (!RTMP_TEST_FLAG(pAdapter, fRTMP_ADAPTER_INTERRUPT_IN_USE)) {
- DBGPRINT(RT_DEBUG_TRACE, ("INFO::Network is down!\n"));
- return -ENETDOWN;
- }
-
- frag->value = pAdapter->CommonCfg.FragmentThreshold;
- frag->disabled = (frag->value == MAX_FRAG_THRESHOLD);
- frag->fixed = 1;
-
- return 0;
-}
-
-#define MAX_WEP_KEY_SIZE 13
-#define MIN_WEP_KEY_SIZE 5
-int rt_ioctl_siwencode(struct net_device *dev,
- struct iw_request_info *info,
- struct iw_point *erq, char *extra)
-{
- struct rt_rtmp_adapter *pAdapter = NULL;
-
- GET_PAD_FROM_NET_DEV(pAdapter, dev);
-
- /*check if the interface is down */
- if (!RTMP_TEST_FLAG(pAdapter, fRTMP_ADAPTER_INTERRUPT_IN_USE)) {
- DBGPRINT(RT_DEBUG_TRACE, ("INFO::Network is down!\n"));
- return -ENETDOWN;
- }
-
- if ((erq->length == 0) && (erq->flags & IW_ENCODE_DISABLED)) {
- pAdapter->StaCfg.PairCipher = Ndis802_11WEPDisabled;
- pAdapter->StaCfg.GroupCipher = Ndis802_11WEPDisabled;
- pAdapter->StaCfg.WepStatus = Ndis802_11WEPDisabled;
- pAdapter->StaCfg.OrigWepStatus = pAdapter->StaCfg.WepStatus;
- pAdapter->StaCfg.AuthMode = Ndis802_11AuthModeOpen;
- goto done;
- } else if (erq->flags & IW_ENCODE_RESTRICTED
- || erq->flags & IW_ENCODE_OPEN) {
- /*pAdapter->StaCfg.PortSecured = WPA_802_1X_PORT_SECURED; */
- STA_PORT_SECURED(pAdapter);
- pAdapter->StaCfg.PairCipher = Ndis802_11WEPEnabled;
- pAdapter->StaCfg.GroupCipher = Ndis802_11WEPEnabled;
- pAdapter->StaCfg.WepStatus = Ndis802_11WEPEnabled;
- pAdapter->StaCfg.OrigWepStatus = pAdapter->StaCfg.WepStatus;
- if (erq->flags & IW_ENCODE_RESTRICTED)
- pAdapter->StaCfg.AuthMode = Ndis802_11AuthModeShared;
- else
- pAdapter->StaCfg.AuthMode = Ndis802_11AuthModeOpen;
- }
-
- if (erq->length > 0) {
- int keyIdx = (erq->flags & IW_ENCODE_INDEX) - 1;
- /* Check the size of the key */
- if (erq->length > MAX_WEP_KEY_SIZE) {
- return -EINVAL;
- }
- /* Check key index */
- if ((keyIdx < 0) || (keyIdx >= NR_WEP_KEYS)) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("==>rt_ioctl_siwencode::Wrong keyIdx=%d! Using default key instead (%d)\n",
- keyIdx, pAdapter->StaCfg.DefaultKeyId));
-
- /*Using default key */
- keyIdx = pAdapter->StaCfg.DefaultKeyId;
- } else
- pAdapter->StaCfg.DefaultKeyId = keyIdx;
-
- NdisZeroMemory(pAdapter->SharedKey[BSS0][keyIdx].Key, 16);
-
- if (erq->length == MAX_WEP_KEY_SIZE) {
- pAdapter->SharedKey[BSS0][keyIdx].KeyLen =
- MAX_WEP_KEY_SIZE;
- pAdapter->SharedKey[BSS0][keyIdx].CipherAlg =
- CIPHER_WEP128;
- } else if (erq->length == MIN_WEP_KEY_SIZE) {
- pAdapter->SharedKey[BSS0][keyIdx].KeyLen =
- MIN_WEP_KEY_SIZE;
- pAdapter->SharedKey[BSS0][keyIdx].CipherAlg =
- CIPHER_WEP64;
- } else
- /* Disable the key */
- pAdapter->SharedKey[BSS0][keyIdx].KeyLen = 0;
-
- /* Check if the key is not marked as invalid */
- if (!(erq->flags & IW_ENCODE_NOKEY)) {
- /* Copy the key in the driver */
- NdisMoveMemory(pAdapter->SharedKey[BSS0][keyIdx].Key,
- extra, erq->length);
- }
- } else {
- /* Do we want to just set the transmit key index ? */
- int index = (erq->flags & IW_ENCODE_INDEX) - 1;
- if ((index >= 0) && (index < 4)) {
- pAdapter->StaCfg.DefaultKeyId = index;
- } else
- /* Don't complain if the mode is only changed */
- if (!(erq->flags & IW_ENCODE_MODE))
- return -EINVAL;
- }
-
-done:
- DBGPRINT(RT_DEBUG_TRACE,
- ("==>rt_ioctl_siwencode::erq->flags=%x\n", erq->flags));
- DBGPRINT(RT_DEBUG_TRACE,
- ("==>rt_ioctl_siwencode::AuthMode=%x\n",
- pAdapter->StaCfg.AuthMode));
- DBGPRINT(RT_DEBUG_TRACE,
- ("==>rt_ioctl_siwencode::DefaultKeyId=%x, KeyLen = %d\n",
- pAdapter->StaCfg.DefaultKeyId,
- pAdapter->SharedKey[BSS0][pAdapter->StaCfg.DefaultKeyId].
- KeyLen));
- DBGPRINT(RT_DEBUG_TRACE,
- ("==>rt_ioctl_siwencode::WepStatus=%x\n",
- pAdapter->StaCfg.WepStatus));
- return 0;
-}
-
-int
-rt_ioctl_giwencode(struct net_device *dev,
- struct iw_request_info *info,
- struct iw_point *erq, char *key)
-{
- int kid;
- struct rt_rtmp_adapter *pAdapter = NULL;
-
- GET_PAD_FROM_NET_DEV(pAdapter, dev);
-
- /*check if the interface is down */
- if (!RTMP_TEST_FLAG(pAdapter, fRTMP_ADAPTER_INTERRUPT_IN_USE)) {
- DBGPRINT(RT_DEBUG_TRACE, ("INFO::Network is down!\n"));
- return -ENETDOWN;
- }
-
- kid = erq->flags & IW_ENCODE_INDEX;
- DBGPRINT(RT_DEBUG_TRACE,
- ("===>rt_ioctl_giwencode %d\n", erq->flags & IW_ENCODE_INDEX));
-
- if (pAdapter->StaCfg.WepStatus == Ndis802_11WEPDisabled) {
- erq->length = 0;
- erq->flags = IW_ENCODE_DISABLED;
- } else if ((kid > 0) && (kid <= 4)) {
- /* copy wep key */
- erq->flags = kid; /* NB: base 1 */
- if (erq->length > pAdapter->SharedKey[BSS0][kid - 1].KeyLen)
- erq->length = pAdapter->SharedKey[BSS0][kid - 1].KeyLen;
- memcpy(key, pAdapter->SharedKey[BSS0][kid - 1].Key,
- erq->length);
- /*if ((kid == pAdapter->PortCfg.DefaultKeyId)) */
- /*erq->flags |= IW_ENCODE_ENABLED; */ /* XXX */
- if (pAdapter->StaCfg.AuthMode == Ndis802_11AuthModeShared)
- erq->flags |= IW_ENCODE_RESTRICTED; /* XXX */
- else
- erq->flags |= IW_ENCODE_OPEN; /* XXX */
-
- } else if (kid == 0) {
- if (pAdapter->StaCfg.AuthMode == Ndis802_11AuthModeShared)
- erq->flags |= IW_ENCODE_RESTRICTED; /* XXX */
- else
- erq->flags |= IW_ENCODE_OPEN; /* XXX */
- erq->length =
- pAdapter->SharedKey[BSS0][pAdapter->StaCfg.DefaultKeyId].
- KeyLen;
- memcpy(key,
- pAdapter->SharedKey[BSS0][pAdapter->StaCfg.DefaultKeyId].
- Key, erq->length);
- /* copy default key ID */
- if (pAdapter->StaCfg.AuthMode == Ndis802_11AuthModeShared)
- erq->flags |= IW_ENCODE_RESTRICTED; /* XXX */
- else
- erq->flags |= IW_ENCODE_OPEN; /* XXX */
- erq->flags = pAdapter->StaCfg.DefaultKeyId + 1; /* NB: base 1 */
- erq->flags |= IW_ENCODE_ENABLED; /* XXX */
- }
-
- return 0;
-
-}
-
-void getBaInfo(struct rt_rtmp_adapter *pAd, char *pOutBuf)
-{
- int i, j;
- struct rt_ba_ori_entry *pOriBAEntry;
- struct rt_ba_rec_entry *pRecBAEntry;
-
- for (i = 0; i < MAX_LEN_OF_MAC_TABLE; i++) {
- struct rt_mac_table_entry *pEntry = &pAd->MacTab.Content[i];
- if (((pEntry->ValidAsCLI || pEntry->ValidAsApCli)
- && (pEntry->Sst == SST_ASSOC))
- || (pEntry->ValidAsWDS) || (pEntry->ValidAsMesh)) {
- sprintf(pOutBuf + strlen(pOutBuf), "\n%pM (Aid = %d) "
- "(AP) -\n", pEntry->Addr, pEntry->Aid);
-
- sprintf(pOutBuf, "%s[Recipient]\n", pOutBuf);
- for (j = 0; j < NUM_OF_TID; j++) {
- if (pEntry->BARecWcidArray[j] != 0) {
- pRecBAEntry =
- &pAd->BATable.BARecEntry[pEntry->
- BARecWcidArray
- [j]];
- sprintf(pOutBuf + strlen(pOutBuf),
- "TID=%d, BAWinSize=%d, LastIndSeq=%d, ReorderingPkts=%d\n",
- j, pRecBAEntry->BAWinSize,
- pRecBAEntry->LastIndSeq,
- pRecBAEntry->list.qlen);
- }
- }
- sprintf(pOutBuf, "%s\n", pOutBuf);
-
- sprintf(pOutBuf, "%s[Originator]\n", pOutBuf);
- for (j = 0; j < NUM_OF_TID; j++) {
- if (pEntry->BAOriWcidArray[j] != 0) {
- pOriBAEntry =
- &pAd->BATable.BAOriEntry[pEntry->
- BAOriWcidArray
- [j]];
- sprintf(pOutBuf + strlen(pOutBuf),
- "TID=%d, BAWinSize=%d, StartSeq=%d, CurTxSeq=%d\n",
- j, pOriBAEntry->BAWinSize,
- pOriBAEntry->Sequence,
- pEntry->TxSeq[j]);
- }
- }
- sprintf(pOutBuf, "%s\n\n", pOutBuf);
- }
- if (strlen(pOutBuf) > (IW_PRIV_SIZE_MASK - 30))
- break;
- }
-
- return;
-}
-
-int rt_ioctl_siwmlme(struct net_device *dev,
- struct iw_request_info *info,
- union iwreq_data *wrqu, char *extra)
-{
- struct rt_rtmp_adapter *pAd = NULL;
- struct iw_mlme *pMlme = (struct iw_mlme *)wrqu->data.pointer;
- struct rt_mlme_queue_elem MsgElem;
- struct rt_mlme_disassoc_req DisAssocReq;
- struct rt_mlme_deauth_req DeAuthReq;
-
- GET_PAD_FROM_NET_DEV(pAd, dev);
-
- DBGPRINT(RT_DEBUG_TRACE, ("====> %s\n", __func__));
-
- if (pMlme == NULL)
- return -EINVAL;
-
- switch (pMlme->cmd) {
-#ifdef IW_MLME_DEAUTH
- case IW_MLME_DEAUTH:
- DBGPRINT(RT_DEBUG_TRACE,
- ("====> %s - IW_MLME_DEAUTH\n", __func__));
- COPY_MAC_ADDR(DeAuthReq.Addr, pAd->CommonCfg.Bssid);
- DeAuthReq.Reason = pMlme->reason_code;
- MsgElem.MsgLen = sizeof(struct rt_mlme_deauth_req);
- NdisMoveMemory(MsgElem.Msg, &DeAuthReq,
- sizeof(struct rt_mlme_deauth_req));
- MlmeDeauthReqAction(pAd, &MsgElem);
- if (INFRA_ON(pAd)) {
- LinkDown(pAd, FALSE);
- pAd->Mlme.AssocMachine.CurrState = ASSOC_IDLE;
- }
- break;
-#endif /* IW_MLME_DEAUTH // */
-#ifdef IW_MLME_DISASSOC
- case IW_MLME_DISASSOC:
- DBGPRINT(RT_DEBUG_TRACE,
- ("====> %s - IW_MLME_DISASSOC\n", __func__));
- COPY_MAC_ADDR(DisAssocReq.Addr, pAd->CommonCfg.Bssid);
- DisAssocReq.Reason = pMlme->reason_code;
-
- MsgElem.Machine = ASSOC_STATE_MACHINE;
- MsgElem.MsgType = MT2_MLME_DISASSOC_REQ;
- MsgElem.MsgLen = sizeof(struct rt_mlme_disassoc_req);
- NdisMoveMemory(MsgElem.Msg, &DisAssocReq,
- sizeof(struct rt_mlme_disassoc_req));
-
- pAd->Mlme.CntlMachine.CurrState = CNTL_WAIT_OID_DISASSOC;
- MlmeDisassocReqAction(pAd, &MsgElem);
- break;
-#endif /* IW_MLME_DISASSOC // */
- default:
- DBGPRINT(RT_DEBUG_TRACE,
- ("====> %s - Unknow Command\n", __func__));
- break;
- }
-
- return 0;
-}
-
-int rt_ioctl_siwauth(struct net_device *dev,
- struct iw_request_info *info,
- union iwreq_data *wrqu, char *extra)
-{
- struct rt_rtmp_adapter *pAdapter = NULL;
- struct iw_param *param = &wrqu->param;
-
- GET_PAD_FROM_NET_DEV(pAdapter, dev);
-
- /*check if the interface is down */
- if (!RTMP_TEST_FLAG(pAdapter, fRTMP_ADAPTER_INTERRUPT_IN_USE)) {
- DBGPRINT(RT_DEBUG_TRACE, ("INFO::Network is down!\n"));
- return -ENETDOWN;
- }
- switch (param->flags & IW_AUTH_INDEX) {
- case IW_AUTH_WPA_VERSION:
- if (param->value == IW_AUTH_WPA_VERSION_WPA) {
- pAdapter->StaCfg.AuthMode = Ndis802_11AuthModeWPAPSK;
- if (pAdapter->StaCfg.BssType == BSS_ADHOC)
- pAdapter->StaCfg.AuthMode =
- Ndis802_11AuthModeWPANone;
- } else if (param->value == IW_AUTH_WPA_VERSION_WPA2)
- pAdapter->StaCfg.AuthMode = Ndis802_11AuthModeWPA2PSK;
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("%s::IW_AUTH_WPA_VERSION - param->value = %d!\n",
- __func__, param->value));
- break;
- case IW_AUTH_CIPHER_PAIRWISE:
- if (param->value == IW_AUTH_CIPHER_NONE) {
- pAdapter->StaCfg.WepStatus = Ndis802_11WEPDisabled;
- pAdapter->StaCfg.OrigWepStatus =
- pAdapter->StaCfg.WepStatus;
- pAdapter->StaCfg.PairCipher = Ndis802_11WEPDisabled;
- } else if (param->value == IW_AUTH_CIPHER_WEP40 ||
- param->value == IW_AUTH_CIPHER_WEP104) {
- pAdapter->StaCfg.WepStatus = Ndis802_11WEPEnabled;
- pAdapter->StaCfg.OrigWepStatus =
- pAdapter->StaCfg.WepStatus;
- pAdapter->StaCfg.PairCipher = Ndis802_11WEPEnabled;
- pAdapter->StaCfg.IEEE8021X = FALSE;
- } else if (param->value == IW_AUTH_CIPHER_TKIP) {
- pAdapter->StaCfg.WepStatus =
- Ndis802_11Encryption2Enabled;
- pAdapter->StaCfg.OrigWepStatus =
- pAdapter->StaCfg.WepStatus;
- pAdapter->StaCfg.PairCipher =
- Ndis802_11Encryption2Enabled;
- } else if (param->value == IW_AUTH_CIPHER_CCMP) {
- pAdapter->StaCfg.WepStatus =
- Ndis802_11Encryption3Enabled;
- pAdapter->StaCfg.OrigWepStatus =
- pAdapter->StaCfg.WepStatus;
- pAdapter->StaCfg.PairCipher =
- Ndis802_11Encryption3Enabled;
- }
- DBGPRINT(RT_DEBUG_TRACE,
- ("%s::IW_AUTH_CIPHER_PAIRWISE - param->value = %d!\n",
- __func__, param->value));
- break;
- case IW_AUTH_CIPHER_GROUP:
- if (param->value == IW_AUTH_CIPHER_NONE) {
- pAdapter->StaCfg.GroupCipher = Ndis802_11WEPDisabled;
- } else if (param->value == IW_AUTH_CIPHER_WEP40 ||
- param->value == IW_AUTH_CIPHER_WEP104) {
- pAdapter->StaCfg.GroupCipher = Ndis802_11WEPEnabled;
- } else if (param->value == IW_AUTH_CIPHER_TKIP) {
- pAdapter->StaCfg.GroupCipher =
- Ndis802_11Encryption2Enabled;
- } else if (param->value == IW_AUTH_CIPHER_CCMP) {
- pAdapter->StaCfg.GroupCipher =
- Ndis802_11Encryption3Enabled;
- }
- DBGPRINT(RT_DEBUG_TRACE,
- ("%s::IW_AUTH_CIPHER_GROUP - param->value = %d!\n",
- __func__, param->value));
- break;
- case IW_AUTH_KEY_MGMT:
- if (param->value == IW_AUTH_KEY_MGMT_802_1X) {
- if (pAdapter->StaCfg.AuthMode ==
- Ndis802_11AuthModeWPAPSK) {
- pAdapter->StaCfg.AuthMode =
- Ndis802_11AuthModeWPA;
- pAdapter->StaCfg.IEEE8021X = FALSE;
- } else if (pAdapter->StaCfg.AuthMode ==
- Ndis802_11AuthModeWPA2PSK) {
- pAdapter->StaCfg.AuthMode =
- Ndis802_11AuthModeWPA2;
- pAdapter->StaCfg.IEEE8021X = FALSE;
- } else
- /* WEP 1x */
- pAdapter->StaCfg.IEEE8021X = TRUE;
- } else if (param->value == 0) {
- /*pAdapter->StaCfg.PortSecured = WPA_802_1X_PORT_SECURED; */
- STA_PORT_SECURED(pAdapter);
- }
- DBGPRINT(RT_DEBUG_TRACE,
- ("%s::IW_AUTH_KEY_MGMT - param->value = %d!\n",
- __func__, param->value));
- break;
- case IW_AUTH_RX_UNENCRYPTED_EAPOL:
- break;
- case IW_AUTH_PRIVACY_INVOKED:
- /*if (param->value == 0)
- {
- pAdapter->StaCfg.AuthMode = Ndis802_11AuthModeOpen;
- pAdapter->StaCfg.WepStatus = Ndis802_11WEPDisabled;
- pAdapter->StaCfg.OrigWepStatus = pAdapter->StaCfg.WepStatus;
- pAdapter->StaCfg.PairCipher = Ndis802_11WEPDisabled;
- pAdapter->StaCfg.GroupCipher = Ndis802_11WEPDisabled;
- } */
- DBGPRINT(RT_DEBUG_TRACE,
- ("%s::IW_AUTH_PRIVACY_INVOKED - param->value = %d!\n",
- __func__, param->value));
- break;
- case IW_AUTH_DROP_UNENCRYPTED:
- if (param->value != 0)
- pAdapter->StaCfg.PortSecured =
- WPA_802_1X_PORT_NOT_SECURED;
- else {
- /*pAdapter->StaCfg.PortSecured = WPA_802_1X_PORT_SECURED; */
- STA_PORT_SECURED(pAdapter);
- }
- DBGPRINT(RT_DEBUG_TRACE,
- ("%s::IW_AUTH_WPA_VERSION - param->value = %d!\n",
- __func__, param->value));
- break;
- case IW_AUTH_80211_AUTH_ALG:
- if (param->value & IW_AUTH_ALG_SHARED_KEY) {
- pAdapter->StaCfg.AuthMode = Ndis802_11AuthModeShared;
- } else if (param->value & IW_AUTH_ALG_OPEN_SYSTEM) {
- pAdapter->StaCfg.AuthMode = Ndis802_11AuthModeOpen;
- } else
- return -EINVAL;
- DBGPRINT(RT_DEBUG_TRACE,
- ("%s::IW_AUTH_80211_AUTH_ALG - param->value = %d!\n",
- __func__, param->value));
- break;
- case IW_AUTH_WPA_ENABLED:
- DBGPRINT(RT_DEBUG_TRACE,
- ("%s::IW_AUTH_WPA_ENABLED - Driver supports WPA!(param->value = %d)\n",
- __func__, param->value));
- break;
- default:
- return -EOPNOTSUPP;
- }
-
- return 0;
-}
-
-int rt_ioctl_giwauth(struct net_device *dev,
- struct iw_request_info *info,
- union iwreq_data *wrqu, char *extra)
-{
- struct rt_rtmp_adapter *pAdapter = NULL;
- struct iw_param *param = &wrqu->param;
-
- GET_PAD_FROM_NET_DEV(pAdapter, dev);
-
- /*check if the interface is down */
- if (!RTMP_TEST_FLAG(pAdapter, fRTMP_ADAPTER_INTERRUPT_IN_USE)) {
- DBGPRINT(RT_DEBUG_TRACE, ("INFO::Network is down!\n"));
- return -ENETDOWN;
- }
-
- switch (param->flags & IW_AUTH_INDEX) {
- case IW_AUTH_DROP_UNENCRYPTED:
- param->value =
- (pAdapter->StaCfg.WepStatus ==
- Ndis802_11WEPDisabled) ? 0 : 1;
- break;
-
- case IW_AUTH_80211_AUTH_ALG:
- param->value =
- (pAdapter->StaCfg.AuthMode ==
- Ndis802_11AuthModeShared) ? IW_AUTH_ALG_SHARED_KEY :
- IW_AUTH_ALG_OPEN_SYSTEM;
- break;
-
- case IW_AUTH_WPA_ENABLED:
- param->value =
- (pAdapter->StaCfg.AuthMode >=
- Ndis802_11AuthModeWPA) ? 1 : 0;
- break;
-
- default:
- return -EOPNOTSUPP;
- }
- DBGPRINT(RT_DEBUG_TRACE,
- ("rt_ioctl_giwauth::param->value = %d!\n", param->value));
- return 0;
-}
-
-void fnSetCipherKey(struct rt_rtmp_adapter *pAdapter,
- int keyIdx,
- u8 CipherAlg,
- IN BOOLEAN bGTK, IN struct iw_encode_ext *ext)
-{
- NdisZeroMemory(&pAdapter->SharedKey[BSS0][keyIdx], sizeof(struct rt_cipher_key));
- pAdapter->SharedKey[BSS0][keyIdx].KeyLen = LEN_TKIP_EK;
- NdisMoveMemory(pAdapter->SharedKey[BSS0][keyIdx].Key, ext->key,
- LEN_TKIP_EK);
- NdisMoveMemory(pAdapter->SharedKey[BSS0][keyIdx].TxMic,
- ext->key + LEN_TKIP_EK, LEN_TKIP_TXMICK);
- NdisMoveMemory(pAdapter->SharedKey[BSS0][keyIdx].RxMic,
- ext->key + LEN_TKIP_EK + LEN_TKIP_TXMICK,
- LEN_TKIP_RXMICK);
- pAdapter->SharedKey[BSS0][keyIdx].CipherAlg = CipherAlg;
-
- /* Update group key information to ASIC Shared Key Table */
- AsicAddSharedKeyEntry(pAdapter,
- BSS0,
- keyIdx,
- pAdapter->SharedKey[BSS0][keyIdx].CipherAlg,
- pAdapter->SharedKey[BSS0][keyIdx].Key,
- pAdapter->SharedKey[BSS0][keyIdx].TxMic,
- pAdapter->SharedKey[BSS0][keyIdx].RxMic);
-
- if (bGTK)
- /* Update ASIC WCID attribute table and IVEIV table */
- RTMPAddWcidAttributeEntry(pAdapter,
- BSS0,
- keyIdx,
- pAdapter->SharedKey[BSS0][keyIdx].
- CipherAlg, NULL);
- else
- /* Update ASIC WCID attribute table and IVEIV table */
- RTMPAddWcidAttributeEntry(pAdapter,
- BSS0,
- keyIdx,
- pAdapter->SharedKey[BSS0][keyIdx].
- CipherAlg,
- &pAdapter->MacTab.
- Content[BSSID_WCID]);
-}
-
-int rt_ioctl_siwencodeext(struct net_device *dev,
- struct iw_request_info *info,
- union iwreq_data *wrqu, char *extra)
-{
- struct rt_rtmp_adapter *pAdapter = NULL;
- struct iw_point *encoding = &wrqu->encoding;
- struct iw_encode_ext *ext = (struct iw_encode_ext *)extra;
- int keyIdx, alg = ext->alg;
-
- GET_PAD_FROM_NET_DEV(pAdapter, dev);
-
- /*check if the interface is down */
- if (!RTMP_TEST_FLAG(pAdapter, fRTMP_ADAPTER_INTERRUPT_IN_USE)) {
- DBGPRINT(RT_DEBUG_TRACE, ("INFO::Network is down!\n"));
- return -ENETDOWN;
- }
-
- if (encoding->flags & IW_ENCODE_DISABLED) {
- keyIdx = (encoding->flags & IW_ENCODE_INDEX) - 1;
- /* set BSSID wcid entry of the Pair-wise Key table as no-security mode */
- AsicRemovePairwiseKeyEntry(pAdapter, BSS0, BSSID_WCID);
- pAdapter->SharedKey[BSS0][keyIdx].KeyLen = 0;
- pAdapter->SharedKey[BSS0][keyIdx].CipherAlg = CIPHER_NONE;
- AsicRemoveSharedKeyEntry(pAdapter, 0, (u8)keyIdx);
- NdisZeroMemory(&pAdapter->SharedKey[BSS0][keyIdx],
- sizeof(struct rt_cipher_key));
- DBGPRINT(RT_DEBUG_TRACE,
- ("%s::Remove all keys!(encoding->flags = %x)\n",
- __func__, encoding->flags));
- } else {
- /* Get Key Index and convet to our own defined key index */
- keyIdx = (encoding->flags & IW_ENCODE_INDEX) - 1;
- if ((keyIdx < 0) || (keyIdx >= NR_WEP_KEYS))
- return -EINVAL;
-
- if (ext->ext_flags & IW_ENCODE_EXT_SET_TX_KEY) {
- pAdapter->StaCfg.DefaultKeyId = keyIdx;
- DBGPRINT(RT_DEBUG_TRACE,
- ("%s::DefaultKeyId = %d\n", __func__,
- pAdapter->StaCfg.DefaultKeyId));
- }
-
- switch (alg) {
- case IW_ENCODE_ALG_NONE:
- DBGPRINT(RT_DEBUG_TRACE,
- ("%s::IW_ENCODE_ALG_NONE\n", __func__));
- break;
- case IW_ENCODE_ALG_WEP:
- DBGPRINT(RT_DEBUG_TRACE,
- ("%s::IW_ENCODE_ALG_WEP - ext->key_len = %d, keyIdx = %d\n",
- __func__, ext->key_len, keyIdx));
- if (ext->key_len == MAX_WEP_KEY_SIZE) {
- pAdapter->SharedKey[BSS0][keyIdx].KeyLen =
- MAX_WEP_KEY_SIZE;
- pAdapter->SharedKey[BSS0][keyIdx].CipherAlg =
- CIPHER_WEP128;
- } else if (ext->key_len == MIN_WEP_KEY_SIZE) {
- pAdapter->SharedKey[BSS0][keyIdx].KeyLen =
- MIN_WEP_KEY_SIZE;
- pAdapter->SharedKey[BSS0][keyIdx].CipherAlg =
- CIPHER_WEP64;
- } else
- return -EINVAL;
-
- NdisZeroMemory(pAdapter->SharedKey[BSS0][keyIdx].Key,
- 16);
- NdisMoveMemory(pAdapter->SharedKey[BSS0][keyIdx].Key,
- ext->key, ext->key_len);
- if (pAdapter->StaCfg.GroupCipher ==
- Ndis802_11GroupWEP40Enabled
- || pAdapter->StaCfg.GroupCipher ==
- Ndis802_11GroupWEP104Enabled) {
- /* Set Group key material to Asic */
- AsicAddSharedKeyEntry(pAdapter, BSS0, keyIdx,
- pAdapter->
- SharedKey[BSS0][keyIdx].
- CipherAlg,
- pAdapter->
- SharedKey[BSS0][keyIdx].
- Key, NULL, NULL);
-
- /* Update WCID attribute table and IVEIV table for this group key table */
- RTMPAddWcidAttributeEntry(pAdapter, BSS0,
- keyIdx,
- pAdapter->
- SharedKey[BSS0]
- [keyIdx].CipherAlg,
- NULL);
-
- STA_PORT_SECURED(pAdapter);
-
- /* Indicate Connected for GUI */
- pAdapter->IndicateMediaState =
- NdisMediaStateConnected;
- }
- break;
- case IW_ENCODE_ALG_TKIP:
- DBGPRINT(RT_DEBUG_TRACE,
- ("%s::IW_ENCODE_ALG_TKIP - keyIdx = %d, ext->key_len = %d\n",
- __func__, keyIdx, ext->key_len));
- if (ext->key_len == 32) {
- if (ext->ext_flags & IW_ENCODE_EXT_SET_TX_KEY) {
- fnSetCipherKey(pAdapter, keyIdx,
- CIPHER_TKIP, FALSE, ext);
- if (pAdapter->StaCfg.AuthMode >=
- Ndis802_11AuthModeWPA2) {
- /*pAdapter->StaCfg.PortSecured = WPA_802_1X_PORT_SECURED; */
- STA_PORT_SECURED(pAdapter);
- pAdapter->IndicateMediaState =
- NdisMediaStateConnected;
- }
- } else if (ext->
- ext_flags & IW_ENCODE_EXT_GROUP_KEY)
- {
- fnSetCipherKey(pAdapter, keyIdx,
- CIPHER_TKIP, TRUE, ext);
-
- /* set 802.1x port control */
- /*pAdapter->StaCfg.PortSecured = WPA_802_1X_PORT_SECURED; */
- STA_PORT_SECURED(pAdapter);
- pAdapter->IndicateMediaState =
- NdisMediaStateConnected;
- }
- } else
- return -EINVAL;
- break;
- case IW_ENCODE_ALG_CCMP:
- if (ext->ext_flags & IW_ENCODE_EXT_SET_TX_KEY) {
- fnSetCipherKey(pAdapter, keyIdx, CIPHER_AES,
- FALSE, ext);
- if (pAdapter->StaCfg.AuthMode >=
- Ndis802_11AuthModeWPA2)
- /*pAdapter->StaCfg.PortSecured = WPA_802_1X_PORT_SECURED; */
- STA_PORT_SECURED(pAdapter);
- pAdapter->IndicateMediaState =
- NdisMediaStateConnected;
- } else if (ext->ext_flags & IW_ENCODE_EXT_GROUP_KEY) {
- fnSetCipherKey(pAdapter, keyIdx, CIPHER_AES,
- TRUE, ext);
-
- /* set 802.1x port control */
- /*pAdapter->StaCfg.PortSecured = WPA_802_1X_PORT_SECURED; */
- STA_PORT_SECURED(pAdapter);
- pAdapter->IndicateMediaState =
- NdisMediaStateConnected;
- }
- break;
- default:
- return -EINVAL;
- }
- }
-
- return 0;
-}
-
-int
-rt_ioctl_giwencodeext(struct net_device *dev,
- struct iw_request_info *info,
- union iwreq_data *wrqu, char *extra)
-{
- struct rt_rtmp_adapter *pAd = NULL;
- char *pKey = NULL;
- struct iw_point *encoding = &wrqu->encoding;
- struct iw_encode_ext *ext = (struct iw_encode_ext *)extra;
- int idx, max_key_len;
-
- GET_PAD_FROM_NET_DEV(pAd, dev);
-
- DBGPRINT(RT_DEBUG_TRACE, ("===> rt_ioctl_giwencodeext\n"));
-
- max_key_len = encoding->length - sizeof(*ext);
- if (max_key_len < 0)
- return -EINVAL;
-
- idx = encoding->flags & IW_ENCODE_INDEX;
- if (idx) {
- if (idx < 1 || idx > 4)
- return -EINVAL;
- idx--;
-
- if ((pAd->StaCfg.WepStatus == Ndis802_11Encryption2Enabled) ||
- (pAd->StaCfg.WepStatus == Ndis802_11Encryption3Enabled)) {
- if (idx != pAd->StaCfg.DefaultKeyId) {
- ext->key_len = 0;
- return 0;
- }
- }
- } else
- idx = pAd->StaCfg.DefaultKeyId;
-
- encoding->flags = idx + 1;
- memset(ext, 0, sizeof(*ext));
-
- ext->key_len = 0;
- switch (pAd->StaCfg.WepStatus) {
- case Ndis802_11WEPDisabled:
- ext->alg = IW_ENCODE_ALG_NONE;
- encoding->flags |= IW_ENCODE_DISABLED;
- break;
- case Ndis802_11WEPEnabled:
- ext->alg = IW_ENCODE_ALG_WEP;
- if (pAd->SharedKey[BSS0][idx].KeyLen > max_key_len)
- return -E2BIG;
- else {
- ext->key_len = pAd->SharedKey[BSS0][idx].KeyLen;
- pKey = (char *)& (pAd->SharedKey[BSS0][idx].Key[0]);
- }
- break;
- case Ndis802_11Encryption2Enabled:
- case Ndis802_11Encryption3Enabled:
- if (pAd->StaCfg.WepStatus == Ndis802_11Encryption2Enabled)
- ext->alg = IW_ENCODE_ALG_TKIP;
- else
- ext->alg = IW_ENCODE_ALG_CCMP;
-
- if (max_key_len < 32)
- return -E2BIG;
- else {
- ext->key_len = 32;
- pKey = (char *)& pAd->StaCfg.PMK[0];
- }
- break;
- default:
- return -EINVAL;
- }
-
- if (ext->key_len && pKey) {
- encoding->flags |= IW_ENCODE_ENABLED;
- memcpy(ext->key, pKey, ext->key_len);
- }
-
- return 0;
-}
-
-int rt_ioctl_siwgenie(struct net_device *dev,
- struct iw_request_info *info,
- union iwreq_data *wrqu, char *extra)
-{
- struct rt_rtmp_adapter *pAd = NULL;
-
- GET_PAD_FROM_NET_DEV(pAd, dev);
-
- DBGPRINT(RT_DEBUG_TRACE, ("===> rt_ioctl_siwgenie\n"));
- pAd->StaCfg.bRSN_IE_FromWpaSupplicant = FALSE;
- if (wrqu->data.length > MAX_LEN_OF_RSNIE ||
- (wrqu->data.length && extra == NULL))
- return -EINVAL;
-
- if (wrqu->data.length) {
- pAd->StaCfg.RSNIE_Len = wrqu->data.length;
- NdisMoveMemory(&pAd->StaCfg.RSN_IE[0], extra,
- pAd->StaCfg.RSNIE_Len);
- pAd->StaCfg.bRSN_IE_FromWpaSupplicant = TRUE;
- } else {
- pAd->StaCfg.RSNIE_Len = 0;
- NdisZeroMemory(&pAd->StaCfg.RSN_IE[0], MAX_LEN_OF_RSNIE);
- }
-
- return 0;
-}
-
-int rt_ioctl_giwgenie(struct net_device *dev,
- struct iw_request_info *info,
- union iwreq_data *wrqu, char *extra)
-{
- struct rt_rtmp_adapter *pAd = NULL;
-
- GET_PAD_FROM_NET_DEV(pAd, dev);
-
- if ((pAd->StaCfg.RSNIE_Len == 0) ||
- (pAd->StaCfg.AuthMode < Ndis802_11AuthModeWPA)) {
- wrqu->data.length = 0;
- return 0;
- }
-
- if (pAd->StaCfg.WpaSupplicantUP == WPA_SUPPLICANT_ENABLE) {
- if (wrqu->data.length < pAd->StaCfg.RSNIE_Len)
- return -E2BIG;
-
- wrqu->data.length = pAd->StaCfg.RSNIE_Len;
- memcpy(extra, &pAd->StaCfg.RSN_IE[0], pAd->StaCfg.RSNIE_Len);
- } else {
- u8 RSNIe = IE_WPA;
-
- if (wrqu->data.length < (pAd->StaCfg.RSNIE_Len + 2)) /* ID, Len */
- return -E2BIG;
- wrqu->data.length = pAd->StaCfg.RSNIE_Len + 2;
-
- if ((pAd->StaCfg.AuthMode == Ndis802_11AuthModeWPA2PSK) ||
- (pAd->StaCfg.AuthMode == Ndis802_11AuthModeWPA2))
- RSNIe = IE_RSN;
-
- extra[0] = (char)RSNIe;
- extra[1] = pAd->StaCfg.RSNIE_Len;
- memcpy(extra + 2, &pAd->StaCfg.RSN_IE[0],
- pAd->StaCfg.RSNIE_Len);
- }
-
- return 0;
-}
-
-int rt_ioctl_siwpmksa(struct net_device *dev,
- struct iw_request_info *info,
- union iwreq_data *wrqu, char *extra)
-{
- struct rt_rtmp_adapter *pAd = NULL;
- struct iw_pmksa *pPmksa = (struct iw_pmksa *)wrqu->data.pointer;
- int CachedIdx = 0, idx = 0;
-
- GET_PAD_FROM_NET_DEV(pAd, dev);
-
- if (pPmksa == NULL)
- return -EINVAL;
-
- DBGPRINT(RT_DEBUG_TRACE, ("===> rt_ioctl_siwpmksa\n"));
- switch (pPmksa->cmd) {
- case IW_PMKSA_FLUSH:
- NdisZeroMemory(pAd->StaCfg.SavedPMK,
- sizeof(struct rt_bssid_info) * PMKID_NO);
- DBGPRINT(RT_DEBUG_TRACE,
- ("rt_ioctl_siwpmksa - IW_PMKSA_FLUSH\n"));
- break;
- case IW_PMKSA_REMOVE:
- for (CachedIdx = 0; CachedIdx < pAd->StaCfg.SavedPMKNum;
- CachedIdx++) {
- /* compare the BSSID */
- if (NdisEqualMemory
- (pPmksa->bssid.sa_data,
- pAd->StaCfg.SavedPMK[CachedIdx].BSSID,
- MAC_ADDR_LEN)) {
- NdisZeroMemory(pAd->StaCfg.SavedPMK[CachedIdx].
- BSSID, MAC_ADDR_LEN);
- NdisZeroMemory(pAd->StaCfg.SavedPMK[CachedIdx].
- PMKID, 16);
- for (idx = CachedIdx;
- idx < (pAd->StaCfg.SavedPMKNum - 1);
- idx++) {
- NdisMoveMemory(&pAd->StaCfg.
- SavedPMK[idx].BSSID[0],
- &pAd->StaCfg.
- SavedPMK[idx +
- 1].BSSID[0],
- MAC_ADDR_LEN);
- NdisMoveMemory(&pAd->StaCfg.
- SavedPMK[idx].PMKID[0],
- &pAd->StaCfg.
- SavedPMK[idx +
- 1].PMKID[0],
- 16);
- }
- pAd->StaCfg.SavedPMKNum--;
- break;
- }
- }
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("rt_ioctl_siwpmksa - IW_PMKSA_REMOVE\n"));
- break;
- case IW_PMKSA_ADD:
- for (CachedIdx = 0; CachedIdx < pAd->StaCfg.SavedPMKNum;
- CachedIdx++) {
- /* compare the BSSID */
- if (NdisEqualMemory
- (pPmksa->bssid.sa_data,
- pAd->StaCfg.SavedPMK[CachedIdx].BSSID,
- MAC_ADDR_LEN))
- break;
- }
-
- /* Found, replace it */
- if (CachedIdx < PMKID_NO) {
- DBGPRINT(RT_DEBUG_OFF,
- ("Update PMKID, idx = %d\n", CachedIdx));
- NdisMoveMemory(&pAd->StaCfg.SavedPMK[CachedIdx].
- BSSID[0], pPmksa->bssid.sa_data,
- MAC_ADDR_LEN);
- NdisMoveMemory(&pAd->StaCfg.SavedPMK[CachedIdx].
- PMKID[0], pPmksa->pmkid, 16);
- pAd->StaCfg.SavedPMKNum++;
- }
- /* Not found, replace the last one */
- else {
- /* Randomly replace one */
- CachedIdx = (pPmksa->bssid.sa_data[5] % PMKID_NO);
- DBGPRINT(RT_DEBUG_OFF,
- ("Update PMKID, idx = %d\n", CachedIdx));
- NdisMoveMemory(&pAd->StaCfg.SavedPMK[CachedIdx].
- BSSID[0], pPmksa->bssid.sa_data,
- MAC_ADDR_LEN);
- NdisMoveMemory(&pAd->StaCfg.SavedPMK[CachedIdx].
- PMKID[0], pPmksa->pmkid, 16);
- }
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("rt_ioctl_siwpmksa - IW_PMKSA_ADD\n"));
- break;
- default:
- DBGPRINT(RT_DEBUG_TRACE,
- ("rt_ioctl_siwpmksa - Unknown Command!\n"));
- break;
- }
-
- return 0;
-}
-
-int rt_ioctl_siwrate(struct net_device *dev,
- struct iw_request_info *info,
- union iwreq_data *wrqu, char *extra)
-{
- struct rt_rtmp_adapter *pAd = NULL;
- u32 rate = wrqu->bitrate.value, fixed = wrqu->bitrate.fixed;
-
- GET_PAD_FROM_NET_DEV(pAd, dev);
-
- /*check if the interface is down */
- if (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_IN_USE)) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("rt_ioctl_siwrate::Network is down!\n"));
- return -ENETDOWN;
- }
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("rt_ioctl_siwrate::(rate = %d, fixed = %d)\n", rate, fixed));
- /* rate = -1 => auto rate
- rate = X, fixed = 1 => (fixed rate X)
- */
- if (rate == -1) {
- /*Auto Rate */
- pAd->StaCfg.DesiredTransmitSetting.field.MCS = MCS_AUTO;
- pAd->StaCfg.bAutoTxRateSwitch = TRUE;
- if ((pAd->CommonCfg.PhyMode <= PHY_11G) ||
- (pAd->MacTab.Content[BSSID_WCID].HTPhyMode.field.MODE <=
- MODE_OFDM))
- RTMPSetDesiredRates(pAd, -1);
-
- SetCommonHT(pAd);
- } else {
- if (fixed) {
- pAd->StaCfg.bAutoTxRateSwitch = FALSE;
- if ((pAd->CommonCfg.PhyMode <= PHY_11G) ||
- (pAd->MacTab.Content[BSSID_WCID].HTPhyMode.field.
- MODE <= MODE_OFDM))
- RTMPSetDesiredRates(pAd, rate);
- else {
- pAd->StaCfg.DesiredTransmitSetting.field.MCS =
- MCS_AUTO;
- SetCommonHT(pAd);
- }
- DBGPRINT(RT_DEBUG_TRACE,
- ("rt_ioctl_siwrate::(HtMcs=%d)\n",
- pAd->StaCfg.DesiredTransmitSetting.field.
- MCS));
- } else {
- /* TODO: rate = X, fixed = 0 => (rates <= X) */
- return -EOPNOTSUPP;
- }
- }
-
- return 0;
-}
-
-int rt_ioctl_giwrate(struct net_device *dev,
- struct iw_request_info *info,
- union iwreq_data *wrqu, char *extra)
-{
- struct rt_rtmp_adapter *pAd = NULL;
- int rate_index = 0, rate_count = 0;
- HTTRANSMIT_SETTING ht_setting;
-/* Remove to global variable
- __s32 ralinkrate[] =
- {2, 4, 11, 22, // CCK
- 12, 18, 24, 36, 48, 72, 96, 108, // OFDM
- 13, 26, 39, 52, 78, 104, 117, 130, 26, 52, 78, 104, 156, 208, 234, 260, // 20MHz, 800ns GI, MCS: 0 ~ 15
- 39, 78, 117, 156, 234, 312, 351, 390, // 20MHz, 800ns GI, MCS: 16 ~ 23
- 27, 54, 81, 108, 162, 216, 243, 270, 54, 108, 162, 216, 324, 432, 486, 540, // 40MHz, 800ns GI, MCS: 0 ~ 15
- 81, 162, 243, 324, 486, 648, 729, 810, // 40MHz, 800ns GI, MCS: 16 ~ 23
- 14, 29, 43, 57, 87, 115, 130, 144, 29, 59, 87, 115, 173, 230, 260, 288, // 20MHz, 400ns GI, MCS: 0 ~ 15
- 43, 87, 130, 173, 260, 317, 390, 433, // 20MHz, 400ns GI, MCS: 16 ~ 23
- 30, 60, 90, 120, 180, 240, 270, 300, 60, 120, 180, 240, 360, 480, 540, 600, // 40MHz, 400ns GI, MCS: 0 ~ 15
- 90, 180, 270, 360, 540, 720, 810, 900}; // 40MHz, 400ns GI, MCS: 16 ~ 23
-*/
- GET_PAD_FROM_NET_DEV(pAd, dev);
-
- rate_count = ARRAY_SIZE(ralinkrate);
- /*check if the interface is down */
- if (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_IN_USE)) {
- DBGPRINT(RT_DEBUG_TRACE, ("INFO::Network is down!\n"));
- return -ENETDOWN;
- }
-
- if ((pAd->StaCfg.bAutoTxRateSwitch == FALSE) &&
- (INFRA_ON(pAd)) &&
- ((pAd->CommonCfg.PhyMode <= PHY_11G)
- || (pAd->MacTab.Content[BSSID_WCID].HTPhyMode.field.MODE <=
- MODE_OFDM)))
- ht_setting.word = pAd->StaCfg.HTPhyMode.word;
- else
- ht_setting.word =
- pAd->MacTab.Content[BSSID_WCID].HTPhyMode.word;
-
- if (ht_setting.field.MODE >= MODE_HTMIX) {
-/* rate_index = 12 + ((u8)ht_setting.field.BW *16) + ((u8)ht_setting.field.ShortGI *32) + ((u8)ht_setting.field.MCS); */
- rate_index =
- 12 + ((u8)ht_setting.field.BW * 24) +
- ((u8)ht_setting.field.ShortGI * 48) +
- ((u8)ht_setting.field.MCS);
- } else if (ht_setting.field.MODE == MODE_OFDM)
- rate_index = (u8)(ht_setting.field.MCS) + 4;
- else if (ht_setting.field.MODE == MODE_CCK)
- rate_index = (u8)(ht_setting.field.MCS);
-
- if (rate_index < 0)
- rate_index = 0;
-
- if (rate_index >= rate_count)
- rate_index = rate_count - 1;
-
- wrqu->bitrate.value = ralinkrate[rate_index] * 500000;
- wrqu->bitrate.disabled = 0;
-
- return 0;
-}
-
-static const iw_handler rt_handler[] = {
- (iw_handler) NULL, /* SIOCSIWCOMMIT */
- (iw_handler) rt_ioctl_giwname, /* SIOCGIWNAME */
- (iw_handler) NULL, /* SIOCSIWNWID */
- (iw_handler) NULL, /* SIOCGIWNWID */
- (iw_handler) rt_ioctl_siwfreq, /* SIOCSIWFREQ */
- (iw_handler) rt_ioctl_giwfreq, /* SIOCGIWFREQ */
- (iw_handler) rt_ioctl_siwmode, /* SIOCSIWMODE */
- (iw_handler) rt_ioctl_giwmode, /* SIOCGIWMODE */
- (iw_handler) NULL, /* SIOCSIWSENS */
- (iw_handler) NULL, /* SIOCGIWSENS */
- (iw_handler) NULL /* not used */ , /* SIOCSIWRANGE */
- (iw_handler) rt_ioctl_giwrange, /* SIOCGIWRANGE */
- (iw_handler) NULL /* not used */ , /* SIOCSIWPRIV */
- (iw_handler) NULL /* kernel code */ , /* SIOCGIWPRIV */
- (iw_handler) NULL /* not used */ , /* SIOCSIWSTATS */
- (iw_handler) rt28xx_get_wireless_stats /* kernel code */ , /* SIOCGIWSTATS */
- (iw_handler) NULL, /* SIOCSIWSPY */
- (iw_handler) NULL, /* SIOCGIWSPY */
- (iw_handler) NULL, /* SIOCSIWTHRSPY */
- (iw_handler) NULL, /* SIOCGIWTHRSPY */
- (iw_handler) rt_ioctl_siwap, /* SIOCSIWAP */
- (iw_handler) rt_ioctl_giwap, /* SIOCGIWAP */
- (iw_handler) rt_ioctl_siwmlme, /* SIOCSIWMLME */
- (iw_handler) rt_ioctl_iwaplist, /* SIOCGIWAPLIST */
- (iw_handler) rt_ioctl_siwscan, /* SIOCSIWSCAN */
- (iw_handler) rt_ioctl_giwscan, /* SIOCGIWSCAN */
- (iw_handler) rt_ioctl_siwessid, /* SIOCSIWESSID */
- (iw_handler) rt_ioctl_giwessid, /* SIOCGIWESSID */
- (iw_handler) rt_ioctl_siwnickn, /* SIOCSIWNICKN */
- (iw_handler) rt_ioctl_giwnickn, /* SIOCGIWNICKN */
- (iw_handler) NULL, /* -- hole -- */
- (iw_handler) NULL, /* -- hole -- */
- (iw_handler) rt_ioctl_siwrate, /* SIOCSIWRATE */
- (iw_handler) rt_ioctl_giwrate, /* SIOCGIWRATE */
- (iw_handler) rt_ioctl_siwrts, /* SIOCSIWRTS */
- (iw_handler) rt_ioctl_giwrts, /* SIOCGIWRTS */
- (iw_handler) rt_ioctl_siwfrag, /* SIOCSIWFRAG */
- (iw_handler) rt_ioctl_giwfrag, /* SIOCGIWFRAG */
- (iw_handler) NULL, /* SIOCSIWTXPOW */
- (iw_handler) NULL, /* SIOCGIWTXPOW */
- (iw_handler) NULL, /* SIOCSIWRETRY */
- (iw_handler) NULL, /* SIOCGIWRETRY */
- (iw_handler) rt_ioctl_siwencode, /* SIOCSIWENCODE */
- (iw_handler) rt_ioctl_giwencode, /* SIOCGIWENCODE */
- (iw_handler) NULL, /* SIOCSIWPOWER */
- (iw_handler) NULL, /* SIOCGIWPOWER */
- (iw_handler) NULL, /* -- hole -- */
- (iw_handler) NULL, /* -- hole -- */
- (iw_handler) rt_ioctl_siwgenie, /* SIOCSIWGENIE */
- (iw_handler) rt_ioctl_giwgenie, /* SIOCGIWGENIE */
- (iw_handler) rt_ioctl_siwauth, /* SIOCSIWAUTH */
- (iw_handler) rt_ioctl_giwauth, /* SIOCGIWAUTH */
- (iw_handler) rt_ioctl_siwencodeext, /* SIOCSIWENCODEEXT */
- (iw_handler) rt_ioctl_giwencodeext, /* SIOCGIWENCODEEXT */
- (iw_handler) rt_ioctl_siwpmksa, /* SIOCSIWPMKSA */
-};
-
-const struct iw_handler_def rt28xx_iw_handler_def = {
- .standard = (iw_handler *) rt_handler,
- .num_standard = sizeof(rt_handler) / sizeof(iw_handler),
-#if IW_HANDLER_VERSION >= 7
- .get_wireless_stats = rt28xx_get_wireless_stats,
-#endif
-};
-
-int rt28xx_sta_ioctl(IN struct net_device *net_dev,
- IN OUT struct ifreq *rq, int cmd)
-{
- struct os_cookie *pObj;
- struct rt_rtmp_adapter *pAd = NULL;
- struct iwreq *wrq = (struct iwreq *)rq;
- BOOLEAN StateMachineTouched = FALSE;
- int Status = NDIS_STATUS_SUCCESS;
-
- GET_PAD_FROM_NET_DEV(pAd, net_dev);
-
- pObj = (struct os_cookie *)pAd->OS_Cookie;
-
- /*check if the interface is down */
- if (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_INTERRUPT_IN_USE)) {
- {
- DBGPRINT(RT_DEBUG_TRACE, ("INFO::Network is down!\n"));
- return -ENETDOWN;
- }
- }
-
- { /* determine this ioctl command is coming from which interface. */
- pObj->ioctl_if_type = INT_MAIN;
- pObj->ioctl_if = MAIN_MBSSID;
- }
-
- switch (cmd) {
- case SIOCGIFHWADDR:
- DBGPRINT(RT_DEBUG_TRACE, ("IOCTL::SIOCGIFHWADDR\n"));
- memcpy(wrq->u.name, pAd->CurrentAddress, ETH_ALEN);
- break;
- case SIOCGIWNAME:
- {
- char *name = &wrq->u.name[0];
- rt_ioctl_giwname(net_dev, NULL, name, NULL);
- break;
- }
- case SIOCGIWESSID: /*Get ESSID */
- {
- struct iw_point *essid = &wrq->u.essid;
- rt_ioctl_giwessid(net_dev, NULL, essid, essid->pointer);
- break;
- }
- case SIOCSIWESSID: /*Set ESSID */
- {
- struct iw_point *essid = &wrq->u.essid;
- rt_ioctl_siwessid(net_dev, NULL, essid, essid->pointer);
- break;
- }
- case SIOCSIWNWID: /* set network id (the cell) */
- case SIOCGIWNWID: /* get network id */
- Status = -EOPNOTSUPP;
- break;
- case SIOCSIWFREQ: /*set channel/frequency (Hz) */
- {
- struct iw_freq *freq = &wrq->u.freq;
- rt_ioctl_siwfreq(net_dev, NULL, freq, NULL);
- break;
- }
- case SIOCGIWFREQ: /* get channel/frequency (Hz) */
- {
- struct iw_freq *freq = &wrq->u.freq;
- rt_ioctl_giwfreq(net_dev, NULL, freq, NULL);
- break;
- }
- case SIOCSIWNICKN: /*set node name/nickname */
- {
- /*struct iw_point *data=&wrq->u.data; */
- /*rt_ioctl_siwnickn(net_dev, NULL, data, NULL); */
- break;
- }
- case SIOCGIWNICKN: /*get node name/nickname */
- {
- struct iw_point *erq = NULL;
- erq = &wrq->u.data;
- erq->length = strlen((char *)pAd->nickname);
- Status =
- copy_to_user(erq->pointer, pAd->nickname,
- erq->length);
- if (Status)
- Status = -EFAULT;
- break;
- }
- case SIOCGIWRATE: /*get default bit rate (bps) */
- rt_ioctl_giwrate(net_dev, NULL, &wrq->u, NULL);
- break;
- case SIOCSIWRATE: /*set default bit rate (bps) */
- rt_ioctl_siwrate(net_dev, NULL, &wrq->u, NULL);
- break;
- case SIOCGIWRTS: /* get RTS/CTS threshold (bytes) */
- {
- struct iw_param *rts = &wrq->u.rts;
- rt_ioctl_giwrts(net_dev, NULL, rts, NULL);
- break;
- }
- case SIOCSIWRTS: /*set RTS/CTS threshold (bytes) */
- {
- struct iw_param *rts = &wrq->u.rts;
- rt_ioctl_siwrts(net_dev, NULL, rts, NULL);
- break;
- }
- case SIOCGIWFRAG: /*get fragmentation thr (bytes) */
- {
- struct iw_param *frag = &wrq->u.frag;
- rt_ioctl_giwfrag(net_dev, NULL, frag, NULL);
- break;
- }
- case SIOCSIWFRAG: /*set fragmentation thr (bytes) */
- {
- struct iw_param *frag = &wrq->u.frag;
- rt_ioctl_siwfrag(net_dev, NULL, frag, NULL);
- break;
- }
- case SIOCGIWENCODE: /*get encoding token & mode */
- {
- struct iw_point *erq = &wrq->u.encoding;
- if (erq)
- rt_ioctl_giwencode(net_dev, NULL, erq,
- erq->pointer);
- break;
- }
- case SIOCSIWENCODE: /*set encoding token & mode */
- {
- struct iw_point *erq = &wrq->u.encoding;
- if (erq)
- rt_ioctl_siwencode(net_dev, NULL, erq,
- erq->pointer);
- break;
- }
- case SIOCGIWAP: /*get access point MAC addresses */
- {
- struct sockaddr *ap_addr = &wrq->u.ap_addr;
- rt_ioctl_giwap(net_dev, NULL, ap_addr,
- ap_addr->sa_data);
- break;
- }
- case SIOCSIWAP: /*set access point MAC addresses */
- {
- struct sockaddr *ap_addr = &wrq->u.ap_addr;
- rt_ioctl_siwap(net_dev, NULL, ap_addr,
- ap_addr->sa_data);
- break;
- }
- case SIOCGIWMODE: /*get operation mode */
- {
- __u32 *mode = &wrq->u.mode;
- rt_ioctl_giwmode(net_dev, NULL, mode, NULL);
- break;
- }
- case SIOCSIWMODE: /*set operation mode */
- {
- __u32 *mode = &wrq->u.mode;
- rt_ioctl_siwmode(net_dev, NULL, mode, NULL);
- break;
- }
- case SIOCGIWSENS: /*get sensitivity (dBm) */
- case SIOCSIWSENS: /*set sensitivity (dBm) */
- case SIOCGIWPOWER: /*get Power Management settings */
- case SIOCSIWPOWER: /*set Power Management settings */
- case SIOCGIWTXPOW: /*get transmit power (dBm) */
- case SIOCSIWTXPOW: /*set transmit power (dBm) */
- case SIOCGIWRANGE: /*Get range of parameters */
- case SIOCGIWRETRY: /*get retry limits and lifetime */
- case SIOCSIWRETRY: /*set retry limits and lifetime */
- case RT_PRIV_IOCTL:
- case RT_PRIV_IOCTL_EXT:
- case RTPRIV_IOCTL_SET:
- case RTPRIV_IOCTL_GSITESURVEY:
- case SIOCGIWPRIV:
- Status = -EOPNOTSUPP;
- break;
- case SIOCETHTOOL:
- break;
- default:
- DBGPRINT(RT_DEBUG_ERROR,
- ("IOCTL::unknown IOCTL's cmd = 0x%08x\n", cmd));
- Status = -EOPNOTSUPP;
- break;
- }
-
- if (StateMachineTouched) /* Upper layer sent a MLME-related operations */
- RTMP_MLME_HANDLER(pAd);
-
- return Status;
-}
-
-/*
- ==========================================================================
- Description:
- Set SSID
- Return:
- TRUE if all parameters are OK, FALSE otherwise
- ==========================================================================
-*/
-int Set_SSID_Proc(struct rt_rtmp_adapter *pAdapter, char *arg)
-{
- struct rt_ndis_802_11_ssid Ssid, *pSsid = NULL;
- BOOLEAN StateMachineTouched = FALSE;
- int success = TRUE;
-
- if (strlen(arg) <= MAX_LEN_OF_SSID) {
- NdisZeroMemory(&Ssid, sizeof(struct rt_ndis_802_11_ssid));
- if (strlen(arg) != 0) {
- NdisMoveMemory(Ssid.Ssid, arg, strlen(arg));
- Ssid.SsidLength = strlen(arg);
- } else /*ANY ssid */
- {
- Ssid.SsidLength = 0;
- memcpy(Ssid.Ssid, "", 0);
- pAdapter->StaCfg.BssType = BSS_INFRA;
- pAdapter->StaCfg.AuthMode = Ndis802_11AuthModeOpen;
- pAdapter->StaCfg.WepStatus =
- Ndis802_11EncryptionDisabled;
- }
- pSsid = &Ssid;
-
- if (pAdapter->Mlme.CntlMachine.CurrState != CNTL_IDLE) {
- RTMP_MLME_RESET_STATE_MACHINE(pAdapter);
- DBGPRINT(RT_DEBUG_TRACE,
- ("MLME busy, reset MLME state machine!\n"));
- }
-
- if ((pAdapter->StaCfg.WpaPassPhraseLen >= 8) &&
- (pAdapter->StaCfg.WpaPassPhraseLen <= 64)) {
- char passphrase_str[65] = { 0 };
- u8 keyMaterial[40];
-
- RTMPMoveMemory(passphrase_str,
- pAdapter->StaCfg.WpaPassPhrase,
- pAdapter->StaCfg.WpaPassPhraseLen);
- RTMPZeroMemory(pAdapter->StaCfg.PMK, 32);
- if (pAdapter->StaCfg.WpaPassPhraseLen == 64) {
- AtoH((char *)pAdapter->StaCfg.WpaPassPhrase,
- pAdapter->StaCfg.PMK, 32);
- } else {
- PasswordHash((char *)pAdapter->StaCfg.
- WpaPassPhrase, Ssid.Ssid,
- Ssid.SsidLength, keyMaterial);
- NdisMoveMemory(pAdapter->StaCfg.PMK,
- keyMaterial, 32);
- }
- }
-
- pAdapter->MlmeAux.CurrReqIsFromNdis = TRUE;
- pAdapter->StaCfg.bScanReqIsFromWebUI = FALSE;
- pAdapter->bConfigChanged = TRUE;
-
- MlmeEnqueue(pAdapter,
- MLME_CNTL_STATE_MACHINE,
- OID_802_11_SSID,
- sizeof(struct rt_ndis_802_11_ssid), (void *) pSsid);
-
- StateMachineTouched = TRUE;
- DBGPRINT(RT_DEBUG_TRACE,
- ("Set_SSID_Proc::(Len=%d,Ssid=%s)\n", Ssid.SsidLength,
- Ssid.Ssid));
- } else
- success = FALSE;
-
- if (StateMachineTouched) /* Upper layer sent a MLME-related operations */
- RTMP_MLME_HANDLER(pAdapter);
-
- return success;
-}
-
-/*
- ==========================================================================
- Description:
- Set Network Type(Infrastructure/Adhoc mode)
- Return:
- TRUE if all parameters are OK, FALSE otherwise
- ==========================================================================
-*/
-int Set_NetworkType_Proc(struct rt_rtmp_adapter *pAdapter, char *arg)
-{
- u32 Value = 0;
-
- if (strcmp(arg, "Adhoc") == 0) {
- if (pAdapter->StaCfg.BssType != BSS_ADHOC) {
- /* Config has changed */
- pAdapter->bConfigChanged = TRUE;
- if (MONITOR_ON(pAdapter)) {
- RTMP_IO_WRITE32(pAdapter, RX_FILTR_CFG,
- STANORMAL);
- RTMP_IO_READ32(pAdapter, MAC_SYS_CTRL, &Value);
- Value &= (~0x80);
- RTMP_IO_WRITE32(pAdapter, MAC_SYS_CTRL, Value);
- OPSTATUS_CLEAR_FLAG(pAdapter,
- fOP_STATUS_MEDIA_STATE_CONNECTED);
- pAdapter->StaCfg.bAutoReconnect = TRUE;
- LinkDown(pAdapter, FALSE);
- }
- if (INFRA_ON(pAdapter)) {
- /*BOOLEAN Cancelled; */
- /* Set the AutoReconnectSsid to prevent it from reconnecting to the old SSID */
- /* Since calling this indicates users don't want to connect to that SSID anymore. */
- pAdapter->MlmeAux.AutoReconnectSsidLen = 32;
- NdisZeroMemory(pAdapter->MlmeAux.
- AutoReconnectSsid,
- pAdapter->MlmeAux.
- AutoReconnectSsidLen);
-
- LinkDown(pAdapter, FALSE);
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("NDIS_STATUS_MEDIA_DISCONNECT Event BB!\n"));
- }
- }
- pAdapter->StaCfg.BssType = BSS_ADHOC;
- pAdapter->net_dev->type = pAdapter->StaCfg.OriDevType;
- DBGPRINT(RT_DEBUG_TRACE,
- ("===>Set_NetworkType_Proc::(AD-HOC)\n"));
- } else if (strcmp(arg, "Infra") == 0) {
- if (pAdapter->StaCfg.BssType != BSS_INFRA) {
- /* Config has changed */
- pAdapter->bConfigChanged = TRUE;
- if (MONITOR_ON(pAdapter)) {
- RTMP_IO_WRITE32(pAdapter, RX_FILTR_CFG,
- STANORMAL);
- RTMP_IO_READ32(pAdapter, MAC_SYS_CTRL, &Value);
- Value &= (~0x80);
- RTMP_IO_WRITE32(pAdapter, MAC_SYS_CTRL, Value);
- OPSTATUS_CLEAR_FLAG(pAdapter,
- fOP_STATUS_MEDIA_STATE_CONNECTED);
- pAdapter->StaCfg.bAutoReconnect = TRUE;
- LinkDown(pAdapter, FALSE);
- }
- if (ADHOC_ON(pAdapter)) {
- /* Set the AutoReconnectSsid to prevent it from reconnecting to the old SSID */
- /* Since calling this indicates users don't want to connect to that SSID anymore. */
- pAdapter->MlmeAux.AutoReconnectSsidLen = 32;
- NdisZeroMemory(pAdapter->MlmeAux.
- AutoReconnectSsid,
- pAdapter->MlmeAux.
- AutoReconnectSsidLen);
-
- LinkDown(pAdapter, FALSE);
- }
- }
- pAdapter->StaCfg.BssType = BSS_INFRA;
- pAdapter->net_dev->type = pAdapter->StaCfg.OriDevType;
- DBGPRINT(RT_DEBUG_TRACE,
- ("===>Set_NetworkType_Proc::(INFRA)\n"));
- } else if (strcmp(arg, "Monitor") == 0) {
- u8 bbpValue = 0;
- BCN_TIME_CFG_STRUC csr;
- OPSTATUS_CLEAR_FLAG(pAdapter, fOP_STATUS_INFRA_ON);
- OPSTATUS_CLEAR_FLAG(pAdapter, fOP_STATUS_ADHOC_ON);
- OPSTATUS_SET_FLAG(pAdapter, fOP_STATUS_MEDIA_STATE_CONNECTED);
- /* disable all periodic state machine */
- pAdapter->StaCfg.bAutoReconnect = FALSE;
- /* reset all mlme state machine */
- RTMP_MLME_RESET_STATE_MACHINE(pAdapter);
- DBGPRINT(RT_DEBUG_TRACE,
- ("fOP_STATUS_MEDIA_STATE_CONNECTED \n"));
- if (pAdapter->CommonCfg.CentralChannel == 0) {
- if (pAdapter->CommonCfg.PhyMode == PHY_11AN_MIXED)
- pAdapter->CommonCfg.CentralChannel = 36;
- else
- pAdapter->CommonCfg.CentralChannel = 6;
- } else
- N_ChannelCheck(pAdapter);
-
- if (pAdapter->CommonCfg.PhyMode >= PHY_11ABGN_MIXED &&
- pAdapter->CommonCfg.RegTransmitSetting.field.BW == BW_40 &&
- pAdapter->CommonCfg.RegTransmitSetting.field.EXTCHA ==
- EXTCHA_ABOVE) {
- /* 40MHz ,control channel at lower */
- RTMP_BBP_IO_READ8_BY_REG_ID(pAdapter, BBP_R4,
- &bbpValue);
- bbpValue &= (~0x18);
- bbpValue |= 0x10;
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAdapter, BBP_R4,
- bbpValue);
- pAdapter->CommonCfg.BBPCurrentBW = BW_40;
- /* RX : control channel at lower */
- RTMP_BBP_IO_READ8_BY_REG_ID(pAdapter, BBP_R3,
- &bbpValue);
- bbpValue &= (~0x20);
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAdapter, BBP_R3,
- bbpValue);
-
- RTMP_IO_READ32(pAdapter, TX_BAND_CFG, &Value);
- Value &= 0xfffffffe;
- RTMP_IO_WRITE32(pAdapter, TX_BAND_CFG, Value);
- pAdapter->CommonCfg.CentralChannel =
- pAdapter->CommonCfg.Channel + 2;
- AsicSwitchChannel(pAdapter,
- pAdapter->CommonCfg.CentralChannel,
- FALSE);
- AsicLockChannel(pAdapter,
- pAdapter->CommonCfg.CentralChannel);
- DBGPRINT(RT_DEBUG_TRACE,
- ("BW_40 ,control_channel(%d), CentralChannel(%d) \n",
- pAdapter->CommonCfg.Channel,
- pAdapter->CommonCfg.CentralChannel));
- } else if (pAdapter->CommonCfg.PhyMode >= PHY_11ABGN_MIXED
- && pAdapter->CommonCfg.RegTransmitSetting.field.BW ==
- BW_40
- && pAdapter->CommonCfg.RegTransmitSetting.field.
- EXTCHA == EXTCHA_BELOW) {
- /* 40MHz ,control channel at upper */
- RTMP_BBP_IO_READ8_BY_REG_ID(pAdapter, BBP_R4,
- &bbpValue);
- bbpValue &= (~0x18);
- bbpValue |= 0x10;
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAdapter, BBP_R4,
- bbpValue);
- pAdapter->CommonCfg.BBPCurrentBW = BW_40;
- RTMP_IO_READ32(pAdapter, TX_BAND_CFG, &Value);
- Value |= 0x1;
- RTMP_IO_WRITE32(pAdapter, TX_BAND_CFG, Value);
-
- RTMP_BBP_IO_READ8_BY_REG_ID(pAdapter, BBP_R3,
- &bbpValue);
- bbpValue |= (0x20);
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAdapter, BBP_R3,
- bbpValue);
- pAdapter->CommonCfg.CentralChannel =
- pAdapter->CommonCfg.Channel - 2;
- AsicSwitchChannel(pAdapter,
- pAdapter->CommonCfg.CentralChannel,
- FALSE);
- AsicLockChannel(pAdapter,
- pAdapter->CommonCfg.CentralChannel);
- DBGPRINT(RT_DEBUG_TRACE,
- ("BW_40 ,control_channel(%d), CentralChannel(%d) \n",
- pAdapter->CommonCfg.Channel,
- pAdapter->CommonCfg.CentralChannel));
- } else {
- /* 20MHz */
- RTMP_BBP_IO_READ8_BY_REG_ID(pAdapter, BBP_R4,
- &bbpValue);
- bbpValue &= (~0x18);
- RTMP_BBP_IO_WRITE8_BY_REG_ID(pAdapter, BBP_R4,
- bbpValue);
- pAdapter->CommonCfg.BBPCurrentBW = BW_20;
- AsicSwitchChannel(pAdapter, pAdapter->CommonCfg.Channel,
- FALSE);
- AsicLockChannel(pAdapter, pAdapter->CommonCfg.Channel);
- DBGPRINT(RT_DEBUG_TRACE,
- ("BW_20, Channel(%d)\n",
- pAdapter->CommonCfg.Channel));
- }
- /* Enable Rx with promiscuous reception */
- RTMP_IO_WRITE32(pAdapter, RX_FILTR_CFG, 0x3);
- /* ASIC supports sniffer function with replacing RSSI with timestamp. */
- /*RTMP_IO_READ32(pAdapter, MAC_SYS_CTRL, &Value); */
- /*Value |= (0x80); */
- /*RTMP_IO_WRITE32(pAdapter, MAC_SYS_CTRL, Value); */
- /* disable sync */
- RTMP_IO_READ32(pAdapter, BCN_TIME_CFG, &csr.word);
- csr.field.bBeaconGen = 0;
- csr.field.bTBTTEnable = 0;
- csr.field.TsfSyncMode = 0;
- RTMP_IO_WRITE32(pAdapter, BCN_TIME_CFG, csr.word);
-
- pAdapter->StaCfg.BssType = BSS_MONITOR;
- pAdapter->net_dev->type = ARPHRD_IEEE80211_PRISM; /*ARPHRD_IEEE80211; // IEEE80211 */
- DBGPRINT(RT_DEBUG_TRACE,
- ("===>Set_NetworkType_Proc::(MONITOR)\n"));
- }
- /* Reset Ralink supplicant to not use, it will be set to start when UI set PMK key */
- pAdapter->StaCfg.WpaState = SS_NOTUSE;
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("Set_NetworkType_Proc::(NetworkType=%d)\n",
- pAdapter->StaCfg.BssType));
-
- return TRUE;
-}
diff --git a/drivers/staging/rt2860/usb_main_dev.c b/drivers/staging/rt2860/usb_main_dev.c
deleted file mode 100644
index 322bf49..0000000
--- a/drivers/staging/rt2860/usb_main_dev.c
+++ /dev/null
@@ -1,927 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************/
-
-#include "rt_config.h"
-
-/* Following information will be show when you run 'modinfo' */
-/* If you have a solution for the bug in current version of driver, please e-mail me. */
-/* Otherwise post to the forum at ralinktech's web site(www.ralinktech.com) and let all users help you. */
-MODULE_AUTHOR("Paul Lin <paul_lin@ralinktech.com>");
-MODULE_DESCRIPTION("RT2870/RT3070 Wireless Lan Linux Driver");
-MODULE_LICENSE("GPL");
-#ifdef MODULE_VERSION
-MODULE_VERSION(STA_DRIVER_VERSION);
-#endif
-
-/* module table */
-struct usb_device_id rtusb_usb_id[] = {
-#ifdef RT2870
- {USB_DEVICE(0x148F, 0x2770)}, /* Ralink */
- {USB_DEVICE(0x148F, 0x2870)}, /* Ralink */
- {USB_DEVICE(0x07B8, 0x2870)}, /* AboCom */
- {USB_DEVICE(0x07B8, 0x2770)}, /* AboCom */
- {USB_DEVICE(0x0DF6, 0x0039)}, /* Sitecom 2770 */
- {USB_DEVICE(0x0DF6, 0x003F)}, /* Sitecom 2770 */
- {USB_DEVICE(0x083A, 0x7512)}, /* Arcadyan 2770 */
- {USB_DEVICE(0x0789, 0x0162)}, /* Logitec 2870 */
- {USB_DEVICE(0x0789, 0x0163)}, /* Logitec 2870 */
- {USB_DEVICE(0x0789, 0x0164)}, /* Logitec 2870 */
- {USB_DEVICE(0x177f, 0x0302)}, /* lsusb */
- {USB_DEVICE(0x0B05, 0x1731)}, /* Asus */
- {USB_DEVICE(0x0B05, 0x1732)}, /* Asus */
- {USB_DEVICE(0x0B05, 0x1742)}, /* Asus */
- {USB_DEVICE(0x0DF6, 0x0017)}, /* Sitecom */
- {USB_DEVICE(0x0DF6, 0x002B)}, /* Sitecom */
- {USB_DEVICE(0x0DF6, 0x002C)}, /* Sitecom */
- {USB_DEVICE(0x0DF6, 0x002D)}, /* Sitecom */
- {USB_DEVICE(0x14B2, 0x3C06)}, /* Conceptronic */
- {USB_DEVICE(0x14B2, 0x3C28)}, /* Conceptronic */
- {USB_DEVICE(0x2019, 0xED06)}, /* Planex Communications, Inc. */
- {USB_DEVICE(0x07D1, 0x3C09)}, /* D-Link */
- {USB_DEVICE(0x07D1, 0x3C11)}, /* D-Link */
- {USB_DEVICE(0x14B2, 0x3C07)}, /* AL */
- {USB_DEVICE(0x050D, 0x8053)}, /* Belkin */
- {USB_DEVICE(0x050D, 0x825B)}, /* Belkin */
- {USB_DEVICE(0x050D, 0x935A)}, /* Belkin F6D4050 v1 */
- {USB_DEVICE(0x050D, 0x935B)}, /* Belkin F6D4050 v2 */
- {USB_DEVICE(0x14B2, 0x3C23)}, /* Airlink */
- {USB_DEVICE(0x14B2, 0x3C27)}, /* Airlink */
- {USB_DEVICE(0x07AA, 0x002F)}, /* Corega */
- {USB_DEVICE(0x07AA, 0x003C)}, /* Corega */
- {USB_DEVICE(0x07AA, 0x003F)}, /* Corega */
- {USB_DEVICE(0x1044, 0x800B)}, /* Gigabyte */
- {USB_DEVICE(0x15A9, 0x0006)}, /* Sparklan */
- {USB_DEVICE(0x083A, 0xB522)}, /* SMC */
- {USB_DEVICE(0x083A, 0xA618)}, /* SMC */
- {USB_DEVICE(0x083A, 0x8522)}, /* Arcadyan */
- {USB_DEVICE(0x083A, 0x7522)}, /* Arcadyan */
- {USB_DEVICE(0x0CDE, 0x0022)}, /* ZCOM */
- {USB_DEVICE(0x0586, 0x3416)}, /* Zyxel */
- {USB_DEVICE(0x0586, 0x341a)}, /* Zyxel NWD-270N */
- {USB_DEVICE(0x0CDE, 0x0025)}, /* Zyxel */
- {USB_DEVICE(0x1740, 0x9701)}, /* EnGenius */
- {USB_DEVICE(0x1740, 0x9702)}, /* EnGenius */
- {USB_DEVICE(0x0471, 0x200f)}, /* Philips */
- {USB_DEVICE(0x14B2, 0x3C25)}, /* Draytek */
- {USB_DEVICE(0x13D3, 0x3247)}, /* AzureWave */
- {USB_DEVICE(0x083A, 0x6618)}, /* Accton */
- {USB_DEVICE(0x15c5, 0x0008)}, /* Amit */
- {USB_DEVICE(0x0E66, 0x0001)}, /* Hawking */
- {USB_DEVICE(0x0E66, 0x0003)}, /* Hawking */
- {USB_DEVICE(0x129B, 0x1828)}, /* Siemens */
- {USB_DEVICE(0x157E, 0x300E)}, /* U-Media */
- {USB_DEVICE(0x050d, 0x805c)},
- {USB_DEVICE(0x050d, 0x815c)},
- {USB_DEVICE(0x1482, 0x3C09)}, /* Abocom */
- {USB_DEVICE(0x14B2, 0x3C09)}, /* Alpha */
- {USB_DEVICE(0x04E8, 0x2018)}, /* samsung linkstick2 */
- {USB_DEVICE(0x1690, 0x0740)}, /* Askey */
- {USB_DEVICE(0x5A57, 0x0280)}, /* Zinwell */
- {USB_DEVICE(0x5A57, 0x0282)}, /* Zinwell */
- {USB_DEVICE(0x7392, 0x7718)},
- {USB_DEVICE(0x7392, 0x7717)},
- {USB_DEVICE(0x0411, 0x016f)}, /* MelCo.,Inc. WLI-UC-G301N */
- {USB_DEVICE(0x1737, 0x0070)}, /* Linksys WUSB100 */
- {USB_DEVICE(0x1737, 0x0071)}, /* Linksys WUSB600N */
- {USB_DEVICE(0x1737, 0x0078)}, /* Linksys WUSB100v2 */
- {USB_DEVICE(0x0411, 0x00e8)}, /* Buffalo WLI-UC-G300N */
- {USB_DEVICE(0x050d, 0x815c)}, /* Belkin F5D8053 */
- {USB_DEVICE(0x100D, 0x9031)}, /* Motorola 2770 */
-#endif /* RT2870 // */
-#ifdef RT3070
- {USB_DEVICE(0x148F, 0x3070)}, /* Ralink 3070 */
- {USB_DEVICE(0x148F, 0x3071)}, /* Ralink 3071 */
- {USB_DEVICE(0x148F, 0x3072)}, /* Ralink 3072 */
- {USB_DEVICE(0x0DB0, 0x3820)}, /* Ralink 3070 */
- {USB_DEVICE(0x0DB0, 0x871C)}, /* Ralink 3070 */
- {USB_DEVICE(0x0DB0, 0x822C)}, /* Ralink 3070 */
- {USB_DEVICE(0x0DB0, 0x871B)}, /* Ralink 3070 */
- {USB_DEVICE(0x0DB0, 0x822B)}, /* Ralink 3070 */
- {USB_DEVICE(0x0DF6, 0x003E)}, /* Sitecom 3070 */
- {USB_DEVICE(0x0DF6, 0x0042)}, /* Sitecom 3072 */
- {USB_DEVICE(0x0DF6, 0x0048)}, /* Sitecom 3070 */
- {USB_DEVICE(0x0DF6, 0x0047)}, /* Sitecom 3071 */
- {USB_DEVICE(0x14B2, 0x3C12)}, /* AL 3070 */
- {USB_DEVICE(0x18C5, 0x0012)}, /* Corega 3070 */
- {USB_DEVICE(0x083A, 0x7511)}, /* Arcadyan 3070 */
- {USB_DEVICE(0x083A, 0xA701)}, /* SMC 3070 */
- {USB_DEVICE(0x083A, 0xA702)}, /* SMC 3072 */
- {USB_DEVICE(0x1740, 0x9703)}, /* EnGenius 3070 */
- {USB_DEVICE(0x1740, 0x9705)}, /* EnGenius 3071 */
- {USB_DEVICE(0x1740, 0x9706)}, /* EnGenius 3072 */
- {USB_DEVICE(0x1740, 0x9707)}, /* EnGenius 3070 */
- {USB_DEVICE(0x1740, 0x9708)}, /* EnGenius 3071 */
- {USB_DEVICE(0x1740, 0x9709)}, /* EnGenius 3072 */
- {USB_DEVICE(0x13D3, 0x3273)}, /* AzureWave 3070 */
- {USB_DEVICE(0x13D3, 0x3305)}, /* AzureWave 3070*/
- {USB_DEVICE(0x1044, 0x800D)}, /* Gigabyte GN-WB32L 3070 */
- {USB_DEVICE(0x2019, 0xAB25)}, /* Planex Communications, Inc. RT3070 */
- {USB_DEVICE(0x07B8, 0x3070)}, /* AboCom 3070 */
- {USB_DEVICE(0x07B8, 0x3071)}, /* AboCom 3071 */
- {USB_DEVICE(0x07B8, 0x3072)}, /* Abocom 3072 */
- {USB_DEVICE(0x7392, 0x7711)}, /* Edimax 3070 */
- {USB_DEVICE(0x1A32, 0x0304)}, /* Quanta 3070 */
- {USB_DEVICE(0x1EDA, 0x2310)}, /* AirTies 3070 */
- {USB_DEVICE(0x07D1, 0x3C0A)}, /* D-Link 3072 */
- {USB_DEVICE(0x07D1, 0x3C0D)}, /* D-Link 3070 */
- {USB_DEVICE(0x07D1, 0x3C0E)}, /* D-Link 3070 */
- {USB_DEVICE(0x07D1, 0x3C0F)}, /* D-Link 3070 */
- {USB_DEVICE(0x07D1, 0x3C16)}, /* D-Link 3070 */
- {USB_DEVICE(0x07D1, 0x3C17)}, /* D-Link 8070 */
- {USB_DEVICE(0x1D4D, 0x000C)}, /* Pegatron Corporation 3070 */
- {USB_DEVICE(0x1D4D, 0x000E)}, /* Pegatron Corporation 3070 */
- {USB_DEVICE(0x5A57, 0x5257)}, /* Zinwell 3070 */
- {USB_DEVICE(0x5A57, 0x0283)}, /* Zinwell 3072 */
- {USB_DEVICE(0x04BB, 0x0945)}, /* I-O DATA 3072 */
- {USB_DEVICE(0x04BB, 0x0947)}, /* I-O DATA 3070 */
- {USB_DEVICE(0x04BB, 0x0948)}, /* I-O DATA 3072 */
- {USB_DEVICE(0x203D, 0x1480)}, /* Encore 3070 */
- {USB_DEVICE(0x20B8, 0x8888)}, /* PARA INDUSTRIAL 3070 */
- {USB_DEVICE(0x0B05, 0x1784)}, /* Asus 3072 */
- {USB_DEVICE(0x203D, 0x14A9)}, /* Encore 3070*/
- {USB_DEVICE(0x0DB0, 0x899A)}, /* MSI 3070*/
- {USB_DEVICE(0x0DB0, 0x3870)}, /* MSI 3070*/
- {USB_DEVICE(0x0DB0, 0x870A)}, /* MSI 3070*/
- {USB_DEVICE(0x0DB0, 0x6899)}, /* MSI 3070 */
- {USB_DEVICE(0x0DB0, 0x3822)}, /* MSI 3070 */
- {USB_DEVICE(0x0DB0, 0x3871)}, /* MSI 3070 */
- {USB_DEVICE(0x0DB0, 0x871A)}, /* MSI 3070 */
- {USB_DEVICE(0x0DB0, 0x822A)}, /* MSI 3070 */
- {USB_DEVICE(0x0DB0, 0x3821)}, /* Ralink 3070 */
- {USB_DEVICE(0x0DB0, 0x821A)}, /* Ralink 3070 */
- {USB_DEVICE(0x083A, 0xA703)}, /* IO-MAGIC */
- {USB_DEVICE(0x13D3, 0x3307)}, /* Azurewave */
- {USB_DEVICE(0x13D3, 0x3321)}, /* Azurewave */
- {USB_DEVICE(0x07FA, 0x7712)}, /* Edimax */
- {USB_DEVICE(0x0789, 0x0166)}, /* Edimax */
- {USB_DEVICE(0x148F, 0x2070)}, /* Edimax */
-#endif /* RT3070 // */
- {USB_DEVICE(0x1737, 0x0077)}, /* Linksys WUSB54GC-EU v3 */
- {USB_DEVICE(0x2001, 0x3C09)}, /* D-Link */
- {USB_DEVICE(0x2001, 0x3C0A)}, /* D-Link 3072 */
- {USB_DEVICE(0x2019, 0xED14)}, /* Planex Communications, Inc. */
- {USB_DEVICE(0x0411, 0x015D)}, /* Buffalo Airstation WLI-UC-GN */
- {} /* Terminating entry */
-};
-
-int const rtusb_usb_id_len =
- sizeof(rtusb_usb_id) / sizeof(struct usb_device_id);
-
-MODULE_DEVICE_TABLE(usb, rtusb_usb_id);
-
-static void rt2870_disconnect(struct usb_device *dev, struct rt_rtmp_adapter *pAd);
-
-static int __devinit rt2870_probe(IN struct usb_interface *intf,
- IN struct usb_device *usb_dev,
- IN const struct usb_device_id *dev_id,
- struct rt_rtmp_adapter **ppAd);
-
-#ifndef PF_NOFREEZE
-#define PF_NOFREEZE 0
-#endif
-
-extern int rt28xx_close(IN struct net_device *net_dev);
-extern int rt28xx_open(struct net_device *net_dev);
-
-static BOOLEAN USBDevConfigInit(IN struct usb_device *dev,
- IN struct usb_interface *intf,
- struct rt_rtmp_adapter *pAd);
-
-/*
-========================================================================
-Routine Description:
- Check the chipset vendor/product ID.
-
-Arguments:
- _dev_p Point to the PCI or USB device
-
-Return Value:
- TRUE Check ok
- FALSE Check fail
-
-Note:
-========================================================================
-*/
-BOOLEAN RT28XXChipsetCheck(IN void *_dev_p)
-{
- struct usb_interface *intf = (struct usb_interface *)_dev_p;
- struct usb_device *dev_p = interface_to_usbdev(intf);
- u32 i;
-
- for (i = 0; i < rtusb_usb_id_len; i++) {
- if (dev_p->descriptor.idVendor == rtusb_usb_id[i].idVendor &&
- dev_p->descriptor.idProduct == rtusb_usb_id[i].idProduct) {
- printk(KERN_INFO "rt2870: idVendor = 0x%x, idProduct = 0x%x\n",
- dev_p->descriptor.idVendor,
- dev_p->descriptor.idProduct);
- break;
- }
- }
-
- if (i == rtusb_usb_id_len) {
- printk(KERN_ERR "rt2870: Error! Device Descriptor not matching!\n");
- return FALSE;
- }
-
- return TRUE;
-}
-
-/**************************************************************************/
-/**************************************************************************/
-/*tested for kernel 2.6series */
-/**************************************************************************/
-/**************************************************************************/
-
-#ifdef CONFIG_PM
-static int rt2870_suspend(struct usb_interface *intf, pm_message_t state);
-static int rt2870_resume(struct usb_interface *intf);
-#endif /* CONFIG_PM // */
-
-static BOOLEAN USBDevConfigInit(IN struct usb_device *dev,
- IN struct usb_interface *intf,
- struct rt_rtmp_adapter *pAd)
-{
- struct usb_host_interface *iface_desc;
- unsigned long BulkOutIdx;
- u32 i;
-
- /* get the active interface descriptor */
- iface_desc = intf->cur_altsetting;
-
- /* get # of enpoints */
- pAd->NumberOfPipes = iface_desc->desc.bNumEndpoints;
- DBGPRINT(RT_DEBUG_TRACE,
- ("NumEndpoints=%d\n", iface_desc->desc.bNumEndpoints));
-
- /* Configure Pipes */
- BulkOutIdx = 0;
-
- for (i = 0; i < pAd->NumberOfPipes; i++) {
- if ((iface_desc->endpoint[i].desc.bmAttributes ==
- USB_ENDPOINT_XFER_BULK) &&
- ((iface_desc->endpoint[i].desc.bEndpointAddress &
- USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)) {
- pAd->BulkInEpAddr =
- iface_desc->endpoint[i].desc.bEndpointAddress;
- pAd->BulkInMaxPacketSize =
- le2cpu16(iface_desc->endpoint[i].desc.
- wMaxPacketSize);
-
- DBGPRINT_RAW(RT_DEBUG_TRACE,
- ("BULK IN MaxPacketSize = %d\n",
- pAd->BulkInMaxPacketSize));
- DBGPRINT_RAW(RT_DEBUG_TRACE,
- ("EP address = 0x%2x\n",
- iface_desc->endpoint[i].desc.
- bEndpointAddress));
- } else
- if ((iface_desc->endpoint[i].desc.bmAttributes ==
- USB_ENDPOINT_XFER_BULK)
- &&
- ((iface_desc->endpoint[i].desc.
- bEndpointAddress & USB_ENDPOINT_DIR_MASK) ==
- USB_DIR_OUT)) {
- /* there are 6 bulk out EP. EP6 highest priority. */
- /* EP1-4 is EDCA. EP5 is HCCA. */
- pAd->BulkOutEpAddr[BulkOutIdx++] =
- iface_desc->endpoint[i].desc.bEndpointAddress;
- pAd->BulkOutMaxPacketSize =
- le2cpu16(iface_desc->endpoint[i].desc.
- wMaxPacketSize);
-
- DBGPRINT_RAW(RT_DEBUG_TRACE,
- ("BULK OUT MaxPacketSize = %d\n",
- pAd->BulkOutMaxPacketSize));
- DBGPRINT_RAW(RT_DEBUG_TRACE,
- ("EP address = 0x%2x \n",
- iface_desc->endpoint[i].desc.
- bEndpointAddress));
- }
- }
-
- if (!(pAd->BulkInEpAddr && pAd->BulkOutEpAddr[0])) {
- printk
- (KERN_ERR "%s: Could not find both bulk-in and bulk-out endpoints\n",
- __FUNCTION__);
- return FALSE;
- }
-
- pAd->config = &dev->config->desc;
- usb_set_intfdata(intf, pAd);
-
- return TRUE;
-
-}
-
-static int __devinit rtusb_probe(struct usb_interface *intf,
- const struct usb_device_id *id)
-{
- struct rt_rtmp_adapter *pAd;
- struct usb_device *dev;
- int rv;
-
- dev = interface_to_usbdev(intf);
- dev = usb_get_dev(dev);
-
- rv = rt2870_probe(intf, dev, id, &pAd);
- if (rv != 0)
- usb_put_dev(dev);
-
- return rv;
-}
-
-static void rtusb_disconnect(struct usb_interface *intf)
-{
- struct usb_device *dev = interface_to_usbdev(intf);
- struct rt_rtmp_adapter *pAd;
-
- pAd = usb_get_intfdata(intf);
- usb_set_intfdata(intf, NULL);
-
- rt2870_disconnect(dev, pAd);
-}
-
-struct usb_driver rtusb_driver = {
- .name = "rt2870",
- .probe = rtusb_probe,
- .disconnect = rtusb_disconnect,
- .id_table = rtusb_usb_id,
-
-#ifdef CONFIG_PM
-suspend:rt2870_suspend,
-resume:rt2870_resume,
-#endif
-};
-
-#ifdef CONFIG_PM
-
-void RT2870RejectPendingPackets(struct rt_rtmp_adapter *pAd)
-{
- /* clear PS packets */
- /* clear TxSw packets */
-}
-
-static int rt2870_suspend(struct usb_interface *intf, pm_message_t state)
-{
- struct net_device *net_dev;
- struct rt_rtmp_adapter *pAd = usb_get_intfdata(intf);
-
- DBGPRINT(RT_DEBUG_TRACE, ("===> rt2870_suspend()\n"));
- net_dev = pAd->net_dev;
- netif_device_detach(net_dev);
-
- pAd->PM_FlgSuspend = 1;
- if (netif_running(net_dev)) {
- RTUSBCancelPendingBulkInIRP(pAd);
- RTUSBCancelPendingBulkOutIRP(pAd);
- }
- DBGPRINT(RT_DEBUG_TRACE, ("<=== rt2870_suspend()\n"));
- return 0;
-}
-
-static int rt2870_resume(struct usb_interface *intf)
-{
- struct net_device *net_dev;
- struct rt_rtmp_adapter *pAd = usb_get_intfdata(intf);
-
- DBGPRINT(RT_DEBUG_TRACE, ("===> rt2870_resume()\n"));
-
- pAd->PM_FlgSuspend = 0;
- net_dev = pAd->net_dev;
- netif_device_attach(net_dev);
- netif_start_queue(net_dev);
- netif_carrier_on(net_dev);
- netif_wake_queue(net_dev);
-
- DBGPRINT(RT_DEBUG_TRACE, ("<=== rt2870_resume()\n"));
- return 0;
-}
-#endif /* CONFIG_PM // */
-
-/* Init driver module */
-int __init rtusb_init(void)
-{
- printk(KERN_DEBUG "rtusb init --->\n");
- return usb_register(&rtusb_driver);
-}
-
-/* Deinit driver module */
-void __exit rtusb_exit(void)
-{
- usb_deregister(&rtusb_driver);
- printk(KERN_DEBUG "<--- rtusb exit\n");
-}
-
-module_init(rtusb_init);
-module_exit(rtusb_exit);
-
-/*--------------------------------------------------------------------- */
-/* function declarations */
-/*--------------------------------------------------------------------- */
-
-/*
-========================================================================
-Routine Description:
- MLME kernel thread.
-
-Arguments:
- *Context the pAd, driver control block pointer
-
-Return Value:
- 0 close the thread
-
-Note:
-========================================================================
-*/
-int MlmeThread(IN void *Context)
-{
- struct rt_rtmp_adapter *pAd;
- struct rt_rtmp_os_task *pTask;
- int status;
- status = 0;
-
- pTask = Context;
- pAd = pTask->priv;
-
- RtmpOSTaskCustomize(pTask);
-
- while (!pTask->task_killed) {
-#ifdef KTHREAD_SUPPORT
- RTMP_WAIT_EVENT_INTERRUPTIBLE(pAd, pTask);
-#else
- RTMP_SEM_EVENT_WAIT(&(pTask->taskSema), status);
-
- /* unlock the device pointers */
- if (status != 0) {
- RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS);
- break;
- }
-#endif
-
- /* lock the device pointers , need to check if required */
- /*down(&(pAd->usbdev_semaphore)); */
-
- if (!pAd->PM_FlgSuspend)
- MlmeHandler(pAd);
- }
-
- /* notify the exit routine that we're actually exiting now
- *
- * complete()/wait_for_completion() is similar to up()/down(),
- * except that complete() is safe in the case where the structure
- * is getting deleted in a parallel mode of execution (i.e. just
- * after the down() -- that's necessary for the thread-shutdown
- * case.
- *
- * complete_and_exit() goes even further than this -- it is safe in
- * the case that the thread of the caller is going away (not just
- * the structure) -- this is necessary for the module-remove case.
- * This is important in preemption kernels, which transfer the flow
- * of execution immediately upon a complete().
- */
- DBGPRINT(RT_DEBUG_TRACE, ("<---%s\n", __FUNCTION__));
-#ifndef KTHREAD_SUPPORT
- pTask->taskPID = THREAD_PID_INIT_VALUE;
- complete_and_exit(&pTask->taskComplete, 0);
-#endif
- return 0;
-
-}
-
-/*
-========================================================================
-Routine Description:
- USB command kernel thread.
-
-Arguments:
- *Context the pAd, driver control block pointer
-
-Return Value:
- 0 close the thread
-
-Note:
-========================================================================
-*/
-int RTUSBCmdThread(IN void *Context)
-{
- struct rt_rtmp_adapter *pAd;
- struct rt_rtmp_os_task *pTask;
- int status;
- status = 0;
-
- pTask = Context;
- pAd = pTask->priv;
-
- RtmpOSTaskCustomize(pTask);
-
- NdisAcquireSpinLock(&pAd->CmdQLock);
- pAd->CmdQ.CmdQState = RTMP_TASK_STAT_RUNNING;
- NdisReleaseSpinLock(&pAd->CmdQLock);
-
- while (pAd && pAd->CmdQ.CmdQState == RTMP_TASK_STAT_RUNNING) {
-#ifdef KTHREAD_SUPPORT
- RTMP_WAIT_EVENT_INTERRUPTIBLE(pAd, pTask);
-#else
- /* lock the device pointers */
- RTMP_SEM_EVENT_WAIT(&(pTask->taskSema), status);
-
- if (status != 0) {
- RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS);
- break;
- }
-#endif
-
- if (pAd->CmdQ.CmdQState == RTMP_TASK_STAT_STOPED)
- break;
-
- if (!pAd->PM_FlgSuspend)
- CMDHandler(pAd);
- }
-
- if (pAd && !pAd->PM_FlgSuspend) { /* Clear the CmdQElements. */
- struct rt_cmdqelmt *pCmdQElmt = NULL;
-
- NdisAcquireSpinLock(&pAd->CmdQLock);
- pAd->CmdQ.CmdQState = RTMP_TASK_STAT_STOPED;
- while (pAd->CmdQ.size) {
- RTUSBDequeueCmd(&pAd->CmdQ, &pCmdQElmt);
- if (pCmdQElmt) {
- if (pCmdQElmt->CmdFromNdis == TRUE) {
- if (pCmdQElmt->buffer != NULL)
- os_free_mem(pAd,
- pCmdQElmt->buffer);
- os_free_mem(pAd, (u8 *)pCmdQElmt);
- } else {
- if ((pCmdQElmt->buffer != NULL)
- && (pCmdQElmt->bufferlength != 0))
- os_free_mem(pAd,
- pCmdQElmt->buffer);
- os_free_mem(pAd, (u8 *)pCmdQElmt);
- }
- }
- }
-
- NdisReleaseSpinLock(&pAd->CmdQLock);
- }
- /* notify the exit routine that we're actually exiting now
- *
- * complete()/wait_for_completion() is similar to up()/down(),
- * except that complete() is safe in the case where the structure
- * is getting deleted in a parallel mode of execution (i.e. just
- * after the down() -- that's necessary for the thread-shutdown
- * case.
- *
- * complete_and_exit() goes even further than this -- it is safe in
- * the case that the thread of the caller is going away (not just
- * the structure) -- this is necessary for the module-remove case.
- * This is important in preemption kernels, which transfer the flow
- * of execution immediately upon a complete().
- */
- DBGPRINT(RT_DEBUG_TRACE, ("<---RTUSBCmdThread\n"));
-
-#ifndef KTHREAD_SUPPORT
- pTask->taskPID = THREAD_PID_INIT_VALUE;
- complete_and_exit(&pTask->taskComplete, 0);
-#endif
- return 0;
-
-}
-
-void RTUSBWatchDog(struct rt_rtmp_adapter *pAd)
-{
- struct rt_ht_tx_context *pHTTXContext;
- int idx;
- unsigned long irqFlags;
- PURB pUrb;
- BOOLEAN needDumpSeq = FALSE;
- u32 MACValue;
- u32 TxRxQ_Pcnt;
-
- idx = 0;
- RTMP_IO_READ32(pAd, TXRXQ_PCNT, &MACValue);
- if ((MACValue & 0xff) != 0) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("TX QUEUE 0 Not EMPTY(Value=0x%0x)!\n",
- MACValue));
- RTMP_IO_WRITE32(pAd, PBF_CFG, 0xf40012);
- while ((MACValue & 0xff) != 0 && (idx++ < 10)) {
- RTMP_IO_READ32(pAd, TXRXQ_PCNT, &MACValue);
- RTMPusecDelay(1);
- }
- RTMP_IO_WRITE32(pAd, PBF_CFG, 0xf40006);
- }
-
- if (pAd->watchDogRxOverFlowCnt >= 2) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("Maybe the Rx Bulk-In hanged! Cancel the pending Rx bulks request!\n"));
- if ((!RTMP_TEST_FLAG
- (pAd,
- (fRTMP_ADAPTER_RESET_IN_PROGRESS |
- fRTMP_ADAPTER_BULKIN_RESET |
- fRTMP_ADAPTER_HALT_IN_PROGRESS |
- fRTMP_ADAPTER_NIC_NOT_EXIST)))) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("Call CMDTHREAD_RESET_BULK_IN to cancel the pending Rx Bulk!\n"));
- RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_BULKIN_RESET);
- RTUSBEnqueueInternalCmd(pAd, CMDTHREAD_RESET_BULK_IN,
- NULL, 0);
- needDumpSeq = TRUE;
- }
- pAd->watchDogRxOverFlowCnt = 0;
- }
-
- RTUSBReadMACRegister(pAd, 0x438, &TxRxQ_Pcnt);
-
- for (idx = 0; idx < NUM_OF_TX_RING; idx++) {
- pUrb = NULL;
-
- RTMP_IRQ_LOCK(&pAd->BulkOutLock[idx], irqFlags);
- if ((pAd->BulkOutPending[idx] == TRUE)
- && pAd->watchDogTxPendingCnt) {
- int actual_length = 0, transfer_buffer_length = 0;
- BOOLEAN isDataPacket = FALSE;
- pAd->watchDogTxPendingCnt[idx]++;
-
- if ((pAd->watchDogTxPendingCnt[idx] > 2) &&
- (!RTMP_TEST_FLAG
- (pAd,
- (fRTMP_ADAPTER_RESET_IN_PROGRESS |
- fRTMP_ADAPTER_HALT_IN_PROGRESS |
- fRTMP_ADAPTER_NIC_NOT_EXIST |
- fRTMP_ADAPTER_BULKOUT_RESET)))
- ) {
- /* FIXME: Following code just support single bulk out. If you wanna support multiple bulk out. Modify it! */
- pHTTXContext =
- (struct rt_ht_tx_context *)(&pAd->TxContext[idx]);
- if (pHTTXContext->IRPPending) { /* Check TxContext. */
- pUrb = pHTTXContext->pUrb;
-
- actual_length = pUrb->actual_length;
- transfer_buffer_length =
- pUrb->transfer_buffer_length;
- isDataPacket = TRUE;
- } else if (idx == MGMTPIPEIDX) {
- struct rt_tx_context *pMLMEContext, *pNULLContext,
- *pPsPollContext;
-
- /*Check MgmtContext. */
- pMLMEContext =
- (struct rt_tx_context *)(pAd->MgmtRing.
- Cell[pAd->MgmtRing.
- TxDmaIdx].
- AllocVa);
- pPsPollContext =
- (struct rt_tx_context *)(&pAd->PsPollContext);
- pNULLContext =
- (struct rt_tx_context *)(&pAd->NullContext);
-
- if (pMLMEContext->IRPPending) {
- ASSERT(pMLMEContext->
- IRPPending);
- pUrb = pMLMEContext->pUrb;
- } else if (pNULLContext->IRPPending) {
- ASSERT(pNULLContext->
- IRPPending);
- pUrb = pNULLContext->pUrb;
- } else if (pPsPollContext->IRPPending) {
- ASSERT(pPsPollContext->
- IRPPending);
- pUrb = pPsPollContext->pUrb;
- }
- }
-
- RTMP_IRQ_UNLOCK(&pAd->BulkOutLock[idx],
- irqFlags);
-
- printk(KERN_INFO "%d:%lu LTL=%d , TL=%d L:%d\n",
- idx, pAd->watchDogTxPendingCnt[idx],
- pAd->TransferedLength[idx],
- actual_length, transfer_buffer_length);
-
- if (pUrb) {
- if ((isDataPacket
- && pAd->TransferedLength[idx] ==
- actual_length
- && pAd->TransferedLength[idx] <
- transfer_buffer_length
- && actual_length != 0
-/* && TxRxQ_Pcnt==0 */
- && pAd->watchDogTxPendingCnt[idx] >
- 3)
- || isDataPacket == FALSE
- || pAd->watchDogTxPendingCnt[idx] >
- 6) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("Maybe the Tx Bulk-Out hanged! Cancel the pending Tx bulks request of idx(%d)!\n",
- idx));
- DBGPRINT(RT_DEBUG_TRACE,
- ("Unlink the pending URB!\n"));
- /* unlink it now */
- RTUSB_UNLINK_URB(pUrb);
- /* Sleep 200 microseconds to give cancellation time to work */
- /*RTMPusecDelay(200); */
- needDumpSeq = TRUE;
- }
- } else {
- DBGPRINT(RT_DEBUG_ERROR,
- ("Unknown bulkOut URB maybe hanged!\n"));
- }
- } else {
- RTMP_IRQ_UNLOCK(&pAd->BulkOutLock[idx],
- irqFlags);
- }
-
- if (isDataPacket == TRUE)
- pAd->TransferedLength[idx] = actual_length;
- } else {
- RTMP_IRQ_UNLOCK(&pAd->BulkOutLock[idx], irqFlags);
- }
- }
-
- /* For Sigma debug, dump the ba_reordering sequence. */
- if ((needDumpSeq == TRUE) && (pAd->CommonCfg.bDisableReordering == 0)) {
- u16 Idx;
- struct rt_ba_rec_entry *pBAEntry = NULL;
- u8 count = 0;
- struct reordering_mpdu *mpdu_blk;
-
- Idx = pAd->MacTab.Content[BSSID_WCID].BARecWcidArray[0];
-
- pBAEntry = &pAd->BATable.BARecEntry[Idx];
- if ((pBAEntry->list.qlen > 0) && (pBAEntry->list.next != NULL)) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("NICUpdateRawCounters():The Queueing pkt in reordering buffer:\n"));
- NdisAcquireSpinLock(&pBAEntry->RxReRingLock);
- mpdu_blk = pBAEntry->list.next;
- while (mpdu_blk) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("\t%d:Seq-%d, bAMSDU-%d!\n", count,
- mpdu_blk->Sequence,
- mpdu_blk->bAMSDU));
- mpdu_blk = mpdu_blk->next;
- count++;
- }
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("\npBAEntry->LastIndSeq=%d!\n",
- pBAEntry->LastIndSeq));
- NdisReleaseSpinLock(&pBAEntry->RxReRingLock);
- }
- }
-}
-
-/*
-========================================================================
-Routine Description:
- Release allocated resources.
-
-Arguments:
- *dev Point to the PCI or USB device
- pAd driver control block pointer
-
-Return Value:
- None
-
-Note:
-========================================================================
-*/
-static void rt2870_disconnect(struct usb_device *dev, struct rt_rtmp_adapter *pAd)
-{
- DBGPRINT(RT_DEBUG_ERROR,
- ("rtusb_disconnect: unregister usbnet usb-%s-%s\n",
- dev->bus->bus_name, dev->devpath));
- if (!pAd) {
- usb_put_dev(dev);
- printk(KERN_ERR "rtusb_disconnect: pAd == NULL!\n");
- return;
- }
- RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST);
-
- /* for debug, wait to show some messages to /proc system */
- udelay(1);
-
- RtmpPhyNetDevExit(pAd, pAd->net_dev);
-
- /* FIXME: Shall we need following delay and flush the schedule?? */
- udelay(1);
- flush_scheduled_work();
- udelay(1);
-
- /* free the root net_device */
- RtmpOSNetDevFree(pAd->net_dev);
-
- RtmpRaDevCtrlExit(pAd);
-
- /* release a use of the usb device structure */
- usb_put_dev(dev);
- udelay(1);
-
- DBGPRINT(RT_DEBUG_ERROR, (" RTUSB disconnect successfully\n"));
-}
-
-static int __devinit rt2870_probe(IN struct usb_interface *intf,
- IN struct usb_device *usb_dev,
- IN const struct usb_device_id *dev_id,
- struct rt_rtmp_adapter **ppAd)
-{
- struct net_device *net_dev = NULL;
- struct rt_rtmp_adapter *pAd = (struct rt_rtmp_adapter *)NULL;
- int status, rv;
- void *handle;
- struct rt_rtmp_os_netdev_op_hook netDevHook;
-
- DBGPRINT(RT_DEBUG_TRACE, ("===>rt2870_probe()!\n"));
-
- /* Check chipset vendor/product ID */
- /*if (RT28XXChipsetCheck(_dev_p) == FALSE) */
- /* goto err_out; */
-
-/*RtmpDevInit============================================= */
- /* Allocate struct rt_rtmp_adapter adapter structure */
- handle = kmalloc(sizeof(struct os_cookie), GFP_KERNEL);
- if (handle == NULL) {
- printk
- ("rt2870_probe(): Allocate memory for os handle failed!\n");
- return -ENOMEM;
- }
- ((struct os_cookie *)handle)->pUsb_Dev = usb_dev;
-
- rv = RTMPAllocAdapterBlock(handle, &pAd);
- if (rv != NDIS_STATUS_SUCCESS) {
- kfree(handle);
- goto err_out;
- }
-/*USBDevInit============================================== */
- if (USBDevConfigInit(usb_dev, intf, pAd) == FALSE)
- goto err_out_free_radev;
-
- RtmpRaDevCtrlInit(pAd, RTMP_DEV_INF_USB);
-
-/*NetDevInit============================================== */
- net_dev = RtmpPhyNetDevInit(pAd, &netDevHook);
- if (net_dev == NULL)
- goto err_out_free_radev;
-
- /* Here are the net_device structure with usb specific parameters.
- * for supporting Network Manager.
- * Set the sysfs physical device reference for the network logical device if set prior to registration will
- * cause a symlink during initialization.
- */
- SET_NETDEV_DEV(net_dev, &(usb_dev->dev));
-
- pAd->StaCfg.OriDevType = net_dev->type;
-
-/*All done, it's time to register the net device to linux kernel. */
- /* Register this device */
- status = RtmpOSNetDevAttach(net_dev, &netDevHook);
- if (status != 0)
- goto err_out_free_netdev;
-
-#ifdef KTHREAD_SUPPORT
- init_waitqueue_head(&pAd->mlmeTask.kthread_q);
- init_waitqueue_head(&pAd->timerTask.kthread_q);
- init_waitqueue_head(&pAd->cmdQTask.kthread_q);
-#endif
-
- *ppAd = pAd;
-
- DBGPRINT(RT_DEBUG_TRACE, ("<===rt2870_probe()!\n"));
-
- return 0;
-
- /* --------------------------- ERROR HANDLE --------------------------- */
-err_out_free_netdev:
- RtmpOSNetDevFree(net_dev);
-
-err_out_free_radev:
- RTMPFreeAdapter(pAd);
-
-err_out:
- *ppAd = NULL;
-
- return -1;
-
-}
diff --git a/drivers/staging/rt2860/wpa.h b/drivers/staging/rt2860/wpa.h
deleted file mode 100644
index a7796d3..0000000
--- a/drivers/staging/rt2860/wpa.h
+++ /dev/null
@@ -1,390 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- wpa.h
-
- Abstract:
-
- Revision History:
- Who When What
- -------- ---------- ----------------------------------------------
- Name Date Modification logs
- Justin P. Mattock 11/07/2010 Fix a typo
-*/
-
-#ifndef __WPA_H__
-#define __WPA_H__
-
-/* EAPOL Key descriptor frame format related length */
-#define LEN_KEY_DESC_NONCE 32
-#define LEN_KEY_DESC_IV 16
-#define LEN_KEY_DESC_RSC 8
-#define LEN_KEY_DESC_ID 8
-#define LEN_KEY_DESC_REPLAY 8
-#define LEN_KEY_DESC_MIC 16
-
-/* The length is the EAPoL-Key frame except key data field. */
-/* Please refer to 802.11i-2004 ,Figure 43u in p.78 */
-#define LEN_EAPOL_KEY_MSG (sizeof(struct rt_key_descripter) - MAX_LEN_OF_RSNIE)
-
-/* EAP Code Type. */
-#define EAP_CODE_REQUEST 1
-#define EAP_CODE_RESPONSE 2
-#define EAP_CODE_SUCCESS 3
-#define EAP_CODE_FAILURE 4
-
-/* EAPOL frame Protocol Version */
-#define EAPOL_VER 1
-#define EAPOL_VER2 2
-
-/* EAPOL-KEY Descriptor Type */
-#define WPA1_KEY_DESC 0xfe
-#define WPA2_KEY_DESC 0x02
-
-/* Key Descriptor Version of Key Information */
-#define DESC_TYPE_TKIP 1
-#define DESC_TYPE_AES 2
-
-#define LEN_MSG1_2WAY 0x7f
-#define MAX_LEN_OF_EAP_HS 256
-
-#define LEN_MASTER_KEY 32
-
-/* EAPOL EK, MK */
-#define LEN_EAP_EK 16
-#define LEN_EAP_MICK 16
-#define LEN_EAP_KEY ((LEN_EAP_EK)+(LEN_EAP_MICK))
-/* TKIP key related */
-#define LEN_PMKID 16
-#define LEN_TKIP_EK 16
-#define LEN_TKIP_RXMICK 8
-#define LEN_TKIP_TXMICK 8
-#define LEN_AES_EK 16
-#define LEN_AES_KEY LEN_AES_EK
-#define LEN_TKIP_KEY ((LEN_TKIP_EK)+(LEN_TKIP_RXMICK)+(LEN_TKIP_TXMICK))
-#define TKIP_AP_TXMICK_OFFSET ((LEN_EAP_KEY)+(LEN_TKIP_EK))
-#define TKIP_AP_RXMICK_OFFSET (TKIP_AP_TXMICK_OFFSET+LEN_TKIP_TXMICK)
-#define TKIP_GTK_LENGTH ((LEN_TKIP_EK)+(LEN_TKIP_RXMICK)+(LEN_TKIP_TXMICK))
-#define LEN_PTK ((LEN_EAP_KEY)+(LEN_TKIP_KEY))
-#define MIN_LEN_OF_GTK 5
-#define LEN_PMK 32
-#define LEN_PMK_NAME 16
-#define LEN_NONCE 32
-
-/* RSN IE Length definition */
-#define MAX_LEN_OF_RSNIE 255
-#define MIN_LEN_OF_RSNIE 8
-
-#define KEY_LIFETIME 3600
-
-/*EAP Packet Type */
-#define EAPPacket 0
-#define EAPOLStart 1
-#define EAPOLLogoff 2
-#define EAPOLKey 3
-#define EAPOLASFAlert 4
-#define EAPTtypeMax 5
-
-#define EAPOL_MSG_INVALID 0
-#define EAPOL_PAIR_MSG_1 1
-#define EAPOL_PAIR_MSG_2 2
-#define EAPOL_PAIR_MSG_3 3
-#define EAPOL_PAIR_MSG_4 4
-#define EAPOL_GROUP_MSG_1 5
-#define EAPOL_GROUP_MSG_2 6
-
-#define PAIRWISEKEY 1
-#define GROUPKEY 0
-
-/* Retry timer counter initial value */
-#define PEER_MSG1_RETRY_TIMER_CTR 0
-#define PEER_MSG3_RETRY_TIMER_CTR 10
-#define GROUP_MSG1_RETRY_TIMER_CTR 20
-
-/*#ifdef CONFIG_AP_SUPPORT */
-/* WPA mechanism retry timer interval */
-#define PEER_MSG1_RETRY_EXEC_INTV 1000 /* 1 sec */
-#define PEER_MSG3_RETRY_EXEC_INTV 3000 /* 3 sec */
-#define GROUP_KEY_UPDATE_EXEC_INTV 1000 /* 1 sec */
-#define PEER_GROUP_KEY_UPDATE_INIV 2000 /* 2 sec */
-
-#define ENQUEUE_EAPOL_START_TIMER 200 /* 200 ms */
-
-/* group rekey interval */
-#define TIME_REKEY 0
-#define PKT_REKEY 1
-#define DISABLE_REKEY 2
-#define MAX_REKEY 2
-
-#define MAX_REKEY_INTER 0x3ffffff
-/*#endif // CONFIG_AP_SUPPORT // */
-
-#define GROUP_SUITE 0
-#define PAIRWISE_SUITE 1
-#define AKM_SUITE 2
-#define PMKID_LIST 3
-
-#define EAPOL_START_DISABLE 0
-#define EAPOL_START_PSK 1
-#define EAPOL_START_1X 2
-
-#define MIX_CIPHER_WPA_TKIP_ON(x) (((x) & 0x08) != 0)
-#define MIX_CIPHER_WPA_AES_ON(x) (((x) & 0x04) != 0)
-#define MIX_CIPHER_WPA2_TKIP_ON(x) (((x) & 0x02) != 0)
-#define MIX_CIPHER_WPA2_AES_ON(x) (((x) & 0x01) != 0)
-
-#ifndef ROUND_UP
-#define ROUND_UP(__x, __y) \
- (((unsigned long)((__x)+((__y)-1))) & ((unsigned long)~((__y)-1)))
-#endif
-
-#define SET_u16_TO_ARRARY(_V, _LEN) \
-{ \
- _V[0] = (_LEN & 0xFF00) >> 8; \
- _V[1] = (_LEN & 0xFF); \
-}
-
-#define INC_u16_TO_ARRARY(_V, _LEN) \
-{ \
- u16 var_len; \
- \
- var_len = (_V[0]<<8) | (_V[1]); \
- var_len += _LEN; \
- \
- _V[0] = (var_len & 0xFF00) >> 8; \
- _V[1] = (var_len & 0xFF); \
-}
-
-#define CONV_ARRARY_TO_u16(_V) ((_V[0]<<8) | (_V[1]))
-
-#define ADD_ONE_To_64BIT_VAR(_V) \
-{ \
- u8 cnt = LEN_KEY_DESC_REPLAY; \
- do \
- { \
- cnt--; \
- _V[cnt]++; \
- if (cnt == 0) \
- break; \
- }while (_V[cnt] == 0); \
-}
-
-#define IS_WPA_CAPABILITY(a) (((a) >= Ndis802_11AuthModeWPA) && ((a) <= Ndis802_11AuthModeWPA1PSKWPA2PSK))
-
-/* EAPOL Key Information definition within Key descriptor format */
-struct PACKED rt_key_info {
- u8 KeyMic:1;
- u8 Secure:1;
- u8 Error:1;
- u8 Request:1;
- u8 EKD_DL:1; /* EKD for AP; DL for STA */
- u8 Rsvd:3;
- u8 KeyDescVer:3;
- u8 KeyType:1;
- u8 KeyIndex:2;
- u8 Install:1;
- u8 KeyAck:1;
-};
-
-/* EAPOL Key descriptor format */
-struct PACKED rt_key_descripter {
- u8 Type;
- struct rt_key_info KeyInfo;
- u8 KeyLength[2];
- u8 ReplayCounter[LEN_KEY_DESC_REPLAY];
- u8 KeyNonce[LEN_KEY_DESC_NONCE];
- u8 KeyIv[LEN_KEY_DESC_IV];
- u8 KeyRsc[LEN_KEY_DESC_RSC];
- u8 KeyId[LEN_KEY_DESC_ID];
- u8 KeyMic[LEN_KEY_DESC_MIC];
- u8 KeyDataLen[2];
- u8 KeyData[MAX_LEN_OF_RSNIE];
-};
-
-struct PACKED rt_eapol_packet {
- u8 ProVer;
- u8 ProType;
- u8 Body_Len[2];
- struct rt_key_descripter KeyDesc;
-};
-
-/*802.11i D10 page 83 */
-struct PACKED rt_gtk_encap {
- u8 Kid:2;
- u8 tx:1;
- u8 rsv:5;
- u8 rsv1;
- u8 GTK[TKIP_GTK_LENGTH];
-};
-
-struct PACKED rt_kde_encap {
- u8 Type;
- u8 Len;
- u8 OUI[3];
- u8 DataType;
- struct rt_gtk_encap GTKEncap;
-};
-
-/* For WPA1 */
-struct PACKED rt_rsnie {
- u8 oui[4];
- u16 version;
- u8 mcast[4];
- u16 ucount;
- struct PACKED {
- u8 oui[4];
- } ucast[1];
-};
-
-/* For WPA2 */
-struct PACKED rt_rsnie2 {
- u16 version;
- u8 mcast[4];
- u16 ucount;
- struct PACKED {
- u8 oui[4];
- } ucast[1];
-};
-
-/* AKM Suite */
-struct PACKED rt_rsnie_auth {
- u16 acount;
- struct PACKED {
- u8 oui[4];
- } auth[1];
-};
-
-typedef union PACKED _RSN_CAPABILITIES {
- struct PACKED {
- u16 PreAuth:1;
- u16 No_Pairwise:1;
- u16 PTKSA_R_Counter:2;
- u16 GTKSA_R_Counter:2;
- u16 Rsvd:10;
- } field;
- u16 word;
-} RSN_CAPABILITIES, *PRSN_CAPABILITIES;
-
-struct PACKED rt_eap_hdr {
- u8 ProVer;
- u8 ProType;
- u8 Body_Len[2];
- u8 code;
- u8 identifier;
- u8 length[2]; /* including code and identifier, followed by length-2 octets of data */
-};
-
-/* For supplicant state machine states. 802.11i Draft 4.1, p. 97 */
-/* We simplified it */
-typedef enum _WpaState {
- SS_NOTUSE, /* 0 */
- SS_START, /* 1 */
- SS_WAIT_MSG_3, /* 2 */
- SS_WAIT_GROUP, /* 3 */
- SS_FINISH, /* 4 */
- SS_KEYUPDATE, /* 5 */
-} WPA_STATE;
-
-/* */
-/* The definition of the cipher combination */
-/* */
-/* bit3 bit2 bit1 bit0 */
-/* +------------+------------+ */
-/* | WPA | WPA2 | */
-/* +------+-----+------+-----+ */
-/* | TKIP | AES | TKIP | AES | */
-/* | 0 | 1 | 1 | 0 | -> 0x06 */
-/* | 0 | 1 | 1 | 1 | -> 0x07 */
-/* | 1 | 0 | 0 | 1 | -> 0x09 */
-/* | 1 | 0 | 1 | 1 | -> 0x0B */
-/* | 1 | 1 | 0 | 1 | -> 0x0D */
-/* | 1 | 1 | 1 | 0 | -> 0x0E */
-/* | 1 | 1 | 1 | 1 | -> 0x0F */
-/* +------+-----+------+-----+ */
-/* */
-typedef enum _WpaMixPairCipher {
- MIX_CIPHER_NOTUSE = 0x00,
- WPA_NONE_WPA2_TKIPAES = 0x03, /* WPA2-TKIPAES */
- WPA_AES_WPA2_TKIP = 0x06,
- WPA_AES_WPA2_TKIPAES = 0x07,
- WPA_TKIP_WPA2_AES = 0x09,
- WPA_TKIP_WPA2_TKIPAES = 0x0B,
- WPA_TKIPAES_WPA2_NONE = 0x0C, /* WPA-TKIPAES */
- WPA_TKIPAES_WPA2_AES = 0x0D,
- WPA_TKIPAES_WPA2_TKIP = 0x0E,
- WPA_TKIPAES_WPA2_TKIPAES = 0x0F,
-} WPA_MIX_PAIR_CIPHER;
-
-struct PACKED rt_rsn_ie_header {
- u8 Eid;
- u8 Length;
- u16 Version; /* Little endian format */
-};
-
-/* Cipher suite selector types */
-struct PACKED rt_cipher_suite_struct {
- u8 Oui[3];
- u8 Type;
-};
-
-/* Authentication and Key Management suite selector */
-struct PACKED rt_akm_suite {
- u8 Oui[3];
- u8 Type;
-};
-
-/* RSN capability */
-struct PACKED rt_rsn_capability {
- u16 Rsv:10;
- u16 GTKSAReplayCnt:2;
- u16 PTKSAReplayCnt:2;
- u16 NoPairwise:1;
- u16 PreAuth:1;
-};
-
-/*========================================
- The prototype is defined in cmm_wpa.c
- ========================================*/
-BOOLEAN WpaMsgTypeSubst(u8 EAPType, int *MsgType);
-
-void PRF(u8 *key, int key_len, u8 *prefix, int prefix_len,
- u8 *data, int data_len, u8 *output, int len);
-
-int PasswordHash(char *password,
- unsigned char *ssid, int ssidlength, unsigned char *output);
-
-u8 *GetSuiteFromRSNIE(u8 *rsnie, u32 rsnie_len, u8 type, u8 *count);
-
-void WpaShowAllsuite(u8 *rsnie, u32 rsnie_len);
-
-void RTMPInsertRSNIE(u8 *pFrameBuf,
- unsigned long *pFrameLen,
- u8 *rsnie_ptr,
- u8 rsnie_len,
- u8 *pmkid_ptr, u8 pmkid_len);
-
-#endif
diff --git a/drivers/staging/rt2870/Kconfig b/drivers/staging/rt2870/Kconfig
deleted file mode 100644
index e988680..0000000
--- a/drivers/staging/rt2870/Kconfig
+++ /dev/null
@@ -1,9 +0,0 @@
-config RT2870
- tristate "Ralink 2870/3070 wireless support"
- depends on USB && (X86 || ARM) && WLAN
- select WIRELESS_EXT
- select WEXT_PRIV
- select CRC_CCITT
- select FW_LOADER
- ---help---
- This is an experimental driver for the Ralink xx70 wireless chips.
diff --git a/drivers/staging/rt2870/Makefile b/drivers/staging/rt2870/Makefile
deleted file mode 100644
index b499910..0000000
--- a/drivers/staging/rt2870/Makefile
+++ /dev/null
@@ -1,55 +0,0 @@
-#
-obj-$(CONFIG_RT2870) += rt2870sta.o
-
-# TODO: all of these should be removed
-ccflags-y := -DLINUX -DAGGREGATION_SUPPORT -DPIGGYBACK_SUPPORT -DWMM_SUPPORT
-ccflags-y += -DRTMP_MAC_USB -DRTMP_USB_SUPPORT -DRT2870 -DRTMP_TIMER_TASK_SUPPORT
-ccflags-y += -DRTMP_RF_RW_SUPPORT -DRTMP_EFUSE_SUPPORT -DRT30xx -DRT3070
-ccflags-y += -DDBG
-
-rt2870sta-y := \
- common/crypt_md5.o \
- common/crypt_sha2.o \
- common/crypt_hmac.o \
- common/mlme.o \
- common/cmm_wep.o \
- common/action.o \
- common/cmm_data.o \
- common/rtmp_init.o \
- common/cmm_tkip.o \
- common/cmm_aes.o \
- common/cmm_sync.o \
- common/eeprom.o \
- common/cmm_sanity.o \
- common/cmm_info.o \
- common/cmm_cfg.o \
- common/cmm_wpa.o \
- common/dfs.o \
- common/spectrum.o \
- common/rtmp_timer.o \
- common/rt_channel.o \
- common/cmm_asic.o \
- sta/assoc.o \
- sta/auth.o \
- sta/auth_rsp.o \
- sta/sync.o \
- sta/sanity.o \
- sta/rtmp_data.o \
- sta/connect.o \
- sta/wpa.o \
- rt_linux.o \
- rt_main_dev.o \
- sta_ioctl.o \
- common/ba_action.o \
- usb_main_dev.o \
- rt_usb.o \
- common/cmm_mac_usb.o \
- common/rtusb_io.o \
- common/rtusb_bulk.o \
- common/rtusb_data.o \
- common/cmm_data_usb.o \
- common/rtmp_mcu.o \
- common/ee_efuse.o \
- chips/rt30xx.o \
- common/rt_rf.o \
- chips/rt3070.o
diff --git a/drivers/staging/rt2870/TODO b/drivers/staging/rt2870/TODO
deleted file mode 100644
index 2df1bfe..0000000
--- a/drivers/staging/rt2870/TODO
+++ /dev/null
@@ -1,17 +0,0 @@
-I'm hesitant to add a TODO file here, as the wireless developers would
-really have people help them out on the "clean" rt2870 driver that can
-be found at the http://rt2x00.serialmonkey.com/ site.
-
-But, if you wish to clean up this driver instead, here's a short list of
-things that need to be done to get it into a more mergable shape:
-
-TODO:
- - checkpatch.pl clean
- - sparse clean
- - port to in-kernel 80211 stack and common rt2x00 infrastructure
- - remove reading from /etc/ config files
- - review by the wireless developer community
-
-Please send any patches or complaints about this driver to Greg
-Kroah-Hartman <greg@kroah.com> and don't bother the upstream wireless
-kernel developers about it, they want nothing to do with it.
diff --git a/drivers/staging/rt2870/aironet.h b/drivers/staging/rt2870/aironet.h
deleted file mode 100644
index ae62597..0000000
--- a/drivers/staging/rt2870/aironet.h
+++ /dev/null
@@ -1 +0,0 @@
-#include "../rt2860/aironet.h"
diff --git a/drivers/staging/rt2870/ap.h b/drivers/staging/rt2870/ap.h
deleted file mode 100644
index fe04b5f..0000000
--- a/drivers/staging/rt2870/ap.h
+++ /dev/null
@@ -1 +0,0 @@
-#include "../rt2860/ap.h"
diff --git a/drivers/staging/rt2870/chips/rt3070.c b/drivers/staging/rt2870/chips/rt3070.c
deleted file mode 100644
index 3a6db5e..0000000
--- a/drivers/staging/rt2870/chips/rt3070.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../../rt2860/chips/rt3070.c"
diff --git a/drivers/staging/rt2870/chips/rt30xx.c b/drivers/staging/rt2870/chips/rt30xx.c
deleted file mode 100644
index 6c56b84..0000000
--- a/drivers/staging/rt2870/chips/rt30xx.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../../rt2860/chips/rt30xx.c"
diff --git a/drivers/staging/rt2870/chlist.h b/drivers/staging/rt2870/chlist.h
deleted file mode 100644
index 3199958..0000000
--- a/drivers/staging/rt2870/chlist.h
+++ /dev/null
@@ -1 +0,0 @@
-#include "../rt2860/chlist.h"
diff --git a/drivers/staging/rt2870/common/acction.c b/drivers/staging/rt2870/common/acction.c
deleted file mode 100644
index fd806c3..0000000
--- a/drivers/staging/rt2870/common/acction.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../../rt2860/common/action.c"
diff --git a/drivers/staging/rt2870/common/action.c b/drivers/staging/rt2870/common/action.c
deleted file mode 100644
index fd806c3..0000000
--- a/drivers/staging/rt2870/common/action.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../../rt2860/common/action.c"
diff --git a/drivers/staging/rt2870/common/action.h b/drivers/staging/rt2870/common/action.h
deleted file mode 100644
index 9a18955..0000000
--- a/drivers/staging/rt2870/common/action.h
+++ /dev/null
@@ -1 +0,0 @@
-#include "../../rt2860/common/action.h"
diff --git a/drivers/staging/rt2870/common/ba_action.c b/drivers/staging/rt2870/common/ba_action.c
deleted file mode 100644
index a9e6a09..0000000
--- a/drivers/staging/rt2870/common/ba_action.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../../rt2860/common/ba_action.c"
diff --git a/drivers/staging/rt2870/common/cmm_aes.c b/drivers/staging/rt2870/common/cmm_aes.c
deleted file mode 100644
index 15d6a14..0000000
--- a/drivers/staging/rt2870/common/cmm_aes.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../../rt2860/common/cmm_aes.c"
diff --git a/drivers/staging/rt2870/common/cmm_asic.c b/drivers/staging/rt2870/common/cmm_asic.c
deleted file mode 100644
index 38de817..0000000
--- a/drivers/staging/rt2870/common/cmm_asic.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../../rt2860/common/cmm_asic.c"
diff --git a/drivers/staging/rt2870/common/cmm_cfg.c b/drivers/staging/rt2870/common/cmm_cfg.c
deleted file mode 100644
index 6b2bdd7..0000000
--- a/drivers/staging/rt2870/common/cmm_cfg.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../../rt2860/common/cmm_cfg.c"
diff --git a/drivers/staging/rt2870/common/cmm_data.c b/drivers/staging/rt2870/common/cmm_data.c
deleted file mode 100644
index df775c3..0000000
--- a/drivers/staging/rt2870/common/cmm_data.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../../rt2860/common/cmm_data.c"
diff --git a/drivers/staging/rt2870/common/cmm_data_usb.c b/drivers/staging/rt2870/common/cmm_data_usb.c
deleted file mode 100644
index 704675f..0000000
--- a/drivers/staging/rt2870/common/cmm_data_usb.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../../rt2860/common/cmm_data_usb.c"
diff --git a/drivers/staging/rt2870/common/cmm_info.c b/drivers/staging/rt2870/common/cmm_info.c
deleted file mode 100644
index 226187e..0000000
--- a/drivers/staging/rt2870/common/cmm_info.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../../rt2860/common/cmm_info.c"
diff --git a/drivers/staging/rt2870/common/cmm_mac_usb.c b/drivers/staging/rt2870/common/cmm_mac_usb.c
deleted file mode 100644
index b26af4a..0000000
--- a/drivers/staging/rt2870/common/cmm_mac_usb.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../../rt2860/common/cmm_mac_usb.c"
diff --git a/drivers/staging/rt2870/common/cmm_profile.c b/drivers/staging/rt2870/common/cmm_profile.c
deleted file mode 100644
index 9926e45..0000000
--- a/drivers/staging/rt2870/common/cmm_profile.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../../rt2860/common/cmm_profile.c"
diff --git a/drivers/staging/rt2870/common/cmm_sanity.c b/drivers/staging/rt2870/common/cmm_sanity.c
deleted file mode 100644
index cb33521..0000000
--- a/drivers/staging/rt2870/common/cmm_sanity.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../../rt2860/common/cmm_sanity.c"
diff --git a/drivers/staging/rt2870/common/cmm_sync.c b/drivers/staging/rt2870/common/cmm_sync.c
deleted file mode 100644
index 5e7221d..0000000
--- a/drivers/staging/rt2870/common/cmm_sync.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../../rt2860/common/cmm_sync.c"
diff --git a/drivers/staging/rt2870/common/cmm_tkip.c b/drivers/staging/rt2870/common/cmm_tkip.c
deleted file mode 100644
index f73c71b..0000000
--- a/drivers/staging/rt2870/common/cmm_tkip.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../../rt2860/common/cmm_tkip.c"
diff --git a/drivers/staging/rt2870/common/cmm_wep.c b/drivers/staging/rt2870/common/cmm_wep.c
deleted file mode 100644
index 5f68107..0000000
--- a/drivers/staging/rt2870/common/cmm_wep.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../../rt2860/common/cmm_wep.c"
diff --git a/drivers/staging/rt2870/common/cmm_wpa.c b/drivers/staging/rt2870/common/cmm_wpa.c
deleted file mode 100644
index 04a54bb..0000000
--- a/drivers/staging/rt2870/common/cmm_wpa.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../../rt2860/common/cmm_wpa.c"
diff --git a/drivers/staging/rt2870/common/crypt_hmac.c b/drivers/staging/rt2870/common/crypt_hmac.c
deleted file mode 100644
index 24d84e7..0000000
--- a/drivers/staging/rt2870/common/crypt_hmac.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../../rt2860/common/crypt_hmac.c"
diff --git a/drivers/staging/rt2870/common/crypt_md5.c b/drivers/staging/rt2870/common/crypt_md5.c
deleted file mode 100644
index 457a2ca..0000000
--- a/drivers/staging/rt2870/common/crypt_md5.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../../rt2860/common/crypt_md5.c"
diff --git a/drivers/staging/rt2870/common/crypt_sha2.c b/drivers/staging/rt2870/common/crypt_sha2.c
deleted file mode 100644
index 07ffb30..0000000
--- a/drivers/staging/rt2870/common/crypt_sha2.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../../rt2860/common/crypt_sha2.c"
diff --git a/drivers/staging/rt2870/common/dfs.c b/drivers/staging/rt2870/common/dfs.c
deleted file mode 100644
index ac2da4c..0000000
--- a/drivers/staging/rt2870/common/dfs.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../../rt2860/common/dfs.c"
diff --git a/drivers/staging/rt2870/common/ee_efuse.c b/drivers/staging/rt2870/common/ee_efuse.c
deleted file mode 100644
index 0e34e65..0000000
--- a/drivers/staging/rt2870/common/ee_efuse.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../../rt2860/common/ee_efuse.c"
diff --git a/drivers/staging/rt2870/common/eeprom.c b/drivers/staging/rt2870/common/eeprom.c
deleted file mode 100644
index def0965..0000000
--- a/drivers/staging/rt2870/common/eeprom.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../../rt2860/common/eeprom.c"
diff --git a/drivers/staging/rt2870/common/md5.c b/drivers/staging/rt2870/common/md5.c
deleted file mode 100644
index 195645c..0000000
--- a/drivers/staging/rt2870/common/md5.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../../rt2860/common/md5.c"
diff --git a/drivers/staging/rt2870/common/mlme.c b/drivers/staging/rt2870/common/mlme.c
deleted file mode 100644
index f88040a..0000000
--- a/drivers/staging/rt2870/common/mlme.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../../rt2860/common/mlme.c"
diff --git a/drivers/staging/rt2870/common/rt_channel.c b/drivers/staging/rt2870/common/rt_channel.c
deleted file mode 100644
index c8ceb4c..0000000
--- a/drivers/staging/rt2870/common/rt_channel.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../../rt2860/common/rt_channel.c"
diff --git a/drivers/staging/rt2870/common/rt_rf.c b/drivers/staging/rt2870/common/rt_rf.c
deleted file mode 100644
index b81cff3..0000000
--- a/drivers/staging/rt2870/common/rt_rf.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../../rt2860/common/rt_rf.c"
diff --git a/drivers/staging/rt2870/common/rtmp_init.c b/drivers/staging/rt2870/common/rtmp_init.c
deleted file mode 100644
index eef10ef..0000000
--- a/drivers/staging/rt2870/common/rtmp_init.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../../rt2860/common/rtmp_init.c"
diff --git a/drivers/staging/rt2870/common/rtmp_mcu.c b/drivers/staging/rt2870/common/rtmp_mcu.c
deleted file mode 100644
index 20b7f13..0000000
--- a/drivers/staging/rt2870/common/rtmp_mcu.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../../rt2860/common/rtmp_mcu.c"
diff --git a/drivers/staging/rt2870/common/rtmp_timer.c b/drivers/staging/rt2870/common/rtmp_timer.c
deleted file mode 100644
index fd4aedc..0000000
--- a/drivers/staging/rt2870/common/rtmp_timer.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../../rt2860/common/rtmp_timer.c"
diff --git a/drivers/staging/rt2870/common/rtmp_tkip.c b/drivers/staging/rt2870/common/rtmp_tkip.c
deleted file mode 100644
index 240bf67..0000000
--- a/drivers/staging/rt2870/common/rtmp_tkip.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../../rt2860/common/rtmp_tkip.c"
diff --git a/drivers/staging/rt2870/common/rtmp_wep.c b/drivers/staging/rt2870/common/rtmp_wep.c
deleted file mode 100644
index ae255ad..0000000
--- a/drivers/staging/rt2870/common/rtmp_wep.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../../rt2860/common/rtmp_wep.c"
diff --git a/drivers/staging/rt2870/common/rtusb_bulk.c b/drivers/staging/rt2870/common/rtusb_bulk.c
deleted file mode 100644
index 679b802..0000000
--- a/drivers/staging/rt2870/common/rtusb_bulk.c
+++ /dev/null
@@ -1,1232 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- rtusb_bulk.c
-
- Abstract:
-
- Revision History:
- Who When What
- -------- ---------- ----------------------------------------------
- Name Date Modification logs
- Paul Lin 06-25-2004 created
-
-*/
-
-#ifdef RTMP_MAC_USB
-
-#include "../rt_config.h"
-/* Match total 6 bulkout endpoint to corresponding queue. */
-u8 EpToQueue[6] =
- { FIFO_EDCA, FIFO_EDCA, FIFO_EDCA, FIFO_EDCA, FIFO_EDCA, FIFO_MGMT };
-
-/*static BOOLEAN SingleBulkOut = FALSE; */
-
-void RTUSB_FILL_BULK_URB(struct urb *pUrb,
- struct usb_device *pUsb_Dev,
- unsigned int bulkpipe,
- void *pTransferBuf,
- int BufSize, usb_complete_t Complete, void *pContext)
-{
-
- usb_fill_bulk_urb(pUrb, pUsb_Dev, bulkpipe, pTransferBuf, BufSize,
- (usb_complete_t) Complete, pContext);
-
-}
-
-void RTUSBInitTxDesc(struct rt_rtmp_adapter *pAd,
- struct rt_tx_context *pTxContext,
- u8 BulkOutPipeId, IN usb_complete_t Func)
-{
- PURB pUrb;
- u8 *pSrc = NULL;
- struct os_cookie *pObj = (struct os_cookie *)pAd->OS_Cookie;
-
- pUrb = pTxContext->pUrb;
- ASSERT(pUrb);
-
- /* Store BulkOut PipeId */
- pTxContext->BulkOutPipeId = BulkOutPipeId;
-
- if (pTxContext->bAggregatible) {
- pSrc = &pTxContext->TransferBuffer->Aggregation[2];
- } else {
- pSrc =
- (u8 *)pTxContext->TransferBuffer->field.WirelessPacket;
- }
-
- /*Initialize a tx bulk urb */
- RTUSB_FILL_BULK_URB(pUrb,
- pObj->pUsb_Dev,
- usb_sndbulkpipe(pObj->pUsb_Dev,
- pAd->BulkOutEpAddr[BulkOutPipeId]),
- pSrc, pTxContext->BulkOutSize, Func, pTxContext);
-
- if (pTxContext->bAggregatible)
- pUrb->transfer_dma =
- (pTxContext->data_dma + TX_BUFFER_NORMSIZE + 2);
- else
- pUrb->transfer_dma = pTxContext->data_dma;
-
- pUrb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP;
-
-}
-
-void RTUSBInitHTTxDesc(struct rt_rtmp_adapter *pAd,
- struct rt_ht_tx_context *pTxContext,
- u8 BulkOutPipeId,
- unsigned long BulkOutSize, IN usb_complete_t Func)
-{
- PURB pUrb;
- u8 *pSrc = NULL;
- struct os_cookie *pObj = (struct os_cookie *)pAd->OS_Cookie;
-
- pUrb = pTxContext->pUrb;
- ASSERT(pUrb);
-
- /* Store BulkOut PipeId */
- pTxContext->BulkOutPipeId = BulkOutPipeId;
-
- pSrc =
- &pTxContext->TransferBuffer->field.WirelessPacket[pTxContext->
- NextBulkOutPosition];
-
- /*Initialize a tx bulk urb */
- RTUSB_FILL_BULK_URB(pUrb,
- pObj->pUsb_Dev,
- usb_sndbulkpipe(pObj->pUsb_Dev,
- pAd->BulkOutEpAddr[BulkOutPipeId]),
- pSrc, BulkOutSize, Func, pTxContext);
-
- pUrb->transfer_dma =
- (pTxContext->data_dma + pTxContext->NextBulkOutPosition);
- pUrb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP;
-
-}
-
-void RTUSBInitRxDesc(struct rt_rtmp_adapter *pAd, struct rt_rx_context *pRxContext)
-{
- PURB pUrb;
- struct os_cookie *pObj = (struct os_cookie *)pAd->OS_Cookie;
- unsigned long RX_bulk_size;
-
- pUrb = pRxContext->pUrb;
- ASSERT(pUrb);
-
- if (pAd->BulkInMaxPacketSize == 64)
- RX_bulk_size = 4096;
- else
- RX_bulk_size = MAX_RXBULK_SIZE;
-
- /*Initialize a rx bulk urb */
- RTUSB_FILL_BULK_URB(pUrb,
- pObj->pUsb_Dev,
- usb_rcvbulkpipe(pObj->pUsb_Dev, pAd->BulkInEpAddr),
- &(pRxContext->
- TransferBuffer[pAd->NextRxBulkInPosition]),
- RX_bulk_size - (pAd->NextRxBulkInPosition),
- (usb_complete_t) RTUSBBulkRxComplete,
- (void *)pRxContext);
-
- pUrb->transfer_dma = pRxContext->data_dma + pAd->NextRxBulkInPosition;
- pUrb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP;
-
-}
-
-/*
- ========================================================================
-
- Routine Description:
-
- Arguments:
-
- Return Value:
-
- Note:
-
- ========================================================================
-*/
-
-#define BULK_OUT_LOCK(pLock, IrqFlags) \
- if (1 /*!(in_interrupt() & 0xffff0000)*/) \
- RTMP_IRQ_LOCK((pLock), IrqFlags);
-
-#define BULK_OUT_UNLOCK(pLock, IrqFlags) \
- if (1 /*!(in_interrupt() & 0xffff0000)*/) \
- RTMP_IRQ_UNLOCK((pLock), IrqFlags);
-
-void RTUSBBulkOutDataPacket(struct rt_rtmp_adapter *pAd,
- u8 BulkOutPipeId, u8 Index)
-{
-
- struct rt_ht_tx_context *pHTTXContext;
- PURB pUrb;
- int ret = 0;
- struct rt_txinfo *pTxInfo, *pLastTxInfo = NULL;
- struct rt_txwi *pTxWI;
- unsigned long TmpBulkEndPos, ThisBulkSize;
- unsigned long IrqFlags = 0, IrqFlags2 = 0;
- u8 *pWirelessPkt, *pAppendant;
- BOOLEAN bTxQLastRound = FALSE;
- u8 allzero[4] = { 0x0, 0x0, 0x0, 0x0 };
-
- BULK_OUT_LOCK(&pAd->BulkOutLock[BulkOutPipeId], IrqFlags);
- if ((pAd->BulkOutPending[BulkOutPipeId] == TRUE)
- || RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NEED_STOP_TX)) {
- BULK_OUT_UNLOCK(&pAd->BulkOutLock[BulkOutPipeId], IrqFlags);
- return;
- }
- pAd->BulkOutPending[BulkOutPipeId] = TRUE;
-
- if (!OPSTATUS_TEST_FLAG(pAd, fOP_STATUS_MEDIA_STATE_CONNECTED)
- ) {
- pAd->BulkOutPending[BulkOutPipeId] = FALSE;
- BULK_OUT_UNLOCK(&pAd->BulkOutLock[BulkOutPipeId], IrqFlags);
- return;
- }
- BULK_OUT_UNLOCK(&pAd->BulkOutLock[BulkOutPipeId], IrqFlags);
-
- pHTTXContext = &(pAd->TxContext[BulkOutPipeId]);
-
- BULK_OUT_LOCK(&pAd->TxContextQueueLock[BulkOutPipeId], IrqFlags2);
- if ((pHTTXContext->ENextBulkOutPosition ==
- pHTTXContext->CurWritePosition)
- || ((pHTTXContext->ENextBulkOutPosition - 8) ==
- pHTTXContext->CurWritePosition)) {
- BULK_OUT_UNLOCK(&pAd->TxContextQueueLock[BulkOutPipeId],
- IrqFlags2);
-
- BULK_OUT_LOCK(&pAd->BulkOutLock[BulkOutPipeId], IrqFlags);
- pAd->BulkOutPending[BulkOutPipeId] = FALSE;
-
- /* Clear Data flag */
- RTUSB_CLEAR_BULK_FLAG(pAd,
- (fRTUSB_BULK_OUT_DATA_FRAG <<
- BulkOutPipeId));
- RTUSB_CLEAR_BULK_FLAG(pAd,
- (fRTUSB_BULK_OUT_DATA_NORMAL <<
- BulkOutPipeId));
-
- BULK_OUT_UNLOCK(&pAd->BulkOutLock[BulkOutPipeId], IrqFlags);
- return;
- }
- /* Clear Data flag */
- RTUSB_CLEAR_BULK_FLAG(pAd,
- (fRTUSB_BULK_OUT_DATA_FRAG << BulkOutPipeId));
- RTUSB_CLEAR_BULK_FLAG(pAd,
- (fRTUSB_BULK_OUT_DATA_NORMAL << BulkOutPipeId));
-
- /*DBGPRINT(RT_DEBUG_TRACE,("BulkOut-B:I=0x%lx, CWPos=%ld, CWRPos=%ld, NBPos=%ld, ENBPos=%ld, bCopy=%d!\n", in_interrupt(), */
- /* pHTTXContext->CurWritePosition, pHTTXContext->CurWriteRealPos, pHTTXContext->NextBulkOutPosition, */
- /* pHTTXContext->ENextBulkOutPosition, pHTTXContext->bCopySavePad)); */
- pHTTXContext->NextBulkOutPosition = pHTTXContext->ENextBulkOutPosition;
- ThisBulkSize = 0;
- TmpBulkEndPos = pHTTXContext->NextBulkOutPosition;
- pWirelessPkt = &pHTTXContext->TransferBuffer->field.WirelessPacket[0];
-
- if ((pHTTXContext->bCopySavePad == TRUE)) {
- if (RTMPEqualMemory(pHTTXContext->SavedPad, allzero, 4)) {
- DBGPRINT_RAW(RT_DEBUG_ERROR,
- ("e1, allzero : %x %x %x %x %x %x %x %x \n",
- pHTTXContext->SavedPad[0],
- pHTTXContext->SavedPad[1],
- pHTTXContext->SavedPad[2],
- pHTTXContext->SavedPad[3]
- , pHTTXContext->SavedPad[4],
- pHTTXContext->SavedPad[5],
- pHTTXContext->SavedPad[6],
- pHTTXContext->SavedPad[7]));
- }
- NdisMoveMemory(&pWirelessPkt[TmpBulkEndPos],
- pHTTXContext->SavedPad, 8);
- pHTTXContext->bCopySavePad = FALSE;
- if (pAd->bForcePrintTX == TRUE)
- DBGPRINT(RT_DEBUG_TRACE,
- ("RTUSBBulkOutDataPacket --> COPY PAD. CurWrite = %ld, NextBulk = %ld. ENextBulk = %ld.\n",
- pHTTXContext->CurWritePosition,
- pHTTXContext->NextBulkOutPosition,
- pHTTXContext->ENextBulkOutPosition));
- }
-
- do {
- pTxInfo = (struct rt_txinfo *)&pWirelessPkt[TmpBulkEndPos];
- pTxWI =
- (struct rt_txwi *)&pWirelessPkt[TmpBulkEndPos + TXINFO_SIZE];
-
- if (pAd->bForcePrintTX == TRUE)
- DBGPRINT(RT_DEBUG_TRACE,
- ("RTUSBBulkOutDataPacket AMPDU = %d.\n",
- pTxWI->AMPDU));
-
- /* add by Iverson, limit BulkOut size to 4k to pass WMM b mode 2T1R test items */
- /*if ((ThisBulkSize != 0) && (pTxWI->AMPDU == 0)) */
- if ((ThisBulkSize != 0) && (pTxWI->PHYMODE == MODE_CCK)) {
- if (((ThisBulkSize & 0xffff8000) != 0)
- || ((ThisBulkSize & 0x1000) == 0x1000)) {
- /* Limit BulkOut size to about 4k bytes. */
- pHTTXContext->ENextBulkOutPosition =
- TmpBulkEndPos;
- break;
- } else
- if (((pAd->BulkOutMaxPacketSize < 512)
- && ((ThisBulkSize & 0xfffff800) !=
- 0))
- /*|| ( (ThisBulkSize != 0) && (pTxWI->AMPDU == 0)) */
- ) {
- /* For USB 1.1 or peer which didn't support AMPDU, limit the BulkOut size. */
- /* For performance in b/g mode, now just check for USB 1.1 and didn't care about the APMDU or not! 2008/06/04. */
- pHTTXContext->ENextBulkOutPosition =
- TmpBulkEndPos;
- break;
- }
- }
- /* end Iverson */
- else {
- if (((ThisBulkSize & 0xffff8000) != 0) || ((ThisBulkSize & 0x6000) == 0x6000)) { /* Limit BulkOut size to about 24k bytes. */
- pHTTXContext->ENextBulkOutPosition =
- TmpBulkEndPos;
- break;
- } else if (((pAd->BulkOutMaxPacketSize < 512) && ((ThisBulkSize & 0xfffff800) != 0)) /*|| ( (ThisBulkSize != 0) && (pTxWI->AMPDU == 0)) */) { /* For USB 1.1 or peer which didn't support AMPDU, limit the BulkOut size. */
- /* For performance in b/g mode, now just check for USB 1.1 and didn't care about the APMDU or not! 2008/06/04. */
- pHTTXContext->ENextBulkOutPosition =
- TmpBulkEndPos;
- break;
- }
- }
-
- if (TmpBulkEndPos == pHTTXContext->CurWritePosition) {
- pHTTXContext->ENextBulkOutPosition = TmpBulkEndPos;
- break;
- }
-
- if (pTxInfo->QSEL != FIFO_EDCA) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("%s(): ====> pTxInfo->QueueSel(%d)!= FIFO_EDCA!!!!\n",
- __func__, pTxInfo->QSEL));
- DBGPRINT(RT_DEBUG_ERROR,
- ("\tCWPos=%ld, NBPos=%ld, ENBPos=%ld, bCopy=%d!\n",
- pHTTXContext->CurWritePosition,
- pHTTXContext->NextBulkOutPosition,
- pHTTXContext->ENextBulkOutPosition,
- pHTTXContext->bCopySavePad));
- hex_dump("Wrong QSel Pkt:",
- (u8 *)&pWirelessPkt[TmpBulkEndPos],
- (pHTTXContext->CurWritePosition -
- pHTTXContext->NextBulkOutPosition));
- }
-
- if (pTxInfo->USBDMATxPktLen <= 8) {
- BULK_OUT_UNLOCK(&pAd->TxContextQueueLock[BulkOutPipeId],
- IrqFlags2);
- DBGPRINT(RT_DEBUG_ERROR /*RT_DEBUG_TRACE */ ,
- ("e2, USBDMATxPktLen==0, Size=%ld, bCSPad=%d, CWPos=%ld, NBPos=%ld, CWRPos=%ld!\n",
- pHTTXContext->BulkOutSize,
- pHTTXContext->bCopySavePad,
- pHTTXContext->CurWritePosition,
- pHTTXContext->NextBulkOutPosition,
- pHTTXContext->CurWriteRealPos));
- {
- DBGPRINT_RAW(RT_DEBUG_ERROR /*RT_DEBUG_TRACE */
- ,
- ("%x %x %x %x %x %x %x %x \n",
- pHTTXContext->SavedPad[0],
- pHTTXContext->SavedPad[1],
- pHTTXContext->SavedPad[2],
- pHTTXContext->SavedPad[3]
- , pHTTXContext->SavedPad[4],
- pHTTXContext->SavedPad[5],
- pHTTXContext->SavedPad[6],
- pHTTXContext->SavedPad[7]));
- }
- pAd->bForcePrintTX = TRUE;
- BULK_OUT_LOCK(&pAd->BulkOutLock[BulkOutPipeId],
- IrqFlags);
- pAd->BulkOutPending[BulkOutPipeId] = FALSE;
- BULK_OUT_UNLOCK(&pAd->BulkOutLock[BulkOutPipeId],
- IrqFlags);
- /*DBGPRINT(RT_DEBUG_LOUD,("Out:pTxInfo->USBDMATxPktLen=%d!\n", pTxInfo->USBDMATxPktLen)); */
- return;
- }
- /* Increase Total transmit byte counter */
- pAd->RalinkCounters.OneSecTransmittedByteCount +=
- pTxWI->MPDUtotalByteCount;
- pAd->RalinkCounters.TransmittedByteCount +=
- pTxWI->MPDUtotalByteCount;
-
- pLastTxInfo = pTxInfo;
-
- /* Make sure we use EDCA QUEUE. */
- pTxInfo->QSEL = FIFO_EDCA;
- ThisBulkSize += (pTxInfo->USBDMATxPktLen + 4);
- TmpBulkEndPos += (pTxInfo->USBDMATxPktLen + 4);
-
- if (TmpBulkEndPos != pHTTXContext->CurWritePosition)
- pTxInfo->USBDMANextVLD = 1;
-
- if (pTxInfo->SwUseLastRound == 1) {
- if (pHTTXContext->CurWritePosition == 8)
- pTxInfo->USBDMANextVLD = 0;
- pTxInfo->SwUseLastRound = 0;
-
- bTxQLastRound = TRUE;
- pHTTXContext->ENextBulkOutPosition = 8;
-
- break;
- }
-
- } while (TRUE);
-
- /* adjust the pTxInfo->USBDMANextVLD value of last pTxInfo. */
- if (pLastTxInfo)
- pLastTxInfo->USBDMANextVLD = 0;
-
- /*
- We need to copy SavedPad when following condition matched!
- 1. Not the last round of the TxQueue and
- 2. any match of following cases:
- (1). The End Position of this bulk out is reach to the Currenct Write position and
- the TxInfo and related header already write to the CurWritePosition.
- =>(ENextBulkOutPosition == CurWritePosition) && (CurWriteRealPos > CurWritePosition)
-
- (2). The EndPosition of the bulk out is not reach to the Current Write Position.
- =>(ENextBulkOutPosition != CurWritePosition)
- */
- if ((bTxQLastRound == FALSE) &&
- (((pHTTXContext->ENextBulkOutPosition ==
- pHTTXContext->CurWritePosition)
- && (pHTTXContext->CurWriteRealPos >
- pHTTXContext->CurWritePosition))
- || (pHTTXContext->ENextBulkOutPosition !=
- pHTTXContext->CurWritePosition))
- ) {
- NdisMoveMemory(pHTTXContext->SavedPad,
- &pWirelessPkt[pHTTXContext->
- ENextBulkOutPosition], 8);
- pHTTXContext->bCopySavePad = TRUE;
- if (RTMPEqualMemory(pHTTXContext->SavedPad, allzero, 4)) {
- u8 *pBuf = &pHTTXContext->SavedPad[0];
- DBGPRINT_RAW(RT_DEBUG_ERROR,
- ("WARNING-Zero-3:%02x%02x%02x%02x%02x%02x%02x%02x,CWPos=%ld, CWRPos=%ld, bCW=%d, NBPos=%ld, TBPos=%ld, TBSize=%ld\n",
- pBuf[0], pBuf[1], pBuf[2], pBuf[3],
- pBuf[4], pBuf[5], pBuf[6], pBuf[7],
- pHTTXContext->CurWritePosition,
- pHTTXContext->CurWriteRealPos,
- pHTTXContext->bCurWriting,
- pHTTXContext->NextBulkOutPosition,
- TmpBulkEndPos, ThisBulkSize));
-
- pBuf = &pWirelessPkt[pHTTXContext->CurWritePosition];
- DBGPRINT_RAW(RT_DEBUG_ERROR,
- ("\tCWPos=%02x%02x%02x%02x%02x%02x%02x%02x\n",
- pBuf[0], pBuf[1], pBuf[2], pBuf[3],
- pBuf[4], pBuf[5], pBuf[6], pBuf[7]));
- }
- /*DBGPRINT(RT_DEBUG_LOUD,("ENPos==CWPos=%ld, CWRPos=%ld, bCSPad=%d!\n", pHTTXContext->CurWritePosition, pHTTXContext->CurWriteRealPos, pHTTXContext->bCopySavePad)); */
- }
-
- if (pAd->bForcePrintTX == TRUE)
- DBGPRINT(RT_DEBUG_TRACE,
- ("BulkOut-A:Size=%ld, CWPos=%ld, NBPos=%ld, ENBPos=%ld, bCopy=%d!\n",
- ThisBulkSize, pHTTXContext->CurWritePosition,
- pHTTXContext->NextBulkOutPosition,
- pHTTXContext->ENextBulkOutPosition,
- pHTTXContext->bCopySavePad));
- /*DBGPRINT(RT_DEBUG_LOUD,("BulkOut-A:Size=%ld, CWPos=%ld, CWRPos=%ld, NBPos=%ld, ENBPos=%ld, bCopy=%d, bLRound=%d!\n", ThisBulkSize, pHTTXContext->CurWritePosition, pHTTXContext->CurWriteRealPos, pHTTXContext->NextBulkOutPosition, pHTTXContext->ENextBulkOutPosition, pHTTXContext->bCopySavePad, bTxQLastRound)); */
-
- /* USB DMA engine requires to pad extra 4 bytes. This pad doesn't count into real bulkoutsize. */
- pAppendant = &pWirelessPkt[TmpBulkEndPos];
- NdisZeroMemory(pAppendant, 8);
- ThisBulkSize += 4;
- pHTTXContext->LastOne = TRUE;
- if ((ThisBulkSize % pAd->BulkOutMaxPacketSize) == 0)
- ThisBulkSize += 4;
- pHTTXContext->BulkOutSize = ThisBulkSize;
-
- pAd->watchDogTxPendingCnt[BulkOutPipeId] = 1;
- BULK_OUT_UNLOCK(&pAd->TxContextQueueLock[BulkOutPipeId], IrqFlags2);
-
- /* Init Tx context descriptor */
- RTUSBInitHTTxDesc(pAd, pHTTXContext, BulkOutPipeId, ThisBulkSize,
- (usb_complete_t) RTUSBBulkOutDataPacketComplete);
-
- pUrb = pHTTXContext->pUrb;
- ret = RTUSB_SUBMIT_URB(pUrb);
- if (ret != 0) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("RTUSBBulkOutDataPacket: Submit Tx URB failed %d\n",
- ret));
-
- BULK_OUT_LOCK(&pAd->BulkOutLock[BulkOutPipeId], IrqFlags);
- pAd->BulkOutPending[BulkOutPipeId] = FALSE;
- pAd->watchDogTxPendingCnt[BulkOutPipeId] = 0;
- BULK_OUT_UNLOCK(&pAd->BulkOutLock[BulkOutPipeId], IrqFlags);
-
- return;
- }
-
- BULK_OUT_LOCK(&pAd->BulkOutLock[BulkOutPipeId], IrqFlags);
- pHTTXContext->IRPPending = TRUE;
- BULK_OUT_UNLOCK(&pAd->BulkOutLock[BulkOutPipeId], IrqFlags);
- pAd->BulkOutReq++;
-
-}
-
-void RTUSBBulkOutDataPacketComplete(struct urb *pUrb, struct pt_regs * pt_regs)
-{
- struct rt_ht_tx_context *pHTTXContext;
- struct rt_rtmp_adapter *pAd;
- struct os_cookie *pObj;
- u8 BulkOutPipeId;
-
- pHTTXContext = (struct rt_ht_tx_context *)pUrb->context;
- pAd = pHTTXContext->pAd;
- pObj = (struct os_cookie *)pAd->OS_Cookie;
-
- /* Store BulkOut PipeId */
- BulkOutPipeId = pHTTXContext->BulkOutPipeId;
- pAd->BulkOutDataOneSecCount++;
-
- switch (BulkOutPipeId) {
- case 0:
- pObj->ac0_dma_done_task.data = (unsigned long)pUrb;
- tasklet_hi_schedule(&pObj->ac0_dma_done_task);
- break;
- case 1:
- pObj->ac1_dma_done_task.data = (unsigned long)pUrb;
- tasklet_hi_schedule(&pObj->ac1_dma_done_task);
- break;
- case 2:
- pObj->ac2_dma_done_task.data = (unsigned long)pUrb;
- tasklet_hi_schedule(&pObj->ac2_dma_done_task);
- break;
- case 3:
- pObj->ac3_dma_done_task.data = (unsigned long)pUrb;
- tasklet_hi_schedule(&pObj->ac3_dma_done_task);
- break;
- }
-
-}
-
-/*
- ========================================================================
-
- Routine Description:
-
- Arguments:
-
- Return Value:
-
- Note: NULL frame use BulkOutPipeId = 0
-
- ========================================================================
-*/
-void RTUSBBulkOutNullFrame(struct rt_rtmp_adapter *pAd)
-{
- struct rt_tx_context *pNullContext = &(pAd->NullContext);
- PURB pUrb;
- int ret = 0;
- unsigned long IrqFlags;
-
- RTMP_IRQ_LOCK(&pAd->BulkOutLock[0], IrqFlags);
- if ((pAd->BulkOutPending[0] == TRUE)
- || RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NEED_STOP_TX)) {
- RTMP_IRQ_UNLOCK(&pAd->BulkOutLock[0], IrqFlags);
- return;
- }
- pAd->BulkOutPending[0] = TRUE;
- pAd->watchDogTxPendingCnt[0] = 1;
- pNullContext->IRPPending = TRUE;
- RTMP_IRQ_UNLOCK(&pAd->BulkOutLock[0], IrqFlags);
-
- /* Increase Total transmit byte counter */
- pAd->RalinkCounters.TransmittedByteCount += pNullContext->BulkOutSize;
-
- /* Clear Null frame bulk flag */
- RTUSB_CLEAR_BULK_FLAG(pAd, fRTUSB_BULK_OUT_DATA_NULL);
-
- /* Init Tx context descriptor */
- RTUSBInitTxDesc(pAd, pNullContext, 0,
- (usb_complete_t) RTUSBBulkOutNullFrameComplete);
-
- pUrb = pNullContext->pUrb;
- ret = RTUSB_SUBMIT_URB(pUrb);
- if (ret != 0) {
- RTMP_IRQ_LOCK(&pAd->BulkOutLock[0], IrqFlags);
- pAd->BulkOutPending[0] = FALSE;
- pAd->watchDogTxPendingCnt[0] = 0;
- pNullContext->IRPPending = FALSE;
- RTMP_IRQ_UNLOCK(&pAd->BulkOutLock[0], IrqFlags);
-
- DBGPRINT(RT_DEBUG_ERROR,
- ("RTUSBBulkOutNullFrame: Submit Tx URB failed %d\n",
- ret));
- return;
- }
-
-}
-
-/* NULL frame use BulkOutPipeId = 0 */
-void RTUSBBulkOutNullFrameComplete(struct urb *pUrb, struct pt_regs * pt_regs)
-{
- struct rt_rtmp_adapter *pAd;
- struct rt_tx_context *pNullContext;
- int Status;
- struct os_cookie *pObj;
-
- pNullContext = (struct rt_tx_context *)pUrb->context;
- pAd = pNullContext->pAd;
- Status = pUrb->status;
-
- pObj = (struct os_cookie *)pAd->OS_Cookie;
- pObj->null_frame_complete_task.data = (unsigned long)pUrb;
- tasklet_hi_schedule(&pObj->null_frame_complete_task);
-}
-
-/*
- ========================================================================
-
- Routine Description:
-
- Arguments:
-
- Return Value:
-
- Note: MLME use BulkOutPipeId = 0
-
- ========================================================================
-*/
-void RTUSBBulkOutMLMEPacket(struct rt_rtmp_adapter *pAd, u8 Index)
-{
- struct rt_tx_context *pMLMEContext;
- PURB pUrb;
- int ret = 0;
- unsigned long IrqFlags;
-
- pMLMEContext =
- (struct rt_tx_context *)pAd->MgmtRing.Cell[pAd->MgmtRing.TxDmaIdx].AllocVa;
- pUrb = pMLMEContext->pUrb;
-
- if ((pAd->MgmtRing.TxSwFreeIdx >= MGMT_RING_SIZE) ||
- (pMLMEContext->InUse == FALSE) ||
- (pMLMEContext->bWaitingBulkOut == FALSE)) {
-
- /* Clear MLME bulk flag */
- RTUSB_CLEAR_BULK_FLAG(pAd, fRTUSB_BULK_OUT_MLME);
-
- return;
- }
-
- RTMP_IRQ_LOCK(&pAd->BulkOutLock[MGMTPIPEIDX], IrqFlags);
- if ((pAd->BulkOutPending[MGMTPIPEIDX] == TRUE)
- || RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NEED_STOP_TX)) {
- RTMP_IRQ_UNLOCK(&pAd->BulkOutLock[MGMTPIPEIDX], IrqFlags);
- return;
- }
-
- pAd->BulkOutPending[MGMTPIPEIDX] = TRUE;
- pAd->watchDogTxPendingCnt[MGMTPIPEIDX] = 1;
- pMLMEContext->IRPPending = TRUE;
- pMLMEContext->bWaitingBulkOut = FALSE;
- RTMP_IRQ_UNLOCK(&pAd->BulkOutLock[MGMTPIPEIDX], IrqFlags);
-
- /* Increase Total transmit byte counter */
- pAd->RalinkCounters.TransmittedByteCount += pMLMEContext->BulkOutSize;
-
- /* Clear MLME bulk flag */
- RTUSB_CLEAR_BULK_FLAG(pAd, fRTUSB_BULK_OUT_MLME);
-
- /* Init Tx context descriptor */
- RTUSBInitTxDesc(pAd, pMLMEContext, MGMTPIPEIDX,
- (usb_complete_t) RTUSBBulkOutMLMEPacketComplete);
-
- /*For mgmt urb buffer, because we use sk_buff, so we need to notify the USB controller do dma mapping. */
- pUrb->transfer_dma = 0;
- pUrb->transfer_flags &= (~URB_NO_TRANSFER_DMA_MAP);
-
- pUrb = pMLMEContext->pUrb;
- ret = RTUSB_SUBMIT_URB(pUrb);
- if (ret != 0) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("RTUSBBulkOutMLMEPacket: Submit MLME URB failed %d\n",
- ret));
- RTMP_IRQ_LOCK(&pAd->BulkOutLock[MGMTPIPEIDX], IrqFlags);
- pAd->BulkOutPending[MGMTPIPEIDX] = FALSE;
- pAd->watchDogTxPendingCnt[MGMTPIPEIDX] = 0;
- pMLMEContext->IRPPending = FALSE;
- pMLMEContext->bWaitingBulkOut = TRUE;
- RTMP_IRQ_UNLOCK(&pAd->BulkOutLock[MGMTPIPEIDX], IrqFlags);
-
- return;
- }
- /*DBGPRINT_RAW(RT_DEBUG_INFO, ("<---RTUSBBulkOutMLMEPacket \n")); */
-/* printk("<---RTUSBBulkOutMLMEPacket,Cpu=%d!, Dma=%d, SwIdx=%d!\n", pAd->MgmtRing.TxCpuIdx, pAd->MgmtRing.TxDmaIdx, pAd->MgmtRing.TxSwFreeIdx); */
-}
-
-void RTUSBBulkOutMLMEPacketComplete(struct urb *pUrb, struct pt_regs * pt_regs)
-{
- struct rt_tx_context *pMLMEContext;
- struct rt_rtmp_adapter *pAd;
- int Status;
- struct os_cookie *pObj;
- int index;
-
- /*DBGPRINT_RAW(RT_DEBUG_INFO, ("--->RTUSBBulkOutMLMEPacketComplete\n")); */
- pMLMEContext = (struct rt_tx_context *)pUrb->context;
- pAd = pMLMEContext->pAd;
- pObj = (struct os_cookie *)pAd->OS_Cookie;
- Status = pUrb->status;
- index = pMLMEContext->SelfIdx;
-
- pObj->mgmt_dma_done_task.data = (unsigned long)pUrb;
- tasklet_hi_schedule(&pObj->mgmt_dma_done_task);
-}
-
-/*
- ========================================================================
-
- Routine Description:
-
- Arguments:
-
- Return Value:
-
- Note: PsPoll use BulkOutPipeId = 0
-
- ========================================================================
-*/
-void RTUSBBulkOutPsPoll(struct rt_rtmp_adapter *pAd)
-{
- struct rt_tx_context *pPsPollContext = &(pAd->PsPollContext);
- PURB pUrb;
- int ret = 0;
- unsigned long IrqFlags;
-
- RTMP_IRQ_LOCK(&pAd->BulkOutLock[0], IrqFlags);
- if ((pAd->BulkOutPending[0] == TRUE)
- || RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NEED_STOP_TX)) {
- RTMP_IRQ_UNLOCK(&pAd->BulkOutLock[0], IrqFlags);
- return;
- }
- pAd->BulkOutPending[0] = TRUE;
- pAd->watchDogTxPendingCnt[0] = 1;
- pPsPollContext->IRPPending = TRUE;
- RTMP_IRQ_UNLOCK(&pAd->BulkOutLock[0], IrqFlags);
-
- /* Clear PS-Poll bulk flag */
- RTUSB_CLEAR_BULK_FLAG(pAd, fRTUSB_BULK_OUT_PSPOLL);
-
- /* Init Tx context descriptor */
- RTUSBInitTxDesc(pAd, pPsPollContext, MGMTPIPEIDX,
- (usb_complete_t) RTUSBBulkOutPsPollComplete);
-
- pUrb = pPsPollContext->pUrb;
- ret = RTUSB_SUBMIT_URB(pUrb);
- if (ret != 0) {
- RTMP_IRQ_LOCK(&pAd->BulkOutLock[0], IrqFlags);
- pAd->BulkOutPending[0] = FALSE;
- pAd->watchDogTxPendingCnt[0] = 0;
- pPsPollContext->IRPPending = FALSE;
- RTMP_IRQ_UNLOCK(&pAd->BulkOutLock[0], IrqFlags);
-
- DBGPRINT(RT_DEBUG_ERROR,
- ("RTUSBBulkOutPsPoll: Submit Tx URB failed %d\n",
- ret));
- return;
- }
-
-}
-
-/* PS-Poll frame use BulkOutPipeId = 0 */
-void RTUSBBulkOutPsPollComplete(struct urb *pUrb, struct pt_regs * pt_regs)
-{
- struct rt_rtmp_adapter *pAd;
- struct rt_tx_context *pPsPollContext;
- int Status;
- struct os_cookie *pObj;
-
- pPsPollContext = (struct rt_tx_context *)pUrb->context;
- pAd = pPsPollContext->pAd;
- Status = pUrb->status;
-
- pObj = (struct os_cookie *)pAd->OS_Cookie;
- pObj->pspoll_frame_complete_task.data = (unsigned long)pUrb;
- tasklet_hi_schedule(&pObj->pspoll_frame_complete_task);
-}
-
-void DoBulkIn(struct rt_rtmp_adapter *pAd)
-{
- struct rt_rx_context *pRxContext;
- PURB pUrb;
- int ret = 0;
- unsigned long IrqFlags;
-
- RTMP_IRQ_LOCK(&pAd->BulkInLock, IrqFlags);
- pRxContext = &(pAd->RxContext[pAd->NextRxBulkInIndex]);
- if ((pAd->PendingRx > 0) || (pRxContext->Readable == TRUE)
- || (pRxContext->InUse == TRUE)) {
- RTMP_IRQ_UNLOCK(&pAd->BulkInLock, IrqFlags);
- return;
- }
- pRxContext->InUse = TRUE;
- pRxContext->IRPPending = TRUE;
- pAd->PendingRx++;
- pAd->BulkInReq++;
- RTMP_IRQ_UNLOCK(&pAd->BulkInLock, IrqFlags);
-
- /* Init Rx context descriptor */
- NdisZeroMemory(pRxContext->TransferBuffer, pRxContext->BulkInOffset);
- RTUSBInitRxDesc(pAd, pRxContext);
-
- pUrb = pRxContext->pUrb;
- ret = RTUSB_SUBMIT_URB(pUrb);
- if (ret != 0) { /* fail */
-
- RTMP_IRQ_LOCK(&pAd->BulkInLock, IrqFlags);
- pRxContext->InUse = FALSE;
- pRxContext->IRPPending = FALSE;
- pAd->PendingRx--;
- pAd->BulkInReq--;
- RTMP_IRQ_UNLOCK(&pAd->BulkInLock, IrqFlags);
- DBGPRINT(RT_DEBUG_ERROR,
- ("RTUSBBulkReceive: Submit Rx URB failed %d\n", ret));
- } else { /* success */
- ASSERT((pRxContext->InUse == pRxContext->IRPPending));
- /*printk("BIDone, Pend=%d,BIIdx=%d,BIRIdx=%d!\n", pAd->PendingRx, pAd->NextRxBulkInIndex, pAd->NextRxBulkInReadIndex); */
- }
-}
-
-/*
- ========================================================================
-
- Routine Description:
- USB_RxPacket initializes a URB and uses the Rx IRP to submit it
- to USB. It checks if an Rx Descriptor is available and passes the
- the coresponding buffer to be filled. If no descriptor is available
- fails the request. When setting the completion routine we pass our
- Adapter Object as Context.
-
- Arguments:
-
- Return Value:
- TRUE found matched tuple cache
- FALSE no matched found
-
- Note:
-
- ========================================================================
-*/
-#define fRTMP_ADAPTER_NEED_STOP_RX \
- (fRTMP_ADAPTER_NIC_NOT_EXIST | fRTMP_ADAPTER_HALT_IN_PROGRESS | \
- fRTMP_ADAPTER_RADIO_OFF | fRTMP_ADAPTER_RESET_IN_PROGRESS | \
- fRTMP_ADAPTER_REMOVE_IN_PROGRESS | fRTMP_ADAPTER_BULKIN_RESET)
-
-#define fRTMP_ADAPTER_NEED_STOP_HANDLE_RX \
- (fRTMP_ADAPTER_NIC_NOT_EXIST | fRTMP_ADAPTER_HALT_IN_PROGRESS | \
- fRTMP_ADAPTER_RADIO_OFF | fRTMP_ADAPTER_RESET_IN_PROGRESS | \
- fRTMP_ADAPTER_REMOVE_IN_PROGRESS)
-
-void RTUSBBulkReceive(struct rt_rtmp_adapter *pAd)
-{
- struct rt_rx_context *pRxContext;
- unsigned long IrqFlags;
-
- /* sanity check */
- if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NEED_STOP_HANDLE_RX))
- return;
-
- while (1) {
-
- RTMP_IRQ_LOCK(&pAd->BulkInLock, IrqFlags);
- pRxContext = &(pAd->RxContext[pAd->NextRxBulkInReadIndex]);
- if (((pRxContext->InUse == FALSE)
- && (pRxContext->Readable == TRUE))
- && (pRxContext->bRxHandling == FALSE)) {
- pRxContext->bRxHandling = TRUE;
- RTMP_IRQ_UNLOCK(&pAd->BulkInLock, IrqFlags);
-
- /* read RxContext, Since not */
- STARxDoneInterruptHandle(pAd, TRUE);
-
- /* Finish to handle this bulkIn buffer. */
- RTMP_IRQ_LOCK(&pAd->BulkInLock, IrqFlags);
- pRxContext->BulkInOffset = 0;
- pRxContext->Readable = FALSE;
- pRxContext->bRxHandling = FALSE;
- pAd->ReadPosition = 0;
- pAd->TransferBufferLength = 0;
- INC_RING_INDEX(pAd->NextRxBulkInReadIndex,
- RX_RING_SIZE);
- RTMP_IRQ_UNLOCK(&pAd->BulkInLock, IrqFlags);
-
- } else {
- RTMP_IRQ_UNLOCK(&pAd->BulkInLock, IrqFlags);
- break;
- }
- }
-
- if (!(RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NEED_STOP_RX)))
- DoBulkIn(pAd);
-
-}
-
-/*
- ========================================================================
-
- Routine Description:
- This routine process Rx Irp and call rx complete function.
-
- Arguments:
- DeviceObject Pointer to the device object for next lower
- device. DeviceObject passed in here belongs to
- the next lower driver in the stack because we
- were invoked via IoCallDriver in USB_RxPacket
- AND it is not OUR device object
- Irp Ptr to completed IRP
- Context Ptr to our Adapter object (context specified
- in IoSetCompletionRoutine
-
- Return Value:
- Always returns STATUS_MORE_PROCESSING_REQUIRED
-
- Note:
- Always returns STATUS_MORE_PROCESSING_REQUIRED
- ========================================================================
-*/
-void RTUSBBulkRxComplete(struct urb *pUrb, struct pt_regs *pt_regs)
-{
- /* use a receive tasklet to handle received packets; */
- /* or sometimes hardware IRQ will be disabled here, so we can not */
- /* use spin_lock_bh()/spin_unlock_bh() after IRQ is disabled. :< */
- struct rt_rx_context *pRxContext;
- struct rt_rtmp_adapter *pAd;
- struct os_cookie *pObj;
-
- pRxContext = (struct rt_rx_context *)pUrb->context;
- pAd = pRxContext->pAd;
- pObj = (struct os_cookie *)pAd->OS_Cookie;
-
- pObj->rx_done_task.data = (unsigned long)pUrb;
- tasklet_hi_schedule(&pObj->rx_done_task);
-
-}
-
-/*
- ========================================================================
-
- Routine Description:
-
- Arguments:
-
- Return Value:
-
- Note:
-
- ========================================================================
-*/
-void RTUSBKickBulkOut(struct rt_rtmp_adapter *pAd)
-{
- /* BulkIn Reset will reset whole USB PHY. So we need to make sure fRTMP_ADAPTER_BULKIN_RESET not flaged. */
- if (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NEED_STOP_TX)
- ) {
- /* 2. PS-Poll frame is next */
- if (RTUSB_TEST_BULK_FLAG(pAd, fRTUSB_BULK_OUT_PSPOLL))
- RTUSBBulkOutPsPoll(pAd);
- /* 5. Mlme frame is next */
- else if ((RTUSB_TEST_BULK_FLAG(pAd, fRTUSB_BULK_OUT_MLME)) ||
- (pAd->MgmtRing.TxSwFreeIdx < MGMT_RING_SIZE)) {
- RTUSBBulkOutMLMEPacket(pAd, pAd->MgmtRing.TxDmaIdx);
- }
- /* 6. Data frame normal is next */
- if (RTUSB_TEST_BULK_FLAG(pAd, fRTUSB_BULK_OUT_DATA_NORMAL)) {
- if (((!RTMP_TEST_FLAG
- (pAd, fRTMP_ADAPTER_BSS_SCAN_IN_PROGRESS))
- ||
- (!OPSTATUS_TEST_FLAG
- (pAd, fOP_STATUS_MEDIA_STATE_CONNECTED))
- )) {
- RTUSBBulkOutDataPacket(pAd, 0,
- pAd->
- NextBulkOutIndex[0]);
- }
- }
- if (RTUSB_TEST_BULK_FLAG(pAd, fRTUSB_BULK_OUT_DATA_NORMAL_2)) {
- if (((!RTMP_TEST_FLAG
- (pAd, fRTMP_ADAPTER_BSS_SCAN_IN_PROGRESS))
- ||
- (!OPSTATUS_TEST_FLAG
- (pAd, fOP_STATUS_MEDIA_STATE_CONNECTED))
- )) {
- RTUSBBulkOutDataPacket(pAd, 1,
- pAd->
- NextBulkOutIndex[1]);
- }
- }
- if (RTUSB_TEST_BULK_FLAG(pAd, fRTUSB_BULK_OUT_DATA_NORMAL_3)) {
- if (((!RTMP_TEST_FLAG
- (pAd, fRTMP_ADAPTER_BSS_SCAN_IN_PROGRESS))
- ||
- (!OPSTATUS_TEST_FLAG
- (pAd, fOP_STATUS_MEDIA_STATE_CONNECTED))
- )) {
- RTUSBBulkOutDataPacket(pAd, 2,
- pAd->
- NextBulkOutIndex[2]);
- }
- }
- if (RTUSB_TEST_BULK_FLAG(pAd, fRTUSB_BULK_OUT_DATA_NORMAL_4)) {
- if (((!RTMP_TEST_FLAG
- (pAd, fRTMP_ADAPTER_BSS_SCAN_IN_PROGRESS))
- ||
- (!OPSTATUS_TEST_FLAG
- (pAd, fOP_STATUS_MEDIA_STATE_CONNECTED))
- )) {
- RTUSBBulkOutDataPacket(pAd, 3,
- pAd->
- NextBulkOutIndex[3]);
- }
- }
- /* 7. Null frame is the last */
- else if (RTUSB_TEST_BULK_FLAG(pAd, fRTUSB_BULK_OUT_DATA_NULL)) {
- if (!RTMP_TEST_FLAG
- (pAd, fRTMP_ADAPTER_BSS_SCAN_IN_PROGRESS)) {
- RTUSBBulkOutNullFrame(pAd);
- }
- }
- /* 8. No data available */
- else
- ;
- }
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Call from Reset action after BulkOut failed.
- Arguments:
-
- Return Value:
-
- Note:
-
- ========================================================================
-*/
-void RTUSBCleanUpDataBulkOutQueue(struct rt_rtmp_adapter *pAd)
-{
- u8 Idx;
- struct rt_ht_tx_context *pTxContext;
-
- DBGPRINT(RT_DEBUG_TRACE, ("--->CleanUpDataBulkOutQueue\n"));
-
- for (Idx = 0; Idx < 4; Idx++) {
- pTxContext = &pAd->TxContext[Idx];
-
- pTxContext->CurWritePosition = pTxContext->NextBulkOutPosition;
- pTxContext->LastOne = FALSE;
- NdisAcquireSpinLock(&pAd->BulkOutLock[Idx]);
- pAd->BulkOutPending[Idx] = FALSE;
- NdisReleaseSpinLock(&pAd->BulkOutLock[Idx]);
- }
-
- DBGPRINT(RT_DEBUG_TRACE, ("<---CleanUpDataBulkOutQueue\n"));
-}
-
-/*
- ========================================================================
-
- Routine Description:
-
- Arguments:
-
- Return Value:
-
- Note:
-
- ========================================================================
-*/
-void RTUSBCleanUpMLMEBulkOutQueue(struct rt_rtmp_adapter *pAd)
-{
- DBGPRINT(RT_DEBUG_TRACE, ("--->CleanUpMLMEBulkOutQueue\n"));
- DBGPRINT(RT_DEBUG_TRACE, ("<---CleanUpMLMEBulkOutQueue\n"));
-}
-
-/*
- ========================================================================
-
- Routine Description:
-
- Arguments:
-
- Return Value:
-
- Note:
-
- ========================================================================
-*/
-void RTUSBCancelPendingIRPs(struct rt_rtmp_adapter *pAd)
-{
- RTUSBCancelPendingBulkInIRP(pAd);
- RTUSBCancelPendingBulkOutIRP(pAd);
-}
-
-/*
- ========================================================================
-
- Routine Description:
-
- Arguments:
-
- Return Value:
-
- Note:
-
- ========================================================================
-*/
-void RTUSBCancelPendingBulkInIRP(struct rt_rtmp_adapter *pAd)
-{
- struct rt_rx_context *pRxContext;
- u32 i;
-
- DBGPRINT_RAW(RT_DEBUG_TRACE, ("--->RTUSBCancelPendingBulkInIRP\n"));
- for (i = 0; i < (RX_RING_SIZE); i++) {
- pRxContext = &(pAd->RxContext[i]);
- if (pRxContext->IRPPending == TRUE) {
- RTUSB_UNLINK_URB(pRxContext->pUrb);
- pRxContext->IRPPending = FALSE;
- pRxContext->InUse = FALSE;
- /*NdisInterlockedDecrement(&pAd->PendingRx); */
- /*pAd->PendingRx--; */
- }
- }
- DBGPRINT_RAW(RT_DEBUG_TRACE, ("<---RTUSBCancelPendingBulkInIRP\n"));
-}
-
-/*
- ========================================================================
-
- Routine Description:
-
- Arguments:
-
- Return Value:
-
- Note:
-
- ========================================================================
-*/
-void RTUSBCancelPendingBulkOutIRP(struct rt_rtmp_adapter *pAd)
-{
- struct rt_ht_tx_context *pHTTXContext;
- struct rt_tx_context *pMLMEContext;
- struct rt_tx_context *pBeaconContext;
- struct rt_tx_context *pNullContext;
- struct rt_tx_context *pPsPollContext;
- struct rt_tx_context *pRTSContext;
- u32 i, Idx;
-/* unsigned int IrqFlags; */
-/* spinlock_t *pLock; */
-/* BOOLEAN *pPending; */
-
-/* pLock = &pAd->BulkOutLock[MGMTPIPEIDX]; */
-/* pPending = &pAd->BulkOutPending[MGMTPIPEIDX]; */
-
- for (Idx = 0; Idx < 4; Idx++) {
- pHTTXContext = &(pAd->TxContext[Idx]);
-
- if (pHTTXContext->IRPPending == TRUE) {
-
- /* Get the USB_CONTEXT and cancel it's IRP; the completion routine will itself */
- /* remove it from the HeadPendingSendList and NULL out HeadPendingSendList */
- /* when the last IRP on the list has been cancelled; that's how we exit this loop */
- /* */
-
- RTUSB_UNLINK_URB(pHTTXContext->pUrb);
-
- /* Sleep 200 microseconds to give cancellation time to work */
- RTMPusecDelay(200);
- }
-
- pAd->BulkOutPending[Idx] = FALSE;
- }
-
- /*RTMP_IRQ_LOCK(pLock, IrqFlags); */
- for (i = 0; i < MGMT_RING_SIZE; i++) {
- pMLMEContext = (struct rt_tx_context *)pAd->MgmtRing.Cell[i].AllocVa;
- if (pMLMEContext && (pMLMEContext->IRPPending == TRUE)) {
-
- /* Get the USB_CONTEXT and cancel it's IRP; the completion routine will itself */
- /* remove it from the HeadPendingSendList and NULL out HeadPendingSendList */
- /* when the last IRP on the list has been cancelled; that's how we exit this loop */
- /* */
-
- RTUSB_UNLINK_URB(pMLMEContext->pUrb);
- pMLMEContext->IRPPending = FALSE;
-
- /* Sleep 200 microsecs to give cancellation time to work */
- RTMPusecDelay(200);
- }
- }
- pAd->BulkOutPending[MGMTPIPEIDX] = FALSE;
- /*RTMP_IRQ_UNLOCK(pLock, IrqFlags); */
-
- for (i = 0; i < BEACON_RING_SIZE; i++) {
- pBeaconContext = &(pAd->BeaconContext[i]);
-
- if (pBeaconContext->IRPPending == TRUE) {
-
- /* Get the USB_CONTEXT and cancel it's IRP; the completion routine will itself */
- /* remove it from the HeadPendingSendList and NULL out HeadPendingSendList */
- /* when the last IRP on the list has been cancelled; that's how we exit this loop */
- /* */
-
- RTUSB_UNLINK_URB(pBeaconContext->pUrb);
-
- /* Sleep 200 microsecs to give cancellation time to work */
- RTMPusecDelay(200);
- }
- }
-
- pNullContext = &(pAd->NullContext);
- if (pNullContext->IRPPending == TRUE)
- RTUSB_UNLINK_URB(pNullContext->pUrb);
-
- pRTSContext = &(pAd->RTSContext);
- if (pRTSContext->IRPPending == TRUE)
- RTUSB_UNLINK_URB(pRTSContext->pUrb);
-
- pPsPollContext = &(pAd->PsPollContext);
- if (pPsPollContext->IRPPending == TRUE)
- RTUSB_UNLINK_URB(pPsPollContext->pUrb);
-
- for (Idx = 0; Idx < 4; Idx++) {
- NdisAcquireSpinLock(&pAd->BulkOutLock[Idx]);
- pAd->BulkOutPending[Idx] = FALSE;
- NdisReleaseSpinLock(&pAd->BulkOutLock[Idx]);
- }
-}
-
-#endif /* RTMP_MAC_USB // */
diff --git a/drivers/staging/rt2870/common/rtusb_data.c b/drivers/staging/rt2870/common/rtusb_data.c
deleted file mode 100644
index 5b72bcd..0000000
--- a/drivers/staging/rt2870/common/rtusb_data.c
+++ /dev/null
@@ -1,262 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- rtusb_data.c
-
- Abstract:
- Ralink USB driver Tx/Rx functions.
-
- Revision History:
- Who When What
- -------- ---------- ----------------------------------------------
- Jan 03-25-2006 created
-
-*/
-
-#ifdef RTMP_MAC_USB
-
-#include "../rt_config.h"
-
-extern u8 Phy11BGNextRateUpward[]; /* defined in mlme.c */
-extern u8 EpToQueue[];
-
-void REPORT_AMSDU_FRAMES_TO_LLC(struct rt_rtmp_adapter *pAd,
- u8 *pData, unsigned long DataSize)
-{
- void *pPacket;
- u32 nMSDU;
- struct sk_buff *pSkb;
-
- nMSDU = 0;
- /* allocate a rx packet */
- pSkb = dev_alloc_skb(RX_BUFFER_AGGRESIZE);
- pPacket = (void *)OSPKT_TO_RTPKT(pSkb);
- if (pSkb) {
-
- /* convert 802.11 to 802.3 packet */
- pSkb->dev = get_netdev_from_bssid(pAd, BSS0);
- RTMP_SET_PACKET_SOURCE(pPacket, PKTSRC_NDIS);
- deaggregate_AMSDU_announce(pAd, pPacket, pData, DataSize);
- } else {
- DBGPRINT(RT_DEBUG_ERROR, ("Can't allocate skb\n"));
- }
-}
-
-/*
- ========================================================================
-
- Routine Description:
- This subroutine will scan through releative ring descriptor to find
- out available free ring descriptor and compare with request size.
-
- Arguments:
- pAd Pointer to our adapter
- RingType Selected Ring
-
- Return Value:
- NDIS_STATUS_FAILURE Not enough free descriptor
- NDIS_STATUS_SUCCESS Enough free descriptor
-
- Note:
-
- ========================================================================
-*/
-int RTUSBFreeDescriptorRequest(struct rt_rtmp_adapter *pAd,
- u8 BulkOutPipeId,
- u32 NumberRequired)
-{
-/* u8 FreeNumber = 0; */
-/* u32 Index; */
- int Status = NDIS_STATUS_FAILURE;
- unsigned long IrqFlags;
- struct rt_ht_tx_context *pHTTXContext;
-
- pHTTXContext = &pAd->TxContext[BulkOutPipeId];
- RTMP_IRQ_LOCK(&pAd->TxContextQueueLock[BulkOutPipeId], IrqFlags);
- if ((pHTTXContext->CurWritePosition < pHTTXContext->NextBulkOutPosition)
- &&
- ((pHTTXContext->CurWritePosition + NumberRequired +
- LOCAL_TXBUF_SIZE) > pHTTXContext->NextBulkOutPosition)) {
-
- RTUSB_SET_BULK_FLAG(pAd,
- (fRTUSB_BULK_OUT_DATA_NORMAL <<
- BulkOutPipeId));
- } else if ((pHTTXContext->CurWritePosition == 8)
- && (pHTTXContext->NextBulkOutPosition <
- (NumberRequired + LOCAL_TXBUF_SIZE))) {
- RTUSB_SET_BULK_FLAG(pAd,
- (fRTUSB_BULK_OUT_DATA_NORMAL <<
- BulkOutPipeId));
- } else if (pHTTXContext->bCurWriting == TRUE) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("RTUSBFreeD c3 --> QueIdx=%d, CWPos=%ld, NBOutPos=%ld!\n",
- BulkOutPipeId, pHTTXContext->CurWritePosition,
- pHTTXContext->NextBulkOutPosition));
- RTUSB_SET_BULK_FLAG(pAd,
- (fRTUSB_BULK_OUT_DATA_NORMAL <<
- BulkOutPipeId));
- } else {
- Status = NDIS_STATUS_SUCCESS;
- }
- RTMP_IRQ_UNLOCK(&pAd->TxContextQueueLock[BulkOutPipeId], IrqFlags);
-
- return Status;
-}
-
-int RTUSBFreeDescriptorRelease(struct rt_rtmp_adapter *pAd,
- u8 BulkOutPipeId)
-{
- unsigned long IrqFlags;
- struct rt_ht_tx_context *pHTTXContext;
-
- pHTTXContext = &pAd->TxContext[BulkOutPipeId];
- RTMP_IRQ_LOCK(&pAd->TxContextQueueLock[BulkOutPipeId], IrqFlags);
- pHTTXContext->bCurWriting = FALSE;
- RTMP_IRQ_UNLOCK(&pAd->TxContextQueueLock[BulkOutPipeId], IrqFlags);
-
- return NDIS_STATUS_SUCCESS;
-}
-
-BOOLEAN RTUSBNeedQueueBackForAgg(struct rt_rtmp_adapter *pAd, u8 BulkOutPipeId)
-{
- unsigned long IrqFlags;
- struct rt_ht_tx_context *pHTTXContext;
- BOOLEAN needQueBack = FALSE;
-
- pHTTXContext = &pAd->TxContext[BulkOutPipeId];
-
- RTMP_IRQ_LOCK(&pAd->TxContextQueueLock[BulkOutPipeId], IrqFlags);
- if ((pHTTXContext->IRPPending ==
- TRUE) /*&& (pAd->TxSwQueue[BulkOutPipeId].Number == 0) */) {
- if ((pHTTXContext->CurWritePosition <
- pHTTXContext->ENextBulkOutPosition)
- &&
- (((pHTTXContext->ENextBulkOutPosition +
- MAX_AGGREGATION_SIZE) < MAX_TXBULK_LIMIT)
- || (pHTTXContext->CurWritePosition >
- MAX_AGGREGATION_SIZE))) {
- needQueBack = TRUE;
- } else
- if ((pHTTXContext->CurWritePosition >
- pHTTXContext->ENextBulkOutPosition)
- &&
- ((pHTTXContext->ENextBulkOutPosition +
- MAX_AGGREGATION_SIZE) <
- pHTTXContext->CurWritePosition)) {
- needQueBack = TRUE;
- }
- }
- RTMP_IRQ_UNLOCK(&pAd->TxContextQueueLock[BulkOutPipeId], IrqFlags);
-
- return needQueBack;
-
-}
-
-/*
- ========================================================================
-
- Routine Description:
-
- Arguments:
-
- Return Value:
-
- IRQL =
-
- Note:
-
- ========================================================================
-*/
-void RTUSBRejectPendingPackets(struct rt_rtmp_adapter *pAd)
-{
- u8 Index;
- struct rt_queue_entry *pEntry;
- void *pPacket;
- struct rt_queue_header *pQueue;
-
- for (Index = 0; Index < 4; Index++) {
- NdisAcquireSpinLock(&pAd->TxSwQueueLock[Index]);
- while (pAd->TxSwQueue[Index].Head != NULL) {
- pQueue = (struct rt_queue_header *)&(pAd->TxSwQueue[Index]);
- pEntry = RemoveHeadQueue(pQueue);
- pPacket = QUEUE_ENTRY_TO_PACKET(pEntry);
- RELEASE_NDIS_PACKET(pAd, pPacket, NDIS_STATUS_FAILURE);
- }
- NdisReleaseSpinLock(&pAd->TxSwQueueLock[Index]);
-
- }
-
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Calculates the duration which is required to transmit out frames
- with given size and specified rate.
-
- Arguments:
- pTxD Pointer to transmit descriptor
- Ack Setting for Ack requirement bit
- Fragment Setting for Fragment bit
- RetryMode Setting for retry mode
- Ifs Setting for IFS gap
- Rate Setting for transmit rate
- Service Setting for service
- Length Frame length
- TxPreamble Short or Long preamble when using CCK rates
- QueIdx - 0-3, according to 802.11e/d4.4 June/2003
-
- Return Value:
- None
-
- IRQL = PASSIVE_LEVEL
- IRQL = DISPATCH_LEVEL
-
- ========================================================================
-*/
-
-void RTMPWriteTxInfo(struct rt_rtmp_adapter *pAd,
- struct rt_txinfo *pTxInfo,
- u16 USBDMApktLen,
- IN BOOLEAN bWiv,
- u8 QueueSel, u8 NextValid, u8 TxBurst)
-{
- pTxInfo->USBDMATxPktLen = USBDMApktLen;
- pTxInfo->QSEL = QueueSel;
- if (QueueSel != FIFO_EDCA)
- DBGPRINT(RT_DEBUG_TRACE,
- ("====> QueueSel != FIFO_EDCA<============\n"));
- pTxInfo->USBDMANextVLD = FALSE; /*NextValid; // Need to check with Jan about this. */
- pTxInfo->USBDMATxburst = TxBurst;
- pTxInfo->WIV = bWiv;
- pTxInfo->SwUseLastRound = 0;
- pTxInfo->rsv = 0;
- pTxInfo->rsv2 = 0;
-}
-
-#endif /* RTMP_MAC_USB // */
diff --git a/drivers/staging/rt2870/common/rtusb_io.c b/drivers/staging/rt2870/common/rtusb_io.c
deleted file mode 100644
index 7d2f7e0..0000000
--- a/drivers/staging/rt2870/common/rtusb_io.c
+++ /dev/null
@@ -1,2104 +0,0 @@
-/*
- *************************************************************************
- * Ralink Tech Inc.
- * 5F., No.36, Taiyuan St., Jhubei City,
- * Hsinchu County 302,
- * Taiwan, R.O.C.
- *
- * (c) Copyright 2002-2007, Ralink Technology, Inc.
- *
- * This program is free software; you can redistribute it and/or modify *
- * it under the terms of the GNU General Public License as published by *
- * the Free Software Foundation; either version 2 of the License, or *
- * (at your option) any later version. *
- * *
- * This program is distributed in the hope that it will be useful, *
- * but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
- * GNU General Public License for more details. *
- * *
- * You should have received a copy of the GNU General Public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
- * *
- *************************************************************************
-
- Module Name:
- rtusb_io.c
-
- Abstract:
-
- Revision History:
- Who When What
- -------- ---------- ----------------------------------------------
- Name Date Modification logs
- Paul Lin 06-25-2004 created
-*/
-
-#ifdef RTMP_MAC_USB
-
-#include "../rt_config.h"
-
-/*
- ========================================================================
-
- Routine Description: NIC initialization complete
-
- Arguments:
-
- Return Value:
-
- IRQL =
-
- Note:
-
- ========================================================================
-*/
-
-static int RTUSBFirmwareRun(struct rt_rtmp_adapter *pAd)
-{
- int Status;
-
- Status = RTUSB_VendorRequest(pAd,
- USBD_TRANSFER_DIRECTION_OUT,
- DEVICE_VENDOR_REQUEST_OUT,
- 0x01, 0x8, 0, NULL, 0);
-
- return Status;
-}
-
-/*
- ========================================================================
-
- Routine Description: Write Firmware to NIC.
-
- Arguments:
-
- Return Value:
-
- IRQL =
-
- Note:
-
- ========================================================================
-*/
-int RTUSBFirmwareWrite(struct rt_rtmp_adapter *pAd,
- const u8 *pFwImage, unsigned long FwLen)
-{
- u32 MacReg;
- int Status;
-/* unsigned long i; */
- u16 writeLen;
-
- Status = RTUSBReadMACRegister(pAd, MAC_CSR0, &MacReg);
-
- writeLen = FwLen;
- RTUSBMultiWrite(pAd, FIRMWARE_IMAGE_BASE, pFwImage, writeLen);
-
- Status = RTUSBWriteMACRegister(pAd, 0x7014, 0xffffffff);
- Status = RTUSBWriteMACRegister(pAd, 0x701c, 0xffffffff);
- Status = RTUSBFirmwareRun(pAd);
-
- /*2008/11/28:KH add to fix the dead rf frequency offset bug<-- */
- RTMPusecDelay(10000);
- RTUSBWriteMACRegister(pAd, H2M_MAILBOX_CSR, 0);
- AsicSendCommandToMcu(pAd, 0x72, 0x00, 0x00, 0x00); /*reset rf by MCU supported by new firmware */
- /*2008/11/28:KH add to fix the dead rf frequency offset bug--> */
-
- return Status;
-}
-
-int RTUSBVenderReset(struct rt_rtmp_adapter *pAd)
-{
- int Status;
- DBGPRINT_RAW(RT_DEBUG_ERROR, ("-->RTUSBVenderReset\n"));
- Status = RTUSB_VendorRequest(pAd,
- USBD_TRANSFER_DIRECTION_OUT,
- DEVICE_VENDOR_REQUEST_OUT,
- 0x01, 0x1, 0, NULL, 0);
-
- DBGPRINT_RAW(RT_DEBUG_ERROR, ("<--RTUSBVenderReset\n"));
- return Status;
-}
-
-/*
- ========================================================================
-
- Routine Description: Read various length data from RT2573
-
- Arguments:
-
- Return Value:
-
- IRQL =
-
- Note:
-
- ========================================================================
-*/
-int RTUSBMultiRead(struct rt_rtmp_adapter *pAd,
- u16 Offset, u8 *pData, u16 length)
-{
- int Status;
-
- Status = RTUSB_VendorRequest(pAd,
- (USBD_TRANSFER_DIRECTION_IN |
- USBD_SHORT_TRANSFER_OK),
- DEVICE_VENDOR_REQUEST_IN, 0x7, 0, Offset,
- pData, length);
-
- return Status;
-}
-
-/*
- ========================================================================
-
- Routine Description: Write various length data to RT2573
-
- Arguments:
-
- Return Value:
-
- IRQL =
-
- Note:
-
- ========================================================================
-*/
-int RTUSBMultiWrite_OneByte(struct rt_rtmp_adapter *pAd,
- u16 Offset, const u8 *pData)
-{
- int Status;
-
- /* TODO: In 2870, use this funciton carefully cause it's not stable. */
- Status = RTUSB_VendorRequest(pAd,
- USBD_TRANSFER_DIRECTION_OUT,
- DEVICE_VENDOR_REQUEST_OUT,
- 0x6, 0, Offset, (u8 *)pData, 1);
-
- return Status;
-}
-
-int RTUSBMultiWrite(struct rt_rtmp_adapter *pAd,
- u16 Offset, const u8 *pData, u16 length)
-{
- int Status;
-
- u16 index = 0, Value;
- const u8 *pSrc = pData;
- u16 resude = 0;
-
- resude = length % 2;
- length += resude;
- do {
- Value = (u16)(*pSrc | (*(pSrc + 1) << 8));
- Status = RTUSBSingleWrite(pAd, Offset + index, Value);
- index += 2;
- length -= 2;
- pSrc = pSrc + 2;
- } while (length > 0);
-
- return Status;
-}
-
-int RTUSBSingleWrite(struct rt_rtmp_adapter *pAd,
- u16 Offset, u16 Value)
-{
- int Status;
-
- Status = RTUSB_VendorRequest(pAd,
- USBD_TRANSFER_DIRECTION_OUT,
- DEVICE_VENDOR_REQUEST_OUT,
- 0x2, Value, Offset, NULL, 0);
-
- return Status;
-
-}
-
-/*
- ========================================================================
-
- Routine Description: Read 32-bit MAC register
-
- Arguments:
-
- Return Value:
-
- IRQL =
-
- Note:
-
- ========================================================================
-*/
-int RTUSBReadMACRegister(struct rt_rtmp_adapter *pAd,
- u16 Offset, u32 *pValue)
-{
- int Status = 0;
- u32 localVal;
-
- Status = RTUSB_VendorRequest(pAd,
- (USBD_TRANSFER_DIRECTION_IN |
- USBD_SHORT_TRANSFER_OK),
- DEVICE_VENDOR_REQUEST_IN, 0x7, 0, Offset,
- &localVal, 4);
-
- *pValue = le2cpu32(localVal);
-
- if (Status < 0)
- *pValue = 0xffffffff;
-
- return Status;
-}
-
-/*
- ========================================================================
-
- Routine Description: Write 32-bit MAC register
-
- Arguments:
-
- Return Value:
-
- IRQL =
-
- Note:
-
- ========================================================================
-*/
-int RTUSBWriteMACRegister(struct rt_rtmp_adapter *pAd,
- u16 Offset, u32 Value)
-{
- int Status;
- u32 localVal;
-
- localVal = Value;
-
- Status = RTUSBSingleWrite(pAd, Offset, (u16)(localVal & 0xffff));
- Status =
- RTUSBSingleWrite(pAd, Offset + 2,
- (u16)((localVal & 0xffff0000) >> 16));
-
- return Status;
-}
-
-/*
- ========================================================================
-
- Routine Description: Read 8-bit BBP register
-
- Arguments:
-
- Return Value:
-
- IRQL =
-
- Note:
-
- ========================================================================
-*/
-int RTUSBReadBBPRegister(struct rt_rtmp_adapter *pAd,
- u8 Id, u8 *pValue)
-{
- BBP_CSR_CFG_STRUC BbpCsr;
- u32 i = 0;
- int status;
-
- /* Verify the busy condition */
- do {
- status = RTUSBReadMACRegister(pAd, BBP_CSR_CFG, &BbpCsr.word);
- if (status >= 0) {
- if (!(BbpCsr.field.Busy == BUSY))
- break;
- }
- DBGPRINT(RT_DEBUG_TRACE,
- ("RTUSBReadBBPRegister(BBP_CSR_CFG_1):retry count=%d!\n",
- i));
- i++;
- } while ((i < RETRY_LIMIT)
- && (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST)));
-
- if ((i == RETRY_LIMIT)
- || (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST))) {
- /* */
- /* Read failed then Return Default value. */
- /* */
- *pValue = pAd->BbpWriteLatch[Id];
-
- DBGPRINT_RAW(RT_DEBUG_ERROR,
- ("Retry count exhausted or device removed!!!\n"));
- return STATUS_UNSUCCESSFUL;
- }
- /* Prepare for write material */
- BbpCsr.word = 0;
- BbpCsr.field.fRead = 1;
- BbpCsr.field.Busy = 1;
- BbpCsr.field.RegNum = Id;
- RTUSBWriteMACRegister(pAd, BBP_CSR_CFG, BbpCsr.word);
-
- i = 0;
- /* Verify the busy condition */
- do {
- status = RTUSBReadMACRegister(pAd, BBP_CSR_CFG, &BbpCsr.word);
- if (status >= 0) {
- if (!(BbpCsr.field.Busy == BUSY)) {
- *pValue = (u8)BbpCsr.field.Value;
- break;
- }
- }
- DBGPRINT(RT_DEBUG_TRACE,
- ("RTUSBReadBBPRegister(BBP_CSR_CFG_2):retry count=%d!\n",
- i));
- i++;
- } while ((i < RETRY_LIMIT)
- && (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST)));
-
- if ((i == RETRY_LIMIT)
- || (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST))) {
- /* */
- /* Read failed then Return Default value. */
- /* */
- *pValue = pAd->BbpWriteLatch[Id];
-
- DBGPRINT_RAW(RT_DEBUG_ERROR,
- ("Retry count exhausted or device removed!!!\n"));
- return STATUS_UNSUCCESSFUL;
- }
-
- return STATUS_SUCCESS;
-}
-
-/*
- ========================================================================
-
- Routine Description: Write 8-bit BBP register
-
- Arguments:
-
- Return Value:
-
- IRQL =
-
- Note:
-
- ========================================================================
-*/
-int RTUSBWriteBBPRegister(struct rt_rtmp_adapter *pAd,
- u8 Id, u8 Value)
-{
- BBP_CSR_CFG_STRUC BbpCsr;
- u32 i = 0;
- int status;
- /* Verify the busy condition */
- do {
- status = RTUSBReadMACRegister(pAd, BBP_CSR_CFG, &BbpCsr.word);
- if (status >= 0) {
- if (!(BbpCsr.field.Busy == BUSY))
- break;
- }
- DBGPRINT(RT_DEBUG_TRACE,
- ("RTUSBWriteBBPRegister(BBP_CSR_CFG):retry count=%d!\n",
- i));
- i++;
- } while ((i < RETRY_LIMIT)
- && (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST)));
-
- if ((i == RETRY_LIMIT)
- || (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST))) {
- DBGPRINT_RAW(RT_DEBUG_ERROR,
- ("Retry count exhausted or device removed!!!\n"));
- return STATUS_UNSUCCESSFUL;
- }
- /* Prepare for write material */
- BbpCsr.word = 0;
- BbpCsr.field.fRead = 0;
- BbpCsr.field.Value = Value;
- BbpCsr.field.Busy = 1;
- BbpCsr.field.RegNum = Id;
- RTUSBWriteMACRegister(pAd, BBP_CSR_CFG, BbpCsr.word);
-
- pAd->BbpWriteLatch[Id] = Value;
-
- return STATUS_SUCCESS;
-}
-
-/*
- ========================================================================
-
- Routine Description: Write RF register through MAC
-
- Arguments:
-
- Return Value:
-
- IRQL =
-
- Note:
-
- ========================================================================
-*/
-int RTUSBWriteRFRegister(struct rt_rtmp_adapter *pAd, u32 Value)
-{
- PHY_CSR4_STRUC PhyCsr4;
- u32 i = 0;
- int status;
-
- NdisZeroMemory(&PhyCsr4, sizeof(PHY_CSR4_STRUC));
- do {
- status = RTUSBReadMACRegister(pAd, RF_CSR_CFG0, &PhyCsr4.word);
- if (status >= 0) {
- if (!(PhyCsr4.field.Busy))
- break;
- }
- DBGPRINT(RT_DEBUG_TRACE,
- ("RTUSBWriteRFRegister(RF_CSR_CFG0):retry count=%d!\n",
- i));
- i++;
- } while ((i < RETRY_LIMIT)
- && (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST)));
-
- if ((i == RETRY_LIMIT)
- || (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST))) {
- DBGPRINT_RAW(RT_DEBUG_ERROR,
- ("Retry count exhausted or device removed!!!\n"));
- return STATUS_UNSUCCESSFUL;
- }
-
- RTUSBWriteMACRegister(pAd, RF_CSR_CFG0, Value);
-
- return STATUS_SUCCESS;
-}
-
-/*
- ========================================================================
-
- Routine Description:
-
- Arguments:
-
- Return Value:
-
- IRQL =
-
- Note:
-
- ========================================================================
-*/
-int RTUSBReadEEPROM(struct rt_rtmp_adapter *pAd,
- u16 Offset, u8 *pData, u16 length)
-{
- int Status = STATUS_SUCCESS;
-
- Status = RTUSB_VendorRequest(pAd,
- (USBD_TRANSFER_DIRECTION_IN |
- USBD_SHORT_TRANSFER_OK),
- DEVICE_VENDOR_REQUEST_IN, 0x9, 0, Offset,
- pData, length);
-
- return Status;
-}
-
-/*
- ========================================================================
-
- Routine Description:
-
- Arguments:
-
- Return Value:
-
- IRQL =
-
- Note:
-
- ========================================================================
-*/
-int RTUSBWriteEEPROM(struct rt_rtmp_adapter *pAd,
- u16 Offset, u8 *pData, u16 length)
-{
- int Status = STATUS_SUCCESS;
-
- Status = RTUSB_VendorRequest(pAd,
- USBD_TRANSFER_DIRECTION_OUT,
- DEVICE_VENDOR_REQUEST_OUT,
- 0x8, 0, Offset, pData, length);
-
- return Status;
-}
-
-int RTUSBReadEEPROM16(struct rt_rtmp_adapter *pAd,
- u16 offset, u16 *pData)
-{
- int status;
- u16 localData;
-
- status = RTUSBReadEEPROM(pAd, offset, (u8 *)(&localData), 2);
- if (status == STATUS_SUCCESS)
- *pData = le2cpu16(localData);
-
- return status;
-
-}
-
-/*
- ========================================================================
-
- Routine Description:
-
- Arguments:
-
- Return Value:
-
- IRQL =
-
- Note:
-
- ========================================================================
-*/
-void RTUSBPutToSleep(struct rt_rtmp_adapter *pAd)
-{
- u32 value;
-
- /* Timeout 0x40 x 50us */
- value = (SLEEPCID << 16) + (OWNERMCU << 24) + (0x40 << 8) + 1;
- RTUSBWriteMACRegister(pAd, 0x7010, value);
- RTUSBWriteMACRegister(pAd, 0x404, 0x30);
- /*RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS); */
- DBGPRINT_RAW(RT_DEBUG_ERROR, ("Sleep Mailbox testvalue %x\n", value));
-
-}
-
-/*
- ========================================================================
-
- Routine Description:
-
- Arguments:
-
- Return Value:
-
- IRQL =
-
- Note:
-
- ========================================================================
-*/
-int RTUSBWakeUp(struct rt_rtmp_adapter *pAd)
-{
- int Status;
-
- Status = RTUSB_VendorRequest(pAd,
- USBD_TRANSFER_DIRECTION_OUT,
- DEVICE_VENDOR_REQUEST_OUT,
- 0x01, 0x09, 0, NULL, 0);
-
- return Status;
-}
-
-/*
- ========================================================================
-
- Routine Description:
-
- Arguments:
-
- Return Value:
-
- IRQL =
-
- Note:
-
- ========================================================================
-*/
-void RTUSBInitializeCmdQ(struct rt_cmdq *cmdq)
-{
- cmdq->head = NULL;
- cmdq->tail = NULL;
- cmdq->size = 0;
- cmdq->CmdQState = RTMP_TASK_STAT_INITED;
-}
-
-/*
- ========================================================================
-
- Routine Description:
-
- Arguments:
-
- Return Value:
-
- IRQL =
-
- Note:
-
- ========================================================================
-*/
-int RTUSBEnqueueCmdFromNdis(struct rt_rtmp_adapter *pAd,
- IN NDIS_OID Oid,
- IN BOOLEAN SetInformation,
- void *pInformationBuffer,
- u32 InformationBufferLength)
-{
- int status;
- struct rt_cmdqelmt *cmdqelmt = NULL;
- struct rt_rtmp_os_task *pTask = &pAd->cmdQTask;
-
-#ifdef KTHREAD_SUPPORT
- if (pTask->kthread_task == NULL)
-#else
- CHECK_PID_LEGALITY(pTask->taskPID) {
- }
- else
-#endif
- return NDIS_STATUS_RESOURCES;
-
- status = os_alloc_mem(pAd, (u8 **) (&cmdqelmt), sizeof(struct rt_cmdqelmt));
- if ((status != NDIS_STATUS_SUCCESS) || (cmdqelmt == NULL))
- return NDIS_STATUS_RESOURCES;
-
- cmdqelmt->buffer = NULL;
- if (pInformationBuffer != NULL) {
- status =
- os_alloc_mem(pAd, (u8 **) & cmdqelmt->buffer,
- InformationBufferLength);
- if ((status != NDIS_STATUS_SUCCESS)
- || (cmdqelmt->buffer == NULL)) {
- kfree(cmdqelmt);
- return NDIS_STATUS_RESOURCES;
- } else {
- NdisMoveMemory(cmdqelmt->buffer, pInformationBuffer,
- InformationBufferLength);
- cmdqelmt->bufferlength = InformationBufferLength;
- }
- } else
- cmdqelmt->bufferlength = 0;
-
- cmdqelmt->command = Oid;
- cmdqelmt->CmdFromNdis = TRUE;
- if (SetInformation == TRUE)
- cmdqelmt->SetOperation = TRUE;
- else
- cmdqelmt->SetOperation = FALSE;
-
- NdisAcquireSpinLock(&pAd->CmdQLock);
- if (pAd->CmdQ.CmdQState & RTMP_TASK_CAN_DO_INSERT) {
- EnqueueCmd((&pAd->CmdQ), cmdqelmt);
- status = NDIS_STATUS_SUCCESS;
- } else {
- status = NDIS_STATUS_FAILURE;
- }
- NdisReleaseSpinLock(&pAd->CmdQLock);
-
- if (status == NDIS_STATUS_FAILURE) {
- if (cmdqelmt->buffer)
- os_free_mem(pAd, cmdqelmt->buffer);
- os_free_mem(pAd, cmdqelmt);
- } else
- RTUSBCMDUp(pAd);
-
- return NDIS_STATUS_SUCCESS;
-}
-
-/*
- ========================================================================
-
- Routine Description:
-
- Arguments:
-
- Return Value:
-
- IRQL =
-
- Note:
-
- ========================================================================
-*/
-int RTUSBEnqueueInternalCmd(struct rt_rtmp_adapter *pAd,
- IN NDIS_OID Oid,
- void *pInformationBuffer,
- u32 InformationBufferLength)
-{
- int status;
- struct rt_cmdqelmt *cmdqelmt = NULL;
-
- status = os_alloc_mem(pAd, (u8 **) & cmdqelmt, sizeof(struct rt_cmdqelmt));
- if ((status != NDIS_STATUS_SUCCESS) || (cmdqelmt == NULL))
- return NDIS_STATUS_RESOURCES;
- NdisZeroMemory(cmdqelmt, sizeof(struct rt_cmdqelmt));
-
- if (InformationBufferLength > 0) {
- status =
- os_alloc_mem(pAd, (u8 **) & cmdqelmt->buffer,
- InformationBufferLength);
- if ((status != NDIS_STATUS_SUCCESS)
- || (cmdqelmt->buffer == NULL)) {
- os_free_mem(pAd, cmdqelmt);
- return NDIS_STATUS_RESOURCES;
- } else {
- NdisMoveMemory(cmdqelmt->buffer, pInformationBuffer,
- InformationBufferLength);
- cmdqelmt->bufferlength = InformationBufferLength;
- }
- } else {
- cmdqelmt->buffer = NULL;
- cmdqelmt->bufferlength = 0;
- }
-
- cmdqelmt->command = Oid;
- cmdqelmt->CmdFromNdis = FALSE;
-
- if (cmdqelmt != NULL) {
- NdisAcquireSpinLock(&pAd->CmdQLock);
- if (pAd->CmdQ.CmdQState & RTMP_TASK_CAN_DO_INSERT) {
- EnqueueCmd((&pAd->CmdQ), cmdqelmt);
- status = NDIS_STATUS_SUCCESS;
- } else {
- status = NDIS_STATUS_FAILURE;
- }
- NdisReleaseSpinLock(&pAd->CmdQLock);
-
- if (status == NDIS_STATUS_FAILURE) {
- if (cmdqelmt->buffer)
- os_free_mem(pAd, cmdqelmt->buffer);
- os_free_mem(pAd, cmdqelmt);
- } else
- RTUSBCMDUp(pAd);
- }
- return NDIS_STATUS_SUCCESS;
-}
-
-/*
- ========================================================================
-
- Routine Description:
-
- Arguments:
-
- Return Value:
-
- IRQL =
-
- Note:
-
- ========================================================================
-*/
-void RTUSBDequeueCmd(struct rt_cmdq *cmdq, struct rt_cmdqelmt * * pcmdqelmt)
-{
- *pcmdqelmt = cmdq->head;
-
- if (*pcmdqelmt != NULL) {
- cmdq->head = cmdq->head->next;
- cmdq->size--;
- if (cmdq->size == 0)
- cmdq->tail = NULL;
- }
-}
-
-/*
- ========================================================================
- usb_control_msg - Builds a control urb, sends it off and waits for completion
- @dev: pointer to the usb device to send the message to
- @pipe: endpoint "pipe" to send the message to
- @request: USB message request value
- @requesttype: USB message request type value
- @value: USB message value
- @index: USB message index value
- @data: pointer to the data to send
- @size: length in bytes of the data to send
- @timeout: time in jiffies to wait for the message to complete before
- timing out (if 0 the wait is forever)
- Context: !in_interrupt ()
-
- This function sends a simple control message to a specified endpoint
- and waits for the message to complete, or timeout.
- If successful, it returns the number of bytes transferred, otherwise a negative error number.
-
- Don't use this function from within an interrupt context, like a
- bottom half handler. If you need an asynchronous message, or need to send
- a message from within interrupt context, use usb_submit_urb()
- If a thread in your driver uses this call, make sure your disconnect()
- method can wait for it to complete. Since you don't have a handle on
- the URB used, you can't cancel the request.
-
- Routine Description:
-
- Arguments:
-
- Return Value:
-
- Note:
-
- ========================================================================
-*/
-int RTUSB_VendorRequest(struct rt_rtmp_adapter *pAd,
- u32 TransferFlags,
- u8 RequestType,
- u8 Request,
- u16 Value,
- u16 Index,
- void *TransferBuffer,
- u32 TransferBufferLength)
-{
- int ret = 0;
- struct os_cookie *pObj = (struct os_cookie *)pAd->OS_Cookie;
-
- if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST)) {
- DBGPRINT(RT_DEBUG_ERROR, ("device disconnected\n"));
- return -1;
- } else if (in_interrupt()) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("in_interrupt, RTUSB_VendorRequest Request%02x Value%04x Offset%04x\n",
- Request, Value, Index));
-
- return -1;
- } else {
-#define MAX_RETRY_COUNT 10
-
- int retryCount = 0;
- void *tmpBuf = TransferBuffer;
-
- ret = down_interruptible(&(pAd->UsbVendorReq_semaphore));
- if (pAd->UsbVendorReqBuf) {
- ASSERT(TransferBufferLength < MAX_PARAM_BUFFER_SIZE);
-
- tmpBuf = (void *)pAd->UsbVendorReqBuf;
- NdisZeroMemory(pAd->UsbVendorReqBuf,
- TransferBufferLength);
-
- if (RequestType == DEVICE_VENDOR_REQUEST_OUT)
- NdisMoveMemory(tmpBuf, TransferBuffer,
- TransferBufferLength);
- }
-
- do {
- if (RequestType == DEVICE_VENDOR_REQUEST_OUT)
- ret =
- usb_control_msg(pObj->pUsb_Dev,
- usb_sndctrlpipe(pObj->
- pUsb_Dev,
- 0), Request,
- RequestType, Value, Index,
- tmpBuf,
- TransferBufferLength,
- CONTROL_TIMEOUT_JIFFIES);
- else if (RequestType == DEVICE_VENDOR_REQUEST_IN)
- ret =
- usb_control_msg(pObj->pUsb_Dev,
- usb_rcvctrlpipe(pObj->
- pUsb_Dev,
- 0), Request,
- RequestType, Value, Index,
- tmpBuf,
- TransferBufferLength,
- CONTROL_TIMEOUT_JIFFIES);
- else {
- DBGPRINT(RT_DEBUG_ERROR,
- ("vendor request direction is failed\n"));
- ret = -1;
- }
-
- retryCount++;
- if (ret < 0) {
- DBGPRINT(RT_DEBUG_OFF, ("#\n"));
- RTMPusecDelay(5000);
- }
- } while ((ret < 0) && (retryCount < MAX_RETRY_COUNT));
-
- if ((pAd->UsbVendorReqBuf)
- && (RequestType == DEVICE_VENDOR_REQUEST_IN))
- NdisMoveMemory(TransferBuffer, tmpBuf,
- TransferBufferLength);
- up(&(pAd->UsbVendorReq_semaphore));
-
- if (ret < 0) {
- DBGPRINT(RT_DEBUG_ERROR,
- ("RTUSB_VendorRequest failed(%d),TxFlags=0x%x, ReqType=%s, Req=0x%x, Index=0x%x\n",
- ret, TransferFlags,
- (RequestType ==
- DEVICE_VENDOR_REQUEST_OUT ? "OUT" : "IN"),
- Request, Index));
- if (Request == 0x2)
- DBGPRINT(RT_DEBUG_ERROR,
- ("\tRequest Value=0x%04x!\n", Value));
-
- if ((TransferBuffer != NULL)
- && (TransferBufferLength > 0))
- hex_dump("Failed TransferBuffer value",
- TransferBuffer, TransferBufferLength);
- }
-
- }
-
- if (ret != -1)
- return STATUS_SUCCESS;
- else
- return STATUS_UNSUCCESSFUL;
-}
-
-/*
- ========================================================================
-
- Routine Description:
- Creates an IRP to submite an IOCTL_INTERNAL_USB_RESET_PORT
- synchronously. Callers of this function must be running at
- PASSIVE LEVEL.
-
- Arguments:
-
- Return Value:
-
- Note:
-
- ========================================================================
-*/
-int RTUSB_ResetDevice(struct rt_rtmp_adapter *pAd)
-{
- int Status = TRUE;
-
- DBGPRINT_RAW(RT_DEBUG_TRACE, ("--->USB_ResetDevice\n"));
- /*RTMP_SET_FLAG(pAd, fRTMP_ADAPTER_RESET_IN_PROGRESS); */
- return Status;
-}
-
-void CMDHandler(struct rt_rtmp_adapter *pAd)
-{
- struct rt_cmdqelmt *cmdqelmt;
- u8 *pData;
- int NdisStatus = NDIS_STATUS_SUCCESS;
-/* unsigned long Now = 0; */
- int ntStatus;
-/* unsigned long IrqFlags; */
-
- while (pAd && pAd->CmdQ.size > 0) {
- NdisStatus = NDIS_STATUS_SUCCESS;
-
- NdisAcquireSpinLock(&pAd->CmdQLock);
- RTUSBDequeueCmd(&pAd->CmdQ, &cmdqelmt);
- NdisReleaseSpinLock(&pAd->CmdQLock);
-
- if (cmdqelmt == NULL)
- break;
-
- pData = cmdqelmt->buffer;
-
- if (!
- (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST)
- || RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS))) {
- switch (cmdqelmt->command) {
- case CMDTHREAD_CHECK_GPIO:
- {
- u32 data;
-
- {
- /* Read GPIO pin2 as Hardware controlled radio state */
-
- RTUSBReadMACRegister(pAd,
- GPIO_CTRL_CFG,
- &data);
-
- if (data & 0x04) {
- pAd->StaCfg.bHwRadio =
- TRUE;
- } else {
- pAd->StaCfg.bHwRadio =
- FALSE;
- }
-
- if (pAd->StaCfg.bRadio !=
- (pAd->StaCfg.bHwRadio
- && pAd->StaCfg.bSwRadio)) {
- pAd->StaCfg.bRadio =
- (pAd->StaCfg.
- bHwRadio
- && pAd->StaCfg.
- bSwRadio);
- if (pAd->StaCfg.
- bRadio == TRUE) {
- DBGPRINT_RAW
- (RT_DEBUG_ERROR,
- ("!!! Radio On !!!\n"));
-
- MlmeRadioOn
- (pAd);
- /* Update extra information */
- pAd->ExtraInfo =
- EXTRA_INFO_CLEAR;
- } else {
- DBGPRINT_RAW
- (RT_DEBUG_ERROR,
- ("!!! Radio Off !!!\n"));
-
- MlmeRadioOff
- (pAd);
- /* Update extra information */
- pAd->ExtraInfo =
- HW_RADIO_OFF;
- }
- }
- }
- }
- break;
-
- case CMDTHREAD_QKERIODIC_EXECUT:
- {
- StaQuickResponeForRateUpExec(NULL, pAd,
- NULL,
- NULL);
- }
- break;
-
- case CMDTHREAD_RESET_BULK_OUT:
- {
- u32 MACValue;
- u8 Index;
- int ret = 0;
- struct rt_ht_tx_context *pHTTXContext;
-/* struct rt_rtmp_tx_ring *pTxRing; */
- unsigned long IrqFlags;
-
- DBGPRINT_RAW(RT_DEBUG_TRACE,
- ("CmdThread : CMDTHREAD_RESET_BULK_OUT(ResetPipeid=0x%0x)===>\n",
- pAd->bulkResetPipeid));
- /* All transfers must be aborted or cancelled before attempting to reset the pipe. */
- /*RTUSBCancelPendingBulkOutIRP(pAd); */
- /* Wait 10ms to let previous packet that are already in HW FIFO to clear. by MAXLEE 12-25-2007 */
- Index = 0;
- do {
- RTUSBReadMACRegister(pAd,
- TXRXQ_PCNT,
- &MACValue);
- if ((MACValue & 0xf00000
- /*0x800000 */) == 0)
- break;
- Index++;
- RTMPusecDelay(10000);
- } while (Index < 100);
- MACValue = 0;
- RTUSBReadMACRegister(pAd, USB_DMA_CFG,
- &MACValue);
- /* To prevent Read Register error, we 2nd check the validity. */
- if ((MACValue & 0xc00000) == 0)
- RTUSBReadMACRegister(pAd,
- USB_DMA_CFG,
- &MACValue);
- /* To prevent Read Register error, we 3rd check the validity. */
- if ((MACValue & 0xc00000) == 0)
- RTUSBReadMACRegister(pAd,
- USB_DMA_CFG,
- &MACValue);
- MACValue |= 0x80000;
- RTUSBWriteMACRegister(pAd, USB_DMA_CFG,
- MACValue);
-
- /* Wait 1ms to prevent next URB to bulkout before HW reset. by MAXLEE 12-25-2007 */
- RTMPusecDelay(1000);
-
- MACValue &= (~0x80000);
- RTUSBWriteMACRegister(pAd, USB_DMA_CFG,
- MACValue);
- DBGPRINT_RAW(RT_DEBUG_TRACE,
- ("\tSet 0x2a0 bit19. Clear USB DMA TX path\n"));
-
- /* Wait 5ms to prevent next URB to bulkout before HW reset. by MAXLEE 12-25-2007 */
- /*RTMPusecDelay(5000); */
-
- if ((pAd->
- bulkResetPipeid &
- BULKOUT_MGMT_RESET_FLAG) ==
- BULKOUT_MGMT_RESET_FLAG) {
- RTMP_CLEAR_FLAG(pAd,
- fRTMP_ADAPTER_BULKOUT_RESET);
- if (pAd->MgmtRing.TxSwFreeIdx <
- MGMT_RING_SIZE
- /* pMLMEContext->bWaitingBulkOut == TRUE */
- ) {
- RTUSB_SET_BULK_FLAG(pAd,
- fRTUSB_BULK_OUT_MLME);
- }
- RTUSBKickBulkOut(pAd);
-
- DBGPRINT_RAW(RT_DEBUG_TRACE,
- ("\tTX MGMT RECOVER Done!\n"));
- } else {
- pHTTXContext =
- &(pAd->
- TxContext[pAd->
- bulkResetPipeid]);
- /*NdisAcquireSpinLock(&pAd->BulkOutLock[pAd->bulkResetPipeid]); */
- RTMP_INT_LOCK(&pAd->
- BulkOutLock[pAd->
- bulkResetPipeid],
- IrqFlags);
- if (pAd->
- BulkOutPending[pAd->
- bulkResetPipeid]
- == FALSE) {
- pAd->
- BulkOutPending[pAd->
- bulkResetPipeid]
- = TRUE;
- pHTTXContext->
- IRPPending = TRUE;
- pAd->
- watchDogTxPendingCnt
- [pAd->
- bulkResetPipeid] =
- 1;
-
- /* no matter what, clean the flag */
- RTMP_CLEAR_FLAG(pAd,
- fRTMP_ADAPTER_BULKOUT_RESET);
-
- /*NdisReleaseSpinLock(&pAd->BulkOutLock[pAd->bulkResetPipeid]); */
- RTMP_INT_UNLOCK(&pAd->
- BulkOutLock
- [pAd->
- bulkResetPipeid],
- IrqFlags);
- {
- RTUSBInitHTTxDesc
- (pAd,
- pHTTXContext,
- pAd->
- bulkResetPipeid,
- pHTTXContext->
- BulkOutSize,
- (usb_complete_t)
- RTUSBBulkOutDataPacketComplete);
-
- ret = RTUSB_SUBMIT_URB
- (pHTTXContext->
- pUrb);
- if (ret != 0) {
- RTMP_INT_LOCK
- (&pAd->
- BulkOutLock
- [pAd->
- bulkResetPipeid],
- IrqFlags);
- pAd->
- BulkOutPending
- [pAd->
- bulkResetPipeid]
- =
- FALSE;
- pHTTXContext->
- IRPPending
- =
- FALSE;
- pAd->
- watchDogTxPendingCnt
- [pAd->
- bulkResetPipeid]
- = 0;
- RTMP_INT_UNLOCK
- (&pAd->
- BulkOutLock
- [pAd->
- bulkResetPipeid],
- IrqFlags);
-
- DBGPRINT
- (RT_DEBUG_ERROR,
- ("CmdThread : CMDTHREAD_RESET_BULK_OUT: Submit Tx URB failed %d\n",
- ret));
- } else {
- RTMP_IRQ_LOCK
- (&pAd->
- BulkOutLock
- [pAd->
- bulkResetPipeid],
- IrqFlags);
- DBGPRINT_RAW
- (RT_DEBUG_TRACE,
- ("\tCMDTHREAD_RESET_BULK_OUT: TxContext[%d]:CWPos=%ld, NBPos=%ld, ENBPos=%ld, bCopy=%d, pending=%d!\n",
- pAd->
- bulkResetPipeid,
- pHTTXContext->
- CurWritePosition,
- pHTTXContext->
- NextBulkOutPosition,
- pHTTXContext->
- ENextBulkOutPosition,
- pHTTXContext->
- bCopySavePad,
- pAd->
- BulkOutPending
- [pAd->
- bulkResetPipeid]));
- DBGPRINT_RAW
- (RT_DEBUG_TRACE,
- ("\t\tBulkOut Req=0x%lx, Complete=0x%lx, Other=0x%lx\n",
- pAd->
- BulkOutReq,
- pAd->
- BulkOutComplete,
- pAd->
- BulkOutCompleteOther));
- RTMP_IRQ_UNLOCK
- (&pAd->
- BulkOutLock
- [pAd->
- bulkResetPipeid],
- IrqFlags);
- DBGPRINT_RAW
- (RT_DEBUG_TRACE,
- ("\tCMDTHREAD_RESET_BULK_OUT: Submit Tx DATA URB for failed BulkReq(0x%lx) Done, status=%d!\n",
- pAd->
- bulkResetReq
- [pAd->
- bulkResetPipeid],
- pHTTXContext->
- pUrb->
- status));
-
- }
- }
- } else {
- /*NdisReleaseSpinLock(&pAd->BulkOutLock[pAd->bulkResetPipeid]); */
- /*RTMP_INT_UNLOCK(&pAd->BulkOutLock[pAd->bulkResetPipeid], IrqFlags); */
-
- DBGPRINT_RAW
- (RT_DEBUG_ERROR,
- ("CmdThread : TX DATA RECOVER FAIL for BulkReq(0x%lx) because BulkOutPending[%d] is TRUE!\n",
- pAd->
- bulkResetReq[pAd->
- bulkResetPipeid],
- pAd->
- bulkResetPipeid));
- if (pAd->
- bulkResetPipeid ==
- 0) {
- u8
- pendingContext
- = 0;
- struct rt_ht_tx_context *
- pHTTXContext
- =
- (struct rt_ht_tx_context *)
- (&pAd->
- TxContext
- [pAd->
- bulkResetPipeid]);
- struct rt_tx_context *
- pMLMEContext
- =
- (struct rt_tx_context *)
- (pAd->
- MgmtRing.
- Cell[pAd->
- MgmtRing.
- TxDmaIdx].
- AllocVa);
- struct rt_tx_context *
- pNULLContext
- =
- (struct rt_tx_context *)
- (&pAd->
- PsPollContext);
- struct rt_tx_context *
- pPsPollContext
- =
- (struct rt_tx_context *)
- (&pAd->
- NullContext);
-
- if (pHTTXContext->IRPPending)
- pendingContext
- |=
- 1;
- else if
- (pMLMEContext->
- IRPPending)
- pendingContext
- |=
- 2;
- else if
- (pNULLContext->
- IRPPending)
- pendingContext
- |=
- 4;
- else if
- (pPsPollContext->
- IRPPending)
- pendingContext
- |=
- 8;
- else
- pendingContext
- = 0;
-
- DBGPRINT_RAW
- (RT_DEBUG_ERROR,
- ("\tTX Occupied by %d!\n",
- pendingContext));
- }
- /* no matter what, clean the flag */
- RTMP_CLEAR_FLAG(pAd,
- fRTMP_ADAPTER_BULKOUT_RESET);
-
- RTMP_INT_UNLOCK(&pAd->
- BulkOutLock
- [pAd->
- bulkResetPipeid],
- IrqFlags);
-
- RTUSB_SET_BULK_FLAG(pAd,
- (fRTUSB_BULK_OUT_DATA_NORMAL
- <<
- pAd->
- bulkResetPipeid));
- }
-
- RTMPDeQueuePacket(pAd, FALSE,
- NUM_OF_TX_RING,
- MAX_TX_PROCESS);
- /*RTUSBKickBulkOut(pAd); */
- }
-
- }
- /*
- // Don't cancel BULKIN.
- while ((atomic_read(&pAd->PendingRx) > 0) &&
- (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST)))
- {
- if (atomic_read(&pAd->PendingRx) > 0)
- {
- DBGPRINT_RAW(RT_DEBUG_ERROR, ("BulkIn IRP Pending!!cancel it!\n"));
- RTUSBCancelPendingBulkInIRP(pAd);
- }
- RTMPusecDelay(100000);
- }
-
- if ((atomic_read(&pAd->PendingRx) == 0) && (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS)))
- {
- u8 i;
- RTUSBRxPacket(pAd);
- pAd->NextRxBulkInReadIndex = 0; // Next Rx Read index
- pAd->NextRxBulkInIndex = 0; // Rx Bulk pointer
- for (i = 0; i < (RX_RING_SIZE); i++)
- {
- struct rt_rx_context *pRxContext = &(pAd->RxContext[i]);
-
- pRxContext->pAd = pAd;
- pRxContext->InUse = FALSE;
- pRxContext->IRPPending = FALSE;
- pRxContext->Readable = FALSE;
- pRxContext->ReorderInUse = FALSE;
-
- }
- RTUSBBulkReceive(pAd);
- DBGPRINT_RAW(RT_DEBUG_ERROR, ("RTUSBBulkReceive\n"));
- } */
- DBGPRINT_RAW(RT_DEBUG_TRACE,
- ("CmdThread : CMDTHREAD_RESET_BULK_OUT<===\n"));
- break;
-
- case CMDTHREAD_RESET_BULK_IN:
- DBGPRINT_RAW(RT_DEBUG_TRACE,
- ("CmdThread : CMDTHREAD_RESET_BULK_IN === >\n"));
-
- /* All transfers must be aborted or cancelled before attempting to reset the pipe. */
- {
- u32 MACValue;
- {
- /*while ((atomic_read(&pAd->PendingRx) > 0) && (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST))) */
- if ((pAd->PendingRx > 0)
- &&
- (!RTMP_TEST_FLAG
- (pAd,
- fRTMP_ADAPTER_NIC_NOT_EXIST))) {
- DBGPRINT_RAW
- (RT_DEBUG_ERROR,
- ("BulkIn IRP Pending!!!\n"));
- RTUSBCancelPendingBulkInIRP
- (pAd);
- RTMPusecDelay(100000);
- pAd->PendingRx = 0;
- }
- }
- /* Wait 10ms before reading register. */
- RTMPusecDelay(10000);
- ntStatus =
- RTUSBReadMACRegister(pAd, MAC_CSR0,
- &MACValue);
-
- if ((NT_SUCCESS(ntStatus) == TRUE) &&
- (!(RTMP_TEST_FLAG
- (pAd,
- (fRTMP_ADAPTER_RESET_IN_PROGRESS
- | fRTMP_ADAPTER_RADIO_OFF |
- fRTMP_ADAPTER_HALT_IN_PROGRESS
- |
- fRTMP_ADAPTER_NIC_NOT_EXIST)))))
- {
- u8 i;
-
- if (RTMP_TEST_FLAG
- (pAd,
- (fRTMP_ADAPTER_RESET_IN_PROGRESS
- | fRTMP_ADAPTER_RADIO_OFF
- |
- fRTMP_ADAPTER_HALT_IN_PROGRESS
- |
- fRTMP_ADAPTER_NIC_NOT_EXIST)))
- break;
- pAd->NextRxBulkInPosition =
- pAd->RxContext[pAd->
- NextRxBulkInIndex].
- BulkInOffset;
- DBGPRINT(RT_DEBUG_TRACE,
- ("BULK_IN_RESET: NBIIdx=0x%x,NBIRIdx=0x%x, BIRPos=0x%lx. BIReq=x%lx, BIComplete=0x%lx, BICFail0x%lx\n",
- pAd->
- NextRxBulkInIndex,
- pAd->
- NextRxBulkInReadIndex,
- pAd->
- NextRxBulkInPosition,
- pAd->BulkInReq,
- pAd->BulkInComplete,
- pAd->
- BulkInCompleteFail));
- for (i = 0; i < RX_RING_SIZE;
- i++) {
- DBGPRINT(RT_DEBUG_TRACE,
- ("\tRxContext[%d]: IRPPending=%d, InUse=%d, Readable=%d!\n",
- i,
- pAd->
- RxContext[i].
- IRPPending,
- pAd->
- RxContext[i].
- InUse,
- pAd->
- RxContext[i].
- Readable));
- }
- /*
-
- DBGPRINT_RAW(RT_DEBUG_ERROR, ("==========================================\n"));
-
- pAd->NextRxBulkInReadIndex = 0; // Next Rx Read index
- pAd->NextRxBulkInIndex = 0; // Rx Bulk pointer
- for (i = 0; i < (RX_RING_SIZE); i++)
- {
- struct rt_rx_context *pRxContext = &(pAd->RxContext[i]);
-
- pRxContext->pAd = pAd;
- pRxContext->InUse = FALSE;
- pRxContext->IRPPending = FALSE;
- pRxContext->Readable = FALSE;
- pRxContext->ReorderInUse = FALSE;
-
- } */
- RTMP_CLEAR_FLAG(pAd,
- fRTMP_ADAPTER_BULKIN_RESET);
- for (i = 0;
- i <
- pAd->CommonCfg.
- NumOfBulkInIRP; i++) {
- /*RTUSBBulkReceive(pAd); */
- struct rt_rx_context *pRxContext;
- PURB pUrb;
- int ret = 0;
- unsigned long IrqFlags;
-
- RTMP_IRQ_LOCK(&pAd->
- BulkInLock,
- IrqFlags);
- pRxContext =
- &(pAd->
- RxContext[pAd->
- NextRxBulkInIndex]);
- if ((pAd->PendingRx > 0)
- || (pRxContext->
- Readable ==
- TRUE)
- || (pRxContext->
- InUse ==
- TRUE)) {
- RTMP_IRQ_UNLOCK
- (&pAd->
- BulkInLock,
- IrqFlags);
- break;
- }
- pRxContext->InUse =
- TRUE;
- pRxContext->IRPPending =
- TRUE;
- pAd->PendingRx++;
- pAd->BulkInReq++;
- RTMP_IRQ_UNLOCK(&pAd->
- BulkInLock,
- IrqFlags);
-
- /* Init Rx context descriptor */
- RTUSBInitRxDesc(pAd,
- pRxContext);
- pUrb = pRxContext->pUrb;
- ret = RTUSB_SUBMIT_URB(pUrb);
- if (ret != 0) { /* fail */
-
- RTMP_IRQ_LOCK
- (&pAd->
- BulkInLock,
- IrqFlags);
- pRxContext->
- InUse =
- FALSE;
- pRxContext->
- IRPPending =
- FALSE;
- pAd->
- PendingRx--;
- pAd->
- BulkInReq--;
- RTMP_IRQ_UNLOCK
- (&pAd->
- BulkInLock,
- IrqFlags);
- DBGPRINT
- (RT_DEBUG_ERROR,
- ("CMDTHREAD_RESET_BULK_IN: Submit Rx URB failed(%d), status=%d\n",
- ret,
- pUrb->
- status));
- } else { /* success */
- /*DBGPRINT(RT_DEBUG_TRACE, ("BIDone, Pend=%d,BIIdx=%d,BIRIdx=%d!\n", */
- /* pAd->PendingRx, pAd->NextRxBulkInIndex, pAd->NextRxBulkInReadIndex)); */
- DBGPRINT_RAW
- (RT_DEBUG_TRACE,
- ("CMDTHREAD_RESET_BULK_IN: Submit Rx URB Done, status=%d!\n",
- pUrb->
- status));
- ASSERT((pRxContext->InUse == pRxContext->IRPPending));
- }
- }
-
- } else {
- /* Card must be removed */
- if (NT_SUCCESS(ntStatus) !=
- TRUE) {
- RTMP_SET_FLAG(pAd,
- fRTMP_ADAPTER_NIC_NOT_EXIST);
- DBGPRINT_RAW
- (RT_DEBUG_ERROR,
- ("CMDTHREAD_RESET_BULK_IN: Read Register Failed!Card must be removed!!\n\n"));
- } else {
- DBGPRINT_RAW
- (RT_DEBUG_ERROR,
- ("CMDTHREAD_RESET_BULK_IN: Cannot do bulk in because flags(0x%lx) on !\n",
- pAd->Flags));
- }
- }
- }
- DBGPRINT_RAW(RT_DEBUG_TRACE,
- ("CmdThread : CMDTHREAD_RESET_BULK_IN <===\n"));
- break;
-
- case CMDTHREAD_SET_ASIC_WCID:
- {
- struct rt_set_asic_wcid SetAsicWcid;
- u16 offset;
- u32 MACValue, MACRValue = 0;
- SetAsicWcid =
- *((struct rt_set_asic_wcid *)(pData));
-
- if (SetAsicWcid.WCID >=
- MAX_LEN_OF_MAC_TABLE)
- return;
-
- offset =
- MAC_WCID_BASE +
- ((u8)SetAsicWcid.WCID) *
- HW_WCID_ENTRY_SIZE;
-
- DBGPRINT_RAW(RT_DEBUG_TRACE,
- ("CmdThread : CMDTHREAD_SET_ASIC_WCID : WCID = %ld, SetTid = %lx, DeleteTid = %lx.\n",
- SetAsicWcid.WCID,
- SetAsicWcid.SetTid,
- SetAsicWcid.DeleteTid));
- MACValue =
- (pAd->MacTab.
- Content[SetAsicWcid.WCID].
- Addr[3] << 24) +
- (pAd->MacTab.
- Content[SetAsicWcid.WCID].
- Addr[2] << 16) +
- (pAd->MacTab.
- Content[SetAsicWcid.WCID].
- Addr[1] << 8) +
- (pAd->MacTab.
- Content[SetAsicWcid.WCID].Addr[0]);
- DBGPRINT_RAW(RT_DEBUG_TRACE,
- ("1-MACValue= %x,\n",
- MACValue));
- RTUSBWriteMACRegister(pAd, offset,
- MACValue);
- /* Read bitmask */
- RTUSBReadMACRegister(pAd, offset + 4,
- &MACRValue);
- if (SetAsicWcid.DeleteTid != 0xffffffff)
- MACRValue &=
- (~SetAsicWcid.DeleteTid);
- if (SetAsicWcid.SetTid != 0xffffffff)
- MACRValue |=
- (SetAsicWcid.SetTid);
- MACRValue &= 0xffff0000;
-
- MACValue =
- (pAd->MacTab.
- Content[SetAsicWcid.WCID].
- Addr[5] << 8) +
- pAd->MacTab.Content[SetAsicWcid.
- WCID].Addr[4];
- MACValue |= MACRValue;
- RTUSBWriteMACRegister(pAd, offset + 4,
- MACValue);
-
- DBGPRINT_RAW(RT_DEBUG_TRACE,
- ("2-MACValue= %x,\n",
- MACValue));
- }
- break;
-
- case CMDTHREAD_SET_ASIC_WCID_CIPHER:
- {
- struct rt_set_asic_wcid_attri SetAsicWcidAttri;
- u16 offset;
- u32 MACRValue = 0;
- SHAREDKEY_MODE_STRUC csr1;
- SetAsicWcidAttri =
- *((struct rt_set_asic_wcid_attri *)
- (pData));
-
- if (SetAsicWcidAttri.WCID >=
- MAX_LEN_OF_MAC_TABLE)
- return;
-
- offset =
- MAC_WCID_ATTRIBUTE_BASE +
- ((u8)SetAsicWcidAttri.WCID) *
- HW_WCID_ATTRI_SIZE;
-
- DBGPRINT_RAW(RT_DEBUG_TRACE,
- ("Cmd : CMDTHREAD_SET_ASIC_WCID_CIPHER : WCID = %ld, Cipher = %lx.\n",
- SetAsicWcidAttri.WCID,
- SetAsicWcidAttri.Cipher));
- /* Read bitmask */
- RTUSBReadMACRegister(pAd, offset,
- &MACRValue);
- MACRValue = 0;
- MACRValue |=
- (((u8)SetAsicWcidAttri.
- Cipher) << 1);
-
- RTUSBWriteMACRegister(pAd, offset,
- MACRValue);
- DBGPRINT_RAW(RT_DEBUG_TRACE,
- ("2-offset = %x , MACValue= %x,\n",
- offset, MACRValue));
-
- offset =
- PAIRWISE_IVEIV_TABLE_BASE +
- ((u8)SetAsicWcidAttri.WCID) *
- HW_IVEIV_ENTRY_SIZE;
- MACRValue = 0;
- if ((SetAsicWcidAttri.Cipher <=
- CIPHER_WEP128))
- MACRValue |=
- (pAd->StaCfg.
- DefaultKeyId << 30);
- else
- MACRValue |= (0x20000000);
- RTUSBWriteMACRegister(pAd, offset,
- MACRValue);
- DBGPRINT_RAW(RT_DEBUG_TRACE,
- ("2-offset = %x , MACValue= %x,\n",
- offset, MACRValue));
-
- /* */
- /* Update cipher algorithm. WSTA always use BSS0 */
- /* */
- /* for adhoc mode only ,because wep status slow than add key, when use zero config */
- if (pAd->StaCfg.BssType == BSS_ADHOC) {
- offset =
- MAC_WCID_ATTRIBUTE_BASE;
-
- RTUSBReadMACRegister(pAd,
- offset,
- &MACRValue);
- MACRValue &= (~0xe);
- MACRValue |=
- (((u8)SetAsicWcidAttri.
- Cipher) << 1);
-
- RTUSBWriteMACRegister(pAd,
- offset,
- MACRValue);
-
- /*Update group key cipher,,because wep status slow than add key, when use zero config */
- RTUSBReadMACRegister(pAd,
- SHARED_KEY_MODE_BASE
- +
- 4 * (0 /
- 2),
- &csr1.
- word);
-
- csr1.field.Bss0Key0CipherAlg =
- SetAsicWcidAttri.Cipher;
- csr1.field.Bss0Key1CipherAlg =
- SetAsicWcidAttri.Cipher;
-
- RTUSBWriteMACRegister(pAd,
- SHARED_KEY_MODE_BASE
- +
- 4 * (0 /
- 2),
- csr1.
- word);
- }
- }
- break;
-
-/*Benson modified for USB interface, avoid in interrupt when write key, 20080724 --> */
- case RT_CMD_SET_KEY_TABLE: /*General call for AsicAddPairwiseKeyEntry() */
- {
- struct rt_add_pairwise_key_entry KeyInfo;
- KeyInfo =
- *((struct rt_add_pairwise_key_entry *)
- (pData));
- AsicAddPairwiseKeyEntry(pAd,
- KeyInfo.MacAddr,
- (u8)KeyInfo.
- MacTabMatchWCID,
- &KeyInfo.
- CipherKey);
- }
- break;
-
- case RT_CMD_SET_RX_WCID_TABLE: /*General call for RTMPAddWcidAttributeEntry() */
- {
- struct rt_mac_table_entry *pEntry;
- u8 KeyIdx = 0;
- u8 CipherAlg = CIPHER_NONE;
- u8 ApIdx = BSS0;
-
- pEntry = (struct rt_mac_table_entry *)(pData);
-
- RTMPAddWcidAttributeEntry(pAd,
- ApIdx,
- KeyIdx,
- CipherAlg,
- pEntry);
- }
- break;
-/*Benson modified for USB interface, avoid in interrupt when write key, 20080724 <-- */
-
- case CMDTHREAD_SET_CLIENT_MAC_ENTRY:
- {
- struct rt_mac_table_entry *pEntry;
- pEntry = (struct rt_mac_table_entry *)pData;
-
- {
- AsicRemovePairwiseKeyEntry(pAd,
- pEntry->
- apidx,
- (u8)
- pEntry->
- Aid);
- if ((pEntry->AuthMode <=
- Ndis802_11AuthModeAutoSwitch)
- && (pEntry->WepStatus ==
- Ndis802_11Encryption1Enabled))
- {
- u32 uIV = 1;
- u8 *ptr;
-
- ptr = (u8 *)& uIV;
- *(ptr + 3) =
- (pAd->StaCfg.
- DefaultKeyId << 6);
- AsicUpdateWCIDIVEIV(pAd,
- pEntry->
- Aid,
- uIV,
- 0);
- AsicUpdateWCIDAttribute
- (pAd, pEntry->Aid,
- BSS0,
- pAd->
- SharedKey[BSS0]
- [pAd->StaCfg.
- DefaultKeyId].
- CipherAlg, FALSE);
- } else if (pEntry->AuthMode ==
- Ndis802_11AuthModeWPANone)
- {
- u32 uIV = 1;
- u8 *ptr;
-
- ptr = (u8 *)& uIV;
- *(ptr + 3) =
- (pAd->StaCfg.
- DefaultKeyId << 6);
- AsicUpdateWCIDIVEIV(pAd,
- pEntry->
- Aid,
- uIV,
- 0);
- AsicUpdateWCIDAttribute
- (pAd, pEntry->Aid,
- BSS0,
- pAd->
- SharedKey[BSS0]
- [pAd->StaCfg.
- DefaultKeyId].
- CipherAlg, FALSE);
- } else {
- /* */
- /* Other case, disable engine. */
- /* Don't worry WPA key, we will add WPA Key after 4-Way handshaking. */
- /* */
- u16 offset;
- offset =
- MAC_WCID_ATTRIBUTE_BASE
- +
- (pEntry->Aid *
- HW_WCID_ATTRI_SIZE);
- /* RX_PKEY_MODE:0 for no security; RX_KEY_TAB:0 for shared key table; BSS_IDX:0 */
- RTUSBWriteMACRegister
- (pAd, offset, 0);
- }
- }
-
- AsicUpdateRxWCIDTable(pAd, pEntry->Aid,
- pEntry->Addr);
- DBGPRINT(RT_DEBUG_TRACE,
- ("UpdateRxWCIDTable(): Aid=%d, "
- "Addr=%pM!\n",
- pEntry->Aid,
- pEntry->Addr));
- }
- break;
-
-/* add by johnli, fix "in_interrupt" error when call "MacTableDeleteEntry" in Rx tasklet */
- case CMDTHREAD_UPDATE_PROTECT:
- {
- AsicUpdateProtect(pAd, 0,
- (ALLN_SETPROTECT),
- TRUE, 0);
- }
- break;
-/* end johnli */
-
- case OID_802_11_ADD_WEP:
- {
- u32 i;
- u32 KeyIdx;
- struct rt_ndis_802_11_wep *pWepKey;
-
- DBGPRINT(RT_DEBUG_TRACE,
- ("CmdThread::OID_802_11_ADD_WEP \n"));
-
- pWepKey = (struct rt_ndis_802_11_wep *)pData;
- KeyIdx = pWepKey->KeyIndex & 0x0fffffff;
-
- /* it is a shared key */
- if ((KeyIdx >= 4)
- || ((pWepKey->KeyLength != 5)
- && (pWepKey->KeyLength !=
- 13))) {
- NdisStatus =
- NDIS_STATUS_INVALID_DATA;
- DBGPRINT(RT_DEBUG_ERROR,
- ("CmdThread::OID_802_11_ADD_WEP, INVALID_DATA!!\n"));
- } else {
- u8 CipherAlg;
- pAd->SharedKey[BSS0][KeyIdx].
- KeyLen =
- (u8)pWepKey->KeyLength;
- NdisMoveMemory(pAd->
- SharedKey[BSS0]
- [KeyIdx].Key,
- &pWepKey->
- KeyMaterial,
- pWepKey->
- KeyLength);
- CipherAlg =
- (pAd->
- SharedKey[BSS0][KeyIdx].
- KeyLen ==
- 5) ? CIPHER_WEP64 :
- CIPHER_WEP128;
-
- /* */
- /* Change the WEP cipher to CKIP cipher if CKIP KP on. */
- /* Funk UI or Meetinghouse UI will add ckip key from this path. */
- /* */
-
- if (pAd->OpMode == OPMODE_STA) {
- pAd->MacTab.
- Content[BSSID_WCID].
- PairwiseKey.
- CipherAlg =
- pAd->
- SharedKey[BSS0]
- [KeyIdx].CipherAlg;
- pAd->MacTab.
- Content[BSSID_WCID].
- PairwiseKey.KeyLen =
- pAd->
- SharedKey[BSS0]
- [KeyIdx].KeyLen;
- }
- pAd->SharedKey[BSS0][KeyIdx].
- CipherAlg = CipherAlg;
- if (pWepKey->
- KeyIndex & 0x80000000) {
- /* Default key for tx (shared key) */
- u8 IVEIV[8];
- u32 WCIDAttri, Value;
- u16 offset, offset2;
- NdisZeroMemory(IVEIV,
- 8);
- pAd->StaCfg.
- DefaultKeyId =
- (u8)KeyIdx;
- /* Add BSSID to WCTable. because this is Tx wep key. */
- /* WCID Attribute UDF:3, BSSIdx:3, Alg:3, Keytable:1=PAIRWISE KEY, BSSIdx is 0 */
- WCIDAttri =
- (CipherAlg << 1) |
- SHAREDKEYTABLE;
-
- offset =
- MAC_WCID_ATTRIBUTE_BASE
- +
- (BSSID_WCID *
- HW_WCID_ATTRI_SIZE);
- RTUSBWriteMACRegister
- (pAd, offset,
- WCIDAttri);
- /* 1. IV/EIV */
- /* Specify key index to find shared key. */
- IVEIV[3] = (u8)(KeyIdx << 6); /*WEP Eiv bit off. groupkey index is not 0 */
- offset =
- PAIRWISE_IVEIV_TABLE_BASE
- +
- (BSS0Mcast_WCID *
- HW_IVEIV_ENTRY_SIZE);
- offset2 =
- PAIRWISE_IVEIV_TABLE_BASE
- +
- (BSSID_WCID *
- HW_IVEIV_ENTRY_SIZE);
- for (i = 0; i < 8;) {
- Value =
- IVEIV[i];
- Value +=
- (IVEIV
- [i +
- 1] << 8);
- Value +=
- (IVEIV
- [i +
- 2] << 16);
- Value +=
- (IVEIV
- [i +
- 3] << 24);
- RTUSBWriteMACRegister
- (pAd,
- offset + i,
- Value);
- RTUSBWriteMACRegister
- (pAd,
- offset2 +
- i, Value);
- i += 4;
- }
-
- /* 2. WCID Attribute UDF:3, BSSIdx:3, Alg:3, Keytable:use share key, BSSIdx is 0 */
- WCIDAttri =
- (pAd->
- SharedKey[BSS0]
- [KeyIdx].
- CipherAlg << 1) |
- SHAREDKEYTABLE;
- offset =
- MAC_WCID_ATTRIBUTE_BASE
- +
- (BSS0Mcast_WCID *
- HW_WCID_ATTRI_SIZE);
- DBGPRINT(RT_DEBUG_TRACE,
- ("BSS0Mcast_WCID : offset = %x, WCIDAttri = %x\n",
- offset,
- WCIDAttri));
- RTUSBWriteMACRegister
- (pAd, offset,
- WCIDAttri);
-
- }
- AsicAddSharedKeyEntry(pAd, BSS0,
- (u8)
- KeyIdx,
- CipherAlg,
- pWepKey->
- KeyMaterial,
- NULL,
- NULL);
- DBGPRINT(RT_DEBUG_TRACE,
- ("CmdThread::OID_802_11_ADD_WEP (KeyIdx=%d, Len=%d-byte)\n",
- KeyIdx,
- pWepKey->KeyLength));
- }
- }
- break;
-
- case CMDTHREAD_802_11_COUNTER_MEASURE:
- break;
-
- case CMDTHREAD_SET_GROUP_KEY:
- WpaStaGroupKeySetting(pAd);
- break;
-
- case CMDTHREAD_SET_PAIRWISE_KEY:
- WpaStaPairwiseKeySetting(pAd);
- break;
-
- case CMDTHREAD_SET_PSM_BIT:
- {
- u16 *pPsm = (u16 *) pData;
- MlmeSetPsmBit(pAd, *pPsm);
- }
- break;
- case CMDTHREAD_FORCE_WAKE_UP:
- AsicForceWakeup(pAd, TRUE);
- break;
-
- default:
- DBGPRINT(RT_DEBUG_ERROR,
- ("--> Control Thread !! ERROR !! Unknown(cmdqelmt->command=0x%x) !! \n",
- cmdqelmt->command));
- break;
- }
- }
-
- if (cmdqelmt->CmdFromNdis == TRUE) {
- if (cmdqelmt->buffer != NULL)
- os_free_mem(pAd, cmdqelmt->buffer);
- os_free_mem(pAd, cmdqelmt);
- } else {
- if ((cmdqelmt->buffer != NULL)
- && (cmdqelmt->bufferlength != 0))
- os_free_mem(pAd, cmdqelmt->buffer);
- os_free_mem(pAd, cmdqelmt);
- }
- } /* end of while */
-}
-
-#endif /* RTMP_MAC_USB // */
diff --git a/drivers/staging/rt2870/common/spectrum.c b/drivers/staging/rt2870/common/spectrum.c
deleted file mode 100644
index 1cf2c26..0000000
--- a/drivers/staging/rt2870/common/spectrum.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../../rt2860/common/spectrum.c"
diff --git a/drivers/staging/rt2870/dfs.h b/drivers/staging/rt2870/dfs.h
deleted file mode 100644
index 1fdbd7b..0000000
--- a/drivers/staging/rt2870/dfs.h
+++ /dev/null
@@ -1 +0,0 @@
-#include "../rt2860/dfs.h"
diff --git a/drivers/staging/rt2870/md5.h b/drivers/staging/rt2870/md5.h
deleted file mode 100644
index d60cd05..0000000
--- a/drivers/staging/rt2870/md5.h
+++ /dev/null
@@ -1 +0,0 @@
-#include "../rt2860/md5.h"
diff --git a/drivers/staging/rt2870/mlme.h b/drivers/staging/rt2870/mlme.h
deleted file mode 100644
index 58753ac..0000000
--- a/drivers/staging/rt2870/mlme.h
+++ /dev/null
@@ -1 +0,0 @@
-#include "../rt2860/mlme.h"
diff --git a/drivers/staging/rt2870/oid.h b/drivers/staging/rt2870/oid.h
deleted file mode 100644
index 1223d81b..0000000
--- a/drivers/staging/rt2870/oid.h
+++ /dev/null
@@ -1 +0,0 @@
-#include "../rt2860/oid.h"
diff --git a/drivers/staging/rt2870/rt28xx.h b/drivers/staging/rt2870/rt28xx.h
deleted file mode 100644
index 29bad95..0000000
--- a/drivers/staging/rt2870/rt28xx.h
+++ /dev/null
@@ -1 +0,0 @@
-#include "../rt2860/rt28xx.h"
diff --git a/drivers/staging/rt2870/rt_config.h b/drivers/staging/rt2870/rt_config.h
deleted file mode 100644
index 1f6d6ed..0000000
--- a/drivers/staging/rt2870/rt_config.h
+++ /dev/null
@@ -1 +0,0 @@
-#include "../rt2860/rt_config.h"
diff --git a/drivers/staging/rt2870/rt_linux.c b/drivers/staging/rt2870/rt_linux.c
deleted file mode 100644
index 88c697b..0000000
--- a/drivers/staging/rt2870/rt_linux.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../rt2860/rt_linux.c"
diff --git a/drivers/staging/rt2870/rt_linux.h b/drivers/staging/rt2870/rt_linux.h
deleted file mode 100644
index b2aeafb..0000000
--- a/drivers/staging/rt2870/rt_linux.h
+++ /dev/null
@@ -1 +0,0 @@
-#include "../rt2860/rt_linux.h"
diff --git a/drivers/staging/rt2870/rt_main_dev.c b/drivers/staging/rt2870/rt_main_dev.c
deleted file mode 100644
index 121e163..0000000
--- a/drivers/staging/rt2870/rt_main_dev.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../rt2860/rt_main_dev.c"
diff --git a/drivers/staging/rt2870/rt_profile.c b/drivers/staging/rt2870/rt_profile.c
deleted file mode 100644
index 15988c5..0000000
--- a/drivers/staging/rt2870/rt_profile.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../rt2860/rt_profile.c"
diff --git a/drivers/staging/rt2870/rt_usb.c b/drivers/staging/rt2870/rt_usb.c
deleted file mode 100644
index 5e02d4c..0000000
--- a/drivers/staging/rt2870/rt_usb.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../rt2860/rt_usb.c"
diff --git a/drivers/staging/rt2870/rtmp.h b/drivers/staging/rt2870/rtmp.h
deleted file mode 100644
index e5ef89f..0000000
--- a/drivers/staging/rt2870/rtmp.h
+++ /dev/null
@@ -1 +0,0 @@
-#include "../rt2860/rtmp.h"
diff --git a/drivers/staging/rt2870/rtmp_ckipmic.h b/drivers/staging/rt2870/rtmp_ckipmic.h
deleted file mode 100644
index 0e7f1df..0000000
--- a/drivers/staging/rt2870/rtmp_ckipmic.h
+++ /dev/null
@@ -1 +0,0 @@
-#include "../rt2860/rtmp_ckipmic.h"
diff --git a/drivers/staging/rt2870/rtmp_def.h b/drivers/staging/rt2870/rtmp_def.h
deleted file mode 100644
index 839d791..0000000
--- a/drivers/staging/rt2870/rtmp_def.h
+++ /dev/null
@@ -1 +0,0 @@
-#include "../rt2860/rtmp_def.h"
diff --git a/drivers/staging/rt2870/rtmp_type.h b/drivers/staging/rt2870/rtmp_type.h
deleted file mode 100644
index fbf97d0..0000000
--- a/drivers/staging/rt2870/rtmp_type.h
+++ /dev/null
@@ -1 +0,0 @@
-#include "../rt2860/rtmp_type.h"
diff --git a/drivers/staging/rt2870/spectrum.h b/drivers/staging/rt2870/spectrum.h
deleted file mode 100644
index 8aa23a18..0000000
--- a/drivers/staging/rt2870/spectrum.h
+++ /dev/null
@@ -1 +0,0 @@
-#include "../rt2860/spectrum.h"
diff --git a/drivers/staging/rt2870/spectrum_def.h b/drivers/staging/rt2870/spectrum_def.h
deleted file mode 100644
index a65f551..0000000
--- a/drivers/staging/rt2870/spectrum_def.h
+++ /dev/null
@@ -1 +0,0 @@
-#include "../rt2860/spectrum_def.h"
diff --git a/drivers/staging/rt2870/sta/aironet.c b/drivers/staging/rt2870/sta/aironet.c
deleted file mode 100644
index 72b7f2e..0000000
--- a/drivers/staging/rt2870/sta/aironet.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../../rt2860/sta/aironet.c"
diff --git a/drivers/staging/rt2870/sta/assoc.c b/drivers/staging/rt2870/sta/assoc.c
deleted file mode 100644
index 46564d7..0000000
--- a/drivers/staging/rt2870/sta/assoc.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../../rt2860/sta/assoc.c"
diff --git a/drivers/staging/rt2870/sta/auth.c b/drivers/staging/rt2870/sta/auth.c
deleted file mode 100644
index 57632f9..0000000
--- a/drivers/staging/rt2870/sta/auth.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../../rt2860/sta/auth.c"
diff --git a/drivers/staging/rt2870/sta/auth_rsp.c b/drivers/staging/rt2870/sta/auth_rsp.c
deleted file mode 100644
index 783e266..0000000
--- a/drivers/staging/rt2870/sta/auth_rsp.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../../rt2860/sta/auth_rsp.c"
diff --git a/drivers/staging/rt2870/sta/connect.c b/drivers/staging/rt2870/sta/connect.c
deleted file mode 100644
index f6c7bbf..0000000
--- a/drivers/staging/rt2870/sta/connect.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../../rt2860/sta/connect.c"
diff --git a/drivers/staging/rt2870/sta/rtmp_data.c b/drivers/staging/rt2870/sta/rtmp_data.c
deleted file mode 100644
index b67e069..0000000
--- a/drivers/staging/rt2870/sta/rtmp_data.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../../rt2860/sta/rtmp_data.c"
diff --git a/drivers/staging/rt2870/sta/sanity.c b/drivers/staging/rt2870/sta/sanity.c
deleted file mode 100644
index f1f2333..0000000
--- a/drivers/staging/rt2870/sta/sanity.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../../rt2860/sta/sanity.c"
diff --git a/drivers/staging/rt2870/sta/sync.c b/drivers/staging/rt2870/sta/sync.c
deleted file mode 100644
index 66c8772..0000000
--- a/drivers/staging/rt2870/sta/sync.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../../rt2860/sta/sync.c"
diff --git a/drivers/staging/rt2870/sta/wpa.c b/drivers/staging/rt2870/sta/wpa.c
deleted file mode 100644
index 57a2eb2..0000000
--- a/drivers/staging/rt2870/sta/wpa.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../../rt2860/sta/wpa.c"
diff --git a/drivers/staging/rt2870/sta_ioctl.c b/drivers/staging/rt2870/sta_ioctl.c
deleted file mode 100644
index 3553a6c..0000000
--- a/drivers/staging/rt2870/sta_ioctl.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../rt2860/sta_ioctl.c"
diff --git a/drivers/staging/rt2870/usb_main_dev.c b/drivers/staging/rt2870/usb_main_dev.c
deleted file mode 100644
index 6e63bc5..0000000
--- a/drivers/staging/rt2870/usb_main_dev.c
+++ /dev/null
@@ -1 +0,0 @@
-#include "../rt2860/usb_main_dev.c"
diff --git a/drivers/staging/rt2870/wpa.h b/drivers/staging/rt2870/wpa.h
deleted file mode 100644
index 7125072..0000000
--- a/drivers/staging/rt2870/wpa.h
+++ /dev/null
@@ -1 +0,0 @@
-#include "../rt2860/wpa.h"
diff --git a/drivers/staging/rtl8712/ieee80211.h b/drivers/staging/rtl8712/ieee80211.h
index 432cf8a..1f4d147 100644
--- a/drivers/staging/rtl8712/ieee80211.h
+++ b/drivers/staging/rtl8712/ieee80211.h
@@ -76,7 +76,7 @@
u8 reserved[32];
u8 data[0];
} wpa_ie;
- struct{
+ struct {
int command;
int reason_code;
} mlme;
@@ -149,11 +149,11 @@
struct ieee80211_hdr_3addr_qos {
u16 frame_ctl;
u16 duration_id;
- u8 addr1[ETH_ALEN];
- u8 addr2[ETH_ALEN];
- u8 addr3[ETH_ALEN];
+ u8 addr1[ETH_ALEN];
+ u8 addr2[ETH_ALEN];
+ u8 addr3[ETH_ALEN];
u16 seq_ctl;
- u16 qc;
+ u16 qc;
} __attribute__ ((packed));
struct eapol {
@@ -461,7 +461,7 @@
uint rx_message_in_bad_msg_fragments;
};
-struct ieee80211_softmac_stats{
+struct ieee80211_softmac_stats {
uint rx_ass_ok;
uint rx_ass_err;
uint rx_probe_rq;
@@ -754,15 +754,17 @@
u8 *r8712_set_ie(u8 *pbuf, sint index, uint len, u8 *source, uint *frlen);
u8 *r8712_get_ie(u8*pbuf, sint index, sint *len, sint limit);
unsigned char *r8712_get_wpa_ie(unsigned char *pie, int *rsn_ie_len, int limit);
-unsigned char *r8712_get_wpa2_ie(unsigned char *pie, int *rsn_ie_len, int limit);
+unsigned char *r8712_get_wpa2_ie(unsigned char *pie, int *rsn_ie_len,
+ int limit);
int r8712_parse_wpa_ie(u8 *wpa_ie, int wpa_ie_len, int *group_cipher,
- int *pairwise_cipher);
+ int *pairwise_cipher);
int r8712_parse_wpa2_ie(u8 *wpa_ie, int wpa_ie_len, int *group_cipher,
- int *pairwise_cipher);
-int r8712_get_sec_ie(u8 *in_ie, uint in_len, u8 *rsn_ie, u16 *rsn_len, u8 *wpa_ie,
- u16 *wpa_len);
+ int *pairwise_cipher);
+int r8712_get_sec_ie(u8 *in_ie, uint in_len, u8 *rsn_ie, u16 *rsn_len,
+ u8 *wpa_ie, u16 *wpa_len);
int r8712_get_wps_ie(u8 *in_ie, uint in_len, u8 *wps_ie, uint *wps_ielen);
-int r8712_generate_ie(struct registry_priv *pregistrypriv, struct _adapter *padapter);
+int r8712_generate_ie(struct registry_priv *pregistrypriv,
+ struct _adapter *padapter);
uint r8712_is_cckrates_included(u8 *rate);
uint r8712_is_cckratesonly_included(u8 *rate);
diff --git a/drivers/staging/rtl8712/if_ether.h b/drivers/staging/rtl8712/if_ether.h
index 36a2ba5..0e9753b 100644
--- a/drivers/staging/rtl8712/if_ether.h
+++ b/drivers/staging/rtl8712/if_ether.h
@@ -99,8 +99,8 @@
};
struct _vlan {
- unsigned short h_vlan_TCI; /* Encapsulates priority and VLAN ID*/
- unsigned short h_vlan_encapsulated_proto;
+ unsigned short h_vlan_TCI; /* Encapsulates priority and VLAN ID*/
+ unsigned short h_vlan_encapsulated_proto;
};
diff --git a/drivers/staging/rtl8712/ip.h b/drivers/staging/rtl8712/ip.h
index 4785a59..f37b0f8 100644
--- a/drivers/staging/rtl8712/ip.h
+++ b/drivers/staging/rtl8712/ip.h
@@ -90,23 +90,23 @@
#define IPOPT_TS_PRESPEC 3 /* specified modules only */
struct ip_options {
- __u32 faddr; /* Saved first hop address */
- unsigned char optlen;
- unsigned char srr;
- unsigned char rr;
- unsigned char ts;
- unsigned char is_setbyuser:1, /* Set by setsockopt? */
- is_data:1, /* Options in __data, rather than skb */
- is_strictroute:1, /* Strict source route */
- srr_is_hit:1, /* Packet destination addr was our one */
- is_changed:1, /* IP checksum more not valid */
- rr_needaddr:1, /* Need to record addr of outgoing dev */
- ts_needtime:1, /* Need to record timestamp */
- ts_needaddr:1; /* Need to record addr of outgoing dev */
- unsigned char router_alert;
- unsigned char __pad1;
- unsigned char __pad2;
- unsigned char __data[0];
+ __u32 faddr; /* Saved first hop address */
+ unsigned char optlen;
+ unsigned char srr;
+ unsigned char rr;
+ unsigned char ts;
+ unsigned char is_setbyuser:1, /* Set by setsockopt? */
+ is_data:1, /* Options in __data, rather than skb */
+ is_strictroute:1, /* Strict source route */
+ srr_is_hit:1, /* Packet destination addr was our one*/
+ is_changed:1, /* IP checksum more not valid */
+ rr_needaddr:1, /* Need to record addr of outgoing dev*/
+ ts_needtime:1, /* Need to record timestamp */
+ ts_needaddr:1; /* Need to record addr of outgoing dev*/
+ unsigned char router_alert;
+ unsigned char __pad1;
+ unsigned char __pad2;
+ unsigned char __data[0];
};
#define optlength(opt) (sizeof(struct ip_options) + opt->optlen)
diff --git a/drivers/staging/rtl8712/mlme_osdep.h b/drivers/staging/rtl8712/mlme_osdep.h
index 7013a49..968e787 100644
--- a/drivers/staging/rtl8712/mlme_osdep.h
+++ b/drivers/staging/rtl8712/mlme_osdep.h
@@ -9,8 +9,8 @@
void r8712_os_indicate_connect(struct _adapter *adapter);
void r8712_report_sec_ie(struct _adapter *adapter, u8 authmode, u8 *sec_ie);
int r8712_recv_indicatepkts_in_order(struct _adapter *adapter,
- struct recv_reorder_ctrl *precvreorder_ctrl,
- int bforced);
+ struct recv_reorder_ctrl *precvreorder_ctrl,
+ int bforced);
void r8712_indicate_wx_assoc_event(struct _adapter *padapter);
void r8712_indicate_wx_disassoc_event(struct _adapter *padapter);
diff --git a/drivers/staging/rtl8712/osdep_service.h b/drivers/staging/rtl8712/osdep_service.h
index 36eeb5a..3d3f73c 100644
--- a/drivers/staging/rtl8712/osdep_service.h
+++ b/drivers/staging/rtl8712/osdep_service.h
@@ -145,7 +145,8 @@
return false;
}
-static inline void list_insert_tail(struct list_head *plist, struct list_head *phead)
+static inline void list_insert_tail(struct list_head *plist,
+ struct list_head *phead)
{
list_add_tail(plist, phead);
}
diff --git a/drivers/staging/rtl8712/recv_osdep.h b/drivers/staging/rtl8712/recv_osdep.h
index b23dd6b..60a54dd 100644
--- a/drivers/staging/rtl8712/recv_osdep.h
+++ b/drivers/staging/rtl8712/recv_osdep.h
@@ -12,7 +12,8 @@
void r8712_recv_indicatepkt(struct _adapter *adapter,
union recv_frame *precv_frame);
void r8712_handle_tkip_mic_err(struct _adapter *padapter, u8 bgroup);
-int r8712_init_recv_priv(struct recv_priv *precvpriv, struct _adapter *padapter);
+int r8712_init_recv_priv(struct recv_priv *precvpriv,
+ struct _adapter *padapter);
void r8712_free_recv_priv(struct recv_priv *precvpriv);
int r8712_os_recv_resource_alloc(struct _adapter *padapter,
union recv_frame *precvframe);
@@ -24,4 +25,3 @@
void r8712_init_recv_timer(struct recv_reorder_ctrl *preorder_ctrl);
#endif
-
diff --git a/drivers/staging/rtl8712/rtl8712_event.h b/drivers/staging/rtl8712/rtl8712_event.h
index 48408f7..2731693 100644
--- a/drivers/staging/rtl8712/rtl8712_event.h
+++ b/drivers/staging/rtl8712/rtl8712_event.h
@@ -5,33 +5,33 @@
void r8712_got_addbareq_event_callback(struct _adapter *adapter , u8 *pbuf);
enum rtl8712_c2h_event {
- GEN_EVT_CODE(_Read_MACREG) = 0, /*0*/
+ GEN_EVT_CODE(_Read_MACREG) = 0, /*0*/
GEN_EVT_CODE(_Read_BBREG),
GEN_EVT_CODE(_Read_RFREG),
GEN_EVT_CODE(_Read_EEPROM),
GEN_EVT_CODE(_Read_EFUSE),
- GEN_EVT_CODE(_Read_CAM), /*5*/
+ GEN_EVT_CODE(_Read_CAM), /*5*/
GEN_EVT_CODE(_Get_BasicRate),
GEN_EVT_CODE(_Get_DataRate),
- GEN_EVT_CODE(_Survey), /*8*/
- GEN_EVT_CODE(_SurveyDone), /*9*/
+ GEN_EVT_CODE(_Survey), /*8*/
+ GEN_EVT_CODE(_SurveyDone), /*9*/
- GEN_EVT_CODE(_JoinBss) , /*10*/
+ GEN_EVT_CODE(_JoinBss), /*10*/
GEN_EVT_CODE(_AddSTA),
GEN_EVT_CODE(_DelSTA),
- GEN_EVT_CODE(_AtimDone) ,
+ GEN_EVT_CODE(_AtimDone),
GEN_EVT_CODE(_TX_Report),
- GEN_EVT_CODE(_CCX_Report), /*15*/
+ GEN_EVT_CODE(_CCX_Report), /*15*/
GEN_EVT_CODE(_DTM_Report),
GEN_EVT_CODE(_TX_Rate_Statistics),
GEN_EVT_CODE(_C2HLBK),
GEN_EVT_CODE(_FWDBG),
- GEN_EVT_CODE(_C2HFEEDBACK), /*20*/
+ GEN_EVT_CODE(_C2HFEEDBACK), /*20*/
GEN_EVT_CODE(_ADDBA),
GEN_EVT_CODE(_C2HBCN),
GEN_EVT_CODE(_ReportPwrState), /*filen: only for PCIE, USB*/
GEN_EVT_CODE(_WPS_PBC), /*24*/
- GEN_EVT_CODE(_ADDBAReq_Report), /*25*/
+ GEN_EVT_CODE(_ADDBAReq_Report), /*25*/
MAX_C2HEVT
};
@@ -48,7 +48,8 @@
{0, NULL},
{0, NULL},
{0, &r8712_survey_event_callback}, /*8*/
- {sizeof(struct surveydone_event), &r8712_surveydone_event_callback},/*9*/
+ {sizeof(struct surveydone_event),
+ &r8712_surveydone_event_callback}, /*9*/
{0, &r8712_joinbss_event_callback}, /*10*/
{sizeof(struct stassoc_event), &r8712_stassoc_event_callback},
@@ -59,8 +60,8 @@
{0, NULL},
{0, NULL},
{0, NULL},
- {0, NULL}, /*fwdbg_event_callback},*/
- {0, NULL}, /*20*/
+ {0, NULL}, /*fwdbg_event_callback},*/
+ {0, NULL}, /*20*/
{0, NULL},
{0, NULL},
{0, &r8712_cpwm_event_callback},
diff --git a/drivers/staging/rtl8712/rtl8712_hal.h b/drivers/staging/rtl8712/rtl8712_hal.h
index 13df200..66baa87 100644
--- a/drivers/staging/rtl8712/rtl8712_hal.h
+++ b/drivers/staging/rtl8712/rtl8712_hal.h
@@ -21,13 +21,13 @@
RTL8712_USB,
};
-enum RTL8712_RF_CONFIG{
+enum RTL8712_RF_CONFIG {
RTL8712_RF_1T1R,
RTL8712_RF_1T2R,
RTL8712_RF_2T2R
};
-enum _RTL8712_HCI_TYPE_{
+enum _RTL8712_HCI_TYPE_ {
RTL8712_HCI_TYPE_PCIE = 0x01,
RTL8712_HCI_TYPE_AP_PCIE = 0x81,
RTL8712_HCI_TYPE_USB = 0x02,
@@ -40,62 +40,62 @@
struct fw_priv { /*8-bytes alignment required*/
/*--- long word 0 ----*/
- unsigned char signature_0; /*0x12: CE product, 0x92: IT product*/
- unsigned char signature_1; /*0x87: CE product, 0x81: IT product*/
- unsigned char hci_sel; /*0x81: PCI-AP, 01:PCIe, 02: 92S-U, 0x82: USB-AP,
+ unsigned char signature_0; /*0x12: CE product, 0x92: IT product*/
+ unsigned char signature_1; /*0x87: CE product, 0x81: IT product*/
+ unsigned char hci_sel; /*0x81: PCI-AP, 01:PCIe, 02: 92S-U, 0x82: USB-AP,
* 0x12: 72S-U, 03:SDIO*/
- unsigned char chip_version; /*the same value as register value*/
- unsigned char customer_ID_0; /*customer ID low byte*/
- unsigned char customer_ID_1; /*customer ID high byte*/
- unsigned char rf_config; /*0x11: 1T1R, 0x12: 1T2R, 0x92: 1T2R turbo,
+ unsigned char chip_version; /*the same value as register value*/
+ unsigned char customer_ID_0; /*customer ID low byte*/
+ unsigned char customer_ID_1; /*customer ID high byte*/
+ unsigned char rf_config; /*0x11: 1T1R, 0x12: 1T2R, 0x92: 1T2R turbo,
* 0x22: 2T2R*/
- unsigned char usb_ep_num; /* 4: 4EP, 6: 6EP, 11: 11EP*/
+ unsigned char usb_ep_num; /* 4: 4EP, 6: 6EP, 11: 11EP*/
/*--- long word 1 ----*/
- unsigned char regulatory_class_0; /*regulatory class bit map 0*/
- unsigned char regulatory_class_1; /*regulatory class bit map 1*/
- unsigned char regulatory_class_2; /*regulatory class bit map 2*/
- unsigned char regulatory_class_3; /*regulatory class bit map 3*/
- unsigned char rfintfs; /* 0:SWSI, 1:HWSI, 2:HWPI*/
- unsigned char def_nettype;
- unsigned char turboMode;
- unsigned char lowPowerMode;/* 0: noral mode, 1: low power mode*/
+ unsigned char regulatory_class_0; /*regulatory class bit map 0*/
+ unsigned char regulatory_class_1; /*regulatory class bit map 1*/
+ unsigned char regulatory_class_2; /*regulatory class bit map 2*/
+ unsigned char regulatory_class_3; /*regulatory class bit map 3*/
+ unsigned char rfintfs; /* 0:SWSI, 1:HWSI, 2:HWPI*/
+ unsigned char def_nettype;
+ unsigned char turboMode;
+ unsigned char lowPowerMode;/* 0: noral mode, 1: low power mode*/
/*--- long word 2 ----*/
- unsigned char lbk_mode; /*0x00: normal, 0x03: MACLBK, 0x01: PHYLBK*/
- unsigned char mp_mode; /* 1: for MP use, 0: for normal driver */
- unsigned char vcsType; /* 0:off 1:on 2:auto */
- unsigned char vcsMode; /* 1:RTS/CTS 2:CTS to self */
- unsigned char rsvd022;
- unsigned char rsvd023;
- unsigned char rsvd024;
- unsigned char rsvd025;
+ unsigned char lbk_mode; /*0x00: normal, 0x03: MACLBK, 0x01: PHYLBK*/
+ unsigned char mp_mode; /* 1: for MP use, 0: for normal driver */
+ unsigned char vcsType; /* 0:off 1:on 2:auto */
+ unsigned char vcsMode; /* 1:RTS/CTS 2:CTS to self */
+ unsigned char rsvd022;
+ unsigned char rsvd023;
+ unsigned char rsvd024;
+ unsigned char rsvd025;
/*--- long word 3 ----*/
- unsigned char qos_en; /*1: QoS enable*/
- unsigned char bw_40MHz_en; /*1: 40MHz BW enable*/
- unsigned char AMSDU2AMPDU_en; /*1: 4181 convert AMSDU to AMPDU,
+ unsigned char qos_en; /*1: QoS enable*/
+ unsigned char bw_40MHz_en; /*1: 40MHz BW enable*/
+ unsigned char AMSDU2AMPDU_en; /*1: 4181 convert AMSDU to AMPDU,
* 0: disable*/
- unsigned char AMPDU_en; /*1: 11n AMPDU enable*/
- unsigned char rate_control_offload; /*1: FW offloads, 0: driver handles*/
- unsigned char aggregation_offload; /*1: FW offloads, 0: driver handles*/
- unsigned char rsvd030;
- unsigned char rsvd031;
+ unsigned char AMPDU_en; /*1: 11n AMPDU enable*/
+ unsigned char rate_control_offload; /*1: FW offloads,0: driver handles*/
+ unsigned char aggregation_offload; /*1: FW offloads,0: driver handles*/
+ unsigned char rsvd030;
+ unsigned char rsvd031;
/*--- long word 4 ----*/
- unsigned char beacon_offload; /* 1. FW offloads, 0: driver handles*/
- unsigned char MLME_offload; /* 2. FW offloads, 0: driver handles*/
- unsigned char hwpc_offload; /* 3. FW offloads, 0: driver handles*/
- unsigned char tcp_checksum_offload; /* 4. FW offloads, 0: driver handles*/
- unsigned char tcp_offload; /* 5. FW offloads, 0: driver handles*/
- unsigned char ps_control_offload; /* 6. FW offloads, 0: driver handles*/
- unsigned char WWLAN_offload; /* 7. FW offloads, 0: driver handles*/
- unsigned char rsvd040;
+ unsigned char beacon_offload; /* 1. FW offloads, 0: driver handles*/
+ unsigned char MLME_offload; /* 2. FW offloads, 0: driver handles*/
+ unsigned char hwpc_offload; /* 3. FW offloads, 0: driver handles*/
+ unsigned char tcp_checksum_offload; /*4. FW offloads,0: driver handles*/
+ unsigned char tcp_offload; /* 5. FW offloads, 0: driver handles*/
+ unsigned char ps_control_offload; /* 6. FW offloads, 0: driver handles*/
+ unsigned char WWLAN_offload; /* 7. FW offloads, 0: driver handles*/
+ unsigned char rsvd040;
/*--- long word 5 ----*/
- unsigned char tcp_tx_frame_len_L; /*tcp tx packet length low byte*/
- unsigned char tcp_tx_frame_len_H; /*tcp tx packet length high byte*/
- unsigned char tcp_rx_frame_len_L; /*tcp rx packet length low byte*/
- unsigned char tcp_rx_frame_len_H; /*tcp rx packet length high byte*/
- unsigned char rsvd050;
- unsigned char rsvd051;
- unsigned char rsvd052;
- unsigned char rsvd053;
+ unsigned char tcp_tx_frame_len_L; /*tcp tx packet length low byte*/
+ unsigned char tcp_tx_frame_len_H; /*tcp tx packet length high byte*/
+ unsigned char tcp_rx_frame_len_L; /*tcp rx packet length low byte*/
+ unsigned char tcp_rx_frame_len_H; /*tcp rx packet length high byte*/
+ unsigned char rsvd050;
+ unsigned char rsvd051;
+ unsigned char rsvd052;
+ unsigned char rsvd053;
};
struct fw_hdr {/*8-byte alinment required*/
diff --git a/drivers/staging/rtl8712/rtl8712_led.c b/drivers/staging/rtl8712/rtl8712_led.c
index 5024ee4..cb1751e 100644
--- a/drivers/staging/rtl8712/rtl8712_led.c
+++ b/drivers/staging/rtl8712/rtl8712_led.c
@@ -49,7 +49,7 @@
* LED object.
*===========================================================================
*/
-enum _LED_STATE_871x{
+enum _LED_STATE_871x {
LED_UNKNOWN = 0,
LED_ON = 1,
LED_OFF = 2,
diff --git a/drivers/staging/rtl8712/rtl8712_recv.c b/drivers/staging/rtl8712/rtl8712_recv.c
index 569e14b..625a8a0 100644
--- a/drivers/staging/rtl8712/rtl8712_recv.c
+++ b/drivers/staging/rtl8712/rtl8712_recv.c
@@ -251,7 +251,7 @@
recvframe_put(prframe, pnfhdr->len);
pfhdr->attrib.icv_len = pnfhdr->attrib.icv_len;
plist = get_next(plist);
- };
+ }
exit:
/* free the defrag_q queue and return the prframe */
r8712_free_recvframe_queue(defrag_q, pfree_recv_queue);
diff --git a/drivers/staging/rtl8712/rtl8712_recv.h b/drivers/staging/rtl8712/rtl8712_recv.h
index 4ba52b9..c48757f 100644
--- a/drivers/staging/rtl8712/rtl8712_recv.h
+++ b/drivers/staging/rtl8712/rtl8712_recv.h
@@ -93,7 +93,7 @@
end ----->
len = (unsigned int )(tail - data);
*/
-struct recv_frame_hdr{
+struct recv_frame_hdr {
struct list_head list;
_pkt *pkt;
_pkt *pkt_newalloc;
diff --git a/drivers/staging/rtl8712/rtl8712_xmit.h b/drivers/staging/rtl8712/rtl8712_xmit.h
index 5d77c51..12a080f 100644
--- a/drivers/staging/rtl8712/rtl8712_xmit.h
+++ b/drivers/staging/rtl8712/rtl8712_xmit.h
@@ -59,25 +59,16 @@
/*OFFSET 20*/
#define DISFB BIT(15)
-struct tx_desc{
-
+struct tx_desc {
/*DWORD 0*/
unsigned int txdw0;
-
unsigned int txdw1;
-
unsigned int txdw2;
-
unsigned int txdw3;
-
unsigned int txdw4;
-
unsigned int txdw5;
-
unsigned int txdw6;
-
unsigned int txdw7;
-
};
diff --git a/drivers/staging/rtl8712/rtl871x_cmd.c b/drivers/staging/rtl8712/rtl871x_cmd.c
index fbb2e4e..ba92762 100644
--- a/drivers/staging/rtl8712/rtl871x_cmd.c
+++ b/drivers/staging/rtl8712/rtl871x_cmd.c
@@ -431,8 +431,7 @@
}
psecnetwork = (struct ndis_wlan_bssid_ex *)&psecuritypriv->sec_bss;
if (psecnetwork == NULL) {
- if (pcmd != NULL)
- kfree((unsigned char *)pcmd);
+ kfree(pcmd);
return _FAIL;
}
memset(psecnetwork, 0, t_len);
@@ -478,8 +477,8 @@
* to avoid some IOT issues, especially for Realtek 8192u
* SoftAP.
*/
- if ((padapter->securitypriv.PrivacyAlgrthm != _WEP40_ ) &&
- (padapter->securitypriv.PrivacyAlgrthm != _WEP104_ )) {
+ if ((padapter->securitypriv.PrivacyAlgrthm != _WEP40_) &&
+ (padapter->securitypriv.PrivacyAlgrthm != _WEP104_)) {
/* restructure_ht_ie */
r8712_restructure_ht_ie(padapter,
&pnetwork->network.IEs[0],
diff --git a/drivers/staging/rtl8712/rtl871x_cmd.h b/drivers/staging/rtl8712/rtl871x_cmd.h
index 2dc7847..dcf256d 100644
--- a/drivers/staging/rtl8712/rtl871x_cmd.h
+++ b/drivers/staging/rtl8712/rtl871x_cmd.h
@@ -562,54 +562,54 @@
};
/*to get TX,RX retry count*/
-struct gettxretrycnt_parm{
+struct gettxretrycnt_parm {
unsigned int rsvd;
};
-struct gettxretrycnt_rsp{
+struct gettxretrycnt_rsp {
unsigned long tx_retrycnt;
};
-struct getrxretrycnt_parm{
+struct getrxretrycnt_parm {
unsigned int rsvd;
};
-struct getrxretrycnt_rsp{
+struct getrxretrycnt_rsp {
unsigned long rx_retrycnt;
};
/*to get BCNOK,BCNERR count*/
-struct getbcnokcnt_parm{
+struct getbcnokcnt_parm {
unsigned int rsvd;
};
-struct getbcnokcnt_rsp{
- unsigned long bcnokcnt;
+struct getbcnokcnt_rsp {
+ unsigned long bcnokcnt;
};
-struct getbcnerrcnt_parm{
+struct getbcnerrcnt_parm {
unsigned int rsvd;
};
-struct getbcnerrcnt_rsp{
+struct getbcnerrcnt_rsp {
unsigned long bcnerrcnt;
};
/* to get current TX power level*/
-struct getcurtxpwrlevel_parm{
+struct getcurtxpwrlevel_parm {
unsigned int rsvd;
};
-struct getcurtxpwrlevel_rsp{
+struct getcurtxpwrlevel_rsp {
unsigned short tx_power;
};
/*dynamic on/off DIG*/
-struct setdig_parm{
+struct setdig_parm {
unsigned char dig_on; /* 1:on , 0:off */
};
/*dynamic on/off RA*/
-struct setra_parm{
+struct setra_parm {
unsigned char ra_on; /* 1:on , 0:off */
};
diff --git a/drivers/staging/rtl8712/rtl871x_event.h b/drivers/staging/rtl8712/rtl871x_event.h
index d452293..6ce0676 100644
--- a/drivers/staging/rtl8712/rtl871x_event.h
+++ b/drivers/staging/rtl8712/rtl871x_event.h
@@ -45,8 +45,8 @@
};
struct stadel_event {
- unsigned char macaddr[6];
- unsigned char rsvd[2];
+ unsigned char macaddr[6];
+ unsigned char rsvd[2];
};
struct addba_event {
@@ -61,7 +61,7 @@
};
#define C2HEVENT_SZ 32
-struct event_node{
+struct event_node {
unsigned char *node;
unsigned char evt_code;
unsigned short evt_sz;
@@ -85,9 +85,9 @@
};
struct ADDBA_Req_Report_parm {
- unsigned char MacAddress[ETH_ALEN];
- unsigned short StartSeqNum;
- unsigned char tid;
+ unsigned char MacAddress[ETH_ALEN];
+ unsigned short StartSeqNum;
+ unsigned char tid;
};
#include "rtl8712_event.h"
diff --git a/drivers/staging/rtl8712/rtl871x_io.c b/drivers/staging/rtl8712/rtl871x_io.c
index e6e3c37..ca84ee0 100644
--- a/drivers/staging/rtl8712/rtl871x_io.c
+++ b/drivers/staging/rtl8712/rtl871x_io.c
@@ -73,8 +73,7 @@
goto _init_intf_hdl_fail;
return _SUCCESS;
_init_intf_hdl_fail:
- if (pintf_priv)
- kfree((u8 *)pintf_priv);
+ kfree(pintf_priv);
return _FAIL;
}
@@ -84,8 +83,7 @@
unload_intf_priv = &r8712_usb_unload_intf_priv;
unload_intf_priv(pintfpriv);
- if (pintfpriv)
- kfree((u8 *)pintfpriv);
+ kfree(pintfpriv);
}
static uint register_intf_hdl(u8 *dev, struct intf_hdl *pintfhdl)
diff --git a/drivers/staging/rtl8712/rtl871x_ioctl_linux.c b/drivers/staging/rtl8712/rtl871x_ioctl_linux.c
index bd315c7..40e6b5c 100644
--- a/drivers/staging/rtl8712/rtl871x_ioctl_linux.c
+++ b/drivers/staging/rtl8712/rtl871x_ioctl_linux.c
@@ -291,7 +291,8 @@
memset(buf, 0, MAX_WPA_IE_LEN);
n = sprintf(buf, "wpa_ie=");
for (i = 0; i < wpa_len; i++) {
- n += snprintf(buf + n, MAX_WPA_IE_LEN - n, "%02x", wpa_ie[i]);
+ n += snprintf(buf + n, MAX_WPA_IE_LEN - n,
+ "%02x", wpa_ie[i]);
if (n >= MAX_WPA_IE_LEN)
break;
}
@@ -310,7 +311,8 @@
memset(buf, 0, MAX_WPA_IE_LEN);
n = sprintf(buf, "rsn_ie=");
for (i = 0; i < rsn_len; i++) {
- n += snprintf(buf + n, MAX_WPA_IE_LEN - n, "%02x", rsn_ie[i]);
+ n += snprintf(buf + n, MAX_WPA_IE_LEN - n,
+ "%02x", rsn_ie[i]);
if (n >= MAX_WPA_IE_LEN)
break;
}
@@ -1732,8 +1734,7 @@
memcpy(param + 1, pext + 1, pext->key_len);
}
ret = wpa_set_encryption(dev, param, param_len);
- if (param)
- kfree((u8 *)param);
+ kfree(param);
return ret;
}
diff --git a/drivers/staging/rtl8712/rtl871x_ioctl_rtl.c b/drivers/staging/rtl8712/rtl871x_ioctl_rtl.c
index 7adbe82..9a33eae 100644
--- a/drivers/staging/rtl8712/rtl871x_ioctl_rtl.c
+++ b/drivers/staging/rtl8712/rtl871x_ioctl_rtl.c
@@ -493,7 +493,7 @@
return status;
}
-enum _CONNECT_STATE_{
+enum _CONNECT_STATE_ {
CHECKINGSTATUS,
ASSOCIATED,
ADHOCMODE,
diff --git a/drivers/staging/rtl8712/rtl871x_ioctl_set.c b/drivers/staging/rtl8712/rtl871x_ioctl_set.c
index 8b1451d..8486eb1 100644
--- a/drivers/staging/rtl8712/rtl871x_ioctl_set.c
+++ b/drivers/staging/rtl8712/rtl871x_ioctl_set.c
@@ -68,7 +68,10 @@
pmlmepriv->fw_state |= _FW_UNDER_LINKING;
pmlmepriv->pscanned = plist;
pmlmepriv->to_join = true;
- if (_queue_empty(queue) == true) {
+
+ /* adhoc mode will start with an empty queue, but skip checking */
+ if (!check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) &&
+ _queue_empty(queue)) {
if (pmlmepriv->fw_state & _FW_UNDER_LINKING)
pmlmepriv->fw_state ^= _FW_UNDER_LINKING;
/* when set_ssid/set_bssid for do_join(), but scanning queue
diff --git a/drivers/staging/rtl8712/rtl871x_ioctl_set.h b/drivers/staging/rtl8712/rtl871x_ioctl_set.h
index 283afbf..8dff2b1 100644
--- a/drivers/staging/rtl8712/rtl871x_ioctl_set.h
+++ b/drivers/staging/rtl8712/rtl871x_ioctl_set.h
@@ -6,19 +6,27 @@
typedef u8 NDIS_802_11_PMKID_VALUE[16];
struct BSSIDInfo {
- unsigned char BSSID[6];
- NDIS_802_11_PMKID_VALUE PMKID;
+ unsigned char BSSID[6];
+ NDIS_802_11_PMKID_VALUE PMKID;
};
u8 r8712_set_802_11_authentication_mode(struct _adapter *pdapter,
enum NDIS_802_11_AUTHENTICATION_MODE authmode);
+
u8 r8712_set_802_11_bssid(struct _adapter *padapter, u8 *bssid);
-u8 r8712_set_802_11_add_wep(struct _adapter *padapter, struct NDIS_802_11_WEP *wep);
+
+u8 r8712_set_802_11_add_wep(struct _adapter *padapter,
+ struct NDIS_802_11_WEP *wep);
+
u8 r8712_set_802_11_disassociate(struct _adapter *padapter);
+
u8 r8712_set_802_11_bssid_list_scan(struct _adapter *padapter);
+
u8 r8712_set_802_11_infrastructure_mode(struct _adapter *padapter,
enum NDIS_802_11_NETWORK_INFRASTRUCTURE networktype);
-void r8712_set_802_11_ssid(struct _adapter *padapter, struct ndis_802_11_ssid *ssid);
+
+void r8712_set_802_11_ssid(struct _adapter *padapter,
+ struct ndis_802_11_ssid *ssid);
#endif
diff --git a/drivers/staging/rtl8712/rtl871x_mp.c b/drivers/staging/rtl8712/rtl871x_mp.c
index 427467c..41e00a2 100644
--- a/drivers/staging/rtl8712/rtl871x_mp.c
+++ b/drivers/staging/rtl8712/rtl871x_mp.c
@@ -217,7 +217,10 @@
return new_value;
}
-static u8 set_bb_reg(struct _adapter *pAdapter, u16 offset, u32 bitmask, u32 value)
+static u8 set_bb_reg(struct _adapter *pAdapter,
+ u16 offset,
+ u32 bitmask,
+ u32 value)
{
u32 org_value, bit_shift, new_value;
@@ -274,8 +277,7 @@
pparm = (struct SetChannel_parm *)_malloc(sizeof(struct
SetChannel_parm));
if (pparm == NULL) {
- if (pcmd != NULL)
- kfree((u8 *)pcmd);
+ kfree(pcmd);
return;
}
pparm->curr_ch = pAdapter->mppriv.curr_ch;
diff --git a/drivers/staging/rtl8712/rtl871x_mp_ioctl.h b/drivers/staging/rtl8712/rtl871x_mp_ioctl.h
index fdd2278..67759c3 100644
--- a/drivers/staging/rtl8712/rtl871x_mp_ioctl.h
+++ b/drivers/staging/rtl8712/rtl871x_mp_ioctl.h
@@ -281,23 +281,23 @@
MP_ERR_MODE
};
-struct rwreg_param{
+struct rwreg_param {
unsigned int offset;
unsigned int width;
unsigned int value;
};
-struct bbreg_param{
+struct bbreg_param {
unsigned int offset;
unsigned int phymask;
unsigned int value;
};
-struct txpower_param{
+struct txpower_param {
unsigned int pwr_index;
};
-struct datarate_param{
+struct datarate_param {
unsigned int rate_index;
};
@@ -321,7 +321,7 @@
unsigned int oid;
};
-struct mp_ioctl_param{
+struct mp_ioctl_param {
unsigned int subcode;
unsigned int len;
unsigned char data[0];
diff --git a/drivers/staging/rtl8712/rtl871x_recv.c b/drivers/staging/rtl8712/rtl871x_recv.c
index a3165e6..aec83dd 100644
--- a/drivers/staging/rtl8712/rtl871x_recv.c
+++ b/drivers/staging/rtl8712/rtl871x_recv.c
@@ -307,9 +307,9 @@
return _SUCCESS;
}
-static sint sta2sta_data_frame(struct _adapter *adapter, union recv_frame *precv_frame,
- struct sta_info **psta
-)
+static sint sta2sta_data_frame(struct _adapter *adapter,
+ union recv_frame *precv_frame,
+ struct sta_info **psta)
{
u8 *ptr = precv_frame->u.hdr.rx_data;
sint ret = _SUCCESS;
@@ -373,8 +373,9 @@
return ret;
}
-static sint ap2sta_data_frame(struct _adapter *adapter, union recv_frame *precv_frame,
- struct sta_info **psta)
+static sint ap2sta_data_frame(struct _adapter *adapter,
+ union recv_frame *precv_frame,
+ struct sta_info **psta)
{
u8 *ptr = precv_frame->u.hdr.rx_data;
struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
@@ -431,8 +432,9 @@
return _SUCCESS;
}
-static sint sta2ap_data_frame(struct _adapter *adapter, union recv_frame *precv_frame,
- struct sta_info **psta)
+static sint sta2ap_data_frame(struct _adapter *adapter,
+ union recv_frame *precv_frame,
+ struct sta_info **psta)
{
struct rx_pkt_attrib *pattrib = &precv_frame->u.hdr.attrib;
struct sta_priv *pstapriv = &adapter->stapriv;
diff --git a/drivers/staging/rtl8712/rtl871x_recv.h b/drivers/staging/rtl8712/rtl871x_recv.h
index bf8115d..cc7a72f 100644
--- a/drivers/staging/rtl8712/rtl871x_recv.h
+++ b/drivers/staging/rtl8712/rtl871x_recv.h
@@ -19,9 +19,9 @@
/* for Rx reordering buffer control */
struct recv_reorder_ctrl {
struct _adapter *padapter;
- u16 indicate_seq;/* =wstart_b, init_value=0xffff */
+ u16 indicate_seq; /* =wstart_b, init_value=0xffff */
u16 wend_b;
- u8 wsize_b;
+ u8 wsize_b;
struct __queue pending_recvframe_queue;
struct timer_list reordering_ctrl_timer;
};
diff --git a/drivers/staging/rtl8712/rtl871x_rf.h b/drivers/staging/rtl8712/rtl871x_rf.h
index c709d8c..6c54966 100644
--- a/drivers/staging/rtl8712/rtl871x_rf.h
+++ b/drivers/staging/rtl8712/rtl871x_rf.h
@@ -22,7 +22,7 @@
u8 modem;
};
-enum _REG_PREAMBLE_MODE{
+enum _REG_PREAMBLE_MODE {
PREAMBLE_LONG = 1,
PREAMBLE_AUTO = 2,
PREAMBLE_SHORT = 3,
diff --git a/drivers/staging/rtl8712/rtl871x_security.h b/drivers/staging/rtl8712/rtl871x_security.h
index 782b70a..bff71d2 100644
--- a/drivers/staging/rtl8712/rtl871x_security.h
+++ b/drivers/staging/rtl8712/rtl871x_security.h
@@ -21,30 +21,31 @@
#ifndef Ndis802_11AuthModeWPA2PSK
#define Ndis802_11AuthModeWPA2PSK (Ndis802_11AuthModeWPANone + 2)
#endif
+
union pn48 {
u64 val;
#if defined(__BIG_ENDIAN)
-struct {
- u8 TSC7;
- u8 TSC6;
- u8 TSC5;
- u8 TSC4;
- u8 TSC3;
- u8 TSC2;
- u8 TSC1;
- u8 TSC0;
-} _byte_;
+ struct {
+ u8 TSC7;
+ u8 TSC6;
+ u8 TSC5;
+ u8 TSC4;
+ u8 TSC3;
+ u8 TSC2;
+ u8 TSC1;
+ u8 TSC0;
+ } _byte_;
#else
-struct {
- u8 TSC0;
- u8 TSC1;
- u8 TSC2;
- u8 TSC3;
- u8 TSC4;
- u8 TSC5;
- u8 TSC6;
- u8 TSC7;
-} _byte_;
+ struct {
+ u8 TSC0;
+ u8 TSC1;
+ u8 TSC2;
+ u8 TSC3;
+ u8 TSC4;
+ u8 TSC5;
+ u8 TSC6;
+ u8 TSC7;
+ } _byte_;
#endif
};
@@ -174,11 +175,11 @@
};
void seccalctkipmic(
- u8 *key,
- u8 *header,
- u8 *data,
- u32 data_len,
- u8 *Miccode,
+ u8 *key,
+ u8 *header,
+ u8 *data,
+ u32 data_len,
+ u8 *Miccode,
u8 priority);
void r8712_secmicsetkey(struct mic_data *pmicdata, u8 * key);
diff --git a/drivers/staging/rtl8712/rtl871x_xmit.c b/drivers/staging/rtl8712/rtl871x_xmit.c
index 75f1a6bb..ccf0891 100644
--- a/drivers/staging/rtl8712/rtl871x_xmit.c
+++ b/drivers/staging/rtl8712/rtl871x_xmit.c
@@ -996,8 +996,7 @@
{
struct xmit_priv *pxmitpriv = &padapter->xmitpriv;
- if (pxmitpriv->hwxmits)
- kfree((u8 *)pxmitpriv->hwxmits);
+ kfree(pxmitpriv->hwxmits);
}
static void init_hwxmits(struct hw_xmit *phwxmit, sint entry)
diff --git a/drivers/staging/rtl8712/rtl871x_xmit.h b/drivers/staging/rtl8712/rtl871x_xmit.h
index d518ce8..df13e67 100644
--- a/drivers/staging/rtl8712/rtl871x_xmit.h
+++ b/drivers/staging/rtl8712/rtl871x_xmit.h
@@ -244,7 +244,8 @@
struct pkt_attrib *pattrib);
int r8712_txframes_sta_ac_pending(struct _adapter *padapter,
struct pkt_attrib *pattrib);
-sint _r8712_init_xmit_priv(struct xmit_priv *pxmitpriv, struct _adapter *padapter);
+sint _r8712_init_xmit_priv(struct xmit_priv *pxmitpriv,
+ struct _adapter *padapter);
void _free_xmit_priv(struct xmit_priv *pxmitpriv);
void r8712_free_xmitframe_ex(struct xmit_priv *pxmitpriv,
struct xmit_frame *pxmitframe);
diff --git a/drivers/staging/rtl8712/wifi.h b/drivers/staging/rtl8712/wifi.h
index 86d4b98..6032cdc 100644
--- a/drivers/staging/rtl8712/wifi.h
+++ b/drivers/staging/rtl8712/wifi.h
@@ -39,38 +39,35 @@
};
enum WIFI_FRAME_SUBTYPE {
-
- /* below is for mgt frame */
- WIFI_ASSOCREQ = (0 | WIFI_MGT_TYPE),
- WIFI_ASSOCRSP = (BIT(4) | WIFI_MGT_TYPE),
- WIFI_REASSOCREQ = (BIT(5) | WIFI_MGT_TYPE),
- WIFI_REASSOCRSP = (BIT(5) | BIT(4) | WIFI_MGT_TYPE),
- WIFI_PROBEREQ = (BIT(6) | WIFI_MGT_TYPE),
- WIFI_PROBERSP = (BIT(6) | BIT(4) | WIFI_MGT_TYPE),
- WIFI_BEACON = (BIT(7) | WIFI_MGT_TYPE),
- WIFI_ATIM = (BIT(7) | BIT(4) | WIFI_MGT_TYPE),
- WIFI_DISASSOC = (BIT(7) | BIT(5) | WIFI_MGT_TYPE),
- WIFI_AUTH = (BIT(7) | BIT(5) | BIT(4) | WIFI_MGT_TYPE),
- WIFI_DEAUTH = (BIT(7) | BIT(6) | WIFI_MGT_TYPE),
- WIFI_ACTION = (BIT(7) | BIT(6) | BIT(4) | WIFI_MGT_TYPE),
-
- /* below is for control frame */
- WIFI_PSPOLL = (BIT(7) | BIT(5) | WIFI_CTRL_TYPE),
- WIFI_RTS = (BIT(7) | BIT(5) | BIT(4) | WIFI_CTRL_TYPE),
- WIFI_CTS = (BIT(7) | BIT(6) | WIFI_CTRL_TYPE),
- WIFI_ACK = (BIT(7) | BIT(6) | BIT(4) | WIFI_CTRL_TYPE),
- WIFI_CFEND = (BIT(7) | BIT(6) | BIT(5) | WIFI_CTRL_TYPE),
- WIFI_CFEND_CFACK = (BIT(7) | BIT(6) | BIT(5) | BIT(4) | WIFI_CTRL_TYPE),
-
- /* below is for data frame */
- WIFI_DATA = (0 | WIFI_DATA_TYPE),
- WIFI_DATA_CFACK = (BIT(4) | WIFI_DATA_TYPE),
- WIFI_DATA_CFPOLL = (BIT(5) | WIFI_DATA_TYPE),
- WIFI_DATA_CFACKPOLL = (BIT(5) | BIT(4) | WIFI_DATA_TYPE),
- WIFI_DATA_NULL = (BIT(6) | WIFI_DATA_TYPE),
- WIFI_CF_ACK = (BIT(6) | BIT(4) | WIFI_DATA_TYPE),
- WIFI_CF_POLL = (BIT(6) | BIT(5) | WIFI_DATA_TYPE),
- WIFI_CF_ACKPOLL = (BIT(6) | BIT(5) | BIT(4) | WIFI_DATA_TYPE),
+ /* below is for mgt frame */
+ WIFI_ASSOCREQ = (0 | WIFI_MGT_TYPE),
+ WIFI_ASSOCRSP = (BIT(4) | WIFI_MGT_TYPE),
+ WIFI_REASSOCREQ = (BIT(5) | WIFI_MGT_TYPE),
+ WIFI_REASSOCRSP = (BIT(5) | BIT(4) | WIFI_MGT_TYPE),
+ WIFI_PROBEREQ = (BIT(6) | WIFI_MGT_TYPE),
+ WIFI_PROBERSP = (BIT(6) | BIT(4) | WIFI_MGT_TYPE),
+ WIFI_BEACON = (BIT(7) | WIFI_MGT_TYPE),
+ WIFI_ATIM = (BIT(7) | BIT(4) | WIFI_MGT_TYPE),
+ WIFI_DISASSOC = (BIT(7) | BIT(5) | WIFI_MGT_TYPE),
+ WIFI_AUTH = (BIT(7) | BIT(5) | BIT(4) | WIFI_MGT_TYPE),
+ WIFI_DEAUTH = (BIT(7) | BIT(6) | WIFI_MGT_TYPE),
+ WIFI_ACTION = (BIT(7) | BIT(6) | BIT(4) | WIFI_MGT_TYPE),
+ /* below is for control frame */
+ WIFI_PSPOLL = (BIT(7) | BIT(5) | WIFI_CTRL_TYPE),
+ WIFI_RTS = (BIT(7) | BIT(5) | BIT(4) | WIFI_CTRL_TYPE),
+ WIFI_CTS = (BIT(7) | BIT(6) | WIFI_CTRL_TYPE),
+ WIFI_ACK = (BIT(7) | BIT(6) | BIT(4) | WIFI_CTRL_TYPE),
+ WIFI_CFEND = (BIT(7) | BIT(6) | BIT(5) | WIFI_CTRL_TYPE),
+ WIFI_CFEND_CFACK = (BIT(7) | BIT(6) | BIT(5) | BIT(4) | WIFI_CTRL_TYPE),
+ /* below is for data frame */
+ WIFI_DATA = (0 | WIFI_DATA_TYPE),
+ WIFI_DATA_CFACK = (BIT(4) | WIFI_DATA_TYPE),
+ WIFI_DATA_CFPOLL = (BIT(5) | WIFI_DATA_TYPE),
+ WIFI_DATA_CFACKPOLL = (BIT(5) | BIT(4) | WIFI_DATA_TYPE),
+ WIFI_DATA_NULL = (BIT(6) | WIFI_DATA_TYPE),
+ WIFI_CF_ACK = (BIT(6) | BIT(4) | WIFI_DATA_TYPE),
+ WIFI_CF_POLL = (BIT(6) | BIT(5) | WIFI_DATA_TYPE),
+ WIFI_CF_ACKPOLL = (BIT(6) | BIT(5) | BIT(4) | WIFI_DATA_TYPE),
};
enum WIFI_REASON_CODE {
@@ -84,7 +81,6 @@
_RSON_CLS3_ = 7,
_RSON_DISAOC_STA_LEAVING_ = 8,
_RSON_ASOC_NOT_AUTH_ = 9,
-
/* WPA reason */
_RSON_INVALID_IE_ = 13,
_RSON_MIC_FAILURE_ = 14,
@@ -97,7 +93,6 @@
_RSON_UNSUPPORT_RSNE_VER_ = 21,
_RSON_INVALID_RSNE_CAP_ = 22,
_RSON_IEEE_802DOT1X_AUTH_FAIL_ = 23,
-
/* below are Realtek definitions */
_RSON_PMK_NOT_AVAILABLE_ = 24,
};
diff --git a/drivers/staging/rtl8712/wlan_bssdef.h b/drivers/staging/rtl8712/wlan_bssdef.h
index 6d92952..0d90e1f 100644
--- a/drivers/staging/rtl8712/wlan_bssdef.h
+++ b/drivers/staging/rtl8712/wlan_bssdef.h
@@ -13,23 +13,23 @@
typedef unsigned char NDIS_802_11_RATES_EX[NDIS_802_11_LENGTH_RATES_EX];
struct ndis_802_11_ssid {
- u32 SsidLength;
- u8 Ssid[32];
+ u32 SsidLength;
+ u8 Ssid[32];
};
enum NDIS_802_11_NETWORK_TYPE {
- Ndis802_11FH,
- Ndis802_11DS,
- Ndis802_11OFDM5,
- Ndis802_11OFDM24,
- Ndis802_11NetworkTypeMax /* not a real type, defined as an upper bound */
+ Ndis802_11FH,
+ Ndis802_11DS,
+ Ndis802_11OFDM5,
+ Ndis802_11OFDM24,
+ Ndis802_11NetworkTypeMax /* not a real type, defined as an upper bound*/
};
struct NDIS_802_11_CONFIGURATION_FH {
- u32 Length; /* Length of structure */
- u32 HopPattern; /* As defined by 802.11, MSB set */
- u32 HopSet; /* to one if non-802.11 */
- u32 DwellTime; /* units are Kusec */
+ u32 Length; /* Length of structure */
+ u32 HopPattern; /* As defined by 802.11, MSB set */
+ u32 HopSet; /* to one if non-802.11 */
+ u32 DwellTime; /* units are Kusec */
};
/*
@@ -37,25 +37,25 @@
ODI Handler will convert the channel number to freq. number.
*/
struct NDIS_802_11_CONFIGURATION {
- u32 Length; /* Length of structure */
- u32 BeaconPeriod; /* units are Kusec */
- u32 ATIMWindow; /* units are Kusec */
- u32 DSConfig; /* Frequency, units are kHz */
- struct NDIS_802_11_CONFIGURATION_FH FHConfig;
+ u32 Length; /* Length of structure */
+ u32 BeaconPeriod; /* units are Kusec */
+ u32 ATIMWindow; /* units are Kusec */
+ u32 DSConfig; /* Frequency, units are kHz */
+ struct NDIS_802_11_CONFIGURATION_FH FHConfig;
};
enum NDIS_802_11_NETWORK_INFRASTRUCTURE {
- Ndis802_11IBSS,
- Ndis802_11Infrastructure,
- Ndis802_11AutoUnknown,
- Ndis802_11InfrastructureMax, /* Not a real value, defined as upper bound */
- Ndis802_11APMode
+ Ndis802_11IBSS,
+ Ndis802_11Infrastructure,
+ Ndis802_11AutoUnknown,
+ Ndis802_11InfrastructureMax, /*Not a real value,defined as upper bound*/
+ Ndis802_11APMode
};
struct NDIS_802_11_FIXED_IEs {
- u8 Timestamp[8];
- u16 BeaconInterval;
- u16 Capabilities;
+ u8 Timestamp[8];
+ u16 BeaconInterval;
+ u16 Capabilities;
};
/*
@@ -70,44 +70,44 @@
*/
struct ndis_wlan_bssid_ex {
- u32 Length;
- unsigned char MacAddress[6];
- u8 Reserved[2];
- struct ndis_802_11_ssid Ssid;
- u32 Privacy;
- s32 Rssi;
- enum NDIS_802_11_NETWORK_TYPE NetworkTypeInUse;
- struct NDIS_802_11_CONFIGURATION Configuration;
- enum NDIS_802_11_NETWORK_INFRASTRUCTURE InfrastructureMode;
- NDIS_802_11_RATES_EX SupportedRates;
- u32 IELength;
-/*(timestamp, beacon interval, and capability information) */
- u8 IEs[MAX_IE_SZ];
+ u32 Length;
+ unsigned char MacAddress[6];
+ u8 Reserved[2];
+ struct ndis_802_11_ssid Ssid;
+ u32 Privacy;
+ s32 Rssi;
+ enum NDIS_802_11_NETWORK_TYPE NetworkTypeInUse;
+ struct NDIS_802_11_CONFIGURATION Configuration;
+ enum NDIS_802_11_NETWORK_INFRASTRUCTURE InfrastructureMode;
+ NDIS_802_11_RATES_EX SupportedRates;
+ u32 IELength;
+ /*(timestamp, beacon interval, and capability information) */
+ u8 IEs[MAX_IE_SZ];
};
enum NDIS_802_11_AUTHENTICATION_MODE {
- Ndis802_11AuthModeOpen,
- Ndis802_11AuthModeShared,
- Ndis802_11AuthModeAutoSwitch,
- Ndis802_11AuthModeWPA,
- Ndis802_11AuthModeWPAPSK,
- Ndis802_11AuthModeWPANone,
- Ndis802_11AuthModeMax /* Not a real mode, defined as upper bound */
+ Ndis802_11AuthModeOpen,
+ Ndis802_11AuthModeShared,
+ Ndis802_11AuthModeAutoSwitch,
+ Ndis802_11AuthModeWPA,
+ Ndis802_11AuthModeWPAPSK,
+ Ndis802_11AuthModeWPANone,
+ Ndis802_11AuthModeMax /* Not a real mode, defined as upper bound */
};
enum {
- Ndis802_11WEPEnabled,
- Ndis802_11Encryption1Enabled = Ndis802_11WEPEnabled,
- Ndis802_11WEPDisabled,
- Ndis802_11EncryptionDisabled = Ndis802_11WEPDisabled,
- Ndis802_11WEPKeyAbsent,
- Ndis802_11Encryption1KeyAbsent = Ndis802_11WEPKeyAbsent,
- Ndis802_11WEPNotSupported,
- Ndis802_11EncryptionNotSupported = Ndis802_11WEPNotSupported,
- Ndis802_11Encryption2Enabled,
- Ndis802_11Encryption2KeyAbsent,
- Ndis802_11Encryption3Enabled,
- Ndis802_11Encryption3KeyAbsent
+ Ndis802_11WEPEnabled,
+ Ndis802_11Encryption1Enabled = Ndis802_11WEPEnabled,
+ Ndis802_11WEPDisabled,
+ Ndis802_11EncryptionDisabled = Ndis802_11WEPDisabled,
+ Ndis802_11WEPKeyAbsent,
+ Ndis802_11Encryption1KeyAbsent = Ndis802_11WEPKeyAbsent,
+ Ndis802_11WEPNotSupported,
+ Ndis802_11EncryptionNotSupported = Ndis802_11WEPNotSupported,
+ Ndis802_11Encryption2Enabled,
+ Ndis802_11Encryption2KeyAbsent,
+ Ndis802_11Encryption3Enabled,
+ Ndis802_11Encryption3KeyAbsent
};
#define NDIS_802_11_AI_REQFI_CAPABILITIES 1
@@ -119,51 +119,51 @@
#define NDIS_802_11_AI_RESFI_ASSOCIATIONID 4
struct NDIS_802_11_AI_REQFI {
- u16 Capabilities;
- u16 ListenInterval;
- unsigned char CurrentAPAddress[6];
+ u16 Capabilities;
+ u16 ListenInterval;
+ unsigned char CurrentAPAddress[6];
};
struct NDIS_802_11_AI_RESFI {
- u16 Capabilities;
- u16 StatusCode;
- u16 AssociationId;
+ u16 Capabilities;
+ u16 StatusCode;
+ u16 AssociationId;
};
struct NDIS_802_11_ASSOCIATION_INFORMATION {
- u32 Length;
- u16 AvailableRequestFixedIEs;
- struct NDIS_802_11_AI_REQFI RequestFixedIEs;
- u32 RequestIELength;
- u32 OffsetRequestIEs;
- u16 AvailableResponseFixedIEs;
- struct NDIS_802_11_AI_RESFI ResponseFixedIEs;
- u32 ResponseIELength;
- u32 OffsetResponseIEs;
+ u32 Length;
+ u16 AvailableRequestFixedIEs;
+ struct NDIS_802_11_AI_REQFI RequestFixedIEs;
+ u32 RequestIELength;
+ u32 OffsetRequestIEs;
+ u16 AvailableResponseFixedIEs;
+ struct NDIS_802_11_AI_RESFI ResponseFixedIEs;
+ u32 ResponseIELength;
+ u32 OffsetResponseIEs;
};
/* Key mapping keys require a BSSID*/
struct NDIS_802_11_KEY {
- u32 Length; /* Length of this structure */
- u32 KeyIndex;
- u32 KeyLength; /* length of key in bytes */
- unsigned char BSSID[6];
- unsigned long long KeyRSC;
- u8 KeyMaterial[32]; /* variable length */
+ u32 Length; /* Length of this structure */
+ u32 KeyIndex;
+ u32 KeyLength; /* length of key in bytes */
+ unsigned char BSSID[6];
+ unsigned long long KeyRSC;
+ u8 KeyMaterial[32]; /* variable length */
};
struct NDIS_802_11_REMOVE_KEY {
- u32 Length; /* Length of this structure */
- u32 KeyIndex;
- unsigned char BSSID[6];
+ u32 Length; /* Length of this structure */
+ u32 KeyIndex;
+ unsigned char BSSID[6];
};
struct NDIS_802_11_WEP {
- u32 Length; /* Length of this structure */
- u32 KeyIndex; /* 0 is the per-client key,
- * 1-N are the global keys */
- u32 KeyLength; /* length of key in bytes */
- u8 KeyMaterial[16];/* variable length depending on above field */
+ u32 Length; /* Length of this structure */
+ u32 KeyIndex; /* 0 is the per-client key,
+ * 1-N are the global keys */
+ u32 KeyLength; /* length of key in bytes */
+ u8 KeyMaterial[16]; /* variable length depending on above field */
};
/* mask for authentication/integrity fields */
@@ -192,15 +192,15 @@
};
enum VRTL_CARRIER_SENSE {
- DISABLE_VCS,
- ENABLE_VCS,
- AUTO_VCS
+ DISABLE_VCS,
+ ENABLE_VCS,
+ AUTO_VCS
};
enum VCS_TYPE {
- NONE_VCS,
- RTS_CTS,
- CTS_TO_SELF
+ NONE_VCS,
+ RTS_CTS,
+ CTS_TO_SELF
};
#define PWR_CAM 0
@@ -211,9 +211,9 @@
enum UAPSD_MAX_SP {
NO_LIMIT,
- TWO_MSDU,
- FOUR_MSDU,
- SIX_MSDU
+ TWO_MSDU,
+ FOUR_MSDU,
+ SIX_MSDU
};
#define NUM_PRE_AUTH_KEY 16
@@ -223,18 +223,18 @@
* WPA2
*/
struct wlan_bssid_ex {
- u32 Length;
- unsigned char MacAddress[6];
- u8 Reserved[2];
- struct ndis_802_11_ssid Ssid;
- u32 Privacy;
- s32 Rssi;
- enum NDIS_802_11_NETWORK_TYPE NetworkTypeInUse;
- struct NDIS_802_11_CONFIGURATION Configuration;
- enum NDIS_802_11_NETWORK_INFRASTRUCTURE InfrastructureMode;
- NDIS_802_11_RATES_EX SupportedRates;
- u32 IELength;
- u8 IEs[MAX_IE_SZ]; /* (timestamp, beacon interval, and capability
+ u32 Length;
+ unsigned char MacAddress[6];
+ u8 Reserved[2];
+ struct ndis_802_11_ssid Ssid;
+ u32 Privacy;
+ s32 Rssi;
+ enum NDIS_802_11_NETWORK_TYPE NetworkTypeInUse;
+ struct NDIS_802_11_CONFIGURATION Configuration;
+ enum NDIS_802_11_NETWORK_INFRASTRUCTURE InfrastructureMode;
+ NDIS_802_11_RATES_EX SupportedRates;
+ u32 IELength;
+ u8 IEs[MAX_IE_SZ]; /* (timestamp, beacon interval, and capability
* information) */
};
diff --git a/drivers/staging/rts_pstor/ms.c b/drivers/staging/rts_pstor/ms.c
index d89795c..2e82587 100644
--- a/drivers/staging/rts_pstor/ms.c
+++ b/drivers/staging/rts_pstor/ms.c
@@ -864,7 +864,7 @@
TRACE_RET(chip, STATUS_FAIL);
}
- buf = (u8 *)rtsx_alloc_dma_buf(chip, 64 * 512, GFP_KERNEL);
+ buf = kmalloc(64 * 512, GFP_KERNEL);
if (buf == NULL) {
TRACE_RET(chip, STATUS_ERROR);
}
@@ -876,11 +876,11 @@
}
retval = rtsx_read_register(chip, MS_TRANS_CFG, &val);
if (retval != STATUS_SUCCESS) {
- rtsx_free_dma_buf(chip, buf);
+ kfree(buf);
TRACE_RET(chip, STATUS_FAIL);
}
if (!(val & MS_INT_BREQ)) {
- rtsx_free_dma_buf(chip, buf);
+ kfree(buf);
TRACE_RET(chip, STATUS_FAIL);
}
retval = ms_transfer_data(chip, MS_TM_AUTO_READ, PRO_READ_LONG_DATA,
@@ -892,7 +892,7 @@
}
}
if (retval != STATUS_SUCCESS) {
- rtsx_free_dma_buf(chip, buf);
+ kfree(buf);
TRACE_RET(chip, STATUS_FAIL);
}
@@ -900,7 +900,7 @@
do {
retval = rtsx_read_register(chip, MS_TRANS_CFG, &val);
if (retval != STATUS_SUCCESS) {
- rtsx_free_dma_buf(chip, buf);
+ kfree(buf);
TRACE_RET(chip, STATUS_FAIL);
}
@@ -909,7 +909,7 @@
retval = ms_transfer_tpc(chip, MS_TM_NORMAL_READ, PRO_READ_LONG_DATA, 0, WAIT_INT);
if (retval != STATUS_SUCCESS) {
- rtsx_free_dma_buf(chip, buf);
+ kfree(buf);
TRACE_RET(chip, STATUS_FAIL);
}
@@ -917,18 +917,18 @@
} while (i < 1024);
if (retval != STATUS_SUCCESS) {
- rtsx_free_dma_buf(chip, buf);
+ kfree(buf);
TRACE_RET(chip, STATUS_FAIL);
}
if ((buf[0] != 0xa5) && (buf[1] != 0xc3)) {
/* Signature code is wrong */
- rtsx_free_dma_buf(chip, buf);
+ kfree(buf);
TRACE_RET(chip, STATUS_FAIL);
}
if ((buf[4] < 1) || (buf[4] > 12)) {
- rtsx_free_dma_buf(chip, buf);
+ kfree(buf);
TRACE_RET(chip, STATUS_FAIL);
}
@@ -950,15 +950,15 @@
RTSX_DEBUGP("sys_info_addr = 0x%x, sys_info_size = 0x%x\n",
sys_info_addr, sys_info_size);
if (sys_info_size != 96) {
- rtsx_free_dma_buf(chip, buf);
+ kfree(buf);
TRACE_RET(chip, STATUS_FAIL);
}
if (sys_info_addr < 0x1A0) {
- rtsx_free_dma_buf(chip, buf);
+ kfree(buf);
TRACE_RET(chip, STATUS_FAIL);
}
if ((sys_info_size + sys_info_addr) > 0x8000) {
- rtsx_free_dma_buf(chip, buf);
+ kfree(buf);
TRACE_RET(chip, STATUS_FAIL);
}
@@ -984,15 +984,15 @@
RTSX_DEBUGP("model_name_addr = 0x%x, model_name_size = 0x%x\n",
model_name_addr, model_name_size);
if (model_name_size != 48) {
- rtsx_free_dma_buf(chip, buf);
+ kfree(buf);
TRACE_RET(chip, STATUS_FAIL);
}
if (model_name_addr < 0x1A0) {
- rtsx_free_dma_buf(chip, buf);
+ kfree(buf);
TRACE_RET(chip, STATUS_FAIL);
}
if ((model_name_size + model_name_addr) > 0x8000) {
- rtsx_free_dma_buf(chip, buf);
+ kfree(buf);
TRACE_RET(chip, STATUS_FAIL);
}
@@ -1005,7 +1005,7 @@
}
if (i == buf[4]) {
- rtsx_free_dma_buf(chip, buf);
+ kfree(buf);
TRACE_RET(chip, STATUS_FAIL);
}
@@ -1042,7 +1042,7 @@
memcpy(ms_card->raw_model_name, buf + model_name_addr, 48);
#endif
- rtsx_free_dma_buf(chip, buf);
+ kfree(buf);
#ifdef SUPPORT_MSXC
if (CHK_MSXC(ms_card)) {
@@ -3784,7 +3784,7 @@
TRACE_RET(chip, STATUS_FAIL);
}
- buf = (u8 *)rtsx_alloc_dma_buf(chip, 1540, GFP_KERNEL);
+ buf = kmalloc(1540, GFP_KERNEL);
if (!buf) {
TRACE_RET(chip, STATUS_ERROR);
}
@@ -3817,9 +3817,7 @@
rtsx_stor_set_xfer_buf(buf, bufflen, srb);
GetEKBFinish:
- if (buf) {
- rtsx_free_dma_buf(chip, buf);
- }
+ kfree(buf);
return retval;
}
@@ -4022,7 +4020,7 @@
TRACE_RET(chip, STATUS_FAIL);
}
- buf = (u8 *)rtsx_alloc_dma_buf(chip, 1028, GFP_KERNEL);
+ buf = kmalloc(1028, GFP_KERNEL);
if (!buf) {
TRACE_RET(chip, STATUS_ERROR);
}
@@ -4055,9 +4053,7 @@
rtsx_stor_set_xfer_buf(buf, bufflen, srb);
GetICVFinish:
- if (buf) {
- rtsx_free_dma_buf(chip, buf);
- }
+ kfree(buf);
return retval;
}
@@ -4081,7 +4077,7 @@
TRACE_RET(chip, STATUS_FAIL);
}
- buf = (u8 *)rtsx_alloc_dma_buf(chip, 1028, GFP_KERNEL);
+ buf = kmalloc(1028, GFP_KERNEL);
if (!buf) {
TRACE_RET(chip, STATUS_ERROR);
}
@@ -4156,9 +4152,7 @@
#endif
SetICVFinish:
- if (buf) {
- rtsx_free_dma_buf(chip, buf);
- }
+ kfree(buf);
return retval;
}
diff --git a/drivers/staging/rts_pstor/rtsx.c b/drivers/staging/rts_pstor/rtsx.c
index 02525d5..5ff59f2 100644
--- a/drivers/staging/rts_pstor/rtsx.c
+++ b/drivers/staging/rts_pstor/rtsx.c
@@ -594,7 +594,9 @@
wait_timeout((delay_use + 5) * 1000);
for (;;) {
- wait_timeout(POLLING_INTERVAL);
+
+ set_current_state(TASK_INTERRUPTIBLE);
+ schedule_timeout(POLLING_INTERVAL);
/* lock the device pointers */
mutex_lock(&(dev->dev_mutex));
diff --git a/drivers/staging/rts_pstor/rtsx.h b/drivers/staging/rts_pstor/rtsx.h
index 4d5ddf6..6afb635 100644
--- a/drivers/staging/rts_pstor/rtsx.h
+++ b/drivers/staging/rts_pstor/rtsx.h
@@ -98,9 +98,6 @@
#define SCSI_LUN(srb) ((srb)->device->lun)
-#define rtsx_alloc_dma_buf(chip, size, flag) kmalloc((size), (flag))
-#define rtsx_free_dma_buf(chip, ptr) kfree((ptr))
-
typedef unsigned long DELAY_PARA_T;
struct rtsx_chip;
diff --git a/drivers/staging/rts_pstor/sd.c b/drivers/staging/rts_pstor/sd.c
index b1277a6..bddb031 100644
--- a/drivers/staging/rts_pstor/sd.c
+++ b/drivers/staging/rts_pstor/sd.c
@@ -2227,6 +2227,7 @@
retval = sd_read_data(chip, SD_TM_NORMAL_READ, cmd,
5, 512, 1, bus_width, NULL, 0, 100);
if (retval != STATUS_SUCCESS) {
+ rtsx_clear_sd_error(chip);
TRACE_RET(chip, STATUS_FAIL);
}
diff --git a/drivers/staging/rts_pstor/spi.c b/drivers/staging/rts_pstor/spi.c
index 8a8689b..c803ba6 100644
--- a/drivers/staging/rts_pstor/spi.c
+++ b/drivers/staging/rts_pstor/spi.c
@@ -505,7 +505,7 @@
TRACE_RET(chip, STATUS_FAIL);
}
- buf = (u8 *)rtsx_alloc_dma_buf(chip, SF_PAGE_LEN, GFP_KERNEL);
+ buf = kmalloc(SF_PAGE_LEN, GFP_KERNEL);
if (buf == NULL)
TRACE_RET(chip, STATUS_ERROR);
@@ -543,7 +543,7 @@
retval = rtsx_transfer_data(chip, 0, buf, pagelen, 0, DMA_FROM_DEVICE, 10000);
if (retval < 0) {
- rtsx_free_dma_buf(chip, buf);
+ kfree(buf);
rtsx_clear_spi_error(chip);
spi_set_err_code(chip, SPI_HW_ERR);
TRACE_RET(chip, STATUS_FAIL);
@@ -556,7 +556,7 @@
}
scsi_set_resid(srb, 0);
- rtsx_free_dma_buf(chip, buf);
+ kfree(buf);
return STATUS_SUCCESS;
}
@@ -584,14 +584,14 @@
}
if (program_mode == BYTE_PROGRAM) {
- buf = rtsx_alloc_dma_buf(chip, 4, GFP_KERNEL);
+ buf = kmalloc(4, GFP_KERNEL);
if (!buf)
TRACE_RET(chip, STATUS_ERROR);
while (len) {
retval = sf_enable_write(chip, SPI_WREN);
if (retval != STATUS_SUCCESS) {
- rtsx_free_dma_buf(chip, buf);
+ kfree(buf);
TRACE_RET(chip, STATUS_FAIL);
}
@@ -605,7 +605,7 @@
retval = rtsx_send_cmd(chip, 0, 100);
if (retval < 0) {
- rtsx_free_dma_buf(chip, buf);
+ kfree(buf);
rtsx_clear_spi_error(chip);
spi_set_err_code(chip, SPI_HW_ERR);
TRACE_RET(chip, STATUS_FAIL);
@@ -613,7 +613,7 @@
retval = sf_polling_status(chip, 100);
if (retval != STATUS_SUCCESS) {
- rtsx_free_dma_buf(chip, buf);
+ kfree(buf);
TRACE_RET(chip, STATUS_FAIL);
}
@@ -621,7 +621,7 @@
len--;
}
- rtsx_free_dma_buf(chip, buf);
+ kfree(buf);
} else if (program_mode == AAI_PROGRAM) {
int first_byte = 1;
@@ -630,7 +630,7 @@
if (retval != STATUS_SUCCESS)
TRACE_RET(chip, STATUS_FAIL);
- buf = rtsx_alloc_dma_buf(chip, 4, GFP_KERNEL);
+ buf = kmalloc(4, GFP_KERNEL);
if (!buf)
TRACE_RET(chip, STATUS_ERROR);
@@ -650,7 +650,7 @@
retval = rtsx_send_cmd(chip, 0, 100);
if (retval < 0) {
- rtsx_free_dma_buf(chip, buf);
+ kfree(buf);
rtsx_clear_spi_error(chip);
spi_set_err_code(chip, SPI_HW_ERR);
TRACE_RET(chip, STATUS_FAIL);
@@ -658,14 +658,14 @@
retval = sf_polling_status(chip, 100);
if (retval != STATUS_SUCCESS) {
- rtsx_free_dma_buf(chip, buf);
+ kfree(buf);
TRACE_RET(chip, STATUS_FAIL);
}
len--;
}
- rtsx_free_dma_buf(chip, buf);
+ kfree(buf);
retval = sf_disable_write(chip, SPI_WRDI);
if (retval != STATUS_SUCCESS)
@@ -675,7 +675,7 @@
if (retval != STATUS_SUCCESS)
TRACE_RET(chip, STATUS_FAIL);
} else if (program_mode == PAGE_PROGRAM) {
- buf = rtsx_alloc_dma_buf(chip, SF_PAGE_LEN, GFP_KERNEL);
+ buf = kmalloc(SF_PAGE_LEN, GFP_KERNEL);
if (!buf)
TRACE_RET(chip, STATUS_NOMEM);
@@ -687,7 +687,7 @@
retval = sf_enable_write(chip, SPI_WREN);
if (retval != STATUS_SUCCESS) {
- rtsx_free_dma_buf(chip, buf);
+ kfree(buf);
TRACE_RET(chip, STATUS_FAIL);
}
@@ -702,7 +702,7 @@
retval = rtsx_transfer_data(chip, 0, buf, pagelen, 0, DMA_TO_DEVICE, 100);
if (retval < 0) {
- rtsx_free_dma_buf(chip, buf);
+ kfree(buf);
rtsx_clear_spi_error(chip);
spi_set_err_code(chip, SPI_HW_ERR);
TRACE_RET(chip, STATUS_FAIL);
@@ -710,7 +710,7 @@
retval = sf_polling_status(chip, 100);
if (retval != STATUS_SUCCESS) {
- rtsx_free_dma_buf(chip, buf);
+ kfree(buf);
TRACE_RET(chip, STATUS_FAIL);
}
@@ -718,7 +718,7 @@
len -= pagelen;
}
- rtsx_free_dma_buf(chip, buf);
+ kfree(buf);
} else {
spi_set_err_code(chip, SPI_INVALID_COMMAND);
TRACE_RET(chip, STATUS_FAIL);
diff --git a/drivers/staging/rts_pstor/xd.c b/drivers/staging/rts_pstor/xd.c
index 9f3add1..9bba5b1 100644
--- a/drivers/staging/rts_pstor/xd.c
+++ b/drivers/staging/rts_pstor/xd.c
@@ -380,7 +380,7 @@
RTSX_DEBUGP("xD ECC error, dummy write!\n");
- buf = (u8 *)rtsx_alloc_dma_buf(chip, 512, GFP_KERNEL);
+ buf = kmalloc(512, GFP_KERNEL);
if (!buf)
return;
@@ -427,7 +427,7 @@
rtsx_write_register(chip, CARD_STOP, SD_STOP | SD_CLR_ERR, SD_STOP | SD_CLR_ERR);
}
- rtsx_free_dma_buf(chip, buf);
+ kfree(buf);
if (chip->asic_code) {
rtsx_write_register(chip, CARD_PULL_CTL2, 0xFF, 0x55);
diff --git a/drivers/staging/sbe-2t3e3/dc.c b/drivers/staging/sbe-2t3e3/dc.c
index 126a972..9dc4ec2 100644
--- a/drivers/staging/sbe-2t3e3/dc.c
+++ b/drivers/staging/sbe-2t3e3/dc.c
@@ -341,10 +341,6 @@
sc->ether.tx_ring = kzalloc(SBE_2T3E3_TX_DESC_RING_SIZE *
sizeof(t3e3_tx_desc_t), GFP_KERNEL);
if (sc->ether.tx_ring == NULL) {
-#ifdef T3E3_USE_CONTIGMALLOC
- t3e3_contigmemory_size = SBE_2T3E3_RX_DESC_RING_SIZE *
- sizeof(t3e3_rx_desc_t);
-#endif
kfree(sc->ether.rx_ring);
sc->ether.rx_ring = NULL;
dev_err(&sc->pdev->dev, "SBE 2T3E3: no buffer space for RX ring\n");
@@ -366,16 +362,8 @@
dev_kfree_skb_any(sc->ether.rx_data[j]);
sc->ether.rx_data[j] = NULL;
}
-#ifdef T3E3_USE_CONTIGMALLOC
- t3e3_contigmemory_size = SBE_2T3E3_RX_DESC_RING_SIZE *
- sizeof(t3e3_rx_desc_t);
-#endif
kfree(sc->ether.rx_ring);
sc->ether.rx_ring = NULL;
-#ifdef T3E3_USE_CONTIGMALLOC
- t3e3_contigmemory_size = SBE_2T3E3_TX_DESC_RING_SIZE *
- sizeof(t3e3_tx_desc_t);
-#endif
kfree(sc->ether.tx_ring);
sc->ether.tx_ring = NULL;
dev_err(&sc->pdev->dev, "SBE 2T3E3: token_alloc err:"
@@ -454,23 +442,10 @@
}
}
- if (sc->ether.rx_ring != NULL) {
-#ifdef T3E3_USE_CONTIGMALLOC
- t3e3_contigmemory_size = SBE_2T3E3_RX_DESC_RING_SIZE *
- sizeof(t3e3_rx_desc_t);
-#endif
- kfree(sc->ether.rx_ring);
- sc->ether.rx_ring = NULL;
- }
-
- if (sc->ether.tx_ring != NULL) {
-#ifdef T3E3_USE_CONTIGMALLOC
- t3e3_contigmemory_size = SBE_2T3E3_TX_DESC_RING_SIZE *
- sizeof(t3e3_tx_desc_t);
-#endif
- kfree(sc->ether.tx_ring);
- sc->ether.tx_ring = NULL;
- }
+ kfree(sc->ether.rx_ring);
+ sc->ether.rx_ring = NULL;
+ kfree(sc->ether.tx_ring);
+ sc->ether.tx_ring = NULL;
}
diff --git a/drivers/staging/sep/sep_driver.c b/drivers/staging/sep/sep_driver.c
index 890eede..52342c1 100644
--- a/drivers/staging/sep/sep_driver.c
+++ b/drivers/staging/sep/sep_driver.c
@@ -1095,13 +1095,16 @@
if (num_pages > 1) {
lli_array[num_pages - 1].block_size =
(app_virt_addr + data_size) & (~PAGE_MASK);
+ if (lli_array[num_pages - 1].block_size == 0)
+ lli_array[num_pages - 1].block_size = PAGE_SIZE;
dev_warn(&sep->pdev->dev,
- "lli_array[%x].bus_address is %08lx, lli_array[%x].block_size is %x\n",
+ "lli_array[%x].bus_address is "
+ "%08lx, lli_array[%x].block_size is %x\n",
num_pages - 1,
- (unsigned long)lli_array[count].bus_address,
+ (unsigned long)lli_array[num_pages -1].bus_address,
num_pages - 1,
- lli_array[count].block_size);
+ lli_array[num_pages -1].block_size);
}
/* Set output params according to the in_out flag */
diff --git a/drivers/staging/sm7xx/TODO b/drivers/staging/sm7xx/TODO
index a66d9e4..7304021 100644
--- a/drivers/staging/sm7xx/TODO
+++ b/drivers/staging/sm7xx/TODO
@@ -2,9 +2,7 @@
- Dual head support
- 2D acceleration support
- use kernel coding style
-- checkpatch.pl clean
- refine the code and remove unused code
-- use kernel framebuffer mode setting instead of hard code
- move it to drivers/video/sm7xx/ or make it be drivers/video/sm7xxfb.c
Please send any patches to Greg Kroah-Hartman <greg@kroah.com> and
diff --git a/drivers/staging/sm7xx/smtcfb.c b/drivers/staging/sm7xx/smtcfb.c
index 3e2230f..a164fc4 100644
--- a/drivers/staging/sm7xx/smtcfb.c
+++ b/drivers/staging/sm7xx/smtcfb.c
@@ -8,21 +8,24 @@
* Copyright (C) 2009 Lemote, Inc.
* Author: Wu Zhangjin, wuzhangjin@gmail.com
*
+ * Copyright (C) 2011 Igalia, S.L.
+ * Author: Javier M. Mellid <jmunhoz@igalia.com>
+ *
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive for
* more details.
*
* Version 0.10.26192.21.01
* - Add PowerPC/Big endian support
- * - Add 2D support for Lynx
- * - Verified on2.6.19.2 Boyod.yang <boyod.yang@siliconmotion.com.cn>
+ * - Verified on 2.6.19.2
+ * Boyod.yang <boyod.yang@siliconmotion.com.cn>
*
* Version 0.09.2621.00.01
- * - Only support Linux Kernel's version 2.6.21.
- * Boyod.yang <boyod.yang@siliconmotion.com.cn>
+ * - Only support Linux Kernel's version 2.6.21
+ * Boyod.yang <boyod.yang@siliconmotion.com.cn>
*
* Version 0.09
- * - Only support Linux Kernel's version 2.6.12.
+ * - Only support Linux Kernel's version 2.6.12
* Boyod.yang <boyod.yang@siliconmotion.com.cn>
*/
@@ -39,16 +42,16 @@
#include <linux/pm.h>
#endif
-struct screen_info smtc_screen_info;
-
#include "smtcfb.h"
#ifdef DEBUG
-#define smdbg(format, arg...) printk(KERN_DEBUG format , ## arg)
+#define smdbg(format, arg...) printk(KERN_DEBUG format , ## arg)
#else
#define smdbg(format, arg...)
#endif
+struct screen_info smtc_screen_info;
+
/*
* Private structure
*/
@@ -99,17 +102,17 @@
static struct vesa_mode_table vesa_mode[] = {
{"0x301", 640, 480, 8},
{"0x303", 800, 600, 8},
- {"0x305", 1024, 768, 8},
+ {"0x305", 1024, 768, 8},
{"0x307", 1280, 1024, 8},
{"0x311", 640, 480, 16},
{"0x314", 800, 600, 16},
- {"0x317", 1024, 768, 16},
+ {"0x317", 1024, 768, 16},
{"0x31A", 1280, 1024, 16},
{"0x312", 640, 480, 24},
{"0x315", 800, 600, 24},
- {"0x318", 1024, 768, 24},
+ {"0x318", 1024, 768, 24},
{"0x31B", 1280, 1024, 24},
};
@@ -125,7 +128,30 @@
0x720
};
-#define numSMTCchipIDs (sizeof(smtc_ChipIDs) / sizeof(u16))
+#define numSMTCchipIDs ARRAY_SIZE(smtc_ChipIDs)
+
+static struct fb_var_screeninfo smtcfb_var = {
+ .xres = 1024,
+ .yres = 600,
+ .xres_virtual = 1024,
+ .yres_virtual = 600,
+ .bits_per_pixel = 16,
+ .red = {16, 8, 0},
+ .green = {8, 8, 0},
+ .blue = {0, 8, 0},
+ .activate = FB_ACTIVATE_NOW,
+ .height = -1,
+ .width = -1,
+ .vmode = FB_VMODE_NONINTERLACED,
+};
+
+static struct fb_fix_screeninfo smtcfb_fix = {
+ .id = "sm712fb",
+ .type = FB_TYPE_PACKED_PIXELS,
+ .visual = FB_VISUAL_TRUECOLOR,
+ .line_length = 800 * 3,
+ .accel = FB_ACCEL_SMI_LYNX,
+};
static void sm712_set_timing(struct smtcfb_info *sfb,
struct par_info *ppar_info)
@@ -268,29 +294,6 @@
}
}
-static struct fb_var_screeninfo smtcfb_var = {
- .xres = 1024,
- .yres = 600,
- .xres_virtual = 1024,
- .yres_virtual = 600,
- .bits_per_pixel = 16,
- .red = {16, 8, 0},
- .green = {8, 8, 0},
- .blue = {0, 8, 0},
- .activate = FB_ACTIVATE_NOW,
- .height = -1,
- .width = -1,
- .vmode = FB_VMODE_NONINTERLACED,
-};
-
-static struct fb_fix_screeninfo smtcfb_fix = {
- .id = "sm712fb",
- .type = FB_TYPE_PACKED_PIXELS,
- .visual = FB_VISUAL_TRUECOLOR,
- .line_length = 800 * 3,
- .accel = FB_ACCEL_SMI_LYNX,
-};
-
/* chan_to_field
*
* convert a colour value into a field position
@@ -604,20 +607,6 @@
}
#endif /* ! __BIG_ENDIAN */
-static struct fb_ops smtcfb_ops = {
- .owner = THIS_MODULE,
- .fb_setcolreg = smtc_setcolreg,
- .fb_blank = cfb_blank,
- .fb_fillrect = cfb_fillrect,
- .fb_imageblit = cfb_imageblit,
- .fb_copyarea = cfb_copyarea,
-#ifdef __BIG_ENDIAN
- .fb_read = smtcfb_read,
- .fb_write = smtcfb_write,
-#endif
-
-};
-
void smtcfb_setmode(struct smtcfb_info *sfb)
{
switch (sfb->fb.var.bits_per_pixel) {
@@ -676,6 +665,47 @@
smtc_set_timing(sfb, &hw);
}
+static int smtc_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
+{
+ /* sanity checks */
+ if (var->xres_virtual < var->xres)
+ var->xres_virtual = var->xres;
+
+ if (var->yres_virtual < var->yres)
+ var->yres_virtual = var->yres;
+
+ /* set valid default bpp */
+ if ((var->bits_per_pixel != 8) && (var->bits_per_pixel != 16) &&
+ (var->bits_per_pixel != 24) && (var->bits_per_pixel != 32))
+ var->bits_per_pixel = 16;
+
+ return 0;
+}
+
+static int smtc_set_par(struct fb_info *info)
+{
+ struct smtcfb_info *sfb = (struct smtcfb_info *)info;
+
+ smtcfb_setmode(sfb);
+
+ return 0;
+}
+
+static struct fb_ops smtcfb_ops = {
+ .owner = THIS_MODULE,
+ .fb_check_var = smtc_check_var,
+ .fb_set_par = smtc_set_par,
+ .fb_setcolreg = smtc_setcolreg,
+ .fb_blank = cfb_blank,
+ .fb_fillrect = cfb_fillrect,
+ .fb_imageblit = cfb_imageblit,
+ .fb_copyarea = cfb_copyarea,
+#ifdef __BIG_ENDIAN
+ .fb_read = smtcfb_read,
+ .fb_write = smtcfb_write,
+#endif
+};
+
/*
* Alloc struct smtcfb_info and assign the default value
*/
@@ -684,7 +714,7 @@
{
struct smtcfb_info *sfb;
- sfb = kzalloc(sizeof(struct smtcfb_info), GFP_KERNEL);
+ sfb = kzalloc(sizeof(*sfb), GFP_KERNEL);
if (!sfb)
return NULL;
@@ -753,7 +783,7 @@
sfb->fb.screen_base = smtc_VRAMBaseAddress;
if (!sfb->fb.screen_base) {
- printk(KERN_INFO "%s: unable to map screen memory\n",
+ printk(KERN_ERR "%s: unable to map screen memory\n",
sfb->fb.fix.id);
return -ENOMEM;
}
@@ -796,7 +826,7 @@
* Returns zero.
*
*/
-static int __init __maybe_unused sm712vga_setup(char *options)
+static int __init sm712vga_setup(char *options)
{
int index;
@@ -812,7 +842,7 @@
smdbg("\nsm712vga_setup = %s\n", options);
for (index = 0;
- index < (sizeof(vesa_mode) / sizeof(struct vesa_mode_table));
+ index < ARRAY_SIZE(vesa_mode);
index++) {
if (strstr(options, vesa_mode[index].mode_index)) {
smtc_screen_info.lfb_width = vesa_mode[index].lfb_width;
@@ -846,7 +876,6 @@
err = pci_enable_device(pdev); /* enable SMTC chip */
if (err)
return err;
- err = -ENOMEM;
hw.chipID = ent->device;
sprintf(name, "sm%Xfb", hw.chipID);
@@ -909,7 +938,7 @@
}
#endif
if (!smtc_RegBaseAddress) {
- printk(KERN_INFO
+ printk(KERN_ERR
"%s: unable to map memory mapped IO\n",
sfb->fb.fix.id);
err = -ENOMEM;
@@ -944,7 +973,7 @@
smtc_seqw(0x6b, 0x02);
break;
default:
- printk(KERN_INFO
+ printk(KERN_ERR
"No valid Silicon Motion display chip was detected!\n");
goto failed_fb;
@@ -976,8 +1005,8 @@
return 0;
- failed:
- printk(KERN_INFO "Silicon Motion, Inc. primary display init fail\n");
+failed:
+ printk(KERN_ERR "Silicon Motion, Inc. primary display init fail\n");
smtc_unmap_smem(sfb);
smtc_unmap_mmio(sfb);
@@ -1016,13 +1045,10 @@
}
#ifdef CONFIG_PM
-/* Jason (08/14/2009)
- * suspend function, called when the suspend event is triggered
- */
-static int __maybe_unused smtcfb_suspend(struct pci_dev *pdev, pm_message_t msg)
+static int smtcfb_pci_suspend(struct device *device)
{
+ struct pci_dev *pdev = to_pci_dev(device);
struct smtcfb_info *sfb;
- int retv;
sfb = pci_get_drvdata(pdev);
@@ -1032,25 +1058,9 @@
smtc_seqw(0x20, (smtc_seqr(0x20) | 0xc0));
smtc_seqw(0x69, (smtc_seqr(0x69) & 0xf7));
- switch (msg.event) {
- case PM_EVENT_FREEZE:
- case PM_EVENT_PRETHAW:
- pdev->dev.power.power_state = msg;
- return 0;
- }
-
- /* when doing suspend, call fb apis and pci apis */
- if (msg.event == PM_EVENT_SUSPEND) {
- console_lock();
- fb_set_suspend(&sfb->fb, 1);
- console_unlock();
- retv = pci_save_state(pdev);
- pci_disable_device(pdev);
- retv = pci_choose_state(pdev, msg);
- retv = pci_set_power_state(pdev, retv);
- }
-
- pdev->dev.power.power_state = msg;
+ console_lock();
+ fb_set_suspend(&sfb->fb, 1);
+ console_unlock();
/* additionally turn off all function blocks including internal PLLs */
smtc_seqw(0x21, 0xff);
@@ -1058,22 +1068,13 @@
return 0;
}
-static int __maybe_unused smtcfb_resume(struct pci_dev *pdev)
+static int smtcfb_pci_resume(struct device *device)
{
+ struct pci_dev *pdev = to_pci_dev(device);
struct smtcfb_info *sfb;
- int retv;
sfb = pci_get_drvdata(pdev);
- /* when resuming, restore pci data and fb cursor */
- if (pdev->dev.power.power_state.event != PM_EVENT_FREEZE) {
- retv = pci_set_power_state(pdev, PCI_D0);
- pci_restore_state(pdev);
- if (pci_enable_device(pdev))
- return -1;
- pci_set_master(pdev);
- }
-
/* reinit hardware */
sm7xx_init_hw();
switch (hw.chipID) {
@@ -1108,22 +1109,30 @@
return 0;
}
-#endif
-/* Jason (08/13/2009)
- * pci_driver struct used to wrap the original driver
- * so that it can be registered into the kernel and
- * the proper method would be called when suspending and resuming
- */
+static const struct dev_pm_ops sm7xx_pm_ops = {
+ .suspend = smtcfb_pci_suspend,
+ .resume = smtcfb_pci_resume,
+ .freeze = smtcfb_pci_suspend,
+ .thaw = smtcfb_pci_resume,
+ .poweroff = smtcfb_pci_suspend,
+ .restore = smtcfb_pci_resume,
+};
+
+#define SM7XX_PM_OPS (&sm7xx_pm_ops)
+
+#else /* !CONFIG_PM */
+
+#define SM7XX_PM_OPS NULL
+
+#endif /* !CONFIG_PM */
+
static struct pci_driver smtcfb_driver = {
.name = "smtcfb",
.id_table = smtcfb_pci_table,
.probe = smtcfb_pci_probe,
.remove = __devexit_p(smtcfb_pci_remove),
-#ifdef CONFIG_PM
- .suspend = smtcfb_suspend,
- .resume = smtcfb_resume,
-#endif
+ .driver.pm = SM7XX_PM_OPS,
};
static int __init smtcfb_init(void)
diff --git a/drivers/staging/sm7xx/smtcfb.h b/drivers/staging/sm7xx/smtcfb.h
index 0c11383..c5e6989 100644
--- a/drivers/staging/sm7xx/smtcfb.h
+++ b/drivers/staging/sm7xx/smtcfb.h
@@ -30,11 +30,6 @@
#define SCREEN_Y_RES 600
#define SCREEN_BPP 16
-#ifndef FIELD_OFFSET
-#define FIELD_OFSFET(type, field) \
- ((unsigned long) (PUCHAR) & (((type *)0)->field))
-#endif
-
/*Assume SM712 graphics chip has 4MB VRAM */
#define SM712_VIDEOMEMORYSIZE 0x00400000
/*Assume SM722 graphics chip has 8MB VRAM */
@@ -790,4 +785,4 @@
},
};
-#define numVGAModes (sizeof(VGAMode) / sizeof(struct ModeInit))
+#define numVGAModes ARRAY_SIZE(VGAMode)
diff --git a/drivers/staging/tm6000/CARDLIST b/drivers/staging/tm6000/CARDLIST
new file mode 100644
index 0000000..b5edce4
--- /dev/null
+++ b/drivers/staging/tm6000/CARDLIST
@@ -0,0 +1,16 @@
+ 1 -> Generic tm5600 board (tm5600) [6000:0001]
+ 2 -> Generic tm6000 board (tm6000) [6000:0001]
+ 3 -> Generic tm6010 board (tm6010) [6000:0002]
+ 4 -> 10Moons UT821 (tm5600) [6000:0001]
+ 5 -> 10Moons UT330 (tm5600)
+ 6 -> ADSTech Dual TV (tm6000) [06e1:f332]
+ 7 -> FreeCom and similar (tm6000) [14aa:0620]
+ 8 -> ADSTech Mini Dual TV (tm6000) [06e1:b339]
+ 9 -> Hauppauge WinTV HVR-900H/USB2 Stick (tm6010) [2040:6600,2040:6601,2040:6610,2040:6611]
+ 10 -> Beholder Wander (tm6010) [6000:dec0]
+ 11 -> Beholder Voyager (tm6010) [6000:dec1]
+ 12 -> TerraTec Cinergy Hybrid XE/Cinergy Hybrid Stick (tm6010) [0ccd:0086,0ccd:00a5]
+ 13 -> TwinHan TU501 (tm6010) [13d3:3240,13d3:3241,13d3:3243,13d3:3264]
+ 14 -> Beholder Wander Lite (tm6010) [6000:dec2]
+ 15 -> Beholder Voyager Lite (tm6010) [6000:dec3]
+
diff --git a/drivers/staging/tm6000/tm6000-alsa.c b/drivers/staging/tm6000/tm6000-alsa.c
index acb0317..2b96047 100644
--- a/drivers/staging/tm6000/tm6000-alsa.c
+++ b/drivers/staging/tm6000/tm6000-alsa.c
@@ -84,7 +84,6 @@
tm6000_set_audio_bitrate(core, 48000);
- tm6000_set_reg(core, TM6010_REQ08_R01_A_INIT, 0x80);
return 0;
}
@@ -101,8 +100,6 @@
/* Disables audio */
tm6000_set_reg_mask(core, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, 0x00, 0x40);
- tm6000_set_reg(core, TM6010_REQ08_R01_A_INIT, 0);
-
return 0;
}
diff --git a/drivers/staging/tm6000/tm6000-cards.c b/drivers/staging/tm6000/tm6000-cards.c
index 146c7e8..a69c82e 100644
--- a/drivers/staging/tm6000/tm6000-cards.c
+++ b/drivers/staging/tm6000/tm6000-cards.c
@@ -54,6 +54,11 @@
#define TM6010_BOARD_BEHOLD_VOYAGER_LITE 15
#define TM5600_BOARD_TERRATEC_GRABSTER 16
+#define is_generic(model) ((model == TM6000_BOARD_UNKNOWN) || \
+ (model == TM5600_BOARD_GENERIC) || \
+ (model == TM6000_BOARD_GENERIC) || \
+ (model == TM6010_BOARD_GENERIC))
+
#define TM6000_MAXBOARDS 16
static unsigned int card[] = {[0 ... (TM6000_MAXBOARDS - 1)] = UNSET };
@@ -64,10 +69,11 @@
struct tm6000_board {
char *name;
+ char eename[16]; /* EEPROM name */
+ unsigned eename_size; /* size of EEPROM name */
+ unsigned eename_pos; /* Position where it appears at ROM */
struct tm6000_capabilities caps;
- enum tm6000_inaudio aradio;
- enum tm6000_inaudio avideo;
enum tm6000_devtype type; /* variant of the chipset */
int tuner_type; /* type of the tuner */
@@ -76,6 +82,9 @@
struct tm6000_gpio gpio;
+ struct tm6000_input vinput[3];
+ struct tm6000_input rinput;
+
char *ir_codes;
};
@@ -83,11 +92,26 @@
[TM6000_BOARD_UNKNOWN] = {
.name = "Unknown tm6000 video grabber",
.caps = {
- .has_tuner = 1,
+ .has_tuner = 1,
+ .has_eeprom = 1,
},
.gpio = {
.tuner_reset = TM6000_GPIO_1,
},
+ .vinput = { {
+ .type = TM6000_INPUT_TV,
+ .vmux = TM6000_VMUX_VIDEO_B,
+ .amux = TM6000_AMUX_ADC1,
+ }, {
+ .type = TM6000_INPUT_COMPOSITE1,
+ .vmux = TM6000_VMUX_VIDEO_A,
+ .amux = TM6000_AMUX_ADC2,
+ }, {
+ .type = TM6000_INPUT_SVIDEO,
+ .vmux = TM6000_VMUX_VIDEO_AB,
+ .amux = TM6000_AMUX_ADC2,
+ },
+ },
},
[TM5600_BOARD_GENERIC] = {
.name = "Generic tm5600 board",
@@ -96,10 +120,25 @@
.tuner_addr = 0xc2 >> 1,
.caps = {
.has_tuner = 1,
+ .has_eeprom = 1,
},
.gpio = {
.tuner_reset = TM6000_GPIO_1,
},
+ .vinput = { {
+ .type = TM6000_INPUT_TV,
+ .vmux = TM6000_VMUX_VIDEO_B,
+ .amux = TM6000_AMUX_ADC1,
+ }, {
+ .type = TM6000_INPUT_COMPOSITE1,
+ .vmux = TM6000_VMUX_VIDEO_A,
+ .amux = TM6000_AMUX_ADC2,
+ }, {
+ .type = TM6000_INPUT_SVIDEO,
+ .vmux = TM6000_VMUX_VIDEO_AB,
+ .amux = TM6000_AMUX_ADC2,
+ },
+ },
},
[TM6000_BOARD_GENERIC] = {
.name = "Generic tm6000 board",
@@ -107,11 +146,25 @@
.tuner_addr = 0xc2 >> 1,
.caps = {
.has_tuner = 1,
- .has_dvb = 1,
+ .has_eeprom = 1,
},
.gpio = {
.tuner_reset = TM6000_GPIO_1,
},
+ .vinput = { {
+ .type = TM6000_INPUT_TV,
+ .vmux = TM6000_VMUX_VIDEO_B,
+ .amux = TM6000_AMUX_ADC1,
+ }, {
+ .type = TM6000_INPUT_COMPOSITE1,
+ .vmux = TM6000_VMUX_VIDEO_A,
+ .amux = TM6000_AMUX_ADC2,
+ }, {
+ .type = TM6000_INPUT_SVIDEO,
+ .vmux = TM6000_VMUX_VIDEO_AB,
+ .amux = TM6000_AMUX_ADC2,
+ },
+ },
},
[TM6010_BOARD_GENERIC] = {
.name = "Generic tm6010 board",
@@ -135,10 +188,27 @@
.dvb_led = TM6010_GPIO_5,
.ir = TM6010_GPIO_0,
},
+ .vinput = { {
+ .type = TM6000_INPUT_TV,
+ .vmux = TM6000_VMUX_VIDEO_B,
+ .amux = TM6000_AMUX_SIF1,
+ }, {
+ .type = TM6000_INPUT_COMPOSITE1,
+ .vmux = TM6000_VMUX_VIDEO_A,
+ .amux = TM6000_AMUX_ADC2,
+ }, {
+ .type = TM6000_INPUT_SVIDEO,
+ .vmux = TM6000_VMUX_VIDEO_AB,
+ .amux = TM6000_AMUX_ADC2,
+ },
+ },
},
[TM5600_BOARD_10MOONS_UT821] = {
.name = "10Moons UT 821",
.tuner_type = TUNER_XC2028,
+ .eename = { '1', '0', 'M', 'O', 'O', 'N', 'S', '5', '6', '0', '0', 0xff, 0x45, 0x5b},
+ .eename_size = 14,
+ .eename_pos = 0x14,
.type = TM5600,
.tuner_addr = 0xc2 >> 1,
.caps = {
@@ -148,6 +218,20 @@
.gpio = {
.tuner_reset = TM6000_GPIO_1,
},
+ .vinput = { {
+ .type = TM6000_INPUT_TV,
+ .vmux = TM6000_VMUX_VIDEO_B,
+ .amux = TM6000_AMUX_ADC1,
+ }, {
+ .type = TM6000_INPUT_COMPOSITE1,
+ .vmux = TM6000_VMUX_VIDEO_A,
+ .amux = TM6000_AMUX_ADC2,
+ }, {
+ .type = TM6000_INPUT_SVIDEO,
+ .vmux = TM6000_VMUX_VIDEO_AB,
+ .amux = TM6000_AMUX_ADC2,
+ },
+ },
},
[TM5600_BOARD_10MOONS_UT330] = {
.name = "10Moons UT 330",
@@ -159,6 +243,20 @@
.has_zl10353 = 0,
.has_eeprom = 1,
},
+ .vinput = { {
+ .type = TM6000_INPUT_TV,
+ .vmux = TM6000_VMUX_VIDEO_B,
+ .amux = TM6000_AMUX_ADC1,
+ }, {
+ .type = TM6000_INPUT_COMPOSITE1,
+ .vmux = TM6000_VMUX_VIDEO_A,
+ .amux = TM6000_AMUX_ADC2,
+ }, {
+ .type = TM6000_INPUT_SVIDEO,
+ .vmux = TM6000_VMUX_VIDEO_AB,
+ .amux = TM6000_AMUX_ADC2,
+ },
+ },
},
[TM6000_BOARD_ADSTECH_DUAL_TV] = {
.name = "ADSTECH Dual TV USB",
@@ -171,6 +269,20 @@
.has_zl10353 = 1,
.has_eeprom = 1,
},
+ .vinput = { {
+ .type = TM6000_INPUT_TV,
+ .vmux = TM6000_VMUX_VIDEO_B,
+ .amux = TM6000_AMUX_ADC1,
+ }, {
+ .type = TM6000_INPUT_COMPOSITE1,
+ .vmux = TM6000_VMUX_VIDEO_A,
+ .amux = TM6000_AMUX_ADC2,
+ }, {
+ .type = TM6000_INPUT_SVIDEO,
+ .vmux = TM6000_VMUX_VIDEO_AB,
+ .amux = TM6000_AMUX_ADC2,
+ },
+ },
},
[TM6000_BOARD_FREECOM_AND_SIMILAR] = {
.name = "Freecom Hybrid Stick / Moka DVB-T Receiver Dual",
@@ -187,6 +299,20 @@
.gpio = {
.tuner_reset = TM6000_GPIO_4,
},
+ .vinput = { {
+ .type = TM6000_INPUT_TV,
+ .vmux = TM6000_VMUX_VIDEO_B,
+ .amux = TM6000_AMUX_ADC1,
+ }, {
+ .type = TM6000_INPUT_COMPOSITE1,
+ .vmux = TM6000_VMUX_VIDEO_A,
+ .amux = TM6000_AMUX_ADC2,
+ }, {
+ .type = TM6000_INPUT_SVIDEO,
+ .vmux = TM6000_VMUX_VIDEO_AB,
+ .amux = TM6000_AMUX_ADC2,
+ },
+ },
},
[TM6000_BOARD_ADSTECH_MINI_DUAL_TV] = {
.name = "ADSTECH Mini Dual TV USB",
@@ -202,9 +328,26 @@
.gpio = {
.tuner_reset = TM6000_GPIO_4,
},
+ .vinput = { {
+ .type = TM6000_INPUT_TV,
+ .vmux = TM6000_VMUX_VIDEO_B,
+ .amux = TM6000_AMUX_ADC1,
+ }, {
+ .type = TM6000_INPUT_COMPOSITE1,
+ .vmux = TM6000_VMUX_VIDEO_A,
+ .amux = TM6000_AMUX_ADC2,
+ }, {
+ .type = TM6000_INPUT_SVIDEO,
+ .vmux = TM6000_VMUX_VIDEO_AB,
+ .amux = TM6000_AMUX_ADC2,
+ },
+ },
},
[TM6010_BOARD_HAUPPAUGE_900H] = {
.name = "Hauppauge WinTV HVR-900H / WinTV USB2-Stick",
+ .eename = { 'H', 0, 'V', 0, 'R', 0, '9', 0, '0', 0, '0', 0, 'H', 0 },
+ .eename_size = 14,
+ .eename_pos = 0x42,
.tuner_type = TUNER_XC2028, /* has a XC3028 */
.tuner_addr = 0xc2 >> 1,
.demod_addr = 0x1e >> 1,
@@ -225,6 +368,20 @@
.dvb_led = TM6010_GPIO_5,
.ir = TM6010_GPIO_0,
},
+ .vinput = { {
+ .type = TM6000_INPUT_TV,
+ .vmux = TM6000_VMUX_VIDEO_B,
+ .amux = TM6000_AMUX_SIF1,
+ }, {
+ .type = TM6000_INPUT_COMPOSITE1,
+ .vmux = TM6000_VMUX_VIDEO_A,
+ .amux = TM6000_AMUX_ADC2,
+ }, {
+ .type = TM6000_INPUT_SVIDEO,
+ .vmux = TM6000_VMUX_VIDEO_AB,
+ .amux = TM6000_AMUX_ADC2,
+ },
+ },
},
[TM6010_BOARD_BEHOLD_WANDER] = {
.name = "Beholder Wander DVB-T/TV/FM USB2.0",
@@ -232,43 +389,73 @@
.tuner_addr = 0xc2 >> 1,
.demod_addr = 0x1e >> 1,
.type = TM6010,
- .avideo = TM6000_AIP_SIF1,
- .aradio = TM6000_AIP_LINE1,
.caps = {
.has_tuner = 1,
.has_dvb = 1,
.has_zl10353 = 1,
.has_eeprom = 1,
.has_remote = 1,
- .has_input_comp = 1,
- .has_input_svid = 1,
+ .has_radio = 1.
},
.gpio = {
.tuner_reset = TM6010_GPIO_0,
.demod_reset = TM6010_GPIO_1,
.power_led = TM6010_GPIO_6,
},
+ .vinput = { {
+ .type = TM6000_INPUT_TV,
+ .vmux = TM6000_VMUX_VIDEO_B,
+ .amux = TM6000_AMUX_SIF1,
+ }, {
+ .type = TM6000_INPUT_COMPOSITE1,
+ .vmux = TM6000_VMUX_VIDEO_A,
+ .amux = TM6000_AMUX_ADC2,
+ }, {
+ .type = TM6000_INPUT_SVIDEO,
+ .vmux = TM6000_VMUX_VIDEO_AB,
+ .amux = TM6000_AMUX_ADC2,
+ },
+ },
+ .rinput = {
+ .type = TM6000_INPUT_RADIO,
+ .amux = TM6000_AMUX_ADC1,
+ },
},
[TM6010_BOARD_BEHOLD_VOYAGER] = {
.name = "Beholder Voyager TV/FM USB2.0",
.tuner_type = TUNER_XC5000,
.tuner_addr = 0xc2 >> 1,
.type = TM6010,
- .avideo = TM6000_AIP_SIF1,
- .aradio = TM6000_AIP_LINE1,
.caps = {
.has_tuner = 1,
.has_dvb = 0,
.has_zl10353 = 0,
.has_eeprom = 1,
.has_remote = 1,
- .has_input_comp = 1,
- .has_input_svid = 1,
+ .has_radio = 1,
},
.gpio = {
.tuner_reset = TM6010_GPIO_0,
.power_led = TM6010_GPIO_6,
},
+ .vinput = { {
+ .type = TM6000_INPUT_TV,
+ .vmux = TM6000_VMUX_VIDEO_B,
+ .amux = TM6000_AMUX_SIF1,
+ }, {
+ .type = TM6000_INPUT_COMPOSITE1,
+ .vmux = TM6000_VMUX_VIDEO_A,
+ .amux = TM6000_AMUX_ADC2,
+ }, {
+ .type = TM6000_INPUT_SVIDEO,
+ .vmux = TM6000_VMUX_VIDEO_AB,
+ .amux = TM6000_AMUX_ADC2,
+ },
+ },
+ .rinput = {
+ .type = TM6000_INPUT_RADIO,
+ .amux = TM6000_AMUX_ADC1,
+ },
},
[TM6010_BOARD_TERRATEC_CINERGY_HYBRID_XE] = {
.name = "Terratec Cinergy Hybrid XE / Cinergy Hybrid-Stick",
@@ -293,11 +480,39 @@
.ir = TM6010_GPIO_0,
},
.ir_codes = RC_MAP_NEC_TERRATEC_CINERGY_XS,
+ .vinput = { {
+ .type = TM6000_INPUT_TV,
+ .vmux = TM6000_VMUX_VIDEO_B,
+ .amux = TM6000_AMUX_SIF1,
+ }, {
+ .type = TM6000_INPUT_COMPOSITE1,
+ .vmux = TM6000_VMUX_VIDEO_A,
+ .amux = TM6000_AMUX_ADC2,
+ }, {
+ .type = TM6000_INPUT_SVIDEO,
+ .vmux = TM6000_VMUX_VIDEO_AB,
+ .amux = TM6000_AMUX_ADC2,
+ },
+ },
},
[TM5600_BOARD_TERRATEC_GRABSTER] = {
.name = "Terratec Grabster AV 150/250 MX",
.type = TM5600,
.tuner_type = TUNER_ABSENT,
+ .vinput = { {
+ .type = TM6000_INPUT_TV,
+ .vmux = TM6000_VMUX_VIDEO_B,
+ .amux = TM6000_AMUX_ADC1,
+ }, {
+ .type = TM6000_INPUT_COMPOSITE1,
+ .vmux = TM6000_VMUX_VIDEO_A,
+ .amux = TM6000_AMUX_ADC2,
+ }, {
+ .type = TM6000_INPUT_SVIDEO,
+ .vmux = TM6000_VMUX_VIDEO_AB,
+ .amux = TM6000_AMUX_ADC2,
+ },
+ },
},
[TM6010_BOARD_TWINHAN_TU501] = {
.name = "Twinhan TU501(704D1)",
@@ -321,6 +536,20 @@
.dvb_led = TM6010_GPIO_5,
.ir = TM6010_GPIO_0,
},
+ .vinput = { {
+ .type = TM6000_INPUT_TV,
+ .vmux = TM6000_VMUX_VIDEO_B,
+ .amux = TM6000_AMUX_SIF1,
+ }, {
+ .type = TM6000_INPUT_COMPOSITE1,
+ .vmux = TM6000_VMUX_VIDEO_A,
+ .amux = TM6000_AMUX_ADC2,
+ }, {
+ .type = TM6000_INPUT_SVIDEO,
+ .vmux = TM6000_VMUX_VIDEO_AB,
+ .amux = TM6000_AMUX_ADC2,
+ },
+ },
},
[TM6010_BOARD_BEHOLD_WANDER_LITE] = {
.name = "Beholder Wander Lite DVB-T/TV/FM USB2.0",
@@ -328,49 +557,63 @@
.tuner_addr = 0xc2 >> 1,
.demod_addr = 0x1e >> 1,
.type = TM6010,
- .avideo = TM6000_AIP_SIF1,
- .aradio = TM6000_AIP_LINE1,
.caps = {
.has_tuner = 1,
.has_dvb = 1,
.has_zl10353 = 1,
.has_eeprom = 1,
.has_remote = 0,
- .has_input_comp = 0,
- .has_input_svid = 0,
+ .has_radio = 1,
},
.gpio = {
.tuner_reset = TM6010_GPIO_0,
.demod_reset = TM6010_GPIO_1,
.power_led = TM6010_GPIO_6,
},
+ .vinput = { {
+ .type = TM6000_INPUT_TV,
+ .vmux = TM6000_VMUX_VIDEO_B,
+ .amux = TM6000_AMUX_SIF1,
+ },
+ },
+ .rinput = {
+ .type = TM6000_INPUT_RADIO,
+ .amux = TM6000_AMUX_ADC1,
+ },
},
[TM6010_BOARD_BEHOLD_VOYAGER_LITE] = {
.name = "Beholder Voyager Lite TV/FM USB2.0",
.tuner_type = TUNER_XC5000,
.tuner_addr = 0xc2 >> 1,
.type = TM6010,
- .avideo = TM6000_AIP_SIF1,
- .aradio = TM6000_AIP_LINE1,
.caps = {
.has_tuner = 1,
.has_dvb = 0,
.has_zl10353 = 0,
.has_eeprom = 1,
.has_remote = 0,
- .has_input_comp = 0,
- .has_input_svid = 0,
+ .has_radio = 1,
},
.gpio = {
.tuner_reset = TM6010_GPIO_0,
.power_led = TM6010_GPIO_6,
},
+ .vinput = { {
+ .type = TM6000_INPUT_TV,
+ .vmux = TM6000_VMUX_VIDEO_B,
+ .amux = TM6000_AMUX_SIF1,
+ },
+ },
+ .rinput = {
+ .type = TM6000_INPUT_RADIO,
+ .amux = TM6000_AMUX_ADC1,
+ },
},
};
/* table of devices that work with this driver */
struct usb_device_id tm6000_id_table[] = {
- { USB_DEVICE(0x6000, 0x0001), .driver_info = TM5600_BOARD_10MOONS_UT821 },
+ { USB_DEVICE(0x6000, 0x0001), .driver_info = TM5600_BOARD_GENERIC },
{ USB_DEVICE(0x6000, 0x0002), .driver_info = TM6010_BOARD_GENERIC },
{ USB_DEVICE(0x06e1, 0xf332), .driver_info = TM6000_BOARD_ADSTECH_DUAL_TV },
{ USB_DEVICE(0x14aa, 0x0620), .driver_info = TM6000_BOARD_FREECOM_AND_SIMILAR },
@@ -679,12 +922,8 @@
memset(&xc2028_cfg, 0, sizeof(xc2028_cfg));
memset(&ctl, 0, sizeof(ctl));
- ctl.input1 = 1;
- ctl.read_not_reliable = 0;
- ctl.msleep = 10;
ctl.demod = XC3028_FE_ZARLINK456;
- ctl.vhfbw7 = 1;
- ctl.uhfbw8 = 1;
+
xc2028_cfg.tuner = TUNER_XC2028;
xc2028_cfg.priv = &ctl;
@@ -729,16 +968,10 @@
}
}
-static int tm6000_init_dev(struct tm6000_core *dev)
+static int fill_board_specific_data(struct tm6000_core *dev)
{
- struct v4l2_frequency f;
- int rc = 0;
+ int rc;
- mutex_init(&dev->lock);
-
- mutex_lock(&dev->lock);
-
- /* Initializa board-specific data */
dev->dev_type = tm6000_boards[dev->model].type;
dev->tuner_type = tm6000_boards[dev->model].tuner_type;
dev->tuner_addr = tm6000_boards[dev->model].tuner_addr;
@@ -751,21 +984,85 @@
dev->caps = tm6000_boards[dev->model].caps;
- dev->avideo = tm6000_boards[dev->model].avideo;
- dev->aradio = tm6000_boards[dev->model].aradio;
+ dev->vinput[0] = tm6000_boards[dev->model].vinput[0];
+ dev->vinput[1] = tm6000_boards[dev->model].vinput[1];
+ dev->vinput[2] = tm6000_boards[dev->model].vinput[2];
+ dev->rinput = tm6000_boards[dev->model].rinput;
+
/* initialize hardware */
rc = tm6000_init(dev);
if (rc < 0)
- goto err;
+ return rc;
rc = v4l2_device_register(&dev->udev->dev, &dev->v4l2_dev);
if (rc < 0)
- goto err;
+ return rc;
- /* register i2c bus */
- rc = tm6000_i2c_register(dev);
- if (rc < 0)
- goto err;
+ return rc;
+}
+
+
+static void use_alternative_detection_method(struct tm6000_core *dev)
+{
+ int i, model = -1;
+
+ if (!dev->eedata_size)
+ return;
+
+ for (i = 0; i < ARRAY_SIZE(tm6000_boards); i++) {
+ if (!tm6000_boards[i].eename_size)
+ continue;
+ if (dev->eedata_size < tm6000_boards[i].eename_pos +
+ tm6000_boards[i].eename_size)
+ continue;
+
+ if (!memcmp(&dev->eedata[tm6000_boards[i].eename_pos],
+ tm6000_boards[i].eename,
+ tm6000_boards[i].eename_size)) {
+ model = i;
+ break;
+ }
+ }
+ if (model < 0) {
+ printk(KERN_INFO "Device has eeprom but is currently unknown\n");
+ return;
+ }
+
+ dev->model = model;
+
+ printk(KERN_INFO "Device identified via eeprom as %s (type = %d)\n",
+ tm6000_boards[model].name, model);
+}
+
+static int tm6000_init_dev(struct tm6000_core *dev)
+{
+ struct v4l2_frequency f;
+ int rc = 0;
+
+ mutex_init(&dev->lock);
+ mutex_lock(&dev->lock);
+
+ if (!is_generic(dev->model)) {
+ rc = fill_board_specific_data(dev);
+ if (rc < 0)
+ goto err;
+
+ /* register i2c bus */
+ rc = tm6000_i2c_register(dev);
+ if (rc < 0)
+ goto err;
+ } else {
+ /* register i2c bus */
+ rc = tm6000_i2c_register(dev);
+ if (rc < 0)
+ goto err;
+
+ use_alternative_detection_method(dev);
+
+ rc = fill_board_specific_data(dev);
+ if (rc < 0)
+ goto err;
+ }
/* Default values for STD and resolutions */
dev->width = 720;
diff --git a/drivers/staging/tm6000/tm6000-core.c b/drivers/staging/tm6000/tm6000-core.c
index 778e534..d7eb2e2 100644
--- a/drivers/staging/tm6000/tm6000-core.c
+++ b/drivers/staging/tm6000/tm6000-core.c
@@ -268,19 +268,18 @@
struct v4l2_frequency f;
if (dev->dev_type == TM6010) {
- /* Enable video */
-
+ /* Enable video and audio */
tm6000_set_reg_mask(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF,
0x60, 0x60);
+ /* Disable TS input */
tm6000_set_reg_mask(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE,
0x00, 0x40);
- tm6000_set_reg(dev, TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc);
-
} else {
/* Enables soft reset */
tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x01);
if (dev->scaler)
+ /* Disable Hfilter and Enable TS Drop err */
tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x20);
else /* Enable Hfilter and disable TS Drop err */
tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0x80);
@@ -300,14 +299,6 @@
/* Disables soft reset */
tm6000_set_reg(dev, TM6010_REQ07_R3F_RESET, 0x00);
-
- /* E3: Select input 0 - TV tuner */
- tm6000_set_reg(dev, TM6000_REQ07_RE3_VADC_INP_LPF_SEL1, 0x00);
- tm6000_set_reg(dev, TM6000_REQ07_REB_VADC_AADC_MODE, 0x60);
-
- /* This controls input */
- tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, TM6000_GPIO_2, 0x0);
- tm6000_set_reg(dev, REQ_03_SET_GET_MCU_PIN, TM6000_GPIO_3, 0x01);
}
msleep(20);
@@ -327,7 +318,7 @@
v4l2_device_call_all(&dev->v4l2_dev, 0, tuner, s_frequency, &f);
msleep(100);
- tm6000_set_standard(dev, &dev->norm);
+ tm6000_set_standard(dev);
tm6000_set_vbi(dev);
tm6000_set_audio_bitrate(dev, 48000);
@@ -343,21 +334,16 @@
int tm6000_init_digital_mode(struct tm6000_core *dev)
{
if (dev->dev_type == TM6010) {
- int val;
- u8 buf[2];
-
- /* digital init */
- val = tm6000_get_reg(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, 0);
- val &= ~0x60;
- tm6000_set_reg(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF, val);
- val = tm6000_get_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, 0);
- val |= 0x40;
- tm6000_set_reg(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE, val);
+ /* Disable video and audio */
+ tm6000_set_reg_mask(dev, TM6010_REQ07_RCC_ACTIVE_VIDEO_IF,
+ 0x00, 0x60);
+ /* Enable TS input */
+ tm6000_set_reg_mask(dev, TM6010_REQ07_RC0_ACTIVE_VIDEO_SOURCE,
+ 0x40, 0x40);
+ /* all power down, but not the digital data port */
tm6000_set_reg(dev, TM6010_REQ07_RFE_POWER_DOWN, 0x28);
tm6000_set_reg(dev, TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xfc);
tm6000_set_reg(dev, TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0xff);
- tm6000_read_write_usb(dev, 0xc0, 0x0e, 0x00c2, 0x0008, buf, 2);
- printk(KERN_INFO"buf %#x %#x\n", buf[0], buf[1]);
} else {
tm6000_set_reg(dev, TM6010_REQ07_RFF_SOFT_RESET, 0x08);
tm6000_set_reg(dev, TM6010_REQ07_RFF_SOFT_RESET, 0x00);
@@ -489,14 +475,6 @@
{ TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xf0 },
{ TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2 },
{ TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x60 },
- { TM6010_REQ08_R03_A_AUTO_GAIN_CTRL, 0x00},
- { TM6010_REQ08_R04_A_SIF_AMP_CTRL, 0x80},
- { TM6010_REQ08_R0C_A_ASD_THRES2, 0x0a},
- { TM6010_REQ08_R0D_A_AMD_THRES, 0x40},
- { TM6010_REQ08_R1A_A_NICAM_SER_MAX, 0x64},
- { TM6010_REQ08_R1B_A_NICAM_SER_MIN, 0x20},
- { TM6010_REQ08_R16_A_AGC_GAIN_MAX, 0xfe},
- { TM6010_REQ08_R17_A_AGC_GAIN_MIN, 0x01},
{ TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc },
{ TM6010_REQ07_R3F_RESET, 0x01 },
@@ -657,24 +635,29 @@
}
EXPORT_SYMBOL_GPL(tm6000_set_audio_bitrate);
-int tm6000_set_audio_input(struct tm6000_core *dev, enum tm6000_inaudio ainp)
+int tm6000_set_audio_rinput(struct tm6000_core *dev)
{
if (dev->dev_type == TM6010) {
/* Audio crossbar setting, default SIF1 */
- u8 areg_f0 = 0x03;
+ u8 areg_f0;
- switch (ainp) {
- case TM6000_AIP_SIF1:
- case TM6000_AIP_SIF2:
+ switch (dev->rinput.amux) {
+ case TM6000_AMUX_SIF1:
+ case TM6000_AMUX_SIF2:
areg_f0 = 0x03;
break;
- case TM6000_AIP_LINE1:
+ case TM6000_AMUX_ADC1:
areg_f0 = 0x00;
break;
- case TM6000_AIP_LINE2:
+ case TM6000_AMUX_ADC2:
areg_f0 = 0x08;
break;
+ case TM6000_AMUX_I2S:
+ areg_f0 = 0x04;
+ break;
default:
+ printk(KERN_INFO "%s: audio input dosn't support\n",
+ dev->name);
return 0;
break;
}
@@ -682,17 +665,18 @@
tm6000_set_reg_mask(dev, TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG,
areg_f0, 0x0f);
} else {
+ u8 areg_eb;
/* Audio setting, default LINE1 */
- u8 areg_eb = 0x00;
-
- switch (ainp) {
- case TM6000_AIP_LINE1:
+ switch (dev->rinput.amux) {
+ case TM6000_AMUX_ADC1:
areg_eb = 0x00;
break;
- case TM6000_AIP_LINE2:
+ case TM6000_AMUX_ADC2:
areg_eb = 0x04;
break;
default:
+ printk(KERN_INFO "%s: audio input dosn't support\n",
+ dev->name);
return 0;
break;
}
@@ -702,7 +686,6 @@
}
return 0;
}
-EXPORT_SYMBOL_GPL(tm6000_set_audio_input);
void tm6010_set_mute_sif(struct tm6000_core *dev, u8 mute)
{
@@ -736,16 +719,16 @@
int tm6000_tvaudio_set_mute(struct tm6000_core *dev, u8 mute)
{
- enum tm6000_inaudio ainp;
+ enum tm6000_mux mux;
if (dev->radio)
- ainp = dev->aradio;
+ mux = dev->rinput.amux;
else
- ainp = dev->avideo;
+ mux = dev->vinput[dev->input].amux;
- switch (ainp) {
- case TM6000_AIP_SIF1:
- case TM6000_AIP_SIF2:
+ switch (mux) {
+ case TM6000_AMUX_SIF1:
+ case TM6000_AMUX_SIF2:
if (dev->dev_type == TM6010)
tm6010_set_mute_sif(dev, mute);
else {
@@ -755,8 +738,8 @@
return -EINVAL;
}
break;
- case TM6000_AIP_LINE1:
- case TM6000_AIP_LINE2:
+ case TM6000_AMUX_ADC1:
+ case TM6000_AMUX_ADC2:
tm6010_set_mute_adc(dev, mute);
break;
default:
@@ -765,7 +748,6 @@
}
return 0;
}
-EXPORT_SYMBOL_GPL(tm6000_tvaudio_set_mute);
void tm6010_set_volume_sif(struct tm6000_core *dev, int vol)
{
@@ -797,17 +779,17 @@
void tm6000_set_volume(struct tm6000_core *dev, int vol)
{
- enum tm6000_inaudio ainp;
+ enum tm6000_mux mux;
if (dev->radio) {
- ainp = dev->aradio;
+ mux = dev->rinput.amux;
vol += 8; /* Offset to 0 dB */
} else
- ainp = dev->avideo;
+ mux = dev->vinput[dev->input].amux;
- switch (ainp) {
- case TM6000_AIP_SIF1:
- case TM6000_AIP_SIF2:
+ switch (mux) {
+ case TM6000_AMUX_SIF1:
+ case TM6000_AMUX_SIF2:
if (dev->dev_type == TM6010)
tm6010_set_volume_sif(dev, vol);
else
@@ -815,15 +797,14 @@
" SIF audio inputs. Please check the %s"
" configuration.\n", dev->name);
break;
- case TM6000_AIP_LINE1:
- case TM6000_AIP_LINE2:
+ case TM6000_AMUX_ADC1:
+ case TM6000_AMUX_ADC2:
tm6010_set_volume_adc(dev, vol);
break;
default:
break;
}
}
-EXPORT_SYMBOL_GPL(tm6000_set_volume);
static LIST_HEAD(tm6000_devlist);
static DEFINE_MUTEX(tm6000_devlist_mutex);
diff --git a/drivers/staging/tm6000/tm6000-i2c.c b/drivers/staging/tm6000/tm6000-i2c.c
index 18de474..8828c12 100644
--- a/drivers/staging/tm6000/tm6000-i2c.c
+++ b/drivers/staging/tm6000/tm6000-i2c.c
@@ -237,35 +237,36 @@
return rc;
}
-static int tm6000_i2c_eeprom(struct tm6000_core *dev,
- unsigned char *eedata, int len)
+static int tm6000_i2c_eeprom(struct tm6000_core *dev)
{
int i, rc;
- unsigned char *p = eedata;
+ unsigned char *p = dev->eedata;
unsigned char bytes[17];
dev->i2c_client.addr = 0xa0 >> 1;
+ dev->eedata_size = 0;
bytes[16] = '\0';
- for (i = 0; i < len; ) {
- *p = i;
- rc = tm6000_i2c_recv_regs(dev, 0xa0, i, p, 1);
+ for (i = 0; i < sizeof(dev->eedata); ) {
+ *p = i;
+ rc = tm6000_i2c_recv_regs(dev, 0xa0, i, p, 1);
if (rc < 1) {
- if (p == eedata)
+ if (p == dev->eedata)
goto noeeprom;
else {
printk(KERN_WARNING
"%s: i2c eeprom read error (err=%d)\n",
dev->name, rc);
}
- return -1;
+ return -EINVAL;
}
+ dev->eedata_size++;
p++;
if (0 == (i % 16))
printk(KERN_INFO "%s: i2c eeprom %02x:", dev->name, i);
- printk(" %02x", eedata[i]);
- if ((eedata[i] >= ' ') && (eedata[i] <= 'z'))
- bytes[i%16] = eedata[i];
+ printk(" %02x", dev->eedata[i]);
+ if ((dev->eedata[i] >= ' ') && (dev->eedata[i] <= 'z'))
+ bytes[i%16] = dev->eedata[i];
else
bytes[i%16] = '.';
@@ -280,15 +281,15 @@
bytes[i%16] = '\0';
for (i %= 16; i < 16; i++)
printk(" ");
+ printk(" %s\n", bytes);
}
- printk(" %s\n", bytes);
return 0;
noeeprom:
printk(KERN_INFO "%s: Huh, no eeprom present (err=%d)?\n",
- dev->name, rc);
- return rc;
+ dev->name, rc);
+ return -EINVAL;
}
/* ----------------------------------------------------------- */
@@ -314,7 +315,6 @@
*/
int tm6000_i2c_register(struct tm6000_core *dev)
{
- unsigned char eedata[256];
int rc;
dev->i2c_adap.owner = THIS_MODULE;
@@ -329,8 +329,7 @@
dev->i2c_client.adapter = &dev->i2c_adap;
strlcpy(dev->i2c_client.name, "tm6000 internal", I2C_NAME_SIZE);
-
- tm6000_i2c_eeprom(dev, eedata, sizeof(eedata));
+ tm6000_i2c_eeprom(dev);
return 0;
}
diff --git a/drivers/staging/tm6000/tm6000-stds.c b/drivers/staging/tm6000/tm6000-stds.c
index da3e51b..8b29d73 100644
--- a/drivers/staging/tm6000/tm6000-stds.c
+++ b/drivers/staging/tm6000/tm6000-stds.c
@@ -22,422 +22,26 @@
#include "tm6000.h"
#include "tm6000-regs.h"
+static unsigned int tm6010_a_mode = 0;
+module_param(tm6010_a_mode, int, 0644);
+MODULE_PARM_DESC(tm6010_a_mode, "set tm6010 sif audio mode");
+
struct tm6000_reg_settings {
unsigned char req;
unsigned char reg;
unsigned char value;
};
-enum tm6000_audio_std {
- BG_NICAM,
- BTSC,
- BG_A2,
- DK_NICAM,
- EIAJ,
- FM_RADIO,
- I_NICAM,
- KOREA_A2,
- L_NICAM,
-};
-
-struct tm6000_std_tv_settings {
- v4l2_std_id id;
- enum tm6000_audio_std audio_default_std;
-
- struct tm6000_reg_settings sif[12];
- struct tm6000_reg_settings nosif[12];
- struct tm6000_reg_settings common[26];
-};
struct tm6000_std_settings {
v4l2_std_id id;
- enum tm6000_audio_std audio_default_std;
- struct tm6000_reg_settings common[37];
-};
-
-static struct tm6000_std_tv_settings tv_stds[] = {
- {
- .id = V4L2_STD_PAL_M,
- .audio_default_std = BTSC,
- .sif = {
- {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf2},
- {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf8},
- {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf3},
- {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x08},
- {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf1},
- {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xe0},
- {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2},
- {TM6010_REQ08_RED_GAIN_SEL, 0xe8},
- {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x62},
- {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfe},
- {TM6010_REQ07_RFE_POWER_DOWN, 0xcb},
- {0, 0, 0},
- },
- .nosif = {
- {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0},
- {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf8},
- {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf3},
- {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x0f},
- {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf1},
- {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xe0},
- {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2},
- {TM6010_REQ08_RED_GAIN_SEL, 0xe8},
- {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x60},
- {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc},
- {TM6010_REQ07_RFE_POWER_DOWN, 0x8b},
- {0, 0, 0},
- },
- .common = {
- {TM6010_REQ07_R3F_RESET, 0x01},
- {TM6010_REQ07_R00_VIDEO_CONTROL0, 0x04},
- {TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e},
- {TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f},
- {TM6010_REQ07_R03_YC_SEP_CONTROL, 0x00},
- {TM6010_REQ07_R07_OUTPUT_CONTROL, 0x31},
- {TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e},
- {TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x83},
- {TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0x0a},
- {TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xe0},
- {TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c},
- {TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc},
- {TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc},
- {TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd},
- {TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88},
- {TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x20},
- {TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0x61},
- {TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x0c},
- {TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c},
- {TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x52},
- {TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6F},
-
- {TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdc},
- {TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07},
-
- {TM6010_REQ07_R3F_RESET, 0x00},
-
- {0, 0, 0},
- },
- }, {
- .id = V4L2_STD_PAL_Nc,
- .audio_default_std = BTSC,
- .sif = {
- {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf2},
- {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf8},
- {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf3},
- {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x08},
- {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf1},
- {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xe0},
- {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2},
- {TM6010_REQ08_RED_GAIN_SEL, 0xe8},
- {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x62},
- {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfe},
- {TM6010_REQ07_RFE_POWER_DOWN, 0xcb},
- {0, 0, 0},
- },
- .nosif = {
- {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0},
- {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf8},
- {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf3},
- {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x0f},
- {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf1},
- {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xe0},
- {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2},
- {TM6010_REQ08_RED_GAIN_SEL, 0xe8},
- {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x60},
- {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc},
- {TM6010_REQ07_RFE_POWER_DOWN, 0x8b},
- {0, 0, 0},
- },
- .common = {
- {TM6010_REQ07_R3F_RESET, 0x01},
- {TM6010_REQ07_R00_VIDEO_CONTROL0, 0x36},
- {TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e},
- {TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f},
- {TM6010_REQ07_R03_YC_SEP_CONTROL, 0x02},
- {TM6010_REQ07_R07_OUTPUT_CONTROL, 0x31},
- {TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e},
- {TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x91},
- {TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0x1f},
- {TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0x0c},
- {TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c},
- {TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc},
- {TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc},
- {TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd},
- {TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x8c},
- {TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x2c},
- {TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0xc1},
- {TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x0c},
- {TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c},
- {TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x52},
- {TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6F},
-
- {TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdc},
- {TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07},
-
- {TM6010_REQ07_R3F_RESET, 0x00},
-
- {0, 0, 0},
- },
- }, {
- .id = V4L2_STD_PAL,
- .audio_default_std = BG_A2,
- .sif = {
- {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf2},
- {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf8},
- {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf3},
- {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x08},
- {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf1},
- {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xe0},
- {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2},
- {TM6010_REQ08_RED_GAIN_SEL, 0xe8},
- {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x62},
- {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfe},
- {TM6010_REQ07_RFE_POWER_DOWN, 0xcb},
- {0, 0, 0}
- },
- .nosif = {
- {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0},
- {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf8},
- {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf3},
- {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x0f},
- {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf1},
- {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xe0},
- {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2},
- {TM6010_REQ08_RED_GAIN_SEL, 0xe8},
- {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x60},
- {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc},
- {TM6010_REQ07_RFE_POWER_DOWN, 0x8b},
- {0, 0, 0},
- },
- .common = {
- {TM6010_REQ07_R3F_RESET, 0x01},
- {TM6010_REQ07_R00_VIDEO_CONTROL0, 0x32},
- {TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e},
- {TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f},
- {TM6010_REQ07_R03_YC_SEP_CONTROL, 0x02},
- {TM6010_REQ07_R07_OUTPUT_CONTROL, 0x31},
- {TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x25},
- {TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0xd5},
- {TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0x63},
- {TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0x50},
- {TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c},
- {TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc},
- {TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc},
- {TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd},
- {TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x8c},
- {TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x2c},
- {TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0xc1},
- {TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x0c},
- {TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c},
- {TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x52},
- {TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6F},
-
- {TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdc},
- {TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07},
-
- {TM6010_REQ07_R3F_RESET, 0x00},
-
- {0, 0, 0},
- },
- }, {
- .id = V4L2_STD_SECAM_B | V4L2_STD_SECAM_G,
- .audio_default_std = BG_NICAM,
- .sif = {
- {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf2},
- {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf8},
- {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf3},
- {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x08},
- {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf1},
- {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xe0},
- {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2},
- {TM6010_REQ08_RED_GAIN_SEL, 0xe8},
- {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x62},
- {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfe},
- {TM6010_REQ07_RFE_POWER_DOWN, 0xcb},
- {0, 0, 0},
- },
- .nosif = {
- {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0},
- {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf8},
- {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf3},
- {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x0f},
- {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf1},
- {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xe0},
- {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2},
- {TM6010_REQ08_RED_GAIN_SEL, 0xe8},
- {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x60},
- {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc},
- {TM6010_REQ07_RFE_POWER_DOWN, 0x8b},
- {0, 0, 0},
- },
- .common = {
- {TM6010_REQ07_R3F_RESET, 0x01},
- {TM6010_REQ07_R00_VIDEO_CONTROL0, 0x38},
- {TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e},
- {TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f},
- {TM6010_REQ07_R03_YC_SEP_CONTROL, 0x02},
- {TM6010_REQ07_R07_OUTPUT_CONTROL, 0x31},
- {TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x24},
- {TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x92},
- {TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xe8},
- {TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xed},
- {TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c},
- {TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc},
- {TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc},
- {TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd},
- {TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x8c},
- {TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x2c},
- {TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0xc1},
- {TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x2c},
- {TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x18},
- {TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42},
- {TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0xFF},
-
- {TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07},
-
- {TM6010_REQ07_R3F_RESET, 0x00},
- {0, 0, 0},
- },
- }, {
- .id = V4L2_STD_SECAM_DK,
- .audio_default_std = DK_NICAM,
- .sif = {
- {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf2},
- {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf8},
- {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf3},
- {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x08},
- {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf1},
- {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xe0},
- {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2},
- {TM6010_REQ08_RED_GAIN_SEL, 0xe8},
- {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x62},
- {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfe},
- {TM6010_REQ07_RFE_POWER_DOWN, 0xcb},
- {0, 0, 0},
- },
- .nosif = {
- {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0},
- {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf8},
- {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf3},
- {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x0f},
- {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf1},
- {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xe0},
- {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2},
- {TM6010_REQ08_RED_GAIN_SEL, 0xe8},
- {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x60},
- {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc},
- {TM6010_REQ07_RFE_POWER_DOWN, 0x8b},
- {0, 0, 0},
- },
- .common = {
- {TM6010_REQ07_R3F_RESET, 0x01},
- {TM6010_REQ07_R00_VIDEO_CONTROL0, 0x38},
- {TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e},
- {TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f},
- {TM6010_REQ07_R03_YC_SEP_CONTROL, 0x02},
- {TM6010_REQ07_R07_OUTPUT_CONTROL, 0x31},
- {TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x24},
- {TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x92},
- {TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xe8},
- {TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xed},
- {TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c},
- {TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc},
- {TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc},
- {TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd},
- {TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x8c},
- {TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x2c},
- {TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0xc1},
- {TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x2c},
- {TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x18},
- {TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42},
- {TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0xFF},
-
- {TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07},
-
- {TM6010_REQ07_R3F_RESET, 0x00},
- {0, 0, 0},
- },
- }, {
- .id = V4L2_STD_NTSC,
- .audio_default_std = BTSC,
- .sif = {
- {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf2},
- {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf8},
- {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf3},
- {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x08},
- {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf1},
- {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xe0},
- {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2},
- {TM6010_REQ08_RED_GAIN_SEL, 0xe8},
- {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x62},
- {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfe},
- {TM6010_REQ07_RFE_POWER_DOWN, 0xcb},
- {0, 0, 0},
- },
- .nosif = {
- {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0},
- {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf8},
- {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf3},
- {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x0f},
- {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf1},
- {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xe0},
- {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2},
- {TM6010_REQ08_RED_GAIN_SEL, 0xe8},
- {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x60},
- {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc},
- {TM6010_REQ07_RFE_POWER_DOWN, 0x8b},
- {0, 0, 0},
- },
- .common = {
- {TM6010_REQ07_R3F_RESET, 0x01},
- {TM6010_REQ07_R00_VIDEO_CONTROL0, 0x00},
- {TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0f},
- {TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f},
- {TM6010_REQ07_R03_YC_SEP_CONTROL, 0x00},
- {TM6010_REQ07_R07_OUTPUT_CONTROL, 0x31},
- {TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x1e},
- {TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x8b},
- {TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xa2},
- {TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xe9},
- {TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c},
- {TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc},
- {TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc},
- {TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd},
- {TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x88},
- {TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x22},
- {TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0x61},
- {TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x1c},
- {TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x1c},
- {TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42},
- {TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0x6F},
-
- {TM6010_REQ07_R04_LUMA_HAGC_CONTROL, 0xdd},
- {TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07},
-
- {TM6010_REQ07_R3F_RESET, 0x00},
-
- {0, 0, 0},
- },
- },
+ struct tm6000_reg_settings common[27];
};
static struct tm6000_std_settings composite_stds[] = {
{
.id = V4L2_STD_PAL_M,
- .audio_default_std = BTSC,
.common = {
- {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0},
- {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf4},
- {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf3},
- {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x0f},
- {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf1},
- {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xe0},
- {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2},
- {TM6010_REQ08_RED_GAIN_SEL, 0xe8},
- {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x68},
- {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc},
- {TM6010_REQ07_RFE_POWER_DOWN, 0x8b},
-
{TM6010_REQ07_R3F_RESET, 0x01},
{TM6010_REQ07_R00_VIDEO_CONTROL0, 0x04},
{TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e},
@@ -467,20 +71,7 @@
},
}, {
.id = V4L2_STD_PAL_Nc,
- .audio_default_std = BTSC,
.common = {
- {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0},
- {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf4},
- {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf3},
- {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x0f},
- {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf1},
- {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xe0},
- {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2},
- {TM6010_REQ08_RED_GAIN_SEL, 0xe8},
- {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x68},
- {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc},
- {TM6010_REQ07_RFE_POWER_DOWN, 0x8b},
-
{TM6010_REQ07_R3F_RESET, 0x01},
{TM6010_REQ07_R00_VIDEO_CONTROL0, 0x36},
{TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e},
@@ -510,20 +101,7 @@
},
}, {
.id = V4L2_STD_PAL,
- .audio_default_std = BG_A2,
.common = {
- {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0},
- {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf4},
- {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf3},
- {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x0f},
- {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf1},
- {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xe0},
- {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2},
- {TM6010_REQ08_RED_GAIN_SEL, 0xe8},
- {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x68},
- {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc},
- {TM6010_REQ07_RFE_POWER_DOWN, 0x8b},
-
{TM6010_REQ07_R3F_RESET, 0x01},
{TM6010_REQ07_R00_VIDEO_CONTROL0, 0x32},
{TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e},
@@ -553,62 +131,7 @@
},
}, {
.id = V4L2_STD_SECAM,
- .audio_default_std = BG_NICAM,
.common = {
- {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0},
- {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf4},
- {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf3},
- {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x0f},
- {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf1},
- {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xe0},
- {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2},
- {TM6010_REQ08_RED_GAIN_SEL, 0xe8},
- {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x68},
- {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc},
- {TM6010_REQ07_RFE_POWER_DOWN, 0x8b},
-
- {TM6010_REQ07_R3F_RESET, 0x01},
- {TM6010_REQ07_R00_VIDEO_CONTROL0, 0x38},
- {TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e},
- {TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f},
- {TM6010_REQ07_R03_YC_SEP_CONTROL, 0x02},
- {TM6010_REQ07_R07_OUTPUT_CONTROL, 0x31},
- {TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x24},
- {TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x92},
- {TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xe8},
- {TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xed},
- {TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c},
- {TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc},
- {TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc},
- {TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd},
- {TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x8c},
- {TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x2c},
- {TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0xc1},
- {TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x2c},
- {TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x18},
- {TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42},
- {TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0xFF},
-
- {TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07},
- {TM6010_REQ07_R3F_RESET, 0x00},
- {0, 0, 0},
- },
- }, {
- .id = V4L2_STD_SECAM_DK,
- .audio_default_std = DK_NICAM,
- .common = {
- {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0},
- {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf4},
- {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf3},
- {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x0f},
- {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf1},
- {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xe0},
- {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2},
- {TM6010_REQ08_RED_GAIN_SEL, 0xe8},
- {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x68},
- {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc},
- {TM6010_REQ07_RFE_POWER_DOWN, 0x8b},
-
{TM6010_REQ07_R3F_RESET, 0x01},
{TM6010_REQ07_R00_VIDEO_CONTROL0, 0x38},
{TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e},
@@ -637,20 +160,7 @@
},
}, {
.id = V4L2_STD_NTSC,
- .audio_default_std = BTSC,
.common = {
- {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0},
- {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf4},
- {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf3},
- {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x0f},
- {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf1},
- {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xe0},
- {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2},
- {TM6010_REQ08_RED_GAIN_SEL, 0xe8},
- {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x68},
- {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc},
- {TM6010_REQ07_RFE_POWER_DOWN, 0x8b},
-
{TM6010_REQ07_R3F_RESET, 0x01},
{TM6010_REQ07_R00_VIDEO_CONTROL0, 0x00},
{TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0f},
@@ -684,20 +194,7 @@
static struct tm6000_std_settings svideo_stds[] = {
{
.id = V4L2_STD_PAL_M,
- .audio_default_std = BTSC,
.common = {
- {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0},
- {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xfc},
- {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf8},
- {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x00},
- {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf2},
- {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xf0},
- {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2},
- {TM6010_REQ08_RED_GAIN_SEL, 0xe0},
- {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x68},
- {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc},
- {TM6010_REQ07_RFE_POWER_DOWN, 0x8a},
-
{TM6010_REQ07_R3F_RESET, 0x01},
{TM6010_REQ07_R00_VIDEO_CONTROL0, 0x05},
{TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e},
@@ -727,20 +224,7 @@
},
}, {
.id = V4L2_STD_PAL_Nc,
- .audio_default_std = BTSC,
.common = {
- {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0},
- {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xfc},
- {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf8},
- {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x00},
- {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf2},
- {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xf0},
- {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2},
- {TM6010_REQ08_RED_GAIN_SEL, 0xe0},
- {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x68},
- {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc},
- {TM6010_REQ07_RFE_POWER_DOWN, 0x8a},
-
{TM6010_REQ07_R3F_RESET, 0x01},
{TM6010_REQ07_R00_VIDEO_CONTROL0, 0x37},
{TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e},
@@ -770,20 +254,7 @@
},
}, {
.id = V4L2_STD_PAL,
- .audio_default_std = BG_A2,
.common = {
- {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0},
- {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xfc},
- {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf8},
- {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x00},
- {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf2},
- {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xf0},
- {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2},
- {TM6010_REQ08_RED_GAIN_SEL, 0xe0},
- {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x68},
- {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc},
- {TM6010_REQ07_RFE_POWER_DOWN, 0x8a},
-
{TM6010_REQ07_R3F_RESET, 0x01},
{TM6010_REQ07_R00_VIDEO_CONTROL0, 0x33},
{TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e},
@@ -813,62 +284,7 @@
},
}, {
.id = V4L2_STD_SECAM,
- .audio_default_std = BG_NICAM,
.common = {
- {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0},
- {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xfc},
- {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf8},
- {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x00},
- {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf2},
- {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xf0},
- {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2},
- {TM6010_REQ08_RED_GAIN_SEL, 0xe0},
- {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x68},
- {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc},
- {TM6010_REQ07_RFE_POWER_DOWN, 0x8a},
-
- {TM6010_REQ07_R3F_RESET, 0x01},
- {TM6010_REQ07_R00_VIDEO_CONTROL0, 0x39},
- {TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e},
- {TM6010_REQ07_R02_VIDEO_CONTROL2, 0x5f},
- {TM6010_REQ07_R03_YC_SEP_CONTROL, 0x03},
- {TM6010_REQ07_R07_OUTPUT_CONTROL, 0x31},
- {TM6010_REQ07_R18_CHROMA_DTO_INCREMENT3, 0x24},
- {TM6010_REQ07_R19_CHROMA_DTO_INCREMENT2, 0x92},
- {TM6010_REQ07_R1A_CHROMA_DTO_INCREMENT1, 0xe8},
- {TM6010_REQ07_R1B_CHROMA_DTO_INCREMENT0, 0xed},
- {TM6010_REQ07_R1C_HSYNC_DTO_INCREMENT3, 0x1c},
- {TM6010_REQ07_R1D_HSYNC_DTO_INCREMENT2, 0xcc},
- {TM6010_REQ07_R1E_HSYNC_DTO_INCREMENT1, 0xcc},
- {TM6010_REQ07_R1F_HSYNC_DTO_INCREMENT0, 0xcd},
- {TM6010_REQ07_R2E_ACTIVE_VIDEO_HSTART, 0x8c},
- {TM6010_REQ07_R30_ACTIVE_VIDEO_VSTART, 0x2a},
- {TM6010_REQ07_R31_ACTIVE_VIDEO_VHIGHT, 0xc1},
- {TM6010_REQ07_R33_VSYNC_HLOCK_MAX, 0x2c},
- {TM6010_REQ07_R35_VSYNC_AGC_MAX, 0x18},
- {TM6010_REQ07_R82_COMB_FILTER_CONFIG, 0x42},
- {TM6010_REQ07_R83_CHROMA_LOCK_CONFIG, 0xFF},
-
- {TM6010_REQ07_R0D_CHROMA_KILL_LEVEL, 0x07},
- {TM6010_REQ07_R3F_RESET, 0x00},
- {0, 0, 0},
- },
- }, {
- .id = V4L2_STD_SECAM_DK,
- .audio_default_std = DK_NICAM,
- .common = {
- {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0},
- {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xfc},
- {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf8},
- {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x00},
- {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf2},
- {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xf0},
- {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2},
- {TM6010_REQ08_RED_GAIN_SEL, 0xe0},
- {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x68},
- {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc},
- {TM6010_REQ07_RFE_POWER_DOWN, 0x8a},
-
{TM6010_REQ07_R3F_RESET, 0x01},
{TM6010_REQ07_R00_VIDEO_CONTROL0, 0x39},
{TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0e},
@@ -897,20 +313,7 @@
},
}, {
.id = V4L2_STD_NTSC,
- .audio_default_std = BTSC,
.common = {
- {TM6010_REQ08_RE2_POWER_DOWN_CTRL1, 0xf0},
- {TM6010_REQ08_RE3_ADC_IN1_SEL, 0xfc},
- {TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf8},
- {TM6010_REQ08_RE6_POWER_DOWN_CTRL2, 0x00},
- {TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf2},
- {TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xf0},
- {TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2},
- {TM6010_REQ08_RED_GAIN_SEL, 0xe0},
- {TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG, 0x68},
- {TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc},
- {TM6010_REQ07_RFE_POWER_DOWN, 0x8a},
-
{TM6010_REQ07_R3F_RESET, 0x01},
{TM6010_REQ07_R00_VIDEO_CONTROL0, 0x01},
{TM6010_REQ07_R01_VIDEO_CONTROL1, 0x0f},
@@ -943,13 +346,11 @@
};
-static int tm6000_set_audio_std(struct tm6000_core *dev,
- enum tm6000_audio_std std)
+static int tm6000_set_audio_std(struct tm6000_core *dev)
{
uint8_t areg_02 = 0x04; /* GC1 Fixed gain 0dB */
- uint8_t areg_05 = 0x09; /* Auto 4.5 = M Japan, Auto 6.5 = DK */
+ uint8_t areg_05 = 0x01; /* Auto 4.5 = M Japan, Auto 6.5 = DK */
uint8_t areg_06 = 0x02; /* Auto de-emphasis, mannual channel mode */
- uint8_t mono_flag = 0; /* No mono */
uint8_t nicam_flag = 0; /* No NICAM */
if (dev->radio) {
@@ -958,82 +359,100 @@
tm6000_set_reg(dev, TM6010_REQ08_R03_A_AUTO_GAIN_CTRL, 0x00);
tm6000_set_reg(dev, TM6010_REQ08_R04_A_SIF_AMP_CTRL, 0x80);
tm6000_set_reg(dev, TM6010_REQ08_R05_A_STANDARD_MOD, 0x0c);
- tm6000_set_reg(dev, TM6010_REQ08_R06_A_SOUND_MOD, 0x00);
+ /* set mono or stereo */
+ if (dev->amode == V4L2_TUNER_MODE_MONO)
+ tm6000_set_reg(dev, TM6010_REQ08_R06_A_SOUND_MOD, 0x00);
+ else if (dev->amode == V4L2_TUNER_MODE_STEREO)
+ tm6000_set_reg(dev, TM6010_REQ08_R06_A_SOUND_MOD, 0x02);
tm6000_set_reg(dev, TM6010_REQ08_R09_A_MAIN_VOL, 0x18);
tm6000_set_reg(dev, TM6010_REQ08_R0C_A_ASD_THRES2, 0x0a);
tm6000_set_reg(dev, TM6010_REQ08_R0D_A_AMD_THRES, 0x40);
- tm6000_set_reg(dev, TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc);
+ tm6000_set_reg(dev, TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfe);
tm6000_set_reg(dev, TM6010_REQ08_R1E_A_GAIN_DEEMPH_OUT, 0x13);
tm6000_set_reg(dev, TM6010_REQ08_R01_A_INIT, 0x80);
return 0;
}
- switch (std) {
-#if 0
- case DK_MONO:
- mono_flag = 1;
+ switch (tm6010_a_mode) {
+ /* auto */
+ case 0:
+ switch (dev->norm) {
+ case V4L2_STD_NTSC_M_KR:
+ areg_05 |= 0x00;
+ break;
+ case V4L2_STD_NTSC_M_JP:
+ areg_05 |= 0x40;
+ break;
+ case V4L2_STD_NTSC_M:
+ case V4L2_STD_PAL_M:
+ case V4L2_STD_PAL_N:
+ areg_05 |= 0x20;
+ break;
+ case V4L2_STD_PAL_Nc:
+ areg_05 |= 0x60;
+ break;
+ case V4L2_STD_SECAM_L:
+ areg_05 |= 0x00;
+ break;
+ case V4L2_STD_DK:
+ areg_05 |= 0x10;
+ break;
+ }
break;
- case DK_A2_1:
+ /* A2 */
+ case 1:
+ switch (dev->norm) {
+ case V4L2_STD_B:
+ case V4L2_STD_GH:
+ areg_05 = 0x05;
+ break;
+ case V4L2_STD_DK:
+ areg_05 = 0x09;
+ break;
+ }
break;
- case DK_A2_3:
- areg_05 = 0x0b;
- break;
- case BG_MONO:
- mono_flag = 1;
- areg_05 = 0x05;
- break;
-#endif
- case BG_NICAM:
- areg_05 = 0x07;
+ /* NICAM */
+ case 2:
+ switch (dev->norm) {
+ case V4L2_STD_B:
+ case V4L2_STD_GH:
+ areg_05 = 0x07;
+ break;
+ case V4L2_STD_DK:
+ areg_05 = 0x06;
+ break;
+ case V4L2_STD_PAL_I:
+ areg_05 = 0x08;
+ break;
+ case V4L2_STD_SECAM_L:
+ areg_05 = 0x0a;
+ areg_02 = 0x02;
+ break;
+ }
nicam_flag = 1;
break;
- case BTSC:
- areg_05 = 0x02;
- break;
- case BG_A2:
- areg_05 = 0x05;
- break;
- case DK_NICAM:
- areg_05 = 0x06;
- nicam_flag = 1;
- break;
- case EIAJ:
- areg_05 = 0x02;
- break;
- case I_NICAM:
- areg_05 = 0x08;
- nicam_flag = 1;
- break;
- case KOREA_A2:
- areg_05 = 0x04;
- break;
- case L_NICAM:
- areg_02 = 0x02; /* GC1 Fixed gain +12dB */
- areg_05 = 0x0a;
- nicam_flag = 1;
- break;
- default:
- /* do nothink */
+ /* other */
+ case 3:
+ switch (dev->norm) {
+ /* DK3_A2 */
+ case V4L2_STD_DK:
+ areg_05 = 0x0b;
+ break;
+ /* Korea */
+ case V4L2_STD_NTSC_M_KR:
+ areg_05 = 0x04;
+ break;
+ /* EIAJ */
+ case V4L2_STD_NTSC_M_JP:
+ areg_05 = 0x03;
+ break;
+ default:
+ areg_05 = 0x02;
+ break;
+ }
break;
}
-#if 0
- switch (tv_audio_mode) {
- case TV_MONO:
- areg_06 = (nicam_flag) ? 0x03 : 0x00;
- break;
- case TV_LANG_A:
- areg_06 = 0x00;
- break;
- case TV_LANG_B:
- areg_06 = 0x01;
- break;
- }
-#endif
-
- if (mono_flag)
- areg_06 = 0x00;
-
tm6000_set_reg(dev, TM6010_REQ08_R01_A_INIT, 0x00);
tm6000_set_reg(dev, TM6010_REQ08_R02_A_FIX_GAIN_CTRL, areg_02);
tm6000_set_reg(dev, TM6010_REQ08_R03_A_AUTO_GAIN_CTRL, 0x00);
@@ -1066,9 +485,6 @@
tm6000_set_reg(dev, TM6010_REQ08_R1E_A_GAIN_DEEMPH_OUT, 0x13);
tm6000_set_reg(dev, TM6010_REQ08_R1F_A_TEST_INTF_SEL, 0x00);
tm6000_set_reg(dev, TM6010_REQ08_R20_A_TEST_PIN_SEL, 0x00);
- tm6000_set_reg(dev, TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf3);
- tm6000_set_reg(dev, TM6010_REQ08_R06_A_SOUND_MOD, 0x00);
- tm6000_set_reg(dev, TM6010_REQ08_RF1_AADC_POWER_DOWN, 0xfc);
tm6000_set_reg(dev, TM6010_REQ08_R01_A_INIT, 0x80);
return 0;
@@ -1095,10 +511,6 @@
if (!set[i].req)
return 0;
- if ((dev->dev_type != TM6010) &&
- (set[i].req == REQ_08_SET_GET_AVREG_BIT))
- continue;
-
rc = tm6000_set_reg(dev, set[i].req, set[i].reg, set[i].value);
if (rc < 0) {
printk(KERN_ERR "Error %i while setting "
@@ -1111,53 +523,126 @@
return 0;
}
-static int tm6000_set_tv(struct tm6000_core *dev, int pos)
-{
- int rc;
-
- /* FIXME: This code is for tm6010 - not tested yet - doesn't work with
- tm5600
- */
-
- /* FIXME: This is tuner-dependent */
- int nosif = 0;
-
- if (nosif) {
- rc = tm6000_load_std(dev, tv_stds[pos].nosif,
- sizeof(tv_stds[pos].nosif));
- } else {
- rc = tm6000_load_std(dev, tv_stds[pos].sif,
- sizeof(tv_stds[pos].sif));
- }
- if (rc < 0)
- return rc;
- rc = tm6000_load_std(dev, tv_stds[pos].common,
- sizeof(tv_stds[pos].common));
-
- tm6000_set_audio_std(dev, tv_stds[pos].audio_default_std);
-
- return rc;
-}
-
-int tm6000_set_standard(struct tm6000_core *dev, v4l2_std_id * norm)
+int tm6000_set_standard(struct tm6000_core *dev)
{
int i, rc = 0;
+ u8 reg_07_fe = 0x8a;
+ u8 reg_08_f1 = 0xfc;
+ u8 reg_08_e2 = 0xf0;
+ u8 reg_08_e6 = 0x0f;
- dev->norm = *norm;
tm6000_get_std_res(dev);
- switch (dev->input) {
- case TM6000_INPUT_TV:
- for (i = 0; i < ARRAY_SIZE(tv_stds); i++) {
- if (*norm & tv_stds[i].id) {
- rc = tm6000_set_tv(dev, i);
- goto ret;
- }
+ if (dev->radio) {
+ /* todo */
+ }
+
+ if (dev->dev_type == TM6010) {
+ switch (dev->vinput[dev->input].vmux) {
+ case TM6000_VMUX_VIDEO_A:
+ tm6000_set_reg(dev, TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf4);
+ tm6000_set_reg(dev, TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf1);
+ tm6000_set_reg(dev, TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xe0);
+ tm6000_set_reg(dev, TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2);
+ tm6000_set_reg(dev, TM6010_REQ08_RED_GAIN_SEL, 0xe8);
+ reg_07_fe |= 0x01;
+ break;
+ case TM6000_VMUX_VIDEO_B:
+ tm6000_set_reg(dev, TM6010_REQ08_RE3_ADC_IN1_SEL, 0xf8);
+ tm6000_set_reg(dev, TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf1);
+ tm6000_set_reg(dev, TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xe0);
+ tm6000_set_reg(dev, TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2);
+ tm6000_set_reg(dev, TM6010_REQ08_RED_GAIN_SEL, 0xe8);
+ reg_07_fe |= 0x01;
+ break;
+ case TM6000_VMUX_VIDEO_AB:
+ tm6000_set_reg(dev, TM6010_REQ08_RE3_ADC_IN1_SEL, 0xfc);
+ tm6000_set_reg(dev, TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf8);
+ reg_08_e6 = 0x00;
+ tm6000_set_reg(dev, TM6010_REQ08_REA_BUFF_DRV_CTRL, 0xf2);
+ tm6000_set_reg(dev, TM6010_REQ08_REB_SIF_GAIN_CTRL, 0xf0);
+ tm6000_set_reg(dev, TM6010_REQ08_REC_REVERSE_YC_CTRL, 0xc2);
+ tm6000_set_reg(dev, TM6010_REQ08_RED_GAIN_SEL, 0xe0);
+ break;
+ default:
+ break;
}
- return -EINVAL;
- case TM6000_INPUT_SVIDEO:
+ switch (dev->vinput[dev->input].amux) {
+ case TM6000_AMUX_ADC1:
+ tm6000_set_reg_mask(dev, TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG,
+ 0x00, 0x0f);
+ break;
+ case TM6000_AMUX_ADC2:
+ tm6000_set_reg_mask(dev, TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG,
+ 0x08, 0x0f);
+ break;
+ case TM6000_AMUX_SIF1:
+ reg_08_e2 |= 0x02;
+ reg_08_e6 = 0x08;
+ reg_07_fe |= 0x40;
+ reg_08_f1 |= 0x02;
+ tm6000_set_reg(dev, TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf3);
+ tm6000_set_reg_mask(dev, TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG,
+ 0x02, 0x0f);
+ break;
+ case TM6000_AMUX_SIF2:
+ reg_08_e2 |= 0x02;
+ reg_08_e6 = 0x08;
+ reg_07_fe |= 0x40;
+ reg_08_f1 |= 0x02;
+ tm6000_set_reg(dev, TM6010_REQ08_RE4_ADC_IN2_SEL, 0xf7);
+ tm6000_set_reg_mask(dev, TM6010_REQ08_RF0_DAUDIO_INPUT_CONFIG,
+ 0x02, 0x0f);
+ break;
+ default:
+ break;
+ }
+ tm6000_set_reg(dev, TM6010_REQ08_RE2_POWER_DOWN_CTRL1, reg_08_e2);
+ tm6000_set_reg(dev, TM6010_REQ08_RE6_POWER_DOWN_CTRL2, reg_08_e6);
+ tm6000_set_reg(dev, TM6010_REQ08_RF1_AADC_POWER_DOWN, reg_08_f1);
+ tm6000_set_reg(dev, TM6010_REQ07_RFE_POWER_DOWN, reg_07_fe);
+ } else {
+ switch (dev->vinput[dev->input].vmux) {
+ case TM6000_VMUX_VIDEO_A:
+ tm6000_set_reg(dev, TM6000_REQ07_RE3_VADC_INP_LPF_SEL1, 0x10);
+ tm6000_set_reg(dev, TM6000_REQ07_RE5_VADC_INP_LPF_SEL2, 0x00);
+ tm6000_set_reg(dev, TM6000_REQ07_RE8_VADC_PWDOWN_CTL, 0x0f);
+ tm6000_set_reg(dev,
+ REQ_03_SET_GET_MCU_PIN, dev->vinput[dev->input].v_gpio, 0);
+ break;
+ case TM6000_VMUX_VIDEO_B:
+ tm6000_set_reg(dev, TM6000_REQ07_RE3_VADC_INP_LPF_SEL1, 0x00);
+ tm6000_set_reg(dev, TM6000_REQ07_RE5_VADC_INP_LPF_SEL2, 0x00);
+ tm6000_set_reg(dev, TM6000_REQ07_RE8_VADC_PWDOWN_CTL, 0x0f);
+ tm6000_set_reg(dev,
+ REQ_03_SET_GET_MCU_PIN, dev->vinput[dev->input].v_gpio, 0);
+ break;
+ case TM6000_VMUX_VIDEO_AB:
+ tm6000_set_reg(dev, TM6000_REQ07_RE3_VADC_INP_LPF_SEL1, 0x10);
+ tm6000_set_reg(dev, TM6000_REQ07_RE5_VADC_INP_LPF_SEL2, 0x10);
+ tm6000_set_reg(dev, TM6000_REQ07_RE8_VADC_PWDOWN_CTL, 0x00);
+ tm6000_set_reg(dev,
+ REQ_03_SET_GET_MCU_PIN, dev->vinput[dev->input].v_gpio, 1);
+ break;
+ default:
+ break;
+ }
+ switch (dev->vinput[dev->input].amux) {
+ case TM6000_AMUX_ADC1:
+ tm6000_set_reg_mask(dev,
+ TM6000_REQ07_REB_VADC_AADC_MODE, 0x00, 0x0f);
+ break;
+ case TM6000_AMUX_ADC2:
+ tm6000_set_reg_mask(dev,
+ TM6000_REQ07_REB_VADC_AADC_MODE, 0x04, 0x0f);
+ break;
+ default:
+ break;
+ }
+ }
+ if (dev->vinput[dev->input].type == TM6000_INPUT_SVIDEO) {
for (i = 0; i < ARRAY_SIZE(svideo_stds); i++) {
- if (*norm & svideo_stds[i].id) {
+ if (dev->norm & svideo_stds[i].id) {
rc = tm6000_load_std(dev, svideo_stds[i].common,
sizeof(svideo_stds[i].
common));
@@ -1165,14 +650,13 @@
}
}
return -EINVAL;
- case TM6000_INPUT_COMPOSITE:
+ } else {
for (i = 0; i < ARRAY_SIZE(composite_stds); i++) {
- if (*norm & composite_stds[i].id) {
+ if (dev->norm & composite_stds[i].id) {
rc = tm6000_load_std(dev,
composite_stds[i].common,
sizeof(composite_stds[i].
common));
- tm6000_set_audio_std(dev, composite_stds[i].audio_default_std);
goto ret;
}
}
@@ -1183,6 +667,11 @@
if (rc < 0)
return rc;
+ if ((dev->dev_type == TM6010) &&
+ ((dev->vinput[dev->input].amux == TM6000_AMUX_SIF1) ||
+ (dev->vinput[dev->input].amux == TM6000_AMUX_SIF2)))
+ tm6000_set_audio_std(dev);
+
msleep(40);
diff --git a/drivers/staging/tm6000/tm6000-usb-isoc.h b/drivers/staging/tm6000/tm6000-usb-isoc.h
index a9e61d9..084c2a8 100644
--- a/drivers/staging/tm6000/tm6000-usb-isoc.h
+++ b/drivers/staging/tm6000/tm6000-usb-isoc.h
@@ -39,7 +39,7 @@
int pos, size, pktsize;
/* Last field: ODD or EVEN? */
- int vfield;
+ int vfield, field;
/* Stores incomplete commands */
u32 tmp_buf;
diff --git a/drivers/staging/tm6000/tm6000-video.c b/drivers/staging/tm6000/tm6000-video.c
index 17db668..4264064 100644
--- a/drivers/staging/tm6000/tm6000-video.c
+++ b/drivers/staging/tm6000/tm6000-video.c
@@ -34,6 +34,7 @@
#include <linux/usb.h>
#include <linux/videodev2.h>
#include <media/v4l2-ioctl.h>
+#include <media/tuner.h>
#include <linux/interrupt.h>
#include <linux/kthread.h>
#include <linux/highmem.h>
@@ -228,7 +229,7 @@
unsigned long header = 0;
int rc = 0;
unsigned int cmd, cpysize, pktsize, size, field, block, line, pos = 0;
- struct tm6000_buffer *vbuf;
+ struct tm6000_buffer *vbuf = NULL;
char *voutp = NULL;
unsigned int linewidth;
@@ -318,7 +319,7 @@
if (pos + size > vbuf->vb.size)
cmd = TM6000_URB_MSG_ERR;
dev->isoc_ctl.vfield = field;
- }
+ }
break;
case TM6000_URB_MSG_VBI:
break;
@@ -333,6 +334,7 @@
size = dev->isoc_ctl.size;
pos = dev->isoc_ctl.pos;
pktsize = dev->isoc_ctl.pktsize;
+ field = dev->isoc_ctl.field;
}
cpysize = (endp - ptr > size) ? size : endp - ptr;
if (cpysize) {
@@ -343,24 +345,26 @@
if (vbuf)
memcpy(&voutp[pos], ptr, cpysize);
break;
- case TM6000_URB_MSG_AUDIO:
- /* Need some code to copy audio buffer */
- if (dev->fourcc == V4L2_PIX_FMT_YUYV) {
- /* Swap word bytes */
- int i;
+ case TM6000_URB_MSG_AUDIO: {
+ int i;
+ for (i = 0; i < cpysize; i += 2)
+ swab16s((u16 *)(ptr + i));
- for (i = 0; i < cpysize; i += 2)
- swab16s((u16 *)(ptr + i));
- }
tm6000_call_fillbuf(dev, TM6000_AUDIO, ptr, cpysize);
break;
+ }
case TM6000_URB_MSG_VBI:
/* Need some code to copy vbi buffer */
break;
- case TM6000_URB_MSG_PTS:
+ case TM6000_URB_MSG_PTS: {
/* Need some code to copy pts */
+ u32 pts;
+ pts = *(u32 *)ptr;
+ dprintk(dev, V4L2_DEBUG_ISOC, "field %d, PTS %x",
+ field, pts);
break;
}
+ }
}
if (ptr + pktsize > endp) {
/* End of URB packet, but cmd processing is not
@@ -369,6 +373,7 @@
dev->isoc_ctl.pos = pos + cpysize;
dev->isoc_ctl.size = size - cpysize;
dev->isoc_ctl.cmd = cmd;
+ dev->isoc_ctl.field = field;
dev->isoc_ctl.pktsize = pktsize - (endp - ptr);
ptr += endp - ptr;
} else {
@@ -883,14 +888,19 @@
static int vidioc_querycap(struct file *file, void *priv,
struct v4l2_capability *cap)
{
+ struct tm6000_core *dev = ((struct tm6000_fh *)priv)->dev;
strlcpy(cap->driver, "tm6000", sizeof(cap->driver));
strlcpy(cap->card, "Trident TVMaster TM5600/6000/6010", sizeof(cap->card));
cap->version = TM6000_VERSION;
cap->capabilities = V4L2_CAP_VIDEO_CAPTURE |
V4L2_CAP_STREAMING |
- V4L2_CAP_TUNER |
+ V4L2_CAP_AUDIO |
V4L2_CAP_READWRITE;
+
+ if (dev->tuner_type != TUNER_ABSENT)
+ cap->capabilities |= V4L2_CAP_TUNER;
+
return 0;
}
@@ -1077,35 +1087,37 @@
return 0;
}
+static const char *iname [] = {
+ [TM6000_INPUT_TV] = "Television",
+ [TM6000_INPUT_COMPOSITE1] = "Composite 1",
+ [TM6000_INPUT_COMPOSITE2] = "Composite 2",
+ [TM6000_INPUT_SVIDEO] = "S-Video",
+};
+
static int vidioc_enum_input(struct file *file, void *priv,
- struct v4l2_input *inp)
+ struct v4l2_input *i)
{
struct tm6000_fh *fh = priv;
struct tm6000_core *dev = fh->dev;
+ unsigned int n;
- switch (inp->index) {
- case TM6000_INPUT_TV:
- inp->type = V4L2_INPUT_TYPE_TUNER;
- strcpy(inp->name, "Television");
- break;
- case TM6000_INPUT_COMPOSITE:
- if (dev->caps.has_input_comp) {
- inp->type = V4L2_INPUT_TYPE_CAMERA;
- strcpy(inp->name, "Composite");
- } else
- return -EINVAL;
- break;
- case TM6000_INPUT_SVIDEO:
- if (dev->caps.has_input_svid) {
- inp->type = V4L2_INPUT_TYPE_CAMERA;
- strcpy(inp->name, "S-Video");
- } else
- return -EINVAL;
- break;
- default:
+ n = i->index;
+ if (n >= 3)
return -EINVAL;
- }
- inp->std = TM6000_STD;
+
+ if (!dev->vinput[n].type)
+ return -EINVAL;
+
+ i->index = n;
+
+ if (dev->vinput[n].type == TM6000_INPUT_TV)
+ i->type = V4L2_INPUT_TYPE_TUNER;
+ else
+ i->type = V4L2_INPUT_TYPE_CAMERA;
+
+ strcpy(i->name, iname[dev->vinput[n].type]);
+
+ i->std = TM6000_STD;
return 0;
}
@@ -1119,38 +1131,26 @@
return 0;
}
+
static int vidioc_s_input(struct file *file, void *priv, unsigned int i)
{
struct tm6000_fh *fh = priv;
struct tm6000_core *dev = fh->dev;
int rc = 0;
- char buf[1];
- switch (i) {
- case TM6000_INPUT_TV:
- dev->input = i;
- *buf = 0;
- break;
- case TM6000_INPUT_COMPOSITE:
- case TM6000_INPUT_SVIDEO:
- dev->input = i;
- *buf = 1;
- break;
- default:
+ if (i >= 3)
return -EINVAL;
- }
- rc = tm6000_read_write_usb(dev, USB_DIR_OUT | USB_TYPE_VENDOR,
- REQ_03_SET_GET_MCU_PIN, 0x03, 1, buf, 1);
+ if (!dev->vinput[i].type)
+ return -EINVAL;
- if (!rc) {
- dev->input = i;
- rc = vidioc_s_std(file, priv, &dev->vfd->current_norm);
- }
+ dev->input = i;
+
+ rc = vidioc_s_std(file, priv, &dev->vfd->current_norm);
return rc;
}
- /* --- controls ---------------------------------------------- */
+/* --- controls ---------------------------------------------- */
static int vidioc_queryctrl(struct file *file, void *priv,
struct v4l2_queryctrl *qc)
{
@@ -1251,7 +1251,11 @@
t->type = V4L2_TUNER_ANALOG_TV;
t->capability = V4L2_TUNER_CAP_NORM;
t->rangehigh = 0xffffffffUL;
- t->rxsubchans = V4L2_TUNER_SUB_MONO;
+ t->rxsubchans = V4L2_TUNER_SUB_STEREO;
+
+ v4l2_device_call_all(&dev->v4l2_dev, 0, tuner, g_tuner, t);
+
+ t->audmode = dev->amode;
return 0;
}
@@ -1267,6 +1271,11 @@
if (0 != t->index)
return -EINVAL;
+ dev->amode = t->audmode;
+ dprintk(dev, 3, "audio mode: %x\n", t->audmode);
+
+ v4l2_device_call_all(&dev->v4l2_dev, 0, tuner, s_tuner, t);
+
return 0;
}
@@ -1320,7 +1329,11 @@
le16_to_cpu(dev->udev->descriptor.idVendor),
le16_to_cpu(dev->udev->descriptor.idProduct));
cap->version = dev->dev_type;
- cap->capabilities = V4L2_CAP_TUNER;
+ cap->capabilities = V4L2_CAP_TUNER |
+ V4L2_CAP_AUDIO |
+ V4L2_CAP_RADIO |
+ V4L2_CAP_READWRITE |
+ V4L2_CAP_STREAMING;
return 0;
}
@@ -1337,17 +1350,10 @@
memset(t, 0, sizeof(*t));
strcpy(t->name, "Radio");
t->type = V4L2_TUNER_RADIO;
+ t->rxsubchans = V4L2_TUNER_SUB_STEREO;
v4l2_device_call_all(&dev->v4l2_dev, 0, tuner, g_tuner, t);
- if ((dev->aradio == TM6000_AIP_LINE1) ||
- (dev->aradio == TM6000_AIP_LINE2)) {
- t->rxsubchans = V4L2_TUNER_SUB_MONO;
- }
- else {
- t->rxsubchans = V4L2_TUNER_SUB_STEREO;
- }
-
return 0;
}
@@ -1368,9 +1374,15 @@
static int radio_enum_input(struct file *file, void *priv,
struct v4l2_input *i)
{
+ struct tm6000_fh *fh = priv;
+ struct tm6000_core *dev = fh->dev;
+
if (i->index != 0)
return -EINVAL;
+ if (!dev->rinput.type)
+ return -EINVAL;
+
strcpy(i->name, "Radio");
i->type = V4L2_INPUT_TYPE_TUNER;
@@ -1379,7 +1391,14 @@
static int radio_g_input(struct file *filp, void *priv, unsigned int *i)
{
- *i = 0;
+ struct tm6000_fh *fh = priv;
+ struct tm6000_core *dev = fh->dev;
+
+ if (dev->input !=5)
+ return -EINVAL;
+
+ *i = dev->input -5;
+
return 0;
}
@@ -1399,6 +1418,17 @@
static int radio_s_input(struct file *filp, void *priv, unsigned int i)
{
+ struct tm6000_fh *fh = priv;
+ struct tm6000_core *dev = fh->dev;
+
+ if (i)
+ return -EINVAL;
+
+ if (!dev->rinput.type)
+ return -EINVAL;
+
+ dev->input = i + 5;
+
return 0;
}
@@ -1512,16 +1542,12 @@
if (fh->radio) {
dprintk(dev, V4L2_DEBUG_OPEN, "video_open: setting radio device\n");
- tm6000_set_audio_input(dev, dev->aradio);
- tm6000_set_volume(dev, dev->ctl_volume);
+ dev->input = 5;
+ tm6000_set_audio_rinput(dev);
v4l2_device_call_all(&dev->v4l2_dev, 0, tuner, s_radio);
tm6000_prepare_isoc(dev);
tm6000_start_thread(dev);
}
- else {
- tm6000_set_audio_input(dev, dev->avideo);
- tm6000_set_volume(dev, dev->ctl_volume);
- }
return 0;
}
@@ -1647,10 +1673,10 @@
};
static const struct v4l2_file_operations radio_fops = {
- .owner = THIS_MODULE,
- .open = tm6000_open,
- .release = tm6000_release,
- .ioctl = video_ioctl2,
+ .owner = THIS_MODULE,
+ .open = tm6000_open,
+ .release = tm6000_release,
+ .unlocked_ioctl = video_ioctl2,
};
static const struct v4l2_ioctl_ops radio_ioctl_ops = {
@@ -1730,24 +1756,26 @@
printk(KERN_INFO "%s: registered device %s\n",
dev->name, video_device_node_name(dev->vfd));
- dev->radio_dev = vdev_init(dev, &tm6000_radio_template,
- "radio");
- if (!dev->radio_dev) {
- printk(KERN_INFO "%s: can't register radio device\n",
- dev->name);
- return ret; /* FIXME release resource */
- }
+ if (dev->caps.has_radio) {
+ dev->radio_dev = vdev_init(dev, &tm6000_radio_template,
+ "radio");
+ if (!dev->radio_dev) {
+ printk(KERN_INFO "%s: can't register radio device\n",
+ dev->name);
+ return ret; /* FIXME release resource */
+ }
- ret = video_register_device(dev->radio_dev, VFL_TYPE_RADIO,
- radio_nr);
- if (ret < 0) {
- printk(KERN_INFO "%s: can't register radio device\n",
- dev->name);
- return ret; /* FIXME release resource */
- }
+ ret = video_register_device(dev->radio_dev, VFL_TYPE_RADIO,
+ radio_nr);
+ if (ret < 0) {
+ printk(KERN_INFO "%s: can't register radio device\n",
+ dev->name);
+ return ret; /* FIXME release resource */
+ }
- printk(KERN_INFO "%s: registered device %s\n",
- dev->name, video_device_node_name(dev->radio_dev));
+ printk(KERN_INFO "%s: registered device %s\n",
+ dev->name, video_device_node_name(dev->radio_dev));
+ }
printk(KERN_INFO "Trident TVMaster TM5600/TM6000/TM6010 USB2 board (Load status: %d)\n", ret);
return ret;
diff --git a/drivers/staging/tm6000/tm6000.h b/drivers/staging/tm6000/tm6000.h
index 99ae50e..ae6369b 100644
--- a/drivers/staging/tm6000/tm6000.h
+++ b/drivers/staging/tm6000/tm6000.h
@@ -40,11 +40,24 @@
#define TM6000_VERSION KERNEL_VERSION(0, 0, 2)
/* Inputs */
-
enum tm6000_itype {
- TM6000_INPUT_TV = 0,
- TM6000_INPUT_COMPOSITE,
+ TM6000_INPUT_TV = 1,
+ TM6000_INPUT_COMPOSITE1,
+ TM6000_INPUT_COMPOSITE2,
TM6000_INPUT_SVIDEO,
+ TM6000_INPUT_DVB,
+ TM6000_INPUT_RADIO,
+};
+
+enum tm6000_mux {
+ TM6000_VMUX_VIDEO_A = 1,
+ TM6000_VMUX_VIDEO_B,
+ TM6000_VMUX_VIDEO_AB,
+ TM6000_AMUX_ADC1,
+ TM6000_AMUX_ADC2,
+ TM6000_AMUX_SIF1,
+ TM6000_AMUX_SIF2,
+ TM6000_AMUX_I2S,
};
enum tm6000_devtype {
@@ -53,12 +66,12 @@
TM6010,
};
-enum tm6000_inaudio {
- TM6000_AIP_UNK = 0,
- TM6000_AIP_SIF1,
- TM6000_AIP_SIF2,
- TM6000_AIP_LINE1,
- TM6000_AIP_LINE2,
+struct tm6000_input {
+ enum tm6000_itype type;
+ enum tm6000_mux vmux;
+ enum tm6000_mux amux;
+ unsigned int v_gpio;
+ unsigned int a_gpio;
};
/* ------------------------------------------------------------------
@@ -129,8 +142,7 @@
unsigned int has_zl10353:1;
unsigned int has_eeprom:1;
unsigned int has_remote:1;
- unsigned int has_input_comp:1;
- unsigned int has_input_svid:1;
+ unsigned int has_radio:1;
};
struct tm6000_dvb {
@@ -167,6 +179,8 @@
int model; /* index in the device_data struct */
int devno; /* marks the number of this device */
enum tm6000_devtype dev_type; /* type of device */
+ unsigned char eedata[256]; /* Eeprom data */
+ unsigned eedata_size; /* Size of the eeprom info */
v4l2_std_id norm; /* Current norm */
int width, height; /* Selected resolution */
@@ -211,6 +225,9 @@
struct v4l2_device v4l2_dev;
int input;
+ struct tm6000_input vinput[3]; /* video input */
+ struct tm6000_input rinput; /* radio input */
+
int freq;
unsigned int fourcc;
@@ -218,6 +235,7 @@
int ctl_mute; /* audio */
int ctl_volume;
+ int amode;
/* DVB-T support */
struct tm6000_dvb *dvb;
@@ -226,8 +244,6 @@
struct snd_tm6000_card *adev;
struct work_struct wq_trigger; /* Trigger to start/stop audio for alsa module */
atomic_t stream_started; /* stream should be running if true */
- enum tm6000_inaudio avideo;
- enum tm6000_inaudio aradio;
struct tm6000_IR *ir;
@@ -302,7 +318,7 @@
int tm6000_init_analog_mode(struct tm6000_core *dev);
int tm6000_init_digital_mode(struct tm6000_core *dev);
int tm6000_set_audio_bitrate(struct tm6000_core *dev, int bitrate);
-int tm6000_set_audio_input(struct tm6000_core *dev, enum tm6000_inaudio ainp);
+int tm6000_set_audio_rinput(struct tm6000_core *dev);
int tm6000_tvaudio_set_mute(struct tm6000_core *dev, u8 mute);
void tm6000_set_volume(struct tm6000_core *dev, int vol);
@@ -323,7 +339,7 @@
/* In tm6000-stds.c */
void tm6000_get_std_res(struct tm6000_core *dev);
-int tm6000_set_standard(struct tm6000_core *dev, v4l2_std_id *norm);
+int tm6000_set_standard(struct tm6000_core *dev);
/* In tm6000-i2c.c */
int tm6000_i2c_register(struct tm6000_core *dev);
diff --git a/drivers/staging/tty/istallion.c b/drivers/staging/tty/istallion.c
index 0b26627..ca18cbf 100644
--- a/drivers/staging/tty/istallion.c
+++ b/drivers/staging/tty/istallion.c
@@ -186,7 +186,6 @@
* re-used for each stats call.
*/
static comstats_t stli_comstats;
-static combrd_t stli_brdstats;
static struct asystats stli_cdkstats;
/*****************************************************************************/
@@ -4005,6 +4004,7 @@
{
struct stlibrd *brdp;
unsigned int i;
+ combrd_t stli_brdstats;
if (copy_from_user(&stli_brdstats, bp, sizeof(combrd_t)))
return -EFAULT;
diff --git a/drivers/staging/usbip/Kconfig b/drivers/staging/usbip/Kconfig
index 2c1d10a..dd13c02 100644
--- a/drivers/staging/usbip/Kconfig
+++ b/drivers/staging/usbip/Kconfig
@@ -1,43 +1,45 @@
-config USB_IP_COMMON
- tristate "USB IP support (EXPERIMENTAL)"
+config USBIP_CORE
+ tristate "USB/IP support (EXPERIMENTAL)"
depends on USB && NET && EXPERIMENTAL
default N
---help---
This enables pushing USB packets over IP to allow remote
- machines access to USB devices directly. For more details,
- and links to the userspace utility programs to let this work
- properly, see http://usbip.sourceforge.net/.
+ machines direct access to USB devices. It provides the
+ USB/IP core that is required by both drivers.
- To compile this driver as a module, choose M here: the
- module will be called usbip_common_mod.
+ For more details, and to get the userspace utility
+ programs, please see http://usbip.sourceforge.net/.
+
+ To compile this as a module, choose M here: the module will
+ be called usbip-core.
If unsure, say N.
-config USB_IP_VHCI_HCD
- tristate "USB IP client driver"
- depends on USB_IP_COMMON
+config USBIP_VHCI_HCD
+ tristate "VHCI hcd"
+ depends on USBIP_CORE
default N
---help---
- This enables the USB IP host controller driver which will
- run on the client machine.
+ This enables the USB/IP virtual host controller driver,
+ which is run on the remote machine.
- To compile this driver as a module, choose M here: the
- module will be called vhci_hcd.
+ To compile this driver as a module, choose M here: the
+ module will be called vhci-hcd.
-config USB_IP_HOST
- tristate "USB IP host driver"
- depends on USB_IP_COMMON
+config USBIP_HOST
+ tristate "Host driver"
+ depends on USBIP_CORE
default N
---help---
- This enables the USB IP device driver which will run on the
- host machine.
+ This enables the USB/IP host driver, which is run on the
+ machine that is sharing the USB devices.
- To compile this driver as a module, choose M here: the
- module will be called usbip.
+ To compile this driver as a module, choose M here: the
+ module will be called usbip-host.
-config USB_IP_DEBUG_ENABLE
- bool "USB-IP Debug Enable"
- depends on USB_IP_COMMON
+config USBIP_DEBUG
+ bool "Debug messages for USB/IP"
+ depends on USBIP_CORE
default N
---help---
- This enables the debug messages from the USB-IP drivers.
+ This enables the debug messages from the USB/IP drivers.
diff --git a/drivers/staging/usbip/Makefile b/drivers/staging/usbip/Makefile
index 279f3cc..9ecd615 100644
--- a/drivers/staging/usbip/Makefile
+++ b/drivers/staging/usbip/Makefile
@@ -1,11 +1,10 @@
-obj-$(CONFIG_USB_IP_COMMON) += usbip_common_mod.o
-usbip_common_mod-y := usbip_common.o usbip_event.o
+ccflags-$(CONFIG_USBIP_DEBUG) := -DDEBUG
-obj-$(CONFIG_USB_IP_VHCI_HCD) += vhci-hcd.o
+obj-$(CONFIG_USBIP_CORE) += usbip-core.o
+usbip-core-y := usbip_common.o usbip_event.o
+
+obj-$(CONFIG_USBIP_VHCI_HCD) += vhci-hcd.o
vhci-hcd-y := vhci_sysfs.o vhci_tx.o vhci_rx.o vhci_hcd.o
-obj-$(CONFIG_USB_IP_HOST) += usbip.o
-usbip-y := stub_dev.o stub_main.o stub_rx.o stub_tx.o
-
-ccflags-$(CONFIG_USB_IP_DEBUG_ENABLE) := -DDEBUG
-
+obj-$(CONFIG_USBIP_HOST) += usbip-host.o
+usbip-host-y := stub_dev.o stub_main.o stub_rx.o stub_tx.o
diff --git a/drivers/staging/usbip/stub.h b/drivers/staging/usbip/stub.h
index 6004fcd..6592aa2 100644
--- a/drivers/staging/usbip/stub.h
+++ b/drivers/staging/usbip/stub.h
@@ -17,13 +17,12 @@
* USA.
*/
-#include <linux/kernel.h>
#include <linux/list.h>
-#include <linux/spinlock.h>
#include <linux/slab.h>
-#include <linux/string.h>
-#include <linux/module.h>
-#include <linux/net.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
+#include <linux/usb.h>
+#include <linux/wait.h>
#define STUB_BUSID_OTHER 0
#define STUB_BUSID_REMOV 1
@@ -58,7 +57,6 @@
struct list_head unlink_tx;
struct list_head unlink_free;
-
wait_queue_head_t tx_waitq;
};
@@ -87,25 +85,22 @@
char shutdown_busid;
};
+/* stub_priv is allocated from stub_priv_cache */
extern struct kmem_cache *stub_priv_cache;
-
-/*-------------------------------------------------------------------------*/
-/* prototype declarations */
-
-/* stub_tx.c */
-void stub_complete(struct urb *);
-int stub_tx_loop(void *data);
-
/* stub_dev.c */
extern struct usb_driver stub_driver;
-/* stub_rx.c */
-int stub_rx_loop(void *data);
-void stub_enqueue_ret_unlink(struct stub_device *, __u32, __u32);
-
/* stub_main.c */
struct bus_id_priv *get_busid_priv(const char *busid);
int del_match_busid(char *busid);
-
void stub_device_cleanup_urbs(struct stub_device *sdev);
+
+/* stub_rx.c */
+int stub_rx_loop(void *data);
+
+/* stub_tx.c */
+void stub_enqueue_ret_unlink(struct stub_device *sdev, __u32 seqnum,
+ __u32 status);
+void stub_complete(struct urb *urb);
+int stub_tx_loop(void *data);
diff --git a/drivers/staging/usbip/stub_dev.c b/drivers/staging/usbip/stub_dev.c
index bce7d03..6e99ec8 100644
--- a/drivers/staging/usbip/stub_dev.c
+++ b/drivers/staging/usbip/stub_dev.c
@@ -17,19 +17,16 @@
* USA.
*/
-#include <linux/slab.h>
+#include <linux/device.h>
#include <linux/kthread.h>
#include "usbip_common.h"
#include "stub.h"
-
-
static int stub_probe(struct usb_interface *interface,
- const struct usb_device_id *id);
+ const struct usb_device_id *id);
static void stub_disconnect(struct usb_interface *interface);
-
/*
* Define device IDs here if you want to explicitly limit exportable devices.
* In the most cases, wild card matching will be ok because driver binding can
@@ -64,12 +61,6 @@
.id_table = stub_table,
};
-
-/*-------------------------------------------------------------------------*/
-
-/* Define sysfs entries for a usbip-bound device */
-
-
/*
* usbip_status shows status of usbip as long as this driver is bound to the
* target device.
@@ -128,13 +119,11 @@
spin_unlock(&sdev->ud.lock);
return -EINVAL;
}
-
#if 0
setnodelay(socket);
setkeepalive(socket);
setreuse(socket);
#endif
-
sdev->ud.tcp_socket = socket;
spin_unlock(&sdev->ud.lock);
@@ -183,10 +172,8 @@
err_debug:
device_remove_file(dev, &dev_attr_usbip_sockfd);
-
err_sockfd:
device_remove_file(dev, &dev_attr_usbip_status);
-
err_status:
return err;
}
@@ -198,12 +185,6 @@
device_remove_file(dev, &dev_attr_usbip_debug);
}
-
-
-/*-------------------------------------------------------------------------*/
-
-/* Event handler functions called by an event handler thread */
-
static void stub_shutdown_connection(struct usbip_device *ud)
{
struct stub_device *sdev = container_of(ud, struct stub_device, ud);
@@ -215,7 +196,8 @@
* step 1?
*/
if (ud->tcp_socket) {
- usbip_udbg("shutdown tcp_socket %p\n", ud->tcp_socket);
+ dev_dbg(&sdev->udev->dev, "shutdown tcp_socket %p\n",
+ ud->tcp_socket);
kernel_sock_shutdown(ud->tcp_socket, SHUT_RDWR);
}
@@ -244,18 +226,15 @@
struct stub_unlink *unlink, *tmp;
spin_lock_irqsave(&sdev->priv_lock, flags);
-
list_for_each_entry_safe(unlink, tmp, &sdev->unlink_tx, list) {
list_del(&unlink->list);
kfree(unlink);
}
-
list_for_each_entry_safe(unlink, tmp,
&sdev->unlink_free, list) {
list_del(&unlink->list);
kfree(unlink);
}
-
spin_unlock_irqrestore(&sdev->priv_lock, flags);
}
}
@@ -266,16 +245,14 @@
struct usb_device *udev = sdev->udev;
int ret;
- usbip_udbg("device reset");
+ dev_dbg(&udev->dev, "device reset");
ret = usb_lock_device_for_reset(udev, sdev->interface);
if (ret < 0) {
dev_err(&udev->dev, "lock for reset\n");
-
spin_lock(&ud->lock);
ud->status = SDEV_ST_ERROR;
spin_unlock(&ud->lock);
-
return;
}
@@ -306,9 +283,6 @@
spin_unlock(&ud->lock);
}
-
-/*-------------------------------------------------------------------------*/
-
/**
* stub_device_alloc - allocate a new stub_device struct
* @interface: usb_interface of a new device
@@ -339,13 +313,12 @@
* devnum may change later if a device is reset. However, devid never
* changes during a usbip connection.
*/
- sdev->devid = (busnum << 16) | devnum;
-
- sdev->ud.side = USBIP_STUB;
- sdev->ud.status = SDEV_ST_AVAILABLE;
+ sdev->devid = (busnum << 16) | devnum;
+ sdev->ud.side = USBIP_STUB;
+ sdev->ud.status = SDEV_ST_AVAILABLE;
/* sdev->ud.lock = SPIN_LOCK_UNLOCKED; */
spin_lock_init(&sdev->ud.lock);
- sdev->ud.tcp_socket = NULL;
+ sdev->ud.tcp_socket = NULL;
INIT_LIST_HEAD(&sdev->priv_init);
INIT_LIST_HEAD(&sdev->priv_tx);
@@ -363,7 +336,8 @@
usbip_start_eh(&sdev->ud);
- usbip_udbg("register new interface\n");
+ dev_dbg(&interface->dev, "register new interface\n");
+
return sdev;
}
@@ -373,14 +347,11 @@
return -EINVAL;
kfree(sdev);
- usbip_udbg("kfree udev ok\n");
+ pr_debug("kfree udev ok\n");
return 0;
}
-
-/*-------------------------------------------------------------------------*/
-
/*
* If a usb device has multiple active interfaces, this driver is bound to all
* the active interfaces. However, usbip exports *a* usb device (i.e., not *an*
@@ -405,10 +376,9 @@
/* check we should claim or not by busid_table */
busid_priv = get_busid_priv(udev_busid);
if (!busid_priv || (busid_priv->status == STUB_BUSID_REMOV) ||
- (busid_priv->status == STUB_BUSID_OTHER)) {
- dev_info(&interface->dev,
- "this device %s is not in match_busid table. skip!\n",
- udev_busid);
+ (busid_priv->status == STUB_BUSID_OTHER)) {
+ dev_info(&interface->dev, "%s is not in match_busid table... "
+ "skip!\n", udev_busid);
/*
* Return value should be ENODEV or ENOXIO to continue trying
@@ -418,36 +388,35 @@
return -ENODEV;
}
- if (udev->descriptor.bDeviceClass == USB_CLASS_HUB) {
- usbip_udbg("this device %s is a usb hub device. skip!\n",
- udev_busid);
+ if (udev->descriptor.bDeviceClass == USB_CLASS_HUB) {
+ dev_dbg(&udev->dev, "%s is a usb hub device... skip!\n",
+ udev_busid);
return -ENODEV;
}
if (!strcmp(udev->bus->bus_name, "vhci_hcd")) {
- usbip_udbg("this device %s is attached on vhci_hcd. skip!\n",
- udev_busid);
+ dev_dbg(&udev->dev, "%s is attached on vhci_hcd... skip!\n",
+ udev_busid);
return -ENODEV;
}
-
if (busid_priv->status == STUB_BUSID_ALLOC) {
sdev = busid_priv->sdev;
if (!sdev)
return -ENODEV;
busid_priv->interf_count++;
- dev_info(&interface->dev,
- "USB/IP Stub: register a new interface "
- "(bus %u dev %u ifn %u)\n", udev->bus->busnum, udev->devnum,
- interface->cur_altsetting->desc.bInterfaceNumber);
+ dev_info(&interface->dev, "usbip-host: register new interface "
+ "(bus %u dev %u ifn %u)\n",
+ udev->bus->busnum, udev->devnum,
+ interface->cur_altsetting->desc.bInterfaceNumber);
/* set private data to usb_interface */
usb_set_intfdata(interface, sdev);
err = stub_add_files(&interface->dev);
if (err) {
- dev_err(&interface->dev, "create sysfs files for %s\n",
+ dev_err(&interface->dev, "stub_add_files for %s\n",
udev_busid);
usb_set_intfdata(interface, NULL);
busid_priv->interf_count--;
@@ -464,7 +433,7 @@
if (!sdev)
return -ENOMEM;
- dev_info(&interface->dev, "USB/IP Stub: register a new device "
+ dev_info(&interface->dev, "usbip-host: register new device "
"(bus %u dev %u ifn %u)\n", udev->bus->busnum, udev->devnum,
interface->cur_altsetting->desc.bInterfaceNumber);
@@ -479,8 +448,7 @@
err = stub_add_files(&interface->dev);
if (err) {
- dev_err(&interface->dev, "create sysfs files for %s\n",
- udev_busid);
+ dev_err(&interface->dev, "stub_add_files for %s\n", udev_busid);
usb_set_intfdata(interface, NULL);
usb_put_intf(interface);
@@ -504,10 +472,8 @@
/* 2. wait for the stop of the event handler */
usbip_stop_eh(&busid_priv->sdev->ud);
}
-
}
-
/*
* called in usb_disconnect() or usb_deregister()
* but only if actconfig(active configuration) exists
@@ -518,10 +484,9 @@
const char *udev_busid = dev_name(interface->dev.parent);
struct bus_id_priv *busid_priv;
+ dev_dbg(&interface->dev, "Enter\n");
+
busid_priv = get_busid_priv(udev_busid);
-
- usbip_udbg("Enter\n");
-
if (!busid_priv) {
BUG();
return;
@@ -531,7 +496,7 @@
/* get stub_device */
if (!sdev) {
- err(" could not get device from inteface data");
+ dev_err(&interface->dev, "could not get device");
/* BUG(); */
return;
}
@@ -559,7 +524,6 @@
busid_priv->interf_count = 0;
-
/* 1. shutdown the current connection */
shutdown_busid(busid_priv);
@@ -576,5 +540,4 @@
busid_priv->status = STUB_BUSID_OTHER;
del_match_busid((char *)udev_busid);
}
- usbip_udbg("bye\n");
}
diff --git a/drivers/staging/usbip/stub_main.c b/drivers/staging/usbip/stub_main.c
index 076a7e5..e9085d6 100644
--- a/drivers/staging/usbip/stub_main.c
+++ b/drivers/staging/usbip/stub_main.c
@@ -17,24 +17,17 @@
* USA.
*/
-#include <linux/slab.h>
+#include <linux/string.h>
#include "usbip_common.h"
#include "stub.h"
-/* Version Information */
-#define DRIVER_VERSION "1.0"
#define DRIVER_AUTHOR "Takahiro Hirofuchi"
-#define DRIVER_DESC "Stub Driver for USB/IP"
+#define DRIVER_DESC "USB/IP Host Driver"
/* stub_priv is allocated from stub_priv_cache */
struct kmem_cache *stub_priv_cache;
-/*-------------------------------------------------------------------------*/
-
-/* Define sysfs entries for the usbip driver */
-
-
/*
* busid_tables defines matching busids that usbip can grab. A user can change
* dynamically what device is locally used and what device is exported to a
@@ -44,7 +37,6 @@
static struct bus_id_priv busid_table[MAX_BUSID];
static spinlock_t busid_table_lock;
-
int match_busid(const char *busid)
{
int i;
@@ -148,11 +140,11 @@
return -1;
}
+
static void init_busid_table(void)
{
int i;
-
for (i = 0; i < MAX_BUSID; i++) {
memset(busid_table[i].name, 0, BUSID_SIZE);
busid_table[i].status = STUB_BUSID_OTHER;
@@ -160,11 +152,12 @@
busid_table[i].sdev = NULL;
busid_table[i].shutdown_busid = 0;
}
+
spin_lock_init(&busid_table_lock);
}
static ssize_t store_match_busid(struct device_driver *dev, const char *buf,
- size_t count)
+ size_t count)
{
int len;
char busid[BUSID_SIZE];
@@ -181,33 +174,25 @@
strncpy(busid, buf + 4, BUSID_SIZE);
-
if (!strncmp(buf, "add ", 4)) {
if (add_match_busid(busid) < 0)
return -ENOMEM;
else {
- usbip_udbg("add busid %s\n", busid);
+ pr_debug("add busid %s\n", busid);
return count;
}
} else if (!strncmp(buf, "del ", 4)) {
if (del_match_busid(busid) < 0)
return -ENODEV;
else {
- usbip_udbg("del busid %s\n", busid);
+ pr_debug("del busid %s\n", busid);
return count;
}
} else
return -EINVAL;
}
-
static DRIVER_ATTR(match_busid, S_IRUSR|S_IWUSR, show_match_busid,
- store_match_busid);
-
-
-
-/*-------------------------------------------------------------------------*/
-
-/* Cleanup functions used to free private data */
+ store_match_busid);
static struct stub_priv *stub_priv_pop_from_listhead(struct list_head *listhead)
{
@@ -254,27 +239,23 @@
{
struct stub_priv *priv;
- usbip_udbg("free sdev %p\n", sdev);
+ dev_dbg(&sdev->udev->dev, "free sdev %p\n", sdev);
while ((priv = stub_priv_pop(sdev))) {
struct urb *urb = priv->urb;
- usbip_udbg(" free urb %p\n", urb);
+ dev_dbg(&sdev->udev->dev, "free urb %p\n", urb);
usb_kill_urb(urb);
kmem_cache_free(stub_priv_cache, priv);
kfree(urb->transfer_buffer);
-
kfree(urb->setup_packet);
usb_free_urb(urb);
}
}
-
-/*-------------------------------------------------------------------------*/
-
static int __init usb_stub_init(void)
{
int ret;
@@ -284,20 +265,17 @@
SLAB_HWCACHE_ALIGN, NULL);
if (!stub_priv_cache) {
- printk(KERN_ERR KBUILD_MODNAME
- ": create stub_priv_cache error\n");
+ pr_err("create stub_priv_cache error\n");
return -ENOMEM;
}
ret = usb_register(&stub_driver);
if (ret) {
- printk(KERN_ERR KBUILD_MODNAME ": usb_register failed %d\n",
- ret);
+ pr_err("usb_register failed %d\n", ret);
goto error_usb_register;
}
- printk(KERN_INFO KBUILD_MODNAME ":"
- DRIVER_DESC ":" DRIVER_VERSION "\n");
+ pr_info(DRIVER_DESC " " USBIP_VERSION "\n");
init_busid_table();
@@ -305,7 +283,7 @@
&driver_attr_match_busid);
if (ret) {
- printk(KERN_ERR KBUILD_MODNAME ": create driver sysfs\n");
+ pr_err("create driver sysfs\n");
goto error_create_file;
}
@@ -337,3 +315,4 @@
MODULE_AUTHOR(DRIVER_AUTHOR);
MODULE_DESCRIPTION(DRIVER_DESC);
MODULE_LICENSE("GPL");
+MODULE_VERSION(USBIP_VERSION);
diff --git a/drivers/staging/usbip/stub_rx.c b/drivers/staging/usbip/stub_rx.c
index 51fbd09..a5c1fa1 100644
--- a/drivers/staging/usbip/stub_rx.c
+++ b/drivers/staging/usbip/stub_rx.c
@@ -17,13 +17,13 @@
* USA.
*/
-#include <linux/slab.h>
+#include <asm/byteorder.h>
#include <linux/kthread.h>
+#include <linux/usb.h>
+#include <linux/usb/hcd.h>
#include "usbip_common.h"
#include "stub.h"
-#include <linux/usb/hcd.h>
-
static int is_clear_halt_cmd(struct urb *urb)
{
@@ -43,7 +43,7 @@
req = (struct usb_ctrlrequest *) urb->setup_packet;
return (req->bRequest == USB_REQ_SET_INTERFACE) &&
- (req->bRequestType == USB_RECIP_INTERFACE);
+ (req->bRequestType == USB_RECIP_INTERFACE);
}
static int is_set_configuration_cmd(struct urb *urb)
@@ -53,7 +53,7 @@
req = (struct usb_ctrlrequest *) urb->setup_packet;
return (req->bRequest == USB_REQ_SET_CONFIGURATION) &&
- (req->bRequestType == USB_RECIP_DEVICE);
+ (req->bRequestType == USB_RECIP_DEVICE);
}
static int is_reset_device_cmd(struct urb *urb)
@@ -67,8 +67,8 @@
index = le16_to_cpu(req->wIndex);
if ((req->bRequest == USB_REQ_SET_FEATURE) &&
- (req->bRequestType == USB_RT_PORT) &&
- (value == USB_PORT_FEAT_RESET)) {
+ (req->bRequestType == USB_RT_PORT) &&
+ (value == USB_PORT_FEAT_RESET)) {
usbip_dbg_stub_rx("reset_device_cmd, port %u\n", index);
return 1;
} else
@@ -102,11 +102,11 @@
ret = usb_clear_halt(urb->dev, target_pipe);
if (ret < 0)
- usbip_uinfo("clear_halt error: devnum %d endp %d, %d\n",
- urb->dev->devnum, target_endp, ret);
+ dev_err(&urb->dev->dev, "usb_clear_halt error: devnum %d endp "
+ "%d ret %d\n", urb->dev->devnum, target_endp, ret);
else
- usbip_uinfo("clear_halt done: devnum %d endp %d\n",
- urb->dev->devnum, target_endp);
+ dev_info(&urb->dev->dev, "usb_clear_halt done: devnum %d endp "
+ "%d\n", urb->dev->devnum, target_endp);
return ret;
}
@@ -122,17 +122,16 @@
alternate = le16_to_cpu(req->wValue);
interface = le16_to_cpu(req->wIndex);
- usbip_dbg_stub_rx("set_interface: inf %u alt %u\n", interface,
- alternate);
+ usbip_dbg_stub_rx("set_interface: inf %u alt %u\n",
+ interface, alternate);
ret = usb_set_interface(urb->dev, interface, alternate);
if (ret < 0)
- usbip_uinfo("set_interface error: inf %u alt %u, %d\n",
- interface, alternate, ret);
+ dev_err(&urb->dev->dev, "usb_set_interface error: inf %u alt "
+ "%u ret %d\n", interface, alternate, ret);
else
- usbip_uinfo("set_interface done: inf %u alt %u\n",
- interface,
- alternate);
+ dev_info(&urb->dev->dev, "usb_set_interface done: inf %u alt "
+ "%u\n", interface, alternate);
return ret;
}
@@ -161,9 +160,8 @@
* A user may need to set a special configuration value before
* exporting the device.
*/
- usbip_uinfo("set_configuration (%d) to %s\n", config,
- dev_name(&urb->dev->dev));
- usbip_uinfo("but, skip!\n");
+ dev_info(&urb->dev->dev, "usb_set_configuration %d to %s... skip!\n",
+ config, dev_name(&urb->dev->dev));
return 0;
/* return usb_driver_set_configuration(urb->dev, config); */
@@ -174,7 +172,7 @@
struct stub_priv *priv = (struct stub_priv *) urb->context;
struct stub_device *sdev = priv->sdev;
- usbip_uinfo("reset_device %s\n", dev_name(&urb->dev->dev));
+ dev_info(&urb->dev->dev, "usb_queue_reset_device\n");
/*
* usb_lock_device_for_reset caused a deadlock: it causes the driver
@@ -228,13 +226,12 @@
* See also comments about unlinking strategy in vhci_hcd.c.
*/
static int stub_recv_cmd_unlink(struct stub_device *sdev,
- struct usbip_header *pdu)
+ struct usbip_header *pdu)
{
unsigned long flags;
struct stub_priv *priv;
-
spin_lock_irqsave(&sdev->priv_lock, flags);
list_for_each_entry(priv, &sdev->priv_init, list) {
@@ -289,7 +286,7 @@
}
usbip_dbg_stub_rx("seqnum %d is not pending\n",
- pdu->u.cmd_unlink.seqnum);
+ pdu->u.cmd_unlink.seqnum);
/*
* The urb of the unlink target is not found in priv_init queue. It was
@@ -301,7 +298,6 @@
spin_unlock_irqrestore(&sdev->priv_lock, flags);
-
return 0;
}
@@ -370,8 +366,6 @@
}
epd = &ep->desc;
-
-
#if 0
/* epnum 0 is always control */
if (epnum == 0) {
@@ -381,7 +375,6 @@
return usb_rcvctrlpipe(udev, 0);
}
#endif
-
if (usb_endpoint_xfer_control(epd)) {
if (dir == USBIP_DIR_OUT)
return usb_sndctrlpipe(udev, epnum);
@@ -430,19 +423,19 @@
return;
ep = (usb_pipein(urb->pipe) ? dev->ep_in : dev->ep_out)
- [usb_pipeendpoint(urb->pipe)];
+ [usb_pipeendpoint(urb->pipe)];
if (!ep)
return;
xfertype = usb_endpoint_type(&ep->desc);
if (xfertype == USB_ENDPOINT_XFER_CONTROL) {
struct usb_ctrlrequest *setup =
- (struct usb_ctrlrequest *) urb->setup_packet;
+ (struct usb_ctrlrequest *) urb->setup_packet;
if (!setup)
return;
is_out = !(setup->bRequestType & USB_DIR_IN) ||
- !setup->wLength;
+ !setup->wLength;
} else {
is_out = usb_endpoint_dir_out(&ep->desc);
}
@@ -478,7 +471,6 @@
struct usb_device *udev = sdev->udev;
int pipe = get_pipe(sdev, pdu->base.ep, pdu->base.direction);
-
priv = stub_priv_alloc(sdev, pdu);
if (!priv)
return;
@@ -486,7 +478,7 @@
/* setup a urb */
if (usb_pipeisoc(pipe))
priv->urb = usb_alloc_urb(pdu->u.cmd_submit.number_of_packets,
- GFP_KERNEL);
+ GFP_KERNEL);
else
priv->urb = usb_alloc_urb(0, GFP_KERNEL);
@@ -500,7 +492,7 @@
if (pdu->u.cmd_submit.transfer_buffer_length > 0) {
priv->urb->transfer_buffer =
kzalloc(pdu->u.cmd_submit.transfer_buffer_length,
- GFP_KERNEL);
+ GFP_KERNEL);
if (!priv->urb->transfer_buffer) {
dev_err(&sdev->interface->dev, "malloc x_buff\n");
usbip_event_add(ud, SDEV_EVENT_ERROR_MALLOC);
@@ -541,7 +533,7 @@
if (ret == 0)
usbip_dbg_stub_rx("submit urb ok, seqnum %u\n",
- pdu->base.seqnum);
+ pdu->base.seqnum);
else {
dev_err(&sdev->interface->dev, "submit_urb error, %d\n", ret);
usbip_dump_header(pdu);
@@ -602,9 +594,8 @@
/* NOTREACHED */
dev_err(dev, "unknown pdu\n");
usbip_event_add(ud, SDEV_EVENT_ERROR_TCP);
- return;
+ break;
}
-
}
int stub_rx_loop(void *data)
@@ -617,5 +608,6 @@
stub_rx_pdu(ud);
}
+
return 0;
}
diff --git a/drivers/staging/usbip/stub_tx.c b/drivers/staging/usbip/stub_tx.c
index 64a52b2..fda2bc9 100644
--- a/drivers/staging/usbip/stub_tx.c
+++ b/drivers/staging/usbip/stub_tx.c
@@ -17,13 +17,12 @@
* USA.
*/
-#include <linux/slab.h>
#include <linux/kthread.h>
+#include <linux/socket.h>
#include "usbip_common.h"
#include "stub.h"
-
static void stub_free_priv_and_urb(struct stub_priv *priv)
{
struct urb *urb = priv->urb;
@@ -71,28 +70,29 @@
usbip_dbg_stub_tx("complete! status %d\n", urb->status);
-
switch (urb->status) {
case 0:
/* OK */
break;
case -ENOENT:
- usbip_uinfo("stopped by a call of usb_kill_urb() because of"
- "cleaning up a virtual connection\n");
+ dev_info(&urb->dev->dev, "stopped by a call to usb_kill_urb() "
+ "because of cleaning up a virtual connection\n");
return;
case -ECONNRESET:
- usbip_uinfo("unlinked by a call of usb_unlink_urb()\n");
+ dev_info(&urb->dev->dev, "unlinked by a call to "
+ "usb_unlink_urb()\n");
break;
case -EPIPE:
- usbip_uinfo("endpoint %d is stalled\n",
- usb_pipeendpoint(urb->pipe));
+ dev_info(&urb->dev->dev, "endpoint %d is stalled\n",
+ usb_pipeendpoint(urb->pipe));
break;
case -ESHUTDOWN:
- usbip_uinfo("device removed?\n");
+ dev_info(&urb->dev->dev, "device removed?\n");
break;
default:
- usbip_uinfo("urb completion with non-zero status %d\n",
- urb->status);
+ dev_info(&urb->dev->dev, "urb completion with non-zero status "
+ "%d\n", urb->status);
+ break;
}
/* link a urb to the queue of tx. */
@@ -104,25 +104,20 @@
} else
list_move_tail(&priv->list, &sdev->priv_tx);
-
spin_unlock_irqrestore(&sdev->priv_lock, flags);
/* wake up tx_thread */
wake_up(&sdev->tx_waitq);
}
-
-/*-------------------------------------------------------------------------*/
-/* fill PDU */
-
static inline void setup_base_pdu(struct usbip_header_basic *base,
- __u32 command, __u32 seqnum)
+ __u32 command, __u32 seqnum)
{
base->command = command;
base->seqnum = seqnum;
base->devid = 0;
base->ep = 0;
- base->direction = 0;
+ base->direction = 0;
}
static void setup_ret_submit_pdu(struct usbip_header *rpdu, struct urb *urb)
@@ -130,22 +125,16 @@
struct stub_priv *priv = (struct stub_priv *) urb->context;
setup_base_pdu(&rpdu->base, USBIP_RET_SUBMIT, priv->seqnum);
-
usbip_pack_pdu(rpdu, urb, USBIP_RET_SUBMIT, 1);
}
static void setup_ret_unlink_pdu(struct usbip_header *rpdu,
- struct stub_unlink *unlink)
+ struct stub_unlink *unlink)
{
setup_base_pdu(&rpdu->base, USBIP_RET_UNLINK, unlink->seqnum);
-
rpdu->u.ret_unlink.status = unlink->status;
}
-
-/*-------------------------------------------------------------------------*/
-/* send RET_SUBMIT */
-
static struct stub_priv *dequeue_from_priv_tx(struct stub_device *sdev)
{
unsigned long flags;
@@ -203,7 +192,7 @@
/* 1. setup usbip_header */
setup_ret_submit_pdu(&pdu_header, urb);
usbip_dbg_stub_tx("setup txdata seqnum: %d urb: %p\n",
- pdu_header.base.seqnum, urb);
+ pdu_header.base.seqnum, urb);
/*usbip_dump_header(pdu_header);*/
usbip_header_correct_endian(&pdu_header, 1);
@@ -214,14 +203,14 @@
/* 2. setup transfer buffer */
if (usb_pipein(urb->pipe) &&
- usb_pipetype(urb->pipe) != PIPE_ISOCHRONOUS &&
- urb->actual_length > 0) {
+ usb_pipetype(urb->pipe) != PIPE_ISOCHRONOUS &&
+ urb->actual_length > 0) {
iov[iovnum].iov_base = urb->transfer_buffer;
iov[iovnum].iov_len = urb->actual_length;
iovnum++;
txsize += urb->actual_length;
} else if (usb_pipein(urb->pipe) &&
- usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
+ usb_pipetype(urb->pipe) == PIPE_ISOCHRONOUS) {
/*
* For isochronous packets: actual length is the sum of
* the actual length of the individual, packets, but as
@@ -232,18 +221,23 @@
int i;
for (i = 0; i < urb->number_of_packets; i++) {
- iov[iovnum].iov_base = urb->transfer_buffer + urb->iso_frame_desc[i].offset;
- iov[iovnum].iov_len = urb->iso_frame_desc[i].actual_length;
+ iov[iovnum].iov_base = urb->transfer_buffer +
+ urb->iso_frame_desc[i].offset;
+ iov[iovnum].iov_len =
+ urb->iso_frame_desc[i].actual_length;
iovnum++;
txsize += urb->iso_frame_desc[i].actual_length;
}
if (txsize != sizeof(pdu_header) + urb->actual_length) {
dev_err(&sdev->interface->dev,
- "actual length of urb (%d) does not match iso packet sizes (%d)\n",
- urb->actual_length, txsize-sizeof(pdu_header));
+ "actual length of urb %d does not "
+ "match iso packet sizes %lu\n",
+ urb->actual_length,
+ txsize-sizeof(pdu_header));
kfree(iov);
- usbip_event_add(&sdev->ud, SDEV_EVENT_ERROR_TCP);
+ usbip_event_add(&sdev->ud,
+ SDEV_EVENT_ERROR_TCP);
return -1;
}
}
@@ -285,20 +279,14 @@
}
spin_lock_irqsave(&sdev->priv_lock, flags);
-
list_for_each_entry_safe(priv, tmp, &sdev->priv_free, list) {
stub_free_priv_and_urb(priv);
}
-
spin_unlock_irqrestore(&sdev->priv_lock, flags);
return total_size;
}
-
-/*-------------------------------------------------------------------------*/
-/* send RET_UNLINK */
-
static struct stub_unlink *dequeue_from_unlink_tx(struct stub_device *sdev)
{
unsigned long flags;
@@ -317,7 +305,6 @@
return NULL;
}
-
static int stub_send_ret_unlink(struct stub_device *sdev)
{
unsigned long flags;
@@ -358,13 +345,10 @@
return -1;
}
-
usbip_dbg_stub_tx("send txdata\n");
-
total_size += txsize;
}
-
spin_lock_irqsave(&sdev->priv_lock, flags);
list_for_each_entry_safe(unlink, tmp, &sdev->unlink_free, list) {
@@ -377,9 +361,6 @@
return total_size;
}
-
-/*-------------------------------------------------------------------------*/
-
int stub_tx_loop(void *data)
{
struct usbip_device *ud = data;
@@ -410,9 +391,9 @@
break;
wait_event_interruptible(sdev->tx_waitq,
- (!list_empty(&sdev->priv_tx) ||
- !list_empty(&sdev->unlink_tx) ||
- kthread_should_stop()));
+ (!list_empty(&sdev->priv_tx) ||
+ !list_empty(&sdev->unlink_tx) ||
+ kthread_should_stop()));
}
return 0;
diff --git a/drivers/staging/usbip/usbip_common.c b/drivers/staging/usbip/usbip_common.c
index 7b1fe45..433a3b6 100644
--- a/drivers/staging/usbip/usbip_common.c
+++ b/drivers/staging/usbip/usbip_common.c
@@ -17,53 +17,46 @@
* USA.
*/
-#include <linux/kernel.h>
+#include <asm/byteorder.h>
#include <linux/file.h>
-#include <linux/tcp.h>
-#include <linux/in.h>
-#include <linux/kthread.h>
+#include <linux/fs.h>
+#include <linux/kernel.h>
#include <linux/slab.h>
+#include <net/sock.h>
+
#include "usbip_common.h"
-/* version information */
-#define DRIVER_VERSION "1.0"
-#define DRIVER_AUTHOR "Takahiro Hirofuchi <hirofuchi _at_ users.sourceforge.net>"
-#define DRIVER_DESC "usbip common driver"
+#define DRIVER_AUTHOR "Takahiro Hirofuchi <hirofuchi@users.sourceforge.net>"
+#define DRIVER_DESC "USB/IP Core"
-/*-------------------------------------------------------------------------*/
-/* debug routines */
-
-#ifdef CONFIG_USB_IP_DEBUG_ENABLE
+#ifdef CONFIG_USBIP_DEBUG
unsigned long usbip_debug_flag = 0xffffffff;
#else
unsigned long usbip_debug_flag;
#endif
EXPORT_SYMBOL_GPL(usbip_debug_flag);
-
/* FIXME */
struct device_attribute dev_attr_usbip_debug;
EXPORT_SYMBOL_GPL(dev_attr_usbip_debug);
-
static ssize_t show_flag(struct device *dev, struct device_attribute *attr,
- char *buf)
+ char *buf)
{
return sprintf(buf, "%lx\n", usbip_debug_flag);
}
static ssize_t store_flag(struct device *dev, struct device_attribute *attr,
- const char *buf, size_t count)
+ const char *buf, size_t count)
{
sscanf(buf, "%lx", &usbip_debug_flag);
-
return count;
}
DEVICE_ATTR(usbip_debug, (S_IRUGO | S_IWUSR), show_flag, store_flag);
static void usbip_dump_buffer(char *buff, int bufflen)
{
- print_hex_dump(KERN_DEBUG, "usb-ip", DUMP_PREFIX_OFFSET, 16, 4,
+ print_hex_dump(KERN_DEBUG, "usbip-core", DUMP_PREFIX_OFFSET, 16, 4,
buff, bufflen, false);
}
@@ -74,29 +67,25 @@
unsigned char dev = usb_pipedevice(p);
unsigned char dir = usb_pipein(p);
- printk(KERN_DEBUG "dev(%d) ", dev);
- printk(KERN_DEBUG "ep(%d) ", ep);
- printk(KERN_DEBUG "%s ", dir ? "IN" : "OUT");
+ pr_debug("dev(%d) ep(%d) [%s] ", dev, ep, dir ? "IN" : "OUT");
switch (type) {
case PIPE_ISOCHRONOUS:
- printk(KERN_DEBUG "%s ", "ISO");
+ pr_debug("ISO\n");
break;
case PIPE_INTERRUPT:
- printk(KERN_DEBUG "%s ", "INT");
+ pr_debug("INT\n");
break;
case PIPE_CONTROL:
- printk(KERN_DEBUG "%s ", "CTL");
+ pr_debug("CTRL\n");
break;
case PIPE_BULK:
- printk(KERN_DEBUG "%s ", "BLK");
+ pr_debug("BULK\n");
break;
default:
- printk(KERN_DEBUG "ERR");
+ pr_debug("ERR\n");
+ break;
}
-
- printk(KERN_DEBUG "\n");
-
}
static void usbip_dump_usb_device(struct usb_device *udev)
@@ -104,60 +93,59 @@
struct device *dev = &udev->dev;
int i;
- dev_dbg(dev, " devnum(%d) devpath(%s)",
+ dev_dbg(dev, " devnum(%d) devpath(%s) ",
udev->devnum, udev->devpath);
switch (udev->speed) {
case USB_SPEED_HIGH:
- printk(KERN_DEBUG " SPD_HIGH");
+ pr_debug("SPD_HIGH ");
break;
case USB_SPEED_FULL:
- printk(KERN_DEBUG " SPD_FULL");
+ pr_debug("SPD_FULL ");
break;
case USB_SPEED_LOW:
- printk(KERN_DEBUG " SPD_LOW");
+ pr_debug("SPD_LOW ");
break;
case USB_SPEED_UNKNOWN:
- printk(KERN_DEBUG " SPD_UNKNOWN");
+ pr_debug("SPD_UNKNOWN ");
break;
default:
- printk(KERN_DEBUG " SPD_ERROR");
+ pr_debug("SPD_ERROR ");
+ break;
}
- printk(KERN_DEBUG " tt %p, ttport %d", udev->tt, udev->ttport);
- printk(KERN_DEBUG "\n");
+ pr_debug("tt %p, ttport %d\n", udev->tt, udev->ttport);
dev_dbg(dev, " ");
for (i = 0; i < 16; i++)
- printk(KERN_DEBUG " %2u", i);
- printk(KERN_DEBUG "\n");
+ pr_debug(" %2u", i);
+ pr_debug("\n");
dev_dbg(dev, " toggle0(IN) :");
for (i = 0; i < 16; i++)
- printk(KERN_DEBUG " %2u", (udev->toggle[0] & (1 << i)) ? 1 : 0);
- printk(KERN_DEBUG "\n");
+ pr_debug(" %2u", (udev->toggle[0] & (1 << i)) ? 1 : 0);
+ pr_debug("\n");
dev_dbg(dev, " toggle1(OUT):");
for (i = 0; i < 16; i++)
- printk(KERN_DEBUG " %2u", (udev->toggle[1] & (1 << i)) ? 1 : 0);
- printk(KERN_DEBUG "\n");
-
+ pr_debug(" %2u", (udev->toggle[1] & (1 << i)) ? 1 : 0);
+ pr_debug("\n");
dev_dbg(dev, " epmaxp_in :");
for (i = 0; i < 16; i++) {
if (udev->ep_in[i])
- printk(KERN_DEBUG " %2u",
- le16_to_cpu(udev->ep_in[i]->desc.wMaxPacketSize));
+ pr_debug(" %2u",
+ le16_to_cpu(udev->ep_in[i]->desc.wMaxPacketSize));
}
- printk(KERN_DEBUG "\n");
+ pr_debug("\n");
dev_dbg(dev, " epmaxp_out :");
for (i = 0; i < 16; i++) {
if (udev->ep_out[i])
- printk(KERN_DEBUG " %2u",
- le16_to_cpu(udev->ep_out[i]->desc.wMaxPacketSize));
+ pr_debug(" %2u",
+ le16_to_cpu(udev->ep_out[i]->desc.wMaxPacketSize));
}
- printk(KERN_DEBUG "\n");
+ pr_debug("\n");
dev_dbg(dev, "parent %p, bus %p\n", udev->parent, udev->bus);
@@ -176,91 +164,84 @@
{
switch (rt & USB_RECIP_MASK) {
case USB_RECIP_DEVICE:
- printk(KERN_DEBUG "DEVICE");
+ pr_debug("DEVICE");
break;
case USB_RECIP_INTERFACE:
- printk(KERN_DEBUG "INTERF");
+ pr_debug("INTERF");
break;
case USB_RECIP_ENDPOINT:
- printk(KERN_DEBUG "ENDPOI");
+ pr_debug("ENDPOI");
break;
case USB_RECIP_OTHER:
- printk(KERN_DEBUG "OTHER ");
+ pr_debug("OTHER ");
break;
default:
- printk(KERN_DEBUG "------");
+ pr_debug("------");
+ break;
}
}
static void usbip_dump_usb_ctrlrequest(struct usb_ctrlrequest *cmd)
{
if (!cmd) {
- printk(KERN_DEBUG " %s : null pointer\n", __func__);
+ pr_debug(" : null pointer\n");
return;
}
- printk(KERN_DEBUG " ");
- printk(KERN_DEBUG "bRequestType(%02X) ", cmd->bRequestType);
- printk(KERN_DEBUG "bRequest(%02X) " , cmd->bRequest);
- printk(KERN_DEBUG "wValue(%04X) ", cmd->wValue);
- printk(KERN_DEBUG "wIndex(%04X) ", cmd->wIndex);
- printk(KERN_DEBUG "wLength(%04X) ", cmd->wLength);
-
- printk(KERN_DEBUG "\n ");
+ pr_debug(" ");
+ pr_debug("bRequestType(%02X) bRequest(%02X) wValue(%04X) wIndex(%04X) "
+ "wLength(%04X) ", cmd->bRequestType, cmd->bRequest,
+ cmd->wValue, cmd->wIndex, cmd->wLength);
+ pr_debug("\n ");
if ((cmd->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
- printk(KERN_DEBUG "STANDARD ");
+ pr_debug("STANDARD ");
switch (cmd->bRequest) {
case USB_REQ_GET_STATUS:
- printk(KERN_DEBUG "GET_STATUS");
+ pr_debug("GET_STATUS\n");
break;
case USB_REQ_CLEAR_FEATURE:
- printk(KERN_DEBUG "CLEAR_FEAT");
+ pr_debug("CLEAR_FEAT\n");
break;
case USB_REQ_SET_FEATURE:
- printk(KERN_DEBUG "SET_FEAT ");
+ pr_debug("SET_FEAT \n");
break;
case USB_REQ_SET_ADDRESS:
- printk(KERN_DEBUG "SET_ADDRRS");
+ pr_debug("SET_ADDRRS\n");
break;
case USB_REQ_GET_DESCRIPTOR:
- printk(KERN_DEBUG "GET_DESCRI");
+ pr_debug("GET_DESCRI\n");
break;
case USB_REQ_SET_DESCRIPTOR:
- printk(KERN_DEBUG "SET_DESCRI");
+ pr_debug("SET_DESCRI\n");
break;
case USB_REQ_GET_CONFIGURATION:
- printk(KERN_DEBUG "GET_CONFIG");
+ pr_debug("GET_CONFIG\n");
break;
case USB_REQ_SET_CONFIGURATION:
- printk(KERN_DEBUG "SET_CONFIG");
+ pr_debug("SET_CONFIG\n");
break;
case USB_REQ_GET_INTERFACE:
- printk(KERN_DEBUG "GET_INTERF");
+ pr_debug("GET_INTERF\n");
break;
case USB_REQ_SET_INTERFACE:
- printk(KERN_DEBUG "SET_INTERF");
+ pr_debug("SET_INTERF\n");
break;
case USB_REQ_SYNCH_FRAME:
- printk(KERN_DEBUG "SYNC_FRAME");
+ pr_debug("SYNC_FRAME\n");
break;
default:
- printk(KERN_DEBUG "REQ(%02X) ", cmd->bRequest);
+ pr_debug("REQ(%02X) \n", cmd->bRequest);
+ break;
}
-
- printk(KERN_DEBUG " ");
usbip_dump_request_type(cmd->bRequestType);
-
- } else if ((cmd->bRequestType & USB_TYPE_MASK) == USB_TYPE_CLASS)
- printk(KERN_DEBUG "CLASS ");
-
- else if ((cmd->bRequestType & USB_TYPE_MASK) == USB_TYPE_VENDOR)
- printk(KERN_DEBUG "VENDOR ");
-
- else if ((cmd->bRequestType & USB_TYPE_MASK) == USB_TYPE_RESERVED)
- printk(KERN_DEBUG "RESERVED");
-
- printk(KERN_DEBUG "\n");
+ } else if ((cmd->bRequestType & USB_TYPE_MASK) == USB_TYPE_CLASS) {
+ pr_debug("CLASS \n");
+ } else if ((cmd->bRequestType & USB_TYPE_MASK) == USB_TYPE_VENDOR) {
+ pr_debug("VENDOR \n");
+ } else if ((cmd->bRequestType & USB_TYPE_MASK) == USB_TYPE_RESERVED) {
+ pr_debug("RESERVED\n");
+ }
}
void usbip_dump_urb(struct urb *urb)
@@ -268,16 +249,15 @@
struct device *dev;
if (!urb) {
- printk(KERN_DEBUG KBUILD_MODNAME
- ":%s: urb: null pointer!!\n", __func__);
+ pr_debug("urb: null pointer!!\n");
return;
}
if (!urb->dev) {
- printk(KERN_DEBUG KBUILD_MODNAME
- ":%s: urb->dev: null pointer!!\n", __func__);
+ pr_debug("urb->dev: null pointer!!\n");
return;
}
+
dev = &urb->dev->dev;
dev_dbg(dev, " urb :%p\n", urb);
@@ -298,7 +278,7 @@
dev_dbg(dev, " setup_packet :%p\n", urb->setup_packet);
if (urb->setup_packet && usb_pipetype(urb->pipe) == PIPE_CONTROL)
- usbip_dump_usb_ctrlrequest(
+ usbip_dump_usb_ctrlrequest(
(struct usb_ctrlrequest *)urb->setup_packet);
dev_dbg(dev, " start_frame :%d\n", urb->start_frame);
@@ -312,47 +292,48 @@
void usbip_dump_header(struct usbip_header *pdu)
{
- usbip_udbg("BASE: cmd %u seq %u devid %u dir %u ep %u\n",
- pdu->base.command,
- pdu->base.seqnum,
- pdu->base.devid,
- pdu->base.direction,
- pdu->base.ep);
+ pr_debug("BASE: cmd %u seq %u devid %u dir %u ep %u\n",
+ pdu->base.command,
+ pdu->base.seqnum,
+ pdu->base.devid,
+ pdu->base.direction,
+ pdu->base.ep);
switch (pdu->base.command) {
case USBIP_CMD_SUBMIT:
- usbip_udbg("CMD_SUBMIT: "
- "x_flags %u x_len %u sf %u #p %u iv %u\n",
- pdu->u.cmd_submit.transfer_flags,
- pdu->u.cmd_submit.transfer_buffer_length,
- pdu->u.cmd_submit.start_frame,
- pdu->u.cmd_submit.number_of_packets,
- pdu->u.cmd_submit.interval);
- break;
+ pr_debug("USBIP_CMD_SUBMIT: "
+ "x_flags %u x_len %u sf %u #p %d iv %d\n",
+ pdu->u.cmd_submit.transfer_flags,
+ pdu->u.cmd_submit.transfer_buffer_length,
+ pdu->u.cmd_submit.start_frame,
+ pdu->u.cmd_submit.number_of_packets,
+ pdu->u.cmd_submit.interval);
+ break;
case USBIP_CMD_UNLINK:
- usbip_udbg("CMD_UNLINK: seq %u\n", pdu->u.cmd_unlink.seqnum);
+ pr_debug("USBIP_CMD_UNLINK: seq %u\n",
+ pdu->u.cmd_unlink.seqnum);
break;
case USBIP_RET_SUBMIT:
- usbip_udbg("RET_SUBMIT: st %d al %u sf %d #p %d ec %d\n",
- pdu->u.ret_submit.status,
- pdu->u.ret_submit.actual_length,
- pdu->u.ret_submit.start_frame,
- pdu->u.ret_submit.number_of_packets,
- pdu->u.ret_submit.error_count);
+ pr_debug("USBIP_RET_SUBMIT: st %d al %u sf %d #p %d ec %d\n",
+ pdu->u.ret_submit.status,
+ pdu->u.ret_submit.actual_length,
+ pdu->u.ret_submit.start_frame,
+ pdu->u.ret_submit.number_of_packets,
+ pdu->u.ret_submit.error_count);
+ break;
case USBIP_RET_UNLINK:
- usbip_udbg("RET_UNLINK: status %d\n", pdu->u.ret_unlink.status);
+ pr_debug("USBIP_RET_UNLINK: status %d\n",
+ pdu->u.ret_unlink.status);
break;
default:
/* NOT REACHED */
- usbip_udbg("UNKNOWN\n");
+ pr_err("unknown command\n");
+ break;
}
}
EXPORT_SYMBOL_GPL(usbip_dump_header);
-/*-------------------------------------------------------------------------*/
-/* socket routines */
-
-/* Send/receive messages over TCP/IP. I refer drivers/block/nbd.c */
+/* Send/receive messages over TCP/IP. I refer drivers/block/nbd.c */
int usbip_xmit(int send, struct socket *sock, char *buf,
int size, int msg_flags)
{
@@ -368,27 +349,24 @@
usbip_dbg_xmit("enter\n");
if (!sock || !buf || !size) {
- printk(KERN_ERR "%s: invalid arg, sock %p buff %p size %d\n",
- __func__, sock, buf, size);
+ pr_err("invalid arg, sock %p buff %p size %d\n", sock, buf,
+ size);
return -EINVAL;
}
-
if (usbip_dbg_flag_xmit) {
if (send) {
if (!in_interrupt())
- printk(KERN_DEBUG "%-10s:", current->comm);
+ pr_debug("%-10s:", current->comm);
else
- printk(KERN_DEBUG "interrupt :");
+ pr_debug("interrupt :");
- printk(KERN_DEBUG "%s: sending... , sock %p, buf %p, "
- "size %d, msg_flags %d\n", __func__,
- sock, buf, size, msg_flags);
+ pr_debug("sending... , sock %p, buf %p, size %d, "
+ "msg_flags %d\n", sock, buf, size, msg_flags);
usbip_dump_buffer(buf, size);
}
}
-
do {
sock->sk->sk_allocation = GFP_NOIO;
iov.iov_base = buf;
@@ -404,13 +382,12 @@
result = kernel_sendmsg(sock, &msg, &iov, 1, size);
else
result = kernel_recvmsg(sock, &msg, &iov, 1, size,
- MSG_WAITALL);
+ MSG_WAITALL);
if (result <= 0) {
- usbip_udbg("usbip_xmit: %s sock %p buf %p size %u ret "
- "%d total %d\n",
- send ? "send" : "receive", sock, buf,
- size, result, total);
+ pr_debug("%s sock %p buf %p size %u ret %d total %d\n",
+ send ? "send" : "receive", sock, buf, size,
+ result, total);
goto err;
}
@@ -420,24 +397,21 @@
} while (size > 0);
-
if (usbip_dbg_flag_xmit) {
if (!send) {
if (!in_interrupt())
- printk(KERN_DEBUG "%-10s:", current->comm);
+ pr_debug("%-10s:", current->comm);
else
- printk(KERN_DEBUG "interrupt :");
+ pr_debug("interrupt :");
- printk(KERN_DEBUG "usbip_xmit: receiving....\n");
+ pr_debug("receiving....\n");
usbip_dump_buffer(bp, osize);
- printk(KERN_DEBUG "usbip_xmit: received, osize %d ret "
- "%d size %d total %d\n", osize, result,
- size, total);
+ pr_debug("received, osize %d ret %d size %d total %d\n",
+ osize, result, size, total);
}
if (send)
- printk(KERN_DEBUG "usbip_xmit: send, total %d\n",
- total);
+ pr_debug("send, total %d\n", total);
}
return total;
@@ -455,7 +429,7 @@
file = fget(sockfd);
if (!file) {
- printk(KERN_ERR "%s: invalid sockfd\n", __func__);
+ pr_err("invalid sockfd\n");
return NULL;
}
@@ -470,11 +444,6 @@
}
EXPORT_SYMBOL_GPL(sockfd_to_socket);
-
-
-/*-------------------------------------------------------------------------*/
-/* pdu routines */
-
/* there may be more cases to tweak the flags. */
static unsigned int tweak_transfer_flags(unsigned int flags)
{
@@ -483,7 +452,7 @@
}
static void usbip_pack_cmd_submit(struct usbip_header *pdu, struct urb *urb,
- int pack)
+ int pack)
{
struct usbip_header_cmd_submit *spdu = &pdu->u.cmd_submit;
@@ -494,7 +463,7 @@
if (pack) {
/* vhci_tx.c */
spdu->transfer_flags =
- tweak_transfer_flags(urb->transfer_flags);
+ tweak_transfer_flags(urb->transfer_flags);
spdu->transfer_buffer_length = urb->transfer_buffer_length;
spdu->start_frame = urb->start_frame;
spdu->number_of_packets = urb->number_of_packets;
@@ -511,7 +480,7 @@
}
static void usbip_pack_ret_submit(struct usbip_header *pdu, struct urb *urb,
- int pack)
+ int pack)
{
struct usbip_header_ret_submit *rpdu = &pdu->u.ret_submit;
@@ -534,9 +503,8 @@
}
}
-
void usbip_pack_pdu(struct usbip_header *pdu, struct urb *urb, int cmd,
- int pack)
+ int pack)
{
switch (cmd) {
case USBIP_CMD_SUBMIT:
@@ -546,14 +514,13 @@
usbip_pack_ret_submit(pdu, urb, pack);
break;
default:
- err("unknown command");
- /* NOTREACHED */
- /* BUG(); */
+ /* NOT REACHED */
+ pr_err("unknown command\n");
+ break;
}
}
EXPORT_SYMBOL_GPL(usbip_pack_pdu);
-
static void correct_endian_basic(struct usbip_header_basic *base, int send)
{
if (send) {
@@ -572,7 +539,7 @@
}
static void correct_endian_cmd_submit(struct usbip_header_cmd_submit *pdu,
- int send)
+ int send)
{
if (send) {
pdu->transfer_flags = cpu_to_be32(pdu->transfer_flags);
@@ -592,7 +559,7 @@
}
static void correct_endian_ret_submit(struct usbip_header_ret_submit *pdu,
- int send)
+ int send)
{
if (send) {
cpu_to_be32s(&pdu->status);
@@ -604,13 +571,13 @@
be32_to_cpus(&pdu->status);
be32_to_cpus(&pdu->actual_length);
be32_to_cpus(&pdu->start_frame);
- cpu_to_be32s(&pdu->number_of_packets);
+ be32_to_cpus(&pdu->number_of_packets);
be32_to_cpus(&pdu->error_count);
}
}
static void correct_endian_cmd_unlink(struct usbip_header_cmd_unlink *pdu,
- int send)
+ int send)
{
if (send)
pdu->seqnum = cpu_to_be32(pdu->seqnum);
@@ -619,7 +586,7 @@
}
static void correct_endian_ret_unlink(struct usbip_header_ret_unlink *pdu,
- int send)
+ int send)
{
if (send)
cpu_to_be32s(&pdu->status);
@@ -653,16 +620,16 @@
correct_endian_ret_unlink(&pdu->u.ret_unlink, send);
break;
default:
- /* NOTREACHED */
- err("unknown command in pdu header: %d", cmd);
- /* BUG(); */
+ /* NOT REACHED */
+ pr_err("unknown command\n");
+ break;
}
}
EXPORT_SYMBOL_GPL(usbip_header_correct_endian);
static void usbip_iso_pakcet_correct_endian(
- struct usbip_iso_packet_descriptor *iso,
- int send)
+ struct usbip_iso_packet_descriptor *iso,
+ int send)
{
/* does not need all members. but copy all simply. */
if (send) {
@@ -679,7 +646,7 @@
}
static void usbip_pack_iso(struct usbip_iso_packet_descriptor *iso,
- struct usb_iso_packet_descriptor *uiso, int pack)
+ struct usb_iso_packet_descriptor *uiso, int pack)
{
if (pack) {
iso->offset = uiso->offset;
@@ -694,7 +661,6 @@
}
}
-
/* must free buffer */
void *usbip_alloc_iso_desc_pdu(struct urb *urb, ssize_t *bufflen)
{
@@ -737,7 +703,7 @@
/* my Bluetooth dongle gets ISO URBs which are np = 0 */
if (np == 0) {
- /* usbip_uinfo("iso np == 0\n"); */
+ /* pr_info("iso np == 0\n"); */
/* usbip_dump_urb(urb); */
return 0;
}
@@ -760,7 +726,6 @@
return -EPIPE;
}
-
for (i = 0; i < np; i++) {
iso = buff + (i * sizeof(*iso));
@@ -773,8 +738,9 @@
if (total_length != urb->actual_length) {
dev_err(&urb->dev->dev,
- "total length of iso packets (%d) not equal to actual length of buffer (%d)\n",
- total_length, urb->actual_length);
+ "total length of iso packets %d not equal to actual "
+ "length of buffer %d\n",
+ total_length, urb->actual_length);
if (ud->side == USBIP_STUB)
usbip_event_add(ud, SDEV_EVENT_ERROR_TCP);
@@ -823,9 +789,10 @@
for (i = np-1; i > 0; i--) {
actualoffset -= urb->iso_frame_desc[i].actual_length;
memmove(urb->transfer_buffer + urb->iso_frame_desc[i].offset,
- urb->transfer_buffer + actualoffset,
- urb->iso_frame_desc[i].actual_length);
+ urb->transfer_buffer + actualoffset,
+ urb->iso_frame_desc[i].actual_length);
}
+
return ret;
}
EXPORT_SYMBOL_GPL(usbip_pad_iso);
@@ -872,13 +839,9 @@
}
EXPORT_SYMBOL_GPL(usbip_recv_xbuff);
-
-/*-------------------------------------------------------------------------*/
-
static int __init usbip_common_init(void)
{
- printk(KERN_INFO KBUILD_MODNAME ": " DRIVER_DESC "" DRIVER_VERSION);
-
+ pr_info(DRIVER_DESC " v" USBIP_VERSION "\n");
return 0;
}
@@ -887,12 +850,10 @@
return;
}
-
-
-
module_init(usbip_common_init);
module_exit(usbip_common_exit);
MODULE_AUTHOR(DRIVER_AUTHOR);
MODULE_DESCRIPTION(DRIVER_DESC);
MODULE_LICENSE("GPL");
+MODULE_VERSION(USBIP_VERSION);
diff --git a/drivers/staging/usbip/usbip_common.h b/drivers/staging/usbip/usbip_common.h
index c767f52..4a641c5 100644
--- a/drivers/staging/usbip/usbip_common.h
+++ b/drivers/staging/usbip/usbip_common.h
@@ -17,42 +17,28 @@
* USA.
*/
-#ifndef __VHCI_COMMON_H
-#define __VHCI_COMMON_H
+#ifndef __USBIP_COMMON_H
+#define __USBIP_COMMON_H
-
-#include <linux/version.h>
+#include <linux/compiler.h>
+#include <linux/device.h>
+#include <linux/interrupt.h>
+#include <linux/net.h>
+#include <linux/printk.h>
+#include <linux/spinlock.h>
+#include <linux/types.h>
#include <linux/usb.h>
-#include <asm/byteorder.h>
-#include <net/sock.h>
+#include <linux/wait.h>
-/*-------------------------------------------------------------------------*/
+#define USBIP_VERSION "1.0.0"
-/*
- * define macros to print messages
- */
+#undef pr_fmt
-/**
- * usbip_udbg - print debug messages if CONFIG_USB_IP_DEBUG_ENABLE is defined
- * @fmt:
- * @args:
- */
-
-#ifdef CONFIG_USB_IP_DEBUG_ENABLE
-
-#define usbip_udbg(fmt, args...) \
- do { \
- printk(KERN_DEBUG "%-10s:(%s,%d) %s: " fmt, \
- (in_interrupt() ? "interrupt" : (current)->comm),\
- __FILE__, __LINE__, __func__, ##args); \
- } while (0)
-
-#else /* CONFIG_USB_IP_DEBUG_ENABLE */
-
-#define usbip_udbg(fmt, args...) do { } while (0)
-
-#endif /* CONFIG_USB_IP_DEBUG_ENABLE */
-
+#ifdef DEBUG
+#define pr_fmt(fmt) KBUILD_MODNAME ": %s:%d: " fmt, __func__, __LINE__
+#else
+#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
+#endif
enum {
usbip_debug_xmit = (1 << 0),
@@ -87,16 +73,16 @@
#define usbip_dbg_with_flag(flag, fmt, args...) \
do { \
if (flag & usbip_debug_flag) \
- usbip_udbg(fmt , ##args); \
+ pr_debug(fmt, ##args); \
} while (0)
-#define usbip_dbg_sysfs(fmt, args...) \
+#define usbip_dbg_sysfs(fmt, args...) \
usbip_dbg_with_flag(usbip_debug_sysfs, fmt , ##args)
-#define usbip_dbg_xmit(fmt, args...) \
+#define usbip_dbg_xmit(fmt, args...) \
usbip_dbg_with_flag(usbip_debug_xmit, fmt , ##args)
-#define usbip_dbg_urb(fmt, args...) \
+#define usbip_dbg_urb(fmt, args...) \
usbip_dbg_with_flag(usbip_debug_urb, fmt , ##args)
-#define usbip_dbg_eh(fmt, args...) \
+#define usbip_dbg_eh(fmt, args...) \
usbip_dbg_with_flag(usbip_debug_eh, fmt , ##args)
#define usbip_dbg_vhci_rh(fmt, args...) \
@@ -107,42 +93,16 @@
usbip_dbg_with_flag(usbip_debug_vhci_rx, fmt , ##args)
#define usbip_dbg_vhci_tx(fmt, args...) \
usbip_dbg_with_flag(usbip_debug_vhci_tx, fmt , ##args)
-#define usbip_dbg_vhci_sysfs(fmt, args...) \
+#define usbip_dbg_vhci_sysfs(fmt, args...) \
usbip_dbg_with_flag(usbip_debug_vhci_sysfs, fmt , ##args)
-#define usbip_dbg_stub_cmp(fmt, args...) \
+#define usbip_dbg_stub_cmp(fmt, args...) \
usbip_dbg_with_flag(usbip_debug_stub_cmp, fmt , ##args)
-#define usbip_dbg_stub_rx(fmt, args...) \
+#define usbip_dbg_stub_rx(fmt, args...) \
usbip_dbg_with_flag(usbip_debug_stub_rx, fmt , ##args)
-#define usbip_dbg_stub_tx(fmt, args...) \
+#define usbip_dbg_stub_tx(fmt, args...) \
usbip_dbg_with_flag(usbip_debug_stub_tx, fmt , ##args)
-
-/**
- * usbip_uerr - print error messages
- * @fmt:
- * @args:
- */
-#define usbip_uerr(fmt, args...) \
- do { \
- printk(KERN_ERR "%-10s: ***ERROR*** (%s,%d) %s: " fmt, \
- (in_interrupt() ? "interrupt" : (current)->comm),\
- __FILE__, __LINE__, __func__, ##args); \
- } while (0)
-
-/**
- * usbip_uinfo - print information messages
- * @fmt:
- * @args:
- */
-#define usbip_uinfo(fmt, args...) \
- do { \
- printk(KERN_INFO "usbip: " fmt , ## args); \
- } while (0)
-
-
-/*-------------------------------------------------------------------------*/
-
/*
* USB/IP request headers.
* Currently, we define 4 request types:
@@ -185,7 +145,7 @@
#define USBIP_DIR_IN 1
__u32 direction;
__u32 ep; /* endpoint number */
-} __attribute__ ((packed));
+} __packed;
/*
* An additional header for a CMD_SUBMIT packet.
@@ -212,43 +172,40 @@
/* set setup packet data for a CTRL request */
unsigned char setup[8];
-} __attribute__ ((packed));
+} __packed;
/*
* An additional header for a RET_SUBMIT packet.
*/
struct usbip_header_ret_submit {
__s32 status;
- __s32 actual_length; /* returned data length */
- __s32 start_frame; /* ISO and INT */
- __s32 number_of_packets; /* ISO only */
- __s32 error_count; /* ISO only */
-} __attribute__ ((packed));
+ __s32 actual_length; /* returned data length */
+ __s32 start_frame; /* ISO and INT */
+ __s32 number_of_packets; /* ISO only */
+ __s32 error_count; /* ISO only */
+} __packed;
/*
* An additional header for a CMD_UNLINK packet.
*/
struct usbip_header_cmd_unlink {
- __u32 seqnum; /* URB's seqnum which will be unlinked */
-} __attribute__ ((packed));
-
+ __u32 seqnum; /* URB's seqnum that will be unlinked */
+} __packed;
/*
* An additional header for a RET_UNLINK packet.
*/
struct usbip_header_ret_unlink {
__s32 status;
-} __attribute__ ((packed));
-
+} __packed;
/* the same as usb_iso_packet_descriptor but packed for pdu */
struct usbip_iso_packet_descriptor {
__u32 offset;
- __u32 length; /* expected length */
+ __u32 length; /* expected length */
__u32 actual_length;
__u32 status;
-} __attribute__ ((packed));
-
+} __packed;
/*
* All usbip packets use a common header to keep code simple.
@@ -262,18 +219,11 @@
struct usbip_header_cmd_unlink cmd_unlink;
struct usbip_header_ret_unlink ret_unlink;
} u;
-} __attribute__ ((packed));
-
-
-
-
-/*-------------------------------------------------------------------------*/
-
+} __packed;
int usbip_xmit(int, struct socket *, char *, int, int);
int usbip_sendmsg(struct socket *, struct msghdr *, int);
-
static inline int interface_to_busnum(struct usb_interface *interface)
{
struct usb_device *udev = interface_to_usbdev(interface);
@@ -304,7 +254,6 @@
void usbip_dump_urb(struct urb *purb);
void usbip_dump_header(struct usbip_header *pdu);
-
struct usbip_device;
enum usbip_side {
@@ -331,7 +280,6 @@
/* a common structure for stub_device and vhci_device */
struct usbip_device {
enum usbip_side side;
-
enum usbip_status status;
/* lock for status */
@@ -370,9 +318,8 @@
} eh_ops;
};
-
void usbip_pack_pdu(struct usbip_header *pdu, struct urb *urb, int cmd,
- int pack);
+ int pack);
void usbip_header_correct_endian(struct usbip_header *pdu, int send);
/* some members of urb must be substituted before. */
@@ -383,12 +330,10 @@
int usbip_pad_iso(struct usbip_device *ud, struct urb *urb);
void *usbip_alloc_iso_desc_pdu(struct urb *urb, ssize_t *bufflen);
-
/* usbip_event.c */
int usbip_start_eh(struct usbip_device *ud);
void usbip_stop_eh(struct usbip_device *ud);
void usbip_event_add(struct usbip_device *ud, unsigned long event);
int usbip_event_happened(struct usbip_device *ud);
-
-#endif
+#endif /* __USBIP_COMMON_H */
diff --git a/drivers/staging/usbip/usbip_event.c b/drivers/staging/usbip/usbip_event.c
index f4b287e..ecd1862 100644
--- a/drivers/staging/usbip/usbip_event.c
+++ b/drivers/staging/usbip/usbip_event.c
@@ -17,9 +17,10 @@
* USA.
*/
-#include "usbip_common.h"
#include <linux/kthread.h>
+#include "usbip_common.h"
+
static int event_handler(struct usbip_device *ud)
{
usbip_dbg_eh("enter\n");
@@ -36,21 +37,18 @@
*/
if (ud->event & USBIP_EH_SHUTDOWN) {
ud->eh_ops.shutdown(ud);
-
ud->event &= ~USBIP_EH_SHUTDOWN;
}
/* Reset the device. */
if (ud->event & USBIP_EH_RESET) {
ud->eh_ops.reset(ud);
-
ud->event &= ~USBIP_EH_RESET;
}
/* Mark the device as unusable. */
if (ud->event & USBIP_EH_UNUSABLE) {
ud->eh_ops.unusable(ud);
-
ud->event &= ~USBIP_EH_UNUSABLE;
}
@@ -68,13 +66,14 @@
while (!kthread_should_stop()) {
wait_event_interruptible(ud->eh_waitq,
- usbip_event_happened(ud) ||
- kthread_should_stop());
+ usbip_event_happened(ud) ||
+ kthread_should_stop());
usbip_dbg_eh("wakeup\n");
if (event_handler(ud) < 0)
break;
}
+
return 0;
}
@@ -85,10 +84,10 @@
ud->eh = kthread_run(event_handler_loop, ud, "usbip_eh");
if (IS_ERR(ud->eh)) {
- printk(KERN_WARNING
- "Unable to start control thread\n");
+ pr_warning("Unable to start control thread\n");
return PTR_ERR(ud->eh);
}
+
return 0;
}
EXPORT_SYMBOL_GPL(usbip_start_eh);
@@ -106,11 +105,8 @@
void usbip_event_add(struct usbip_device *ud, unsigned long event)
{
spin_lock(&ud->lock);
-
ud->event |= event;
-
wake_up(&ud->eh_waitq);
-
spin_unlock(&ud->lock);
}
EXPORT_SYMBOL_GPL(usbip_event_add);
@@ -120,10 +116,8 @@
int happened = 0;
spin_lock(&ud->lock);
-
if (ud->event != 0)
happened = 1;
-
spin_unlock(&ud->lock);
return happened;
diff --git a/drivers/staging/usbip/userspace/AUTHORS b/drivers/staging/usbip/userspace/AUTHORS
new file mode 100644
index 0000000..2f73e65
--- /dev/null
+++ b/drivers/staging/usbip/userspace/AUTHORS
@@ -0,0 +1,2 @@
+Takahiro Hirofuchi
+Robert Leibl
diff --git a/drivers/staging/usbip/userspace/COPYING b/drivers/staging/usbip/userspace/COPYING
new file mode 100644
index 0000000..c5611e4
--- /dev/null
+++ b/drivers/staging/usbip/userspace/COPYING
@@ -0,0 +1,340 @@
+ GNU GENERAL PUBLIC LICENSE
+ Version 2, June 1991
+
+ Copyright (C) 1989, 1991 Free Software Foundation, Inc.
+ 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+ Everyone is permitted to copy and distribute verbatim copies
+ of this license document, but changing it is not allowed.
+
+ Preamble
+
+ The licenses for most software are designed to take away your
+freedom to share and change it. By contrast, the GNU General Public
+License is intended to guarantee your freedom to share and change free
+software--to make sure the software is free for all its users. This
+General Public License applies to most of the Free Software
+Foundation's software and to any other program whose authors commit to
+using it. (Some other Free Software Foundation software is covered by
+the GNU Library General Public License instead.) You can apply it to
+your programs, too.
+
+ When we speak of free software, we are referring to freedom, not
+price. Our General Public Licenses are designed to make sure that you
+have the freedom to distribute copies of free software (and charge for
+this service if you wish), that you receive source code or can get it
+if you want it, that you can change the software or use pieces of it
+in new free programs; and that you know you can do these things.
+
+ To protect your rights, we need to make restrictions that forbid
+anyone to deny you these rights or to ask you to surrender the rights.
+These restrictions translate to certain responsibilities for you if you
+distribute copies of the software, or if you modify it.
+
+ For example, if you distribute copies of such a program, whether
+gratis or for a fee, you must give the recipients all the rights that
+you have. You must make sure that they, too, receive or can get the
+source code. And you must show them these terms so they know their
+rights.
+
+ We protect your rights with two steps: (1) copyright the software, and
+(2) offer you this license which gives you legal permission to copy,
+distribute and/or modify the software.
+
+ Also, for each author's protection and ours, we want to make certain
+that everyone understands that there is no warranty for this free
+software. If the software is modified by someone else and passed on, we
+want its recipients to know that what they have is not the original, so
+that any problems introduced by others will not reflect on the original
+authors' reputations.
+
+ Finally, any free program is threatened constantly by software
+patents. We wish to avoid the danger that redistributors of a free
+program will individually obtain patent licenses, in effect making the
+program proprietary. To prevent this, we have made it clear that any
+patent must be licensed for everyone's free use or not licensed at all.
+
+ The precise terms and conditions for copying, distribution and
+modification follow.
+
+ GNU GENERAL PUBLIC LICENSE
+ TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION
+
+ 0. This License applies to any program or other work which contains
+a notice placed by the copyright holder saying it may be distributed
+under the terms of this General Public License. The "Program", below,
+refers to any such program or work, and a "work based on the Program"
+means either the Program or any derivative work under copyright law:
+that is to say, a work containing the Program or a portion of it,
+either verbatim or with modifications and/or translated into another
+language. (Hereinafter, translation is included without limitation in
+the term "modification".) Each licensee is addressed as "you".
+
+Activities other than copying, distribution and modification are not
+covered by this License; they are outside its scope. The act of
+running the Program is not restricted, and the output from the Program
+is covered only if its contents constitute a work based on the
+Program (independent of having been made by running the Program).
+Whether that is true depends on what the Program does.
+
+ 1. You may copy and distribute verbatim copies of the Program's
+source code as you receive it, in any medium, provided that you
+conspicuously and appropriately publish on each copy an appropriate
+copyright notice and disclaimer of warranty; keep intact all the
+notices that refer to this License and to the absence of any warranty;
+and give any other recipients of the Program a copy of this License
+along with the Program.
+
+You may charge a fee for the physical act of transferring a copy, and
+you may at your option offer warranty protection in exchange for a fee.
+
+ 2. You may modify your copy or copies of the Program or any portion
+of it, thus forming a work based on the Program, and copy and
+distribute such modifications or work under the terms of Section 1
+above, provided that you also meet all of these conditions:
+
+ a) You must cause the modified files to carry prominent notices
+ stating that you changed the files and the date of any change.
+
+ b) You must cause any work that you distribute or publish, that in
+ whole or in part contains or is derived from the Program or any
+ part thereof, to be licensed as a whole at no charge to all third
+ parties under the terms of this License.
+
+ c) If the modified program normally reads commands interactively
+ when run, you must cause it, when started running for such
+ interactive use in the most ordinary way, to print or display an
+ announcement including an appropriate copyright notice and a
+ notice that there is no warranty (or else, saying that you provide
+ a warranty) and that users may redistribute the program under
+ these conditions, and telling the user how to view a copy of this
+ License. (Exception: if the Program itself is interactive but
+ does not normally print such an announcement, your work based on
+ the Program is not required to print an announcement.)
+
+These requirements apply to the modified work as a whole. If
+identifiable sections of that work are not derived from the Program,
+and can be reasonably considered independent and separate works in
+themselves, then this License, and its terms, do not apply to those
+sections when you distribute them as separate works. But when you
+distribute the same sections as part of a whole which is a work based
+on the Program, the distribution of the whole must be on the terms of
+this License, whose permissions for other licensees extend to the
+entire whole, and thus to each and every part regardless of who wrote it.
+
+Thus, it is not the intent of this section to claim rights or contest
+your rights to work written entirely by you; rather, the intent is to
+exercise the right to control the distribution of derivative or
+collective works based on the Program.
+
+In addition, mere aggregation of another work not based on the Program
+with the Program (or with a work based on the Program) on a volume of
+a storage or distribution medium does not bring the other work under
+the scope of this License.
+
+ 3. You may copy and distribute the Program (or a work based on it,
+under Section 2) in object code or executable form under the terms of
+Sections 1 and 2 above provided that you also do one of the following:
+
+ a) Accompany it with the complete corresponding machine-readable
+ source code, which must be distributed under the terms of Sections
+ 1 and 2 above on a medium customarily used for software interchange; or,
+
+ b) Accompany it with a written offer, valid for at least three
+ years, to give any third party, for a charge no more than your
+ cost of physically performing source distribution, a complete
+ machine-readable copy of the corresponding source code, to be
+ distributed under the terms of Sections 1 and 2 above on a medium
+ customarily used for software interchange; or,
+
+ c) Accompany it with the information you received as to the offer
+ to distribute corresponding source code. (This alternative is
+ allowed only for noncommercial distribution and only if you
+ received the program in object code or executable form with such
+ an offer, in accord with Subsection b above.)
+
+The source code for a work means the preferred form of the work for
+making modifications to it. For an executable work, complete source
+code means all the source code for all modules it contains, plus any
+associated interface definition files, plus the scripts used to
+control compilation and installation of the executable. However, as a
+special exception, the source code distributed need not include
+anything that is normally distributed (in either source or binary
+form) with the major components (compiler, kernel, and so on) of the
+operating system on which the executable runs, unless that component
+itself accompanies the executable.
+
+If distribution of executable or object code is made by offering
+access to copy from a designated place, then offering equivalent
+access to copy the source code from the same place counts as
+distribution of the source code, even though third parties are not
+compelled to copy the source along with the object code.
+
+ 4. You may not copy, modify, sublicense, or distribute the Program
+except as expressly provided under this License. Any attempt
+otherwise to copy, modify, sublicense or distribute the Program is
+void, and will automatically terminate your rights under this License.
+However, parties who have received copies, or rights, from you under
+this License will not have their licenses terminated so long as such
+parties remain in full compliance.
+
+ 5. You are not required to accept this License, since you have not
+signed it. However, nothing else grants you permission to modify or
+distribute the Program or its derivative works. These actions are
+prohibited by law if you do not accept this License. Therefore, by
+modifying or distributing the Program (or any work based on the
+Program), you indicate your acceptance of this License to do so, and
+all its terms and conditions for copying, distributing or modifying
+the Program or works based on it.
+
+ 6. Each time you redistribute the Program (or any work based on the
+Program), the recipient automatically receives a license from the
+original licensor to copy, distribute or modify the Program subject to
+these terms and conditions. You may not impose any further
+restrictions on the recipients' exercise of the rights granted herein.
+You are not responsible for enforcing compliance by third parties to
+this License.
+
+ 7. If, as a consequence of a court judgment or allegation of patent
+infringement or for any other reason (not limited to patent issues),
+conditions are imposed on you (whether by court order, agreement or
+otherwise) that contradict the conditions of this License, they do not
+excuse you from the conditions of this License. If you cannot
+distribute so as to satisfy simultaneously your obligations under this
+License and any other pertinent obligations, then as a consequence you
+may not distribute the Program at all. For example, if a patent
+license would not permit royalty-free redistribution of the Program by
+all those who receive copies directly or indirectly through you, then
+the only way you could satisfy both it and this License would be to
+refrain entirely from distribution of the Program.
+
+If any portion of this section is held invalid or unenforceable under
+any particular circumstance, the balance of the section is intended to
+apply and the section as a whole is intended to apply in other
+circumstances.
+
+It is not the purpose of this section to induce you to infringe any
+patents or other property right claims or to contest validity of any
+such claims; this section has the sole purpose of protecting the
+integrity of the free software distribution system, which is
+implemented by public license practices. Many people have made
+generous contributions to the wide range of software distributed
+through that system in reliance on consistent application of that
+system; it is up to the author/donor to decide if he or she is willing
+to distribute software through any other system and a licensee cannot
+impose that choice.
+
+This section is intended to make thoroughly clear what is believed to
+be a consequence of the rest of this License.
+
+ 8. If the distribution and/or use of the Program is restricted in
+certain countries either by patents or by copyrighted interfaces, the
+original copyright holder who places the Program under this License
+may add an explicit geographical distribution limitation excluding
+those countries, so that distribution is permitted only in or among
+countries not thus excluded. In such case, this License incorporates
+the limitation as if written in the body of this License.
+
+ 9. The Free Software Foundation may publish revised and/or new versions
+of the General Public License from time to time. Such new versions will
+be similar in spirit to the present version, but may differ in detail to
+address new problems or concerns.
+
+Each version is given a distinguishing version number. If the Program
+specifies a version number of this License which applies to it and "any
+later version", you have the option of following the terms and conditions
+either of that version or of any later version published by the Free
+Software Foundation. If the Program does not specify a version number of
+this License, you may choose any version ever published by the Free Software
+Foundation.
+
+ 10. If you wish to incorporate parts of the Program into other free
+programs whose distribution conditions are different, write to the author
+to ask for permission. For software which is copyrighted by the Free
+Software Foundation, write to the Free Software Foundation; we sometimes
+make exceptions for this. Our decision will be guided by the two goals
+of preserving the free status of all derivatives of our free software and
+of promoting the sharing and reuse of software generally.
+
+ NO WARRANTY
+
+ 11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY
+FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN
+OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES
+PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED
+OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS
+TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE
+PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING,
+REPAIR OR CORRECTION.
+
+ 12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
+WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR
+REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES,
+INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING
+OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED
+TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY
+YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER
+PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE
+POSSIBILITY OF SUCH DAMAGES.
+
+ END OF TERMS AND CONDITIONS
+
+ How to Apply These Terms to Your New Programs
+
+ If you develop a new program, and you want it to be of the greatest
+possible use to the public, the best way to achieve this is to make it
+free software which everyone can redistribute and change under these terms.
+
+ To do so, attach the following notices to the program. It is safest
+to attach them to the start of each source file to most effectively
+convey the exclusion of warranty; and each file should have at least
+the "copyright" line and a pointer to where the full notice is found.
+
+ <one line to give the program's name and a brief idea of what it does.>
+ Copyright (C) <year> <name of author>
+
+ This program is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 2 of the License, or
+ (at your option) any later version.
+
+ This program is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
+
+
+Also add information on how to contact you by electronic and paper mail.
+
+If the program is interactive, make it output a short notice like this
+when it starts in an interactive mode:
+
+ Gnomovision version 69, Copyright (C) year name of author
+ Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+ This is free software, and you are welcome to redistribute it
+ under certain conditions; type `show c' for details.
+
+The hypothetical commands `show w' and `show c' should show the appropriate
+parts of the General Public License. Of course, the commands you use may
+be called something other than `show w' and `show c'; they could even be
+mouse-clicks or menu items--whatever suits your program.
+
+You should also get your employer (if you work as a programmer) or your
+school, if any, to sign a "copyright disclaimer" for the program, if
+necessary. Here is a sample; alter the names:
+
+ Yoyodyne, Inc., hereby disclaims all copyright interest in the program
+ `Gnomovision' (which makes passes at compilers) written by James Hacker.
+
+ <signature of Ty Coon>, 1 April 1989
+ Ty Coon, President of Vice
+
+This General Public License does not permit incorporating your program into
+proprietary programs. If your program is a subroutine library, you may
+consider it more useful to permit linking proprietary applications with the
+library. If this is what you want to do, use the GNU Library General
+Public License instead of this License.
diff --git a/drivers/staging/usbip/userspace/INSTALL b/drivers/staging/usbip/userspace/INSTALL
new file mode 100644
index 0000000..d3c5b40
--- /dev/null
+++ b/drivers/staging/usbip/userspace/INSTALL
@@ -0,0 +1,237 @@
+Installation Instructions
+*************************
+
+Copyright (C) 1994, 1995, 1996, 1999, 2000, 2001, 2002, 2004, 2005,
+2006, 2007 Free Software Foundation, Inc.
+
+This file is free documentation; the Free Software Foundation gives
+unlimited permission to copy, distribute and modify it.
+
+Basic Installation
+==================
+
+Briefly, the shell commands `./configure; make; make install' should
+configure, build, and install this package. The following
+more-detailed instructions are generic; see the `README' file for
+instructions specific to this package.
+
+ The `configure' shell script attempts to guess correct values for
+various system-dependent variables used during compilation. It uses
+those values to create a `Makefile' in each directory of the package.
+It may also create one or more `.h' files containing system-dependent
+definitions. Finally, it creates a shell script `config.status' that
+you can run in the future to recreate the current configuration, and a
+file `config.log' containing compiler output (useful mainly for
+debugging `configure').
+
+ It can also use an optional file (typically called `config.cache'
+and enabled with `--cache-file=config.cache' or simply `-C') that saves
+the results of its tests to speed up reconfiguring. Caching is
+disabled by default to prevent problems with accidental use of stale
+cache files.
+
+ If you need to do unusual things to compile the package, please try
+to figure out how `configure' could check whether to do them, and mail
+diffs or instructions to the address given in the `README' so they can
+be considered for the next release. If you are using the cache, and at
+some point `config.cache' contains results you don't want to keep, you
+may remove or edit it.
+
+ The file `configure.ac' (or `configure.in') is used to create
+`configure' by a program called `autoconf'. You need `configure.ac' if
+you want to change it or regenerate `configure' using a newer version
+of `autoconf'.
+
+The simplest way to compile this package is:
+
+ 1. `cd' to the directory containing the package's source code and type
+ `./configure' to configure the package for your system.
+
+ Running `configure' might take a while. While running, it prints
+ some messages telling which features it is checking for.
+
+ 2. Type `make' to compile the package.
+
+ 3. Optionally, type `make check' to run any self-tests that come with
+ the package.
+
+ 4. Type `make install' to install the programs and any data files and
+ documentation.
+
+ 5. You can remove the program binaries and object files from the
+ source code directory by typing `make clean'. To also remove the
+ files that `configure' created (so you can compile the package for
+ a different kind of computer), type `make distclean'. There is
+ also a `make maintainer-clean' target, but that is intended mainly
+ for the package's developers. If you use it, you may have to get
+ all sorts of other programs in order to regenerate files that came
+ with the distribution.
+
+ 6. Often, you can also type `make uninstall' to remove the installed
+ files again.
+
+Compilers and Options
+=====================
+
+Some systems require unusual options for compilation or linking that the
+`configure' script does not know about. Run `./configure --help' for
+details on some of the pertinent environment variables.
+
+ You can give `configure' initial values for configuration parameters
+by setting variables in the command line or in the environment. Here
+is an example:
+
+ ./configure CC=c99 CFLAGS=-g LIBS=-lposix
+
+ *Note Defining Variables::, for more details.
+
+Compiling For Multiple Architectures
+====================================
+
+You can compile the package for more than one kind of computer at the
+same time, by placing the object files for each architecture in their
+own directory. To do this, you can use GNU `make'. `cd' to the
+directory where you want the object files and executables to go and run
+the `configure' script. `configure' automatically checks for the
+source code in the directory that `configure' is in and in `..'.
+
+ With a non-GNU `make', it is safer to compile the package for one
+architecture at a time in the source code directory. After you have
+installed the package for one architecture, use `make distclean' before
+reconfiguring for another architecture.
+
+Installation Names
+==================
+
+By default, `make install' installs the package's commands under
+`/usr/local/bin', include files under `/usr/local/include', etc. You
+can specify an installation prefix other than `/usr/local' by giving
+`configure' the option `--prefix=PREFIX'.
+
+ You can specify separate installation prefixes for
+architecture-specific files and architecture-independent files. If you
+pass the option `--exec-prefix=PREFIX' to `configure', the package uses
+PREFIX as the prefix for installing programs and libraries.
+Documentation and other data files still use the regular prefix.
+
+ In addition, if you use an unusual directory layout you can give
+options like `--bindir=DIR' to specify different values for particular
+kinds of files. Run `configure --help' for a list of the directories
+you can set and what kinds of files go in them.
+
+ If the package supports it, you can cause programs to be installed
+with an extra prefix or suffix on their names by giving `configure' the
+option `--program-prefix=PREFIX' or `--program-suffix=SUFFIX'.
+
+Optional Features
+=================
+
+Some packages pay attention to `--enable-FEATURE' options to
+`configure', where FEATURE indicates an optional part of the package.
+They may also pay attention to `--with-PACKAGE' options, where PACKAGE
+is something like `gnu-as' or `x' (for the X Window System). The
+`README' should mention any `--enable-' and `--with-' options that the
+package recognizes.
+
+ For packages that use the X Window System, `configure' can usually
+find the X include and library files automatically, but if it doesn't,
+you can use the `configure' options `--x-includes=DIR' and
+`--x-libraries=DIR' to specify their locations.
+
+Specifying the System Type
+==========================
+
+There may be some features `configure' cannot figure out automatically,
+but needs to determine by the type of machine the package will run on.
+Usually, assuming the package is built to be run on the _same_
+architectures, `configure' can figure that out, but if it prints a
+message saying it cannot guess the machine type, give it the
+`--build=TYPE' option. TYPE can either be a short name for the system
+type, such as `sun4', or a canonical name which has the form:
+
+ CPU-COMPANY-SYSTEM
+
+where SYSTEM can have one of these forms:
+
+ OS KERNEL-OS
+
+ See the file `config.sub' for the possible values of each field. If
+`config.sub' isn't included in this package, then this package doesn't
+need to know the machine type.
+
+ If you are _building_ compiler tools for cross-compiling, you should
+use the option `--target=TYPE' to select the type of system they will
+produce code for.
+
+ If you want to _use_ a cross compiler, that generates code for a
+platform different from the build platform, you should specify the
+"host" platform (i.e., that on which the generated programs will
+eventually be run) with `--host=TYPE'.
+
+Sharing Defaults
+================
+
+If you want to set default values for `configure' scripts to share, you
+can create a site shell script called `config.site' that gives default
+values for variables like `CC', `cache_file', and `prefix'.
+`configure' looks for `PREFIX/share/config.site' if it exists, then
+`PREFIX/etc/config.site' if it exists. Or, you can set the
+`CONFIG_SITE' environment variable to the location of the site script.
+A warning: not all `configure' scripts look for a site script.
+
+Defining Variables
+==================
+
+Variables not defined in a site shell script can be set in the
+environment passed to `configure'. However, some packages may run
+configure again during the build, and the customized values of these
+variables may be lost. In order to avoid this problem, you should set
+them in the `configure' command line, using `VAR=value'. For example:
+
+ ./configure CC=/usr/local2/bin/gcc
+
+causes the specified `gcc' to be used as the C compiler (unless it is
+overridden in the site shell script).
+
+Unfortunately, this technique does not work for `CONFIG_SHELL' due to
+an Autoconf bug. Until the bug is fixed you can use this workaround:
+
+ CONFIG_SHELL=/bin/bash /bin/bash ./configure CONFIG_SHELL=/bin/bash
+
+`configure' Invocation
+======================
+
+`configure' recognizes the following options to control how it operates.
+
+`--help'
+`-h'
+ Print a summary of the options to `configure', and exit.
+
+`--version'
+`-V'
+ Print the version of Autoconf used to generate the `configure'
+ script, and exit.
+
+`--cache-file=FILE'
+ Enable the cache: use and save the results of the tests in FILE,
+ traditionally `config.cache'. FILE defaults to `/dev/null' to
+ disable caching.
+
+`--config-cache'
+`-C'
+ Alias for `--cache-file=config.cache'.
+
+`--quiet'
+`--silent'
+`-q'
+ Do not print messages saying which checks are being made. To
+ suppress all normal output, redirect it to `/dev/null' (any error
+ messages will still be shown).
+
+`--srcdir=DIR'
+ Look for the package's source code in directory DIR. Usually
+ `configure' can determine that directory automatically.
+
+`configure' also accepts some other, not widely useful, options. Run
+`configure --help' for more details.
+
diff --git a/drivers/staging/usbip/userspace/Makefile.am b/drivers/staging/usbip/userspace/Makefile.am
new file mode 100644
index 0000000..83f51b8
--- /dev/null
+++ b/drivers/staging/usbip/userspace/Makefile.am
@@ -0,0 +1,11 @@
+SUBDIRS := libsrc src
+includedir := @includedir@/usbip
+include_HEADERS := $(addprefix libsrc/, \
+ usbip.h usbip_common.h vhci_driver.h stub_driver.h)
+
+dist_man_MANS := $(addprefix doc/, usbip.8 usbipd.8 usbip_bind_driver.8)
+
+if INSTALL_USBIDS
+pkgdata_DATA := usb.ids
+EXTRA_DIST := $(pkgdata_DATA)
+endif
diff --git a/drivers/staging/usbip/userspace/README b/drivers/staging/usbip/userspace/README
new file mode 100644
index 0000000..2ee84b9
--- /dev/null
+++ b/drivers/staging/usbip/userspace/README
@@ -0,0 +1,215 @@
+# vim:tw=78:ts=4:expandtab:ai:sw=4
+#
+# README for usbip-utils
+#
+# Copyright (C) 2005-2008 Takahiro Hirofuchi
+
+
+[Requirements]
+ - USB/IP device drivers
+ Its source code is included under $(top)/drivers/.
+
+ - sysfsutils >= 2.0.0
+ sysfsutils library
+
+ - libwrap0-dev
+ tcp wrapper library
+
+ - gcc >= 4.0
+
+ - libglib2.0-dev >= 2.6.0
+
+ - libtool, automake >= 1.9, autoconf >= 2.5.0, pkg-config
+
+[Install]
+ 0. Skip here if you see a configure script.
+ $ ./autogen.sh
+
+ 1. Compile & install.
+ $ ./configure
+ $ make install
+
+ 2. Compile & install USB/IP drivers if not yet.
+
+[Usage]
+ server:# (Attach your USB device physically.)
+
+ server:# insmod usbip-core.ko
+ server:# insmod usbip-host.ko
+ - It was formerly named as stub.ko.
+
+ server:# usbipd -D
+ - Start usbip daemon.
+
+ server:# usbip_bind_driver --list
+ - List driver assignments for usb devices.
+
+ server:# usbip_bind_driver --usbip 1-2
+ - Bind usbip-host.ko to the device of busid 1-2.
+ - A usb device 1-2 is now exportable to other hosts!
+ - Use 'usbip_bind_driver --other 1-2' when you want to shutdown exporting
+ and use the device locally.
+
+
+ client:# insmod usbip-core.ko
+ client:# insmod vhci-hcd.ko
+ - It was formerly named as vhci.ko.
+
+ client:# usbip --list server
+ - List exportable usb devices on the server.
+
+ client:# usbip --attach server 1-2
+ - Connect the remote USB device.
+
+ client:# usbip --port
+ - Show virtual port status.
+
+ client:# usbip --detach 0
+ - Detach the usb device.
+
+
+[Output Example]
+--------------------------------------------------------------------------------------------------------
+- SERVER SIDE (physically attach your USB devices to this host) ----------------------------------------
+--------------------------------------------------------------------------------------------------------
+trois:# insmod (somewhere)/usbip-core.ko
+trois:# insmod (somewhere)/usbip-host.ko
+trois:# usbipd -D
+
+--------------------------------------------------------------------------------------------------------
+In another terminal, let's look up what usb devices are physically attached to
+this host. We can see a usb storage device of busid 3-3.2 is now bound to
+usb-storage driver. To export this device, we first mark the device as
+"exportable"; the device is bound to usbip driver. Please remember you can not
+export a usb hub.
+
+ trois:# usbip_bind_driver --list
+ List USB devices
+ - busid 3-3.2 (04bb:0206)
+ 3-3.2:1.0 -> usb-storage
+
+ - busid 3-3.1 (08bb:2702)
+ 3-3.1:1.0 -> snd-usb-audio
+ 3-3.1:1.1 -> snd-usb-audio
+
+ - busid 3-3 (0409:0058)
+ 3-3:1.0 -> hub
+
+ - busid 3-2 (0711:0902)
+ 3-2:1.0 -> none
+
+ - busid 1-1 (05a9:a511)
+ 1-1:1.0 -> ov511
+
+ - busid 4-1 (046d:08b2)
+ 4-1:1.0 -> none
+ 4-1:1.1 -> none
+ 4-1:1.2 -> none
+
+ - busid 5-2 (058f:9254)
+ 5-2:1.0 -> hub
+
+--------------------------------------------------------------------------------------------------------
+Mark the device of busid 3-3.2 as exportable.
+
+ trois:# usbip_bind_driver --usbip 3-3.2
+ ** (process:24621): DEBUG: 3-3.2:1.0 -> none
+ ** (process:24621): DEBUG: write "add 3-3.2" to /sys/bus/usb/drivers/usbip/match_busid
+ ** Message: bind 3-3.2 to usbip, complete!
+
+ trois:# usbip_bind_driver --list
+ List USB devices
+ - busid 3-3.2 (04bb:0206)
+ 3-3.2:1.0 -> usbip
+ (snip)
+
+Iterate the above operation for other devices if you like.
+
+
+--------------------------------------------------------------------------------------------------------
+- CLIENT SIDE ------------------------------------------------------------------------------------------
+--------------------------------------------------------------------------------------------------------
+First, let's list available remote devices which are marked as exportable in
+the server host.
+
+ deux:# insmod (somewhere)/usbip-core.ko
+ deux:# insmod (somewhere)/vhci_hcd.ko
+
+ deux:# usbip --list 10.0.0.3
+ - 10.0.0.3
+ 1-1: Prolific Technology, Inc. : unknown product (067b:3507)
+ : /sys/devices/pci0000:00/0000:00:1f.2/usb1/1-1
+ : (Defined at Interface level) / unknown subclass / unknown protocol (00/00/00)
+ : 0 - Mass Storage / SCSI / Bulk (Zip) (08/06/50)
+
+ 1-2.2.1: Apple Computer, Inc. : unknown product (05ac:0203)
+ : /sys/devices/pci0000:00/0000:00:1f.2/usb1/1-2/1-2.2/1-2.2.1
+ : (Defined at Interface level) / unknown subclass / unknown protocol (00/00/00)
+ : 0 - Human Interface Devices / Boot Interface Subclass / Keyboard (03/01/01)
+
+ 1-2.2.3: OmniVision Technologies, Inc. : OV511+ WebCam (05a9:a511)
+ : /sys/devices/pci0000:00/0000:00:1f.2/usb1/1-2/1-2.2/1-2.2.3
+ : (Defined at Interface level) / unknown subclass / unknown protocol (00/00/00)
+ : 0 - Vendor Specific Class / unknown subclass / unknown protocol (ff/00/00)
+
+ 3-1: Logitech, Inc. : QuickCam Pro 4000 (046d:08b2)
+ : /sys/devices/pci0000:00/0000:00:1e.0/0000:02:0a.0/usb3/3-1
+ : (Defined at Interface level) / unknown subclass / unknown protocol (00/00/00)
+ : 0 - Data / unknown subclass / unknown protocol (0a/ff/00)
+ : 1 - Audio / Control Device / unknown protocol (01/01/00)
+ : 2 - Audio / Streaming / unknown protocol (01/02/00)
+
+ 4-1: Logitech, Inc. : QuickCam Express (046d:0870)
+ : /sys/devices/pci0000:00/0000:00:1e.0/0000:02:0a.1/usb4/4-1
+ : Vendor Specific Class / Vendor Specific Subclass / Vendor Specific Protocol (ff/ff/ff)
+ : 0 - Vendor Specific Class / Vendor Specific Subclass / Vendor Specific Protocol (ff/ff/ff)
+
+ 4-2: Texas Instruments Japan : unknown product (08bb:2702)
+ : /sys/devices/pci0000:00/0000:00:1e.0/0000:02:0a.1/usb4/4-2
+ : (Defined at Interface level) / unknown subclass / unknown protocol (00/00/00)
+ : 0 - Audio / Control Device / unknown protocol (01/01/00)
+ : 1 - Audio / Streaming / unknown protocol (01/02/00)
+
+--------------------------------------------------------------------------------------------------------
+Attach a remote usb device!
+
+ deux:# usbip --attach 10.0.0.3 1-1
+ port 0 attached
+
+--------------------------------------------------------------------------------------------------------
+Show what devices are attached to this client.
+
+ deux:# usbip --port
+ Port 00: <Port in Use> at Full Speed(12Mbps)
+ Prolific Technology, Inc. : unknown product (067b:3507)
+ 6-1 -> usbip://10.0.0.3:3240/1-1 (remote bus/dev 001/004)
+ 6-1:1.0 used by usb-storage
+ /sys/class/scsi_device/0:0:0:0/device
+ /sys/class/scsi_host/host0/device
+ /sys/block/sda/device
+
+--------------------------------------------------------------------------------------------------------
+Detach the imported device.
+
+ deux:# usbip --detach 0
+ port 0 detached
+
+--------------------------------------------------------------------------------------------------------
+
+
+[Check List]
+ - See Debug Tips in the project wiki.
+ - http://usbip.wiki.sourceforge.net/how-to-debug-usbip
+ - usbip-host.ko must be bound to the target device.
+ - See /proc/bus/usb/devices and find "Driver=..." lines of the device.
+ - Shutdown firewall.
+ - usbip now uses TCP port 3240.
+ - Disable SELinux.
+ - If possible, compile your kernel with CONFIG_USB_DEBUG flag and try
+ again.
+ - Check your kernel and daemon messages.
+ ex. /var/log/{messages, kern.log, daemon.log, syslog}
+
+
+[Contact]
+ Mailing List: usbip-devel _at_ lists.sourceforge.net
diff --git a/drivers/staging/usbip/userspace/autogen.sh b/drivers/staging/usbip/userspace/autogen.sh
new file mode 100755
index 0000000..e1112d3
--- /dev/null
+++ b/drivers/staging/usbip/userspace/autogen.sh
@@ -0,0 +1,9 @@
+#!/bin/sh -x
+
+#aclocal
+#autoheader
+#libtoolize --copy --force
+#automake-1.9 -acf
+#autoconf
+
+autoreconf -i -f -v
diff --git a/drivers/staging/usbip/userspace/cleanup.sh b/drivers/staging/usbip/userspace/cleanup.sh
new file mode 100755
index 0000000..da2f89b
--- /dev/null
+++ b/drivers/staging/usbip/userspace/cleanup.sh
@@ -0,0 +1,10 @@
+#!/bin/sh -x
+
+
+if [ -r Makefile ]; then
+ make distclean
+fi
+
+FILES="configure cscope.out Makefile.in depcomp compile config.guess config.sub config.h.in~ config.log config.status ltmain.sh libtool config.h.in autom4te.cache missing aclocal.m4 install-sh cmd/Makefile.in lib/Makefile.in Makefile lib/Makefile cmd/Makefile"
+
+rm -Rf $FILES
diff --git a/drivers/staging/usbip/userspace/configure.ac b/drivers/staging/usbip/userspace/configure.ac
new file mode 100644
index 0000000..e3afa15
--- /dev/null
+++ b/drivers/staging/usbip/userspace/configure.ac
@@ -0,0 +1,114 @@
+dnl Process this file with autoconf to produce a configure script.
+
+AC_PREREQ(2.59)
+AC_INIT([usbip], [0.1.8], [usbip-devel@lists.sourceforge.net])
+AC_DEFINE([USBIP_VERSION], [0x000106], [numeric version number])
+
+CURRENT=0
+REVISION=1
+AGE=0
+AC_SUBST([LIBUSBIP_VERSION], [$CURRENT:$REVISION:$AGE], [library version])
+
+AC_CONFIG_SRCDIR([src/usbipd.c])
+AC_CONFIG_HEADERS([config.h])
+
+AM_INIT_AUTOMAKE([foreign])
+LT_INIT
+
+# Silent build for automake >= 1.11
+m4_ifdef([AM_SILENT_RULES], [AM_SILENT_RULES([yes])])
+
+AC_SUBST([EXTRA_CFLAGS], ["-Wall -Werror -Wextra -std=gnu99"])
+
+# Checks for programs.
+AC_PROG_CC
+AC_PROG_INSTALL
+AC_PROG_MAKE_SET
+
+# Checks for header files.
+AC_HEADER_DIRENT
+AC_HEADER_STDC
+AC_CHECK_HEADERS([arpa/inet.h fcntl.h netdb.h netinet/in.h stdint.h stdlib.h dnl
+ string.h strings.h sys/socket.h syslog.h unistd.h])
+
+# Checks for typedefs, structures, and compiler characteristics.
+AC_TYPE_INT32_T
+AC_TYPE_SIZE_T
+AC_TYPE_SSIZE_T
+AC_TYPE_UINT16_T
+AC_TYPE_UINT32_T
+AC_TYPE_UINT8_T
+
+# Checks for library functions.
+AC_FUNC_REALLOC
+AC_CHECK_FUNCS([bzero memset mkdir regcomp socket strchr strerror strstr dnl
+ strtoul])
+
+AC_CHECK_HEADER([sysfs/libsysfs.h],
+ [AC_CHECK_LIB([sysfs], [sysfs_open_directory_list],
+ [LIBS="$LIBS -lsysfs"],
+ [AC_MSG_ERROR([Missing sysfs2 library!])])],
+ [AC_MSG_ERROR([Missing /usr/include/sysfs/libsysfs.h])])
+
+# Checks for libwrap library.
+AC_MSG_CHECKING([whether to use the libwrap (TCP wrappers) library])
+AC_ARG_WITH([tcp-wrappers],
+ [AS_HELP_STRING([--with-tcp-wrappers],
+ [use the libwrap (TCP wrappers) library])],
+ dnl [ACTION-IF-GIVEN]
+ [saved_LIBS="$LIBS"
+ if test "$withval" = "yes"; then
+ AC_MSG_RESULT([yes])
+ AC_MSG_CHECKING([for hosts_access in -lwrap])
+ LIBS="-lwrap $LIBS"
+ AC_TRY_LINK(
+ [int hosts_access(); int allow_severity, deny_severity;],
+ [hosts_access()],
+ [AC_MSG_RESULT([yes]);
+ AC_DEFINE([HAVE_LIBWRAP], [1],
+ [use tcp wrapper]) wrap_LIB="-lwrap"],
+ [AC_MSG_RESULT([not found]); exit 1])
+ else
+ AC_MSG_RESULT([no])
+ fi
+ LIBS="$saved_LIBS"],
+ dnl [ACTION-IF-NOT-GIVEN]
+ [AC_MSG_RESULT([(default)])
+ AC_MSG_CHECKING([for hosts_access in -lwrap])
+ saved_LIBS="$LIBS"
+ LIBS="-lwrap $saved_LIBS"
+ AC_TRY_LINK(
+ [int hosts_access(); int allow_severity, deny_severity;],
+ [hosts_access()],
+ [AC_MSG_RESULT([yes]);
+ AC_DEFINE([HAVE_LIBWRAP], [1], [use tcp wrapper])],
+ [AC_MSG_RESULT([no]); LIBS="$saved_LIBS"])])
+
+# Sets directory containing usb.ids.
+USBIDS_DIR='${datadir}/usbip'
+AC_ARG_WITH([usbids-dir],
+ [AS_HELP_STRING([--with-usbids-dir=DIR],
+ [where usb.ids is found (default ${datadir}/usbip)])],
+ [USBIDS_DIR=$withval])
+AC_SUBST([USBIDS_DIR])
+
+dnl FIXME: when disabled, empty directry is created
+usbids=install
+AC_ARG_ENABLE([usbids-install],
+ [AS_HELP_STRING([--enable-usbids-install],
+ [install usb.ids (default)])],
+ [AS_CASE([$enableval],
+ [yes], [usbids=install],
+ [no], [usbids=notinstall],
+ [AC_MSG_ERROR(
+ [bad value ${enableval} for --enable-usbids-install])]
+ )])
+AM_CONDITIONAL([INSTALL_USBIDS], [test x$usbids = xinstall])
+
+GLIB2_REQUIRED=2.6.0
+PKG_CHECK_MODULES([PACKAGE], [glib-2.0 >= $GLIB2_REQUIRED])
+AC_SUBST([PACKAGE_CFLAGS])
+AC_SUBST([PACKAGE_LIBS])
+
+AC_CONFIG_FILES([Makefile libsrc/Makefile src/Makefile])
+AC_OUTPUT
diff --git a/drivers/staging/usbip/userspace/doc/usbip.8 b/drivers/staging/usbip/userspace/doc/usbip.8
new file mode 100644
index 0000000..1653bb2
--- /dev/null
+++ b/drivers/staging/usbip/userspace/doc/usbip.8
@@ -0,0 +1,71 @@
+.TH USBIP "8" "February 2009" "usbip" "System Administration Utilities"
+.SH NAME
+usbip \- manage USB/IP devices
+.SH SYNOPSIS
+.B usbip
+[\fIoptions\fR]
+
+.SH DESCRIPTION
+Devices exported by USB/IP servers can be listed, attached and
+detached using this program.
+
+.SH OPTIONS
+.HP
+\fB\-a\fR, \fB\-\-attach\fR <host> <bus_id>
+.IP
+Attach a remote USB device.
+.PP
+
+.HP
+\fB\-x\fR, \fB\-\-attachall\fR <host>
+.IP
+Attach all remote USB devices on the specific host.
+.PP
+
+.HP
+\fB\-d\fR, \fB\-\-detach\fR <ports>
+.IP
+Detach an imported USB device.
+.PP
+
+.HP
+\fB\-l\fR, \fB\-\-list\fR <hosts>
+.IP
+List exported USB devices.
+.PP
+
+.HP
+\fB\-p\fR, \fB\-\-port\fR
+.IP
+List virtual USB port status.
+.PP
+
+.HP
+\fB\-D\fR, \fB\-\-debug\fR
+.IP
+Print debugging information.
+.PP
+
+.HP
+\fB\-v\fR, \fB\-\-version\fR
+.IP
+Show version.
+.PP
+
+.SH EXAMPLES
+
+ client:# usbip --list server
+ - List exportable usb devices on the server.
+
+ client:# usbip --attach server 1-2
+ - Connect the remote USB device.
+
+ client:# usbip --port
+ - Show virtual port status.
+
+ client:# usbip --detach 0
+ - Detach the usb device.
+
+.SH "SEE ALSO"
+\fBusbipd\fP\fB(8)\fB\fP,
+\fBusbip_attach_driver\fP\fB(8)\fB\fP
diff --git a/drivers/staging/usbip/userspace/doc/usbip_bind_driver.8 b/drivers/staging/usbip/userspace/doc/usbip_bind_driver.8
new file mode 100644
index 0000000..d43bbd6
--- /dev/null
+++ b/drivers/staging/usbip/userspace/doc/usbip_bind_driver.8
@@ -0,0 +1,42 @@
+.TH USBIP_BIND_DRIVER "8" "February 2009" "usbip" "System Administration Utilities"
+.SH NAME
+usbip_bind_driver \- change driver binding for USB/IP
+
+.SH SYNOPSIS
+.B usbip_bind_driver
+[\fIoptions\fR]
+
+.SH DESCRIPTION
+Driver bindings for USB devices can be changed using
+this program. It is used to export and unexport USB
+devices over USB/IP.
+
+.SH OPTIONS
+.TP
+\fB\-u\fR, \fB\-\-usbip\fR <busid>
+Make a device exportable
+.TP
+\fB\-o\fR, \fB\-\-other\fR <busid>
+Use a device by a local driver
+.TP
+\fB\-l\fR, \fB\-\-list\fR
+Print usb devices and their drivers
+.TP
+\fB\-L\fR, \fB\-\-list2\fR
+Print usb devices and their drivers in parseable mode
+
+.SH EXAMPLES
+
+ server:# usbip_bind_driver --list
+ - List driver assignments for usb devices.
+
+ server:# usbip_bind_driver --usbip 1-2
+ - Bind usbip-host.ko to the device of busid 1-2.
+ - A usb device 1-2 is now exportable to other hosts!
+
+ server:# usbip_bind_driver --other 1-2
+ - Shutdown exporting and use the device locally.
+
+.SH "SEE ALSO"
+\fBusbip\fP\fB(8)\fB\fP,
+\fBusbipd\fP\fB(8)\fB\fP
diff --git a/drivers/staging/usbip/userspace/doc/usbipd.8 b/drivers/staging/usbip/userspace/doc/usbipd.8
new file mode 100644
index 0000000..006559f
--- /dev/null
+++ b/drivers/staging/usbip/userspace/doc/usbipd.8
@@ -0,0 +1,62 @@
+.TH USBIP "8" "February 2009" "usbip" "System Administration Utilities"
+.SH NAME
+usbipd \- USB/IP server daemon
+.SH SYNOPSIS
+.B usbipd
+[\fIoptions\fR]
+
+.SH DESCRIPTION
+.B usbipd
+provides USB/IP clients access to exported USB devices.
+
+Devices have to explicitly be exported using
+.B usbip_bind_driver
+before usbipd makes them available to other hosts.
+
+The daemon accepts connections from USB/IP clients
+on TCP port 3240.
+
+.SH OPTIONS
+.HP
+\fB\-D\fR, \fB\-\-daemon\fR
+.IP
+Run as a daemon process.
+.PP
+
+.HP
+\fB\-d\fR, \fB\-\-debug\fR
+.IP
+Print debugging information.
+.PP
+
+.HP
+\fB\-v\fR, \fB\-\-version\fR
+.IP
+Show version.
+.PP
+
+.SH LIMITATIONS
+
+.B usbipd
+offers no authentication or authorization for USB/IP. Any
+USB/IP client can connect and use exported devices.
+
+.SH EXAMPLES
+
+ server:# modprobe usbip
+
+ server:# usbipd -D
+ - Start usbip daemon.
+
+ server:# usbip_bind_driver --list
+ - List driver assignments for usb devices.
+
+ server:# usbip_bind_driver --usbip 1-2
+ - Bind usbip-host.ko to the device of busid 1-2.
+ - A usb device 1-2 is now exportable to other hosts!
+ - Use 'usbip_bind_driver --other 1-2' when you want to shutdown exporting and use the device locally.
+
+.SH "SEE ALSO"
+\fBusbip\fP\fB(8)\fB\fP,
+\fBusbip_attach_driver\fP\fB(8)\fB\fP
+
diff --git a/drivers/staging/usbip/userspace/libsrc/Makefile.am b/drivers/staging/usbip/userspace/libsrc/Makefile.am
new file mode 100644
index 0000000..77ecf6b
--- /dev/null
+++ b/drivers/staging/usbip/userspace/libsrc/Makefile.am
@@ -0,0 +1,7 @@
+libusbip_la_CPPFLAGS := -DUSBIDS_FILE='"@USBIDS_DIR@/usb.ids"'
+libusbip_la_CFLAGS := @EXTRA_CFLAGS@
+libusbip_la_LDFLAGS := -version-info @LIBUSBIP_VERSION@
+
+lib_LTLIBRARIES := libusbip.la
+libusbip_la_SOURCES := names.c names.h stub_driver.c stub_driver.h usbip.h \
+ usbip_common.c usbip_common.h vhci_driver.c vhci_driver.h
diff --git a/drivers/staging/usbip/userspace/libsrc/names.c b/drivers/staging/usbip/userspace/libsrc/names.c
new file mode 100644
index 0000000..b4de18b
--- /dev/null
+++ b/drivers/staging/usbip/userspace/libsrc/names.c
@@ -0,0 +1,793 @@
+/*****************************************************************************/
+/*
+ * names.c -- USB name database manipulation routines
+ *
+ * Copyright (C) 1999, 2000 Thomas Sailer (sailer@ife.ee.ethz.ch)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ */
+
+/*
+ * Copyright (C) 2005 Takahiro Hirofuchi
+ * - names_deinit() is added.
+ */
+
+/*****************************************************************************/
+
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <fcntl.h>
+#include <dirent.h>
+#include <string.h>
+#include <errno.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <stdio.h>
+#include <ctype.h>
+
+
+#include "names.h"
+
+
+/* ---------------------------------------------------------------------- */
+
+struct vendor {
+ struct vendor *next;
+ u_int16_t vendorid;
+ char name[1];
+};
+
+struct product {
+ struct product *next;
+ u_int16_t vendorid, productid;
+ char name[1];
+};
+
+struct class {
+ struct class *next;
+ u_int8_t classid;
+ char name[1];
+};
+
+struct subclass {
+ struct subclass *next;
+ u_int8_t classid, subclassid;
+ char name[1];
+};
+
+struct protocol {
+ struct protocol *next;
+ u_int8_t classid, subclassid, protocolid;
+ char name[1];
+};
+
+struct audioterminal {
+ struct audioterminal *next;
+ u_int16_t termt;
+ char name[1];
+};
+
+struct genericstrtable {
+ struct genericstrtable *next;
+ unsigned int num;
+ char name[1];
+};
+
+/* ---------------------------------------------------------------------- */
+
+#define HASH1 0x10
+#define HASH2 0x02
+#define HASHSZ 16
+
+static unsigned int hashnum(unsigned int num)
+{
+ unsigned int mask1 = HASH1 << 27, mask2 = HASH2 << 27;
+
+ for (; mask1 >= HASH1; mask1 >>= 1, mask2 >>= 1)
+ if (num & mask1)
+ num ^= mask2;
+ return num & (HASHSZ-1);
+}
+
+/* ---------------------------------------------------------------------- */
+
+static struct vendor *vendors[HASHSZ] = { NULL, };
+static struct product *products[HASHSZ] = { NULL, };
+static struct class *classes[HASHSZ] = { NULL, };
+static struct subclass *subclasses[HASHSZ] = { NULL, };
+static struct protocol *protocols[HASHSZ] = { NULL, };
+static struct audioterminal *audioterminals[HASHSZ] = { NULL, };
+static struct genericstrtable *hiddescriptors[HASHSZ] = { NULL, };
+static struct genericstrtable *reports[HASHSZ] = { NULL, };
+static struct genericstrtable *huts[HASHSZ] = { NULL, };
+static struct genericstrtable *biass[HASHSZ] = { NULL, };
+static struct genericstrtable *physdess[HASHSZ] = { NULL, };
+static struct genericstrtable *hutus[HASHSZ] = { NULL, };
+static struct genericstrtable *langids[HASHSZ] = { NULL, };
+static struct genericstrtable *countrycodes[HASHSZ] = { NULL, };
+
+/* ---------------------------------------------------------------------- */
+
+static const char *names_genericstrtable(struct genericstrtable *t[HASHSZ], unsigned int index)
+{
+ struct genericstrtable *h;
+
+ for (h = t[hashnum(index)]; h; h = h->next)
+ if (h->num == index)
+ return h->name;
+ return NULL;
+}
+
+const char *names_hid(u_int8_t hidd)
+{
+ return names_genericstrtable(hiddescriptors, hidd);
+}
+
+const char *names_reporttag(u_int8_t rt)
+{
+ return names_genericstrtable(reports, rt);
+}
+
+const char *names_huts(unsigned int data)
+{
+ return names_genericstrtable(huts, data);
+}
+
+const char *names_hutus(unsigned int data)
+{
+ return names_genericstrtable(hutus, data);
+}
+
+const char *names_langid(u_int16_t langid)
+{
+ return names_genericstrtable(langids, langid);
+}
+
+const char *names_physdes(u_int8_t ph)
+{
+ return names_genericstrtable(physdess, ph);
+}
+
+const char *names_bias(u_int8_t b)
+{
+ return names_genericstrtable(biass, b);
+}
+
+const char *names_countrycode(unsigned int countrycode)
+{
+ return names_genericstrtable(countrycodes, countrycode);
+}
+
+const char *names_vendor(u_int16_t vendorid)
+{
+ struct vendor *v;
+
+ v = vendors[hashnum(vendorid)];
+ for (; v; v = v->next)
+ if (v->vendorid == vendorid)
+ return v->name;
+ return NULL;
+}
+
+const char *names_product(u_int16_t vendorid, u_int16_t productid)
+{
+ struct product *p;
+
+ p = products[hashnum((vendorid << 16) | productid)];
+ for (; p; p = p->next)
+ if (p->vendorid == vendorid && p->productid == productid)
+ return p->name;
+ return NULL;
+}
+
+const char *names_class(u_int8_t classid)
+{
+ struct class *c;
+
+ c = classes[hashnum(classid)];
+ for (; c; c = c->next)
+ if (c->classid == classid)
+ return c->name;
+ return NULL;
+}
+
+const char *names_subclass(u_int8_t classid, u_int8_t subclassid)
+{
+ struct subclass *s;
+
+ s = subclasses[hashnum((classid << 8) | subclassid)];
+ for (; s; s = s->next)
+ if (s->classid == classid && s->subclassid == subclassid)
+ return s->name;
+ return NULL;
+}
+
+const char *names_protocol(u_int8_t classid, u_int8_t subclassid, u_int8_t protocolid)
+{
+ struct protocol *p;
+
+ p = protocols[hashnum((classid << 16) | (subclassid << 8) | protocolid)];
+ for (; p; p = p->next)
+ if (p->classid == classid && p->subclassid == subclassid && p->protocolid == protocolid)
+ return p->name;
+ return NULL;
+}
+
+const char *names_audioterminal(u_int16_t termt)
+{
+ struct audioterminal *at;
+
+ at = audioterminals[hashnum(termt)];
+ for (; at; at = at->next)
+ if (at->termt == termt)
+ return at->name;
+ return NULL;
+}
+
+/* ---------------------------------------------------------------------- */
+/* add a cleanup function by takahiro */
+
+struct pool {
+ struct pool *next;
+ void *mem;
+};
+
+static struct pool *pool_head = NULL;
+
+static void *my_malloc(size_t size)
+{
+ struct pool *p;
+
+ p = calloc(1, sizeof(struct pool));
+ if (!p) {
+ free(p);
+ return NULL;
+ }
+
+ p->mem = calloc(1, size);
+ if (!p->mem)
+ return NULL;
+
+ p->next = pool_head;
+ pool_head = p;
+
+ return p->mem;
+}
+
+void names_free(void)
+{
+ struct pool *pool;
+
+ if (!pool_head)
+ return;
+
+ for (pool = pool_head; pool != NULL; ) {
+ struct pool *tmp;
+
+ if (pool->mem)
+ free(pool->mem);
+
+ tmp = pool;
+ pool = pool->next;
+ free(tmp);
+ }
+}
+
+/* ---------------------------------------------------------------------- */
+
+static int new_vendor(const char *name, u_int16_t vendorid)
+{
+ struct vendor *v;
+ unsigned int h = hashnum(vendorid);
+
+ v = vendors[h];
+ for (; v; v = v->next)
+ if (v->vendorid == vendorid)
+ return -1;
+ v = my_malloc(sizeof(struct vendor) + strlen(name));
+ if (!v)
+ return -1;
+ strcpy(v->name, name);
+ v->vendorid = vendorid;
+ v->next = vendors[h];
+ vendors[h] = v;
+ return 0;
+}
+
+static int new_product(const char *name, u_int16_t vendorid, u_int16_t productid)
+{
+ struct product *p;
+ unsigned int h = hashnum((vendorid << 16) | productid);
+
+ p = products[h];
+ for (; p; p = p->next)
+ if (p->vendorid == vendorid && p->productid == productid)
+ return -1;
+ p = my_malloc(sizeof(struct product) + strlen(name));
+ if (!p)
+ return -1;
+ strcpy(p->name, name);
+ p->vendorid = vendorid;
+ p->productid = productid;
+ p->next = products[h];
+ products[h] = p;
+ return 0;
+}
+
+static int new_class(const char *name, u_int8_t classid)
+{
+ struct class *c;
+ unsigned int h = hashnum(classid);
+
+ c = classes[h];
+ for (; c; c = c->next)
+ if (c->classid == classid)
+ return -1;
+ c = my_malloc(sizeof(struct class) + strlen(name));
+ if (!c)
+ return -1;
+ strcpy(c->name, name);
+ c->classid = classid;
+ c->next = classes[h];
+ classes[h] = c;
+ return 0;
+}
+
+static int new_subclass(const char *name, u_int8_t classid, u_int8_t subclassid)
+{
+ struct subclass *s;
+ unsigned int h = hashnum((classid << 8) | subclassid);
+
+ s = subclasses[h];
+ for (; s; s = s->next)
+ if (s->classid == classid && s->subclassid == subclassid)
+ return -1;
+ s = my_malloc(sizeof(struct subclass) + strlen(name));
+ if (!s)
+ return -1;
+ strcpy(s->name, name);
+ s->classid = classid;
+ s->subclassid = subclassid;
+ s->next = subclasses[h];
+ subclasses[h] = s;
+ return 0;
+}
+
+static int new_protocol(const char *name, u_int8_t classid, u_int8_t subclassid, u_int8_t protocolid)
+{
+ struct protocol *p;
+ unsigned int h = hashnum((classid << 16) | (subclassid << 8) | protocolid);
+
+ p = protocols[h];
+ for (; p; p = p->next)
+ if (p->classid == classid && p->subclassid == subclassid && p->protocolid == protocolid)
+ return -1;
+ p = my_malloc(sizeof(struct protocol) + strlen(name));
+ if (!p)
+ return -1;
+ strcpy(p->name, name);
+ p->classid = classid;
+ p->subclassid = subclassid;
+ p->protocolid = protocolid;
+ p->next = protocols[h];
+ protocols[h] = p;
+ return 0;
+}
+
+static int new_audioterminal(const char *name, u_int16_t termt)
+{
+ struct audioterminal *at;
+ unsigned int h = hashnum(termt);
+
+ at = audioterminals[h];
+ for (; at; at = at->next)
+ if (at->termt == termt)
+ return -1;
+ at = my_malloc(sizeof(struct audioterminal) + strlen(name));
+ if (!at)
+ return -1;
+ strcpy(at->name, name);
+ at->termt = termt;
+ at->next = audioterminals[h];
+ audioterminals[h] = at;
+ return 0;
+}
+
+static int new_genericstrtable(struct genericstrtable *t[HASHSZ], const char *name, unsigned int index)
+{
+ struct genericstrtable *g;
+ unsigned int h = hashnum(index);
+
+ for (g = t[h]; g; g = g->next)
+ if (g->num == index)
+ return -1;
+ g = my_malloc(sizeof(struct genericstrtable) + strlen(name));
+ if (!g)
+ return -1;
+ strcpy(g->name, name);
+ g->num = index;
+ g->next = t[h];
+ t[h] = g;
+ return 0;
+}
+
+static int new_hid(const char *name, u_int8_t hidd)
+{
+ return new_genericstrtable(hiddescriptors, name, hidd);
+}
+
+static int new_reporttag(const char *name, u_int8_t rt)
+{
+ return new_genericstrtable(reports, name, rt);
+}
+
+static int new_huts(const char *name, unsigned int data)
+{
+ return new_genericstrtable(huts, name, data);
+}
+
+static int new_hutus(const char *name, unsigned int data)
+{
+ return new_genericstrtable(hutus, name, data);
+}
+
+static int new_langid(const char *name, u_int16_t langid)
+{
+ return new_genericstrtable(langids, name, langid);
+}
+
+static int new_physdes(const char *name, u_int8_t ph)
+{
+ return new_genericstrtable(physdess, name, ph);
+}
+static int new_bias(const char *name, u_int8_t b)
+{
+ return new_genericstrtable(biass, name, b);
+}
+
+static int new_countrycode(const char *name, unsigned int countrycode)
+{
+ return new_genericstrtable(countrycodes, name, countrycode);
+}
+
+/* ---------------------------------------------------------------------- */
+
+#define DBG(x)
+
+static void parse(FILE *f)
+{
+ char buf[512], *cp;
+ unsigned int linectr = 0;
+ int lastvendor = -1, lastclass = -1, lastsubclass = -1, lasthut=-1, lastlang=-1;
+ unsigned int u;
+
+ while (fgets(buf, sizeof(buf), f)) {
+ linectr++;
+ /* remove line ends */
+ if ((cp = strchr(buf, 13)))
+ *cp = 0;
+ if ((cp = strchr(buf, 10)))
+ *cp = 0;
+ if (buf[0] == '#' || !buf[0])
+ continue;
+ cp = buf;
+ if (buf[0] == 'P' && buf[1] == 'H' && buf[2] == 'Y' && buf[3] == 'S' && buf[4] == 'D' &&
+ buf[5] == 'E' && buf[6] == 'S' && /*isspace(buf[7])*/ buf[7] == ' ') {
+ cp = buf + 8;
+ while (isspace(*cp))
+ cp++;
+ if (!isxdigit(*cp)) {
+ fprintf(stderr, "Invalid Physdes type at line %u\n", linectr);
+ continue;
+ }
+ u = strtoul(cp, &cp, 16);
+ while (isspace(*cp))
+ cp++;
+ if (!*cp) {
+ fprintf(stderr, "Invalid Physdes type at line %u\n", linectr);
+ continue;
+ }
+ if (new_physdes(cp, u))
+ fprintf(stderr, "Duplicate Physdes type spec at line %u terminal type %04x %s\n", linectr, u, cp);
+ DBG(printf("line %5u physdes type %02x %s\n", linectr, u, cp));
+ continue;
+
+ }
+ if (buf[0] == 'P' && buf[1] == 'H' && buf[2] == 'Y' && /*isspace(buf[3])*/ buf[3] == ' ') {
+ cp = buf + 4;
+ while (isspace(*cp))
+ cp++;
+ if (!isxdigit(*cp)) {
+ fprintf(stderr, "Invalid PHY type at line %u\n", linectr);
+ continue;
+ }
+ u = strtoul(cp, &cp, 16);
+ while (isspace(*cp))
+ cp++;
+ if (!*cp) {
+ fprintf(stderr, "Invalid PHY type at line %u\n", linectr);
+ continue;
+ }
+ if (new_physdes(cp, u))
+ fprintf(stderr, "Duplicate PHY type spec at line %u terminal type %04x %s\n", linectr, u, cp);
+ DBG(printf("line %5u PHY type %02x %s\n", linectr, u, cp));
+ continue;
+
+ }
+ if (buf[0] == 'B' && buf[1] == 'I' && buf[2] == 'A' && buf[3] == 'S' && /*isspace(buf[4])*/ buf[4] == ' ') {
+ cp = buf + 5;
+ while (isspace(*cp))
+ cp++;
+ if (!isxdigit(*cp)) {
+ fprintf(stderr, "Invalid BIAS type at line %u\n", linectr);
+ continue;
+ }
+ u = strtoul(cp, &cp, 16);
+ while (isspace(*cp))
+ cp++;
+ if (!*cp) {
+ fprintf(stderr, "Invalid BIAS type at line %u\n", linectr);
+ continue;
+ }
+ if (new_bias(cp, u))
+ fprintf(stderr, "Duplicate BIAS type spec at line %u terminal type %04x %s\n", linectr, u, cp);
+ DBG(printf("line %5u BIAS type %02x %s\n", linectr, u, cp));
+ continue;
+
+ }
+ if (buf[0] == 'L' && /*isspace(buf[1])*/ buf[1] == ' ') {
+ cp = buf+2;
+ while (isspace(*cp))
+ cp++;
+ if (!isxdigit(*cp)) {
+ fprintf(stderr, "Invalid LANGID spec at line %u\n", linectr);
+ continue;
+ }
+ u = strtoul(cp, &cp, 16);
+ while (isspace(*cp))
+ cp++;
+ if (!*cp) {
+ fprintf(stderr, "Invalid LANGID spec at line %u\n", linectr);
+ continue;
+ }
+ if (new_langid(cp, u))
+ fprintf(stderr, "Duplicate LANGID spec at line %u language-id %04x %s\n", linectr, u, cp);
+ DBG(printf("line %5u LANGID %02x %s\n", linectr, u, cp));
+ lasthut = lastclass = lastvendor = lastsubclass = -1;
+ lastlang = u;
+ continue;
+ }
+ if (buf[0] == 'C' && /*isspace(buf[1])*/ buf[1] == ' ') {
+ /* class spec */
+ cp = buf+2;
+ while (isspace(*cp))
+ cp++;
+ if (!isxdigit(*cp)) {
+ fprintf(stderr, "Invalid class spec at line %u\n", linectr);
+ continue;
+ }
+ u = strtoul(cp, &cp, 16);
+ while (isspace(*cp))
+ cp++;
+ if (!*cp) {
+ fprintf(stderr, "Invalid class spec at line %u\n", linectr);
+ continue;
+ }
+ if (new_class(cp, u))
+ fprintf(stderr, "Duplicate class spec at line %u class %04x %s\n", linectr, u, cp);
+ DBG(printf("line %5u class %02x %s\n", linectr, u, cp));
+ lasthut = lastlang = lastvendor = lastsubclass = -1;
+ lastclass = u;
+ continue;
+ }
+ if (buf[0] == 'A' && buf[1] == 'T' && isspace(buf[2])) {
+ /* audio terminal type spec */
+ cp = buf+3;
+ while (isspace(*cp))
+ cp++;
+ if (!isxdigit(*cp)) {
+ fprintf(stderr, "Invalid audio terminal type at line %u\n", linectr);
+ continue;
+ }
+ u = strtoul(cp, &cp, 16);
+ while (isspace(*cp))
+ cp++;
+ if (!*cp) {
+ fprintf(stderr, "Invalid audio terminal type at line %u\n", linectr);
+ continue;
+ }
+ if (new_audioterminal(cp, u))
+ fprintf(stderr, "Duplicate audio terminal type spec at line %u terminal type %04x %s\n", linectr, u, cp);
+ DBG(printf("line %5u audio terminal type %02x %s\n", linectr, u, cp));
+ continue;
+ }
+ if (buf[0] == 'H' && buf[1] == 'C' && buf[2] == 'C' && isspace(buf[3])) {
+ /* HID Descriptor bCountryCode */
+ cp = buf+3;
+ while (isspace(*cp))
+ cp++;
+ if (!isxdigit(*cp)) {
+ fprintf(stderr, "Invalid HID country code at line %u\n", linectr);
+ continue;
+ }
+ u = strtoul(cp, &cp, 10);
+ while (isspace(*cp))
+ cp++;
+ if (!*cp) {
+ fprintf(stderr, "Invalid HID country code at line %u\n", linectr);
+ continue;
+ }
+ if (new_countrycode(cp, u))
+ fprintf(stderr, "Duplicate HID country code at line %u country %02u %s\n", linectr, u, cp);
+ DBG(printf("line %5u keyboard country code %02u %s\n", linectr, u, cp));
+ continue;
+ }
+ if (isxdigit(*cp)) {
+ /* vendor */
+ u = strtoul(cp, &cp, 16);
+ while (isspace(*cp))
+ cp++;
+ if (!*cp) {
+ fprintf(stderr, "Invalid vendor spec at line %u\n", linectr);
+ continue;
+ }
+ if (new_vendor(cp, u))
+ fprintf(stderr, "Duplicate vendor spec at line %u vendor %04x %s\n", linectr, u, cp);
+ DBG(printf("line %5u vendor %04x %s\n", linectr, u, cp));
+ lastvendor = u;
+ lasthut = lastlang = lastclass = lastsubclass = -1;
+ continue;
+ }
+ if (buf[0] == '\t' && isxdigit(buf[1])) {
+ /* product or subclass spec */
+ u = strtoul(buf+1, &cp, 16);
+ while (isspace(*cp))
+ cp++;
+ if (!*cp) {
+ fprintf(stderr, "Invalid product/subclass spec at line %u\n", linectr);
+ continue;
+ }
+ if (lastvendor != -1) {
+ if (new_product(cp, lastvendor, u))
+ fprintf(stderr, "Duplicate product spec at line %u product %04x:%04x %s\n", linectr, lastvendor, u, cp);
+ DBG(printf("line %5u product %04x:%04x %s\n", linectr, lastvendor, u, cp));
+ continue;
+ }
+ if (lastclass != -1) {
+ if (new_subclass(cp, lastclass, u))
+ fprintf(stderr, "Duplicate subclass spec at line %u class %02x:%02x %s\n", linectr, lastclass, u, cp);
+ DBG(printf("line %5u subclass %02x:%02x %s\n", linectr, lastclass, u, cp));
+ lastsubclass = u;
+ continue;
+ }
+ if (lasthut != -1) {
+ if (new_hutus(cp, (lasthut << 16)+u))
+ fprintf(stderr, "Duplicate HUT Usage Spec at line %u\n", linectr);
+ continue;
+ }
+ if (lastlang != -1) {
+ if (new_langid(cp, lastlang+(u<<10)))
+ fprintf(stderr, "Duplicate LANGID Usage Spec at line %u\n", linectr);
+ continue;
+ }
+ fprintf(stderr, "Product/Subclass spec without prior Vendor/Class spec at line %u\n", linectr);
+ continue;
+ }
+ if (buf[0] == '\t' && buf[1] == '\t' && isxdigit(buf[2])) {
+ /* protocol spec */
+ u = strtoul(buf+2, &cp, 16);
+ while (isspace(*cp))
+ cp++;
+ if (!*cp) {
+ fprintf(stderr, "Invalid protocol spec at line %u\n", linectr);
+ continue;
+ }
+ if (lastclass != -1 && lastsubclass != -1) {
+ if (new_protocol(cp, lastclass, lastsubclass, u))
+ fprintf(stderr, "Duplicate protocol spec at line %u class %02x:%02x:%02x %s\n", linectr, lastclass, lastsubclass, u, cp);
+ DBG(printf("line %5u protocol %02x:%02x:%02x %s\n", linectr, lastclass, lastsubclass, u, cp));
+ continue;
+ }
+ fprintf(stderr, "Protocol spec without prior Class and Subclass spec at line %u\n", linectr);
+ continue;
+ }
+ if (buf[0] == 'H' && buf[1] == 'I' && buf[2] == 'D' && /*isspace(buf[3])*/ buf[3] == ' ') {
+ cp = buf + 4;
+ while (isspace(*cp))
+ cp++;
+ if (!isxdigit(*cp)) {
+ fprintf(stderr, "Invalid HID type at line %u\n", linectr);
+ continue;
+ }
+ u = strtoul(cp, &cp, 16);
+ while (isspace(*cp))
+ cp++;
+ if (!*cp) {
+ fprintf(stderr, "Invalid HID type at line %u\n", linectr);
+ continue;
+ }
+ if (new_hid(cp, u))
+ fprintf(stderr, "Duplicate HID type spec at line %u terminal type %04x %s\n", linectr, u, cp);
+ DBG(printf("line %5u HID type %02x %s\n", linectr, u, cp));
+ continue;
+
+ }
+ if (buf[0] == 'H' && buf[1] == 'U' && buf[2] == 'T' && /*isspace(buf[3])*/ buf[3] == ' ') {
+ cp = buf + 4;
+ while (isspace(*cp))
+ cp++;
+ if (!isxdigit(*cp)) {
+ fprintf(stderr, "Invalid HUT type at line %u\n", linectr);
+ continue;
+ }
+ u = strtoul(cp, &cp, 16);
+ while (isspace(*cp))
+ cp++;
+ if (!*cp) {
+ fprintf(stderr, "Invalid HUT type at line %u\n", linectr);
+ continue;
+ }
+ if (new_huts(cp, u))
+ fprintf(stderr, "Duplicate HUT type spec at line %u terminal type %04x %s\n", linectr, u, cp);
+ lastlang = lastclass = lastvendor = lastsubclass = -1;
+ lasthut = u;
+ DBG(printf("line %5u HUT type %02x %s\n", linectr, u, cp));
+ continue;
+
+ }
+ if (buf[0] == 'R' && buf[1] == ' ') {
+ cp = buf + 2;
+ while (isspace(*cp))
+ cp++;
+ if (!isxdigit(*cp)) {
+ fprintf(stderr, "Invalid Report type at line %u\n", linectr);
+ continue;
+ }
+ u = strtoul(cp, &cp, 16);
+ while (isspace(*cp))
+ cp++;
+ if (!*cp) {
+ fprintf(stderr, "Invalid Report type at line %u\n", linectr);
+ continue;
+ }
+ if (new_reporttag(cp, u))
+ fprintf(stderr, "Duplicate Report type spec at line %u terminal type %04x %s\n", linectr, u, cp);
+ DBG(printf("line %5u Report type %02x %s\n", linectr, u, cp));
+ continue;
+
+ }
+ if (buf[0] == 'V' && buf[1] == 'T') {
+ /* add here */
+ continue;
+ }
+ fprintf(stderr, "Unknown line at line %u\n", linectr);
+ }
+}
+
+/* ---------------------------------------------------------------------- */
+
+int names_init(char *n)
+{
+ FILE *f;
+
+ if (!(f = fopen(n, "r"))) {
+ return errno;
+ }
+ parse(f);
+ fclose(f);
+ return 0;
+}
diff --git a/drivers/staging/usbip/userspace/libsrc/names.h b/drivers/staging/usbip/userspace/libsrc/names.h
new file mode 100644
index 0000000..3a269fe
--- /dev/null
+++ b/drivers/staging/usbip/userspace/libsrc/names.h
@@ -0,0 +1,57 @@
+/*****************************************************************************/
+
+/*
+ * names.h -- USB name database manipulation routines
+ *
+ * Copyright (C) 1999, 2000 Thomas Sailer (sailer@ife.ee.ethz.ch)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ *
+ */
+
+/*
+ * Copyright (C) 2005 Takahiro Hirofuchi
+ * - names_free() is added.
+ */
+
+/*****************************************************************************/
+
+#ifndef _NAMES_H
+#define _NAMES_H
+
+#include <sys/types.h>
+
+/* ---------------------------------------------------------------------- */
+
+extern const char *names_vendor(u_int16_t vendorid);
+extern const char *names_product(u_int16_t vendorid, u_int16_t productid);
+extern const char *names_class(u_int8_t classid);
+extern const char *names_subclass(u_int8_t classid, u_int8_t subclassid);
+extern const char *names_protocol(u_int8_t classid, u_int8_t subclassid, u_int8_t protocolid);
+extern const char *names_audioterminal(u_int16_t termt);
+extern const char *names_hid(u_int8_t hidd);
+extern const char *names_reporttag(u_int8_t rt);
+extern const char *names_huts(unsigned int data);
+extern const char *names_hutus(unsigned int data);
+extern const char *names_langid(u_int16_t langid);
+extern const char *names_physdes(u_int8_t ph);
+extern const char *names_bias(u_int8_t b);
+extern const char *names_countrycode(unsigned int countrycode);
+extern int names_init(char *n);
+extern void names_free(void);
+
+/* ---------------------------------------------------------------------- */
+#endif /* _NAMES_H */
diff --git a/drivers/staging/usbip/userspace/libsrc/stub_driver.c b/drivers/staging/usbip/userspace/libsrc/stub_driver.c
new file mode 100644
index 0000000..cc33643
--- /dev/null
+++ b/drivers/staging/usbip/userspace/libsrc/stub_driver.c
@@ -0,0 +1,391 @@
+/*
+ * Copyright (C) 2005-2007 Takahiro Hirofuchi
+ */
+
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <unistd.h>
+
+#include "usbip.h"
+
+/* kernel module name */
+static const char *usbip_stub_driver_name = "usbip-host";
+
+
+struct usbip_stub_driver *stub_driver;
+
+static struct sysfs_driver *open_sysfs_stub_driver(void)
+{
+ int ret;
+
+ char sysfs_mntpath[SYSFS_PATH_MAX];
+ char stub_driver_path[SYSFS_PATH_MAX];
+ struct sysfs_driver *stub_driver;
+
+
+ ret = sysfs_get_mnt_path(sysfs_mntpath, SYSFS_PATH_MAX);
+ if (ret < 0) {
+ err("sysfs must be mounted");
+ return NULL;
+ }
+
+ snprintf(stub_driver_path, SYSFS_PATH_MAX, "%s/%s/usb/%s/%s",
+ sysfs_mntpath, SYSFS_BUS_NAME, SYSFS_DRIVERS_NAME,
+ usbip_stub_driver_name);
+
+ stub_driver = sysfs_open_driver_path(stub_driver_path);
+ if (!stub_driver) {
+ err("usbip-core.ko and usbip-host.ko must be loaded");
+ return NULL;
+ }
+
+ return stub_driver;
+}
+
+
+#define SYSFS_OPEN_RETRIES 100
+
+/* only the first interface value is true! */
+static int32_t read_attr_usbip_status(struct usb_device *udev)
+{
+ char attrpath[SYSFS_PATH_MAX];
+ struct sysfs_attribute *attr;
+ int value = 0;
+ int ret;
+ struct stat s;
+ int retries = SYSFS_OPEN_RETRIES;
+
+ /* This access is racy!
+ *
+ * Just after detach, our driver removes the sysfs
+ * files and recreates them.
+ *
+ * We may try and fail to open the usbip_status of
+ * an exported device in the (short) window where
+ * it has been removed and not yet recreated.
+ *
+ * This is a bug in the interface. Nothing we can do
+ * except work around it here by polling for the sysfs
+ * usbip_status to reappear.
+ */
+
+ snprintf(attrpath, SYSFS_PATH_MAX, "%s/%s:%d.%d/usbip_status",
+ udev->path, udev->busid,
+ udev->bConfigurationValue,
+ 0);
+
+ while (retries > 0) {
+ if (stat(attrpath, &s) == 0)
+ break;
+
+ if (errno != ENOENT) {
+ err("error stat'ing %s", attrpath);
+ return -1;
+ }
+
+ usleep(10000); /* 10ms */
+ retries--;
+ }
+
+ if (retries == 0)
+ err("usbip_status not ready after %d retries",
+ SYSFS_OPEN_RETRIES);
+ else if (retries < SYSFS_OPEN_RETRIES)
+ info("warning: usbip_status ready after %d retries",
+ SYSFS_OPEN_RETRIES - retries);
+
+ attr = sysfs_open_attribute(attrpath);
+ if (!attr) {
+ err("open %s", attrpath);
+ return -1;
+ }
+
+ ret = sysfs_read_attribute(attr);
+ if (ret) {
+ err("read %s", attrpath);
+ sysfs_close_attribute(attr);
+ return -1;
+ }
+
+ value = atoi(attr->value);
+
+ sysfs_close_attribute(attr);
+
+ return value;
+}
+
+
+static void usbip_exported_device_delete(void *dev)
+{
+ struct usbip_exported_device *edev =
+ (struct usbip_exported_device *) dev;
+
+ sysfs_close_device(edev->sudev);
+ free(dev);
+}
+
+
+static struct usbip_exported_device *usbip_exported_device_new(char *sdevpath)
+{
+ struct usbip_exported_device *edev = NULL;
+
+ edev = (struct usbip_exported_device *) calloc(1, sizeof(*edev));
+ if (!edev) {
+ err("alloc device");
+ return NULL;
+ }
+
+ edev->sudev = sysfs_open_device_path(sdevpath);
+ if (!edev->sudev) {
+ err("open %s", sdevpath);
+ goto err;
+ }
+
+ read_usb_device(edev->sudev, &edev->udev);
+
+ edev->status = read_attr_usbip_status(&edev->udev);
+ if (edev->status < 0)
+ goto err;
+
+ /* reallocate buffer to include usb interface data */
+ size_t size = sizeof(*edev) + edev->udev.bNumInterfaces * sizeof(struct usb_interface);
+ edev = (struct usbip_exported_device *) realloc(edev, size);
+ if (!edev) {
+ err("alloc device");
+ goto err;
+ }
+
+ for (int i=0; i < edev->udev.bNumInterfaces; i++)
+ read_usb_interface(&edev->udev, i, &edev->uinf[i]);
+
+ return edev;
+
+err:
+ if (edev && edev->sudev)
+ sysfs_close_device(edev->sudev);
+ if (edev)
+ free(edev);
+ return NULL;
+}
+
+
+static int check_new(struct dlist *dlist, struct sysfs_device *target)
+{
+ struct sysfs_device *dev;
+
+ dlist_for_each_data(dlist, dev, struct sysfs_device) {
+ if (!strncmp(dev->bus_id, target->bus_id, SYSFS_BUS_ID_SIZE))
+ /* found. not new */
+ return 0;
+ }
+
+ return 1;
+}
+
+static void delete_nothing(void *dev __attribute__((unused)))
+{
+ /* do not delete anything. but, its container will be deleted. */
+}
+
+static int refresh_exported_devices(void)
+{
+ struct sysfs_device *suinf; /* sysfs_device of usb_interface */
+ struct dlist *suinf_list;
+
+ struct sysfs_device *sudev; /* sysfs_device of usb_device */
+ struct dlist *sudev_list;
+
+
+ sudev_list = dlist_new_with_delete(sizeof(struct sysfs_device), delete_nothing);
+
+ suinf_list = sysfs_get_driver_devices(stub_driver->sysfs_driver);
+ if (!suinf_list) {
+ printf("Bind usbip-host.ko to a usb device to be exportable!\n");
+ goto bye;
+ }
+
+ /* collect unique USB devices (not interfaces) */
+ dlist_for_each_data(suinf_list, suinf, struct sysfs_device) {
+
+ /* get usb device of this usb interface */
+ sudev = sysfs_get_device_parent(suinf);
+ if (!sudev) {
+ err("get parent dev of %s", suinf->name);
+ continue;
+ }
+
+ if (check_new(sudev_list, sudev)) {
+ dlist_unshift(sudev_list, sudev);
+ }
+ }
+
+ dlist_for_each_data(sudev_list, sudev, struct sysfs_device) {
+ struct usbip_exported_device *edev;
+
+ edev = usbip_exported_device_new(sudev->path);
+ if (!edev) {
+ err("usbip_exported_device new");
+ continue;
+ }
+
+ dlist_unshift(stub_driver->edev_list, (void *) edev);
+ stub_driver->ndevs++;
+ }
+
+
+ dlist_destroy(sudev_list);
+
+bye:
+
+ return 0;
+}
+
+int usbip_stub_refresh_device_list(void)
+{
+ int ret;
+
+ if (stub_driver->edev_list)
+ dlist_destroy(stub_driver->edev_list);
+
+ stub_driver->ndevs = 0;
+
+ stub_driver->edev_list = dlist_new_with_delete(sizeof(struct usbip_exported_device),
+ usbip_exported_device_delete);
+ if (!stub_driver->edev_list) {
+ err("alloc dlist");
+ return -1;
+ }
+
+ ret = refresh_exported_devices();
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+int usbip_stub_driver_open(void)
+{
+ int ret;
+
+
+ stub_driver = (struct usbip_stub_driver *) calloc(1, sizeof(*stub_driver));
+ if (!stub_driver) {
+ err("alloc stub_driver");
+ return -1;
+ }
+
+ stub_driver->ndevs = 0;
+
+ stub_driver->edev_list = dlist_new_with_delete(sizeof(struct usbip_exported_device),
+ usbip_exported_device_delete);
+ if (!stub_driver->edev_list) {
+ err("alloc dlist");
+ goto err;
+ }
+
+ stub_driver->sysfs_driver = open_sysfs_stub_driver();
+ if (!stub_driver->sysfs_driver)
+ goto err;
+
+ ret = refresh_exported_devices();
+ if (ret < 0)
+ goto err;
+
+ return 0;
+
+
+err:
+ if (stub_driver->sysfs_driver)
+ sysfs_close_driver(stub_driver->sysfs_driver);
+ if (stub_driver->edev_list)
+ dlist_destroy(stub_driver->edev_list);
+ free(stub_driver);
+
+ stub_driver = NULL;
+ return -1;
+}
+
+
+void usbip_stub_driver_close(void)
+{
+ if (!stub_driver)
+ return;
+
+ if (stub_driver->edev_list)
+ dlist_destroy(stub_driver->edev_list);
+ if (stub_driver->sysfs_driver)
+ sysfs_close_driver(stub_driver->sysfs_driver);
+ free(stub_driver);
+
+ stub_driver = NULL;
+}
+
+int usbip_stub_export_device(struct usbip_exported_device *edev, int sockfd)
+{
+ char attrpath[SYSFS_PATH_MAX];
+ struct sysfs_attribute *attr;
+ char sockfd_buff[30];
+ int ret;
+
+
+ if (edev->status != SDEV_ST_AVAILABLE) {
+ info("device not available, %s", edev->udev.busid);
+ switch( edev->status ) {
+ case SDEV_ST_ERROR:
+ info(" status SDEV_ST_ERROR");
+ break;
+ case SDEV_ST_USED:
+ info(" status SDEV_ST_USED");
+ break;
+ default:
+ info(" status unknown: 0x%x", edev->status);
+ }
+ return -1;
+ }
+
+ /* only the first interface is true */
+ snprintf(attrpath, sizeof(attrpath), "%s/%s:%d.%d/%s",
+ edev->udev.path,
+ edev->udev.busid,
+ edev->udev.bConfigurationValue, 0,
+ "usbip_sockfd");
+
+ attr = sysfs_open_attribute(attrpath);
+ if (!attr) {
+ err("open %s", attrpath);
+ return -1;
+ }
+
+ snprintf(sockfd_buff, sizeof(sockfd_buff), "%d\n", sockfd);
+
+ dbg("write: %s", sockfd_buff);
+
+ ret = sysfs_write_attribute(attr, sockfd_buff, strlen(sockfd_buff));
+ if (ret < 0) {
+ err("write sockfd %s to %s", sockfd_buff, attrpath);
+ goto err_write_sockfd;
+ }
+
+ info("connect %s", edev->udev.busid);
+
+err_write_sockfd:
+ sysfs_close_attribute(attr);
+
+ return ret;
+}
+
+struct usbip_exported_device *usbip_stub_get_device(int num)
+{
+ struct usbip_exported_device *edev;
+ struct dlist *dlist = stub_driver->edev_list;
+ int count = 0;
+
+ dlist_for_each_data(dlist, edev, struct usbip_exported_device) {
+ if (num == count)
+ return edev;
+ else
+ count++ ;
+ }
+
+ return NULL;
+}
diff --git a/drivers/staging/usbip/userspace/libsrc/stub_driver.h b/drivers/staging/usbip/userspace/libsrc/stub_driver.h
new file mode 100644
index 0000000..3107d18
--- /dev/null
+++ b/drivers/staging/usbip/userspace/libsrc/stub_driver.h
@@ -0,0 +1,36 @@
+/*
+ * Copyright (C) 2005-2007 Takahiro Hirofuchi
+ */
+
+#ifndef _USBIP_STUB_DRIVER_H
+#define _USBIP_STUB_DRIVER_H
+
+#include "usbip.h"
+
+
+struct usbip_stub_driver {
+ int ndevs;
+ struct sysfs_driver *sysfs_driver;
+
+ struct dlist *edev_list; /* list of exported device */
+};
+
+struct usbip_exported_device {
+ struct sysfs_device *sudev;
+
+ int32_t status;
+ struct usb_device udev;
+ struct usb_interface uinf[];
+};
+
+
+extern struct usbip_stub_driver *stub_driver;
+
+int usbip_stub_driver_open(void);
+void usbip_stub_driver_close(void);
+
+int usbip_stub_refresh_device_list(void);
+int usbip_stub_export_device(struct usbip_exported_device *edev, int sockfd);
+
+struct usbip_exported_device *usbip_stub_get_device(int num);
+#endif
diff --git a/drivers/staging/usbip/userspace/libsrc/usbip.h b/drivers/staging/usbip/userspace/libsrc/usbip.h
new file mode 100644
index 0000000..7cb8e6f
--- /dev/null
+++ b/drivers/staging/usbip/userspace/libsrc/usbip.h
@@ -0,0 +1,19 @@
+/*
+ * Copyright (C) 2005-2007 Takahiro Hirofuchi
+ */
+
+#ifndef _USBIP_H
+#define _USBIP_H
+
+#ifdef HAVE_CONFIG_H
+#include "../config.h"
+#endif
+
+#include "usbip_common.h"
+#include "stub_driver.h"
+#include "vhci_driver.h"
+#ifdef DMALLOC
+#include <dmalloc.h>
+#endif
+
+#endif
diff --git a/drivers/staging/usbip/userspace/libsrc/usbip_common.c b/drivers/staging/usbip/userspace/libsrc/usbip_common.c
new file mode 100644
index 0000000..a128a92
--- /dev/null
+++ b/drivers/staging/usbip/userspace/libsrc/usbip_common.c
@@ -0,0 +1,282 @@
+/*
+ * Copyright (C) 2005-2007 Takahiro Hirofuchi
+ */
+
+#include "usbip.h"
+#include "names.h"
+
+int usbip_use_syslog = 0;
+int usbip_use_stderr = 0;
+int usbip_use_debug = 0;
+
+struct speed_string {
+ int num;
+ char *speed;
+ char *desc;
+};
+
+static const struct speed_string speed_strings[] = {
+ { USB_SPEED_UNKNOWN, "unknown", "Unknown Speed"},
+ { USB_SPEED_LOW, "1.5", "Low Speed(1.5Mbps)" },
+ { USB_SPEED_FULL, "12", "Full Speed(12Mbps)" },
+ { USB_SPEED_HIGH, "480", "High Speed(480Mbps)" },
+ { 0, NULL, NULL }
+};
+
+struct portst_string {
+ int num;
+ char *desc;
+};
+
+static struct portst_string portst_strings[] = {
+ { SDEV_ST_AVAILABLE, "Device Available" },
+ { SDEV_ST_USED, "Device in Use" },
+ { SDEV_ST_ERROR, "Device Error"},
+ { VDEV_ST_NULL, "Port Available"},
+ { VDEV_ST_NOTASSIGNED, "Port Initializing"},
+ { VDEV_ST_USED, "Port in Use"},
+ { VDEV_ST_ERROR, "Port Error"},
+ { 0, NULL}
+};
+
+const char *usbip_status_string(int32_t status)
+{
+ for (int i=0; portst_strings[i].desc != NULL; i++)
+ if (portst_strings[i].num == status)
+ return portst_strings[i].desc;
+
+ return "Unknown Status";
+}
+
+const char *usbip_speed_string(int num)
+{
+ for (int i=0; speed_strings[i].speed != NULL; i++)
+ if (speed_strings[i].num == num)
+ return speed_strings[i].desc;
+
+ return "Unknown Speed";
+}
+
+
+#define DBG_UDEV_INTEGER(name)\
+ dbg("%-20s = %x", to_string(name), (int) udev->name)
+
+#define DBG_UINF_INTEGER(name)\
+ dbg("%-20s = %x", to_string(name), (int) uinf->name)
+
+void dump_usb_interface(struct usb_interface *uinf)
+{
+ char buff[100];
+ usbip_names_get_class(buff, sizeof(buff),
+ uinf->bInterfaceClass,
+ uinf->bInterfaceSubClass,
+ uinf->bInterfaceProtocol);
+ dbg("%-20s = %s", "Interface(C/SC/P)", buff);
+}
+
+void dump_usb_device(struct usb_device *udev)
+{
+ char buff[100];
+
+
+ dbg("%-20s = %s", "path", udev->path);
+ dbg("%-20s = %s", "busid", udev->busid);
+
+ usbip_names_get_class(buff, sizeof(buff),
+ udev->bDeviceClass,
+ udev->bDeviceSubClass,
+ udev->bDeviceProtocol);
+ dbg("%-20s = %s", "Device(C/SC/P)", buff);
+
+ DBG_UDEV_INTEGER(bcdDevice);
+
+ usbip_names_get_product(buff, sizeof(buff),
+ udev->idVendor,
+ udev->idProduct);
+ dbg("%-20s = %s", "Vendor/Product", buff);
+
+ DBG_UDEV_INTEGER(bNumConfigurations);
+ DBG_UDEV_INTEGER(bNumInterfaces);
+
+ dbg("%-20s = %s", "speed",
+ usbip_speed_string(udev->speed));
+
+ DBG_UDEV_INTEGER(busnum);
+ DBG_UDEV_INTEGER(devnum);
+}
+
+
+int read_attr_value(struct sysfs_device *dev, const char *name, const char *format)
+{
+ char attrpath[SYSFS_PATH_MAX];
+ struct sysfs_attribute *attr;
+ int num = 0;
+ int ret;
+
+ snprintf(attrpath, sizeof(attrpath), "%s/%s", dev->path, name);
+
+ attr = sysfs_open_attribute(attrpath);
+ if (!attr) {
+ err("open attr %s", attrpath);
+ return 0;
+ }
+
+ ret = sysfs_read_attribute(attr);
+ if (ret < 0) {
+ err("read attr");
+ goto err;
+ }
+
+ ret = sscanf(attr->value, format, &num);
+ if (ret < 1) {
+ err("sscanf");
+ goto err;
+ }
+
+err:
+ sysfs_close_attribute(attr);
+
+ return num;
+}
+
+
+int read_attr_speed(struct sysfs_device *dev)
+{
+ char attrpath[SYSFS_PATH_MAX];
+ struct sysfs_attribute *attr;
+ char speed[100];
+ int ret;
+
+ snprintf(attrpath, sizeof(attrpath), "%s/%s", dev->path, "speed");
+
+ attr = sysfs_open_attribute(attrpath);
+ if (!attr) {
+ err("open attr");
+ return 0;
+ }
+
+ ret = sysfs_read_attribute(attr);
+ if (ret < 0) {
+ err("read attr");
+ goto err;
+ }
+
+ ret = sscanf(attr->value, "%s\n", speed);
+ if (ret < 1) {
+ err("sscanf");
+ goto err;
+ }
+err:
+ sysfs_close_attribute(attr);
+
+ for (int i=0; speed_strings[i].speed != NULL; i++) {
+ if (!strcmp(speed, speed_strings[i].speed))
+ return speed_strings[i].num;
+ }
+
+ return USB_SPEED_UNKNOWN;
+}
+
+#define READ_ATTR(object, type, dev, name, format)\
+ do { (object)->name = (type) read_attr_value(dev, to_string(name), format); } while (0)
+
+
+int read_usb_device(struct sysfs_device *sdev, struct usb_device *udev)
+{
+ uint32_t busnum, devnum;
+
+ READ_ATTR(udev, uint8_t, sdev, bDeviceClass, "%02x\n");
+ READ_ATTR(udev, uint8_t, sdev, bDeviceSubClass, "%02x\n");
+ READ_ATTR(udev, uint8_t, sdev, bDeviceProtocol, "%02x\n");
+
+ READ_ATTR(udev, uint16_t, sdev, idVendor, "%04x\n");
+ READ_ATTR(udev, uint16_t, sdev, idProduct, "%04x\n");
+ READ_ATTR(udev, uint16_t, sdev, bcdDevice, "%04x\n");
+
+ READ_ATTR(udev, uint8_t, sdev, bConfigurationValue, "%02x\n");
+ READ_ATTR(udev, uint8_t, sdev, bNumConfigurations, "%02x\n");
+ READ_ATTR(udev, uint8_t, sdev, bNumInterfaces, "%02x\n");
+
+ READ_ATTR(udev, uint8_t, sdev, devnum, "%d\n");
+ udev->speed = read_attr_speed(sdev);
+
+ strncpy(udev->path, sdev->path, SYSFS_PATH_MAX);
+ strncpy(udev->busid, sdev->name, SYSFS_BUS_ID_SIZE);
+
+ sscanf(sdev->name, "%u-%u", &busnum, &devnum);
+ udev->busnum = busnum;
+
+ return 0;
+}
+
+int read_usb_interface(struct usb_device *udev, int i, struct usb_interface *uinf)
+{
+ char busid[SYSFS_BUS_ID_SIZE];
+ struct sysfs_device *sif;
+
+ sprintf(busid, "%s:%d.%d", udev->busid, udev->bConfigurationValue, i);
+
+ sif = sysfs_open_device("usb", busid);
+ if (!sif) {
+ err("open sif of %s", busid);
+ return -1;
+ }
+
+ READ_ATTR(uinf, uint8_t, sif, bInterfaceClass, "%02x\n");
+ READ_ATTR(uinf, uint8_t, sif, bInterfaceSubClass, "%02x\n");
+ READ_ATTR(uinf, uint8_t, sif, bInterfaceProtocol, "%02x\n");
+
+ sysfs_close_device(sif);
+
+ return 0;
+}
+
+int usbip_names_init(char *f)
+{
+ return names_init(f);
+}
+
+void usbip_names_free()
+{
+ names_free();
+}
+
+void usbip_names_get_product(char *buff, size_t size, uint16_t vendor, uint16_t product)
+{
+ const char *prod, *vend;
+
+ prod = names_product(vendor, product);
+ if (!prod)
+ prod = "unknown product";
+
+
+ vend = names_vendor(vendor);
+ if (!vend)
+ vend = "unknown vendor";
+
+ snprintf(buff, size, "%s : %s (%04x:%04x)", vend, prod, vendor, product);
+}
+
+void usbip_names_get_class(char *buff, size_t size, uint8_t class, uint8_t subclass, uint8_t protocol)
+{
+ const char *c, *s, *p;
+
+ if (class == 0 && subclass == 0 && protocol == 0) {
+ snprintf(buff, size, "(Defined at Interface level) (%02x/%02x/%02x)", class, subclass, protocol);
+ return;
+ }
+
+ p = names_protocol(class, subclass, protocol);
+ if (!p)
+ p = "unknown protocol";
+
+ s = names_subclass(class, subclass);
+ if (!s)
+ s = "unknown subclass";
+
+ c = names_class(class);
+ if (!c)
+ c = "unknown class";
+
+ snprintf(buff, size, "%s / %s / %s (%02x/%02x/%02x)", c, s, p, class, subclass, protocol);
+}
diff --git a/drivers/staging/usbip/userspace/libsrc/usbip_common.h b/drivers/staging/usbip/userspace/libsrc/usbip_common.h
new file mode 100644
index 0000000..c254b54
--- /dev/null
+++ b/drivers/staging/usbip/userspace/libsrc/usbip_common.h
@@ -0,0 +1,149 @@
+/*
+ * Copyright (C) 2005-2007 Takahiro Hirofuchi
+ */
+
+#ifndef _USBIP_COMMON_H
+#define _USBIP_COMMON_H
+
+#include <unistd.h>
+#include <stdint.h>
+#include <syslog.h>
+#include <errno.h>
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+#include <strings.h>
+
+#include <sysfs/libsysfs.h>
+#include <netdb.h>
+#include <sys/socket.h>
+
+#ifndef USBIDS_FILE
+#define USBIDS_FILE "/usr/share/hwdata/usb.ids"
+#endif
+
+#ifndef VHCI_STATE_PATH
+#define VHCI_STATE_PATH "/var/run/vhci_hcd"
+#endif
+
+//#include <linux/usb_ch9.h>
+enum usb_device_speed {
+ USB_SPEED_UNKNOWN = 0, /* enumerating */
+ USB_SPEED_LOW, USB_SPEED_FULL, /* usb 1.1 */
+ USB_SPEED_HIGH, /* usb 2.0 */
+ USB_SPEED_VARIABLE /* wireless (usb 2.5) */
+};
+
+/* FIXME: how to sync with drivers/usbip_common.h ? */
+enum usbip_device_status{
+ /* sdev is available. */
+ SDEV_ST_AVAILABLE = 0x01,
+ /* sdev is now used. */
+ SDEV_ST_USED,
+ /* sdev is unusable because of a fatal error. */
+ SDEV_ST_ERROR,
+
+ /* vdev does not connect a remote device. */
+ VDEV_ST_NULL,
+ /* vdev is used, but the USB address is not assigned yet */
+ VDEV_ST_NOTASSIGNED,
+ VDEV_ST_USED,
+ VDEV_ST_ERROR
+};
+
+extern int usbip_use_syslog;
+extern int usbip_use_stderr;
+extern int usbip_use_debug ;
+
+#define err(fmt, args...) do { \
+ if (usbip_use_syslog) { \
+ syslog(LOG_ERR, "usbip err: %13s:%4d (%-12s) " fmt "\n", \
+ __FILE__, __LINE__, __FUNCTION__, ##args); \
+ } \
+ if (usbip_use_stderr) { \
+ fprintf(stderr, "usbip err: %13s:%4d (%-12s) " fmt "\n", \
+ __FILE__, __LINE__, __FUNCTION__, ##args); \
+ } \
+} while (0)
+
+#define notice(fmt, args...) do { \
+ if (usbip_use_syslog) { \
+ syslog(LOG_DEBUG, "usbip: " fmt, ##args); \
+ } \
+ if (usbip_use_stderr) { \
+ fprintf(stderr, "usbip: " fmt "\n", ##args); \
+ } \
+} while (0)
+
+#define info(fmt, args...) do { \
+ if (usbip_use_syslog) { \
+ syslog(LOG_DEBUG, fmt, ##args); \
+ } \
+ if (usbip_use_stderr) { \
+ fprintf(stderr, fmt "\n", ##args); \
+ } \
+} while (0)
+
+#define dbg(fmt, args...) do { \
+ if (usbip_use_debug) { \
+ if (usbip_use_syslog) { \
+ syslog(LOG_DEBUG, "usbip dbg: %13s:%4d (%-12s) " fmt, \
+ __FILE__, __LINE__, __FUNCTION__, ##args); \
+ } \
+ if (usbip_use_stderr) { \
+ fprintf(stderr, "usbip dbg: %13s:%4d (%-12s) " fmt "\n", \
+ __FILE__, __LINE__, __FUNCTION__, ##args); \
+ } \
+ } \
+} while (0)
+
+
+#define BUG() do { err("sorry, it's a bug"); abort(); } while (0)
+
+
+struct usb_interface {
+ uint8_t bInterfaceClass;
+ uint8_t bInterfaceSubClass;
+ uint8_t bInterfaceProtocol;
+ uint8_t padding; /* alignment */
+} __attribute__((packed));
+
+
+
+struct usb_device {
+ char path[SYSFS_PATH_MAX];
+ char busid[SYSFS_BUS_ID_SIZE];
+
+ uint32_t busnum;
+ uint32_t devnum;
+ uint32_t speed;
+
+ uint16_t idVendor;
+ uint16_t idProduct;
+ uint16_t bcdDevice;
+
+ uint8_t bDeviceClass;
+ uint8_t bDeviceSubClass;
+ uint8_t bDeviceProtocol;
+ uint8_t bConfigurationValue;
+ uint8_t bNumConfigurations;
+ uint8_t bNumInterfaces;
+} __attribute__((packed));
+
+#define to_string(s) #s
+
+void dump_usb_interface(struct usb_interface *);
+void dump_usb_device(struct usb_device *);
+int read_usb_device(struct sysfs_device *sdev, struct usb_device *udev);
+int read_attr_value(struct sysfs_device *dev, const char *name, const char *format);
+int read_usb_interface(struct usb_device *udev, int i, struct usb_interface *uinf);
+
+const char *usbip_speed_string(int num);
+const char *usbip_status_string(int32_t status);
+
+int usbip_names_init(char *);
+void usbip_names_free(void);
+void usbip_names_get_product(char *buff, size_t size, uint16_t vendor, uint16_t product);
+void usbip_names_get_class(char *buff, size_t size, uint8_t class, uint8_t subclass, uint8_t protocol);
+
+#endif
diff --git a/drivers/staging/usbip/userspace/libsrc/vhci_driver.c b/drivers/staging/usbip/userspace/libsrc/vhci_driver.c
new file mode 100644
index 0000000..db43f8d
--- /dev/null
+++ b/drivers/staging/usbip/userspace/libsrc/vhci_driver.c
@@ -0,0 +1,506 @@
+/*
+ * Copyright (C) 2005-2007 Takahiro Hirofuchi
+ */
+
+
+#include "usbip.h"
+
+
+static const char vhci_driver_name[] = "vhci_hcd";
+
+struct usbip_vhci_driver *vhci_driver;
+
+static struct usbip_imported_device *imported_device_init(struct usbip_imported_device *idev, char *busid)
+{
+ struct sysfs_device *sudev;
+
+ sudev = sysfs_open_device("usb", busid);
+ if (!sudev) {
+ err("sysfs_open_device %s", busid);
+ goto err;
+ }
+ read_usb_device(sudev, &idev->udev);
+ sysfs_close_device(sudev);
+
+ /* add class devices of this imported device */
+ struct class_device *cdev;
+ dlist_for_each_data(vhci_driver->cdev_list, cdev, struct class_device) {
+ if (!strncmp(cdev->devpath, idev->udev.path, strlen(idev->udev.path))) {
+ struct class_device *new_cdev;
+
+ /* alloc and copy because dlist is linked from only one list */
+ new_cdev = calloc(1, sizeof(*new_cdev));
+ if (!new_cdev)
+ goto err;
+
+ memcpy(new_cdev, cdev, sizeof(*new_cdev));
+ dlist_unshift(idev->cdev_list, (void*) new_cdev);
+ }
+ }
+
+ return idev;
+
+err:
+ return NULL;
+}
+
+
+
+static int parse_status(char *value)
+{
+ int ret = 0;
+ char *c;
+
+
+ for (int i = 0; i < vhci_driver->nports; i++)
+ bzero(&vhci_driver->idev[i], sizeof(struct usbip_imported_device));
+
+
+ /* skip a header line */
+ c = strchr(value, '\n') + 1;
+
+ while (*c != '\0') {
+ int port, status, speed, devid;
+ unsigned long socket;
+ char lbusid[SYSFS_BUS_ID_SIZE];
+
+ ret = sscanf(c, "%d %d %d %x %lx %s\n",
+ &port, &status, &speed,
+ &devid, &socket, lbusid);
+
+ if (ret < 5) {
+ err("scanf %d", ret);
+ BUG();
+ }
+
+ dbg("port %d status %d speed %d devid %x",
+ port, status, speed, devid);
+ dbg("socket %lx lbusid %s", socket, lbusid);
+
+
+ /* if a device is connected, look at it */
+ {
+ struct usbip_imported_device *idev = &vhci_driver->idev[port];
+
+ idev->port = port;
+ idev->status = status;
+
+ idev->devid = devid;
+
+ idev->busnum = (devid >> 16);
+ idev->devnum = (devid & 0x0000ffff);
+
+ idev->cdev_list = dlist_new(sizeof(struct class_device));
+ if (!idev->cdev_list) {
+ err("init new device");
+ return -1;
+ }
+
+ if (idev->status != VDEV_ST_NULL && idev->status != VDEV_ST_NOTASSIGNED) {
+ idev = imported_device_init(idev, lbusid);
+ if (!idev) {
+ err("init new device");
+ return -1;
+ }
+ }
+ }
+
+
+ /* go to the next line */
+ c = strchr(c, '\n') + 1;
+ }
+
+ dbg("exit");
+
+ return 0;
+}
+
+
+static int check_usbip_device(struct sysfs_class_device *cdev)
+{
+ char clspath[SYSFS_PATH_MAX]; /* /sys/class/video4linux/video0/device */
+ char devpath[SYSFS_PATH_MAX]; /* /sys/devices/platform/vhci_hcd/usb6/6-1:1.1 */
+
+ int ret;
+
+ snprintf(clspath, sizeof(clspath), "%s/device", cdev->path);
+
+ ret = sysfs_get_link(clspath, devpath, SYSFS_PATH_MAX);
+ if (!ret) {
+ if (!strncmp(devpath, vhci_driver->hc_device->path,
+ strlen(vhci_driver->hc_device->path))) {
+ /* found usbip device */
+ struct class_device *cdev;
+
+ cdev = calloc(1, sizeof(*cdev));
+ if (!cdev) {
+ err("calloc cdev");
+ return -1;
+ }
+ dlist_unshift(vhci_driver->cdev_list, (void*) cdev);
+ strncpy(cdev->clspath, clspath, sizeof(cdev->clspath));
+ strncpy(cdev->devpath, devpath, sizeof(cdev->clspath));
+ dbg(" found %s %s", clspath, devpath);
+ }
+ }
+
+ return 0;
+}
+
+
+static int search_class_for_usbip_device(char *cname)
+{
+ struct sysfs_class *class;
+ struct dlist *cdev_list;
+ struct sysfs_class_device *cdev;
+ int ret = 0;
+
+ class = sysfs_open_class(cname);
+ if (!class) {
+ err("open class");
+ return -1;
+ }
+
+ dbg("class %s", class->name);
+
+ cdev_list = sysfs_get_class_devices(class);
+ if (!cdev_list)
+ /* nothing */
+ goto out;
+
+ dlist_for_each_data(cdev_list, cdev, struct sysfs_class_device) {
+ dbg(" cdev %s", cdev->name);
+ ret = check_usbip_device(cdev);
+ if (ret < 0)
+ goto out;
+ }
+
+out:
+ sysfs_close_class(class);
+
+ return ret;
+}
+
+
+static int refresh_class_device_list(void)
+{
+ int ret;
+ struct dlist *cname_list;
+ char *cname;
+
+ /* search under /sys/class */
+ cname_list = sysfs_open_directory_list("/sys/class");
+ if (!cname_list) {
+ err("open class directory");
+ return -1;
+ }
+
+ dlist_for_each_data(cname_list, cname, char) {
+ ret = search_class_for_usbip_device(cname);
+ if (ret < 0) {
+ sysfs_close_list(cname_list);
+ return -1;
+ }
+ }
+
+ sysfs_close_list(cname_list);
+
+ /* seach under /sys/block */
+ ret = search_class_for_usbip_device(SYSFS_BLOCK_NAME);
+ if (ret < 0)
+ return -1;
+
+ return 0;
+}
+
+
+static int refresh_imported_device_list(void)
+{
+ struct sysfs_attribute *attr_status;
+
+
+ attr_status = sysfs_get_device_attr(vhci_driver->hc_device, "status");
+ if (!attr_status) {
+ err("get attr %s of %s", "status", vhci_driver->hc_device->name);
+ return -1;
+ }
+
+ dbg("name %s, path %s, len %d, method %d\n", attr_status->name,
+ attr_status->path, attr_status->len, attr_status->method);
+
+ dbg("%s", attr_status->value);
+
+ return parse_status(attr_status->value);
+}
+
+static int get_nports(void)
+{
+ int nports = 0;
+ struct sysfs_attribute *attr_status;
+
+ attr_status = sysfs_get_device_attr(vhci_driver->hc_device, "status");
+ if (!attr_status) {
+ err("get attr %s of %s", "status", vhci_driver->hc_device->name);
+ return -1;
+ }
+
+ dbg("name %s, path %s, len %d, method %d\n", attr_status->name,
+ attr_status->path, attr_status->len, attr_status->method);
+
+ dbg("%s", attr_status->value);
+
+ {
+ char *c;
+
+ /* skip a header line */
+ c = strchr(attr_status->value, '\n') + 1;
+
+ while (*c != '\0') {
+ /* go to the next line */
+ c = strchr(c, '\n') + 1;
+ nports += 1;
+ }
+ }
+
+ return nports;
+}
+
+static int get_hc_busid(char *sysfs_mntpath, char *hc_busid)
+{
+ struct sysfs_driver *sdriver;
+ char sdriver_path[SYSFS_PATH_MAX];
+
+ struct sysfs_device *hc_dev;
+ struct dlist *hc_devs;
+
+ int found = 0;
+
+ snprintf(sdriver_path, SYSFS_PATH_MAX, "%s/%s/platform/%s/%s",
+ sysfs_mntpath, SYSFS_BUS_NAME, SYSFS_DRIVERS_NAME,
+ vhci_driver_name);
+
+ sdriver = sysfs_open_driver_path(sdriver_path);
+ if (!sdriver) {
+ info("%s is not found", sdriver_path);
+ info("load usbip-core.ko and vhci-hcd.ko !");
+ return -1;
+ }
+
+ hc_devs = sysfs_get_driver_devices(sdriver);
+ if (!hc_devs) {
+ err("get hc list");
+ goto err;
+ }
+
+ /* assume only one vhci_hcd */
+ dlist_for_each_data(hc_devs, hc_dev, struct sysfs_device) {
+ strncpy(hc_busid, hc_dev->bus_id, SYSFS_BUS_ID_SIZE);
+ found = 1;
+ }
+
+err:
+ sysfs_close_driver(sdriver);
+
+ if (found)
+ return 0;
+
+ err("not found usbip hc");
+ return -1;
+}
+
+
+/* ---------------------------------------------------------------------- */
+
+int usbip_vhci_driver_open(void)
+{
+ int ret;
+ char hc_busid[SYSFS_BUS_ID_SIZE];
+
+ vhci_driver = (struct usbip_vhci_driver *) calloc(1, sizeof(*vhci_driver));
+ if (!vhci_driver) {
+ err("alloc vhci_driver");
+ return -1;
+ }
+
+ ret = sysfs_get_mnt_path(vhci_driver->sysfs_mntpath, SYSFS_PATH_MAX);
+ if (ret < 0) {
+ err("sysfs must be mounted");
+ goto err;
+ }
+
+ ret = get_hc_busid(vhci_driver->sysfs_mntpath, hc_busid);
+ if (ret < 0)
+ goto err;
+
+ /* will be freed in usbip_driver_close() */
+ vhci_driver->hc_device = sysfs_open_device("platform", hc_busid);
+ if (!vhci_driver->hc_device) {
+ err("get sysfs vhci_driver");
+ goto err;
+ }
+
+ vhci_driver->nports = get_nports();
+
+ info("%d ports available\n", vhci_driver->nports);
+
+ vhci_driver->cdev_list = dlist_new(sizeof(struct class_device));
+ if (!vhci_driver->cdev_list)
+ goto err;
+
+ if (refresh_class_device_list())
+ goto err;
+
+ if (refresh_imported_device_list())
+ goto err;
+
+
+ return 0;
+
+
+err:
+ if (vhci_driver->cdev_list)
+ dlist_destroy(vhci_driver->cdev_list);
+ if (vhci_driver->hc_device)
+ sysfs_close_device(vhci_driver->hc_device);
+ if (vhci_driver)
+ free(vhci_driver);
+
+ vhci_driver = NULL;
+ return -1;
+}
+
+
+void usbip_vhci_driver_close()
+{
+ if (!vhci_driver)
+ return;
+
+ if (vhci_driver->cdev_list)
+ dlist_destroy(vhci_driver->cdev_list);
+
+ for (int i = 0; i < vhci_driver->nports; i++) {
+ if (vhci_driver->idev[i].cdev_list)
+ dlist_destroy(vhci_driver->idev[i].cdev_list);
+ }
+
+ if (vhci_driver->hc_device)
+ sysfs_close_device(vhci_driver->hc_device);
+ free(vhci_driver);
+
+ vhci_driver = NULL;
+}
+
+
+int usbip_vhci_refresh_device_list(void)
+{
+ if (vhci_driver->cdev_list)
+ dlist_destroy(vhci_driver->cdev_list);
+
+
+ for (int i = 0; i < vhci_driver->nports; i++) {
+ if (vhci_driver->idev[i].cdev_list)
+ dlist_destroy(vhci_driver->idev[i].cdev_list);
+ }
+
+ vhci_driver->cdev_list = dlist_new(sizeof(struct class_device));
+ if (!vhci_driver->cdev_list)
+ goto err;
+
+ if (refresh_class_device_list())
+ goto err;
+
+ if (refresh_imported_device_list())
+ goto err;
+
+ return 0;
+err:
+ if (vhci_driver->cdev_list)
+ dlist_destroy(vhci_driver->cdev_list);
+
+ for (int i = 0; i < vhci_driver->nports; i++) {
+ if (vhci_driver->idev[i].cdev_list)
+ dlist_destroy(vhci_driver->idev[i].cdev_list);
+ }
+
+ err("refresh device list");
+ return -1;
+}
+
+
+int usbip_vhci_get_free_port(void)
+{
+ for (int i = 0; i < vhci_driver->nports; i++) {
+ if (vhci_driver->idev[i].status == VDEV_ST_NULL)
+ return i;
+ }
+
+ return -1;
+}
+
+int usbip_vhci_attach_device2(uint8_t port, int sockfd, uint32_t devid,
+ uint32_t speed) {
+ struct sysfs_attribute *attr_attach;
+ char buff[200]; /* what size should be ? */
+ int ret;
+
+ attr_attach = sysfs_get_device_attr(vhci_driver->hc_device, "attach");
+ if (!attr_attach) {
+ err("get attach");
+ return -1;
+ }
+
+ snprintf(buff, sizeof(buff), "%u %u %u %u",
+ port, sockfd, devid, speed);
+ dbg("writing: %s", buff);
+
+ ret = sysfs_write_attribute(attr_attach, buff, strlen(buff));
+ if (ret < 0) {
+ err("write to attach failed");
+ return -1;
+ }
+
+ info("port %d attached", port);
+
+ return 0;
+}
+
+static unsigned long get_devid(uint8_t busnum, uint8_t devnum)
+{
+ return (busnum << 16) | devnum;
+}
+
+/* will be removed */
+int usbip_vhci_attach_device(uint8_t port, int sockfd, uint8_t busnum,
+ uint8_t devnum, uint32_t speed)
+{
+ int devid = get_devid(busnum, devnum);
+
+ return usbip_vhci_attach_device2(port, sockfd, devid, speed);
+}
+
+int usbip_vhci_detach_device(uint8_t port)
+{
+ struct sysfs_attribute *attr_detach;
+ char buff[200]; /* what size should be ? */
+ int ret;
+
+ attr_detach = sysfs_get_device_attr(vhci_driver->hc_device, "detach");
+ if (!attr_detach) {
+ err("get detach");
+ return -1;
+ }
+
+ snprintf(buff, sizeof(buff), "%u", port);
+ dbg("writing to detach");
+ dbg("writing: %s", buff);
+
+ ret = sysfs_write_attribute(attr_detach, buff, strlen(buff));
+ if (ret < 0) {
+ err("write to detach failed");
+ return -1;
+ }
+
+ info("port %d detached", port);
+
+ return 0;
+}
diff --git a/drivers/staging/usbip/userspace/libsrc/vhci_driver.h b/drivers/staging/usbip/userspace/libsrc/vhci_driver.h
new file mode 100644
index 0000000..cad8ad7
--- /dev/null
+++ b/drivers/staging/usbip/userspace/libsrc/vhci_driver.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (C) 2005-2007 Takahiro Hirofuchi
+ */
+
+#ifndef _VHCI_DRIVER_H
+#define _VHCI_DRIVER_H
+
+#include "usbip.h"
+
+
+
+#define MAXNPORT 128
+
+struct class_device {
+ char clspath[SYSFS_PATH_MAX];
+ char devpath[SYSFS_PATH_MAX];
+};
+
+struct usbip_imported_device {
+ uint8_t port;
+ uint32_t status;
+
+ uint32_t devid;
+
+ uint8_t busnum;
+ uint8_t devnum;
+
+
+ struct dlist *cdev_list; /* list of class device */
+ struct usb_device udev;
+};
+
+struct usbip_vhci_driver {
+ char sysfs_mntpath[SYSFS_PATH_MAX];
+ struct sysfs_device *hc_device; /* /sys/devices/platform/vhci_hcd */
+
+ struct dlist *cdev_list; /* list of class device */
+
+ int nports;
+ struct usbip_imported_device idev[MAXNPORT];
+};
+
+
+extern struct usbip_vhci_driver *vhci_driver;
+
+int usbip_vhci_driver_open(void);
+void usbip_vhci_driver_close(void);
+
+int usbip_vhci_refresh_device_list(void);
+
+
+int usbip_vhci_get_free_port(void);
+int usbip_vhci_attach_device2(uint8_t port, int sockfd, uint32_t devid,
+ uint32_t speed);
+
+/* will be removed */
+int usbip_vhci_attach_device(uint8_t port, int sockfd, uint8_t busnum,
+ uint8_t devnum, uint32_t speed);
+
+int usbip_vhci_detach_device(uint8_t port);
+#endif
diff --git a/drivers/staging/usbip/userspace/src/Makefile.am b/drivers/staging/usbip/userspace/src/Makefile.am
new file mode 100644
index 0000000..05a7aa5
--- /dev/null
+++ b/drivers/staging/usbip/userspace/src/Makefile.am
@@ -0,0 +1,10 @@
+AM_CPPFLAGS := -I$(top_srcdir)/libsrc -DUSBIDS_FILE='"@USBIDS_DIR@/usb.ids"'
+AM_CFLAGS := @EXTRA_CFLAGS@ @PACKAGE_CFLAGS@
+LDADD := $(top_srcdir)/libsrc/libusbip.la @PACKAGE_LIBS@
+
+sbin_PROGRAMS := usbip usbipd usbip_bind_driver
+
+usbip_SOURCES := usbip.c usbip_network.c usbip_network.h
+usbipd_SOURCES := usbipd.c usbip_network.c usbip_network.h
+usbip_bind_driver_SOURCES := bind-driver.c utils.c utils.h \
+ usbip_network.h usbip_network.c
diff --git a/drivers/staging/usbip/userspace/src/bind-driver.c b/drivers/staging/usbip/userspace/src/bind-driver.c
new file mode 100644
index 0000000..201ffbb
--- /dev/null
+++ b/drivers/staging/usbip/userspace/src/bind-driver.c
@@ -0,0 +1,643 @@
+/*
+ *
+ * Copyright (C) 2005-2007 Takahiro Hirofuchi
+ */
+
+#include "utils.h"
+
+#define _GNU_SOURCE
+#include <getopt.h>
+#include <glib.h>
+
+
+
+static const struct option longopts[] = {
+ {"usbip", required_argument, NULL, 'u'},
+ {"other", required_argument, NULL, 'o'},
+ {"list", no_argument, NULL, 'l'},
+ {"list2", no_argument, NULL, 'L'},
+ {"help", no_argument, NULL, 'h'},
+#if 0
+ {"allusbip", no_argument, NULL, 'a'},
+ {"export-to", required_argument, NULL, 'e'},
+ {"unexport", required_argument, NULL, 'x'},
+ {"busid", required_argument, NULL, 'b'},
+#endif
+
+ {NULL, 0, NULL, 0}
+};
+
+static const char match_busid_path[] = "/sys/bus/usb/drivers/usbip/match_busid";
+
+
+static void show_help(void)
+{
+ printf("Usage: usbip_bind_driver [OPTION]\n");
+ printf("Change driver binding for USB/IP.\n");
+ printf(" --usbip busid make a device exportable\n");
+ printf(" --other busid use a device by a local driver\n");
+ printf(" --list print usb devices and their drivers\n");
+ printf(" --list2 print usb devices and their drivers in parseable mode\n");
+#if 0
+ printf(" --allusbip make all devices exportable\n");
+ printf(" --export-to host export the device to 'host'\n");
+ printf(" --unexport host unexport a device previously exported to 'host'\n");
+ printf(" --busid busid the busid used for --export-to\n");
+#endif
+}
+
+static int modify_match_busid(char *busid, int add)
+{
+ int fd;
+ int ret;
+ char buff[BUS_ID_SIZE + 4];
+
+ /* BUS_IS_SIZE includes NULL termination? */
+ if (strnlen(busid, BUS_ID_SIZE) > BUS_ID_SIZE - 1) {
+ g_warning("too long busid");
+ return -1;
+ }
+
+ fd = open(match_busid_path, O_WRONLY);
+ if (fd < 0)
+ return -1;
+
+ if (add)
+ snprintf(buff, BUS_ID_SIZE + 4, "add %s", busid);
+ else
+ snprintf(buff, BUS_ID_SIZE + 4, "del %s", busid);
+
+ g_debug("write \"%s\" to %s", buff, match_busid_path);
+
+ ret = write(fd, buff, sizeof(buff));
+ if (ret < 0) {
+ close(fd);
+ return -1;
+ }
+
+ close(fd);
+
+ return 0;
+}
+
+static const char unbind_path_format[] = "/sys/bus/usb/devices/%s/driver/unbind";
+
+/* buggy driver may cause dead lock */
+static int unbind_interface_busid(char *busid)
+{
+ char unbind_path[PATH_MAX];
+ int fd;
+ int ret;
+
+ snprintf(unbind_path, sizeof(unbind_path), unbind_path_format, busid);
+
+ fd = open(unbind_path, O_WRONLY);
+ if (fd < 0) {
+ g_warning("opening unbind_path failed: %d", fd);
+ return -1;
+ }
+
+ ret = write(fd, busid, strnlen(busid, BUS_ID_SIZE));
+ if (ret < 0) {
+ g_warning("write to unbind_path failed: %d", ret);
+ close(fd);
+ return -1;
+ }
+
+ close(fd);
+
+ return 0;
+}
+
+static int unbind_interface(char *busid, int configvalue, int interface)
+{
+ char inf_busid[BUS_ID_SIZE];
+ g_debug("unbinding interface");
+
+ snprintf(inf_busid, BUS_ID_SIZE, "%s:%d.%d", busid, configvalue, interface);
+
+ return unbind_interface_busid(inf_busid);
+}
+
+
+static const char bind_path_format[] = "/sys/bus/usb/drivers/%s/bind";
+
+static int bind_interface_busid(char *busid, char *driver)
+{
+ char bind_path[PATH_MAX];
+ int fd;
+ int ret;
+
+ snprintf(bind_path, sizeof(bind_path), bind_path_format, driver);
+
+ fd = open(bind_path, O_WRONLY);
+ if (fd < 0)
+ return -1;
+
+ ret = write(fd, busid, strnlen(busid, BUS_ID_SIZE));
+ if (ret < 0) {
+ close(fd);
+ return -1;
+ }
+
+ close(fd);
+
+ return 0;
+}
+
+static int bind_interface(char *busid, int configvalue, int interface, char *driver)
+{
+ char inf_busid[BUS_ID_SIZE];
+
+ snprintf(inf_busid, BUS_ID_SIZE, "%s:%d.%d", busid, configvalue, interface);
+
+ return bind_interface_busid(inf_busid, driver);
+}
+
+static int unbind(char *busid)
+{
+ int configvalue = 0;
+ int ninterface = 0;
+ int devclass = 0;
+ int i;
+ int failed = 0;
+
+ configvalue = read_bConfigurationValue(busid);
+ ninterface = read_bNumInterfaces(busid);
+ devclass = read_bDeviceClass(busid);
+
+ if (configvalue < 0 || ninterface < 0 || devclass < 0) {
+ g_warning("read config and ninf value, removed?");
+ return -1;
+ }
+
+ if (devclass == 0x09) {
+ g_message("skip unbinding of hub");
+ return -1;
+ }
+
+ for (i = 0; i < ninterface; i++) {
+ char driver[PATH_MAX];
+ int ret;
+
+ bzero(&driver, sizeof(driver));
+
+ getdriver(busid, configvalue, i, driver, PATH_MAX-1);
+
+ g_debug(" %s:%d.%d -> %s ", busid, configvalue, i, driver);
+
+ if (!strncmp("none", driver, PATH_MAX))
+ continue; /* unbound interface */
+
+#if 0
+ if (!strncmp("usbip", driver, PATH_MAX))
+ continue; /* already bound to usbip */
+#endif
+
+ /* unbinding */
+ ret = unbind_interface(busid, configvalue, i);
+ if (ret < 0) {
+ g_warning("unbind driver at %s:%d.%d failed",
+ busid, configvalue, i);
+ failed = 1;
+ }
+ }
+
+ if (failed)
+ return -1;
+ else
+ return 0;
+}
+
+/* call at unbound state */
+static int bind_to_usbip(char *busid)
+{
+ int configvalue = 0;
+ int ninterface = 0;
+ int i;
+ int failed = 0;
+
+ configvalue = read_bConfigurationValue(busid);
+ ninterface = read_bNumInterfaces(busid);
+
+ if (configvalue < 0 || ninterface < 0) {
+ g_warning("read config and ninf value, removed?");
+ return -1;
+ }
+
+ for (i = 0; i < ninterface; i++) {
+ int ret;
+
+ ret = bind_interface(busid, configvalue, i, "usbip");
+ if (ret < 0) {
+ g_warning("bind usbip at %s:%d.%d, failed",
+ busid, configvalue, i);
+ failed = 1;
+ /* need to contine binding at other interfaces */
+ }
+ }
+
+ if (failed)
+ return -1;
+ else
+ return 0;
+}
+
+
+static int use_device_by_usbip(char *busid)
+{
+ int ret;
+
+ ret = unbind(busid);
+ if (ret < 0) {
+ g_warning("unbind drivers of %s, failed", busid);
+ return -1;
+ }
+
+ ret = modify_match_busid(busid, 1);
+ if (ret < 0) {
+ g_warning("add %s to match_busid, failed", busid);
+ return -1;
+ }
+
+ ret = bind_to_usbip(busid);
+ if (ret < 0) {
+ g_warning("bind usbip to %s, failed", busid);
+ modify_match_busid(busid, 0);
+ return -1;
+ }
+
+ g_message("bind %s to usbip, complete!", busid);
+
+ return 0;
+}
+
+
+
+static int use_device_by_other(char *busid)
+{
+ int ret;
+ int config;
+
+ /* read and write the same config value to kick probing */
+ config = read_bConfigurationValue(busid);
+ if (config < 0) {
+ g_warning("read bConfigurationValue of %s, failed", busid);
+ return -1;
+ }
+
+ ret = modify_match_busid(busid, 0);
+ if (ret < 0) {
+ g_warning("del %s to match_busid, failed", busid);
+ return -1;
+ }
+
+ ret = write_bConfigurationValue(busid, config);
+ if (ret < 0) {
+ g_warning("read bConfigurationValue of %s, failed", busid);
+ return -1;
+ }
+
+ g_message("bind %s to other drivers than usbip, complete!", busid);
+
+ return 0;
+}
+
+
+#include <sys/types.h>
+#include <regex.h>
+
+#include <errno.h>
+#include <string.h>
+#include <stdio.h>
+
+
+
+static int is_usb_device(char *busid)
+{
+ int ret;
+
+ regex_t regex;
+ regmatch_t pmatch[1];
+
+ ret = regcomp(®ex, "^[0-9]+-[0-9]+(\\.[0-9]+)*$", REG_NOSUB|REG_EXTENDED);
+ if (ret < 0)
+ g_error("regcomp: %s\n", strerror(errno));
+
+ ret = regexec(®ex, busid, 0, pmatch, 0);
+ if (ret)
+ return 0; /* not matched */
+
+ return 1;
+}
+
+
+#include <dirent.h>
+static int show_devices(void)
+{
+ DIR *dir;
+
+ dir = opendir("/sys/bus/usb/devices/");
+ if (!dir)
+ g_error("opendir: %s", strerror(errno));
+
+ printf("List USB devices\n");
+ for (;;) {
+ struct dirent *dirent;
+ char *busid;
+
+ dirent = readdir(dir);
+ if (!dirent)
+ break;
+
+ busid = dirent->d_name;
+
+ if (is_usb_device(busid)) {
+ char name[100] = {'\0'};
+ char driver[100] = {'\0'};
+ int conf, ninf = 0;
+ int i;
+
+ conf = read_bConfigurationValue(busid);
+ ninf = read_bNumInterfaces(busid);
+
+ getdevicename(busid, name, sizeof(name));
+
+ printf(" - busid %s (%s)\n", busid, name);
+
+ for (i = 0; i < ninf; i++) {
+ getdriver(busid, conf, i, driver, sizeof(driver));
+ printf(" %s:%d.%d -> %s\n", busid, conf, i, driver);
+ }
+ printf("\n");
+ }
+ }
+
+ closedir(dir);
+
+ return 0;
+}
+
+static int show_devices2(void)
+{
+ DIR *dir;
+
+ dir = opendir("/sys/bus/usb/devices/");
+ if (!dir)
+ g_error("opendir: %s", strerror(errno));
+
+ for (;;) {
+ struct dirent *dirent;
+ char *busid;
+
+ dirent = readdir(dir);
+ if (!dirent)
+ break;
+
+ busid = dirent->d_name;
+
+ if (is_usb_device(busid)) {
+ char name[100] = {'\0'};
+ char driver[100] = {'\0'};
+ int conf, ninf = 0;
+ int i;
+
+ conf = read_bConfigurationValue(busid);
+ ninf = read_bNumInterfaces(busid);
+
+ getdevicename(busid, name, sizeof(name));
+
+ printf("busid=%s#usbid=%s#", busid, name);
+
+ for (i = 0; i < ninf; i++) {
+ getdriver(busid, conf, i, driver, sizeof(driver));
+ printf("%s:%d.%d=%s#", busid, conf, i, driver);
+ }
+ printf("\n");
+ }
+ }
+
+ closedir(dir);
+
+ return 0;
+}
+
+
+#if 0
+static int export_to(char *host, char *busid) {
+
+ int ret;
+
+ if( host == NULL ) {
+ printf( "no host given\n\n");
+ show_help();
+ return -1;
+ }
+ if( busid == NULL ) {
+ /* XXX print device list and ask for busnumber, if none is
+ * given */
+ printf( "no busid given, use --busid switch\n\n");
+ show_help();
+ return -1;
+ }
+
+
+ ret = use_device_by_usbip(busid);
+ if( ret != 0 ) {
+ printf( "could not bind driver to usbip\n");
+ return -1;
+ }
+
+ printf( "DEBUG: exporting device '%s' to '%s'\n", busid, host );
+ ret = export_busid_to_host(host, busid); /* usbip_export.[ch] */
+ if( ret != 0 ) {
+ printf( "could not export device to host\n" );
+ printf( " host: %s, device: %s\n", host, busid );
+ use_device_by_other(busid);
+ return -1;
+ }
+
+ return 0;
+}
+
+static int unexport_from(char *host, char *busid) {
+
+ int ret;
+
+ if (!host || !busid)
+ g_error("no host or no busid\n");
+
+ g_message("unexport_from: host: '%s', busid: '%s'", host, busid);
+
+ ret = unexport_busid_from_host(host, busid); /* usbip_export.[ch] */
+ if( ret != 0 ) {
+ err( "could not unexport device from host\n" );
+ err( " host: %s, device: %s\n", host, busid );
+ }
+
+ ret = use_device_by_other(busid);
+ if (ret < 0)
+ g_error("could not unbind device from usbip\n");
+
+ return 0;
+}
+
+
+static int allusbip(void)
+{
+ DIR *dir;
+
+ dir = opendir("/sys/bus/usb/devices/");
+ if (!dir)
+ g_error("opendir: %s", strerror(errno));
+
+ for (;;) {
+ struct dirent *dirent;
+ char *busid;
+
+ dirent = readdir(dir);
+ if (!dirent)
+ break;
+
+ busid = dirent->d_name;
+
+ if (!is_usb_device(busid))
+ continue;
+
+ {
+ char name[PATH_MAX];
+ int conf, ninf = 0;
+ int i;
+ int be_local = 0;
+
+ conf = read_bConfigurationValue(busid);
+ ninf = read_bNumInterfaces(busid);
+
+ getdevicename(busid, name, sizeof(name));
+
+ for (i = 0; i < ninf; i++) {
+ char driver[PATH_MAX];
+
+ getdriver(busid, conf, i, driver, sizeof(driver));
+#if 0
+ if (strncmp(driver, "usbhid", 6) == 0 || strncmp(driver, "usb-storage", 11) == 0) {
+ be_local = 1;
+ break;
+ }
+#endif
+ }
+
+ if (be_local == 0)
+ use_device_by_usbip(busid);
+ }
+ }
+
+ closedir(dir);
+
+ return 0;
+}
+#endif
+
+int main(int argc, char **argv)
+{
+ char *busid = NULL;
+ char *remote_host __attribute__((unused)) = NULL;
+
+ enum {
+ cmd_unknown = 0,
+ cmd_use_by_usbip,
+ cmd_use_by_other,
+ cmd_list,
+ cmd_list2,
+ cmd_allusbip,
+ cmd_export_to,
+ cmd_unexport,
+ cmd_help,
+ } cmd = cmd_unknown;
+
+ if (geteuid() != 0)
+ g_warning("running non-root?");
+
+ for (;;) {
+ int c;
+ int index = 0;
+
+ c = getopt_long(argc, argv, "u:o:hlLae:x:b:", longopts, &index);
+ if (c == -1)
+ break;
+
+ switch (c) {
+ case 'u':
+ cmd = cmd_use_by_usbip;
+ busid = optarg;
+ break;
+ case 'o' :
+ cmd = cmd_use_by_other;
+ busid = optarg;
+ break;
+ case 'l' :
+ cmd = cmd_list;
+ break;
+ case 'L' :
+ cmd = cmd_list2;
+ break;
+ case 'a' :
+ cmd = cmd_allusbip;
+ break;
+ case 'b':
+ busid = optarg;
+ break;
+ case 'e':
+ cmd = cmd_export_to;
+ remote_host = optarg;
+ break;
+ case 'x':
+ cmd = cmd_unexport;
+ remote_host = optarg;
+ break;
+ case 'h': /* fallthrough */
+ case '?':
+ cmd = cmd_help;
+ break;
+ default:
+ g_error("getopt");
+ }
+
+ //if (cmd)
+ // break;
+ }
+
+ switch (cmd) {
+ case cmd_use_by_usbip:
+ use_device_by_usbip(busid);
+ break;
+ case cmd_use_by_other:
+ use_device_by_other(busid);
+ break;
+ case cmd_list:
+ show_devices();
+ break;
+ case cmd_list2:
+ show_devices2();
+ break;
+#if 0
+ case cmd_allusbip:
+ allusbip();
+ break;
+ case cmd_export_to:
+ export_to(remote_host, busid);
+ break;
+ case cmd_unexport:
+ unexport_from(remote_host, busid);
+ break;
+#endif
+ case cmd_help: /* fallthrough */
+ case cmd_unknown:
+ show_help();
+ break;
+ default:
+ g_error("NOT REACHED");
+ }
+
+ return 0;
+}
diff --git a/drivers/staging/usbip/userspace/src/usbip.c b/drivers/staging/usbip/userspace/src/usbip.c
new file mode 100644
index 0000000..01a5628
--- /dev/null
+++ b/drivers/staging/usbip/userspace/src/usbip.c
@@ -0,0 +1,723 @@
+/*
+ *
+ * Copyright (C) 2005-2007 Takahiro Hirofuchi
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "../config.h"
+#endif
+
+#include "usbip.h"
+#include "usbip_network.h"
+#include <ctype.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <stdlib.h>
+#include <fcntl.h>
+#include <glib.h>
+
+static const char version[] = PACKAGE_STRING;
+
+
+/* /sys/devices/platform/vhci_hcd/usb6/6-1/6-1:1.1 -> 1 */
+static int get_interface_number(char *path)
+{
+ char *c;
+
+ c = strstr(path, vhci_driver->hc_device->bus_id);
+ if (!c)
+ return -1; /* hc exist? */
+ c++;
+ /* -> usb6/6-1/6-1:1.1 */
+
+ c = strchr(c, '/');
+ if (!c)
+ return -1; /* hc exist? */
+ c++;
+ /* -> 6-1/6-1:1.1 */
+
+ c = strchr(c, '/');
+ if (!c)
+ return -1; /* no interface path */
+ c++;
+ /* -> 6-1:1.1 */
+
+ c = strchr(c, ':');
+ if (!c)
+ return -1; /* no configuration? */
+ c++;
+ /* -> 1.1 */
+
+ c = strchr(c, '.');
+ if (!c)
+ return -1; /* no interface? */
+ c++;
+ /* -> 1 */
+
+
+ return atoi(c);
+}
+
+
+static struct sysfs_device *open_usb_interface(struct usb_device *udev, int i)
+{
+ struct sysfs_device *suinf;
+ char busid[SYSFS_BUS_ID_SIZE];
+
+ snprintf(busid, SYSFS_BUS_ID_SIZE, "%s:%d.%d",
+ udev->busid, udev->bConfigurationValue, i);
+
+ suinf = sysfs_open_device("usb", busid);
+ if (!suinf)
+ err("sysfs_open_device %s", busid);
+
+ return suinf;
+}
+
+
+#define MAX_BUFF 100
+static int record_connection(char *host, char *port, char *busid, int rhport)
+{
+ int fd;
+ char path[PATH_MAX+1];
+ char buff[MAX_BUFF+1];
+ int ret;
+
+ mkdir(VHCI_STATE_PATH, 0700);
+
+ snprintf(path, PATH_MAX, VHCI_STATE_PATH"/port%d", rhport);
+
+ fd = open(path, O_WRONLY|O_CREAT|O_TRUNC, S_IRWXU);
+ if (fd < 0)
+ return -1;
+
+ snprintf(buff, MAX_BUFF, "%s %s %s\n",
+ host, port, busid);
+
+ ret = write(fd, buff, strlen(buff));
+ if (ret != (ssize_t) strlen(buff)) {
+ close(fd);
+ return -1;
+ }
+
+ close(fd);
+
+ return 0;
+}
+
+static int read_record(int rhport, char *host, char *port, char *busid)
+{
+ FILE *file;
+ char path[PATH_MAX+1];
+
+ snprintf(path, PATH_MAX, VHCI_STATE_PATH"/port%d", rhport);
+
+ file = fopen(path, "r");
+ if (!file) {
+ err("fopen");
+ return -1;
+ }
+
+ if (fscanf(file, "%s %s %s\n", host, port, busid) != 3) {
+ err("fscanf");
+ fclose(file);
+ return -1;
+ }
+
+ fclose(file);
+
+ return 0;
+}
+
+
+int usbip_vhci_imported_device_dump(struct usbip_imported_device *idev)
+{
+ char product_name[100];
+ char host[NI_MAXHOST] = "unknown host";
+ char serv[NI_MAXSERV] = "unknown port";
+ char remote_busid[SYSFS_BUS_ID_SIZE];
+ int ret;
+
+ if (idev->status == VDEV_ST_NULL || idev->status == VDEV_ST_NOTASSIGNED) {
+ info("Port %02d: <%s>", idev->port, usbip_status_string(idev->status));
+ return 0;
+ }
+
+ ret = read_record(idev->port, host, serv, remote_busid);
+ if (ret) {
+ err("read_record");
+ return -1;
+ }
+
+ info("Port %02d: <%s> at %s", idev->port,
+ usbip_status_string(idev->status), usbip_speed_string(idev->udev.speed));
+
+ usbip_names_get_product(product_name, sizeof(product_name),
+ idev->udev.idVendor, idev->udev.idProduct);
+
+ info(" %s", product_name);
+
+ info("%10s -> usbip://%s:%s/%s (remote devid %08x (bus/dev %03d/%03d))",
+ idev->udev.busid, host, serv, remote_busid,
+ idev->devid,
+ idev->busnum, idev->devnum);
+
+ for (int i=0; i < idev->udev.bNumInterfaces; i++) {
+ /* show interface information */
+ struct sysfs_device *suinf;
+
+ suinf = open_usb_interface(&idev->udev, i);
+ if (!suinf)
+ continue;
+
+ info(" %6s used by %-17s", suinf->bus_id, suinf->driver_name);
+ sysfs_close_device(suinf);
+
+ /* show class device information */
+ struct class_device *cdev;
+
+ dlist_for_each_data(idev->cdev_list, cdev, struct class_device) {
+ int ifnum = get_interface_number(cdev->devpath);
+ if (ifnum == i) {
+ info(" %s", cdev->clspath);
+ }
+ }
+ }
+
+ return 0;
+}
+
+
+
+
+static int query_exported_devices(int sockfd)
+{
+ int ret;
+ struct op_devlist_reply rep;
+ uint16_t code = OP_REP_DEVLIST;
+
+ bzero(&rep, sizeof(rep));
+
+ ret = usbip_send_op_common(sockfd, OP_REQ_DEVLIST, 0);
+ if (ret < 0) {
+ err("send op_common");
+ return -1;
+ }
+
+ ret = usbip_recv_op_common(sockfd, &code);
+ if (ret < 0) {
+ err("recv op_common");
+ return -1;
+ }
+
+ ret = usbip_recv(sockfd, (void *) &rep, sizeof(rep));
+ if (ret < 0) {
+ err("recv op_devlist");
+ return -1;
+ }
+
+ PACK_OP_DEVLIST_REPLY(0, &rep);
+ dbg("exportable %d devices", rep.ndev);
+
+ for (unsigned int i=0; i < rep.ndev; i++) {
+ char product_name[100];
+ char class_name[100];
+ struct usb_device udev;
+
+ bzero(&udev, sizeof(udev));
+
+ ret = usbip_recv(sockfd, (void *) &udev, sizeof(udev));
+ if (ret < 0) {
+ err("recv usb_device[%d]", i);
+ return -1;
+ }
+ pack_usb_device(0, &udev);
+
+ usbip_names_get_product(product_name, sizeof(product_name),
+ udev.idVendor, udev.idProduct);
+ usbip_names_get_class(class_name, sizeof(class_name), udev.bDeviceClass,
+ udev.bDeviceSubClass, udev.bDeviceProtocol);
+
+ info("%8s: %s", udev.busid, product_name);
+ info("%8s: %s", " ", udev.path);
+ info("%8s: %s", " ", class_name);
+
+ for (int j=0; j < udev.bNumInterfaces; j++) {
+ struct usb_interface uinf;
+
+ ret = usbip_recv(sockfd, (void *) &uinf, sizeof(uinf));
+ if (ret < 0) {
+ err("recv usb_interface[%d]", j);
+ return -1;
+ }
+
+ pack_usb_interface(0, &uinf);
+ usbip_names_get_class(class_name, sizeof(class_name), uinf.bInterfaceClass,
+ uinf.bInterfaceSubClass, uinf.bInterfaceProtocol);
+
+ info("%8s: %2d - %s", " ", j, class_name);
+ }
+
+ info(" ");
+ }
+
+ return rep.ndev;
+}
+
+static int import_device(int sockfd, struct usb_device *udev)
+{
+ int ret;
+ int port;
+
+ ret = usbip_vhci_driver_open();
+ if (ret < 0) {
+ err("open vhci_driver");
+ return -1;
+ }
+
+ port = usbip_vhci_get_free_port();
+ if (port < 0) {
+ err("no free port");
+ usbip_vhci_driver_close();
+ return -1;
+ }
+
+ ret = usbip_vhci_attach_device(port, sockfd, udev->busnum,
+ udev->devnum, udev->speed);
+ if (ret < 0) {
+ err("import device");
+ usbip_vhci_driver_close();
+ return -1;
+ }
+
+ usbip_vhci_driver_close();
+
+ return port;
+}
+
+
+static int query_import_device(int sockfd, char *busid)
+{
+ int ret;
+ struct op_import_request request;
+ struct op_import_reply reply;
+ uint16_t code = OP_REP_IMPORT;
+
+ bzero(&request, sizeof(request));
+ bzero(&reply, sizeof(reply));
+
+
+ /* send a request */
+ ret = usbip_send_op_common(sockfd, OP_REQ_IMPORT, 0);
+ if (ret < 0) {
+ err("send op_common");
+ return -1;
+ }
+
+ strncpy(request.busid, busid, SYSFS_BUS_ID_SIZE-1);
+
+ PACK_OP_IMPORT_REQUEST(0, &request);
+
+ ret = usbip_send(sockfd, (void *) &request, sizeof(request));
+ if (ret < 0) {
+ err("send op_import_request");
+ return -1;
+ }
+
+
+ /* recieve a reply */
+ ret = usbip_recv_op_common(sockfd, &code);
+ if (ret < 0) {
+ err("recv op_common");
+ return -1;
+ }
+
+ ret = usbip_recv(sockfd, (void *) &reply, sizeof(reply));
+ if (ret < 0) {
+ err("recv op_import_reply");
+ return -1;
+ }
+
+ PACK_OP_IMPORT_REPLY(0, &reply);
+
+
+ /* check the reply */
+ if (strncmp(reply.udev.busid, busid, SYSFS_BUS_ID_SIZE)) {
+ err("recv different busid %s", reply.udev.busid);
+ return -1;
+ }
+
+
+ /* import a device */
+ return import_device(sockfd, &reply.udev);
+}
+
+static int attach_device(char *host, char *busid)
+{
+ int sockfd;
+ int ret;
+ int rhport;
+
+ sockfd = tcp_connect(host, USBIP_PORT_STRING);
+ if (sockfd < 0) {
+ err("tcp connect");
+ return -1;
+ }
+
+ rhport = query_import_device(sockfd, busid);
+ if (rhport < 0) {
+ err("query");
+ return -1;
+ }
+
+ close(sockfd);
+
+ ret = record_connection(host, USBIP_PORT_STRING,
+ busid, rhport);
+ if (ret < 0) {
+ err("record connection");
+ return -1;
+ }
+
+ return 0;
+}
+
+static int detach_port(char *port)
+{
+ int ret;
+ uint8_t portnum;
+
+ for (unsigned int i=0; i < strlen(port); i++)
+ if (!isdigit(port[i])) {
+ err("invalid port %s", port);
+ return -1;
+ }
+
+ /* check max port */
+
+ portnum = atoi(port);
+
+ ret = usbip_vhci_driver_open();
+ if (ret < 0) {
+ err("open vhci_driver");
+ return -1;
+ }
+
+ ret = usbip_vhci_detach_device(portnum);
+ if (ret < 0)
+ return -1;
+
+ usbip_vhci_driver_close();
+
+ return ret;
+}
+
+static int show_exported_devices(char *host)
+{
+ int ret;
+ int sockfd;
+
+ sockfd = tcp_connect(host, USBIP_PORT_STRING);
+ if (sockfd < 0) {
+ err("- %s failed", host);
+ return -1;
+ }
+
+ info("- %s", host);
+
+ ret = query_exported_devices(sockfd);
+ if (ret < 0) {
+ err("query");
+ return -1;
+ }
+
+ close(sockfd);
+ return 0;
+}
+
+static int attach_exported_devices(char *host, int sockfd)
+{
+ int ret;
+ struct op_devlist_reply rep;
+ uint16_t code = OP_REP_DEVLIST;
+
+ bzero(&rep, sizeof(rep));
+
+ ret = usbip_send_op_common(sockfd, OP_REQ_DEVLIST, 0);
+ if(ret < 0) {
+ err("send op_common");
+ return -1;
+ }
+
+ ret = usbip_recv_op_common(sockfd, &code);
+ if(ret < 0) {
+ err("recv op_common");
+ return -1;
+ }
+
+ ret = usbip_recv(sockfd, (void *) &rep, sizeof(rep));
+ if(ret < 0) {
+ err("recv op_devlist");
+ return -1;
+ }
+
+ PACK_OP_DEVLIST_REPLY(0, &rep);
+ dbg("exportable %d devices", rep.ndev);
+
+ for(unsigned int i=0; i < rep.ndev; i++) {
+ char product_name[100];
+ char class_name[100];
+ struct usb_device udev;
+
+ bzero(&udev, sizeof(udev));
+
+ ret = usbip_recv(sockfd, (void *) &udev, sizeof(udev));
+ if(ret < 0) {
+ err("recv usb_device[%d]", i);
+ return -1;
+ }
+ pack_usb_device(0, &udev);
+
+ usbip_names_get_product(product_name, sizeof(product_name),
+ udev.idVendor, udev.idProduct);
+ usbip_names_get_class(class_name, sizeof(class_name), udev.bDeviceClass,
+ udev.bDeviceSubClass, udev.bDeviceProtocol);
+
+ dbg("Attaching usb port %s from host %s on usbip, with deviceid: %s", udev.busid, host, product_name);
+
+ for (int j=0; j < udev.bNumInterfaces; j++) {
+ struct usb_interface uinf;
+
+ ret = usbip_recv(sockfd, (void *) &uinf, sizeof(uinf));
+ if (ret < 0) {
+ err("recv usb_interface[%d]", j);
+ return -1;
+ }
+
+ pack_usb_interface(0, &uinf);
+ usbip_names_get_class(class_name, sizeof(class_name), uinf.bInterfaceClass,
+ uinf.bInterfaceSubClass, uinf.bInterfaceProtocol);
+
+ dbg("interface %2d - %s", j, class_name);
+ }
+
+ attach_device(host, udev.busid);
+ }
+
+ return rep.ndev;
+}
+
+static int attach_devices_all(char *host)
+{
+ int ret;
+ int sockfd;
+
+ sockfd = tcp_connect(host, USBIP_PORT_STRING);
+ if(sockfd < 0) {
+ err("- %s failed", host);
+ return -1;
+ }
+
+ info("- %s", host);
+
+ ret = attach_exported_devices(host, sockfd);
+ if(ret < 0) {
+ err("query");
+ return -1;
+ }
+
+ close(sockfd);
+ return 0;
+}
+
+
+const char help_message[] = "\
+Usage: usbip [options] \n\
+ -a, --attach [host] [bus_id] \n\
+ Attach a remote USB device. \n\
+ \n\
+ -x, --attachall [host] \n\
+ Attach all remote USB devices on the specific host. \n\
+ \n\
+ -d, --detach [ports] \n\
+ Detach an imported USB device. \n\
+ \n\
+ -l, --list [hosts] \n\
+ List exported USB devices. \n\
+ \n\
+ -p, --port \n\
+ List virtual USB port status. \n\
+ \n\
+ -D, --debug \n\
+ Print debugging information. \n\
+ \n\
+ -v, --version \n\
+ Show version. \n\
+ \n\
+ -h, --help \n\
+ Print this help. \n";
+
+static void show_help(void)
+{
+ printf("%s", help_message);
+}
+
+static int show_port_status(void)
+{
+ int ret;
+ struct usbip_imported_device *idev;
+
+ ret = usbip_vhci_driver_open();
+ if (ret < 0)
+ return ret;
+
+ for (int i = 0; i < vhci_driver->nports; i++) {
+ idev = &vhci_driver->idev[i];
+
+ if (usbip_vhci_imported_device_dump(idev) < 0)
+ ret = -1;
+ }
+
+ usbip_vhci_driver_close();
+
+ return ret;
+}
+
+#define _GNU_SOURCE
+#include <getopt.h>
+static const struct option longopts[] = {
+ {"attach", no_argument, NULL, 'a'},
+ {"attachall", no_argument, NULL, 'x'},
+ {"detach", no_argument, NULL, 'd'},
+ {"port", no_argument, NULL, 'p'},
+ {"list", no_argument, NULL, 'l'},
+ {"version", no_argument, NULL, 'v'},
+ {"help", no_argument, NULL, 'h'},
+ {"debug", no_argument, NULL, 'D'},
+ {"syslog", no_argument, NULL, 'S'},
+ {NULL, 0, NULL, 0}
+};
+
+int main(int argc, char *argv[])
+{
+ int ret;
+
+ enum {
+ cmd_attach = 1,
+ cmd_attachall,
+ cmd_detach,
+ cmd_port,
+ cmd_list,
+ cmd_help,
+ cmd_version
+ } cmd = 0;
+
+ usbip_use_stderr = 1;
+
+ if (geteuid() != 0)
+ g_warning("running non-root?");
+
+ ret = usbip_names_init(USBIDS_FILE);
+ if (ret)
+ notice("failed to open %s", USBIDS_FILE);
+
+ for (;;) {
+ int c;
+ int index = 0;
+
+ c = getopt_long(argc, argv, "adplvhDSx", longopts, &index);
+
+ if (c == -1)
+ break;
+
+ switch(c) {
+ case 'a':
+ if (!cmd)
+ cmd = cmd_attach;
+ else
+ cmd = cmd_help;
+ break;
+ case 'd':
+ if (!cmd)
+ cmd = cmd_detach;
+ else
+ cmd = cmd_help;
+ break;
+ case 'p':
+ if (!cmd)
+ cmd = cmd_port;
+ else cmd = cmd_help;
+ break;
+ case 'l':
+ if (!cmd)
+ cmd = cmd_list;
+ else
+ cmd = cmd_help;
+ break;
+ case 'v':
+ if (!cmd)
+ cmd = cmd_version;
+ else
+ cmd = cmd_help;
+ break;
+ case 'x':
+ if(!cmd)
+ cmd = cmd_attachall;
+ else
+ cmd = cmd_help;
+ break;
+ case 'h':
+ cmd = cmd_help;
+ break;
+ case 'D':
+ usbip_use_debug = 1;
+ break;
+ case 'S':
+ usbip_use_syslog = 1;
+ break;
+ case '?':
+ break;
+
+ default:
+ err("getopt");
+ }
+ }
+
+ ret = 0;
+ switch(cmd) {
+ case cmd_attach:
+ if (optind == argc - 2)
+ ret = attach_device(argv[optind], argv[optind+1]);
+ else
+ show_help();
+ break;
+ case cmd_detach:
+ while (optind < argc)
+ ret = detach_port(argv[optind++]);
+ break;
+ case cmd_port:
+ ret = show_port_status();
+ break;
+ case cmd_list:
+ while (optind < argc)
+ ret = show_exported_devices(argv[optind++]);
+ break;
+ case cmd_attachall:
+ while(optind < argc)
+ ret = attach_devices_all(argv[optind++]);
+ break;
+ case cmd_version:
+ printf("%s\n", version);
+ break;
+ case cmd_help:
+ show_help();
+ break;
+ default:
+ show_help();
+ }
+
+
+ usbip_names_free();
+
+ exit((ret == 0) ? EXIT_SUCCESS : EXIT_FAILURE);
+}
diff --git a/drivers/staging/usbip/userspace/src/usbip_network.c b/drivers/staging/usbip/userspace/src/usbip_network.c
new file mode 100644
index 0000000..01be3c7
--- /dev/null
+++ b/drivers/staging/usbip/userspace/src/usbip_network.c
@@ -0,0 +1,251 @@
+/*
+ *
+ * Copyright (C) 2005-2007 Takahiro Hirofuchi
+ */
+
+#include "usbip_network.h"
+
+void pack_uint32_t(int pack, uint32_t *num)
+{
+ uint32_t i;
+
+ if (pack)
+ i = htonl(*num);
+ else
+ i = ntohl(*num);
+
+ *num = i;
+}
+
+void pack_uint16_t(int pack, uint16_t *num)
+{
+ uint16_t i;
+
+ if (pack)
+ i = htons(*num);
+ else
+ i = ntohs(*num);
+
+ *num = i;
+}
+
+void pack_usb_device(int pack, struct usb_device *udev)
+{
+ pack_uint32_t(pack, &udev->busnum);
+ pack_uint32_t(pack, &udev->devnum);
+ pack_uint32_t(pack, &udev->speed );
+
+ pack_uint16_t(pack, &udev->idVendor );
+ pack_uint16_t(pack, &udev->idProduct);
+ pack_uint16_t(pack, &udev->bcdDevice);
+}
+
+void pack_usb_interface(int pack __attribute__((unused)),
+ struct usb_interface *udev __attribute__((unused)))
+{
+ /* uint8_t members need nothing */
+}
+
+
+static ssize_t usbip_xmit(int sockfd, void *buff, size_t bufflen, int sending)
+{
+ ssize_t total = 0;
+
+ if (!bufflen)
+ return 0;
+
+ do {
+ ssize_t nbytes;
+
+ if (sending)
+ nbytes = send(sockfd, buff, bufflen, 0);
+ else
+ nbytes = recv(sockfd, buff, bufflen, MSG_WAITALL);
+
+ if (nbytes <= 0)
+ return -1;
+
+ buff = (void *) ((intptr_t) buff + nbytes);
+ bufflen -= nbytes;
+ total += nbytes;
+
+ } while (bufflen > 0);
+
+
+ return total;
+}
+
+ssize_t usbip_recv(int sockfd, void *buff, size_t bufflen)
+{
+ return usbip_xmit(sockfd, buff, bufflen, 0);
+}
+
+ssize_t usbip_send(int sockfd, void *buff, size_t bufflen)
+{
+ return usbip_xmit(sockfd, buff, bufflen, 1);
+}
+
+int usbip_send_op_common(int sockfd, uint32_t code, uint32_t status)
+{
+ int ret;
+ struct op_common op_common;
+
+ bzero(&op_common, sizeof(op_common));
+
+ op_common.version = USBIP_VERSION;
+ op_common.code = code;
+ op_common.status = status;
+
+ PACK_OP_COMMON(1, &op_common);
+
+ ret = usbip_send(sockfd, (void *) &op_common, sizeof(op_common));
+ if (ret < 0) {
+ err("send op_common");
+ return -1;
+ }
+
+ return 0;
+}
+
+int usbip_recv_op_common(int sockfd, uint16_t *code)
+{
+ int ret;
+ struct op_common op_common;
+
+ bzero(&op_common, sizeof(op_common));
+
+ ret = usbip_recv(sockfd, (void *) &op_common, sizeof(op_common));
+ if (ret < 0) {
+ err("recv op_common, %d", ret);
+ goto err;
+ }
+
+ PACK_OP_COMMON(0, &op_common);
+
+ if (op_common.version != USBIP_VERSION) {
+ err("version mismatch, %d %d", op_common.version, USBIP_VERSION);
+ goto err;
+ }
+
+ switch(*code) {
+ case OP_UNSPEC:
+ break;
+ default:
+ if (op_common.code != *code) {
+ info("unexpected pdu %d for %d", op_common.code, *code);
+ goto err;
+ }
+ }
+
+ if (op_common.status != ST_OK) {
+ info("request failed at peer, %d", op_common.status);
+ goto err;
+ }
+
+ *code = op_common.code;
+
+ return 0;
+err:
+ return -1;
+}
+
+
+int usbip_set_reuseaddr(int sockfd)
+{
+ const int val = 1;
+ int ret;
+
+ ret = setsockopt(sockfd, SOL_SOCKET, SO_REUSEADDR, &val, sizeof(val));
+ if (ret < 0)
+ err("setsockopt SO_REUSEADDR");
+
+ return ret;
+}
+
+int usbip_set_nodelay(int sockfd)
+{
+ const int val = 1;
+ int ret;
+
+ ret = setsockopt(sockfd, IPPROTO_TCP, TCP_NODELAY, &val, sizeof(val));
+ if (ret < 0)
+ err("setsockopt TCP_NODELAY");
+
+ return ret;
+}
+
+int usbip_set_keepalive(int sockfd)
+{
+ const int val = 1;
+ int ret;
+
+ ret = setsockopt(sockfd, SOL_SOCKET, SO_KEEPALIVE, &val, sizeof(val));
+ if (ret < 0)
+ err("setsockopt SO_KEEPALIVE");
+
+ return ret;
+}
+
+/* IPv6 Ready */
+/*
+ * moved here from vhci_attach.c
+ */
+int tcp_connect(char *hostname, char *service)
+{
+ struct addrinfo hints, *res, *res0;
+ int sockfd;
+ int err;
+
+
+ memset(&hints, 0, sizeof(hints));
+ hints.ai_socktype = SOCK_STREAM;
+
+ /* get all possible addresses */
+ err = getaddrinfo(hostname, service, &hints, &res0);
+ if (err) {
+ err("%s %s: %s", hostname, service, gai_strerror(err));
+ return -1;
+ }
+
+ /* try all the addresses */
+ for (res = res0; res; res = res->ai_next) {
+ char hbuf[NI_MAXHOST], sbuf[NI_MAXSERV];
+
+ err = getnameinfo(res->ai_addr, res->ai_addrlen,
+ hbuf, sizeof(hbuf), sbuf, sizeof(sbuf), NI_NUMERICHOST | NI_NUMERICSERV);
+ if (err) {
+ err("%s %s: %s", hostname, service, gai_strerror(err));
+ continue;
+ }
+
+ dbg("trying %s port %s\n", hbuf, sbuf);
+
+ sockfd = socket(res->ai_family, res->ai_socktype, res->ai_protocol);
+ if (sockfd < 0) {
+ err("socket");
+ continue;
+ }
+
+ /* should set TCP_NODELAY for usbip */
+ usbip_set_nodelay(sockfd);
+ /* TODO: write code for heatbeat */
+ usbip_set_keepalive(sockfd);
+
+ err = connect(sockfd, res->ai_addr, res->ai_addrlen);
+ if (err < 0) {
+ close(sockfd);
+ continue;
+ }
+
+ /* connected */
+ dbg("connected to %s:%s", hbuf, sbuf);
+ freeaddrinfo(res0);
+ return sockfd;
+ }
+
+
+ dbg("%s:%s, %s", hostname, service, "no destination to connect to");
+ freeaddrinfo(res0);
+
+ return -1;
+}
diff --git a/drivers/staging/usbip/userspace/src/usbip_network.h b/drivers/staging/usbip/userspace/src/usbip_network.h
new file mode 100644
index 0000000..1225466
--- /dev/null
+++ b/drivers/staging/usbip/userspace/src/usbip_network.h
@@ -0,0 +1,198 @@
+/*
+ * Copyright (C) 2005-2007 Takahiro Hirofuchi
+ */
+
+#ifndef _USBIP_NETWORK_H
+#define _USBIP_NETWORK_H
+
+#include "usbip.h"
+#include <sys/types.h>
+#include <sys/socket.h>
+#include <netinet/tcp.h>
+
+
+/* -------------------------------------------------- */
+/* Define Protocol Format */
+/* -------------------------------------------------- */
+
+
+/* ---------------------------------------------------------------------- */
+/* Common header for all the kinds of PDUs. */
+struct op_common {
+ uint16_t version;
+
+#define OP_REQUEST (0x80 << 8)
+#define OP_REPLY (0x00 << 8)
+ uint16_t code;
+
+ /* add more error code */
+#define ST_OK 0x00
+#define ST_NA 0x01
+ uint32_t status; /* op_code status (for reply) */
+
+} __attribute__((packed));
+
+#define PACK_OP_COMMON(pack, op_common) do {\
+ pack_uint16_t(pack, &(op_common)->version);\
+ pack_uint16_t(pack, &(op_common)->code );\
+ pack_uint32_t(pack, &(op_common)->status );\
+} while (0)
+
+
+/* ---------------------------------------------------------------------- */
+/* Dummy Code */
+#define OP_UNSPEC 0x00
+#define OP_REQ_UNSPEC OP_UNSPEC
+#define OP_REP_UNSPEC OP_UNSPEC
+
+/* ---------------------------------------------------------------------- */
+/* Retrieve USB device information. (still not used) */
+#define OP_DEVINFO 0x02
+#define OP_REQ_DEVINFO (OP_REQUEST | OP_DEVINFO)
+#define OP_REP_DEVINFO (OP_REPLY | OP_DEVINFO)
+
+struct op_devinfo_request {
+ char busid[SYSFS_BUS_ID_SIZE];
+} __attribute__((packed));
+
+struct op_devinfo_reply {
+ struct usb_device udev;
+ struct usb_interface uinf[];
+} __attribute__((packed));
+
+
+/* ---------------------------------------------------------------------- */
+/* Import a remote USB device. */
+#define OP_IMPORT 0x03
+#define OP_REQ_IMPORT (OP_REQUEST | OP_IMPORT)
+#define OP_REP_IMPORT (OP_REPLY | OP_IMPORT)
+
+struct op_import_request {
+ char busid[SYSFS_BUS_ID_SIZE];
+} __attribute__((packed));
+
+struct op_import_reply {
+ struct usb_device udev;
+// struct usb_interface uinf[];
+} __attribute__((packed));
+
+#define PACK_OP_IMPORT_REQUEST(pack, request) do {\
+} while (0)
+
+#define PACK_OP_IMPORT_REPLY(pack, reply) do {\
+ pack_usb_device(pack, &(reply)->udev);\
+} while (0)
+
+
+
+/* ---------------------------------------------------------------------- */
+/* Export a USB device to a remote host. */
+#define OP_EXPORT 0x06
+#define OP_REQ_EXPORT (OP_REQUEST | OP_EXPORT)
+#define OP_REP_EXPORT (OP_REPLY | OP_EXPORT)
+
+struct op_export_request {
+ struct usb_device udev;
+} __attribute__((packed));
+
+struct op_export_reply {
+ int returncode;
+} __attribute__((packed));
+
+
+#define PACK_OP_EXPORT_REQUEST(pack, request) do {\
+ pack_usb_device(pack, &(request)->udev);\
+} while (0)
+
+#define PACK_OP_EXPORT_REPLY(pack, reply) do {\
+} while (0)
+
+/* ---------------------------------------------------------------------- */
+/* un-Export a USB device from a remote host. */
+#define OP_UNEXPORT 0x07
+#define OP_REQ_UNEXPORT (OP_REQUEST | OP_UNEXPORT)
+#define OP_REP_UNEXPORT (OP_REPLY | OP_UNEXPORT)
+
+struct op_unexport_request {
+ struct usb_device udev;
+} __attribute__((packed));
+
+struct op_unexport_reply {
+ int returncode;
+} __attribute__((packed));
+
+#define PACK_OP_UNEXPORT_REQUEST(pack, request) do {\
+ pack_usb_device(pack, &(request)->udev);\
+} while (0)
+
+#define PACK_OP_UNEXPORT_REPLY(pack, reply) do {\
+} while (0)
+
+
+
+/* ---------------------------------------------------------------------- */
+/* Negotiate IPSec encryption key. (still not used) */
+#define OP_CRYPKEY 0x04
+#define OP_REQ_CRYPKEY (OP_REQUEST | OP_CRYPKEY)
+#define OP_REP_CRYPKEY (OP_REPLY | OP_CRYPKEY)
+
+struct op_crypkey_request {
+ /* 128bit key */
+ uint32_t key[4];
+} __attribute__((packed));
+
+struct op_crypkey_reply {
+ uint32_t __reserved;
+} __attribute__((packed));
+
+
+/* ---------------------------------------------------------------------- */
+/* Retrieve the list of exported USB devices. */
+#define OP_DEVLIST 0x05
+#define OP_REQ_DEVLIST (OP_REQUEST | OP_DEVLIST)
+#define OP_REP_DEVLIST (OP_REPLY | OP_DEVLIST)
+
+struct op_devlist_request {
+} __attribute__((packed));
+
+struct op_devlist_reply {
+ uint32_t ndev;
+ /* followed by reply_extra[] */
+} __attribute__((packed));
+
+struct op_devlist_reply_extra {
+ struct usb_device udev;
+ struct usb_interface uinf[];
+} __attribute__((packed));
+
+#define PACK_OP_DEVLIST_REQUEST(pack, request) do {\
+} while (0)
+
+#define PACK_OP_DEVLIST_REPLY(pack, reply) do {\
+ pack_uint32_t(pack, &(reply)->ndev);\
+} while (0)
+
+
+/* -------------------------------------------------- */
+/* Declare Prototype Function */
+/* -------------------------------------------------- */
+
+void pack_uint32_t(int pack, uint32_t *num);
+void pack_uint16_t(int pack, uint16_t *num);
+void pack_usb_device(int pack, struct usb_device *udev);
+void pack_usb_interface(int pack, struct usb_interface *uinf);
+
+ssize_t usbip_recv(int sockfd, void *buff, size_t bufflen);
+ssize_t usbip_send(int sockfd, void *buff, size_t bufflen);
+int usbip_send_op_common(int sockfd, uint32_t code, uint32_t status);
+int usbip_recv_op_common(int sockfd, uint16_t *code);
+int usbip_set_reuseaddr(int sockfd);
+int usbip_set_nodelay(int sockfd);
+int usbip_set_keepalive(int sockfd);
+
+int tcp_connect(char *hostname, char *service);
+
+#define USBIP_PORT 3240
+#define USBIP_PORT_STRING "3240"
+
+#endif
diff --git a/drivers/staging/usbip/userspace/src/usbipd.c b/drivers/staging/usbip/userspace/src/usbipd.c
new file mode 100644
index 0000000..ec9faac
--- /dev/null
+++ b/drivers/staging/usbip/userspace/src/usbipd.c
@@ -0,0 +1,570 @@
+/*
+ *
+ * Copyright (C) 2005-2007 Takahiro Hirofuchi
+ */
+
+#ifdef HAVE_CONFIG_H
+#include "../config.h"
+#endif
+
+#include <unistd.h>
+#include <netdb.h>
+#include <strings.h>
+#include <stdlib.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <arpa/inet.h>
+#include <sys/socket.h>
+#include <netinet/in.h>
+
+#ifdef HAVE_LIBWRAP
+#include <tcpd.h>
+#endif
+
+#define _GNU_SOURCE
+#include <getopt.h>
+#include <signal.h>
+
+#include "usbip.h"
+#include "usbip_network.h"
+
+#include <glib.h>
+
+static const char version[] = PACKAGE_STRING;
+
+
+static int send_reply_devlist(int sockfd)
+{
+ int ret;
+ struct usbip_exported_device *edev;
+ struct op_devlist_reply reply;
+
+
+ reply.ndev = 0;
+
+ /* how many devices are exported ? */
+ dlist_for_each_data(stub_driver->edev_list, edev, struct usbip_exported_device) {
+ reply.ndev += 1;
+ }
+
+ dbg("%d devices are exported", reply.ndev);
+
+ ret = usbip_send_op_common(sockfd, OP_REP_DEVLIST, ST_OK);
+ if (ret < 0) {
+ err("send op_common");
+ return ret;
+ }
+
+ PACK_OP_DEVLIST_REPLY(1, &reply);
+
+ ret = usbip_send(sockfd, (void *) &reply, sizeof(reply));
+ if (ret < 0) {
+ err("send op_devlist_reply");
+ return ret;
+ }
+
+ dlist_for_each_data(stub_driver->edev_list, edev, struct usbip_exported_device) {
+ struct usb_device pdu_udev;
+
+ dump_usb_device(&edev->udev);
+ memcpy(&pdu_udev, &edev->udev, sizeof(pdu_udev));
+ pack_usb_device(1, &pdu_udev);
+
+ ret = usbip_send(sockfd, (void *) &pdu_udev, sizeof(pdu_udev));
+ if (ret < 0) {
+ err("send pdu_udev");
+ return ret;
+ }
+
+ for (int i=0; i < edev->udev.bNumInterfaces; i++) {
+ struct usb_interface pdu_uinf;
+
+ dump_usb_interface(&edev->uinf[i]);
+ memcpy(&pdu_uinf, &edev->uinf[i], sizeof(pdu_uinf));
+ pack_usb_interface(1, &pdu_uinf);
+
+ ret = usbip_send(sockfd, (void *) &pdu_uinf, sizeof(pdu_uinf));
+ if (ret < 0) {
+ err("send pdu_uinf");
+ return ret;
+ }
+ }
+ }
+
+ return 0;
+}
+
+
+static int recv_request_devlist(int sockfd)
+{
+ int ret;
+ struct op_devlist_request req;
+
+ bzero(&req, sizeof(req));
+
+ ret = usbip_recv(sockfd, (void *) &req, sizeof(req));
+ if (ret < 0) {
+ err("recv devlist request");
+ return -1;
+ }
+
+ ret = send_reply_devlist(sockfd);
+ if (ret < 0) {
+ err("send devlist reply");
+ return -1;
+ }
+
+ return 0;
+}
+
+
+static int recv_request_import(int sockfd)
+{
+ int ret;
+ struct op_import_request req;
+ struct op_common reply;
+ struct usbip_exported_device *edev;
+ int found = 0;
+ int error = 0;
+
+ bzero(&req, sizeof(req));
+ bzero(&reply, sizeof(reply));
+
+ ret = usbip_recv(sockfd, (void *) &req, sizeof(req));
+ if (ret < 0) {
+ err("recv import request");
+ return -1;
+ }
+
+ PACK_OP_IMPORT_REQUEST(0, &req);
+
+ dlist_for_each_data(stub_driver->edev_list, edev, struct usbip_exported_device) {
+ if (!strncmp(req.busid, edev->udev.busid, SYSFS_BUS_ID_SIZE)) {
+ dbg("found requested device %s", req.busid);
+ found = 1;
+ break;
+ }
+ }
+
+ if (found) {
+ /* should set TCP_NODELAY for usbip */
+ usbip_set_nodelay(sockfd);
+
+ /* export_device needs a TCP/IP socket descriptor */
+ ret = usbip_stub_export_device(edev, sockfd);
+ if (ret < 0)
+ error = 1;
+ } else {
+ info("not found requested device %s", req.busid);
+ error = 1;
+ }
+
+
+ ret = usbip_send_op_common(sockfd, OP_REP_IMPORT, (!error ? ST_OK : ST_NA));
+ if (ret < 0) {
+ err("send import reply");
+ return -1;
+ }
+
+ if (!error) {
+ struct usb_device pdu_udev;
+
+ memcpy(&pdu_udev, &edev->udev, sizeof(pdu_udev));
+ pack_usb_device(1, &pdu_udev);
+
+ ret = usbip_send(sockfd, (void *) &pdu_udev, sizeof(pdu_udev));
+ if (ret < 0) {
+ err("send devinfo");
+ return -1;
+ }
+ }
+
+ return 0;
+}
+
+
+
+static int recv_pdu(int sockfd)
+{
+ int ret;
+ uint16_t code = OP_UNSPEC;
+
+
+ ret = usbip_recv_op_common(sockfd, &code);
+ if (ret < 0) {
+ err("recv op_common, %d", ret);
+ return ret;
+ }
+
+
+ ret = usbip_stub_refresh_device_list();
+ if (ret < 0)
+ return -1;
+
+ switch(code) {
+ case OP_REQ_DEVLIST:
+ ret = recv_request_devlist(sockfd);
+ break;
+
+ case OP_REQ_IMPORT:
+ ret = recv_request_import(sockfd);
+ break;
+
+ case OP_REQ_DEVINFO:
+ case OP_REQ_CRYPKEY:
+
+ default:
+ err("unknown op_code, %d", code);
+ ret = -1;
+ }
+
+
+ return ret;
+}
+
+
+
+
+static void log_addrinfo(struct addrinfo *ai)
+{
+ int ret;
+ char hbuf[NI_MAXHOST];
+ char sbuf[NI_MAXSERV];
+
+ ret = getnameinfo(ai->ai_addr, ai->ai_addrlen, hbuf, sizeof(hbuf),
+ sbuf, sizeof(sbuf), NI_NUMERICHOST | NI_NUMERICSERV);
+ if (ret)
+ err("getnameinfo, %s", gai_strerror(ret));
+
+ info("listen at [%s]:%s", hbuf, sbuf);
+}
+
+static struct addrinfo *my_getaddrinfo(char *host, int ai_family)
+{
+ int ret;
+ struct addrinfo hints, *ai_head;
+
+ bzero(&hints, sizeof(hints));
+
+ hints.ai_family = ai_family;
+ hints.ai_socktype = SOCK_STREAM;
+ hints.ai_flags = AI_PASSIVE;
+
+ ret = getaddrinfo(host, USBIP_PORT_STRING, &hints, &ai_head);
+ if (ret) {
+ err("%s: %s", USBIP_PORT_STRING, gai_strerror(ret));
+ return NULL;
+ }
+
+ return ai_head;
+}
+
+#define MAXSOCK 20
+static int listen_all_addrinfo(struct addrinfo *ai_head, int lsock[])
+{
+ struct addrinfo *ai;
+ int n = 0; /* number of sockets */
+
+ for (ai = ai_head; ai && n < MAXSOCK; ai = ai->ai_next) {
+ int ret;
+
+ lsock[n] = socket(ai->ai_family, ai->ai_socktype, ai->ai_protocol);
+ if (lsock[n] < 0)
+ continue;
+
+ usbip_set_reuseaddr(lsock[n]);
+ usbip_set_nodelay(lsock[n]);
+
+ if (lsock[n] >= FD_SETSIZE) {
+ close(lsock[n]);
+ lsock[n] = -1;
+ continue;
+ }
+
+ ret = bind(lsock[n], ai->ai_addr, ai->ai_addrlen);
+ if (ret < 0) {
+ close(lsock[n]);
+ lsock[n] = -1;
+ continue;
+ }
+
+ ret = listen(lsock[n], SOMAXCONN);
+ if (ret < 0) {
+ close(lsock[n]);
+ lsock[n] = -1;
+ continue;
+ }
+
+ log_addrinfo(ai);
+
+ /* next if succeed */
+ n++;
+ }
+
+ if (n == 0) {
+ err("no socket to listen to");
+ return -1;
+ }
+
+ dbg("listen %d address%s", n, (n==1)?"":"es");
+
+ return n;
+}
+
+#ifdef HAVE_LIBWRAP
+static int tcpd_auth(int csock)
+{
+ int ret;
+ struct request_info request;
+
+ request_init(&request, RQ_DAEMON, "usbipd", RQ_FILE, csock, 0);
+
+ fromhost(&request);
+
+ ret = hosts_access(&request);
+ if (!ret)
+ return -1;
+
+ return 0;
+}
+#endif
+
+static int my_accept(int lsock)
+{
+ int csock;
+ struct sockaddr_storage ss;
+ socklen_t len = sizeof(ss);
+ char host[NI_MAXHOST], port[NI_MAXSERV];
+ int ret;
+
+ bzero(&ss, sizeof(ss));
+
+ csock = accept(lsock, (struct sockaddr *) &ss, &len);
+ if (csock < 0) {
+ err("accept");
+ return -1;
+ }
+
+ ret = getnameinfo((struct sockaddr *) &ss, len,
+ host, sizeof(host), port, sizeof(port),
+ (NI_NUMERICHOST | NI_NUMERICSERV));
+ if (ret)
+ err("getnameinfo, %s", gai_strerror(ret));
+
+#ifdef HAVE_LIBWRAP
+ ret = tcpd_auth(csock);
+ if (ret < 0) {
+ info("deny access from %s", host);
+ close(csock);
+ return -1;
+ }
+#endif
+
+ info("connected from %s:%s", host, port);
+
+ return csock;
+}
+
+
+GMainLoop *main_loop;
+
+static void signal_handler(int i)
+{
+ dbg("signal catched, code %d", i);
+
+ if (main_loop)
+ g_main_loop_quit(main_loop);
+}
+
+static void set_signal(void)
+{
+ struct sigaction act;
+
+ bzero(&act, sizeof(act));
+ act.sa_handler = signal_handler;
+ sigemptyset(&act.sa_mask);
+ sigaction(SIGTERM, &act, NULL);
+ sigaction(SIGINT, &act, NULL);
+}
+
+
+gboolean process_comming_request(GIOChannel *gio, GIOCondition condition,
+ gpointer data __attribute__((unused)))
+{
+ int ret;
+
+ if (condition & (G_IO_ERR | G_IO_HUP | G_IO_NVAL))
+ g_error("unknown condition");
+
+
+ if (condition & G_IO_IN) {
+ int lsock;
+ int csock;
+
+ lsock = g_io_channel_unix_get_fd(gio);
+
+ csock = my_accept(lsock);
+ if (csock < 0)
+ return TRUE;
+
+ ret = recv_pdu(csock);
+ if (ret < 0)
+ err("process recieved pdu");
+
+ close(csock);
+ }
+
+ return TRUE;
+}
+
+
+static void do_standalone_mode(gboolean daemonize)
+{
+ int ret;
+ int lsock[MAXSOCK];
+ struct addrinfo *ai_head;
+ int n;
+
+
+
+ ret = usbip_names_init(USBIDS_FILE);
+ if (ret)
+ err("open usb.ids");
+
+ ret = usbip_stub_driver_open();
+ if (ret < 0)
+ g_error("driver open failed");
+
+ if (daemonize) {
+ if (daemon(0,0) < 0)
+ g_error("daemonizing failed: %s", g_strerror(errno));
+
+ usbip_use_syslog = 1;
+ }
+
+ set_signal();
+
+ ai_head = my_getaddrinfo(NULL, PF_UNSPEC);
+ if (!ai_head)
+ return;
+
+ n = listen_all_addrinfo(ai_head, lsock);
+ if (n <= 0)
+ g_error("no socket to listen to");
+
+ for (int i = 0; i < n; i++) {
+ GIOChannel *gio;
+
+ gio = g_io_channel_unix_new(lsock[i]);
+ g_io_add_watch(gio, (G_IO_IN | G_IO_ERR | G_IO_HUP | G_IO_NVAL),
+ process_comming_request, NULL);
+ }
+
+
+ info("usbipd start (%s)", version);
+
+
+ main_loop = g_main_loop_new(FALSE, FALSE);
+ g_main_loop_run(main_loop);
+
+ info("shutdown");
+
+ freeaddrinfo(ai_head);
+ usbip_names_free();
+ usbip_stub_driver_close();
+
+ return;
+}
+
+
+static const char help_message[] = "\
+Usage: usbipd [options] \n\
+ -D, --daemon \n\
+ Run as a daemon process. \n\
+ \n\
+ -d, --debug \n\
+ Print debugging information. \n\
+ \n\
+ -v, --version \n\
+ Show version. \n\
+ \n\
+ -h, --help \n\
+ Print this help. \n";
+
+static void show_help(void)
+{
+ printf("%s", help_message);
+}
+
+static const struct option longopts[] = {
+ {"daemon", no_argument, NULL, 'D'},
+ {"debug", no_argument, NULL, 'd'},
+ {"version", no_argument, NULL, 'v'},
+ {"help", no_argument, NULL, 'h'},
+ {NULL, 0, NULL, 0}
+};
+
+int main(int argc, char *argv[])
+{
+ gboolean daemonize = FALSE;
+
+ enum {
+ cmd_standalone_mode = 1,
+ cmd_help,
+ cmd_version
+ } cmd = cmd_standalone_mode;
+
+
+ usbip_use_stderr = 1;
+ usbip_use_syslog = 0;
+
+ if (geteuid() != 0)
+ g_warning("running non-root?");
+
+ for (;;) {
+ int c;
+ int index = 0;
+
+ c = getopt_long(argc, argv, "vhdD", longopts, &index);
+
+ if (c == -1)
+ break;
+
+ switch (c) {
+ case 'd':
+ usbip_use_debug = 1;
+ continue;
+ case 'v':
+ cmd = cmd_version;
+ break;
+ case 'h':
+ cmd = cmd_help;
+ break;
+ case 'D':
+ daemonize = TRUE;
+ break;
+ case '?':
+ show_help();
+ exit(EXIT_FAILURE);
+ default:
+ err("getopt");
+ }
+ }
+
+ switch (cmd) {
+ case cmd_standalone_mode:
+ do_standalone_mode(daemonize);
+ break;
+ case cmd_version:
+ printf("%s\n", version);
+ break;
+ case cmd_help:
+ show_help();
+ break;
+ default:
+ info("unknown cmd");
+ show_help();
+ }
+
+ return 0;
+}
diff --git a/drivers/staging/usbip/userspace/src/utils.c b/drivers/staging/usbip/userspace/src/utils.c
new file mode 100644
index 0000000..8f44108
--- /dev/null
+++ b/drivers/staging/usbip/userspace/src/utils.c
@@ -0,0 +1,255 @@
+/*
+ *
+ * Copyright (C) 2005-2007 Takahiro Hirofuchi
+ */
+
+#include "utils.h"
+
+int read_integer(char *path)
+{
+ char buff[100];
+ int fd;
+ int ret = 0;
+
+ bzero(buff, sizeof(buff));
+
+ fd = open(path, O_RDONLY);
+ if (fd < 0)
+ return -1;
+
+ ret = read(fd, buff, sizeof(buff));
+ if (ret < 0) {
+ close(fd);
+ return -1;
+ }
+
+ sscanf(buff, "%d", &ret);
+
+ close(fd);
+
+ return ret;
+}
+
+int read_string(char *path, char *string, size_t len)
+{
+ int fd;
+ int ret = 0;
+ char *p;
+
+ bzero(string, len);
+
+ fd = open(path, O_RDONLY);
+ if (fd < 0) {
+ string = NULL;
+ return -1;
+ }
+
+ ret = read(fd, string, len-1);
+ if (ret < 0) {
+ string = NULL;
+ close(fd);
+ return -1;
+ }
+
+ p = strchr(string, '\n');
+ *p = '\0';
+
+ close(fd);
+
+ return 0;
+}
+
+int write_integer(char *path, int value)
+{
+ int fd;
+ int ret;
+ char buff[100];
+
+ snprintf(buff, sizeof(buff), "%d", value);
+
+ fd = open(path, O_WRONLY);
+ if (fd < 0)
+ return -1;
+
+ ret = write(fd, buff, strlen(buff));
+ if (ret < 0) {
+ close(fd);
+ return -1;
+ }
+
+ close(fd);
+
+ return 0;
+}
+
+int read_bConfigurationValue(char *busid)
+{
+ char path[PATH_MAX];
+
+ snprintf(path, PATH_MAX, "/sys/bus/usb/devices/%s/bConfigurationValue", busid);
+
+ return read_integer(path);
+}
+
+int write_bConfigurationValue(char *busid, int config)
+{
+ char path[PATH_MAX];
+
+ snprintf(path, PATH_MAX, "/sys/bus/usb/devices/%s/bConfigurationValue", busid);
+
+ return write_integer(path, config);
+}
+
+int read_bNumInterfaces(char *busid)
+{
+ char path[PATH_MAX];
+
+ snprintf(path, PATH_MAX, "/sys/bus/usb/devices/%s/bNumInterfaces", busid);
+
+ return read_integer(path);
+}
+
+int read_bDeviceClass(char *busid)
+{
+ char path[PATH_MAX];
+
+ snprintf(path, PATH_MAX, "/sys/bus/usb/devices/%s/bDeviceClass", busid);
+
+ return read_integer(path);
+}
+
+int getdriver(char *busid, int conf, int infnum, char *driver, size_t len)
+{
+ char path[PATH_MAX];
+ char linkto[PATH_MAX];
+ int ret;
+
+ snprintf(path, PATH_MAX, "/sys/bus/usb/devices/%s:%d.%d/driver", busid, conf, infnum);
+
+ /* readlink does not add NULL */
+ bzero(linkto, sizeof(linkto));
+ ret = readlink(path, linkto, sizeof(linkto)-1);
+ if (ret < 0) {
+ strncpy(driver, "none", len);
+ return -1;
+ } else {
+ strncpy(driver, basename(linkto), len);
+ return 0;
+ }
+}
+
+int getdevicename(char *busid, char *name, size_t len)
+{
+ char path[PATH_MAX];
+ char idProduct[10], idVendor[10];
+
+ snprintf(path, PATH_MAX, "/sys/bus/usb/devices/%s/idVendor", busid);
+ read_string(path, idVendor, sizeof(idVendor));
+
+ snprintf(path, PATH_MAX, "/sys/bus/usb/devices/%s/idProduct", busid);
+ read_string(path, idProduct, sizeof(idProduct));
+
+ if (!idVendor[0] || !idProduct[0])
+ return -1;
+
+ snprintf(name, len, "%s:%s", idVendor, idProduct);
+
+ return 0;
+}
+
+#define MAXLINE 100
+
+/* if this cannot read a whole line, return -1 */
+int readline(int sockfd, char *buff, int bufflen)
+{
+ int ret;
+ char c;
+ int index = 0;
+
+
+ while (index < bufflen) {
+ ret = read(sockfd, &c, sizeof(c));
+ if (ret < 0 && errno == EINTR)
+ continue;
+ if (ret <= 0) {
+ return -1;
+ }
+
+ buff[index] = c;
+
+ if ( index > 0 && buff[index-1] == '\r' && buff[index] == '\n') {
+ /* end of line */
+ buff[index-1] = '\0'; /* get rid of delimitor */
+ return index;
+ } else
+ index++;
+ }
+
+ return -1;
+}
+
+#if 0
+int writeline(int sockfd, char *str, int strlen)
+{
+ int ret;
+ int index = 0;
+ int len;
+ char buff[MAXLINE];
+
+ if (strlen + 3 > MAXLINE)
+ return -1;
+
+ strncpy(buff, str, strlen);
+ buff[strlen+1] = '\r';
+ buff[strlen+2] = '\n';
+ buff[strlen+3] = '\0';
+
+ len = strlen + 3;
+
+ while (len > 0) {
+ ret = write(sockfd, buff+index, len);
+ if (ret <= 0) {
+ return -1;
+ }
+
+ len -= ret;
+ index += ret;
+ }
+
+ return index;
+}
+#endif
+
+int writeline(int sockfd, char *str, int strlen)
+{
+ int ret;
+ int index = 0;
+ int len;
+ char buff[MAXLINE];
+
+ len = strnlen(str, strlen);
+
+ if (strlen + 2 > MAXLINE)
+ return -1;
+
+ memcpy(buff, str, strlen);
+ buff[strlen] = '\r';
+ buff[strlen+1] = '\n'; /* strlen+1 <= MAXLINE-1 */
+
+ len = strlen + 2;
+
+ while (len > 0) {
+ ret = write(sockfd, buff+index, len);
+ if (ret < 0 && errno == EINTR)
+ continue;
+ if (ret <= 0) {
+ return -1;
+ }
+
+ len -= ret;
+ index += ret;
+ }
+
+ return index;
+}
+
diff --git a/drivers/staging/usbip/userspace/src/utils.h b/drivers/staging/usbip/userspace/src/utils.h
new file mode 100644
index 0000000..6c29ae9
--- /dev/null
+++ b/drivers/staging/usbip/userspace/src/utils.h
@@ -0,0 +1,38 @@
+
+#ifdef HAVE_CONFIG_H
+#include "../config.h"
+#endif
+
+#define _GNU_SOURCE
+#include <string.h>
+#include <sys/un.h>
+#include <sys/types.h>
+#include <sys/socket.h>
+
+#include <sysfs/libsysfs.h>
+#include <glib.h>
+#include <unistd.h>
+#include <stdio.h>
+#include <sys/types.h>
+#include <sys/stat.h>
+#include <fcntl.h>
+#include <stdlib.h>
+#include <time.h>
+#include <errno.h>
+
+
+
+/* Be sync to kernel header */
+#define BUS_ID_SIZE 20
+
+int read_string(char *path, char *, size_t len);
+int read_integer(char *path);
+int getdevicename(char *busid, char *name, size_t len);
+int getdriver(char *busid, int conf, int infnum, char *driver, size_t len);
+int read_bNumInterfaces(char *busid);
+int read_bConfigurationValue(char *busid);
+int write_integer(char *path, int value);
+int write_bConfigurationValue(char *busid, int config);
+int read_bDeviceClass(char *busid);
+int readline(int sockfd, char *str, int strlen);
+int writeline(int sockfd, char *buff, int bufflen);
diff --git a/drivers/staging/usbip/userspace/usb.ids b/drivers/staging/usbip/userspace/usb.ids
new file mode 100644
index 0000000..b1f8744
--- /dev/null
+++ b/drivers/staging/usbip/userspace/usb.ids
@@ -0,0 +1,13209 @@
+#
+# List of USB ID's
+#
+# Maintained by Stephen J. Gowdy <gowdy@slac.stanford.edu>
+# If you have any new entries, send them to the maintainer.
+# Send entries as patches (diff -u old new).
+# The latest version can be obtained from
+# http://www.linux-usb.org/usb.ids
+#
+# $Id: usb.ids,v 1.346 2008/04/23 13:51:46 gowdy Exp $
+#
+
+# Vendors, devices and interfaces. Please keep sorted.
+
+# Syntax:
+# vendor vendor_name
+# device device_name <-- single tab
+# interface interface_name <-- two tabs
+
+0001 Fry's Electronics
+0002 Ingram
+0003 Club Mac
+0004 Nebraska Furniture Mart
+0145 Unknown
+ 0112 Card Reader
+0204 Chipsbank Microelectronics Co., Ltd
+ 6025 CBM2080 Flash drive controller
+ 6026 CBM1180 Flash drive controller
+02ad HUMAX Co., Ltd.
+ 138c PVR Mass Storage
+0386 LTS
+ 0001 PSX for USB Converter
+03e8 EndPoints, Inc.
+ 0004 SE401 WebCam
+ 0008 101 Ethernet [klsi]
+ 0015 USB ATAPI Enclosure
+ 2123 SiPix StyleCam Deluxe
+ 8004 Aox 99001
+03e9 Thesys Microelectronics
+03ea Data Broadcasting Corp.
+03eb Atmel Corp.
+ 2002 Mass Storage Device
+ 2015 at90usbkey sample firmware (HID keyboard)
+ 2018 at90usbkey sample firmware (CDC ACM)
+ 2019 stk525 sample firmware (microphone)
+ 201c at90usbkey sample firmware (HID mouse)
+ 201d at90usbkey sample firmware (HID generic)
+ 2022 at90usbkey sample firmware (composite device)
+ 2103 JTAG ICE mkII
+ 2104 AVR ISP mkII
+ 2107 AVR Dragon
+ 2ffb at90usb AVR DFU bootloader
+ 2ffd at89c5130/c5131 DFU bootloader
+ 2fff at89c5132/c51snd1c DFU bootloader
+ 3301 at43301 4-port Hub
+ 3312 4-port Hub
+ 5601 at76c510 Prism-II 802.11b Access Point
+ 5603 Cisco 7920 WiFi IP Phone
+ 6124 at91sam SAMBA bootloader
+ 7603 at76c503a D-Link DWL-120 802.11b Adapter
+ 7604 FastVNET
+ 7605 at76c503a 802.11b Adapter
+ 7606 at76c505 802.11b Adapter
+ 7611 at76c510 rfmd2948 802.11b Access Point
+ 7613 WL-1130 USB
+ 7614 AT76c505a Wireless Adapter
+03ec Iwatsu America, Inc.
+03ed Mitel Corp.
+03ee Mitsumi
+ 0000 CD-R/RW Drive
+ 2501 eHome Infrared Receiver
+ 2502 eHome Infrared Receiver
+ 5609 Japanese Keyboard
+ 641f WIF-0402C Bluetooth Adapter
+ 6438 Bluetooth Device
+ 6440 WML-C52APR Bluetooth Adapter
+ 6901 SmartDisk FDD
+ 6902 Floppy Disk Drive
+ 7500 CD-R/RW
+ ffff Dongle with BlueCore in DFU mode
+03f0 Hewlett-Packard
+ 0004 DeskJet 895c
+ 0011 OfficeJet G55
+ 0012 DeskJet 1125C Printer Port
+ 0024 KU-0316 Keyboard
+ 0101 ScanJet 4100c
+ 0102 PhotoSmart S20
+ 0104 DeskJet 880c/970c
+ 0105 ScanJet 4200c
+ 0107 CD-Writer Plus
+ 010c Multimedia Keyboard Hub
+ 0111 G55xi Printer/Scanner/Copier
+ 0117 LaserJet 3200
+ 011c hn210w 802.11b Adapter
+ 011d Integrated Bluetooth Module
+ 0121 HP49g+ Calculator
+ 0122 HID Internet Keyboard
+ 0201 ScanJet 6200c
+ 0202 PhotoSmart S20
+ 0204 DeskJet 815c
+ 0205 ScanJet 3300c
+ 0207 CD-Writer Plus 8200e
+ 020c Multimedia Keyboard
+ 0211 OfficeJet G85
+ 0212 DeskJet 1220C
+ 0217 LaserJet 2200
+ 0218 APOLLO P2500/2600
+ 2624 Pole Display (HP522 2 x 20 Line Display)
+ 0304 DeskJet 810c/812c
+ 0305 ScanJet 4300c
+ 0307 CD-Writer+ CD-4e
+ 0311 OfficeJet G85xi
+ 0312 Color Inkjet CP1700
+ 0314 designjet 30/130 series
+ 0317 LaserJet 1200
+ 0401 ScanJet 5200c
+ 0404 DeskJet 830c/832c
+ 0405 ScanJet 3400cse
+ 0411 OfficeJet G95
+ 0412 Printing Support
+ 0417 LaserJet 1200 series
+ 0504 DeskJet 885c
+ 0505 ScanJet 2100c
+ 0507 DVD+RW
+ 050c 5219 Wireless Keyboard
+ 0511 OfficeJet K60
+ 0512 DeckJet 450
+ 0517 LaserJet 1000
+ 051d integrated module with Bluetooth wireless technology.
+ 0601 ScanJet 6300c
+ 0604 DeskJet 840c
+ 0605 ScanJet 2200c
+ 0611 OfficeJet K60xi
+ 0612 business inkjet 3000
+ 0624 Bluetooth Dongle
+ 0701 ScanJet 5300c/5370c
+ 0704 DeskJet 825c
+ 0705 ScanJet 4400c
+ 0711 OfficeJet K80
+ 0712 DeskJet 1180c
+ 0714 Printing Support
+ 0801 ScanJet 7400c
+ 0804 DeskJet 816c
+ 0805 HP4470C
+ 0811 OfficeJet K80xi
+ 0817 LaserJet 3300
+ 0901 ScanJet 2300c
+ 0904 DeskJet 845c
+ 0912 Printing Support
+ 0917 LaserJet 3330
+ 0924 Modular Smartcard Keyboard
+ 0a01 ScanJet 2400c
+ 0a17 color LaserJet 3700
+ 0b01 Scanjet 82x0C
+ 0b17 Laserjet 2300d
+ 0c17 LaserJet 1010
+ 0c24 Bluetooth Dongle
+ 0d12 Officejet 9100 series
+ 0d17 LaserJet 1012
+ 0e17 LaserJet 1015
+ 0f11 OfficeJet V40
+ 0f12 Printing Support
+ 0f17 LaserJet 1150
+ 1001 Photo Scanner 1000
+ 1002 photosmart 140 series
+ 1004 DeskJet 970c/970cse
+ 1005 ScanJet 5400c
+ 1011 OfficeJet V40xi
+ 1016 Jornada 548 / iPAQ HW6515 Pocket PC
+ 1017 LaserJet 1300
+ 1024 Smart Card Keyboard
+ 1102 photosmart 240 series
+ 1104 DeskJet 959c
+ 1105 ScanJet 5470c
+ 1111 officejet v60
+ 1116 Jornada 568 Pocket PC
+ 1117 LaserJet 1300n
+ 1151 PSC-750xi Printer/Scanner/Copier
+ 1202 Photosmart 320 Series
+ 1204 DeskJet 930c
+ 1205 ScanJet 4500C/5550C
+ 1211 officejet v60xi
+ 1217 LaserJet 2300L
+ 1302 Photosmart 370 Series
+ 1305 ScanJet 4570c
+ 1311 OfficeJet V30
+ 1312 Deskjet 460
+ 1317 LaserJet 1005
+ 1405 Scanjet 3670
+ 1411 PSC 750
+ 1424 f2105 Monitor Hub
+ 1502 Photosmart 420 Series
+ 1504 DeskJet 920c
+ 1511 PSC 750xi
+ 1512 Printing Support
+ 1517 color LaserJet 3500
+ 1524 Smart Card Keyboard - KR
+ 1602 Photosmart 330 Series
+ 1604 DeskJet 940c
+ 1605 ScanJet 5530C Photosmart
+ 1611 psc 780
+ 1617 LaserJet 3015
+ 161d Wireless Rechargeable Optical Mouse (HID)
+ 1624 Smart Card Keyboard - JP
+ 1702 Photosmart 380 Series
+ 1704 deskjet 948C
+ 1705 ScanJet 5590
+ 1711 psc 780xi
+ 1712 Printing Support
+ 1717 LaserJet 3020
+ 171d Wireless (Bluetooth + WLAN) Interface [Integrated Module]
+ 1801 Inkjet P-2000U
+ 1802 Photosmart 470 Series
+ 1804 deskjet 916C
+ 1805 ScanJet 7650
+ 1811 PSC 720
+ 1817 LaserJet 3030
+ 181d integrated module with Bluetooth 2.0 wireless technology.
+ 1902 Photosmart A430 series
+ 1904 DeskJet 3820
+ 1911 OfficeJet V45
+ 1917 LaserJet 3380
+ 1a02 Photosmart A510 series
+ 1a11 officejet 5100 series
+ 1a17 color LaserJet 4650
+ 1b02 Photosmart A610 series
+ 1b04 deskjet 3810
+ 1b05 ScanJet 4850C/4890C
+ 1c02 Photosmart A710 series
+ 1c17 Color LaserJet 2550l
+ 1d02 Photosmart A310 series
+ 1d17 LaserJet 1320
+ 1e02 Photosmart A320 Printer series
+ 1e11 PSC-950
+ 1e17 LaserJet 1160 series
+ 1f02 Photosmart A440 Printer series
+ 1f11 PSC 920
+ 1f12 Officejet Pro K5300
+ 1f17 color LaserJet 5550
+ 2001 Floppy
+ 2002 Hub
+ 2004 DeskJet 640c
+ 2005 ScanJet 3570c
+ 2012 Officejet Pro K5400
+ 2102 photosmart 7345
+ 2104 DeskJet 630c
+ 2112 Officejet Pro L7500
+ 2202 photosmart 7600 series
+ 2205 ScanJet 3500c
+ 2212 Officejet Pro L7600
+ 2217 color LaserJet 9500 MFP
+ 2302 photosmart 7600 series
+ 2304 DeskJet 656c
+ 2305 ScanJet 3970c
+ 2311 officejet d series
+ 2312 Officejet Pro L7700
+ 2317 LaserJet 4350
+ 2402 photosmart 7700 series
+ 2405 ScanJet 4070 Photosmart
+ 2417 LaserJet 4250
+ 2424 LP1965 19" Monitor Hub
+ 2502 photosmart 7700 series
+ 2505 ScanJet 3770
+ 2512 Officejet Pro L7300
+ 2517 LaserJet 2410
+ 2524 LP3065 30" Monitor Hub
+ 2602 Photosmart A520 series
+ 2605 ScanJet 3800c
+ 2611 officejet 7100 series
+ 2617 Color LaserJet 2820 Series
+ 2702 Photosmart A620 series
+ 2704 Deskjet 915
+ 2717 Color LaserJet 2830
+ 2811 PSC-2100
+ 2817 Color LaserJet 2840
+ 2902 Photosmart A820 series
+ 2911 PSC 2200
+ 2917 LaserJet 2420
+ 2a11 PSC 2150 series
+ 2a17 LaserJet 2430
+ 2b11 PSC 2170 series
+ 2b17 LaserJet 1020
+ 2c17 Printing Support
+ 2d11 OfficeJet 6110
+ 2d17 Printing Support
+ 2e11 PSC 1000
+ 2e17 Printing Support
+ 2f11 PSC 1200
+ 2f17 EWS 2605dn
+ 3002 photosmart P1000
+ 3004 deskjet 980c
+ 3005 ScanJet 4670v
+ 3011 PSC 1100 series
+ 3017 Printing Support
+ 3102 PhotoSmart P1100 Printer w/ Card Reader
+ 3104 DeskJet 960c
+ 3111 officejet 4100 series
+ 3117 EWS 2605dtn
+ 3202 photosmart 1215
+ 3211 officejet 4105 series
+ 3217 LaserJet 3050
+ 3302 photosmart 1218
+ 3304 DeskJet 990c
+ 3317 LaserJet 3052
+ 3402 photosmart 1115
+ 3404 DeskJet 6122
+ 3417 LaserJet 3055
+ 3502 photosmart 230
+ 3504 DeskJet 6127c
+ 3511 PSC 2300
+ 3517 LaserJet 3390
+ 3602 photosmart 1315
+ 3611 PSC 2410 Photosmart
+ 3617 EWS 2605
+ 3711 PSC 2500
+ 3717 EWS UPD
+ 3802 photosmart 100
+ 3817 LaserJet P2015 Series
+ 3902 photosmart 130
+ 3a02 photosmart 7150
+ 3a11 OfficeJet 5500 series
+ 3a17 Printing Support
+ 3b02 photosmart 7150~
+ 3b11 PSC 1300 series
+ 3b17 LaserJet M1005 MFP
+ 3c02 PhotoSmart 7350
+ 3c11 PSC 1358
+ 3c17 EWS UPD
+ 3d02 photosmart 7350~
+ 3d11 OfficeJet 4215
+ 3e02 photosmart 7550
+ 3f02 photosmart 7550~
+ 3f11 PSC-1315/PSC-1317
+ 4002 PhotoSmart 720 / PhotoSmart 935 (storage)
+ 4004 cp1160
+ 4102 PhotoSmart 618
+ 4105 ScanJet 4370
+ 4111 Officejet 7200 series
+ 4117 Printing Support
+ 4202 PhotoSmart 812
+ 4205 Scanjet G3010
+ 4211 Officejet 7300 series
+ 4217 EWS CM1015
+ 4302 PhotoSmart 850 (ptp)
+ 4311 Officejet 7400 series
+ 4317 Color LaserJet CM1017
+ 4402 PhotoSmart 935 (ptp)
+ 4417 EWS UPD
+ 4502 PhotoSmart 945 (PTP mode)
+ 4505 ScanJet G4010
+ 4511 Photosmart 2600
+ 4517 EWS UPD
+ 4605 ScanJet G4050
+ 4611 Photosmart 2700
+ 4811 PSC 1600
+ 4911 PSC 2350
+ 4b11 Officejet 6200
+ 4c11 PSC 1500 series
+ 4c17 EWS UPD
+ 4d11 PSC 1400
+ 4d17 EWS UPD
+ 4e11 Photosmart 2570 series
+ 4f11 Officejet 5600 (USBHUB)
+ 5004 DeskJet 995c
+ 5011 Photosmart 3100 Series
+ 5017 EWS UPD
+ 5111 Photosmart 3200 Series
+ 5211 Photosmart 3300 Series
+ 5311 Officejet 6300
+ 5411 Officejet 4300
+ 5511 Deskjet F300 series
+ 5611 PhotoSmart C3180
+ 5617 LaserJet M1120 MFP
+ 5711 Photosmart C4100 series
+ 5717 LaserJet M1120n MFP
+ 5811 Photosmart C5100 series
+ 5817 LaserJet M1319f MFP
+ 5911 PhotoSmart C6180
+ 5a11 Photosmart C7100 series
+ 5b11 Officejet J2100 Series
+ 5c11 Photosmart C4200 Printer series
+ 5d11 Photosmart C5200 series
+ 5e11 Photosmart D7400 series
+ 6004 DeskJet 5550
+ 6102 Hewlett Packard Digital Camera
+ 6104 DeskJet 5650c
+ 6117 color LaserJet 3550
+ 6202 PhotoSmart 215
+ 6204 DeskJet 5150c
+ 6217 Color LaserJet 4700
+ 6302 PhotoSmart 318/612
+ 6317 Color LaserJet 4730mfp
+ 6402 PhotoSmart 715 (ptp)
+ 6411 Photosmart C8100 series
+ 6417 LaserJet 5200
+ 6502 PhotoSmart 120 (ptp)
+ 6511 Photosmart C7200 series
+ 6602 PhotoSmart 320
+ 6611 Photosmart C4380 series
+ 6617 LaserJet 5200L
+ 6702 PhotoSmart 720 (ptp)
+ 6717 Color LaserJet 3000
+ 6802 PhotoSmart 620 (ptp)
+ 6811 Photosmart D5300 series
+ 6817 Color LaserJet 3800
+ 6911 Photosmart D7200 series
+ 6917 Color LaserJet 3600
+ 6a02 PhotoSmart 735 (ptp)
+ 6a11 Photosmart C6200 series
+ 6a17 LaserJet 4240
+ 6b02 PhotoSmart R707 (PTP mode)
+ 6c17 Color LaserJet 4610
+ 6f17 Color LaserJet CP6015 series
+ 7004 DeskJet 3320c
+ 7102 PhotoSmart 635 (PTP mode)
+ 7104 DeskJet 3420c
+ 7117 CM8060 Color MFP with Edgeline Technology
+ 7202 PhotoSmart 43x (ptp)
+ 7204 DeskJet 36xx
+ 7217 LaserJet M5035 MFP
+ 7302 PhotoSmart M307 (PTP mode)
+ 7304 DeskJet 35xx
+ 7317 LaserJet P3005
+ 7404 Printing Support
+ 7417 LaserJet M4345 MFP
+ 7504 Printing Support
+ 7517 LaserJet M3035 MFP
+ 7604 Deskjet 3940
+ 7617 LaserJet P3004
+ 7702 PhotoSmart R817 (PTP mode)
+ 7704 Deskjet D4100
+ 7717 CM8050 Color MFP with Edgeline Technology
+ 7804 Deskjet D1360
+ 7817 Color LaserJet CP3505
+ 7917 LaserJet M5025 MFP
+ 7a02 PhotoSmart M415 (PTP mode)
+ 7a17 LaserJet M3027 MFP
+ 7b02 PhotoSmart M23 (PTP mode)
+ 7b17 Color LaserJet CP4005
+ 7c17 Color LaserJet CM6040 Series
+ 7d04 Deskjet F2100 Printer series
+ 7d17 Color LaserJet CM4730 MFP
+ 7e04 Deskjet F4100 Printer series
+ 8017 LaserJet P4515
+ 8104 Printing Support
+ 8117 LaserJet P4015
+ 811c Ethernet HN210E
+ 8204 Printing Support
+ 8217 LaserJet P4014
+ 8317 LaserJet M9050 MFP
+ 8404 Deskjet 6800 Series
+ 8417 LaserJet M9040 MFP
+ 8504 Deskjet 6600 Series
+ 8604 Deskjet 5440
+ 8704 deskjet 5900 series
+ 8804 Deskjet 6980 Series
+ 8904 Deskjet 6940 Series
+ 9002 Photosmart M437
+ 9102 Photosmart M537
+ 9302 Photosmart R930 series
+ 9402 Photosmart R837
+ 9502 Photosmart R840 series
+ 9602 Photosmart M730 series
+ 9702 Photosmart R740 series
+ 9802 Photosmart Mz60 series
+ 9902 Photosmart M630 series
+ 9a02 Photosmart E330 series
+ 9b02 Photosmart M540 series
+ 9c02 Photosmart M440 series
+ a004 DeskJet 5850c
+ b002 photosmart 7200 series
+ b102 photosmart 7200 series
+ b202 photosmart 7600 series
+ b302 photosmart 7600 series
+ b402 photosmart 7700 series
+ b502 photosmart 7700 series
+ b602 photosmart 7900 series
+ b702 photosmart 7900 series
+ b802 Photosmart 7400 Series
+ b902 Photosmart 7800 Series
+ ba02 Photosmart 8100 Series
+ bb02 Photosmart 8400 Series
+ bc02 Photosmart 8700 Series
+ bd02 Photosmart Pro B9100 series
+ bef4 NEC Picty760
+ c002 Photosmart 7800 Series
+ c102 Photosmart 8000 Series
+ c202 Photosmart 8200 Series
+ c302 Deskjet D2300
+ c402 Photosmart D5100 series
+ c502 Photosmart D6100 series
+ c602 Photosmart D7100 series
+ c702 Photosmart D7300 series
+ c802 Photosmart D5060 Printer
+ d104 Bluetooth Dongle
+ efbe NEC Picty900
+ f0be NEC Picty920
+ f1be NEC Picty800
+03f1 Genoa Technology
+03f2 Oak Technology, Inc.
+03f3 Adaptec, Inc.
+ 0020 AWN-8020 WLAN
+ 0080 AVC-1100 Audio Capture
+ 0083 AVC-2200 Device
+ 0087 AVC-2210 Loader
+ 0088 AVC-2210 Device
+ 008b AVC-2310 Loader
+ 008c AVC-2310 Device
+ 0094 eHome Infrared Receiver
+ 009b AVC-1410 GameBridge TV NTSC
+ 2000 USBXchange
+ 2001 USBXchange Adapter
+ 2002 USB2-Xchange
+ 2003 USB2-Xchange Adapter
+ adcc Composite Device Support
+03f4 Diebold, Inc.
+03f5 Siemens Electromechanical
+03f8 Epson Imaging Technology Center
+03f9 KeyTronic Corp.
+ 0100 Keyboard
+ 0101 Keyboard
+ 0102 Keyboard Mouse
+03fb OPTi, Inc.
+03fc Elitegroup Computer Systems
+03fd Xilinx, Inc.
+03fe Farallon Comunications
+0400 National Semiconductor Corp.
+ 0807 Bluetooth Dongle
+ 080a Bluetooth Device
+ 1000 Mustek BearPaw 1200 Scanner
+ 1001 Mustek BearPaw 2400 Scanner
+ 1237 Hub
+ a000 Smart Display Reference Device
+ c35b Printing Support
+0401 National Registry, Inc.
+0402 ALi Corp.
+ 5462 M5462 IDE Controller
+ 5602 Video Camera Controller
+ 5603 USB 2.0 Q-tec Webcam 300
+ 5621 USB 2.0 Storage Device
+ 5623 VistaScan Astra 3600
+ 5627 Welland ME-740PS USB2 3.5" Power Saving Enclosure
+ 5632 USB 2.0 Host-to-Host Link
+ 5635 USB 2.0 Flash Card Reader
+ 5636 USB 2.0 Storage Device
+ 5637 M5637 IDE Controller
+0403 Future Technology Devices International, Ltd
+ 0000 H4SMK 7 Port Hub
+ 0232 Serial Converter
+ 6001 FT232 USB-Serial (UART) IC
+ 6007 Serial Converter
+ 6008 Serial Converter
+ 6009 Serial Converter
+ 6010 FT2232C Dual USB-UART/FIFO IC
+ 8040 4 Port Hub
+ 8070 7 Port Hub
+ 8370 7 Port Hub
+ 8371 PS/2 Keyboard And Mouse
+ 8372 FT8U100AX Serial Port
+ c630 lcd2usb interface
+ c7d0 RR-CirKits LocoBuffer-USB
+ cc48 product FTDI TACTRIX_OPENPORT_13M 0xcc48 OpenPort 1.3 Mitsubishi
+ cc49 product FTDI TACTRIX_OPENPORT_13S 0xcc49 OpenPort 1.3 Subaru
+ cc4a product FTDI TACTRIX_OPENPORT_13U 0xcc4a OpenPort 1.3 Universal
+ d010 SCS PTC-IIusb
+ d011 SCS Position-Tracker/TNC
+ d012 SCS DRAGON 1
+ d013 SCS DRAGON 1
+ d6f8 UNI Black BOX
+ e700 Elster Unicom III Optical Probe
+ e888 Expert ISDN Control USB
+ e889 USB-RS232 OptoBridge
+ e88a Expert mouseCLOCK USB II
+ e88b Precision Clock MSF USB
+ e88c Expert mouseCLOCK USB II HBG
+ ea90 Eclo 1-Wire Adapter
+ f208 Papenmeier Braille-Display
+ f680 Suunto Sports Instrument
+ f918 Ant8 Logic Probe
+ fa00 Matrix Orbital USB Serial
+ fa01 Matrix Orbital MX2 or MX3
+ fa02 Matrix Orbital MX4 or MX5
+ fa03 Matrix Orbital VK/LK202 Family
+ fa04 Matrix Orbital VK/LK204 Family
+ fc08 Crystalfontz CFA-632 USB LCD
+ fc09 Crystalfontz CFA-634 USB LCD
+ fc0b Crystalfontz CFA-633 USB LCD
+ fc0c Crystalfontz CFA-631 USB LCD
+ fc0d Crystalfontz CFA-635 USB LCD
+ fc82 SEMC DSS-20 SyncStation
+ fd48 ShipModul MiniPlex-4xUSB NMEA Multiplexer
+ ff08 ToolHouse LoopBack Adapter
+ ff18 Logbook Bus
+ ff19 Logbook Bus
+ ff1a Logbook Bus
+ ff1b Logbook Bus
+ ff1c Logbook Bus
+ ff1d Logbook Bus
+ ff1e Logbook Bus
+ ff1f Logbook Bus
+0404 NCR Corp.
+ 0202 78XX Scanner
+ 0203 78XX Scanner - Embedded System
+ 0310 K590 Printer, Self-Service
+ 0311 7167 Printer, Receipt/Slip
+ 0312 7197 Printer Receipt
+ 0320 5932-USB Keyboard
+ 0321 5953-USB Dynakey
+ 0322 5932-USB Enhanced Keyboard
+ 0323 5932-USB Enhanced Keyboard, Flash-Recovery/Download
+ 0324 5953-USB Enhanced Dynakey
+ 0325 5953-USB Enhanced Dynakey Flash-Recovery/Download
+ 0328 K016: USB-MSR ISO 3-track MSR: POS Standard (See HID pages)
+ 0329 K018: USB-MSR JIS 2-Track MSR: POS Standard
+ 032a K016: USB-MSR ISO 3-Track MSR: HID Keyboard Mode
+ 032b K016/K018: USB-MSR Flash-Recovery/Download
+0405 Synopsys, Inc.
+0406 Fujitsu-ICL Computers
+0407 Fujitsu Personal Systems, Inc.
+0408 Quanta Computer, Inc.
+0409 NEC Corp.
+ 0011 PC98 Series Layout Keyboard Mouse
+ 0012 ATerm IT75DSU ISDN TA
+ 0014 Japanese Keyboard
+ 0019 109 Japanese Keyboard with Bus-Powered Hub
+ 001a PC98 Series Layout Keyboard with Bus-Powered Hub
+ 0025 Mini Keyboard with Bus-Powered Hub
+ 0027 MultiSync Monitor
+ 002c Clik!-USB Drive
+ 0034 109 Japanese Keyboard with One-touch start buttons
+ 003f Wireless Keyboard with One-touch start buttons
+ 0040 Floppy
+ 004e SuperScript 1400 Series
+ 004f Wireless Keyboard with One-touch start buttons
+ 0058 HighSpeed Hub
+ 0059 HighSpeed Hub
+ 005a HighSpeed Hub
+ 006a Conceptronic USB Harddisk Box
+ 0081 SuperScript 1400 Series
+ 0082 SuperScript 1400 Series
+ 0094 Japanese Keyboard with One-touch start buttons
+ 0095 Japanese Keyboard
+ 00a9 AtermIT21L 128K Support Standard
+ 00aa AtermITX72 128K Support Standard
+ 00ab AtermITX62 128K Support Standard
+ 00ac AtermIT42 128K Support Standard
+ 00ae INSMATEV70G-MAX Standard
+ 00af AtermITX70 128K Support Standard
+ 00b0 AtermITX80 128K Support Standard
+ 00b2 AtermITX80D 128K Support Standard
+ 00c0 Wireless Remocon
+ 00f7 Smart Display PK-SD10
+ 011d e228 Mobile Phone
+ 0203 HID Audio Controls
+ 55aa Hub
+ 55ab Hub [iMac/iTouch kbd]
+ 8010 Intellibase Hub
+ 8011 Intellibase Hub
+ efbe P!cty 900 [HP DJ]
+ f0be P!cty 920 [HP DJ 812c]
+040a Kodak Co.
+ 0001 DVC-323
+ 0002 DVC-325
+ 0100 DC-220
+ 0110 DC-260
+ 0111 DC-265
+ 0112 DC-290
+ 0120 DC-240
+ 0121 DC-240 (PTP firmware)
+ 0130 DC-280
+ 0131 DC-5000
+ 0132 DC-3400
+ 0140 DC-4800
+ 0160 DC4800
+ 0170 DX3900
+ 0200 Digital Camera
+ 0300 EZ-200
+ 0400 MC3
+ 0402 Digital Camera
+ 0403 Z7590
+ 0500 DX3500
+ 0510 DX3600
+ 0525 DX3215
+ 0530 DX3700
+ 0535 EasyShare CX4230 Camera
+ 0540 LS420
+ 0550 DX4900
+ 0555 DX4330
+ 0560 CX4200
+ 0565 CX4210
+ 0566 CX4300
+ 0567 LS753
+ 0568 LS443
+ 0569 LS663
+ 0570 DX6340
+ 0571 CX6330
+ 0572 DX6440
+ 0573 CX6230
+ 0574 CX6200
+ 0575 DX6490
+ 0576 DX4530
+ 0577 DX7630
+ 0578 CX7300/CX7310
+ 0579 CX7220
+ 057a CX7330
+ 057b CX7430
+ 057c CX7530
+ 057d DX7440
+ 057e C300
+ 057f DX7590
+ 0580 Z730
+ 0581 Digital Camera
+ 0582 Digital Camera
+ 0583 Digital Camera
+ 0584 CX6445
+ 0585 Digital Camera
+ 0586 CX7525
+ 0587 Digital Camera
+ 0588 Digital Camera
+ 0589 EasyShare C360
+ 058a C310
+ 058b Digital Camera
+ 058c C330
+ 058d C340
+ 058e V530
+ 058f V550
+ 0590 Digital Camera
+ 0591 Digital Camera
+ 0592 Digital Camera
+ 0593 Digital Camera
+ 0594 Digital Camera
+ 0595 Digital Camera
+ 0596 Digital Camera
+ 0597 Digital Camera
+ 0598 Digital Camera
+ 0599 Digital Camera
+ 059a Digital Camera
+ 059b Digital Camera
+ 059c Digital Camera
+ 059d Digital Camera
+ 059e Digital Camera
+ 059f Digital Camera
+ 05a0 Digital Camera
+ 05a1 Digital Camera
+ 05a2 Digital Camera
+ 05a3 Digital Camera
+ 05a4 Digital Camera
+ 05a5 Digital Camera
+ 05a6 Digital Camera
+ 05a7 Digital Camera
+ 05a8 Digital Camera
+ 05a9 Digital Camera
+ 05aa Digital Camera
+ 05ab Digital Camera
+ 05ac Digital Camera
+ 05ad Digital Camera
+ 05ae Digital Camera
+ 05af Digital Camera
+ 05b0 Digital Camera
+ 05b1 Digital Camera
+ 05b2 Digital Camera
+ 05b3 EasyShare Z710 Camera
+ 05b4 Digital Camera
+ 05b5 Digital Camera
+ 05b6 Digital Camera
+ 05b7 Digital Camera
+ 05b8 Digital Camera
+ 05b9 Digital Camera
+ 05ba Digital Camera
+ 05bb Digital Camera
+ 05bc Digital Camera
+ 05bd Digital Camera
+ 05be Digital Camera
+ 05bf Digital Camera
+ 05c0 Digital Camera
+ 05c1 Digital Camera
+ 05c2 Digital Camera
+ 05c3 Digital Camera
+ 05c4 Digital Camera
+ 05c5 Digital Camera
+ 4000 InkJet Color Printer
+ 410d EasyShare G600 Printer Dock
+ 5010 Wireless Adapter
+ 5012 DBT-220 Bluetooth Adapter
+ 6001 i30
+ 6002 i40
+ 6003 i50
+ 6004 i60
+ 6005 i80
+040b Weltrend Semiconductor
+ 6510 Weltrend Bar Code Reader
+ 6520 XBOX Xploder
+040c VTech Computers, Ltd
+040d VIA Technologies, Inc.
+ 3184 VNT VT6656 USB-802.11 Wireless LAN Adapter
+ 6205 USB 2.0 Card Reader
+040e MCCI
+040f Echo Speech Corp.
+0411 MelCo., Inc.
+ 0001 LUA-TX Ethernet [pegasus]
+ 0005 LUA-TX Ethernet
+ 0006 WLI-USB-L11 Wireless LAN Adapter
+ 0009 LUA2-TX Ethernet
+ 000b WLI-USB-L11G-WR Wireless LAN Adapter
+ 000d WLI-USB-L11G Wireless LAN Adapter
+ 0012 LUA-KTX Ethernet
+ 0013 USB2-IDE Adapter
+ 0016 WLI-USB-S11 802.11b Adapter
+ 0018 USB2-IDE Adapter
+ 001c USB-IDE Bridge: DUB-PxxG
+ 0027 WLI-USB-KS11G 802.11b Adapter
+ 003d LUA-U2-KTX Ethernet
+ 0044 WLI-USB-KB11 Wireless LAN Adapter
+ 004d WLI-USB-B11 Wireless LAN Adapter
+ 0050 WLI2-USB2-G54 Wireless LAN Adapter
+ 005e WLI-U2-KG54-YB WLAN
+ 0065 Python2 WDM Encoder
+ 0066 WLI-U2-KG54 WLAN
+ 0067 WLI-U2-KG54-AI WLAN
+ 008b Nintendo Wi-Fi
+ 0091 WLI-U2-KAMG54 Wireless LAN Adapter
+ 0092 WLI-U2-KAMG54 Bootloader
+ 0097 WLI-U2-KG54-BB
+ 00a9 WLI-U2-AMG54HP Wireless LAN Adapter
+ 00aa WLI-U2-AMG54HP Bootloader
+ 00b3 PC-OP-RS1 RemoteStation
+ 00ca 802.11n Network Adapter
+ 00cb WLI-U2-G300N 802.11n Adapter
+ 00d8 WLI-U2-SG54HP
+ 00d9 WLI-U2-G54HP
+ 00da WLI-U2-KG54L
+0412 Award Software International
+0413 Leadtek Research, Inc.
+ 1310 WinFast TV - NTSC + FM
+ 1311 WinFast TV - NTSC + MTS + FM
+ 1312 WinFast TV - PAL BG + FM
+ 1313 WinFast TV - PAL BG+TXT + FM
+ 1314 WinFast TV Audio - PHP PAL I
+ 1315 WinFast TV Audio - PHP PAL I+TXT
+ 1316 WinFast TV Audio - PHP PAL DK
+ 1317 WinFast TV Audio - PHP PAL DK+TXT
+ 1318 WinFast TV - PAL I/DK + FM
+ 1319 WinFast TV - PAL N + FM
+ 131a WinFast TV Audio - PHP SECAM LL
+ 131b WinFast TV Audio - PHP SECAM LL+TXT
+ 131c WinFast TV Audio - PHP SECAM DK
+ 131d WinFast TV - SECAM DK + TXT + FM
+ 131e WinFast TV - NTSC Japan + FM
+ 1320 WinFast TV - NTSC
+ 1321 WinFast TV - NTSC + MTS
+ 1322 WinFast TV - PAL BG
+ 1323 WinFast TV - PAL BG+TXT
+ 1324 WinFast TV Audio - PHP PAL I
+ 1325 WinFast TV Audio - PHP PAL I+TXT
+ 1326 WinFast TV Audio - PHP PAL DK
+ 1327 WinFast TV Audio - PHP PAL DK+TXT
+ 1328 WinFast TV - PAL I/DK
+ 1329 WinFast TV - PAL N
+ 132a WinFast TV Audio - PHP SECAM LL
+ 132b WinFast TV Audio - PHP SECAM LL+TXT
+ 132c WinFast TV Audio - PHP SECAM DK
+ 132d WinFast TV - SECAM DK + TXT
+ 132e WinFast TV - NTSC Japan
+ 6023 EMP Audio Device
+ 6024 WinFast PalmTop/Novo TV Video
+ 6025 WinFast DTV Dongle (cold state)
+ 6026 WinFast DTV Dongle (warm state)
+ 6125 WinFast DTV Dongle
+ 6126 WinFast DTV Dongle BDA Driver
+ 6f00 WinFast DTV Dongle (STK7700P based)
+0414 Giga-Byte Technology Co., Ltd
+0416 Winbond Electronics Corp.
+ 0035 W89C35 802.11bg WLAN Adapter
+ 0101 Hub
+ 0961 AVL Flash Card Reader
+ 3810 Smart Card Controller
+ 3811 Generic Controller - Single interface
+ 3812 Smart Card Controller_2Interface
+ 3813 Panel Display
+ 5518 4-Port Hub
+ 551a PC Sync Keypad
+ 551b PC Async Keypad
+ 551c Sync Tenkey
+ 551d Async Tenkey
+ 551e Keyboard
+ 551f Keyboard w/ Sys and Media
+ 5521 Keyboard
+ 6481 16-bit Scanner
+ 7721 Memory Stick Reader/Writer
+ 7722 Memory Stick Reader/Writer
+ 7723 SD Card Reader
+0417 Symbios Logic
+0418 AST Research
+0419 Samsung Info. Systems America, Inc.
+ 0001 IrDA Remote Controller
+ 3001 Xerox P1202 Laser Printer
+ 3003 Olivetti PG L12L
+ 3201 Docuprint P8ex
+ 3404 SCX-5x12 Series
+ 3406 MFP 830 Series
+ 3407 ML-912
+ 3601 InkJet Color Printer
+ 3602 InkJet Color Printer
+ 4602 Remote NDIS Network Device
+ 8001 Hub
+ 8002 SyncMaster 757DFX HID Device
+041a Phoenix Technologies, Ltd
+041b d'TV
+041d S3, Inc.
+041e Creative Technology, Ltd
+ 1002 Nomad II
+ 1003 Blaster GamePad Cobra
+ 1050 GamePad Cobra
+ 3000 SoundBlaster Extigy
+ 3002 SB External Composite Device
+ 3010 SoundBlaster MP3+
+ 3014 SB External Composite Device
+ 3015 Sound Blaster Digital Music LX
+ 3020 SoundBlaster Audigy 2 NX
+ 3030 SB External Composite Device
+ 3040 SoundBlaster Live! 24-bit External SB0490
+ 3060 Sound Blaster Audigy 2 ZS External
+ 3061 SoundBlaster Audigy 2 ZS Video Editor
+ 3090 Sound Blaster Digital Music SX
+ 3f02 E-Mu 0202
+ 3f04 E-Mu 0404
+ 4003 VideoBlaster WebCam Go Plus [W9967CF]
+ 4004 Nomad II MG
+ 4005 WebCam Blaster Go ES
+ 4007 Go Mini
+ 400a PC-Cam 300
+ 400b PC-Cam 600
+ 400c WebCam 5 [pwc]
+ 400d WebCam PD1001
+ 400f PC-CAM 550 (Composite)
+ 4011 WebCam PRO eX
+ 4012 PC-CAM350
+ 4013 PC-Cam 750
+ 4015 CardCam Value
+ 4016 CardCam
+ 4017 WebCam Mobile
+ 4018 WebCam Vista
+ 4019 Audio Device
+ 401c WebCam NX [PD1110]
+ 401d WebCam NX Ultra
+ 401e WebCam NX Pro
+ 401f Webcam Notebook
+ 4020 WebCam NX
+ 4021 WebCam NX Ultra
+ 4022 WebCam NX Pro
+ 4028 Vista Plus cam [VF0090]
+ 402f DC-CAM 3000Z
+ 4034 WebCam Instant
+ 4035 WebCam Instant
+ 4036 Webcam Live!/Live! Pro
+ 4037 WebCam Live!
+ 4038 ORITE CCD Webcam(PC370R)
+ 4039 WebCam Live! Effects
+ 403a WebCam NX Pro 2
+ 403c WebCam Live! Ultra
+ 403d WebCam Notebook Ultra
+ 403e WebCam Vista Plus
+ 4041 WebCam Live! Motion
+ 4045 Live! Cam Voice
+ 4049 Live! Cam Voice
+ 4051 Live! Cam Notebook Pro
+ 4052 Live! Cam Vista IM
+ 4053 Live! Cam Video IM
+ 4054 Live! Cam Video IM
+ 4055 Live! Cam Video IM Pro
+ 4056 Live! Cam Video IM Pro
+ 4057 Live! Cam Optia
+ 4058 Live! Cam Optia AF
+ 4068 WebCam Live! Notebook
+ 4100 Nomad Jukebox 2
+ 4101 Nomad Jukebox 3
+ 4102 NOMAD MuVo^2
+ 4106 Nomad MuVo
+ 4107 NOMAD MuVo
+ 4108 Nomad Jukebox Zen
+ 4109 Nomad Jukebox Zen NX
+ 410b Nomad Jukebox Zen USB 2.0
+ 410c Nomad MuVo NX
+ 410f NOMAD MuVo^2 (Flash)
+ 4110 Nomad Jukebox Zen Xtra
+ 4111 Dell Digital Jukebox
+ 4116 MuVo^2
+ 4117 Nomad MuVo TX
+ 411b Zen Touch
+ 411c Nomad MuVo USB 2.0
+ 411d Zen
+ 411e Zen Micro
+ 4123 Zen Portable Media Center
+ 4124 MuVo^2 FM (uHDD)
+ 4126 Dell DJ (2nd gen)
+ 4127 Dell DJ
+ 4128 NOMAD Jukebox Zen Xtra (mtp)
+ 412b MuVo N200 with FM radio
+ 4130 Zen Micro (mtp)
+ 4131 Zen Touch (mtp)
+ 4133 Mass Storage Device
+ 4134 Zen Neeon
+ 4136 Zen Sleek
+ 4137 Zen Sleek (mtp)
+ 4139 Zen Nano Plus
+ 413c Zen MicroPhoto
+ 4151 Zen Vision:M (mtp)
+ 4155 Zen Stone plus
+ 500f Broadband Blaster 8012U-V
+ 5015 TECOM Bluetooth Device
+ ffff WebCam Live! Ultra
+041f LCS Telegraphics
+0420 Chips and Technologies
+ 1307 Celly SIM Card Reader
+0421 Nokia Mobile Phones
+ 0018 6288 GSM Smartphone
+ 0019 6288 GSM Smartphone (imaging mode)
+ 001a 6288 GSM Smartphone (file transfer mode)
+ 0024 5610 XpressMusic (Storage mode)
+ 0025 5610 XpressMusic (PC-Suite mode)
+ 0028 5610 XpressMusic (Imaging mode)
+ 0096 N810 Internet Tablet
+ 0103 ADL Flashing Engine AVALON Parent
+ 0104 ADL Re-Flashing Engine Parent
+ 0105 E-61 (Firmware update mode)
+ 0106 ROM Parent
+ 0400 7600 Phone Parent
+ 0401 6650 GSM Phone
+ 0402 6255 Phone Parent
+ 0404 5510
+ 0405 9500 GSM Communicator
+ 0407 Music Player HDR-1(tm)
+ 040b N-Gage GSM Phone
+ 040d 6620 Phone Parent
+ 040e 6651 Phone Parent
+ 040f 6230 GSM Phone
+ 0410 6630 Imaging Smartphone
+ 0411 7610 Phone Parent
+ 0413 6260 Phone Parent
+ 0414 7370
+ 0415 9300 GSM Smartphone
+ 0416 6170 Phone Parent
+ 0417 7270 Phone Parent
+ 0418 E-70 (PC-Suite mode)
+ 0419 E-60 (PC-Suite mode)
+ 041a 9500 GSM Communicator (RNDIS)
+ 041b 9300 GSM Smartphone (RNDIS)
+ 041c 7710 Phone Parent
+ 041d 6670 Phone Parent
+ 041e 6680
+ 041f 6235 Phone Parent
+ 0421 3230 Phone Parent
+ 0422 6681 Phone Parent
+ 0423 6682 Phone Parent
+ 0428 6230i Modem
+ 0429 6230i MultiMedia Card
+ 0431 770 Internet Tablet
+ 0432 N90 Phone Parent
+ 0435 E-70 (IP Passthrough/RNDIS mode)
+ 0436 E-60 (IP Passthrough/RNDIS mode)
+ 0437 6265 Phone Parent
+ 043a N70 USB Phone Parent
+ 043b 3155 Phone Parent
+ 043c 6155 Phone Parent
+ 043d 6270 Phone Parent
+ 0443 N70 Phone Parent
+ 044c NM850iG Phone Parent
+ 044d E-61 (PC Suite mode)
+ 044e E-61 (Data Exchange mode)
+ 044f E-61 (IP Passthrough/RNDIS mode)
+ 0453 9300 Phone Parent
+ 0456 6111 Phone Parent
+ 045a 6280 Phone Parent
+ 045d 6282 Phone Parent
+ 046e 6110 Navigator
+ 0485 MTP Device
+ 04c3 N800 Internet Tablet
+ 04ce E90 Communicator (PC-Suite mode)
+ 04cf E90 Communicator (Storage mode)
+ 04f9 6300 (PC-Suite mode)
+ 0600 Digital Pen SU-1B
+ 0800 Connectivity Cable DKU-5
+ 0801 Data Cable DKU-6
+ 0802 CA-42 Phone Parent
+0422 ADI Systems, Inc.
+0423 Computer Access Technology Corp.
+ 000a NetMate Ethernet
+ 000c NetMate2 Ethernet
+ 000d USB Chief Analyzer
+ 0100 Generic Universal Protocol Analyzer
+ 0101 UPA USBTracer
+ 0200 Generic 10K Universal Protocol Analyzer
+ 020a PETracer ML
+ 0300 Generic Universal Protocol Analyzer
+ 0301 2500H Tracer Trainer
+ 030a PETracer x1
+ 1237 Andromeda Hub
+0424 Standard Microsystems Corp.
+ 0001 Integrated Hub
+ 0acd Sitecom Internal Multi Memory reader/writer MD-005
+ 0fdc Floppy
+ 10cd Sitecom Internal Multi Memory reader/writer MD-005
+ 2020 USB Hub
+ 20cd Sitecom Internal Multi Memory reader/writer MD-005
+ 20fc 6-in-1 Card Reader
+ 2228 9-in-2 Card Reader
+ 223a 8-in-1 Card Reader
+ 2503 USB 2.0 Hub
+ 2504 USB 2.0 Hub
+ 2524 USB MultiSwitch Hub
+0425 Motorola Semiconductors HK, Ltd
+ 0101 G-Tech Wireless Mouse & Keyboard
+0426 Integrated Device Technology, Inc.
+ 0426 WDM Driver
+0427 Motorola Electronics Taiwan, Ltd
+0428 Advanced Gravis Computer Tech, Ltd
+ 4001 GamePad Pro
+0429 Cirrus Logic
+042a Ericsson Austrian, AG
+042b Intel Corp.
+ 9316 8x931Hx Customer Hub
+042c Innovative Semiconductors, Inc.
+042d Micronics
+042e Acer, Inc.
+ 0380 MP3 Player
+042f Molex, Inc.
+0430 Sun Microsystems, Inc.
+ 0002 109 Keyboard
+ 0005 Type 6 Keyboard
+ 000a 109 Japanese Keyboard
+ 000b 109 Japanese Keyboard
+ 0082 109 Japanese Keyboard
+ 0083 109 Japanese Keyboard
+ 0100 3-button Mouse
+ 36ba Bus Powered Hub
+0431 Itac Systems, Inc.
+ 0100 Mouse-Trak 3-button Track Ball
+0432 Unisys Corp.
+0433 Alps Electric, Inc.
+ 1101 IBM Game Controller
+ abab Keyboard
+0434 Samsung Info. Systems America, Inc.
+0435 Hyundai Electronics America
+0436 Taugagreining HF
+ 0005 CameraMate (DPCM_USB)
+0437 Framatome Connectors USA
+0438 Advanced Micro Devices, Inc.
+0439 Voice Technologies Group
+043d Lexmark International, Inc.
+ 0001 Laser Printer
+ 0002 Optra E310 Printer
+ 0003 Laser Printer
+ 0004 Laser Printer
+ 0005 Laser Printer
+ 0006 Laser Printer
+ 0007 Laser Printer
+ 0008 Inkjet Color Printer
+ 0009 Optra S2450 Printer
+ 000a Laser Printer
+ 000b Inkjet Color Printer
+ 000c Optra E312 Printer
+ 000d Laser Printer
+ 000e Laser Printer
+ 000f Laser Printer
+ 0010 Laser Printer
+ 0011 Laser Printer
+ 0012 Inkjet Color Printer
+ 0013 Inkjet Color Printer
+ 0014 InkJet Color Printer
+ 0015 InkJet Color Printer
+ 0016 Z12 Color Jetprinter
+ 0017 Z32 printer
+ 0018 Z52 Printer
+ 0019 Forms Printer
+ 001a Z65 Printer
+ 001b InkJet Photo Printer
+ 001c Kodak Personal Picture Maker 200 Printer
+ 001d InkJet Color Printer
+ 001e InkJet Photo Printer
+ 001f Kodak Personal Picture Maker 200 Card Reader
+ 0020 Z51 Printer
+ 0021 Z33 Printer
+ 0022 InkJet Color Printer
+ 0023 Laser Printer
+ 0024 Laser Printer
+ 0025 InkJet Color Printer
+ 0026 InkJet Color Printer
+ 0027 InkJet Color Printer
+ 0028 InkJet Color Printer
+ 0029 Scan Print Copy
+ 002a Scan Print Copy
+ 002b Scan Print Copy
+ 002c Scan Print Copy
+ 002d X70/X73 Scan/Print/Copy
+ 002e Scan Print Copy
+ 002f Scan Print Copy
+ 0030 Scan Print Copy
+ 0031 Scan Print Copy
+ 0032 Scan Print Copy
+ 0033 Scan Print Copy
+ 0034 Scan Print Copy
+ 0035 Scan Print Copy
+ 0036 Scan Print Copy
+ 0037 Scan Print Copy
+ 0038 Scan Print Copy
+ 0039 Scan Print Copy
+ 003a Scan Print Copy
+ 003b Scan Print Copy
+ 003c Scan Print Copy
+ 003d X83 Scan/Print/Copy
+ 003e Scan Print Copy
+ 003f Scan Print Copy
+ 0040 Scan Print Copy
+ 0041 Scan Print Copy
+ 0042 Scan Print Copy
+ 0043 Scan Print Copy
+ 0044 Scan Print Copy
+ 0045 Scan Print Copy
+ 0046 Scan Print Copy
+ 0047 Scan Print Copy
+ 0048 Scan Print Copy
+ 0049 Scan Print Copy
+ 004a Scan Print Copy
+ 004b Scan Print Copy
+ 004c Scan Print Copy
+ 004d Laser Printer
+ 004e Laser Printer
+ 004f InkJet Color Printer
+ 0050 InkJet Color Printer
+ 0051 Laser Printer
+ 0052 Laser Printer
+ 0053 InkJet Color Printer
+ 0054 InkJet Color Printer
+ 0057 Z35 Printer
+ 0058 Laser Printer
+ 005a X63
+ 005c InkJet Color Printer
+ 0060 X74/X75 Scanner
+ 0061 X74 Hub
+ 0065 X5130
+ 0069 X74/X75 Printer
+ 006d X125
+ 0072 X6170 Printer
+ 0073 InkJet Color Printer
+ 0078 InkJet Color Printer
+ 0079 InkJet Color Printer
+ 007a Generic Hub
+ 007b InkJet Color Printer
+ 007c Lexmark X1110/X1130/X1140/X1150/X1170/X1180/X1185
+ 007d Photo 3150
+ 008a 4200 Series
+ 008b InkJet Color Printer
+ 008c to CF/SM/SD/MS Card Reader
+ 008e InkJet Color Printer
+ 008f X422
+ 0093 X5250
+ 0095 E220 Printer
+ 0096 2200 Series
+ 0097 P6250
+ 0098 7100 Series
+ 009e P910 Series Human Interface Device
+ 009f InkJet Color Printer
+ 00a9 IBM Infoprint 1410 MFP
+ 00ab InkJet Color Printer
+ 00b2 3300 Series
+ 00b8 7300 Series
+ 00b9 8300 Series
+ 00ba InkJet Color Printer
+ 00bb 2300 Series
+ 00bd Printing Support
+ 00be Printing Support
+ 00bf Printing Support
+ 00c0 6300 Series
+ 00c1 4300 Series
+ 00c7 Printing Support
+ 00c8 Printing Support
+ 00c9 Printing Support
+ 00cb Printing Support
+ 00d0 9300 Series
+ 00d3 X340 Scanner
+ 00d4 X342n Scanner
+ 00d5 Printing Support
+ 00d6 X340 Scanner
+ 00e8 X642e
+ 00e9 2400 Series
+ 00f6 3400 Series
+ 00f7 InkJet Color Printer
+ 00ff InkJet Color Printer
+ 010b 2500 Series
+ 010d 3500-4500 Series
+ 010f 6500 Series
+ 4303 Xerox WorkCentre Pro 412
+043e LG Electronics USA, Inc.
+ 42bd Flatron 795FT Plus Monitor
+ 4a4d Flatron 915FT Plus Monitor
+ 7001 MF-PD100 Soul Digital MP3 Player
+ 7013 MP3 Player
+ 8484 LPC-U30 Webcam II
+ 8585 LPC-UC35 Webcam
+ 8888 Electronics VCS Camera II(LPC-U20)
+ 9800 Remote Control Receiver_iMON
+ 9803 eHome Infrared Receiver
+ 9804 DMB Receiver Control
+ 9c01 LGE Sync
+043f RadiSys Corp.
+0440 Eizo Nanao Corp.
+0441 Winbond Systems Lab.
+ 1456 Hub
+0442 Ericsson, Inc.
+ abba Bluetooth Device
+0443 Gateway, Inc.
+ 000e Multimedia Keyboard
+ 002e Millennium Keyboard
+0445 Lucent Technologies, Inc.
+0446 NMB Technologies Corp.
+ 6781 Keyboard with PS/2 Mouse Port
+ 6782 Keyboard
+0447 Momentum Microsystems
+044a Shamrock Tech. Co., Ltd
+044b WSI
+044c CCL/ITRI
+044d Siemens Nixdorf AG
+044e Alps Electric Co., Ltd
+ 1104 Japanese Keyboard
+ 2002 MD-5500 Printer
+ 2014 Bluetooth Device
+ 3001 UGTZ4 Bluetooth
+ 3002 Bluetooth Device
+ 3003 Bluetooth Device
+ 3004 Bluetooth Adapter
+ 3005 Integrated Bluetooth Device
+ 3006 Bluetooth Adapter
+ 3007 GlidePoint PS/2 TouchPad
+ 300c Bluetooth Controller (ALPS/UGPZ6)
+ 300d Bluetooth Controller (ALPS/UGPZ6)
+ ffff Compaq Bluetooth Multiport Module
+044f ThrustMaster, Inc.
+ 0400 HOTAS Cougar
+ a003 Rage 3D Game Pad
+ a01b PK-GP301 Driving Wheel
+ a0a0 Top Gun Joystick
+ a0a1 Top Gun Joystick (rev2)
+ a0a3 Fusion Digital GamePad
+ a201 PK-GP201 PlayStick
+ b203 360 Modena Pro Wheel
+ b300 Firestorm Dual Power
+ b304 Firestorm Dual Power
+ b307 vibrating Upad
+ b603 force feedback Wheel
+ b605 force feedback Racing Wheel
+ b700 Tacticalboard
+0450 DFI, Inc.
+0451 Texas Instruments, Inc.
+ 1234 Bluetooth Device
+ 1428 Hub
+ 1446 TUSB2040/2070 Hub
+ 2036 TUSB2036 Hub
+ 2046 TUSB2046 Hub
+ 2077 TUSB2077 Hub
+ 3410 TUSB3410 Microcontroller
+ 3f02 SMC WSKP100 Wi-Fi Phone
+ 5409 Frontier Labs NEX IA+ Digital Audio Player
+ 6000 AU5 ADSL Modem (pre-reenum)
+ 6001 AU5 ADSL Modem
+ 6060 RNDIS/BeWAN ADSL2+
+ 6070 RNDIS/BeWAN ADSL2+
+ 625f Trekstor USB-Stick 12 CS-D 12 GB
+ dbc0 Device Bay Controller
+ e001 GraphLink
+ e004 TI-89 Titanium Calculator
+ e008 TI-84 Plus Silver Calculator
+ f430 MSP-FET430UIF JTAG Tool
+ ffff Bluetooth Device
+0452 Mitsubishi Electronics America, Inc.
+ 0021 HID Monitor Controls
+ 0050 Diamond Pro 900u CRT Monitor
+ 0051 Integrated Hub
+0453 CMD Technology
+ 6781 NMB Keyboard
+ 6783 Chicony Composite Keyboard
+0454 Vobis Microcomputer AG
+0455 Telematics International, Inc.
+0456 Analog Devices, Inc.
+0457 Silicon Integrated Systems Corp.
+ 0150 Super Talent 1GB Flash Drive
+ 0151 Super Flash 1GB / GXT 64MB Flash Drive
+ 0162 SiS162 usb Wireless LAN Adapter
+ 0163 802.11 Wireless LAN Adapter
+ 5401 Wireless Adapter RO80211GS-USB
+0458 KYE Systems Corp. (Mouse Systems)
+ 0001 Mouse
+ 0002 Genius NetMouse Pro
+ 0003 Genius NetScroll+
+ 0006 Easy Mouse+ USB(USB\Vid_0458&Pid;_0006) Mouse
+ 000b NetMouse Wheel(P+U)
+ 000c TACOMA Fingerprint V1.06.01
+ 000e VideoCAM Web
+ 0013 TACOMA Fingerprint Mouse V1.06.01
+ 001a Genius WebScroll+
+ 0036 Pocket Mouse LE
+ 004c Slimstar Pro Keyboard
+ 0056 Ergo 300 Mouse
+ 0057 Enhanced Gaming Device
+ 0059 Enhanced Laser Device
+ 005a Enhanced Device
+ 005b Enhanced Device
+ 005c Enhanced Laser Gaming Device
+ 005d Enhanced Device
+ 0061 Bluetooth Dongle
+ 0083 Bluetooth Dongle
+ 0100 EasyPen Tablet
+ 0101 CueCat
+ 1001 Joystick
+ 1002 Game Pad
+ 1003 Genius VideoCam
+ 1004 Flight2000 F-23 Joystick
+ 100a Aashima Technology Trust Sight Fighter Vibration Feedback Joystick
+ 2001 ColorPage-Vivid Pro Scanner
+ 2004 ColorPage-HR6 V1 Scanner
+ 2005 ColorPage-HR6/Vivid3
+ 2007 ColorPage-HR6 V2 Scanner
+ 2008 ColorPage-HR6 V2 Scanner
+ 2009 ColorPage-HR6A Scanner
+ 2011 ColorPage-Vivid3x Scanner
+ 2012 Plustek Scanner
+ 2013 ColorPage-HR7 Scanner
+ 2014 ColorPage-Vivid4
+ 2015 ColorPage-HR7LE Scanner
+ 2016 ColorPage-HR6X Scanner
+ 2017 ColorPage-Vivid3xe
+ 2018 ColorPage-HR7X
+ 2019 ColorPage-HR6X Slim
+ 201a ColorPage-Vivid4xe
+ 201b ColorPage-Vivid4x
+ 201c ColorPage-HR8
+ 201d ColorPage-Vivid 1200 X
+ 201e ColorPage-Slim 1200
+ 201f ColorPage-Vivid 1200 XE
+ 2020 ColorPage-Slim 1200 USB2
+ 2021 ColorPage-SF600
+ 301d Genius MaxFire MiniPad
+ 6001 GF3000F Ethernet Adapter
+ 7004 VideoCAM Express
+ 7007 VideoCAM Web
+ 7009 G-Shot G312 Still Camera Device
+ 700c VideoCAM Web V3
+ 700d G-Shot G511 Composite Device
+ 700f VideoCAM Web V4
+ 7012 WebCAM USB2.0
+ 7014 VideoCAM Live V3
+ 701c G-Shot G512 Still Camera
+ 7020 Sim 321C
+0459 Adobe Systems, Inc.
+045a SONICblue, Inc.
+ 07da Supra Express 56K modem
+ 0b4a SupraMax 2890 56K Modem [Lucent Atlas]
+ 0b68 SupraMax 56K Modem
+ 5001 Rio 600 MP3 Player
+ 5002 Rio 800 MP3 Player
+ 5003 Nike Psa/Play MP3 Player
+ 5005 Rio S10 MP3 Player
+ 5006 Rio S50 MP3 Player
+ 5007 Rio S35 MP3 Player
+ 5008 Rio 900 MP3 Player
+ 5009 Rio S30 MP3 Player
+ 500d Fuse MP3 Player
+ 500e Chiba MP3 Player
+ 500f Cali MP3 Player
+ 5010 Rio S11 MP3 Player
+ 501c Virgin MPF-1000
+ 501d Rio Fuse
+ 501e Rio Chiba
+ 501f Rio Cali
+ 503f Cali256 MP3 Player
+ 5202 Rio Riot MP3 Player
+ 5210 Rio Karma Music Player
+ 5220 Rio Nitrus MP3 Player
+ 5221 Rio Eigen
+045b Hitachi, Ltd
+045d Nortel Networks, Ltd
+045e Microsoft Corp.
+ 0007 SideWinder Game Pad
+ 0008 SideWinder Precision Pro
+ 0009 IntelliMouse
+ 000b Natural Keyboard Elite
+ 000e SideWinder® Freestyle Pro
+ 0014 Digital Sound System 80
+ 001a SideWinder Precision Racing Wheel
+ 001b SideWinder Force Feedback 2 Joystick
+ 001c Internet Keyboard Pro
+ 001d Natural Keyboard Pro
+ 001e IntelliMouse Explorer
+ 0023 Trackball Optical
+ 0024 Trackball Explorer
+ 0025 IntelliEye Mouse
+ 0026 SideWinder GamePad Pro
+ 0027 SideWinder PnP GamePad
+ 0028 SideWinder Dual Strike
+ 0029 IntelliMouse Optical
+ 002b Internet Keyboard Pro
+ 002d Internet Keyboard
+ 002f Integrated Hub
+ 0033 Sidewinder Strategic Commander
+ 0034 SideWinder Force Feedback Wheel
+ 0038 SideWinder Precision 2
+ 0039 IntelliMouse Optical
+ 003b SideWinder Game Voice
+ 003c SideWinder Joystick
+ 0040 Wheel Mouse Optical
+ 0047 IntelliMouse Explorer 3.0
+ 0048 Office Keyboard 1.0A
+ 0053 Optical Mouse
+ 0059 Wireless IntelliMouse Explorer
+ 005c Office Keyboard (106/109)
+ 005f Wireless MultiMedia Keyboard
+ 0061 Wireless MultiMedia Keyboard (106/109)
+ 0063 Wireless Natural MultiMedia Keyboard
+ 0065 Wireless Natural MultiMedia Keyboard (106/109)
+ 006a Wireless Optical Mouse (IntelliPoint)
+ 006d eHome Remote Control Keyboard keys
+ 006e MN510 802.11b Adapter
+ 006f Smart Display Reference Device
+ 0070 Wireless MultiMedia Keyboard
+ 0071 Wireless MultiMedia Keyboard (106/109)
+ 0072 Wireless Natural MultiMedia Keyboard
+ 0073 Wireless Natural MultiMedia Keyboard (106/109)
+ 007a 10/100 USB NIC
+ 007d Notebook Optical Mouse
+ 007e Wireless Transceiver for Bluetooth
+ 0080 Digital Media Pro Keyboard
+ 0083 Basic Optical Mouse
+ 0084 Basic Optical Mouse
+ 008a Wireless Keyboard and Mouse
+ 008b Dual Receiver Wireless Mouse (IntelliPoint)
+ 008c Wireless Intellimouse Explorer 2.0
+ 0095 IntelliMouse Explorer 4.0 (IntelliPoint)
+ 009c Wireless Transceiver for Bluetooth 2.0
+ 00a0 eHome Infrared Receiver
+ 00b0 Digital Media Pro Keyboard
+ 00b9 Wireless Optical Mouse 3.0
+ 00bb Fingerprint Reader
+ 00bc Fingerprint Reader
+ 00bd Fingerprint Reader
+ 00c2 Wireless Adapter MN-710
+ 00c9 MTP Device
+ 00ce Generic PPC Flash device
+ 00d1 Optical Mouse with Tilt Wheel
+ 00da eHome Infrared Receiver
+ 00db Natural Ergonomic Keyboard 4000 V1.0
+ 00e1 Wireless Laser Mouse 6000 Reciever
+ 00f4 LifeCam VX-6000.
+ 00f5 LifeCam VX-3000.
+ 00f7 LifeCam VX-1000.
+ 00f8 LifeCam NX-6000.
+ 0202 Xbox Controller
+ 0280 XBox Device
+ 0284 Xbox DVD Playback Kit
+ 0285 Xbox Controller S
+ 0288 Xbox Controller S Hub
+ 0289 Xbox Controller S
+ 028b Xbox360 DVD Emulator
+ 028d Xbox360 Memory Unit 64MB
+ 028e Xbox360 Controller
+ 028f Xbox360 Wireless Controller
+ 0290 Xbox360 Performance Pipe (PIX)
+ 0292 Xbox360 Wireless Networking Adapter
+ 029c Xbox360 HD-DVD Drive
+ 029d Xbox360 HD-DVD Drive
+ 029e Xbox360 HD-DVD Memory Unit
+ 0400 Windows Powered Pocket PC 2002
+ 0401 Windows Powered Pocket PC 2002
+ 0402 Windows Powered Pocket PC 2002
+ 0403 Windows Powered Pocket PC 2002
+ 0404 Windows Powered Pocket PC 2002
+ 0405 Windows Powered Pocket PC 2002
+ 0406 Windows Powered Pocket PC 2002
+ 0407 Windows Powered Pocket PC 2002
+ 0408 Windows Powered Pocket PC 2002
+ 0409 Windows Powered Pocket PC 2002
+ 040a Windows Powered Pocket PC 2002
+ 040b Windows Powered Pocket PC 2002
+ 040c Windows Powered Pocket PC 2002
+ 040d Windows Powered Pocket PC 2002
+ 040e Windows Powered Pocket PC 2002
+ 040f Windows Powered Pocket PC 2002
+ 0410 Windows Powered Pocket PC 2002
+ 0411 Windows Powered Pocket PC 2002
+ 0412 Windows Powered Pocket PC 2002
+ 0413 Windows Powered Pocket PC 2002
+ 0414 Windows Powered Pocket PC 2002
+ 0415 Windows Powered Pocket PC 2002
+ 0416 Windows Powered Pocket PC 2002
+ 0417 Windows Powered Pocket PC 2002
+ 0432 Windows Powered Pocket PC 2003
+ 0433 Windows Powered Pocket PC 2003
+ 0434 Windows Powered Pocket PC 2003
+ 0435 Windows Powered Pocket PC 2003
+ 0436 Windows Powered Pocket PC 2003
+ 0437 Windows Powered Pocket PC 2003
+ 0438 Windows Powered Pocket PC 2003
+ 0439 Windows Powered Pocket PC 2003
+ 043a Windows Powered Pocket PC 2003
+ 043b Windows Powered Pocket PC 2003
+ 043c Windows Powered Pocket PC 2003
+ 043d Becker Traffic Assist Highspeed 7934
+ 043e Windows Powered Pocket PC 2003
+ 043f Windows Powered Pocket PC 2003
+ 0440 Windows Powered Pocket PC 2003
+ 0441 Windows Powered Pocket PC 2003
+ 0442 Windows Powered Pocket PC 2003
+ 0443 Windows Powered Pocket PC 2003
+ 0444 Windows Powered Pocket PC 2003
+ 0445 Windows Powered Pocket PC 2003
+ 0446 Windows Powered Pocket PC 2003
+ 0447 Windows Powered Pocket PC 2003
+ 0448 Windows Powered Pocket PC 2003
+ 0449 Windows Powered Pocket PC 2003
+ 044a Windows Powered Pocket PC 2003
+ 044b Windows Powered Pocket PC 2003
+ 044c Windows Powered Pocket PC 2003
+ 044d Windows Powered Pocket PC 2003
+ 044e Windows Powered Pocket PC 2003
+ 044f Windows Powered Pocket PC 2003
+ 0450 Windows Powered Pocket PC 2003
+ 0451 Windows Powered Pocket PC 2003
+ 0452 Windows Powered Pocket PC 2003
+ 0453 Windows Powered Pocket PC 2003
+ 0454 Windows Powered Pocket PC 2003
+ 0455 Windows Powered Pocket PC 2003
+ 0456 Windows Powered Pocket PC 2003
+ 0457 Windows Powered Pocket PC 2003
+ 0458 Windows Powered Pocket PC 2003
+ 0459 Windows Powered Pocket PC 2003
+ 045a Windows Powered Pocket PC 2003
+ 045b Windows Powered Pocket PC 2003
+ 045c Windows Powered Pocket PC 2003
+ 045d Windows Powered Pocket PC 2003
+ 045e Windows Powered Pocket PC 2003
+ 045f Windows Powered Pocket PC 2003
+ 0460 Windows Powered Pocket PC 2003
+ 0461 Windows Powered Pocket PC 2003
+ 0462 Windows Powered Pocket PC 2003
+ 0463 Windows Powered Pocket PC 2003
+ 0464 Windows Powered Pocket PC 2003
+ 0465 Windows Powered Pocket PC 2003
+ 0466 Windows Powered Pocket PC 2003
+ 0467 Windows Powered Pocket PC 2003
+ 0468 Windows Powered Pocket PC 2003
+ 0469 Windows Powered Pocket PC 2003
+ 046a Windows Powered Pocket PC 2003
+ 046b Windows Powered Pocket PC 2003
+ 046c Windows Powered Pocket PC 2003
+ 046d Windows Powered Pocket PC 2003
+ 046e Windows Powered Pocket PC 2003
+ 046f Windows Powered Pocket PC 2003
+ 0470 Windows Powered Pocket PC 2003
+ 0471 Windows Powered Pocket PC 2003
+ 0472 Windows Powered Pocket PC 2003
+ 0473 Windows Powered Pocket PC 2003
+ 0474 Windows Powered Pocket PC 2003
+ 0475 Windows Powered Pocket PC 2003
+ 0476 Windows Powered Pocket PC 2003
+ 0477 Windows Powered Pocket PC 2003
+ 0478 Windows Powered Pocket PC 2003
+ 0479 Windows Powered Pocket PC 2003
+ 047a Windows Powered Pocket PC 2003
+ 047b Windows Powered Pocket PC 2003
+ 04c8 Windows Powered Smartphone 2002
+ 04c9 Windows Powered Smartphone 2002
+ 04ca Windows Powered Smartphone 2002
+ 04cb Windows Powered Smartphone 2002
+ 04cc Windows Powered Smartphone 2002
+ 04cd Windows Powered Smartphone 2002
+ 04ce Windows Powered Smartphone 2002
+ 04d7 Windows Powered Smartphone 2003
+ 04d8 Windows Powered Smartphone 2003
+ 04d9 Windows Powered Smartphone 2003
+ 04da Windows Powered Smartphone 2003
+ 04db Windows Powered Smartphone 2003
+ 04dc Windows Powered Smartphone 2003
+ 04dd Windows Powered Smartphone 2003
+ 04de Windows Powered Smartphone 2003
+ 04df Windows Powered Smartphone 2003
+ 04e0 Windows Powered Smartphone 2003
+ 04e1 Windows Powered Smartphone 2003
+ 04e2 Windows Powered Smartphone 2003
+ 04e3 Windows Powered Smartphone 2003
+ 04e4 Windows Powered Smartphone 2003
+ 04e5 Windows Powered Smartphone 2003
+ 04e6 Windows Powered Smartphone 2003
+ 04e7 Windows Powered Smartphone 2003
+ 04e8 Windows Powered Smartphone 2003
+ 04e9 Windows Powered Smartphone 2003
+ 04ea Windows Powered Smartphone 2003
+ 0708 Transceiver v 3.0 for Bluetooth
+ 070a Charon Bluetooth Dongle (DFU)
+ 930a ISOUSB.SYS Intel 82930 Isochronous IO Test Board
+ fff8 Keyboard
+0460 Ace Cad Enterprise Co., Ltd
+0461 Primax Electronics, Ltd
+ 0300 G2-300 Scanner
+ 0301 G2E-300 Scanner
+ 0302 G2-300 #2 Scanner
+ 0303 G2E-300 #2 Scanner
+ 0340 Colorado 9600 Scanner
+ 0341 Colorado 600u Scanner
+ 0345 Visioneer 6200 Scanner
+ 0346 Memorex Maxx 6136u Scanner
+ 0347 Primascan Colorado 2600u/Visioneer 4400 Scanner
+ 0360 Colorado 19200 Scanner
+ 0361 Colorado 1200u Scanner
+ 0363 VistaScan Astra 3600(ENG)
+ 0364 LG Electronics Scanworks 600U Scanner
+ 0365 VistaScan Astra 3600(ENG)
+ 0366 6400
+ 0367 VistaScan Astra 3600(ENG)
+ 0371 Visioneer Onetouch 8920 Scanner
+ 0374 UMAX Astra 2500
+ 0375 VistaScan Astra 3600(ENG)
+ 0377 Medion MD 5345 Scanner
+ 0378 VistaScan Astra 3600(ENG)
+ 037b Medion MD 6190 Scanner
+ 037c VistaScan Astra 3600(ENG)
+ 0380 G2-600 Scanner
+ 0381 ReadyScan 636i Scanner
+ 0382 G2-600 #2 Scanner
+ 0383 G2E-600 Scanner
+ 038a UMAX Astra 3000/3600
+ 038b Xerox 2400 Onetouch
+ 038c UMAX Astra 4100
+ 0392 Medion/Lifetec/Tevion/Cytron MD 6190
+ 03a8 9420M
+ 0813 IBM UltraPort Camera
+ 0815 Micro Innovations WebCam
+ 0819 Fujifilm IX-30 Camera [webcam mode]
+ 081a Fujifilm IX-30 Camera [storage mode]
+ 081c Elitegroup ECS-C11 Camera
+ 081d Elitegroup ECS-C11 Storage
+ 0a00 Web Cam 320
+ 4d01 Comfort Keyboard
+ 4d02 Mouse-in-a-Box
+ 4d03 Kensington Mouse-in-a-box
+ 4d04 Mouse
+ 4d06 Balless Mouse (HID)
+ 4d2a PoPo Elixir Mouse (HID)
+ 4d2b Wireless Laser Mini Mouse (HID)
+ 4d2c PoPo Mini Pointer Mouse (HID)
+ 4d2e Optical Mobile Mouse (HID)
+0463 MGE UPS Systems
+ 0001 UPS
+ ffff UPS
+0464 AMP/Tycoelectronics Corp.
+0467 AT&T Paradyne
+0468 Wieson Technologies Co., Ltd
+046a Cherry GmbH
+ 0001 My3000 Keyboard
+ 0003 My3000 Hub
+ 0004 CyBoard Keyboard
+ 0005 XX33 SmartCard Reader Keyboard
+ 0010 SmartBoard XX44
+ 0023 Cymotion Master Linux Keyboard
+ 002d SmartTerminal XX44
+ 003e SmartTerminal ST-2xxx
+046b American Megatrends, Inc.
+ 0001 Keyboard
+ 0101 PS/2 Keyboard, Mouse & Joystick Ports
+ 0301 USB 1.0 Hub
+ 0500 Serial & Parallel Ports
+046c Toshiba Corp., Digital Media Equipment
+046d Logitech, Inc.
+ 0082 Acer Aspire 5672 Webcam
+ 0200 WingMan Extreme Joystick
+ 0203 M2452 Keyboard
+ 0301 M4848 Mouse
+ 0401 HP PageScan
+ 0402 NEC PageScan
+ 040f Logitech/Storm PageScan
+ 0430 Mic (Cordless)
+ 0801 QuickCam Home
+ 0810 QuickCam Pro
+ 0820 QuickCam VC
+ 0830 QuickClip
+ 0840 QuickCam Express
+ 0850 QuickCam Web
+ 0870 QuickCam Express
+ 0890 QuickCam Traveler
+ 0892 OrbiCam
+ 0894 CrystalCam
+ 0895 QuickCam for Dell Notebooks
+ 0896 OrbiCam
+ 0897 QuickCam for Dell Notebooks
+ 0899 QuickCam for Dell Notebooks
+ 08a0 QuickCam IM
+ 08a1 QuickCam IM with sound
+ 08a2 Labtec WebCam Pro
+ 08a3 QuickCam QuickCam Chat
+ 08a6 QuickCam IM
+ 08a7 QuickCam Image
+ 08a9 Notebook Deluxe
+ 08aa Labtec Notebooks
+ 08ac QuickCam Cool
+ 08ad QuickCam Communicate STX
+ 08ae Quickcam for Notebooks
+ 08af QuickCam Easy/Cool
+ 08b0 QuickCam 3000 Pro [pwc]
+ 08b1 QuickCam Notebook Pro
+ 08b2 QuickCam Pro 4000
+ 08b3 QuickCam Zoom
+ 08b4 QuickCam Zoom
+ 08b5 QuickCam Sphere
+ 08b9 QuickCam IM
+ 08bd Microphone (Pro 4000)
+ 08c0 QuickCam Pro 3000
+ 08c1 QuickCam Fusion
+ 08c2 QuickCam PTZ
+ 08c3 Camera (Notebooks Pro)
+ 08c5 QuickCam Pro 5000
+ 08c6 QuickCam for DELL Notebooks
+ 08c9 QuickCam Ultra Vision
+ 08ca Mic (Fusion)
+ 08cb Mic (Notebooks Pro)
+ 08cc Mic (PTZ)
+ 08ce QuickCam Pro 5000
+ 08cf QuickCam UpdateMe
+ 08d0 QuickCam Express
+ 08d7 QuickCam Communicate STX
+ 08d8 QuickCam for Notebook Deluxe
+ 08d9 QuickCam IM/Connect
+ 08da QuickCam Messanger
+ 08dd QuickCam for Notebooks
+ 08e0 QuickCam Express
+ 08e1 Labtec WebCam
+ 08f0 QuickCam Messenger
+ 08f1 QuickCam Express
+ 08f2 Microphone (Messenger)
+ 08f3 QuickCam Express
+ 08f4 Labtec WebCam
+ 08f5 QuickCam Messenger Communicate
+ 08f6 Quickcam Messenger Plus
+ 0900 ClickSmart 310
+ 0901 ClickSmart 510
+ 0903 ClickSmart 820
+ 0905 ClickSmart 820
+ 0910 QuickCam Cordless
+ 0920 QuickCam Express
+ 0921 Labtec WebCam
+ 0922 QuickCam Live
+ 0928 Quickcam Express
+ 0929 Labtec WebCam Pro
+ 092a QuickCam for Notebooks
+ 092b Labtec WebCam Plus
+ 092c QuickCam Chat
+ 092d QuickCam Express / Go
+ 092e QuickCam Chat
+ 092f QuickCam Express Plus
+ 0950 Pocket Camera
+ 0960 ClickSmart 420
+ 0970 Pocket750
+ 0990 QuickCam Pro 9000
+ 0991 QuickCam Pro for Notebooks
+ 0992 QuickCam Communicate Deluxe
+ 0994 QuickCam Orbit/Sphere AF
+ 09b0 OrbiCam
+ 09c0 QuickCam for Dell Notebooks Mic
+ 09c1 QuickCam Deluxe for Notebooks
+ 0a01 USB Headset
+ 0a02 Premium Stereo USB Headset 350
+ 0a03 Logitech USB Microphone
+ 0a04 V20 portable speakers (USB powered)
+ 0b02 BT Mini-Receiver (HID proxy mode)
+ 8801 Video Camera
+ b305 BT Mini-Receiver
+ bfe4 Premium Optical Wheel Mouse
+ c000 N43 [Pilot Mouse]
+ c001 N48/M-BB48 [FirstMouse Plus]
+ c002 M-BA47 [MouseMan Plus]
+ c003 MouseMan
+ c004 WingMan Gaming Mouse
+ c005 WingMan Gaming Wheel Mouse
+ c00b MouseMan Wheel
+ c00c Optical Wheel Mouse
+ c00d MouseMan Wheel+
+ c00e M-BJ58/M-BJ69 Optical Wheel Mouse
+ c00f MouseMan Traveler/Mobile
+ c011 Optical MouseMan
+ c012 Mouseman Dual Optical
+ c014 Corded Workstation Mouse
+ c015 Corded Workstation Mouse
+ c016 M-UV69a/HP M-UV96 Optical Wheel Mouse
+ c018 Optical Wheel Mouse
+ c019 Optical Tilt Wheel Mouse
+ c01a M-BQ85 Optical Wheel Mouse
+ c01b MX310 Optical Mouse
+ c01c Optical Mouse
+ c01d MX510 Optical Mouse
+ c01e MX518 Optical Mouse
+ c024 MX300 Optical Mouse
+ c025 MX500 Optical Mouse
+ c030 iFeel Mouse
+ c031 iFeel Mouse+
+ c032 MouseMan iFeel
+ c033 iFeel MouseMan+
+ c034 MouseMan Optical
+ c035 Mouse
+ c036 Mouse
+ c037 Mouse
+ c038 Mouse
+ c03d M-BT69a Pilot Optical Mouse
+ c03e Premium Optical Wheel Mouse
+ c03f UltraX Optical Mouse
+ c040 Corded Tilt-Wheel Mouse
+ c043 MX320 Laser Mouse
+ c044 LX3 Optical Mouse
+ c045 Optical Mouse
+ c046 RX1000 Laser Mouse
+ c047 Laser Mouse
+ c049 G5 Laser Mouse
+ c050 RX 250 Optical Mouse
+ c051 G3 (MX518) Optical Mouse
+ c053 Laser Mouse
+ c101 UltraX Media Remote
+ c201 WingMan Extreme Joystick with Throttle
+ c202 WingMan Formula
+ c207 WingMan Extreme Digital 3D
+ c208 WingMan Gamepad Extreme
+ c209 WingMan Gamepad
+ c20a WingMan RumblePad
+ c20b WingMan Action Pad
+ c20c WingMan Precision
+ c20d WingMan Attack 2
+ c20e WingMan Formula GP
+ c211 iTouch Cordless Reciever
+ c212 WingMan Extreme Digital 3D
+ c213 J-UH16 (Freedom 2.4 Cordless Joystick)
+ c214 ATK3 (Attack III Joystick)
+ c215 Extreme 3D Pro
+ c216 Dual Action Gamepad
+ c218 Logitech RumblePad 2 USB
+ c219 Cordless RumblePad 2
+ c21a Precision Gamepad
+ c221 G15 Keyboard / Keyboard
+ c222 G15 Keyboard / LCD
+ c223 G15 Keyboard / USB Hub
+ c281 WingMan Force
+ c283 WingMan Force 3D
+ c285 WingMan Strike Force 3D
+ c286 Force 3D Pro
+ c291 WingMan Formula Force
+ c293 WingMan Formula Force GP
+ c294 Driving Force
+ c295 Momo Force Steering Wheel
+ c298 Driving Force Pro
+ c2a0 Wingman Force Feedback Mouse
+ c2a1 WingMan Force Feedback Mouse
+ c301 iTouch Keyboard
+ c302 iTouch Pro Keyboard
+ c303 iTouch Keyboard
+ c305 Internet Keyboard
+ c307 Internet Keyboard
+ c308 Internet Navigator Keyboard
+ c309 Internet Keyboard
+ c30a iTouch Composite
+ c30c Internet Keys (X)
+ c30d Internet Keys
+ c30e UltraX Keys (X)
+ c30f Logicool HID-Compliant Keyboard (106 key)
+ c315 Classic New Touch Keyboard
+ c316 HID-Compliant Keyboard
+ c401 TrackMan Marble Wheel
+ c402 Marble Mouse (2-button)
+ c403 Turbo TrackMan Marble FX
+ c404 TrackMan Wheel
+ c408 Marble Mouse (4-button)
+ c501 Cordless Mouse Receiver
+ c502 Cordless Mouse & iTouch Keys
+ c503 Cordless Mouse+Keyboard Receiver
+ c504 Cordless Mouse+Keyboard Receiver
+ c505 Cordless Mouse+Keyboard Receiver
+ c506 MX-700 Cordless Mouse Receiver
+ c508 Cordless Trackball
+ c509 Cordless Keyboard
+ c50a Cordless Mouse
+ c50b Cordless Desktop Optical
+ c50d Cordless Mouse
+ c50e MX-1000 Cordless Mouse Receiver
+ c510 Cordless Mouse
+ c512 LX-700 Cordless Desktop Receiver
+ c513 MX3000 Cordless Desktop Receiver
+ c514 Cordless Mouse
+ c517 LX710 Cordless Desktop Laser
+ c518 MX610 Laser Cordless Mouse
+ c51a MX Revolution/G7 Cordless Mouse
+ c521 MX620 Laser Cordless Mouse
+ c625 3Dconnexion Space Pilot 3D Mouse
+ c626 3DConnexion Space Navigator 3D Mouse
+ c627 3DConnexion Space Explorer 3D Mouse
+ c702 Cordless Presenter
+ c703 Elite Keyboard Y-RP20 + Mouse MX900 (Bluetooth)
+ c707 Bluetooth wireless hub
+ c708 Bluetooth wireless hub
+ c709 BT Mini-Receiver (HCI mode)
+ c70a MX5000 Cordless Desktop
+ c70b BT Mini-Receiver (HID proxy mode)
+ c70c BT Mini-Receiver (HID proxy mode)
+ c70d Bluetooth wireless hub
+ c70e MX1000 Bluetooth Laser Mouse
+ c70f Bluetooth wireless hub
+ c712 Bluetooth wireless hub
+ c715 Bluetooth wireless hub
+ c71a Bluetooth wireless hub
+ c71d Bluetooth wireless hub
+ c720 Bluetooth wireless hub
+ ca03 MOMO Racing
+ ca04 Formula Vibration Feedback Wheel
+ d001 QuickCam Pro
+046e Behavior Tech. Computer Corp.
+ 0100 Keyboard
+ 3001 Mass Storage Device
+ 3002 Mass Storage Device
+ 3003 Mass Storage Device
+ 3005 Mass Storage Device
+ 3008 Mass Storage Device
+ 5250 KeyMaestro Multimedia Keyboard
+ 5273 KeyMaestro Multimedia Keyboard
+ 5308 KeyMaestro Keyboard
+ 5408 KeyMaestro Multimedia Keyboard/Hub
+ 5720 Smart Card Reader
+ 6782 BTC 7932 mouse+keyboard
+046f Crystal Semiconductor
+0471 Philips
+ 0101 DSS350 Digital Speaker System
+ 0104 DSS330 Digital Speaker System [uda1321]
+ 0105 UDA1321
+ 0160 MP3 Player
+ 0161 MP3 Player
+ 0201 Hub
+ 0222 Creative Nomad Jukebox
+ 0302 PCA645VC WebCam [pwc]
+ 0303 PCA646VC WebCam [pwc]
+ 0304 Askey VC010 WebCam [pwc]
+ 0307 PCVC675K WebCam [pwc]
+ 0308 PCVC680K WebCam [pwc]
+ 030b PC VGA Camera (Vesta Fun)
+ 030c PCVC690K WebCam [pwc]
+ 0310 PCVC730K WebCam [pwc]
+ 0311 PCVC740K ToUcam Pro [pwc]
+ 0312 PCVC750K WebCam [pwc]
+ 0314 DMVC 1000K
+ 0316 DMVC 2000K Video Capture
+ 0321 FunCam
+ 0325 SPC 200NC PC Camera
+ 0326 SPC 300NC PC Camera
+ 0327 WebCam SPC 6000 NC (WebCam w/ mic)
+ 0329 ORITE CCD Webcam(PC370R)
+ 0401 Semiconductors CICT Keyboard
+ 0402 PS/2 Mouse on Semiconductors CICT Keyboard
+ 0406 15 inch Detachable Monitor
+ 0407 10 inch Mobile Monitor
+ 0471 Digital Speaker System
+ 0601 OVU1020 IR Dongle (Kbd+Mouse)
+ 0602 ATI Remote Wonder II Input Device
+ 0603 ATI Remote Wonder II Controller
+ 0608 eHome Infrared Receiver
+ 060a TSU9600 Remote Control
+ 060e RF Dongle
+ 0619 TSU9400 Remote Control
+ 0700 Semiconductors CICT Hub
+ 0701 150P1 TFT Display
+ 0809 AVNET Bluetooth Device
+ 0811 JR24 CDRW
+ 0815 eHome Infrared Receiver
+ 1120 Creative Rhomba MP3 player
+ 1125 Nike psa[128max Player
+ 1137 HDD065 MP3 player
+ 1201 Arima Bluetooth Device
+ 1230 Wireless Adapter 11g
+ 1232 SNU6500 Wireless Adapter
+ 1233 Wireless Adapter Bootloader Download
+ 1236 SNU5600
+ 1237 TalkTalk SNU5630NS/05 Wireless Adapter
+ 1552 ISP 1581 Hi-Speed USB MPEG2 Encoder Reference Kit
+ 1801 Diva MP3 player
+ 200a Wireless Network Adapter
+ 200f 802.11n Wireless Adapter
+ 485d Senselock SenseIV v2.x
+0472 Chicony Electronics Co., Ltd
+ 0065 PFU-65 Keyboard
+0473 Sanyo Information Business Co., Ltd
+0474 Sanyo Electric Co., Ltd
+ 0110 Digital Voice Recorder R200
+ 0217 Xacti J2
+ 022f C5 Digital Media Camera (mass storage mode)
+ 0230 C5 Digital Media Camera (PictBridge mode)
+ 0231 C5 Digital Media Camera (PC control mode)
+ 0401 Optical Drive
+ 0701 SCP-4900 Cellphone
+ 071f Usb Com Port Enumerator
+0475 Relisys/Teco Information System
+ 0100 NEC Petiscan
+ 0103 Eclipse 1200U/Episode
+ 0210 Scorpio Ultra 3
+0476 AESP
+0477 Seagate Technology, Inc.
+0478 Connectix Corp.
+ 0001 QuickCam
+ 0002 QuickClip
+ 0003 QuickCam Pro
+0479 Advanced Peripheral Laboratories
+047a Semtech Corp.
+ 0004 ScreenCoder UR7HCTS2-USB
+047b Silitek Corp.
+ 0001 Keyboard
+ 0002 Keyboard and Mouse
+ 00f9 SK-1789u Keyboard
+ 0101 BlueTooth Keyboard and Mouse
+ 020b SK-3105 SmartCard Reader
+ 050e Internet Compact Keyboard
+ 1000 Trust Office Scan USB 19200
+ 1002 HP ScanJet 4300c Parallel Port
+047c Dell Computer Corp.
+047d Kensington
+ 1001 Mouse*in*a*Box
+ 1002 Expert Mouse Pro
+ 1003 Orbit TrackBall
+ 1004 MouseWorks
+ 1005 TurboBall
+ 1006 TurboRing
+ 1009 Orbit TrackBall for Mac
+ 1012 PocketMouse
+ 1013 Mouse*in*a*Box Optical Pro
+ 1014 Expert Mouse Pro Wireless
+ 1015 Expert Mouse
+ 1016 ADB/USB Orbit
+ 1018 Studio Mouse
+ 101d Mouse*in*a*Box Optical Pro
+ 101e Studio Mouse Wireless
+ 101f PocketMouse Pro
+ 1020 Expert Mouse Trackball
+ 1021 Expert Mouse Wireless
+ 1022 Orbit Optical
+ 1023 Pocket Mouse Pro Wireless
+ 1024 PocketMouse
+ 1025 Mouse*in*a*Box Optical Elite Wireless
+ 1026 Pocket Mouse Pro
+ 1027 StudioMouse
+ 1028 StudioMouse Wireless
+ 1029 Mouse*in*a*Box Optical Elite
+ 102a Mouse*in*a*Box Optical
+ 102b PocketMouse
+ 102c Iridio
+ 102d Pilot Optical
+ 102e Pilot Optical Pro
+ 102f Pilot Optical Pro Wireless
+ 104a PilotMouse Mini Retractable
+ 105d PocketMouse Bluetooth
+ 105e Bluetooth EDR Dongle
+ 1061 PocketMouse Grip
+ 1062 PocketMouse Max
+ 1063 PocketMouse Max Wireless
+ 1064 PocketMouse 2.0 Wireless
+ 1065 PocketMouse 2.0
+ 1066 PocketMouse Max Glow
+ 1067 ValueMouse
+ 1068 ValueOpt White
+ 1069 ValueOpt Black
+ 106a PilotMouse Laser Wireless Mini
+ 106b PilotMouse Laser - 3 Button
+ 106c PilotMouse Laser - Gaming
+ 106d PilotMouse Laser - Wired
+ 106e PilotMouse Micro Laser
+ 1070 ValueOpt Travel
+ 1071 ValueOpt RF TX
+ 1072 PocketMouse Colour
+ 1073 PilotMouse Laser - 6 Button
+ 1074 PilotMouse Laser Wireless Mini
+ 1075 SlimBlade Presenter Media Mouse
+ 1076 SlimBlade Media Mouse
+ 1077 SlimBlade Presenter Mouse
+ 1152 Bluetooth EDR Dongle
+ 2002 Optical Elite Wireless
+ 2010 Wireless Presentation Remote
+ 2021 PilotBoard Wireless
+ 2030 PilotBoard Wireless
+ 2034 SlimBlade Media Notebook Set
+ 4003 Gravis Xterminator Digital Gamepad
+ 4005 Gravis Eliminator GamePad Pro
+ 4006 Gravis Eliminator AfterShock
+ 4007 Gravis Xterminator Force
+ 4008 Gravis Destroyer TiltPad
+ 5001 Cabo I Camera
+ 5002 VideoCam CABO II
+ 5003 VideoCam
+047e Agere Systems, Inc. (Lucent)
+ 0300 ORiNOCO Card
+ 1001 USS720 Parallel Port
+ 2892 Systems Soft Modem
+ bad1 Lucent 56k Modem
+ f101 Atlas Modem
+047f Plantronics, Inc.
+ 0101 Bulk Driver
+ 0301 Bulk Driver
+ 0ca1 USB DSP v4 Audio Interface
+0480 Toshiba America Info. Systems, Inc.
+ 0001 InTouch Module
+ 0004 InTouch Module
+ 0011 InTouch Module
+ 0014 InTouch Module
+0481 Zenith Data Systems
+0482 Kyocera Corp.
+ 000e FS-1020D Printer
+ 0100 Finecam S3x
+ 0101 Finecam S4
+ 0103 Finecam S5
+ 0105 Finecam L3
+ 0106 Finecam
+ 0107 Digital Camera Device
+ 0108 Digital Camera Device
+ 0203 AH-K3001V
+ 0204 iBurst Terminal
+0483 SGS Thomson Microelectronics
+ 0137 BeWAN ADSL USB ST (blue or green)
+ 1307 Cytronix 6in1 card reader
+ 163d Cool Icam Digi-MP3
+ 2015 TouchChip® Fingerprint Reader
+ 2016 Fingerprint Reader
+ 2017 Biometric Smart Card Reader
+ 2018 BioSimKey
+ 2302 Portable Flash Device (PFD)
+ 4810 ISDN adapter
+ 481d BT Digital Access adapter
+ 5000 ST Micro Bluetooth Device
+ 5001 ST Micro Bluetooth Device
+ 7270 ST Micro Serial Bridge
+ 7554 56k SoftModem
+ ff10 Swann ST56 Modem
+0484 Specialix
+0485 Nokia Monitors
+0486 ASUS Computers, Inc.
+0487 Stewart Connector
+0488 Cirque Corp.
+0489 Foxconn / Hon Hai
+ 0502 SmartMedia Card Reader Firmware Loader
+ 0503 SmartMedia Card Reader
+048a S-MOS Systems, Inc.
+048c Alps Electric Ireland, Ltd
+048d Integrated Technology Express, Inc.
+048f Eicon Tech.
+0490 United Microelectronics Corp.
+0491 Capetronic
+ 0003 Taxan Monitor Control
+0492 Samsung SemiConductor, Inc.
+0493 MAG Technology Co., Ltd
+0495 ESS Technology, Inc.
+0496 Micron Electronics
+0497 Smile International
+0498 Capetronic (Kaohsiung) Corp.
+0499 Yamaha Corp.
+ 1000 UX256 MIDI I/F
+ 1001 MU1000
+ 1002 MU2000
+ 1003 MU500
+ 1004 UW500
+ 1005 MOTIF6
+ 1006 MOTIF7
+ 1007 MOTIF8
+ 1008 UX96 MIDI I/F
+ 1009 UX16 MIDI I/F
+ 100a EOS BX
+ 100c UC-MX
+ 100d UC-KX
+ 100e S08
+ 100f CLP-150
+ 1010 CLP-170
+ 1011 P-250
+ 1012 TYROS
+ 1013 PF-500
+ 1014 S90
+ 1015 MOTIF-R
+ 1016 MDP-5
+ 1017 CVP-204
+ 1018 CVP-206
+ 1019 CVP-208
+ 101a CVP-210
+ 101b PSR-1100
+ 101c PSR-2100
+ 101d CLP-175
+ 101e PSR-K1
+ 101f EZ-J24
+ 1020 EZ-250i
+ 1021 MOTIF ES 6
+ 1022 MOTIF ES 7
+ 1023 MOTIF ES 8
+ 1024 CVP-301
+ 1025 CVP-303
+ 1026 CVP-305
+ 1027 CVP-307
+ 1028 CVP-309
+ 1029 CVP-309GP
+ 102a PSR-1500
+ 102b PSR-3000
+ 102e ELS-01/01C
+ 1030 PSR-295/293
+ 1031 DGX-205/203
+ 1032 DGX-305
+ 1033 DGX-505
+ 2000 DGP-7
+ 2001 DGP-5
+ 3001 YST-MS55D USB Speaker
+ 4000 NetVolante RTA54i Broadband&ISDN Router
+ 4001 NetVolante RTW65b Broadband Wireless Router
+ 4002 NetVolante RTW65i Broadband&ISDN Wireless Router
+ 4004 NetVolante RTA55i Broadband VoIP Router
+ 5000 CS1D
+ 5001 DSP1D
+ 5002 DME32
+ 5003 DM2000
+ 5004 02R96
+ 5005 ACU16-C
+ 5006 NHB32-C
+ 5007 DM1000
+ 5008 01V96
+ 5009 SPX2000
+ 500a PM5D
+ 500b DME64N
+ 500c DME24N
+ 6001 CRW2200UX Lightspeed 2 External CD-RW Drive
+ 7000 DTX
+ 7010 UB99
+049a Gandalf Technologies, Ltd
+049b Curtis Computer Products
+049c Acer Advanced Labs, Inc.
+ 0002 Keyboard (???)
+049d VLSI Technology
+049f Compaq Computer Corp.
+ 0002 InkJet Color Printer
+ 0003 iPAQ PocketPC
+ 000e Internet Keyboard
+ 0012 InkJet Color Printer
+ 0018 PA-1/PA-2 MP3 Player
+ 0019 InkJet Color Printer
+ 001a S4 100 Scanner
+ 001e IJ650 Inkjet Printer
+ 001f WL215 Adapter
+ 0021 S200 Scanner
+ 0027 Bluetooth Multiport Module by Compaq
+ 002a 1400P Inkjet Printer
+ 002b A3000
+ 002c Lexmark X125
+ 0032 802.11b Adapter [ipaq h5400]
+ 0033 802.11b Adapter [orinoco]
+ 0036 Bluetooth Multiport Module
+ 0051 KU-0133 Easy Access Interner Keyboard
+ 0076 Wireless LAN MultiPort W200
+ 0080 GPRS Multiport
+ 0086 Bluetooth Device
+ 504a Personal Jukebox PJB100
+ 505a Linux-USB "CDC Subset" Device, or Itsy (experimental)
+ 8511 iPAQ Networking 10/100 Ethernet [pegasus2]
+04a0 Digital Equipment Corp.
+04a1 SystemSoft Corp.
+ fff0 Telex Composite Device
+04a2 FirePower Systems
+04a3 Trident Microsystems, Inc.
+04a4 Hitachi, Ltd
+ 0004 DVD-CAM DZ-MV100A Camcorder
+ 001e DVDCAM USB HS Interface
+04a5 Acer Peripherals Inc. (now BenQ Corp.)
+ 0001 Keyboard
+ 0002 API Ergo K/B
+ 0003 API Generic K/B Mouse
+ 12a6 AcerScan C310U
+ 1a20 Prisa 310U
+ 1a2a Prisa 620U
+ 2022 Prisa 320U/340U
+ 2040 Prisa 620UT
+ 205e ScanPrisa 640BU
+ 2060 Prisa 620U+/640U
+ 207e Prisa 640BU
+ 209e ScanPrisa 640BT
+ 20ae S2W 3000U
+ 20b0 S2W 3300U/4300U
+ 20be Prisa 640BT
+ 20c0 Prisa 1240UT
+ 20de S2W 4300U+
+ 20f8 Benq 5000
+ 20fc Benq 5000
+ 20fe SW2 5300U
+ 2137 Benq 5150/5250
+ 2202 Benq 7400UT
+ 3003 Benq WebCam
+ 3008 Benq 1500
+ 300a Benq 3410
+ 300c Benq 1016
+ 3019 Benq DC C40
+ 4000 P30 Composite Device
+ 6001 Mass Storage Device
+ 6002 Mass Storage Device
+ 6003 ATA/ATAPI Adapter
+ 6004 Mass Storage Device
+ 6005 Mass Storage Device
+ 6006 Mass Storage Device
+ 6007 Mass Storage Device
+ 6008 Mass Storage Device
+ 6009 Mass Storage Device
+ 600a Mass Storage Device
+ 600b Mass Storage Device
+ 600c Mass Storage Device
+ 600d Mass Storage Device
+ 600e Mass Storage Device
+ 600f Mass Storage Device
+ 6010 Mass Storage Device
+ 6011 Mass Storage Device
+ 6012 Mass Storage Device
+ 6013 Mass Storage Device
+ 6014 Mass Storage Device
+ 6015 Mass Storage Device
+ 6125 MP3 Player
+ 6180 MP3 Player
+ 6200 MP3 Player
+ 7500 Hi-Speed Mass Storage Device
+ 9000 AWL300 Wireless Adapter
+ 9001 AWL400 Wireless Adapter
+ 9213 Kbd Hub
+04a6 Nokia Display Products
+ 00b9 Audio
+ 0180 Hub Type P
+ 0181 HID Monitor Controls
+04a7 Visioneer
+ 0100 StrobePro
+ 0101 Strobe Pro Scanner (1.01)
+ 0102 StrobePro Scanner
+ 0211 OneTouch 7600 Scanner
+ 0221 OneTouch 5300 Scanner
+ 0223 OneTouch 8200
+ 0224 OneTouch 4800 USB/Microtek Scanport 3000
+ 0225 VistaScan Astra 3600(ENG)
+ 0226 OneTouch 5300 USB
+ 0229 OneTouch 7100
+ 022a OneTouch 6600
+ 022c OneTouch 9000/9020
+ 0231 6100 Scanner
+ 0311 6200 EPP/USB Scanner
+ 0321 OneTouch 8100 EPP/USB Scanner
+ 0331 OneTouch 8600 EPP/USB Scanner
+ 0341 6400
+ 0361 VistaScan Astra 3600(ENG)
+ 0362 OneTouch 9320
+ 0371 OneTouch 8700/8920
+ 0380 OneTouch 7700
+ 0382 Photo Port 7700
+ 0390 9650
+ 03a0 Xerox 4800 One Touch
+ 0410 OneTouch Pro 8800/8820
+ 0421 9450 USB
+ 0423 9750 Scanner
+ 0424 Strobe XP 450
+ 0425 Strobe XP 100
+ 0426 Strobe XP 200
+ 0427 Strobe XP 100
+ 0444 OneTouch 7300
+ 0445 CardReader 100
+ 0446 Xerox DocuMate 510
+ 0447 XEROX DocuMate 520
+ 0448 XEROX DocuMate 250
+ 0449 Xerox DocuMate 252
+ 044a Xerox 6400
+ 044c Xerox DocuMate 262
+ 0474 Strobe XP 300
+ 0475 Xerox DocuMate 272
+ 0478 Strobe XP 220
+ 0479 Strobe XP 470
+ 047a 9450
+ 047b 9650
+ 047d 9420
+ 0480 9520
+ 048f Strobe XP 470
+ 0491 Strobe XP 450
+ 0493 9750
+ 0494 Strobe XP 120
+ 0497 Patriot 430
+ 0498 Patriot 680
+ 0499 Patriot 780
+ 049b Strobe XP 100
+ 04a0 7400
+04a8 Multivideo Labs, Inc.
+ 0101 Hub
+ 0303 Peripheral Switch
+ 0404 Peripheral Switch
+04a9 Canon, Inc.
+ 1005 BJ Printer Hub
+ 1035 PD Printer Storage
+ 1050 BJC-8200
+ 1051 BJC-3000 Color Printer
+ 1052 BJC-6100
+ 1053 BJC-6200
+ 1054 BJC-6500
+ 1055 BJC-85
+ 1056 BJC-2110 Color Printer
+ 1057 LR1
+ 105a BJC-55
+ 105b S600 Printer
+ 105c S400
+ 105d S450 Printer
+ 105e S800
+ 1062 S500 Printer
+ 1063 S4500
+ 1064 S300 Printer
+ 1065 S100
+ 1066 S630
+ 1067 S900
+ 1068 S9000
+ 1069 S820
+ 106a S200 Printer
+ 106b S520 Printer
+ 106d S750 Printer
+ 106e S820D
+ 1070 S530D
+ 1072 I850 Printer
+ 1073 I550 Printer
+ 1074 S330 Printer
+ 1076 i70
+ 1077 i950
+ 107a S830D
+ 107b i320
+ 107c i470D
+ 107d i9100
+ 107e i450
+ 107f i860
+ 1082 i350
+ 1084 i250
+ 1085 i255
+ 1086 i560
+ 1088 i965
+ 108a i455
+ 108b i900D
+ 108c i475D
+ 108d PIXMA iP2000
+ 108f i80
+ 1090 i9900 Photo Printer
+ 1091 PIXMA iP1500
+ 1093 PIXMA iP4000
+ 1094 PIXMA iP3000x Printer
+ 1095 PIXMA iP6000D
+ 1097 PIXMA iP5000
+ 1098 PIXMA iP1000
+ 1099 PIXMA iP8500
+ 109c PIXMA iP4000R
+ 109d iP90
+ 10a0 PIXMA iP1600 Printer
+ 10a2 iP4200
+ 10a4 iP5200R
+ 10a5 iP5200
+ 10a7 iP6210D
+ 10a8 iP6220D
+ 10a9 iP6600D
+ 10b6 PIXMA iP4300 Printer
+ 1404 W6400PG
+ 1405 W8400PG
+ 150f BIJ2350 PCL
+ 1510 BIJ1350 PCL
+ 1512 BIJ1350D PCL
+ 1601 DR-2080C Scanner
+ 1607 DR-6080 Scanner
+ 1700 PIXMA MP110 Scanner
+ 1701 PIXMA MP130 Scanner
+ 1702 MP410 Composite
+ 1703 MP430 Composite
+ 1704 MP330 Composite
+ 1706 PIXMA MP750 Scanner
+ 1707 PIXMA MP780 Scanner
+ 1708 PIXMA MP760 Scanner
+ 1709 PIXMA MP150 Scanner
+ 170a PIXMA MP170 Scanner
+ 170b PIXMA MP450 Scanner
+ 170c PIXMA MP500 Scanner
+ 170d PIXMA MP800 Scanner
+ 170e MP800R
+ 1710 MP950
+ 1712 MP530
+ 1713 PIXMA MP830 Scanner
+ 1714 MP160
+ 1715 MP180 Storage
+ 1716 MP460 Composite
+ 1717 MP510
+ 1718 MP600 Storage
+ 171a MP810 Storage
+ 171b MP960
+ 1721 MP210 ser
+ 1723 MP470 ser
+ 1725 MP610 ser
+ 1726 MP970 ser
+ 1727 MX300 ser
+ 1728 MX310 ser
+ 1729 MX700 ser
+ 172b MP140 ser
+ 2200 CanoScan LiDE 25
+ 2201 CanoScan FB320U
+ 2202 CanoScan FB620U
+ 2204 CanoScan FB630U
+ 2205 CanoScan FB1210U
+ 2206 CanoScan N650U/N656U
+ 2207 CanoScan 1220U
+ 2208 CanoScan D660U
+ 220a CanoScan D2400UF
+ 220b CanoScan D646U
+ 220c CanoScan D1250U2
+ 220d CanoScan N670U/N676U/LiDE 20
+ 220e CanoScan N1240U/LiDE 30
+ 220f CanoScan 8000F
+ 2210 CanoScan 9900F
+ 2212 CanoScan 5000F
+ 2213 CanoScan LiDE 50/LiDE 35/LiDE 40
+ 2214 CanoScan LiDE 80
+ 2215 CanoScan 3000/3000F/3000ex
+ 2216 CanoScan 3200F
+ 2217 CanoScan 5200F
+ 2219 CanoScan 9950F
+ 221b CanoScan 4200F
+ 221c CanoScan LiDE 60
+ 221e CanoScan 8400F
+ 221f CanoScan LiDE 500F
+ 2220 CanoScan LIDE 25
+ 2225 CanoScan LiDE 70
+ 2228 CanoScan 4400F
+ 2602 MultiPASS C555
+ 2603 MultiPASS C755
+ 260a CAPT Printer
+ 260e LBP-2000
+ 2610 MPC600F
+ 2611 SmartBase MPC400
+ 2612 MultiPASS C855
+ 2617 CAPT Printer
+ 261a iR1600
+ 261b iR1610
+ 261c iC2300
+ 261f MPC200 Printer
+ 2621 iR2000
+ 2622 iR2010
+ 2623 FAX-B180C
+ 2629 FAXPHONE L75
+ 262b LaserShot LBP-1120 Printer
+ 262d iR C3200
+ 262f MultiPASS MP730
+ 2630 MultiPASS MP700
+ 2631 LASER CLASS 700
+ 2632 FAX-L2000
+ 2635 MPC190
+ 2637 iR C6800
+ 2638 iR C3100
+ 263c Smartbase MP360
+ 263d MP370
+ 263e MP390 FAX
+ 263f MP375
+ 2646 MF5530 Scanner Device V1.9.1
+ 2647 MF5550 Composite
+ 264e MF5630
+ 264f MF5650 (FAX)
+ 2650 iR 6800C EUR
+ 2651 iR 3100C EUR
+ 2655 FP-L170/MF350/L380/L398
+ 2659 MF8100
+ 265b CAPT Printer
+ 265c iR C3220
+ 265d MF5730
+ 265e MF5750
+ 265f MF5770
+ 2660 MF3110
+ 2663 iR3570/iR4570
+ 2664 iR2270/iR2870
+ 2665 iR C2620
+ 2666 iR C5800
+ 2667 iR85PLUS
+ 2669 iR105PLUS
+ 266a CAPT Device
+ 266b iR8070
+ 266c iR9070
+ 266d iR 5800C EUR
+ 266e CAPT Device
+ 266f iR2230
+ 2670 iR3530
+ 2671 iR5570/iR6570
+ 2672 iR C3170
+ 2673 iR 3170C EUR
+ 2674 L120
+ 2675 iR2830
+ 2676 CAPT Device
+ 2677 iR C2570
+ 2678 iR 2570C EUR
+ 2679 CAPT Device
+ 267a iR2016
+ 267b iR2020
+ 267d MF7100 Series
+ 2684 MF3200 Series
+ 2687 iR4530
+ 2688 LBP3460
+ 268c iR C6870
+ 268d iR 6870C EUR
+ 268e iR C5870
+ 268f iR 5870C EUR
+ 2691 iR7105
+ 26a3 MF4100 Series
+ 26b5 MF4200 Series
+ 3041 PowerShot S10
+ 3042 CanoScan FS4000US Film Scanner
+ 3043 PowerShot S20
+ 3044 EOS D30
+ 3045 PowerShot S100
+ 3046 IXY Digital
+ 3047 Digital IXUS
+ 3048 PowerShot G1
+ 3049 PowerShot Pro90 IS
+ 304a CP-10
+ 304b IXY Digital 300
+ 304c PowerShot S300
+ 304d Digital IXUS 300
+ 304e PowerShot A20
+ 304f PowerShot A10
+ 3050 PowerShot unknown 1
+ 3051 PowerShot S110
+ 3052 Digital IXUS V
+ 3055 PowerShot G2
+ 3056 PowerShot S40
+ 3057 PowerShot S30
+ 3058 PowerShot A40
+ 3059 PowerShot A30
+ 305b ZR45MC Digital Camcorder
+ 305c PowerShot unknown 2
+ 3060 EOS D60
+ 3061 PowerShot A100
+ 3062 PowerShot A200
+ 3063 CP-100
+ 3065 PowerShot S200
+ 3066 Digital IXUS 330
+ 3067 MV550i Digital Video Camera
+ 3069 PowerShot G3
+ 306a Digital unknown 3
+ 306b MVX2i Digital Video Camera
+ 306c PowerShot S45
+ 306d PowerShot S45 PtP Mode
+ 306e PowerShot G3 (normal mode)
+ 306f PowerShot G3 (ptp)
+ 3070 PowerShot S230
+ 3071 PowerShot S230 (ptp)
+ 3072 PowerShot SD100 / Digital IXUS II (ptp)
+ 3073 PowerShot A70 (ptp)
+ 3074 PowerShot A60 (ptp)
+ 3075 IXUS 400 Camera
+ 3076 PowerShot A300
+ 3077 PowerShot S50
+ 3078 ZR70MC Digital Camcorder
+ 307a MV650i (normal mode)
+ 307b MV630i Digital Video Camera
+ 307c MV630i (normal mode)
+ 307d CP-300
+ 307f Optura 20
+ 3080 MVX150i (normal mode) / Optura 20 (normal mode)
+ 3081 Optura 10
+ 3082 MVX100i / Optura 10
+ 3083 EOS 10D
+ 3084 EOS 300D / EOS Digital Rebel
+ 3085 PowerShot G5
+ 3087 Elura 50 (PTP mode)
+ 3088 Elura 50 (normal mode)
+ 308d MVX3i
+ 308e FV M1 (normal mode) / MVX 3i (normal mode) / Optura Xi (normal mode)
+ 3093 Optura 300
+ 3096 IXY DV M2 (normal mode) / MVX 10i (normal mode)
+ 3099 EOS 300D (ptp)
+ 309a PowerShot A80
+ 309b Digital IXUS (ptp)
+ 309c PowerShot S1 IS
+ 309d Camera
+ 309f Camera
+ 30a0 Camera
+ 30a1 Camera
+ 30a2 Camera
+ 30a8 Elura 60E/Optura 40 (ptp)
+ 30a9 MVX25i (normal mode) / Optura 40 (normal mode)
+ 30b1 PowerShot S70 (normal mode) / PowerShot S70 (PTP mode)
+ 30b2 PowerShot S60 (normal mode) / PowerShot S60 (PTP mode)
+ 30b3 PowerShot G6 (normal mode) / PowerShot G6 (PTP mode)
+ 30b4 PowerShot S500
+ 30b5 PowerShot A75
+ 30b6 Digital IXUS II2 / Digital IXUS II2 (PTP mode) / PowerShot SD110 (PTP mode) / PowerShot SD110 Digital ELPH
+ 30b7 PowerShot A400 / PowerShot A400 (PTP mode)
+ 30b8 PowerShot A310 / PowerShot A310 (PTP mode)
+ 30b9 Powershot A85
+ 30ba PowerShot S410 Digital Elph
+ 30bb PowerShot A95
+ 30bd CP-220
+ 30be CP-330
+ 30bf Digital IXUS 40
+ 30c0 Digital IXUS 30 (PTP mode) / PowerShot SD200 (PTP mode)
+ 30c1 Digital IXUS 50 (normal mode) / IXY Digital 55 (normal mode) / PowerShot A520 (PTP mode) / PowerShot SD400 (normal mode)
+ 30c2 PowerShot A510 (normal mode) / PowerShot A510 (PTP mode)
+ 30c4 Digital IXUS i5 (normal mode) / IXY Digital L2 (normal mode) / PowerShot SD20 (normal mode)
+ 30ea EOS 1D Mark II (PTP mode)
+ 30eb EOS 20D
+ 30ec EOS 20D (ptp)
+ 30ee EOS 350D
+ 30ef EOS 350D (ptp)
+ 30f0 PowerShot S2 IS (PTP mode)
+ 30f2 Digital IXUS 700 (normal mode) / Digital IXUS 700 (PTP mode) / IXY Digital 600 (normal mode) / PowerShot SD500 (normal mode) / PowerShot SD500 (PTP mode)
+ 30f6 SELPHY CP400
+ 30f8 Powershot A430
+ 30f9 PowerShot A410 (PTP mode)
+ 30fc PowerShot A620 (PTP mode)
+ 30fd PowerShot A610 (normal mode)/PowerShot A610 (PTP mode)
+ 30ff Digital IXUS 55 (PTP mode)/PowerShot SD450 (PTP mode)
+ 310b SELPHY CP600
+ 310e Digital IXUS 50 (PTP mode)
+ 3116 Digital IXUS 750 (PTP mode)
+ 3117 PowerShot A700
+ 3138 PowerShot A710 IS
+ 315a PowerShot G9
+ 3176 PowerShot A590
+ 31ff Digital IXUS 55
+04aa DaeWoo Telecom, Ltd
+04ab Chromatic Research
+04ac Micro Audiometrics Corp.
+04ad Dooin Electronics
+ 2501 Bluetooth Device
+04af Winnov L.P.
+04b0 Nikon Corp.
+ 0102 Coolpix 990
+ 0103 Coolpix 880
+ 0104 Coolpix 995
+ 0106 Coolpix 775
+ 0107 Coolpix 5000
+ 0108 Coolpix 2500
+ 0109 Coolpix 2500 (ptp)
+ 010a Coolpix 4500
+ 010b Coolpix 4500 (ptp)
+ 010d Coolpix 5700 (ptp)
+ 010e Coolpix 4300 (storage)
+ 010f Coolpix 4300 (ptp)
+ 0110 Coolpix 3500 (Sierra Mode)
+ 0111 Coolpix 3500 (ptp)
+ 0112 Coolpix 885 (ptp)
+ 0113 Coolpix 5000 (ptp)
+ 0114 Coolpix 3100 (storage)
+ 0115 Coolpix 3100 (ptp)
+ 0117 Coolpix 2100 (ptp)
+ 0119 Coolpix 5400 (ptp)
+ 011d Coolpix 3700 (ptp)
+ 0121 Coolpix 3200 (ptp)
+ 0122 Coolpix 2200 (ptp)
+ 0126 Coolpix 8800
+ 0129 Coolpix 4800 (ptp)
+ 012c Coolpix 4100 (storage)
+ 012d Coolpix 4100 (ptp)
+ 012e Coolpix 5600 (ptp)
+ 0130 Coolpix 4600 (ptp)
+ 0135 Coolpix 5900 (ptp)
+ 0136 Coolpix 7900 (storage)
+ 0137 Coolpix 7900 (ptp)
+ 0141 Coolpix P2 (storage)
+ 0142 Coolpix P2 (ptp)
+ 0163 Coolpix P5100 (ptp)
+ 0169 Coolpix P50 (ptp)
+ 0202 Coolpix SQ (ptp)
+ 0203 Coolpix 4200 (mass storage mode)
+ 0204 Coolpix 4200 (ptp)
+ 0205 Coolpix 5200 (storage)
+ 0206 Coolpix 5200 (ptp)
+ 0301 Coolpix 2000 (storage)
+ 0302 Coolpix 2000 (ptp)
+ 0402 DSC D100 (ptp)
+ 0403 D2H (mass storage mode)
+ 0404 D2H SLR (ptp)
+ 0405 D70 (mass storage mode)
+ 0406 DSC D70 (ptp)
+ 0408 D2X SLR (ptp)
+ 0409 D50 digital camera
+ 040a D50 (ptp)
+ 040c D2Hs
+ 040e DSC D70s (ptp)
+ 0413 D40 (mass storage mode)
+ 4000 Coolscan LS 40 ED
+ 4001 LS 50 ED/Coolscan V ED
+ 4002 Super Coolscan LS-5000 ED
+04b1 Pan International
+04b3 IBM Corp.
+ 3003 Rapid Access III Keyboard
+ 3004 Media Access Pro Keyboard
+ 300a Rapid Access IIIe Keyboard
+ 3016 UltraNav Keyboard Hub
+ 3018 UltraNav Keyboard
+ 301b SK-8815 Keyboard
+ 301c Enhanced Performance Keyboard
+ 3020 Enhanced Performance Keyboard
+ 3100 NetVista Mouse
+ 3103 ScrollPoint Pro Mouse
+ 3104 ScrollPoint Wireless Mouse
+ 3105 ScrollPoint Optical (HID)
+ 3107 ThinkPad 800dpi Optical Travel Mouse
+ 3108 800dpi Optical Mouse w/ Scroll Point
+ 3109 Optical ScrollPoint Pro Mouse
+ 310b Red Wheel Mouse
+ 4427 Portable CD ROM
+ 4482 Serial Converter
+ 4525 Double sided CRT
+ 4550 NVRAM (128 KB)
+ 4554 Cash Drawer
+ 4580 Hub w/ NVRAM
+ 4581 4800-2xx Hub w/ Cash Drawer
+ 4604 Keyboard w/ Card Reader
+ 4671 4820 LCD w/ MSR/KB
+04b4 Cypress Semiconductor Corp.
+ 0000 Dacal DC-101 CD Library
+ 0001 Mouse
+ 0002 CY7C63x0x Thermometer
+ 0101 Keyboard/Hub
+ 0102 Keyboard with APM
+ 0130 MyIRC Remote Receiver
+ 0bad MetaGeek Wi-Spy
+ 1002 CY7C63001 R100 FM Radio
+ 1006 Human Interface Device
+ 4381 SCAPS USC-1 Scanner Controller
+ 4611 Storage Adapter FX2 (CY)
+ 4616 Flash Disk (TPP)
+ 5500 HID->COM RS232 Adapter
+ 6370 ViewMate Desktop Mouse CC2201
+ 6560 CY7C65640 USB-2.0 "TetraHub"
+ 6830 CY7C68300A EZ-USB AT2 USB 2.0 to ATA/ATAPI
+ 6831 Storage Adapter ISD-300LP (CY)
+ 7417 Wireless PC Lock
+ 8613 CY7C68013 EZ-USB FX2 USB 2.0 Development Kit
+ 8614 DTV-DVB UDST7020BDA DVB-S Box(DVBS for MCE2005)
+ cc04 Centor USB RACIA-ALVAR USB PORT
+ cc06 Centor-P RACIA-ALVAR USB PORT
+ d5d5 CY7C63x0x Zoltrix Z-Boxer GamePad
+ f000 CY30700 Licorice evaluation board
+04b5 ROHM LSI Systems USA, LLC
+04b6 Hint Corp.
+04b7 Compal Electronics, Inc.
+04b8 Seiko Epson Corp.
+ 0001 Stylus Color 740 / Photo 750
+ 0002 ISD Smart Cable for Mac
+ 0003 ISD Smart Cable
+ 0004 Printer
+ 0005 Stylus D88+
+ 0006 Printer
+ 0007 Printer
+ 0101 Perfection 636
+ 0102 GT-2200
+ 0103 Perfection 610
+ 0104 Perfection 1200
+ 0105 StylusScan 2000
+ 0106 Stylus Scan 2500
+ 0107 Expression 1600U
+ 0109 Expression 1640 XL
+ 010a Perfection 1640SU
+ 010b Perfection 1240
+ 010c Perfection 640
+ 010e Perfection 1680
+ 010f Perfection 1250
+ 0110 Perfection 1650
+ 0112 Perfection 2450
+ 0114 Perfection 660
+ 0116 Perfection 3170 (GT-9400)
+ 0118 Perfection 4180 (GF-F600)
+ 0119 Perfection 4490 Photo
+ 011a 1000 ICS
+ 011b Perfection 2400 Photo
+ 011c Perfection 3200
+ 011d Perfection 1260 Photo
+ 011e Perfection 1660 Photo
+ 011f Perfection 1670
+ 0120 Perfection 1270 scanner
+ 0121 Perfection 2480 Photo
+ 0122 Perfection 3590 scanner
+ 0126 GT-15000 (ES-7000)
+ 0128 Perfection 4870 (GT-X700)
+ 0129 Expression 10000XL (ES-10000G)
+ 012a Perfection 4990 Photo scanner
+ 012b GT-2500 (ES-H300)
+ 012c Perfection V350 (GT-F700)
+ 012d Perfection V10/V100 (GT-S600/F650)
+ 012f Perfection V350 (GT-F700)
+ 0202 Receipt Printer M129C
+ 0401 CP 800 Digital Camera
+ 0402 PhotoPC 850z
+ 0403 PhotoPC 3000z
+ 0509 JVC PIX-MC10
+ 0601 Stylus Photo 875DC Card Reader
+ 0602 Stylus Photo 895 Card Reader
+ 0801 Stylus CX5200/CX5400/CX6600
+ 0802 Stylus CX3200
+ 0803 Printer (Composite Device)
+ 0804 Storage Device
+ 0805 Stylus CX6400
+ 0806 Stylus Photo RX600/610
+ 0807 Stylus Photo RX500/510
+ 0808 Stylus CX5200
+ 0809 Storage Device
+ 080a Storage Device
+ 080c ME100
+ 080d Stylus CX4500/4600
+ 080e CX-3500/3600/3650 MFP
+ 080f Stylus Photo RX425 scanner
+ 0810 Stylus Photo RX700 (PM-A900)
+ 0811 Stylus Photo RX620 all-in-one
+ 0812 MFP Composite Device
+ 0813 Stylus CX6500/6600
+ 0814 (PM-A700)
+ 0815 AcuLaser CX11 (LP-A500)
+ 0816 Printer (Composite Device)
+ 0817 (LP-M5500)
+ 0818 Stylus CX3700/CX3800/DX3800
+ 0819 Stylus CX4700/CX4800/DX4800 (PX-A750)
+ 081a Stylus Photo RX520/RX530 (PM-A750)
+ 081b MFP Composite Device
+ 081c Stylus Photo RX640/RX650 (PM-A890)
+ 081d (PM-A950)
+ 081e MFP Composite Device
+ 081f Stylus CX7700/7800
+ 0820 CX4200 MP scanner
+ 0821 MFP Composite Device
+ 0822 Storage Device
+ 0823 MFP Composite Device
+ 0824 Storage Device
+ 0825 MFP Composite Device
+ 0826 Storage Device
+ 0827 Stylus Photo RX560/580/590 (PM-A820)
+ 0828 (PM-A970)
+ 0829 (PM-T990)
+ 082a (PM-A920)
+ 082b Stylus DX5050
+ 082c Storage Device
+ 082d Storage Device
+ 082e 0x082e DX-60x0 MFP scanner
+ 082f Stylus DX4050
+ 0830 Stylus CX2800/CX2900/ME200
+ 0831 MFP Composite Device
+ 0832 MFP Composite Device
+ 0833 (LP-M5600)
+ 0834 MFP Composite Device
+ 0835 AcuLaser CX21
+ 0836 MFP Composite Device
+ 0837 MFP Composite Device
+ 0838 CX7300/CX7400/DX7400
+ 0839 CX8300/CX8400/DX8400
+ 083a CX9300F/CX9400Fax/DX9400F
+ 083b MFP Composite Device
+ 083c MFP Composite Device
+ 083d MFP Composite Device
+ 083e MFP Composite Device
+ 083f Stylus DX4450
+04b9 Rainbow Technologies, Inc.
+ 0300 SafeNet USB SuperPro/UltraPro
+ 1000 iKey 1000 Token
+ 1001 iKey 1200 Token
+ 1002 iKey Token
+ 1003 iKey Token
+ 1004 iKey Token
+ 1005 iKey Token
+ 1006 iKey Token
+ 1200 iKey 2000 Token
+ 1201 iKey Token
+ 1202 iKey 2032 Token
+ 1203 iKey Token
+ 1204 iKey Token
+ 1205 iKey Token
+ 1206 iKey Token
+ 1300 iKey 3000 Token
+ 1301 iKey 3000
+ 1302 iKey Token
+ 1303 iKey Token
+ 1304 iKey Token
+ 1305 iKey Token
+ 1306 iKey Token
+04ba Toucan Systems, Ltd
+04bb I-O Data Device, Inc.
+ 0101 USB2-IDE/ATAPI Bridge Adapter
+ 0201 USB2-IDE/ATAPI Bridge Adapter
+ 0204 DVD Multi-plus unit iU-CD2
+ 0206 DVD Multi-plus unit DVR-UEH8
+ 0301 Storage Device
+ 0314 USB-SSMRW SD-card
+ 0319 USB2-IDE/ATAPI Bridge Adapter
+ 031a USB2-IDE/ATAPI Bridge Adapter
+ 031b USB2-IDE/ATAPI Bridge Adapter
+ 031e USB-SDRW SD-card
+ 0502 Nogatech Live! (BT)
+ 0901 USB ETT
+ 0904 ET/TX Ethernet [pegasus]
+ 0913 ET/TX-S Ethernet [pegasus2]
+ 0919 USB WN-B11
+ 0922 IOData AirPort WN-B11/USBS 802.11b
+ 0930 ETG-US2
+ 0937 WN-WAG/USL Wireless LAN Adapter
+ 0938 WN-G54/USL Wireless LAN Adapter
+ 0a03 Serial USB-RSAQ1
+ 0a07 USB2-iCN Adapter
+ 0a08 USB2-iCN Adapter
+ 0c01 FM-10 Pro Disk
+04bd Toshiba Electronics Taiwan Corp.
+04be Telia Research AB
+04bf TDK Corp.
+ 0100 MediaReader CF
+ 0115 USB-PDC Adapter UPA9664
+ 0116 USB-cdmaOne Adapter UCA1464
+ 0117 USB-PHS Adapter UHA6400
+ 0118 USB-PHS Adapter UPA6400
+ 0135 MediaReader Dual
+ 0202 73S1121F Smart Card Reader-
+ 0309 Bluetooth USB dongle
+ 030a IBM Bluetooth Ultraport Module
+ 030b Bluetooth Device
+ 030c Ultraport Bluetooth Device
+ 0310 Integrated Bluetooth
+ 0311 Integrated Bluetooth Device
+ 0317 Bluetooth UltraPort Module from IBM
+ 0318 IBM Integrated Bluetooth
+ 0319 Bluetooth Adapter
+ 0320 Bluetooth Adapter
+ 0321 Bluetooth Device
+ 0a28 INDI AV-IN Device
+04c1 U.S. Robotics (3Com)
+ 0020 56K Voice Pro
+ 0022 56K Voice Pro
+ 007e ISDN TA
+ 0082 OfficeConnect Analog Modem
+ 008f Pro ISDN TA
+ 0097 OfficeConnect Analog
+ 009d HomeConnect WebCam [vicam]
+ 00a9 ISDN Pro TA-U
+ 00b9 HomeConnect IDSL Modem
+ 3021 56k Voice FaxModem Pro
+04c2 Methode Electronics Far East PTE, Ltd
+04c3 Maxi Switch, Inc.
+ 1102 Mouse
+ 2102 Mouse
+04c4 Lockheed Martin Energy Research
+04c5 Fujitsu, Ltd
+ 1029 fi-4010c Scanner
+ 1033 fi-4110CU
+ 1041 fi-4120c Scanner
+ 1042 fi-4220c Scanner
+ 105b AH-F401U Air H device
+ 1096 fi-5110EOX
+ 1097 fi-5110C
+ 10ae fi-4120C2
+ 10af fi-4220C2
+ 10e0 fi-5120c Scanner
+ 10e1 fi-5220C
+ 10e7 fi-5900C
+ 10fe S500
+04c6 Toshiba America Electronic Components
+04c7 Micro Macro Technologies
+04c8 Konica Corp.
+ 0720 Digital Color Camera
+ 0721 e-miniD Camera
+ 0722 e-mini
+ 0723 KD-200Z Camera
+ 0726 KD-310Z Camera
+ 0728 Revio C2 Mass Storage Device
+ 0729 Revio C2 Digital Camera
+ 072c Revio KD20M
+ 072d Revio KD410Z
+04ca Lite-On Technology Corp.
+ 1766 HID Monitor Controls
+ 9304 Hub
+04cb Fuji Photo Film Co., Ltd
+ 0100 FinePix 30i/40i/50i, A101/201, 1300/2200, 1400/2400/2600/2800/4500/4700/4800/4900/6800/6900 Zoom
+ 0103 FinePix NX-500/NX-700 printer
+ 0104 FinePix A101, 2600/2800/4800/6800 Zoom (PC CAM)
+ 0108 FinePix F601 Zoom (DSC)
+ 0109 FinePix F601 Zoom (PC CAM)
+ 010a FinePix S602 (Pro) Zoom (DSC)
+ 010b FinePix S602 (Pro) Zoom (PC CAM)
+ 010d FinePix Digital Camera 020531
+ 010e FinePix F402 Zoom (DSC)
+ 010f FinePix F402 Zoom (PC CAM)
+ 0110 FinePix M603 Zoom (DSC)
+ 0111 FinePix M603 Zoom (PC CAM)
+ 0112 FinePix A202, A200 Zoom (DSC)
+ 0113 FinePix A202, A200 Zoom (PC CAM)
+ 0114 FinePix F401 Zoom (DSC)
+ 0115 FinePix F401 Zoom (PC CAM)
+ 0116 FinePix A203 Zoom (DSC)
+ 0117 FinePix A203 Zoom (PC CAM)
+ 0118 FinePix A303 Zoom (DSC)
+ 0119 FinePix A303 Zoom (PC CAM)
+ 011a FinePix S304/3800 Zoom (DSC)
+ 011b FinePix S304/3800 Zoom (PC CAM)
+ 011c FinePix A204/2650 Zoom (DSC)
+ 011d FinePix A204/2650 Zoom (PC CAM)
+ 0120 FinePix F700 Zoom (DSC)
+ 0121 FinePix F700 Zoom (PC CAM)
+ 0122 FinePix F410 Zoom (DSC)
+ 0123 FinePix F410 Zoom (PC CAM)
+ 0124 FinePix A310 Zoom (DSC)
+ 0125 FinePix A310 Zoom (PC CAM)
+ 0126 FinePix A210 Zoom (DSC)
+ 0127 FinePix A210 Zoom (PC CAM)
+ 0128 FinePix A205(S) Zoom (DSC)
+ 0129 FinePix A205(S) Zoom (PC CAM)
+ 012a FinePix F610 Zoom (DSC)
+ 012b FinePix Digital Camera 030513
+ 012c FinePix S7000 Zoom (DSC)
+ 012d FinePix S7000 Zoom (PC CAM)
+ 012f FinePix Digital Camera 030731
+ 0130 FinePix S5000 Zoom (DSC)
+ 0131 FinePix S5000 Zoom (PC CAM)
+ 013b FinePix Digital Camera 030722
+ 013c FinePix S3000 Zoom (DSC)
+ 013d FinePix S3000 Zoom (PC CAM)
+ 013e FinePix F420 Zoom (DSC)
+ 013f FinePix F420 Zoom (PC CAM)
+ 0142 FinePix S7000 Zoom (PTP)
+ 0148 FinePix A330 Zoom (DSC)
+ 0149 FinePix A330 Zoom (UVC)
+ 014a FinePix A330 Zoom (PTP)
+ 014b FinePix A340 Zoom (DSC)
+ 0159 FinePix F710 Zoom (DSC)
+ 0165 FinePix S3500 Zoom (DSC)
+ 0168 FinePix E500 Zoom (DSC)
+ 0169 FinePix E500 Zoom (UVC)
+ 016b FinePix E510 Zoom (DSC)
+ 016c FinePix E510 Zoom (PC CAM)
+ 016e FinePix S5500 Zoom (DSC)
+ 016f FinePix S5500 Zoom (UVC)
+ 0171 FinePix E550 Zoom (DSC)
+ 0172 FinePix E550 Zoom (PTP)
+ 0177 FinePix F10 (DSC)
+ 0179 Finepix F10 (PTP)
+ 0186 FinePix S5200/S5600 Zoom (DSC)
+ 0188 FinePix S5200/S5600 Zoom (PTP)
+ 018e FinePix S9500 Zoom (DSC)
+ 018f FinePix S9500 Zoom (PTP)
+ 0192 FinePix E900 Zoom (DSC)
+ 0193 FinePix E900 Zoom (PTP)
+ 019b FinePix F30 (PTP)
+ 01bf FinePix F6000fd/S6500fd Zoom (PTP)
+ 01c0 FinePix F20 (PTP)
+ 01c1 FinePix F31fd (PTP)
+ 01c4 FinePix S5700 Zoom (PTP)
+ 01c5 FinePix F40fd (PTP)
+ 01c6 FinePix A820 Zoom (PTP)
+ 01d2 FinePix A800 Zoom (PTP)
+ 01d5 FinePix F47 (PTP)
+04cc Philips Semiconductors
+ 1122 Hub
+ 1521 USB 2.0 Hub
+ 8116 Camera
+04cd Tatung Co. Of America
+04ce ScanLogic Corp.
+ 0002 SL11R-IDE IDE Bridge
+ 0100 USB2PRN Printer Class
+ 0300 Phantom 336CX - C3 scanner
+ 04ce SL11DEMO, VID: 0x4ce, PID: 0x4ce
+ 07d1 SL11R, VID: 0x4ce, PID: 0x07D1
+04cf Myson Century, Inc.
+ 0800 MTP800 Mass Storage Device
+ 8810 CS8810 Mass Storage Device
+ 8811 CS8811 Mass Storage Device
+ 8813 CS8813 Mass Storage Device
+ 8818 USB2.0 to ATAPI Bridge Controller
+04d0 Digi International
+04d1 ITT Canon
+04d2 Altec Lansing Technologies
+ 0070 ADA70 Speakers
+ 0305 Non-Compliant Audio Device
+ 0311 ADA-310 Speakers
+ 2060 Claritel-i750 - vp
+ ff05 ADA-305 Speakers
+ ff47 Lansing HID Audio Controls
+ ff49 Lansing HID Audio Controls
+04d3 VidUS, Inc.
+04d4 LSI Logic, Inc.
+04d5 Forte Technologies, Inc.
+04d6 Mentor Graphics
+04d7 Oki Semiconductor
+ 1be4 Bluetooth Device
+04d8 Microchip Technology, Inc.
+ 0002 USB-LCD 2x20
+ 8000 In-Circuit Debugger
+ 8001 ICD2 in-circuit debugger
+04d9 Holtek Semiconductor, Inc.
+ 1203 MC Industries Keyboard
+04da Panasonic (Matsushita)
+ 0901 LS-120 Camera
+ 0b01 CD-R/RW Drive
+ 0b03 SuperDisk 240MB
+ 0d01 CD-R Drive KXL-840AN
+ 0d09 CD-R Drive KXL-RW32AN
+ 0d0a CD-R Drive KXL-CB20AN
+ 0d0d CDRCB03
+ 0d0e DVD-ROM & CD-R/RW
+ 0f40 Printer
+ 1500 MFSUSB Driver
+ 1b00 MultiMediaCard
+ 2121 EB-VS6
+ 2317 DVC USB-SERIAL Driver for WinXP
+ 2319 NV-GS15 (webcam mode)
+ 231d DVC Web Camera Device
+ 231e DVC DV Stream Device
+ 2372 Lumix DMC-FZ10 Camera
+ 2374 DMC-FZ20
+04db Hypertec Pty, Ltd
+04dc Huan Hsin Holdings, Ltd
+04dd Sharp Corp.
+ 13a6 MFC2000
+ 6006 AL-1216
+ 6007 AL-1045
+ 6008 AL-1255
+ 6009 AL-1530CS
+ 600a AL-1540CS
+ 600b AL-1456
+ 600c AL-1555
+ 600d AL-1225
+ 600e AL-1551CS
+ 600f AR-122E
+ 6010 AR-152E
+ 6011 AR-157E
+ 6012 SN-1045
+ 6013 SN-1255
+ 6014 SN-1456
+ 6015 SN-1555
+ 6016 AR-153E
+ 6017 AR-122E N
+ 6018 AR-153E N
+ 6019 AR-152E N
+ 601a AR-157E N
+ 601b AL-1217
+ 601c AL-1226
+ 601d AR-123E
+ 7002 DVC Ver.1.0
+ 7004 VE-CG40U Digital Still Camera
+ 7005 VE-CG30 Digital Still Camera
+ 7007 VL-Z7S Digital Camcorder
+ 8004 Zaurus SL-5000D/SL-5500 PDA
+ 8005 Zaurus A-300
+ 8006 Zaurus SL-B500/SL-5600 PDA
+ 8007 Zaurus C-700 PDA
+ 9014 IM-DR80 Portable NetMD Player
+ 9031 Zaurus C-750/C-760/C-860/SL-C3000 PDA
+ 9032 Zaurus SL-6000
+ 903a GSM GPRS
+ 9050 Zaurus C-860 PDA
+ 9056 Viewcam Z
+ 9073 AM-900
+ 9074 GSM GPRS
+ 90a9 Sharp Composite
+ 90d0 USB-to-Serial Comm. Port
+ 90f2 Sharp 3G GSM USB Control
+ 9120 WS004SH
+ 9122 WS007SH
+ 9123 W-ZERO3 ES Smartphone
+ 91a3 922SH Internet Machine
+04de MindShare, Inc.
+04df Interlink Electronics
+04e1 Iiyama North America, Inc.
+ 0201 Monitor Hub
+04e2 Exar Corp.
+04e3 Zilog, Inc.
+04e4 ACC Microelectronics
+04e5 Promise Technology
+04e6 SCM Microsystems, Inc.
+ 0001 E-USB ATA Bridge
+ 0002 eUSCSI SCSI Bridge
+ 0003 eUSB SmartMedia Card Reader
+ 0005 eUSB SmartMedia/CompactFlash Card Reader
+ 0006 eUSB SmartMedia Card Reader
+ 0007 Hifd
+ 0009 eUSB ATA/ATAPI Adapter
+ 000a eUSB CompactFlash Adapter
+ 000b eUSCSI Bridge
+ 000c eUSCSI Bridge
+ 000d Dazzle MS
+ 0012 Dazzle SD/MMC
+ 0101 eUSB ATA Bridge
+ 0311 Dazzle DM-CF
+ 0312 Dazzle DM-SD/MMC
+ 0313 Dazzle SM
+ 0314 Dazzle MS
+ 0322 e-Film Reader-5
+ 0325 eUSB ORCA Quad Reader
+ 0327 Digital Media Reader
+ 03fe DMHS2 DFU Adapter
+ 0406 eUSB SmartDM Reader
+ 04e6 eUSB DFU Adapter
+ 04e7 STCII DFU Adapter
+ 04e8 eUSBDM DFU Adapter
+ 04e9 DM-E DFU Adapter
+ 0500 Veridicom 5thSense Fingerprint Sensor and eUSB SmartCard
+ 0701 DCS200 Loader Device
+ 0702 DVD Creation Station 200
+ 0703 DVC100 Loader Device
+ 0704 Digital Video Creator 100
+ 1001 SCR300 Smart Card Reader
+ 1010 USBAT-2 CompactFlash Card Reader
+ 1014 e-Film Reader-3
+ 1020 USBAT ATA/ATAPI Adapter
+ 2007 RSA SecurID ComboReader
+ 2009 Citibank Smart Card Reader
+ 200a Reflex v.2 Smart Card Reader
+ 200d STR391 Reader
+ 5111 SCR331-DI SmartCard Reader
+ 5113 SCR333 SmartCard Reader
+ 5114 SCR331-DI SmartCard Reader
+ 5115 SCR335 SmartCard Reader
+ 5116 SCR331-LC1 SmartCard Reader
+ 5117 SCR3320 - Smart Card Reader
+ 5118 Expresscard SIM Card Reader
+ 5119 SCR3340 - ExpressCard54 Smart Card Reader
+ 511b SmartCard Reader
+ 511d SCR3311 Smart Card Reader
+ 5120 SCR331-DI SmartCard Reader
+ 5121 SDI010 Smart Card Reader
+ 5151 SCR338 Keyboard Smart Card Reader
+ 5410 SCR35xx Smart Card Reader
+ e000 SCRx31 Reader
+ e001 SCR331 SmartCard Reader
+ e003 SPR532 PinPad SmartCard Reader
+04e7 Elo TouchSystems
+ 0001 TouchScreen
+ 0002 Touchmonitor Interface 2600 Rev 2
+ 0004 4000U CarrollTouch® Touchmonitor Interface
+ 0007 2500U IntelliTouch® Touchmonitor Interface
+ 0008 3000U AccuTouch® Touchmonitor Interface
+ 0009 4000U CarrollTouch® Touchmonitor Interface
+ 0020 Touchscreen Interface (2700)
+ 0021 Touchmonitor Interface
+ 0030 4500U CarrollTouch® Touchmonitor Interface
+ 0032 Touchmonitor Interface
+ 0033 Touchmonitor Interface
+ 0041 5010 Surface Capacitive Touchmonitor Interface
+ 0042 Touchmonitor Interface
+ 0050 2216 AccuTouch® Touchmonitor Interface
+ 0071 Touchmonitor Interface
+ 0072 Touchmonitor Interface
+ 0081 Touchmonitor Interface
+ 0082 Touchmonitor Interface
+ 00ff Touchmonitor Interface
+04e8 Samsung Electronics Co., Ltd
+ 0110 Connect3D Flash Drive
+ 0111 Connect3D Flash Drive
+ 1003 MP3 Player and Recorder
+ 1006 SDC-200Z
+ 3004 ML-4600
+ 3005 Docuprint P1210
+ 3008 ML-6060 laser printer
+ 300c ML-1210 Printer
+ 300e Laser Printer
+ 3104 ML-3550N
+ 3226 Laser Printer
+ 3228 Laser Printer
+ 322a Laser Printer
+ 322c Laser Printer
+ 3230 ML-1440
+ 3232 Laser Printer
+ 3236 ML-1450
+ 3238 ML-1430
+ 323a ML-1710 Printer
+ 323b Phaser 3130
+ 323c Laser Printer
+ 323d Phaser 3120
+ 323e Laser Printer
+ 3240 Laser Printer
+ 3242 Laser Printer
+ 3248 Color Laser Printer
+ 324a Laser Printer
+ 324c ML-1740 Printer
+ 324d Phaser 3121
+ 325f Phaser 3425 Laser Printer
+ 3260 CLP-510 Color Laser Printer
+ 3268 ML-1610 Mono Laser Printer
+ 326c ML-2010P Mono Laser Printer
+ 3409 SCX-4216F Scanner
+ 340c SCX-5x15 Series
+ 340d SCX-6x20 Series
+ 340e MFP 560 Series
+ 340f Printing Support
+ 3412 SCX-4x20 Series
+ 3413 SCX-4100 Scanner
+ 3415 Composite Device
+ 3419 Composite Device
+ 341a Printing Support
+ 341b SCX-4200 Series
+ 341c Composite Device
+ 341d Composite Device
+ 341f Composite Device
+ 3420 Composite Device
+ 3605 InkJet Color Printer
+ 3606 InkJet Color Printer
+ 3609 InkJet Color Printer
+ 3902 InkJet Color Printer
+ 3903 Xerox WorkCentre XK50cx
+ 390f InkJet Color Printer
+ 3911 SCX-1020 Series
+ 5000 YP-MF Series
+ 5001 YP-100
+ 5002 YP-30
+ 5003 YP-700
+ 5004 YP-30
+ 5005 YP-300
+ 5006 YP-750
+ 500d MP3 Player
+ 5010 MP3 Player
+ 5011 YP-780
+ 5013 YP-60
+ 5015 yepp upgrade
+ 501b MP3 Player
+ 503b YP-U1 MP3 Player
+ 5050 YP-U2 MP3 Player
+ 507d YP-U3 MP3 Player
+ 508b YP-S5 MP3 Player
+ 5a00 YP-NEU
+ 5a01 YP-NDU
+ 5a03 Yepp MP3 Player
+ 5a04 YP-800
+ 5a08 YP-90
+ 5a0f MTP Device
+ 5b01 Memory Stick Reader/Writer
+ 5b02 Memory Stick Reader/Writer
+ 5b03 Memory Stick Reader/Writer
+ 5b04 Memory Stick Reader/Writer
+ 5b05 Memory Stick Reader/Writer
+ 5b11 SEW-2001u Card
+ 5f00 NEXiO Sync
+ 5f01 NEXiO Sync
+ 5f02 NEXiO Sync
+ 5f03 NEXiO Sync
+ 5f04 NEXiO Sync
+ 6601 Z100 Mobile Phone
+ 6611 MITs Sync
+ 6613 MITs Sync
+ 6615 MITs Sync
+ 6617 MITs Sync
+ 6619 MITs Sync
+ 661b MITs Sync
+ 661e Handheld
+ 6620 Handheld
+ 6622 Handheld
+ 6624 Handheld
+ 662e MITs Sync
+ 6630 MITs Sync
+ 6632 MITs Sync
+ 663f SGH-E720/SGH-E840
+ 6640 Usb Modem Enumerator
+ 7011 SEW-2003U Card
+ 7021 Bluetooth Device
+ 7061 eHome Infrared Receiver
+ 7081 Human Interface Device
+ 8001 Handheld
+ e020 SERI E02 SCOM 6200 UMTS Phone
+ e021 SERI E02 SCOM 6200 Virtual UARTs
+ e022 SERI E02 SCOM 6200 Flash Load Disk
+ ff30 SG_iMON
+04e9 PC-Tel, Inc.
+04ea Brooktree Corp.
+04eb Northstar Systems, Inc.
+04ec Tokyo Electron Device, Ltd
+04ed Annabooks
+04ef Pacific Electronic International, Inc.
+04f0 Daewoo Electronics Co., Ltd
+04f1 Victor Company of Japan, Ltd
+ 0001 GC-QX3 Digital Still Camera
+ 0004 GR-DVL815U Digital Video Camera
+ 0006 DV Camera Storage
+ 0008 GZ-MG30AA/MC500E Digital Video Camera
+ 0009 GR-DX25EK Digital Video Camera
+ 000a GR-D72 Digital Video Camera
+ 3008 MP-PRX1 Ethernet
+04f2 Chicony Electronics Co., Ltd
+ 0001 KU-8933 Keyboard
+ 0002 NT68P81 Keyboard
+ 0110 KU-2971 Keyboard
+ 0111 KU-9908 Keyboard
+ 0112 KU-8933 Keyboard with PS/2 Mouse port
+ 0116 KU-2971 German Keyboard
+ 0403 KU-0420 keyboard
+ a001 E-Video DC-100 Camera
+ a120 ORITE CCD Webcam(PC370R)
+ a121 ORITE CCD Webcam(PC370R)
+ a122 ORITE CCD Webcam(PC370R)
+ a123 ORITE CCD Webcam(PC370R)
+ a124 ORITE CCD Webcam(PC370R)
+ a133 Gateway Webcam
+ a204 DSC WIA Device (1300)
+ a208 DSC WIA Device (2320)
+ a209 Labtec DC-2320
+ a20a DSC WIA Device (3310)
+ a20c DSC WIA Device (3320)
+ a210 Audio Device
+ b009 Integrated Camera
+ b010 Integrated Camera
+ b012 1.3 MPixel UVC webcam
+ b018 Video Device
+ b022 Camera
+ b025 Camera
+ b027 Gateway Webcam
+ b028 VGA UVC WebCam
+04f3 Elan Microelectronics Corp.
+ 0210 AM-400 Hama Optical Mouse
+04f4 Harting Elektronik, Inc.
+04f5 Fujitsu-ICL Systems, Inc.
+04f6 Norand Corp.
+04f7 Newnex Technology Corp.
+04f8 FuturePlus Systems
+04f9 Brother Industries, Ltd
+ 0002 HL-1050 Laser Printer
+ 0005 Printer
+ 0006 HL-1240 Laser Printer
+ 0007 HL-1250 Laser Printer
+ 0008 HL-1270 Laser Printer
+ 0009 Printer
+ 000a P2500 Series
+ 000b Printer
+ 000c Printer
+ 000d HL-1440 Laser Printer
+ 000e HL-1450 series
+ 000f HL-1470N series
+ 0010 Printer
+ 0011 Printer
+ 0012 Printer
+ 0013 Printer
+ 0014 Printer
+ 0015 Printer
+ 0016 Printer
+ 0017 Printer
+ 0018 Printer
+ 001c Printer
+ 001e Printer
+ 0020 HL-5130 series
+ 0021 HL-5140 series
+ 0022 HL-5150D series
+ 0023 HL-5170DN series
+ 0024 Printer
+ 0025 Printer
+ 0027 HL-2030 Laser Printer
+ 0028 Printer
+ 0029 Printer
+ 002a Printer
+ 002b Printer
+ 002c Printer
+ 002d Printer
+ 0100 MFC8600/9650 Series
+ 0101 MFC9600/9870 Series
+ 0102 MFC9750/1200 Series
+ 0104 MFC-8300J
+ 0105 MFC-9600J
+ 0106 MFC-7300C
+ 0107 MFC-7400C
+ 0108 MFC-9200C
+ 0109 MFC-830
+ 010a MFC-840
+ 010b MFC-860
+ 010c MFC-7400J
+ 010d MFC-9200J
+ 010e MFC3100C Scanner
+ 010f MFC 5100C
+ 0110 MFC4800 Scanner
+ 0111 MFC 6800
+ 0112 DCP1000 Port(FaxModem)
+ 0113 MFC-8500
+ 0114 MFC9700 Port(FaxModem)
+ 0115 MFC9800 Scanner
+ 0116 DCP1400 Scanner
+ 0119 MFC-9660
+ 011b MFC-9880
+ 011c MFC-9760
+ 011d MFC-9070
+ 011e MFC-9180
+ 011f MFC-9160
+ 0120 MFC580 Port(FaxModem)
+ 0121 MFC-590
+ 0122 MFC-5100J
+ 0129 Imagistics 2500 (MFC-8640D clone)
+ 012f FAX-4750e
+ 0132 MFC-5200C RemovableDisk
+ 0135 MFC-100 Scanner
+ 0136 MFC-150CL Scanner
+ 013c MFC-890 Port
+ 013d MFC-5200J Printer
+ 013e MFC-4420C RemovableDisk
+ 013f MFC-4820C RemovableDisk
+ 0140 DCP-8020
+ 0141 DCP-8025D
+ 0142 MFC-8420
+ 0143 MFC-8820D
+ 0144 DCP-4020C RemovableDisk
+ 0146 MFC-3220C
+ 0147 FAX-1820C Printer
+ 0148 MFC-3320CN Printer
+ 0149 FAX-1920CN Printer
+ 014a MFC-3420C
+ 014b MFC-3820CN
+ 014d FAX-1815C Printer
+ 014e MFC-8820J
+ 0150 MFC-8220 Port(FaxModem)
+ 0151 MFC-8210J
+ 0157 MFC-3420J Printer
+ 0158 MFC-3820JN Port(FaxModem)
+ 015d MFC Composite Device
+ 015e DCP-8045D
+ 015f MFC-8440
+ 0160 MFC-8840D
+ 0161 MFC-210C
+ 0162 MFC-420CN Remote Setup Port
+ 0163 MFC-410CN RemovableDisk
+ 0165 MFC-620CN
+ 0166 MFC-610CLN RemovableDisk
+ 0168 MFC-620CLN
+ 0169 DCP-110C RemovableDisk
+ 016b DCP-310CN RemovableDisk
+ 016c FAX-2440C Printer
+ 016d MFC-5440CN
+ 016e MFC-5840CN Remote Setup Port
+ 0170 FAX-1840C Printer
+ 0171 FAX-1835C Printer
+ 0172 FAX-1940CN Printer
+ 0173 MFC-3240C Remote Setup Port
+ 0174 MFC-3340CN RemovableDisk
+ 017b Imagistics sx2100
+ 0180 MFC-7420
+ 0181 MFC-7820N Port(FaxModem)
+ 0182 Composite Device
+ 0183 DCP-7020
+ 0184 DCP-7025 Printer
+ 0185 MFC-7220 Printer
+ 0186 Composite Device
+ 0187 FAX-2820 Printer
+ 0188 FAX-2920 Printer
+ 018a MFC-9420CN
+ 018c DCP-115C
+ 018d DCP-116C
+ 018e DCP-117C
+ 018f DCP-118C
+ 0190 DCP-120C
+ 0191 DCP-315CN
+ 0192 DCP-340CW
+ 0193 MFC-215C
+ 0194 MFC-425CN
+ 0195 MFC-820CW Remote Setup Port
+ 0196 MFC-820CN Remote Setup Port
+ 0197 MFC-640CW
+ 019a MFC-840CLN Remote Setup Port
+ 01a2 MFC-8640D
+ 01a3 Composite Device
+ 01a4 DCP-8065DN Printer
+ 01a5 MFC-8460N Port(FaxModem)
+ 01a6 MFC-8860DN Port(FaxModem)
+ 01a7 MFC-8870DW Printer
+ 01a8 DCP-130C
+ 01a9 DCP-330C
+ 01aa DCP-540CN
+ 01ab MFC-240C
+ 01ae DCP-750CW RemovableDisk
+ 01af MFC-440CN
+ 01b0 MFC-660CN
+ 01b1 MFC-665CW Remote Setup Port
+ 01b2 MFC-845CW Remote Setup Port
+ 01b4 MFC-460CN Remote Setup Port
+ 01b5 MFC-630CD
+ 01b6 MFC-850CDN
+ 01b7 MFC-5460CN Remote Setup Port
+ 01b8 MFC-5860CN
+ 01ba MFC-3360C
+ 01bd MFC-8660DN
+ 01be DCP-750CN RemovableDisk
+ 01bf MFC-860CDN Remote Setup Port
+ 01c0 DCP-128C
+ 01c1 DCP-129C
+ 01c2 DCP-131C
+ 01c3 DCP-329C
+ 01c4 DCP-331C
+ 01c5 MFC-239C
+ 01ca MFC-9440CN Remote Setup Port
+ 01ce DCP-135C
+ 01cf DCP-150C
+ 01d0 DCP-350C
+ 01d1 DCP-560CN
+ 01d4 MFC-230C
+ 01d5 MFC-235C
+ 01d6 MFC-260C
+ 01df DCP-155C
+ 01e0 MFC-265C
+ 01e1 DCP-153C
+ 01e2 DCP-157C
+ 01e3 DCP-353C
+ 01e4 DCP-357C
+ 1000 Printer
+ 1002 Printer
+ 2002 PTUSB Printing
+ 2004 PT-2300/2310 p-Touch Laber Printer
+ 2015 QL-500 P-touch label printer
+ 2100 Card Reader Writer
+04fa Dallas Semiconductor
+ 2490 DS1490F 2-in-1 Fob, 1-Wire adapter
+ 4201 DS4201 Audio DAC
+04fb Biostar Microtech International Corp.
+04fc Sunplus Technology Co., Ltd
+ 0003 CM1092 Optical Scroller Mouse
+ 0013 ViewMate Desktop Mouse CC2201
+ 0015 ViewMate Desktop Mouse CC2201
+ 0232 Fingerprint
+ 0561 Flexcam 100
+ 1533 Mass Storage
+ 504a SPCA504a Digital Camera
+ 504b Aiptek, 1.3 mega PockerCam
+ 5330 Digitrex 2110
+ 5331 Vivitar Vivicam 10
+ 5720 Card Reader Driver
+ 7333 Finet Technology Palmpix DC-85
+ 757a Aiptek, MP315 MP3 Player
+ ffff PureDigital Ritz Disposable
+04fd Soliton Systems, K.K.
+ 0003 Smart Card Reader II
+04fe PFU, Ltd
+04ff E-CMOS Corp.
+0500 Siam United Hi-Tech
+ 0001 DART Keyboard Mouse
+ 0002 DART-2 Keyboard
+0501 Fujikura DDK, Ltd
+0502 Acer, Inc.
+ 0001 Handheld
+ 0736 Handheld
+ 15b1 PDA n311
+ 1631 c10 Series
+ 1632 c20 Series
+ 16e1 n10 Handheld Sync
+ 16e2 n20 Pocket PC Sync
+ 16e3 n30 Handheld Sync
+ d001 Divio NW801/DVC-V6+ Digital Camera
+0503 Hitachi America, Ltd
+0504 Hayes Microcomputer Products
+0506 3Com Corp.
+ 009d HomeConnect Camera
+ 00a0 3CREB96 Bluetooth Adapter
+ 00a1 Bluetooth Device
+ 00a2 Bluetooth Device
+ 00df 3Com Home Connect lite
+ 0100 HomeConnect ADSL Modem Driver
+ 03e8 3C19250 Ethernet [klsi]
+ 0a01 3CRSHEW696 Wireless Adapter
+ 0a11 3CRWE254G72 802.11g Adapter
+ 11f8 HomeConnect 3C460
+ 2922 HomeConnect Cable Modem External with
+ 3021 U.S.Robotics 56000 Voice FaxModem Pro
+ 4601 3C460B 10/100 Ethernet Adapter
+ f002 3CP4218 ADSL Modem (pre-init)
+ f003 3CP4218 ADSL Modem
+ f100 3CP4218 ADSL Modem (pre-init)
+0507 Hosiden Corp.
+ 0011 Konami ParaParaParadise Controller
+0508 Clarion Co., Ltd
+0509 Aztech Systems, Ltd
+ 0801 ADSL Modem
+ 0802 ADSL Modem (RFC1483)
+ 0806 DSL Modem
+ 080f Binatone ADSL500 Modem Network Interface
+ 0812 Pirelli ADSL Modem Network Interface
+050a Cinch Connectors
+050b Cable System International
+050c InnoMedia, Inc.
+050d Belkin Components
+ 0004 Direct Connect
+ 0012 F8T012 Bluetooth Adapter
+ 0013 F8T013 Bluetooth Adapter
+ 0050 F5D6050 802.11b Wireless Adapter
+ 0081 F8T001v2 Bluetooth
+ 0083 Bluetooth Device
+ 0084 F8T003v2 Bluetooth
+ 0102 Flip KVM
+ 0103 F5U103 Serial Adapter [etek]
+ 0106 VideoBus II Adapter, Video
+ 0108 F1DE108B KVM
+ 0109 F5U109/F5U409 PDA Adapter
+ 0115 SCSI Adapter
+ 0119 F5U120-PC Dual PS/2 Ports
+ 0121 F5D5050 100Mbps Ethernet
+ 0122 Ethernet Adapter
+ 0131 Bluetooth Device with trace filter
+ 0201 Peripheral Switch
+ 0208 USBView II Video Adapter [nt1004]
+ 0210 F5U228 Hi-Speed USB 2.0 DVD Creator
+ 0211 F5U211 USB 2.0 15-in-1 Media Reader & Writer
+ 0224 F5U224 USB 2.0 4-Port Hub
+ 0234 F5U234 USB 2.0 4-Port Hub
+ 0237 F5U237 USB 2.0 7-Port Hub
+ 0240 F5U240 USB 2.0 CF Card Reader
+ 0257 F5U257 Serial
+ 0409 F5U409 Serial
+ 0551 F6C550-AVR UPS
+ 0802 Nostromo n40 Gamepad
+ 0803 Nostromo 1745 GamePad
+ 0805 Nostromo N50 GamePad
+ 0815 Nostromo n52 HID SpeedPad Mouse Wheel
+ 0826 ErgoFit Wireless Optical Mouse (HID)
+ 0980 HID UPS Battery
+ 1202 F5U120-PC Parallel Printer Port
+ 1203 F5U120-PC Serial Port
+ 258a F5U258 Host to Host cable
+ 3101 F1DF102U/F1DG102U Flip Hub
+ 3201 F1DF102U/F1DG102U Flip KVM
+ 4050 ZD1211B
+ 5055 F5D5055
+ 6051 11Mbps Wireless Network Adapter
+ 7050 F5D7050 ver 1000 WiFi
+ 7051 F5D7051 54g USB Network Adapter
+ 705a F5D7050A Wireless Adapter
+ 705b Wireless G Adapter
+ 705c F5D7050 v4000 Wireless Adapter
+ 905b F5D9050 ver 3 Wireless Adapter
+ 905c Wireless G Plus MIMO Network Adapter
+050e Neon Technology, Inc.
+050f KC Technology, Inc.
+ 0001 Hub
+ 0003 KC82C160S Hub
+ 0180 KC-180 IrDA Dongle
+ 0190 KC2190 USB Host-to-Host cable
+0510 Sejin Electron, Inc.
+ 0001 Keyboard
+ 1000 Keyboard with PS/2 Mouse Port
+ e001 Mouse
+0511 N'Able (DataBook) Technologies, Inc.
+0512 Hualon Microelectronics Corp.
+0513 digital-X, Inc.
+0514 FCI Electronics
+0515 ACTC
+0516 Longwell Electronics
+0517 Butterfly Communications
+0518 EzKEY Corp.
+ 0001 USB to PS2 Adaptor v1.09
+ 0002 EZ-9900C Keyboard
+0519 Star Micronics Co., Ltd
+ c002 Xlive Bluetooth XBM-100S MP3 Player
+051a WYSE Technology
+ a005 Smart Display Version 9973
+051b Silicon Graphics
+051c Shuttle, Inc.
+ c001 eHome Infrared Receiver
+ c002 eHome Infrared Receiver
+051d American Power Conversion
+ 0001 UPS
+ 0002 Uninterruptible Power Supply
+ 0003 UPS
+051e Scientific Atlanta, Inc.
+051f IO Systems (Elite Electronics), Inc.
+0520 Taiwan Semiconductor Manufacturing Co.
+0521 Airborn Connectors
+0522 Advanced Connectek, Inc.
+0523 ATEN GmbH
+0524 Sola Electronics
+0525 Netchip Technology, Inc.
+ 100d RFMD Bluetooth Device
+ 1080 NET1080 USB-USB Bridge
+ a140 USB Clik! 40
+ a141 (OME) PocketZip 40 MP3 Player Driver
+ a220 GVC Bluetooth Wireless Adapter
+ a4a0 Linux-USB "Gadget Zero"
+ a4a1 Linux-USB Ethernet Gadget
+ a4a2 Linux-USB Ethernet/RNDIS Gadget
+ a4a3 Linux-USB user-mode isochronous source/sink
+ a4a4 Linux-USB user-mode bulk source/sink
+ a4a5 Linux-USB File Storage Gadget
+ a4a6 Linux-USB Serial Gadget
+ a4a7 Linux-USB Serial Gadget (CDC ACM mode)
+ a4a8 Linux-USB Printer Gadget
+0526 Temic MHS S.A.
+0527 ALTRA
+0528 ATI Technologies, Inc.
+ 7561 TV Wonder
+ 7562 TV Wonder, Edition (FN5)
+ 7563 TV Wonder, Edition (FI)
+ 7564 TV Wonder, Edition (FQ)
+ 7565 TV Wonder, Edition (NTSC+)
+ 7566 TV Wonder, Edition (FN5)
+ 7567 TV Wonder, Edition (FI)
+ 7568 TV Wonder, Edition (FQ)
+ 7569 Live! Pro (A)
+ 756a Live! Pro Audio (O)
+0529 Aladdin Knowledge Systems
+ 0001 HASP v0.06
+ 030b eToken R1 v3.1.3.x
+ 0313 eToken R1 v3.2.3.x
+ 031b eToken R1 v3.3.3.x
+ 0323 eToken R1 v3.4.3.x
+ 0412 eToken R2 v2.2.4.x
+ 041a eToken R2 v2.2.4.x
+ 0422 eToken R2 v2.4.4.x
+ 042a eToken R2 v2.5.4.x
+ 050c eToken Pro v4.1.5.x
+ 0514 eToken Pro v4.2.5.4
+ 0600 eToken Pro 64k (4.2)
+052a Crescent Heart Software
+052b Tekom Technologies, Inc.
+ 0102 Ca508A HP1020 Camera v.1.3.1.6
+ 0801 Yakumo MegaImage 37
+ 1512 Yakumo MegaImage IV
+ 1513 Aosta CX100 WebCam
+ 1514 Aosta CX100 WebCam Storage
+ 1905 Yakumo MegaImage 47
+ 1911 Yakumo MegaImage 47 SL
+ 2202 WDM Still Image Capture
+ 2203 Sound Vision Stream Driver
+ 3a06 DigiLife DDV-5120A
+ d001 P35U Camera Capture
+052c Canon Information Systems, Inc.
+052d Avid Electronics Corp.
+052e Standard Microsystems Corp.
+052f Unicore Software, Inc.
+0530 American Microsystems, Inc.
+0531 Wacom Technology Corp.
+0532 Systech Corp.
+0533 Alcatel Mobile Phones
+0534 Motorola, Inc.
+0535 LIH TZU Electric Co., Ltd
+0536 Hand Held Products (Welch Allyn, Inc.)
+ 01a0 PDT
+0537 Inventec Corp.
+0538 Caldera International, Inc. (SCO)
+0539 Shyh Shiun Terminals Co., Ltd
+053a Preh Werke GmbH & Co. KG
+053b Global Village Communication
+053c Institut of Microelectronic & Mechatronic Systems
+053d Silicon Architect
+053e Mobility Electronics
+053f Synopsys, Inc.
+0540 UniAccess AB
+ 0101 Panache Surf ISDN TA
+0541 Sirf Technology, Inc.
+0543 ViewSonic Corp.
+ 00fe G773 Monitor Hub
+ 00ff P815 Monitor Hub
+ 0bf2 airpanel V150 Wireless Smart Display
+ 0bf3 airpanel V110 Wireless Smart Display
+ 0ed9 Color Pocket PC V35
+ 0f01 airsync Wi-Fi Wireless Adapter
+ 1527 Color Pocket PC V36
+ 1529 Color Pocket PC V37
+ 152b Color Pocket PC V38
+ 152e Pocket PC
+ 1921 Communicator Pocket PC
+ 1922 Smartphone
+ 1923 Pocket PC V30
+ 1a11 Wireless 802.11g Adapter
+ 1e60 TA310 - ATSC/NTSC/PAL Driver(PCM4)
+ 4153 ViewSonic G773 Control (?)
+0544 Cristie Electronics, Ltd
+0545 Xirlink, Inc.
+ 7333 Trution Web Camera
+ 8002 IBM NetCamera
+ 8009 Veo PC Camera
+ 800c Veo StingRay
+ 800d Veo PC Camera
+ 8080 IBM C-It WebCam
+ 808a Veo PC Camera
+ 808b Veo PC Camera
+ 808d Veo PC Camera
+ 810a Veo Advanced Connect WebCam
+ 810b Veo PC Camera
+ 810c Veo PC Camera
+ 8135 Veo Mobile/Advanced Web Camera
+ 813a Veo PC Camera
+ 813b Veo PC Camera
+ 813c Veo Mobile/Advanced Web Camera
+ 8333 Veo Stingray/Connect Web Camera
+ 888c eVision 123 digital camera
+ 888d eVision 123 digital camera
+0546 Polaroid Corp.
+ 0daf PDC 2300Z
+ 1bed PDC 1320 Camera
+ 3097 PDC 310
+ 3187 Digital Cam
+ dccf Sound Vision Stream Driver
+0547 Anchor Chips, Inc.
+ 0001 ICSI Bluetooth Device
+ 1002 Python2 WDM Encoder
+ 2131 AN2131 EZUSB Microcontroller
+ 2235 AN2235 EZUSB-FX Microcontroller
+ 2710 EZ-Link Loader (EZLNKLDR.SYS)
+ 2720 AN2720 USB-USB Bridge
+ 2727 Xircom PGUNET USB-USB Bridge
+ 2750 EZ-Link (EZLNKUSB.SYS)
+ 2810 Cypress USB ATAPI Bridge
+ 7777 Bluetooth Device
+ 9999 AN2131 uninitialized (?)
+0548 Tyan Computer Corp.
+ 1005 EZ Cart II GameBoy Flash Programmer
+0549 Pixera Corp.
+054a Fujitsu Microelectronics, Inc.
+054b New Media Corp.
+054c Sony Corp.
+ 0001 HUB
+ 0002 Standard HUB
+ 0010 DSC-S30/S70/S75/F505V/F505/FD92/W1 Cybershot/Mavica Digital Camera
+ 0014 Nogatech USBVision (SY)
+ 0022 Storage Adapter V2 (TPP)
+ 0023 CD Writer
+ 0024 Mavica CD-1000 Camera
+ 0025 NW-MS7 Walkman MemoryStick Reader
+ 002b Portable USB Harddrive V2
+ 002c USB Floppy Disk Drive
+ 002d MSAC-US1 MemoryStick Reader
+ 002e Sony HandyCam MemoryStick Reader
+ 0030 Storage Adapter V2 (TPP)
+ 0032 MemoryStick MSC-U01 Reader
+ 0035 Network Walkman (E)
+ 0036 Net MD
+ 0037 MG Memory Stick Reader/Writer
+ 0038 Clie PEG-S300/D PalmOS PDA
+ 0039 Network Walkman (MS)
+ 003c VAIO-MX LCD Control
+ 0045 Digital Imaging Video
+ 0046 Network Walkman
+ 004a Memory Stick Hi-Fi System
+ 004b Memory Stick Reader/Writer
+ 004e DSC-xxx (ptp)
+ 0056 MG Memory Stick Reader/Writer
+ 0058 Clie PEG-N7x0C PalmOS PDA Mass Storage
+ 0066 Clie PEG-N7x0C/PEG-T425 PalmOS PDA Serial
+ 0069 Memorystick MSC-U03 Reader
+ 006d Clie PEG-T425 PDA Mass Storage
+ 006f Network Walkman (EV)
+ 0073 Storage CRX1750U
+ 0075 Net MD
+ 0076 Storage Adapter ACR-U20
+ 007c Net MD
+ 007f IC Recorder (MS)
+ 0080 Net MD
+ 0081 Net MD
+ 0084 Net MD
+ 0085 Net MD
+ 0086 Net MD
+ 008b Micro Vault 64M Mass Storage
+ 0095 Sony Clie s360
+ 0099 Clie NR70 PDA Mass Storage
+ 009a Clie NR70 PDA Serial
+ 00ab Visual Communication Camera (PCGA-UVC10)
+ 00af DPP-EX Series Digital Photo Printer
+ 00bf IC Recorder (S)
+ 00c0 Handycam DCR-30
+ 00c6 Net MD
+ 00c7 Net MD
+ 00c8 MZ-N710 Minidisc Walkman
+ 00c9 Net MD
+ 00ca MZ-DN430 Minidisc Walkman
+ 00cb MSAC-US20 Memory Stick Reader
+ 00da Sony Clie nx60
+ 00e8 Network Walkman (MS)
+ 00e9 Handheld
+ 00eb Net MD
+ 0101 Net MD
+ 0103 IC Recorder (ST)
+ 0105 Micro Vault Hub
+ 0107 VCC-U01 Visual Communication Camera
+ 0110 Digital Imaging Video
+ 0113 Net MD
+ 0116 IC Recorder (P)
+ 0144 Clie PEG-TH55 PDA
+ 0147 Visual Communication Camera (PCGA-UVC11)
+ 014c Aiwa AM-NX9 Net MD Music Recorder MDLP
+ 014d Memory Stick Reader/Writer
+ 0154 Eyetoy Audio Device
+ 015f IC Recorder (BM)
+ 0169 Clie PEG-TJ35 PDA Serial
+ 016a Clie PEG-TJ35 PDA Mass Storage
+ 016b Mobile HDD
+ 016d IC Recorder (SX)
+ 016e DPP-EX50 Digital Photo Printer
+ 0171 Fingerprint Sensor 3500
+ 017e Net MD
+ 017f Hi-MD WALKMAN
+ 0180 Net MD
+ 0181 Hi-MD WALKMAN
+ 0182 Net MD
+ 0183 Hi-MD WALKMAN
+ 0184 Net MD
+ 0185 Hi-MD WALKMAN
+ 0186 Net MD
+ 0187 Hi-MD WALKMAN
+ 0188 Net MD
+ 018a Net MD
+ 018b Hi-MD SOUND GATE
+ 019e Micro Vault 1.0G Mass Storage
+ 01ad ATRAC HDD PA
+ 01bd MRW62E Multi-Card Reader/Writer
+ 01c3 NW-E55 Network Walkman
+ 01c6 MEMORY P-AUDIO
+ 01c7 Printing Support
+ 01d0 DVD+RW External Drive DRU-700A
+ 01d5 IC RECORDER
+ 01de VRD-VC10 [Video Capture]
+ 01e9 Net MD
+ 01ea Hi-MD WALKMAN
+ 01ee IC RECORDER
+ 01fa Sony IC Recorder (P)
+ 01fb NW-E405 Network Walkman
+ 020f Device
+ 0210 ATRAC HDD PA
+ 0219 Net MD
+ 021a Hi-MD WALKMAN
+ 021b Net MD
+ 021c Hi-MD WALKMAN
+ 021d Net MD
+ 0227 Printing Support
+ 022c Net MD
+ 022d Hi-MD AUDIO
+ 0233 ATRAC HDD PA
+ 0236 Mobile HDD
+ 023b DVD+RW External Drive DRU-800UL
+ 023c Net MD
+ 023d Hi-MD WALKMAN
+ 0243 MicroVault Flash Drive
+ 0257 IFU-WLM2 USB Wireless LAN Module (Wireless Mode)
+ 0258 IFU-WLM2 USB Wireless LAN Module (Memory Mode)
+ 0259 IC RECORDER
+ 0267 Tachikoma Device
+ 0268 Batoh Device
+ 0269 HDD WALKMAN
+ 026a HDD WALKMAN
+ 0271 IC Recorder (P)
+ 027c NETWORK WALKMAN
+ 027e SONY Communicator
+ 027f IC RECORDER
+ 0286 Net MD
+ 0287 Hi-MD WALKMAN
+ 029b PRS-500 eBook reader
+ 02ae PlayStation 3 Memory Card Adaptor
+ 02af Handycam DCR-DVD306E
+ 02c4 Device
+ 02d2 PSP
+054d Try Corp.
+054e Proside Corp.
+054f WYSE Technology Taiwan
+0550 Fuji Xerox Co., Ltd
+ 0002 InkJet Color Printer
+ 0004 InkJet Color Printer
+ 0005 InkJet Color Printer
+0551 CompuTrend Systems, Inc.
+0552 Philips Monitors
+0553 STMicroelectronics Imaging Division (VLSI Vision)
+ 0001 TerraCAM
+ 0002 CPiA WebCam
+ 0100 STV0672 Camera
+ 0140 Video Camera
+ 0150 CDE CAM 100
+ 0151 Digital Blue QX5 Microscope
+ 0200 Dual-mode Camera0
+ 0201 Dual-mode Camera1
+ 0202 Aiptek PenCam 1
+ 0674 Multi-mode Camera
+ 0679 NMS Video Camera (Webcam)
+ 1002 Che-ez! Splash
+0554 Dictaphone Corp.
+0555 ANAM S&T Co., Ltd
+0556 Asahi Kasei Microsystems Co., Ltd
+ 0001 AK5370 I/F A/D Converter
+0557 ATEN International Co., Ltd
+ 2001 UC-1284 Printer Port
+ 2002 10Mbps Ethernet [klsi]
+ 2004 UC-100KM PS/2 Mouse and Keyboard adapter
+ 2006 UC-1284B Printer Port
+ 2007 UC-110T 100Mbps Ethernet [pegasus]
+ 2008 UC-232A Serial Port [pl2303]
+ 2009 UC-210T Ethernet
+ 2202 CS124U Miniview II KVM Switch
+ 2600 IDE Bridge
+ 4000 DSB-650 10Mbps Ethernet [klsi]
+ 7000 Hub
+0558 Truevision, Inc.
+0559 Cadence Design Systems, Inc.
+055a Kenwood USA
+055b KnowledgeTek, Inc.
+055c Proton Electronic Ind.
+055d Samsung Electro-Mechanics Co.
+ 0001 Keyboard
+ 0bb1 Bluetooth Device
+ 1030 Optical Wheel Mouse (OMS3CB/OMGB30)
+ 1031 Optical Wheel Mouse (OMA3CB/OMGI30)
+ 1040 Mouse HID Device
+ 1050 E-Mail Optical Wheel Mouse (OMS3CE)
+ 1080 Optical Wheel Mouse (OMS3CH)
+ 2020 Floppy Disk Drive
+ 6780 Keyboard V1
+ 6781 Keyboard Mouse
+ 8001 E.M. Hub
+ 9000 AnyCam [pwc]
+ 9001 MPC-C30 AnyCam Premium for Notebooks [pwc]
+ a010 WLAN Adapter(SWL-2300)
+ a011 Boot Device
+ a012 WLAN Adapter(SWL-2300)
+ a013 WLAN Adapter(SWL-2350)
+ a230 Boot Device
+ b000 11Mbps WLAN Mini Adapter
+ b230 Netopia 802.11b WLAN Adapter
+ b231 LG Wireless LAN 11b Adapter
+055e CTX Opto-Electronics Corp.
+055f Mustek Systems, Inc.
+ 0001 ScanExpress 1200 CU
+ 0002 ScanExpress 600 CU
+ 0003 ScanExpress 1200 USB
+ 0006 ScanExpress 1200 UB
+ 0007 ScanExpress 1200 USB Plus
+ 0008 ScanExpress 1200 CU Plus
+ 0010 BearPaw 1200F
+ 0210 ScanExpress A3 USB
+ 0218 BearPaw 2400 TA
+ 0219 BearPaw 2400 TA Plus
+ 021a BearPaw 2448 TA Plus
+ 021c BearPaw 1200 CU Plus
+ 021d BearPaw 2400 CU Plus
+ 021e BearPaw 1200 TA/CS
+ 021f SNAPSCAN e22
+ 0400 BearPaw 2400 TA Pro
+ 0401 P 3600 A3 Pro
+ 0408 BearPaw 2448 CU Pro
+ 0873 ScanExpress 600 USB
+ 1000 BearPaw 4800 TA Pro
+ a350 gSmart 350
+ a800 MDC 800 Camera
+ b500 MDC 3000 Camera
+ c005 PC CAM 300A
+ c200 gSmart 300
+ c220 gSmart mini
+ c360 Mustek DV 4000
+ c420 gSmart mini 2
+ c440 Mustek DV 3000
+ c520 gSmart mini 3
+ c530 Mustek Gsmart LCD 2
+ c631 MDC-4000
+ c650 Mustek MDC5500Z
+ d001 WCam 300
+ d003 PC CAM 300A
+ d004 PC CAM 300A
+0560 Interface Corp.
+0561 Oasis Design, Inc.
+0562 Telex Communications, Inc.
+ 0001 Enhanced Microphone
+ 0002 Telex Microphone
+0563 Immersion Corp.
+0564 Chinon Industries, Inc.
+0565 Peracom Networks, Inc.
+ 0001 Serial Port [etek]
+ 0002 Enet Ethernet [klsi]
+ 0003 @Home Networks Ethernet [klsi]
+ 0005 Enet2 Ethernet [klsi]
+ 0041 Peracom Remote NDIS Ethernet Adapter
+0566 Monterey International Corp.
+ 0110 ViewMate Desktop Mouse CC2201
+ 1001 ViewMate Desktop Mouse CC2201
+ 1002 ViewMate Desktop Mouse CC2201
+ 1003 ViewMate Desktop Mouse CC2201
+ 1004 ViewMate Desktop Mouse CC2201
+ 1005 ViewMate Desktop Mouse CC2201
+ 1006 ViewMate Desktop Mouse CC2201
+ 1007 ViewMate Desktop Mouse CC2201
+ 2800 MIC K/B
+ 2801 MIC K/B Mouse
+ 2802 Kbd Hub
+0567 Xyratex International, Ltd
+0568 Quartz Ingenierie
+0569 SegaSoft
+056a Wacom Co., Ltd
+ 0000 PenPartner
+ 0001 PenPartner 4x5
+ 0002 PenPartner 6x8
+ 0010 Graphire
+ 0011 Graphire 2
+ 0013 Graphire 3 4x5
+ 0020 Intuos 4x5
+ 0021 Intuos 6x8
+ 0022 Intuos 9x12
+ 0023 Intuos 12x12
+ 0024 Intuos 12x18
+ 0030 PL400
+ 0031 PL500
+ 0032 PL600
+ 0034 PL550
+ 0035 PL800
+ 0041 Intuos2 4x5
+ 0042 Intuos 2 6x8
+ 0043 Intuos 2
+ 0044 Intuos2 12x12
+ 0045 Intuos2 12x18
+ 0400 PenPartner 4x5
+ 4850 PenPartner 6x8
+056b Decicon, Inc.
+056c eTEK Labs
+ 0006 KwikLink Host-Host Connector
+ 8007 Kwik232 Serial Port
+ 8100 KwikLink Host-Host Connector
+ 8101 KwikLink USB-USB Bridge
+056d EIZO Corp.
+ 0000 Hub
+ 0001 Monitor
+ 0002 HID Monitor Controls
+ 0003 Device Bay Controller
+056e Elecom Co., Ltd
+ 0002 29UO Mouse
+ 200c LD-USB/TX
+ 4002 Laneed 100Mbps Ethernet LD-USB/TX [pegasus]
+ 4005 LD-USBL/TX
+ 400b LD-USB/TX
+ 4010 LD-USB20
+ 5003 UC-SGT
+ 5004 UC-SGT
+ abc1 LD-USB/TX
+056f Korea Data Systems Co., Ltd
+ cd00 CDM-751 CD organizer
+0570 Epson America
+0571 Interex, Inc.
+ 0002 echoFX InterView Lite
+0572 Conexant Systems (Rockwell), Inc.
+ 0001 Ezcam II WebCam
+ 0002 Ezcam II WebCam
+ 0040 Wondereye CP-115 WebCam
+ 0041 WebCam Notebook
+ 0042 WebCam Notebook
+ 1232 V.90 modem
+ 1234 Typhoon Redfun Modem V90 56k
+ 1252 HCF V90 Data Fax Voice Modem
+ 1253 Zoom V.92 Faxmodem
+ 1300 SoftK56 Data Fax Voice CARP
+ 1301 Modem Enumerator
+ 2000 SoftGate 802.11 Adapter
+ 2002 SoftGate 802.11 Adapter
+ 8390 WinFast PalmTop/Novo TV Video
+ 8392 WinFast PalmTop/Novo TV Video
+ cafe AccessRunner ADSL Modem
+ cb00 E-Tech ADSL Modem v2
+ cb01 GeekADSL Promax Q31 ADSL Modem
+ cb06 StarModem Network Interface
+0573 Zoran Co. Personal Media Division (Nogatech)
+ 0003 USBGear USBG-V1
+ 0400 D-Link V100
+ 0600 Dazzle USBVision (1006)
+ 1300 leadtek USBVision (1006)
+ 2000 X10 va10a Wireless Camera
+ 2001 Dazzle EmMe (2001)
+ 2101 Zoran Co. PMD (Nogatech) AV-grabber Manhattan
+ 2d00 Osprey 50
+ 2d01 Hauppauge USB-Live Model 600
+ 3000 Dazzle MicroCam (NTSC)
+ 3001 Dazzle MicroCam (PAL)
+ 4000 Nogatech TV! (NTSC)
+ 4001 Nogatech TV! (PAL)
+ 4002 Nogatech TV! (PAL-I-)
+ 4003 Nogatech TV! (MF-)
+ 4008 Nogatech TV! (NTSC) (T)
+ 4009 Nogatech TV! (PAL) (T)
+ 4010 Nogatech TV! (NTSC) (A)
+ 4100 USB-TV FM (NTSC)
+ 4110 PNY USB-TV (NTSC) FM
+ 4400 Nogatech TV! Pro (NTSC)
+ 4401 Nogatech TV! Pro (PAL)
+ 4450 PixelView PlayTv-USB PRO (PAL) FM
+ 4451 Nogatech TV! Pro (PAL+)
+ 4452 Nogatech TV! Pro (PAL-I+)
+ 4500 Nogatech TV! Pro (NTSC)
+ 4501 Nogatech TV! Pro (PAL)
+ 4550 ZTV ZT-721 2.4GHz USB A/V Receiver
+ 4551 Dazzle TV! Pro Audio (P+)
+ 4d00 Hauppauge WinTV-USB USA
+ 4d01 Hauppauge WinTV-USB
+ 4d02 Hauppauge WinTV-USB UK
+ 4d03 Hauppauge WinTV-USB France
+ 4d04 Hauppauge WinTV (PAL D/K)
+ 4d10 Hauppauge WinTV-USB with FM USA radio
+ 4d11 Hauppauge WinTV-USB (PAL) with FM radio
+ 4d12 Hauppauge WinTV-USB UK with FM Radio
+ 4d14 Hauppauge WinTV (PAL D/K FM)
+ 4d20 Hauppauge WinTV-USB II (PAL) with FM radio
+ 4d21 Hauppauge WinTV-USB II (PAL)
+ 4d22 Hauppauge WinTV-USB II (PAL) Model 566
+ 4d23 Hauppauge WinTV-USB France 4D23
+ 4d24 Hauppauge WinTV Pro (PAL D/K)
+ 4d25 Hauppauge WinTV-USB Model 40209 rev B234
+ 4d26 Hauppauge WinTV-USB Model 40209 rev B243
+ 4d27 Hauppauge WinTV-USB Model 40204 Rev B281
+ 4d28 Hauppauge WinTV-USB Model 40204 rev B283
+ 4d29 Hauppauge WinTV-USB Model 40205 rev B298
+ 4d2a Hauppague WinTV-USB Model 602 Rev B285
+ 4d2b Hauppague WinTV-USB Model 602 Rev B282
+ 4d2c Hauppauge WinTV Pro (PAL/SECAM)
+ 4d30 Hauppauge WinTV-USB FM Model 40211 Rev B123
+ 4d31 Hauppauge WinTV-USB III (PAL) with FM radio Model 568
+ 4d32 Hauppauge WinTV-USB III (PAL) FM Model 573
+ 4d34 Hauppauge WinTV Pro (PAL D/K FM)
+ 4d35 Hauppauge WinTV-USB III (PAL) FM Model 597
+ 4d36 Hauppauge WinTV Pro (PAL B/G FM)
+ 4d37 Hauppauge WinTV-USB Model 40219 rev E189
+ 4d38 Hauppauge WinTV Pro (NTSC FM)
+0574 City University of Hong Kong
+0575 Philips Creative Display Solutions
+0576 BAFO/Quality Computer Accessories
+0577 ELSA
+0578 Intrinsix Corp.
+0579 GVC Corp.
+057a Samsung Electronics America
+057b Y-E Data, Inc.
+ 0000 FlashBuster-U Floppy
+ 0001 Tri-Media Reader Floppy
+ 0006 Tri-Media Reader Card Reader
+ 0010 Memory Stick Reader Writer
+ 0020 HEXA Media Drive 6-in-1 Card Reader Writer
+ 0030 Memory Card Viewer (TV)
+057c AVM GmbH
+ 0b00 ISDN-Controller B1 Family
+ 0c00 ISDN-Controller FRITZ!Card
+ 1000 ISDN-Controller FRITZ!Card v2.0
+ 1900 ISDN-Controller FRITZ!Card v2.1
+ 2000 ISDN-Connector FRITZ!X
+ 2200 BlueFRITZ!
+ 2300 Teledat X130 DSL
+ 2800 ISDN-Connector TA
+ 3200 Teledat X130 DSL
+ 3500 FRITZ!Card DSL SL
+ 3701 FRITZ!Box SL
+ 3702 FRITZ!Box
+ 3800 BlueFRITZ! Bluetooth Stick
+ 3a00 FRITZ!Box Fon
+ 3c00 FRITZ!Box WLAN
+ 3d00 Fritz!Box
+ 3e01 FRITZ!Box (Annex A)
+ 4001 FRITZ!Box Fon (Annex A)
+ 4101 FRITZ!Box WLAN (Annex A)
+ 4201 FRITZ!Box Fon WLAN (Annex A)
+ 4601 Eumex 5520PC (WinXP/2000)
+ 4602 Eumex 400 (WinXP/2000)
+ 4701 AVM FRITZ!Box Fon ata
+ 5401 Eumex 300 IP
+ 5601 AVM FRITZ!WLAN Stick
+ 6201 WLAN USB v1.1
+ 62ff WLAN USB v1.1 [no firmware]
+057d Shark Multimedia, Inc.
+057e Nintendo Co., Ltd
+ 0306 Wii Remote Controller RVL-003
+057f QuickShot, Ltd
+ 6238 USB StrikePad
+0580 Denron, Inc.
+0581 Racal Data Group
+0582 Roland Corp.
+ 0000 UA-100
+ 0002 UM-4/MPU-64 MIDI Interface
+ 0003 SoundCanvas SC-8850
+ 0004 U-8
+ 0005 Edirol UM-2 MIDI Adapter
+ 0007 SoundCanvas SC-8820
+ 0008 PC-300
+ 0009 Edirol UM-1SX MIDI Adapter
+ 000b SK-500
+ 000c SC-D70
+ 0010 EDIROL UA-5
+ 0011 Edirol UA-5 Sound Capture
+ 0012 XV-5050
+ 0013 XV-5050
+ 0014 EDIROL UM-880 MIDI I/F (native)
+ 0015 EDIROL UM-880 MIDI I/F (generic)
+ 0016 EDIROL SD-90
+ 0017 EDIROL SD-90
+ 001b MMP-2
+ 001c MMP-2
+ 001d V-SYNTH
+ 001e V-SYNTH
+ 0023 EDIROL UM-550
+ 0024 EDIROL UM-550
+ 0025 EDIROL UA-20
+ 0026 EDIROL UA-20
+ 0027 EDIROL SD-20
+ 0028 EDIROL SD-20
+ 0029 EDIROL SD-80
+ 002a EDIROL SD-80
+ 002b EDIROL UA-700
+ 002c EDIROL UA-700
+ 002d XV-2020 Synthesizer
+ 002e XV-2020 Synthesizer
+ 002f VariOS
+ 0030 VariOS
+ 0033 EDIROL PCR
+ 0034 EDIROL PCR
+ 0037 Digital Piano
+ 0038 Digital Piano
+ 003b BOSS GS-10
+ 003c BOSS GS-10
+ 0040 GI-20
+ 0041 GI-20
+ 0042 RS-70
+ 0043 RS-70
+ 0044 EDIROL UA-1000
+ 0047 EDIROL UR-80 WAVE
+ 0048 EDIROL UR-80 MIDI
+ 0049 EDIROL UR-80 WAVE
+ 004a EDIROL UR-80 MIDI
+ 004b EDIROL M-100FX
+ 004c EDIROL PCR-A WAVE
+ 004d EDIROL PCR-A MIDI
+ 004e EDIROL PCR-A WAVE
+ 004f EDIROL PCR-A MIDI
+ 0050 EDIROL UA-3FX
+ 0052 EDIROL UM-1SX
+ 0054 Digital Piano
+ 0060 EXR Series
+ 0064 EDIROL PCR-1 WAVE
+ 0065 EDIROL PCR-1 MIDI
+ 0066 EDIROL PCR-1 WAVE
+ 0067 EDIROL PCR-1 MIDI
+ 006a SP-606
+ 006b SP-606
+ 006d FANTOM-X
+ 006e FANTOM-X
+ 0073 EDIROL UA-25
+ 0074 EDIROL UA-25
+ 0075 BOSS DR-880
+ 0076 BOSS DR-880
+ 007a RD
+ 007b RD
+ 007d EDIROL UA-101
+ 0080 G-70
+ 0081 G-70
+ 008b EDIROL PC-50
+ 008c EDIROL PC-50
+ 008d EDIROL UA-101 USB1
+ 0092 EDIROL PC-80 WAVE
+ 0093 EDIROL PC-80 MIDI
+ 0096 EDIROL UA-1EX
+ 009a EDIROL UM-3EX
+ 009d EDIROL UM-1
+ 00a2 Digital Piano
+ 00a3 EDIROL UA-4FX
+ 00a6 Juno-G
+ 00ad SH-201
+ 00c4 EDIROL M-16DX
+0583 Padix Co., Ltd (Rockfire)
+ 2030 RM-203 USB Nest [mode 1]
+ 2031 RM-203 USB Nest [mode 2]
+ 2032 RM-203 USB Nest [mode 3]
+ 2033 RM-203 USB Nest [mode 4]
+ 2050 PX-205 PSX Bridge
+ 3050 QF-305u Gamepad
+ 688f QF-688uv Windstorm Pro Joystick
+ 7070 QF-707u Bazooka Joystick
+0584 RATOC System, Inc.
+ 0008 Fujifilm MemoryCard ReaderWriter
+ b000 REX-USB60
+0585 FlashPoint Technology, Inc.
+ 0001 Digital Camera
+ 0002 Digital Camera
+ 0003 Digital Camera
+ 0004 Digital Camera
+ 0005 Digital Camera
+ 0006 Digital Camera
+ 0007 Digital Camera
+ 0008 Digital Camera
+ 0009 Digital Camera
+ 000a Digital Camera
+ 000b Digital Camera
+ 000c Digital Camera
+ 000d Digital Camera
+ 000e Digital Camera
+ 000f Digital Camera
+0586 ZyXEL Communications Corp.
+ 1000 Omni NET Modem / ISDN TA
+ 1500 Omni 56K Plus
+ 2011 Scorpion-980N keyboard
+ 3304 LAN Modem
+ 330a ADSL Modem Interface
+ 330e USB Broadband ADSL Modem Rev 1.10
+ 3400 ZyAIR B-220 IEEE 802.11b Adapter
+ 3401 ZyAIR G-220
+ 3402 (ZD1211)IEEE 802.11b+g Adapter
+ 3407 G-200 v2
+ 3409 AG-225H
+ 340a M-202
+ 340f G-220 v2
+ 3410 Wi-Fi Wireless LAN Adapter
+ 3412 Wi-Fi Wireless LAN Adapter
+ 3413 AG-225H v2 802.11a/g Wi-Fi Finder & Adapter
+ 3415 G-210H 802.11g Wireless Adapter
+0587 America Kotobuki Electronics Industries, Inc.
+0588 Sapien Design
+0589 Victron
+058a Nohau Corp.
+058b Infineon Technologies
+058c In Focus Systems
+ 0007 Flash
+ 0008 LP130
+ 000a LP530
+ 0010 Projector
+ 0011 Projector
+ 0012 Projector
+ 0013 Projector
+ 0014 Projector
+ 0015 Projector
+ 0016 Projector
+ 0017 Projector
+ 0018 Projector
+ 0019 Projector
+ 001a Projector
+ 001b Projector
+ 001c Projector
+ 001d Projector
+ 001e Projector
+ 001f Projector
+058d Micrel Semiconductor
+058e Tripath Technology, Inc.
+058f Alcor Micro Corp.
+ 2412 SCard R/W CSR-145
+ 2802 Monterey Keyboard
+ 5492 Hub
+ 6232 Hi-Speed 16-in-1 Flash Card Reader/Writer
+ 6360 Multimedia Card Reader
+ 6361 Multimedia Card Reader
+ 6362 Hi-Speed 21-in-1 Flash Card Reader/Writer (Internal/External)
+ 6377 Multimedia Card Reader
+ 6386 Memory Card
+ 6387 Transcend JetFlash Flash Drive
+ 6390 USB 2.0-IDE bridge
+ 9213 MacAlly Kbd Hub
+ 9215 AU9814 Hub
+ 9254 Hub
+ 9310 Mass Storage (UID4/5A & UID7A)
+ 9320 Micro Storage Driver for Win98
+ 9321 Micro Storage Driver for Win98
+ 9330 SD Reader
+ 9331 Micro Storage Driver for Win98
+ 9340 Delkin eFilm Reader-32
+ 9350 Delkin eFilm Reader-32
+ 9360 8-in-1 Media Card Reader
+ 9361 Multimedia Card Reader
+ 9368 Multimedia Card Reader
+ 9380 Flash drive
+ 9382 Acer/Sweex Flash drive
+ 9410 Keyboard
+ 9472 Keyboard Hub
+ 9510 ChunghwaTL USB02 Smartcard Reader
+ 9520 EMV Certified Smart Card Reader
+ 9720 USB-Serial Adapter
+0590 Omron Corp.
+ 0004 Cable Modem
+ 000b MR56SVS
+ 0028 HJ-720IT Pedometer
+0591 Questra Consulting
+0592 Powerware Corp.
+ 0002 UPS (X-Slot)
+0593 Incite
+0594 Princeton Graphic Systems
+0595 Zoran Microelectronics, Ltd
+ 1001 Digitrex DSC-1300/DSC-2100 (mass storage mode)
+ 4343 Digital Camera EX-20 DSC
+0596 MicroTouch Systems, Inc.
+ 0001 Touchscreen
+ 0002 Touch Screen Controller
+0597 Trisignal Communications
+0598 Niigata Canotec Co., Inc.
+0599 Brilliance Semiconductor, Inc.
+059a Spectrum Signal Processing, Inc.
+059b Iomega Corp.
+ 0001 Zip 100 (Type 1)
+ 000b Zip 100 (Type 2)
+ 0021 Win98 Disk Controller
+ 0030 Zip 250 (Ver 1)
+ 0031 Zip 100 (Type 3)
+ 0032 Zip 250 (Ver 2)
+ 0034 Zip 100 Driver
+ 0037 Zip 750 MB
+ 0040 SCSI Bridge
+ 0042 Rev 70 GB
+ 0050 Zip CD 650 Writer
+ 0053 CDRW55292EXT CD-RW External Drive
+ 0057 Mass Storage Device
+ 005d Mass Storage Device
+ 005f Mass Storage Device
+ 0060 PCMCIA PocketZip Dock
+ 0061 Varo PocketZip 40 MP3 Player
+ 006d HipZip MP3 Player
+ 007c Ultra Max USB/1394
+ 00db FotoShow Zip 250 Driver
+ 0150 Mass Storage Device
+ 015d Super DVD Writer
+ 0173 Hi-Speed USB-to-IDE Bridge Controller
+ 0174 Hi-Speed USB-to-IDE Bridge Controller
+ 0176 Hi-Speed USB-to-IDE Bridge Controller
+ 0177 Hi-Speed USB-to-IDE Bridge Controller
+ 0178 Hi-Speed USB-to-IDE Bridge Controller
+ 0179 Hi-Speed USB-to-IDE Bridge Controller
+ 017a HDD
+ 017b HDD/1394A
+ 017c HDD/1394B
+ 0251 Optical
+ 0252 Optical
+ 1052 DVD+RW External Drive
+059c A-Trend Technology Co., Ltd
+059d Advanced Input Devices
+059e Intelligent Instrumentation
+059f LaCie, Ltd
+ 0201 StudioDrive USB2
+ 0202 StudioDrive USB2
+ 0203 StudioDrive USB2
+ 0211 PocketDrive
+ 0212 PocketDrive
+ 0213 PocketDrive USB2
+ 0323 LaCie d2 Drive USB2
+ 0641 Mobile Hard Drive
+ 1010 Desktop Hard Drive
+ a601 HardDrive
+ a602 CD R/W
+05a0 Vetronix Corp.
+05a1 USC Corp.
+05a2 Fuji Film Microdevices Co., Ltd
+05a3 ARC International
+05a4 Ortek Technology, Inc.
+ 9720 Keyboard Mouse
+ 9722 Keyboard
+ 9731 MCK-600W/MCK-800USB Keyboard
+05a5 Sampo Technology Corp.
+05a6 Cisco Systems, Inc.
+ 0001 CVA124 Cable Voice Adapter (WDM)
+ 0002 CVA122 Cable Voice Adapter (WDM)
+ 0003 CVA124E Cable Voice Adapter (WDM)
+ 0004 CVA122E Cable Voice Adapter (WDM)
+05a7 Bose Corp.
+05a8 Spacetec IMC Corp.
+05a9 OmniVision Technologies, Inc.
+ 0511 OV511 WebCam
+ 0518 OV518 WebCam
+ 0519 OV519 Microphone
+ 1550 VEHO Filmscanner
+ 2800 SuperCAM
+ 4519 Webcam Classic
+ 8519 OV519 WebCam
+ a511 OV511+ WebCam
+ a518 D-Link DSB-C310 WebCam
+05aa Utilux South China, Ltd
+05ab In-System Design
+ 0002 Parallel Port
+ 0030 Storage Adapter V2 (TPP)
+ 0031 ATA Bridge
+ 0060 USB 2.0 ATA Bridge
+ 0061 Storage Adapter V3 (TPP-I)
+ 0101 Storage Adapter (TPP)
+ 0130 Compact Flash and Microdrive Reader (TPP)
+ 0200 USS725 ATA Bridge
+ 0201 Storage Adapter (TPP)
+ 0202 ATA Bridge
+ 0300 Portable Hard Drive (TPP)
+ 0301 Portable Hard Drive V2
+ 0350 Portable Hard Drive (TPP)
+ 0351 Portable Hard Drive V2
+ 081a ATA Bridge
+ 0cda ATA Bridge for CD-R/RW
+ 1001 BAYI Printer Class Support
+ 5700 Storage Adapter V2 (TPP)
+ 5701 USB Storage Adapter V2
+ 5901 Smart Board (TPP)
+ 5a01 ATI Storage Adapter (TPP)
+ 5d01 DataBook Adapter (TPP)
+05ac Apple, Inc.
+ 0201 USB Keyboard [Alps or Logitech, M2452]
+ 0202 Keyboard [ALPS]
+ 0205 Extended Keyboard [Mitsumi]
+ 0206 Extended Keyboard [Mitsumi]
+ 020b Pro Keyboard [Mitsumi, A1048/US layout]
+ 020c Extended Keyboard [Mitsumi]
+ 020d Pro Keyboard [Mitsumi, A1048/JIS layout]
+ 020e Internal Keyboard/Trackpad
+ 020f Internal Keyboard/Trackpad
+ 021b Internal Keyboard/Trackpad
+ 0220 Aluminum Keyboard
+ 0221 Keyboard (Aluminium) (ISO)
+ 0229 Internal Keyboard/Trackpad (MacBook Pro) (ANSI)
+ 022a Internal Keyboard/Trackpad (MacBook Pro) (ISO)
+ 022b Internal Keyboard/Trackpad (MacBook Pro) (JIS)
+ 0301 USB Mouse [Mitsumi, M4848]
+ 0302 Optical Mouse [Fujitsu]
+ 0304 Optical USB Mouse [Mitsumi]
+ 0306 Optical USB Mouse [Fujitsu]
+ 1000 Bluetooth HCI MacBookPro (HID mode)
+ 1001 Keyboard Hub [ALPS]
+ 1002 Extended Keyboard Hub [Mitsumi]
+ 1003 Hub in Pro Keyboard [Mitsumi, A1048]
+ 1006 Hub in Aluminum Keyboard
+ 1101 Speakers
+ 1201 3G iPod
+ 1202 iPod 2G
+ 1203 iPod 4.Gen Grayscale 40G
+ 1204 iPod [Photo]
+ 1205 iPod Mini 1.Gen/2.Gen
+ 1206 iPod '06'
+ 1207 iPod '07'
+ 1208 iPod '08'
+ 1209 iPod Video
+ 120a iPod Nano
+ 1260 iPod Nano 2.Gen
+ 1261 iPod Classic
+ 1300 iPod Shuffle
+ 1301 iPod Shuffle 2.Gen
+ 8202 HCF V.90 Data/Fax Modem
+ 8203 Bluetooth HCI
+ 8204 Bluetooth HCI [Bluetooth 2.0 + EDR, build-in]
+ 8205 Bluetooth HCI MacBookPro
+ 8206 Bluetooth USB Host Controller
+ 8240 IR Receiver [build-in]
+ 8300 Built-in iSight (no firmware loaded)
+ 8501 Built-in iSight [Micron]
+ 912f Hub in 30" Cinema Display
+ 9221 30" Cinema Display
+ ffff Bluetooth in DFU mode - Driver
+05ad Y.C. Cable U.S.A., Inc.
+05ae Synopsys, Inc.
+05af Jing-Mold Enterprise Co., Ltd
+ 0821 IDE to
+ 9167 KB 9151B - 678
+ 9267 KB 9251B - 678 Mouse
+05b0 Fountain Technologies, Inc.
+05b1 First International Computer, Inc.
+ 1389 Bluetooth Wireless Adapter
+05b4 LG Semicon Co., Ltd
+ 4857 M-Any DAH-210
+ 6001 Digisette DUO-MP3 AR-100
+05b5 Dialogic Corp.
+05b6 Proxima Corp.
+05b7 Medianix Semiconductor, Inc.
+05b8 Agiler, Inc.
+ 3002 Scroll Mouse
+05b9 Philips Research Laboratories
+05ba DigitalPersona, Inc.
+05bb Grey Cell Systems
+05bc 3G Green Green Globe Co., Ltd
+ 0004 Trackball
+05bd RAFI GmbH & Co. KG
+05be Tyco Electronics (Raychem)
+05bf S & S Research
+05c0 Keil Software
+05c1 Kawasaki Microelectronics, Inc.
+05c2 Media Phonics (Suisse) S.A.
+05c5 Digi International, Inc.
+ 0002 AccelePort USB 2
+ 0004 AccelePort USB 4
+ 0008 AccelePort USB 8
+05c6 Qualcomm, Inc.
+ 3100 CDMA Wireless Modem/Phone
+ 3196 CDMA Wireless Modem
+ 3197 CDMA Wireless Modem/Phone
+05c7 Qtronix Corp.
+ 0113 PC Line Mouse
+ 1001 Lynx Mouse
+ 2001 Keyboard
+ 2011 SCorpius Keyboard
+ 6001 Ten-Keypad
+05c8 Cheng Uei Precision Industry Co., Ltd (Foxlink)
+05c9 Semtech Corp.
+05ca Ricoh Co., Ltd
+ 0101 RDC-5300 Camera
+ 0325 Caplio GX (ptp)
+ 032d Caplio GX 8 (ptp)
+ 032f Caplio R3 (ptp)
+ 03a1 IS200e
+ 0403 Printing Support
+ 0405 Type 101
+ 0406 Type 102
+ 1830 Visual Communication Camera VGP-VCC2
+ 1835 Visual Communication Camera VGP-VCC5
+ 1870 Webcam 1000
+ 2201 RDC-7 Camera
+ 2202 Caplio RR30
+ 2203 Caplio 300G
+ 2204 Caplio G3
+ 2205 Caplio RR30 / Medion MD 6126 Camera
+ 2206 Konica DG-3Z
+ 2207 Caplio Pro G3
+ 2208 Caplio G4
+ 2209 Caplio 400G wide
+ 220a KONICA MINOLTA DG-4Wide
+ 220b Caplio RX
+ 220c Caplio GX
+ 220d Caplio R1/RZ1
+ 220e Sea & Sea 5000G
+ 220f Rollei dr5 / Rollei dr5 (PTP mode)
+ 2211 Caplio R1S
+ 2212 Caplio R1v Camera
+ 2213 Caplio R2
+ 2214 Caplio GX 8
+ 2215 DSC 725
+ 2216 Caplio R3
+ 2222 RDC-i500
+05cb PowerVision Technologies, Inc.
+ 1483 PV8630 interface (scanners, webcams)
+05cc ELSA AG
+ 2100 MicroLink ISDN Office
+ 2219 MicroLink ISDN
+ 2265 MicroLink 56k
+ 2267 MicroLink 56k (V.250)
+ 2280 MicroLink 56k Fun
+ 3000 Micolink USB2Ethernet [pegasus]
+ 3100 AirLancer USB-11
+ 3363 MicroLink ADSL Fun
+05cd Silicom, Ltd
+05ce sci-worx GmbH
+05cf Sung Forn Co., Ltd
+05d0 GE Medical Systems Lunar
+05d1 Brainboxes, Ltd
+ 0003 Bluetooth Adapter BL-554
+05d2 Wave Systems Corp.
+05d3 Tohoku Ricoh Co., Ltd
+05d5 Super Gate Technology Co., Ltd
+05d6 Philips Semiconductors, CICT
+05d7 Thomas & Betts Corp.
+ 0099 10Mbps Ethernet [klsi]
+05d8 Ultima Electronics Corp.
+ 4001 Artec Ultima 2000
+ 4002 Artec Ultima 2000 (GT6801 based)/Lifetec LT9385/ScanMagic 1200 UB Plus Scanner
+ 4003 Artec E+ 48U
+ 4004 Artec E+ Pro
+ 4005 MEM48U
+ 4006 TRUST EASY WEBSCAN 19200
+ 4007 TRUST 240H EASY WEBSCAN GOLD
+ 4008 Trust Easy Webscan 19200
+ 4009 Umax Astraslim
+ 4013 IT Scan 1200
+ 8105 Artec T1 USB TVBOX (cold)
+ 8106 Artec T1 USB TVBOX (warm)
+ 8107 Artec T1 USB TVBOX with AN2235 (cold)
+ 8108 Artec T1 USB TVBOX with AN2235 (warm)
+ 8109 Artec T1 USB2.0 TVBOX (cold
+05d9 Axiohm Transaction Solutions
+ a225 A225 Printer
+ a758 A758 Printer
+ a794 A794 Printer
+05da Microtek International, Inc.
+ 0091 ScanMaker X6u
+ 0093 ScanMaker V6USL
+ 0094 Phantom 336CX/C3
+ 0099 ScanMaker X6/X6U
+ 009a Phantom C6
+ 00a0 Phantom 336CX/C3 (#2)
+ 00a3 ScanMaker V6USL
+ 00ac ScanMaker V6UL
+ 00b6 ScanMaker V6UPL
+ 00ef ScanMaker V6UPL
+ 1006 Jenoptik JD350 entrance
+ 1011 NHJ Che-ez! Kiss Digital Camera
+ 1018 Digital Dream Enigma 1.3
+ 1020 Digital Dream l'espion xtra
+ 1025 Take-it Still Camera Device
+ 1026 Take-it
+ 1043 Take-It 1300 DSC Bulk Driver
+ 1045 Take-it D1
+ 1047 Take-it Camera Composite Device
+ 1048 Take-it Q3
+ 1049 3M Still Camera Device
+ 1051 Camcorder Series
+ 1052 Mass Storage Device
+ 1053 Take-it DV Composite Device
+ 1054 Mass Storage Device
+ 1055 Digital Camera Series(536)
+ 1056 Mass Storage Device
+ 1057 Take-it DSC Camera Device(536)
+ 1058 Mass Storage Device
+ 1059 Camcorder DSC Series
+ 1060 Microtek Take-it MV500
+ 2007 ArtixScan DI 1210
+ 200c 1394_USB2 Scanner
+ 200e ArtixScan DI 810
+ 2017 UF ICE Scanner
+ 201c 4800 Scanner
+ 201d ArtixScan DI 1610
+ 201f 4800 Scanner-ICE
+ 202e ArtixScan DI 2020
+ 208b ScanMaker 6800
+ 208f ArtixScan DI 2010
+ 209e ScanMaker 4700LP
+ 20a7 ScanMaker 5600
+ 20b0 ScanMaker X12USL
+ 20b1 ScanMaker 8700
+ 20b4 ScanMaker 4700
+ 20bd ScanMaker 5700
+ 20c9 ScanMaker 6700
+ 20d2 Microtek ArtixScan 1800f
+ 20d6 PS4000
+ 20de ScanMaker 9800XL
+ 20e0 ScanMaker 9700XL
+ 20ed ScanMaker 4700
+ 20ee Micortek ScanMaker X12USL
+ 3008 Scanner
+ 300a 4800 ICE Scanner
+ 300b 4800 Scanner
+ 300f MiniScan C5
+ 3020 4800dpi Scanner
+ 3021 1200dpi Scanner
+ 3022 Scanner 4800dpi
+ 3023 USB1200II Scanner
+ 30c1 USB600 Scanner
+ 30ce ScanMaker 3800
+ 30cf ScanMaker 4800
+ 30d4 USB1200 Scanner
+ 30d8 Scanner
+ 30d9 USB2400 Scanner
+ 30e4 ScanMaker 4100
+ 30e5 USB3200 Scanner
+ 30e6 ScanMaker i320
+ 40b3 ScanMaker 3600
+ 40b8 ScanMaker 3700
+ 40c7 ScanMaker 4600
+ 40ca ScanMaker 3600
+ 40cb ScanMaker 3700
+ 40dd ScanMaker 3750i
+ 40ff ScanMaker 3600
+ 5003 Goya
+ 5013 3200 Scanner
+ 80a3 ScanMaker V6USL (#2)
+ 80ac ScanMaker V6UL/SpicyU
+05db Sun Corp. (Suntac?)
+ 0003 SUNTAC U-Cable type D2
+ 0005 SUNTAC U-Cable type P1
+ 0009 SUNTAC Slipper U
+ 000a SUNTAC Ir-Trinity
+ 000b SUNTAC U-Cable type A3
+ 0011 SUNTAC U-Cable type A4
+05dc Lexar Media, Inc.
+ 0001 jumpSHOT CompactFlash Reader
+ 0002 JumpShot
+ 0003 JumpShot
+ 0080 Jumpdrive Secure 64MB
+ 0081 RBC Compact Flash Drive
+ 00a7 JumpDrive Impact
+ 0100 JumpDrive PRO
+ 0200 JumpDrive 2.0 Pro
+ 0300 Jumpdrive Geysr
+ 0301 JumpDrive Classic
+ 0302 JD Micro
+ 0303 JD Micro Pro
+ 0304 JD Secure II
+ 0310 JumpDrive
+ 0311 JumpDrive Classic
+ 0312 JD Micro
+ 0313 JD Micro Pro
+ 0320 JumpDrive
+ 0321 JD Micro
+ 0322 JD Micro Pro
+ 0323 UFC
+ 0330 JumpDrive Expression
+ 0340 JumpDrive TAD
+ 0350 Express Card
+ 0400 UFDC
+ 0401 UFDC
+ 0403 Locked B Device
+ 0405 Locked C Device
+ 0407 Locked D Device
+ 0409 Locked E Device
+ 040b Locked F Device
+ 040d Locked G Device
+ 040f Locked H Device
+ 0410 JumpDrive
+ 0411 JumpDrive
+ 0413 Locked J Device
+ 0415 Locked K Device
+ 0417 Locked L Device
+ 0419 Locked M Device
+ 041b Locked N Device
+ 041d Locked O Device
+ 041f Locked P Device
+ 0420 JumpDrive
+ 0421 JumpDrive
+ 0423 Locked R Device
+ 0425 Locked S Device
+ 0427 Locked T Device
+ 0429 Locked U Device
+ 042b Locked V Device
+ 042d Locked W Device
+ 042f Locked X Device
+ 0431 Locked Y Device
+ 0433 Locked Z Device
+ 4d02 MP3 Player
+ 4d12 MP3 Player
+ a300 JumpDrive2
+ a400 JumpDrive trade; Pro 40-501
+ a410 JumpDrive 128MB/256MB
+ a411 JumpDrive Traveler
+ a420 JumpDrive Pro
+ a421 JumpDrive Pro II
+ a422 JumpDrive Micro Pro
+ a430 JumpDrive Secure
+ a431 JumpDrive Secure II
+ a432 JumpDrive Classic
+ a440 JumpDrive Lightning
+ a450 JumpDrive TouchGuard
+ a460 JD Mercury
+ a501 JumpDrive Classic
+ a510 JumpDrive Sport
+ a530 JumpDrive Expression
+ a531 JumpDrive Secure II
+ a560 JumpDrive FireFly
+ a701 JumpDrive FireFly
+ b002 USB CF Reader
+ b018 Multi-Card Reader
+05dd Delta Electronics, Inc.
+ ff31 AWU-120
+ ff32 FriendlyNET AeroLAN AL2011
+ ff35 PCW 100 - Wireless 802.11b Adapter
+ ff91 2Wire PC Port Phoneline 10Mbps Adapter
+05df Silicon Vision, Inc.
+05e0 Symbol Technologies
+ 0700 Bar Code Scanner (CS1504)
+ 0800 Spectrum24 Wireless LAN Adapter
+ 1200 DS6608 Bar Code Scanner
+ 1900 SNAPI Imaging Device
+ 2000 MC3090 Rugged Mobile Computer
+ 200d MC70 Rugged Mobile Computer
+05e1 Syntek Semiconductor Co., Ltd
+ 0500 DC-112X
+ 0501 WebCam, Chipset DC-1125 similar to 174f:a311 - Asus F2F, F2J, F3J, F3T, G1, Z53JA
+ 0890 STK011 Camera
+ 0892 STK013 Camera
+ 0895 STK016 Camera
+ 0896 STK017 Camera
+05e2 ElecVision, Inc.
+05e3 Genesys Logic, Inc.
+ 000a Keyboard with PS/2 Port
+ 000b Mouse
+ 0100 Nintendo Game Boy Advance SP
+ 0120 Pacific Image Electronics PrimeFilm 1800u slide/negative scanner
+ 0131 CF/SM Reader/Writer
+ 0142 Multiple Slides Scanner-3600
+ 0143 Multiple Frames Film Scanner-36series
+ 0180 Plustek Scanner
+ 0182 Wize Media 1000
+ 0189 ScanJet 4600 series
+ 018a Xerox 6400
+ 0300 GLUSB98PT Parallel Port
+ 0301 USB2LPT Cable Release2
+ 0406 Hub
+ 0501 GL620USB Host-Host interface
+ 0502 GL620USB GeneLink USB-USB Bridge
+ 0504 HID Keyboard Filter
+ 0604 USB 1.1 Hub
+ 0605 USB 2.0 Hub [ednet]
+ 0606 USB 2.0 Hub / D-Link DUB-H4 USB 2.0 Hub
+ 0608 USB-2.0 4-Port HUB
+ 0660 USB 2.0 Hub
+ 0700 SIIG US2256 CompactFlash Card Reader
+ 0701 USB 2.0 IDE Adapter
+ 0702 USB 2.0 IDE Adapter
+ 0703 Card Reader
+ 0704 Card Reader
+ 0705 Card Reader
+ 0706 Card Reader
+ 0707 Card Reader
+ 0708 Card Reader
+ 0709 Card Reader
+ 070a Pen Flash
+ 070b DMHS1B Rev 3 DFU Adapter
+ 070e X-PRO CR20xA USB 2.0 Internal Card Reader
+ 070f Pen Flash
+ 0710 USB 2.0 33-in-1 Card Reader
+ 0711 Card Reader
+ 0712 Delkin Mass Storage Device
+ 0715 USB 2.0 microSD Reader
+ 0760 USB 2.0 Card Reader/Writer
+ 0761 Genesys Mass Storage Device
+ 0780 USBFS DFU Adapter
+ 07a0 Pen Flash
+ 0927 Card Reader
+ 1205 Afilias Optical Mouse H3003
+ a700 Pen Flash
+ f102 VX7012 TV Box
+ f103 VX7012 TV Box
+ f104 VX7012 TV Box
+ fd21 3M TL20 Temperature Logger
+ fe00 Razer Mouse
+05e4 Red Wing Corp.
+05e5 Fuji Electric Co., Ltd
+05e6 Keithley Instruments
+05e8 ICC, Inc.
+05e9 Kawasaki LSI
+ 0008 KL5KUSB101B Ethernet [klsi]
+ 0009 Sony 10Mbps Ethernet [pegasus]
+ 000c USB-to-RS-232
+ 000d USB-to-RS-232
+ 0014 RS-232 J104
+ 0040 Ethernet Adapter
+ 2008 Ethernet Adapter
+05eb FFC, Ltd
+05ec COM21, Inc.
+05ee Cytechinfo Inc.
+05ef AVB, Inc. [anko?]
+ 020a Top Shot Pegasus Joystick
+ 8884 Mag Turbo Force Wheel
+ 8888 Top Shot Force Feedback Racing Wheel
+05f0 Canopus Co., Ltd
+ 0101 DA-Port DAC
+05f1 Compass Communications
+05f2 Dexin Corp., Ltd
+ 0010 AQ Mouse
+05f3 PI Engineering, Inc.
+ 0007 Kinesis Advantage PRO MPC/USB Keyboard
+ 0081 Kinesis Integrated Hub
+ 020b PS2 Adapter
+ 0232 X-Keys Switch Interface, Programming Mode
+ 0261 X-Keys Switch Interface, SPLAT Mode
+ 0264 X-Keys Switch Interface, Composite Mode
+05f5 Unixtar Technology, Inc.
+05f6 AOC International
+05f7 RFC Distribution(s) PTE, Ltd
+05f9 PSC Scanning, Inc.
+05fa Siemens Telecommunications Systems, Ltd
+ 3301 Keyboard with PS/2 Mouse Port
+ 3302 Keyboard
+ 3303 Keyboard with PS/2 Mouse Port
+05fc Harman Multimedia
+ 7849 Harman/Kardon SoundSticks
+05fd InterAct, Inc.
+ 0239 SV-239 HammerHead Digital
+ 0251 Raider Pro
+ 0253 ProPad 8 Digital
+ 0286 SV-286 Cyclone Digital
+ 262a 3dfx HammerHead FX
+ 262f HammerHead Fx
+ daae Game Shark
+05fe Chic Technology Corp.
+ 0001 Mouse
+ 0003 Cypress USB Mouse
+ 0005 Viewmaster 4D Browser Mouse
+ 0007 Twinhead Mouse
+ 0009 Inland Pro 4500/5000 Mouse
+ 0011 Browser Mouse
+ 1010 Optical Wireless
+05ff LeCroy Corp.
+0600 Barco Display Systems
+0601 Jazz Hipster Corp.
+ 0003 Internet Security Co., Ltd. SecureKey
+0602 Vista Imaging, Inc.
+ 1001 ViCam WebCam
+0603 Novatek Microelectronics Corp.
+ 00f1 Keyboard
+ 6871 Mouse
+0604 Jean Co., Ltd
+0605 Anchor C&C Co., Ltd
+0606 Royal Information Electronics Co., Ltd
+0607 Bridge Information Co., Ltd
+0608 Genrad Ads
+0609 SMK Manufacturing, Inc.
+ 031d eHome Infrared Receiver
+ 0322 eHome Infrared Receiver
+ ff12 SMK Bluetooth Device
+060a Worthington Data Solutions, Inc.
+060b Solid Year
+ 0001 MacAlly Keyboard
+ 1006 Japanese Keyboard - 260U
+ 2101 Keyboard
+ 5811 ACK-571U Wireless Keyboard
+ 5903 Japanese Keyboard - 595U
+ 6001 SolidTek USB 2p HUB
+ 6002 SolidTek USB Keyboard
+ 6003 Japanese Keyboard - 600HM
+ a001 Maxwell Compact Pc PM3
+060c EEH Datalink GmbH
+060d Auctor Corp.
+060e Transmonde Technologies, Inc.
+060f Joinsoon Electronics Mfg. Co., Ltd
+0610 Costar Electronics, Inc.
+0611 Totoku Electric Co., Ltd
+0613 TransAct Technologies, Inc.
+0614 Bio-Rad Laboratories
+0615 Quabbin Wire & Cable Co., Inc.
+0616 Future Techno Designs PVT, Ltd
+0617 Swiss Federal Insitute of Technology
+0618 MacAlly
+ 0101 Mouse
+0619 Seiko Instruments, Inc.
+ 0101 SLP-100 Driver
+ 0102 SLP-200 Driver
+ 0103 SLP-100N Driver
+ 0104 SLP-200N Driver
+ 0105 SLP-240 Driver
+061a Veridicom International, Inc.
+ 0110 5thSense Fingerprint Sensor
+ 0200 FPS200 Fingerprint Sensor
+ 8200 VKI-A Fingerprint Sensor/Flash Storage (dumb)
+ 9200 VKI-B Fingerprint Sensor/Flash Storage (smart)
+061b Promptus Communications, Inc.
+061c Act Labs, Ltd
+061d Quatech, Inc.
+061e Nissei Electric Co.
+ 0001 nissei 128DE-USB -
+ 0010 nissei 128DE-PNA -
+0620 Alaris, Inc.
+ 0004 QuickVideo weeCam
+ 0007 QuickVideo weeCam
+ 000a QuickVideo weeCam
+ 000b QuickVideo weeCam
+0621 ODU-Steckverbindungssysteme GmbH & Co. KG
+0622 Iotech, Inc.
+0623 Littelfuse, Inc.
+0624 Avocent Corp.
+0625 TiMedia Technology Co., Ltd
+0626 Nippon Systems Development Co., Ltd
+0627 Adomax Technology Co., Ltd
+0628 Tasking Software, Inc.
+0629 Zida Technologies, Ltd
+062a Creative Labs
+ 0000 Optical mouse
+ 0001 Notebook Optical Mouse
+ 0201 Defender Office Keyboard (K7310) S Zodiak KM-9010
+ 9003 VoIP Conference Hub (A16GH)
+ 9004 USR9602 USB Internet Mini Phone
+062b Greatlink Electronics Taiwan, Ltd
+062c Institute for Information Industry
+062d Taiwan Tai-Hao Enterprises Co., Ltd
+062e Mainsuper Enterprises Co., Ltd
+062f Sin Sheng Terminal & Machine, Inc.
+0631 JUJO Electronics Corp.
+0633 Cyrix Corp.
+0634 Micron Technology, Inc.
+0635 Methode Electronics, Inc.
+0636 Sierra Imaging, Inc.
+ 0003 Vivicam 35Xx
+0638 Avision, Inc.
+ 0268 iVina 1200U Scanner
+ 026a Minolta Dimage Scan Dual II
+ 0a10 iVina FB1600/UMAX Astra 4500
+ 0a13 AV600U
+ 0a16 SC-215
+ 0a30 UMAX Astra 6700 Scanner
+ 0a41 Avision AM3000/MF3000 Series
+ 0f01 fi-4010CU
+ 4004 Minolta Dimage Scan Elite II
+0639 Chrontel, Inc.
+063a Techwin Corp.
+063b Taugagreining HF
+063c Yamaichi Electronics Co., Ltd (Sakura)
+063d Fong Kai Industrial Co., Ltd
+063e RealMedia Technology, Inc.
+063f New Technology Cable, Ltd
+0640 Hitex Development Tools
+0641 Woods Industries, Inc.
+0642 VIA Medical Corp.
+0644 TEAC Corp.
+ 0000 Floppy
+ 1000 CD-ROM Drive
+ 800d TASCAM Portastudio DP-01FX
+ d001 CD-R/RW Unit
+ d002 CD-R/RW Unit
+ d010 CD-RW/DVD Unit
+0645 Who? Vision Systems, Inc.
+0646 UMAX
+0647 Acton Research Corp.
+ 0100 ARC SpectraPro UV/VIS/IR Monochromator/Spectrograph
+ 0101 ARC AM-VM Mono Airpath/Vacuum Monochromator/Spectrograph
+ 0102 ARC Inspectrum Mono
+ 0103 ARC Filterwheel
+ 03e9 Inspectrum 128x1024 F VIS Spectrograph
+ 03ea Inspectrum 256x1024 F VIS Spectrograph
+ 03eb Inspectrum 128x1024 B VIS Spectrograph
+ 03ec Inspectrum 256x1024 B VIS Spectrograph
+0648 Inside Out Networks
+0649 Weli Science Co., Ltd
+064b White Mountain DSP, Inc.
+064c Ji-Haw Industrial Co., Ltd
+064d TriTech Microelectronics, Ltd
+064e Suyin Corp.
+064f WIBU-Systems AG
+ 0bd7 BOX/U
+ 0bd8 BOX/RU
+0650 Dynapro Systems
+0651 Likom Technology Sdn. Bhd.
+0652 Stargate Solutions, Inc.
+0653 CNF, Inc.
+0654 Granite Microsystems, Inc.
+ 0005 Device Bay Controller
+ 0006 Hub
+ 0007 Device Bay Controller
+ 0016 Hub
+0655 Space Shuttle Hi-Tech Co., Ltd
+0656 Glory Mark Electronic, Ltd
+0657 Tekcon Electronics Corp.
+0658 Sigma Designs, Inc.
+0659 Aethra
+065a Optoelectronics Co., Ltd
+ 0001 Barcode scanner
+065b Tracewell Systems
+065e Silicon Graphics
+065f Good Way Technology Co., Ltd & GWC technology Inc.
+0660 TSAY-E (BVI) International, Inc.
+0661 Hamamatsu Photonics K.K.
+0662 Kansai Electric Co., Ltd
+0663 Topmax Electronic Co., Ltd
+ 0103 CobraPad
+0667 Aiwa Co., Ltd
+ 0fa1 TD-U8000 Tape Drive
+0668 WordWand
+0669 Oce' Printing Systems GmbH
+066a Total Technologies, Ltd
+066b Linksys, Inc.
+ 0105 SCM eUSB SmartMedia Card Reader
+ 010a Melco MCR-U2 SmartMedia / CompactFlash Reader
+ 200c USB10TX
+ 2202 USB10TX Ethernet [pegasus]
+ 2203 USB100TX Ethernet [pegasus]
+ 2204 USB100TX HomePNA Ethernet [pegasus]
+ 2206 USB Ethernet [pegasus]
+ 2207 HomeLink Phoneline 10M Network Adapter
+ 2211 WUSB11 802.11b Adapter
+ 2212 WUSB11v2.5 802.11b Adapter
+ 2213 WUSB12v1.1 802.11b Adapter
+ 2219 Instant Wireless Network Adapter
+ 400b USB10TX
+066d Entrega, Inc.
+066e Acer Semiconductor America, Inc.
+066f SigmaTel, Inc.
+ 003b MP3 Player
+ 003e MP3 Player
+ 003f MP3 Player
+ 0040 MP3 Player
+ 0041 MP3 Player
+ 0042 MP3 Player
+ 0043 MP3 Player
+ 004b A-Max PA11 MP3 Player
+ 3400 STMP3400 D-Major MP3 Player
+ 3410 STMP3410 D-Major MP3 Player
+ 3500 Player Recovery Device
+ 4200 STIr4200 IrDA Bridge
+ 4210 STIr4210 IrDA Bridge
+ 8000 MSCN MP3 Player
+ 8001 SigmaTel MSCN Audio Player
+ 8004 MSCNMMC MP3 Player
+ 8008 i-Bead 100 MP3 Player
+ 8020 MP3 Player
+ 8034 MP3 Player
+ 8036 MP3 Player
+ 8038 MP3 Player
+ 8056 MP3 Player
+ 8060 MP3 Player
+ 8066 MP3 Player
+ 807e MP3 Player
+ 8092 MP3 Player
+ 8096 MP3 Player
+ 809a MP3 Player
+ 80aa MP3 Player
+ 80ac MP3 Player
+ 80b8 MP3 Player
+ 80ba MP3 Player
+ 80bc MP3 Player
+ 80bf MP3 Player
+ 80c5 MP3 Player
+ 80c8 MP3 Player
+ 80ca MP3 Player
+ 80cc MP3 Player
+ 8104 MP3 Player
+ 8106 MP3 Player
+ 8108 MP3 Player
+ 810a MP3 Player
+ 810c MP3 Player
+ 8122 MP3 Player
+ 8124 MP3 Player
+ 8126 MP3 Player
+ 8128 MP3 Player
+ 8134 MP3 Player
+ 8136 MP3 Player
+ 8138 MP3 Player
+ 813a MP3 Player
+ 813e MP3 Player
+ 8140 MP3 Player
+ 8142 MP3 Player
+ 8144 MP3 Player
+ 8146 MP3 Player
+ 8148 MP3 Player
+ 814c MP3 Player
+ 8201 MP3 Player
+ 8202 Jens of Sweden / I-BEAD 150M/150H MP3 player
+ 8203 MP3 Player
+ 8204 MP3 Player
+ 8205 MP3 Player
+ 8206 Digital MP3 Music Player
+ 8207 MP3 Player
+ 8208 MP3 Player
+ 8209 MP3 Player
+ 820a MP3 Player
+ 820b MP3 Player
+ 820c MP3 Player
+ 820d MP3 Player
+ 820e MP3 Player
+ 820f MP3 Player
+ 8210 MP3 Player
+ 8211 MP3 Player
+ 8212 MP3 Player
+ 8213 MP3 Player
+ 8214 MP3 Player
+ 8215 MP3 Player
+ 8216 MP3 Player
+ 8217 MP3 Player
+ 8218 MP3 Player
+ 8219 MP3 Player
+ 821a MP3 Player
+ 821b MP3 Player
+ 821c MP3 Player
+ 821d MP3 Player
+ 821e MP3 Player
+ 821f MP3 Player
+ 8220 MP3 Player
+ 8221 MP3 Player
+ 8222 MP3 Player
+ 8223 MP3 Player
+ 8224 MP3 Player
+ 8225 MP3 Player
+ 8226 MP3 Player
+ 8227 MP3 Player
+ 8228 MP3 Player
+ 8229 MP3 Player
+ 8230 MP3 Player
+ 9000 MP3 Player
+ 9001 MP3 Player
+ 9002 MP3 Player
+0672 Labtec, Inc.
+ 1041 LCS1040 Speaker System
+ 5000 SpaceBall 4000 FLX
+0673 HCL
+ 5000 Keyboard
+0674 Key Mouse Electronic Enterprise Co., Ltd
+0675 Draytech
+ 0110 Vigor 128 ISDN TA
+ 0550 Vigor550
+0676 Teles AG
+0677 Aiwa Co., Ltd
+ 07d5 TM-ED1285(USB)
+ 0fa1 TD-U8000 Tape Drive
+0678 ACard Technology Corp.
+067b Prolific Technology, Inc.
+ 0000 PL2301 USB-USB Bridge
+ 0001 PL2302 USB-USB Bridge
+ 04bb PL2303 Serial (IODATA USB-RSAQ2)
+ 0610 Onext EG210U MODEM
+ 0611 AlDiga AL-11U Quad-band GSM/GPRS/EDGE modem
+ 2303 PL2303 Serial Port
+ 2305 PL2305 Parallel Port
+ 2307 PL2307 USB-ATAPI4 Bridge
+ 2313 FITEL PHS U Cable Adaptor
+ 2315 Flash Disk Embedded Hub
+ 2316 Flash Disk Security Device
+ 2317 Mass Storage Device
+ 2501 PL2501 USB-USB Bridge (USB 2.0)
+ 2507 PL2507 Hi-speed USB to IDE bridge controller
+ 2515 Flash Disk Embedded Hub
+ 2517 Flash Disk Mass Storage Device
+ 25a1 PL25A1 Host-Host Bridge
+ 3400 Hi-Speed Flash Disk with TruePrint AES3400
+ 3500 Hi-Speed Flash Disk with TruePrint AES3500
+ 3507 PL3507 ATAPI6 Bridge
+ aaa0 Prolific Pharos
+ aaa2 PL2303 Serial Adapter (IODATA USB-RSAQ3)
+067c Efficient Networks, Inc.
+ 1001 Siemens SpeedStream 100MBps Ethernet
+ 1022 Siemens SpeedStream 1022 802.11b Adapter
+ 1023 SpeedStream Wireless
+ 4020 SpeedStream 4020 ATM/ADSL Installer
+ 4031 Efficient ADSL Modem
+ 4032 SpeedStream 4031 ATM/ADSL Installer
+ 4033 SpeedStream 4031 ATM/ADSL Installer
+ 4060 Alcatel Speedstream 4060 ADSL Modem
+ 4062 Efficient Networks 4060 Loader
+ 5667 Efficient Networks Virtual Bus for ADSL Modem
+ c031 SpeedStream 4031 ATM/ADSL Installer
+ c032 SpeedStream 4031 ATM/ADSL Installer
+ c033 SpeedStream 4031 ATM/ADSL Installer
+ c060 SpeedStream 4060 Miniport ATM/ADSL Adapter
+ d667 Efficient Networks Virtual Bus for ADSL Modem
+ e240 Speedstream Ethernet Adapter E240
+ e540 Speedstream Ethernet Adapter E240
+067d Hohner Corp.
+067e Intermec
+ 1001 Mobile Computer
+067f Virata, Ltd
+ 4552 DSL-200 ADSL Modem
+ 6542 DSL Modem
+ 6549 DSL Modem
+ 7541 DSL Modem
+0680 Realtek Semiconductor Corp., CPP Div. (Avance Logic)
+ 0002 Arowana Optical Wheel Mouse MSOP-01
+0681 Siemens Information and Communication Products
+ 0001 Dect Base
+ 0002 Gigaset 3075 Passive ISDN
+ 0005 ID-Mouse with Fingerprint Reader
+ 0012 I-Gate 802.11b Adapter
+ 001b WLL013
+ 0022 Gigaset SX353 ISDN
+ 002b A-100-I ADSL Modem
+ 002e ADSL Router_S-141
+ 0034 GSM module MC35/ES75 USB Modem
+ 3c06 54g USB Network Adapter
+0682 Victor Company of Japan, Ltd
+0684 Actiontec Electronics, Inc.
+0686 Minolta Co., Ltd
+ 2001 PagePro 4110W
+ 3001 PagePro 4100
+ 3006 PagePro 1250W
+ 302e Develop D 1650iD PCL
+ 3034 Develop D 2050iD PCL
+ 4001 Dimage 2300
+ 4003 Dimage 2330 Zoom Camera
+ 4004 Scan Elite II
+ 4005 Minolta DiMAGE E201 Mass Storage Device
+ 4006 Dimage 7 Camera
+ 4007 Dimage S304 Camera
+ 4008 Dimage 5 Camera
+ 4009 Dimage X Camera
+ 400a Dimage S404 Camera
+ 400b Dimage 7i Camera
+ 400c Dimage F100 Camera
+ 400d Scan Dual III
+ 400e Dimage 5400
+ 400f Dimage 7Hi Camera
+ 4010 Dimage Xi Camera
+ 4011 Dimage F300 Camera
+ 4012 Dimage F200 Camera
+ 4014 Dimage S414 Camera
+ 4015 Dimage XT Camera [storage]
+ 4016 Dimage XT Camera [remote mode]
+ 4017 Dimage E223
+ 4018 Dimage Z1 Camera
+ 401a Dimage A1 Camera
+ 401c Dimage X20 Camera
+ 401e Dimage E323 Camera
+068a Pertech, Inc.
+068b Potrans International, Inc.
+068e CH Products, Inc.
+ 00e2 HFX OEM Joystick
+ 00f1 Pro Throttle
+ 00f2 Flight Sim Pedals
+ 00f3 Fighterstick
+ 00ff Flight Sim Yoke
+ 0500 GameStick 3D
+ 0501 CH Pro Pedals
+ 0504 F-16 Combat Stick
+0690 Golden Bridge Electech, Inc.
+0693 Hagiwara Sys-Com Co., Ltd
+ 0002 FlashGate SmartMedia Card Reader
+ 0003 FlashGate CompactFlash Card Reader
+ 0005 FlashGate
+ 0006 SM PCCard R/W and SPD
+ 0007 FlashGate ME (Authenticated)
+ 000a SDCard/MMC Reader/Writer
+0694 Lego Group
+ 0001 Mindstorms Tower
+0698 Chuntex (CTX)
+ 1786 1300ex Monitor
+ 9999 VLxxxx Monitor+Hub
+0699 Tektronix, Inc.
+069a Askey Computer Corp.
+ 0001 VC010 WebCam [pwc]
+ 0303 Cable Modem
+ 0311 ADSL Router Remote NDIS Device
+ 0318 Remote NDIS Device
+ 0319 220V Remote NDIS Device
+ 0320 IEEE 802.11b Wireless LAN Card
+ 0321 Dynalink WLL013 / Compex WLU11A 802.11b Adapter
+ 0402 Scientific Atlanta WebSTAR 100 & 200 series Cable Modem
+ 0811 BT Virtual Bus for Helium
+ 0821 BT Voyager 1010 802.11b Adapter
+ 4402 Scientific Atlanta WebSTAR 2000 series Cable Modem
+ 4403 Scientific Atlanta WebSTAR 300 series Cable Modem
+ 4501 Scientific-Atlanta WebSTAR 2000 series Cable Modem
+069b Thomson, Inc.
+ 0704 DCM245 Cable Modem
+ 070c MP3 Player
+ 070d MP3 Player
+ 070e MP3 Player
+ 070f RCA Lyra RD1071 MP3 Player
+ 2220 RCA Kazoo RD1000 MP3 Player
+ 300a RCA Lyra MP3 Player
+ 3012 MP3 Player
+ 3013 MP3 Player
+ 5557 RCA CDS6300
+069d Hughes Network Systems (HNS)
+ 0001 Satellite Receiver Device
+ 0002 Satellite Device
+069e Marx
+ 0005 CryptoBox v1.2
+069f Allied Data Technologies BV
+ 0010 Tornado Speakerphone FaxModem 56.0
+ 0011 Tornado Speakerphone FaxModem 56.0
+ 1000 ADT VvBus for CopperJet
+06a2 Topro Technology, Inc.
+06a3 Saitek PLC
+ 0006 Cyborg Gold Joystick
+ 0109 P880 Pad
+ 0160 ST290 Pro
+ 0200 Xbox Adrenalin Hub
+ 0241 Xbox Adrenalin Gamepad
+ 0255 X52 Flight Controller
+ 040b P990 Dual Analog Pad
+ 040c P2900 Wireless Pad
+ 0422 ST90 Joystick
+ 0460 ST290 Pro Flight Stick
+ 0463 ST290
+ 0464 Cyborg Evo
+ 0471 Cyborg Graphite Stick
+ 0501 R100 Sports Wheel
+ 0502 ST200 Stick
+ 0506 R220 Digital Wheel
+ 051e Cyborg Digital II Stick
+ 052d P750 Gamepad
+ 053c X45 Flight Controller
+ 053f X36F Flightstick
+ 056c P2000 Tilt Pad
+ 056f P2000 Tilt Pad
+ 05d2 PC Dash 2
+ 075c X52 Flight Controller
+ 0805 R440 Force Wheel
+ 1003 GM2 Action Pad
+ 1009 Action Pad
+ 100a SP550 Pad and Joystick Combo
+ 100b SP550 Pad
+ 1509 P3000 Wireless Pad
+ 1589 P3000 Wireless Pad
+ 2541 X45 Flight Controller
+ 3509 P3000 RF GamePad
+ 353e Cyborg Evo Wireless
+ 3589 P3000 Wireless Pad
+ 35be Cyborg Evo
+ 5509 P3000 Wireless Pad
+ 8000 Gamers' Keyboard
+ 801e Cyborg 3D Digital Stick II
+ 8021 Eclipse II Keyboard
+ 802d P750 Pad
+ 803f X36 Flight Controller
+ 806f P2000 Tilt Pad
+ 80c0 Pro Gamer Command Unit
+ a502 Gaming Mouse
+ ff04 R440 Force Wheel
+ ff0c Cyborg Force Rumble Pad
+ ff0d P2600 Rumble Force Pad
+ ff12 Cyborg 3D Force Stick
+ ff17 ST 330 Rumble Force Stick
+ ff52 Cyborg 3D Rumble Force Joystick
+ ffb5 Cyborg Evo Force Joystick
+06a4 Xiamen Doowell Electron Co., Ltd
+06a5 Divio
+ 0000 Typhoon Webcam 100k [nw8000]
+ d001 ProLink DS3303u WebCam
+ d800 Chicony TwinkleCam
+ d820 Wize Media 1000
+06a7 MicroStore, Inc.
+06a8 Topaz Systems, Inc.
+ 0042 SignatureGem 1X5 Pad
+ 0043 SignatureGem 1X5-HID Pad
+06a9 Westell
+ 0005 WireSpeed Dual Connect Modem
+ 0006 WireSpeed Dual Connect Modem
+ 000a WireSpeed Dual Connect Modem
+ 000b WireSpeed Dual Connect Modem
+ 000e 802.11g Adapter
+06aa Sysgration, Ltd
+06ac Fujitsu Laboratories of America, Inc.
+06ad Greatland Electronics Taiwan, Ltd
+06ae Professional Multimedia Testing Centre
+06af Harting, Inc. of North America
+06b8 Pixela Corp.
+06b9 Alcatel Telecom
+ 0121 SpeedTouch 121g Wireless Dongle
+ 2001 SPEED TOUCH Card
+ 4061 SpeedTouch ISDN or ADSL Modem
+ a5a5 DynaMiTe Modem
+06ba Smooth Cord & Connector Co., Ltd
+06bb EDA, Inc.
+06bc Oki Data Corp.
+06bd AGFA-Gevaert NV
+ 0001 SnapScan 1212U
+ 0002 SnapScan 1236U
+ 0100 SnapScan Touch
+ 0101 SNAPSCAN ELITE
+ 0200 ScanMaker 8700
+ 02bf DUOSCAN f40
+ 0400 CL30
+ 0401 Mass Storage
+ 0403 ePhoto CL18 Camera
+ 0404 ePhoto CL20 Camera
+ 2061 SnapScan 1212U (?)
+ 208d Snapscan e40
+ 208f SnapScan e50
+ 2091 SnapScan e20
+ 2093 SnapScan e10
+ 2095 SnapScan e25
+ 2097 SnapScan e26
+ 20fd SnapScan e52
+ 20ff SnapScan e42
+06be AME Optimedia Technology Co., Ltd
+ 1005 Dazzle DPVM! (1005)
+ d001 P35U Camera Capture
+06bf Leoco Corp.
+06c2 Phidgets Inc. (formerly GLAB)
+ 0030 PhidgetRFID
+ 0038 4-Motor PhidgetServo v3.0
+ 0039 1-Motor PhidgetServo v3.0
+ 003a 8-Motor PhidgetAvancedServo
+ 0040 PhidgetInterface Kit 0-0-4
+ 0044 PhidgetInterface Kit 0-16-16
+ 0045 PhidgetInterface Kit 8-8-8
+ 0048 PhidgetStepper (Under Development)
+ 0049 PhidgetTextLED Ver 1.0
+ 004a PhidgetLED Ver 1.0
+ 004b PhidgetEncoder Ver 1.0
+ 0051 PhidgetInterface Kit 0-5-7 (Custom)
+ 0052 PhidgetTextLCD
+ 0053 PhidgetInterfaceKit 0-8-8
+ 0058 PhidgetMotorControl Ver 1.0
+ 0070 PhidgetTemperatureSensor Ver 1.0
+ 0071 PhidgetAccelerometer Ver 1.0
+ 0072 PhidgetWeightSensor Ver 1.0
+ 0073 PhidgetHumiditySensor
+ 0074 PhidgetPHSensor
+ 0075 PhidgetGyroscope
+06c4 Bizlink International Corp.
+06c5 Hagenuk, GmbH
+06c6 Infowave Software, Inc.
+06c8 SIIG, Inc.
+06c9 Taxan (Europe), Ltd
+ 0005 Monitor Control
+ 0007 Monitor Control
+ 0009 Monitor Control
+06ca Newer Technology, Inc.
+06cb Synaptics, Inc.
+ 0001 HID Device
+ 0002 HID Device
+ 0003 HID Device
+ 0005 Touchpad/FPS
+ 0006 HID Device
+ 0007 HID Device
+ 0008 HID Device
+ 0009 Composite TouchPad and TrackPoint
+ 000e HID Device
+ 0010 Composite Human Interface Device
+ 0013 Human Interface Device
+06cc Terayon Communication Systems
+ 0101 Cable Modem
+ 0102 Cable Modem
+ 0103 Cable Modem
+ 0104 Cable Modem
+ 0304 Cable Modem
+06cd Keyspan
+ 0101 USA-28 PDA [no firmware]
+ 0102 USA-28X PDA [no firmware]
+ 0103 USA-19 PDA [no firmware]
+ 0104 PDA [prerenum]
+ 0105 USA-18X PDA [no firmware]
+ 0106 USA-19W PDA [no firmware]
+ 0107 USA-19 PDA
+ 0108 USA-19W PDA
+ 0109 USA-49W serial adapter [no firmware]
+ 010a USA-49W serial adapter
+ 010b USA-19Qi serial adapter [no firmware]
+ 010c USA-19Qi serial adapter
+ 010d USA-19Q serial Adapter (no firmware)
+ 010e USA-19Q serial Adapter
+ 010f USA-28 PDA
+ 0110 USA-28Xb PDA
+ 0111 USA-18 serial Adapter
+ 0112 USA-18X PDA
+ 0113 USA-28Xb PDA [no firmware]
+ 0114 USA-28Xa PDA [no firmware]
+ 0115 USA-28Xa PDA
+ 0116 USA-18XA serial Adapter (no firmware)
+ 0117 USA-18XA serial Adapter
+ 0118 USA-19QW PDA [no firmware]
+ 0119 USA-19QW PDA
+ 011a USA-49Wlc serial adapter [no firmware]
+ 011b MPR Serial Preloader (MPRQI)
+ 011c MPR Serial (MPRQI)
+ 011d MPR Serial Preloader (MPRQ)
+ 011e MPR Serial (MPRQ)
+ 0121 USA-19hs serial adapter
+ 012a USA-49Wlc serial adapter
+ 0201 Digital Media Remote
+ 0202 UIA-11 remote control
+06cf SpheronVR AG
+ 1010 PanoCam 10
+ 1012 PanoCam 12/12X
+06d0 LapLink, Inc.
+ 0622 LapLink Gold USB-USB Bridge [net1080]
+06d1 Daewoo Electronics Co., Ltd
+06d3 Mitsubishi Electric Corp.
+ 0380 CP8000D Port
+ 0381 CP770D Port
+ 0385 CP900D Port
+ 0387 CP980D Port
+ 038b CP3020D Port
+ 038c CP900DW(ID) Port
+ 0393 CP9500D/DW Port
+ 0394 CP9000D/DW Port
+ 03a1 CP9550D/DW Port
+06d4 Cisco Systems
+06d5 Toshiba
+ 4000 Japanese Keyboard
+06d6 Aashima Technology B.V.
+ 002d Trust PowerC@m 350FT
+ 002e Trust PowerC@m 350FS
+ 0030 Trust 710 LCD POWERC@M ZOOM - MSD
+ 0031 Trust 710 LCD POWERC@M ZOOM
+ 003a Trust PowerC@m 770Z
+ 003c Trust 910z PowerC@m
+ 003f Trust 735S POWERC@M ZOOM, WDM DSC Bulk Driver
+ 0050 Trust 738AV LCD PV Digital Camera
+ 0062 TRUST 782AV LCD P. V. Video Capture
+ 0066 TRUST Digital PCTV and Movie Editor
+ 006b TRUST AUDIO VIDEO EDITOR
+06d7 Network Computing Devices (NCD)
+06d8 Technical Marketing Research, Inc.
+06da Phoenixtec Power Co., Ltd
+ 0002 UPS
+06db Paradyne
+06dc Foxlink Image Technology Co., Ltd
+ 0012 Scan 1200c Scanner
+ 0014 Prolink Winscan Pro 2448U
+06de Heisei Electronics Co., Ltd
+06e0 Multi-Tech Systems, Inc.
+ f101 MT5634ZBA-USB MultiModemUSB (old firmware)
+ f103 MT5634MU MultiMobileUSB
+ f104 MT5634ZBA-USB MultiModemUSB (new firmware)
+ f107 MT5634ZBA-USB-V92 MultiModemUSB
+06e1 ADS Technologies, Inc.
+ 0008 UBS-10BT Ethernet [klsi]
+ 0009 UBS-10BT Ethernet
+ 0833 Mass Storage Device
+ a160 Instant Video-To-Go RDX-160 (no firmware)
+ a161 Instant Video-To-Go RDX-160
+ a190 Instand VCD Capture
+ a191 Instant VideoXpress
+ a337 Mini DigitalTV
+ a701 DVD Xpress
+ b337 Mini DigitalTV
+ b701 DVD Xpress B
+06e4 Alcatel Microelectronics
+06e6 Tiger Jet Network, Inc.
+ 0200 Internet Phone
+ 0201 Internet Phone
+ 0202 Composite Device
+ 0203 Internet Phone
+ 0210 Composite Device
+ 0211 Internet Phone
+ 0212 Internet Phone
+ 031c Internet Phone
+ 031d Internet Phone
+ 031e Internet Phone
+ 3200 Composite Device
+ 3201 Internet Phone
+ 3202 Composite Device
+ 3203 Composite Device
+ 7200 Composite Device
+ 7210 Composite Device
+ 7250 Composite Device
+ 825c Internet Phone
+ 831c Internet Phone
+ 831d Composite Device
+ 831e Composite Device
+ b200 Composite Device
+ b201 Composite Device
+ b202 Internet Phone
+ b210 Internet Phone
+ b211 Composite Device
+ b212 Composite Device
+ b250 Composite Device
+ b251 Internet Phone
+ b252 Internet Phone
+ c200 Internet Phone
+ c201 Internet Phone
+ c202 Composite Device
+ c203 Internet Phone
+ c210 Personal PhoneGateway
+ c211 Personal PhoneGateway
+ c212 Personal PhoneGateway
+ c213 PPG Device
+ c25c Composite Device
+ c290 PPG Device
+ c291 PPG Device
+ c292 PPG Device
+ c293 Personal PhoneGateway
+ c31c Composite Device
+ c39c Personal PhoneGateway
+ c39d PPG Device
+ c39e PPG Device
+ c39f PPG Device
+ c700 Internet Phone
+ c701 Internet Phone
+ c702 Composite Device
+ c703 Internet Phone
+ c710 VoIP Combo Device
+ c711 VoIP Combo
+ c712 VoIP Combo Device
+ c713 VoIP Combo Device
+ cf00 Composite Device
+ cf01 Internet Phone
+ cf02 Internet Phone
+ cf03 Composite Device
+ d210 Personal PhoneGateway
+ d211 PPG Device
+ d212 PPG Device
+ d213 Personal PhoneGateway
+ d700 Composite Device
+ d701 Composite Device
+ d702 Internet Phone
+ d703 Composite Device
+ d710 VoIP Combo
+ d711 VoIP Combo Device
+ d712 VoIP Combo
+ d713 VoIP Combo
+ df00 Composite Device
+ df01 Composite Device
+ df02 Internet Phone
+ df03 Internet Phone
+ f200 Internet Phone
+ f201 Internet Phone
+ f202 Composite Device
+ f203 Composite Device
+ f210 Internet Phone
+ f250 Composite Device
+ f252 Internet Phone
+ f310 Internet Phone
+ f350 Composite Device
+06ea Sirius Technologies
+ 0001 NetCom Roadster II 56k
+ 0002 Roadster II 56k
+06eb PC Expert Tech. Co., Ltd
+06ef I.A.C. Geometrische Ingenieurs B.V.
+06f0 T.N.C Industrial Co., Ltd
+ de01 DualCam Video Camera
+ de02 DualCam Still Camera
+06f1 Opcode Systems, Inc.
+ a011 SonicPort
+ a021 SonicPort Optical
+06f2 Emine Technology Co.
+ 0011 KVM Switch Keyboard
+06f6 Wintrend Technology Co., Ltd
+06f7 Wailly Technology Ltd
+ 0003 USB->Din 4 Adaptor
+06f8 Guillemot Corp.
+ a300 Dual Analog Leader GamePad
+ b000 Hercules DJ Console
+ c000 Hercules Muse Pocket
+ d002 Hercules DJ Console
+ e000 HWGUSB2-54 WLAN
+ e010 HWGUSB2-54-LB
+ e020 HWGUSB2-54V2-AP
+06fa HSD S.r.L
+06fc Motorola Semiconductor Products Sector
+06fd Boston Acoustics
+ 0101 Audio Device
+ 0102 Audio Device
+ 0201 2-piece Audio Device
+06fe Gallant Computer, Inc.
+0701 Supercomal Wire & Cable SDN. BHD.
+0703 Bvtech Industry, Inc.
+0705 NKK Corp.
+0706 Ariel Corp.
+0707 Standard Microsystems Corp.
+ 0100 2202 Ethernet [klsi]
+ 0200 2202 Ethernet [pegasus]
+ 0201 EZ Connect USB Ethernet
+ ee04 SMCWUSB32 802.11b Wireless LAN Card
+ ee06 EZ-Connect 802.11g Adapter
+ ee13 EZ-Connect 802.11g Adapter
+0708 Putercom Co., Ltd
+ 047e USB-1284 BRIDGE
+0709 Silicon Systems, Ltd (SSL)
+070a Oki Electric Industry Co., Ltd
+ 4002 Bluetooth Device
+ 4003 Bluetooth Device
+070d Comoss Electronic Co., Ltd
+070e Excel Cell Electronic Co., Ltd
+0710 Connect Tech, Inc.
+ 0001 WhiteHeat (fake ID)
+ 8001 WhiteHeat
+0711 Magic Control Technology Corp.
+ 0100 Hub
+ 0180 IRXpress Infrared Device
+ 0181 IRXpress Infrared Device
+ 0200 BAY-3U1S1P Serial Port
+ 0210 MCT1S Serial Port
+ 0230 MCT-232 Serial Port
+ 0231 PS/2 Mouse Port
+ 0232 Serial On Port
+ 0240 PS/2 to USB Converter
+ 0300 BAY-3U1S1P Parallel Port
+ 0302 Parallel Port
+ 0900 SVGA Adapter
+0713 Interval Research Corp.
+0714 NewMotion, Inc.
+ 0003 ADB to USB convertor
+0717 ZNK Corp.
+0718 Imation Corp.
+ 0002 SuperDisk 120MB
+ 0003 SuperDisk 120MB (Authenticated)
+ 0060 Flash Drive
+ 0061 Flash Drive
+ 0062 Flash Drive
+ 0063 Swivel Flash Drive
+ 0064 Flash Drive
+ 0065 Flash Drive
+ 0066 Flash Drive
+ 0067 Flash Drive
+ 0068 Flash Drive
+ 0084 USB Flash Drive Mini
+0719 Tremon Enterprises Co., Ltd
+071b Domain Technologies, Inc.
+ 0002 DTI-56362-USB Digital Interface Unit
+ 0101 Audio4-USB DSP Data Acquisition Unit
+ 0201 Audio4-5410 DSP Data Acquisition Unit
+ 0301 SB-USB JTAG Emulator
+071c Xionics Document Technologies, Inc.
+071d Eicon Networks Corp.
+ 1000 Diva ISDN TA
+ 1003 Diva
+ 2000 Teledat Surf
+071e Ariston Technologies
+0723 Centillium Communications Corp.
+ 0002 Palladia 300/400 Adsl Modem
+0726 Vanguard International Semiconductor-America
+0729 Amitm
+ 1000 USC-1000 Serial Port
+072e Sunix Co., Ltd
+072f Advanced Card Systems, Ltd
+ 0001 AC1030-based SmartCard Reader
+ 0008 ACR 80 Smart Card Reader
+ 1000 PLDT Drive
+ 1001 PLDT Drive
+ 8002 AET63 BioTRUSTKey
+ 8003 ACR120
+ 8103 ACR120
+ 9000 ACR38 AC1038-based Smart Card Reader
+ 90cc ACR38 SmartCard Reader
+ 90cf ACR38 SAM Smart Card Reader
+ 90d0 PertoSmart EMV - Card Reader
+0731 Susteen, Inc.
+ 0528 SonyEricsson DCU-11 Cable
+0732 Goldfull Electronics & Telecommunications Corp.
+0733 ViewQuest Technologies, Inc.
+ 0101 Digital Video Camera
+ 0110 VQ110
+ 0401 CS330 WebCam
+ 0402 M-318B WebCam
+ 0430 Intel Pro Share WebCam
+ 0630 VQ630 Dual Mode Digital Camera(Bulk)
+ 0631 Hercules Dualpix
+ 0780 Smart Cam Deluxe(composite)
+ 1310 Epsilon 1.3/Jenoptik JD C1.3/UMAX AstraPix 470
+ 1311 Digital Dream Epsilon 1.3
+ 2211 Jenoptik
+0734 Lasat Communications A/S
+ 0001 560V Modem
+ 0002 Lasat 560V Modem
+ 043a DVS Audio
+0735 Asuscom Network
+ 2100 ISDN Adapter
+ 2101 ISDN Adapter
+ 6694 ISDN Adapter
+ c541 ISDN TA 280
+0736 Lorom Industrial Co., Ltd
+0738 Mad Catz, Inc.
+ 4507 XBox Device
+ 4516 XBox Device
+ 4520 XBox Device
+ 4526 XBox Device
+ 4536 XBox Device
+ 4540 XBox Device
+ 4556 XBox Device
+ 4566 XBox Device
+ 4576 XBox Device
+ 4586 XBox Device
+ 4588 XBox Device
+073a Chaplet Systems, Inc.
+073b Suncom Technologies
+073d Eutron S.p.a.
+ 0005 Crypto Token
+ 0007 CryptoIdentity CCID
+ 0025 SmartKey 3
+ 0c00 Pocket Reader
+ 0d00 StarSign Bio Token 3.0 EU
+073c Industrial Electronic Engineers, Inc.
+ 0305 Pole Display (PC305-3415 2 x 20 Line Display)
+ 0322 Pole Display (PC322-3415 2 x 20 Line Display)
+ 0324 Pole Display (LB324-USB 4 x 20 Line Display)
+ 0330 Pole Display (P330-3415 2 x 20 Line Display)
+ 0450 Pole Display (L450-USB Graphic Line Display)
+ 0505 Pole Display (SPC505-3415 2 x 20 Line Display)
+ 0522 Pole Display (SPC522-3415 2 x 20 Line Display)
+ 0624 Pole Display (SP324-3415 2 x 20 Line Display)
+073e NEC, Inc.
+ 0301 Game Pad
+0745 Syntech Information Co., Ltd
+0746 Onkyo Corp.
+ 5500 SE-U55 Audio Device
+0747 Labway Corp.
+0748 Strong Man Enterprise Co., Ltd
+0749 EVer Electronics Corp.
+074a Ming Fortune Industry Co., Ltd
+074b Polestar Tech. Corp.
+074c C-C-C Group PLC
+074d Micronas GmbH
+ 3553 Composite USB-Device
+ 3554 Composite USB-Device
+ 3556 Composite USB-Device
+074e Digital Stream Corp.
+ 0001 PS/2 Adapter
+ 0002 PS/2 Adapter
+0755 Aureal Semiconductor
+0757 Network Technologies, Inc.
+075b Sophisticated Circuits, Inc.
+ 0001 Kick-off! Watchdog
+0763 Midiman
+ 0115 KeyRig 25
+ 0117 Trigger Finger
+ 0119 MidAir
+ 0150 M-Audio Uno
+ 0160 M-Audio 1x1
+ 0192 M-Audio Keystation 88es
+ 0193 ProKeys 88
+ 0194 ProKeys 88sx
+ 0195 Oxygen 8 v2
+ 0196 Oxygen 49
+ 0197 Oxygen 61
+ 0198 Axiom 25
+ 0199 Axiom 49
+ 019a Axiom 61
+ 019b KeyRig 49
+ 019c KeyStudio
+ 1001 MidiSport 2x2
+ 1002 MidiSport 2x2
+ 1003 MidiSport 2x2
+ 1010 MidiSport 1x1
+ 1011 MidiSport 1x1
+ 1014 M-Audio Keystation Loader
+ 1015 M-Audio Keystation
+ 1020 Midisport 4x4
+ 1021 MidiSport 4x4
+ 1030 Midisport 8x8
+ 1031 MidiSport 8x8/s Loader
+ 1033 MidiSport 8x8/s
+ 1040 M-Audio MidiSport 2x4 Loader
+ 1041 M-Audio MidiSport 2x4
+ 2001 M Audio Quattro
+ 2002 M Audio Duo
+ 2003 M Audio AudioPhile
+ 2004 M-Audio MobilePre
+ 2006 M-Audio Transit
+ 2007 M-Audio Sonica Theater
+ 2008 M-Audio Ozone
+ 200d M-Audio OmniStudio
+ 200f M-Audio MobilePre
+ 2010 M-Audio Fast Track
+ 2013 M-Audio JamLab
+ 2015 M-Audio RunTime DFU
+ 2016 M-Audio RunTime DFU
+ 2019 M-Audio Ozone Academic
+ 201a M-Audio Micro
+ 201b M-Audio RunTime DFU
+ 201d M-Audio Producer
+ 2080 M-Audio RunTime DFU
+ 2081 M-Audio RunTime DFU
+ 2803 M-Audio Audiophile DFU
+ 2804 M-Audio MobilePre DFU
+ 2806 M-Audio Transit DFU
+ 2815 M-Audio DFU
+ 2816 M-Audio DFU
+ 281b M-Audio DFU
+ 2880 M-Audio DFU
+ 2881 M-Audio DFU
+0764 Cyber Power System, Inc.
+ 0005 Cyber Power UPS
+ 0501 CP1500 AVR UPS
+0765 X-Rite, Inc.
+0766 Jess-Link Products Co., Ltd
+0767 Tokheim Corp.
+0768 Camtel Technology Corp.
+ 0006 Camtel Technology USB TV Genie Pro FM Model TVB330
+ 0023 eHome Infrared Receiver
+0769 Surecom Technology Corp.
+ 11f2 EP-9001-g 802.11g 54M WLAN Adapter
+ 11f3 RT2570
+ 11f7 802.11g 54M WLAN Adapter
+ 31f3 RT2573
+076a Smart Technology Enablers, Inc.
+076b OmniKey AG
+ 0596 CardMan 2020
+ 1021 CardMan 1021
+ 1221 CardMan 1221
+ 1784 CardMan 6020
+ 3021 CardMan 3121
+ 3610 CardMan 3620
+ 3621 CardMan 3621
+ 3821 CardMan 3821
+ 4321 CardMan 4321
+ 5121 CardMan 5121
+ 5125 CardMan 5125
+ 6622 CardMan 6121
+ a011 CCID Smart Card Reader Keyboard
+ a021 CCID Smart Card Reader
+ a022 CardMan Smart@Link
+ c000 CardMan 3x21 CS
+ c001 CardMan 5121 CS
+076c Partner Tech
+076d Denso Corp.
+076e Kuan Tech Enterprise Co., Ltd
+076f Jhen Vei Electronic Co., Ltd
+0770 Welch Allyn, Inc - Medical Division
+0774 AmTRAN Technology Co., Ltd
+0775 Longshine Electronics Corp.
+0776 Inalways Corp.
+0777 Comda Enterprise Corp.
+0778 Volex, Inc.
+0779 Fairchild Semiconductor
+077a Sankyo Seiki Mfg. Co., Ltd
+077b Linksys
+ 08be BEFCMU10 v4 Cable Modem
+ 2219 WUSB11 V2.6 802.11b Adapter
+ 2226 USB200M 100baseTX Adapter
+077c Forward Electronics Co., Ltd
+ 0005 NEC Keyboard
+077d Griffin Technology
+ 0223 IMic Audio In/Out
+ 0405 iMate, ADB Adapter
+ 0410 PowerMate
+ 041a PowerWave
+ 07af iMic
+ 627a Radio SHARK
+077f Well Excellent & Most Corp.
+0781 SanDisk Corp.
+ 0001 SDDR-05a ImageMate CompactFlash Reader
+ 0002 SDDR-31 ImageMate II CompactFlash Reader
+ 0005 SDDR-05b (CF II) ImageMate CompactFlash Reader
+ 0100 ImageMate SDDR-12
+ 0200 SDDR-09 (SSFDC) ImageMate SmartMedia Reader [eusb]
+ 0400 SecureMate SD/MMC Reader
+ 0621 SDDR-86 Imagemate 6-in-1 Reader
+ 0720 Sansa C200 series in recovery mode
+ 0729 Sansa E200 series in recovery mode
+ 0810 SDDR-75 ImageMate CF-SM Reader
+ 0830 ImageMate CF/MMC/SD Reader
+ 1234 Cruzer Mini Flash Drive
+ 5150 SDCZ2 Cruzer Mini Flash Drive (thin)
+ 5151 Cruzer Micro 256/512MB Flash Drive
+ 5153 Cruzer USB-Flash-Drive
+ 5406 Cruzer Micro 1/4GB Flash Drive
+ 5408 Cruzer Titanium U3
+ 6100 Ultra II SD Plus 2GB
+ 7100 Cruzer Mini
+ 7101 Pen Flash
+ 7102 Cruzer Mini
+ 7103 Cruzer Mini
+ 7104 Cruzer Micro Mini 256MB Flash Drive
+ 7105 Cruzer Mini
+ 7106 Cruzer Mini
+ 7112 Cruzer Micro 128MB Flash Drive
+ 7113 Cruzer Micro 256MB Flash Drive
+ 7114 Cruzer Mini
+ 7115 Cruzer Mini
+ 7420 Sansa E200 series (mtp)
+ 7421 Sansa E200 series
+ 7432 Sansa Clip (mtp)
+ 7433 Sansa Clip (msc)
+ 7450 Sansa C250
+ 7451 Sansa C240
+ 7480 Sansa Connect
+ 7481 Sansa Connect (in recovery mode)
+ 8181 Pen Flash
+ 8183 Hi-Speed Mass Storage Device
+ 8185 SDCZ2 Cruzer Mini Flash Drive (older, thick)
+ 8888 Card Reader
+ 8889 SDDR-88 Imagemate 8-in-1 Reader
+ 8919 Card Reader
+ 8989 ImageMate 12-in-1 Reader
+ 9191 ImageMate CF
+ 9219 Card Reader
+ 9292 ImageMate CF Reader/Writer
+ 9393 ImageMate SD-MMC
+ 9595 ImageMate xD-SM
+ 9797 ImageMate MS-PRO
+ 9919 Card Reader
+ 9999 SDDR-99 5-in-1 Reader
+ a7e8 SDDR-113 MicroMate SDHC Reader
+ b2b3 SDDR-103 MobileMate SD+ Reader
+0782 Trackerball
+0783 C3PO
+ 0003 LTC31 SmartCard Reader
+0784 Vivitar, Inc.
+ 0100 Vivicam 2655
+ 1310 Vivicam 3305
+ 1688 Vivicam 3665
+ 1689 Gateway DC-M42/Labtec DC-505/Vivitar Vivicam 3705
+ 2620 AOL Photocam Plus
+ 2888 Polaroid DC700
+ 3330 Nytec ND-3200 Camera
+ 4300 Traveler D1
+ 5260 Werlisa Sport PX 100 / JVC GC-A33 Camera
+ 5300 Pretec dc530
+0785 NTT-ME
+ 0001 MN128mini-V ISDN TA
+ 0003 MN128mini-J ISDN TA
+0789 Logitec Corp.
+ 0026 LHD Device
+ 0033 DVD Multi-plus unit LDR-H443SU2
+ 0063 LDR Device
+ 0064 LDR-R Device
+ 00b3 DVD Multi-plus unit LDR-H443U2
+ 010c Realtek RTL8187 Wireless 802.11g 54Mbps Network Adapter
+078b Happ Controls, Inc.
+ 0010 Driving UGCI
+ 0020 Flying UGCI
+ 0030 Fighting UGCI
+078c GTCO/CalComp
+ 0400 Digitizer (Whiteboard)
+078e Brincom, Inc.
+0790 Pro-Image Manufacturing Co., Ltd
+0791 Copartner Wire and Cable Mfg. Corp.
+0792 Axis Communications AB
+0793 Wha Yu Industrial Co., Ltd
+0794 ABL Electronics Corp.
+0795 RealChip, Inc.
+0796 Certicom Corp.
+0797 Grandtech Semiconductor Corp.
+ 6801 Flatbed Scanner
+ 6802 InkJet Color Printer
+ 8001 SmartCam
+ 801a Typhoon StyloCam
+ 801c Meade Binoculars/Camera
+ 8901 ScanHex SX-35a
+ 8909 ScanHex SX-35b
+ 8911 ScanHex SX-35c
+0798 Optelec
+ 0001 Braille Voyager
+079b Sagem
+ 0027 USB-Serial Controller
+ 004a XG-760A
+ 004b Wi-Fi 11g adapter
+ 0056 Agfa AP1100 Photo Printer
+ 0062 XG-76NA
+079d Alfadata Computer Corp.
+ 0201 GamePort Adapter
+07a1 Digicom S.p.A.
+ d952 Palladio USB V.92 Modem
+07a2 National Technical Systems
+07a3 Onnto Corp.
+07a4 Be, Inc.
+07a6 ADMtek, Inc.
+ 07c2 AN986A Ethernet
+ 0986 AN986 Pegasus Ethernet
+ 8266 Infineon WildCard-USB Wireless LAN Adapter
+ 8511 ADM8511 Pegasus II Ethernet
+ 8513 AN8513 Ethernet
+ 8515 AN8515 Ethernet
+07aa Corega K.K.
+ 0001 Ether USB-T Ethernet [klsi]
+ 0004 FEther USB-TX Ethernet [pegasus]
+ 000c WirelessLAN USB-11
+ 000d FEther USB-TXS
+ 0012 Stick-11 802.11b Adapter
+ 0017 FEther USB2-TX
+ 001a ULUSB-11 Key
+ 002f CG-WLUSB2GNL
+ 7613 Stick-11 V2 802.11b Adapter
+ 9601 FEther USB-TXC
+07ab Freecom Technologies
+ fc01 IDE bridge
+ fc02 Cable II USB-2
+ fc03 USB2-IDE IDE bridge
+ fcf8 Freecom Classic SL Network Drive
+07af Microtech
+ 0004 SCSI-DB25 SCSI Bridge [shuttle]
+ 0005 SCSI-HD50 SCSI Bridge [shuttle]
+ 0006 CameraMate SmartMedia and CompactFlash Card Reader [eusb/shuttle]
+ fc01 Freecom USB-IDE
+07b0 Trust Technologies
+ 0001 ISDN TA
+ 0002 ISDN TA128 Plus
+ 0003 ISDN TA128 Deluxe
+ 0005 ISDN TA128 SE
+ 0006 ISDN TA128 CE
+ 0007 ISDN TA
+ 0008 ISDN TA
+07b1 IMP, Inc.
+07b2 Motorola BCS, Inc.
+ 0100 SURFboard Voice over IP Cable Modem
+ 0900 SURFboard Gateway
+ 0950 SURFboard SBG950 Gateway
+ 1000 SURFboard SBG1000 Gateway
+ 4100 SurfBoard SB4100 Cable Modem
+ 4200 SurfBoard SB4200 Cable Modem
+ 4210 SurfBoard 4210 Cable Modem
+ 4220 SURFboard SB4220 Cable Modem
+ 4500 CG4500 Communications Gateway
+ 450b CG4501 Communications Gateway
+ 450e CG4500E Communications Gateway
+ 5100 SurfBoard SB5100 Cable Modem
+ 5101 SurfBoard SB5101 Cable Modem
+ 5120 SurfBoard SB5120 Cable Modem (RNDIS)
+ 7030 Wireless Adapter WU830G
+07b3 Plustek, Inc.
+ 0001 OpticPro 1212U Scanner
+ 0003 Scanner
+ 0010 OpticPro U12 Scanner
+ 0011 OpticPro U24 Scanner
+ 0013 OpticPro UT12 Scanner
+ 0014 Scanner
+ 0015 OpticPro U24 Scanner
+ 0017 OpticPro UT12/16/24 Scanner
+ 0204 Scanner
+ 0400 OpticPro 1248U Scanner
+ 0401 OpticPro 1248U Scanner #2
+ 0403 OpticPro U16B Scanner
+ 0404 Scanner
+ 0405 A8 Namecard-s Controller
+ 0406 A8 Namecard-D Controller
+ 0410 Scanner
+ 0412 Scanner
+ 0800 OpticPro ST48 Scanner
+ 0c03 OpticPro ST64+ Scanner
+07b4 Olympus Optical Co., Ltd
+ 0100 Camedia C-2100/C-3000 Ultra Zoom Camera
+ 0102 Camedia E-10/C-220/C-50 Camera
+ 0105 Camedia C-310Z/C-700/C-750UZ/C-755/C-765UZ/C-3040/C-4000/C-5050Z/D-560/C-3020Z Zoom Camera
+ 0109 C-370Z/D-535Z/X-450
+ 0112 MAUSB-100 xD Card Reader
+ 0113 Mju 500
+ 0114 C-350Z Camera
+ 0118 Mju Mini Digital/Mju Digital 500 Camera
+ 0184 P-S100 port
+ 0203 Digital Voice Recorder DW-90
+ 0206 Digital Voice Recorder DS-330
+ 0207 Digital Voice Recorder & Camera W-10
+ 0209 Digital Voice Recorder DM-20
+ 020d Digital Voice Recorder VN-240PC
+07b5 Mega World International, Ltd
+ 0017 Joystick
+ 0213 Thrustmaster Firestorm Digital 3 Gamepad
+ 9902 GamePad
+07b6 Marubun Corp.
+07b7 TIME Interconnect, Ltd
+07b8 D-Link Corp.
+ 110c XX1
+ 1201 IEEE 802.11b Adapter
+ 200c XX2
+ 2573 Wireless LAN Card
+ 4000 DU-E10 Ethernet [klsi]
+ 4002 DU-E100 Ethernet [pegasus]
+ 4003 1/10/100 Ethernet Adapter
+ 4004 XX4
+ 4007 XX5
+ 400b XX6
+ 400c XX7
+ 401a RTL8151
+ 4102 USB 1.1 10/100M Fast Ethernet Adapter
+ 4104 XX9
+ 420a UF200 Ethernet
+ 6001 WL54
+ a001 Wireless Network Adapter
+ abc1 DU-E10 Ethernet [pegasus]
+ b000 BWU613
+ b02a AboCom Bluetooth Device
+ b02b Bluetooth dongle
+ b02c BCM92045DG-Flash with trace filter
+ b02d BCM92045DG-Flash with trace filter
+ b02e BCM92045DG-Flash with trace filter
+ b030 BCM92045DG-Flash with trace filter
+ b031 BCM92045DG-Flash with trace filter
+ b032 BCM92045DG-Flash with trace filter
+ b033 BCM92045DG-Flash with trace filter
+ b21a 802.11g Wireless Adapter
+ b21b HWU54DM
+ b21c RT2573
+ b21d RT2573
+ b21e RT2573
+ b21f WUG2700
+ d011 MP3 Player
+ e001 Mass Storage Device
+ e002 Mass Storage Device
+ e003 Mass Storage Device
+ e004 Mass Storage Device
+ e005 Mass Storage Device
+ e006 Mass Storage Device
+ e007 Mass Storage Device
+ e008 Mass Storage Device
+ e009 Mass Storage Device
+ e00a Mass Storage Device
+ e4f0 Card Reader Driver
+ f101 DSB-560 Modem [atlas]
+07bc Canon Computer Systems, Inc.
+07bd Webgear, Inc.
+07be Veridicom
+07c0 Code Mercenaries Hard- und Software GmbH
+ 1121 The Claw
+ 1500 IO-Warrior 40
+ 1501 IO-Warrior 24
+ 1502 IO-Warrior 48
+ 1503 IO-Warrior 28
+07c1 Keisokugiken
+ 0068 HKS-0200 USBDAQ
+07c4 Datafab Systems, Inc.
+ 0102 USB to LS120
+ 0103 USB to IDE
+ 1234 USB to ATAPI
+ a000 CompactFlash Card Reader
+ a001 CompactFlash & SmartMedia Card Reader [eusb]
+ a002 Disk Drive
+ a003 Datafab-based Reader
+ a004 USB to MMC Class Drive
+ a005 CompactFlash & SmartMedia Card Reader
+ a006 SmartMedia Card Reader
+ a007 Memory Stick Class Drive
+ a103 MDSM-B reader
+ a107 USB to Memory Stick (LC1) Drive
+ a109 LC1 CompactFlash & SmartMedia Card Reader
+ a10b USB to CF+MS(LC1)
+ a200 DF-UT-06 Hama MMC/SD Reader
+ a400 CompactFlash & Microdrive Reader
+ a600 Card Reader
+ ad01 Mass Storage Device
+ ae01 Mass Storage Device
+ af01 Mass Storage Device
+ b000 USB to CF(LC1)
+ b001 USB to CF+PCMCIA
+ b004 MMC/SD Reader
+ b006 USB to PCMCIA
+ b00a USB to CF+SD Drive(LC1)
+ b00b USB to Memory Stick(LC1)
+07c5 APG Cash Drawer
+07c6 ShareWave, Inc.
+07c7 Powertech Industrial Co., Ltd
+07c8 B.U.G., Inc.
+ 0202 MN128-SOHO PAL
+07c9 Allied Telesyn International
+ b100 AT-USB100
+07ca AVerMedia Technologies, Inc.
+ 0002 AVerTV PVR USB/EZMaker Pro Device
+ 0026 AVerTV
+ 1228 MPEG-2 Capture Device (M038)
+ e880 MPEG-2 Capture Device (E880)
+ e882 MPEG-2 Capture Device (E882)
+07cb Kingmax Technology, Inc.
+07cc Carry Computer Eng., Co., Ltd
+ 0000 CF Card Reader
+ 0001 Reader (UICSE)
+ 0002 Reader (UIS)
+ 0003 SM Card Reader
+ 0004 SM/CF/PCMCIA Card Reader
+ 0005 Reader (UISA2SE)
+ 0006 SM/CF/PCMCIA Card Reader
+ 0007 Reader (UISA6SE)
+ 000c SM/CF Card Reader
+ 000d SM/CF Card Reader
+ 000e Reader (UISDA)
+ 000f Reader (UICLIK)
+ 0010 Reader (UISMA)
+ 0012 Reader (UISC6SE-FLASH)
+ 0014 Litronic Fortezza Reader
+ 0030 Mass Storage (UISDMC12S)
+ 0040 Mass Storage (UISDMC13S)
+ 0100 Reader (UID)
+ 0101 Reader (UIM)
+ 0102 Reader (UISDMA)
+ 0103 Reader (UISDMC)
+ 0104 Reader (UISDM)
+ 0200 6-in-1 Card Reader
+ 0201 Mass Storage (UISDMC1S & UISDMC3S)
+ 0202 Mass Storage (UISDMC5S)
+ 0203 Mass Storage (UISMC5S)
+ 0204 Mass Storage (UIM4/5S & UIM7S)
+ 0205 Mass Storage (UIS4/5S & UIS7S)
+ 0206 Mass Storage (UISDMC10S & UISDMC11S)
+ 0207 Mass Storage (UPIDMA)
+ 0208 Mass Storage (UCFC II)
+ 0210 Mass Storage (UPIXXA)
+ 0213 Mass Storage (UPIDA)
+ 0214 Mass Storage (UPIMA)
+ 0215 Mass Storage (UPISA)
+ 0217 Mass Storage (UPISDMA)
+ 0223 Mass Storage (UCIDA)
+ 0224 Mass Storage (UCIMA)
+ 0225 Mass Storage (UIS7S)
+ 0227 Mass Storage (UCIDMA)
+ 0234 Mass Storage (UIM7S)
+ 0235 Mass Storage (UIS4S-S)
+ 0237 Velper (UISDMC4S)
+ 0300 6-in-1 Card Reader
+ 0301 6-in-1 Card Reader
+ 0303 Mass Storage (UID10W)
+ 0304 Mass Storage (UIM10W)
+ 0305 Mass Storage (UIS10W)
+ 0308 Mass Storage (UIC10W)
+ 0309 Mass Storage (UISC3W)
+ 0310 Mass Storage (UISDMA2W)
+ 0311 Mass Storage (UISDMC14W)
+ 0320 Mass Storage (UISDMC4W)
+ 0321 Mass Storage (UISDMC37W)
+ 0330 WINTERREADER Reader
+ 0350 9-in-1 Card Reader
+ 0500 Mass Storage
+ 0501 Mass Storage
+07cd Elektor
+ 0001 USBuart Serial Port
+07cf Casio Computer Co., Ltd
+ 1001 QV-8000SX/5700/3000EX Digicam; Exilim EX-M20
+ 1003 Exilim EX-S500
+ 1004 Exilim EX-Z120
+ 1011 USB-CASIO PC CAMERA
+ 2002 E-125 Cassiopeia Pocket PC
+ 3801 WMP-1 MP3-Watch
+ 4001 Label Printer KL-P1000
+ 4007 CW50 Device
+ 4104 Cw75 Device
+ 4107 CW-L300 Device
+ 4500 LV-20 Digital Camera
+ 6801 PL-40R
+ 6802 MIDI Keyboard
+07d0 Dazzle
+ 0001 Digital Video Creator I
+ 0002 Global Village VideoFX Grabber
+ 0003 Fusion Model DVC-50 Rev 1 (NTSC)
+ 0004 DVC-800 (PAL) Grabber
+ 0005 Fusion Video and Audio Ports
+ 0006 DVC 150 Loader Device
+ 0007 DVC 150
+ 0327 Fusion Digital Media Reader
+ 1001 DM-FLEX DFU Adapter
+ 1002 DMHS2 DFU Adapter
+ 1102 CF Reader/Writer
+ 1103 SD Reader/Writer
+ 1104 SM Reader/Writer
+ 1105 MS Reader/Writer
+ 1106 xD/SM Reader/Writer
+ 1202 MultiSlot Reader/Writer
+ 2000 FX2 DFU Adapter
+ 2001 eUSB CompactFlash Reader
+ 4100 Kingsun SF-620 Infrared Adapter
+ 4959 Kingsun KS-959 Infrared Adapter
+07d1 D-Link System
+ 13ec VvBus for Helium 2xx
+ 13ed VvBus for Helium 2xx
+ 13f1 DSL-302G Modem
+ 13f2 DSL-502G Router
+ 3a07 WUA-2340 Adapter
+ 3a08 predator Bootloader Download
+ 3a0d DWA-120 Wireless 108G Adapter
+ 3b01 AirPlus G DWL-G122 Wireless Adapter
+ 3b10 RangeBooster N Adapter
+ 3b11 Wireless N Adapter DWA-130
+ 3c03 DWL-G122 802.11g Adapter [ralink rt73]
+ 3c04 WUA-1340
+ 3c05 EH103 Wireless G Adapter
+ 3c07 Wireless G DWA-110 Adapter
+ 3c09 DWA-140 802.11n Adapter [ralink rt2870]
+ 5100 Remote NDIS Device
+ f101 DBT-122 Bluetooth
+ fc01 DBT-120 Bluetooth Adapter
+07d2 Aptio Products, Inc.
+07d3 Cyberdata Corp.
+07d7 GCC Technologies, Inc.
+07da Arasan Chip Systems
+07de Diamond Multimedia
+ 2820 VC500 Video Capture Dongle
+07df David Electronics Co., Ltd
+07e1 Ambient Technologies, Inc.
+ 5201 V.90 Modem
+07e2 Elmeg GmbH & Co., Ltd
+07e3 Planex Communications, Inc.
+07e4 Movado Enterprise Co., Ltd
+ 0967 SCard R/W CSR-145
+ 0968 SCard R/W CSR-145
+07e5 QPS, Inc.
+ 05c2 IDE-to-USB2.0 PCA
+ 5c01 Que! CDRW
+07e6 Allied Cable Corp.
+07e7 Mirvo Toys, Inc.
+07e8 Labsystems
+07ea Iwatsu Electric Co., Ltd
+07eb Double-H Technology Co., Ltd
+07ec Taiyo Electric Wire & Cable Co., Ltd
+07ee Torex Retail (formerly Logware)
+ 0002 Cash Drawer I/F
+07ef STSN
+ 0001 Internet Access Device
+07f6 Circuit Assembly Corp.
+07f7 Century Corp.
+ 0005 ScanLogic/Century Corporation uATA
+ 011e Century USB Disk Enclosure
+07f9 Dotop Technology, Inc.
+07fa Draytek
+ 0778 miniVigor 128 ISDN TA
+ 1012 BeWAN ADSL USB ST (grey)
+ a904 BeWAN ADSL
+ a905 BeWAN ADSL ST
+07fd Mark of the Unicorn
+ 0000 FastLane MIDI Interface
+ 0001 FastLane Quad MIDI Interface
+ 0002 MOTU Audio for 64 bit
+0801 Mag-Tek
+ 0002 Mini Swipe Reader
+0802 Mako Technologies, LLC
+0803 Zoom Telephonics, Inc.
+ 1300 V92 Faxmodem
+ 4310 Wireless-G
+ 5241 Cable Modem
+ 5551 DSL Modem
+ 9700 2986L FaxModem
+ 9800 Cable Modem
+ a312 Wireless-G
+0809 Genicom Technology, Inc.
+080a Evermuch Technology Co., Ltd
+080c Datalogic S.p.A.
+ 0300 Gryphon D120 Barcode Scanner
+ 0400 Gryphon D120 Barcode Scanner
+ 0500 Gryphon D120 Barcode Scanner
+ 0600 Gryphon M100 Barcode Scanner
+080d Teco Image Systems Co., Ltd
+ 0102 Hercules Scan@home 48
+ 0104 3.2Slim
+ 0110 UMAX AstraSlim 1200 Scanner
+0810 Personal Communication Systems, Inc.
+0813 Mattel, Inc.
+ 0001 Intel Play QX3 Microscope
+ 0002 Dual Mode Camera Plus
+081a MG Logic
+ 1000 Duo Pen Tablet
+081b Indigita Corp.
+ 0600 Storage Adapter
+ 0601 Storage Adapter
+081c Mipsys
+081e AlphaSmart, Inc.
+ df00 Handheld
+0822 Reudo Corp.
+ 2001 IRXpress Infrared Device
+0825 GC Protronics
+0826 Data Transit
+0827 BroadLogic, Inc.
+0828 Sato Corp.
+0829 DirecTV Broadband, Inc. (Telocity)
+082d Handspring
+ 0100 Visor
+ 0200 Treo
+ 0300 Treo 600
+ 0400 Handheld
+ 0500 Handheld
+ 0600 Handheld
+0830 Palm, Inc.
+ 0001 m500
+ 0002 m505
+ 0003 m515
+ 0004 Handheld
+ 0005 Handheld
+ 0006 Handheld
+ 0010 Handheld
+ 0011 Handheld
+ 0012 Handheld
+ 0013 Handheld
+ 0014 Handheld
+ 0020 i705
+ 0021 Handheld
+ 0022 Handheld
+ 0023 Handheld
+ 0024 Handheld
+ 0030 Handheld
+ 0031 Tungsten W
+ 0032 Handheld
+ 0033 Handheld
+ 0034 Handheld
+ 0040 m125
+ 0041 Handheld
+ 0042 Handheld
+ 0043 Handheld
+ 0044 Handheld
+ 0050 m130
+ 0051 Handheld
+ 0052 Handheld
+ 0053 Handheld
+ 0054 Handheld
+ 0060 Tungsten C/E/T/T2/T3 / Zire 71
+ 0061 Lifedrive / Treo 650/680 / Tunsten E2/T5/TX / Zire 21/31/72 / Z22
+ 0062 Handheld
+ 0063 Handheld
+ 0064 Handheld
+ 0070 Zire
+ 0071 Handheld
+ 0072 Handheld
+ 0080 Serial Adapter [for Palm III]
+ 0081 Handheld
+ 0082 Handheld
+0832 Kouwell Electronics Corp.
+ 5850 Cable
+0833 Sourcenext Corp.
+ 012e KeikaiDenwa 8 with charger
+ 039f KeikaiDenwa 8
+0835 Action Star Enterprise Co., Ltd
+0839 Samsung Techwin Co., Ltd
+ 0005 Digimax Camera
+ 0008 Digimax 230 Camera
+ 0009 Digimax 340
+ 000a Digimax 410
+ 000e Digimax 360
+ 0010 Digimax 300
+ 1003 Digimax 210SE
+ 1005 Digimax 220
+ 1009 Digimax V4
+ 1012 6500 Document Camera
+ 1058 S730 Camera
+ 1542 Digimax 50 Duo
+ 3000 Digimax 35 MP3
+083a Accton Technology Corp.
+ 1046 10/100 Ethernet [pegasus]
+ 1060 HomeLine Adapter
+ 1f4d SMC8013WG Broadband Remote NDIS Device
+ 3046 10/100 Series Adapter
+ 3060 1/10/100 Adapter
+ 3501 2664W
+ 3502 WN3501D Wireless Adapter
+ 3503 T-Sinus 111 Wireless Adapter
+ 4501 T-Sinus 154data
+ 4505 SMCWUSB-G
+ 5046 SpeedStream 10/100 Ethernet [pegasus]
+ 5501 Wireless Adapter 11g
+ 6500 Cable Modem
+ 6618 802.11n Wireless Adapter
+ 7522 802.11N Wireless Adapter
+ a618 SMC EZ Connect N Draft 11n Wireless Adapter
+ b004 CPWUE001 USB/Ethernet Adapter
+ b522 EZ Connect N Draft 11n Wireless USB2.0 Adapter
+ bb01 BlueExpert Bluetooth Device
+ c003 802.11b Wireless Adapter
+ c501 Zoom Wireless-G
+ c561 802.11a/g Wireless Adapter
+ e501 ZD1211B
+ f501 802.11g Wireless Adapter
+ f502 802.11g Wireless Adapter
+083f Global Village
+ b100 TelePort V.90 Fax/Modem
+0840 Argosy Research, Inc.
+ 0060 Storage Adapter Bridge Module
+0841 Rioport.com, Inc.
+ 0001 Rio 500
+0844 Welland Industrial Co., Ltd
+0846 NetGear, Inc.
+ 1001 EA101 Ethernet [klsi]
+ 1002 Ethernet
+ 1020 Ethernet 10/100, USB1.1
+ 1040 USB 2.0 Ethernet
+ 4110 MA111 WiFi (v1)
+ 4200 WG121 WiFi (v1)
+ 4210 WG121 WiFi (v2)
+ 4220 WG111 WiFi (v1)
+ 4230 MA111 WiFi (v2)
+ 4240 WG111 WiFi (v2)
+ 4260 WG111v3 802.11g Adapter [realtek RTL8187B]
+ 4300 WG111U
+ 4301 WG111U (no firmware)
+ 6a00 WG111 WiFi (v2)
+ 7100 WN121T Wireless Adapter
+ 9000 RangeMax NEXT Wireless-N Adapter WN111
+ a001 PA101 Phoneline10X Adapter
+084d Minton Optic Industry Co., Inc.
+ 0001 Jenoptik JD800i
+ 0003 S-Cam F5 Digital Camera
+ 0011 Argus DC3500 Digital Camera
+ 0014 Praktica DC 32
+ 0019 Praktica DPix3000
+ 0025 Praktica DC 60
+ 1001 ScanHex SX-35d
+084e KB Gear
+ 0001 KBGear JamCam
+ 1002 Pablo Tablet
+084f Empeg
+ 0001 Empeg-Car Mark I/II Player
+0850 Fast Point Technologies, Inc.
+0851 Macronix International Co., Ltd
+ 1542 SiPix Blink
+ 1543 Maxell WS30 Slim Digital Camera
+ a168 MXIC
+0852 CSEM
+0853 Topre Corporation
+ 0100 HHKB Professional
+0854 ActiveWire, Inc.
+ 0100 I/O Board
+ 0101 I/O Board, rev1
+0856 B&B Electronics
+ ac01 uLinks USOTL4 RS422/485 Adapter
+0858 Hitachi Maxell, Ltd
+ 3102 Bluetooth Device
+ ffff Maxell module with BlueCore in DFU mode
+0859 Minolta Systems Laboratory, Inc.
+085a Xircom
+ 0001 Portstation Dual Serial Port
+ 0003 Portstation Paraller Port
+ 0008 Ethernet
+ 0009 Ethernet
+ 000b Portstation Dual PS/2 Port
+ 0021 1 port to Serial Converter
+ 0022 Parallel Port
+ 0023 2 port to Serial Converter
+ 0024 Parallel Port
+ 0027 1 port to Serial Converter
+ 0028 PortGear to SCSI Converter
+ 0032 PortStation SCSI Module
+ 003c Bluetooth Adapter
+ 0299 Colorvision, Inc. Monitor Spyder
+ 8021 1 port to Serial
+ 8023 2 port to Serial
+ 8027 PGSDB9 Serial Port
+085c ColorVision, Inc.
+ 0200 Monitor Spyder
+0862 Teletrol Systems, Inc.
+0863 Filanet Corp.
+0864 NetGear, Inc.
+ 4100 MA101 802.11b Adapter
+ 4102 MA101 802.11b Adapter
+0867 Data Translation, Inc.
+ 9812 ECON Data acquisition unit
+ 9816 DT9816 ECON data acquisition module
+ 9836 DT9836 data acquisition card
+086a Emagic Soft- und Hardware GmbH
+ 0001 Unitor8
+ 0002 AMT8
+ 0003 MT4
+086c DeTeWe - Deutsche Telephonwerke AG & Co.
+ 1001 Eumex 504PC ISDN TA
+ 1002 Eumex 504PC (FlashLoad)
+ 1003 TA33 ISDN TA
+ 1004 TA33 (FlashLoad)
+ 1005 Eumex 604PC HomeNet
+ 1006 Eumex 604PC HomeNet (FlashLoad)
+ 1007 Eumex 704PC DSL
+ 1008 Eumex 704PC DSL (FlashLoad)
+ 1009 Eumex 724PC DSL
+ 100a Eumex 724PC DSL (FlashLoad)
+ 100b OpenCom 30
+ 100c OpenCom 30 (FlashLoad)
+ 100d BeeTel Home 100
+ 100e BeeTel Home 100 (FlashLoad)
+ 1011 USB2DECT
+ 1012 USB2DECT (FlashLoad)
+ 1013 Eumex 704PC LAN
+ 1014 Eumex 704PC LAN (FlashLoad)
+ 1021 OpenCom 40
+ 1022 OpenCom 40 (FlashLoad)
+ 1023 OpenCom 45
+ 1024 OpenCom 45 (FlashLoad)
+ 1025 Sinus 61 data
+ 1029 dect BOX
+ 102c Eumex 604PC HomeNet [FlashLoad]
+ 1030 Eumex 704PC DSL [FlashLoad]
+ 1032 OpenCom 40 [FlashLoad]
+ 1033 OpenCom 30 plus
+ 1034 OpenCom 30 plus (FlashLoad)
+ 1055 Eumex 220 ISDN TA
+ 2000 OpenCom 1000
+086e System TALKS, Inc.
+ 1920 SGC-X2UL
+086f MEC IMEX, Inc.
+0870 Metricom
+ 0001 Ricochet GS
+0871 SanDisk, Inc.
+ 0001 SDDR-01 Compact Flash Reader
+ 0002 SDDR-31 Compact Flash Reader
+ 0005 SDDR-05 Compact Flash Reader
+0873 Xpeed, Inc.
+0874 A-Tec Subsystem, Inc.
+0879 Comtrol Corp.
+087c Adesso/Kbtek America, Inc.
+087d Jaton Corp.
+ 5704 Ethernet
+087e Fujitsu Computer Products of America
+087f Virtual IP Group, Inc.
+0880 APT Technologies, Inc.
+0883 Recording Industry Association of America (RIAA)
+0885 Boca Research, Inc.
+0886 XAC Automation Corp.
+ 0630 Intel PC Camera CS630
+0887 Hannstar Electronics Corp.
+088b MassWorks, Inc.
+ 4944 MassWorks ID-75 TouchScreen
+0892 DioGraphy, Inc.
+ 0101 Smartdio Reader/Writer
+089c United Technologies Research Cntr.
+089d Icron Technologies Corp.
+089e NST Co., Ltd
+089f Primex Aerospace Co.
+08a5 e9, Inc.
+08a8 Andrea Electronics
+08ae Macally (Mace Group, Inc.)
+08b4 Sorenson Vision, Inc.
+08b8 J. Gordon Electronic Design, Inc.
+ 01f4 USBSIMM1
+08b9 RadioShack Corp. (Tandy)
+08bb Texas Instruments Japan
+ 2702 Speakers
+ 2900 PCM2900 Audio Codec
+ 2904 PCM2904 Audio Codec
+08bd Citizen Watch Co., Ltd
+ 1100 X1-USB Floppy
+08c3 Precise Biometrics
+ 0001 100 SC
+ 0002 100 A
+ 0003 100 SC BioKeyboard
+ 0006 100 A BioKeyboard
+ 0100 100 MC ISP
+ 0101 100 MC FingerPrint and SmartCard Reader
+ 0300 100 AX
+ 0400 100 SC
+ 0401 150 MC
+ 0402 200 MC FingerPrint and SmartCard Reader
+ 0404 100 SC Upgrade
+ 0405 150 MC Upgrade
+ 0406 100 MC Upgrade
+08c4 Proxim, Inc.
+ 02f2 Farallon Home Phoneline Adapter
+08c7 Key Nice Enterprise Co., Ltd
+08c8 2Wire, Inc.
+08c9 Nippon Telegraph and Telephone Corp.
+08ca Aiptek International, Inc.
+ 0010 Tablet
+ 0020 APT-6000U Tablet
+ 0021 APT-2 Tablet
+ 0022 Tablet
+ 0023 Tablet
+ 0024 Tablet
+ 0100 Pen Drive
+ 0102 DualCam
+ 0103 Pocket DV Digital Camera
+ 0104 Pocket DVII
+ 0105 Mega DV(Disk)
+ 0106 Pocket DV3100+
+ 0107 Pocket DV 3100
+ 0109 Nisis DV4 Digital Camera
+ 010a Trust 738AV LCD PV Mass Storage
+ 0111 PenCam VGA Plus
+ 2008 Mini PenCam 2
+ 2010 Pocket CAM 3 Mega (webcam)
+ 2011 Pocket CAM 3 Mega (storage)
+ 2018 Pencam SD 2
+ 2024 Pocket DV3500
+ 2042 DV 5100M Composite Device
+ 2043 DV 5100M(Disk)
+08cd Jue Hsun Ind. Corp.
+08ce Long Well Electronics Corp.
+08cf Productivity Enhancement Products
+08d1 smartBridges, Inc.
+ 0001 smartNIC Ethernet [catc]
+ 0003 smartNIC 2 PnP Ethernet
+08d3 Virtual Ink
+08d4 Fujitsu Siemens Computers
+ 0009 SCR SmartCard Reader
+08d9 Increment P Corp.
+08dd Billionton Systems, Inc.
+ 0112 Wireless LAN Adapter
+ 0113 Wireless LAN Adapter
+ 0986 USB-100N Ethernet [pegasus]
+ 0987 USBLP-100 HomePNA Ethernet [pegasus]
+ 0988 USBEL-100 Ethernet [pegasus]
+ 1986 10/100 LAN Adapter
+ 2103 DVB-T TV-Tuner Card-R
+ 8511 USBE-100 Ethernet [pegasus2]
+ 90ff USB2AR Ethernet
+08de ???
+ 7a01 802.11b Adapter
+08df Spyrus, Inc.
+ 0001 Rosetta Token V1
+ 0002 Rosetta Token V2
+ 0003 Rosetta Token V3
+ 0a00 Lynks Interface
+08e3 Olitec, Inc.
+ 0002 USB-RS232 Bridge
+ 0100 Interface ADSL
+ 0101 Interface ADSL
+ 0102 ADSL
+ 0301 RNIS
+08e4 Pioneer Corp.
+08e5 Litronic
+08e6 Gemplus
+ 0001 GemPC-Touch 430
+ 0430 GemPC430 SmartCard Reader
+ 0432 GemPC432 SmartCard Reader
+ 0435 GemPC435 SmartCard Reader
+ 0437 GemPC433 SL SmartCard Reader
+ 1359 UA SECURE STORAGE TOKEN
+ 2202 Gem e-Seal Pro Token
+ 3437 GemPC Twin SmartCard Reader
+ 3438 GemPC Key SmartCard Reader
+ 3478 PinPad Smart Card Reader
+ 4433 GemPC433-Swap
+ 5501 GemProx-PU Contactless Smart Card Reader
+ ace0 UA HYBRID TOKEN
+08e7 Pan-International Wire & Cable
+08e8 Integrated Memory Logic
+08e9 Extended Systems, Inc.
+ 0100 XTNDAccess IrDA Dongle
+08ea Ericsson, Inc., Blue Ridge Labs
+ 00c9 ADSL Modem HM120dp Loader
+ 00ca ADSL WAN Modem HM120dp
+ 00ce HM230d Virtual Bus for Helium
+ abba USB Driver for Bluetooth Wireless Technology
+ abbb Bluetooth Device in DFU State
+08ec M-Systems Flash Disk Pioneers
+ 0001 TravelDrive 2C
+ 0002 TravelDrive 2C
+ 0005 TravelDrive 2C
+ 0008 TravelDrive 2C
+ 0010 DiskOnKey
+ 0011 DiskOnKey
+ 0012 TravelDrive 2C
+ 0014 TravelDrive 2C
+ 0015 Kingston DataTraveler ELITE
+ 0016 Kingston DataTraveler U3
+ 0020 TravelDrive
+ 0021 TravelDrive
+ 0022 TravelDrive
+ 0023 TravelDrive
+ 0024 TravelDrive
+ 0025 TravelDrive
+ 0026 TravelDrive
+ 0027 TravelDrive
+ 0028 TravelDrive
+ 0029 TravelDrive
+ 0030 TravelDrive
+ 0822 TravelDrive 2C
+ 0832 Hi-Speed Mass Storage Device
+ 0998 Kingston Data Traveler2.0 Disk Driver
+ 0999 Kingston Data Traveler2.0 Disk Driver
+ 1000 TravelDrive 2C
+ 2000 TravelDrive 2C
+ 2038 TravelDrive
+ 2039 TravelDrive
+ 204a TravelDrive
+ 204b TravelDrive
+08ee CCSI/Hesso
+08f0 Corex Technologies
+08f1 CTI Electronics Corp.
+08f5 SysTec Co., Ltd
+08f6 Logic 3 International, Ltd
+08f7 Vernier
+ 0001 LabPro
+ 0002 EasyTemp
+08f8 Keen Top International Enterprise Co., Ltd
+08f9 Wipro Technologies
+08fa Caere
+08fb Socket Communications
+08fc Sicon Cable Technology Co., Ltd
+08fd Digianswer A/S
+ 0001 Bluetooth Device
+08ff AuthenTec, Inc.
+ 1600 AES1600
+ 1610 AES1600
+ 2500 AES2501
+ 2501 AES2501
+ 2502 AES2501
+ 2503 AES2501
+ 2504 AES2501
+ 2505 AES2501
+ 2506 AES2501
+ 2507 AES2501
+ 2508 AES2501
+ 2509 AES2501
+ 250a AES2501
+ 250b AES2501
+ 250c AES2501
+ 250d AES2501
+ 250e AES2501
+ 250f AES2501
+ 2510 AES2510
+ 2580 AES2501 Fingerprint Sensor
+ 2588 AES2501
+ 2589 AES2501
+ 258a AES2501
+ 258b AES2501
+ 258c AES2501
+ 258d AES2501
+ 258e AES2501
+ 258f AES2501
+ 3400 AES3400 TruePrint Sensor
+ 3401 AES3400 Sensor
+ 3402 AES3400 Sensor
+ 3403 AES3400 Sensor
+ 3404 AES3400 TruePrint Sensor
+ 3405 AES3400 TruePrint Sensor
+ 3406 AES3400 TruePrint Sensor
+ 3407 AES3400 TruePrint Sensor
+ 4902 BioMV with TruePrint AES3500
+ 4903 BioMV with TruePrint AES3400
+ 5500 AES4000
+ 5501 AES4000 TruePrint Sensor
+ 5503 AES4000 TruePrint Sensor
+ 5505 AES4000 TruePrint Sensor
+ 5507 AES4000 TruePrint Sensor
+ 55ff AES4000 TruePrint Sensor.
+ 5700 AES3500 Fingerprint Reader
+ 5701 AES3500 TruePrint Sensor
+ 5702 AES3500 TruePrint Sensor
+ 5703 AES3500 TruePrint Sensor
+ 5704 AES3500-BZ TruePrint Sensor
+ 5705 AES3500-BZ TruePrint Sensor
+ 5706 AES3500-BZ TruePrint Sensor
+ 5707 AES3500-BZ TruePrint Sensor
+ 5710 AES3500 TruePrint Sensor
+ 5711 AES3500 TruePrint Sensor
+ 5712 AES3500 TruePrint Sensor
+ 5713 AES3500 TruePrint Sensor
+ 5714 AES3500-BZ TruePrint Sensor
+ 5715 AES3500-BZ TruePrint Sensor
+ 5716 AES3500-BZ TruePrint Sensor
+ 5717 AES3500-BZ TruePrint Sensor
+ 5730 AES3500 TruePrint Sensor
+ 5731 AES3500 TruePrint Sensor
+ 5732 AES3500 TruePrint Sensor
+ 5733 AES3500 TruePrint Sensor
+ 5734 AES3500-BZ TruePrint Sensor
+ 5735 AES3500-BZ TruePrint Sensor
+ 5736 AES3500-BZ TruePrint Sensor
+ 5737 AES3500-BZ TruePrint Sensor
+ afe3 FingerLoc Sensor Module (Anchor)
+ afe4 FingerLoc Sensor Module (Anchor)
+ afe5 FingerLoc Sensor Module (Anchor)
+ afe6 FingerLoc Sensor Module (Anchor)
+ fffd AES2510 Sensor (USB Emulator)
+ ffff Sensor (Emulator)
+0900 Pinnacle Systems, Inc.
+0901 VST Technologies
+ 0001 Hard Drive Adapter (TPP)
+ 0002 SigmaDrive Adapter (TPP)
+0906 Faraday Technology Corp.
+0909 Audio-Technica Corp.
+090a Trumpion Microelectronics, Inc.
+ 1001 T33520 USB Flash Card Controller
+ 1100 Comotron C3310 MP3 player
+ 1200 MP3 player
+ 1540 Digitex Container Flash Disk
+090b Neurosmith
+090c Feiya Technology Corp.
+ 1000 Memory Bar
+ 1132 5-in-1 Card Reader
+090d Multiport Computer Vertriebs GmbH
+090e Shining Technology, Inc.
+090f Fujitsu Devices, Inc.
+0910 Alation Systems, Inc.
+0911 Philips Speech Processing
+ 2512 SpeechMike Pro
+0912 Voquette, Inc.
+0915 GlobeSpan, Inc.
+ 0001 DSL Modem
+ 0002 ADSL ATM Modem
+ 0005 LAN Modem
+ 2000 802.11 Adapter
+ 2002 802.11 Adapter
+ 8000 ADSL LAN Modem
+ 8005 DSL-302G Modem
+ 8101 ADSL WAN Modem
+ 8102 DSL-200 ADSL Modem
+ 8103 DSL-200 ADSL Modem
+ 8104 DSL-200 Modem
+ 8400 DSL Modem
+ 8401 DSL Modem
+ 8402 DSL Modem
+ 8500 DSL Modem
+ 8501 DSL Modem
+0917 SmartDisk Corp.
+ 0001 eFilm Reader-11 SM/CF
+ 0002 eFilm Reader-11 SM
+ 0003 eFilm Reader-11 CF
+ 0200 FireFly
+ 0201 FireLite
+ 0202 STORAGE ADAPTER (FirePower)
+ 0204 FlashTrax Storage
+ 0205 STORAGE ADAPTER (CrossFire)
+ 0206 FireFly 20G HDD
+ 0207 FireLite
+ 020f STORAGE ADAPTER (FireLite)
+ da01 eFilm Reader-11 Test
+ ffff eFilm Reader-11 (Class/PDR)
+0919 Tiger Electronics
+ 0100 Fast Flicks Digital Camera
+091e Garmin International
+ 0003 GPSmap (various models)
+ 0004 Garmin iQue 3600
+ 0200 Data Card Programmer (install)
+ 1200 Data Card Programmer
+0920 Echelon Co.
+ 7500 Network Interface
+0921 GoHubs, Inc.
+ 1001 GoCOM232 Serial
+0922 Dymo-CoStar Corp.
+ 0007 LabelWriter 330
+ 0009 LabelWriter 310
+0923 IC Media Corp.
+ 010f SIIG MobileCam
+0924 Xerox
+ 23dd DocuPrint M760 (X760_USB)
+ 3d5b Phaser 6115MFP TWAIN Scanner
+ 420f WorkCentre PE220 Series
+ 421f M20 Scanner
+ 423b Printing Support
+ ffef WorkCenter M15
+ fffb DocuPrint M750 (X750_USB)
+0925 Lakeview Research
+ 8101 Phidgets, Inc., 1-Motor PhidgetServo v2.0
+ 8104 Phidgets, Inc., 4-Motor PhidgetServo v2.0
+ 8800 WiseGroup Ltd, MP-8800 Quad Joypad
+ 8866 WiseGroup Ltd, MP-8866 Dual Joypad
+0927 Summus, Ltd
+0928 Oxford Semiconductor, Ltd
+0929 American Biometric Co.
+092a Toshiba Information & Industrial Sys. And Services
+092b Sena Technologies, Inc.
+092f Northern Embedded Science/CAVNEX
+ 0004 JTAG-4
+ 0005 JTAG-5
+0930 Toshiba Corp.
+ 0009 Gigabeat F/X (HDD audio player)
+ 000c Gigabeat F (mtp)
+ 0010 Gigabeat S (mtp)
+ 0301 PCX1100U Cable Modem (WDM)
+ 0302 PCX2000 Cable Modem (WDM)
+ 0305 Cable Modem PCX3000
+ 0307 Cable Modem PCX2500
+ 0308 PCX2200 Cable Modem (WDM)
+ 0309 PCX5000 Cable Modem (WDM)
+ 030b Cable Modem PCX2600
+ 0501 Bluetooth Controller
+ 0502 Integrated Bluetooth
+ 0503 Bluetooth Controller
+ 0505 Integrated Bluetooth
+ 0506 Integrated Bluetooth
+ 0507 Bluetooth Adapter
+ 0508 Integrated Bluetooth HCI
+ 0509 BT EDR Dongle
+ 0706 PocketPC e740
+ 0707 Pocket PC e330 Series
+ 0708 Pocket PC e350 Series
+ 0709 Pocket PC e750 Series
+ 070a Pocket PC e400 Series
+ 070b Pocket PC e800 Series
+ 1300 Wireless Broadband (CDMA EV-DO) SM-Bus Minicard Status Port
+ 1301 Wireless Broadband (CDMA EV-DO) Minicard Status Port
+ 1302 Wireless Broadband (3G HSDPA) SM-Bus Minicard Status Port
+ 1303 Wireless Broadband (3G HSDPA) Minicard Status Port
+ 1308 Broadband (3G HSDPA) SM-Bus Minicard Diagnostics Port
+ 642f TravelDrive
+ 6506 TravelDrive 2C
+ 6507 TravelDrive 2C
+ 6508 TravelDrive 2C
+ 6509 TravelDrive 2C
+ 6510 TravelDrive 2C
+ 6517 TravelDrive 2C
+ 6518 TravelDrive 2C
+ 6519 Kingston DataTraveler 2.0 USB Stick
+ 651a TravelDrive 2C
+ 651b TravelDrive 2C
+ 651c TravelDrive 2C
+ 651d TravelDrive 2C
+ 651e TravelDrive 2C
+ 651f TravelDrive 2C
+ 6520 TravelDrive 2C
+ 6521 TravelDrive 2C
+ 6522 TravelDrive 2C
+ 6523 TravelDrive
+ 6524 TravelDrive
+ 6525 TravelDrive
+ 6526 TravelDrive
+ 6527 TravelDrive
+ 6528 TravelDrive
+ 6529 TravelDrive
+ 652a TravelDrive
+ 652b TravelDrive
+ 652c TravelDrive
+ 652d TravelDrive
+ 652f TravelDrive
+ 6530 TravelDrive
+ 6531 TravelDrive
+ 6532 256M USB Stick
+ 6533 512M USB Stick
+ 6534 TravelDrive
+ 653c Kingston DataTraveler 2.0 USB Stick (512M)
+ 653d Kingston DataTraveler 2.0 USB Stick (1GB)
+ 653e USB Flash Memory
+ 6540 TransMemory USB Flash Memory
+0931 Harmonic Data Systems, Ltd
+0932 Crescentec Corp.
+ 0300 VideoAdvantage
+ 0302 Syntek DC-112X
+ 0320 VideoAdvantage
+ 1100 Video Enhamcement Device
+ 1112 Veo Web Camera
+ a311 Video Enhancement Device
+0933 Quantum Corp.
+0934 Netcom Systems
+0939 Lumberg, Inc.
+093a Pixart Imaging, Inc.
+ 0007 CMOS 100K-R Rev. 1.90
+ 010e Digital camera, CD302N/Elta Medi@ digi-cam/HE-501A
+ 010f Argus DC-1610/DC-1620/Emprex PCD3600/Philips P44417B keychain camera/Precision Mini,Model HA513A/Vivitar Vivicam 55
+ 2460 Q-TEC WEBCAM 100
+ 2468 Cammaestro 2.5DU/X-EYE/Orite SC-120/ICGear TravelCam/Easy Snap Snake Eye WebCam
+ 2470 SoC PC-Camera
+ 2471 SoC PC-Camera
+ 2500 USB Optical Mouse
+ 2600 Typhoon Easycam USB 330K (newer)/Typhoon Easycam USB 2.0 VGA 1.3M/Sansun SN-508
+ 2601 SPC 610NC Laptop Camera
+093b Plextor Corp.
+ 0010 Storage Adapter
+ 0011 PlexWriter 40/12/40U
+ 0042 PX-712UF DVD RW
+ a002 ConvertX M402U XLOADER
+ a003 ConvertX AV100U A/V Capture Audio
+ a004 ConvertX TV402U XLOADER
+ a005 KWorld EMP Audio Device
+ a102 ConvertX M402U A/V Capture
+ a104 ConvertX PX-TV402U/NA
+093c Intrepid Control Systems, Inc.
+ 0601 ValueCAN
+ 0701 NeoVI Blue vehicle bus interface
+093d InnoSync, Inc.
+093e J.S.T. Mfg. Co., Ltd
+093f Olympia Telecom Vertriebs GmbH
+0940 Japan Storage Battery Co., Ltd
+0941 Photobit Corp.
+0942 i2Go.com, LLC
+0943 HCL Technologies India Private, Ltd
+0944 KORG, Inc.
+0945 Pasco Scientific
+0948 Kronauer music in digital
+ 0301 USB Pro (24/48)
+ 0302 USB Pro (24/96 playback)
+ 0303 USB Pro (24/96 record)
+ 0304 USB Pro (16/48)
+ 1105 USB One
+094b Linkup Systems Corp.
+094d Cable Television Laboratories
+094f Yano
+ 0101 U640MO-03
+ 05fc METALWEAR-HDD
+0951 Kingston Technology
+ 0008 Ethernet
+ 000a KNU101TX 100baseTX Ethernet
+ 1600 Data Traveler II Pen Drive
+ 1601 Data Traveler II+ Pen Drive
+ 1602 Data Traveler Mini
+ 1603 Data Traveler 1GB/2GB Pen Drive
+0954 RPM Systems Corp.
+0955 NVidia Corp.
+0956 BSquare Corp.
+0957 Agilent Technologies, Inc.
+ 0200 E-Video DC-350 Camera
+ 0202 E-Video DC-350 Camera
+0958 CompuLink Research, Inc.
+0959 Cologne Chip AG
+ 2bd0 Intelligent ISDN (Ver. 3.60.04)
+095a Portsmith
+ 3003 Express Ethernet
+095b Medialogic Corp.
+095c K-Tec Electronics
+095d Polycom, Inc.
+ 0001 Polycom ViaVideo
+0967 Acer (??)
+ 0204 WarpLink 802.11b Adapter
+0968 Catalyst Enterprises, Inc.
+096e Feitian Technologies, Inc.
+ 0802 ePass2000 (G&D STARCOS SPK 2.4)
+0971 Gretag-Macbeth AG
+0973 Schlumberger
+ 0001 e-gate Smart Card
+0974 Datagraphix, a business unit of Anacomp
+0975 OL'E Communications, Inc.
+0976 Adirondack Wire & Cable
+0977 Lightsurf Technologies
+0978 Beckhoff GmbH
+0979 Jeilin Technology Corp., Ltd
+ 0224 JL2005A Toy Camera
+ 0226 JL2005A Toy Camera
+097a Minds At Work LLC
+ 0001 Digital Wallet
+097b Knudsen Engineering, Ltd
+097c Marunix Co., Ltd
+097d Rosun Technologies, Inc.
+097f Barun Electronics Co., Ltd
+0981 Oak Technology, Ltd
+0984 Apricorn
+ 0200 Hard Drive Storage (TPP)
+0985 cab Produkttechnik GmbH & Co KG
+ 00a3 A3/200 or A3/300 Label Printer
+0986 Matsushita Electric Works, Ltd.
+098c Vitana Corp.
+098d INDesign
+098e Integrated Intellectual Property, Inc.
+098f Kenwood TMI Corp.
+0993 Gemstar eBook Group, Ltd
+ 0001 REB1100 eBook Reader
+ 0002 eBook
+0996 Integrated Telecom Express, Inc.
+099a Zippy Technology Corp.
+ 610c EL-610 Super Mini Electron luminescent Keyboard
+09a3 PairGain Technologies
+09a4 Contech Research, Inc.
+09a5 VCON Telecommunications
+09a6 Poinchips
+ 8001 Mass Storage Device
+09a7 Data Transmission Network Corp.
+09a8 Lin Shiung Enterprise Co., Ltd
+09a9 Smart Card Technologies Co., Ltd
+09aa Intersil Corp.
+ 1000 Prism GT 802.11b/g Adapter
+ 3642 Prism 2.x 802.11b Adapter
+09ab Japan Cash Machine Co., Ltd.
+09ae Tripp Lite
+09b2 Franklin Electronic Publishers, Inc.
+ 0001 eBookman Palm Computer
+09b3 Altius Solutions, Inc.
+09b4 MDS Telephone Systems
+09b5 Celltrix Technology Co., Ltd
+09bc Grundig
+ 0002 MPaxx MP150 MP3 Player
+09be MySmart.Com
+ 0001 MySmartPad
+09bf Auerswald GmbH & Co. KG
+ 00c0 COMpact 2104 ISDN PBX
+ 00db COMpact 4410/2206 ISDN ISDN
+ 00f1 COMfort System Telephones
+09c1 Arris Interactive LLC
+ 1337 TOUCHSTONE DEVICE
+09c2 Nisca Corp.
+09c3 ActivCard, Inc.
+ 0007 Reader V2
+ 0008 SmartCard Reader
+09c4 ACTiSYS Corp.
+ 0011 ACT-IR2000U IrDA Dongle
+09c5 Memory Corp.
+09cc Workbit Corp.
+ 0404 BAFO USB-ATA/ATAPI Bridge Controller
+09cd Psion Dacom Home Networks, Ltd
+09ce City Electronics, Ltd
+09cf Electronics Testing Center, Taiwan
+09d1 NeoMagic, Inc.
+09d2 Vreelin Engineering, Inc.
+09d3 Com One
+ 0001 ISDN TA
+09d7 Novatel Wireless
+ 0100 NovAtel FlexPack GPS receiver
+09d9 KRF Tech, Ltd
+09da A4 Tech Co., Ltd
+ 0006 Optical Mouse WOP-35 / Trust 450L Optical Mouse
+ 000a Port Mouse
+ 0018 Trust Human Interface Device
+ 001a Wireless Mouse & RXM-15 Receiver
+ 002a Wireless Optical Mouse NB-30
+09db Measurement Computing Corp.
+ 0075 MiniLab 1008
+ 0076 PMD-1024
+ 007a PMD-1208LS
+ 0081 USB-1616FS
+ 0088 USB-1616FS internal hub
+09dc Aimex Corp.
+09dd Fellowes, Inc.
+09df Addonics Technologies Corp.
+09e1 Intellon Corp.
+ 5121 MicroLink dLAN
+09e5 Jo-Dan International, Inc.
+09e6 Silutia, Inc.
+09e7 Real 3D, Inc.
+09e8 AKAI Professional M.I. Corp.
+09e9 Chen-Source, Inc.
+09eb IM Networks, Inc.
+ 4331 iRhythm Tuner Remote
+09ef Xitel
+ 0101 MD-Port DG2 MiniDisc Interface
+09f5 AresCom
+ 0168 Network Adapter
+ 0188 LAN Adapter
+ 0850 Adapter
+09f6 RocketChips, Inc.
+09f7 Edu-Science (H.K.), Ltd
+09f8 SoftConnex Technologies, Inc.
+09f9 Bay Associates
+09fa Mtek Vision
+09fb Altera
+09ff Gain Technology Corp.
+0a00 Liquid Audio
+0a01 ViA, Inc.
+0a07 Ontrak Control Systems Inc.
+ 0064 ADU100 Data Acquisition Interface
+ 00c8 ADU200 Relay I/O Interface
+ 00d0 ADU208 Data Acquisition Interface
+0a0b Cybex Computer Products Co.
+0a11 Xentec, Inc.
+0a12 Cambridge Silicon Radio, Ltd
+ 0001 Bluetooth Dongle (HCI mode)
+ 0002 Frontline Test Equipment Bluetooth Device
+ 0003 Nanosira
+ 0004 Nanosira WHQL Reference Radio
+ 0005 Nanosira-Multimedia
+ 0006 Nanosira-Multimedia WHQL Reference Radio
+ 0007 Nanosira3-ROM
+ 0008 Nanosira3-ROM
+ 0009 Nanosira4-EDR WHQL Reference Radio
+ 000a Nanosira4-EDR-ROM
+ 000b Nanosira5-ROM
+ 0043 Bluetooth Device
+ 0100 Casira with BlueCore2-External Module
+ 0101 Casira with BlueCore2-Flash Module
+ 0102 Casira with BlueCore3-Multimedia Module
+ 0103 Casira with BlueCore3-Flash Module
+ 0104 Casira with BlueCore4-External Module
+ 0105 Casira with BlueCore4-Multimedia Module
+ 1000 Bluetooth Dongle (HID proxy mode)
+ 1010 Bluetooth Device
+ 1011 Bluetooth Device
+ 1012 Bluetooth Device
+ ffff USB Bluetooth Device in DFU State
+0a13 Telebyte, Inc.
+0a14 Spacelabs Medical, Inc.
+0a15 Scalar Corp.
+0a16 Trek Technology (S) PTE, Ltd
+ 1111 ThumbDrive
+ 8888 IBM USB Memory Key
+ 9988 Trek2000 TD-G2
+0a17 Pentax Corp.
+ 0004 Pentax Optio 330
+ 0006 Pentax Optio S
+ 0007 Pentax Optio 550
+ 0009 Pentax Optio 33WR
+ 000a Pentax Optio 555
+ 000c Pentax Optio 43WR (mass storage mode)
+ 000d Pentax Optio 43WR
+ 0015 Pentax Optio S40/S5i
+ 003b Pentax Optio 50 (mass storage mode)
+ 003d Pentax Optio S55
+ 0043 Pentax *ist DL
+ 0047 Pentax Optio S60
+ 0052 Optio 60 Digital Camera
+ 006e Pentax K10D
+ 0070 Pentax K100D
+ 1001 EI2000 Camera powered by Digita!
+0a18 Heidelberger Druckmaschinen AG
+0a19 Hua Geng Technologies, Inc.
+0a21 Medtronic Physio Control Corp.
+0a22 Century Semiconductor USA, Inc.
+0a2c AK-Modul-Bus Computer GmbH
+ 0008 GPIO Ports
+0a34 TG3 Electronics, Inc.
+ 0110 Deck 82-key backlit keyboard
+0a39 Gilat Satellite Networks, Ltd
+0a3a PentaMedia Co., Ltd
+ 0163 KN-W510U 1.0 Wireless LAN Adapter
+0a3c NTT DoCoMo, Inc.
+0a3d Varo Vision
+0a3f Swissonic AG
+0a43 Boca Systems, Inc.
+0a46 Davicom Semiconductor, Inc.
+ 0268 ST268
+ 9601 DM9601 To Fast Ethernet Adapter
+0a47 Hirose Electric
+0a48 I/O Interconnect
+ 3233 Multimedia Card Reader
+ 3239 Multimedia Card Reader
+ 3258 Dane Elec zMate SD Reader
+ 3259 Dane Elec zMate CF Reader
+ 5000 MediaGear xD-SM
+ 500a Mass Storage Device
+ 500f Mass Storage Device
+ 5010 Mass Storage Device
+ 5011 Mass Storage Device
+ 5014 Mass Storage Device
+ 5020 Mass Storage Device
+ 5021 Mass Storage Device
+ 5022 Mass Storage Device
+ 5023 Mass Storage Device
+ 5024 Mass Storage Device
+ 5025 Mass Storage Device
+0a4b Fujitsu Media Devices, Ltd
+0a4c Computex Co., Ltd
+0a4d Evolution Electronics, Ltd
+ 0064 MK-225 Driver
+ 0065 MK-225C Driver
+ 0066 MK-225C Driver
+ 0067 MK-425C Driver
+ 0078 MK-37 Driver
+ 0079 MK-37C Driver
+ 007a MK-37C Driver
+ 008c TerraTec MIDI MASTER
+ 008d MK-249C Driver
+ 008e MK-249C MIDI Keyboard
+ 008f MK-449C Driver
+ 0090 Keystation 49e Driver
+ 0091 Keystation 61es Driver
+ 00a0 MK-361 Driver
+ 00a1 MK-361C Driver
+ 00a2 MK-361C Driver
+ 00a3 MK-461C MIDI Keyboard
+ 00b5 Keystation Pro 88 Driver
+ 00d2 E-Keys Driver
+ 00f0 UC-16 Driver
+ 00f1 X-Session Driver
+ 00f5 UC-33e MIDI Controller
+0a4e Steinberg Soft-und Hardware GmbH
+0a4f Litton Systems, Inc.
+0a50 Mimaki Engineering Co., Ltd
+0a51 Sony Electronics, Inc.
+0a52 Jebsee Electronics Co., Ltd
+0a53 Portable Peripheral Co., Ltd
+ 1000 Scanner
+ 2000 Q-Scan A6 Scanner
+ 2001 Q-Scan A6 Scanner
+ 2013 Media Drive A6 Scanner
+ 2014 Media Drive A6 Scanner
+ 2015 BizCardReader 600C
+ 2016 BizCardReader 600C
+ 202a Scanshell-CSSN
+ 3000 Q-Scan A8 Scanner
+ 3002 Q-Scan A8 Reader
+ 3015 BizCardReader 300G
+ 5001 BizCardReader 900C
+0a5a Electronics For Imaging, Inc.
+0a5b EAsics NV
+0a5c Broadcom Corp.
+ 0201 iLine10(tm) Network Adapter
+ 2000 Bluetooth Device
+ 2009 Bluetooth Controller
+ 200a Bluetooth dongle
+ 200f Bluetooth Controller
+ 201d Bluetooth Device
+ 201e IBM Integrated Bluetooth IV
+ 2020 Bluetooth Dongle
+ 2033 BCM2033 Bluetooth
+ 2035 BCM2035 Bluetooth
+ 2038 Blutonium Device
+ 2039 Bluetooth Device
+ 2045 Bluetooth Controller
+ 2046 Bluetooth Device
+ 2047 Bluetooth Device
+ 205e Bluetooth Device
+ 2100 Bluetooth 2.0+eDR dongle
+ 2101 A-Link BlueUsbA2 Bluetooth
+ 2102 ANYCOM Blue USB-200/250
+ 2110 Bluetooth Controller
+ 2111 ANYCOM Blue USB-UHE 200/250
+ 2120 2045 Bluetooth 2.0 USB-UHE Device with trace filter
+ 2121 BCM2210 Bluetooth
+ 2122 Bluetooth 2.0+EDR dongle
+ 2130 2045 Bluetooth 2.0 USB-UHE Device with trace filter
+ 2131 2045 Bluetooth 2.0 Device with trace filter
+ 6300 Pirelli Remote NDIS Device
+0a5d Diatrend Corp.
+0a5f Zebra
+ 0009 LP2844 Printer
+ 930a Printer
+0a62 MPMan
+ 0010 MPMan MP-F40 MP3 Player
+0a66 ClearCube Technology
+0a67 Medeli Electronics Co., Ltd
+0a68 Comaide Corp.
+0a69 Chroma ate, Inc.
+0a6b Green House Co., Ltd
+ 0001 Compact Flash R/W with MP3 player
+0a6c Integrated Circuit Systems, Inc.
+0a6d UPS Manufacturing
+0a6e Benwin
+0a6f Core Technology, Inc.
+ 0400 Xanboo
+0a70 International Game Technology
+0a72 Sanwa Denshi
+0a7d NSTL, Inc.
+0a7e Octagon Systems Corp.
+0a80 Rexon Technology Corp., Ltd
+0a81 Chesen Electronics Corp.
+ 0101 Keyboard
+ 0103 Keyboard
+ 0203 Mouse
+ 0205 PS/2 Keyboard+Mouse Adapter
+0a82 Syscan
+ 4600 TravelScan 460/464
+0a83 NextComm, Inc.
+0a84 Maui Innovative Peripherals
+0a85 Idexx Labs
+0a86 NITGen Co., Ltd
+0a8d Picturetel
+0a8e Japan Aviation Electronics Industry, Ltd
+ 2011 Filter Driver For JAE XMC R/W
+0a90 Candy Technology Co., Ltd
+0a91 Globlink Technology, Inc.
+ 3801 Targus PAKP003 Mouse
+0a92 EGO SYStems, Inc.
+ 0011 SYS WaveTerminal U2A
+ 0021 GIGAPort
+ 0031 GIGAPortAG
+ 0053 AudioTrak Optoplay
+ 0061 Waveterminal U24
+ 0071 MAYA EX7
+ 0091 Maya 44
+ 00b1 MAYA EX5
+ 1000 MIDI Mate
+ 1010 RoMI/O
+ 1020 M4U
+ 1030 M8U
+ 1090 KeyControl49
+ 10a0 KeyControl25
+0a93 C Technologies AB
+ 0002 C-Pen 10
+ 0005 MyPen Light
+ 000d Input Pen
+ 0010 C-Pen 20
+0a94 Intersense
+0aa3 Lava Computer Mfg., Inc.
+0aa4 Develco Elektronik
+0aa5 First International Digital
+ 0002 irock! 500 Series
+ 0801 MP3 Player
+0aa6 Perception Digital, Ltd
+ 0101 Hercules Jukebox
+ 1501 Store 'n' Go HD Drive
+0aa7 Wincor Nixdorf International GmbH
+ 0100 POS Keyboard, TA58P-USB
+ 0101 POS Keyboard, TA85P-USB
+ 0102 POS Keyboard, TA59-USB
+ 0103 POS Keyboard, TA60-USB
+ 0104 SNIkey Keyboard, SNIKey-KB-USB
+ 0200 Operator Display, BA63-USB
+ 0201 Operator Display, BA66-USB
+ 0202 Operator Display & Scanner, XiCheck-BA63
+ 0203 Operator Display & Scanner, XiCheck-BA66
+ 0204 Graphics Operator Display, BA63GV
+ 0300 POS Printer (printer class mode), TH210
+ 0301 POS Printer (native mode), TH210
+ 0302 POS Printer (printer class mode), TH220
+ 0303 POS Printer (native mode), TH220
+ 0304 POS Printer, TH230
+ 0305 Lottery Printer, XiPrintPlus
+ 0306 POS Printer (printer class mode), TH320
+ 0307 POS Printer (native mode), TH320
+ 0308 POS Printer (printer class mode), TH420
+ 0309 POS Printer (native mode), TH420
+ 030a POS Printer, TH200B
+ 0400 Lottery Scanner, Xiscan S
+ 0401 Lottery Scanner, Xiscan 3
+ 4304 Banking Printer TP07
+0aa8 TriGem Computer, Inc.
+ 0060 TG 11Mbps WLAN Mini Adapter
+ 1001 DreamComboM4100
+ 3002 InkJet Color Printer
+ 8001 TG_iMON
+ 8002 TG_KLOSS
+ a001 TG_X2
+ a002 TGVFD_KLOSS
+ ffda iMON_VFD
+0aa9 Baromtec Co.
+ f01b Medion MD 6242 MP3 Player
+0aaa Japan CBM Corp.
+0aab Vision Shape Europe SA
+0aac iCompression, Inc.
+0aad Rohde & Schwarz GmbH & Co. KG
+0aae NEC infrontia Corp. (Nitsuko)
+0aaf Digitalway Co., Ltd
+0ab0 Arrow Strong Electronics Co., Ltd
+0aba Ellisys
+ 8001 USB Tracker 110 Protocol Analyzer
+0abe Stereo-Link
+ 0101 SL1200 DAC
+0ac3 Sanyo Semiconductor Company Micro
+0ac4 Leco Corp.
+0ac5 I & C Corp.
+0ac6 Singing Electrons, Inc.
+0ac7 Panwest Corp.
+0ac8 Z-Star Microelectronics Corp.
+ 0301 Web Camera
+ 0302 ZC0302 WebCam
+ 0321 USB 2.0 Webcam
+ 0323 Luxya WC-1200 USB 2.0 Webcam
+ 301b ZC0301 WebCam
+ 303b ZC0303 WebCam
+ 305b ZC0305 WebCam
+ 307b USB 1.1 WebCam
+ c002 Visual Communication Camera VGP-VCC1
+0ac9 Micro Solutions, Inc.
+ 0000 Backpack CD-ReWriter
+ 0001 BACKPACK 2 Cable
+ 0010 BACKPACK
+ 0011 Backpack 40GB Hard Drive
+ 0110 BACKPACK
+ 0111 BackPack
+ 1234 BACKPACK
+0aca OPEN Networks Ltd
+ 1060 OPEN NT1 Plus II
+0acc Koga Electronics Co.
+0acd ID Tech
+ 0401 ID TECH Spectrum III Hybrid Smartcard Reader
+0ace ZyDAS
+ 1201 802.11b WiFi
+ 1211 802.11b/g USB2 WiFi
+ 1215 WLA-54L WiFi
+ 1608 ONMI FAXMODEM 56K UNO (ZyXEL)
+0acf Intoto, Inc.
+0ad0 Intellix Corp.
+0ad1 Remotec Technology, Ltd
+0ad2 Service & Quality Technology Co., Ltd
+0ae3 Allion Computer, Inc.
+0ae4 Taito Corp.
+0ae7 Neodym Systems, Inc.
+0ae8 System Support Co., Ltd
+0ae9 North Shore Circuit Design L.L.P.
+0aea SciEssence, LLC
+0aeb TTP Communications, Ltd
+0aec Neodio Technologies Corp.
+ 2101 SmartMedia Card Reader
+ 2102 CompactFlash Card Reader
+ 2103 MMC/SD Card Reader
+ 2104 MemoryStick Card Reader
+ 2201 SmartMedia+CompactFlash Card Reader
+ 2202 SmartMedia+MMC/SD Card Reader
+ 2203 SmartMedia+MemoryStick Card Reader
+ 2204 CompactFlash+MMC/SD Card Reader
+ 2205 CompactFlash+MemoryStick Card Reader
+ 2206 MMC/SD+MemoryStick Card Reader
+ 2301 SmartMedia+CompactFlash+MMC/SD Card Reader
+ 2302 SmartMedia+CompactFlash+MemoryStick Card Reader
+ 2303 SmartMedia+MMC/SD+MemoryStick Card Reader
+ 2304 CompactFlash+MMC/SD+MemoryStick Card Reader
+ 3016 MMC/SD+Memory Stick Card Reader
+ 3050 ND3050 8-in-1 Card Reader
+ 3060 1.1 FS Card Reader
+ 3101 MMC/SD Card Reader
+ 3102 MemoryStick Card Reader
+ 3201 MMC/SD+MemoryStick Card Reader
+ 3216 HS Card Reader
+ 3260 7-in-1 Card Reader
+ 5010 ND5010 Card Reader
+0af0 Option
+ 5000 UMTS Card
+ 6000 GlobeTrotter 3G datacard
+ 6300 GT 3G Quad UMTS/GPRS Card
+ 6600 GlobeTrotter 3G+ datacard
+0af6 Silver I Co., Ltd
+0af7 B2C2, Inc.
+ 0101 Digital TV USB Receiver (DVB-S/T/C / ATSC)
+0af9 Hama, Inc.
+ 0010 USB SightCam 100
+ 0011 Micro Innovations IC50C WebCam
+0afc Zaptronix Ltd
+0afd Tateno Dennou, Inc.
+0afe Cummins Engine Co.
+0aff Jump Zone Network Products, Inc.
+0b00 INGENICO
+0b05 ASUSTek Computer, Inc.
+ 1101 Mass Storage (UISDMC4S)
+ 1706 WL-167G 802.11g Adapter [ralink]
+ 1707 WL-167g Wireless Adapter
+ 1708 Mass Storage Device
+ 170b Mass Storage Device
+ 170c WL-159g
+ 170d 802.11b/g Wireless Network Adapter
+ 1712 BT-183 Bluetooth 2.0+EDR adapter
+ 1715 2045 Bluetooth 2.0 Device with trace filter
+ 1716 Bluetooth Device
+ 171b A9T wireless
+ 171c 802.11b/g Wireless Network Adapter
+ 1723 WL-167G v2 802.11g Adapter [ralink]
+ 1724 RT2573
+ 1726 Laptop OLED Display
+ 172a ASUS 802.11n Network Adapter
+ 172b 802.11n Network Adapter
+ 1731 ASUS 802.11n Network Adapter
+ 1732 802.11n Network Adapter
+ 173c BT-183 Bluetooth 2.0
+ 1742 802.11n Network Adapter
+ 6101 Cable Modem
+ 620a Remote NDIS Device
+0b0c Todos Data System AB
+ 0009 Todos Argos Mini II Smart Card Reader
+0b0e GN Netcom
+0b0f AVID Technology
+0b10 Pcally
+0b11 I Tech Solutions Co., Ltd
+0b1e Electronic Warfare Assoc., Inc. (EWA)
+0b1f Insyde Software Corp.
+0b20 TransDimension, Inc.
+0b21 Yokogawa Electric Corp.
+0b22 Japan System Development Co., Ltd
+0b23 Pan-Asia Electronics Co., Ltd
+0b24 Link Evolution Corp.
+0b27 Ritek Corp.
+0b28 Kenwood Corp.
+0b2c Village Center, Inc.
+0b30 PNY Technologies, Inc.
+ 0006 SM Media-Shuttle Card Reader
+0b33 Contour Design, Inc.
+ 0020 ShuttleXpress
+0b37 Hitachi ULSI Systems Co., Ltd
+0b39 Omnidirectional Control Technology, Inc.
+ 0109 USB TO Ethernet
+ 0421 Serial
+ 0801 USB-Parallel Bridge
+ 0901 OCT To Fast Ethernet Converter
+ 0c03 LAN DOCK Serial Converter
+0b3a IPaxess
+0b3b Tekram Technology Co., Ltd
+ 0163 TL-WN320G 1.0 WLAN Adapter
+ 1601 Allnet 0193 802.11b Adapter
+ 1602 ZyXEL ZyAIR B200 802.11b Adapter
+ 1612 AIR.Mate 2@net 802.11b Adapter
+ 1613 802.11b Wireless LAN Adapter
+ 1620 Allnet USB 2.0 Wireless Network Adapter
+ 1630 QuickWLAN
+ 5630 ZD1211
+ 6630 ZD1211
+0b3c Olivetti Techcenter
+ a010 Simple_Way Printer/Scanner/Copier
+0b3e Kikusui Electronics Corp.
+0b41 Hal Corp.
+ 0011 Crossam2+USB IR commander
+0b43 Play.com, Inc.
+ 0003 PS2 Controller Converter
+0b47 Sportbug.com, Inc.
+0b48 TechnoTrend AG
+ 1003 Technotrend/Hauppauge USB-Nova
+ 1004 TT-PCline
+ 1005 Technotrend/Hauppauge USB-Nova
+ 1006 Technotrend/Hauppauge DEC3000-s
+ 1007 TT-micro plus Device
+ 1008 Technotrend/Hauppauge DEC2000-t
+ 1009 Technotrend/Hauppauge DEC2540-t
+0b49 ASCII Corp.
+ 064f Trance Vibrator
+0b4b Pine Corp. Ltd.
+ 0100 D'music MP3 Player
+0b4d Graphtec America, Inc.
+ 110a Graphtec CC200-20
+0b4e Musical Electronics, Ltd
+ 6500 MP3 Player
+ 8028 MP3 Player
+ 8920 MP3 Player
+0b50 Dumpries Co., Ltd
+0b51 Comfort Keyboard Co.
+ 0020 Comfort Keyboard
+0b52 Colorado MicroDisplay, Inc.
+0b54 Sinbon Electronics Co., Ltd
+0b56 TYI Systems, Ltd
+0b57 Beijing HanwangTechnology Co., Ltd
+0b59 Lake Communications, Ltd
+0b5a Corel Corp.
+0b5f Green Electronics Co., Ltd
+0b60 Nsine, Ltd
+0b61 NEC Viewtechnology, Ltd
+0b62 Orange Micro, Inc.
+ 000b Bluetooth Device
+ 0059 iBOT2 WebCam
+0b63 ADLink Technology, Inc.
+0b64 Wonderful Wire Cable Co., Ltd
+0b65 Expert Magnetics Corp.
+0b69 CacheVision
+0b6a Maxim Integrated Products
+0b6f Nagano Japan Radio Co., Ltd
+0b70 PortalPlayer, Inc.
+ 00ba iRiver H10 20GB
+0b71 SHIN-EI Sangyo Co., Ltd
+0b72 Embedded Wireless Technology Co., Ltd
+0b73 Computone Corp.
+0b75 Roland DG Corp.
+0b79 Sunrise Telecom, Inc.
+0b7a Zeevo, Inc.
+ 07d0 Bluetooth Dongle
+0b7b Taiko Denki Co., Ltd
+0b7c ITRAN Communications, Ltd
+0b7d Astrodesign, Inc.
+0b84 Rextron Technology, Inc.
+0b85 Elkat Electronics, Sdn., Bhd.
+0b86 Exputer Systems, Inc.
+ 5100 XMC5100 Zippy Drive
+ 5110 XMC5110 Flash Drive
+ 5200 XMC5200 Zippy Drive
+ 5201 XMC5200 Zippy Drive
+ 5202 XMC5200 Zippy Drive
+ 5280 XMC5280 Storage Drive
+ fff0 ISP5200 Debugger
+0b87 Plus-One I & T, Inc.
+0b88 Sigma Koki Co., Ltd, Technology Center
+0b89 Advanced Digital Broadcast, Ltd
+0b95 ASIX Electronics Corp.
+ 1720 10/100 Ethernet
+ 1780 AX88178
+ 7720 AX88772
+0b96 Sewon Telecom
+0b97 O2 Micro, Inc.
+ 7732 Smart Card Reader
+ 7761 Oz776 1.1 Hub
+ 7762 Oz776 SmartCard Reader
+ 7772 OZ776 CCID Smartcard Reader
+0b98 Playmates Toys, Inc.
+0b99 Audio International, Inc.
+0b9b Dipl.-Ing. Stefan Kunde
+ 4012 Reflex RC-controller Interface
+0b9d Softprotec Co.
+0b9f Chippo Technologies
+0baf U.S. Robotics
+ 00e5 USR6000
+ 00eb USR1120 802.11b Adapter
+ 00ec 56K Faxmodem
+ 00f1 SureConnect ADSL ATM Adapter
+ 00f2 SureConnect ADSL Loader
+ 00f5 SureConnect ADSL ATM Adapter
+ 00f6 SureConnect ADSL Loader
+ 00f7 SureConnect ADSL ATM Adapter
+ 00f8 SureConnect ADSL Loader
+ 00f9 SureConnect ADSL ATM Adapter
+ 00fa SureConnect ADSL Loader
+ 00fb SureConnect ADSL Ethernet/USB Router
+ 0118 U5 802.11g Adapter
+ 011b Wireless MAXg Adapter
+ 0121 USR5423 WLAN
+ 6112 FaxModem Model 5633
+0bb0 Concord Camera Corp.
+ 0100 Sound Vision Stream
+ 5007 3340z/Rollei DC3100
+0bb1 Infinilink Corp.
+0bb2 Ambit Microsystems Corp.
+ 0302 WLAN
+ 6098 USB Cable Modem
+0bb3 Ofuji Technology
+0bb4 High Tech Computer Corp.
+ 00ce mmO2 XDA GSM/GPRS Pocket PC
+ 00cf SPV C500 Smart Phone
+ 0a01 PocketPC Sync
+ 0a02 Himalaya GSM/GPRS Pocket PC
+ 0a03 PocketPC Sync
+ 0a04 PocketPC Sync
+ 0a05 PocketPC Sync
+ 0a06 PocketPC Sync
+ 0a07 Magician PocketPC SmartPhone / O2 XDA
+ 0a08 PocketPC Sync
+ 0a09 PocketPC Sync
+ 0a0a PocketPC Sync
+ 0a0b PocketPC Sync
+ 0a0c PocketPC Sync
+ 0a0d PocketPC Sync
+ 0a0e PocketPC Sync
+ 0a0f PocketPC Sync
+ 0a10 PocketPC Sync
+ 0a11 PocketPC Sync
+ 0a12 PocketPC Sync
+ 0a13 PocketPC Sync
+ 0a14 PocketPC Sync
+ 0a15 PocketPC Sync
+ 0a16 PocketPC Sync
+ 0a17 PocketPC Sync
+ 0a18 PocketPC Sync
+ 0a19 PocketPC Sync
+ 0a1a PocketPC Sync
+ 0a1b PocketPC Sync
+ 0a1c PocketPC Sync
+ 0a1d PocketPC Sync
+ 0a1e PocketPC Sync
+ 0a1f PocketPC Sync
+ 0a20 PocketPC Sync
+ 0a21 PocketPC Sync
+ 0a22 PocketPC Sync
+ 0a23 PocketPC Sync
+ 0a24 PocketPC Sync
+ 0a25 PocketPC Sync
+ 0a26 PocketPC Sync
+ 0a27 PocketPC Sync
+ 0a28 PocketPC Sync
+ 0a29 PocketPC Sync
+ 0a2a PocketPC Sync
+ 0a2b PocketPC Sync
+ 0a2c PocketPC Sync
+ 0a2d PocketPC Sync
+ 0a2e PocketPC Sync
+ 0a2f PocketPC Sync
+ 0a30 PocketPC Sync
+ 0a31 PocketPC Sync
+ 0a32 PocketPC Sync
+ 0a33 PocketPC Sync
+ 0a34 PocketPC Sync
+ 0a35 PocketPC Sync
+ 0a36 PocketPC Sync
+ 0a37 PocketPC Sync
+ 0a38 PocketPC Sync
+ 0a39 PocketPC Sync
+ 0a3a PocketPC Sync
+ 0a3b PocketPC Sync
+ 0a3c PocketPC Sync
+ 0a3d PocketPC Sync
+ 0a3e PocketPC Sync
+ 0a3f PocketPC Sync
+ 0a40 PocketPC Sync
+ 0a41 PocketPC Sync
+ 0a42 PocketPC Sync
+ 0a43 PocketPC Sync
+ 0a44 PocketPC Sync
+ 0a45 PocketPC Sync
+ 0a46 PocketPC Sync
+ 0a47 PocketPC Sync
+ 0a48 PocketPC Sync
+ 0a49 PocketPC Sync
+ 0a4a PocketPC Sync
+ 0a4b PocketPC Sync
+ 0a4c PocketPC Sync
+ 0a4d PocketPC Sync
+ 0a4e PocketPC Sync
+ 0a4f PocketPC Sync
+ 0a50 HTC SmartPhone Sync
+ 0a51 SPV C400 / T-Mobile SDA GSM/GPRS Pocket PC
+ 0a52 SmartPhone Sync
+ 0a53 SmartPhone Sync
+ 0a54 SmartPhone Sync
+ 0a55 SmartPhone Sync
+ 0a56 SmartPhone Sync
+ 0a57 SmartPhone Sync
+ 0a58 SmartPhone Sync
+ 0a59 SmartPhone Sync
+ 0a5a SmartPhone Sync
+ 0a5b SmartPhone Sync
+ 0a5c SmartPhone Sync
+ 0a5d SmartPhone Sync
+ 0a5e SmartPhone Sync
+ 0a5f SmartPhone Sync
+ 0a60 SmartPhone Sync
+ 0a61 SmartPhone Sync
+ 0a62 SmartPhone Sync
+ 0a63 SmartPhone Sync
+ 0a64 SmartPhone Sync
+ 0a65 SmartPhone Sync
+ 0a66 SmartPhone Sync
+ 0a67 SmartPhone Sync
+ 0a68 SmartPhone Sync
+ 0a69 SmartPhone Sync
+ 0a6a SmartPhone Sync
+ 0a6b SmartPhone Sync
+ 0a6c SmartPhone Sync
+ 0a6d SmartPhone Sync
+ 0a6e SmartPhone Sync
+ 0a6f SmartPhone Sync
+ 0a70 SmartPhone Sync
+ 0a71 SmartPhone Sync
+ 0a72 SmartPhone Sync
+ 0a73 SmartPhone Sync
+ 0a74 SmartPhone Sync
+ 0a75 SmartPhone Sync
+ 0a76 SmartPhone Sync
+ 0a77 SmartPhone Sync
+ 0a78 SmartPhone Sync
+ 0a79 SmartPhone Sync
+ 0a7a SmartPhone Sync
+ 0a7b SmartPhone Sync
+ 0a7c SmartPhone Sync
+ 0a7d SmartPhone Sync
+ 0a7e SmartPhone Sync
+ 0a7f SmartPhone Sync
+ 0a80 SmartPhone Sync
+ 0a81 SmartPhone Sync
+ 0a82 SmartPhone Sync
+ 0a83 SmartPhone Sync
+ 0a84 SmartPhone Sync
+ 0a85 SmartPhone Sync
+ 0a86 SmartPhone Sync
+ 0a87 SmartPhone Sync
+ 0a88 SmartPhone Sync
+ 0a89 SmartPhone Sync
+ 0a8a SmartPhone Sync
+ 0a8b SmartPhone Sync
+ 0a8c SmartPhone Sync
+ 0a8d SmartPhone Sync
+ 0a8e SmartPhone Sync
+ 0a8f SmartPhone Sync
+ 0a90 SmartPhone Sync
+ 0a91 SmartPhone Sync
+ 0a92 SmartPhone Sync
+ 0a93 SmartPhone Sync
+ 0a94 SmartPhone Sync
+ 0a95 SmartPhone Sync
+ 0a96 SmartPhone Sync
+ 0a97 SmartPhone Sync
+ 0a98 SmartPhone Sync
+ 0a99 SmartPhone Sync
+ 0a9a SmartPhone Sync
+ 0a9b SmartPhone Sync
+ 0a9c SmartPhone Sync
+ 0a9d SmartPhone Sync
+ 0a9e SmartPhone Sync
+ 0a9f SmartPhone Sync
+ 0b04 Hermes / TyTN / T-Mobile MDA Vario II / O2 Xda Trion
+ 0b06 Athena / Advantage x7500 / Dopod U1000 / T-Mobile AMEO
+ 0b0c Elf / Touch / P3450 / T-Mobile MDA Touch / O2 Xda Nova / Dopod S1
+ 0bce Vario MDA
+0bb5 Murata Manufacturing Co., Ltd
+0bb6 Network Alchemy
+0bb7 Joytech Computer Co., Ltd
+0bb8 Hitachi Semiconductor and Devices Sales Co., Ltd
+0bb9 Eiger M&C Co., Ltd
+0bba ZAccess Systems
+0bbb General Meters Corp.
+0bbc Assistive Technology, Inc.
+0bbd System Connection, Inc.
+0bc0 Knilink Technology, Inc.
+0bc1 Fuw Yng Electronics Co., Ltd
+0bc2 Seagate RSS LLC
+ 2000 Storage Adapter V3 (TPP)
+0bc3 IPWireless, Inc.
+0bc4 Microcube Corp.
+0bc5 JCN Co., Ltd
+0bc6 ExWAY, Inc.
+0bc7 X10 Wireless Technology, Inc.
+ 0001 ActiveHome (ACPI-compliant)
+ 0002 Firecracker Interface (ACPI-compliant)
+ 0003 VGA Video Sender (ACPI-compliant)
+ 0004 X10 Receiver
+ 0005 Wireless Transceiver (ACPI-compliant)
+ 0006 Wireless Transceiver (ACPI-compliant)
+ 0007 Wireless Transceiver (ACPI-compliant)
+ 0008 Wireless Transceiver (ACPI-compliant)
+ 0009 Wireless Transceiver (ACPI-compliant)
+ 000a Wireless Transceiver (ACPI-compliant)
+ 000b Transceiver (ACPI-compliant)
+ 000c Transceiver (ACPI-compliant)
+ 000d Transceiver (ACPI-compliant)
+ 000e Transceiver (ACPI-compliant)
+ 000f Transceiver (ACPI-compliant)
+0bc8 Telmax Communications
+0bc9 ECI Telecom, Ltd
+0bca Startek Engineering, Inc.
+0bcb Perfect Technic Enterprise Co., Ltd
+0bd7 Andrew Pargeter & Associates
+ a021 Amptek DP4 multichannel signal analyzer
+0bda Realtek Semiconductor Corp.
+ 0103 USB 2.0 Card Reader
+ 0104 Mass Storage Device
+ 0106 Mass Storage Device
+ 0107 Mass Storage Device
+ 0108 Mass Storage Device
+ 0111 Card Reader
+ 0113 Mass Storage Device
+ 0115 Mass Storage Device
+ 0116 Mass Storage Device
+ 0117 Mass Storage Device
+ 0118 Mass Storage Device
+ 0151 Mass Stroage Device
+ 0152 Mass Stroage Device
+ 0153 Mass Stroage Device
+ 0156 Mass Stroage Device
+ 0157 Mass Stroage Device
+ 0158 Mass Stroage Device
+ 0161 Mass Stroage Device
+ 0168 Mass Stroage Device
+ 0169 Mass Stroage Device
+ 0171 Mass Stroage Device
+ 0176 Mass Stroage Device
+ 0178 Mass Stroage Device
+ 2831 2831U Device
+ 8150 RTL8150 Fast Ethernet Adapter
+ 8151 RTL8151 Adapteon Business Mobile Networks BV
+ 8187 RTL8187 Wireless Adapter
+ 8189 RTL8187B Wireless 802.11g 54Mbps Network Adapter
+ 8197 RTL8187B Wireless Adapter
+0bdb Ericsson Business Mobile Networks BV
+ 1000 BV Bluetooth Device
+ 1002 Bluetooth Device 1.2
+0bdc Y Media Corp.
+0bdd Orange PCS
+0be2 Kanda Tsushin Kogyo Co., Ltd
+0be3 TOYO Corp.
+0be4 Elka International, Ltd
+0be5 DOME imaging systems, Inc.
+0be6 Dong Guan Humen Wonderful Wire Cable Factory
+0bee LTK Industries, Ltd
+0bef Way2Call Communications
+0bf0 Pace Micro Technology PLC
+0bf1 Intracom S.A.
+ 0001 netMod Driver Ver 2.4.17 (CAPI)
+ 0002 netMod Driver Ver 2.4 (CAPI)
+ 0003 netMod Driver Ver 2.4 (CAPI)
+0bf2 Konexx
+0bf6 Addonics Technologies, Inc.
+ 0103 Storage Device
+ 1234 Storage Device
+ a000 Cable 205 (TPP)
+ a001 Cable 205
+ a002 IDE Bridge
+0bf7 Sunny Giken, Inc.
+0bf8 Fujitsu Siemens Computers
+ 1001 Fujitsu Pocket Loox 600 PDA
+0c04 MOTO Development Group, Inc.
+0c05 Appian Graphics
+0c06 Hasbro Games, Inc.
+0c07 Infinite Data Storage, Ltd
+0c08 Agate
+ 0378 Q 16MB Storage Device
+0c09 Comjet Information System
+ a5a5 Litto Version USB2.0
+0c0a Highpoint Technologies, Inc.
+0c0b Dura Micro, Inc. (Acomdata)
+ 27cb 6-in-1 Flash Reader and Writer
+ 27d7 Multi Memory reader/writer MD-005
+ 27da Multi Memory reader/writer MD-005
+ 27dc Multi Memory reader/writer MD-005
+ 27e7 3,5'' HDD case MD-231
+ 27ee 3,5'' HDD case MD-231
+ 2814 3,5'' HDD case MD-231
+ 2815 3,5'' HDD case MD-231
+ 281d 3,5'' HDD case MD-231
+ a109 CF/SM Reader and Writer
+ a10c SD/MS Reader and Writer
+ b001 USB 2.0 Mass Storage IDE adapter
+ b004 MMC/SD Reader and Writer
+0c12 Zeroplus
+ 0005 PSX Vibration Feedback Converter
+ 8809 Red Octane Ignition Xbox DDR Pad
+0c15 Iris Graphics
+0c16 Gyration, Inc.
+ 0080 eHome Infrared Receiver
+ 0081 eHome Infrared Receiver
+0c17 Cyberboard A/S
+0c18 SynerTek Korea, Inc.
+0c19 cyberPIXIE, Inc.
+0c1a Silicon Motion, Inc.
+0c1b MIPS Technologies
+0c1c Hang Zhou Silan Electronics Co., Ltd
+0c22 Tally Printer Corp.
+0c23 Lernout + Hauspie
+0c24 Taiyo Yuden
+ 0001 Bluetooth Adaptor
+ 0002 Bluetooth Device2
+ 0005 Bluetooth Device(BC04-External)
+ 000b Bluetooth Device(BC04-External)
+ 000c Bluetooth Adaptor
+ 000e Bluetooth Device(BC04-External)
+ 000f Bluetooth Driver (V2.0+EDR)
+ 0010 Bluetooth Device(BC04-External)
+ 0012 Bluetooth Device(BC04-External)
+ 0018 Bluetooth Device(BC04-External)
+ 0019 Bluetooth Device
+ 0c24 Bluetooth Device(SAMPLE)
+ ffff Bluetooth module with BlueCore in DFU mode
+0c25 Sampo Corp.
+ 0310 Scream Cam
+0c27 RFIDeas, Inc
+ 3bfa pcProx Card Reader
+0c2e Metro
+ 0200 Metrologic Scanner
+0c35 Eagletron, Inc.
+0c36 E Ink Corp.
+0c37 e.Digital
+0c38 Der An Electric Wire & Cable Co., Ltd
+0c39 IFR
+0c3a Furui Precise Component (Kunshan) Co., Ltd
+0c3b Komatsu, Ltd
+0c3c Radius Co., Ltd
+0c3d Innocom, Inc.
+0c3e Nextcell, Inc.
+0c44 Motorola iDEN
+ 0021 iDEN P2k0 Device
+ 0022 iDEN P2k1 Device
+ 03a2 iDEN Smartphone
+0c45 Microdia
+ 1020 Mass Storage Reader
+ 1028 Mass Storage Reader
+ 1030 Mass Storage Reader
+ 1031 Sonix Mass Storage Device
+ 1032 Mass Storage Reader
+ 1033 Sonix Mass Storage Device
+ 1034 Mass Storage Reader
+ 1035 Mass Storage Reader
+ 1036 Mass Storage Reader
+ 1037 Sonix Mass Storage Device
+ 1050 CF Card Reader
+ 1058 HDD Reader
+ 1060 iFlash SM-Direct Card Reader
+ 1061 Mass Storage Reader
+ 1062 Mass Storage Reader
+ 1063 Sonix Mass Storage Device
+ 1064 Mass Storage Reader
+ 1065 Mass Storage Reader
+ 1066 Mass Storage Reader
+ 1067 Mass Storage Reader
+ 1158 A56AK
+ 184c VoIP Phone
+ 6001 Genius VideoCAM NB
+ 6005 Sweex Mini WebCam
+ 6007 VideoCAM Eye
+ 6009 VideoCAM ExpressII
+ 600d TwinkleCam USB camera
+ 6011 PC Camera (SN9C102)
+ 6019 PC Camera (SN9C102)
+ 6024 VideoCAM ExpressII
+ 6025 VideoCAM ExpressII
+ 6028 Typhoon Easycam USB 330K (older)
+ 6029 Triplex i-mini PC Camera
+ 602a Meade ETX-105EC Camera
+ 602b VideoCAM NB 300
+ 602c Clas Ohlson TWC-30XOP WebCam
+ 602d VideoCAM ExpressII
+ 602e VideoCAM Messenger
+ 6030 VideoCAM ExpressII
+ 603f VideoCAM ExpressII
+ 6040 CCD PC Camera (PC390A)
+ 606a CCD PC Camera (PC390A)
+ 607a CCD PC Camera (PC390A)
+ 607b Win2 PC Camera
+ 607c CCD PC Camera (PC390A)
+ 607e CCD PC Camera (PC390A)
+ 6080 Audio (Microphone)
+ 6082 VideoCAM Look
+ 6083 VideoCAM Look
+ 608c VideoCAM Look
+ 608e VideoCAM Look
+ 608f VideoCAM Look
+ 60a8 VideoCAM Look
+ 60aa VideoCAM Look
+ 60ab PC Camera
+ 60af VideoCAM Look
+ 60b0 Genius VideoCam Look
+ 60c0 PC Camera with Mic (SN9C105)
+ 60c8 Win2 PC Camera
+ 60cc Composite Device
+ 60ec Composite Device
+ 60ef Win2 PC Camera
+ 60fa PC Camera with Mic (SN9C105)
+ 60fb Composite Device
+ 60fc PC Camera with Mic (SN9C105)
+ 60fe Audio (Microphone)
+ 6108 Win2 PC Camera
+ 6122 PC Camera (SN9C110)
+ 6123 PC Camera (SN9C110)
+ 612a PC Camera (SN9C110)
+ 612c PC Camera (SN9C110)
+ 612e PC Camera (SN9C110)
+ 612f PC Camera (SN9C110)
+ 6130 PC Camera (SN9C120)
+ 6138 Win2 PC Camera
+ 613a PC Camera (SN9C120)
+ 613b Win2 PC Camera
+ 613c PC Camera (SN9C120)
+ 613e PC Camera (SN9C120)
+ 6240 PC Camera (SN9C201)
+ 6242 PC Camera (SN9C201)
+ 6243 PC Camera (SN9C201)
+ 6248 PC Camera (SN9C201)
+ 624b PC Camera (SN9C201)
+ 624c PC Camera (SN9C201)
+ 624e PC Camera (SN9C201)
+ 624f PC Camera (SN9C201)
+ 6260 PC Camera (SN9C201)
+ 6270 U-CAM PC Camera NE878
+ 627a PC Camera (SN9C201)
+ 627b PC Camera (SN9C201)
+ 627c PC Camera (SN9C201)
+ 627f PC Camera (SN9C201)
+ 6280 Composite Device
+ 6282 Audio (Microphone)
+ 6283 Audio (Microphone)
+ 6288 Audio (Microphone)
+ 628a Composite Device
+ 628b PC Camera (SN9C202)
+ 628c PC Camera (SN9C202)
+ 628e Composite Device
+ 628f Composite Device
+ 62a0 Audio (Microphone)
+ 62b0 Audio (Microphone)
+ 62ba PC Camera (SN9C202)
+ 62bb PC Camera (SN9C202)
+ 62bc Composite Device
+ 62c0 Pavilion Webcam
+ 8000 DC31VC
+ 8006 Dual Mode Camera (8006 VGA)
+ 800a Vivitar Vivicam3350B
+0c46 WaveRider Communications, Inc.
+0c4b Reiner SCT Kartensysteme GmbH
+ 0100 cyberJack e-com/pinpad
+ 0300 cyberJack pinpad(a)
+0c52 Sealevel Systems, Inc.
+ 2101 Serial Converter
+0c53 ViewPLUS, Inc.
+0c54 Glory, Ltd
+0c55 Spectrum Digital, Inc.
+ 0510 Spectrum Digital XDS510 JTAG Debugger
+ 0540 SPI540
+ 5416 TMS320C5416 DSK
+ 6416 TMS320C6416 DDB
+0c56 Billion Bright, Ltd
+0c57 Imaginative Design Operation Co., Ltd
+0c58 Vidar Systems Corp.
+0c59 Dong Guan Shinko Wire Co., Ltd
+0c5a TRS International Mfg., Inc.
+0c5e Xytronix Research & Design
+0c62 Chant Sincere Co., Ltd
+0c63 Toko, Inc.
+0c64 Signality System Engineering Co., Ltd
+0c65 Eminence Enterprise Co., Ltd
+0c66 Rexon Electronics Corp.
+0c67 Concept Telecom, Ltd
+0c70 MCT Elektronikladen
+ 0000 USB08 Development board
+0c74 Optronic Laboratories Inc.
+ 0002 OL 700-30 Goniometer
+0c76 JMTek, LLC.
+ 0001 Mass Storage Controller
+ 0002 Mass Storage Controller
+ 0003 USBdisk
+ 0004 Mass Storage Controller
+ 0005 Transcend USB Flash disk
+ 0006 Transcend JetFlash
+ 0007 Mass Storage Device
+0c77 Sipix Group, Ltd
+ 1001 SiPix Web2
+ 1002 SiPix SC2100
+ 1010 SiPix Snap
+ 1011 SiPix Blink 2
+ 1015 SiPix CAMeleon
+0c78 Detto Corp.
+0c79 NuConnex Technologies Pte., Ltd
+0c7a Wing-Span Enterprise Co., Ltd
+0c86 NDA Technologies, Inc.
+0c88 Kyocera Wireless Corp.
+ 0021 Handheld
+ 17da Qualcomm Kyocera CDMA Technologies MSM
+0c89 Honda Tsushin Kogyo Co., Ltd
+0c8a Pathway Connectivity, Inc.
+0c8b Wavefly Corp.
+0c8c Coactive Networks
+0c8d Tempo
+0c8e Cesscom Co., Ltd
+ 6000 Luxian Series
+0c8f Applied Microsystems
+0c98 Berkshire Products, Inc.
+ 1140 USB PC Watchdog
+0c99 Innochips Co., Ltd
+0c9a Hanwool Robotics Corp.
+0c9b Jobin Yvon, Inc.
+0c9d SemTek
+ 0170 3873 Manual Insert card reader
+0ca2 Zyfer
+0ca3 Sega Corp.
+0ca4 ST&T Instrument Corp.
+0ca5 BAE Systems Canada, Inc.
+0ca6 Castles Technology Co., Ltd
+ 0010 EZUSB PC/SC Smart Card Reader
+ 0050 EZ220PU Reader Controller
+ 1077 Bludrive Family Smart Card Reader
+ 107e Reader Controller
+ 2010 myPad110 PC/SC Smart Card Reader
+0ca7 Information Systems Laboratories
+0cad Motorola CGISS
+ 9001 PowerPad Pocket PC Device
+0cae Ascom Business Systems, Ltd
+0caf Buslink
+ 2507 Hi-Speed USB-to-IDE Bridge Controller
+ 2515 Flash Disk Embedded Hub
+ 2516 Flash Disk Security Device
+ 2517 Flash Disk Mass Storage Device
+ 25c7 Hi-Speed USB-to-IDE Bridge Controller
+ 3a00 Hard Drive
+ 3a20 Mass Storage Device
+ 3acd Mass Storage Device
+0cb0 Flying Pig Systems
+0cb1 Innovonics, Inc.
+0cb6 Celestix Networks, Pte., Ltd
+0cb7 Singatron Enterprise Co., Ltd
+0cb8 Opticis Co., Ltd
+0cba Trust Electronic (Shanghai) Co., Ltd
+0cbb Shanghai Darong Electronics Co., Ltd
+0cbc Palmax Technology Co., Ltd
+ 0101 Pocket PC P6C
+ 0201 Personal Digital Assistant
+ 0301 Personal Digital Assistant P6M+
+ 0401 Pocket PC
+0cbd Pentel Co., Ltd (Electronics Equipment Div.)
+0cbe Keryx Technologies, Inc.
+0cbf Union Genius Computer Co., Ltd
+0cc0 Kuon Yi Industrial Corp.
+0cc1 Given Imaging, Ltd
+0cc2 Timex Corp.
+0cc3 Rimage Corp.
+0cc4 emsys GmbH
+0cc5 Sendo
+0cc6 Intermagic Corp.
+0cc7 Kontron Medical AG
+0cc8 Technotools Corp.
+0cc9 BroadMAX Technologies, Inc.
+0cca Amphenol
+0ccb SKNet Co., Ltd
+0ccc Domex Technology Corp.
+0ccd TerraTec Electronic GmbH
+ 0012 PHASE 26
+ 0013 PHASE 26
+ 0014 PHASE 26
+ 0015 Flash Update for TerraTec PHASE 26
+ 0021 Cameo Grabster 200
+ 0023 Mystify Claw
+ 0028 Aureon 5.1 MkII
+ 0032 MIDI HUBBLE
+ 0035 Miditech Play'n Roll
+ 0036 Cinergy 250 Audio
+ 0037 Cinergy 250 Audio
+ 0038 Cinergy T^2 DVB-T Receiver
+ 0039 Grabster AV 400
+ 003b Cinergy 400
+ 003c Grabster AV 250
+ 0042 Cinergy Hybrid T XS
+ 0043 Cinergy T XS
+ 004e Cinergy T XS
+ 004f Cinergy Analog XS
+ 005c Cinergy T²
+ 0069 Cinergy T XE DVB-T Receiver
+0cd4 Bang Olufsen
+ 0101 BeolinkPC2
+0cd7 NewChip S.r.l.
+0cd8 JS Digitech, Inc.
+ 2007 Smart Card Reader/JSTU-9700
+0cd9 Hitachi Shin Din Cable, Ltd
+0cde Z-Com
+ 0001 M4Y-750
+ 0002 XI-725/726 Prism2.5 802.11b Adapter
+ 0003 Sagem 802.11b Dongle
+ 0004 Sagem 802.11b Dongle
+ 0005 XI-735 Prism3 802.11b Adapter
+ 0006 Medion 40900 802.11b Adapter
+ 0008 Sitecom Wireless Network Adapter 100G+ WL-125
+ 0009 (ZD1211)IEEE 802.11b+g Adapter
+ 0011 ZD1211
+ 0012 AR5523
+ 0013 AR5523 driver (no firmware)
+ 0014 NB 802.11g Wireless LAN Adapter(3887A)
+ 0015 Zoom Wireless-G
+ 0016 NB 802.11g Wireless LAN Adapter(3887A)
+ 0018 NB 802.11a/b/g Wireless LAN Adapter(3887A)
+ 001a ZD1211B
+ 001c 802.11b/g Wireless Network Adapter
+ 0020 Wi-Fi Wireless LAN Adapter
+ 0022 802.11b/g/n Wireless Network Adapter
+0ce9 pico Technology
+ 1001 PicoScope3204
+0cf1 e-Conn Electronic Co., Ltd
+0cf2 ENE Technology, Inc.
+0cf3 Atheros Communications, Inc.
+ 0001 AR5523
+ 0002 AR5523 (no firmware)
+ 0003 AR5523
+ 0004 AR5523 (no firmware)
+ 0005 AR5523
+ 0006 AR5523 (no firmware)
+0cf4 Fomtex Corp.
+0cf5 Cellink Co., Ltd
+0cf6 Compucable Corp.
+0cf7 ishoni Networks
+0cf8 Clarisys, Inc.
+ 0750 Claritel-i750 - vp
+0cf9 Central System Research Co., Ltd
+0cfa Inviso, Inc.
+0cfc Minolta-QMS, Inc.
+0cff SAFA MEDIA Co., Ltd.
+ 0320 SR-380N
+0d06 telos EDV Systementwicklung GmbH
+0d08 UTStarcom
+ 0602 DV007 [serial]
+ 0603 DV007 [storage]
+0d0b Contemporary Controls
+0d0c Astron Electronics Co., Ltd
+0d0d MKNet Corp.
+0d0e Hybrid Networks, Inc.
+0d0f Feng Shin Cable Co., Ltd
+0d10 Elastic Networks
+ 0001 StormPort (WDM)
+0d11 Maspro Denkoh Corp.
+0d12 Hansol Electronics, Inc.
+0d13 BMF Corp.
+0d14 Array Comm, Inc.
+0d15 OnStream b.v.
+0d16 Hi-Touch Imaging Technologies Co., Ltd
+ 0001 PhotoShuttle
+ 0002 Photo Printer 730 series
+ 0004 Photo Printer 63xPL/PS
+ 0100 Photo Printer 63xPL/PS
+ 0102 Photo Printer 64xPS
+ 0103 Photo Printer 730 series
+ 0104 Photo Printer 63xPL/PS
+ 0105 Photo Printer 64xPS
+ 0200 Photo Printer 64xDL
+0d17 NALTEC, Inc.
+0d18 coaXmedia
+0d19 Hank Connection Industrial Co., Ltd
+0d32 Leo Hui Electric Wire & Cable Co., Ltd
+0d33 AirSpeak, Inc.
+0d34 Rearden Steel Technologies
+0d35 Dah Kun Co., Ltd
+0d3a Posiflex Technologies, Inc.
+0d3c Sri Cable Technology, Ltd
+0d3d Tangtop Technology Co., Ltd
+ 0001 HID Keyboard
+0d3e Fitcom, inc.
+0d3f MTS Systems Corp.
+0d40 Ascor, Inc.
+0d41 Ta Yun Terminals Industrial Co., Ltd
+0d42 Full Der Co., Ltd
+0d46 Kobil Systems GmbH
+ 2012 KAAN Standard Plus (Smartcard reader)
+ 3003 mIDentity Light / KAAN SIM III
+ 4000 mIDentity (mass storage)
+ 4001 mIDentity Basic/Classic (composite device)
+ 4081 mIDentity Basic/Classic (installationless)
+0d49 Maxtor
+ 3000 Drive
+ 3010 3000LE Drive
+ 3100 Hi-Speed USB-IDE Bridge Controller
+ 5000 5000XT Drive
+ 5010 5000LE Drive
+ 5020 Mobile Hard Disk Drive
+ 7000 OneTouch
+ 7010 OneTouch
+0d4a NF Corp.
+0d4b Grape Systems, Inc.
+0d4c Tedas AG
+0d4d Coherent, Inc.
+0d4e Agere Systems Netherland BV
+ 047a WLAN Card
+ 1000 Wireless Card Model 0801
+ 1001 Wireless Card Model 0802
+0d4f EADS Airbus France
+0d50 Cleware GmbH
+ 0011 USB-Temp2 Thermometer
+0d51 Volex (Asia) Pte., Ltd
+0d53 HMI Co., Ltd
+0d54 Holon Corp.
+0d55 ASKA Technologies, Inc.
+0d56 AVLAB Technology, Inc.
+0d57 Solomon Microtech, Ltd
+0d5c Belkin
+ a002 F5D6050 802.11b Adapter
+0d5e Myacom, Ltd
+ 2346 BT Digital Access adapter
+0d5f CSI, Inc.
+0d60 IVL Technologies, Ltd
+0d61 Meilu Electronics (Shenzhen) Co., Ltd
+0d62 Darfon Electronics Corp.
+ 0003 Smartcard Reader
+ 0004 Filter Driver
+ 0306 M530 Mouse
+ 0800 Magic Wheel
+ 2021 AM805 Keyboard
+ 2026 TECOM Bluetooth Device
+ a100 Benq Mouse
+0d63 Fritz Gegauf AG
+0d64 DXG Technology Corp.
+ 0105 Dual Mode Digital Camera 1.3M
+ 0107 Horus MT-409 Camera
+ 0108 Dual Mode Digital Camera
+ 0202 Dual Mode Video Camera Device
+ 0303 DXG-305V Camera
+ 1001 SiPix Stylecam/UMAX AstraPix 320s
+ 1002 Fashion Cam 01 Dual-Mode DSC (Video Camera)
+ 1003 Fashion Cam Dual-Mode DSC (Controller)
+ 1021 D-Link DSC 350F
+ 1208 Dual Mode Still Camera Device
+ 2208 Mass Storage
+ 3105 Dual Mode Digital Camera Disk
+ 3108 Digicam Mass Storage Device
+0d65 KMJP Co., Ltd
+0d66 TMT
+0d67 Advanet, Inc.
+0d68 Super Link Electronics Co., Ltd
+0d69 NSI
+0d6a Megapower International Corp.
+0d6b And-Or Logic
+0d70 Try Computer Co., Ltd
+0d71 Hirakawa Hewtech Corp.
+0d72 Winmate Communication, Inc.
+0d73 Hit's Communications, Inc.
+0d76 MFP Korea, Inc.
+0d77 Power Sentry/Newpoint
+0d78 Japan Distributor Corp.
+0d7a MARX Datentechnik GmbH
+0d7b Wellco Technology Co., Ltd
+0d7c Taiwan Line Tek Electronic Co., Ltd
+0d7d Phison Electronics Corp.
+ 0100 PS1001/1011/1006/1026 Flash Disk
+ 0110 Gigabyte FlexDrive
+ 0120 Disk Pro 64MB
+ 0124 GIGABYTE Disk
+ 0240 I/O-Magic/Transcend 6-in-1 Card Reader
+ 110e NEC uPD720121/130 USB-ATA/ATAPI Bridge
+ 1240 Apacer 6-in-1 Card Reader 2.0
+ 1270 Wolverine SixPac 6000
+ 1300 Flash Disk
+ 1320 PS2031 Flash Disk
+ 1400 Attache 256MB USB 2.0 Flash Drive
+ 1420 PS2044 Pen Drive
+ 1470 Vosonic X's-Drive II+ VP2160
+ 1900 USB Thumb Drive
+0d7e American Computer & Digital Components
+ 2507 Hi-Speed USB-to-IDE Bridge Controller
+ 2517 Hi-Speed Mass Storage Device
+ 25c7 Hi-Speed USB-to-IDE Bridge Controller
+0d7f Essential Reality LLC
+0d80 H.R. Silvine Electronics, Inc.
+0d81 TechnoVision
+0d83 Think Outside, Inc.
+0d89 Oz Software
+0d8a King Jim Co., Ltd
+ 0101 TEPRA PRO
+0d8b Ascom Telecommunications, Ltd
+0d8c C-Media Electronics, Inc.
+ 0001 Audio Device
+ 0002 Composite Device
+ 0003 Sound Device
+ 0006 Storm HP-USB500 5.1 Headset
+ 000c Audio Adapter
+ 000d Composite Device
+ 000e Audio Adapter (Planet UP-100, Genius G-Talk)
+ 0102 CM106 Like Sound Device
+ 0103 Turtle Beach Audio Advantage Micro
+ 0201 CM6501
+ 5000 Mass Storage Controller
+ 5200 Mass Storage Controller(0D8C,5200)
+ b213 USB Phone CM109 (aka CT2000,VPT1000)
+0d8d Promotion & Display Technology, Ltd
+ 0234 V-234 Composite Device
+ 0550 V-550 Composite Device
+ 0551 V-551 Composite Device
+ 0552 V-552 Composite Device
+ 0651 V-651 Composite Device
+ 0652 V-652 Composite Device
+ 0653 V-653 Composite Device
+ 0654 V-654 Composite Device
+ 0655 V-655 Composite Device
+ 0656 V-656 Composite Device
+ 0657 V-657 Composite Device
+ 0658 V-658 Composite Device
+ 0659 V-659 Composite Device
+ 0660 V-660 Composite Device
+ 0661 V-661 Composite Device
+ 0662 V-662 Composite Device
+ 0850 V-850 Composite Device
+ 0851 V-851 Composite Device
+ 0852 V-852 Composite Device
+ 0901 V-901 Composite Device
+ 0902 V-902 Composite Device
+ 0903 V-903 Composite Device
+ 4754 Voyager DMP Composite Device
+ bb00 Bloomberg Composite Device
+ bb01 Bloomberg Composite Device
+ bb02 Bloomberg Composite Device
+ bb03 Bloomberg Composite Device
+ bb04 Bloomberg Composite Device
+ bb05 Bloomberg Composite Device
+ fffe Global Tuner Composite Device
+ ffff Voyager DMP Composite Device
+0d8e Global Sun Technology, Inc.
+ 0163 802.11g 54 Mbps Wireless Dongle
+ 1621 802.11b Wireless Adapter
+ 3762 802.11g Wireless Mini adapter
+ 3763 802.11g Wireless dongle
+ 7100 802.11b Adapter
+ 7110 WL-210
+ 7801 AR5523
+ 7802 AR5523 (no firmware)
+ 7811 AR5523
+ 7812 AR5523 (no firmware)
+ 7a01 PRISM25 802.11b Adapter
+0d8f Pitney Bowes
+0d90 Sure-Fire Electrical Corp.
+0d96 Skanhex Technology, Inc.
+ 0000 Jenoptik JD350 video
+ 3300 SX330z Camera
+ 4100 SX410z Camera
+ 4102 MD 9700 Camera
+ 4104 Jenoptik JD-4100z3s
+ 410a Medion 9801/Novatech SX-410z
+ 5200 SX-520z Camera
+0d97 Santa Barbara Instrument Group
+ 0001 SBIG Astronomy Camera (without firmware)
+ 0101 SBIG Astronomy Camera (with firmware)
+0d98 Mars Semiconductor Corp.
+ 0300 Avaya Wireless Card
+0d99 Trazer Technologies, Inc.
+0d9a RTX Telecom AS
+ 0001 Bluetooth Device
+0d9b Tat Shing Electrical Co.
+0d9c Chee Chen Hi-Technology Co., Ltd
+0d9d Sanwa Supply, Inc.
+0d9e Avaya
+ 0300 Wireless Card
+0d9f Powercom Co., Ltd
+0da0 Danger Research
+0da1 Suzhou Peter's Precise Industrial Co., Ltd
+0da2 Land Instruments International, Ltd
+0da3 Nippon Electro-Sensory Devices Corp.
+0da4 Polar Electro OY
+ 0001 Interface
+0da7 IOGear, Inc.
+0da8 softDSP Co., Ltd
+ 0001 SDS 200A Oscilloscope
+0dab Cubig Group
+ 0100 DVR/CVR-M140 MP3 Player
+0dad Westover Scientific
+0db0 Micro Star International
+ 1020 PC2PC WLAN Card
+ 1967 Bluetooth Dongle
+ 4011 Medion Flash XL V2.0 Card Reader
+ 4600 802.11b/g Turbo Wireless Adapter
+ 5501 Mass Storage Device
+ 5502 Mass Storage Device
+ 5513 MP3 Player
+ 5515 MP3 Player
+ 5516 MP3 Player
+ 6823 UB11B/MS-6823 802.11b Wi-Fi adapter
+ 6826 IEEE 802.11g Wireless Network Adapter
+ 6855 Bluetooth Device
+ 6861 MSI-6861 802.11g WiFi adapter
+ 6865 RT2570
+ 6869 RT2570
+ 6874 RT2573
+ 6877 RT2573
+ 6881 Bluetooth Class I EDR Device
+ 688a Bluetooth Class I EDR Device
+ 6970 Bluetooth adapter
+ 697a Bluetooth Dongle
+ 6982 Medion Flash XL Card Reader
+ a861 RT2573
+ a874 RT2573
+ a970 Bluetooth dongle
+ a97a Bluetooth EDR Device
+ b970 Bluetooth EDR Device
+ b97a Bluetooth EDR Device
+0db1 Wen Te Electronics Co., Ltd
+0db2 Shian Hwi Plug Parts, Plastic Factory
+0db3 Tekram Technology Co., Ltd
+0db4 Chung Fu Chen Yeh Enterprise Corp.
+0db7 ELCON Systemtechnik
+ 0002 Goldpfeil P-LAN
+0dbe Jiuh Shiuh Precision Industry Co., Ltd
+0dbf Quik Tech Solutions
+ 0002 SmartDongle Security Key
+ 0200 HDD Storage Solution
+ 021b USB-2.0 IDE Adapter
+ 0300 Storage Adapter
+ 0333 Storage Adapter
+ 0707 ZIV Drive
+0dc0 Great Notions
+0dc1 Tamagawa Seiki Co., Ltd
+0dc3 Athena Smartcard Solutions, Inc.
+ 0801 ASEDrive III
+ 0802 ASEDrive IIIe
+ 1104 ASEDrive IIIe KB
+ 1701 ASEKey
+ 1702 ASEKey
+0dc4 Macpower Peripherals, Ltd
+ 0040 Mass Storage Device
+ 0041 Mass Storage Device
+ 0042 Mass Storage Device
+ 0101 Hi-Speed Mass Storage Device
+0dc5 SDK Co., Ltd
+0dc6 Precision Squared Technology Corp.
+0dc7 First Cable Line, Inc.
+0dcd NetworkFab Corp.
+ 0001 Remote Interface Adapter
+ 0002 High Bandwidth Codec
+0dd0 Access Solutions
+ 1002 Triple Talk Speech Synthesizer
+0dd1 Contek Electronics Co., Ltd
+0dd2 Power Quotient International Co., Ltd
+ 0003 Mass Storage (P)
+0dd3 MediaQ
+0dd4 Custom Engineering SPA
+0dd5 California Micro Devices
+0dd7 Kocom Co., Ltd
+0dd8 Netac Technology Co., Ltd
+ 1060 USB-CF-Card
+ e007 OnlyDisk U222 Pendrive
+0dd9 HighSpeed Surfing
+0dda Integrated Circuit Solution, Inc.
+ 0001 Multi-Card Reader 6in1
+ 0002 Multi-Card Reader 7in1
+ 0003 Flash Disk
+ 0005 Internal Multi-Card Reader 6in1
+ 0008 SD single card reader
+ 0009 MS single card reader
+ 000a MS+SD Dual Card Reader
+ 000b SM single card reader
+ 0101 All-In-One Card Reader
+ 0102 All-In-One Card Reader
+ 0301 MP3 Player
+ 0302 Multi-Card MP3 Player
+ 1001 Multi-Flash Disk
+ 2001 Multi-Card Reader
+ 2002 Q018 default PID
+ 2003 Multi-Card Reader
+ 2005 Datalux DLX-1611 16in1 Card Reader
+ 2006 All-In-One Card Reader
+ 2007 USB to ATAPI bridge
+ 2008 All-In-One Card Reader
+ 2013 SD/MS Combo Card Reader
+ 2014 SD/MS Single Card Reader
+ 2023 card reader SD/MS DEMO board with ICSI brand name (MaskROM version)
+ 2024 card reader SD/MS DEMO board with Generic brand name (MaskROM version)
+ 2026 USB2.0 Card Reader
+ 2027 USB 2.0 Card Reader
+ 2315 UFD MP3 player (model 2)
+ 2318 UFD MP3 player (model 1)
+ 2321 UFD MP3 player
+0ddb Tamarack, Inc.
+0ddd Datelink Technology Co., Ltd
+0dde Ubicom, Inc.
+0de0 BD Consumer Healthcare
+0dea UTECH Electronic (D.G.) Co., Ltd.
+0ded Novasonics
+0dee Lifetime Memory Products
+ 4010 Storage Adapter
+0def Full Rise Electronic Co., Ltd
+0df6 Sitecom Europe B.V.
+ 0001 C-Media VOIP Device
+ 0004 Bluetooth 2.0 Adapter 100m
+ 0007 Bluetooth 2.0 Adapter 10m
+ 000b Bluetooth 2.0.USB Adapter DFU
+ 000d WL-168 Wireless Network Adapter 54g
+ 0017 WL-182
+ 0019 Bluetooth 2.0 adapter 10m CN-512v2 001
+ 001a Bluetooth 2.0 adapter 100m CN-521v2 001
+ 061c LN-028
+ 21f4 44 St Bluetooth Device
+ 2200 Sitecom bluetooth2.0 class 2 dongle CN-512
+ 2208 Sitecom bluetooth2.0 class 2 dongle CN-520
+ 2209 Sitecom bluetooth2.0 class 1 dongle CN-521
+ 9071 zd1211 802.11g Adapter
+ 9075 ZD1211B
+ 90ac WL-172
+ 9712 WL-113 rev 2
+0df7 Mobile Action Technology, Inc.
+ 0620 MA-620 Infrared Adapter
+ 0700 MA-700 Bluetooth Adapter
+ 0720 MA-720 Bluetooth Adapter
+ 0722 Bluetooth Dongle
+ 0800 Data Cable
+ 0820 Data Cable
+ 1800 Generic Card Reader
+ 1802 Card Reader
+0dfa Toyo Communication Equipment Co., Ltd
+0dfc GeneralTouch Technology Co., Ltd
+ 0001 Touchscreen
+0e03 Nippon Systemware Co., Ltd
+0e08 Winbest Technology Co., Ltd
+0e0c Gesytec
+ 0101 LonUSB LonTalk Network Adapter
+0e16 JMTek, LLC
+0e17 Walex Electronic, Ltd
+0e1b Crewave
+0e21 Cowon Systems, Inc.
+ 0300 iAudio CW200
+ 0400 MP3 Player
+ 0510 iAudio X5
+ 0513 iAudio X5, side USB port
+ 0520 iAudio M5
+ 0700 iAudio U3
+0e22 Symbian Ltd.
+0e23 Liou Yuane Enterprise Co., Ltd
+0e25 VinChip Systems, Inc.
+0e26 J-Phone East Co., Ltd
+0e30 HeartMath LLC
+0e34 Micro Computer Control Corp.
+0e35 3Pea Technologies, Inc.
+0e36 TiePie engineering
+ 0008 Handyscope HS3
+ 0009 Handyscope HS3 (br)
+ 000a Handyscope HS4
+ 000b Handyscope HS4 (br)
+ 000e Handyscope HS4 Diff
+ 000f Handyscope HS4 Diff (br)
+ 0010 Handyscope HS2
+ 0018 Handyprobe HP2
+ 0042 TiePieSCOPE HS801
+ 00fd USB To Parallel adapter
+ 00fe USB To Parallel adapter
+0e38 Stratitec, Inc.
+0e39 Smart Modular Technologies, Inc.
+ 0137 Bluetooth Device
+0e3a Neostar Technology Co., Ltd
+ 1100 CW-1100 Wireless Network Adapter
+0e3b Mansella, Ltd
+0e41 Line6, Inc.
+ 4250 BassPODxt
+ 4252 BassPODxt Pro
+ 4642 BassPODxt Live
+ 4650 PODxt Live
+ 4750 GuitarPort
+ 5044 PODxt
+ 5050 PODxt Pro
+ 534d SeaMonkey
+0e44 Sun-Riseful Technology Co., Ltd.
+0e48 Julia Corp., Ltd
+ 0100 CardPro SmartCard Reader
+0e4a Shenzhen Bao Hing Electric Wire & Cable Mfr. Co.
+0e4c Radica Games, Ltd
+0e55 Speed Dragon Multimedia, Ltd
+ 110b MS3303H USB-to-Serial Bridge
+0e56 Kingston Technology Company, Inc.
+ 6021 K-PEX 100
+0e5a Active Co., Ltd
+0e5b Union Power Information Industrial Co., Ltd
+0e5c Bitland Information Technology Co., Ltd
+ 6118 LCD Device
+ 6119 remote receive and control device
+ 6441 C-Media Sound Device
+0e5d Neltron Industrial Co., Ltd
+0e66 Hawking
+ 400b UF100 10/100 Network Adapter
+ 400c UF100 Ethernet [pegasus2]
+0e67 Fossil, Inc.
+ 0002 Wrist PDA
+0e6a Megawin Technology Co., Ltd
+0e70 Tokyo Electronic Industry Co., Ltd
+0e72 Hsi-Chin Electronics Co., Ltd
+0e75 TVS Electronics, Ltd
+0e79 Archos, Inc.
+ 1106 Pocket Medai Assistant - PMA400
+0e7b On-Tech Industry Co., Ltd
+0e7e Gmate, Inc.
+ 0001 Yopy 3000 PDA
+ 1001 YP3X00 PDA
+0e82 Ching Tai Electric Wire & Cable Co., Ltd
+0e83 Shin An Wire & Cable Co.
+0e8c Well Force Electronic Co., Ltd
+0e8d MediaTek Inc.
+0e8f GreenAsia Inc.
+ 0012 Joystick
+0e90 WiebeTech, LLC
+ 0100 Storage Adapter V1
+0e91 VTech Engineering Canada, Ltd
+0e92 C's Glory Enterprise Co., Ltd
+0e93 eM Technics Co., Ltd
+0e95 Future Technology Co., Ltd
+0e96 Aplux Communications, Ltd
+ c001 TRUST 380 USB2 SPACEC@M
+0e97 Fingerworks, Inc.
+0e98 Advanced Analogic Technologies, Inc.
+0e99 Parallel Dice Co., Ltd
+0e9a TA HSING Industries, Ltd
+0e9b ADTEC Corp.
+0e9c Streamzap, Inc.
+ 0000 Streamzap Remote Control
+0e9f Tamura Corp.
+0ea0 Ours Technology, Inc.
+ 2126 7-in-1 Card Reader
+ 2168 Transcend JetFlash 2.0 / Astone USB Drive
+ 6803 OTI-6803 Flash Disk
+ 6808 OTI-6808 Flash Disk
+ 6828 OTI-6828 Flash Disk
+0ea6 Nihon Computer Co., Ltd
+0ea7 MSL Enterprises Corp.
+0ea8 CenDyne, Inc.
+0ead Humax Co., Ltd
+0eb0 NovaTech
+ 9020 NovaTech NV-902W
+ 9021 RT2573
+0eb1 WIS Technologies, Inc.
+ 6666 WinFast WalkieTV TV Loader
+ 6668 WinFast WalkieTV TV Loader
+ 7007 WinFast WalkieTV WDM Capture
+0eb2 Y-S Electronic Co., Ltd
+0eb3 Saint Technology Corp.
+0eb7 Endor AG
+0ebe VWeb Corp.
+0ebf Omega Technology of Taiwan, Inc.
+0ec0 LHI Technology (China) Co., Ltd
+0ec1 Abit Computer Corp.
+0ec2 Sweetray Industrial, Ltd
+0ec3 Axell Co., Ltd
+0ec4 Ballracing Developments, Ltd
+0ec5 GT Information System Co., Ltd
+0ec6 InnoVISION Multimedia, Ltd
+0ec7 Theta Link Corp.
+ 1008 So., Show 301 Digital Camera
+0ecd Lite-On IT Corp.
+ 1400 CD\RW 40X
+0ece TaiSol Electronics Co., Ltd
+0ecf Phogenix Imaging, LLC
+0ed1 WinMaxGroup
+ 6660 USB Flash Disk 64M-C
+ 6680 USB Flash Disk 64M-B
+ 7634 MP3 Player
+0ed2 Kyoto Micro Computer Co., Ltd
+0ed3 Wing-Tech Enterprise Co., Ltd
+0ed5 Fiberbyte
+ e000 USB-inSync Device
+ f000 Fiberbyte USB-inSync Device
+ f201 Fiberbyte USB-inSync DAQ-2500X
+0eda Noriake Itron Corp.
+0edf e-MDT Co., Ltd
+ 2060 FID irock! 100 Series
+0ee0 Shima Seiki Mfg., Ltd
+0ee1 Sarotech Co., Ltd
+0ee2 AMI Semiconductor, Inc.
+0ee3 ComTrue Technology Corp.
+ 1000 Image Tank 1.5
+0ee4 Sunrich Technology, Ltd
+0eee Digital Stream Technology, Inc.
+ 8810 Mass Storage Drive
+0eef D-WAV Scientific Co., Ltd
+ 0001 eGalax TouchScreen
+ 0002 Touchscreen Controller(Professional)
+0ef0 Hitachi Cable, Ltd
+0ef1 Aichi Micro Intelligent Corp.
+0ef2 I/O Magic Corp.
+0ef3 Lynn Products, Inc.
+0ef4 DSI Datotech
+0ef5 PointChips
+ 2202 Flash Disk
+ 2366 Flash Disk
+0ef6 Yield Microelectronics Corp.
+0ef7 SM Tech Co., Ltd (Tulip)
+0efd Oasis Semiconductor
+0efe Wem Technology, Inc.
+0f06 Visual Frontier Enterprise Co., Ltd
+0f08 CSL Wire & Plug (Shen Zhen) Co.
+0f0c CAS Corp.
+0f0d Hori Co., Ltd
+0f0e Energy Full Corp.
+0f12 Mars Engineering Corp.
+0f13 Acetek Technology Co., Ltd
+0f19 Oracom Co., Ltd
+0f1b Onset Computer Corp.
+0f1c Funai Electric Co., Ltd
+0f1d Iwill Corp.
+0f21 IOI Technology Corp.
+0f22 Senior Industries, Inc.
+0f23 Leader Tech Manufacturer Co., Ltd
+0f24 Flex-P Industries, Snd., Bhd.
+0f2d ViPower, Inc.
+0f2e Geniality Maple Technology Co., Ltd
+0f2f Priva Design Services
+0f30 Jess Technology Co., Ltd
+ 001c PS3 Guitar Controller Dongle
+ 0110 10-Button Joypad
+0f31 Chrysalis Development
+0f32 YFC-BonEagle Electric Co., Ltd
+0f37 Kokuyo Co., Ltd
+0f38 Nien-Yi Industrial Corp.
+0f3d Airprime, Incorporated
+ 0112 CDMA 1xEVDO PC Card, PC 5220
+0f41 RDC Semiconductor Co., Ltd
+0f42 Nital Consulting Services, Inc.
+0f44 Polhemus
+ ef11 Patriot (firmware not loaded)
+ ef12 Patriot
+ ff11 Liberty (firmware not loaded)
+ ff12 Liberty
+0f4b St. John Technology Co., Ltd
+0f4c WorldWide Cable Opto Corp.
+0f4d Microtune, Inc.
+ 1000 Bluetooth Dongle
+0f4e Freedom Scientific
+0f52 Wing Key Electrical Co., Ltd
+0f53 Dongguan White Horse Cable Factory, Ltd
+0f54 Kawai Musical Instruments Mfg. Co., Ltd
+0f55 AmbiCom, Inc.
+0f5c Prairiecomm, Inc.
+0f5d NewAge International, LLC
+ 9455 Compact Drive
+0f5f Key Technology Corp.
+0f60 NTK, Ltd
+0f61 Varian, Inc.
+0f62 Acrox Technologies Co., Ltd
+ 1001 Targus Mini Trackball Optical Mouse
+0f68 Kobe Steel, Ltd
+0f69 Dionex Corp.
+0f6a Vibren Technologies, Inc.
+0f6e INTELLIGENT SYSTEMS
+ 0100 GameBoy Color Emulator
+ 0201 GameBoy Advance Flash Gang Writer
+ 0202 GameBoy Advance Capture
+ 0300 Gamecube DOL Viewer
+ 0400 NDS Emulator
+ 0401 NDS UIC
+ 0402 NDS Writer
+ 0403 NDS Capture
+ 0404 NDS Emulator (Lite)
+0f73 DFI
+0f7c DQ Technology, Inc.
+0f7d NetBotz, Inc.
+0f7e Fluke Corp.
+0f88 VTech Holdings, Ltd
+ 3012 RT2570
+ 3014 ZD1211B
+0f8b Yazaki Corp.
+0f8c Young Generation International Corp.
+0f8d Uniwill Computer Corp.
+0f8e Kingnet Technology Co., Ltd
+0f8f Soma Networks
+0f97 CviLux Corp.
+0f98 CyberBank Corp.
+0f9c Hyun Won, Inc.
+ 0301 M-Any Premium DAH-610 MP3/WMA Player
+ 0332 mobiBLU DAH-1200 MP3/Ogg Player
+0f9e Lucent Technologies
+0fa3 Starconn Electronic Co., Ltd
+0fa4 ATL Technology
+0fa5 Sotec Co., Ltd
+0fa7 Epox Computer Co., Ltd
+0fa8 Logic Controls, Inc.
+0faf Winpoint Electronic Corp.
+0fb0 Haurtian Wire & Cable Co., Ltd
+0fb1 Inclose Design, Inc.
+0fb2 Juan-Chern Industrial Co., Ltd
+0fb8 Wistron Corp.
+ 0002 eHome Infrared Receiver
+0fb9 AACom Corp.
+0fba San Shing Electronics Co., Ltd
+0fbb Bitwise Systems, Inc.
+0fc1 Mitac Internatinal Corp.
+0fc2 Plug and Jack Industrial, Inc.
+0fc5 Delcom Engineering
+ 1222 I/O Development Board
+0fc6 Dataplus Supplies, Inc.
+0fca Research In Motion, Ltd.
+ 0001 Blackberry Handheld
+0fce Sony Ericsson Mobile Communications AB
+ 1010 WMC Modem
+ d008 V800-Vodafone 802SE WMC Modem
+ d016 K750i Phone
+ d017 K608i Phone
+ d019 VDC EGPRS Modem
+ d025 520 WMC Data Modem
+ d038 W850i Phone
+ d041 K510i Phone
+ d042 W810i Phone
+ d046 K610i Phone
+0fcf Dynastream Innovations, Inc.
+0fd0 Tulip Computers B.V.
+0fd1 Giant Electronics Ltd.
+0fd4 Tenovis GmbH & Co., KG
+0fd5 Direct Access Technology, Inc.
+0fdc Micro Plus
+0fe4 IN-Tech Electronics, Ltd
+0fe5 Greenconn (U.S.A.), Inc.
+0fe9 DVICO
+ db00 FusionHDTV DVB-T (MT352+LgZ201) (uninitialized)
+ db01 FusionHDTV DVB-T (MT352+LgZ201) (initialized)
+ db10 FusionHDTV DVB-T (MT352+Thomson7579) (uninitialized)
+ db11 FusionHDTV DVB-T (MT352+Thomson7579) (initialized)
+0fea United Computer Accessories
+0feb CRS Electronic Co., Ltd
+0fec UMC Electronics Co., Ltd
+0fed Access Co., Ltd
+0fee Xsido Corp.
+0fef MJ Research, Inc.
+0ff6 Core Valley Co., Ltd
+0ff7 CHI SHING Computer Accessories Co., Ltd
+0fff Aopen, Inc.
+1000 Speed Tech Corp.
+1001 Ritronics Components (S) Pte., Ltd
+1003 Sigma Corp.
+ 0100 Sigma SD10
+1004 LG Electronics, Inc.
+ 1fae U8120 3G Cellphone
+ 6000 VX4400/VX6000 Cellphone
+ 6005 T5100
+ 6800 CDMA Modem
+ 7000 LG LDP-7024D(LD)USB
+1005 Apacer Technology, Inc.
+ 1001 MP3 Player
+ 1004 MP3 Player
+ 1006 MP3 Player
+ b113 Handy Steno 2.0/HT203
+ b223 CD-RW + 6 in 1 Card Reader Digital Storage / Converter
+1006 iRiver, Ltd.
+ 3001 iHP-100
+ 3002 iHP-120/140 MP3 Player
+ 3003 H320/H340
+ 3004 H340 (mtp)
+1009 Emuzed, Inc.
+ 000e eHome Infrared Receiver
+ 0013 Angel MPEG Device
+ 0015 Lumanate Wave PAL SECAM DVBT Device
+ 0016 Lumanate Wave NTSC/ATSC Combo Device
+100a AV Chaseway, Ltd
+ 2402 MP3 Player
+ 2404 MP3 Player
+ 2405 MP3 Player
+ 2406 MP3 Player
+ a0c0 MP3 Player
+100b Chou Chin Industrial Co., Ltd
+100d Netopia, Inc.
+ 3342 Cayman 3352 DSL Modem
+ 3382 3380 Series Network Interface
+ cb01 Cayman 3341 Ethernet DSL Router
+1010 Fukuda Denshi Co., Ltd
+1011 Mobile Media Tech.
+ 0001 AccFast Mp3
+1012 SDKM Fibres, Wires & Cables Berhad
+1013 TST-Touchless Sensor Technology AG
+1014 Densitron Technologies PLC
+1015 Softronics Pty., Ltd
+1016 Xiamen Hung's Enterprise Co., Ltd
+1017 Speedy Industrial Supplies, Pte., Ltd
+1019 Elitegroup Computer Systems (ECS)
+ 0c55 USB Flash Reader, Desknote UCR-61S2B
+1020 Labtec
+ 000a Wireless Optical Mouse
+1022 Shinko Shoji Co., Ltd
+1025 Hyper-Paltek
+ 005e USB DVB-T device
+ 005f USB DVB-T device
+ 0300 MP3 Player
+ 0350 MP3 Player
+1026 Newly Corp.
+1027 Time Domain
+1028 Inovys Corp.
+1029 Atlantic Coast Telesys
+102a Ramos Technology Co., Ltd
+102b Infotronic America, Inc.
+102c Etoms Electronics Corp.
+ 6251 Q-Cam
+102d Winic Corp.
+1031 Comax Technology, Inc.
+1032 C-One Technology Corp.
+1033 Nucam Corp.
+ 0068 3,5'' HDD case MD-231
+1038 Ideazon, Inc.
+ 0100 Zboard
+1039 devolo AG
+ 2140 dsl+ 1100 duo
+103d Stanton
+ 0100 ScratchAmp
+ 0101 ScratchAmp
+1043 iCreate Technologies Corp.
+ 160f Wireless Network Adapter
+ 4901 AV-836 Video Capture Device
+ 8006 Flash Disk 32-256 MB
+1044 Chu Yuen Enterprise Co., Ltd
+ 7001 U7000 TV tuner device
+ 8001 GN-54G
+ 8002 GN-BR402W
+ 8003 GN-WLBM101
+ 8004 GN-WLBZ101 802.11b Adapter
+ 8005 GN-WLBZ201 802.11b Adapter
+ 8006 GN-WBZB-M 802.11b Adapter
+ 8007 GN-WBKG
+ 8008 GN-WB01GS
+ 800a GN-WI05GS
+ 800b GN-WB30N 802.11n WLAN Card
+1046 Winbond Electronics Corp. [hex]
+ 8901 Bluetooth Device
+ 9967 W9967CF/W9968CF WebCam IC
+1048 Targus Group International
+104c AMCO TEC International, Inc.
+1053 Immanuel Electronics Co., Ltd
+1054 BMS International Beheer N.V.
+ 5004 DSL 7420 Loader
+ 5005 DSL 7420 LAN Modem
+1055 Complex Micro Interconnection Co., Ltd
+1056 Hsin Chen Ent Co., Ltd
+1057 ON Semiconductor
+1058 Western Digital Technologies, Inc.
+ 0200 Firewire USB Combo
+ 0400 External HDD
+ 0500 hub
+ 0702 Passport External HDD
+ 0901 MyBook External HDD
+ 1001 External Hard Disk
+1059 Giesecke & Devrient GmbH
+ 000b StarSign Bio Token 3.0
+105c Hong Ji Electric Wire & Cable (Dongguan) Co., Ltd
+105d Delkin Devices, Inc.
+105e Valence Semiconductor Design, Ltd
+105f Chin Shong Enterprise Co., Ltd
+1060 Easthome Industrial Co., Ltd
+1063 Motorola Electronics Taiwan, Ltd [hex]
+ 1555 MC141555 Hub
+ 4100 SB4100 USB Cable Modem
+1065 CCYU Technology
+ 0020 USB-DVR2 Dev Board
+ 2136 EasyDisk ED1064
+106a Loyal Legend, Ltd
+106c Curitel Communications, Inc.
+ 1101 CDMA 2000 1xRTT USB modem (HX-550C)
+ 1102 Packet Service
+ 1103 Packet Service Diagnostic Serial Port (WDM)
+ 1104 Packet Service Diagnostic Serial Port (WDM)
+ 1105 Composite Device
+ 1106 Packet Service Diagnostic Serial Port (WDM)
+ 1301 Composite Device
+ 1302 Packet Service Diagnostic Serial Port (WDM)
+ 1303 Packet Service
+ 1304 Packet Service
+ 1401 Composite Device
+ 1402 Packet Service
+ 1403 Packet Service Diagnostic Serial Port (WDM)
+ 1501 Packet Service
+ 1502 Packet Service Diagnostic Serial Port (WDM)
+ 1503 Packet Service
+ 1601 Packet Service
+ 1602 Packet Service Diagnostic Serial Port (WDM)
+ 1603 Packet Service
+ 2101 AudioVox 8900 Cell Phone
+ 2102 Packet Service
+ 2103 Packet Service Diagnostic Serial Port (WDM)
+ 2301 Packet Service
+ 2302 Packet Service Diagnostic Serial Port (WDM)
+ 2303 Packet Service
+ 2401 Packet Service Diagnostic Serial Port (WDM)
+ 2402 Packet Service
+ 2403 Packet Service Diagnostic Serial Port (WDM)
+ 2501 Packet Service
+ 2502 Packet Service Diagnostic Serial Port (WDM)
+ 2503 Packet Service
+ 2601 Packet Service
+ 2602 Packet Service Diagnostic Serial Port (WDM)
+ 2603 Packet Service
+ 3701 Broadband Wireless modem
+ 3702 Pantech PX-500
+ 3eb4 Packet Service Diagnostic Serial Port (WDM)
+ 4101 Packet Service Diagnostic Serial Port (WDM)
+ 4102 Packet Service
+ 4301 Composite Device
+ 4302 Packet Service Diagnostic Serial Port (WDM)
+ 4401 Composite Device
+ 4402 Packet Service
+ 4501 Packet Service
+ 4502 Packet Service Diagnostic Serial Port (WDM)
+ 4601 Composite Device
+ 4602 Packet Service Diagnostic Serial Port (WDM)
+ 5101 Packet Service
+ 5102 Packet Service Diagnostic Serial Port (WDM)
+ 5301 Packet Service Diagnostic Serial Port (WDM)
+ 5302 Packet Service
+ 5401 Packet Service
+ 5402 Packet Service Diagnostic Serial Port (WDM)
+ 5501 Packet Service Diagnostic Serial Port (WDM)
+ 5502 Packet Service
+ 5601 Packet Service Diagnostic Serial Port (WDM)
+ 5602 Packet Service
+ 7101 Composite Device
+ 7102 Packet Service
+ a000 Packet Service
+ a001 Packet Service Diagnostic Serial Port (WDM)
+ c100 Packet Service
+ c200 Packet Service
+ c500 Packet Service Diagnostic Serial Port (WDM)
+ e200 Packet Service
+106d San Chieh Manufacturing, Ltd
+106e ConectL
+106f Money Controls
+1076 GCT Semiconductor, Inc.
+ 0031 Bluetooth Device
+ 0032 Bluetooth Device
+107d Arlec Australia, Ltd
+107e Midoriya Electric Co., Ltd
+107f KidzMouse, Inc.
+1082 Shin-Etsukaken Co., Ltd
+1083 Canon Electronics, Inc.
+1084 Pantech Co., Ltd
+108a Chloride Power Protection
+108b Grand-tek Technology Co., Ltd
+108c Robert Bosch GmbH
+108e Lotes Co., Ltd.
+1099 Surface Optics Corp.
+109a DATASOFT Systems GmbH
+109f eSOL Co., Ltd
+ 3163 Trigem Mobile SmartDisplay84
+ 3164 Trigem Mobile SmartDisplay121
+10a0 Hirotech, Inc.
+10a3 Mitsubishi Materials Corp.
+10a9 SK Teletech Co., Ltd
+10aa Cables To Go
+10ab USI Co., Ltd
+ 1002 Bluetooth Device
+ 1003 BC02-EXT in DFU
+ 1005 Bluetooth Adptr
+ 1006 BC04-EXT in DFU
+ 10c5 Sony-Ericsson / Samsung DataCable
+10ac Honeywell, Inc.
+10ae Princeton Technology Corp.
+10af Liebert Corp.
+ 0000 UPS
+ 0001 PowerSure PSA UPS
+ 0002 PowerSure PST UPS
+ 0003 PowerSure PSP UPS
+ 0004 PowerSure PSI UPS
+ 0005 UPStation GXT 2U UPS
+ 0006 UPStation GXT UPS
+ 0007 Nfinity Power Systems UPS
+ 0008 PowerSure Interactive UPS
+10b5 Comodo (PLX?)
+ 9060 Test Board
+10b8 DiBcom
+ 0bb8 DiBcom USB DVB-T reference design (MOD300) (cold)
+ 0bb9 DiBcom USB DVB-T reference design (MOD300) (warm)
+ 0bc6 DiBcom USB2.0 DVB-T reference design (MOD3000P) (cold)
+ 0bc7 DiBcom USB2.0 DVB-T reference design (MOD3000P) (warm)
+10bb TM Technology, Inc.
+10bc Dinging Technology Co., Ltd
+10bd TMT Technology, Inc.
+ 1427 Ethernet
+10bf SmartHome
+ 0001 SmartHome PowerLinc
+10c4 Cygnal Integrated Products, Inc.
+ 0002 F32x USBXpress Device
+ 80a9 CP210x to UART Bridge Controller
+ 80ca ATM2400 Sensor Device
+ ea60 CP210x Composite Device
+10c5 Sanei Electric, Inc.
+10c6 Intec, Inc.
+10cb Eratech
+10cc GBM Connector Co., Ltd
+ 1101 MP3 Player
+10cd Kycon, Inc.
+10ce Silicon Labs
+ ea6a MobiData EDGE USB Modem
+10cf Velleman Components, Inc.
+ 5500 8055 Experiment Interface Board (address=0)
+ 5501 8055 Experiment Interface Board (address=1)
+ 5502 8055 Experiment Interface Board (address=2)
+ 5503 8055 Experiment Interface Board (address=3)
+10d1 Hottinger Baldwin Measurement
+ 0101 USB-Module for Spider8, CP32
+ 0202 CP22 - Communication Processor
+ 0301 CP42 - Communication Processor
+10d4 Man Boon Manufactory, Ltd
+10d5 Uni Class Technology Co., Ltd
+10d6 Actions Semiconductor Co., Ltd
+ 1000 MP3 Player
+ 1100 MPMan MP-Ki 128 MP3 Player/Recorder
+ 1101 D-Wave 2GB MP4 Player
+ 8888 ADFU Device
+ ff51 ADFU Device
+10de Authenex, Inc.
+10df In-Win Development, Inc.
+10e0 Post-Op Video, Inc.
+10e1 CablePlus, Ltd
+10e2 Nada Electronics, Ltd
+10ec Vast Technologies, Inc.
+10f5 Turtle Beach
+ 0200 Audio Advantage Roadie
+10fb Pictos Technologies, Inc.
+10fd Anubis Electronics, Ltd
+ 804d Typhoon Webshot II Webcam [zc0301]
+ 8050 FlyCAM-USB 300 XP2
+ de00 WinFast WalkieTV WDM Capture Driver.
+1100 VirTouch, Ltd
+ 0001 VTPlayer VTP-1 Braille Mouse
+1101 EasyPass Industrial Co., Ltd
+ 0001 FSK Electronics Super GSM Reader
+1108 Brightcom Technologies, Ltd
+1110 Analog Devices Canada, Ltd (Allied Telesyn)
+ 5c01 Huawei MT-882 Remote NDIS Network Device
+ 6489 ADSL ETH/USB RTR
+ 9000 ADSL LAN Adapter
+ 9001 ADSL Loader
+ 900f AT-AR215 DSL Modem
+ 9010 AT-AR215 DSL Modem
+ 9021 ADSL WAN Adapter
+ 9022 ADSL Loader
+ 9023 ADSL WAN Adapter
+ 9024 ADSL Loader
+ 9031 ADSL LAN Adapter
+ 9032 ADSL Loader
+1111 Pandora International Ltd.
+ 8888 Evolution Device
+1112 YM ELECTRIC CO., Ltd
+1113 Medion AG
+111e VSO Electric Co., Ltd
+112e Master Hill Electric Wire and Cable Co., Ltd
+112f Cellon International, Inc.
+1130 Tenx Technology, Inc.
+ f211 USB audio headset
+1131 Integrated System Solution Corp.
+ 1001 KY-BT100 Bluetooth Adapter
+ 1002 Bluetooth Device
+ 1003 Bluetooth Device
+ 1004 Bluetooth Device
+1132 Toshiba Corp., Digital Media Equipment [hex]
+ 4331 PDR-M4/M5/M70 Digital Camera
+ 4332 PDR-M60 Digital Camera
+ 4333 PDR-M2300/PDR-M700
+ 4334 PDR-M65
+ 4335 PDR-M61
+ 4337 PDR-M11
+ 4338 PDR-M25
+113c Arin Tech Co., Ltd
+113d Mapower Electronics Co., Ltd
+1141 V One Multimedia, Pte., Ltd
+1142 CyberScan Technologies, Inc.
+1145 Japan Radio Company
+ 0001 AirH PHONE AH-J3001V/J3002V
+1146 Shimane SANYO Electric Co., Ltd.
+1147 Ever Great Electric Wire and Cable Co., Ltd
+114b Sphairon Access Systems GmbH
+ 0110 Turbolink UB801R WLAN USB Adapter
+114c Tinius Olsen Testing Machine Co., Inc.
+114d Alpha Imaging Technology Corp.
+115b Salix Technology Co., Ltd.
+1162 Secugen Corp.
+1163 DeLorme Publishing, Inc.
+ 0100 Earthmate GPS
+1164 YUAN High-Tech Development Co., Ltd
+ 0300 ELSAVISION 460D
+ 0601 Analog TV Tuner
+ 0900 TigerBird BMP837 USB2.0 WDM Encoder
+ 0bc7 Digital TV Tuner
+1165 Telson Electronics Co., Ltd
+1166 Bantam Interactive Technologies
+1167 Salient Systems Corp.
+1168 BizConn International Corp.
+116e Gigastorage Corp.
+116f Silicon 10 Technology Corp.
+1175 Shengyih Steel Mold Co., Ltd
+117d Santa Electronic, Inc.
+117e JNC, Inc.
+1182 Venture Corp., Ltd
+1183 Compaq Computer Corp. [hex] (Digital Dream ??)
+ 0001 DigitalDream l'espion XS
+ 19c7 ISDN TA
+ 4008 56k FaxModem
+ 504a PJB-100 Personal Jukebox
+1184 Kyocera Elco Corp.
+1188 Bloomberg L.P.
+1189 Acer Communications & Multimedia
+ 0893 EP-1427X-2 Ethernet Adapter
+118f You Yang Technology Co., Ltd
+1190 Tripace
+1191 Loyalty Founder Enterprise Co., Ltd
+1196 Yankee Robotics, LLC
+ 0010 Trifid Camera without code
+ 0011 Trifid Camera
+1197 Technoimagia Co., Ltd
+1198 StarShine Technology Corp.
+1199 Sierra Wireless, Inc.
+ 0019 AC595U
+ 0021 AC597E
+ 0110 Composite Device
+ 0112 CDMA 1xEVDO PC Card, AirCard 580
+ 0120 AC595U
+ 0218 MC5720 Wireless Modem
+ 6467 MP Series Network Adapter
+ 6468 MP Series Network Adapter
+ 6469 MP Series Network Adapter
+ 6802 MC8755 Device
+ 6803 MC8765 Device
+ 6804 MC8755 Device
+ 6805 MC8765 Device
+ 6812 MC8775 Device
+ 6820 AC875 Device
+ 6832 MC8780 Device
+ 6833 MC8781 Device
+ 683a MC8785 Device
+ 6850 AirCard 880 Device
+ 6851 AirCard 881 Device
+ 6852 AirCard 880E Device
+ 6853 AirCard 881E Device
+ 6854 AirCard 885 Device
+ 6870 MC8780 Device
+ 6871 MC8781 Device
+119a ZHAN QI Technology Co., Ltd
+119b ruwido austria GmbH
+ 0400 Infrared Keyboard V2.01
+11a0 Chipcon AS
+ eb11 CC2400EB 2.0 ZigBee Sniffer
+11a3 Technovas Co., Ltd
+ 8031 MP3 Player
+ 8032 MP3 Player
+11aa GlobalMedia Group, LLC
+ 1518 iREZ K2
+11ab Exito Electronics Co., Ltd
+11b0 ATECH FLASH TECHNOLOGY
+11db Topfield Co., Ltd.
+ 1000 PVR
+ 1100 PVR
+11e6 K.I. Technology Co. Ltd.
+11f5 Siemens AG (?)
+ 0001 SX1
+ 0003 Mobile phone USB cable
+ 0004 X75
+11f6 Prolific
+ 2001 Willcom WSIM
+11f7 Alcatel (?)
+ 02df TD10 Mobile phone USB cable
+1209 InterBiometrics
+ 1001 USB Hub
+ 1002 USB Relais
+ 1003 IBSecureCam-P
+ 1004 IBSecureCam-O
+ 1005 IBSecureCam-N
+120e Hudson Soft Co., Ltd
+121e Jungsoft Co., Ltd
+ 3403 Muzio JM250 Audio Player
+1223 SKYCABLE ENTERPRISE. CO., LTD.
+1230 Chipidea-Microelectronica, S.A.
+1235 Novation EMS
+ 0001 ReMOTE Audio/XStation
+ 0002 Speedio
+ 4661 ReMOTE25
+1241 Belkin
+ 1111 Mouse
+ 1122 Typhoon Stream Optical Mouse USB+PS/2
+ 1155 PS2/USB Browser Combo Mouse
+ 1166 MI-2150 Trust Mouse
+ 1177 F8E842-DL Mouse
+ 1503 Keyboard
+124a AirVast
+ 4017 PC-Chips 802.11b Adapter
+124b Nyko (Honey Bee)
+ 4d01 Airflo EX Joystick
+125f A-DATA Technology Co., Ltd.
+1264 Covidien Energy-based Devices
+1267 Logic3 / SpectraVideo plc
+ 0103 G-720 Keyboard
+ 0201 A4Tech SWOP-3 Mouse
+ a001 JP260 PC Game Pad
+ c002 Wireless Optical Mouse
+126c Aristocrat Technologies
+126d Bel Stewart
+126e Strobe Data, Inc.
+126f TwinMOS
+ 1325 Mobile Disk
+ 2168 Mobile Disk III
+ a006 G240
+1275 Xaxero Marine Software Engineering, Ltd.
+ 0002 WeatherFax 2000 Demodulator
+ 0080 SkyEye Weather Satellite Receiver
+1286 Marvell Semiconductor, Inc.
+ 8001 BLOB boot loader firmware
+1292 Innomedia
+ 0258 Creative Labs VoIP Blaster
+1293 Belkin Components [hex]
+ 0002 F5U002 Parallel Port [uss720]
+ 2101 104-key keyboard
+1294 RISO KAGAKU CORP.
+129b CyberTAN Technology
+ 1666 TG54USB
+12a7 Trendchip Technologies Corp.
+12ab Honey Bee Electronic International Ltd.
+12ba Licensed by Sony Computer Entertainment America
+ 0200 Harmonix Guitar for PlayStation(R)3
+ 0210 Harmonix Drum Kit for PlayStation(R)3
+12d1 Huawei Technologies Co., Ltd.
+ 1001 E620 USB Modem
+ 1003 E220 HSDPA Modem / E270 HSDPA/HSUPA Modem
+12d2 LINE TECH INDUSTRIAL CO., LTD.
+12d7 BETTER WIRE FACTORY CO., LTD.
+12ef Tapwave, Inc.
+ 0100 Tapwave Handheld [Tapwave Zodiac]
+12f5 Dynamic System Electronics Corp.
+12f7 Memorex Products, Inc.
+ 1a00 TD Classic 003B
+ 1e23 TravelDrive 2007 Flash Drive
+12fd AIN Comm. Technology Co., Ltd
+ 1001 AWU2000b 802.11b Stick
+1307 Transcend Information, Inc.
+ 0163 512MB USB Flash Drive
+ 1169 TS2GJF210 JetFlash 210 2GB
+1310 Roper
+ 0001 Class 1 Bluetooth Dongle
+1312 ICS Electronics
+131d Natural Point
+ 0155 TrackIR 3 Pro Head Tracker
+132b Konica Minolta
+ 0000 Dimage A2 Camera
+ 0001 Minolta DiMAGE A2 (ptp)
+ 0003 Dimage Xg Camera
+ 0006 Dimage Z2 Camera
+ 0007 Minolta DiMAGE Z2 (PictBridge mode)
+ 0008 Dimage X21 Camera
+ 000a Dimage Scan Dual IV
+ 000b Dimage Z10 Camera
+ 000d Dimage X50 Camera [storage?]
+ 000f Dimage X50 Camera [p2p?]
+ 0010 Dimage G600 Camera
+ 0012 Dimage Scan Elite5400 2
+ 0013 Dimage X31 Camera
+ 0015 Dimage G530 Camera
+ 0017 Dimage Z3 Camera
+ 0018 Minolta DiMAGE Z3 (PictBridge mode)
+ 0019 Dimage A200 Camera
+ 0021 Dimage Z5 Camera
+ 0022 Minolta DiMAGE Z5 (PictBridge mode)
+1342 Mobility
+ 0200 EasiDock 200 Hub
+ 0201 EasiDock 200 Keyboard and Mouse Port
+ 0202 EasiDock 200 Serial Port
+ 0203 EasiDock 200 Printer Port
+ 0204 Ethernet
+ 0304 EasiDock Ethernet
+1348 Katsuragawa Electric Co., Ltd.
+134e Digby's Bitpile, Inc. DBA D Bit
+136b STEC
+1370 Swissbit
+ 6828 Victorinox Flash Drive
+1371 Dick Smith Electronics
+ 9022 RT2573
+ 9032 C-Net CWD-854 rev F
+1376 Vimtron Electronics Co., Ltd.
+1385 Netgear, Inc
+ 4250 WG111T
+ 4251 WG111T (no firmware)
+ 5f00 WPN111 RangeMax(TM) Wireless USB 2.0 Adapter
+ 5f01 WPN111 (no firmware)
+138e Jungo LTD
+ 9000 Raisonance S.A. STM32 ARM evaluation board
+1390 TOMTOM B.V.
+1395 Sennheiser Communications
+ 3556 USB Headset
+1398 Q-tec
+ 2103 USB 2.0 Storage Device
+13ad Baltech
+ 9999 Card reader
+13b0 PerkinElmer Optoelectronics
+ 000a Alesis Photon X25 MIDI Controller
+13b1 Linksys
+ 000b WUSB11 v4.0 802.11b Adapter
+ 000d WUSB54G Wireless Adapter
+ 0011 WUSB54GP v4.0 802.11g Adapter
+ 0018 USB200M 10/100 Ethernet Adapter
+ 001a HU200TS Wireless Adapter
+ 0020 WUSB54GC 802.11g Adapter [ralink rt73]
+ 0023 WUSB54GR
+ 0024 WUSBF54G v1.1 802.11g Adapter w/ Wi-Fi Finder
+13b3 Nippon Dics Co., Ltd.
+13be Ricoh Printing Systems, Ltd.
+13ca JyeTai Precision Industrial Co., Ltd.
+13cf Wisair Ltd.
+13d1 A-Max Technology Macao Commercial Offshore Co. Ltd.
+13d2 Shark Multimedia
+ 0400 Pocket Ethernet [klsi]
+13d3 IMC Networks
+ 3201 VisionDTV USB-Ter/HAMA USB DVB-T device cold
+ 3202 VisionDTV USB-Ter/HAMA USB DVB-T device warm
+ 3203 DTV-DVB UDST7020BDA DVB-S Box(DVBS for MCE2005)
+ 3204 DTV-DVB UDST7020BDA DVB-S Box(DVBS for MCE2005)
+ 3205 DNTV Live! Tiny USB2 BDA (No Remote)
+ 3206 DNTV Live! Tiny USB2 BDA (No Remote)
+ 3207 DTV-DVB UDST7020BDA DVB-S Box(DVBS for MCE2005)
+ 3208 DTV-DVB UDST7020BDA DVB-S Box(DVBS for MCE2005)
+ 3209 DTV-DVB UDST7022BDA DVB-S Box(Without HID)
+ 3211 DTV-DVB Hybrid Analog/Capture / Pinnacle PCTV 310e
+ 3212 DTV-DVB UDTT704C - DVBT/NTSC/PAL Driver(PCM4)
+ 3213 DTV-DVB UDTT704D - DVBT/NTSC/PAL Driver (PCM4)
+ 3214 DTV-DVB UDTT704F -(MiniCard) DVBT/NTSC/PAL Driver(Without HID)
+ 3215 DTV-DVB UDAT7240 - ATSC/NTSC/PAL Driver(PCM4)
+ 3216 DTV-DVB UDTT 7047-USB 2.0 DVB-T Driver
+ 3217 Digital-TV Receiver.
+ 3219 DTV-DVB UDTT7049 - DVB-T Driver(Without HID)
+ 3220 DTV-DVB UDTT 7047M-USB 2.0 DVB-T Driver
+ 3223 DNTV Live! Tiny USB2 BDA (No Remote)
+ 3224 DNTV Live! Tiny USB2 BDA (No Remote)
+ 3226 DigitalNow TinyTwin DVB-T Receiver
+ 3236 DTV-DVB UDTT 7047A-USB 2.0 DVB-T Driver
+ 3237 DTV-DVB UDTT 704J - dual DVB-T Driver
+ 3239 DTV-DVB UDTT704D - DVBT/NTSC/PAL Driver(Without HID)
+ 3240 DTV-DVB UDXTTM6010 - A/D Driver(Without HID)
+ 3241 DTV-DVB UDXTTM6010 - A/D Driver(Without HID)
+ 3242 DTV-DVB UDAT7240LP - ATSC/NTSC/PAL Driver(Without HID)
+ 3243 DTV-DVB UDXTTM6010 - A/D Driver(Without HID)
+ 3244 DTV-DVB UDTT 7047Z-USB 2.0 DVB-T Driver
+ 3247 802.11 n/g/b Wireless LAN Adapter
+ 7020 DTV-DVB UDST7020BDA DVB-S Box(DVBS for MCE2005)
+ 7022 DTV-DVB UDST7022BDA DVB-S Box(Without HID)
+13dc ALEREON, INC.
+13dd i.Tech Dynamic Limited
+13e1 Kaibo Wire & Cable (Shenzhen) Co., Ltd.
+13e5 Rane
+ 0001 SL-1
+13e6 TechnoScope Co., Ltd.
+13fd Initio Corporation
+13fe Kingston Technology Company Inc.
+ 1a00 512MB/1GB Flash Drive
+ 1a23 512MB Flash Drive
+ 1d00 DataTraveler 2.0 1GB/4GB Flash Drive / Patriot Xporter 4GB Flash Drive
+ 1f00 DataTraveler 2.0 4GB Flash Drive
+1400 Axxion Group Corp.
+1402 Bowe Bell & Howell
+1403 Sitronix
+ 0001 Digital Photo Frame
+140e Telechips, Inc.
+1410 Novatel Wireless
+ 1110 Merlin S620
+ 1120 Merlin EX720
+ 1130 Merlin S720
+ 1400 Merlin U740
+ 2110 Ovation U720/MCD3000
+ 4100 U727
+1415 Nam Tai E&E Products Ltd. or OmniVision Technologies, Inc.
+ 0000 Sony SingStar USBMIC
+ 2000 Sony Playstation Eye
+1419 ABILITY ENTERPRISE CO., LTD.
+1429 Vega Technologies Industrial (Austria) Co.
+1430 RedOctane
+1431 Pertech Resources, Inc.
+1435 Wistron NeWeb
+ 0711 UR055G
+ 0826 AR5523
+ 0827 AR5523 (no firmware)
+ 0828 AR5523
+ 0829 AR5523 (no firmware)
+1436 Denali Software, Inc.
+143c Altek Corporation
+1453 Radio Shack
+ 4026 26-183 Serial Cable
+1456 Extending Wire & Cable Co., Ltd.
+1457 First International Computer, Inc.
+ 5117 OpenMoko Neo1973 kernel usbnet (g_ether, CDC Ethernet) mode
+ 5118 OpenMoko Neo1973 Debug board (V2+)
+ 5119 OpenMoko Neo1973 u-boot cdc_acm serial port
+ 5120 OpenMoko Neo1973 u-boot usbtty generic serial
+ 5121 OpenMoko Neo1973 kernel mass storage (g_storage) mode
+ 5122 OpenMoko Neo1973 kernel cdc_ether USB network
+ 5123 OpenMoko Neo1973 internal USB CSR4 module
+ 5124 OpenMoko Neo1973 Bluetooth Device ID service
+1461 Staccato Communications
+1462 Micro Star International
+ 5512 MegaStick-1 Flash Stick
+1472 Huawei-3Com
+ 0009 Aolynk WUB320g
+147a Formosa Industrial Computing, Inc.
+ e015 eHome Infrared Receiver
+ e016 eHome Infrared Receiver
+147f Hama GmbH & Co., KG
+1484 Elsa AG [hex]
+ 1746 Ecomo 19H99 Monitor
+ 7616 Elsa Hub
+1485 Silicom
+ 0001 U2E
+ 0002 Psion Gold Port Ethernet
+1487 DSP Group, Ltd.
+148e EVATRONIX SA
+148f Ralink Technology, Corp.
+ 1706 RT2500USB Wireless Adapter
+ 2570 802.11g WiFi
+ 2573 RT2501USB Wireless Adapter
+ 2671 RT2601USB Wireless Adapter
+ 9020 RT2500USB Wireless Adapter
+ 9021 RT2501USB Wireless Adapter
+1497 Panstrong Company Ltd.
+149a Imagination Technologies
+ 2107 DBX1 DSP core
+14aa AVerMedia (again) or C&E
+ 0001 Avermedia AverTV DVBT USB1.1 (cold)
+ 0002 Avermedia AverTV DVBT USB1.1 (warm)
+ 0201 AVermedia/Yakumo/Hama/Typhoon DVB-T USB2.0 (cold)
+ 0221 AVermedia DVBT Tuner Dongle
+ 0301 AVermedia/Yakumo/Hama/Typhoon DVB-T USB2.0 (warm)
+14ad CTK Corporation
+14ae Printronix Inc.
+14af ATP Electronics Inc.
+14b0 StarTech.com Ltd.
+14b2 Atheros Communications Inc
+ 3a93 USB WLAN Device
+ 3c02 C54RU WLAN
+ 3c22 C54RU
+14c0 Rockwell Automation, Inc.
+14c2 Gemlight Computer, Ltd
+ 0250 Storage Adapter V2
+ 0350 Storage Adapter V2
+14cd Super Top
+ 6600 USB 2.0 IDE DEVICE
+14d8 JAMER INDUSTRIES CO., LTD.
+14dd Raritan Computer, Inc.
+14e5 SAIN Information & Communications Co., Ltd.
+14ea Planex Communications
+ ab10 GW-US54GZ
+ ab11 GU-1000T
+ ab13 GW-US54Mini
+14ed Shure Inc.
+1500 Ellisys
+1501 Pine-Tum Enterprise Co., Ltd.
+1513 Hypercom
+1516 CompUSA
+ 8628 128M Pen Drive
+1518 Cheshire Engineering Corp.
+ 0001 HDReye High Dynamic Range Camera
+ 0002 HDReye (before firmware loads)
+1520 Bitwire Corp.
+1524 ENE Technology Inc
+ 6680 UTS 6680
+1527 Silicon Portals
+ 0200 YAP Phone (no firmware)
+ 0201 YAP Phone
+1529 UBIQUAM Co., Ltd.
+ 3100 CDMA 1xRTT USB Modem (U-100/105/200/300/520)
+152d JMicron Technology Corp. / JMicron USA Technology Corp.
+ 2338 JM20337 Hi-Speed USB to SATA & PATA Combo Bridge
+152e LG (HLDS)
+ e001 GSA-5120D DVD-RW
+1532 Razer USA, Ltd
+ 0001 RZ01-020300 Optical Mouse [Diamondback]
+ 0003 Krait Mouse
+ 0007 DeathAdder Mouse
+ 0102 Tarantula Keyboard
+1546 U-Blox AG
+154b PNY
+ 0010 USB 2.0 Flash Drive
+154d ConnectCounty Holdings Berhad
+154e D&M Holdings, Inc. (Denon/Marantz)
+ 3000 Marantz RC9001 Remote Control
+1554 Prolink Microsystems Corp.
+1557 OQO
+ 0002 model 01 WiFi interface
+ 0003 model 01 Bluetooth interface
+ 7720 model 01+ Ethernet
+ 8150 model 01 Ethernet interface
+1568 Sunf Pu Technology Co., Ltd
+156f Quantum Corporation
+1570 ALLTOP TECHNOLOGY CO., LTD.
+157b Ketron SRL
+157e TRENDnet
+ 3006 TEW-444UB EU
+ 3007 TEW-444UB EU (no firmware)
+ 300a TEW-429UB 802.11g Adapter with HotSpot Detector
+ 300b TEW-429UB
+ 300d TEW-429UB C1
+ 3204 ALL0298 v2
+ 3205 AR5523
+ 3206 AR5523 (no firmware)
+1582 Fiberline
+ 6003 WL-430U
+1587 SMA Technologie AG
+158d Oakley Inc.
+1598 Kunshan Guoji Electronics Co., Ltd.
+15a2 Freescale Semiconductor, Inc.
+15a8 Teams Power Limited
+15aa Gearway Electronics (Dong Guan) Co., Ltd.
+15ba Olimex Ltd.
+ 0003 OpenOCD JTAG
+ 0004 OpenOCD JTAG TINY
+15c2 SoundGraph Inc.
+ ffdc iMON PAD Remote Controller
+15c6 Laboratoires MXM
+ 1000 DigistimSP (cold)
+ 1001 DigistimSP (warm)
+ 1002 DigimapSP USB (cold)
+ 1003 DigimapSP USB (warm)
+15c9 D-Box Technologies
+15ca Textech International Ltd.
+ 00c3 Mini Optical Mouse
+15d5 Coulomb Electronics Ltd.
+15dc Hynix Semiconductor Inc.
+15e0 Seong Ji Industrial Co., Ltd.
+15e1 RSA
+ 2007 RSA SecurID (R) Authenticator
+15e8 SohoWare
+ 9100 NUB100 Ethernet [pegasus]
+ 9110 10/100 USB Ethernet
+15e9 Pacific Digital Corp.
+ 04ce MemoryFrame MF-570
+ 1968 MemoryFrame MF-570
+ 1969 Digital Frame
+15ec Belcarra Technologies Corp.
+15f4 HanfTek
+ 0001 HanfTek UMT-010 USB2.0 DVB-T (cold)
+ 0025 HanfTek UMT-010 USB2.0 DVB-T (warm)
+1604 Tascam
+ 8000 US-428 Audio/Midi Controller (without fw)
+ 8001 US-428 Audio/Midi Controller
+ 8004 US-224 Audio/Midi Controller (without fw)
+ 8005 US-224 Audio/Midi Controller
+ 8006 US-122 Audio/Midi Interface (without fw)
+ 8007 US-122 Audio/Midi Interface
+1606 Umax [hex]
+ 0002 Astra 1236U Scanner
+ 0010 Astra 1220U
+ 0030 Astra 2000U
+ 0050 Scanner
+ 0060 Astra 3400U
+ 0130 Astra 2100U
+ 0160 Astra 5400U
+ 0230 Astra 2200/2200SU
+ 0350 Astra 4800/4850 Scanner
+ 1030 Astra 4000U
+ 1220 Genesys Logic Scanner Controller NT5.0
+ 2010 AstraCam Digital Camera
+ 2020 AstraCam 1000
+ 2030 AstraCam 1800 Digital Camera
+1608 Inside Out Networks [hex]
+ 0001 EdgePort/4 Serial Port
+ 0002 Edgeport/8
+ 0003 Rapidport/4
+ 0004 Edgeport/4
+ 0005 Edgeport/2
+ 0006 Edgeport/4i
+ 0007 Edgeport/2i
+ 0008 Edgeport/8
+ 000c Edgeport/421
+ 000d Edgeport/21
+ 000e Edgeport/4
+ 000f Edgeport/8
+ 0010 Edgeport/2
+ 0011 Edgeport/4
+ 0012 Edgeport/416
+ 0014 Edgeport/8i
+ 0018 Edgeport/412
+ 0019 Edgeport/412
+ 001a Edgeport/2+2i
+ 0101 Edgeport/4
+ 0105 Edgeport/2
+ 0106 Edgeport/4i
+ 0107 Edgeport/2i
+ 010c Edgeport/421
+ 010d Edgeport/21
+ 0110 Edgeport/2
+ 0111 Edgeport/4
+ 0112 Edgeport/416
+ 0114 Edgeport/8i
+ 0201 Edgeport/4
+ 0203 Rapidport/4
+ 0204 Edgeport/4
+ 0205 Edgeport/2
+ 0206 Edgeport/4i
+ 0207 Edgeport/2i
+ 020c Edgeport/421
+ 020d Edgeport/21
+ 020e Edgeport/4
+ 020f Edgeport/8
+ 0210 Edgeport/2
+ 0211 Edgeport/4
+ 0212 Edgeport/416
+ 0214 Edgeport/8i
+ 0215 Edgeport/1
+ 0216 EPOS/44
+ 0217 Edgeport/42
+ 021a Edgeport/2+2i
+ 021b Edgeport/2c
+ 021c Edgeport/221c
+ 021d Edgeport/22c
+ 021e Edgeport/21c
+ 021f Edgeport/62
+ 0240 Edgeport/1
+ 0241 Edgeport/1i
+ 0242 Edgeport/4s
+ 0243 Edgeport/8s
+ 0244 Edgeport/8
+ 0245 Edgeport/22c
+ 0301 Watchport/P
+ 0302 Watchport/M
+ 0303 Watchport/W
+ 0304 Watchport/T
+ 0305 Watchport/H
+ 0306 Watchport/E
+ 0307 Watchport/L
+ 0308 Watchport/R
+ 0309 Watchport/A
+ 030a Watchport/D
+ 030b Watchport/D
+ 030c Power Management Port
+ 030e Power Management Port
+ 030f Watchport/G
+ 0310 Watchport/Tc
+ 0311 Watchport/Hc
+ 1403 MultiTech Systems MT4X56 Modem
+ 1a17 Agilent Technologies (E6473)
+1619 L & K Precision Technology Co., Ltd.
+1621 Wionics Research
+1628 Stonestreet One, Inc.
+162a Airgo Networks Inc.
+162f WiQuest Communications, Inc.
+1631 Good Way Technology
+ 6200 GWUSB2E
+ c019 RT2573
+1645 Entrega [hex]
+ 0001 1S Serial Port
+ 0002 2S Serial Port
+ 0003 1S25 Serial Port
+ 0004 4S Serial Port
+ 0005 E45 Ethernet [klsi]
+ 0006 Parallel Port
+ 0007 U1-SC25 SCSI
+ 0008 Ethernet
+ 0016 Bi-directional to Parallel Printer Converter
+ 0080 1 port to Serial Converter
+ 0081 1 port to Serial Converter
+ 0093 1S9 Serial Port
+ 8000 EZ-USB
+ 8001 1 port to Serial
+ 8002 2x Serial Port
+ 8003 1 port to Serial
+ 8004 2U4S serial/usb hub
+ 8005 Ethernet
+ 8080 1 port to Serial
+ 8081 1 port to Serial
+ 8093 PortGear Serial Port
+164a ChipX
+1657 Struck Innovative Systeme GmbH
+ 3150 SIS3150 USB2.0 to VME interface
+1660 Creatix Polymedia GmbH
+1668 Actiontec Electronics, Inc. [hex]
+ 0009 Gateway
+ 0333 Modem
+ 0358 InternetPhoneWizard
+ 0405 Gateway
+ 0408 Prism2.5 802.11b Adapter
+ 0413 Gateway
+ 0421 Prism2.5 802.11b Adapter
+ 0441 IBM Integrated Bluetooth II
+ 0500 BTM200B BlueTooth Adapter
+ 1050 802.11g Wireless Mini adapter
+ 1441 IBM Integrated Bluetooth II
+ 2441 BMDC-2 IBM Bluetooth III w.56k
+ 3441 IBM Integrated Bluetooth III
+ 6010 Gateway
+ 6097 802.11b Wireless Adapter
+ 6106 ROPEX FreeLan 802.11b
+ 7605 UAT1 Wireless Ethernet Adapter
+1669 PiKRON Ltd. [hex]
+ 1001 uLan2USB Converter - PS1 protocol
+1679 Total Phase
+ 2001 Beagle USB 12 Protocol Analyzer
+1682 Maxwise Production Enterprise Ltd.
+1684 Godspeed Computer Corp.
+1686 ZOOM Corporation
+ 0045 H4 Digital Recorder
+1687 Kingmax Digital Inc.
+168c Atheros Communications
+ 0001 AR5523
+ 0002 AR5523 (no firmware)
+1690 Askey Computer Corp. [hex]
+ 0101 Creative Modem Blaster DE5670
+ 0102 CDC Modem Board
+ 0103 Askey 1456 VQE-R3 Modem [conexant]
+ 0104 HCF V90 Data Fax RTAD Modem
+ 0107 HCF V.90 Data,Fax,RTAD Modem
+ 0109 Askey MagicXpress V.90 Pocket Modem [conexant]
+ 0203 Voyager ADSL Modem Loader
+ 0204 Voyager ADSL Modem
+ 0205 DSL Modem
+ 0206 GlobeSpan ADSL WAN Modem
+ 0208 DSL Modem
+ 0209 Voyager 100 ADSL Modem
+ 0211 Globespan Virata ADSL LAN Modem
+ 0212 DSL Modem
+ 0213 HM121d DSL Modem
+ 0214 HM121d DSL Modem
+ 0215 Voyager 105 ADSL Modem
+ 0701 WLAN
+ 0710 SMCWUSBT-G
+ 0711 SMCWUSBT-G (no firmware)
+ 0712 AR5523
+ 0713 AR5523 (no firmware)
+ 0715 Voyager 1055 Laptop Adapter
+ 0722 RT2573
+ 0726 Wi-Fi Wireless LAN Adapter
+ 0901 Voyager 205 ADSL Router
+1696 Hitachi Video and Information System, Inc.
+1697 VTec Test, Inc.
+16a5 Shenzhen Zhengerya Cable Co., Ltd.
+16ab Global Sun Technology
+ 7801 AR5523
+ 7802 AR5523 (no firmware)
+ 7811 AR5523
+ 7812 AR5523 (no firmware)
+16ac Dongguan ChingLung Wire & Cable Co., Ltd.
+16c0 VOTI
+ 03e8 free for internal lab use 1000
+ 03e9 free for internal lab use 1001
+ 03ea free for internal lab use 1002
+ 03eb free for internal lab use 1003
+ 03ec free for internal lab use 1004
+ 03ed free for internal lab use 1005
+ 03ee free for internal lab use 1006
+ 03ef free for internal lab use 1007
+ 03f0 free for internal lab use 1008
+ 03f1 free for internal lab use 1009
+ 076b OpenPCD 13.56MHz RFID Reader
+ 076c OpenPICC 13.56MHz RFID Simulator (native)
+ 08ac OpenBeacon USB stick
+16cc silex technology, Inc.
+16d3 Frontline Test Equipment, Inc.
+16d5 AnyDATA Corporation
+ 6501 CDMA 2000 1xRTT/EV-DO USB Modem
+16d8 CMOTECH Co., Ltd.
+ 5141 CMOTECH CDMA Technologies USB modem
+ 5543 CDMA 2000 1xRTT/1xEVDO USB modem
+ 6280 CMOTECH CDMA Technologies USB modem
+16df King Billion Electronics Co., Ltd.
+16f5 Futurelogic Inc.
+1706 BlueView Technologies, Inc.
+1707 ARTIMI
+170b Swissonic
+ 0011 MIDI-USB 1x1
+170d Avnera
+1733 Cellink Technology Co., Ltd
+ 0101 RF Wireless Optical Mouse OP-701
+1736 CANON IMAGING SYSTEM TECHNOLOGIES INC.
+1737 Linksys
+ 0039 USB1000
+1740 Senao
+ 2000 NUB-8301
+1743 General Atomics
+174c ASMedia Technology Inc.
+174f Syntek
+ 5a35 1.3MPixel Web Cam - Asus G1s
+ 6a31 Web Cam - Asus A8J, F3S, F5R, VX2S, V1S
+ 6a33 Web Cam - Asus F3SA, F9J, F9S
+ 6a51 2.0MPixel Web Cam - Asus Z96J, Z96S, S96S
+ 6a54 Web Cam
+ 6d51 2.0Mpixel Web Cam - Eurocom D900C
+ 8a12 0.3MPixel Web Cam - Packard Bell MX37-T-003
+ a311 1.3MPixel Web Cam - Asus A3A, A6J, A6K, A6M, A6R, A6T, A6V, A7T, A7sv, A7U
+ a312 1.3MPixel Web Cam
+ a821 Web Cam - Packard Bell BU45, PB Easynote MX66-208W
+ aa11 Web Cam
+1759 LucidPort Technology, Inc.
+1772 System Level Solutions, Inc.
+1781 Multiple Vendors
+ 083e MetaGeek Wi-Spy
+ 0938 Iguanaworks USB IR Transceiver
+1782 Spreadtrum Communications Inc.
+1784 TopSeed Technology Corp.
+1788 ShenZhen Litkconn Technology Co., Ltd.
+1796 Printrex, Inc.
+1797 JALCO CO., LTD.
+17a5 Advanced Connection Technology Inc.
+17a7 MICOMSOFT CO., LTD.
+17b3 Grey Innovation
+ 0004 Linux-USB Midi Gadget
+17c3 Singim International Corp.
+17cc Native Instruments
+ 0815 Audio Kontrol 1
+ 1940 RigKontrol3
+ 1969 RigKontrol2
+ 1978 Audio 8 DJ
+ 4711 Kore Controller
+ 4712 Kore Controller 2
+17cf Hip Hing Cable & Plug Mfy. Ltd.
+17d0 Sanford L.P.
+17d3 Korea Techtron Co., Ltd.
+17e9 Newnham Research
+ 0051 USB VGA Adaptor
+17eb Cornice, Inc.
+17ef Lenovo
+ 3815 ChipsBnk 2GB USB Stick
+17f5 K.K. Rocky
+17f6 Unicomp, Inc
+1822 Twinhan
+ 3201 VisionDTV USB-Ter/HAMA USB DVB-T device cold
+ 3202 VisionDTV USB-Ter/HAMA USB DVB-T device warm
+1831 Gwo Jinn Industries Co., Ltd.
+1832 Huizhou Shenghua Industrial Co., Ltd.
+1854 Memory Devices Ltd.
+185b Compro
+ d000 Compro Videomate DVB-U2000 - DVB-T USB cold
+ d001 Compro Videomate DVB-U2000 - DVB-T USB warm
+1861 Tech Technology Industrial Company
+1862 Teridian Semiconductor Corp.
+1871 Aveo Technology Corp.
+1894 Topseed
+ 5632 Atek Tote Remote
+ 5641 TSAM-004 Presentation Remote
+1897 Evertop Wire Cable Co.
+18b6 Mikkon Technology Limited
+18b7 Zotek Electronic Co., Ltd.
+18c5 AMIT
+ 0002 CG-WLUSB2GO
+18d5 Starline International Group Limited
+18d9 Kaba
+ 01xy LEGIC advant desktop reader
+18e3 Fitipower Integrated Technology Inc
+18e8 Qcom
+ 6196 RT2573
+ 6229 RT2573
+18ea Matrox Graphics, Inc.
+ 0002 DualHead2Go [Analog Edition]
+ 0004 TripleHead2Go [Digital Edition]
+18fd FineArch Inc.
+190d Motorola GSG
+1914 Alco Digital Devices Limited
+1915 Linksys
+ 2233 WUSB11 v2.8 802.11b Adapter
+ 2234 WUSB54G 802.11g Adapter
+192f Avago Technologies, Pte.
+1930 Shenzhen Xianhe Technology Co., Ltd.
+1931 Ningbo Broad Telecommunication Co., Ltd.
+1949 Lab126
+1951 Hyperstone AG
+1953 Ironkey Inc.
+1954 Radiient Technologies
+195d Itron Technology iONE
+ 7002 Libra-Q11 IR remote
+ 7006 Libra-Q26 / 1.0 Remote
+ 7777 Scorpius wireless keyboard
+1967 CASIO HITACHI Mobile Communications Co., Ltd.
+196b Wispro Technology Inc.
+1970 Dane-Elec Corp. USA
+1975 Dongguan Guneetal Wire & Cable Co., Ltd.
+1976 Chipsbrand Microelectronics (HK) Co., Ltd.
+1977 T-Logic
+ 0111 TL203 MP3 Player and Voice Recorder
+1989 Nuconn Technology Corp.
+198f Beceem Communications Inc.
+1990 Acron Precision Industrial Co., Ltd.
+1995 Trillium Technology Pty. Ltd.
+ 3202 REC-ADPT-USB (recorder)
+ 3203 REC-A-ADPT-USB (recorder)
+199e The Imaging Source Europe GmbH
+199f Benica Corporation
+19a8 Biforst Technology Inc.
+19af S Life
+ 6611 Celestia VoIP Phone
+19b5 B & W Group
+19b6 Infotech Logistic, LLC
+19ca Mindtribe
+ 0001 Sandio 3D HID Mouse
+19cf Parrot SA
+19e1 WeiDuan Electronic Accessory (S.Z.) Co., Ltd.
+19e8 Industrial Technology Research Institute
+19ef Pak Heng Technology (Shenzhen) Co., Ltd.
+19ff Best Buy
+ 0201 Rocketfish Wireless 2.4G Laser Mouse
+1a08 Bellwood International, Inc.
+1a0a USB-IF non-workshop
+ badd USB OTG Compliance test device
+1a12 KES Co., Ltd.
+1a25 Amphenol East Asia Ltd.
+1a2a Seagate Branded Solutions
+1a36 Biwin Technology Ltd.
+1a40 TERMINUS TECHNOLOGY INC.
+1a41 Action Electronics Co., Ltd.
+1a4a Silicon Image
+1a4b SafeBoot International B.V.
+1a61 Abbott Diabetes Care
+1a6a Spansion Inc.
+1a6d SamYoung Electronics Co., Ltd
+1a6e Global Unichip Corp.
+1a6f Sagem Orga GmbH
+1a79 Bayer Health Care LLC
+1a7b Lumberg Connect GmbH & Co. KG
+1a89 Dynalith Systems Co., Ltd.
+1a8b SGS Taiwan Ltd.
+1a98 Leica Camera AG
+1aa4 Data Drive Thru, Inc.
+1aa5 UBeacon Technologies, Inc.
+1aa6 eFortune Technology Corp.
+1acb Salcomp Plc
+1ad1 Desay Wire Co., Ltd.
+1ae4 ic-design Reinhard Gottinger GmbH
+1aed High Top Precision Electronic Co., Ltd.
+1aef Conntech Electronic (Suzhou) Corporation
+1b04 Meilhaus Electronic GmBH
+ 0630 ME-630
+ 0940 ME-94
+ 0950 ME-95
+ 0960 ME-96
+ 1000 ME-1000
+ 100a ME-1000
+ 100b ME-1000
+ 1400 ME-1400
+ 140a ME-1400A
+ 140b ME-1400B
+ 140c ME-1400C
+ 140d ME-1400D
+ 140e ME-1400E
+ 14ea ME-1400EA
+ 14eb ME-1400EB
+ 1604 ME-1600/4U
+ 1608 ME-1600/8U
+ 160c ME-1600/12U
+ 160f ME-1600/16U
+ 168f ME-1600/16U8I
+ 4610 ME-4610
+ 4650 ME-4650
+ 4660 ME-4660
+ 4661 ME-4660I
+ 4662 ME-4660
+ 4663 ME-4660I
+ 4670 ME-4670
+ 4671 ME-4670I
+ 4672 ME-4670S
+ 4673 ME-4670IS
+ 4680 ME-4680
+ 4681 ME-4680I
+ 4682 ME-4680S
+ 4683 ME-4680IS
+ 6004 ME-6000/4
+ 6008 ME-6000/8
+ 600f ME-6000/16
+ 6014 ME-6000I/4
+ 6018 ME-6000I/8
+ 601f ME-6000I/16
+ 6034 ME-6000ISLE/4
+ 6038 ME-6000ISLE/8
+ 603f ME-6000ISLE/16
+ 6044 ME-6000/4/DIO
+ 6048 ME-6000/8/DIO
+ 604f ME-6000/16/DIO
+ 6054 ME-6000I/4/DIO
+ 6058 ME-6000I/8/DIO
+ 605f ME-6000I/16/DIO
+ 6074 ME-6000ISLE/4/DIO
+ 6078 ME-6000ISLE/8/DIO
+ 607f ME-6000ISLE/16/DIO
+ 6104 ME-6100/4
+ 6108 ME-6100/8
+ 610f ME-6100/16
+ 6114 ME-6100I/4
+ 6118 ME-6100I/8
+ 611f ME-6100I/16
+ 6134 ME-6100ISLE/4
+ 6138 ME-6100ISLE/8
+ 613f ME-6100ISLE/16
+ 6144 ME-6100/4/DIO
+ 6148 ME-6100/8/DIO
+ 614f ME-6100/16/DIO
+ 6154 ME-6100I/4/DIO
+ 6158 ME-6100I/8/DIO
+ 615f ME-6100I/16/DIO
+ 6174 ME-6100ISLE/4/DIO
+ 6178 ME-6100ISLE/8/DIO
+ 617f ME-6100ISLE/16/DIO
+ 6259 ME-6200I/9/DIO
+ 6359 ME-6300I/9/DIO
+ 810a ME-8100A
+ 810b ME-8100B
+ 820a ME-8200A
+ 820b ME-8200B
+1b20 MStar Semiconductor, Inc.
+1b22 WiLinx Corp.
+1b26 Cellex Power Products, Inc.
+1b27 Current Electronics Inc.
+1b28 NAVIsis Inc.
+1b32 Ugobe Life Forms, Inc.
+1b36 ViXS Systems, Inc.
+1b3f Generalplus Technology Inc.
+1b47 Energizer Holdings, Inc.
+ 0001 CHUSB Duo Charger (NiMH AA/AAA USB smart charger)
+1b48 Plastron Precision Co., Ltd.
+1b59 K.S. Terminals Inc.
+1b5a Chao Zhou Kai Yuan Electric Co., Ltd.
+1b65 The Hong Kong Standards and Testing Centre Ltd.
+1b72 ATERGI TECHNOLOGY CO., LTD.
+1b76 Legend Silicon Corp.
+1b86 Dongguan Guanshang Electronics Co., Ltd.
+1b88 ShenMing Electron (Dong Guan) Co., Ltd.
+1b8c Altium Limited
+1b8d e-MOVE Technology Co., Ltd.
+1b8e Amlogic, Inc.
+1b8f MA LABS, Inc.
+1b98 YMax Communications Corp.
+1b99 Shenzhen Yuanchuan Electronic
+1ba1 JINQ CHERN ENTERPRISE CO., LTD.
+1ba2 Lite Metals & Plastic (Shenzhen) Co., Ltd.
+1ba4 Ember Corporation
+ 0001 InSight USB Link
+1ba8 China Telecommunication Technology Labs
+1bad Harmonix Music
+ 0002 Harmonix Guitar for Xbox 360
+ 0003 Harmonix Drum Kit for Xbox 360
+1bbb T & A Mobile Phones
+1bc4 Ford Motor Co.
+1bc5 AVIXE Technology (China) Ltd.
+1bce Contac Cable Industrial Limited
+1bcf Sunplus Innovation Technology Inc.
+1bd0 Hangzhou Riyue Electronic Co., Ltd.
+1bde P-TWO INDUSTRIES, INC.
+1bef Shenzhen Tongyuan Network-Communication Cables Co., Ltd
+1bf0 RealVision Inc.
+1bf5 Extranet Systems Inc.
+1bf6 Orient Semiconductor Electronics, Ltd.
+1bfd TouchPack
+ 1688 Resistive Touch Screen
+1c02 Kreton Corporation
+1c04 QNAP System Inc.
+1c0d Relm Wireless
+1c10 Lanterra Industrial Co., Ltd.
+1c13 ALECTRONIC LIMITED
+1c1a Datel Electronics Ltd.
+1c1b Volkswagen of America, Inc.
+1c1f Goldvish S.A.
+1c20 Fuji Electric Device Technology Co., Ltd.
+1c21 ADDMM LLC
+1c22 ZHONGSHAN CHIANG YU ELECTRIC CO., LTD.
+1c26 Shanghai Haiying Electronics Co., Ltd.
+1c27 HuiYang D & S Cable Co., Ltd.
+1c31 LS Cable Ltd.
+1c37 Authorizer Technologies, Inc.
+1c3d NONIN MEDICAL INC.
+1c3e Wep Peripherals
+1c49 Cherng Weei Technology Corp.
+1c6b Philips & Lite-ON Digital Solutions Corporation
+1c6c Skydigital Inc.
+1c77 Kaetat Industrial Co., Ltd.
+1c78 Datascope Corp.
+1c79 Unigen Corporation
+1c7a LighTuning Technology Inc.
+1c7b LUXSHARE PRECISION INDUSTRY (SHENZHEN) CO., LTD.
+1c87 2N TELEKOMUNIKACE a.s.
+1c88 Somagic, Inc.
+1c89 HONGKONG WEIDIDA ELECTRON LIMITED
+1c8e ASTRON INTERNATIONAL CORP.
+1c98 ALPINE ELECTRONICS, INC.
+1ca0 ACCARIO Inc.
+1cb3 Aces Electronic Co., Ltd.
+1cb4 OPEX CORPORATION
+1cbe Luminary Micro Inc.
+1cbf FORTAT SKYMARK INDUSTRIAL COMPANY
+1cc0 PlantSense
+1cca NextWave Broadband Inc.
+1ccd Bodatong Technology (Shenzhen) Co., Ltd.
+1cd4 adp corporation
+1cd5 Firecomms Ltd.
+1cd6 Antonio Precise Products Manufactory Ltd.
+1cde Telecommunications Technology Association (TTA)
+1cdf WonTen Technology Co., Ltd.
+1ce0 EDIMAX TECHNOLOGY CO., LTD.
+1ce1 Amphenol KAE
+1cfc ANDES TECHNOLOGY CORPORATION
+1cfd Flextronics Digital Design Japan, LTD.
+1d08 NINGBO HENTEK DRAGON ELECTRONICS CO., LTD.
+1d09 TechFaith Wireless Technology Limited
+1d0a Johnson Controls, Inc. The Automotive Business Unit
+1d0b HAN HUA CABLE & WIRE TECHNOLOGY (J.X.) CO., LTD.
+1d14 ALPHA-SAT TECHNOLOGY LIMITED
+1d1f Diostech Co., Ltd.
+1d20 SAMTACK INC.
+1d50 OpenMoko, Inc.
+1d5b Smartronix, Inc.
+1d6b Linux Foundation
+ 0001 1.1 root hub
+ 0002 2.0 root hub
+ 0003 3.0 root hub
+1ebb NuCORE Technology, Inc.
+2001 D-Link Corp. [hex]
+ 0001 DWL-120 WIRELESS ADAPTER
+ 0201 DHN-120 10Mb Home Phoneline Adapter
+ 1a00 10/100 Ethernet
+ 200c 10/100 Ethernet
+ 3200 DWL-120 802.11b (Atmel RFMD503A) [usbvnetr]
+ 3500 Elitegroup Computer Systems WLAN card WL-162
+ 3700 DWL-122 802.11b
+ 3701 DWL-G120 Spinnaker 802.11b
+ 3702 DWL-120 rev F
+ 3703 DWL-122 802.11b
+ 3704 DWL-G122 802.11g rev. A2
+ 3705 AirPlus G DWL-G120 Wireless Adapter(rev.C)
+ 3761 IEEE 802.11g USB2.0 Wireless Network Adapter-PN
+ 3a00 DWL-AG132
+ 3a01 DWL-AG132 (no firmware)
+ 3a02 DWL-G132
+ 3a03 DWL-G132 (no firmware)
+ 3a04 DWL-AG122
+ 3a05 DWL-AG122 (no firmware)
+ 3a80 AirPlus Xtreme G DWL-G132 Wireless Adapter
+ 3a81 predator Bootloader Download
+ 3a82 AirPremier AG DWL-AG132 Wireless Adapter
+ 3a83 predator Bootloader Download
+ 3b00 AirPlus DWL-120+ Wireless Adapter
+ 3b01 WLAN Boot Device
+ 3c00 DWL-G122 802.11g rev. B1 [ralink]
+ 3c01 AirPlus AG DWL-AG122 Wireless Adapter
+ 3c02 AirPlus G DWL-G122 Wireless Adapter
+ 3c05 DUB-E100 Fast Ethernet [asix]
+ 4000 DSB-650C Ethernet [klsi]
+ 4001 DSB-650TX Ethernet [pegasus]
+ 4002 DSB-650TX Ethernet [pegasus]
+ 4003 DSB-650TX-PNA Ethernet [pegasus]
+ 400b 10/100 Ethernet
+ 4102 10/100 Ethernet
+ 5100 DSL-200 ADSL ATM Modem
+ 5102 DSL-200 ADSL Loader
+ 5b00 Remote NDIS Network Device
+ 9414 Cable Modem
+ 9b00 Broadband Cable Modem Remote NDIS Device
+ abc1 DSB-650 Ethernet [pegasus]
+ f013 DLink 7 port USB2.0 Hub
+ f10d Accent Communications Modem
+ f110 DUB-AV300 A/V Capture
+ f111 DBT-122 Bluetooth adapter
+ f112 DUB-T210 Audio Device
+ f116 Formosa 2
+ f117 Formosa 3
+ f118 Formosa 4
+2019 PLANEX
+ 3220 GW-US11S WLAN
+ 5303 GW-US54GXS
+ ab01 GW-US54HP
+ ab50 GW-US54Mini2
+ c002 GW-US54SG
+ c007 GW-US54GZL
+ ed02 GW-USMM
+2040 Hauppauge
+ 6502 WinTV HVR-900
+ 6503 WinTV HVR-930
+ 7050 Nova-T Stick
+ 9300 WinTV NOVA-T USB2 (cold)
+ 9301 WinTV NOVA-T USB2 (warm)
+2101 ActionStar
+ 0201 SIIG 4-to-2 Printer Switch
+2162 Creative (?)
+ 2031 Network Blaster Wireless Adapter
+ 500c DE5771 Modem Blaster
+ 8001 Broadxent BritePort DSL Bridge 8010U
+2222 MacAlly
+ 0004 iWebKey Keyboard
+ 4050 AirStick joystick
+2233 RadioShack Corporation
+ 6323 USB Electronic Scale
+22b8 Motorola PCS
+ 0001 Wally 2.2 chipset
+ 0002 Wally 2.4 chipset
+ 0005 V.60c/V.60i GSM Phone
+ 0850 Bluetooth Device
+ 1001 Patriot 1.0 (GSM) chipset
+ 1002 Patriot 2.0 chipset
+ 1005 T280e GSM/GPRS Phone
+ 1101 Patriot 1.0 (TDMA) chipset
+ 1801 Rainbow chipset flash
+ 2035 Bluetooth Device
+ 2805 GSM Modem
+ 2821 T720 GSM Phone
+ 2822 V.120e GSM Phone
+ 2823 Flash Interface
+ 2a01 MSM6050 chipset
+ 2a02 CDMA modem
+ 2a03 MSM6050 chipset flash
+ 2a21 V710 GSM Phone (P2K)
+ 2a22 V710 GSM Phone (AT)
+ 2a23 MSM6100 chipset flash
+ 2a41 MSM6300 chipset
+ 2a42 Usb Modem
+ 2a43 MSM6300 chipset flash
+ 2a61 E815 GSM Phone (P2K)
+ 2a62 E815 GSM Phone (AT)
+ 2a63 MSM6500 chipset flash
+ 2a81 MSM6025 chipset
+ 2a83 MSM6025 chipset flash
+ 2ac1 MSM6100 chipset
+ 2ac3 MSM6100 chipset flash
+ 3001 A835/E1000 GSM Phone (P2K)
+ 3002 A835/E1000 GSM Phone (AT)
+ 3801 C350L/C450 (P2K)
+ 3802 C330/C350L/C450/EZX GSM Phone (AT)
+ 3803 Neptune LT chipset flash
+ 4001 OMAP 1.0 chipset
+ 4002 A920/A925 UMTS Phone
+ 4003 OMAP 1.0 chipset flash
+ 4008 OMAP 1.0 chipset RDL
+ 4204 MPx200 Smartphone
+ 4214 MPc GSM
+ 4224 MPx220 Smartphone
+ 4234 MPc CDMA
+ 4244 MPx100 Smartphone
+ 4801 Neptune LTS chipset
+ 4803 Neptune LTS chipset flash
+ 4810 Triplet GSM Phone (storage)
+ 4901 Triplet GSM Phone (P2K)
+ 4902 Triplet GSM Phone (AT)
+ 4903 Neptune LTE chipset flash
+ 4a01 Neptune LTX chipset
+ 4a03 Neptune LTX chipset flash
+ 4a32 L6-imode Phone
+ 5801 Neptune ULS chipset
+ 5803 Neptune ULS chipset flash
+ 5901 Neptune VLT chipset
+ 5903 Neptune VLT chipset flash
+ 6001 Dalhart EZX
+ 6003 Dalhart flash
+ 6004 EZX GSM Phone (CDC Net)
+ 6008 Dalhart RDL
+ 6009 EZX GSM Phone (P2K)
+ 600a Dalhart EZX config 17
+ 600b Dalhart EZX config 18
+ 600c EZX GSM Phone (USBLAN)
+ 6021 JUIX chipset
+ 6023 JUIX chipset flash
+ 6026 Flash RAM Downloader/miniOS
+ 6027 USBLAN
+ 604c EZX GSM Phone (Storage)
+ 6101 Talon integrated chipset
+ 6401 Argon chipset
+ 6403 Argon chipset flash
+ 6415 ROKR Z6 (MTP mode)
+ 6604 Washington CDMA Phone
+ 6631 CDC Modem
+22b9 eTurboTouch Technology, Inc.
+22ba Technology Innovation Holdings, Ltd
+2304 Pinnacle Systems, Inc. [hex]
+ 0109 Studio PCTV USB (SECAM)
+ 0110 Studio PCTV USB (PAL)
+ 0111 Miro PCTV USB
+ 0112 Studio PCTV USB (NTSC) with FM radio
+ 0201 Systems MovieBox Device
+ 0204 MovieBox USB_B
+ 0205 DVC 150B
+ 0206 Systems MovieBox Deluxe Device
+ 0207 Dazzle DVC90 Video Device
+ 0208 Studio PCTV USB2
+ 020e PCTV 200e
+ 020f PCTV 400e BDA Device
+ 0210 Studio PCTV USB (PAL) with FM radio
+ 0212 Studio PCTV USB (NTSC)
+ 0213 500-USB Device
+ 0214 Studio PCTV USB (PAL) with FM radio
+ 0216 PCTV 60e
+ 0219 PCTV 260e
+ 021a Dazzle DVC100 Audio Device
+ 021b Dazzle DVC130/DVC170
+ 021d Dazzle DVC130
+ 021e Dazzle DVC170
+ 021f PCTV Sat HDTV Pro BDA Device
+ 0222 PCTV Sat Pro BDA Device
+ 0223 DazzleTV Sat BDA Device
+ 0226 PCTV 330e
+ 0227 PCTV for Mac, HD Stick
+ 0228 PCTV DVB-T Flash Stick
+ 022a PCTV 160e
+ 022b PCTV 71e
+ 0232 PCTV 170e
+ 0300 Studio Linx Video input cable (NTSC)
+ 0301 Studio Linx Video input cable (PAL)
+ 0302 Dazzle DVC120
+ 0419 PCTV Bungee USB (PAL) with FM radio
+ 061d PCTV Deluxe (NTSC) Device
+ 061e PCTV Deluxe (PAL) Device
+2318 Shining Technologies, Inc. [hex]
+ 0011 CitiDISK Jr. IDE Enclosure
+2375 Digit@lway, Inc.
+ 0001 Digital Audio Player
+2406 SANHO Digital Electronics Co., Ltd.
+ 6688 PD7X Portable Storage
+2478 Tripp-Lite
+ 2008 U209-000-R Serial Port
+2632 TwinMOS
+ 3209 7-in-1 Card Reader
+2650 Electronics For Imaging, Inc. [hex]
+2730 Citizen
+ 200f CT-S310 Label printer
+2735 DigitalWay
+ 0003 MPIO 1.5GB Hard Disc Drive
+2770 NHJ, Ltd
+ 0a01 ScanJet 4600 series
+ 905c Che-Ez Snap SNAP-U/Digigr8/Soundstar TDC-35
+ 9060 A130
+ 9120 Che-ez! Snap / iClick Tiny VGA Digital Camera
+ 9130 TCG 501
+ 913c Argus DC-1730
+ 9150 Mini Cam
+ 9153 iClick 5X
+ 915d Cyberpix S-210S / Little Tikes My Real Digital Camera
+ 930b CCD Webcam(PC370R)
+ 930c CCD Webcam(PC370R)
+2899 Toptronic Industrial Co., Ltd
+2c02 Planex Communications
+ 14ea GW-US11H WLAN
+2fb2 Fujitsu, Ltd
+3125 Eagletron
+ 0001 TrackerPod Camera Stand
+3176 Whanam Electronics Co., Ltd
+3275 VidzMedia Pte Ltd
+ 4fb1 MonsterTV P2H
+3334 AEI
+ 1701 Fast Ethernet
+3340 Yakumo
+ 043a Mio A701 DigiWalker PPCPhone
+ 0e3a Pocket PC 300 GPS SL / Typhoon MyGuide 3500
+ a0a3 deltaX 5 BT (D) PDA
+3504 Micro Star
+ f110 Security Key
+3538 Power Quotient International Co., Ltd
+ 0001 Travel Flash
+ 0015 Mass Storge Device
+ 0022 Hi-Speed Mass Storage Device
+ 0042 Cool Drive U339 Flash Disk
+3579 DIVA
+ 6901 Media Reader
+3636 InVibro
+3838 WEM
+ 0001 5-in-1 Card Reader
+3923 National Instruments Corp.
+ 12c0 DAQPad-6020E
+ 12d0 DAQPad-6507
+ 12e0 NI 4350
+ 12f0 NI 5102
+ 1750 DAQPad-6508
+ 17b0 USB-ISA-Bridge
+ 1820 DAQPad-6020E (68 pin I/O)
+ 1830 DAQPad-6020E (BNC)
+ 1f00 DAQPad-6024E
+ 1f10 DAQPad-6024E
+ 1f20 DAQPad-6025E
+ 1f30 DAQPad-6025E
+ 1f40 DAQPad-6036E
+ 1f50 DAQPad-6036E
+ 2f80 DAQPad-6052E
+ 2f90 DAQPad-6052E
+ 703c USB-485 RS485 Cable
+ 7254 NI MIO (data acquisition card) firmware updater
+ 729e USB-6251 (OEM) data acquisition card
+40bb I-O Data
+ 0a09 USB2.0-SCSI Bridge USB2-SC
+4101 i-rocks
+ 1301 IR-2510 usb phone
+4102 iRiver, Ltd.
+ 1001 iFP-100 series mp3 player
+ 1003 iFP-300 series mp3 player
+ 1005 iFP-500 series mp3 player
+ 1007 iFP-700 series mp3/ogg vorbis player
+ 1008 iFP-800 series mp3/ogg vorbis player
+ 100a iFP-1000 series mp3/ogg vorbis player
+ 1014 T20 series mp3/ogg vorbis player (ums firmware)
+ 1101 iFP-100 series mp3 player (ums firmware)
+ 1103 iFP-300 series mp3 player (ums firmware)
+ 1105 iFP-500 series mp3 player (ums firmware)
+ 1113 T10 (alternate)
+ 1117 T10
+ 1119 T30 series mp3/ogg/wma player
+ 2002 H10 6GB
+ 2101 H10 20GB (mtp)
+ 2102 H10 5GB (mtp)
+ 2105 H10 5/6GB (mtp)
+413c Dell Computer Corp.
+ 0058 Port Replicator
+ 1001 Keyboard Hub
+ 1002 Keyboard Hub
+ 2001 Keyboard HID Support
+ 2002 SK-8125 Keyboard
+ 2003 Keyboard
+ 2005 RT7D50 Keyboard
+ 2100 SK-3106 Keyboard
+ 2101 SmartCard Reader Keyboard
+ 2500 DRAC4 Remote Access Card
+ 3010 Optical Wheel Mouse
+ 3200 Mouse
+ 4001 Axim X5
+ 4002 Axim X3
+ 4003 Axim X30
+ 4004 Axim Sync
+ 4005 Axim Sync
+ 4006 Axim Sync
+ 4007 Axim Sync
+ 4008 Axim Sync
+ 4009 Axim Sync
+ 4011 Axim X51v
+ 5103 AIO Printer A940
+ 5105 AIO Printer A920
+ 5107 AIO Printer A960
+ 5109 Photo AIO Printer 922
+ 5110 Photo AIO Printer 962
+ 5111 Photo AIO Printer 942
+ 5112 Photo AIO Printer 924
+ 5113 Photo AIO Printer 944
+ 5114 Photo AIO Printer 964
+ 5115 Photo AIO Printer 926
+ 5116 AIO Printer 946
+ 5117 Photo AIO Printer 966
+ 5118 AIO 810
+ 5124 Laser MFP 1815
+ 5128 Photo AIO 928
+ 5200 Laser Printer
+ 5202 Printing Support
+ 5203 Printing Support
+ 5210 Printing Support
+ 5211 Printing Support
+ 5220 Laser MFP 1600n
+ 5225 Printing Support
+ 5226 Printing Support
+ 5300 Laser Printer
+ 5400 Laser Printer
+ 5401 Laser Printer
+ 5601 Laser Printer 3100cn
+ 5602 Laser Printer 3000cn
+ 5631 Laser Printer 5100cn
+ 5905 Printing Support
+ 8000 BC02 Bluetooth USB Adapter
+ 8010 TrueMobile Bluetooth Module in
+ 8100 TrueMobile 1180 802.11b Adapter
+ 8102 TrueMobile 1300 USB2.0 WLAN Card
+ 8103 Wireless 350 Bluetooth
+ 8104 Wireless 1450 Dual-band (802.11a/b/g) USB2.0 Adapter
+ 8105 U2 in HID - Driver
+ 8106 Wireless 350 Bluetooth Internal Card in
+ 8110 Wireless 3xx Bluetooth Internal Card
+ 8111 Wireless 3xx Bluetooth Internal Card in
+ 8114 Wireless 5700 Mobile Broadband (CDMA EV-DO) Minicard Modem
+ 8115 Wireless 5500 Mobile Broadband (3G HSDPA) Minicard Modem
+ 8116 Wireless 5505 Mobile Broadband (3G HSDPA) Minicard Modem
+ 8117 Wireless 5700 Mobile Broadband (CDMA EV-DO) Expresscard Modem
+ 8118 Wireless 5510 Mobile Broadband (3G HSDPA) Expresscard Status Port
+ 8120 Bluetooth adapter
+ 8121 Eastfold in HID
+ 8122 Eastfold in DFU
+ 8123 eHome Infrared Receiver
+ 8124 eHome Infrared Receiver
+ 8126 Wireless 355 Bluetooth
+ 8127 Wireless 355 Module with Bluetooth 2.0 + EDR Technology.
+ 8128 Wireless 5700-Sprint Mobile Broadband (CDMA EV-DO) Mini-Card Status Port
+ 8129 Wireless 5700-Telus Mobile Broadband (CDMA EV-DO) Mini-Card Status Port
+ 8131 Wireless 360 Bluetooth 2.0 + EDR module.
+ 8133 Wireless 5720 VZW Mobile Broadband (EVDO Rev-A) Minicard GPS Port
+ 8134 Wireless 5720 Sprint Mobile Broadband (EVDO Rev-A) Minicard Status Port
+ 8135 Wireless 5720 TELUS Mobile Broadband (EVDO Rev-A) Minicard Diagnostics Port
+ 8136 Wireless 5520 Cingular Mobile Broadband (3G HSDPA) Minicard Diagnostics Port
+ 8137 Wireless 5520 Voda L Mobile Broadband (3G HSDPA) Minicard Status Port
+ 8138 Wireless 5520 Voda I Mobile Broadband (3G HSDPA) Minicard EAP-SIM Port
+ 8140 Wireless 360 Bluetooth
+ 8142 Mobile 360 in DFU
+ 8501 Bluetooth Adapter
+ a001 Hub
+ a005 Internal 2.0 Hub
+ a700 Hub (in 1905FP LCD Monitor)
+4146 USBest Technology
+ 9281 Iomega Micro Mini 128MB Flash Drive
+ ba01 Intuix Flash Drive
+4242 USB Design by Example
+ 4201 Buttons and Lights HID device
+ 4220 Echo 1 Camera
+4348 WinChipHead
+ 5523 USB->RS 232 adapter with Prolifec PL 2303 chipset
+ 5537 13.56Mhz RFID Card Reader and Writer
+ 5584 CH34x printer adapter cable
+4572 Shuttle, Inc.
+ 4572 Shuttle PN31 Remote
+4586 Panram
+ 1026 Crystal Bar Flash Drive
+4670 EMS Production
+ 9394 Game Cube USB Memory Adaptor 64M
+4752 Miditech
+ 0011 Midistart-2
+4766 Aceeca
+ 0001 MEZ1000 RDA
+4855 Memorex
+ 7288 Ultra Traveldrive 160G 2.5" HDD
+5032 Grandtec
+ 0bb8 Grandtec USB1.1 DVB-T (cold)
+ 0bb9 Grandtec USB1.1 DVB-T (warm)
+ 0fa0 Grandtec USB1.1 DVB-T (cold)
+ 0fa1 Grandtec USB1.1 DVB-T (warm)
+5041 Linksys (?)
+ 2234 WUSB54G 802.11g Adapter
+5173 Sweex
+ 1809 ZD1211
+5345 Owon
+ 1234 PDS6062T Oscilloscope
+544d Transmeta Corp.
+5543 UC-Logic Technology Corp.
+ 0002 SuperPen WP3325U Tablet
+ 0003 Genius MousePen 4x3 Tablet/Aquila L1 Tablet
+ 0004 Genius MousePen 5x4 Tablet
+ 0005 Genius MousePen 8x6 Tablet
+ 0041 Genius PenSketch 6x8 Tablet
+ 0042 Genius PenSketch 12x9 Tablet
+55aa OnSpec Electronic, Inc.
+ 0015 Hard Drive
+ 0102 SuperDisk
+ 0103 IDE Hard Drive
+ 0201 DDI to Reader-19
+ 1234 ATAPI Bridge
+ a103 Sandisk SDDR-55 SmartMedia Card Reader
+ b000 USB to CompactFlash Card Reader
+ b004 OnSpec MMC/SD Reader/Writer
+ b00b USB to Memory Stick Card Reader
+ b00c USB to SmartMedia Card Reader
+ b012 Mitsumi FA402M 8-in-2 Card Reader
+ b200 Compact Flash Reader
+ b204 MMC/ SD Reader
+ b207 Memory Stick Reader
+5986 Acer, Inc
+ 0102 Crystal Eye webcam
+5a57 Zinwell
+ 0260 RT2570
+6189 Sitecom
+ 182d USB 2.0 Ethernet
+ 2068 USB to serial cable (v2)
+6253 TwinHan Technology Co., Ltd
+ 0100 Ir reciver f. remote control
+636c CoreLogic, Inc.
+6547 Arkmicro Technologies Inc.
+ 0232 ARK3116 Serial
+6666 Prototype product Vendor ID
+ 0667 WiseGroup Smart Joy PSX, PS-PC Smart JoyPad
+ 2667 JCOP BlueZ Smartcard reader
+ 8804 WiseGroup SuperJoy Box 5
+6891 3Com
+ a727 3CRUSB10075
+6993 Freshtel
+ b001 FT-102 VoIP USB Phone
+6a75 Shanghai Jujo Electronics Co., Ltd
+7104 CME (Central Music Co.)
+ 2202 UF5/UF6/UF7/UF8 MIDI Master Keyboard
+8086 Intel Corp.
+ 0001 AnyPoint (TM) Home Network 1.6 Mbps Wireless Adapter
+ 0100 Personal Audio Player 3000
+ 0101 Personal Audio Player 3000
+ 0110 Easy PC Camera
+ 0120 PC Camera CS120
+ 0200 AnyPoint(TM) Wireless II Network 11Mbps Adapter
+ 0431 Intel Pro Video PC Camera
+ 0510 Digital Movie Creator
+ 0630 Pocket PC Camera
+ 0780 CS780 Microphone Input
+ 07d3 BLOB boot loader firmware
+ 0dad Cherry MiniatureCard Keyboard
+ 1010 AnyPoint(TM) Home Network 10 Mbps Phoneline Adapter
+ 110a Bluetooth Controller from (Ericsson P4A)
+ 110b Bluetooth Controller from (Intel/CSR)
+ 1110 PRO/Wireless LAN Module
+ 1111 PRO/Wireless 2011B 802.11b Adapter
+ 1134 Hollister Mobile Monitor
+ 1234 Prototype Reader/Writer
+ 3100 PRO/DSL 3220 Modem - WAN
+ 3101 PRO/DSL 3220 Modem
+ 3240 AnyPoint® 3240 Modem - WAN
+ 3241 AnyPoint® 3240 Modem
+ 8602 Miniature Card Slot
+ 9303 Intel 8x930Hx Hub
+ 9890 82930 Test Board
+ beef SCM Miniature Card Reader/Writer
+ c013 Wireless HID Station
+ f001 XScale PXA27x Bulverde flash
+8341 EGO Systems, Inc.
+ 2000 Flashdisk
+9016 Sitecom
+ 182d WL-022
+9710 MosChip Semiconductor
+ 7703 MCS7703 Serial Port Adapter
+ 7705 Printer cable
+ 7715 Printer cable
+ 7780 MS7780 4Mbps Fast IRDA Adapter
+ 7830 MCS7830 Ethernet
+a727 3Com
+ 6893 AR5523
+ 6895 AR5523
+ 6897 AR5523
+c251 Keil Software, Inc.
+ 2710 ULink
+eb1a eMPIA Technology, Inc.
+ 17de KWorld V-Stream XPERT DTV - DVB-T USB cold
+ 17df KWorld V-Stream XPERT DTV - DVB-T USB warm
+ 2710 SilverCrest WebCam
+ 2750 ECS Elitegroup G220 integrated webcam
+ 2800 Terratec Cinergy 200
+ 2801 GrabBeeX+ Video Encoder
+f003 Hewlett Packard
+ 6002 PhotoSmart C500
+
+# List of known device classes, subclasses and protocols
+
+# Syntax:
+# C class class_name
+# subclass subclass_name <-- single tab
+# protocol protocol_name <-- two tabs
+
+C 00 (Defined at Interface level)
+C 01 Audio
+ 01 Control Device
+ 02 Streaming
+ 03 MIDI Streaming
+C 02 Communications
+ 01 Direct Line
+ 02 Abstract (modem)
+ 00 None
+ 01 AT-commands (v.25ter)
+ 02 AT-commands (PCCA101)
+ 03 AT-commands (PCCA101 + wakeup)
+ 04 AT-commands (GSM)
+ 05 AT-commands (3G)
+ 06 AT-commands (CDMA)
+ fe Defined by command set descriptor
+ ff Vendor Specific (MSFT RNDIS?)
+ 03 Telephone
+ 04 Multi-Channel
+ 05 CAPI Control
+ 06 Ethernet Networking
+ 07 ATM Networking
+ 08 Wireless Handset Control
+ 09 Device Management
+ 0a Mobile Direct Line
+ 0b OBEX
+ 0c Ethernet Emulation
+ 07 Ethernet Emulation (EEM)
+C 03 Human Interface Device
+ 00 No Subclass
+ 00 None
+ 01 Keyboard
+ 02 Mouse
+ 01 Boot Interface Subclass
+ 00 None
+ 01 Keyboard
+ 02 Mouse
+C 05 Physical Interface Device
+C 06 Imaging
+ 01 Still Image Capture
+ 01 Picture Transfer Protocol (PIMA 15470)
+C 07 Printer
+ 01 Printer
+ 00 Reserved/Undefined
+ 01 Unidirectional
+ 02 Bidirectional
+ 03 IEEE 1284.4 compatible bidirectional
+ ff Vendor Specific
+C 08 Mass Storage
+ 01 RBC (typically Flash)
+ 00 Control/Bulk/Interrupt
+ 01 Control/Bulk
+ 50 Bulk (Zip)
+ 02 SFF-8020i, MMC-2 (ATAPI)
+ 03 QIC-157
+ 04 Floppy (UFI)
+ 00 Control/Bulk/Interrupt
+ 01 Control/Bulk
+ 50 Bulk (Zip)
+ 05 SFF-8070i
+ 06 SCSI
+ 00 Control/Bulk/Interrupt
+ 01 Control/Bulk
+ 50 Bulk (Zip)
+C 09 Hub
+ 00 Unused
+ 00 Full speed (or root) hub
+ 01 Single TT
+ 02 TT per port
+C 0a CDC Data
+ 00 Unused
+ 30 I.430 ISDN BRI
+ 31 HDLC
+ 32 Transparent
+ 50 Q.921M
+ 51 Q.921
+ 52 Q.921TM
+ 90 V.42bis
+ 91 Q.932 EuroISDN
+ 92 V.120 V.24 rate ISDN
+ 93 CAPI 2.0
+ fd Host Based Driver
+ fe CDC PUF
+ ff Vendor specific
+C 0b Chip/SmartCard
+C 0d Content Security
+C 0e Video
+ 00 Undefined
+ 01 Video Control
+ 02 Video Streaming
+ 03 Video Interface Collection
+C dc Diagnostic
+ 01 Reprogrammable Diagnostics
+ 01 USB2 Compliance
+C e0 Wireless
+ 01 Radio Frequency
+ 01 Bluetooth
+ 02 Ultra WideBand Radio Control
+ 03 RNDIS
+ 02 Wireless USB Wire Adapter
+ 01 Host Wire Adapter Control/Data Streaming
+ 02 Device Wire Adapter Control/Data Streaming
+ 03 Device Wire Adapter Isochronous Streaming
+C ef Miscellaneous Device
+ 01 ?
+ 01 Microsoft ActiveSync
+ 02 Palm Sync
+ 02 ?
+ 01 Interface Association
+ 02 Wire Adapter Multifunction Peripheral
+ 03 ?
+ 01 Cable Based Association
+C fe Application Specific Interface
+ 01 Device Firmware Update
+ 02 IRDA Bridge
+ 03 Test and Measurement
+ 01 TMC
+ 02 USB488
+C ff Vendor Specific Class
+ ff Vendor Specific Subclass
+ ff Vendor Specific Protocol
+
+# List of Audio Class Terminal Types
+
+# Syntax:
+# AT terminal_type terminal_type_name
+
+AT 0100 USB Undefined
+AT 0101 USB Streaming
+AT 01ff USB Vendor Specific
+AT 0200 Input Undefined
+AT 0201 Microphone
+AT 0202 Desktop Microphone
+AT 0203 Personal Microphone
+AT 0204 Omni-directional Microphone
+AT 0205 Microphone Array
+AT 0206 Processing Microphone Array
+AT 0300 Output Undefined
+AT 0301 Speaker
+AT 0302 Headphones
+AT 0303 Head Mounted Display Audio
+AT 0304 Desktop Speaker
+AT 0305 Room Speaker
+AT 0306 Communication Speaker
+AT 0307 Low Frequency Effects Speaker
+AT 0400 Bidirectional Undefined
+AT 0401 Handset
+AT 0402 Headset
+AT 0403 Speakerphone, no echo reduction
+AT 0404 Echo-suppressing speakerphone
+AT 0405 Echo-canceling speakerphone
+AT 0500 Telephony Undefined
+AT 0501 Phone line
+AT 0502 Telephone
+AT 0503 Down Line Phone
+AT 0600 External Undefined
+AT 0601 Analog Connector
+AT 0602 Digital Audio Interface
+AT 0603 Line Connector
+AT 0604 Legacy Audio Connector
+AT 0605 SPDIF interface
+AT 0606 1394 DA stream
+AT 0607 1394 DV stream soundtrack
+AT 0700 Embedded Undefined
+AT 0701 Level Calibration Noise Source
+AT 0702 Equalization Noise
+AT 0703 CD Player
+AT 0704 DAT
+AT 0705 DCC
+AT 0706 MiniDisc
+AT 0707 Analog Tape
+AT 0708 Phonograph
+AT 0709 VCR Audio
+AT 070a Video Disc Audio
+AT 070b DVD Audio
+AT 070c TV Tuner Audio
+AT 070d Satellite Receiver Audio
+AT 070e Cable Tuner Audio
+AT 070f DSS Audio
+AT 0710 Radio Receiver
+AT 0711 Radio Transmitter
+AT 0712 Multitrack Recorder
+AT 0713 Synthesizer
+
+# List of HID Descriptor Types
+
+# Syntax:
+# HID descriptor_type descriptor_type_name
+
+HID 21 HID
+HID 22 Report
+HID 23 Physical
+
+# List of HID Descriptor Item Types
+# Note: 2 bits LSB encode data length following
+
+# Syntax:
+# R item_type item_type_name
+
+# Main Items
+R 80 Input
+R 90 Output
+R b0 Feature
+R a0 Collection
+R c0 End Collection
+
+# Global Items
+R 04 Usage Page
+R 14 Logical Minimum
+R 24 Logical Maximum
+R 34 Physical Minimum
+R 44 Physical Maximum
+R 54 Unit Exponent
+R 64 Unit
+R 74 Report Size
+R 84 Report ID
+R 94 Report Count
+R a4 Push
+R b4 Pop
+
+# Local Items
+R 08 Usage
+R 18 Usage Minimum
+R 28 Usage Maximum
+R 38 Designator Index
+R 48 Designator Minimum
+R 58 Designator Maximum
+R 78 String Index
+R 88 String Minimum
+R 98 String Maximum
+R a8 Delimiter
+
+# List of Physical Descriptor Bias Types
+
+# Syntax:
+# BIAS item_type item_type_name
+
+BIAS 0 Not Applicable
+BIAS 1 Right Hand
+BIAS 2 Left Hand
+BIAS 3 Both Hands
+BIAS 4 Either Hand
+
+# List of Physical Descriptor Item Types
+
+# Syntax:
+# PHY item_type item_type_name
+
+PHY 00 None
+PHY 01 Hand
+PHY 02 Eyeball
+PHY 03 Eyebrow
+PHY 04 Eyelid
+PHY 05 Ear
+PHY 06 Nose
+PHY 07 Mouth
+PHY 08 Upper Lip
+PHY 09 Lower Lip
+PHY 0a Jaw
+PHY 0b Neck
+PHY 0c Upper Arm
+PHY 0d Elbow
+PHY 0e Forearm
+PHY 0f Wrist
+PHY 10 Palm
+PHY 11 Thumb
+PHY 12 Index Finger
+PHY 13 Middle Finger
+PHY 14 Ring Finger
+PHY 15 Little Finger
+PHY 16 Head
+PHY 17 Shoulder
+PHY 18 Hip
+PHY 19 Waist
+PHY 1a Thigh
+PHY 1b Knee
+PHY 1c calf
+PHY 1d Ankle
+PHY 1e Foot
+PHY 1f Heel
+PHY 20 Ball of Foot
+PHY 21 Big Toe
+PHY 22 Second Toe
+PHY 23 Third Toe
+PHY 24 Fourth Toe
+PHY 25 Fifth Toe
+PHY 26 Brow
+PHY 27 Cheek
+
+# List of HID Usages
+
+# Syntax:
+# HUT hi _usage_page hid_usage_page_name
+# hid_usage hid_usage_name
+
+HUT 00 Undefined
+HUT 01 Generic Desktop Controls
+ 000 Undefined
+ 001 Pointer
+ 002 Mouse
+ 004 Joystick
+ 005 Gamepad
+ 006 Keyboard
+ 007 Keypad
+ 008 Multi-Axis Controller
+ 030 Direction-X
+ 031 Direction-Y
+ 032 Direction-Z
+ 033 Rotate-X
+ 034 Rotate-Y
+ 035 Rotate-Z
+ 036 Slider
+ 037 Dial
+ 038 Wheel
+ 039 Hat Switch
+ 03a Counted Buffer
+ 03b Byte Count
+ 03c Motion Wakeup
+ 03d Start
+ 03e Select
+ 040 Vector-X
+ 041 Vector-Y
+ 042 Vector-Z
+ 043 Vector-X relative Body
+ 044 Vector-Y relative Body
+ 045 Vector-Z relative Body
+ 046 Vector
+ 080 System Control
+ 081 System Power Down
+ 082 System Sleep
+ 083 System Wake Up
+ 084 System Context Menu
+ 085 System Main Menu
+ 086 System App Menu
+ 087 System Menu Help
+ 088 System Menu Exit
+ 089 System Menu Select
+ 08a System Menu Right
+ 08b System Menu Left
+ 08c System Menu Up
+ 08d System Menu Down
+ 090 Direction Pad Up
+ 091 Direction Pad Down
+ 092 Direction Pad Right
+ 093 Direction Pad Left
+HUT 02 Simulation Controls
+ 000 Undefined
+ 001 Flight Simulation Device
+ 002 Automobile Simulation Device
+ 003 Tank Simulation Device
+ 004 Spaceship Simulation Device
+ 005 Submarine Simulation Device
+ 006 Sailing Simulation Device
+ 007 Motorcycle Simulation Device
+ 008 Sports Simulation Device
+ 009 Airplane Simualtion Device
+ 00a Helicopter Simulation Device
+ 00b Magic Carpet Simulation Device
+ 00c Bicycle Simulation Device
+ 020 Flight Control Stick
+ 021 Flight Stick
+ 022 Cyclic Control
+ 023 Cyclic Trim
+ 024 Flight Yoke
+ 025 Track Control
+ 0b0 Aileron
+ 0b1 Aileron Trim
+ 0b2 Anti-Torque Control
+ 0b3 Autopilot Enable
+ 0b4 Chaff Release
+ 0b5 Collective Control
+ 0b6 Dive Break
+ 0b7 Electronic Countermeasures
+ 0b8 Elevator
+ 0b9 Elevator Trim
+ 0ba Rudder
+ 0bb Throttle
+ 0bc Flight COmmunications
+ 0bd Flare Release
+ 0be Landing Gear
+ 0bf Toe Break
+ 0c0 Trigger
+ 0c1 Weapon Arm
+ 0c2 Weapons Select
+ 0c3 Wing Flaps
+ 0c4 Accelerator
+ 0c5 Brake
+ 0c6 Clutch
+ 0c7 Shifter
+ 0c8 Steering
+ 0c9 Turret Direction
+ 0ca Barrel Elevation
+ 0cb Drive Plane
+ 0cc Ballast
+ 0cd Bicylce Crank
+ 0ce Handle Bars
+ 0cf Front Brake
+ 0d0 Rear Brake
+HUT 03 VR Controls
+ 000 Unidentified
+ 001 Belt
+ 002 Body Suit
+ 003 Flexor
+ 004 Glove
+ 005 Head Tracker
+ 006 Head Mounted Display
+ 007 Hand Tracker
+ 008 Oculometer
+ 009 Vest
+ 00a Animatronic Device
+ 020 Stereo Enable
+ 021 Display Enable
+HUT 04 Sport Controls
+ 000 Unidentified
+ 001 Baseball Bat
+ 002 Golf Club
+ 003 Rowing Machine
+ 004 Treadmill
+ 030 Oar
+ 031 Slope
+ 032 Rate
+ 033 Stick Speed
+ 034 Stick Face Angle
+ 035 Stick Heel/Toe
+ 036 Stick Follow Through
+ 047 Stick Temp
+ 038 Stick Type
+ 039 Stick Height
+ 050 Putter
+ 051 1 Iron
+ 052 2 Iron
+ 053 3 Iron
+ 054 4 Iron
+ 055 5 Iron
+ 056 6 Iron
+ 057 7 Iron
+ 058 8 Iron
+ 059 9 Iron
+ 05a 10 Iron
+ 05b 11 Iron
+ 05c Sand Wedge
+ 05d Loft Wedge
+ 05e Power Wedge
+ 05f 1 Wood
+ 060 3 Wood
+ 061 5 Wood
+ 062 7 Wood
+ 063 9 Wood
+HUT 05 Game Controls
+ 000 Undefined
+ 001 3D Game Controller
+ 002 Pinball Device
+ 003 Gun Device
+ 020 Point Of View
+ 021 Turn Right/Left
+ 022 Pitch Right/Left
+ 023 Roll Forward/Backward
+ 024 Move Right/Left
+ 025 Move Forward/Backward
+ 026 Move Up/Down
+ 027 Lean Right/Left
+ 028 Lean Forward/Backward
+ 029 Height of POV
+ 02a Flipper
+ 02b Secondary Flipper
+ 02c Bump
+ 02d New Game
+ 02e Shoot Ball
+ 02f Player
+ 030 Gun Bolt
+ 031 Gun Clip
+ 032 Gun Selector
+ 033 Gun Single Shot
+ 034 Gun Burst
+ 035 Gun Automatic
+ 036 Gun Safety
+ 037 Gamepad Fire/Jump
+ 038 Gamepad Fun
+ 039 Gamepad Trigger
+HUT 07 Keyboard
+ 000 No Event
+ 001 Keyboard ErrorRollOver
+ 002 Keyboard POSTfail
+ 003 Keyboard Error Undefined
+ 004 A
+ 005 B
+ 006 C
+ 007 D
+ 008 E
+ 009 F
+ 00a G
+ 00b H
+ 00c I
+ 00d J
+ 00e K
+ 00f L
+ 010 M
+ 011 N
+ 012 O
+ 013 P
+ 014 Q
+ 015 R
+ 016 S
+ 017 T
+ 018 U
+ 019 V
+ 01a W
+ 01b X
+ 01c Y
+ 01d Z
+ 01e 1 and ! (One and Exclamation)
+ 01f 2 and @ (2 and at)
+ 020 3 and # (3 and Hash)
+ 021 4 and $ (4 and Dollar Sign)
+ 022 5 and % (5 and Percent Sign)
+ 023 6 and ^ (6 and circumflex)
+ 024 7 and & (Seven and Ampersand)
+ 025 8 and * (Eight and asterisk)
+ 026 9 and ( (Nine and Parenthesis Left)
+ 027 0 and ) (Zero and Parenthesis Right)
+ 028 Return (Enter)
+ 029 Escape
+ 02a Delete (Backspace)
+ 02b Tab
+ 02c Space Bar
+ 02d - and _ (Minus and underscore)
+ 02e = and + (Equal and Plus)
+ 02f [ and { (Bracket and Braces Left)
+ 030 ] and } (Bracket and Braces Right)
+ 031 \ and | (Backslash and Bar)
+ 032 # and ~ (Hash and Tilde, Non-US Keyboard near right shift)
+ 033 ; and : (Semicolon and Colon)
+ 034 ´ and " (Accent Acute and Double Quotes)
+ 035 ` and ~ (Accent Grace and Tilde)
+ 036 , and < (Comma and Less)
+ 037 . and > (Period and Greater)
+ 038 / and ? (Slash and Question Mark)
+ 039 Caps Lock
+ 03a F1
+ 03b F2
+ 03c F3
+ 03d F4
+ 03e F5
+ 03f F6
+ 040 F7
+ 041 F8
+ 042 F9
+ 043 F10
+ 044 F11
+ 045 F12
+ 046 Print Screen
+ 047 Scroll Lock
+ 048 Pause
+ 049 Insert
+ 04a Home
+ 04b Page Up
+ 04c Delete Forward (without Changing Position)
+ 04d End
+ 04e Page Down
+ 04f Right Arrow
+ 050 Left Arrow
+ 051 Down Arrow
+ 052 Up Arrow
+ 053 Num Lock and Clear
+ 054 Keypad / (Division Sign)
+ 055 Keypad * (Multiplication Sign)
+ 056 Keypad - (Subtraction Sign)
+ 057 Keypad + (Addition Sign)
+ 058 Keypad Enter
+ 059 Keypad 1 and END
+ 05a Keypad 2 and Down Arrow
+ 05b Keypad 3 and Page Down
+ 05c Keypad 4 and Left Arrow
+ 05d Keypad 5 (Tactilei Raised)
+ 05f Keypad 6 and Right Arrow
+ 060 Keypad 7 and Home
+ 061 Keypad 8 and Up Arrow
+ 062 Keypad 8 and Page Up
+ 063 Keypad . (decimal delimiter) and Delete
+ 064 \ and | (Backslash and Bar, UK and Non-US Keyboard near left shift)
+ 065 Keyboard Application (Windows Key for Win95 or Compose)
+ 066 Power (not a key)
+ 067 Keypad = (Equal Sign)
+ 068 F13
+ 069 F14
+ 06a F15
+ 06b F16
+ 06c F17
+ 06d F18
+ 06e F19
+ 06f F20
+ 070 F21
+ 071 F22
+ 072 F23
+ 073 F24
+ 074 Execute
+ 075 Help
+ 076 Menu
+ 077 Select
+ 078 Stop
+ 079 Again
+ 07a Undo
+ 07b Cut
+ 07c Copy
+ 07d Paste
+ 07e Find
+ 07f Mute
+ 080 Volume Up
+ 081 Volume Down
+ 082 Locking Caps Lock
+ 083 Locking Num Lock
+ 084 Locking Scroll Lock
+ 085 Keypad Comma
+ 086 Keypad Equal Sign (AS/400)
+ 087 International 1 (PC98)
+ 088 International 2 (PC98)
+ 089 International 3 (PC98)
+ 08a International 4 (PC98)
+ 08b International 5 (PC98)
+ 08c International 6 (PC98)
+ 08d International 7 (Toggle Single/Double Byte Mode)
+ 08e International 8
+ 08f International 9
+ 090 LANG 1 (Hangul/English Toggle, Korea)
+ 091 LANG 2 (Hanja Conversion, Korea)
+ 092 LANG 3 (Katakana, Japan)
+ 093 LANG 4 (Hiragana, Japan)
+ 094 LANG 5 (Zenkaku/Hankaku, Japan)
+ 095 LANG 6
+ 096 LANG 7
+ 097 LANG 8
+ 098 LANG 9
+ 099 Alternate Erase
+ 09a SysReq/Attention
+ 09b Cancel
+ 09c Clear
+ 09d Prior
+ 09e Return
+ 09f Separator
+ 0a0 Out
+ 0a1 Open
+ 0a2 Clear/Again
+ 0a3 CrSel/Props
+ 0a4 ExSel
+ 0e0 Control Left
+ 0e1 Shift Left
+ 0e2 Alt Left
+ 0e3 GUI Left
+ 0e4 Control Right
+ 0e5 Shift Right
+ 0e6 Alt Rigth
+ 0e7 GUI Right
+HUT 08 LEDs
+ 000 Undefined
+ 001 NumLock
+ 002 CapsLock
+ 003 Scroll Lock
+ 004 Compose
+ 005 Kana
+ 006 Power
+ 007 Shift
+ 008 Do not disturb
+ 009 Mute
+ 00a Tone Enabke
+ 00b High Cut Filter
+ 00c Low Cut Filter
+ 00d Equalizer Enable
+ 00e Sound Field ON
+ 00f Surround On
+ 010 Repeat
+ 011 Stereo
+ 012 Sampling Rate Detect
+ 013 Spinning
+ 014 CAV
+ 015 CLV
+ 016 Recording Format Detect
+ 017 Off-Hook
+ 018 Ring
+ 019 Message Waiting
+ 01a Data Mode
+ 01b Battery Operation
+ 01c Battery OK
+ 01d Battery Low
+ 01e Speaker
+ 01f Head Set
+ 020 Hold
+ 021 Microphone
+ 022 Coverage
+ 023 Night Mode
+ 024 Send Calls
+ 025 Call Pickup
+ 026 Conference
+ 027 Stand-by
+ 028 Camera On
+ 029 Camera Off
+ 02a On-Line
+ 02b Off-Line
+ 02c Busy
+ 02d Ready
+ 02e Paper-Out
+ 02f Paper-Jam
+ 030 Remote
+ 031 Forward
+ 032 Reverse
+ 033 Stop
+ 034 Rewind
+ 035 Fast Forward
+ 036 Play
+ 037 Pause
+ 038 Record
+ 039 Error
+ 03a Usage Selected Indicator
+ 03b Usage In Use Indicator
+ 03c Usage Multi Indicator
+ 03d Indicator On
+ 03e Indicator Flash
+ 03f Indicator Slow Blink
+ 040 Indicator Fast Blink
+ 041 Indicator Off
+ 042 Flash On Time
+ 043 Slow Blink On Time
+ 044 Slow Blink Off Time
+ 045 Fast Blink On Time
+ 046 Fast Blink Off Time
+ 047 Usage Color Indicator
+ 048 Indicator Red
+ 049 Indicator Green
+ 04a Indicator Amber
+ 04b Generic Indicator
+ 04c System Suspend
+ 04d External Power Connected
+HUT 09 Buttons
+ 000 No Button Pressed
+ 001 Button 1 (Primary)
+ 002 Button 2 (Secondary)
+ 003 Button 3 (Tertiary)
+ 004 Button 4
+ 005 Button 5
+HUT 0a Ordinal
+ 001 Instance 1
+ 002 Instance 2
+ 003 Instance 3
+HUT 0b Telephony
+ 000 Unassigned
+ 001 Phone
+ 002 Answering Machine
+ 003 Message Controls
+ 004 Handset
+ 005 Headset
+ 006 Telephony Key Pad
+ 007 Programmable Button
+ 020 Hook Switch
+ 021 Flash
+ 022 Feature
+ 023 Hold
+ 024 Redial
+ 025 Transfer
+ 026 Drop
+ 027 Park
+ 028 Forward Calls
+ 029 Alternate Function
+ 02a Line
+ 02b Speaker Phone
+ 02c Conference
+ 02d Ring Enable
+ 02e Ring Select
+ 02f Phone Mute
+ 030 Caller ID
+ 050 Speed Dial
+ 051 Store Number
+ 052 Recall Number
+ 053 Phone Directory
+ 070 Voice Mail
+ 071 Screen Calls
+ 072 Do Not Disturb
+ 073 Message
+ 074 Answer On/Offf
+ 090 Inside Dial Tone
+ 091 Outside Dial Tone
+ 092 Inside Ring Tone
+ 093 Outside Ring Tone
+ 094 Priority Ring Tone
+ 095 Inside Ringback
+ 096 Priority Ringback
+ 097 Line Busy Tone
+ 098 Recorder Tone
+ 099 Call Waiting Tone
+ 09a Confirmation Tone 1
+ 09b Confirmation Tone 2
+ 09c Tones Off
+ 09d Outside Ringback
+ 0b0 Key 1
+ 0b1 Key 2
+ 0b3 Key 3
+ 0b4 Key 4
+ 0b5 Key 5
+ 0b6 Key 6
+ 0b7 Key 7
+ 0b8 Key 8
+ 0b9 Key 9
+ 0ba Key Star
+ 0bb Key Pound
+ 0bc Key A
+ 0bd Key B
+ 0be Key C
+ 0bf Key D
+HUT 0c Consumer
+ 000 Unassigned
+ 001 Consumer Control
+ 002 Numeric Key Pad
+ 003 Programmable Buttons
+ 020 +10
+ 021 +100
+ 022 AM/PM
+ 030 Power
+ 031 Reset
+ 032 Sleep
+ 033 Sleep After
+ 034 Sleep Mode
+ 035 Illumination
+ 036 Function Buttons
+ 040 Menu
+ 041 Menu Pick
+ 042 Menu Up
+ 043 Menu Down
+ 044 Menu Left
+ 045 Menu Right
+ 046 Menu Escape
+ 047 Menu Value Increase
+ 048 Menu Value Decrease
+ 060 Data on Screen
+ 061 Closed Caption
+ 062 Closed Caption Select
+ 063 VCR/TV
+ 064 Broadcast Mode
+ 065 Snapshot
+ 066 Still
+ 080 Selection
+ 081 Assign Selection
+ 082 Mode Step
+ 083 Recall Last
+ 084 Enter Channel
+ 085 Order Movie
+ 086 Channel
+ 087 Media Selection
+ 088 Media Select Computer
+ 089 Media Select TV
+ 08a Media Select WWW
+ 08b Media Select DVD
+ 08c Media Select Telephone
+ 08d Media Select Program Guide
+ 08e Media Select Video Phone
+ 08f Media Select Games
+ 090 Media Select Messages
+ 091 Media Select CD
+ 092 Media Select VCR
+ 093 Media Select Tuner
+ 094 Quit
+ 095 Help
+ 096 Media Select Tape
+ 097 Media Select Cable
+ 098 Media Select Satellite
+ 099 Media Select Security
+ 09a Media Select Home
+ 09b Media Select Call
+ 09c Channel Increment
+ 09d Channel Decrement
+ 09e Media Select SAP
+ 0a0 VCR Plus
+ 0a1 Once
+ 0a2 Daily
+ 0a3 Weekly
+ 0a4 Monthly
+ 0b0 Play
+ 0b1 Pause
+ 0b2 Record
+ 0b3 Fast Forward
+ 0b4 Rewind
+ 0b5 Scan Next Track
+ 0b6 Scan Previous Track
+ 0b7 Stop
+ 0b8 Eject
+ 0b9 Random Play
+ 0ba Select Disc
+ 0bb Enter Disc
+ 0bc Repeat
+ 0bd Tracking
+ 0be Track Normal
+ 0bf Slow Tracking
+ 0c0 Frame Forward
+ 0c1 Frame Back
+ 0c2 Mark
+ 0c3 Clear Mark
+ 0c4 Repeat from Mark
+ 0c5 Return to Mark
+ 0c6 Search Mark Forward
+ 0c7 Search Mark Backward
+ 0c8 Counter Reset
+ 0c9 Show Counter
+ 0ca Tracking Increment
+ 0cb Tracking Decrement
+ 0cc Stop/Eject
+ 0cd Play/Pause
+ 0ce Play/Skip
+ 0e0 Volume
+ 0e1 Balance
+ 0e2 Mute
+ 0e3 Bass
+ 0e4 Treble
+ 0e5 Bass Boost
+ 0e6 Surround Mode
+ 0e7 Loudness
+ 0e8 MPX
+ 0e9 Volume Increment
+ 0ea Volume Decrement
+ 0f0 Speed Select
+ 0f1 Playback Speed
+ 0f2 Standard Play
+ 0f3 Long Play
+ 0f4 Extended Play
+ 0f5 Slow
+ 100 Fan Enable
+ 101 Fan Speed
+ 102 Light Enable
+ 103 Light Illumination Level
+ 104 Climate Control Enable
+ 105 Room Temperature
+ 106 Security Enable
+ 107 Fire Alarm
+ 108 Police Alarm
+ 150 Balance Right
+ 151 Balance Left
+ 152 Bass Increment
+ 153 Bass Decrement
+ 154 Treble Increment
+ 155 Treble Decrement
+ 160 Speaker System
+ 161 Channel Left
+ 162 Channel Right
+ 163 Channel Center
+ 164 Channel Front
+ 165 Channel Center Front
+ 166 Channel Side
+ 167 Channel Surround
+ 168 Channel Low Frequency Enhancement
+ 169 Channel Top
+ 16a Channel Unknown
+ 170 Sub-Channel
+ 171 Sub-Channel Increment
+ 172 Sub-Channel Decrement
+ 173 Alternative Audio Increment
+ 174 Alternative Audio Decrement
+ 180 Application Launch Buttons
+ 181 AL Launch Button Configuration Tool
+ 182 AL Launch Button Configuration
+ 183 AL Consumer Control Configuration
+ 184 AL Word Processor
+ 185 AL Text Editor
+ 186 AL Spreadsheet
+ 187 AL Graphics Editor
+ 188 AL Presentation App
+ 189 AL Database App
+ 18a AL Email Reader
+ 18b AL Newsreader
+ 18c AL Voicemail
+ 18d AL Contacts/Address Book
+ 18e AL Calendar/Schedule
+ 18f AL Task/Project Manager
+ 190 AL Log/Jounal/Timecard
+ 191 AL Checkbook/Finance
+ 192 AL Calculator
+ 193 AL A/V Capture/Playback
+ 194 AL Local Machine Browser
+ 195 AL LAN/Wan Browser
+ 196 AL Internet Browser
+ 197 AL Remote Networking/ISP Connect
+ 198 AL Network Conference
+ 199 AL Network Chat
+ 19a AL Telephony/Dialer
+ 19b AL Logon
+ 19c AL Logoff
+ 19d AL Logon/Logoff
+ 19e AL Terminal Local/Screensaver
+ 19f AL Control Panel
+ 1a0 AL Command Line Processor/Run
+ 1a1 AL Process/Task Manager
+ 1a2 AL Select Task/Application
+ 1a3 AL Next Task/Application
+ 1a4 AL Previous Task/Application
+ 1a5 AL Preemptive Halt Task/Application
+ 200 Generic GUI Application Controls
+ 201 AC New
+ 202 AC Open
+ 203 AC CLose
+ 204 AC Exit
+ 205 AC Maximize
+ 206 AC Minimize
+ 207 AC Save
+ 208 AC Print
+ 209 AC Properties
+ 21a AC Undo
+ 21b AC Copy
+ 21c AC Cut
+ 21d AC Paste
+ 21e AC Select All
+ 21f AC Find
+ 220 AC Find and Replace
+ 221 AC Search
+ 222 AC Go To
+ 223 AC Home
+ 224 AC Back
+ 225 AC Forward
+ 226 AC Stop
+ 227 AC Refresh
+ 228 AC Previous Link
+ 229 AC Next Link
+ 22b AC History
+ 22c AC Subscriptions
+ 22d AC Zoom In
+ 22e AC Zoom Out
+ 22f AC Zoom
+ 230 AC Full Screen View
+ 231 AC Normal View
+ 232 AC View Toggle
+ 233 AC Scroll Up
+ 234 AC Scroll Down
+ 235 AC Scroll
+ 236 AC Pan Left
+ 237 AC Pan Right
+ 238 AC Pan
+ 239 AC New Window
+ 23a AC Tile Horizontally
+ 23b AC Tile Vertically
+ 23c AC Format
+HUT 0d Digitizer
+ 000 Undefined
+ 001 Digitizer
+ 002 Pen
+ 003 Light Pen
+ 004 Touch Screen
+ 005 Touch Pad
+ 006 White Board
+ 007 Coordinate Measuring Machine
+ 008 3D Digitizer
+ 009 Stereo Plotter
+ 00a Articulated Arm
+ 00b Armature
+ 00c Multiple Point Digitizer
+ 00d Free Space Wand
+ 020 Stylus
+ 021 Puck
+ 022 Finger
+ 030 Tip Pressure
+ 031 Barrel Pressure
+ 032 In Range
+ 033 Touch
+ 034 Untouch
+ 035 Tap
+ 036 Quality
+ 037 Data Valid
+ 038 Transducer Index
+ 039 Tablet Function Keys
+ 03a Program Change Keys
+ 03b Battery Strength
+ 03c Invert
+ 03d X Tilt
+ 03e Y Tilt
+ 03f Azimuth
+ 040 Altitude
+ 041 Twist
+ 042 Tip Switch
+ 043 Secondary Tip Switch
+ 044 Barrel Switch
+ 045 Eraser
+ 046 Tablet Pick
+HUT 0f PID Page
+ 000 Undefined
+ 001 Physical Interface Device
+ 020 Normal
+ 021 Set Effect Report
+ 022 Effect Block Index
+ 023 Parameter Block Offset
+ 024 ROM Flag
+ 025 Effect Type
+ 026 ET Constant Force
+ 027 ET Ramp
+ 028 ET Custom Force Data
+ 030 ET Square
+ 031 ET Sine
+ 032 ET Triangle
+ 033 ET Sawtooth Up
+ 034 ET Sawtooth Down
+ 040 ET Spring
+ 041 ET Damper
+ 042 ET Inertia
+ 043 ET Friction
+ 050 Duration
+ 051 Sample Period
+ 052 Gain
+ 053 Trigger Button
+ 054 Trigger Repeat Interval
+ 055 Axes Enable
+ 056 Direction Enable
+ 057 Direction
+ 058 Type Specific Block Offset
+ 059 Block Type
+ 05A Set Envelope Report
+ 05B Attack Level
+ 05C Attack Time
+ 05D Fade Level
+ 05E Fade Time
+ 05F Set Condition Report
+ 060 CP Offset
+ 061 Positive Coefficient
+ 062 Negative Coefficient
+ 063 Positive Saturation
+ 064 Negative Saturation
+ 065 Dead Band
+ 066 Download Force Sample
+ 067 Isoch Custom Force Enable
+ 068 Custom Force Data Report
+ 069 Custom Force Data
+ 06A Custom Force Vendor Defined Data
+ 06B Set Custom Force Report
+ 06C Custom Force Data Offset
+ 06D Sample Count
+ 06E Set Periodic Report
+ 06F Offset
+ 070 Magnitude
+ 071 Phase
+ 072 Period
+ 073 Set Constant Force Report
+ 074 Set Ramp Force Report
+ 075 Ramp Start
+ 076 Ramp End
+ 077 Effect Operation Report
+ 078 Effect Operation
+ 079 Op Effect Start
+ 07A Op Effect Start Solo
+ 07B Op Effect Stop
+ 07C Loop Count
+ 07D Device Gain Report
+ 07E Device Gain
+ 07F PID Pool Report
+ 080 RAM Pool Size
+ 081 ROM Pool Size
+ 082 ROM Effect Block Count
+ 083 Simultaneous Effects Max
+ 084 Pool Alignment
+ 085 PID Pool Move Report
+ 086 Move Source
+ 087 Move Destination
+ 088 Move Length
+ 089 PID Block Load Report
+ 08B Block Load Status
+ 08C Block Load Success
+ 08D Block Load Full
+ 08E Block Load Error
+ 08F Block Handle
+ 090 PID Block Free Report
+ 091 Type Specific Block Handle
+ 092 PID State Report
+ 094 Effect Playing
+ 095 PID Device Control Report
+ 096 PID Device Control
+ 097 DC Enable Actuators
+ 098 DC Disable Actuators
+ 099 DC Stop All Effects
+ 09A DC Device Reset
+ 09B DC Device Pause
+ 09C DC Device Continue
+ 09F Device Paused
+ 0A0 Actuators Enabled
+ 0A4 Safety Switch
+ 0A5 Actuator Override Switch
+ 0A6 Actuator Power
+ 0A7 Start Delay
+ 0A8 Parameter Block Size
+ 0A9 Device Managed Pool
+ 0AA Shared Parameter Blocks
+ 0AB Create New Effect Report
+ 0AC RAM Pool Available
+HUT 10 Unicode
+HUT 14 Alphanumeric Display
+ 000 Undefined
+ 001 Alphanumeric Display
+ 020 Display Attributes Report
+ 021 ASCII Character Set
+ 022 Data Read Back
+ 023 Font Read Back
+ 024 Display Control Report
+ 025 Clear Display
+ 026 Display Enable
+ 027 Screen Saver Delay
+ 028 Screen Saver Enable
+ 029 Vertical Scroll
+ 02a Horizontal Scroll
+ 02b Character Report
+ 02c Display Data
+ 02d Display Status
+ 02e Stat Not Ready
+ 02f Stat Ready
+ 030 Err Not a loadable Character
+ 031 Err Font Data Cannot Be Read
+ 032 Cursur Position Report
+ 033 Row
+ 034 Column
+ 035 Rows
+ 036 Columns
+ 037 Cursor Pixel Positioning
+ 038 Cursor Mode
+ 039 Cursor Enable
+ 03a Cursor Blink
+ 03b Font Report
+ 03c Font Data
+ 03d Character Width
+ 03e Character Height
+ 03f Character Spacing Horizontal
+ 040 Character Spacing Vertical
+ 041 Unicode Character Set
+HUT 80 USB Monitor
+ 001 Monitor Control
+ 002 EDID Information
+ 003 VDIF Information
+ 004 VESA Version
+HUT 81 USB Monitor Enumerated Values
+HUT 82 Monitor VESA Virtual Controls
+ 001 Degauss
+ 010 Brightness
+ 012 Contrast
+ 016 Red Video Gain
+ 018 Green Video Gain
+ 01a Blue Video Gain
+ 01c Focus
+ 020 Horizontal Position
+ 022 Horizontal Size
+ 024 Horizontal Pincushion
+ 026 Horizontal Pincushion Balance
+ 028 Horizontal Misconvergence
+ 02a Horizontal Linearity
+ 02c Horizontal Linearity Balance
+ 030 Vertical Position
+ 032 Vertical Size
+ 034 Vertical Pincushion
+ 036 Vertical Pincushion Balance
+ 038 Vertical Misconvergence
+ 03a Vertical Linearity
+ 03c Vertical Linearity Balance
+ 040 Parallelogram Balance (Key Distortion)
+ 042 Trapezoidal Distortion (Key)
+ 044 Tilt (Rotation)
+ 046 Top Corner Distortion Control
+ 048 Top Corner Distortion Balance
+ 04a Bottom Corner Distortion Control
+ 04c Bottom Corner Distortion Balance
+ 056 Horizontal Moire
+ 058 Vertical Moire
+ 05e Input Level Select
+ 060 Input Source Select
+ 06c Red Video Black Level
+ 06e Green Video Black Level
+ 070 Blue Video Black Level
+ 0a2 Auto Size Center
+ 0a4 Polarity Horizontal Sychronization
+ 0a6 Polarity Vertical Synchronization
+ 0aa Screen Orientation
+ 0ac Horizontal Frequency in Hz
+ 0ae Vertical Frequency in 0.1 Hz
+ 0b0 Settings
+ 0ca On Screen Display (OSD)
+ 0d4 Stereo Mode
+HUT 84 Power Device Page
+ 000 Undefined
+ 001 iName
+ 002 Present Status
+ 003 Changed Status
+ 004 UPS
+ 005 Power Supply
+ 010 Battery System
+ 011 Battery System ID
+ 012 Battery
+ 013 Battery ID
+ 014 Charger
+ 015 Charger ID
+ 016 Power Converter
+ 017 Power Converter ID
+ 018 Outlet System
+ 019 Outlet System ID
+ 01a Input
+ 01b Input ID
+ 01c Output
+ 01d Output ID
+ 01e Flow
+ 01f Flow ID
+ 020 Outlet
+ 021 Outlet ID
+ 022 Gang
+ 023 Gang ID
+ 024 Power Summary
+ 025 Power Summary ID
+ 030 Voltage
+ 031 Current
+ 032 Frequency
+ 033 Apparent Power
+ 034 Active Power
+ 035 Percent Load
+ 036 Temperature
+ 037 Humidity
+ 038 Bad Count
+ 040 Config Voltage
+ 041 Config Current
+ 042 Config Frequency
+ 043 Config Apparent Power
+ 044 Config Active Power
+ 045 Config Percent Load
+ 046 Config Temperature
+ 047 Config Humidity
+ 050 Switch On Control
+ 051 Switch Off Control
+ 052 Toggle Control
+ 053 Low Voltage Transfer
+ 054 High Voltage Transfer
+ 055 Delay Before Reboot
+ 056 Delay Before Startup
+ 057 Delay Before Shutdown
+ 058 Test
+ 059 Module Reset
+ 05a Audible Alarm Control
+ 060 Present
+ 061 Good
+ 062 Internal Failure
+ 063 Voltage out of range
+ 064 Frequency out of range
+ 065 Overload
+ 066 Over Charged
+ 067 Over Temperature
+ 068 Shutdown Requested
+ 069 Shutdown Imminent
+ 06a Reserved
+ 06b Switch On/Off
+ 06c Switchable
+ 06d Used
+ 06e Boost
+ 06f Buck
+ 070 Initialized
+ 071 Tested
+ 072 Awaiting Power
+ 073 Communication Lost
+ 0fd iManufacturer
+ 0fe iProduct
+ 0ff iSerialNumber
+HUT 85 Battery System Page
+ 000 Undefined
+ 001 SMB Battery Mode
+ 002 SMB Battery Status
+ 003 SMB Alarm Warning
+ 004 SMB Charger Mode
+ 005 SMB Charger Status
+ 006 SMB Charger Spec Info
+ 007 SMB Selector State
+ 008 SMB Selector Presets
+ 009 SMB Selector Info
+ 010 Optional Mfg. Function 1
+ 011 Optional Mfg. Function 2
+ 012 Optional Mfg. Function 3
+ 013 Optional Mfg. Function 4
+ 014 Optional Mfg. Function 5
+ 015 Connection to SMBus
+ 016 Output Connection
+ 017 Charger Connection
+ 018 Battery Insertion
+ 019 Use Next
+ 01a OK to use
+ 01b Battery Supported
+ 01c SelectorRevision
+ 01d Charging Indicator
+ 028 Manufacturer Access
+ 029 Remaining Capacity Limit
+ 02a Remaining Time Limit
+ 02b At Rate
+ 02c Capacity Mode
+ 02d Broadcast To Charger
+ 02e Primary Battery
+ 02f Charge Controller
+ 040 Terminate Charge
+ 041 Terminate Discharge
+ 042 Below Remaining Capacity Limit
+ 043 Remaining Time Limit Expired
+ 044 Charging
+ 045 Discharging
+ 046 Fully Charged
+ 047 Fully Discharged
+ 048 Conditioning Flag
+ 049 At Rate OK
+ 04a SMB Error Code
+ 04b Need Replacement
+ 060 At Rate Time To Full
+ 061 At Rate Time To Empty
+ 062 Average Current
+ 063 Max Error
+ 064 Relative State Of Charge
+ 065 Absolute State Of Charge
+ 066 Remaining Capacity
+ 067 Full Charge Capacity
+ 068 Run Time To Empty
+ 069 Average Time To Empty
+ 06a Average Time To Full
+ 06b Cycle Count
+ 080 Batt. Pack Model Level
+ 081 Internal Charge Controller
+ 082 Primary Battery Support
+ 083 Design Capacity
+ 084 Specification Info
+ 085 Manufacturer Date
+ 086 Serial Number
+ 087 iManufacturerName
+ 088 iDeviceName
+ 089 iDeviceChemistry
+ 08a Manufacturer Data
+ 08b Rechargeable
+ 08c Warning Capacity Limit
+ 08d Capacity Granularity 1
+ 08e Capacity Granularity 2
+ 08f iOEMInformation
+ 0c0 Inhibit Charge
+ 0c1 Enable Polling
+ 0c2 Reset To Zero
+ 0d0 AC Present
+ 0d1 Battery Present
+ 0d2 Power Fail
+ 0d3 Alarm Inhibited
+ 0d4 Thermistor Under Range
+ 0d5 Thermistor Hot
+ 0d6 Thermistor Cold
+ 0d7 Thermistor Over Range
+ 0d8 Voltage Out Of Range
+ 0d9 Current Out Of Range
+ 0da Current Not Regulated
+ 0db Voltage Not Regulated
+ 0dc Master Mode
+ 0f0 Charger Selector Support
+ 0f1 Charger Spec
+ 0f2 Level 2
+ 0f3 Level 3
+HUT 86 Power Pages
+HUT 87 Power Pages
+HUT 8c Bar Code Scanner Page (POS)
+HUT 8d Scale Page (POS)
+HUT 90 Camera Control Page
+HUT 91 Arcade Control Page
+HUT f0 Cash Device
+ 0f1 Cash Drawer
+ 0f2 Cash Drawer Number
+ 0f3 Cash Drawer Set
+ 0f4 Cash Drawer Status
+HUT ff Vendor Specific
+
+# List of Languages
+
+# Syntax:
+# L language_id language_name
+# dialect_id dialect_name
+
+L 0001 Arabic
+ 01 Saudi Arabia
+ 02 Iraq
+ 03 Egypt
+ 04 Libya
+ 05 Algeria
+ 06 Morocco
+ 07 Tunesia
+ 08 Oman
+ 09 Yemen
+ 0a Syria
+ 0b Jordan
+ 0c Lebanon
+ 0d Kuwait
+ 0e U.A.E
+ 0f Bahrain
+ 10 Qatar
+L 0002 Bulgarian
+L 0003 Catalan
+L 0004 Chinese
+ 01 Traditional
+ 02 Simplified
+ 03 Hongkong SAR, PRC
+ 04 Singapore
+ 05 Macau SAR
+L 0005 Czech
+L 0006 Danish
+L 0007 German
+ 01 German
+ 02 Swiss
+ 03 Austrian
+ 04 Luxembourg
+ 05 Liechtenstein
+L 0008 Greek
+L 0009 English
+ 01 US
+ 02 UK
+ 03 Australian
+ 04 Canadian
+ 05 New Zealand
+ 06 Ireland
+ 07 South Africa
+ 08 Jamaica
+ 09 Carribean
+ 0a Belize
+ 0b Trinidad
+ 0c Zimbabwe
+ 0d Philippines
+L 000a Spanish
+ 01 Castilian
+ 02 Mexican
+ 03 Modern
+ 04 Guatemala
+ 05 Costa Rica
+ 06 Panama
+ 07 Dominican Republic
+ 08 Venzuela
+ 09 Colombia
+ 0a Peru
+ 0b Argentina
+ 0c Ecuador
+ 0d Chile
+ 0e Uruguay
+ 0f Paraguay
+ 10 Bolivia
+ 11 El Salvador
+ 12 Honduras
+ 13 Nicaragua
+ 14 Puerto Rico
+L 000b Finnish
+L 000c French
+ 01 French
+ 02 Belgian
+ 03 Canadian
+ 04 Swiss
+ 05 Luxembourg
+ 06 Monaco
+L 000d Hebrew
+L 000e Hungarian
+L 000f Idelandic
+L 0010 Italian
+ 01 Italian
+ 02 Swiss
+L 0011 Japanese
+L 0012 Korean
+ 01 Korean
+L 0013 Dutch
+ 01 Dutch
+ 02 Belgian
+L 0014 Norwegian
+ 01 Bokmal
+ 02 Nynorsk
+L 0015 Polish
+L 0016 Portuguese
+ 01 Portuguese
+ 02 Brazilian
+L 0017 forgotten
+L 0018 Romanian
+L 0019 Russian
+L 001a Serbian
+ 01 Croatian
+ 02 Latin
+ 03 Cyrillic
+L 001b Slovak
+L 001c Albanian
+L 001d Swedish
+ 01 Swedish
+ 02 Finland
+L 001e Thai
+L 001f Turkish
+L 0020 Urdu
+ 01 Pakistan
+ 02 India
+L 0021 Indonesian
+L 0022 Ukrainian
+L 0023 Belarusian
+L 0024 Slovenian
+L 0025 Estonian
+L 0026 Latvian
+L 0027 Lithuanian
+ 01 Lithuanian
+L 0028 forgotten
+L 0029 Farsi
+L 002a Vietnamese
+L 002b Armenian
+L 002c Azeri
+ 01 Cyrillic
+ 02 Latin
+L 002d Basque
+L 002e forgotten
+L 002f Macedonian
+L 0036 Afrikaans
+L 0037 Georgian
+L 0038 Faeroese
+L 0039 Hindi
+L 003e Malay
+ 01 Malaysia
+ 02 Brunei Darassalam
+L 003f Kazak
+L 0041 Awahili
+L 0043 Uzbek
+ 01 Latin
+ 02 Cyrillic
+L 0044 Tatar
+L 0045 Bengali
+L 0046 Punjabi
+L 0047 Gujarati
+L 0048 Oriya
+L 0049 Tamil
+L 004a Telugu
+L 004b Kannada
+L 004c Malayalam
+L 004d Assamese
+L 004e Marathi
+L 004f Sanskrit
+L 0057 Konkani
+L 0058 Manipuri
+L 0059 Sindhi
+L 0060 Kashmiri
+ 02 India
+L 0061 Nepali
+ 02 India
+
+# HID Descriptor bCountryCode
+# HID Specification 1.11 (2001-06-27) page 23
+#
+# Syntax:
+# HCC country_code keymap_type
+
+HCC 00 Not supported
+HCC 01 Arabic
+HCC 02 Belgian
+HCC 03 Canadian-Bilingual
+HCC 04 Canadian-French
+HCC 05 Czech Republic
+HCC 06 Danish
+HCC 07 Finnish
+HCC 08 French
+HCC 09 German
+HCC 10 Greek
+HCC 11 Hebrew
+HCC 12 Hungary
+HCC 13 International (ISO)
+HCC 14 Italian
+HCC 15 Japan (Katakana)
+HCC 16 Korean
+HCC 17 Latin American
+HCC 18 Netherlands/Dutch
+HCC 19 Norwegian
+HCC 20 Persian (Farsi)
+HCC 21 Poland
+HCC 22 Portuguese
+HCC 23 Russia
+HCC 24 Slovakia
+HCC 25 Spanish
+HCC 26 Swedish
+HCC 27 Swiss/French
+HCC 28 Swiss/German
+HCC 29 Switzerland
+HCC 30 Taiwan
+HCC 31 Turkish-Q
+HCC 32 UK
+HCC 33 US
+HCC 34 Yugoslavia
+HCC 35 Turkish-F
+
+# List of Video Class Terminal Types
+
+# Syntax:
+# VT terminal_type terminal_type_name
+
+VT 0100 USB Vendor Specific
+VT 0101 USB Streaming
+VT 0200 Input Vendor Specific
+VT 0201 Camera Sensor
+VT 0202 Sequential Media
+VT 0300 Output Vendor Specific
+VT 0301 Generic Display
+VT 0302 Sequential Media
+VT 0400 External Vendor Specific
+VT 0401 Composite Video
+VT 0402 S-Video
+VT 0403 Component Video
diff --git a/drivers/staging/usbip/vhci.h b/drivers/staging/usbip/vhci.h
index d3f1e5f..d5bc8e7 100644
--- a/drivers/staging/usbip/vhci.h
+++ b/drivers/staging/usbip/vhci.h
@@ -17,9 +17,14 @@
* USA.
*/
-#include <linux/platform_device.h>
+#include <linux/device.h>
+#include <linux/list.h>
+#include <linux/spinlock.h>
+#include <linux/sysfs.h>
+#include <linux/types.h>
+#include <linux/usb.h>
#include <linux/usb/hcd.h>
-
+#include <linux/wait.h>
struct vhci_device {
struct usb_device *udev;
@@ -33,12 +38,11 @@
/* speed of a remote device */
enum usb_device_speed speed;
- /* vhci root-hub port to which this device is attached */
+ /* vhci root-hub port to which this device is attached */
__u32 rhport;
struct usbip_device ud;
-
/* lock for the below link lists */
spinlock_t priv_lock;
@@ -54,7 +58,6 @@
wait_queue_head_t waitq_tx;
};
-
/* urb->hcpriv, use container_of() */
struct vhci_priv {
unsigned long seqnum;
@@ -64,7 +67,6 @@
struct urb *urb;
};
-
struct vhci_unlink {
/* seqnum of this request */
unsigned long seqnum;
@@ -85,12 +87,12 @@
/* for usb_bus.hcpriv */
struct vhci_hcd {
- spinlock_t lock;
+ spinlock_t lock;
- u32 port_status[VHCI_NPORTS];
+ u32 port_status[VHCI_NPORTS];
- unsigned resuming:1;
- unsigned long re_timeout;
+ unsigned resuming:1;
+ unsigned long re_timeout;
atomic_t seqnum;
@@ -102,25 +104,21 @@
struct vhci_device vdev[VHCI_NPORTS];
};
-
extern struct vhci_hcd *the_controller;
extern struct attribute_group dev_attr_group;
-
-
-/*-------------------------------------------------------------------------*/
-/* prototype declaration */
+#define hardware (&the_controller->pdev.dev)
/* vhci_hcd.c */
void rh_port_connect(int rhport, enum usb_device_speed speed);
void rh_port_disconnect(int rhport);
+
+/* vhci_rx.c */
+struct urb *pickup_urb_and_free_priv(struct vhci_device *vdev, __u32 seqnum);
int vhci_rx_loop(void *data);
+
+/* vhci_tx.c */
int vhci_tx_loop(void *data);
-struct urb *pickup_urb_and_free_priv(struct vhci_device *vdev,
- __u32 seqnum);
-
-#define hardware (&the_controller->pdev.dev)
-
static inline struct vhci_device *port_to_vdev(__u32 port)
{
return &the_controller->vdev[port];
diff --git a/drivers/staging/usbip/vhci_hcd.c b/drivers/staging/usbip/vhci_hcd.c
index 4f4f133..a76e8fa 100644
--- a/drivers/staging/usbip/vhci_hcd.c
+++ b/drivers/staging/usbip/vhci_hcd.c
@@ -17,21 +17,18 @@
* USA.
*/
-#include <linux/slab.h>
+#include <linux/init.h>
+#include <linux/kernel.h>
#include <linux/kthread.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
#include "usbip_common.h"
#include "vhci.h"
-#define DRIVER_VERSION "1.0"
#define DRIVER_AUTHOR "Takahiro Hirofuchi"
-#define DRIVER_DESC "Virtual Host Controller Interface Driver for USB/IP"
-#define DRIVER_LICENCE "GPL"
-MODULE_AUTHOR(DRIVER_AUTHOR);
-MODULE_DESCRIPTION(DRIVER_DESC);
-MODULE_LICENSE(DRIVER_LICENCE);
-
-
+#define DRIVER_DESC "USB/IP 'Virtual' Host Controller (VHCI) Driver"
/*
* TODO
@@ -43,15 +40,13 @@
* - clean up everything
*/
-
/* See usb gadget dummy hcd */
-
static int vhci_hub_status(struct usb_hcd *hcd, char *buff);
static int vhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
- u16 wIndex, char *buff, u16 wLength);
+ u16 wIndex, char *buff, u16 wLength);
static int vhci_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
- gfp_t mem_flags);
+ gfp_t mem_flags);
static int vhci_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status);
static int vhci_start(struct usb_hcd *vhci_hcd);
static void vhci_stop(struct usb_hcd *hcd);
@@ -62,57 +57,53 @@
struct vhci_hcd *the_controller;
-static const char *bit_desc[] = {
+static const char * const bit_desc[] = {
"CONNECTION", /*0*/
"ENABLE", /*1*/
"SUSPEND", /*2*/
"OVER_CURRENT", /*3*/
"RESET", /*4*/
- "R5", /*5*/
- "R6", /*6*/
- "R7", /*7*/
+ "R5", /*5*/
+ "R6", /*6*/
+ "R7", /*7*/
"POWER", /*8*/
"LOWSPEED", /*9*/
"HIGHSPEED", /*10*/
"PORT_TEST", /*11*/
"INDICATOR", /*12*/
- "R13", /*13*/
- "R14", /*14*/
- "R15", /*15*/
+ "R13", /*13*/
+ "R14", /*14*/
+ "R15", /*15*/
"C_CONNECTION", /*16*/
"C_ENABLE", /*17*/
"C_SUSPEND", /*18*/
"C_OVER_CURRENT", /*19*/
"C_RESET", /*20*/
- "R21", /*21*/
- "R22", /*22*/
- "R23", /*23*/
- "R24", /*24*/
- "R25", /*25*/
- "R26", /*26*/
- "R27", /*27*/
- "R28", /*28*/
- "R29", /*29*/
- "R30", /*30*/
- "R31", /*31*/
+ "R21", /*21*/
+ "R22", /*22*/
+ "R23", /*23*/
+ "R24", /*24*/
+ "R25", /*25*/
+ "R26", /*26*/
+ "R27", /*27*/
+ "R28", /*28*/
+ "R29", /*29*/
+ "R30", /*30*/
+ "R31", /*31*/
};
-
static void dump_port_status(u32 status)
{
int i = 0;
- printk(KERN_DEBUG "status %08x:", status);
+ pr_debug("status %08x:", status);
for (i = 0; i < 32; i++) {
if (status & (1 << i))
- printk(" %s", bit_desc[i]);
+ pr_debug(" %s", bit_desc[i]);
}
-
- printk("\n");
+ pr_debug("\n");
}
-
-
void rh_port_connect(int rhport, enum usb_device_speed speed)
{
unsigned long flags;
@@ -156,26 +147,20 @@
the_controller->port_status[rhport] |=
(1 << USB_PORT_FEAT_C_CONNECTION);
-
/* not yet complete the disconnection
* spin_lock(&vdev->ud.lock);
* vdev->ud.status = VHC_ST_DISCONNECT;
* spin_unlock(&vdev->ud.lock); */
spin_unlock_irqrestore(&the_controller->lock, flags);
-
usb_hcd_poll_rh_status(vhci_to_hcd(the_controller));
}
-
-
-/*----------------------------------------------------------------------*/
-
-#define PORT_C_MASK \
- ((USB_PORT_STAT_C_CONNECTION \
- | USB_PORT_STAT_C_ENABLE \
- | USB_PORT_STAT_C_SUSPEND \
- | USB_PORT_STAT_C_OVERCURRENT \
+#define PORT_C_MASK \
+ ((USB_PORT_STAT_C_CONNECTION \
+ | USB_PORT_STAT_C_ENABLE \
+ | USB_PORT_STAT_C_SUSPEND \
+ | USB_PORT_STAT_C_OVERCURRENT \
| USB_PORT_STAT_C_RESET) << 16)
/*
@@ -210,7 +195,6 @@
int rhport;
int changed = 0;
-
*event_bits = 0;
vhci = hcd_to_vhci(hcd);
@@ -232,7 +216,7 @@
}
}
- usbip_uinfo("changed %d\n", changed);
+ pr_info("changed %d\n", changed);
if (hcd->state == HC_STATE_SUSPENDED)
usb_hcd_resume_root_hub(hcd);
@@ -278,10 +262,9 @@
* wIndex shows the port number and begins from 1.
*/
usbip_dbg_vhci_rh("typeReq %x wValue %x wIndex %x\n", typeReq, wValue,
- wIndex);
+ wIndex);
if (wIndex > VHCI_NPORTS)
- printk(KERN_ERR "%s: invalid port number %d\n", __func__,
- wIndex);
+ pr_err("invalid port number %d\n", wIndex);
rhport = ((__u8)(wIndex & 0x00ff)) - 1;
dum = hcd_to_vhci(hcd);
@@ -311,7 +294,7 @@
break;
case USB_PORT_FEAT_POWER:
usbip_dbg_vhci_rh(" ClearPortFeature: "
- "USB_PORT_FEAT_POWER\n");
+ "USB_PORT_FEAT_POWER\n");
dum->port_status[rhport] = 0;
/* dum->address = 0; */
/* dum->hdev = 0; */
@@ -319,23 +302,24 @@
break;
case USB_PORT_FEAT_C_RESET:
usbip_dbg_vhci_rh(" ClearPortFeature: "
- "USB_PORT_FEAT_C_RESET\n");
+ "USB_PORT_FEAT_C_RESET\n");
switch (dum->vdev[rhport].speed) {
case USB_SPEED_HIGH:
dum->port_status[rhport] |=
- USB_PORT_STAT_HIGH_SPEED;
+ USB_PORT_STAT_HIGH_SPEED;
break;
case USB_SPEED_LOW:
dum->port_status[rhport] |=
- USB_PORT_STAT_LOW_SPEED;
+ USB_PORT_STAT_LOW_SPEED;
break;
default:
break;
}
default:
usbip_dbg_vhci_rh(" ClearPortFeature: default %x\n",
- wValue);
+ wValue);
dum->port_status[rhport] &= ~(1 << wValue);
+ break;
}
break;
case GetHubDescriptor:
@@ -349,8 +333,7 @@
case GetPortStatus:
usbip_dbg_vhci_rh(" GetPortStatus port %x\n", wIndex);
if (wIndex > VHCI_NPORTS || wIndex < 1) {
- printk(KERN_ERR "%s: invalid port number %d\n",
- __func__, wIndex);
+ pr_err("invalid port number %d\n", wIndex);
retval = -EPIPE;
}
@@ -360,7 +343,6 @@
* complete it!!
* */
if (dum->resuming && time_after(jiffies, dum->re_timeout)) {
- printk(KERN_ERR "%s: not yet\n", __func__);
dum->port_status[rhport] |=
(1 << USB_PORT_FEAT_C_SUSPEND);
dum->port_status[rhport] &=
@@ -375,39 +357,38 @@
}
if ((dum->port_status[rhport] & (1 << USB_PORT_FEAT_RESET)) !=
- 0 && time_after(jiffies, dum->re_timeout)) {
+ 0 && time_after(jiffies, dum->re_timeout)) {
dum->port_status[rhport] |=
- (1 << USB_PORT_FEAT_C_RESET);
+ (1 << USB_PORT_FEAT_C_RESET);
dum->port_status[rhport] &=
- ~(1 << USB_PORT_FEAT_RESET);
+ ~(1 << USB_PORT_FEAT_RESET);
dum->re_timeout = 0;
if (dum->vdev[rhport].ud.status ==
- VDEV_ST_NOTASSIGNED) {
+ VDEV_ST_NOTASSIGNED) {
usbip_dbg_vhci_rh(" enable rhport %d "
- "(status %u)\n",
- rhport,
- dum->vdev[rhport].ud.status);
+ "(status %u)\n",
+ rhport,
+ dum->vdev[rhport].ud.status);
dum->port_status[rhport] |=
- USB_PORT_STAT_ENABLE;
+ USB_PORT_STAT_ENABLE;
}
#if 0
if (dum->driver) {
-
dum->port_status[rhport] |=
- USB_PORT_STAT_ENABLE;
+ USB_PORT_STAT_ENABLE;
/* give it the best speed we agree on */
dum->gadget.speed = dum->driver->speed;
dum->gadget.ep0->maxpacket = 64;
switch (dum->gadget.speed) {
case USB_SPEED_HIGH:
dum->port_status[rhport] |=
- USB_PORT_STAT_HIGH_SPEED;
+ USB_PORT_STAT_HIGH_SPEED;
break;
case USB_SPEED_LOW:
dum->gadget.ep0->maxpacket = 8;
dum->port_status[rhport] |=
- USB_PORT_STAT_LOW_SPEED;
+ USB_PORT_STAT_LOW_SPEED;
break;
default:
dum->gadget.speed = USB_SPEED_FULL;
@@ -415,14 +396,12 @@
}
}
#endif
-
}
((u16 *) buf)[0] = cpu_to_le16(dum->port_status[rhport]);
- ((u16 *) buf)[1] =
- cpu_to_le16(dum->port_status[rhport] >> 16);
+ ((u16 *) buf)[1] = cpu_to_le16(dum->port_status[rhport] >> 16);
usbip_dbg_vhci_rh(" GetPortStatus bye %x %x\n", ((u16 *)buf)[0],
- ((u16 *)buf)[1]);
+ ((u16 *)buf)[1]);
break;
case SetHubFeature:
usbip_dbg_vhci_rh(" SetHubFeature\n");
@@ -432,11 +411,10 @@
switch (wValue) {
case USB_PORT_FEAT_SUSPEND:
usbip_dbg_vhci_rh(" SetPortFeature: "
- "USB_PORT_FEAT_SUSPEND\n");
- printk(KERN_ERR "%s: not yet\n", __func__);
+ "USB_PORT_FEAT_SUSPEND\n");
#if 0
dum->port_status[rhport] |=
- (1 << USB_PORT_FEAT_SUSPEND);
+ (1 << USB_PORT_FEAT_SUSPEND);
if (dum->driver->suspend) {
spin_unlock(&dum->lock);
dum->driver->suspend(&dum->gadget);
@@ -446,13 +424,13 @@
break;
case USB_PORT_FEAT_RESET:
usbip_dbg_vhci_rh(" SetPortFeature: "
- "USB_PORT_FEAT_RESET\n");
+ "USB_PORT_FEAT_RESET\n");
/* if it's already running, disconnect first */
if (dum->port_status[rhport] & USB_PORT_STAT_ENABLE) {
dum->port_status[rhport] &=
- ~(USB_PORT_STAT_ENABLE |
- USB_PORT_STAT_LOW_SPEED |
- USB_PORT_STAT_HIGH_SPEED);
+ ~(USB_PORT_STAT_ENABLE |
+ USB_PORT_STAT_LOW_SPEED |
+ USB_PORT_STAT_HIGH_SPEED);
#if 0
if (dum->driver) {
dev_dbg(hardware, "disconnect\n");
@@ -468,13 +446,14 @@
/* FALLTHROUGH */
default:
usbip_dbg_vhci_rh(" SetPortFeature: default %d\n",
- wValue);
+ wValue);
dum->port_status[rhport] |= (1 << wValue);
+ break;
}
break;
default:
- printk(KERN_ERR "%s: default: no such request\n", __func__);
+ pr_err("default: no such request\n");
/* dev_dbg (hardware,
* "hub control req%04x v%04x i%04x l%d\n",
* typeReq, wValue, wIndex, wLength); */
@@ -484,7 +463,7 @@
}
if (usbip_dbg_flag_vhci_rh) {
- printk(KERN_DEBUG "port %d\n", rhport);
+ pr_debug("port %d\n", rhport);
dump_port_status(prev_port_status[rhport]);
dump_port_status(dum->port_status[rhport]);
}
@@ -495,10 +474,6 @@
return retval;
}
-
-
-/*----------------------------------------------------------------------*/
-
static struct vhci_device *get_vdev(struct usb_device *udev)
{
int i;
@@ -520,7 +495,7 @@
unsigned long flag;
if (!vdev) {
- err("could not get virtual device");
+ pr_err("could not get virtual device");
/* BUG(); */
return;
}
@@ -538,14 +513,13 @@
priv->seqnum = atomic_inc_return(&the_controller->seqnum);
if (priv->seqnum == 0xffff)
- usbip_uinfo("seqnum max\n");
+ dev_info(&urb->dev->dev, "seqnum max\n");
priv->vdev = vdev;
priv->urb = urb;
urb->hcpriv = (void *) priv;
-
list_add_tail(&priv->list, &vdev->priv_tx);
wake_up(&vdev->waitq_tx);
@@ -561,7 +535,7 @@
struct vhci_device *vdev;
usbip_dbg_vhci_hc("enter, usb_hcd %p urb %p mem_flags %d\n",
- hcd, urb, mem_flags);
+ hcd, urb, mem_flags);
/* patch to usb_sg_init() is in 2.5.60 */
BUG_ON(!urb->transfer_buffer && urb->transfer_buffer_length);
@@ -578,8 +552,9 @@
/* refuse enqueue for dead connection */
spin_lock(&vdev->ud.lock);
- if (vdev->ud.status == VDEV_ST_NULL || vdev->ud.status == VDEV_ST_ERROR) {
- usbip_uerr("enqueue for inactive port %d\n", vdev->rhport);
+ if (vdev->ud.status == VDEV_ST_NULL ||
+ vdev->ud.status == VDEV_ST_ERROR) {
+ dev_err(dev, "enqueue for inactive port %d\n", vdev->rhport);
spin_unlock(&vdev->ud.lock);
spin_unlock_irqrestore(&the_controller->lock, flags);
return -ENODEV;
@@ -599,11 +574,10 @@
* 2. Set_Address request to DevAddr(0) EndPoint(0)
*
*/
-
if (usb_pipedevice(urb->pipe) == 0) {
__u8 type = usb_pipetype(urb->pipe);
struct usb_ctrlrequest *ctrlreq =
- (struct usb_ctrlrequest *) urb->setup_packet;
+ (struct usb_ctrlrequest *) urb->setup_packet;
if (type != PIPE_CONTROL || !ctrlreq) {
dev_err(dev, "invalid request to devnum 0\n");
@@ -636,8 +610,8 @@
case USB_REQ_GET_DESCRIPTOR:
if (ctrlreq->wValue == (USB_DT_DEVICE << 8))
usbip_dbg_vhci_hc("Not yet?: "
- "Get_Descriptor to device 0 "
- "(get max pipe size)\n");
+ "Get_Descriptor to device 0 "
+ "(get max pipe size)\n");
if (vdev->udev)
usb_put_dev(vdev->udev);
@@ -657,7 +631,6 @@
out:
vhci_tx_urb(urb);
-
spin_unlock_irqrestore(&the_controller->lock, flags);
return 0;
@@ -724,8 +697,7 @@
struct vhci_priv *priv;
struct vhci_device *vdev;
- usbip_uinfo("vhci_hcd: dequeue a urb %p\n", urb);
-
+ pr_info("dequeue a urb %p\n", urb);
spin_lock_irqsave(&the_controller->lock, flags);
@@ -755,8 +727,7 @@
spin_lock_irqsave(&vdev->priv_lock, flags2);
- usbip_uinfo("vhci_hcd: device %p seems to be disconnected\n",
- vdev);
+ pr_info("device %p seems to be disconnected\n", vdev);
list_del(&priv->list);
kfree(priv);
urb->hcpriv = NULL;
@@ -768,14 +739,13 @@
* vhci_rx will receive RET_UNLINK and give back the URB.
* Otherwise, we give back it here.
*/
- usbip_uinfo("vhci_hcd: vhci_urb_dequeue() gives back urb %p\n",
- urb);
+ pr_info("gives back urb %p\n", urb);
usb_hcd_unlink_urb_from_ep(hcd, urb);
spin_unlock_irqrestore(&the_controller->lock, flags);
usb_hcd_giveback_urb(vhci_to_hcd(the_controller), urb,
- urb->status);
+ urb->status);
spin_lock_irqsave(&the_controller->lock, flags);
} else {
@@ -788,7 +758,7 @@
/* setup CMD_UNLINK pdu */
unlink = kzalloc(sizeof(struct vhci_unlink), GFP_ATOMIC);
if (!unlink) {
- usbip_uerr("malloc vhci_unlink\n");
+ pr_err("malloc vhci_unlink\n");
spin_unlock_irqrestore(&vdev->priv_lock, flags2);
spin_unlock_irqrestore(&the_controller->lock, flags);
usbip_event_add(&vdev->ud, VDEV_EVENT_ERROR_MALLOC);
@@ -797,12 +767,11 @@
unlink->seqnum = atomic_inc_return(&the_controller->seqnum);
if (unlink->seqnum == 0xffff)
- usbip_uinfo("seqnum max\n");
+ pr_info("seqnum max\n");
unlink->unlink_seqnum = priv->seqnum;
- usbip_uinfo("vhci_hcd: device %p seems to be still connected\n",
- vdev);
+ pr_info("device %p seems to be still connected\n", vdev);
/* send cmd_unlink and try to cancel the pending URB in the
* peer */
@@ -825,7 +794,7 @@
spin_lock(&vdev->priv_lock);
list_for_each_entry_safe(unlink, tmp, &vdev->unlink_tx, list) {
- usbip_uinfo("unlink cleanup tx %lu\n", unlink->unlink_seqnum);
+ pr_info("unlink cleanup tx %lu\n", unlink->unlink_seqnum);
list_del(&unlink->list);
kfree(unlink);
}
@@ -834,12 +803,12 @@
struct urb *urb;
/* give back URB of unanswered unlink request */
- usbip_uinfo("unlink cleanup rx %lu\n", unlink->unlink_seqnum);
+ pr_info("unlink cleanup rx %lu\n", unlink->unlink_seqnum);
urb = pickup_urb_and_free_priv(vdev, unlink->unlink_seqnum);
if (!urb) {
- usbip_uinfo("the urb (seqnum %lu) was already given back\n",
- unlink->unlink_seqnum);
+ pr_info("the urb (seqnum %lu) was already given back\n",
+ unlink->unlink_seqnum);
list_del(&unlink->list);
kfree(unlink);
continue;
@@ -851,7 +820,8 @@
usb_hcd_unlink_urb_from_ep(vhci_to_hcd(the_controller), urb);
spin_unlock(&the_controller->lock);
- usb_hcd_giveback_urb(vhci_to_hcd(the_controller), urb, urb->status);
+ usb_hcd_giveback_urb(vhci_to_hcd(the_controller), urb,
+ urb->status);
list_del(&unlink->list);
kfree(unlink);
@@ -871,7 +841,7 @@
/* need this? see stub_dev.c */
if (ud->tcp_socket) {
- usbip_udbg("shutdown tcp_socket %p\n", ud->tcp_socket);
+ pr_debug("shutdown tcp_socket %p\n", ud->tcp_socket);
kernel_sock_shutdown(ud->tcp_socket, SHUT_RDWR);
}
@@ -881,14 +851,14 @@
if (vdev->ud.tcp_tx)
kthread_stop(vdev->ud.tcp_tx);
- usbip_uinfo("stop threads\n");
+ pr_info("stop threads\n");
/* active connection is closed */
if (vdev->ud.tcp_socket != NULL) {
sock_release(vdev->ud.tcp_socket);
vdev->ud.tcp_socket = NULL;
}
- usbip_uinfo("release socket\n");
+ pr_info("release socket\n");
vhci_device_unlink_cleanup(vdev);
@@ -914,7 +884,7 @@
*/
rh_port_disconnect(vdev->rhport);
- usbip_uinfo("disconnect device\n");
+ pr_info("disconnect device\n");
}
@@ -932,7 +902,6 @@
vdev->udev = NULL;
ud->tcp_socket = NULL;
-
ud->status = VDEV_ST_NULL;
spin_unlock(&ud->lock);
@@ -941,9 +910,7 @@
static void vhci_device_unusable(struct usbip_device *ud)
{
spin_lock(&ud->lock);
-
ud->status = VDEV_ST_ERROR;
-
spin_unlock(&ud->lock);
}
@@ -972,9 +939,6 @@
usbip_start_eh(&vdev->ud);
}
-
-/*----------------------------------------------------------------------*/
-
static int vhci_start(struct usb_hcd *hcd)
{
struct vhci_hcd *vhci = hcd_to_vhci(hcd);
@@ -983,7 +947,6 @@
usbip_dbg_vhci_hc("enter vhci_start\n");
-
/* initialize private data of usb_hcd */
for (rhport = 0; rhport < VHCI_NPORTS; rhport++) {
@@ -995,17 +958,14 @@
atomic_set(&vhci->seqnum, 0);
spin_lock_init(&vhci->lock);
-
-
hcd->power_budget = 0; /* no limit */
hcd->state = HC_STATE_RUNNING;
hcd->uses_new_polling = 1;
-
/* vhci_hcd is now ready to be controlled through sysfs */
err = sysfs_create_group(&vhci_dev(vhci)->kobj, &dev_attr_group);
if (err) {
- usbip_uerr("create sysfs files\n");
+ pr_err("create sysfs files\n");
return err;
}
@@ -1019,7 +979,6 @@
usbip_dbg_vhci_hc("stop VHCI controller\n");
-
/* 1. remove the userland interface of vhci_hcd */
sysfs_remove_group(&vhci_dev(vhci)->kobj, &dev_attr_group);
@@ -1030,20 +989,14 @@
usbip_event_add(&vdev->ud, VDEV_EVENT_REMOVED);
usbip_stop_eh(&vdev->ud);
}
-
-
- usbip_uinfo("vhci_stop done\n");
}
-/*----------------------------------------------------------------------*/
-
static int vhci_get_frame_number(struct usb_hcd *hcd)
{
- usbip_uerr("Not yet implemented\n");
+ pr_err("Not yet implemented\n");
return 0;
}
-
#ifdef CONFIG_PM
/* FIXME: suspend/resume */
@@ -1091,8 +1044,6 @@
#define vhci_bus_resume NULL
#endif
-
-
static struct hc_driver vhci_hc_driver = {
.description = driver_name,
.product_desc = driver_desc,
@@ -1119,8 +1070,6 @@
struct usb_hcd *hcd;
int ret;
- usbip_uinfo("proving...\n");
-
usbip_dbg_vhci_hc("name %s id %d\n", pdev->name, pdev->id);
/* will be removed */
@@ -1135,7 +1084,7 @@
*/
hcd = usb_create_hcd(&vhci_hc_driver, &pdev->dev, dev_name(&pdev->dev));
if (!hcd) {
- usbip_uerr("create hcd failed\n");
+ pr_err("create hcd failed\n");
return -ENOMEM;
}
hcd->has_tt = 1;
@@ -1149,18 +1098,16 @@
*/
ret = usb_add_hcd(hcd, 0, 0);
if (ret != 0) {
- usbip_uerr("usb_add_hcd failed %d\n", ret);
+ pr_err("usb_add_hcd failed %d\n", ret);
usb_put_hcd(hcd);
the_controller = NULL;
return ret;
}
-
usbip_dbg_vhci_hc("bye\n");
return 0;
}
-
static int vhci_hcd_remove(struct platform_device *pdev)
{
struct usb_hcd *hcd;
@@ -1178,12 +1125,9 @@
usb_put_hcd(hcd);
the_controller = NULL;
-
return 0;
}
-
-
#ifdef CONFIG_PM
/* what should happen for USB/IP under suspend/resume? */
@@ -1194,25 +1138,23 @@
int connected = 0;
int ret = 0;
- dev_dbg(&pdev->dev, "%s\n", __func__);
-
hcd = platform_get_drvdata(pdev);
spin_lock(&the_controller->lock);
for (rhport = 0; rhport < VHCI_NPORTS; rhport++)
if (the_controller->port_status[rhport] &
- USB_PORT_STAT_CONNECTION)
+ USB_PORT_STAT_CONNECTION)
connected += 1;
spin_unlock(&the_controller->lock);
if (connected > 0) {
- usbip_uinfo("We have %d active connection%s. Do not suspend.\n",
- connected, (connected == 1 ? "" : "s"));
+ dev_info(&pdev->dev, "We have %d active connection%s. Do not "
+ "suspend.\n", connected, (connected == 1 ? "" : "s"));
ret = -EBUSY;
} else {
- usbip_uinfo("suspend vhci_hcd");
+ dev_info(&pdev->dev, "suspend vhci_hcd");
clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
}
@@ -1239,7 +1181,6 @@
#endif
-
static struct platform_driver vhci_driver = {
.probe = vhci_hcd_probe,
.remove = __devexit_p(vhci_hcd_remove),
@@ -1251,8 +1192,6 @@
},
};
-/*----------------------------------------------------------------------*/
-
/*
* The VHCI 'device' is 'virtual'; not a real plug&play hardware.
* We need to add this virtual device as a platform device arbitrarily:
@@ -1277,13 +1216,9 @@
{
int ret;
- usbip_dbg_vhci_hc("enter\n");
if (usb_disabled())
return -ENODEV;
- printk(KERN_INFO KBUILD_MODNAME ": %s, %s\n", driver_name,
- DRIVER_VERSION);
-
ret = platform_driver_register(&vhci_driver);
if (ret < 0)
goto err_driver_register;
@@ -1292,26 +1227,25 @@
if (ret < 0)
goto err_platform_device_register;
- usbip_dbg_vhci_hc("bye\n");
+ pr_info(DRIVER_DESC " v" USBIP_VERSION "\n");
return ret;
- /* error occurred */
err_platform_device_register:
platform_driver_unregister(&vhci_driver);
-
err_driver_register:
- usbip_dbg_vhci_hc("bye\n");
return ret;
}
-module_init(vhci_init);
static void __exit vhci_cleanup(void)
{
- usbip_dbg_vhci_hc("enter\n");
-
platform_device_unregister(&the_pdev);
platform_driver_unregister(&vhci_driver);
-
- usbip_dbg_vhci_hc("bye\n");
}
+
+module_init(vhci_init);
module_exit(vhci_cleanup);
+
+MODULE_AUTHOR(DRIVER_AUTHOR);
+MODULE_DESCRIPTION(DRIVER_DESC);
+MODULE_LICENSE("GPL");
+MODULE_VERSION(USBIP_VERSION);
diff --git a/drivers/staging/usbip/vhci_rx.c b/drivers/staging/usbip/vhci_rx.c
index 2ffc96a..e42ce9d 100644
--- a/drivers/staging/usbip/vhci_rx.c
+++ b/drivers/staging/usbip/vhci_rx.c
@@ -17,16 +17,14 @@
* USA.
*/
-#include <linux/slab.h>
#include <linux/kthread.h>
+#include <linux/slab.h>
#include "usbip_common.h"
#include "vhci.h"
-
/* get URB from transmitted urb queue. caller must hold vdev->priv_lock */
-struct urb *pickup_urb_and_free_priv(struct vhci_device *vdev,
- __u32 seqnum)
+struct urb *pickup_urb_and_free_priv(struct vhci_device *vdev, __u32 seqnum)
{
struct vhci_priv *priv, *tmp;
struct urb *urb = NULL;
@@ -38,12 +36,12 @@
status = urb->status;
usbip_dbg_vhci_rx("find urb %p vurb %p seqnum %u\n",
- urb, priv, seqnum);
+ urb, priv, seqnum);
/* TODO: fix logic here to improve indent situtation */
if (status != -EINPROGRESS) {
if (status == -ENOENT ||
- status == -ECONNRESET)
+ status == -ECONNRESET)
dev_info(&urb->dev->dev,
"urb %p was unlinked "
"%ssynchronuously.\n", urb,
@@ -66,36 +64,30 @@
}
static void vhci_recv_ret_submit(struct vhci_device *vdev,
- struct usbip_header *pdu)
+ struct usbip_header *pdu)
{
struct usbip_device *ud = &vdev->ud;
struct urb *urb;
spin_lock(&vdev->priv_lock);
-
urb = pickup_urb_and_free_priv(vdev, pdu->base.seqnum);
-
spin_unlock(&vdev->priv_lock);
if (!urb) {
- usbip_uerr("cannot find a urb of seqnum %u\n",
- pdu->base.seqnum);
- usbip_uinfo("max seqnum %d\n",
- atomic_read(&the_controller->seqnum));
+ pr_err("cannot find a urb of seqnum %u\n", pdu->base.seqnum);
+ pr_info("max seqnum %d\n",
+ atomic_read(&the_controller->seqnum));
usbip_event_add(ud, VDEV_EVENT_ERROR_TCP);
return;
}
-
/* unpack the pdu to a urb */
usbip_pack_pdu(pdu, urb, USBIP_RET_SUBMIT, 0);
-
/* recv transfer buffer */
if (usbip_recv_xbuff(ud, urb) < 0)
return;
-
/* recv iso_packet_descriptor */
if (usbip_recv_iso(ud, urb) < 0)
return;
@@ -107,7 +99,6 @@
if (usbip_dbg_flag_vhci_rx)
usbip_dump_urb(urb);
-
usbip_dbg_vhci_rx("now giveback urb %p\n", urb);
spin_lock(&the_controller->lock);
@@ -116,25 +107,23 @@
usb_hcd_giveback_urb(vhci_to_hcd(the_controller), urb, urb->status);
-
usbip_dbg_vhci_rx("Leave\n");
return;
}
-
static struct vhci_unlink *dequeue_pending_unlink(struct vhci_device *vdev,
- struct usbip_header *pdu)
+ struct usbip_header *pdu)
{
struct vhci_unlink *unlink, *tmp;
spin_lock(&vdev->priv_lock);
list_for_each_entry_safe(unlink, tmp, &vdev->unlink_rx, list) {
- usbip_uinfo("unlink->seqnum %lu\n", unlink->seqnum);
+ pr_info("unlink->seqnum %lu\n", unlink->seqnum);
if (unlink->seqnum == pdu->base.seqnum) {
usbip_dbg_vhci_rx("found pending unlink, %lu\n",
- unlink->seqnum);
+ unlink->seqnum);
list_del(&unlink->list);
spin_unlock(&vdev->priv_lock);
@@ -147,9 +136,8 @@
return NULL;
}
-
static void vhci_recv_ret_unlink(struct vhci_device *vdev,
- struct usbip_header *pdu)
+ struct usbip_header *pdu)
{
struct vhci_unlink *unlink;
struct urb *urb;
@@ -158,15 +146,13 @@
unlink = dequeue_pending_unlink(vdev, pdu);
if (!unlink) {
- usbip_uinfo("cannot find the pending unlink %u\n",
- pdu->base.seqnum);
+ pr_info("cannot find the pending unlink %u\n",
+ pdu->base.seqnum);
return;
}
spin_lock(&vdev->priv_lock);
-
urb = pickup_urb_and_free_priv(vdev, unlink->unlink_seqnum);
-
spin_unlock(&vdev->priv_lock);
if (!urb) {
@@ -175,21 +161,21 @@
* already received the result of its submit result and gave
* back the URB.
*/
- usbip_uinfo("the urb (seqnum %d) was already given backed\n",
- pdu->base.seqnum);
+ pr_info("the urb (seqnum %d) was already given backed\n",
+ pdu->base.seqnum);
} else {
usbip_dbg_vhci_rx("now giveback urb %p\n", urb);
/* If unlink is succeed, status is -ECONNRESET */
urb->status = pdu->u.ret_unlink.status;
- usbip_uinfo("%d\n", urb->status);
+ pr_info("urb->status %d\n", urb->status);
spin_lock(&the_controller->lock);
usb_hcd_unlink_urb_from_ep(vhci_to_hcd(the_controller), urb);
spin_unlock(&the_controller->lock);
usb_hcd_giveback_urb(vhci_to_hcd(the_controller), urb,
- urb->status);
+ urb->status);
}
kfree(unlink);
@@ -202,9 +188,7 @@
int empty = 0;
spin_lock(&vdev->priv_lock);
-
empty = list_empty(&vdev->priv_rx);
-
spin_unlock(&vdev->priv_lock);
return empty;
@@ -217,7 +201,6 @@
struct usbip_header pdu;
struct vhci_device *vdev = container_of(ud, struct vhci_device, ud);
-
usbip_dbg_vhci_rx("Enter\n");
memset(&pdu, 0, sizeof(pdu));
@@ -226,26 +209,26 @@
ret = usbip_xmit(0, ud->tcp_socket, (char *) &pdu, sizeof(pdu), 0);
if (ret < 0) {
if (ret == -ECONNRESET)
- usbip_uinfo("connection reset by peer\n");
+ pr_info("connection reset by peer\n");
else if (ret == -EAGAIN) {
/* ignore if connection was idle */
if (vhci_priv_tx_empty(vdev))
return;
- usbip_uinfo("connection timed out with pending urbs\n");
+ pr_info("connection timed out with pending urbs\n");
} else if (ret != -ERESTARTSYS)
- usbip_uinfo("xmit failed %d\n", ret);
+ pr_info("xmit failed %d\n", ret);
usbip_event_add(ud, VDEV_EVENT_ERROR_TCP);
return;
}
if (ret == 0) {
- usbip_uinfo("connection closed");
+ pr_info("connection closed");
usbip_event_add(ud, VDEV_EVENT_DOWN);
return;
}
if (ret != sizeof(pdu)) {
- usbip_uerr("received pdu size is %d, should be %d\n",
- ret, (unsigned int)sizeof(pdu));
+ pr_err("received pdu size is %d, should be %d\n", ret,
+ (unsigned int)sizeof(pdu));
usbip_event_add(ud, VDEV_EVENT_ERROR_TCP);
return;
}
@@ -263,21 +246,18 @@
vhci_recv_ret_unlink(vdev, &pdu);
break;
default:
- /* NOTREACHED */
- usbip_uerr("unknown pdu %u\n", pdu.base.command);
+ /* NOT REACHED */
+ pr_err("unknown pdu %u\n", pdu.base.command);
usbip_dump_header(&pdu);
usbip_event_add(ud, VDEV_EVENT_ERROR_TCP);
+ break;
}
}
-
-/*-------------------------------------------------------------------------*/
-
int vhci_rx_loop(void *data)
{
struct usbip_device *ud = data;
-
while (!kthread_should_stop()) {
if (usbip_event_happened(ud))
break;
diff --git a/drivers/staging/usbip/vhci_sysfs.c b/drivers/staging/usbip/vhci_sysfs.c
index e2dadbd..d9736f9 100644
--- a/drivers/staging/usbip/vhci_sysfs.c
+++ b/drivers/staging/usbip/vhci_sysfs.c
@@ -17,12 +17,12 @@
* USA.
*/
+#include <linux/kthread.h>
+#include <linux/net.h>
+
#include "usbip_common.h"
#include "vhci.h"
-#include <linux/in.h>
-#include <linux/kthread.h>
-
/* TODO: refine locking ?*/
/* Sysfs entry to show port status */
@@ -53,20 +53,19 @@
struct vhci_device *vdev = port_to_vdev(i);
spin_lock(&vdev->ud.lock);
-
out += sprintf(out, "%03u %03u ", i, vdev->ud.status);
if (vdev->ud.status == VDEV_ST_USED) {
out += sprintf(out, "%03u %08x ",
- vdev->speed, vdev->devid);
+ vdev->speed, vdev->devid);
out += sprintf(out, "%16p ", vdev->ud.tcp_socket);
out += sprintf(out, "%s", dev_name(&vdev->udev->dev));
- } else
+ } else {
out += sprintf(out, "000 000 000 0000000000000000 0-0");
+ }
out += sprintf(out, "\n");
-
spin_unlock(&vdev->ud.lock);
}
@@ -90,7 +89,7 @@
spin_lock(&vdev->ud.lock);
if (vdev->ud.status == VDEV_ST_NULL) {
- usbip_uerr("not connected %d\n", vdev->ud.status);
+ pr_err("not connected %d\n", vdev->ud.status);
/* unlock */
spin_unlock(&vdev->ud.lock);
@@ -118,7 +117,7 @@
/* check rhport */
if (rhport >= VHCI_NPORTS) {
- usbip_uerr("invalid port %u\n", rhport);
+ dev_err(dev, "invalid port %u\n", rhport);
return -EINVAL;
}
@@ -127,6 +126,7 @@
return -EINVAL;
usbip_dbg_vhci_sysfs("Leave\n");
+
return count;
}
static DEVICE_ATTR(detach, S_IWUSR, NULL, store_detach);
@@ -136,7 +136,7 @@
{
/* check rhport */
if ((rhport < 0) || (rhport >= VHCI_NPORTS)) {
- usbip_uerr("port %u\n", rhport);
+ pr_err("port %u\n", rhport);
return -EINVAL;
}
@@ -148,7 +148,7 @@
case USB_SPEED_WIRELESS:
break;
default:
- usbip_uerr("speed %d\n", speed);
+ pr_err("speed %d\n", speed);
return -EINVAL;
}
@@ -183,8 +183,7 @@
sscanf(buf, "%u %u %u %u", &rhport, &sockfd, &devid, &speed);
usbip_dbg_vhci_sysfs("rhport(%u) sockfd(%u) devid(%u) speed(%u)\n",
- rhport, sockfd, devid, speed);
-
+ rhport, sockfd, devid, speed);
/* check received parameters */
if (valid_args(rhport, speed) < 0)
@@ -199,9 +198,7 @@
/* begin a lock */
spin_lock(&the_controller->lock);
-
vdev = port_to_vdev(rhport);
-
spin_lock(&vdev->ud.lock);
if (vdev->ud.status != VDEV_ST_NULL) {
@@ -209,12 +206,12 @@
spin_unlock(&vdev->ud.lock);
spin_unlock(&the_controller->lock);
- usbip_uerr("port %d already used\n", rhport);
+ dev_err(dev, "port %d already used\n", rhport);
return -EINVAL;
}
- usbip_uinfo("rhport(%u) sockfd(%d) devid(%u) speed(%u)\n",
- rhport, sockfd, devid, speed);
+ dev_info(dev, "rhport(%u) sockfd(%d) devid(%u) speed(%u)\n",
+ rhport, sockfd, devid, speed);
vdev->devid = devid;
vdev->speed = speed;
diff --git a/drivers/staging/usbip/vhci_tx.c b/drivers/staging/usbip/vhci_tx.c
index d9ab49d..9b437e7 100644
--- a/drivers/staging/usbip/vhci_tx.c
+++ b/drivers/staging/usbip/vhci_tx.c
@@ -17,29 +17,26 @@
* USA.
*/
-#include <linux/slab.h>
#include <linux/kthread.h>
+#include <linux/slab.h>
#include "usbip_common.h"
#include "vhci.h"
-
static void setup_cmd_submit_pdu(struct usbip_header *pdup, struct urb *urb)
{
struct vhci_priv *priv = ((struct vhci_priv *)urb->hcpriv);
struct vhci_device *vdev = priv->vdev;
usbip_dbg_vhci_tx("URB, local devnum %u, remote devid %u\n",
- usb_pipedevice(urb->pipe), vdev->devid);
+ usb_pipedevice(urb->pipe), vdev->devid);
- pdup->base.command = USBIP_CMD_SUBMIT;
- pdup->base.seqnum = priv->seqnum;
- pdup->base.devid = vdev->devid;
- if (usb_pipein(urb->pipe))
- pdup->base.direction = USBIP_DIR_IN;
- else
- pdup->base.direction = USBIP_DIR_OUT;
- pdup->base.ep = usb_pipeendpoint(urb->pipe);
+ pdup->base.command = USBIP_CMD_SUBMIT;
+ pdup->base.seqnum = priv->seqnum;
+ pdup->base.devid = vdev->devid;
+ pdup->base.direction = usb_pipein(urb->pipe) ?
+ USBIP_DIR_IN : USBIP_DIR_OUT;
+ pdup->base.ep = usb_pipeendpoint(urb->pipe);
usbip_pack_pdu(pdup, urb, USBIP_CMD_SUBMIT, 1);
@@ -65,8 +62,6 @@
return NULL;
}
-
-
static int vhci_send_cmd_submit(struct vhci_device *vdev)
{
struct vhci_priv *priv = NULL;
@@ -90,7 +85,6 @@
usbip_dbg_vhci_tx("setup txdata urb %p\n", urb);
-
/* 1. setup usbip_header */
setup_cmd_submit_pdu(&pdu_header, urb);
usbip_header_correct_endian(&pdu_header, 1);
@@ -124,8 +118,8 @@
ret = kernel_sendmsg(vdev->ud.tcp_socket, &msg, iov, 3, txsize);
if (ret != txsize) {
- usbip_uerr("sendmsg failed!, retval %d for %zd\n", ret,
- txsize);
+ pr_err("sendmsg failed!, ret=%d for %zd\n", ret,
+ txsize);
kfree(iso_buffer);
usbip_event_add(&vdev->ud, VDEV_EVENT_ERROR_TCP);
return -1;
@@ -140,9 +134,6 @@
return total_size;
}
-
-/*-------------------------------------------------------------------------*/
-
static struct vhci_unlink *dequeue_from_unlink_tx(struct vhci_device *vdev)
{
unsigned long flags;
@@ -182,7 +173,6 @@
usbip_dbg_vhci_tx("setup cmd unlink, %lu\n", unlink->seqnum);
-
/* 1. setup usbip_header */
pdu_header.base.command = USBIP_CMD_UNLINK;
pdu_header.base.seqnum = unlink->seqnum;
@@ -198,13 +188,12 @@
ret = kernel_sendmsg(vdev->ud.tcp_socket, &msg, iov, 1, txsize);
if (ret != txsize) {
- usbip_uerr("sendmsg failed!, retval %d for %zd\n", ret,
- txsize);
+ pr_err("sendmsg failed!, ret=%d for %zd\n", ret,
+ txsize);
usbip_event_add(&vdev->ud, VDEV_EVENT_ERROR_TCP);
return -1;
}
-
usbip_dbg_vhci_tx("send txdata\n");
total_size += txsize;
@@ -213,9 +202,6 @@
return total_size;
}
-
-/*-------------------------------------------------------------------------*/
-
int vhci_tx_loop(void *data)
{
struct usbip_device *ud = data;
@@ -229,9 +215,9 @@
break;
wait_event_interruptible(vdev->waitq_tx,
- (!list_empty(&vdev->priv_tx) ||
- !list_empty(&vdev->unlink_tx) ||
- kthread_should_stop()));
+ (!list_empty(&vdev->priv_tx) ||
+ !list_empty(&vdev->unlink_tx) ||
+ kthread_should_stop()));
usbip_dbg_vhci_tx("pending urbs ?, now wake up\n");
}
diff --git a/drivers/staging/vt6655/bssdb.c b/drivers/staging/vt6655/bssdb.c
index 57c1cc9..577599e 100644
--- a/drivers/staging/vt6655/bssdb.c
+++ b/drivers/staging/vt6655/bssdb.c
@@ -1289,7 +1289,7 @@
memset(pDevice->skb->cb, 0, sizeof(pDevice->skb->cb));
netif_rx(pDevice->skb);
pDevice->skb = dev_alloc_skb((int)pDevice->rx_buf_sz);
- };
+ }
#ifdef WPA_SUPPLICANT_DRIVER_WEXT_SUPPORT
// if(pDevice->bWPASuppWextEnabled == true)
{
@@ -1489,7 +1489,7 @@
}
}
}
- };
+ }
if ((pMgmt->eCurrMode == WMAC_MODE_IBSS_STA) ||
(pMgmt->eCurrMode == WMAC_MODE_ESS_AP)) {
@@ -1543,9 +1543,9 @@
}
}
}
- };
+ }
}
- };
+ }
return;
diff --git a/drivers/staging/vt6655/device.h b/drivers/staging/vt6655/device.h
index 2e7c2fd..780205c 100644
--- a/drivers/staging/vt6655/device.h
+++ b/drivers/staging/vt6655/device.h
@@ -396,7 +396,7 @@
struct pci_dev* pcid;
-#if CONFIG_PM
+#ifdef CONFIG_PM
u32 pci_state[16];
#endif
diff --git a/drivers/staging/vt6655/device_main.c b/drivers/staging/vt6655/device_main.c
index ad39c87..3d2a9ba 100644
--- a/drivers/staging/vt6655/device_main.c
+++ b/drivers/staging/vt6655/device_main.c
@@ -900,7 +900,7 @@
if(ii>20)
break;
}
- };
+ }
return true;
}
@@ -1446,7 +1446,7 @@
if (!device_alloc_frag_buf(pDevice, pDeF)) {
DBG_PRT(MSG_LEVEL_ERR,KERN_ERR "%s: can not alloc frag bufs\n",
pDevice->dev->name);
- };
+ }
}
pDevice->cbDFCB = CB_MAX_RX_FRAG;
pDevice->cbFreeDFCB = pDevice->cbDFCB;
@@ -2104,7 +2104,7 @@
dev_kfree_skb_irq(skb);
spin_unlock_irq(&pDevice->lock);
return 0;
- };
+ }
cbMPDULen = skb->len;
pbMPDU = skb->data;
@@ -2136,7 +2136,7 @@
if (pDevice->bStopTx0Pkt == true) {
dev_kfree_skb_irq(skb);
return false;
- };
+ }
if (AVAIL_TD(pDevice, TYPE_TXDMA0) <= 0) {
dev_kfree_skb_irq(skb);
@@ -2865,7 +2865,7 @@
pDevice->bBeaconSent = false;
if (pDevice->bEnablePSMode) {
PSbIsNextTBTTWakeUp((void *)pDevice);
- };
+ }
if ((pDevice->eOPMode == OP_MODE_AP) ||
(pDevice->eOPMode == OP_MODE_ADHOC)) {
@@ -2876,7 +2876,7 @@
if (pDevice->eOPMode == OP_MODE_ADHOC && pDevice->pMgmt->wCurrATIMWindow > 0) {
// todo adhoc PS mode
- };
+ }
}
@@ -2885,7 +2885,7 @@
if (pDevice->eOPMode == OP_MODE_ADHOC) {
pDevice->bIsBeaconBufReadySet = false;
pDevice->cbBeaconBufReadySetCnt = 0;
- };
+ }
if (pDevice->eOPMode == OP_MODE_AP) {
if(pMgmt->byDTIMCount > 0) {
diff --git a/drivers/staging/vt6655/dpc.c b/drivers/staging/vt6655/dpc.c
index 1513073..cf0deac 100644
--- a/drivers/staging/vt6655/dpc.c
+++ b/drivers/staging/vt6655/dpc.c
@@ -700,7 +700,7 @@
pDevice->pMgmt->bInTIMWake = false;
}
}
- };
+ }
// Now it only supports 802.11g Infrastructure Mode, and support rate must up to 54 Mbps
if (pDevice->bDiversityEnable && (FrameSize>50) &&
@@ -884,7 +884,7 @@
memset(pDevice->skb->cb, 0, sizeof(pDevice->skb->cb));
netif_rx(pDevice->skb);
pDevice->skb = dev_alloc_skb((int)pDevice->rx_buf_sz);
- };
+ }
return false;
@@ -1049,7 +1049,7 @@
);
DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO "dpc: send vMgrDeAuthenBeginSta 1\n");
return true;
- };
+ }
if (pMgmt->sNodeDBTable[iSANodeIndex].eNodeState < NODE_ASSOC) {
// send deassoc notification
// reason = (7) class 3 received from nonassoc sta
@@ -1061,7 +1061,7 @@
);
DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO "dpc: send vMgrDisassocBeginSta 2\n");
return true;
- };
+ }
if (pMgmt->sNodeDBTable[iSANodeIndex].bPSEnable) {
// delcare received ps-poll event
@@ -1486,7 +1486,7 @@
bRelayOnly = true;
}
}
- };
+ }
}
if (bRelayOnly || bRelayAndForward) {
diff --git a/drivers/staging/vt6655/ioctl.c b/drivers/staging/vt6655/ioctl.c
index 5624a41..8cf88c3 100644
--- a/drivers/staging/vt6655/ioctl.c
+++ b/drivers/staging/vt6655/ioctl.c
@@ -91,7 +91,7 @@
if (copy_from_user(&sScanCmd, pReq->data, sizeof(SCmdScan))) {
result = -EFAULT;
break;
- };
+ }
pItemSSID = (PWLAN_IE_SSID)sScanCmd.ssid;
if (pItemSSID->len != 0) {
@@ -128,7 +128,7 @@
if (copy_from_user(&sZoneTypeCmd, pReq->data, sizeof(SCmdZoneTypeSet))) {
result = -EFAULT;
break;
- };
+ }
if(sZoneTypeCmd.bWrite==true) {
//////write zonetype
@@ -167,7 +167,7 @@
if (copy_to_user(pReq->data, &sZoneTypeCmd, sizeof(SCmdZoneTypeSet))) {
result = -EFAULT;
break;
- };
+ }
}
break;
@@ -186,7 +186,7 @@
if (copy_from_user(&sJoinCmd, pReq->data, sizeof(SCmdBSSJoin))) {
result = -EFAULT;
break;
- };
+ }
pItemSSID = (PWLAN_IE_SSID)sJoinCmd.ssid;
memset(pMgmt->abyDesireSSID, 0, WLAN_IEHDR_LEN + WLAN_SSID_MAXLEN + 1);
@@ -234,7 +234,7 @@
if (copy_from_user(&sWEPCmd, pReq->data, sizeof(SCmdSetWEP))) {
result = -EFAULT;
break;
- };
+ }
if (sWEPCmd.bEnableWep != true) {
pDevice->bEncryptionEnable = false;
pDevice->eEncryptionStatus = Ndis802_11EncryptionDisabled;
@@ -300,7 +300,7 @@
if (copy_to_user(pReq->data, &sLinkStatus, sizeof(SCmdLinkStatus))) {
result = -EFAULT;
break;
- };
+ }
break;
@@ -312,12 +312,12 @@
if (!pBSS->bActive)
continue;
cbListCount++;
- };
+ }
sList.uItem = cbListCount;
if (copy_to_user(pReq->data, &sList, sizeof(SBSSIDList))) {
result = -EFAULT;
break;
- };
+ }
pReq->wResult = 0;
break;
@@ -325,7 +325,7 @@
if (copy_from_user(&sList, pReq->data, sizeof(SBSSIDList))) {
result = -EFAULT;
break;
- };
+ }
pList = (PSBSSIDList)kmalloc(sizeof(SBSSIDList) + (sList.uItem * sizeof(SBSSIDItem)), (int)GFP_ATOMIC);
if (pList == NULL) {
result = -ENOMEM;
@@ -367,7 +367,7 @@
if (copy_to_user(pReq->data, pList, sizeof(SBSSIDList) + (sList.uItem * sizeof(SBSSIDItem)))) {
result = -EFAULT;
break;
- };
+ }
kfree(pList);
pReq->wResult = 0;
break;
@@ -376,14 +376,14 @@
if (copy_to_user(pReq->data, &(pDevice->s802_11Counter), sizeof(SDot11MIBCount))) {
result = -EFAULT;
break;
- };
+ }
break;
case WLAN_CMD_GET_STAT:
if (copy_to_user(pReq->data, &(pDevice->scStatistic), sizeof(SStatCounter))) {
result = -EFAULT;
break;
- };
+ }
break;
case WLAN_CMD_STOP_MAC:
@@ -427,7 +427,7 @@
if (copy_from_user(&sValue, pReq->data, sizeof(SCmdValue))) {
result = -EFAULT;
break;
- };
+ }
if (sValue.dwValue == 1) {
if (vt6655_hostap_set_hostapd(pDevice, 1, 1) == 0){
DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO "Enable HOSTAP\n");
@@ -455,7 +455,7 @@
if (copy_from_user(&sValue, pReq->data, sizeof(SCmdValue))) {
result = -EFAULT;
break;
- };
+ }
if (sValue.dwValue == 1) {
pDevice->bEnable8021x = true;
@@ -475,7 +475,7 @@
if (copy_from_user(&sValue, pReq->data, sizeof(SCmdValue))) {
result = -EFAULT;
break;
- };
+ }
if (sValue.dwValue == 1) {
pDevice->bEnableHostWEP = true;
@@ -494,7 +494,7 @@
if (copy_from_user(&sValue, pReq->data, sizeof(SCmdValue))) {
result = -EFAULT;
break;
- };
+ }
if (sValue.dwValue == 1) {
DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO "up wpadev\n");
memcpy(pDevice->wpadev->dev_addr, pDevice->dev->dev_addr, ETH_ALEN);
@@ -519,7 +519,7 @@
if (copy_from_user(&sStartAPCmd, pReq->data, sizeof(SCmdStartAP))) {
result = -EFAULT;
break;
- };
+ }
if (sStartAPCmd.wBSSType == AP) {
pMgmt->eConfigMode = WMAC_CONFIG_AP;
@@ -606,13 +606,13 @@
if (!pNode->bActive)
continue;
cbListCount++;
- };
+ }
sNodeList.uItem = cbListCount;
if (copy_to_user(pReq->data, &sNodeList, sizeof(SNodeList))) {
result = -EFAULT;
break;
- };
+ }
pReq->wResult = 0;
break;
@@ -621,7 +621,7 @@
if (copy_from_user(&sNodeList, pReq->data, sizeof(SNodeList))) {
result = -EFAULT;
break;
- };
+ }
pNodeList = (PSNodeList)kmalloc(sizeof(SNodeList) + (sNodeList.uItem * sizeof(SNodeItem)), (int)GFP_ATOMIC);
if (pNodeList == NULL) {
result = -ENOMEM;
@@ -657,11 +657,11 @@
if (jj >= pNodeList->uItem)
break;
}
- };
+ }
if (copy_to_user(pReq->data, pNodeList, sizeof(SNodeList) + (sNodeList.uItem * sizeof(SNodeItem)))) {
result = -EFAULT;
break;
- };
+ }
kfree(pNodeList);
pReq->wResult = 0;
break;
diff --git a/drivers/staging/vt6655/power.c b/drivers/staging/vt6655/power.c
index 7207aca..4c0b02e 100644
--- a/drivers/staging/vt6655/power.c
+++ b/drivers/staging/vt6655/power.c
@@ -221,7 +221,7 @@
((pDevice->dwIsr& ISR_RXDMA0) != 0) &&
((pDevice->dwIsr & ISR_RXDMA1) != 0)){
return false;
- };
+ }
if (pMgmt->eCurrMode != WMAC_MODE_IBSS_STA) {
if (bCheckCountToWakeUp &&
diff --git a/drivers/staging/vt6655/rxtx.c b/drivers/staging/vt6655/rxtx.c
index c920cf6..6935b37 100644
--- a/drivers/staging/vt6655/rxtx.c
+++ b/drivers/staging/vt6655/rxtx.c
@@ -2902,13 +2902,13 @@
if (pDevice->bEnableHostWEP) {
uNodeIndex = 0;
bNodeExist = true;
- };
+ }
}
else {
if (pDevice->bEnableHostWEP) {
if (BSSDBbIsSTAInNodeDB(pDevice->pMgmt, (unsigned char *)(p80211Header->sA3.abyAddr1), &uNodeIndex))
bNodeExist = true;
- };
+ }
bNeedACK = true;
pTxBufHead->wFIFOCtl |= FIFOCTL_NEEDACK;
};
diff --git a/drivers/staging/vt6655/wcmd.c b/drivers/staging/vt6655/wcmd.c
index c30170a..bab3b01 100644
--- a/drivers/staging/vt6655/wcmd.c
+++ b/drivers/staging/vt6655/wcmd.c
@@ -385,7 +385,7 @@
spin_unlock_irq(&pDevice->lock);
vCommandTimerWait((void *)pDevice, 10);
return;
- };
+ }
if (pMgmt->uScanChannel == 0 ) {
pMgmt->uScanChannel = pDevice->byMinChannel;
@@ -519,7 +519,7 @@
vCommandTimerWait((void *)pDevice, 10);
spin_unlock_irq(&pDevice->lock);
return;
- };
+ }
DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO" CARDbRadioPowerOff\n");
//2008-09-02 <mark> by chester
// CARDbRadioPowerOff(pDevice);
@@ -532,7 +532,7 @@
vCommandTimerWait((void *)pDevice, 10);
spin_unlock_irq(&pDevice->lock);
return;
- };
+ }
//2008-09-02 <mark> by chester
// CARDbRadioPowerOff(pDevice);
s_bCommandComplete(pDevice);
@@ -619,7 +619,7 @@
vMgrCreateOwnIBSS((void *)pDevice, &Status);
if (Status != CMD_STATUS_SUCCESS){
DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO " WLAN_CMD_IBSS_CREATE fail ! \n");
- };
+ }
BSSvAddMulticastNode(pDevice);
}
}
@@ -631,7 +631,7 @@
vMgrCreateOwnIBSS((void *)pDevice, &Status);
if (Status != CMD_STATUS_SUCCESS){
DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO" WLAN_CMD_IBSS_CREATE fail ! \n");
- };
+ }
BSSvAddMulticastNode(pDevice);
if (netif_queue_stopped(pDevice->dev)){
netif_wake_queue(pDevice->dev);
@@ -783,7 +783,7 @@
vMgrCreateOwnIBSS((void *)pDevice, &Status);
if (Status != CMD_STATUS_SUCCESS){
DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO " vMgrCreateOwnIBSS fail ! \n");
- };
+ }
// alway turn off unicast bit
MACvRegBitsOff(pDevice->PortOffset, MAC_REG_RCR, RCR_UNICAST);
pDevice->byRxMode &= ~RCR_UNICAST;
@@ -814,7 +814,7 @@
}
pMgmt->sNodeDBTable[0].wEnQueueCnt--;
}
- };
+ }
// PS nodes tx
for (ii = 1; ii < (MAX_NODE_NUM + 1); ii++) {
diff --git a/drivers/staging/vt6655/wmgr.c b/drivers/staging/vt6655/wmgr.c
index e540110..ab289c3 100644
--- a/drivers/staging/vt6655/wmgr.c
+++ b/drivers/staging/vt6655/wmgr.c
@@ -661,7 +661,7 @@
if (*pStatus == CMD_STATUS_PENDING) {
pMgmt->eCurrState = WMAC_STATE_IDLE;
*pStatus = CMD_STATUS_SUCCESS;
- };
+ }
return;
}
@@ -1019,7 +1019,7 @@
(sFrame.pSuppRates == 0)){
DBG_PORT80(0xCC);
return;
- };
+ }
pMgmt->sAssocInfo.AssocInfo.ResponseFixedIEs.Capabilities = *(sFrame.pwCapInfo);
pMgmt->sAssocInfo.AssocInfo.ResponseFixedIEs.StatusCode = *(sFrame.pwStatus);
@@ -1039,7 +1039,7 @@
if ( (pMgmt->wCurrAID >> 14) != (BIT0 | BIT1) )
{
DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO "AID from AP, has two msb clear.\n");
- };
+ }
DBG_PRT(MSG_LEVEL_INFO, KERN_INFO "Association Successful, AID=%d.\n", pMgmt->wCurrAID & ~(BIT14|BIT15));
pMgmt->eCurrState = WMAC_STATE_ASSOC;
BSSvUpdateAPNode((void *)pDevice, sFrame.pwCapInfo, sFrame.pSuppRates, sFrame.pExtSuppRates);
@@ -1692,7 +1692,7 @@
//try to send associate packet again because of inactivity timeout
// if (pMgmt->eCurrState == WMAC_STATE_ASSOC) {
// vMgrReAssocBeginSta((PSDevice)pDevice, pMgmt, &CmdStatus);
- // };
+ // }
if ((pDevice->bWPADEVUp) && (pDevice->skb != NULL)) {
wpahdr = (viawget_wpa_header *)pDevice->skb->data;
wpahdr->type = VIAWGET_DISASSOC_MSG;
@@ -1707,7 +1707,7 @@
memset(pDevice->skb->cb, 0, sizeof(pDevice->skb->cb));
netif_rx(pDevice->skb);
pDevice->skb = dev_alloc_skb((int)pDevice->rx_buf_sz);
- };
+ }
#ifdef WPA_SUPPLICANT_DRIVER_WEXT_SUPPORT
// if(pDevice->bWPASuppWextEnabled == true)
@@ -1778,7 +1778,7 @@
netif_stop_queue(pDevice->dev);
pDevice->bLinkPass = false;
}
- };
+ }
if ((pDevice->bWPADEVUp) && (pDevice->skb != NULL)) {
wpahdr = (viawget_wpa_header *)pDevice->skb->data;
@@ -1793,7 +1793,7 @@
memset(pDevice->skb->cb, 0, sizeof(pDevice->skb->cb));
netif_rx(pDevice->skb);
pDevice->skb = dev_alloc_skb((int)pDevice->rx_buf_sz);
- };
+ }
#ifdef WPA_SUPPLICANT_DRIVER_WEXT_SUPPORT
// if(pDevice->bWPASuppWextEnabled == true)
@@ -1912,7 +1912,7 @@
(sFrame.pSuppRates == 0) ) {
DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO "Rx beacon frame error\n");
return;
- };
+ }
if (sFrame.pDSParms != NULL) {
@@ -2054,7 +2054,7 @@
sFrame.pSSID->len
) == 0) {
bIsSSIDEqual = true;
- };
+ }
}
if ((WLAN_GET_CAP_INFO_ESS(*sFrame.pwCapInfo)== true) &&
@@ -2138,8 +2138,8 @@
if (WLAN_GET_CAP_INFO_ESS(*sFrame.pwCapInfo)) {
if (sFrame.pCFParms->wCFPDurRemaining > 0) {
// TODO: deal with CFP period to set NAV
- };
- };
+ }
+ }
HIDWORD(qwTimestamp) = cpu_to_le32(HIDWORD(*sFrame.pqwTimestamp));
LODWORD(qwTimestamp) = cpu_to_le32(LODWORD(*sFrame.pqwTimestamp));
@@ -2160,7 +2160,7 @@
}
else if (HIDWORD(qwTimestamp) < HIDWORD(qwLocalTSF)) {
bTSFOffsetPostive = false;
- };
+ }
if (bTSFOffsetPostive) {
qwTSFOffset = CARDqGetTSFOffset(pRxPacket->byRxRate, (qwTimestamp), (qwLocalTSF));
@@ -2218,7 +2218,7 @@
if (pMgmt->bInTIM) {
PSvSendPSPOLL((PSDevice)pDevice);
// DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO "BCN:PS-POLL sent..\n");
- };
+ }
}
else {
@@ -2231,7 +2231,7 @@
}
if(PSbConsiderPowerDown(pDevice, false, false)) {
DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO "BCN: Power down now...\n");
- };
+ }
}
}
@@ -2316,7 +2316,7 @@
pMgmt->sNodeDBTable[0].bActive = true;
pMgmt->sNodeDBTable[0].uInActiveCount = 0;
- };
+ }
}
else if (bIsSSIDEqual) {
@@ -2356,9 +2356,9 @@
// Prepare beacon frame
bMgrPrepareBeaconToSend((void *)pDevice, pMgmt);
// }
- };
+ }
}
- };
+ }
// endian issue ???
// Update TSF
if (bUpdateTSF) {
@@ -2590,7 +2590,7 @@
pMgmt->byCSSPK = KEY_CTL_WEP;
pMgmt->byCSSGK = KEY_CTL_WEP;
}
- };
+ }
pMgmt->byERPContext = 0;
@@ -2683,7 +2683,7 @@
*pStatus = CMD_STATUS_RESOURCES;
DBG_PRT(MSG_LEVEL_NOTICE, KERN_INFO "BSS finding:BSS list is empty.\n");
return;
- };
+ }
// memset(pMgmt->abyDesireBSSID, 0, WLAN_BSSID_LEN);
// Search known BSS list for prefer BSSID or SSID
@@ -2699,7 +2699,7 @@
pItemSSID = (PWLAN_IE_SSID)pMgmt->abyDesireSSID;
DBG_PRT(MSG_LEVEL_NOTICE, KERN_INFO "Scanning [%s] not found, disconnected !\n", pItemSSID->abySSID);
return;
- };
+ }
DBG_PRT(MSG_LEVEL_NOTICE, KERN_INFO "AP(BSS) finding:Found a AP(BSS)..\n");
if (WLAN_GET_CAP_INFO_ESS(cpu_to_le16(pCurr->wCapInfo))){
@@ -3179,7 +3179,7 @@
}
wEndIndex = ii;
}
- };
+ }
// Round start index down to nearest even number
@@ -4343,7 +4343,7 @@
DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO "Probe resp:Fail addr:[%p] \n", pRxPacket->p80211Header);
DBG_PORT80(0xCC);
return;
- };
+ }
if(sFrame.pSSID->len == 0)
DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO "Rx Probe resp: SSID len = 0 \n");
@@ -4625,7 +4625,7 @@
//DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO "rx beacon\n");
if (pMgmt->eScanState != WMAC_NO_SCANNING) {
bInScan = true;
- };
+ }
s_vMgrRxBeacon(pDevice, pMgmt, pRxPacket, bInScan);
break;
diff --git a/drivers/staging/vt6655/wpactl.c b/drivers/staging/vt6655/wpactl.c
index fbae16d..a0f994e 100644
--- a/drivers/staging/vt6655/wpactl.c
+++ b/drivers/staging/vt6655/wpactl.c
@@ -653,7 +653,7 @@
}
- };
+ }
kfree(ptempBSS);
@@ -679,7 +679,7 @@
if (!pBSS->bActive)
continue;
count++;
- };
+ }
pBuf = kcalloc(count, sizeof(struct viawget_scan_result), (int)GFP_ATOMIC);
@@ -723,7 +723,7 @@
if (copy_to_user(param->u.scan_results.buf, pBuf, sizeof(struct viawget_scan_result) * count)) {
ret = -EFAULT;
- };
+ }
param->u.scan_results.scan_count = count;
DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO " param->u.scan_results.scan_count = %d\n", count)
@@ -832,7 +832,7 @@
break;
default:
pDevice->eEncryptionStatus = Ndis802_11EncryptionDisabled;
- };
+ }
//DavidWang add for WPA_supplicant support open/share mode
@@ -875,7 +875,7 @@
if (pCurr == NULL){
printk("wpa_set_associate---->hidden mode site survey before associate.......\n");
bScheduleCommand((void *) pDevice, WLAN_CMD_BSSID_SCAN, pMgmt->abyDesireSSID);
- };
+ }
}
/****************************************************************/
bScheduleCommand((void *) pDevice, WLAN_CMD_SSID, NULL);
diff --git a/drivers/staging/vt6656/bssdb.c b/drivers/staging/vt6656/bssdb.c
index 2bdd0a2..af006df 100644
--- a/drivers/staging/vt6656/bssdb.c
+++ b/drivers/staging/vt6656/bssdb.c
@@ -1192,7 +1192,7 @@
memset(pDevice->skb->cb, 0, sizeof(pDevice->skb->cb));
netif_rx(pDevice->skb);
pDevice->skb = dev_alloc_skb((int)pDevice->rx_buf_sz);
- };
+ }
#ifdef WPA_SUPPLICANT_DRIVER_WEXT_SUPPORT
// if(pDevice->bWPASuppWextEnabled == TRUE)
{
@@ -1416,7 +1416,7 @@
}
}
}
- };
+ }
if ((pMgmt->eCurrMode == WMAC_MODE_IBSS_STA) ||
(pMgmt->eCurrMode == WMAC_MODE_ESS_AP)) {
@@ -1472,9 +1472,9 @@
}
}
}
- };
+ }
}
- };
+ }
return;
diff --git a/drivers/staging/vt6656/dpc.c b/drivers/staging/vt6656/dpc.c
index f4fb0c6..cb817ce 100644
--- a/drivers/staging/vt6656/dpc.c
+++ b/drivers/staging/vt6656/dpc.c
@@ -730,7 +730,7 @@
pMgmt->bInTIMWake = FALSE;
}
}
- };
+ }
// Now it only supports 802.11g Infrastructure Mode, and support rate must up to 54 Mbps
if (pDevice->bDiversityEnable && (FrameSize>50) &&
@@ -913,7 +913,7 @@
memset(pDevice->skb->cb, 0, sizeof(pDevice->skb->cb));
netif_rx(pDevice->skb);
pDevice->skb = dev_alloc_skb((int)pDevice->rx_buf_sz);
- };
+ }
return FALSE;
@@ -1045,7 +1045,7 @@
);
DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO "dpc: send vMgrDeAuthenBeginSta 1\n");
return TRUE;
- };
+ }
if (pMgmt->sNodeDBTable[iSANodeIndex].eNodeState < NODE_ASSOC) {
// send deassoc notification
// reason = (7) class 3 received from nonassoc sta
@@ -1057,7 +1057,7 @@
);
DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO "dpc: send vMgrDisassocBeginSta 2\n");
return TRUE;
- };
+ }
if (pMgmt->sNodeDBTable[iSANodeIndex].bPSEnable) {
// delcare received ps-poll event
@@ -1488,7 +1488,7 @@
bRelayOnly = TRUE;
}
}
- };
+ }
}
if (bRelayOnly || bRelayAndForward) {
diff --git a/drivers/staging/vt6656/ioctl.c b/drivers/staging/vt6656/ioctl.c
index 2fe071c..cfe9c95 100644
--- a/drivers/staging/vt6656/ioctl.c
+++ b/drivers/staging/vt6656/ioctl.c
@@ -90,7 +90,7 @@
if (copy_from_user(&sScanCmd, pReq->data, sizeof(SCmdScan))) {
result = -EFAULT;
break;
- };
+ }
pItemSSID = (PWLAN_IE_SSID)sScanCmd.ssid;
if (pItemSSID->len != 0) {
@@ -124,7 +124,7 @@
if (copy_from_user(&sZoneTypeCmd, pReq->data, sizeof(SCmdZoneTypeSet))) {
result = -EFAULT;
break;
- };
+ }
if(sZoneTypeCmd.bWrite==TRUE) {
//////write zonetype
@@ -163,7 +163,7 @@
if (copy_to_user(pReq->data, &sZoneTypeCmd, sizeof(SCmdZoneTypeSet))) {
result = -EFAULT;
break;
- };
+ }
}
break;
@@ -173,7 +173,7 @@
if (copy_from_user(&sJoinCmd, pReq->data, sizeof(SCmdBSSJoin))) {
result = -EFAULT;
break;
- };
+ }
pItemSSID = (PWLAN_IE_SSID)sJoinCmd.ssid;
memset(pMgmt->abyDesireSSID, 0, WLAN_IEHDR_LEN + WLAN_SSID_MAXLEN + 1);
@@ -223,7 +223,7 @@
if (copy_from_user(&sWEPCmd, pReq->data, sizeof(SCmdSetWEP))) {
result = -EFAULT;
break;
- };
+ }
if (sWEPCmd.bEnableWep != TRUE) {
int uu;
@@ -295,7 +295,7 @@
if (copy_to_user(pReq->data, &sLinkStatus, sizeof(SCmdLinkStatus))) {
result = -EFAULT;
break;
- };
+ }
break;
@@ -307,12 +307,12 @@
if (!pBSS->bActive)
continue;
cbListCount++;
- };
+ }
sList.uItem = cbListCount;
if (copy_to_user(pReq->data, &sList, sizeof(SBSSIDList))) {
result = -EFAULT;
break;
- };
+ }
pReq->wResult = 0;
break;
@@ -320,7 +320,7 @@
if (copy_from_user(&sList, pReq->data, sizeof(SBSSIDList))) {
result = -EFAULT;
break;
- };
+ }
pList = (PSBSSIDList)kmalloc(sizeof(SBSSIDList) + (sList.uItem * sizeof(SBSSIDItem)), (int)GFP_ATOMIC);
if (pList == NULL) {
result = -ENOMEM;
@@ -362,7 +362,7 @@
if (copy_to_user(pReq->data, pList, sizeof(SBSSIDList) + (sList.uItem * sizeof(SBSSIDItem)))) {
result = -EFAULT;
break;
- };
+ }
kfree(pList);
pReq->wResult = 0;
break;
@@ -371,14 +371,14 @@
if (copy_to_user(pReq->data, &(pDevice->s802_11Counter), sizeof(SDot11MIBCount))) {
result = -EFAULT;
break;
- };
+ }
break;
case WLAN_CMD_GET_STAT:
if (copy_to_user(pReq->data, &(pDevice->scStatistic), sizeof(SStatCounter))) {
result = -EFAULT;
break;
- };
+ }
break;
case WLAN_CMD_STOP_MAC:
@@ -415,7 +415,7 @@
if (copy_from_user(&sValue, pReq->data, sizeof(SCmdValue))) {
result = -EFAULT;
break;
- };
+ }
if (sValue.dwValue == 1) {
if (vt6656_hostap_set_hostapd(pDevice, 1, 1) == 0){
DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO "Enable HOSTAP\n");
@@ -443,7 +443,7 @@
if (copy_from_user(&sValue, pReq->data, sizeof(SCmdValue))) {
result = -EFAULT;
break;
- };
+ }
if (sValue.dwValue == 1) {
pDevice->bEnable8021x = TRUE;
@@ -463,7 +463,7 @@
if (copy_from_user(&sValue, pReq->data, sizeof(SCmdValue))) {
result = -EFAULT;
break;
- };
+ }
if (sValue.dwValue == 1) {
pDevice->bEnableHostWEP = TRUE;
@@ -482,7 +482,7 @@
if (copy_from_user(&sValue, pReq->data, sizeof(SCmdValue))) {
result = -EFAULT;
break;
- };
+ }
if (sValue.dwValue == 1) {
DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO "up wpadev\n");
memcpy(pDevice->wpadev->dev_addr,
@@ -507,7 +507,7 @@
if (copy_from_user(&sStartAPCmd, pReq->data, sizeof(SCmdStartAP))) {
result = -EFAULT;
break;
- };
+ }
if (sStartAPCmd.wBSSType == AP) {
pMgmt->eConfigMode = WMAC_CONFIG_AP;
@@ -594,13 +594,13 @@
if (!pNode->bActive)
continue;
cbListCount++;
- };
+ }
sNodeList.uItem = cbListCount;
if (copy_to_user(pReq->data, &sNodeList, sizeof(SNodeList))) {
result = -EFAULT;
break;
- };
+ }
pReq->wResult = 0;
break;
@@ -609,7 +609,7 @@
if (copy_from_user(&sNodeList, pReq->data, sizeof(SNodeList))) {
result = -EFAULT;
break;
- };
+ }
pNodeList = (PSNodeList)kmalloc(sizeof(SNodeList) + (sNodeList.uItem * sizeof(SNodeItem)), (int)GFP_ATOMIC);
if (pNodeList == NULL) {
result = -ENOMEM;
@@ -645,11 +645,11 @@
if (jj >= pNodeList->uItem)
break;
}
- };
+ }
if (copy_to_user(pReq->data, pNodeList, sizeof(SNodeList) + (sNodeList.uItem * sizeof(SNodeItem)))) {
result = -EFAULT;
break;
- };
+ }
kfree(pNodeList);
pReq->wResult = 0;
break;
diff --git a/drivers/staging/vt6656/main_usb.c b/drivers/staging/vt6656/main_usb.c
index af14ab0..e18efd4 100644
--- a/drivers/staging/vt6656/main_usb.c
+++ b/drivers/staging/vt6656/main_usb.c
@@ -709,7 +709,7 @@
if(ii>20)
break;
}
- };
+ }
return TRUE;
}
@@ -955,7 +955,6 @@
pDevice->pInterruptURB = usb_alloc_urb(0, GFP_ATOMIC);
if (pDevice->pInterruptURB == NULL) {
DBG_PRT(MSG_LEVEL_ERR,KERN_ERR"Failed to alloc int urb\n");
- usb_kill_urb(pDevice->pControlURB);
usb_free_urb(pDevice->pControlURB);
goto free_rx_tx;
}
@@ -963,8 +962,6 @@
pDevice->intBuf.pDataBuf = kmalloc(MAX_INTERRUPT_SIZE, GFP_KERNEL);
if (pDevice->intBuf.pDataBuf == NULL) {
DBG_PRT(MSG_LEVEL_ERR,KERN_ERR"Failed to alloc int buf\n");
- usb_kill_urb(pDevice->pControlURB);
- usb_kill_urb(pDevice->pInterruptURB);
usb_free_urb(pDevice->pControlURB);
usb_free_urb(pDevice->pInterruptURB);
goto free_rx_tx;
@@ -995,7 +992,7 @@
DBG_PRT(MSG_LEVEL_ERR,KERN_ERR "%s: can not alloc frag bufs\n",
pDevice->dev->name);
goto free_frag;
- };
+ }
}
pDevice->cbDFCB = CB_MAX_RX_FRAG;
pDevice->cbFreeDFCB = pDevice->cbDFCB;
diff --git a/drivers/staging/vt6656/rxtx.c b/drivers/staging/vt6656/rxtx.c
index 5185d61..9b64b10 100644
--- a/drivers/staging/vt6656/rxtx.c
+++ b/drivers/staging/vt6656/rxtx.c
@@ -2441,13 +2441,13 @@
if (pDevice->bEnableHostWEP) {
uNodeIndex = 0;
bNodeExist = TRUE;
- };
+ }
}
else {
if (pDevice->bEnableHostWEP) {
if (BSSbIsSTAInNodeDB(pDevice, (PBYTE)(p80211Header->sA3.abyAddr1), &uNodeIndex))
bNodeExist = TRUE;
- };
+ }
bNeedACK = TRUE;
pTxBufHead->wFIFOCtl |= FIFOCTL_NEEDACK;
};
diff --git a/drivers/staging/vt6656/wcmd.c b/drivers/staging/vt6656/wcmd.c
index 019fb52..78ea121 100644
--- a/drivers/staging/vt6656/wcmd.c
+++ b/drivers/staging/vt6656/wcmd.c
@@ -642,7 +642,7 @@
if (Status != CMD_STATUS_SUCCESS){
DBG_PRT(MSG_LEVEL_DEBUG,
KERN_INFO "WLAN_CMD_IBSS_CREATE fail!\n");
- };
+ }
BSSvAddMulticastNode(pDevice);
}
s_bClearBSSID_SCAN(pDevice);
@@ -658,7 +658,7 @@
if (Status != CMD_STATUS_SUCCESS){
DBG_PRT(MSG_LEVEL_DEBUG,
KERN_INFO "WLAN_CMD_IBSS_CREATE fail!\n");
- };
+ }
BSSvAddMulticastNode(pDevice);
s_bClearBSSID_SCAN(pDevice);
/*
@@ -793,7 +793,7 @@
if (Status != CMD_STATUS_SUCCESS) {
DBG_PRT(MSG_LEVEL_DEBUG,
KERN_INFO "vMgrCreateOwnIBSS fail!\n");
- };
+ }
// alway turn off unicast bit
MACvRegBitsOff(pDevice, MAC_REG_RCR, RCR_UNICAST);
pDevice->byRxMode &= ~RCR_UNICAST;
@@ -827,7 +827,7 @@
pMgmt->sNodeDBTable[0].wEnQueueCnt--;
}
- };
+ }
// PS nodes tx
for (ii = 1; ii < (MAX_NODE_NUM + 1); ii++) {
diff --git a/drivers/staging/vt6656/wmgr.c b/drivers/staging/vt6656/wmgr.c
index 2ec200d..d67748f 100644
--- a/drivers/staging/vt6656/wmgr.c
+++ b/drivers/staging/vt6656/wmgr.c
@@ -593,7 +593,7 @@
if (*pStatus == CMD_STATUS_PENDING) {
pMgmt->eCurrState = WMAC_STATE_IDLE;
*pStatus = CMD_STATUS_SUCCESS;
- };
+ }
return;
}
@@ -942,7 +942,7 @@
|| (sFrame.pSuppRates == NULL)) {
DBG_PORT80(0xCC);
return;
- };
+ }
pMgmt->sAssocInfo.AssocInfo.ResponseFixedIEs.Capabilities = *(sFrame.pwCapInfo);
pMgmt->sAssocInfo.AssocInfo.ResponseFixedIEs.StatusCode = *(sFrame.pwStatus);
@@ -962,7 +962,7 @@
if ( (pMgmt->wCurrAID >> 14) != (BIT0 | BIT1) )
{
DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO "AID from AP, has two msb clear.\n");
- };
+ }
DBG_PRT(MSG_LEVEL_INFO, KERN_INFO "Association Successful, AID=%d.\n", pMgmt->wCurrAID & ~(BIT14|BIT15));
pMgmt->eCurrState = WMAC_STATE_ASSOC;
BSSvUpdateAPNode((void *) pDevice,
@@ -1621,7 +1621,7 @@
memset(pDevice->skb->cb, 0, sizeof(pDevice->skb->cb));
netif_rx(pDevice->skb);
pDevice->skb = dev_alloc_skb((int)pDevice->rx_buf_sz);
- };
+ }
//TODO: do something let upper layer know or
//try to send associate packet again because of inactivity timeout
@@ -1636,7 +1636,7 @@
pDevice->byReAssocCount ++;
return; //mike add: you'll retry for many times, so it cann't be regarded as disconnected!
}
- };
+ }
#ifdef WPA_SUPPLICANT_DRIVER_WEXT_SUPPORT
// if(pDevice->bWPASuppWextEnabled == TRUE)
@@ -1710,7 +1710,7 @@
pDevice->bLinkPass = FALSE;
ControlvMaskByte(pDevice,MESSAGE_REQUEST_MACREG,MAC_REG_PAPEDELAY,LEDSTS_STS,LEDSTS_SLOW);
}
- };
+ }
if ((pDevice->bWPADEVUp) && (pDevice->skb != NULL)) {
wpahdr = (viawget_wpa_header *)pDevice->skb->data;
@@ -1725,7 +1725,7 @@
memset(pDevice->skb->cb, 0, sizeof(pDevice->skb->cb));
netif_rx(pDevice->skb);
pDevice->skb = dev_alloc_skb((int)pDevice->rx_buf_sz);
- };
+ }
#ifdef WPA_SUPPLICANT_DRIVER_WEXT_SUPPORT
// if(pDevice->bWPASuppWextEnabled == TRUE)
@@ -1845,7 +1845,7 @@
DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO "Rx beacon frame error\n");
return;
- };
+ }
if( byCurrChannel > CB_MAX_CHANNEL_24G )
{
@@ -1974,7 +1974,7 @@
sFrame.pSSID->len
) == 0) {
bIsSSIDEqual = TRUE;
- };
+ }
}
if ((WLAN_GET_CAP_INFO_ESS(*sFrame.pwCapInfo)== TRUE) &&
@@ -2074,8 +2074,8 @@
if (WLAN_GET_CAP_INFO_ESS(*sFrame.pwCapInfo)) {
if (sFrame.pCFParms->wCFPDurRemaining > 0) {
// TODO: deal with CFP period to set NAV
- };
- };
+ }
+ }
HIDWORD(qwTimestamp) = cpu_to_le32(HIDWORD(*sFrame.pqwTimestamp));
LODWORD(qwTimestamp) = cpu_to_le32(LODWORD(*sFrame.pqwTimestamp));
@@ -2096,7 +2096,7 @@
}
else if (HIDWORD(qwTimestamp) < HIDWORD(qwLocalTSF)) {
bTSFOffsetPostive = FALSE;
- };
+ }
if (bTSFOffsetPostive) {
qwTSFOffset = CARDqGetTSFOffset(pRxPacket->byRxRate, (qwTimestamp), (qwLocalTSF));
@@ -2154,7 +2154,7 @@
if (pMgmt->bInTIM) {
PSvSendPSPOLL((PSDevice)pDevice);
// DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO "BCN:PS-POLL sent..\n");
- };
+ }
}
else {
@@ -2167,7 +2167,7 @@
}
if(PSbConsiderPowerDown(pDevice, FALSE, FALSE)) {
DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO "BCN: Power down now...\n");
- };
+ }
}
}
@@ -2247,7 +2247,7 @@
pMgmt->sNodeDBTable[0].bActive = TRUE;
pMgmt->sNodeDBTable[0].uInActiveCount = 0;
- };
+ }
}
else if (bIsSSIDEqual) {
@@ -2292,9 +2292,9 @@
// Prepare beacon frame
bMgrPrepareBeaconToSend((void *) pDevice, pMgmt);
// }
- };
+ }
}
- };
+ }
// endian issue ???
// Update TSF
if (bUpdateTSF) {
@@ -2556,7 +2556,7 @@
pMgmt->byCSSPK = KEY_CTL_WEP;
pMgmt->byCSSGK = KEY_CTL_WEP;
}
- };
+ }
pMgmt->byERPContext = 0;
@@ -2614,7 +2614,7 @@
*pStatus = CMD_STATUS_RESOURCES;
DBG_PRT(MSG_LEVEL_NOTICE, KERN_INFO "BSS finding:BSS list is empty.\n");
return;
- };
+ }
// memset(pMgmt->abyDesireBSSID, 0, WLAN_BSSID_LEN);
// Search known BSS list for prefer BSSID or SSID
@@ -2630,7 +2630,7 @@
pItemSSID = (PWLAN_IE_SSID)pMgmt->abyDesireSSID;
DBG_PRT(MSG_LEVEL_NOTICE, KERN_INFO "Scanning [%s] not found, disconnected !\n", pItemSSID->abySSID);
return;
- };
+ }
DBG_PRT(MSG_LEVEL_NOTICE, KERN_INFO "AP(BSS) finding:Found a AP(BSS)..\n");
@@ -3061,7 +3061,7 @@
MACvRegBitsOn(pDevice, MAC_REG_RCR, RCR_BSSID);
pDevice->byRxMode |= RCR_BSSID;
pMgmt->bCurrBSSIDFilterOn = TRUE;
- };
+ }
if (pDevice->byBBType == BB_TYPE_11A) {
memcpy(pMgmt->abyCurrSuppRates, &abyCurrSuppRatesA[0], sizeof(abyCurrSuppRatesA));
@@ -3167,7 +3167,7 @@
}
wEndIndex = (WORD)ii;
}
- };
+ }
// Round start index down to nearest even number
@@ -4209,7 +4209,7 @@
pRxPacket->p80211Header);
DBG_PORT80(0xCC);
return;
- };
+ }
if(sFrame.pSSID->len == 0)
DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO "Rx Probe resp: SSID len = 0 \n");
@@ -4491,7 +4491,7 @@
//DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO "rx beacon\n");
if (pMgmt->eScanState != WMAC_NO_SCANNING) {
bInScan = TRUE;
- };
+ }
s_vMgrRxBeacon(pDevice, pMgmt, pRxPacket, bInScan);
break;
diff --git a/drivers/staging/vt6656/wpactl.c b/drivers/staging/vt6656/wpactl.c
index 8752736..9216df0 100644
--- a/drivers/staging/vt6656/wpactl.c
+++ b/drivers/staging/vt6656/wpactl.c
@@ -660,7 +660,7 @@
}
- };
+ }
kfree(ptempBSS);
@@ -673,7 +673,7 @@
if (!pBSS->bActive)
continue;
count++;
- };
+ }
pBuf = kcalloc(count, sizeof(struct viawget_scan_result), (int)GFP_ATOMIC);
@@ -729,7 +729,7 @@
if (copy_to_user(param->u.scan_results.buf, pBuf, sizeof(struct viawget_scan_result) * count)) {
ret = -EFAULT;
- };
+ }
param->u.scan_results.scan_count = count;
DBG_PRT(MSG_LEVEL_DEBUG, KERN_INFO " param->u.scan_results.scan_count = %d\n", count)
@@ -831,7 +831,7 @@
break;
default:
pDevice->eEncryptionStatus = Ndis802_11EncryptionDisabled;
- };
+ }
pMgmt->Roam_dbm = param->u.wpa_associate.roam_dbm;
// if ((pMgmt->Roam_dbm > 40)&&(pMgmt->Roam_dbm<80))
@@ -886,7 +886,7 @@
bScheduleCommand((void *) pDevice,
WLAN_CMD_BSSID_SCAN,
pMgmt->abyDesireSSID);
- };
+ }
}
/****************************************************************/
diff --git a/drivers/staging/westbridge/astoria/arch/arm/mach-omap2/cyashalomap_kernel.c b/drivers/staging/westbridge/astoria/arch/arm/mach-omap2/cyashalomap_kernel.c
index 3bcedce..dd4cd41 100644
--- a/drivers/staging/westbridge/astoria/arch/arm/mach-omap2/cyashalomap_kernel.c
+++ b/drivers/staging/westbridge/astoria/arch/arm/mach-omap2/cyashalomap_kernel.c
@@ -768,7 +768,7 @@
cy_as_hal_print_message(KERN_INFO "%s virt_addr=%x\n",
gpio_vma_tab[i].name,
(u32)gpio_vma_tab[i].virt_addr);
- };
+ }
/*
* force OMAP_GPIO_126 to rleased state,
diff --git a/drivers/staging/westbridge/astoria/block/cyasblkdev_block.c b/drivers/staging/westbridge/astoria/block/cyasblkdev_block.c
index 289729d..87452bd 100644
--- a/drivers/staging/westbridge/astoria/block/cyasblkdev_block.c
+++ b/drivers/staging/westbridge/astoria/block/cyasblkdev_block.c
@@ -515,7 +515,7 @@
while (blk_end_request(gl_bd->queue.req,
status, blk_rq_sectors(gl_bd->queue.req)*512)) {
retry_cnt++;
- };
+ }
#ifndef WESTBRIDGE_NDEBUG
cy_as_hal_print_message(
diff --git a/drivers/staging/winbond/mto.c b/drivers/staging/winbond/mto.c
index c03e501..5250217 100644
--- a/drivers/staging/winbond/mto.c
+++ b/drivers/staging/winbond/mto.c
@@ -40,14 +40,9 @@
2, 4, 11, 22, 12, 18, 24, 36, 48, 72, 96, 108
};
-static int TotalTxPkt;
-static int TotalTxPktRetry;
/* this record the retry rate at different data rate */
static int retryrate_rec[MTO_MAX_DATA_RATE_LEVELS];
-static int PeriodTotalTxPkt;
-static int PeriodTotalTxPktRetry;
-
static u8 boSparseTxTraffic;
void MTO_Init(struct wbsoft_priv *adapter);
@@ -174,9 +169,4 @@
MTO_HAL()->dto_tx_retry_count += index;
MTO_HAL()->dto_tx_frag_count += (index + 1);
}
- TotalTxPkt++;
- TotalTxPktRetry += (index + 1);
-
- PeriodTotalTxPkt++;
- PeriodTotalTxPktRetry += (index + 1);
}
diff --git a/drivers/staging/winbond/phy_calibration.c b/drivers/staging/winbond/phy_calibration.c
index 09844db..79e53e4 100644
--- a/drivers/staging/winbond/phy_calibration.c
+++ b/drivers/staging/winbond/phy_calibration.c
@@ -27,10 +27,10 @@
#define DEG2RAD(X) 0.017453 * (X)
static const s32 Angles[] = {
- FIXED(DEG2RAD(45.0)), FIXED(DEG2RAD(26.565)), FIXED(DEG2RAD(14.0362)),
- FIXED(DEG2RAD(7.12502)), FIXED(DEG2RAD(3.57633)), FIXED(DEG2RAD(1.78991)),
- FIXED(DEG2RAD(0.895174)), FIXED(DEG2RAD(0.447614)), FIXED(DEG2RAD(0.223811)),
- FIXED(DEG2RAD(0.111906)), FIXED(DEG2RAD(0.055953)), FIXED(DEG2RAD(0.027977))
+ FIXED(DEG2RAD(45.0)), FIXED(DEG2RAD(26.565)), FIXED(DEG2RAD(14.0362)),
+ FIXED(DEG2RAD(7.12502)), FIXED(DEG2RAD(3.57633)), FIXED(DEG2RAD(1.78991)),
+ FIXED(DEG2RAD(0.895174)), FIXED(DEG2RAD(0.447614)), FIXED(DEG2RAD(0.223811)),
+ FIXED(DEG2RAD(0.111906)), FIXED(DEG2RAD(0.055953)), FIXED(DEG2RAD(0.027977))
};
/****************** LOCAL FUNCTION DECLARATION SECTION **********************/
diff --git a/drivers/staging/winbond/wb35tx.c b/drivers/staging/winbond/wb35tx.c
index 44fc3fe..5df39d4 100644
--- a/drivers/staging/winbond/wb35tx.c
+++ b/drivers/staging/winbond/wb35tx.c
@@ -291,7 +291,6 @@
if (atomic_inc_return(&pWb35Tx->TxResultCount) == 1) {
pWb35Tx->EP2vm_state = VM_RUNNING;
Wb35Tx_EP2VM(adapter);
- }
- else
+ } else
atomic_dec(&pWb35Tx->TxResultCount);
}
diff --git a/drivers/staging/wlags49_h2/wl_cs.c b/drivers/staging/wlags49_h2/wl_cs.c
index 6555891..a3a727c 100644
--- a/drivers/staging/wlags49_h2/wl_cs.c
+++ b/drivers/staging/wlags49_h2/wl_cs.c
@@ -378,7 +378,7 @@
} /* wl_adapter_close */
/*============================================================================*/
-static struct pcmcia_device_id wl_adapter_ids[] = {
+static const struct pcmcia_device_id wl_adapter_ids[] = {
#if !((HCF_TYPE) & HCF_TYPE_HII5)
PCMCIA_DEVICE_MANF_CARD(0x0156, 0x0003),
PCMCIA_DEVICE_PROD_ID12("Agere Systems", "Wireless PC Card Model 0110",
diff --git a/drivers/staging/xgifb/XGI_main.h b/drivers/staging/xgifb/XGI_main.h
index 46b5958..f6cd22d 100644
--- a/drivers/staging/xgifb/XGI_main.h
+++ b/drivers/staging/xgifb/XGI_main.h
@@ -9,7 +9,7 @@
#include "vb_struct.h"
#include "vb_def.h"
-#define XGIFAIL(x) do { printk(x "\n"); return -EINVAL; } while(0)
+#define XGIFAIL(x) do { printk(x "\n"); return -EINVAL; } while (0)
#define VER_MAJOR 0
#define VER_MINOR 8
@@ -44,11 +44,15 @@
#define XGIINITSTATIC static
static DEFINE_PCI_DEVICE_TABLE(xgifb_pci_table) = {
- { PCI_VENDOR_ID_XG, PCI_DEVICE_ID_XG_20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
- { PCI_VENDOR_ID_XG, PCI_DEVICE_ID_XG_27, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 1},
- { PCI_VENDOR_ID_XG, PCI_DEVICE_ID_XG_40, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 2},
- { PCI_VENDOR_ID_XG, PCI_DEVICE_ID_XG_42, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 3},
- { 0 }
+ {PCI_VENDOR_ID_XG, PCI_DEVICE_ID_XG_20, PCI_ANY_ID, PCI_ANY_ID,
+ 0, 0, 0},
+ {PCI_VENDOR_ID_XG, PCI_DEVICE_ID_XG_27, PCI_ANY_ID, PCI_ANY_ID,
+ 0, 0, 1},
+ {PCI_VENDOR_ID_XG, PCI_DEVICE_ID_XG_40, PCI_ANY_ID, PCI_ANY_ID,
+ 0, 0, 2},
+ {PCI_VENDOR_ID_XG, PCI_DEVICE_ID_XG_42, PCI_ANY_ID, PCI_ANY_ID,
+ 0, 0, 3},
+ {0}
};
MODULE_DEVICE_TABLE(pci, xgifb_pci_table);
@@ -148,10 +152,10 @@
#define XGI_DATA_BUS_64 0x00
#define XGI_DATA_BUS_128 0x01
#define XGI_DUAL_CHANNEL_MASK 0x0C
-#define XGI_SINGLE_CHANNEL_1_RANK 0x0
-#define XGI_SINGLE_CHANNEL_2_RANK 0x1
-#define XGI_ASYM_DDR 0x02
-#define XGI_DUAL_CHANNEL_1_RANK 0x3
+#define XGI_SINGLE_CHANNEL_1_RANK 0x0
+#define XGI_SINGLE_CHANNEL_2_RANK 0x1
+#define XGI_ASYM_DDR 0x02
+#define XGI_DUAL_CHANNEL_1_RANK 0x3
#define XGI550_DRAM_SIZE_MASK 0x3F /* 550/650/740 SR14 */
#define XGI550_DRAM_SIZE_4MB 0x00
@@ -190,11 +194,11 @@
#define XGI_VB_CRT2 0x10
#define XGI_CRT1 0x20
#define XGI_VB_HIVISION 0x40
-#define XGI_VB_YPBPR 0x80
-#define XGI_VB_TV (XGI_VB_COMPOSITE | XGI_VB_SVIDEO | \
- XGI_VB_SCART | XGI_VB_HIVISION|XGI_VB_YPBPR)
+#define XGI_VB_YPBPR 0x80
+#define XGI_VB_TV (XGI_VB_COMPOSITE | XGI_VB_SVIDEO | \
+ XGI_VB_SCART | XGI_VB_HIVISION|XGI_VB_YPBPR)
-#define XGI_EXTERNAL_CHIP_MASK 0x0E /* CR37 */
+#define XGI_EXTERNAL_CHIP_MASK 0x0E /* CR37 */
#define XGI_EXTERNAL_CHIP_XGI301 0x01 /* in CR37 << 1 ! */
#define XGI_EXTERNAL_CHIP_LVDS 0x02 /* in CR37 << 1 ! */
#define XGI_EXTERNAL_CHIP_TRUMPION 0x03 /* in CR37 << 1 ! */
@@ -216,46 +220,10 @@
#define SR_BUFFER_SIZE 5
#define CR_BUFFER_SIZE 5
-/* Useful macros */
-#define inXGIREG(base) inb(base)
-#define outXGIREG(base,val) outb(val,base)
-#define orXGIREG(base,val) do { \
- unsigned char __Temp = inb(base); \
- outXGIREG(base, __Temp | (val)); \
- } while (0)
-#define andXGIREG(base,val) do { \
- unsigned char __Temp = inb(base); \
- outXGIREG(base, __Temp & (val)); \
- } while (0)
-#define inXGIIDXREG(base,idx,var) do { \
- outb(idx,base); var=inb((base)+1); \
- } while (0)
-#define outXGIIDXREG(base,idx,val) do { \
- outb(idx,base); outb((val),(base)+1); \
- } while (0)
-#define orXGIIDXREG(base,idx,val) do { \
- unsigned char __Temp; \
- outb(idx,base); \
- __Temp = inb((base)+1)|(val); \
- outXGIIDXREG(base,idx,__Temp); \
- } while (0)
-#define andXGIIDXREG(base,idx,and) do { \
- unsigned char __Temp; \
- outb(idx,base); \
- __Temp = inb((base)+1)&(and); \
- outXGIIDXREG(base,idx,__Temp); \
- } while (0)
-#define setXGIIDXREG(base,idx,and,or) do { \
- unsigned char __Temp; \
- outb(idx,base); \
- __Temp = (inb((base)+1)&(and))|(or); \
- outXGIIDXREG(base,idx,__Temp); \
- } while (0)
-
/* ------------------- Global Variables ----------------------------- */
/* Fbcon variables */
-static struct fb_info* fb_info;
+static struct fb_info *fb_info;
static int video_type = FB_TYPE_PACKED_PIXELS;
@@ -304,7 +272,7 @@
static int XGIfb_crt1off = 0;
static int XGIfb_forcecrt1 = -1;
static int XGIfb_userom = 0;
-//static int XGIfb_useoem = -1;
+/*static int XGIfb_useoem = -1; */
/* global flags */
static int XGIfb_registered;
@@ -316,8 +284,10 @@
static int XGIfb_CRT2_write_enable = 0;
-static int XGIfb_crt2type = -1; /* TW: CRT2 type (for overriding autodetection) */
-static int XGIfb_tvplug = -1; /* PR: Tv plug type (for overriding autodetection) */
+/* TW: CRT2 type (for overriding autodetection) */
+static int XGIfb_crt2type = -1;
+/* PR: Tv plug type (for overriding autodetection) */
+static int XGIfb_tvplug = -1;
static unsigned char XGIfb_detectedpdc = 0;
@@ -354,82 +324,155 @@
u8 chipset;
} XGIbios_mode[] = {
#define MODE_INDEX_NONE 0 /* TW: index for mode=none */
- {"none", 0xFF, 0x0000, 0x0000, 0, 0, 0, 0, 0, 0, MD_XGI300|MD_XGI315}, /* TW: for mode "none" */
- {"320x240x16", 0x56, 0x0000, 0x0000, 320, 240, 16, 1, 40, 15, MD_XGI315},
- {"320x480x8", 0x5A, 0x0000, 0x0000, 320, 480, 8, 1, 40, 30, MD_XGI315}, /* TW: FSTN */
- {"320x480x16", 0x5B, 0x0000, 0x0000, 320, 480, 16, 1, 40, 30, MD_XGI315}, /* TW: FSTN */
- {"640x480x8", 0x2E, 0x0101, 0x0101, 640, 480, 8, 1, 80, 30, MD_XGI300|MD_XGI315},
- {"640x480x16", 0x44, 0x0111, 0x0111, 640, 480, 16, 1, 80, 30, MD_XGI300|MD_XGI315},
- {"640x480x24", 0x62, 0x013a, 0x0112, 640, 480, 32, 1, 80, 30, MD_XGI300|MD_XGI315}, /* TW: That's for people who mix up color- and fb depth */
- {"640x480x32", 0x62, 0x013a, 0x0112, 640, 480, 32, 1, 80, 30, MD_XGI300|MD_XGI315},
- {"720x480x8", 0x31, 0x0000, 0x0000, 720, 480, 8, 1, 90, 30, MD_XGI300|MD_XGI315},
- {"720x480x16", 0x33, 0x0000, 0x0000, 720, 480, 16, 1, 90, 30, MD_XGI300|MD_XGI315},
- {"720x480x24", 0x35, 0x0000, 0x0000, 720, 480, 32, 1, 90, 30, MD_XGI300|MD_XGI315},
- {"720x480x32", 0x35, 0x0000, 0x0000, 720, 480, 32, 1, 90, 30, MD_XGI300|MD_XGI315},
- {"720x576x8", 0x32, 0x0000, 0x0000, 720, 576, 8, 1, 90, 36, MD_XGI300|MD_XGI315},
- {"720x576x16", 0x34, 0x0000, 0x0000, 720, 576, 16, 1, 90, 36, MD_XGI300|MD_XGI315},
- {"720x576x24", 0x36, 0x0000, 0x0000, 720, 576, 32, 1, 90, 36, MD_XGI300|MD_XGI315},
- {"720x576x32", 0x36, 0x0000, 0x0000, 720, 576, 32, 1, 90, 36, MD_XGI300|MD_XGI315},
- {"800x480x8", 0x70, 0x0000, 0x0000, 800, 480, 8, 1, 100, 30, MD_XGI300|MD_XGI315},
- {"800x480x16", 0x7a, 0x0000, 0x0000, 800, 480, 16, 1, 100, 30, MD_XGI300|MD_XGI315},
- {"800x480x24", 0x76, 0x0000, 0x0000, 800, 480, 32, 1, 100, 30, MD_XGI300|MD_XGI315},
- {"800x480x32", 0x76, 0x0000, 0x0000, 800, 480, 32, 1, 100, 30, MD_XGI300|MD_XGI315},
+ {"none", 0xFF, 0x0000, 0x0000, 0, 0, 0, 0, 0, 0,
+ MD_XGI300|MD_XGI315}, /* TW: for mode "none" */
+ {"320x240x16", 0x56, 0x0000, 0x0000, 320, 240, 16, 1, 40, 15,
+ MD_XGI315},
+ {"320x480x8", 0x5A, 0x0000, 0x0000, 320, 480, 8, 1, 40, 30,
+ MD_XGI315}, /* TW: FSTN */
+ {"320x480x16", 0x5B, 0x0000, 0x0000, 320, 480, 16, 1, 40, 30,
+ MD_XGI315}, /* TW: FSTN */
+ {"640x480x8", 0x2E, 0x0101, 0x0101, 640, 480, 8, 1, 80, 30,
+ MD_XGI300|MD_XGI315},
+ {"640x480x16", 0x44, 0x0111, 0x0111, 640, 480, 16, 1, 80, 30,
+ MD_XGI300|MD_XGI315},
+ {"640x480x24", 0x62, 0x013a, 0x0112, 640, 480, 32, 1, 80, 30,
+ MD_XGI300|MD_XGI315}, /* TW: That's for people who mix up color-
+ and fb depth */
+ {"640x480x32", 0x62, 0x013a, 0x0112, 640, 480, 32, 1, 80, 30,
+ MD_XGI300|MD_XGI315},
+ {"720x480x8", 0x31, 0x0000, 0x0000, 720, 480, 8, 1, 90, 30,
+ MD_XGI300|MD_XGI315},
+ {"720x480x16", 0x33, 0x0000, 0x0000, 720, 480, 16, 1, 90, 30,
+ MD_XGI300|MD_XGI315},
+ {"720x480x24", 0x35, 0x0000, 0x0000, 720, 480, 32, 1, 90, 30,
+ MD_XGI300|MD_XGI315},
+ {"720x480x32", 0x35, 0x0000, 0x0000, 720, 480, 32, 1, 90, 30,
+ MD_XGI300|MD_XGI315},
+ {"720x576x8", 0x32, 0x0000, 0x0000, 720, 576, 8, 1, 90, 36,
+ MD_XGI300|MD_XGI315},
+ {"720x576x16", 0x34, 0x0000, 0x0000, 720, 576, 16, 1, 90, 36,
+ MD_XGI300|MD_XGI315},
+ {"720x576x24", 0x36, 0x0000, 0x0000, 720, 576, 32, 1, 90, 36,
+ MD_XGI300|MD_XGI315},
+ {"720x576x32", 0x36, 0x0000, 0x0000, 720, 576, 32, 1, 90, 36,
+ MD_XGI300|MD_XGI315},
+ {"800x480x8", 0x70, 0x0000, 0x0000, 800, 480, 8, 1, 100, 30,
+ MD_XGI300|MD_XGI315},
+ {"800x480x16", 0x7a, 0x0000, 0x0000, 800, 480, 16, 1, 100, 30,
+ MD_XGI300|MD_XGI315},
+ {"800x480x24", 0x76, 0x0000, 0x0000, 800, 480, 32, 1, 100, 30,
+ MD_XGI300|MD_XGI315},
+ {"800x480x32", 0x76, 0x0000, 0x0000, 800, 480, 32, 1, 100, 30,
+ MD_XGI300|MD_XGI315},
#define DEFAULT_MODE 21 /* TW: index for 800x600x8 */
#define DEFAULT_LCDMODE 21 /* TW: index for 800x600x8 */
#define DEFAULT_TVMODE 21 /* TW: index for 800x600x8 */
- {"800x600x8", 0x30, 0x0103, 0x0103, 800, 600, 8, 1, 100, 37, MD_XGI300|MD_XGI315},
- {"800x600x16", 0x47, 0x0114, 0x0114, 800, 600, 16, 1, 100, 37, MD_XGI300|MD_XGI315},
- {"800x600x24", 0x63, 0x013b, 0x0115, 800, 600, 32, 1, 100, 37, MD_XGI300|MD_XGI315},
- {"800x600x32", 0x63, 0x013b, 0x0115, 800, 600, 32, 1, 100, 37, MD_XGI300|MD_XGI315},
- {"1024x576x8", 0x71, 0x0000, 0x0000, 1024, 576, 8, 1, 128, 36, MD_XGI300|MD_XGI315},
- {"1024x576x16", 0x74, 0x0000, 0x0000, 1024, 576, 16, 1, 128, 36, MD_XGI300|MD_XGI315},
- {"1024x576x24", 0x77, 0x0000, 0x0000, 1024, 576, 32, 1, 128, 36, MD_XGI300|MD_XGI315},
- {"1024x576x32", 0x77, 0x0000, 0x0000, 1024, 576, 32, 1, 128, 36, MD_XGI300|MD_XGI315},
- {"1024x600x8", 0x20, 0x0000, 0x0000, 1024, 600, 8, 1, 128, 37, MD_XGI300 }, /* TW: 300 series only */
- {"1024x600x16", 0x21, 0x0000, 0x0000, 1024, 600, 16, 1, 128, 37, MD_XGI300 },
- {"1024x600x24", 0x22, 0x0000, 0x0000, 1024, 600, 32, 1, 128, 37, MD_XGI300 },
- {"1024x600x32", 0x22, 0x0000, 0x0000, 1024, 600, 32, 1, 128, 37, MD_XGI300 },
- {"1024x768x8", 0x38, 0x0105, 0x0105, 1024, 768, 8, 1, 128, 48, MD_XGI300|MD_XGI315},
- {"1024x768x16", 0x4A, 0x0117, 0x0117, 1024, 768, 16, 1, 128, 48, MD_XGI300|MD_XGI315},
- {"1024x768x24", 0x64, 0x013c, 0x0118, 1024, 768, 32, 1, 128, 48, MD_XGI300|MD_XGI315},
- {"1024x768x32", 0x64, 0x013c, 0x0118, 1024, 768, 32, 1, 128, 48, MD_XGI300|MD_XGI315},
- {"1152x768x8", 0x23, 0x0000, 0x0000, 1152, 768, 8, 1, 144, 48, MD_XGI300 }, /* TW: 300 series only */
- {"1152x768x16", 0x24, 0x0000, 0x0000, 1152, 768, 16, 1, 144, 48, MD_XGI300 },
- {"1152x768x24", 0x25, 0x0000, 0x0000, 1152, 768, 32, 1, 144, 48, MD_XGI300 },
- {"1152x768x32", 0x25, 0x0000, 0x0000, 1152, 768, 32, 1, 144, 48, MD_XGI300 },
- {"1280x720x8", 0x79, 0x0000, 0x0000, 1280, 720, 8, 1, 160, 45, MD_XGI300|MD_XGI315},
- {"1280x720x16", 0x75, 0x0000, 0x0000, 1280, 720, 16, 1, 160, 45, MD_XGI300|MD_XGI315},
- {"1280x720x24", 0x78, 0x0000, 0x0000, 1280, 720, 32, 1, 160, 45, MD_XGI300|MD_XGI315},
- {"1280x720x32", 0x78, 0x0000, 0x0000, 1280, 720, 32, 1, 160, 45, MD_XGI300|MD_XGI315},
- {"1280x768x8", 0x23, 0x0000, 0x0000, 1280, 768, 8, 1, 160, 48, MD_XGI315}, /* TW: 310/325 series only */
- {"1280x768x16", 0x24, 0x0000, 0x0000, 1280, 768, 16, 1, 160, 48, MD_XGI315},
- {"1280x768x24", 0x25, 0x0000, 0x0000, 1280, 768, 32, 1, 160, 48, MD_XGI315},
- {"1280x768x32", 0x25, 0x0000, 0x0000, 1280, 768, 32, 1, 160, 48, MD_XGI315},
+ {"800x600x8", 0x30, 0x0103, 0x0103, 800, 600, 8, 1, 100, 37,
+ MD_XGI300|MD_XGI315},
+ {"800x600x16", 0x47, 0x0114, 0x0114, 800, 600, 16, 1, 100, 37,
+ MD_XGI300|MD_XGI315},
+ {"800x600x24", 0x63, 0x013b, 0x0115, 800, 600, 32, 1, 100, 37,
+ MD_XGI300|MD_XGI315},
+ {"800x600x32", 0x63, 0x013b, 0x0115, 800, 600, 32, 1, 100, 37,
+ MD_XGI300|MD_XGI315},
+ {"1024x576x8", 0x71, 0x0000, 0x0000, 1024, 576, 8, 1, 128, 36,
+ MD_XGI300|MD_XGI315},
+ {"1024x576x16", 0x74, 0x0000, 0x0000, 1024, 576, 16, 1, 128, 36,
+ MD_XGI300|MD_XGI315},
+ {"1024x576x24", 0x77, 0x0000, 0x0000, 1024, 576, 32, 1, 128, 36,
+ MD_XGI300|MD_XGI315},
+ {"1024x576x32", 0x77, 0x0000, 0x0000, 1024, 576, 32, 1, 128, 36,
+ MD_XGI300|MD_XGI315},
+ {"1024x600x8", 0x20, 0x0000, 0x0000, 1024, 600, 8, 1, 128, 37,
+ MD_XGI300 }, /* TW: 300 series only */
+ {"1024x600x16", 0x21, 0x0000, 0x0000, 1024, 600, 16, 1, 128, 37,
+ MD_XGI300 },
+ {"1024x600x24", 0x22, 0x0000, 0x0000, 1024, 600, 32, 1, 128, 37,
+ MD_XGI300 },
+ {"1024x600x32", 0x22, 0x0000, 0x0000, 1024, 600, 32, 1, 128, 37,
+ MD_XGI300 },
+ {"1024x768x8", 0x38, 0x0105, 0x0105, 1024, 768, 8, 1, 128, 48,
+ MD_XGI300|MD_XGI315},
+ {"1024x768x16", 0x4A, 0x0117, 0x0117, 1024, 768, 16, 1, 128, 48,
+ MD_XGI300|MD_XGI315},
+ {"1024x768x24", 0x64, 0x013c, 0x0118, 1024, 768, 32, 1, 128, 48,
+ MD_XGI300|MD_XGI315},
+ {"1024x768x32", 0x64, 0x013c, 0x0118, 1024, 768, 32, 1, 128, 48,
+ MD_XGI300|MD_XGI315},
+ {"1152x768x8", 0x23, 0x0000, 0x0000, 1152, 768, 8, 1, 144, 48,
+ MD_XGI300 }, /* TW: 300 series only */
+ {"1152x768x16", 0x24, 0x0000, 0x0000, 1152, 768, 16, 1, 144, 48,
+ MD_XGI300 },
+ {"1152x768x24", 0x25, 0x0000, 0x0000, 1152, 768, 32, 1, 144, 48,
+ MD_XGI300 },
+ {"1152x768x32", 0x25, 0x0000, 0x0000, 1152, 768, 32, 1, 144, 48,
+ MD_XGI300 },
+ {"1280x720x8", 0x79, 0x0000, 0x0000, 1280, 720, 8, 1, 160, 45,
+ MD_XGI300|MD_XGI315},
+ {"1280x720x16", 0x75, 0x0000, 0x0000, 1280, 720, 16, 1, 160, 45,
+ MD_XGI300|MD_XGI315},
+ {"1280x720x24", 0x78, 0x0000, 0x0000, 1280, 720, 32, 1, 160, 45,
+ MD_XGI300|MD_XGI315},
+ {"1280x720x32", 0x78, 0x0000, 0x0000, 1280, 720, 32, 1, 160, 45,
+ MD_XGI300|MD_XGI315},
+ {"1280x768x8", 0x23, 0x0000, 0x0000, 1280, 768, 8, 1, 160, 48,
+ MD_XGI315}, /* TW: 310/325 series only */
+ {"1280x768x16", 0x24, 0x0000, 0x0000, 1280, 768, 16, 1, 160, 48,
+ MD_XGI315},
+ {"1280x768x24", 0x25, 0x0000, 0x0000, 1280, 768, 32, 1, 160, 48,
+ MD_XGI315},
+ {"1280x768x32", 0x25, 0x0000, 0x0000, 1280, 768, 32, 1, 160, 48,
+ MD_XGI315},
#define MODEINDEX_1280x960 48
- {"1280x960x8", 0x7C, 0x0000, 0x0000, 1280, 960, 8, 1, 160, 60, MD_XGI300|MD_XGI315}, /* TW: Modenumbers being patched */
- {"1280x960x16", 0x7D, 0x0000, 0x0000, 1280, 960, 16, 1, 160, 60, MD_XGI300|MD_XGI315},
- {"1280x960x24", 0x7E, 0x0000, 0x0000, 1280, 960, 32, 1, 160, 60, MD_XGI300|MD_XGI315},
- {"1280x960x32", 0x7E, 0x0000, 0x0000, 1280, 960, 32, 1, 160, 60, MD_XGI300|MD_XGI315},
- {"1280x1024x8", 0x3A, 0x0107, 0x0107, 1280, 1024, 8, 1, 160, 64, MD_XGI300|MD_XGI315},
- {"1280x1024x16", 0x4D, 0x011a, 0x011a, 1280, 1024, 16, 1, 160, 64, MD_XGI300|MD_XGI315},
- {"1280x1024x24", 0x65, 0x013d, 0x011b, 1280, 1024, 32, 1, 160, 64, MD_XGI300|MD_XGI315},
- {"1280x1024x32", 0x65, 0x013d, 0x011b, 1280, 1024, 32, 1, 160, 64, MD_XGI300|MD_XGI315},
- {"1400x1050x8", 0x26, 0x0000, 0x0000, 1400, 1050, 8, 1, 175, 65, MD_XGI315}, /* TW: 310/325 series only */
- {"1400x1050x16", 0x27, 0x0000, 0x0000, 1400, 1050, 16, 1, 175, 65, MD_XGI315},
- {"1400x1050x24", 0x28, 0x0000, 0x0000, 1400, 1050, 32, 1, 175, 65, MD_XGI315},
- {"1400x1050x32", 0x28, 0x0000, 0x0000, 1400, 1050, 32, 1, 175, 65, MD_XGI315},
- {"1600x1200x8", 0x3C, 0x0130, 0x011c, 1600, 1200, 8, 1, 200, 75, MD_XGI300|MD_XGI315},
- {"1600x1200x16", 0x3D, 0x0131, 0x011e, 1600, 1200, 16, 1, 200, 75, MD_XGI300|MD_XGI315},
- {"1600x1200x24", 0x66, 0x013e, 0x011f, 1600, 1200, 32, 1, 200, 75, MD_XGI300|MD_XGI315},
- {"1600x1200x32", 0x66, 0x013e, 0x011f, 1600, 1200, 32, 1, 200, 75, MD_XGI300|MD_XGI315},
- {"1920x1440x8", 0x68, 0x013f, 0x0000, 1920, 1440, 8, 1, 240, 75, MD_XGI300|MD_XGI315},
- {"1920x1440x16", 0x69, 0x0140, 0x0000, 1920, 1440, 16, 1, 240, 75, MD_XGI300|MD_XGI315},
- {"1920x1440x24", 0x6B, 0x0141, 0x0000, 1920, 1440, 32, 1, 240, 75, MD_XGI300|MD_XGI315},
- {"1920x1440x32", 0x6B, 0x0141, 0x0000, 1920, 1440, 32, 1, 240, 75, MD_XGI300|MD_XGI315},
- {"2048x1536x8", 0x6c, 0x0000, 0x0000, 2048, 1536, 8, 1, 256, 96, MD_XGI315}, /* TW: 310/325 series only */
- {"2048x1536x16", 0x6d, 0x0000, 0x0000, 2048, 1536, 16, 1, 256, 96, MD_XGI315},
- {"2048x1536x24", 0x6e, 0x0000, 0x0000, 2048, 1536, 32, 1, 256, 96, MD_XGI315},
- {"2048x1536x32", 0x6e, 0x0000, 0x0000, 2048, 1536, 32, 1, 256, 96, MD_XGI315},
+ {"1280x960x8", 0x7C, 0x0000, 0x0000, 1280, 960, 8, 1, 160, 60,
+ MD_XGI300|MD_XGI315}, /* TW: Modenumbers being patched */
+ {"1280x960x16", 0x7D, 0x0000, 0x0000, 1280, 960, 16, 1, 160, 60,
+ MD_XGI300|MD_XGI315},
+ {"1280x960x24", 0x7E, 0x0000, 0x0000, 1280, 960, 32, 1, 160, 60,
+ MD_XGI300|MD_XGI315},
+ {"1280x960x32", 0x7E, 0x0000, 0x0000, 1280, 960, 32, 1, 160, 60,
+ MD_XGI300|MD_XGI315},
+ {"1280x1024x8", 0x3A, 0x0107, 0x0107, 1280, 1024, 8, 1, 160, 64,
+ MD_XGI300|MD_XGI315},
+ {"1280x1024x16", 0x4D, 0x011a, 0x011a, 1280, 1024, 16, 1, 160, 64,
+ MD_XGI300|MD_XGI315},
+ {"1280x1024x24", 0x65, 0x013d, 0x011b, 1280, 1024, 32, 1, 160, 64,
+ MD_XGI300|MD_XGI315},
+ {"1280x1024x32", 0x65, 0x013d, 0x011b, 1280, 1024, 32, 1, 160, 64,
+ MD_XGI300|MD_XGI315},
+ {"1400x1050x8", 0x26, 0x0000, 0x0000, 1400, 1050, 8, 1, 175, 65,
+ MD_XGI315}, /* TW: 310/325 series only */
+ {"1400x1050x16", 0x27, 0x0000, 0x0000, 1400, 1050, 16, 1, 175, 65,
+ MD_XGI315},
+ {"1400x1050x24", 0x28, 0x0000, 0x0000, 1400, 1050, 32, 1, 175, 65,
+ MD_XGI315},
+ {"1400x1050x32", 0x28, 0x0000, 0x0000, 1400, 1050, 32, 1, 175, 65,
+ MD_XGI315},
+ {"1600x1200x8", 0x3C, 0x0130, 0x011c, 1600, 1200, 8, 1, 200, 75,
+ MD_XGI300|MD_XGI315},
+ {"1600x1200x16", 0x3D, 0x0131, 0x011e, 1600, 1200, 16, 1, 200, 75,
+ MD_XGI300|MD_XGI315},
+ {"1600x1200x24", 0x66, 0x013e, 0x011f, 1600, 1200, 32, 1, 200, 75,
+ MD_XGI300|MD_XGI315},
+ {"1600x1200x32", 0x66, 0x013e, 0x011f, 1600, 1200, 32, 1, 200, 75,
+ MD_XGI300|MD_XGI315},
+ {"1920x1440x8", 0x68, 0x013f, 0x0000, 1920, 1440, 8, 1, 240, 75,
+ MD_XGI300|MD_XGI315},
+ {"1920x1440x16", 0x69, 0x0140, 0x0000, 1920, 1440, 16, 1, 240, 75,
+ MD_XGI300|MD_XGI315},
+ {"1920x1440x24", 0x6B, 0x0141, 0x0000, 1920, 1440, 32, 1, 240, 75,
+ MD_XGI300|MD_XGI315},
+ {"1920x1440x32", 0x6B, 0x0141, 0x0000, 1920, 1440, 32, 1, 240, 75,
+ MD_XGI300|MD_XGI315},
+ {"2048x1536x8", 0x6c, 0x0000, 0x0000, 2048, 1536, 8, 1, 256, 96,
+ MD_XGI315}, /* TW: 310/325 series only */
+ {"2048x1536x16", 0x6d, 0x0000, 0x0000, 2048, 1536, 16, 1, 256, 96,
+ MD_XGI315},
+ {"2048x1536x24", 0x6e, 0x0000, 0x0000, 2048, 1536, 32, 1, 256, 96,
+ MD_XGI315},
+ {"2048x1536x32", 0x6e, 0x0000, 0x0000, 2048, 1536, 32, 1, 256, 96,
+ MD_XGI315},
{"\0", 0x00, 0, 0, 0, 0, 0, 0, 0}
};
@@ -437,44 +480,45 @@
#ifdef MODULE
static int xgifb_mode_idx = 1;
#else
-static int xgifb_mode_idx = -1; /* Use a default mode if we are inside the kernel */
+static int xgifb_mode_idx = -1; /* Use a default mode if we are
+ inside the kernel */
#endif
static u8 XGIfb_mode_no = 0;
static u8 XGIfb_rate_idx = 0;
/* TW: CR36 evaluation */
-static const unsigned short XGI300paneltype[] =
- { LCD_UNKNOWN, LCD_800x600, LCD_1024x768, LCD_1280x1024,
- LCD_1280x960, LCD_640x480, LCD_1024x600, LCD_1152x768,
- LCD_1024x768, LCD_1024x768, LCD_1024x768,
- LCD_1024x768, LCD_1024x768, LCD_1024x768, LCD_1024x768 };
+static const unsigned short XGI300paneltype[] = {
+ LCD_UNKNOWN, LCD_800x600, LCD_1024x768, LCD_1280x1024,
+ LCD_1280x960, LCD_640x480, LCD_1024x600, LCD_1152x768,
+ LCD_1024x768, LCD_1024x768, LCD_1024x768,
+ LCD_1024x768, LCD_1024x768, LCD_1024x768, LCD_1024x768};
-static const unsigned short XGI310paneltype[] =
- { LCD_UNKNOWN, LCD_800x600, LCD_1024x768, LCD_1280x1024,
- LCD_640x480, LCD_1024x600, LCD_1152x864, LCD_1280x960,
- LCD_1152x768, LCD_1400x1050,LCD_1280x768, LCD_1600x1200,
- LCD_1024x768, LCD_1024x768, LCD_1024x768 };
+static const unsigned short XGI310paneltype[] = {
+ LCD_UNKNOWN, LCD_800x600, LCD_1024x768, LCD_1280x1024,
+ LCD_640x480, LCD_1024x600, LCD_1152x864, LCD_1280x960,
+ LCD_1152x768, LCD_1400x1050, LCD_1280x768, LCD_1600x1200,
+ LCD_1024x768, LCD_1024x768, LCD_1024x768};
static const struct _XGI_crt2type {
char name[10];
int type_no;
int tvplug_no;
} XGI_crt2type[] = {
- {"NONE", 0, -1},
- {"LCD", DISPTYPE_LCD, -1},
- {"TV", DISPTYPE_TV, -1},
- {"VGA", DISPTYPE_CRT2, -1},
- {"SVIDEO", DISPTYPE_TV, TVPLUG_SVIDEO},
- {"COMPOSITE", DISPTYPE_TV, TVPLUG_COMPOSITE},
- {"SCART", DISPTYPE_TV, TVPLUG_SCART},
- {"none", 0, -1},
- {"lcd", DISPTYPE_LCD, -1},
- {"tv", DISPTYPE_TV, -1},
- {"vga", DISPTYPE_CRT2, -1},
- {"svideo", DISPTYPE_TV, TVPLUG_SVIDEO},
- {"composite", DISPTYPE_TV, TVPLUG_COMPOSITE},
- {"scart", DISPTYPE_TV, TVPLUG_SCART},
- {"\0", -1, -1}
+ {"NONE", 0, -1},
+ {"LCD", DISPTYPE_LCD, -1},
+ {"TV", DISPTYPE_TV, -1},
+ {"VGA", DISPTYPE_CRT2, -1},
+ {"SVIDEO", DISPTYPE_TV, TVPLUG_SVIDEO},
+ {"COMPOSITE", DISPTYPE_TV, TVPLUG_COMPOSITE},
+ {"SCART", DISPTYPE_TV, TVPLUG_SCART},
+ {"none", 0, -1},
+ {"lcd", DISPTYPE_LCD, -1},
+ {"tv", DISPTYPE_TV, -1},
+ {"vga", DISPTYPE_CRT2, -1},
+ {"svideo", DISPTYPE_TV, TVPLUG_SVIDEO},
+ {"composite", DISPTYPE_TV, TVPLUG_COMPOSITE},
+ {"scart", DISPTYPE_TV, TVPLUG_SCART},
+ {"\0", -1, -1}
};
/* TV standard */
@@ -482,11 +526,11 @@
char name[6];
int type_no;
} XGI_tvtype[] = {
- {"PAL", 1},
- {"NTSC", 2},
- {"pal", 1},
- {"ntsc", 2},
- {"\0", -1}
+ {"PAL", 1},
+ {"NTSC", 2},
+ {"pal", 1},
+ {"ntsc", 2},
+ {"\0", -1}
};
static const struct _XGI_vrate {
@@ -495,13 +539,19 @@
u16 yres;
u16 refresh;
} XGIfb_vrate[] = {
- {1, 640, 480, 60}, {2, 640, 480, 72}, {3, 640, 480, 75}, {4, 640, 480, 85},
- {5, 640, 480,100}, {6, 640, 480, 120}, {7, 640, 480, 160}, {8, 640, 480, 200},
+ {1, 640, 480, 60}, {2, 640, 480, 72},
+ {3, 640, 480, 75}, {4, 640, 480, 85},
+
+ {5, 640, 480, 100}, {6, 640, 480, 120},
+ {7, 640, 480, 160}, {8, 640, 480, 200},
+
{1, 720, 480, 60},
{1, 720, 576, 58},
{1, 800, 480, 60}, {2, 800, 480, 75}, {3, 800, 480, 85},
- {1, 800, 600, 60}, {2, 800, 600, 72}, {3, 800, 600, 75},
- {4, 800, 600, 85}, {5, 800, 600, 100}, {6, 800, 600, 120}, {7, 800, 600, 160},
+ {1, 800, 600, 60}, {2, 800, 600, 72}, {3, 800, 600, 75},
+ {4, 800, 600, 85}, {5, 800, 600, 100},
+ {6, 800, 600, 120}, {7, 800, 600, 160},
+
{1, 1024, 768, 60}, {2, 1024, 768, 70}, {3, 1024, 768, 75},
{4, 1024, 768, 85}, {5, 1024, 768, 100}, {6, 1024, 768, 120},
{1, 1024, 576, 60}, {2, 1024, 576, 75}, {3, 1024, 576, 85},
@@ -509,279 +559,187 @@
{1, 1152, 768, 60},
{1, 1280, 720, 60}, {2, 1280, 720, 75}, {3, 1280, 720, 85},
{1, 1280, 768, 60},
- {1, 1280, 1024, 60}, {2, 1280, 1024, 75}, {3, 1280, 1024, 85},
+ {1, 1280, 1024, 60}, {2, 1280, 1024, 75}, {3, 1280, 1024, 85},
{1, 1280, 960, 70},
{1, 1400, 1050, 60},
- {1, 1600, 1200, 60}, {2, 1600, 1200, 65}, {3, 1600, 1200, 70}, {4, 1600, 1200, 75},
- {5, 1600, 1200, 85}, {6, 1600, 1200, 100}, {7, 1600, 1200, 120},
- {1, 1920, 1440, 60}, {2, 1920, 1440, 65}, {3, 1920, 1440, 70}, {4, 1920, 1440, 75},
+ {1, 1600, 1200, 60}, {2, 1600, 1200, 65},
+ {3, 1600, 1200, 70}, {4, 1600, 1200, 75},
+
+ {5, 1600, 1200, 85}, {6, 1600, 1200, 100},
+ {7, 1600, 1200, 120},
+
+ {1, 1920, 1440, 60}, {2, 1920, 1440, 65},
+ {3, 1920, 1440, 70}, {4, 1920, 1440, 75},
+
{5, 1920, 1440, 85}, {6, 1920, 1440, 100},
- {1, 2048, 1536, 60}, {2, 2048, 1536, 65}, {3, 2048, 1536, 70}, {4, 2048, 1536, 75},
+ {1, 2048, 1536, 60}, {2, 2048, 1536, 65},
+ {3, 2048, 1536, 70}, {4, 2048, 1536, 75},
+
{5, 2048, 1536, 85},
{0, 0, 0, 0}
};
static const struct _chswtable {
- int subsysVendor;
- int subsysCard;
- char *vendorName;
- char *cardName;
+ int subsysVendor;
+ int subsysCard;
+ char *vendorName;
+ char *cardName;
} mychswtable[] = {
- { 0x1631, 0x1002, "Mitachi", "0x1002" },
+ { 0x1631, 0x1002, "Mitachi", "0x1002" },
{ 0, 0, "" , "" }
};
-// Eden Chen
+/* Eden Chen */
static const struct _XGI_TV_filter {
u8 filter[9][4];
} XGI_TV_filter[] = {
- { {{0x00,0x00,0x00,0x40}, /* NTSCFilter_0 */
- {0x00,0xE0,0x10,0x60},
- {0x00,0xEE,0x10,0x44},
- {0x00,0xF4,0x10,0x38},
- {0xF8,0xF4,0x18,0x38},
- {0xFC,0xFB,0x14,0x2A},
- {0x00,0x00,0x10,0x20},
- {0x00,0x04,0x10,0x18},
- {0xFF,0xFF,0xFF,0xFF} }},
- { {{0x00,0x00,0x00,0x40}, /* NTSCFilter_1 */
- {0x00,0xE0,0x10,0x60},
- {0x00,0xEE,0x10,0x44},
- {0x00,0xF4,0x10,0x38},
- {0xF8,0xF4,0x18,0x38},
- {0xFC,0xFB,0x14,0x2A},
- {0x00,0x00,0x10,0x20},
- {0x00,0x04,0x10,0x18},
- {0xFF,0xFF,0xFF,0xFF} }},
- { {{0x00,0x00,0x00,0x40}, /* NTSCFilter_2 */
- {0xF5,0xEE,0x1B,0x44},
- {0xF8,0xF4,0x18,0x38},
- {0xEB,0x04,0x25,0x18},
- {0xF1,0x05,0x1F,0x16},
- {0xF6,0x06,0x1A,0x14},
- {0xFA,0x06,0x16,0x14},
- {0x00,0x04,0x10,0x18},
- {0xFF,0xFF,0xFF,0xFF} }},
- { {{0x00,0x00,0x00,0x40}, /* NTSCFilter_3 */
- {0xF1,0x04,0x1F,0x18},
- {0xEE,0x0D,0x22,0x06},
- {0xF7,0x06,0x19,0x14},
- {0xF4,0x0B,0x1C,0x0A},
- {0xFA,0x07,0x16,0x12},
- {0xF9,0x0A,0x17,0x0C},
- {0x00,0x07,0x10,0x12},
- {0xFF,0xFF,0xFF,0xFF} }},
- { {{0x00,0x00,0x00,0x40}, /* NTSCFilter_4 */
- {0x00,0xE0,0x10,0x60},
- {0x00,0xEE,0x10,0x44},
- {0x00,0xF4,0x10,0x38},
- {0xF8,0xF4,0x18,0x38},
- {0xFC,0xFB,0x14,0x2A},
- {0x00,0x00,0x10,0x20},
- {0x00,0x04,0x10,0x18},
- {0xFF,0xFF,0xFF,0xFF} }},
- { {{0x00,0x00,0x00,0x40}, /* NTSCFilter_5 */
- {0xF5,0xEE,0x1B,0x44},
- {0xF8,0xF4,0x18,0x38},
- {0xEB,0x04,0x25,0x18},
- {0xF1,0x05,0x1F,0x16},
- {0xF6,0x06,0x1A,0x14},
- {0xFA,0x06,0x16,0x14},
- {0x00,0x04,0x10,0x18},
- {0xFF,0xFF,0xFF,0xFF} }},
- { {{0x00,0x00,0x00,0x40}, /* NTSCFilter_6 */
- {0xEB,0x04,0x25,0x18},
- {0xE7,0x0E,0x29,0x04},
- {0xEE,0x0C,0x22,0x08},
- {0xF6,0x0B,0x1A,0x0A},
- {0xF9,0x0A,0x17,0x0C},
- {0xFC,0x0A,0x14,0x0C},
- {0x00,0x08,0x10,0x10},
- {0xFF,0xFF,0xFF,0xFF} }},
- { {{0x00,0x00,0x00,0x40}, /* NTSCFilter_7 */
- {0xEC,0x02,0x24,0x1C},
- {0xF2,0x04,0x1E,0x18},
- {0xEB,0x15,0x25,0xF6},
- {0xF4,0x10,0x1C,0x00},
- {0xF8,0x0F,0x18,0x02},
- {0x00,0x04,0x10,0x18},
- {0x01,0x06,0x0F,0x14},
- {0xFF,0xFF,0xFF,0xFF} }},
- { {{0x00,0x00,0x00,0x40}, /* PALFilter_0 */
- {0x00,0xE0,0x10,0x60},
- {0x00,0xEE,0x10,0x44},
- {0x00,0xF4,0x10,0x38},
- {0xF8,0xF4,0x18,0x38},
- {0xFC,0xFB,0x14,0x2A},
- {0x00,0x00,0x10,0x20},
- {0x00,0x04,0x10,0x18},
- {0xFF,0xFF,0xFF,0xFF} }},
- { {{0x00,0x00,0x00,0x40}, /* PALFilter_1 */
- {0x00,0xE0,0x10,0x60},
- {0x00,0xEE,0x10,0x44},
- {0x00,0xF4,0x10,0x38},
- {0xF8,0xF4,0x18,0x38},
- {0xFC,0xFB,0x14,0x2A},
- {0x00,0x00,0x10,0x20},
- {0x00,0x04,0x10,0x18},
- {0xFF,0xFF,0xFF,0xFF} }},
- { {{0x00,0x00,0x00,0x40}, /* PALFilter_2 */
- {0xF5,0xEE,0x1B,0x44},
- {0xF8,0xF4,0x18,0x38},
- {0xF1,0xF7,0x01,0x32},
- {0xF5,0xFB,0x1B,0x2A},
- {0xF9,0xFF,0x17,0x22},
- {0xFB,0x01,0x15,0x1E},
- {0x00,0x04,0x10,0x18},
- {0xFF,0xFF,0xFF,0xFF} }},
- { {{0x00,0x00,0x00,0x40}, /* PALFilter_3 */
- {0xF5,0xFB,0x1B,0x2A},
- {0xEE,0xFE,0x22,0x24},
- {0xF3,0x00,0x1D,0x20},
- {0xF9,0x03,0x17,0x1A},
- {0xFB,0x02,0x14,0x1E},
- {0xFB,0x04,0x15,0x18},
- {0x00,0x06,0x10,0x14},
- {0xFF,0xFF,0xFF,0xFF} }},
- { {{0x00,0x00,0x00,0x40}, /* PALFilter_4 */
- {0x00,0xE0,0x10,0x60},
- {0x00,0xEE,0x10,0x44},
- {0x00,0xF4,0x10,0x38},
- {0xF8,0xF4,0x18,0x38},
- {0xFC,0xFB,0x14,0x2A},
- {0x00,0x00,0x10,0x20},
- {0x00,0x04,0x10,0x18},
- {0xFF,0xFF,0xFF,0xFF} }},
- { {{0x00,0x00,0x00,0x40}, /* PALFilter_5 */
- {0xF5,0xEE,0x1B,0x44},
- {0xF8,0xF4,0x18,0x38},
- {0xF1,0xF7,0x1F,0x32},
- {0xF5,0xFB,0x1B,0x2A},
- {0xF9,0xFF,0x17,0x22},
- {0xFB,0x01,0x15,0x1E},
- {0x00,0x04,0x10,0x18},
- {0xFF,0xFF,0xFF,0xFF} }},
- { {{0x00,0x00,0x00,0x40}, /* PALFilter_6 */
- {0xF5,0xEE,0x1B,0x2A},
- {0xEE,0xFE,0x22,0x24},
- {0xF3,0x00,0x1D,0x20},
- {0xF9,0x03,0x17,0x1A},
- {0xFB,0x02,0x14,0x1E},
- {0xFB,0x04,0x15,0x18},
- {0x00,0x06,0x10,0x14},
- {0xFF,0xFF,0xFF,0xFF} }},
- { {{0x00,0x00,0x00,0x40}, /* PALFilter_7 */
- {0xF5,0xEE,0x1B,0x44},
- {0xF8,0xF4,0x18,0x38},
- {0xFC,0xFB,0x14,0x2A},
- {0xEB,0x05,0x25,0x16},
- {0xF1,0x05,0x1F,0x16},
- {0xFA,0x07,0x16,0x12},
- {0x00,0x07,0x10,0x12},
- {0xFF,0xFF,0xFF,0xFF} }}
+ { { {0x00, 0x00, 0x00, 0x40}, /* NTSCFilter_0 */
+ {0x00, 0xE0, 0x10, 0x60},
+ {0x00, 0xEE, 0x10, 0x44},
+ {0x00, 0xF4, 0x10, 0x38},
+ {0xF8, 0xF4, 0x18, 0x38},
+ {0xFC, 0xFB, 0x14, 0x2A},
+ {0x00, 0x00, 0x10, 0x20},
+ {0x00, 0x04, 0x10, 0x18},
+ {0xFF, 0xFF, 0xFF, 0xFF} } },
+ { { {0x00, 0x00, 0x00, 0x40}, /* NTSCFilter_1 */
+ {0x00, 0xE0, 0x10, 0x60},
+ {0x00, 0xEE, 0x10, 0x44},
+ {0x00, 0xF4, 0x10, 0x38},
+ {0xF8, 0xF4, 0x18, 0x38},
+ {0xFC, 0xFB, 0x14, 0x2A},
+ {0x00, 0x00, 0x10, 0x20},
+ {0x00, 0x04, 0x10, 0x18},
+ {0xFF, 0xFF, 0xFF, 0xFF} } },
+ { { {0x00, 0x00, 0x00, 0x40}, /* NTSCFilter_2 */
+ {0xF5, 0xEE, 0x1B, 0x44},
+ {0xF8, 0xF4, 0x18, 0x38},
+ {0xEB, 0x04, 0x25, 0x18},
+ {0xF1, 0x05, 0x1F, 0x16},
+ {0xF6, 0x06, 0x1A, 0x14},
+ {0xFA, 0x06, 0x16, 0x14},
+ {0x00, 0x04, 0x10, 0x18},
+ {0xFF, 0xFF, 0xFF, 0xFF} } },
+ { { {0x00, 0x00, 0x00, 0x40}, /* NTSCFilter_3 */
+ {0xF1, 0x04, 0x1F, 0x18},
+ {0xEE, 0x0D, 0x22, 0x06},
+ {0xF7, 0x06, 0x19, 0x14},
+ {0xF4, 0x0B, 0x1C, 0x0A},
+ {0xFA, 0x07, 0x16, 0x12},
+ {0xF9, 0x0A, 0x17, 0x0C},
+ {0x00, 0x07, 0x10, 0x12},
+ {0xFF, 0xFF, 0xFF, 0xFF} } },
+ { { {0x00, 0x00, 0x00, 0x40}, /* NTSCFilter_4 */
+ {0x00, 0xE0, 0x10, 0x60},
+ {0x00, 0xEE, 0x10, 0x44},
+ {0x00, 0xF4, 0x10, 0x38},
+ {0xF8, 0xF4, 0x18, 0x38},
+ {0xFC, 0xFB, 0x14, 0x2A},
+ {0x00, 0x00, 0x10, 0x20},
+ {0x00, 0x04, 0x10, 0x18},
+ {0xFF, 0xFF, 0xFF, 0xFF} } },
+ { { {0x00, 0x00, 0x00, 0x40}, /* NTSCFilter_5 */
+ {0xF5, 0xEE, 0x1B, 0x44},
+ {0xF8, 0xF4, 0x18, 0x38},
+ {0xEB, 0x04, 0x25, 0x18},
+ {0xF1, 0x05, 0x1F, 0x16},
+ {0xF6, 0x06, 0x1A, 0x14},
+ {0xFA, 0x06, 0x16, 0x14},
+ {0x00, 0x04, 0x10, 0x18},
+ {0xFF, 0xFF, 0xFF, 0xFF} } },
+ { { {0x00, 0x00, 0x00, 0x40}, /* NTSCFilter_6 */
+ {0xEB, 0x04, 0x25, 0x18},
+ {0xE7, 0x0E, 0x29, 0x04},
+ {0xEE, 0x0C, 0x22, 0x08},
+ {0xF6, 0x0B, 0x1A, 0x0A},
+ {0xF9, 0x0A, 0x17, 0x0C},
+ {0xFC, 0x0A, 0x14, 0x0C},
+ {0x00, 0x08, 0x10, 0x10},
+ {0xFF, 0xFF, 0xFF, 0xFF} } },
+ { { {0x00, 0x00, 0x00, 0x40}, /* NTSCFilter_7 */
+ {0xEC, 0x02, 0x24, 0x1C},
+ {0xF2, 0x04, 0x1E, 0x18},
+ {0xEB, 0x15, 0x25, 0xF6},
+ {0xF4, 0x10, 0x1C, 0x00},
+ {0xF8, 0x0F, 0x18, 0x02},
+ {0x00, 0x04, 0x10, 0x18},
+ {0x01, 0x06, 0x0F, 0x14},
+ {0xFF, 0xFF, 0xFF, 0xFF} } },
+ { { {0x00, 0x00, 0x00, 0x40}, /* PALFilter_0 */
+ {0x00, 0xE0, 0x10, 0x60},
+ {0x00, 0xEE, 0x10, 0x44},
+ {0x00, 0xF4, 0x10, 0x38},
+ {0xF8, 0xF4, 0x18, 0x38},
+ {0xFC, 0xFB, 0x14, 0x2A},
+ {0x00, 0x00, 0x10, 0x20},
+ {0x00, 0x04, 0x10, 0x18},
+ {0xFF, 0xFF, 0xFF, 0xFF} } },
+ { { {0x00, 0x00, 0x00, 0x40}, /* PALFilter_1 */
+ {0x00, 0xE0, 0x10, 0x60},
+ {0x00, 0xEE, 0x10, 0x44},
+ {0x00, 0xF4, 0x10, 0x38},
+ {0xF8, 0xF4, 0x18, 0x38},
+ {0xFC, 0xFB, 0x14, 0x2A},
+ {0x00, 0x00, 0x10, 0x20},
+ {0x00, 0x04, 0x10, 0x18},
+ {0xFF, 0xFF, 0xFF, 0xFF} } },
+ { { {0x00, 0x00, 0x00, 0x40}, /* PALFilter_2 */
+ {0xF5, 0xEE, 0x1B, 0x44},
+ {0xF8, 0xF4, 0x18, 0x38},
+ {0xF1, 0xF7, 0x01, 0x32},
+ {0xF5, 0xFB, 0x1B, 0x2A},
+ {0xF9, 0xFF, 0x17, 0x22},
+ {0xFB, 0x01, 0x15, 0x1E},
+ {0x00, 0x04, 0x10, 0x18},
+ {0xFF, 0xFF, 0xFF, 0xFF} } },
+ { { {0x00, 0x00, 0x00, 0x40}, /* PALFilter_3 */
+ {0xF5, 0xFB, 0x1B, 0x2A},
+ {0xEE, 0xFE, 0x22, 0x24},
+ {0xF3, 0x00, 0x1D, 0x20},
+ {0xF9, 0x03, 0x17, 0x1A},
+ {0xFB, 0x02, 0x14, 0x1E},
+ {0xFB, 0x04, 0x15, 0x18},
+ {0x00, 0x06, 0x10, 0x14},
+ {0xFF, 0xFF, 0xFF, 0xFF} } },
+ { { {0x00, 0x00, 0x00, 0x40}, /* PALFilter_4 */
+ {0x00, 0xE0, 0x10, 0x60},
+ {0x00, 0xEE, 0x10, 0x44},
+ {0x00, 0xF4, 0x10, 0x38},
+ {0xF8, 0xF4, 0x18, 0x38},
+ {0xFC, 0xFB, 0x14, 0x2A},
+ {0x00, 0x00, 0x10, 0x20},
+ {0x00, 0x04, 0x10, 0x18},
+ {0xFF, 0xFF, 0xFF, 0xFF} } },
+ { { {0x00, 0x00, 0x00, 0x40}, /* PALFilter_5 */
+ {0xF5, 0xEE, 0x1B, 0x44},
+ {0xF8, 0xF4, 0x18, 0x38},
+ {0xF1, 0xF7, 0x1F, 0x32},
+ {0xF5, 0xFB, 0x1B, 0x2A},
+ {0xF9, 0xFF, 0x17, 0x22},
+ {0xFB, 0x01, 0x15, 0x1E},
+ {0x00, 0x04, 0x10, 0x18},
+ {0xFF, 0xFF, 0xFF, 0xFF} } },
+ { { {0x00, 0x00, 0x00, 0x40}, /* PALFilter_6 */
+ {0xF5, 0xEE, 0x1B, 0x2A},
+ {0xEE, 0xFE, 0x22, 0x24},
+ {0xF3, 0x00, 0x1D, 0x20},
+ {0xF9, 0x03, 0x17, 0x1A},
+ {0xFB, 0x02, 0x14, 0x1E},
+ {0xFB, 0x04, 0x15, 0x18},
+ {0x00, 0x06, 0x10, 0x14},
+ {0xFF, 0xFF, 0xFF, 0xFF} } },
+ { { {0x00, 0x00, 0x00, 0x40}, /* PALFilter_7 */
+ {0xF5, 0xEE, 0x1B, 0x44},
+ {0xF8, 0xF4, 0x18, 0x38},
+ {0xFC, 0xFB, 0x14, 0x2A},
+ {0xEB, 0x05, 0x25, 0x16},
+ {0xF1, 0x05, 0x1F, 0x16},
+ {0xFA, 0x07, 0x16, 0x12},
+ {0x00, 0x07, 0x10, 0x12},
+ {0xFF, 0xFF, 0xFF, 0xFF} } }
};
static int filter = -1;
static unsigned char filter_tb;
-
-/* ---------------------- Routine prototypes ------------------------- */
-
-/* Interface used by the world */
-#ifndef MODULE
-XGIINITSTATIC int __init XGIfb_setup(char *options);
-#endif
-
-/* Interface to the low level console driver */
-
-
-
-/* fbdev routines */
-XGIINITSTATIC int __init xgifb_init(void);
-static int XGIfb_set_par(struct fb_info *info);
-static int XGIfb_blank(int blank,
- struct fb_info *info);
-/*static int XGIfb_mmap(struct fb_info *info, struct file *file,
- struct vm_area_struct *vma);
-*/
-
-/*
-extern int XGIfb_mode_rate_to_dclock(VB_DEVICE_INFO *XGI_Pr,
- struct xgi_hw_device_info *HwDeviceExtension,
- unsigned char modeno, unsigned char rateindex);
-extern int XGIfb_mode_rate_to_ddata(VB_DEVICE_INFO *XGI_Pr, struct xgi_hw_device_info *HwDeviceExtension,
- unsigned char modeno, unsigned char rateindex,
- unsigned int *left_margin, unsigned int *right_margin,
- unsigned int *upper_margin, unsigned int *lower_margin,
- unsigned int *hsync_len, unsigned int *vsync_len,
- unsigned int *sync, unsigned int *vmode);
-*/
-extern unsigned char XGI_SearchModeID(unsigned short ModeNo,
- unsigned short *ModeIdIndex,
- struct vb_device_info *);
-static int XGIfb_get_fix(struct fb_fix_screeninfo *fix, int con,
- struct fb_info *info);
-
-/* Internal general routines */
-static void XGIfb_search_mode(const char *name);
-static int XGIfb_validate_mode(int modeindex);
-static u8 XGIfb_search_refresh_rate(unsigned int rate);
-static int XGIfb_setcolreg(unsigned regno, unsigned red, unsigned green,
- unsigned blue, unsigned transp,
- struct fb_info *fb_info);
-static int XGIfb_do_set_var(struct fb_var_screeninfo *var, int isactive,
- struct fb_info *info);
-static void XGIfb_pre_setmode(void);
-static void XGIfb_post_setmode(void);
-
-/* Internal hardware access routines */
-void XGIfb_set_reg4(u16 port, unsigned long data);
-u32 XGIfb_get_reg3(u16 port);
-
-/* Chipset-dependent internal routines */
-
-
-static int XGIfb_get_dram_size(void);
-static void XGIfb_detect_VB(void);
-static void XGIfb_get_VB_type(void);
-static int XGIfb_has_VB(void);
-
-
-/* Internal routines to access PCI configuration space */
-unsigned char XGIfb_query_VGA_config_space(struct xgi_hw_device_info *pXGIhw_ext,
- unsigned long offset,
- unsigned long set,
- unsigned long *value);
-//BOOLEAN XGIfb_query_north_bridge_space(PXGI_HW_DEVICE_INFO pXGIhw_ext,
-// unsigned long offset, unsigned long set, unsigned long *value);
-
-
-/* Routines from init.c/init301.c */
-extern void InitTo330Pointer(unsigned char, struct vb_device_info *pVBInfo);
-extern unsigned char XGIInitNew(struct xgi_hw_device_info *HwDeviceExtension);
-extern unsigned char XGISetModeNew(struct xgi_hw_device_info *HwDeviceExtension,
- unsigned short ModeNo);
-//extern void XGI_SetEnableDstn(VB_DEVICE_INFO *XGI_Pr);
-extern void XGI_LongWait(struct vb_device_info *XGI_Pr);
-extern unsigned short XGI_GetRatePtrCRT2(struct xgi_hw_device_info *pXGIHWDE,
- unsigned short ModeNo,
- unsigned short ModeIdIndex,
- struct vb_device_info *pVBInfo);
-/* TW: Chrontel TV functions */
-extern unsigned short XGI_GetCH700x(struct vb_device_info *XGI_Pr,
- unsigned short tempbx);
-extern void XGI_SetCH700x(struct vb_device_info *XGI_Pr, unsigned short tempbx);
-extern unsigned short XGI_GetCH701x(struct vb_device_info *XGI_Pr,
- unsigned short tempbx);
-extern void XGI_SetCH701x(struct vb_device_info *XGI_Pr, unsigned short tempbx);
-extern void XGI_SetCH70xxANDOR(struct vb_device_info *XGI_Pr,
- unsigned short tempax,
- unsigned short tempbh);
-extern void XGI_DDC2Delay(struct vb_device_info *XGI_Pr, unsigned short delaytime);
-
-/* TW: Sensing routines */
-void XGI_Sense30x(void);
-int XGIDoSense(int tempbl, int tempbh, int tempcl, int tempch);
-
-extern struct XGI21_LVDSCapStruct XGI21_LCDCapList[13];
#endif
diff --git a/drivers/staging/xgifb/XGI_main_26.c b/drivers/staging/xgifb/XGI_main_26.c
index 721bd25..cadec2a 100644
--- a/drivers/staging/xgifb/XGI_main_26.c
+++ b/drivers/staging/xgifb/XGI_main_26.c
@@ -33,7 +33,7 @@
#define XGIFB_PAN
#endif
-#include <asm/io.h>
+#include <linux/io.h>
#ifdef CONFIG_MTRR
#include <asm/mtrr.h>
#endif
@@ -41,7 +41,9 @@
#include "XGIfb.h"
#include "vgatypes.h"
#include "XGI_main.h"
+#include "vb_init.h"
#include "vb_util.h"
+#include "vb_setmode.h"
#define Index_CR_GPIO_Reg1 0x48
#define Index_CR_GPIO_Reg2 0x49
@@ -50,7 +52,6 @@
#define GPIOG_EN (1<<6)
#define GPIOG_WRITE (1<<6)
#define GPIOG_READ (1<<1)
-int XGIfb_GetXG21DefaultLVDSModeIdx(void);
#define XGIFB_ROM_SIZE 65536
@@ -69,69 +70,69 @@
{
u8 i, reg;
- outXGIIDXREG(XGISR, 0x05, 0x86);
+ xgifb_reg_set(XGISR, 0x05, 0x86);
/*
- outXGIIDXREG(XGISR, 0x08, 0x4f);
- outXGIIDXREG(XGISR, 0x0f, 0x20);
- outXGIIDXREG(XGISR, 0x11, 0x4f);
- outXGIIDXREG(XGISR, 0x13, 0x45);
- outXGIIDXREG(XGISR, 0x14, 0x51);
- outXGIIDXREG(XGISR, 0x1e, 0x41);
- outXGIIDXREG(XGISR, 0x1f, 0x0);
- outXGIIDXREG(XGISR, 0x20, 0xa1);
- outXGIIDXREG(XGISR, 0x22, 0xfb);
- outXGIIDXREG(XGISR, 0x26, 0x22);
- outXGIIDXREG(XGISR, 0x3e, 0x07);
+ xgifb_reg_set(XGISR, 0x08, 0x4f);
+ xgifb_reg_set(XGISR, 0x0f, 0x20);
+ xgifb_reg_set(XGISR, 0x11, 0x4f);
+ xgifb_reg_set(XGISR, 0x13, 0x45);
+ xgifb_reg_set(XGISR, 0x14, 0x51);
+ xgifb_reg_set(XGISR, 0x1e, 0x41);
+ xgifb_reg_set(XGISR, 0x1f, 0x0);
+ xgifb_reg_set(XGISR, 0x20, 0xa1);
+ xgifb_reg_set(XGISR, 0x22, 0xfb);
+ xgifb_reg_set(XGISR, 0x26, 0x22);
+ xgifb_reg_set(XGISR, 0x3e, 0x07);
*/
- /* outXGIIDXREG(XGICR, 0x19, 0x00); */
- /* outXGIIDXREG(XGICR, 0x1a, 0x3C); */
- /* outXGIIDXREG(XGICR, 0x22, 0xff); */
- /* outXGIIDXREG(XGICR, 0x3D, 0x10); */
+ /* xgifb_reg_set(XGICR, 0x19, 0x00); */
+ /* xgifb_reg_set(XGICR, 0x1a, 0x3C); */
+ /* xgifb_reg_set(XGICR, 0x22, 0xff); */
+ /* xgifb_reg_set(XGICR, 0x3D, 0x10); */
- /* outXGIIDXREG(XGICR, 0x4a, 0xf3); */
+ /* xgifb_reg_set(XGICR, 0x4a, 0xf3); */
- /* outXGIIDXREG(XGICR, 0x57, 0x0); */
- /* outXGIIDXREG(XGICR, 0x7a, 0x2c); */
+ /* xgifb_reg_set(XGICR, 0x57, 0x0); */
+ /* xgifb_reg_set(XGICR, 0x7a, 0x2c); */
- /* outXGIIDXREG(XGICR, 0x82, 0xcc); */
- /* outXGIIDXREG(XGICR, 0x8c, 0x0); */
+ /* xgifb_reg_set(XGICR, 0x82, 0xcc); */
+ /* xgifb_reg_set(XGICR, 0x8c, 0x0); */
/*
- outXGIIDXREG(XGICR, 0x99, 0x1);
- outXGIIDXREG(XGICR, 0x41, 0x40);
+ xgifb_reg_set(XGICR, 0x99, 0x1);
+ xgifb_reg_set(XGICR, 0x41, 0x40);
*/
for (i = 0; i < 0x4f; i++) {
- inXGIIDXREG(XGISR, i, reg);
+ reg = xgifb_reg_get(XGISR, i);
printk("\no 3c4 %x", i);
printk("\ni 3c5 => %x", reg);
}
for (i = 0; i < 0xF0; i++) {
- inXGIIDXREG(XGICR, i, reg);
+ reg = xgifb_reg_get(XGICR, i);
printk("\no 3d4 %x", i);
printk("\ni 3d5 => %x", reg);
}
/*
- outXGIIDXREG(XGIPART1,0x2F,1);
+ xgifb_reg_set(XGIPART1,0x2F,1);
for (i=1; i < 0x50; i++) {
- inXGIIDXREG(XGIPART1, i, reg);
+ reg = xgifb_reg_get(XGIPART1, i);
printk("\no d004 %x", i);
printk("\ni d005 => %x", reg);
}
for (i=0; i < 0x50; i++) {
- inXGIIDXREG(XGIPART2, i, reg);
+ reg = xgifb_reg_get(XGIPART2, i);
printk("\no d010 %x", i);
printk("\ni d011 => %x", reg);
}
for (i=0; i < 0x50; i++) {
- inXGIIDXREG(XGIPART3, i, reg);
+ reg = xgifb_reg_get(XGIPART3, i);
printk("\no d012 %x",i);
printk("\ni d013 => %x",reg);
}
for (i=0; i < 0x50; i++) {
- inXGIIDXREG(XGIPART4, i, reg);
+ reg = xgifb_reg_get(XGIPART4, i);
printk("\no d014 %x",i);
printk("\ni d015 => %x",reg);
}
@@ -348,10 +349,10 @@
else {
j = 0;
while (XGI_Pr->EModeIDTable[j].Ext_ModeID != 0xff) {
- if (XGI_Pr->EModeIDTable[j].Ext_ModeID
- == XGI_Pr->RefIndex[RefreshRateTableIndex].ModeID) {
- if (XGI_Pr->EModeIDTable[j].Ext_ModeFlag
- & DoubleScanMode) {
+ if (XGI_Pr->EModeIDTable[j].Ext_ModeID ==
+ XGI_Pr->RefIndex[RefreshRateTableIndex].ModeID) {
+ if (XGI_Pr->EModeIDTable[j].Ext_ModeFlag &
+ DoubleScanMode) {
*vmode = FB_VMODE_DOUBLE;
}
break;
@@ -377,30 +378,22 @@
XGI_Pr->P3c8 = BaseAddr + 0x18;
XGI_Pr->P3c9 = BaseAddr + 0x19;
XGI_Pr->P3da = BaseAddr + 0x2A;
- XGI_Pr->Part1Port = BaseAddr + XGI_CRT2_PORT_04; /* Digital video interface registers (LCD) */
- XGI_Pr->Part2Port = BaseAddr + XGI_CRT2_PORT_10; /* 301 TV Encoder registers */
- XGI_Pr->Part3Port = BaseAddr + XGI_CRT2_PORT_12; /* 301 Macrovision registers */
- XGI_Pr->Part4Port = BaseAddr + XGI_CRT2_PORT_14; /* 301 VGA2 (and LCD) registers */
- XGI_Pr->Part5Port = BaseAddr + XGI_CRT2_PORT_14 + 2; /* 301 palette address port registers */
+ /* Digital video interface registers (LCD) */
+ XGI_Pr->Part1Port = BaseAddr + XGI_CRT2_PORT_04;
+ /* 301 TV Encoder registers */
+ XGI_Pr->Part2Port = BaseAddr + XGI_CRT2_PORT_10;
+ /* 301 Macrovision registers */
+ XGI_Pr->Part3Port = BaseAddr + XGI_CRT2_PORT_12;
+ /* 301 VGA2 (and LCD) registers */
+ XGI_Pr->Part4Port = BaseAddr + XGI_CRT2_PORT_14;
+ /* 301 palette address port registers */
+ XGI_Pr->Part5Port = BaseAddr + XGI_CRT2_PORT_14 + 2;
}
-void XGIfb_set_reg4(u16 port, unsigned long data)
-{
- outl((u32)(data & 0xffffffff), port);
-}
-
-u32 XGIfb_get_reg3(u16 port)
-{
- u32 data;
-
- data = inl(port);
- return data;
-}
-
/* ------------ Interface for init & mode switching code ------------- */
-unsigned char XGIfb_query_VGA_config_space(
+static unsigned char XGIfb_query_VGA_config_space(
struct xgi_hw_device_info *pXGIhw_ext, unsigned long offset,
unsigned long set, unsigned long *value)
{
@@ -436,63 +429,35 @@
return 1;
}
-/*
-unsigned char XGIfb_query_north_bridge_space(struct xgi_hw_device_info *pXGIhw_ext,
- unsigned long offset, unsigned long set, unsigned long *value)
-{
- static struct pci_dev *pdev = NULL;
- static unsigned char init = 0, valid_pdev = 0;
- u16 nbridge_id = 0;
-
- if (!init) {
- init = 1;
- switch (xgi_video_info.chip) {
- case XGI_540:
- nbridge_id = PCI_DEVICE_ID_XG_540;
- break;
- case XGI_630:
- nbridge_id = PCI_DEVICE_ID_XG_630;
- break;
- case XGI_730:
- nbridge_id = PCI_DEVICE_ID_XG_730;
- break;
- case XGI_550:
- nbridge_id = PCI_DEVICE_ID_XG_550;
- break;
- case XGI_650:
- nbridge_id = PCI_DEVICE_ID_XG_650;
- break;
- case XGI_740:
- nbridge_id = PCI_DEVICE_ID_XG_740;
- break;
- default:
- nbridge_id = 0;
- break;
- }
-
- pdev = pci_get_device(PCI_VENDOR_ID_SI, nbridge_id, pdev);
- if (pdev) {
- valid_pdev = 1;
- pci_dev_put(pdev);
- }
- }
-
- if (!valid_pdev) {
- printk(KERN_DEBUG "XGIfb: Can't find XGI %d North Bridge device.\n",
- nbridge_id);
- return 0;
- }
-
- if (set == 0)
- pci_read_config_dword(pdev, offset, (u32 *)value);
- else
- pci_write_config_dword(pdev, offset, (u32)(*value));
-
- return 1;
-}
-*/
/* ------------------ Internal helper routines ----------------- */
+static int XGIfb_GetXG21DefaultLVDSModeIdx(void)
+{
+
+ int found_mode = 0;
+ int XGIfb_mode_idx = 0;
+
+ found_mode = 0;
+ while ((XGIbios_mode[XGIfb_mode_idx].mode_no != 0)
+ && (XGIbios_mode[XGIfb_mode_idx].xres
+ <= XGI21_LCDCapList[0].LVDSHDE)) {
+ if ((XGIbios_mode[XGIfb_mode_idx].xres
+ == XGI21_LCDCapList[0].LVDSHDE)
+ && (XGIbios_mode[XGIfb_mode_idx].yres
+ == XGI21_LCDCapList[0].LVDSVDE)
+ && (XGIbios_mode[XGIfb_mode_idx].bpp == 8)) {
+ XGIfb_mode_no = XGIbios_mode[XGIfb_mode_idx].mode_no;
+ found_mode = 1;
+ break;
+ }
+ XGIfb_mode_idx++;
+ }
+ if (!found_mode)
+ XGIfb_mode_idx = 0;
+
+ return XGIfb_mode_idx;
+}
+
static void XGIfb_search_mode(const char *name)
{
int i = 0, j = 0, l;
@@ -551,8 +516,8 @@
vesamode &= 0x1dff; /* Clean VESA mode number from other flags */
while (XGIbios_mode[i].mode_no != 0) {
- if ((XGIbios_mode[i].vesa_mode_no_1 == vesamode)
- || (XGIbios_mode[i].vesa_mode_no_2 == vesamode)) {
+ if ((XGIbios_mode[i].vesa_mode_no_1 == vesamode) ||
+ (XGIbios_mode[i].vesa_mode_no_2 == vesamode)) {
xgifb_mode_idx = i;
j = 1;
break;
@@ -569,11 +534,13 @@
unsigned char *pData;
int i, j, k;
- inXGIIDXREG(XGISR, 0x1e, tmp);
- outXGIIDXREG(XGISR, 0x1e, tmp | 4);
+ tmp = xgifb_reg_get(XGISR, 0x1e);
+ xgifb_reg_set(XGISR, 0x1e, tmp | 4);
pData = xgi_video_info.mmio_vbase + 0x20000;
- if ((pData[0x0] == 0x55) && (pData[0x1] == 0xAA) && (pData[0x65] & 0x1)) {
+ if ((pData[0x0] == 0x55) &&
+ (pData[0x1] == 0xAA) &&
+ (pData[0x65] & 0x1)) {
i = pData[0x316] | (pData[0x317] << 8);
j = pData[i - 1];
if (j == 0xff)
@@ -616,33 +583,6 @@
return 0;
}
-int XGIfb_GetXG21DefaultLVDSModeIdx(void)
-{
-
- int found_mode = 0;
- int XGIfb_mode_idx = 0;
-
- found_mode = 0;
- while ((XGIbios_mode[XGIfb_mode_idx].mode_no != 0)
- && (XGIbios_mode[XGIfb_mode_idx].xres
- <= XGI21_LCDCapList[0].LVDSHDE)) {
- if ((XGIbios_mode[XGIfb_mode_idx].xres
- == XGI21_LCDCapList[0].LVDSHDE)
- && (XGIbios_mode[XGIfb_mode_idx].yres
- == XGI21_LCDCapList[0].LVDSVDE)
- && (XGIbios_mode[XGIfb_mode_idx].bpp == 8)) {
- XGIfb_mode_no = XGIbios_mode[XGIfb_mode_idx].mode_no;
- found_mode = 1;
- break;
- }
- XGIfb_mode_idx++;
- }
- if (!found_mode)
- XGIfb_mode_idx = 0;
-
- return XGIfb_mode_idx;
-}
-
static int XGIfb_validate_mode(int myindex)
{
u16 xres, yres;
@@ -656,8 +596,8 @@
return -1;
if (XGIbios_mode[myindex].yres > yres)
return -1;
- if ((XGIbios_mode[myindex].xres < xres)
- && (XGIbios_mode[myindex].yres < yres)) {
+ if ((XGIbios_mode[myindex].xres < xres) &&
+ (XGIbios_mode[myindex].yres < yres)) {
if (XGIbios_mode[myindex].bpp > 8)
return -1;
}
@@ -733,7 +673,7 @@
if (XGIbios_mode[myindex].yres > yres)
return -1;
if ((XGIhw_ext.ulExternalChip == 0x01) || /* LVDS */
- (XGIhw_ext.ulExternalChip == 0x05)) { /* LVDS+Chrontel */
+ (XGIhw_ext.ulExternalChip == 0x05)) { /* LVDS+Chrontel */
switch (XGIbios_mode[myindex].xres) {
case 512:
if (XGIbios_mode[myindex].yres != 512)
@@ -752,13 +692,11 @@
return -1;
break;
case 1024:
- if ((XGIbios_mode[myindex].yres != 600)
- && (XGIbios_mode[myindex].yres
- != 768))
+ if ((XGIbios_mode[myindex].yres != 600) &&
+ (XGIbios_mode[myindex].yres != 768))
return -1;
- if ((XGIbios_mode[myindex].yres == 600)
- && (XGIhw_ext.ulCRT2LCDType
- != LCD_1024x600))
+ if ((XGIbios_mode[myindex].yres == 600) &&
+ (XGIhw_ext.ulCRT2LCDType != LCD_1024x600))
return -1;
break;
case 1152:
@@ -768,13 +706,11 @@
return -1;
break;
case 1280:
- if ((XGIbios_mode[myindex].yres != 768)
- && (XGIbios_mode[myindex].yres
- != 1024))
+ if ((XGIbios_mode[myindex].yres != 768) &&
+ (XGIbios_mode[myindex].yres != 1024))
return -1;
- if ((XGIbios_mode[myindex].yres == 768)
- && (XGIhw_ext.ulCRT2LCDType
- != LCD_1280x768))
+ if ((XGIbios_mode[myindex].yres == 768) &&
+ (XGIhw_ext.ulCRT2LCDType != LCD_1280x768))
return -1;
break;
case 1400:
@@ -795,9 +731,8 @@
return -1;
break;
case 640:
- if ((XGIbios_mode[myindex].yres != 400)
- && (XGIbios_mode[myindex].yres
- != 480))
+ if ((XGIbios_mode[myindex].yres != 400) &&
+ (XGIbios_mode[myindex].yres != 480))
return -1;
break;
case 800:
@@ -809,13 +744,12 @@
return -1;
break;
case 1280:
- if ((XGIbios_mode[myindex].yres != 960)
- && (XGIbios_mode[myindex].yres
- != 1024))
+ if ((XGIbios_mode[myindex].yres != 960) &&
+ (XGIbios_mode[myindex].yres != 1024))
return -1;
if (XGIbios_mode[myindex].yres == 960) {
- if (XGIhw_ext.ulCRT2LCDType
- == LCD_1400x1050)
+ if (XGIhw_ext.ulCRT2LCDType ==
+ LCD_1400x1050)
return -1;
}
break;
@@ -847,8 +781,8 @@
return -1;
}
/* TW: LVDS/CHRONTEL does not support 720 */
- if (xgi_video_info.hasVB == HASVB_LVDS_CHRONTEL
- || xgi_video_info.hasVB == HASVB_CHRONTEL) {
+ if (xgi_video_info.hasVB == HASVB_LVDS_CHRONTEL ||
+ xgi_video_info.hasVB == HASVB_CHRONTEL) {
return -1;
}
break;
@@ -900,31 +834,31 @@
XGIfb_rate_idx = 0;
while ((XGIfb_vrate[i].idx != 0) && (XGIfb_vrate[i].xres <= xres)) {
- if ((XGIfb_vrate[i].xres == xres) && (XGIfb_vrate[i].yres
- == yres)) {
+ if ((XGIfb_vrate[i].xres == xres) &&
+ (XGIfb_vrate[i].yres == yres)) {
if (XGIfb_vrate[i].refresh == rate) {
XGIfb_rate_idx = XGIfb_vrate[i].idx;
break;
} else if (XGIfb_vrate[i].refresh > rate) {
if ((XGIfb_vrate[i].refresh - rate) <= 3) {
DPRINTK("XGIfb: Adjusting rate from %d up to %d\n",
- rate, XGIfb_vrate[i].refresh);
+ rate, XGIfb_vrate[i].refresh);
XGIfb_rate_idx = XGIfb_vrate[i].idx;
- xgi_video_info.refresh_rate
- = XGIfb_vrate[i].refresh;
+ xgi_video_info.refresh_rate =
+ XGIfb_vrate[i].refresh;
} else if (((rate - XGIfb_vrate[i - 1].refresh)
<= 2) && (XGIfb_vrate[i].idx
!= 1)) {
DPRINTK("XGIfb: Adjusting rate from %d down to %d\n",
- rate, XGIfb_vrate[i-1].refresh);
+ rate, XGIfb_vrate[i-1].refresh);
XGIfb_rate_idx = XGIfb_vrate[i - 1].idx;
- xgi_video_info.refresh_rate
- = XGIfb_vrate[i - 1].refresh;
+ xgi_video_info.refresh_rate =
+ XGIfb_vrate[i - 1].refresh;
}
break;
} else if ((rate - XGIfb_vrate[i].refresh) <= 2) {
DPRINTK("XGIfb: Adjusting rate from %d down to %d\n",
- rate, XGIfb_vrate[i].refresh);
+ rate, XGIfb_vrate[i].refresh);
XGIfb_rate_idx = XGIfb_vrate[i].idx;
break;
}
@@ -934,8 +868,8 @@
if (XGIfb_rate_idx > 0) {
return XGIfb_rate_idx;
} else {
- printk(KERN_INFO
- "XGIfb: Unsupported rate %d for %dx%d\n", rate, xres, yres);
+ printk(KERN_INFO "XGIfb: Unsupported rate %d for %dx%d\n",
+ rate, xres, yres);
return 0;
}
}
@@ -991,6 +925,282 @@
}
}
+/* --------------------- SetMode routines ------------------------- */
+
+static void XGIfb_pre_setmode(void)
+{
+ u8 cr30 = 0, cr31 = 0;
+
+ cr31 = xgifb_reg_get(XGICR, 0x31);
+ cr31 &= ~0x60;
+
+ switch (xgi_video_info.disp_state & DISPTYPE_DISP2) {
+ case DISPTYPE_CRT2:
+ cr30 = (XGI_VB_OUTPUT_CRT2 | XGI_SIMULTANEOUS_VIEW_ENABLE);
+ cr31 |= XGI_DRIVER_MODE;
+ break;
+ case DISPTYPE_LCD:
+ cr30 = (XGI_VB_OUTPUT_LCD | XGI_SIMULTANEOUS_VIEW_ENABLE);
+ cr31 |= XGI_DRIVER_MODE;
+ break;
+ case DISPTYPE_TV:
+ if (xgi_video_info.TV_type == TVMODE_HIVISION)
+ cr30 = (XGI_VB_OUTPUT_HIVISION
+ | XGI_SIMULTANEOUS_VIEW_ENABLE);
+ else if (xgi_video_info.TV_plug == TVPLUG_SVIDEO)
+ cr30 = (XGI_VB_OUTPUT_SVIDEO
+ | XGI_SIMULTANEOUS_VIEW_ENABLE);
+ else if (xgi_video_info.TV_plug == TVPLUG_COMPOSITE)
+ cr30 = (XGI_VB_OUTPUT_COMPOSITE
+ | XGI_SIMULTANEOUS_VIEW_ENABLE);
+ else if (xgi_video_info.TV_plug == TVPLUG_SCART)
+ cr30 = (XGI_VB_OUTPUT_SCART
+ | XGI_SIMULTANEOUS_VIEW_ENABLE);
+ cr31 |= XGI_DRIVER_MODE;
+
+ if (XGIfb_tvmode == 1 || xgi_video_info.TV_type == TVMODE_PAL)
+ cr31 |= 0x01;
+ else
+ cr31 &= ~0x01;
+ break;
+ default: /* disable CRT2 */
+ cr30 = 0x00;
+ cr31 |= (XGI_DRIVER_MODE | XGI_VB_OUTPUT_DISABLE);
+ }
+
+ xgifb_reg_set(XGICR, IND_XGI_SCRATCH_REG_CR30, cr30);
+ xgifb_reg_set(XGICR, IND_XGI_SCRATCH_REG_CR31, cr31);
+ xgifb_reg_set(XGICR, IND_XGI_SCRATCH_REG_CR33, (XGIfb_rate_idx & 0x0F));
+}
+
+static void XGIfb_post_setmode(void)
+{
+ u8 reg;
+ unsigned char doit = 1;
+ /*
+ xgifb_reg_set(XGISR,IND_XGI_PASSWORD,XGI_PASSWORD);
+ xgifb_reg_set(XGICR, 0x13, 0x00);
+ xgifb_reg_and_or(XGISR,0x0E, 0xF0, 0x01);
+ *test*
+ */
+ if (xgi_video_info.video_bpp == 8) {
+ /* TW: We can't switch off CRT1 on LVDS/Chrontel
+ * in 8bpp Modes */
+ if ((xgi_video_info.hasVB == HASVB_LVDS) ||
+ (xgi_video_info.hasVB == HASVB_LVDS_CHRONTEL)) {
+ doit = 0;
+ }
+ /* TW: We can't switch off CRT1 on 301B-DH
+ * in 8bpp Modes if using LCD */
+ if (xgi_video_info.disp_state & DISPTYPE_LCD)
+ doit = 0;
+ }
+
+ /* TW: We can't switch off CRT1 if bridge is in slave mode */
+ if (xgi_video_info.hasVB != HASVB_NONE) {
+ reg = xgifb_reg_get(XGIPART1, 0x00);
+
+ if ((reg & 0x50) == 0x10)
+ doit = 0;
+
+ } else {
+ XGIfb_crt1off = 0;
+ }
+
+ reg = xgifb_reg_get(XGICR, 0x17);
+ if ((XGIfb_crt1off) && (doit))
+ reg &= ~0x80;
+ else
+ reg |= 0x80;
+ xgifb_reg_set(XGICR, 0x17, reg);
+
+ xgifb_reg_and(XGISR, IND_XGI_RAMDAC_CONTROL, ~0x04);
+
+ if ((xgi_video_info.disp_state & DISPTYPE_TV) && (xgi_video_info.hasVB
+ == HASVB_301)) {
+
+ reg = xgifb_reg_get(XGIPART4, 0x01);
+
+ if (reg < 0xB0) { /* Set filter for XGI301 */
+ switch (xgi_video_info.video_width) {
+ case 320:
+ filter_tb = (xgi_video_info.TV_type ==
+ TVMODE_NTSC) ? 4 : 12;
+ break;
+ case 640:
+ filter_tb = (xgi_video_info.TV_type ==
+ TVMODE_NTSC) ? 5 : 13;
+ break;
+ case 720:
+ filter_tb = (xgi_video_info.TV_type ==
+ TVMODE_NTSC) ? 6 : 14;
+ break;
+ case 800:
+ filter_tb = (xgi_video_info.TV_type ==
+ TVMODE_NTSC) ? 7 : 15;
+ break;
+ default:
+ filter = -1;
+ break;
+ }
+ xgifb_reg_or(XGIPART1, XGIfb_CRT2_write_enable, 0x01);
+
+ if (xgi_video_info.TV_type == TVMODE_NTSC) {
+
+ xgifb_reg_and(XGIPART2, 0x3a, 0x1f);
+
+ if (xgi_video_info.TV_plug == TVPLUG_SVIDEO) {
+
+ xgifb_reg_and(XGIPART2, 0x30, 0xdf);
+
+ } else if (xgi_video_info.TV_plug
+ == TVPLUG_COMPOSITE) {
+
+ xgifb_reg_or(XGIPART2, 0x30, 0x20);
+
+ switch (xgi_video_info.video_width) {
+ case 640:
+ xgifb_reg_set(XGIPART2,
+ 0x35,
+ 0xEB);
+ xgifb_reg_set(XGIPART2,
+ 0x36,
+ 0x04);
+ xgifb_reg_set(XGIPART2,
+ 0x37,
+ 0x25);
+ xgifb_reg_set(XGIPART2,
+ 0x38,
+ 0x18);
+ break;
+ case 720:
+ xgifb_reg_set(XGIPART2,
+ 0x35,
+ 0xEE);
+ xgifb_reg_set(XGIPART2,
+ 0x36,
+ 0x0C);
+ xgifb_reg_set(XGIPART2,
+ 0x37,
+ 0x22);
+ xgifb_reg_set(XGIPART2,
+ 0x38,
+ 0x08);
+ break;
+ case 800:
+ xgifb_reg_set(XGIPART2,
+ 0x35,
+ 0xEB);
+ xgifb_reg_set(XGIPART2,
+ 0x36,
+ 0x15);
+ xgifb_reg_set(XGIPART2,
+ 0x37,
+ 0x25);
+ xgifb_reg_set(XGIPART2,
+ 0x38,
+ 0xF6);
+ break;
+ }
+ }
+
+ } else if (xgi_video_info.TV_type == TVMODE_PAL) {
+
+ xgifb_reg_and(XGIPART2, 0x3A, 0x1F);
+
+ if (xgi_video_info.TV_plug == TVPLUG_SVIDEO) {
+
+ xgifb_reg_and(XGIPART2, 0x30, 0xDF);
+
+ } else if (xgi_video_info.TV_plug
+ == TVPLUG_COMPOSITE) {
+
+ xgifb_reg_or(XGIPART2, 0x30, 0x20);
+
+ switch (xgi_video_info.video_width) {
+ case 640:
+ xgifb_reg_set(XGIPART2,
+ 0x35,
+ 0xF1);
+ xgifb_reg_set(XGIPART2,
+ 0x36,
+ 0xF7);
+ xgifb_reg_set(XGIPART2,
+ 0x37,
+ 0x1F);
+ xgifb_reg_set(XGIPART2,
+ 0x38,
+ 0x32);
+ break;
+ case 720:
+ xgifb_reg_set(XGIPART2,
+ 0x35,
+ 0xF3);
+ xgifb_reg_set(XGIPART2,
+ 0x36,
+ 0x00);
+ xgifb_reg_set(XGIPART2,
+ 0x37,
+ 0x1D);
+ xgifb_reg_set(XGIPART2,
+ 0x38,
+ 0x20);
+ break;
+ case 800:
+ xgifb_reg_set(XGIPART2,
+ 0x35,
+ 0xFC);
+ xgifb_reg_set(XGIPART2,
+ 0x36,
+ 0xFB);
+ xgifb_reg_set(XGIPART2,
+ 0x37,
+ 0x14);
+ xgifb_reg_set(XGIPART2,
+ 0x38,
+ 0x2A);
+ break;
+ }
+ }
+ }
+
+ if ((filter >= 0) && (filter <= 7)) {
+ DPRINTK("FilterTable[%d]-%d: %02x %02x %02x %02x\n",
+ filter_tb, filter,
+ XGI_TV_filter[filter_tb].
+ filter[filter][0],
+ XGI_TV_filter[filter_tb].
+ filter[filter][1],
+ XGI_TV_filter[filter_tb].
+ filter[filter][2],
+ XGI_TV_filter[filter_tb].
+ filter[filter][3]
+ );
+ xgifb_reg_set(
+ XGIPART2,
+ 0x35,
+ (XGI_TV_filter[filter_tb].
+ filter[filter][0]));
+ xgifb_reg_set(
+ XGIPART2,
+ 0x36,
+ (XGI_TV_filter[filter_tb].
+ filter[filter][1]));
+ xgifb_reg_set(
+ XGIPART2,
+ 0x37,
+ (XGI_TV_filter[filter_tb].
+ filter[filter][2]));
+ xgifb_reg_set(
+ XGIPART2,
+ 0x38,
+ (XGI_TV_filter[filter_tb].
+ filter[filter][3]));
+ }
+ }
+ }
+}
+
static int XGIfb_do_set_var(struct fb_var_screeninfo *var, int isactive,
struct fb_info *info)
{
@@ -1039,7 +1249,10 @@
}
printk(KERN_DEBUG "XGIfb: Change mode to %dx%dx%d-%dHz\n",
- var->xres, var->yres, var->bits_per_pixel, xgi_video_info.refresh_rate);
+ var->xres,
+ var->yres,
+ var->bits_per_pixel,
+ xgi_video_info.refresh_rate);
old_mode = xgifb_mode_idx;
xgifb_mode_idx = 0;
@@ -1064,8 +1277,8 @@
xgifb_mode_idx = -1;
if (xgifb_mode_idx < 0) {
- printk(KERN_ERR "XGIfb: Mode %dx%dx%d not supported\n", var->xres,
- var->yres, var->bits_per_pixel);
+ printk(KERN_ERR "XGIfb: Mode %dx%dx%d not supported\n",
+ var->xres, var->yres, var->bits_per_pixel);
xgifb_mode_idx = old_mode;
return -EINVAL;
}
@@ -1079,16 +1292,19 @@
XGIfb_pre_setmode();
if (XGISetModeNew(&XGIhw_ext, XGIfb_mode_no) == 0) {
- printk(KERN_ERR "XGIfb: Setting mode[0x%x] failed\n", XGIfb_mode_no);
+ printk(KERN_ERR "XGIfb: Setting mode[0x%x] failed\n",
+ XGIfb_mode_no);
return -EINVAL;
}
info->fix.line_length = ((info->var.xres_virtual
* info->var.bits_per_pixel) >> 6);
- outXGIIDXREG(XGISR, IND_XGI_PASSWORD, XGI_PASSWORD);
+ xgifb_reg_set(XGISR, IND_XGI_PASSWORD, XGI_PASSWORD);
- outXGIIDXREG(XGICR, 0x13, (info->fix.line_length & 0x00ff));
- outXGIIDXREG(XGISR, 0x0E, (info->fix.line_length & 0xff00) >> 8);
+ xgifb_reg_set(XGICR, 0x13, (info->fix.line_length & 0x00ff));
+ xgifb_reg_set(XGISR,
+ 0x0E,
+ (info->fix.line_length & 0xff00) >> 8);
XGIfb_post_setmode();
@@ -1112,16 +1328,16 @@
xgi_video_info.XGI310_AccelDepth = 0x00000000;
xgi_video_info.video_cmap_len = 256;
#if defined(__powerpc__)
- inXGIIDXREG(XGICR, 0x4D, cr_data);
- outXGIIDXREG(XGICR, 0x4D, (cr_data & 0xE0));
+ cr_data = xgifb_reg_get(XGICR, 0x4D);
+ xgifb_reg_set(XGICR, 0x4D, (cr_data & 0xE0));
#endif
break;
case 16:
xgi_video_info.DstColor = 0x8000;
xgi_video_info.XGI310_AccelDepth = 0x00010000;
#if defined(__powerpc__)
- inXGIIDXREG(XGICR, 0x4D, cr_data);
- outXGIIDXREG(XGICR, 0x4D, ((cr_data & 0xE0) | 0x0B));
+ cr_data = xgifb_reg_get(XGICR, 0x4D);
+ xgifb_reg_set(XGICR, 0x4D, ((cr_data & 0xE0) | 0x0B));
#endif
xgi_video_info.video_cmap_len = 16;
break;
@@ -1130,13 +1346,14 @@
xgi_video_info.XGI310_AccelDepth = 0x00020000;
xgi_video_info.video_cmap_len = 16;
#if defined(__powerpc__)
- inXGIIDXREG(XGICR, 0x4D, cr_data);
- outXGIIDXREG(XGICR, 0x4D, ((cr_data & 0xE0) | 0x15));
+ cr_data = xgifb_reg_get(XGICR, 0x4D);
+ xgifb_reg_set(XGICR, 0x4D, ((cr_data & 0xE0) | 0x15));
#endif
break;
default:
xgi_video_info.video_cmap_len = 16;
- printk(KERN_ERR "XGIfb: Unsupported depth %d", xgi_video_info.video_bpp);
+ printk(KERN_ERR "XGIfb: Unsupported depth %d",
+ xgi_video_info.video_bpp);
break;
}
}
@@ -1179,20 +1396,23 @@
break;
}
- outXGIIDXREG(XGISR, IND_XGI_PASSWORD, XGI_PASSWORD);
+ xgifb_reg_set(XGISR, IND_XGI_PASSWORD, XGI_PASSWORD);
- outXGIIDXREG(XGICR, 0x0D, base & 0xFF);
- outXGIIDXREG(XGICR, 0x0C, (base >> 8) & 0xFF);
- outXGIIDXREG(XGISR, 0x0D, (base >> 16) & 0xFF);
- outXGIIDXREG(XGISR, 0x37, (base >> 24) & 0x03);
- setXGIIDXREG(XGISR, 0x37, 0xDF, (base >> 21) & 0x04);
+ xgifb_reg_set(XGICR, 0x0D, base & 0xFF);
+ xgifb_reg_set(XGICR, 0x0C, (base >> 8) & 0xFF);
+ xgifb_reg_set(XGISR, 0x0D, (base >> 16) & 0xFF);
+ xgifb_reg_set(XGISR, 0x37, (base >> 24) & 0x03);
+ xgifb_reg_and_or(XGISR, 0x37, 0xDF, (base >> 21) & 0x04);
if (xgi_video_info.disp_state & DISPTYPE_DISP2) {
- orXGIIDXREG(XGIPART1, XGIfb_CRT2_write_enable, 0x01);
- outXGIIDXREG(XGIPART1, 0x06, (base & 0xFF));
- outXGIIDXREG(XGIPART1, 0x05, ((base >> 8) & 0xFF));
- outXGIIDXREG(XGIPART1, 0x04, ((base >> 16) & 0xFF));
- setXGIIDXREG(XGIPART1, 0x02, 0x7F, ((base >> 24) & 0x01) << 7);
+ xgifb_reg_or(XGIPART1, XGIfb_CRT2_write_enable, 0x01);
+ xgifb_reg_set(XGIPART1, 0x06, (base & 0xFF));
+ xgifb_reg_set(XGIPART1, 0x05, ((base >> 8) & 0xFF));
+ xgifb_reg_set(XGIPART1, 0x04, ((base >> 16) & 0xFF));
+ xgifb_reg_and_or(XGIPART1,
+ 0x02,
+ 0x7F,
+ ((base >> 24) & 0x01) << 7);
}
/* printk("End of pan_var"); */
return 0;
@@ -1235,15 +1455,15 @@
switch (info->var.bits_per_pixel) {
case 8:
- outXGIREG(XGIDACA, regno);
- outXGIREG(XGIDACD, (red >> 10));
- outXGIREG(XGIDACD, (green >> 10));
- outXGIREG(XGIDACD, (blue >> 10));
+ outb(regno, XGIDACA);
+ outb((red >> 10), XGIDACD);
+ outb((green >> 10), XGIDACD);
+ outb((blue >> 10), XGIDACD);
if (xgi_video_info.disp_state & DISPTYPE_DISP2) {
- outXGIREG(XGIDAC2A, regno);
- outXGIREG(XGIDAC2D, (red >> 8));
- outXGIREG(XGIDAC2D, (green >> 8));
- outXGIREG(XGIDAC2D, (blue >> 8));
+ outb(regno, XGIDAC2A);
+ outb((red >> 8), XGIDAC2D);
+ outb((green >> 8), XGIDAC2D);
+ outb((blue >> 8), XGIDAC2D);
}
break;
case 16:
@@ -1262,6 +1482,41 @@
return 0;
}
+/* ----------- FBDev related routines for all series ---------- */
+
+static int XGIfb_get_fix(struct fb_fix_screeninfo *fix, int con,
+ struct fb_info *info)
+{
+ DEBUGPRN("inside get_fix");
+ memset(fix, 0, sizeof(struct fb_fix_screeninfo));
+
+ strcpy(fix->id, myid);
+
+ fix->smem_start = xgi_video_info.video_base;
+
+ fix->smem_len = xgi_video_info.video_size;
+
+ fix->type = video_type;
+ fix->type_aux = 0;
+ if (xgi_video_info.video_bpp == 8)
+ fix->visual = FB_VISUAL_PSEUDOCOLOR;
+ else
+ fix->visual = FB_VISUAL_DIRECTCOLOR;
+ fix->xpanstep = 0;
+#ifdef XGIFB_PAN
+ if (XGIfb_ypan)
+ fix->ypanstep = 1;
+#endif
+ fix->ywrapstep = 0;
+ fix->line_length = xgi_video_info.video_linelength;
+ fix->mmio_start = xgi_video_info.mmio_base;
+ fix->mmio_len = xgi_video_info.mmio_size;
+ fix->accel = FB_ACCEL_XGI_XABRE;
+
+ DEBUGPRN("end of get_fix");
+ return 0;
+}
+
static int XGIfb_set_par(struct fb_info *info)
{
int err;
@@ -1307,7 +1562,8 @@
if (var->pixclock && htotal && vtotal) {
drate = 1000000000 / var->pixclock;
hrate = (drate * 1000) / htotal;
- xgi_video_info.refresh_rate = (unsigned int) (hrate * 2 / vtotal);
+ xgi_video_info.refresh_rate =
+ (unsigned int) (hrate * 2 / vtotal);
printk(KERN_DEBUG
"%s: pixclock = %d ,htotal=%d, vtotal=%d\n"
"%s: drate=%d, hrate=%d, refresh_rate=%d\n",
@@ -1350,10 +1606,10 @@
var->xres, var->yres, var->bits_per_pixel);
search_idx = 0;
while (XGIbios_mode[search_idx].mode_no != 0) {
-
if ((var->xres <= XGIbios_mode[search_idx].xres) &&
- (var->yres <= XGIbios_mode[search_idx].yres) &&
- (var->bits_per_pixel == XGIbios_mode[search_idx].bpp)) {
+ (var->yres <= XGIbios_mode[search_idx].yres) &&
+ (var->bits_per_pixel ==
+ XGIbios_mode[search_idx].bpp)) {
if (XGIfb_validate_mode(search_idx) > 0) {
found_mode = 1;
break;
@@ -1393,7 +1649,8 @@
} /* else { */
/* TW: Now patch yres_virtual if we use panning */
/* May I do this? */
- /* var->yres_virtual = xgi_video_info.heapstart / (var->xres * (var->bits_per_pixel >> 3)); */
+ /* var->yres_virtual = xgi_video_info.heapstart /
+ (var->xres * (var->bits_per_pixel >> 3)); */
/* if (var->yres_virtual <= var->yres) { */
/* TW: Paranoia check */
/* var->yres_virtual = var->yres; */
@@ -1460,51 +1717,16 @@
{
u8 reg;
- inXGIIDXREG(XGICR, 0x17, reg);
+ reg = xgifb_reg_get(XGICR, 0x17);
if (blank > 0)
reg &= 0x7f;
else
reg |= 0x80;
- outXGIIDXREG(XGICR, 0x17, reg);
- outXGIIDXREG(XGISR, 0x00, 0x01); /* Synchronous Reset */
- outXGIIDXREG(XGISR, 0x00, 0x03); /* End Reset */
- return 0;
-}
-
-/* ----------- FBDev related routines for all series ---------- */
-
-static int XGIfb_get_fix(struct fb_fix_screeninfo *fix, int con,
- struct fb_info *info)
-{
- DEBUGPRN("inside get_fix");
- memset(fix, 0, sizeof(struct fb_fix_screeninfo));
-
- strcpy(fix->id, myid);
-
- fix->smem_start = xgi_video_info.video_base;
-
- fix->smem_len = xgi_video_info.video_size;
-
- fix->type = video_type;
- fix->type_aux = 0;
- if (xgi_video_info.video_bpp == 8)
- fix->visual = FB_VISUAL_PSEUDOCOLOR;
- else
- fix->visual = FB_VISUAL_DIRECTCOLOR;
- fix->xpanstep = 0;
-#ifdef XGIFB_PAN
- if (XGIfb_ypan)
- fix->ypanstep = 1;
-#endif
- fix->ywrapstep = 0;
- fix->line_length = xgi_video_info.video_linelength;
- fix->mmio_start = xgi_video_info.mmio_base;
- fix->mmio_len = xgi_video_info.mmio_size;
- fix->accel = FB_ACCEL_XGI_XABRE;
-
- DEBUGPRN("end of get_fix");
+ xgifb_reg_set(XGICR, 0x17, reg);
+ xgifb_reg_set(XGISR, 0x00, 0x01); /* Synchronous Reset */
+ xgifb_reg_set(XGISR, 0x00, 0x03); /* End Reset */
return 0;
}
@@ -1537,9 +1759,9 @@
/* xorg driver sets 32MB * 1 channel */
if (xgi_video_info.chip == XG27)
- outXGIIDXREG(XGISR, IND_XGI_DRAM_SIZE, 0x51);
+ xgifb_reg_set(XGISR, IND_XGI_DRAM_SIZE, 0x51);
- inXGIIDXREG(XGISR, IND_XGI_DRAM_SIZE, reg);
+ reg = xgifb_reg_get(XGISR, IND_XGI_DRAM_SIZE);
switch ((reg & XGI_DRAM_SIZE_MASK) >> 4) {
case XGI_DRAM_SIZE_1MB:
xgi_video_info.video_size = 0x100000;
@@ -1614,8 +1836,9 @@
/* xgi_video_info.video_size = 0x200000; */ /* 1024x768x16 */
/* xgi_video_info.video_size = 0x1000000; */ /* benchmark */
- printk("XGIfb: SR14=%x DramSzie %x ChannelNum %x\n", reg,
- xgi_video_info.video_size, ChannelNum);
+ printk("XGIfb: SR14=%x DramSzie %x ChannelNum %x\n",
+ reg,
+ xgi_video_info.video_size, ChannelNum);
return 0;
}
@@ -1636,7 +1859,7 @@
break;
}
- inXGIIDXREG(XGICR, IND_XGI_SCRATCH_REG_CR32, cr32);
+ cr32 = xgifb_reg_get(XGICR, IND_XGI_SCRATCH_REG_CR32);
if ((cr32 & XGI_CRT1) && !XGIfb_crt1off)
XGIfb_crt1off = 0;
@@ -1673,7 +1896,7 @@
xgi_video_info.TV_plug = TVPLUG_SCART;
if (xgi_video_info.TV_type == 0) {
- inXGIIDXREG(XGICR, 0x38, temp);
+ temp = xgifb_reg_get(XGICR, 0x38);
if (temp & 0x10)
xgi_video_info.TV_type = TVMODE_PAL;
else
@@ -1689,30 +1912,11 @@
}
}
-static void XGIfb_get_VB_type(void)
-{
- u8 reg;
-
- if (!XGIfb_has_VB()) {
- inXGIIDXREG(XGICR, IND_XGI_SCRATCH_REG_CR37, reg);
- switch ((reg & XGI_EXTERNAL_CHIP_MASK) >> 1) {
- case XGI310_EXTERNAL_CHIP_LVDS:
- xgi_video_info.hasVB = HASVB_LVDS;
- break;
- case XGI310_EXTERNAL_CHIP_LVDS_CHRONTEL:
- xgi_video_info.hasVB = HASVB_LVDS_CHRONTEL;
- break;
- default:
- break;
- }
- }
-}
-
static int XGIfb_has_VB(void)
{
u8 vb_chipid;
- inXGIIDXREG(XGIPART4, 0x00, vb_chipid);
+ vb_chipid = xgifb_reg_get(XGIPART4, 0x00);
switch (vb_chipid) {
case 0x01:
xgi_video_info.hasVB = HASVB_301;
@@ -1727,344 +1931,23 @@
return 1;
}
-/* ------------------ Sensing routines ------------------ */
-
-/* TW: Determine and detect attached devices on XGI30x */
-int XGIDoSense(int tempbl, int tempbh, int tempcl, int tempch)
-{
- int temp, i;
-
- outXGIIDXREG(XGIPART4, 0x11, tempbl);
- temp = tempbh | tempcl;
- setXGIIDXREG(XGIPART4, 0x10, 0xe0, temp);
- for (i = 0; i < 10; i++)
- XGI_LongWait(&XGI_Pr);
- tempch &= 0x7f;
- inXGIIDXREG(XGIPART4, 0x03, temp);
- temp ^= 0x0e;
- temp &= tempch;
- return temp;
-}
-
-void XGI_Sense30x(void)
-{
- u8 backupP4_0d;
- u8 testsvhs_tempbl, testsvhs_tempbh;
- u8 testsvhs_tempcl, testsvhs_tempch;
- u8 testcvbs_tempbl, testcvbs_tempbh;
- u8 testcvbs_tempcl, testcvbs_tempch;
- u8 testvga2_tempbl, testvga2_tempbh;
- u8 testvga2_tempcl, testvga2_tempch;
- int myflag, result;
-
- inXGIIDXREG(XGIPART4, 0x0d, backupP4_0d);
- outXGIIDXREG(XGIPART4, 0x0d, (backupP4_0d | 0x04));
-
- testvga2_tempbh = 0x00;
- testvga2_tempbl = 0xd1;
- testsvhs_tempbh = 0x00;
- testsvhs_tempbl = 0xb9;
- testcvbs_tempbh = 0x00;
- testcvbs_tempbl = 0xb3;
- if ((XGIhw_ext.ujVBChipID != VB_CHIP_301) && (XGIhw_ext.ujVBChipID
- != VB_CHIP_302)) {
- testvga2_tempbh = 0x01;
- testvga2_tempbl = 0x90;
- testsvhs_tempbh = 0x01;
- testsvhs_tempbl = 0x6b;
- testcvbs_tempbh = 0x01;
- testcvbs_tempbl = 0x74;
- if (XGIhw_ext.ujVBChipID == VB_CHIP_301LV
- || XGIhw_ext.ujVBChipID == VB_CHIP_302LV) {
- testvga2_tempbh = 0x00;
- testvga2_tempbl = 0x00;
- testsvhs_tempbh = 0x02;
- testsvhs_tempbl = 0x00;
- testcvbs_tempbh = 0x01;
- testcvbs_tempbl = 0x00;
- }
- }
- if (XGIhw_ext.ujVBChipID != VB_CHIP_301LV && XGIhw_ext.ujVBChipID
- != VB_CHIP_302LV) {
- inXGIIDXREG(XGIPART4, 0x01, myflag);
- if (myflag & 0x04) {
- testvga2_tempbh = 0x00;
- testvga2_tempbl = 0xfd;
- testsvhs_tempbh = 0x00;
- testsvhs_tempbl = 0xdd;
- testcvbs_tempbh = 0x00;
- testcvbs_tempbl = 0xee;
- }
- }
- if ((XGIhw_ext.ujVBChipID == VB_CHIP_301LV) || (XGIhw_ext.ujVBChipID
- == VB_CHIP_302LV)) {
- testvga2_tempbh = 0x00;
- testvga2_tempbl = 0x00;
- testvga2_tempch = 0x00;
- testvga2_tempcl = 0x00;
- testsvhs_tempch = 0x04;
- testsvhs_tempcl = 0x08;
- testcvbs_tempch = 0x08;
- testcvbs_tempcl = 0x08;
- } else {
- testvga2_tempch = 0x0e;
- testvga2_tempcl = 0x08;
- testsvhs_tempch = 0x06;
- testsvhs_tempcl = 0x04;
- testcvbs_tempch = 0x08;
- testcvbs_tempcl = 0x04;
- }
-
- if (testvga2_tempch || testvga2_tempcl || testvga2_tempbh
- || testvga2_tempbl) {
- result = XGIDoSense(testvga2_tempbl, testvga2_tempbh,
- testvga2_tempcl, testvga2_tempch);
- if (result) {
- printk(KERN_INFO "XGIfb: Detected secondary VGA connection\n");
- orXGIIDXREG(XGICR, 0x32, 0x10);
- }
- }
-
- result = XGIDoSense(testsvhs_tempbl, testsvhs_tempbh, testsvhs_tempcl,
- testsvhs_tempch);
- if (result) {
- printk(KERN_INFO "XGIfb: Detected TV connected to SVHS output\n");
- /* TW: So we can be sure that there IS a SVHS output */
- xgi_video_info.TV_plug = TVPLUG_SVIDEO;
- orXGIIDXREG(XGICR, 0x32, 0x02);
- }
-
- if (!result) {
- result = XGIDoSense(testcvbs_tempbl, testcvbs_tempbh,
- testcvbs_tempcl, testcvbs_tempch);
- if (result) {
- printk(KERN_INFO "XGIfb: Detected TV connected to CVBS output\n");
- /* TW: So we can be sure that there IS a CVBS output */
- xgi_video_info.TV_plug = TVPLUG_COMPOSITE;
- orXGIIDXREG(XGICR, 0x32, 0x01);
- }
- }
- XGIDoSense(0, 0, 0, 0);
-
- outXGIIDXREG(XGIPART4, 0x0d, backupP4_0d);
-}
-
-/* --------------------- SetMode routines ------------------------- */
-
-static void XGIfb_pre_setmode(void)
-{
- u8 cr30 = 0, cr31 = 0;
-
- inXGIIDXREG(XGICR, 0x31, cr31);
- cr31 &= ~0x60;
-
- switch (xgi_video_info.disp_state & DISPTYPE_DISP2) {
- case DISPTYPE_CRT2:
- cr30 = (XGI_VB_OUTPUT_CRT2 | XGI_SIMULTANEOUS_VIEW_ENABLE);
- cr31 |= XGI_DRIVER_MODE;
- break;
- case DISPTYPE_LCD:
- cr30 = (XGI_VB_OUTPUT_LCD | XGI_SIMULTANEOUS_VIEW_ENABLE);
- cr31 |= XGI_DRIVER_MODE;
- break;
- case DISPTYPE_TV:
- if (xgi_video_info.TV_type == TVMODE_HIVISION)
- cr30 = (XGI_VB_OUTPUT_HIVISION
- | XGI_SIMULTANEOUS_VIEW_ENABLE);
- else if (xgi_video_info.TV_plug == TVPLUG_SVIDEO)
- cr30 = (XGI_VB_OUTPUT_SVIDEO
- | XGI_SIMULTANEOUS_VIEW_ENABLE);
- else if (xgi_video_info.TV_plug == TVPLUG_COMPOSITE)
- cr30 = (XGI_VB_OUTPUT_COMPOSITE
- | XGI_SIMULTANEOUS_VIEW_ENABLE);
- else if (xgi_video_info.TV_plug == TVPLUG_SCART)
- cr30 = (XGI_VB_OUTPUT_SCART
- | XGI_SIMULTANEOUS_VIEW_ENABLE);
- cr31 |= XGI_DRIVER_MODE;
-
- if (XGIfb_tvmode == 1 || xgi_video_info.TV_type == TVMODE_PAL)
- cr31 |= 0x01;
- else
- cr31 &= ~0x01;
- break;
- default: /* disable CRT2 */
- cr30 = 0x00;
- cr31 |= (XGI_DRIVER_MODE | XGI_VB_OUTPUT_DISABLE);
- }
-
- outXGIIDXREG(XGICR, IND_XGI_SCRATCH_REG_CR30, cr30);
- outXGIIDXREG(XGICR, IND_XGI_SCRATCH_REG_CR31, cr31);
- outXGIIDXREG(XGICR, IND_XGI_SCRATCH_REG_CR33, (XGIfb_rate_idx & 0x0F));
-}
-
-static void XGIfb_post_setmode(void)
+static void XGIfb_get_VB_type(void)
{
u8 reg;
- unsigned char doit = 1;
- /*
- outXGIIDXREG(XGISR,IND_XGI_PASSWORD,XGI_PASSWORD);
- outXGIIDXREG(XGICR, 0x13, 0x00);
- setXGIIDXREG(XGISR,0x0E, 0xF0, 0x01);
- *test*
- */
- if (xgi_video_info.video_bpp == 8) {
- /* TW: We can't switch off CRT1 on LVDS/Chrontel in 8bpp Modes */
- if ((xgi_video_info.hasVB == HASVB_LVDS)
- || (xgi_video_info.hasVB == HASVB_LVDS_CHRONTEL)) {
- doit = 0;
+
+ if (!XGIfb_has_VB()) {
+ reg = xgifb_reg_get(XGICR, IND_XGI_SCRATCH_REG_CR37);
+ switch ((reg & XGI_EXTERNAL_CHIP_MASK) >> 1) {
+ case XGI310_EXTERNAL_CHIP_LVDS:
+ xgi_video_info.hasVB = HASVB_LVDS;
+ break;
+ case XGI310_EXTERNAL_CHIP_LVDS_CHRONTEL:
+ xgi_video_info.hasVB = HASVB_LVDS_CHRONTEL;
+ break;
+ default:
+ break;
}
- /* TW: We can't switch off CRT1 on 301B-DH in 8bpp Modes if using LCD */
- if (xgi_video_info.disp_state & DISPTYPE_LCD)
- doit = 0;
}
-
- /* TW: We can't switch off CRT1 if bridge is in slave mode */
- if (xgi_video_info.hasVB != HASVB_NONE) {
- inXGIIDXREG(XGIPART1, 0x00, reg);
-
- if ((reg & 0x50) == 0x10)
- doit = 0;
-
- } else {
- XGIfb_crt1off = 0;
- }
-
- inXGIIDXREG(XGICR, 0x17, reg);
- if ((XGIfb_crt1off) && (doit))
- reg &= ~0x80;
- else
- reg |= 0x80;
- outXGIIDXREG(XGICR, 0x17, reg);
-
- andXGIIDXREG(XGISR, IND_XGI_RAMDAC_CONTROL, ~0x04);
-
- if ((xgi_video_info.disp_state & DISPTYPE_TV) && (xgi_video_info.hasVB
- == HASVB_301)) {
-
- inXGIIDXREG(XGIPART4, 0x01, reg);
-
- if (reg < 0xB0) { /* Set filter for XGI301 */
-
- switch (xgi_video_info.video_width) {
- case 320:
- filter_tb = (xgi_video_info.TV_type == TVMODE_NTSC) ? 4 : 12;
- break;
- case 640:
- filter_tb = (xgi_video_info.TV_type == TVMODE_NTSC) ? 5 : 13;
- break;
- case 720:
- filter_tb = (xgi_video_info.TV_type == TVMODE_NTSC) ? 6 : 14;
- break;
- case 800:
- filter_tb = (xgi_video_info.TV_type == TVMODE_NTSC) ? 7 : 15;
- break;
- default:
- filter = -1;
- break;
- }
-
- orXGIIDXREG(XGIPART1, XGIfb_CRT2_write_enable, 0x01);
-
- if (xgi_video_info.TV_type == TVMODE_NTSC) {
-
- andXGIIDXREG(XGIPART2, 0x3a, 0x1f);
-
- if (xgi_video_info.TV_plug == TVPLUG_SVIDEO) {
-
- andXGIIDXREG(XGIPART2, 0x30, 0xdf);
-
- } else if (xgi_video_info.TV_plug
- == TVPLUG_COMPOSITE) {
-
- orXGIIDXREG(XGIPART2, 0x30, 0x20);
-
- switch (xgi_video_info.video_width) {
- case 640:
- outXGIIDXREG(XGIPART2, 0x35, 0xEB);
- outXGIIDXREG(XGIPART2, 0x36, 0x04);
- outXGIIDXREG(XGIPART2, 0x37, 0x25);
- outXGIIDXREG(XGIPART2, 0x38, 0x18);
- break;
- case 720:
- outXGIIDXREG(XGIPART2, 0x35, 0xEE);
- outXGIIDXREG(XGIPART2, 0x36, 0x0C);
- outXGIIDXREG(XGIPART2, 0x37, 0x22);
- outXGIIDXREG(XGIPART2, 0x38, 0x08);
- break;
- case 800:
- outXGIIDXREG(XGIPART2, 0x35, 0xEB);
- outXGIIDXREG(XGIPART2, 0x36, 0x15);
- outXGIIDXREG(XGIPART2, 0x37, 0x25);
- outXGIIDXREG(XGIPART2, 0x38, 0xF6);
- break;
- }
- }
-
- } else if (xgi_video_info.TV_type == TVMODE_PAL) {
-
- andXGIIDXREG(XGIPART2, 0x3A, 0x1F);
-
- if (xgi_video_info.TV_plug == TVPLUG_SVIDEO) {
-
- andXGIIDXREG(XGIPART2, 0x30, 0xDF);
-
- } else if (xgi_video_info.TV_plug
- == TVPLUG_COMPOSITE) {
-
- orXGIIDXREG(XGIPART2, 0x30, 0x20);
-
- switch (xgi_video_info.video_width) {
- case 640:
- outXGIIDXREG(XGIPART2, 0x35, 0xF1);
- outXGIIDXREG(XGIPART2, 0x36, 0xF7);
- outXGIIDXREG(XGIPART2, 0x37, 0x1F);
- outXGIIDXREG(XGIPART2, 0x38, 0x32);
- break;
- case 720:
- outXGIIDXREG(XGIPART2, 0x35, 0xF3);
- outXGIIDXREG(XGIPART2, 0x36, 0x00);
- outXGIIDXREG(XGIPART2, 0x37, 0x1D);
- outXGIIDXREG(XGIPART2, 0x38, 0x20);
- break;
- case 800:
- outXGIIDXREG(XGIPART2, 0x35, 0xFC);
- outXGIIDXREG(XGIPART2, 0x36, 0xFB);
- outXGIIDXREG(XGIPART2, 0x37, 0x14);
- outXGIIDXREG(XGIPART2, 0x38, 0x2A);
- break;
- }
- }
- }
-
- if ((filter >= 0) && (filter <= 7)) {
- DPRINTK("FilterTable[%d]-%d: %02x %02x %02x %02x\n", filter_tb, filter,
- XGI_TV_filter[filter_tb].filter[filter][0],
- XGI_TV_filter[filter_tb].filter[filter][1],
- XGI_TV_filter[filter_tb].filter[filter][2],
- XGI_TV_filter[filter_tb].filter[filter][3]
- );
- outXGIIDXREG(
- XGIPART2,
- 0x35,
- (XGI_TV_filter[filter_tb].filter[filter][0]));
- outXGIIDXREG(
- XGIPART2,
- 0x36,
- (XGI_TV_filter[filter_tb].filter[filter][1]));
- outXGIIDXREG(
- XGIPART2,
- 0x37,
- (XGI_TV_filter[filter_tb].filter[filter][2]));
- outXGIIDXREG(
- XGIPART2,
- 0x38,
- (XGI_TV_filter[filter_tb].filter[filter][3]));
- }
-
- }
-
- }
-
}
XGIINITSTATIC int __init XGIfb_setup(char *options)
@@ -2086,15 +1969,19 @@
if (!strncmp(this_opt, "mode:", 5)) {
XGIfb_search_mode(this_opt + 5);
} else if (!strncmp(this_opt, "vesa:", 5)) {
- XGIfb_search_vesamode(simple_strtoul(this_opt + 5, NULL, 0));
+ XGIfb_search_vesamode(simple_strtoul(
+ this_opt + 5, NULL, 0));
} else if (!strncmp(this_opt, "mode:", 5)) {
XGIfb_search_mode(this_opt + 5);
} else if (!strncmp(this_opt, "vesa:", 5)) {
- XGIfb_search_vesamode(simple_strtoul(this_opt + 5, NULL, 0));
+ XGIfb_search_vesamode(simple_strtoul(
+ this_opt + 5, NULL, 0));
} else if (!strncmp(this_opt, "vrate:", 6)) {
- xgi_video_info.refresh_rate = simple_strtoul(this_opt + 6, NULL, 0);
+ xgi_video_info.refresh_rate = simple_strtoul(
+ this_opt + 6, NULL, 0);
} else if (!strncmp(this_opt, "rate:", 5)) {
- xgi_video_info.refresh_rate = simple_strtoul(this_opt + 5, NULL, 0);
+ xgi_video_info.refresh_rate = simple_strtoul(
+ this_opt + 5, NULL, 0);
} else if (!strncmp(this_opt, "off", 3)) {
XGIfb_off = 1;
} else if (!strncmp(this_opt, "crt1off", 7)) {
@@ -2104,7 +1991,8 @@
} else if (!strncmp(this_opt, "forcecrt2type:", 14)) {
XGIfb_search_crt2type(this_opt + 14);
} else if (!strncmp(this_opt, "forcecrt1:", 10)) {
- XGIfb_forcecrt1 = (int)simple_strtoul(this_opt + 10, NULL, 0);
+ XGIfb_forcecrt1 = (int)simple_strtoul(
+ this_opt + 10, NULL, 0);
} else if (!strncmp(this_opt, "tvmode:", 7)) {
XGIfb_search_tvstd(this_opt + 7);
} else if (!strncmp(this_opt, "tvstandard:", 11)) {
@@ -2122,12 +2010,15 @@
} else if (!strncmp(this_opt, "noypan", 6)) {
XGIfb_ypan = 0;
} else if (!strncmp(this_opt, "userom:", 7)) {
- XGIfb_userom = (int)simple_strtoul(this_opt + 7, NULL, 0);
+ XGIfb_userom = (int)simple_strtoul(
+ this_opt + 7, NULL, 0);
/* } else if (!strncmp(this_opt, "useoem:", 7)) { */
- /* XGIfb_useoem = (int)simple_strtoul(this_opt + 7, NULL, 0); */
+ /* XGIfb_useoem = (int)simple_strtoul(
+ this_opt + 7, NULL, 0); */
} else {
XGIfb_search_mode(this_opt);
- /* printk(KERN_INFO "XGIfb: Invalid option %s\n", this_opt); */
+ /* printk(KERN_INFO "XGIfb: Invalid option %s\n",
+ this_opt); */
}
/* TW: Panning only with acceleration */
@@ -2178,7 +2069,9 @@
return -ENOMEM;
xgi_video_info.chip_id = pdev->device;
- pci_read_config_byte(pdev, PCI_REVISION_ID, &xgi_video_info.revision_id);
+ pci_read_config_byte(pdev,
+ PCI_REVISION_ID,
+ &xgi_video_info.revision_id);
XGIhw_ext.jChipRevision = xgi_video_info.revision_id;
xgi_video_info.pcibus = pdev->bus->number;
@@ -2194,7 +2087,7 @@
XGIhw_ext.pjIOAddress = (unsigned char *)xgi_video_info.vga_base;
/* XGI_Pr.RelIO = ioremap(pci_resource_start(pdev, 2), 128) + 0x30; */
printk("XGIfb: Relocate IO address: %lx [%08lx]\n",
- (unsigned long)pci_resource_start(pdev, 2), XGI_Pr.RelIO);
+ (unsigned long)pci_resource_start(pdev, 2), XGI_Pr.RelIO);
if (pci_enable_device(pdev)) {
ret = -EIO;
@@ -2203,8 +2096,8 @@
XGIRegInit(&XGI_Pr, (unsigned long)XGIhw_ext.pjIOAddress);
- outXGIIDXREG(XGISR, IND_XGI_PASSWORD, XGI_PASSWORD);
- inXGIIDXREG(XGISR, IND_XGI_PASSWORD, reg1);
+ xgifb_reg_set(XGISR, IND_XGI_PASSWORD, XGI_PASSWORD);
+ reg1 = xgifb_reg_get(XGISR, IND_XGI_PASSWORD);
if (reg1 != 0xa1) { /*I/O error */
printk("\nXGIfb: I/O error!!!");
@@ -2214,8 +2107,8 @@
switch (xgi_video_info.chip_id) {
case PCI_DEVICE_ID_XG_20:
- orXGIIDXREG(XGICR, Index_CR_GPIO_Reg3, GPIOG_EN);
- inXGIIDXREG(XGICR, Index_CR_GPIO_Reg1, CR48);
+ xgifb_reg_or(XGICR, Index_CR_GPIO_Reg3, GPIOG_EN);
+ CR48 = xgifb_reg_get(XGICR, Index_CR_GPIO_Reg1);
if (CR48&GPIOG_READ)
xgi_video_info.chip = XG21;
else
@@ -2249,7 +2142,8 @@
if ((xgi_video_info.chip == XG21) || (XGIfb_userom)) {
XGIhw_ext.pjVirtualRomBase = xgifb_copy_rom(pdev);
if (XGIhw_ext.pjVirtualRomBase)
- printk(KERN_INFO "XGIfb: Video ROM found and mapped to %p\n", XGIhw_ext.pjVirtualRomBase);
+ printk(KERN_INFO "XGIfb: Video ROM found and mapped to %p\n",
+ XGIhw_ext.pjVirtualRomBase);
else
printk(KERN_INFO "XGIfb: Video ROM not found\n");
} else {
@@ -2264,17 +2158,23 @@
goto error;
}
- if ((xgifb_mode_idx < 0) || ((XGIbios_mode[xgifb_mode_idx].mode_no) != 0xFF)) {
+ if ((xgifb_mode_idx < 0) ||
+ ((XGIbios_mode[xgifb_mode_idx].mode_no) != 0xFF)) {
/* Enable PCI_LINEAR_ADDRESSING and MMIO_ENABLE */
- orXGIIDXREG(XGISR, IND_XGI_PCI_ADDRESS_SET, (XGI_PCI_ADDR_ENABLE | XGI_MEM_MAP_IO_ENABLE));
+ xgifb_reg_or(XGISR,
+ IND_XGI_PCI_ADDRESS_SET,
+ (XGI_PCI_ADDR_ENABLE | XGI_MEM_MAP_IO_ENABLE));
/* Enable 2D accelerator engine */
- orXGIIDXREG(XGISR, IND_XGI_MODULE_ENABLE, XGI_ENABLE_2D);
+ xgifb_reg_or(XGISR, IND_XGI_MODULE_ENABLE, XGI_ENABLE_2D);
}
XGIhw_ext.ulVideoMemorySize = xgi_video_info.video_size;
- if (!request_mem_region(xgi_video_info.video_base, xgi_video_info.video_size, "XGIfb FB")) {
- printk("unable request memory size %x", xgi_video_info.video_size);
+ if (!request_mem_region(xgi_video_info.video_base,
+ xgi_video_info.video_size,
+ "XGIfb FB")) {
+ printk("unable request memory size %x",
+ xgi_video_info.video_size);
printk(KERN_ERR "XGIfb: Fatal error: Unable to reserve frame buffer memory\n");
printk(KERN_ERR "XGIfb: Is there another framebuffer driver active?\n");
ret = -ENODEV;
@@ -2295,7 +2195,9 @@
xgi_video_info.mmio_size);
printk(KERN_INFO "XGIfb: Framebuffer at 0x%lx, mapped to 0x%p, size %dk\n",
- xgi_video_info.video_base, xgi_video_info.video_vbase, xgi_video_info.video_size / 1024);
+ xgi_video_info.video_base,
+ xgi_video_info.video_vbase,
+ xgi_video_info.video_size / 1024);
printk(KERN_INFO "XGIfb: MMIO at 0x%lx, mapped to 0x%p, size %ldk\n",
xgi_video_info.mmio_base, xgi_video_info.mmio_vbase,
@@ -2308,19 +2210,21 @@
xgi_video_info.mtrr = (unsigned int) 0;
- if ((xgifb_mode_idx < 0) || ((XGIbios_mode[xgifb_mode_idx].mode_no) != 0xFF)) {
+ if ((xgifb_mode_idx < 0) ||
+ ((XGIbios_mode[xgifb_mode_idx].mode_no) != 0xFF)) {
xgi_video_info.hasVB = HASVB_NONE;
- if ((xgi_video_info.chip == XG20) || (xgi_video_info.chip == XG27)) {
+ if ((xgi_video_info.chip == XG20) ||
+ (xgi_video_info.chip == XG27)) {
xgi_video_info.hasVB = HASVB_NONE;
} else if (xgi_video_info.chip == XG21) {
- inXGIIDXREG(XGICR, 0x38, CR38);
+ CR38 = xgifb_reg_get(XGICR, 0x38);
if ((CR38&0xE0) == 0xC0) {
xgi_video_info.disp_state = DISPTYPE_LCD;
if (!XGIfb_GetXG21LVDSData()) {
int m;
for (m = 0; m < sizeof(XGI21_LCDCapList)/sizeof(struct XGI21_LVDSCapStruct); m++) {
if ((XGI21_LCDCapList[m].LVDSHDE == XGIbios_mode[xgifb_mode_idx].xres) &&
- (XGI21_LCDCapList[m].LVDSVDE == XGIbios_mode[xgifb_mode_idx].yres)) {
+ (XGI21_LCDCapList[m].LVDSVDE == XGIbios_mode[xgifb_mode_idx].yres)) {
xgifb_reg_set(XGI_Pr.P3d4, 0x36, m);
}
}
@@ -2340,7 +2244,7 @@
switch (xgi_video_info.hasVB) {
case HASVB_301:
- inXGIIDXREG(XGIPART4, 0x01, reg);
+ reg = xgifb_reg_get(XGIPART4, 0x01);
if (reg >= 0xE0) {
XGIhw_ext.ujVBChipID = VB_CHIP_302LV;
printk(KERN_INFO "XGIfb: XGI302LV bridge detected (revision 0x%02x)\n", reg);
@@ -2350,7 +2254,7 @@
}
/* else if (reg >= 0xB0) {
XGIhw_ext.ujVBChipID = VB_CHIP_301B;
- inXGIIDXREG(XGIPART4, 0x23, reg1);
+ reg1 = xgifb_reg_get(XGIPART4, 0x23);
printk("XGIfb: XGI301B bridge detected\n");
} */
else {
@@ -2359,7 +2263,7 @@
}
break;
case HASVB_302:
- inXGIIDXREG(XGIPART4, 0x01, reg);
+ reg = xgifb_reg_get(XGIPART4, 0x01);
if (reg >= 0xE0) {
XGIhw_ext.ujVBChipID = VB_CHIP_302LV;
printk(KERN_INFO "XGIfb: XGI302LV bridge detected (revision 0x%02x)\n", reg);
@@ -2367,7 +2271,7 @@
XGIhw_ext.ujVBChipID = VB_CHIP_301LV;
printk(KERN_INFO "XGIfb: XGI302LV bridge detected (revision 0x%02x)\n", reg);
} else if (reg >= 0xB0) {
- inXGIIDXREG(XGIPART4, 0x23, reg1);
+ reg1 = xgifb_reg_get(XGIPART4, 0x23);
XGIhw_ext.ujVBChipID = VB_CHIP_302B;
@@ -2404,14 +2308,16 @@
if (XGIfb_crt1off)
xgi_video_info.disp_state |= DISPMODE_SINGLE;
else
- xgi_video_info.disp_state |= (DISPMODE_MIRROR | DISPTYPE_CRT1);
+ xgi_video_info.disp_state |= (DISPMODE_MIRROR |
+ DISPTYPE_CRT1);
} else {
- xgi_video_info.disp_state = DISPMODE_SINGLE | DISPTYPE_CRT1;
+ xgi_video_info.disp_state = DISPMODE_SINGLE |
+ DISPTYPE_CRT1;
}
if (xgi_video_info.disp_state & DISPTYPE_LCD) {
if (!enable_dstn) {
- inXGIIDXREG(XGICR, IND_XGI_LCD_PANEL, reg);
+ reg = xgifb_reg_get(XGICR, IND_XGI_LCD_PANEL);
reg &= 0x0f;
XGIhw_ext.ulCRT2LCDType = XGI310paneltype[reg];
@@ -2431,21 +2337,25 @@
(XGIhw_ext.ujVBChipID == VB_CHIP_301LV) ||
(XGIhw_ext.ujVBChipID == VB_CHIP_302LV)) {
int tmp;
- inXGIIDXREG(XGICR, 0x34, tmp);
+ tmp = xgifb_reg_get(XGICR, 0x34);
if (tmp <= 0x13) {
- /* Currently on LCDA? (Some BIOSes leave CR38) */
- inXGIIDXREG(XGICR, 0x38, tmp);
+ /* Currently on LCDA?
+ *(Some BIOSes leave CR38) */
+ tmp = xgifb_reg_get(XGICR, 0x38);
if ((tmp & 0x03) == 0x03) {
/* XGI_Pr.XGI_UseLCDA = 1; */
} else {
- /* Currently on LCDA? (Some newer BIOSes set D0 in CR35) */
- inXGIIDXREG(XGICR, 0x35, tmp);
+ /* Currently on LCDA?
+ *(Some newer BIOSes set D0 in CR35) */
+ tmp = xgifb_reg_get(XGICR, 0x35);
if (tmp & 0x01) {
/* XGI_Pr.XGI_UseLCDA = 1; */
} else {
- inXGIIDXREG(XGICR, 0x30, tmp);
+ tmp = xgifb_reg_get(XGICR,
+ 0x30);
if (tmp & 0x20) {
- inXGIIDXREG(XGIPART1, 0x13, tmp);
+ tmp = xgifb_reg_get(
+ XGIPART1, 0x13);
if (tmp & 0x04) {
/* XGI_Pr.XGI_UseLCDA = 1; */
}
@@ -2464,7 +2374,8 @@
case DISPTYPE_LCD:
xgifb_mode_idx = DEFAULT_LCDMODE;
if (xgi_video_info.chip == XG21)
- xgifb_mode_idx = XGIfb_GetXG21DefaultLVDSModeIdx();
+ xgifb_mode_idx =
+ XGIfb_GetXG21DefaultLVDSModeIdx();
break;
case DISPTYPE_TV:
xgifb_mode_idx = DEFAULT_TVMODE;
@@ -2477,18 +2388,26 @@
XGIfb_mode_no = XGIbios_mode[xgifb_mode_idx].mode_no;
+ /* yilin set default refresh rate */
if (xgi_video_info.refresh_rate == 0)
- xgi_video_info.refresh_rate = 60; /* yilin set default refresh rate */
- if (XGIfb_search_refresh_rate(xgi_video_info.refresh_rate) == 0) {
+ xgi_video_info.refresh_rate = 60;
+ if (XGIfb_search_refresh_rate(
+ xgi_video_info.refresh_rate) == 0) {
XGIfb_rate_idx = XGIbios_mode[xgifb_mode_idx].rate_idx;
xgi_video_info.refresh_rate = 60;
}
xgi_video_info.video_bpp = XGIbios_mode[xgifb_mode_idx].bpp;
- xgi_video_info.video_vwidth = xgi_video_info.video_width = XGIbios_mode[xgifb_mode_idx].xres;
- xgi_video_info.video_vheight = xgi_video_info.video_height = XGIbios_mode[xgifb_mode_idx].yres;
+ xgi_video_info.video_vwidth =
+ xgi_video_info.video_width =
+ XGIbios_mode[xgifb_mode_idx].xres;
+ xgi_video_info.video_vheight =
+ xgi_video_info.video_height =
+ XGIbios_mode[xgifb_mode_idx].yres;
xgi_video_info.org_x = xgi_video_info.org_y = 0;
- xgi_video_info.video_linelength = xgi_video_info.video_width * (xgi_video_info.video_bpp >> 3);
+ xgi_video_info.video_linelength =
+ xgi_video_info.video_width *
+ (xgi_video_info.video_bpp >> 3);
switch (xgi_video_info.video_bpp) {
case 8:
xgi_video_info.DstColor = 0x0000;
@@ -2507,16 +2426,23 @@
break;
default:
xgi_video_info.video_cmap_len = 16;
- printk(KERN_INFO "XGIfb: Unsupported depth %d", xgi_video_info.video_bpp);
+ printk(KERN_INFO "XGIfb: Unsupported depth %d",
+ xgi_video_info.video_bpp);
break;
}
printk(KERN_INFO "XGIfb: Default mode is %dx%dx%d (%dHz)\n",
- xgi_video_info.video_width, xgi_video_info.video_height, xgi_video_info.video_bpp,
- xgi_video_info.refresh_rate);
+ xgi_video_info.video_width,
+ xgi_video_info.video_height,
+ xgi_video_info.video_bpp,
+ xgi_video_info.refresh_rate);
- default_var.xres = default_var.xres_virtual = xgi_video_info.video_width;
- default_var.yres = default_var.yres_virtual = xgi_video_info.video_height;
+ default_var.xres =
+ default_var.xres_virtual =
+ xgi_video_info.video_width;
+ default_var.yres =
+ default_var.yres_virtual =
+ xgi_video_info.video_height;
default_var.bits_per_pixel = xgi_video_info.video_bpp;
XGIfb_bpp_to_var(&default_var);
@@ -2532,10 +2458,12 @@
&default_var.hsync_len, &default_var.vsync_len,
&default_var.sync, &default_var.vmode)) {
- if ((default_var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
+ if ((default_var.vmode & FB_VMODE_MASK) ==
+ FB_VMODE_INTERLACED) {
default_var.yres <<= 1;
default_var.yres_virtual <<= 1;
- } else if ((default_var.vmode & FB_VMODE_MASK) == FB_VMODE_DOUBLE) {
+ } else if ((default_var.vmode & FB_VMODE_MASK) ==
+ FB_VMODE_DOUBLE) {
default_var.pixclock >>= 1;
default_var.yres >>= 1;
default_var.yres_virtual >>= 1;
@@ -2555,9 +2483,10 @@
fb_alloc_cmap(&fb_info->cmap, 256 , 0);
#ifdef CONFIG_MTRR
- xgi_video_info.mtrr = mtrr_add((unsigned int) xgi_video_info.video_base,
- (unsigned int) xgi_video_info.video_size,
- MTRR_TYPE_WRCOMB, 1);
+ xgi_video_info.mtrr = mtrr_add(
+ (unsigned int) xgi_video_info.video_base,
+ (unsigned int) xgi_video_info.video_size,
+ MTRR_TYPE_WRCOMB, 1);
if (xgi_video_info.mtrr)
printk(KERN_INFO "XGIfb: Added MTRRs\n");
#endif
@@ -2570,7 +2499,7 @@
XGIfb_registered = 1;
printk(KERN_INFO "fb%d: %s frame buffer device, Version %d.%d.%02d\n",
- fb_info->node, myid, VER_MAJOR, VER_MINOR, VER_LEVEL);
+ fb_info->node, myid, VER_MAJOR, VER_MINOR, VER_LEVEL);
}
diff --git a/drivers/staging/xgifb/XGIfb.h b/drivers/staging/xgifb/XGIfb.h
index b43a758..45b6015 100644
--- a/drivers/staging/xgifb/XGIfb.h
+++ b/drivers/staging/xgifb/XGIfb.h
@@ -1,7 +1,7 @@
#ifndef _LINUX_XGIFB
#define _LINUX_XGIFB
-#include <asm/ioctl.h>
-#include <asm/types.h>
+#include <linux/ioctl.h>
+#include <linux/types.h>
#define DISPTYPE_CRT1 0x00000008L
#define DISPTYPE_CRT2 0x00000004L
@@ -13,99 +13,99 @@
#define DISPMODE_MIRROR 0x00000010L
#define DISPMODE_DUALVIEW 0x00000040L
-#define HASVB_NONE 0x00
-#define HASVB_301 0x01
-#define HASVB_LVDS 0x02
-#define HASVB_TRUMPION 0x04
-#define HASVB_LVDS_CHRONTEL 0x10
-#define HASVB_302 0x20
-#define HASVB_303 0x40
-#define HASVB_CHRONTEL 0x80
+#define HASVB_NONE 0x00
+#define HASVB_301 0x01
+#define HASVB_LVDS 0x02
+#define HASVB_TRUMPION 0x04
+#define HASVB_LVDS_CHRONTEL 0x10
+#define HASVB_302 0x20
+#define HASVB_303 0x40
+#define HASVB_CHRONTEL 0x80
#ifndef XGIFB_ID
-#define XGIFB_ID 0x53495346 /* Identify myself with 'XGIF' */
+#define XGIFB_ID 0x53495346 /* Identify myself with 'XGIF' */
#endif
enum XGI_CHIP_TYPE {
- XG40 = 32,
- XG41,
- XG42,
- XG45,
- XG20 = 48,
- XG21,
- XG27,
+ XG40 = 32,
+ XG41,
+ XG42,
+ XG45,
+ XG20 = 48,
+ XG21,
+ XG27,
};
enum xgi_tvtype {
TVMODE_NTSC = 0,
TVMODE_PAL,
TVMODE_HIVISION,
- TVTYPE_PALM, // vicki@030226
- TVTYPE_PALN, // vicki@030226
- TVTYPE_NTSCJ, // vicki@030226
+ TVTYPE_PALM, /* vicki@030226 */
+ TVTYPE_PALN, /* vicki@030226 */
+ TVTYPE_NTSCJ, /* vicki@030226 */
TVMODE_TOTAL
};
-enum xgi_tv_plug { /* vicki@030226 */
-// TVPLUG_Legacy = 0,
-// TVPLUG_COMPOSITE,
-// TVPLUG_SVIDEO,
-// TVPLUG_SCART,
-// TVPLUG_TOTAL
- TVPLUG_UNKNOWN = 0,
- TVPLUG_COMPOSITE = 1,
- TVPLUG_SVIDEO = 2,
- TVPLUG_COMPOSITE_AND_SVIDEO = 3,
- TVPLUG_SCART = 4,
- TVPLUG_YPBPR_525i = 5,
- TVPLUG_YPBPR_525P = 6,
- TVPLUG_YPBPR_750P = 7,
- TVPLUG_YPBPR_1080i = 8,
+enum xgi_tv_plug { /* vicki@030226 */
+/* TVPLUG_Legacy = 0, */
+/* TVPLUG_COMPOSITE, */
+/* TVPLUG_SVIDEO, */
+/* TVPLUG_SCART, */
+/* TVPLUG_TOTAL */
+ TVPLUG_UNKNOWN = 0,
+ TVPLUG_COMPOSITE = 1,
+ TVPLUG_SVIDEO = 2,
+ TVPLUG_COMPOSITE_AND_SVIDEO = 3,
+ TVPLUG_SCART = 4,
+ TVPLUG_YPBPR_525i = 5,
+ TVPLUG_YPBPR_525P = 6,
+ TVPLUG_YPBPR_750P = 7,
+ TVPLUG_YPBPR_1080i = 8,
TVPLUG_TOTAL
};
-struct video_info{
- int chip_id;
- unsigned int video_size;
- unsigned long video_base;
- char * video_vbase;
- unsigned long mmio_base;
+struct video_info {
+ int chip_id;
+ unsigned int video_size;
+ unsigned long video_base;
+ char *video_vbase;
+ unsigned long mmio_base;
unsigned long mmio_size;
- char * mmio_vbase;
- unsigned long vga_base;
- unsigned long mtrr;
+ char *mmio_vbase;
+ unsigned long vga_base;
+ unsigned long mtrr;
- int video_bpp;
- int video_cmap_len;
- int video_width;
- int video_height;
- int video_vwidth;
- int video_vheight;
- int org_x;
- int org_y;
- int video_linelength;
- unsigned int refresh_rate;
+ int video_bpp;
+ int video_cmap_len;
+ int video_width;
+ int video_height;
+ int video_vwidth;
+ int video_vheight;
+ int org_x;
+ int org_y;
+ int video_linelength;
+ unsigned int refresh_rate;
- unsigned long disp_state;
- unsigned char hasVB;
- unsigned char TV_type;
- unsigned char TV_plug;
+ unsigned long disp_state;
+ unsigned char hasVB;
+ unsigned char TV_type;
+ unsigned char TV_plug;
enum XGI_CHIP_TYPE chip;
- unsigned char revision_id;
+ unsigned char revision_id;
- unsigned short DstColor;
- unsigned long XGI310_AccelDepth;
- unsigned long CommandReg;
+ unsigned short DstColor;
+ unsigned long XGI310_AccelDepth;
+ unsigned long CommandReg;
- unsigned int pcibus;
- unsigned int pcislot;
- unsigned int pcifunc;
+ unsigned int pcibus;
+ unsigned int pcislot;
+ unsigned int pcifunc;
- unsigned short subsysvendor;
- unsigned short subsysdevice;
+ unsigned short subsysvendor;
+ unsigned short subsysdevice;
- char reserved[236];
+ char reserved[236];
};
diff --git a/drivers/staging/xgifb/vb_def.h b/drivers/staging/xgifb/vb_def.h
index 4de182b..339c071 100644
--- a/drivers/staging/xgifb/vb_def.h
+++ b/drivers/staging/xgifb/vb_def.h
@@ -1,4 +1,5 @@
-/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/xgi/initdef.h,v 1.4 2000/12/02 01:16:17 dawes Exp $ */
+/* $XFree86: xc/programs/Xserver/hw/xfree86/drivers/xgi/initdef.h
+ * ,v 1.4 2000/12/02 01:16:17 dawes Exp $*/
#ifndef _INITDEF_
#define _INITDEF_
@@ -7,38 +8,38 @@
#endif
/* shampoo */
-#define SEQ_ADDRESS_PORT 0x0014
-#define SEQ_DATA_PORT 0x0015
-#define MISC_OUTPUT_REG_READ_PORT 0x001C
-#define MISC_OUTPUT_REG_WRITE_PORT 0x0012
-#define GRAPH_DATA_PORT 0x1F
-#define GRAPH_ADDRESS_PORT 0x1E
-#define XGI_MASK_DUAL_CHIP 0x04 /* SR3A */
-#define CRTC_ADDRESS_PORT_COLOR 0x0024
+#define SEQ_ADDRESS_PORT 0x0014
+#define SEQ_DATA_PORT 0x0015
+#define MISC_OUTPUT_REG_READ_PORT 0x001C
+#define MISC_OUTPUT_REG_WRITE_PORT 0x0012
+#define GRAPH_DATA_PORT 0x1F
+#define GRAPH_ADDRESS_PORT 0x1E
+#define XGI_MASK_DUAL_CHIP 0x04 /* SR3A */
+#define CRTC_ADDRESS_PORT_COLOR 0x0024
#define VIDEO_SUBSYSTEM_ENABLE_PORT 0x0013
-#define PCI_COMMAND 0x04
+#define PCI_COMMAND 0x04
/* ~shampoo */
-#define VB_XGI301 0x0001 /*301b*/
-#define VB_XGI301B 0x0002
-#define VB_XGI302B 0x0004
+#define VB_XGI301 0x0001 /*301b*/
+#define VB_XGI301B 0x0002
+#define VB_XGI302B 0x0004
#define VB_XGI301LV 0x0008 /*301lv*/
#define VB_XGI302LV 0x0010
-#define VB_XGI301C 0x0020 /* for 301C */
-#define VB_NoLCD 0x8000
+#define VB_XGI301C 0x0020 /* for 301C */
+#define VB_NoLCD 0x8000
/*end 301b*/
-#define VB_YPbPrInfo 0x07 /*301lv*/
-#define VB_YPbPr525i 0x00
-#define VB_YPbPr525p 0x01
-#define VB_YPbPr750p 0x02
-#define VB_YPbPr1080i 0x03
+#define VB_YPbPrInfo 0x07 /*301lv*/
+#define VB_YPbPr525i 0x00
+#define VB_YPbPr525p 0x01
+#define VB_YPbPr750p 0x02
+#define VB_YPbPr1080i 0x03
/* #define CRT1Len 17 */
-#define LVDSCRT1Len 15
-#define CHTVRegDataLen 5
+#define LVDSCRT1Len 15
+#define CHTVRegDataLen 5
/* #define ModeInfoFlag 0x07 */
/* #define IsTextMode 0x07 */
@@ -70,8 +71,8 @@
#define NoSupportTV 0x0070
#define NoSupportHiVisionTV 0x0060
#define NoSupportLCD 0x0058
-#define SupportCHTV 0x0800
-#define SupportCRT2in301C 0x0100 /* for 301C */
+#define SupportCHTV 0x0800
+#define SupportCRT2in301C 0x0100 /* for 301C */
#define SupportTV1024 0x0800 /*301b*/
#define SupportYPbPr 0x1000 /*301lv*/
#define InterlaceMode 0x0080
@@ -104,7 +105,7 @@
#define DisableCRT2Display 0x2000
#define DriverMode 0x4000
#define HotKeySwitch 0x8000
-#define SetCHTVOverScan 0x8000
+#define SetCHTVOverScan 0x8000
/* #define SetCRT2ToLCDA 0x8000 301b */
#define PanelRGB18Bit 0x0100
#define PanelRGB24Bit 0x0000
@@ -112,8 +113,8 @@
#define TVOverScan 0x10
#define TVOverScanShift 4
#define ClearBufferFlag 0x20
-#define EnableDualEdge 0x01 /*301b*/
-#define SetToLCDA 0x02
+#define EnableDualEdge 0x01 /*301b*/
+#define SetToLCDA 0x02
#define YPbPrModeInfo 0x38
/* #define YPbPrMode525i 0x00 */
@@ -123,7 +124,7 @@
#define SetSCARTOutput 0x01
#define BoardTVType 0x02
-#define EnablePALMN 0x40
+#define EnablePALMN 0x40
/* #define ProgrammingCRT2 0x01 */
/* #define TVSimuMode 0x02 */
/* #define RPLLDIV2XO 0x04 */
@@ -133,9 +134,9 @@
#define CheckWinDos 0x40
#define SetJDOSMode 0x80
-#define Panel320x480 0x07/*fstn*/
+#define Panel320x480 0x07 /*fstn*/
/* [ycchen] 02/12/03 Modify for Multi-Sync. LCD Support */
-#define PanelResInfo 0x1F /* CR36 Panel Type/LCDResInfo */
+#define PanelResInfo 0x1F /* CR36 Panel Type/LCDResInfo */
#define PanelRefInfo 0x60
#define Panel800x600 0x01
#define Panel1024x768 0x02
@@ -200,7 +201,7 @@
#define SoftDramType 0x80
#define VCLK40 0x04
-#define VCLK162 0x21
+#define VCLK162 0x21
#define LCDRGB18Bit 0x01
#define LoadDACFlag 0x1000
@@ -228,11 +229,11 @@
#define StStructSize 0x06
-#define XGI_CRT2_PORT_00 0x00 - 0x030
-#define XGI_CRT2_PORT_04 0x04 - 0x030
-#define XGI_CRT2_PORT_10 0x10 - 0x30
-#define XGI_CRT2_PORT_12 0x12 - 0x30
-#define XGI_CRT2_PORT_14 0x14 - 0x30
+#define XGI_CRT2_PORT_00 (0x00 - 0x030)
+#define XGI_CRT2_PORT_04 (0x04 - 0x030)
+#define XGI_CRT2_PORT_10 (0x10 - 0x30)
+#define XGI_CRT2_PORT_12 (0x12 - 0x30)
+#define XGI_CRT2_PORT_14 (0x14 - 0x30)
#define LCDNonExpanding 0x10
@@ -274,8 +275,8 @@
#define _PanelType0E 0x70
#define _PanelType0F 0x78
-
-#define PRIMARY_VGA 0 /* 1: XGI is primary vga 0:XGI is secondary vga */
+/* 1: XGI is primary vga 0:XGI is secondary vga */
+#define PRIMARY_VGA 0
#define BIOSIDCodeAddr 0x235
#define OEMUtilIDCodeAddr 0x237
#define VBModeIDTableAddr 0x239
@@ -362,656 +363,660 @@
#define VideoSenseDataOffset 0xC1
#define OutputSelectOffset 0xF3
-#define ECLK_MCLK_DISTANCE 0x14
+#define ECLK_MCLK_DISTANCE 0x14
#define VBIOSTablePointerStart 0x200
-#define StandTablePtrOffset VBIOSTablePointerStart+0x02
-#define EModeIDTablePtrOffset VBIOSTablePointerStart+0x04
-#define CRT1TablePtrOffset VBIOSTablePointerStart+0x06
-#define ScreenOffsetPtrOffset VBIOSTablePointerStart+0x08
-#define VCLKDataPtrOffset VBIOSTablePointerStart+0x0A
-#define MCLKDataPtrOffset VBIOSTablePointerStart+0x0E
-#define CRT2PtrDataPtrOffset VBIOSTablePointerStart+0x10
-#define TVAntiFlickPtrOffset VBIOSTablePointerStart+0x12
-#define TVDelayPtr1Offset VBIOSTablePointerStart+0x14
-#define TVPhaseIncrPtr1Offset VBIOSTablePointerStart+0x16
-#define TVYFilterPtr1Offset VBIOSTablePointerStart+0x18
-#define LCDDelayPtr1Offset VBIOSTablePointerStart+0x20
-#define TVEdgePtr1Offset VBIOSTablePointerStart+0x24
-#define CRT2Delay1Offset VBIOSTablePointerStart+0x28
-#define LCDDataDesOffset VBIOSTablePointerStart-0x02
-#define LCDDataPtrOffset VBIOSTablePointerStart+0x2A
-#define LCDDesDataPtrOffset VBIOSTablePointerStart+0x2C
-#define LCDDataList VBIOSTablePointerStart+0x22 /* add for GetLCDPtr */
-#define TVDataList VBIOSTablePointerStart+0x36 /* add for GetTVPtr */
+#define StandTablePtrOffset (VBIOSTablePointerStart+0x02)
+#define EModeIDTablePtrOffset (VBIOSTablePointerStart+0x04)
+#define CRT1TablePtrOffset (VBIOSTablePointerStart+0x06)
+#define ScreenOffsetPtrOffset (VBIOSTablePointerStart+0x08)
+#define VCLKDataPtrOffset (VBIOSTablePointerStart+0x0A)
+#define MCLKDataPtrOffset (VBIOSTablePointerStart+0x0E)
+#define CRT2PtrDataPtrOffset (VBIOSTablePointerStart+0x10)
+#define TVAntiFlickPtrOffset (VBIOSTablePointerStart+0x12)
+#define TVDelayPtr1Offset (VBIOSTablePointerStart+0x14)
+#define TVPhaseIncrPtr1Offset (VBIOSTablePointerStart+0x16)
+#define TVYFilterPtr1Offset (VBIOSTablePointerStart+0x18)
+#define LCDDelayPtr1Offset (VBIOSTablePointerStart+0x20)
+#define TVEdgePtr1Offset (VBIOSTablePointerStart+0x24)
+#define CRT2Delay1Offset (VBIOSTablePointerStart+0x28)
+#define LCDDataDesOffset (VBIOSTablePointerStart-0x02)
+#define LCDDataPtrOffset (VBIOSTablePointerStart+0x2A)
+#define LCDDesDataPtrOffset (VBIOSTablePointerStart+0x2C)
+/* add LCDDataList for GetLCDPtr */
+#define LCDDataList (VBIOSTablePointerStart+0x22)
+/* add TVDataList for GetTVPtr */
+#define TVDataList (VBIOSTablePointerStart+0x36)
/* */
/* Modify from 310.inc */
/* */
/* */
-#define ShowMsgFlag 0x20 /* SoftSetting */
-#define ShowVESAFlag 0x10
-#define HotPlugFunction 0x08
-#define ModeSoftSetting 0x04
-#define TVSoftSetting 0x02
-#define LCDSoftSetting 0x01
+#define ShowMsgFlag 0x20 /* SoftSetting */
+#define ShowVESAFlag 0x10
+#define HotPlugFunction 0x08
+#define ModeSoftSetting 0x04
+#define TVSoftSetting 0x02
+#define LCDSoftSetting 0x01
-#define GatingCRTinLCDA 0x10
-#define SetHiTVOutput 0x08
-#define SetYPbPrOutput 0x04
-#define BoardTVType 0x02
-#define SetSCARTOutput 0x01
+#define GatingCRTinLCDA 0x10
+#define SetHiTVOutput 0x08
+#define SetYPbPrOutput 0x04
+#define BoardTVType 0x02
+#define SetSCARTOutput 0x01
-#define ModeSettingYPbPr 0x02 /* TVModeSetting, Others as same as CR30 */
+/* TVModeSetting, Others as same as CR30 */
+#define ModeSettingYPbPr 0x02
/* TVModeSetting same as CR35 */
/* LCDModeSetting same as CR37 */
-#define EnableNewTVFont 0x10 /* MiscCapability */
+#define EnableNewTVFont 0x10 /* MiscCapability */
-#define EnableLCDOutput 0x80 /* LCDCfgSetting */
+#define EnableLCDOutput 0x80 /* LCDCfgSetting */
-#define SoftDRAMType 0x80 /* DRAMSetting */
-#define SoftDRAMConfig 0x40
-#define MosSelDRAMType 0x20
-#define SDRAM 000h
-#define SGRAM 0x01
-#define ESDRAM 0x02
+#define SoftDRAMType 0x80 /* DRAMSetting */
+#define SoftDRAMConfig 0x40
+#define MosSelDRAMType 0x20
+#define SDRAM 000h
+#define SGRAM 0x01
+#define ESDRAM 0x02
-#define EnableAGPCfgSetting 0x01 /* AGPCfgSetting */
+#define EnableAGPCfgSetting 0x01 /* AGPCfgSetting */
/* ---------------- SetMode Stack */
-#define CRT1Len 15
-#define VCLKLen 4
-#define DefThreshold 0x0100
-#define ExtRegsSize (57+8+37+70+63+28+768+1)/64+1
+#define CRT1Len 15
+#define VCLKLen 4
+#define DefThreshold 0x0100
+#define ExtRegsSize ((57+8+37+70+63+28+768+1)/64+1)
-#define VGA_XGI315 0x0001 /* VGA Type Info */
-#define VGA_SNewis315e 0x0002 /* 315 series */
-#define VGA_XGI550 0x0004
-#define VGA_XGI640 0x0008
-#define VGA_XGI740 0x0010
-#define VGA_XGI650 0x0020
-#define VGA_XGI650M 0x0040
-#define VGA_XGI651 0x0080
-#define VGA_XGI340 0x0001 /* 340 series */
-#define VGA_XGI330 0x0001 /* 330 series */
-#define VGA_XGI660 0x0001 /* 660 series */
+#define VGA_XGI315 0x0001 /* VGA Type Info */
+#define VGA_SNewis315e 0x0002 /* 315 series */
+#define VGA_XGI550 0x0004
+#define VGA_XGI640 0x0008
+#define VGA_XGI740 0x0010
+#define VGA_XGI650 0x0020
+#define VGA_XGI650M 0x0040
+#define VGA_XGI651 0x0080
+#define VGA_XGI340 0x0001 /* 340 series */
+#define VGA_XGI330 0x0001 /* 330 series */
+#define VGA_XGI660 0x0001 /* 660 series */
-#define VB_XGI301 0x0001 /* VB Type Info */
-#define VB_XGI301B 0x0002 /* 301 series */
-#define VB_XGI302B 0x0004
-#define VB_NoLCD 0x8000
-#define VB_XGI301LV 0x0008
-#define VB_XGI302LV 0x0010
-#define VB_LVDS_NS 0x0001 /* 3rd party chip */
-#define VB_CH7017 0x0002
-#define VB_CH7007 0x0080 /* [Billy] 07/05/03 */
+#define VB_XGI301 0x0001 /* VB Type Info */
+#define VB_XGI301B 0x0002 /* 301 series */
+#define VB_XGI302B 0x0004
+#define VB_NoLCD 0x8000
+#define VB_XGI301LV 0x0008
+#define VB_XGI302LV 0x0010
+#define VB_LVDS_NS 0x0001 /* 3rd party chip */
+#define VB_CH7017 0x0002
+#define VB_CH7007 0x0080 /* [Billy] 07/05/03 */
/* #define VB_LVDS_SI 0x0004 */
-#define ModeInfoFlag 0x0007
-#define IsTextMode 0x0007
-#define ModeText 0x0000
-#define ModeCGA 0x0001
-#define ModeEGA 0x0002 /* 16 colors mode */
-#define ModeVGA 0x0003 /* 256 colors mode */
-#define Mode15Bpp 0x0004 /* 15 Bpp Color Mode */
-#define Mode16Bpp 0x0005 /* 16 Bpp Color Mode */
-#define Mode24Bpp 0x0006 /* 24 Bpp Color Mode */
-#define Mode32Bpp 0x0007 /* 32 Bpp Color Mode */
+#define ModeInfoFlag 0x0007
+#define IsTextMode 0x0007
+#define ModeText 0x0000
+#define ModeCGA 0x0001
+#define ModeEGA 0x0002 /* 16 colors mode */
+#define ModeVGA 0x0003 /* 256 colors mode */
+#define Mode15Bpp 0x0004 /* 15 Bpp Color Mode */
+#define Mode16Bpp 0x0005 /* 16 Bpp Color Mode */
+#define Mode24Bpp 0x0006 /* 24 Bpp Color Mode */
+#define Mode32Bpp 0x0007 /* 32 Bpp Color Mode */
-#define DACInfoFlag 0x0018
-#define MONODAC 0x0000
-#define CGADAC 0x0008
-#define EGADAC 0x0010
-#define VGADAC 0x0018
+#define DACInfoFlag 0x0018
+#define MONODAC 0x0000
+#define CGADAC 0x0008
+#define EGADAC 0x0010
+#define VGADAC 0x0018
-#define MemoryInfoFlag 0x01e0
-#define MemorySizeShift 5
-#define Need1MSize 0x0000
-#define Need2MSize 0x0020
-#define Need4MSize 0x0060
-#define Need8MSize 0x00e0
-#define Need16MSize 0x01e0
+#define MemoryInfoFlag 0x01e0
+#define MemorySizeShift 5
+#define Need1MSize 0x0000
+#define Need2MSize 0x0020
+#define Need4MSize 0x0060
+#define Need8MSize 0x00e0
+#define Need16MSize 0x01e0
-#define Charx8Dot 0x0200
-#define LineCompareOff 0x0400
-#define CRT2Mode 0x0800
-#define HalfDCLK 0x1000
-#define NoSupportSimuTV 0x2000
-#define DoubleScanMode 0x8000
+#define Charx8Dot 0x0200
+#define LineCompareOff 0x0400
+#define CRT2Mode 0x0800
+#define HalfDCLK 0x1000
+#define NoSupportSimuTV 0x2000
+#define DoubleScanMode 0x8000
/* -------------- Ext_InfoFlag */
-#define SupportModeInfo 0x0007
-#define Support256 0x0003
-#define Support15Bpp 0x0004
-#define Support16Bpp 0x0005
-#define Support24Bpp 0x0006
-#define Support32Bpp 0x0007
+#define SupportModeInfo 0x0007
+#define Support256 0x0003
+#define Support15Bpp 0x0004
+#define Support16Bpp 0x0005
+#define Support24Bpp 0x0006
+#define Support32Bpp 0x0007
-#define SupportAllCRT2 0x0078
-#define SupportTV 0x0008
-#define SupportHiVisionTV 0x0010
-#define SupportLCD 0x0020
-#define SupportRAMDAC2 0x0040
-#define NoSupportTV 0x0070
-#define NoSupportHiVisionTV 0x0060
-#define NoSupportLCD 0x0058
-#define SupportTV1024 0x0800 /* 301btest */
-#define SupportYPbPr 0x1000 /* 301lv */
-#define InterlaceMode 0x0080
-#define SyncPP 0x0000
-#define SyncPN 0x4000
-#define SyncNP 0x8000
-#define SyncNN 0xC000
+#define SupportAllCRT2 0x0078
+#define SupportTV 0x0008
+#define SupportHiVisionTV 0x0010
+#define SupportLCD 0x0020
+#define SupportRAMDAC2 0x0040
+#define NoSupportTV 0x0070
+#define NoSupportHiVisionTV 0x0060
+#define NoSupportLCD 0x0058
+#define SupportTV1024 0x0800 /* 301btest */
+#define SupportYPbPr 0x1000 /* 301lv */
+#define InterlaceMode 0x0080
+#define SyncPP 0x0000
+#define SyncPN 0x4000
+#define SyncNP 0x8000
+#define SyncNN 0xC000
/* -------------- SetMode Stack/Scratch */
-#define SetSimuScanMode 0x0001 /* VBInfo/CR30 & CR31 */
-#define SwitchToCRT2 0x0002
-#define SetCRT2ToTV1 0x009C
-#define SetCRT2ToTV 0x089C
-#define SetCRT2ToAVIDEO 0x0004
-#define SetCRT2ToSVIDEO 0x0008
-#define SetCRT2ToSCART 0x0010
-#define SetCRT2ToLCD 0x0020
-#define SetCRT2ToRAMDAC 0x0040
-#define SetCRT2ToHiVisionTV 0x0080
-#define SetCRT2ToLCDA 0x0100
-#define SetInSlaveMode 0x0200
-#define SetNotSimuMode 0x0400
-#define HKEventMode 0x0800
-#define SetCRT2ToYPbPr 0x0800
-#define LoadDACFlag 0x1000
-#define DisableCRT2Display 0x2000
-#define DriverMode 0x4000
-#define SetCRT2ToDualEdge 0x8000
-#define HotKeySwitch 0x8000
+#define SetSimuScanMode 0x0001 /* VBInfo/CR30 & CR31 */
+#define SwitchToCRT2 0x0002
+#define SetCRT2ToTV1 0x009C
+#define SetCRT2ToTV 0x089C
+#define SetCRT2ToAVIDEO 0x0004
+#define SetCRT2ToSVIDEO 0x0008
+#define SetCRT2ToSCART 0x0010
+#define SetCRT2ToLCD 0x0020
+#define SetCRT2ToRAMDAC 0x0040
+#define SetCRT2ToHiVisionTV 0x0080
+#define SetCRT2ToLCDA 0x0100
+#define SetInSlaveMode 0x0200
+#define SetNotSimuMode 0x0400
+#define HKEventMode 0x0800
+#define SetCRT2ToYPbPr 0x0800
+#define LoadDACFlag 0x1000
+#define DisableCRT2Display 0x2000
+#define DriverMode 0x4000
+#define SetCRT2ToDualEdge 0x8000
+#define HotKeySwitch 0x8000
-#define ProgrammingCRT2 0x0001 /* Set Flag */
-#define EnableVCMode 0x0002
-#define SetHKEventMode 0x0004
-#define ReserveTVOption 0x0008
-#define DisableRelocateIO 0x0010
-#define Win9xDOSMode 0x0020
-#define JDOSMode 0x0040
+#define ProgrammingCRT2 0x0001 /* Set Flag */
+#define EnableVCMode 0x0002
+#define SetHKEventMode 0x0004
+#define ReserveTVOption 0x0008
+#define DisableRelocateIO 0x0010
+#define Win9xDOSMode 0x0020
+#define JDOSMode 0x0040
/* #define SetWin9xforJap 0x0080 // not used now */
/* #define SetWin9xforKorea 0x0100 // not used now */
-#define GatingCRT 0x0800
-#define DisableChB 0x1000
-#define EnableChB 0x2000
-#define DisableChA 0x4000
-#define EnableChA 0x8000
+#define GatingCRT 0x0800
+#define DisableChB 0x1000
+#define EnableChB 0x2000
+#define DisableChA 0x4000
+#define EnableChA 0x8000
-#define SetNTSCTV 0x0000 /* TV Info */
-#define SetPALTV 0x0001
-#define SetNTSCJ 0x0002
-#define SetPALMTV 0x0004
-#define SetPALNTV 0x0008
-#define SetCHTVUnderScan 0x0000
+#define SetNTSCTV 0x0000 /* TV Info */
+#define SetPALTV 0x0001
+#define SetNTSCJ 0x0002
+#define SetPALMTV 0x0004
+#define SetPALNTV 0x0008
+#define SetCHTVUnderScan 0x0000
/* #define SetCHTVOverScan 0x0010 */
-#define SetYPbPrMode525i 0x0020
-#define SetYPbPrMode525p 0x0040
-#define SetYPbPrMode750p 0x0080
-#define SetYPbPrMode1080i 0x0100
-#define SetTVStdMode 0x0200
-#define SetTVLowResolution 0x0400
-#define SetTVSimuMode 0x0800
-#define TVSimuMode 0x0800
-#define RPLLDIV2XO 0x1000
-#define NTSC1024x768 0x2000
-#define SetTVLockMode 0x4000
+#define SetYPbPrMode525i 0x0020
+#define SetYPbPrMode525p 0x0040
+#define SetYPbPrMode750p 0x0080
+#define SetYPbPrMode1080i 0x0100
+#define SetTVStdMode 0x0200
+#define SetTVLowResolution 0x0400
+#define SetTVSimuMode 0x0800
+#define TVSimuMode 0x0800
+#define RPLLDIV2XO 0x1000
+#define NTSC1024x768 0x2000
+#define SetTVLockMode 0x4000
-#define LCDVESATiming 0x0001 /* LCD Info/CR37 */
-#define EnableLVDSDDA 0x0002
-#define EnableScalingLCD 0x0008
-#define SetPWDEnable 0x0004
-#define SetLCDtoNonExpanding 0x0010
-#define SetLCDPolarity 0x00e0
-#define SetLCDDualLink 0x0100
-#define SetLCDLowResolution 0x0200
-#define SetLCDStdMode 0x0400
+#define LCDVESATiming 0x0001 /* LCD Info/CR37 */
+#define EnableLVDSDDA 0x0002
+#define EnableScalingLCD 0x0008
+#define SetPWDEnable 0x0004
+#define SetLCDtoNonExpanding 0x0010
+#define SetLCDPolarity 0x00e0
+#define SetLCDDualLink 0x0100
+#define SetLCDLowResolution 0x0200
+#define SetLCDStdMode 0x0400
-#define DefaultLCDCap 0x80ea /* LCD Capability shampoo */
-#define RLVDSDHL00 0x0000
-#define RLVDSDHL01 0x0001
-#define RLVDSDHL10 0x0002 /* default */
-#define RLVDSDHL11 0x0003
-#define EnableLCD24bpp 0x0004 /* default */
-#define DisableLCD24bpp 0x0000
-#define RLVDSClkSFT0 0x0000
-#define RLVDSClkSFT1 0x0008 /* default */
-#define EnableLVDSDCBal 0x0010
-#define DisableLVDSDCBal 0x0000 /* default */
-#define SinglePolarity 0x0020 /* default */
-#define MultiPolarity 0x0000
-#define LCDPolarity 0x00c0 /* default: SyncNN */
-#define LCDSingleLink 0x0000 /* default */
-#define LCDDualLink 0x0100
-#define EnableSpectrum 0x0200
-#define DisableSpectrum 0x0000 /* default */
-#define PWDEnable 0x0400
-#define PWDDisable 0x0000 /* default */
-#define PWMEnable 0x0800
-#define PWMDisable 0x0000 /* default */
-#define EnableVBCLKDRVLOW 0x4000
-#define EnableVBCLKDRVHigh 0x0000 /* default */
-#define EnablePLLSPLOW 0x8000
-#define EnablePLLSPHigh 0x0000 /* default */
+/* LCD Capability shampoo */
+#define DefaultLCDCap 0x80ea
+#define RLVDSDHL00 0x0000
+#define RLVDSDHL01 0x0001
+#define RLVDSDHL10 0x0002 /* default */
+#define RLVDSDHL11 0x0003
+#define EnableLCD24bpp 0x0004 /* default */
+#define DisableLCD24bpp 0x0000
+#define RLVDSClkSFT0 0x0000
+#define RLVDSClkSFT1 0x0008 /* default */
+#define EnableLVDSDCBal 0x0010
+#define DisableLVDSDCBal 0x0000 /* default */
+#define SinglePolarity 0x0020 /* default */
+#define MultiPolarity 0x0000
+#define LCDPolarity 0x00c0 /* default: SyncNN */
+#define LCDSingleLink 0x0000 /* default */
+#define LCDDualLink 0x0100
+#define EnableSpectrum 0x0200
+#define DisableSpectrum 0x0000 /* default */
+#define PWDEnable 0x0400
+#define PWDDisable 0x0000 /* default */
+#define PWMEnable 0x0800
+#define PWMDisable 0x0000 /* default */
+#define EnableVBCLKDRVLOW 0x4000
+#define EnableVBCLKDRVHigh 0x0000 /* default */
+#define EnablePLLSPLOW 0x8000
+#define EnablePLLSPHigh 0x0000 /* default */
-#define LCDBToA 0x20 /* LCD SetFlag */
-#define StLCDBToA 0x40
-#define LockLCDBToA 0x80
-#define LCDToFull 0x10
-#define AVIDEOSense 0x01 /* CR32 */
-#define SVIDEOSense 0x02
-#define SCARTSense 0x04
-#define LCDSense 0x08
-#define Monitor2Sense 0x10
-#define Monitor1Sense 0x20
-#define HiTVSense 0x40
+#define LCDBToA 0x20 /* LCD SetFlag */
+#define StLCDBToA 0x40
+#define LockLCDBToA 0x80
+#define LCDToFull 0x10
+#define AVIDEOSense 0x01 /* CR32 */
+#define SVIDEOSense 0x02
+#define SCARTSense 0x04
+#define LCDSense 0x08
+#define Monitor2Sense 0x10
+#define Monitor1Sense 0x20
+#define HiTVSense 0x40
-#ifdef NewScratch
-#define YPbPrSense 0x80 /* NEW SCRATCH */
+#ifdef NewScratch
+#define YPbPrSense 0x80 /* NEW SCRATCH */
#endif
-#define TVSense 0xc7
+#define TVSense 0xc7
-#define TVOverScan 0x10 /* CR35 */
-#define TVOverScanShift 4
+#define TVOverScan 0x10 /* CR35 */
+#define TVOverScanShift 4
-#ifdef NewScratch
-#define NTSCMode 0x00
-#define PALMode 0x00
-#define NTSCJMode 0x02
-#define PALMNMode 0x0c
-#define YPbPrMode 0xe0
-#define YPbPrMode525i 0x00
-#define YPbPrMode525p 0x20
-#define YPbPrMode750p 0x40
-#define YPbPrMode1080i 0x60
+#ifdef NewScratch
+#define NTSCMode 0x00
+#define PALMode 0x00
+#define NTSCJMode 0x02
+#define PALMNMode 0x0c
+#define YPbPrMode 0xe0
+#define YPbPrMode525i 0x00
+#define YPbPrMode525p 0x20
+#define YPbPrMode750p 0x40
+#define YPbPrMode1080i 0x60
#else /* Old Scratch */
-#define ClearBufferFlag 0x20
+#define ClearBufferFlag 0x20
#endif
-#define LCDRGB18Bit 0x01 /* CR37 */
-#define LCDNonExpanding 0x10
-#define LCDNonExpandingShift 4
-#define LCDSync 0x20
-#define LCDSyncBit 0xe0 /* H/V polarity & sync ID */
-#define LCDSyncShift 6
+#define LCDRGB18Bit 0x01 /* CR37 */
+#define LCDNonExpanding 0x10
+#define LCDNonExpandingShift 4
+#define LCDSync 0x20
+#define LCDSyncBit 0xe0 /* H/V polarity & sync ID */
+#define LCDSyncShift 6
-#ifdef NewScratch
-#define ScalingLCD 0x08
+#ifdef NewScratch
+#define ScalingLCD 0x08
+#else /* Old Scratch */
+#define ExtChipType 0x0e
+#define ExtChip301 0x02
+#define ExtChipLVDS 0x04
+#define ExtChipCH7019 0x06
+#define ScalingLCD 0x10
+#endif
+
+#define EnableDualEdge 0x01 /* CR38 */
+#define SetToLCDA 0x02
+#ifdef NewScratch
+#define SetYPbPr 0x04
+#define DisableChannelA 0x08
+#define DisableChannelB 0x10
+#define ExtChipType 0xe0
+#define ExtChip301 0x20
+#define ExtChipLVDS 0x40
+#define ExtChipCH7019 0x60
#else /* Old Scratch */
-#define ExtChipType 0x0e
-#define ExtChip301 0x02
-#define ExtChipLVDS 0x04
-#define ExtChipCH7019 0x06
-#define ScalingLCD 0x10
+#define YPbPrSense 0x04
+#define SetYPbPr 0x08
+#define YPbPrMode 0x30
+#define YPbPrMode525i 0x00
+#define YPbPrMode525p 0x10
+#define YPbPrMode750p 0x20
+#define YPbPrMode1080i 0x30
+#define PALMNMode 0xc0
#endif
-#define EnableDualEdge 0x01 /* CR38 */
-#define SetToLCDA 0x02
-#ifdef NewScratch
-#define SetYPbPr 0x04
-#define DisableChannelA 0x08
-#define DisableChannelB 0x10
-#define ExtChipType 0xe0
-#define ExtChip301 0x20
-#define ExtChipLVDS 0x40
-#define ExtChipCH7019 0x60
-#else /* Old Scratch */
-#define YPbPrSense 0x04
-#define SetYPbPr 0x08
-#define YPbPrMode 0x30
-#define YPbPrMode525i 0x00
-#define YPbPrMode525p 0x10
-#define YPbPrMode750p 0x20
-#define YPbPrMode1080i 0x30
-#define PALMNMode 0xc0
-#endif
+#define BacklightControlBit 0x01 /* CR3A */
+#define Win9xforJap 0x40
+#define Win9xforKorea 0x80
-#define BacklightControlBit 0x01 /* CR3A */
-#define Win9xforJap 0x40
-#define Win9xforKorea 0x80
+#define ForceMDBits 0x07 /* CR3B */
+#define ForceMD_JDOS 0x00
+#define ForceMD_640x400T 0x01
+#define ForceMD_640x350T 0x02
+#define ForceMD_720x400T 0x03
+#define ForceMD_640x480E 0x04
+#define ForceMD_640x400E 0x05
+#define ForceP1Bit 0x10
+#define ForceP2Bit 0x20
+#define EnableForceMDinBIOS 0x40
+#define EnableForceMDinDrv 0x80
-#define ForceMDBits 0x07 /* CR3B */
-#define ForceMD_JDOS 0x00
-#define ForceMD_640x400T 0x01
-#define ForceMD_640x350T 0x02
-#define ForceMD_720x400T 0x03
-#define ForceMD_640x480E 0x04
-#define ForceMD_640x400E 0x05
-#define ForceP1Bit 0x10
-#define ForceP2Bit 0x20
-#define EnableForceMDinBIOS 0x40
-#define EnableForceMDinDrv 0x80
-
-#ifdef NewScratch /* New Scratch */
+#ifdef NewScratch /* New Scratch */
/* ---------------------- VUMA Information */
-#define LCDSettingFromCMOS 0x04 /* CR3C */
-#define TVSettingFromCMOS 0x08
-#define DisplayDeviceFromCMOS 0x10
-#define HKSupportInSBIOS 0x20
-#define OSDSupportInSBIOS 0x40
-#define DisableLogo 0x80
+#define LCDSettingFromCMOS 0x04 /* CR3C */
+#define TVSettingFromCMOS 0x08
+#define DisplayDeviceFromCMOS 0x10
+#define HKSupportInSBIOS 0x20
+#define OSDSupportInSBIOS 0x40
+#define DisableLogo 0x80
/* ---------------------- HK Evnet Definition */
-#define HKEvent 0x0f /* CR3D */
-#define HK_ModeSwitch 0x01
-#define HK_Expanding 0x02
-#define HK_OverScan 0x03
-#define HK_Brightness 0x04
-#define HK_Contrast 0x05
-#define HK_Mute 0x06
-#define HK_Volume 0x07
-#define ModeSwitchStatus 0xf0
-#define ActiveCRT1 0x10
-#define ActiveLCD 0x0020
-#define ActiveTV 0x40
-#define ActiveCRT2 0x80
+#define HKEvent 0x0f /* CR3D */
+#define HK_ModeSwitch 0x01
+#define HK_Expanding 0x02
+#define HK_OverScan 0x03
+#define HK_Brightness 0x04
+#define HK_Contrast 0x05
+#define HK_Mute 0x06
+#define HK_Volume 0x07
+#define ModeSwitchStatus 0xf0
+#define ActiveCRT1 0x10
+#define ActiveLCD 0x0020
+#define ActiveTV 0x40
+#define ActiveCRT2 0x80
-#define TVSwitchStatus 0x1f /* CR3E */
-#define ActiveAVideo 0x01
-#define ActiveSVideo 0x02
-#define ActiveSCART 0x04
-#define ActiveHiTV 0x08
-#define ActiveYPbPr 0x10
+#define TVSwitchStatus 0x1f /* CR3E */
+#define ActiveAVideo 0x01
+#define ActiveSVideo 0x02
+#define ActiveSCART 0x04
+#define ActiveHiTV 0x08
+#define ActiveYPbPr 0x10
-#define EnableHKEvent 0x01 /* CR3F */
-#define EnableOSDEvent 0x02
-#define StartOSDEvent 0x04
-#define IgnoreHKEvent 0x08
-#define IgnoreOSDEvent 0x10
+#define EnableHKEvent 0x01 /* CR3F */
+#define EnableOSDEvent 0x02
+#define StartOSDEvent 0x04
+#define IgnoreHKEvent 0x08
+#define IgnoreOSDEvent 0x10
#else /* Old Scratch */
-#define OSD_SBIOS 0x02 /* SR17 */
-#define DisableLogo 0x04
-#define SelectKDOS 0x08
-#define KorWinMode 0x10
-#define KorMode3Bit 0x0020
-#define PSCCtrlBit 0x40
-#define NPSCCtrlBitShift 6
-#define BlueScreenBit 0x80
+#define OSD_SBIOS 0x02 /* SR17 */
+#define DisableLogo 0x04
+#define SelectKDOS 0x08
+#define KorWinMode 0x10
+#define KorMode3Bit 0x0020
+#define PSCCtrlBit 0x40
+#define NPSCCtrlBitShift 6
+#define BlueScreenBit 0x80
-#define HKEvent 0x0f /* CR79 */
-#define HK_ModeSwitch 0x01
-#define HK_Expanding 0x02
-#define HK_OverScan 0x03
-#define HK_Brightness 0x04
-#define HK_Contrast 0x05
-#define HK_Mute 0x06
-#define HK_Volume 0x07
-#define ActivePAL 0x0020
-#define ActivePALShift 5
-#define ActiveNonExpanding 0x40
-#define ActiveNonExpandingShift 6
-#define ActiveOverScan 0x80
-#define ActiveOverScanShift 7
+#define HKEvent 0x0f /* CR79 */
+#define HK_ModeSwitch 0x01
+#define HK_Expanding 0x02
+#define HK_OverScan 0x03
+#define HK_Brightness 0x04
+#define HK_Contrast 0x05
+#define HK_Mute 0x06
+#define HK_Volume 0x07
+#define ActivePAL 0x0020
+#define ActivePALShift 5
+#define ActiveNonExpanding 0x40
+#define ActiveNonExpandingShift 6
+#define ActiveOverScan 0x80
+#define ActiveOverScanShift 7
-#define ModeSwitchStatus 0x0b /* SR15 */
-#define ActiveCRT1 0x01
-#define ActiveLCD 0x02
-#define ActiveCRT2 0x08
+#define ModeSwitchStatus 0x0b /* SR15 */
+#define ActiveCRT1 0x01
+#define ActiveLCD 0x02
+#define ActiveCRT2 0x08
-#define TVSwitchStatus 0xf0 /* SR16 */
-#define TVConfigShift 3
-#define ActiveTV 0x01
-#define ActiveYPbPr 0x04
-#define ActiveAVideo 0x10
-#define ActiveSVideo 0x0020
-#define ActiveSCART 0x40
-#define ActiveHiTV 0x80
+#define TVSwitchStatus 0xf0 /* SR16 */
+#define TVConfigShift 3
+#define ActiveTV 0x01
+#define ActiveYPbPr 0x04
+#define ActiveAVideo 0x10
+#define ActiveSVideo 0x0020
+#define ActiveSCART 0x40
+#define ActiveHiTV 0x80
-#define EnableHKEvent 0x01 /* CR7A */
-#define EnableOSDEvent 0x02
-#define StartOSDEvent 0x04
-#define CMOSSupport 0x08
-#define HotKeySupport 0x10
-#define IngoreHKOSDEvent 0x20
+#define EnableHKEvent 0x01 /* CR7A */
+#define EnableOSDEvent 0x02
+#define StartOSDEvent 0x04
+#define CMOSSupport 0x08
+#define HotKeySupport 0x10
+#define IngoreHKOSDEvent 0x20
#endif
/* //------------- Misc. Definition */
-#define SelectCRT1Rate 00h
+#define SelectCRT1Rate 00h
/* #define SelectCRT2Rate 04h */
-#define DDC1DelayTime 1000
-#ifdef TRUMPION
-#define DDC2DelayTime 15
+#define DDC1DelayTime 1000
+#ifdef TRUMPION
+#define DDC2DelayTime 15
#else
-#define DDC2DelayTime 150
+#define DDC2DelayTime 150
#endif
-#define R_FACTOR 04Dh
-#define G_FACTOR 097h
-#define B_FACTOR 01Ch
+#define R_FACTOR 04Dh
+#define G_FACTOR 097h
+#define B_FACTOR 01Ch
/* --------------------------------------------------------- */
/* translated from asm code 301def.h */
/* */
/* --------------------------------------------------------- */
-#define LCDDataLen 8
-#define HiTVDataLen 12
-#define TVDataLen 12
-#define LVDSCRT1Len_H 8
-#define LVDSCRT1Len_V 7
-#define LVDSDataLen 6
-#define LVDSDesDataLen 6
-#define LCDDesDataLen 6
-#define LVDSDesDataLen2 8
-#define LCDDesDataLen2 8
-#define CHTVRegLen 16
-#define CHLVRegLen 12
+#define LCDDataLen 8
+#define HiTVDataLen 12
+#define TVDataLen 12
+#define LVDSCRT1Len_H 8
+#define LVDSCRT1Len_V 7
+#define LVDSDataLen 6
+#define LVDSDesDataLen 6
+#define LCDDesDataLen 6
+#define LVDSDesDataLen2 8
+#define LCDDesDataLen2 8
+#define CHTVRegLen 16
+#define CHLVRegLen 12
-#define StHiTVHT 892
-#define StHiTVVT 1126
-#define StHiTextTVHT 1000
-#define StHiTextTVVT 1126
-#define ExtHiTVHT 2100
-#define ExtHiTVVT 1125
-#define NTSCHT 1716
-#define NTSCVT 525
-#define NTSC1024x768HT 1908
-#define NTSC1024x768VT 525
-#define PALHT 1728
-#define PALVT 625
+#define StHiTVHT 892
+#define StHiTVVT 1126
+#define StHiTextTVHT 1000
+#define StHiTextTVVT 1126
+#define ExtHiTVHT 2100
+#define ExtHiTVVT 1125
+#define NTSCHT 1716
+#define NTSCVT 525
+#define NTSC1024x768HT 1908
+#define NTSC1024x768VT 525
+#define PALHT 1728
+#define PALVT 625
-#define YPbPrTV525iHT 1716 /* YPbPr */
-#define YPbPrTV525iVT 525
-#define YPbPrTV525pHT 1716
-#define YPbPrTV525pVT 525
-#define YPbPrTV750pHT 1650
-#define YPbPrTV750pVT 750
+#define YPbPrTV525iHT 1716 /* YPbPr */
+#define YPbPrTV525iVT 525
+#define YPbPrTV525pHT 1716
+#define YPbPrTV525pVT 525
+#define YPbPrTV750pHT 1650
+#define YPbPrTV750pVT 750
-#define CRT2VCLKSel 0xc0
+#define CRT2VCLKSel 0xc0
-#define CRT2Delay1 0x04 /* XGI301 */
-#define CRT2Delay2 0x0A /* 301B,302 */
+#define CRT2Delay1 0x04 /* XGI301 */
+#define CRT2Delay2 0x0A /* 301B,302 */
-#define VCLK25_175 0x00
-#define VCLK28_322 0x01
-#define VCLK31_5 0x02
-#define VCLK36 0x03
-#define VCLK40 0x04
-#define VCLK43_163 0x05
-#define VCLK44_9 0x06
-#define VCLK49_5 0x07
-#define VCLK50 0x08
-#define VCLK52_406 0x09
-#define VCLK56_25 0x0A
-#define VCLK65 0x0B
-#define VCLK67_765 0x0C
-#define VCLK68_179 0x0D
-#define VCLK72_852 0x0E
-#define VCLK75 0x0F
-#define VCLK75_8 0x10
-#define VCLK78_75 0x11
-#define VCLK79_411 0x12
-#define VCLK83_95 0x13
-#define VCLK84_8 0x14
-#define VCLK86_6 0x15
-#define VCLK94_5 0x16
-#define VCLK104_998 0x17
-#define VCLK105_882 0x18
-#define VCLK108_2 0x19
-#define VCLK109_175 0x1A
-#define VCLK113_309 0x1B
-#define VCLK116_406 0x1C
-#define VCLK132_258 0x1D
-#define VCLK135_5 0x1E
-#define VCLK139_054 0x1F
-#define VCLK157_5 0x20
-#define VCLK162 0x21
-#define VCLK175 0x22
-#define VCLK189 0x23
-#define VCLK194_4 0x24
-#define VCLK202_5 0x25
-#define VCLK229_5 0x26
-#define VCLK234 0x27
-#define VCLK252_699 0x28
-#define VCLK254_817 0x29
-#define VCLK265_728 0x2A
-#define VCLK266_952 0x2B
-#define VCLK269_655 0x2C
-#define VCLK272_042 0x2D
-#define VCLK277_015 0x2E
-#define VCLK286_359 0x2F
-#define VCLK291_132 0x30
-#define VCLK291_766 0x31
-#define VCLK309_789 0x32
-#define VCLK315_195 0x33
-#define VCLK323_586 0x34
-#define VCLK330_615 0x35
-#define VCLK332_177 0x36
-#define VCLK340_477 0x37
-#define VCLK375_847 0x38
-#define VCLK388_631 0x39
-#define VCLK125_999 0x51
-#define VCLK148_5 0x52
-#define VCLK178_992 0x54
-#define VCLK217_325 0x55
-#define VCLK299_505 0x56
-#define YPbPr750pVCLK 0x57
+#define VCLK25_175 0x00
+#define VCLK28_322 0x01
+#define VCLK31_5 0x02
+#define VCLK36 0x03
+#define VCLK40 0x04
+#define VCLK43_163 0x05
+#define VCLK44_9 0x06
+#define VCLK49_5 0x07
+#define VCLK50 0x08
+#define VCLK52_406 0x09
+#define VCLK56_25 0x0A
+#define VCLK65 0x0B
+#define VCLK67_765 0x0C
+#define VCLK68_179 0x0D
+#define VCLK72_852 0x0E
+#define VCLK75 0x0F
+#define VCLK75_8 0x10
+#define VCLK78_75 0x11
+#define VCLK79_411 0x12
+#define VCLK83_95 0x13
+#define VCLK84_8 0x14
+#define VCLK86_6 0x15
+#define VCLK94_5 0x16
+#define VCLK104_998 0x17
+#define VCLK105_882 0x18
+#define VCLK108_2 0x19
+#define VCLK109_175 0x1A
+#define VCLK113_309 0x1B
+#define VCLK116_406 0x1C
+#define VCLK132_258 0x1D
+#define VCLK135_5 0x1E
+#define VCLK139_054 0x1F
+#define VCLK157_5 0x20
+#define VCLK162 0x21
+#define VCLK175 0x22
+#define VCLK189 0x23
+#define VCLK194_4 0x24
+#define VCLK202_5 0x25
+#define VCLK229_5 0x26
+#define VCLK234 0x27
+#define VCLK252_699 0x28
+#define VCLK254_817 0x29
+#define VCLK265_728 0x2A
+#define VCLK266_952 0x2B
+#define VCLK269_655 0x2C
+#define VCLK272_042 0x2D
+#define VCLK277_015 0x2E
+#define VCLK286_359 0x2F
+#define VCLK291_132 0x30
+#define VCLK291_766 0x31
+#define VCLK309_789 0x32
+#define VCLK315_195 0x33
+#define VCLK323_586 0x34
+#define VCLK330_615 0x35
+#define VCLK332_177 0x36
+#define VCLK340_477 0x37
+#define VCLK375_847 0x38
+#define VCLK388_631 0x39
+#define VCLK125_999 0x51
+#define VCLK148_5 0x52
+#define VCLK178_992 0x54
+#define VCLK217_325 0x55
+#define VCLK299_505 0x56
+#define YPbPr750pVCLK 0x57
-#define TVVCLKDIV2 0x3A
-#define TVVCLK 0x3B
-#define HiTVVCLKDIV2 0x3C
-#define HiTVVCLK 0x3D
-#define HiTVSimuVCLK 0x3E
-#define HiTVTextVCLK 0x3F
-#define VCLK39_77 0x40
+#define TVVCLKDIV2 0x3A
+#define TVVCLK 0x3B
+#define HiTVVCLKDIV2 0x3C
+#define HiTVVCLK 0x3D
+#define HiTVSimuVCLK 0x3E
+#define HiTVTextVCLK 0x3F
+#define VCLK39_77 0x40
/* #define YPbPr750pVCLK 0x0F */
-#define YPbPr525pVCLK 0x3A
+#define YPbPr525pVCLK 0x3A
/* #define ;;YPbPr525iVCLK 0x3B */
/* #define ;;YPbPr525iVCLK_2 0x3A */
-#define NTSC1024VCLK 0x41
-#define VCLK25_175_41 0x42 /* ; ScaleLCD */
-#define VCLK25_175_42 0x43
-#define VCLK28_322_43 0x44
-#define VCLK40_44 0x45
-#define VCLKQVGA_1 0x46 /* ; QVGA */
-#define VCLKQVGA_2 0x47
-#define VCLKQVGA_3 0x48
-#define VCLK35_2 0x49 /* ; 800x480 */
-#define VCLK122_61 0x4A
-#define VCLK80_350 0x4B
-#define VCLK107_385 0x4C
+#define NTSC1024VCLK 0x41
+#define VCLK25_175_41 0x42 /* ; ScaleLCD */
+#define VCLK25_175_42 0x43
+#define VCLK28_322_43 0x44
+#define VCLK40_44 0x45
+#define VCLKQVGA_1 0x46 /* ; QVGA */
+#define VCLKQVGA_2 0x47
+#define VCLKQVGA_3 0x48
+#define VCLK35_2 0x49 /* ; 800x480 */
+#define VCLK122_61 0x4A
+#define VCLK80_350 0x4B
+#define VCLK107_385 0x4C
-#define CHTVVCLK30_2 0x50 /* ;;CHTV */
-#define CHTVVCLK28_1 0x51
-#define CHTVVCLK43_6 0x52
-#define CHTVVCLK26_4 0x53
-#define CHTVVCLK24_6 0x54
-#define CHTVVCLK47_8 0x55
-#define CHTVVCLK31_5 0x56
-#define CHTVVCLK26_2 0x57
-#define CHTVVCLK39 0x58
-#define CHTVVCLK36 0x59
+#define CHTVVCLK30_2 0x50 /* ;;CHTV */
+#define CHTVVCLK28_1 0x51
+#define CHTVVCLK43_6 0x52
+#define CHTVVCLK26_4 0x53
+#define CHTVVCLK24_6 0x54
+#define CHTVVCLK47_8 0x55
+#define CHTVVCLK31_5 0x56
+#define CHTVVCLK26_2 0x57
+#define CHTVVCLK39 0x58
+#define CHTVVCLK36 0x59
-#define CH7007TVVCLK30_2 0x00 /* [Billy] 2007/05/18 For CH7007 */
-#define CH7007TVVCLK28_1 0x01
-#define CH7007TVVCLK43_6 0x02
-#define CH7007TVVCLK26_4 0x03
-#define CH7007TVVCLK24_6 0x04
-#define CH7007TVVCLK47_8 0x05
-#define CH7007TVVCLK31_5 0x06
-#define CH7007TVVCLK26_2 0x07
-#define CH7007TVVCLK39 0x08
-#define CH7007TVVCLK36 0x09
+#define CH7007TVVCLK30_2 0x00 /* [Billy] 2007/05/18 For CH7007 */
+#define CH7007TVVCLK28_1 0x01
+#define CH7007TVVCLK43_6 0x02
+#define CH7007TVVCLK26_4 0x03
+#define CH7007TVVCLK24_6 0x04
+#define CH7007TVVCLK47_8 0x05
+#define CH7007TVVCLK31_5 0x06
+#define CH7007TVVCLK26_2 0x07
+#define CH7007TVVCLK39 0x08
+#define CH7007TVVCLK36 0x09
-#define RES320x200 0x00
-#define RES320x240 0x01
-#define RES400x300 0x02
-#define RES512x384 0x03
-#define RES640x400 0x04
-#define RES640x480x60 0x05
-#define RES640x480x72 0x06
-#define RES640x480x75 0x07
-#define RES640x480x85 0x08
-#define RES640x480x100 0x09
-#define RES640x480x120 0x0A
-#define RES640x480x160 0x0B
-#define RES640x480x200 0x0C
-#define RES800x600x56 0x0D
-#define RES800x600x60 0x0E
-#define RES800x600x72 0x0F
-#define RES800x600x75 0x10
-#define RES800x600x85 0x11
-#define RES800x600x100 0x12
-#define RES800x600x120 0x13
-#define RES800x600x160 0x14
-#define RES1024x768x43 0x15
-#define RES1024x768x60 0x16
-#define RES1024x768x70 0x17
-#define RES1024x768x75 0x18
-#define RES1024x768x85 0x19
-#define RES1024x768x100 0x1A
-#define RES1024x768x120 0x1B
-#define RES1280x1024x43 0x1C
-#define RES1280x1024x60 0x1D
-#define RES1280x1024x75 0x1E
-#define RES1280x1024x85 0x1F
-#define RES1600x1200x60 0x20
-#define RES1600x1200x65 0x21
-#define RES1600x1200x70 0x22
-#define RES1600x1200x75 0x23
-#define RES1600x1200x85 0x24
-#define RES1600x1200x100 0x25
-#define RES1600x1200x120 0x26
-#define RES1920x1440x60 0x27
-#define RES1920x1440x65 0x28
-#define RES1920x1440x70 0x29
-#define RES1920x1440x75 0x2A
-#define RES1920x1440x85 0x2B
-#define RES1920x1440x100 0x2C
-#define RES2048x1536x60 0x2D
-#define RES2048x1536x65 0x2E
-#define RES2048x1536x70 0x2F
-#define RES2048x1536x75 0x30
-#define RES2048x1536x85 0x31
-#define RES800x480x60 0x32
-#define RES800x480x75 0x33
-#define RES800x480x85 0x34
-#define RES1024x576x60 0x35
-#define RES1024x576x75 0x36
-#define RES1024x576x85 0x37
-#define RES1280x720x60 0x38
-#define RES1280x720x75 0x39
-#define RES1280x720x85 0x3A
-#define RES1280x960x60 0x3B
-#define RES720x480x60 0x3C
-#define RES720x576x56 0x3D
-#define RES856x480x79I 0x3E
-#define RES856x480x60 0x3F
-#define RES1280x768x60 0x40
-#define RES1400x1050x60 0x41
-#define RES1152x864x60 0x42
-#define RES1152x864x75 0x43
-#define RES1024x768x160 0x44
-#define RES1280x960x75 0x45
-#define RES1280x960x85 0x46
-#define RES1280x960x120 0x47
+#define RES320x200 0x00
+#define RES320x240 0x01
+#define RES400x300 0x02
+#define RES512x384 0x03
+#define RES640x400 0x04
+#define RES640x480x60 0x05
+#define RES640x480x72 0x06
+#define RES640x480x75 0x07
+#define RES640x480x85 0x08
+#define RES640x480x100 0x09
+#define RES640x480x120 0x0A
+#define RES640x480x160 0x0B
+#define RES640x480x200 0x0C
+#define RES800x600x56 0x0D
+#define RES800x600x60 0x0E
+#define RES800x600x72 0x0F
+#define RES800x600x75 0x10
+#define RES800x600x85 0x11
+#define RES800x600x100 0x12
+#define RES800x600x120 0x13
+#define RES800x600x160 0x14
+#define RES1024x768x43 0x15
+#define RES1024x768x60 0x16
+#define RES1024x768x70 0x17
+#define RES1024x768x75 0x18
+#define RES1024x768x85 0x19
+#define RES1024x768x100 0x1A
+#define RES1024x768x120 0x1B
+#define RES1280x1024x43 0x1C
+#define RES1280x1024x60 0x1D
+#define RES1280x1024x75 0x1E
+#define RES1280x1024x85 0x1F
+#define RES1600x1200x60 0x20
+#define RES1600x1200x65 0x21
+#define RES1600x1200x70 0x22
+#define RES1600x1200x75 0x23
+#define RES1600x1200x85 0x24
+#define RES1600x1200x100 0x25
+#define RES1600x1200x120 0x26
+#define RES1920x1440x60 0x27
+#define RES1920x1440x65 0x28
+#define RES1920x1440x70 0x29
+#define RES1920x1440x75 0x2A
+#define RES1920x1440x85 0x2B
+#define RES1920x1440x100 0x2C
+#define RES2048x1536x60 0x2D
+#define RES2048x1536x65 0x2E
+#define RES2048x1536x70 0x2F
+#define RES2048x1536x75 0x30
+#define RES2048x1536x85 0x31
+#define RES800x480x60 0x32
+#define RES800x480x75 0x33
+#define RES800x480x85 0x34
+#define RES1024x576x60 0x35
+#define RES1024x576x75 0x36
+#define RES1024x576x85 0x37
+#define RES1280x720x60 0x38
+#define RES1280x720x75 0x39
+#define RES1280x720x85 0x3A
+#define RES1280x960x60 0x3B
+#define RES720x480x60 0x3C
+#define RES720x576x56 0x3D
+#define RES856x480x79I 0x3E
+#define RES856x480x60 0x3F
+#define RES1280x768x60 0x40
+#define RES1400x1050x60 0x41
+#define RES1152x864x60 0x42
+#define RES1152x864x75 0x43
+#define RES1024x768x160 0x44
+#define RES1280x960x75 0x45
+#define RES1280x960x85 0x46
+#define RES1280x960x120 0x47
-#define LFBDRAMTrap 0x30
+#define LFBDRAMTrap 0x30
#endif
diff --git a/drivers/staging/xgifb/vb_ext.c b/drivers/staging/xgifb/vb_ext.c
index d7c1b2e..7e1f76a 100644
--- a/drivers/staging/xgifb/vb_ext.c
+++ b/drivers/staging/xgifb/vb_ext.c
@@ -1,5 +1,5 @@
#include <linux/version.h>
-#include <asm/io.h>
+#include <linux/io.h>
#include <linux/types.h>
#include "XGIfb.h"
@@ -26,7 +26,9 @@
return 1;
}
-static unsigned char XGINew_Sense(unsigned short tempbx, unsigned short tempcx, struct vb_device_info *pVBInfo)
+static unsigned char XGINew_Sense(unsigned short tempbx,
+ unsigned short tempcx,
+ struct vb_device_info *pVBInfo)
{
unsigned short temp, i, tempch;
@@ -50,7 +52,9 @@
return 0;
}
-static unsigned char XGINew_GetLCDDDCInfo(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo)
+static unsigned char
+XGINew_GetLCDDDCInfo(struct xgi_hw_device_info *HwDeviceExtension,
+ struct vb_device_info *pVBInfo)
{
unsigned short temp;
@@ -154,7 +158,9 @@
}
}
-static unsigned char XGINew_BridgeIsEnable(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo)
+static unsigned char
+XGINew_BridgeIsEnable(struct xgi_hw_device_info *HwDeviceExtension,
+ struct vb_device_info *pVBInfo)
{
unsigned short flag;
@@ -170,7 +176,9 @@
return 0;
}
-static unsigned char XGINew_SenseHiTV(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo)
+static unsigned char
+XGINew_SenseHiTV(struct xgi_hw_device_info *HwDeviceExtension,
+ struct vb_device_info *pVBInfo)
{
unsigned short tempbx, tempcx, temp, i, tempch;
@@ -238,21 +246,29 @@
}
}
-void XGI_GetSenseStatus(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo)
+void XGI_GetSenseStatus(struct xgi_hw_device_info *HwDeviceExtension,
+ struct vb_device_info *pVBInfo)
{
- unsigned short tempax = 0, tempbx, tempcx, temp, P2reg0 = 0, SenseModeNo = 0,
- OutputSelect = *pVBInfo->pOutputSelect, ModeIdIndex, i;
+ unsigned short tempax = 0, tempbx, tempcx, temp,
+ P2reg0 = 0, SenseModeNo = 0,
+ OutputSelect = *pVBInfo->pOutputSelect,
+ ModeIdIndex, i;
pVBInfo->BaseAddr = (unsigned long) HwDeviceExtension->pjIOAddress;
if (pVBInfo->IF_DEF_LVDS == 1) {
- tempax = xgifb_reg_get(pVBInfo->P3c4, 0x1A); /* ynlai 02/27/2002 */
+ /* ynlai 02/27/2002 */
+ tempax = xgifb_reg_get(pVBInfo->P3c4, 0x1A);
tempbx = xgifb_reg_get(pVBInfo->P3c4, 0x1B);
tempax = ((tempax & 0xFE) >> 1) | (tempbx << 8);
if (tempax == 0x00) { /* Get Panel id from DDC */
temp = XGINew_GetLCDDDCInfo(HwDeviceExtension, pVBInfo);
if (temp == 1) { /* LCD connect */
- xgifb_reg_and_or(pVBInfo->P3d4, 0x39, 0xFF, 0x01); /* set CR39 bit0="1" */
- xgifb_reg_and_or(pVBInfo->P3d4, 0x37, 0xEF, 0x00); /* clean CR37 bit4="0" */
+ /* set CR39 bit0="1" */
+ xgifb_reg_and_or(pVBInfo->P3d4,
+ 0x39, 0xFF, 0x01);
+ /* clean CR37 bit4="0" */
+ xgifb_reg_and_or(pVBInfo->P3d4,
+ 0x37, 0xEF, 0x00);
temp = LCDSense;
} else { /* LCD don't connect */
temp = 0;
@@ -273,25 +289,47 @@
xgifb_reg_and_or(pVBInfo->P3d4, 0x32, 0xA0, temp);
} else {
if (XGI_BridgeIsOn(pVBInfo)) {
- P2reg0 = xgifb_reg_get(pVBInfo->Part2Port, 0x00);
- if (!XGINew_BridgeIsEnable(HwDeviceExtension, pVBInfo)) {
+ P2reg0 = xgifb_reg_get(pVBInfo->Part2Port,
+ 0x00);
+ if (!XGINew_BridgeIsEnable(HwDeviceExtension,
+ pVBInfo)) {
SenseModeNo = 0x2e;
- /* xgifb_reg_set(pVBInfo->P3d4, 0x30, 0x41); */
- /* XGISetModeNew(HwDeviceExtension, 0x2e); // ynlai InitMode */
+ /* xgifb_reg_set(pVBInfo->P3d4, 0x30, 0x41);
+ * XGISetModeNew(HwDeviceExtension, 0x2e);
+ * // ynlai InitMode */
- temp = XGI_SearchModeID(SenseModeNo, &ModeIdIndex, pVBInfo);
- XGI_GetVGAType(HwDeviceExtension, pVBInfo);
+ temp = XGI_SearchModeID(SenseModeNo,
+ &ModeIdIndex,
+ pVBInfo);
+ XGI_GetVGAType(HwDeviceExtension,
+ pVBInfo);
XGI_GetVBType(pVBInfo);
pVBInfo->SetFlag = 0x00;
pVBInfo->ModeType = ModeVGA;
- pVBInfo->VBInfo = SetCRT2ToRAMDAC | LoadDACFlag | SetInSlaveMode;
- XGI_GetLCDInfo(0x2e, ModeIdIndex, pVBInfo);
- XGI_GetTVInfo(0x2e, ModeIdIndex, pVBInfo);
- XGI_EnableBridge(HwDeviceExtension, pVBInfo);
- XGI_SetCRT2Group301(SenseModeNo, HwDeviceExtension, pVBInfo);
- XGI_SetCRT2ModeRegs(0x2e, HwDeviceExtension, pVBInfo);
- /* XGI_DisableBridge( HwDeviceExtension, pVBInfo ) ; */
- xgifb_reg_and_or(pVBInfo->P3c4, 0x01, 0xDF, 0x20); /* Display Off 0212 */
+ pVBInfo->VBInfo = SetCRT2ToRAMDAC |
+ LoadDACFlag |
+ SetInSlaveMode;
+ XGI_GetLCDInfo(0x2e,
+ ModeIdIndex,
+ pVBInfo);
+ XGI_GetTVInfo(0x2e,
+ ModeIdIndex,
+ pVBInfo);
+ XGI_EnableBridge(HwDeviceExtension,
+ pVBInfo);
+ XGI_SetCRT2Group301(SenseModeNo,
+ HwDeviceExtension,
+ pVBInfo);
+ XGI_SetCRT2ModeRegs(0x2e,
+ HwDeviceExtension,
+ pVBInfo);
+ /* XGI_DisableBridge(HwDeviceExtension,
+ * pVBInfo ) ; */
+ /* Display Off 0212 */
+ xgifb_reg_and_or(pVBInfo->P3c4,
+ 0x01,
+ 0xDF,
+ 0x20);
for (i = 0; i < 20; i++)
XGI_LongWait(pVBInfo);
}
@@ -304,29 +342,38 @@
tempcx = 0x0E08;
if (XGINew_Sense(tempbx, tempcx, pVBInfo)) {
- if (XGINew_Sense(tempbx, tempcx, pVBInfo))
+ if (XGINew_Sense(tempbx,
+ tempcx,
+ pVBInfo))
tempax |= Monitor2Sense;
}
if (pVBInfo->VBType & VB_XGI301C)
- xgifb_reg_or(pVBInfo->Part4Port, 0x0d, 0x04);
+ xgifb_reg_or(pVBInfo->Part4Port,
+ 0x0d,
+ 0x04);
- if (XGINew_SenseHiTV(HwDeviceExtension, pVBInfo)) { /* add by kuku for Multi-adapter sense HiTV */
+ /* add by kuku for Multi-adapter sense HiTV */
+ if (XGINew_SenseHiTV(HwDeviceExtension,
+ pVBInfo)) {
tempax |= HiTVSense;
if ((pVBInfo->VBType & VB_XGI301C))
- tempax ^= (HiTVSense | YPbPrSense);
+ tempax ^= (HiTVSense |
+ YPbPrSense);
}
- if (!(tempax & (HiTVSense | YPbPrSense))) { /* start */
-
+ /* start */
+ if (!(tempax & (HiTVSense | YPbPrSense))) {
tempbx = *pVBInfo->pYCSenseData;
-
if (!(XGINew_Is301B(pVBInfo)))
tempbx = *pVBInfo->pYCSenseData2;
-
tempcx = 0x0604;
- if (XGINew_Sense(tempbx, tempcx, pVBInfo)) {
- if (XGINew_Sense(tempbx, tempcx, pVBInfo))
+ if (XGINew_Sense(tempbx,
+ tempcx,
+ pVBInfo)) {
+ if (XGINew_Sense(tempbx,
+ tempcx,
+ pVBInfo))
tempax |= SVIDEOSense;
}
@@ -337,8 +384,12 @@
tempbx = *pVBInfo->pVideoSenseData2;
tempcx = 0x0804;
- if (XGINew_Sense(tempbx, tempcx, pVBInfo)) {
- if (XGINew_Sense(tempbx, tempcx, pVBInfo))
+ if (XGINew_Sense(tempbx,
+ tempcx,
+ pVBInfo)) {
+ if (XGINew_Sense(tempbx,
+ tempcx,
+ pVBInfo))
tempax |= AVIDEOSense;
}
} else {
@@ -349,7 +400,9 @@
tempbx = *pVBInfo->pVideoSenseData2;
tempcx = 0x0804;
- if (XGINew_Sense(tempbx, tempcx, pVBInfo)) {
+ if (XGINew_Sense(tempbx,
+ tempcx,
+ pVBInfo)) {
if (XGINew_Sense(tempbx, tempcx, pVBInfo))
tempax |= AVIDEOSense;
}
@@ -370,7 +423,9 @@
if (!(P2reg0 & 0x20)) {
pVBInfo->VBInfo = DisableCRT2Display;
- /* XGI_SetCRT2Group301(SenseModeNo, HwDeviceExtension, pVBInfo); */
+ /* XGI_SetCRT2Group301(SenseModeNo,
+ * HwDeviceExtension,
+ * pVBInfo); */
}
}
}
@@ -378,7 +433,8 @@
}
-unsigned short XGINew_SenseLCD(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo)
+unsigned short XGINew_SenseLCD(struct xgi_hw_device_info *HwDeviceExtension,
+ struct vb_device_info *pVBInfo)
{
/* unsigned short SoftSetting ; */
unsigned short temp;
diff --git a/drivers/staging/xgifb/vb_ext.h b/drivers/staging/xgifb/vb_ext.h
index cabe365..814a446 100644
--- a/drivers/staging/xgifb/vb_ext.h
+++ b/drivers/staging/xgifb/vb_ext.h
@@ -1,27 +1,28 @@
-#ifndef _VBEXT_
-#define _VBEXT_
+#ifndef _VBEXT_
+#define _VBEXT_
struct DWORDREGS {
- unsigned long Eax, Ebx, Ecx, Edx, Esi, Edi, Ebp;
+ unsigned long Eax, Ebx, Ecx, Edx, Esi, Edi, Ebp;
};
struct WORDREGS {
- unsigned short ax, hi_ax, bx, hi_bx, cx, hi_cx, dx, hi_dx, si,
- hi_si, di, hi_di, bp, hi_bp;
+ unsigned short ax, hi_ax, bx, hi_bx, cx, hi_cx, dx, hi_dx, si,
+ hi_si, di, hi_di, bp, hi_bp;
};
struct BYTEREGS {
- unsigned char al, ah, hi_al, hi_ah, bl, bh, hi_bl, hi_bh, cl, ch,
- hi_cl, hi_ch, dl, dh, hi_dl, hi_dh;
+ unsigned char al, ah, hi_al, hi_ah, bl, bh, hi_bl, hi_bh, cl, ch,
+ hi_cl, hi_ch, dl, dh, hi_dl, hi_dh;
};
-typedef union _X86_REGS {
- struct DWORDREGS e;
- struct WORDREGS x;
- struct BYTEREGS h;
+typedef union _X86_REGS {
+ struct DWORDREGS e;
+ struct WORDREGS x;
+ struct BYTEREGS h;
} X86_REGS, *PX86_REGS;
-extern void XGI_GetSenseStatus(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *pVBInfo);
+extern void XGI_GetSenseStatus(struct xgi_hw_device_info *HwDeviceExtension,
+ struct vb_device_info *pVBInfo);
extern unsigned short XGINew_SenseLCD(struct xgi_hw_device_info *,
struct vb_device_info *pVBInfo);
diff --git a/drivers/staging/xgifb/vb_init.c b/drivers/staging/xgifb/vb_init.c
index 61d1370..33c6876 100644
--- a/drivers/staging/xgifb/vb_init.c
+++ b/drivers/staging/xgifb/vb_init.c
@@ -13,7 +13,7 @@
#include "vb_ext.h"
-#include <asm/io.h>
+#include <linux/io.h>
static unsigned char XGINew_ChannelAB, XGINew_DataBusWidth;
@@ -39,8 +39,9 @@
static int XGINew_RAMType;
-static unsigned char XGINew_GetXG20DRAMType(struct xgi_hw_device_info *HwDeviceExtension,
- struct vb_device_info *pVBInfo)
+static unsigned char
+XGINew_GetXG20DRAMType(struct xgi_hw_device_info *HwDeviceExtension,
+ struct vb_device_info *pVBInfo)
{
unsigned char data, temp;
@@ -50,10 +51,9 @@
return data;
} else {
data = xgifb_reg_get(pVBInfo->P3c4, 0x39) & 0x02;
-
if (data == 0)
- data = (xgifb_reg_get(pVBInfo->P3c4, 0x3A) & 0x02) >> 1;
-
+ data = (xgifb_reg_get(pVBInfo->P3c4, 0x3A) &
+ 0x02) >> 1;
return data;
}
} else if (HwDeviceExtension->jChipType == XG27) {
@@ -62,19 +62,22 @@
return data;
}
temp = xgifb_reg_get(pVBInfo->P3c4, 0x3B);
-
- if ((temp & 0x88) == 0x80) /* SR3B[7][3]MAA15 MAA11 (Power on Trapping) */
+ /* SR3B[7][3]MAA15 MAA11 (Power on Trapping) */
+ if ((temp & 0x88) == 0x80)
data = 0; /* DDR */
else
data = 1; /* DDRII */
return data;
} else if (HwDeviceExtension->jChipType == XG21) {
- xgifb_reg_and(pVBInfo->P3d4, 0xB4, ~0x02); /* Independent GPIO control */
+ /* Independent GPIO control */
+ xgifb_reg_and(pVBInfo->P3d4, 0xB4, ~0x02);
udelay(800);
xgifb_reg_or(pVBInfo->P3d4, 0x4A, 0x80); /* Enable GPIOH read */
- temp = xgifb_reg_get(pVBInfo->P3d4, 0x48); /* GPIOF 0:DVI 1:DVO */
+ /* GPIOF 0:DVI 1:DVO */
+ temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
/* HOTPLUG_SUPPORT */
- /* for current XG20 & XG21, GPIOH is floating, driver will fix DDR temporarily */
+ /* for current XG20 & XG21, GPIOH is floating, driver will
+ * fix DDR temporarily */
if (temp & 0x01) /* DVI read GPIOH */
data = 1; /* DDRII */
else
@@ -92,7 +95,8 @@
}
}
-static void XGINew_DDR1x_MRS_340(unsigned long P3c4, struct vb_device_info *pVBInfo)
+static void XGINew_DDR1x_MRS_340(unsigned long P3c4,
+ struct vb_device_info *pVBInfo)
{
xgifb_reg_set(P3c4, 0x18, 0x01);
xgifb_reg_set(P3c4, 0x19, 0x20);
@@ -126,24 +130,42 @@
struct vb_device_info *pVBInfo)
{
- xgifb_reg_set(pVBInfo->P3c4, 0x28, pVBInfo->MCLKData[XGINew_RAMType].SR28);
- xgifb_reg_set(pVBInfo->P3c4, 0x29, pVBInfo->MCLKData[XGINew_RAMType].SR29);
- xgifb_reg_set(pVBInfo->P3c4, 0x2A, pVBInfo->MCLKData[XGINew_RAMType].SR2A);
+ xgifb_reg_set(pVBInfo->P3c4,
+ 0x28,
+ pVBInfo->MCLKData[XGINew_RAMType].SR28);
+ xgifb_reg_set(pVBInfo->P3c4,
+ 0x29,
+ pVBInfo->MCLKData[XGINew_RAMType].SR29);
+ xgifb_reg_set(pVBInfo->P3c4,
+ 0x2A,
+ pVBInfo->MCLKData[XGINew_RAMType].SR2A);
- xgifb_reg_set(pVBInfo->P3c4, 0x2E, pVBInfo->ECLKData[XGINew_RAMType].SR2E);
- xgifb_reg_set(pVBInfo->P3c4, 0x2F, pVBInfo->ECLKData[XGINew_RAMType].SR2F);
- xgifb_reg_set(pVBInfo->P3c4, 0x30, pVBInfo->ECLKData[XGINew_RAMType].SR30);
+ xgifb_reg_set(pVBInfo->P3c4,
+ 0x2E,
+ pVBInfo->ECLKData[XGINew_RAMType].SR2E);
+ xgifb_reg_set(pVBInfo->P3c4,
+ 0x2F,
+ pVBInfo->ECLKData[XGINew_RAMType].SR2F);
+ xgifb_reg_set(pVBInfo->P3c4,
+ 0x30,
+ pVBInfo->ECLKData[XGINew_RAMType].SR30);
- /* [Vicent] 2004/07/07, When XG42 ECLK = MCLK = 207MHz, Set SR32 D[1:0] = 10b */
- /* [Hsuan] 2004/08/20, Modify SR32 value, when MCLK=207MHZ, ELCK=250MHz, Set SR32 D[1:0] = 10b */
+ /* [Vicent] 2004/07/07,
+ * When XG42 ECLK = MCLK = 207MHz, Set SR32 D[1:0] = 10b */
+ /* [Hsuan] 2004/08/20,
+ * Modify SR32 value, when MCLK=207MHZ, ELCK=250MHz,
+ * Set SR32 D[1:0] = 10b */
if (HwDeviceExtension->jChipType == XG42) {
- if ((pVBInfo->MCLKData[XGINew_RAMType].SR28 == 0x1C)
- && (pVBInfo->MCLKData[XGINew_RAMType].SR29 == 0x01)
- && (((pVBInfo->ECLKData[XGINew_RAMType].SR2E == 0x1C)
- && (pVBInfo->ECLKData[XGINew_RAMType].SR2F == 0x01))
- || ((pVBInfo->ECLKData[XGINew_RAMType].SR2E == 0x22)
- && (pVBInfo->ECLKData[XGINew_RAMType].SR2F == 0x01))))
- xgifb_reg_set(pVBInfo->P3c4, 0x32, ((unsigned char) xgifb_reg_get(pVBInfo->P3c4, 0x32) & 0xFC) | 0x02);
+ if ((pVBInfo->MCLKData[XGINew_RAMType].SR28 == 0x1C) &&
+ (pVBInfo->MCLKData[XGINew_RAMType].SR29 == 0x01) &&
+ (((pVBInfo->ECLKData[XGINew_RAMType].SR2E == 0x1C) &&
+ (pVBInfo->ECLKData[XGINew_RAMType].SR2F == 0x01)) ||
+ ((pVBInfo->ECLKData[XGINew_RAMType].SR2E == 0x22) &&
+ (pVBInfo->ECLKData[XGINew_RAMType].SR2F == 0x01))))
+ xgifb_reg_set(pVBInfo->P3c4,
+ 0x32,
+ ((unsigned char) xgifb_reg_get(
+ pVBInfo->P3c4, 0x32) & 0xFC) | 0x02);
}
}
@@ -152,7 +174,8 @@
unsigned long P3c4, struct vb_device_info *pVBInfo)
{
unsigned long P3d4 = P3c4 + 0x10;
- XGINew_RAMType = (int) XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
+ XGINew_RAMType = (int) XGINew_GetXG20DRAMType(HwDeviceExtension,
+ pVBInfo);
XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
/* Set Double Frequency */
@@ -216,7 +239,8 @@
xgifb_reg_set(P3c4, 0x16, 0xA0); /* Set SR16 */
udelay(15);
- xgifb_reg_set(P3c4, 0x1B, 0x04); /* Set SR1B refresh control 000:close; 010:open */
+ /* Set SR1B refresh control 000:close; 010:open */
+ xgifb_reg_set(P3c4, 0x1B, 0x04);
udelay(200);
}
@@ -226,7 +250,8 @@
{
unsigned long P3d4 = P3c4 + 0x10;
- XGINew_RAMType = (int) XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
+ XGINew_RAMType = (int) XGINew_GetXG20DRAMType(HwDeviceExtension,
+ pVBInfo);
XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
xgifb_reg_set(P3d4, 0x97, 0x11); /* CR97 */
@@ -268,9 +293,9 @@
udelay(200);
}
-static void XGINew_DDR1x_MRS_XG20(unsigned long P3c4, struct vb_device_info *pVBInfo)
+static void XGINew_DDR1x_MRS_XG20(unsigned long P3c4,
+ struct vb_device_info *pVBInfo)
{
-
xgifb_reg_set(P3c4, 0x18, 0x01);
xgifb_reg_set(P3c4, 0x19, 0x40);
xgifb_reg_set(P3c4, 0x16, 0x00);
@@ -306,9 +331,15 @@
if (HwDeviceExtension->jChipType >= XG20) {
XGINew_SetMemoryClock(HwDeviceExtension, pVBInfo);
- xgifb_reg_set(P3d4, 0x82, pVBInfo->CR40[11][XGINew_RAMType]); /* CR82 */
- xgifb_reg_set(P3d4, 0x85, pVBInfo->CR40[12][XGINew_RAMType]); /* CR85 */
- xgifb_reg_set(P3d4, 0x86, pVBInfo->CR40[13][XGINew_RAMType]); /* CR86 */
+ xgifb_reg_set(P3d4,
+ 0x82,
+ pVBInfo->CR40[11][XGINew_RAMType]); /* CR82 */
+ xgifb_reg_set(P3d4,
+ 0x85,
+ pVBInfo->CR40[12][XGINew_RAMType]); /* CR85 */
+ xgifb_reg_set(P3d4,
+ 0x86,
+ pVBInfo->CR40[13][XGINew_RAMType]); /* CR86 */
xgifb_reg_set(P3d4, 0x98, 0x01);
xgifb_reg_set(P3d4, 0x9A, 0x02);
@@ -320,24 +351,46 @@
switch (HwDeviceExtension->jChipType) {
case XG41:
case XG42:
- xgifb_reg_set(P3d4, 0x82, pVBInfo->CR40[11][XGINew_RAMType]); /* CR82 */
- xgifb_reg_set(P3d4, 0x85, pVBInfo->CR40[12][XGINew_RAMType]); /* CR85 */
- xgifb_reg_set(P3d4, 0x86, pVBInfo->CR40[13][XGINew_RAMType]); /* CR86 */
+ /* CR82 */
+ xgifb_reg_set(P3d4,
+ 0x82,
+ pVBInfo->CR40[11][XGINew_RAMType]);
+ /* CR85 */
+ xgifb_reg_set(P3d4,
+ 0x85,
+ pVBInfo->CR40[12][XGINew_RAMType]);
+ /* CR86 */
+ xgifb_reg_set(P3d4,
+ 0x86,
+ pVBInfo->CR40[13][XGINew_RAMType]);
break;
default:
xgifb_reg_set(P3d4, 0x82, 0x88);
xgifb_reg_set(P3d4, 0x86, 0x00);
- xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
+ /* Insert read command for delay */
+ xgifb_reg_get(P3d4, 0x86);
xgifb_reg_set(P3d4, 0x86, 0x88);
xgifb_reg_get(P3d4, 0x86);
- xgifb_reg_set(P3d4, 0x86, pVBInfo->CR40[13][XGINew_RAMType]);
+ xgifb_reg_set(P3d4,
+ 0x86,
+ pVBInfo->CR40[13][XGINew_RAMType]);
xgifb_reg_set(P3d4, 0x82, 0x77);
xgifb_reg_set(P3d4, 0x85, 0x00);
- xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
+
+ /* Insert read command for delay */
+ xgifb_reg_get(P3d4, 0x85);
xgifb_reg_set(P3d4, 0x85, 0x88);
- xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
- xgifb_reg_set(P3d4, 0x85, pVBInfo->CR40[12][XGINew_RAMType]); /* CR85 */
- xgifb_reg_set(P3d4, 0x82, pVBInfo->CR40[11][XGINew_RAMType]); /* CR82 */
+
+ /* Insert read command for delay */
+ xgifb_reg_get(P3d4, 0x85);
+ /* CR85 */
+ xgifb_reg_set(P3d4,
+ 0x85,
+ pVBInfo->CR40[12][XGINew_RAMType]);
+ /* CR82 */
+ xgifb_reg_set(P3d4,
+ 0x82,
+ pVBInfo->CR40[11][XGINew_RAMType]);
break;
}
@@ -354,13 +407,15 @@
{
unsigned long P3d4 = Port, P3c4 = Port - 0x10;
- /* keep following setting sequence, each setting in the same reg insert idle */
+ /* keep following setting sequence, each setting in
+ * the same reg insert idle */
xgifb_reg_set(P3d4, 0x82, 0x77);
xgifb_reg_set(P3d4, 0x86, 0x00);
xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
xgifb_reg_set(P3d4, 0x86, 0x88);
xgifb_reg_get(P3d4, 0x86); /* Insert read command for delay */
- xgifb_reg_set(P3d4, 0x86, pVBInfo->CR40[13][XGINew_RAMType]); /* CR86 */
+ /* CR86 */
+ xgifb_reg_set(P3d4, 0x86, pVBInfo->CR40[13][XGINew_RAMType]);
xgifb_reg_set(P3d4, 0x82, 0x77);
xgifb_reg_set(P3d4, 0x85, 0x00);
xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
@@ -368,7 +423,8 @@
xgifb_reg_get(P3d4, 0x85); /* Insert read command for delay */
xgifb_reg_set(P3d4, 0x85, pVBInfo->CR40[12][XGINew_RAMType]); /* CR85 */
if (HwDeviceExtension->jChipType == XG27)
- xgifb_reg_set(P3d4, 0x82, pVBInfo->CR40[11][XGINew_RAMType]); /* CR82 */
+ /* CR82 */
+ xgifb_reg_set(P3d4, 0x82, pVBInfo->CR40[11][XGINew_RAMType]);
else
xgifb_reg_set(P3d4, 0x82, 0xA8); /* CR82 */
@@ -395,12 +451,14 @@
temp2 = 0;
for (i = 0; i < 4; i++) {
- temp = pVBInfo->CR6B[XGINew_RAMType][i]; /* CR6B DQS fine tune delay */
+ /* CR6B DQS fine tune delay */
+ temp = pVBInfo->CR6B[XGINew_RAMType][i];
for (j = 0; j < 4; j++) {
temp1 = ((temp >> (2 * j)) & 0x03) << 2;
temp2 |= temp1;
xgifb_reg_set(P3d4, 0x6B, temp2);
- xgifb_reg_get(P3d4, 0x6B); /* Insert read command for delay */
+ /* Insert read command for delay */
+ xgifb_reg_get(P3d4, 0x6B);
temp2 &= 0xF0;
temp2 += 0x10;
}
@@ -408,12 +466,14 @@
temp2 = 0;
for (i = 0; i < 4; i++) {
- temp = pVBInfo->CR6E[XGINew_RAMType][i]; /* CR6E DQM fine tune delay */
+ /* CR6E DQM fine tune delay */
+ temp = pVBInfo->CR6E[XGINew_RAMType][i];
for (j = 0; j < 4; j++) {
temp1 = ((temp >> (2 * j)) & 0x03) << 2;
temp2 |= temp1;
xgifb_reg_set(P3d4, 0x6E, temp2);
- xgifb_reg_get(P3d4, 0x6E); /* Insert read command for delay */
+ /* Insert read command for delay */
+ xgifb_reg_get(P3d4, 0x6E);
temp2 &= 0xF0;
temp2 += 0x10;
}
@@ -421,15 +481,18 @@
temp3 = 0;
for (k = 0; k < 4; k++) {
- xgifb_reg_and_or(P3d4, 0x6E, 0xFC, temp3); /* CR6E_D[1:0] select channel */
+ /* CR6E_D[1:0] select channel */
+ xgifb_reg_and_or(P3d4, 0x6E, 0xFC, temp3);
temp2 = 0;
for (i = 0; i < 8; i++) {
- temp = pVBInfo->CR6F[XGINew_RAMType][8 * k + i]; /* CR6F DQ fine tune delay */
+ /* CR6F DQ fine tune delay */
+ temp = pVBInfo->CR6F[XGINew_RAMType][8 * k + i];
for (j = 0; j < 4; j++) {
temp1 = (temp >> (2 * j)) & 0x03;
temp2 |= temp1;
xgifb_reg_set(P3d4, 0x6F, temp2);
- xgifb_reg_get(P3d4, 0x6F); /* Insert read command for delay */
+ /* Insert read command for delay */
+ xgifb_reg_get(P3d4, 0x6F);
temp2 &= 0xF8;
temp2 += 0x08;
}
@@ -441,7 +504,8 @@
xgifb_reg_set(P3d4, 0x81, pVBInfo->CR40[10][XGINew_RAMType]); /* CR81 */
temp2 = 0x80;
- temp = pVBInfo->CR89[XGINew_RAMType][0]; /* CR89 terminator type select */
+ /* CR89 terminator type select */
+ temp = pVBInfo->CR89[XGINew_RAMType][0];
for (j = 0; j < 4; j++) {
temp1 = (temp >> (2 * j)) & 0x03;
temp2 |= temp1;
@@ -468,19 +532,20 @@
if (HwDeviceExtension->jChipType == XG27)
xgifb_reg_set(P3d4, 0x8F, *pVBInfo->pCR8F); /* CR8F */
- for (j = 0; j <= 6; j++)
+ for (j = 0; j <= 6; j++) /* CR90 - CR96 */
xgifb_reg_set(P3d4, (0x90 + j),
- pVBInfo->CR40[14 + j][XGINew_RAMType]); /* CR90 - CR96 */
+ pVBInfo->CR40[14 + j][XGINew_RAMType]);
- for (j = 0; j <= 2; j++)
+ for (j = 0; j <= 2; j++) /* CRC3 - CRC5 */
xgifb_reg_set(P3d4, (0xC3 + j),
- pVBInfo->CR40[21 + j][XGINew_RAMType]); /* CRC3 - CRC5 */
+ pVBInfo->CR40[21 + j][XGINew_RAMType]);
- for (j = 0; j < 2; j++)
+ for (j = 0; j < 2; j++) /* CR8A - CR8B */
xgifb_reg_set(P3d4, (0x8A + j),
- pVBInfo->CR40[1 + j][XGINew_RAMType]); /* CR8A - CR8B */
+ pVBInfo->CR40[1 + j][XGINew_RAMType]);
- if ((HwDeviceExtension->jChipType == XG41) || (HwDeviceExtension->jChipType == XG42))
+ if ((HwDeviceExtension->jChipType == XG41) ||
+ (HwDeviceExtension->jChipType == XG42))
xgifb_reg_set(P3d4, 0x8C, 0x87);
xgifb_reg_set(P3d4, 0x59, pVBInfo->CR40[4][XGINew_RAMType]); /* CR59 */
@@ -550,7 +615,10 @@
memsize = data >> 4;
/* [2004/03/25] Vicent, Fix DRAM Sizing Error */
- xgifb_reg_set(pVBInfo->P3c4, 0x14, (xgifb_reg_get(pVBInfo->P3c4, 0x14) & 0x0F) | (data & 0xF0));
+ xgifb_reg_set(pVBInfo->P3c4,
+ 0x14,
+ (xgifb_reg_get(pVBInfo->P3c4, 0x14) & 0x0F) |
+ (data & 0xF0));
/* data |= XGINew_ChannelAB << 2; */
/* data |= (XGINew_DataBusWidth / 64) << 1; */
@@ -591,7 +659,10 @@
memsize = data >> 4;
/* [2004/03/25] Vicent, Fix DRAM Sizing Error */
- xgifb_reg_set(pVBInfo->P3c4, 0x14, (xgifb_reg_get(pVBInfo->P3c4, 0x14) & 0x0F) | (data & 0xF0));
+ xgifb_reg_set(pVBInfo->P3c4,
+ 0x14,
+ (xgifb_reg_get(pVBInfo->P3c4, 0x14) & 0x0F) |
+ (data & 0xF0));
udelay(15);
/* data |= XGINew_ChannelAB << 2; */
@@ -617,7 +688,8 @@
*((unsigned long *) (pVBInfo->FBAddr + Position)) = Position;
}
- udelay(500); /* [Vicent] 2004/04/16. Fix #1759 Memory Size error in Multi-Adapter. */
+ udelay(500); /* [Vicent] 2004/04/16.
+ Fix #1759 Memory Size error in Multi-Adapter. */
Position = 0;
@@ -626,7 +698,8 @@
for (i = StartAddr; i <= StopAddr; i++) {
Position = 1 << i;
- if ((*(unsigned long *) (pVBInfo->FBAddr + Position)) != Position)
+ if ((*(unsigned long *) (pVBInfo->FBAddr + Position)) !=
+ Position)
return 0;
}
return 1;
@@ -665,67 +738,96 @@
> 0x1000000) {
XGINew_DataBusWidth = 32; /* 32 bits */
- xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1); /* 22bit + 2 rank + 32bit */
+ /* 22bit + 2 rank + 32bit */
+ xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x52);
udelay(15);
if (XGINew_ReadWriteRest(24, 23, pVBInfo) == 1)
return;
- if ((HwDeviceExtension->ulVideoMemorySize - 1) > 0x800000) {
- xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x31); /* 22bit + 1 rank + 32bit */
- xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x42);
+ if ((HwDeviceExtension->ulVideoMemorySize - 1) >
+ 0x800000) {
+ /* 22bit + 1 rank + 32bit */
+ xgifb_reg_set(pVBInfo->P3c4,
+ 0x13,
+ 0x31);
+ xgifb_reg_set(pVBInfo->P3c4,
+ 0x14,
+ 0x42);
udelay(15);
- if (XGINew_ReadWriteRest(23, 23, pVBInfo) == 1)
+ if (XGINew_ReadWriteRest(23,
+ 23,
+ pVBInfo) == 1)
return;
}
}
- if ((HwDeviceExtension->ulVideoMemorySize - 1) > 0x800000) {
+ if ((HwDeviceExtension->ulVideoMemorySize - 1) >
+ 0x800000) {
XGINew_DataBusWidth = 16; /* 16 bits */
- xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1); /* 22bit + 2 rank + 16bit */
+ /* 22bit + 2 rank + 16bit */
+ xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
udelay(15);
if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
return;
else
- xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x31);
+ xgifb_reg_set(pVBInfo->P3c4,
+ 0x13,
+ 0x31);
udelay(15);
}
} else { /* Dual_16_8 */
- if ((HwDeviceExtension->ulVideoMemorySize - 1) > 0x800000) {
-
+ if ((HwDeviceExtension->ulVideoMemorySize - 1) >
+ 0x800000) {
XGINew_DataBusWidth = 16; /* 16 bits */
- xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1); /* (0x31:12x8x2) 22bit + 2 rank */
- xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41); /* 0x41:16Mx16 bit*/
+ /* (0x31:12x8x2) 22bit + 2 rank */
+ xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
+ /* 0x41:16Mx16 bit*/
+ xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x41);
udelay(15);
if (XGINew_ReadWriteRest(23, 22, pVBInfo) == 1)
return;
- if ((HwDeviceExtension->ulVideoMemorySize - 1) > 0x400000) {
- xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x31); /* (0x31:12x8x2) 22bit + 1 rank */
- xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x31); /* 0x31:8Mx16 bit*/
+ if ((HwDeviceExtension->ulVideoMemorySize - 1) >
+ 0x400000) {
+ /* (0x31:12x8x2) 22bit + 1 rank */
+ xgifb_reg_set(pVBInfo->P3c4,
+ 0x13,
+ 0x31);
+ /* 0x31:8Mx16 bit*/
+ xgifb_reg_set(pVBInfo->P3c4,
+ 0x14,
+ 0x31);
udelay(15);
- if (XGINew_ReadWriteRest(22, 22, pVBInfo) == 1)
+ if (XGINew_ReadWriteRest(22,
+ 22,
+ pVBInfo) == 1)
return;
}
}
- if ((HwDeviceExtension->ulVideoMemorySize - 1) > 0x400000) {
+ if ((HwDeviceExtension->ulVideoMemorySize - 1) >
+ 0x400000) {
XGINew_DataBusWidth = 8; /* 8 bits */
- xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1); /* (0x31:12x8x2) 22bit + 2 rank */
- xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30); /* 0x30:8Mx8 bit*/
+ /* (0x31:12x8x2) 22bit + 2 rank */
+ xgifb_reg_set(pVBInfo->P3c4, 0x13, 0xB1);
+ /* 0x30:8Mx8 bit*/
+ xgifb_reg_set(pVBInfo->P3c4, 0x14, 0x30);
udelay(15);
if (XGINew_ReadWriteRest(22, 21, pVBInfo) == 1)
return;
- else
- xgifb_reg_set(pVBInfo->P3c4, 0x13, 0x31); /* (0x31:12x8x2) 22bit + 1 rank */
+ else /* (0x31:12x8x2) 22bit + 1 rank */
+ xgifb_reg_set(pVBInfo->P3c4,
+ 0x13,
+ 0x31);
udelay(15);
}
}
@@ -911,13 +1013,18 @@
if (HwDeviceExtension->jChipType >= XG20) {
for (i = 0; i < 12; i++) {
- XGINew_SetDRAMSizingType(i, XGINew_DDRDRAM_TYPE20, pVBInfo);
- memsize = XGINew_SetDRAMSize20Reg(i, XGINew_DDRDRAM_TYPE20, pVBInfo);
+ XGINew_SetDRAMSizingType(i,
+ XGINew_DDRDRAM_TYPE20,
+ pVBInfo);
+ memsize = XGINew_SetDRAMSize20Reg(i,
+ XGINew_DDRDRAM_TYPE20,
+ pVBInfo);
if (memsize == 0)
continue;
addr = memsize + (XGINew_ChannelAB - 2) + 20;
- if ((HwDeviceExtension->ulVideoMemorySize - 1) < (unsigned long) (1 << addr))
+ if ((HwDeviceExtension->ulVideoMemorySize - 1) <
+ (unsigned long) (1 << addr))
continue;
if (XGINew_ReadWriteRest(addr, 5, pVBInfo) == 1)
@@ -925,14 +1032,19 @@
}
} else {
for (i = 0; i < 4; i++) {
- XGINew_SetDRAMSizingType(i, XGINew_DDRDRAM_TYPE340, pVBInfo);
- memsize = XGINew_SetDRAMSizeReg(i, XGINew_DDRDRAM_TYPE340, pVBInfo);
+ XGINew_SetDRAMSizingType(i,
+ XGINew_DDRDRAM_TYPE340,
+ pVBInfo);
+ memsize = XGINew_SetDRAMSizeReg(i,
+ XGINew_DDRDRAM_TYPE340,
+ pVBInfo);
if (memsize == 0)
continue;
addr = memsize + (XGINew_ChannelAB - 2) + 20;
- if ((HwDeviceExtension->ulVideoMemorySize - 1) < (unsigned long) (1 << addr))
+ if ((HwDeviceExtension->ulVideoMemorySize - 1) <
+ (unsigned long) (1 << addr))
continue;
if (XGINew_ReadWriteRest(addr, 9, pVBInfo) == 1)
@@ -953,7 +1065,8 @@
XGISetModeNew(HwDeviceExtension, 0x2e);
data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
- xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short) (data & 0xDF)); /* disable read cache */
+ /* disable read cache */
+ xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short) (data & 0xDF));
XGI_DisplayOff(HwDeviceExtension, pVBInfo);
/* data = xgifb_reg_get(pVBInfo->P3c4, 0x1); */
@@ -961,12 +1074,15 @@
/* xgifb_reg_set(pVBInfo->P3c4, 0x01, data); *//* Turn OFF Display */
XGINew_DDRSizing340(HwDeviceExtension, pVBInfo);
data = xgifb_reg_get(pVBInfo->P3c4, 0x21);
- xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short) (data | 0x20)); /* enable read cache */
+ /* enable read cache */
+ xgifb_reg_set(pVBInfo->P3c4, 0x21, (unsigned short) (data | 0x20));
}
-static void ReadVBIOSTablData(unsigned char ChipType, struct vb_device_info *pVBInfo)
+static void ReadVBIOSTablData(unsigned char ChipType,
+ struct vb_device_info *pVBInfo)
{
- volatile unsigned char *pVideoMemory = (unsigned char *) pVBInfo->ROMAddr;
+ volatile unsigned char *pVideoMemory =
+ (unsigned char *) pVBInfo->ROMAddr;
unsigned long i;
unsigned char j, k;
/* Volari customize data area end */
@@ -980,24 +1096,34 @@
if (j != 0xff) {
k = 0;
do {
- pVBInfo->XG21_LVDSCapList[k].LVDS_Capability
- = pVideoMemory[i] | (pVideoMemory[i + 1] << 8);
+ pVBInfo->XG21_LVDSCapList[k].
+ LVDS_Capability
+ = pVideoMemory[i] |
+ (pVideoMemory[i + 1] << 8);
pVBInfo->XG21_LVDSCapList[k].LVDSHT
- = pVideoMemory[i + 2] | (pVideoMemory[i + 3] << 8);
+ = pVideoMemory[i + 2] |
+ (pVideoMemory[i + 3] << 8);
pVBInfo->XG21_LVDSCapList[k].LVDSVT
- = pVideoMemory[i + 4] | (pVideoMemory[i + 5] << 8);
+ = pVideoMemory[i + 4] |
+ (pVideoMemory[i + 5] << 8);
pVBInfo->XG21_LVDSCapList[k].LVDSHDE
- = pVideoMemory[i + 6] | (pVideoMemory[i + 7] << 8);
+ = pVideoMemory[i + 6] |
+ (pVideoMemory[i + 7] << 8);
pVBInfo->XG21_LVDSCapList[k].LVDSVDE
- = pVideoMemory[i + 8] | (pVideoMemory[i + 9] << 8);
+ = pVideoMemory[i + 8] |
+ (pVideoMemory[i + 9] << 8);
pVBInfo->XG21_LVDSCapList[k].LVDSHFP
- = pVideoMemory[i + 10] | (pVideoMemory[i + 11] << 8);
+ = pVideoMemory[i + 10] |
+ (pVideoMemory[i + 11] << 8);
pVBInfo->XG21_LVDSCapList[k].LVDSVFP
- = pVideoMemory[i + 12] | (pVideoMemory[i + 13] << 8);
+ = pVideoMemory[i + 12] |
+ (pVideoMemory[i + 13] << 8);
pVBInfo->XG21_LVDSCapList[k].LVDSHSYNC
- = pVideoMemory[i + 14] | (pVideoMemory[i + 15] << 8);
+ = pVideoMemory[i + 14] |
+ (pVideoMemory[i + 15] << 8);
pVBInfo->XG21_LVDSCapList[k].LVDSVSYNC
- = pVideoMemory[i + 16] | (pVideoMemory[i + 17] << 8);
+ = pVideoMemory[i + 16] |
+ (pVideoMemory[i + 17] << 8);
pVBInfo->XG21_LVDSCapList[k].VCLKData1
= pVideoMemory[i + 18];
pVBInfo->XG21_LVDSCapList[k].VCLKData2
@@ -1015,26 +1141,38 @@
i += 25;
j--;
k++;
- } while ((j > 0) && (k < (sizeof(XGI21_LCDCapList) / sizeof(struct XGI21_LVDSCapStruct))));
+ } while ((j > 0) &&
+ (k < (sizeof(XGI21_LCDCapList) /
+ sizeof(struct
+ XGI21_LVDSCapStruct))));
} else {
pVBInfo->XG21_LVDSCapList[0].LVDS_Capability
- = pVideoMemory[i] | (pVideoMemory[i + 1] << 8);
+ = pVideoMemory[i] |
+ (pVideoMemory[i + 1] << 8);
pVBInfo->XG21_LVDSCapList[0].LVDSHT
- = pVideoMemory[i + 2] | (pVideoMemory[i + 3] << 8);
+ = pVideoMemory[i + 2] |
+ (pVideoMemory[i + 3] << 8);
pVBInfo->XG21_LVDSCapList[0].LVDSVT
- = pVideoMemory[i + 4] | (pVideoMemory[i + 5] << 8);
+ = pVideoMemory[i + 4] |
+ (pVideoMemory[i + 5] << 8);
pVBInfo->XG21_LVDSCapList[0].LVDSHDE
- = pVideoMemory[i + 6] | (pVideoMemory[i + 7] << 8);
+ = pVideoMemory[i + 6] |
+ (pVideoMemory[i + 7] << 8);
pVBInfo->XG21_LVDSCapList[0].LVDSVDE
- = pVideoMemory[i + 8] | (pVideoMemory[i + 9] << 8);
+ = pVideoMemory[i + 8] |
+ (pVideoMemory[i + 9] << 8);
pVBInfo->XG21_LVDSCapList[0].LVDSHFP
- = pVideoMemory[i + 10] | (pVideoMemory[i + 11] << 8);
+ = pVideoMemory[i + 10] |
+ (pVideoMemory[i + 11] << 8);
pVBInfo->XG21_LVDSCapList[0].LVDSVFP
- = pVideoMemory[i + 12] | (pVideoMemory[i + 13] << 8);
+ = pVideoMemory[i + 12] |
+ (pVideoMemory[i + 13] << 8);
pVBInfo->XG21_LVDSCapList[0].LVDSHSYNC
- = pVideoMemory[i + 14] | (pVideoMemory[i + 15] << 8);
+ = pVideoMemory[i + 14] |
+ (pVideoMemory[i + 15] << 8);
pVBInfo->XG21_LVDSCapList[0].LVDSVSYNC
- = pVideoMemory[i + 16] | (pVideoMemory[i + 17] << 8);
+ = pVideoMemory[i + 16] |
+ (pVideoMemory[i + 17] << 8);
pVBInfo->XG21_LVDSCapList[0].VCLKData1
= pVideoMemory[i + 18];
pVBInfo->XG21_LVDSCapList[0].VCLKData2
@@ -1197,21 +1335,31 @@
if ((pVideoMemory[0x65] & 0x01)) { /* For XG21 LVDS */
pVBInfo->IF_DEF_LVDS = 1;
xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
- xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0); /* LVDS on chip */
+ /* LVDS on chip */
+ xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0);
} else {
#endif
- xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03); /* Enable GPIOA/B read */
+ /* Enable GPIOA/B read */
+ xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03);
Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0xC0;
if (Temp == 0xC0) { /* DVI & DVO GPIOA/B pull high */
XGINew_SenseLCD(HwDeviceExtension, pVBInfo);
xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
- xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x20, 0x20); /* Enable read GPIOF */
+ /* Enable read GPIOF */
+ xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x20, 0x20);
Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x04;
if (!Temp)
- xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0x80); /* TMDS on chip */
+ xgifb_reg_and_or(pVBInfo->P3d4,
+ 0x38,
+ ~0xE0,
+ 0x80); /* TMDS on chip */
else
- xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xA0); /* Only DVO on chip */
- xgifb_reg_and(pVBInfo->P3d4, 0x4A, ~0x20); /* Disable read GPIOF */
+ xgifb_reg_and_or(pVBInfo->P3d4,
+ 0x38,
+ ~0xE0,
+ 0xA0); /* Only DVO on chip */
+ /* Disable read GPIOF */
+ xgifb_reg_and(pVBInfo->P3d4, 0x4A, ~0x20);
}
#if 1
}
@@ -1225,16 +1373,19 @@
pVBInfo->IF_DEF_LVDS = 0;
bCR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
- xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x07, 0x07); /* Enable GPIOA/B/C read */
+ /* Enable GPIOA/B/C read */
+ xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x07, 0x07);
Temp = xgifb_reg_get(pVBInfo->P3d4, 0x48) & 0x07;
xgifb_reg_set(pVBInfo->P3d4, 0x4A, bCR4A);
if (Temp <= 0x02) {
pVBInfo->IF_DEF_LVDS = 1;
- xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0); /* LVDS setting */
+ /* LVDS setting */
+ xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xC0);
xgifb_reg_set(pVBInfo->P3d4, 0x30, 0x21);
} else {
- xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xA0); /* TMDS/DVO setting */
+ /* TMDS/DVO setting */
+ xgifb_reg_and_or(pVBInfo->P3d4, 0x38, ~0xE0, 0xA0);
}
xgifb_reg_or(pVBInfo->P3d4, 0x32, LCDSense);
@@ -1245,7 +1396,8 @@
unsigned char CR38, CR4A, temp;
CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
- xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x10, 0x10); /* enable GPIOE read */
+ /* enable GPIOE read */
+ xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x10, 0x10);
CR38 = xgifb_reg_get(pVBInfo->P3d4, 0x38);
temp = 0;
if ((CR38 & 0xE0) > 0x80) {
@@ -1264,7 +1416,8 @@
unsigned char CR4A, temp;
CR4A = xgifb_reg_get(pVBInfo->P3d4, 0x4A);
- xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03); /* enable GPIOA/B/C read */
+ /* enable GPIOA/B/C read */
+ xgifb_reg_and_or(pVBInfo->P3d4, 0x4A, ~0x03, 0x03);
temp = xgifb_reg_get(pVBInfo->P3d4, 0x48);
if (temp <= 2)
temp &= 0x03;
@@ -1344,7 +1497,8 @@
printk("5");
if (HwDeviceExtension->jChipType < XG20) /* kuku 2004/06/25 */
- XGI_GetVBType(pVBInfo); /* Run XGI_GetVBType before InitTo330Pointer */
+ /* Run XGI_GetVBType before InitTo330Pointer */
+ XGI_GetVBType(pVBInfo);
InitTo330Pointer(HwDeviceExtension->jChipType, pVBInfo);
@@ -1381,7 +1535,8 @@
xgifb_reg_set(pVBInfo->P3c4, i, 0);
printk("9");
- if (HwDeviceExtension->jChipType == XG42) /* [Hsuan] 2004/08/20 Auto over driver for XG42 */
+ /* [Hsuan] 2004/08/20 Auto over driver for XG42 */
+ if (HwDeviceExtension->jChipType == XG42)
xgifb_reg_set(pVBInfo->P3c4, 0x3B, 0xC0);
/* for (i = 0x30; i <= 0x3F; i++) */
@@ -1397,7 +1552,8 @@
/* 3.SetMemoryClock
- XGINew_RAMType = (int)XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
+ XGINew_RAMType = (int)XGINew_GetXG20DRAMType(HwDeviceExtension,
+ pVBInfo);
*/
printk("11");
@@ -1411,8 +1567,10 @@
xgifb_reg_set(pVBInfo->P3c4, 0x11, 0x0F);
xgifb_reg_set(pVBInfo->P3c4, 0x1F, *pVBInfo->pSR1F);
/* xgifb_reg_set(pVBInfo->P3c4, 0x20, 0x20); */
- xgifb_reg_set(pVBInfo->P3c4, 0x20, 0xA0); /* alan, 2001/6/26 Frame buffer can read/write SR20 */
- xgifb_reg_set(pVBInfo->P3c4, 0x36, 0x70); /* Hsuan, 2006/01/01 H/W request for slow corner chip */
+ /* alan, 2001/6/26 Frame buffer can read/write SR20 */
+ xgifb_reg_set(pVBInfo->P3c4, 0x20, 0xA0);
+ /* Hsuan, 2006/01/01 H/W request for slow corner chip */
+ xgifb_reg_set(pVBInfo->P3c4, 0x36, 0x70);
if (HwDeviceExtension->jChipType == XG27) /* Alan 12/07/2006 */
xgifb_reg_set(pVBInfo->P3c4, 0x36, *pVBInfo->pSR36);
@@ -1441,14 +1599,24 @@
ChipsetID &= 0x0000FFFF;
- if ((ChipsetID == 0x700E) || (ChipsetID == 0x1022) || (ChipsetID == 0x1106) || (ChipsetID == 0x10DE)) {
+ if ((ChipsetID == 0x700E) ||
+ (ChipsetID == 0x1022) ||
+ (ChipsetID == 0x1106) ||
+ (ChipsetID == 0x10DE)) {
if (ChipsetID == 0x1106) {
- if ((VendorID == 0x1019) && (GraphicVendorID == 0x1019))
- xgifb_reg_set(pVBInfo->P3d4, 0x5F, 0x0D);
+ if ((VendorID == 0x1019) &&
+ (GraphicVendorID == 0x1019))
+ xgifb_reg_set(pVBInfo->P3d4,
+ 0x5F,
+ 0x0D);
else
- xgifb_reg_set(pVBInfo->P3d4, 0x5F, 0x0B);
+ xgifb_reg_set(pVBInfo->P3d4,
+ 0x5F,
+ 0x0B);
} else {
- xgifb_reg_set(pVBInfo->P3d4, 0x5F, 0x0B);
+ xgifb_reg_set(pVBInfo->P3d4,
+ 0x5F,
+ 0x0B);
}
}
}
@@ -1458,13 +1626,19 @@
/* Set AGP customize registers (in SetDefAGPRegs) Start */
for (i = 0x47; i <= 0x4C; i++)
- xgifb_reg_set(pVBInfo->P3d4, i, pVBInfo->AGPReg[i - 0x47]);
+ xgifb_reg_set(pVBInfo->P3d4,
+ i,
+ pVBInfo->AGPReg[i - 0x47]);
for (i = 0x70; i <= 0x71; i++)
- xgifb_reg_set(pVBInfo->P3d4, i, pVBInfo->AGPReg[6 + i - 0x70]);
+ xgifb_reg_set(pVBInfo->P3d4,
+ i,
+ pVBInfo->AGPReg[6 + i - 0x70]);
for (i = 0x74; i <= 0x77; i++)
- xgifb_reg_set(pVBInfo->P3d4, i, pVBInfo->AGPReg[8 + i - 0x74]);
+ xgifb_reg_set(pVBInfo->P3d4,
+ i,
+ pVBInfo->AGPReg[8 + i - 0x74]);
/* Set AGP customize registers (in SetDefAGPRegs) End */
/* [Hsuan]2004/12/14 AGP Input Delay Adjustment on 850 */
/* outl(0x80000000, 0xcf8); */
@@ -1472,7 +1646,10 @@
/* if (ChipsetID == 0x25308086) */
/* xgifb_reg_set(pVBInfo->P3d4, 0x77, 0xF0); */
- HwDeviceExtension->pQueryVGAConfigSpace(HwDeviceExtension, 0x50, 0, &Temp); /* Get */
+ HwDeviceExtension->pQueryVGAConfigSpace(HwDeviceExtension,
+ 0x50,
+ 0,
+ &Temp); /* Get */
Temp >>= 20;
Temp &= 0xF;
@@ -1490,12 +1667,16 @@
if (HwDeviceExtension->jChipType < XG20) { /* kuku 2004/06/25 */
/* Set VB */
XGI_UnLockCRT2(HwDeviceExtension, pVBInfo);
- xgifb_reg_and_or(pVBInfo->Part0Port, 0x3F, 0xEF, 0x00); /* alan, disable VideoCapture */
+ /* alan, disable VideoCapture */
+ xgifb_reg_and_or(pVBInfo->Part0Port, 0x3F, 0xEF, 0x00);
xgifb_reg_set(pVBInfo->Part1Port, 0x00, 0x00);
- temp1 = (unsigned char) xgifb_reg_get(pVBInfo->P3d4, 0x7B); /* chk if BCLK>=100MHz */
+ /* chk if BCLK>=100MHz */
+ temp1 = (unsigned char) xgifb_reg_get(pVBInfo->P3d4, 0x7B);
temp = (unsigned char) ((temp1 >> 4) & 0x0F);
- xgifb_reg_set(pVBInfo->Part1Port, 0x02, (*pVBInfo->pCRT2Data_1_2));
+ xgifb_reg_set(pVBInfo->Part1Port,
+ 0x02,
+ (*pVBInfo->pCRT2Data_1_2));
printk("16");
@@ -1504,10 +1685,15 @@
xgifb_reg_set(pVBInfo->P3c4, 0x27, 0x1F);
- if ((HwDeviceExtension->jChipType == XG42)
- && XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo) != 0) { /* Not DDR */
- xgifb_reg_set(pVBInfo->P3c4, 0x31, (*pVBInfo->pSR31 & 0x3F) | 0x40);
- xgifb_reg_set(pVBInfo->P3c4, 0x32, (*pVBInfo->pSR32 & 0xFC) | 0x01);
+ if ((HwDeviceExtension->jChipType == XG42) &&
+ XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo) != 0) {
+ /* Not DDR */
+ xgifb_reg_set(pVBInfo->P3c4,
+ 0x31,
+ (*pVBInfo->pSR31 & 0x3F) | 0x40);
+ xgifb_reg_set(pVBInfo->P3c4,
+ 0x32,
+ (*pVBInfo->pSR32 & 0xFC) | 0x01);
} else {
xgifb_reg_set(pVBInfo->P3c4, 0x31, *pVBInfo->pSR31);
xgifb_reg_set(pVBInfo->P3c4, 0x32, *pVBInfo->pSR32);
@@ -1522,9 +1708,15 @@
if (XGI_BridgeIsOn(pVBInfo) == 1) {
if (pVBInfo->IF_DEF_LVDS == 0) {
xgifb_reg_set(pVBInfo->Part2Port, 0x00, 0x1C);
- xgifb_reg_set(pVBInfo->Part4Port, 0x0D, *pVBInfo->pCRT2Data_4_D);
- xgifb_reg_set(pVBInfo->Part4Port, 0x0E, *pVBInfo->pCRT2Data_4_E);
- xgifb_reg_set(pVBInfo->Part4Port, 0x10, *pVBInfo->pCRT2Data_4_10);
+ xgifb_reg_set(pVBInfo->Part4Port,
+ 0x0D,
+ *pVBInfo->pCRT2Data_4_D);
+ xgifb_reg_set(pVBInfo->Part4Port,
+ 0x0E,
+ *pVBInfo->pCRT2Data_4_E);
+ xgifb_reg_set(pVBInfo->Part4Port,
+ 0x10,
+ *pVBInfo->pCRT2Data_4_10);
xgifb_reg_set(pVBInfo->Part4Port, 0x0F, 0x3F);
}
@@ -1542,31 +1734,42 @@
printk("183");
/* XGINew_DetectMonitor(HwDeviceExtension); */
pVBInfo->IF_DEF_CH7007 = 0;
- if ((HwDeviceExtension->jChipType == XG21) && (pVBInfo->IF_DEF_CH7007)) {
+ if ((HwDeviceExtension->jChipType == XG21) &&
+ (pVBInfo->IF_DEF_CH7007)) {
printk("184");
- XGI_GetSenseStatus(HwDeviceExtension, pVBInfo); /* sense CRT2 */
+ /* sense CRT2 */
+ XGI_GetSenseStatus(HwDeviceExtension, pVBInfo);
printk("185");
}
if (HwDeviceExtension->jChipType == XG21) {
printk("186");
- xgifb_reg_and_or(pVBInfo->P3d4, 0x32, ~Monitor1Sense, Monitor1Sense); /* Z9 default has CRT */
+ xgifb_reg_and_or(pVBInfo->P3d4,
+ 0x32,
+ ~Monitor1Sense,
+ Monitor1Sense); /* Z9 default has CRT */
temp = GetXG21FPBits(pVBInfo);
xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x01, temp);
printk("187");
}
if (HwDeviceExtension->jChipType == XG27) {
- xgifb_reg_and_or(pVBInfo->P3d4, 0x32, ~Monitor1Sense, Monitor1Sense); /* Z9 default has CRT */
+ xgifb_reg_and_or(pVBInfo->P3d4,
+ 0x32,
+ ~Monitor1Sense,
+ Monitor1Sense); /* Z9 default has CRT */
temp = GetXG27FPBits(pVBInfo);
xgifb_reg_and_or(pVBInfo->P3d4, 0x37, ~0x03, temp);
}
printk("19");
- XGINew_RAMType = (int) XGINew_GetXG20DRAMType(HwDeviceExtension, pVBInfo);
+ XGINew_RAMType = (int) XGINew_GetXG20DRAMType(HwDeviceExtension,
+ pVBInfo);
- XGINew_SetDRAMDefaultRegister340(HwDeviceExtension, pVBInfo->P3d4, pVBInfo);
+ XGINew_SetDRAMDefaultRegister340(HwDeviceExtension,
+ pVBInfo->P3d4,
+ pVBInfo);
printk("20");
XGINew_SetDRAMSize_340(HwDeviceExtension, pVBInfo);
@@ -1594,7 +1797,9 @@
/* OutPortLong(0xcf8, base); */
/* Temp = (InPortLong(0xcfc) & 0xFFFF); */
/* if (Temp == 0x1039) { */
- xgifb_reg_set(pVBInfo->P3c4, 0x22, (unsigned char) ((*pVBInfo->pSR22) & 0xFE));
+ xgifb_reg_set(pVBInfo->P3c4,
+ 0x22,
+ (unsigned char) ((*pVBInfo->pSR22) & 0xFE));
/* } else { */
/* xgifb_reg_set(pVBInfo->P3c4, 0x22, *pVBInfo->pSR22); */
/* } */
diff --git a/drivers/staging/xgifb/vb_init.h b/drivers/staging/xgifb/vb_init.h
index b47352b..6b77230 100644
--- a/drivers/staging/xgifb/vb_init.h
+++ b/drivers/staging/xgifb/vb_init.h
@@ -1,7 +1,6 @@
-#ifndef _VBINIT_
-#define _VBINIT_
-extern unsigned char XGIInitNew(struct xgi_hw_device_info *HwDeviceExtension) ;
+#ifndef _VBINIT_
+#define _VBINIT_
+extern unsigned char XGIInitNew(struct xgi_hw_device_info *HwDeviceExtension);
extern struct XGI21_LVDSCapStruct XGI21_LCDCapList[13];
-
#endif
diff --git a/drivers/staging/xgifb/vb_setmode.c b/drivers/staging/xgifb/vb_setmode.c
index 9669c22..2669b1b 100644
--- a/drivers/staging/xgifb/vb_setmode.c
+++ b/drivers/staging/xgifb/vb_setmode.c
@@ -1,5 +1,5 @@
-#include <asm/io.h>
+#include <linux/io.h>
#include <linux/delay.h>
#include <linux/types.h>
#include <linux/version.h>
@@ -71,7 +71,8 @@
= (struct XGI_CRT1TableStruct *) XGI_CRT1Table;
/* add for new UNIVGABIOS */
- /* XGINew_UBLCDDataTable = (struct XGI_LCDDataTablStruct *) XGI_LCDDataTable; */
+ /* XGINew_UBLCDDataTable =
+ * (struct XGI_LCDDataTablStruct *) XGI_LCDDataTable; */
/* XGINew_UBTVDataTable = (XGI_TVDataTablStruct *) XGI_TVDataTable; */
pVBInfo->MCLKData = (struct XGI_MCLKDataStruct *) XGI340New_MCLKData;
@@ -190,8 +191,9 @@
}
-static unsigned char XGI_GetModePtr(unsigned short ModeNo, unsigned short ModeIdIndex,
- struct vb_device_info *pVBInfo)
+static unsigned char XGI_GetModePtr(unsigned short ModeNo,
+ unsigned short ModeIdIndex,
+ struct vb_device_info *pVBInfo)
{
unsigned char index;
@@ -207,21 +209,24 @@
}
/*
-unsigned char XGI_SetBIOSData(unsigned short ModeNo, unsigned short ModeIdIndex) {
+unsigned char XGI_SetBIOSData(unsigned short ModeNo,
+ unsigned short ModeIdIndex) {
return (0);
}
*/
-/* unsigned char XGI_ClearBankRegs(unsigned short ModeNo, unsigned short ModeIdIndex) {
+/* unsigned char XGI_ClearBankRegs(unsigned short ModeNo,
+ unsigned short ModeIdIndex) {
return( 0 ) ;
}
*/
-static void XGI_SetSeqRegs(unsigned short ModeNo, unsigned short StandTableIndex,
- unsigned short ModeIdIndex, struct vb_device_info *pVBInfo)
+static void XGI_SetSeqRegs(unsigned short ModeNo,
+ unsigned short StandTableIndex,
+ unsigned short ModeIdIndex,
+ struct vb_device_info *pVBInfo)
{
unsigned char tempah, SRdata;
-
unsigned short i, modeflag;
if (ModeNo <= 0x13)
@@ -246,19 +251,25 @@
xgifb_reg_set(pVBInfo->P3c4, 0x01, tempah); /* Set SR1 */
for (i = 02; i <= 04; i++) {
- SRdata = pVBInfo->StandTable[StandTableIndex].SR[i - 1]; /* Get SR2,3,4 from file */
+ /* Get SR2,3,4 from file */
+ SRdata = pVBInfo->StandTable[StandTableIndex].SR[i - 1];
xgifb_reg_set(pVBInfo->P3c4, i, SRdata); /* Set SR2 3 4 */
}
}
static void XGI_SetMiscRegs(unsigned short StandTableIndex,
- struct vb_device_info *pVBInfo)
+ struct vb_device_info *pVBInfo)
{
unsigned char Miscdata;
- Miscdata = pVBInfo->StandTable[StandTableIndex].MISC; /* Get Misc from file */
+ /* Get Misc from file */
+ Miscdata = pVBInfo->StandTable[StandTableIndex].MISC;
/*
- if (pVBInfo->VBType & (VB_XGI301B | VB_XGI302B | VB_XGI301LV | VB_XGI302LV | VB_XGI301C)) {
+ if (pVBInfo->VBType & (VB_XGI301B |
+ VB_XGI302B |
+ VB_XGI301LV |
+ VB_XGI302LV |
+ VB_XGI301C)) {
if (pVBInfo->VBInfo & SetCRT2ToLCDA) {
Miscdata |= 0x0C;
}
@@ -269,7 +280,8 @@
}
static void XGI_SetCRTCRegs(struct xgi_hw_device_info *HwDeviceExtension,
- unsigned short StandTableIndex, struct vb_device_info *pVBInfo)
+ unsigned short StandTableIndex,
+ struct vb_device_info *pVBInfo)
{
unsigned char CRTCdata;
unsigned short i;
@@ -279,11 +291,13 @@
xgifb_reg_set(pVBInfo->P3d4, 0x11, CRTCdata); /* Unlock CRTC */
for (i = 0; i <= 0x18; i++) {
- CRTCdata = pVBInfo->StandTable[StandTableIndex].CRTC[i]; /* Get CRTC from file */
+ /* Get CRTC from file */
+ CRTCdata = pVBInfo->StandTable[StandTableIndex].CRTC[i];
xgifb_reg_set(pVBInfo->P3d4, i, CRTCdata); /* Set CRTC(3d4) */
}
/*
- if ((HwDeviceExtension->jChipType == XGI_630) && (HwDeviceExtension->jChipRevision == 0x30)) {
+ if ((HwDeviceExtension->jChipType == XGI_630) &&
+ (HwDeviceExtension->jChipRevision == 0x30)) {
if (pVBInfo->VBInfo & SetInSlaveMode) {
if (pVBInfo->VBInfo & (SetCRT2ToLCD | SetCRT2ToTV)) {
xgifb_reg_set(pVBInfo->P3d4, 0x18, 0xFE);
@@ -293,8 +307,10 @@
*/
}
-static void XGI_SetATTRegs(unsigned short ModeNo, unsigned short StandTableIndex,
- unsigned short ModeIdIndex, struct vb_device_info *pVBInfo)
+static void XGI_SetATTRegs(unsigned short ModeNo,
+ unsigned short StandTableIndex,
+ unsigned short ModeIdIndex,
+ struct vb_device_info *pVBInfo)
{
unsigned char ARdata;
unsigned short i, modeflag;
@@ -313,8 +329,8 @@
} else {
if (pVBInfo->VBInfo & (SetCRT2ToTV
| SetCRT2ToLCD)) {
- if (pVBInfo->VBInfo
- & SetInSlaveMode)
+ if (pVBInfo->VBInfo &
+ SetInSlaveMode)
ARdata = 0;
}
}
@@ -334,13 +350,14 @@
}
static void XGI_SetGRCRegs(unsigned short StandTableIndex,
- struct vb_device_info *pVBInfo)
+ struct vb_device_info *pVBInfo)
{
unsigned char GRdata;
unsigned short i;
for (i = 0; i <= 0x08; i++) {
- GRdata = pVBInfo->StandTable[StandTableIndex].GRC[i]; /* Get GR from file */
+ /* Get GR from file */
+ GRdata = pVBInfo->StandTable[StandTableIndex].GRC[i];
xgifb_reg_set(pVBInfo->P3ce, i, GRdata); /* Set GR(3ce) */
}
@@ -382,7 +399,8 @@
unsigned short tempax, tempbx, resinfo, modeflag, infoflag;
if (ModeNo <= 0x13)
- modeflag = pVBInfo->SModeIDTable[ModeIdIndex].St_ModeFlag; /* si+St_ModeFlag */
+ /* si+St_ModeFlag */
+ modeflag = pVBInfo->SModeIDTable[ModeIdIndex].St_ModeFlag;
else
modeflag = pVBInfo->EModeIDTable[ModeIdIndex].Ext_ModeFlag;
@@ -398,12 +416,14 @@
tempax |= SupportCRT2in301C;
}
- if (pVBInfo->VBInfo & (SetCRT2ToLCD | SetCRT2ToLCDA)) { /* 301b */
+ /* 301b */
+ if (pVBInfo->VBInfo & (SetCRT2ToLCD | SetCRT2ToLCDA)) {
tempax |= SupportLCD;
if (pVBInfo->LCDResInfo != Panel1280x1024) {
if (pVBInfo->LCDResInfo != Panel1280x960) {
- if (pVBInfo->LCDInfo & LCDNonExpanding) {
+ if (pVBInfo->LCDInfo &
+ LCDNonExpanding) {
if (resinfo >= 9) {
tempax = 0;
return 0;
@@ -414,8 +434,8 @@
}
if (pVBInfo->VBInfo & SetCRT2ToHiVisionTV) { /* for HiTV */
- if ((pVBInfo->VBType & VB_XGI301LV)
- && (pVBInfo->VBExtInfo == VB_YPbPr1080i)) {
+ if ((pVBInfo->VBType & VB_XGI301LV) &&
+ (pVBInfo->VBExtInfo == VB_YPbPr1080i)) {
tempax |= SupportYPbPr;
if (pVBInfo->VBInfo & SetInSlaveMode) {
if (resinfo == 4)
@@ -444,9 +464,11 @@
}
}
} else {
- if (pVBInfo->VBInfo & (SetCRT2ToAVIDEO
- | SetCRT2ToSVIDEO | SetCRT2ToSCART
- | SetCRT2ToYPbPr | SetCRT2ToHiVisionTV)) {
+ if (pVBInfo->VBInfo & (SetCRT2ToAVIDEO |
+ SetCRT2ToSVIDEO |
+ SetCRT2ToSCART |
+ SetCRT2ToYPbPr |
+ SetCRT2ToHiVisionTV)) {
tempax |= SupportTV;
if (pVBInfo->VBType & (VB_XGI301B | VB_XGI302B
@@ -457,10 +479,10 @@
if (!(pVBInfo->VBInfo & SetPALTV)) {
if (modeflag & NoSupportSimuTV) {
- if (pVBInfo->VBInfo
- & SetInSlaveMode) {
- if (!(pVBInfo->VBInfo
- & SetNotSimuMode)) {
+ if (pVBInfo->VBInfo &
+ SetInSlaveMode) {
+ if (!(pVBInfo->VBInfo &
+ SetNotSimuMode)) {
return 0;
}
}
@@ -490,10 +512,10 @@
}
}
- for (; pVBInfo->RefIndex[RefreshRateTableIndex + (*i)].ModeID == tempbx; (*i)--) {
- infoflag
- = pVBInfo->RefIndex[RefreshRateTableIndex
- + (*i)].Ext_InfoFlag;
+ for (; pVBInfo->RefIndex[RefreshRateTableIndex + (*i)].ModeID ==
+ tempbx; (*i)--) {
+ infoflag = pVBInfo->RefIndex[RefreshRateTableIndex + (*i)].
+ Ext_InfoFlag;
if (infoflag & tempax)
return 1;
@@ -502,9 +524,8 @@
}
for ((*i) = 0;; (*i)++) {
- infoflag
- = pVBInfo->RefIndex[RefreshRateTableIndex
- + (*i)].Ext_InfoFlag;
+ infoflag = pVBInfo->RefIndex[RefreshRateTableIndex + (*i)].
+ Ext_InfoFlag;
if (pVBInfo->RefIndex[RefreshRateTableIndex + (*i)].ModeID
!= tempbx) {
return 0;
@@ -521,7 +542,8 @@
{
unsigned short sync, temp;
- sync = pVBInfo->RefIndex[RefreshRateTableIndex].Ext_InfoFlag >> 8; /* di+0x00 */
+ /* di+0x00 */
+ sync = pVBInfo->RefIndex[RefreshRateTableIndex].Ext_InfoFlag >> 8;
sync &= 0xC0;
temp = 0x2F;
temp |= sync;
@@ -538,7 +560,8 @@
/* xgifb_reg_set(pVBInfo->P3d4, 0x56, 0); */
/* xgifb_reg_and_or(pVBInfo->P3d4, 0x11, 0x7f, 0x00); */
- data = (unsigned char) xgifb_reg_get(pVBInfo->P3d4, 0x11); /* unlock cr0-7 */
+ /* unlock cr0-7 */
+ data = (unsigned char) xgifb_reg_get(pVBInfo->P3d4, 0x11);
data &= 0x7F;
xgifb_reg_set(pVBInfo->P3d4, 0x11, data);
@@ -591,8 +614,9 @@
}
}
-static void XGI_SetCRT1Timing_V(unsigned short ModeIdIndex, unsigned short ModeNo,
- struct vb_device_info *pVBInfo)
+static void XGI_SetCRT1Timing_V(unsigned short ModeIdIndex,
+ unsigned short ModeNo,
+ struct vb_device_info *pVBInfo)
{
unsigned char data;
unsigned short i, j;
@@ -650,7 +674,8 @@
unsigned char index, data;
unsigned short i;
- index = pVBInfo->RefIndex[RefreshRateTableIndex].Ext_CRT1CRTC; /* Get index */
+ /* Get index */
+ index = pVBInfo->RefIndex[RefreshRateTableIndex].Ext_CRT1CRTC;
index = index & IndexMask;
data = (unsigned char) xgifb_reg_get(pVBInfo->P3d4, 0x11);
@@ -688,9 +713,12 @@
if (ModeNo <= 0x13) {
StandTableIndex = XGI_GetModePtr(ModeNo, ModeIdIndex, pVBInfo);
- Tempax = pVBInfo->StandTable[StandTableIndex].CRTC[4]; /* CR04 HRS */
- xgifb_reg_set(pVBInfo->P3c4, 0x2E, Tempax); /* SR2E [7:0]->HRS */
- Tempbx = pVBInfo->StandTable[StandTableIndex].CRTC[5]; /* Tempbx: CR05 HRE */
+ /* CR04 HRS */
+ Tempax = pVBInfo->StandTable[StandTableIndex].CRTC[4];
+ /* SR2E [7:0]->HRS */
+ xgifb_reg_set(pVBInfo->P3c4, 0x2E, Tempax);
+ /* Tempbx: CR05 HRE */
+ Tempbx = pVBInfo->StandTable[StandTableIndex].CRTC[5];
Tempbx &= 0x1F; /* Tempbx: HRE[4:0] */
Tempcx = Tempax;
Tempcx &= 0xE0; /* Tempcx: HRS[7:5] */
@@ -698,27 +726,34 @@
if (Tempbx < (Tempax & 0x1F)) /* IF HRE < HRS */
Tempdx |= 0x20; /* Tempdx: HRE = HRE + 0x20 */
Tempdx <<= 2; /* Tempdx << 2 */
- xgifb_reg_set(pVBInfo->P3c4, 0x2F, Tempdx); /* SR2F [7:2]->HRE */
+ /* SR2F [7:2]->HRE */
+ xgifb_reg_set(pVBInfo->P3c4, 0x2F, Tempdx);
xgifb_reg_and_or(pVBInfo->P3c4, 0x30, 0xE3, 00);
- Tempax = pVBInfo->StandTable[StandTableIndex].CRTC[16]; /* Tempax: CR16 VRS */
+ /* Tempax: CR16 VRS */
+ Tempax = pVBInfo->StandTable[StandTableIndex].CRTC[16];
Tempbx = Tempax; /* Tempbx=Tempax */
Tempax &= 0x01; /* Tempax: VRS[0] */
xgifb_reg_or(pVBInfo->P3c4, 0x33, Tempax); /* SR33[0]->VRS */
- Tempax = pVBInfo->StandTable[StandTableIndex].CRTC[7]; /* Tempax: CR7 VRS */
+
+ /* Tempax: CR7 VRS */
+ Tempax = pVBInfo->StandTable[StandTableIndex].CRTC[7];
Tempdx = Tempbx >> 1; /* Tempdx: VRS[7:1] */
Tempcx = Tempax & 0x04; /* Tempcx: CR7[2] */
Tempcx <<= 5; /* Tempcx[7]: VRS[8] */
Tempdx |= Tempcx; /* Tempdx: VRS[8:1] */
- xgifb_reg_set(pVBInfo->P3c4, 0x34, Tempdx); /* SR34[7:0]: VRS[8:1] */
+ /* SR34[7:0]: VRS[8:1] */
+ xgifb_reg_set(pVBInfo->P3c4, 0x34, Tempdx);
- Temp1 = Tempcx << 1; /* Temp1[8]: VRS[8] unsigned char -> unsigned short */
+ /* Temp1[8]: VRS[8] unsigned char -> unsigned short */
+ Temp1 = Tempcx << 1;
Temp1 |= Tempbx; /* Temp1[8:0]: VRS[8:0] */
Tempax &= 0x80; /* Tempax[7]: CR7[7] */
Temp2 = Tempax << 2; /* Temp2[9]: VRS[9] */
Temp1 |= Temp2; /* Temp1[9:0]: VRS[9:0] */
- Tempax = pVBInfo->StandTable[StandTableIndex].CRTC[17]; /* CR16 VRE */
+ /* CR16 VRE */
+ Tempax = pVBInfo->StandTable[StandTableIndex].CRTC[17];
Tempax &= 0x0F; /* Tempax[3:0]: VRE[3:0] */
Temp2 = Temp1 & 0x3F0; /* Temp2[9:4]: VRS[9:4] */
Temp2 |= Tempax; /* Temp2[9:0]: VRE[9:0] */
@@ -733,12 +768,15 @@
Tempbx = (unsigned char) Temp1; /* Tempbx[1:0]: VRS[10:9] */
Tempax |= Tempbx; /* VRE[5:0]VRS[10:9] */
Tempax &= 0x7F;
- xgifb_reg_set(pVBInfo->P3c4, 0x3F, Tempax); /* SR3F D[7:2]->VRE D[1:0]->VRS */
+ /* SR3F D[7:2]->VRE D[1:0]->VRS */
+ xgifb_reg_set(pVBInfo->P3c4, 0x3F, Tempax);
} else {
index = pVBInfo->RefIndex[RefreshRateTableIndex].Ext_CRT1CRTC;
- Tempax = pVBInfo->XGINEWUB_CRT1Table[index].CR[3]; /* Tempax: CR4 HRS */
+ /* Tempax: CR4 HRS */
+ Tempax = pVBInfo->XGINEWUB_CRT1Table[index].CR[3];
Tempcx = Tempax; /* Tempcx: HRS */
- xgifb_reg_set(pVBInfo->P3c4, 0x2E, Tempax); /* SR2E[7:0]->HRS */
+ /* SR2E[7:0]->HRS */
+ xgifb_reg_set(pVBInfo->P3c4, 0x2E, Tempax);
Tempdx = pVBInfo->XGINEWUB_CRT1Table[index].CR[5]; /* SRB */
Tempdx &= 0xC0; /* Tempdx[7:6]: SRB[7:6] */
@@ -766,14 +804,17 @@
Tempax <<= 2; /* Tempax[7:2]: HRE[5:0] */
Tempdx >>= 6; /* Tempdx[7:6]->[1:0] HRS[9:8] */
Tempax |= Tempdx; /* HRE[5:0]HRS[9:8] */
- xgifb_reg_set(pVBInfo->P3c4, 0x2F, Tempax); /* SR2F D[7:2]->HRE, D[1:0]->HRS */
+ /* SR2F D[7:2]->HRE, D[1:0]->HRS */
+ xgifb_reg_set(pVBInfo->P3c4, 0x2F, Tempax);
xgifb_reg_and_or(pVBInfo->P3c4, 0x30, 0xE3, 00);
- Tempax = pVBInfo->XGINEWUB_CRT1Table[index].CR[10]; /* CR10 VRS */
+ /* CR10 VRS */
+ Tempax = pVBInfo->XGINEWUB_CRT1Table[index].CR[10];
Tempbx = Tempax; /* Tempbx: VRS */
Tempax &= 0x01; /* Tempax[0]: VRS[0] */
xgifb_reg_or(pVBInfo->P3c4, 0x33, Tempax); /* SR33[0]->VRS[0] */
- Tempax = pVBInfo->XGINEWUB_CRT1Table[index].CR[9]; /* CR7[2][7] VRE */
+ /* CR7[2][7] VRE */
+ Tempax = pVBInfo->XGINEWUB_CRT1Table[index].CR[9];
Tempcx = Tempbx >> 1; /* Tempcx[6:0]: VRS[7:1] */
Tempdx = Tempax & 0x04; /* Tempdx[2]: CR7[2] */
Tempdx <<= 5; /* Tempdx[7]: VRS[8] */
@@ -786,15 +827,18 @@
Tempax &= 0x80;
Temp2 = Tempax << 2; /* Temp2[9]: VRS[9] */
Temp1 |= Temp2; /* Temp1[9:0]: VRS[9:0] */
- Tempax = pVBInfo->XGINEWUB_CRT1Table[index].CR[14]; /* Tempax: SRA */
+ /* Tempax: SRA */
+ Tempax = pVBInfo->XGINEWUB_CRT1Table[index].CR[14];
Tempax &= 0x08; /* Tempax[3]: VRS[3] */
Temp2 = Tempax;
Temp2 <<= 7; /* Temp2[10]: VRS[10] */
Temp1 |= Temp2; /* Temp1[10:0]: VRS[10:0] */
- Tempax = pVBInfo->XGINEWUB_CRT1Table[index].CR[11]; /* Tempax: CR11 VRE */
+ /* Tempax: CR11 VRE */
+ Tempax = pVBInfo->XGINEWUB_CRT1Table[index].CR[11];
Tempax &= 0x0F; /* Tempax[3:0]: VRE[3:0] */
- Tempbx = pVBInfo->XGINEWUB_CRT1Table[index].CR[14]; /* Tempbx: SRA */
+ /* Tempbx: SRA */
+ Tempbx = pVBInfo->XGINEWUB_CRT1Table[index].CR[14];
Tempbx &= 0x20; /* Tempbx[5]: VRE[5] */
Tempbx >>= 1; /* Tempbx[4]: VRE[4] */
Tempax |= Tempbx; /* Tempax[4:0]: VRE[4:0] */
@@ -813,21 +857,26 @@
Tempbx = (unsigned char) Temp1;
Tempax |= Tempbx; /* Tempax[7:0]: VRE[5:0]VRS[10:9] */
Tempax &= 0x7F;
- xgifb_reg_set(pVBInfo->P3c4, 0x3F, Tempax); /* SR3F D[7:2]->VRE D[1:0]->VRS */
+ /* SR3F D[7:2]->VRE D[1:0]->VRS */
+ xgifb_reg_set(pVBInfo->P3c4, 0x3F, Tempax);
}
}
-static void XGI_SetXG27CRTC(unsigned short ModeNo, unsigned short ModeIdIndex,
- unsigned short RefreshRateTableIndex,
- struct vb_device_info *pVBInfo)
+static void XGI_SetXG27CRTC(unsigned short ModeNo,
+ unsigned short ModeIdIndex,
+ unsigned short RefreshRateTableIndex,
+ struct vb_device_info *pVBInfo)
{
unsigned short StandTableIndex, index, Tempax, Tempbx, Tempcx, Tempdx;
if (ModeNo <= 0x13) {
StandTableIndex = XGI_GetModePtr(ModeNo, ModeIdIndex, pVBInfo);
- Tempax = pVBInfo->StandTable[StandTableIndex].CRTC[4]; /* CR04 HRS */
- xgifb_reg_set(pVBInfo->P3c4, 0x2E, Tempax); /* SR2E [7:0]->HRS */
- Tempbx = pVBInfo->StandTable[StandTableIndex].CRTC[5]; /* Tempbx: CR05 HRE */
+ /* CR04 HRS */
+ Tempax = pVBInfo->StandTable[StandTableIndex].CRTC[4];
+ /* SR2E [7:0]->HRS */
+ xgifb_reg_set(pVBInfo->P3c4, 0x2E, Tempax);
+ /* Tempbx: CR05 HRE */
+ Tempbx = pVBInfo->StandTable[StandTableIndex].CRTC[5];
Tempbx &= 0x1F; /* Tempbx: HRE[4:0] */
Tempcx = Tempax;
Tempcx &= 0xE0; /* Tempcx: HRS[7:5] */
@@ -835,39 +884,50 @@
if (Tempbx < (Tempax & 0x1F)) /* IF HRE < HRS */
Tempdx |= 0x20; /* Tempdx: HRE = HRE + 0x20 */
Tempdx <<= 2; /* Tempdx << 2 */
- xgifb_reg_set(pVBInfo->P3c4, 0x2F, Tempdx); /* SR2F [7:2]->HRE */
+ /* SR2F [7:2]->HRE */
+ xgifb_reg_set(pVBInfo->P3c4, 0x2F, Tempdx);
xgifb_reg_and_or(pVBInfo->P3c4, 0x30, 0xE3, 00);
- Tempax = pVBInfo->StandTable[StandTableIndex].CRTC[16]; /* Tempax: CR10 VRS */
+ /* Tempax: CR10 VRS */
+ Tempax = pVBInfo->StandTable[StandTableIndex].CRTC[16];
xgifb_reg_set(pVBInfo->P3c4, 0x34, Tempax); /* SR34[7:0]->VRS */
Tempcx = Tempax; /* Tempcx=Tempax=VRS[7:0] */
- Tempax = pVBInfo->StandTable[StandTableIndex].CRTC[7]; /* Tempax[7][2]: CR7[7][2] VRS[9][8] */
+ /* Tempax[7][2]: CR7[7][2] VRS[9][8] */
+ Tempax = pVBInfo->StandTable[StandTableIndex].CRTC[7];
Tempbx = Tempax; /* Tempbx=CR07 */
Tempax &= 0x04; /* Tempax[2]: CR07[2] VRS[8] */
Tempax >>= 2;
- xgifb_reg_and_or(pVBInfo->P3c4, 0x35, ~0x01, Tempax); /* SR35 D[0]->VRS D[8] */
+ /* SR35 D[0]->VRS D[8] */
+ xgifb_reg_and_or(pVBInfo->P3c4, 0x35, ~0x01, Tempax);
Tempcx |= (Tempax << 8); /* Tempcx[8] |= VRS[8] */
Tempcx |= (Tempbx & 0x80) << 2; /* Tempcx[9] |= VRS[9] */
- Tempax = pVBInfo->StandTable[StandTableIndex].CRTC[17]; /* CR11 VRE */
+ /* CR11 VRE */
+ Tempax = pVBInfo->StandTable[StandTableIndex].CRTC[17];
Tempax &= 0x0F; /* Tempax: VRE[3:0] */
Tempbx = Tempcx; /* Tempbx=Tempcx=VRS[9:0] */
Tempbx &= 0x3F0; /* Tempbx[9:4]: VRS[9:4] */
Tempbx |= Tempax; /* Tempbx[9:0]: VRE[9:0] */
if (Tempax <= (Tempcx & 0x0F)) /* VRE[3:0]<=VRS[3:0] */
Tempbx |= 0x10; /* Tempbx: VRE + 0x10 */
- Tempax = (unsigned char) Tempbx & 0xFF; /* Tempax[7:0]: VRE[7:0] */
+ /* Tempax[7:0]: VRE[7:0] */
+ Tempax = (unsigned char) Tempbx & 0xFF;
Tempax <<= 2; /* Tempax << 2: VRE[5:0] */
Tempcx = (Tempcx & 0x600) >> 8; /* Tempcx VRS[10:9] */
- xgifb_reg_and_or(pVBInfo->P3c4, 0x3F, ~0xFC, Tempax); /* SR3F D[7:2]->VRE D[5:0] */
- xgifb_reg_and_or(pVBInfo->P3c4, 0x35, ~0x06, Tempcx); /* SR35 D[2:1]->VRS[10:9] */
+ /* SR3F D[7:2]->VRE D[5:0] */
+ xgifb_reg_and_or(pVBInfo->P3c4, 0x3F, ~0xFC, Tempax);
+ /* SR35 D[2:1]->VRS[10:9] */
+ xgifb_reg_and_or(pVBInfo->P3c4, 0x35, ~0x06, Tempcx);
} else {
index = pVBInfo->RefIndex[RefreshRateTableIndex].Ext_CRT1CRTC;
- Tempax = pVBInfo->XGINEWUB_CRT1Table[index].CR[3]; /* Tempax: CR4 HRS */
+ /* Tempax: CR4 HRS */
+ Tempax = pVBInfo->XGINEWUB_CRT1Table[index].CR[3];
Tempbx = Tempax; /* Tempbx: HRS[7:0] */
- xgifb_reg_set(pVBInfo->P3c4, 0x2E, Tempax); /* SR2E[7:0]->HRS */
+ /* SR2E[7:0]->HRS */
+ xgifb_reg_set(pVBInfo->P3c4, 0x2E, Tempax);
- Tempax = pVBInfo->XGINEWUB_CRT1Table[index].CR[5]; /* SR0B */
+ /* SR0B */
+ Tempax = pVBInfo->XGINEWUB_CRT1Table[index].CR[5];
Tempax &= 0xC0; /* Tempax[7:6]: SR0B[7:6]: HRS[9:8]*/
Tempbx |= (Tempax << 2); /* Tempbx: HRS[9:0] */
@@ -883,7 +943,8 @@
Tempbx = Tempbx & 0x3C0; /* Tempbx[9:6]: HRS[9:6] */
Tempbx |= Tempcx; /* Tempbx: HRS[9:6]HRE[5:0] */
- Tempax = pVBInfo->XGINEWUB_CRT1Table[index].CR[3]; /* Tempax: CR4 HRS */
+ /* Tempax: CR4 HRS */
+ Tempax = pVBInfo->XGINEWUB_CRT1Table[index].CR[3];
Tempax &= 0x3F; /* Tempax: HRS[5:0] */
if (Tempcx <= Tempax) /* HRE[5:0] < HRS[5:0] */
Tempbx += 0x40; /* Tempbx= Tempbx + 0x40 : HRE[9:0]*/
@@ -892,27 +953,35 @@
Tempax &= 0xC0; /* Tempax[7:6]: SR0B[7:6]: HRS[9:8]*/
Tempax >>= 6; /* Tempax[1:0]: HRS[9:8]*/
Tempax |= ((Tempbx << 2) & 0xFF); /* Tempax[7:2]: HRE[5:0] */
- xgifb_reg_set(pVBInfo->P3c4, 0x2F, Tempax); /* SR2F [7:2][1:0]: HRE[5:0]HRS[9:8] */
+ /* SR2F [7:2][1:0]: HRE[5:0]HRS[9:8] */
+ xgifb_reg_set(pVBInfo->P3c4, 0x2F, Tempax);
xgifb_reg_and_or(pVBInfo->P3c4, 0x30, 0xE3, 00);
- Tempax = pVBInfo->XGINEWUB_CRT1Table[index].CR[10]; /* CR10 VRS */
- xgifb_reg_set(pVBInfo->P3c4, 0x34, Tempax); /* SR34[7:0]->VRS[7:0] */
+ /* CR10 VRS */
+ Tempax = pVBInfo->XGINEWUB_CRT1Table[index].CR[10];
+ /* SR34[7:0]->VRS[7:0] */
+ xgifb_reg_set(pVBInfo->P3c4, 0x34, Tempax);
Tempcx = Tempax; /* Tempcx <= VRS[7:0] */
- Tempax = pVBInfo->XGINEWUB_CRT1Table[index].CR[9]; /* CR7[7][2] VRS[9][8] */
+ /* CR7[7][2] VRS[9][8] */
+ Tempax = pVBInfo->XGINEWUB_CRT1Table[index].CR[9];
Tempbx = Tempax; /* Tempbx <= CR07[7:0] */
Tempax = Tempax & 0x04; /* Tempax[2]: CR7[2]: VRS[8] */
Tempax >>= 2; /* Tempax[0]: VRS[8] */
- xgifb_reg_and_or(pVBInfo->P3c4, 0x35, ~0x01, Tempax); /* SR35[0]: VRS[8] */
+ /* SR35[0]: VRS[8] */
+ xgifb_reg_and_or(pVBInfo->P3c4, 0x35, ~0x01, Tempax);
Tempcx |= (Tempax << 8); /* Tempcx <= VRS[8:0] */
Tempcx |= ((Tempbx & 0x80) << 2); /* Tempcx <= VRS[9:0] */
- Tempax = pVBInfo->XGINEWUB_CRT1Table[index].CR[14]; /* Tempax: SR0A */
+ /* Tempax: SR0A */
+ Tempax = pVBInfo->XGINEWUB_CRT1Table[index].CR[14];
Tempax &= 0x08; /* SR0A[3] VRS[10] */
Tempcx |= (Tempax << 7); /* Tempcx <= VRS[10:0] */
- Tempax = pVBInfo->XGINEWUB_CRT1Table[index].CR[11]; /* Tempax: CR11 VRE */
+ /* Tempax: CR11 VRE */
+ Tempax = pVBInfo->XGINEWUB_CRT1Table[index].CR[11];
Tempax &= 0x0F; /* Tempax[3:0]: VRE[3:0] */
- Tempbx = pVBInfo->XGINEWUB_CRT1Table[index].CR[14]; /* Tempbx: SR0A */
+ /* Tempbx: SR0A */
+ Tempbx = pVBInfo->XGINEWUB_CRT1Table[index].CR[14];
Tempbx &= 0x20; /* Tempbx[5]: SR0A[5]: VRE[4] */
Tempbx >>= 1; /* Tempbx[4]: VRE[4] */
Tempax |= Tempbx; /* Tempax[4:0]: VRE[4:0] */
@@ -923,10 +992,13 @@
if (Tempbx <= Tempcx) /* VRE <= VRS */
Tempbx |= 0x20; /* VRE + 0x20 */
- Tempax = (Tempbx << 2) & 0xFF; /* Tempax: Tempax[7:0]; VRE[5:0]00 */
- xgifb_reg_and_or(pVBInfo->P3c4, 0x3F, ~0xFC, Tempax); /* SR3F[7:2]:VRE[5:0] */
+ /* Tempax: Tempax[7:0]; VRE[5:0]00 */
+ Tempax = (Tempbx << 2) & 0xFF;
+ /* SR3F[7:2]:VRE[5:0] */
+ xgifb_reg_and_or(pVBInfo->P3c4, 0x3F, ~0xFC, Tempax);
Tempax = Tempcx >> 8;
- xgifb_reg_and_or(pVBInfo->P3c4, 0x35, ~0x07, Tempax); /* SR35[2:0]:VRS[10:8] */
+ /* SR35[2:0]:VRS[10:8] */
+ xgifb_reg_and_or(pVBInfo->P3c4, 0x35, ~0x07, Tempax);
}
}
@@ -970,20 +1042,25 @@
if (ModeNo <= 0x13) {
b3CC = (unsigned char) inb(XGI_P3cc);
if (b3CC & 0x40)
- xgifb_reg_or(pVBInfo->P3c4, 0x30, 0x20); /* Hsync polarity */
+ /* Hsync polarity */
+ xgifb_reg_or(pVBInfo->P3c4, 0x30, 0x20);
if (b3CC & 0x80)
- xgifb_reg_or(pVBInfo->P3c4, 0x35, 0x80); /* Vsync polarity */
+ /* Vsync polarity */
+ xgifb_reg_or(pVBInfo->P3c4, 0x35, 0x80);
} else {
Data = pVBInfo->RefIndex[RefreshRateTableIndex].Ext_InfoFlag;
if (Data & 0x4000)
- xgifb_reg_or(pVBInfo->P3c4, 0x30, 0x20); /* Hsync polarity */
+ /* Hsync polarity */
+ xgifb_reg_or(pVBInfo->P3c4, 0x30, 0x20);
if (Data & 0x8000)
- xgifb_reg_or(pVBInfo->P3c4, 0x35, 0x80); /* Vsync polarity */
+ /* Vsync polarity */
+ xgifb_reg_or(pVBInfo->P3c4, 0x35, 0x80);
}
}
static void XGI_SetXG27LCD(struct vb_device_info *pVBInfo,
- unsigned short RefreshRateTableIndex, unsigned short ModeNo)
+ unsigned short RefreshRateTableIndex,
+ unsigned short ModeNo)
{
unsigned short Data, Temp, b3CC;
unsigned short XGI_P3cc;
@@ -1018,15 +1095,19 @@
if (ModeNo <= 0x13) {
b3CC = (unsigned char) inb(XGI_P3cc);
if (b3CC & 0x40)
- xgifb_reg_or(pVBInfo->P3c4, 0x30, 0x20); /* Hsync polarity */
+ /* Hsync polarity */
+ xgifb_reg_or(pVBInfo->P3c4, 0x30, 0x20);
if (b3CC & 0x80)
- xgifb_reg_or(pVBInfo->P3c4, 0x35, 0x80); /* Vsync polarity */
+ /* Vsync polarity */
+ xgifb_reg_or(pVBInfo->P3c4, 0x35, 0x80);
} else {
Data = pVBInfo->RefIndex[RefreshRateTableIndex].Ext_InfoFlag;
if (Data & 0x4000)
- xgifb_reg_or(pVBInfo->P3c4, 0x30, 0x20); /* Hsync polarity */
+ /* Hsync polarity */
+ xgifb_reg_or(pVBInfo->P3c4, 0x30, 0x20);
if (Data & 0x8000)
- xgifb_reg_or(pVBInfo->P3c4, 0x35, 0x80); /* Vsync polarity */
+ /* Vsync polarity */
+ xgifb_reg_or(pVBInfo->P3c4, 0x35, 0x80);
}
}
@@ -1036,8 +1117,9 @@
/* Output : CRT1 CRTC */
/* Description : Modify CRT1 Hsync/Vsync to fix LCD mode timing */
/* --------------------------------------------------------------------- */
-static void XGI_UpdateXG21CRTC(unsigned short ModeNo, struct vb_device_info *pVBInfo,
- unsigned short RefreshRateTableIndex)
+static void XGI_UpdateXG21CRTC(unsigned short ModeNo,
+ struct vb_device_info *pVBInfo,
+ unsigned short RefreshRateTableIndex)
{
int i, index = -1;
@@ -1048,13 +1130,13 @@
index = i;
}
} else {
- if (ModeNo == 0x2E
- && (pVBInfo->RefIndex[RefreshRateTableIndex].Ext_CRT1CRTC
- == RES640x480x60))
+ if (ModeNo == 0x2E &&
+ (pVBInfo->RefIndex[RefreshRateTableIndex].Ext_CRT1CRTC ==
+ RES640x480x60))
index = 12;
- else if (ModeNo == 0x2E
- && (pVBInfo->RefIndex[RefreshRateTableIndex].Ext_CRT1CRTC
- == RES640x480x72))
+ else if (ModeNo == 0x2E &&
+ (pVBInfo->RefIndex[RefreshRateTableIndex].
+ Ext_CRT1CRTC == RES640x480x72))
index = 13;
else if (ModeNo == 0x2F)
index = 14;
@@ -1157,16 +1239,19 @@
unsigned short resindex;
if (ModeNo <= 0x13)
- resindex = pVBInfo->SModeIDTable[ModeIdIndex].St_ResInfo; /* si+St_ResInfo */
+ /* si+St_ResInfo */
+ resindex = pVBInfo->SModeIDTable[ModeIdIndex].St_ResInfo;
else
- resindex = pVBInfo->EModeIDTable[ModeIdIndex].Ext_RESINFO; /* si+Ext_ResInfo */
+ /* si+Ext_ResInfo */
+ resindex = pVBInfo->EModeIDTable[ModeIdIndex].Ext_RESINFO;
return resindex;
}
-static void XGI_SetCRT1Offset(unsigned short ModeNo, unsigned short ModeIdIndex,
- unsigned short RefreshRateTableIndex,
- struct xgi_hw_device_info *HwDeviceExtension,
- struct vb_device_info *pVBInfo)
+static void XGI_SetCRT1Offset(unsigned short ModeNo,
+ unsigned short ModeIdIndex,
+ unsigned short RefreshRateTableIndex,
+ struct xgi_hw_device_info *HwDeviceExtension,
+ struct vb_device_info *pVBInfo)
{
unsigned short temp, ah, al, temp2, i, DisplayUnit;
@@ -1254,29 +1339,39 @@
{
unsigned short tempbx;
- unsigned short LCDXlat1VCLK[4] = { VCLK65 + 2, VCLK65 + 2, VCLK65 + 2,
- VCLK65 + 2 };
- unsigned short LCDXlat2VCLK[4] = { VCLK108_2 + 5, VCLK108_2 + 5,
- VCLK108_2 + 5, VCLK108_2 + 5 };
+ unsigned short LCDXlat1VCLK[4] = { VCLK65 + 2,
+ VCLK65 + 2,
+ VCLK65 + 2,
+ VCLK65 + 2 };
+ unsigned short LCDXlat2VCLK[4] = { VCLK108_2 + 5,
+ VCLK108_2 + 5,
+ VCLK108_2 + 5,
+ VCLK108_2 + 5 };
unsigned short LVDSXlat1VCLK[4] = { VCLK40, VCLK40, VCLK40, VCLK40 };
- unsigned short LVDSXlat2VCLK[4] = { VCLK65 + 2, VCLK65 + 2, VCLK65 + 2,
- VCLK65 + 2 };
- unsigned short LVDSXlat3VCLK[4] = { VCLK65 + 2, VCLK65 + 2, VCLK65 + 2,
- VCLK65 + 2 };
+ unsigned short LVDSXlat2VCLK[4] = { VCLK65 + 2,
+ VCLK65 + 2,
+ VCLK65 + 2,
+ VCLK65 + 2 };
+ unsigned short LVDSXlat3VCLK[4] = { VCLK65 + 2,
+ VCLK65 + 2,
+ VCLK65 + 2,
+ VCLK65 + 2 };
unsigned short CRT2Index, VCLKIndex;
unsigned short modeflag, resinfo;
unsigned char *CHTVVCLKPtr = NULL;
if (ModeNo <= 0x13) {
- modeflag = pVBInfo->SModeIDTable[ModeIdIndex].St_ModeFlag; /* si+St_ResInfo */
+ /* si+St_ResInfo */
+ modeflag = pVBInfo->SModeIDTable[ModeIdIndex].St_ModeFlag;
resinfo = pVBInfo->SModeIDTable[ModeIdIndex].St_ResInfo;
CRT2Index = pVBInfo->SModeIDTable[ModeIdIndex].St_CRT2CRTC;
} else {
- modeflag = pVBInfo->EModeIDTable[ModeIdIndex].Ext_ModeFlag; /* si+Ext_ResInfo */
+ /* si+Ext_ResInfo */
+ modeflag = pVBInfo->EModeIDTable[ModeIdIndex].Ext_ModeFlag;
resinfo = pVBInfo->EModeIDTable[ModeIdIndex].Ext_RESINFO;
- CRT2Index
- = pVBInfo->RefIndex[RefreshRateTableIndex].Ext_CRT2CRTC;
+ CRT2Index = pVBInfo->RefIndex[RefreshRateTableIndex].
+ Ext_CRT2CRTC;
}
if (pVBInfo->IF_DEF_LVDS == 0) {
@@ -1291,41 +1386,35 @@
if (pVBInfo->VBInfo & SetCRT2ToHiVisionTV) {
if (pVBInfo->SetFlag & RPLLDIV2XO) {
VCLKIndex = HiTVVCLKDIV2;
-
VCLKIndex += 25;
-
} else {
VCLKIndex = HiTVVCLK;
-
VCLKIndex += 25;
-
}
if (pVBInfo->SetFlag & TVSimuMode) {
if (modeflag & Charx8Dot) {
- VCLKIndex
- = HiTVSimuVCLK;
-
+ VCLKIndex =
+ HiTVSimuVCLK;
VCLKIndex += 25;
-
} else {
- VCLKIndex
- = HiTVTextVCLK;
-
+ VCLKIndex =
+ HiTVTextVCLK;
VCLKIndex += 25;
-
}
}
- if (pVBInfo->VBType & VB_XGI301LV) { /* 301lv */
- if (!(pVBInfo->VBExtInfo
- == VB_YPbPr1080i)) {
- VCLKIndex
- = YPbPr750pVCLK;
+ /* 301lv */
+ if (pVBInfo->VBType & VB_XGI301LV) {
+ if (!(pVBInfo->VBExtInfo ==
+ VB_YPbPr1080i)) {
+ VCLKIndex =
+ YPbPr750pVCLK;
if (!(pVBInfo->VBExtInfo
- == VB_YPbPr750p)) {
- VCLKIndex
- = YPbPr525pVCLK;
+ ==
+ VB_YPbPr750p)) {
+ VCLKIndex =
+ YPbPr525pVCLK;
if (!(pVBInfo->VBExtInfo
== VB_YPbPr525p)) {
VCLKIndex
@@ -1340,27 +1429,27 @@
}
} else {
if (pVBInfo->VBInfo & SetCRT2ToTV) {
- if (pVBInfo->SetFlag
- & RPLLDIV2XO) {
+ if (pVBInfo->SetFlag &
+ RPLLDIV2XO) {
VCLKIndex = TVVCLKDIV2;
-
VCLKIndex += 25;
-
} else {
VCLKIndex = TVVCLK;
-
VCLKIndex += 25;
-
}
}
}
} else { /* for CRT2 */
+ /* Port 3cch */
VCLKIndex = (unsigned char) inb(
- (pVBInfo->P3ca + 0x02)); /* Port 3cch */
+ (pVBInfo->P3ca + 0x02));
VCLKIndex = ((VCLKIndex >> 2) & 0x03);
if (ModeNo > 0x13) {
- VCLKIndex
- = pVBInfo->RefIndex[RefreshRateTableIndex].Ext_CRTVCLK; /* di+Ext_CRTVCLK */
+ /* di+Ext_CRTVCLK */
+ VCLKIndex =
+ pVBInfo->RefIndex[
+ RefreshRateTableIndex].
+ Ext_CRTVCLK;
VCLKIndex &= IndexMask;
}
}
@@ -1403,12 +1492,11 @@
}
} else {
VCLKIndex = VCLKIndex >> 6;
- if ((pVBInfo->LCDResInfo == Panel800x600)
- || (pVBInfo->LCDResInfo == Panel320x480))
+ if ((pVBInfo->LCDResInfo == Panel800x600) ||
+ (pVBInfo->LCDResInfo == Panel320x480))
VCLKIndex = LVDSXlat1VCLK[VCLKIndex];
- else if ((pVBInfo->LCDResInfo == Panel1024x768)
- || (pVBInfo->LCDResInfo
- == Panel1024x768x75))
+ else if ((pVBInfo->LCDResInfo == Panel1024x768) ||
+ (pVBInfo->LCDResInfo == Panel1024x768x75))
VCLKIndex = LVDSXlat2VCLK[VCLKIndex];
else
VCLKIndex = LVDSXlat3VCLK[VCLKIndex];
@@ -1419,10 +1507,11 @@
return VCLKIndex;
}
-static void XGI_SetCRT1VCLK(unsigned short ModeNo, unsigned short ModeIdIndex,
- struct xgi_hw_device_info *HwDeviceExtension,
- unsigned short RefreshRateTableIndex,
- struct vb_device_info *pVBInfo)
+static void XGI_SetCRT1VCLK(unsigned short ModeNo,
+ unsigned short ModeIdIndex,
+ struct xgi_hw_device_info *HwDeviceExtension,
+ unsigned short RefreshRateTableIndex,
+ struct vb_device_info *pVBInfo)
{
unsigned char index, data;
unsigned short vclkindex;
@@ -1461,7 +1550,8 @@
}
if (HwDeviceExtension->jChipType >= XG20) {
- if (pVBInfo->EModeIDTable[ModeIdIndex].Ext_ModeFlag & HalfDCLK) {
+ if (pVBInfo->EModeIDTable[ModeIdIndex].Ext_ModeFlag &
+ HalfDCLK) {
data = xgifb_reg_get(pVBInfo->P3c4, 0x2B);
xgifb_reg_set(pVBInfo->P3c4, 0x2B, data);
data = xgifb_reg_get(pVBInfo->P3c4, 0x2C);
@@ -1575,10 +1665,11 @@
if (ModeNo > 0x13) {
modeflag = pVBInfo->EModeIDTable[ModeIdIndex].Ext_ModeFlag;
- infoflag
- = pVBInfo->RefIndex[RefreshRateTableIndex].Ext_InfoFlag;
+ infoflag = pVBInfo->RefIndex[RefreshRateTableIndex].
+ Ext_InfoFlag;
} else
- modeflag = pVBInfo->SModeIDTable[ModeIdIndex].St_ModeFlag; /* si+St_ModeFlag */
+ /* si+St_ModeFlag */
+ modeflag = pVBInfo->SModeIDTable[ModeIdIndex].St_ModeFlag;
if (xgifb_reg_get(pVBInfo->P3d4, 0x31) & 0x01)
xgifb_reg_and_or(pVBInfo->P3c4, 0x1F, 0x3F, 0x00);
@@ -1652,7 +1743,8 @@
/* if (modeflag&HalfDCLK) //030305 fix lowresolution bug */
/* if (XGINew_IF_DEF_NEW_LOWRES) */
- /* XGI_VesaLowResolution(ModeNo, ModeIdIndex); //030305 fix lowresolution bug */
+ /* XGI_VesaLowResolution(ModeNo, ModeIdIndex);
+ * //030305 fix lowresolution bug */
data = xgifb_reg_get(pVBInfo->P3d4, 0x31);
@@ -1681,7 +1773,9 @@
}
/*
-void XGI_VesaLowResolution(unsigned short ModeNo, unsigned short ModeIdIndex, struct vb_device_info *pVBInfo)
+void XGI_VesaLowResolution(unsigned short ModeNo,
+ unsigned short ModeIdIndex,
+ struct vb_device_info *pVBInfo)
{
unsigned short modeflag;
@@ -1693,17 +1787,37 @@
if (ModeNo > 0x13) {
if (modeflag & DoubleScanMode) {
if (modeflag & HalfDCLK) {
- if (pVBInfo->VBType & VB_XGI301B | VB_XGI302B | VB_XGI301LV | VB_XGI302LV | VB_XGI301C)) {
- if (!(pVBInfo->VBInfo & SetCRT2ToRAMDAC)) {
- if (pVBInfo->VBInfo & SetInSlaveMode) {
- xgifb_reg_and_or(pVBInfo->P3c4, 0x01, 0xf7, 0x00);
- xgifb_reg_and_or(pVBInfo->P3c4, 0x0f, 0x7f, 0x00);
+ if (pVBInfo->VBType & VB_XGI301B |
+ VB_XGI302B |
+ VB_XGI301LV |
+ VB_XGI302LV |
+ VB_XGI301C)) {
+ if (!(pVBInfo->VBInfo &
+ SetCRT2ToRAMDAC)) {
+ if (pVBInfo->VBInfo &
+ SetInSlaveMode) {
+ xgifb_reg_and_or(
+ pVBInfo->P3c4,
+ 0x01,
+ 0xf7,
+ 0x00);
+ xgifb_reg_and_or(
+ pVBInfo->P3c4,
+ 0x0f,
+ 0x7f,
+ 0x00);
return;
}
}
}
- xgifb_reg_and_or(pVBInfo->P3c4, 0x0f, 0xff, 0x80);
- xgifb_reg_and_or(pVBInfo->P3c4, 0x01, 0xf7, 0x00);
+ xgifb_reg_and_or(pVBInfo->P3c4,
+ 0x0f,
+ 0xff,
+ 0x80);
+ xgifb_reg_and_or(pVBInfo->P3c4,
+ 0x01,
+ 0xf7,
+ 0x00);
return;
}
}
@@ -1712,8 +1826,11 @@
}
*/
-static void XGI_WriteDAC(unsigned short dl, unsigned short ah, unsigned short al,
- unsigned short dh, struct vb_device_info *pVBInfo)
+static void XGI_WriteDAC(unsigned short dl,
+ unsigned short ah,
+ unsigned short al,
+ unsigned short dh,
+ struct vb_device_info *pVBInfo)
{
unsigned short temp, bh, bl;
@@ -1831,15 +1948,18 @@
}
}
-static void XGI_GetLVDSResInfo(unsigned short ModeNo, unsigned short ModeIdIndex,
- struct vb_device_info *pVBInfo)
+static void XGI_GetLVDSResInfo(unsigned short ModeNo,
+ unsigned short ModeIdIndex,
+ struct vb_device_info *pVBInfo)
{
unsigned short resindex, xres, yres, modeflag;
if (ModeNo <= 0x13)
- modeflag = pVBInfo->SModeIDTable[ModeIdIndex].St_ResInfo; /* si+St_ResInfo */
+ /* si+St_ResInfo */
+ modeflag = pVBInfo->SModeIDTable[ModeIdIndex].St_ResInfo;
else
- modeflag = pVBInfo->EModeIDTable[ModeIdIndex].Ext_RESINFO; /* si+Ext_ResInfo */
+ /* si+Ext_ResInfo */
+ modeflag = pVBInfo->EModeIDTable[ModeIdIndex].Ext_RESINFO;
/* if (ModeNo > 0x13) */
/* modeflag = pVBInfo->EModeIDTable[ModeIdIndex].Ext_ModeFlag; */
@@ -1847,9 +1967,11 @@
/* modeflag = pVBInfo->SModeIDTable[ModeIdIndex].St_ModeFlag; */
if (ModeNo <= 0x13)
- resindex = pVBInfo->SModeIDTable[ModeIdIndex].St_ResInfo; /* si+St_ResInfo */
+ /* si+St_ResInfo */
+ resindex = pVBInfo->SModeIDTable[ModeIdIndex].St_ResInfo;
else
- resindex = pVBInfo->EModeIDTable[ModeIdIndex].Ext_RESINFO; /* si+Ext_ResInfo */
+ /* si+Ext_ResInfo */
+ resindex = pVBInfo->EModeIDTable[ModeIdIndex].Ext_RESINFO;
/* resindex = XGI_GetResInfo(ModeNo, ModeIdIndex, pVBInfo); */
@@ -1903,19 +2025,21 @@
if (tempbx <= 1) { /* ExpLink */
if (ModeNo <= 0x13) {
- tempal = pVBInfo->SModeIDTable[ModeIdIndex].St_CRT2CRTC; /* find no Ext_CRT2CRTC2 */
+ /* find no Ext_CRT2CRTC2 */
+ tempal = pVBInfo->SModeIDTable[ModeIdIndex].St_CRT2CRTC;
} else {
- tempal
- = pVBInfo->RefIndex[RefreshRateTableIndex].Ext_CRT2CRTC;
+ tempal = pVBInfo->RefIndex[RefreshRateTableIndex].
+ Ext_CRT2CRTC;
}
if (pVBInfo->VBInfo & SetCRT2ToLCDA) {
if (ModeNo <= 0x13)
- tempal
- = pVBInfo->SModeIDTable[ModeIdIndex].St_CRT2CRTC2;
+ tempal = pVBInfo->SModeIDTable[ModeIdIndex].
+ St_CRT2CRTC2;
else
- tempal
- = pVBInfo->RefIndex[RefreshRateTableIndex].Ext_CRT2CRTC2;
+ tempal = pVBInfo->RefIndex[
+ RefreshRateTableIndex].
+ Ext_CRT2CRTC2;
}
if (tempbx & 0x01)
@@ -1933,7 +2057,8 @@
tempcx = LVDSDesDataLen2;
}
/* mov di, word ptr cs:LCDDataList[bx] */
- /* tempdi = pVideoMemory[LCDDataList + tempbx * 2] | (pVideoMemory[LCDDataList + tempbx * 2 + 1] << 8); */
+ /* tempdi = pVideoMemory[LCDDataList + tempbx * 2] |
+ (pVideoMemory[LCDDataList + tempbx * 2 + 1] << 8); */
switch (tempbx) {
case 0:
@@ -2243,36 +2368,36 @@
return &XGI_CetLCDDes1024x768Data[tempal];
break;
case 3:
- if ((pVBInfo->VBType & VB_XGI301LV) || (pVBInfo->VBType
- & VB_XGI302LV))
+ if ((pVBInfo->VBType & VB_XGI301LV) ||
+ (pVBInfo->VBType & VB_XGI302LV))
return &XGI_ExtLCDDLDes1280x1024Data[tempal];
else
return &XGI_ExtLCDDes1280x1024Data[tempal];
break;
case 4:
- if ((pVBInfo->VBType & VB_XGI301LV) || (pVBInfo->VBType
- & VB_XGI302LV))
+ if ((pVBInfo->VBType & VB_XGI301LV) ||
+ (pVBInfo->VBType & VB_XGI302LV))
return &XGI_StLCDDLDes1280x1024Data[tempal];
else
return &XGI_StLCDDes1280x1024Data[tempal];
break;
case 5:
- if ((pVBInfo->VBType & VB_XGI301LV) || (pVBInfo->VBType
- & VB_XGI302LV))
+ if ((pVBInfo->VBType & VB_XGI301LV) ||
+ (pVBInfo->VBType & VB_XGI302LV))
return &XGI_CetLCDDLDes1280x1024Data[tempal];
else
return &XGI_CetLCDDes1280x1024Data[tempal];
break;
case 6:
- if ((pVBInfo->VBType & VB_XGI301LV) || (pVBInfo->VBType
- & VB_XGI302LV))
+ if ((pVBInfo->VBType & VB_XGI301LV) ||
+ (pVBInfo->VBType & VB_XGI302LV))
return &XGI_ExtLCDDLDes1400x1050Data[tempal];
else
return &XGI_ExtLCDDes1400x1050Data[tempal];
break;
case 7:
- if ((pVBInfo->VBType & VB_XGI301LV) || (pVBInfo->VBType
- & VB_XGI302LV))
+ if ((pVBInfo->VBType & VB_XGI301LV) ||
+ (pVBInfo->VBType & VB_XGI302LV))
return &XGI_StLCDDLDes1400x1050Data[tempal];
else
return &XGI_StLCDDes1400x1050Data[tempal];
@@ -2284,15 +2409,15 @@
return &XGI_CetLCDDes1400x1050Data2[tempal];
break;
case 10:
- if ((pVBInfo->VBType & VB_XGI301LV) || (pVBInfo->VBType
- & VB_XGI302LV))
+ if ((pVBInfo->VBType & VB_XGI301LV) ||
+ (pVBInfo->VBType & VB_XGI302LV))
return &XGI_ExtLCDDLDes1600x1200Data[tempal];
else
return &XGI_ExtLCDDes1600x1200Data[tempal];
break;
case 11:
- if ((pVBInfo->VBType & VB_XGI301LV) || (pVBInfo->VBType
- & VB_XGI302LV))
+ if ((pVBInfo->VBType & VB_XGI301LV) ||
+ (pVBInfo->VBType & VB_XGI302LV))
return &XGI_StLCDDLDes1600x1200Data[tempal];
else
return &XGI_StLCDDes1600x1200Data[tempal];
@@ -2310,22 +2435,22 @@
return &XGI_CetLCDDes1024x768x75Data[tempal];
break;
case 16:
- if ((pVBInfo->VBType & VB_XGI301LV) || (pVBInfo->VBType
- & VB_XGI302LV))
+ if ((pVBInfo->VBType & VB_XGI301LV) ||
+ (pVBInfo->VBType & VB_XGI302LV))
return &XGI_ExtLCDDLDes1280x1024x75Data[tempal];
else
return &XGI_ExtLCDDes1280x1024x75Data[tempal];
break;
case 17:
- if ((pVBInfo->VBType & VB_XGI301LV) || (pVBInfo->VBType
- & VB_XGI302LV))
+ if ((pVBInfo->VBType & VB_XGI301LV) ||
+ (pVBInfo->VBType & VB_XGI302LV))
return &XGI_StLCDDLDes1280x1024x75Data[tempal];
else
return &XGI_StLCDDes1280x1024x75Data[tempal];
break;
case 18:
- if ((pVBInfo->VBType & VB_XGI301LV) || (pVBInfo->VBType
- & VB_XGI302LV))
+ if ((pVBInfo->VBType & VB_XGI301LV) ||
+ (pVBInfo->VBType & VB_XGI302LV))
return &XGI_CetLCDDLDes1280x1024x75Data[tempal];
else
return &XGI_CetLCDDes1280x1024x75Data[tempal];
@@ -2423,7 +2548,8 @@
i++;
}
- if (table == 0x00) { /* 07/05/22 */
+ /* 07/05/22 */
+ if (table == 0x00) {
} else if (table == 0x01) {
} else if (table == 0x04) {
switch (tempdi[i].DATAPTR) {
@@ -2528,14 +2654,12 @@
if (pVBInfo->VBInfo & (SetCRT2ToLCD | SetCRT2ToLCDA)) {
if (!(pVBInfo->LCDInfo & (SetLCDtoNonExpanding
| EnableScalingLCD))) {
- if ((pVBInfo->LCDResInfo == Panel1024x768)
- || (pVBInfo->LCDResInfo
- == Panel1024x768x75)) {
+ if ((pVBInfo->LCDResInfo == Panel1024x768) ||
+ (pVBInfo->LCDResInfo == Panel1024x768x75)) {
pVBInfo->HDE = 1024;
pVBInfo->VDE = 768;
- } else if ((pVBInfo->LCDResInfo == Panel1280x1024)
- || (pVBInfo->LCDResInfo
- == Panel1280x1024x75)) {
+ } else if ((pVBInfo->LCDResInfo == Panel1280x1024) ||
+ (pVBInfo->LCDResInfo == Panel1280x1024x75)) {
pVBInfo->HDE = 1280;
pVBInfo->VDE = 1024;
} else if (pVBInfo->LCDResInfo == Panel1400x1050) {
@@ -2569,17 +2693,17 @@
index = index & IndexMask;
- if ((pVBInfo->IF_DEF_ScaleLCD == 0) || ((pVBInfo->IF_DEF_ScaleLCD == 1)
- && (!(pVBInfo->LCDInfo & EnableScalingLCD)))) {
+ if ((pVBInfo->IF_DEF_ScaleLCD == 0) ||
+ ((pVBInfo->IF_DEF_ScaleLCD == 1) &&
+ (!(pVBInfo->LCDInfo & EnableScalingLCD)))) {
tempbx = 0;
if (pVBInfo->VBInfo & (SetCRT2ToLCD | SetCRT2ToLCDA)) {
- LCDPtr
- = (struct XGI_LVDSCRT1HDataStruct *) XGI_GetLcdPtr(
- tempbx, ModeNo,
- ModeIdIndex,
- RefreshRateTableIndex,
- pVBInfo);
+ LCDPtr = (struct XGI_LVDSCRT1HDataStruct *)
+ XGI_GetLcdPtr(tempbx, ModeNo,
+ ModeIdIndex,
+ RefreshRateTableIndex,
+ pVBInfo);
for (i = 0; i < 8; i++)
pVBInfo->TimingH[0].data[i] = LCDPtr[0].Reg[i];
@@ -2587,23 +2711,30 @@
if (pVBInfo->IF_DEF_CH7007 == 1) {
if (pVBInfo->VBInfo & SetCRT2ToTV) {
- CH7007TV_TimingHPtr
- = (struct XGI_CH7007TV_TimingHStruct *) XGI_GetTVPtr(
- tempbx,
- ModeNo,
- ModeIdIndex,
- RefreshRateTableIndex,
- pVBInfo);
+ CH7007TV_TimingHPtr =
+ (struct XGI_CH7007TV_TimingHStruct *)
+ XGI_GetTVPtr(
+ tempbx,
+ ModeNo,
+ ModeIdIndex,
+ RefreshRateTableIndex,
+ pVBInfo);
for (i = 0; i < 8; i++)
- pVBInfo->TimingH[0].data[i]
- = CH7007TV_TimingHPtr[0].data[i];
+ pVBInfo->TimingH[0].data[i] =
+ CH7007TV_TimingHPtr[0].data[i];
}
}
/* if (pVBInfo->IF_DEF_CH7017 == 1) {
if (pVBInfo->VBInfo & SetCRT2ToTV)
- TVPtr = (struct XGI330_CHTVDataStruct *)XGI_GetTVPtr(tempbx, ModeNo, ModeIdIndex, RefreshRateTableIndex, pVBInfo);
+ TVPtr = (struct XGI330_CHTVDataStruct *)
+ XGI_GetTVPtr(
+ tempbx,
+ ModeNo,
+ ModeIdIndex,
+ RefreshRateTableIndex,
+ pVBInfo);
}
*/
@@ -2619,34 +2750,41 @@
tempbx = 1;
if (pVBInfo->VBInfo & (SetCRT2ToLCD | SetCRT2ToLCDA)) {
- LCDPtr1
- = (struct XGI_LVDSCRT1VDataStruct *) XGI_GetLcdPtr(
- tempbx, ModeNo,
- ModeIdIndex,
- RefreshRateTableIndex,
- pVBInfo);
+ LCDPtr1 = (struct XGI_LVDSCRT1VDataStruct *)
+ XGI_GetLcdPtr(
+ tempbx,
+ ModeNo,
+ ModeIdIndex,
+ RefreshRateTableIndex,
+ pVBInfo);
for (i = 0; i < 7; i++)
pVBInfo->TimingV[0].data[i] = LCDPtr1[0].Reg[i];
}
if (pVBInfo->IF_DEF_CH7007 == 1) {
if (pVBInfo->VBInfo & SetCRT2ToTV) {
- CH7007TV_TimingVPtr
- = (struct XGI_CH7007TV_TimingVStruct *) XGI_GetTVPtr(
- tempbx,
- ModeNo,
- ModeIdIndex,
- RefreshRateTableIndex,
- pVBInfo);
+ CH7007TV_TimingVPtr =
+ (struct XGI_CH7007TV_TimingVStruct *)
+ XGI_GetTVPtr(
+ tempbx,
+ ModeNo,
+ ModeIdIndex,
+ RefreshRateTableIndex,
+ pVBInfo);
for (i = 0; i < 7; i++)
- pVBInfo->TimingV[0].data[i]
- = CH7007TV_TimingVPtr[0].data[i];
+ pVBInfo->TimingV[0].data[i] =
+ CH7007TV_TimingVPtr[0].data[i];
}
}
/* if (pVBInfo->IF_DEF_CH7017 == 1) {
if (pVBInfo->VBInfo & SetCRT2ToTV)
- TVPtr = (struct XGI330_CHTVDataStruct *)XGI_GetTVPtr(tempbx, ModeNo, ModeIdIndex, RefreshRateTableIndex, pVBInfo);
+ TVPtr = (struct XGI330_CHTVDataStruct *)
+ XGI_GetTVPtr(tempbx,
+ ModeNo,
+ ModeIdIndex,
+ RefreshRateTableIndex,
+ pVBInfo);
}
*/
@@ -2723,8 +2861,9 @@
return i;
}
-static void XGI_GetLCDSync(unsigned short *HSyncWidth, unsigned short *VSyncWidth,
- struct vb_device_info *pVBInfo)
+static void XGI_GetLCDSync(unsigned short *HSyncWidth,
+ unsigned short *VSyncWidth,
+ struct vb_device_info *pVBInfo)
{
unsigned short Index;
@@ -2754,33 +2893,35 @@
& (SetCRT2ToLCD | SetCRT2ToLCDA))) {
if (pVBInfo->IF_DEF_OEMUtil == 1) {
tempbx = 8;
- LCDPtr
- = (struct XGI330_LCDDataDesStruct *) XGI_GetLcdPtr(
- tempbx,
- ModeNo,
- ModeIdIndex,
- RefreshRateTableIndex,
- pVBInfo);
+ LCDPtr = (struct XGI330_LCDDataDesStruct *)
+ XGI_GetLcdPtr(tempbx,
+ ModeNo,
+ ModeIdIndex,
+ RefreshRateTableIndex,
+ pVBInfo);
}
- if ((pVBInfo->IF_DEF_OEMUtil == 0) || (LCDPtr == NULL)) {
+ if ((pVBInfo->IF_DEF_OEMUtil == 0) ||
+ (LCDPtr == NULL)) {
tempbx = 3;
if (pVBInfo->LCDInfo & EnableScalingLCD)
- LCDPtr1
- = (struct XGI330_LCDDataDesStruct2 *) XGI_GetLcdPtr(
- tempbx,
- ModeNo,
- ModeIdIndex,
- RefreshRateTableIndex,
- pVBInfo);
+ LCDPtr1 =
+ (struct XGI330_LCDDataDesStruct2 *)
+ XGI_GetLcdPtr(
+ tempbx,
+ ModeNo,
+ ModeIdIndex,
+ RefreshRateTableIndex,
+ pVBInfo);
else
- LCDPtr
- = (struct XGI330_LCDDataDesStruct *) XGI_GetLcdPtr(
- tempbx,
- ModeNo,
- ModeIdIndex,
- RefreshRateTableIndex,
- pVBInfo);
+ LCDPtr =
+ (struct XGI330_LCDDataDesStruct *)
+ XGI_GetLcdPtr(
+ tempbx,
+ ModeNo,
+ ModeIdIndex,
+ RefreshRateTableIndex,
+ pVBInfo);
}
XGI_GetLCDSync(&tempax, &tempbx, pVBInfo);
@@ -2788,14 +2929,12 @@
push2 = tempax;
/* GetLCDResInfo */
- if ((pVBInfo->LCDResInfo == Panel1024x768)
- || (pVBInfo->LCDResInfo
- == Panel1024x768x75)) {
+ if ((pVBInfo->LCDResInfo == Panel1024x768) ||
+ (pVBInfo->LCDResInfo == Panel1024x768x75)) {
tempax = 1024;
tempbx = 768;
- } else if ((pVBInfo->LCDResInfo == Panel1280x1024)
- || (pVBInfo->LCDResInfo
- == Panel1280x1024x75)) {
+ } else if ((pVBInfo->LCDResInfo == Panel1280x1024) ||
+ (pVBInfo->LCDResInfo == Panel1280x1024x75)) {
tempax = 1280;
tempbx = 1024;
} else if (pVBInfo->LCDResInfo == Panel1400x1050) {
@@ -2813,8 +2952,8 @@
pVBInfo->VGAVDE = tempbx;
}
- if ((pVBInfo->IF_DEF_ScaleLCD == 1)
- && (pVBInfo->LCDInfo & EnableScalingLCD)) {
+ if ((pVBInfo->IF_DEF_ScaleLCD == 1) &&
+ (pVBInfo->LCDInfo & EnableScalingLCD)) {
tempax = pVBInfo->HDE;
tempbx = pVBInfo->VDE;
}
@@ -2961,16 +3100,18 @@
if (pVBInfo->VBType & VB_XGI301C) {
temp2 = push3;
- xgifb_reg_set(pVBInfo->Part4Port, 0x3c,
- (unsigned short) (temp2 & 0xff));
- xgifb_reg_set(pVBInfo->Part4Port, 0x3b,
- (unsigned short) ((temp2 >> 8)
- & 0xff));
+ xgifb_reg_set(pVBInfo->Part4Port,
+ 0x3c,
+ (unsigned short) (temp2 & 0xff));
+ xgifb_reg_set(pVBInfo->Part4Port,
+ 0x3b,
+ (unsigned short) ((temp2 >> 8) &
+ 0xff));
tempbx = (unsigned short) (temp2 >> 16);
xgifb_reg_and_or(pVBInfo->Part4Port, 0x3a,
~0xc0,
- (unsigned short) ((tempbx
- & 0xff) << 6));
+ (unsigned short) ((tempbx &
+ 0xff) << 6));
tempcx = pVBInfo->VGAVDE;
if (tempcx == pVBInfo->VDE)
@@ -3072,12 +3213,14 @@
unsigned char *CHTVVCLKPtr = NULL;
if (ModeNo <= 0x13)
- modeflag = pVBInfo->SModeIDTable[ModeIdIndex].St_ModeFlag; /* si+St_ResInfo */
+ /* si+St_ResInfo */
+ modeflag = pVBInfo->SModeIDTable[ModeIdIndex].St_ModeFlag;
else
- modeflag = pVBInfo->EModeIDTable[ModeIdIndex].Ext_ModeFlag; /* si+Ext_ResInfo */
+ /* si+Ext_ResInfo */
+ modeflag = pVBInfo->EModeIDTable[ModeIdIndex].Ext_ModeFlag;
- if ((pVBInfo->SetFlag & ProgrammingCRT2) && (!(pVBInfo->LCDInfo
- & EnableScalingLCD))) { /* {LCDA/LCDB} */
+ if ((pVBInfo->SetFlag & ProgrammingCRT2) &&
+ (!(pVBInfo->LCDInfo & EnableScalingLCD))) { /* {LCDA/LCDB} */
index = XGI_GetLCDCapPtr(pVBInfo);
tempal = pVBInfo->LCDCapList[index].LCD_VCLK;
@@ -3085,8 +3228,12 @@
return tempal;
/* {TV} */
- if (pVBInfo->VBType & (VB_XGI301B | VB_XGI302B | VB_XGI301LV
- | VB_XGI302LV | VB_XGI301C)) {
+ if (pVBInfo->VBType &
+ (VB_XGI301B |
+ VB_XGI302B |
+ VB_XGI301LV |
+ VB_XGI302LV |
+ VB_XGI301C)) {
if (pVBInfo->VBInfo & SetCRT2ToHiVisionTV) {
tempal = HiTVVCLKDIV2;
if (!(pVBInfo->TVInfo & RPLLDIV2XO))
@@ -3121,11 +3268,14 @@
if (pVBInfo->VBInfo & SetCRT2ToTV)
return tempal;
}
- /* else if ((pVBInfo->IF_DEF_CH7017==1)&&(pVBInfo->VBType&VB_CH7017)) {
+ /* else if ((pVBInfo->IF_DEF_CH7017==1) &&
+ (pVBInfo->VBType&VB_CH7017)) {
if (ModeNo<=0x13)
- *tempal = pVBInfo->SModeIDTable[ModeIdIndex].St_CRT2CRTC;
+ *tempal = pVBInfo->SModeIDTable[ModeIdIndex].
+ St_CRT2CRTC;
else
- *tempal = pVBInfo->RefIndex[RefreshRateTableIndex].Ext_CRT2CRTC;
+ *tempal = pVBInfo->RefIndex[
+ RefreshRateTableIndex].Ext_CRT2CRTC;
*tempal = *tempal & 0x1F;
tempbx = 0;
if (pVBInfo->TVInfo & SetPALTV)
@@ -3136,15 +3286,18 @@
} */
} /* {End of VB} */
- if ((pVBInfo->IF_DEF_CH7007 == 1) && (pVBInfo->VBType & VB_CH7007)) { /* [Billy] 07/05/08 CH7007 */
- /* VideoDebugPrint((0, "XGI_GetVCLKPtr: pVBInfo->IF_DEF_CH7007==1\n")); */
+ if ((pVBInfo->IF_DEF_CH7007 == 1) &&
+ (pVBInfo->VBType & VB_CH7007)) { /* [Billy] 07/05/08 CH7007 */
+ /* VideoDebugPrint((
+ 0,
+ "XGI_GetVCLKPtr: pVBInfo->IF_DEF_CH7007==1\n")); */
if ((pVBInfo->VBInfo & SetCRT2ToTV)) {
if (ModeNo <= 0x13) {
- tempal
- = pVBInfo->SModeIDTable[ModeIdIndex].St_CRT2CRTC;
+ tempal = pVBInfo->SModeIDTable[ModeIdIndex].
+ St_CRT2CRTC;
} else {
- tempal
- = pVBInfo->RefIndex[RefreshRateTableIndex].Ext_CRT2CRTC;
+ tempal = pVBInfo->RefIndex[
+ RefreshRateTableIndex].Ext_CRT2CRTC;
}
tempal = tempal & 0x0F;
@@ -3208,7 +3361,8 @@
tempal = tempal >> 2;
tempal &= 0x03;
- if ((pVBInfo->LCDInfo & EnableScalingLCD) && (modeflag & Charx8Dot)) /* for Dot8 Scaling LCD */
+ /* for Dot8 Scaling LCD */
+ if ((pVBInfo->LCDInfo & EnableScalingLCD) && (modeflag & Charx8Dot))
tempal = tempal ^ tempal; /* ; set to VCLK25MHz always */
if (ModeNo <= 0x13)
@@ -3222,7 +3376,9 @@
unsigned char *di_1, struct vb_device_info *pVBInfo)
{
if (pVBInfo->IF_DEF_CH7007 == 1) { /* [Billy] 2007/05/16 */
- /* VideoDebugPrint((0, "XGI_GetVCLKLen: pVBInfo->IF_DEF_CH7007==1\n")); */
+ /* VideoDebugPrint((
+ 0,
+ "XGI_GetVCLKLen: pVBInfo->IF_DEF_CH7007==1\n")); */
*di_0 = (unsigned char) XGI_CH7007VCLKData[tempal].SR2B;
*di_1 = (unsigned char) XGI_CH7007VCLKData[tempal].SR2C;
} else if (pVBInfo->VBType & (VB_XGI301 | VB_XGI301B | VB_XGI302B
@@ -3291,7 +3447,8 @@
temp &= 0x0f;
if (!(temp == 0x08)) {
- tempax = xgifb_reg_get(pVBInfo->Part1Port, 0x13); /* Check ChannelA by Part1_13 [2003/10/03] */
+ /* Check ChannelA by Part1_13 [2003/10/03] */
+ tempax = xgifb_reg_get(pVBInfo->Part1Port, 0x13);
if (tempax & 0x04)
tempcl = tempcl | ActiveLCD;
@@ -3388,13 +3545,12 @@
tempbx = VB_XGI301LV;
if (flag >= 0xE0) {
tempbx = VB_XGI302LV;
- tempah
- = xgifb_reg_get(
- pVBInfo->Part4Port,
- 0x39);
+ tempah = xgifb_reg_get(
+ pVBInfo->Part4Port,
+ 0x39);
if (tempah != 0xFF)
- tempbx
- = VB_XGI301C;
+ tempbx =
+ VB_XGI301C;
}
}
}
@@ -3436,7 +3592,8 @@
tempbx = 0;
if (pVBInfo->VBType & 0xFFFF) {
- temp = xgifb_reg_get(pVBInfo->P3d4, 0x30); /* Check Display Device */
+ /* Check Display Device */
+ temp = xgifb_reg_get(pVBInfo->P3d4, 0x30);
tempbx = tempbx | temp;
temp = xgifb_reg_get(pVBInfo->P3d4, 0x31);
push = temp;
@@ -3455,29 +3612,34 @@
if ((pVBInfo->Set_VGAType >= XG20)
|| (pVBInfo->Set_VGAType >= XG40)) {
if (pVBInfo->IF_DEF_LVDS == 0) {
- /* if ((pVBInfo->VBType & VB_XGI302B) || (pVBInfo->VBType & VB_XGI301LV) || (pVBInfo->VBType & VB_XGI302LV) || (pVBInfo->VBType & VB_XGI301C)) */
- if (pVBInfo->VBType & (VB_XGI302B
- | VB_XGI301LV
- | VB_XGI302LV
- | VB_XGI301C)) {
+ /* if ((pVBInfo->VBType & VB_XGI302B)
+ || (pVBInfo->VBType & VB_XGI301LV)
+ || (pVBInfo->VBType & VB_XGI302LV)
+ || (pVBInfo->VBType & VB_XGI301C))
+ */
+ if (pVBInfo->VBType &
+ (VB_XGI302B |
+ VB_XGI301LV |
+ VB_XGI302LV |
+ VB_XGI301C)) {
if (temp & EnableDualEdge) {
- tempbx
- |= SetCRT2ToDualEdge;
+ tempbx |=
+ SetCRT2ToDualEdge;
if (temp & SetToLCDA)
- tempbx
- |= SetCRT2ToLCDA;
+ tempbx |=
+ SetCRT2ToLCDA;
}
}
} else if (pVBInfo->IF_DEF_CH7017 == 1) {
if (pVBInfo->VBType & VB_CH7017) {
if (temp & EnableDualEdge) {
- tempbx
- |= SetCRT2ToDualEdge;
+ tempbx |=
+ SetCRT2ToDualEdge;
if (temp & SetToLCDA)
- tempbx
- |= SetCRT2ToLCDA;
+ tempbx |=
+ SetCRT2ToLCDA;
}
}
}
@@ -3485,29 +3647,30 @@
}
if (pVBInfo->IF_DEF_YPbPr == 1) {
- if (((pVBInfo->IF_DEF_LVDS == 0) && ((pVBInfo->VBType
- & VB_XGI301LV) || (pVBInfo->VBType
- & VB_XGI302LV) || (pVBInfo->VBType
- & VB_XGI301C)))
- || ((pVBInfo->IF_DEF_CH7017 == 1)
- && (pVBInfo->VBType
- & VB_CH7017))
- || ((pVBInfo->IF_DEF_CH7007 == 1)
- && (pVBInfo->VBType
- & VB_CH7007))) { /* [Billy] 07/05/04 */
+ /* [Billy] 07/05/04 */
+ if (((pVBInfo->IF_DEF_LVDS == 0) &&
+ ((pVBInfo->VBType & VB_XGI301LV) ||
+ (pVBInfo->VBType & VB_XGI302LV) ||
+ (pVBInfo->VBType & VB_XGI301C))) ||
+ ((pVBInfo->IF_DEF_CH7017 == 1) &&
+ (pVBInfo->VBType & VB_CH7017)) ||
+ ((pVBInfo->IF_DEF_CH7007 == 1) &&
+ (pVBInfo->VBType & VB_CH7007))) {
if (temp & SetYPbPr) { /* temp = CR38 */
if (pVBInfo->IF_DEF_HiVision == 1) {
+ /* shampoo add for new
+ * scratch */
temp = xgifb_reg_get(
pVBInfo->P3d4,
- 0x35); /* shampoo add for new scratch */
+ 0x35);
temp &= YPbPrMode;
tempbx |= SetCRT2ToHiVisionTV;
if (temp != YPbPrMode1080i) {
- tempbx
- &= (~SetCRT2ToHiVisionTV);
- tempbx
- |= SetCRT2ToYPbPr;
+ tempbx &=
+ (~SetCRT2ToHiVisionTV);
+ tempbx |=
+ SetCRT2ToYPbPr;
}
}
@@ -3532,11 +3695,13 @@
}
} else { /* 3nd party chip */
if (pVBInfo->IF_DEF_CH7017 == 1)
- temp = (SetCRT2ToTV | SetCRT2ToLCD
- | SetCRT2ToLCDA);
- else if (pVBInfo->IF_DEF_CH7007 == 1) { /* [Billy] 07/05/03 */
+ temp = (SetCRT2ToTV |
+ SetCRT2ToLCD |
+ SetCRT2ToLCDA);
+ /* [Billy] 07/05/03 */
+ else if (pVBInfo->IF_DEF_CH7007 == 1)
temp = SetCRT2ToTV;
- } else
+ else
temp = SetCRT2ToLCD;
}
@@ -3549,60 +3714,67 @@
if (!(pVBInfo->VBType & VB_NoLCD)) {
if (tempbx & SetCRT2ToLCDA) {
if (tempbx & SetSimuScanMode)
- tempbx
- &= (~(SetCRT2ToLCD
- | SetCRT2ToRAMDAC
- | SwitchToCRT2));
+ tempbx &= (~(SetCRT2ToLCD |
+ SetCRT2ToRAMDAC |
+ SwitchToCRT2));
else
- tempbx
- &= (~(SetCRT2ToLCD
- | SetCRT2ToRAMDAC
- | SetCRT2ToTV
- | SwitchToCRT2));
+ tempbx &= (~(SetCRT2ToLCD |
+ SetCRT2ToRAMDAC |
+ SetCRT2ToTV |
+ SwitchToCRT2));
}
}
}
/* shampoo add */
- if (!(tempbx & (SwitchToCRT2 | SetSimuScanMode))) { /* for driver abnormal */
+ /* for driver abnormal */
+ if (!(tempbx & (SwitchToCRT2 | SetSimuScanMode))) {
if (pVBInfo->IF_DEF_CRT2Monitor == 1) {
if (tempbx & SetCRT2ToRAMDAC) {
- tempbx &= (0xFF00 | SetCRT2ToRAMDAC
- | SwitchToCRT2
- | SetSimuScanMode);
+ tempbx &= (0xFF00 |
+ SetCRT2ToRAMDAC |
+ SwitchToCRT2 |
+ SetSimuScanMode);
tempbx &= (0x00FF | (~SetCRT2ToYPbPr));
}
} else {
- tempbx &= (~(SetCRT2ToRAMDAC | SetCRT2ToLCD
- | SetCRT2ToTV));
+ tempbx &= (~(SetCRT2ToRAMDAC |
+ SetCRT2ToLCD |
+ SetCRT2ToTV));
}
}
if (!(pVBInfo->VBType & VB_NoLCD)) {
if (tempbx & SetCRT2ToLCD) {
- tempbx &= (0xFF00 | SetCRT2ToLCD | SwitchToCRT2
- | SetSimuScanMode);
+ tempbx &= (0xFF00 |
+ SetCRT2ToLCD |
+ SwitchToCRT2 |
+ SetSimuScanMode);
tempbx &= (0x00FF | (~SetCRT2ToYPbPr));
}
}
if (tempbx & SetCRT2ToSCART) {
- tempbx &= (0xFF00 | SetCRT2ToSCART | SwitchToCRT2
- | SetSimuScanMode);
+ tempbx &= (0xFF00 |
+ SetCRT2ToSCART |
+ SwitchToCRT2 |
+ SetSimuScanMode);
tempbx &= (0x00FF | (~SetCRT2ToYPbPr));
}
if (pVBInfo->IF_DEF_YPbPr == 1) {
if (tempbx & SetCRT2ToYPbPr)
- tempbx &= (0xFF00 | SwitchToCRT2
- | SetSimuScanMode);
+ tempbx &= (0xFF00 |
+ SwitchToCRT2 |
+ SetSimuScanMode);
}
if (pVBInfo->IF_DEF_HiVision == 1) {
if (tempbx & SetCRT2ToHiVisionTV)
- tempbx &= (0xFF00 | SetCRT2ToHiVisionTV
- | SwitchToCRT2
- | SetSimuScanMode);
+ tempbx &= (0xFF00 |
+ SetCRT2ToHiVisionTV |
+ SwitchToCRT2 |
+ SetSimuScanMode);
}
if (tempax & DisableCRT2Display) { /* Set Display Device Info */
@@ -3611,38 +3783,35 @@
}
if (!(tempbx & DisableCRT2Display)) {
- if ((!(tempbx & DriverMode))
- || (!(modeflag & CRT2Mode))) {
+ if ((!(tempbx & DriverMode)) ||
+ (!(modeflag & CRT2Mode))) {
if (pVBInfo->IF_DEF_LCDA == 1) {
if (!(tempbx & SetCRT2ToLCDA))
- tempbx
- |= (SetInSlaveMode
- | SetSimuScanMode);
+ tempbx |= (SetInSlaveMode |
+ SetSimuScanMode);
}
if (pVBInfo->IF_DEF_VideoCapture == 1) {
- if (((HwDeviceExtension->jChipType
- == XG40)
- && (pVBInfo->Set_VGAType
- == XG40))
- || ((HwDeviceExtension->jChipType
- == XG41)
- && (pVBInfo->Set_VGAType
- == XG41))
- || ((HwDeviceExtension->jChipType
- == XG42)
- && (pVBInfo->Set_VGAType
- == XG42))
- || ((HwDeviceExtension->jChipType
- == XG45)
- && (pVBInfo->Set_VGAType
- == XG45))) {
+ if (((HwDeviceExtension->jChipType ==
+ XG40) &&
+ (pVBInfo->Set_VGAType == XG40)) ||
+ ((HwDeviceExtension->jChipType ==
+ XG41) &&
+ (pVBInfo->Set_VGAType == XG41)) ||
+ ((HwDeviceExtension->jChipType ==
+ XG42) &&
+ (pVBInfo->Set_VGAType == XG42)) ||
+ ((HwDeviceExtension->jChipType ==
+ XG45) &&
+ (pVBInfo->Set_VGAType == XG45))) {
if (ModeNo <= 13) {
- if (!(tempbx
- & SetCRT2ToRAMDAC)) { /*CRT2 not need to support*/
- tempbx
- &= (0x00FF
- | (~SetInSlaveMode));
+ if (!(tempbx &
+ SetCRT2ToRAMDAC)) {
+ /*CRT2 not need
+ * to support*/
+ tempbx &=
+ (0x00FF |
+ (~SetInSlaveMode));
pVBInfo->SetFlag
|= EnableVCMode;
}
@@ -3651,11 +3820,13 @@
}
}
- /* LCD+TV can't support in slave mode (Force LCDA+TV->LCDB) */
- if ((tempbx & SetInSlaveMode) && (tempbx
- & SetCRT2ToLCDA)) {
- tempbx ^= (SetCRT2ToLCD | SetCRT2ToLCDA
- | SetCRT2ToDualEdge);
+ /* LCD+TV can't support in slave mode
+ * (Force LCDA+TV->LCDB) */
+ if ((tempbx & SetInSlaveMode) &&
+ (tempbx & SetCRT2ToLCDA)) {
+ tempbx ^= (SetCRT2ToLCD |
+ SetCRT2ToLCDA |
+ SetCRT2ToDualEdge);
pVBInfo->SetFlag |= ReserveTVOption;
}
}
@@ -3674,33 +3845,40 @@
if (pVBInfo->VBInfo & SetCRT2ToTV) {
if (ModeNo <= 0x13) {
- modeflag
- = pVBInfo->SModeIDTable[ModeIdIndex].St_ModeFlag; /* si+St_ModeFlag */
- resinfo = pVBInfo->SModeIDTable[ModeIdIndex].St_ResInfo; /* si+St_ResInfo */
+ modeflag = pVBInfo->SModeIDTable[ModeIdIndex].
+ St_ModeFlag; /* si+St_ModeFlag */
+ resinfo = pVBInfo->SModeIDTable[ModeIdIndex].
+ St_ResInfo; /* si+St_ResInfo */
} else {
- modeflag
- = pVBInfo->EModeIDTable[ModeIdIndex].Ext_ModeFlag;
- resinfo
- = pVBInfo->EModeIDTable[ModeIdIndex].Ext_RESINFO; /* si+Ext_ResInfo */
+ modeflag = pVBInfo->EModeIDTable[ModeIdIndex].
+ Ext_ModeFlag;
+ resinfo = pVBInfo->EModeIDTable[ModeIdIndex].
+ Ext_RESINFO; /* si+Ext_ResInfo */
}
if (pVBInfo->VBInfo & SetCRT2ToTV) {
temp = xgifb_reg_get(pVBInfo->P3d4, 0x35);
tempbx = temp;
if (tempbx & SetPALTV) {
- tempbx &= (SetCHTVOverScan | SetPALMTV
- | SetPALNTV | SetPALTV);
+ tempbx &= (SetCHTVOverScan |
+ SetPALMTV |
+ SetPALNTV |
+ SetPALTV);
if (tempbx & SetPALMTV)
- tempbx &= ~SetPALTV; /* set to NTSC if PAL-M */
+ /* set to NTSC if PAL-M */
+ tempbx &= ~SetPALTV;
} else
- tempbx &= (SetCHTVOverScan | SetNTSCJ
- | SetPALTV);
+ tempbx &= (SetCHTVOverScan |
+ SetNTSCJ |
+ SetPALTV);
/*
if (pVBInfo->IF_DEF_LVDS == 0) {
- index1 = xgifb_reg_get(pVBInfo->P3d4, 0x38); //PAL-M/PAL-N Info
- temp2 = (index1 & 0xC0) >> 5; //00:PAL, 01:PAL-M, 10:PAL-N
+ //PAL-M/PAL-N Info
+ index1 = xgifb_reg_get(pVBInfo->P3d4, 0x38);
+ //00:PAL, 01:PAL-M, 10:PAL-N
+ temp2 = (index1 & 0xC0) >> 5;
tempbx |= temp2;
- if (temp2 & 0x02) //PAL-M
+ if (temp2 & 0x02) //PAL-M
tempbx &= (~SetPALTV);
}
*/
@@ -3746,12 +3924,13 @@
}
if (pVBInfo->IF_DEF_LVDS == 0) { /* shampoo */
- if ((pVBInfo->VBInfo & SetInSlaveMode)
- && (!(pVBInfo->VBInfo & SetNotSimuMode)))
+ if ((pVBInfo->VBInfo & SetInSlaveMode) &&
+ (!(pVBInfo->VBInfo & SetNotSimuMode)))
tempbx |= TVSimuMode;
- if (!(tempbx & SetPALTV) && (modeflag > 13) && (resinfo
- == 8)) /* NTSC 1024x768, */
+ if (!(tempbx & SetPALTV) &&
+ (modeflag > 13) &&
+ (resinfo == 8)) /* NTSC 1024x768, */
tempbx |= NTSC1024x768;
tempbx |= RPLLDIV2XO;
@@ -3760,12 +3939,15 @@
if (pVBInfo->VBInfo & SetInSlaveMode)
tempbx &= (~RPLLDIV2XO);
} else {
- if (tempbx & (SetYPbPrMode525p
- | SetYPbPrMode750p))
+ if (tempbx &
+ (SetYPbPrMode525p | SetYPbPrMode750p))
tempbx &= (~RPLLDIV2XO);
- else if (!(pVBInfo->VBType & (VB_XGI301B
- | VB_XGI302B | VB_XGI301LV
- | VB_XGI302LV | VB_XGI301C))) {
+ else if (!(pVBInfo->VBType &
+ (VB_XGI301B |
+ VB_XGI302B |
+ VB_XGI301LV |
+ VB_XGI302LV |
+ VB_XGI301C))) {
if (tempbx & TVSimuMode)
tempbx &= (~RPLLDIV2XO);
}
@@ -3785,10 +3967,12 @@
pVBInfo->LCDInfo = 0;
if (ModeNo <= 0x13) {
- modeflag = pVBInfo->SModeIDTable[ModeIdIndex].St_ModeFlag; /* si+St_ModeFlag // */
+ /* si+St_ModeFlag // */
+ modeflag = pVBInfo->SModeIDTable[ModeIdIndex].St_ModeFlag;
} else {
modeflag = pVBInfo->EModeIDTable[ModeIdIndex].Ext_ModeFlag;
- resinfo = pVBInfo->EModeIDTable[ModeIdIndex].Ext_RESINFO; /* si+Ext_ResInfo // */
+ /* si+Ext_ResInfo // */
+ resinfo = pVBInfo->EModeIDTable[ModeIdIndex].Ext_RESINFO;
}
temp = xgifb_reg_get(pVBInfo->P3d4, 0x36); /* Get LCD Res.Info */
@@ -3857,7 +4041,8 @@
if ((pVBInfo->LCDResInfo == Panel1400x1050) && (pVBInfo->VBInfo
& SetCRT2ToLCD) && (ModeNo > 0x13) && (resinfo
== 9) && (!(tempbx & EnableScalingLCD)))
- tempbx |= SetLCDtoNonExpanding; /* set to center in 1280x1024 LCDB for Panel1400x1050 */
+ /* set to center in 1280x1024 LCDB for Panel1400x1050 */
+ tempbx |= SetLCDtoNonExpanding;
}
/*
@@ -3875,7 +4060,7 @@
if (ModeNo > 0x13) {
if (pVBInfo->LCDResInfo
== Panel1024x768) {
- if (resinfo == 4) { /* 512x384 */
+ if (resinfo == 4) {/* 512x384 */
tempbx |= EnableLVDSDDA;
}
}
@@ -3895,8 +4080,8 @@
if (pVBInfo->IF_DEF_PWD == 1) {
if (pVBInfo->LCDInfo & SetPWDEnable) {
- if ((pVBInfo->VBType & VB_XGI302LV) || (pVBInfo->VBType
- & VB_XGI301C)) {
+ if ((pVBInfo->VBType & VB_XGI302LV) ||
+ (pVBInfo->VBType & VB_XGI301C)) {
if (!(tempax & PWDEnable))
pVBInfo->LCDInfo &= ~SetPWDEnable;
}
@@ -3908,13 +4093,13 @@
if (pVBInfo->VBInfo & SetInSlaveMode) {
if (!(tempax & LockLCDBToA)) {
if (ModeNo <= 0x13) {
- pVBInfo->VBInfo
- &= ~(SetSimuScanMode
- | SetInSlaveMode
- | SetCRT2ToLCD);
- pVBInfo->VBInfo
- |= SetCRT2ToLCDA
- | SetCRT2ToDualEdge;
+ pVBInfo->VBInfo &=
+ ~(SetSimuScanMode |
+ SetInSlaveMode |
+ SetCRT2ToLCD);
+ pVBInfo->VBInfo |=
+ SetCRT2ToLCDA |
+ SetCRT2ToDualEdge;
}
}
}
@@ -3925,9 +4110,15 @@
if (pVBInfo->IF_DEF_LVDS == 0) {
if (tempax & (LockLCDBToA | StLCDBToA)) {
if (pVBInfo->VBInfo & SetInSlaveMode) {
- if (!((!(tempax & LockLCDBToA)) && (ModeNo > 0x13))) {
- pVBInfo->VBInfo&=~(SetSimuScanMode|SetInSlaveMode|SetCRT2ToLCD);
- pVBInfo->VBInfo|=SetCRT2ToLCDA|SetCRT2ToDualEdge;
+ if (!((!(tempax & LockLCDBToA)) &&
+ (ModeNo > 0x13))) {
+ pVBInfo->VBInfo &=
+ ~(SetSimuScanMode |
+ SetInSlaveMode |
+ SetCRT2ToLCD);
+ pVBInfo->VBInfo |=
+ SetCRT2ToLCDA |
+ SetCRT2ToDualEdge;
}
}
}
@@ -3943,11 +4134,16 @@
if (ModeNo <= 5)
ModeNo |= 1;
if (ModeNo <= 0x13) {
- /* for (*ModeIdIndex=0; *ModeIdIndex < sizeof(pVBInfo->SModeIDTable) / sizeof(struct XGI_StStruct); (*ModeIdIndex)++) */
+ /* for (*ModeIdIndex=0;
+ *ModeIdIndex < sizeof(pVBInfo->SModeIDTable)
+ / sizeof(struct XGI_StStruct);
+ (*ModeIdIndex)++) */
for (*ModeIdIndex = 0;; (*ModeIdIndex)++) {
- if (pVBInfo->SModeIDTable[*ModeIdIndex].St_ModeID == ModeNo)
+ if (pVBInfo->SModeIDTable[*ModeIdIndex].St_ModeID ==
+ ModeNo)
break;
- if (pVBInfo->SModeIDTable[*ModeIdIndex].St_ModeID == 0xFF)
+ if (pVBInfo->SModeIDTable[*ModeIdIndex].St_ModeID ==
+ 0xFF)
return 0;
}
@@ -3957,11 +4153,16 @@
(*ModeIdIndex) += 2; /* 400 lines */
/* else 350 lines */
} else {
- /* for (*ModeIdIndex=0; *ModeIdIndex < sizeof(pVBInfo->EModeIDTable) / sizeof(struct XGI_ExtStruct); (*ModeIdIndex)++) */
+ /* for (*ModeIdIndex=0;
+ *ModeIdIndex < sizeof(pVBInfo->EModeIDTable)
+ / sizeof(struct XGI_ExtStruct);
+ (*ModeIdIndex)++) */
for (*ModeIdIndex = 0;; (*ModeIdIndex)++) {
- if (pVBInfo->EModeIDTable[*ModeIdIndex].Ext_ModeID == ModeNo)
+ if (pVBInfo->EModeIDTable[*ModeIdIndex].Ext_ModeID ==
+ ModeNo)
break;
- if (pVBInfo->EModeIDTable[*ModeIdIndex].Ext_ModeID == 0xFF)
+ if (pVBInfo->EModeIDTable[*ModeIdIndex].Ext_ModeID ==
+ 0xFF)
return 0;
}
}
@@ -4002,19 +4203,22 @@
tmp = temp;
if (HwDeviceExtension->jChipType == XG40) {
- temp = 1 << ((temp & 0x0F0) >> 4); /* memory size per channel SR14[7:4] */
+ /* memory size per channel SR14[7:4] */
+ temp = 1 << ((temp & 0x0F0) >> 4);
if ((tmp & 0x0c) == 0x0C) { /* Qual channels */
temp <<= 2;
} else if ((tmp & 0x0c) == 0x08) { /* Dual channels */
temp <<= 1;
}
} else if (HwDeviceExtension->jChipType == XG42) {
- temp = 1 << ((temp & 0x0F0) >> 4); /* memory size per channel SR14[7:4] */
+ /* memory size per channel SR14[7:4] */
+ temp = 1 << ((temp & 0x0F0) >> 4);
if ((tmp & 0x04) == 0x04) { /* Dual channels */
temp <<= 1;
}
} else if (HwDeviceExtension->jChipType == XG45) {
- temp = 1 << ((temp & 0x0F0) >> 4); /* memory size per channel SR14[7:4] */
+ /* memory size per channel SR14[7:4] */
+ temp = 1 << ((temp & 0x0F0) >> 4);
if ((tmp & 0x0c) == 0x0C) { /* Qual channels */
temp <<= 2;
} else if ((tmp & 0x0c) == 0x08) { /* triple channels */
@@ -4033,7 +4237,13 @@
#endif
/*
-void XGINew_IsLowResolution(unsigned short ModeNo, unsigned short ModeIdIndex, unsigned char XGINew_CheckMemorySize(struct xgi_hw_device_info *HwDeviceExtension, unsigned short ModeNo, unsigned short ModeIdIndex, struct vb_device_info *pVBInfo)
+void XGINew_IsLowResolution(unsigned short ModeNo,
+ unsigned short ModeIdIndex,
+ unsigned char XGINew_CheckMemorySize(
+ struct xgi_hw_device_info *HwDeviceExtension,
+ unsigned short ModeNo,
+ unsigned short ModeIdIndex,
+ struct vb_device_info *pVBInfo)
{
unsigned short data ;
unsigned short ModeFlag ;
@@ -4122,35 +4332,43 @@
if (pXGIHWDE->jChipType == XG21) {
if (pVBInfo->IF_DEF_LVDS == 1) {
if (!(XGI_XG21GetPSCValue(pVBInfo) & 0x1)) {
- XGI_XG21BLSignalVDD(0x01, 0x01, pVBInfo); /* LVDS VDD on */
+ /* LVDS VDD on */
+ XGI_XG21BLSignalVDD(0x01, 0x01, pVBInfo);
XGI_XG21SetPanelDelay(2, pVBInfo);
}
if (!(XGI_XG21GetPSCValue(pVBInfo) & 0x20))
- XGI_XG21BLSignalVDD(0x20, 0x20, pVBInfo); /* LVDS signal on */
+ /* LVDS signal on */
+ XGI_XG21BLSignalVDD(0x20, 0x20, pVBInfo);
XGI_XG21SetPanelDelay(3, pVBInfo);
- XGI_XG21BLSignalVDD(0x02, 0x02, pVBInfo); /* LVDS backlight on */
+ /* LVDS backlight on */
+ XGI_XG21BLSignalVDD(0x02, 0x02, pVBInfo);
} else {
- XGI_XG21BLSignalVDD(0x20, 0x20, pVBInfo); /* DVO/DVI signal on */
+ /* DVO/DVI signal on */
+ XGI_XG21BLSignalVDD(0x20, 0x20, pVBInfo);
}
}
- if (pVBInfo->IF_DEF_CH7007 == 1) { /* [Billy] 07/05/23 For CH7007 */
-
+ /* [Billy] 07/05/23 For CH7007 */
+ if (pVBInfo->IF_DEF_CH7007 == 1) {
}
if (pXGIHWDE->jChipType == XG27) {
if (pVBInfo->IF_DEF_LVDS == 1) {
if (!(XGI_XG27GetPSCValue(pVBInfo) & 0x1)) {
- XGI_XG27BLSignalVDD(0x01, 0x01, pVBInfo); /* LVDS VDD on */
+ /* LVDS VDD on */
+ XGI_XG27BLSignalVDD(0x01, 0x01, pVBInfo);
XGI_XG21SetPanelDelay(2, pVBInfo);
}
if (!(XGI_XG27GetPSCValue(pVBInfo) & 0x20))
- XGI_XG27BLSignalVDD(0x20, 0x20, pVBInfo); /* LVDS signal on */
+ /* LVDS signal on */
+ XGI_XG27BLSignalVDD(0x20, 0x20, pVBInfo);
XGI_XG21SetPanelDelay(3, pVBInfo);
- XGI_XG27BLSignalVDD(0x02, 0x02, pVBInfo); /* LVDS backlight on */
+ /* LVDS backlight on */
+ XGI_XG27BLSignalVDD(0x02, 0x02, pVBInfo);
} else {
- XGI_XG27BLSignalVDD(0x20, 0x20, pVBInfo); /* DVO/DVI signal on */
+ /* DVO/DVI signal on */
+ XGI_XG27BLSignalVDD(0x20, 0x20, pVBInfo);
}
}
@@ -4162,10 +4380,12 @@
if (pXGIHWDE->jChipType == XG21) {
if (pVBInfo->IF_DEF_LVDS == 1) {
- XGI_XG21BLSignalVDD(0x02, 0x00, pVBInfo); /* LVDS backlight off */
+ /* LVDS backlight off */
+ XGI_XG21BLSignalVDD(0x02, 0x00, pVBInfo);
XGI_XG21SetPanelDelay(3, pVBInfo);
} else {
- XGI_XG21BLSignalVDD(0x20, 0x00, pVBInfo); /* DVO/DVI signal off */
+ /* DVO/DVI signal off */
+ XGI_XG21BLSignalVDD(0x20, 0x00, pVBInfo);
}
}
@@ -4177,12 +4397,14 @@
if (pXGIHWDE->jChipType == XG27) {
if ((XGI_XG27GetPSCValue(pVBInfo) & 0x2)) {
- XGI_XG27BLSignalVDD(0x02, 0x00, pVBInfo); /* LVDS backlight off */
+ /* LVDS backlight off */
+ XGI_XG27BLSignalVDD(0x02, 0x00, pVBInfo);
XGI_XG21SetPanelDelay(3, pVBInfo);
}
if (pVBInfo->IF_DEF_LVDS == 0)
- XGI_XG27BLSignalVDD(0x20, 0x00, pVBInfo); /* DVO/DVI signal off */
+ /* DVO/DVI signal off */
+ XGI_XG27BLSignalVDD(0x20, 0x00, pVBInfo);
}
xgifb_reg_and_or(pVBInfo->P3c4, 0x01, 0xDF, 0x20);
@@ -4200,8 +4422,10 @@
#if 0
static void XGI_WaitDisplay(struct vb_device_info *pVBInfo)
{
- while (!(inb(pVBInfo->P3da) & 0x01));
- while (inb(pVBInfo->P3da) & 0x01);
+ while (!(inb(pVBInfo->P3da) & 0x01))
+ ;
+ while (inb(pVBInfo->P3da) & 0x01)
+ ;
}
#endif
@@ -4211,18 +4435,21 @@
xgifb_reg_or(pVBInfo->Part1Port, 0x01, 0x40);
}
-static void XGI_SaveCRT2Info(unsigned short ModeNo, struct vb_device_info *pVBInfo)
+static void XGI_SaveCRT2Info(unsigned short ModeNo,
+ struct vb_device_info *pVBInfo)
{
unsigned short temp1, temp2;
- xgifb_reg_set(pVBInfo->P3d4, 0x34, ModeNo); /* reserve CR34 for CRT1 Mode No */
+ /* reserve CR34 for CRT1 Mode No */
+ xgifb_reg_set(pVBInfo->P3d4, 0x34, ModeNo);
temp1 = (pVBInfo->VBInfo & SetInSlaveMode) >> 8;
temp2 = ~(SetInSlaveMode >> 8);
xgifb_reg_and_or(pVBInfo->P3d4, 0x31, temp2, temp1);
}
-static void XGI_GetCRT2ResInfo(unsigned short ModeNo, unsigned short ModeIdIndex,
- struct vb_device_info *pVBInfo)
+static void XGI_GetCRT2ResInfo(unsigned short ModeNo,
+ unsigned short ModeIdIndex,
+ struct vb_device_info *pVBInfo)
{
unsigned short xres, yres, modeflag, resindex;
@@ -4230,11 +4457,13 @@
if (ModeNo <= 0x13) {
xres = pVBInfo->StResInfo[resindex].HTotal;
yres = pVBInfo->StResInfo[resindex].VTotal;
- /* modeflag = pVBInfo->SModeIDTable[ModeIdIndex].St_ModeFlag; si+St_ResInfo */
+ /* si+St_ResInfo */
+ /* modeflag = pVBInfo->SModeIDTable[ModeIdIndex].St_ModeFlag;*/
} else {
xres = pVBInfo->ModeResInfo[resindex].HTotal; /* xres->ax */
yres = pVBInfo->ModeResInfo[resindex].VTotal; /* yres->bx */
- modeflag = pVBInfo->EModeIDTable[ModeIdIndex].Ext_ModeFlag; /* si+St_ModeFlag */
+ /* si+St_ModeFlag */
+ modeflag = pVBInfo->EModeIDTable[ModeIdIndex].Ext_ModeFlag;
/*
if (pVBInfo->IF_DEF_FSTN) {
@@ -4306,9 +4535,10 @@
return 0;
}
-static void XGI_GetRAMDAC2DATA(unsigned short ModeNo, unsigned short ModeIdIndex,
- unsigned short RefreshRateTableIndex,
- struct vb_device_info *pVBInfo)
+static void XGI_GetRAMDAC2DATA(unsigned short ModeNo,
+ unsigned short ModeIdIndex,
+ unsigned short RefreshRateTableIndex,
+ struct vb_device_info *pVBInfo)
{
unsigned short tempax, tempbx, temp1, temp2, modeflag = 0, tempcx,
StandTableIndex, CRT1Index;
@@ -4324,24 +4554,23 @@
temp1 = pVBInfo->StandTable[StandTableIndex].CRTC[7];
} else {
modeflag = pVBInfo->EModeIDTable[ModeIdIndex].Ext_ModeFlag;
- CRT1Index
- = pVBInfo->RefIndex[RefreshRateTableIndex].Ext_CRT1CRTC;
+ CRT1Index = pVBInfo->RefIndex[RefreshRateTableIndex].
+ Ext_CRT1CRTC;
CRT1Index &= IndexMask;
- temp1
- = (unsigned short) pVBInfo->XGINEWUB_CRT1Table[CRT1Index].CR[0];
- temp2
- = (unsigned short) pVBInfo->XGINEWUB_CRT1Table[CRT1Index].CR[5];
+ temp1 = (unsigned short) pVBInfo->
+ XGINEWUB_CRT1Table[CRT1Index].CR[0];
+ temp2 = (unsigned short) pVBInfo->
+ XGINEWUB_CRT1Table[CRT1Index].CR[5];
tempax = (temp1 & 0xFF) | ((temp2 & 0x03) << 8);
- tempbx
- = (unsigned short) pVBInfo->XGINEWUB_CRT1Table[CRT1Index].CR[8];
- tempcx
- = (unsigned short) pVBInfo->XGINEWUB_CRT1Table[CRT1Index].CR[14]
- << 8;
+ tempbx = (unsigned short) pVBInfo->
+ XGINEWUB_CRT1Table[CRT1Index].CR[8];
+ tempcx = (unsigned short) pVBInfo->
+ XGINEWUB_CRT1Table[CRT1Index].CR[14] << 8;
tempcx &= 0x0100;
tempcx = tempcx << 2;
tempbx |= tempcx;
- temp1
- = (unsigned short) pVBInfo->XGINEWUB_CRT1Table[CRT1Index].CR[9];
+ temp1 = (unsigned short) pVBInfo->
+ XGINEWUB_CRT1Table[CRT1Index].CR[9];
}
if (temp1 & 0x01)
@@ -4373,10 +4602,12 @@
struct XGI_TVDataStruct *TVPtr = NULL;
if (ModeNo <= 0x13) {
- modeflag = pVBInfo->SModeIDTable[ModeIdIndex].St_ModeFlag; /* si+St_ResInfo */
+ /* si+St_ResInfo */
+ modeflag = pVBInfo->SModeIDTable[ModeIdIndex].St_ModeFlag;
resinfo = pVBInfo->SModeIDTable[ModeIdIndex].St_ResInfo;
} else {
- modeflag = pVBInfo->EModeIDTable[ModeIdIndex].Ext_ModeFlag; /* si+Ext_ResInfo */
+ /* si+Ext_ResInfo */
+ modeflag = pVBInfo->EModeIDTable[ModeIdIndex].Ext_ModeFlag;
resinfo = pVBInfo->EModeIDTable[ModeIdIndex].Ext_RESINFO;
}
@@ -4598,7 +4829,8 @@
return ColorDepth[index];
}
-static unsigned short XGI_GetOffset(unsigned short ModeNo, unsigned short ModeIdIndex,
+static unsigned short XGI_GetOffset(unsigned short ModeNo,
+ unsigned short ModeIdIndex,
unsigned short RefreshRateTableIndex,
struct xgi_hw_device_info *HwDeviceExtension,
struct vb_device_info *pVBInfo)
@@ -4610,7 +4842,8 @@
if (ModeNo <= 0x14)
infoflag = 0;
else
- infoflag = pVBInfo->RefIndex[RefreshRateTableIndex].Ext_InfoFlag;
+ infoflag = pVBInfo->
+ RefIndex[RefreshRateTableIndex].Ext_InfoFlag;
index = (modeinfo >> 8) & 0xFF;
@@ -4657,8 +4890,10 @@
static void XGI_SetCRT2FIFO(struct vb_device_info *pVBInfo)
{
- xgifb_reg_set(pVBInfo->Part1Port, 0x01, 0x3B); /* threshold high ,disable auto threshold */
- xgifb_reg_and_or(pVBInfo->Part1Port, 0x02, ~(0x3F), 0x04); /* threshold low default 04h */
+ /* threshold high ,disable auto threshold */
+ xgifb_reg_set(pVBInfo->Part1Port, 0x01, 0x3B);
+ /* threshold low default 04h */
+ xgifb_reg_and_or(pVBInfo->Part1Port, 0x02, ~(0x3F), 0x04);
}
static void XGI_PreSetGroup1(unsigned short ModeNo, unsigned short ModeIdIndex,
@@ -4669,7 +4904,8 @@
unsigned short tempcx = 0, CRT1Index = 0, resinfo = 0;
if (ModeNo > 0x13) {
- CRT1Index = pVBInfo->RefIndex[RefreshRateTableIndex].Ext_CRT1CRTC;
+ CRT1Index = pVBInfo->
+ RefIndex[RefreshRateTableIndex].Ext_CRT1CRTC;
CRT1Index &= IndexMask;
resinfo = pVBInfo->EModeIDTable[ModeIdIndex].Ext_RESINFO;
}
@@ -4695,7 +4931,8 @@
pushbx = 0, CRT1Index = 0, modeflag, resinfo = 0;
if (ModeNo > 0x13) {
- CRT1Index = pVBInfo->RefIndex[RefreshRateTableIndex].Ext_CRT1CRTC;
+ CRT1Index = pVBInfo->
+ RefIndex[RefreshRateTableIndex].Ext_CRT1CRTC;
CRT1Index &= IndexMask;
resinfo = pVBInfo->EModeIDTable[ModeIdIndex].Ext_RESINFO;
}
@@ -4707,11 +4944,13 @@
/* bainy change table name */
if (modeflag & HalfDCLK) {
- temp = (pVBInfo->VGAHT / 2 - 1) & 0x0FF; /* BTVGA2HT 0x08,0x09 */
+ /* BTVGA2HT 0x08,0x09 */
+ temp = (pVBInfo->VGAHT / 2 - 1) & 0x0FF;
xgifb_reg_set(pVBInfo->Part1Port, 0x08, temp);
temp = (((pVBInfo->VGAHT / 2 - 1) & 0xFF00) >> 8) << 4;
xgifb_reg_and_or(pVBInfo->Part1Port, 0x09, ~0x0F0, temp);
- temp = (pVBInfo->VGAHDE / 2 + 16) & 0x0FF; /* BTVGA2HDEE 0x0A,0x0C */
+ /* BTVGA2HDEE 0x0A,0x0C */
+ temp = (pVBInfo->VGAHDE / 2 + 16) & 0x0FF;
xgifb_reg_set(pVBInfo->Part1Port, 0x0A, temp);
tempcx = ((pVBInfo->VGAHT - pVBInfo->VGAHDE) / 2) >> 2;
pushbx = pVBInfo->VGAHDE / 2 + 16;
@@ -4721,8 +4960,9 @@
if (pVBInfo->VBInfo & SetCRT2ToRAMDAC) {
tempbx = pVBInfo->XGINEWUB_CRT1Table[CRT1Index].CR[4];
- tempbx |= ((pVBInfo->XGINEWUB_CRT1Table[CRT1Index].CR[14]
- & 0xC0) << 2);
+ tempbx |= ((pVBInfo->
+ XGINEWUB_CRT1Table[CRT1Index].CR[14] &
+ 0xC0) << 2);
tempbx = (tempbx - 3) << 3; /* (VGAHRS-3)*8 */
tempcx = pVBInfo->XGINEWUB_CRT1Table[CRT1Index].CR[5];
tempcx &= 0x1F;
@@ -4745,7 +4985,8 @@
xgifb_reg_set(pVBInfo->Part1Port, 0x08, temp);
temp = (((pVBInfo->VGAHT - 1) & 0xFF00) >> 8) << 4;
xgifb_reg_and_or(pVBInfo->Part1Port, 0x09, ~0x0F0, temp);
- temp = (pVBInfo->VGAHDE + 16) & 0x0FF; /* BTVGA2HDEE 0x0A,0x0C */
+ /* BTVGA2HDEE 0x0A,0x0C */
+ temp = (pVBInfo->VGAHDE + 16) & 0x0FF;
xgifb_reg_set(pVBInfo->Part1Port, 0x0A, temp);
tempcx = (pVBInfo->VGAHT - pVBInfo->VGAHDE) >> 2; /* cx */
pushbx = pVBInfo->VGAHDE + 16;
@@ -4755,8 +4996,9 @@
if (pVBInfo->VBInfo & SetCRT2ToRAMDAC) {
tempbx = pVBInfo->XGINEWUB_CRT1Table[CRT1Index].CR[3];
- tempbx |= ((pVBInfo->XGINEWUB_CRT1Table[CRT1Index].CR[5]
- & 0xC0) << 2);
+ tempbx |= ((pVBInfo->
+ XGINEWUB_CRT1Table[CRT1Index].CR[5] &
+ 0xC0) << 2);
tempbx = (tempbx - 3) << 3; /* (VGAHRS-3)*8 */
tempcx = pVBInfo->XGINEWUB_CRT1Table[CRT1Index].CR[4];
tempcx &= 0x1F;
@@ -4801,8 +5043,10 @@
tempax = pVBInfo->VGAVDE;
tempbx = pVBInfo->VGAVDE;
tempcx = pVBInfo->VGAVT;
- tempbx = (pVBInfo->VGAVT + pVBInfo->VGAVDE) >> 1; /* BTVGA2VRS 0x10,0x11 */
- tempcx = ((pVBInfo->VGAVT - pVBInfo->VGAVDE) >> 4) + tempbx + 1; /* BTVGA2VRE 0x11 */
+ /* BTVGA2VRS 0x10,0x11 */
+ tempbx = (pVBInfo->VGAVT + pVBInfo->VGAVDE) >> 1;
+ /* BTVGA2VRE 0x11 */
+ tempcx = ((pVBInfo->VGAVT - pVBInfo->VGAVDE) >> 4) + tempbx + 1;
if (pVBInfo->VBInfo & SetCRT2ToRAMDAC) {
tempbx = pVBInfo->XGINEWUB_CRT1Table[CRT1Index].CR[10];
@@ -4860,12 +5104,15 @@
modeflag, CRT1Index;
if (ModeNo <= 0x13) {
- modeflag = pVBInfo->SModeIDTable[ModeIdIndex].St_ModeFlag; /* si+St_ResInfo */
+ /* si+St_ResInfo */
+ modeflag = pVBInfo->SModeIDTable[ModeIdIndex].St_ModeFlag;
resinfo = pVBInfo->SModeIDTable[ModeIdIndex].St_ResInfo;
} else {
- modeflag = pVBInfo->EModeIDTable[ModeIdIndex].Ext_ModeFlag; /* si+Ext_ResInfo */
+ /* si+Ext_ResInfo */
+ modeflag = pVBInfo->EModeIDTable[ModeIdIndex].Ext_ModeFlag;
resinfo = pVBInfo->EModeIDTable[ModeIdIndex].Ext_RESINFO;
- CRT1Index = pVBInfo->RefIndex[RefreshRateTableIndex].Ext_CRT1CRTC;
+ CRT1Index = pVBInfo->
+ RefIndex[RefreshRateTableIndex].Ext_CRT1CRTC;
CRT1Index &= IndexMask;
}
@@ -4911,8 +5158,10 @@
}
}
- xgifb_reg_set(pVBInfo->Part1Port, 0x05, temp); /* 0x05 Horizontal Display Start */
- xgifb_reg_set(pVBInfo->Part1Port, 0x06, 0x03); /* 0x06 Horizontal Blank end */
+ /* 0x05 Horizontal Display Start */
+ xgifb_reg_set(pVBInfo->Part1Port, 0x05, temp);
+ /* 0x06 Horizontal Blank end */
+ xgifb_reg_set(pVBInfo->Part1Port, 0x06, 0x03);
if (!(pVBInfo->VBInfo & DisableCRT2Display)) { /* 030226 bainy */
if (pVBInfo->VBInfo & SetCRT2ToTV)
@@ -4960,15 +5209,14 @@
if (pVBInfo->LCDResInfo != Panel1280x960) {
if (pVBInfo->VGAHDE >= 800) {
temp -= 7;
- if (pVBInfo->ModeType
- == ModeEGA) {
- if (pVBInfo->VGAVDE
- == 1024) {
+ if (pVBInfo->ModeType ==
+ ModeEGA) {
+ if (pVBInfo->VGAVDE ==
+ 1024) {
temp += 15;
- if (pVBInfo->LCDResInfo
- != Panel1280x1024) {
- temp
- += 7;
+ if (pVBInfo->LCDResInfo != Panel1280x1024) {
+ temp +=
+ 7;
}
}
}
@@ -4989,8 +5237,10 @@
}
}
- xgifb_reg_set(pVBInfo->Part1Port, 0x07, temp); /* 0x07 Horizontal Retrace Start */
- xgifb_reg_set(pVBInfo->Part1Port, 0x08, 0); /* 0x08 Horizontal Retrace End */
+ /* 0x07 Horizontal Retrace Start */
+ xgifb_reg_set(pVBInfo->Part1Port, 0x07, temp);
+ /* 0x08 Horizontal Retrace End */
+ xgifb_reg_set(pVBInfo->Part1Port, 0x08, 0);
if (pVBInfo->VBInfo & SetCRT2ToTV) {
if (pVBInfo->TVInfo & TVSimuMode) {
@@ -5087,7 +5337,8 @@
temp = tempbx & 0x00FF;
tempbx--;
temp = tempbx & 0x00FF;
- xgifb_reg_set(pVBInfo->Part1Port, 0x10, temp); /* 0x10 vertical Blank Start */
+ /* 0x10 vertical Blank Start */
+ xgifb_reg_set(pVBInfo->Part1Port, 0x10, temp);
tempbx = push2;
tempbx--;
temp = tempbx & 0x00FF;
@@ -5110,7 +5361,8 @@
if (tempbx & 0x0400)
tempcx |= 0x0600;
- xgifb_reg_set(pVBInfo->Part1Port, 0x11, 0x00); /* 0x11 Vertival Blank End */
+ /* 0x11 Vertival Blank End */
+ xgifb_reg_set(pVBInfo->Part1Port, 0x11, 0x00);
tempax = push1;
tempax -= tempbx; /* 0x0C Vertical Retrace Start */
@@ -5129,12 +5381,12 @@
} else {
if (pVBInfo->TVInfo & TVSimuMode) {
if (pVBInfo->TVInfo & SetPALTV) {
- if (pVBInfo->VBType
- & VB_XGI301LV) {
- if (!(pVBInfo->TVInfo
- & (SetYPbPrMode525p
- | SetYPbPrMode750p
- | SetYPbPrMode1080i)))
+ if (pVBInfo->VBType &
+ VB_XGI301LV) {
+ if (!(pVBInfo->TVInfo &
+ (SetYPbPrMode525p |
+ SetYPbPrMode750p |
+ SetYPbPrMode1080i)))
tempbx += 40;
} else {
tempbx += 40;
@@ -5149,10 +5401,10 @@
if (pVBInfo->TVInfo & TVSimuMode) {
if (pVBInfo->TVInfo & SetPALTV) {
if (pVBInfo->VBType & VB_XGI301LV) {
- if (!(pVBInfo->TVInfo
- & (SetYPbPrMode525p
- | SetYPbPrMode750p
- | SetYPbPrMode1080i)))
+ if (!(pVBInfo->TVInfo &
+ (SetYPbPrMode525p |
+ SetYPbPrMode750p |
+ SetYPbPrMode1080i)))
tempbx += 40;
} else {
tempbx += 40;
@@ -5199,7 +5451,8 @@
tempbx = push1; /* pop ax */
temp = tempbx & 0x00FF;
temp &= 0x0F;
- xgifb_reg_set(pVBInfo->Part1Port, 0x0D, temp); /* 0x0D vertical Retrace End */
+ /* 0x0D vertical Retrace End */
+ xgifb_reg_set(pVBInfo->Part1Port, 0x0D, temp);
if (tempbx & 0x0010)
tempcx |= 0x2000;
@@ -5242,14 +5495,16 @@
unsigned long longtemp, tempeax, tempebx, temp2, tempecx;
if (ModeNo <= 0x13) {
- modeflag = pVBInfo->SModeIDTable[ModeIdIndex].St_ModeFlag; /* si+St_ResInfo */
+ /* si+St_ResInfo */
+ modeflag = pVBInfo->SModeIDTable[ModeIdIndex].St_ModeFlag;
resinfo = pVBInfo->SModeIDTable[ModeIdIndex].St_ResInfo;
crt2crtc = pVBInfo->SModeIDTable[ModeIdIndex].St_CRT2CRTC;
} else {
- modeflag = pVBInfo->EModeIDTable[ModeIdIndex].Ext_ModeFlag; /* si+Ext_ResInfo */
+ /* si+Ext_ResInfo */
+ modeflag = pVBInfo->EModeIDTable[ModeIdIndex].Ext_ModeFlag;
resinfo = pVBInfo->EModeIDTable[ModeIdIndex].Ext_RESINFO;
- crt2crtc
- = pVBInfo->RefIndex[RefreshRateTableIndex].Ext_CRT2CRTC;
+ crt2crtc = pVBInfo->RefIndex[RefreshRateTableIndex].
+ Ext_CRT2CRTC;
}
tempax = 0;
@@ -5308,7 +5563,8 @@
xgifb_reg_set(pVBInfo->Part2Port, i, TimingPoint[j]);
for (i = 0x39; i <= 0x45; i++, j++)
- xgifb_reg_set(pVBInfo->Part2Port, i, TimingPoint[j]); /* di->temp2[j] */
+ /* di->temp2[j] */
+ xgifb_reg_set(pVBInfo->Part2Port, i, TimingPoint[j]);
if (pVBInfo->VBInfo & SetCRT2ToTV)
xgifb_reg_and_or(pVBInfo->Part2Port, 0x3A, 0x1F, 0x00);
@@ -5453,9 +5709,10 @@
tempbx = 853;
if (pVBInfo->VBInfo & SetCRT2ToTV) {
- if (pVBInfo->VBType & (VB_XGI301LV | VB_XGI302LV | VB_XGI301C)) {
- if (!(pVBInfo->TVInfo & (SetYPbPrMode525p
- | SetYPbPrMode750p)))
+ if (pVBInfo->VBType &
+ (VB_XGI301LV | VB_XGI302LV | VB_XGI301C)) {
+ if (!(pVBInfo->TVInfo &
+ (SetYPbPrMode525p | SetYPbPrMode750p)))
tempbx = tempbx >> 1;
} else
tempbx = tempbx >> 1;
@@ -5688,13 +5945,15 @@
struct XGI_LCDDesStruct *LCDBDesPtr = NULL;
if (ModeNo <= 0x13) {
- modeflag = pVBInfo->SModeIDTable[ModeIdIndex].St_ModeFlag; /* si+St_ResInfo */
+ /* si+St_ResInfo */
+ modeflag = pVBInfo->SModeIDTable[ModeIdIndex].St_ModeFlag;
resinfo = pVBInfo->SModeIDTable[ModeIdIndex].St_ResInfo;
} else {
- modeflag = pVBInfo->EModeIDTable[ModeIdIndex].Ext_ModeFlag; /* si+Ext_ResInfo */
+ /* si+Ext_ResInfo */
+ modeflag = pVBInfo->EModeIDTable[ModeIdIndex].Ext_ModeFlag;
resinfo = pVBInfo->EModeIDTable[ModeIdIndex].Ext_RESINFO;
- CRT1Index
- = pVBInfo->RefIndex[RefreshRateTableIndex].Ext_CRT1CRTC;
+ CRT1Index = pVBInfo->RefIndex[RefreshRateTableIndex].
+ Ext_CRT1CRTC;
CRT1Index &= IndexMask;
}
@@ -5755,7 +6014,8 @@
if ((tempah == Panel1024x768) || (tempah == Panel1024x768x75)) {
tempbx = 1024;
tempcx = 768;
- } else if ((tempah == Panel1280x1024) || (tempah == Panel1280x1024x75)) {
+ } else if ((tempah == Panel1280x1024) ||
+ (tempah == Panel1280x1024x75)) {
tempbx = 1280;
tempcx = 1024;
} else if (tempah == Panel1400x1050) {
@@ -5965,16 +6225,23 @@
for (i = 0x80, j = 0; i <= 0xBF; i++, j++)
xgifb_reg_set(pVBInfo->Part2Port, i, Tap4TimingPtr->Reg[j]);
- if ((pVBInfo->VBInfo & SetCRT2ToTV) && (!(pVBInfo->VBInfo & SetCRT2ToHiVisionTV))) {
- Tap4TimingPtr = XGI_GetTap4Ptr(1, pVBInfo); /* Set Vertical Scaling */
+ if ((pVBInfo->VBInfo & SetCRT2ToTV) &&
+ (!(pVBInfo->VBInfo & SetCRT2ToHiVisionTV))) {
+ /* Set Vertical Scaling */
+ Tap4TimingPtr = XGI_GetTap4Ptr(1, pVBInfo);
for (i = 0xC0, j = 0; i < 0xFF; i++, j++)
- xgifb_reg_set(pVBInfo->Part2Port, i, Tap4TimingPtr->Reg[j]);
+ xgifb_reg_set(pVBInfo->Part2Port,
+ i,
+ Tap4TimingPtr->Reg[j]);
}
- if ((pVBInfo->VBInfo & SetCRT2ToTV) && (!(pVBInfo->VBInfo & SetCRT2ToHiVisionTV)))
- xgifb_reg_and_or(pVBInfo->Part2Port, 0x4E, ~0x14, 0x04); /* Enable V.Scaling */
+ if ((pVBInfo->VBInfo & SetCRT2ToTV) &&
+ (!(pVBInfo->VBInfo & SetCRT2ToHiVisionTV)))
+ /* Enable V.Scaling */
+ xgifb_reg_and_or(pVBInfo->Part2Port, 0x4E, ~0x14, 0x04);
else
- xgifb_reg_and_or(pVBInfo->Part2Port, 0x4E, ~0x14, 0x10); /* Enable H.Scaling */
+ /* Enable H.Scaling */
+ xgifb_reg_and_or(pVBInfo->Part2Port, 0x4E, ~0x14, 0x10);
#endif
}
@@ -5986,9 +6253,11 @@
unsigned short modeflag;
if (ModeNo <= 0x13)
- modeflag = pVBInfo->SModeIDTable[ModeIdIndex].St_ModeFlag; /* si+St_ResInfo */
+ /* si+St_ResInfo */
+ modeflag = pVBInfo->SModeIDTable[ModeIdIndex].St_ModeFlag;
else
- modeflag = pVBInfo->EModeIDTable[ModeIdIndex].Ext_ModeFlag; /* si+Ext_ResInfo */
+ /* si+Ext_ResInfo */
+ modeflag = pVBInfo->EModeIDTable[ModeIdIndex].Ext_ModeFlag;
xgifb_reg_set(pVBInfo->Part3Port, 0x00, 0x00);
if (pVBInfo->TVInfo & SetPALTV) {
@@ -6047,9 +6316,11 @@
unsigned long tempebx, tempeax, templong;
if (ModeNo <= 0x13)
- modeflag = pVBInfo->SModeIDTable[ModeIdIndex].St_ModeFlag; /* si+St_ResInfo */
+ /* si+St_ResInfo */
+ modeflag = pVBInfo->SModeIDTable[ModeIdIndex].St_ModeFlag;
else
- modeflag = pVBInfo->EModeIDTable[ModeIdIndex].Ext_ModeFlag; /* si+Ext_ResInfo */
+ /* si+Ext_ResInfo */
+ modeflag = pVBInfo->EModeIDTable[ModeIdIndex].Ext_ModeFlag;
temp = pVBInfo->RVBHCFACT;
xgifb_reg_set(pVBInfo->Part4Port, 0x13, temp);
@@ -6162,7 +6433,9 @@
if (XGI_IsLCDDualLink(pVBInfo))
tempax = tempax >> 1;
- /* if((pVBInfo->VBInfo&(SetCRT2ToLCD))||((pVBInfo->TVInfo&SetYPbPrMode525p)||(pVBInfo->TVInfo&SetYPbPrMode750p))) { */
+ /* if((pVBInfo->VBInfo&(SetCRT2ToLCD)) ||
+ ((pVBInfo->TVInfo&SetYPbPrMode525p) ||
+ (pVBInfo->TVInfo&SetYPbPrMode750p))) { */
if (pVBInfo->VBInfo & SetCRT2ToLCD) {
if (tempax > 800)
tempax -= 800;
@@ -6179,12 +6452,17 @@
/*
if (pVBInfo->VBInfo & (SetCRT2ToTV | SetCRT2ToHiVisionTV)) {
if (pVBInfo->VBType & VB_XGI301LV) {
- if (!(pVBInfo->TVInfo & (SetYPbPrMode525p | SetYPbPrMode750p | SetYPbPrMode1080i))) {
+ if (!(pVBInfo->TVInfo &
+ (SetYPbPrMode525p |
+ SetYPbPrMode750p |
+ SetYPbPrMode1080i))) {
if (pVBInfo->VGAHDE > 800) {
if (pVBInfo->VGAHDE == 1024)
- tempax = (tempax * 25 / 32) - 1;
+ tempax =(tempax * 25 /
+ 32) - 1;
else
- tempax = (tempax * 20 / 32) - 1;
+ tempax = (tempax * 20 /
+ 32) - 1;
}
}
} else {
@@ -6297,7 +6575,8 @@
if (tempbh & 0x20) {
temp = (tempbl >> 4) & 0x02;
- xgifb_reg_and_or(pVBInfo->P3d4, 0xB4, ~0x02, temp); /* CR B4[1] */
+ /* CR B4[1] */
+ xgifb_reg_and_or(pVBInfo->P3d4, 0xB4, ~0x02, temp);
}
@@ -6325,7 +6604,8 @@
if (tempbh & 0x20) {
temp = (tempbl >> 4) & 0x02;
- xgifb_reg_and_or(pVBInfo->P3d4, 0xB4, ~0x02, temp); /* CR B4[1] */
+ /* CR B4[1] */
+ xgifb_reg_and_or(pVBInfo->P3d4, 0xB4, ~0x02, temp);
}
xgifb_reg_and_or(pVBInfo->P3d4, 0xB4, ~tempbh0, tempbl0);
@@ -6390,11 +6670,13 @@
if (ModeNo <= 0x13) {
xres = pVBInfo->StResInfo[resindex].HTotal;
yres = pVBInfo->StResInfo[resindex].VTotal;
- modeflag = pVBInfo->SModeIDTable[ModeIdIndex].St_ModeFlag; /* si+St_ResInfo */
+ /* si+St_ResInfo */
+ modeflag = pVBInfo->SModeIDTable[ModeIdIndex].St_ModeFlag;
} else {
xres = pVBInfo->ModeResInfo[resindex].HTotal; /* xres->ax */
yres = pVBInfo->ModeResInfo[resindex].VTotal; /* yres->bx */
- modeflag = pVBInfo->EModeIDTable[ModeIdIndex].Ext_ModeFlag; /* si+St_ModeFlag */
+ /* si+St_ModeFlag */
+ modeflag = pVBInfo->EModeIDTable[ModeIdIndex].Ext_ModeFlag;
}
if (!(modeflag & Charx8Dot)) {
@@ -6419,12 +6701,13 @@
return 0;
if (ModeNo > 0x13) {
- if ((xres
- != (pVBInfo->XG21_LVDSCapList[lvdstableindex].LVDSHDE))
- || (yres
- != (pVBInfo->XG21_LVDSCapList[lvdstableindex].LVDSVDE))) {
- colordepth = XGI_GetColorDepth(ModeNo, ModeIdIndex,
- pVBInfo);
+ if ((xres != (pVBInfo->XG21_LVDSCapList[lvdstableindex].
+ LVDSHDE)) ||
+ (yres != (pVBInfo->XG21_LVDSCapList[lvdstableindex].
+ LVDSVDE))) {
+ colordepth = XGI_GetColorDepth(ModeNo,
+ ModeIdIndex,
+ pVBInfo);
if (colordepth > 2)
return 0;
@@ -6439,8 +6722,10 @@
temp = xgifb_reg_get(pVBInfo->P3d4, 0x37); /* D[0] 1: 18bit */
temp = (temp & 1) << 6;
- xgifb_reg_and_or(pVBInfo->P3c4, 0x06, ~0x40, temp); /* SR06[6] 18bit Dither */
- xgifb_reg_and_or(pVBInfo->P3c4, 0x09, ~0xc0, temp | 0x80); /* SR09[7] enable FP output, SR09[6] 1: sigle 18bits, 0: dual 12bits */
+ /* SR06[6] 18bit Dither */
+ xgifb_reg_and_or(pVBInfo->P3c4, 0x06, ~0x40, temp);
+ /* SR09[7] enable FP output, SR09[6] 1: sigle 18bits, 0: dual 12bits */
+ xgifb_reg_and_or(pVBInfo->P3c4, 0x09, ~0xc0, temp | 0x80);
}
@@ -6448,15 +6733,19 @@
{
unsigned char temp;
- temp = xgifb_reg_get(pVBInfo->P3d4, 0x37); /* D[1:0] 01: 18bit, 00: dual 12, 10: single 24 */
+ /* D[1:0] 01: 18bit, 00: dual 12, 10: single 24 */
+ temp = xgifb_reg_get(pVBInfo->P3d4, 0x37);
temp = (temp & 3) << 6;
- xgifb_reg_and_or(pVBInfo->P3c4, 0x06, ~0xc0, temp & 0x80); /* SR06[7]0: dual 12/1: single 24 [6] 18bit Dither <= 0 h/w recommend */
- xgifb_reg_and_or(pVBInfo->P3c4, 0x09, ~0xc0, temp | 0x80); /* SR09[7] enable FP output, SR09[6] 1: sigle 18bits, 0: 24bits */
+ /* SR06[7]0: dual 12/1: single 24 [6] 18bit Dither <= 0 h/w recommend */
+ xgifb_reg_and_or(pVBInfo->P3c4, 0x06, ~0xc0, temp & 0x80);
+ /* SR09[7] enable FP output, SR09[6] 1: sigle 18bits, 0: 24bits */
+ xgifb_reg_and_or(pVBInfo->P3c4, 0x09, ~0xc0, temp | 0x80);
}
-static void XGI_SetXG21LVDSPara(unsigned short ModeNo, unsigned short ModeIdIndex,
- struct vb_device_info *pVBInfo)
+static void XGI_SetXG21LVDSPara(unsigned short ModeNo,
+ unsigned short ModeIdIndex,
+ struct vb_device_info *pVBInfo)
{
unsigned char temp, Miscdata;
unsigned short xres, yres, modeflag, resindex, lvdstableindex;
@@ -6466,28 +6755,33 @@
lvdstableindex = XGI_GetLVDSOEMTableIndex(pVBInfo);
- temp = (unsigned char) ((pVBInfo->XG21_LVDSCapList[lvdstableindex].LVDS_Capability
- & (LCDPolarity << 8)) >> 8);
+ temp = (unsigned char) ((pVBInfo->XG21_LVDSCapList[lvdstableindex].
+ LVDS_Capability &
+ (LCDPolarity << 8)) >> 8);
temp &= LCDPolarity;
Miscdata = (unsigned char) inb(pVBInfo->P3cc);
outb((Miscdata & 0x3F) | temp, pVBInfo->P3c2);
- temp = (unsigned char) (pVBInfo->XG21_LVDSCapList[lvdstableindex].LVDS_Capability
- & LCDPolarity);
- xgifb_reg_and_or(pVBInfo->P3c4, 0x35, ~0x80, temp & 0x80); /* SR35[7] FP VSync polarity */
- xgifb_reg_and_or(pVBInfo->P3c4, 0x30, ~0x20, (temp & 0x40) >> 1); /* SR30[5] FP HSync polarity */
+ temp = (unsigned char) (pVBInfo->XG21_LVDSCapList[lvdstableindex].
+ LVDS_Capability & LCDPolarity);
+ /* SR35[7] FP VSync polarity */
+ xgifb_reg_and_or(pVBInfo->P3c4, 0x35, ~0x80, temp & 0x80);
+ /* SR30[5] FP HSync polarity */
+ xgifb_reg_and_or(pVBInfo->P3c4, 0x30, ~0x20, (temp & 0x40) >> 1);
XGI_SetXG21FPBits(pVBInfo);
resindex = XGI_GetResInfo(ModeNo, ModeIdIndex, pVBInfo);
if (ModeNo <= 0x13) {
xres = pVBInfo->StResInfo[resindex].HTotal;
yres = pVBInfo->StResInfo[resindex].VTotal;
- modeflag = pVBInfo->SModeIDTable[ModeIdIndex].St_ModeFlag; /* si+St_ResInfo */
+ /* si+St_ResInfo */
+ modeflag = pVBInfo->SModeIDTable[ModeIdIndex].St_ModeFlag;
} else {
xres = pVBInfo->ModeResInfo[resindex].HTotal; /* xres->ax */
yres = pVBInfo->ModeResInfo[resindex].VTotal; /* yres->bx */
- modeflag = pVBInfo->EModeIDTable[ModeIdIndex].Ext_ModeFlag; /* si+St_ModeFlag */
+ /* si+St_ModeFlag */
+ modeflag = pVBInfo->EModeIDTable[ModeIdIndex].Ext_ModeFlag;
}
if (!(modeflag & Charx8Dot))
@@ -6619,18 +6913,21 @@
xgifb_reg_and_or(pVBInfo->P3c4, 0x31, ~0x30, value);
xgifb_reg_set(pVBInfo->P3c4,
- 0x2B,
- pVBInfo->XG21_LVDSCapList[lvdstableindex].VCLKData1);
+ 0x2B,
+ pVBInfo->XG21_LVDSCapList[lvdstableindex].
+ VCLKData1);
xgifb_reg_set(pVBInfo->P3c4,
- 0x2C,
- pVBInfo->XG21_LVDSCapList[lvdstableindex].VCLKData2);
+ 0x2C,
+ pVBInfo->XG21_LVDSCapList[lvdstableindex].
+ VCLKData2);
value += 0x10;
}
if (!(modeflag & Charx8Dot)) {
inb(pVBInfo->P3da); /* reset 3da */
outb(0x13, pVBInfo->P3c0); /* set index */
- outb(0x00, pVBInfo->P3c0); /* set data, panning = 0, shift left 1 dot*/
+ /* set data, panning = 0, shift left 1 dot*/
+ outb(0x00, pVBInfo->P3c0);
inb(pVBInfo->P3da); /* Enable Attribute */
outb(0x20, pVBInfo->P3c0);
@@ -6641,8 +6938,9 @@
}
/* no shadow case */
-static void XGI_SetXG27LVDSPara(unsigned short ModeNo, unsigned short ModeIdIndex,
- struct vb_device_info *pVBInfo)
+static void XGI_SetXG27LVDSPara(unsigned short ModeNo,
+ unsigned short ModeIdIndex,
+ struct vb_device_info *pVBInfo)
{
unsigned char temp, Miscdata;
unsigned short xres, yres, modeflag, resindex, lvdstableindex;
@@ -6651,28 +6949,33 @@
unsigned short value;
lvdstableindex = XGI_GetLVDSOEMTableIndex(pVBInfo);
- temp = (unsigned char) ((pVBInfo->XG21_LVDSCapList[lvdstableindex].LVDS_Capability
- & (LCDPolarity << 8)) >> 8);
+ temp = (unsigned char) ((pVBInfo->XG21_LVDSCapList[lvdstableindex].
+ LVDS_Capability &
+ (LCDPolarity << 8)) >> 8);
temp &= LCDPolarity;
Miscdata = (unsigned char) inb(pVBInfo->P3cc);
outb((Miscdata & 0x3F) | temp, pVBInfo->P3c2);
- temp = (unsigned char) (pVBInfo->XG21_LVDSCapList[lvdstableindex].LVDS_Capability
- & LCDPolarity);
- xgifb_reg_and_or(pVBInfo->P3c4, 0x35, ~0x80, temp & 0x80); /* SR35[7] FP VSync polarity */
- xgifb_reg_and_or(pVBInfo->P3c4, 0x30, ~0x20, (temp & 0x40) >> 1); /* SR30[5] FP HSync polarity */
+ temp = (unsigned char) (pVBInfo->XG21_LVDSCapList[lvdstableindex].
+ LVDS_Capability & LCDPolarity);
+ /* SR35[7] FP VSync polarity */
+ xgifb_reg_and_or(pVBInfo->P3c4, 0x35, ~0x80, temp & 0x80);
+ /* SR30[5] FP HSync polarity */
+ xgifb_reg_and_or(pVBInfo->P3c4, 0x30, ~0x20, (temp & 0x40) >> 1);
XGI_SetXG27FPBits(pVBInfo);
resindex = XGI_GetResInfo(ModeNo, ModeIdIndex, pVBInfo);
if (ModeNo <= 0x13) {
xres = pVBInfo->StResInfo[resindex].HTotal;
yres = pVBInfo->StResInfo[resindex].VTotal;
- modeflag = pVBInfo->SModeIDTable[ModeIdIndex].St_ModeFlag; /* si+St_ResInfo */
+ /* si+St_ResInfo */
+ modeflag = pVBInfo->SModeIDTable[ModeIdIndex].St_ModeFlag;
} else {
xres = pVBInfo->ModeResInfo[resindex].HTotal; /* xres->ax */
yres = pVBInfo->ModeResInfo[resindex].VTotal; /* yres->bx */
- modeflag = pVBInfo->EModeIDTable[ModeIdIndex].Ext_ModeFlag; /* si+St_ModeFlag */
+ /* si+St_ModeFlag */
+ modeflag = pVBInfo->EModeIDTable[ModeIdIndex].Ext_ModeFlag;
}
if (!(modeflag & Charx8Dot))
@@ -6713,7 +7016,8 @@
if (LVDSVRS > LVDSVT)
LVDSVRS -= LVDSVT;
- LVDSVRE = LVDSVRS + pVBInfo->XG21_LVDSCapList[lvdstableindex].LVDSVSYNC;
+ LVDSVRE = LVDSVRS + pVBInfo->XG21_LVDSCapList[lvdstableindex].
+ LVDSVSYNC;
if (LVDSVRE > LVDSVT)
LVDSVRE -= LVDSVT;
@@ -6803,18 +7107,21 @@
xgifb_reg_and_or(pVBInfo->P3c4, 0x31, ~0x30, value);
xgifb_reg_set(pVBInfo->P3c4,
- 0x2B,
- pVBInfo->XG21_LVDSCapList[lvdstableindex].VCLKData1);
+ 0x2B,
+ pVBInfo->XG21_LVDSCapList[lvdstableindex].
+ VCLKData1);
xgifb_reg_set(pVBInfo->P3c4,
- 0x2C,
- pVBInfo->XG21_LVDSCapList[lvdstableindex].VCLKData2);
+ 0x2C,
+ pVBInfo->XG21_LVDSCapList[lvdstableindex].
+ VCLKData2);
value += 0x10;
}
if (!(modeflag & Charx8Dot)) {
inb(pVBInfo->P3da); /* reset 3da */
outb(0x13, pVBInfo->P3c0); /* set index */
- outb(0x00, pVBInfo->P3c0); /* set data, panning = 0, shift left 1 dot*/
+ /* set data, panning = 0, shift left 1 dot*/
+ outb(0x00, pVBInfo->P3c0);
inb(pVBInfo->P3da); /* Enable Attribute */
outb(0x20, pVBInfo->P3c0);
@@ -6908,14 +7215,19 @@
/*
if (CH7017) {
- if (!(pVBInfo->VBInfo & (SetCRT2ToLCD | SetCRT2toLCDA)) || (XGI_DisableChISLCD(pVBInfo))) {
+ if (!(pVBInfo->VBInfo &
+ (SetCRT2ToLCD | SetCRT2toLCDA)) ||
+ (XGI_DisableChISLCD(pVBInfo))) {
if (!XGI_IsLCDON(pVBInfo)) {
if (DISCHARGE) {
tempbx = XGINew_GetCH7005(0x61);
- if (tempbx < 0x01) // first time we power up
- XGINew_SetCH7005(0x0066); // and disable power sequence
+ // first time we power up
+ if (tempbx < 0x01)
+ // and disable power sequence
+ XGINew_SetCH7005(0x0066);
else
- XGINew_SetCH7005(0x5f66); // leave VDD on - disable power
+ // leave VDD on - disable power
+ XGINew_SetCH7005(0x5f66);
}
}
}
@@ -6925,29 +7237,35 @@
if (pVBInfo->VBType & (VB_XGI301B | VB_XGI302B | VB_XGI301LV
| VB_XGI302LV | VB_XGI301C)) {
tempah = 0x3F;
- if (!(pVBInfo->VBInfo & (DisableCRT2Display | SetSimuScanMode))) {
+ if (!(pVBInfo->VBInfo &
+ (DisableCRT2Display | SetSimuScanMode))) {
if (pVBInfo->VBInfo & SetCRT2ToLCDA) {
if (pVBInfo->VBInfo & SetCRT2ToDualEdge) {
tempah = 0x7F; /* Disable Channel A */
if (!(pVBInfo->VBInfo & SetCRT2ToLCDA))
- tempah = 0xBF; /* Disable Channel B */
+ /* Disable Channel B */
+ tempah = 0xBF;
if (pVBInfo->SetFlag & DisableChB)
- tempah &= 0xBF; /* force to disable Cahnnel */
+ /* force to disable Cahnnel */
+ tempah &= 0xBF;
if (pVBInfo->SetFlag & DisableChA)
- tempah &= 0x7F; /* Force to disable Channel B */
+ /* Force to disable Channel B */
+ tempah &= 0x7F;
}
}
}
- xgifb_reg_and(pVBInfo->Part4Port, 0x1F, tempah); /* disable part4_1f */
+ /* disable part4_1f */
+ xgifb_reg_and(pVBInfo->Part4Port, 0x1F, tempah);
if (pVBInfo->VBType & (VB_XGI302LV | VB_XGI301C)) {
if (((pVBInfo->VBInfo & (SetCRT2ToLCD | SetCRT2ToLCDA)))
|| (XGI_DisableChISLCD(pVBInfo))
|| (XGI_IsLCDON(pVBInfo)))
- xgifb_reg_or(pVBInfo->Part4Port, 0x30, 0x80); /* LVDS Driver power down */
+ /* LVDS Driver power down */
+ xgifb_reg_or(pVBInfo->Part4Port, 0x30, 0x80);
}
if ((pVBInfo->SetFlag & DisableChA) || (pVBInfo->VBInfo
@@ -6961,38 +7279,48 @@
if (pVBInfo->VBInfo & SetCRT2ToLCDA) {
if ((pVBInfo->SetFlag & DisableChA) || (pVBInfo->VBInfo
& SetCRT2ToLCDA))
- xgifb_reg_and(pVBInfo->Part1Port, 0x1e, 0xdf); /* Power down */
+ /* Power down */
+ xgifb_reg_and(pVBInfo->Part1Port, 0x1e, 0xdf);
}
- xgifb_reg_and(pVBInfo->P3c4, 0x32, 0xdf); /* disable TV as primary VGA swap */
+ /* disable TV as primary VGA swap */
+ xgifb_reg_and(pVBInfo->P3c4, 0x32, 0xdf);
if ((pVBInfo->VBInfo & (SetSimuScanMode | SetCRT2ToDualEdge)))
xgifb_reg_and(pVBInfo->Part2Port, 0x00, 0xdf);
- if ((pVBInfo->SetFlag & DisableChB) || (pVBInfo->VBInfo
- & (DisableCRT2Display | SetSimuScanMode))
- || ((!(pVBInfo->VBInfo & SetCRT2ToLCDA))
- && (pVBInfo->VBInfo
- & (SetCRT2ToRAMDAC
- | SetCRT2ToLCD
- | SetCRT2ToTV))))
- xgifb_reg_or(pVBInfo->Part1Port, 0x00, 0x80); /* BScreenOff=1 */
+ if ((pVBInfo->SetFlag & DisableChB) ||
+ (pVBInfo->VBInfo &
+ (DisableCRT2Display | SetSimuScanMode)) ||
+ ((!(pVBInfo->VBInfo & SetCRT2ToLCDA)) &&
+ (pVBInfo->VBInfo &
+ (SetCRT2ToRAMDAC | SetCRT2ToLCD | SetCRT2ToTV))))
+ /* BScreenOff=1 */
+ xgifb_reg_or(pVBInfo->Part1Port, 0x00, 0x80);
- if ((pVBInfo->SetFlag & DisableChB) || (pVBInfo->VBInfo
- & (DisableCRT2Display | SetSimuScanMode))
- || (!(pVBInfo->VBInfo & SetCRT2ToLCDA))
- || (pVBInfo->VBInfo & (SetCRT2ToRAMDAC
- | SetCRT2ToLCD | SetCRT2ToTV))) {
- tempah = xgifb_reg_get(pVBInfo->Part1Port, 0x00); /* save Part1 index 0 */
- xgifb_reg_or(pVBInfo->Part1Port, 0x00, 0x10); /* BTDAC = 1, avoid VB reset */
- xgifb_reg_and(pVBInfo->Part1Port, 0x1E, 0xDF); /* disable CRT2 */
- xgifb_reg_set(pVBInfo->Part1Port, 0x00, tempah); /* restore Part1 index 0 */
+ if ((pVBInfo->SetFlag & DisableChB) ||
+ (pVBInfo->VBInfo &
+ (DisableCRT2Display | SetSimuScanMode)) ||
+ (!(pVBInfo->VBInfo & SetCRT2ToLCDA)) ||
+ (pVBInfo->VBInfo &
+ (SetCRT2ToRAMDAC | SetCRT2ToLCD | SetCRT2ToTV))) {
+ /* save Part1 index 0 */
+ tempah = xgifb_reg_get(pVBInfo->Part1Port, 0x00);
+ /* BTDAC = 1, avoid VB reset */
+ xgifb_reg_or(pVBInfo->Part1Port, 0x00, 0x10);
+ /* disable CRT2 */
+ xgifb_reg_and(pVBInfo->Part1Port, 0x1E, 0xDF);
+ /* restore Part1 index 0 */
+ xgifb_reg_set(pVBInfo->Part1Port, 0x00, tempah);
}
} else { /* {301} */
if (pVBInfo->VBInfo & (SetCRT2ToLCD | SetCRT2ToTV)) {
- xgifb_reg_or(pVBInfo->Part1Port, 0x00, 0x80); /* BScreenOff=1 */
- xgifb_reg_and(pVBInfo->Part1Port, 0x1E, 0xDF); /* Disable CRT2 */
- xgifb_reg_and(pVBInfo->P3c4, 0x32, 0xDF); /* Disable TV asPrimary VGA swap */
+ /* BScreenOff=1 */
+ xgifb_reg_or(pVBInfo->Part1Port, 0x00, 0x80);
+ /* Disable CRT2 */
+ xgifb_reg_and(pVBInfo->Part1Port, 0x1E, 0xDF);
+ /* Disable TV asPrimary VGA swap */
+ xgifb_reg_and(pVBInfo->P3c4, 0x32, 0xDF);
}
if (pVBInfo->VBInfo & (DisableCRT2Display | SetCRT2ToLCDA
@@ -7116,12 +7444,19 @@
/*
if (pVBInfo->VBInfo & SetCRT2ToRAMDAC)
tempbl = CRT2Delay1; // Get CRT2 Delay
- if (pVBInfo->VBType & (VB_XGI301B | VB_XGI302B | VB_XGI301LV | VB_XGI302LV | VB_XGI301C))
+ if (pVBInfo->VBType &
+ (VB_XGI301B |
+ VB_XGI302B |
+ VB_XGI301LV |
+ VB_XGI302LV |
+ VB_XGI301C))
tempbl = CRT2Delay2;
*/
if (pVBInfo->VBInfo & (SetCRT2ToLCD | SetCRT2ToLCDA)) {
- index = XGI_GetLCDCapPtr(pVBInfo); /* Get LCD Delay */
- tempbh = pVBInfo->LCDCapList[index].LCD_DelayCompensation;
+ /* Get LCD Delay */
+ index = XGI_GetLCDCapPtr(pVBInfo);
+ tempbh = pVBInfo->LCDCapList[index].
+ LCD_DelayCompensation;
if (!(pVBInfo->VBInfo & SetCRT2ToLCDA))
tempbl = tempbh;
@@ -7147,9 +7482,10 @@
tempbl = 0;
tempbh = 0;
if (pVBInfo->VBInfo & SetCRT2ToLCD) {
- tempah
- = pVBInfo->LCDCapList[XGI_GetLCDCapPtr(
- pVBInfo)].LCD_DelayCompensation; /* / Get LCD Delay */
+ /* / Get LCD Delay */
+ tempah = pVBInfo->LCDCapList[
+ XGI_GetLCDCapPtr(pVBInfo)].
+ LCD_DelayCompensation;
tempah &= 0x0f;
tempah = tempah << 4;
xgifb_reg_and_or(pVBInfo->Part1Port, 0x2D, 0x0f,
@@ -7158,7 +7494,8 @@
}
}
-static void XGI_SetLCDCap_A(unsigned short tempcx, struct vb_device_info *pVBInfo)
+static void XGI_SetLCDCap_A(unsigned short tempcx,
+ struct vb_device_info *pVBInfo)
{
unsigned short temp;
@@ -7166,7 +7503,8 @@
if (temp & LCDRGB18Bit) {
xgifb_reg_and_or(pVBInfo->Part1Port, 0x19, 0x0F,
- (unsigned short) (0x20 | (tempcx & 0x00C0))); /* Enable Dither */
+ /* Enable Dither */
+ (unsigned short) (0x20 | (tempcx & 0x00C0)));
xgifb_reg_and_or(pVBInfo->Part1Port, 0x1A, 0x7F, 0x80);
} else {
xgifb_reg_and_or(pVBInfo->Part1Port, 0x19, 0x0F,
@@ -7176,10 +7514,17 @@
/*
if (tempcx & EnableLCD24bpp) { // 24bits
- xgifb_reg_and_or(pVBInfo->Part1Port, 0x19, 0x0F, (unsigned short)(0x30 | (tempcx&0x00C0)));
+ xgifb_reg_and_or(pVBInfo->Part1Port,
+ 0x19,
+ 0x0F,
+ (unsigned short)(0x30 | (tempcx&0x00C0)));
xgifb_reg_and_or(pVBInfo->Part1Port, 0x1A, 0x7F, 0x00);
} else {
- xgifb_reg_and_or(pVBInfo->Part1Port, 0x19, 0x0F, (unsigned short)(0x20 | (tempcx&0x00C0))); // Enable Dither
+ xgifb_reg_and_or(pVBInfo->Part1Port,
+ 0x19,
+ 0x0F,
+ // Enable Dither
+ (unsigned short)(0x20 | (tempcx&0x00C0)));
xgifb_reg_and_or(pVBInfo->Part1Port, 0x1A, 0x7F, 0x80);
}
*/
@@ -7191,7 +7536,8 @@
/* Output : */
/* Description : */
/* --------------------------------------------------------------------- */
-static void XGI_SetLCDCap_B(unsigned short tempcx, struct vb_device_info *pVBInfo)
+static void XGI_SetLCDCap_B(unsigned short tempcx,
+ struct vb_device_info *pVBInfo)
{
if (tempcx & EnableLCD24bpp) /* 24bits */
xgifb_reg_and_or(pVBInfo->Part2Port, 0x1A, 0xE0,
@@ -7209,7 +7555,8 @@
index = XGI_GetLCDCapPtr(pVBInfo);
- xgifb_reg_and(pVBInfo->Part4Port, 0x30, 0x8F); /* disable down spectrum D[4] */
+ /* disable down spectrum D[4] */
+ xgifb_reg_and(pVBInfo->Part4Port, 0x30, 0x8F);
XGI_LongWait(pVBInfo);
xgifb_reg_or(pVBInfo->Part4Port, 0x30, 0x20); /* reset spectrum */
XGI_LongWait(pVBInfo);
@@ -7232,9 +7579,14 @@
tempcx = pVBInfo->LCDCapList[XGI_GetLCDCapPtr(pVBInfo)].LCD_Capability;
- if (pVBInfo->VBType & (VB_XGI301B | VB_XGI302B | VB_XGI301LV
- | VB_XGI302LV | VB_XGI301C)) {
- if (pVBInfo->VBType & (VB_XGI301LV | VB_XGI302LV | VB_XGI301C)) { /* 301LV/302LV only */
+ if (pVBInfo->VBType &
+ (VB_XGI301B |
+ VB_XGI302B |
+ VB_XGI301LV |
+ VB_XGI302LV |
+ VB_XGI301C)) { /* 301LV/302LV only */
+ if (pVBInfo->VBType &
+ (VB_XGI301LV | VB_XGI302LV | VB_XGI301C)) {
/* Set 301LV Capability */
xgifb_reg_set(pVBInfo->Part4Port, 0x24,
(unsigned char) (tempcx & 0x1F));
@@ -7269,8 +7621,9 @@
/* Output : */
/* Description : Set TV Customized Param. */
/* --------------------------------------------------------------------- */
-static void XGI_SetAntiFlicker(unsigned short ModeNo, unsigned short ModeIdIndex,
- struct vb_device_info *pVBInfo)
+static void XGI_SetAntiFlicker(unsigned short ModeNo,
+ unsigned short ModeIdIndex,
+ struct vb_device_info *pVBInfo)
{
unsigned short tempbx, index;
@@ -7294,8 +7647,9 @@
xgifb_reg_and_or(pVBInfo->Part2Port, 0x0A, 0x8F, tempah);
}
-static void XGI_SetEdgeEnhance(unsigned short ModeNo, unsigned short ModeIdIndex,
- struct vb_device_info *pVBInfo)
+static void XGI_SetEdgeEnhance(unsigned short ModeNo,
+ unsigned short ModeIdIndex,
+ struct vb_device_info *pVBInfo)
{
unsigned short tempbx, index;
@@ -7388,10 +7742,11 @@
}
if (ModeNo <= 0x13)
- tempal = pVBInfo->SModeIDTable[ModeIdIndex].VB_StTVYFilterIndex;
+ tempal = pVBInfo->SModeIDTable[ModeIdIndex].
+ VB_StTVYFilterIndex;
else
- tempal
- = pVBInfo->EModeIDTable[ModeIdIndex].VB_ExtTVYFilterIndex;
+ tempal = pVBInfo->EModeIDTable[ModeIdIndex].
+ VB_ExtTVYFilterIndex;
if (tempcl == 0)
index = tempal * 4;
@@ -7424,8 +7779,9 @@
/* Output : */
/* Description : Customized Param. for 301 */
/* --------------------------------------------------------------------- */
-static void XGI_OEM310Setting(unsigned short ModeNo, unsigned short ModeIdIndex,
- struct vb_device_info *pVBInfo)
+static void XGI_OEM310Setting(unsigned short ModeNo,
+ unsigned short ModeIdIndex,
+ struct vb_device_info *pVBInfo)
{
if (pVBInfo->SetFlag & Win9xDOSMode)
return;
@@ -7462,7 +7818,8 @@
unsigned char tempah;
- /* xgifb_reg_set(pVBInfo->Part1Port, 0x03, 0x00); // fix write part1 index 0 BTDRAM bit Bug */
+ /* // fix write part1 index 0 BTDRAM bit Bug
+ * xgifb_reg_set(pVBInfo->Part1Port, 0x03, 0x00); */
tempah = 0;
if (!(pVBInfo->VBInfo & DisableCRT2Display)) {
tempah = xgifb_reg_get(pVBInfo->Part1Port, 0x00);
@@ -7476,7 +7833,8 @@
tempcl = pVBInfo->ModeType;
tempcl -= ModeVGA;
if (tempcl >= 0) {
- tempah = (0x008 >> tempcl); /* BT Color */
+ /* BT Color */
+ tempah = (0x008 >> tempcl);
if (tempah == 0)
tempah = 1;
tempah |= 0x040;
@@ -7525,8 +7883,8 @@
if (pVBInfo->VBInfo & (SetCRT2ToRAMDAC | SetCRT2ToTV
| SetCRT2ToLCD | SetCRT2ToLCDA)) {
- if ((pVBInfo->VBInfo & SetCRT2ToLCDA)
- && (!(pVBInfo->VBInfo & SetSimuScanMode))) {
+ if ((pVBInfo->VBInfo & SetCRT2ToLCDA) &&
+ (!(pVBInfo->VBInfo & SetSimuScanMode))) {
tempbl &= 0xf7;
tempah |= 0x01;
xgifb_reg_and_or(pVBInfo->Part1Port, 0x2e,
@@ -7537,23 +7895,26 @@
tempah |= 0x01;
}
- if (pVBInfo->VBInfo & (SetCRT2ToRAMDAC
- | SetCRT2ToTV | SetCRT2ToLCD)) {
+ if (pVBInfo->VBInfo &
+ (SetCRT2ToRAMDAC |
+ SetCRT2ToTV |
+ SetCRT2ToLCD)) {
tempbl &= 0xf8;
tempah = 0x01;
if (!(pVBInfo->VBInfo & SetInSlaveMode))
tempah |= 0x02;
- if (!(pVBInfo->VBInfo & SetCRT2ToRAMDAC)) {
+ if (!(pVBInfo->VBInfo &
+ SetCRT2ToRAMDAC)) {
tempah = tempah ^ 0x05;
- if (!(pVBInfo->VBInfo
- & SetCRT2ToLCD))
+ if (!(pVBInfo->VBInfo &
+ SetCRT2ToLCD))
tempah = tempah ^ 0x01;
}
- if (!(pVBInfo->VBInfo
- & SetCRT2ToDualEdge))
+ if (!(pVBInfo->VBInfo &
+ SetCRT2ToDualEdge))
tempah |= 0x08;
xgifb_reg_and_or(pVBInfo->Part1Port,
0x2e, tempbl, tempah);
@@ -7578,7 +7939,8 @@
tempah |= 0x080;
if (pVBInfo->VBInfo & SetCRT2ToTV) {
- /* if (!(pVBInfo->TVInfo & (SetYPbPrMode525p | SetYPbPrMode750p))) { */
+ /* if (!(pVBInfo->TVInfo &
+ (SetYPbPrMode525p | SetYPbPrMode750p))) { */
tempah |= 0x020;
if (ModeNo > 0x13) {
if (pVBInfo->VBInfo & DriverMode)
@@ -7594,7 +7956,9 @@
tempah |= 0x40;
if (pVBInfo->VBInfo & SetCRT2ToTV) {
- /* if ((!(pVBInfo->VBInfo & SetCRT2ToHiVisionTV)) && (!(pVBInfo->TVInfo & (SetYPbPrMode525p | SetYPbPrMode750p)))) { */
+ /* if ((!(pVBInfo->VBInfo & SetCRT2ToHiVisionTV)) &&
+ (!(pVBInfo->TVInfo &
+ (SetYPbPrMode525p | SetYPbPrMode750p)))) { */
if (pVBInfo->TVInfo & RPLLDIV2XO)
tempah |= 0x40;
/* } */
@@ -7805,13 +8169,12 @@
if (pVBInfo->VBType & (VB_XGI301B | VB_XGI302B
| VB_XGI301LV | VB_XGI302LV
| VB_XGI301C))
- temp
- = LCDARefreshIndex[pVBInfo->LCDResInfo
- & 0x0F]; /* 301b */
+ /* 301b */
+ temp = LCDARefreshIndex[
+ pVBInfo->LCDResInfo & 0x0F];
else
- temp
- = LCDRefreshIndex[pVBInfo->LCDResInfo
- & 0x0F];
+ temp = LCDRefreshIndex[
+ pVBInfo->LCDResInfo & 0x0F];
if (index > temp)
index = temp;
@@ -7825,35 +8188,34 @@
ModeNo = pVBInfo->RefIndex[RefreshRateTableIndex].ModeID;
if (pXGIHWDE->jChipType >= XG20) { /* for XG20, XG21, XG27 */
/*
- if (pVBInfo->RefIndex[RefreshRateTableIndex].Ext_InfoFlag & XG2xNotSupport) {
+ if (pVBInfo->RefIndex[RefreshRateTableIndex].Ext_InfoFlag &
+ XG2xNotSupport) {
index++;
}
*/
- if ((pVBInfo->RefIndex[RefreshRateTableIndex].XRes == 800)
- && (pVBInfo->RefIndex[RefreshRateTableIndex].YRes
- == 600)) {
+ if ((pVBInfo->RefIndex[RefreshRateTableIndex].XRes == 800) &&
+ (pVBInfo->RefIndex[RefreshRateTableIndex].YRes == 600)) {
index++;
}
- /* Alan 10/19/2007; do the similar adjustment like XGISearchCRT1Rate() */
- if ((pVBInfo->RefIndex[RefreshRateTableIndex].XRes == 1024)
- && (pVBInfo->RefIndex[RefreshRateTableIndex].YRes
- == 768)) {
+ /* Alan 10/19/2007;
+ * do the similar adjustment like XGISearchCRT1Rate() */
+ if ((pVBInfo->RefIndex[RefreshRateTableIndex].XRes == 1024) &&
+ (pVBInfo->RefIndex[RefreshRateTableIndex].YRes == 768)) {
index++;
}
- if ((pVBInfo->RefIndex[RefreshRateTableIndex].XRes == 1280)
- && (pVBInfo->RefIndex[RefreshRateTableIndex].YRes
- == 1024)) {
+ if ((pVBInfo->RefIndex[RefreshRateTableIndex].XRes == 1280) &&
+ (pVBInfo->RefIndex[RefreshRateTableIndex].YRes == 1024)) {
index++;
}
}
i = 0;
do {
- if (pVBInfo->RefIndex[RefreshRateTableIndex + i].ModeID
- != ModeNo)
+ if (pVBInfo->RefIndex[RefreshRateTableIndex + i].
+ ModeID != ModeNo)
break;
- temp
- = pVBInfo->RefIndex[RefreshRateTableIndex + i].Ext_InfoFlag;
+ temp = pVBInfo->RefIndex[RefreshRateTableIndex + i].
+ Ext_InfoFlag;
temp &= ModeInfoFlag;
if (temp < pVBInfo->ModeType)
break;
@@ -7863,9 +8225,8 @@
} while (index != 0xFFFF);
if (!(pVBInfo->VBInfo & SetCRT2ToRAMDAC)) {
if (pVBInfo->VBInfo & SetInSlaveMode) {
- temp
- = pVBInfo->RefIndex[RefreshRateTableIndex
- + i - 1].Ext_InfoFlag;
+ temp = pVBInfo->RefIndex[RefreshRateTableIndex + i - 1].
+ Ext_InfoFlag;
if (temp & InterlaceMode)
i++;
}
@@ -8055,11 +8416,14 @@
| VB_XGI302LV | VB_XGI301C)) {
if (!(pVBInfo->SetFlag & DisableChA)) {
if (pVBInfo->SetFlag & EnableChA) {
- xgifb_reg_set(pVBInfo->Part1Port, 0x1E, 0x20); /* Power on */
+ /* Power on */
+ xgifb_reg_set(pVBInfo->Part1Port, 0x1E, 0x20);
} else {
- if (pVBInfo->VBInfo & SetCRT2ToDualEdge) { /* SetCRT2ToLCDA ) */
+ /* SetCRT2ToLCDA ) */
+ if (pVBInfo->VBInfo & SetCRT2ToDualEdge) {
+ /* Power on */
xgifb_reg_set(pVBInfo->Part1Port,
- 0x1E, 0x20); /* Power on */
+ 0x1E, 0x20);
}
}
}
@@ -8072,7 +8436,8 @@
pVBInfo->P3c4, 0x32);
tempah &= 0xDF;
if (pVBInfo->VBInfo & SetInSlaveMode) {
- if (!(pVBInfo->VBInfo & SetCRT2ToRAMDAC))
+ if (!(pVBInfo->VBInfo &
+ SetCRT2ToRAMDAC))
tempah |= 0x20;
}
xgifb_reg_set(pVBInfo->P3c4, 0x32, tempah);
@@ -8082,10 +8447,11 @@
pVBInfo->Part1Port, 0x2E);
if (!(tempah & 0x80))
+ /* BVBDOENABLE = 1 */
xgifb_reg_or(pVBInfo->Part1Port,
- 0x2E, 0x80); /* BVBDOENABLE = 1 */
-
- xgifb_reg_and(pVBInfo->Part1Port, 0x00, 0x7F); /* BScreenOFF = 0 */
+ 0x2E, 0x80);
+ /* BScreenOFF = 0 */
+ xgifb_reg_and(pVBInfo->Part1Port, 0x00, 0x7F);
}
}
@@ -8095,15 +8461,17 @@
0x20); /* shampoo 0129 */
if (pVBInfo->VBType & (VB_XGI302LV | VB_XGI301C)) {
if (!XGI_DisableChISLCD(pVBInfo)) {
- if (XGI_EnableChISLCD(pVBInfo)
- || (pVBInfo->VBInfo
- & (SetCRT2ToLCD
- | SetCRT2ToLCDA)))
+ if (XGI_EnableChISLCD(pVBInfo) ||
+ (pVBInfo->VBInfo &
+ (SetCRT2ToLCD | SetCRT2ToLCDA)))
+ /* LVDS PLL power on */
xgifb_reg_and(
- pVBInfo->Part4Port,
- 0x2A, 0x7F); /* LVDS PLL power on */
+ pVBInfo->Part4Port,
+ 0x2A,
+ 0x7F);
}
- xgifb_reg_and(pVBInfo->Part4Port, 0x30, 0x7F); /* LVDS Driver power on */
+ /* LVDS Driver power on */
+ xgifb_reg_and(pVBInfo->Part4Port, 0x30, 0x7F);
}
}
@@ -8114,33 +8482,35 @@
if (!(pVBInfo->VBInfo & SetSimuScanMode)) {
if (pVBInfo->VBInfo & SetCRT2ToLCDA) {
- if (pVBInfo->VBInfo & SetCRT2ToDualEdge) {
+ if (pVBInfo->VBInfo &
+ SetCRT2ToDualEdge) {
tempah = tempah & 0x40;
- if (pVBInfo->VBInfo
- & SetCRT2ToLCDA)
+ if (pVBInfo->VBInfo &
+ SetCRT2ToLCDA)
tempah = tempah ^ 0xC0;
- if (pVBInfo->SetFlag
- & DisableChB)
+ if (pVBInfo->SetFlag &
+ DisableChB)
tempah &= 0xBF;
- if (pVBInfo->SetFlag
- & DisableChA)
+ if (pVBInfo->SetFlag &
+ DisableChA)
tempah &= 0x7F;
- if (pVBInfo->SetFlag
- & EnableChB)
+ if (pVBInfo->SetFlag &
+ EnableChB)
tempah |= 0x40;
- if (pVBInfo->SetFlag
- & EnableChA)
+ if (pVBInfo->SetFlag &
+ EnableChA)
tempah |= 0x80;
}
}
}
}
- xgifb_reg_or(pVBInfo->Part4Port, 0x1F, tempah); /* EnablePart4_1F */
+ /* EnablePart4_1F */
+ xgifb_reg_or(pVBInfo->Part4Port, 0x1F, tempah);
if (pVBInfo->SetFlag & Win9xDOSMode) {
XGI_DisplayOn(HwDeviceExtension, pVBInfo);
@@ -8150,7 +8520,8 @@
if (!(pVBInfo->SetFlag & DisableChA)) {
XGI_VBLongWait(pVBInfo);
if (!(pVBInfo->SetFlag & GatingCRT)) {
- XGI_DisableGatingCRT(HwDeviceExtension, pVBInfo);
+ XGI_DisableGatingCRT(HwDeviceExtension,
+ pVBInfo);
XGI_DisplayOn(HwDeviceExtension, pVBInfo);
XGI_VBLongWait(pVBInfo);
}
@@ -8159,12 +8530,14 @@
else { /* LVDS */
if (pVBInfo->VBInfo & (SetCRT2ToTV | SetCRT2ToLCD
| SetCRT2ToLCDA))
- xgifb_reg_or(pVBInfo->Part1Port, 0x1E, 0x20); /* enable CRT2 */
+ /* enable CRT2 */
+ xgifb_reg_or(pVBInfo->Part1Port, 0x1E, 0x20);
tempah = (unsigned char) xgifb_reg_get(pVBInfo->Part1Port,
0x2E);
if (!(tempah & 0x80))
- xgifb_reg_or(pVBInfo->Part1Port, 0x2E, 0x80); /* BVBDOENABLE = 1 */
+ /* BVBDOENABLE = 1 */
+ xgifb_reg_or(pVBInfo->Part1Port, 0x2E, 0x80);
xgifb_reg_and(pVBInfo->Part1Port, 0x00, 0x7F);
XGI_DisplayOn(HwDeviceExtension, pVBInfo);
@@ -8222,8 +8595,8 @@
RefreshRateTableIndex, pVBInfo);
}
- if ((HwDeviceExtension->jChipType >= XG20)
- && (HwDeviceExtension->jChipType < XG27)) { /* fix H/W DCLK/2 bug */
+ if ((HwDeviceExtension->jChipType >= XG20) &&
+ (HwDeviceExtension->jChipType < XG27)) { /* fix H/W DCLK/2 bug */
if ((ModeNo == 0x00) | (ModeNo == 0x01)) {
xgifb_reg_set(pVBInfo->P3c4, 0x2B, 0x4E);
xgifb_reg_set(pVBInfo->P3c4, 0x2C, 0xE9);
@@ -8242,8 +8615,10 @@
temp = xgifb_reg_get(pVBInfo->P3d4, 0x38);
if (temp & 0xA0) {
- /* xgifb_reg_and(pVBInfo->P3d4, 0x4A, ~0x20); *//* Enable write GPIOF */
- /* xgifb_reg_and(pVBInfo->P3d4, 0x48, ~0x20); *//* P. DWN */
+ /* Enable write GPIOF */
+ /* xgifb_reg_and(pVBInfo->P3d4, 0x4A, ~0x20); */
+ /* P. DWN */
+ /* xgifb_reg_and(pVBInfo->P3d4, 0x48, ~0x20); */
/* XG21 CRT1 Timing */
if (HwDeviceExtension->jChipType == XG27)
XGI_SetXG27CRTC(ModeNo, ModeIdIndex,
@@ -8270,7 +8645,8 @@
XGI_SetXG21LVDSPara(ModeNo,
ModeIdIndex, pVBInfo);
}
- /* xgifb_reg_or(pVBInfo->P3d4, 0x48, 0x20); *//* P. ON */
+ /* P. ON */
+ /* xgifb_reg_or(pVBInfo->P3d4, 0x48, 0x20); */
}
}
@@ -8289,7 +8665,8 @@
unsigned short ModeNo)
{
unsigned short ModeIdIndex;
- /* unsigned char *pVBInfo->FBAddr = HwDeviceExtension->pjVideoMemoryAddress; */
+ /* unsigned char *pVBInfo->FBAddr =
+ HwDeviceExtension->pjVideoMemoryAddress; */
struct vb_device_info VBINF;
struct vb_device_info *pVBInfo = &VBINF;
pVBInfo->ROMAddr = HwDeviceExtension->pjVirtualRomBase;
@@ -8334,7 +8711,8 @@
pVBInfo->Part4Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14;
pVBInfo->Part5Port = pVBInfo->BaseAddr + XGI_CRT2_PORT_14 + 2;
- if (HwDeviceExtension->jChipType == XG21) { /* for x86 Linux, XG21 LVDS */
+ /* for x86 Linux, XG21 LVDS */
+ if (HwDeviceExtension->jChipType == XG21) {
if ((xgifb_reg_get(pVBInfo->P3d4, 0x38) & 0xE0) == 0xC0)
pVBInfo->IF_DEF_LVDS = 1;
}
@@ -8417,17 +8795,17 @@
} /* !XG20 */
else {
if (pVBInfo->IF_DEF_LVDS == 1)
- if (!XGI_XG21CheckLVDSMode(ModeNo, ModeIdIndex, pVBInfo))
+ if (!XGI_XG21CheckLVDSMode(ModeNo,
+ ModeIdIndex,
+ pVBInfo))
return 0;
if (ModeNo <= 0x13) {
- pVBInfo->ModeType
- = pVBInfo->SModeIDTable[ModeIdIndex].St_ModeFlag
- & ModeInfoFlag;
+ pVBInfo->ModeType = pVBInfo->SModeIDTable[ModeIdIndex].
+ St_ModeFlag & ModeInfoFlag;
} else {
- pVBInfo->ModeType
- = pVBInfo->EModeIDTable[ModeIdIndex].Ext_ModeFlag
- & ModeInfoFlag;
+ pVBInfo->ModeType = pVBInfo->EModeIDTable[ModeIdIndex].
+ Ext_ModeFlag & ModeInfoFlag;
}
pVBInfo->SetFlag = 0;
@@ -8455,7 +8833,10 @@
pVBInfo->ModeType = modeflag&ModeInfoFlag;
pVBInfo->SetFlag = 0x00;
pVBInfo->VBInfo = DisableCRT2Display;
- temp = XGINew_CheckMemorySize(HwDeviceExtension, ModeNo, ModeIdIndex, pVBInfo);
+ temp = XGINew_CheckMemorySize(HwDeviceExtension,
+ ModeNo,
+ ModeIdIndex,
+ pVBInfo);
if (temp == 0)
return (0);
diff --git a/drivers/staging/xgifb/vb_setmode.h b/drivers/staging/xgifb/vb_setmode.h
index 7a2e564..1bd8667 100644
--- a/drivers/staging/xgifb/vb_setmode.h
+++ b/drivers/staging/xgifb/vb_setmode.h
@@ -1,38 +1,71 @@
-#ifndef _VBSETMODE_
-#define _VBSETMODE_
+#ifndef _VBSETMODE_
+#define _VBSETMODE_
-extern void InitTo330Pointer(unsigned char, struct vb_device_info *);
-extern void XGI_UnLockCRT2(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *);
-extern void XGI_LockCRT2(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *);
-extern void XGI_LongWait(struct vb_device_info *);
-extern void XGI_SetCRT2ModeRegs(unsigned short ModeNo,
- struct xgi_hw_device_info *,
+extern void InitTo330Pointer(unsigned char, struct vb_device_info *);
+extern void XGI_UnLockCRT2(struct xgi_hw_device_info *HwDeviceExtension,
+ struct vb_device_info *);
+extern void XGI_LockCRT2(struct xgi_hw_device_info *HwDeviceExtension,
+ struct vb_device_info *);
+extern void XGI_LongWait(struct vb_device_info *);
+extern void XGI_SetCRT2ModeRegs(unsigned short ModeNo,
+ struct xgi_hw_device_info *,
+ struct vb_device_info *);
+extern void XGI_DisableBridge(struct xgi_hw_device_info *HwDeviceExtension,
+ struct vb_device_info *);
+extern void XGI_EnableBridge(struct xgi_hw_device_info *HwDeviceExtension,
+ struct vb_device_info *);
+extern void XGI_DisplayOff(struct xgi_hw_device_info *,
+ struct vb_device_info *);
+extern void XGI_DisplayOn(struct xgi_hw_device_info *,
+ struct vb_device_info *);
+extern void XGI_GetVBType(struct vb_device_info *);
+extern void XGI_SenseCRT1(struct vb_device_info *);
+extern void XGI_GetVGAType(struct xgi_hw_device_info *HwDeviceExtension,
+ struct vb_device_info *);
+extern void XGI_GetVBInfo(unsigned short ModeNo,
+ unsigned short ModeIdIndex,
+ struct xgi_hw_device_info *HwDeviceExtension,
+ struct vb_device_info *);
+extern void XGI_GetTVInfo(unsigned short ModeNo,
+ unsigned short ModeIdIndex,
+ struct vb_device_info *);
+extern unsigned short XGI_GetResInfo(unsigned short ModeNo,
+ unsigned short ModeIdIndex,
+ struct vb_device_info *pVBInfo);
+
+extern unsigned char XGISetModeNew(struct xgi_hw_device_info *HwDeviceExtension,
+ unsigned short ModeNo) ;
+
+extern unsigned char XGI_SearchModeID(unsigned short ModeNo,
+ unsigned short *ModeIdIndex,
struct vb_device_info *);
-extern void XGI_DisableBridge(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *);
-extern void XGI_EnableBridge(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *);
-extern void XGI_DisplayOff(struct xgi_hw_device_info *, struct vb_device_info *);
-extern void XGI_DisplayOn(struct xgi_hw_device_info *, struct vb_device_info *);
-extern void XGI_GetVBType(struct vb_device_info *);
-extern void XGI_SenseCRT1(struct vb_device_info *);
-extern void XGI_GetVGAType(struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *);
-extern void XGI_GetVBInfo(unsigned short ModeNo, unsigned short ModeIdIndex, struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *);
-extern void XGI_GetTVInfo(unsigned short ModeNo, unsigned short ModeIdIndex, struct vb_device_info *);
-extern unsigned short XGI_GetResInfo(unsigned short ModeNo, unsigned short ModeIdIndex, struct vb_device_info *pVBInfo);
+extern unsigned char XGI_GetLCDInfo(unsigned short ModeNo,
+ unsigned short ModeIdIndex,
+ struct vb_device_info *);
+extern unsigned char XGI_BridgeIsOn(struct vb_device_info *);
-extern unsigned char XGISetModeNew(struct xgi_hw_device_info *HwDeviceExtension, unsigned short ModeNo) ;
+extern unsigned char
+XGI_SetCRT2Group301(unsigned short ModeNo,
+ struct xgi_hw_device_info *HwDeviceExtension,
+ struct vb_device_info *);
+extern unsigned short XGI_GetRatePtrCRT2(struct xgi_hw_device_info *pXGIHWDE,
+ unsigned short ModeNo,
+ unsigned short ModeIdIndex,
+ struct vb_device_info *);
-extern unsigned char XGI_SearchModeID(unsigned short ModeNo, unsigned short *ModeIdIndex, struct vb_device_info *);
-extern unsigned char XGI_GetLCDInfo(unsigned short ModeNo, unsigned short ModeIdIndex, struct vb_device_info *);
-extern unsigned char XGI_BridgeIsOn(struct vb_device_info *);
-extern unsigned char XGI_SetCRT2Group301(unsigned short ModeNo, struct xgi_hw_device_info *HwDeviceExtension, struct vb_device_info *);
-extern unsigned short XGI_GetRatePtrCRT2(struct xgi_hw_device_info *pXGIHWDE, unsigned short ModeNo, unsigned short ModeIdIndex, struct vb_device_info *);
-
-extern void XGI_SetXG21FPBits(struct vb_device_info *pVBInfo);
-extern void XGI_SetXG27FPBits(struct vb_device_info *pVBInfo);
-extern void XGI_XG21BLSignalVDD(unsigned short tempbh, unsigned short tempbl, struct vb_device_info *pVBInfo);
-extern void XGI_XG27BLSignalVDD(unsigned short tempbh, unsigned short tempbl, struct vb_device_info *pVBInfo);
-extern void XGI_XG21SetPanelDelay(unsigned short tempbl, struct vb_device_info *pVBInfo);
-extern unsigned char XGI_XG21CheckLVDSMode(unsigned short ModeNo, unsigned short ModeIdIndex, struct vb_device_info *pVBInfo);
-extern unsigned short XGI_GetLVDSOEMTableIndex(struct vb_device_info *pVBInfo);
+extern void XGI_SetXG21FPBits(struct vb_device_info *pVBInfo);
+extern void XGI_SetXG27FPBits(struct vb_device_info *pVBInfo);
+extern void XGI_XG21BLSignalVDD(unsigned short tempbh,
+ unsigned short tempbl,
+ struct vb_device_info *pVBInfo);
+extern void XGI_XG27BLSignalVDD(unsigned short tempbh,
+ unsigned short tempbl,
+ struct vb_device_info *pVBInfo);
+extern void XGI_XG21SetPanelDelay(unsigned short tempbl,
+ struct vb_device_info *pVBInfo);
+extern unsigned char XGI_XG21CheckLVDSMode(unsigned short ModeNo,
+ unsigned short ModeIdIndex,
+ struct vb_device_info *pVBInfo);
+extern unsigned short XGI_GetLVDSOEMTableIndex(struct vb_device_info *pVBInfo);
#endif
diff --git a/drivers/staging/xgifb/vb_struct.h b/drivers/staging/xgifb/vb_struct.h
index 9c6e0c7..377d27c 100644
--- a/drivers/staging/xgifb/vb_struct.h
+++ b/drivers/staging/xgifb/vb_struct.h
@@ -7,369 +7,324 @@
#define EXTERN extern
#endif
-
-
-
-struct XGI_PanelDelayTblStruct
-{
- unsigned char timer[2];
+struct XGI_PanelDelayTblStruct {
+ unsigned char timer[2];
};
-struct XGI_LCDDataStruct
-{
- unsigned short RVBHCMAX;
- unsigned short RVBHCFACT;
- unsigned short VGAHT;
- unsigned short VGAVT;
- unsigned short LCDHT;
- unsigned short LCDVT;
+struct XGI_LCDDataStruct {
+ unsigned short RVBHCMAX;
+ unsigned short RVBHCFACT;
+ unsigned short VGAHT;
+ unsigned short VGAVT;
+ unsigned short LCDHT;
+ unsigned short LCDVT;
};
-struct XGI_LVDSCRT1HDataStruct
-{
- unsigned char Reg[8];
+struct XGI_LVDSCRT1HDataStruct {
+ unsigned char Reg[8];
};
-struct XGI_LVDSCRT1VDataStruct
-{
- unsigned char Reg[7];
+struct XGI_LVDSCRT1VDataStruct {
+ unsigned char Reg[7];
};
-
-struct XGI_TVDataStruct
-{
- unsigned short RVBHCMAX;
- unsigned short RVBHCFACT;
- unsigned short VGAHT;
- unsigned short VGAVT;
- unsigned short TVHDE;
- unsigned short TVVDE;
- unsigned short RVBHRS;
- unsigned char FlickerMode;
- unsigned short HALFRVBHRS;
- unsigned char RY1COE;
- unsigned char RY2COE;
- unsigned char RY3COE;
- unsigned char RY4COE;
+struct XGI_TVDataStruct {
+ unsigned short RVBHCMAX;
+ unsigned short RVBHCFACT;
+ unsigned short VGAHT;
+ unsigned short VGAVT;
+ unsigned short TVHDE;
+ unsigned short TVVDE;
+ unsigned short RVBHRS;
+ unsigned char FlickerMode;
+ unsigned short HALFRVBHRS;
+ unsigned char RY1COE;
+ unsigned char RY2COE;
+ unsigned char RY3COE;
+ unsigned char RY4COE;
};
-struct XGI_LVDSDataStruct
-{
- unsigned short VGAHT;
- unsigned short VGAVT;
- unsigned short LCDHT;
- unsigned short LCDVT;
+struct XGI_LVDSDataStruct {
+ unsigned short VGAHT;
+ unsigned short VGAVT;
+ unsigned short LCDHT;
+ unsigned short LCDVT;
};
-struct XGI_LVDSDesStruct
-{
- unsigned short LCDHDES;
- unsigned short LCDVDES;
+struct XGI_LVDSDesStruct {
+ unsigned short LCDHDES;
+ unsigned short LCDVDES;
};
-struct XGI_LVDSCRT1DataStruct
-{
- unsigned char CR[15];
+struct XGI_LVDSCRT1DataStruct {
+ unsigned char CR[15];
};
/*add for LCDA*/
-struct XGI_StStruct
-{
- unsigned char St_ModeID;
- unsigned short St_ModeFlag;
- unsigned char St_StTableIndex;
- unsigned char St_CRT2CRTC;
- unsigned char St_CRT2CRTC2;
- unsigned char St_ResInfo;
- unsigned char VB_StTVFlickerIndex;
- unsigned char VB_StTVEdgeIndex;
- unsigned char VB_StTVYFilterIndex;
+struct XGI_StStruct {
+ unsigned char St_ModeID;
+ unsigned short St_ModeFlag;
+ unsigned char St_StTableIndex;
+ unsigned char St_CRT2CRTC;
+ unsigned char St_CRT2CRTC2;
+ unsigned char St_ResInfo;
+ unsigned char VB_StTVFlickerIndex;
+ unsigned char VB_StTVEdgeIndex;
+ unsigned char VB_StTVYFilterIndex;
};
-struct XGI_StandTableStruct
-{
- unsigned char CRT_COLS;
- unsigned char ROWS;
- unsigned char CHAR_HEIGHT;
- unsigned short CRT_LEN;
- unsigned char SR[4];
- unsigned char MISC;
- unsigned char CRTC[0x19];
- unsigned char ATTR[0x14];
- unsigned char GRC[9];
+struct XGI_StandTableStruct {
+ unsigned char CRT_COLS;
+ unsigned char ROWS;
+ unsigned char CHAR_HEIGHT;
+ unsigned short CRT_LEN;
+ unsigned char SR[4];
+ unsigned char MISC;
+ unsigned char CRTC[0x19];
+ unsigned char ATTR[0x14];
+ unsigned char GRC[9];
};
-struct XGI_ExtStruct
-{
- unsigned char Ext_ModeID;
- unsigned short Ext_ModeFlag;
- unsigned short Ext_ModeInfo;
- unsigned short Ext_Point;
- unsigned short Ext_VESAID;
- unsigned char Ext_VESAMEMSize;
- unsigned char Ext_RESINFO;
- unsigned char VB_ExtTVFlickerIndex;
- unsigned char VB_ExtTVEdgeIndex;
- unsigned char VB_ExtTVYFilterIndex;
- unsigned char REFindex;
+struct XGI_ExtStruct {
+ unsigned char Ext_ModeID;
+ unsigned short Ext_ModeFlag;
+ unsigned short Ext_ModeInfo;
+ unsigned short Ext_Point;
+ unsigned short Ext_VESAID;
+ unsigned char Ext_VESAMEMSize;
+ unsigned char Ext_RESINFO;
+ unsigned char VB_ExtTVFlickerIndex;
+ unsigned char VB_ExtTVEdgeIndex;
+ unsigned char VB_ExtTVYFilterIndex;
+ unsigned char REFindex;
};
-struct XGI_Ext2Struct
-{
- unsigned short Ext_InfoFlag;
- unsigned char Ext_CRT1CRTC;
- unsigned char Ext_CRTVCLK;
- unsigned char Ext_CRT2CRTC;
- unsigned char Ext_CRT2CRTC2;
- unsigned char ModeID;
- unsigned short XRes;
- unsigned short YRes;
- /* unsigned short ROM_OFFSET; */
+struct XGI_Ext2Struct {
+ unsigned short Ext_InfoFlag;
+ unsigned char Ext_CRT1CRTC;
+ unsigned char Ext_CRTVCLK;
+ unsigned char Ext_CRT2CRTC;
+ unsigned char Ext_CRT2CRTC2;
+ unsigned char ModeID;
+ unsigned short XRes;
+ unsigned short YRes;
+ /* unsigned short ROM_OFFSET; */
};
-struct XGI_MCLKDataStruct
-{
- unsigned char SR28, SR29, SR2A;
- unsigned short CLOCK;
+struct XGI_MCLKDataStruct {
+ unsigned char SR28, SR29, SR2A;
+ unsigned short CLOCK;
};
-struct XGI_ECLKDataStruct
-{
- unsigned char SR2E, SR2F, SR30;
- unsigned short CLOCK;
+struct XGI_ECLKDataStruct {
+ unsigned char SR2E, SR2F, SR30;
+ unsigned short CLOCK;
};
-struct XGI_VCLKDataStruct
-{
- unsigned char SR2B, SR2C;
- unsigned short CLOCK;
+struct XGI_VCLKDataStruct {
+ unsigned char SR2B, SR2C;
+ unsigned short CLOCK;
};
-struct XGI_VBVCLKDataStruct
-{
- unsigned char Part4_A, Part4_B;
- unsigned short CLOCK;
+struct XGI_VBVCLKDataStruct {
+ unsigned char Part4_A, Part4_B;
+ unsigned short CLOCK;
};
-struct XGI_StResInfoStruct
-{
- unsigned short HTotal;
- unsigned short VTotal;
+struct XGI_StResInfoStruct {
+ unsigned short HTotal;
+ unsigned short VTotal;
};
-struct XGI_ModeResInfoStruct
-{
- unsigned short HTotal;
- unsigned short VTotal;
- unsigned char XChar;
- unsigned char YChar;
+struct XGI_ModeResInfoStruct {
+ unsigned short HTotal;
+ unsigned short VTotal;
+ unsigned char XChar;
+ unsigned char YChar;
};
-struct XGI_LCDNBDesStruct
-{
- unsigned char NB[12];
-};
- /*add for new UNIVGABIOS*/
-struct XGI_LCDDesStruct
-{
- unsigned short LCDHDES;
- unsigned short LCDHRS;
- unsigned short LCDVDES;
- unsigned short LCDVRS;
+struct XGI_LCDNBDesStruct {
+ unsigned char NB[12];
};
-struct XGI_LCDDataTablStruct
-{
- unsigned char PANELID;
- unsigned short MASK;
- unsigned short CAP;
- unsigned short DATAPTR;
+/*add for new UNIVGABIOS*/
+struct XGI_LCDDesStruct {
+ unsigned short LCDHDES;
+ unsigned short LCDHRS;
+ unsigned short LCDVDES;
+ unsigned short LCDVRS;
};
-struct XGI_TVTablDataStruct
-{
- unsigned short MASK;
- unsigned short CAP;
- unsigned short DATAPTR;
+struct XGI_LCDDataTablStruct {
+ unsigned char PANELID;
+ unsigned short MASK;
+ unsigned short CAP;
+ unsigned short DATAPTR;
};
-struct XGI330_LCDDataDesStruct
-{
- unsigned short LCDHDES;
- unsigned short LCDHRS;
- unsigned short LCDVDES;
- unsigned short LCDVRS;
+struct XGI_TVTablDataStruct {
+ unsigned short MASK;
+ unsigned short CAP;
+ unsigned short DATAPTR;
+};
+
+struct XGI330_LCDDataDesStruct {
+ unsigned short LCDHDES;
+ unsigned short LCDHRS;
+ unsigned short LCDVDES;
+ unsigned short LCDVRS;
};
-struct XGI330_LVDSDataStruct
-{
- unsigned short VGAHT;
- unsigned short VGAVT;
- unsigned short LCDHT;
- unsigned short LCDVT;
+struct XGI330_LVDSDataStruct {
+ unsigned short VGAHT;
+ unsigned short VGAVT;
+ unsigned short LCDHT;
+ unsigned short LCDVT;
};
-struct XGI330_LCDDataDesStruct2
-{
- unsigned short LCDHDES;
- unsigned short LCDHRS;
- unsigned short LCDVDES;
- unsigned short LCDVRS;
- unsigned short LCDHSync;
- unsigned short LCDVSync;
+struct XGI330_LCDDataDesStruct2 {
+ unsigned short LCDHDES;
+ unsigned short LCDHRS;
+ unsigned short LCDVDES;
+ unsigned short LCDVRS;
+ unsigned short LCDHSync;
+ unsigned short LCDVSync;
};
-struct XGI330_LCDDataStruct
-{
- unsigned short RVBHCMAX;
- unsigned short RVBHCFACT;
- unsigned short VGAHT;
- unsigned short VGAVT;
- unsigned short LCDHT;
- unsigned short LCDVT;
+struct XGI330_LCDDataStruct {
+ unsigned short RVBHCMAX;
+ unsigned short RVBHCFACT;
+ unsigned short VGAHT;
+ unsigned short VGAVT;
+ unsigned short LCDHT;
+ unsigned short LCDVT;
};
-struct XGI330_TVDataStruct
-{
- unsigned short RVBHCMAX;
- unsigned short RVBHCFACT;
- unsigned short VGAHT;
- unsigned short VGAVT;
- unsigned short TVHDE;
- unsigned short TVVDE;
- unsigned short RVBHRS;
- unsigned char FlickerMode;
- unsigned short HALFRVBHRS;
+struct XGI330_TVDataStruct {
+ unsigned short RVBHCMAX;
+ unsigned short RVBHCFACT;
+ unsigned short VGAHT;
+ unsigned short VGAVT;
+ unsigned short TVHDE;
+ unsigned short TVVDE;
+ unsigned short RVBHRS;
+ unsigned char FlickerMode;
+ unsigned short HALFRVBHRS;
};
-struct XGI330_LCDDataTablStruct
-{
- unsigned char PANELID;
- unsigned short MASK;
- unsigned short CAP;
- unsigned short DATAPTR;
+struct XGI330_LCDDataTablStruct {
+ unsigned char PANELID;
+ unsigned short MASK;
+ unsigned short CAP;
+ unsigned short DATAPTR;
};
-struct XGI330_TVDataTablStruct
-{
- unsigned short MASK;
- unsigned short CAP;
- unsigned short DATAPTR;
+struct XGI330_TVDataTablStruct {
+ unsigned short MASK;
+ unsigned short CAP;
+ unsigned short DATAPTR;
};
-struct XGI330_CHTVDataStruct
-{
- unsigned short VGAHT;
- unsigned short VGAVT;
- unsigned short LCDHT;
- unsigned short LCDVT;
+struct XGI330_CHTVDataStruct {
+ unsigned short VGAHT;
+ unsigned short VGAVT;
+ unsigned short LCDHT;
+ unsigned short LCDVT;
};
-struct XGI_TimingHStruct
-{
- unsigned char data[8];
+struct XGI_TimingHStruct {
+ unsigned char data[8];
};
-struct XGI_TimingVStruct
-{
- unsigned char data[7];
+struct XGI_TimingVStruct {
+ unsigned char data[7];
};
-struct XGI_CH7007TV_TimingHStruct
-{
- unsigned char data[10];
+struct XGI_CH7007TV_TimingHStruct {
+ unsigned char data[10];
};
-struct XGI_CH7007TV_TimingVStruct
-{
- unsigned char data[10];
+struct XGI_CH7007TV_TimingVStruct {
+ unsigned char data[10];
};
-struct XGI_XG21CRT1Struct
-{
- unsigned char ModeID, CR02, CR03, CR15, CR16;
+struct XGI_XG21CRT1Struct {
+ unsigned char ModeID, CR02, CR03, CR15, CR16;
};
-struct XGI330_CHTVRegDataStruct
-{
- unsigned char Reg[16];
+struct XGI330_CHTVRegDataStruct {
+ unsigned char Reg[16];
};
-struct XGI330_LCDCapStruct
-{
- unsigned char LCD_ID;
- unsigned short LCD_Capability;
- unsigned char LCD_SetFlag;
- unsigned char LCD_DelayCompensation;
- unsigned char LCD_HSyncWidth;
- unsigned char LCD_VSyncWidth;
- unsigned char LCD_VCLK;
- unsigned char LCDA_VCLKData1;
- unsigned char LCDA_VCLKData2;
- unsigned char LCUCHAR_VCLKData1;
- unsigned char LCUCHAR_VCLKData2;
- unsigned char PSC_S1;
- unsigned char PSC_S2;
- unsigned char PSC_S3;
- unsigned char PSC_S4;
- unsigned char PSC_S5;
- unsigned char PWD_2B;
- unsigned char PWD_2C;
- unsigned char PWD_2D;
- unsigned char PWD_2E;
- unsigned char PWD_2F;
- unsigned char Spectrum_31;
- unsigned char Spectrum_32;
- unsigned char Spectrum_33;
- unsigned char Spectrum_34;
+struct XGI330_LCDCapStruct {
+ unsigned char LCD_ID;
+ unsigned short LCD_Capability;
+ unsigned char LCD_SetFlag;
+ unsigned char LCD_DelayCompensation;
+ unsigned char LCD_HSyncWidth;
+ unsigned char LCD_VSyncWidth;
+ unsigned char LCD_VCLK;
+ unsigned char LCDA_VCLKData1;
+ unsigned char LCDA_VCLKData2;
+ unsigned char LCUCHAR_VCLKData1;
+ unsigned char LCUCHAR_VCLKData2;
+ unsigned char PSC_S1;
+ unsigned char PSC_S2;
+ unsigned char PSC_S3;
+ unsigned char PSC_S4;
+ unsigned char PSC_S5;
+ unsigned char PWD_2B;
+ unsigned char PWD_2C;
+ unsigned char PWD_2D;
+ unsigned char PWD_2E;
+ unsigned char PWD_2F;
+ unsigned char Spectrum_31;
+ unsigned char Spectrum_32;
+ unsigned char Spectrum_33;
+ unsigned char Spectrum_34;
};
-struct XGI21_LVDSCapStruct
-{
- unsigned short LVDS_Capability;
- unsigned short LVDSHT;
- unsigned short LVDSVT;
- unsigned short LVDSHDE;
- unsigned short LVDSVDE;
- unsigned short LVDSHFP;
- unsigned short LVDSVFP;
- unsigned short LVDSHSYNC;
- unsigned short LVDSVSYNC;
- unsigned char VCLKData1;
- unsigned char VCLKData2;
- unsigned char PSC_S1;
- unsigned char PSC_S2;
- unsigned char PSC_S3;
- unsigned char PSC_S4;
- unsigned char PSC_S5;
+struct XGI21_LVDSCapStruct {
+ unsigned short LVDS_Capability;
+ unsigned short LVDSHT;
+ unsigned short LVDSVT;
+ unsigned short LVDSHDE;
+ unsigned short LVDSVDE;
+ unsigned short LVDSHFP;
+ unsigned short LVDSVFP;
+ unsigned short LVDSHSYNC;
+ unsigned short LVDSVSYNC;
+ unsigned char VCLKData1;
+ unsigned char VCLKData2;
+ unsigned char PSC_S1;
+ unsigned char PSC_S2;
+ unsigned char PSC_S3;
+ unsigned char PSC_S4;
+ unsigned char PSC_S5;
};
-struct XGI_CRT1TableStruct
-{
- unsigned char CR[16];
+struct XGI_CRT1TableStruct {
+ unsigned char CR[16];
};
-struct XGI330_VCLKDataStruct
-{
- unsigned char SR2B, SR2C;
- unsigned short CLOCK;
+struct XGI330_VCLKDataStruct {
+ unsigned char SR2B, SR2C;
+ unsigned short CLOCK;
};
-struct XGI301C_Tap4TimingStruct
-{
- unsigned short DE;
- unsigned char Reg[64]; /* C0-FF */
+struct XGI301C_Tap4TimingStruct {
+ unsigned short DE;
+ unsigned char Reg[64]; /* C0-FF */
};
-struct XGI_New_StandTableStruct
-{
+struct XGI_New_StandTableStruct {
unsigned char CRT_COLS;
unsigned char ROWS;
unsigned char CHAR_HEIGHT;
@@ -381,36 +336,37 @@
unsigned char GRC[9];
};
-struct vb_device_info
-{
- unsigned char ISXPDOS;
- unsigned long P3c4,P3d4,P3c0,P3ce,P3c2,P3cc;
- unsigned long P3ca,P3c6,P3c7,P3c8,P3c9,P3da;
- unsigned long Part0Port,Part1Port,Part2Port;
- unsigned long Part3Port,Part4Port,Part5Port;
- unsigned short RVBHCFACT,RVBHCMAX,RVBHRS;
- unsigned short VGAVT,VGAHT,VGAVDE,VGAHDE;
- unsigned short VT,HT,VDE,HDE;
- unsigned short LCDHRS,LCDVRS,LCDHDES,LCDVDES;
+struct vb_device_info {
+ unsigned char ISXPDOS;
+ unsigned long P3c4, P3d4, P3c0, P3ce, P3c2, P3cc;
+ unsigned long P3ca, P3c6, P3c7, P3c8, P3c9, P3da;
+ unsigned long Part0Port, Part1Port, Part2Port;
+ unsigned long Part3Port, Part4Port, Part5Port;
+ unsigned short RVBHCFACT, RVBHCMAX, RVBHRS;
+ unsigned short VGAVT, VGAHT, VGAVDE, VGAHDE;
+ unsigned short VT, HT, VDE, HDE;
+ unsigned short LCDHRS, LCDVRS, LCDHDES, LCDVDES;
- unsigned short ModeType;
- unsigned short IF_DEF_LVDS,IF_DEF_TRUMPION,IF_DEF_DSTN;/* ,IF_DEF_FSTN; add for dstn */
- unsigned short IF_DEF_CRT2Monitor,IF_DEF_VideoCapture;
- unsigned short IF_DEF_LCDA,IF_DEF_CH7017,IF_DEF_YPbPr,IF_DEF_ScaleLCD,IF_DEF_OEMUtil,IF_DEF_PWD;
- unsigned short IF_DEF_ExpLink;
- unsigned short IF_DEF_CH7005,IF_DEF_HiVision;
- unsigned short IF_DEF_CH7007; /* Billy 2007/05/03 */
- unsigned short LCDResInfo,LCDTypeInfo, VBType;/*301b*/
- unsigned short VBInfo,TVInfo,LCDInfo, Set_VGAType;
- unsigned short VBExtInfo;/*301lv*/
- unsigned short SetFlag;
- unsigned short NewFlickerMode;
- unsigned short SelectCRT2Rate;
+ unsigned short ModeType;
+ /* ,IF_DEF_FSTN; add for dstn */
+ unsigned short IF_DEF_LVDS, IF_DEF_TRUMPION, IF_DEF_DSTN;
+ unsigned short IF_DEF_CRT2Monitor, IF_DEF_VideoCapture;
+ unsigned short IF_DEF_LCDA, IF_DEF_CH7017, IF_DEF_YPbPr,
+ IF_DEF_ScaleLCD, IF_DEF_OEMUtil, IF_DEF_PWD;
+ unsigned short IF_DEF_ExpLink;
+ unsigned short IF_DEF_CH7005, IF_DEF_HiVision;
+ unsigned short IF_DEF_CH7007; /* Billy 2007/05/03 */
+ unsigned short LCDResInfo, LCDTypeInfo, VBType;/*301b*/
+ unsigned short VBInfo, TVInfo, LCDInfo, Set_VGAType;
+ unsigned short VBExtInfo;/*301lv*/
+ unsigned short SetFlag;
+ unsigned short NewFlickerMode;
+ unsigned short SelectCRT2Rate;
- unsigned char *ROMAddr;
- unsigned char *FBAddr;
- unsigned long BaseAddr;
- unsigned long RelIO;
+ unsigned char *ROMAddr;
+ unsigned char *FBAddr;
+ unsigned long BaseAddr;
+ unsigned long RelIO;
unsigned char (*CR6B)[4];
unsigned char (*CR6E)[4];
@@ -420,107 +376,106 @@
unsigned char (*SR15)[8];
unsigned char (*CR40)[8];
- unsigned char *pSoftSetting;
- unsigned char *pOutputSelect;
+ unsigned char *pSoftSetting;
+ unsigned char *pOutputSelect;
- unsigned short *pRGBSenseData;
- unsigned short *pRGBSenseData2; /*301b*/
- unsigned short *pVideoSenseData;
- unsigned short *pVideoSenseData2;
- unsigned short *pYCSenseData;
- unsigned short *pYCSenseData2;
+ unsigned short *pRGBSenseData;
+ unsigned short *pRGBSenseData2; /*301b*/
+ unsigned short *pVideoSenseData;
+ unsigned short *pVideoSenseData2;
+ unsigned short *pYCSenseData;
+ unsigned short *pYCSenseData2;
- unsigned char *pSR07;
- unsigned char *CR49;
- unsigned char *pSR1F;
- unsigned char *AGPReg;
- unsigned char *SR16;
- unsigned char *pSR21;
- unsigned char *pSR22;
- unsigned char *pSR23;
- unsigned char *pSR24;
- unsigned char *SR25;
- unsigned char *pSR31;
- unsigned char *pSR32;
- unsigned char *pSR33;
- unsigned char *pSR36; /* alan 12/07/2006 */
- unsigned char *pCRCF;
- unsigned char *pCRD0; /* alan 12/07/2006 */
- unsigned char *pCRDE; /* alan 12/07/2006 */
- unsigned char *pCR8F; /* alan 12/07/2006 */
- unsigned char *pSR40; /* alan 12/07/2006 */
- unsigned char *pSR41; /* alan 12/07/2006 */
- unsigned char *pDVOSetting;
- unsigned char *pCR2E;
- unsigned char *pCR2F;
- unsigned char *pCR46;
- unsigned char *pCR47;
- unsigned char *pCRT2Data_1_2;
- unsigned char *pCRT2Data_4_D;
- unsigned char *pCRT2Data_4_E;
- unsigned char *pCRT2Data_4_10;
- struct XGI_MCLKDataStruct *MCLKData;
- struct XGI_ECLKDataStruct *ECLKData;
+ unsigned char *pSR07;
+ unsigned char *CR49;
+ unsigned char *pSR1F;
+ unsigned char *AGPReg;
+ unsigned char *SR16;
+ unsigned char *pSR21;
+ unsigned char *pSR22;
+ unsigned char *pSR23;
+ unsigned char *pSR24;
+ unsigned char *SR25;
+ unsigned char *pSR31;
+ unsigned char *pSR32;
+ unsigned char *pSR33;
+ unsigned char *pSR36; /* alan 12/07/2006 */
+ unsigned char *pCRCF;
+ unsigned char *pCRD0; /* alan 12/07/2006 */
+ unsigned char *pCRDE; /* alan 12/07/2006 */
+ unsigned char *pCR8F; /* alan 12/07/2006 */
+ unsigned char *pSR40; /* alan 12/07/2006 */
+ unsigned char *pSR41; /* alan 12/07/2006 */
+ unsigned char *pDVOSetting;
+ unsigned char *pCR2E;
+ unsigned char *pCR2F;
+ unsigned char *pCR46;
+ unsigned char *pCR47;
+ unsigned char *pCRT2Data_1_2;
+ unsigned char *pCRT2Data_4_D;
+ unsigned char *pCRT2Data_4_E;
+ unsigned char *pCRT2Data_4_10;
+ struct XGI_MCLKDataStruct *MCLKData;
+ struct XGI_ECLKDataStruct *ECLKData;
- unsigned char *XGI_TVDelayList;
- unsigned char *XGI_TVDelayList2;
- unsigned char *CHTVVCLKUNTSC;
- unsigned char *CHTVVCLKONTSC;
- unsigned char *CHTVVCLKUPAL;
- unsigned char *CHTVVCLKOPAL;
- unsigned char *NTSCTiming;
- unsigned char *PALTiming;
- unsigned char *HiTVExtTiming;
- unsigned char *HiTVSt1Timing;
- unsigned char *HiTVSt2Timing;
- unsigned char *HiTVTextTiming;
- unsigned char *YPbPr750pTiming;
- unsigned char *YPbPr525pTiming;
- unsigned char *YPbPr525iTiming;
- unsigned char *HiTVGroup3Data;
- unsigned char *HiTVGroup3Simu;
- unsigned char *HiTVGroup3Text;
- unsigned char *Ren525pGroup3;
- unsigned char *Ren750pGroup3;
- unsigned char *ScreenOffset;
- unsigned char *pXGINew_DRAMTypeDefinition;
- unsigned char *pXGINew_I2CDefinition ;
- unsigned char *pXGINew_CR97 ;
+ unsigned char *XGI_TVDelayList;
+ unsigned char *XGI_TVDelayList2;
+ unsigned char *CHTVVCLKUNTSC;
+ unsigned char *CHTVVCLKONTSC;
+ unsigned char *CHTVVCLKUPAL;
+ unsigned char *CHTVVCLKOPAL;
+ unsigned char *NTSCTiming;
+ unsigned char *PALTiming;
+ unsigned char *HiTVExtTiming;
+ unsigned char *HiTVSt1Timing;
+ unsigned char *HiTVSt2Timing;
+ unsigned char *HiTVTextTiming;
+ unsigned char *YPbPr750pTiming;
+ unsigned char *YPbPr525pTiming;
+ unsigned char *YPbPr525iTiming;
+ unsigned char *HiTVGroup3Data;
+ unsigned char *HiTVGroup3Simu;
+ unsigned char *HiTVGroup3Text;
+ unsigned char *Ren525pGroup3;
+ unsigned char *Ren750pGroup3;
+ unsigned char *ScreenOffset;
+ unsigned char *pXGINew_DRAMTypeDefinition;
+ unsigned char *pXGINew_I2CDefinition ;
+ unsigned char *pXGINew_CR97 ;
- struct XGI330_LCDCapStruct *LCDCapList;
- struct XGI21_LVDSCapStruct *XG21_LVDSCapList;
+ struct XGI330_LCDCapStruct *LCDCapList;
+ struct XGI21_LVDSCapStruct *XG21_LVDSCapList;
- struct XGI_TimingHStruct *TimingH;
- struct XGI_TimingVStruct *TimingV;
+ struct XGI_TimingHStruct *TimingH;
+ struct XGI_TimingVStruct *TimingV;
- struct XGI_StStruct *SModeIDTable;
- struct XGI_StandTableStruct *StandTable;
- struct XGI_ExtStruct *EModeIDTable;
- struct XGI_Ext2Struct *RefIndex;
- /* XGINew_CRT1TableStruct *CRT1Table; */
- struct XGI_CRT1TableStruct *XGINEWUB_CRT1Table;
- struct XGI_VCLKDataStruct *VCLKData;
- struct XGI_VBVCLKDataStruct *VBVCLKData;
- struct XGI_StResInfoStruct *StResInfo;
- struct XGI_ModeResInfoStruct *ModeResInfo;
- struct XGI_XG21CRT1Struct *UpdateCRT1;
+ struct XGI_StStruct *SModeIDTable;
+ struct XGI_StandTableStruct *StandTable;
+ struct XGI_ExtStruct *EModeIDTable;
+ struct XGI_Ext2Struct *RefIndex;
+ /* XGINew_CRT1TableStruct *CRT1Table; */
+ struct XGI_CRT1TableStruct *XGINEWUB_CRT1Table;
+ struct XGI_VCLKDataStruct *VCLKData;
+ struct XGI_VBVCLKDataStruct *VBVCLKData;
+ struct XGI_StResInfoStruct *StResInfo;
+ struct XGI_ModeResInfoStruct *ModeResInfo;
+ struct XGI_XG21CRT1Struct *UpdateCRT1;
}; /* _struct vb_device_info */
-struct TimingInfo
-{
- unsigned short Horizontal_ACTIVE;
- unsigned short Horizontal_FP;
- unsigned short Horizontal_SYNC;
- unsigned short Horizontal_BP;
- unsigned short Vertical_ACTIVE;
- unsigned short Vertical_FP;
- unsigned short Vertical_SYNC;
- unsigned short Vertical_BP;
- double DCLK;
- unsigned char FrameRate;
- unsigned char Interlace;
- unsigned short Margin;
+struct TimingInfo {
+ unsigned short Horizontal_ACTIVE;
+ unsigned short Horizontal_FP;
+ unsigned short Horizontal_SYNC;
+ unsigned short Horizontal_BP;
+ unsigned short Vertical_ACTIVE;
+ unsigned short Vertical_FP;
+ unsigned short Vertical_SYNC;
+ unsigned short Vertical_BP;
+ double DCLK;
+ unsigned char FrameRate;
+ unsigned char Interlace;
+ unsigned short Margin;
};
#define _VB_STRUCT_
diff --git a/drivers/staging/xgifb/vb_table.h b/drivers/staging/xgifb/vb_table.h
index d71cd55..d10de48 100644
--- a/drivers/staging/xgifb/vb_table.h
+++ b/drivers/staging/xgifb/vb_table.h
@@ -1,186 +1,206 @@
#define Tap4
-//yilin modify for xgi20
-static struct XGI_MCLKDataStruct XGI340New_MCLKData[] =
-{
- { 0x16,0x01,0x01,166},
- { 0x19,0x02,0x01,124},
- { 0x7C,0x08,0x01,200},
- { 0x79,0x06,0x01,250},
- { 0x29,0x01,0x81,301},
- { 0x5c,0x23,0x01,166},
- { 0x5c,0x23,0x01,166},
- { 0x5c,0x23,0x01,166}
+/* yilin modify for xgi20 */
+static struct XGI_MCLKDataStruct XGI340New_MCLKData[] = {
+ {0x16, 0x01, 0x01, 166},
+ {0x19, 0x02, 0x01, 124},
+ {0x7C, 0x08, 0x01, 200},
+ {0x79, 0x06, 0x01, 250},
+ {0x29, 0x01, 0x81, 301},
+ {0x5c, 0x23, 0x01, 166},
+ {0x5c, 0x23, 0x01, 166},
+ {0x5c, 0x23, 0x01, 166}
};
-static struct XGI_MCLKDataStruct XGI27New_MCLKData[] =
-{
- { 0x5c,0x23,0x01,166},
- { 0x19,0x02,0x01,124},
- { 0x7C,0x08,0x80,200},
- { 0x79,0x06,0x80,250},
- { 0x29,0x01,0x81,300},
- { 0x5c,0x23,0x01,166},
- { 0x5c,0x23,0x01,166},
- { 0x5c,0x23,0x01,166}
+static struct XGI_MCLKDataStruct XGI27New_MCLKData[] = {
+ {0x5c, 0x23, 0x01, 166},
+ {0x19, 0x02, 0x01, 124},
+ {0x7C, 0x08, 0x80, 200},
+ {0x79, 0x06, 0x80, 250},
+ {0x29, 0x01, 0x81, 300},
+ {0x5c, 0x23, 0x01, 166},
+ {0x5c, 0x23, 0x01, 166},
+ {0x5c, 0x23, 0x01, 166}
};
-//yilin modify for xgi20
-static struct XGI_ECLKDataStruct XGI340_ECLKData[] =
-{
- { 0x5c,0x23,0x01,166},
- { 0x55,0x84,0x01,123},
- { 0x7C,0x08,0x01,200},
- { 0x79,0x06,0x01,250},
- { 0x29,0x01,0x81,301},
- { 0x5c,0x23,0x01,166},
- { 0x5c,0x23,0x01,166},
- { 0x5c,0x23,0x01,166}
+/* yilin modify for xgi20 */
+static struct XGI_ECLKDataStruct XGI340_ECLKData[] = {
+ {0x5c, 0x23, 0x01, 166},
+ {0x55, 0x84, 0x01, 123},
+ {0x7C, 0x08, 0x01, 200},
+ {0x79, 0x06, 0x01, 250},
+ {0x29, 0x01, 0x81, 301},
+ {0x5c, 0x23, 0x01, 166},
+ {0x5c, 0x23, 0x01, 166},
+ {0x5c, 0x23, 0x01, 166}
};
-
-
static unsigned char XGI340_SR13[4][8] = {
-{0x35,0x45,0xb1,0x00,0x00,0x00,0x00,0x00},/* SR13 */
-{0x41,0x51,0x5c,0x00,0x00,0x00,0x00,0x00},/* SR14 */
-{0x31,0x42,0x42,0x00,0x00,0x00,0x00,0x00},/* SR18 */
-{0x03,0x03,0x03,0x00,0x00,0x00,0x00,0x00}/* SR1B */
+ {0x35, 0x45, 0xb1, 0x00, 0x00, 0x00, 0x00, 0x00}, /* SR13 */
+ {0x41, 0x51, 0x5c, 0x00, 0x00, 0x00, 0x00, 0x00}, /* SR14 */
+ {0x31, 0x42, 0x42, 0x00, 0x00, 0x00, 0x00, 0x00}, /* SR18 */
+ {0x03, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00} /* SR1B */
};
-static unsigned char XGI340_cr41[24][8] =
-{{0x20,0x50,0x60,0x00,0x00,0x00,0x00,0x00},/* 0 CR41 */
-{0xc4,0x40,0x84,0x00,0x00,0x00,0x00,0x00},/* 1 CR8A */
-{0xc4,0x40,0x84,0x00,0x00,0x00,0x00,0x00},/* 2 CR8B */
-{0xb5,0xa4,0xa4,0x00,0x00,0x00,0x00,0x00},
-{0xf0,0xf0,0xf0,0x00,0x00,0x00,0x00,0x00},
-{0x90,0x90,0x24,0x00,0x00,0x00,0x00,0x00},/* 5 CR68 */
-{0x77,0x77,0x44,0x00,0x00,0x00,0x00,0x00},/* 6 CR69 */
-{0x77,0x77,0x44,0x00,0x00,0x00,0x00,0x00},/* 7 CR6A */
-{0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00},/* 8 CR6D */
-{0x55,0x55,0x55,0x00,0x00,0x00,0x00,0x00},/* 9 CR80 */
-{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/* 10 CR81 */
-{0x88,0xa8,0x48,0x00,0x00,0x00,0x00,0x00},/* 11 CR82 */
-{0x44,0x44,0x77,0x00,0x00,0x00,0x00,0x00},/* 12 CR85 */
-{0x48,0x48,0x88,0x00,0x00,0x00,0x00,0x00},/* 13 CR86 */
-{0x54,0x54,0x44,0x00,0x00,0x00,0x00,0x00},/* 14 CR90 */
-{0x54,0x54,0x44,0x00,0x00,0x00,0x00,0x00},/* 15 CR91 */
-{0x0a,0x0a,0x07,0x00,0x00,0x00,0x00,0x00},/* 16 CR92 */
-{0x44,0x44,0x44,0x00,0x00,0x00,0x00,0x00},/* 17 CR93 */
-{0x10,0x10,0x0A,0x00,0x00,0x00,0x00,0x00},/* 18 CR94 */
-{0x11,0x11,0x0a,0x00,0x00,0x00,0x00,0x00},/* 19 CR95 */
-{0x05,0x05,0x05,0x00,0x00,0x00,0x00,0x00},/* 20 CR96 */
-{0xf0,0xf0,0xf0,0x00,0x00,0x00,0x00,0x00},/* 21 CRC3 */
-{0x05,0x00,0x02,0x00,0x00,0x00,0x00,0x00},/* 22 CRC4 */
-{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}/* 23 CRC5 */
+static unsigned char XGI340_cr41[24][8] = {
+ {0x20, 0x50, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00}, /* 0 CR41 */
+ {0xc4, 0x40, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00}, /* 1 CR8A */
+ {0xc4, 0x40, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00}, /* 2 CR8B */
+ {0xb5, 0xa4, 0xa4, 0x00, 0x00, 0x00, 0x00, 0x00},
+ {0xf0, 0xf0, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00},
+ {0x90, 0x90, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00}, /* 5 CR68 */
+ {0x77, 0x77, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00}, /* 6 CR69 */
+ {0x77, 0x77, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00}, /* 7 CR6A */
+ {0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00}, /* 8 CR6D */
+ {0x55, 0x55, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00}, /* 9 CR80 */
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /* 10 CR81 */
+ {0x88, 0xa8, 0x48, 0x00, 0x00, 0x00, 0x00, 0x00}, /* 11 CR82 */
+ {0x44, 0x44, 0x77, 0x00, 0x00, 0x00, 0x00, 0x00}, /* 12 CR85 */
+ {0x48, 0x48, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00}, /* 13 CR86 */
+ {0x54, 0x54, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00}, /* 14 CR90 */
+ {0x54, 0x54, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00}, /* 15 CR91 */
+ {0x0a, 0x0a, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00}, /* 16 CR92 */
+ {0x44, 0x44, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00}, /* 17 CR93 */
+ {0x10, 0x10, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x00}, /* 18 CR94 */
+ {0x11, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00}, /* 19 CR95 */
+ {0x05, 0x05, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00}, /* 20 CR96 */
+ {0xf0, 0xf0, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00}, /* 21 CRC3 */
+ {0x05, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00}, /* 22 CRC4 */
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /* 23 CRC5 */
};
-
-static unsigned char XGI27_cr41[24][8] =
-{
-{0x20,0x40,0x60,0x00,0x00,0x00,0x00,0x00},/* 0 CR41 */
-{0xC4,0x40,0x84,0x00,0x00,0x00,0x00,0x00},/* 1 CR8A */
-{0xC4,0x40,0x84,0x00,0x00,0x00,0x00,0x00},/* 2 CR8B */
-{0xB5,0x13,0xa4,0x00,0x00,0x00,0x00,0x00},/* 3 CR40[7],CR99[2:0],CR45[3:0]*/
-{0xf0,0xf5,0xf0,0x00,0x00,0x00,0x00,0x00},/* 4 CR59 */
-{0x90,0x90,0x24,0x00,0x00,0x00,0x00,0x00},/* 5 CR68 */
-{0x77,0x67,0x44,0x00,0x00,0x00,0x00,0x00},/* 6 CR69 */
-{0x77,0x77,0x44,0x00,0x00,0x00,0x00,0x00},/* 7 CR6A */
-{0xff,0xff,0xff,0x00,0x00,0x00,0x00,0x00},/* 8 CR6D */
-{0x55,0x55,0x55,0x00,0x00,0x00,0x00,0x00},/* 9 CR80 */
-{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},/* 10 CR81 */
-{0x88,0xcc,0x48,0x00,0x00,0x00,0x00,0x00},/* 11 CR82 */
-{0x44,0x88,0x77,0x00,0x00,0x00,0x00,0x00},/* 12 CR85 */
-{0x48,0x88,0x88,0x00,0x00,0x00,0x00,0x00},/* 13 CR86 */
-{0x54,0x32,0x44,0x00,0x00,0x00,0x00,0x00},/* 14 CR90 */
-{0x54,0x33,0x44,0x00,0x00,0x00,0x00,0x00},/* 15 CR91 */
-{0x0a,0x07,0x07,0x00,0x00,0x00,0x00,0x00},/* 16 CR92 */
-{0x44,0x63,0x44,0x00,0x00,0x00,0x00,0x00},/* 17 CR93 */
-{0x10,0x14,0x0A,0x00,0x00,0x00,0x00,0x00},/* 18 CR94 */
-{0x11,0x0B,0x0C,0x00,0x00,0x00,0x00,0x00},/* 19 CR95 */
-{0x05,0x22,0x05,0x00,0x00,0x00,0x00,0x00},/* 20 CR96 */
-{0xf0,0xf0,0x00,0x00,0x00,0x00,0x00,0x00},/* 21 CRC3 */
-{0x05,0x00,0x02,0x00,0x00,0x00,0x00,0x00},/* 22 CRC4 */
-{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}/* 23 CRC5 */
+static unsigned char XGI27_cr41[24][8] = {
+ {0x20, 0x40, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00}, /* 0 CR41 */
+ {0xC4, 0x40, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00}, /* 1 CR8A */
+ {0xC4, 0x40, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00}, /* 2 CR8B */
+ {0xB5, 0x13, 0xa4, 0x00, 0x00, 0x00, 0x00, 0x00}, /* 3 CR40[7],
+ CR99[2:0],
+ CR45[3:0]*/
+ {0xf0, 0xf5, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00}, /* 4 CR59 */
+ {0x90, 0x90, 0x24, 0x00, 0x00, 0x00, 0x00, 0x00}, /* 5 CR68 */
+ {0x77, 0x67, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00}, /* 6 CR69 */
+ {0x77, 0x77, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00}, /* 7 CR6A */
+ {0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00}, /* 8 CR6D */
+ {0x55, 0x55, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00}, /* 9 CR80 */
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /* 10 CR81 */
+ {0x88, 0xcc, 0x48, 0x00, 0x00, 0x00, 0x00, 0x00}, /* 11 CR82 */
+ {0x44, 0x88, 0x77, 0x00, 0x00, 0x00, 0x00, 0x00}, /* 12 CR85 */
+ {0x48, 0x88, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00}, /* 13 CR86 */
+ {0x54, 0x32, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00}, /* 14 CR90 */
+ {0x54, 0x33, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00}, /* 15 CR91 */
+ {0x0a, 0x07, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00}, /* 16 CR92 */
+ {0x44, 0x63, 0x44, 0x00, 0x00, 0x00, 0x00, 0x00}, /* 17 CR93 */
+ {0x10, 0x14, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x00}, /* 18 CR94 */
+ {0x11, 0x0B, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00}, /* 19 CR95 */
+ {0x05, 0x22, 0x05, 0x00, 0x00, 0x00, 0x00, 0x00}, /* 20 CR96 */
+ {0xf0, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, /* 21 CRC3 */
+ {0x05, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00}, /* 22 CRC4 */
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} /* 23 CRC5 */
};
static unsigned char XGI340_CR6B[8][4] = {
-{0xaa,0xaa,0xaa,0xaa},
-{0xaa,0xaa,0xaa,0xaa},
-{0xaa,0xaa,0xaa,0xaa},
-{0x00,0x00,0x00,0x00},
-{0x00,0x00,0x00,0x00},
-{0x00,0x00,0x00,0x00},
-{0x00,0x00,0x00,0x00},
-{0x00,0x00,0x00,0x00}
+ {0xaa, 0xaa, 0xaa, 0xaa},
+ {0xaa, 0xaa, 0xaa, 0xaa},
+ {0xaa, 0xaa, 0xaa, 0xaa},
+ {0x00, 0x00, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00}
};
static unsigned char XGI340_CR6E[8][4] = {
-{0x00,0x00,0x00,0x00},
-{0x00,0x00,0x00,0x00},
-{0x00,0x00,0x00,0x00},
-{0x00,0x00,0x00,0x00},
-{0x00,0x00,0x00,0x00},
-{0x00,0x00,0x00,0x00},
-{0x00,0x00,0x00,0x00},
-{0x00,0x00,0x00,0x00}
+ {0x00, 0x00, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00}
};
static unsigned char XGI340_CR6F[8][32] = {
-{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},
-{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},
-{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},
-{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},
-{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},
-{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},
-{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},
-{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
};
static unsigned char XGI340_CR89[8][2] = {
-{0x00,0x00},
-{0x00,0x00},
-{0x00,0x00},
-{0x00,0x00},
-{0x00,0x00},
-{0x00,0x00},
-{0x00,0x00},
-{0x00,0x00}
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00},
+ {0x00, 0x00}
};
- /* CR47,CR48,CR49,CR4A,CR4B,CR4C,CR70,CR71,CR74,CR75,CR76,CR77 */
+/* CR47,CR48,CR49,CR4A,CR4B,CR4C,CR70,CR71,CR74,CR75,CR76,CR77 */
static unsigned char XGI340_AGPReg[12] = {
- 0x28, 0x23, 0x00, 0x20, 0x00, 0x20, 0x00,
- 0x05, 0xd0, 0x10, 0x10, 0x00};
+ 0x28, 0x23, 0x00, 0x20, 0x00, 0x20,
+ 0x00, 0x05, 0xd0, 0x10, 0x10, 0x00
+};
static unsigned char XGI340_SR16[4] = {0x03, 0x83, 0x03, 0x83};
#if 0
static unsigned char XGI330_SR15_1[8][8] = {
-{0x0,0x0,0x00,0x00,0x20,0x20,0x00,0x00},
-{0x5,0x15,0x15,0x15,0x15,0x15,0x00,0x00},
-{0xba,0xba,0xba,0xba,0xBA,0xBA,0x00,0x00},
-{0x55,0x57,0x57,0xAB,0xAB,0xAB,0x00,0x00},
-{0x60,0x34,0x34,0x34,0x34,0x34,0x00,0x00},
-{0x0,0x80,0x80,0x80,0x83,0x83,0x00,0x00},
-{0x50,0x50,0x50,0x3C,0x3C,0x3C,0x00,0x00},
-{0x0,0xa5,0xfb,0xf6,0xF6,0xF6,0x00,0x00}
+ {0x0, 0x0, 0x00, 0x00, 0x20, 0x20, 0x00, 0x00},
+ {0x5, 0x15, 0x15, 0x15, 0x15, 0x15, 0x00, 0x00},
+ {0xba, 0xba, 0xba, 0xba, 0xBA, 0xBA, 0x00, 0x00},
+ {0x55, 0x57, 0x57, 0xAB, 0xAB, 0xAB, 0x00, 0x00},
+ {0x60, 0x34, 0x34, 0x34, 0x34, 0x34, 0x00, 0x00},
+ {0x0, 0x80, 0x80, 0x80, 0x83, 0x83, 0x00, 0x00},
+ {0x50, 0x50, 0x50, 0x3C, 0x3C, 0x3C, 0x00, 0x00},
+ {0x0, 0xa5, 0xfb, 0xf6, 0xF6, 0xF6, 0x00, 0x00}
};
static unsigned char XGI330_cr40_1[15][8] = {
-{0x66,0x40,0x40,0x28,0x24,0x24,0x00,0x00},
-{0x66,0x00,0x00,0x00,0x00,0x00,0x00,0x00},
-{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},
-{0x00,0x00,0x00,0x00,0x0F,0x0F,0x00,0x00},
-{0x00,0xf0,0xf0,0xf0,0xF0,0xF0,0x00,0x00},
-{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},
-{0x10,0x10,0x10,0x10,0x20,0x20,0x00,0x00},
-{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},
-{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},
-{0x88,0x88,0x88,0xAA,0xAC,0xAC,0x00,0x00},
-{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},
-{0x00,0x00,0x00,0x00,0x77,0x77,0x00,0x00},
-{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},
-{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00},
-{0x00,0xA2,0x00,0x00,0xA2,0xA2,0x00,0x00},
+ {0x66, 0x40, 0x40, 0x28, 0x24, 0x24, 0x00, 0x00},
+ {0x66, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00, 0x0F, 0x0F, 0x00, 0x00},
+ {0x00, 0xf0, 0xf0, 0xf0, 0xF0, 0xF0, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ {0x10, 0x10, 0x10, 0x10, 0x20, 0x20, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ {0x88, 0x88, 0x88, 0xAA, 0xAC, 0xAC, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00, 0x77, 0x77, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+ {0x00, 0xA2, 0x00, 0x00, 0xA2, 0xA2, 0x00, 0x00},
};
#endif
@@ -191,3248 +211,3380 @@
static unsigned char XG40_CRCF = 0x13;
static unsigned char XG40_DRAMTypeDefinition = 0xFF ;
-static struct XGI_StStruct XGI330_SModeIDTable[] =
-{
- {0x01,0x9208,0x01,0x00,0x10,0x00,0x00,0x01,0x00},
- {0x01,0x1210,0x14,0x01,0x00,0x01,0x00,0x01,0x00},
- {0x01,0x1010,0x17,0x02,0x11,0x00,0x00,0x01,0x01},
- {0x03,0x8208,0x03,0x00,0x14,0x00,0x00,0x01,0x02},
- {0x03,0x0210,0x16,0x01,0x04,0x01,0x00,0x01,0x02},
- {0x03,0x0010,0x18,0x02,0x15,0x00,0x00,0x01,0x03},
- {0x05,0x9209,0x05,0x00,0x10,0x00,0x00,0x00,0x04},
- {0x06,0x8209,0x06,0x00,0x14,0x00,0x00,0x00,0x05},
- {0x07,0x0000,0x07,0x03,0x05,0x03,0x00,0x01,0x03},
- {0x07,0x0000,0x19,0x02,0x15,0x02,0x00,0x01,0x03},
- {0x0d,0x920a,0x0d,0x00,0x10,0x00,0x00,0x00,0x04},
- {0x0e,0x820a,0x0e,0x00,0x14,0x00,0x00,0x00,0x05},
- {0x0f,0x0202,0x11,0x01,0x04,0x01,0x00,0x00,0x05},
- {0x10,0x0212,0x12,0x01,0x04,0x01,0x00,0x00,0x05},
- {0x11,0x0212,0x1a,0x04,0x24,0x04,0x00,0x00,0x05},
- {0x12,0x0212,0x1b,0x04,0x24,0x04,0x00,0x00,0x05},
- {0x13,0x021b,0x1c,0x00,0x14,0x00,0x00,0x00,0x04},
- {0x12,0x0010,0x18,0x02,0x24,0x02,0x00,0x00,0x05},/* St_CRT2CRTC2 not sure */
- {0x12,0x0210,0x18,0x01,0x24,0x01,0x00,0x00,0x05},/* St_CRT2CRTC2 not sure */
- {0xff,0x0000,0x00,0x00,0x00,0x00,0x00,0x00,0x00}
+static struct XGI_StStruct XGI330_SModeIDTable[] = {
+ {0x01, 0x9208, 0x01, 0x00, 0x10, 0x00, 0x00, 0x01, 0x00},
+ {0x01, 0x1210, 0x14, 0x01, 0x00, 0x01, 0x00, 0x01, 0x00},
+ {0x01, 0x1010, 0x17, 0x02, 0x11, 0x00, 0x00, 0x01, 0x01},
+ {0x03, 0x8208, 0x03, 0x00, 0x14, 0x00, 0x00, 0x01, 0x02},
+ {0x03, 0x0210, 0x16, 0x01, 0x04, 0x01, 0x00, 0x01, 0x02},
+ {0x03, 0x0010, 0x18, 0x02, 0x15, 0x00, 0x00, 0x01, 0x03},
+ {0x05, 0x9209, 0x05, 0x00, 0x10, 0x00, 0x00, 0x00, 0x04},
+ {0x06, 0x8209, 0x06, 0x00, 0x14, 0x00, 0x00, 0x00, 0x05},
+ {0x07, 0x0000, 0x07, 0x03, 0x05, 0x03, 0x00, 0x01, 0x03},
+ {0x07, 0x0000, 0x19, 0x02, 0x15, 0x02, 0x00, 0x01, 0x03},
+ {0x0d, 0x920a, 0x0d, 0x00, 0x10, 0x00, 0x00, 0x00, 0x04},
+ {0x0e, 0x820a, 0x0e, 0x00, 0x14, 0x00, 0x00, 0x00, 0x05},
+ {0x0f, 0x0202, 0x11, 0x01, 0x04, 0x01, 0x00, 0x00, 0x05},
+ {0x10, 0x0212, 0x12, 0x01, 0x04, 0x01, 0x00, 0x00, 0x05},
+ {0x11, 0x0212, 0x1a, 0x04, 0x24, 0x04, 0x00, 0x00, 0x05},
+ {0x12, 0x0212, 0x1b, 0x04, 0x24, 0x04, 0x00, 0x00, 0x05},
+ {0x13, 0x021b, 0x1c, 0x00, 0x14, 0x00, 0x00, 0x00, 0x04},
+ {0x12, 0x0010, 0x18, 0x02, 0x24, 0x02, 0x00, 0x00, 0x05},/* St_CRT2CRTC2
+ not sure */
+ {0x12, 0x0210, 0x18, 0x01, 0x24, 0x01, 0x00, 0x00, 0x05},/* St_CRT2CRTC2
+ not sure */
+ {0xff, 0x0000, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}
};
-static struct XGI_ExtStruct XGI330_EModeIDTable[] =
-{
- {0x6a,0x2212,0x0407,0x3a81,0x0102,0x08,0x07,0x00,0x00,0x07,0x0e},
- {0x2e,0x0a1b,0x0306,0x3a57,0x0101,0x08,0x06,0x00,0x00,0x05,0x06},
- {0x2f,0x0a1b,0x0305,0x3a50,0x0100,0x08,0x05,0x00,0x00,0x05,0x05},
- {0x30,0x2a1b,0x0407,0x3a81,0x0103,0x08,0x07,0x00,0x00,0x07,0x0e},
- {0x31,0x0a1b,0x030d,0x3b85,0x0000,0x08,0x0d,0x00,0x00,0x06,0x3d},
- {0x32,0x0a1b,0x0a0e,0x3b8c,0x0000,0x08,0x0e,0x00,0x00,0x06,0x3e},
- {0x33,0x0a1d,0x0a0d,0x3b85,0x0000,0x08,0x0d,0x00,0x00,0x06,0x3d},
- {0x34,0x2a1d,0x0a0e,0x3b8c,0x0000,0x08,0x0e,0x00,0x00,0x06,0x3e},
- {0x35,0x0a1f,0x0a0d,0x3b85,0x0000,0x08,0x0d,0x00,0x00,0x06,0x3d},
- {0x36,0x2a1f,0x0a0e,0x3b8c,0x0000,0x08,0x0e,0x00,0x00,0x06,0x3e},
- {0x37,0x0212,0x0508,0x3aab,0x0104,0x08,0x08,0x00,0x00,0x00,0x16},
- {0x38,0x0a1b,0x0508,0x3aab,0x0105,0x08,0x08,0x00,0x00,0x00,0x16},
- {0x3a,0x0e3b,0x0609,0x3adc,0x0107,0x08,0x09,0x00,0x00,0x00,0x1e},
- {0x3c,0x0e3b,0x070a,0x3af2,0x0130,0x08,0x0a,0x00,0x00,0x00,0x22}, /* mode 1600x1200 add CRT2MODE [2003/10/07] */
- {0x3d,0x0e7d,0x070a,0x3af2,0x0131,0x08,0x0a,0x00,0x00,0x00,0x22}, /* mode 1600x1200 add CRT2MODE */
- {0x40,0x9a1c,0x0000,0x3a34,0x010d,0x08,0x00,0x00,0x00,0x04,0x00},
- {0x41,0x9a1d,0x0000,0x3a34,0x010e,0x08,0x00,0x00,0x00,0x04,0x00}, /* ModeIdIndex = 0x10 */
- {0x43,0x0a1c,0x0306,0x3a57,0x0110,0x08,0x06,0x00,0x00,0x05,0x06},
- {0x44,0x0a1d,0x0306,0x3a57,0x0111,0x08,0x06,0x00,0x00,0x05,0x06},
- {0x46,0x2a1c,0x0407,0x3a81,0x0113,0x08,0x07,0x00,0x00,0x07,0x0e},
- {0x47,0x2a1d,0x0407,0x3a81,0x0114,0x08,0x07,0x00,0x00,0x07,0x0e},
- {0x49,0x0a3c,0x0508,0x3aab,0x0116,0x08,0x08,0x00,0x00,0x00,0x16},
- {0x4a,0x0a3d,0x0508,0x3aab,0x0117,0x08,0x08,0x00,0x00,0x00,0x16},
- {0x4c,0x0e7c,0x0609,0x3adc,0x0119,0x08,0x09,0x00,0x00,0x00,0x1e},
- {0x4d,0x0e7d,0x0609,0x3adc,0x011a,0x08,0x09,0x00,0x00,0x00,0x1e},
- {0x50,0x9a1b,0x0001,0x3a3b,0x0132,0x08,0x01,0x00,0x00,0x04,0x02},
- {0x51,0xba1b,0x0103,0x3a42,0x0133,0x08,0x03,0x00,0x00,0x07,0x03},
- {0x52,0x9a1b,0x0204,0x3a49,0x0134,0x08,0x04,0x00,0x00,0x00,0x04},
- {0x56,0x9a1d,0x0001,0x3a3b,0x0135,0x08,0x01,0x00,0x00,0x04,0x02},
- {0x57,0xba1d,0x0103,0x3a42,0x0136,0x08,0x03,0x00,0x00,0x07,0x03},
- {0x58,0x9a1d,0x0204,0x3a49,0x0137,0x08,0x04,0x00,0x00,0x00,0x04},
- {0x59,0x9a1b,0x0000,0x3a34,0x0138,0x08,0x00,0x00,0x00,0x04,0x00},
- {0x5A,0x021b,0x0014,0x3b83,0x0138,0x08,0x01,0x00,0x00,0x04,0x3f}, /* ModeIdIndex = 0x20 */
- {0x5B,0x0a1d,0x0014,0x3b83,0x0135,0x08,0x01,0x00,0x00,0x04,0x3f},
- {0x5d,0x0a1d,0x0305,0x3a50,0x0139,0x08,0x05,0x00,0x00,0x07,0x05},
- {0x62,0x0a3f,0x0306,0x3a57,0x013a,0x08,0x06,0x00,0x00,0x05,0x06},
- {0x63,0x2a3f,0x0407,0x3a81,0x013b,0x08,0x07,0x00,0x00,0x07,0x0e},
- {0x64,0x0a7f,0x0508,0x3aab,0x013c,0x08,0x08,0x00,0x00,0x00,0x16},
- {0x65,0x0eff,0x0609,0x3adc,0x013d,0x08,0x09,0x00,0x00,0x00,0x1e},
- {0x66,0x0eff,0x070a,0x3af2,0x013e,0x08,0x0a,0x00,0x00,0x00,0x22}, /* mode 1600x1200 add CRT2MODE */
- {0x68,0x067b,0x080b,0x3b17,0x013f,0x08,0x0b,0x00,0x00,0x00,0x29},
- {0x69,0x06fd,0x080b,0x3b17,0x0140,0x08,0x0b,0x00,0x00,0x00,0x29},
- {0x6b,0x07ff,0x080b,0x3b17,0x0141,0x10,0x0b,0x00,0x00,0x00,0x29},
- {0x6c,0x067b,0x090c,0x3b37,0x0000,0x08,0x0c,0x00,0x00,0x00,0x2f},
- {0x6d,0x06fd,0x090c,0x3b37,0x0000,0x10,0x0c,0x00,0x00,0x00,0x2f},
- {0x6e,0x07ff,0x090c,0x3b37,0x0000,0x10,0x0c,0x00,0x00,0x00,0x2f},
- {0x70,0x2a1b,0x0410,0x3b52,0x0000,0x08,0x10,0x00,0x00,0x07,0x34},
- {0x71,0x0a1b,0x0511,0x3b63,0x0000,0x08,0x11,0x00,0x00,0x00,0x37},
- {0x74,0x0a1d,0x0511,0x3b63,0x0000,0x08,0x11,0x00,0x00,0x00,0x37}, /* ModeIdIndex = 0x30 */
- {0x75,0x0a3d,0x0612,0x3b74,0x0000,0x08,0x12,0x00,0x00,0x00,0x3a},
- {0x76,0x2a1f,0x0410,0x3b52,0x0000,0x08,0x10,0x00,0x00,0x07,0x34},
- {0x77,0x0a1f,0x0511,0x3b63,0x0000,0x08,0x11,0x00,0x00,0x00,0x37},
- {0x78,0x0a3f,0x0612,0x3b74,0x0000,0x08,0x12,0x00,0x00,0x00,0x3a},
- {0x79,0x0a3b,0x0612,0x3b74,0x0000,0x08,0x12,0x00,0x00,0x00,0x3a},
- {0x7a,0x2a1d,0x0410,0x3b52,0x0000,0x08,0x10,0x00,0x00,0x07,0x34},
- {0x7b,0x0e3b,0x060f,0x3ad0,0x0000,0x08,0x0f,0x00,0x00,0x00,0x1d},
- {0x7c,0x0e7d,0x060f,0x3ad0,0x0000,0x08,0x0f,0x00,0x00,0x00,0x1d},
- {0x7d,0x0eff,0x060f,0x3ad0,0x0000,0x08,0x0f,0x00,0x00,0x00,0x1d},
- {0x20,0x0e3b,0x0D16,0x49e0,0x0000,0x08,0x16,0x00,0x00,0x00,0x43},
- {0x21,0x0e7d,0x0D16,0x49e0,0x0000,0x08,0x16,0x00,0x00,0x00,0x43},
- {0x22,0x0eff,0x0D16,0x49e0,0x0000,0x08,0x16,0x00,0x00,0x00,0x43},
- {0x23,0x0e3b,0x0614,0x49d5,0x0000,0x08,0x14,0x00,0x00,0x00,0x41},
- {0x24,0x0e7d,0x0614,0x49d5,0x0000,0x08,0x14,0x00,0x00,0x00,0x41},
- {0x25,0x0eff,0x0614,0x49d5,0x0000,0x08,0x14,0x00,0x00,0x00,0x41},
- {0x26,0x063b,0x0c15,0x49dc,0x0000,0x08,0x15,0x00,0x00,0x00,0x42}, /* ModeIdIndex = 0x40 */
- {0x27,0x067d,0x0c15,0x49dc,0x0000,0x08,0x15,0x00,0x00,0x00,0x42},
- {0x28,0x06ff,0x0c15,0x49dc,0x0000,0x08,0x15,0x00,0x00,0x00,0x42},
- {0xff,0x0000,0x0000,0x0000,0x0000,0x00,0x00,0x00,0x00,0x00,0x00}
+static struct XGI_ExtStruct XGI330_EModeIDTable[] = {
+ {0x6a, 0x2212, 0x0407, 0x3a81, 0x0102, 0x08,
+ 0x07, 0x00, 0x00, 0x07, 0x0e},
+ {0x2e, 0x0a1b, 0x0306, 0x3a57, 0x0101, 0x08,
+ 0x06, 0x00, 0x00, 0x05, 0x06},
+ {0x2f, 0x0a1b, 0x0305, 0x3a50, 0x0100, 0x08,
+ 0x05, 0x00, 0x00, 0x05, 0x05},
+ {0x30, 0x2a1b, 0x0407, 0x3a81, 0x0103, 0x08,
+ 0x07, 0x00, 0x00, 0x07, 0x0e},
+ {0x31, 0x0a1b, 0x030d, 0x3b85, 0x0000, 0x08,
+ 0x0d, 0x00, 0x00, 0x06, 0x3d},
+ {0x32, 0x0a1b, 0x0a0e, 0x3b8c, 0x0000, 0x08,
+ 0x0e, 0x00, 0x00, 0x06, 0x3e},
+ {0x33, 0x0a1d, 0x0a0d, 0x3b85, 0x0000, 0x08,
+ 0x0d, 0x00, 0x00, 0x06, 0x3d},
+ {0x34, 0x2a1d, 0x0a0e, 0x3b8c, 0x0000, 0x08,
+ 0x0e, 0x00, 0x00, 0x06, 0x3e},
+ {0x35, 0x0a1f, 0x0a0d, 0x3b85, 0x0000, 0x08,
+ 0x0d, 0x00, 0x00, 0x06, 0x3d},
+ {0x36, 0x2a1f, 0x0a0e, 0x3b8c, 0x0000, 0x08,
+ 0x0e, 0x00, 0x00, 0x06, 0x3e},
+ {0x37, 0x0212, 0x0508, 0x3aab, 0x0104, 0x08,
+ 0x08, 0x00, 0x00, 0x00, 0x16},
+ {0x38, 0x0a1b, 0x0508, 0x3aab, 0x0105, 0x08,
+ 0x08, 0x00, 0x00, 0x00, 0x16},
+ {0x3a, 0x0e3b, 0x0609, 0x3adc, 0x0107, 0x08,
+ 0x09, 0x00, 0x00, 0x00, 0x1e},
+ {0x3c, 0x0e3b, 0x070a, 0x3af2, 0x0130, 0x08,
+ 0x0a, 0x00, 0x00, 0x00, 0x22}, /* mode 1600x1200
+ add CRT2MODE [2003/10/07] */
+ {0x3d, 0x0e7d, 0x070a, 0x3af2, 0x0131, 0x08,
+ 0x0a, 0x00, 0x00, 0x00, 0x22}, /* mode 1600x1200
+ add CRT2MODE */
+ {0x40, 0x9a1c, 0x0000, 0x3a34, 0x010d, 0x08,
+ 0x00, 0x00, 0x00, 0x04, 0x00},
+ {0x41, 0x9a1d, 0x0000, 0x3a34, 0x010e, 0x08,
+ 0x00, 0x00, 0x00, 0x04, 0x00}, /* ModeIdIndex = 0x10 */
+ {0x43, 0x0a1c, 0x0306, 0x3a57, 0x0110, 0x08,
+ 0x06, 0x00, 0x00, 0x05, 0x06},
+ {0x44, 0x0a1d, 0x0306, 0x3a57, 0x0111, 0x08,
+ 0x06, 0x00, 0x00, 0x05, 0x06},
+ {0x46, 0x2a1c, 0x0407, 0x3a81, 0x0113, 0x08,
+ 0x07, 0x00, 0x00, 0x07, 0x0e},
+ {0x47, 0x2a1d, 0x0407, 0x3a81, 0x0114, 0x08,
+ 0x07, 0x00, 0x00, 0x07, 0x0e},
+ {0x49, 0x0a3c, 0x0508, 0x3aab, 0x0116, 0x08,
+ 0x08, 0x00, 0x00, 0x00, 0x16},
+ {0x4a, 0x0a3d, 0x0508, 0x3aab, 0x0117, 0x08,
+ 0x08, 0x00, 0x00, 0x00, 0x16},
+ {0x4c, 0x0e7c, 0x0609, 0x3adc, 0x0119, 0x08,
+ 0x09, 0x00, 0x00, 0x00, 0x1e},
+ {0x4d, 0x0e7d, 0x0609, 0x3adc, 0x011a, 0x08,
+ 0x09, 0x00, 0x00, 0x00, 0x1e},
+ {0x50, 0x9a1b, 0x0001, 0x3a3b, 0x0132, 0x08,
+ 0x01, 0x00, 0x00, 0x04, 0x02},
+ {0x51, 0xba1b, 0x0103, 0x3a42, 0x0133, 0x08,
+ 0x03, 0x00, 0x00, 0x07, 0x03},
+ {0x52, 0x9a1b, 0x0204, 0x3a49, 0x0134, 0x08,
+ 0x04, 0x00, 0x00, 0x00, 0x04},
+ {0x56, 0x9a1d, 0x0001, 0x3a3b, 0x0135, 0x08,
+ 0x01, 0x00, 0x00, 0x04, 0x02},
+ {0x57, 0xba1d, 0x0103, 0x3a42, 0x0136, 0x08,
+ 0x03, 0x00, 0x00, 0x07, 0x03},
+ {0x58, 0x9a1d, 0x0204, 0x3a49, 0x0137, 0x08,
+ 0x04, 0x00, 0x00, 0x00, 0x04},
+ {0x59, 0x9a1b, 0x0000, 0x3a34, 0x0138, 0x08,
+ 0x00, 0x00, 0x00, 0x04, 0x00},
+ {0x5A, 0x021b, 0x0014, 0x3b83, 0x0138, 0x08,
+ 0x01, 0x00, 0x00, 0x04, 0x3f}, /* ModeIdIndex = 0x20 */
+ {0x5B, 0x0a1d, 0x0014, 0x3b83, 0x0135, 0x08,
+ 0x01, 0x00, 0x00, 0x04, 0x3f},
+ {0x5d, 0x0a1d, 0x0305, 0x3a50, 0x0139, 0x08,
+ 0x05, 0x00, 0x00, 0x07, 0x05},
+ {0x62, 0x0a3f, 0x0306, 0x3a57, 0x013a, 0x08,
+ 0x06, 0x00, 0x00, 0x05, 0x06},
+ {0x63, 0x2a3f, 0x0407, 0x3a81, 0x013b, 0x08,
+ 0x07, 0x00, 0x00, 0x07, 0x0e},
+ {0x64, 0x0a7f, 0x0508, 0x3aab, 0x013c, 0x08,
+ 0x08, 0x00, 0x00, 0x00, 0x16},
+ {0x65, 0x0eff, 0x0609, 0x3adc, 0x013d, 0x08,
+ 0x09, 0x00, 0x00, 0x00, 0x1e},
+ {0x66, 0x0eff, 0x070a, 0x3af2, 0x013e, 0x08,
+ 0x0a, 0x00, 0x00, 0x00, 0x22}, /* mode 1600x1200
+ add CRT2MODE */
+ {0x68, 0x067b, 0x080b, 0x3b17, 0x013f, 0x08,
+ 0x0b, 0x00, 0x00, 0x00, 0x29},
+ {0x69, 0x06fd, 0x080b, 0x3b17, 0x0140, 0x08,
+ 0x0b, 0x00, 0x00, 0x00, 0x29},
+ {0x6b, 0x07ff, 0x080b, 0x3b17, 0x0141, 0x10,
+ 0x0b, 0x00, 0x00, 0x00, 0x29},
+ {0x6c, 0x067b, 0x090c, 0x3b37, 0x0000, 0x08,
+ 0x0c, 0x00, 0x00, 0x00, 0x2f},
+ {0x6d, 0x06fd, 0x090c, 0x3b37, 0x0000, 0x10,
+ 0x0c, 0x00, 0x00, 0x00, 0x2f},
+ {0x6e, 0x07ff, 0x090c, 0x3b37, 0x0000, 0x10,
+ 0x0c, 0x00, 0x00, 0x00, 0x2f},
+ {0x70, 0x2a1b, 0x0410, 0x3b52, 0x0000, 0x08,
+ 0x10, 0x00, 0x00, 0x07, 0x34},
+ {0x71, 0x0a1b, 0x0511, 0x3b63, 0x0000, 0x08,
+ 0x11, 0x00, 0x00, 0x00, 0x37},
+ {0x74, 0x0a1d, 0x0511, 0x3b63, 0x0000, 0x08,
+ 0x11, 0x00, 0x00, 0x00, 0x37}, /* ModeIdIndex = 0x30 */
+ {0x75, 0x0a3d, 0x0612, 0x3b74, 0x0000, 0x08,
+ 0x12, 0x00, 0x00, 0x00, 0x3a},
+ {0x76, 0x2a1f, 0x0410, 0x3b52, 0x0000, 0x08,
+ 0x10, 0x00, 0x00, 0x07, 0x34},
+ {0x77, 0x0a1f, 0x0511, 0x3b63, 0x0000, 0x08,
+ 0x11, 0x00, 0x00, 0x00, 0x37},
+ {0x78, 0x0a3f, 0x0612, 0x3b74, 0x0000, 0x08,
+ 0x12, 0x00, 0x00, 0x00, 0x3a},
+ {0x79, 0x0a3b, 0x0612, 0x3b74, 0x0000, 0x08,
+ 0x12, 0x00, 0x00, 0x00, 0x3a},
+ {0x7a, 0x2a1d, 0x0410, 0x3b52, 0x0000, 0x08,
+ 0x10, 0x00, 0x00, 0x07, 0x34},
+ {0x7b, 0x0e3b, 0x060f, 0x3ad0, 0x0000, 0x08,
+ 0x0f, 0x00, 0x00, 0x00, 0x1d},
+ {0x7c, 0x0e7d, 0x060f, 0x3ad0, 0x0000, 0x08,
+ 0x0f, 0x00, 0x00, 0x00, 0x1d},
+ {0x7d, 0x0eff, 0x060f, 0x3ad0, 0x0000, 0x08,
+ 0x0f, 0x00, 0x00, 0x00, 0x1d},
+ {0x20, 0x0e3b, 0x0D16, 0x49e0, 0x0000, 0x08,
+ 0x16, 0x00, 0x00, 0x00, 0x43},
+ {0x21, 0x0e7d, 0x0D16, 0x49e0, 0x0000, 0x08,
+ 0x16, 0x00, 0x00, 0x00, 0x43},
+ {0x22, 0x0eff, 0x0D16, 0x49e0, 0x0000, 0x08,
+ 0x16, 0x00, 0x00, 0x00, 0x43},
+ {0x23, 0x0e3b, 0x0614, 0x49d5, 0x0000, 0x08,
+ 0x14, 0x00, 0x00, 0x00, 0x41},
+ {0x24, 0x0e7d, 0x0614, 0x49d5, 0x0000, 0x08,
+ 0x14, 0x00, 0x00, 0x00, 0x41},
+ {0x25, 0x0eff, 0x0614, 0x49d5, 0x0000, 0x08,
+ 0x14, 0x00, 0x00, 0x00, 0x41},
+ {0x26, 0x063b, 0x0c15, 0x49dc, 0x0000, 0x08,
+ 0x15, 0x00, 0x00, 0x00, 0x42}, /* ModeIdIndex = 0x40 */
+ {0x27, 0x067d, 0x0c15, 0x49dc, 0x0000, 0x08,
+ 0x15, 0x00, 0x00, 0x00, 0x42},
+ {0x28, 0x06ff, 0x0c15, 0x49dc, 0x0000, 0x08,
+ 0x15, 0x00, 0x00, 0x00, 0x42},
+ {0xff, 0x0000, 0x0000, 0x0000, 0x0000, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00}
};
-static struct XGI_StandTableStruct XGI330_StandTable[] =
-{
+static struct XGI_StandTableStruct XGI330_StandTable[] = {
/* MD_0_200 */
- {
- 0x28,0x18,0x08,0x0800,
- {0x09,0x03,0x00,0x02},
- 0x63,
- {0x2d,0x27,0x28,0x90,0x2b,0xa0,0xbf,0x1f,
- 0x00,0xc7,0x06,0x07,0x00,0x00,0x00,0x00,
- 0x9c,0x8e,0x8f,0x14,0x1f,0x96,0xb9,0xa3,
- 0xff},
- {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,
- 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,
- 0x08,0x00,0x0f,0x00},
- {0x00,0x00,0x00,0x00,0x00,0x10,0x0e,0x00,
- 0xff}
- },
+ {
+ 0x28, 0x18, 0x08, 0x0800,
+ {0x09, 0x03, 0x00, 0x02},
+ 0x63,
+ {0x2d, 0x27, 0x28, 0x90, 0x2b, 0xa0, 0xbf, 0x1f,
+ 0x00, 0xc7, 0x06, 0x07, 0x00, 0x00, 0x00, 0x00,
+ 0x9c, 0x8e, 0x8f, 0x14, 0x1f, 0x96, 0xb9, 0xa3,
+ 0xff},
+ {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
+ 0x08, 0x00, 0x0f, 0x00},
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0e, 0x00,
+ 0xff}
+ },
/* MD_1_200 */
- {
- 0x28,0x18,0x08,0x0800,
- {0x09,0x03,0x00,0x02},
- 0x63,
- {0x2d,0x27,0x28,0x90,0x2b,0xa0,0xbf,0x1f,
- 0x00,0xc7,0x06,0x07,0x00,0x00,0x00,0x00,
- 0x9c,0x8e,0x8f,0x14,0x1f,0x96,0xb9,0xa3,
- 0xff},
- {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,
- 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,
- 0x08,0x00,0x0f,0x00},
- {0x00,0x00,0x00,0x00,0x00,0x10,0x0e,0x00,
- 0xff}
- },
+ {
+ 0x28, 0x18, 0x08, 0x0800,
+ {0x09, 0x03, 0x00, 0x02},
+ 0x63,
+ {0x2d, 0x27, 0x28, 0x90, 0x2b, 0xa0, 0xbf, 0x1f,
+ 0x00, 0xc7, 0x06, 0x07, 0x00, 0x00, 0x00, 0x00,
+ 0x9c, 0x8e, 0x8f, 0x14, 0x1f, 0x96, 0xb9, 0xa3,
+ 0xff},
+ {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
+ 0x08, 0x00, 0x0f, 0x00},
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0e, 0x00,
+ 0xff}
+ },
/* MD_2_200 */
- {
- 0x50,0x18,0x08,0x1000,
- {0x01,0x03,0x00,0x02},
- 0x63,
- {0x5f,0x4f,0x50,0x82,0x55,0x81,0xbf,0x1f,
- 0x00,0xc7,0x06,0x07,0x00,0x00,0x00,0x00,
- 0x9c,0x8e,0x8f,0x28,0x1f,0x96,0xb9,0xa3,
- 0xff},
- {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,
- 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,
- 0x08,0x00,0x0f,0x00},
- {0x00,0x00,0x00,0x00,0x00,0x10,0x0e,0x00,
- 0xff}
- },
+ {
+ 0x50, 0x18, 0x08, 0x1000,
+ {0x01, 0x03, 0x00, 0x02},
+ 0x63,
+ {0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f,
+ 0x00, 0xc7, 0x06, 0x07, 0x00, 0x00, 0x00, 0x00,
+ 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3,
+ 0xff},
+ {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
+ 0x08, 0x00, 0x0f, 0x00},
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0e, 0x00,
+ 0xff}
+ },
/* MD_3_200 */
- {
- 0x50,0x18,0x08,0x1000,
- {0x01,0x03,0x00,0x02},
- 0x63,
- {0x5f,0x4f,0x50,0x82,0x55,0x81,0xbf,0x1f,
- 0x00,0xc7,0x06,0x07,0x00,0x00,0x00,0x00,
- 0x9c,0x8e,0x8f,0x28,0x1f,0x96,0xb9,0xa3,
- 0xff},
- {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,
- 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,
- 0x08,0x00,0x0f,0x00},
- {0x00,0x00,0x00,0x00,0x00,0x10,0x0e,0x00,
- 0xff}
- },
+ {
+ 0x50, 0x18, 0x08, 0x1000,
+ {0x01, 0x03, 0x00, 0x02},
+ 0x63,
+ {0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f,
+ 0x00, 0xc7, 0x06, 0x07, 0x00, 0x00, 0x00, 0x00,
+ 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3,
+ 0xff},
+ {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
+ 0x08, 0x00, 0x0f, 0x00},
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0e, 0x00,
+ 0xff}
+ },
/* MD_4 */
- {
- 0x28,0x18,0x08,0x4000,
- {0x09,0x03,0x00,0x02},
- 0x63,
- {0x2d,0x27,0x28,0x90,0x2c,0x80,0xbf,0x1f,
- 0x00,0xc1,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x9c,0x8e,0x8f,0x14,0x00,0x96,0xb9,0xa2,
- 0xff},
- {0x00,0x13,0x15,0x17,0x02,0x04,0x06,0x07,
- 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,
- 0x01,0x00,0x03,0x00},
- {0x00,0x00,0x00,0x00,0x00,0x30,0x0f,0x00,
- 0xff}
- },
+ {
+ 0x28, 0x18, 0x08, 0x4000,
+ {0x09, 0x03, 0x00, 0x02},
+ 0x63,
+ {0x2d, 0x27, 0x28, 0x90, 0x2c, 0x80, 0xbf, 0x1f,
+ 0x00, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x9c, 0x8e, 0x8f, 0x14, 0x00, 0x96, 0xb9, 0xa2,
+ 0xff},
+ {0x00, 0x13, 0x15, 0x17, 0x02, 0x04, 0x06, 0x07,
+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
+ 0x01, 0x00, 0x03, 0x00},
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0f, 0x00,
+ 0xff}
+ },
/* MD_5 */
- {
- 0x28,0x18,0x08,0x4000,
- {0x09,0x03,0x00,0x02},
- 0x63,
- {0x2d,0x27,0x28,0x90,0x2c,0x80,0xbf,0x1f,
- 0x00,0xc1,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x9c,0x8e,0x8f,0x14,0x00,0x96,0xb9,0xa2,
- 0xff},
- {0x00,0x13,0x15,0x17,0x02,0x04,0x06,0x07,
- 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,
- 0x01,0x00,0x03,0x00},
- {0x00,0x00,0x00,0x00,0x00,0x30,0x0f,0x00,
- 0xff}
- },
+ {
+ 0x28, 0x18, 0x08, 0x4000,
+ {0x09, 0x03, 0x00, 0x02},
+ 0x63,
+ {0x2d, 0x27, 0x28, 0x90, 0x2c, 0x80, 0xbf, 0x1f,
+ 0x00, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x9c, 0x8e, 0x8f, 0x14, 0x00, 0x96, 0xb9, 0xa2,
+ 0xff},
+ {0x00, 0x13, 0x15, 0x17, 0x02, 0x04, 0x06, 0x07,
+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
+ 0x01, 0x00, 0x03, 0x00},
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x0f, 0x00,
+ 0xff}
+ },
/* MD_6 */
- {
- 0x50,0x18,0x08,0x4000,
- {0x01,0x01,0x00,0x06},
- 0x63,
- {0x5f,0x4f,0x50,0x82,0x55,0x81,0xbf,0x1f,
- 0x00,0xc1,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x9c,0x8e,0x8f,0x28,0x00,0x96,0xb9,0xc2,
- 0xff},
- {0x00,0x17,0x17,0x17,0x17,0x17,0x17,0x17,
- 0x17,0x17,0x17,0x17,0x17,0x17,0x17,0x17,
- 0x01,0x00,0x01,0x00},
- {0x00,0x00,0x00,0x00,0x00,0x00,0x0d,0x00,
- 0xff}
- },
+ {
+ 0x50, 0x18, 0x08, 0x4000,
+ {0x01, 0x01, 0x00, 0x06},
+ 0x63,
+ {0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f,
+ 0x00, 0xc1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x9c, 0x8e, 0x8f, 0x28, 0x00, 0x96, 0xb9, 0xc2,
+ 0xff},
+ {0x00, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17,
+ 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17, 0x17,
+ 0x01, 0x00, 0x01, 0x00},
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0d, 0x00,
+ 0xff}
+ },
/* MD_7 */
- {
- 0x50,0x18,0x0e,0x1000,
- {0x00,0x03,0x00,0x03},
- 0xa6,
- {0x5f,0x4f,0x50,0x82,0x55,0x81,0xbf,0x1f,
- 0x00,0x4d,0x0b,0x0c,0x00,0x00,0x00,0x00,
- 0x83,0x85,0x5d,0x28,0x0d,0x63,0xba,0xa3,
- 0xff},
- {0x00,0x08,0x08,0x08,0x08,0x08,0x08,0x08,
- 0x10,0x18,0x18,0x18,0x18,0x18,0x18,0x18,
- 0x0e,0x00,0x0f,0x08},
- {0x00,0x00,0x00,0x00,0x00,0x10,0x0a,0x00,
- 0xff}
- },
+ {
+ 0x50, 0x18, 0x0e, 0x1000,
+ {0x00, 0x03, 0x00, 0x03},
+ 0xa6,
+ {0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f,
+ 0x00, 0x4d, 0x0b, 0x0c, 0x00, 0x00, 0x00, 0x00,
+ 0x83, 0x85, 0x5d, 0x28, 0x0d, 0x63, 0xba, 0xa3,
+ 0xff},
+ {0x00, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
+ 0x10, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+ 0x0e, 0x00, 0x0f, 0x08},
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0a, 0x00,
+ 0xff}
+ },
/* MDA_DAC */
- {
- 0x00,0x00,0x00,0x0000,
- {0x00,0x00,0x00,0x15},
- 0x15,
- {0x15,0x15,0x15,0x15,0x15,0x15,0x15,0x15,
- 0x15,0x15,0x15,0x15,0x15,0x15,0x3f,0x3f,
- 0x3f,0x3f,0x3f,0x3f,0x3f,0x3f,0x00,0x00,
- 0x00},
- {0x00,0x00,0x00,0x00,0x00,0x15,0x15,0x15,
- 0x15,0x15,0x15,0x15,0x15,0x15,0x15,0x15,
- 0x15,0x15,0x15,0x15},
- {0x15,0x3f,0x3f,0x3f,0x3f,0x3f,0x3f,0x3f,
- 0x3f}
- },
+ {
+ 0x00, 0x00, 0x00, 0x0000,
+ {0x00, 0x00, 0x00, 0x15},
+ 0x15,
+ {0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15,
+ 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x3f, 0x3f,
+ 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x00, 0x00,
+ 0x00},
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x15, 0x15, 0x15,
+ 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15, 0x15,
+ 0x15, 0x15, 0x15, 0x15},
+ {0x15, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f,
+ 0x3f}
+ },
/* CGA_DAC */
- {
- 0x00,0x10,0x04,0x0114,
- {0x11,0x09,0x15,0x00},
- 0x10,
- {0x04,0x14,0x01,0x11,0x09,0x15,0x2a,0x3a,
- 0x2e,0x3e,0x2b,0x3b,0x2f,0x3f,0x2a,0x3a,
- 0x2e,0x3e,0x2b,0x3b,0x2f,0x3f,0x00,0x10,
- 0x04},
- {0x14,0x01,0x11,0x09,0x15,0x00,0x10,0x04,
- 0x14,0x01,0x11,0x09,0x15,0x2a,0x3a,0x2e,
- 0x3e,0x2b,0x3b,0x2f},
- {0x3f,0x2a,0x3a,0x2e,0x3e,0x2b,0x3b,0x2f,
- 0x3f}
- },
+ {
+ 0x00, 0x10, 0x04, 0x0114,
+ {0x11, 0x09, 0x15, 0x00},
+ 0x10,
+ {0x04, 0x14, 0x01, 0x11, 0x09, 0x15, 0x2a, 0x3a,
+ 0x2e, 0x3e, 0x2b, 0x3b, 0x2f, 0x3f, 0x2a, 0x3a,
+ 0x2e, 0x3e, 0x2b, 0x3b, 0x2f, 0x3f, 0x00, 0x10,
+ 0x04},
+ {0x14, 0x01, 0x11, 0x09, 0x15, 0x00, 0x10, 0x04,
+ 0x14, 0x01, 0x11, 0x09, 0x15, 0x2a, 0x3a, 0x2e,
+ 0x3e, 0x2b, 0x3b, 0x2f},
+ {0x3f, 0x2a, 0x3a, 0x2e, 0x3e, 0x2b, 0x3b, 0x2f,
+ 0x3f}
+ },
/* EGA_DAC */
- {
- 0x00,0x10,0x04,0x0114,
- {0x11,0x05,0x15,0x20},
- 0x30,
- {0x24,0x34,0x21,0x31,0x25,0x35,0x08,0x18,
- 0x0c,0x1c,0x09,0x19,0x0d,0x1d,0x28,0x38,
- 0x2c,0x3c,0x29,0x39,0x2d,0x3d,0x02,0x12,
- 0x06},
- {0x16,0x03,0x13,0x07,0x17,0x22,0x32,0x26,
- 0x36,0x23,0x33,0x27,0x37,0x0a,0x1a,0x0e,
- 0x1e,0x0b,0x1b,0x0f},
- {0x1f,0x2a,0x3a,0x2e,0x3e,0x2b,0x3b,0x2f,
- 0x3f}
- },
+ {
+ 0x00, 0x10, 0x04, 0x0114,
+ {0x11, 0x05, 0x15, 0x20},
+ 0x30,
+ {0x24, 0x34, 0x21, 0x31, 0x25, 0x35, 0x08, 0x18,
+ 0x0c, 0x1c, 0x09, 0x19, 0x0d, 0x1d, 0x28, 0x38,
+ 0x2c, 0x3c, 0x29, 0x39, 0x2d, 0x3d, 0x02, 0x12,
+ 0x06},
+ {0x16, 0x03, 0x13, 0x07, 0x17, 0x22, 0x32, 0x26,
+ 0x36, 0x23, 0x33, 0x27, 0x37, 0x0a, 0x1a, 0x0e,
+ 0x1e, 0x0b, 0x1b, 0x0f},
+ {0x1f, 0x2a, 0x3a, 0x2e, 0x3e, 0x2b, 0x3b, 0x2f,
+ 0x3f}
+ },
/* VGA_DAC */
- {
- 0x00,0x10,0x04,0x0114,
- {0x11,0x09,0x15,0x2a},
- 0x3a,
- {0x2e,0x3e,0x2b,0x3b,0x2f,0x3f,0x00,0x05,
- 0x08,0x0b,0x0e,0x11,0x14,0x18,0x1c,0x20,
- 0x24,0x28,0x2d,0x32,0x38,0x3f,0x00,0x10,
- 0x1f},
- {0x2f,0x3f,0x1f,0x27,0x2f,0x37,0x3f,0x2d,
- 0x31,0x36,0x3a,0x3f,0x00,0x07,0x0e,0x15,
- 0x1c,0x0e,0x11,0x15},
- {0x18,0x1c,0x14,0x16,0x18,0x1a,0x1c,0x00,
- 0x04}
- },
- {
- 0x08,0x0c,0x10,0x0a08,
- {0x0c,0x0e,0x10,0x0b},
- 0x0c,
- {0x0d,0x0f,0x10,0x10,0x01,0x08,0x00,0x00,
- 0x00,0x00,0x01,0x00,0x02,0x02,0x01,0x00,
- 0x04,0x04,0x01,0x00,0x05,0x02,0x05,0x00,
- 0x06},
- {0x01,0x06,0x05,0x06,0x00,0x08,0x01,0x08,
- 0x00,0x07,0x02,0x07,0x06,0x07,0x00,0x00,
- 0x00,0x00,0x00,0x00},
- {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x00}
- },
+ {
+ 0x00, 0x10, 0x04, 0x0114,
+ {0x11, 0x09, 0x15, 0x2a},
+ 0x3a,
+ {0x2e, 0x3e, 0x2b, 0x3b, 0x2f, 0x3f, 0x00, 0x05,
+ 0x08, 0x0b, 0x0e, 0x11, 0x14, 0x18, 0x1c, 0x20,
+ 0x24, 0x28, 0x2d, 0x32, 0x38, 0x3f, 0x00, 0x10,
+ 0x1f},
+ {0x2f, 0x3f, 0x1f, 0x27, 0x2f, 0x37, 0x3f, 0x2d,
+ 0x31, 0x36, 0x3a, 0x3f, 0x00, 0x07, 0x0e, 0x15,
+ 0x1c, 0x0e, 0x11, 0x15},
+ {0x18, 0x1c, 0x14, 0x16, 0x18, 0x1a, 0x1c, 0x00,
+ 0x04}
+ },
+ {
+ 0x08, 0x0c, 0x10, 0x0a08,
+ {0x0c, 0x0e, 0x10, 0x0b},
+ 0x0c,
+ {0x0d, 0x0f, 0x10, 0x10, 0x01, 0x08, 0x00, 0x00,
+ 0x00, 0x00, 0x01, 0x00, 0x02, 0x02, 0x01, 0x00,
+ 0x04, 0x04, 0x01, 0x00, 0x05, 0x02, 0x05, 0x00,
+ 0x06},
+ {0x01, 0x06, 0x05, 0x06, 0x00, 0x08, 0x01, 0x08,
+ 0x00, 0x07, 0x02, 0x07, 0x06, 0x07, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00}
+ },
/* MD_D */
- {
- 0x28,0x18,0x08,0x2000,
- {0x09,0x0f,0x00,0x06},
- 0x63,
- {0x2d,0x27,0x28,0x90,0x2c,0x80,0xbf,0x1f,
- 0x00,0xc0,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x9c,0x8e,0x8f,0x14,0x00,0x96,0xb9,0xe3,
- 0xff},
- {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,
- 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,
- 0x01,0x00,0x0f,0x00},
- {0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f,
- 0xff}
- },
+ {
+ 0x28, 0x18, 0x08, 0x2000,
+ {0x09, 0x0f, 0x00, 0x06},
+ 0x63,
+ {0x2d, 0x27, 0x28, 0x90, 0x2c, 0x80, 0xbf, 0x1f,
+ 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x9c, 0x8e, 0x8f, 0x14, 0x00, 0x96, 0xb9, 0xe3,
+ 0xff},
+ {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
+ 0x01, 0x00, 0x0f, 0x00},
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f,
+ 0xff}
+ },
/* MD_E */
- {
- 0x50,0x18,0x08,0x4000,
- {0x01,0x0f,0x00,0x06},
- 0x63,
- {0x5f,0x4f,0x50,0x82,0x55,0x81,0xbf,0x1f,
- 0x00,0xc0,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x9c,0x8e,0x8f,0x28,0x00,0x96,0xb9,0xe3,
- 0xff},
- {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,
- 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,
- 0x01,0x00,0x0f,0x00},
- {0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f,
- 0xff}
- },
+ {
+ 0x50, 0x18, 0x08, 0x4000,
+ {0x01, 0x0f, 0x00, 0x06},
+ 0x63,
+ {0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f,
+ 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x9c, 0x8e, 0x8f, 0x28, 0x00, 0x96, 0xb9, 0xe3,
+ 0xff},
+ {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
+ 0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
+ 0x01, 0x00, 0x0f, 0x00},
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f,
+ 0xff}
+ },
/* ExtVGATable */
- {
- 0x00,0x00,0x00,0x0000,
- {0x01,0x0f,0x00,0x0e},
- 0x23,
- {0x5f,0x4f,0x50,0x82,0x54,0x80,0x0b,0x3e,
- 0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00,
- 0xea,0x8c,0xdf,0x28,0x40,0xe7,0x04,0xa3,
- 0xff},
- {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,
- 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,
- 0x01,0x00,0x00,0x00},
- {0x00,0x00,0x00,0x00,0x00,0x40,0x05,0x0f,
- 0xff}
- },
+ {
+ 0x00, 0x00, 0x00, 0x0000,
+ {0x01, 0x0f, 0x00, 0x0e},
+ 0x23,
+ {0x5f, 0x4f, 0x50, 0x82, 0x54, 0x80, 0x0b, 0x3e,
+ 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0xea, 0x8c, 0xdf, 0x28, 0x40, 0xe7, 0x04, 0xa3,
+ 0xff},
+ {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
+ 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
+ 0x01, 0x00, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0f,
+ 0xff}
+ },
/* ROM_SAVEPTR */
- {
- 0x9f,0x3b,0x00,0x00c0,
- {0x00,0x00,0x00,0x00},
- 0x00,
- {0x00,0x00,0x00,0x00,0x00,0x00,0xbb,0x3f,
- 0x00,0xc0,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x00,0x00,0x1a,0x00,0xac,0x3e,0x00,0xc0,
- 0x00},
- {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x00,0x00,0x00,0x00},
- {0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x00}
- },
+ {
+ 0x9f, 0x3b, 0x00, 0x00c0,
+ {0x00, 0x00, 0x00, 0x00},
+ 0x00,
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xbb, 0x3f,
+ 0x00, 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x1a, 0x00, 0xac, 0x3e, 0x00, 0xc0,
+ 0x00},
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00, 0x00, 0x00, 0x00},
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x00}
+ },
/* MD_F */
- {
- 0x50,0x18,0x0e,0x8000,
- {0x01,0x0f,0x00,0x06},
- 0xa2,
- {0x5f,0x4f,0x50,0x82,0x55,0x81,0xbf,0x1f,
- 0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x82,0x84,0x5d,0x28,0x0f,0x63,0xba,0xe3,
- 0xff},
- {0x00,0x08,0x00,0x00,0x18,0x18,0x00,0x00,
- 0x00,0x08,0x00,0x00,0x00,0x18,0x00,0x00,
- 0x0b,0x00,0x05,0x00},
- {0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x05,
- 0xff}
- },
+ {
+ 0x50, 0x18, 0x0e, 0x8000,
+ {0x01, 0x0f, 0x00, 0x06},
+ 0xa2,
+ {0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f,
+ 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x82, 0x84, 0x5d, 0x28, 0x0f, 0x63, 0xba, 0xe3,
+ 0xff},
+ {0x00, 0x08, 0x00, 0x00, 0x18, 0x18, 0x00, 0x00,
+ 0x00, 0x08, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00,
+ 0x0b, 0x00, 0x05, 0x00},
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x05,
+ 0xff}
+ },
/* MD_10 */
- {
- 0x50,0x18,0x0e,0x8000,
- {0x01,0x0f,0x00,0x06},
- 0xa3,
- {0x5f,0x4f,0x50,0x82,0x55,0x81,0xbf,0x1f,
- 0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x82,0x84,0x5d,0x28,0x0f,0x63,0xba,0xe3,
- 0xff},
- {0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07,
- 0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,
- 0x01,0x00,0x0f,0x00},
- {0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f,
- 0xff}
- },
+ {
+ 0x50, 0x18, 0x0e, 0x8000,
+ {0x01, 0x0f, 0x00, 0x06},
+ 0xa3,
+ {0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f,
+ 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x82, 0x84, 0x5d, 0x28, 0x0f, 0x63, 0xba, 0xe3,
+ 0xff},
+ {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07,
+ 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
+ 0x01, 0x00, 0x0f, 0x00},
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f,
+ 0xff}
+ },
/* MD_0_350 */
- {
- 0x28,0x18,0x0e,0x0800,
- {0x09,0x03,0x00,0x02},
- 0xa3,
- {0x2d,0x27,0x28,0x90,0x2b,0xb1,0xbf,0x1f,
- 0x00,0x4d,0x0b,0x0c,0x00,0x00,0x00,0x00,
- 0x83,0x85,0x5d,0x14,0x1f,0x63,0xba,0xa3,
- 0xff},
- {0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07,
- 0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,
- 0x08,0x00,0x0f,0x00},
- {0x00,0x00,0x00,0x00,0x00,0x10,0x0e,0x00,
- 0xff}
- },
+ {
+ 0x28, 0x18, 0x0e, 0x0800,
+ {0x09, 0x03, 0x00, 0x02},
+ 0xa3,
+ {0x2d, 0x27, 0x28, 0x90, 0x2b, 0xb1, 0xbf, 0x1f,
+ 0x00, 0x4d, 0x0b, 0x0c, 0x00, 0x00, 0x00, 0x00,
+ 0x83, 0x85, 0x5d, 0x14, 0x1f, 0x63, 0xba, 0xa3,
+ 0xff},
+ {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07,
+ 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
+ 0x08, 0x00, 0x0f, 0x00},
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0e, 0x00,
+ 0xff}
+ },
/* MD_1_350 */
- {
- 0x28,0x18,0x0e,0x0800,
- {0x09,0x03,0x00,0x02},
- 0xa3,
- {0x2d,0x27,0x28,0x90,0x2b,0xa0,0xbf,0x1f,
- 0x00,0x4d,0x0b,0x0c,0x00,0x00,0x00,0x00,
- 0x83,0x85,0x5d,0x14,0x1f,0x63,0xba,0xa3,
- 0xff},
- {0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07,
- 0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,
- 0x08,0x00,0x0f,0x00},
- {0x00,0x00,0x00,0x00,0x00,0x10,0x0e,0x00,
- 0xff}
- },
+ {
+ 0x28, 0x18, 0x0e, 0x0800,
+ {0x09, 0x03, 0x00, 0x02},
+ 0xa3,
+ {0x2d, 0x27, 0x28, 0x90, 0x2b, 0xa0, 0xbf, 0x1f,
+ 0x00, 0x4d, 0x0b, 0x0c, 0x00, 0x00, 0x00, 0x00,
+ 0x83, 0x85, 0x5d, 0x14, 0x1f, 0x63, 0xba, 0xa3,
+ 0xff},
+ {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07,
+ 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
+ 0x08, 0x00, 0x0f, 0x00},
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0e, 0x00,
+ 0xff}
+ },
/* MD_2_350 */
- {
- 0x50,0x18,0x0e,0x1000,
- {0x01,0x03,0x00,0x02},
- 0xa3,
- {0x5f,0x4f,0x50,0x82,0x55,0x81,0xbf,0x1f,
- 0x00,0x4d,0x0b,0x0c,0x00,0x00,0x00,0x00,
- 0x83,0x85,0x5d,0x28,0x1f,0x63,0xba,0xa3,
- 0xff},
- {0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07,
- 0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,
- 0x08,0x00,0x0f,0x00},
- {0x00,0x00,0x00,0x00,0x00,0x10,0x0e,0x00,
- 0xff}
- },
+ {
+ 0x50, 0x18, 0x0e, 0x1000,
+ {0x01, 0x03, 0x00, 0x02},
+ 0xa3,
+ {0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f,
+ 0x00, 0x4d, 0x0b, 0x0c, 0x00, 0x00, 0x00, 0x00,
+ 0x83, 0x85, 0x5d, 0x28, 0x1f, 0x63, 0xba, 0xa3,
+ 0xff},
+ {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07,
+ 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
+ 0x08, 0x00, 0x0f, 0x00},
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0e, 0x00,
+ 0xff}
+ },
/* MD_3_350 */
- {
- 0x50,0x18,0x0e,0x1000,
- {0x01,0x03,0x00,0x02},
- 0xa3,
- {0x5f,0x4f,0x50,0x82,0x55,0x81,0xbf,0x1f,
- 0x00,0x4d,0x0b,0x0c,0x00,0x00,0x00,0x00,
- 0x83,0x85,0x5d,0x28,0x1f,0x63,0xba,0xa3,
- 0xff},
- {0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07,
- 0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,
- 0x08,0x00,0x0f,0x00},
- {0x00,0x00,0x00,0x00,0x00,0x10,0x0e,0x00,
- 0xff}
- },
+ {
+ 0x50, 0x18, 0x0e, 0x1000,
+ {0x01, 0x03, 0x00, 0x02},
+ 0xa3,
+ {0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f,
+ 0x00, 0x4d, 0x0b, 0x0c, 0x00, 0x00, 0x00, 0x00,
+ 0x83, 0x85, 0x5d, 0x28, 0x1f, 0x63, 0xba, 0xa3,
+ 0xff},
+ {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07,
+ 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
+ 0x08, 0x00, 0x0f, 0x00},
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0e, 0x00,
+ 0xff}
+ },
/* MD_0_1_400 */
- {
- 0x28,0x18,0x10,0x0800,
- {0x08,0x03,0x00,0x02},
- 0x67,
- {0x2d,0x27,0x28,0x90,0x2b,0xb1,0xbf,0x1f,
- 0x00,0x4f,0x0d,0x0e,0x00,0x00,0x00,0x00,
- 0x9c,0x8e,0x8f,0x14,0x1f,0x96,0xb9,0xa3,
- 0xff},
- {0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07,
- 0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,
- 0x0c,0x00,0x0f,0x08},
- {0x00,0x00,0x00,0x00,0x00,0x10,0x0e,0x00,
- 0xff}
- },
+ {
+ 0x28, 0x18, 0x10, 0x0800,
+ {0x08, 0x03, 0x00, 0x02},
+ 0x67,
+ {0x2d, 0x27, 0x28, 0x90, 0x2b, 0xb1, 0xbf, 0x1f,
+ 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00,
+ 0x9c, 0x8e, 0x8f, 0x14, 0x1f, 0x96, 0xb9, 0xa3,
+ 0xff},
+ {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07,
+ 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
+ 0x0c, 0x00, 0x0f, 0x08},
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0e, 0x00,
+ 0xff}
+ },
/* MD_2_3_400 */
- {
- 0x50,0x18,0x10,0x1000,
- {0x00,0x03,0x00,0x02},
- 0x67,
- {0x5f,0x4f,0x50,0x82,0x55,0x81,0xbf,0x1f,
- 0x00,0x4f,0x0d,0x0e,0x00,0x00,0x00,0x00,
- 0x9c,0x8e,0x8f,0x28,0x1f,0x96,0xb9,0xa3,
- 0xff},
- {0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07,
- 0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,
- 0x0c,0x00,0x0f,0x08},
- {0x00,0x00,0x00,0x00,0x00,0x10,0x0e,0x00,
- 0xff}
- },
+ {
+ 0x50, 0x18, 0x10, 0x1000,
+ {0x00, 0x03, 0x00, 0x02},
+ 0x67,
+ {0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f,
+ 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00,
+ 0x9c, 0x8e, 0x8f, 0x28, 0x1f, 0x96, 0xb9, 0xa3,
+ 0xff},
+ {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07,
+ 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
+ 0x0c, 0x00, 0x0f, 0x08},
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0e, 0x00,
+ 0xff}
+ },
/* MD_7_400 */
- {
- 0x50,0x18,0x10,0x1000,
- {0x00,0x03,0x00,0x02},
- 0x66,
- {0x5f,0x4f,0x50,0x82,0x55,0x81,0xbf,0x1f,
- 0x00,0x4f,0x0d,0x0e,0x00,0x00,0x00,0x00,
- 0x9c,0x8e,0x8f,0x28,0x0f,0x96,0xb9,0xa3,
- 0xff},
- {0x00,0x08,0x08,0x08,0x08,0x08,0x08,0x08,
- 0x10,0x18,0x18,0x18,0x18,0x18,0x18,0x18,
- 0x0e,0x00,0x0f,0x08},
- {0x00,0x00,0x00,0x00,0x00,0x10,0x0a,0x00,
- 0xff}
- },
+ {
+ 0x50, 0x18, 0x10, 0x1000,
+ {0x00, 0x03, 0x00, 0x02},
+ 0x66,
+ {0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f,
+ 0x00, 0x4f, 0x0d, 0x0e, 0x00, 0x00, 0x00, 0x00,
+ 0x9c, 0x8e, 0x8f, 0x28, 0x0f, 0x96, 0xb9, 0xa3,
+ 0xff},
+ {0x00, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08,
+ 0x10, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18,
+ 0x0e, 0x00, 0x0f, 0x08},
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x0a, 0x00,
+ 0xff}
+ },
/* MD_11 */
- {
- 0x50,0x1d,0x10,0xa000,
- {0x01,0x0f,0x00,0x06},
- 0xe3,
- {0x5f,0x4f,0x50,0x82,0x55,0x81,0x0b,0x3e,
- 0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00,
- 0xe9,0x8b,0xdf,0x28,0x00,0xe7,0x04,0xc3,
- 0xff},
- {0x00,0x3f,0x3f,0x3f,0x3f,0x3f,0x3f,0x3f,
- 0x3f,0x3f,0x3f,0x3f,0x3f,0x3f,0x3f,0x3f,
- 0x01,0x00,0x0f,0x00},
- {0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x01,
- 0xff}
- },
+ {
+ 0x50, 0x1d, 0x10, 0xa000,
+ {0x01, 0x0f, 0x00, 0x06},
+ 0xe3,
+ {0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0x0b, 0x3e,
+ 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0xe9, 0x8b, 0xdf, 0x28, 0x00, 0xe7, 0x04, 0xc3,
+ 0xff},
+ {0x00, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f,
+ 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f, 0x3f,
+ 0x01, 0x00, 0x0f, 0x00},
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x01,
+ 0xff}
+ },
/* ExtEGATable */
- {
- 0x50,0x1d,0x10,0xa000,
- {0x01,0x0f,0x00,0x06},
- 0xe3,
- {0x5f,0x4f,0x50,0x82,0x55,0x81,0x0b,0x3e,
- 0x00,0x40,0x00,0x00,0x00,0x00,0x00,0x00,
- 0xe9,0x8b,0xdf,0x28,0x00,0xe7,0x04,0xe3,
- 0xff},
- {0x00,0x01,0x02,0x03,0x04,0x05,0x14,0x07,
- 0x38,0x39,0x3a,0x3b,0x3c,0x3d,0x3e,0x3f,
- 0x01,0x00,0x0f,0x00},
- {0x00,0x00,0x00,0x00,0x00,0x00,0x05,0x0f,
- 0xff}
- },
+ {
+ 0x50, 0x1d, 0x10, 0xa000,
+ {0x01, 0x0f, 0x00, 0x06},
+ 0xe3,
+ {0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0x0b, 0x3e,
+ 0x00, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0xe9, 0x8b, 0xdf, 0x28, 0x00, 0xe7, 0x04, 0xe3,
+ 0xff},
+ {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x14, 0x07,
+ 0x38, 0x39, 0x3a, 0x3b, 0x3c, 0x3d, 0x3e, 0x3f,
+ 0x01, 0x00, 0x0f, 0x00},
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x05, 0x0f,
+ 0xff}
+ },
/* MD_13 */
- {
- 0x28,0x18,0x08,0x2000,
- {0x01,0x0f,0x00,0x0e},
- 0x63,
- {0x5f,0x4f,0x50,0x82,0x55,0x81,0xbf,0x1f,
- 0x00,0x41,0x00,0x00,0x00,0x00,0x00,0x00,
- 0x9c,0x8e,0x8f,0x28,0x40,0x96,0xb9,0xa3,
- 0xff},
- {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,
- 0x08,0x09,0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,
- 0x41,0x00,0x0f,0x00},
- {0x00,0x00,0x00,0x00,0x00,0x40,0x05,0x0f,
- 0xff}
- }
+ {
+ 0x28, 0x18, 0x08, 0x2000,
+ {0x01, 0x0f, 0x00, 0x0e},
+ 0x63,
+ {0x5f, 0x4f, 0x50, 0x82, 0x55, 0x81, 0xbf, 0x1f,
+ 0x00, 0x41, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+ 0x9c, 0x8e, 0x8f, 0x28, 0x40, 0x96, 0xb9, 0xa3,
+ 0xff},
+ {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
+ 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
+ 0x41, 0x00, 0x0f, 0x00},
+ {0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x05, 0x0f,
+ 0xff}
+ }
};
-static struct XGI_TimingHStruct XGI_TimingH[] =
-{{{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}}};
-
-static struct XGI_TimingVStruct XGI_TimingV[] =
-{{{0x00,0x00,0x00,0x00,0x00,0x00,0x00}}};
-
-static struct XGI_XG21CRT1Struct XGI_UpdateCRT1Table[] =
-{
- {0x01,0x27,0x91,0x8f,0xc0}, /* 00 */
- {0x03,0x4f,0x83,0x8f,0xc0}, /* 01 */
- {0x05,0x27,0x91,0x8f,0xc0}, /* 02 */
- {0x06,0x4f,0x83,0x8f,0xc0}, /* 03 */
- {0x07,0x4f,0x83,0x8f,0xc0}, /* 04 */
- {0x0d,0x27,0x91,0x8f,0xc0}, /* 05 */
- {0x0e,0x4f,0x83,0x8f,0xc0}, /* 06 */
- {0x0f,0x4f,0x83,0x5d,0xc0}, /* 07 */
- {0x10,0x4f,0x83,0x5d,0xc0}, /* 08 */
- {0x11,0x4f,0x83,0xdf,0x0c}, /* 09 */
- {0x12,0x4f,0x83,0xdf,0x0c}, /* 10 */
- {0x13,0x4f,0x83,0x8f,0xc0}, /* 11 */
- {0x2e,0x4f,0x83,0xdf,0x0c}, /* 12 */
- {0x2e,0x4f,0x87,0xdf,0xc0}, /* 13 */
- {0x2f,0x4f,0x83,0x8f,0xc0}, /* 14 */
- {0x50,0x27,0x91,0xdf,0x0c}, /* 15 */
- {0x59,0x27,0x91,0x8f,0xc0} /* 16 */
+static struct XGI_TimingHStruct XGI_TimingH[] = {
+ { {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }
};
-static struct XGI_CRT1TableStruct XGI_CRT1Table[] =
-{
- {{0x2d,0x28,0x90,0x2c,0x90,0x00,0x04,0x00,
- 0xbf,0x1f,0x9c,0x8e,0x96,0xb9,0x30}}, /* 0x0 */
- {{0x2d,0x28,0x90,0x2c,0x90,0x00,0x04,0x00,
- 0x0b,0x3e,0xe9,0x8b,0xe7,0x04,0x00}}, /* 0x1 */
- {{0x3D,0x31,0x81,0x37,0x1F,0x00,0x05,0x00,
- 0x72,0xF0,0x58,0x8C,0x57,0x73,0xA0}}, /* 0x2 */
- {{0x4F,0x3F,0x93,0x45,0x0D,0x00,0x01,0x00,
- 0x24,0xF5,0x02,0x88,0xFF,0x25,0x90}}, /* 0x3 */
- {{0x5F,0x50,0x82,0x55,0x81,0x00,0x05,0x00,
- 0xBF,0x1F,0x9C,0x8E,0x96,0xB9,0x30}}, /* 0x4 */
- {{0x5F,0x50,0x82,0x55,0x81,0x00,0x05,0x00,
- 0x0B,0x3E,0xE9,0x8B,0xE7,0x04,0x00}}, /* 0x5 */
- {{0x63,0x50,0x86,0x56,0x9B,0x00,0x01,0x00,
- 0x06,0x3E,0xE8,0x8B,0xE7,0xFF,0x10}}, /* 0x6 */
- {{0x64,0x4F,0x88,0x55,0x9D,0x00,0x01,0x00,
- 0xF2,0x1F,0xE0,0x83,0xDF,0xF3,0x10}}, /* 0x7 */
- {{0x63,0x4F,0x87,0x5A,0x81,0x00,0x05,0x00,
- 0xFB,0x1F,0xE0,0x83,0xDF,0xFC,0x10}}, /* 0x8 */
- {{0x65,0x4F,0x89,0x58,0x80,0x00,0x05,0x60,
- 0xFB,0x1F,0xE0,0x83,0xDF,0xFC,0x80}}, /* 0x9 */
- {{0x65,0x4F,0x89,0x58,0x80,0x00,0x05,0x60,
- 0x01,0x3E,0xE0,0x83,0xDF,0x02,0x80}}, /* 0xa */
- {{0x67,0x4F,0x8B,0x58,0x81,0x00,0x05,0x60,
- 0x0D,0x3E,0xE0,0x83,0xDF,0x0E,0x90}}, /* 0xb */
- {{0x65,0x4F,0x89,0x57,0x9F,0x00,0x01,0x00,
- 0xFB,0x1F,0xE6,0x8A,0xDF,0xFC,0x10}}, /* 0xc */
- {{0x7B,0x63,0x9F,0x6A,0x93,0x00,0x05,0x00, /* ; 0D (800x600,56Hz) */
- 0x6F,0xF0,0x58,0x8A,0x57,0x70,0xA0}}, /* ; (VCLK 36.0MHz) */
- {{0x7F,0x63,0x83,0x6C,0x1C,0x00,0x06,0x00, /* ; 0E (800x600,60Hz) */
- 0x72,0xF0,0x58,0x8C,0x57,0x73,0xA0}}, /* ; (VCLK 40.0MHz) */
- {{0x7D,0x63,0x81,0x6E,0x1D,0x00,0x06,0x00, /* ; 0F (800x600,72Hz) */
- 0x98,0xF0,0x7C,0x82,0x57,0x99,0x80}}, /* ; (VCLK 50.0MHz) */
- {{0x7F,0x63,0x83,0x69,0x13,0x00,0x06,0x00, /* ; 10 (800x600,75Hz) */
- 0x6F,0xF0,0x58,0x8B,0x57,0x70,0xA0}}, /* ; (VCLK 49.5MHz) */
- {{0x7E,0x63,0x82,0x6B,0x13,0x00,0x06,0x00, /* ; 11 (800x600,85Hz) */
- 0x75,0xF0,0x58,0x8B,0x57,0x76,0xA0}}, /* ; (VCLK 56.25MHz) */
- {{0x81,0x63,0x85,0x6D,0x18,0x00,0x06,0x60, /* ; 12 (800x600,100Hz) */
- 0x7A,0xF0,0x58,0x8B,0x57,0x7B,0xA0}}, /* ; (VCLK 75.8MHz) */
- {{0x83,0x63,0x87,0x6E,0x19,0x00,0x06,0x60, /* ; 13 (800x600,120Hz) */
- 0x81,0xF0,0x58,0x8B,0x57,0x82,0xA0}}, /* ; (VCLK 79.411MHz) */
- {{0x85,0x63,0x89,0x6F,0x1A,0x00,0x06,0x60, /* ; 14 (800x600,160Hz) */
- 0x91,0xF0,0x58,0x8B,0x57,0x92,0xA0}}, /* ; (VCLK 105.822MHz) */
- {{0x99,0x7F,0x9D,0x84,0x1A,0x00,0x02,0x00,
- 0x96,0x1F,0x7F,0x83,0x7F,0x97,0x10}}, /* 0x15 */
- {{0xA3,0x7F,0x87,0x86,0x97,0x00,0x02,0x00,
- 0x24,0xF5,0x02,0x88,0xFF,0x25,0x90}}, /* 0x16 */
- {{0xA1,0x7F,0x85,0x86,0x97,0x00,0x02,0x00,
- 0x24,0xF5,0x02,0x88,0xFF,0x25,0x90}}, /* 0x17 */
- {{0x9F,0x7F,0x83,0x85,0x91,0x00,0x02,0x00,
- 0x1E,0xF5,0x00,0x83,0xFF,0x1F,0x90}}, /* 0x18 */
- {{0xA7,0x7F,0x8B,0x89,0x95,0x00,0x02,0x00,
- 0x26,0xF5,0x00,0x83,0xFF,0x27,0x90}}, /* 0x19 */
- {{0xA9,0x7F,0x8D,0x8C,0x9A,0x00,0x02,0x62,
- 0x2C,0xF5,0x00,0x83,0xFF,0x2D,0x14}}, /* 0x1a */
- {{0xAB,0x7F,0x8F,0x8D,0x9B,0x00,0x02,0x62,
- 0x35,0xF5,0x00,0x83,0xFF,0x36,0x14}}, /* 0x1b */
- {{0xCF,0x9F,0x93,0xB2,0x01,0x00,0x03,0x00,
- 0x14,0xBA,0x00,0x83,0xFF,0x15,0x00}}, /* 0x1c */
- {{0xCE,0x9F,0x92,0xA9,0x17,0x00,0x07,0x00,
- 0x28,0x5A,0x00,0x83,0xFF,0x29,0x89}}, /* 0x1d */
- {{0xCE,0x9F,0x92,0xA5,0x17,0x00,0x07,0x00,
- 0x28,0x5A,0x00,0x83,0xFF,0x29,0x89}}, /* 0x1e */
- {{0xD3,0x9F,0x97,0xAB,0x1F,0x00,0x07,0x00,
- 0x2E,0x5A,0x00,0x83,0xFF,0x2F,0x89}}, /* 0x1f */
- {{0x09,0xC7,0x8D,0xD3,0x0B,0x01,0x04,0x00,
- 0xE0,0x10,0xB0,0x83,0xAF,0xE1,0x2F}}, /* 0x20 */
- {{0x09,0xC7,0x8D,0xD3,0x0B,0x01,0x04,0x00,
- 0xE0,0x10,0xB0,0x83,0xAF,0xE1,0x2F}}, /* 0x21 */
- {{0x09,0xC7,0x8D,0xD3,0x0B,0x01,0x04,0x00,
- 0xE0,0x10,0xB0,0x83,0xAF,0xE1,0x2F}}, /* 0x22 */
- {{0x09,0xC7,0x8D,0xD3,0x0B,0x01,0x04,0x00,
- 0xE0,0x10,0xB0,0x83,0xAF,0xE1,0x2F}}, /* 0x23 */
- {{0x09,0xC7,0x8D,0xD3,0x0B,0x01,0x04,0x00,
- 0xE0,0x10,0xB0,0x83,0xAF,0xE1,0x2F}}, /* 0x24 */
- {{0x09,0xC7,0x8D,0xD3,0x0B,0x01,0x04,0x00,
- 0xE0,0x10,0xB0,0x83,0xAF,0xE1,0x2F}}, /* 0x25 */
- {{0x09,0xC7,0x8D,0xD3,0x0B,0x01,0x04,0x00,
- 0xE0,0x10,0xB0,0x83,0xAF,0xE1,0x2F}}, /* 0x26 */
- {{0x40,0xEF,0x84,0x03,0x1D,0x41,0x01,0x00,
- 0xDA,0x1F,0xA0,0x83,0x9F,0xDB,0x1F}}, /* 0x27 */
- {{0x43,0xEF,0x87,0x06,0x00,0x41,0x05,0x62,
- 0xD4,0x1F,0xA0,0x83,0x9F,0xD5,0x9F}}, /* 0x28 */
- {{0x45,0xEF,0x89,0x07,0x01,0x41,0x05,0x62,
- 0xD9,0x1F,0xA0,0x83,0x9F,0xDA,0x9F}}, /* 0x29 */
- {{0x40,0xEF,0x84,0x03,0x1D,0x41,0x01,0x00,
- 0xDA,0x1F,0xA0,0x83,0x9F,0xDB,0x1F}}, /* 0x2a */
- {{0x40,0xEF,0x84,0x03,0x1D,0x41,0x01,0x00,
- 0xDA,0x1F,0xA0,0x83,0x9F,0xDB,0x1F}}, /* 0x2b */
- {{0x40,0xEF,0x84,0x03,0x1D,0x41,0x01,0x00,
- 0xDA,0x1F,0xA0,0x83,0x9F,0xDB,0x1F}}, /* 0x2c */
- {{0x59,0xFF,0x9D,0x17,0x13,0x41,0x05,0x44,
- 0x33,0xBA,0x00,0x83,0xFF,0x34,0x0F}}, /* 0x2d */
- {{0x5B,0xFF,0x9F,0x18,0x14,0x41,0x05,0x44,
- 0x38,0xBA,0x00,0x83,0xFF,0x39,0x0F}}, /* 0x2e */
- {{0x5B,0xFF,0x9F,0x18,0x14,0x41,0x05,0x44,
- 0x3D,0xBA,0x00,0x83,0xFF,0x3E,0x0F}}, /* 0x2f */
- {{0x5D,0xFF,0x81,0x19,0x95,0x41,0x05,0x44,
- 0x41,0xBA,0x00,0x84,0xFF,0x42,0x0F}}, /* 0x30 */
- {{0x55,0xFF,0x99,0x0D,0x0C,0x41,0x05,0x00,
- 0x3E,0xBA,0x00,0x84,0xFF,0x3F,0x0F}}, /* 0x31 */
- {{0x7F,0x63,0x83,0x6C,0x1C,0x00,0x06,0x00,
- 0x72,0xBA,0x27,0x8B,0xDF,0x73,0x80}}, /* 0x32 */
- {{0x7F,0x63,0x83,0x69,0x13,0x00,0x06,0x00,
- 0x6F,0xBA,0x26,0x89,0xDF,0x6F,0x80}}, /* 0x33 */
- {{0x7F,0x63,0x82,0x6B,0x13,0x00,0x06,0x00,
- 0x75,0xBA,0x29,0x8C,0xDF,0x75,0x80}}, /* 0x34 */
- {{0xA3,0x7F,0x87,0x86,0x97,0x00,0x02,0x00,
- 0x24,0xF1,0xAF,0x85,0x3F,0x25,0xB0}}, /* 0x35 */
- {{0x9F,0x7F,0x83,0x85,0x91,0x00,0x02,0x00,
- 0x1E,0xF1,0xAD,0x81,0x3F,0x1F,0xB0}}, /* 0x36 */
- {{0xA7,0x7F,0x88,0x89,0x15,0x00,0x02,0x00,
- 0x26,0xF1,0xB1,0x85,0x3F,0x27,0xB0}}, /* 0x37 */
- {{0xCE,0x9F,0x92,0xA9,0x17,0x00,0x07,0x00,
- 0x28,0xC4,0x7A,0x8E,0xCF,0x29,0xA1}}, /* 0x38 */
- {{0xCE,0x9F,0x92,0xA5,0x17,0x00,0x07,0x00,
- 0x28,0xD4,0x7A,0x8E,0xCF,0x29,0xA1}}, /* 0x39 */
- {{0xD3,0x9F,0x97,0xAB,0x1F,0x00,0x07,0x00,
- 0x2E,0xD4,0x7D,0x81,0xCF,0x2F,0xA1}}, /* 0x3a */
- {{0xDC,0x9F,0x00,0xAB,0x19,0x00,0x07,0x00,
- 0xE6,0xEF,0xC0,0xC3,0xBF,0xE7,0x90}}, /* 0x3b */
- {{0x6B,0x59,0x8F,0x5E,0x8C,0x00,0x05,0x00,
- 0x0B,0x3E,0xE9,0x8B,0xE7,0x04,0x00}}, /* 0x3c */
- {{0x7B,0x63,0x9F,0x6A,0x93,0x00,0x05,0x00,
- 0x6F,0xF0,0x58,0x8A,0x57,0x70,0xA0}}, /* 0x3d */
- {{0x86,0x6A,0x8a,0x74,0x06,0x00,0x02,0x00,
- 0x8c,0x15,0x4f,0x83,0xef,0x8d,0x30}}, /* 0x3e */
- {{0x81,0x6A,0x85,0x70,0x00,0x00,0x02,0x00,
- 0x0f,0x3e,0xeb,0x8e,0xdf,0x10,0x00}}, /* 0x3f */
- {{0xCE,0x9F,0x92,0xA9,0x17,0x00,0x07,0x00,
- 0x20,0xF5,0x03,0x88,0xFF,0x21,0x90}}, /* 0x40 */
- {{0xE6,0xAE,0x8A,0xBD,0x90,0x00,0x03,0x00,
- 0x3D,0x10,0x1A,0x8D,0x19,0x3E,0x2F}}, /* 0x41 */
- {{0xB9,0x8F,0x9D,0x9B,0x8A,0x00,0x06,0x00,
- 0x7D,0xFF,0x60,0x83,0x5F,0x7E,0x90}}, /* 0x42 */
- {{0xC3,0x8F,0x87,0x9B,0x0B,0x00,0x07,0x00,
- 0x82,0xFF,0x60,0x83,0x5F,0x83,0x90}}, /* 0x43 */
- {{0xAD,0x7F,0x91,0x8E,0x9C,0x00,0x02,0x82,
- 0x49,0xF5,0x00,0x83,0xFF,0x4A,0x90}}, /* 0x44 */
- {{0xCD,0x9F,0x91,0xA7,0x19,0x00,0x07,0x60,
- 0xE6,0xFF,0xC0,0x83,0xBF,0xE7,0x90}}, /* 0x45 */
- {{0xD3,0x9F,0x97,0xAB,0x1F,0x00,0x07,0x60,
- 0xF1,0xFF,0xC0,0x83,0xBF,0xF2,0x90}}, /* 0x46 */
- {{0xD7,0x9F,0x9B,0xAC,0x1E,0x00,0x07,0x00,
- 0x03,0xDE,0xC0,0x84,0xBF,0x04,0x90}} /* 0x47 */
+static struct XGI_TimingVStruct XGI_TimingV[] = {
+ { {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00} }
+};
+
+static struct XGI_XG21CRT1Struct XGI_UpdateCRT1Table[] = {
+ {0x01, 0x27, 0x91, 0x8f, 0xc0}, /* 00 */
+ {0x03, 0x4f, 0x83, 0x8f, 0xc0}, /* 01 */
+ {0x05, 0x27, 0x91, 0x8f, 0xc0}, /* 02 */
+ {0x06, 0x4f, 0x83, 0x8f, 0xc0}, /* 03 */
+ {0x07, 0x4f, 0x83, 0x8f, 0xc0}, /* 04 */
+ {0x0d, 0x27, 0x91, 0x8f, 0xc0}, /* 05 */
+ {0x0e, 0x4f, 0x83, 0x8f, 0xc0}, /* 06 */
+ {0x0f, 0x4f, 0x83, 0x5d, 0xc0}, /* 07 */
+ {0x10, 0x4f, 0x83, 0x5d, 0xc0}, /* 08 */
+ {0x11, 0x4f, 0x83, 0xdf, 0x0c}, /* 09 */
+ {0x12, 0x4f, 0x83, 0xdf, 0x0c}, /* 10 */
+ {0x13, 0x4f, 0x83, 0x8f, 0xc0}, /* 11 */
+ {0x2e, 0x4f, 0x83, 0xdf, 0x0c}, /* 12 */
+ {0x2e, 0x4f, 0x87, 0xdf, 0xc0}, /* 13 */
+ {0x2f, 0x4f, 0x83, 0x8f, 0xc0}, /* 14 */
+ {0x50, 0x27, 0x91, 0xdf, 0x0c}, /* 15 */
+ {0x59, 0x27, 0x91, 0x8f, 0xc0} /* 16 */
+};
+
+static struct XGI_CRT1TableStruct XGI_CRT1Table[] = {
+ { {0x2d, 0x28, 0x90, 0x2c, 0x90, 0x00, 0x04, 0x00,
+ 0xbf, 0x1f, 0x9c, 0x8e, 0x96, 0xb9, 0x30} }, /* 0x0 */
+ { {0x2d, 0x28, 0x90, 0x2c, 0x90, 0x00, 0x04, 0x00,
+ 0x0b, 0x3e, 0xe9, 0x8b, 0xe7, 0x04, 0x00} }, /* 0x1 */
+ { {0x3D, 0x31, 0x81, 0x37, 0x1F, 0x00, 0x05, 0x00,
+ 0x72, 0xF0, 0x58, 0x8C, 0x57, 0x73, 0xA0} }, /* 0x2 */
+ { {0x4F, 0x3F, 0x93, 0x45, 0x0D, 0x00, 0x01, 0x00,
+ 0x24, 0xF5, 0x02, 0x88, 0xFF, 0x25, 0x90} }, /* 0x3 */
+ { {0x5F, 0x50, 0x82, 0x55, 0x81, 0x00, 0x05, 0x00,
+ 0xBF, 0x1F, 0x9C, 0x8E, 0x96, 0xB9, 0x30} }, /* 0x4 */
+ { {0x5F, 0x50, 0x82, 0x55, 0x81, 0x00, 0x05, 0x00,
+ 0x0B, 0x3E, 0xE9, 0x8B, 0xE7, 0x04, 0x00} }, /* 0x5 */
+ { {0x63, 0x50, 0x86, 0x56, 0x9B, 0x00, 0x01, 0x00,
+ 0x06, 0x3E, 0xE8, 0x8B, 0xE7, 0xFF, 0x10} }, /* 0x6 */
+ { {0x64, 0x4F, 0x88, 0x55, 0x9D, 0x00, 0x01, 0x00,
+ 0xF2, 0x1F, 0xE0, 0x83, 0xDF, 0xF3, 0x10} }, /* 0x7 */
+ { {0x63, 0x4F, 0x87, 0x5A, 0x81, 0x00, 0x05, 0x00,
+ 0xFB, 0x1F, 0xE0, 0x83, 0xDF, 0xFC, 0x10} }, /* 0x8 */
+ { {0x65, 0x4F, 0x89, 0x58, 0x80, 0x00, 0x05, 0x60,
+ 0xFB, 0x1F, 0xE0, 0x83, 0xDF, 0xFC, 0x80} }, /* 0x9 */
+ { {0x65, 0x4F, 0x89, 0x58, 0x80, 0x00, 0x05, 0x60,
+ 0x01, 0x3E, 0xE0, 0x83, 0xDF, 0x02, 0x80} }, /* 0xa */
+ { {0x67, 0x4F, 0x8B, 0x58, 0x81, 0x00, 0x05, 0x60,
+ 0x0D, 0x3E, 0xE0, 0x83, 0xDF, 0x0E, 0x90} }, /* 0xb */
+ { {0x65, 0x4F, 0x89, 0x57, 0x9F, 0x00, 0x01, 0x00,
+ 0xFB, 0x1F, 0xE6, 0x8A, 0xDF, 0xFC, 0x10} }, /* 0xc */
+ { {0x7B, 0x63, 0x9F, 0x6A, 0x93, 0x00, 0x05, 0x00, /* ;
+ 0D (800x600,56Hz) */
+ 0x6F, 0xF0, 0x58, 0x8A, 0x57, 0x70, 0xA0} }, /* ;
+ (VCLK 36.0MHz) */
+ { {0x7F, 0x63, 0x83, 0x6C, 0x1C, 0x00, 0x06, 0x00, /* ;
+ 0E (800x600,60Hz) */
+ 0x72, 0xF0, 0x58, 0x8C, 0x57, 0x73, 0xA0} }, /* ;
+ (VCLK 40.0MHz) */
+ { {0x7D, 0x63, 0x81, 0x6E, 0x1D, 0x00, 0x06, 0x00, /* ;
+ 0F (800x600,72Hz) */
+ 0x98, 0xF0, 0x7C, 0x82, 0x57, 0x99, 0x80} }, /* ;
+ (VCLK 50.0MHz) */
+ { {0x7F, 0x63, 0x83, 0x69, 0x13, 0x00, 0x06, 0x00, /* ;
+ 10 (800x600,75Hz) */
+ 0x6F, 0xF0, 0x58, 0x8B, 0x57, 0x70, 0xA0} }, /* ;
+ (VCLK 49.5MHz) */
+ { {0x7E, 0x63, 0x82, 0x6B, 0x13, 0x00, 0x06, 0x00, /* ;
+ 11 (800x600,85Hz) */
+ 0x75, 0xF0, 0x58, 0x8B, 0x57, 0x76, 0xA0} }, /* ;
+ (VCLK 56.25MHz) */
+ { {0x81, 0x63, 0x85, 0x6D, 0x18, 0x00, 0x06, 0x60, /* ;
+ 12 (800x600,100Hz) */
+ 0x7A, 0xF0, 0x58, 0x8B, 0x57, 0x7B, 0xA0} }, /* ;
+ (VCLK 75.8MHz) */
+ { {0x83, 0x63, 0x87, 0x6E, 0x19, 0x00, 0x06, 0x60, /* ;
+ 13 (800x600,120Hz) */
+ 0x81, 0xF0, 0x58, 0x8B, 0x57, 0x82, 0xA0} }, /* ;
+ (VCLK 79.411MHz) */
+ { {0x85, 0x63, 0x89, 0x6F, 0x1A, 0x00, 0x06, 0x60, /* ;
+ 14 (800x600,160Hz) */
+ 0x91, 0xF0, 0x58, 0x8B, 0x57, 0x92, 0xA0} }, /* ;
+ (VCLK 105.822MHz) */
+ { {0x99, 0x7F, 0x9D, 0x84, 0x1A, 0x00, 0x02, 0x00,
+ 0x96, 0x1F, 0x7F, 0x83, 0x7F, 0x97, 0x10} }, /* 0x15 */
+ { {0xA3, 0x7F, 0x87, 0x86, 0x97, 0x00, 0x02, 0x00,
+ 0x24, 0xF5, 0x02, 0x88, 0xFF, 0x25, 0x90} }, /* 0x16 */
+ { {0xA1, 0x7F, 0x85, 0x86, 0x97, 0x00, 0x02, 0x00,
+ 0x24, 0xF5, 0x02, 0x88, 0xFF, 0x25, 0x90} }, /* 0x17 */
+ { {0x9F, 0x7F, 0x83, 0x85, 0x91, 0x00, 0x02, 0x00,
+ 0x1E, 0xF5, 0x00, 0x83, 0xFF, 0x1F, 0x90} }, /* 0x18 */
+ { {0xA7, 0x7F, 0x8B, 0x89, 0x95, 0x00, 0x02, 0x00,
+ 0x26, 0xF5, 0x00, 0x83, 0xFF, 0x27, 0x90} }, /* 0x19 */
+ { {0xA9, 0x7F, 0x8D, 0x8C, 0x9A, 0x00, 0x02, 0x62,
+ 0x2C, 0xF5, 0x00, 0x83, 0xFF, 0x2D, 0x14} }, /* 0x1a */
+ { {0xAB, 0x7F, 0x8F, 0x8D, 0x9B, 0x00, 0x02, 0x62,
+ 0x35, 0xF5, 0x00, 0x83, 0xFF, 0x36, 0x14} }, /* 0x1b */
+ { {0xCF, 0x9F, 0x93, 0xB2, 0x01, 0x00, 0x03, 0x00,
+ 0x14, 0xBA, 0x00, 0x83, 0xFF, 0x15, 0x00} }, /* 0x1c */
+ { {0xCE, 0x9F, 0x92, 0xA9, 0x17, 0x00, 0x07, 0x00,
+ 0x28, 0x5A, 0x00, 0x83, 0xFF, 0x29, 0x89} }, /* 0x1d */
+ { {0xCE, 0x9F, 0x92, 0xA5, 0x17, 0x00, 0x07, 0x00,
+ 0x28, 0x5A, 0x00, 0x83, 0xFF, 0x29, 0x89} }, /* 0x1e */
+ { {0xD3, 0x9F, 0x97, 0xAB, 0x1F, 0x00, 0x07, 0x00,
+ 0x2E, 0x5A, 0x00, 0x83, 0xFF, 0x2F, 0x89} }, /* 0x1f */
+ { {0x09, 0xC7, 0x8D, 0xD3, 0x0B, 0x01, 0x04, 0x00,
+ 0xE0, 0x10, 0xB0, 0x83, 0xAF, 0xE1, 0x2F} }, /* 0x20 */
+ { {0x09, 0xC7, 0x8D, 0xD3, 0x0B, 0x01, 0x04, 0x00,
+ 0xE0, 0x10, 0xB0, 0x83, 0xAF, 0xE1, 0x2F} }, /* 0x21 */
+ { {0x09, 0xC7, 0x8D, 0xD3, 0x0B, 0x01, 0x04, 0x00,
+ 0xE0, 0x10, 0xB0, 0x83, 0xAF, 0xE1, 0x2F} }, /* 0x22 */
+ { {0x09, 0xC7, 0x8D, 0xD3, 0x0B, 0x01, 0x04, 0x00,
+ 0xE0, 0x10, 0xB0, 0x83, 0xAF, 0xE1, 0x2F} }, /* 0x23 */
+ { {0x09, 0xC7, 0x8D, 0xD3, 0x0B, 0x01, 0x04, 0x00,
+ 0xE0, 0x10, 0xB0, 0x83, 0xAF, 0xE1, 0x2F} }, /* 0x24 */
+ { {0x09, 0xC7, 0x8D, 0xD3, 0x0B, 0x01, 0x04, 0x00,
+ 0xE0, 0x10, 0xB0, 0x83, 0xAF, 0xE1, 0x2F} }, /* 0x25 */
+ { {0x09, 0xC7, 0x8D, 0xD3, 0x0B, 0x01, 0x04, 0x00,
+ 0xE0, 0x10, 0xB0, 0x83, 0xAF, 0xE1, 0x2F} }, /* 0x26 */
+ { {0x40, 0xEF, 0x84, 0x03, 0x1D, 0x41, 0x01, 0x00,
+ 0xDA, 0x1F, 0xA0, 0x83, 0x9F, 0xDB, 0x1F} }, /* 0x27 */
+ { {0x43, 0xEF, 0x87, 0x06, 0x00, 0x41, 0x05, 0x62,
+ 0xD4, 0x1F, 0xA0, 0x83, 0x9F, 0xD5, 0x9F} }, /* 0x28 */
+ { {0x45, 0xEF, 0x89, 0x07, 0x01, 0x41, 0x05, 0x62,
+ 0xD9, 0x1F, 0xA0, 0x83, 0x9F, 0xDA, 0x9F} }, /* 0x29 */
+ { {0x40, 0xEF, 0x84, 0x03, 0x1D, 0x41, 0x01, 0x00,
+ 0xDA, 0x1F, 0xA0, 0x83, 0x9F, 0xDB, 0x1F} }, /* 0x2a */
+ { {0x40, 0xEF, 0x84, 0x03, 0x1D, 0x41, 0x01, 0x00,
+ 0xDA, 0x1F, 0xA0, 0x83, 0x9F, 0xDB, 0x1F} }, /* 0x2b */
+ { {0x40, 0xEF, 0x84, 0x03, 0x1D, 0x41, 0x01, 0x00,
+ 0xDA, 0x1F, 0xA0, 0x83, 0x9F, 0xDB, 0x1F} }, /* 0x2c */
+ { {0x59, 0xFF, 0x9D, 0x17, 0x13, 0x41, 0x05, 0x44,
+ 0x33, 0xBA, 0x00, 0x83, 0xFF, 0x34, 0x0F} }, /* 0x2d */
+ { {0x5B, 0xFF, 0x9F, 0x18, 0x14, 0x41, 0x05, 0x44,
+ 0x38, 0xBA, 0x00, 0x83, 0xFF, 0x39, 0x0F} }, /* 0x2e */
+ { {0x5B, 0xFF, 0x9F, 0x18, 0x14, 0x41, 0x05, 0x44,
+ 0x3D, 0xBA, 0x00, 0x83, 0xFF, 0x3E, 0x0F} }, /* 0x2f */
+ { {0x5D, 0xFF, 0x81, 0x19, 0x95, 0x41, 0x05, 0x44,
+ 0x41, 0xBA, 0x00, 0x84, 0xFF, 0x42, 0x0F} }, /* 0x30 */
+ { {0x55, 0xFF, 0x99, 0x0D, 0x0C, 0x41, 0x05, 0x00,
+ 0x3E, 0xBA, 0x00, 0x84, 0xFF, 0x3F, 0x0F} }, /* 0x31 */
+ { {0x7F, 0x63, 0x83, 0x6C, 0x1C, 0x00, 0x06, 0x00,
+ 0x72, 0xBA, 0x27, 0x8B, 0xDF, 0x73, 0x80} }, /* 0x32 */
+ { {0x7F, 0x63, 0x83, 0x69, 0x13, 0x00, 0x06, 0x00,
+ 0x6F, 0xBA, 0x26, 0x89, 0xDF, 0x6F, 0x80} }, /* 0x33 */
+ { {0x7F, 0x63, 0x82, 0x6B, 0x13, 0x00, 0x06, 0x00,
+ 0x75, 0xBA, 0x29, 0x8C, 0xDF, 0x75, 0x80} }, /* 0x34 */
+ { {0xA3, 0x7F, 0x87, 0x86, 0x97, 0x00, 0x02, 0x00,
+ 0x24, 0xF1, 0xAF, 0x85, 0x3F, 0x25, 0xB0} }, /* 0x35 */
+ { {0x9F, 0x7F, 0x83, 0x85, 0x91, 0x00, 0x02, 0x00,
+ 0x1E, 0xF1, 0xAD, 0x81, 0x3F, 0x1F, 0xB0} }, /* 0x36 */
+ { {0xA7, 0x7F, 0x88, 0x89, 0x15, 0x00, 0x02, 0x00,
+ 0x26, 0xF1, 0xB1, 0x85, 0x3F, 0x27, 0xB0} }, /* 0x37 */
+ { {0xCE, 0x9F, 0x92, 0xA9, 0x17, 0x00, 0x07, 0x00,
+ 0x28, 0xC4, 0x7A, 0x8E, 0xCF, 0x29, 0xA1} }, /* 0x38 */
+ { {0xCE, 0x9F, 0x92, 0xA5, 0x17, 0x00, 0x07, 0x00,
+ 0x28, 0xD4, 0x7A, 0x8E, 0xCF, 0x29, 0xA1} }, /* 0x39 */
+ { {0xD3, 0x9F, 0x97, 0xAB, 0x1F, 0x00, 0x07, 0x00,
+ 0x2E, 0xD4, 0x7D, 0x81, 0xCF, 0x2F, 0xA1} }, /* 0x3a */
+ { {0xDC, 0x9F, 0x00, 0xAB, 0x19, 0x00, 0x07, 0x00,
+ 0xE6, 0xEF, 0xC0, 0xC3, 0xBF, 0xE7, 0x90} }, /* 0x3b */
+ { {0x6B, 0x59, 0x8F, 0x5E, 0x8C, 0x00, 0x05, 0x00,
+ 0x0B, 0x3E, 0xE9, 0x8B, 0xE7, 0x04, 0x00} }, /* 0x3c */
+ { {0x7B, 0x63, 0x9F, 0x6A, 0x93, 0x00, 0x05, 0x00,
+ 0x6F, 0xF0, 0x58, 0x8A, 0x57, 0x70, 0xA0} }, /* 0x3d */
+ { {0x86, 0x6A, 0x8a, 0x74, 0x06, 0x00, 0x02, 0x00,
+ 0x8c, 0x15, 0x4f, 0x83, 0xef, 0x8d, 0x30} }, /* 0x3e */
+ { {0x81, 0x6A, 0x85, 0x70, 0x00, 0x00, 0x02, 0x00,
+ 0x0f, 0x3e, 0xeb, 0x8e, 0xdf, 0x10, 0x00} }, /* 0x3f */
+ { {0xCE, 0x9F, 0x92, 0xA9, 0x17, 0x00, 0x07, 0x00,
+ 0x20, 0xF5, 0x03, 0x88, 0xFF, 0x21, 0x90} }, /* 0x40 */
+ { {0xE6, 0xAE, 0x8A, 0xBD, 0x90, 0x00, 0x03, 0x00,
+ 0x3D, 0x10, 0x1A, 0x8D, 0x19, 0x3E, 0x2F} }, /* 0x41 */
+ { {0xB9, 0x8F, 0x9D, 0x9B, 0x8A, 0x00, 0x06, 0x00,
+ 0x7D, 0xFF, 0x60, 0x83, 0x5F, 0x7E, 0x90} }, /* 0x42 */
+ { {0xC3, 0x8F, 0x87, 0x9B, 0x0B, 0x00, 0x07, 0x00,
+ 0x82, 0xFF, 0x60, 0x83, 0x5F, 0x83, 0x90} }, /* 0x43 */
+ { {0xAD, 0x7F, 0x91, 0x8E, 0x9C, 0x00, 0x02, 0x82,
+ 0x49, 0xF5, 0x00, 0x83, 0xFF, 0x4A, 0x90} }, /* 0x44 */
+ { {0xCD, 0x9F, 0x91, 0xA7, 0x19, 0x00, 0x07, 0x60,
+ 0xE6, 0xFF, 0xC0, 0x83, 0xBF, 0xE7, 0x90} }, /* 0x45 */
+ { {0xD3, 0x9F, 0x97, 0xAB, 0x1F, 0x00, 0x07, 0x60,
+ 0xF1, 0xFF, 0xC0, 0x83, 0xBF, 0xF2, 0x90} }, /* 0x46 */
+ { {0xD7, 0x9F, 0x9B, 0xAC, 0x1E, 0x00, 0x07, 0x00,
+ 0x03, 0xDE, 0xC0, 0x84, 0xBF, 0x04, 0x90} } /* 0x47 */
};
#if 0
static struct XGI330_CHTVRegDataStruct XGI_CHTVRegUNTSC[] = {
- /* Index:000h,001h,002h,004h,003h,005h,006h,007h,008h,015h,01Fh,00Ch,00Dh,00Eh,00Fh,010h */
- {{ 0x4A,0x77,0xBB,0x94,0x84,0x48,0xFE,0x50,0x04,0x00,0x80,0x00,0x00,0x00,0x00,0x01 }},/* 00 (640x200,640x400) */
- {{ 0x4A,0x77,0xBB,0x94,0x84,0x48,0xFE,0x50,0x04,0x00,0x80,0x00,0x00,0x00,0x00,0x01 }},/* 01 (640x350) */
- {{ 0x4A,0x77,0xBB,0x94,0x84,0x48,0xFE,0x50,0x04,0x00,0x80,0x00,0x00,0x00,0x00,0x01 }},/* 02 (720x400) */
- {{ 0x4A,0x77,0xBB,0x94,0x84,0x48,0xFE,0x50,0x04,0x00,0x80,0x00,0x00,0x00,0x00,0x01 }},/* 03 (720x350) */
- {{ 0x6A,0x77,0xBB,0x6E,0x84,0x2E,0x02,0x5A,0x04,0x00,0x80,0x20,0x7E,0x80,0x97,0x00 }},/* 04 (640x480) ;;5/6/02 */
- {{ 0xCF,0x77,0xB7,0xC8,0x84,0x3B,0x02,0x5A,0x04,0x00,0x80,0x19,0x88,0xAE,0xA3,0x00 }},/* 05 (800x600) ;;1/12/02 */
- {{ 0xEE,0x77,0xBB,0x66,0x87,0x32,0x01,0x5A,0x04,0x00,0x80,0x1B,0xD4,0x2F,0x6F,0x00 }}/* 06 (1024x768) ;;5/6/02 */
- };
+ /* Index: 000h, 001h, 002h, 004h, 003h, 005h, 006h, 007h,
+ 008h, 015h, 01Fh, 00Ch, 00Dh, 00Eh, 00Fh, 010h */
+ /* 00 (640x200,640x400) */
+ { {0x4A, 0x77, 0xBB, 0x94, 0x84, 0x48, 0xFE, 0x50,
+ 0x04, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x01 } },
+ /* 01 (640x350) */
+ { {0x4A, 0x77, 0xBB, 0x94, 0x84, 0x48, 0xFE, 0x50,
+ 0x04, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x01 } },
+ /* 02 (720x400) */
+ { {0x4A, 0x77, 0xBB, 0x94, 0x84, 0x48, 0xFE, 0x50,
+ 0x04, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x01 } },
+ /* 03 (720x350) */
+ { {0x4A, 0x77, 0xBB, 0x94, 0x84, 0x48, 0xFE, 0x50,
+ 0x04, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x01 } },
+ /* 04 (640x480) ;;5/6/02 */
+ { {0x6A, 0x77, 0xBB, 0x6E, 0x84, 0x2E, 0x02, 0x5A,
+ 0x04, 0x00, 0x80, 0x20, 0x7E, 0x80, 0x97, 0x00 } },
+ /* 05 (800x600) ;;1/12/02 */
+ { {0xCF, 0x77, 0xB7, 0xC8, 0x84, 0x3B, 0x02, 0x5A,
+ 0x04, 0x00, 0x80, 0x19, 0x88, 0xAE, 0xA3, 0x00 } },
+ /* 06 (1024x768) ;;5/6/02 */
+ { {0xEE, 0x77, 0xBB, 0x66, 0x87, 0x32, 0x01, 0x5A,
+ 0x04, 0x00, 0x80, 0x1B, 0xD4, 0x2F, 0x6F, 0x00 } }
+};
static struct XGI330_CHTVRegDataStruct XGI_CHTVRegONTSC[] = {
- /* Index:000h,001h,002h,004h,003h,005h,006h,007h,008h,015h,01Fh,00Ch,00Dh,00Eh,00Fh,010h */
- {{ 0x49,0x77,0xBB,0x7B,0x84,0x34,0x00,0x50,0x04,0x00,0x80,0x00,0x00,0x00,0x00,0x01 }},/* 00 (640x200,640x400) */
- {{ 0x49,0x77,0xBB,0x7B,0x84,0x34,0x00,0x50,0x04,0x00,0x80,0x00,0x00,0x00,0x00,0x01 }},/* 01 (640x350) */
- {{ 0x49,0x77,0xBB,0x7B,0x84,0x34,0x00,0x50,0x04,0x00,0x80,0x00,0x00,0x00,0x00,0x01 }},/* 02 (720x400) */
- {{ 0x49,0x77,0xBB,0x7B,0x84,0x34,0x00,0x50,0x04,0x00,0x80,0x00,0x00,0x00,0x00,0x01 }},/* 03 (720x350) */
- {{ 0x69,0x77,0xBB,0x6E,0x84,0x1E,0x00,0x5A,0x04,0x00,0x80,0x25,0x1A,0x80,0x26,0x00 }},/* 04 (640x480) ;;5/6/02 */
- {{ 0xCE,0x77,0xB7,0xB6,0x83,0x2C,0x02,0x5A,0x04,0x00,0x80,0x1C,0x00,0x82,0x97,0x00 }},/* 05 (800x600) ;;5/6/02 */
- {{ 0xED,0x77,0xBB,0x66,0x8C,0x21,0x02,0x5A,0x04,0x00,0x80,0x1F,0xA0,0x7E,0x73,0x00 }}/* 06 (1024x768) ;;5/6/02 */
- };
+ /* Index: 000h, 001h, 002h, 004h, 003h, 005h, 006h, 007h,
+ 008h, 015h, 01Fh, 00Ch, 00Dh, 00Eh, 00Fh, 010h */
+ /* 00 (640x200,640x400) */
+ { {0x49, 0x77, 0xBB, 0x7B, 0x84, 0x34, 0x00, 0x50,
+ 0x04, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x01} },
+ /* 01 (640x350) */
+ { {0x49, 0x77, 0xBB, 0x7B, 0x84, 0x34, 0x00 , 0x50,
+ 0x04, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x01} },
+ /* 02 (720x400) */
+ { {0x49, 0x77, 0xBB, 0x7B, 0x84, 0x34, 0x00 , 0x50,
+ 0x04, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x01} },
+ /* 03 (720x350) */
+ { {0x49, 0x77, 0xBB, 0x7B, 0x84, 0x34, 0x00 , 0x50,
+ 0x04, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x01} },
+ /* 04 (640x480) ;;5/6/02 */
+ { {0x69, 0x77, 0xBB, 0x6E, 0x84, 0x1E, 0x00 , 0x5A,
+ 0x04, 0x00, 0x80, 0x25, 0x1A, 0x80, 0x26, 0x00} },
+ /* 05 (800x600) ;;5/6/02 */
+ { {0xCE, 0x77, 0xB7, 0xB6, 0x83, 0x2C, 0x02 , 0x5A,
+ 0x04, 0x00, 0x80, 0x1C, 0x00, 0x82, 0x97, 0x00} },
+ /* 06 (1024x768) ;;5/6/02 */
+ { {0xED, 0x77, 0xBB, 0x66, 0x8C, 0x21, 0x02 , 0x5A,
+ 0x04, 0x00, 0x80, 0x1F, 0xA0, 0x7E, 0x73, 0x00} }
+};
static struct XGI330_CHTVRegDataStruct XGI_CHTVRegUPAL[] = {
- /* Index:000h,001h,002h,004h,003h,005h,006h,007h,008h,015h,01Fh,00Ch,00Dh,00Eh,00Fh,010h */
- {{ 0x41,0x7F,0xB7,0x34,0xAD,0x50,0x34,0x83,0x05,0x00,0x80,0x00,0x00,0x00,0x00,0x01 }},/* ; 00 (640x200,640x400) */
- {{ 0x41,0x7F,0xB7,0x80,0x85,0x50,0x00,0x83,0x05,0x00,0x80,0x00,0x00,0x00,0x00,0x01 }},/* ; 01 (640x350) */
- {{ 0x41,0x7F,0xB7,0x34,0xAD,0x50,0x34,0x83,0x05,0x00,0x80,0x00,0x00,0x00,0x00,0x01 }},/* ; 02 (720x400) */
- {{ 0x41,0x7F,0xB7,0x12,0x85,0x50,0x00,0x83,0x05,0x00,0x80,0x00,0x00,0x00,0x00,0x01 }},/* ; 03 (720x350) */
- {{ 0x61,0x7F,0xB7,0x99,0x84,0x35,0x04,0x5A,0x05,0x00,0x80,0x26,0x2A,0x55,0x5D,0x00 }},/* ; 04 (640x480) */
- {{ 0xC3,0x7F,0xB7,0x7A,0x84,0x40,0x02,0x5A,0x05,0x00,0x80,0x1F,0x84,0x3D,0x28,0x00 }},/* ; 05 (800x600) ;;1/12/02 */
- {{ 0xE5,0x7F,0xB7,0x1D,0xA7,0x3E,0x04,0x5A,0x05,0x00,0x80,0x20,0x3E,0xE4,0x22,0x00 }}/* ; 06 (1024x768) ;;1/12/02 */
- };
+ /* Index: 000h, 001h, 002h, 004h, 003h, 005h, 006h, 007h,
+ 008h, 015h, 01Fh, 00Ch, 00Dh, 00Eh, 00Fh, 010h */
+ /* ; 00 (640x200,640x400) */
+ { {0x41, 0x7F, 0xB7, 0x34, 0xAD, 0x50, 0x34, 0x83,
+ 0x05, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x01} },
+ /* ; 01 (640x350) */
+ { {0x41, 0x7F, 0xB7, 0x80, 0x85, 0x50, 0x00, 0x83,
+ 0x05, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x01} },
+ /* ; 02 (720x400) */
+ { {0x41, 0x7F, 0xB7, 0x34, 0xAD, 0x50, 0x34, 0x83,
+ 0x05, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x01} },
+ /* ; 03 (720x350) */
+ { {0x41, 0x7F, 0xB7, 0x12, 0x85, 0x50, 0x00, 0x83,
+ 0x05, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x01} },
+ /* ; 04 (640x480) */
+ { {0x61, 0x7F, 0xB7, 0x99, 0x84, 0x35, 0x04, 0x5A,
+ 0x05, 0x00, 0x80, 0x26, 0x2A, 0x55, 0x5D, 0x00} },
+ /* ; 05 (800x600) ;;1/12/02 */
+ { {0xC3, 0x7F, 0xB7, 0x7A, 0x84, 0x40, 0x02, 0x5A,
+ 0x05, 0x00, 0x80, 0x1F, 0x84, 0x3D, 0x28, 0x00} },
+ /* ; 06 (1024x768) ;;1/12/02 */
+ { {0xE5, 0x7F, 0xB7, 0x1D, 0xA7, 0x3E, 0x04, 0x5A,
+ 0x05, 0x00, 0x80, 0x20, 0x3E, 0xE4, 0x22, 0x00} }
+};
static struct XGI330_CHTVRegDataStruct XGI_CHTVRegOPAL[] = {
- /* Index:000,0x01,0x02,0x04,0x03,0x05,0x06,0x07,0x08,0x15,0x1F,0x0C,0x0D,0x0E,0x0F,0x10h */
- {{ 0x41,0x7F,0xB7,0x36,0xAD,0x50,0x34,0x83,0x05,0x00,0x80,0x00,0x00,0x00,0x00,0x01 }},/* 00 (640x200,640x400) */
- {{ 0x41,0x7F,0xB7,0x86,0x85,0x50,0x00,0x83,0x05,0x00,0x80,0x00,0x00,0x00,0x00,0x01 }},/* 01 (640x350) */
- {{ 0x41,0x7F,0xB7,0x36,0xAD,0x50,0x34,0x83,0x05,0x00,0x80,0x00,0x00,0x00,0x00,0x01 }},/* 02 (720x400) */
- {{ 0x41,0x7F,0xB7,0x86,0x85,0x50,0x00,0x83,0x05,0x00,0x80,0x00,0x00,0x00,0x00,0x01 }},/* 03 (720x350) */
- {{ 0x61,0x7F,0xB7,0x99,0x84,0x35,0x04,0x5A,0x05,0x00,0x80,0x26,0x2A,0x55,0x5D,0x00 }},/* 04 (640x480) */
- {{ 0xC1,0x7F,0xB7,0x4D,0x8C,0x1E,0x31,0x5A,0x05,0x00,0x80,0x26,0x78,0x19,0x34,0x00 }},/* 05 (800x600) ;;1/12/02 */
- {{ 0xE4,0x7F,0xB7,0x1E,0xAF,0x29,0x37,0x5A,0x05,0x00,0x80,0x25,0x8C,0xB2,0x2A,0x00 }}/* 06 (1024x768) ;;1/12/02 */
- };
+ /* Index: 000, 0x01, 0x02, 0x04, 0x03, 0x05, 0x06, 0x07,
+ 0x08, 0x15, 0x1F, 0x0C, 0x0D, 0x0E, 0x0F, 0x10h */
+ /* 00 (640x200,640x400) */
+ { {0x41, 0x7F, 0xB7, 0x36, 0xAD, 0x50, 0x34, 0x83,
+ 0x05, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x01} },
+ /* 01 (640x350) */
+ { {0x41, 0x7F, 0xB7, 0x86, 0x85, 0x50, 0x00, 0x83,
+ 0x05, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x01} },
+ /* 02 (720x400) */
+ { {0x41, 0x7F, 0xB7, 0x36, 0xAD, 0x50, 0x34, 0x83,
+ 0x05, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x01} },
+ /* 03 (720x350) */
+ { {0x41, 0x7F, 0xB7, 0x86, 0x85, 0x50, 0x00, 0x83,
+ 0x05, 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x01} },
+ /* 04 (640x480) */
+ { {0x61, 0x7F, 0xB7, 0x99, 0x84, 0x35, 0x04, 0x5A,
+ 0x05, 0x00, 0x80, 0x26, 0x2A, 0x55, 0x5D, 0x00} },
+ /* 05 (800x600) ;;1/12/02 */
+ { {0xC1, 0x7F, 0xB7, 0x4D, 0x8C, 0x1E, 0x31, 0x5A,
+ 0x05, 0x00, 0x80, 0x26, 0x78, 0x19, 0x34, 0x00} },
+ /* 06 (1024x768) ;;1/12/02 */
+ { {0xE4, 0x7F, 0xB7, 0x1E, 0xAF, 0x29, 0x37, 0x5A,
+ 0x05, 0x00, 0x80, 0x25, 0x8C, 0xB2, 0x2A, 0x00} }
+};
#endif
static unsigned char XGI_CH7017LV1024x768[] = {
- 0x60, 0x02, 0x00, 0x07, 0x40, 0xED, 0xA3,
- 0xC8, 0xC7, 0xAC, 0xE0, 0x02};
+ 0x60, 0x02, 0x00, 0x07, 0x40, 0xED,
+ 0xA3, 0xC8, 0xC7, 0xAC, 0xE0, 0x02};
static unsigned char XGI_CH7017LV1400x1050[] = {
- 0x60, 0x03, 0x11, 0x00, 0x40, 0xE3, 0xAD,
- 0xDB, 0xF6, 0xAC, 0xE0, 0x02};
-
+ 0x60, 0x03, 0x11, 0x00, 0x40, 0xE3,
+ 0xAD, 0xDB, 0xF6, 0xAC, 0xE0, 0x02};
/*add for new UNIVGABIOS*/
-static struct XGI330_LCDDataStruct XGI_StLCD1024x768Data[] =
-{
- { 62, 25, 800, 546,1344, 806},
- { 32, 15, 930, 546,1344, 806},
- { 62, 25, 800, 546,1344, 806}, /* chiawen for dot9 -> dot8 */
- { 104, 45, 945, 496,1344, 806},
- { 62, 25, 800, 546,1344, 806},
- { 31, 18,1008, 624,1344, 806},
- { 1, 1,1344, 806,1344, 806}
+static struct XGI330_LCDDataStruct XGI_StLCD1024x768Data[] = {
+ {62, 25, 800, 546, 1344, 806},
+ {32, 15, 930, 546, 1344, 806},
+ {62, 25, 800, 546, 1344, 806}, /*chiawenfordot9->dot8*/
+ {104, 45, 945, 496, 1344, 806},
+ {62, 25, 800, 546, 1344, 806},
+ {31, 18, 1008, 624, 1344, 806},
+ {1, 1, 1344, 806, 1344, 806}
};
-static struct XGI330_LCDDataStruct XGI_ExtLCD1024x768Data[] =
-{
- { 42, 25,1536, 419,1344, 806}, /* { 12, 5, 896, 512,1344, 806}, // alan 09/12/2003 */
- { 48, 25,1536, 369,1344, 806}, /* { 12, 5, 896, 510,1344, 806}, // alan 09/12/2003 */
- { 42, 25,1536, 419,1344, 806}, /* { 32, 15,1008, 505,1344, 806}, // alan 09/12/2003 */
- { 48, 25,1536, 369,1344, 806}, /* { 32, 15,1008, 514,1344, 806}, // alan 09/12/2003 */
- { 12, 5, 896, 500,1344, 806},
- { 42, 25,1024, 625,1344, 806},
- { 1, 1,1344, 806,1344, 806},
- { 12, 5, 896, 500,1344, 806},
- { 42, 25,1024, 625,1344, 806},
- { 1, 1,1344, 806,1344, 806},
- { 12, 5, 896, 500,1344, 806},
- { 42, 25,1024, 625,1344, 806},
- { 1, 1,1344, 806,1344, 806}
+static struct XGI330_LCDDataStruct XGI_ExtLCD1024x768Data[] = {
+ /* { 12, 5, 896, 512,1344, 806}, // alan 09/12/2003 */
+ {42, 25, 1536, 419, 1344, 806},
+ /* { 12, 5, 896, 510,1344, 806}, // alan 09/12/2003 */
+ {48, 25, 1536, 369, 1344, 806},
+ /* { 32, 15,1008, 505,1344, 806}, // alan 09/12/2003 */
+ {42, 25, 1536, 419, 1344, 806},
+ /* { 32, 15,1008, 514,1344, 806}, // alan 09/12/2003 */
+ {48, 25, 1536, 369, 1344, 806},
+ {12, 5, 896, 500, 1344, 806},
+ {42, 25, 1024, 625, 1344, 806},
+ {1, 1, 1344, 806, 1344, 806},
+ {12, 5, 896, 500, 1344, 806},
+ {42, 25, 1024, 625, 1344, 806},
+ {1, 1, 1344, 806, 1344, 806},
+ {12, 5, 896, 500, 1344, 806},
+ {42, 25, 1024, 625, 1344, 806},
+ {1, 1, 1344, 806, 1344, 806}
};
-/*struct XGI330_LCDDataStruct XGI_St2LCD1024x768Data[] =
-{
- { 62, 25, 800, 546,1344, 806},
- { 32, 15, 930, 546,1344, 806},
- { 62, 25, 800, 546,1344, 806},
- { 104, 45, 945, 496,1344, 806},
- { 62, 25, 800, 546,1344, 806},
- { 31, 18,1008, 624,1344, 806},
- { 1, 1,1344, 806,1344, 806}
+/*struct XGI330_LCDDataStruct XGI_St2LCD1024x768Data[] = {
+ {62, 25, 800, 546, 1344, 806},
+ {32, 15, 930, 546, 1344, 806},
+ {62, 25, 800, 546, 1344, 806},
+ {104, 45, 945, 496, 1344, 806},
+ {62, 25, 800, 546, 1344, 806},
+ {31, 18, 1008, 624, 1344, 806},
+ {1, 1, 1344, 806, 1344, 806}
};*/
-static struct XGI330_LCDDataStruct XGI_CetLCD1024x768Data[] =
-{
- { 1,1,1344,806,1344,806 }, /* ; 00 (320x200,320x400,640x200,640x400) */
- { 1,1,1344,806,1344,806 }, /* 01 (320x350,640x350) */
- { 1,1,1344,806,1344,806 }, /* 02 (360x400,720x400) */
- { 1,1,1344,806,1344,806 }, /* 03 (720x350) */
- { 1,1,1344,806,1344,806 }, /* 04 (640x480x60Hz) */
- { 1,1,1344,806,1344,806 }, /* 05 (800x600x60Hz) */
- { 1,1,1344,806,1344,806 } /* 06 (1024x768x60Hz) */
+static struct XGI330_LCDDataStruct XGI_CetLCD1024x768Data[] = {
+ {1, 1, 1344, 806, 1344, 806}, /* ; 00 (320x200,320x400,
+ 640x200,640x400) */
+ {1, 1, 1344, 806, 1344, 806}, /* 01 (320x350,640x350) */
+ {1, 1, 1344, 806, 1344, 806}, /* 02 (360x400,720x400) */
+ {1, 1, 1344, 806, 1344, 806}, /* 03 (720x350) */
+ {1, 1, 1344, 806, 1344, 806}, /* 04 (640x480x60Hz) */
+ {1, 1, 1344, 806, 1344, 806}, /* 05 (800x600x60Hz) */
+ {1, 1, 1344, 806, 1344, 806} /* 06 (1024x768x60Hz) */
};
-static struct XGI330_LCDDataStruct XGI_StLCD1280x1024Data[] =
-{
- { 22, 5, 800, 510,1650,1088},
- { 22, 5, 800, 510,1650,1088},
- { 176, 45, 900, 510,1650,1088},
- { 176, 45, 900, 510,1650,1088},
- { 22, 5, 800, 510,1650,1088},
- { 13, 5,1024, 675,1560,1152},
- { 16, 9,1266, 804,1688,1072},
- { 1, 1,1688,1066,1688,1066}
+static struct XGI330_LCDDataStruct XGI_StLCD1280x1024Data[] = {
+ {22, 5, 800, 510, 1650, 1088},
+ {22, 5, 800, 510, 1650, 1088},
+ {176, 45, 900, 510, 1650, 1088},
+ {176, 45, 900, 510, 1650, 1088},
+ {22, 5, 800, 510, 1650, 1088},
+ {13, 5, 1024, 675, 1560, 1152},
+ {16, 9, 1266, 804, 1688, 1072},
+ {1, 1, 1688, 1066, 1688, 1066}
};
-static struct XGI330_LCDDataStruct XGI_ExtLCD1280x1024Data[] =
-{
- { 211, 60,1024, 501,1688,1066},
- { 211, 60,1024, 508,1688,1066},
- { 211, 60,1024, 501,1688,1066},
- { 211, 60,1024, 508,1688,1066},
- { 211, 60,1024, 500,1688,1066},
- { 211, 75,1024, 625,1688,1066},
- { 211, 120,1280, 798,1688,1066},
- { 1, 1,1688,1066,1688,1066}
+static struct XGI330_LCDDataStruct XGI_ExtLCD1280x1024Data[] = {
+ {211, 60, 1024, 501, 1688, 1066},
+ {211, 60, 1024, 508, 1688, 1066},
+ {211, 60, 1024, 501, 1688, 1066},
+ {211, 60, 1024, 508, 1688, 1066},
+ {211, 60, 1024, 500, 1688, 1066},
+ {211, 75, 1024, 625, 1688, 1066},
+ {211, 120, 1280, 798, 1688, 1066},
+ {1, 1, 1688, 1066, 1688, 1066}
};
#if 0
-static struct XGI330_LCDDataStruct XGI_St2LCD1280x1024Data[] =
-{
- { 22, 5, 800, 510,1650,1088},
- { 22, 5, 800, 510,1650,1088},
- { 176, 45, 900, 510,1650,1088},
- { 176, 45, 900, 510,1650,1088},
- { 22, 5, 800, 510,1650,1088},
- { 13, 5,1024, 675,1560,1152},
- { 16, 9,1266, 804,1688,1072},
- { 1, 1,1688,1066,1688,1066}
+static struct XGI330_LCDDataStruct XGI_St2LCD1280x1024Data[] = {
+ {22, 5, 800, 510, 1650, 1088},
+ {22, 5, 800, 510, 1650, 1088},
+ {176, 45, 900, 510, 1650, 1088},
+ {176, 45, 900, 510, 1650, 1088},
+ {22, 5, 800, 510, 1650, 1088},
+ {13, 5, 1024, 675, 1560, 1152},
+ {16, 9, 1266, 804, 1688, 1072},
+ {1, 1, 1688, 1066, 1688, 1066}
};
#endif
-static struct XGI330_LCDDataStruct XGI_CetLCD1280x1024Data[] =
-{
- { 1,1,1688,1066,1688,1066 }, /* 00 (320x200,320x400,640x200,640x400) */
- { 1,1,1688,1066,1688,1066 }, /* 01 (320x350,640x350) */
- { 1,1,1688,1066,1688,1066 }, /* 02 (360x400,720x400) */
- { 1,1,1688,1066,1688,1066 }, /* 03 (720x350) */
- { 1,1,1688,1066,1688,1066 }, /* 04 (640x480x60Hz) */
- { 1,1,1688,1066,1688,1066 }, /* 05 (800x600x60Hz) */
- { 1,1,1688,1066,1688,1066 }, /* 06 (1024x768x60Hz) */
- { 1,1,1688,1066,1688,1066 }, /* 07 (1280x1024x60Hz) */
- { 1,1,1688,1066,1688,1066 } /* 08 (1400x1050x60Hz) */
+static struct XGI330_LCDDataStruct XGI_CetLCD1280x1024Data[] = {
+ {1, 1, 1688, 1066, 1688, 1066}, /* 00 (320x200,320x400,
+ 640x200,640x400) */
+ {1, 1, 1688, 1066, 1688, 1066}, /* 01 (320x350,640x350) */
+ {1, 1, 1688, 1066, 1688, 1066}, /* 02 (360x400,720x400) */
+ {1, 1, 1688, 1066, 1688, 1066}, /* 03 (720x350) */
+ {1, 1, 1688, 1066, 1688, 1066}, /* 04 (640x480x60Hz) */
+ {1, 1, 1688, 1066, 1688, 1066}, /* 05 (800x600x60Hz) */
+ {1, 1, 1688, 1066, 1688, 1066}, /* 06 (1024x768x60Hz) */
+ {1, 1, 1688, 1066, 1688, 1066}, /* 07 (1280x1024x60Hz) */
+ {1, 1, 1688, 1066, 1688, 1066} /* 08 (1400x1050x60Hz) */
};
-static struct XGI330_LCDDataStruct XGI_StLCD1400x1050Data[] =
-{
- { 211,100,2100,408,1688,1066 }, /* 00 (320x200,320x400,640x200,640x400) */
- { 211,64,1536,358,1688,1066 }, /* 01 (320x350,640x350) */
- { 211,100,2100,408,1688,1066 }, /* 02 (360x400,720x400) */
- { 211,64,1536,358,1688,1066 }, /* 03 (720x350) */
- { 211,48,840,488,1688,1066 }, /* 04 (640x480x60Hz) */
- { 211,72,1008,609,1688,1066 }, /* 05 (800x600x60Hz) */
- { 211,128,1400,776,1688,1066 }, /* 06 (1024x768x60Hz) */
- { 1,1,1688,1066,1688,1066 }, /* 07 (1280x1024x60Hz w/o Scaling) */
- { 1,1,1688,1066,1688,1066 } /* 08 (1400x1050x60Hz) */
+static struct XGI330_LCDDataStruct XGI_StLCD1400x1050Data[] = {
+ {211, 100, 2100, 408, 1688, 1066}, /* 00 (320x200,320x400,
+ 640x200,640x400) */
+ {211, 64, 1536, 358, 1688, 1066}, /* 01 (320x350,640x350) */
+ {211, 100, 2100, 408, 1688, 1066}, /* 02 (360x400,720x400) */
+ {211, 64, 1536, 358, 1688, 1066}, /* 03 (720x350) */
+ {211, 48, 840, 488, 1688, 1066}, /* 04 (640x480x60Hz) */
+ {211, 72, 1008, 609, 1688, 1066}, /* 05 (800x600x60Hz) */
+ {211, 128, 1400, 776, 1688, 1066}, /* 06 (1024x768x60Hz) */
+ {1, 1, 1688, 1066, 1688, 1066}, /* 07 (1280x1024x60Hz
+ w/o Scaling) */
+ {1, 1, 1688, 1066, 1688, 1066} /* 08 (1400x1050x60Hz) */
};
-static struct XGI330_LCDDataStruct XGI_ExtLCD1400x1050Data[] =
-{
- { 211,100,2100,408,1688,1066 }, /* 00 (320x200,320x400,640x200,640x400) */
- { 211,64,1536,358,1688,1066 }, /* 01 (320x350,640x350) */
- { 211,100,2100,408,1688,1066 }, /* 02 (360x400,720x400) */
- { 211,64,1536,358,1688,1066 }, /* 03 (720x350) */
- { 211,48,840,488,1688,1066 }, /* 04 (640x480x60Hz) */
- { 211,72,1008,609,1688,1066 }, /* 05 (800x600x60Hz) */
- { 211,128,1400,776,1688,1066 }, /* 06 (1024x768x60Hz) */
- { 1,1,1688,1066,1688,1066 }, /* 07 (1280x1024x60Hz w/o Scaling) */
- { 1,1,1688,1066,1688,1066 } /* 08 (1400x1050x60Hz) */
+static struct XGI330_LCDDataStruct XGI_ExtLCD1400x1050Data[] = {
+ {211, 100, 2100, 408, 1688, 1066}, /* 00 (320x200,320x400,
+ 640x200,640x400) */
+ {211, 64, 1536, 358, 1688, 1066}, /* 01 (320x350,640x350) */
+ {211, 100, 2100, 408, 1688, 1066}, /* 02 (360x400,720x400) */
+ {211, 64, 1536, 358, 1688, 1066}, /* 03 (720x350) */
+ {211, 48, 840, 488, 1688, 1066}, /* 04 (640x480x60Hz) */
+ {211, 72, 1008, 609, 1688, 1066}, /* 05 (800x600x60Hz) */
+ {211, 128, 1400, 776, 1688, 1066}, /* 06 (1024x768x60Hz) */
+ {1, 1, 1688, 1066, 1688, 1066}, /* 07 (1280x1024x60Hz
+ w/o Scaling) */
+ {1, 1, 1688, 1066, 1688, 1066} /* 08 (1400x1050x60Hz) */
};
-static struct XGI330_LCDDataStruct XGI_ExtLCD1600x1200Data[] =
-{
- { 4,1,1620,420,2160,1250 }, /* { 3,1,2160,425,2160,1250 }, // 00 (320x200,320x400,640x200,640x400) // alan 10/14/2003 */
- { 27,7,1920,375,2160,1250 }, /* 01 (320x350,640x350) */
- { 4,1,1620,420,2160,1250 }, /* { 3,1,2160,425,2160,1250 }, // 02 (360x400,720x400) // alan 10/14/2003 */
- { 27,7,1920,375,2160,1250 }, /* 03 (720x350) */
- { 27,4,800,500,2160,1250 }, /* 04 (640x480x60Hz) */
- { 4,1,1080,625,2160,1250 }, /* 05 (800x600x60Hz) */
- { 5,2,1350,800,2160,1250 }, /* 06 (1024x768x60Hz) */
- { 27,16,1500,1064,2160,1250 }, /* 07 (1280x1024x60Hz) */
- { 9,7,1920,1106,2160,1250 }, /* 08 (1400x1050x60Hz) */
- { 1,1,2160,1250,2160,1250 } /* 09 (1600x1200x60Hz) ;302lv */
+static struct XGI330_LCDDataStruct XGI_ExtLCD1600x1200Data[] = {
+ {4, 1, 1620, 420, 2160, 1250}, /* { 3,1,2160,425,2160,1250 },
+ // 00 (320x200,320x400,
+ // 640x200,640x400)
+ // // alan 10/14/2003 */
+ {27, 7, 1920, 375, 2160, 1250}, /* 01 (320x350,640x350) */
+ {4, 1, 1620, 420, 2160, 1250}, /* { 3,1,2160,425,2160,1250 },
+ // 02 (360x400,720x400)
+ // // alan 10/14/2003 */
+ {27, 7, 1920, 375, 2160, 1250}, /* 03 (720x350) */
+ {27, 4, 800, 500, 2160, 1250}, /* 04 (640x480x60Hz) */
+ {4, 1, 1080, 625, 2160, 1250}, /* 05 (800x600x60Hz) */
+ {5, 2, 1350, 800, 2160, 1250}, /* 06 (1024x768x60Hz) */
+ {27, 16, 1500, 1064, 2160, 1250}, /* 07 (1280x1024x60Hz) */
+ {9, 7, 1920, 1106, 2160, 1250}, /* 08 (1400x1050x60Hz) */
+ {1, 1, 2160, 1250, 2160, 1250} /* 09 (1600x1200x60Hz) ;302lv */
};
-static struct XGI330_LCDDataStruct XGI_StLCD1600x1200Data[] =
-{
- { 27,4,800,500,2160,1250 },/* 00 (320x200,320x400,640x200,640x400) */
- { 27,4,800,500,2160,1250 },/* 01 (320x350,640x350) */
- { 27,4,800,500,2160,1250 },/* 02 (360x400,720x400) */
- { 27,4,800,500,2160,1250 },/* 03 (720x350) */
- { 27,4,800,500,2160,1250 },/* 04 (320x240,640x480) */
- { 4,1,1080,625,2160,1250 },/* 05 (400x300,800x600) */
- { 5,2,1350,800,2160,1250 },/* 06 (512x384,1024x768) */
- { 135,88,1600,1100,2160,1250 },/* 07 (1280x1024) */
- { 1,1,1800,1500,2160,1250 },/* 08 (1400x1050) */
- { 1,1,2160,1250,2160,1250 } /* 09 (1600x1200) */
+static struct XGI330_LCDDataStruct XGI_StLCD1600x1200Data[] = {
+ {27, 4, 800, 500, 2160, 1250}, /* 00 (320x200,320x400,
+ 640x200,640x400) */
+ {27, 4, 800, 500, 2160, 1250}, /* 01 (320x350,640x350) */
+ {27, 4, 800, 500, 2160, 1250}, /* 02 (360x400,720x400) */
+ {27, 4, 800, 500, 2160, 1250}, /* 03 (720x350) */
+ {27, 4, 800, 500, 2160, 1250}, /* 04 (320x240,640x480) */
+ {4, 1, 1080, 625, 2160, 1250}, /* 05 (400x300,800x600) */
+ {5, 2, 1350, 800, 2160, 1250}, /* 06 (512x384,1024x768) */
+ {135, 88, 1600, 1100, 2160, 1250}, /* 07 (1280x1024) */
+ {1, 1, 1800, 1500, 2160, 1250}, /* 08 (1400x1050) */
+ {1, 1, 2160, 1250, 2160, 1250} /* 09 (1600x1200) */
};
-static struct XGI330_LCDDataStruct XGI_CetLCD1400x1050Data[] =
-{
- { 1,1,1688,1066,1688,1066 }, /* 00 (320x200,320x400,640x200,640x400) */
- { 1,1,1688,1066,1688,1066 }, /* 01 (320x350,640x350) */
- { 1,1,1688,1066,1688,1066 }, /* 02 (360x400,720x400) */
- { 1,1,1688,1066,1688,1066 }, /* 03 (720x350) */
- { 1,1,1688,1066,1688,1066 }, /* 04 (640x480x60Hz) */
- { 1,1,1688,1066,1688,1066 }, /* 05 (800x600x60Hz) */
- { 1,1,1688,1066,1688,1066 }, /* 06 (1024x768x60Hz) */
- { 1,1,1688,1066,1688,1066 }, /* 07 (1280x1024x60Hz) */
- { 1,1,1688,1066,1688,1066 } /* 08 (1400x1050x60Hz) */
+static struct XGI330_LCDDataStruct XGI_CetLCD1400x1050Data[] = {
+ {1, 1, 1688, 1066, 1688, 1066}, /* 00 (320x200,320x400,
+ 640x200,640x400) */
+ {1, 1, 1688, 1066, 1688, 1066}, /* 01 (320x350,640x350) */
+ {1, 1, 1688, 1066, 1688, 1066}, /* 02 (360x400,720x400) */
+ {1, 1, 1688, 1066, 1688, 1066}, /* 03 (720x350) */
+ {1, 1, 1688, 1066, 1688, 1066}, /* 04 (640x480x60Hz) */
+ {1, 1, 1688, 1066, 1688, 1066}, /* 05 (800x600x60Hz) */
+ {1, 1, 1688, 1066, 1688, 1066}, /* 06 (1024x768x60Hz) */
+ {1, 1, 1688, 1066, 1688, 1066}, /* 07 (1280x1024x60Hz) */
+ {1, 1, 1688, 1066, 1688, 1066} /* 08 (1400x1050x60Hz) */
};
-static struct XGI330_LCDDataStruct XGI_NoScalingData[] =
-{
- { 1, 1, 800, 449, 800, 449},
- { 1, 1, 800, 449, 800, 449},
- { 1, 1, 900, 449, 900, 449},
- { 1, 1, 900, 449, 900, 449},
- { 1, 1, 800, 525, 800, 525},
- { 1, 1,1056, 628,1056, 628},
- { 1, 1,1344, 806,1344, 806},
- { 1, 1,1688,1066,1688,1066}
+static struct XGI330_LCDDataStruct XGI_NoScalingData[] = {
+ {1, 1, 800, 449, 800, 449},
+ {1, 1, 800, 449, 800, 449},
+ {1, 1, 900, 449, 900, 449},
+ {1, 1, 900, 449, 900, 449},
+ {1, 1, 800, 525, 800, 525},
+ {1, 1, 1056, 628, 1056, 628},
+ {1, 1, 1344, 806, 1344, 806},
+ {1, 1, 1688, 1066, 1688, 1066}
};
-static struct XGI330_LCDDataStruct XGI_ExtLCD1024x768x75Data[] =
-{
- {42,25,1536,419,1344,806 }, /* ; 00 (320x200,320x400,640x200,640x400) */
- {48,25,1536,369,1344,806 }, /* ; 01 (320x350,640x350) */
- {42,25,1536,419,1344,806 }, /* ; 02 (360x400,720x400) */
- {48,25,1536,369,1344,806 }, /* ; 03 (720x350) */
- {8,5,1312,500,1312,800 }, /* ; 04 (640x480x75Hz) */
- {41,25,1024,625,1312,800 }, /* ; 05 (800x600x75Hz) */
- {1,1,1312,800,1312,800 } /* ; 06 (1024x768x75Hz) */
+static struct XGI330_LCDDataStruct XGI_ExtLCD1024x768x75Data[] = {
+ {42, 25, 1536, 419, 1344, 806}, /* ; 00 (320x200,320x400,
+ 640x200,640x400) */
+ {48, 25, 1536, 369, 1344, 806}, /* ; 01 (320x350,640x350) */
+ {42, 25, 1536, 419, 1344, 806}, /* ; 02 (360x400,720x400) */
+ {48, 25, 1536, 369, 1344, 806}, /* ; 03 (720x350) */
+ {8, 5, 1312, 500, 1312, 800}, /* ; 04 (640x480x75Hz) */
+ {41, 25, 1024, 625, 1312, 800}, /* ; 05 (800x600x75Hz) */
+ {1, 1, 1312, 800, 1312, 800} /* ; 06 (1024x768x75Hz) */
};
#if 0
-static struct XGI330_LCDDataStruct XGI_StLCD1024x768x75Data[] =
-{
- {42,25,1536,419,1344,806 }, /* ; 00 (320x200,320x400,640x200,640x400) */
- {48,25,1536,369,1344,806 }, /* ; 01 (320x350,640x350) */
- {42,25,1536,419,1344,806 }, /* ; 02 (360x400,720x400) */
- {48,25,1536,369,1344,806 }, /* ; 03 (720x350) */
- {8,5,1312,500,1312,800 }, /* ; 04 (640x480x75Hz) */
- {41,25,1024,625,1312,800 }, /* ; 05 (800x600x75Hz) */
- {1,1,1312,800,1312,800 } /* ; 06 (1024x768x75Hz) */
+static struct XGI330_LCDDataStruct XGI_StLCD1024x768x75Data[] = {
+ {42, 25, 1536, 419, 1344, 806}, /* ; 00 (320x200,320x400,
+ 640x200,640x400) */
+ {48, 25, 1536, 369, 1344, 806}, /* ; 01 (320x350,640x350) */
+ {42, 25, 1536, 419, 1344, 806}, /* ; 02 (360x400,720x400) */
+ {48, 25, 1536, 369, 1344, 806}, /* ; 03 (720x350) */
+ {8, 5, 1312, 500, 1312, 800}, /* ; 04 (640x480x75Hz) */
+ {41, 25, 1024, 625, 1312, 800}, /* ; 05 (800x600x75Hz) */
+ {1, 1, 1312, 800, 1312, 800} /* ; 06 (1024x768x75Hz) */
};
#endif
-static struct XGI330_LCDDataStruct XGI_CetLCD1024x768x75Data[] =
-{
- {1,1,1312,800,1312,800}, /* ; 00 (320x200,320x400,640x200,640x400) */
- {1,1,1312,800,1312,800}, /* ; 01 (320x350,640x350) */
- {1,1,1312,800,1312,800}, /* ; 02 (360x400,720x400) */
- {1,1,1312,800,1312,800}, /* ; 03 (720x350) */
- {1,1,1312,800,1312,800}, /* ; 04 (640x480x75Hz) */
- {1,1,1312,800,1312,800}, /* ; 05 (800x600x75Hz) */
- {1,1,1312,800,1312,800} /* ; 06 (1024x768x75Hz) */
+static struct XGI330_LCDDataStruct XGI_CetLCD1024x768x75Data[] = {
+ {1, 1, 1312, 800, 1312, 800}, /* ; 00 (320x200,320x400,
+ 640x200,640x400) */
+ {1, 1, 1312, 800, 1312, 800}, /* ; 01 (320x350,640x350) */
+ {1, 1, 1312, 800, 1312, 800}, /* ; 02 (360x400,720x400) */
+ {1, 1, 1312, 800, 1312, 800}, /* ; 03 (720x350) */
+ {1, 1, 1312, 800, 1312, 800}, /* ; 04 (640x480x75Hz) */
+ {1, 1, 1312, 800, 1312, 800}, /* ; 05 (800x600x75Hz) */
+ {1, 1, 1312, 800, 1312, 800} /* ; 06 (1024x768x75Hz) */
};
-static struct XGI330_LCDDataStruct XGI_ExtLCD1280x1024x75Data[] =
-{
- {211,60,1024,501,1688,1066 }, /* ; 00 (320x200,320x400,640x200,640x400) */
- {211,60,1024,508,1688,1066 }, /* ; 01 (320x350,640x350) */
- {211,60,1024,501,1688,1066 }, /* ; 02 (360x400,720x400) */
- {211,60,1024,508,1688,1066 }, /* ; 03 (720x350) */
- {211,45,768,498,1688,1066 }, /* ; 04 (640x480x75Hz) */
- {211,75,1024,625,1688,1066 }, /* ; 05 (800x600x75Hz) */
- {211,120,1280,798,1688,1066 }, /* ; 06 (1024x768x75Hz) */
- {1,1,1688,1066,1688,1066 } /* ; 07 (1280x1024x75Hz) */
+static struct XGI330_LCDDataStruct XGI_ExtLCD1280x1024x75Data[] = {
+ {211, 60, 1024, 501, 1688, 1066}, /* ; 00 (320x200,320x400,
+ 640x200,640x400) */
+ {211, 60, 1024, 508, 1688, 1066}, /* ; 01 (320x350,640x350) */
+ {211, 60, 1024, 501, 1688, 1066}, /* ; 02 (360x400,720x400) */
+ {211, 60, 1024, 508, 1688, 1066}, /* ; 03 (720x350) */
+ {211, 45, 768, 498, 1688, 1066}, /* ; 04 (640x480x75Hz) */
+ {211, 75, 1024, 625, 1688, 1066}, /* ; 05 (800x600x75Hz) */
+ {211, 120, 1280, 798, 1688, 1066}, /* ; 06 (1024x768x75Hz) */
+ {1, 1, 1688, 1066, 1688, 1066} /* ; 07 (1280x1024x75Hz) */
};
-static struct XGI330_LCDDataStruct XGI_StLCD1280x1024x75Data[] =
-{
- {211,60,1024,501,1688,1066 }, /* ; 00 (320x200,320x400,640x200,640x400) */
- {211,60,1024,508,1688,1066 }, /* ; 01 (320x350,640x350) */
- {211,60,1024,501,1688,1066 }, /* ; 02 (360x400,720x400) */
- {211,60,1024,508,1688,1066 }, /* ; 03 (720x350) */
- {211,45,768,498,1688,1066 }, /* ; 04 (640x480x75Hz) */
- {211,75,1024,625,1688,1066 }, /* ; 05 (800x600x75Hz) */
- {211,120,1280,798,1688,1066}, /* ; 06 (1024x768x75Hz) */
- {1,1,1688,1066,1688,1066 } /* ; 07 (1280x1024x75Hz) */
+static struct XGI330_LCDDataStruct XGI_StLCD1280x1024x75Data[] = {
+ {211, 60, 1024, 501, 1688, 1066}, /* ; 00 (320x200,320x400,
+ 640x200,640x400) */
+ {211, 60, 1024, 508, 1688, 1066}, /* ; 01 (320x350,640x350) */
+ {211, 60, 1024, 501, 1688, 1066}, /* ; 02 (360x400,720x400) */
+ {211, 60, 1024, 508, 1688, 1066}, /* ; 03 (720x350) */
+ {211, 45, 768, 498, 1688, 1066}, /* ; 04 (640x480x75Hz) */
+ {211, 75, 1024, 625, 1688, 1066}, /* ; 05 (800x600x75Hz) */
+ {211, 120, 1280, 798, 1688, 1066}, /* ; 06 (1024x768x75Hz) */
+ {1, 1, 1688, 1066, 1688, 1066} /* ; 07 (1280x1024x75Hz) */
};
-static struct XGI330_LCDDataStruct XGI_CetLCD1280x1024x75Data[] =
-{
- {1,1,1688,1066,1688,1066}, /* ; 00 (320x200,320x400,640x200,640x400) */
- {1,1,1688,1066,1688,1066}, /* ; 01 (320x350,640x350) */
- {1,1,1688,1066,1688,1066}, /* ; 02 (360x400,720x400) */
- {1,1,1688,1066,1688,1066}, /* ; 03 (720x350) */
- {1,1,1688,1066,1688,1066}, /* ; 04 (640x480x75Hz) */
- {1,1,1688,1066,1688,1066}, /* ; 05 (800x600x75Hz) */
- {1,1,1688,1066,1688,1066}, /* ; 06 (1024x768x75Hz) */
- {1,1,1688,1066,1688,1066} /* ; 07 (1280x1024x75Hz) */
+static struct XGI330_LCDDataStruct XGI_CetLCD1280x1024x75Data[] = {
+ {1, 1, 1688, 1066, 1688, 1066}, /* ; 00 (320x200,320x400,
+ 640x200,640x400) */
+ {1, 1, 1688, 1066, 1688, 1066}, /* ; 01 (320x350,640x350) */
+ {1, 1, 1688, 1066, 1688, 1066}, /* ; 02 (360x400,720x400) */
+ {1, 1, 1688, 1066, 1688, 1066}, /* ; 03 (720x350) */
+ {1, 1, 1688, 1066, 1688, 1066}, /* ; 04 (640x480x75Hz) */
+ {1, 1, 1688, 1066, 1688, 1066}, /* ; 05 (800x600x75Hz) */
+ {1, 1, 1688, 1066, 1688, 1066}, /* ; 06 (1024x768x75Hz) */
+ {1, 1, 1688, 1066, 1688, 1066} /* ; 07 (1280x1024x75Hz) */
};
-static struct XGI330_LCDDataStruct XGI_NoScalingDatax75[] =
-{
- {1,1,800,449,800,449 }, /* ; 00 (320x200,320x400,640x200,640x400) */
- {1,1,800,449,800,449 }, /* ; 01 (320x350,640x350) */
- {1,1,900,449,900,449 }, /* ; 02 (360x400,720x400) */
- {1,1,900,449,900,449 }, /* ; 03 (720x350) */
- {1,1,840,500,840,500 }, /* ; 04 (640x480x75Hz) */
- {1,1,1056,625,1056,625 }, /* ; 05 (800x600x75Hz) */
- {1,1,1312,800,1312,800 }, /* ; 06 (1024x768x75Hz) */
- {1,1,1688,1066,1688,1066}, /* ; 07 (1280x1024x75Hz) */
- {1,1,1688,1066,1688,1066}, /* ; 08 (1400x1050x75Hz) ;;[ycchen] 12/19/02 */
- {1,1,2160,1250,2160,1250}, /* ; 09 (1600x1200x75Hz) */
- {1,1,1688,806,1688,806 } /* ; 0A (1280x768x75Hz) */
+static struct XGI330_LCDDataStruct XGI_NoScalingDatax75[] = {
+ {1, 1, 800, 449, 800, 449}, /* ; 00 (320x200, 320x400,
+ 640x200, 640x400) */
+ {1, 1, 800, 449, 800, 449}, /* ; 01 (320x350, 640x350) */
+ {1, 1, 900, 449, 900, 449}, /* ; 02 (360x400, 720x400) */
+ {1, 1, 900, 449, 900, 449}, /* ; 03 (720x350) */
+ {1, 1, 840, 500, 840, 500}, /* ; 04 (640x480x75Hz) */
+ {1, 1, 1056, 625, 1056, 625}, /* ; 05 (800x600x75Hz) */
+ {1, 1, 1312, 800, 1312, 800}, /* ; 06 (1024x768x75Hz) */
+ {1, 1, 1688, 1066, 1688, 1066}, /* ; 07 (1280x1024x75Hz) */
+ {1, 1, 1688, 1066, 1688, 1066}, /* ; 08 (1400x1050x75Hz)
+ ;;[ycchen] 12/19/02 */
+ {1, 1, 2160, 1250, 2160, 1250}, /* ; 09 (1600x1200x75Hz) */
+ {1, 1, 1688, 806, 1688, 806} /* ; 0A (1280x768x75Hz) */
};
-static struct XGI330_LCDDataDesStruct XGI_ExtLCDDes1024x768Data[] =
-{
- { 9,1057,0, 771 }, /* ; 00 (320x200,320x400,640x200,640x400) */
- { 9,1057,0, 771 }, /* ; 01 (320x350,640x350) */
- { 9,1057,0, 771 }, /* ; 02 (360x400,720x400) */
- { 9,1057,0, 771 }, /* ; 03 (720x350) */
- { 9,1057,0, 771 }, /* ; 04 (640x480x60Hz) */
- { 9,1057,0, 771 }, /* ; 05 (800x600x60Hz) */
- { 9,1057,805, 770 } /* ; 06 (1024x768x60Hz) */
+static struct XGI330_LCDDataDesStruct XGI_ExtLCDDes1024x768Data[] = {
+ {9, 1057, 0, 771}, /* ; 00 (320x200,320x400,640x200,640x400) */
+ {9, 1057, 0, 771}, /* ; 01 (320x350,640x350) */
+ {9, 1057, 0, 771}, /* ; 02 (360x400,720x400) */
+ {9, 1057, 0, 771}, /* ; 03 (720x350) */
+ {9, 1057, 0, 771}, /* ; 04 (640x480x60Hz) */
+ {9, 1057, 0, 771}, /* ; 05 (800x600x60Hz) */
+ {9, 1057, 805, 770} /* ; 06 (1024x768x60Hz) */
};
-static struct XGI330_LCDDataDesStruct XGI_StLCDDes1024x768Data[] =
-{
- { 9,1057,737,703 }, /* ; 00 (320x200,320x400,640x200,640x400) */
- { 9,1057,686,651 }, /* ; 01 (320x350,640x350) */
- { 9,1057,737,703 }, /* ; 02 (360x400,720x400) */
- { 9,1057,686,651 }, /* ; 03 (720x350) */
- { 9,1057,776,741 }, /* ; 04 (640x480x60Hz) */
- { 9,1057, 0 ,771 }, /* ; 05 (800x600x60Hz) */
- { 9,1057,805,770 } /* ; 06 (1024x768x60Hz) */
+static struct XGI330_LCDDataDesStruct XGI_StLCDDes1024x768Data[] = {
+ {9, 1057, 737, 703}, /* ; 00 (320x200,320x400,640x200,640x400) */
+ {9, 1057, 686, 651}, /* ; 01 (320x350,640x350) */
+ {9, 1057, 737, 703}, /* ; 02 (360x400,720x400) */
+ {9, 1057, 686, 651}, /* ; 03 (720x350) */
+ {9, 1057, 776, 741}, /* ; 04 (640x480x60Hz) */
+ {9, 1057, 0, 771}, /* ; 05 (800x600x60Hz) */
+ {9, 1057, 805, 770} /* ; 06 (1024x768x60Hz) */
};
-static struct XGI330_LCDDataDesStruct XGI_CetLCDDes1024x768Data[] =
-{
- { 1152,856,622,587 }, /* ; 00 (320x200,320x400,640x200,640x400) */
- { 1152,856,597,562 }, /* ; 01 (320x350,640x350) */
- { 1152,856,622,587 }, /* ; 02 (360x400,720x400) */
- { 1152,856,597,562 }, /* ; 03 (720x350) */
- { 1152,856,662,627 }, /* ; 04 (640x480x60Hz) */
- { 1232,936,722,687 }, /* ; 05 (800x600x60Hz) */
- { 0,1048,805,770 } /* ; 06 (1024x768x60Hz) */
+static struct XGI330_LCDDataDesStruct XGI_CetLCDDes1024x768Data[] = {
+ {1152, 856, 622, 587}, /* ; 00 (320x200,320x400,640x200,640x400) */
+ {1152, 856, 597, 562}, /* ; 01 (320x350,640x350) */
+ {1152, 856, 622, 587}, /* ; 02 (360x400,720x400) */
+ {1152, 856, 597, 562}, /* ; 03 (720x350) */
+ {1152, 856, 662, 627}, /* ; 04 (640x480x60Hz) */
+ {1232, 936, 722, 687}, /* ; 05 (800x600x60Hz) */
+ {0, 1048, 805, 770} /* ; 06 (1024x768x60Hz) */
};
-static struct XGI330_LCDDataDesStruct XGI_ExtLCDDLDes1280x1024Data[] =
-{
- { 18,1346,981,940 },/* 00 (320x200,320x400,640x200,640x400) */
- { 18,1346,926,865 },/* 01 (320x350,640x350) */
- { 18,1346,981,940 },/* 02 (360x400,720x400) */
- { 18,1346,926,865 },/* 03 (720x350) */
- { 18,1346,0,1025 },/* 04 (640x480x60Hz) */
- { 18,1346,0,1025 },/* 05 (800x600x60Hz) */
- { 18,1346,1065,1024 },/* 06 (1024x768x60Hz) */
- { 18,1346,1065,1024 }/* 07 (1280x1024x60Hz) */
+static struct XGI330_LCDDataDesStruct XGI_ExtLCDDLDes1280x1024Data[] = {
+ {18, 1346, 981, 940}, /* 00 (320x200,320x400,640x200,640x400) */
+ {18, 1346, 926, 865}, /* 01 (320x350,640x350) */
+ {18, 1346, 981, 940}, /* 02 (360x400,720x400) */
+ {18, 1346, 926, 865}, /* 03 (720x350) */
+ {18, 1346, 0, 1025}, /* 04 (640x480x60Hz) */
+ {18, 1346, 0, 1025}, /* 05 (800x600x60Hz) */
+ {18, 1346, 1065, 1024}, /* 06 (1024x768x60Hz) */
+ {18, 1346, 1065, 1024} /* 07 (1280x1024x60Hz) */
};
-static struct XGI330_LCDDataDesStruct XGI_StLCDDLDes1280x1024Data[] =
-{
- { 18,1346,970,907 },/* 00 (320x200,320x400,640x200,640x400) */
- { 18,1346,917,854 },/* 01 (320x350,640x350) */
- { 18,1346,970,907 },/* 02 (360x400,720x400) */
- { 18,1346,917,854 },/* 03 (720x350) */
- { 18,1346,0,1025 },/* 04 (640x480x60Hz) */
- { 18,1346,0,1025 },/* 05 (800x600x60Hz) */
- { 18,1346,1065,1024 },/* 06 (1024x768x60Hz) */
- { 18,1346,1065,1024 }/* 07 (1280x1024x60Hz) */
+static struct XGI330_LCDDataDesStruct XGI_StLCDDLDes1280x1024Data[] = {
+ {18, 1346, 970, 907}, /* 00 (320x200,320x400,640x200,640x400) */
+ {18, 1346, 917, 854}, /* 01 (320x350,640x350) */
+ {18, 1346, 970, 907}, /* 02 (360x400,720x400) */
+ {18, 1346, 917, 854}, /* 03 (720x350) */
+ {18, 1346, 0, 1025}, /* 04 (640x480x60Hz) */
+ {18, 1346, 0, 1025}, /* 05 (800x600x60Hz) */
+ {18, 1346, 1065, 1024}, /* 06 (1024x768x60Hz) */
+ {18, 1346, 1065, 1024} /* 07 (1280x1024x60Hz) */
};
-static struct XGI330_LCDDataDesStruct XGI_CetLCDDLDes1280x1024Data[] =
-{
- { 1368,1008,752,711 }, /* 00 (320x200,320x400,640x200,640x400) */
- { 1368,1008,729,688 }, /* 01 (320x350,640x350) */
- { 1368,1008,752,711 }, /* 02 (360x400,720x400) */
- { 1368,1008,729,688 }, /* 03 (720x350) */
- { 1368,1008,794,753 }, /* 04 (640x480x60Hz) */
- { 1448,1068,854,813 }, /* 05 (800x600x60Hz) */
- { 1560,1200,938,897 }, /* 06 (1024x768x60Hz) */
- { 18,1346,1065,1024 } /* 07 (1280x1024x60Hz) */
+static struct XGI330_LCDDataDesStruct XGI_CetLCDDLDes1280x1024Data[] = {
+ {1368, 1008, 752, 711}, /* 00 (320x200,320x400,640x200,640x400) */
+ {1368, 1008, 729, 688}, /* 01 (320x350,640x350) */
+ {1368, 1008, 752, 711}, /* 02 (360x400,720x400) */
+ {1368, 1008, 729, 688}, /* 03 (720x350) */
+ {1368, 1008, 794, 753}, /* 04 (640x480x60Hz) */
+ {1448, 1068, 854, 813}, /* 05 (800x600x60Hz) */
+ {1560, 1200, 938, 897}, /* 06 (1024x768x60Hz) */
+ {18, 1346, 1065, 1024} /* 07 (1280x1024x60Hz) */
};
-static struct XGI330_LCDDataDesStruct XGI_ExtLCDDes1280x1024Data[] =
-{
- { 9,1337,981,940 }, /* ; 00 (320x200,320x400,640x200,640x400) */
- { 9,1337,926,884 }, /* ; 01 (320x350,640x350) alan, 2003/09/30 */
- { 9,1337,981,940 }, /* ; 02 (360x400,720x400) */
- { 9,1337,926,884 }, /* ; 03 (720x350) alan, 2003/09/30 */
- { 9,1337,0,1025 }, /* ; 04 (640x480x60Hz) */
- { 9,1337,0,1025 }, /* ; 05 (800x600x60Hz) */
- { 9,1337,1065,1024 }, /* ; 06 (1024x768x60Hz) */
- { 9,1337,1065,1024 } /* ; 07 (1280x1024x60Hz) */
+static struct XGI330_LCDDataDesStruct XGI_ExtLCDDes1280x1024Data[] = {
+ {9, 1337, 981, 940}, /* ; 00 (320x200,320x400,640x200,640x400) */
+ {9, 1337, 926, 884}, /* ; 01 (320x350,640x350) alan, 2003/09/30 */
+ {9, 1337, 981, 940}, /* ; 02 (360x400,720x400) */
+ {9, 1337, 926, 884}, /* ; 03 (720x350) alan, 2003/09/30 */
+ {9, 1337, 0, 1025}, /* ; 04 (640x480x60Hz) */
+ {9, 1337, 0, 1025}, /* ; 05 (800x600x60Hz) */
+ {9, 1337, 1065, 1024}, /* ; 06 (1024x768x60Hz) */
+ {9, 1337, 1065, 1024} /* ; 07 (1280x1024x60Hz) */
};
-static struct XGI330_LCDDataDesStruct XGI_StLCDDes1280x1024Data[] =
-{
- { 9,1337,970,907 }, /* ; 00 (320x200,320x400,640x200,640x400) */
- { 9,1337,917,854 }, /* ; 01 (320x350,640x350) */
- { 9,1337,970,907 }, /* ; 02 (360x400,720x400) */
- { 9,1337,917,854 }, /* ; 03 (720x350) */
- { 9,1337,0,1025 }, /* ; 04 (640x480x60Hz) */
- { 9,1337,0,1025 }, /* ; 05 (800x600x60Hz) */
- { 9,1337,1065,1024 }, /* ; 06 (1024x768x60Hz) */
- { 9,1337,1065,1024 } /* ; 07 (1280x1024x60Hz) */
+static struct XGI330_LCDDataDesStruct XGI_StLCDDes1280x1024Data[] = {
+ {9, 1337, 970, 907}, /* ; 00 (320x200,320x400,640x200,640x400) */
+ {9, 1337, 917, 854}, /* ; 01 (320x350,640x350) */
+ {9, 1337, 970, 907}, /* ; 02 (360x400,720x400) */
+ {9, 1337, 917, 854}, /* ; 03 (720x350) */
+ {9, 1337, 0, 1025}, /* ; 04 (640x480x60Hz) */
+ {9, 1337, 0, 1025}, /* ; 05 (800x600x60Hz) */
+ {9, 1337, 1065, 1024}, /* ; 06 (1024x768x60Hz) */
+ {9, 1337, 1065, 1024} /* ; 07 (1280x1024x60Hz) */
};
-static struct XGI330_LCDDataDesStruct XGI_CetLCDDes1280x1024Data[] =
-{
- { 1368,1008,752,711 }, /* 00 (320x200,320x400,640x200,640x400) */
- { 1368,1008,729,688 }, /* 01 (320x350,640x350) */
- { 1368,1008,752,711 }, /* 02 (360x400,720x400) */
- { 1368,1008,729,688 }, /* 03 (720x350) */
- { 1368,1008,794,753 }, /* 04 (640x480x60Hz) */
- { 1448,1068,854,813 }, /* 05 (800x600x60Hz) */
- { 1560,1200,938,897 }, /* 06 (1024x768x60Hz) */
- { 9,1337,1065,1024 } /* 07 (1280x1024x60Hz) */
+static struct XGI330_LCDDataDesStruct XGI_CetLCDDes1280x1024Data[] = {
+ {1368, 1008, 752, 711}, /* 00 (320x200,320x400,640x200,640x400) */
+ {1368, 1008, 729, 688}, /* 01 (320x350,640x350) */
+ {1368, 1008, 752, 711}, /* 02 (360x400,720x400) */
+ {1368, 1008, 729, 688}, /* 03 (720x350) */
+ {1368, 1008, 794, 753}, /* 04 (640x480x60Hz) */
+ {1448, 1068, 854, 813}, /* 05 (800x600x60Hz) */
+ {1560, 1200, 938, 897}, /* 06 (1024x768x60Hz) */
+ {9, 1337, 1065, 1024} /* 07 (1280x1024x60Hz) */
};
-static struct XGI330_LCDDataDesStruct XGI_StLCDDLDes1400x1050Data[] =
-{
- { 18,1464,0,1051 }, /* 00 (320x200,320x400,640x200,640x400) */
- { 18,1464,0,1051 }, /* 01 (320x350,640x350) */
- { 18,1464,0,1051 }, /* 02 (360x400,720x400) */
- { 18,1464,0,1051 }, /* 03 (720x350) */
- { 18,1464,0,1051 }, /* 04 (640x480x60Hz) */
- { 18,1464,0,1051 }, /* 05 (800x600x60Hz) */
- { 18,1464,0,1051 }, /* 06 (1024x768x60Hz) */
- { 1646,1406,1053,1038 }, /* 07 (1280x1024x60Hz) */
- { 18,1464,0,1051 } /* 08 (1400x1050x60Hz) */
+static struct XGI330_LCDDataDesStruct XGI_StLCDDLDes1400x1050Data[] = {
+ {18, 1464, 0, 1051}, /* 00 (320x200,320x400,640x200,640x400) */
+ {18, 1464, 0, 1051}, /* 01 (320x350,640x350) */
+ {18, 1464, 0, 1051}, /* 02 (360x400,720x400) */
+ {18, 1464, 0, 1051}, /* 03 (720x350) */
+ {18, 1464, 0, 1051}, /* 04 (640x480x60Hz) */
+ {18, 1464, 0, 1051}, /* 05 (800x600x60Hz) */
+ {18, 1464, 0, 1051}, /* 06 (1024x768x60Hz) */
+ {1646, 1406, 1053, 1038}, /* 07 (1280x1024x60Hz) */
+ {18, 1464, 0, 1051} /* 08 (1400x1050x60Hz) */
};
-static struct XGI330_LCDDataDesStruct XGI_ExtLCDDLDes1400x1050Data[] =
-{
- { 18,1464,0,1051 }, /* 00 (320x200,320x400,640x200,640x400) */
- { 18,1464,0,1051 }, /* 01 (320x350,640x350) */
- { 18,1464,0,1051 }, /* 02 (360x400,720x400) */
- { 18,1464,0,1051 }, /* 03 (720x350) */
- { 18,1464,0,1051 }, /* 04 (640x480x60Hz) */
- { 18,1464,0,1051 }, /* 05 (800x600x60Hz) */
- { 18,1464,0,1051 }, /* 06 (1024x768x60Hz) */
- { 1646,1406,1053,1038 }, /* 07 (1280x1024x60Hz) */
- { 18,1464,0,1051 } /* 08 (1400x1050x60Hz) */
+static struct XGI330_LCDDataDesStruct XGI_ExtLCDDLDes1400x1050Data[] = {
+ {18, 1464, 0, 1051}, /* 00 (320x200,320x400,640x200,640x400) */
+ {18, 1464, 0, 1051}, /* 01 (320x350,640x350) */
+ {18, 1464, 0, 1051}, /* 02 (360x400,720x400) */
+ {18, 1464, 0, 1051}, /* 03 (720x350) */
+ {18, 1464, 0, 1051}, /* 04 (640x480x60Hz) */
+ {18, 1464, 0, 1051}, /* 05 (800x600x60Hz) */
+ {18, 1464, 0, 1051}, /* 06 (1024x768x60Hz) */
+ {1646, 1406, 1053, 1038}, /* 07 (1280x1024x60Hz) */
+ {18, 1464, 0, 1051} /* 08 (1400x1050x60Hz) */
};
-static struct XGI330_LCDDataDesStruct XGI_StLCDDes1400x1050Data[] =
-{
- { 9,1455,0,1051 },/* 00 (320x200,320x400,640x200,640x400) */
- { 9,1455,0,1051 },/* 01 (320x350,640x350) */
- { 9,1455,0,1051 },/* 02 (360x400,720x400) */
- { 9,1455,0,1051 },/* 03 (720x350) */
- { 9,1455,0,1051 },/* 04 (640x480x60Hz) */
- { 9,1455,0,1051 },/* 05 (800x600x60Hz) */
- { 9,1455,0,1051 },/* 06 (1024x768x60Hz) */
- { 1637,1397,1053,1038 },/* 07 (1280x1024x60Hz) */
- { 9,1455,0,1051 } /* 08 (1400x1050x60Hz) */
+static struct XGI330_LCDDataDesStruct XGI_StLCDDes1400x1050Data[] = {
+ {9, 1455, 0, 1051}, /* 00 (320x200,320x400,640x200,640x400) */
+ {9, 1455, 0, 1051}, /* 01 (320x350,640x350) */
+ {9, 1455, 0, 1051}, /* 02 (360x400,720x400) */
+ {9, 1455, 0, 1051}, /* 03 (720x350) */
+ {9, 1455, 0, 1051}, /* 04 (640x480x60Hz) */
+ {9, 1455, 0, 1051}, /* 05 (800x600x60Hz) */
+ {9, 1455, 0, 1051}, /* 06 (1024x768x60Hz) */
+ {1637, 1397, 1053, 1038}, /* 07 (1280x1024x60Hz) */
+ {9, 1455, 0, 1051} /* 08 (1400x1050x60Hz) */
};
-static struct XGI330_LCDDataDesStruct XGI_ExtLCDDes1400x1050Data[] =
-{
- { 9,1455,0,1051 },/* 00 (320x200,320x400,640x200,640x400) */
- { 9,1455,0,1051 },/* 01 (320x350,640x350) */
- { 9,1455,0,1051 },/* 02 (360x400,720x400) */
- { 9,1455,0,1051 },/* 03 (720x350) */
- { 9,1455,0,1051 },/* 04 (640x480x60Hz) */
- { 9,1455,0,1051 },/* 05 (800x600x60Hz) */
- { 9,1455,0,1051 },/* 06 (1024x768x60Hz) */
- { 1637,1397,1053,1038 },/* 07 (1280x1024x60Hz) */
- { 9,1455,0,1051 } /* 08 (1400x1050x60Hz) */
+static struct XGI330_LCDDataDesStruct XGI_ExtLCDDes1400x1050Data[] = {
+ {9, 1455, 0, 1051}, /* 00 (320x200,320x400,640x200,640x400) */
+ {9, 1455, 0, 1051}, /* 01 (320x350,640x350) */
+ {9, 1455, 0, 1051}, /* 02 (360x400,720x400) */
+ {9, 1455, 0, 1051}, /* 03 (720x350) */
+ {9, 1455, 0, 1051}, /* 04 (640x480x60Hz) */
+ {9, 1455, 0, 1051}, /* 05 (800x600x60Hz) */
+ {9, 1455, 0, 1051}, /* 06 (1024x768x60Hz) */
+ {1637, 1397, 1053, 1038}, /* 07 (1280x1024x60Hz) */
+ {9, 1455, 0, 1051} /* 08 (1400x1050x60Hz) */
};
-static struct XGI330_LCDDataDesStruct XGI_CetLCDDes1400x1050Data[] =
-{
- { 1308,1068,781,766 }, /* 00 (320x200,320x400,640x200,640x400) */
- { 1308,1068,781,766 }, /* 01 (320x350,640x350) */
- { 1308,1068,781,766 }, /* 02 (360x400,720x400) */
- { 1308,1068,781,766 }, /* 03 (720x350) */
- { 1308,1068,781,766 }, /* 04 (640x480x60Hz) */
- { 1388,1148,841,826 }, /* 05 (800x600x60Hz) */
- { 1490,1250,925,910 }, /* 06 (1024x768x60Hz) */
- { 1646,1406,1053,1038 }, /* 07 (1280x1024x60Hz) */
- { 18,1464,0,1051 } /* 08 (1400x1050x60Hz) */
+static struct XGI330_LCDDataDesStruct XGI_CetLCDDes1400x1050Data[] = {
+ {1308, 1068, 781, 766}, /* 00 (320x200,320x400,640x200,640x400) */
+ {1308, 1068, 781, 766}, /* 01 (320x350,640x350) */
+ {1308, 1068, 781, 766}, /* 02 (360x400,720x400) */
+ {1308, 1068, 781, 766}, /* 03 (720x350) */
+ {1308, 1068, 781, 766}, /* 04 (640x480x60Hz) */
+ {1388, 1148, 841, 826}, /* 05 (800x600x60Hz) */
+ {1490, 1250, 925, 910}, /* 06 (1024x768x60Hz) */
+ {1646, 1406, 1053, 1038}, /* 07 (1280x1024x60Hz) */
+ {18, 1464, 0, 1051} /* 08 (1400x1050x60Hz) */
};
-static struct XGI330_LCDDataDesStruct XGI_CetLCDDes1400x1050Data2[] =
-{
- { 0,1448,0,1051 }, /* 00 (320x200,320x400,640x200,640x400) */
- { 0,1448,0,1051 }, /* 01 (320x350,640x350) */
- { 0,1448,0,1051 }, /* 02 (360x400,720x400) */
- { 0,1448,0,1051 }, /* 03 (720x350) */
- { 0,1448,0,1051 } /* 04 (640x480x60Hz) */
+static struct XGI330_LCDDataDesStruct XGI_CetLCDDes1400x1050Data2[] = {
+ {0, 1448, 0, 1051}, /* 00 (320x200,320x400,640x200,640x400) */
+ {0, 1448, 0, 1051}, /* 01 (320x350,640x350) */
+ {0, 1448, 0, 1051}, /* 02 (360x400,720x400) */
+ {0, 1448, 0, 1051}, /* 03 (720x350) */
+ {0, 1448, 0, 1051} /* 04 (640x480x60Hz) */
};
-
-
-static struct XGI330_LCDDataDesStruct XGI_ExtLCDDLDes1600x1200Data[] =
-{
- { 18,1682,0,1201 }, /* 00 (320x200,320x400,640x200,640x400) */
- { 18,1682,0,1201 }, /* 01 (320x350,640x350) */
- { 18,1682,0,1201 }, /* 02 (360x400,720x400) */
- { 18,1682,0,1201 }, /* 03 (720x350) */
- { 18,1682,0,1201 }, /* 04 (640x480x60Hz) */
- { 18,1682,0,1201 }, /* 05 (800x600x60Hz) */
- { 18,1682,0,1201 }, /* 06 (1024x768x60Hz) */
- { 18,1682,0,1201 }, /* 07 (1280x1024x60Hz) */
- { 18,1682,0,1201 }, /* 08 (1400x1050x60Hz) */
- { 18,1682,0,1201 } /* 09 (1600x1200x60Hz) */
+static struct XGI330_LCDDataDesStruct XGI_ExtLCDDLDes1600x1200Data[] = {
+ {18, 1682, 0, 1201}, /* 00 (320x200,320x400,640x200,640x400) */
+ {18, 1682, 0, 1201}, /* 01 (320x350,640x350) */
+ {18, 1682, 0, 1201}, /* 02 (360x400,720x400) */
+ {18, 1682, 0, 1201}, /* 03 (720x350) */
+ {18, 1682, 0, 1201}, /* 04 (640x480x60Hz) */
+ {18, 1682, 0, 1201}, /* 05 (800x600x60Hz) */
+ {18, 1682, 0, 1201}, /* 06 (1024x768x60Hz) */
+ {18, 1682, 0, 1201}, /* 07 (1280x1024x60Hz) */
+ {18, 1682, 0, 1201}, /* 08 (1400x1050x60Hz) */
+ {18, 1682, 0, 1201} /* 09 (1600x1200x60Hz) */
};
-static struct XGI330_LCDDataDesStruct XGI_StLCDDLDes1600x1200Data[] =
-{
- { 18,1682,1150,1101 }, /* 00 (320x200,320x400,640x200,640x400) */
- { 18,1682,1083,1034 }, /* 01 (320x350,640x350) */
- { 18,1682,1150,1101 }, /* 02 (360x400,720x400) */
- { 18,1682,1083,1034 }, /* 03 (720x350) */
- { 18,1682,0,1201 }, /* 04 (640x480x60Hz) */
- { 18,1682,0,1201 }, /* 05 (800x600x60Hz) */
- { 18,1682,0,1201 }, /* 06 (1024x768x60Hz) */
- { 18,1682,1232,1183 }, /* 07 (1280x1024x60Hz) */
- { 18,1682,0,1201 }, /* 08 (1400x1050x60Hz) */
- { 18,1682,0,1201 } /* 09 (1600x1200x60Hz) */
+static struct XGI330_LCDDataDesStruct XGI_StLCDDLDes1600x1200Data[] = {
+ {18, 1682, 1150, 1101}, /* 00 (320x200,320x400,640x200,640x400) */
+ {18, 1682, 1083, 1034}, /* 01 (320x350,640x350) */
+ {18, 1682, 1150, 1101}, /* 02 (360x400,720x400) */
+ {18, 1682, 1083, 1034}, /* 03 (720x350) */
+ {18, 1682, 0, 1201}, /* 04 (640x480x60Hz) */
+ {18, 1682, 0, 1201}, /* 05 (800x600x60Hz) */
+ {18, 1682, 0, 1201}, /* 06 (1024x768x60Hz) */
+ {18, 1682, 1232, 1183}, /* 07 (1280x1024x60Hz) */
+ {18, 1682, 0, 1201}, /* 08 (1400x1050x60Hz) */
+ {18, 1682, 0, 1201} /* 09 (1600x1200x60Hz) */
};
-static struct XGI330_LCDDataDesStruct XGI_ExtLCDDes1600x1200Data[] =
-{
- { 9,1673,0,1201 },/* 00 (320x200,320x400,640x200,640x400) */
- { 9,1673,0,1201 },/* 01 (320x350,640x350) */
- { 9,1673,0,1201 },/* 02 (360x400,720x400) */
- { 9,1673,0,1201 },/* 03 (720x350) */
- { 9,1673,0,1201 },/* 04 (640x480x60Hz) */
- { 9,1673,0,1201 },/* 05 (800x600x60Hz) */
- { 9,1673,0,1201 },/* 06 (1024x768x60Hz) */
- { 9,1673,0,1201 },/* 07 (1280x1024x60Hz) */
- { 9,1673,0,1201 },/* 08 (1400x1050x60Hz) */
- { 9,1673,0,1201 } /* 09 (1600x1200x60Hz) */
+static struct XGI330_LCDDataDesStruct XGI_ExtLCDDes1600x1200Data[] = {
+ {9, 1673, 0, 1201}, /* 00 (320x200,320x400,640x200,640x400) */
+ {9, 1673, 0, 1201}, /* 01 (320x350,640x350) */
+ {9, 1673, 0, 1201}, /* 02 (360x400,720x400) */
+ {9, 1673, 0, 1201}, /* 03 (720x350) */
+ {9, 1673, 0, 1201}, /* 04 (640x480x60Hz) */
+ {9, 1673, 0, 1201}, /* 05 (800x600x60Hz) */
+ {9, 1673, 0, 1201}, /* 06 (1024x768x60Hz) */
+ {9, 1673, 0, 1201}, /* 07 (1280x1024x60Hz) */
+ {9, 1673, 0, 1201}, /* 08 (1400x1050x60Hz) */
+ {9, 1673, 0, 1201} /* 09 (1600x1200x60Hz) */
};
-static struct XGI330_LCDDataDesStruct XGI_StLCDDes1600x1200Data[] =
-{
- { 9,1673,1150,1101 },/* 00 (320x200,320x400,640x200,640x400) */
- { 9,1673,1083,1034 },/* 01 (320x350,640x350) */
- { 9,1673,1150,1101 },/* 02 (360x400,720x400) */
- { 9,1673,1083,1034 },/* 03 (720x350) */
- { 9,1673,0,1201 },/* 04 (640x480x60Hz) */
- { 9,1673,0,1201 },/* 05 (800x600x60Hz) */
- { 9,1673,0,1201 },/* 06 (1024x768x60Hz) */
- { 9,1673,1232,1183 },/* 07 (1280x1024x60Hz) */
- { 9,1673,0,1201 },/* 08 (1400x1050x60Hz) */
- { 9,1673,0,1201 } /* 09 (1600x1200x60Hz) */
+static struct XGI330_LCDDataDesStruct XGI_StLCDDes1600x1200Data[] = {
+ {9, 1673, 1150, 1101}, /* 00 (320x200,320x400,640x200,640x400) */
+ {9, 1673, 1083, 1034}, /* 01 (320x350,640x350) */
+ {9, 1673, 1150, 1101}, /* 02 (360x400,720x400) */
+ {9, 1673, 1083, 1034}, /* 03 (720x350) */
+ {9, 1673, 0, 1201}, /* 04 (640x480x60Hz) */
+ {9, 1673, 0, 1201}, /* 05 (800x600x60Hz) */
+ {9, 1673, 0, 1201}, /* 06 (1024x768x60Hz) */
+ {9, 1673, 1232, 1183}, /* 07 (1280x1024x60Hz) */
+ {9, 1673, 0, 1201}, /* 08 (1400x1050x60Hz) */
+ {9, 1673, 0, 1201} /* 09 (1600x1200x60Hz) */
};
-static struct XGI330_LCDDataDesStruct2 XGI_NoScalingDesData[] =
-{
- { 9,657,448,405,96,2 }, /* 00 (320x200,320x400,640x200,640x400) */
- { 9,657,448,355,96,2 }, /* 01 (320x350,640x350) */
- { 9,657,448,405,96,2 }, /* 02 (360x400,720x400) */
- { 9,657,448,355,96,2 }, /* 03 (720x350) */
- { 9,657,1,483,96,2 }, /* 04 (640x480x60Hz) */
- { 9,849,627,600,128,4 }, /* 05 (800x600x60Hz) */
- { 9,1057,805,770,0136,6 }, /* 06 (1024x768x60Hz) */
- { 9,1337,0,1025,112,3 }, /* 07 (1280x1024x60Hz) */
- { 9,1457,0,1051,112,3 }, /* 08 (1400x1050x60Hz) }, //;[ycchen] 12/19/02 */
- { 9,1673,0,1201,192,3 }, /* 09 (1600x1200x60Hz) */
- { 9,1337,0,771,112,6 } /* 0A (1280x768x60Hz) */
+static struct XGI330_LCDDataDesStruct2 XGI_NoScalingDesData[] = {
+ {9, 657, 448, 405, 96, 2}, /* 00 (320x200,320x400,
+ 640x200,640x400) */
+ {9, 657, 448, 355, 96, 2}, /* 01 (320x350,640x350) */
+ {9, 657, 448, 405, 96, 2}, /* 02 (360x400,720x400) */
+ {9, 657, 448, 355, 96, 2}, /* 03 (720x350) */
+ {9, 657, 1, 483, 96, 2}, /* 04 (640x480x60Hz) */
+ {9, 849, 627, 600, 128, 4}, /* 05 (800x600x60Hz) */
+ {9, 1057, 805, 770, 0136, 6}, /* 06 (1024x768x60Hz) */
+ {9, 1337, 0, 1025, 112, 3}, /* 07 (1280x1024x60Hz) */
+ {9, 1457, 0, 1051, 112, 3}, /* 08 (1400x1050x60Hz) },
+ //;[ycchen] 12/19/02 */
+ {9, 1673, 0, 1201, 192, 3}, /* 09 (1600x1200x60Hz) */
+ {9, 1337, 0, 771, 112, 6} /* 0A (1280x768x60Hz) */
};
-static struct XGI330_LCDDataDesStruct XGI_ExtLCDDes1024x768x75Data[] = /* ;;1024x768x75Hz */
-{
- {9,1049,0,769}, /* ; 00 (320x200,320x400,640x200,640x400) */
- {9,1049,0,769}, /* ; 01 (320x350,640x350) */
- {9,1049,0,769}, /* ; 02 (360x400,720x400) */
- {9,1049,0,769}, /* ; 03 (720x350) */
- {9,1049,0,769}, /* ; 04 (640x480x75Hz) */
- {9,1049,0,769}, /* ; 05 (800x600x75Hz) */
- {9,1049,0,769} /* ; 06 (1024x768x75Hz) */
+/* ;;1024x768x75Hz */
+static struct XGI330_LCDDataDesStruct XGI_ExtLCDDes1024x768x75Data[] = {
+ {9, 1049, 0, 769}, /* ; 00 (320x200,320x400,640x200,640x400) */
+ {9, 1049, 0, 769}, /* ; 01 (320x350,640x350) */
+ {9, 1049, 0, 769}, /* ; 02 (360x400,720x400) */
+ {9, 1049, 0, 769}, /* ; 03 (720x350) */
+ {9, 1049, 0, 769}, /* ; 04 (640x480x75Hz) */
+ {9, 1049, 0, 769}, /* ; 05 (800x600x75Hz) */
+ {9, 1049, 0, 769} /* ; 06 (1024x768x75Hz) */
};
-static struct XGI330_LCDDataDesStruct XGI_StLCDDes1024x768x75Data[] =
-{
- {9,1049,0,769}, /* ; 00 (320x200,320x400,640x200,640x400) */
- {9,1049,0,769}, /* ; 01 (320x350,640x350) */
- {9,1049,0,769}, /* ; 02 (360x400,720x400) */
- {9,1049,0,769}, /* ; 03 (720x350) */
- {9,1049,0,769}, /* ; 04 (640x480x75Hz) */
- {9,1049,0,769}, /* ; 05 (800x600x75Hz) */
- {9,1049,0,769} /* ; 06 (1024x768x75Hz) */
+static struct XGI330_LCDDataDesStruct XGI_StLCDDes1024x768x75Data[] = {
+ {9, 1049, 0, 769}, /* ; 00 (320x200,320x400,640x200,640x400) */
+ {9, 1049, 0, 769}, /* ; 01 (320x350,640x350) */
+ {9, 1049, 0, 769}, /* ; 02 (360x400,720x400) */
+ {9, 1049, 0, 769}, /* ; 03 (720x350) */
+ {9, 1049, 0, 769}, /* ; 04 (640x480x75Hz) */
+ {9, 1049, 0, 769}, /* ; 05 (800x600x75Hz) */
+ {9, 1049, 0, 769} /* ; 06 (1024x768x75Hz) */
};
-static struct XGI330_LCDDataDesStruct XGI_CetLCDDes1024x768x75Data[] = /* ;;1024x768x75Hz */
-{
- {1152,856,622,587}, /* ; 00 (320x200,320x400,640x200,640x400) */
- {1152,856,597,562}, /* ; 01 (320x350,640x350) */
- {1192,896,622,587}, /* ; 02 (360x400,720x400) */
- {1192,896,597,562}, /* ; 03 (720x350) */
- {1129,857,656,625}, /* ; 04 (640x480x75Hz) */
- {1209,937,716,685}, /* ; 05 (800x600x75Hz) */
- {9,1049,0,769} /* ; 06 (1024x768x75Hz) */
+/* ;;1024x768x75Hz */
+static struct XGI330_LCDDataDesStruct XGI_CetLCDDes1024x768x75Data[] = {
+ {1152, 856, 622, 587}, /* ; 00 (320x200,320x400,640x200,640x400) */
+ {1152, 856, 597, 562}, /* ; 01 (320x350,640x350) */
+ {1192, 896, 622, 587}, /* ; 02 (360x400,720x400) */
+ {1192, 896, 597, 562}, /* ; 03 (720x350) */
+ {1129, 857, 656, 625}, /* ; 04 (640x480x75Hz) */
+ {1209, 937, 716, 685}, /* ; 05 (800x600x75Hz) */
+ {9, 1049, 0, 769} /* ; 06 (1024x768x75Hz) */
};
-static struct XGI330_LCDDataDesStruct XGI_ExtLCDDLDes1280x1024x75Data[] = /* ;;1280x1024x75Hz */
-{
- {18,1314,0,1025 },/* ; 00 (320x200,320x400,640x200,640x400) */
- {18,1314,0,1025 },/* ; 01 (320x350,640x350) */
- {18,1314,0,1025 },/* ; 02 (360x400,720x400) */
- {18,1314,0,1025 },/* ; 03 (720x350) */
- {18,1314,0,1025 },/* ; 04 (640x480x60Hz) */
- {18,1314,0,1025 },/* ; 05 (800x600x60Hz) */
- {18,1314,0,1025 },/* ; 06 (1024x768x60Hz) */
- {18,1314,0,1025 }/* ; 07 (1280x1024x60Hz) */
+/* ;;1280x1024x75Hz */
+static struct XGI330_LCDDataDesStruct XGI_ExtLCDDLDes1280x1024x75Data[] = {
+ {18, 1314, 0, 1025}, /* ; 00 (320x200,320x400,640x200,640x400) */
+ {18, 1314, 0, 1025}, /* ; 01 (320x350,640x350) */
+ {18, 1314, 0, 1025}, /* ; 02 (360x400,720x400) */
+ {18, 1314, 0, 1025}, /* ; 03 (720x350) */
+ {18, 1314, 0, 1025}, /* ; 04 (640x480x60Hz) */
+ {18, 1314, 0, 1025}, /* ; 05 (800x600x60Hz) */
+ {18, 1314, 0, 1025}, /* ; 06 (1024x768x60Hz) */
+ {18, 1314, 0, 1025} /* ; 07 (1280x1024x60Hz) */
};
-static struct XGI330_LCDDataDesStruct XGI_StLCDDLDes1280x1024x75Data[] =
-{
- {18,1314,0,1025 },/* ; 00 (320x200,320x400,640x200,640x400) */
- {18,1314,0,1025 },/* ; 01 (320x350,640x350) */
- {18,1314,0,1025 },/* ; 02 (360x400,720x400) */
- {18,1314,0,1025 },/* ; 03 (720x350) */
- {18,1314,0,1025 },/* ; 04 (640x480x60Hz) */
- {18,1314,0,1025 },/* ; 05 (800x600x60Hz) */
- {18,1314,0,1025 },/* ; 06 (1024x768x60Hz) */
- {18,1314,0,1025 }/* ; 07 (1280x1024x60Hz) */
+static struct XGI330_LCDDataDesStruct XGI_StLCDDLDes1280x1024x75Data[] = {
+ {18, 1314, 0, 1025}, /* ; 00 (320x200,320x400,640x200,640x400) */
+ {18, 1314, 0, 1025}, /* ; 01 (320x350,640x350) */
+ {18, 1314, 0, 1025}, /* ; 02 (360x400,720x400) */
+ {18, 1314, 0, 1025}, /* ; 03 (720x350) */
+ {18, 1314, 0, 1025}, /* ; 04 (640x480x60Hz) */
+ {18, 1314, 0, 1025}, /* ; 05 (800x600x60Hz) */
+ {18, 1314, 0, 1025}, /* ; 06 (1024x768x60Hz) */
+ {18, 1314, 0, 1025} /* ; 07 (1280x1024x60Hz) */
};
-static struct XGI330_LCDDataDesStruct XGI_CetLCDDLDes1280x1024x75Data[] = /* 1280x1024x75Hz */
-{
- {1368,1008,752,711}, /* ; 00 (320x200,320x400,640x200,640x400) */
- {1368,1008,729,688}, /* ; 01 (320x350,640x350) */
- {1408,1048,752,711}, /* ; 02 (360x400,720x400) */
- {1408,1048,729,688}, /* ; 03 (720x350) */
- {1377,985,794,753}, /* ; 04 (640x480x75Hz) */
- {1457,1065,854,813}, /* ; 05 (800x600x75Hz) */
- {1569,1177,938,897}, /* ; 06 (1024x768x75Hz) */
- {18,1314,0,1025} /* ; 07 (1280x1024x75Hz) */
+/* 1280x1024x75Hz */
+static struct XGI330_LCDDataDesStruct XGI_CetLCDDLDes1280x1024x75Data[] = {
+ {1368, 1008, 752, 711}, /* ; 00 (320x200,320x400,640x200,640x400) */
+ {1368, 1008, 729, 688}, /* ; 01 (320x350,640x350) */
+ {1408, 1048, 752, 711}, /* ; 02 (360x400,720x400) */
+ {1408, 1048, 729, 688}, /* ; 03 (720x350) */
+ {1377, 985, 794, 753}, /* ; 04 (640x480x75Hz) */
+ {1457, 1065, 854, 813}, /* ; 05 (800x600x75Hz) */
+ {1569, 1177, 938, 897}, /* ; 06 (1024x768x75Hz) */
+ {18, 1314, 0, 1025} /* ; 07 (1280x1024x75Hz) */
};
-static struct XGI330_LCDDataDesStruct XGI_ExtLCDDes1280x1024x75Data[] = /* ;;1280x1024x75Hz */
-{
- {9,1305,0,1025},/* ; 00 (320x200,320x400,640x200,640x400) */
- {9,1305,0,1025},/* ; 01 (320x350,640x350) */
- {9,1305,0,1025},/* ; 02 (360x400,720x400) */
- {9,1305,0,1025},/* ; 03 (720x350) */
- {9,1305,0,1025},/* ; 04 (640x480x60Hz) */
- {9,1305,0,1025},/* ; 05 (800x600x60Hz) */
- {9,1305,0,1025},/* ; 06 (1024x768x60Hz) */
- {9,1305,0,1025} /* ; 07 (1280x1024x60Hz) */
+/* ;;1280x1024x75Hz */
+static struct XGI330_LCDDataDesStruct XGI_ExtLCDDes1280x1024x75Data[] = {
+ {9, 1305, 0, 1025}, /* ; 00 (320x200,320x400,640x200,640x400) */
+ {9, 1305, 0, 1025}, /* ; 01 (320x350,640x350) */
+ {9, 1305, 0, 1025}, /* ; 02 (360x400,720x400) */
+ {9, 1305, 0, 1025}, /* ; 03 (720x350) */
+ {9, 1305, 0, 1025}, /* ; 04 (640x480x60Hz) */
+ {9, 1305, 0, 1025}, /* ; 05 (800x600x60Hz) */
+ {9, 1305, 0, 1025}, /* ; 06 (1024x768x60Hz) */
+ {9, 1305, 0, 1025} /* ; 07 (1280x1024x60Hz) */
};
-static struct XGI330_LCDDataDesStruct XGI_StLCDDes1280x1024x75Data[] =
-{
- {9,1305,0,1025},/* ; 00 (320x200,320x400,640x200,640x400) */
- {9,1305,0,1025},/* ; 01 (320x350,640x350) */
- {9,1305,0,1025},/* ; 02 (360x400,720x400) */
- {9,1305,0,1025},/* ; 03 (720x350) */
- {9,1305,0,1025},/* ; 04 (640x480x60Hz) */
- {9,1305,0,1025},/* ; 05 (800x600x60Hz) */
- {9,1305,0,1025},/* ; 06 (1024x768x60Hz) */
- {9,1305,0,1025} /* ; 07 (1280x1024x60Hz) */
+static struct XGI330_LCDDataDesStruct XGI_StLCDDes1280x1024x75Data[] = {
+ {9, 1305, 0, 1025}, /* ; 00 (320x200,320x400,640x200,640x400) */
+ {9, 1305, 0, 1025}, /* ; 01 (320x350,640x350) */
+ {9, 1305, 0, 1025}, /* ; 02 (360x400,720x400) */
+ {9, 1305, 0, 1025}, /* ; 03 (720x350) */
+ {9, 1305, 0, 1025}, /* ; 04 (640x480x60Hz) */
+ {9, 1305, 0, 1025}, /* ; 05 (800x600x60Hz) */
+ {9, 1305, 0, 1025}, /* ; 06 (1024x768x60Hz) */
+ {9, 1305, 0, 1025} /* ; 07 (1280x1024x60Hz) */
};
-static struct XGI330_LCDDataDesStruct XGI_CetLCDDes1280x1024x75Data[] = /* 1280x1024x75Hz */
-{
- {1368,1008,752,711}, /* ; 00 (320x200,320x400,640x200,640x400) */
- {1368,1008,729,688}, /* ; 01 (320x350,640x350) */
- {1408,1048,752,711}, /* ; 02 (360x400,720x400) */
- {1408,1048,729,688}, /* ; 03 (720x350) */
- {1377,985,794,753}, /* ; 04 (640x480x75Hz) */
- {1457,1065,854,813}, /* ; 05 (800x600x75Hz) */
- {1569,1177,938,897}, /* ; 06 (1024x768x75Hz) */
- {9,1305,0,1025} /* ; 07 (1280x1024x75Hz) */
+/* 1280x1024x75Hz */
+static struct XGI330_LCDDataDesStruct XGI_CetLCDDes1280x1024x75Data[] = {
+ {1368, 1008, 752, 711}, /* ; 00 (320x200,320x400,640x200,640x400) */
+ {1368, 1008, 729, 688}, /* ; 01 (320x350,640x350) */
+ {1408, 1048, 752, 711}, /* ; 02 (360x400,720x400) */
+ {1408, 1048, 729, 688}, /* ; 03 (720x350) */
+ {1377, 985, 794, 753}, /* ; 04 (640x480x75Hz) */
+ {1457, 1065, 854, 813}, /* ; 05 (800x600x75Hz) */
+ {1569, 1177, 938, 897}, /* ; 06 (1024x768x75Hz) */
+ {9, 1305, 0, 1025} /* ; 07 (1280x1024x75Hz) */
};
-static struct XGI330_LCDDataDesStruct2 XGI_NoScalingDesDatax75[] = /* Scaling LCD 75Hz */
-{
- {9,657,448,405,96,2}, /* ; 00 (320x200,320x400,640x200,640x400) */
- {9,657,448,355,96,2}, /* ; 01 (320x350,640x350) */
- {9,738,448,405,108,2}, /* ; 02 (360x400,720x400) */
- {9,738,448,355,108,2}, /* ; 03 (720x350) */
- {9,665,0,481,64,3}, /* ; 04 (640x480x75Hz) */
- {9,825,0,601,80,3}, /* ; 05 (800x600x75Hz) */
- {9,1049,0,769,96,3}, /* ; 06 (1024x768x75Hz) */
- {9,1305,0,1025,144,3}, /* ; 07 (1280x1024x75Hz) */
- {9,1457,0,1051,112,3}, /* ; 08 (1400x1050x60Hz) ;;[ycchen] 12/19/02 */
- {9,1673,0,1201,192,3}, /* ; 09 (1600x1200x75Hz) */
- {9,1337,0,771,112,6} /* ; 0A (1280x768x60Hz) */
+/* Scaling LCD 75Hz */
+static struct XGI330_LCDDataDesStruct2 XGI_NoScalingDesDatax75[] = {
+ {9, 657, 448, 405, 96, 2}, /* ; 00 (320x200,320x400,
+ 640x200,640x400) */
+ {9, 657, 448, 355, 96, 2}, /* ; 01 (320x350,640x350) */
+ {9, 738, 448, 405, 108, 2}, /* ; 02 (360x400,720x400) */
+ {9, 738, 448, 355, 108, 2}, /* ; 03 (720x350) */
+ {9, 665, 0, 481, 64, 3}, /* ; 04 (640x480x75Hz) */
+ {9, 825, 0, 601, 80, 3}, /* ; 05 (800x600x75Hz) */
+ {9, 1049, 0, 769, 96, 3}, /* ; 06 (1024x768x75Hz) */
+ {9, 1305, 0, 1025, 144, 3}, /* ; 07 (1280x1024x75Hz) */
+ {9, 1457, 0, 1051, 112, 3}, /* ; 08 (1400x1050x60Hz)
+ ;;[ycchen] 12/19/02 */
+ {9, 1673, 0, 1201, 192, 3}, /* ; 09 (1600x1200x75Hz) */
+ {9, 1337, 0, 771, 112, 6} /* ; 0A (1280x768x60Hz) */
};
-static struct XGI330_TVDataStruct XGI_StPALData[] =
-{
- { 1, 1, 864, 525,1270, 400, 100, 0, 760},
- { 1, 1, 864, 525,1270, 350, 100, 0, 760},
- { 1, 1, 864, 525,1270, 400, 0, 0, 720},
- { 1, 1, 864, 525,1270, 350, 0, 0, 720},
- { 1, 1, 864, 525,1270, 480, 50, 0, 760},
- { 1, 1, 864, 525,1270, 600, 50, 0, 0}
+static struct XGI330_TVDataStruct XGI_StPALData[] = {
+ {1, 1, 864, 525, 1270, 400, 100, 0, 760},
+ {1, 1, 864, 525, 1270, 350, 100, 0, 760},
+ {1, 1, 864, 525, 1270, 400, 0, 0, 720},
+ {1, 1, 864, 525, 1270, 350, 0, 0, 720},
+ {1, 1, 864, 525, 1270, 480, 50, 0, 760},
+ {1, 1, 864, 525, 1270, 600, 50, 0, 0}
};
-static struct XGI330_TVDataStruct XGI_ExtPALData[] =
-{
- { 2, 1,1080, 463,1270, 500, 50, 0, 50},
- { 15, 7,1152, 413,1270, 500, 50, 0, 50},
- { 2, 1,1080, 463,1270, 500, 50, 0, 50},
- { 15, 7,1152, 413,1270, 500, 50, 0, 50},
- { 2, 1, 900, 543,1270, 500, 0, 0, 50},
- { 4, 3,1080, 663,1270, 500, 438, 0, 438},
- { 1, 1,1125, 831,1270, 500, 686, 0, 686}, /*301b*/
- { 3, 2,1080, 619,1270, 540, 438, 0, 438}
+static struct XGI330_TVDataStruct XGI_ExtPALData[] = {
+ {2, 1, 1080, 463, 1270, 500, 50, 0, 50},
+ {15, 7, 1152, 413, 1270, 500, 50, 0, 50},
+ {2, 1, 1080, 463, 1270, 500, 50, 0, 50},
+ {15, 7, 1152, 413, 1270, 500, 50, 0, 50},
+ {2, 1, 900, 543, 1270, 500, 0, 0, 50},
+ {4, 3, 1080, 663, 1270, 500, 438, 0, 438},
+ {1, 1, 1125, 831, 1270, 500, 686, 0, 686}, /*301b*/
+ {3, 2, 1080, 619, 1270, 540, 438, 0, 438}
};
-static struct XGI330_TVDataStruct XGI_StNTSCData[] =
-{
- { 1, 1, 858, 525,1270, 400, 50, 0, 760},
- { 1, 1, 858, 525,1270, 350, 50, 0, 640},
- { 1, 1, 858, 525,1270, 400, 0, 0, 720},
- { 1, 1, 858, 525,1270, 350, 0, 0, 720},
- { 1, 1, 858, 525,1270, 480, 0, 0, 760}
+static struct XGI330_TVDataStruct XGI_StNTSCData[] = {
+ {1, 1, 858, 525, 1270, 400, 50, 0, 760},
+ {1, 1, 858, 525, 1270, 350, 50, 0, 640},
+ {1, 1, 858, 525, 1270, 400, 0, 0, 720},
+ {1, 1, 858, 525, 1270, 350, 0, 0, 720},
+ {1, 1, 858, 525, 1270, 480, 0, 0, 760}
};
-static struct XGI330_TVDataStruct XGI_ExtNTSCData[] =
-{
- { 9, 5, 1001, 453,1270, 420, 171, 0, 171},
- { 12, 5, 858, 403,1270, 420, 171, 0, 171},
- { 9, 5, 1001, 453,1270, 420, 171, 0, 171},
- { 12, 5, 858, 403,1270, 420, 171, 0, 171},
- { 143, 80, 836, 523,1270, 420, 224, 0, 0},
- { 143, 120,1008, 643,1270, 420, 0, 1, 0},
- { 1, 1,1120, 821,1516, 420, 0, 1, 0}, /*301b*/
- { 2, 1, 858, 503,1584, 480, 0, 1, 0},
- { 3, 2,1001, 533,1270, 420, 0, 0, 0}
+static struct XGI330_TVDataStruct XGI_ExtNTSCData[] = {
+ {9, 5, 1001, 453, 1270, 420, 171, 0, 171},
+ {12, 5, 858, 403, 1270, 420, 171, 0, 171},
+ {9, 5, 1001, 453, 1270, 420, 171, 0, 171},
+ {12, 5, 858, 403, 1270, 420, 171, 0, 171},
+ {143, 80, 836, 523, 1270, 420, 224, 0, 0},
+ {143, 120, 1008, 643, 1270, 420, 0, 1, 0},
+ {1, 1, 1120, 821, 1516, 420, 0, 1, 0}, /*301b*/
+ {2, 1, 858, 503, 1584, 480, 0, 1, 0},
+ {3, 2, 1001, 533, 1270, 420, 0, 0, 0}
};
-static struct XGI330_TVDataStruct XGI_St1HiTVData[] =
-{
- { 1,1,892,563,690,800,0,0,0 }, /* 00 (320x200,320x400,640x200,640x400) */
- { 1,1,892,563,690,700,0,0,0 }, /* 01 (320x350,640x350) */
- { 1,1,1000,563,785,800,0,0,0 }, /* 02 (360x400,720x400) */
- { 1,1,1000,563,785,700,0,0,0 }, /* 03 (720x350) */
- { 1,1,892,563,690,960,0,0,0 }, /* 04 (320x240,640x480) */
- { 8,5,1050,683,1648,960,0x150,1,0 } /* 05 (400x300,800x600) */
+static struct XGI330_TVDataStruct XGI_St1HiTVData[] = {
+ {1, 1, 892, 563, 690, 800, 0, 0, 0}, /* 00 (320x200,320x400,
+ 640x200,640x400) */
+ {1, 1, 892, 563, 690, 700, 0, 0, 0}, /* 01 (320x350,640x350) */
+ {1, 1, 1000, 563, 785, 800, 0, 0, 0}, /* 02 (360x400,720x400) */
+ {1, 1, 1000, 563, 785, 700, 0, 0, 0}, /* 03 (720x350) */
+ {1, 1, 892, 563, 690, 960, 0, 0, 0}, /* 04 (320x240,640x480) */
+ {8, 5, 1050, 683, 1648, 960, 0x150, 1, 0} /* 05 (400x300,800x600) */
};
-static struct XGI330_TVDataStruct XGI_St2HiTVData[] =
-{
- { 3,1,840,483,1648,960,0x032,0,0 }, /* 00 (320x200,320x400,640x200,640x400) */
- { 1,1,892,563,690,700,0,0,0 }, /* 01 (320x350,640x350) */
- { 3,1,840,483,1648,960,0x032,0,0 }, /* 02 (360x400,720x400) */
- { 1,1,1000,563,785,700,0,0,0 }, /* 03 (720x350) */
- { 5,2,840,563,1648,960,0x08D,1,0 }, /* 04 (320x240,640x480) */
- { 8,5,1050,683,1648,960,0x17C,1,0 } /* 05 (400x300,800x600) */
-
+static struct XGI330_TVDataStruct XGI_St2HiTVData[] = {
+ {3, 1, 840, 483, 1648, 960, 0x032, 0, 0}, /* 00 (320x200,320x400,
+ 640x200,640x400) */
+ {1, 1, 892, 563, 690, 700, 0, 0, 0}, /* 01 (320x350,640x350) */
+ {3, 1, 840, 483, 1648, 960, 0x032, 0, 0}, /* 02 (360x400,720x400) */
+ {1, 1, 1000, 563, 785, 700, 0, 0, 0}, /* 03 (720x350) */
+ {5, 2, 840, 563, 1648, 960, 0x08D, 1, 0}, /* 04 (320x240,640x480) */
+ {8, 5, 1050, 683, 1648, 960, 0x17C, 1, 0} /* 05 (400x300,800x600) */
};
-static struct XGI330_TVDataStruct XGI_ExtHiTVData[] =
-{
- { 6,1,840,563,1632,960,0,0,0 }, /* 00 (320x200,320x400,640x200,640x400) */
- { 3,1,960,563,1632,960,0,0,0 }, /* 01 (320x350,640x350) */
- { 3,1,840,483,1632,960,0,0,0 }, /* 02 (360x400,720x400) */
- { 3,1,960,563,1632,960,0,0,0 }, /* 03 (720x350) */
- { 5,1,840,563,1648,960,0x166,1,0 }, /* 04 (320x240,640x480) */
- { 16,5,1050,683,1648,960,0x143,1,0 }, /* 05 (400x300,800x600) */
- { 25,12,1260,851,1648,960,0x032,0,0 }, /* 06 (512x384,1024x768) */
- { 5,4,1575,1124,1648,960,0x128,0,0 }, /* 07 (1280x1024) */
- { 4,1,1050,563,1548,960,0x143,1,0 }, /* 08 (800x480) */
- { 5,2,1400,659,1648,960,0x032,0,0 }, /* 09 (1024x576) */
- { 8,5,1750,803,1648,960,0x128,0,0 } /* 0A (1280x720) */
-
+static struct XGI330_TVDataStruct XGI_ExtHiTVData[] = {
+ {6, 1, 840, 563, 1632, 960, 0, 0, 0}, /* 00 (320x200,320x400,
+ 640x200,640x400) */
+ {3, 1, 960, 563, 1632, 960, 0, 0, 0}, /* 01 (320x350,640x350) */
+ {3, 1, 840, 483, 1632, 960, 0, 0, 0}, /* 02 (360x400,720x400) */
+ {3, 1, 960, 563, 1632, 960, 0, 0, 0}, /* 03 (720x350) */
+ {5, 1, 840, 563, 1648, 960, 0x166, 1, 0}, /* 04 (320x240,640x480) */
+ {16, 5, 1050, 683, 1648, 960, 0x143, 1, 0}, /* 05 (400x300,800x600) */
+ {25, 12, 1260, 851, 1648, 960, 0x032, 0, 0}, /* 06 (512x384,1024x768)*/
+ {5, 4, 1575, 1124, 1648, 960, 0x128, 0, 0}, /* 07 (1280x1024) */
+ {4, 1, 1050, 563, 1548, 960, 0x143, 1, 0}, /* 08 (800x480) */
+ {5, 2, 1400, 659, 1648, 960, 0x032, 0, 0}, /* 09 (1024x576) */
+ {8, 5, 1750, 803, 1648, 960, 0x128, 0, 0} /* 0A (1280x720) */
};
-static struct XGI330_TVDataStruct XGI_ExtYPbPr525iData[] =
-{
- { 9, 5, 1001, 453,1270, 420, 171, 0, 171},
- { 12, 5, 858, 403,1270, 420, 171, 0, 171},
- { 9, 5, 1001, 453,1270, 420, 171, 0, 171},
- { 12, 5, 858, 403,1270, 420, 171, 0, 171},
- { 143, 80, 836, 523,1250, 420, 224, 0, 0},
- { 143, 120,1008, 643,1250, 420, 0, 1, 0},
- { 1, 1,1120, 821,1516, 420, 0, 1, 0}, /*301b*/
- { 2, 1, 858, 503,1584, 480, 0, 1, 0},
- { 3, 2,1001, 533,1250, 420, 0, 0, 0}
+static struct XGI330_TVDataStruct XGI_ExtYPbPr525iData[] = {
+ { 9, 5, 1001, 453, 1270, 420, 171, 0, 171},
+ { 12, 5, 858, 403, 1270, 420, 171, 0, 171},
+ { 9, 5, 1001, 453, 1270, 420, 171, 0, 171},
+ { 12, 5, 858, 403, 1270, 420, 171, 0, 171},
+ {143, 80, 836, 523, 1250, 420, 224, 0, 0},
+ {143, 120, 1008, 643, 1250, 420, 0, 1, 0},
+ { 1, 1, 1120, 821, 1516, 420, 0, 1, 0}, /*301b*/
+ { 2, 1, 858, 503, 1584, 480, 0, 1, 0},
+ { 3, 2, 1001, 533, 1250, 420, 0, 0, 0}
};
-static struct XGI330_TVDataStruct XGI_StYPbPr525iData[] =
-{
- { 1, 1, 858, 525,1270, 400, 50, 0, 760},
- { 1, 1, 858, 525,1270, 350, 50, 0, 640},
- { 1, 1, 858, 525,1270, 400, 0, 0, 720},
- { 1, 1, 858, 525,1270, 350, 0, 0, 720},
- { 1, 1, 858, 525,1270, 480, 0, 0, 760},
+static struct XGI330_TVDataStruct XGI_StYPbPr525iData[] = {
+ {1, 1, 858, 525, 1270, 400, 50, 0, 760},
+ {1, 1, 858, 525, 1270, 350, 50, 0, 640},
+ {1, 1, 858, 525, 1270, 400, 0, 0, 720},
+ {1, 1, 858, 525, 1270, 350, 0, 0, 720},
+ {1, 1, 858, 525, 1270, 480, 0, 0, 760},
};
-static struct XGI330_TVDataStruct XGI_ExtYPbPr525pData[] =
-{
- { 9, 5, 1001, 453,1270, 420, 171, 0, 171},
- { 12, 5, 858, 403,1270, 420, 171, 0, 171},
- { 9, 5, 1001, 453,1270, 420, 171, 0, 171},
- { 12, 5, 858, 403,1270, 420, 171, 0, 171},
- { 143, 80, 836, 523,1270, 420, 224, 0, 0},
- { 143, 120,1008, 643,1270, 420, 0, 1, 0},
- { 1, 1,1120, 821,1516, 420, 0, 1, 0}, /*301b*/
- { 2, 1, 858, 503,1584, 480, 0, 1, 0},
- { 3, 2,1001, 533,1270, 420, 0, 0, 0}
- };
-
-static struct XGI330_TVDataStruct XGI_StYPbPr525pData[] =
-{
- { 1, 1,1716, 525,1270, 400, 50, 0, 760},
- { 1, 1,1716, 525,1270, 350, 50, 0, 640},
- { 1, 1,1716, 525,1270, 400, 0, 0, 720},
- { 1, 1,1716, 525,1270, 350, 0, 0, 720},
- { 1, 1,1716, 525,1270, 480, 0, 0, 760},
+static struct XGI330_TVDataStruct XGI_ExtYPbPr525pData[] = {
+ { 9, 5, 1001, 453, 1270, 420, 171, 0, 171},
+ { 12, 5, 858, 403, 1270, 420, 171, 0, 171},
+ { 9, 5, 1001, 453, 1270, 420, 171, 0, 171},
+ { 12, 5, 858, 403, 1270, 420, 171, 0, 171},
+ {143, 80, 836, 523, 1270, 420, 224, 0, 0},
+ {143, 120, 1008, 643, 1270, 420, 0, 1, 0},
+ { 1, 1, 1120, 821, 1516, 420, 0, 1, 0}, /*301b*/
+ { 2, 1, 858, 503, 1584, 480, 0, 1, 0},
+ { 3, 2, 1001, 533, 1270, 420, 0, 0, 0}
};
-static struct XGI330_TVDataStruct XGI_ExtYPbPr750pData[] =
-{
- { 3, 1, 935, 470,1130, 680, 50, 0, 0}, /* 00 (320x200,320x400,640x200,640x400) */
- { 24, 7, 935, 420,1130, 680, 50, 0, 0}, /* 01 (320x350,640x350) */
- { 3, 1, 935, 470,1130, 680, 50, 0, 0}, /* 02 (360x400,720x400) */
- { 24, 7, 935, 420,1130, 680, 50, 0, 0}, /* 03 (720x350) */
- { 2, 1,1100, 590,1130, 640, 50, 0, 0}, /* 04 (320x240,640x480) */
- { 3, 2,1210, 690,1130, 660, 50, 0, 0}, /* 05 (400x300,800x600) */
- { 1, 1,1375, 878,1130, 640, 638, 0, 0}, /* 06 (1024x768) */
- { 2, 1, 858, 503,1130, 480, 0, 1, 0}, /* 07 (720x480) */
- { 5, 4,1815, 570,1130, 660, 50, 0, 0},
- { 5, 3,1100, 686,1130, 640, 50, 1, 0},
- { 10, 9,1320, 830,1130, 640, 50, 0, 0}
+static struct XGI330_TVDataStruct XGI_StYPbPr525pData[] = {
+ {1, 1, 1716, 525, 1270, 400, 50, 0, 760},
+ {1, 1, 1716, 525, 1270, 350, 50, 0, 640},
+ {1, 1, 1716, 525, 1270, 400, 0, 0, 720},
+ {1, 1, 1716, 525, 1270, 350, 0, 0, 720},
+ {1, 1, 1716, 525, 1270, 480, 0, 0, 760},
};
-static struct XGI330_TVDataStruct XGI_StYPbPr750pData[] =
-{
- { 1, 1,1650, 750,1280, 400, 50, 0, 760},
- { 1, 1,1650, 750,1280, 350, 50, 0, 640},
- { 1, 1,1650, 750,1280, 400, 0, 0, 720},
- { 1, 1,1650, 750,1280, 350, 0, 0, 720},
- { 1, 1,1650, 750,1280, 480, 0, 0, 760},
+static struct XGI330_TVDataStruct XGI_ExtYPbPr750pData[] = {
+ { 3, 1, 935, 470, 1130, 680, 50, 0, 0}, /* 00 (320x200,320x400,
+ 640x200,640x400) */
+ {24, 7, 935, 420, 1130, 680, 50, 0, 0}, /* 01 (320x350,640x350) */
+ { 3, 1, 935, 470, 1130, 680, 50, 0, 0}, /* 02 (360x400,720x400) */
+ {24, 7, 935, 420, 1130, 680, 50, 0, 0}, /* 03 (720x350) */
+ { 2, 1, 1100, 590, 1130, 640, 50, 0, 0}, /* 04 (320x240,640x480) */
+ { 3, 2, 1210, 690, 1130, 660, 50, 0, 0}, /* 05 (400x300,800x600) */
+ { 1, 1, 1375, 878, 1130, 640, 638, 0, 0}, /* 06 (1024x768) */
+ { 2, 1, 858, 503, 1130, 480, 0, 1, 0}, /* 07 (720x480) */
+ { 5, 4, 1815, 570, 1130, 660, 50, 0, 0},
+ { 5, 3, 1100, 686, 1130, 640, 50, 1, 0},
+ {10, 9, 1320, 830, 1130, 640, 50, 0, 0}
+};
+
+static struct XGI330_TVDataStruct XGI_StYPbPr750pData[] = {
+ {1, 1, 1650, 750, 1280, 400, 50, 0, 760},
+ {1, 1, 1650, 750, 1280, 350, 50, 0, 640},
+ {1, 1, 1650, 750, 1280, 400, 0, 0, 720},
+ {1, 1, 1650, 750, 1280, 350, 0, 0, 720},
+ {1, 1, 1650, 750, 1280, 480, 0, 0, 760},
};
static unsigned char XGI330_NTSCTiming[] = {
- 0x17,0x1d,0x03,0x09,0x05,0x06,0x0c,0x0c,
- 0x94,0x49,0x01,0x0a,0x06,0x0d,0x04,0x0a,
- 0x06,0x14,0x0d,0x04,0x0a,0x00,0x85,0x1b,
- 0x0c,0x50,0x00,0x97,0x00,0xda,0x4a,0x17,
- 0x7d,0x05,0x4b,0x00,0x00,0xe2,0x00,0x02,
- 0x03,0x0a,0x65,0x9d,0x08,0x92,0x8f,0x40,
- 0x60,0x80,0x14,0x90,0x8c,0x60,0x14,0x50,
- 0x00,0x40,0x44,0x00,0xdb,0x02,0x3b,0x00};
+ 0x17, 0x1d, 0x03, 0x09, 0x05, 0x06, 0x0c, 0x0c,
+ 0x94, 0x49, 0x01, 0x0a, 0x06, 0x0d, 0x04, 0x0a,
+ 0x06, 0x14, 0x0d, 0x04, 0x0a, 0x00, 0x85, 0x1b,
+ 0x0c, 0x50, 0x00, 0x97, 0x00, 0xda, 0x4a, 0x17,
+ 0x7d, 0x05, 0x4b, 0x00, 0x00, 0xe2, 0x00, 0x02,
+ 0x03, 0x0a, 0x65, 0x9d, 0x08, 0x92, 0x8f, 0x40,
+ 0x60, 0x80, 0x14, 0x90, 0x8c, 0x60, 0x14, 0x50,
+ 0x00, 0x40, 0x44, 0x00, 0xdb, 0x02, 0x3b, 0x00
+};
static unsigned char XGI330_PALTiming[] = {
- 0x21,0x5A,0x35,0x6e,0x04,0x38,0x3d,0x70,
- 0x94,0x49,0x01,0x12,0x06,0x3e,0x35,0x6d,
- 0x06,0x14,0x3e,0x35,0x6d,0x00,0x45,0x2b,
- 0x70,0x50,0x00,0x9b,0x00,0xd9,0x5d,0x17,
- 0x7d,0x05,0x45,0x00,0x00,0xe8,0x00,0x02,
- 0x0d,0x00,0x68,0xb0,0x0b,0x92,0x8f,0x40,
- 0x60,0x80,0x14,0x90,0x8c,0x60,0x14,0x63,
- 0x00,0x40,0x3e,0x00,0xe1,0x02,0x28,0x00};
-
-static unsigned char XGI330_HiTVExtTiming[] =
-{
- 0x2D,0x60,0x2C,0x5F,0x08,0x31,0x3A,0x64,
- 0x28,0x02,0x01,0x3D,0x06,0x3E,0x35,0x6D,
- 0x06,0x14,0x3E,0x35,0x6D,0x00,0xC5,0x3F,
- 0x64,0x90,0x33,0x8C,0x18,0x36,0x3E,0x13,
- 0x2A,0xDE,0x2A,0x44,0x40,0x2A,0x44,0x40,
- 0x8E,0x8E,0x82,0x07,0x0B,
- 0x92,0x0F,0x40,0x60,0x80,0x14,0x90,0x8C,
- 0x60,0x14,0x3D,0x63,0x4F,
- 0x27,0x00,0xfc,0xff,0x6a,0x00
-
+ 0x21, 0x5A, 0x35, 0x6e, 0x04, 0x38, 0x3d, 0x70,
+ 0x94, 0x49, 0x01, 0x12, 0x06, 0x3e, 0x35, 0x6d,
+ 0x06, 0x14, 0x3e, 0x35, 0x6d, 0x00, 0x45, 0x2b,
+ 0x70, 0x50, 0x00, 0x9b, 0x00, 0xd9, 0x5d, 0x17,
+ 0x7d, 0x05, 0x45, 0x00, 0x00, 0xe8, 0x00, 0x02,
+ 0x0d, 0x00, 0x68, 0xb0, 0x0b, 0x92, 0x8f, 0x40,
+ 0x60, 0x80, 0x14, 0x90, 0x8c, 0x60, 0x14, 0x63,
+ 0x00, 0x40, 0x3e, 0x00, 0xe1, 0x02, 0x28, 0x00
};
-static unsigned char XGI330_HiTVSt1Timing[] =
-{
- 0x32,0x65,0x2C,0x5F,0x08,0x31,0x3A,0x65,
- 0x28,0x02,0x01,0x3D,0x06,0x3E,0x35,0x6D,
- 0x06,0x14,0x3E,0x35,0x6D,0x00,0xC5,0x3F,
- 0x65,0x90,0x7B,0xA8,0x03,0xF0,0x87,0x03,
- 0x11,0x15,0x11,0xCF,0x10,0x11,0xCF,0x10,
- 0x35,0x35,0x3B,0x69,0x1D,
- 0x92,0x0F,0x40,0x60,0x80,0x14,0x90,0x8C,
- 0x60,0x04,0x86,0xAF,0x5D,
- 0x0E,0x00,0xfc,0xff,0x2d,0x00
+static unsigned char XGI330_HiTVExtTiming[] = {
+ 0x2D, 0x60, 0x2C, 0x5F, 0x08, 0x31, 0x3A, 0x64,
+ 0x28, 0x02, 0x01, 0x3D, 0x06, 0x3E, 0x35, 0x6D,
+ 0x06, 0x14, 0x3E, 0x35, 0x6D, 0x00, 0xC5, 0x3F,
+ 0x64, 0x90, 0x33, 0x8C, 0x18, 0x36, 0x3E, 0x13,
+ 0x2A, 0xDE, 0x2A, 0x44, 0x40, 0x2A, 0x44, 0x40,
+ 0x8E, 0x8E, 0x82, 0x07, 0x0B,
+ 0x92, 0x0F, 0x40, 0x60, 0x80, 0x14, 0x90, 0x8C,
+ 0x60, 0x14, 0x3D, 0x63, 0x4F,
+ 0x27, 0x00, 0xfc, 0xff, 0x6a, 0x00
};
-static unsigned char XGI330_HiTVSt2Timing[] =
-{
- 0x32,0x65,0x2C,0x5F,0x08,0x31,0x3A,0x64,
- 0x28,0x02,0x01,0x3D,0x06,0x3E,0x35,0x6D,
- 0x06,0x14,0x3E,0x35,0x6D,0x00,0xC5,0x3F,
- 0x64,0x90,0x33,0x8C,0x18,0x36,0x3E,0x13,
- 0x2A,0xDE,0x2A,0x44,0x40,0x2A,0x44,0x40,
- 0x8E,0x8E,0x82,0x07,0x0B,
- 0x92,0x0F,0x40,0x60,0x80,0x14,0x90,0x8C,
- 0x60,0x14,0x3D,0x63,0x4F,
- 0x27,0x00,0xFC,0xff,0x6a,0x00
+static unsigned char XGI330_HiTVSt1Timing[] = {
+ 0x32, 0x65, 0x2C, 0x5F, 0x08, 0x31, 0x3A, 0x65,
+ 0x28, 0x02, 0x01, 0x3D, 0x06, 0x3E, 0x35, 0x6D,
+ 0x06, 0x14, 0x3E, 0x35, 0x6D, 0x00, 0xC5, 0x3F,
+ 0x65, 0x90, 0x7B, 0xA8, 0x03, 0xF0, 0x87, 0x03,
+ 0x11, 0x15, 0x11, 0xCF, 0x10, 0x11, 0xCF, 0x10,
+ 0x35, 0x35, 0x3B, 0x69, 0x1D,
+ 0x92, 0x0F, 0x40, 0x60, 0x80, 0x14, 0x90, 0x8C,
+ 0x60, 0x04, 0x86, 0xAF, 0x5D,
+ 0x0E, 0x00, 0xfc, 0xff, 0x2d, 0x00
};
-static unsigned char XGI330_HiTVTextTiming[] =
-{
- 0x32,0x65,0x2C,0x5F,0x08,0x31,0x3A,0x65,
- 0x28,0x02,0x01,0x3D,0x06,0x3E,0x35,0x6D,
- 0x06,0x14,0x3E,0x35,0x6D,0x00,0xC5,0x3F,
- 0x65,0x90,0xE7,0xBC,0x03,0x0C,0x97,0x03,
- 0x14,0x78,0x14,0x08,0x20,0x14,0x08,0x20,
- 0xC8,0xC8,0x3B,0xD2,0x26,
- 0x92,0x0F,0x40,0x60,0x80,0x14,0x90,0x8C,
- 0x60,0x04,0x96,0x72,0x5C,
- 0x11,0x00,0xFC,0xFF,0x32,0x00
+static unsigned char XGI330_HiTVSt2Timing[] = {
+ 0x32, 0x65, 0x2C, 0x5F, 0x08, 0x31, 0x3A, 0x64,
+ 0x28, 0x02, 0x01, 0x3D, 0x06, 0x3E, 0x35, 0x6D,
+ 0x06, 0x14, 0x3E, 0x35, 0x6D, 0x00, 0xC5, 0x3F,
+ 0x64, 0x90, 0x33, 0x8C, 0x18, 0x36, 0x3E, 0x13,
+ 0x2A, 0xDE, 0x2A, 0x44, 0x40, 0x2A, 0x44, 0x40,
+ 0x8E, 0x8E, 0x82, 0x07, 0x0B,
+ 0x92, 0x0F, 0x40, 0x60, 0x80, 0x14, 0x90, 0x8C,
+ 0x60, 0x14, 0x3D, 0x63, 0x4F,
+ 0x27, 0x00, 0xFC, 0xff, 0x6a, 0x00
};
-static unsigned char XGI330_YPbPr750pTiming[] =
-{
- 0x30,0x1d,0xe8,0x09,0x09,0xed,0x0c,0x0c,
- 0x98,0x0a,0x01,0x0c,0x06,0x0d,0x04,0x0a,
- 0x06,0x14,0x0d,0x04,0x0a,0x00,0x85,0x3f,
- 0xed,0x50,0x70,0x9f,0x16,0x59,0x60,0x13,
- 0x27,0x0b,0x27,0xfc,0x30,0x27,0x1c,0xb0,
- 0x4b,0x4b,0x6f,0x2f,0x63,
- 0x92,0x0F,0x40,0x60,0x80,0x14,0x90,0x8C,
- 0x60,0x14,0x73,0x00,0x40,
- 0x11,0x00,0xfc,0xff,0x32,0x00
+static unsigned char XGI330_HiTVTextTiming[] = {
+ 0x32, 0x65, 0x2C, 0x5F, 0x08, 0x31, 0x3A, 0x65,
+ 0x28, 0x02, 0x01, 0x3D, 0x06, 0x3E, 0x35, 0x6D,
+ 0x06, 0x14, 0x3E, 0x35, 0x6D, 0x00, 0xC5, 0x3F,
+ 0x65, 0x90, 0xE7, 0xBC, 0x03, 0x0C, 0x97, 0x03,
+ 0x14, 0x78, 0x14, 0x08, 0x20, 0x14, 0x08, 0x20,
+ 0xC8, 0xC8, 0x3B, 0xD2, 0x26,
+ 0x92, 0x0F, 0x40, 0x60, 0x80, 0x14, 0x90, 0x8C,
+ 0x60, 0x04, 0x96, 0x72, 0x5C,
+ 0x11, 0x00, 0xFC, 0xFF, 0x32, 0x00
};
-static unsigned char XGI330_YPbPr525pTiming[] =
-{
- 0x3E,0x11,0x06,0x09,0x0b,0x0c,0x0c,0x0c,
- 0x98,0x0a,0x01,0x0d,0x06,0x0d,0x04,0x0a,
- 0x06,0x14,0x0d,0x04,0x0a,0x00,0x85,0x3f,
- 0x0c,0x50,0xb2,0x9f,0x16,0x59,0x4f,0x13,
- 0xad,0x11,0xad,0x1d,0x40,0x8a,0x3d,0xb8,
- 0x51,0x5e,0x60,0x49,0x7d,
- 0x92,0x0F,0x40,0x60,0x80,0x14,0x90,0x8C,
- 0x60,0x14,0x4B,0x43,0x41,
- 0x11,0x00,0xFC,0xFF,0x32,0x00
+static unsigned char XGI330_YPbPr750pTiming[] = {
+ 0x30, 0x1d, 0xe8, 0x09, 0x09, 0xed, 0x0c, 0x0c,
+ 0x98, 0x0a, 0x01, 0x0c, 0x06, 0x0d, 0x04, 0x0a,
+ 0x06, 0x14, 0x0d, 0x04, 0x0a, 0x00, 0x85, 0x3f,
+ 0xed, 0x50, 0x70, 0x9f, 0x16, 0x59, 0x60, 0x13,
+ 0x27, 0x0b, 0x27, 0xfc, 0x30, 0x27, 0x1c, 0xb0,
+ 0x4b, 0x4b, 0x6f, 0x2f, 0x63,
+ 0x92, 0x0F, 0x40, 0x60, 0x80, 0x14, 0x90, 0x8C,
+ 0x60, 0x14, 0x73, 0x00, 0x40,
+ 0x11, 0x00, 0xfc, 0xff, 0x32, 0x00
};
-static unsigned char XGI330_YPbPr525iTiming[] =
-{
- 0x1B,0x21,0x03,0x09,0x05,0x06,0x0C,0x0C,
- 0x94,0x49,0x01,0x0A,0x06,0x0D,0x04,0x0A,
- 0x06,0x14,0x0D,0x04,0x0A,0x00,0x85,0x1B,
- 0x0C,0x50,0x00,0x97,0x00,0xDA,0x4A,0x17,
- 0x7D,0x05,0x4B,0x00,0x00,0xE2,0x00,0x02,
- 0x03,0x0A,0x65,0x9D,0x08,
- 0x92,0x8F,0x40,0x60,0x80,0x14,0x90,0x8C,
- 0x60,0x14,0x4B,0x00,0x40,
- 0x44,0x00,0xDB,0x02,0x3B,0x00
-
+static unsigned char XGI330_YPbPr525pTiming[] = {
+ 0x3E, 0x11, 0x06, 0x09, 0x0b, 0x0c, 0x0c, 0x0c,
+ 0x98, 0x0a, 0x01, 0x0d, 0x06, 0x0d, 0x04, 0x0a,
+ 0x06, 0x14, 0x0d, 0x04, 0x0a, 0x00, 0x85, 0x3f,
+ 0x0c, 0x50, 0xb2, 0x9f, 0x16, 0x59, 0x4f, 0x13,
+ 0xad, 0x11, 0xad, 0x1d, 0x40, 0x8a, 0x3d, 0xb8,
+ 0x51, 0x5e, 0x60, 0x49, 0x7d,
+ 0x92, 0x0F, 0x40, 0x60, 0x80, 0x14, 0x90, 0x8C,
+ 0x60, 0x14, 0x4B, 0x43, 0x41,
+ 0x11, 0x00, 0xFC, 0xFF, 0x32, 0x00
};
-static unsigned char XGI330_HiTVGroup3Data[] =
-{
- 0x00,0x1A,0x22,0x63,0x62,0x22,0x08,0x5F,
- 0x05,0x21,0xB2,0xB2,0x55,0x77,0x2A,0xA6,
- 0x25,0x2F,0x47,0xFA,0xC8,0xFF,0x8E,0x20,
- 0x8C,0x6E,0x60,0x2E,0x58,0x48,0x72,0x44,
- 0x56,0x36,0x4F,0x6E,0x3F,0x80,0x00,0x80,
- 0x4F,0x7F,0x03,0xA8,0x7D,0x20,0x1A,0xA9,
- 0x14,0x05,0x03,0x7E,0x64,0x31,0x14,0x75,
- 0x18,0x05,0x18,0x05,0x4C,0xA8,0x01
+static unsigned char XGI330_YPbPr525iTiming[] = {
+ 0x1B, 0x21, 0x03, 0x09, 0x05, 0x06, 0x0C, 0x0C,
+ 0x94, 0x49, 0x01, 0x0A, 0x06, 0x0D, 0x04, 0x0A,
+ 0x06, 0x14, 0x0D, 0x04, 0x0A, 0x00, 0x85, 0x1B,
+ 0x0C, 0x50, 0x00, 0x97, 0x00, 0xDA, 0x4A, 0x17,
+ 0x7D, 0x05, 0x4B, 0x00, 0x00, 0xE2, 0x00, 0x02,
+ 0x03, 0x0A, 0x65, 0x9D, 0x08,
+ 0x92, 0x8F, 0x40, 0x60, 0x80, 0x14, 0x90, 0x8C,
+ 0x60, 0x14, 0x4B, 0x00, 0x40,
+ 0x44, 0x00, 0xDB, 0x02, 0x3B, 0x00
};
-static unsigned char XGI330_HiTVGroup3Simu[] =
-{
- 0x00,0x1A,0x22,0x63,0x62,0x22,0x08,0x95,
- 0xDB,0x20,0xB8,0xB8,0x55,0x47,0x2A,0xA6,
- 0x25,0x2F,0x47,0xFA,0xC8,0xFF,0x8E,0x20,
- 0x8C,0x6E,0x60,0x15,0x26,0xD3,0xE4,0x11,
- 0x56,0x36,0x4F,0x6E,0x3F,0x80,0x00,0x80,
- 0x67,0x36,0x01,0x47,0x0E,0x10,0xBE,0xB4,
- 0x01,0x05,0x03,0x7E,0x65,0x31,0x14,0x75,
- 0x18,0x05,0x18,0x05,0x4C,0xA8,0x01
+static unsigned char XGI330_HiTVGroup3Data[] = {
+ 0x00, 0x1A, 0x22, 0x63, 0x62, 0x22, 0x08, 0x5F,
+ 0x05, 0x21, 0xB2, 0xB2, 0x55, 0x77, 0x2A, 0xA6,
+ 0x25, 0x2F, 0x47, 0xFA, 0xC8, 0xFF, 0x8E, 0x20,
+ 0x8C, 0x6E, 0x60, 0x2E, 0x58, 0x48, 0x72, 0x44,
+ 0x56, 0x36, 0x4F, 0x6E, 0x3F, 0x80, 0x00, 0x80,
+ 0x4F, 0x7F, 0x03, 0xA8, 0x7D, 0x20, 0x1A, 0xA9,
+ 0x14, 0x05, 0x03, 0x7E, 0x64, 0x31, 0x14, 0x75,
+ 0x18, 0x05, 0x18, 0x05, 0x4C, 0xA8, 0x01
};
-static unsigned char XGI330_HiTVGroup3Text[] =
-{
- 0x00,0x1A,0x22,0x63,0x62,0x22,0x08,0xA7,
- 0xF5,0x20,0xCE,0xCE,0x55,0x47,0x2A,0xA6,
- 0x25,0x2F,0x47,0xFA,0xC8,0xFF,0x8E,0x20,
- 0x8C,0x6E,0x60,0x18,0x2C,0x0C,0x20,0x22,
- 0x56,0x36,0x4F,0x6E,0x3F,0x80,0x00,0x80,
- 0x93,0x3C,0x01,0x50,0x2F,0x10,0xF4,0xCA,
- 0x01,0x05,0x03,0x7E,0x65,0x31,0x14,0x75,
- 0x18,0x05,0x18,0x05,0x4C,0xA8,0x01
+static unsigned char XGI330_HiTVGroup3Simu[] = {
+ 0x00, 0x1A, 0x22, 0x63, 0x62, 0x22, 0x08, 0x95,
+ 0xDB, 0x20, 0xB8, 0xB8, 0x55, 0x47, 0x2A, 0xA6,
+ 0x25, 0x2F, 0x47, 0xFA, 0xC8, 0xFF, 0x8E, 0x20,
+ 0x8C, 0x6E, 0x60, 0x15, 0x26, 0xD3, 0xE4, 0x11,
+ 0x56, 0x36, 0x4F, 0x6E, 0x3F, 0x80, 0x00, 0x80,
+ 0x67, 0x36, 0x01, 0x47, 0x0E, 0x10, 0xBE, 0xB4,
+ 0x01, 0x05, 0x03, 0x7E, 0x65, 0x31, 0x14, 0x75,
+ 0x18, 0x05, 0x18, 0x05, 0x4C, 0xA8, 0x01
};
-static unsigned char XGI330_Ren525pGroup3[] =
-{
- 0x00,0x14,0x15,0x25,0x55,0x15,0x0b,0x13,
- 0xB1,0x41,0x62,0x62,0xFF,0xF4,0x45,0xa6,
- 0x25,0x2F,0x67,0xF6,0xbf,0xFF,0x8E,0x20,
- 0xAC,0xDA,0x60,0xFe,0x6A,0x9A,0x06,0x10,
- 0xd1,0x04,0x18,0x0a,0xFF,0x80,0x00,0x80,
- 0x3c,0x77,0x00,0xEF,0xE0,0x10,0xB0,0xE0,
- 0x10,0x4F,0x0F,0x0F,0x05,0x0F,0x08,0x6E,
- 0x1a,0x1F,0x25,0x2a,0x4C,0xAA,0x01
+static unsigned char XGI330_HiTVGroup3Text[] = {
+ 0x00, 0x1A, 0x22, 0x63, 0x62, 0x22, 0x08, 0xA7,
+ 0xF5, 0x20, 0xCE, 0xCE, 0x55, 0x47, 0x2A, 0xA6,
+ 0x25, 0x2F, 0x47, 0xFA, 0xC8, 0xFF, 0x8E, 0x20,
+ 0x8C, 0x6E, 0x60, 0x18, 0x2C, 0x0C, 0x20, 0x22,
+ 0x56, 0x36, 0x4F, 0x6E, 0x3F, 0x80, 0x00, 0x80,
+ 0x93, 0x3C, 0x01, 0x50, 0x2F, 0x10, 0xF4, 0xCA,
+ 0x01, 0x05, 0x03, 0x7E, 0x65, 0x31, 0x14, 0x75,
+ 0x18, 0x05, 0x18, 0x05, 0x4C, 0xA8, 0x01
};
-static unsigned char XGI330_Ren750pGroup3[] =
-{
- 0x00,0x14,0x15,0x25,0x55,0x15,0x0b,0x7a,
- 0x54,0x41,0xE7,0xE7,0xFF,0xF4,0x45,0xa6,
- 0x25,0x2F,0x67,0xF6,0xbf,0xFF,0x8E,0x20,
- 0xAC,0x6A,0x60,0x2b,0x52,0xCD,0x61,0x10,
- 0x51,0x04,0x18,0x0a,0x1F,0x80,0x00,0x80,
- 0xFF,0xA4,0x04,0x2B,0x94,0x21,0x72,0x94,
- 0x26,0x05,0x01,0x0F,0xed,0x0F,0x0A,0x64,
- 0x18,0x1D,0x23,0x28,0x4C,0xAA,0x01
+static unsigned char XGI330_Ren525pGroup3[] = {
+ 0x00, 0x14, 0x15, 0x25, 0x55, 0x15, 0x0b, 0x13,
+ 0xB1, 0x41, 0x62, 0x62, 0xFF, 0xF4, 0x45, 0xa6,
+ 0x25, 0x2F, 0x67, 0xF6, 0xbf, 0xFF, 0x8E, 0x20,
+ 0xAC, 0xDA, 0x60, 0xFe, 0x6A, 0x9A, 0x06, 0x10,
+ 0xd1, 0x04, 0x18, 0x0a, 0xFF, 0x80, 0x00, 0x80,
+ 0x3c, 0x77, 0x00, 0xEF, 0xE0, 0x10, 0xB0, 0xE0,
+ 0x10, 0x4F, 0x0F, 0x0F, 0x05, 0x0F, 0x08, 0x6E,
+ 0x1a, 0x1F, 0x25, 0x2a, 0x4C, 0xAA, 0x01
+};
+
+static unsigned char XGI330_Ren750pGroup3[] = {
+ 0x00, 0x14, 0x15, 0x25, 0x55, 0x15, 0x0b, 0x7a,
+ 0x54, 0x41, 0xE7, 0xE7, 0xFF, 0xF4, 0x45, 0xa6,
+ 0x25, 0x2F, 0x67, 0xF6, 0xbf, 0xFF, 0x8E, 0x20,
+ 0xAC, 0x6A, 0x60, 0x2b, 0x52, 0xCD, 0x61, 0x10,
+ 0x51, 0x04, 0x18, 0x0a, 0x1F, 0x80, 0x00, 0x80,
+ 0xFF, 0xA4, 0x04, 0x2B, 0x94, 0x21, 0x72, 0x94,
+ 0x26, 0x05, 0x01, 0x0F, 0xed, 0x0F, 0x0A, 0x64,
+ 0x18, 0x1D, 0x23, 0x28, 0x4C, 0xAA, 0x01
};
#if 0
-static struct XGI_PanelDelayTblStruct XGI330_PanelDelayTbl[] =
-{
-{{0x00,0x00}},
-{{0x00,0x00}},
-{{0x00,0x00}},
-{{0x00,0x00}},
-{{0x00,0x00}},
-{{0x00,0x00}},
-{{0x00,0x00}},
-{{0x00,0x00}},
-{{0x00,0x00}},
-{{0x00,0x00}},
-{{0x00,0x00}},
-{{0x00,0x00}},
-{{0x00,0x00}},
-{{0x00,0x00}},
-{{0x00,0x00}},
-{{0x00,0x00}}
+static struct XGI_PanelDelayTblStruct XGI330_PanelDelayTbl[] = {
+ { {0x00, 0x00} },
+ { {0x00, 0x00} },
+ { {0x00, 0x00} },
+ { {0x00, 0x00} },
+ { {0x00, 0x00} },
+ { {0x00, 0x00} },
+ { {0x00, 0x00} },
+ { {0x00, 0x00} },
+ { {0x00, 0x00} },
+ { {0x00, 0x00} },
+ { {0x00, 0x00} },
+ { {0x00, 0x00} },
+ { {0x00, 0x00} },
+ { {0x00, 0x00} },
+ { {0x00, 0x00} },
+ { {0x00, 0x00} }
};
-static struct XGI330_LVDSDataStruct XGI330_LVDS320x480Data_1[] =
-{
- {848, 433,400,525},
- {848, 389,400,525},
- {848, 433,400,525},
- {848, 389,400,525},
- {848, 518,400, 525},
- {1056, 628,400,525},
- {400, 525,400,525},
- {800, 449,1000, 644},
- {800, 525,1000, 635}
+static struct XGI330_LVDSDataStruct XGI330_LVDS320x480Data_1[] = {
+ {848, 433, 400, 525},
+ {848, 389, 400, 525},
+ {848, 433, 400, 525},
+ {848, 389, 400, 525},
+ {848, 518, 400, 525},
+ {1056, 628, 400, 525},
+ {400, 525, 400, 525},
+ {800, 449, 1000, 644},
+ {800, 525, 1000, 635}
};
-static struct XGI330_LVDSDataStruct XGI330_LVDS800x600Data_1[] =
-{
- {848, 433,1060, 629},
- {848, 389,1060, 629},
- {848, 433,1060, 629},
- {848, 389,1060, 629},
- {848, 518,1060, 629},
- {1056, 628,1056, 628},
- {1056, 628,1056, 628},
- {800, 449,1000, 644},
- {800, 525,1000, 635}
+static struct XGI330_LVDSDataStruct XGI330_LVDS800x600Data_1[] = {
+ {848, 433, 1060, 629},
+ {848, 389, 1060, 629},
+ {848, 433, 1060, 629},
+ {848, 389, 1060, 629},
+ {848, 518, 1060, 629},
+ {1056, 628, 1056, 628},
+ {1056, 628, 1056, 628},
+ {800, 449, 1000, 644},
+ {800, 525, 1000, 635}
};
-static struct XGI330_LVDSDataStruct XGI330_LVDS800x600Data_2[] =
-{
- {1056, 628,1056, 628},
- {1056, 628,1056, 628},
- {1056, 628,1056, 628},
- {1056, 628,1056, 628},
- {1056, 628,1056, 628},
- {1056, 628,1056, 628},
- {1056, 628,1056, 628},
- {800, 449,1000, 644},
- {800, 525,1000, 635}
+static struct XGI330_LVDSDataStruct XGI330_LVDS800x600Data_2[] = {
+ {1056, 628, 1056, 628},
+ {1056, 628, 1056, 628},
+ {1056, 628, 1056, 628},
+ {1056, 628, 1056, 628},
+ {1056, 628, 1056, 628},
+ {1056, 628, 1056, 628},
+ {1056, 628, 1056, 628},
+ {800, 449, 1000, 644},
+ {800, 525, 1000, 635}
};
#endif
-static struct XGI330_LVDSDataStruct XGI_LVDS1024x768Data_1[] =
-{
- { 960 , 438 , 1344 , 806 } , /* 00 (320x200,320x400,640x200,640x400) */
- { 960 , 388 , 1344 , 806 } , /* 01 (320x350,640x350) */
- { 1040, 438 , 1344 , 806 } , /* 02 (360x400,720x400) */
- { 1040, 388 , 1344 , 806 } , /* 03 (720x350) */
- { 960 , 518 , 1344 , 806 } , /* 04 (320x240,640x480) */
- {1120 , 638 , 1344 , 806 } , /* 05 (400x300,800x600) */
- {1344 , 806 , 1344 , 806 } /* 06 (512x384,1024x768) */
+static struct XGI330_LVDSDataStruct XGI_LVDS1024x768Data_1[] = {
+ { 960, 438, 1344, 806}, /* 00 (320x200,320x400,640x200,640x400) */
+ { 960, 388, 1344, 806}, /* 01 (320x350,640x350) */
+ {1040, 438, 1344, 806}, /* 02 (360x400,720x400) */
+ {1040, 388, 1344, 806}, /* 03 (720x350) */
+ { 960, 518, 1344, 806}, /* 04 (320x240,640x480) */
+ {1120, 638, 1344, 806}, /* 05 (400x300,800x600) */
+ {1344, 806, 1344, 806} /* 06 (512x384,1024x768) */
};
-static struct XGI330_LVDSDataStruct XGI_LVDS1024x768Data_2[] =
-{
- {1344, 806,1344, 806},
- {1344, 806,1344, 806},
- {1344, 806,1344, 806},
- {1344, 806,1344, 806},
- {1344, 806,1344, 806},
- {1344, 806,1344, 806},
- {1344, 806,1344, 806},
- {800, 449,1280, 801},
- {800, 525,1280, 813}
+static struct XGI330_LVDSDataStruct XGI_LVDS1024x768Data_2[] = {
+ {1344, 806, 1344, 806},
+ {1344, 806, 1344, 806},
+ {1344, 806, 1344, 806},
+ {1344, 806, 1344, 806},
+ {1344, 806, 1344, 806},
+ {1344, 806, 1344, 806},
+ {1344, 806, 1344, 806},
+ {800, 449, 1280, 801},
+ {800, 525, 1280, 813}
};
-static struct XGI330_LVDSDataStruct XGI_LVDS1280x1024Data_1[] =
-{
- {1048, 442,1688, 1066},
- {1048, 392,1688, 1066},
- {1048, 442,1688, 1066},
- {1048, 392,1688, 1066},
- {1048, 522,1688, 1066},
- {1208, 642,1688, 1066},
- {1432, 810,1688, 1066},
- {1688, 1066,1688, 1066}
+static struct XGI330_LVDSDataStruct XGI_LVDS1280x1024Data_1[] = {
+ {1048, 442, 1688, 1066},
+ {1048, 392, 1688, 1066},
+ {1048, 442, 1688, 1066},
+ {1048, 392, 1688, 1066},
+ {1048, 522, 1688, 1066},
+ {1208, 642, 1688, 1066},
+ {1432, 810, 1688, 1066},
+ {1688, 1066, 1688, 1066}
};
-static struct XGI330_LVDSDataStruct XGI_LVDS1280x1024Data_2[] =
-{
- {1344, 806,1344, 806},
- {1344, 806,1344, 806},
- {1344, 806,1344, 806},
- {1344, 806,1344, 806},
- {1344, 806,1344, 806},
- {1344, 806,1344, 806},
- {1344, 806,1344, 806},
- {800, 449,1280, 801},
- {800, 525,1280, 813}
+static struct XGI330_LVDSDataStruct XGI_LVDS1280x1024Data_2[] = {
+ {1344, 806, 1344, 806},
+ {1344, 806, 1344, 806},
+ {1344, 806, 1344, 806},
+ {1344, 806, 1344, 806},
+ {1344, 806, 1344, 806},
+ {1344, 806, 1344, 806},
+ {1344, 806, 1344, 806},
+ {800, 449, 1280, 801},
+ {800, 525, 1280, 813}
};
/*
-struct XGI330_LVDSDataStruct XGI_LVDS1280x768Data_1[] =
-{
- {768,438,1408,806},
- {768,388,1408,806},
- {768,438,1408,806},
- {768,388,1408,806},
- {768,518,1408,806},
- {928,638,1408,806},
- {1408,806,1408,806},
- {1408,806,1408,806},
- {1408,806,1408,806}
+struct XGI330_LVDSDataStruct XGI_LVDS1280x768Data_1[] = {
+ {768, 438, 1408, 806},
+ {768, 388, 1408, 806},
+ {768, 438, 1408, 806},
+ {768, 388, 1408, 806},
+ {768, 518, 1408, 806},
+ {928, 638, 1408, 806},
+ {1408, 806, 1408, 806},
+ {1408, 806, 1408, 806},
+ {1408, 806, 1408, 806}
};
-struct XGI330_LVDSDataStruct XGI_LVDS1280x768Data_2[] =
-{
- {1408, 806,1408, 806},
- {1408, 806,1408, 806},
- {1408, 806,1408, 806},
- {1408, 806,1408, 806},
- {1408, 806,1408, 806},
- {1408, 806,1408, 806},
- {1408, 806,1408, 806},
- {1408, 806,1408, 806},
- {1408, 806,1408, 806}
+struct XGI330_LVDSDataStruct XGI_LVDS1280x768Data_2[] = {
+ {1408, 806, 1408, 806},
+ {1408, 806, 1408, 806},
+ {1408, 806, 1408, 806},
+ {1408, 806, 1408, 806},
+ {1408, 806, 1408, 806},
+ {1408, 806, 1408, 806},
+ {1408, 806, 1408, 806},
+ {1408, 806, 1408, 806},
+ {1408, 806, 1408, 806}
};
-struct XGI330_LVDSDataStruct XGI_LVDS1280x768NData_1[] =
-{
- {704, 438,1344, 806},
- {704, 388,1344, 806},
- {704, 438,1344, 806},
- {704, 388,1344, 806},
- {704, 518,1344, 806},
- {864, 638,1344, 806},
- {1088, 806,1344, 806},
- {1344, 806,1344, 806},
- {1344, 806,1344, 806}
+struct XGI330_LVDSDataStruct XGI_LVDS1280x768NData_1[] = {
+ {704, 438, 1344, 806},
+ {704, 388, 1344, 806},
+ {704, 438, 1344, 806},
+ {704, 388, 1344, 806},
+ {704, 518, 1344, 806},
+ {864, 638, 1344, 806},
+ {1088, 806, 1344, 806},
+ {1344, 806, 1344, 806},
+ {1344, 806, 1344, 806}
};
-struct XGI330_LVDSDataStruct XGI_LVDS1280x768NData_2[] =
-{
- {1344, 806,1344, 806},
- {1344, 806,1344, 806},
- {1344, 806,1344, 806},
- {1344, 806,1344, 806},
- {1344, 806,1344, 806},
- {1344, 806,1344, 806},
- {1344, 806,1344, 806},
- {1344, 806,1344, 806},
- {1344, 806,1344, 806}
+struct XGI330_LVDSDataStruct XGI_LVDS1280x768NData_2[] = {
+ {1344, 806, 1344, 806},
+ {1344, 806, 1344, 806},
+ {1344, 806, 1344, 806},
+ {1344, 806, 1344, 806},
+ {1344, 806, 1344, 806},
+ {1344, 806, 1344, 806},
+ {1344, 806, 1344, 806},
+ {1344, 806, 1344, 806},
+ {1344, 806, 1344, 806}
};
-struct XGI330_LVDSDataStruct XGI_LVDS1280x768SData_1[] =
-{
- {1048,438,1688,806},
- {1048,388,1688,806},
- {1148,438,1688,806},
- {1148,388,1688,806},
- {1048,518,1688,806},
- {1208,638,1688,806},
- {1432,806,1688,806},
- {1688,806,1688,806},
- {1688,806,1688,806}
+struct XGI330_LVDSDataStruct XGI_LVDS1280x768SData_1[] = {
+ {1048, 438, 1688, 806},
+ {1048, 388, 1688, 806},
+ {1148, 438, 1688, 806},
+ {1148, 388, 1688, 806},
+ {1048, 518, 1688, 806},
+ {1208, 638, 1688, 806},
+ {1432, 806, 1688, 806},
+ {1688, 806, 1688, 806},
+ {1688, 806, 1688, 806}
};
-struct XGI330_LVDSDataStruct XGI_LVDS1280x768SData_2[] =
-{
- {1688,806,1688,806},
- {1688,806,1688,806},
- {1688,806,1688,806},
- {1688,806,1688,806},
- {1688,806,1688,806},
- {1688,806,1688,806},
- {1688,806,1688,806},
- {1688,806,1688,806},
- {1688,806,1688,806}
+struct XGI330_LVDSDataStruct XGI_LVDS1280x768SData_2[] = {
+ {1688, 806, 1688, 806},
+ {1688, 806, 1688, 806},
+ {1688, 806, 1688, 806},
+ {1688, 806, 1688, 806},
+ {1688, 806, 1688, 806},
+ {1688, 806, 1688, 806},
+ {1688, 806, 1688, 806},
+ {1688, 806, 1688, 806},
+ {1688, 806, 1688, 806}
};
*/
-static struct XGI330_LVDSDataStruct XGI_LVDS1400x1050Data_1[] =
-{
- {928,416,1688,1066},
- {928,366,1688,1066},
- {928,416,1688,1066},
- {928,366,1688,1066},
- {928,496,1688,1066},
- {1088,616,1688,1066},
- {1312,784,1688,1066},
- {1568,1040,1688,1066},
- {1688,1066,1688,1066}
+static struct XGI330_LVDSDataStruct XGI_LVDS1400x1050Data_1[] = {
+ {928, 416, 1688, 1066},
+ {928, 366, 1688, 1066},
+ {928, 416, 1688, 1066},
+ {928, 366, 1688, 1066},
+ {928, 496, 1688, 1066},
+ {1088, 616, 1688, 1066},
+ {1312, 784, 1688, 1066},
+ {1568, 1040, 1688, 1066},
+ {1688, 1066, 1688, 1066}
};
-static struct XGI330_LVDSDataStruct XGI_LVDS1400x1050Data_2[] =
-{
- {1688,1066,1688,1066},
- {1688,1066,1688,1066},
- {1688,1066,1688,1066},
- {1688,1066,1688,1066},
- {1688,1066,1688,1066},
- {1688,1066,1688,1066},
- {1688,1066,1688,1066},
- {1688,1066,1688,1066},
- {1688,1066,1688,1066}
+static struct XGI330_LVDSDataStruct XGI_LVDS1400x1050Data_2[] = {
+ {1688, 1066, 1688, 1066},
+ {1688, 1066, 1688, 1066},
+ {1688, 1066, 1688, 1066},
+ {1688, 1066, 1688, 1066},
+ {1688, 1066, 1688, 1066},
+ {1688, 1066, 1688, 1066},
+ {1688, 1066, 1688, 1066},
+ {1688, 1066, 1688, 1066},
+ {1688, 1066, 1688, 1066}
};
-static struct XGI330_LVDSDataStruct XGI_LVDS1600x1200Data_1[] =
-{ /* ;;[ycchen] 12/05/02 LCDHTxLCDVT=2048x1320 */
- { 1088,520,2048,1320 },/* 00 (320x200,320x400,640x200,640x400) */
- { 1088,470,2048,1320 },/* 01 (320x350,640x350) */
- { 1088,520,2048,1320 },/* 02 (360x400,720x400) */
- { 1088,470,2048,1320 },/* 03 (720x350) */
- { 1088,600,2048,1320 },/* 04 (320x240,640x480) */
- { 1248,720,2048,1320 },/* 05 (400x300,800x600) */
- { 1472,888,2048,1320 },/* 06 (512x384,1024x768) */
- { 1728,1144,2048,1320 },/* 07 (640x512,1280x1024) */
- { 1848,1170,2048,1320 },/* 08 (1400x1050) */
- { 2048,1320,2048,1320 } /* 09 (1600x1200) */
+/* ;;[ycchen] 12/05/02 LCDHTxLCDVT=2048x1320 */
+static struct XGI330_LVDSDataStruct XGI_LVDS1600x1200Data_1[] = {
+ {1088, 520, 2048, 1320}, /* 00 (320x200,320x400,640x200,640x400) */
+ {1088, 470, 2048, 1320}, /* 01 (320x350,640x350) */
+ {1088, 520, 2048, 1320}, /* 02 (360x400,720x400) */
+ {1088, 470, 2048, 1320}, /* 03 (720x350) */
+ {1088, 600, 2048, 1320}, /* 04 (320x240,640x480) */
+ {1248, 720, 2048, 1320}, /* 05 (400x300,800x600) */
+ {1472, 888, 2048, 1320}, /* 06 (512x384,1024x768) */
+ {1728, 1144, 2048, 1320}, /* 07 (640x512,1280x1024) */
+ {1848, 1170, 2048, 1320}, /* 08 (1400x1050) */
+ {2048, 1320, 2048, 1320} /* 09 (1600x1200) */
};
-static struct XGI330_LVDSDataStruct XGI_LVDSNoScalingData[] =
-{
- { 800,449,800,449 }, /* 00 (320x200,320x400,640x200,640x400) */
- { 800,449,800,449 }, /* 01 (320x350,640x350) */
- { 800,449,800,449 }, /* 02 (360x400,720x400) */
- { 800,449,800,449 }, /* 03 (720x350) */
- { 800,525,800,525 }, /* 04 (640x480x60Hz) */
- { 1056,628,1056,628 }, /* 05 (800x600x60Hz) */
- { 1344,806,1344,806 }, /* 06 (1024x768x60Hz) */
- { 1688,1066,1688,1066 }, /* 07 (1280x1024x60Hz) */
- { 1688,1066,1688,1066 }, /* 08 (1400x1050x60Hz) ;;[ycchen] 12/19/02 */
- { 2160,1250,2160,1250 }, /* 09 (1600x1200x60Hz) */
- { 1688,806,1688,806 } /* 0A (1280x768x60Hz) */
+static struct XGI330_LVDSDataStruct XGI_LVDSNoScalingData[] = {
+ { 800, 449, 800, 449}, /* 00 (320x200,320x400,640x200,640x400) */
+ { 800, 449, 800, 449}, /* 01 (320x350,640x350) */
+ { 800, 449, 800, 449}, /* 02 (360x400,720x400) */
+ { 800, 449, 800, 449}, /* 03 (720x350) */
+ { 800, 525, 800, 525}, /* 04 (640x480x60Hz) */
+ {1056, 628, 1056, 628}, /* 05 (800x600x60Hz) */
+ {1344, 806, 1344, 806}, /* 06 (1024x768x60Hz) */
+ {1688, 1066, 1688, 1066}, /* 07 (1280x1024x60Hz) */
+ {1688, 1066, 1688, 1066}, /* 08 (1400x1050x60Hz) ;;[ycchen] 12/19/02 */
+ {2160, 1250, 2160, 1250}, /* 09 (1600x1200x60Hz) */
+ {1688, 806, 1688, 806} /* 0A (1280x768x60Hz) */
};
-static struct XGI330_LVDSDataStruct XGI_LVDS1024x768Data_1x75[] =
-{
- {960,438,1312,800 }, /* 00 (320x200,320x400,640x200,640x400) */
- {960,388,1312,800 }, /* 01 (320x350,640x350) */
- {1040,438,1312,800 }, /* 02 (360x400,720x400) */
- {1040,388,1312,800 }, /* 03 (720x350) */
- {928,512,1312,800 }, /* 04 (320x240,640x480) */
- {1088,632,1312,800 }, /* 05 (400x300,800x600) */
- {1312,800,1312,800 }, /* 06 (512x384,1024x768) */
+static struct XGI330_LVDSDataStruct XGI_LVDS1024x768Data_1x75[] = {
+ { 960, 438, 1312, 800}, /* 00 (320x200,320x400,640x200,640x400) */
+ { 960, 388, 1312, 800}, /* 01 (320x350,640x350) */
+ {1040, 438, 1312, 800}, /* 02 (360x400,720x400) */
+ {1040, 388, 1312, 800}, /* 03 (720x350) */
+ { 928, 512, 1312, 800}, /* 04 (320x240,640x480) */
+ {1088, 632, 1312, 800}, /* 05 (400x300,800x600) */
+ {1312, 800, 1312, 800}, /* 06 (512x384,1024x768) */
};
-static struct XGI330_LVDSDataStruct XGI_LVDS1024x768Data_2x75[] =
-{
- {1312,800,1312,800}, /* ; 00 (320x200,320x400,640x200,640x400) */
- {1312,800,1312,800}, /* ; 01 (320x350,640x350) */
- {1312,800,1312,800}, /* ; 02 (360x400,720x400) */
- {1312,800,1312,800}, /* ; 03 (720x350) */
- {1312,800,1312,800}, /* ; 04 (320x240,640x480) */
- {1312,800,1312,800}, /* ; 05 (400x300,800x600) */
- {1312,800,1312,800}, /* ; 06 (512x384,1024x768) */
+static struct XGI330_LVDSDataStruct XGI_LVDS1024x768Data_2x75[] = {
+ {1312, 800, 1312, 800}, /* ; 00 (320x200,320x400,640x200,640x400) */
+ {1312, 800, 1312, 800}, /* ; 01 (320x350,640x350) */
+ {1312, 800, 1312, 800}, /* ; 02 (360x400,720x400) */
+ {1312, 800, 1312, 800}, /* ; 03 (720x350) */
+ {1312, 800, 1312, 800}, /* ; 04 (320x240,640x480) */
+ {1312, 800, 1312, 800}, /* ; 05 (400x300,800x600) */
+ {1312, 800, 1312, 800}, /* ; 06 (512x384,1024x768) */
};
-static struct XGI330_LVDSDataStruct XGI_LVDS1280x1024Data_1x75[] =
-{
- {1048,442,1688,1066 }, /* ; 00 (320x200,320x400,640x200,640x400) */
- {1048,392,1688,1066 }, /* ; 01 (320x350,640x350) */
- {1128,442,1688,1066 }, /* ; 02 (360x400,720x400) */
- {1128,392,1688,1066 }, /* ; 03 (720x350) */
- {1048,522,1688,1066 }, /* ; 04 (320x240,640x480) */
- {1208,642,1688,1066 }, /* ; 05 (400x300,800x600) */
- {1432,810,1688,1066 }, /* ; 06 (512x384,1024x768) */
- {1688,1066,1688,1066 }, /* ; 06; 07 (640x512,1280x1024) */
+static struct XGI330_LVDSDataStruct XGI_LVDS1280x1024Data_1x75[] = {
+ {1048, 442, 1688, 1066 }, /* ; 00 (320x200,320x400,640x200,640x400) */
+ {1048, 392, 1688, 1066 }, /* ; 01 (320x350,640x350) */
+ {1128, 442, 1688, 1066 }, /* ; 02 (360x400,720x400) */
+ {1128, 392, 1688, 1066 }, /* ; 03 (720x350) */
+ {1048, 522, 1688, 1066 }, /* ; 04 (320x240,640x480) */
+ {1208, 642, 1688, 1066 }, /* ; 05 (400x300,800x600) */
+ {1432, 810, 1688, 1066 }, /* ; 06 (512x384,1024x768) */
+ {1688, 1066, 1688, 1066 }, /* ; 06; 07 (640x512,1280x1024) */
};
-static struct XGI330_LVDSDataStruct XGI_LVDS1280x1024Data_2x75[] =
-{
- {1688,1066,1688,1066 }, /* ; 00 (320x200,320x400,640x200,640x400) */
- {1688,1066,1688,1066 }, /* ; 01 (320x350,640x350) */
- {1688,1066,1688,1066 }, /* ; 02 (360x400,720x400) */
- {1688,1066,1688,1066 }, /* ; 03 (720x350) */
- {1688,1066,1688,1066 }, /* ; 04 (320x240,640x480) */
- {1688,1066,1688,1066 }, /* ; 05 (400x300,800x600) */
- {1688,1066,1688,1066 }, /* ; 06 (512x384,1024x768) */
- {1688,1066,1688,1066 }, /* ; 06; 07 (640x512,1280x1024) */
+static struct XGI330_LVDSDataStruct XGI_LVDS1280x1024Data_2x75[] = {
+ {1688, 1066, 1688, 1066 }, /* ; 00 (320x200,320x400,640x200,640x400) */
+ {1688, 1066, 1688, 1066 }, /* ; 01 (320x350,640x350) */
+ {1688, 1066, 1688, 1066 }, /* ; 02 (360x400,720x400) */
+ {1688, 1066, 1688, 1066 }, /* ; 03 (720x350) */
+ {1688, 1066, 1688, 1066 }, /* ; 04 (320x240,640x480) */
+ {1688, 1066, 1688, 1066 }, /* ; 05 (400x300,800x600) */
+ {1688, 1066, 1688, 1066 }, /* ; 06 (512x384,1024x768) */
+ {1688, 1066, 1688, 1066 }, /* ; 06; 07 (640x512,1280x1024) */
};
-static struct XGI330_LVDSDataStruct XGI_LVDSNoScalingDatax75[] =
-{
- {800,449,800,449 }, /* ; 00 (320x200,320x400,640x200,640x400) */
- {800,449,800,449 }, /* ; 01 (320x350,640x350) */
- {900,449,900,449 }, /* ; 02 (360x400,720x400) */
- {900,449,900,449 }, /* ; 03 (720x350) */
- {800,500,800,500 }, /* ; 04 (640x480x75Hz) */
- {1056,625,1056,625 }, /* ; 05 (800x600x75Hz) */
- {1312,800,1312,800 }, /* ; 06 (1024x768x75Hz) */
- {1688,1066,1688,1066 }, /* ; 07 (1280x1024x75Hz) */
- {1688,1066,1688,1066 }, /* ; 08 (1400x1050x75Hz) ;;[ycchen] 12/19/02 */
- {2160,1250,2160,1250 }, /* ; 09 (1600x1200x75Hz) */
- {1688,806,1688,806 }, /* ; 0A (1280x768x75Hz) */
+static struct XGI330_LVDSDataStruct XGI_LVDSNoScalingDatax75[] = {
+ { 800, 449, 800, 449}, /* ; 00 (320x200,320x400,640x200,640x400) */
+ { 800, 449, 800, 449}, /* ; 01 (320x350,640x350) */
+ { 900, 449, 900, 449}, /* ; 02 (360x400,720x400) */
+ { 900, 449, 900, 449}, /* ; 03 (720x350) */
+ { 800, 500, 800, 500}, /* ; 04 (640x480x75Hz) */
+ {1056, 625, 1056, 625}, /* ; 05 (800x600x75Hz) */
+ {1312, 800, 1312, 800}, /* ; 06 (1024x768x75Hz) */
+ {1688, 1066, 1688, 1066}, /* ; 07 (1280x1024x75Hz) */
+ {1688, 1066, 1688, 1066}, /* ; 08 (1400x1050x75Hz)
+ ;;[ycchen] 12/19/02 */
+ {2160, 1250, 2160, 1250}, /* ; 09 (1600x1200x75Hz) */
+ {1688, 806, 1688, 806}, /* ; 0A (1280x768x75Hz) */
};
-static struct XGI330_LVDSDataStruct XGI_LVDS1024x768Des_1[] =
-{
- { 0,1048, 0, 771 }, /* 00 (320x200,320x400,640x200,640x400) */
- { 0,1048, 0, 771 }, /* 01 (320x350,640x350) */
- { 0,1048, 0, 771 }, /* 02 (360x400,720x400) */
- { 0,1048, 0, 771 }, /* 03 (720x350) */
- { 0,1048, 0, 771 }, /* 04 (640x480x60Hz) */
- { 0,1048, 0, 771 }, /* 05 (800x600x60Hz) */
- { 0,1048, 805, 770 } /* 06 (1024x768x60Hz) */
+static struct XGI330_LVDSDataStruct XGI_LVDS1024x768Des_1[] = {
+ {0, 1048, 0, 771}, /* 00 (320x200,320x400,640x200,640x400) */
+ {0, 1048, 0, 771}, /* 01 (320x350,640x350) */
+ {0, 1048, 0, 771}, /* 02 (360x400,720x400) */
+ {0, 1048, 0, 771}, /* 03 (720x350) */
+ {0, 1048, 0, 771}, /* 04 (640x480x60Hz) */
+ {0, 1048, 0, 771}, /* 05 (800x600x60Hz) */
+ {0, 1048, 805, 770} /* 06 (1024x768x60Hz) */
} ;
-static struct XGI330_LVDSDataStruct XGI_LVDS1024x768Des_2[] =
-{
- { 1142, 856, 622, 587 }, /* 00 (320x200,320x400,640x200,640x400) */
- { 1142, 856, 597, 562 }, /* 01 (320x350,640x350) */
- { 1142, 856, 622, 587 }, /* 02 (360x400,720x400) */
- { 1142, 856, 597, 562 }, /* 03 (720x350) */
- { 1142,1048, 722, 687 }, /* 04 (640x480x60Hz) */
- { 1232, 936, 722, 687 }, /* 05 (800x600x60Hz) */
- { 0,1048, 805, 771 } /* 06 (1024x768x60Hz) */
+static struct XGI330_LVDSDataStruct XGI_LVDS1024x768Des_2[] = {
+ {1142, 856, 622, 587}, /* 00 (320x200,320x400,640x200,640x400) */
+ {1142, 856, 597, 562}, /* 01 (320x350,640x350) */
+ {1142, 856, 622, 587}, /* 02 (360x400,720x400) */
+ {1142, 856, 597, 562}, /* 03 (720x350) */
+ {1142, 1048, 722, 687}, /* 04 (640x480x60Hz) */
+ {1232, 936, 722, 687}, /* 05 (800x600x60Hz) */
+ { 0, 1048, 805, 771} /* 06 (1024x768x60Hz) */
};
-static struct XGI330_LVDSDataStruct XGI_LVDS1024x768Des_3[] =
-{
- { 320, 24, 622, 587 }, /* 00 (320x200,320x400,640x200,640x400) */
- { 320, 24, 597, 562 }, /* 01 (320x350,640x350) */
- { 320, 24, 622, 587 }, /* 02 (360x400,720x400) */
- { 320, 24, 597, 562 }, /* 03 (720x350) */
- { 320, 24, 722, 687 } /* 04 (640x480x60Hz) */
+static struct XGI330_LVDSDataStruct XGI_LVDS1024x768Des_3[] = {
+ {320, 24, 622, 587}, /* 00 (320x200,320x400,640x200,640x400) */
+ {320, 24, 597, 562}, /* 01 (320x350,640x350) */
+ {320, 24, 622, 587}, /* 02 (360x400,720x400) */
+ {320, 24, 597, 562}, /* 03 (720x350) */
+ {320, 24, 722, 687} /* 04 (640x480x60Hz) */
};
-static struct XGI330_LVDSDataStruct XGI_LVDS1280x1024Des_1[] =
-{
- { 0,1328, 0, 1025 }, /* 00 (320x200,320x400,640x200,640x400) */
- { 0,1328, 0, 1025 }, /* 01 (320x350,640x350) */
- { 0,1328, 0, 1025 }, /* 02 (360x400,720x400) */
- { 0,1328, 0, 1025 }, /* 03 (720x350) */
- { 0,1328, 0, 1025 }, /* 04 (640x480x60Hz) */
- { 0,1328, 0, 1025 }, /* 05 (800x600x60Hz) */
- { 0,1328, 0, 1025 }, /* 06 (1024x768x60Hz) */
- { 0,1328, 1065, 1024 } /* 07 (1280x1024x60Hz) */
+static struct XGI330_LVDSDataStruct XGI_LVDS1280x1024Des_1[] = {
+ {0, 1328, 0, 1025}, /* 00 (320x200,320x400,640x200,640x400) */
+ {0, 1328, 0, 1025}, /* 01 (320x350,640x350) */
+ {0, 1328, 0, 1025}, /* 02 (360x400,720x400) */
+ {0, 1328, 0, 1025}, /* 03 (720x350) */
+ {0, 1328, 0, 1025}, /* 04 (640x480x60Hz) */
+ {0, 1328, 0, 1025}, /* 05 (800x600x60Hz) */
+ {0, 1328, 0, 1025}, /* 06 (1024x768x60Hz) */
+ {0, 1328, 1065, 1024} /* 07 (1280x1024x60Hz) */
};
/* The Display setting for DE Mode Panel */
-static struct XGI330_LVDSDataStruct XGI_LVDS1280x1024Des_2[] =
-{
- { 1368,1008,752,711 }, /* 00 (320x200,320x400,640x200,640x400) */
- { 1368,1008,729,688 }, /* 01 (320x350,640x350) */
- { 1408,1048,752,711 }, /* 02 (360x400,720x400) */
- { 1408,1048,729,688 }, /* 03 (720x350) */
- { 1368,1008,794,753 }, /* 04 (640x480x60Hz) */
- { 1448,1068,854,813 }, /* 05 (800x600x60Hz) */
- { 1560,1200,938,897 }, /* 06 (1024x768x60Hz) */
- { 0000,1328,0,1025 } /* 07 (1280x1024x60Hz) */
+static struct XGI330_LVDSDataStruct XGI_LVDS1280x1024Des_2[] = {
+ {1368, 1008, 752, 711}, /* 00 (320x200,320x400,640x200,640x400) */
+ {1368, 1008, 729, 688}, /* 01 (320x350,640x350) */
+ {1408, 1048, 752, 711}, /* 02 (360x400,720x400) */
+ {1408, 1048, 729, 688}, /* 03 (720x350) */
+ {1368, 1008, 794, 753}, /* 04 (640x480x60Hz) */
+ {1448, 1068, 854, 813}, /* 05 (800x600x60Hz) */
+ {1560, 1200, 938, 897}, /* 06 (1024x768x60Hz) */
+ {0000, 1328, 0, 1025} /* 07 (1280x1024x60Hz) */
};
-static struct XGI330_LVDSDataStruct XGI_LVDS1400x1050Des_1[] =
-{
- { 0,1448,0,1051 }, /* 00 (320x200,320x400,640x200,640x400) */
- { 0,1448,0,1051 }, /* 01 (320x350,640x350) */
- { 0,1448,0,1051 }, /* 02 (360x400,720x400) */
- { 0,1448,0,1051 }, /* 03 (720x350) */
- { 0,1448,0,1051 }, /* 04 (640x480x60Hz) */
- { 0,1448,0,1051 }, /* 05 (800x600x60Hz) */
- { 0,1448,0,1051 }, /* 06 (1024x768x60Hz) */
- { 0,1448,0,1051 }, /* 07 (1280x1024x60Hz) */
- { 0,1448,0,1051 } /* 08 (1400x1050x60Hz) */
+static struct XGI330_LVDSDataStruct XGI_LVDS1400x1050Des_1[] = {
+ {0, 1448, 0, 1051}, /* 00 (320x200,320x400,640x200,640x400) */
+ {0, 1448, 0, 1051}, /* 01 (320x350,640x350) */
+ {0, 1448, 0, 1051}, /* 02 (360x400,720x400) */
+ {0, 1448, 0, 1051}, /* 03 (720x350) */
+ {0, 1448, 0, 1051}, /* 04 (640x480x60Hz) */
+ {0, 1448, 0, 1051}, /* 05 (800x600x60Hz) */
+ {0, 1448, 0, 1051}, /* 06 (1024x768x60Hz) */
+ {0, 1448, 0, 1051}, /* 07 (1280x1024x60Hz) */
+ {0, 1448, 0, 1051} /* 08 (1400x1050x60Hz) */
};
-static struct XGI330_LVDSDataStruct XGI_LVDS1400x1050Des_2[] =
-{
- { 1308,1068, 781, 766 }, /* 00 (320x200,320x400,640x200,640x400) */
- { 1308,1068, 781, 766 }, /* 01 (320x350,640x350) */
- { 1308,1068, 781, 766 }, /* 02 (360x400,720x400) */
- { 1308,1068, 781, 766 }, /* 03 (720x350) */
- { 1308,1068, 781, 766 }, /* 04 (640x480x60Hz) */
- { 1388,1148, 841, 826 }, /* 05 (800x600x60Hz) */
- { 1490,1250, 925, 910 }, /* 06 (1024x768x60Hz) */
- { 1608,1368,1053,1038 }, /* 07 (1280x1024x60Hz) */
- { 0,1448,0,1051 } /* 08 (1400x1050x60Hz) */
+static struct XGI330_LVDSDataStruct XGI_LVDS1400x1050Des_2[] = {
+ {1308, 1068, 781, 766}, /* 00 (320x200,320x400,640x200,640x400) */
+ {1308, 1068, 781, 766}, /* 01 (320x350,640x350) */
+ {1308, 1068, 781, 766}, /* 02 (360x400,720x400) */
+ {1308, 1068, 781, 766}, /* 03 (720x350) */
+ {1308, 1068, 781, 766}, /* 04 (640x480x60Hz) */
+ {1388, 1148, 841, 826}, /* 05 (800x600x60Hz) */
+ {1490, 1250, 925, 910}, /* 06 (1024x768x60Hz) */
+ {1608, 1368, 1053, 1038}, /* 07 (1280x1024x60Hz) */
+ { 0, 1448, 0, 1051} /* 08 (1400x1050x60Hz) */
};
-static struct XGI330_LVDSDataStruct XGI_LVDS1600x1200Des_1[] =
-{
- { 0,1664,0,1201 }, /* 00 (320x200,320x400,640x200,640x400) */
- { 0,1664,0,1201 }, /* 01 (320x350,640x350) */
- { 0,1664,0,1201 }, /* 02 (360x400,720x400) */
- { 0,1664,0,1201 }, /* 03 (720x350) */
- { 0,1664,0,1201 }, /* 04 (640x480x60Hz) */
- { 0,1664,0,1201 }, /* 05 (800x600x60Hz) */
- { 0,1664,0,1201 }, /* 06 (1024x768x60Hz) */
- { 0,1664,0,1201 }, /* 07 (1280x1024x60Hz) */
- { 0,1664,0,1201 }, /* 08 (1400x1050x60Hz) */
- { 0,1664,0,1201 } /* 09 (1600x1200x60Hz) */
+static struct XGI330_LVDSDataStruct XGI_LVDS1600x1200Des_1[] = {
+ {0, 1664, 0, 1201}, /* 00 (320x200,320x400,640x200,640x400) */
+ {0, 1664, 0, 1201}, /* 01 (320x350,640x350) */
+ {0, 1664, 0, 1201}, /* 02 (360x400,720x400) */
+ {0, 1664, 0, 1201}, /* 03 (720x350) */
+ {0, 1664, 0, 1201}, /* 04 (640x480x60Hz) */
+ {0, 1664, 0, 1201}, /* 05 (800x600x60Hz) */
+ {0, 1664, 0, 1201}, /* 06 (1024x768x60Hz) */
+ {0, 1664, 0, 1201}, /* 07 (1280x1024x60Hz) */
+ {0, 1664, 0, 1201}, /* 08 (1400x1050x60Hz) */
+ {0, 1664, 0, 1201} /* 09 (1600x1200x60Hz) */
};
-
-
-static struct XGI330_LCDDataDesStruct2 XGI_LVDSNoScalingDesData[] =
-{
- { 0, 648, 448, 405, 96, 2 }, /* 00 (320x200,320x400,640x200,640x400) */
- { 0, 648, 448, 355, 96, 2 }, /* 01 (320x350,640x350) */
- { 0, 648, 448, 405, 96, 2 }, /* 02 (360x400,720x400) */
- { 0, 648, 448, 355, 96, 2 }, /* 03 (720x350) */
- { 0, 648, 1, 483, 96, 2 }, /* 04 (640x480x60Hz) */
- { 0, 840, 627, 600, 128, 4 }, /* 05 (800x600x60Hz) */
- { 0,1048, 805, 770, 136, 6 }, /* 06 (1024x768x60Hz) */
- { 0,1328,0,1025, 112, 3 }, /* 07 (1280x1024x60Hz) */
- { 0,1438,0,1051, 112, 3 }, /* 08 (1400x1050x60Hz) ;;[ycchen] 12/19/02 */
- { 0,1664,0,1201, 192, 3 }, /* 09 (1600x1200x60Hz) */
- { 0,1328,0,0771, 112, 6 } /* 0A (1280x768x60Hz) */
+static struct XGI330_LCDDataDesStruct2 XGI_LVDSNoScalingDesData[] = {
+ {0, 648, 448, 405, 96, 2}, /* 00 (320x200,320x400,
+ 640x200,640x400) */
+ {0, 648, 448, 355, 96, 2}, /* 01 (320x350,640x350) */
+ {0, 648, 448, 405, 96, 2}, /* 02 (360x400,720x400) */
+ {0, 648, 448, 355, 96, 2}, /* 03 (720x350) */
+ {0, 648, 1, 483, 96, 2}, /* 04 (640x480x60Hz) */
+ {0, 840, 627, 600, 128, 4}, /* 05 (800x600x60Hz) */
+ {0, 1048, 805, 770, 136, 6}, /* 06 (1024x768x60Hz) */
+ {0, 1328, 0, 1025, 112, 3}, /* 07 (1280x1024x60Hz) */
+ {0, 1438, 0, 1051, 112, 3}, /* 08 (1400x1050x60Hz)
+ ;;[ycchen] 12/19/02 */
+ {0, 1664, 0, 1201, 192, 3}, /* 09 (1600x1200x60Hz) */
+ {0, 1328, 0, 0771, 112, 6} /* 0A (1280x768x60Hz) */
};
-static struct XGI330_LVDSDataStruct XGI_LVDS1024x768Des_1x75[] = /* ; 1024x768 Full-screen */
-{
- {0,1040,0,769}, /* ; 00 (320x200,320x400,640x200,640x400) */
- {0,1040,0,769}, /* ; 01 (320x350,640x350) */
- {0,1040,0,769}, /* ; 02 (360x400,720x400) */
- {0,1040,0,769}, /* ; 03 (720x350) */
- {0,1040,0,769}, /* ; 04 (640x480x75Hz) */
- {0,1040,0,769}, /* ; 05 (800x600x75Hz) */
- {0,1040,0,769} /* ; 06 (1024x768x75Hz) */
+/* ; 1024x768 Full-screen */
+static struct XGI330_LVDSDataStruct XGI_LVDS1024x768Des_1x75[] = {
+ {0, 1040, 0, 769}, /* ; 00 (320x200,320x400,640x200,640x400) */
+ {0, 1040, 0, 769}, /* ; 01 (320x350,640x350) */
+ {0, 1040, 0, 769}, /* ; 02 (360x400,720x400) */
+ {0, 1040, 0, 769}, /* ; 03 (720x350) */
+ {0, 1040, 0, 769}, /* ; 04 (640x480x75Hz) */
+ {0, 1040, 0, 769}, /* ; 05 (800x600x75Hz) */
+ {0, 1040, 0, 769} /* ; 06 (1024x768x75Hz) */
};
-static struct XGI330_LVDSDataStruct XGI_LVDS1024x768Des_2x75[] = /* ; 1024x768 center-screen (Enh. Mode) */
-{
- {1142, 856,622,587 }, /* 00 (320x200,320x400,640x200,640x400) */
- {1142, 856,597,562 }, /* 01 (320x350,640x350) */
- {1142, 856,622,587 }, /* 02 (360x400,720x400) */
- {1142, 856,597,562 }, /* 03 (720x350) */
- {1142,1048,722,687 }, /* 04 (640x480x60Hz) */
- {1232, 936,722,687 }, /* 05 (800x600x60Hz) */
- { 0,1048,805,771 } /* 06 (1024x768x60Hz) */
+/* ; 1024x768 center-screen (Enh. Mode) */
+static struct XGI330_LVDSDataStruct XGI_LVDS1024x768Des_2x75[] = {
+ {1142, 856, 622, 587}, /* 00 (320x200,320x400,640x200,640x400) */
+ {1142, 856, 597, 562}, /* 01 (320x350,640x350) */
+ {1142, 856, 622, 587}, /* 02 (360x400,720x400) */
+ {1142, 856, 597, 562}, /* 03 (720x350) */
+ {1142, 1048, 722, 687}, /* 04 (640x480x60Hz) */
+ {1232, 936, 722, 687}, /* 05 (800x600x60Hz) */
+ { 0, 1048, 805, 771} /* 06 (1024x768x60Hz) */
};
-static struct XGI330_LVDSDataStruct XGI_LVDS1024x768Des_3x75[] = /* ; 1024x768 center-screen (St.Mode) */
-{
- {320,24,622,587 }, /* ; 00 (320x200,320x400,640x200,640x400) */
- {320,24,597,562 }, /* ; 01 (320x350,640x350) */
- {320,24,622,587 }, /* ; 02 (360x400,720x400) */
- {320,24,597,562 }, /* ; 03 (720x350) */
- {320,24,722,687 } /* ; 04 (640x480x60Hz) */
+/* ; 1024x768 center-screen (St.Mode) */
+static struct XGI330_LVDSDataStruct XGI_LVDS1024x768Des_3x75[] = {
+ {320, 24, 622, 587}, /* ; 00 (320x200,320x400,640x200,640x400) */
+ {320, 24, 597, 562}, /* ; 01 (320x350,640x350) */
+ {320, 24, 622, 587}, /* ; 02 (360x400,720x400) */
+ {320, 24, 597, 562}, /* ; 03 (720x350) */
+ {320, 24, 722, 687} /* ; 04 (640x480x60Hz) */
};
-static struct XGI330_LVDSDataStruct XGI_LVDS1280x1024Des_1x75[] =
-{
- {0,1296,0,1025}, /* ; 00 (320x200,320x400,640x200,640x400) */
- {0,1296,0,1025}, /* ; 01 (320x350,640x350) */
- {0,1296,0,1025}, /* ; 02 (360x400,720x400) */
- {0,1296,0,1025}, /* ; 03 (720x350) */
- {0,1296,0,1025}, /* ; 04 (640x480x75Hz) */
- {0,1296,0,1025}, /* ; 05 (800x600x75Hz) */
- {0,1296,0,1025}, /* ; 06 (1024x768x75Hz) */
- {0,1296,0,1025} /* ; 07 (1280x1024x75Hz) */
+static struct XGI330_LVDSDataStruct XGI_LVDS1280x1024Des_1x75[] = {
+ {0, 1296, 0, 1025}, /* ; 00 (320x200,320x400,640x200,640x400) */
+ {0, 1296, 0, 1025}, /* ; 01 (320x350,640x350) */
+ {0, 1296, 0, 1025}, /* ; 02 (360x400,720x400) */
+ {0, 1296, 0, 1025}, /* ; 03 (720x350) */
+ {0, 1296, 0, 1025}, /* ; 04 (640x480x75Hz) */
+ {0, 1296, 0, 1025}, /* ; 05 (800x600x75Hz) */
+ {0, 1296, 0, 1025}, /* ; 06 (1024x768x75Hz) */
+ {0, 1296, 0, 1025} /* ; 07 (1280x1024x75Hz) */
};
/* The Display setting for DE Mode Panel */
-static struct XGI330_LVDSDataStruct XGI_LVDS1280x1024Des_2x75[] = /* [ycchen] 02/18/03 Set DE as default */
-{
- {1368,976,752,711 }, /* ; 00 (320x200,320x400,640x200,640x400) */
- {1368,976,729,688 }, /* ; 01 (320x350,640x350) */
- {1408,976,752,711 }, /* ; 02 (360x400,720x400) */
- {1408,976,729,688 }, /* ; 03 (720x350) */
- {1368,976,794,753 }, /* ; 04 (640x480x75Hz) */
- {1448,1036,854,813}, /* ; 05 (800x600x75Hz) */
- {1560,1168,938,897}, /* ; 06 (1024x768x75Hz) */
- {0,1296,0,1025 } /* ; 07 (1280x1024x75Hz) */
+/* [ycchen] 02/18/03 Set DE as default */
+static struct XGI330_LVDSDataStruct XGI_LVDS1280x1024Des_2x75[] = {
+ {1368, 976, 752, 711}, /* ; 00 (320x200,320x400,640x200,640x400) */
+ {1368, 976, 729, 688}, /* ; 01 (320x350,640x350) */
+ {1408, 976, 752, 711}, /* ; 02 (360x400,720x400) */
+ {1408, 976, 729, 688}, /* ; 03 (720x350) */
+ {1368, 976, 794, 753}, /* ; 04 (640x480x75Hz) */
+ {1448, 1036, 854, 813}, /* ; 05 (800x600x75Hz) */
+ {1560, 1168, 938, 897}, /* ; 06 (1024x768x75Hz) */
+ { 0, 1296, 0, 1025} /* ; 07 (1280x1024x75Hz) */
};
-static struct XGI330_LCDDataDesStruct2 XGI_LVDSNoScalingDesDatax75[] = /* Scaling LCD 75Hz */
-{
- { 0,648,448,405,96,2 }, /* ; 00 (320x200,320x400,640x200,640x400) */
- { 0,648,448,355,96,2 }, /* ; 01 (320x350,640x350) */
- { 0,729,448,405,108,2 }, /* ; 02 (360x400,720x400) */
- { 0,729,448,355,108,2 }, /* ; 03 (720x350) */
- { 0,656,0,481,64,3 }, /* ; 04 (640x480x75Hz) */
- { 0,816,0,601,80,3 }, /* ; 05 (800x600x75Hz) */
- { 0,1040,0,769,96,3 }, /* ; 06 (1024x768x75Hz) */
- { 0,1296,0,1025,144,3 }, /* ; 07 (1280x1024x75Hz) */
- { 0,1448,0,1051,112,3 }, /* ; 08 (1400x1050x75Hz) ;;[ycchen] 12/19/02 */
- { 0,1664,0,1201,192,3 }, /* ; 09 (1600x1200x75Hz) */
- { 0,1328,0,771,112,6 } /* ; 0A (1280x768x75Hz) */
+/* Scaling LCD 75Hz */
+static struct XGI330_LCDDataDesStruct2 XGI_LVDSNoScalingDesDatax75[] = {
+ {0, 648, 448, 405, 96, 2}, /* ; 00 (320x200,320x400,
+ 640x200,640x400) */
+ {0, 648, 448, 355, 96, 2}, /* ; 01 (320x350,640x350) */
+ {0, 729, 448, 405, 108, 2}, /* ; 02 (360x400,720x400) */
+ {0, 729, 448, 355, 108, 2}, /* ; 03 (720x350) */
+ {0, 656, 0, 481, 64, 3}, /* ; 04 (640x480x75Hz) */
+ {0, 816, 0, 601, 80, 3}, /* ; 05 (800x600x75Hz) */
+ {0, 1040, 0, 769, 96, 3}, /* ; 06 (1024x768x75Hz) */
+ {0, 1296, 0, 1025, 144, 3}, /* ; 07 (1280x1024x75Hz) */
+ {0, 1448, 0, 1051, 112, 3}, /* ; 08 (1400x1050x75Hz)
+ ;;[ycchen] 12/19/02 */
+ {0, 1664, 0, 1201, 192, 3}, /* ; 09 (1600x1200x75Hz) */
+ {0, 1328, 0, 771, 112, 6} /* ; 0A (1280x768x75Hz) */
};
#if 0
-static struct XGI330_LVDSDataStruct XGI330_LVDS640x480Data_1[] =
-{
- {800, 449, 800, 449},
- {800, 449, 800, 449},
- {800, 449, 800, 449},
- {800, 449, 800, 449},
- {800, 525, 800, 525},
- {1056, 628,1056, 628},
- {1056, 628,1056, 628},
- {1056, 628,1056, 628},
- {1056, 628,1056, 628}
+static struct XGI330_LVDSDataStruct XGI330_LVDS640x480Data_1[] = {
+ { 800, 449, 800, 449},
+ { 800, 449, 800, 449},
+ { 800, 449, 800, 449},
+ { 800, 449, 800, 449},
+ { 800, 525, 800, 525},
+ {1056, 628, 1056, 628},
+ {1056, 628, 1056, 628},
+ {1056, 628, 1056, 628},
+ {1056, 628, 1056, 628}
};
#endif
-static struct XGI330_CHTVDataStruct XGI_CHTVUNTSCData[] =
-{
- {840, 600, 840, 600},
- {840, 600, 840, 600},
- {840, 600, 840, 600},
- {840, 600, 840, 600},
- {784, 600, 784, 600},
- {1064, 750,1064, 750}
+static struct XGI330_CHTVDataStruct XGI_CHTVUNTSCData[] = {
+ { 840, 600, 840, 600},
+ { 840, 600, 840, 600},
+ { 840, 600, 840, 600},
+ { 840, 600, 840, 600},
+ { 784, 600, 784, 600},
+ {1064, 750, 1064, 750}
};
-static struct XGI330_CHTVDataStruct XGI_CHTVONTSCData[] =
-{
- {840, 525, 840, 525},
- {840, 525, 840, 525},
- {840, 525, 840, 525},
- {840, 525, 840, 525},
- {784, 525, 784, 525},
- {1040, 700,1040, 700}
+static struct XGI330_CHTVDataStruct XGI_CHTVONTSCData[] = {
+ { 840, 525, 840, 525},
+ { 840, 525, 840, 525},
+ { 840, 525, 840, 525},
+ { 840, 525, 840, 525},
+ { 784, 525, 784, 525},
+ {1040, 700, 1040, 700}
};
-static struct XGI330_CHTVDataStruct XGI_CHTVUPALData[] =
-{
- {1008, 625,1008, 625},
- {1008, 625,1008, 625},
- {1008, 625,1008, 625},
- {1008, 625,1008, 625},
- {840, 750, 840, 750},
- {936, 836, 936, 836}
+static struct XGI330_CHTVDataStruct XGI_CHTVUPALData[] = {
+ {1008, 625, 1008, 625},
+ {1008, 625, 1008, 625},
+ {1008, 625, 1008, 625},
+ {1008, 625, 1008, 625},
+ { 840, 750, 840, 750},
+ { 936, 836, 936, 836}
};
-static struct XGI330_CHTVDataStruct XGI_CHTVOPALData[] =
-{
- {1008, 625,1008, 625},
- {1008, 625,1008, 625},
- {1008, 625,1008, 625},
- {1008, 625,1008, 625},
- {840, 625, 840, 625},
- {960, 750, 960, 750}
+static struct XGI330_CHTVDataStruct XGI_CHTVOPALData[] = {
+ {1008, 625, 1008, 625},
+ {1008, 625, 1008, 625},
+ {1008, 625, 1008, 625},
+ {1008, 625, 1008, 625},
+ {840, 625, 840, 625},
+ {960, 750, 960, 750}
};
-static struct XGI_LVDSCRT1HDataStruct XGI_LVDSCRT11024x768_1_H[] =
-{
- /* CR00,CR02,CR03,CR04,CR05,SR0B,SR0C,SR0E */
- {{ 0x4B,0x27,0x8F,0x32,0x1B,0x00,0x45,0x00 }}, /* 00 (320x) */
- {{ 0x4B,0x27,0x8F,0x2B,0x03,0x00,0x44,0x00 }}, /* 01 (360x) */
- {{ 0x55,0x31,0x99,0x46,0x1D,0x00,0x55,0x00 }}, /* 02 (400x) */
- {{ 0x63,0x3F,0x87,0x4A,0x93,0x00,0x01,0x00 }}, /* 03 (512x) */
- {{ 0x73,0x4F,0x97,0x55,0x86,0x00,0x05,0x00 }}, /* 04 (640x) */
- {{ 0x73,0x4F,0x97,0x55,0x86,0x00,0x05,0x00 }}, /* 05 (720x) */
- {{ 0x87,0x63,0x8B,0x69,0x1A,0x00,0x26,0x00 }}, /* 06 (800x) */
- {{ 0xA3,0x7F,0x87,0x86,0x97,0x00,0x02,0x00 }} /* 07 (1024x) */
+/* CR00,CR02,CR03,CR04,CR05,SR0B,SR0C,SR0E */
+static struct XGI_LVDSCRT1HDataStruct XGI_LVDSCRT11024x768_1_H[] = {
+ { {0x4B, 0x27, 0x8F, 0x32, 0x1B, 0x00, 0x45, 0x00} }, /* 00 (320x) */
+ { {0x4B, 0x27, 0x8F, 0x2B, 0x03, 0x00, 0x44, 0x00} }, /* 01 (360x) */
+ { {0x55, 0x31, 0x99, 0x46, 0x1D, 0x00, 0x55, 0x00} }, /* 02 (400x) */
+ { {0x63, 0x3F, 0x87, 0x4A, 0x93, 0x00, 0x01, 0x00} }, /* 03 (512x) */
+ { {0x73, 0x4F, 0x97, 0x55, 0x86, 0x00, 0x05, 0x00} }, /* 04 (640x) */
+ { {0x73, 0x4F, 0x97, 0x55, 0x86, 0x00, 0x05, 0x00} }, /* 05 (720x) */
+ { {0x87, 0x63, 0x8B, 0x69, 0x1A, 0x00, 0x26, 0x00} }, /* 06 (800x) */
+ { {0xA3, 0x7F, 0x87, 0x86, 0x97, 0x00, 0x02, 0x00} } /* 07 (1024x) */
};
-static struct XGI_LVDSCRT1HDataStruct XGI_LVDSCRT11280x1024_1_H[] =
-{
- /* CR00,CR02,CR03,CR04,CR05,SR0B,SR0C,SR0E */
- {{ 0x56,0x27,0x9A,0x30,0x1E,0x00,0x05,0x00 }}, /* 00 (320x) */
- {{ 0x56,0x27,0x9A,0x30,0x1E,0x00,0x05,0x00 }}, /* 01 (360x) */
- {{ 0x60,0x31,0x84,0x3A,0x88,0x00,0x01,0x00 }}, /* 02 (400x) */
- {{ 0x6E,0x3F,0x92,0x48,0x96,0x00,0x01,0x00 }}, /* 03 (512x) */
- {{ 0x7E,0x4F,0x82,0x58,0x06,0x00,0x06,0x00 }}, /* 04 (640x) */
- {{ 0x7E,0x4F,0x82,0x58,0x06,0x00,0x06,0x00 }}, /* 05 (720x) */
- {{ 0x92,0x63,0x96,0x6C,0x1A,0x00,0x06,0x00 }}, /* 06 (800x) */
- {{ 0xAE,0x7F,0x92,0x88,0x96,0x00,0x02,0x00 }}, /* 07 (1024x) */
- {{ 0xCE,0x9F,0x92,0xA8,0x16,0x00,0x07,0x00 }} /* 08 (1280x) */
+/* CR00,CR02,CR03,CR04,CR05,SR0B,SR0C,SR0E */
+static struct XGI_LVDSCRT1HDataStruct XGI_LVDSCRT11280x1024_1_H[] = {
+ { {0x56, 0x27, 0x9A, 0x30, 0x1E, 0x00, 0x05, 0x00 } }, /* 00 (320x) */
+ { {0x56, 0x27, 0x9A, 0x30, 0x1E, 0x00, 0x05, 0x00 } }, /* 01 (360x) */
+ { {0x60, 0x31, 0x84, 0x3A, 0x88, 0x00, 0x01, 0x00 } }, /* 02 (400x) */
+ { {0x6E, 0x3F, 0x92, 0x48, 0x96, 0x00, 0x01, 0x00 } }, /* 03 (512x) */
+ { {0x7E, 0x4F, 0x82, 0x58, 0x06, 0x00, 0x06, 0x00 } }, /* 04 (640x) */
+ { {0x7E, 0x4F, 0x82, 0x58, 0x06, 0x00, 0x06, 0x00 } }, /* 05 (720x) */
+ { {0x92, 0x63, 0x96, 0x6C, 0x1A, 0x00, 0x06, 0x00 } }, /* 06 (800x) */
+ { {0xAE, 0x7F, 0x92, 0x88, 0x96, 0x00, 0x02, 0x00 } }, /* 07 (1024x) */
+ { {0xCE, 0x9F, 0x92, 0xA8, 0x16, 0x00, 0x07, 0x00 } } /* 08 (1280x) */
};
-static struct XGI_LVDSCRT1HDataStruct XGI_LVDSCRT11024x768_2_H[] =
-{
- /* CR00,CR02,CR03,CR04,CR05,SR0B,SR0C,SR0E */
- {{ 0x63,0x27,0x87,0x3B,0x8C,0x00,0x01,0x00 }}, /* 00 (320x) */
- {{ 0x63,0x27,0x87,0x3B,0x8C,0x00,0x01,0x00 }}, /* 01 (360x) */
- {{ 0x63,0x31,0x87,0x3D,0x8E,0x00,0x01,0x00 }}, /* 02 (400x) */
- {{ 0x63,0x3F,0x87,0x45,0x96,0x00,0x01,0x00 }}, /* 03 (512x) */
- {{ 0xA3,0x4F,0x87,0x6E,0x9F,0x00,0x06,0x00 }}, /* 04 (640x) */
- {{ 0xA3,0x4F,0x87,0x6E,0x9F,0x00,0x06,0x00 }}, /* 05 (720x) */
- {{ 0xA3,0x63,0x87,0x78,0x89,0x00,0x02,0x00 }}, /* 06 (800x) */
- {{ 0xA3,0x7F,0x87,0x86,0x97,0x00,0x02,0x00 }} /* 07 (1024x) */
+/* CR00,CR02,CR03,CR04,CR05,SR0B,SR0C,SR0E */
+static struct XGI_LVDSCRT1HDataStruct XGI_LVDSCRT11024x768_2_H[] = {
+ { {0x63, 0x27, 0x87, 0x3B, 0x8C, 0x00, 0x01, 0x00} }, /* 00 (320x) */
+ { {0x63, 0x27, 0x87, 0x3B, 0x8C, 0x00, 0x01, 0x00} }, /* 01 (360x) */
+ { {0x63, 0x31, 0x87, 0x3D, 0x8E, 0x00, 0x01, 0x00} }, /* 02 (400x) */
+ { {0x63, 0x3F, 0x87, 0x45, 0x96, 0x00, 0x01, 0x00} }, /* 03 (512x) */
+ { {0xA3, 0x4F, 0x87, 0x6E, 0x9F, 0x00, 0x06, 0x00} }, /* 04 (640x) */
+ { {0xA3, 0x4F, 0x87, 0x6E, 0x9F, 0x00, 0x06, 0x00} }, /* 05 (720x) */
+ { {0xA3, 0x63, 0x87, 0x78, 0x89, 0x00, 0x02, 0x00} }, /* 06 (800x) */
+ { {0xA3, 0x7F, 0x87, 0x86, 0x97, 0x00, 0x02, 0x00} } /* 07 (1024x) */
};
-static struct XGI_LVDSCRT1HDataStruct XGI_LVDSCRT11280x1024_2_H[] =
-{
- /* CR00,CR02,CR03,CR04,CR05,SR0B,SR0C,SR0E */
- {{ 0x7E,0x3B,0x9A,0x44,0x12,0x00,0x01,0x00 }}, /* 00 (320x) */
- {{ 0x7E,0x3B,0x9A,0x44,0x12,0x00,0x01,0x00 }}, /* 01 (360x) */
- {{ 0x7E,0x40,0x84,0x49,0x91,0x00,0x01,0x00 }}, /* 02 (400x) */
- {{ 0x7E,0x47,0x93,0x50,0x9E,0x00,0x01,0x00 }}, /* 03 (512x) */
- {{ 0xCE,0x77,0x8A,0x80,0x8E,0x00,0x02,0x00 }}, /* 04 (640x) */
- {{ 0xCE,0x77,0x8A,0x80,0x8E,0x00,0x02,0x00 }}, /* 05 (720x) */
- {{ 0xCE,0x81,0x94,0x8A,0x98,0x00,0x02,0x00 }}, /* 06 (800x) */
- {{ 0xCE,0x8F,0x82,0x98,0x06,0x00,0x07,0x00 }}, /* 07 (1024x) */
- {{ 0xCE,0x9F,0x92,0xA8,0x16,0x00,0x07,0x00 }} /* 08 (1280x) */
+/* CR00,CR02,CR03,CR04,CR05,SR0B,SR0C,SR0E */
+static struct XGI_LVDSCRT1HDataStruct XGI_LVDSCRT11280x1024_2_H[] = {
+ { {0x7E, 0x3B, 0x9A, 0x44, 0x12, 0x00, 0x01, 0x00} }, /* 00 (320x) */
+ { {0x7E, 0x3B, 0x9A, 0x44, 0x12, 0x00, 0x01, 0x00} }, /* 01 (360x) */
+ { {0x7E, 0x40, 0x84, 0x49, 0x91, 0x00, 0x01, 0x00} }, /* 02 (400x) */
+ { {0x7E, 0x47, 0x93, 0x50, 0x9E, 0x00, 0x01, 0x00} }, /* 03 (512x) */
+ { {0xCE, 0x77, 0x8A, 0x80, 0x8E, 0x00, 0x02, 0x00} }, /* 04 (640x) */
+ { {0xCE, 0x77, 0x8A, 0x80, 0x8E, 0x00, 0x02, 0x00} }, /* 05 (720x) */
+ { {0xCE, 0x81, 0x94, 0x8A, 0x98, 0x00, 0x02, 0x00} }, /* 06 (800x) */
+ { {0xCE, 0x8F, 0x82, 0x98, 0x06, 0x00, 0x07, 0x00} }, /* 07 (1024x) */
+ { {0xCE, 0x9F, 0x92, 0xA8, 0x16, 0x00, 0x07, 0x00} } /* 08 (1280x) */
};
-static struct XGI_LVDSCRT1HDataStruct XGI_LVDSCRT11400x1050_1_H[] =
-{ /* CR00,CR02,CR03,CR04,CR05,SR0B,SR0C,SR0E */
- {{ 0x47,0x27,0x8B,0x2C,0x1A,0x00,0x05,0x00 }}, /* 00 (320x) */
- {{ 0x47,0x27,0x8B,0x30,0x1E,0x00,0x05,0x00 }}, /* 01 (360x) */
- {{ 0x51,0x31,0x95,0x36,0x04,0x00,0x01,0x00 }}, /* 02 (400x) */
- {{ 0x5F,0x3F,0x83,0x44,0x92,0x00,0x01,0x00 }}, /* 03 (512x) */
- {{ 0x6F,0x4F,0x93,0x54,0x82,0x00,0x05,0x00 }}, /* 04 (640x) */
- {{ 0x6F,0x4F,0x93,0x54,0x82,0x00,0x05,0x00 }}, /* 05 (720x) */
- {{ 0x83,0x63,0x87,0x68,0x16,0x00,0x06,0x00 }}, /* 06 (800x) */
- {{ 0x9F,0x7F,0x83,0x84,0x92,0x00,0x02,0x00 }}, /* 07 (1024x) */
- {{ 0xBF,0x9F,0x83,0xA4,0x12,0x00,0x07,0x00 }}, /* 08 (1280x) */
- {{ 0xCE,0xAE,0x92,0xB3,0x01,0x00,0x03,0x00 }} /* 09 (1400x) */
+/* CR00,CR02,CR03,CR04,CR05,SR0B,SR0C,SR0E */
+static struct XGI_LVDSCRT1HDataStruct XGI_LVDSCRT11400x1050_1_H[] = {
+ { {0x47, 0x27, 0x8B, 0x2C, 0x1A, 0x00, 0x05, 0x00} }, /* 00 (320x) */
+ { {0x47, 0x27, 0x8B, 0x30, 0x1E, 0x00, 0x05, 0x00} }, /* 01 (360x) */
+ { {0x51, 0x31, 0x95, 0x36, 0x04, 0x00, 0x01, 0x00} }, /* 02 (400x) */
+ { {0x5F, 0x3F, 0x83, 0x44, 0x92, 0x00, 0x01, 0x00} }, /* 03 (512x) */
+ { {0x6F, 0x4F, 0x93, 0x54, 0x82, 0x00, 0x05, 0x00} }, /* 04 (640x) */
+ { {0x6F, 0x4F, 0x93, 0x54, 0x82, 0x00, 0x05, 0x00} }, /* 05 (720x) */
+ { {0x83, 0x63, 0x87, 0x68, 0x16, 0x00, 0x06, 0x00} }, /* 06 (800x) */
+ { {0x9F, 0x7F, 0x83, 0x84, 0x92, 0x00, 0x02, 0x00} }, /* 07 (1024x) */
+ { {0xBF, 0x9F, 0x83, 0xA4, 0x12, 0x00, 0x07, 0x00} }, /* 08 (1280x) */
+ { {0xCE, 0xAE, 0x92, 0xB3, 0x01, 0x00, 0x03, 0x00} } /* 09 (1400x) */
};
-static struct XGI_LVDSCRT1HDataStruct XGI_LVDSCRT11400x1050_2_H[] =
-{ /* CR00,CR02,CR03,CR04,CR05,SR0B,SR0C,SR0E */
- {{ 0x76,0x3F,0x83,0x45,0x8C,0x00,0x41,0x00 }}, /* 00 (320x) */
- {{ 0x76,0x3F,0x83,0x45,0x8C,0x00,0x41,0x00 }}, /* 01 (360x) */
- {{ 0x76,0x31,0x9A,0x48,0x9F,0x00,0x41,0x00 }}, /* 02 (400x) */
- {{ 0x76,0x3F,0x9A,0x4F,0x96,0x00,0x41,0x00 }}, /* 03 (512x) */
- {{ 0xCE,0x7E,0x82,0x87,0x9E,0x00,0x02,0x00 }}, /* 04 (640x) */
- {{ 0xCE,0x7E,0x82,0x87,0x9E,0x00,0x02,0x00 }}, /* 05 (720x) */
- {{ 0xCE,0x63,0x92,0x96,0x04,0x00,0x07,0x00 }}, /* 06 (800x) */
- {{ 0xCE,0x7F,0x92,0xA4,0x12,0x00,0x07,0x00 }}, /* 07 (1024x) */
- {{ 0xCE,0x9F,0x92,0xB4,0x02,0x00,0x03,0x00 }}, /* 08 (1280x) */
- {{ 0xCE,0xAE,0x92,0xBC,0x0A,0x00,0x03,0x00 }} /* 09 (1400x) */
+/* CR00,CR02,CR03,CR04,CR05,SR0B,SR0C,SR0E */
+static struct XGI_LVDSCRT1HDataStruct XGI_LVDSCRT11400x1050_2_H[] = {
+ { {0x76, 0x3F, 0x83, 0x45, 0x8C, 0x00, 0x41, 0x00} }, /* 00 (320x) */
+ { {0x76, 0x3F, 0x83, 0x45, 0x8C, 0x00, 0x41, 0x00} }, /* 01 (360x) */
+ { {0x76, 0x31, 0x9A, 0x48, 0x9F, 0x00, 0x41, 0x00} }, /* 02 (400x) */
+ { {0x76, 0x3F, 0x9A, 0x4F, 0x96, 0x00, 0x41, 0x00} }, /* 03 (512x) */
+ { {0xCE, 0x7E, 0x82, 0x87, 0x9E, 0x00, 0x02, 0x00} }, /* 04 (640x) */
+ { {0xCE, 0x7E, 0x82, 0x87, 0x9E, 0x00, 0x02, 0x00} }, /* 05 (720x) */
+ { {0xCE, 0x63, 0x92, 0x96, 0x04, 0x00, 0x07, 0x00} }, /* 06 (800x) */
+ { {0xCE, 0x7F, 0x92, 0xA4, 0x12, 0x00, 0x07, 0x00} }, /* 07 (1024x) */
+ { {0xCE, 0x9F, 0x92, 0xB4, 0x02, 0x00, 0x03, 0x00} }, /* 08 (1280x) */
+ { {0xCE, 0xAE, 0x92, 0xBC, 0x0A, 0x00, 0x03, 0x00} } /* 09 (1400x) */
};
-static struct XGI_LVDSCRT1HDataStruct XGI_LVDSCRT11600x1200_1_H[] =
/* ;302lv channelA [ycchen] 12/05/02 LCDHT=2048 */
-{ /* ; CR00,CR02,CR03,CR04,CR05,SR0B,SR0C,SR0E */
- {{ 0x5B,0x27,0x9F,0x32,0x0A,0x00,0x01,0x00 }},/* 00 (320x) */
- {{ 0x5B,0x27,0x9F,0x32,0x0A,0x00,0x01,0x00 }},/* 01 (360x) */
- {{ 0x65,0x31,0x89,0x3C,0x94,0x00,0x01,0x00 }},/* 02 (400x) */
- {{ 0x73,0x3F,0x97,0x4A,0x82,0x00,0x05,0x00 }},/* 03 (512x) */
- {{ 0x83,0x4F,0x87,0x51,0x09,0x00,0x06,0x00 }},/* 04 (640x) */
- {{ 0x83,0x4F,0x87,0x51,0x09,0x00,0x06,0x00 }},/* 05 (720x) */
- {{ 0x97,0x63,0x9B,0x65,0x1D,0x00,0x06,0xF0 }},/* 06 (800x) */
- {{ 0xB3,0x7F,0x97,0x81,0x99,0x00,0x02,0x00 }},/* 07 (1024x) */
- {{ 0xD3,0x9F,0x97,0xA1,0x19,0x00,0x07,0x00 }},/* 08 (1280x) */
- {{ 0xE2,0xAE,0x86,0xB9,0x91,0x00,0x03,0x00 }},/* 09 (1400x) */
- {{ 0xFB,0xC7,0x9F,0xC9,0x81,0x00,0x07,0x00 }} /* 0A (1600x) */
+/* ; CR00,CR02,CR03,CR04,CR05,SR0B,SR0C,SR0E */
+static struct XGI_LVDSCRT1HDataStruct XGI_LVDSCRT11600x1200_1_H[] = {
+ { {0x5B, 0x27, 0x9F, 0x32, 0x0A, 0x00, 0x01, 0x00} }, /* 00 (320x) */
+ { {0x5B, 0x27, 0x9F, 0x32, 0x0A, 0x00, 0x01, 0x00} }, /* 01 (360x) */
+ { {0x65, 0x31, 0x89, 0x3C, 0x94, 0x00, 0x01, 0x00} }, /* 02 (400x) */
+ { {0x73, 0x3F, 0x97, 0x4A, 0x82, 0x00, 0x05, 0x00} }, /* 03 (512x) */
+ { {0x83, 0x4F, 0x87, 0x51, 0x09, 0x00, 0x06, 0x00} }, /* 04 (640x) */
+ { {0x83, 0x4F, 0x87, 0x51, 0x09, 0x00, 0x06, 0x00} }, /* 05 (720x) */
+ { {0x97, 0x63, 0x9B, 0x65, 0x1D, 0x00, 0x06, 0xF0} }, /* 06 (800x) */
+ { {0xB3, 0x7F, 0x97, 0x81, 0x99, 0x00, 0x02, 0x00} }, /* 07 (1024x) */
+ { {0xD3, 0x9F, 0x97, 0xA1, 0x19, 0x00, 0x07, 0x00} }, /* 08 (1280x) */
+ { {0xE2, 0xAE, 0x86, 0xB9, 0x91, 0x00, 0x03, 0x00} }, /* 09 (1400x) */
+ { {0xFB, 0xC7, 0x9F, 0xC9, 0x81, 0x00, 0x07, 0x00} } /* 0A (1600x) */
};
-static struct XGI_LVDSCRT1VDataStruct XGI_LVDSCRT11024x768_1_V[] =
-{ /* CR06,CR07,CR10,CR11,CR15,CR16,SR0A+CR09(5->7) */
- {{ 0x97,0x1F,0x60,0x87,0x5D,0x83,0x10 }}, /* 00 (x350) */
- {{ 0xB4,0x1F,0x92,0x89,0x8F,0xB5,0x30 }}, /* 01 (x400) */
- {{ 0x04,0x3E,0xE2,0x89,0xDF,0x05,0x00 }}, /* 02 (x480) */
- {{ 0x7C,0xF0,0x5A,0x8F,0x57,0x7D,0xA0 }}, /* 03 (x600) */
- {{ 0x24,0xF5,0x02,0x88,0xFF,0x25,0x90 }} /* 04 (x768) */
+/* CR06,CR07,CR10,CR11,CR15,CR16,SR0A+CR09(5->7) */
+static struct XGI_LVDSCRT1VDataStruct XGI_LVDSCRT11024x768_1_V[] = {
+ { {0x97, 0x1F, 0x60, 0x87, 0x5D, 0x83, 0x10} }, /* 00 (x350) */
+ { {0xB4, 0x1F, 0x92, 0x89, 0x8F, 0xB5, 0x30} }, /* 01 (x400) */
+ { {0x04, 0x3E, 0xE2, 0x89, 0xDF, 0x05, 0x00} }, /* 02 (x480) */
+ { {0x7C, 0xF0, 0x5A, 0x8F, 0x57, 0x7D, 0xA0} }, /* 03 (x600) */
+ { {0x24, 0xF5, 0x02, 0x88, 0xFF, 0x25, 0x90} } /* 04 (x768) */
};
-static struct XGI_LVDSCRT1VDataStruct XGI_LVDSCRT11024x768_2_V[] =
-{ /* CR06,CR07,CR10,CR11,CR15,CR16,SR0A */
- {{ 0x24,0xBB,0x31,0x87,0x5D,0x25,0x30 }}, /* 00 (x350) */
- {{ 0x24,0xBB,0x4A,0x80,0x8F,0x25,0x30 }}, /* 01 (x400) */
- {{ 0x24,0xBB,0x72,0x88,0xDF,0x25,0x30 }}, /* 02 (x480) */
- {{ 0x24,0xF1,0xAE,0x84,0x57,0x25,0xB0 }}, /* 03 (x600) */
- {{ 0x24,0xF5,0x02,0x88,0xFF,0x25,0x90 }} /* 04 (x768) */
+/* CR06,CR07,CR10,CR11,CR15,CR16,SR0A */
+static struct XGI_LVDSCRT1VDataStruct XGI_LVDSCRT11024x768_2_V[] = {
+ { {0x24, 0xBB, 0x31, 0x87, 0x5D, 0x25, 0x30} }, /* 00 (x350) */
+ { {0x24, 0xBB, 0x4A, 0x80, 0x8F, 0x25, 0x30} }, /* 01 (x400) */
+ { {0x24, 0xBB, 0x72, 0x88, 0xDF, 0x25, 0x30} }, /* 02 (x480) */
+ { {0x24, 0xF1, 0xAE, 0x84, 0x57, 0x25, 0xB0} }, /* 03 (x600) */
+ { {0x24, 0xF5, 0x02, 0x88, 0xFF, 0x25, 0x90} } /* 04 (x768) */
};
-static struct XGI_LVDSCRT1VDataStruct XGI_LVDSCRT11280x1024_1_V[] =
-{ /* CR06,CR07,CR10,CR11,CR15,CR16,SR0A */
- {{ 0x86,0x1F,0x5E,0x82,0x5D,0x87,0x00 }}, /* 00 (x350) */
- {{ 0xB8,0x1F,0x90,0x84,0x8F,0xB9,0x30 }}, /* 01 (x400) */
- {{ 0x08,0x3E,0xE0,0x84,0xDF,0x09,0x00 }}, /* 02 (x480) */
- {{ 0x80,0xF0,0x58,0x8C,0x57,0x81,0xA0 }}, /* 03 (x600) */
- {{ 0x28,0xF5,0x00,0x84,0xFF,0x29,0x90 }}, /* 04 (x768) */
- {{ 0x28,0x5A,0x13,0x87,0xFF,0x29,0xA9 }} /* 05 (x1024) */
+/* CR06,CR07,CR10,CR11,CR15,CR16,SR0A */
+static struct XGI_LVDSCRT1VDataStruct XGI_LVDSCRT11280x1024_1_V[] = {
+ { {0x86, 0x1F, 0x5E, 0x82, 0x5D, 0x87, 0x00} }, /* 00 (x350) */
+ { {0xB8, 0x1F, 0x90, 0x84, 0x8F, 0xB9, 0x30} }, /* 01 (x400) */
+ { {0x08, 0x3E, 0xE0, 0x84, 0xDF, 0x09, 0x00} }, /* 02 (x480) */
+ { {0x80, 0xF0, 0x58, 0x8C, 0x57, 0x81, 0xA0} }, /* 03 (x600) */
+ { {0x28, 0xF5, 0x00, 0x84, 0xFF, 0x29, 0x90} }, /* 04 (x768) */
+ { {0x28, 0x5A, 0x13, 0x87, 0xFF, 0x29, 0xA9} } /* 05 (x1024) */
};
-static struct XGI_LVDSCRT1VDataStruct XGI_LVDSCRT11280x1024_2_V[] =
-{ /* CR06,CR07,CR10,CR11,CR15,CR16,SR0A */
- {{ 0x28,0xD2,0xAF,0x83,0xAE,0xD8,0xA1 }}, /* 00 (x350) */
- {{ 0x28,0xD2,0xC8,0x8C,0xC7,0xF2,0x81 }}, /* 01 (x400) */
- {{ 0x28,0xD2,0xF0,0x84,0xEF,0x1A,0xB1 }}, /* 02 (x480) */
- {{ 0x28,0xDE,0x2C,0x8F,0x2B,0x56,0x91 }}, /* 03 (x600) */
- {{ 0x28,0xDE,0x80,0x83,0x7F,0xAA,0x91 }}, /* 04 (x768) */
- {{ 0x28,0x5A,0x13,0x87,0xFF,0x29,0xA9 }} /* 05 (x1024) */
+/* CR06,CR07,CR10,CR11,CR15,CR16,SR0A */
+static struct XGI_LVDSCRT1VDataStruct XGI_LVDSCRT11280x1024_2_V[] = {
+ { {0x28, 0xD2, 0xAF, 0x83, 0xAE, 0xD8, 0xA1} }, /* 00 (x350) */
+ { {0x28, 0xD2, 0xC8, 0x8C, 0xC7, 0xF2, 0x81} }, /* 01 (x400) */
+ { {0x28, 0xD2, 0xF0, 0x84, 0xEF, 0x1A, 0xB1} }, /* 02 (x480) */
+ { {0x28, 0xDE, 0x2C, 0x8F, 0x2B, 0x56, 0x91} }, /* 03 (x600) */
+ { {0x28, 0xDE, 0x80, 0x83, 0x7F, 0xAA, 0x91} }, /* 04 (x768) */
+ { {0x28, 0x5A, 0x13, 0x87, 0xFF, 0x29, 0xA9} } /* 05 (x1024) */
};
-static struct XGI_LVDSCRT1VDataStruct XGI_LVDSCRT11400x1050_1_V[] =
-{ /* CR06,CR07,CR10,CR11,CR15,CR16,SR0A */
- {{ 0x6C,0x1F,0x60,0x84,0x5D,0x6D,0x10 }}, /* 00 (x350) */
- {{ 0x9E,0x1F,0x93,0x86,0x8F,0x9F,0x30 }}, /* 01 (x400) */
- {{ 0xEE,0x1F,0xE2,0x86,0xDF,0xEF,0x10 }}, /* 02 (x480) */
- {{ 0x66,0xF0,0x5A,0x8e,0x57,0x67,0xA0 }}, /* 03 (x600) */
- {{ 0x0E,0xF5,0x02,0x86,0xFF,0x0F,0x90 }}, /* 04 (x768) */
- {{ 0x0E,0x5A,0x02,0x86,0xFF,0x0F,0x89 }}, /* 05 (x1024) */
- {{ 0x28,0x10,0x1A,0x80,0x19,0x29,0x0F }} /* 06 (x1050) */
+/* CR06,CR07,CR10,CR11,CR15,CR16,SR0A */
+static struct XGI_LVDSCRT1VDataStruct XGI_LVDSCRT11400x1050_1_V[] = {
+ { {0x6C, 0x1F, 0x60, 0x84, 0x5D, 0x6D, 0x10} }, /* 00 (x350) */
+ { {0x9E, 0x1F, 0x93, 0x86, 0x8F, 0x9F, 0x30} }, /* 01 (x400) */
+ { {0xEE, 0x1F, 0xE2, 0x86, 0xDF, 0xEF, 0x10} }, /* 02 (x480) */
+ { {0x66, 0xF0, 0x5A, 0x8e, 0x57, 0x67, 0xA0} }, /* 03 (x600) */
+ { {0x0E, 0xF5, 0x02, 0x86, 0xFF, 0x0F, 0x90} }, /* 04 (x768) */
+ { {0x0E, 0x5A, 0x02, 0x86, 0xFF, 0x0F, 0x89} }, /* 05 (x1024) */
+ { {0x28, 0x10, 0x1A, 0x80, 0x19, 0x29, 0x0F} } /* 06 (x1050) */
};
-static struct XGI_LVDSCRT1VDataStruct XGI_LVDSCRT11400x1050_2_V[] =
-{ /* CR06,CR07,CR10,CR11,CR15,CR16,SR0A */
- {{ 0x28,0x92,0xB6,0x83,0xB5,0xCF,0x81 }}, /* 00 (x350) */
- {{ 0x28,0x92,0xD5,0x82,0xD4,0xEE,0x81 }}, /* 01 (x400) */
- {{ 0x28,0x92,0xFD,0x8A,0xFC,0x16,0xB1 }}, /* 02 (x480) */
- {{ 0x28,0xD4,0x39,0x86,0x57,0x29,0x81 }}, /* 03 (x600) */
- {{ 0x28,0xD4,0x8D,0x9A,0xFF,0x29,0xA1 }}, /* 04 (x768) */
- {{ 0x28,0x5A,0x0D,0x9A,0xFF,0x29,0xA9 }}, /* 05 (x1024) */
- {{ 0x28,0x10,0x1A,0x87,0x19,0x29,0x8F }} /* 06 (x1050) */
+/* CR06,CR07,CR10,CR11,CR15,CR16,SR0A */
+static struct XGI_LVDSCRT1VDataStruct XGI_LVDSCRT11400x1050_2_V[] = {
+ { {0x28, 0x92, 0xB6, 0x83, 0xB5, 0xCF, 0x81} }, /* 00 (x350) */
+ { {0x28, 0x92, 0xD5, 0x82, 0xD4, 0xEE, 0x81} }, /* 01 (x400) */
+ { {0x28, 0x92, 0xFD, 0x8A, 0xFC, 0x16, 0xB1} }, /* 02 (x480) */
+ { {0x28, 0xD4, 0x39, 0x86, 0x57, 0x29, 0x81} }, /* 03 (x600) */
+ { {0x28, 0xD4, 0x8D, 0x9A, 0xFF, 0x29, 0xA1} }, /* 04 (x768) */
+ { {0x28, 0x5A, 0x0D, 0x9A, 0xFF, 0x29, 0xA9} }, /* 05 (x1024) */
+ { {0x28, 0x10, 0x1A, 0x87, 0x19, 0x29, 0x8F} } /* 06 (x1050) */
};
-static struct XGI_LVDSCRT1VDataStruct XGI_LVDSCRT11600x1200_1_V[] =
-{
- /* CR06,CR07,CR10,CR11,CR15,CR16,SR0A+CR09(5->7) */
- {{ 0xd4,0x1F,0x81,0x84,0x5D,0xd5,0x10 }}, /* 00 (x350) */
- {{ 0x06,0x3e,0xb3,0x86,0x8F,0x07,0x20 }}, /* 01 (x400) */
- {{ 0x56,0xba,0x03,0x86,0xDF,0x57,0x00 }}, /* 02 (x480) */
- {{ 0xce,0xF0,0x7b,0x8e,0x57,0xcf,0xa0 }}, /* 03 (x600) */
- {{ 0x76,0xF5,0x23,0x86,0xFF,0x77,0x90 }}, /* 04 (x768) */
- {{ 0x76,0x5A,0x23,0x86,0xFF,0x77,0x89 }}, /* 05 (x1024) */
- {{ 0x90,0x10,0x1A,0x8E,0x19,0x91,0x2F }}, /* 06 (x1050) */
- {{ 0x26,0x11,0xd3,0x86,0xaF,0x27,0x3f }} /* 07 (x1200) */
+/* CR06,CR07,CR10,CR11,CR15,CR16,SR0A+CR09(5->7) */
+static struct XGI_LVDSCRT1VDataStruct XGI_LVDSCRT11600x1200_1_V[] = {
+ { {0xd4, 0x1F, 0x81, 0x84, 0x5D, 0xd5, 0x10} }, /* 00 (x350) */
+ { {0x06, 0x3e, 0xb3, 0x86, 0x8F, 0x07, 0x20} }, /* 01 (x400) */
+ { {0x56, 0xba, 0x03, 0x86, 0xDF, 0x57, 0x00} }, /* 02 (x480) */
+ { {0xce, 0xF0, 0x7b, 0x8e, 0x57, 0xcf, 0xa0} }, /* 03 (x600) */
+ { {0x76, 0xF5, 0x23, 0x86, 0xFF, 0x77, 0x90} }, /* 04 (x768) */
+ { {0x76, 0x5A, 0x23, 0x86, 0xFF, 0x77, 0x89} }, /* 05 (x1024) */
+ { {0x90, 0x10, 0x1A, 0x8E, 0x19, 0x91, 0x2F} }, /* 06 (x1050) */
+ { {0x26, 0x11, 0xd3, 0x86, 0xaF, 0x27, 0x3f} } /* 07 (x1200) */
};
-static struct XGI_LVDSCRT1HDataStruct XGI_LVDSCRT11024x768_1_Hx75[] =
-{ /* CR00,CR02,CR03,CR04,CR05,SR0B,SR0C,SR0E */
- {{ 0x4B,0x27,0x8F,0x32,0x1B,0x00,0x45,0x00 }},/* ; 00 (320x) */
- {{ 0x4B,0x27,0x8F,0x2B,0x03,0x00,0x44,0x00 }},/* ; 01 (360x) */
- {{ 0x55,0x31,0x99,0x46,0x1D,0x00,0x55,0x00 }},/* ; 02 (400x) */
- {{ 0x63,0x3F,0x87,0x4A,0x93,0x00,0x01,0x00 }},/* ; 03 (512x) */
- {{ 0x6F,0x4F,0x93,0x54,0x80,0x00,0x05,0x00 }},/* ; 04 (640x) */
- {{ 0x6F,0x4F,0x93,0x54,0x80,0x00,0x05,0x00 }},/* ; 05 (720x) */
- {{ 0x83,0x63,0x87,0x68,0x14,0x00,0x26,0x00 }},/* ; 06 (800x) */
- {{ 0x9F,0x7F,0x83,0x85,0x91,0x00,0x02,0x00 }} /* ; 07 (1024x) */
+/* CR00,CR02,CR03,CR04,CR05,SR0B,SR0C,SR0E */
+static struct XGI_LVDSCRT1HDataStruct XGI_LVDSCRT11024x768_1_Hx75[] = {
+ { {0x4B, 0x27, 0x8F, 0x32, 0x1B, 0x00, 0x45, 0x00} },/* ; 00 (320x) */
+ { {0x4B, 0x27, 0x8F, 0x2B, 0x03, 0x00, 0x44, 0x00} },/* ; 01 (360x) */
+ { {0x55, 0x31, 0x99, 0x46, 0x1D, 0x00, 0x55, 0x00} },/* ; 02 (400x) */
+ { {0x63, 0x3F, 0x87, 0x4A, 0x93, 0x00, 0x01, 0x00} },/* ; 03 (512x) */
+ { {0x6F, 0x4F, 0x93, 0x54, 0x80, 0x00, 0x05, 0x00} },/* ; 04 (640x) */
+ { {0x6F, 0x4F, 0x93, 0x54, 0x80, 0x00, 0x05, 0x00} },/* ; 05 (720x) */
+ { {0x83, 0x63, 0x87, 0x68, 0x14, 0x00, 0x26, 0x00} },/* ; 06 (800x) */
+ { {0x9F, 0x7F, 0x83, 0x85, 0x91, 0x00, 0x02, 0x00} } /* ; 07 (1024x) */
};
-static struct XGI_LVDSCRT1VDataStruct XGI_LVDSCRT11024x768_1_Vx75[] =
-{ /* CR06,CR07,CR10,CR11,CR15,CR16,SR0A+CR09(5->7) */
- {{ 0x97,0x1F,0x60,0x87,0x5D,0x83,0x10 }},/* ; 00 (x350) */
- {{ 0xB4,0x1F,0x92,0x89,0x8F,0xB5,0x30 }},/* ; 01 (x400) */
- {{ 0xFE,0x1F,0xE0,0x84,0xDF,0xFF,0x10 }},/* ; 02 (x480) */
- {{ 0x76,0xF0,0x58,0x8C,0x57,0x77,0xA0 }},/* ; 03 (x600) */
- {{ 0x1E,0xF5,0x00,0x83,0xFF,0x1F,0x90 }} /* ; 04 (x768) */
+/* CR06,CR07,CR10,CR11,CR15,CR16,SR0A+CR09(5->7) */
+static struct XGI_LVDSCRT1VDataStruct XGI_LVDSCRT11024x768_1_Vx75[] = {
+ { {0x97, 0x1F, 0x60, 0x87, 0x5D, 0x83, 0x10} },/* ; 00 (x350) */
+ { {0xB4, 0x1F, 0x92, 0x89, 0x8F, 0xB5, 0x30} },/* ; 01 (x400) */
+ { {0xFE, 0x1F, 0xE0, 0x84, 0xDF, 0xFF, 0x10} },/* ; 02 (x480) */
+ { {0x76, 0xF0, 0x58, 0x8C, 0x57, 0x77, 0xA0} },/* ; 03 (x600) */
+ { {0x1E, 0xF5, 0x00, 0x83, 0xFF, 0x1F, 0x90} } /* ; 04 (x768) */
};
-static struct XGI_LVDSCRT1HDataStruct XGI_LVDSCRT11024x768_2_Hx75[] =
-{ /* CR00,CR02,CR03,CR04,CR05,SR0B,SR0C,SR0E */
- {{ 0x63,0x27,0x87,0x3B,0x8C,0x00,0x01,0x00 }},/* ; 00 (320x) */
- {{ 0x63,0x27,0x87,0x3B,0x8C,0x00,0x01,0x00 }},/* ; 01 (360x) */
- {{ 0x63,0x31,0x87,0x3D,0x8E,0x00,0x01,0x00 }},/* ; 02 (400x) */
- {{ 0x63,0x3F,0x87,0x45,0x96,0x00,0x01,0x00 }},/* ; 03 (512x) */
- {{ 0xA3,0x4F,0x87,0x6E,0x9F,0x00,0x06,0x00 }},/* ; 04 (640x) */
- {{ 0xA3,0x4F,0x87,0x6E,0x9F,0x00,0x06,0x00 }},/* ; 05 (720x) */
- {{ 0xA3,0x63,0x87,0x78,0x89,0x00,0x02,0x00 }},/* ; 06 (800x) */
- {{ 0xA3,0x7F,0x87,0x86,0x97,0x00,0x02,0x00 }} /* ; 07 (1024x) */
+/* CR00,CR02,CR03,CR04,CR05,SR0B,SR0C,SR0E */
+static struct XGI_LVDSCRT1HDataStruct XGI_LVDSCRT11024x768_2_Hx75[] = {
+ { {0x63, 0x27, 0x87, 0x3B, 0x8C, 0x00, 0x01, 0x00} },/* ; 00 (320x) */
+ { {0x63, 0x27, 0x87, 0x3B, 0x8C, 0x00, 0x01, 0x00} },/* ; 01 (360x) */
+ { {0x63, 0x31, 0x87, 0x3D, 0x8E, 0x00, 0x01, 0x00} },/* ; 02 (400x) */
+ { {0x63, 0x3F, 0x87, 0x45, 0x96, 0x00, 0x01, 0x00} },/* ; 03 (512x) */
+ { {0xA3, 0x4F, 0x87, 0x6E, 0x9F, 0x00, 0x06, 0x00} },/* ; 04 (640x) */
+ { {0xA3, 0x4F, 0x87, 0x6E, 0x9F, 0x00, 0x06, 0x00} },/* ; 05 (720x) */
+ { {0xA3, 0x63, 0x87, 0x78, 0x89, 0x00, 0x02, 0x00} },/* ; 06 (800x) */
+ { {0xA3, 0x7F, 0x87, 0x86, 0x97, 0x00, 0x02, 0x00} } /* ; 07 (1024x) */
};
-static struct XGI_LVDSCRT1VDataStruct XGI_LVDSCRT11024x768_2_Vx75[] =
-{ /* CR06,CR07,CR10,CR11,CR15,CR16,SR0A */
- {{ 0x24,0xBB,0x31,0x87,0x5D,0x25,0x30 }},/* ; 00 (x350) */
- {{ 0x24,0xBB,0x4A,0x80,0x8F,0x25,0x30 }},/* ; 01 (x400) */
- {{ 0x24,0xBB,0x72,0x88,0xDF,0x25,0x30 }},/* ; 02 (x480) */
- {{ 0x24,0xF1,0xAE,0x84,0x57,0x25,0xB0 }},/* ; 03 (x600) */
- {{ 0x24,0xF5,0x02,0x88,0xFF,0x25,0x90 }} /* ; 04 (x768) */
+/* CR06,CR07,CR10,CR11,CR15,CR16,SR0A */
+static struct XGI_LVDSCRT1VDataStruct XGI_LVDSCRT11024x768_2_Vx75[] = {
+ { {0x24, 0xBB, 0x31, 0x87, 0x5D, 0x25, 0x30} },/* ; 00 (x350) */
+ { {0x24, 0xBB, 0x4A, 0x80, 0x8F, 0x25, 0x30} },/* ; 01 (x400) */
+ { {0x24, 0xBB, 0x72, 0x88, 0xDF, 0x25, 0x30} },/* ; 02 (x480) */
+ { {0x24, 0xF1, 0xAE, 0x84, 0x57, 0x25, 0xB0} },/* ; 03 (x600) */
+ { {0x24, 0xF5, 0x02, 0x88, 0xFF, 0x25, 0x90} } /* ; 04 (x768) */
};
-static struct XGI_LVDSCRT1HDataStruct XGI_LVDSCRT11280x1024_1_Hx75[] =
-{ /* CR00,CR02,CR03,CR04,CR05,SR0B,SR0C,SR0E */
- {{ 0x56,0x27,0x9A,0x30,0x1E,0x00,0x05,0x00 }},/* ; 00 (320x) */
- {{ 0x56,0x27,0x9A,0x30,0x1E,0x00,0x05,0x00 }},/* ; 01 (360x) */
- {{ 0x60,0x31,0x84,0x3A,0x88,0x00,0x01,0x00 }},/* ; 02 (400x) */
- {{ 0x6E,0x3F,0x92,0x48,0x96,0x00,0x01,0x00 }},/* ; 03 (512x) */
- {{ 0x7E,0x4F,0x82,0x54,0x06,0x00,0x06,0x00 }},/* ; 04 (640x) */
- {{ 0x7E,0x4F,0x82,0x54,0x06,0x00,0x06,0x00 }},/* ; 05 (720x) */
- {{ 0x92,0x63,0x96,0x68,0x1A,0x00,0x06,0x00 }},/* ; 06 (800x) */
- {{ 0xAE,0x7F,0x92,0x84,0x96,0x00,0x02,0x00 }},/* ; 07 (1024x) */
- {{ 0xCE,0x9F,0x92,0xA5,0x17,0x00,0x07,0x00 }} /* ; 08 (1280x) */
+/* CR00,CR02,CR03,CR04,CR05,SR0B,SR0C,SR0E */
+static struct XGI_LVDSCRT1HDataStruct XGI_LVDSCRT11280x1024_1_Hx75[] = {
+ { {0x56, 0x27, 0x9A, 0x30, 0x1E, 0x00, 0x05, 0x00} },/* ; 00 (320x) */
+ { {0x56, 0x27, 0x9A, 0x30, 0x1E, 0x00, 0x05, 0x00} },/* ; 01 (360x) */
+ { {0x60, 0x31, 0x84, 0x3A, 0x88, 0x00, 0x01, 0x00} },/* ; 02 (400x) */
+ { {0x6E, 0x3F, 0x92, 0x48, 0x96, 0x00, 0x01, 0x00} },/* ; 03 (512x) */
+ { {0x7E, 0x4F, 0x82, 0x54, 0x06, 0x00, 0x06, 0x00} },/* ; 04 (640x) */
+ { {0x7E, 0x4F, 0x82, 0x54, 0x06, 0x00, 0x06, 0x00} },/* ; 05 (720x) */
+ { {0x92, 0x63, 0x96, 0x68, 0x1A, 0x00, 0x06, 0x00} },/* ; 06 (800x) */
+ { {0xAE, 0x7F, 0x92, 0x84, 0x96, 0x00, 0x02, 0x00} },/* ; 07 (1024x) */
+ { {0xCE, 0x9F, 0x92, 0xA5, 0x17, 0x00, 0x07, 0x00} } /* ; 08 (1280x) */
};
-static struct XGI_LVDSCRT1VDataStruct XGI_LVDSCRT11280x1024_1_Vx75[] =
-{ /* CR06,CR07,CR10,CR11,CR15,CR16,SR0A */
- {{ 0x86,0xD1,0xBC,0x80,0xBB,0xE5,0x00 }},/* ; 00 (x350) */
- {{ 0xB8,0x1F,0x90,0x84,0x8F,0xB9,0x30 }},/* ; 01 (x400) */
- {{ 0x08,0x3E,0xE0,0x84,0xDF,0x09,0x00 }},/* ; 02 (x480) */
- {{ 0x80,0xF0,0x58,0x8C,0x57,0x81,0xA0 }},/* ; 03 (x600) */
- {{ 0x28,0xF5,0x00,0x84,0xFF,0x29,0x90 }},/* ; 04 (x768) */
- {{ 0x28,0x5A,0x13,0x87,0xFF,0x29,0xA9 }} /* ; 05 (x1024) */
+/* CR06,CR07,CR10,CR11,CR15,CR16,SR0A */
+static struct XGI_LVDSCRT1VDataStruct XGI_LVDSCRT11280x1024_1_Vx75[] = {
+ { {0x86, 0xD1, 0xBC, 0x80, 0xBB, 0xE5, 0x00} },/* ; 00 (x350) */
+ { {0xB8, 0x1F, 0x90, 0x84, 0x8F, 0xB9, 0x30} },/* ; 01 (x400) */
+ { {0x08, 0x3E, 0xE0, 0x84, 0xDF, 0x09, 0x00} },/* ; 02 (x480) */
+ { {0x80, 0xF0, 0x58, 0x8C, 0x57, 0x81, 0xA0} },/* ; 03 (x600) */
+ { {0x28, 0xF5, 0x00, 0x84, 0xFF, 0x29, 0x90} },/* ; 04 (x768) */
+ { {0x28, 0x5A, 0x13, 0x87, 0xFF, 0x29, 0xA9} } /* ; 05 (x1024) */
+};
+/* CR00,CR02,CR03,CR04,CR05,SR0B,SR0C,SR0E */
+static struct XGI_LVDSCRT1HDataStruct XGI_LVDSCRT11280x1024_2_Hx75[] = {
+ { {0x7E, 0x3B, 0x9A, 0x44, 0x12, 0x00, 0x01, 0x00} },/* ; 00 (320x) */
+ { {0x7E, 0x3B, 0x9A, 0x44, 0x12, 0x00, 0x01, 0x00} },/* ; 01 (360x) */
+ { {0x7E, 0x40, 0x84, 0x49, 0x91, 0x00, 0x01, 0x00} },/* ; 02 (400x) */
+ { {0x7E, 0x47, 0x93, 0x50, 0x9E, 0x00, 0x01, 0x00} },/* ; 03 (512x) */
+ { {0xCE, 0x77, 0x8A, 0x80, 0x8E, 0x00, 0x02, 0x00} },/* ; 04 (640x) */
+ { {0xCE, 0x77, 0x8A, 0x80, 0x8E, 0x00, 0x02, 0x00} },/* ; 05 (720x) */
+ { {0xCE, 0x81, 0x94, 0x8A, 0x98, 0x00, 0x02, 0x00} },/* ; 06 (800x) */
+ { {0xCE, 0x8F, 0x82, 0x98, 0x06, 0x00, 0x07, 0x00} },/* ; 07 (1024x) */
+ { {0xCE, 0x9F, 0x92, 0xA8, 0x16, 0x00, 0x07, 0x00} } /* ; 08 (1280x) */
};
-static struct XGI_LVDSCRT1HDataStruct XGI_LVDSCRT11280x1024_2_Hx75[] =
-{
- /* CR00,CR02,CR03,CR04,CR05,SR0B,SR0C,SR0E */
- {{ 0x7E,0x3B,0x9A,0x44,0x12,0x00,0x01,0x00 }},/* ; 00 (320x) */
- {{ 0x7E,0x3B,0x9A,0x44,0x12,0x00,0x01,0x00 }},/* ; 01 (360x) */
- {{ 0x7E,0x40,0x84,0x49,0x91,0x00,0x01,0x00 }},/* ; 02 (400x) */
- {{ 0x7E,0x47,0x93,0x50,0x9E,0x00,0x01,0x00 }},/* ; 03 (512x) */
- {{ 0xCE,0x77,0x8A,0x80,0x8E,0x00,0x02,0x00 }},/* ; 04 (640x) */
- {{ 0xCE,0x77,0x8A,0x80,0x8E,0x00,0x02,0x00 }},/* ; 05 (720x) */
- {{ 0xCE,0x81,0x94,0x8A,0x98,0x00,0x02,0x00 }},/* ; 06 (800x) */
- {{ 0xCE,0x8F,0x82,0x98,0x06,0x00,0x07,0x00 }},/* ; 07 (1024x) */
- {{ 0xCE,0x9F,0x92,0xA8,0x16,0x00,0x07,0x00 }} /* ; 08 (1280x) */
-};
-
-static struct XGI_LVDSCRT1VDataStruct XGI_LVDSCRT11280x1024_2_Vx75[] =
-{
- /* CR06,CR07,CR10,CR11,CR15,CR16,SR0A */
- {{ 0x28,0xD2,0xAF,0x83,0xAE,0xD8,0xA1 }},/* ; 00 (x350) */
- {{ 0x28,0xD2,0xC8,0x8C,0xC7,0xF2,0x81 }},/* ; 01 (x400) */
- {{ 0x28,0xD2,0xF0,0x84,0xEF,0x1A,0xB1 }},/* ; 02 (x480) */
- {{ 0x28,0xDE,0x2C,0x8F,0x2B,0x56,0x91 }},/* ; 03 (x600) */
- {{ 0x28,0xDE,0x80,0x83,0x7F,0xAA,0x91 }},/* ; 04 (x768) */
- {{ 0x28,0x5A,0x13,0x87,0xFF,0x29,0xA9 }} /* ; 05 (x1024) */
+/* CR06,CR07,CR10,CR11,CR15,CR16,SR0A */
+static struct XGI_LVDSCRT1VDataStruct XGI_LVDSCRT11280x1024_2_Vx75[] = {
+ { {0x28, 0xD2, 0xAF, 0x83, 0xAE, 0xD8, 0xA1} },/* ; 00 (x350) */
+ { {0x28, 0xD2, 0xC8, 0x8C, 0xC7, 0xF2, 0x81} },/* ; 01 (x400) */
+ { {0x28, 0xD2, 0xF0, 0x84, 0xEF, 0x1A, 0xB1} },/* ; 02 (x480) */
+ { {0x28, 0xDE, 0x2C, 0x8F, 0x2B, 0x56, 0x91} },/* ; 03 (x600) */
+ { {0x28, 0xDE, 0x80, 0x83, 0x7F, 0xAA, 0x91} },/* ; 04 (x768) */
+ { {0x28, 0x5A, 0x13, 0x87, 0xFF, 0x29, 0xA9} } /* ; 05 (x1024) */
};
#if 0
-static struct XGI_LVDSCRT1DataStruct XGI_CHTVCRT1UNTSC[] =
-{
- {{0x64,0x4f,0x88,0x56,0x9f,0x56,0x3e,
- 0xe8,0x84,0x8f,0x57,0x20,0x00,0x01,0x00 }},
- {{0x64,0x4f,0x88,0x56,0x9f,0x56,0x3e,
- 0xd0,0x82,0x5d,0x57,0x00,0x00,0x01,0x00 }},
- {{0x64,0x4f,0x88,0x56,0x9f,0x56,0x3e,
- 0xe8,0x84,0x8f,0x57,0x20,0x00,0x01,0x00 }},
- {{0x64,0x4f,0x88,0x56,0x9f,0x56,0x3e,
- 0xd0,0x82,0x5d,0x57,0x00,0x00,0x01,0x00 }},
- {{0x5d,0x4f,0x81,0x53,0x9c,0x56,0xba,
- 0x18,0x84,0xdf,0x57,0x00,0x00,0x01,0x00 }},
- {{0x80,0x63,0x84,0x6c,0x17,0xec,0xf0,
- 0x90,0x8c,0x57,0xed,0x20,0x00,0x06,0x01 }}
+static struct XGI_LVDSCRT1DataStruct XGI_CHTVCRT1UNTSC[] = {
+ { {0x64, 0x4f, 0x88, 0x56, 0x9f, 0x56, 0x3e,
+ 0xe8, 0x84, 0x8f, 0x57, 0x20, 0x00, 0x01, 0x00 } },
+ { {0x64, 0x4f, 0x88, 0x56, 0x9f, 0x56, 0x3e,
+ 0xd0, 0x82, 0x5d, 0x57, 0x00, 0x00, 0x01, 0x00 } },
+ { {0x64, 0x4f, 0x88, 0x56, 0x9f, 0x56, 0x3e,
+ 0xe8, 0x84, 0x8f, 0x57, 0x20, 0x00, 0x01, 0x00 } },
+ { {0x64, 0x4f, 0x88, 0x56, 0x9f, 0x56, 0x3e,
+ 0xd0, 0x82, 0x5d, 0x57, 0x00, 0x00, 0x01, 0x00 } },
+ { {0x5d, 0x4f, 0x81, 0x53, 0x9c, 0x56, 0xba,
+ 0x18, 0x84, 0xdf, 0x57, 0x00, 0x00, 0x01, 0x00 } },
+ { {0x80, 0x63, 0x84, 0x6c, 0x17, 0xec, 0xf0,
+ x90, 0x8c, 0x57, 0xed, 0x20, 0x00, 0x06, 0x01 } }
};
-static struct XGI_LVDSCRT1DataStruct XGI_CHTVCRT1ONTSC[] =
-{
- {{0x64,0x4f,0x88,0x5a,0x9f,0x0b,0x3e,
- 0xc0,0x84,0x8f,0x0c,0x20,0x00,0x01,0x00 }},
- {{0x64,0x4f,0x88,0x5a,0x9f,0x0b,0x3e,
- 0xb0,0x8d,0x5d,0x0c,0x00,0x00,0x01,0x00 }},
- {{0x64,0x4f,0x88,0x5a,0x9f,0x0b,0x3e,
- 0xc0,0x84,0x8f,0x0c,0x20,0x00,0x01,0x00 }},
- {{0x64,0x4f,0x88,0x5a,0x9f,0x0b,0x3e,
- 0xb0,0x8d,0x5d,0x0c,0x00,0x00,0x01,0x00 }},
- {{0x5d,0x4f,0x81,0x56,0x9c,0x0b,0x3e,
- 0xe8,0x84,0xdf,0x0c,0x00,0x00,0x01,0x00 }},
- {{0x7d,0x63,0x81,0x6a,0x16,0xba,0xf0,
- 0x7f,0x86,0x57,0xbb,0x00,0x00,0x06,0x01 }}
+static struct XGI_LVDSCRT1DataStruct XGI_CHTVCRT1ONTSC[] = {
+ { {0x64, 0x4f, 0x88, 0x5a, 0x9f, 0x0b, 0x3e,
+ 0xc0, 0x84, 0x8f, 0x0c, 0x20, 0x00, 0x01, 0x00 } },
+ { {0x64, 0x4f, 0x88, 0x5a, 0x9f, 0x0b, 0x3e,
+ 0xb0, 0x8d, 0x5d, 0x0c, 0x00, 0x00, 0x01, 0x00 } },
+ { {0x64, 0x4f, 0x88, 0x5a, 0x9f, 0x0b, 0x3e,
+ 0xc0, 0x84, 0x8f, 0x0c, 0x20, 0x00, 0x01, 0x00 } },
+ { {0x64, 0x4f, 0x88, 0x5a, 0x9f, 0x0b, 0x3e,
+ 0xb0, 0x8d, 0x5d, 0x0c, 0x00, 0x00, 0x01, 0x00 } },
+ { {0x5d, 0x4f, 0x81, 0x56, 0x9c, 0x0b, 0x3e,
+ 0xe8, 0x84, 0xdf, 0x0c, 0x00, 0x00, 0x01, 0x00 } },
+ { {0x7d, 0x63, 0x81, 0x6a, 0x16, 0xba, 0xf0,
+ x7f, 0x86, 0x57, 0xbb, 0x00, 0x00, 0x06, 0x01 } }
};
-static struct XGI_LVDSCRT1DataStruct XGI_CHTVCRT1UPAL[] =
-{
- {{0x79,0x4f,0x9d,0x5a,0x90,0x6f,0x3e,
- 0xf8,0x83,0x8f,0x70,0x20,0x00,0x05,0x00 }},
- {{0x79,0x4f,0x9d,0x5a,0x90,0x6f,0x3e,
- 0xde,0x81,0x5d,0x70,0x00,0x00,0x05,0x00 }},
- {{0x79,0x4f,0x9d,0x5a,0x90,0x6f,0x3e,
- 0xf8,0x83,0x8f,0x70,0x20,0x00,0x05,0x00 }},
- {{0x79,0x4f,0x9d,0x5a,0x90,0x6f,0x3e,
- 0xde,0x81,0x5d,0x70,0x00,0x00,0x05,0x00 }},
- {{0x64,0x4f,0x88,0x55,0x80,0xec,0xba,
- 0x50,0x84,0xdf,0xed,0x00,0x00,0x05,0x00 }},
- {{0x70,0x63,0x94,0x68,0x8d,0x42,0xf1,
- 0xc8,0x8c,0x57,0xe9,0x20,0x00,0x05,0x01 }}
+static struct XGI_LVDSCRT1DataStruct XGI_CHTVCRT1UPAL[] = {
+ { {0x79, 0x4f, 0x9d, 0x5a, 0x90, 0x6f, 0x3e,
+ 0xf8, 0x83, 0x8f, 0x70, 0x20, 0x00, 0x05, 0x00 } },
+ { {0x79, 0x4f, 0x9d, 0x5a, 0x90, 0x6f, 0x3e,
+ 0xde, 0x81, 0x5d, 0x70, 0x00, 0x00, 0x05, 0x00 } },
+ { {0x79, 0x4f, 0x9d, 0x5a, 0x90, 0x6f, 0x3e,
+ 0xf8, 0x83, 0x8f, 0x70, 0x20, 0x00, 0x05, 0x00 } },
+ { {0x79, 0x4f, 0x9d, 0x5a, 0x90, 0x6f, 0x3e,
+ 0xde, 0x81, 0x5d, 0x70, 0x00, 0x00, 0x05, 0x00 } },
+ { {0x64, 0x4f, 0x88, 0x55, 0x80, 0xec, 0xba,
+ 0x50, 0x84, 0xdf, 0xed, 0x00, 0x00, 0x05, 0x00 } },
+ { {0x70, 0x63, 0x94, 0x68, 0x8d, 0x42, 0xf1,
+ xc8, 0x8c, 0x57, 0xe9, 0x20, 0x00, 0x05, 0x01 } }
};
-static struct XGI_LVDSCRT1DataStruct XGI_CHTVCRT1OPAL[] =
-{
- {{0x79,0x4f,0x9d,0x5a,0x90,0x6f,0x3e,
- 0xf0,0x83,0x8f,0x70,0x20,0x00,0x05,0x00 }},
- {{0x79,0x4f,0x9d,0x5a,0x90,0x6f,0x3e,
- 0xde,0x81,0x5d,0x70,0x00,0x00,0x05,0x00 }},
- {{0x79,0x4f,0x9d,0x5a,0x90,0x6f,0x3e,
- 0xf0,0x83,0x8f,0x70,0x20,0x00,0x05,0x00 }},
- {{0x79,0x4f,0x9d,0x5a,0x90,0x6f,0x3e,
- 0xde,0x81,0x5d,0x70,0x00,0x00,0x05,0x00 }},
- {{0x64,0x4f,0x88,0x55,0x80,0x6f,0xba,
- 0x20,0x83,0xdf,0x70,0x00,0x00,0x05,0x00 }},
- {{0x73,0x63,0x97,0x69,0x8e,0xec,0xf0,
- 0x90,0x8c,0x57,0xed,0x20,0x00,0x05,0x01 }}
+static struct XGI_LVDSCRT1DataStruct XGI_CHTVCRT1OPAL[] = {
+ { {0x79, 0x4f, 0x9d, 0x5a, 0x90, 0x6f, 0x3e,
+ 0xf0, 0x83, 0x8f, 0x70, 0x20, 0x00, 0x05, 0x00 } },
+ { {0x79, 0x4f, 0x9d, 0x5a, 0x90, 0x6f, 0x3e,
+ 0xde, 0x81, 0x5d, 0x70, 0x00, 0x00, 0x05, 0x00 } },
+ { {0x79, 0x4f, 0x9d, 0x5a, 0x90, 0x6f, 0x3e,
+ 0xf0, 0x83, 0x8f, 0x70, 0x20, 0x00, 0x05, 0x00 } },
+ { {0x79, 0x4f, 0x9d, 0x5a, 0x90, 0x6f, 0x3e,
+ 0xde, 0x81, 0x5d, 0x70, 0x00, 0x00, 0x05, 0x00 } },
+ { {0x64, 0x4f, 0x88, 0x55, 0x80, 0x6f, 0xba,
+ 0x20, 0x83, 0xdf, 0x70, 0x00, 0x00, 0x05, 0x00 } },
+ { {0x73, 0x63, 0x97, 0x69, 0x8e, 0xec, 0xf0,
+ x90, 0x8c, 0x57, 0xed, 0x20, 0x00, 0x05, 0x01 } }
};
#endif
/*add for new UNIVGABIOS*/
-static struct XGI330_LCDDataTablStruct XGI_LCDDataTable[] =
-{
- {Panel1024x768,0x0019,0x0001,0}, /* XGI_ExtLCD1024x768Data */
- {Panel1024x768,0x0019,0x0000,1}, /* XGI_StLCD1024x768Data */
- {Panel1024x768,0x0018,0x0010,2}, /* XGI_CetLCD1024x768Data */
- {Panel1280x1024,0x0019,0x0001,3}, /* XGI_ExtLCD1280x1024Data */
- {Panel1280x1024,0x0019,0x0000,4}, /* XGI_StLCD1280x1024Data */
- {Panel1280x1024,0x0018,0x0010,5}, /* XGI_CetLCD1280x1024Data */
- {Panel1400x1050,0x0019,0x0001,6}, /* XGI_ExtLCD1400x1050Data */
- {Panel1400x1050,0x0019,0x0000,7}, /* XGI_StLCD1400x1050Data */
- {Panel1400x1050,0x0018,0x0010,8}, /* XGI_CetLCD1400x1050Data */
- {Panel1600x1200,0x0019,0x0001,9}, /* XGI_ExtLCD1600x1200Data */
- {Panel1600x1200,0x0019,0x0000,10}, /* XGI_StLCD1600x1200Data */
- {PanelRef60Hz,0x0008,0x0008,11}, /* XGI_NoScalingData */
- {Panel1024x768x75,0x0019,0x0001,12}, /* XGI_ExtLCD1024x768x75Data */
- {Panel1024x768x75,0x0019,0x0000,13}, /* XGI_StLCD1024x768x75Data */
- {Panel1024x768x75,0x0018,0x0010,14}, /* XGI_CetLCD1024x768x75Data */
- {Panel1280x1024x75,0x0019,0x0001,15}, /* XGI_ExtLCD1280x1024x75Data */
- {Panel1280x1024x75,0x0019,0x0000,16}, /* XGI_StLCD1280x1024x75Data */
- {Panel1280x1024x75,0x0018,0x0010,17}, /* XGI_CetLCD1280x1024x75Data */
- {PanelRef75Hz,0x0008,0x0008,18}, /* XGI_NoScalingDatax75 */
- {0xFF,0x0000,0x0000,0} /* End of table */
+static struct XGI330_LCDDataTablStruct XGI_LCDDataTable[] = {
+ {Panel1024x768, 0x0019, 0x0001, 0}, /* XGI_ExtLCD1024x768Data */
+ {Panel1024x768, 0x0019, 0x0000, 1}, /* XGI_StLCD1024x768Data */
+ {Panel1024x768, 0x0018, 0x0010, 2}, /* XGI_CetLCD1024x768Data */
+ {Panel1280x1024, 0x0019, 0x0001, 3}, /* XGI_ExtLCD1280x1024Data */
+ {Panel1280x1024, 0x0019, 0x0000, 4}, /* XGI_StLCD1280x1024Data */
+ {Panel1280x1024, 0x0018, 0x0010, 5}, /* XGI_CetLCD1280x1024Data */
+ {Panel1400x1050, 0x0019, 0x0001, 6}, /* XGI_ExtLCD1400x1050Data */
+ {Panel1400x1050, 0x0019, 0x0000, 7}, /* XGI_StLCD1400x1050Data */
+ {Panel1400x1050, 0x0018, 0x0010, 8}, /* XGI_CetLCD1400x1050Data */
+ {Panel1600x1200, 0x0019, 0x0001, 9}, /* XGI_ExtLCD1600x1200Data */
+ {Panel1600x1200, 0x0019, 0x0000, 10}, /* XGI_StLCD1600x1200Data */
+ {PanelRef60Hz, 0x0008, 0x0008, 11}, /* XGI_NoScalingData */
+ {Panel1024x768x75, 0x0019, 0x0001, 12}, /* XGI_ExtLCD1024x768x75Data */
+ {Panel1024x768x75, 0x0019, 0x0000, 13}, /* XGI_StLCD1024x768x75Data */
+ {Panel1024x768x75, 0x0018, 0x0010, 14}, /* XGI_CetLCD1024x768x75Data */
+ {Panel1280x1024x75, 0x0019, 0x0001, 15}, /* XGI_ExtLCD1280x1024x75Data*/
+ {Panel1280x1024x75, 0x0019, 0x0000, 16}, /* XGI_StLCD1280x1024x75Data */
+ {Panel1280x1024x75, 0x0018, 0x0010, 17}, /* XGI_CetLCD1280x1024x75Data*/
+ {PanelRef75Hz, 0x0008, 0x0008, 18}, /* XGI_NoScalingDatax75 */
+ {0xFF, 0x0000, 0x0000, 0} /* End of table */
};
-static struct XGI330_LCDDataTablStruct XGI_LCDDesDataTable[] =
-{
- {Panel1024x768,0x0019,0x0001,0}, /* XGI_ExtLCDDes1024x768Data */
- {Panel1024x768,0x0019,0x0000,1}, /* XGI_StLCDDes1024x768Data */
- {Panel1024x768,0x0018,0x0010,2}, /* XGI_CetLCDDes1024x768Data */
- {Panel1280x1024,0x0019,0x0001,3}, /* XGI_ExtLCDDes1280x1024Data */
- {Panel1280x1024,0x0019,0x0000,4}, /* XGI_StLCDDes1280x1024Data */
- {Panel1280x1024,0x0018,0x0010,5}, /* XGI_CetLCDDes1280x1024Data */
- {Panel1400x1050,0x0019,0x0001,6}, /* XGI_ExtLCDDes1400x1050Data */
- {Panel1400x1050,0x0019,0x0000,7}, /* XGI_StLCDDes1400x1050Data */
- {Panel1400x1050,0x0418,0x0010,8}, /* XGI_CetLCDDes1400x1050Data */
- {Panel1400x1050,0x0418,0x0410,9}, /* XGI_CetLCDDes1400x1050Data2 */
- {Panel1600x1200,0x0019,0x0001,10}, /* XGI_ExtLCDDes1600x1200Data */
- {Panel1600x1200,0x0019,0x0000,11}, /* XGI_StLCDDes1600x1200Data */
- {PanelRef60Hz,0x0008,0x0008,12}, /* XGI_NoScalingDesData */
- {Panel1024x768x75,0x0019,0x0001,13}, /* XGI_ExtLCDDes1024x768x75Data */
- {Panel1024x768x75,0x0019,0x0000,14}, /* XGI_StLCDDes1024x768x75Data */
- {Panel1024x768x75,0x0018,0x0010,15}, /* XGI_CetLCDDes1024x768x75Data */
- {Panel1280x1024x75,0x0019,0x0001,16}, /* XGI_ExtLCDDes1280x1024x75Data */
- {Panel1280x1024x75,0x0019,0x0000,17}, /* XGI_StLCDDes1280x1024x75Data */
- {Panel1280x1024x75,0x0018,0x0010,18}, /* XGI_CetLCDDes1280x1024x75Data */
- {PanelRef75Hz,0x0008,0x0008,19}, /* XGI_NoScalingDesDatax75 */
- {0xFF,0x0000,0x0000,0}
+static struct XGI330_LCDDataTablStruct XGI_LCDDesDataTable[] = {
+ {Panel1024x768, 0x0019, 0x0001, 0}, /* XGI_ExtLCDDes1024x768Data */
+ {Panel1024x768, 0x0019, 0x0000, 1}, /* XGI_StLCDDes1024x768Data */
+ {Panel1024x768, 0x0018, 0x0010, 2}, /* XGI_CetLCDDes1024x768Data */
+ {Panel1280x1024, 0x0019, 0x0001, 3}, /* XGI_ExtLCDDes1280x1024Data */
+ {Panel1280x1024, 0x0019, 0x0000, 4}, /* XGI_StLCDDes1280x1024Data */
+ {Panel1280x1024, 0x0018, 0x0010, 5}, /* XGI_CetLCDDes1280x1024Data */
+ {Panel1400x1050, 0x0019, 0x0001, 6}, /* XGI_ExtLCDDes1400x1050Data */
+ {Panel1400x1050, 0x0019, 0x0000, 7}, /* XGI_StLCDDes1400x1050Data */
+ {Panel1400x1050, 0x0418, 0x0010, 8}, /* XGI_CetLCDDes1400x1050Data */
+ {Panel1400x1050, 0x0418, 0x0410, 9}, /* XGI_CetLCDDes1400x1050Data2 */
+ {Panel1600x1200, 0x0019, 0x0001, 10}, /* XGI_ExtLCDDes1600x1200Data */
+ {Panel1600x1200, 0x0019, 0x0000, 11}, /* XGI_StLCDDes1600x1200Data */
+ {PanelRef60Hz, 0x0008, 0x0008, 12}, /* XGI_NoScalingDesData */
+ {Panel1024x768x75, 0x0019, 0x0001, 13}, /*XGI_ExtLCDDes1024x768x75Data*/
+ {Panel1024x768x75, 0x0019, 0x0000, 14}, /* XGI_StLCDDes1024x768x75Data*/
+ {Panel1024x768x75, 0x0018, 0x0010, 15}, /*XGI_CetLCDDes1024x768x75Data*/
+ /* XGI_ExtLCDDes1280x1024x75Data */
+ {Panel1280x1024x75, 0x0019, 0x0001, 16},
+ /* XGI_StLCDDes1280x1024x75Data */
+ {Panel1280x1024x75, 0x0019, 0x0000, 17},
+ /* XGI_CetLCDDes1280x1024x75Data */
+ {Panel1280x1024x75, 0x0018, 0x0010, 18},
+ {PanelRef75Hz, 0x0008, 0x0008, 19}, /* XGI_NoScalingDesDatax75 */
+ {0xFF, 0x0000, 0x0000, 0}
};
-static struct XGI330_LCDDataTablStruct XGI_EPLLCDCRT1Ptr_H[] =
-{
- {Panel1024x768,0x0018,0x0000,0}, /* XGI_LVDSCRT11024x768_1_H */
- {Panel1024x768,0x0018,0x0010,1}, /* XGI_LVDSCRT11024x768_2_H */
- {Panel1280x1024,0x0018,0x0000,2}, /* XGI_LVDSCRT11280x1024_1_H */
- {Panel1280x1024,0x0018,0x0010,3}, /* XGI_LVDSCRT11280x1024_2_H */
- {Panel1400x1050,0x0018,0x0000,4}, /* XGI_LVDSCRT11400x1050_1_H */
- {Panel1400x1050,0x0018,0x0010,5}, /* XGI_LVDSCRT11400x1050_2_H */
- {Panel1600x1200,0x0018,0x0000,6}, /* XGI_LVDSCRT11600x1200_1_H */
- {Panel1024x768x75,0x0018,0x0000,7}, /* XGI_LVDSCRT11024x768_1_Hx75 */
- {Panel1024x768x75,0x0018,0x0010,8}, /* XGI_LVDSCRT11024x768_2_Hx75 */
- {Panel1280x1024x75,0x0018,0x0000,9}, /* XGI_LVDSCRT11280x1024_1_Hx75 */
- {Panel1280x1024x75,0x0018,0x0010,10}, /* XGI_LVDSCRT11280x1024_2_Hx75 */
- {0xFF,0x0000,0x0000,0}
+static struct XGI330_LCDDataTablStruct XGI_EPLLCDCRT1Ptr_H[] = {
+ {Panel1024x768, 0x0018, 0x0000, 0}, /* XGI_LVDSCRT11024x768_1_H */
+ {Panel1024x768, 0x0018, 0x0010, 1}, /* XGI_LVDSCRT11024x768_2_H */
+ {Panel1280x1024, 0x0018, 0x0000, 2}, /* XGI_LVDSCRT11280x1024_1_H */
+ {Panel1280x1024, 0x0018, 0x0010, 3}, /* XGI_LVDSCRT11280x1024_2_H */
+ {Panel1400x1050, 0x0018, 0x0000, 4}, /* XGI_LVDSCRT11400x1050_1_H */
+ {Panel1400x1050, 0x0018, 0x0010, 5}, /* XGI_LVDSCRT11400x1050_2_H */
+ {Panel1600x1200, 0x0018, 0x0000, 6}, /* XGI_LVDSCRT11600x1200_1_H */
+ {Panel1024x768x75, 0x0018, 0x0000, 7}, /* XGI_LVDSCRT11024x768_1_Hx75 */
+ {Panel1024x768x75, 0x0018, 0x0010, 8}, /* XGI_LVDSCRT11024x768_2_Hx75 */
+ {Panel1280x1024x75, 0x0018, 0x0000, 9}, /*XGI_LVDSCRT11280x1024_1_Hx75*/
+ {Panel1280x1024x75, 0x0018, 0x0010, 10},/*XGI_LVDSCRT11280x1024_2_Hx75*/
+ {0xFF, 0x0000, 0x0000, 0}
};
-static struct XGI330_LCDDataTablStruct XGI_EPLLCDCRT1Ptr_V[] =
-{
- {Panel1024x768,0x0018,0x0000,0}, /* XGI_LVDSCRT11024x768_1_V */
- {Panel1024x768,0x0018,0x0010,1}, /* XGI_LVDSCRT11024x768_2_V */
- {Panel1280x1024,0x0018,0x0000,2}, /* XGI_LVDSCRT11280x1024_1_V */
- {Panel1280x1024,0x0018,0x0010,3}, /* XGI_LVDSCRT11280x1024_2_V */
- {Panel1400x1050,0x0018,0x0000,4}, /* XGI_LVDSCRT11400x1050_1_V */
- {Panel1400x1050,0x0018,0x0010,5}, /* XGI_LVDSCRT11400x1050_2_V */
- {Panel1600x1200,0x0018,0x0000,6}, /* XGI_LVDSCRT11600x1200_1_V */
- {Panel1024x768x75,0x0018,0x0000,7}, /* XGI_LVDSCRT11024x768_1_Vx75 */
- {Panel1024x768x75,0x0018,0x0010,8}, /* XGI_LVDSCRT11024x768_2_Vx75 */
- {Panel1280x1024x75,0x0018,0x0000,9}, /* XGI_LVDSCRT11280x1024_1_Vx75 */
- {Panel1280x1024x75,0x0018,0x0010,10}, /* XGI_LVDSCRT11280x1024_2_Vx75 */
- {0xFF,0x0000,0x0000,0}
+static struct XGI330_LCDDataTablStruct XGI_EPLLCDCRT1Ptr_V[] = {
+ {Panel1024x768, 0x0018, 0x0000, 0}, /* XGI_LVDSCRT11024x768_1_V */
+ {Panel1024x768, 0x0018, 0x0010, 1}, /* XGI_LVDSCRT11024x768_2_V */
+ {Panel1280x1024, 0x0018, 0x0000, 2}, /* XGI_LVDSCRT11280x1024_1_V */
+ {Panel1280x1024, 0x0018, 0x0010, 3}, /* XGI_LVDSCRT11280x1024_2_V */
+ {Panel1400x1050, 0x0018, 0x0000, 4}, /* XGI_LVDSCRT11400x1050_1_V */
+ {Panel1400x1050, 0x0018, 0x0010, 5}, /* XGI_LVDSCRT11400x1050_2_V */
+ {Panel1600x1200, 0x0018, 0x0000, 6}, /* XGI_LVDSCRT11600x1200_1_V */
+ {Panel1024x768x75, 0x0018, 0x0000, 7}, /* XGI_LVDSCRT11024x768_1_Vx75 */
+ {Panel1024x768x75, 0x0018, 0x0010, 8}, /* XGI_LVDSCRT11024x768_2_Vx75 */
+ {Panel1280x1024x75, 0x0018, 0x0000, 9}, /*XGI_LVDSCRT11280x1024_1_Vx75*/
+ {Panel1280x1024x75, 0x0018, 0x0010, 10},/*XGI_LVDSCRT11280x1024_2_Vx75*/
+ {0xFF, 0x0000, 0x0000, 0}
};
-static struct XGI330_LCDDataTablStruct XGI_EPLLCDDataPtr[] =
-{
- {Panel1024x768,0x0018,0x0000,0}, /* XGI_LVDS1024x768Data_1 */
- {Panel1024x768,0x0018,0x0010,1}, /* XGI_LVDS1024x768Data_2 */
- {Panel1280x1024,0x0018,0x0000,2}, /* XGI_LVDS1280x1024Data_1 */
- {Panel1280x1024,0x0018,0x0010,3}, /* XGI_LVDS1280x1024Data_2 */
- {Panel1400x1050,0x0018,0x0000,4}, /* XGI_LVDS1400x1050Data_1 */
- {Panel1400x1050,0x0018,0x0010,5}, /* XGI_LVDS1400x1050Data_2 */
- {Panel1600x1200,0x0018,0x0000,6}, /* XGI_LVDS1600x1200Data_1 */
- {PanelRef60Hz,0x0008,0x0008,7}, /* XGI_LVDSNoScalingData */
- {Panel1024x768x75,0x0018,0x0000,8}, /* XGI_LVDS1024x768Data_1x75 */
- {Panel1024x768x75,0x0018,0x0010,9}, /* XGI_LVDS1024x768Data_2x75 */
- {Panel1280x1024x75,0x0018,0x0000,10}, /* XGI_LVDS1280x1024Data_1x75 */
- {Panel1280x1024x75,0x0018,0x0010,11}, /* XGI_LVDS1280x1024Data_2x75 */
- {PanelRef75Hz,0x0008,0x0008,12}, /* XGI_LVDSNoScalingDatax75 */
- {0xFF,0x0000,0x0000,0}
+static struct XGI330_LCDDataTablStruct XGI_EPLLCDDataPtr[] = {
+ {Panel1024x768, 0x0018, 0x0000, 0}, /* XGI_LVDS1024x768Data_1 */
+ {Panel1024x768, 0x0018, 0x0010, 1}, /* XGI_LVDS1024x768Data_2 */
+ {Panel1280x1024, 0x0018, 0x0000, 2}, /* XGI_LVDS1280x1024Data_1 */
+ {Panel1280x1024, 0x0018, 0x0010, 3}, /* XGI_LVDS1280x1024Data_2 */
+ {Panel1400x1050, 0x0018, 0x0000, 4}, /* XGI_LVDS1400x1050Data_1 */
+ {Panel1400x1050, 0x0018, 0x0010, 5}, /* XGI_LVDS1400x1050Data_2 */
+ {Panel1600x1200, 0x0018, 0x0000, 6}, /* XGI_LVDS1600x1200Data_1 */
+ {PanelRef60Hz, 0x0008, 0x0008, 7}, /* XGI_LVDSNoScalingData */
+ {Panel1024x768x75, 0x0018, 0x0000, 8}, /* XGI_LVDS1024x768Data_1x75 */
+ {Panel1024x768x75, 0x0018, 0x0010, 9}, /* XGI_LVDS1024x768Data_2x75 */
+ {Panel1280x1024x75, 0x0018, 0x0000, 10}, /* XGI_LVDS1280x1024Data_1x75*/
+ {Panel1280x1024x75, 0x0018, 0x0010, 11}, /*XGI_LVDS1280x1024Data_2x75*/
+ {PanelRef75Hz, 0x0008, 0x0008, 12}, /* XGI_LVDSNoScalingDatax75 */
+ {0xFF, 0x0000, 0x0000, 0}
};
-static struct XGI330_LCDDataTablStruct XGI_EPLLCDDesDataPtr[] =
-{
- {Panel1024x768,0x0018,0x0000,0}, /* XGI_LVDS1024x768Des_1 */
- {Panel1024x768,0x0618,0x0410,1}, /* XGI_LVDS1024x768Des_3 */
- {Panel1024x768,0x0018,0x0010,2}, /* XGI_LVDS1024x768Des_2 */
- {Panel1280x1024,0x0018,0x0000,3}, /* XGI_LVDS1280x1024Des_1 */
- {Panel1280x1024,0x0018,0x0010,4}, /* XGI_LVDS1280x1024Des_2 */
- {Panel1400x1050,0x0018,0x0000,5}, /* XGI_LVDS1400x1050Des_1 */
- {Panel1400x1050,0x0018,0x0010,6}, /* XGI_LVDS1400x1050Des_2 */
- {Panel1600x1200,0x0018,0x0000,7}, /* XGI_LVDS1600x1200Des_1 */
- {PanelRef60Hz,0x0008,0x0008,8}, /* XGI_LVDSNoScalingDesData */
- {Panel1024x768x75,0x0018,0x0000,9}, /* XGI_LVDS1024x768Des_1x75 */
- {Panel1024x768x75,0x0618,0x0410,10}, /* XGI_LVDS1024x768Des_3x75 */
- {Panel1024x768x75,0x0018,0x0010,11}, /* XGI_LVDS1024x768Des_2x75 */
- {Panel1280x1024x75,0x0018,0x0000,12}, /* XGI_LVDS1280x1024Des_1x75 */
- {Panel1280x1024x75,0x0018,0x0010,13}, /* XGI_LVDS1280x1024Des_2x75 */
- {PanelRef75Hz,0x0008,0x0008,14}, /* XGI_LVDSNoScalingDesDatax75 */
- {0xFF,0x0000,0x0000,0}
+static struct XGI330_LCDDataTablStruct XGI_EPLLCDDesDataPtr[] = {
+ {Panel1024x768, 0x0018, 0x0000, 0}, /* XGI_LVDS1024x768Des_1 */
+ {Panel1024x768, 0x0618, 0x0410, 1}, /* XGI_LVDS1024x768Des_3 */
+ {Panel1024x768, 0x0018, 0x0010, 2}, /* XGI_LVDS1024x768Des_2 */
+ {Panel1280x1024, 0x0018, 0x0000, 3}, /* XGI_LVDS1280x1024Des_1 */
+ {Panel1280x1024, 0x0018, 0x0010, 4}, /* XGI_LVDS1280x1024Des_2 */
+ {Panel1400x1050, 0x0018, 0x0000, 5}, /* XGI_LVDS1400x1050Des_1 */
+ {Panel1400x1050, 0x0018, 0x0010, 6}, /* XGI_LVDS1400x1050Des_2 */
+ {Panel1600x1200, 0x0018, 0x0000, 7}, /* XGI_LVDS1600x1200Des_1 */
+ {PanelRef60Hz, 0x0008, 0x0008, 8}, /* XGI_LVDSNoScalingDesData */
+ {Panel1024x768x75, 0x0018, 0x0000, 9}, /* XGI_LVDS1024x768Des_1x75 */
+ {Panel1024x768x75, 0x0618, 0x0410, 10}, /* XGI_LVDS1024x768Des_3x75 */
+ {Panel1024x768x75, 0x0018, 0x0010, 11}, /* XGI_LVDS1024x768Des_2x75 */
+ {Panel1280x1024x75, 0x0018, 0x0000, 12}, /* XGI_LVDS1280x1024Des_1x75 */
+ {Panel1280x1024x75, 0x0018, 0x0010, 13}, /* XGI_LVDS1280x1024Des_2x75 */
+ {PanelRef75Hz, 0x0008, 0x0008, 14}, /* XGI_LVDSNoScalingDesDatax75 */
+ {0xFF, 0x0000, 0x0000, 0}
};
-static struct XGI330_LCDDataTablStruct XGI_EPLCHLCDRegPtr[] =
-{
- {Panel1024x768,0x0000,0x0000,0}, /* XGI_CH7017LV1024x768 */
- {Panel1400x1050,0x0000,0x0000,1}, /* XGI_CH7017LV1400x1050 */
- {0xFF,0x0000,0x0000,0}
+static struct XGI330_LCDDataTablStruct XGI_EPLCHLCDRegPtr[] = {
+ {Panel1024x768, 0x0000, 0x0000, 0}, /* XGI_CH7017LV1024x768 */
+ {Panel1400x1050, 0x0000, 0x0000, 1}, /* XGI_CH7017LV1400x1050 */
+ {0xFF, 0x0000, 0x0000, 0}
};
-static struct XGI330_TVDataTablStruct XGI_TVDataTable[] =
-{
- {0x09E1,0x0001,0}, /* XGI_ExtPALData */
- {0x09E1,0x0000,1}, /* XGI_ExtNTSCData */
- {0x09E1,0x0801,2}, /* XGI_StPALData */
- {0x09E1,0x0800,3}, /* XGI_StNTSCData */
- {0x49E0,0x0100,4}, /* XGI_ExtHiTVData */
- {0x49E0,0x4100,5}, /* XGI_St2HiTVData */
- {0x49E0,0x4900,13}, /* XGI_St1HiTVData */
- {0x09E0,0x0020,6}, /* XGI_ExtYPbPr525iData */
- {0x09E0,0x0040,7}, /* XGI_ExtYPbPr525pData */
- {0x09E0,0x0080,8}, /* XGI_ExtYPbPr750pData */
- {0x09E0,0x0820,9}, /* XGI_StYPbPr525iData */
- {0x09E0,0x0840,10}, /* XGI_StYPbPr525pData */
- {0x09E0,0x0880,11}, /* XGI_StYPbPr750pData */
- {0xffff,0x0000,12} /* END */
+static struct XGI330_TVDataTablStruct XGI_TVDataTable[] = {
+ {0x09E1, 0x0001, 0}, /* XGI_ExtPALData */
+ {0x09E1, 0x0000, 1}, /* XGI_ExtNTSCData */
+ {0x09E1, 0x0801, 2}, /* XGI_StPALData */
+ {0x09E1, 0x0800, 3}, /* XGI_StNTSCData */
+ {0x49E0, 0x0100, 4}, /* XGI_ExtHiTVData */
+ {0x49E0, 0x4100, 5}, /* XGI_St2HiTVData */
+ {0x49E0, 0x4900, 13}, /* XGI_St1HiTVData */
+ {0x09E0, 0x0020, 6}, /* XGI_ExtYPbPr525iData */
+ {0x09E0, 0x0040, 7}, /* XGI_ExtYPbPr525pData */
+ {0x09E0, 0x0080, 8}, /* XGI_ExtYPbPr750pData */
+ {0x09E0, 0x0820, 9}, /* XGI_StYPbPr525iData */
+ {0x09E0, 0x0840, 10}, /* XGI_StYPbPr525pData */
+ {0x09E0, 0x0880, 11}, /* XGI_StYPbPr750pData */
+ {0xffff, 0x0000, 12} /* END */
};
#if 0
-static unsigned short TVLenList[] =
-{
- LVDSCRT1Len_H,
- LVDSCRT1Len_V,
- LVDSDataLen,
- 0,
- TVDataLen,
- 0,
- 0,
- CHTVRegLen
-} ;
+static unsigned short TVLenList[] = {
+ LVDSCRT1Len_H,
+ LVDSCRT1Len_V,
+ LVDSDataLen,
+ 0,
+ TVDataLen,
+ 0,
+ 0,
+ CHTVRegLen
+};
#endif
/* Chrontel 7017 TV CRT1 Timing List */
-static struct XGI330_TVDataTablStruct XGI_EPLCHTVCRT1Ptr[] =
-{
- {0x0011,0x0000,0}, /* XGI_CHTVCRT1UNTSC */
- {0x0011,0x0010,1}, /* XGI_CHTVCRT1ONTSC */
- {0x0011,0x0001,2}, /* XGI_CHTVCRT1UPAL */
- {0x0011,0x0011,3}, /* XGI_CHTVCRT1OPAL */
- {0xFFFF,0x0000,4}
+static struct XGI330_TVDataTablStruct XGI_EPLCHTVCRT1Ptr[] = {
+ {0x0011, 0x0000, 0}, /* XGI_CHTVCRT1UNTSC */
+ {0x0011, 0x0010, 1}, /* XGI_CHTVCRT1ONTSC */
+ {0x0011, 0x0001, 2}, /* XGI_CHTVCRT1UPAL */
+ {0x0011, 0x0011, 3}, /* XGI_CHTVCRT1OPAL */
+ {0xFFFF, 0x0000, 4}
};
/* ;;Chrontel 7017 TV Timing List */
-static struct XGI330_TVDataTablStruct XGI_EPLCHTVDataPtr[] =
-{
- {0x0011,0x0000,0}, /* XGI_CHTVUNTSCData */
- {0x0011,0x0010,1}, /* XGI_CHTVONTSCData */
- {0x0011,0x0001,2}, /* XGI_CHTVUPALData */
- {0x0011,0x0011,3}, /* XGI_CHTVOPALData */
- {0xFFFF,0x0000,4}
+static struct XGI330_TVDataTablStruct XGI_EPLCHTVDataPtr[] = {
+ {0x0011, 0x0000, 0}, /* XGI_CHTVUNTSCData */
+ {0x0011, 0x0010, 1}, /* XGI_CHTVONTSCData */
+ {0x0011, 0x0001, 2}, /* XGI_CHTVUPALData */
+ {0x0011, 0x0011, 3}, /* XGI_CHTVOPALData */
+ {0xFFFF, 0x0000, 4}
};
/* ;;Chrontel 7017 TV Reg. List */
-static struct XGI330_TVDataTablStruct XGI_EPLCHTVRegPtr[] =
-{
- {0x0011,0x0000,0}, /* XGI_CHTVRegUNTSC */
- {0x0011,0x0010,1}, /* XGI_CHTVRegONTSC */
- {0x0011,0x0001,2}, /* XGI_CHTVRegUPAL */
- {0x0011,0x0011,3}, /* XGI_CHTVRegOPAL */
- {0xFFFF,0x0000,4}
+static struct XGI330_TVDataTablStruct XGI_EPLCHTVRegPtr[] = {
+ {0x0011, 0x0000, 0}, /* XGI_CHTVRegUNTSC */
+ {0x0011, 0x0010, 1}, /* XGI_CHTVRegONTSC */
+ {0x0011, 0x0001, 2}, /* XGI_CHTVRegUPAL */
+ {0x0011, 0x0011, 3}, /* XGI_CHTVRegOPAL */
+ {0xFFFF, 0x0000, 4}
};
-static unsigned short LCDLenList[] =
-{
- LVDSCRT1Len_H,
- LVDSCRT1Len_V,
- LVDSDataLen,
- LCDDesDataLen,
- LCDDataLen,
- LCDDesDataLen,
- 0,
- LCDDesDataLen,
- LCDDesDataLen,
- 0
-} ;
+static unsigned short LCDLenList[] = {
+ LVDSCRT1Len_H,
+ LVDSCRT1Len_V,
+ LVDSDataLen,
+ LCDDesDataLen,
+ LCDDataLen,
+ LCDDesDataLen,
+ 0,
+ LCDDesDataLen,
+ LCDDesDataLen,
+ 0
+};
#if 0
-static struct XGI330_LCDCapStruct XGI660_LCDDLCapList[] = /* 660, Dual link */
-{
+/* 660, Dual link */
+static struct XGI330_LCDCapStruct XGI660_LCDDLCapList[] = {
/* LCDCap1024x768 */
- {Panel1024x768, DefaultLCDCap, 0, 0x014, 0x88, 0x06, VCLK65,
- 0x6C, 0xC3, 0x35, 0x62, 0x02, 0x14, 0x0A, 0x02, 0x00,
- 0x30, 0x10, 0x5A, 0x10, 0x10, 0x0A, 0xC0, 0x28, 0x10},
+ {Panel1024x768, DefaultLCDCap, 0, 0x014, 0x88, 0x06, VCLK65,
+ 0x6C, 0xC3, 0x35, 0x62, 0x02, 0x14, 0x0A, 0x02, 0x00,
+ 0x30, 0x10, 0x5A, 0x10, 0x10, 0x0A, 0xC0, 0x28, 0x10},
/* LCDCap1280x1024 */
- {Panel1280x1024, LCDDualLink+DefaultLCDCap, StLCDBToA, 0x053, 0x70, 0x03, VCLK108_2,
- 0x70, 0x44, 0xF8, 0x2F, 0x02, 0x14, 0x0A, 0x02, 0x00,
- 0x30, 0x10, 0x5A, 0x10, 0x10, 0x0A, 0xC0, 0x30, 0x10},
+ {Panel1280x1024, LCDDualLink+DefaultLCDCap, StLCDBToA,
+ 0x053, 0x70, 0x03, VCLK108_2,
+ 0x70, 0x44, 0xF8, 0x2F, 0x02, 0x14, 0x0A, 0x02, 0x00,
+ 0x30, 0x10, 0x5A, 0x10, 0x10, 0x0A, 0xC0, 0x30, 0x10},
/* LCDCap1400x1050 */
- {Panel1400x1050, LCDDualLink+DefaultLCDCap, StLCDBToA, 0x053, 0x70, 0x03, VCLK108_2,
- 0x70, 0x44, 0xF8, 0x2F, 0x02, 0x14, 0x0A, 0x02, 0x00,
- 0x30, 0x10, 0x5A, 0x10, 0x10, 0x0A, 0xC0, 0x30, 0x10},
+ {Panel1400x1050, LCDDualLink+DefaultLCDCap, StLCDBToA,
+ 0x053, 0x70, 0x03, VCLK108_2,
+ 0x70, 0x44, 0xF8, 0x2F, 0x02, 0x14, 0x0A, 0x02, 0x00,
+ 0x30, 0x10, 0x5A, 0x10, 0x10, 0x0A, 0xC0, 0x30, 0x10},
/* LCDCap1600x1200 */
- {Panel1600x1200, LCDDualLink+DefaultLCDCap, LCDToFull, 0x053, 0xC0, 0x03, VCLK162,
- 0x43, 0x22, 0x70, 0x24, 0x02, 0x14, 0x0A, 0x02, 0x00,
- 0x30, 0x10, 0x5A, 0x10, 0x10, 0x0A, 0xC0, 0x30, 0x10},
+ {Panel1600x1200, LCDDualLink+DefaultLCDCap, LCDToFull,
+ 0x053, 0xC0, 0x03, VCLK162,
+ 0x43, 0x22, 0x70, 0x24, 0x02, 0x14, 0x0A, 0x02, 0x00,
+ 0x30, 0x10, 0x5A, 0x10, 0x10, 0x0A, 0xC0, 0x30, 0x10},
/* LCDCap1024x768x75 */
- {Panel1024x768x75, DefaultLCDCap, 0, 0x014, 0x60, 0, VCLK78_75,
- 0x2B, 0x61, 0x2B, 0x61, 0x02, 0x14, 0x0A, 0x02, 0x00,
- 0x30, 0x10, 0x5A, 0x10, 0x10, 0x0A, 0xC0, 0x28, 0x10},
+ {Panel1024x768x75, DefaultLCDCap, 0, 0x014, 0x60, 0, VCLK78_75,
+ 0x2B, 0x61, 0x2B, 0x61, 0x02, 0x14, 0x0A, 0x02, 0x00,
+ 0x30, 0x10, 0x5A, 0x10, 0x10, 0x0A, 0xC0, 0x28, 0x10},
/* LCDCap1280x1024x75 */
- {Panel1280x1024x75, LCDDualLink+DefaultLCDCap, StLCDBToA, 0x053, 0x90, 0x03, VCLK135_5,
- 0x54, 0x42, 0x4A, 0x61, 0x02, 0x14, 0x0A, 0x02, 0x00,
- 0x30, 0x10, 0x5A, 0x10, 0x10, 0x0A, 0xC0, 0x30, 0x10},
+ {Panel1280x1024x75, LCDDualLink+DefaultLCDCap, StLCDBToA,
+ 0x053, 0x90, 0x03, VCLK135_5,
+ 0x54, 0x42, 0x4A, 0x61, 0x02, 0x14, 0x0A, 0x02, 0x00,
+ 0x30, 0x10, 0x5A, 0x10, 0x10, 0x0A, 0xC0, 0x30, 0x10},
/* LCDCapDefault */
- {0xFF, DefaultLCDCap, 0, 0x053, 0x88, 0x06, VCLK65,
- 0x6C, 0xC3, 0x35, 0x62, 0x02, 0x14, 0x0A, 0x02, 0x00,
- 0x30, 0x10, 0x5A, 0x10, 0x10, 0x0A, 0xC0, 0x28, 0x10}
+ {0xFF, DefaultLCDCap, 0, 0x053, 0x88, 0x06, VCLK65,
+ 0x6C, 0xC3, 0x35, 0x62, 0x02, 0x14, 0x0A, 0x02, 0x00,
+ 0x30, 0x10, 0x5A, 0x10, 0x10, 0x0A, 0xC0, 0x28, 0x10}
};
#endif
-static struct XGI330_LCDCapStruct XGI_LCDDLCapList[] = /* Dual link only */
-{
+/* Dual link only */
+static struct XGI330_LCDCapStruct XGI_LCDDLCapList[] = {
/* LCDCap1024x768 */
- {Panel1024x768, DefaultLCDCap, 0, 0x012, 0x88, 0x06, VCLK65,
- 0x6C, 0xC3, 0x35, 0x62, 0x02, 0x14, 0x0A, 0x02, 0x00,
- 0x30, 0x10, 0x5A, 0x10, 0x10, 0x0A, 0xC0, 0x28, 0x10},
+ {Panel1024x768, DefaultLCDCap, 0, 0x012, 0x88, 0x06, VCLK65,
+ 0x6C, 0xC3, 0x35, 0x62, 0x02, 0x14, 0x0A, 0x02, 0x00,
+ 0x30, 0x10, 0x5A, 0x10, 0x10, 0x0A, 0xC0, 0x28, 0x10},
/* LCDCap1280x1024 */
- {Panel1280x1024, LCDDualLink+DefaultLCDCap, StLCDBToA, 0x012, 0x70, 0x03, VCLK108_2,
- 0x70, 0x44, 0xF8, 0x2F, 0x02, 0x14, 0x0A, 0x02, 0x00,
- 0x30, 0x10, 0x5A, 0x10, 0x10, 0x0A, 0xC0, 0x30, 0x10},
+ {Panel1280x1024, LCDDualLink+DefaultLCDCap, StLCDBToA,
+ 0x012, 0x70, 0x03, VCLK108_2,
+ 0x70, 0x44, 0xF8, 0x2F, 0x02, 0x14, 0x0A, 0x02, 0x00,
+ 0x30, 0x10, 0x5A, 0x10, 0x10, 0x0A, 0xC0, 0x30, 0x10},
/* LCDCap1400x1050 */
- {Panel1400x1050, LCDDualLink+DefaultLCDCap, StLCDBToA, 0x012, 0x70, 0x03, VCLK108_2,
- 0x70, 0x44, 0xF8, 0x2F, 0x02, 0x14, 0x0A, 0x02, 0x00,
- 0x30, 0x10, 0x5A, 0x10, 0x10, 0x0A, 0xC0, 0x30, 0x10},
+ {Panel1400x1050, LCDDualLink+DefaultLCDCap, StLCDBToA,
+ 0x012, 0x70, 0x03, VCLK108_2,
+ 0x70, 0x44, 0xF8, 0x2F, 0x02, 0x14, 0x0A, 0x02, 0x00,
+ 0x30, 0x10, 0x5A, 0x10, 0x10, 0x0A, 0xC0, 0x30, 0x10},
/* LCDCap1600x1200 */
- {Panel1600x1200, LCDDualLink+DefaultLCDCap, LCDToFull, 0x012, 0xC0, 0x03, VCLK162,
- 0x43, 0x22, 0x70, 0x24, 0x02, 0x14, 0x0A, 0x02, 0x00,
- 0x30, 0x10, 0x5A, 0x10, 0x10, 0x0A, 0xC0, 0x30, 0x10},
+ {Panel1600x1200, LCDDualLink+DefaultLCDCap, LCDToFull,
+ 0x012, 0xC0, 0x03, VCLK162,
+ 0x43, 0x22, 0x70, 0x24, 0x02, 0x14, 0x0A, 0x02, 0x00,
+ 0x30, 0x10, 0x5A, 0x10, 0x10, 0x0A, 0xC0, 0x30, 0x10},
/* LCDCap1024x768x75 */
- {Panel1024x768x75, DefaultLCDCap, 0, 0x012, 0x60, 0, VCLK78_75,
- 0x2B, 0x61, 0x2B, 0x61, 0x02, 0x14, 0x0A, 0x02, 0x00,
- 0x30, 0x10, 0x5A, 0x10, 0x10, 0x0A, 0xC0, 0x28, 0x10},
+ {Panel1024x768x75, DefaultLCDCap, 0, 0x012, 0x60, 0, VCLK78_75,
+ 0x2B, 0x61, 0x2B, 0x61, 0x02, 0x14, 0x0A, 0x02, 0x00,
+ 0x30, 0x10, 0x5A, 0x10, 0x10, 0x0A, 0xC0, 0x28, 0x10},
/* LCDCap1280x1024x75 */
- {Panel1280x1024x75, LCDDualLink+DefaultLCDCap, StLCDBToA, 0x012, 0x90, 0x03, VCLK135_5,
- 0x54, 0x42, 0x4A, 0x61, 0x02, 0x14, 0x0A, 0x02, 0x00,
- 0x30, 0x10, 0x5A, 0x10, 0x10, 0x0A, 0xC0, 0x30, 0x10},
+ {Panel1280x1024x75, LCDDualLink+DefaultLCDCap, StLCDBToA,
+ 0x012, 0x90, 0x03, VCLK135_5,
+ 0x54, 0x42, 0x4A, 0x61, 0x02, 0x14, 0x0A, 0x02, 0x00,
+ 0x30, 0x10, 0x5A, 0x10, 0x10, 0x0A, 0xC0, 0x30, 0x10},
/* LCDCapDefault */
- {0xFF, DefaultLCDCap, 0, 0x012, 0x88, 0x06, VCLK65,
- 0x6C, 0xC3, 0x35, 0x62, 0x02, 0x14, 0x0A, 0x02, 0x00,
- 0x30, 0x10, 0x5A, 0x10, 0x10, 0x0A, 0xC0, 0x28, 0x10}
+ {0xFF, DefaultLCDCap, 0, 0x012, 0x88, 0x06, VCLK65,
+ 0x6C, 0xC3, 0x35, 0x62, 0x02, 0x14, 0x0A, 0x02, 0x00,
+ 0x30, 0x10, 0x5A, 0x10, 0x10, 0x0A, 0xC0, 0x28, 0x10}
};
#if 0
-static struct XGI330_LCDCapStruct XGI660_LCDCapList[] =
-{
+static struct XGI330_LCDCapStruct XGI660_LCDCapList[] = {
/* LCDCap1024x768 */
- {Panel1024x768, DefaultLCDCap, 0, 0x014, 0x88, 0x06, VCLK65,
- 0x6C, 0xC3, 0x35, 0x62, 0x02, 0x14, 0x0A, 0x02, 0x00,
- 0x30, 0x10, 0x5A, 0x10, 0x10, 0x0A, 0xC0, 0x28, 0x10},
+ {Panel1024x768, DefaultLCDCap, 0, 0x014, 0x88, 0x06, VCLK65,
+ 0x6C, 0xC3, 0x35, 0x62, 0x02, 0x14, 0x0A, 0x02, 0x00,
+ 0x30, 0x10, 0x5A, 0x10, 0x10, 0x0A, 0xC0, 0x28, 0x10},
/* LCDCap1280x1024 */
- {Panel1280x1024, DefaultLCDCap, StLCDBToA, 0x053, 0x70, 0x03, VCLK108_2,
- 0x70, 0x44, 0xF8, 0x2F, 0x02, 0x14, 0x0A, 0x02, 0x00,
- 0x30, 0x10, 0x5A, 0x10, 0x10, 0x0A, 0xC0, 0x30, 0x10},
+ {Panel1280x1024, DefaultLCDCap, StLCDBToA, 0x053, 0x70, 0x03, VCLK108_2,
+ 0x70, 0x44, 0xF8, 0x2F, 0x02, 0x14, 0x0A, 0x02, 0x00,
+ 0x30, 0x10, 0x5A, 0x10, 0x10, 0x0A, 0xC0, 0x30, 0x10},
/* LCDCap1400x1050 */
- {Panel1400x1050, DefaultLCDCap, StLCDBToA, 0x053, 0x70, 0x03, VCLK108_2,
- 0x70, 0x44, 0xF8, 0x2F, 0x02, 0x14, 0x0A, 0x02, 0x00,
- 0x30, 0x10, 0x5A, 0x10, 0x10, 0x0A, 0xC0, 0x30, 0x10},
+ {Panel1400x1050, DefaultLCDCap, StLCDBToA, 0x053, 0x70, 0x03, VCLK108_2,
+ 0x70, 0x44, 0xF8, 0x2F, 0x02, 0x14, 0x0A, 0x02, 0x00,
+ 0x30, 0x10, 0x5A, 0x10, 0x10, 0x0A, 0xC0, 0x30, 0x10},
/* LCDCap1600x1200 */
- {Panel1600x1200, DefaultLCDCap, LCDToFull, 0x053, 0xC0, 0x03, VCLK162,
- 0x5A, 0x23, 0x5A, 0x23, 0x02, 0x14, 0x0A, 0x02, 0x00,
- 0x30, 0x10, 0x5A, 0x10, 0x10, 0x0A, 0xC0, 0x30, 0x10},
+ {Panel1600x1200, DefaultLCDCap, LCDToFull, 0x053, 0xC0, 0x03, VCLK162,
+ 0x5A, 0x23, 0x5A, 0x23, 0x02, 0x14, 0x0A, 0x02, 0x00,
+ 0x30, 0x10, 0x5A, 0x10, 0x10, 0x0A, 0xC0, 0x30, 0x10},
/* LCDCap1024x768x75 */
- {Panel1024x768x75, DefaultLCDCap, 0, 0x014, 0x60, 0, VCLK78_75,
- 0x2B, 0x61, 0x2B, 0x61, 0x02, 0x14, 0x0A, 0x02, 0x00,
- 0x30, 0x10, 0x5A, 0x10, 0x10, 0x0A, 0xC0, 0x28, 0x10},
+ {Panel1024x768x75, DefaultLCDCap, 0, 0x014, 0x60, 0, VCLK78_75,
+ 0x2B, 0x61, 0x2B, 0x61, 0x02, 0x14, 0x0A, 0x02, 0x00,
+ 0x30, 0x10, 0x5A, 0x10, 0x10, 0x0A, 0xC0, 0x28, 0x10},
/* LCDCap1280x1024x75 */
- {Panel1280x1024x75,+DefaultLCDCap, StLCDBToA, 0x053, 0x90, 0x03, VCLK135_5,
- 0x54, 0x42, 0x4A, 0x61, 0x02, 0x14, 0x0A, 0x02, 0x00,
- 0x30, 0x10, 0x5A, 0x10, 0x10, 0x0A, 0xC0, 0x30, 0x10},
+ {Panel1280x1024x75, + DefaultLCDCap, StLCDBToA,
+ 0x053, 0x90, 0x03, VCLK135_5,
+ 0x54, 0x42, 0x4A, 0x61, 0x02, 0x14, 0x0A, 0x02, 0x00,
+ 0x30, 0x10, 0x5A, 0x10, 0x10, 0x0A, 0xC0, 0x30, 0x10},
/* LCDCapDefault */
- {0xFF, DefaultLCDCap, 0, 0x053, 0x88, 0x06, VCLK65,
- 0x6C, 0xC3, 0x35, 0x62, 0x02, 0x14, 0x0A, 0x02, 0x00,
- 0x30, 0x10, 0x5A, 0x10, 0x10, 0x0A, 0xC0, 0x28, 0x10}
+ {0xFF, DefaultLCDCap, 0, 0x053, 0x88, 0x06, VCLK65,
+ 0x6C, 0xC3, 0x35, 0x62, 0x02, 0x14, 0x0A, 0x02, 0x00,
+ 0x30, 0x10, 0x5A, 0x10, 0x10, 0x0A, 0xC0, 0x28, 0x10}
};
#endif
-static struct XGI330_LCDCapStruct XGI_LCDCapList[] =
-{
+static struct XGI330_LCDCapStruct XGI_LCDCapList[] = {
/* LCDCap1024x768 */
- {Panel1024x768, DefaultLCDCap, 0, 0x012, 0x88, 0x06, VCLK65,
- 0x6C, 0xC3, 0x35, 0x62, 0x02, 0x14, 0x0A, 0x02, 0x00,
- 0x30, 0x10, 0x5A, 0x10, 0x10, 0x0A, 0xC0, 0x28, 0x10},
+ {Panel1024x768, DefaultLCDCap, 0, 0x012, 0x88, 0x06, VCLK65,
+ 0x6C, 0xC3, 0x35, 0x62, 0x02, 0x14, 0x0A, 0x02, 0x00,
+ 0x30, 0x10, 0x5A, 0x10, 0x10, 0x0A, 0xC0, 0x28, 0x10},
/* LCDCap1280x1024 */
- {Panel1280x1024, DefaultLCDCap, StLCDBToA, 0x012, 0x70, 0x03, VCLK108_2,
- 0x70, 0x44, 0xF8, 0x2F, 0x02, 0x14, 0x0A, 0x02, 0x00,
- 0x30, 0x10, 0x5A, 0x10, 0x10, 0x0A, 0xC0, 0x30, 0x10},
+ {Panel1280x1024, DefaultLCDCap, StLCDBToA,
+ 0x012, 0x70, 0x03, VCLK108_2,
+ 0x70, 0x44, 0xF8, 0x2F, 0x02, 0x14, 0x0A, 0x02, 0x00,
+ 0x30, 0x10, 0x5A, 0x10, 0x10, 0x0A, 0xC0, 0x30, 0x10},
/* LCDCap1400x1050 */
- {Panel1400x1050, DefaultLCDCap, StLCDBToA, 0x012, 0x70, 0x03, VCLK108_2,
- 0x70, 0x44, 0xF8, 0x2F, 0x02, 0x14, 0x0A, 0x02, 0x00,
- 0x30, 0x10, 0x5A, 0x10, 0x10, 0x0A, 0xC0, 0x30, 0x10},
+ {Panel1400x1050, DefaultLCDCap, StLCDBToA,
+ 0x012, 0x70, 0x03, VCLK108_2,
+ 0x70, 0x44, 0xF8, 0x2F, 0x02, 0x14, 0x0A, 0x02, 0x00,
+ 0x30, 0x10, 0x5A, 0x10, 0x10, 0x0A, 0xC0, 0x30, 0x10},
/* LCDCap1600x1200 */
- {Panel1600x1200, DefaultLCDCap, LCDToFull, 0x012, 0xC0, 0x03, VCLK162,
- 0x5A, 0x23, 0x5A, 0x23, 0x02, 0x14, 0x0A, 0x02, 0x00,
- 0x30, 0x10, 0x5A, 0x10, 0x10, 0x0A, 0xC0, 0x30, 0x10},
+ {Panel1600x1200, DefaultLCDCap, LCDToFull,
+ 0x012, 0xC0, 0x03, VCLK162,
+ 0x5A, 0x23, 0x5A, 0x23, 0x02, 0x14, 0x0A, 0x02, 0x00,
+ 0x30, 0x10, 0x5A, 0x10, 0x10, 0x0A, 0xC0, 0x30, 0x10},
/* LCDCap1024x768x75 */
- {Panel1024x768x75, DefaultLCDCap, 0, 0x012, 0x60, 0, VCLK78_75,
- 0x2B, 0x61, 0x2B, 0x61, 0x02, 0x14, 0x0A, 0x02, 0x00,
- 0x30, 0x10, 0x5A, 0x10, 0x10, 0x0A, 0xC0, 0x28, 0x10},
+ {Panel1024x768x75, DefaultLCDCap, 0, 0x012, 0x60, 0, VCLK78_75,
+ 0x2B, 0x61, 0x2B, 0x61, 0x02, 0x14, 0x0A, 0x02, 0x00,
+ 0x30, 0x10, 0x5A, 0x10, 0x10, 0x0A, 0xC0, 0x28, 0x10},
/* LCDCap1280x1024x75 */
- {Panel1280x1024x75, DefaultLCDCap, StLCDBToA, 0x012, 0x90, 0x03, VCLK135_5,
- 0x54, 0x42, 0x4A, 0x61, 0x02, 0x14, 0x0A, 0x02, 0x00,
- 0x30, 0x10, 0x5A, 0x10, 0x10, 0x0A, 0xC0, 0x30, 0x10},
+ {Panel1280x1024x75, DefaultLCDCap, StLCDBToA,
+ 0x012, 0x90, 0x03, VCLK135_5,
+ 0x54, 0x42, 0x4A, 0x61, 0x02, 0x14, 0x0A, 0x02, 0x00,
+ 0x30, 0x10, 0x5A, 0x10, 0x10, 0x0A, 0xC0, 0x30, 0x10},
/* LCDCapDefault */
- {0xFF, DefaultLCDCap, 0, 0x012, 0x88, 0x06, VCLK65,
- 0x6C, 0xC3, 0x35, 0x62, 0x02, 0x14, 0x0A, 0x02, 0x00,
- 0x30, 0x10, 0x5A, 0x10, 0x10, 0x0A, 0xC0, 0x28, 0x10}
+ {0xFF, DefaultLCDCap, 0, 0x012, 0x88, 0x06, VCLK65,
+ 0x6C, 0xC3, 0x35, 0x62, 0x02, 0x14, 0x0A, 0x02, 0x00,
+ 0x30, 0x10, 0x5A, 0x10, 0x10, 0x0A, 0xC0, 0x28, 0x10}
};
-struct XGI21_LVDSCapStruct XGI21_LCDCapList[] =
-{
- {DisableLCD24bpp + LCDPolarity,
- 2160,1250,1600,1200, 64, 1, 192, 3,
- 0x70,0x24,0x20,0x04,0x0A,0x02,0xC8
- },
- {DisableLCD24bpp + LCDPolarity,
- 1688,1066,1280,1024, 48, 1, 112, 3,
- 0x70,0x44,0x20,0x04,0x0A,0x02,0xC8
- },
- {DisableLCD24bpp + LCDPolarity + (LCDPolarity << 8),
- 1344, 806,1024, 768, 24, 3, 136, 6,
- 0x6C,0x65,0x20,0x04,0x0A,0x02,0xC8
- },
- {DisableLCD24bpp + LCDPolarity,
- 1056, 628, 800, 600, 40, 1, 128, 4,
- 0x42,0xE2,0x20,0x14,0x0A,0x02,0x00
- },
- {DisableLCD24bpp + LCDPolarity,
- 928, 525, 800, 480, 40, 13, 48, 3,
- 0x52,0xC5,0x20,0x14,0x0A,0x02,0x00
- },
- {DisableLCD24bpp + LCDPolarity + (LCDPolarity << 8),
- 800, 525, 640, 480, 16, 10, 96, 2,
- 0x1B,0xE1,0x20,0x04,0x0A,0x02,0xC8
- }
-
+struct XGI21_LVDSCapStruct XGI21_LCDCapList[] = {
+ {DisableLCD24bpp + LCDPolarity,
+ 2160, 1250, 1600, 1200, 64, 1, 192, 3,
+ 0x70, 0x24, 0x20, 0x04, 0x0A, 0x02, 0xC8
+ },
+ {DisableLCD24bpp + LCDPolarity,
+ 1688, 1066, 1280, 1024, 48, 1, 112, 3,
+ 0x70, 0x44, 0x20, 0x04, 0x0A, 0x02, 0xC8
+ },
+ {DisableLCD24bpp + LCDPolarity + (LCDPolarity << 8),
+ 1344, 806, 1024, 768, 24, 3, 136, 6,
+ 0x6C, 0x65, 0x20, 0x04, 0x0A, 0x02, 0xC8
+ },
+ {DisableLCD24bpp + LCDPolarity,
+ 1056, 628, 800, 600, 40, 1, 128, 4,
+ 0x42, 0xE2, 0x20, 0x14, 0x0A, 0x02, 0x00
+ },
+ {DisableLCD24bpp + LCDPolarity,
+ 928, 525, 800, 480, 40, 13, 48, 3,
+ 0x52, 0xC5, 0x20, 0x14, 0x0A, 0x02, 0x00
+ },
+ {DisableLCD24bpp + LCDPolarity + (LCDPolarity << 8),
+ 800, 525, 640, 480, 16, 10, 96, 2,
+ 0x1B, 0xE1, 0x20, 0x04, 0x0A, 0x02, 0xC8
+ }
};
-static struct XGI_Ext2Struct XGI330_RefIndex[] =
-{
-{Support32Bpp + SupportAllCRT2 + SyncPN, RES320x200, VCLK25_175, 0x00,0x10,0x59, 320, 200},/* 00 */
-{Support32Bpp + SupportAllCRT2 + SyncPN, RES320x200, VCLK25_175, 0x00,0x10,0x00, 320, 400},/* 01 */
-{Support32Bpp + SupportAllCRT2 + SyncNN, RES320x240, VCLK25_175, 0x04,0x20,0x50, 320, 240},/* 02 */
-{Support32Bpp + SupportAllCRT2 + SyncPP, RES400x300, VCLK40, 0x05,0x32,0x51, 400, 300},/* 03 */
-{Support32Bpp + NoSupportTV + SyncNN + SupportTV1024, RES512x384, VCLK65, 0x06,0x43,0x52, 512, 384},/* 04 */
-{Support32Bpp + SupportAllCRT2 + SyncPN, RES640x400, VCLK25_175, 0x00,0x14,0x2f, 640, 400},/* 05 */
-{Support32Bpp + SupportAllCRT2 + SyncNN, RES640x480x60, VCLK25_175, 0x04,0x24,0x2e, 640, 480},/* 06 640x480x60Hz (LCD 640x480x60z) */
-{Support32Bpp + NoSupportHiVisionTV + SyncNN, RES640x480x72, VCLK31_5, 0x04,0x24,0x2e, 640, 480},/* 07 640x480x72Hz (LCD 640x480x70Hz) */
-{Support32Bpp + NoSupportHiVisionTV + SyncNN, RES640x480x75, VCLK31_5, 0x47,0x24,0x2e, 640, 480},/* 08 640x480x75Hz (LCD 640x480x75Hz) */
-{Support32Bpp + SupportRAMDAC2 + SyncNN, RES640x480x85, VCLK36, 0x8A,0x24,0x2e, 640, 480},/* 09 640x480x85Hz */
-{Support32Bpp + SupportRAMDAC2 + SyncPN, RES640x480x100, VCLK43_163, 0x00,0x24,0x2e, 640, 480},/* 0a 640x480x100Hz */
-{Support32Bpp + SupportRAMDAC2 + SyncPN, RES640x480x120, VCLK52_406, 0x00,0x24,0x2e, 640, 480},/* 0b 640x480x120Hz */
-{Support32Bpp + SupportRAMDAC2 + SyncPN, RES640x480x160, VCLK72_852, 0x00,0x24,0x2e, 640, 480},/* 0c 640x480x160Hz */
-{Support32Bpp + SupportRAMDAC2 + SyncNN, RES640x480x200, VCLK86_6, 0x00,0x24,0x2e, 640, 480},/* 0d 640x480x200Hz */
-{Support32Bpp + NoSupportLCD + SyncPP, RES800x600x56, VCLK36, 0x05,0x36,0x6a, 800, 600},/* 0e 800x600x56Hz */
-{Support32Bpp + NoSupportTV + SyncPP, RES800x600x60, VCLK40, 0x05,0x36,0x6a, 800, 600},/* 0f 800x600x60Hz (LCD 800x600x60Hz) */
-{Support32Bpp + NoSupportHiVisionTV + SyncPP, RES800x600x72, VCLK50, 0x48,0x36,0x6a, 800, 600},/* 10 800x600x72Hz (LCD 800x600x70Hz) */
-{Support32Bpp + NoSupportHiVisionTV + SyncPP, RES800x600x75, VCLK49_5, 0x8B,0x36,0x6a, 800, 600},/* 11 800x600x75Hz (LCD 800x600x75Hz) */
-{Support32Bpp + SupportRAMDAC2 + SyncPP, RES800x600x85, VCLK56_25, 0x00,0x36,0x6a, 800, 600},/* 12 800x600x85Hz */
-{Support32Bpp + SupportRAMDAC2 + SyncPN, RES800x600x100, VCLK68_179, 0x00,0x36,0x6a, 800, 600},/* 13 800x600x100Hz */
-{Support32Bpp + SupportRAMDAC2 + SyncPN, RES800x600x120, VCLK83_95, 0x00,0x36,0x6a, 800, 600},/* 14 800x600x120Hz */
-{Support32Bpp + SupportRAMDAC2 + SyncPN, RES800x600x160, VCLK116_406,0x00,0x36,0x6a, 800, 600},/* 15 800x600x160Hz */
-{Support32Bpp + InterlaceMode + SyncPP, RES1024x768x43, VCLK44_9, 0x00,0x47,0x37,1024, 768},/* 16 1024x768x43Hz */
-{Support32Bpp + NoSupportTV + SyncNN + SupportTV1024, RES1024x768x60, VCLK65, 0x06,0x47,0x37,1024, 768},/* 17 1024x768x60Hz (LCD 1024x768x60Hz) */
-{Support32Bpp + NoSupportHiVisionTV + SyncNN, RES1024x768x70, VCLK75, 0x49,0x47,0x37,1024, 768},/* 18 1024x768x70Hz (LCD 1024x768x70Hz) */
-{Support32Bpp + NoSupportHiVisionTV + SyncPP, RES1024x768x75, VCLK78_75, 0x00,0x47,0x37,1024, 768},/* 19 1024x768x75Hz (LCD 1024x768x75Hz) */
-{Support32Bpp + SupportRAMDAC2 + SyncPP, RES1024x768x85, VCLK94_5, 0x8C,0x47,0x37,1024, 768},/* 1a 1024x768x85Hz */
-{Support32Bpp + SupportRAMDAC2 + SyncPN, RES1024x768x100, VCLK113_309,0x00,0x47,0x37,1024, 768},/* 1b 1024x768x100Hz */
-{Support32Bpp + SupportRAMDAC2 + SyncPN, RES1024x768x120, VCLK139_054,0x00,0x47,0x37,1024, 768},/* 1c 1024x768x120Hz */
-{Support32Bpp + SupportLCD + SyncPP, RES1280x960x60, VCLK108_2, 0x08,0x58,0x7b,1280, 960},/* 1d 1280x960x60Hz */
-{Support32Bpp + InterlaceMode + SyncPP, RES1280x1024x43, VCLK78_75, 0x00,0x58,0x3a,1280,1024},/* 1e 1280x1024x43Hz */
-{Support32Bpp + NoSupportTV + SyncPP, RES1280x1024x60, VCLK108_2, 0x07,0x58,0x3a,1280,1024},/* 1f 1280x1024x60Hz (LCD 1280x1024x60Hz) */
-{Support32Bpp + NoSupportTV + SyncPP, RES1280x1024x75, VCLK135_5, 0x00,0x58,0x3a,1280,1024},/* 20 1280x1024x75Hz (LCD 1280x1024x75Hz) */
-{Support32Bpp + SyncPP, RES1280x1024x85, VCLK157_5, 0x00,0x58,0x3a,1280,1024},/* 21 1280x1024x85Hz */
-{Support32Bpp + SupportLCD + SyncPP + SupportCRT2in301C, RES1600x1200x60, VCLK162, 0x09,0x7A,0x3c,1600,1200},/* 22 1600x1200x60Hz */
-{Support32Bpp + SyncPP + SupportCRT2in301C, RES1600x1200x65, VCLK175, 0x00,0x69,0x3c,1600,1200},/* 23 1600x1200x65Hz */
-{Support32Bpp + SyncPP + SupportCRT2in301C, RES1600x1200x70, VCLK189, 0x00,0x69,0x3c,1600,1200},/* 24 1600x1200x70Hz */
-{Support32Bpp + SyncPP + SupportCRT2in301C, RES1600x1200x75, VCLK202_5, 0x00,0x69,0x3c,1600,1200},/* 25 1600x1200x75Hz */
-{Support32Bpp + SyncPP, RES1600x1200x85, VCLK229_5, 0x00,0x69,0x3c,1600,1200},/* 26 1600x1200x85Hz */
-{Support32Bpp + SyncPP, RES1600x1200x100,VCLK269_655,0x00,0x69,0x3c,1600,1200},/* 27 1600x1200x100Hz */
-{Support32Bpp + SyncPP, RES1600x1200x120,VCLK323_586,0x00,0x69,0x3c,1600,1200},/* 28 1600x1200x120Hz */
-{Support32Bpp + SupportLCD + SyncNP, RES1920x1440x60, VCLK234, 0x00,0x00,0x68,1920,1440},/* 29 1920x1440x60Hz */
-{Support32Bpp + SyncPN, RES1920x1440x65, VCLK254_817,0x00,0x00,0x68,1920,1440},/* 2a 1920x1440x65Hz */
-{Support32Bpp + SyncPN, RES1920x1440x70, VCLK277_015,0x00,0x00,0x68,1920,1440},/* 2b 1920x1440x70Hz */
-{Support32Bpp + SyncPN, RES1920x1440x75, VCLK291_132,0x00,0x00,0x68,1920,1440},/* 2c 1920x1440x75Hz */
-{Support32Bpp + SyncPN, RES1920x1440x85, VCLK330_615,0x00,0x00,0x68,1920,1440},/* 2d 1920x1440x85Hz */
-{Support16Bpp + SyncPN, RES1920x1440x100,VCLK388_631,0x00,0x00,0x68,1920,1440},/* 2e 1920x1440x100Hz */
-{Support32Bpp + SupportLCD + SyncPN, RES2048x1536x60, VCLK266_952,0x00,0x00,0x6c,2048,1536},/* 2f 2048x1536x60Hz */
-{Support32Bpp + SyncPN, RES2048x1536x65, VCLK291_766,0x00,0x00,0x6c,2048,1536},/* 30 2048x1536x65Hz */
-{Support32Bpp + SyncPN, RES2048x1536x70, VCLK315_195,0x00,0x00,0x6c,2048,1536},/* 31 2048x1536x70Hz */
-{Support32Bpp + SyncPN, RES2048x1536x75, VCLK340_477,0x00,0x00,0x6c,2048,1536},/* 32 2048x1536x75Hz */
-{Support16Bpp + SyncPN, RES2048x1536x85, VCLK375_847,0x00,0x00,0x6c,2048,1536},/* 33 2048x1536x85Hz */
-{Support32Bpp + SupportHiVisionTV + SupportRAMDAC2 + SyncPP + SupportYPbPr, RES800x480x60, VCLK39_77, 0x08,0x00,0x70, 800, 480},/* 34 800x480x60Hz */
-{Support32Bpp + SupportRAMDAC2 + SyncPP, RES800x480x75, VCLK49_5, 0x08,0x00,0x70, 800, 480},/* 35 800x480x75Hz */
-{Support32Bpp + SupportRAMDAC2 + SyncPP, RES800x480x85, VCLK56_25, 0x08,0x00,0x70, 800, 480},/* 36 800x480x85Hz */
-{Support32Bpp + SupportHiVisionTV + SupportRAMDAC2 + SyncPP + SupportYPbPr, RES1024x576x60, VCLK65, 0x09,0x00,0x71,1024, 576},/* 37 1024x576x60Hz */
-{Support32Bpp + SupportRAMDAC2 + SyncPP, RES1024x576x75, VCLK78_75, 0x09,0x00,0x71,1024, 576},/* 38 1024x576x75Hz */
-{Support32Bpp + SupportRAMDAC2 + SyncPP, RES1024x576x85, VCLK94_5, 0x09,0x00,0x71,1024, 576},/* 39 1024x576x85Hz */
-{Support32Bpp + SupportHiVisionTV + SupportRAMDAC2 + SyncPP + SupportYPbPr, RES1280x720x60, VCLK108_2, 0x0A,0x00,0x75,1280, 720},/* 3a 1280x720x60Hz */
-{Support32Bpp + SupportRAMDAC2 + SyncPP, RES1280x720x75, VCLK135_5, 0x0A,0x00,0x75,1280, 720},/* 3b 1280x720x75Hz */
-{Support32Bpp + SupportRAMDAC2 + SyncPP, RES1280x720x85, VCLK157_5, 0x0A,0x00,0x75,1280, 720},/* 3c 1280x720x85Hz */
-{Support32Bpp + SupportTV + SyncNN, RES720x480x60, VCLK28_322, 0x06,0x00,0x31, 720, 480},/* 3d 720x480x60Hz */
-{Support32Bpp + SupportTV + SyncPP, RES720x576x56, VCLK36, 0x06,0x00,0x32, 720, 576},/* 3e 720x576x56Hz */
-{Support32Bpp + InterlaceMode + NoSupportLCD + SyncPP, RES856x480x79I, VCLK35_2, 0x00,0x00,0x00, 856, 480},/* 3f 856x480x79I */
-{Support32Bpp + NoSupportLCD + SyncNN, RES856x480x60, VCLK35_2, 0x00,0x00,0x00, 856, 480},/* 40 856x480x60Hz */
-{Support32Bpp + NoSupportHiVisionTV + SyncPP, RES1280x768x60, VCLK79_411, 0x08,0x48,0x23,1280, 768},/* 41 1280x768x60Hz */
-{Support32Bpp + NoSupportHiVisionTV + SyncPP, RES1400x1050x60, VCLK122_61, 0x08,0x69,0x26,1400,1050},/* 42 1400x1050x60Hz */
-{Support32Bpp + SupportRAMDAC2 + SyncPP, RES1152x864x60, VCLK80_350, 0x37,0x00,0x20,1152, 864},/* 43 1152x864x60Hz */
-{Support32Bpp + SupportRAMDAC2 + SyncPP, RES1152x864x75, VCLK107_385,0x37,0x00,0x20,1152, 864},/* 44 1152x864x75Hz */
-{Support32Bpp + SupportLCD + SupportRAMDAC2 + SyncPP, RES1280x960x75, VCLK125_999,0x3A,0x88,0x7b,1280, 960},/* 45 1280x960x75Hz */
-{Support32Bpp + SupportLCD + SupportRAMDAC2 + SyncPP, RES1280x960x85, VCLK148_5, 0x0A,0x88,0x7b,1280, 960},/* 46 1280x960x85Hz */
-{Support32Bpp + SupportLCD + SupportRAMDAC2 + SyncPP, RES1280x960x120, VCLK217_325,0x3A,0x88,0x7b,1280, 960},/* 47 1280x960x120Hz */
-{Support32Bpp + SupportRAMDAC2 + SyncPN, RES1024x768x160, VCLK139_054,0x30,0x47,0x37,1024, 768},/* 48 1024x768x160Hz */
+static struct XGI_Ext2Struct XGI330_RefIndex[] = {
+ {Support32Bpp + SupportAllCRT2 + SyncPN, RES320x200, VCLK25_175,
+ 0x00, 0x10, 0x59, 320, 200},/* 00 */
+ {Support32Bpp + SupportAllCRT2 + SyncPN, RES320x200, VCLK25_175,
+ 0x00, 0x10, 0x00, 320, 400},/* 01 */
+ {Support32Bpp + SupportAllCRT2 + SyncNN, RES320x240, VCLK25_175,
+ 0x04, 0x20, 0x50, 320, 240},/* 02 */
+ {Support32Bpp + SupportAllCRT2 + SyncPP, RES400x300, VCLK40,
+ 0x05, 0x32, 0x51, 400, 300},/* 03 */
+ {Support32Bpp + NoSupportTV + SyncNN + SupportTV1024, RES512x384,
+ VCLK65, 0x06, 0x43, 0x52, 512, 384},/* 04 */
+ {Support32Bpp + SupportAllCRT2 + SyncPN, RES640x400, VCLK25_175,
+ 0x00, 0x14, 0x2f, 640, 400},/* 05 */
+ {Support32Bpp + SupportAllCRT2 + SyncNN, RES640x480x60, VCLK25_175,
+ 0x04, 0x24, 0x2e, 640, 480},/* 06 640x480x60Hz (LCD 640x480x60z) */
+ {Support32Bpp + NoSupportHiVisionTV + SyncNN, RES640x480x72, VCLK31_5,
+ 0x04, 0x24, 0x2e, 640, 480},/* 07 640x480x72Hz (LCD 640x480x70Hz) */
+ {Support32Bpp + NoSupportHiVisionTV + SyncNN, RES640x480x75, VCLK31_5,
+ 0x47, 0x24, 0x2e, 640, 480},/* 08 640x480x75Hz (LCD 640x480x75Hz) */
+ {Support32Bpp + SupportRAMDAC2 + SyncNN, RES640x480x85, VCLK36,
+ 0x8A, 0x24, 0x2e, 640, 480},/* 09 640x480x85Hz */
+ {Support32Bpp + SupportRAMDAC2 + SyncPN, RES640x480x100, VCLK43_163,
+ 0x00, 0x24, 0x2e, 640, 480},/* 0a 640x480x100Hz */
+ {Support32Bpp + SupportRAMDAC2 + SyncPN, RES640x480x120, VCLK52_406,
+ 0x00, 0x24, 0x2e, 640, 480},/* 0b 640x480x120Hz */
+ {Support32Bpp + SupportRAMDAC2 + SyncPN, RES640x480x160, VCLK72_852,
+ 0x00, 0x24, 0x2e, 640, 480},/* 0c 640x480x160Hz */
+ {Support32Bpp + SupportRAMDAC2 + SyncNN, RES640x480x200, VCLK86_6,
+ 0x00, 0x24, 0x2e, 640, 480},/* 0d 640x480x200Hz */
+ {Support32Bpp + NoSupportLCD + SyncPP, RES800x600x56, VCLK36,
+ 0x05, 0x36, 0x6a, 800, 600},/* 0e 800x600x56Hz */
+ {Support32Bpp + NoSupportTV + SyncPP, RES800x600x60, VCLK40,
+ 0x05, 0x36, 0x6a, 800, 600},/* 0f 800x600x60Hz (LCD 800x600x60Hz) */
+ {Support32Bpp + NoSupportHiVisionTV + SyncPP, RES800x600x72, VCLK50,
+ 0x48, 0x36, 0x6a, 800, 600},/* 10 800x600x72Hz (LCD 800x600x70Hz) */
+ {Support32Bpp + NoSupportHiVisionTV + SyncPP, RES800x600x75, VCLK49_5,
+ 0x8B, 0x36, 0x6a, 800, 600},/* 11 800x600x75Hz (LCD 800x600x75Hz) */
+ {Support32Bpp + SupportRAMDAC2 + SyncPP, RES800x600x85, VCLK56_25,
+ 0x00, 0x36, 0x6a, 800, 600},/* 12 800x600x85Hz */
+ {Support32Bpp + SupportRAMDAC2 + SyncPN, RES800x600x100, VCLK68_179,
+ 0x00, 0x36, 0x6a, 800, 600},/* 13 800x600x100Hz */
+ {Support32Bpp + SupportRAMDAC2 + SyncPN, RES800x600x120, VCLK83_95,
+ 0x00, 0x36, 0x6a, 800, 600},/* 14 800x600x120Hz */
+ {Support32Bpp + SupportRAMDAC2 + SyncPN, RES800x600x160, VCLK116_406,
+ 0x00, 0x36, 0x6a, 800, 600},/* 15 800x600x160Hz */
+ {Support32Bpp + InterlaceMode + SyncPP, RES1024x768x43, VCLK44_9,
+ 0x00, 0x47, 0x37, 1024, 768},/* 16 1024x768x43Hz */
+ /* 17 1024x768x60Hz (LCD 1024x768x60Hz) */
+ {Support32Bpp + NoSupportTV + SyncNN + SupportTV1024, RES1024x768x60,
+ VCLK65, 0x06, 0x47, 0x37, 1024, 768},
+ {Support32Bpp + NoSupportHiVisionTV + SyncNN, RES1024x768x70, VCLK75,
+ 0x49, 0x47, 0x37, 1024, 768},/* 18 1024x768x70Hz (LCD 1024x768x70Hz) */
+ {Support32Bpp + NoSupportHiVisionTV + SyncPP, RES1024x768x75, VCLK78_75,
+ 0x00, 0x47, 0x37, 1024, 768},/* 19 1024x768x75Hz (LCD 1024x768x75Hz) */
+ {Support32Bpp + SupportRAMDAC2 + SyncPP, RES1024x768x85, VCLK94_5,
+ 0x8C, 0x47, 0x37, 1024, 768},/* 1a 1024x768x85Hz */
+ {Support32Bpp + SupportRAMDAC2 + SyncPN, RES1024x768x100, VCLK113_309,
+ 0x00, 0x47, 0x37, 1024, 768},/* 1b 1024x768x100Hz */
+ {Support32Bpp + SupportRAMDAC2 + SyncPN, RES1024x768x120, VCLK139_054,
+ 0x00, 0x47, 0x37, 1024, 768},/* 1c 1024x768x120Hz */
+ {Support32Bpp + SupportLCD + SyncPP, RES1280x960x60, VCLK108_2,
+ 0x08, 0x58, 0x7b, 1280, 960},/* 1d 1280x960x60Hz */
+ {Support32Bpp + InterlaceMode + SyncPP, RES1280x1024x43, VCLK78_75,
+ 0x00, 0x58, 0x3a, 1280, 1024},/* 1e 1280x1024x43Hz */
+ {Support32Bpp + NoSupportTV + SyncPP, RES1280x1024x60, VCLK108_2,
+ 0x07, 0x58, 0x3a, 1280, 1024},/*1f 1280x1024x60Hz (LCD 1280x1024x60Hz)*/
+ {Support32Bpp + NoSupportTV + SyncPP, RES1280x1024x75, VCLK135_5,
+ 0x00, 0x58, 0x3a, 1280, 1024},/*20 1280x1024x75Hz (LCD 1280x1024x75Hz)*/
+ {Support32Bpp + SyncPP, RES1280x1024x85, VCLK157_5,
+ 0x00, 0x58, 0x3a, 1280, 1024},/* 21 1280x1024x85Hz */
+ /* 22 1600x1200x60Hz */
+ {Support32Bpp + SupportLCD + SyncPP + SupportCRT2in301C,
+ RES1600x1200x60, VCLK162, 0x09, 0x7A, 0x3c, 1600, 1200},
+ {Support32Bpp + SyncPP + SupportCRT2in301C, RES1600x1200x65, VCLK175,
+ 0x00, 0x69, 0x3c, 1600, 1200},/* 23 1600x1200x65Hz */
+ {Support32Bpp + SyncPP + SupportCRT2in301C, RES1600x1200x70, VCLK189,
+ 0x00, 0x69, 0x3c, 1600, 1200},/* 24 1600x1200x70Hz */
+ {Support32Bpp + SyncPP + SupportCRT2in301C, RES1600x1200x75, VCLK202_5,
+ 0x00, 0x69, 0x3c, 1600, 1200},/* 25 1600x1200x75Hz */
+ {Support32Bpp + SyncPP, RES1600x1200x85, VCLK229_5,
+ 0x00, 0x69, 0x3c, 1600, 1200},/* 26 1600x1200x85Hz */
+ {Support32Bpp + SyncPP, RES1600x1200x100, VCLK269_655,
+ 0x00, 0x69, 0x3c, 1600, 1200},/* 27 1600x1200x100Hz */
+ {Support32Bpp + SyncPP, RES1600x1200x120, VCLK323_586,
+ 0x00, 0x69, 0x3c, 1600, 1200},/* 28 1600x1200x120Hz */
+ {Support32Bpp + SupportLCD + SyncNP, RES1920x1440x60, VCLK234,
+ 0x00, 0x00, 0x68, 1920, 1440},/* 29 1920x1440x60Hz */
+ {Support32Bpp + SyncPN, RES1920x1440x65, VCLK254_817,
+ 0x00, 0x00, 0x68, 1920, 1440},/* 2a 1920x1440x65Hz */
+ {Support32Bpp + SyncPN, RES1920x1440x70, VCLK277_015,
+ 0x00, 0x00, 0x68, 1920, 1440},/* 2b 1920x1440x70Hz */
+ {Support32Bpp + SyncPN, RES1920x1440x75, VCLK291_132,
+ 0x00, 0x00, 0x68, 1920, 1440},/* 2c 1920x1440x75Hz */
+ {Support32Bpp + SyncPN, RES1920x1440x85, VCLK330_615,
+ 0x00, 0x00, 0x68, 1920, 1440},/* 2d 1920x1440x85Hz */
+ {Support16Bpp + SyncPN, RES1920x1440x100, VCLK388_631,
+ 0x00, 0x00, 0x68, 1920, 1440},/* 2e 1920x1440x100Hz */
+ {Support32Bpp + SupportLCD + SyncPN, RES2048x1536x60, VCLK266_952,
+ 0x00, 0x00, 0x6c, 2048, 1536},/* 2f 2048x1536x60Hz */
+ {Support32Bpp + SyncPN, RES2048x1536x65, VCLK291_766,
+ 0x00, 0x00, 0x6c, 2048, 1536},/* 30 2048x1536x65Hz */
+ {Support32Bpp + SyncPN, RES2048x1536x70, VCLK315_195,
+ 0x00, 0x00, 0x6c, 2048, 1536},/* 31 2048x1536x70Hz */
+ {Support32Bpp + SyncPN, RES2048x1536x75, VCLK340_477,
+ 0x00, 0x00, 0x6c, 2048, 1536},/* 32 2048x1536x75Hz */
+ {Support16Bpp + SyncPN, RES2048x1536x85, VCLK375_847,
+ 0x00, 0x00, 0x6c, 2048, 1536},/* 33 2048x1536x85Hz */
+ {Support32Bpp + SupportHiVisionTV + SupportRAMDAC2 +
+ SyncPP + SupportYPbPr, RES800x480x60, VCLK39_77,
+ 0x08, 0x00, 0x70, 800, 480},/* 34 800x480x60Hz */
+ {Support32Bpp + SupportRAMDAC2 + SyncPP, RES800x480x75, VCLK49_5,
+ 0x08, 0x00, 0x70, 800, 480},/* 35 800x480x75Hz */
+ {Support32Bpp + SupportRAMDAC2 + SyncPP, RES800x480x85, VCLK56_25,
+ 0x08, 0x00, 0x70, 800, 480},/* 36 800x480x85Hz */
+ {Support32Bpp + SupportHiVisionTV + SupportRAMDAC2 +
+ SyncPP + SupportYPbPr, RES1024x576x60, VCLK65,
+ 0x09, 0x00, 0x71, 1024, 576},/* 37 1024x576x60Hz */
+ {Support32Bpp + SupportRAMDAC2 + SyncPP, RES1024x576x75, VCLK78_75,
+ 0x09, 0x00, 0x71, 1024, 576},/* 38 1024x576x75Hz */
+ {Support32Bpp + SupportRAMDAC2 + SyncPP, RES1024x576x85, VCLK94_5,
+ 0x09, 0x00, 0x71, 1024, 576},/* 39 1024x576x85Hz */
+ {Support32Bpp + SupportHiVisionTV + SupportRAMDAC2 +
+ SyncPP + SupportYPbPr, RES1280x720x60, VCLK108_2,
+ 0x0A, 0x00, 0x75, 1280, 720},/* 3a 1280x720x60Hz*/
+ {Support32Bpp + SupportRAMDAC2 + SyncPP, RES1280x720x75, VCLK135_5,
+ 0x0A, 0x00, 0x75, 1280, 720},/* 3b 1280x720x75Hz */
+ {Support32Bpp + SupportRAMDAC2 + SyncPP, RES1280x720x85, VCLK157_5,
+ 0x0A, 0x00, 0x75, 1280, 720},/* 3c 1280x720x85Hz */
+ {Support32Bpp + SupportTV + SyncNN, RES720x480x60, VCLK28_322,
+ 0x06, 0x00, 0x31, 720, 480},/* 3d 720x480x60Hz */
+ {Support32Bpp + SupportTV + SyncPP, RES720x576x56, VCLK36,
+ 0x06, 0x00, 0x32, 720, 576},/* 3e 720x576x56Hz */
+ {Support32Bpp + InterlaceMode + NoSupportLCD + SyncPP, RES856x480x79I,
+ VCLK35_2, 0x00, 0x00, 0x00, 856, 480},/* 3f 856x480x79I */
+ {Support32Bpp + NoSupportLCD + SyncNN, RES856x480x60, VCLK35_2,
+ 0x00, 0x00, 0x00, 856, 480},/* 40 856x480x60Hz */
+ {Support32Bpp + NoSupportHiVisionTV + SyncPP, RES1280x768x60,
+ VCLK79_411, 0x08, 0x48, 0x23, 1280, 768},/* 41 1280x768x60Hz */
+ {Support32Bpp + NoSupportHiVisionTV + SyncPP, RES1400x1050x60,
+ VCLK122_61, 0x08, 0x69, 0x26, 1400, 1050},/* 42 1400x1050x60Hz */
+ {Support32Bpp + SupportRAMDAC2 + SyncPP, RES1152x864x60, VCLK80_350,
+ 0x37, 0x00, 0x20, 1152, 864},/* 43 1152x864x60Hz */
+ {Support32Bpp + SupportRAMDAC2 + SyncPP, RES1152x864x75, VCLK107_385,
+ 0x37, 0x00, 0x20, 1152, 864},/* 44 1152x864x75Hz */
+ {Support32Bpp + SupportLCD + SupportRAMDAC2 + SyncPP, RES1280x960x75,
+ VCLK125_999, 0x3A, 0x88, 0x7b, 1280, 960},/* 45 1280x960x75Hz */
+ {Support32Bpp + SupportLCD + SupportRAMDAC2 + SyncPP, RES1280x960x85,
+ VCLK148_5, 0x0A, 0x88, 0x7b, 1280, 960},/* 46 1280x960x85Hz */
+ {Support32Bpp + SupportLCD + SupportRAMDAC2 + SyncPP, RES1280x960x120,
+ VCLK217_325, 0x3A, 0x88, 0x7b, 1280, 960},/* 47 1280x960x120Hz */
+ {Support32Bpp + SupportRAMDAC2 + SyncPN, RES1024x768x160, VCLK139_054,
+ 0x30, 0x47, 0x37, 1024, 768},/* 48 1024x768x160Hz */
};
#if 0
-static struct XGI330_VCLKDataStruct XGI330_VCLKData[] =
-{
- { 0x1b,0xe1, 25}, /* 0x0 */
- { 0x4e,0xe4, 28}, /* 0x1 */
- { 0x57,0xe4, 31}, /* 0x2 */
- { 0xc3,0xc8, 36}, /* 0x3 */
- { 0x42,0xe2, 40}, /* 0x4 */
- { 0xfe,0xcd, 43}, /* 0x5 */
- { 0x5d,0xc4, 44}, /* 0x6 */
- { 0x52,0xe2, 49}, /* 0x7 */
- { 0x53,0xe2, 50}, /* 0x8 */
- { 0x74,0x67, 52}, /* 0x9 */
- { 0x6d,0x66, 56}, /* 0xa */
- { 0x6c,0xc3, 65}, /* 0xb */
- { 0x46,0x44, 67}, /* 0xc */
- { 0xb1,0x46, 68}, /* 0xd */
- { 0xd3,0x4a, 72}, /* 0xe */
- { 0x29,0x61, 75}, /* 0xf */
- { 0x6e,0x46, 76}, /* 0x10 */
- { 0x2b,0x61, 78}, /* 0x11 */
- { 0x31,0x42, 79}, /* 0x12 */
- { 0xab,0x44, 83}, /* 0x13 */
- { 0x46,0x25, 84}, /* 0x14 */
- { 0x78,0x29, 86}, /* 0x15 */
- { 0x62,0x44, 94}, /* 0x16 */
- { 0x2b,0x41,104}, /* 0x17 */
- { 0x3a,0x23,105}, /* 0x18 */
- { 0x70,0x44,108}, /* 0x19 */
- { 0x3c,0x23,109}, /* 0x1a */
- { 0x5e,0x43,113}, /* 0x1b */
- { 0xbc,0x44,116}, /* 0x1c */
- { 0xe0,0x46,132}, /* 0x1d */
- { 0x54,0x42,135}, /* 0x1e */
- { 0xea,0x2a,139}, /* 0x1f */
- { 0x41,0x22,157}, /* 0x20 */
- { 0x70,0x24,162}, /* 0x21 */
- { 0x30,0x21,175}, /* 0x22 */
- { 0x4e,0x22,189}, /* 0x23 */
- { 0xde,0x26,194}, /* 0x24 */
- { 0x62,0x06,202}, /* 0x25 */
- { 0x3f,0x03,229}, /* 0x26 */
- { 0xb8,0x06,234}, /* 0x27 */
- { 0x34,0x02,253}, /* 0x28 */
- { 0x58,0x04,255}, /* 0x29 */
- { 0x24,0x01,265}, /* 0x2a */
- { 0x9b,0x02,267}, /* 0x2b */
- { 0x70,0x05,270}, /* 0x2c */
- { 0x25,0x01,272}, /* 0x2d */
- { 0x9c,0x02,277}, /* 0x2e */
- { 0x27,0x01,286}, /* 0x2f */
- { 0x3c,0x02,291}, /* 0x30 */
- { 0xef,0x0a,292}, /* 0x31 */
- { 0xf6,0x0a,310}, /* 0x32 */
- { 0x95,0x01,315}, /* 0x33 */
- { 0xf0,0x09,324}, /* 0x34 */
- { 0xfe,0x0a,331}, /* 0x35 */
- { 0xf3,0x09,332}, /* 0x36 */
- { 0xea,0x08,340}, /* 0x37 */
- { 0xe8,0x07,376}, /* 0x38 */
- { 0xde,0x06,389}, /* 0x39 */
- { 0x52,0x2a, 54}, /* 0x3a */
- { 0x52,0x6a, 27}, /* 0x3b */
- { 0x62,0x24, 70}, /* 0x3c */
- { 0x62,0x64, 70}, /* 0x3d */
- { 0xa8,0x4c, 30}, /* 0x3e */
- { 0x20,0x26, 33}, /* 0x3f */
- { 0x31,0xc2, 39}, /* 0x40 */
- { 0x60,0x36, 30}, /* 0x41 */
- { 0x40,0x4A, 28}, /* 0x42 */
- { 0x9F,0x46, 44}, /* 0x43 */
- { 0x97,0x2C, 26}, /* 0x44 */
- { 0x44,0xE4, 25}, /* 0x45 */
- { 0x7E,0x32, 47}, /* 0x46 */
- { 0x08,0x24, 31}, /* 0x47 */
- { 0x97,0x2c, 26}, /* 0x48 */
- { 0xCE,0x3c, 39}, /* 0x49 */
- { 0x52,0x4A, 36}, /* 0x4a */
- { 0x2C,0x61, 95}, /* 0x4b */
- { 0x78,0x27,108}, /* 0x4c */
- { 0x66,0x43,123}, /* 0x4d */
- { 0x2c,0x61, 80}, /* 0x4e */
- { 0x3b,0x61,108} /* 0x4f */
+static struct XGI330_VCLKDataStruct XGI330_VCLKData[] = {
+ {0x1b, 0xe1, 25}, /* 0x0 */
+ {0x4e, 0xe4, 28}, /* 0x1 */
+ {0x57, 0xe4, 31}, /* 0x2 */
+ {0xc3, 0xc8, 36}, /* 0x3 */
+ {0x42, 0xe2, 40}, /* 0x4 */
+ {0xfe, 0xcd, 43}, /* 0x5 */
+ {0x5d, 0xc4, 44}, /* 0x6 */
+ {0x52, 0xe2, 49}, /* 0x7 */
+ {0x53, 0xe2, 50}, /* 0x8 */
+ {0x74, 0x67, 52}, /* 0x9 */
+ {0x6d, 0x66, 56}, /* 0xa */
+ {0x6c, 0xc3, 65}, /* 0xb */
+ {0x46, 0x44, 67}, /* 0xc */
+ {0xb1, 0x46, 68}, /* 0xd */
+ {0xd3, 0x4a, 72}, /* 0xe */
+ {0x29, 0x61, 75}, /* 0xf */
+ {0x6e, 0x46, 76}, /* 0x10 */
+ {0x2b, 0x61, 78}, /* 0x11 */
+ {0x31, 0x42, 79}, /* 0x12 */
+ {0xab, 0x44, 83}, /* 0x13 */
+ {0x46, 0x25, 84}, /* 0x14 */
+ {0x78, 0x29, 86}, /* 0x15 */
+ {0x62, 0x44, 94}, /* 0x16 */
+ {0x2b, 0x41, 104}, /* 0x17 */
+ {0x3a, 0x23, 105}, /* 0x18 */
+ {0x70, 0x44, 108}, /* 0x19 */
+ {0x3c, 0x23, 109}, /* 0x1a */
+ {0x5e, 0x43, 113}, /* 0x1b */
+ {0xbc, 0x44, 116}, /* 0x1c */
+ {0xe0, 0x46, 132}, /* 0x1d */
+ {0x54, 0x42, 135}, /* 0x1e */
+ {0xea, 0x2a, 139}, /* 0x1f */
+ {0x41, 0x22, 157}, /* 0x20 */
+ {0x70, 0x24, 162}, /* 0x21 */
+ {0x30, 0x21, 175}, /* 0x22 */
+ {0x4e, 0x22, 189}, /* 0x23 */
+ {0xde, 0x26, 194}, /* 0x24 */
+ {0x62, 0x06, 202}, /* 0x25 */
+ {0x3f, 0x03, 229}, /* 0x26 */
+ {0xb8, 0x06, 234}, /* 0x27 */
+ {0x34, 0x02, 253}, /* 0x28 */
+ {0x58, 0x04, 255}, /* 0x29 */
+ {0x24, 0x01, 265}, /* 0x2a */
+ {0x9b, 0x02, 267}, /* 0x2b */
+ {0x70, 0x05, 270}, /* 0x2c */
+ {0x25, 0x01, 272}, /* 0x2d */
+ {0x9c, 0x02, 277}, /* 0x2e */
+ {0x27, 0x01, 286}, /* 0x2f */
+ {0x3c, 0x02, 291}, /* 0x30 */
+ {0xef, 0x0a, 292}, /* 0x31 */
+ {0xf6, 0x0a, 310}, /* 0x32 */
+ {0x95, 0x01, 315}, /* 0x33 */
+ {0xf0, 0x09, 324}, /* 0x34 */
+ {0xfe, 0x0a, 331}, /* 0x35 */
+ {0xf3, 0x09, 332}, /* 0x36 */
+ {0xea, 0x08, 340}, /* 0x37 */
+ {0xe8, 0x07, 376}, /* 0x38 */
+ {0xde, 0x06, 389}, /* 0x39 */
+ {0x52, 0x2a, 54}, /* 0x3a */
+ {0x52, 0x6a, 27}, /* 0x3b */
+ {0x62, 0x24, 70}, /* 0x3c */
+ {0x62, 0x64, 70}, /* 0x3d */
+ {0xa8, 0x4c, 30}, /* 0x3e */
+ {0x20, 0x26, 33}, /* 0x3f */
+ {0x31, 0xc2, 39}, /* 0x40 */
+ {0x60, 0x36, 30}, /* 0x41 */
+ {0x40, 0x4A, 28}, /* 0x42 */
+ {0x9F, 0x46, 44}, /* 0x43 */
+ {0x97, 0x2C, 26}, /* 0x44 */
+ {0x44, 0xE4, 25}, /* 0x45 */
+ {0x7E, 0x32, 47}, /* 0x46 */
+ {0x08, 0x24, 31}, /* 0x47 */
+ {0x97, 0x2c, 26}, /* 0x48 */
+ {0xCE, 0x3c, 39}, /* 0x49 */
+ {0x52, 0x4A, 36}, /* 0x4a */
+ {0x2C, 0x61, 95}, /* 0x4b */
+ {0x78, 0x27, 108}, /* 0x4c */
+ {0x66, 0x43, 123}, /* 0x4d */
+ {0x2c, 0x61, 80}, /* 0x4e */
+ {0x3b, 0x61, 108} /* 0x4f */
};
-static struct XGI_VBVCLKDataStruct XGI330_VBVCLKData[] =
-{
- { 0x1b,0xe1, 25}, /* 0x0 */
- { 0x4e,0xe4, 28}, /* 0x1 */
- { 0x57,0xe4, 31}, /* 0x2 */
- { 0xc3,0xc8, 36}, /* 0x3 */
- { 0x42,0x47, 40}, /* 0x4 */
- { 0xfe,0xcd, 43}, /* 0x5 */
- { 0x5d,0xc4, 44}, /* 0x6 */
- { 0x52,0x47, 49}, /* 0x7 */
- { 0x53,0x47, 50}, /* 0x8 */
- { 0x74,0x67, 52}, /* 0x9 */
- { 0x6d,0x66, 56}, /* 0xa */
- { 0x5a,0x64, 65}, /* 0xb */
- { 0x46,0x44, 67}, /* 0xc */
- { 0xb1,0x46, 68}, /* 0xd */
- { 0xd3,0x4a, 72}, /* 0xe */
- { 0x29,0x61, 75}, /* 0xf */
- { 0x6d,0x46, 75}, /* 0x10 */
- { 0x41,0x43, 78}, /* 0x11 */
- { 0x31,0x42, 79}, /* 0x12 */
- { 0xab,0x44, 83}, /* 0x13 */
- { 0x46,0x25, 84}, /* 0x14 */
- { 0x78,0x29, 86}, /* 0x15 */
- { 0x62,0x44, 94}, /* 0x16 */
- { 0x2b,0x22,104}, /* 0x17 */
- { 0x49,0x24,105}, /* 0x18 */
- { 0xf8,0x2f,108}, /* 0x19 */
- { 0x3c,0x23,109}, /* 0x1a */
- { 0x5e,0x43,113}, /* 0x1b */
- { 0xbc,0x44,116}, /* 0x1c */
- { 0xe0,0x46,132}, /* 0x1d */
- { 0xd4,0x28,135}, /* 0x1e */
- { 0xea,0x2a,139}, /* 0x1f */
- { 0x41,0x22,157}, /* 0x20 */
- { 0x70,0x24,162}, /* 0x21 */
- { 0x30,0x21,175}, /* 0x22 */
- { 0x4e,0x22,189}, /* 0x23 */
- { 0xde,0x26,194}, /* 0x24 */
- { 0x70,0x07,202}, /* 0x25 */
- { 0x3f,0x03,229}, /* 0x26 */
- { 0xb8,0x06,234}, /* 0x27 */
- { 0x34,0x02,253}, /* 0x28 */
- { 0x58,0x04,255}, /* 0x29 */
- { 0x24,0x01,265}, /* 0x2a */
- { 0x9b,0x02,267}, /* 0x2b */
- { 0x70,0x05,270}, /* 0x2c */
- { 0x25,0x01,272}, /* 0x2d */
- { 0x9c,0x02,277}, /* 0x2e */
- { 0x27,0x01,286}, /* 0x2f */
- { 0x3c,0x02,291}, /* 0x30 */
- { 0xef,0x0a,292}, /* 0x31 */
- { 0xf6,0x0a,310}, /* 0x32 */
- { 0x95,0x01,315}, /* 0x33 */
- { 0xf0,0x09,324}, /* 0x34 */
- { 0xfe,0x0a,331}, /* 0x35 */
- { 0xf3,0x09,332}, /* 0x36 */
- { 0xea,0x08,340}, /* 0x37 */
- { 0xe8,0x07,376}, /* 0x38 */
- { 0xde,0x06,389}, /* 0x39 */
- { 0x52,0x2a, 54}, /* 0x3a */
- { 0x52,0x6a, 27}, /* 0x3b */
- { 0x62,0x24, 70}, /* 0x3c */
- { 0x62,0x64, 70}, /* 0x3d */
- { 0xa8,0x4c, 30}, /* 0x3e */
- { 0x20,0x26, 33}, /* 0x3f */
- { 0x31,0xc2, 39}, /* 0x40 */
- { 0x2e,0x48, 25}, /* 0x41 */
- { 0x24,0x46, 25}, /* 0x42 */
- { 0x26,0x64, 28}, /* 0x43 */
- { 0x37,0x64, 40}, /* 0x44 */
- { 0xa1,0x42,108}, /* 0x45 */
- { 0x37,0x61,100}, /* 0x46 */
- { 0x78,0x27,108}, /* 0x47 */
- { 0x5e,0x64,68}, /* 0x48 chiawen for fuj1280x768*/
- { 0x70,0x44,108}, /* 0x49 chiawen for 1400x1050*/
+static struct XGI_VBVCLKDataStruct XGI330_VBVCLKData[] = {
+ {0x1b, 0xe1, 25}, /* 0x0 */
+ {0x4e, 0xe4, 28}, /* 0x1 */
+ {0x57, 0xe4, 31}, /* 0x2 */
+ {0xc3, 0xc8, 36}, /* 0x3 */
+ {0x42, 0x47, 40}, /* 0x4 */
+ {0xfe, 0xcd, 43}, /* 0x5 */
+ {0x5d, 0xc4, 44}, /* 0x6 */
+ {0x52, 0x47, 49}, /* 0x7 */
+ {0x53, 0x47, 50}, /* 0x8 */
+ {0x74, 0x67, 52}, /* 0x9 */
+ {0x6d, 0x66, 56}, /* 0xa */
+ {0x5a, 0x64, 65}, /* 0xb */
+ {0x46, 0x44, 67}, /* 0xc */
+ {0xb1, 0x46, 68}, /* 0xd */
+ {0xd3, 0x4a, 72}, /* 0xe */
+ {0x29, 0x61, 75}, /* 0xf */
+ {0x6d, 0x46, 75}, /* 0x10 */
+ {0x41, 0x43, 78}, /* 0x11 */
+ {0x31, 0x42, 79}, /* 0x12 */
+ {0xab, 0x44, 83}, /* 0x13 */
+ {0x46, 0x25, 84}, /* 0x14 */
+ {0x78, 0x29, 86}, /* 0x15 */
+ {0x62, 0x44, 94}, /* 0x16 */
+ {0x2b, 0x22, 104}, /* 0x17 */
+ {0x49, 0x24, 105}, /* 0x18 */
+ {0xf8, 0x2f, 108}, /* 0x19 */
+ {0x3c, 0x23, 109}, /* 0x1a */
+ {0x5e, 0x43, 113}, /* 0x1b */
+ {0xbc, 0x44, 116}, /* 0x1c */
+ {0xe0, 0x46, 132}, /* 0x1d */
+ {0xd4, 0x28, 135}, /* 0x1e */
+ {0xea, 0x2a, 139}, /* 0x1f */
+ {0x41, 0x22, 157}, /* 0x20 */
+ {0x70, 0x24, 162}, /* 0x21 */
+ {0x30, 0x21, 175}, /* 0x22 */
+ {0x4e, 0x22, 189}, /* 0x23 */
+ {0xde, 0x26, 194}, /* 0x24 */
+ {0x70, 0x07, 202}, /* 0x25 */
+ {0x3f, 0x03, 229}, /* 0x26 */
+ {0xb8, 0x06, 234}, /* 0x27 */
+ {0x34, 0x02, 253}, /* 0x28 */
+ {0x58, 0x04, 255}, /* 0x29 */
+ {0x24, 0x01, 265}, /* 0x2a */
+ {0x9b, 0x02, 267}, /* 0x2b */
+ {0x70, 0x05, 270}, /* 0x2c */
+ {0x25, 0x01, 272}, /* 0x2d */
+ {0x9c, 0x02, 277}, /* 0x2e */
+ {0x27, 0x01, 286}, /* 0x2f */
+ {0x3c, 0x02, 291}, /* 0x30 */
+ {0xef, 0x0a, 292}, /* 0x31 */
+ {0xf6, 0x0a, 310}, /* 0x32 */
+ {0x95, 0x01, 315}, /* 0x33 */
+ {0xf0, 0x09, 324}, /* 0x34 */
+ {0xfe, 0x0a, 331}, /* 0x35 */
+ {0xf3, 0x09, 332}, /* 0x36 */
+ {0xea, 0x08, 340}, /* 0x37 */
+ {0xe8, 0x07, 376}, /* 0x38 */
+ {0xde, 0x06, 389}, /* 0x39 */
+ {0x52, 0x2a, 54}, /* 0x3a */
+ {0x52, 0x6a, 27}, /* 0x3b */
+ {0x62, 0x24, 70}, /* 0x3c */
+ {0x62, 0x64, 70}, /* 0x3d */
+ {0xa8, 0x4c, 30}, /* 0x3e */
+ {0x20, 0x26, 33}, /* 0x3f */
+ {0x31, 0xc2, 39}, /* 0x40 */
+ {0x2e, 0x48, 25}, /* 0x41 */
+ {0x24, 0x46, 25}, /* 0x42 */
+ {0x26, 0x64, 28}, /* 0x43 */
+ {0x37, 0x64, 40}, /* 0x44 */
+ {0xa1, 0x42, 108}, /* 0x45 */
+ {0x37, 0x61, 100}, /* 0x46 */
+ {0x78, 0x27, 108}, /* 0x47 */
+ {0x5e, 0x64, 68}, /* 0x48 chiawen for fuj1280x768*/
+ {0x70, 0x44, 108}, /* 0x49 chiawen for 1400x1050*/
};
#endif
static unsigned char XGI330_ScreenOffset[] = {
- 0x14, 0x19, 0x20, 0x28, 0x32, 0x40,
- 0x50, 0x64, 0x78, 0x80, 0x2d, 0x35,
- 0x57, 0x48};
-
-static struct XGI_StResInfoStruct XGI330_StResInfo[] =
-{
- { 640,400},
- { 640,350},
- { 720,400},
- { 720,350},
- { 640,480}
+ 0x14, 0x19, 0x20, 0x28, 0x32, 0x40,
+ 0x50, 0x64, 0x78, 0x80, 0x2d, 0x35,
+ 0x57, 0x48
};
-static struct XGI_ModeResInfoStruct XGI330_ModeResInfo[] =
-{
- { 320, 200, 8, 8},
- { 320, 240, 8, 8},
- { 320, 400, 8, 8},
- { 400, 300, 8, 8},
- { 512, 384, 8, 8},
- { 640, 400, 8,16},
- { 640, 480, 8,16},
- { 800, 600, 8,16},
- { 1024, 768, 8,16},
- { 1280,1024, 8,16},
- { 1600,1200, 8,16},
- { 1920,1440, 8,16},
- { 2048,1536, 8,16},
- { 720, 480, 8,16},
- { 720, 576, 8,16},
- { 1280, 960, 8,16},
- { 800, 480, 8,16},
- { 1024, 576, 8,16},
- { 1280, 720, 8,16},
- { 856, 480, 8,16},
- { 1280, 768, 8,16},
- { 1400,1050, 8,16},
- { 1152, 864, 8,16}
+static struct XGI_StResInfoStruct XGI330_StResInfo[] = {
+ {640, 400},
+ {640, 350},
+ {720, 400},
+ {720, 350},
+ {640, 480}
+};
+
+static struct XGI_ModeResInfoStruct XGI330_ModeResInfo[] = {
+ { 320, 200, 8, 8},
+ { 320, 240, 8, 8},
+ { 320, 400, 8, 8},
+ { 400, 300, 8, 8},
+ { 512, 384, 8, 8},
+ { 640, 400, 8, 16},
+ { 640, 480, 8, 16},
+ { 800, 600, 8, 16},
+ {1024, 768, 8, 16},
+ {1280, 1024, 8, 16},
+ {1600, 1200, 8, 16},
+ {1920, 1440, 8, 16},
+ {2048, 1536, 8, 16},
+ { 720, 480, 8, 16},
+ { 720, 576, 8, 16},
+ {1280, 960, 8, 16},
+ { 800, 480, 8, 16},
+ {1024, 576, 8, 16},
+ {1280, 720, 8, 16},
+ { 856, 480, 8, 16},
+ {1280, 768, 8, 16},
+ {1400, 1050, 8, 16},
+ {1152, 864, 8, 16}
};
static unsigned char XGI330_OutputSelect = 0x40;
@@ -3441,22 +3593,22 @@
#if 0
static unsigned char XGI330New_SR15[8][8] = {
-{0x0,0x4,0x60,0x60},
-{0xf,0xf,0xf,0xf},
-{0xba,0xba,0xba,0xba},
-{0xa9,0xa9,0xac,0xac},
-{0xa0,0xa0,0xa0,0xa8},
-{0x0,0x0,0x2,0x2},
-{0x30,0x30,0x40,0x40},
-{0x0,0xa5,0xfb,0xf6}
+ { 0x0, 0x4, 0x60, 0x60},
+ { 0xf, 0xf, 0xf, 0xf},
+ {0xba, 0xba, 0xba, 0xba},
+ {0xa9, 0xa9, 0xac, 0xac},
+ {0xa0, 0xa0, 0xa0, 0xa8},
+ { 0x0, 0x0, 0x2, 0x2},
+ {0x30, 0x30, 0x40, 0x40},
+ { 0x0, 0xa5, 0xfb, 0xf6}
};
static unsigned char XGI330New_CR40[5][8] = {
-{0x77,0x77,0x44,0x44},
-{0x77,0x77,0x44,0x44},
-{0x0,0x0,0x0,0x0},
-{0x5b,0x5b,0xab,0xab},
-{0x0,0x0,0xf0,0xf8}
+ {0x77, 0x77, 0x44, 0x44},
+ {0x77, 0x77, 0x44, 0x44},
+ { 0x0, 0x0, 0x0, 0x0},
+ {0x5b, 0x5b, 0xab, 0xab},
+ { 0x0, 0x0, 0xf0, 0xf8}
};
#endif
@@ -3509,7 +3661,9 @@
static unsigned char XG27_CR97 = 0xC1 ;
static unsigned char XG27_SR36 = 0x30 ;
static unsigned char XG27_CR8F = 0x0C ;
-static unsigned char XG27_CRD0[] = {0, 0, 0, 0, 0, 0, 0, 0x82, 0x00, 0x66, 0x01, 0x00};
+static unsigned char XG27_CRD0[] = {
+ 0, 0, 0, 0, 0, 0, 0, 0x82, 0x00, 0x66, 0x01, 0x00
+};
static unsigned char XG27_CRDE[] = {0, 0};
static unsigned char XG27_SR40 = 0x04 ;
static unsigned char XG27_SR41 = 0x00 ;
@@ -3522,871 +3676,660 @@
static unsigned char XGI330_CHTVVCLKOPAL[] = {0x00};
-static unsigned char XGI7007_CHTVVCLKUNTSC[] = {CH7007TVVCLK30_2,
- CH7007TVVCLK30_2,
- CH7007TVVCLK30_2,
- CH7007TVVCLK30_2,
- CH7007TVVCLK28_1,
- CH7007TVVCLK47_8
- };
-
-static unsigned char XGI7007_CHTVVCLKONTSC[] = {CH7007TVVCLK26_4,
- CH7007TVVCLK26_4,
- CH7007TVVCLK26_4,
- CH7007TVVCLK26_4,
- CH7007TVVCLK24_6,
- CH7007TVVCLK43_6
- };
-
-static unsigned char XGI7007_CHTVVCLKUPAL[] = {CH7007TVVCLK31_5,
- CH7007TVVCLK31_5,
- CH7007TVVCLK31_5,
- CH7007TVVCLK31_5,
- CH7007TVVCLK26_2,
- CH7007TVVCLK39
- };
-
-static unsigned char XGI7007_CHTVVCLKOPAL[] = {CH7007TVVCLK31_5,
- CH7007TVVCLK31_5,
- CH7007TVVCLK31_5,
- CH7007TVVCLK31_5,
- CH7007TVVCLK26_2,
- CH7007TVVCLK36
- };
-
-static struct XGI330_VCLKDataStruct XGI_CH7007VCLKData[] =
-{
- { 0x60,0x36,30}, /* 0 30.2 MHZ */
- { 0x40,0x4A,28}, /* 1 28.19 MHZ */
- { 0x9F,0x46,44}, /* 2 43.6 MHZ */
- { 0x97,0x2C,26}, /* 3 26.4 MHZ */
- { 0x44,0xE4,25}, /* 4 24.6 MHZ */
- { 0x7E,0x32,47}, /* 5 47.832 MHZ */
- { 0x8A,0x24,31}, /* 6 31.5 MHZ */
- { 0x97,0x2C,26}, /* 7 26.2 MHZ */
- { 0xCE,0x3C,39}, /* 8 39 MHZ */
- { 0x52,0x4A,36}, /* 9 36 MHZ */
- { 0xFF,0x00,0 } /* End mark */
+static unsigned char XGI7007_CHTVVCLKUNTSC[] = {
+ CH7007TVVCLK30_2,
+ CH7007TVVCLK30_2,
+ CH7007TVVCLK30_2,
+ CH7007TVVCLK30_2,
+ CH7007TVVCLK28_1,
+ CH7007TVVCLK47_8
};
-static struct XGI330_VCLKDataStruct XGI_VCLKData[] =
-{
- /* SR2B,SR2C,SR2D */
- { 0x1B,0xE1,25 },/* 00 (25.175MHz) */
+static unsigned char XGI7007_CHTVVCLKONTSC[] = {
+ CH7007TVVCLK26_4,
+ CH7007TVVCLK26_4,
+ CH7007TVVCLK26_4,
+ CH7007TVVCLK26_4,
+ CH7007TVVCLK24_6,
+ CH7007TVVCLK43_6
+};
- { 0x4E,0xE4,28 },/* 01 (28.322MHz) */
+static unsigned char XGI7007_CHTVVCLKUPAL[] = {
+ CH7007TVVCLK31_5,
+ CH7007TVVCLK31_5,
+ CH7007TVVCLK31_5,
+ CH7007TVVCLK31_5,
+ CH7007TVVCLK26_2,
+ CH7007TVVCLK39
+};
- { 0x57,0xE4,31 },/* 02 (31.500MHz) */
+static unsigned char XGI7007_CHTVVCLKOPAL[] = {
+ CH7007TVVCLK31_5,
+ CH7007TVVCLK31_5,
+ CH7007TVVCLK31_5,
+ CH7007TVVCLK31_5,
+ CH7007TVVCLK26_2,
+ CH7007TVVCLK36
+};
- { 0xC3,0xC8,36 },/* 03 (36.000MHz) */
+static struct XGI330_VCLKDataStruct XGI_CH7007VCLKData[] = {
+ {0x60, 0x36, 30}, /* 0 30.2 MHZ */
+ {0x40, 0x4A, 28}, /* 1 28.19 MHZ */
+ {0x9F, 0x46, 44}, /* 2 43.6 MHZ */
+ {0x97, 0x2C, 26}, /* 3 26.4 MHZ */
+ {0x44, 0xE4, 25}, /* 4 24.6 MHZ */
+ {0x7E, 0x32, 47}, /* 5 47.832 MHZ */
+ {0x8A, 0x24, 31}, /* 6 31.5 MHZ */
+ {0x97, 0x2C, 26}, /* 7 26.2 MHZ */
+ {0xCE, 0x3C, 39}, /* 8 39 MHZ */
+ {0x52, 0x4A, 36}, /* 9 36 MHZ */
+ {0xFF, 0x00, 0} /* End mark */
+};
- { 0x42,0xE2,40 },/* 04 (40.000MHz) */
-
- { 0xFE,0xCD,43 },/* 05 (43.163MHz) */
-
- { 0x5D,0xC4,44 },/* 06 (44.900MHz) */
-
- { 0x52,0xE2,49 },/* 07 (49.500MHz) */
-
- { 0x53,0xE2,50 },/* 08 (50.000MHz) */
-
- { 0x74,0x67,52 },/* 09 (52.406MHz) */
-
- { 0x6D,0x66,56 },/* 0A (56.250MHz) */
-
- { 0x6C,0xC3,65 },/* 0B (65.000MHz) */
-
- { 0x46,0x44,67 },/* 0C (67.765MHz) */
-
- { 0xB1,0x46,68 },/* 0D (68.179MHz) */
-
- { 0xD3,0x4A,72 },/* 0E (72.852MHz) */
-
- { 0x29,0x61,75 },/* 0F (75.000MHz) */
-
- { 0x6E,0x46,76 },/* 10 (75.800MHz) */
-
- { 0x2B,0x61,78 },/* 11 (78.750MHz) */
-
- { 0x31,0x42,79 },/* 12 (79.411MHz) */
-
- { 0xAB,0x44,83 },/* 13 (83.950MHz) */
-
- { 0x46,0x25,84 },/* 14 (84.800MHz) */
-
- { 0x78,0x29,86 },/* 15 (86.600MHz) */
-
- { 0x62,0x44,94 },/* 16 (94.500MHz) */
-
- { 0x2B,0x41,104 },/* 17 (104.998MHz) */
-
- { 0x3A,0x23,105 },/* 18 (105.882MHz) */
-
- { 0x70,0x44,108 },/* 19 (107.862MHz) */
-
- { 0x3C,0x23,109 },/* 1A (109.175MHz) */
-
- { 0x5E,0x43,113 },/* 1B (113.309MHz) */
-
- { 0xBC,0x44,116 },/* 1C (116.406MHz) */
-
- { 0xE0,0x46,132 },/* 1D (132.258MHz) */
-
- { 0x54,0x42,135 },/* 1E (135.500MHz) */
-
- { 0x9C,0x22,139 },/* 1F (139.275MHz) */
-
- { 0x41,0x22,157 },/* 20 (157.500MHz) */
-
- { 0x70,0x24,162 },/* 21 (161.793MHz) */
-
- { 0x30,0x21,175 },/* 22 (175.000MHz) */
-
- { 0x4E,0x22,189 },/* 23 (188.520MHz) */
-
- { 0xDE,0x26,194 },/* 24 (194.400MHz) */
-
- { 0x62,0x06,202 },/* 25 (202.500MHz) */
-
- { 0x3F,0x03,229 },/* 26 (229.500MHz) */
-
- { 0xB8,0x06,234 },/* 27 (233.178MHz) */
-
- { 0x34,0x02,253 },/* 28 (252.699MHz) */
-
- { 0x58,0x04,255 },/* 29 (254.817MHz) */
-
- { 0x24,0x01,265 },/* 2A (265.728MHz) */
-
- { 0x9B,0x02,267 },/* 2B (266.952MHz) */
-
- { 0x70,0x05,270 },/* 2C (269.65567MHz) */
-
- { 0x25,0x01,272 },/* 2D (272.04199MHz) */
-
- { 0x9C,0x02,277 },/* 2E (277.015MHz) */
-
- { 0x27,0x01,286 },/* 2F (286.359985MHz) */
-
- { 0xB3,0x04,291 },/* 30 (291.13266MHz) */
-
- { 0xBC,0x05,292 },/* 31 (291.766MHz) */
-
- { 0xF6,0x0A,310 },/* 32 (309.789459MHz) */
-
- { 0x95,0x01,315 },/* 33 (315.195MHz) */
-
- { 0xF0,0x09,324 },/* 34 (323.586792MHz) */
-
- { 0xFE,0x0A,331 },/* 35 (330.615631MHz) */
-
- { 0xF3,0x09,332 },/* 36 (332.177612MHz) */
-
- { 0x5E,0x03,340 },/* 37 (340.477MHz) */
-
- { 0xE8,0x07,376 },/* 38 (375.847504MHz) */
-
- { 0xDE, 0x06,389 },/* 39 (388.631439MHz) */
-
- { 0x52,0x2A,54 },/* 3A (54.000MHz) */
-
- { 0x52,0x6A,27 },/* 3B (27.000MHz) */
-
- { 0x62,0x24,70 },/* 3C (70.874991MHz) */
-
- { 0x62,0x64,70 },/* 3D (70.1048912MHz) */
-
- { 0xA8,0x4C,30 },/* 3E (30.1048912MHz) */
-
- { 0x20,0x26,33 },/* 3F (33.7499957MHz) */
-
- { 0x31,0xc2,39 },/* 40 (39.77MHz) */
-
- { 0x11,0x21,30 },/* 41 (30MHz) }// NTSC 1024X768 */
-
- { 0x2E,0x48,25 },/* 42 (25.175MHz) }// ScaleLCD */
-
- { 0x24,0x46,25 },/* 43 (25.175MHz) */
-
- { 0x26,0x64,28 },/* 44 (28.322MHz) */
-
- { 0x37,0x64,40 },/* 45 (40.000MHz) */
-
- { 0xA1,0x42,108 },/* 46 (95.000MHz) }// QVGA */
-
- { 0x37,0x61,100 },/* 47 (100.00MHz) */
-
- { 0x78,0x27,108 },/* 48 (108.200MHz) */
-
- { 0xBF,0xC8,35 },/* 49 (35.2MHz) */
-
- { 0x66,0x43,123 },/* 4A (122.61Mhz) */
-
- { 0x2C,0x61,80 },/* 4B (80.350Mhz) */
-
- { 0x3B,0x61,108 },/* 4C (107.385Mhz) */
-
-
-/* { 0x60,0x36,30 },// 4D (30.200MHz) }// No use
-
- { 0x60,0x36,30 },// 4E (30.200MHz) }// No use
-
- { 0x60,0x36,30 },// 4F (30.200MHz) }// No use
-
- { 0x60,0x36,30 },// 50 (30.200MHz) }// CHTV
-
- { 0x40,0x4A,28 },// 51 (28.190MHz)
-
- { 0x9F,0x46,44 },// 52 (43.600MHz)
-
- { 0x97,0x2C,26 },// 53 (26.400MHz)
-
- { 0x44,0xE4,25 },// 54 (24.600MHz)
-
- { 0x7E,0x32,47 },// 55 (47.832MHz)
-
- { 0x8A,0x24,31 },// 56 (31.500MHz)
-
- { 0x97,0x2C,26 },// 57 (26.200MHz)
-
- { 0xCE,0x3C,39 },// 58 (39.000MHz)
-
- { 0x52,0x4A,36 },// 59 (36.000MHz)
-
-*/
- { 0x69,0x61,191 }, /* 4D (190.96MHz ) */
- { 0x4F,0x22,192 }, /* 4E (192.069MHz) */
- { 0x28,0x26,322 }, /* 4F (322.273MHz) */
- { 0x5C,0x6B,27 }, /* 50 (27.74HMz) */
- { 0x57,0x24,126 }, /* 51 (125.999MHz) */
- { 0x5C,0x42,148 }, /* 52 (148.5MHz) */
- { 0x42,0x61,120 }, /* 53 (120.839MHz) */
- { 0x62,0x61,178 }, /* 54 (178.992MHz) */
- { 0x59,0x22,217 }, /* 55 (217.325MHz) */
- { 0x29,0x01,300 }, /* 56 (299.505Mhz) */
- { 0x52,0x63,74 }, /* 57 (74.25MHz) */
-
-
- { 0xFF,0x00,0 }/* End mark */
- } ;
-
-static struct XGI330_VCLKDataStruct XGI_VBVCLKData[] =
-{
- { 0x1B,0xE1,25 },/* 00 (25.175MHz) */
-
- { 0x4E,0xE4,28 },/* 01 (28.322MHz) */
-
- { 0x57,0xE4,31 },/* 02 (31.500MHz) */
-
- { 0xC3,0xC8,36 },/* 03 (36.000MHz) */
-
- { 0x42,0x47,40 },/* 04 (40.000MHz) */
-
- { 0xFE,0xCD,43 },/* 05 (43.163MHz) */
-
- { 0x5D,0xC4,44 },/* 06 (44.900MHz) */
-
- { 0x52,0x47,49 },/* 07 (49.500MHz) */
-
- { 0x53,0x47,50 },/* 08 (50.000MHz) */
-
- { 0x74,0x67,52 },/* 09 (52.406MHz) */
-
- { 0x6D,0x66,56 },/* 0A (56.250MHz) */
-
- { 0x35,0x62,65 },/* 0B (65.000MHz) */
-
- { 0x46,0x44,67 },/* 0C (67.765MHz) */
-
- { 0xB1,0x46,68 },/* 0D (68.179MHz) */
-
- { 0xD3,0x4A,72 },/* 0E (72.852MHz) */
-
- { 0x29,0x61,75 },/* 0F (75.000MHz) */
-
- { 0x6D,0x46,75 },/* 10 (75.800MHz) */
-
- { 0x41,0x43,78 },/* 11 (78.750MHz) */
-
- { 0x31,0x42,79 },/* 12 (79.411MHz) */
-
- { 0xAB,0x44,83 },/* 13 (83.950MHz) */
-
- { 0x46,0x25,84 },/* 14 (84.800MHz) */
-
- { 0x78,0x29,86 },/* 15 (86.600MHz) */
-
- { 0x62,0x44,94 },/* 16 (94.500MHz) */
-
- { 0x2B,0x22,104 },/* 17 (104.998MHz) */
-
- { 0x49,0x24,105 },/* 18 (105.882MHz) */
-
- { 0xF8,0x2F,108 },/* 19 (108.279MHz) */
-
- { 0x3C,0x23,109 },/* 1A (109.175MHz) */
-
- { 0x5E,0x43,113 },/* 1B (113.309MHz) */
-
- { 0xBC,0x44,116 },/* 1C (116.406MHz) */
-
- { 0xE0,0x46,132 },/* 1D (132.258MHz) */
-
- { 0xD4,0x28,135 },/* 1E (135.220MHz) */
-
- { 0xEA,0x2A,139 },/* 1F (139.275MHz) */
-
- { 0x41,0x22,157 },/* 20 (157.500MHz) */
-
- { 0x70,0x24,162 },/* 21 (161.793MHz) */
-
- { 0x30,0x21,175 },/* 22 (175.000MHz) */
-
- { 0x4E,0x22,189 },/* 23 (188.520MHz) */
-
- { 0xDE,0x26,194 },/* 24 (194.400MHz) */
-
- { 0x70,0x07,202 },/* 25 (202.500MHz) */
-
- { 0x3F,0x03,229 },/* 26 (229.500MHz) */
-
- { 0xB8,0x06,234 },/* 27 (233.178MHz) */
-
- { 0x34,0x02,253 },/* 28 (252.699997 MHz) */
-
- { 0x58,0x04,255 },/* 29 (254.817MHz) */
-
- { 0x24,0x01,265 },/* 2A (265.728MHz) */
-
- { 0x9B,0x02,267 },/* 2B (266.952MHz) */
-
- { 0x70,0x05,270 },/* 2C (269.65567 MHz) */
-
- { 0x25,0x01,272 },/* 2D (272.041992 MHz) */
-
- { 0x9C,0x02,277 },/* 2E (277.015MHz) */
-
- { 0x27,0x01,286 },/* 2F (286.359985 MHz) */
-
- { 0x3C,0x02,291 },/* 30 (291.132660 MHz) */
-
- { 0xEF,0x0A,292 },/* 31 (291.766MHz) */
-
- { 0xF6,0x0A,310 },/* 32 (309.789459 MHz) */
-
- { 0x95,0x01,315 },/* 33 (315.195MHz) */
-
- { 0xF0,0x09,324 },/* 34 (323.586792 MHz) */
-
- { 0xFE,0x0A,331 },/* 35 (330.615631 MHz) */
-
- { 0xF3,0x09,332 },/* 36 (332.177612 MHz) */
-
- { 0xEA,0x08,340 },/* 37 (340.477MHz) */
-
- { 0xE8,0x07,376 },/* 38 (375.847504 MHz) */
-
- { 0xDE,0x06,389 },/* 39 (388.631439 MHz) */
-
- { 0x52,0x2A,54 },/* 3A (54.000MHz) */
-
- { 0x52,0x6A,27 },/* 3B (27.000MHz) */
-
-
- { 0x62,0x24,70 },/* 3C (70.874991MHz) */
-
-
- { 0x62,0x64,70 },/* 3D (70.1048912MHz) */
-
- { 0xA8,0x4C,30 },/* 3E (30.1048912MHz) */
-
- { 0x20,0x26,33 },/* 3F (33.7499957MHz) */
-
- { 0x31,0xc2,39 },/* 40 (39.77MHz) */
-
- { 0x11,0x21,30 },/* 41 (30MHz) }// NTSC 1024X768 */
-
- { 0x2E,0x48,25 },/* 42 (25.175MHz) }// ScaleLCD */
-
- { 0x24,0x46,25 },/* 43 (25.175MHz) */
-
- { 0x26,0x64,28 },/* 44 (28.322MHz) */
-
- { 0x37,0x64,40 },/* 45 (40.000MHz) */
-
- { 0xA1,0x42,108 },/* 46 (95.000MHz) }// QVGA */
-
- { 0x37,0x61,100 },/* 47 (100.00MHz) */
-
- { 0x78,0x27,108 },/* 48 (108.200MHz) */
-
- { 0xBF,0xC8,35 },/* 49 (35.2MHz) */
-
- { 0x66,0x43,123 },/* 4A (122.61Mhz) */
-
- { 0x2C,0x61,80 },/* 4B (80.350Mhz) */
-
- { 0x3B,0x61,108 },/* 4C (107.385Mhz) */
-
+static struct XGI330_VCLKDataStruct XGI_VCLKData[] = {
+ /* SR2B,SR2C,SR2D */
+ {0x1B, 0xE1, 25}, /* 00 (25.175MHz) */
+ {0x4E, 0xE4, 28}, /* 01 (28.322MHz) */
+ {0x57, 0xE4, 31}, /* 02 (31.500MHz) */
+ {0xC3, 0xC8, 36}, /* 03 (36.000MHz) */
+ {0x42, 0xE2, 40}, /* 04 (40.000MHz) */
+ {0xFE, 0xCD, 43}, /* 05 (43.163MHz) */
+ {0x5D, 0xC4, 44}, /* 06 (44.900MHz) */
+ {0x52, 0xE2, 49}, /* 07 (49.500MHz) */
+ {0x53, 0xE2, 50}, /* 08 (50.000MHz) */
+ {0x74, 0x67, 52}, /* 09 (52.406MHz) */
+ {0x6D, 0x66, 56}, /* 0A (56.250MHz) */
+ {0x6C, 0xC3, 65}, /* 0B (65.000MHz) */
+ {0x46, 0x44, 67}, /* 0C (67.765MHz) */
+ {0xB1, 0x46, 68}, /* 0D (68.179MHz) */
+ {0xD3, 0x4A, 72}, /* 0E (72.852MHz) */
+ {0x29, 0x61, 75}, /* 0F (75.000MHz) */
+ {0x6E, 0x46, 76}, /* 10 (75.800MHz) */
+ {0x2B, 0x61, 78}, /* 11 (78.750MHz) */
+ {0x31, 0x42, 79}, /* 12 (79.411MHz) */
+ {0xAB, 0x44, 83}, /* 13 (83.950MHz) */
+ {0x46, 0x25, 84}, /* 14 (84.800MHz) */
+ {0x78, 0x29, 86}, /* 15 (86.600MHz) */
+ {0x62, 0x44, 94}, /* 16 (94.500MHz) */
+ {0x2B, 0x41, 104}, /* 17 (104.998MHz) */
+ {0x3A, 0x23, 105}, /* 18 (105.882MHz) */
+ {0x70, 0x44, 108}, /* 19 (107.862MHz) */
+ {0x3C, 0x23, 109}, /* 1A (109.175MHz) */
+ {0x5E, 0x43, 113}, /* 1B (113.309MHz) */
+ {0xBC, 0x44, 116}, /* 1C (116.406MHz) */
+ {0xE0, 0x46, 132}, /* 1D (132.258MHz) */
+ {0x54, 0x42, 135}, /* 1E (135.500MHz) */
+ {0x9C, 0x22, 139}, /* 1F (139.275MHz) */
+ {0x41, 0x22, 157}, /* 20 (157.500MHz) */
+ {0x70, 0x24, 162}, /* 21 (161.793MHz) */
+ {0x30, 0x21, 175}, /* 22 (175.000MHz) */
+ {0x4E, 0x22, 189}, /* 23 (188.520MHz) */
+ {0xDE, 0x26, 194}, /* 24 (194.400MHz) */
+ {0x62, 0x06, 202}, /* 25 (202.500MHz) */
+ {0x3F, 0x03, 229}, /* 26 (229.500MHz) */
+ {0xB8, 0x06, 234}, /* 27 (233.178MHz) */
+ {0x34, 0x02, 253}, /* 28 (252.699MHz) */
+ {0x58, 0x04, 255}, /* 29 (254.817MHz) */
+ {0x24, 0x01, 265}, /* 2A (265.728MHz) */
+ {0x9B, 0x02, 267}, /* 2B (266.952MHz) */
+ {0x70, 0x05, 270}, /* 2C (269.65567MHz) */
+ {0x25, 0x01, 272}, /* 2D (272.04199MHz) */
+ {0x9C, 0x02, 277}, /* 2E (277.015MHz) */
+ {0x27, 0x01, 286}, /* 2F (286.359985MHz) */
+ {0xB3, 0x04, 291}, /* 30 (291.13266MHz) */
+ {0xBC, 0x05, 292}, /* 31 (291.766MHz) */
+ {0xF6, 0x0A, 310}, /* 32 (309.789459MHz) */
+ {0x95, 0x01, 315}, /* 33 (315.195MHz) */
+ {0xF0, 0x09, 324}, /* 34 (323.586792MHz) */
+ {0xFE, 0x0A, 331}, /* 35 (330.615631MHz) */
+ {0xF3, 0x09, 332}, /* 36 (332.177612MHz) */
+ {0x5E, 0x03, 340}, /* 37 (340.477MHz) */
+ {0xE8, 0x07, 376}, /* 38 (375.847504MHz) */
+ {0xDE, 0x06, 389}, /* 39 (388.631439MHz) */
+ {0x52, 0x2A, 54}, /* 3A (54.000MHz) */
+ {0x52, 0x6A, 27}, /* 3B (27.000MHz) */
+ {0x62, 0x24, 70}, /* 3C (70.874991MHz) */
+ {0x62, 0x64, 70}, /* 3D (70.1048912MHz) */
+ {0xA8, 0x4C, 30}, /* 3E (30.1048912MHz) */
+ {0x20, 0x26, 33}, /* 3F (33.7499957MHz) */
+ {0x31, 0xc2, 39}, /* 40 (39.77MHz) */
+ {0x11, 0x21, 30}, /* 41 (30MHz) }// NTSC 1024X768 */
+ {0x2E, 0x48, 25}, /* 42 (25.175MHz) }// ScaleLCD */
+ {0x24, 0x46, 25}, /* 43 (25.175MHz) */
+ {0x26, 0x64, 28}, /* 44 (28.322MHz) */
+ {0x37, 0x64, 40}, /* 45 (40.000MHz) */
+ {0xA1, 0x42, 108}, /* 46 (95.000MHz) }// QVGA */
+ {0x37, 0x61, 100}, /* 47 (100.00MHz) */
+ {0x78, 0x27, 108}, /* 48 (108.200MHz) */
+ {0xBF, 0xC8, 35}, /* 49 (35.2MHz) */
+ {0x66, 0x43, 123}, /* 4A (122.61Mhz) */
+ {0x2C, 0x61, 80}, /* 4B (80.350Mhz) */
+ {0x3B, 0x61, 108}, /* 4C (107.385Mhz) */
/*
- { 0x60,0x36,30 },// 4D (30.200MHz) }// No use
-
- { 0x60,0x36,30 },// 4E (30.200MHz) }// No use
-
- { 0x60,0x36,30 },// 4F (30.200MHz) }// No use
-
- { 0x60,0x36,30 },// 50 (30.200MHz) }// CHTV
-
- { 0x40,0x4A,28 },// 51 (28.190MHz)
-
- { 0x9F,0x46,44 },// 52 (43.600MHz)
-
- { 0x97,0x2C,26 },// 53 (26.400MHz)
-
- { 0x44,0xE4,25 },// 54 (24.600MHz)
-
- { 0x7E,0x32,47 },// 55 (47.832MHz)
-
- { 0x8A,0x24,31 },// 56 (31.500MHz)
-
- { 0x97,0x2C,26 },// 57 (26.200MHz)
-
- { 0xCE,0x3C,39 },// 58 (39.000MHz)
-
- { 0x52,0x4A,36 },// 59 (36.000MHz)
+ {0x60, 0x36, 30},// 4D (30.200MHz) }// No use
+ {0x60, 0x36, 30},// 4E (30.200MHz) }// No use
+ {0x60, 0x36, 30},// 4F (30.200MHz) }// No use
+ {0x60, 0x36, 30},// 50 (30.200MHz) }// CHTV
+ {0x40, 0x4A, 28},// 51 (28.190MHz)
+ {0x9F, 0x46, 44},// 52 (43.600MHz)
+ {0x97, 0x2C, 26},// 53 (26.400MHz)
+ {0x44, 0xE4, 25},// 54 (24.600MHz)
+ {0x7E, 0x32, 47},// 55 (47.832MHz)
+ {0x8A, 0x24, 31},// 56 (31.500MHz)
+ {0x97, 0x2C, 26},// 57 (26.200MHz)
+ {0xCE, 0x3C, 39},// 58 (39.000MHz)
+ {0x52, 0x4A, 36},// 59 (36.000MHz)
*/
- { 0x69,0x61,191 }, /* 4D (190.96MHz ) */
- { 0x4F,0x22,192 }, /* 4E (192.069MHz) */
- { 0x28,0x26,322 }, /* 4F (322.273MHz) */
- { 0x5C,0x6B,27 }, /* 50 (27.74HMz) */
- { 0x57,0x24,126 }, /* 51 (125.999MHz) */
- { 0x5C,0x42,148 }, /* 52 (148.5MHz) */
- { 0x42,0x61,120 }, /* 53 (120.839MHz) */
- { 0x62,0x61,178 }, /* 54 (178.992MHz) */
- { 0x59,0x22,217 }, /* 55 (217.325MHz) */
- { 0x29,0x01,300 }, /* 56 (299.505Mhz) */
- { 0x52,0x63,74 }, /* 57 (74.25MHz) */
+ {0x69, 0x61, 191}, /* 4D (190.96MHz ) */
+ {0x4F, 0x22, 192}, /* 4E (192.069MHz) */
+ {0x28, 0x26, 322}, /* 4F (322.273MHz) */
+ {0x5C, 0x6B, 27}, /* 50 (27.74HMz) */
+ {0x57, 0x24, 126}, /* 51 (125.999MHz) */
+ {0x5C, 0x42, 148}, /* 52 (148.5MHz) */
+ {0x42, 0x61, 120}, /* 53 (120.839MHz) */
+ {0x62, 0x61, 178}, /* 54 (178.992MHz) */
+ {0x59, 0x22, 217}, /* 55 (217.325MHz) */
+ {0x29, 0x01, 300}, /* 56 (299.505Mhz) */
+ {0x52, 0x63, 74}, /* 57 (74.25MHz) */
+ {0xFF, 0x00, 0} /* End mark */
+};
-
- { 0xFF,0x00,0 } /* End mark */
+static struct XGI330_VCLKDataStruct XGI_VBVCLKData[] = {
+ {0x1B, 0xE1, 25}, /* 00 (25.175MHz) */
+ {0x4E, 0xE4, 28}, /* 01 (28.322MHz) */
+ {0x57, 0xE4, 31}, /* 02 (31.500MHz) */
+ {0xC3, 0xC8, 36}, /* 03 (36.000MHz) */
+ {0x42, 0x47, 40}, /* 04 (40.000MHz) */
+ {0xFE, 0xCD, 43}, /* 05 (43.163MHz) */
+ {0x5D, 0xC4, 44}, /* 06 (44.900MHz) */
+ {0x52, 0x47, 49}, /* 07 (49.500MHz) */
+ {0x53, 0x47, 50}, /* 08 (50.000MHz) */
+ {0x74, 0x67, 52}, /* 09 (52.406MHz) */
+ {0x6D, 0x66, 56}, /* 0A (56.250MHz) */
+ {0x35, 0x62, 65}, /* 0B (65.000MHz) */
+ {0x46, 0x44, 67}, /* 0C (67.765MHz) */
+ {0xB1, 0x46, 68}, /* 0D (68.179MHz) */
+ {0xD3, 0x4A, 72}, /* 0E (72.852MHz) */
+ {0x29, 0x61, 75}, /* 0F (75.000MHz) */
+ {0x6D, 0x46, 75}, /* 10 (75.800MHz) */
+ {0x41, 0x43, 78}, /* 11 (78.750MHz) */
+ {0x31, 0x42, 79}, /* 12 (79.411MHz) */
+ {0xAB, 0x44, 83}, /* 13 (83.950MHz) */
+ {0x46, 0x25, 84}, /* 14 (84.800MHz) */
+ {0x78, 0x29, 86}, /* 15 (86.600MHz) */
+ {0x62, 0x44, 94}, /* 16 (94.500MHz) */
+ {0x2B, 0x22, 104}, /* 17 (104.998MHz) */
+ {0x49, 0x24, 105}, /* 18 (105.882MHz) */
+ {0xF8, 0x2F, 108}, /* 19 (108.279MHz) */
+ {0x3C, 0x23, 109}, /* 1A (109.175MHz) */
+ {0x5E, 0x43, 113}, /* 1B (113.309MHz) */
+ {0xBC, 0x44, 116}, /* 1C (116.406MHz) */
+ {0xE0, 0x46, 132}, /* 1D (132.258MHz) */
+ {0xD4, 0x28, 135}, /* 1E (135.220MHz) */
+ {0xEA, 0x2A, 139}, /* 1F (139.275MHz) */
+ {0x41, 0x22, 157}, /* 20 (157.500MHz) */
+ {0x70, 0x24, 162}, /* 21 (161.793MHz) */
+ {0x30, 0x21, 175}, /* 22 (175.000MHz) */
+ {0x4E, 0x22, 189}, /* 23 (188.520MHz) */
+ {0xDE, 0x26, 194}, /* 24 (194.400MHz) */
+ {0x70, 0x07, 202}, /* 25 (202.500MHz) */
+ {0x3F, 0x03, 229}, /* 26 (229.500MHz) */
+ {0xB8, 0x06, 234}, /* 27 (233.178MHz) */
+ {0x34, 0x02, 253}, /* 28 (252.699997 MHz) */
+ {0x58, 0x04, 255}, /* 29 (254.817MHz) */
+ {0x24, 0x01, 265}, /* 2A (265.728MHz) */
+ {0x9B, 0x02, 267}, /* 2B (266.952MHz) */
+ {0x70, 0x05, 270}, /* 2C (269.65567 MHz) */
+ {0x25, 0x01, 272}, /* 2D (272.041992 MHz) */
+ {0x9C, 0x02, 277}, /* 2E (277.015MHz) */
+ {0x27, 0x01, 286}, /* 2F (286.359985 MHz) */
+ {0x3C, 0x02, 291}, /* 30 (291.132660 MHz) */
+ {0xEF, 0x0A, 292}, /* 31 (291.766MHz) */
+ {0xF6, 0x0A, 310}, /* 32 (309.789459 MHz) */
+ {0x95, 0x01, 315}, /* 33 (315.195MHz) */
+ {0xF0, 0x09, 324}, /* 34 (323.586792 MHz) */
+ {0xFE, 0x0A, 331}, /* 35 (330.615631 MHz) */
+ {0xF3, 0x09, 332}, /* 36 (332.177612 MHz) */
+ {0xEA, 0x08, 340}, /* 37 (340.477MHz) */
+ {0xE8, 0x07, 376}, /* 38 (375.847504 MHz) */
+ {0xDE, 0x06, 389}, /* 39 (388.631439 MHz) */
+ {0x52, 0x2A, 54}, /* 3A (54.000MHz) */
+ {0x52, 0x6A, 27}, /* 3B (27.000MHz) */
+ {0x62, 0x24, 70}, /* 3C (70.874991MHz) */
+ {0x62, 0x64, 70}, /* 3D (70.1048912MHz) */
+ {0xA8, 0x4C, 30}, /* 3E (30.1048912MHz) */
+ {0x20, 0x26, 33}, /* 3F (33.7499957MHz) */
+ {0x31, 0xc2, 39}, /* 40 (39.77MHz) */
+ {0x11, 0x21, 30}, /* 41 (30MHz) }// NTSC 1024X768 */
+ {0x2E, 0x48, 25}, /* 42 (25.175MHz) }// ScaleLCD */
+ {0x24, 0x46, 25}, /* 43 (25.175MHz) */
+ {0x26, 0x64, 28}, /* 44 (28.322MHz) */
+ {0x37, 0x64, 40}, /* 45 (40.000MHz) */
+ {0xA1, 0x42, 108}, /* 46 (95.000MHz) }// QVGA */
+ {0x37, 0x61, 100}, /* 47 (100.00MHz) */
+ {0x78, 0x27, 108}, /* 48 (108.200MHz) */
+ {0xBF, 0xC8, 35 }, /* 49 (35.2MHz) */
+ {0x66, 0x43, 123}, /* 4A (122.61Mhz) */
+ {0x2C, 0x61, 80 }, /* 4B (80.350Mhz) */
+ {0x3B, 0x61, 108}, /* 4C (107.385Mhz) */
+/*
+ {0x60, 0x36, 30}, // 4D (30.200MHz) }// No use
+ {0x60, 0x36, 30}, // 4E (30.200MHz) }// No use
+ {0x60, 0x36, 30}, // 4F (30.200MHz) }// No use
+ {0x60, 0x36, 30}, // 50 (30.200MHz) }// CHTV
+ {0x40, 0x4A, 28}, // 51 (28.190MHz)
+ {0x9F, 0x46, 44}, // 52 (43.600MHz)
+ {0x97, 0x2C, 26}, // 53 (26.400MHz)
+ {0x44, 0xE4, 25}, // 54 (24.600MHz)
+ {0x7E, 0x32, 47}, // 55 (47.832MHz)
+ {0x8A, 0x24, 31}, // 56 (31.500MHz)
+ {0x97, 0x2C, 26}, // 57 (26.200MHz)
+ {0xCE, 0x3C, 39}, // 58 (39.000MHz)
+ {0x52, 0x4A, 36}, // 59 (36.000MHz)
+*/
+ {0x69, 0x61, 191}, /* 4D (190.96MHz ) */
+ {0x4F, 0x22, 192}, /* 4E (192.069MHz) */
+ {0x28, 0x26, 322}, /* 4F (322.273MHz) */
+ {0x5C, 0x6B, 27}, /* 50 (27.74HMz) */
+ {0x57, 0x24, 126}, /* 51 (125.999MHz) */
+ {0x5C, 0x42, 148}, /* 52 (148.5MHz) */
+ {0x42, 0x61, 120}, /* 53 (120.839MHz) */
+ {0x62, 0x61, 178}, /* 54 (178.992MHz) */
+ {0x59, 0x22, 217}, /* 55 (217.325MHz) */
+ {0x29, 0x01, 300}, /* 56 (299.505Mhz) */
+ {0x52, 0x63, 74}, /* 57 (74.25MHz) */
+ {0xFF, 0x00, 0} /* End mark */
};
#if 0
-static unsigned char XGI660_TVDelayList[] =
-{
- 0x44, /* ; 0 ExtNTSCDelay */
- 0x44, /* ; 1 StNTSCDelay */
- 0x44, /* ; 2 ExtPALDelay */
- 0x44, /* ; 3 StPALDelay */
- 0x44, /* ; 4 ExtHiTVDelay(1080i) */
- 0x44, /* ; 5 StHiTVDelay(1080i) */
- 0x44, /* ; 6 ExtYPbPrDelay(525i) */
- 0x44, /* ; 7 StYPbPrDealy(525i) */
- 0x44, /* ; 8 ExtYPbPrDelay(525p) */
- 0x44, /* ; 9 StYPbPrDealy(525p) */
- 0x44, /* ; A ExtYPbPrDelay(750p) */
- 0x44 /* ; B StYPbPrDealy(750p) */
+static unsigned char XGI660_TVDelayList[] = {
+ 0x44, /* ; 0 ExtNTSCDelay */
+ 0x44, /* ; 1 StNTSCDelay */
+ 0x44, /* ; 2 ExtPALDelay */
+ 0x44, /* ; 3 StPALDelay */
+ 0x44, /* ; 4 ExtHiTVDelay(1080i) */
+ 0x44, /* ; 5 StHiTVDelay(1080i) */
+ 0x44, /* ; 6 ExtYPbPrDelay(525i) */
+ 0x44, /* ; 7 StYPbPrDealy(525i) */
+ 0x44, /* ; 8 ExtYPbPrDelay(525p) */
+ 0x44, /* ; 9 StYPbPrDealy(525p) */
+ 0x44, /* ; A ExtYPbPrDelay(750p) */
+ 0x44 /* ; B StYPbPrDealy(750p) */
};
-static unsigned char XGI660_TVDelayList2[] =
-{
- 0x44, /* ; 0 ExtNTSCDelay */
- 0x44, /* ; 1 StNTSCDelay */
- 0x44, /* ; 2 ExtPALDelay */
- 0x44, /* ; 3 StPALDelay */
- 0x44, /* ; 4 ExtHiTVDelay */
- 0x44, /* ; 5 StHiTVDelay */
- 0x44, /* ; 6 ExtYPbPrDelay(525i) */
- 0x44, /* ; 7 StYPbPrDealy(525i) */
- 0x44, /* ; 8 ExtYPbPrDelay(525p) */
- 0x44, /* ; 9 StYPbPrDealy(525p) */
- 0x44, /* ; A ExtYPbPrDelay(750p) */
- 0x44 /* ; B StYPbPrDealy(750p) */
+static unsigned char XGI660_TVDelayList2[] = {
+ 0x44, /* ; 0 ExtNTSCDelay */
+ 0x44, /* ; 1 StNTSCDelay */
+ 0x44, /* ; 2 ExtPALDelay */
+ 0x44, /* ; 3 StPALDelay */
+ 0x44, /* ; 4 ExtHiTVDelay */
+ 0x44, /* ; 5 StHiTVDelay */
+ 0x44, /* ; 6 ExtYPbPrDelay(525i) */
+ 0x44, /* ; 7 StYPbPrDealy(525i) */
+ 0x44, /* ; 8 ExtYPbPrDelay(525p) */
+ 0x44, /* ; 9 StYPbPrDealy(525p) */
+ 0x44, /* ; A ExtYPbPrDelay(750p) */
+ 0x44 /* ; B StYPbPrDealy(750p) */
};
#endif
-static unsigned char XGI301TVDelayList[] =
-{
- 0x22, /* ; 0 ExtNTSCDelay */
- 0x22, /* ; 1 StNTSCDelay */
- 0x22, /* ; 2 ExtPALDelay */
- 0x22, /* ; 3 StPALDelay */
- 0x88, /* ; 4 ExtHiTVDelay(1080i) */
- 0xBB, /* ; 5 StHiTVDelay(1080i) */
- 0x22, /* ; 6 ExtYPbPrDelay(525i) */
- 0x22, /* ; 7 StYPbPrDealy(525i) */
- 0x22, /* ; 8 ExtYPbPrDelay(525p) */
- 0x22, /* ; 9 StYPbPrDealy(525p) */
- 0x22, /* ; A ExtYPbPrDelay(750p) */
- 0x22 /* B StYPbPrDealy(750p) */
+static unsigned char XGI301TVDelayList[] = {
+ 0x22, /* ; 0 ExtNTSCDelay */
+ 0x22, /* ; 1 StNTSCDelay */
+ 0x22, /* ; 2 ExtPALDelay */
+ 0x22, /* ; 3 StPALDelay */
+ 0x88, /* ; 4 ExtHiTVDelay(1080i) */
+ 0xBB, /* ; 5 StHiTVDelay(1080i) */
+ 0x22, /* ; 6 ExtYPbPrDelay(525i) */
+ 0x22, /* ; 7 StYPbPrDealy(525i) */
+ 0x22, /* ; 8 ExtYPbPrDelay(525p) */
+ 0x22, /* ; 9 StYPbPrDealy(525p) */
+ 0x22, /* ; A ExtYPbPrDelay(750p) */
+ 0x22 /* B StYPbPrDealy(750p) */
};
-static unsigned char XGI301TVDelayList2[] =
-{
- 0x22, /* ; 0 ExtNTSCDelay */
- 0x22, /* ; 1 StNTSCDelay */
- 0x22, /* ; 2 ExtPALDelay */
- 0x22, /* ; 3 StPALDelay */
- 0x22, /* ; 4 ExtHiTVDelay */
- 0x22, /* ; 5 StHiTVDelay */
- 0x22, /* ; 6 ExtYPbPrDelay(525i) */
- 0x22, /* ; 7 StYPbPrDealy(525i) */
- 0x22, /* ; 8 ExtYPbPrDelay(525p) */
- 0x22, /* ; 9 StYPbPrDealy(525p) */
- 0x22, /* ; A ExtYPbPrDelay(750p) */
- 0x22 /* ; B StYPbPrDealy(750p) */
+static unsigned char XGI301TVDelayList2[] = {
+ 0x22, /* ; 0 ExtNTSCDelay */
+ 0x22, /* ; 1 StNTSCDelay */
+ 0x22, /* ; 2 ExtPALDelay */
+ 0x22, /* ; 3 StPALDelay */
+ 0x22, /* ; 4 ExtHiTVDelay */
+ 0x22, /* ; 5 StHiTVDelay */
+ 0x22, /* ; 6 ExtYPbPrDelay(525i) */
+ 0x22, /* ; 7 StYPbPrDealy(525i) */
+ 0x22, /* ; 8 ExtYPbPrDelay(525p) */
+ 0x22, /* ; 9 StYPbPrDealy(525p) */
+ 0x22, /* ; A ExtYPbPrDelay(750p) */
+ 0x22 /* ; B StYPbPrDealy(750p) */
};
-static unsigned char TVAntiFlickList[] =
-{/* NTSCAntiFlicker */
- 0x04, /* ; 0 Adaptive */
- 0x00, /* ; 1 new anti-flicker ? */
-/* PALAntiFlicker */
- 0x04, /* ; 0 Adaptive */
- 0x08, /* ; 1 new anti-flicker ? */
-/* HiTVAntiFlicker */
- 0x04, /* ; 0 ? */
- 0x00 /* ; 1 new anti-flicker ? */
+static unsigned char TVAntiFlickList[] = {/* NTSCAntiFlicker */
+ 0x04, /* ; 0 Adaptive */
+ 0x00, /* ; 1 new anti-flicker ? */
+
+ 0x04, /* ; 0 Adaptive */
+ 0x08, /* ; 1 new anti-flicker ? */
+
+ 0x04, /* ; 0 ? */
+ 0x00 /* ; 1 new anti-flicker ? */
};
-static unsigned char TVEdgeList[] =
-{
- 0x00, /* ; 0 NTSC No Edge enhance */
- 0x04, /* ; 1 NTSC Adaptive Edge enhance */
- 0x00, /* ; 0 PAL No Edge enhance */
- 0x04, /* ; 1 PAL Adaptive Edge enhance */
- 0x00, /* ; 0 HiTV */
- 0x00 /* ; 1 HiTV */
+static unsigned char TVEdgeList[] = {
+ 0x00, /* ; 0 NTSC No Edge enhance */
+ 0x04, /* ; 1 NTSC Adaptive Edge enhance */
+ 0x00, /* ; 0 PAL No Edge enhance */
+ 0x04, /* ; 1 PAL Adaptive Edge enhance */
+ 0x00, /* ; 0 HiTV */
+ 0x00 /* ; 1 HiTV */
};
-static unsigned long TVPhaseList[] =
-{ 0x08BAED21, /* ; 0 NTSC phase */
- 0x00E3052A, /* ; 1 PAL phase */
- 0x9B2EE421, /* ; 2 PAL-M phase */
- 0xBA3EF421, /* ; 3 PAL-N phase */
- 0xA7A28B1E, /* ; 4 NTSC 1024x768 */
- 0xE00A831E, /* ; 5 PAL-M 1024x768 */
- 0x00000000, /* ; 6 reserved */
- 0x00000000, /* ; 7 reserved */
- 0xD67BF021, /* ; 8 NTSC phase */
- 0xE986092A, /* ; 9 PAL phase */
- 0xA4EFE621, /* ; A PAL-M phase */
- 0x4694F621, /* ; B PAL-N phase */
- 0x8BDE711C, /* ; C NTSC 1024x768 */
- 0xE00A831E /* ; D PAL-M 1024x768 */
+static unsigned long TVPhaseList[] = {
+ 0x08BAED21, /* ; 0 NTSC phase */
+ 0x00E3052A, /* ; 1 PAL phase */
+ 0x9B2EE421, /* ; 2 PAL-M phase */
+ 0xBA3EF421, /* ; 3 PAL-N phase */
+ 0xA7A28B1E, /* ; 4 NTSC 1024x768 */
+ 0xE00A831E, /* ; 5 PAL-M 1024x768 */
+ 0x00000000, /* ; 6 reserved */
+ 0x00000000, /* ; 7 reserved */
+ 0xD67BF021, /* ; 8 NTSC phase */
+ 0xE986092A, /* ; 9 PAL phase */
+ 0xA4EFE621, /* ; A PAL-M phase */
+ 0x4694F621, /* ; B PAL-N phase */
+ 0x8BDE711C, /* ; C NTSC 1024x768 */
+ 0xE00A831E /* ; D PAL-M 1024x768 */
};
-static unsigned char NTSCYFilter1[] =
-{
- 0x00,0xF4,0x10,0x38 ,/* 0 : 320x text mode */
- 0x00,0xF4,0x10,0x38 ,/* 1 : 360x text mode */
- 0xEB,0x04,0x25,0x18 ,/* 2 : 640x text mode */
- 0xF1,0x04,0x1F,0x18 ,/* 3 : 720x text mode */
- 0x00,0xF4,0x10,0x38 ,/* 4 : 320x gra. mode */
- 0xEB,0x04,0x25,0x18 ,/* 5 : 640x gra. mode */
- 0xEB,0x15,0x25,0xF6 /* 6 : 800x gra. mode */
+static unsigned char NTSCYFilter1[] = {
+ 0x00, 0xF4, 0x10, 0x38, /* 0 : 320x text mode */
+ 0x00, 0xF4, 0x10, 0x38, /* 1 : 360x text mode */
+ 0xEB, 0x04, 0x25, 0x18, /* 2 : 640x text mode */
+ 0xF1, 0x04, 0x1F, 0x18, /* 3 : 720x text mode */
+ 0x00, 0xF4, 0x10, 0x38, /* 4 : 320x gra. mode */
+ 0xEB, 0x04, 0x25, 0x18, /* 5 : 640x gra. mode */
+ 0xEB, 0x15, 0x25, 0xF6 /* 6 : 800x gra. mode */
};
-static unsigned char PALYFilter1[] =
-{
- 0x00,0xF4,0x10,0x38, /* 0 : 320x text mode */
- 0x00,0xF4,0x10,0x38 ,/* 1 : 360x text mode */
- 0xF1,0xF7,0x1F,0x32 ,/* 2 : 640x text mode */
- 0xF3,0x00,0x1D,0x20 ,/* 3 : 720x text mode */
- 0x00,0xF4,0x10,0x38 ,/* 4 : 320x gra. mode */
- 0xF1,0xF7,0x1F,0x32 ,/* 5 : 640x gra. mode */
- 0xFC,0xFB,0x14,0x2A /* 6 : 800x gra. mode */
+static unsigned char PALYFilter1[] = {
+ 0x00, 0xF4, 0x10, 0x38, /* 0 : 320x text mode */
+ 0x00, 0xF4, 0x10, 0x38, /* 1 : 360x text mode */
+ 0xF1, 0xF7, 0x1F, 0x32, /* 2 : 640x text mode */
+ 0xF3, 0x00, 0x1D, 0x20, /* 3 : 720x text mode */
+ 0x00, 0xF4, 0x10, 0x38, /* 4 : 320x gra. mode */
+ 0xF1, 0xF7, 0x1F, 0x32, /* 5 : 640x gra. mode */
+ 0xFC, 0xFB, 0x14, 0x2A /* 6 : 800x gra. mode */
};
-static unsigned char PALMYFilter1[] =
-{
- 0x00,0xF4,0x10,0x38, /* 0 : 320x text mode */
- 0x00,0xF4,0x10,0x38, /* 1 : 360x text mode */
- 0xEB,0x04,0x10,0x18, /* 2 : 640x text mode */
- 0xF7,0x06,0x19,0x14, /* 3 : 720x text mode */
- 0x00,0xF4,0x10,0x38, /* 4 : 320x gra. mode */
- 0xEB,0x04,0x25,0x18, /* 5 : 640x gra. mode */
- 0xEB,0x15,0x25,0xF6, /* 6 : 800x gra. mode */
- 0xFF,0xFF,0xFF,0xFF /* End of Table */
+static unsigned char PALMYFilter1[] = {
+ 0x00, 0xF4, 0x10, 0x38, /* 0 : 320x text mode */
+ 0x00, 0xF4, 0x10, 0x38, /* 1 : 360x text mode */
+ 0xEB, 0x04, 0x10, 0x18, /* 2 : 640x text mode */
+ 0xF7, 0x06, 0x19, 0x14, /* 3 : 720x text mode */
+ 0x00, 0xF4, 0x10, 0x38, /* 4 : 320x gra. mode */
+ 0xEB, 0x04, 0x25, 0x18, /* 5 : 640x gra. mode */
+ 0xEB, 0x15, 0x25, 0xF6, /* 6 : 800x gra. mode */
+ 0xFF, 0xFF, 0xFF, 0xFF /* End of Table */
};
-static unsigned char PALNYFilter1[] =
-{
- 0x00,0xF4,0x10,0x38, /* 0 : 320x text mode */
- 0x00,0xF4,0x10,0x38, /* 1 : 360x text mode */
- 0xEB,0x04,0x10,0x18, /* 2 : 640x text mode */
- 0xF7,0x06,0x19,0x14, /* 3 : 720x text mode */
- 0x00,0xF4,0x10,0x38, /* 4 : 320x gra. mode */
- 0xEB,0x04,0x25,0x18, /* 5 : 640x gra. mode */
- 0xEB,0x15,0x25,0xF6, /* 6 : 800x gra. mode */
- 0xFF,0xFF,0xFF,0xFF /* End of Table */
+static unsigned char PALNYFilter1[] = {
+ 0x00, 0xF4, 0x10, 0x38, /* 0 : 320x text mode */
+ 0x00, 0xF4, 0x10, 0x38, /* 1 : 360x text mode */
+ 0xEB, 0x04, 0x10, 0x18, /* 2 : 640x text mode */
+ 0xF7, 0x06, 0x19, 0x14, /* 3 : 720x text mode */
+ 0x00, 0xF4, 0x10, 0x38, /* 4 : 320x gra. mode */
+ 0xEB, 0x04, 0x25, 0x18, /* 5 : 640x gra. mode */
+ 0xEB, 0x15, 0x25, 0xF6, /* 6 : 800x gra. mode */
+ 0xFF, 0xFF, 0xFF, 0xFF /* End of Table */
};
-static unsigned char NTSCYFilter2[] =
-{
- 0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46, /* 0 : 320x text mode */
- 0x01,0x02,0xFE,0xF7,0x03,0x27,0x3C, /* 1 : 360x text mode */
- 0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46, /* 2 : 640x text mode */
- 0x01,0x02,0xFE,0xF7,0x03,0x27,0x3C, /* 3 : 720x text mode */
- 0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46, /* 4 : 320x gra. mode */
- 0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46, /* 5 : 640x gra. mode */
- 0x01,0x01,0xFC,0xF8,0x08,0x26,0x38, /* 6 : 800x gra. mode */
- 0xFF,0xFF,0xFC,0x00,0x0F,0x22,0x28 /* 7 : 1024xgra. mode */
+static unsigned char NTSCYFilter2[] = {
+ 0xFF, 0x03, 0x02, 0xF6, 0xFC, 0x27, 0x46, /* 0 : 320x text mode */
+ 0x01, 0x02, 0xFE, 0xF7, 0x03, 0x27, 0x3C, /* 1 : 360x text mode */
+ 0xFF, 0x03, 0x02, 0xF6, 0xFC, 0x27, 0x46, /* 2 : 640x text mode */
+ 0x01, 0x02, 0xFE, 0xF7, 0x03, 0x27, 0x3C, /* 3 : 720x text mode */
+ 0xFF, 0x03, 0x02, 0xF6, 0xFC, 0x27, 0x46, /* 4 : 320x gra. mode */
+ 0xFF, 0x03, 0x02, 0xF6, 0xFC, 0x27, 0x46, /* 5 : 640x gra. mode */
+ 0x01, 0x01, 0xFC, 0xF8, 0x08, 0x26, 0x38, /* 6 : 800x gra. mode */
+ 0xFF, 0xFF, 0xFC, 0x00, 0x0F, 0x22, 0x28 /* 7 : 1024xgra. mode */
};
-static unsigned char PALYFilter2[] =
-{
- 0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46, /* 0 : 320x text mode */
- 0x01,0x02,0xFE,0xF7,0x03,0x27,0x3C, /* 1 : 360x text mode */
- 0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46, /* 2 : 640x text mode */
- 0x01,0x02,0xFE,0xF7,0x03,0x27,0x3C, /* 3 : 720x text mode */
- 0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46, /* 4 : 320x gra. mode */
- 0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46, /* 5 : 640x gra. mode */
- 0x01,0x01,0xFC,0xF8,0x08,0x26,0x38, /* 6 : 800x gra. mode */
- 0xFF,0xFF,0xFC,0x00,0x0F,0x22,0x28 /* 7 : 1024xgra. mode */
+static unsigned char PALYFilter2[] = {
+ 0xFF, 0x03, 0x02, 0xF6, 0xFC, 0x27, 0x46, /* 0 : 320x text mode */
+ 0x01, 0x02, 0xFE, 0xF7, 0x03, 0x27, 0x3C, /* 1 : 360x text mode */
+ 0xFF, 0x03, 0x02, 0xF6, 0xFC, 0x27, 0x46, /* 2 : 640x text mode */
+ 0x01, 0x02, 0xFE, 0xF7, 0x03, 0x27, 0x3C, /* 3 : 720x text mode */
+ 0xFF, 0x03, 0x02, 0xF6, 0xFC, 0x27, 0x46, /* 4 : 320x gra. mode */
+ 0xFF, 0x03, 0x02, 0xF6, 0xFC, 0x27, 0x46, /* 5 : 640x gra. mode */
+ 0x01, 0x01, 0xFC, 0xF8, 0x08, 0x26, 0x38, /* 6 : 800x gra. mode */
+ 0xFF, 0xFF, 0xFC, 0x00, 0x0F, 0x22, 0x28 /* 7 : 1024xgra. mode */
};
-static unsigned char PALMYFilter2[] =
-{
- 0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46, /* 0 : 320x text mode */
- 0x01,0x02,0xFE,0xF7,0x03,0x27,0x3C, /* 1 : 360x text mode */
- 0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46, /* 2 : 640x text mode */
- 0x01,0x02,0xFE,0xF7,0x03,0x27,0x3C, /* 3 : 720x text mode */
- 0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46, /* 4 : 320x gra. mode */
- 0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46, /* 5 : 640x gra. mode */
- 0x01,0x01,0xFC,0xF8,0x08,0x26,0x38, /* 6 : 800x gra. mode */
- 0xFF,0xFF,0xFC,0x00,0x0F,0x22,0x28 /* 7 : 1024xgra. mode */
+static unsigned char PALMYFilter2[] = {
+ 0xFF, 0x03, 0x02, 0xF6, 0xFC, 0x27, 0x46, /* 0 : 320x text mode */
+ 0x01, 0x02, 0xFE, 0xF7, 0x03, 0x27, 0x3C, /* 1 : 360x text mode */
+ 0xFF, 0x03, 0x02, 0xF6, 0xFC, 0x27, 0x46, /* 2 : 640x text mode */
+ 0x01, 0x02, 0xFE, 0xF7, 0x03, 0x27, 0x3C, /* 3 : 720x text mode */
+ 0xFF, 0x03, 0x02, 0xF6, 0xFC, 0x27, 0x46, /* 4 : 320x gra. mode */
+ 0xFF, 0x03, 0x02, 0xF6, 0xFC, 0x27, 0x46, /* 5 : 640x gra. mode */
+ 0x01, 0x01, 0xFC, 0xF8, 0x08, 0x26, 0x38, /* 6 : 800x gra. mode */
+ 0xFF, 0xFF, 0xFC, 0x00, 0x0F, 0x22, 0x28 /* 7 : 1024xgra. mode */
};
-static unsigned char PALNYFilter2[] =
-{
- 0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46, /* 0 : 320x text mode */
- 0x01,0x02,0xFE,0xF7,0x03,0x27,0x3C, /* 1 : 360x text mode */
- 0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46, /* 2 : 640x text mode */
- 0x01,0x02,0xFE,0xF7,0x03,0x27,0x3C, /* 3 : 720x text mode */
- 0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46, /* 4 : 320x gra. mode */
- 0xFF,0x03,0x02,0xF6,0xFC,0x27,0x46, /* 5 : 640x gra. mode */
- 0x01,0x01,0xFC,0xF8,0x08,0x26,0x38, /* 6 : 800x gra. mode */
- 0xFF,0xFF,0xFC,0x00,0x0F,0x22,0x28 /* 7 : 1024xgra. mode */
+static unsigned char PALNYFilter2[] = {
+ 0xFF, 0x03, 0x02, 0xF6, 0xFC, 0x27, 0x46, /* 0 : 320x text mode */
+ 0x01, 0x02, 0xFE, 0xF7, 0x03, 0x27, 0x3C, /* 1 : 360x text mode */
+ 0xFF, 0x03, 0x02, 0xF6, 0xFC, 0x27, 0x46, /* 2 : 640x text mode */
+ 0x01, 0x02, 0xFE, 0xF7, 0x03, 0x27, 0x3C, /* 3 : 720x text mode */
+ 0xFF, 0x03, 0x02, 0xF6, 0xFC, 0x27, 0x46, /* 4 : 320x gra. mode */
+ 0xFF, 0x03, 0x02, 0xF6, 0xFC, 0x27, 0x46, /* 5 : 640x gra. mode */
+ 0x01, 0x01, 0xFC, 0xF8, 0x08, 0x26, 0x38, /* 6 : 800x gra. mode */
+ 0xFF, 0xFF, 0xFC, 0x00, 0x0F, 0x22, 0x28 /* 7 : 1024xgra. mode */
};
-static unsigned char XGI_NTSC1024AdjTime[] =
-{
- 0xa7,0x07,0xf2,0x6e,0x17,0x8b,0x73,0x53,
- 0x13,0x40,0x34,0xF4,0x63,0xBB,0xCC,0x7A,
- 0x58,0xe4,0x73,0xd0,0x13
+static unsigned char XGI_NTSC1024AdjTime[] = {
+ 0xa7, 0x07, 0xf2, 0x6e, 0x17, 0x8b, 0x73, 0x53,
+ 0x13, 0x40, 0x34, 0xF4, 0x63, 0xBB, 0xCC, 0x7A,
+ 0x58, 0xe4, 0x73, 0xd0, 0x13
};
-static struct XGI301C_Tap4TimingStruct HiTVTap4Timing[] =
-{
- {0,{
- 0x00,0x20,0x00,0x00,0x7F,0x20,0x02,0x7F, /* ; C0-C7 */
- 0x7D,0x20,0x04,0x7F,0x7D,0x1F,0x06,0x7E, /* ; C8-CF */
- 0x7C,0x1D,0x09,0x7E,0x7C,0x1B,0x0B,0x7E, /* ; D0-D7 */
- 0x7C,0x19,0x0E,0x7D,0x7C,0x17,0x11,0x7C, /* ; D8-DF */
- 0x7C,0x14,0x14,0x7C,0x7C,0x11,0x17,0x7C, /* ; E0-E7 */
- 0x7D,0x0E,0x19,0x7C,0x7E,0x0B,0x1B,0x7C, /* ; EA-EF */
- 0x7E,0x09,0x1D,0x7C,0x7F,0x06,0x1F,0x7C, /* ; F0-F7 */
- 0x7F,0x04,0x20,0x7D,0x00,0x02,0x20,0x7E /* ; F8-FF */
+static struct XGI301C_Tap4TimingStruct HiTVTap4Timing[] = {
+ {0, {
+ 0x00, 0x20, 0x00, 0x00, 0x7F, 0x20, 0x02, 0x7F, /* ; C0-C7 */
+ 0x7D, 0x20, 0x04, 0x7F, 0x7D, 0x1F, 0x06, 0x7E, /* ; C8-CF */
+ 0x7C, 0x1D, 0x09, 0x7E, 0x7C, 0x1B, 0x0B, 0x7E, /* ; D0-D7 */
+ 0x7C, 0x19, 0x0E, 0x7D, 0x7C, 0x17, 0x11, 0x7C, /* ; D8-DF */
+ 0x7C, 0x14, 0x14, 0x7C, 0x7C, 0x11, 0x17, 0x7C, /* ; E0-E7 */
+ 0x7D, 0x0E, 0x19, 0x7C, 0x7E, 0x0B, 0x1B, 0x7C, /* ; EA-EF */
+ 0x7E, 0x09, 0x1D, 0x7C, 0x7F, 0x06, 0x1F, 0x7C, /* ; F0-F7 */
+ 0x7F, 0x04, 0x20, 0x7D, 0x00, 0x02, 0x20, 0x7E /* ; F8-FF */
}
}
};
-static struct XGI301C_Tap4TimingStruct EnlargeTap4Timing[] =
-{
- {0,{
- 0x00,0x20,0x00,0x00,0x7F,0x20,0x02,0x7F, /* ; C0-C7 */
- 0x7D,0x20,0x04,0x7F,0x7D,0x1F,0x06,0x7E, /* ; C8-CF */
- 0x7C,0x1D,0x09,0x7E,0x7C,0x1B,0x0B,0x7E, /* ; D0-D7 */
- 0x7C,0x19,0x0E,0x7D,0x7C,0x17,0x11,0x7C, /* ; D8-DF */
- 0x7C,0x14,0x14,0x7C,0x7C,0x11,0x17,0x7C, /* ; E0-E7 */
- 0x7D,0x0E,0x19,0x7C,0x7E,0x0B,0x1B,0x7C, /* ; EA-EF */
- 0x7E,0x09,0x1D,0x7C,0x7F,0x06,0x1F,0x7C, /* ; F0-F7 */
- 0x7F,0x04,0x20,0x7D,0x00,0x02,0x20,0x7E /* ; F8-FF */
+static struct XGI301C_Tap4TimingStruct EnlargeTap4Timing[] = {
+ {0, {
+ 0x00, 0x20, 0x00, 0x00, 0x7F, 0x20, 0x02, 0x7F, /* ; C0-C7 */
+ 0x7D, 0x20, 0x04, 0x7F, 0x7D, 0x1F, 0x06, 0x7E, /* ; C8-CF */
+ 0x7C, 0x1D, 0x09, 0x7E, 0x7C, 0x1B, 0x0B, 0x7E, /* ; D0-D7 */
+ 0x7C, 0x19, 0x0E, 0x7D, 0x7C, 0x17, 0x11, 0x7C, /* ; D8-DF */
+ 0x7C, 0x14, 0x14, 0x7C, 0x7C, 0x11, 0x17, 0x7C, /* ; E0-E7 */
+ 0x7D, 0x0E, 0x19, 0x7C, 0x7E, 0x0B, 0x1B, 0x7C, /* ; EA-EF */
+ 0x7E, 0x09, 0x1D, 0x7C, 0x7F, 0x06, 0x1F, 0x7C, /* ; F0-F7 */
+ 0x7F, 0x04, 0x20, 0x7D, 0x00, 0x02, 0x20, 0x7E /* ; F8-FF */
}
}
};
-static struct XGI301C_Tap4TimingStruct NoScaleTap4Timing[] =
-{
- {0,{
- 0x00,0x20,0x00,0x00,0x7F,0x20,0x02,0x7F, /* ; C0-C7 */
- 0x7D,0x20,0x04,0x7F,0x7D,0x1F,0x06,0x7E, /* ; C8-CF */
- 0x7C,0x1D,0x09,0x7E,0x7C,0x1B,0x0B,0x7E, /* ; D0-D7 */
- 0x7C,0x19,0x0E,0x7D,0x7C,0x17,0x11,0x7C, /* ; D8-DF */
- 0x7C,0x14,0x14,0x7C,0x7C,0x11,0x17,0x7C, /* ; E0-E7 */
- 0x7D,0x0E,0x19,0x7C,0x7E,0x0B,0x1B,0x7C, /* ; EA-EF */
- 0x7E,0x09,0x1D,0x7C,0x7F,0x06,0x1F,0x7C, /* ; F0-F7 */
- 0x7F,0x04,0x20,0x7D,0x00,0x02,0x20,0x7E /* ; F8-FF */
+static struct XGI301C_Tap4TimingStruct NoScaleTap4Timing[] = {
+ {0, {
+ 0x00, 0x20, 0x00, 0x00, 0x7F, 0x20, 0x02, 0x7F, /* ; C0-C7 */
+ 0x7D, 0x20, 0x04, 0x7F, 0x7D, 0x1F, 0x06, 0x7E, /* ; C8-CF */
+ 0x7C, 0x1D, 0x09, 0x7E, 0x7C, 0x1B, 0x0B, 0x7E, /* ; D0-D7 */
+ 0x7C, 0x19, 0x0E, 0x7D, 0x7C, 0x17, 0x11, 0x7C, /* ; D8-DF */
+ 0x7C, 0x14, 0x14, 0x7C, 0x7C, 0x11, 0x17, 0x7C, /* ; E0-E7 */
+ 0x7D, 0x0E, 0x19, 0x7C, 0x7E, 0x0B, 0x1B, 0x7C, /* ; EA-EF */
+ 0x7E, 0x09, 0x1D, 0x7C, 0x7F, 0x06, 0x1F, 0x7C, /* ; F0-F7 */
+ 0x7F, 0x04, 0x20, 0x7D, 0x00, 0x02, 0x20, 0x7E /* ; F8-FF */
}
}
};
-static struct XGI301C_Tap4TimingStruct PALTap4Timing[] =
-{
- {600, {
- 0x05,0x19,0x05,0x7D,0x03,0x19,0x06,0x7E, /* ; C0-C7 */
- 0x02,0x19,0x08,0x7D,0x01,0x18,0x0A,0x7D, /* ; C8-CF */
- 0x00,0x18,0x0C,0x7C,0x7F,0x17,0x0E,0x7C, /* ; D0-D7 */
- 0x7E,0x16,0x0F,0x7D,0x7E,0x14,0x11,0x7D, /* ; D8-DF */
- 0x7D,0x13,0x13,0x7D,0x7D,0x11,0x14,0x7E, /* ; E0-E7 */
- 0x7D,0x0F,0x16,0x7E,0x7D,0x0E,0x17,0x7E, /* ; EA-EF */
- 0x7D,0x0C,0x18,0x7F,0x7D,0x0A,0x18,0x01, /* ; F0-F7 */
- 0x7D,0x08,0x19,0x02,0x7D,0x06,0x19,0x04 /* ; F8-FF */
- }
- },
- {768, {
- 0x08,0x12,0x08,0x7E,0x07,0x12,0x09,0x7E, /* ; C0-C7 */
- 0x06,0x12,0x0A,0x7E,0x05,0x11,0x0B,0x7F, /* ; C8-CF */
- 0x04,0x11,0x0C,0x7F,0x03,0x11,0x0C,0x00, /* ; D0-D7 */
- 0x03,0x10,0x0D,0x00,0x02,0x0F,0x0E,0x01, /* ; D8-DF */
- 0x01,0x0F,0x0F,0x01,0x01,0x0E,0x0F,0x02, /* ; E0-E7 */
- 0x00,0x0D,0x10,0x03,0x7F,0x0C,0x11,0x04, /* ; EA-EF */
- 0x7F,0x0C,0x11,0x04,0x7F,0x0B,0x11,0x05, /* ; F0-F7 */
- 0x7E,0x0A,0x12,0x06,0x7E,0x09,0x12,0x07 /* ; F8-FF */
- }
- },
- {0xFFFF,
- {
- 0x04,0x1A,0x04,0x7E,0x02,0x1B,0x05,0x7E, /* ; C0-C7 */
- 0x01,0x1A,0x07,0x7E,0x00,0x1A,0x09,0x7D, /* ; C8-CF */
- 0x7F,0x19,0x0B,0x7D,0x7E,0x18,0x0D,0x7D, /* ; D0-D7 */
- 0x7D,0x17,0x10,0x7C,0x7D,0x15,0x12,0x7C, /* ; D8-DF */
- 0x7C,0x14,0x14,0x7C,0x7C,0x12,0x15,0x7D, /* ; E0-E7 */
- 0x7C,0x10,0x17,0x7D,0x7C,0x0D,0x18,0x7F, /* ; EA-EF */
- 0x7D,0x0B,0x19,0x7F,0x7D,0x09,0x1A,0x00, /* ; F0-F7 */
- 0x7D,0x07,0x1A,0x02,0x7E,0x05,0x1B,0x02 /* ; F8-FF */
- }
- }
+static struct XGI301C_Tap4TimingStruct PALTap4Timing[] = {
+ {600, {
+ 0x05, 0x19, 0x05, 0x7D, 0x03, 0x19, 0x06, 0x7E, /* ; C0-C7 */
+ 0x02, 0x19, 0x08, 0x7D, 0x01, 0x18, 0x0A, 0x7D, /* ; C8-CF */
+ 0x00, 0x18, 0x0C, 0x7C, 0x7F, 0x17, 0x0E, 0x7C, /* ; D0-D7 */
+ 0x7E, 0x16, 0x0F, 0x7D, 0x7E, 0x14, 0x11, 0x7D, /* ; D8-DF */
+ 0x7D, 0x13, 0x13, 0x7D, 0x7D, 0x11, 0x14, 0x7E, /* ; E0-E7 */
+ 0x7D, 0x0F, 0x16, 0x7E, 0x7D, 0x0E, 0x17, 0x7E, /* ; EA-EF */
+ 0x7D, 0x0C, 0x18, 0x7F, 0x7D, 0x0A, 0x18, 0x01, /* ; F0-F7 */
+ 0x7D, 0x08, 0x19, 0x02, 0x7D, 0x06, 0x19, 0x04 /* ; F8-FF */
+ }
+ },
+ {768, {
+ 0x08, 0x12, 0x08, 0x7E, 0x07, 0x12, 0x09, 0x7E, /* ; C0-C7 */
+ 0x06, 0x12, 0x0A, 0x7E, 0x05, 0x11, 0x0B, 0x7F, /* ; C8-CF */
+ 0x04, 0x11, 0x0C, 0x7F, 0x03, 0x11, 0x0C, 0x00, /* ; D0-D7 */
+ 0x03, 0x10, 0x0D, 0x00, 0x02, 0x0F, 0x0E, 0x01, /* ; D8-DF */
+ 0x01, 0x0F, 0x0F, 0x01, 0x01, 0x0E, 0x0F, 0x02, /* ; E0-E7 */
+ 0x00, 0x0D, 0x10, 0x03, 0x7F, 0x0C, 0x11, 0x04, /* ; EA-EF */
+ 0x7F, 0x0C, 0x11, 0x04, 0x7F, 0x0B, 0x11, 0x05, /* ; F0-F7 */
+ 0x7E, 0x0A, 0x12, 0x06, 0x7E, 0x09, 0x12, 0x07 /* ; F8-FF */
+ }
+ },
+ {0xFFFF, {
+ 0x04, 0x1A, 0x04, 0x7E, 0x02, 0x1B, 0x05, 0x7E, /* ; C0-C7 */
+ 0x01, 0x1A, 0x07, 0x7E, 0x00, 0x1A, 0x09, 0x7D, /* ; C8-CF */
+ 0x7F, 0x19, 0x0B, 0x7D, 0x7E, 0x18, 0x0D, 0x7D, /* ; D0-D7 */
+ 0x7D, 0x17, 0x10, 0x7C, 0x7D, 0x15, 0x12, 0x7C, /* ; D8-DF */
+ 0x7C, 0x14, 0x14, 0x7C, 0x7C, 0x12, 0x15, 0x7D, /* ; E0-E7 */
+ 0x7C, 0x10, 0x17, 0x7D, 0x7C, 0x0D, 0x18, 0x7F, /* ; EA-EF */
+ 0x7D, 0x0B, 0x19, 0x7F, 0x7D, 0x09, 0x1A, 0x00, /* ; F0-F7 */
+ 0x7D, 0x07, 0x1A, 0x02, 0x7E, 0x05, 0x1B, 0x02 /* ; F8-FF */
+ }
+ }
};
-static struct XGI301C_Tap4TimingStruct NTSCTap4Timing[] =
-{
+static struct XGI301C_Tap4TimingStruct NTSCTap4Timing[] = {
{480, {
- 0x04,0x1A,0x04,0x7E,0x03,0x1A,0x06,0x7D, /* ; C0-C7 */
- 0x01,0x1A,0x08,0x7D,0x00,0x19,0x0A,0x7D, /* ; C8-CF */
- 0x7F,0x19,0x0C,0x7C,0x7E,0x18,0x0E,0x7C, /* ; D0-D7 */
- 0x7E,0x17,0x10,0x7B,0x7D,0x15,0x12,0x7C, /* ; D8-DF */
- 0x7D,0x13,0x13,0x7D,0x7C,0x12,0x15,0x7D, /* ; E0-E7 */
- 0x7C,0x10,0x17,0x7D,0x7C,0x0E,0x18,0x7E, /* ; EA-EF */
- 0x7D,0x0C,0x19,0x7E,0x7D,0x0A,0x19,0x00, /* ; F0-F7 */
- 0x7D,0x08,0x1A,0x01,0x7E,0x06,0x1A,0x02 /* ; F8-FF */
- }
- },
- {600, {
- 0x07,0x14,0x07,0x7E,0x06,0x14,0x09,0x7D, /* ; C0-C7 */
- 0x05,0x14,0x0A,0x7D,0x04,0x13,0x0B,0x7E, /* ; C8-CF */
- 0x03,0x13,0x0C,0x7E,0x02,0x12,0x0D,0x7F, /* ; D0-D7 */
- 0x01,0x12,0x0E,0x7F,0x01,0x11,0x0F,0x7F, /* ; D8-DF */
- 0x01,0x10,0x10,0x00,0x7F,0x0F,0x11,0x01, /* ; E0-E7 */
- 0x7F,0x0E,0x12,0x01,0x7E,0x0D,0x12,0x03, /* ; EA-EF */
- 0x7E,0x0C,0x13,0x03,0x7E,0x0B,0x13,0x04, /* ; F0-F7 */
- 0x7E,0x0A,0x14,0x04,0x7D,0x09,0x14,0x06 /* ; F8-FF */
- }
- },
- {0xFFFF,
- {
- 0x09,0x0F,0x09,0x7F,0x08,0x0F,0x09,0x00, /* ; C0-C7 */
- 0x07,0x0F,0x0A,0x00,0x06,0x0F,0x0A,0x01, /* ; C8-CF */
- 0x06,0x0E,0x0B,0x01,0x05,0x0E,0x0B,0x02, /* ; D0-D7 */
- 0x04,0x0E,0x0C,0x02,0x04,0x0D,0x0C,0x03, /* ; D8-DF */
- 0x03,0x0D,0x0D,0x03,0x02,0x0C,0x0D,0x05, /* ; E0-E7 */
- 0x02,0x0C,0x0E,0x04,0x01,0x0B,0x0E,0x06, /* ; EA-EF */
- 0x01,0x0B,0x0E,0x06,0x00,0x0A,0x0F,0x07, /* ; F0-F7 */
- 0x00,0x0A,0x0F,0x07,0x00,0x09,0x0F,0x08 /* ; F8-FF */
- }
- }
+ 0x04, 0x1A, 0x04, 0x7E, 0x03, 0x1A, 0x06, 0x7D, /* ; C0-C7 */
+ 0x01, 0x1A, 0x08, 0x7D, 0x00, 0x19, 0x0A, 0x7D, /* ; C8-CF */
+ 0x7F, 0x19, 0x0C, 0x7C, 0x7E, 0x18, 0x0E, 0x7C, /* ; D0-D7 */
+ 0x7E, 0x17, 0x10, 0x7B, 0x7D, 0x15, 0x12, 0x7C, /* ; D8-DF */
+ 0x7D, 0x13, 0x13, 0x7D, 0x7C, 0x12, 0x15, 0x7D, /* ; E0-E7 */
+ 0x7C, 0x10, 0x17, 0x7D, 0x7C, 0x0E, 0x18, 0x7E, /* ; EA-EF */
+ 0x7D, 0x0C, 0x19, 0x7E, 0x7D, 0x0A, 0x19, 0x00, /* ; F0-F7 */
+ 0x7D, 0x08, 0x1A, 0x01, 0x7E, 0x06, 0x1A, 0x02 /* ; F8-FF */
+ }
+ },
+ {600, {
+ 0x07, 0x14, 0x07, 0x7E, 0x06, 0x14, 0x09, 0x7D, /* ; C0-C7 */
+ 0x05, 0x14, 0x0A, 0x7D, 0x04, 0x13, 0x0B, 0x7E, /* ; C8-CF */
+ 0x03, 0x13, 0x0C, 0x7E, 0x02, 0x12, 0x0D, 0x7F, /* ; D0-D7 */
+ 0x01, 0x12, 0x0E, 0x7F, 0x01, 0x11, 0x0F, 0x7F, /* ; D8-DF */
+ 0x01, 0x10, 0x10, 0x00, 0x7F, 0x0F, 0x11, 0x01, /* ; E0-E7 */
+ 0x7F, 0x0E, 0x12, 0x01, 0x7E, 0x0D, 0x12, 0x03, /* ; EA-EF */
+ 0x7E, 0x0C, 0x13, 0x03, 0x7E, 0x0B, 0x13, 0x04, /* ; F0-F7 */
+ 0x7E, 0x0A, 0x14, 0x04, 0x7D, 0x09, 0x14, 0x06 /* ; F8-FF */
+ }
+ },
+ {0xFFFF, {
+ 0x09, 0x0F, 0x09, 0x7F, 0x08, 0x0F, 0x09, 0x00, /* ; C0-C7 */
+ 0x07, 0x0F, 0x0A, 0x00, 0x06, 0x0F, 0x0A, 0x01, /* ; C8-CF */
+ 0x06, 0x0E, 0x0B, 0x01, 0x05, 0x0E, 0x0B, 0x02, /* ; D0-D7 */
+ 0x04, 0x0E, 0x0C, 0x02, 0x04, 0x0D, 0x0C, 0x03, /* ; D8-DF */
+ 0x03, 0x0D, 0x0D, 0x03, 0x02, 0x0C, 0x0D, 0x05, /* ; E0-E7 */
+ 0x02, 0x0C, 0x0E, 0x04, 0x01, 0x0B, 0x0E, 0x06, /* ; EA-EF */
+ 0x01, 0x0B, 0x0E, 0x06, 0x00, 0x0A, 0x0F, 0x07, /* ; F0-F7 */
+ 0x00, 0x0A, 0x0F, 0x07, 0x00, 0x09, 0x0F, 0x08 /* ; F8-FF */
+ }
+ }
};
-static struct XGI301C_Tap4TimingStruct YPbPr525pTap4Timing[] =
-{
+static struct XGI301C_Tap4TimingStruct YPbPr525pTap4Timing[] = {
{480, {
- 0x04,0x1A,0x04,0x7E,0x03,0x1A,0x06,0x7D, /* ; C0-C7 */
- 0x01,0x1A,0x08,0x7D,0x00,0x19,0x0A,0x7D, /* ; C8-CF */
- 0x7F,0x19,0x0C,0x7C,0x7E,0x18,0x0E,0x7C, /* ; D0-D7 */
- 0x7E,0x17,0x10,0x7B,0x7D,0x15,0x12,0x7C, /* ; D8-DF */
- 0x7D,0x13,0x13,0x7D,0x7C,0x12,0x15,0x7D, /* ; E0-E7 */
- 0x7C,0x10,0x17,0x7D,0x7C,0x0E,0x18,0x7E, /* ; EA-EF */
- 0x7D,0x0C,0x19,0x7E,0x7D,0x0A,0x19,0x00, /* ; F0-F7 */
- 0x7D,0x08,0x1A,0x01,0x7E,0x06,0x1A,0x02 /* ; F8-FF */
- }
- },
- {600, {
- 0x07,0x14,0x07,0x7E,0x06,0x14,0x09,0x7D, /* ; C0-C7 */
- 0x05,0x14,0x0A,0x7D,0x04,0x13,0x0B,0x7E, /* ; C8-CF */
- 0x03,0x13,0x0C,0x7E,0x02,0x12,0x0D,0x7F, /* ; D0-D7 */
- 0x01,0x12,0x0E,0x7F,0x01,0x11,0x0F,0x7F, /* ; D8-DF */
- 0x01,0x10,0x10,0x00,0x7F,0x0F,0x11,0x01, /* ; E0-E7 */
- 0x7F,0x0E,0x12,0x01,0x7E,0x0D,0x12,0x03, /* ; EA-EF */
- 0x7E,0x0C,0x13,0x03,0x7E,0x0B,0x13,0x04, /* ; F0-F7 */
- 0x7E,0x0A,0x14,0x04,0x7D,0x09,0x14,0x06 /* ; F8-FF */
- }
- },
- {0xFFFF,
- {
- 0x09,0x0F,0x09,0x7F,0x08,0x0F,0x09,0x00, /* ; C0-C7 */
- 0x07,0x0F,0x0A,0x00,0x06,0x0F,0x0A,0x01, /* ; C8-CF */
- 0x06,0x0E,0x0B,0x01,0x05,0x0E,0x0B,0x02, /* ; D0-D7 */
- 0x04,0x0E,0x0C,0x02,0x04,0x0D,0x0C,0x03, /* ; D8-DF */
- 0x03,0x0D,0x0D,0x03,0x02,0x0C,0x0D,0x05, /* ; E0-E7 */
- 0x02,0x0C,0x0E,0x04,0x01,0x0B,0x0E,0x06, /* ; EA-EF */
- 0x01,0x0B,0x0E,0x06,0x00,0x0A,0x0F,0x07, /* ; F0-F7 */
- 0x00,0x0A,0x0F,0x07,0x00,0x09,0x0F,0x08 /* ; F8-FF */
- }
- }
+ 0x04, 0x1A, 0x04, 0x7E, 0x03, 0x1A, 0x06, 0x7D, /* ; C0-C7 */
+ 0x01, 0x1A, 0x08, 0x7D, 0x00, 0x19, 0x0A, 0x7D, /* ; C8-CF */
+ 0x7F, 0x19, 0x0C, 0x7C, 0x7E, 0x18, 0x0E, 0x7C, /* ; D0-D7 */
+ 0x7E, 0x17, 0x10, 0x7B, 0x7D, 0x15, 0x12, 0x7C, /* ; D8-DF */
+ 0x7D, 0x13, 0x13, 0x7D, 0x7C, 0x12, 0x15, 0x7D, /* ; E0-E7 */
+ 0x7C, 0x10, 0x17, 0x7D, 0x7C, 0x0E, 0x18, 0x7E, /* ; EA-EF */
+ 0x7D, 0x0C, 0x19, 0x7E, 0x7D, 0x0A, 0x19, 0x00, /* ; F0-F7 */
+ 0x7D, 0x08, 0x1A, 0x01, 0x7E, 0x06, 0x1A, 0x02 /* ; F8-FF */
+ }
+ },
+ {600, {
+ 0x07, 0x14, 0x07, 0x7E, 0x06, 0x14, 0x09, 0x7D, /* ; C0-C7 */
+ 0x05, 0x14, 0x0A, 0x7D, 0x04, 0x13, 0x0B, 0x7E, /* ; C8-CF */
+ 0x03, 0x13, 0x0C, 0x7E, 0x02, 0x12, 0x0D, 0x7F, /* ; D0-D7 */
+ 0x01, 0x12, 0x0E, 0x7F, 0x01, 0x11, 0x0F, 0x7F, /* ; D8-DF */
+ 0x01, 0x10, 0x10, 0x00, 0x7F, 0x0F, 0x11, 0x01, /* ; E0-E7 */
+ 0x7F, 0x0E, 0x12, 0x01, 0x7E, 0x0D, 0x12, 0x03, /* ; EA-EF */
+ 0x7E, 0x0C, 0x13, 0x03, 0x7E, 0x0B, 0x13, 0x04, /* ; F0-F7 */
+ 0x7E, 0x0A, 0x14, 0x04, 0x7D, 0x09, 0x14, 0x06 /* ; F8-FF */
+ }
+ },
+ {0xFFFF, {
+ 0x09, 0x0F, 0x09, 0x7F, 0x08, 0x0F, 0x09, 0x00, /* ; C0-C7 */
+ 0x07, 0x0F, 0x0A, 0x00, 0x06, 0x0F, 0x0A, 0x01, /* ; C8-CF */
+ 0x06, 0x0E, 0x0B, 0x01, 0x05, 0x0E, 0x0B, 0x02, /* ; D0-D7 */
+ 0x04, 0x0E, 0x0C, 0x02, 0x04, 0x0D, 0x0C, 0x03, /* ; D8-DF */
+ 0x03, 0x0D, 0x0D, 0x03, 0x02, 0x0C, 0x0D, 0x05, /* ; E0-E7 */
+ 0x02, 0x0C, 0x0E, 0x04, 0x01, 0x0B, 0x0E, 0x06, /* ; EA-EF */
+ 0x01, 0x0B, 0x0E, 0x06, 0x00, 0x0A, 0x0F, 0x07, /* ; F0-F7 */
+ 0x00, 0x0A, 0x0F, 0x07, 0x00, 0x09, 0x0F, 0x08 /* ; F8-FF */
+ }
+ }
};
-static struct XGI301C_Tap4TimingStruct YPbPr525iTap4Timing[] =
-{
+static struct XGI301C_Tap4TimingStruct YPbPr525iTap4Timing[] = {
{480, {
- 0x04,0x1A,0x04,0x7E,0x03,0x1A,0x06,0x7D, /* ; C0-C7 */
- 0x01,0x1A,0x08,0x7D,0x00,0x19,0x0A,0x7D, /* ; C8-CF */
- 0x7F,0x19,0x0C,0x7C,0x7E,0x18,0x0E,0x7C, /* ; D0-D7 */
- 0x7E,0x17,0x10,0x7B,0x7D,0x15,0x12,0x7C, /* ; D8-DF */
- 0x7D,0x13,0x13,0x7D,0x7C,0x12,0x15,0x7D, /* ; E0-E7 */
- 0x7C,0x10,0x17,0x7D,0x7C,0x0E,0x18,0x7E, /* ; EA-EF */
- 0x7D,0x0C,0x19,0x7E,0x7D,0x0A,0x19,0x00, /* ; F0-F7 */
- 0x7D,0x08,0x1A,0x01,0x7E,0x06,0x1A,0x02 /* ; F8-FF */
- }
- },
- {600, {
- 0x07,0x14,0x07,0x7E,0x06,0x14,0x09,0x7D, /* ; C0-C7 */
- 0x05,0x14,0x0A,0x7D,0x04,0x13,0x0B,0x7E, /* ; C8-CF */
- 0x03,0x13,0x0C,0x7E,0x02,0x12,0x0D,0x7F, /* ; D0-D7 */
- 0x01,0x12,0x0E,0x7F,0x01,0x11,0x0F,0x7F, /* ; D8-DF */
- 0x01,0x10,0x10,0x00,0x7F,0x0F,0x11,0x01, /* ; E0-E7 */
- 0x7F,0x0E,0x12,0x01,0x7E,0x0D,0x12,0x03, /* ; EA-EF */
- 0x7E,0x0C,0x13,0x03,0x7E,0x0B,0x13,0x04, /* ; F0-F7 */
- 0x7E,0x0A,0x14,0x04,0x7D,0x09,0x14,0x06 /* ; F8-FF */
- }
- },
- {0xFFFF,
- {
- 0x09,0x0F,0x09,0x7F,0x08,0x0F,0x09,0x00, /* ; C0-C7 */
- 0x07,0x0F,0x0A,0x00,0x06,0x0F,0x0A,0x01, /* ; C8-CF */
- 0x06,0x0E,0x0B,0x01,0x05,0x0E,0x0B,0x02, /* ; D0-D7 */
- 0x04,0x0E,0x0C,0x02,0x04,0x0D,0x0C,0x03, /* ; D8-DF */
- 0x03,0x0D,0x0D,0x03,0x02,0x0C,0x0D,0x05, /* ; E0-E7 */
- 0x02,0x0C,0x0E,0x04,0x01,0x0B,0x0E,0x06, /* ; EA-EF */
- 0x01,0x0B,0x0E,0x06,0x00,0x0A,0x0F,0x07, /* ; F0-F7 */
- 0x00,0x0A,0x0F,0x07,0x00,0x09,0x0F,0x08 /* ; F8-FF */
- }
- }
+ 0x04, 0x1A, 0x04, 0x7E, 0x03, 0x1A, 0x06, 0x7D, /* ; C0-C7 */
+ 0x01, 0x1A, 0x08, 0x7D, 0x00, 0x19, 0x0A, 0x7D, /* ; C8-CF */
+ 0x7F, 0x19, 0x0C, 0x7C, 0x7E, 0x18, 0x0E, 0x7C, /* ; D0-D7 */
+ 0x7E, 0x17, 0x10, 0x7B, 0x7D, 0x15, 0x12, 0x7C, /* ; D8-DF */
+ 0x7D, 0x13, 0x13, 0x7D, 0x7C, 0x12, 0x15, 0x7D, /* ; E0-E7 */
+ 0x7C, 0x10, 0x17, 0x7D, 0x7C, 0x0E, 0x18, 0x7E, /* ; EA-EF */
+ 0x7D, 0x0C, 0x19, 0x7E, 0x7D, 0x0A, 0x19, 0x00, /* ; F0-F7 */
+ 0x7D, 0x08, 0x1A, 0x01, 0x7E, 0x06, 0x1A, 0x02 /* ; F8-FF */
+ }
+ },
+ {600, {
+ 0x07, 0x14, 0x07, 0x7E, 0x06, 0x14, 0x09, 0x7D, /* ; C0-C7 */
+ 0x05, 0x14, 0x0A, 0x7D, 0x04, 0x13, 0x0B, 0x7E, /* ; C8-CF */
+ 0x03, 0x13, 0x0C, 0x7E, 0x02, 0x12, 0x0D, 0x7F, /* ; D0-D7 */
+ 0x01, 0x12, 0x0E, 0x7F, 0x01, 0x11, 0x0F, 0x7F, /* ; D8-DF */
+ 0x01, 0x10, 0x10, 0x00, 0x7F, 0x0F, 0x11, 0x01, /* ; E0-E7 */
+ 0x7F, 0x0E, 0x12, 0x01, 0x7E, 0x0D, 0x12, 0x03, /* ; EA-EF */
+ 0x7E, 0x0C, 0x13, 0x03, 0x7E, 0x0B, 0x13, 0x04, /* ; F0-F7 */
+ 0x7E, 0x0A, 0x14, 0x04, 0x7D, 0x09, 0x14, 0x06 /* ; F8-FF */
+ }
+ },
+ {0xFFFF, {
+ 0x09, 0x0F, 0x09, 0x7F, 0x08, 0x0F, 0x09, 0x00, /* ; C0-C7 */
+ 0x07, 0x0F, 0x0A, 0x00, 0x06, 0x0F, 0x0A, 0x01, /* ; C8-CF */
+ 0x06, 0x0E, 0x0B, 0x01, 0x05, 0x0E, 0x0B, 0x02, /* ; D0-D7 */
+ 0x04, 0x0E, 0x0C, 0x02, 0x04, 0x0D, 0x0C, 0x03, /* ; D8-DF */
+ 0x03, 0x0D, 0x0D, 0x03, 0x02, 0x0C, 0x0D, 0x05, /* ; E0-E7 */
+ 0x02, 0x0C, 0x0E, 0x04, 0x01, 0x0B, 0x0E, 0x06, /* ; EA-EF */
+ 0x01, 0x0B, 0x0E, 0x06, 0x00, 0x0A, 0x0F, 0x07, /* ; F0-F7 */
+ 0x00, 0x0A, 0x0F, 0x07, 0x00, 0x09, 0x0F, 0x08 /* ; F8-FF */
+ }
+ }
};
-static struct XGI301C_Tap4TimingStruct YPbPr750pTap4Timing[] =
-{ {0xFFFF,
- {
- 0x05,0x19,0x05,0x7D,0x03,0x19,0x06,0x7E, /* ; C0-C7 */
- 0x02,0x19,0x08,0x7D,0x01,0x18,0x0A,0x7D, /* ; C8-CF */
- 0x00,0x18,0x0C,0x7C,0x7F,0x17,0x0E,0x7C, /* ; D0-D7 */
- 0x7E,0x16,0x0F,0x7D,0x7E,0x14,0x11,0x7D, /* ; D8-DF */
- 0x7D,0x13,0x13,0x7D,0x7D,0x11,0x14,0x7E, /* ; E0-E7 */
- 0x7D,0x0F,0x16,0x7E,0x7D,0x0E,0x17,0x7E, /* ; EA-EF */
- 0x7D,0x0C,0x18,0x7F,0x7D,0x0A,0x18,0x01, /* ; F0-F7 */
- 0x7D,0x08,0x19,0x02,0x7D,0x06,0x19,0x04 /* F8-FF */
- }
- }
+static struct XGI301C_Tap4TimingStruct YPbPr750pTap4Timing[] = {
+ {0xFFFF, {
+ 0x05, 0x19, 0x05, 0x7D, 0x03, 0x19, 0x06, 0x7E, /* ; C0-C7 */
+ 0x02, 0x19, 0x08, 0x7D, 0x01, 0x18, 0x0A, 0x7D, /* ; C8-CF */
+ 0x00, 0x18, 0x0C, 0x7C, 0x7F, 0x17, 0x0E, 0x7C, /* ; D0-D7 */
+ 0x7E, 0x16, 0x0F, 0x7D, 0x7E, 0x14, 0x11, 0x7D, /* ; D8-DF */
+ 0x7D, 0x13, 0x13, 0x7D, 0x7D, 0x11, 0x14, 0x7E, /* ; E0-E7 */
+ 0x7D, 0x0F, 0x16, 0x7E, 0x7D, 0x0E, 0x17, 0x7E, /* ; EA-EF */
+ 0x7D, 0x0C, 0x18, 0x7F, 0x7D, 0x0A, 0x18, 0x01, /* ; F0-F7 */
+ 0x7D, 0x08, 0x19, 0x02, 0x7D, 0x06, 0x19, 0x04 /* F8-FF */
+ }
+ }
};
diff --git a/drivers/staging/xgifb/vb_util.c b/drivers/staging/xgifb/vb_util.c
index a97e44f..ea2b795 100644
--- a/drivers/staging/xgifb/vb_util.c
+++ b/drivers/staging/xgifb/vb_util.c
@@ -3,7 +3,7 @@
#include "vb_struct.h"
#include "XGIfb.h"
-#include <asm/io.h>
+#include <linux/io.h>
#include <linux/types.h>
#include "vb_util.h"
diff --git a/drivers/staging/xgifb/vgatypes.h b/drivers/staging/xgifb/vgatypes.h
index d613e84..5aeb3a4 100644
--- a/drivers/staging/xgifb/vgatypes.h
+++ b/drivers/staging/xgifb/vgatypes.h
@@ -1,4 +1,3 @@
-
#ifndef _VGATYPES_
#define _VGATYPES_
@@ -6,79 +5,79 @@
#ifndef XGI_VB_CHIP_TYPE
enum XGI_VB_CHIP_TYPE {
- VB_CHIP_Legacy = 0,
- VB_CHIP_301,
- VB_CHIP_301B,
- VB_CHIP_301LV,
- VB_CHIP_302,
- VB_CHIP_302B,
- VB_CHIP_302LV,
- VB_CHIP_301C,
- VB_CHIP_302ELV,
- VB_CHIP_UNKNOWN, /* other video bridge or no video bridge */
- MAX_VB_CHIP
+ VB_CHIP_Legacy = 0,
+ VB_CHIP_301,
+ VB_CHIP_301B,
+ VB_CHIP_301LV,
+ VB_CHIP_302,
+ VB_CHIP_302B,
+ VB_CHIP_302LV,
+ VB_CHIP_301C,
+ VB_CHIP_302ELV,
+ VB_CHIP_UNKNOWN, /* other video bridge or no video bridge */
+ MAX_VB_CHIP
};
#endif
#ifndef XGI_LCD_TYPE
enum XGI_LCD_TYPE {
- LCD_INVALID = 0,
- LCD_320x480, /* FSTN, DSTN */
- LCD_640x480,
- LCD_640x480_2, /* FSTN, DSTN */
- LCD_640x480_3, /* FSTN, DSTN */
- LCD_800x600,
- LCD_848x480,
- LCD_1024x600,
- LCD_1024x768,
- LCD_1152x768,
- LCD_1152x864,
- LCD_1280x720,
- LCD_1280x768,
- LCD_1280x800,
- LCD_1280x960,
- LCD_1280x1024,
- LCD_1400x1050,
- LCD_1600x1200,
- LCD_1680x1050,
- LCD_1920x1440,
- LCD_2048x1536,
- LCD_CUSTOM,
- LCD_UNKNOWN
+ LCD_INVALID = 0,
+ LCD_320x480, /* FSTN, DSTN */
+ LCD_640x480,
+ LCD_640x480_2, /* FSTN, DSTN */
+ LCD_640x480_3, /* FSTN, DSTN */
+ LCD_800x600,
+ LCD_848x480,
+ LCD_1024x600,
+ LCD_1024x768,
+ LCD_1152x768,
+ LCD_1152x864,
+ LCD_1280x720,
+ LCD_1280x768,
+ LCD_1280x800,
+ LCD_1280x960,
+ LCD_1280x1024,
+ LCD_1400x1050,
+ LCD_1600x1200,
+ LCD_1680x1050,
+ LCD_1920x1440,
+ LCD_2048x1536,
+ LCD_CUSTOM,
+ LCD_UNKNOWN
};
#endif
-struct XGI_DSReg
-{
- unsigned char jIdx;
- unsigned char jVal;
+struct XGI_DSReg {
+ unsigned char jIdx;
+ unsigned char jVal;
};
-struct xgi_hw_device_info
-{
- unsigned long ulExternalChip; /* NO VB or other video bridge*/
- /* if ujVBChipID = VB_CHIP_UNKNOWN, */
+struct xgi_hw_device_info {
+ unsigned long ulExternalChip; /* NO VB or other video bridge*/
+ /* if ujVBChipID = VB_CHIP_UNKNOWN, */
- unsigned char *pjVirtualRomBase; /* ROM image */
+ unsigned char *pjVirtualRomBase; /* ROM image */
- unsigned char *pjVideoMemoryAddress;/* base virtual memory address */
- /* of Linear VGA memory */
+ unsigned char *pjVideoMemoryAddress;/* base virtual memory address */
+ /* of Linear VGA memory */
- unsigned long ulVideoMemorySize; /* size, in bytes, of the memory on the board */
+ unsigned long ulVideoMemorySize; /* size, in bytes, of the
+ memory on the board */
- unsigned char *pjIOAddress; /* base I/O address of VGA ports (0x3B0) */
+ unsigned char *pjIOAddress; /* base I/O address of VGA ports (0x3B0) */
- unsigned char jChipType; /* Used to Identify Graphics Chip */
- /* defined in the data structure type */
- /* "XGI_CHIP_TYPE" */
+ unsigned char jChipType; /* Used to Identify Graphics Chip */
+ /* defined in the data structure type */
+ /* "XGI_CHIP_TYPE" */
- unsigned char jChipRevision; /* Used to Identify Graphics Chip Revision */
+ unsigned char jChipRevision; /* Used to Identify Graphics
+ Chip Revision */
- unsigned char ujVBChipID; /* the ID of video bridge */
- /* defined in the data structure type */
- /* "XGI_VB_CHIP_TYPE" */
+ unsigned char ujVBChipID; /* the ID of video bridge */
+ /* defined in the data structure type */
+ /* "XGI_VB_CHIP_TYPE" */
- unsigned long ulCRT2LCDType; /* defined in the data structure type */
+ unsigned long ulCRT2LCDType; /* defined in the data structure type */
unsigned char(*pQueryVGAConfigSpace)(struct xgi_hw_device_info *,
unsigned long, unsigned long,
@@ -87,7 +86,5 @@
/* Additional IOCTL for communication xgifb <> X driver */
/* If changing this, xgifb.h must also be changed (for xgifb) */
-
-
#endif
diff --git a/drivers/staging/zcache/zcache.c b/drivers/staging/zcache/zcache.c
index b8a2b30..77ac2d4 100644
--- a/drivers/staging/zcache/zcache.c
+++ b/drivers/staging/zcache/zcache.c
@@ -1181,9 +1181,12 @@
/*
* zcache shrinker interface (only useful for ephemeral pages, so zbud only)
*/
-static int shrink_zcache_memory(struct shrinker *shrink, int nr, gfp_t gfp_mask)
+static int shrink_zcache_memory(struct shrinker *shrink,
+ struct shrink_control *sc)
{
int ret = -1;
+ int nr = sc->nr_to_scan;
+ gfp_t gfp_mask = sc->gfp_mask;
if (nr >= 0) {
if (!(gfp_mask & __GFP_FS))
diff --git a/drivers/telephony/ixj_pcmcia.c b/drivers/telephony/ixj_pcmcia.c
index d005b9e..05032e2 100644
--- a/drivers/telephony/ixj_pcmcia.c
+++ b/drivers/telephony/ixj_pcmcia.c
@@ -157,7 +157,7 @@
pcmcia_disable_device(link);
}
-static struct pcmcia_device_id ixj_ids[] = {
+static const struct pcmcia_device_id ixj_ids[] = {
PCMCIA_DEVICE_MANF_CARD(0x0257, 0x0600),
PCMCIA_DEVICE_NULL
};
diff --git a/drivers/tty/Kconfig b/drivers/tty/Kconfig
index 3fd7199..bd7cc05 100644
--- a/drivers/tty/Kconfig
+++ b/drivers/tty/Kconfig
@@ -319,3 +319,34 @@
This line discipline provides support for the GSM MUX protocol and
presents the mux as a set of 61 individual tty devices.
+config TRACE_ROUTER
+ tristate "Trace data router for MIPI P1149.7 cJTAG standard"
+ depends on TRACE_SINK
+ default n
+ help
+ The trace router uses the Linux tty line discipline framework to
+ route trace data coming from a tty port (say UART for example) to
+ the trace sink line discipline driver and to another tty port (say
+ USB). This is part of a solution for the MIPI P1149.7, compact JTAG,
+ standard, which is for debugging mobile devices. The PTI driver in
+ drivers/misc/pti.c defines the majority of this MIPI solution.
+
+ You should select this driver if the target kernel is meant for
+ a mobile device containing a modem. Then you will need to select
+ "Trace data sink for MIPI P1149.7 cJTAG standard" line discipline
+ driver.
+
+config TRACE_SINK
+ tristate "Trace data sink for MIPI P1149.7 cJTAG standard"
+ default n
+ help
+ The trace sink uses the Linux line discipline framework to receive
+ trace data coming from the trace router line discipline driver
+ to a user-defined tty port target, like USB.
+ This is to provide a way to extract modem trace data on
+ devices that do not have a PTI HW module, or just need modem
+ trace data to come out of a different HW output port.
+ This is part of a solution for the P1149.7, compact JTAG, standard.
+
+ If you select this option, you need to select
+ "Trace data router for MIPI P1149.7 cJTAG standard".
diff --git a/drivers/tty/Makefile b/drivers/tty/Makefile
index 690522f..ea89b0b 100644
--- a/drivers/tty/Makefile
+++ b/drivers/tty/Makefile
@@ -6,6 +6,8 @@
obj-$(CONFIG_MAGIC_SYSRQ) += sysrq.o
obj-$(CONFIG_N_HDLC) += n_hdlc.o
obj-$(CONFIG_N_GSM) += n_gsm.o
+obj-$(CONFIG_TRACE_ROUTER) += n_tracerouter.o
+obj-$(CONFIG_TRACE_SINK) += n_tracesink.o
obj-$(CONFIG_R3964) += n_r3964.o
obj-y += vt/
diff --git a/drivers/tty/amiserial.c b/drivers/tty/amiserial.c
index f214e50..2205795 100644
--- a/drivers/tty/amiserial.c
+++ b/drivers/tty/amiserial.c
@@ -1,6 +1,4 @@
/*
- * linux/drivers/char/amiserial.c
- *
* Serial driver for the amiga builtin port.
*
* This code was created by taking serial.c version 4.30 from kernel
diff --git a/drivers/tty/cyclades.c b/drivers/tty/cyclades.c
index c99728f..bfa05e8 100644
--- a/drivers/tty/cyclades.c
+++ b/drivers/tty/cyclades.c
@@ -3,8 +3,6 @@
#undef Z_EXT_CHARS_IN_BUFFER
/*
- * linux/drivers/char/cyclades.c
- *
* This file contains the driver for the Cyclades async multiport
* serial boards.
*
@@ -1445,13 +1443,11 @@
{
struct cyclades_card *card;
unsigned long flags;
- int channel;
if (!(info->port.flags & ASYNC_INITIALIZED))
return;
card = info->card;
- channel = info->line - card->first_line;
if (!cy_is_Z(card)) {
spin_lock_irqsave(&card->card_lock, flags);
@@ -1476,6 +1472,7 @@
spin_unlock_irqrestore(&card->card_lock, flags);
} else {
#ifdef CY_DEBUG_OPEN
+ int channel = info->line - card->first_line;
printk(KERN_DEBUG "cyc shutdown Z card %d, channel %d, "
"base_addr %p\n", card, channel, card->base_addr);
#endif
diff --git a/drivers/tty/ipwireless/Makefile b/drivers/tty/ipwireless/Makefile
index db80873d..fe2e173 100644
--- a/drivers/tty/ipwireless/Makefile
+++ b/drivers/tty/ipwireless/Makefile
@@ -1,6 +1,4 @@
#
-# drivers/char/pcmcia/ipwireless/Makefile
-#
# Makefile for the IPWireless driver
#
diff --git a/drivers/tty/ipwireless/main.c b/drivers/tty/ipwireless/main.c
index 444155a..655c794 100644
--- a/drivers/tty/ipwireless/main.c
+++ b/drivers/tty/ipwireless/main.c
@@ -33,7 +33,7 @@
#include <pcmcia/ss.h>
#include <pcmcia/ds.h>
-static struct pcmcia_device_id ipw_ids[] = {
+static const struct pcmcia_device_id ipw_ids[] = {
PCMCIA_DEVICE_MANF_CARD(0x02f2, 0x0100),
PCMCIA_DEVICE_MANF_CARD(0x02f2, 0x0200),
PCMCIA_DEVICE_NULL
diff --git a/drivers/tty/moxa.c b/drivers/tty/moxa.c
index 35b0c38..ba679ce 100644
--- a/drivers/tty/moxa.c
+++ b/drivers/tty/moxa.c
@@ -371,7 +371,7 @@
tmp.cflag = p->cflag;
else
tmp.cflag = ttyp->termios->c_cflag;
- tty_kref_put(tty);
+ tty_kref_put(ttyp);
copy:
if (copy_to_user(argm, &tmp, sizeof(tmp)))
return -EFAULT;
@@ -1129,7 +1129,6 @@
struct moxa_port *ch = container_of(port, struct moxa_port, port);
MoxaPortDisable(ch);
MoxaPortFlushData(ch, 2);
- clear_bit(ASYNCB_NORMAL_ACTIVE, &port->flags);
}
static int moxa_carrier_raised(struct tty_port *port)
@@ -1155,7 +1154,6 @@
struct moxa_board_conf *brd;
struct moxa_port *ch;
int port;
- int retval;
port = tty->index;
if (port == MAX_PORTS) {
@@ -1190,10 +1188,7 @@
mutex_unlock(&ch->port.mutex);
mutex_unlock(&moxa_openlock);
- retval = tty_port_block_til_ready(&ch->port, tty, filp);
- if (retval == 0)
- set_bit(ASYNCB_NORMAL_ACTIVE, &ch->port.flags);
- return retval;
+ return tty_port_block_til_ready(&ch->port, tty, filp);
}
static void moxa_close(struct tty_struct *tty, struct file *filp)
@@ -1207,14 +1202,15 @@
const unsigned char *buf, int count)
{
struct moxa_port *ch = tty->driver_data;
+ unsigned long flags;
int len;
if (ch == NULL)
return 0;
- spin_lock_bh(&moxa_lock);
+ spin_lock_irqsave(&moxa_lock, flags);
len = MoxaPortWriteData(tty, buf, count);
- spin_unlock_bh(&moxa_lock);
+ spin_unlock_irqrestore(&moxa_lock, flags);
set_bit(LOWWAIT, &ch->statusflags);
return len;
@@ -1281,10 +1277,8 @@
unsigned int set, unsigned int clear)
{
struct moxa_port *ch;
- int port;
int dtr, rts;
- port = tty->index;
mutex_lock(&moxa_openlock);
ch = tty->driver_data;
if (!ch) {
@@ -1756,11 +1750,9 @@
speed_t baud)
{
void __iomem *ofsAddr;
- tcflag_t cflag;
tcflag_t mode = 0;
ofsAddr = port->tableAddr;
- cflag = termio->c_cflag; /* termio->c_cflag */
mode = termio->c_cflag & CSIZE;
if (mode == CS5)
diff --git a/drivers/tty/n_gsm.c b/drivers/tty/n_gsm.c
index 77623b9..a4c42a7 100644
--- a/drivers/tty/n_gsm.c
+++ b/drivers/tty/n_gsm.c
@@ -526,19 +526,6 @@
return olen;
}
-static void hex_packet(const unsigned char *p, int len)
-{
- int i;
- for (i = 0; i < len; i++) {
- if (i && (i % 16) == 0) {
- pr_cont("\n");
- pr_debug("");
- }
- pr_cont("%02X ", *p++);
- }
- pr_cont("\n");
-}
-
/**
* gsm_send - send a control frame
* @gsm: our GSM mux
@@ -685,10 +672,10 @@
len = msg->len + 2;
}
- if (debug & 4) {
- pr_debug("gsm_data_kick:\n");
- hex_packet(gsm->txframe, len);
- }
+ if (debug & 4)
+ print_hex_dump_bytes("gsm_data_kick: ",
+ DUMP_PREFIX_OFFSET,
+ gsm->txframe, len);
if (gsm->output(gsm, gsm->txframe + skip_sof,
len - skip_sof) < 0)
@@ -2095,10 +2082,9 @@
set_bit(TTY_DO_WRITE_WAKEUP, &gsm->tty->flags);
return -ENOSPC;
}
- if (debug & 4) {
- pr_debug("-->%d bytes out\n", len);
- hex_packet(data, len);
- }
+ if (debug & 4)
+ print_hex_dump_bytes("gsmld_output: ", DUMP_PREFIX_OFFSET,
+ data, len);
gsm->tty->ops->write(gsm->tty, data, len);
return len;
}
@@ -2142,8 +2128,8 @@
gsm->tty = NULL;
}
-static void gsmld_receive_buf(struct tty_struct *tty, const unsigned char *cp,
- char *fp, int count)
+static unsigned int gsmld_receive_buf(struct tty_struct *tty,
+ const unsigned char *cp, char *fp, int count)
{
struct gsm_mux *gsm = tty->disc_data;
const unsigned char *dp;
@@ -2152,10 +2138,9 @@
char buf[64];
char flags;
- if (debug & 4) {
- pr_debug("Inbytes %dd\n", count);
- hex_packet(cp, count);
- }
+ if (debug & 4)
+ print_hex_dump_bytes("gsmld_receive: ", DUMP_PREFIX_OFFSET,
+ cp, count);
for (i = count, dp = cp, f = fp; i; i--, dp++) {
flags = *f++;
@@ -2177,6 +2162,8 @@
}
/* FASYNC if needed ? */
/* If clogged call tty_throttle(tty); */
+
+ return count;
}
/**
diff --git a/drivers/tty/n_hdlc.c b/drivers/tty/n_hdlc.c
index cea5603..cac6663 100644
--- a/drivers/tty/n_hdlc.c
+++ b/drivers/tty/n_hdlc.c
@@ -188,8 +188,8 @@
poll_table *wait);
static int n_hdlc_tty_open(struct tty_struct *tty);
static void n_hdlc_tty_close(struct tty_struct *tty);
-static void n_hdlc_tty_receive(struct tty_struct *tty, const __u8 *cp,
- char *fp, int count);
+static unsigned int n_hdlc_tty_receive(struct tty_struct *tty,
+ const __u8 *cp, char *fp, int count);
static void n_hdlc_tty_wakeup(struct tty_struct *tty);
#define bset(p,b) ((p)[(b) >> 5] |= (1 << ((b) & 0x1f)))
@@ -509,8 +509,8 @@
* Called by tty low level driver when receive data is available. Data is
* interpreted as one HDLC frame.
*/
-static void n_hdlc_tty_receive(struct tty_struct *tty, const __u8 *data,
- char *flags, int count)
+static unsigned int n_hdlc_tty_receive(struct tty_struct *tty,
+ const __u8 *data, char *flags, int count)
{
register struct n_hdlc *n_hdlc = tty2n_hdlc (tty);
register struct n_hdlc_buf *buf;
@@ -521,20 +521,20 @@
/* This can happen if stuff comes in on the backup tty */
if (!n_hdlc || tty != n_hdlc->tty)
- return;
+ return -ENODEV;
/* verify line is using HDLC discipline */
if (n_hdlc->magic != HDLC_MAGIC) {
printk("%s(%d) line not using HDLC discipline\n",
__FILE__,__LINE__);
- return;
+ return -EINVAL;
}
if ( count>maxframe ) {
if (debuglevel >= DEBUG_LEVEL_INFO)
printk("%s(%d) rx count>maxframesize, data discarded\n",
__FILE__,__LINE__);
- return;
+ return -EINVAL;
}
/* get a free HDLC buffer */
@@ -550,7 +550,7 @@
if (debuglevel >= DEBUG_LEVEL_INFO)
printk("%s(%d) no more rx buffers, data discarded\n",
__FILE__,__LINE__);
- return;
+ return -EINVAL;
}
/* copy received data to HDLC buffer */
@@ -565,6 +565,8 @@
if (n_hdlc->tty->fasync != NULL)
kill_fasync (&n_hdlc->tty->fasync, SIGIO, POLL_IN);
+ return count;
+
} /* end of n_hdlc_tty_receive() */
/**
diff --git a/drivers/tty/n_r3964.c b/drivers/tty/n_r3964.c
index 5c6c314..a4bc39c 100644
--- a/drivers/tty/n_r3964.c
+++ b/drivers/tty/n_r3964.c
@@ -139,8 +139,8 @@
static void r3964_set_termios(struct tty_struct *tty, struct ktermios *old);
static unsigned int r3964_poll(struct tty_struct *tty, struct file *file,
struct poll_table_struct *wait);
-static void r3964_receive_buf(struct tty_struct *tty, const unsigned char *cp,
- char *fp, int count);
+static unsigned int r3964_receive_buf(struct tty_struct *tty,
+ const unsigned char *cp, char *fp, int count);
static struct tty_ldisc_ops tty_ldisc_N_R3964 = {
.owner = THIS_MODULE,
@@ -1239,8 +1239,8 @@
return result;
}
-static void r3964_receive_buf(struct tty_struct *tty, const unsigned char *cp,
- char *fp, int count)
+static unsigned int r3964_receive_buf(struct tty_struct *tty,
+ const unsigned char *cp, char *fp, int count)
{
struct r3964_info *pInfo = tty->disc_data;
const unsigned char *p;
@@ -1257,6 +1257,8 @@
}
}
+
+ return count;
}
MODULE_LICENSE("GPL");
diff --git a/drivers/tty/n_tracerouter.c b/drivers/tty/n_tracerouter.c
new file mode 100644
index 0000000..1f063d3
--- /dev/null
+++ b/drivers/tty/n_tracerouter.c
@@ -0,0 +1,243 @@
+/*
+ * n_tracerouter.c - Trace data router through tty space
+ *
+ * Copyright (C) Intel 2011
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ * This trace router uses the Linux line discipline framework to route
+ * trace data coming from a HW Modem to a PTI (Parallel Trace Module) port.
+ * The solution is not specific to a HW modem and this line disciple can
+ * be used to route any stream of data in kernel space.
+ * This is part of a solution for the P1149.7, compact JTAG, standard.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/ioctl.h>
+#include <linux/tty.h>
+#include <linux/tty_ldisc.h>
+#include <linux/errno.h>
+#include <linux/string.h>
+#include <linux/mutex.h>
+#include <linux/slab.h>
+#include <asm-generic/bug.h>
+#include "n_tracesink.h"
+
+/*
+ * Other ldisc drivers use 65536 which basically means,
+ * 'I can always accept 64k' and flow control is off.
+ * This number is deemed appropriate for this driver.
+ */
+#define RECEIVE_ROOM 65536
+#define DRIVERNAME "n_tracerouter"
+
+/*
+ * struct to hold private configuration data for this ldisc.
+ * opencalled is used to hold if this ldisc has been opened.
+ * kref_tty holds the tty reference the ldisc sits on top of.
+ */
+struct tracerouter_data {
+ u8 opencalled;
+ struct tty_struct *kref_tty;
+};
+static struct tracerouter_data *tr_data;
+
+/* lock for when tty reference is being used */
+static DEFINE_MUTEX(routelock);
+
+/**
+ * n_tracerouter_open() - Called when a tty is opened by a SW entity.
+ * @tty: terminal device to the ldisc.
+ *
+ * Return:
+ * 0 for success.
+ *
+ * Caveats: This should only be opened one time per SW entity.
+ */
+static int n_tracerouter_open(struct tty_struct *tty)
+{
+ int retval = -EEXIST;
+
+ mutex_lock(&routelock);
+ if (tr_data->opencalled == 0) {
+
+ tr_data->kref_tty = tty_kref_get(tty);
+ if (tr_data->kref_tty == NULL) {
+ retval = -EFAULT;
+ } else {
+ tr_data->opencalled = 1;
+ tty->disc_data = tr_data;
+ tty->receive_room = RECEIVE_ROOM;
+ tty_driver_flush_buffer(tty);
+ retval = 0;
+ }
+ }
+ mutex_unlock(&routelock);
+ return retval;
+}
+
+/**
+ * n_tracerouter_close() - close connection
+ * @tty: terminal device to the ldisc.
+ *
+ * Called when a software entity wants to close a connection.
+ */
+static void n_tracerouter_close(struct tty_struct *tty)
+{
+ struct tracerouter_data *tptr = tty->disc_data;
+
+ mutex_lock(&routelock);
+ WARN_ON(tptr->kref_tty != tr_data->kref_tty);
+ tty_driver_flush_buffer(tty);
+ tty_kref_put(tr_data->kref_tty);
+ tr_data->kref_tty = NULL;
+ tr_data->opencalled = 0;
+ tty->disc_data = NULL;
+ mutex_unlock(&routelock);
+}
+
+/**
+ * n_tracerouter_read() - read request from user space
+ * @tty: terminal device passed into the ldisc.
+ * @file: pointer to open file object.
+ * @buf: pointer to the data buffer that gets eventually returned.
+ * @nr: number of bytes of the data buffer that is returned.
+ *
+ * function that allows read() functionality in userspace. By default if this
+ * is not implemented it returns -EIO. This module is functioning like a
+ * router via n_tracerouter_receivebuf(), and there is no real requirement
+ * to implement this function. However, an error return value other than
+ * -EIO should be used just to show that there was an intent not to have
+ * this function implemented. Return value based on read() man pages.
+ *
+ * Return:
+ * -EINVAL
+ */
+static ssize_t n_tracerouter_read(struct tty_struct *tty, struct file *file,
+ unsigned char __user *buf, size_t nr) {
+ return -EINVAL;
+}
+
+/**
+ * n_tracerouter_write() - Function that allows write() in userspace.
+ * @tty: terminal device passed into the ldisc.
+ * @file: pointer to open file object.
+ * @buf: pointer to the data buffer that gets eventually returned.
+ * @nr: number of bytes of the data buffer that is returned.
+ *
+ * By default if this is not implemented, it returns -EIO.
+ * This should not be implemented, ever, because
+ * 1. this driver is functioning like a router via
+ * n_tracerouter_receivebuf()
+ * 2. No writes to HW will ever go through this line discpline driver.
+ * However, an error return value other than -EIO should be used
+ * just to show that there was an intent not to have this function
+ * implemented. Return value based on write() man pages.
+ *
+ * Return:
+ * -EINVAL
+ */
+static ssize_t n_tracerouter_write(struct tty_struct *tty, struct file *file,
+ const unsigned char *buf, size_t nr) {
+ return -EINVAL;
+}
+
+/**
+ * n_tracerouter_receivebuf() - Routing function for driver.
+ * @tty: terminal device passed into the ldisc. It's assumed
+ * tty will never be NULL.
+ * @cp: buffer, block of characters to be eventually read by
+ * someone, somewhere (user read() call or some kernel function).
+ * @fp: flag buffer.
+ * @count: number of characters (aka, bytes) in cp.
+ *
+ * This function takes the input buffer, cp, and passes it to
+ * an external API function for processing.
+ */
+static void n_tracerouter_receivebuf(struct tty_struct *tty,
+ const unsigned char *cp,
+ char *fp, int count)
+{
+ mutex_lock(&routelock);
+ n_tracesink_datadrain((u8 *) cp, count);
+ mutex_unlock(&routelock);
+}
+
+/*
+ * Flush buffer is not impelemented as the ldisc has no internal buffering
+ * so the tty_driver_flush_buffer() is sufficient for this driver's needs.
+ */
+
+static struct tty_ldisc_ops tty_ptirouter_ldisc = {
+ .owner = THIS_MODULE,
+ .magic = TTY_LDISC_MAGIC,
+ .name = DRIVERNAME,
+ .open = n_tracerouter_open,
+ .close = n_tracerouter_close,
+ .read = n_tracerouter_read,
+ .write = n_tracerouter_write,
+ .receive_buf = n_tracerouter_receivebuf
+};
+
+/**
+ * n_tracerouter_init - module initialisation
+ *
+ * Registers this module as a line discipline driver.
+ *
+ * Return:
+ * 0 for success, any other value error.
+ */
+static int __init n_tracerouter_init(void)
+{
+ int retval;
+
+ tr_data = kzalloc(sizeof(struct tracerouter_data), GFP_KERNEL);
+ if (tr_data == NULL)
+ return -ENOMEM;
+
+
+ /* Note N_TRACEROUTER is defined in linux/tty.h */
+ retval = tty_register_ldisc(N_TRACEROUTER, &tty_ptirouter_ldisc);
+ if (retval < 0) {
+ pr_err("%s: Registration failed: %d\n", __func__, retval);
+ kfree(tr_data);
+ }
+ return retval;
+}
+
+/**
+ * n_tracerouter_exit - module unload
+ *
+ * Removes this module as a line discipline driver.
+ */
+static void __exit n_tracerouter_exit(void)
+{
+ int retval = tty_unregister_ldisc(N_TRACEROUTER);
+
+ if (retval < 0)
+ pr_err("%s: Unregistration failed: %d\n", __func__, retval);
+ else
+ kfree(tr_data);
+}
+
+module_init(n_tracerouter_init);
+module_exit(n_tracerouter_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Jay Freyensee");
+MODULE_ALIAS_LDISC(N_TRACEROUTER);
+MODULE_DESCRIPTION("Trace router ldisc driver");
diff --git a/drivers/tty/n_tracesink.c b/drivers/tty/n_tracesink.c
new file mode 100644
index 0000000..ddce58b
--- /dev/null
+++ b/drivers/tty/n_tracesink.c
@@ -0,0 +1,238 @@
+/*
+ * n_tracesink.c - Trace data router and sink path through tty space.
+ *
+ * Copyright (C) Intel 2011
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ * The trace sink uses the Linux line discipline framework to receive
+ * trace data coming from the PTI source line discipline driver
+ * to a user-desired tty port, like USB.
+ * This is to provide a way to extract modem trace data on
+ * devices that do not have a PTI HW module, or just need modem
+ * trace data to come out of a different HW output port.
+ * This is part of a solution for the P1149.7, compact JTAG, standard.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/types.h>
+#include <linux/ioctl.h>
+#include <linux/tty.h>
+#include <linux/tty_ldisc.h>
+#include <linux/errno.h>
+#include <linux/string.h>
+#include <asm-generic/bug.h>
+#include "n_tracesink.h"
+
+/*
+ * Other ldisc drivers use 65536 which basically means,
+ * 'I can always accept 64k' and flow control is off.
+ * This number is deemed appropriate for this driver.
+ */
+#define RECEIVE_ROOM 65536
+#define DRIVERNAME "n_tracesink"
+
+/*
+ * there is a quirk with this ldisc is he can write data
+ * to a tty from anyone calling his kernel API, which
+ * meets customer requirements in the drivers/misc/pti.c
+ * project. So he needs to know when he can and cannot write when
+ * the API is called. In theory, the API can be called
+ * after an init() but before a successful open() which
+ * would crash the system if tty is not checked.
+ */
+static struct tty_struct *this_tty;
+static DEFINE_MUTEX(writelock);
+
+/**
+ * n_tracesink_open() - Called when a tty is opened by a SW entity.
+ * @tty: terminal device to the ldisc.
+ *
+ * Return:
+ * 0 for success,
+ * -EFAULT = couldn't get a tty kref n_tracesink will sit
+ * on top of
+ * -EEXIST = open() called successfully once and it cannot
+ * be called again.
+ *
+ * Caveats: open() should only be successful the first time a
+ * SW entity calls it.
+ */
+static int n_tracesink_open(struct tty_struct *tty)
+{
+ int retval = -EEXIST;
+
+ mutex_lock(&writelock);
+ if (this_tty == NULL) {
+ this_tty = tty_kref_get(tty);
+ if (this_tty == NULL) {
+ retval = -EFAULT;
+ } else {
+ tty->disc_data = this_tty;
+ tty_driver_flush_buffer(tty);
+ retval = 0;
+ }
+ }
+ mutex_unlock(&writelock);
+
+ return retval;
+}
+
+/**
+ * n_tracesink_close() - close connection
+ * @tty: terminal device to the ldisc.
+ *
+ * Called when a software entity wants to close a connection.
+ */
+static void n_tracesink_close(struct tty_struct *tty)
+{
+ mutex_lock(&writelock);
+ tty_driver_flush_buffer(tty);
+ tty_kref_put(this_tty);
+ this_tty = NULL;
+ tty->disc_data = NULL;
+ mutex_unlock(&writelock);
+}
+
+/**
+ * n_tracesink_read() - read request from user space
+ * @tty: terminal device passed into the ldisc.
+ * @file: pointer to open file object.
+ * @buf: pointer to the data buffer that gets eventually returned.
+ * @nr: number of bytes of the data buffer that is returned.
+ *
+ * function that allows read() functionality in userspace. By default if this
+ * is not implemented it returns -EIO. This module is functioning like a
+ * router via n_tracesink_receivebuf(), and there is no real requirement
+ * to implement this function. However, an error return value other than
+ * -EIO should be used just to show that there was an intent not to have
+ * this function implemented. Return value based on read() man pages.
+ *
+ * Return:
+ * -EINVAL
+ */
+static ssize_t n_tracesink_read(struct tty_struct *tty, struct file *file,
+ unsigned char __user *buf, size_t nr) {
+ return -EINVAL;
+}
+
+/**
+ * n_tracesink_write() - Function that allows write() in userspace.
+ * @tty: terminal device passed into the ldisc.
+ * @file: pointer to open file object.
+ * @buf: pointer to the data buffer that gets eventually returned.
+ * @nr: number of bytes of the data buffer that is returned.
+ *
+ * By default if this is not implemented, it returns -EIO.
+ * This should not be implemented, ever, because
+ * 1. this driver is functioning like a router via
+ * n_tracesink_receivebuf()
+ * 2. No writes to HW will ever go through this line discpline driver.
+ * However, an error return value other than -EIO should be used
+ * just to show that there was an intent not to have this function
+ * implemented. Return value based on write() man pages.
+ *
+ * Return:
+ * -EINVAL
+ */
+static ssize_t n_tracesink_write(struct tty_struct *tty, struct file *file,
+ const unsigned char *buf, size_t nr) {
+ return -EINVAL;
+}
+
+/**
+ * n_tracesink_datadrain() - Kernel API function used to route
+ * trace debugging data to user-defined
+ * port like USB.
+ *
+ * @buf: Trace debuging data buffer to write to tty target
+ * port. Null value will return with no write occurring.
+ * @count: Size of buf. Value of 0 or a negative number will
+ * return with no write occuring.
+ *
+ * Caveat: If this line discipline does not set the tty it sits
+ * on top of via an open() call, this API function will not
+ * call the tty's write() call because it will have no pointer
+ * to call the write().
+ */
+void n_tracesink_datadrain(u8 *buf, int count)
+{
+ mutex_lock(&writelock);
+
+ if ((buf != NULL) && (count > 0) && (this_tty != NULL))
+ this_tty->ops->write(this_tty, buf, count);
+
+ mutex_unlock(&writelock);
+}
+EXPORT_SYMBOL_GPL(n_tracesink_datadrain);
+
+/*
+ * Flush buffer is not impelemented as the ldisc has no internal buffering
+ * so the tty_driver_flush_buffer() is sufficient for this driver's needs.
+ */
+
+/*
+ * tty_ldisc function operations for this driver.
+ */
+static struct tty_ldisc_ops tty_n_tracesink = {
+ .owner = THIS_MODULE,
+ .magic = TTY_LDISC_MAGIC,
+ .name = DRIVERNAME,
+ .open = n_tracesink_open,
+ .close = n_tracesink_close,
+ .read = n_tracesink_read,
+ .write = n_tracesink_write
+};
+
+/**
+ * n_tracesink_init- module initialisation
+ *
+ * Registers this module as a line discipline driver.
+ *
+ * Return:
+ * 0 for success, any other value error.
+ */
+static int __init n_tracesink_init(void)
+{
+ /* Note N_TRACESINK is defined in linux/tty.h */
+ int retval = tty_register_ldisc(N_TRACESINK, &tty_n_tracesink);
+
+ if (retval < 0)
+ pr_err("%s: Registration failed: %d\n", __func__, retval);
+
+ return retval;
+}
+
+/**
+ * n_tracesink_exit - module unload
+ *
+ * Removes this module as a line discipline driver.
+ */
+static void __exit n_tracesink_exit(void)
+{
+ int retval = tty_unregister_ldisc(N_TRACESINK);
+
+ if (retval < 0)
+ pr_err("%s: Unregistration failed: %d\n", __func__, retval);
+}
+
+module_init(n_tracesink_init);
+module_exit(n_tracesink_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Jay Freyensee");
+MODULE_ALIAS_LDISC(N_TRACESINK);
+MODULE_DESCRIPTION("Trace sink ldisc driver");
diff --git a/drivers/tty/n_tracesink.h b/drivers/tty/n_tracesink.h
new file mode 100644
index 0000000..a68bb44
--- /dev/null
+++ b/drivers/tty/n_tracesink.h
@@ -0,0 +1,36 @@
+/*
+ * n_tracesink.h - Kernel driver API to route trace data in kernel space.
+ *
+ * Copyright (C) Intel 2011
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ * The PTI (Parallel Trace Interface) driver directs trace data routed from
+ * various parts in the system out through the Intel Penwell PTI port and
+ * out of the mobile device for analysis with a debugging tool
+ * (Lauterbach, Fido). This is part of a solution for the MIPI P1149.7,
+ * compact JTAG, standard.
+ *
+ * This header file is used by n_tracerouter to be able to send the
+ * data of it's tty port to the tty port this module sits. This
+ * mechanism can also be used independent of the PTI module.
+ *
+ */
+
+#ifndef N_TRACESINK_H_
+#define N_TRACESINK_H_
+
+void n_tracesink_datadrain(u8 *buf, int count);
+
+#endif
diff --git a/drivers/tty/n_tty.c b/drivers/tty/n_tty.c
index 0ad3288..95d0a9c 100644
--- a/drivers/tty/n_tty.c
+++ b/drivers/tty/n_tty.c
@@ -81,38 +81,6 @@
return put_user(x, ptr);
}
-/**
- * n_tty_set__room - receive space
- * @tty: terminal
- *
- * Called by the driver to find out how much data it is
- * permitted to feed to the line discipline without any being lost
- * and thus to manage flow control. Not serialized. Answers for the
- * "instant".
- */
-
-static void n_tty_set_room(struct tty_struct *tty)
-{
- /* tty->read_cnt is not read locked ? */
- int left = N_TTY_BUF_SIZE - tty->read_cnt - 1;
- int old_left;
-
- /*
- * If we are doing input canonicalization, and there are no
- * pending newlines, let characters through without limit, so
- * that erase characters will be handled. Other excess
- * characters will be beeped.
- */
- if (left <= 0)
- left = tty->icanon && !tty->canon_data;
- old_left = tty->receive_room;
- tty->receive_room = left;
-
- /* Did this open up the receive buffer? We may need to flip */
- if (left && !old_left)
- schedule_work(&tty->buf.work);
-}
-
static void put_tty_queue_nolock(unsigned char c, struct tty_struct *tty)
{
if (tty->read_cnt < N_TTY_BUF_SIZE) {
@@ -184,7 +152,6 @@
tty->canon_head = tty->canon_data = tty->erasing = 0;
memset(&tty->read_flags, 0, sizeof tty->read_flags);
- n_tty_set_room(tty);
check_unthrottle(tty);
}
@@ -1360,17 +1327,19 @@
* calls one at a time and in order (or using flush_to_ldisc)
*/
-static void n_tty_receive_buf(struct tty_struct *tty, const unsigned char *cp,
- char *fp, int count)
+static unsigned int n_tty_receive_buf(struct tty_struct *tty,
+ const unsigned char *cp, char *fp, int count)
{
const unsigned char *p;
char *f, flags = TTY_NORMAL;
int i;
char buf[64];
unsigned long cpuflags;
+ int left;
+ int ret = 0;
if (!tty->read_buf)
- return;
+ return 0;
if (tty->real_raw) {
spin_lock_irqsave(&tty->read_lock, cpuflags);
@@ -1380,6 +1349,7 @@
memcpy(tty->read_buf + tty->read_head, cp, i);
tty->read_head = (tty->read_head + i) & (N_TTY_BUF_SIZE-1);
tty->read_cnt += i;
+ ret += i;
cp += i;
count -= i;
@@ -1389,8 +1359,10 @@
memcpy(tty->read_buf + tty->read_head, cp, i);
tty->read_head = (tty->read_head + i) & (N_TTY_BUF_SIZE-1);
tty->read_cnt += i;
+ ret += i;
spin_unlock_irqrestore(&tty->read_lock, cpuflags);
} else {
+ ret = count;
for (i = count, p = cp, f = fp; i; i--, p++) {
if (f)
flags = *f++;
@@ -1418,8 +1390,6 @@
tty->ops->flush_chars(tty);
}
- n_tty_set_room(tty);
-
if ((!tty->icanon && (tty->read_cnt >= tty->minimum_to_wake)) ||
L_EXTPROC(tty)) {
kill_fasync(&tty->fasync, SIGIO, POLL_IN);
@@ -1432,8 +1402,12 @@
* mode. We don't want to throttle the driver if we're in
* canonical mode and don't have a newline yet!
*/
- if (tty->receive_room < TTY_THRESHOLD_THROTTLE)
+ left = N_TTY_BUF_SIZE - tty->read_cnt - 1;
+
+ if (left < TTY_THRESHOLD_THROTTLE)
tty_throttle(tty);
+
+ return ret;
}
int is_ignored(int sig)
@@ -1477,7 +1451,6 @@
if (test_bit(TTY_HW_COOK_IN, &tty->flags)) {
tty->raw = 1;
tty->real_raw = 1;
- n_tty_set_room(tty);
return;
}
if (I_ISTRIP(tty) || I_IUCLC(tty) || I_IGNCR(tty) ||
@@ -1530,7 +1503,6 @@
else
tty->real_raw = 0;
}
- n_tty_set_room(tty);
/* The termios change make the tty ready for I/O */
wake_up_interruptible(&tty->write_wait);
wake_up_interruptible(&tty->read_wait);
@@ -1812,8 +1784,6 @@
retval = -ERESTARTSYS;
break;
}
- /* FIXME: does n_tty_set_room need locking ? */
- n_tty_set_room(tty);
timeout = schedule_timeout(timeout);
continue;
}
@@ -1885,10 +1855,8 @@
* longer than TTY_THRESHOLD_UNTHROTTLE in canonical mode,
* we won't get any more characters.
*/
- if (n_tty_chars_in_buffer(tty) <= TTY_THRESHOLD_UNTHROTTLE) {
- n_tty_set_room(tty);
+ if (n_tty_chars_in_buffer(tty) <= TTY_THRESHOLD_UNTHROTTLE)
check_unthrottle(tty);
- }
if (b - buf >= minimum)
break;
@@ -1910,7 +1878,6 @@
} else if (test_and_clear_bit(TTY_PUSH, &tty->flags))
goto do_it_again;
- n_tty_set_room(tty);
return retval;
}
diff --git a/drivers/tty/nozomi.c b/drivers/tty/nozomi.c
index fd0a9852..b1aecc7 100644
--- a/drivers/tty/nozomi.c
+++ b/drivers/tty/nozomi.c
@@ -364,8 +364,6 @@
u8 toggle_ul;
u16 token_dl;
- /* mutex to ensure one access patch to this port */
- struct mutex tty_sem;
wait_queue_head_t tty_wait;
struct async_icount tty_icount;
@@ -1431,8 +1429,8 @@
}
for (i = PORT_MDM; i < MAX_PORT; i++) {
- if (kfifo_alloc(&dc->port[i].fifo_ul,
- FIFO_BUFFER_SIZE_UL, GFP_ATOMIC)) {
+ if (kfifo_alloc(&dc->port[i].fifo_ul, FIFO_BUFFER_SIZE_UL,
+ GFP_KERNEL)) {
dev_err(&pdev->dev,
"Could not allocate kfifo buffer\n");
ret = -ENOMEM;
@@ -1474,7 +1472,6 @@
struct device *tty_dev;
struct port *port = &dc->port[i];
port->dc = dc;
- mutex_init(&port->tty_sem);
tty_port_init(&port->port);
port->port.ops = &noz_tty_port_ops;
tty_dev = tty_register_device(ntty_driver, dc->index_start + i,
@@ -1688,13 +1685,6 @@
if (!dc || !port)
return -ENODEV;
- mutex_lock(&port->tty_sem);
-
- if (unlikely(!port->port.count)) {
- DBG1(" ");
- goto exit;
- }
-
rval = kfifo_in(&port->fifo_ul, (unsigned char *)buffer, count);
/* notify card */
@@ -1719,7 +1709,6 @@
spin_unlock_irqrestore(&dc->spin_mutex, flags);
exit:
- mutex_unlock(&port->tty_sem);
return rval;
}
@@ -1738,12 +1727,9 @@
int room = 4096;
const struct nozomi *dc = get_dc_by_tty(tty);
- if (dc) {
- mutex_lock(&port->tty_sem);
- if (port->port.count)
- room = kfifo_avail(&port->fifo_ul);
- mutex_unlock(&port->tty_sem);
- }
+ if (dc)
+ room = kfifo_avail(&port->fifo_ul);
+
return room;
}
@@ -1889,11 +1875,6 @@
goto exit_in_buffer;
}
- if (unlikely(!port->port.count)) {
- dev_err(&dc->pdev->dev, "No tty open?\n");
- goto exit_in_buffer;
- }
-
rval = kfifo_len(&port->fifo_ul);
exit_in_buffer:
diff --git a/drivers/tty/pty.c b/drivers/tty/pty.c
index 2107747..98b6e3b 100644
--- a/drivers/tty/pty.c
+++ b/drivers/tty/pty.c
@@ -1,6 +1,4 @@
/*
- * linux/drivers/char/pty.c
- *
* Copyright (C) 1991, 1992 Linus Torvalds
*
* Added support for a Unix98-style ptmx device.
@@ -295,8 +293,8 @@
return -ENOMEM;
if (!try_module_get(driver->other->owner)) {
/* This cannot in fact currently happen */
- free_tty_struct(o_tty);
- return -ENOMEM;
+ retval = -ENOMEM;
+ goto err_free_tty;
}
initialize_tty_struct(o_tty, driver->other, idx);
@@ -304,13 +302,11 @@
the easy way .. */
retval = tty_init_termios(tty);
if (retval)
- goto free_mem_out;
+ goto err_deinit_tty;
retval = tty_init_termios(o_tty);
- if (retval) {
- tty_free_termios(tty);
- goto free_mem_out;
- }
+ if (retval)
+ goto err_free_termios;
/*
* Everything allocated ... set up the o_tty structure.
@@ -327,10 +323,14 @@
tty->count++;
driver->ttys[idx] = tty;
return 0;
-free_mem_out:
+err_free_termios:
+ tty_free_termios(tty);
+err_deinit_tty:
+ deinitialize_tty_struct(o_tty);
module_put(o_tty->driver->owner);
+err_free_tty:
free_tty_struct(o_tty);
- return -ENOMEM;
+ return retval;
}
static int pty_bsd_ioctl(struct tty_struct *tty,
@@ -559,20 +559,19 @@
return -ENOMEM;
if (!try_module_get(driver->other->owner)) {
/* This cannot in fact currently happen */
- free_tty_struct(o_tty);
- return -ENOMEM;
+ goto err_free_tty;
}
initialize_tty_struct(o_tty, driver->other, idx);
tty->termios = kzalloc(sizeof(struct ktermios[2]), GFP_KERNEL);
if (tty->termios == NULL)
- goto free_mem_out;
+ goto err_free_mem;
*tty->termios = driver->init_termios;
tty->termios_locked = tty->termios + 1;
o_tty->termios = kzalloc(sizeof(struct ktermios[2]), GFP_KERNEL);
if (o_tty->termios == NULL)
- goto free_mem_out;
+ goto err_free_mem;
*o_tty->termios = driver->other->init_termios;
o_tty->termios_locked = o_tty->termios + 1;
@@ -591,11 +590,13 @@
tty->count++;
pty_count++;
return 0;
-free_mem_out:
+err_free_mem:
+ deinitialize_tty_struct(o_tty);
kfree(o_tty->termios);
- module_put(o_tty->driver->owner);
- free_tty_struct(o_tty);
kfree(tty->termios);
+ module_put(o_tty->driver->owner);
+err_free_tty:
+ free_tty_struct(o_tty);
return -ENOMEM;
}
diff --git a/drivers/tty/rocket.c b/drivers/tty/rocket.c
index 036feeb..13043e8 100644
--- a/drivers/tty/rocket.c
+++ b/drivers/tty/rocket.c
@@ -1380,7 +1380,6 @@
static void rp_throttle(struct tty_struct *tty)
{
struct r_port *info = tty->driver_data;
- CHANNEL_t *cp;
#ifdef ROCKET_DEBUG_THROTTLE
printk(KERN_INFO "throttle %s: %d....\n", tty->name,
@@ -1390,7 +1389,6 @@
if (rocket_paranoia_check(info, "rp_throttle"))
return;
- cp = &info->channel;
if (I_IXOFF(tty))
rp_send_xchar(tty, STOP_CHAR(tty));
@@ -1400,7 +1398,6 @@
static void rp_unthrottle(struct tty_struct *tty)
{
struct r_port *info = tty->driver_data;
- CHANNEL_t *cp;
#ifdef ROCKET_DEBUG_THROTTLE
printk(KERN_INFO "unthrottle %s: %d....\n", tty->name,
tty->ldisc.chars_in_buffer(tty));
@@ -1409,7 +1406,6 @@
if (rocket_paranoia_check(info, "rp_throttle"))
return;
- cp = &info->channel;
if (I_IXOFF(tty))
rp_send_xchar(tty, START_CHAR(tty));
@@ -1722,13 +1718,10 @@
static int rp_chars_in_buffer(struct tty_struct *tty)
{
struct r_port *info = tty->driver_data;
- CHANNEL_t *cp;
if (rocket_paranoia_check(info, "rp_chars_in_buffer"))
return 0;
- cp = &info->channel;
-
#ifdef ROCKET_DEBUG_WRITE
printk(KERN_INFO "rp_chars_in_buffer returns %d...\n", info->xmit_cnt);
#endif
@@ -1779,7 +1772,6 @@
{
int num_aiops, aiop, max_num_aiops, num_chan, chan;
unsigned int aiopio[MAX_AIOPS_PER_BOARD];
- char *str, *board_type;
CONTROLLER_t *ctlp;
int fast_clock = 0;
@@ -1800,7 +1792,6 @@
/* Depending on the model, set up some config variables */
switch (dev->device) {
case PCI_DEVICE_ID_RP4QUAD:
- str = "Quadcable";
max_num_aiops = 1;
ports_per_aiop = 4;
rocketModel[i].model = MODEL_RP4QUAD;
@@ -1808,42 +1799,36 @@
rocketModel[i].numPorts = 4;
break;
case PCI_DEVICE_ID_RP8OCTA:
- str = "Octacable";
max_num_aiops = 1;
rocketModel[i].model = MODEL_RP8OCTA;
strcpy(rocketModel[i].modelString, "RocketPort 8 port w/octa cable");
rocketModel[i].numPorts = 8;
break;
case PCI_DEVICE_ID_URP8OCTA:
- str = "Octacable";
max_num_aiops = 1;
rocketModel[i].model = MODEL_UPCI_RP8OCTA;
strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/octa cable");
rocketModel[i].numPorts = 8;
break;
case PCI_DEVICE_ID_RP8INTF:
- str = "8";
max_num_aiops = 1;
rocketModel[i].model = MODEL_RP8INTF;
strcpy(rocketModel[i].modelString, "RocketPort 8 port w/external I/F");
rocketModel[i].numPorts = 8;
break;
case PCI_DEVICE_ID_URP8INTF:
- str = "8";
max_num_aiops = 1;
rocketModel[i].model = MODEL_UPCI_RP8INTF;
strcpy(rocketModel[i].modelString, "RocketPort UPCI 8 port w/external I/F");
rocketModel[i].numPorts = 8;
break;
case PCI_DEVICE_ID_RP8J:
- str = "8J";
max_num_aiops = 1;
rocketModel[i].model = MODEL_RP8J;
strcpy(rocketModel[i].modelString, "RocketPort 8 port w/RJ11 connectors");
rocketModel[i].numPorts = 8;
break;
case PCI_DEVICE_ID_RP4J:
- str = "4J";
max_num_aiops = 1;
ports_per_aiop = 4;
rocketModel[i].model = MODEL_RP4J;
@@ -1851,56 +1836,48 @@
rocketModel[i].numPorts = 4;
break;
case PCI_DEVICE_ID_RP8SNI:
- str = "8 (DB78 Custom)";
max_num_aiops = 1;
rocketModel[i].model = MODEL_RP8SNI;
strcpy(rocketModel[i].modelString, "RocketPort 8 port w/ custom DB78");
rocketModel[i].numPorts = 8;
break;
case PCI_DEVICE_ID_RP16SNI:
- str = "16 (DB78 Custom)";
max_num_aiops = 2;
rocketModel[i].model = MODEL_RP16SNI;
strcpy(rocketModel[i].modelString, "RocketPort 16 port w/ custom DB78");
rocketModel[i].numPorts = 16;
break;
case PCI_DEVICE_ID_RP16INTF:
- str = "16";
max_num_aiops = 2;
rocketModel[i].model = MODEL_RP16INTF;
strcpy(rocketModel[i].modelString, "RocketPort 16 port w/external I/F");
rocketModel[i].numPorts = 16;
break;
case PCI_DEVICE_ID_URP16INTF:
- str = "16";
max_num_aiops = 2;
rocketModel[i].model = MODEL_UPCI_RP16INTF;
strcpy(rocketModel[i].modelString, "RocketPort UPCI 16 port w/external I/F");
rocketModel[i].numPorts = 16;
break;
case PCI_DEVICE_ID_CRP16INTF:
- str = "16";
max_num_aiops = 2;
rocketModel[i].model = MODEL_CPCI_RP16INTF;
strcpy(rocketModel[i].modelString, "RocketPort Compact PCI 16 port w/external I/F");
rocketModel[i].numPorts = 16;
break;
case PCI_DEVICE_ID_RP32INTF:
- str = "32";
max_num_aiops = 4;
rocketModel[i].model = MODEL_RP32INTF;
strcpy(rocketModel[i].modelString, "RocketPort 32 port w/external I/F");
rocketModel[i].numPorts = 32;
break;
case PCI_DEVICE_ID_URP32INTF:
- str = "32";
max_num_aiops = 4;
rocketModel[i].model = MODEL_UPCI_RP32INTF;
strcpy(rocketModel[i].modelString, "RocketPort UPCI 32 port w/external I/F");
rocketModel[i].numPorts = 32;
break;
case PCI_DEVICE_ID_RPP4:
- str = "Plus Quadcable";
max_num_aiops = 1;
ports_per_aiop = 4;
altChanRingIndicator++;
@@ -1910,7 +1887,6 @@
rocketModel[i].numPorts = 4;
break;
case PCI_DEVICE_ID_RPP8:
- str = "Plus Octacable";
max_num_aiops = 2;
ports_per_aiop = 4;
altChanRingIndicator++;
@@ -1920,7 +1896,6 @@
rocketModel[i].numPorts = 8;
break;
case PCI_DEVICE_ID_RP2_232:
- str = "Plus 2 (RS-232)";
max_num_aiops = 1;
ports_per_aiop = 2;
altChanRingIndicator++;
@@ -1930,7 +1905,6 @@
rocketModel[i].numPorts = 2;
break;
case PCI_DEVICE_ID_RP2_422:
- str = "Plus 2 (RS-422)";
max_num_aiops = 1;
ports_per_aiop = 2;
altChanRingIndicator++;
@@ -1943,7 +1917,6 @@
max_num_aiops = 1;
ports_per_aiop = 6;
- str = "6-port";
/* If revision is 1, the rocketmodem flash must be loaded.
* If it is 2 it is a "socketed" version. */
@@ -1961,7 +1934,6 @@
case PCI_DEVICE_ID_RP4M:
max_num_aiops = 1;
ports_per_aiop = 4;
- str = "4-port";
if (dev->revision == 1) {
rcktpt_type[i] = ROCKET_TYPE_MODEMII;
rocketModel[i].loadrm2 = 1;
@@ -1974,7 +1946,6 @@
rocketModel[i].numPorts = 4;
break;
default:
- str = "(unknown/unsupported)";
max_num_aiops = 0;
break;
}
@@ -2000,14 +1971,12 @@
if (!
(sInW(ConfigIO + _PCI_9030_GPIO_CTRL) &
PCI_GPIO_CTRL_8PORT)) {
- str = "Quadcable";
ports_per_aiop = 4;
rocketModel[i].numPorts = 4;
}
}
break;
case PCI_DEVICE_ID_UPCI_RM3_8PORT:
- str = "8 ports";
max_num_aiops = 1;
rocketModel[i].model = MODEL_UPCI_RM3_8PORT;
strcpy(rocketModel[i].modelString, "RocketModem III 8 port");
@@ -2018,7 +1987,6 @@
rcktpt_type[i] = ROCKET_TYPE_MODEMIII;
break;
case PCI_DEVICE_ID_UPCI_RM3_4PORT:
- str = "4 ports";
max_num_aiops = 1;
rocketModel[i].model = MODEL_UPCI_RM3_4PORT;
strcpy(rocketModel[i].modelString, "RocketModem III 4 port");
@@ -2032,21 +2000,6 @@
break;
}
- switch (rcktpt_type[i]) {
- case ROCKET_TYPE_MODEM:
- board_type = "RocketModem";
- break;
- case ROCKET_TYPE_MODEMII:
- board_type = "RocketModem II";
- break;
- case ROCKET_TYPE_MODEMIII:
- board_type = "RocketModem III";
- break;
- default:
- board_type = "RocketPort";
- break;
- }
-
if (fast_clock) {
sClockPrescale = 0x12; /* mod 2 (divide by 3) */
rp_baud_base[i] = 921600;
diff --git a/drivers/tty/serial/21285.c b/drivers/tty/serial/21285.c
index d89aa38..1b37626 100644
--- a/drivers/tty/serial/21285.c
+++ b/drivers/tty/serial/21285.c
@@ -1,6 +1,4 @@
/*
- * linux/drivers/serial/21285.c
- *
* Driver for the serial port on the 21285 StrongArm-110 core logic chip.
*
* Based on drivers/char/serial.c
diff --git a/drivers/tty/serial/68328serial.c b/drivers/tty/serial/68328serial.c
index d5bfd41..e0a7754 100644
--- a/drivers/tty/serial/68328serial.c
+++ b/drivers/tty/serial/68328serial.c
@@ -281,7 +281,7 @@
#ifdef CONFIG_MAGIC_SYSRQ
} else if (ch == 0x10) { /* ^P */
show_state();
- show_free_areas();
+ show_free_areas(0);
show_buffers();
/* show_net_buffers(); */
return;
diff --git a/drivers/tty/serial/8250.c b/drivers/tty/serial/8250.c
index 6611535..b40f7b9 100644
--- a/drivers/tty/serial/8250.c
+++ b/drivers/tty/serial/8250.c
@@ -1,6 +1,4 @@
/*
- * linux/drivers/char/8250.c
- *
* Driver for 8250/16550-type serial ports
*
* Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
@@ -273,7 +271,7 @@
.fifo_size = 32,
.tx_loadsz = 32,
.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
- .flags = UART_CAP_FIFO | UART_CAP_UUE,
+ .flags = UART_CAP_FIFO | UART_CAP_UUE | UART_CAP_RTOIE,
},
[PORT_RM9000] = {
.name = "RM9000",
@@ -303,6 +301,14 @@
.fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10,
.flags = UART_CAP_FIFO | UART_CAP_AFE,
},
+ [PORT_TEGRA] = {
+ .name = "Tegra",
+ .fifo_size = 32,
+ .tx_loadsz = 8,
+ .fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_01 |
+ UART_FCR_T_TRIG_01,
+ .flags = UART_CAP_FIFO | UART_CAP_RTOIE,
+ },
};
#if defined(CONFIG_MIPS_ALCHEMY)
@@ -1427,6 +1433,27 @@
serial_out(up, UART_IER, up->ier);
}
+/*
+ * Clear the Tegra rx fifo after a break
+ *
+ * FIXME: This needs to become a port specific callback once we have a
+ * framework for this
+ */
+static void clear_rx_fifo(struct uart_8250_port *up)
+{
+ unsigned int status, tmout = 10000;
+ do {
+ status = serial_in(up, UART_LSR);
+ if (status & (UART_LSR_FIFOE | UART_LSR_BRK_ERROR_BITS))
+ status = serial_in(up, UART_RX);
+ else
+ break;
+ if (--tmout == 0)
+ break;
+ udelay(1);
+ } while (1);
+}
+
static void
receive_chars(struct uart_8250_port *up, unsigned int *status)
{
@@ -1462,6 +1489,13 @@
lsr &= ~(UART_LSR_FE | UART_LSR_PE);
up->port.icount.brk++;
/*
+ * If tegra port then clear the rx fifo to
+ * accept another break/character.
+ */
+ if (up->port.type == PORT_TEGRA)
+ clear_rx_fifo(up);
+
+ /*
* We do the SysRQ and SAK checking
* here because otherwise the break
* may get masked by ignore_status_mask
@@ -2405,7 +2439,9 @@
UART_ENABLE_MS(&up->port, termios->c_cflag))
up->ier |= UART_IER_MSI;
if (up->capabilities & UART_CAP_UUE)
- up->ier |= UART_IER_UUE | UART_IER_RTOIE;
+ up->ier |= UART_IER_UUE;
+ if (up->capabilities & UART_CAP_RTOIE)
+ up->ier |= UART_IER_RTOIE;
serial_out(up, UART_IER, up->ier);
diff --git a/drivers/tty/serial/8250.h b/drivers/tty/serial/8250.h
index 6e19ea3..6edf4a6 100644
--- a/drivers/tty/serial/8250.h
+++ b/drivers/tty/serial/8250.h
@@ -1,6 +1,4 @@
/*
- * linux/drivers/char/8250.h
- *
* Driver for 8250/16550-type serial ports
*
* Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
@@ -44,6 +42,7 @@
#define UART_CAP_SLEEP (1 << 10) /* UART has IER sleep */
#define UART_CAP_AFE (1 << 11) /* MCR-based hw flow control */
#define UART_CAP_UUE (1 << 12) /* UART needs IER bit 6 set (Xscale) */
+#define UART_CAP_RTOIE (1 << 13) /* UART needs IER bit 4 set (Xscale, Tegra) */
#define UART_BUG_QUOT (1 << 0) /* UART has buggy quot LSB */
#define UART_BUG_TXEN (1 << 1) /* UART has buggy TX IIR status */
diff --git a/drivers/tty/serial/8250_accent.c b/drivers/tty/serial/8250_accent.c
index 9c10262..34b51c6 100644
--- a/drivers/tty/serial/8250_accent.c
+++ b/drivers/tty/serial/8250_accent.c
@@ -1,6 +1,4 @@
/*
- * linux/drivers/serial/8250_accent.c
- *
* Copyright (C) 2005 Russell King.
* Data taken from include/asm-i386/serial.h
*
diff --git a/drivers/tty/serial/8250_boca.c b/drivers/tty/serial/8250_boca.c
index 3bfe0f7..d125dc1 100644
--- a/drivers/tty/serial/8250_boca.c
+++ b/drivers/tty/serial/8250_boca.c
@@ -1,6 +1,4 @@
/*
- * linux/drivers/serial/8250_boca.c
- *
* Copyright (C) 2005 Russell King.
* Data taken from include/asm-i386/serial.h
*
diff --git a/drivers/tty/serial/8250_exar_st16c554.c b/drivers/tty/serial/8250_exar_st16c554.c
index 567143a..bf53aab 100644
--- a/drivers/tty/serial/8250_exar_st16c554.c
+++ b/drivers/tty/serial/8250_exar_st16c554.c
@@ -1,6 +1,4 @@
/*
- * linux/drivers/serial/8250_exar.c
- *
* Written by Paul B Schroeder < pschroeder "at" uplogix "dot" com >
* Based on 8250_boca.
*
diff --git a/drivers/tty/serial/8250_fourport.c b/drivers/tty/serial/8250_fourport.c
index 6375d68..be15826 100644
--- a/drivers/tty/serial/8250_fourport.c
+++ b/drivers/tty/serial/8250_fourport.c
@@ -1,6 +1,4 @@
/*
- * linux/drivers/serial/8250_fourport.c
- *
* Copyright (C) 2005 Russell King.
* Data taken from include/asm-i386/serial.h
*
diff --git a/drivers/tty/serial/8250_hub6.c b/drivers/tty/serial/8250_hub6.c
index 7609150..a5c778e 100644
--- a/drivers/tty/serial/8250_hub6.c
+++ b/drivers/tty/serial/8250_hub6.c
@@ -1,6 +1,4 @@
/*
- * linux/drivers/serial/8250_hub6.c
- *
* Copyright (C) 2005 Russell King.
* Data taken from include/asm-i386/serial.h
*
diff --git a/drivers/tty/serial/8250_mca.c b/drivers/tty/serial/8250_mca.c
index d10be94..d20abf0 100644
--- a/drivers/tty/serial/8250_mca.c
+++ b/drivers/tty/serial/8250_mca.c
@@ -1,6 +1,4 @@
/*
- * linux/drivers/serial/8250_mca.c
- *
* Copyright (C) 2005 Russell King.
* Data taken from include/asm-i386/serial.h
*
diff --git a/drivers/tty/serial/8250_pci.c b/drivers/tty/serial/8250_pci.c
index 738cec9..4b4968a 100644
--- a/drivers/tty/serial/8250_pci.c
+++ b/drivers/tty/serial/8250_pci.c
@@ -1,6 +1,4 @@
/*
- * linux/drivers/char/8250_pci.c
- *
* Probe module for 8250/16550-type PCI serial ports.
*
* Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
@@ -973,6 +971,14 @@
return ret;
}
+static int
+pci_omegapci_setup(struct serial_private *priv,
+ struct pciserial_board *board,
+ struct uart_port *port, int idx)
+{
+ return setup_port(priv, port, 2, idx * 8, 0);
+}
+
static int skip_tx_en_setup(struct serial_private *priv,
const struct pciserial_board *board,
struct uart_port *port, int idx)
@@ -1012,6 +1018,8 @@
#define PCI_DEVICE_ID_TITAN_200EI 0xA016
#define PCI_DEVICE_ID_TITAN_200EISI 0xA017
#define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
+#define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
+#define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
/* Unknown vendors/cards - this should not be in linux/pci_ids.h */
#define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
@@ -1412,7 +1420,7 @@
.setup = pci_default_setup,
},
/*
- * For Oxford Semiconductor and Mainpine
+ * For Oxford Semiconductor Tornado based devices
*/
{
.vendor = PCI_VENDOR_ID_OXSEMI,
@@ -1430,6 +1438,24 @@
.init = pci_oxsemi_tornado_init,
.setup = pci_default_setup,
},
+ {
+ .vendor = PCI_VENDOR_ID_DIGI,
+ .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
+ .subvendor = PCI_SUBVENDOR_ID_IBM,
+ .subdevice = PCI_ANY_ID,
+ .init = pci_oxsemi_tornado_init,
+ .setup = pci_default_setup,
+ },
+ /*
+ * Cronyx Omega PCI (PLX-chip based)
+ */
+ {
+ .vendor = PCI_VENDOR_ID_PLX,
+ .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
+ .subvendor = PCI_ANY_ID,
+ .subdevice = PCI_ANY_ID,
+ .setup = pci_omegapci_setup,
+ },
/*
* Default "match everything" terminator entry
*/
@@ -1617,6 +1643,7 @@
pbn_ADDIDATA_PCIe_4_3906250,
pbn_ADDIDATA_PCIe_8_3906250,
pbn_ce4100_1_115200,
+ pbn_omegapci,
};
/*
@@ -2312,6 +2339,12 @@
.base_baud = 921600,
.reg_shift = 2,
},
+ [pbn_omegapci] = {
+ .flags = FL_BASE0,
+ .num_ports = 8,
+ .base_baud = 115200,
+ .uart_offset = 0x200,
+ },
};
static const struct pci_device_id softmodem_blacklist[] = {
@@ -3075,6 +3108,14 @@
{ PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
pbn_oxsemi_8_4000000 },
+
+ /*
+ * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
+ */
+ { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
+ PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
+ pbn_oxsemi_2_4000000 },
+
/*
* SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
* from skokodyn@yahoo.com
@@ -3801,6 +3842,12 @@
PCI_ANY_ID, PCI_ANY_ID, 0, 0,
pbn_ce4100_1_115200 },
+ /*
+ * Cronyx Omega PCI
+ */
+ { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
+ PCI_ANY_ID, PCI_ANY_ID, 0, 0,
+ pbn_omegapci },
/*
* These entries match devices with class COMMUNICATION_SERIAL,
diff --git a/drivers/tty/serial/8250_pnp.c b/drivers/tty/serial/8250_pnp.c
index 4822cb5..fc301f6 100644
--- a/drivers/tty/serial/8250_pnp.c
+++ b/drivers/tty/serial/8250_pnp.c
@@ -1,6 +1,4 @@
/*
- * linux/drivers/char/8250_pnp.c
- *
* Probe module for 8250/16550-type ISAPNP serial ports.
*
* Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig
index b1f0f83..636144c 100644
--- a/drivers/tty/serial/Kconfig
+++ b/drivers/tty/serial/Kconfig
@@ -537,7 +537,7 @@
config SERIAL_S5PV210
tristate "Samsung S5PV210 Serial port support"
- depends on SERIAL_SAMSUNG && (CPU_S5PV210 || CPU_S5P6442 || CPU_EXYNOS4210)
+ depends on SERIAL_SAMSUNG && (CPU_S5PV210 || CPU_EXYNOS4210)
select SERIAL_SAMSUNG_UARTS_4 if (CPU_S5PV210 || CPU_EXYNOS4210)
default y
help
@@ -1585,7 +1585,7 @@
Support for the IFX6x60 modem devices on Intel MID platforms.
config SERIAL_PCH_UART
- tristate "Intel EG20T PCH UART/OKI SEMICONDUCTOR ML7213 IOH"
+ tristate "Intel EG20T PCH / OKI SEMICONDUCTOR IOH(ML7213/ML7223) UART"
depends on PCI
select SERIAL_CORE
help
@@ -1593,10 +1593,12 @@
which is an IOH(Input/Output Hub) for x86 embedded processor.
Enabling PCH_DMA, this PCH UART works as DMA mode.
- This driver also can be used for OKI SEMICONDUCTOR ML7213 IOH(Input/
- Output Hub) which is for IVI(In-Vehicle Infotainment) use.
- ML7213 is companion chip for Intel Atom E6xx series.
- ML7213 is completely compatible for Intel EG20T PCH.
+ This driver also can be used for OKI SEMICONDUCTOR IOH(Input/
+ Output Hub), ML7213 and ML7223.
+ ML7213 IOH is for IVI(In-Vehicle Infotainment) use and ML7223 IOH is
+ for MP(Media Phone) use.
+ ML7213/ML7223 is companion chip for Intel Atom E6xx series.
+ ML7213/ML7223 is completely compatible for Intel EG20T PCH.
config SERIAL_MSM_SMD
bool "Enable tty device interface for some SMD ports"
@@ -1620,4 +1622,17 @@
help
Enable a MXS AUART port to be the system console.
+config SERIAL_XILINX_PS_UART
+ tristate "Xilinx PS UART support"
+ select SERIAL_CORE
+ help
+ This driver supports the Xilinx PS UART port.
+
+config SERIAL_XILINX_PS_UART_CONSOLE
+ bool "Xilinx PS UART console support"
+ depends on SERIAL_XILINX_PS_UART=y
+ select SERIAL_CORE_CONSOLE
+ help
+ Enable a Xilinx PS UART port to be the system console.
+
endmenu
diff --git a/drivers/tty/serial/Makefile b/drivers/tty/serial/Makefile
index 3527604..cb2628f 100644
--- a/drivers/tty/serial/Makefile
+++ b/drivers/tty/serial/Makefile
@@ -95,3 +95,4 @@
obj-$(CONFIG_SERIAL_MSM_SMD) += msm_smd_tty.o
obj-$(CONFIG_SERIAL_MXS_AUART) += mxs-auart.o
obj-$(CONFIG_SERIAL_LANTIQ) += lantiq.o
+obj-$(CONFIG_SERIAL_XILINX_PS_UART) += xilinx_uartps.o
diff --git a/drivers/tty/serial/altera_uart.c b/drivers/tty/serial/altera_uart.c
index 6d5b036..50bc5a5 100644
--- a/drivers/tty/serial/altera_uart.c
+++ b/drivers/tty/serial/altera_uart.c
@@ -540,11 +540,14 @@
int i = pdev->id;
int ret;
- /* -1 emphasizes that the platform must have one port, no .N suffix */
- if (i == -1)
- i = 0;
+ /* if id is -1 scan for a free id and use that one */
+ if (i == -1) {
+ for (i = 0; i < CONFIG_SERIAL_ALTERA_UART_MAXPORTS; i++)
+ if (altera_uart_ports[i].port.mapbase == 0)
+ break;
+ }
- if (i >= CONFIG_SERIAL_ALTERA_UART_MAXPORTS)
+ if (i < 0 || i >= CONFIG_SERIAL_ALTERA_UART_MAXPORTS)
return -EINVAL;
port = &altera_uart_ports[i].port;
@@ -587,6 +590,8 @@
port->ops = &altera_uart_ops;
port->flags = UPF_BOOT_AUTOCONF;
+ dev_set_drvdata(&pdev->dev, port);
+
uart_add_one_port(&altera_uart_driver, port);
return 0;
@@ -594,14 +599,13 @@
static int __devexit altera_uart_remove(struct platform_device *pdev)
{
- struct uart_port *port;
- int i = pdev->id;
+ struct uart_port *port = dev_get_drvdata(&pdev->dev);
- if (i == -1)
- i = 0;
-
- port = &altera_uart_ports[i].port;
- uart_remove_one_port(&altera_uart_driver, port);
+ if (port) {
+ uart_remove_one_port(&altera_uart_driver, port);
+ dev_set_drvdata(&pdev->dev, NULL);
+ port->mapbase = 0;
+ }
return 0;
}
diff --git a/drivers/tty/serial/amba-pl010.c b/drivers/tty/serial/amba-pl010.c
index d742dd2..c0d10c4 100644
--- a/drivers/tty/serial/amba-pl010.c
+++ b/drivers/tty/serial/amba-pl010.c
@@ -1,6 +1,4 @@
/*
- * linux/drivers/char/amba.c
- *
* Driver for AMBA serial ports
*
* Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c
index 6deee4e..8dc0541 100644
--- a/drivers/tty/serial/amba-pl011.c
+++ b/drivers/tty/serial/amba-pl011.c
@@ -1,6 +1,4 @@
/*
- * linux/drivers/char/amba.c
- *
* Driver for AMBA serial ports
*
* Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c
index f119d17..652bdac 100644
--- a/drivers/tty/serial/atmel_serial.c
+++ b/drivers/tty/serial/atmel_serial.c
@@ -1,6 +1,4 @@
/*
- * linux/drivers/char/atmel_serial.c
- *
* Driver for Atmel AT91 / AT32 Serial ports
* Copyright (C) 2003 Rick Bronson
*
diff --git a/drivers/tty/serial/clps711x.c b/drivers/tty/serial/clps711x.c
index b6acd19..e6c3dbd 100644
--- a/drivers/tty/serial/clps711x.c
+++ b/drivers/tty/serial/clps711x.c
@@ -1,6 +1,4 @@
/*
- * linux/drivers/char/clps711x.c
- *
* Driver for CLPS711x serial ports
*
* Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
diff --git a/drivers/tty/serial/cpm_uart/cpm_uart.h b/drivers/tty/serial/cpm_uart/cpm_uart.h
index b754dcf..cf34d26 100644
--- a/drivers/tty/serial/cpm_uart/cpm_uart.h
+++ b/drivers/tty/serial/cpm_uart/cpm_uart.h
@@ -1,6 +1,4 @@
/*
- * linux/drivers/serial/cpm_uart.h
- *
* Driver for CPM (SCC/SMC) serial ports
*
* Copyright (C) 2004 Freescale Semiconductor, Inc.
diff --git a/drivers/tty/serial/cpm_uart/cpm_uart_core.c b/drivers/tty/serial/cpm_uart/cpm_uart_core.c
index a9a6a5f..9488da7 100644
--- a/drivers/tty/serial/cpm_uart/cpm_uart_core.c
+++ b/drivers/tty/serial/cpm_uart/cpm_uart_core.c
@@ -1,6 +1,4 @@
/*
- * linux/drivers/serial/cpm_uart.c
- *
* Driver for CPM (SCC/SMC) serial ports; core driver
*
* Based on arch/ppc/cpm2_io/uart.c by Dan Malek
diff --git a/drivers/tty/serial/cpm_uart/cpm_uart_cpm1.c b/drivers/tty/serial/cpm_uart/cpm_uart_cpm1.c
index 3fc1d66..18f7957 100644
--- a/drivers/tty/serial/cpm_uart/cpm_uart_cpm1.c
+++ b/drivers/tty/serial/cpm_uart/cpm_uart_cpm1.c
@@ -1,6 +1,4 @@
/*
- * linux/drivers/serial/cpm_uart.c
- *
* Driver for CPM (SCC/SMC) serial ports; CPM1 definitions
*
* Maintainer: Kumar Gala (galak@kernel.crashing.org) (CPM2)
diff --git a/drivers/tty/serial/cpm_uart/cpm_uart_cpm1.h b/drivers/tty/serial/cpm_uart/cpm_uart_cpm1.h
index 10eecd6..60c7e94 100644
--- a/drivers/tty/serial/cpm_uart/cpm_uart_cpm1.h
+++ b/drivers/tty/serial/cpm_uart/cpm_uart_cpm1.h
@@ -1,6 +1,4 @@
/*
- * linux/drivers/serial/cpm_uart/cpm_uart_cpm1.h
- *
* Driver for CPM (SCC/SMC) serial ports
*
* definitions for cpm1
diff --git a/drivers/tty/serial/cpm_uart/cpm_uart_cpm2.c b/drivers/tty/serial/cpm_uart/cpm_uart_cpm2.c
index 814ac00..a4927e6 100644
--- a/drivers/tty/serial/cpm_uart/cpm_uart_cpm2.c
+++ b/drivers/tty/serial/cpm_uart/cpm_uart_cpm2.c
@@ -1,6 +1,4 @@
/*
- * linux/drivers/serial/cpm_uart_cpm2.c
- *
* Driver for CPM (SCC/SMC) serial ports; CPM2 definitions
*
* Maintainer: Kumar Gala (galak@kernel.crashing.org) (CPM2)
diff --git a/drivers/tty/serial/cpm_uart/cpm_uart_cpm2.h b/drivers/tty/serial/cpm_uart/cpm_uart_cpm2.h
index 7194c63..51e651a 100644
--- a/drivers/tty/serial/cpm_uart/cpm_uart_cpm2.h
+++ b/drivers/tty/serial/cpm_uart/cpm_uart_cpm2.h
@@ -1,6 +1,4 @@
/*
- * linux/drivers/serial/cpm_uart/cpm_uart_cpm2.h
- *
* Driver for CPM (SCC/SMC) serial ports
*
* definitions for cpm2
diff --git a/drivers/tty/serial/ifx6x60.c b/drivers/tty/serial/ifx6x60.c
index 8ee5a41..5315525 100644
--- a/drivers/tty/serial/ifx6x60.c
+++ b/drivers/tty/serial/ifx6x60.c
@@ -41,7 +41,6 @@
#include <linux/tty.h>
#include <linux/device.h>
#include <linux/spi/spi.h>
-#include <linux/tty.h>
#include <linux/kfifo.h>
#include <linux/tty_flip.h>
#include <linux/timer.h>
@@ -56,7 +55,6 @@
#include <linux/sched.h>
#include <linux/time.h>
#include <linux/wait.h>
-#include <linux/tty.h>
#include <linux/pm.h>
#include <linux/pm_runtime.h>
#include <linux/spi/ifx_modem.h>
diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c
index 62df72d..a544731 100644
--- a/drivers/tty/serial/imx.c
+++ b/drivers/tty/serial/imx.c
@@ -1,6 +1,4 @@
/*
- * linux/drivers/serial/imx.c
- *
* Driver for Motorola IMX serial ports
*
* Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
diff --git a/drivers/tty/serial/msm_serial.c b/drivers/tty/serial/msm_serial.c
index bfee9b4..e6ba838 100644
--- a/drivers/tty/serial/msm_serial.c
+++ b/drivers/tty/serial/msm_serial.c
@@ -1,5 +1,5 @@
/*
- * drivers/serial/msm_serial.c - driver for msm7k serial device and console
+ * Driver for msm7k serial device and console
*
* Copyright (C) 2007 Google, Inc.
* Author: Robert Love <rlove@google.com>
diff --git a/drivers/tty/serial/msm_serial.h b/drivers/tty/serial/msm_serial.h
index 9b8dc5d..e4acef5 100644
--- a/drivers/tty/serial/msm_serial.h
+++ b/drivers/tty/serial/msm_serial.h
@@ -1,6 +1,4 @@
/*
- * drivers/serial/msm_serial.h
- *
* Copyright (C) 2007 Google, Inc.
* Author: Robert Love <rlove@google.com>
* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
diff --git a/drivers/tty/serial/msm_smd_tty.c b/drivers/tty/serial/msm_smd_tty.c
index beeff1e..4f41dcd 100644
--- a/drivers/tty/serial/msm_smd_tty.c
+++ b/drivers/tty/serial/msm_smd_tty.c
@@ -1,5 +1,4 @@
-/* drivers/tty/serial/msm_smd_tty.c
- *
+/*
* Copyright (C) 2007 Google, Inc.
* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
* Author: Brian Swetland <swetland@google.com>
diff --git a/drivers/tty/serial/netx-serial.c b/drivers/tty/serial/netx-serial.c
index 7735c9f..d40da78 100644
--- a/drivers/tty/serial/netx-serial.c
+++ b/drivers/tty/serial/netx-serial.c
@@ -1,6 +1,4 @@
/*
- * drivers/serial/netx-serial.c
- *
* Copyright (c) 2005 Sascha Hauer <s.hauer@pengutronix.de>, Pengutronix
*
* This program is free software; you can redistribute it and/or modify
diff --git a/drivers/tty/serial/pch_uart.c b/drivers/tty/serial/pch_uart.c
index 26403b8..f2cb750 100644
--- a/drivers/tty/serial/pch_uart.c
+++ b/drivers/tty/serial/pch_uart.c
@@ -15,6 +15,7 @@
*Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
*/
#include <linux/serial_reg.h>
+#include <linux/slab.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/serial_core.h>
@@ -253,6 +254,8 @@
pch_ml7213_uart0,
pch_ml7213_uart1,
pch_ml7213_uart2,
+ pch_ml7223_uart0,
+ pch_ml7223_uart1,
};
static struct pch_uart_driver_data drv_dat[] = {
@@ -263,6 +266,8 @@
[pch_ml7213_uart0] = {PCH_UART_8LINE, 0},
[pch_ml7213_uart1] = {PCH_UART_2LINE, 1},
[pch_ml7213_uart2] = {PCH_UART_2LINE, 2},
+ [pch_ml7223_uart0] = {PCH_UART_8LINE, 0},
+ [pch_ml7223_uart1] = {PCH_UART_2LINE, 1},
};
static unsigned int default_baud = 9600;
@@ -1534,6 +1539,10 @@
.driver_data = pch_ml7213_uart1},
{PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x8029),
.driver_data = pch_ml7213_uart2},
+ {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800C),
+ .driver_data = pch_ml7223_uart0},
+ {PCI_DEVICE(PCI_VENDOR_ID_ROHM, 0x800D),
+ .driver_data = pch_ml7223_uart1},
{0,},
};
diff --git a/drivers/tty/serial/pmac_zilog.c b/drivers/tty/serial/pmac_zilog.c
index e1c8d4f..5acd24a 100644
--- a/drivers/tty/serial/pmac_zilog.c
+++ b/drivers/tty/serial/pmac_zilog.c
@@ -1,6 +1,4 @@
/*
- * linux/drivers/serial/pmac_zilog.c
- *
* Driver for PowerMac Z85c30 based ESCC cell found in the
* "macio" ASICs of various PowerMac models
*
diff --git a/drivers/tty/serial/pxa.c b/drivers/tty/serial/pxa.c
index 1102a39..4302e6e 100644
--- a/drivers/tty/serial/pxa.c
+++ b/drivers/tty/serial/pxa.c
@@ -1,6 +1,4 @@
/*
- * linux/drivers/serial/pxa.c
- *
* Based on drivers/serial/8250.c by Russell King.
*
* Author: Nicolas Pitre
diff --git a/drivers/tty/serial/s3c2400.c b/drivers/tty/serial/s3c2400.c
index fed1a9a..d13051b 100644
--- a/drivers/tty/serial/s3c2400.c
+++ b/drivers/tty/serial/s3c2400.c
@@ -1,5 +1,4 @@
-/* linux/drivers/serial/s3c240.c
- *
+/*
* Driver for Samsung SoC onboard UARTs.
*
* Ben Dooks, Copyright (c) 2003-2005 Simtec Electronics
diff --git a/drivers/tty/serial/s3c2410.c b/drivers/tty/serial/s3c2410.c
index 73f089d..bffe6ff 100644
--- a/drivers/tty/serial/s3c2410.c
+++ b/drivers/tty/serial/s3c2410.c
@@ -1,5 +1,4 @@
-/* linux/drivers/serial/s3c2410.c
- *
+/*
* Driver for Samsung S3C2410 SoC onboard UARTs.
*
* Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
diff --git a/drivers/tty/serial/s3c2412.c b/drivers/tty/serial/s3c2412.c
index 1700b1a..7e2b950 100644
--- a/drivers/tty/serial/s3c2412.c
+++ b/drivers/tty/serial/s3c2412.c
@@ -1,5 +1,4 @@
-/* linux/drivers/serial/s3c2412.c
- *
+/*
* Driver for Samsung S3C2412 and S3C2413 SoC onboard UARTs.
*
* Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
diff --git a/drivers/tty/serial/s3c2440.c b/drivers/tty/serial/s3c2440.c
index 094cc39..9e10d41 100644
--- a/drivers/tty/serial/s3c2440.c
+++ b/drivers/tty/serial/s3c2440.c
@@ -1,5 +1,4 @@
-/* linux/drivers/serial/s3c2440.c
- *
+/*
* Driver for Samsung S3C2440 and S3C2442 SoC onboard UARTs.
*
* Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
diff --git a/drivers/tty/serial/s3c24a0.c b/drivers/tty/serial/s3c24a0.c
index fad6083..914eff2 100644
--- a/drivers/tty/serial/s3c24a0.c
+++ b/drivers/tty/serial/s3c24a0.c
@@ -1,5 +1,4 @@
-/* linux/drivers/serial/s3c24a0.c
- *
+/*
* Driver for Samsung S3C24A0 SoC onboard UARTs.
*
* Based on drivers/serial/s3c2410.c
diff --git a/drivers/tty/serial/s3c6400.c b/drivers/tty/serial/s3c6400.c
index 4be92ab..ded26c4 100644
--- a/drivers/tty/serial/s3c6400.c
+++ b/drivers/tty/serial/s3c6400.c
@@ -1,5 +1,4 @@
-/* linux/drivers/serial/s3c6400.c
- *
+/*
* Driver for Samsung S3C6400 and S3C6410 SoC onboard UARTs.
*
* Copyright 2008 Openmoko, Inc.
diff --git a/drivers/tty/serial/s5pv210.c b/drivers/tty/serial/s5pv210.c
index 6ebccd7..fb2619f 100644
--- a/drivers/tty/serial/s5pv210.c
+++ b/drivers/tty/serial/s5pv210.c
@@ -1,5 +1,4 @@
-/* linux/drivers/serial/s5pv210.c
- *
+/*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
diff --git a/drivers/tty/serial/sa1100.c b/drivers/tty/serial/sa1100.c
index 2199d81..ef7a21a 100644
--- a/drivers/tty/serial/sa1100.c
+++ b/drivers/tty/serial/sa1100.c
@@ -1,6 +1,4 @@
/*
- * linux/drivers/char/sa1100.c
- *
* Driver for SA11x0 serial ports
*
* Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
diff --git a/drivers/tty/serial/samsung.c b/drivers/tty/serial/samsung.c
index 9e2fa8d..f66f648 100644
--- a/drivers/tty/serial/samsung.c
+++ b/drivers/tty/serial/samsung.c
@@ -1,5 +1,4 @@
-/* linux/drivers/serial/samsuing.c
- *
+/*
* Driver core for Samsung SoC onboard UARTs.
*
* Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
diff --git a/drivers/tty/serial/samsung.h b/drivers/tty/serial/samsung.h
index 0ac06a0..5b098cd 100644
--- a/drivers/tty/serial/samsung.h
+++ b/drivers/tty/serial/samsung.h
@@ -1,5 +1,4 @@
-/* linux/drivers/serial/samsung.h
- *
+/*
* Driver for Samsung SoC onboard UARTs.
*
* Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics
diff --git a/drivers/tty/serial/sb1250-duart.c b/drivers/tty/serial/sb1250-duart.c
index 602d984..ea2340b 100644
--- a/drivers/tty/serial/sb1250-duart.c
+++ b/drivers/tty/serial/sb1250-duart.c
@@ -1,6 +1,4 @@
/*
- * drivers/serial/sb1250-duart.c
- *
* Support for the asynchronous serial interface (DUART) included
* in the BCM1250 and derived System-On-a-Chip (SOC) devices.
*
diff --git a/drivers/tty/serial/serial_core.c b/drivers/tty/serial/serial_core.c
index 733fe8e..db7912c 100644
--- a/drivers/tty/serial/serial_core.c
+++ b/drivers/tty/serial/serial_core.c
@@ -1,6 +1,4 @@
/*
- * linux/drivers/char/core.c
- *
* Driver core for serial ports
*
* Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
@@ -172,12 +170,16 @@
retval = uport->ops->startup(uport);
if (retval == 0) {
- if (init_hw) {
- /*
- * Initialise the hardware port settings.
- */
- uart_change_speed(tty, state, NULL);
+ if (uart_console(uport) && uport->cons->cflag) {
+ tty->termios->c_cflag = uport->cons->cflag;
+ uport->cons->cflag = 0;
+ }
+ /*
+ * Initialise the hardware port settings.
+ */
+ uart_change_speed(tty, state, NULL);
+ if (init_hw) {
/*
* Setup the RTS and DTR signals once the
* port is open and ready to respond.
@@ -1240,17 +1242,6 @@
}
spin_unlock_irqrestore(&state->uart_port->lock, flags);
}
-#if 0
- /*
- * No need to wake up processes in open wait, since they
- * sample the CLOCAL flag once, and don't recheck it.
- * XXX It's not clear whether the current behavior is correct
- * or not. Hence, this may change.....
- */
- if (!(old_termios->c_cflag & CLOCAL) &&
- (tty->termios->c_cflag & CLOCAL))
- wake_up_interruptible(&state->uart_port.open_wait);
-#endif
}
/*
@@ -1423,7 +1414,6 @@
if (time_after(jiffies, expire))
break;
}
- set_current_state(TASK_RUNNING); /* might not be needed */
}
static void uart_wait_until_sent(struct tty_struct *tty, int timeout)
@@ -1466,45 +1456,6 @@
mutex_unlock(&port->mutex);
}
-/**
- * uart_update_termios - update the terminal hw settings
- * @tty: tty associated with UART
- * @state: UART to update
- *
- * Copy across the serial console cflag setting into the termios settings
- * for the initial open of the port. This allows continuity between the
- * kernel settings, and the settings init adopts when it opens the port
- * for the first time.
- */
-static void uart_update_termios(struct tty_struct *tty,
- struct uart_state *state)
-{
- struct uart_port *port = state->uart_port;
-
- if (uart_console(port) && port->cons->cflag) {
- tty->termios->c_cflag = port->cons->cflag;
- port->cons->cflag = 0;
- }
-
- /*
- * If the device failed to grab its irq resources,
- * or some other error occurred, don't try to talk
- * to the port hardware.
- */
- if (!(tty->flags & (1 << TTY_IO_ERROR))) {
- /*
- * Make termios settings take effect.
- */
- uart_change_speed(tty, state, NULL);
-
- /*
- * And finally enable the RTS and DTR signals.
- */
- if (tty->termios->c_cflag & CBAUD)
- uart_set_mctrl(port, TIOCM_DTR | TIOCM_RTS);
- }
-}
-
static int uart_carrier_raised(struct tty_port *port)
{
struct uart_state *state = container_of(port, struct uart_state, port);
@@ -1524,16 +1475,8 @@
struct uart_state *state = container_of(port, struct uart_state, port);
struct uart_port *uport = state->uart_port;
- if (onoff) {
+ if (onoff)
uart_set_mctrl(uport, TIOCM_DTR | TIOCM_RTS);
-
- /*
- * If this is the first open to succeed,
- * adjust things to suit.
- */
- if (!test_and_set_bit(ASYNCB_NORMAL_ACTIVE, &port->flags))
- uart_update_termios(port->tty, state);
- }
else
uart_clear_mctrl(uport, TIOCM_DTR | TIOCM_RTS);
}
@@ -1586,15 +1529,6 @@
pr_debug("uart_open(%d) called\n", line);
/*
- * tty->driver->num won't change, so we won't fail here with
- * tty->driver_data set to something non-NULL (and therefore
- * we won't get caught by uart_close()).
- */
- retval = -ENODEV;
- if (line >= tty->driver->num)
- goto fail;
-
- /*
* We take the semaphore inside uart_get to guarantee that we won't
* be re-entered while allocating the state structure, or while we
* request any IRQs that the driver may need. This also has the nice
@@ -1972,13 +1906,9 @@
struct tty_port *port = &state->port;
struct device *tty_dev;
struct uart_match match = {uport, drv};
- struct tty_struct *tty;
mutex_lock(&port->mutex);
- /* Must be inside the mutex lock until we convert to tty_port */
- tty = port->tty;
-
tty_dev = device_find_child(uport->dev, &match, serial_match_port);
if (device_may_wakeup(tty_dev)) {
if (!enable_irq_wake(uport->irq))
diff --git a/drivers/tty/serial/serial_cs.c b/drivers/tty/serial/serial_cs.c
index 1ef4df9..eef736f 100644
--- a/drivers/tty/serial/serial_cs.c
+++ b/drivers/tty/serial/serial_cs.c
@@ -670,7 +670,7 @@
return -ENODEV;
}
-static struct pcmcia_device_id serial_ids[] = {
+static const struct pcmcia_device_id serial_ids[] = {
PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0057, 0x0021),
PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0089, 0x110a),
PCMCIA_PFC_DEVICE_MANF_CARD(1, 0x0104, 0x000a),
diff --git a/drivers/tty/serial/serial_ks8695.c b/drivers/tty/serial/serial_ks8695.c
index b196202..2430319 100644
--- a/drivers/tty/serial/serial_ks8695.c
+++ b/drivers/tty/serial/serial_ks8695.c
@@ -1,6 +1,4 @@
/*
- * drivers/serial/serial_ks8695.c
- *
* Driver for KS8695 serial ports
*
* Based on drivers/serial/serial_amba.c, by Kam Lee.
diff --git a/drivers/tty/serial/serial_txx9.c b/drivers/tty/serial/serial_txx9.c
index c50e9fb..8e3fc19 100644
--- a/drivers/tty/serial/serial_txx9.c
+++ b/drivers/tty/serial/serial_txx9.c
@@ -1,6 +1,4 @@
/*
- * drivers/serial/serial_txx9.c
- *
* Derived from many drivers using generic_serial interface,
* especially serial_tx3912.c by Steven J. Hill and r39xx_serial.c
* (was in Linux/VR tree) by Jim Pick.
diff --git a/drivers/tty/serial/sh-sci.c b/drivers/tty/serial/sh-sci.c
index 920a6f9..ebd8629 100644
--- a/drivers/tty/serial/sh-sci.c
+++ b/drivers/tty/serial/sh-sci.c
@@ -1,6 +1,4 @@
/*
- * drivers/serial/sh-sci.c
- *
* SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
*
* Copyright (C) 2002 - 2011 Paul Mundt
@@ -43,6 +41,7 @@
#include <linux/platform_device.h>
#include <linux/serial_sci.h>
#include <linux/notifier.h>
+#include <linux/pm_runtime.h>
#include <linux/cpufreq.h>
#include <linux/clk.h>
#include <linux/ctype.h>
@@ -562,6 +561,9 @@
{
struct sci_port *port = (struct sci_port *)data;
+ if (port->enable)
+ port->enable(&port->port);
+
if (sci_rxd_in(&port->port) == 0) {
port->break_flag = 1;
sci_schedule_break_timer(port);
@@ -571,6 +573,9 @@
sci_schedule_break_timer(port);
} else
port->break_flag = 0;
+
+ if (port->disable)
+ port->disable(&port->port);
}
static int sci_handle_errors(struct uart_port *port)
@@ -839,6 +844,8 @@
{
struct sci_port *sci_port = to_sci_port(port);
+ pm_runtime_get_sync(port->dev);
+
clk_enable(sci_port->iclk);
sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
clk_enable(sci_port->fclk);
@@ -850,6 +857,8 @@
clk_disable(sci_port->fclk);
clk_disable(sci_port->iclk);
+
+ pm_runtime_put_sync(port->dev);
}
static int sci_request_irq(struct sci_port *port)
@@ -1758,6 +1767,8 @@
sci_port->enable = sci_clk_enable;
sci_port->disable = sci_clk_disable;
port->dev = &dev->dev;
+
+ pm_runtime_enable(&dev->dev);
}
sci_port->break_timer.data = (unsigned long)sci_port;
@@ -1777,7 +1788,7 @@
*
* For the muxed case there's nothing more to do.
*/
- port->irq = p->irqs[SCIx_TXI_IRQ];
+ port->irq = p->irqs[SCIx_RXI_IRQ];
if (p->dma_dev)
dev_dbg(port->dev, "DMA device %p, tx %d, rx %d\n",
@@ -1938,6 +1949,7 @@
clk_put(port->iclk);
clk_put(port->fclk);
+ pm_runtime_disable(&dev->dev);
return 0;
}
diff --git a/drivers/tty/serial/sh-sci.h b/drivers/tty/serial/sh-sci.h
index 5fefed5..b04d937 100644
--- a/drivers/tty/serial/sh-sci.h
+++ b/drivers/tty/serial/sh-sci.h
@@ -270,12 +270,12 @@
#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
defined(CONFIG_CPU_SUBTYPE_SH7720) || \
defined(CONFIG_CPU_SUBTYPE_SH7721) || \
- defined(CONFIG_ARCH_SH73A0) || \
- defined(CONFIG_ARCH_SH7367) || \
- defined(CONFIG_ARCH_SH7377)
+ defined(CONFIG_ARCH_SH7367)
#define SCIF_FNS(name, scif_offset, scif_size) \
CPU_SCIF_FNS(name, scif_offset, scif_size)
-#elif defined(CONFIG_ARCH_SH7372)
+#elif defined(CONFIG_ARCH_SH7377) || \
+ defined(CONFIG_ARCH_SH7372) || \
+ defined(CONFIG_ARCH_SH73A0)
#define SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scifb_offset, sh4_scifb_size) \
CPU_SCIx_FNS(name, sh4_scifa_offset, sh4_scifa_size, sh4_scifb_offset, sh4_scifb_size)
#define SCIF_FNS(name, scif_offset, scif_size) \
@@ -313,9 +313,7 @@
#if defined(CONFIG_CPU_SUBTYPE_SH7705) || \
defined(CONFIG_CPU_SUBTYPE_SH7720) || \
defined(CONFIG_CPU_SUBTYPE_SH7721) || \
- defined(CONFIG_ARCH_SH73A0) || \
- defined(CONFIG_ARCH_SH7367) || \
- defined(CONFIG_ARCH_SH7377)
+ defined(CONFIG_ARCH_SH7367)
SCIF_FNS(SCSMR, 0x00, 16)
SCIF_FNS(SCBRR, 0x04, 8)
@@ -326,7 +324,9 @@
SCIF_FNS(SCxTDR, 0x20, 8)
SCIF_FNS(SCxRDR, 0x24, 8)
SCIF_FNS(SCLSR, 0x00, 0)
-#elif defined(CONFIG_ARCH_SH7372)
+#elif defined(CONFIG_ARCH_SH7377) || \
+ defined(CONFIG_ARCH_SH7372) || \
+ defined(CONFIG_ARCH_SH73A0)
SCIF_FNS(SCSMR, 0x00, 16)
SCIF_FNS(SCBRR, 0x04, 8)
SCIF_FNS(SCSCR, 0x08, 16)
diff --git a/drivers/tty/serial/vt8500_serial.c b/drivers/tty/serial/vt8500_serial.c
index 322bf56..37fc4e3 100644
--- a/drivers/tty/serial/vt8500_serial.c
+++ b/drivers/tty/serial/vt8500_serial.c
@@ -1,6 +1,4 @@
/*
- * drivers/serial/vt8500_serial.c
- *
* Copyright (C) 2010 Alexey Charkov <alchark@gmail.com>
*
* Based on msm_serial.c, which is:
diff --git a/drivers/tty/serial/xilinx_uartps.c b/drivers/tty/serial/xilinx_uartps.c
new file mode 100644
index 0000000..19cc1e8
--- /dev/null
+++ b/drivers/tty/serial/xilinx_uartps.c
@@ -0,0 +1,1113 @@
+/*
+ * Xilinx PS UART driver
+ *
+ * 2011 (c) Xilinx Inc.
+ *
+ * This program is free software; you can redistribute it
+ * and/or modify it under the terms of the GNU General Public
+ * License as published by the Free Software Foundation;
+ * either version 2 of the License, or (at your option) any
+ * later version.
+ *
+ */
+
+#include <linux/platform_device.h>
+#include <linux/serial_core.h>
+#include <linux/console.h>
+#include <linux/serial.h>
+#include <linux/irq.h>
+#include <linux/io.h>
+#include <linux/of.h>
+
+#define XUARTPS_TTY_NAME "ttyPS"
+#define XUARTPS_NAME "xuartps"
+#define XUARTPS_MAJOR 0 /* use dynamic node allocation */
+#define XUARTPS_MINOR 0 /* works best with devtmpfs */
+#define XUARTPS_NR_PORTS 2
+#define XUARTPS_FIFO_SIZE 16 /* FIFO size */
+#define XUARTPS_REGISTER_SPACE 0xFFF
+
+#define xuartps_readl(offset) ioread32(port->membase + offset)
+#define xuartps_writel(val, offset) iowrite32(val, port->membase + offset)
+
+/********************************Register Map********************************/
+/** UART
+ *
+ * Register offsets for the UART.
+ *
+ */
+#define XUARTPS_CR_OFFSET 0x00 /* Control Register [8:0] */
+#define XUARTPS_MR_OFFSET 0x04 /* Mode Register [10:0] */
+#define XUARTPS_IER_OFFSET 0x08 /* Interrupt Enable [10:0] */
+#define XUARTPS_IDR_OFFSET 0x0C /* Interrupt Disable [10:0] */
+#define XUARTPS_IMR_OFFSET 0x10 /* Interrupt Mask [10:0] */
+#define XUARTPS_ISR_OFFSET 0x14 /* Interrupt Status [10:0]*/
+#define XUARTPS_BAUDGEN_OFFSET 0x18 /* Baud Rate Generator [15:0] */
+#define XUARTPS_RXTOUT_OFFSET 0x1C /* RX Timeout [7:0] */
+#define XUARTPS_RXWM_OFFSET 0x20 /* RX FIFO Trigger Level [5:0] */
+#define XUARTPS_MODEMCR_OFFSET 0x24 /* Modem Control [5:0] */
+#define XUARTPS_MODEMSR_OFFSET 0x28 /* Modem Status [8:0] */
+#define XUARTPS_SR_OFFSET 0x2C /* Channel Status [11:0] */
+#define XUARTPS_FIFO_OFFSET 0x30 /* FIFO [15:0] or [7:0] */
+#define XUARTPS_BAUDDIV_OFFSET 0x34 /* Baud Rate Divider [7:0] */
+#define XUARTPS_FLOWDEL_OFFSET 0x38 /* Flow Delay [15:0] */
+#define XUARTPS_IRRX_PWIDTH_OFFSET 0x3C /* IR Minimum Received Pulse
+ Width [15:0] */
+#define XUARTPS_IRTX_PWIDTH_OFFSET 0x40 /* IR Transmitted pulse
+ Width [7:0] */
+#define XUARTPS_TXWM_OFFSET 0x44 /* TX FIFO Trigger Level [5:0] */
+
+/** Control Register
+ *
+ * The Control register (CR) controls the major functions of the device.
+ *
+ * Control Register Bit Definitions
+ */
+#define XUARTPS_CR_STOPBRK 0x00000100 /* Stop TX break */
+#define XUARTPS_CR_STARTBRK 0x00000080 /* Set TX break */
+#define XUARTPS_CR_TX_DIS 0x00000020 /* TX disabled. */
+#define XUARTPS_CR_TX_EN 0x00000010 /* TX enabled */
+#define XUARTPS_CR_RX_DIS 0x00000008 /* RX disabled. */
+#define XUARTPS_CR_RX_EN 0x00000004 /* RX enabled */
+#define XUARTPS_CR_TXRST 0x00000002 /* TX logic reset */
+#define XUARTPS_CR_RXRST 0x00000001 /* RX logic reset */
+#define XUARTPS_CR_RST_TO 0x00000040 /* Restart Timeout Counter */
+
+/** Mode Register
+ *
+ * The mode register (MR) defines the mode of transfer as well as the data
+ * format. If this register is modified during transmission or reception,
+ * data validity cannot be guaranteed.
+ *
+ * Mode Register Bit Definitions
+ *
+ */
+#define XUARTPS_MR_CLKSEL 0x00000001 /* Pre-scalar selection */
+#define XUARTPS_MR_CHMODE_L_LOOP 0x00000200 /* Local loop back mode */
+#define XUARTPS_MR_CHMODE_NORM 0x00000000 /* Normal mode */
+
+#define XUARTPS_MR_STOPMODE_2_BIT 0x00000080 /* 2 stop bits */
+#define XUARTPS_MR_STOPMODE_1_BIT 0x00000000 /* 1 stop bit */
+
+#define XUARTPS_MR_PARITY_NONE 0x00000020 /* No parity mode */
+#define XUARTPS_MR_PARITY_MARK 0x00000018 /* Mark parity mode */
+#define XUARTPS_MR_PARITY_SPACE 0x00000010 /* Space parity mode */
+#define XUARTPS_MR_PARITY_ODD 0x00000008 /* Odd parity mode */
+#define XUARTPS_MR_PARITY_EVEN 0x00000000 /* Even parity mode */
+
+#define XUARTPS_MR_CHARLEN_6_BIT 0x00000006 /* 6 bits data */
+#define XUARTPS_MR_CHARLEN_7_BIT 0x00000004 /* 7 bits data */
+#define XUARTPS_MR_CHARLEN_8_BIT 0x00000000 /* 8 bits data */
+
+/** Interrupt Registers
+ *
+ * Interrupt control logic uses the interrupt enable register (IER) and the
+ * interrupt disable register (IDR) to set the value of the bits in the
+ * interrupt mask register (IMR). The IMR determines whether to pass an
+ * interrupt to the interrupt status register (ISR).
+ * Writing a 1 to IER Enables an interrupt, writing a 1 to IDR disables an
+ * interrupt. IMR and ISR are read only, and IER and IDR are write only.
+ * Reading either IER or IDR returns 0x00.
+ *
+ * All four registers have the same bit definitions.
+ */
+#define XUARTPS_IXR_TOUT 0x00000100 /* RX Timeout error interrupt */
+#define XUARTPS_IXR_PARITY 0x00000080 /* Parity error interrupt */
+#define XUARTPS_IXR_FRAMING 0x00000040 /* Framing error interrupt */
+#define XUARTPS_IXR_OVERRUN 0x00000020 /* Overrun error interrupt */
+#define XUARTPS_IXR_TXFULL 0x00000010 /* TX FIFO Full interrupt */
+#define XUARTPS_IXR_TXEMPTY 0x00000008 /* TX FIFO empty interrupt */
+#define XUARTPS_ISR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt */
+#define XUARTPS_IXR_RXTRIG 0x00000001 /* RX FIFO trigger interrupt */
+#define XUARTPS_IXR_RXFULL 0x00000004 /* RX FIFO full interrupt. */
+#define XUARTPS_IXR_RXEMPTY 0x00000002 /* RX FIFO empty interrupt. */
+#define XUARTPS_IXR_MASK 0x00001FFF /* Valid bit mask */
+
+/** Channel Status Register
+ *
+ * The channel status register (CSR) is provided to enable the control logic
+ * to monitor the status of bits in the channel interrupt status register,
+ * even if these are masked out by the interrupt mask register.
+ */
+#define XUARTPS_SR_RXEMPTY 0x00000002 /* RX FIFO empty */
+#define XUARTPS_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
+#define XUARTPS_SR_TXFULL 0x00000010 /* TX FIFO full */
+#define XUARTPS_SR_RXTRIG 0x00000001 /* Rx Trigger */
+
+/**
+ * xuartps_isr - Interrupt handler
+ * @irq: Irq number
+ * @dev_id: Id of the port
+ *
+ * Returns IRQHANDLED
+ **/
+static irqreturn_t xuartps_isr(int irq, void *dev_id)
+{
+ struct uart_port *port = (struct uart_port *)dev_id;
+ struct tty_struct *tty;
+ unsigned long flags;
+ unsigned int isrstatus, numbytes;
+ unsigned int data;
+ char status = TTY_NORMAL;
+
+ /* Get the tty which could be NULL so don't assume it's valid */
+ tty = tty_port_tty_get(&port->state->port);
+
+ spin_lock_irqsave(&port->lock, flags);
+
+ /* Read the interrupt status register to determine which
+ * interrupt(s) is/are active.
+ */
+ isrstatus = xuartps_readl(XUARTPS_ISR_OFFSET);
+
+ /* drop byte with parity error if IGNPAR specified */
+ if (isrstatus & port->ignore_status_mask & XUARTPS_IXR_PARITY)
+ isrstatus &= ~(XUARTPS_IXR_RXTRIG | XUARTPS_IXR_TOUT);
+
+ isrstatus &= port->read_status_mask;
+ isrstatus &= ~port->ignore_status_mask;
+
+ if ((isrstatus & XUARTPS_IXR_TOUT) ||
+ (isrstatus & XUARTPS_IXR_RXTRIG)) {
+ /* Receive Timeout Interrupt */
+ while ((xuartps_readl(XUARTPS_SR_OFFSET) &
+ XUARTPS_SR_RXEMPTY) != XUARTPS_SR_RXEMPTY) {
+ data = xuartps_readl(XUARTPS_FIFO_OFFSET);
+ port->icount.rx++;
+
+ if (isrstatus & XUARTPS_IXR_PARITY) {
+ port->icount.parity++;
+ status = TTY_PARITY;
+ } else if (isrstatus & XUARTPS_IXR_FRAMING) {
+ port->icount.frame++;
+ status = TTY_FRAME;
+ } else if (isrstatus & XUARTPS_IXR_OVERRUN)
+ port->icount.overrun++;
+
+ if (tty)
+ uart_insert_char(port, isrstatus,
+ XUARTPS_IXR_OVERRUN, data,
+ status);
+ }
+ spin_unlock(&port->lock);
+ if (tty)
+ tty_flip_buffer_push(tty);
+ spin_lock(&port->lock);
+ }
+
+ /* Dispatch an appropriate handler */
+ if ((isrstatus & XUARTPS_IXR_TXEMPTY) == XUARTPS_IXR_TXEMPTY) {
+ if (uart_circ_empty(&port->state->xmit)) {
+ xuartps_writel(XUARTPS_IXR_TXEMPTY,
+ XUARTPS_IDR_OFFSET);
+ } else {
+ numbytes = port->fifosize;
+ /* Break if no more data available in the UART buffer */
+ while (numbytes--) {
+ if (uart_circ_empty(&port->state->xmit))
+ break;
+ /* Get the data from the UART circular buffer
+ * and write it to the xuartps's TX_FIFO
+ * register.
+ */
+ xuartps_writel(
+ port->state->xmit.buf[port->state->xmit.
+ tail], XUARTPS_FIFO_OFFSET);
+
+ port->icount.tx++;
+
+ /* Adjust the tail of the UART buffer and wrap
+ * the buffer if it reaches limit.
+ */
+ port->state->xmit.tail =
+ (port->state->xmit.tail + 1) & \
+ (UART_XMIT_SIZE - 1);
+ }
+
+ if (uart_circ_chars_pending(
+ &port->state->xmit) < WAKEUP_CHARS)
+ uart_write_wakeup(port);
+ }
+ }
+
+ xuartps_writel(isrstatus, XUARTPS_ISR_OFFSET);
+
+ /* be sure to release the lock and tty before leaving */
+ spin_unlock_irqrestore(&port->lock, flags);
+ tty_kref_put(tty);
+
+ return IRQ_HANDLED;
+}
+
+/**
+ * xuartps_set_baud_rate - Calculate and set the baud rate
+ * @port: Handle to the uart port structure
+ * @baud: Baud rate to set
+ *
+ * Returns baud rate, requested baud when possible, or actual baud when there
+ * was too much error
+ **/
+static unsigned int xuartps_set_baud_rate(struct uart_port *port,
+ unsigned int baud)
+{
+ unsigned int sel_clk;
+ unsigned int calc_baud = 0;
+ unsigned int brgr_val, brdiv_val;
+ unsigned int bauderror;
+
+ /* Formula to obtain baud rate is
+ * baud_tx/rx rate = sel_clk/CD * (BDIV + 1)
+ * input_clk = (Uart User Defined Clock or Apb Clock)
+ * depends on UCLKEN in MR Reg
+ * sel_clk = input_clk or input_clk/8;
+ * depends on CLKS in MR reg
+ * CD and BDIV depends on values in
+ * baud rate generate register
+ * baud rate clock divisor register
+ */
+ sel_clk = port->uartclk;
+ if (xuartps_readl(XUARTPS_MR_OFFSET) & XUARTPS_MR_CLKSEL)
+ sel_clk = sel_clk / 8;
+
+ /* Find the best values for baud generation */
+ for (brdiv_val = 4; brdiv_val < 255; brdiv_val++) {
+
+ brgr_val = sel_clk / (baud * (brdiv_val + 1));
+ if (brgr_val < 2 || brgr_val > 65535)
+ continue;
+
+ calc_baud = sel_clk / (brgr_val * (brdiv_val + 1));
+
+ if (baud > calc_baud)
+ bauderror = baud - calc_baud;
+ else
+ bauderror = calc_baud - baud;
+
+ /* use the values when percent error is acceptable */
+ if (((bauderror * 100) / baud) < 3) {
+ calc_baud = baud;
+ break;
+ }
+ }
+
+ /* Set the values for the new baud rate */
+ xuartps_writel(brgr_val, XUARTPS_BAUDGEN_OFFSET);
+ xuartps_writel(brdiv_val, XUARTPS_BAUDDIV_OFFSET);
+
+ return calc_baud;
+}
+
+/*----------------------Uart Operations---------------------------*/
+
+/**
+ * xuartps_start_tx - Start transmitting bytes
+ * @port: Handle to the uart port structure
+ *
+ **/
+static void xuartps_start_tx(struct uart_port *port)
+{
+ unsigned int status, numbytes = port->fifosize;
+
+ if (uart_circ_empty(&port->state->xmit) || uart_tx_stopped(port))
+ return;
+
+ status = xuartps_readl(XUARTPS_CR_OFFSET);
+ /* Set the TX enable bit and clear the TX disable bit to enable the
+ * transmitter.
+ */
+ xuartps_writel((status & ~XUARTPS_CR_TX_DIS) | XUARTPS_CR_TX_EN,
+ XUARTPS_CR_OFFSET);
+
+ while (numbytes-- && ((xuartps_readl(XUARTPS_SR_OFFSET)
+ & XUARTPS_SR_TXFULL)) != XUARTPS_SR_TXFULL) {
+
+ /* Break if no more data available in the UART buffer */
+ if (uart_circ_empty(&port->state->xmit))
+ break;
+
+ /* Get the data from the UART circular buffer and
+ * write it to the xuartps's TX_FIFO register.
+ */
+ xuartps_writel(
+ port->state->xmit.buf[port->state->xmit.tail],
+ XUARTPS_FIFO_OFFSET);
+ port->icount.tx++;
+
+ /* Adjust the tail of the UART buffer and wrap
+ * the buffer if it reaches limit.
+ */
+ port->state->xmit.tail = (port->state->xmit.tail + 1) &
+ (UART_XMIT_SIZE - 1);
+ }
+
+ /* Enable the TX Empty interrupt */
+ xuartps_writel(XUARTPS_IXR_TXEMPTY, XUARTPS_IER_OFFSET);
+
+ if (uart_circ_chars_pending(&port->state->xmit) < WAKEUP_CHARS)
+ uart_write_wakeup(port);
+}
+
+/**
+ * xuartps_stop_tx - Stop TX
+ * @port: Handle to the uart port structure
+ *
+ **/
+static void xuartps_stop_tx(struct uart_port *port)
+{
+ unsigned int regval;
+
+ regval = xuartps_readl(XUARTPS_CR_OFFSET);
+ regval |= XUARTPS_CR_TX_DIS;
+ /* Disable the transmitter */
+ xuartps_writel(regval, XUARTPS_CR_OFFSET);
+}
+
+/**
+ * xuartps_stop_rx - Stop RX
+ * @port: Handle to the uart port structure
+ *
+ **/
+static void xuartps_stop_rx(struct uart_port *port)
+{
+ unsigned int regval;
+
+ regval = xuartps_readl(XUARTPS_CR_OFFSET);
+ regval |= XUARTPS_CR_RX_DIS;
+ /* Disable the receiver */
+ xuartps_writel(regval, XUARTPS_CR_OFFSET);
+}
+
+/**
+ * xuartps_tx_empty - Check whether TX is empty
+ * @port: Handle to the uart port structure
+ *
+ * Returns TIOCSER_TEMT on success, 0 otherwise
+ **/
+static unsigned int xuartps_tx_empty(struct uart_port *port)
+{
+ unsigned int status;
+
+ status = xuartps_readl(XUARTPS_ISR_OFFSET) & XUARTPS_IXR_TXEMPTY;
+ return status ? TIOCSER_TEMT : 0;
+}
+
+/**
+ * xuartps_break_ctl - Based on the input ctl we have to start or stop
+ * transmitting char breaks
+ * @port: Handle to the uart port structure
+ * @ctl: Value based on which start or stop decision is taken
+ *
+ **/
+static void xuartps_break_ctl(struct uart_port *port, int ctl)
+{
+ unsigned int status;
+ unsigned long flags;
+
+ spin_lock_irqsave(&port->lock, flags);
+
+ status = xuartps_readl(XUARTPS_CR_OFFSET);
+
+ if (ctl == -1)
+ xuartps_writel(XUARTPS_CR_STARTBRK | status,
+ XUARTPS_CR_OFFSET);
+ else {
+ if ((status & XUARTPS_CR_STOPBRK) == 0)
+ xuartps_writel(XUARTPS_CR_STOPBRK | status,
+ XUARTPS_CR_OFFSET);
+ }
+ spin_unlock_irqrestore(&port->lock, flags);
+}
+
+/**
+ * xuartps_set_termios - termios operations, handling data length, parity,
+ * stop bits, flow control, baud rate
+ * @port: Handle to the uart port structure
+ * @termios: Handle to the input termios structure
+ * @old: Values of the previously saved termios structure
+ *
+ **/
+static void xuartps_set_termios(struct uart_port *port,
+ struct ktermios *termios, struct ktermios *old)
+{
+ unsigned int cval = 0;
+ unsigned int baud;
+ unsigned long flags;
+ unsigned int ctrl_reg, mode_reg;
+
+ spin_lock_irqsave(&port->lock, flags);
+
+ /* Empty the receive FIFO 1st before making changes */
+ while ((xuartps_readl(XUARTPS_SR_OFFSET) &
+ XUARTPS_SR_RXEMPTY) != XUARTPS_SR_RXEMPTY) {
+ xuartps_readl(XUARTPS_FIFO_OFFSET);
+ }
+
+ /* Disable the TX and RX to set baud rate */
+ xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) |
+ (XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS),
+ XUARTPS_CR_OFFSET);
+
+ /* Min baud rate = 6bps and Max Baud Rate is 10Mbps for 100Mhz clk */
+ baud = uart_get_baud_rate(port, termios, old, 0, 10000000);
+ baud = xuartps_set_baud_rate(port, baud);
+ if (tty_termios_baud_rate(termios))
+ tty_termios_encode_baud_rate(termios, baud, baud);
+
+ /*
+ * Update the per-port timeout.
+ */
+ uart_update_timeout(port, termios->c_cflag, baud);
+
+ /* Set TX/RX Reset */
+ xuartps_writel(xuartps_readl(XUARTPS_CR_OFFSET) |
+ (XUARTPS_CR_TXRST | XUARTPS_CR_RXRST),
+ XUARTPS_CR_OFFSET);
+
+ ctrl_reg = xuartps_readl(XUARTPS_CR_OFFSET);
+
+ /* Clear the RX disable and TX disable bits and then set the TX enable
+ * bit and RX enable bit to enable the transmitter and receiver.
+ */
+ xuartps_writel(
+ (ctrl_reg & ~(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS))
+ | (XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN),
+ XUARTPS_CR_OFFSET);
+
+ xuartps_writel(10, XUARTPS_RXTOUT_OFFSET);
+
+ port->read_status_mask = XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_RXTRIG |
+ XUARTPS_IXR_OVERRUN | XUARTPS_IXR_TOUT;
+ port->ignore_status_mask = 0;
+
+ if (termios->c_iflag & INPCK)
+ port->read_status_mask |= XUARTPS_IXR_PARITY |
+ XUARTPS_IXR_FRAMING;
+
+ if (termios->c_iflag & IGNPAR)
+ port->ignore_status_mask |= XUARTPS_IXR_PARITY |
+ XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN;
+
+ /* ignore all characters if CREAD is not set */
+ if ((termios->c_cflag & CREAD) == 0)
+ port->ignore_status_mask |= XUARTPS_IXR_RXTRIG |
+ XUARTPS_IXR_TOUT | XUARTPS_IXR_PARITY |
+ XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN;
+
+ mode_reg = xuartps_readl(XUARTPS_MR_OFFSET);
+
+ /* Handling Data Size */
+ switch (termios->c_cflag & CSIZE) {
+ case CS6:
+ cval |= XUARTPS_MR_CHARLEN_6_BIT;
+ break;
+ case CS7:
+ cval |= XUARTPS_MR_CHARLEN_7_BIT;
+ break;
+ default:
+ case CS8:
+ cval |= XUARTPS_MR_CHARLEN_8_BIT;
+ termios->c_cflag &= ~CSIZE;
+ termios->c_cflag |= CS8;
+ break;
+ }
+
+ /* Handling Parity and Stop Bits length */
+ if (termios->c_cflag & CSTOPB)
+ cval |= XUARTPS_MR_STOPMODE_2_BIT; /* 2 STOP bits */
+ else
+ cval |= XUARTPS_MR_STOPMODE_1_BIT; /* 1 STOP bit */
+
+ if (termios->c_cflag & PARENB) {
+ /* Mark or Space parity */
+ if (termios->c_cflag & CMSPAR) {
+ if (termios->c_cflag & PARODD)
+ cval |= XUARTPS_MR_PARITY_MARK;
+ else
+ cval |= XUARTPS_MR_PARITY_SPACE;
+ } else if (termios->c_cflag & PARODD)
+ cval |= XUARTPS_MR_PARITY_ODD;
+ else
+ cval |= XUARTPS_MR_PARITY_EVEN;
+ } else
+ cval |= XUARTPS_MR_PARITY_NONE;
+ xuartps_writel(cval , XUARTPS_MR_OFFSET);
+
+ spin_unlock_irqrestore(&port->lock, flags);
+}
+
+/**
+ * xuartps_startup - Called when an application opens a xuartps port
+ * @port: Handle to the uart port structure
+ *
+ * Returns 0 on success, negative error otherwise
+ **/
+static int xuartps_startup(struct uart_port *port)
+{
+ unsigned int retval = 0, status = 0;
+
+ retval = request_irq(port->irq, xuartps_isr, 0, XUARTPS_NAME,
+ (void *)port);
+ if (retval)
+ return retval;
+
+ /* Disable the TX and RX */
+ xuartps_writel(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS,
+ XUARTPS_CR_OFFSET);
+
+ /* Set the Control Register with TX/RX Enable, TX/RX Reset,
+ * no break chars.
+ */
+ xuartps_writel(XUARTPS_CR_TXRST | XUARTPS_CR_RXRST,
+ XUARTPS_CR_OFFSET);
+
+ status = xuartps_readl(XUARTPS_CR_OFFSET);
+
+ /* Clear the RX disable and TX disable bits and then set the TX enable
+ * bit and RX enable bit to enable the transmitter and receiver.
+ */
+ xuartps_writel((status & ~(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS))
+ | (XUARTPS_CR_TX_EN | XUARTPS_CR_RX_EN |
+ XUARTPS_CR_STOPBRK), XUARTPS_CR_OFFSET);
+
+ /* Set the Mode Register with normal mode,8 data bits,1 stop bit,
+ * no parity.
+ */
+ xuartps_writel(XUARTPS_MR_CHMODE_NORM | XUARTPS_MR_STOPMODE_1_BIT
+ | XUARTPS_MR_PARITY_NONE | XUARTPS_MR_CHARLEN_8_BIT,
+ XUARTPS_MR_OFFSET);
+
+ /* Set the RX FIFO Trigger level to 14 assuming FIFO size as 16 */
+ xuartps_writel(14, XUARTPS_RXWM_OFFSET);
+
+ /* Receive Timeout register is enabled with value of 10 */
+ xuartps_writel(10, XUARTPS_RXTOUT_OFFSET);
+
+
+ /* Set the Interrupt Registers with desired interrupts */
+ xuartps_writel(XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_PARITY |
+ XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN |
+ XUARTPS_IXR_RXTRIG | XUARTPS_IXR_TOUT, XUARTPS_IER_OFFSET);
+ xuartps_writel(~(XUARTPS_IXR_TXEMPTY | XUARTPS_IXR_PARITY |
+ XUARTPS_IXR_FRAMING | XUARTPS_IXR_OVERRUN |
+ XUARTPS_IXR_RXTRIG | XUARTPS_IXR_TOUT), XUARTPS_IDR_OFFSET);
+
+ return retval;
+}
+
+/**
+ * xuartps_shutdown - Called when an application closes a xuartps port
+ * @port: Handle to the uart port structure
+ *
+ **/
+static void xuartps_shutdown(struct uart_port *port)
+{
+ int status;
+
+ /* Disable interrupts */
+ status = xuartps_readl(XUARTPS_IMR_OFFSET);
+ xuartps_writel(status, XUARTPS_IDR_OFFSET);
+
+ /* Disable the TX and RX */
+ xuartps_writel(XUARTPS_CR_TX_DIS | XUARTPS_CR_RX_DIS,
+ XUARTPS_CR_OFFSET);
+ free_irq(port->irq, port);
+}
+
+/**
+ * xuartps_type - Set UART type to xuartps port
+ * @port: Handle to the uart port structure
+ *
+ * Returns string on success, NULL otherwise
+ **/
+static const char *xuartps_type(struct uart_port *port)
+{
+ return port->type == PORT_XUARTPS ? XUARTPS_NAME : NULL;
+}
+
+/**
+ * xuartps_verify_port - Verify the port params
+ * @port: Handle to the uart port structure
+ * @ser: Handle to the structure whose members are compared
+ *
+ * Returns 0 if success otherwise -EINVAL
+ **/
+static int xuartps_verify_port(struct uart_port *port,
+ struct serial_struct *ser)
+{
+ if (ser->type != PORT_UNKNOWN && ser->type != PORT_XUARTPS)
+ return -EINVAL;
+ if (port->irq != ser->irq)
+ return -EINVAL;
+ if (ser->io_type != UPIO_MEM)
+ return -EINVAL;
+ if (port->iobase != ser->port)
+ return -EINVAL;
+ if (ser->hub6 != 0)
+ return -EINVAL;
+ return 0;
+}
+
+/**
+ * xuartps_request_port - Claim the memory region attached to xuartps port,
+ * called when the driver adds a xuartps port via
+ * uart_add_one_port()
+ * @port: Handle to the uart port structure
+ *
+ * Returns 0, -ENOMEM if request fails
+ **/
+static int xuartps_request_port(struct uart_port *port)
+{
+ if (!request_mem_region(port->mapbase, XUARTPS_REGISTER_SPACE,
+ XUARTPS_NAME)) {
+ return -ENOMEM;
+ }
+
+ port->membase = ioremap(port->mapbase, XUARTPS_REGISTER_SPACE);
+ if (!port->membase) {
+ dev_err(port->dev, "Unable to map registers\n");
+ release_mem_region(port->mapbase, XUARTPS_REGISTER_SPACE);
+ return -ENOMEM;
+ }
+ return 0;
+}
+
+/**
+ * xuartps_release_port - Release the memory region attached to a xuartps
+ * port, called when the driver removes a xuartps
+ * port via uart_remove_one_port().
+ * @port: Handle to the uart port structure
+ *
+ **/
+static void xuartps_release_port(struct uart_port *port)
+{
+ release_mem_region(port->mapbase, XUARTPS_REGISTER_SPACE);
+ iounmap(port->membase);
+ port->membase = NULL;
+}
+
+/**
+ * xuartps_config_port - Configure xuartps, called when the driver adds a
+ * xuartps port
+ * @port: Handle to the uart port structure
+ * @flags: If any
+ *
+ **/
+static void xuartps_config_port(struct uart_port *port, int flags)
+{
+ if (flags & UART_CONFIG_TYPE && xuartps_request_port(port) == 0)
+ port->type = PORT_XUARTPS;
+}
+
+/**
+ * xuartps_get_mctrl - Get the modem control state
+ *
+ * @port: Handle to the uart port structure
+ *
+ * Returns the modem control state
+ *
+ **/
+static unsigned int xuartps_get_mctrl(struct uart_port *port)
+{
+ return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
+}
+
+static void xuartps_set_mctrl(struct uart_port *port, unsigned int mctrl)
+{
+ /* N/A */
+}
+
+static void xuartps_enable_ms(struct uart_port *port)
+{
+ /* N/A */
+}
+
+/** The UART operations structure
+ */
+static struct uart_ops xuartps_ops = {
+ .set_mctrl = xuartps_set_mctrl,
+ .get_mctrl = xuartps_get_mctrl,
+ .enable_ms = xuartps_enable_ms,
+
+ .start_tx = xuartps_start_tx, /* Start transmitting */
+ .stop_tx = xuartps_stop_tx, /* Stop transmission */
+ .stop_rx = xuartps_stop_rx, /* Stop reception */
+ .tx_empty = xuartps_tx_empty, /* Transmitter busy? */
+ .break_ctl = xuartps_break_ctl, /* Start/stop
+ * transmitting break
+ */
+ .set_termios = xuartps_set_termios, /* Set termios */
+ .startup = xuartps_startup, /* App opens xuartps */
+ .shutdown = xuartps_shutdown, /* App closes xuartps */
+ .type = xuartps_type, /* Set UART type */
+ .verify_port = xuartps_verify_port, /* Verification of port
+ * params
+ */
+ .request_port = xuartps_request_port, /* Claim resources
+ * associated with a
+ * xuartps port
+ */
+ .release_port = xuartps_release_port, /* Release resources
+ * associated with a
+ * xuartps port
+ */
+ .config_port = xuartps_config_port, /* Configure when driver
+ * adds a xuartps port
+ */
+};
+
+static struct uart_port xuartps_port[2];
+
+/**
+ * xuartps_get_port - Configure the port from the platform device resource
+ * info
+ *
+ * Returns a pointer to a uart_port or NULL for failure
+ **/
+static struct uart_port *xuartps_get_port(void)
+{
+ struct uart_port *port;
+ int id;
+
+ /* Find the next unused port */
+ for (id = 0; id < XUARTPS_NR_PORTS; id++)
+ if (xuartps_port[id].mapbase == 0)
+ break;
+
+ if (id >= XUARTPS_NR_PORTS)
+ return NULL;
+
+ port = &xuartps_port[id];
+
+ /* At this point, we've got an empty uart_port struct, initialize it */
+ spin_lock_init(&port->lock);
+ port->membase = NULL;
+ port->iobase = 1; /* mark port in use */
+ port->irq = 0;
+ port->type = PORT_UNKNOWN;
+ port->iotype = UPIO_MEM32;
+ port->flags = UPF_BOOT_AUTOCONF;
+ port->ops = &xuartps_ops;
+ port->fifosize = XUARTPS_FIFO_SIZE;
+ port->line = id;
+ port->dev = NULL;
+ return port;
+}
+
+/*-----------------------Console driver operations--------------------------*/
+
+#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
+/**
+ * xuartps_console_wait_tx - Wait for the TX to be full
+ * @port: Handle to the uart port structure
+ *
+ **/
+static void xuartps_console_wait_tx(struct uart_port *port)
+{
+ while ((xuartps_readl(XUARTPS_SR_OFFSET) & XUARTPS_SR_TXEMPTY)
+ != XUARTPS_SR_TXEMPTY)
+ barrier();
+}
+
+/**
+ * xuartps_console_putchar - write the character to the FIFO buffer
+ * @port: Handle to the uart port structure
+ * @ch: Character to be written
+ *
+ **/
+static void xuartps_console_putchar(struct uart_port *port, int ch)
+{
+ xuartps_console_wait_tx(port);
+ xuartps_writel(ch, XUARTPS_FIFO_OFFSET);
+}
+
+/**
+ * xuartps_console_write - perform write operation
+ * @port: Handle to the uart port structure
+ * @s: Pointer to character array
+ * @count: No of characters
+ **/
+static void xuartps_console_write(struct console *co, const char *s,
+ unsigned int count)
+{
+ struct uart_port *port = &xuartps_port[co->index];
+ unsigned long flags;
+ unsigned int imr;
+ int locked = 1;
+
+ if (oops_in_progress)
+ locked = spin_trylock_irqsave(&port->lock, flags);
+ else
+ spin_lock_irqsave(&port->lock, flags);
+
+ /* save and disable interrupt */
+ imr = xuartps_readl(XUARTPS_IMR_OFFSET);
+ xuartps_writel(imr, XUARTPS_IDR_OFFSET);
+
+ uart_console_write(port, s, count, xuartps_console_putchar);
+ xuartps_console_wait_tx(port);
+
+ /* restore interrupt state, it seems like there may be a h/w bug
+ * in that the interrupt enable register should not need to be
+ * written based on the data sheet
+ */
+ xuartps_writel(~imr, XUARTPS_IDR_OFFSET);
+ xuartps_writel(imr, XUARTPS_IER_OFFSET);
+
+ if (locked)
+ spin_unlock_irqrestore(&port->lock, flags);
+}
+
+/**
+ * xuartps_console_setup - Initialize the uart to default config
+ * @co: Console handle
+ * @options: Initial settings of uart
+ *
+ * Returns 0, -ENODEV if no device
+ **/
+static int __init xuartps_console_setup(struct console *co, char *options)
+{
+ struct uart_port *port = &xuartps_port[co->index];
+ int baud = 9600;
+ int bits = 8;
+ int parity = 'n';
+ int flow = 'n';
+
+ if (co->index < 0 || co->index >= XUARTPS_NR_PORTS)
+ return -EINVAL;
+
+ if (!port->mapbase) {
+ pr_debug("console on ttyPS%i not present\n", co->index);
+ return -ENODEV;
+ }
+
+ if (options)
+ uart_parse_options(options, &baud, &parity, &bits, &flow);
+
+ return uart_set_options(port, co, baud, parity, bits, flow);
+}
+
+static struct uart_driver xuartps_uart_driver;
+
+static struct console xuartps_console = {
+ .name = XUARTPS_TTY_NAME,
+ .write = xuartps_console_write,
+ .device = uart_console_device,
+ .setup = xuartps_console_setup,
+ .flags = CON_PRINTBUFFER,
+ .index = -1, /* Specified on the cmdline (e.g. console=ttyPS ) */
+ .data = &xuartps_uart_driver,
+};
+
+/**
+ * xuartps_console_init - Initialization call
+ *
+ * Returns 0 on success, negative error otherwise
+ **/
+static int __init xuartps_console_init(void)
+{
+ register_console(&xuartps_console);
+ return 0;
+}
+
+console_initcall(xuartps_console_init);
+
+#endif /* CONFIG_SERIAL_XILINX_PS_UART_CONSOLE */
+
+/** Structure Definitions
+ */
+static struct uart_driver xuartps_uart_driver = {
+ .owner = THIS_MODULE, /* Owner */
+ .driver_name = XUARTPS_NAME, /* Driver name */
+ .dev_name = XUARTPS_TTY_NAME, /* Node name */
+ .major = XUARTPS_MAJOR, /* Major number */
+ .minor = XUARTPS_MINOR, /* Minor number */
+ .nr = XUARTPS_NR_PORTS, /* Number of UART ports */
+#ifdef CONFIG_SERIAL_XILINX_PS_UART_CONSOLE
+ .cons = &xuartps_console, /* Console */
+#endif
+};
+
+/* ---------------------------------------------------------------------
+ * Platform bus binding
+ */
+/**
+ * xuartps_probe - Platform driver probe
+ * @pdev: Pointer to the platform device structure
+ *
+ * Returns 0 on success, negative error otherwise
+ **/
+static int __devinit xuartps_probe(struct platform_device *pdev)
+{
+ int rc;
+ struct uart_port *port;
+ struct resource *res, *res2;
+ int clk = 0;
+
+#ifdef CONFIG_OF
+ const unsigned int *prop;
+
+ prop = of_get_property(pdev->dev.of_node, "clock", NULL);
+ if (prop)
+ clk = be32_to_cpup(prop);
+#else
+ clk = *((unsigned int *)(pdev->dev.platform_data));
+#endif
+ if (!clk) {
+ dev_err(&pdev->dev, "no clock specified\n");
+ return -ENODEV;
+ }
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res)
+ return -ENODEV;
+
+ res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+ if (!res2)
+ return -ENODEV;
+
+ /* Initialize the port structure */
+ port = xuartps_get_port();
+
+ if (!port) {
+ dev_err(&pdev->dev, "Cannot get uart_port structure\n");
+ return -ENODEV;
+ } else {
+ /* Register the port.
+ * This function also registers this device with the tty layer
+ * and triggers invocation of the config_port() entry point.
+ */
+ port->mapbase = res->start;
+ port->irq = res2->start;
+ port->dev = &pdev->dev;
+ port->uartclk = clk;
+ dev_set_drvdata(&pdev->dev, port);
+ rc = uart_add_one_port(&xuartps_uart_driver, port);
+ if (rc) {
+ dev_err(&pdev->dev,
+ "uart_add_one_port() failed; err=%i\n", rc);
+ dev_set_drvdata(&pdev->dev, NULL);
+ return rc;
+ }
+ return 0;
+ }
+}
+
+/**
+ * xuartps_remove - called when the platform driver is unregistered
+ * @pdev: Pointer to the platform device structure
+ *
+ * Returns 0 on success, negative error otherwise
+ **/
+static int __devexit xuartps_remove(struct platform_device *pdev)
+{
+ struct uart_port *port = dev_get_drvdata(&pdev->dev);
+ int rc = 0;
+
+ /* Remove the xuartps port from the serial core */
+ if (port) {
+ rc = uart_remove_one_port(&xuartps_uart_driver, port);
+ dev_set_drvdata(&pdev->dev, NULL);
+ port->mapbase = 0;
+ }
+ return rc;
+}
+
+/**
+ * xuartps_suspend - suspend event
+ * @pdev: Pointer to the platform device structure
+ * @state: State of the device
+ *
+ * Returns 0
+ **/
+static int xuartps_suspend(struct platform_device *pdev, pm_message_t state)
+{
+ /* Call the API provided in serial_core.c file which handles
+ * the suspend.
+ */
+ uart_suspend_port(&xuartps_uart_driver, &xuartps_port[pdev->id]);
+ return 0;
+}
+
+/**
+ * xuartps_resume - Resume after a previous suspend
+ * @pdev: Pointer to the platform device structure
+ *
+ * Returns 0
+ **/
+static int xuartps_resume(struct platform_device *pdev)
+{
+ uart_resume_port(&xuartps_uart_driver, &xuartps_port[pdev->id]);
+ return 0;
+}
+
+/* Match table for of_platform binding */
+
+#ifdef CONFIG_OF
+static struct of_device_id xuartps_of_match[] __devinitdata = {
+ { .compatible = "xlnx,xuartps", },
+ {}
+};
+MODULE_DEVICE_TABLE(of, xuartps_of_match);
+#else
+#define xuartps_of_match NULL
+#endif
+
+static struct platform_driver xuartps_platform_driver = {
+ .probe = xuartps_probe, /* Probe method */
+ .remove = __exit_p(xuartps_remove), /* Detach method */
+ .suspend = xuartps_suspend, /* Suspend */
+ .resume = xuartps_resume, /* Resume after a suspend */
+ .driver = {
+ .owner = THIS_MODULE,
+ .name = XUARTPS_NAME, /* Driver name */
+ .of_match_table = xuartps_of_match,
+ },
+};
+
+/* ---------------------------------------------------------------------
+ * Module Init and Exit
+ */
+/**
+ * xuartps_init - Initial driver registration call
+ *
+ * Returns whether the registration was successful or not
+ **/
+static int __init xuartps_init(void)
+{
+ int retval = 0;
+
+ /* Register the xuartps driver with the serial core */
+ retval = uart_register_driver(&xuartps_uart_driver);
+ if (retval)
+ return retval;
+
+ /* Register the platform driver */
+ retval = platform_driver_register(&xuartps_platform_driver);
+ if (retval)
+ uart_unregister_driver(&xuartps_uart_driver);
+
+ return retval;
+}
+
+/**
+ * xuartps_exit - Driver unregistration call
+ **/
+static void __exit xuartps_exit(void)
+{
+ /* The order of unregistration is important. Unregister the
+ * UART driver before the platform driver crashes the system.
+ */
+
+ /* Unregister the platform driver */
+ platform_driver_unregister(&xuartps_platform_driver);
+
+ /* Unregister the xuartps driver */
+ uart_unregister_driver(&xuartps_uart_driver);
+}
+
+module_init(xuartps_init);
+module_exit(xuartps_exit);
+
+MODULE_DESCRIPTION("Driver for PS UART");
+MODULE_AUTHOR("Xilinx Inc.");
+MODULE_LICENSE("GPL");
diff --git a/drivers/tty/synclink.c b/drivers/tty/synclink.c
index 27da23d..272e417 100644
--- a/drivers/tty/synclink.c
+++ b/drivers/tty/synclink.c
@@ -1,6 +1,4 @@
/*
- * linux/drivers/char/synclink.c
- *
* $Id: synclink.c,v 4.38 2005/11/07 16:30:34 paulkf Exp $
*
* Device driver for Microgate SyncLink ISA and PCI
diff --git a/drivers/tty/tty_buffer.c b/drivers/tty/tty_buffer.c
index f1a7918..46de2e0 100644
--- a/drivers/tty/tty_buffer.c
+++ b/drivers/tty/tty_buffer.c
@@ -416,6 +416,7 @@
struct tty_buffer *head, *tail = tty->buf.tail;
int seen_tail = 0;
while ((head = tty->buf.head) != NULL) {
+ int copied;
int count;
char *char_buf;
unsigned char *flag_buf;
@@ -442,17 +443,19 @@
line discipline as we want to empty the queue */
if (test_bit(TTY_FLUSHPENDING, &tty->flags))
break;
- if (!tty->receive_room || seen_tail)
- break;
- if (count > tty->receive_room)
- count = tty->receive_room;
char_buf = head->char_buf_ptr + head->read;
flag_buf = head->flag_buf_ptr + head->read;
- head->read += count;
spin_unlock_irqrestore(&tty->buf.lock, flags);
- disc->ops->receive_buf(tty, char_buf,
+ copied = disc->ops->receive_buf(tty, char_buf,
flag_buf, count);
spin_lock_irqsave(&tty->buf.lock, flags);
+
+ head->read += copied;
+
+ if (copied == 0 || seen_tail) {
+ schedule_work(&tty->buf.work);
+ break;
+ }
}
clear_bit(TTY_FLUSHING, &tty->flags);
}
diff --git a/drivers/tty/tty_io.c b/drivers/tty/tty_io.c
index d7d50b4..6556f74 100644
--- a/drivers/tty/tty_io.c
+++ b/drivers/tty/tty_io.c
@@ -1,6 +1,4 @@
/*
- * linux/drivers/char/tty_io.c
- *
* Copyright (C) 1991, 1992 Linus Torvalds
*/
@@ -964,12 +962,14 @@
}
void tty_write_unlock(struct tty_struct *tty)
+ __releases(&tty->atomic_write_lock)
{
mutex_unlock(&tty->atomic_write_lock);
wake_up_interruptible_poll(&tty->write_wait, POLLOUT);
}
int tty_write_lock(struct tty_struct *tty, int ndelay)
+ __acquires(&tty->atomic_write_lock)
{
if (!mutex_trylock(&tty->atomic_write_lock)) {
if (ndelay)
@@ -1391,16 +1391,15 @@
return ERR_PTR(-ENODEV);
tty = alloc_tty_struct();
- if (!tty)
- goto fail_no_mem;
+ if (!tty) {
+ retval = -ENOMEM;
+ goto err_module_put;
+ }
initialize_tty_struct(tty, driver, idx);
retval = tty_driver_install_tty(driver, tty);
- if (retval < 0) {
- free_tty_struct(tty);
- module_put(driver->owner);
- return ERR_PTR(retval);
- }
+ if (retval < 0)
+ goto err_deinit_tty;
/*
* Structures all installed ... call the ldisc open routines.
@@ -1409,15 +1408,18 @@
*/
retval = tty_ldisc_setup(tty, tty->link);
if (retval)
- goto release_mem_out;
+ goto err_release_tty;
return tty;
-fail_no_mem:
+err_deinit_tty:
+ deinitialize_tty_struct(tty);
+ free_tty_struct(tty);
+err_module_put:
module_put(driver->owner);
- return ERR_PTR(-ENOMEM);
+ return ERR_PTR(retval);
/* call the tty release_tty routine to clean out this slot */
-release_mem_out:
+err_release_tty:
if (printk_ratelimit())
printk(KERN_INFO "tty_init_dev: ldisc open failed, "
"clearing slot %d\n", idx);
@@ -1892,6 +1894,7 @@
retval = tty_add_file(tty, filp);
if (retval) {
tty_unlock();
+ tty_release(inode, filp);
return retval;
}
@@ -1902,12 +1905,10 @@
#ifdef TTY_DEBUG_HANGUP
printk(KERN_DEBUG "opening %s...", tty->name);
#endif
- if (!retval) {
- if (tty->ops->open)
- retval = tty->ops->open(tty, filp);
- else
- retval = -ENODEV;
- }
+ if (tty->ops->open)
+ retval = tty->ops->open(tty, filp);
+ else
+ retval = -ENODEV;
filp->f_flags = saved_flags;
if (!retval && test_bit(TTY_EXCLUSIVE, &tty->flags) &&
@@ -2888,6 +2889,20 @@
}
/**
+ * deinitialize_tty_struct
+ * @tty: tty to deinitialize
+ *
+ * This subroutine deinitializes a tty structure that has been newly
+ * allocated but tty_release cannot be called on that yet.
+ *
+ * Locking: none - tty in question must not be exposed at this point
+ */
+void deinitialize_tty_struct(struct tty_struct *tty)
+{
+ tty_ldisc_deinit(tty);
+}
+
+/**
* tty_put_char - write one character to a tty
* @tty: tty
* @ch: character
diff --git a/drivers/tty/tty_ioctl.c b/drivers/tty/tty_ioctl.c
index 620c971..53f2442 100644
--- a/drivers/tty/tty_ioctl.c
+++ b/drivers/tty/tty_ioctl.c
@@ -1,6 +1,4 @@
/*
- * linux/drivers/char/tty_ioctl.c
- *
* Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
*
* Modified by Fred N. van Kempen, 01/29/93, to add line disciplines
diff --git a/drivers/tty/tty_ldisc.c b/drivers/tty/tty_ldisc.c
index e19e136..5d01d32 100644
--- a/drivers/tty/tty_ldisc.c
+++ b/drivers/tty/tty_ldisc.c
@@ -956,6 +956,19 @@
tty_ldisc_assign(tty, ld);
}
+/**
+ * tty_ldisc_init - ldisc cleanup for new tty
+ * @tty: tty that was allocated recently
+ *
+ * The tty structure must not becompletely set up (tty_ldisc_setup) when
+ * this call is made.
+ */
+void tty_ldisc_deinit(struct tty_struct *tty)
+{
+ put_ldisc(tty->ldisc);
+ tty_ldisc_assign(tty, NULL);
+}
+
void tty_ldisc_begin(void)
{
/* Setup the default TTY line discipline. */
diff --git a/drivers/tty/tty_mutex.c b/drivers/tty/tty_mutex.c
index 1336975..3b2bb77 100644
--- a/drivers/tty/tty_mutex.c
+++ b/drivers/tty/tty_mutex.c
@@ -1,6 +1,3 @@
-/*
- * drivers/char/tty_lock.c
- */
#include <linux/tty.h>
#include <linux/module.h>
#include <linux/kallsyms.h>
diff --git a/drivers/tty/vt/keyboard.c b/drivers/tty/vt/keyboard.c
index d6b342b..3761ccf 100644
--- a/drivers/tty/vt/keyboard.c
+++ b/drivers/tty/vt/keyboard.c
@@ -1,6 +1,4 @@
/*
- * linux/drivers/char/keyboard.c
- *
* Written for linux by Johan Myreen as a translation from
* the assembly version by Linus (with diacriticals added)
*
diff --git a/drivers/tty/vt/selection.c b/drivers/tty/vt/selection.c
index adf0ad2..67b1d0d 100644
--- a/drivers/tty/vt/selection.c
+++ b/drivers/tty/vt/selection.c
@@ -1,6 +1,4 @@
/*
- * linux/drivers/char/selection.c
- *
* This module exports the functions:
*
* 'int set_selection(struct tiocl_selection __user *, struct tty_struct *)'
@@ -334,8 +332,7 @@
continue;
}
count = sel_buffer_lth - pasted;
- count = min(count, tty->receive_room);
- tty->ldisc->ops->receive_buf(tty, sel_buffer + pasted,
+ count = tty->ldisc->ops->receive_buf(tty, sel_buffer + pasted,
NULL, count);
pasted += count;
}
diff --git a/drivers/tty/vt/vc_screen.c b/drivers/tty/vt/vc_screen.c
index 1564261..66825c9 100644
--- a/drivers/tty/vt/vc_screen.c
+++ b/drivers/tty/vt/vc_screen.c
@@ -1,6 +1,4 @@
/*
- * linux/drivers/char/vc_screen.c
- *
* Provide access to virtual console memory.
* /dev/vcs0: the screen as it is being viewed right now (possibly scrolled)
* /dev/vcsN: the screen of /dev/ttyN (1 <= N <= 63)
diff --git a/drivers/tty/vt/vt.c b/drivers/tty/vt/vt.c
index 4bea1ef..b3915b7 100644
--- a/drivers/tty/vt/vt.c
+++ b/drivers/tty/vt/vt.c
@@ -1,6 +1,4 @@
/*
- * linux/drivers/char/vt.c
- *
* Copyright (C) 1991, 1992 Linus Torvalds
*/
@@ -858,7 +856,7 @@
{
unsigned long old_origin, new_origin, new_scr_end, rlth, rrem, err = 0;
unsigned long end;
- unsigned int old_cols, old_rows, old_row_size, old_screen_size;
+ unsigned int old_rows, old_row_size;
unsigned int new_cols, new_rows, new_row_size, new_screen_size;
unsigned int user;
unsigned short *newscreen;
@@ -887,9 +885,7 @@
return -ENOMEM;
old_rows = vc->vc_rows;
- old_cols = vc->vc_cols;
old_row_size = vc->vc_size_row;
- old_screen_size = vc->vc_screenbuf_size;
err = resize_screen(vc, new_cols, new_rows, user);
if (err) {
@@ -1197,6 +1193,13 @@
vc->vc_x + 1);
}
break;
+ case 3: /* erase scroll-back buffer (and whole display) */
+ scr_memsetw(vc->vc_screenbuf, vc->vc_video_erase_char,
+ vc->vc_screenbuf_size >> 1);
+ set_origin(vc);
+ if (CON_IS_VISIBLE(vc))
+ update_screen(vc);
+ /* fall through */
case 2: /* erase whole display */
count = vc->vc_cols * vc->vc_rows;
start = (unsigned short *)vc->vc_origin;
diff --git a/drivers/tty/vt/vt_ioctl.c b/drivers/tty/vt/vt_ioctl.c
index 937d172..5e096f4 100644
--- a/drivers/tty/vt/vt_ioctl.c
+++ b/drivers/tty/vt/vt_ioctl.c
@@ -1,6 +1,4 @@
/*
- * linux/drivers/char/vt_ioctl.c
- *
* Copyright (C) 1992 obz under the linux copyright
*
* Dynamic diacritical handling - aeb@cwi.nl - Dec 1993
@@ -698,10 +696,23 @@
break;
case KDGKBMODE:
- uival = ((kbd->kbdmode == VC_RAW) ? K_RAW :
- (kbd->kbdmode == VC_MEDIUMRAW) ? K_MEDIUMRAW :
- (kbd->kbdmode == VC_UNICODE) ? K_UNICODE :
- K_XLATE);
+ switch (kbd->kbdmode) {
+ case VC_RAW:
+ uival = K_RAW;
+ break;
+ case VC_MEDIUMRAW:
+ uival = K_MEDIUMRAW;
+ break;
+ case VC_UNICODE:
+ uival = K_UNICODE;
+ break;
+ case VC_OFF:
+ uival = K_OFF;
+ break;
+ default:
+ uival = K_XLATE;
+ break;
+ }
goto setint;
/* this could be folded into KDSKBMODE, but for compatibility
@@ -1499,7 +1510,6 @@
{
struct vc_data *vc = tty->driver_data;
struct console_font_op op; /* used in multiple places here */
- struct kbd_struct *kbd;
unsigned int console;
void __user *up = (void __user *)arg;
int perm;
@@ -1522,7 +1532,6 @@
if (current->signal->tty == tty || capable(CAP_SYS_TTY_CONFIG))
perm = 1;
- kbd = kbd_table + console;
switch (cmd) {
/*
* these need special handlers for incompatible data structures
diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
index 006489d..48f1781 100644
--- a/drivers/usb/Kconfig
+++ b/drivers/usb/Kconfig
@@ -65,8 +65,10 @@
default y if ARCH_CNS3XXX
default y if ARCH_VT8500
default y if PLAT_SPEAR
+ default y if PLAT_S5P
default y if ARCH_MSM
default y if MICROBLAZE
+ default y if SPARC_LEON
default PCI
# ARM SA1111 chips have a non-PCI based "OHCI-compatible" USB host interface.
@@ -116,6 +118,8 @@
source "drivers/usb/musb/Kconfig"
+source "drivers/usb/renesas_usbhs/Kconfig"
+
source "drivers/usb/class/Kconfig"
source "drivers/usb/storage/Kconfig"
diff --git a/drivers/usb/Makefile b/drivers/usb/Makefile
index 239f050..30ddf8d 100644
--- a/drivers/usb/Makefile
+++ b/drivers/usb/Makefile
@@ -22,6 +22,7 @@
obj-$(CONFIG_USB_HWA_HCD) += host/
obj-$(CONFIG_USB_ISP1760_HCD) += host/
obj-$(CONFIG_USB_IMX21_HCD) += host/
+obj-$(CONFIG_USB_FSL_MPH_DR_OF) += host/
obj-$(CONFIG_USB_C67X00_HCD) += c67x00/
@@ -45,3 +46,8 @@
obj-$(CONFIG_USB_ATM) += atm/
obj-$(CONFIG_USB_SPEEDTOUCH) += atm/
+
+obj-$(CONFIG_USB_MUSB_HDRC) += musb/
+obj-$(CONFIG_USB_RENESAS_USBHS) += renesas_usbhs/
+obj-$(CONFIG_USB_OTG_UTILS) += otg/
+obj-$(CONFIG_USB_GADGET) += gadget/
diff --git a/drivers/usb/class/cdc-acm.c b/drivers/usb/class/cdc-acm.c
index e057e53..395a347 100644
--- a/drivers/usb/class/cdc-acm.c
+++ b/drivers/usb/class/cdc-acm.c
@@ -7,35 +7,12 @@
* Copyright (c) 2000 Vojtech Pavlik <vojtech@suse.cz>
* Copyright (c) 2004 Oliver Neukum <oliver@neukum.name>
* Copyright (c) 2005 David Kubicek <dave@awk.cz>
+ * Copyright (c) 2011 Johan Hovold <jhovold@gmail.com>
*
* USB Abstract Control Model driver for USB modems and ISDN adapters
*
* Sponsored by SuSE
*
- * ChangeLog:
- * v0.9 - thorough cleaning, URBification, almost a rewrite
- * v0.10 - some more cleanups
- * v0.11 - fixed flow control, read error doesn't stop reads
- * v0.12 - added TIOCM ioctls, added break handling, made struct acm
- * kmalloced
- * v0.13 - added termios, added hangup
- * v0.14 - sized down struct acm
- * v0.15 - fixed flow control again - characters could be lost
- * v0.16 - added code for modems with swapped data and control interfaces
- * v0.17 - added new style probing
- * v0.18 - fixed new style probing for devices with more configurations
- * v0.19 - fixed CLOCAL handling (thanks to Richard Shih-Ping Chan)
- * v0.20 - switched to probing on interface (rather than device) class
- * v0.21 - revert to probing on device for devices with multiple configs
- * v0.22 - probe only the control interface. if usbcore doesn't choose the
- * config we want, sysadmin changes bConfigurationValue in sysfs.
- * v0.23 - use softirq for rx processing, as needed by tty layer
- * v0.24 - change probe method to evaluate CDC union descriptor
- * v0.25 - downstream tasks paralelized to maximize throughput
- * v0.26 - multiple write urbs, writesize increased
- */
-
-/*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
@@ -74,13 +51,7 @@
#include "cdc-acm.h"
-#define ACM_CLOSE_TIMEOUT 15 /* seconds to let writes drain */
-
-/*
- * Version Information
- */
-#define DRIVER_VERSION "v0.26"
-#define DRIVER_AUTHOR "Armin Fuerst, Pavel Machek, Johannes Erdfelt, Vojtech Pavlik, David Kubicek"
+#define DRIVER_AUTHOR "Armin Fuerst, Pavel Machek, Johannes Erdfelt, Vojtech Pavlik, David Kubicek, Johan Hovold"
#define DRIVER_DESC "USB Abstract Control Model driver for USB modems and ISDN adapters"
static struct usb_driver acm_driver;
@@ -94,12 +65,6 @@
static const struct tty_port_operations acm_port_ops = {
};
-#ifdef VERBOSE_DEBUG
-#define verbose 1
-#else
-#define verbose 0
-#endif
-
/*
* Functions for ACM control messages.
*/
@@ -111,8 +76,9 @@
request, USB_RT_ACM, value,
acm->control->altsetting[0].desc.bInterfaceNumber,
buf, len, 5000);
- dbg("acm_control_msg: rq: 0x%02x val: %#x len: %#x result: %d",
- request, value, len, retval);
+ dev_dbg(&acm->control->dev,
+ "%s - rq 0x%02x, val %#x, len %#x, result %d\n",
+ __func__, request, value, len, retval);
return retval < 0 ? retval : 0;
}
@@ -192,7 +158,9 @@
rc = usb_submit_urb(wb->urb, GFP_ATOMIC);
if (rc < 0) {
- dbg("usb_submit_urb(write bulk) failed: %d", rc);
+ dev_err(&acm->data->dev,
+ "%s - usb_submit_urb(write bulk) failed: %d\n",
+ __func__, rc);
acm_write_done(acm, wb);
}
return rc;
@@ -211,7 +179,8 @@
return -ENODEV;
}
- dbg("%s susp_count: %d", __func__, acm->susp_count);
+ dev_vdbg(&acm->data->dev, "%s - susp_count %d\n", __func__,
+ acm->susp_count);
usb_autopm_get_interface_async(acm->control);
if (acm->susp_count) {
if (!acm->delayed_wb)
@@ -287,10 +256,14 @@
case -ENOENT:
case -ESHUTDOWN:
/* this urb is terminated, clean up */
- dbg("%s - urb shutting down with status: %d", __func__, status);
+ dev_dbg(&acm->control->dev,
+ "%s - urb shutting down with status: %d\n",
+ __func__, status);
return;
default:
- dbg("%s - nonzero urb status received: %d", __func__, status);
+ dev_dbg(&acm->control->dev,
+ "%s - nonzero urb status received: %d\n",
+ __func__, status);
goto exit;
}
@@ -302,8 +275,8 @@
data = (unsigned char *)(dr + 1);
switch (dr->bNotificationType) {
case USB_CDC_NOTIFY_NETWORK_CONNECTION:
- dbg("%s network", dr->wValue ?
- "connected to" : "disconnected from");
+ dev_dbg(&acm->control->dev, "%s - network connection: %d\n",
+ __func__, dr->wValue);
break;
case USB_CDC_NOTIFY_SERIAL_STATE:
@@ -313,7 +286,8 @@
if (tty) {
if (!acm->clocal &&
(acm->ctrlin & ~newctrl & ACM_CTRL_DCD)) {
- dbg("calling hangup");
+ dev_dbg(&acm->control->dev,
+ "%s - calling hangup\n", __func__);
tty_hangup(tty);
}
tty_kref_put(tty);
@@ -321,7 +295,10 @@
acm->ctrlin = newctrl;
- dbg("input control lines: dcd%c dsr%c break%c ring%c framing%c parity%c overrun%c",
+ dev_dbg(&acm->control->dev,
+ "%s - input control lines: dcd%c dsr%c break%c "
+ "ring%c framing%c parity%c overrun%c\n",
+ __func__,
acm->ctrlin & ACM_CTRL_DCD ? '+' : '-',
acm->ctrlin & ACM_CTRL_DSR ? '+' : '-',
acm->ctrlin & ACM_CTRL_BRK ? '+' : '-',
@@ -332,7 +309,10 @@
break;
default:
- dbg("unknown notification %d received: index %d len %d data0 %d data1 %d",
+ dev_dbg(&acm->control->dev,
+ "%s - unknown notification %d received: index %d "
+ "len %d data0 %d data1 %d\n",
+ __func__,
dr->bNotificationType, dr->wIndex,
dr->wLength, data[0], data[1]);
break;
@@ -340,166 +320,96 @@
exit:
retval = usb_submit_urb(urb, GFP_ATOMIC);
if (retval)
- dev_err(&urb->dev->dev, "%s - usb_submit_urb failed with "
- "result %d", __func__, retval);
+ dev_err(&acm->control->dev, "%s - usb_submit_urb failed: %d\n",
+ __func__, retval);
}
-/* data interface returns incoming bytes, or we got unthrottled */
-static void acm_read_bulk(struct urb *urb)
+static int acm_submit_read_urb(struct acm *acm, int index, gfp_t mem_flags)
{
- struct acm_rb *buf;
- struct acm_ru *rcv = urb->context;
- struct acm *acm = rcv->instance;
- int status = urb->status;
+ int res;
- dbg("Entering acm_read_bulk with status %d", status);
+ if (!test_and_clear_bit(index, &acm->read_urbs_free))
+ return 0;
- if (!ACM_READY(acm)) {
- dev_dbg(&acm->data->dev, "Aborting, acm not ready");
+ dev_vdbg(&acm->data->dev, "%s - urb %d\n", __func__, index);
+
+ res = usb_submit_urb(acm->read_urbs[index], mem_flags);
+ if (res) {
+ if (res != -EPERM) {
+ dev_err(&acm->data->dev,
+ "%s - usb_submit_urb failed: %d\n",
+ __func__, res);
+ }
+ set_bit(index, &acm->read_urbs_free);
+ return res;
+ }
+
+ return 0;
+}
+
+static int acm_submit_read_urbs(struct acm *acm, gfp_t mem_flags)
+{
+ int res;
+ int i;
+
+ for (i = 0; i < acm->rx_buflimit; ++i) {
+ res = acm_submit_read_urb(acm, i, mem_flags);
+ if (res)
+ return res;
+ }
+
+ return 0;
+}
+
+static void acm_process_read_urb(struct acm *acm, struct urb *urb)
+{
+ struct tty_struct *tty;
+
+ if (!urb->actual_length)
+ return;
+
+ tty = tty_port_tty_get(&acm->port);
+ if (!tty)
+ return;
+
+ tty_insert_flip_string(tty, urb->transfer_buffer, urb->actual_length);
+ tty_flip_buffer_push(tty);
+
+ tty_kref_put(tty);
+}
+
+static void acm_read_bulk_callback(struct urb *urb)
+{
+ struct acm_rb *rb = urb->context;
+ struct acm *acm = rb->instance;
+ unsigned long flags;
+
+ dev_vdbg(&acm->data->dev, "%s - urb %d, len %d\n", __func__,
+ rb->index, urb->actual_length);
+ set_bit(rb->index, &acm->read_urbs_free);
+
+ if (!acm->dev) {
+ dev_dbg(&acm->data->dev, "%s - disconnected\n", __func__);
return;
}
usb_mark_last_busy(acm->dev);
- if (status)
- dev_dbg(&acm->data->dev, "bulk rx status %d\n", status);
+ if (urb->status) {
+ dev_dbg(&acm->data->dev, "%s - non-zero urb status: %d\n",
+ __func__, urb->status);
+ return;
+ }
+ acm_process_read_urb(acm, urb);
- buf = rcv->buffer;
- buf->size = urb->actual_length;
-
- if (likely(status == 0)) {
- spin_lock(&acm->read_lock);
- acm->processing++;
- list_add_tail(&rcv->list, &acm->spare_read_urbs);
- list_add_tail(&buf->list, &acm->filled_read_bufs);
- spin_unlock(&acm->read_lock);
+ /* throttle device if requested by tty */
+ spin_lock_irqsave(&acm->read_lock, flags);
+ acm->throttled = acm->throttle_req;
+ if (!acm->throttled && !acm->susp_count) {
+ spin_unlock_irqrestore(&acm->read_lock, flags);
+ acm_submit_read_urb(acm, rb->index, GFP_ATOMIC);
} else {
- /* we drop the buffer due to an error */
- spin_lock(&acm->read_lock);
- list_add_tail(&rcv->list, &acm->spare_read_urbs);
- list_add(&buf->list, &acm->spare_read_bufs);
- spin_unlock(&acm->read_lock);
- /* nevertheless the tasklet must be kicked unconditionally
- so the queue cannot dry up */
- }
- if (likely(!acm->susp_count))
- tasklet_schedule(&acm->urb_task);
-}
-
-static void acm_rx_tasklet(unsigned long _acm)
-{
- struct acm *acm = (void *)_acm;
- struct acm_rb *buf;
- struct tty_struct *tty;
- struct acm_ru *rcv;
- unsigned long flags;
- unsigned char throttled;
-
- dbg("Entering acm_rx_tasklet");
-
- if (!ACM_READY(acm)) {
- dbg("acm_rx_tasklet: ACM not ready");
- return;
- }
-
- spin_lock_irqsave(&acm->throttle_lock, flags);
- throttled = acm->throttle;
- spin_unlock_irqrestore(&acm->throttle_lock, flags);
- if (throttled) {
- dbg("acm_rx_tasklet: throttled");
- return;
- }
-
- tty = tty_port_tty_get(&acm->port);
-
-next_buffer:
- spin_lock_irqsave(&acm->read_lock, flags);
- if (list_empty(&acm->filled_read_bufs)) {
spin_unlock_irqrestore(&acm->read_lock, flags);
- goto urbs;
}
- buf = list_entry(acm->filled_read_bufs.next,
- struct acm_rb, list);
- list_del(&buf->list);
- spin_unlock_irqrestore(&acm->read_lock, flags);
-
- dbg("acm_rx_tasklet: procesing buf 0x%p, size = %d", buf, buf->size);
-
- if (tty) {
- spin_lock_irqsave(&acm->throttle_lock, flags);
- throttled = acm->throttle;
- spin_unlock_irqrestore(&acm->throttle_lock, flags);
- if (!throttled) {
- tty_insert_flip_string(tty, buf->base, buf->size);
- tty_flip_buffer_push(tty);
- } else {
- tty_kref_put(tty);
- dbg("Throttling noticed");
- spin_lock_irqsave(&acm->read_lock, flags);
- list_add(&buf->list, &acm->filled_read_bufs);
- spin_unlock_irqrestore(&acm->read_lock, flags);
- return;
- }
- }
-
- spin_lock_irqsave(&acm->read_lock, flags);
- list_add(&buf->list, &acm->spare_read_bufs);
- spin_unlock_irqrestore(&acm->read_lock, flags);
- goto next_buffer;
-
-urbs:
- tty_kref_put(tty);
-
- while (!list_empty(&acm->spare_read_bufs)) {
- spin_lock_irqsave(&acm->read_lock, flags);
- if (list_empty(&acm->spare_read_urbs)) {
- acm->processing = 0;
- spin_unlock_irqrestore(&acm->read_lock, flags);
- return;
- }
- rcv = list_entry(acm->spare_read_urbs.next,
- struct acm_ru, list);
- list_del(&rcv->list);
- spin_unlock_irqrestore(&acm->read_lock, flags);
-
- buf = list_entry(acm->spare_read_bufs.next,
- struct acm_rb, list);
- list_del(&buf->list);
-
- rcv->buffer = buf;
-
- if (acm->is_int_ep)
- usb_fill_int_urb(rcv->urb, acm->dev,
- acm->rx_endpoint,
- buf->base,
- acm->readsize,
- acm_read_bulk, rcv, acm->bInterval);
- else
- usb_fill_bulk_urb(rcv->urb, acm->dev,
- acm->rx_endpoint,
- buf->base,
- acm->readsize,
- acm_read_bulk, rcv);
- rcv->urb->transfer_dma = buf->dma;
- rcv->urb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP;
-
- /* This shouldn't kill the driver as unsuccessful URBs are
- returned to the free-urbs-pool and resubmited ASAP */
- spin_lock_irqsave(&acm->read_lock, flags);
- if (acm->susp_count ||
- usb_submit_urb(rcv->urb, GFP_ATOMIC) < 0) {
- list_add(&buf->list, &acm->spare_read_bufs);
- list_add(&rcv->list, &acm->spare_read_urbs);
- acm->processing = 0;
- spin_unlock_irqrestore(&acm->read_lock, flags);
- return;
- } else {
- spin_unlock_irqrestore(&acm->read_lock, flags);
- dbg("acm_rx_tasklet: sending urb 0x%p, rcv 0x%p, buf 0x%p", rcv->urb, rcv, buf);
- }
- }
- spin_lock_irqsave(&acm->read_lock, flags);
- acm->processing = 0;
- spin_unlock_irqrestore(&acm->read_lock, flags);
}
/* data interface wrote those outgoing bytes */
@@ -509,9 +419,9 @@
struct acm *acm = wb->instance;
unsigned long flags;
- if (verbose || urb->status
- || (urb->actual_length != urb->transfer_buffer_length))
- dev_dbg(&acm->data->dev, "tx %d/%d bytes -- > %d\n",
+ if (urb->status || (urb->actual_length != urb->transfer_buffer_length))
+ dev_vdbg(&acm->data->dev, "%s - len %d/%d, status %d\n",
+ __func__,
urb->actual_length,
urb->transfer_buffer_length,
urb->status);
@@ -521,8 +431,6 @@
spin_unlock_irqrestore(&acm->write_lock, flags);
if (ACM_READY(acm))
schedule_work(&acm->work);
- else
- wake_up_interruptible(&acm->drain_wait);
}
static void acm_softint(struct work_struct *work)
@@ -530,7 +438,8 @@
struct acm *acm = container_of(work, struct acm, work);
struct tty_struct *tty;
- dev_vdbg(&acm->data->dev, "tx work\n");
+ dev_vdbg(&acm->data->dev, "%s\n", __func__);
+
if (!ACM_READY(acm))
return;
tty = tty_port_tty_get(&acm->port);
@@ -548,8 +457,6 @@
{
struct acm *acm;
int rv = -ENODEV;
- int i;
- dbg("Entering acm_tty_open.");
mutex_lock(&open_mutex);
@@ -559,6 +466,8 @@
else
rv = 0;
+ dev_dbg(&acm->control->dev, "%s\n", __func__);
+
set_bit(TTY_NO_WRITE_SPLIT, &tty->flags);
tty->driver_data = acm;
@@ -578,38 +487,28 @@
acm->ctrlurb->dev = acm->dev;
if (usb_submit_urb(acm->ctrlurb, GFP_KERNEL)) {
- dbg("usb_submit_urb(ctrl irq) failed");
+ dev_err(&acm->control->dev,
+ "%s - usb_submit_urb(ctrl irq) failed\n", __func__);
goto bail_out;
}
if (0 > acm_set_control(acm, acm->ctrlout = ACM_CTRL_DTR | ACM_CTRL_RTS) &&
(acm->ctrl_caps & USB_CDC_CAP_LINE))
- goto full_bailout;
+ goto bail_out;
usb_autopm_put_interface(acm->control);
- INIT_LIST_HEAD(&acm->spare_read_urbs);
- INIT_LIST_HEAD(&acm->spare_read_bufs);
- INIT_LIST_HEAD(&acm->filled_read_bufs);
-
- for (i = 0; i < acm->rx_buflimit; i++)
- list_add(&(acm->ru[i].list), &acm->spare_read_urbs);
- for (i = 0; i < acm->rx_buflimit; i++)
- list_add(&(acm->rb[i].list), &acm->spare_read_bufs);
-
- acm->throttle = 0;
+ if (acm_submit_read_urbs(acm, GFP_KERNEL))
+ goto bail_out;
set_bit(ASYNCB_INITIALIZED, &acm->port.flags);
rv = tty_port_block_til_ready(&acm->port, tty, filp);
- tasklet_schedule(&acm->urb_task);
mutex_unlock(&acm->mutex);
out:
mutex_unlock(&open_mutex);
return rv;
-full_bailout:
- usb_kill_urb(acm->ctrlurb);
bail_out:
acm->port.count--;
mutex_unlock(&acm->mutex);
@@ -622,26 +521,24 @@
static void acm_tty_unregister(struct acm *acm)
{
- int i, nr;
+ int i;
- nr = acm->rx_buflimit;
tty_unregister_device(acm_tty_driver, acm->minor);
usb_put_intf(acm->control);
acm_table[acm->minor] = NULL;
usb_free_urb(acm->ctrlurb);
for (i = 0; i < ACM_NW; i++)
usb_free_urb(acm->wb[i].urb);
- for (i = 0; i < nr; i++)
- usb_free_urb(acm->ru[i].urb);
+ for (i = 0; i < acm->rx_buflimit; i++)
+ usb_free_urb(acm->read_urbs[i]);
kfree(acm->country_codes);
kfree(acm);
}
-static int acm_tty_chars_in_buffer(struct tty_struct *tty);
-
static void acm_port_down(struct acm *acm)
{
- int i, nr = acm->rx_buflimit;
+ int i;
+
mutex_lock(&open_mutex);
if (acm->dev) {
usb_autopm_get_interface(acm->control);
@@ -649,10 +546,8 @@
usb_kill_urb(acm->ctrlurb);
for (i = 0; i < ACM_NW; i++)
usb_kill_urb(acm->wb[i].urb);
- tasklet_disable(&acm->urb_task);
- for (i = 0; i < nr; i++)
- usb_kill_urb(acm->ru[i].urb);
- tasklet_enable(&acm->urb_task);
+ for (i = 0; i < acm->rx_buflimit; i++)
+ usb_kill_urb(acm->read_urbs[i]);
acm->control->needs_remote_wakeup = 0;
usb_autopm_put_interface(acm->control);
}
@@ -698,13 +593,13 @@
int wbn;
struct acm_wb *wb;
- dbg("Entering acm_tty_write to write %d bytes,", count);
-
if (!ACM_READY(acm))
return -EINVAL;
if (!count)
return 0;
+ dev_vdbg(&acm->data->dev, "%s - count %d\n", __func__, count);
+
spin_lock_irqsave(&acm->write_lock, flags);
wbn = acm_wb_alloc(acm);
if (wbn < 0) {
@@ -714,7 +609,7 @@
wb = &acm->wb[wbn];
count = (count > acm->writesize) ? acm->writesize : count;
- dbg("Get %d bytes...", count);
+ dev_vdbg(&acm->data->dev, "%s - write %d\n", __func__, count);
memcpy(wb->buf, buf, count);
wb->len = count;
spin_unlock_irqrestore(&acm->write_lock, flags);
@@ -751,22 +646,31 @@
static void acm_tty_throttle(struct tty_struct *tty)
{
struct acm *acm = tty->driver_data;
+
if (!ACM_READY(acm))
return;
- spin_lock_bh(&acm->throttle_lock);
- acm->throttle = 1;
- spin_unlock_bh(&acm->throttle_lock);
+
+ spin_lock_irq(&acm->read_lock);
+ acm->throttle_req = 1;
+ spin_unlock_irq(&acm->read_lock);
}
static void acm_tty_unthrottle(struct tty_struct *tty)
{
struct acm *acm = tty->driver_data;
+ unsigned int was_throttled;
+
if (!ACM_READY(acm))
return;
- spin_lock_bh(&acm->throttle_lock);
- acm->throttle = 0;
- spin_unlock_bh(&acm->throttle_lock);
- tasklet_schedule(&acm->urb_task);
+
+ spin_lock_irq(&acm->read_lock);
+ was_throttled = acm->throttled;
+ acm->throttled = 0;
+ acm->throttle_req = 0;
+ spin_unlock_irq(&acm->read_lock);
+
+ if (was_throttled)
+ acm_submit_read_urbs(acm, GFP_KERNEL);
}
static int acm_tty_break_ctl(struct tty_struct *tty, int state)
@@ -777,7 +681,8 @@
return -EINVAL;
retval = acm_send_break(acm, state ? 0xffff : 0);
if (retval < 0)
- dbg("send break failed");
+ dev_dbg(&acm->control->dev, "%s - send break failed\n",
+ __func__);
return retval;
}
@@ -872,7 +777,9 @@
if (memcmp(&acm->line, &newline, sizeof newline)) {
memcpy(&acm->line, &newline, sizeof newline);
- dbg("set line: %d %d %d %d", le32_to_cpu(newline.dwDTERate),
+ dev_dbg(&acm->control->dev, "%s - set line: %d %d %d %d\n",
+ __func__,
+ le32_to_cpu(newline.dwDTERate),
newline.bCharFormat, newline.bParityType,
newline.bDataBits);
acm_set_line(acm, &acm->line);
@@ -897,11 +804,11 @@
static void acm_read_buffers_free(struct acm *acm)
{
struct usb_device *usb_dev = interface_to_usbdev(acm->control);
- int i, n = acm->rx_buflimit;
+ int i;
- for (i = 0; i < n; i++)
+ for (i = 0; i < acm->rx_buflimit; i++)
usb_free_coherent(usb_dev, acm->readsize,
- acm->rb[i].base, acm->rb[i].dma);
+ acm->read_buffers[i].base, acm->read_buffers[i].dma);
}
/* Little helper: write buffers allocate */
@@ -946,7 +853,7 @@
u8 ac_management_function = 0;
u8 call_management_function = 0;
int call_interface_num = -1;
- int data_interface_num;
+ int data_interface_num = -1;
unsigned long quirks;
int num_rx_buf;
int i;
@@ -1030,7 +937,11 @@
if (!union_header) {
if (call_interface_num > 0) {
dev_dbg(&intf->dev, "No union descriptor, using call management descriptor\n");
- data_interface = usb_ifnum_to_if(usb_dev, (data_interface_num = call_interface_num));
+ /* quirks for Droids MuIn LCD */
+ if (quirks & NO_DATA_INTERFACE)
+ data_interface = usb_ifnum_to_if(usb_dev, 0);
+ else
+ data_interface = usb_ifnum_to_if(usb_dev, (data_interface_num = call_interface_num));
control_interface = intf;
} else {
if (intf->cur_altsetting->desc.bNumEndpoints != 3) {
@@ -1133,7 +1044,7 @@
epwrite = t;
}
made_compressed_probe:
- dbg("interfaces are valid");
+ dev_dbg(&intf->dev, "interfaces are valid\n");
for (minor = 0; minor < ACM_TTY_MINORS && acm_table[minor]; minor++);
if (minor == ACM_TTY_MINORS) {
@@ -1143,7 +1054,7 @@
acm = kzalloc(sizeof(struct acm), GFP_KERNEL);
if (acm == NULL) {
- dev_dbg(&intf->dev, "out of memory (acm kzalloc)\n");
+ dev_err(&intf->dev, "out of memory (acm kzalloc)\n");
goto alloc_fail;
}
@@ -1162,11 +1073,7 @@
acm->ctrlsize = ctrlsize;
acm->readsize = readsize;
acm->rx_buflimit = num_rx_buf;
- acm->urb_task.func = acm_rx_tasklet;
- acm->urb_task.data = (unsigned long) acm;
INIT_WORK(&acm->work, acm_softint);
- init_waitqueue_head(&acm->drain_wait);
- spin_lock_init(&acm->throttle_lock);
spin_lock_init(&acm->write_lock);
spin_lock_init(&acm->read_lock);
mutex_init(&acm->mutex);
@@ -1179,53 +1086,69 @@
buf = usb_alloc_coherent(usb_dev, ctrlsize, GFP_KERNEL, &acm->ctrl_dma);
if (!buf) {
- dev_dbg(&intf->dev, "out of memory (ctrl buffer alloc)\n");
+ dev_err(&intf->dev, "out of memory (ctrl buffer alloc)\n");
goto alloc_fail2;
}
acm->ctrl_buffer = buf;
if (acm_write_buffers_alloc(acm) < 0) {
- dev_dbg(&intf->dev, "out of memory (write buffer alloc)\n");
+ dev_err(&intf->dev, "out of memory (write buffer alloc)\n");
goto alloc_fail4;
}
acm->ctrlurb = usb_alloc_urb(0, GFP_KERNEL);
if (!acm->ctrlurb) {
- dev_dbg(&intf->dev, "out of memory (ctrlurb kmalloc)\n");
+ dev_err(&intf->dev, "out of memory (ctrlurb kmalloc)\n");
goto alloc_fail5;
}
for (i = 0; i < num_rx_buf; i++) {
- struct acm_ru *rcv = &(acm->ru[i]);
+ struct acm_rb *rb = &(acm->read_buffers[i]);
+ struct urb *urb;
- rcv->urb = usb_alloc_urb(0, GFP_KERNEL);
- if (rcv->urb == NULL) {
- dev_dbg(&intf->dev,
+ rb->base = usb_alloc_coherent(acm->dev, readsize, GFP_KERNEL,
+ &rb->dma);
+ if (!rb->base) {
+ dev_err(&intf->dev, "out of memory "
+ "(read bufs usb_alloc_coherent)\n");
+ goto alloc_fail6;
+ }
+ rb->index = i;
+ rb->instance = acm;
+
+ urb = usb_alloc_urb(0, GFP_KERNEL);
+ if (!urb) {
+ dev_err(&intf->dev,
"out of memory (read urbs usb_alloc_urb)\n");
goto alloc_fail6;
}
-
- rcv->urb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP;
- rcv->instance = acm;
- }
- for (i = 0; i < num_rx_buf; i++) {
- struct acm_rb *rb = &(acm->rb[i]);
-
- rb->base = usb_alloc_coherent(acm->dev, readsize,
- GFP_KERNEL, &rb->dma);
- if (!rb->base) {
- dev_dbg(&intf->dev,
- "out of memory (read bufs usb_alloc_coherent)\n");
- goto alloc_fail7;
+ urb->transfer_flags |= URB_NO_TRANSFER_DMA_MAP;
+ urb->transfer_dma = rb->dma;
+ if (acm->is_int_ep) {
+ usb_fill_int_urb(urb, acm->dev,
+ acm->rx_endpoint,
+ rb->base,
+ acm->readsize,
+ acm_read_bulk_callback, rb,
+ acm->bInterval);
+ } else {
+ usb_fill_bulk_urb(urb, acm->dev,
+ acm->rx_endpoint,
+ rb->base,
+ acm->readsize,
+ acm_read_bulk_callback, rb);
}
+
+ acm->read_urbs[i] = urb;
+ __set_bit(i, &acm->read_urbs_free);
}
for (i = 0; i < ACM_NW; i++) {
struct acm_wb *snd = &(acm->wb[i]);
snd->urb = usb_alloc_urb(0, GFP_KERNEL);
if (snd->urb == NULL) {
- dev_dbg(&intf->dev,
- "out of memory (write urbs usb_alloc_urb)");
- goto alloc_fail8;
+ dev_err(&intf->dev,
+ "out of memory (write urbs usb_alloc_urb)\n");
+ goto alloc_fail7;
}
if (usb_endpoint_xfer_int(epwrite))
@@ -1244,7 +1167,7 @@
i = device_create_file(&intf->dev, &dev_attr_bmCapabilities);
if (i < 0)
- goto alloc_fail8;
+ goto alloc_fail7;
if (cfd) { /* export the country data */
acm->country_codes = kmalloc(cfd->bLength - 4, GFP_KERNEL);
@@ -1296,14 +1219,13 @@
acm_table[minor] = acm;
return 0;
-alloc_fail8:
+alloc_fail7:
for (i = 0; i < ACM_NW; i++)
usb_free_urb(acm->wb[i].urb);
-alloc_fail7:
- acm_read_buffers_free(acm);
alloc_fail6:
for (i = 0; i < num_rx_buf; i++)
- usb_free_urb(acm->ru[i].urb);
+ usb_free_urb(acm->read_urbs[i]);
+ acm_read_buffers_free(acm);
usb_free_urb(acm->ctrlurb);
alloc_fail5:
acm_write_buffers_free(acm);
@@ -1318,17 +1240,14 @@
static void stop_data_traffic(struct acm *acm)
{
int i;
- dbg("Entering stop_data_traffic");
- tasklet_disable(&acm->urb_task);
+ dev_dbg(&acm->control->dev, "%s\n", __func__);
usb_kill_urb(acm->ctrlurb);
for (i = 0; i < ACM_NW; i++)
usb_kill_urb(acm->wb[i].urb);
for (i = 0; i < acm->rx_buflimit; i++)
- usb_kill_urb(acm->ru[i].urb);
-
- tasklet_enable(&acm->urb_task);
+ usb_kill_urb(acm->read_urbs[i]);
cancel_work_sync(&acm->work);
}
@@ -1389,11 +1308,9 @@
if (message.event & PM_EVENT_AUTO) {
int b;
- spin_lock_irq(&acm->read_lock);
- spin_lock(&acm->write_lock);
- b = acm->processing + acm->transmitting;
- spin_unlock(&acm->write_lock);
- spin_unlock_irq(&acm->read_lock);
+ spin_lock_irq(&acm->write_lock);
+ b = acm->transmitting;
+ spin_unlock_irq(&acm->write_lock);
if (b)
return -EBUSY;
}
@@ -1455,7 +1372,7 @@
if (rv < 0)
goto err_out;
- tasklet_schedule(&acm->urb_task);
+ rv = acm_submit_read_urbs(acm, GFP_NOIO);
}
err_out:
@@ -1622,6 +1539,11 @@
.driver_info = NOT_A_MODEM,
},
+ /* Support for Droids MuIn LCD */
+ { USB_DEVICE(0x04d8, 0x000b),
+ .driver_info = NO_DATA_INTERFACE,
+ },
+
/* control interfaces without any protocol set */
{ USB_INTERFACE_INFO(USB_CLASS_COMM, USB_CDC_SUBCLASS_ACM,
USB_CDC_PROTO_NONE) },
@@ -1716,8 +1638,7 @@
return retval;
}
- printk(KERN_INFO KBUILD_MODNAME ": " DRIVER_VERSION ":"
- DRIVER_DESC "\n");
+ printk(KERN_INFO KBUILD_MODNAME ": " DRIVER_DESC "\n");
return 0;
}
diff --git a/drivers/usb/class/cdc-acm.h b/drivers/usb/class/cdc-acm.h
index b4ea54d..ca7937f 100644
--- a/drivers/usb/class/cdc-acm.h
+++ b/drivers/usb/class/cdc-acm.h
@@ -72,16 +72,10 @@
};
struct acm_rb {
- struct list_head list;
int size;
unsigned char *base;
dma_addr_t dma;
-};
-
-struct acm_ru {
- struct list_head list;
- struct acm_rb *buffer;
- struct urb *urb;
+ int index;
struct acm *instance;
};
@@ -97,35 +91,30 @@
unsigned int country_code_size; /* size of this buffer */
unsigned int country_rel_date; /* release date of version */
struct acm_wb wb[ACM_NW];
- struct acm_ru ru[ACM_NR];
- struct acm_rb rb[ACM_NR];
+ unsigned long read_urbs_free;
+ struct urb *read_urbs[ACM_NR];
+ struct acm_rb read_buffers[ACM_NR];
int rx_buflimit;
int rx_endpoint;
spinlock_t read_lock;
- struct list_head spare_read_urbs;
- struct list_head spare_read_bufs;
- struct list_head filled_read_bufs;
int write_used; /* number of non-empty write buffers */
- int processing;
int transmitting;
spinlock_t write_lock;
struct mutex mutex;
struct usb_cdc_line_coding line; /* bits, stop, parity */
struct work_struct work; /* work queue entry for line discipline waking up */
- wait_queue_head_t drain_wait; /* close processing */
- struct tasklet_struct urb_task; /* rx processing */
- spinlock_t throttle_lock; /* synchronize throtteling and read callback */
unsigned int ctrlin; /* input control lines (DCD, DSR, RI, break, overruns) */
unsigned int ctrlout; /* output control lines (DTR, RTS) */
unsigned int writesize; /* max packet size for the output bulk endpoint */
unsigned int readsize,ctrlsize; /* buffer sizes for freeing */
unsigned int minor; /* acm minor number */
- unsigned char throttle; /* throttled by tty layer */
unsigned char clocal; /* termios CLOCAL */
unsigned int ctrl_caps; /* control capabilities from the class specific header */
unsigned int susp_count; /* number of suspended interfaces */
unsigned int combined_interfaces:1; /* control and data collapsed */
unsigned int is_int_ep:1; /* interrupt endpoints contrary to spec used */
+ unsigned int throttled:1; /* actually throttled */
+ unsigned int throttle_req:1; /* throttle requested */
u8 bInterval;
struct acm_wb *delayed_wb; /* write queued for a device about to be woken */
};
@@ -137,3 +126,4 @@
#define SINGLE_RX_URB 2
#define NO_CAP_LINE 4
#define NOT_A_MODEM 8
+#define NO_DATA_INTERFACE 16
diff --git a/drivers/usb/class/cdc-wdm.c b/drivers/usb/class/cdc-wdm.c
index a97c018..2b9ff51 100644
--- a/drivers/usb/class/cdc-wdm.c
+++ b/drivers/usb/class/cdc-wdm.c
@@ -542,6 +542,8 @@
mutex_lock(&desc->lock);
if (!desc->count++) {
+ desc->werr = 0;
+ desc->rerr = 0;
rv = usb_submit_urb(desc->validity, GFP_KERNEL);
if (rv < 0) {
desc->count--;
@@ -853,6 +855,18 @@
struct wdm_device *desc = usb_get_intfdata(intf);
mutex_lock(&desc->lock);
+ kill_urbs(desc);
+
+ /*
+ * we notify everybody using poll of
+ * an exceptional situation
+ * must be done before recovery lest a spontaneous
+ * message from the device is lost
+ */
+ spin_lock_irq(&desc->iuspin);
+ desc->rerr = -EINTR;
+ spin_unlock_irq(&desc->iuspin);
+ wake_up_all(&desc->wait);
return 0;
}
diff --git a/drivers/usb/core/config.c b/drivers/usb/core/config.c
index 83126b0..c962608 100644
--- a/drivers/usb/core/config.c
+++ b/drivers/usb/core/config.c
@@ -129,7 +129,7 @@
max_tx = ep->desc.wMaxPacketSize * (desc->bMaxBurst + 1);
else
max_tx = 999999;
- if (desc->wBytesPerInterval > max_tx) {
+ if (le16_to_cpu(desc->wBytesPerInterval) > max_tx) {
dev_warn(ddev, "%s endpoint with wBytesPerInterval of %d in "
"config %d interface %d altsetting %d ep %d: "
"setting to %d\n",
diff --git a/drivers/usb/core/devices.c b/drivers/usb/core/devices.c
index 96fdfb8..0149c09 100644
--- a/drivers/usb/core/devices.c
+++ b/drivers/usb/core/devices.c
@@ -64,49 +64,49 @@
/* Define ALLOW_SERIAL_NUMBER if you want to see the serial number of devices */
#define ALLOW_SERIAL_NUMBER
-static const char *format_topo =
+static const char format_topo[] =
/* T: Bus=dd Lev=dd Prnt=dd Port=dd Cnt=dd Dev#=ddd Spd=dddd MxCh=dd */
"\nT: Bus=%2.2d Lev=%2.2d Prnt=%2.2d Port=%2.2d Cnt=%2.2d Dev#=%3d Spd=%-4s MxCh=%2d\n";
-static const char *format_string_manufacturer =
+static const char format_string_manufacturer[] =
/* S: Manufacturer=xxxx */
"S: Manufacturer=%.100s\n";
-static const char *format_string_product =
+static const char format_string_product[] =
/* S: Product=xxxx */
"S: Product=%.100s\n";
#ifdef ALLOW_SERIAL_NUMBER
-static const char *format_string_serialnumber =
+static const char format_string_serialnumber[] =
/* S: SerialNumber=xxxx */
"S: SerialNumber=%.100s\n";
#endif
-static const char *format_bandwidth =
+static const char format_bandwidth[] =
/* B: Alloc=ddd/ddd us (xx%), #Int=ddd, #Iso=ddd */
"B: Alloc=%3d/%3d us (%2d%%), #Int=%3d, #Iso=%3d\n";
-static const char *format_device1 =
+static const char format_device1[] =
/* D: Ver=xx.xx Cls=xx(sssss) Sub=xx Prot=xx MxPS=dd #Cfgs=dd */
"D: Ver=%2x.%02x Cls=%02x(%-5s) Sub=%02x Prot=%02x MxPS=%2d #Cfgs=%3d\n";
-static const char *format_device2 =
+static const char format_device2[] =
/* P: Vendor=xxxx ProdID=xxxx Rev=xx.xx */
"P: Vendor=%04x ProdID=%04x Rev=%2x.%02x\n";
-static const char *format_config =
+static const char format_config[] =
/* C: #Ifs=dd Cfg#=dd Atr=xx MPwr=dddmA */
"C:%c #Ifs=%2d Cfg#=%2d Atr=%02x MxPwr=%3dmA\n";
-static const char *format_iad =
+static const char format_iad[] =
/* A: FirstIf#=dd IfCount=dd Cls=xx(sssss) Sub=xx Prot=xx */
"A: FirstIf#=%2d IfCount=%2d Cls=%02x(%-5s) Sub=%02x Prot=%02x\n";
-static const char *format_iface =
+static const char format_iface[] =
/* I: If#=dd Alt=dd #EPs=dd Cls=xx(sssss) Sub=xx Prot=xx Driver=xxxx*/
"I:%c If#=%2d Alt=%2d #EPs=%2d Cls=%02x(%-5s) Sub=%02x Prot=%02x Driver=%s\n";
-static const char *format_endpt =
+static const char format_endpt[] =
/* E: Ad=xx(s) Atr=xx(ssss) MxPS=dddd Ivl=D?s */
"E: Ad=%02x(%c) Atr=%02x(%-4s) MxPS=%4d Ivl=%d%cs\n";
diff --git a/drivers/usb/core/file.c b/drivers/usb/core/file.c
index cf6a542..99458c8 100644
--- a/drivers/usb/core/file.c
+++ b/drivers/usb/core/file.c
@@ -236,13 +236,6 @@
void usb_deregister_dev(struct usb_interface *intf,
struct usb_class_driver *class_driver)
{
- int minor_base = class_driver->minor_base;
- char name[20];
-
-#ifdef CONFIG_USB_DYNAMIC_MINORS
- minor_base = 0;
-#endif
-
if (intf->minor == -1)
return;
@@ -252,7 +245,6 @@
usb_minors[intf->minor] = NULL;
up_write(&minor_rwsem);
- snprintf(name, sizeof(name), class_driver->name, intf->minor - minor_base);
device_destroy(usb_class->class, MKDEV(USB_MAJOR, intf->minor));
intf->usb_dev = NULL;
intf->minor = -1;
diff --git a/drivers/usb/core/hcd.c b/drivers/usb/core/hcd.c
index 77a7fae..ace9f844 100644
--- a/drivers/usb/core/hcd.c
+++ b/drivers/usb/core/hcd.c
@@ -986,7 +986,7 @@
spin_unlock_irq (&hcd_root_hub_lock);
/* Did the HC die before the root hub was registered? */
- if (HCD_DEAD(hcd) || hcd->state == HC_STATE_HALT)
+ if (HCD_DEAD(hcd))
usb_hc_died (hcd); /* This time clean up */
}
@@ -2128,9 +2128,6 @@
set_bit(HCD_FLAG_SAW_IRQ, &hcd->flags);
if (hcd->shared_hcd)
set_bit(HCD_FLAG_SAW_IRQ, &hcd->shared_hcd->flags);
-
- if (unlikely(hcd->state == HC_STATE_HALT))
- usb_hc_died(hcd);
rc = IRQ_HANDLED;
}
@@ -2407,6 +2404,7 @@
rhdev->speed = USB_SPEED_SUPER;
break;
default:
+ retval = -EINVAL;
goto err_set_rh_speed;
}
diff --git a/drivers/usb/core/hub.c b/drivers/usb/core/hub.c
index 93720bdc..79a58c3 100644
--- a/drivers/usb/core/hub.c
+++ b/drivers/usb/core/hub.c
@@ -379,15 +379,6 @@
*status = le16_to_cpu(hub->status->port.wPortStatus);
*change = le16_to_cpu(hub->status->port.wPortChange);
- if ((hub->hdev->parent != NULL) &&
- hub_is_superspeed(hub->hdev)) {
- /* Translate the USB 3 port status */
- u16 tmp = *status & USB_SS_PORT_STAT_MASK;
- if (*status & USB_SS_PORT_STAT_POWER)
- tmp |= USB_PORT_STAT_POWER;
- *status = tmp;
- }
-
ret = 0;
}
mutex_unlock(&hub->status_mutex);
@@ -2160,11 +2151,76 @@
return status;
}
+/* Warm reset a USB3 protocol port */
+static int hub_port_warm_reset(struct usb_hub *hub, int port)
+{
+ int ret;
+ u16 portstatus, portchange;
+
+ if (!hub_is_superspeed(hub->hdev)) {
+ dev_err(hub->intfdev, "only USB3 hub support warm reset\n");
+ return -EINVAL;
+ }
+
+ /* Warm reset the port */
+ ret = set_port_feature(hub->hdev,
+ port, USB_PORT_FEAT_BH_PORT_RESET);
+ if (ret) {
+ dev_err(hub->intfdev, "cannot warm reset port %d\n", port);
+ return ret;
+ }
+
+ msleep(20);
+ ret = hub_port_status(hub, port, &portstatus, &portchange);
+
+ if (portchange & USB_PORT_STAT_C_RESET)
+ clear_port_feature(hub->hdev, port, USB_PORT_FEAT_C_RESET);
+
+ if (portchange & USB_PORT_STAT_C_BH_RESET)
+ clear_port_feature(hub->hdev, port,
+ USB_PORT_FEAT_C_BH_PORT_RESET);
+
+ if (portchange & USB_PORT_STAT_C_LINK_STATE)
+ clear_port_feature(hub->hdev, port,
+ USB_PORT_FEAT_C_PORT_LINK_STATE);
+
+ return ret;
+}
+
+/* Check if a port is power on */
+static int port_is_power_on(struct usb_hub *hub, unsigned portstatus)
+{
+ int ret = 0;
+
+ if (hub_is_superspeed(hub->hdev)) {
+ if (portstatus & USB_SS_PORT_STAT_POWER)
+ ret = 1;
+ } else {
+ if (portstatus & USB_PORT_STAT_POWER)
+ ret = 1;
+ }
+
+ return ret;
+}
+
#ifdef CONFIG_PM
-#define MASK_BITS (USB_PORT_STAT_POWER | USB_PORT_STAT_CONNECTION | \
- USB_PORT_STAT_SUSPEND)
-#define WANT_BITS (USB_PORT_STAT_POWER | USB_PORT_STAT_CONNECTION)
+/* Check if a port is suspended(USB2.0 port) or in U3 state(USB3.0 port) */
+static int port_is_suspended(struct usb_hub *hub, unsigned portstatus)
+{
+ int ret = 0;
+
+ if (hub_is_superspeed(hub->hdev)) {
+ if ((portstatus & USB_PORT_STAT_LINK_STATE)
+ == USB_SS_PORT_LS_U3)
+ ret = 1;
+ } else {
+ if (portstatus & USB_PORT_STAT_SUSPEND)
+ ret = 1;
+ }
+
+ return ret;
+}
/* Determine whether the device on a port is ready for a normal resume,
* is ready for a reset-resume, or should be disconnected.
@@ -2174,7 +2230,9 @@
int status, unsigned portchange, unsigned portstatus)
{
/* Is the device still present? */
- if (status || (portstatus & MASK_BITS) != WANT_BITS) {
+ if (status || port_is_suspended(hub, portstatus) ||
+ !port_is_power_on(hub, portstatus) ||
+ !(portstatus & USB_PORT_STAT_CONNECTION)) {
if (status >= 0)
status = -ENODEV;
}
@@ -2285,14 +2343,10 @@
}
/* see 7.1.7.6 */
- /* Clear PORT_POWER if it's a USB3.0 device connected to USB 3.0
- * external hub.
- * FIXME: this is a temporary workaround to make the system able
- * to suspend/resume.
- */
- if ((hub->hdev->parent != NULL) && hub_is_superspeed(hub->hdev))
- status = clear_port_feature(hub->hdev, port1,
- USB_PORT_FEAT_POWER);
+ if (hub_is_superspeed(hub->hdev))
+ status = set_port_feature(hub->hdev,
+ port1 | (USB_SS_PORT_LS_U3 << 3),
+ USB_PORT_FEAT_LINK_STATE);
else
status = set_port_feature(hub->hdev, port1,
USB_PORT_FEAT_SUSPEND);
@@ -2439,7 +2493,7 @@
/* Skip the initial Clear-Suspend step for a remote wakeup */
status = hub_port_status(hub, port1, &portstatus, &portchange);
- if (status == 0 && !(portstatus & USB_PORT_STAT_SUSPEND))
+ if (status == 0 && !port_is_suspended(hub, portstatus))
goto SuspendCleared;
// dev_dbg(hub->intfdev, "resume port %d\n", port1);
@@ -2447,8 +2501,13 @@
set_bit(port1, hub->busy_bits);
/* see 7.1.7.7; affects power usage, but not budgeting */
- status = clear_port_feature(hub->hdev,
- port1, USB_PORT_FEAT_SUSPEND);
+ if (hub_is_superspeed(hub->hdev))
+ status = set_port_feature(hub->hdev,
+ port1 | (USB_SS_PORT_LS_U0 << 3),
+ USB_PORT_FEAT_LINK_STATE);
+ else
+ status = clear_port_feature(hub->hdev,
+ port1, USB_PORT_FEAT_SUSPEND);
if (status) {
dev_dbg(hub->intfdev, "can't resume port %d, status %d\n",
port1, status);
@@ -2470,9 +2529,15 @@
SuspendCleared:
if (status == 0) {
- if (portchange & USB_PORT_STAT_C_SUSPEND)
- clear_port_feature(hub->hdev, port1,
- USB_PORT_FEAT_C_SUSPEND);
+ if (hub_is_superspeed(hub->hdev)) {
+ if (portchange & USB_PORT_STAT_C_LINK_STATE)
+ clear_port_feature(hub->hdev, port1,
+ USB_PORT_FEAT_C_PORT_LINK_STATE);
+ } else {
+ if (portchange & USB_PORT_STAT_C_SUSPEND)
+ clear_port_feature(hub->hdev, port1,
+ USB_PORT_FEAT_C_SUSPEND);
+ }
}
clear_bit(port1, hub->busy_bits);
@@ -3147,7 +3212,7 @@
/* maybe switch power back on (e.g. root hub was reset) */
if ((wHubCharacteristics & HUB_CHAR_LPSM) < 2
- && !(portstatus & USB_PORT_STAT_POWER))
+ && !port_is_power_on(hub, portstatus))
set_port_feature(hdev, port1, USB_PORT_FEAT_POWER);
if (portstatus & USB_PORT_STAT_ENABLE)
@@ -3490,6 +3555,16 @@
USB_PORT_FEAT_C_PORT_CONFIG_ERROR);
}
+ /* Warm reset a USB3 protocol port if it's in
+ * SS.Inactive state.
+ */
+ if (hub_is_superspeed(hub->hdev) &&
+ (portstatus & USB_PORT_STAT_LINK_STATE)
+ == USB_SS_PORT_LS_SS_INACTIVE) {
+ dev_dbg(hub_dev, "warm reset port %d\n", i);
+ hub_port_warm_reset(hub, i);
+ }
+
if (connect_change)
hub_port_connect_change(hub, i,
portstatus, portchange);
diff --git a/drivers/usb/core/sysfs.c b/drivers/usb/core/sysfs.c
index 6781c36..cf05b97 100644
--- a/drivers/usb/core/sysfs.c
+++ b/drivers/usb/core/sysfs.c
@@ -842,22 +842,19 @@
NULL
};
-int usb_create_sysfs_intf_files(struct usb_interface *intf)
+void usb_create_sysfs_intf_files(struct usb_interface *intf)
{
struct usb_device *udev = interface_to_usbdev(intf);
struct usb_host_interface *alt = intf->cur_altsetting;
- int retval;
if (intf->sysfs_files_created || intf->unregistering)
- return 0;
+ return;
- if (alt->string == NULL &&
- !(udev->quirks & USB_QUIRK_CONFIG_INTF_STRINGS))
+ if (!alt->string && !(udev->quirks & USB_QUIRK_CONFIG_INTF_STRINGS))
alt->string = usb_cache_string(udev, alt->desc.iInterface);
- if (alt->string)
- retval = device_create_file(&intf->dev, &dev_attr_interface);
+ if (alt->string && device_create_file(&intf->dev, &dev_attr_interface))
+ ; /* We don't actually care if the function fails. */
intf->sysfs_files_created = 1;
- return 0;
}
void usb_remove_sysfs_intf_files(struct usb_interface *intf)
diff --git a/drivers/usb/core/usb.c b/drivers/usb/core/usb.c
index d9d4b16..8706fc9 100644
--- a/drivers/usb/core/usb.c
+++ b/drivers/usb/core/usb.c
@@ -953,8 +953,7 @@
if (dev->type == &usb_device_type)
(void) usb_create_sysfs_dev_files(to_usb_device(dev));
else if (dev->type == &usb_if_device_type)
- (void) usb_create_sysfs_intf_files(
- to_usb_interface(dev));
+ usb_create_sysfs_intf_files(to_usb_interface(dev));
break;
case BUS_NOTIFY_DEL_DEVICE:
diff --git a/drivers/usb/core/usb.h b/drivers/usb/core/usb.h
index d450b74..d44d4b7 100644
--- a/drivers/usb/core/usb.h
+++ b/drivers/usb/core/usb.h
@@ -4,7 +4,7 @@
extern int usb_create_sysfs_dev_files(struct usb_device *dev);
extern void usb_remove_sysfs_dev_files(struct usb_device *dev);
-extern int usb_create_sysfs_intf_files(struct usb_interface *intf);
+extern void usb_create_sysfs_intf_files(struct usb_interface *intf);
extern void usb_remove_sysfs_intf_files(struct usb_interface *intf);
extern int usb_create_ep_devs(struct device *parent,
struct usb_host_endpoint *endpoint,
diff --git a/drivers/usb/early/ehci-dbgp.c b/drivers/usb/early/ehci-dbgp.c
index a6a350f..1fc8f12 100644
--- a/drivers/usb/early/ehci-dbgp.c
+++ b/drivers/usb/early/ehci-dbgp.c
@@ -102,6 +102,9 @@
#define dbgp_kgdb_mode (0)
#endif
+/* Local version of HC_LENGTH macro as ehci struct is not available here */
+#define EARLY_HC_LENGTH(p) (0x00ff & (p)) /* bits 7 : 0 */
+
/*
* USB Packet IDs (PIDs)
*/
@@ -892,7 +895,7 @@
dbgp_printk("ehci_bar: %p\n", ehci_bar);
ehci_caps = ehci_bar;
- ehci_regs = ehci_bar + HC_LENGTH(readl(&ehci_caps->hc_capbase));
+ ehci_regs = ehci_bar + EARLY_HC_LENGTH(readl(&ehci_caps->hc_capbase));
ehci_debug = ehci_bar + offset;
ehci_dev.bus = bus;
ehci_dev.slot = slot;
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index bc5123c..58456d1 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -260,6 +260,24 @@
default USB_GADGET
select USB_GADGET_SELECTED
+config USB_GADGET_RENESAS_USBHS
+ boolean "Renesas USBHS"
+ depends on USB_RENESAS_USBHS
+ select USB_GADGET_DUALSPEED
+ help
+ Renesas USBHS is a discrete USB host and peripheral controller
+ chip that supports both full and high speed USB 2.0 data transfers.
+ platform is able to configure endpoint (pipe) style
+
+ Say "y" to enable the gadget specific portion of the USBHS driver.
+
+
+config USB_RENESAS_USBHS_UDC
+ tristate
+ depends on USB_GADGET_RENESAS_USBHS
+ default USB_GADGET
+ select USB_GADGET_SELECTED
+
config USB_GADGET_PXA27X
boolean "PXA 27x"
depends on ARCH_PXA && (PXA27x || PXA3xx)
@@ -338,6 +356,23 @@
boolean "S3C2410 udc debug messages"
depends on USB_GADGET_S3C2410
+config USB_GADGET_S3C_HSUDC
+ boolean "S3C2416, S3C2443 and S3C2450 USB Device Controller"
+ depends on ARCH_S3C2410
+ select USB_GADGET_DUALSPEED
+ help
+ Samsung's S3C2416, S3C2443 and S3C2450 is an ARM9 based SoC
+ integrated with dual speed USB 2.0 device controller. It has
+ 8 endpoints, as well as endpoint zero.
+
+ This driver has been tested on S3C2416 and S3C2450 processors.
+
+config USB_S3C_HSUDC
+ tristate
+ depends on USB_GADGET_S3C_HSUDC
+ default USB_GADGET
+ select USB_GADGET_SELECTED
+
config USB_GADGET_PXA_U2O
boolean "PXA9xx Processor USB2.0 controller"
select USB_GADGET_DUALSPEED
diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile
index 1ea15ee..4fe92b1 100644
--- a/drivers/usb/gadget/Makefile
+++ b/drivers/usb/gadget/Makefile
@@ -22,6 +22,7 @@
obj-$(CONFIG_USB_FSL_QE) += fsl_qe_udc.o
obj-$(CONFIG_USB_CI13XXX_PCI) += ci13xxx_pci.o
obj-$(CONFIG_USB_S3C_HSOTG) += s3c-hsotg.o
+obj-$(CONFIG_USB_S3C_HSUDC) += s3c-hsudc.o
obj-$(CONFIG_USB_LANGWELL) += langwell_udc.o
obj-$(CONFIG_USB_EG20T) += pch_udc.o
obj-$(CONFIG_USB_PXA_U2O) += mv_udc.o
diff --git a/drivers/usb/gadget/at91_udc.c b/drivers/usb/gadget/at91_udc.c
index 9b7cdb1..41dc093 100644
--- a/drivers/usb/gadget/at91_udc.c
+++ b/drivers/usb/gadget/at91_udc.c
@@ -1767,7 +1767,7 @@
}
/* newer chips have more FIFO memory than rm9200 */
- if (cpu_is_at91sam9260()) {
+ if (cpu_is_at91sam9260() || cpu_is_at91sam9g20()) {
udc->ep[0].maxpacket = 64;
udc->ep[3].maxpacket = 64;
udc->ep[4].maxpacket = 512;
diff --git a/drivers/usb/gadget/ci13xxx_udc.c b/drivers/usb/gadget/ci13xxx_udc.c
index e09178b..baaf87e 100644
--- a/drivers/usb/gadget/ci13xxx_udc.c
+++ b/drivers/usb/gadget/ci13xxx_udc.c
@@ -310,7 +310,7 @@
udc->udc_driver->notify_event(udc,
CI13XXX_CONTROLLER_RESET_EVENT);
- if (udc->udc_driver->flags && CI13XXX_DISABLE_STREAMING)
+ if (udc->udc_driver->flags & CI13XXX_DISABLE_STREAMING)
hw_cwrite(CAP_USBMODE, USBMODE_SDIS, USBMODE_SDIS);
/* USBMODE should be configured step by step */
@@ -1634,8 +1634,6 @@
gadget_for_each_ep(ep, gadget) {
usb_ep_disable(ep);
}
- usb_ep_disable(&udc->ep0out.ep);
- usb_ep_disable(&udc->ep0in.ep);
if (udc->status != NULL) {
usb_ep_free_request(&udc->ep0in.ep, udc->status);
@@ -1678,18 +1676,10 @@
if (retval)
goto done;
- retval = usb_ep_enable(&udc->ep0out.ep, &ctrl_endpt_out_desc);
- if (retval)
- goto done;
+ udc->status = usb_ep_alloc_request(&udc->ep0in.ep, GFP_ATOMIC);
+ if (udc->status == NULL)
+ retval = -ENOMEM;
- retval = usb_ep_enable(&udc->ep0in.ep, &ctrl_endpt_in_desc);
- if (!retval) {
- udc->status = usb_ep_alloc_request(&udc->ep0in.ep, GFP_ATOMIC);
- if (udc->status == NULL) {
- usb_ep_disable(&udc->ep0out.ep);
- retval = -ENOMEM;
- }
- }
spin_lock(udc->lock);
done:
@@ -1843,7 +1833,8 @@
__acquires(mEp->lock)
{
struct ci13xxx_req *mReq, *mReqTemp;
- int retval;
+ struct ci13xxx_ep *mEpTemp = mEp;
+ int uninitialized_var(retval);
trace("%p", mEp);
@@ -1859,12 +1850,15 @@
dbg_done(_usb_addr(mEp), mReq->ptr->token, retval);
if (mReq->req.complete != NULL) {
spin_unlock(mEp->lock);
- mReq->req.complete(&mEp->ep, &mReq->req);
+ if ((mEp->type == USB_ENDPOINT_XFER_CONTROL) &&
+ mReq->req.length)
+ mEpTemp = &_udc->ep0in;
+ mReq->req.complete(&mEpTemp->ep, &mReq->req);
spin_lock(mEp->lock);
}
}
- if (retval == EBUSY)
+ if (retval == -EBUSY)
retval = 0;
if (retval < 0)
dbg_event(_usb_addr(mEp), "DONE", retval);
@@ -1894,7 +1888,7 @@
for (i = 0; i < hw_ep_max; i++) {
struct ci13xxx_ep *mEp = &udc->ci13xxx_ep[i];
- int type, num, err = -EINVAL;
+ int type, num, dir, err = -EINVAL;
struct usb_ctrlrequest req;
if (mEp->desc == NULL)
@@ -1952,7 +1946,10 @@
if (req.wLength != 0)
break;
num = le16_to_cpu(req.wIndex);
+ dir = num & USB_ENDPOINT_DIR_MASK;
num &= USB_ENDPOINT_NUMBER_MASK;
+ if (dir) /* TX */
+ num += hw_ep_max/2;
if (!udc->ci13xxx_ep[num].wedge) {
spin_unlock(udc->lock);
err = usb_ep_clear_halt(
@@ -2001,7 +1998,10 @@
if (req.wLength != 0)
break;
num = le16_to_cpu(req.wIndex);
+ dir = num & USB_ENDPOINT_DIR_MASK;
num &= USB_ENDPOINT_NUMBER_MASK;
+ if (dir) /* TX */
+ num += hw_ep_max/2;
spin_unlock(udc->lock);
err = usb_ep_set_halt(&udc->ci13xxx_ep[num].ep);
@@ -2110,7 +2110,12 @@
(mEp->ep.maxpacket << ffs_nr(QH_MAX_PKT)) & QH_MAX_PKT;
mEp->qh.ptr->td.next |= TD_TERMINATE; /* needed? */
- retval |= hw_ep_enable(mEp->num, mEp->dir, mEp->type);
+ /*
+ * Enable endpoints in the HW other than ep0 as ep0
+ * is always enabled
+ */
+ if (mEp->num)
+ retval |= hw_ep_enable(mEp->num, mEp->dir, mEp->type);
spin_unlock_irqrestore(mEp->lock, flags);
return retval;
@@ -2242,11 +2247,15 @@
spin_lock_irqsave(mEp->lock, flags);
- if (mEp->type == USB_ENDPOINT_XFER_CONTROL &&
- !list_empty(&mEp->qh.queue)) {
- _ep_nuke(mEp);
- retval = -EOVERFLOW;
- warn("endpoint ctrl %X nuked", _usb_addr(mEp));
+ if (mEp->type == USB_ENDPOINT_XFER_CONTROL) {
+ if (req->length)
+ mEp = (_udc->ep0_dir == RX) ?
+ &_udc->ep0out : &_udc->ep0in;
+ if (!list_empty(&mEp->qh.queue)) {
+ _ep_nuke(mEp);
+ retval = -EOVERFLOW;
+ warn("endpoint ctrl %X nuked", _usb_addr(mEp));
+ }
}
/* first nuke then test link, e.g. previous status has not sent */
@@ -2497,6 +2506,15 @@
return ret;
}
+static int ci13xxx_vbus_draw(struct usb_gadget *_gadget, unsigned mA)
+{
+ struct ci13xxx *udc = container_of(_gadget, struct ci13xxx, gadget);
+
+ if (udc->transceiver)
+ return otg_set_power(udc->transceiver, mA);
+ return -ENOTSUPP;
+}
+
/**
* Device operations part of the API to the USB controller hardware,
* which don't involve endpoints (or i/o)
@@ -2505,6 +2523,7 @@
static const struct usb_gadget_ops usb_gadget_ops = {
.vbus_session = ci13xxx_vbus_session,
.wakeup = ci13xxx_wakeup,
+ .vbus_draw = ci13xxx_vbus_draw,
};
/**
@@ -2595,6 +2614,14 @@
}
if (retval)
goto done;
+ spin_unlock_irqrestore(udc->lock, flags);
+ retval = usb_ep_enable(&udc->ep0out.ep, &ctrl_endpt_out_desc);
+ if (retval)
+ return retval;
+ retval = usb_ep_enable(&udc->ep0in.ep, &ctrl_endpt_in_desc);
+ if (retval)
+ return retval;
+ spin_lock_irqsave(udc->lock, flags);
udc->gadget.ep0 = &udc->ep0in.ep;
/* bind gadget */
diff --git a/drivers/usb/gadget/composite.c b/drivers/usb/gadget/composite.c
index 82314ed..5cbb1a4 100644
--- a/drivers/usb/gadget/composite.c
+++ b/drivers/usb/gadget/composite.c
@@ -461,12 +461,23 @@
reset_config(cdev);
goto done;
}
+
+ if (result == USB_GADGET_DELAYED_STATUS) {
+ DBG(cdev,
+ "%s: interface %d (%s) requested delayed status\n",
+ __func__, tmp, f->name);
+ cdev->delayed_status++;
+ DBG(cdev, "delayed_status count %d\n",
+ cdev->delayed_status);
+ }
}
/* when we return, be sure our power usage is valid */
power = c->bMaxPower ? (2 * c->bMaxPower) : CONFIG_USB_GADGET_VBUS_DRAW;
done:
usb_gadget_vbus_draw(gadget, power);
+ if (result >= 0 && cdev->delayed_status)
+ result = USB_GADGET_DELAYED_STATUS;
return result;
}
@@ -895,6 +906,14 @@
if (w_value && !f->set_alt)
break;
value = f->set_alt(f, w_index, w_value);
+ if (value == USB_GADGET_DELAYED_STATUS) {
+ DBG(cdev,
+ "%s: interface %d (%s) requested delayed status\n",
+ __func__, intf, f->name);
+ cdev->delayed_status++;
+ DBG(cdev, "delayed_status count %d\n",
+ cdev->delayed_status);
+ }
break;
case USB_REQ_GET_INTERFACE:
if (ctrl->bRequestType != (USB_DIR_IN|USB_RECIP_INTERFACE))
@@ -958,7 +977,7 @@
}
/* respond with data transfer before status phase? */
- if (value >= 0) {
+ if (value >= 0 && value != USB_GADGET_DELAYED_STATUS) {
req->length = value;
req->zero = value < w_length;
value = usb_ep_queue(gadget->ep0, req, GFP_ATOMIC);
@@ -967,6 +986,10 @@
req->status = 0;
composite_setup_complete(gadget->ep0, req);
}
+ } else if (value == USB_GADGET_DELAYED_STATUS && w_length != 0) {
+ WARN(cdev,
+ "%s: Delayed status not supported for w_length != 0",
+ __func__);
}
done:
@@ -1289,3 +1312,40 @@
return;
usb_gadget_unregister_driver(&composite_driver);
}
+
+/**
+ * usb_composite_setup_continue() - Continue with the control transfer
+ * @cdev: the composite device who's control transfer was kept waiting
+ *
+ * This function must be called by the USB function driver to continue
+ * with the control transfer's data/status stage in case it had requested to
+ * delay the data/status stages. A USB function's setup handler (e.g. set_alt())
+ * can request the composite framework to delay the setup request's data/status
+ * stages by returning USB_GADGET_DELAYED_STATUS.
+ */
+void usb_composite_setup_continue(struct usb_composite_dev *cdev)
+{
+ int value;
+ struct usb_request *req = cdev->req;
+ unsigned long flags;
+
+ DBG(cdev, "%s\n", __func__);
+ spin_lock_irqsave(&cdev->lock, flags);
+
+ if (cdev->delayed_status == 0) {
+ WARN(cdev, "%s: Unexpected call\n", __func__);
+
+ } else if (--cdev->delayed_status == 0) {
+ DBG(cdev, "%s: Completing delayed status\n", __func__);
+ req->length = 0;
+ value = usb_ep_queue(cdev->gadget->ep0, req, GFP_ATOMIC);
+ if (value < 0) {
+ DBG(cdev, "ep_queue --> %d\n", value);
+ req->status = 0;
+ composite_setup_complete(cdev->gadget->ep0, req);
+ }
+ }
+
+ spin_unlock_irqrestore(&cdev->lock, flags);
+}
+
diff --git a/drivers/usb/gadget/dbgp.c b/drivers/usb/gadget/dbgp.c
index e5ac8a3..dbe92ee 100644
--- a/drivers/usb/gadget/dbgp.c
+++ b/drivers/usb/gadget/dbgp.c
@@ -261,8 +261,8 @@
o_desc.wMaxPacketSize =
__constant_cpu_to_le16(USB_DEBUG_MAX_PACKET_SIZE);
- dbg_desc.bDebugInEndpoint = i_desc.bEndpointAddress & 0x7f;
- dbg_desc.bDebugOutEndpoint = o_desc.bEndpointAddress & 0x7f;
+ dbg_desc.bDebugInEndpoint = i_desc.bEndpointAddress;
+ dbg_desc.bDebugOutEndpoint = o_desc.bEndpointAddress;
#ifdef CONFIG_USB_G_DBGP_SERIAL
dbgp.serial->in = dbgp.i_ep;
@@ -312,6 +312,7 @@
dbgp.req->length = DBGP_REQ_EP0_LEN;
gadget->ep0->driver_data = gadget;
+ device_desc.bMaxPacketSize0 = gadget->ep0->maxpacket;
#ifdef CONFIG_USB_G_DBGP_SERIAL
dbgp.serial = kzalloc(sizeof(struct gserial), GFP_KERNEL);
@@ -350,9 +351,9 @@
u8 request = ctrl->bRequest;
u16 value = le16_to_cpu(ctrl->wValue);
u16 length = le16_to_cpu(ctrl->wLength);
- int err = 0;
- void *data;
- u16 len;
+ int err = -EOPNOTSUPP;
+ void *data = NULL;
+ u16 len = 0;
gadget->ep0->driver_data = gadget;
@@ -371,10 +372,9 @@
default:
goto fail;
}
+ err = 0;
} else if (request == USB_REQ_SET_FEATURE &&
value == USB_DEVICE_DEBUG_MODE) {
- len = 0;
- data = NULL;
dev_dbg(&dbgp.gadget->dev, "setup: feat debug\n");
#ifdef CONFIG_USB_G_DBGP_PRINTK
err = dbgp_enable_ep();
diff --git a/drivers/usb/gadget/dummy_hcd.c b/drivers/usb/gadget/dummy_hcd.c
index 3214ca3..61ff927 100644
--- a/drivers/usb/gadget/dummy_hcd.c
+++ b/drivers/usb/gadget/dummy_hcd.c
@@ -892,10 +892,11 @@
return rc;
}
- platform_set_drvdata (pdev, dum);
rc = device_create_file (&dum->gadget.dev, &dev_attr_function);
if (rc < 0)
device_unregister (&dum->gadget.dev);
+ else
+ platform_set_drvdata(pdev, dum);
return rc;
}
@@ -1995,11 +1996,29 @@
retval = platform_device_add(the_hcd_pdev);
if (retval < 0)
goto err_add_hcd;
+ if (!the_controller) {
+ /*
+ * The hcd was added successfully but its probe function failed
+ * for some reason.
+ */
+ retval = -EINVAL;
+ goto err_add_udc;
+ }
retval = platform_device_add(the_udc_pdev);
if (retval < 0)
goto err_add_udc;
+ if (!platform_get_drvdata(the_udc_pdev)) {
+ /*
+ * The udc was added successfully but its probe function failed
+ * for some reason.
+ */
+ retval = -EINVAL;
+ goto err_probe_udc;
+ }
return retval;
+err_probe_udc:
+ platform_device_del(the_udc_pdev);
err_add_udc:
platform_device_del(the_hcd_pdev);
err_add_hcd:
diff --git a/drivers/usb/gadget/f_audio.c b/drivers/usb/gadget/f_audio.c
index 0111f8a..8ee330a 100644
--- a/drivers/usb/gadget/f_audio.c
+++ b/drivers/usb/gadget/f_audio.c
@@ -177,7 +177,7 @@
};
/* Standard ISO OUT Endpoint Descriptor */
-static struct usb_endpoint_descriptor as_out_ep_desc __initdata = {
+static struct usb_endpoint_descriptor as_out_ep_desc = {
.bLength = USB_DT_ENDPOINT_AUDIO_SIZE,
.bDescriptorType = USB_DT_ENDPOINT,
.bEndpointAddress = USB_DIR_OUT,
diff --git a/drivers/usb/gadget/f_mass_storage.c b/drivers/usb/gadget/f_mass_storage.c
index 6d8e533..efb58f9 100644
--- a/drivers/usb/gadget/f_mass_storage.c
+++ b/drivers/usb/gadget/f_mass_storage.c
@@ -347,6 +347,7 @@
/* Data shared by all the FSG instances. */
struct fsg_common {
struct usb_gadget *gadget;
+ struct usb_composite_dev *cdev;
struct fsg_dev *fsg, *new_fsg;
wait_queue_head_t fsg_wait;
@@ -613,6 +614,11 @@
if (!fsg_is_set(fsg->common))
return -EOPNOTSUPP;
+ ++fsg->common->ep0_req_tag; /* Record arrival of a new request */
+ req->context = NULL;
+ req->length = 0;
+ dump_msg(fsg, "ep0-setup", (u8 *) ctrl, sizeof(*ctrl));
+
switch (ctrl->bRequest) {
case USB_BULK_RESET_REQUEST:
@@ -1584,37 +1590,6 @@
return rc;
}
-static int pad_with_zeros(struct fsg_dev *fsg)
-{
- struct fsg_buffhd *bh = fsg->common->next_buffhd_to_fill;
- u32 nkeep = bh->inreq->length;
- u32 nsend;
- int rc;
-
- bh->state = BUF_STATE_EMPTY; /* For the first iteration */
- fsg->common->usb_amount_left = nkeep + fsg->common->residue;
- while (fsg->common->usb_amount_left > 0) {
-
- /* Wait for the next buffer to be free */
- while (bh->state != BUF_STATE_EMPTY) {
- rc = sleep_thread(fsg->common);
- if (rc)
- return rc;
- }
-
- nsend = min(fsg->common->usb_amount_left, FSG_BUFLEN);
- memset(bh->buf + nkeep, 0, nsend - nkeep);
- bh->inreq->length = nsend;
- bh->inreq->zero = 0;
- start_transfer(fsg, fsg->bulk_in, bh->inreq,
- &bh->inreq_busy, &bh->state);
- bh = fsg->common->next_buffhd_to_fill = bh->next;
- fsg->common->usb_amount_left -= nsend;
- nkeep = 0;
- }
- return 0;
-}
-
static int throw_away_data(struct fsg_common *common)
{
struct fsg_buffhd *bh;
@@ -1702,6 +1677,10 @@
if (common->data_size == 0) {
/* Nothing to send */
+ /* Don't know what to do if common->fsg is NULL */
+ } else if (!fsg_is_set(common)) {
+ rc = -EIO;
+
/* If there's no residue, simply send the last buffer */
} else if (common->residue == 0) {
bh->inreq->zero = 0;
@@ -1710,24 +1689,19 @@
common->next_buffhd_to_fill = bh->next;
/*
- * For Bulk-only, if we're allowed to stall then send the
- * short packet and halt the bulk-in endpoint. If we can't
- * stall, pad out the remaining data with 0's.
+ * For Bulk-only, mark the end of the data with a short
+ * packet. If we are allowed to stall, halt the bulk-in
+ * endpoint. (Note: This violates the Bulk-Only Transport
+ * specification, which requires us to pad the data if we
+ * don't halt the endpoint. Presumably nobody will mind.)
*/
- } else if (common->can_stall) {
+ } else {
bh->inreq->zero = 1;
if (!start_in_transfer(common, bh))
- /* Don't know what to do if
- * common->fsg is NULL */
rc = -EIO;
common->next_buffhd_to_fill = bh->next;
- if (common->fsg)
+ if (common->can_stall)
rc = halt_bulk_in_endpoint(common->fsg);
- } else if (fsg_is_set(common)) {
- rc = pad_with_zeros(common->fsg);
- } else {
- /* Don't know what to do if common->fsg is NULL */
- rc = -EIO;
}
break;
@@ -1910,7 +1884,7 @@
common->lun, lun);
/* Check the LUN */
- if (common->lun >= 0 && common->lun < common->nluns) {
+ if (common->lun < common->nluns) {
curlun = &common->luns[common->lun];
common->curlun = curlun;
if (common->cmnd[0] != REQUEST_SENSE) {
@@ -2468,7 +2442,7 @@
struct fsg_dev *fsg = fsg_from_func(f);
fsg->common->new_fsg = fsg;
raise_exception(fsg->common, FSG_STATE_CONFIG_CHANGE);
- return 0;
+ return USB_GADGET_DELAYED_STATUS;
}
static void fsg_disable(struct usb_function *f)
@@ -2604,6 +2578,8 @@
case FSG_STATE_CONFIG_CHANGE:
do_set_interface(common, common->new_fsg);
+ if (common->new_fsg)
+ usb_composite_setup_continue(common->cdev);
break;
case FSG_STATE_EXIT:
@@ -2774,6 +2750,7 @@
common->gadget = gadget;
common->ep0 = gadget->ep0;
common->ep0req = cdev->req;
+ common->cdev = cdev;
/* Maybe allocate device-global string IDs, and patch descriptors */
if (fsg_strings[FSG_STRING_INTERFACE].id == 0) {
@@ -2800,6 +2777,7 @@
for (i = 0, lcfg = cfg->luns; i < nluns; ++i, ++curlun, ++lcfg) {
curlun->cdrom = !!lcfg->cdrom;
curlun->ro = lcfg->cdrom || lcfg->ro;
+ curlun->initially_ro = curlun->ro;
curlun->removable = lcfg->removable;
curlun->dev.release = fsg_lun_release;
curlun->dev.parent = &gadget->dev;
diff --git a/drivers/usb/gadget/f_rndis.c b/drivers/usb/gadget/f_rndis.c
index 882484a..fa12ec8 100644
--- a/drivers/usb/gadget/f_rndis.c
+++ b/drivers/usb/gadget/f_rndis.c
@@ -420,8 +420,7 @@
*/
case ((USB_DIR_OUT | USB_TYPE_CLASS | USB_RECIP_INTERFACE) << 8)
| USB_CDC_SEND_ENCAPSULATED_COMMAND:
- if (w_length > req->length || w_value
- || w_index != rndis->ctrl_id)
+ if (w_value || w_index != rndis->ctrl_id)
goto invalid;
/* read the request; process it later */
value = w_length;
diff --git a/drivers/usb/gadget/file_storage.c b/drivers/usb/gadget/file_storage.c
index a6eacb5..0360f56 100644
--- a/drivers/usb/gadget/file_storage.c
+++ b/drivers/usb/gadget/file_storage.c
@@ -1947,37 +1947,6 @@
return rc;
}
-static int pad_with_zeros(struct fsg_dev *fsg)
-{
- struct fsg_buffhd *bh = fsg->next_buffhd_to_fill;
- u32 nkeep = bh->inreq->length;
- u32 nsend;
- int rc;
-
- bh->state = BUF_STATE_EMPTY; // For the first iteration
- fsg->usb_amount_left = nkeep + fsg->residue;
- while (fsg->usb_amount_left > 0) {
-
- /* Wait for the next buffer to be free */
- while (bh->state != BUF_STATE_EMPTY) {
- rc = sleep_thread(fsg);
- if (rc)
- return rc;
- }
-
- nsend = min(fsg->usb_amount_left, (u32) mod_data.buflen);
- memset(bh->buf + nkeep, 0, nsend - nkeep);
- bh->inreq->length = nsend;
- bh->inreq->zero = 0;
- start_transfer(fsg, fsg->bulk_in, bh->inreq,
- &bh->inreq_busy, &bh->state);
- bh = fsg->next_buffhd_to_fill = bh->next;
- fsg->usb_amount_left -= nsend;
- nkeep = 0;
- }
- return 0;
-}
-
static int throw_away_data(struct fsg_dev *fsg)
{
struct fsg_buffhd *bh;
@@ -2082,18 +2051,20 @@
}
}
- /* For Bulk-only, if we're allowed to stall then send the
- * short packet and halt the bulk-in endpoint. If we can't
- * stall, pad out the remaining data with 0's. */
+ /*
+ * For Bulk-only, mark the end of the data with a short
+ * packet. If we are allowed to stall, halt the bulk-in
+ * endpoint. (Note: This violates the Bulk-Only Transport
+ * specification, which requires us to pad the data if we
+ * don't halt the endpoint. Presumably nobody will mind.)
+ */
else {
- if (mod_data.can_stall) {
- bh->inreq->zero = 1;
- start_transfer(fsg, fsg->bulk_in, bh->inreq,
- &bh->inreq_busy, &bh->state);
- fsg->next_buffhd_to_fill = bh->next;
+ bh->inreq->zero = 1;
+ start_transfer(fsg, fsg->bulk_in, bh->inreq,
+ &bh->inreq_busy, &bh->state);
+ fsg->next_buffhd_to_fill = bh->next;
+ if (mod_data.can_stall)
rc = halt_bulk_in_endpoint(fsg);
- } else
- rc = pad_with_zeros(fsg);
}
break;
@@ -2314,7 +2285,7 @@
fsg->lun = lun; // Use LUN from the command
/* Check the LUN */
- if (fsg->lun >= 0 && fsg->lun < fsg->nluns) {
+ if (fsg->lun < fsg->nluns) {
fsg->curlun = curlun = &fsg->luns[fsg->lun];
if (fsg->cmnd[0] != REQUEST_SENSE) {
curlun->sense_data = SS_NO_SENSE;
diff --git a/drivers/usb/gadget/fsl_qe_udc.h b/drivers/usb/gadget/fsl_qe_udc.h
index e35e24f..1da5fb0 100644
--- a/drivers/usb/gadget/fsl_qe_udc.h
+++ b/drivers/usb/gadget/fsl_qe_udc.h
@@ -207,7 +207,7 @@
/* Frame status field */
/* Receive side */
-#define FRAME_OK 0x00000000 /* Frame tranmitted or received OK */
+#define FRAME_OK 0x00000000 /* Frame transmitted or received OK */
#define FRAME_ERROR 0x80000000 /* Error occurred on frame */
#define START_FRAME_LOST 0x40000000 /* START_FRAME_LOST */
#define END_FRAME_LOST 0x20000000 /* END_FRAME_LOST */
diff --git a/drivers/usb/gadget/fsl_udc_core.c b/drivers/usb/gadget/fsl_udc_core.c
index 07499c1..2cd9a60 100644
--- a/drivers/usb/gadget/fsl_udc_core.c
+++ b/drivers/usb/gadget/fsl_udc_core.c
@@ -1,12 +1,13 @@
/*
- * Copyright (C) 2004-2007 Freescale Semicondutor, Inc. All rights reserved.
+ * Copyright (C) 2004-2007,2011 Freescale Semiconductor, Inc.
+ * All rights reserved.
*
* Author: Li Yang <leoli@freescale.com>
* Jiang Bo <tanya.jiang@freescale.com>
*
* Description:
* Freescale high-speed USB SOC DR module device controller driver.
- * This can be found on MPC8349E/MPC8313E cpus.
+ * This can be found on MPC8349E/MPC8313E/MPC5121E cpus.
* The driver is previously named as mpc_udc. Based on bare board
* code from Dave Liu and Shlomi Gridish.
*
@@ -45,6 +46,7 @@
#include <asm/system.h>
#include <asm/unaligned.h>
#include <asm/dma.h>
+#include <asm/cacheflush.h>
#include "fsl_usb2_udc.h"
@@ -77,12 +79,64 @@
static void fsl_ep_fifo_flush(struct usb_ep *_ep);
#ifdef CONFIG_PPC32
-#define fsl_readl(addr) in_le32(addr)
-#define fsl_writel(val32, addr) out_le32(addr, val32)
-#else
+/*
+ * On some SoCs, the USB controller registers can be big or little endian,
+ * depending on the version of the chip. In order to be able to run the
+ * same kernel binary on 2 different versions of an SoC, the BE/LE decision
+ * must be made at run time. _fsl_readl and fsl_writel are pointers to the
+ * BE or LE readl() and writel() functions, and fsl_readl() and fsl_writel()
+ * call through those pointers. Platform code for SoCs that have BE USB
+ * registers should set pdata->big_endian_mmio flag.
+ *
+ * This also applies to controller-to-cpu accessors for the USB descriptors,
+ * since their endianness is also SoC dependant. Platform code for SoCs that
+ * have BE USB descriptors should set pdata->big_endian_desc flag.
+ */
+static u32 _fsl_readl_be(const unsigned __iomem *p)
+{
+ return in_be32(p);
+}
+
+static u32 _fsl_readl_le(const unsigned __iomem *p)
+{
+ return in_le32(p);
+}
+
+static void _fsl_writel_be(u32 v, unsigned __iomem *p)
+{
+ out_be32(p, v);
+}
+
+static void _fsl_writel_le(u32 v, unsigned __iomem *p)
+{
+ out_le32(p, v);
+}
+
+static u32 (*_fsl_readl)(const unsigned __iomem *p);
+static void (*_fsl_writel)(u32 v, unsigned __iomem *p);
+
+#define fsl_readl(p) (*_fsl_readl)((p))
+#define fsl_writel(v, p) (*_fsl_writel)((v), (p))
+
+static inline u32 cpu_to_hc32(const u32 x)
+{
+ return udc_controller->pdata->big_endian_desc
+ ? (__force u32)cpu_to_be32(x)
+ : (__force u32)cpu_to_le32(x);
+}
+
+static inline u32 hc32_to_cpu(const u32 x)
+{
+ return udc_controller->pdata->big_endian_desc
+ ? be32_to_cpu((__force __be32)x)
+ : le32_to_cpu((__force __le32)x);
+}
+#else /* !CONFIG_PPC32 */
#define fsl_readl(addr) readl(addr)
#define fsl_writel(val32, addr) writel(val32, addr)
-#endif
+#define cpu_to_hc32(x) cpu_to_le32(x)
+#define hc32_to_cpu(x) le32_to_cpu(x)
+#endif /* CONFIG_PPC32 */
/********************************************************************
* Internal Used Function
@@ -177,7 +231,8 @@
static int dr_controller_setup(struct fsl_udc *udc)
{
- unsigned int tmp, portctrl;
+ unsigned int tmp, portctrl, ep_num;
+ unsigned int max_no_of_ep;
#ifndef CONFIG_ARCH_MXC
unsigned int ctrl;
#endif
@@ -226,9 +281,12 @@
/* Set the controller as device mode */
tmp = fsl_readl(&dr_regs->usbmode);
+ tmp &= ~USB_MODE_CTRL_MODE_MASK; /* clear mode bits */
tmp |= USB_MODE_CTRL_MODE_DEVICE;
/* Disable Setup Lockout */
tmp |= USB_MODE_SETUP_LOCK_OFF;
+ if (udc->pdata->es)
+ tmp |= USB_MODE_ES;
fsl_writel(tmp, &dr_regs->usbmode);
/* Clear the setup status */
@@ -242,22 +300,34 @@
udc->ep_qh, (int)tmp,
fsl_readl(&dr_regs->endpointlistaddr));
+ max_no_of_ep = (0x0000001F & fsl_readl(&dr_regs->dccparams));
+ for (ep_num = 1; ep_num < max_no_of_ep; ep_num++) {
+ tmp = fsl_readl(&dr_regs->endptctrl[ep_num]);
+ tmp &= ~(EPCTRL_TX_TYPE | EPCTRL_RX_TYPE);
+ tmp |= (EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT)
+ | (EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT);
+ fsl_writel(tmp, &dr_regs->endptctrl[ep_num]);
+ }
/* Config control enable i/o output, cpu endian register */
#ifndef CONFIG_ARCH_MXC
- ctrl = __raw_readl(&usb_sys_regs->control);
- ctrl |= USB_CTRL_IOENB;
- __raw_writel(ctrl, &usb_sys_regs->control);
+ if (udc->pdata->have_sysif_regs) {
+ ctrl = __raw_readl(&usb_sys_regs->control);
+ ctrl |= USB_CTRL_IOENB;
+ __raw_writel(ctrl, &usb_sys_regs->control);
+ }
#endif
#if defined(CONFIG_PPC32) && !defined(CONFIG_NOT_COHERENT_CACHE)
/* Turn on cache snooping hardware, since some PowerPC platforms
* wholly rely on hardware to deal with cache coherent. */
- /* Setup Snooping for all the 4GB space */
- tmp = SNOOP_SIZE_2GB; /* starts from 0x0, size 2G */
- __raw_writel(tmp, &usb_sys_regs->snoop1);
- tmp |= 0x80000000; /* starts from 0x8000000, size 2G */
- __raw_writel(tmp, &usb_sys_regs->snoop2);
+ if (udc->pdata->have_sysif_regs) {
+ /* Setup Snooping for all the 4GB space */
+ tmp = SNOOP_SIZE_2GB; /* starts from 0x0, size 2G */
+ __raw_writel(tmp, &usb_sys_regs->snoop1);
+ tmp |= 0x80000000; /* starts from 0x8000000, size 2G */
+ __raw_writel(tmp, &usb_sys_regs->snoop2);
+ }
#endif
return 0;
@@ -293,6 +363,19 @@
{
unsigned int tmp;
+ pr_debug("%s\n", __func__);
+
+ /* if we're in OTG mode, and the Host is currently using the port,
+ * stop now and don't rip the controller out from under the
+ * ehci driver
+ */
+ if (udc->gadget.is_otg) {
+ if (!(fsl_readl(&dr_regs->otgsc) & OTGSC_STS_USB_ID)) {
+ pr_debug("udc: Leaving early\n");
+ return;
+ }
+ }
+
/* disable all INTR */
fsl_writel(0, &dr_regs->usbintr);
@@ -318,12 +401,14 @@
if (ep_num)
tmp_epctrl |= EPCTRL_TX_DATA_TOGGLE_RST;
tmp_epctrl |= EPCTRL_TX_ENABLE;
+ tmp_epctrl &= ~EPCTRL_TX_TYPE;
tmp_epctrl |= ((unsigned int)(ep_type)
<< EPCTRL_TX_EP_TYPE_SHIFT);
} else {
if (ep_num)
tmp_epctrl |= EPCTRL_RX_DATA_TOGGLE_RST;
tmp_epctrl |= EPCTRL_RX_ENABLE;
+ tmp_epctrl &= ~EPCTRL_RX_TYPE;
tmp_epctrl |= ((unsigned int)(ep_type)
<< EPCTRL_RX_EP_TYPE_SHIFT);
}
@@ -409,7 +494,7 @@
if (zlt)
tmp |= EP_QUEUE_HEAD_ZLT_SEL;
- p_QH->max_pkt_length = cpu_to_le32(tmp);
+ p_QH->max_pkt_length = cpu_to_hc32(tmp);
p_QH->next_dtd_ptr = 1;
p_QH->size_ioc_int_sts = 0;
}
@@ -546,10 +631,13 @@
/* disable ep on controller */
ep_num = ep_index(ep);
epctrl = fsl_readl(&dr_regs->endptctrl[ep_num]);
- if (ep_is_in(ep))
- epctrl &= ~EPCTRL_TX_ENABLE;
- else
- epctrl &= ~EPCTRL_RX_ENABLE;
+ if (ep_is_in(ep)) {
+ epctrl &= ~(EPCTRL_TX_ENABLE | EPCTRL_TX_TYPE);
+ epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_TX_EP_TYPE_SHIFT;
+ } else {
+ epctrl &= ~(EPCTRL_RX_ENABLE | EPCTRL_TX_TYPE);
+ epctrl |= EPCTRL_EP_TYPE_BULK << EPCTRL_RX_EP_TYPE_SHIFT;
+ }
fsl_writel(epctrl, &dr_regs->endptctrl[ep_num]);
udc = (struct fsl_udc *)ep->udc;
@@ -616,7 +704,7 @@
struct fsl_req *lastreq;
lastreq = list_entry(ep->queue.prev, struct fsl_req, queue);
lastreq->tail->next_td_ptr =
- cpu_to_le32(req->head->td_dma & DTD_ADDR_MASK);
+ cpu_to_hc32(req->head->td_dma & DTD_ADDR_MASK);
/* Read prime bit, if 1 goto done */
if (fsl_readl(&dr_regs->endpointprime) & bitmask)
goto out;
@@ -641,10 +729,10 @@
/* Write dQH next pointer and terminate bit to 0 */
temp = req->head->td_dma & EP_QUEUE_HEAD_NEXT_POINTER_MASK;
- dQH->next_dtd_ptr = cpu_to_le32(temp);
+ dQH->next_dtd_ptr = cpu_to_hc32(temp);
/* Clear active and halt bit */
- temp = cpu_to_le32(~(EP_QUEUE_HEAD_STATUS_ACTIVE
+ temp = cpu_to_hc32(~(EP_QUEUE_HEAD_STATUS_ACTIVE
| EP_QUEUE_HEAD_STATUS_HALT));
dQH->size_ioc_int_sts &= temp;
@@ -682,17 +770,17 @@
dtd->td_dma = *dma;
/* Clear reserved field */
- swap_temp = cpu_to_le32(dtd->size_ioc_sts);
+ swap_temp = hc32_to_cpu(dtd->size_ioc_sts);
swap_temp &= ~DTD_RESERVED_FIELDS;
- dtd->size_ioc_sts = cpu_to_le32(swap_temp);
+ dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
/* Init all of buffer page pointers */
swap_temp = (u32) (req->req.dma + req->req.actual);
- dtd->buff_ptr0 = cpu_to_le32(swap_temp);
- dtd->buff_ptr1 = cpu_to_le32(swap_temp + 0x1000);
- dtd->buff_ptr2 = cpu_to_le32(swap_temp + 0x2000);
- dtd->buff_ptr3 = cpu_to_le32(swap_temp + 0x3000);
- dtd->buff_ptr4 = cpu_to_le32(swap_temp + 0x4000);
+ dtd->buff_ptr0 = cpu_to_hc32(swap_temp);
+ dtd->buff_ptr1 = cpu_to_hc32(swap_temp + 0x1000);
+ dtd->buff_ptr2 = cpu_to_hc32(swap_temp + 0x2000);
+ dtd->buff_ptr3 = cpu_to_hc32(swap_temp + 0x3000);
+ dtd->buff_ptr4 = cpu_to_hc32(swap_temp + 0x4000);
req->req.actual += *length;
@@ -716,7 +804,7 @@
if (*is_last && !req->req.no_interrupt)
swap_temp |= DTD_IOC;
- dtd->size_ioc_sts = cpu_to_le32(swap_temp);
+ dtd->size_ioc_sts = cpu_to_hc32(swap_temp);
mb();
@@ -743,7 +831,7 @@
is_first = 0;
req->head = dtd;
} else {
- last_dtd->next_td_ptr = cpu_to_le32(dma);
+ last_dtd->next_td_ptr = cpu_to_hc32(dma);
last_dtd->next_td_virt = dtd;
}
last_dtd = dtd;
@@ -751,7 +839,7 @@
req->dtd_count++;
} while (!is_last);
- dtd->next_td_ptr = cpu_to_le32(DTD_NEXT_TERMINATE);
+ dtd->next_td_ptr = cpu_to_hc32(DTD_NEXT_TERMINATE);
req->tail = dtd;
@@ -962,6 +1050,36 @@
return status;
}
+static int fsl_ep_fifo_status(struct usb_ep *_ep)
+{
+ struct fsl_ep *ep;
+ struct fsl_udc *udc;
+ int size = 0;
+ u32 bitmask;
+ struct ep_queue_head *d_qh;
+
+ ep = container_of(_ep, struct fsl_ep, ep);
+ if (!_ep || (!ep->desc && ep_index(ep) != 0))
+ return -ENODEV;
+
+ udc = (struct fsl_udc *)ep->udc;
+
+ if (!udc->driver || udc->gadget.speed == USB_SPEED_UNKNOWN)
+ return -ESHUTDOWN;
+
+ d_qh = &ep->udc->ep_qh[ep_index(ep) * 2 + ep_is_in(ep)];
+
+ bitmask = (ep_is_in(ep)) ? (1 << (ep_index(ep) + 16)) :
+ (1 << (ep_index(ep)));
+
+ if (fsl_readl(&dr_regs->endptstatus) & bitmask)
+ size = (d_qh->size_ioc_int_sts & DTD_PACKET_SIZE)
+ >> DTD_LENGTH_BIT_POS;
+
+ pr_debug("%s %u\n", __func__, size);
+ return size;
+}
+
static void fsl_ep_fifo_flush(struct usb_ep *_ep)
{
struct fsl_ep *ep;
@@ -1014,6 +1132,7 @@
.dequeue = fsl_ep_dequeue,
.set_halt = fsl_ep_set_halt,
+ .fifo_status = fsl_ep_fifo_status,
.fifo_flush = fsl_ep_fifo_flush, /* flush fifo */
};
@@ -1228,6 +1347,10 @@
req = udc->status_req;
/* Fill in the reqest structure */
*((u16 *) req->req.buf) = cpu_to_le16(tmp);
+
+ /* flush cache for the req buffer */
+ flush_dcache_range((u32)req->req.buf, (u32)req->req.buf + 8);
+
req->ep = ep;
req->req.length = 2;
req->req.status = -EINPROGRESS;
@@ -1280,6 +1403,7 @@
/* Status phase from udc */
{
int rc = -EOPNOTSUPP;
+ u16 ptc = 0;
if ((setup->bRequestType & (USB_RECIP_MASK | USB_TYPE_MASK))
== (USB_RECIP_ENDPOINT | USB_TYPE_STANDARD)) {
@@ -1301,17 +1425,19 @@
| USB_TYPE_STANDARD)) {
/* Note: The driver has not include OTG support yet.
* This will be set when OTG support is added */
- if (!gadget_is_otg(&udc->gadget))
- break;
- else if (setup->bRequest == USB_DEVICE_B_HNP_ENABLE)
- udc->gadget.b_hnp_enable = 1;
- else if (setup->bRequest == USB_DEVICE_A_HNP_SUPPORT)
- udc->gadget.a_hnp_support = 1;
- else if (setup->bRequest ==
- USB_DEVICE_A_ALT_HNP_SUPPORT)
- udc->gadget.a_alt_hnp_support = 1;
- else
- break;
+ if (wValue == USB_DEVICE_TEST_MODE)
+ ptc = wIndex >> 8;
+ else if (gadget_is_otg(&udc->gadget)) {
+ if (setup->bRequest ==
+ USB_DEVICE_B_HNP_ENABLE)
+ udc->gadget.b_hnp_enable = 1;
+ else if (setup->bRequest ==
+ USB_DEVICE_A_HNP_SUPPORT)
+ udc->gadget.a_hnp_support = 1;
+ else if (setup->bRequest ==
+ USB_DEVICE_A_ALT_HNP_SUPPORT)
+ udc->gadget.a_alt_hnp_support = 1;
+ }
rc = 0;
} else
break;
@@ -1320,6 +1446,15 @@
if (ep0_prime_status(udc, EP_DIR_IN))
ep0stall(udc);
}
+ if (ptc) {
+ u32 tmp;
+
+ mdelay(10);
+ tmp = fsl_readl(&dr_regs->portsc1) | (ptc << 16);
+ fsl_writel(tmp, &dr_regs->portsc1);
+ printk(KERN_INFO "udc: switch to test mode %d.\n", ptc);
+ }
+
return;
}
@@ -1394,6 +1529,7 @@
{
u32 temp;
struct ep_queue_head *qh;
+ struct fsl_usb2_platform_data *pdata = udc->pdata;
qh = &udc->ep_qh[ep_num * 2 + EP_DIR_OUT];
@@ -1408,7 +1544,16 @@
fsl_writel(temp | USB_CMD_SUTW, &dr_regs->usbcmd);
/* Copy the setup packet to local buffer */
- memcpy(buffer_ptr, (u8 *) qh->setup_buffer, 8);
+ if (pdata->le_setup_buf) {
+ u32 *p = (u32 *)buffer_ptr;
+ u32 *s = (u32 *)qh->setup_buffer;
+
+ /* Convert little endian setup buffer to CPU endian */
+ *p++ = le32_to_cpu(*s++);
+ *p = le32_to_cpu(*s);
+ } else {
+ memcpy(buffer_ptr, (u8 *) qh->setup_buffer, 8);
+ }
} while (!(fsl_readl(&dr_regs->usbcmd) & USB_CMD_SUTW));
/* Clear Setup Tripwire */
@@ -1432,19 +1577,19 @@
actual = curr_req->req.length;
for (j = 0; j < curr_req->dtd_count; j++) {
- remaining_length = (le32_to_cpu(curr_td->size_ioc_sts)
+ remaining_length = (hc32_to_cpu(curr_td->size_ioc_sts)
& DTD_PACKET_SIZE)
>> DTD_LENGTH_BIT_POS;
actual -= remaining_length;
- if ((errors = le32_to_cpu(curr_td->size_ioc_sts) &
- DTD_ERROR_MASK)) {
+ errors = hc32_to_cpu(curr_td->size_ioc_sts);
+ if (errors & DTD_ERROR_MASK) {
if (errors & DTD_STATUS_HALTED) {
ERR("dTD error %08x QH=%d\n", errors, pipe);
/* Clear the errors and Halt condition */
- tmp = le32_to_cpu(curr_qh->size_ioc_int_sts);
+ tmp = hc32_to_cpu(curr_qh->size_ioc_int_sts);
tmp &= ~errors;
- curr_qh->size_ioc_int_sts = cpu_to_le32(tmp);
+ curr_qh->size_ioc_int_sts = cpu_to_hc32(tmp);
status = -EPIPE;
/* FIXME: continue with next queued TD? */
@@ -1462,7 +1607,7 @@
ERR("Unknown error has occurred (0x%x)!\n",
errors);
- } else if (le32_to_cpu(curr_td->size_ioc_sts)
+ } else if (hc32_to_cpu(curr_td->size_ioc_sts)
& DTD_STATUS_ACTIVE) {
VDBG("Request not complete");
status = REQ_UNCOMPLETE;
@@ -1551,6 +1696,9 @@
{
u32 speed;
+ if (udc->bus_reset)
+ udc->bus_reset = 0;
+
/* Bus resetting is finished */
if (!(fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET)) {
/* Get the speed */
@@ -1658,6 +1806,8 @@
if (fsl_readl(&dr_regs->portsc1) & PORTSCX_PORT_RESET) {
VDBG("Bus reset");
+ /* Bus is reseting */
+ udc->bus_reset = 1;
/* Reset all the queues, include XD, dTD, EP queue
* head and TR Queue */
reset_queues(udc);
@@ -1735,6 +1885,7 @@
/* Reset Received */
if (irq_src & USB_STS_RESET) {
+ VDBG("reset int");
reset_irq(udc);
status = IRQ_HANDLED;
}
@@ -1792,11 +1943,30 @@
goto out;
}
- /* Enable DR IRQ reg and Set usbcmd reg Run bit */
- dr_controller_run(udc_controller);
- udc_controller->usb_state = USB_STATE_ATTACHED;
- udc_controller->ep0_state = WAIT_FOR_SETUP;
- udc_controller->ep0_dir = 0;
+ if (udc_controller->transceiver) {
+ /* Suspend the controller until OTG enable it */
+ udc_controller->stopped = 1;
+ printk(KERN_INFO "Suspend udc for OTG auto detect\n");
+
+ /* connect to bus through transceiver */
+ if (udc_controller->transceiver) {
+ retval = otg_set_peripheral(udc_controller->transceiver,
+ &udc_controller->gadget);
+ if (retval < 0) {
+ ERR("can't bind to transceiver\n");
+ driver->unbind(&udc_controller->gadget);
+ udc_controller->gadget.dev.driver = 0;
+ udc_controller->driver = 0;
+ return retval;
+ }
+ }
+ } else {
+ /* Enable DR IRQ reg and set USBCMD reg Run bit */
+ dr_controller_run(udc_controller);
+ udc_controller->usb_state = USB_STATE_ATTACHED;
+ udc_controller->ep0_state = WAIT_FOR_SETUP;
+ udc_controller->ep0_dir = 0;
+ }
printk(KERN_INFO "%s: bind to driver %s\n",
udc_controller->gadget.name, driver->driver.name);
@@ -2044,16 +2214,18 @@
next += t;
#ifndef CONFIG_ARCH_MXC
- tmp_reg = usb_sys_regs->snoop1;
- t = scnprintf(next, size, "Snoop1 Reg : = [0x%x]\n\n", tmp_reg);
- size -= t;
- next += t;
+ if (udc->pdata->have_sysif_regs) {
+ tmp_reg = usb_sys_regs->snoop1;
+ t = scnprintf(next, size, "Snoop1 Reg : = [0x%x]\n\n", tmp_reg);
+ size -= t;
+ next += t;
- tmp_reg = usb_sys_regs->control;
- t = scnprintf(next, size, "General Control Reg : = [0x%x]\n\n",
- tmp_reg);
- size -= t;
- next += t;
+ tmp_reg = usb_sys_regs->control;
+ t = scnprintf(next, size, "General Control Reg : = [0x%x]\n\n",
+ tmp_reg);
+ size -= t;
+ next += t;
+ }
#endif
/* ------fsl_udc, fsl_ep, fsl_request structure information ----- */
@@ -2233,6 +2405,7 @@
*/
static int __init fsl_udc_probe(struct platform_device *pdev)
{
+ struct fsl_usb2_platform_data *pdata;
struct resource *res;
int ret = -ENODEV;
unsigned int i;
@@ -2249,20 +2422,35 @@
return -ENOMEM;
}
+ pdata = pdev->dev.platform_data;
+ udc_controller->pdata = pdata;
spin_lock_init(&udc_controller->lock);
udc_controller->stopped = 1;
+#ifdef CONFIG_USB_OTG
+ if (pdata->operating_mode == FSL_USB2_DR_OTG) {
+ udc_controller->transceiver = otg_get_transceiver();
+ if (!udc_controller->transceiver) {
+ ERR("Can't find OTG driver!\n");
+ ret = -ENODEV;
+ goto err_kfree;
+ }
+ }
+#endif
+
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
ret = -ENXIO;
goto err_kfree;
}
- if (!request_mem_region(res->start, res->end - res->start + 1,
- driver_name)) {
- ERR("request mem region for %s failed\n", pdev->name);
- ret = -EBUSY;
- goto err_kfree;
+ if (pdata->operating_mode == FSL_USB2_DR_DEVICE) {
+ if (!request_mem_region(res->start, res->end - res->start + 1,
+ driver_name)) {
+ ERR("request mem region for %s failed\n", pdev->name);
+ ret = -EBUSY;
+ goto err_kfree;
+ }
}
dr_regs = ioremap(res->start, resource_size(res));
@@ -2271,9 +2459,29 @@
goto err_release_mem_region;
}
+ pdata->regs = (void *)dr_regs;
+
+ /*
+ * do platform specific init: check the clock, grab/config pins, etc.
+ */
+ if (pdata->init && pdata->init(pdev)) {
+ ret = -ENODEV;
+ goto err_iounmap_noclk;
+ }
+
+ /* Set accessors only after pdata->init() ! */
+ if (pdata->big_endian_mmio) {
+ _fsl_readl = _fsl_readl_be;
+ _fsl_writel = _fsl_writel_be;
+ } else {
+ _fsl_readl = _fsl_readl_le;
+ _fsl_writel = _fsl_writel_le;
+ }
+
#ifndef CONFIG_ARCH_MXC
- usb_sys_regs = (struct usb_sys_interface *)
- ((u32)dr_regs + USB_DR_SYS_OFFSET);
+ if (pdata->have_sysif_regs)
+ usb_sys_regs = (struct usb_sys_interface *)
+ ((u32)dr_regs + USB_DR_SYS_OFFSET);
#endif
/* Initialize USB clocks */
@@ -2313,9 +2521,11 @@
goto err_free_irq;
}
- /* initialize usb hw reg except for regs for EP,
- * leave usbintr reg untouched */
- dr_controller_setup(udc_controller);
+ if (!udc_controller->transceiver) {
+ /* initialize usb hw reg except for regs for EP,
+ * leave usbintr reg untouched */
+ dr_controller_setup(udc_controller);
+ }
fsl_udc_clk_finalize(pdev);
@@ -2335,6 +2545,9 @@
if (ret < 0)
goto err_free_irq;
+ if (udc_controller->transceiver)
+ udc_controller->gadget.is_otg = 1;
+
/* setup QH and epctrl for ep0 */
ep0_setup(udc_controller);
@@ -2373,11 +2586,14 @@
err_free_irq:
free_irq(udc_controller->irq, udc_controller);
err_iounmap:
+ if (pdata->exit)
+ pdata->exit(pdev);
fsl_udc_clk_release();
err_iounmap_noclk:
iounmap(dr_regs);
err_release_mem_region:
- release_mem_region(res->start, res->end - res->start + 1);
+ if (pdata->operating_mode == FSL_USB2_DR_DEVICE)
+ release_mem_region(res->start, res->end - res->start + 1);
err_kfree:
kfree(udc_controller);
udc_controller = NULL;
@@ -2390,6 +2606,7 @@
static int __exit fsl_udc_remove(struct platform_device *pdev)
{
struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
DECLARE_COMPLETION(done);
@@ -2410,12 +2627,20 @@
dma_pool_destroy(udc_controller->td_pool);
free_irq(udc_controller->irq, udc_controller);
iounmap(dr_regs);
- release_mem_region(res->start, res->end - res->start + 1);
+ if (pdata->operating_mode == FSL_USB2_DR_DEVICE)
+ release_mem_region(res->start, res->end - res->start + 1);
device_unregister(&udc_controller->gadget.dev);
/* free udc --wait for the release() finished */
wait_for_completion(&done);
+ /*
+ * do platform specific un-initialization:
+ * release iomux pins, etc.
+ */
+ if (pdata->exit)
+ pdata->exit(pdev);
+
return 0;
}
@@ -2446,6 +2671,62 @@
return 0;
}
+static int fsl_udc_otg_suspend(struct device *dev, pm_message_t state)
+{
+ struct fsl_udc *udc = udc_controller;
+ u32 mode, usbcmd;
+
+ mode = fsl_readl(&dr_regs->usbmode) & USB_MODE_CTRL_MODE_MASK;
+
+ pr_debug("%s(): mode 0x%x stopped %d\n", __func__, mode, udc->stopped);
+
+ /*
+ * If the controller is already stopped, then this must be a
+ * PM suspend. Remember this fact, so that we will leave the
+ * controller stopped at PM resume time.
+ */
+ if (udc->stopped) {
+ pr_debug("gadget already stopped, leaving early\n");
+ udc->already_stopped = 1;
+ return 0;
+ }
+
+ if (mode != USB_MODE_CTRL_MODE_DEVICE) {
+ pr_debug("gadget not in device mode, leaving early\n");
+ return 0;
+ }
+
+ /* stop the controller */
+ usbcmd = fsl_readl(&dr_regs->usbcmd) & ~USB_CMD_RUN_STOP;
+ fsl_writel(usbcmd, &dr_regs->usbcmd);
+
+ udc->stopped = 1;
+
+ pr_info("USB Gadget suspended\n");
+
+ return 0;
+}
+
+static int fsl_udc_otg_resume(struct device *dev)
+{
+ pr_debug("%s(): stopped %d already_stopped %d\n", __func__,
+ udc_controller->stopped, udc_controller->already_stopped);
+
+ /*
+ * If the controller was stopped at suspend time, then
+ * don't resume it now.
+ */
+ if (udc_controller->already_stopped) {
+ udc_controller->already_stopped = 0;
+ pr_debug("gadget was already stopped, leaving early\n");
+ return 0;
+ }
+
+ pr_info("USB Gadget resume\n");
+
+ return fsl_udc_resume(NULL);
+}
+
/*-------------------------------------------------------------------------
Register entry point for the peripheral controller driver
--------------------------------------------------------------------------*/
@@ -2458,6 +2739,9 @@
.driver = {
.name = (char *)driver_name,
.owner = THIS_MODULE,
+ /* udc suspend/resume called from OTG driver */
+ .suspend = fsl_udc_otg_suspend,
+ .resume = fsl_udc_otg_resume,
},
};
diff --git a/drivers/usb/gadget/fsl_usb2_udc.h b/drivers/usb/gadget/fsl_usb2_udc.h
index e88cce5..1d51be8 100644
--- a/drivers/usb/gadget/fsl_usb2_udc.h
+++ b/drivers/usb/gadget/fsl_usb2_udc.h
@@ -275,7 +275,9 @@
#define USB_MODE_CTRL_MODE_IDLE 0x00000000
#define USB_MODE_CTRL_MODE_DEVICE 0x00000002
#define USB_MODE_CTRL_MODE_HOST 0x00000003
+#define USB_MODE_CTRL_MODE_MASK 0x00000003
#define USB_MODE_CTRL_MODE_RSV 0x00000001
+#define USB_MODE_ES 0x00000004 /* Endian Select */
#define USB_MODE_SETUP_LOCK_OFF 0x00000008
#define USB_MODE_STREAM_DISABLE 0x00000010
/* Endpoint Flush Register */
@@ -461,6 +463,7 @@
struct fsl_udc {
struct usb_gadget gadget;
struct usb_gadget_driver *driver;
+ struct fsl_usb2_platform_data *pdata;
struct completion *done; /* to make sure release() is done */
struct fsl_ep *eps;
unsigned int max_ep;
@@ -473,6 +476,8 @@
unsigned vbus_active:1;
unsigned stopped:1;
unsigned remote_wakeup:1;
+ unsigned already_stopped:1;
+ unsigned big_endian_desc:1;
struct ep_queue_head *ep_qh; /* Endpoints Queue-Head */
struct fsl_req *status_req; /* ep0 status request */
@@ -483,6 +488,7 @@
dma_addr_t ep_qh_dma; /* dma address of QH */
u32 max_pipes; /* Device max pipes */
+ u32 bus_reset; /* Device is bus resetting */
u32 resume_state; /* USB state to resume */
u32 usb_state; /* USB current state */
u32 ep0_state; /* Endpoint zero state */
diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h
index e896f63..bcdac7c 100644
--- a/drivers/usb/gadget/gadget_chips.h
+++ b/drivers/usb/gadget/gadget_chips.h
@@ -136,6 +136,12 @@
#define gadget_is_s3c_hsotg(g) 0
#endif
+#ifdef CONFIG_USB_S3C_HSUDC
+#define gadget_is_s3c_hsudc(g) (!strcmp("s3c-hsudc", (g)->name))
+#else
+#define gadget_is_s3c_hsudc(g) 0
+#endif
+
#ifdef CONFIG_USB_GADGET_EG20T
#define gadget_is_pch(g) (!strcmp("pch_udc", (g)->name))
#else
@@ -148,6 +154,12 @@
#define gadget_is_ci13xxx_msm(g) 0
#endif
+#ifdef CONFIG_USB_GADGET_RENESAS_USBHS
+#define gadget_is_renesas_usbhs(g) (!strcmp("renesas_usbhs_udc", (g)->name))
+#else
+#define gadget_is_renesas_usbhs(g) 0
+#endif
+
/**
* usb_gadget_controller_number - support bcdDevice id convention
* @gadget: the controller being driven
@@ -207,6 +219,11 @@
return 0x27;
else if (gadget_is_ci13xxx_msm(gadget))
return 0x28;
+ else if (gadget_is_renesas_usbhs(gadget))
+ return 0x29;
+ else if (gadget_is_s3c_hsudc(gadget))
+ return 0x30;
+
return -ENOENT;
}
diff --git a/drivers/usb/gadget/printer.c b/drivers/usb/gadget/printer.c
index c3f2bd4..271ef94 100644
--- a/drivers/usb/gadget/printer.c
+++ b/drivers/usb/gadget/printer.c
@@ -1189,6 +1189,8 @@
else if (gadget->a_alt_hnp_support)
DBG(dev, "HNP needs a different root port\n");
value = printer_set_config(dev, wValue);
+ if (!value)
+ value = set_interface(dev, PRINTER_INTERFACE);
break;
case USB_REQ_GET_CONFIGURATION:
if (ctrl->bRequestType != USB_DIR_IN)
diff --git a/drivers/usb/gadget/s3c-hsotg.c b/drivers/usb/gadget/s3c-hsotg.c
index 0912679..acb9cc4 100644
--- a/drivers/usb/gadget/s3c-hsotg.c
+++ b/drivers/usb/gadget/s3c-hsotg.c
@@ -1,5 +1,8 @@
/* linux/drivers/usb/gadget/s3c-hsotg.c
*
+ * Copyright (c) 2011 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com
+ *
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk>
@@ -613,11 +616,10 @@
maxpkt = S3C_DxEPTSIZ_PktCnt_LIMIT + 1;
} else {
maxsize = 64+64;
- if (hs_ep->dir_in) {
+ if (hs_ep->dir_in)
maxpkt = S3C_DIEPTSIZ0_PktCnt_LIMIT + 1;
- } else {
+ else
maxpkt = 2;
- }
}
/* we made the constant loading easier above by using +1 */
@@ -679,6 +681,14 @@
__func__, readl(hsotg->regs + epctrl_reg), index,
hs_ep->dir_in ? "in" : "out");
+ /* If endpoint is stalled, we will restart request later */
+ ctrl = readl(hsotg->regs + epctrl_reg);
+
+ if (ctrl & S3C_DxEPCTL_Stall) {
+ dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
+ return;
+ }
+
length = ureq->length - ureq->actual;
if (0)
@@ -731,18 +741,6 @@
/* write size / packets */
writel(epsize, hsotg->regs + epsize_reg);
- ctrl = readl(hsotg->regs + epctrl_reg);
-
- if (ctrl & S3C_DxEPCTL_Stall) {
- dev_warn(hsotg->dev, "%s: ep%d is stalled\n", __func__, index);
-
- /* not sure what we can do here, if it is EP0 then we should
- * get this cleared once the endpoint has transmitted the
- * STALL packet, otherwise it needs to be cleared by the
- * host.
- */
- }
-
if (using_dma(hsotg)) {
unsigned int dma_reg;
@@ -1048,6 +1046,20 @@
static int s3c_hsotg_ep_sethalt(struct usb_ep *ep, int value);
/**
+ * get_ep_head - return the first request on the endpoint
+ * @hs_ep: The controller endpoint to get
+ *
+ * Get the first request on the endpoint.
+ */
+static struct s3c_hsotg_req *get_ep_head(struct s3c_hsotg_ep *hs_ep)
+{
+ if (list_empty(&hs_ep->queue))
+ return NULL;
+
+ return list_first_entry(&hs_ep->queue, struct s3c_hsotg_req, queue);
+}
+
+/**
* s3c_hsotg_process_req_featire - process request {SET,CLEAR}_FEATURE
* @hsotg: The device state
* @ctrl: USB control request
@@ -1055,8 +1067,12 @@
static int s3c_hsotg_process_req_feature(struct s3c_hsotg *hsotg,
struct usb_ctrlrequest *ctrl)
{
+ struct s3c_hsotg_ep *ep0 = &hsotg->eps[0];
+ struct s3c_hsotg_req *hs_req;
+ bool restart;
bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
struct s3c_hsotg_ep *ep;
+ int ret;
dev_dbg(hsotg->dev, "%s: %s_FEATURE\n",
__func__, set ? "SET" : "CLEAR");
@@ -1072,6 +1088,36 @@
switch (le16_to_cpu(ctrl->wValue)) {
case USB_ENDPOINT_HALT:
s3c_hsotg_ep_sethalt(&ep->ep, set);
+
+ ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0);
+ if (ret) {
+ dev_err(hsotg->dev,
+ "%s: failed to send reply\n", __func__);
+ return ret;
+ }
+
+ if (!set) {
+ /*
+ * If we have request in progress,
+ * then complete it
+ */
+ if (ep->req) {
+ hs_req = ep->req;
+ ep->req = NULL;
+ list_del_init(&hs_req->queue);
+ hs_req->req.complete(&ep->ep,
+ &hs_req->req);
+ }
+
+ /* If we have pending request, then start it */
+ restart = !list_empty(&ep->queue);
+ if (restart) {
+ hs_req = get_ep_head(ep);
+ s3c_hsotg_start_req(hsotg, ep,
+ hs_req, false);
+ }
+ }
+
break;
default:
@@ -1148,14 +1194,6 @@
dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
}
- if (ret > 0) {
- if (!ep0->dir_in) {
- /* need to generate zlp in reply or take data */
- /* todo - deal with any data we might be sent? */
- ret = s3c_hsotg_send_reply(hsotg, ep0, NULL, 0);
- }
- }
-
/* the request is either unhandlable, or is not formatted correctly
* so respond with a STALL for the status stage to indicate failure.
*/
@@ -1247,20 +1285,6 @@
}
/**
- * get_ep_head - return the first request on the endpoint
- * @hs_ep: The controller endpoint to get
- *
- * Get the first request on the endpoint.
-*/
-static struct s3c_hsotg_req *get_ep_head(struct s3c_hsotg_ep *hs_ep)
-{
- if (list_empty(&hs_ep->queue))
- return NULL;
-
- return list_first_entry(&hs_ep->queue, struct s3c_hsotg_req, queue);
-}
-
-/**
* s3c_hsotg_complete_request - complete a request given to us
* @hsotg: The device state.
* @hs_ep: The endpoint the request was on.
@@ -1683,6 +1707,37 @@
dev_err(hsotg->dev, "ep%d: bad mps of %d\n", ep, mps);
}
+/**
+ * s3c_hsotg_txfifo_flush - flush Tx FIFO
+ * @hsotg: The driver state
+ * @idx: The index for the endpoint (0..15)
+ */
+static void s3c_hsotg_txfifo_flush(struct s3c_hsotg *hsotg, unsigned int idx)
+{
+ int timeout;
+ int val;
+
+ writel(S3C_GRSTCTL_TxFNum(idx) | S3C_GRSTCTL_TxFFlsh,
+ hsotg->regs + S3C_GRSTCTL);
+
+ /* wait until the fifo is flushed */
+ timeout = 100;
+
+ while (1) {
+ val = readl(hsotg->regs + S3C_GRSTCTL);
+
+ if ((val & (S3C_GRSTCTL_TxFFlsh)) == 0)
+ break;
+
+ if (--timeout == 0) {
+ dev_err(hsotg->dev,
+ "%s: timeout flushing fifo (GRSTCTL=%08x)\n",
+ __func__, val);
+ }
+
+ udelay(1);
+ }
+}
/**
* s3c_hsotg_trytx - check to see if anything needs transmitting
@@ -1775,10 +1830,12 @@
u32 epctl_reg = dir_in ? S3C_DIEPCTL(idx) : S3C_DOEPCTL(idx);
u32 epsiz_reg = dir_in ? S3C_DIEPTSIZ(idx) : S3C_DOEPTSIZ(idx);
u32 ints;
- u32 clear = 0;
ints = readl(hsotg->regs + epint_reg);
+ /* Clear endpoint interrupts */
+ writel(ints, hsotg->regs + epint_reg);
+
dev_dbg(hsotg->dev, "%s: ep%d(%s) DxEPINT=0x%08x\n",
__func__, idx, dir_in ? "in" : "out", ints);
@@ -1801,19 +1858,28 @@
s3c_hsotg_handle_outdone(hsotg, idx, false);
}
-
- clear |= S3C_DxEPINT_XferCompl;
}
if (ints & S3C_DxEPINT_EPDisbld) {
dev_dbg(hsotg->dev, "%s: EPDisbld\n", __func__);
- clear |= S3C_DxEPINT_EPDisbld;
+
+ if (dir_in) {
+ int epctl = readl(hsotg->regs + epctl_reg);
+
+ s3c_hsotg_txfifo_flush(hsotg, idx);
+
+ if ((epctl & S3C_DxEPCTL_Stall) &&
+ (epctl & S3C_DxEPCTL_EPType_Bulk)) {
+ int dctl = readl(hsotg->regs + S3C_DCTL);
+
+ dctl |= S3C_DCTL_CGNPInNAK;
+ writel(dctl, hsotg->regs + S3C_DCTL);
+ }
+ }
}
- if (ints & S3C_DxEPINT_AHBErr) {
+ if (ints & S3C_DxEPINT_AHBErr)
dev_dbg(hsotg->dev, "%s: AHBErr\n", __func__);
- clear |= S3C_DxEPINT_AHBErr;
- }
if (ints & S3C_DxEPINT_Setup) { /* Setup or Timeout */
dev_dbg(hsotg->dev, "%s: Setup/Timeout\n", __func__);
@@ -1829,14 +1895,10 @@
else
s3c_hsotg_handle_outdone(hsotg, 0, true);
}
-
- clear |= S3C_DxEPINT_Setup;
}
- if (ints & S3C_DxEPINT_Back2BackSetup) {
+ if (ints & S3C_DxEPINT_Back2BackSetup)
dev_dbg(hsotg->dev, "%s: B2BSetup/INEPNakEff\n", __func__);
- clear |= S3C_DxEPINT_Back2BackSetup;
- }
if (dir_in) {
/* not sure if this is important, but we'll clear it anyway
@@ -1844,14 +1906,12 @@
if (ints & S3C_DIEPMSK_INTknTXFEmpMsk) {
dev_dbg(hsotg->dev, "%s: ep%d: INTknTXFEmpMsk\n",
__func__, idx);
- clear |= S3C_DIEPMSK_INTknTXFEmpMsk;
}
/* this probably means something bad is happening */
if (ints & S3C_DIEPMSK_INTknEPMisMsk) {
dev_warn(hsotg->dev, "%s: ep%d: INTknEP\n",
__func__, idx);
- clear |= S3C_DIEPMSK_INTknEPMisMsk;
}
/* FIFO has space or is empty (see GAHBCFG) */
@@ -1860,11 +1920,8 @@
dev_dbg(hsotg->dev, "%s: ep%d: TxFIFOEmpty\n",
__func__, idx);
s3c_hsotg_trytx(hsotg, hs_ep);
- clear |= S3C_DIEPMSK_TxFIFOEmpty;
}
}
-
- writel(clear, hsotg->regs + epint_reg);
}
/**
@@ -2056,7 +2113,6 @@
dev_info(hsotg->dev, "OTGInt: %08x\n", otgint);
writel(otgint, hsotg->regs + S3C_GOTGINT);
- writel(S3C_GINTSTS_OTGInt, hsotg->regs + S3C_GINTSTS);
}
if (gintsts & S3C_GINTSTS_DisconnInt) {
@@ -2072,8 +2128,9 @@
}
if (gintsts & S3C_GINTSTS_EnumDone) {
- s3c_hsotg_irq_enumdone(hsotg);
writel(S3C_GINTSTS_EnumDone, hsotg->regs + S3C_GINTSTS);
+
+ s3c_hsotg_irq_enumdone(hsotg);
}
if (gintsts & S3C_GINTSTS_ConIDStsChng) {
@@ -2101,10 +2158,6 @@
if (daint_in & 1)
s3c_hsotg_epint(hsotg, ep, 1);
}
-
- writel(daint, hsotg->regs + S3C_DAINT);
- writel(gintsts & (S3C_GINTSTS_OEPInt | S3C_GINTSTS_IEPInt),
- hsotg->regs + S3C_GINTSTS);
}
if (gintsts & S3C_GINTSTS_USBRst) {
@@ -2112,6 +2165,8 @@
dev_dbg(hsotg->dev, "GNPTXSTS=%08x\n",
readl(hsotg->regs + S3C_GNPTXSTS));
+ writel(S3C_GINTSTS_USBRst, hsotg->regs + S3C_GINTSTS);
+
kill_all_requests(hsotg, &hsotg->eps[0], -ECONNRESET, true);
/* it seems after a reset we can end up with a situation
@@ -2123,8 +2178,6 @@
s3c_hsotg_init_fifo(hsotg);
s3c_hsotg_enqueue_setup(hsotg);
-
- writel(S3C_GINTSTS_USBRst, hsotg->regs + S3C_GINTSTS);
}
/* check both FIFOs */
@@ -2138,8 +2191,6 @@
s3c_hsotg_disable_gsint(hsotg, S3C_GINTSTS_NPTxFEmp);
s3c_hsotg_irq_fifoempty(hsotg, false);
-
- writel(S3C_GINTSTS_NPTxFEmp, hsotg->regs + S3C_GINTSTS);
}
if (gintsts & S3C_GINTSTS_PTxFEmp) {
@@ -2149,8 +2200,6 @@
s3c_hsotg_disable_gsint(hsotg, S3C_GINTSTS_PTxFEmp);
s3c_hsotg_irq_fifoempty(hsotg, true);
-
- writel(S3C_GINTSTS_PTxFEmp, hsotg->regs + S3C_GINTSTS);
}
if (gintsts & S3C_GINTSTS_RxFLvl) {
@@ -2159,7 +2208,6 @@
* set. */
s3c_hsotg_handle_rx(hsotg);
- writel(S3C_GINTSTS_RxFLvl, hsotg->regs + S3C_GINTSTS);
}
if (gintsts & S3C_GINTSTS_ModeMis) {
@@ -2193,19 +2241,17 @@
if (gintsts & S3C_GINTSTS_GOUTNakEff) {
dev_info(hsotg->dev, "GOUTNakEff triggered\n");
- s3c_hsotg_dump(hsotg);
-
writel(S3C_DCTL_CGOUTNak, hsotg->regs + S3C_DCTL);
- writel(S3C_GINTSTS_GOUTNakEff, hsotg->regs + S3C_GINTSTS);
+
+ s3c_hsotg_dump(hsotg);
}
if (gintsts & S3C_GINTSTS_GINNakEff) {
dev_info(hsotg->dev, "GINNakEff triggered\n");
- s3c_hsotg_dump(hsotg);
-
writel(S3C_DCTL_CGNPInNAK, hsotg->regs + S3C_DCTL);
- writel(S3C_GINTSTS_GINNakEff, hsotg->regs + S3C_GINTSTS);
+
+ s3c_hsotg_dump(hsotg);
}
/* if we've had fifo events, we should try and go around the
@@ -2403,11 +2449,6 @@
dev_info(hs->dev, "ep_dequeue(%p,%p)\n", ep, req);
- if (hs_req == hs_ep->req) {
- dev_dbg(hs->dev, "%s: already in progress\n", __func__);
- return -EINPROGRESS;
- }
-
spin_lock_irqsave(&hs_ep->lock, flags);
if (!on_list(hs_ep, hs_req)) {
@@ -2429,6 +2470,7 @@
unsigned long irqflags;
u32 epreg;
u32 epctl;
+ u32 xfertype;
dev_info(hs->dev, "%s(ep %p %s, %d)\n", __func__, ep, ep->name, value);
@@ -2439,10 +2481,17 @@
epreg = S3C_DIEPCTL(index);
epctl = readl(hs->regs + epreg);
- if (value)
- epctl |= S3C_DxEPCTL_Stall;
- else
+ if (value) {
+ epctl |= S3C_DxEPCTL_Stall + S3C_DxEPCTL_SNAK;
+ if (epctl & S3C_DxEPCTL_EPEna)
+ epctl |= S3C_DxEPCTL_EPDis;
+ } else {
epctl &= ~S3C_DxEPCTL_Stall;
+ xfertype = epctl & S3C_DxEPCTL_EPType_MASK;
+ if (xfertype == S3C_DxEPCTL_EPType_Bulk ||
+ xfertype == S3C_DxEPCTL_EPType_Intterupt)
+ epctl |= S3C_DxEPCTL_SetD0PID;
+ }
writel(epctl, hs->regs + epreg);
@@ -2451,8 +2500,13 @@
if (value)
epctl |= S3C_DxEPCTL_Stall;
- else
+ else {
epctl &= ~S3C_DxEPCTL_Stall;
+ xfertype = epctl & S3C_DxEPCTL_EPType_MASK;
+ if (xfertype == S3C_DxEPCTL_EPType_Bulk ||
+ xfertype == S3C_DxEPCTL_EPType_Intterupt)
+ epctl |= S3C_DxEPCTL_SetD0PID;
+ }
writel(epctl, hs->regs + epreg);
@@ -2491,9 +2545,9 @@
timeout = 1000;
do {
grstctl = readl(hsotg->regs + S3C_GRSTCTL);
- } while (!(grstctl & S3C_GRSTCTL_CSftRst) && timeout-- > 0);
+ } while ((grstctl & S3C_GRSTCTL_CSftRst) && timeout-- > 0);
- if (!(grstctl & S3C_GRSTCTL_CSftRst)) {
+ if (grstctl & S3C_GRSTCTL_CSftRst) {
dev_err(hsotg->dev, "Failed to get CSftRst asserted\n");
return -EINVAL;
}
@@ -2510,13 +2564,10 @@
return -ETIMEDOUT;
}
- if (grstctl & S3C_GRSTCTL_CSftRst)
- continue;
-
if (!(grstctl & S3C_GRSTCTL_AHBIdle))
continue;
- break; /* reset done */
+ break; /* reset done */
}
dev_dbg(hsotg->dev, "reset successful\n");
@@ -2588,6 +2639,12 @@
writel(1 << 18 | S3C_DCFG_DevSpd_HS, hsotg->regs + S3C_DCFG);
+ /* Clear any pending OTG interrupts */
+ writel(0xffffffff, hsotg->regs + S3C_GOTGINT);
+
+ /* Clear any pending interrupts */
+ writel(0xffffffff, hsotg->regs + S3C_GINTSTS);
+
writel(S3C_GINTSTS_DisconnInt | S3C_GINTSTS_SessReqInt |
S3C_GINTSTS_ConIDStsChng | S3C_GINTSTS_USBRst |
S3C_GINTSTS_EnumDone | S3C_GINTSTS_OTGInt |
@@ -3261,7 +3318,7 @@
hsotg->clk = clk_get(&pdev->dev, "otg");
if (IS_ERR(hsotg->clk)) {
dev_err(dev, "cannot get otg clock\n");
- ret = -EINVAL;
+ ret = PTR_ERR(hsotg->clk);
goto err_mem;
}
diff --git a/drivers/usb/gadget/s3c-hsudc.c b/drivers/usb/gadget/s3c-hsudc.c
new file mode 100644
index 0000000..cfe3cf5
--- /dev/null
+++ b/drivers/usb/gadget/s3c-hsudc.c
@@ -0,0 +1,1349 @@
+/* linux/drivers/usb/gadget/s3c-hsudc.c
+ *
+ * Copyright (c) 2010 Samsung Electronics Co., Ltd.
+ * http://www.samsung.com/
+ *
+ * S3C24XX USB 2.0 High-speed USB controller gadget driver
+ *
+ * The S3C24XX USB 2.0 high-speed USB controller supports upto 9 endpoints.
+ * Each endpoint can be configured as either in or out endpoint. Endpoints
+ * can be configured for Bulk or Interrupt transfer mode.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/spinlock.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/clk.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+
+#include <mach/regs-s3c2443-clock.h>
+#include <plat/udc.h>
+
+#define S3C_HSUDC_REG(x) (x)
+
+/* Non-Indexed Registers */
+#define S3C_IR S3C_HSUDC_REG(0x00) /* Index Register */
+#define S3C_EIR S3C_HSUDC_REG(0x04) /* EP Intr Status */
+#define S3C_EIR_EP0 (1<<0)
+#define S3C_EIER S3C_HSUDC_REG(0x08) /* EP Intr Enable */
+#define S3C_FAR S3C_HSUDC_REG(0x0c) /* Gadget Address */
+#define S3C_FNR S3C_HSUDC_REG(0x10) /* Frame Number */
+#define S3C_EDR S3C_HSUDC_REG(0x14) /* EP Direction */
+#define S3C_TR S3C_HSUDC_REG(0x18) /* Test Register */
+#define S3C_SSR S3C_HSUDC_REG(0x1c) /* System Status */
+#define S3C_SSR_DTZIEN_EN (0xff8f)
+#define S3C_SSR_ERR (0xff80)
+#define S3C_SSR_VBUSON (1 << 8)
+#define S3C_SSR_HSP (1 << 4)
+#define S3C_SSR_SDE (1 << 3)
+#define S3C_SSR_RESUME (1 << 2)
+#define S3C_SSR_SUSPEND (1 << 1)
+#define S3C_SSR_RESET (1 << 0)
+#define S3C_SCR S3C_HSUDC_REG(0x20) /* System Control */
+#define S3C_SCR_DTZIEN_EN (1 << 14)
+#define S3C_SCR_RRD_EN (1 << 5)
+#define S3C_SCR_SUS_EN (1 << 1)
+#define S3C_SCR_RST_EN (1 << 0)
+#define S3C_EP0SR S3C_HSUDC_REG(0x24) /* EP0 Status */
+#define S3C_EP0SR_EP0_LWO (1 << 6)
+#define S3C_EP0SR_STALL (1 << 4)
+#define S3C_EP0SR_TX_SUCCESS (1 << 1)
+#define S3C_EP0SR_RX_SUCCESS (1 << 0)
+#define S3C_EP0CR S3C_HSUDC_REG(0x28) /* EP0 Control */
+#define S3C_BR(_x) S3C_HSUDC_REG(0x60 + (_x * 4))
+
+/* Indexed Registers */
+#define S3C_ESR S3C_HSUDC_REG(0x2c) /* EPn Status */
+#define S3C_ESR_FLUSH (1 << 6)
+#define S3C_ESR_STALL (1 << 5)
+#define S3C_ESR_LWO (1 << 4)
+#define S3C_ESR_PSIF_ONE (1 << 2)
+#define S3C_ESR_PSIF_TWO (2 << 2)
+#define S3C_ESR_TX_SUCCESS (1 << 1)
+#define S3C_ESR_RX_SUCCESS (1 << 0)
+#define S3C_ECR S3C_HSUDC_REG(0x30) /* EPn Control */
+#define S3C_ECR_DUEN (1 << 7)
+#define S3C_ECR_FLUSH (1 << 6)
+#define S3C_ECR_STALL (1 << 1)
+#define S3C_ECR_IEMS (1 << 0)
+#define S3C_BRCR S3C_HSUDC_REG(0x34) /* Read Count */
+#define S3C_BWCR S3C_HSUDC_REG(0x38) /* Write Count */
+#define S3C_MPR S3C_HSUDC_REG(0x3c) /* Max Pkt Size */
+
+#define WAIT_FOR_SETUP (0)
+#define DATA_STATE_XMIT (1)
+#define DATA_STATE_RECV (2)
+
+/**
+ * struct s3c_hsudc_ep - Endpoint representation used by driver.
+ * @ep: USB gadget layer representation of device endpoint.
+ * @name: Endpoint name (as required by ep autoconfiguration).
+ * @dev: Reference to the device controller to which this EP belongs.
+ * @desc: Endpoint descriptor obtained from the gadget driver.
+ * @queue: Transfer request queue for the endpoint.
+ * @stopped: Maintains state of endpoint, set if EP is halted.
+ * @bEndpointAddress: EP address (including direction bit).
+ * @fifo: Base address of EP FIFO.
+ */
+struct s3c_hsudc_ep {
+ struct usb_ep ep;
+ char name[20];
+ struct s3c_hsudc *dev;
+ const struct usb_endpoint_descriptor *desc;
+ struct list_head queue;
+ u8 stopped;
+ u8 wedge;
+ u8 bEndpointAddress;
+ void __iomem *fifo;
+};
+
+/**
+ * struct s3c_hsudc_req - Driver encapsulation of USB gadget transfer request.
+ * @req: Reference to USB gadget transfer request.
+ * @queue: Used for inserting this request to the endpoint request queue.
+ */
+struct s3c_hsudc_req {
+ struct usb_request req;
+ struct list_head queue;
+};
+
+/**
+ * struct s3c_hsudc - Driver's abstraction of the device controller.
+ * @gadget: Instance of usb_gadget which is referenced by gadget driver.
+ * @driver: Reference to currenty active gadget driver.
+ * @dev: The device reference used by probe function.
+ * @lock: Lock to synchronize the usage of Endpoints (EP's are indexed).
+ * @regs: Remapped base address of controller's register space.
+ * @mem_rsrc: Device memory resource used for remapping device register space.
+ * irq: IRQ number used by the controller.
+ * uclk: Reference to the controller clock.
+ * ep0state: Current state of EP0.
+ * ep: List of endpoints supported by the controller.
+ */
+struct s3c_hsudc {
+ struct usb_gadget gadget;
+ struct usb_gadget_driver *driver;
+ struct device *dev;
+ struct s3c24xx_hsudc_platdata *pd;
+ spinlock_t lock;
+ void __iomem *regs;
+ struct resource *mem_rsrc;
+ int irq;
+ struct clk *uclk;
+ int ep0state;
+ struct s3c_hsudc_ep ep[];
+};
+
+#define ep_maxpacket(_ep) ((_ep)->ep.maxpacket)
+#define ep_is_in(_ep) ((_ep)->bEndpointAddress & USB_DIR_IN)
+#define ep_index(_ep) ((_ep)->bEndpointAddress & \
+ USB_ENDPOINT_NUMBER_MASK)
+
+static struct s3c_hsudc *the_controller;
+static const char driver_name[] = "s3c-udc";
+static const char ep0name[] = "ep0-control";
+
+static inline struct s3c_hsudc_req *our_req(struct usb_request *req)
+{
+ return container_of(req, struct s3c_hsudc_req, req);
+}
+
+static inline struct s3c_hsudc_ep *our_ep(struct usb_ep *ep)
+{
+ return container_of(ep, struct s3c_hsudc_ep, ep);
+}
+
+static inline struct s3c_hsudc *to_hsudc(struct usb_gadget *gadget)
+{
+ return container_of(gadget, struct s3c_hsudc, gadget);
+}
+
+static inline void set_index(struct s3c_hsudc *hsudc, int ep_addr)
+{
+ ep_addr &= USB_ENDPOINT_NUMBER_MASK;
+ writel(ep_addr, hsudc->regs + S3C_IR);
+}
+
+static inline void __orr32(void __iomem *ptr, u32 val)
+{
+ writel(readl(ptr) | val, ptr);
+}
+
+static void s3c_hsudc_init_phy(void)
+{
+ u32 cfg;
+
+ cfg = readl(S3C2443_PWRCFG) | S3C2443_PWRCFG_USBPHY;
+ writel(cfg, S3C2443_PWRCFG);
+
+ cfg = readl(S3C2443_URSTCON);
+ cfg |= (S3C2443_URSTCON_FUNCRST | S3C2443_URSTCON_PHYRST);
+ writel(cfg, S3C2443_URSTCON);
+ mdelay(1);
+
+ cfg = readl(S3C2443_URSTCON);
+ cfg &= ~(S3C2443_URSTCON_FUNCRST | S3C2443_URSTCON_PHYRST);
+ writel(cfg, S3C2443_URSTCON);
+
+ cfg = readl(S3C2443_PHYCTRL);
+ cfg &= ~(S3C2443_PHYCTRL_CLKSEL | S3C2443_PHYCTRL_DSPORT);
+ cfg |= (S3C2443_PHYCTRL_EXTCLK | S3C2443_PHYCTRL_PLLSEL);
+ writel(cfg, S3C2443_PHYCTRL);
+
+ cfg = readl(S3C2443_PHYPWR);
+ cfg &= ~(S3C2443_PHYPWR_FSUSPEND | S3C2443_PHYPWR_PLL_PWRDN |
+ S3C2443_PHYPWR_XO_ON | S3C2443_PHYPWR_PLL_REFCLK |
+ S3C2443_PHYPWR_ANALOG_PD);
+ cfg |= S3C2443_PHYPWR_COMMON_ON;
+ writel(cfg, S3C2443_PHYPWR);
+
+ cfg = readl(S3C2443_UCLKCON);
+ cfg |= (S3C2443_UCLKCON_DETECT_VBUS | S3C2443_UCLKCON_FUNC_CLKEN |
+ S3C2443_UCLKCON_TCLKEN);
+ writel(cfg, S3C2443_UCLKCON);
+}
+
+static void s3c_hsudc_uninit_phy(void)
+{
+ u32 cfg;
+
+ cfg = readl(S3C2443_PWRCFG) & ~S3C2443_PWRCFG_USBPHY;
+ writel(cfg, S3C2443_PWRCFG);
+
+ writel(S3C2443_PHYPWR_FSUSPEND, S3C2443_PHYPWR);
+
+ cfg = readl(S3C2443_UCLKCON) & ~S3C2443_UCLKCON_FUNC_CLKEN;
+ writel(cfg, S3C2443_UCLKCON);
+}
+
+/**
+ * s3c_hsudc_complete_request - Complete a transfer request.
+ * @hsep: Endpoint to which the request belongs.
+ * @hsreq: Transfer request to be completed.
+ * @status: Transfer completion status for the transfer request.
+ */
+static void s3c_hsudc_complete_request(struct s3c_hsudc_ep *hsep,
+ struct s3c_hsudc_req *hsreq, int status)
+{
+ unsigned int stopped = hsep->stopped;
+ struct s3c_hsudc *hsudc = hsep->dev;
+
+ list_del_init(&hsreq->queue);
+ hsreq->req.status = status;
+
+ if (!ep_index(hsep)) {
+ hsudc->ep0state = WAIT_FOR_SETUP;
+ hsep->bEndpointAddress &= ~USB_DIR_IN;
+ }
+
+ hsep->stopped = 1;
+ spin_unlock(&hsudc->lock);
+ if (hsreq->req.complete != NULL)
+ hsreq->req.complete(&hsep->ep, &hsreq->req);
+ spin_lock(&hsudc->lock);
+ hsep->stopped = stopped;
+}
+
+/**
+ * s3c_hsudc_nuke_ep - Terminate all requests queued for a endpoint.
+ * @hsep: Endpoint for which queued requests have to be terminated.
+ * @status: Transfer completion status for the transfer request.
+ */
+static void s3c_hsudc_nuke_ep(struct s3c_hsudc_ep *hsep, int status)
+{
+ struct s3c_hsudc_req *hsreq;
+
+ while (!list_empty(&hsep->queue)) {
+ hsreq = list_entry(hsep->queue.next,
+ struct s3c_hsudc_req, queue);
+ s3c_hsudc_complete_request(hsep, hsreq, status);
+ }
+}
+
+/**
+ * s3c_hsudc_stop_activity - Stop activity on all endpoints.
+ * @hsudc: Device controller for which EP activity is to be stopped.
+ * @driver: Reference to the gadget driver which is currently active.
+ *
+ * All the endpoints are stopped and any pending transfer requests if any on
+ * the endpoint are terminated.
+ */
+static void s3c_hsudc_stop_activity(struct s3c_hsudc *hsudc,
+ struct usb_gadget_driver *driver)
+{
+ struct s3c_hsudc_ep *hsep;
+ int epnum;
+
+ hsudc->gadget.speed = USB_SPEED_UNKNOWN;
+
+ for (epnum = 0; epnum < hsudc->pd->epnum; epnum++) {
+ hsep = &hsudc->ep[epnum];
+ hsep->stopped = 1;
+ s3c_hsudc_nuke_ep(hsep, -ESHUTDOWN);
+ }
+
+ spin_unlock(&hsudc->lock);
+ driver->disconnect(&hsudc->gadget);
+ spin_lock(&hsudc->lock);
+}
+
+/**
+ * s3c_hsudc_read_setup_pkt - Read the received setup packet from EP0 fifo.
+ * @hsudc: Device controller from which setup packet is to be read.
+ * @buf: The buffer into which the setup packet is read.
+ *
+ * The setup packet received in the EP0 fifo is read and stored into a
+ * given buffer address.
+ */
+
+static void s3c_hsudc_read_setup_pkt(struct s3c_hsudc *hsudc, u16 *buf)
+{
+ int count;
+
+ count = readl(hsudc->regs + S3C_BRCR);
+ while (count--)
+ *buf++ = (u16)readl(hsudc->regs + S3C_BR(0));
+
+ writel(S3C_EP0SR_RX_SUCCESS, hsudc->regs + S3C_EP0SR);
+}
+
+/**
+ * s3c_hsudc_write_fifo - Write next chunk of transfer data to EP fifo.
+ * @hsep: Endpoint to which the data is to be written.
+ * @hsreq: Transfer request from which the next chunk of data is written.
+ *
+ * Write the next chunk of data from a transfer request to the endpoint FIFO.
+ * If the transfer request completes, 1 is returned, otherwise 0 is returned.
+ */
+static int s3c_hsudc_write_fifo(struct s3c_hsudc_ep *hsep,
+ struct s3c_hsudc_req *hsreq)
+{
+ u16 *buf;
+ u32 max = ep_maxpacket(hsep);
+ u32 count, length;
+ bool is_last;
+ void __iomem *fifo = hsep->fifo;
+
+ buf = hsreq->req.buf + hsreq->req.actual;
+ prefetch(buf);
+
+ length = hsreq->req.length - hsreq->req.actual;
+ length = min(length, max);
+ hsreq->req.actual += length;
+
+ writel(length, hsep->dev->regs + S3C_BWCR);
+ for (count = 0; count < length; count += 2)
+ writel(*buf++, fifo);
+
+ if (count != max) {
+ is_last = true;
+ } else {
+ if (hsreq->req.length != hsreq->req.actual || hsreq->req.zero)
+ is_last = false;
+ else
+ is_last = true;
+ }
+
+ if (is_last) {
+ s3c_hsudc_complete_request(hsep, hsreq, 0);
+ return 1;
+ }
+
+ return 0;
+}
+
+/**
+ * s3c_hsudc_read_fifo - Read the next chunk of data from EP fifo.
+ * @hsep: Endpoint from which the data is to be read.
+ * @hsreq: Transfer request to which the next chunk of data read is written.
+ *
+ * Read the next chunk of data from the endpoint FIFO and a write it to the
+ * transfer request buffer. If the transfer request completes, 1 is returned,
+ * otherwise 0 is returned.
+ */
+static int s3c_hsudc_read_fifo(struct s3c_hsudc_ep *hsep,
+ struct s3c_hsudc_req *hsreq)
+{
+ struct s3c_hsudc *hsudc = hsep->dev;
+ u32 csr, offset;
+ u16 *buf, word;
+ u32 buflen, rcnt, rlen;
+ void __iomem *fifo = hsep->fifo;
+ u32 is_short = 0;
+
+ offset = (ep_index(hsep)) ? S3C_ESR : S3C_EP0SR;
+ csr = readl(hsudc->regs + offset);
+ if (!(csr & S3C_ESR_RX_SUCCESS))
+ return -EINVAL;
+
+ buf = hsreq->req.buf + hsreq->req.actual;
+ prefetchw(buf);
+ buflen = hsreq->req.length - hsreq->req.actual;
+
+ rcnt = readl(hsudc->regs + S3C_BRCR);
+ rlen = (csr & S3C_ESR_LWO) ? (rcnt * 2 - 1) : (rcnt * 2);
+
+ hsreq->req.actual += min(rlen, buflen);
+ is_short = (rlen < hsep->ep.maxpacket);
+
+ while (rcnt-- != 0) {
+ word = (u16)readl(fifo);
+ if (buflen) {
+ *buf++ = word;
+ buflen--;
+ } else {
+ hsreq->req.status = -EOVERFLOW;
+ }
+ }
+
+ writel(S3C_ESR_RX_SUCCESS, hsudc->regs + offset);
+
+ if (is_short || hsreq->req.actual == hsreq->req.length) {
+ s3c_hsudc_complete_request(hsep, hsreq, 0);
+ return 1;
+ }
+
+ return 0;
+}
+
+/**
+ * s3c_hsudc_epin_intr - Handle in-endpoint interrupt.
+ * @hsudc - Device controller for which the interrupt is to be handled.
+ * @ep_idx - Endpoint number on which an interrupt is pending.
+ *
+ * Handles interrupt for a in-endpoint. The interrupts that are handled are
+ * stall and data transmit complete interrupt.
+ */
+static void s3c_hsudc_epin_intr(struct s3c_hsudc *hsudc, u32 ep_idx)
+{
+ struct s3c_hsudc_ep *hsep = &hsudc->ep[ep_idx];
+ struct s3c_hsudc_req *hsreq;
+ u32 csr;
+
+ csr = readl((u32)hsudc->regs + S3C_ESR);
+ if (csr & S3C_ESR_STALL) {
+ writel(S3C_ESR_STALL, hsudc->regs + S3C_ESR);
+ return;
+ }
+
+ if (csr & S3C_ESR_TX_SUCCESS) {
+ writel(S3C_ESR_TX_SUCCESS, hsudc->regs + S3C_ESR);
+ if (list_empty(&hsep->queue))
+ return;
+
+ hsreq = list_entry(hsep->queue.next,
+ struct s3c_hsudc_req, queue);
+ if ((s3c_hsudc_write_fifo(hsep, hsreq) == 0) &&
+ (csr & S3C_ESR_PSIF_TWO))
+ s3c_hsudc_write_fifo(hsep, hsreq);
+ }
+}
+
+/**
+ * s3c_hsudc_epout_intr - Handle out-endpoint interrupt.
+ * @hsudc - Device controller for which the interrupt is to be handled.
+ * @ep_idx - Endpoint number on which an interrupt is pending.
+ *
+ * Handles interrupt for a out-endpoint. The interrupts that are handled are
+ * stall, flush and data ready interrupt.
+ */
+static void s3c_hsudc_epout_intr(struct s3c_hsudc *hsudc, u32 ep_idx)
+{
+ struct s3c_hsudc_ep *hsep = &hsudc->ep[ep_idx];
+ struct s3c_hsudc_req *hsreq;
+ u32 csr;
+
+ csr = readl((u32)hsudc->regs + S3C_ESR);
+ if (csr & S3C_ESR_STALL) {
+ writel(S3C_ESR_STALL, hsudc->regs + S3C_ESR);
+ return;
+ }
+
+ if (csr & S3C_ESR_FLUSH) {
+ __orr32(hsudc->regs + S3C_ECR, S3C_ECR_FLUSH);
+ return;
+ }
+
+ if (csr & S3C_ESR_RX_SUCCESS) {
+ if (list_empty(&hsep->queue))
+ return;
+
+ hsreq = list_entry(hsep->queue.next,
+ struct s3c_hsudc_req, queue);
+ if (((s3c_hsudc_read_fifo(hsep, hsreq)) == 0) &&
+ (csr & S3C_ESR_PSIF_TWO))
+ s3c_hsudc_read_fifo(hsep, hsreq);
+ }
+}
+
+/** s3c_hsudc_set_halt - Set or clear a endpoint halt.
+ * @_ep: Endpoint on which halt has to be set or cleared.
+ * @value: 1 for setting halt on endpoint, 0 to clear halt.
+ *
+ * Set or clear endpoint halt. If halt is set, the endpoint is stopped.
+ * If halt is cleared, for in-endpoints, if there are any pending
+ * transfer requests, transfers are started.
+ */
+static int s3c_hsudc_set_halt(struct usb_ep *_ep, int value)
+{
+ struct s3c_hsudc_ep *hsep = our_ep(_ep);
+ struct s3c_hsudc *hsudc = hsep->dev;
+ struct s3c_hsudc_req *hsreq;
+ unsigned long irqflags;
+ u32 ecr;
+ u32 offset;
+
+ if (value && ep_is_in(hsep) && !list_empty(&hsep->queue))
+ return -EAGAIN;
+
+ spin_lock_irqsave(&hsudc->lock, irqflags);
+ set_index(hsudc, ep_index(hsep));
+ offset = (ep_index(hsep)) ? S3C_ECR : S3C_EP0CR;
+ ecr = readl(hsudc->regs + offset);
+
+ if (value) {
+ ecr |= S3C_ECR_STALL;
+ if (ep_index(hsep))
+ ecr |= S3C_ECR_FLUSH;
+ hsep->stopped = 1;
+ } else {
+ ecr &= ~S3C_ECR_STALL;
+ hsep->stopped = hsep->wedge = 0;
+ }
+ writel(ecr, hsudc->regs + offset);
+
+ if (ep_is_in(hsep) && !list_empty(&hsep->queue) && !value) {
+ hsreq = list_entry(hsep->queue.next,
+ struct s3c_hsudc_req, queue);
+ if (hsreq)
+ s3c_hsudc_write_fifo(hsep, hsreq);
+ }
+
+ spin_unlock_irqrestore(&hsudc->lock, irqflags);
+ return 0;
+}
+
+/** s3c_hsudc_set_wedge - Sets the halt feature with the clear requests ignored
+ * @_ep: Endpoint on which wedge has to be set.
+ *
+ * Sets the halt feature with the clear requests ignored.
+ */
+static int s3c_hsudc_set_wedge(struct usb_ep *_ep)
+{
+ struct s3c_hsudc_ep *hsep = our_ep(_ep);
+
+ if (!hsep)
+ return -EINVAL;
+
+ hsep->wedge = 1;
+ return usb_ep_set_halt(_ep);
+}
+
+/** s3c_hsudc_handle_reqfeat - Handle set feature or clear feature requests.
+ * @_ep: Device controller on which the set/clear feature needs to be handled.
+ * @ctrl: Control request as received on the endpoint 0.
+ *
+ * Handle set feature or clear feature control requests on the control endpoint.
+ */
+static int s3c_hsudc_handle_reqfeat(struct s3c_hsudc *hsudc,
+ struct usb_ctrlrequest *ctrl)
+{
+ struct s3c_hsudc_ep *hsep;
+ bool set = (ctrl->bRequest == USB_REQ_SET_FEATURE);
+ u8 ep_num = ctrl->wIndex & USB_ENDPOINT_NUMBER_MASK;
+
+ if (ctrl->bRequestType == USB_RECIP_ENDPOINT) {
+ hsep = &hsudc->ep[ep_num];
+ switch (le16_to_cpu(ctrl->wValue)) {
+ case USB_ENDPOINT_HALT:
+ if (set || (!set && !hsep->wedge))
+ s3c_hsudc_set_halt(&hsep->ep, set);
+ return 0;
+ }
+ }
+
+ return -ENOENT;
+}
+
+/**
+ * s3c_hsudc_process_req_status - Handle get status control request.
+ * @hsudc: Device controller on which get status request has be handled.
+ * @ctrl: Control request as received on the endpoint 0.
+ *
+ * Handle get status control request received on control endpoint.
+ */
+static void s3c_hsudc_process_req_status(struct s3c_hsudc *hsudc,
+ struct usb_ctrlrequest *ctrl)
+{
+ struct s3c_hsudc_ep *hsep0 = &hsudc->ep[0];
+ struct s3c_hsudc_req hsreq;
+ struct s3c_hsudc_ep *hsep;
+ __le16 reply;
+ u8 epnum;
+
+ switch (ctrl->bRequestType & USB_RECIP_MASK) {
+ case USB_RECIP_DEVICE:
+ reply = cpu_to_le16(0);
+ break;
+
+ case USB_RECIP_INTERFACE:
+ reply = cpu_to_le16(0);
+ break;
+
+ case USB_RECIP_ENDPOINT:
+ epnum = le16_to_cpu(ctrl->wIndex) & USB_ENDPOINT_NUMBER_MASK;
+ hsep = &hsudc->ep[epnum];
+ reply = cpu_to_le16(hsep->stopped ? 1 : 0);
+ break;
+ }
+
+ INIT_LIST_HEAD(&hsreq.queue);
+ hsreq.req.length = 2;
+ hsreq.req.buf = &reply;
+ hsreq.req.actual = 0;
+ hsreq.req.complete = NULL;
+ s3c_hsudc_write_fifo(hsep0, &hsreq);
+}
+
+/**
+ * s3c_hsudc_process_setup - Process control request received on endpoint 0.
+ * @hsudc: Device controller on which control request has been received.
+ *
+ * Read the control request received on endpoint 0, decode it and handle
+ * the request.
+ */
+static void s3c_hsudc_process_setup(struct s3c_hsudc *hsudc)
+{
+ struct s3c_hsudc_ep *hsep = &hsudc->ep[0];
+ struct usb_ctrlrequest ctrl = {0};
+ int ret;
+
+ s3c_hsudc_nuke_ep(hsep, -EPROTO);
+ s3c_hsudc_read_setup_pkt(hsudc, (u16 *)&ctrl);
+
+ if (ctrl.bRequestType & USB_DIR_IN) {
+ hsep->bEndpointAddress |= USB_DIR_IN;
+ hsudc->ep0state = DATA_STATE_XMIT;
+ } else {
+ hsep->bEndpointAddress &= ~USB_DIR_IN;
+ hsudc->ep0state = DATA_STATE_RECV;
+ }
+
+ switch (ctrl.bRequest) {
+ case USB_REQ_SET_ADDRESS:
+ if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
+ break;
+ hsudc->ep0state = WAIT_FOR_SETUP;
+ return;
+
+ case USB_REQ_GET_STATUS:
+ if ((ctrl.bRequestType & USB_TYPE_MASK) != USB_TYPE_STANDARD)
+ break;
+ s3c_hsudc_process_req_status(hsudc, &ctrl);
+ return;
+
+ case USB_REQ_SET_FEATURE:
+ case USB_REQ_CLEAR_FEATURE:
+ if ((ctrl.bRequestType & USB_TYPE_MASK) != USB_TYPE_STANDARD)
+ break;
+ s3c_hsudc_handle_reqfeat(hsudc, &ctrl);
+ hsudc->ep0state = WAIT_FOR_SETUP;
+ return;
+ }
+
+ if (hsudc->driver) {
+ spin_unlock(&hsudc->lock);
+ ret = hsudc->driver->setup(&hsudc->gadget, &ctrl);
+ spin_lock(&hsudc->lock);
+
+ if (ctrl.bRequest == USB_REQ_SET_CONFIGURATION) {
+ hsep->bEndpointAddress &= ~USB_DIR_IN;
+ hsudc->ep0state = WAIT_FOR_SETUP;
+ }
+
+ if (ret < 0) {
+ dev_err(hsudc->dev, "setup failed, returned %d\n",
+ ret);
+ s3c_hsudc_set_halt(&hsep->ep, 1);
+ hsudc->ep0state = WAIT_FOR_SETUP;
+ hsep->bEndpointAddress &= ~USB_DIR_IN;
+ }
+ }
+}
+
+/** s3c_hsudc_handle_ep0_intr - Handle endpoint 0 interrupt.
+ * @hsudc: Device controller on which endpoint 0 interrupt has occured.
+ *
+ * Handle endpoint 0 interrupt when it occurs. EP0 interrupt could occur
+ * when a stall handshake is sent to host or data is sent/received on
+ * endpoint 0.
+ */
+static void s3c_hsudc_handle_ep0_intr(struct s3c_hsudc *hsudc)
+{
+ struct s3c_hsudc_ep *hsep = &hsudc->ep[0];
+ struct s3c_hsudc_req *hsreq;
+ u32 csr = readl(hsudc->regs + S3C_EP0SR);
+ u32 ecr;
+
+ if (csr & S3C_EP0SR_STALL) {
+ ecr = readl(hsudc->regs + S3C_EP0CR);
+ ecr &= ~(S3C_ECR_STALL | S3C_ECR_FLUSH);
+ writel(ecr, hsudc->regs + S3C_EP0CR);
+
+ writel(S3C_EP0SR_STALL, hsudc->regs + S3C_EP0SR);
+ hsep->stopped = 0;
+
+ s3c_hsudc_nuke_ep(hsep, -ECONNABORTED);
+ hsudc->ep0state = WAIT_FOR_SETUP;
+ hsep->bEndpointAddress &= ~USB_DIR_IN;
+ return;
+ }
+
+ if (csr & S3C_EP0SR_TX_SUCCESS) {
+ writel(S3C_EP0SR_TX_SUCCESS, hsudc->regs + S3C_EP0SR);
+ if (ep_is_in(hsep)) {
+ if (list_empty(&hsep->queue))
+ return;
+
+ hsreq = list_entry(hsep->queue.next,
+ struct s3c_hsudc_req, queue);
+ s3c_hsudc_write_fifo(hsep, hsreq);
+ }
+ }
+
+ if (csr & S3C_EP0SR_RX_SUCCESS) {
+ if (hsudc->ep0state == WAIT_FOR_SETUP)
+ s3c_hsudc_process_setup(hsudc);
+ else {
+ if (!ep_is_in(hsep)) {
+ if (list_empty(&hsep->queue))
+ return;
+ hsreq = list_entry(hsep->queue.next,
+ struct s3c_hsudc_req, queue);
+ s3c_hsudc_read_fifo(hsep, hsreq);
+ }
+ }
+ }
+}
+
+/**
+ * s3c_hsudc_ep_enable - Enable a endpoint.
+ * @_ep: The endpoint to be enabled.
+ * @desc: Endpoint descriptor.
+ *
+ * Enables a endpoint when called from the gadget driver. Endpoint stall if
+ * any is cleared, transfer type is configured and endpoint interrupt is
+ * enabled.
+ */
+static int s3c_hsudc_ep_enable(struct usb_ep *_ep,
+ const struct usb_endpoint_descriptor *desc)
+{
+ struct s3c_hsudc_ep *hsep;
+ struct s3c_hsudc *hsudc;
+ unsigned long flags;
+ u32 ecr = 0;
+
+ hsep = container_of(_ep, struct s3c_hsudc_ep, ep);
+ if (!_ep || !desc || hsep->desc || _ep->name == ep0name
+ || desc->bDescriptorType != USB_DT_ENDPOINT
+ || hsep->bEndpointAddress != desc->bEndpointAddress
+ || ep_maxpacket(hsep) < le16_to_cpu(desc->wMaxPacketSize))
+ return -EINVAL;
+
+ if ((desc->bmAttributes == USB_ENDPOINT_XFER_BULK
+ && le16_to_cpu(desc->wMaxPacketSize) != ep_maxpacket(hsep))
+ || !desc->wMaxPacketSize)
+ return -ERANGE;
+
+ hsudc = hsep->dev;
+ if (!hsudc->driver || hsudc->gadget.speed == USB_SPEED_UNKNOWN)
+ return -ESHUTDOWN;
+
+ spin_lock_irqsave(&hsudc->lock, flags);
+
+ set_index(hsudc, hsep->bEndpointAddress);
+ ecr |= ((usb_endpoint_xfer_int(desc)) ? S3C_ECR_IEMS : S3C_ECR_DUEN);
+ writel(ecr, hsudc->regs + S3C_ECR);
+
+ hsep->stopped = hsep->wedge = 0;
+ hsep->desc = desc;
+ hsep->ep.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
+
+ s3c_hsudc_set_halt(_ep, 0);
+ __set_bit(ep_index(hsep), hsudc->regs + S3C_EIER);
+
+ spin_unlock_irqrestore(&hsudc->lock, flags);
+ return 0;
+}
+
+/**
+ * s3c_hsudc_ep_disable - Disable a endpoint.
+ * @_ep: The endpoint to be disabled.
+ * @desc: Endpoint descriptor.
+ *
+ * Disables a endpoint when called from the gadget driver.
+ */
+static int s3c_hsudc_ep_disable(struct usb_ep *_ep)
+{
+ struct s3c_hsudc_ep *hsep = our_ep(_ep);
+ struct s3c_hsudc *hsudc = hsep->dev;
+ unsigned long flags;
+
+ if (!_ep || !hsep->desc)
+ return -EINVAL;
+
+ spin_lock_irqsave(&hsudc->lock, flags);
+
+ set_index(hsudc, hsep->bEndpointAddress);
+ __clear_bit(ep_index(hsep), hsudc->regs + S3C_EIER);
+
+ s3c_hsudc_nuke_ep(hsep, -ESHUTDOWN);
+
+ hsep->desc = 0;
+ hsep->stopped = 1;
+
+ spin_unlock_irqrestore(&hsudc->lock, flags);
+ return 0;
+}
+
+/**
+ * s3c_hsudc_alloc_request - Allocate a new request.
+ * @_ep: Endpoint for which request is allocated (not used).
+ * @gfp_flags: Flags used for the allocation.
+ *
+ * Allocates a single transfer request structure when called from gadget driver.
+ */
+static struct usb_request *s3c_hsudc_alloc_request(struct usb_ep *_ep,
+ gfp_t gfp_flags)
+{
+ struct s3c_hsudc_req *hsreq;
+
+ hsreq = kzalloc(sizeof *hsreq, gfp_flags);
+ if (!hsreq)
+ return 0;
+
+ INIT_LIST_HEAD(&hsreq->queue);
+ return &hsreq->req;
+}
+
+/**
+ * s3c_hsudc_free_request - Deallocate a request.
+ * @ep: Endpoint for which request is deallocated (not used).
+ * @_req: Request to be deallocated.
+ *
+ * Allocates a single transfer request structure when called from gadget driver.
+ */
+static void s3c_hsudc_free_request(struct usb_ep *ep, struct usb_request *_req)
+{
+ struct s3c_hsudc_req *hsreq;
+
+ hsreq = container_of(_req, struct s3c_hsudc_req, req);
+ WARN_ON(!list_empty(&hsreq->queue));
+ kfree(hsreq);
+}
+
+/**
+ * s3c_hsudc_queue - Queue a transfer request for the endpoint.
+ * @_ep: Endpoint for which the request is queued.
+ * @_req: Request to be queued.
+ * @gfp_flags: Not used.
+ *
+ * Start or enqueue a request for a endpoint when called from gadget driver.
+ */
+static int s3c_hsudc_queue(struct usb_ep *_ep, struct usb_request *_req,
+ gfp_t gfp_flags)
+{
+ struct s3c_hsudc_req *hsreq;
+ struct s3c_hsudc_ep *hsep;
+ struct s3c_hsudc *hsudc;
+ unsigned long flags;
+ u32 offset;
+ u32 csr;
+
+ hsreq = container_of(_req, struct s3c_hsudc_req, req);
+ if ((!_req || !_req->complete || !_req->buf ||
+ !list_empty(&hsreq->queue)))
+ return -EINVAL;
+
+ hsep = container_of(_ep, struct s3c_hsudc_ep, ep);
+ hsudc = hsep->dev;
+ if (!hsudc->driver || hsudc->gadget.speed == USB_SPEED_UNKNOWN)
+ return -ESHUTDOWN;
+
+ spin_lock_irqsave(&hsudc->lock, flags);
+ set_index(hsudc, hsep->bEndpointAddress);
+
+ _req->status = -EINPROGRESS;
+ _req->actual = 0;
+
+ if (!ep_index(hsep) && _req->length == 0) {
+ hsudc->ep0state = WAIT_FOR_SETUP;
+ s3c_hsudc_complete_request(hsep, hsreq, 0);
+ spin_unlock_irqrestore(&hsudc->lock, flags);
+ return 0;
+ }
+
+ if (list_empty(&hsep->queue) && !hsep->stopped) {
+ offset = (ep_index(hsep)) ? S3C_ESR : S3C_EP0SR;
+ if (ep_is_in(hsep)) {
+ csr = readl((u32)hsudc->regs + offset);
+ if (!(csr & S3C_ESR_TX_SUCCESS) &&
+ (s3c_hsudc_write_fifo(hsep, hsreq) == 1))
+ hsreq = 0;
+ } else {
+ csr = readl((u32)hsudc->regs + offset);
+ if ((csr & S3C_ESR_RX_SUCCESS)
+ && (s3c_hsudc_read_fifo(hsep, hsreq) == 1))
+ hsreq = 0;
+ }
+ }
+
+ if (hsreq != 0)
+ list_add_tail(&hsreq->queue, &hsep->queue);
+
+ spin_unlock_irqrestore(&hsudc->lock, flags);
+ return 0;
+}
+
+/**
+ * s3c_hsudc_dequeue - Dequeue a transfer request from an endpoint.
+ * @_ep: Endpoint from which the request is dequeued.
+ * @_req: Request to be dequeued.
+ *
+ * Dequeue a request from a endpoint when called from gadget driver.
+ */
+static int s3c_hsudc_dequeue(struct usb_ep *_ep, struct usb_request *_req)
+{
+ struct s3c_hsudc_ep *hsep = our_ep(_ep);
+ struct s3c_hsudc *hsudc = hsep->dev;
+ struct s3c_hsudc_req *hsreq;
+ unsigned long flags;
+
+ hsep = container_of(_ep, struct s3c_hsudc_ep, ep);
+ if (!_ep || hsep->ep.name == ep0name)
+ return -EINVAL;
+
+ spin_lock_irqsave(&hsudc->lock, flags);
+
+ list_for_each_entry(hsreq, &hsep->queue, queue) {
+ if (&hsreq->req == _req)
+ break;
+ }
+ if (&hsreq->req != _req) {
+ spin_unlock_irqrestore(&hsudc->lock, flags);
+ return -EINVAL;
+ }
+
+ set_index(hsudc, hsep->bEndpointAddress);
+ s3c_hsudc_complete_request(hsep, hsreq, -ECONNRESET);
+
+ spin_unlock_irqrestore(&hsudc->lock, flags);
+ return 0;
+}
+
+static struct usb_ep_ops s3c_hsudc_ep_ops = {
+ .enable = s3c_hsudc_ep_enable,
+ .disable = s3c_hsudc_ep_disable,
+ .alloc_request = s3c_hsudc_alloc_request,
+ .free_request = s3c_hsudc_free_request,
+ .queue = s3c_hsudc_queue,
+ .dequeue = s3c_hsudc_dequeue,
+ .set_halt = s3c_hsudc_set_halt,
+ .set_wedge = s3c_hsudc_set_wedge,
+};
+
+/**
+ * s3c_hsudc_initep - Initialize a endpoint to default state.
+ * @hsudc - Reference to the device controller.
+ * @hsep - Endpoint to be initialized.
+ * @epnum - Address to be assigned to the endpoint.
+ *
+ * Initialize a endpoint with default configuration.
+ */
+static void s3c_hsudc_initep(struct s3c_hsudc *hsudc,
+ struct s3c_hsudc_ep *hsep, int epnum)
+{
+ char *dir;
+
+ if ((epnum % 2) == 0) {
+ dir = "out";
+ } else {
+ dir = "in";
+ hsep->bEndpointAddress = USB_DIR_IN;
+ }
+
+ hsep->bEndpointAddress |= epnum;
+ if (epnum)
+ snprintf(hsep->name, sizeof(hsep->name), "ep%d%s", epnum, dir);
+ else
+ snprintf(hsep->name, sizeof(hsep->name), "%s", ep0name);
+
+ INIT_LIST_HEAD(&hsep->queue);
+ INIT_LIST_HEAD(&hsep->ep.ep_list);
+ if (epnum)
+ list_add_tail(&hsep->ep.ep_list, &hsudc->gadget.ep_list);
+
+ hsep->dev = hsudc;
+ hsep->ep.name = hsep->name;
+ hsep->ep.maxpacket = epnum ? 512 : 64;
+ hsep->ep.ops = &s3c_hsudc_ep_ops;
+ hsep->fifo = hsudc->regs + S3C_BR(epnum);
+ hsep->desc = 0;
+ hsep->stopped = 0;
+ hsep->wedge = 0;
+
+ set_index(hsudc, epnum);
+ writel(hsep->ep.maxpacket, hsudc->regs + S3C_MPR);
+}
+
+/**
+ * s3c_hsudc_setup_ep - Configure all endpoints to default state.
+ * @hsudc: Reference to device controller.
+ *
+ * Configures all endpoints to default state.
+ */
+static void s3c_hsudc_setup_ep(struct s3c_hsudc *hsudc)
+{
+ int epnum;
+
+ hsudc->ep0state = WAIT_FOR_SETUP;
+ INIT_LIST_HEAD(&hsudc->gadget.ep_list);
+ for (epnum = 0; epnum < hsudc->pd->epnum; epnum++)
+ s3c_hsudc_initep(hsudc, &hsudc->ep[epnum], epnum);
+}
+
+/**
+ * s3c_hsudc_reconfig - Reconfigure the device controller to default state.
+ * @hsudc: Reference to device controller.
+ *
+ * Reconfigures the device controller registers to a default state.
+ */
+static void s3c_hsudc_reconfig(struct s3c_hsudc *hsudc)
+{
+ writel(0xAA, hsudc->regs + S3C_EDR);
+ writel(1, hsudc->regs + S3C_EIER);
+ writel(0, hsudc->regs + S3C_TR);
+ writel(S3C_SCR_DTZIEN_EN | S3C_SCR_RRD_EN | S3C_SCR_SUS_EN |
+ S3C_SCR_RST_EN, hsudc->regs + S3C_SCR);
+ writel(0, hsudc->regs + S3C_EP0CR);
+
+ s3c_hsudc_setup_ep(hsudc);
+}
+
+/**
+ * s3c_hsudc_irq - Interrupt handler for device controller.
+ * @irq: Not used.
+ * @_dev: Reference to the device controller.
+ *
+ * Interrupt handler for the device controller. This handler handles controller
+ * interrupts and endpoint interrupts.
+ */
+static irqreturn_t s3c_hsudc_irq(int irq, void *_dev)
+{
+ struct s3c_hsudc *hsudc = _dev;
+ struct s3c_hsudc_ep *hsep;
+ u32 ep_intr;
+ u32 sys_status;
+ u32 ep_idx;
+
+ spin_lock(&hsudc->lock);
+
+ sys_status = readl(hsudc->regs + S3C_SSR);
+ ep_intr = readl(hsudc->regs + S3C_EIR) & 0x3FF;
+
+ if (!ep_intr && !(sys_status & S3C_SSR_DTZIEN_EN)) {
+ spin_unlock(&hsudc->lock);
+ return IRQ_HANDLED;
+ }
+
+ if (sys_status) {
+ if (sys_status & S3C_SSR_VBUSON)
+ writel(S3C_SSR_VBUSON, hsudc->regs + S3C_SSR);
+
+ if (sys_status & S3C_SSR_ERR)
+ writel(S3C_SSR_ERR, hsudc->regs + S3C_SSR);
+
+ if (sys_status & S3C_SSR_SDE) {
+ writel(S3C_SSR_SDE, hsudc->regs + S3C_SSR);
+ hsudc->gadget.speed = (sys_status & S3C_SSR_HSP) ?
+ USB_SPEED_HIGH : USB_SPEED_FULL;
+ }
+
+ if (sys_status & S3C_SSR_SUSPEND) {
+ writel(S3C_SSR_SUSPEND, hsudc->regs + S3C_SSR);
+ if (hsudc->gadget.speed != USB_SPEED_UNKNOWN
+ && hsudc->driver && hsudc->driver->suspend)
+ hsudc->driver->suspend(&hsudc->gadget);
+ }
+
+ if (sys_status & S3C_SSR_RESUME) {
+ writel(S3C_SSR_RESUME, hsudc->regs + S3C_SSR);
+ if (hsudc->gadget.speed != USB_SPEED_UNKNOWN
+ && hsudc->driver && hsudc->driver->resume)
+ hsudc->driver->resume(&hsudc->gadget);
+ }
+
+ if (sys_status & S3C_SSR_RESET) {
+ writel(S3C_SSR_RESET, hsudc->regs + S3C_SSR);
+ for (ep_idx = 0; ep_idx < hsudc->pd->epnum; ep_idx++) {
+ hsep = &hsudc->ep[ep_idx];
+ hsep->stopped = 1;
+ s3c_hsudc_nuke_ep(hsep, -ECONNRESET);
+ }
+ s3c_hsudc_reconfig(hsudc);
+ hsudc->ep0state = WAIT_FOR_SETUP;
+ }
+ }
+
+ if (ep_intr & S3C_EIR_EP0) {
+ writel(S3C_EIR_EP0, hsudc->regs + S3C_EIR);
+ set_index(hsudc, 0);
+ s3c_hsudc_handle_ep0_intr(hsudc);
+ }
+
+ ep_intr >>= 1;
+ ep_idx = 1;
+ while (ep_intr) {
+ if (ep_intr & 1) {
+ hsep = &hsudc->ep[ep_idx];
+ set_index(hsudc, ep_idx);
+ writel(1 << ep_idx, hsudc->regs + S3C_EIR);
+ if (ep_is_in(hsep))
+ s3c_hsudc_epin_intr(hsudc, ep_idx);
+ else
+ s3c_hsudc_epout_intr(hsudc, ep_idx);
+ }
+ ep_intr >>= 1;
+ ep_idx++;
+ }
+
+ spin_unlock(&hsudc->lock);
+ return IRQ_HANDLED;
+}
+
+int usb_gadget_probe_driver(struct usb_gadget_driver *driver,
+ int (*bind)(struct usb_gadget *))
+{
+ struct s3c_hsudc *hsudc = the_controller;
+ int ret;
+
+ if (!driver
+ || (driver->speed != USB_SPEED_FULL &&
+ driver->speed != USB_SPEED_HIGH)
+ || !bind
+ || !driver->unbind || !driver->disconnect || !driver->setup)
+ return -EINVAL;
+
+ if (!hsudc)
+ return -ENODEV;
+
+ if (hsudc->driver)
+ return -EBUSY;
+
+ hsudc->driver = driver;
+ hsudc->gadget.dev.driver = &driver->driver;
+ hsudc->gadget.speed = USB_SPEED_UNKNOWN;
+ ret = device_add(&hsudc->gadget.dev);
+ if (ret) {
+ dev_err(hsudc->dev, "failed to probe gadget device");
+ return ret;
+ }
+
+ ret = bind(&hsudc->gadget);
+ if (ret) {
+ dev_err(hsudc->dev, "%s: bind failed\n", hsudc->gadget.name);
+ device_del(&hsudc->gadget.dev);
+
+ hsudc->driver = NULL;
+ hsudc->gadget.dev.driver = NULL;
+ return ret;
+ }
+
+ enable_irq(hsudc->irq);
+ dev_info(hsudc->dev, "bound driver %s\n", driver->driver.name);
+
+ s3c_hsudc_reconfig(hsudc);
+ s3c_hsudc_init_phy();
+ if (hsudc->pd->gpio_init)
+ hsudc->pd->gpio_init();
+
+ return 0;
+}
+EXPORT_SYMBOL(usb_gadget_probe_driver);
+
+int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
+{
+ struct s3c_hsudc *hsudc = the_controller;
+ unsigned long flags;
+
+ if (!hsudc)
+ return -ENODEV;
+
+ if (!driver || driver != hsudc->driver || !driver->unbind)
+ return -EINVAL;
+
+ spin_lock_irqsave(&hsudc->lock, flags);
+ hsudc->driver = 0;
+ s3c_hsudc_uninit_phy();
+ if (hsudc->pd->gpio_uninit)
+ hsudc->pd->gpio_uninit();
+ s3c_hsudc_stop_activity(hsudc, driver);
+ spin_unlock_irqrestore(&hsudc->lock, flags);
+
+ driver->unbind(&hsudc->gadget);
+ device_del(&hsudc->gadget.dev);
+ disable_irq(hsudc->irq);
+
+ dev_info(hsudc->dev, "unregistered gadget driver '%s'\n",
+ driver->driver.name);
+ return 0;
+}
+EXPORT_SYMBOL(usb_gadget_unregister_driver);
+
+static inline u32 s3c_hsudc_read_frameno(struct s3c_hsudc *hsudc)
+{
+ return readl(hsudc->regs + S3C_FNR) & 0x3FF;
+}
+
+static int s3c_hsudc_gadget_getframe(struct usb_gadget *gadget)
+{
+ return s3c_hsudc_read_frameno(to_hsudc(gadget));
+}
+
+static struct usb_gadget_ops s3c_hsudc_gadget_ops = {
+ .get_frame = s3c_hsudc_gadget_getframe,
+};
+
+static int s3c_hsudc_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct resource *res;
+ struct s3c_hsudc *hsudc;
+ struct s3c24xx_hsudc_platdata *pd = pdev->dev.platform_data;
+ int ret;
+
+ hsudc = kzalloc(sizeof(struct s3c_hsudc) +
+ sizeof(struct s3c_hsudc_ep) * pd->epnum,
+ GFP_KERNEL);
+ if (!hsudc) {
+ dev_err(dev, "cannot allocate memory\n");
+ return -ENOMEM;
+ }
+
+ the_controller = hsudc;
+ platform_set_drvdata(pdev, dev);
+ hsudc->dev = dev;
+ hsudc->pd = pdev->dev.platform_data;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ dev_err(dev, "unable to obtain driver resource data\n");
+ ret = -ENODEV;
+ goto err_res;
+ }
+
+ hsudc->mem_rsrc = request_mem_region(res->start, resource_size(res),
+ dev_name(&pdev->dev));
+ if (!hsudc->mem_rsrc) {
+ dev_err(dev, "failed to reserve register area\n");
+ ret = -ENODEV;
+ goto err_res;
+ }
+
+ hsudc->regs = ioremap(res->start, resource_size(res));
+ if (!hsudc->regs) {
+ dev_err(dev, "error mapping device register area\n");
+ ret = -EBUSY;
+ goto err_remap;
+ }
+
+ ret = platform_get_irq(pdev, 0);
+ if (ret < 0) {
+ dev_err(dev, "unable to obtain IRQ number\n");
+ goto err_irq;
+ }
+ hsudc->irq = ret;
+
+ ret = request_irq(hsudc->irq, s3c_hsudc_irq, 0, driver_name, hsudc);
+ if (ret < 0) {
+ dev_err(dev, "irq request failed\n");
+ goto err_irq;
+ }
+
+ spin_lock_init(&hsudc->lock);
+
+ device_initialize(&hsudc->gadget.dev);
+ dev_set_name(&hsudc->gadget.dev, "gadget");
+
+ hsudc->gadget.is_dualspeed = 1;
+ hsudc->gadget.ops = &s3c_hsudc_gadget_ops;
+ hsudc->gadget.name = dev_name(dev);
+ hsudc->gadget.dev.parent = dev;
+ hsudc->gadget.dev.dma_mask = dev->dma_mask;
+ hsudc->gadget.ep0 = &hsudc->ep[0].ep;
+
+ hsudc->gadget.is_otg = 0;
+ hsudc->gadget.is_a_peripheral = 0;
+
+ s3c_hsudc_setup_ep(hsudc);
+
+ hsudc->uclk = clk_get(&pdev->dev, "usb-device");
+ if (IS_ERR(hsudc->uclk)) {
+ dev_err(dev, "failed to find usb-device clock source\n");
+ return PTR_ERR(hsudc->uclk);
+ }
+ clk_enable(hsudc->uclk);
+
+ local_irq_disable();
+
+ disable_irq(hsudc->irq);
+ local_irq_enable();
+ return 0;
+
+err_irq:
+ iounmap(hsudc->regs);
+
+err_remap:
+ release_resource(hsudc->mem_rsrc);
+ kfree(hsudc->mem_rsrc);
+
+err_res:
+ kfree(hsudc);
+ return ret;
+}
+
+static struct platform_driver s3c_hsudc_driver = {
+ .driver = {
+ .owner = THIS_MODULE,
+ .name = "s3c-hsudc",
+ },
+ .probe = s3c_hsudc_probe,
+};
+
+static int __init s3c_hsudc_modinit(void)
+{
+ return platform_driver_register(&s3c_hsudc_driver);
+}
+
+static void __exit s3c_hsudc_modexit(void)
+{
+ platform_driver_unregister(&s3c_hsudc_driver);
+}
+
+module_init(s3c_hsudc_modinit);
+module_exit(s3c_hsudc_modexit);
+
+MODULE_DESCRIPTION("Samsung S3C24XX USB high-speed controller driver");
+MODULE_AUTHOR("Thomas Abraham <thomas.ab@samsung.com>");
+MODULE_LICENSE("GPL");
diff --git a/drivers/usb/gadget/storage_common.c b/drivers/usb/gadget/storage_common.c
index b015561..1fa4f70 100644
--- a/drivers/usb/gadget/storage_common.c
+++ b/drivers/usb/gadget/storage_common.c
@@ -708,13 +708,14 @@
static ssize_t fsg_store_ro(struct device *dev, struct device_attribute *attr,
const char *buf, size_t count)
{
- ssize_t rc = count;
+ ssize_t rc;
struct fsg_lun *curlun = fsg_lun_from_dev(dev);
struct rw_semaphore *filesem = dev_get_drvdata(dev);
- unsigned long ro;
+ unsigned ro;
- if (strict_strtoul(buf, 2, &ro))
- return -EINVAL;
+ rc = kstrtouint(buf, 2, &ro);
+ if (rc)
+ return rc;
/*
* Allow the write-enable status to change only while the
@@ -728,6 +729,7 @@
curlun->ro = ro;
curlun->initially_ro = ro;
LDBG(curlun, "read-only status set to %d\n", curlun->ro);
+ rc = count;
}
up_read(filesem);
return rc;
@@ -738,10 +740,12 @@
const char *buf, size_t count)
{
struct fsg_lun *curlun = fsg_lun_from_dev(dev);
- unsigned long nofua;
+ unsigned nofua;
+ int ret;
- if (strict_strtoul(buf, 2, &nofua))
- return -EINVAL;
+ ret = kstrtouint(buf, 2, &nofua);
+ if (ret)
+ return ret;
/* Sync data when switching from async mode to sync */
if (!nofua && curlun->nofua)
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index e0e0787..ab085f1 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -106,13 +106,13 @@
depends on USB_EHCI_HCD && (PPC_CELLEB || PPC_PS3 || 440EPX || \
ARCH_IXP4XX || XPS_USB_HCD_XILINX || \
PPC_MPC512x || CPU_CAVIUM_OCTEON || \
- PMC_MSP)
+ PMC_MSP || SPARC_LEON)
default y
config USB_EHCI_BIG_ENDIAN_DESC
bool
depends on USB_EHCI_HCD && (440EPX || ARCH_IXP4XX || XPS_USB_HCD_XILINX || \
- PPC_MPC512x || PMC_MSP)
+ PPC_MPC512x || PMC_MSP || SPARC_LEON)
default y
config XPS_USB_HCD_XILINX
@@ -188,6 +188,12 @@
Enables support for the on-chip EHCI controller on the SuperH.
If you use the PCI EHCI controller, this option is not necessary.
+config USB_EHCI_S5P
+ boolean "S5P EHCI support"
+ depends on USB_EHCI_HCD && PLAT_S5P
+ help
+ Enable support for the S5P SOC's on-chip EHCI controller.
+
config USB_W90X900_EHCI
bool "W90X900(W90P910) EHCI support"
depends on USB_EHCI_HCD && ARCH_W90X900
@@ -202,6 +208,15 @@
It is needed for high-speed (480Mbit/sec) USB 2.0 device
support.
+config USB_EHCI_ATH79
+ bool "EHCI support for AR7XXX/AR9XXX SoCs"
+ depends on USB_EHCI_HCD && (SOC_AR71XX || SOC_AR724X || SOC_AR913X)
+ select USB_EHCI_ROOT_HUB_TT
+ default y
+ ---help---
+ Enables support for the built-in EHCI controller present
+ on the Atheros AR7XXX/AR9XXX SoCs.
+
config USB_OXU210HP_HCD
tristate "OXU210HP HCD support"
depends on USB
@@ -287,6 +302,14 @@
Enables support for the on-chip OHCI controller on
OMAP3 and later chips.
+config USB_OHCI_ATH79
+ bool "USB OHCI support for the Atheros AR71XX/AR7240 SoCs"
+ depends on USB_OHCI_HCD && (SOC_AR71XX || SOC_AR724X)
+ default y
+ help
+ Enables support for the built-in OHCI controller present on the
+ Atheros AR71XX/AR7240 SoCs.
+
config USB_OHCI_HCD_PPC_SOC
bool "OHCI support for on-chip PPC USB controller"
depends on USB_OHCI_HCD && (STB03xxx || PPC_MPC52xx)
@@ -373,7 +396,7 @@
config USB_UHCI_HCD
tristate "UHCI HCD (most Intel and VIA) support"
- depends on USB && PCI
+ depends on USB && (PCI || SPARC_LEON)
---help---
The Universal Host Controller Interface is a standard by Intel for
accessing the USB hardware in the PC (which is also called the USB
@@ -382,11 +405,27 @@
with Intel PCI chipsets (like intel 430TX, 440FX, 440LX, 440BX,
i810, i820) conform to this standard. Also all VIA PCI chipsets
(like VIA VP2, VP3, MVP3, Apollo Pro, Apollo Pro II or Apollo Pro
- 133). If unsure, say Y.
+ 133) and LEON/GRLIB SoCs with the GRUSBHC controller.
+ If unsure, say Y.
To compile this driver as a module, choose M here: the
module will be called uhci-hcd.
+config USB_UHCI_SUPPORT_NON_PCI_HC
+ bool
+ depends on USB_UHCI_HCD
+ default y if SPARC_LEON
+
+config USB_UHCI_BIG_ENDIAN_MMIO
+ bool
+ depends on USB_UHCI_SUPPORT_NON_PCI_HC && SPARC_LEON
+ default y
+
+config USB_UHCI_BIG_ENDIAN_DESC
+ bool
+ depends on USB_UHCI_SUPPORT_NON_PCI_HC && SPARC_LEON
+ default y
+
config USB_FHCI_HCD
tristate "Freescale QE USB Host Controller support"
depends on USB && OF_GPIO && QE_GPIO && QUICC_ENGINE
@@ -444,6 +483,16 @@
To compile this driver as a module, choose M here: the
module will be called sl811-hcd.
+config USB_SL811_HCD_ISO
+ bool "partial ISO support"
+ depends on USB_SL811_HCD
+ help
+ The driver doesn't support iso_frame_desc (yet), but for some simple
+ devices that just queue one ISO frame per URB, then ISO transfers
+ "should" work using the normal urb status fields.
+
+ If unsure, say N.
+
config USB_SL811_CS
tristate "CF/PCMCIA support for SL811HS HCD"
depends on USB_SL811_HCD && PCMCIA
diff --git a/drivers/usb/host/ehci-ath79.c b/drivers/usb/host/ehci-ath79.c
new file mode 100644
index 0000000..98cc8a1
--- /dev/null
+++ b/drivers/usb/host/ehci-ath79.c
@@ -0,0 +1,202 @@
+/*
+ * Bus Glue for Atheros AR7XXX/AR9XXX built-in EHCI controller.
+ *
+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * Parts of this file are based on Atheros' 2.6.15 BSP
+ * Copyright (C) 2007 Atheros Communications, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/platform_device.h>
+
+enum {
+ EHCI_ATH79_IP_V1 = 0,
+ EHCI_ATH79_IP_V2,
+};
+
+static const struct platform_device_id ehci_ath79_id_table[] = {
+ {
+ .name = "ar71xx-ehci",
+ .driver_data = EHCI_ATH79_IP_V1,
+ },
+ {
+ .name = "ar724x-ehci",
+ .driver_data = EHCI_ATH79_IP_V2,
+ },
+ {
+ .name = "ar913x-ehci",
+ .driver_data = EHCI_ATH79_IP_V2,
+ },
+ {
+ /* terminating entry */
+ },
+};
+
+MODULE_DEVICE_TABLE(platform, ehci_ath79_id_table);
+
+static int ehci_ath79_init(struct usb_hcd *hcd)
+{
+ struct ehci_hcd *ehci = hcd_to_ehci(hcd);
+ struct platform_device *pdev = to_platform_device(hcd->self.controller);
+ const struct platform_device_id *id;
+ int hclength;
+ int ret;
+
+ id = platform_get_device_id(pdev);
+ if (!id) {
+ dev_err(hcd->self.controller, "missing device id\n");
+ return -EINVAL;
+ }
+
+ hclength = HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
+ switch (id->driver_data) {
+ case EHCI_ATH79_IP_V1:
+ ehci->has_synopsys_hc_bug = 1;
+
+ ehci->caps = hcd->regs;
+ ehci->regs = hcd->regs + hclength;
+ break;
+
+ case EHCI_ATH79_IP_V2:
+ hcd->has_tt = 1;
+
+ ehci->caps = hcd->regs + 0x100;
+ ehci->regs = hcd->regs + 0x100 + hclength;
+ break;
+
+ default:
+ BUG();
+ }
+
+ dbg_hcs_params(ehci, "reset");
+ dbg_hcc_params(ehci, "reset");
+ ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
+ ehci->sbrn = 0x20;
+
+ ehci_reset(ehci);
+
+ ret = ehci_init(hcd);
+ if (ret)
+ return ret;
+
+ ehci_port_power(ehci, 0);
+
+ return 0;
+}
+
+static const struct hc_driver ehci_ath79_hc_driver = {
+ .description = hcd_name,
+ .product_desc = "Atheros built-in EHCI controller",
+ .hcd_priv_size = sizeof(struct ehci_hcd),
+ .irq = ehci_irq,
+ .flags = HCD_MEMORY | HCD_USB2,
+
+ .reset = ehci_ath79_init,
+ .start = ehci_run,
+ .stop = ehci_stop,
+ .shutdown = ehci_shutdown,
+
+ .urb_enqueue = ehci_urb_enqueue,
+ .urb_dequeue = ehci_urb_dequeue,
+ .endpoint_disable = ehci_endpoint_disable,
+ .endpoint_reset = ehci_endpoint_reset,
+
+ .get_frame_number = ehci_get_frame,
+
+ .hub_status_data = ehci_hub_status_data,
+ .hub_control = ehci_hub_control,
+
+ .relinquish_port = ehci_relinquish_port,
+ .port_handed_over = ehci_port_handed_over,
+
+ .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
+};
+
+static int ehci_ath79_probe(struct platform_device *pdev)
+{
+ struct usb_hcd *hcd;
+ struct resource *res;
+ int irq;
+ int ret;
+
+ if (usb_disabled())
+ return -ENODEV;
+
+ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+ if (!res) {
+ dev_dbg(&pdev->dev, "no IRQ specified\n");
+ return -ENODEV;
+ }
+ irq = res->start;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ dev_dbg(&pdev->dev, "no base address specified\n");
+ return -ENODEV;
+ }
+
+ hcd = usb_create_hcd(&ehci_ath79_hc_driver, &pdev->dev,
+ dev_name(&pdev->dev));
+ if (!hcd)
+ return -ENOMEM;
+
+ hcd->rsrc_start = res->start;
+ hcd->rsrc_len = res->end - res->start + 1;
+
+ if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) {
+ dev_dbg(&pdev->dev, "controller already in use\n");
+ ret = -EBUSY;
+ goto err_put_hcd;
+ }
+
+ hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
+ if (!hcd->regs) {
+ dev_dbg(&pdev->dev, "error mapping memory\n");
+ ret = -EFAULT;
+ goto err_release_region;
+ }
+
+ ret = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED);
+ if (ret)
+ goto err_iounmap;
+
+ return 0;
+
+err_iounmap:
+ iounmap(hcd->regs);
+
+err_release_region:
+ release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
+err_put_hcd:
+ usb_put_hcd(hcd);
+ return ret;
+}
+
+static int ehci_ath79_remove(struct platform_device *pdev)
+{
+ struct usb_hcd *hcd = platform_get_drvdata(pdev);
+
+ usb_remove_hcd(hcd);
+ iounmap(hcd->regs);
+ release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
+ usb_put_hcd(hcd);
+
+ return 0;
+}
+
+static struct platform_driver ehci_ath79_driver = {
+ .probe = ehci_ath79_probe,
+ .remove = ehci_ath79_remove,
+ .id_table = ehci_ath79_id_table,
+ .driver = {
+ .owner = THIS_MODULE,
+ .name = "ath79-ehci",
+ }
+};
+
+MODULE_ALIAS(PLATFORM_MODULE_PREFIX "ath79-ehci");
diff --git a/drivers/usb/host/ehci-atmel.c b/drivers/usb/host/ehci-atmel.c
index b2ed55c..a5a3ef1 100644
--- a/drivers/usb/host/ehci-atmel.c
+++ b/drivers/usb/host/ehci-atmel.c
@@ -56,7 +56,7 @@
/* registers start at offset 0x0 */
ehci->caps = hcd->regs;
ehci->regs = hcd->regs +
- HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
+ HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
dbg_hcs_params(ehci, "reset");
dbg_hcc_params(ehci, "reset");
diff --git a/drivers/usb/host/ehci-au1xxx.c b/drivers/usb/host/ehci-au1xxx.c
index a869e3c..42ae574 100644
--- a/drivers/usb/host/ehci-au1xxx.c
+++ b/drivers/usb/host/ehci-au1xxx.c
@@ -175,7 +175,8 @@
ehci = hcd_to_ehci(hcd);
ehci->caps = hcd->regs;
- ehci->regs = hcd->regs + HC_LENGTH(readl(&ehci->caps->hc_capbase));
+ ehci->regs = hcd->regs +
+ HC_LENGTH(ehci, readl(&ehci->caps->hc_capbase));
/* cache this readonly data; minimize chip reads */
ehci->hcs_params = readl(&ehci->caps->hcs_params);
@@ -215,10 +216,7 @@
struct usb_hcd *hcd = dev_get_drvdata(dev);
struct ehci_hcd *ehci = hcd_to_ehci(hcd);
unsigned long flags;
- int rc;
-
- return 0;
- rc = 0;
+ int rc = 0;
if (time_before(jiffies, ehci->next_statechange))
msleep(10);
@@ -233,13 +231,13 @@
(void)ehci_readl(ehci, &ehci->regs->intr_enable);
clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
-
- au1xxx_stop_ehc();
spin_unlock_irqrestore(&ehci->lock, flags);
// could save FLADJ in case of Vaux power loss
// ... we'd only use it to handle clock skew
+ au1xxx_stop_ehc();
+
return rc;
}
diff --git a/drivers/usb/host/ehci-cns3xxx.c b/drivers/usb/host/ehci-cns3xxx.c
index 708a05b..d41745c 100644
--- a/drivers/usb/host/ehci-cns3xxx.c
+++ b/drivers/usb/host/ehci-cns3xxx.c
@@ -34,7 +34,7 @@
ehci->caps = hcd->regs;
ehci->regs = hcd->regs
- + HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
+ + HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
hcd->has_tt = 0;
diff --git a/drivers/usb/host/ehci-dbg.c b/drivers/usb/host/ehci-dbg.c
index 693c29b..40a844c 100644
--- a/drivers/usb/host/ehci-dbg.c
+++ b/drivers/usb/host/ehci-dbg.c
@@ -726,7 +726,7 @@
}
/* Capability Registers */
- i = HC_VERSION(ehci_readl(ehci, &ehci->caps->hc_capbase));
+ i = HC_VERSION(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
temp = scnprintf (next, size,
"bus %s, device %s\n"
"%s\n"
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c
index 5c761df..f380bf9 100644
--- a/drivers/usb/host/ehci-fsl.c
+++ b/drivers/usb/host/ehci-fsl.c
@@ -117,6 +117,9 @@
pdata->regs = hcd->regs;
+ if (pdata->power_budget)
+ hcd->power_budget = pdata->power_budget;
+
/*
* do platform specific init: check the clock, grab/config pins, etc.
*/
@@ -134,6 +137,30 @@
retval = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED);
if (retval != 0)
goto err4;
+
+#ifdef CONFIG_USB_OTG
+ if (pdata->operating_mode == FSL_USB2_DR_OTG) {
+ struct ehci_hcd *ehci = hcd_to_ehci(hcd);
+
+ ehci->transceiver = otg_get_transceiver();
+ dev_dbg(&pdev->dev, "hcd=0x%p ehci=0x%p, transceiver=0x%p\n",
+ hcd, ehci, ehci->transceiver);
+
+ if (ehci->transceiver) {
+ retval = otg_set_host(ehci->transceiver,
+ &ehci_to_hcd(ehci)->self);
+ if (retval) {
+ if (ehci->transceiver)
+ put_device(ehci->transceiver->dev);
+ goto err4;
+ }
+ } else {
+ dev_err(&pdev->dev, "can't find transceiver\n");
+ retval = -ENODEV;
+ goto err4;
+ }
+ }
+#endif
return retval;
err4:
@@ -164,6 +191,12 @@
struct platform_device *pdev)
{
struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
+ struct ehci_hcd *ehci = hcd_to_ehci(hcd);
+
+ if (ehci->transceiver) {
+ otg_set_host(ehci->transceiver, NULL);
+ put_device(ehci->transceiver->dev);
+ }
usb_remove_hcd(hcd);
@@ -291,7 +324,7 @@
/* EHCI registers start at offset 0x100 */
ehci->caps = hcd->regs + 0x100;
ehci->regs = hcd->regs + 0x100 +
- HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
+ HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
dbg_hcs_params(ehci, "reset");
dbg_hcc_params(ehci, "reset");
@@ -328,6 +361,149 @@
#ifdef CONFIG_PM
+#ifdef CONFIG_PPC_MPC512x
+static int ehci_fsl_mpc512x_drv_suspend(struct device *dev)
+{
+ struct usb_hcd *hcd = dev_get_drvdata(dev);
+ struct ehci_hcd *ehci = hcd_to_ehci(hcd);
+ struct fsl_usb2_platform_data *pdata = dev->platform_data;
+ u32 tmp;
+
+#ifdef DEBUG
+ u32 mode = ehci_readl(ehci, hcd->regs + FSL_SOC_USB_USBMODE);
+ mode &= USBMODE_CM_MASK;
+ tmp = ehci_readl(ehci, hcd->regs + 0x140); /* usbcmd */
+
+ dev_dbg(dev, "suspend=%d already_suspended=%d "
+ "mode=%d usbcmd %08x\n", pdata->suspended,
+ pdata->already_suspended, mode, tmp);
+#endif
+
+ /*
+ * If the controller is already suspended, then this must be a
+ * PM suspend. Remember this fact, so that we will leave the
+ * controller suspended at PM resume time.
+ */
+ if (pdata->suspended) {
+ dev_dbg(dev, "already suspended, leaving early\n");
+ pdata->already_suspended = 1;
+ return 0;
+ }
+
+ dev_dbg(dev, "suspending...\n");
+
+ hcd->state = HC_STATE_SUSPENDED;
+ dev->power.power_state = PMSG_SUSPEND;
+
+ /* ignore non-host interrupts */
+ clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
+
+ /* stop the controller */
+ tmp = ehci_readl(ehci, &ehci->regs->command);
+ tmp &= ~CMD_RUN;
+ ehci_writel(ehci, tmp, &ehci->regs->command);
+
+ /* save EHCI registers */
+ pdata->pm_command = ehci_readl(ehci, &ehci->regs->command);
+ pdata->pm_command &= ~CMD_RUN;
+ pdata->pm_status = ehci_readl(ehci, &ehci->regs->status);
+ pdata->pm_intr_enable = ehci_readl(ehci, &ehci->regs->intr_enable);
+ pdata->pm_frame_index = ehci_readl(ehci, &ehci->regs->frame_index);
+ pdata->pm_segment = ehci_readl(ehci, &ehci->regs->segment);
+ pdata->pm_frame_list = ehci_readl(ehci, &ehci->regs->frame_list);
+ pdata->pm_async_next = ehci_readl(ehci, &ehci->regs->async_next);
+ pdata->pm_configured_flag =
+ ehci_readl(ehci, &ehci->regs->configured_flag);
+ pdata->pm_portsc = ehci_readl(ehci, &ehci->regs->port_status[0]);
+ pdata->pm_usbgenctrl = ehci_readl(ehci,
+ hcd->regs + FSL_SOC_USB_USBGENCTRL);
+
+ /* clear the W1C bits */
+ pdata->pm_portsc &= cpu_to_hc32(ehci, ~PORT_RWC_BITS);
+
+ pdata->suspended = 1;
+
+ /* clear PP to cut power to the port */
+ tmp = ehci_readl(ehci, &ehci->regs->port_status[0]);
+ tmp &= ~PORT_POWER;
+ ehci_writel(ehci, tmp, &ehci->regs->port_status[0]);
+
+ return 0;
+}
+
+static int ehci_fsl_mpc512x_drv_resume(struct device *dev)
+{
+ struct usb_hcd *hcd = dev_get_drvdata(dev);
+ struct ehci_hcd *ehci = hcd_to_ehci(hcd);
+ struct fsl_usb2_platform_data *pdata = dev->platform_data;
+ u32 tmp;
+
+ dev_dbg(dev, "suspend=%d already_suspended=%d\n",
+ pdata->suspended, pdata->already_suspended);
+
+ /*
+ * If the controller was already suspended at suspend time,
+ * then don't resume it now.
+ */
+ if (pdata->already_suspended) {
+ dev_dbg(dev, "already suspended, leaving early\n");
+ pdata->already_suspended = 0;
+ return 0;
+ }
+
+ if (!pdata->suspended) {
+ dev_dbg(dev, "not suspended, leaving early\n");
+ return 0;
+ }
+
+ pdata->suspended = 0;
+
+ dev_dbg(dev, "resuming...\n");
+
+ /* set host mode */
+ tmp = USBMODE_CM_HOST | (pdata->es ? USBMODE_ES : 0);
+ ehci_writel(ehci, tmp, hcd->regs + FSL_SOC_USB_USBMODE);
+
+ ehci_writel(ehci, pdata->pm_usbgenctrl,
+ hcd->regs + FSL_SOC_USB_USBGENCTRL);
+ ehci_writel(ehci, ISIPHYCTRL_PXE | ISIPHYCTRL_PHYE,
+ hcd->regs + FSL_SOC_USB_ISIPHYCTRL);
+
+ /* restore EHCI registers */
+ ehci_writel(ehci, pdata->pm_command, &ehci->regs->command);
+ ehci_writel(ehci, pdata->pm_intr_enable, &ehci->regs->intr_enable);
+ ehci_writel(ehci, pdata->pm_frame_index, &ehci->regs->frame_index);
+ ehci_writel(ehci, pdata->pm_segment, &ehci->regs->segment);
+ ehci_writel(ehci, pdata->pm_frame_list, &ehci->regs->frame_list);
+ ehci_writel(ehci, pdata->pm_async_next, &ehci->regs->async_next);
+ ehci_writel(ehci, pdata->pm_configured_flag,
+ &ehci->regs->configured_flag);
+ ehci_writel(ehci, pdata->pm_portsc, &ehci->regs->port_status[0]);
+
+ set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
+ hcd->state = HC_STATE_RUNNING;
+ dev->power.power_state = PMSG_ON;
+
+ tmp = ehci_readl(ehci, &ehci->regs->command);
+ tmp |= CMD_RUN;
+ ehci_writel(ehci, tmp, &ehci->regs->command);
+
+ usb_hcd_resume_root_hub(hcd);
+
+ return 0;
+}
+#else
+static inline int ehci_fsl_mpc512x_drv_suspend(struct device *dev)
+{
+ return 0;
+}
+
+static inline int ehci_fsl_mpc512x_drv_resume(struct device *dev)
+{
+ return 0;
+}
+#endif /* CONFIG_PPC_MPC512x */
+
static struct ehci_fsl *hcd_to_ehci_fsl(struct usb_hcd *hcd)
{
struct ehci_hcd *ehci = hcd_to_ehci(hcd);
@@ -341,6 +517,11 @@
struct ehci_fsl *ehci_fsl = hcd_to_ehci_fsl(hcd);
void __iomem *non_ehci = hcd->regs;
+ if (of_device_is_compatible(dev->parent->of_node,
+ "fsl,mpc5121-usb2-dr")) {
+ return ehci_fsl_mpc512x_drv_suspend(dev);
+ }
+
ehci_prepare_ports_for_controller_suspend(hcd_to_ehci(hcd),
device_may_wakeup(dev));
if (!fsl_deep_sleep())
@@ -357,6 +538,11 @@
struct ehci_hcd *ehci = hcd_to_ehci(hcd);
void __iomem *non_ehci = hcd->regs;
+ if (of_device_is_compatible(dev->parent->of_node,
+ "fsl,mpc5121-usb2-dr")) {
+ return ehci_fsl_mpc512x_drv_resume(dev);
+ }
+
ehci_prepare_ports_for_controller_resume(ehci);
if (!fsl_deep_sleep())
return 0;
@@ -391,6 +577,38 @@
#define EHCI_FSL_PM_OPS NULL
#endif /* CONFIG_PM */
+#ifdef CONFIG_USB_OTG
+static int ehci_start_port_reset(struct usb_hcd *hcd, unsigned port)
+{
+ struct ehci_hcd *ehci = hcd_to_ehci(hcd);
+ u32 status;
+
+ if (!port)
+ return -EINVAL;
+
+ port--;
+
+ /* start port reset before HNP protocol time out */
+ status = readl(&ehci->regs->port_status[port]);
+ if (!(status & PORT_CONNECT))
+ return -ENODEV;
+
+ /* khubd will finish the reset later */
+ if (ehci_is_TDI(ehci)) {
+ writel(PORT_RESET |
+ (status & ~(PORT_CSC | PORT_PEC | PORT_OCC)),
+ &ehci->regs->port_status[port]);
+ } else {
+ writel(PORT_RESET, &ehci->regs->port_status[port]);
+ }
+
+ return 0;
+}
+#else
+#define ehci_start_port_reset NULL
+#endif /* CONFIG_USB_OTG */
+
+
static const struct hc_driver ehci_fsl_hc_driver = {
.description = hcd_name,
.product_desc = "Freescale On-Chip EHCI Host Controller",
@@ -430,6 +648,7 @@
.hub_control = ehci_hub_control,
.bus_suspend = ehci_bus_suspend,
.bus_resume = ehci_bus_resume,
+ .start_port_reset = ehci_start_port_reset,
.relinquish_port = ehci_relinquish_port,
.port_handed_over = ehci_port_handed_over,
diff --git a/drivers/usb/host/ehci-fsl.h b/drivers/usb/host/ehci-fsl.h
index 3fabed3..4918062 100644
--- a/drivers/usb/host/ehci-fsl.h
+++ b/drivers/usb/host/ehci-fsl.h
@@ -27,6 +27,10 @@
#define PORT_PTS_SERIAL (3<<30)
#define PORT_PTS_PTW (1<<28)
#define FSL_SOC_USB_PORTSC2 0x188
+#define FSL_SOC_USB_USBMODE 0x1a8
+#define USBMODE_CM_MASK (3 << 0) /* controller mode mask */
+#define USBMODE_CM_HOST (3 << 0) /* controller mode: host */
+#define USBMODE_ES (1 << 2) /* (Big) Endian Select */
#define FSL_SOC_USB_USBGENCTRL 0x200
#define USBGENCTRL_PPP (1 << 3)
diff --git a/drivers/usb/host/ehci-grlib.c b/drivers/usb/host/ehci-grlib.c
new file mode 100644
index 0000000..93b230d
--- /dev/null
+++ b/drivers/usb/host/ehci-grlib.c
@@ -0,0 +1,242 @@
+/*
+ * Driver for Aeroflex Gaisler GRLIB GRUSBHC EHCI host controller
+ *
+ * GRUSBHC is typically found on LEON/GRLIB SoCs
+ *
+ * (c) Jan Andersson <jan@gaisler.com>
+ *
+ * Based on ehci-ppc-of.c which is:
+ * (c) Valentine Barshak <vbarshak@ru.mvista.com>
+ * and in turn based on "ehci-ppc-soc.c" by Stefan Roese <sr@denx.de>
+ * and "ohci-ppc-of.c" by Sylvain Munaut <tnt@246tNt.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software Foundation,
+ * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+
+#include <linux/signal.h>
+
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+
+#define GRUSBHC_HCIVERSION 0x0100 /* Known value of cap. reg. HCIVERSION */
+
+/* called during probe() after chip reset completes */
+static int ehci_grlib_setup(struct usb_hcd *hcd)
+{
+ struct ehci_hcd *ehci = hcd_to_ehci(hcd);
+ int retval;
+
+ retval = ehci_halt(ehci);
+ if (retval)
+ return retval;
+
+ retval = ehci_init(hcd);
+ if (retval)
+ return retval;
+
+ ehci->sbrn = 0x20;
+ ehci_port_power(ehci, 1);
+
+ return ehci_reset(ehci);
+}
+
+
+static const struct hc_driver ehci_grlib_hc_driver = {
+ .description = hcd_name,
+ .product_desc = "GRLIB GRUSBHC EHCI",
+ .hcd_priv_size = sizeof(struct ehci_hcd),
+
+ /*
+ * generic hardware linkage
+ */
+ .irq = ehci_irq,
+ .flags = HCD_MEMORY | HCD_USB2,
+
+ /*
+ * basic lifecycle operations
+ */
+ .reset = ehci_grlib_setup,
+ .start = ehci_run,
+ .stop = ehci_stop,
+ .shutdown = ehci_shutdown,
+
+ /*
+ * managing i/o requests and associated device resources
+ */
+ .urb_enqueue = ehci_urb_enqueue,
+ .urb_dequeue = ehci_urb_dequeue,
+ .endpoint_disable = ehci_endpoint_disable,
+ .endpoint_reset = ehci_endpoint_reset,
+
+ /*
+ * scheduling support
+ */
+ .get_frame_number = ehci_get_frame,
+
+ /*
+ * root hub support
+ */
+ .hub_status_data = ehci_hub_status_data,
+ .hub_control = ehci_hub_control,
+#ifdef CONFIG_PM
+ .bus_suspend = ehci_bus_suspend,
+ .bus_resume = ehci_bus_resume,
+#endif
+ .relinquish_port = ehci_relinquish_port,
+ .port_handed_over = ehci_port_handed_over,
+
+ .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
+};
+
+
+static int __devinit ehci_hcd_grlib_probe(struct platform_device *op)
+{
+ struct device_node *dn = op->dev.of_node;
+ struct usb_hcd *hcd;
+ struct ehci_hcd *ehci = NULL;
+ struct resource res;
+ u32 hc_capbase;
+ int irq;
+ int rv;
+
+ if (usb_disabled())
+ return -ENODEV;
+
+ dev_dbg(&op->dev, "initializing GRUSBHC EHCI USB Controller\n");
+
+ rv = of_address_to_resource(dn, 0, &res);
+ if (rv)
+ return rv;
+
+ /* usb_create_hcd requires dma_mask != NULL */
+ op->dev.dma_mask = &op->dev.coherent_dma_mask;
+ hcd = usb_create_hcd(&ehci_grlib_hc_driver, &op->dev,
+ "GRUSBHC EHCI USB");
+ if (!hcd)
+ return -ENOMEM;
+
+ hcd->rsrc_start = res.start;
+ hcd->rsrc_len = res.end - res.start + 1;
+
+ if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) {
+ printk(KERN_ERR "%s: request_mem_region failed\n", __FILE__);
+ rv = -EBUSY;
+ goto err_rmr;
+ }
+
+ irq = irq_of_parse_and_map(dn, 0);
+ if (irq == NO_IRQ) {
+ printk(KERN_ERR "%s: irq_of_parse_and_map failed\n", __FILE__);
+ rv = -EBUSY;
+ goto err_irq;
+ }
+
+ hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
+ if (!hcd->regs) {
+ printk(KERN_ERR "%s: ioremap failed\n", __FILE__);
+ rv = -ENOMEM;
+ goto err_ioremap;
+ }
+
+ ehci = hcd_to_ehci(hcd);
+
+ ehci->caps = hcd->regs;
+
+ /* determine endianness of this implementation */
+ hc_capbase = ehci_readl(ehci, &ehci->caps->hc_capbase);
+ if (HC_VERSION(ehci, hc_capbase) != GRUSBHC_HCIVERSION) {
+ ehci->big_endian_mmio = 1;
+ ehci->big_endian_desc = 1;
+ ehci->big_endian_capbase = 1;
+ }
+
+ ehci->regs = hcd->regs +
+ HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
+
+ /* cache this readonly data; minimize chip reads */
+ ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
+
+ rv = usb_add_hcd(hcd, irq, 0);
+ if (rv)
+ goto err_ehci;
+
+ return 0;
+
+err_ehci:
+ iounmap(hcd->regs);
+err_ioremap:
+ irq_dispose_mapping(irq);
+err_irq:
+ release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
+err_rmr:
+ usb_put_hcd(hcd);
+
+ return rv;
+}
+
+
+static int ehci_hcd_grlib_remove(struct platform_device *op)
+{
+ struct usb_hcd *hcd = dev_get_drvdata(&op->dev);
+
+ dev_set_drvdata(&op->dev, NULL);
+
+ dev_dbg(&op->dev, "stopping GRLIB GRUSBHC EHCI USB Controller\n");
+
+ usb_remove_hcd(hcd);
+
+ iounmap(hcd->regs);
+ irq_dispose_mapping(hcd->irq);
+ release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
+
+ usb_put_hcd(hcd);
+
+ return 0;
+}
+
+
+static void ehci_hcd_grlib_shutdown(struct platform_device *op)
+{
+ struct usb_hcd *hcd = dev_get_drvdata(&op->dev);
+
+ if (hcd->driver->shutdown)
+ hcd->driver->shutdown(hcd);
+}
+
+
+static const struct of_device_id ehci_hcd_grlib_of_match[] = {
+ {
+ .name = "GAISLER_EHCI",
+ },
+ {
+ .name = "01_026",
+ },
+ {},
+};
+MODULE_DEVICE_TABLE(of, ehci_hcd_grlib_of_match);
+
+
+static struct platform_driver ehci_grlib_driver = {
+ .probe = ehci_hcd_grlib_probe,
+ .remove = ehci_hcd_grlib_remove,
+ .shutdown = ehci_hcd_grlib_shutdown,
+ .driver = {
+ .name = "grlib-ehci",
+ .owner = THIS_MODULE,
+ .of_match_table = ehci_hcd_grlib_of_match,
+ },
+};
diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c
index 78561d1..b435ed6 100644
--- a/drivers/usb/host/ehci-hcd.c
+++ b/drivers/usb/host/ehci-hcd.c
@@ -739,7 +739,7 @@
up_write(&ehci_cf_port_reset_rwsem);
ehci->last_periodic_enable = ktime_get_real();
- temp = HC_VERSION(ehci_readl(ehci, &ehci->caps->hc_capbase));
+ temp = HC_VERSION(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
ehci_info (ehci,
"USB %x.%x started, EHCI %x.%02x%s\n",
((ehci->sbrn & 0xf0)>>4), (ehci->sbrn & 0x0f),
@@ -777,8 +777,9 @@
goto dead;
}
+ /* Shared IRQ? */
masked_status = status & INTR_MASK;
- if (!masked_status) { /* irq sharing? */
+ if (!masked_status || unlikely(hcd->state == HC_STATE_HALT)) {
spin_unlock(&ehci->lock);
return IRQ_NONE;
}
@@ -873,6 +874,7 @@
dead:
ehci_reset(ehci);
ehci_writel(ehci, 0, &ehci->regs->configured_flag);
+ usb_hc_died(hcd);
/* generic layer kills/unlinks all urbs, then
* uses ehci_stop to clean up the rest
*/
@@ -1265,6 +1267,21 @@
#define PLATFORM_DRIVER tegra_ehci_driver
#endif
+#ifdef CONFIG_USB_EHCI_S5P
+#include "ehci-s5p.c"
+#define PLATFORM_DRIVER s5p_ehci_driver
+#endif
+
+#ifdef CONFIG_USB_EHCI_ATH79
+#include "ehci-ath79.c"
+#define PLATFORM_DRIVER ehci_ath79_driver
+#endif
+
+#ifdef CONFIG_SPARC_LEON
+#include "ehci-grlib.c"
+#define PLATFORM_DRIVER ehci_grlib_driver
+#endif
+
#if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER) && \
!defined(PS3_SYSTEM_BUS_DRIVER) && !defined(OF_PLATFORM_DRIVER) && \
!defined(XILINX_OF_PLATFORM_DRIVER)
diff --git a/drivers/usb/host/ehci-hub.c b/drivers/usb/host/ehci-hub.c
index d05ea03..ea6184b 100644
--- a/drivers/usb/host/ehci-hub.c
+++ b/drivers/usb/host/ehci-hub.c
@@ -27,6 +27,7 @@
*/
/*-------------------------------------------------------------------------*/
+#include <linux/usb/otg.h>
#define PORT_WAKE_BITS (PORT_WKOC_E|PORT_WKDISC_E|PORT_WKCONN_E)
@@ -127,7 +128,7 @@
return 0;
}
-static void ehci_adjust_port_wakeup_flags(struct ehci_hcd *ehci,
+static __maybe_unused void ehci_adjust_port_wakeup_flags(struct ehci_hcd *ehci,
bool suspending, bool do_wakeup)
{
int port;
@@ -801,6 +802,13 @@
goto error;
if (ehci->no_selective_suspend)
break;
+#ifdef CONFIG_USB_OTG
+ if ((hcd->self.otg_port == (wIndex + 1))
+ && hcd->self.b_hnp_enable) {
+ otg_start_hnp(ehci->transceiver);
+ break;
+ }
+#endif
if (!(temp & PORT_SUSPEND))
break;
if ((temp & PORT_PE) == 0)
diff --git a/drivers/usb/host/ehci-ixp4xx.c b/drivers/usb/host/ehci-ixp4xx.c
index 89b7c70..50e600d 100644
--- a/drivers/usb/host/ehci-ixp4xx.c
+++ b/drivers/usb/host/ehci-ixp4xx.c
@@ -23,7 +23,7 @@
ehci->caps = hcd->regs + 0x100;
ehci->regs = hcd->regs + 0x100
- + HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
+ + HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
hcd->has_tt = 1;
diff --git a/drivers/usb/host/ehci-msm.c b/drivers/usb/host/ehci-msm.c
index 9ce1b0b..b5a0bf6 100644
--- a/drivers/usb/host/ehci-msm.c
+++ b/drivers/usb/host/ehci-msm.c
@@ -41,7 +41,7 @@
ehci->caps = USB_CAPLENGTH;
ehci->regs = USB_CAPLENGTH +
- HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
+ HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
dbg_hcs_params(ehci, "reset");
dbg_hcc_params(ehci, "reset");
diff --git a/drivers/usb/host/ehci-mxc.c b/drivers/usb/host/ehci-mxc.c
index 25c8c10..0c058be 100644
--- a/drivers/usb/host/ehci-mxc.c
+++ b/drivers/usb/host/ehci-mxc.c
@@ -208,7 +208,7 @@
/* EHCI registers start at offset 0x100 */
ehci->caps = hcd->regs + 0x100;
ehci->regs = hcd->regs + 0x100 +
- HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
+ HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
/* set up the PORTSCx register */
ehci_writel(ehci, pdata->portsc, &ehci->regs->port_status[0]);
diff --git a/drivers/usb/host/ehci-octeon.c b/drivers/usb/host/ehci-octeon.c
index a31a031..ff55757 100644
--- a/drivers/usb/host/ehci-octeon.c
+++ b/drivers/usb/host/ehci-octeon.c
@@ -151,7 +151,7 @@
ehci->caps = hcd->regs;
ehci->regs = hcd->regs +
- HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
+ HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
/* cache this readonly data; minimize chip reads */
ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
diff --git a/drivers/usb/host/ehci-omap.c b/drivers/usb/host/ehci-omap.c
index 627f3a6..55a57c2 100644
--- a/drivers/usb/host/ehci-omap.c
+++ b/drivers/usb/host/ehci-omap.c
@@ -208,7 +208,7 @@
/* we know this is the memory we want, no need to ioremap again */
omap_ehci->caps = hcd->regs;
omap_ehci->regs = hcd->regs
- + HC_LENGTH(readl(&omap_ehci->caps->hc_capbase));
+ + HC_LENGTH(ehci, readl(&omap_ehci->caps->hc_capbase));
dbg_hcs_params(omap_ehci, "reset");
dbg_hcc_params(omap_ehci, "reset");
diff --git a/drivers/usb/host/ehci-orion.c b/drivers/usb/host/ehci-orion.c
index 281e094..395bdb0 100644
--- a/drivers/usb/host/ehci-orion.c
+++ b/drivers/usb/host/ehci-orion.c
@@ -251,7 +251,7 @@
ehci = hcd_to_ehci(hcd);
ehci->caps = hcd->regs + 0x100;
ehci->regs = hcd->regs + 0x100 +
- HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
+ HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
hcd->has_tt = 1;
ehci->sbrn = 0x20;
diff --git a/drivers/usb/host/ehci-pci.c b/drivers/usb/host/ehci-pci.c
index d5eaea7..660b80a 100644
--- a/drivers/usb/host/ehci-pci.c
+++ b/drivers/usb/host/ehci-pci.c
@@ -70,7 +70,7 @@
ehci->caps = hcd->regs;
ehci->regs = hcd->regs +
- HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
+ HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
dbg_hcs_params(ehci, "reset");
dbg_hcc_params(ehci, "reset");
diff --git a/drivers/usb/host/ehci-pmcmsp.c b/drivers/usb/host/ehci-pmcmsp.c
index a216864..cd69099 100644
--- a/drivers/usb/host/ehci-pmcmsp.c
+++ b/drivers/usb/host/ehci-pmcmsp.c
@@ -83,7 +83,7 @@
ehci->caps = hcd->regs;
ehci->regs = hcd->regs +
- HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
+ HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
dbg_hcs_params(ehci, "reset");
dbg_hcc_params(ehci, "reset");
diff --git a/drivers/usb/host/ehci-ppc-of.c b/drivers/usb/host/ehci-ppc-of.c
index 1f09f25..8552db6 100644
--- a/drivers/usb/host/ehci-ppc-of.c
+++ b/drivers/usb/host/ehci-ppc-of.c
@@ -179,7 +179,7 @@
ehci->caps = hcd->regs;
ehci->regs = hcd->regs +
- HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
+ HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
/* cache this readonly data; minimize chip reads */
ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
diff --git a/drivers/usb/host/ehci-ps3.c b/drivers/usb/host/ehci-ps3.c
index 1dee33b..64626a7 100644
--- a/drivers/usb/host/ehci-ps3.c
+++ b/drivers/usb/host/ehci-ps3.c
@@ -29,7 +29,7 @@
ehci->big_endian_mmio = 1;
ehci->caps = hcd->regs;
- ehci->regs = hcd->regs + HC_LENGTH(ehci_readl(ehci,
+ ehci->regs = hcd->regs + HC_LENGTH(ehci, ehci_readl(ehci,
&ehci->caps->hc_capbase));
dbg_hcs_params(ehci, "reset");
diff --git a/drivers/usb/host/ehci-q.c b/drivers/usb/host/ehci-q.c
index 42abd0f..5d6bc62 100644
--- a/drivers/usb/host/ehci-q.c
+++ b/drivers/usb/host/ehci-q.c
@@ -826,6 +826,7 @@
is_input, 0,
hb_mult(maxp) * max_packet(maxp)));
qh->start = NO_FRAME;
+ qh->stamp = ehci->periodic_stamp;
if (urb->dev->speed == USB_SPEED_HIGH) {
qh->c_usecs = 0;
@@ -1183,6 +1184,10 @@
ehci->reclaim = NULL;
start_unlink_async (ehci, next);
}
+
+ if (ehci->has_synopsys_hc_bug)
+ ehci_writel(ehci, (u32) ehci->async->qh_dma,
+ &ehci->regs->async_next);
}
/* makes sure the async qh will become idle */
diff --git a/drivers/usb/host/ehci-s5p.c b/drivers/usb/host/ehci-s5p.c
new file mode 100644
index 0000000..e3374c8
--- /dev/null
+++ b/drivers/usb/host/ehci-s5p.c
@@ -0,0 +1,202 @@
+/*
+ * SAMSUNG S5P USB HOST EHCI Controller
+ *
+ * Copyright (C) 2011 Samsung Electronics Co.Ltd
+ * Author: Jingoo Han <jg1.han@samsung.com>
+ * Author: Joonyoung Shim <jy0922.shim@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ */
+
+#include <linux/clk.h>
+#include <linux/platform_device.h>
+#include <mach/regs-pmu.h>
+#include <plat/cpu.h>
+#include <plat/ehci.h>
+#include <plat/usb-phy.h>
+
+struct s5p_ehci_hcd {
+ struct device *dev;
+ struct usb_hcd *hcd;
+ struct clk *clk;
+};
+
+static const struct hc_driver s5p_ehci_hc_driver = {
+ .description = hcd_name,
+ .product_desc = "S5P EHCI Host Controller",
+ .hcd_priv_size = sizeof(struct ehci_hcd),
+
+ .irq = ehci_irq,
+ .flags = HCD_MEMORY | HCD_USB2,
+
+ .reset = ehci_init,
+ .start = ehci_run,
+ .stop = ehci_stop,
+ .shutdown = ehci_shutdown,
+
+ .get_frame_number = ehci_get_frame,
+
+ .urb_enqueue = ehci_urb_enqueue,
+ .urb_dequeue = ehci_urb_dequeue,
+ .endpoint_disable = ehci_endpoint_disable,
+ .endpoint_reset = ehci_endpoint_reset,
+
+ .hub_status_data = ehci_hub_status_data,
+ .hub_control = ehci_hub_control,
+ .bus_suspend = ehci_bus_suspend,
+ .bus_resume = ehci_bus_resume,
+
+ .relinquish_port = ehci_relinquish_port,
+ .port_handed_over = ehci_port_handed_over,
+
+ .clear_tt_buffer_complete = ehci_clear_tt_buffer_complete,
+};
+
+static int __devinit s5p_ehci_probe(struct platform_device *pdev)
+{
+ struct s5p_ehci_platdata *pdata;
+ struct s5p_ehci_hcd *s5p_ehci;
+ struct usb_hcd *hcd;
+ struct ehci_hcd *ehci;
+ struct resource *res;
+ int irq;
+ int err;
+
+ pdata = pdev->dev.platform_data;
+ if (!pdata) {
+ dev_err(&pdev->dev, "No platform data defined\n");
+ return -EINVAL;
+ }
+
+ s5p_ehci = kzalloc(sizeof(struct s5p_ehci_hcd), GFP_KERNEL);
+ if (!s5p_ehci)
+ return -ENOMEM;
+
+ s5p_ehci->dev = &pdev->dev;
+
+ hcd = usb_create_hcd(&s5p_ehci_hc_driver, &pdev->dev,
+ dev_name(&pdev->dev));
+ if (!hcd) {
+ dev_err(&pdev->dev, "Unable to create HCD\n");
+ err = -ENOMEM;
+ goto fail_hcd;
+ }
+
+ s5p_ehci->clk = clk_get(&pdev->dev, "usbhost");
+
+ if (IS_ERR(s5p_ehci->clk)) {
+ dev_err(&pdev->dev, "Failed to get usbhost clock\n");
+ err = PTR_ERR(s5p_ehci->clk);
+ goto fail_clk;
+ }
+
+ err = clk_enable(s5p_ehci->clk);
+ if (err)
+ goto fail_clken;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ dev_err(&pdev->dev, "Failed to get I/O memory\n");
+ err = -ENXIO;
+ goto fail_io;
+ }
+
+ hcd->rsrc_start = res->start;
+ hcd->rsrc_len = resource_size(res);
+ hcd->regs = ioremap(res->start, resource_size(res));
+ if (!hcd->regs) {
+ dev_err(&pdev->dev, "Failed to remap I/O memory\n");
+ err = -ENOMEM;
+ goto fail_io;
+ }
+
+ irq = platform_get_irq(pdev, 0);
+ if (!irq) {
+ dev_err(&pdev->dev, "Failed to get IRQ\n");
+ err = -ENODEV;
+ goto fail;
+ }
+
+ if (pdata->phy_init)
+ pdata->phy_init(pdev, S5P_USB_PHY_HOST);
+
+ ehci = hcd_to_ehci(hcd);
+ ehci->caps = hcd->regs;
+ ehci->regs = hcd->regs +
+ HC_LENGTH(ehci, readl(&ehci->caps->hc_capbase));
+
+ dbg_hcs_params(ehci, "reset");
+ dbg_hcc_params(ehci, "reset");
+
+ /* cache this readonly data; minimize chip reads */
+ ehci->hcs_params = readl(&ehci->caps->hcs_params);
+
+ err = usb_add_hcd(hcd, irq, IRQF_DISABLED | IRQF_SHARED);
+ if (err) {
+ dev_err(&pdev->dev, "Failed to add USB HCD\n");
+ goto fail;
+ }
+
+ platform_set_drvdata(pdev, s5p_ehci);
+
+ return 0;
+
+fail:
+ iounmap(hcd->regs);
+fail_io:
+ clk_disable(s5p_ehci->clk);
+fail_clken:
+ clk_put(s5p_ehci->clk);
+fail_clk:
+ usb_put_hcd(hcd);
+fail_hcd:
+ kfree(s5p_ehci);
+ return err;
+}
+
+static int __devexit s5p_ehci_remove(struct platform_device *pdev)
+{
+ struct s5p_ehci_platdata *pdata = pdev->dev.platform_data;
+ struct s5p_ehci_hcd *s5p_ehci = platform_get_drvdata(pdev);
+ struct usb_hcd *hcd = s5p_ehci->hcd;
+
+ usb_remove_hcd(hcd);
+
+ if (pdata && pdata->phy_exit)
+ pdata->phy_exit(pdev, S5P_USB_PHY_HOST);
+
+ iounmap(hcd->regs);
+
+ clk_disable(s5p_ehci->clk);
+ clk_put(s5p_ehci->clk);
+
+ usb_put_hcd(hcd);
+ kfree(s5p_ehci);
+
+ return 0;
+}
+
+static void s5p_ehci_shutdown(struct platform_device *pdev)
+{
+ struct s5p_ehci_hcd *s5p_ehci = platform_get_drvdata(pdev);
+ struct usb_hcd *hcd = s5p_ehci->hcd;
+
+ if (hcd->driver->shutdown)
+ hcd->driver->shutdown(hcd);
+}
+
+static struct platform_driver s5p_ehci_driver = {
+ .probe = s5p_ehci_probe,
+ .remove = __devexit_p(s5p_ehci_remove),
+ .shutdown = s5p_ehci_shutdown,
+ .driver = {
+ .name = "s5p-ehci",
+ .owner = THIS_MODULE,
+ }
+};
+
+MODULE_ALIAS("platform:s5p-ehci");
diff --git a/drivers/usb/host/ehci-sched.c b/drivers/usb/host/ehci-sched.c
index 1543c83..6c9fbe3 100644
--- a/drivers/usb/host/ehci-sched.c
+++ b/drivers/usb/host/ehci-sched.c
@@ -471,8 +471,10 @@
*/
status = handshake_on_error_set_halt(ehci, &ehci->regs->status,
STS_PSS, 0, 9 * 125);
- if (status)
+ if (status) {
+ usb_hc_died(ehci_to_hcd(ehci));
return status;
+ }
cmd = ehci_readl(ehci, &ehci->regs->command) | CMD_PSE;
ehci_writel(ehci, cmd, &ehci->regs->command);
@@ -510,8 +512,10 @@
*/
status = handshake_on_error_set_halt(ehci, &ehci->regs->status,
STS_PSS, STS_PSS, 9 * 125);
- if (status)
+ if (status) {
+ usb_hc_died(ehci_to_hcd(ehci));
return status;
+ }
cmd = ehci_readl(ehci, &ehci->regs->command) & ~CMD_PSE;
ehci_writel(ehci, cmd, &ehci->regs->command);
@@ -2287,6 +2291,7 @@
}
clock &= mod - 1;
clock_frame = clock >> 3;
+ ++ehci->periodic_stamp;
for (;;) {
union ehci_shadow q, *q_p;
@@ -2315,10 +2320,14 @@
temp.qh = qh_get (q.qh);
type = Q_NEXT_TYPE(ehci, q.qh->hw->hw_next);
q = q.qh->qh_next;
- modified = qh_completions (ehci, temp.qh);
- if (unlikely(list_empty(&temp.qh->qtd_list) ||
- temp.qh->needs_rescan))
- intr_deschedule (ehci, temp.qh);
+ if (temp.qh->stamp != ehci->periodic_stamp) {
+ modified = qh_completions(ehci, temp.qh);
+ if (!modified)
+ temp.qh->stamp = ehci->periodic_stamp;
+ if (unlikely(list_empty(&temp.qh->qtd_list) ||
+ temp.qh->needs_rescan))
+ intr_deschedule(ehci, temp.qh);
+ }
qh_put (temp.qh);
break;
case Q_TYPE_FSTN:
@@ -2460,6 +2469,7 @@
if (ehci->clock_frame != clock_frame) {
free_cached_lists(ehci);
ehci->clock_frame = clock_frame;
+ ++ehci->periodic_stamp;
}
} else {
now_uframe++;
diff --git a/drivers/usb/host/ehci-sh.c b/drivers/usb/host/ehci-sh.c
index 595f70f..86a95bb 100644
--- a/drivers/usb/host/ehci-sh.c
+++ b/drivers/usb/host/ehci-sh.c
@@ -23,7 +23,7 @@
int ret;
ehci->caps = hcd->regs;
- ehci->regs = hcd->regs + HC_LENGTH(ehci_readl(ehci,
+ ehci->regs = hcd->regs + HC_LENGTH(ehci, ehci_readl(ehci,
&ehci->caps->hc_capbase));
dbg_hcs_params(ehci, "reset");
diff --git a/drivers/usb/host/ehci-spear.c b/drivers/usb/host/ehci-spear.c
index 75c0087..dbf1e4e 100644
--- a/drivers/usb/host/ehci-spear.c
+++ b/drivers/usb/host/ehci-spear.c
@@ -38,7 +38,7 @@
/* registers start at offset 0x0 */
ehci->caps = hcd->regs;
- ehci->regs = hcd->regs + HC_LENGTH(ehci_readl(ehci,
+ ehci->regs = hcd->regs + HC_LENGTH(ehci, ehci_readl(ehci,
&ehci->caps->hc_capbase));
/* cache this readonly data; minimize chip reads */
ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c
index a516af2..02b2bfd 100644
--- a/drivers/usb/host/ehci-tegra.c
+++ b/drivers/usb/host/ehci-tegra.c
@@ -58,6 +58,71 @@
clk_disable(tegra->emc_clk);
}
+static int tegra_ehci_internal_port_reset(
+ struct ehci_hcd *ehci,
+ u32 __iomem *portsc_reg
+)
+{
+ u32 temp;
+ unsigned long flags;
+ int retval = 0;
+ int i, tries;
+ u32 saved_usbintr;
+
+ spin_lock_irqsave(&ehci->lock, flags);
+ saved_usbintr = ehci_readl(ehci, &ehci->regs->intr_enable);
+ /* disable USB interrupt */
+ ehci_writel(ehci, 0, &ehci->regs->intr_enable);
+ spin_unlock_irqrestore(&ehci->lock, flags);
+
+ /*
+ * Here we have to do Port Reset at most twice for
+ * Port Enable bit to be set.
+ */
+ for (i = 0; i < 2; i++) {
+ temp = ehci_readl(ehci, portsc_reg);
+ temp |= PORT_RESET;
+ ehci_writel(ehci, temp, portsc_reg);
+ mdelay(10);
+ temp &= ~PORT_RESET;
+ ehci_writel(ehci, temp, portsc_reg);
+ mdelay(1);
+ tries = 100;
+ do {
+ mdelay(1);
+ /*
+ * Up to this point, Port Enable bit is
+ * expected to be set after 2 ms waiting.
+ * USB1 usually takes extra 45 ms, for safety,
+ * we take 100 ms as timeout.
+ */
+ temp = ehci_readl(ehci, portsc_reg);
+ } while (!(temp & PORT_PE) && tries--);
+ if (temp & PORT_PE)
+ break;
+ }
+ if (i == 2)
+ retval = -ETIMEDOUT;
+
+ /*
+ * Clear Connect Status Change bit if it's set.
+ * We can't clear PORT_PEC. It will also cause PORT_PE to be cleared.
+ */
+ if (temp & PORT_CSC)
+ ehci_writel(ehci, PORT_CSC, portsc_reg);
+
+ /*
+ * Write to clear any interrupt status bits that might be set
+ * during port reset.
+ */
+ temp = ehci_readl(ehci, &ehci->regs->status);
+ ehci_writel(ehci, temp, &ehci->regs->status);
+
+ /* restore original interrupt enable bits */
+ ehci_writel(ehci, saved_usbintr, &ehci->regs->intr_enable);
+ return retval;
+}
+
static int tegra_ehci_hub_control(
struct usb_hcd *hcd,
u16 typeReq,
@@ -121,6 +186,13 @@
goto done;
}
+ /* For USB1 port we need to issue Port Reset twice internally */
+ if (tegra->phy->instance == 0 &&
+ (typeReq == SetPortFeature && wValue == USB_PORT_FEAT_RESET)) {
+ spin_unlock_irqrestore(&ehci->lock, flags);
+ return tegra_ehci_internal_port_reset(ehci, status_reg);
+ }
+
/*
* Tegra host controller will time the resume operation to clear the bit
* when the port control state switches to HS or FS Idle. This behavior
@@ -328,7 +400,7 @@
/* EHCI registers start at offset 0x100 */
ehci->caps = hcd->regs + 0x100;
ehci->regs = hcd->regs + 0x100 +
- HC_LENGTH(readl(&ehci->caps->hc_capbase));
+ HC_LENGTH(ehci, readl(&ehci->caps->hc_capbase));
dbg_hcs_params(ehci, "reset");
dbg_hcc_params(ehci, "reset");
diff --git a/drivers/usb/host/ehci-vt8500.c b/drivers/usb/host/ehci-vt8500.c
index 2016806..47d7496 100644
--- a/drivers/usb/host/ehci-vt8500.c
+++ b/drivers/usb/host/ehci-vt8500.c
@@ -121,7 +121,8 @@
ehci = hcd_to_ehci(hcd);
ehci->caps = hcd->regs;
- ehci->regs = hcd->regs + HC_LENGTH(readl(&ehci->caps->hc_capbase));
+ ehci->regs = hcd->regs +
+ HC_LENGTH(ehci, readl(&ehci->caps->hc_capbase));
dbg_hcs_params(ehci, "reset");
dbg_hcc_params(ehci, "reset");
diff --git a/drivers/usb/host/ehci-w90x900.c b/drivers/usb/host/ehci-w90x900.c
index 6bc3580..52a027a 100644
--- a/drivers/usb/host/ehci-w90x900.c
+++ b/drivers/usb/host/ehci-w90x900.c
@@ -57,7 +57,7 @@
ehci = hcd_to_ehci(hcd);
ehci->caps = hcd->regs;
ehci->regs = hcd->regs +
- HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
+ HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
/* enable PHY 0,1,the regs only apply to w90p910
* 0xA4,0xA8 were offsets of PHY0 and PHY1 controller of
diff --git a/drivers/usb/host/ehci-xilinx-of.c b/drivers/usb/host/ehci-xilinx-of.c
index effc58d..a64d6d6 100644
--- a/drivers/usb/host/ehci-xilinx-of.c
+++ b/drivers/usb/host/ehci-xilinx-of.c
@@ -220,7 +220,7 @@
*/
ehci->caps = hcd->regs + 0x100;
ehci->regs = hcd->regs + 0x100 +
- HC_LENGTH(ehci_readl(ehci, &ehci->caps->hc_capbase));
+ HC_LENGTH(ehci, ehci_readl(ehci, &ehci->caps->hc_capbase));
/* cache this readonly data; minimize chip reads */
ehci->hcs_params = ehci_readl(ehci, &ehci->caps->hcs_params);
diff --git a/drivers/usb/host/ehci.h b/drivers/usb/host/ehci.h
index 333ddc1..bd6ff48 100644
--- a/drivers/usb/host/ehci.h
+++ b/drivers/usb/host/ehci.h
@@ -118,6 +118,7 @@
struct timer_list watchdog;
unsigned long actions;
unsigned stamp;
+ unsigned periodic_stamp;
unsigned random_frame;
unsigned long next_statechange;
ktime_t last_periodic_enable;
@@ -128,12 +129,14 @@
unsigned has_fsl_port_bug:1; /* FreeScale */
unsigned big_endian_mmio:1;
unsigned big_endian_desc:1;
+ unsigned big_endian_capbase:1;
unsigned has_amcc_usb23:1;
unsigned need_io_watchdog:1;
unsigned broken_periodic:1;
unsigned amd_pll_fix:1;
unsigned fs_i_thresh:1; /* Intel iso scheduling */
unsigned use_dummy_qh:1; /* AMD Frame List table quirk*/
+ unsigned has_synopsys_hc_bug:1; /* Synopsys HC */
/* required for usb32 quirk */
#define OHCI_CTRL_HCFS (3 << 6)
@@ -160,6 +163,10 @@
#ifdef DEBUG
struct dentry *debug_dir;
#endif
+ /*
+ * OTG controllers and transceivers need software interaction
+ */
+ struct otg_transceiver *transceiver;
};
/* convert between an HCD pointer and the corresponding EHCI_HCD */
@@ -600,12 +607,18 @@
* This attempts to support either format at compile time without a
* runtime penalty, or both formats with the additional overhead
* of checking a flag bit.
+ *
+ * ehci_big_endian_capbase is a special quirk for controllers that
+ * implement the HC capability registers as separate registers and not
+ * as fields of a 32-bit register.
*/
#ifdef CONFIG_USB_EHCI_BIG_ENDIAN_MMIO
#define ehci_big_endian_mmio(e) ((e)->big_endian_mmio)
+#define ehci_big_endian_capbase(e) ((e)->big_endian_capbase)
#else
#define ehci_big_endian_mmio(e) 0
+#define ehci_big_endian_capbase(e) 0
#endif
/*
diff --git a/drivers/usb/host/isp116x-hcd.c b/drivers/usb/host/isp116x-hcd.c
index c0e22f2..baae4cc 100644
--- a/drivers/usb/host/isp116x-hcd.c
+++ b/drivers/usb/host/isp116x-hcd.c
@@ -612,6 +612,7 @@
/* IRQ's are off, we do no DMA,
perfectly ready to die ... */
hcd->state = HC_STATE_HALT;
+ usb_hc_died(hcd);
ret = IRQ_HANDLED;
goto done;
}
diff --git a/drivers/usb/host/isp1760-hcd.c b/drivers/usb/host/isp1760-hcd.c
index 7b2e69a..c9e6e45 100644
--- a/drivers/usb/host/isp1760-hcd.c
+++ b/drivers/usb/host/isp1760-hcd.c
@@ -8,6 +8,8 @@
*
* (c) 2007 Sebastian Siewior <bigeasy@linutronix.de>
*
+ * (c) 2011 Arvid Brodin <arvid.brodin@enea.com>
+ *
*/
#include <linux/module.h>
#include <linux/kernel.h>
@@ -26,14 +28,18 @@
static struct kmem_cache *qtd_cachep;
static struct kmem_cache *qh_cachep;
+static struct kmem_cache *urb_listitem_cachep;
struct isp1760_hcd {
u32 hcs_params;
spinlock_t lock;
- struct inter_packet_info atl_ints[32];
- struct inter_packet_info int_ints[32];
+ struct slotinfo atl_slots[32];
+ int atl_done_map;
+ struct slotinfo int_slots[32];
+ int int_done_map;
struct memory_chunk memory_pool[BLOCKS];
- u32 atl_queued;
+ struct list_head controlqhs, bulkqhs, interruptqhs;
+ int active_ptds;
/* periodic schedule support */
#define DEFAULT_I_TDPS 1024
@@ -85,18 +91,34 @@
struct list_head qtd_list;
struct urb *urb;
size_t length;
+ size_t actual_length;
- /* isp special*/
+ /* QTD_ENQUEUED: waiting for transfer (inactive) */
+ /* QTD_PAYLOAD_ALLOC: chip mem has been allocated for payload */
+ /* QTD_XFER_STARTED: valid ptd has been written to isp176x - only
+ interrupt handler may touch this qtd! */
+ /* QTD_XFER_COMPLETE: payload has been transferred successfully */
+ /* QTD_RETIRE: transfer error/abort qtd */
+#define QTD_ENQUEUED 0
+#define QTD_PAYLOAD_ALLOC 1
+#define QTD_XFER_STARTED 2
+#define QTD_XFER_COMPLETE 3
+#define QTD_RETIRE 4
u32 status;
-#define URB_ENQUEUED (1 << 1)
};
+/* Queue head, one for each active endpoint */
struct isp1760_qh {
- /* first part defined by EHCI spec */
+ struct list_head qh_list;
struct list_head qtd_list;
-
u32 toggle;
u32 ping;
+ int slot;
+};
+
+struct urb_listitem {
+ struct list_head urb_list;
+ struct urb *urb;
};
/*
@@ -272,7 +294,7 @@
payload_addr += priv->memory_pool[curr + i].size;
}
- BUG_ON(payload_addr - priv->memory_pool[0].start > PAYLOAD_AREA_SIZE);
+ WARN_ON(payload_addr - priv->memory_pool[0].start > PAYLOAD_AREA_SIZE);
}
static void alloc_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd)
@@ -280,7 +302,7 @@
struct isp1760_hcd *priv = hcd_to_priv(hcd);
int i;
- BUG_ON(qtd->payload_addr);
+ WARN_ON(qtd->payload_addr);
if (!qtd->length)
return;
@@ -293,19 +315,6 @@
return;
}
}
-
- dev_err(hcd->self.controller,
- "%s: Cannot allocate %zu bytes of memory\n"
- "Current memory map:\n",
- __func__, qtd->length);
- for (i = 0; i < BLOCKS; i++) {
- dev_err(hcd->self.controller, "Pool %2d size %4d status: %d\n",
- i, priv->memory_pool[i].size,
- priv->memory_pool[i].free);
- }
- /* XXX maybe -ENOMEM could be possible */
- BUG();
- return;
}
static void free_mem(struct usb_hcd *hcd, struct isp1760_qtd *qtd)
@@ -318,7 +327,7 @@
for (i = 0; i < BLOCKS; i++) {
if (priv->memory_pool[i].start == qtd->payload_addr) {
- BUG_ON(priv->memory_pool[i].free);
+ WARN_ON(priv->memory_pool[i].free);
priv->memory_pool[i].free = 1;
qtd->payload_addr = 0;
return;
@@ -327,19 +336,8 @@
dev_err(hcd->self.controller, "%s: Invalid pointer: %08x\n",
__func__, qtd->payload_addr);
- BUG();
-}
-
-static void isp1760_init_regs(struct usb_hcd *hcd)
-{
- reg_write32(hcd->regs, HC_BUFFER_STATUS_REG, 0);
- reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
- reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
- reg_write32(hcd->regs, HC_ISO_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
-
- reg_write32(hcd->regs, HC_ATL_PTD_DONEMAP_REG, ~NO_TRANSFER_ACTIVE);
- reg_write32(hcd->regs, HC_INT_PTD_DONEMAP_REG, ~NO_TRANSFER_ACTIVE);
- reg_write32(hcd->regs, HC_ISO_PTD_DONEMAP_REG, ~NO_TRANSFER_ACTIVE);
+ WARN_ON(1);
+ qtd->payload_addr = 0;
}
static int handshake(struct usb_hcd *hcd, u32 reg,
@@ -377,31 +375,27 @@
return retval;
}
-static void qh_destroy(struct isp1760_qh *qh)
-{
- BUG_ON(!list_empty(&qh->qtd_list));
- kmem_cache_free(qh_cachep, qh);
-}
-
-static struct isp1760_qh *isp1760_qh_alloc(gfp_t flags)
+static struct isp1760_qh *qh_alloc(gfp_t flags)
{
struct isp1760_qh *qh;
qh = kmem_cache_zalloc(qh_cachep, flags);
if (!qh)
- return qh;
+ return NULL;
+ INIT_LIST_HEAD(&qh->qh_list);
INIT_LIST_HEAD(&qh->qtd_list);
+ qh->slot = -1;
+
return qh;
}
-/* magic numbers that can affect system performance */
-#define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
-#define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
-#define EHCI_TUNE_RL_TT 0
-#define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
-#define EHCI_TUNE_MULT_TT 1
-#define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */
+static void qh_free(struct isp1760_qh *qh)
+{
+ WARN_ON(!list_empty(&qh->qtd_list));
+ WARN_ON(qh->slot > -1);
+ kmem_cache_free(qh_cachep, qh);
+}
/* one-time init, only for memory state */
static int priv_init(struct usb_hcd *hcd)
@@ -411,6 +405,10 @@
spin_lock_init(&priv->lock);
+ INIT_LIST_HEAD(&priv->interruptqhs);
+ INIT_LIST_HEAD(&priv->controlqhs);
+ INIT_LIST_HEAD(&priv->bulkqhs);
+
/*
* hw default: 1K periodic list heads, one per frame.
* periodic_size can shrink by USBCMD update if hcc_params allows.
@@ -468,7 +466,10 @@
}
/* pre reset */
- isp1760_init_regs(hcd);
+ reg_write32(hcd->regs, HC_BUFFER_STATUS_REG, 0);
+ reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
+ reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
+ reg_write32(hcd->regs, HC_ISO_PTD_SKIPMAP_REG, NO_TRANSFER_ACTIVE);
/* reset */
reg_write32(hcd->regs, HC_RESET_REG, SW_RESET_RESET_ALL);
@@ -488,12 +489,15 @@
16 : 32, (priv->devflags & ISP1760_FLAG_ANALOG_OC) ?
"analog" : "digital");
+ /* This is weird: at the first plug-in of a device there seems to be
+ one packet queued that never gets returned? */
+ priv->active_ptds = -1;
+
/* ATL reset */
reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode | ALL_ATX_RESET);
mdelay(10);
reg_write32(hcd->regs, HC_HW_MODE_CTRL, hwmode);
- reg_write32(hcd->regs, HC_INTERRUPT_REG, INTERRUPT_ENABLE_MASK);
reg_write32(hcd->regs, HC_INTERRUPT_ENABLE, INTERRUPT_ENABLE_MASK);
/*
@@ -516,14 +520,21 @@
reg_write32(hcd->regs, HC_ATL_PTD_LASTPTD_REG, 0x80000000);
reg_write32(hcd->regs, HC_INT_PTD_LASTPTD_REG, 0x80000000);
reg_write32(hcd->regs, HC_ISO_PTD_LASTPTD_REG, 0x00000001);
+
+ reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, 0xffffffff);
+ reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, 0xffffffff);
+ reg_write32(hcd->regs, HC_ISO_PTD_SKIPMAP_REG, 0xffffffff);
+
+ reg_write32(hcd->regs, HC_BUFFER_STATUS_REG,
+ ATL_BUF_FILL | INT_BUF_FILL);
}
static void isp1760_enable_interrupts(struct usb_hcd *hcd)
{
reg_write32(hcd->regs, HC_ATL_IRQ_MASK_AND_REG, 0);
- reg_write32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG, 0);
+ reg_write32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG, 0xffffffff);
reg_write32(hcd->regs, HC_INT_IRQ_MASK_AND_REG, 0);
- reg_write32(hcd->regs, HC_INT_IRQ_MASK_OR_REG, 0);
+ reg_write32(hcd->regs, HC_INT_IRQ_MASK_OR_REG, 0xffffffff);
reg_write32(hcd->regs, HC_ISO_IRQ_MASK_AND_REG, 0);
reg_write32(hcd->regs, HC_ISO_IRQ_MASK_OR_REG, 0xffffffff);
/* step 23 passed */
@@ -548,8 +559,7 @@
command |= CMD_RUN;
reg_write32(hcd->regs, HC_USBCMD, command);
- retval = handshake(hcd, HC_USBCMD, CMD_RUN, CMD_RUN,
- 250 * 1000);
+ retval = handshake(hcd, HC_USBCMD, CMD_RUN, CMD_RUN, 250 * 1000);
if (retval)
return retval;
@@ -598,12 +608,19 @@
return (qtd->urb != urb);
}
-static void transform_into_atl(struct isp1760_qh *qh,
+/* magic numbers that can affect system performance */
+#define EHCI_TUNE_CERR 3 /* 0-3 qtd retries; 0 == don't stop */
+#define EHCI_TUNE_RL_HS 4 /* nak throttle; see 4.9 */
+#define EHCI_TUNE_RL_TT 0
+#define EHCI_TUNE_MULT_HS 1 /* 1-3 transactions/uframe; 4.10.3 */
+#define EHCI_TUNE_MULT_TT 1
+#define EHCI_TUNE_FLS 2 /* (small) 256 frame schedule */
+
+static void create_ptd_atl(struct isp1760_qh *qh,
struct isp1760_qtd *qtd, struct ptd *ptd)
{
u32 maxpacket;
u32 multi;
- u32 pid_code;
u32 rl = RL_COUNTER;
u32 nak = NAK_COUNTER;
@@ -616,67 +633,62 @@
maxpacket &= 0x7ff;
/* DW0 */
- ptd->dw0 = PTD_VALID;
- ptd->dw0 |= PTD_LENGTH(qtd->length);
- ptd->dw0 |= PTD_MAXPACKET(maxpacket);
- ptd->dw0 |= PTD_ENDPOINT(usb_pipeendpoint(qtd->urb->pipe));
+ ptd->dw0 = DW0_VALID_BIT;
+ ptd->dw0 |= TO_DW0_LENGTH(qtd->length);
+ ptd->dw0 |= TO_DW0_MAXPACKET(maxpacket);
+ ptd->dw0 |= TO_DW0_ENDPOINT(usb_pipeendpoint(qtd->urb->pipe));
/* DW1 */
ptd->dw1 = usb_pipeendpoint(qtd->urb->pipe) >> 1;
- ptd->dw1 |= PTD_DEVICE_ADDR(usb_pipedevice(qtd->urb->pipe));
-
- pid_code = qtd->packet_type;
- ptd->dw1 |= PTD_PID_TOKEN(pid_code);
+ ptd->dw1 |= TO_DW1_DEVICE_ADDR(usb_pipedevice(qtd->urb->pipe));
+ ptd->dw1 |= TO_DW1_PID_TOKEN(qtd->packet_type);
if (usb_pipebulk(qtd->urb->pipe))
- ptd->dw1 |= PTD_TRANS_BULK;
+ ptd->dw1 |= DW1_TRANS_BULK;
else if (usb_pipeint(qtd->urb->pipe))
- ptd->dw1 |= PTD_TRANS_INT;
+ ptd->dw1 |= DW1_TRANS_INT;
if (qtd->urb->dev->speed != USB_SPEED_HIGH) {
/* split transaction */
- ptd->dw1 |= PTD_TRANS_SPLIT;
+ ptd->dw1 |= DW1_TRANS_SPLIT;
if (qtd->urb->dev->speed == USB_SPEED_LOW)
- ptd->dw1 |= PTD_SE_USB_LOSPEED;
+ ptd->dw1 |= DW1_SE_USB_LOSPEED;
- ptd->dw1 |= PTD_PORT_NUM(qtd->urb->dev->ttport);
- ptd->dw1 |= PTD_HUB_NUM(qtd->urb->dev->tt->hub->devnum);
+ ptd->dw1 |= TO_DW1_PORT_NUM(qtd->urb->dev->ttport);
+ ptd->dw1 |= TO_DW1_HUB_NUM(qtd->urb->dev->tt->hub->devnum);
/* SE bit for Split INT transfers */
if (usb_pipeint(qtd->urb->pipe) &&
(qtd->urb->dev->speed == USB_SPEED_LOW))
ptd->dw1 |= 2 << 16;
- ptd->dw3 = 0;
rl = 0;
nak = 0;
} else {
- ptd->dw0 |= PTD_MULTI(multi);
+ ptd->dw0 |= TO_DW0_MULTI(multi);
if (usb_pipecontrol(qtd->urb->pipe) ||
usb_pipebulk(qtd->urb->pipe))
- ptd->dw3 = qh->ping;
- else
- ptd->dw3 = 0;
+ ptd->dw3 |= TO_DW3_PING(qh->ping);
}
/* DW2 */
ptd->dw2 = 0;
- ptd->dw2 |= PTD_DATA_START_ADDR(base_to_chip(qtd->payload_addr));
- ptd->dw2 |= PTD_RL_CNT(rl);
- ptd->dw3 |= PTD_NAC_CNT(nak);
+ ptd->dw2 |= TO_DW2_DATA_START_ADDR(base_to_chip(qtd->payload_addr));
+ ptd->dw2 |= TO_DW2_RL(rl);
/* DW3 */
- ptd->dw3 |= qh->toggle;
+ ptd->dw3 |= TO_DW3_NAKCOUNT(nak);
+ ptd->dw3 |= TO_DW3_DATA_TOGGLE(qh->toggle);
if (usb_pipecontrol(qtd->urb->pipe)) {
if (qtd->data_buffer == qtd->urb->setup_packet)
- ptd->dw3 &= ~PTD_DATA_TOGGLE(1);
+ ptd->dw3 &= ~TO_DW3_DATA_TOGGLE(1);
else if (last_qtd_of_urb(qtd, qh))
- ptd->dw3 |= PTD_DATA_TOGGLE(1);
+ ptd->dw3 |= TO_DW3_DATA_TOGGLE(1);
}
- ptd->dw3 |= PTD_ACTIVE;
+ ptd->dw3 |= DW3_ACTIVE_BIT;
/* Cerr */
- ptd->dw3 |= PTD_CERR(ERR_COUNTER);
+ ptd->dw3 |= TO_DW3_CERR(ERR_COUNTER);
}
static void transform_add_int(struct isp1760_qh *qh,
@@ -731,197 +743,13 @@
ptd->dw4 = usof;
}
-static void transform_into_int(struct isp1760_qh *qh,
+static void create_ptd_int(struct isp1760_qh *qh,
struct isp1760_qtd *qtd, struct ptd *ptd)
{
- transform_into_atl(qh, qtd, ptd);
+ create_ptd_atl(qh, qtd, ptd);
transform_add_int(qh, qtd, ptd);
}
-static int qtd_fill(struct isp1760_qtd *qtd, void *databuffer, size_t len,
- u32 token)
-{
- int count;
-
- qtd->data_buffer = databuffer;
- qtd->packet_type = GET_QTD_TOKEN_TYPE(token);
-
- if (len > MAX_PAYLOAD_SIZE)
- count = MAX_PAYLOAD_SIZE;
- else
- count = len;
-
- qtd->length = count;
- return count;
-}
-
-static int check_error(struct usb_hcd *hcd, struct ptd *ptd)
-{
- int error = 0;
-
- if (ptd->dw3 & DW3_HALT_BIT) {
- error = -EPIPE;
-
- if (ptd->dw3 & DW3_ERROR_BIT)
- pr_err("error bit is set in DW3\n");
- }
-
- if (ptd->dw3 & DW3_QTD_ACTIVE) {
- dev_err(hcd->self.controller, "Transfer active bit is set DW3\n"
- "nak counter: %d, rl: %d\n",
- (ptd->dw3 >> 19) & 0xf, (ptd->dw2 >> 25) & 0xf);
- }
-
- return error;
-}
-
-static void check_int_err_status(struct usb_hcd *hcd, u32 dw4)
-{
- u32 i;
-
- dw4 >>= 8;
-
- for (i = 0; i < 8; i++) {
- switch (dw4 & 0x7) {
- case INT_UNDERRUN:
- dev_err(hcd->self.controller, "Underrun (%d)\n", i);
- break;
-
- case INT_EXACT:
- dev_err(hcd->self.controller,
- "Transaction error (%d)\n", i);
- break;
-
- case INT_BABBLE:
- dev_err(hcd->self.controller, "Babble error (%d)\n", i);
- break;
- }
- dw4 >>= 3;
- }
-}
-
-static void enqueue_one_qtd(struct usb_hcd *hcd, struct isp1760_qtd *qtd)
-{
- if (qtd->length && (qtd->length <= MAX_PAYLOAD_SIZE)) {
- switch (qtd->packet_type) {
- case IN_PID:
- break;
- case OUT_PID:
- case SETUP_PID:
- mem_writes8(hcd->regs, qtd->payload_addr,
- qtd->data_buffer, qtd->length);
- }
- }
-}
-
-static void enqueue_one_atl_qtd(struct usb_hcd *hcd, struct isp1760_qh *qh,
- u32 slot, struct isp1760_qtd *qtd)
-{
- struct isp1760_hcd *priv = hcd_to_priv(hcd);
- struct ptd ptd;
-
- alloc_mem(hcd, qtd);
- transform_into_atl(qh, qtd, &ptd);
- ptd_write(hcd->regs, ATL_PTD_OFFSET, slot, &ptd);
- enqueue_one_qtd(hcd, qtd);
-
- priv->atl_ints[slot].qh = qh;
- priv->atl_ints[slot].qtd = qtd;
- qtd->status |= URB_ENQUEUED;
- qtd->status |= slot << 16;
-}
-
-static void enqueue_one_int_qtd(struct usb_hcd *hcd, struct isp1760_qh *qh,
- u32 slot, struct isp1760_qtd *qtd)
-{
- struct isp1760_hcd *priv = hcd_to_priv(hcd);
- struct ptd ptd;
-
- alloc_mem(hcd, qtd);
- transform_into_int(qh, qtd, &ptd);
- ptd_write(hcd->regs, INT_PTD_OFFSET, slot, &ptd);
- enqueue_one_qtd(hcd, qtd);
-
- priv->int_ints[slot].qh = qh;
- priv->int_ints[slot].qtd = qtd;
- qtd->status |= URB_ENQUEUED;
- qtd->status |= slot << 16;
-}
-
-static void enqueue_an_ATL_packet(struct usb_hcd *hcd, struct isp1760_qh *qh,
- struct isp1760_qtd *qtd)
-{
- struct isp1760_hcd *priv = hcd_to_priv(hcd);
- u32 skip_map, or_map;
- u32 slot;
- u32 buffstatus;
-
- /*
- * When this function is called from the interrupt handler to enqueue
- * a follow-up packet, the SKIP register gets written and read back
- * almost immediately. With ISP1761, this register requires a delay of
- * 195ns between a write and subsequent read (see section 15.1.1.3).
- */
- mmiowb();
- ndelay(195);
- skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
-
- BUG_ON(!skip_map);
- slot = __ffs(skip_map);
-
- enqueue_one_atl_qtd(hcd, qh, slot, qtd);
-
- or_map = reg_read32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG);
- or_map |= (1 << slot);
- reg_write32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG, or_map);
-
- skip_map &= ~(1 << slot);
- reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map);
-
- priv->atl_queued++;
- if (priv->atl_queued == 2)
- reg_write32(hcd->regs, HC_INTERRUPT_ENABLE,
- INTERRUPT_ENABLE_SOT_MASK);
-
- buffstatus = reg_read32(hcd->regs, HC_BUFFER_STATUS_REG);
- buffstatus |= ATL_BUFFER;
- reg_write32(hcd->regs, HC_BUFFER_STATUS_REG, buffstatus);
-}
-
-static void enqueue_an_INT_packet(struct usb_hcd *hcd, struct isp1760_qh *qh,
- struct isp1760_qtd *qtd)
-{
- u32 skip_map, or_map;
- u32 slot;
- u32 buffstatus;
-
- /*
- * When this function is called from the interrupt handler to enqueue
- * a follow-up packet, the SKIP register gets written and read back
- * almost immediately. With ISP1761, this register requires a delay of
- * 195ns between a write and subsequent read (see section 15.1.1.3).
- */
- mmiowb();
- ndelay(195);
- skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
-
- BUG_ON(!skip_map);
- slot = __ffs(skip_map);
-
- enqueue_one_int_qtd(hcd, qh, slot, qtd);
-
- or_map = reg_read32(hcd->regs, HC_INT_IRQ_MASK_OR_REG);
- or_map |= (1 << slot);
- reg_write32(hcd->regs, HC_INT_IRQ_MASK_OR_REG, or_map);
-
- skip_map &= ~(1 << slot);
- reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map);
-
- buffstatus = reg_read32(hcd->regs, HC_BUFFER_STATUS_REG);
- buffstatus |= INT_BUFFER;
- reg_write32(hcd->regs, HC_BUFFER_STATUS_REG, buffstatus);
-}
-
static void isp1760_urb_done(struct usb_hcd *hcd, struct urb *urb)
__releases(priv->lock)
__acquires(priv->lock)
@@ -948,557 +776,654 @@
spin_lock(&priv->lock);
}
-static void isp1760_qtd_free(struct isp1760_qtd *qtd)
-{
- BUG_ON(qtd->payload_addr);
- kmem_cache_free(qtd_cachep, qtd);
-}
-
-static struct isp1760_qtd *clean_this_qtd(struct isp1760_qtd *qtd,
- struct isp1760_qh *qh)
-{
- struct isp1760_qtd *tmp_qtd;
-
- if (list_is_last(&qtd->qtd_list, &qh->qtd_list))
- tmp_qtd = NULL;
- else
- tmp_qtd = list_entry(qtd->qtd_list.next, struct isp1760_qtd,
- qtd_list);
- list_del(&qtd->qtd_list);
- isp1760_qtd_free(qtd);
- return tmp_qtd;
-}
-
-/*
- * Remove this QTD from the QH list and free its memory. If this QTD
- * isn't the last one than remove also his successor(s).
- * Returns the QTD which is part of an new URB and should be enqueued.
- */
-static struct isp1760_qtd *clean_up_qtdlist(struct isp1760_qtd *qtd,
- struct isp1760_qh *qh)
-{
- struct urb *urb;
-
- urb = qtd->urb;
- do {
- qtd = clean_this_qtd(qtd, qh);
- } while (qtd && (qtd->urb == urb));
-
- return qtd;
-}
-
-static void do_atl_int(struct usb_hcd *hcd)
-{
- struct isp1760_hcd *priv = hcd_to_priv(hcd);
- u32 done_map, skip_map;
- struct ptd ptd;
- struct urb *urb;
- u32 slot;
- u32 length;
- u32 or_map;
- u32 status = -EINVAL;
- int error;
- struct isp1760_qtd *qtd;
- struct isp1760_qh *qh;
- u32 rl;
- u32 nakcount;
-
- done_map = reg_read32(hcd->regs, HC_ATL_PTD_DONEMAP_REG);
- skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
-
- or_map = reg_read32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG);
- or_map &= ~done_map;
- reg_write32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG, or_map);
-
- while (done_map) {
- status = 0;
- priv->atl_queued--;
-
- slot = __ffs(done_map);
- done_map &= ~(1 << slot);
- skip_map |= (1 << slot);
-
- qtd = priv->atl_ints[slot].qtd;
- qh = priv->atl_ints[slot].qh;
-
- if (!qh) {
- dev_err(hcd->self.controller, "qh is 0\n");
- continue;
- }
- ptd_read(hcd->regs, ATL_PTD_OFFSET, slot, &ptd);
-
- rl = (ptd.dw2 >> 25) & 0x0f;
- nakcount = (ptd.dw3 >> 19) & 0xf;
-
- /* Transfer Error, *but* active and no HALT -> reload */
- if ((ptd.dw3 & DW3_ERROR_BIT) && (ptd.dw3 & DW3_QTD_ACTIVE) &&
- !(ptd.dw3 & DW3_HALT_BIT)) {
-
- /* according to ppriv code, we have to
- * reload this one if trasfered bytes != requested bytes
- * else act like everything went smooth..
- * XXX This just doesn't feel right and hasn't
- * triggered so far.
- */
-
- length = PTD_XFERRED_LENGTH(ptd.dw3);
- dev_err(hcd->self.controller,
- "Should reload now... transferred %d "
- "of %zu\n", length, qtd->length);
- BUG();
- }
-
- if (!nakcount && (ptd.dw3 & DW3_QTD_ACTIVE)) {
- u32 buffstatus;
-
- /*
- * NAKs are handled in HW by the chip. Usually if the
- * device is not able to send data fast enough.
- * This happens mostly on slower hardware.
- */
-
- /* RL counter = ERR counter */
- ptd.dw3 &= ~(0xf << 19);
- ptd.dw3 |= rl << 19;
- ptd.dw3 &= ~(3 << (55 - 32));
- ptd.dw3 |= ERR_COUNTER << (55 - 32);
-
- /*
- * It is not needed to write skip map back because it
- * is unchanged. Just make sure that this entry is
- * unskipped once it gets written to the HW.
- */
- skip_map &= ~(1 << slot);
- or_map = reg_read32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG);
- or_map |= 1 << slot;
- reg_write32(hcd->regs, HC_ATL_IRQ_MASK_OR_REG, or_map);
-
- ptd.dw0 |= PTD_VALID;
- ptd_write(hcd->regs, ATL_PTD_OFFSET, slot, &ptd);
-
- priv->atl_queued++;
- if (priv->atl_queued == 2)
- reg_write32(hcd->regs, HC_INTERRUPT_ENABLE,
- INTERRUPT_ENABLE_SOT_MASK);
-
- buffstatus = reg_read32(hcd->regs,
- HC_BUFFER_STATUS_REG);
- buffstatus |= ATL_BUFFER;
- reg_write32(hcd->regs, HC_BUFFER_STATUS_REG,
- buffstatus);
- continue;
- }
-
- error = check_error(hcd, &ptd);
- if (error) {
- status = error;
- priv->atl_ints[slot].qh->toggle = 0;
- priv->atl_ints[slot].qh->ping = 0;
- qtd->urb->status = -EPIPE;
-
-#if 0
- printk(KERN_ERR "Error in %s().\n", __func__);
- printk(KERN_ERR "IN dw0: %08x dw1: %08x dw2: %08x "
- "dw3: %08x dw4: %08x dw5: %08x dw6: "
- "%08x dw7: %08x\n",
- ptd.dw0, ptd.dw1, ptd.dw2, ptd.dw3,
- ptd.dw4, ptd.dw5, ptd.dw6, ptd.dw7);
-#endif
- } else {
- priv->atl_ints[slot].qh->toggle = ptd.dw3 & (1 << 25);
- priv->atl_ints[slot].qh->ping = ptd.dw3 & (1 << 26);
- }
-
- length = PTD_XFERRED_LENGTH(ptd.dw3);
- if (length) {
- switch (DW1_GET_PID(ptd.dw1)) {
- case IN_PID:
- mem_reads8(hcd->regs, qtd->payload_addr,
- qtd->data_buffer, length);
-
- case OUT_PID:
-
- qtd->urb->actual_length += length;
-
- case SETUP_PID:
- break;
- }
- }
-
- priv->atl_ints[slot].qtd = NULL;
- priv->atl_ints[slot].qh = NULL;
-
- free_mem(hcd, qtd);
-
- reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map);
-
- if (qtd->urb->status == -EPIPE) {
- /* HALT was received */
-
- urb = qtd->urb;
- qtd = clean_up_qtdlist(qtd, qh);
- isp1760_urb_done(hcd, urb);
-
- } else if (usb_pipebulk(qtd->urb->pipe) &&
- (length < qtd->length)) {
- /* short BULK received */
-
- if (qtd->urb->transfer_flags & URB_SHORT_NOT_OK) {
- qtd->urb->status = -EREMOTEIO;
- dev_dbg(hcd->self.controller,
- "short bulk, %d instead %zu "
- "with URB_SHORT_NOT_OK flag.\n",
- length, qtd->length);
- }
-
- if (qtd->urb->status == -EINPROGRESS)
- qtd->urb->status = 0;
-
- urb = qtd->urb;
- qtd = clean_up_qtdlist(qtd, qh);
- isp1760_urb_done(hcd, urb);
-
- } else if (last_qtd_of_urb(qtd, qh)) {
- /* that was the last qtd of that URB */
-
- if (qtd->urb->status == -EINPROGRESS)
- qtd->urb->status = 0;
-
- urb = qtd->urb;
- qtd = clean_up_qtdlist(qtd, qh);
- isp1760_urb_done(hcd, urb);
-
- } else {
- /* next QTD of this URB */
-
- qtd = clean_this_qtd(qtd, qh);
- BUG_ON(!qtd);
- }
-
- if (qtd)
- enqueue_an_ATL_packet(hcd, qh, qtd);
-
- skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
- }
- if (priv->atl_queued <= 1)
- reg_write32(hcd->regs, HC_INTERRUPT_ENABLE,
- INTERRUPT_ENABLE_MASK);
-}
-
-static void do_intl_int(struct usb_hcd *hcd)
-{
- struct isp1760_hcd *priv = hcd_to_priv(hcd);
- u32 done_map, skip_map;
- struct ptd ptd;
- struct urb *urb;
- u32 length;
- u32 or_map;
- int error;
- u32 slot;
- struct isp1760_qtd *qtd;
- struct isp1760_qh *qh;
-
- done_map = reg_read32(hcd->regs, HC_INT_PTD_DONEMAP_REG);
- skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
-
- or_map = reg_read32(hcd->regs, HC_INT_IRQ_MASK_OR_REG);
- or_map &= ~done_map;
- reg_write32(hcd->regs, HC_INT_IRQ_MASK_OR_REG, or_map);
-
- while (done_map) {
- slot = __ffs(done_map);
- done_map &= ~(1 << slot);
- skip_map |= (1 << slot);
-
- qtd = priv->int_ints[slot].qtd;
- qh = priv->int_ints[slot].qh;
-
- if (!qh) {
- dev_err(hcd->self.controller, "(INT) qh is 0\n");
- continue;
- }
-
- ptd_read(hcd->regs, INT_PTD_OFFSET, slot, &ptd);
- check_int_err_status(hcd, ptd.dw4);
-
- error = check_error(hcd, &ptd);
- if (error) {
-#if 0
- printk(KERN_ERR "Error in %s().\n", __func__);
- printk(KERN_ERR "IN dw0: %08x dw1: %08x dw2: %08x "
- "dw3: %08x dw4: %08x dw5: %08x dw6: "
- "%08x dw7: %08x\n",
- ptd.dw0, ptd.dw1, ptd.dw2, ptd.dw3,
- ptd.dw4, ptd.dw5, ptd.dw6, ptd.dw7);
-#endif
- qtd->urb->status = -EPIPE;
- priv->int_ints[slot].qh->toggle = 0;
- priv->int_ints[slot].qh->ping = 0;
-
- } else {
- priv->int_ints[slot].qh->toggle = ptd.dw3 & (1 << 25);
- priv->int_ints[slot].qh->ping = ptd.dw3 & (1 << 26);
- }
-
- if (qtd->urb->dev->speed != USB_SPEED_HIGH)
- length = PTD_XFERRED_LENGTH_LO(ptd.dw3);
- else
- length = PTD_XFERRED_LENGTH(ptd.dw3);
-
- if (length) {
- switch (DW1_GET_PID(ptd.dw1)) {
- case IN_PID:
- mem_reads8(hcd->regs, qtd->payload_addr,
- qtd->data_buffer, length);
- case OUT_PID:
-
- qtd->urb->actual_length += length;
-
- case SETUP_PID:
- break;
- }
- }
-
- priv->int_ints[slot].qtd = NULL;
- priv->int_ints[slot].qh = NULL;
-
- reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map);
- free_mem(hcd, qtd);
-
- if (qtd->urb->status == -EPIPE) {
- /* HALT received */
-
- urb = qtd->urb;
- qtd = clean_up_qtdlist(qtd, qh);
- isp1760_urb_done(hcd, urb);
-
- } else if (last_qtd_of_urb(qtd, qh)) {
-
- if (qtd->urb->status == -EINPROGRESS)
- qtd->urb->status = 0;
-
- urb = qtd->urb;
- qtd = clean_up_qtdlist(qtd, qh);
- isp1760_urb_done(hcd, urb);
-
- } else {
- /* next QTD of this URB */
-
- qtd = clean_this_qtd(qtd, qh);
- BUG_ON(!qtd);
- }
-
- if (qtd)
- enqueue_an_INT_packet(hcd, qh, qtd);
-
- skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
- }
-}
-
-static struct isp1760_qh *qh_make(struct usb_hcd *hcd, struct urb *urb,
- gfp_t flags)
-{
- struct isp1760_qh *qh;
- int is_input, type;
-
- qh = isp1760_qh_alloc(flags);
- if (!qh)
- return qh;
-
- /*
- * init endpoint/device data for this QH
- */
- is_input = usb_pipein(urb->pipe);
- type = usb_pipetype(urb->pipe);
-
- if (!usb_pipecontrol(urb->pipe))
- usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe), !is_input,
- 1);
- return qh;
-}
-
-/*
- * For control/bulk/interrupt, return QH with these TDs appended.
- * Allocates and initializes the QH if necessary.
- * Returns null if it can't allocate a QH it needs to.
- * If the QH has TDs (urbs) already, that's great.
- */
-static struct isp1760_qh *qh_append_tds(struct usb_hcd *hcd,
- struct urb *urb, struct list_head *qtd_list, int epnum,
- void **ptr)
-{
- struct isp1760_qh *qh;
-
- qh = (struct isp1760_qh *)*ptr;
- if (!qh) {
- /* can't sleep here, we have priv->lock... */
- qh = qh_make(hcd, urb, GFP_ATOMIC);
- if (!qh)
- return qh;
- *ptr = qh;
- }
-
- list_splice(qtd_list, qh->qtd_list.prev);
-
- return qh;
-}
-
-static void qtd_list_free(struct urb *urb, struct list_head *qtd_list)
-{
- struct list_head *entry, *temp;
-
- list_for_each_safe(entry, temp, qtd_list) {
- struct isp1760_qtd *qtd;
-
- qtd = list_entry(entry, struct isp1760_qtd, qtd_list);
- list_del(&qtd->qtd_list);
- isp1760_qtd_free(qtd);
- }
-}
-
-static int isp1760_prepare_enqueue(struct usb_hcd *hcd, struct urb *urb,
- struct list_head *qtd_list, gfp_t mem_flags, packet_enqueue *p)
-{
- struct isp1760_hcd *priv = hcd_to_priv(hcd);
- struct isp1760_qtd *qtd;
- int epnum;
- unsigned long flags;
- struct isp1760_qh *qh = NULL;
- int rc;
- int qh_busy;
-
- qtd = list_entry(qtd_list->next, struct isp1760_qtd, qtd_list);
- epnum = urb->ep->desc.bEndpointAddress;
-
- spin_lock_irqsave(&priv->lock, flags);
- if (!HCD_HW_ACCESSIBLE(hcd)) {
- rc = -ESHUTDOWN;
- goto done;
- }
- rc = usb_hcd_link_urb_to_ep(hcd, urb);
- if (rc)
- goto done;
-
- qh = urb->ep->hcpriv;
- if (qh)
- qh_busy = !list_empty(&qh->qtd_list);
- else
- qh_busy = 0;
-
- qh = qh_append_tds(hcd, urb, qtd_list, epnum, &urb->ep->hcpriv);
- if (!qh) {
- usb_hcd_unlink_urb_from_ep(hcd, urb);
- rc = -ENOMEM;
- goto done;
- }
-
- if (!qh_busy)
- p(hcd, qh, qtd);
-
-done:
- spin_unlock_irqrestore(&priv->lock, flags);
- if (!qh)
- qtd_list_free(urb, qtd_list);
- return rc;
-}
-
-static struct isp1760_qtd *isp1760_qtd_alloc(gfp_t flags)
+static struct isp1760_qtd *qtd_alloc(gfp_t flags, struct urb *urb,
+ u8 packet_type)
{
struct isp1760_qtd *qtd;
qtd = kmem_cache_zalloc(qtd_cachep, flags);
- if (qtd)
- INIT_LIST_HEAD(&qtd->qtd_list);
+ if (!qtd)
+ return NULL;
+
+ INIT_LIST_HEAD(&qtd->qtd_list);
+ qtd->urb = urb;
+ qtd->packet_type = packet_type;
+ qtd->status = QTD_ENQUEUED;
+ qtd->actual_length = 0;
return qtd;
}
+static void qtd_free(struct isp1760_qtd *qtd)
+{
+ WARN_ON(qtd->payload_addr);
+ kmem_cache_free(qtd_cachep, qtd);
+}
+
+static void start_bus_transfer(struct usb_hcd *hcd, u32 ptd_offset, int slot,
+ struct slotinfo *slots, struct isp1760_qtd *qtd,
+ struct isp1760_qh *qh, struct ptd *ptd)
+{
+ struct isp1760_hcd *priv = hcd_to_priv(hcd);
+ int skip_map;
+
+ WARN_ON((slot < 0) || (slot > 31));
+ WARN_ON(qtd->length && !qtd->payload_addr);
+ WARN_ON(slots[slot].qtd);
+ WARN_ON(slots[slot].qh);
+ WARN_ON(qtd->status != QTD_PAYLOAD_ALLOC);
+
+ slots[slot].qtd = qtd;
+ slots[slot].qh = qh;
+ qh->slot = slot;
+ qtd->status = QTD_XFER_STARTED; /* Set this before writing ptd, since
+ interrupt routine may preempt and expects this value. */
+ ptd_write(hcd->regs, ptd_offset, slot, ptd);
+ priv->active_ptds++;
+
+ /* Make sure done map has not triggered from some unlinked transfer */
+ if (ptd_offset == ATL_PTD_OFFSET) {
+ priv->atl_done_map |= reg_read32(hcd->regs,
+ HC_ATL_PTD_DONEMAP_REG);
+ priv->atl_done_map &= ~(1 << qh->slot);
+
+ skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
+ skip_map &= ~(1 << qh->slot);
+ reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map);
+ } else {
+ priv->int_done_map |= reg_read32(hcd->regs,
+ HC_INT_PTD_DONEMAP_REG);
+ priv->int_done_map &= ~(1 << qh->slot);
+
+ skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
+ skip_map &= ~(1 << qh->slot);
+ reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map);
+ }
+}
+
+static int is_short_bulk(struct isp1760_qtd *qtd)
+{
+ return (usb_pipebulk(qtd->urb->pipe) &&
+ (qtd->actual_length < qtd->length));
+}
+
+static void collect_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh,
+ struct list_head *urb_list)
+{
+ int last_qtd;
+ struct isp1760_qtd *qtd, *qtd_next;
+ struct urb_listitem *urb_listitem;
+
+ list_for_each_entry_safe(qtd, qtd_next, &qh->qtd_list, qtd_list) {
+ if (qtd->status < QTD_XFER_COMPLETE)
+ break;
+
+ if (list_is_last(&qtd->qtd_list, &qh->qtd_list))
+ last_qtd = 1;
+ else
+ last_qtd = qtd->urb != qtd_next->urb;
+
+ if ((!last_qtd) && (qtd->status == QTD_RETIRE))
+ qtd_next->status = QTD_RETIRE;
+
+ if (qtd->status == QTD_XFER_COMPLETE) {
+ if (qtd->actual_length) {
+ switch (qtd->packet_type) {
+ case IN_PID:
+ mem_reads8(hcd->regs, qtd->payload_addr,
+ qtd->data_buffer,
+ qtd->actual_length);
+ /* Fall through (?) */
+ case OUT_PID:
+ qtd->urb->actual_length +=
+ qtd->actual_length;
+ /* Fall through ... */
+ case SETUP_PID:
+ break;
+ }
+ }
+
+ if (is_short_bulk(qtd)) {
+ if (qtd->urb->transfer_flags & URB_SHORT_NOT_OK)
+ qtd->urb->status = -EREMOTEIO;
+ if (!last_qtd)
+ qtd_next->status = QTD_RETIRE;
+ }
+ }
+
+ if (qtd->payload_addr)
+ free_mem(hcd, qtd);
+
+ if (last_qtd) {
+ if ((qtd->status == QTD_RETIRE) &&
+ (qtd->urb->status == -EINPROGRESS))
+ qtd->urb->status = -EPIPE;
+ /* Defer calling of urb_done() since it releases lock */
+ urb_listitem = kmem_cache_zalloc(urb_listitem_cachep,
+ GFP_ATOMIC);
+ if (unlikely(!urb_listitem))
+ break;
+ urb_listitem->urb = qtd->urb;
+ list_add_tail(&urb_listitem->urb_list, urb_list);
+ }
+
+ list_del(&qtd->qtd_list);
+ qtd_free(qtd);
+ }
+}
+
+#define ENQUEUE_DEPTH 2
+static void enqueue_qtds(struct usb_hcd *hcd, struct isp1760_qh *qh)
+{
+ struct isp1760_hcd *priv = hcd_to_priv(hcd);
+ int ptd_offset;
+ struct slotinfo *slots;
+ int curr_slot, free_slot;
+ int n;
+ struct ptd ptd;
+ struct isp1760_qtd *qtd;
+
+ if (unlikely(list_empty(&qh->qtd_list))) {
+ WARN_ON(1);
+ return;
+ }
+
+ if (usb_pipeint(list_entry(qh->qtd_list.next, struct isp1760_qtd,
+ qtd_list)->urb->pipe)) {
+ ptd_offset = INT_PTD_OFFSET;
+ slots = priv->int_slots;
+ } else {
+ ptd_offset = ATL_PTD_OFFSET;
+ slots = priv->atl_slots;
+ }
+
+ free_slot = -1;
+ for (curr_slot = 0; curr_slot < 32; curr_slot++) {
+ if ((free_slot == -1) && (slots[curr_slot].qtd == NULL))
+ free_slot = curr_slot;
+ if (slots[curr_slot].qh == qh)
+ break;
+ }
+
+ n = 0;
+ list_for_each_entry(qtd, &qh->qtd_list, qtd_list) {
+ if (qtd->status == QTD_ENQUEUED) {
+ WARN_ON(qtd->payload_addr);
+ alloc_mem(hcd, qtd);
+ if ((qtd->length) && (!qtd->payload_addr))
+ break;
+
+ if ((qtd->length) &&
+ ((qtd->packet_type == SETUP_PID) ||
+ (qtd->packet_type == OUT_PID))) {
+ mem_writes8(hcd->regs, qtd->payload_addr,
+ qtd->data_buffer, qtd->length);
+ }
+
+ qtd->status = QTD_PAYLOAD_ALLOC;
+ }
+
+ if (qtd->status == QTD_PAYLOAD_ALLOC) {
/*
- * create a list of filled qtds for this URB; won't link into qh.
+ if ((curr_slot > 31) && (free_slot == -1))
+ dev_dbg(hcd->self.controller, "%s: No slot "
+ "available for transfer\n", __func__);
+*/
+ /* Start xfer for this endpoint if not already done */
+ if ((curr_slot > 31) && (free_slot > -1)) {
+ if (usb_pipeint(qtd->urb->pipe))
+ create_ptd_int(qh, qtd, &ptd);
+ else
+ create_ptd_atl(qh, qtd, &ptd);
+
+ start_bus_transfer(hcd, ptd_offset, free_slot,
+ slots, qtd, qh, &ptd);
+ curr_slot = free_slot;
+ }
+
+ n++;
+ if (n >= ENQUEUE_DEPTH)
+ break;
+ }
+ }
+}
+
+void schedule_ptds(struct usb_hcd *hcd)
+{
+ struct isp1760_hcd *priv;
+ struct isp1760_qh *qh, *qh_next;
+ struct list_head *ep_queue;
+ struct usb_host_endpoint *ep;
+ LIST_HEAD(urb_list);
+ struct urb_listitem *urb_listitem, *urb_listitem_next;
+
+ if (!hcd) {
+ WARN_ON(1);
+ return;
+ }
+
+ priv = hcd_to_priv(hcd);
+
+ /*
+ * check finished/retired xfers, transfer payloads, call urb_done()
+ */
+ ep_queue = &priv->interruptqhs;
+ while (ep_queue) {
+ list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list) {
+ ep = list_entry(qh->qtd_list.next, struct isp1760_qtd,
+ qtd_list)->urb->ep;
+ collect_qtds(hcd, qh, &urb_list);
+ if (list_empty(&qh->qtd_list)) {
+ list_del(&qh->qh_list);
+ if (ep->hcpriv == NULL) {
+ /* Endpoint has been disabled, so we
+ can free the associated queue head. */
+ qh_free(qh);
+ }
+ }
+ }
+
+ if (ep_queue == &priv->interruptqhs)
+ ep_queue = &priv->controlqhs;
+ else if (ep_queue == &priv->controlqhs)
+ ep_queue = &priv->bulkqhs;
+ else
+ ep_queue = NULL;
+ }
+
+ list_for_each_entry_safe(urb_listitem, urb_listitem_next, &urb_list,
+ urb_list) {
+ isp1760_urb_done(hcd, urb_listitem->urb);
+ kmem_cache_free(urb_listitem_cachep, urb_listitem);
+ }
+
+ /*
+ * Schedule packets for transfer.
+ *
+ * According to USB2.0 specification:
+ *
+ * 1st prio: interrupt xfers, up to 80 % of bandwidth
+ * 2nd prio: control xfers
+ * 3rd prio: bulk xfers
+ *
+ * ... but let's use a simpler scheme here (mostly because ISP1761 doc
+ * is very unclear on how to prioritize traffic):
+ *
+ * 1) Enqueue any queued control transfers, as long as payload chip mem
+ * and PTD ATL slots are available.
+ * 2) Enqueue any queued INT transfers, as long as payload chip mem
+ * and PTD INT slots are available.
+ * 3) Enqueue any queued bulk transfers, as long as payload chip mem
+ * and PTD ATL slots are available.
+ *
+ * Use double buffering (ENQUEUE_DEPTH==2) as a compromise between
+ * conservation of chip mem and performance.
+ *
+ * I'm sure this scheme could be improved upon!
+ */
+ ep_queue = &priv->controlqhs;
+ while (ep_queue) {
+ list_for_each_entry_safe(qh, qh_next, ep_queue, qh_list)
+ enqueue_qtds(hcd, qh);
+
+ if (ep_queue == &priv->controlqhs)
+ ep_queue = &priv->interruptqhs;
+ else if (ep_queue == &priv->interruptqhs)
+ ep_queue = &priv->bulkqhs;
+ else
+ ep_queue = NULL;
+ }
+}
+
+#define PTD_STATE_QTD_DONE 1
+#define PTD_STATE_QTD_RELOAD 2
+#define PTD_STATE_URB_RETIRE 3
+
+static int check_int_transfer(struct usb_hcd *hcd, struct ptd *ptd,
+ struct urb *urb)
+{
+ __dw dw4;
+ int i;
+
+ dw4 = ptd->dw4;
+ dw4 >>= 8;
+
+ /* FIXME: ISP1761 datasheet does not say what to do with these. Do we
+ need to handle these errors? Is it done in hardware? */
+
+ if (ptd->dw3 & DW3_HALT_BIT) {
+
+ urb->status = -EPROTO; /* Default unknown error */
+
+ for (i = 0; i < 8; i++) {
+ switch (dw4 & 0x7) {
+ case INT_UNDERRUN:
+ dev_dbg(hcd->self.controller, "%s: underrun "
+ "during uFrame %d\n",
+ __func__, i);
+ urb->status = -ECOMM; /* Could not write data */
+ break;
+ case INT_EXACT:
+ dev_dbg(hcd->self.controller, "%s: transaction "
+ "error during uFrame %d\n",
+ __func__, i);
+ urb->status = -EPROTO; /* timeout, bad CRC, PID
+ error etc. */
+ break;
+ case INT_BABBLE:
+ dev_dbg(hcd->self.controller, "%s: babble "
+ "error during uFrame %d\n",
+ __func__, i);
+ urb->status = -EOVERFLOW;
+ break;
+ }
+ dw4 >>= 3;
+ }
+
+ return PTD_STATE_URB_RETIRE;
+ }
+
+ return PTD_STATE_QTD_DONE;
+}
+
+static int check_atl_transfer(struct usb_hcd *hcd, struct ptd *ptd,
+ struct urb *urb)
+{
+ WARN_ON(!ptd);
+ if (ptd->dw3 & DW3_HALT_BIT) {
+ if (ptd->dw3 & DW3_BABBLE_BIT)
+ urb->status = -EOVERFLOW;
+ else if (FROM_DW3_CERR(ptd->dw3))
+ urb->status = -EPIPE; /* Stall */
+ else if (ptd->dw3 & DW3_ERROR_BIT)
+ urb->status = -EPROTO; /* XactErr */
+ else
+ urb->status = -EPROTO; /* Unknown */
+/*
+ dev_dbg(hcd->self.controller, "%s: ptd error:\n"
+ " dw0: %08x dw1: %08x dw2: %08x dw3: %08x\n"
+ " dw4: %08x dw5: %08x dw6: %08x dw7: %08x\n",
+ __func__,
+ ptd->dw0, ptd->dw1, ptd->dw2, ptd->dw3,
+ ptd->dw4, ptd->dw5, ptd->dw6, ptd->dw7);
+*/
+ return PTD_STATE_URB_RETIRE;
+ }
+
+ if ((ptd->dw3 & DW3_ERROR_BIT) && (ptd->dw3 & DW3_ACTIVE_BIT)) {
+ /* Transfer Error, *but* active and no HALT -> reload */
+ dev_dbg(hcd->self.controller, "PID error; reloading ptd\n");
+ return PTD_STATE_QTD_RELOAD;
+ }
+
+ if (!FROM_DW3_NAKCOUNT(ptd->dw3) && (ptd->dw3 & DW3_ACTIVE_BIT)) {
+ /*
+ * NAKs are handled in HW by the chip. Usually if the
+ * device is not able to send data fast enough.
+ * This happens mostly on slower hardware.
+ */
+ return PTD_STATE_QTD_RELOAD;
+ }
+
+ return PTD_STATE_QTD_DONE;
+}
+
+static irqreturn_t isp1760_irq(struct usb_hcd *hcd)
+{
+ struct isp1760_hcd *priv = hcd_to_priv(hcd);
+ u32 imask;
+ irqreturn_t irqret = IRQ_NONE;
+ struct ptd ptd;
+ struct isp1760_qh *qh;
+ int slot;
+ int state;
+ struct slotinfo *slots;
+ u32 ptd_offset;
+ struct isp1760_qtd *qtd;
+ int modified;
+ static int last_active_ptds;
+ int int_skip_map, atl_skip_map;
+
+ spin_lock(&priv->lock);
+
+ if (!(hcd->state & HC_STATE_RUNNING))
+ goto leave;
+
+ imask = reg_read32(hcd->regs, HC_INTERRUPT_REG);
+ if (unlikely(!imask))
+ goto leave;
+ reg_write32(hcd->regs, HC_INTERRUPT_REG, imask); /* Clear */
+
+ int_skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
+ atl_skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
+ priv->int_done_map |= reg_read32(hcd->regs, HC_INT_PTD_DONEMAP_REG);
+ priv->atl_done_map |= reg_read32(hcd->regs, HC_ATL_PTD_DONEMAP_REG);
+ priv->int_done_map &= ~int_skip_map;
+ priv->atl_done_map &= ~atl_skip_map;
+
+ modified = priv->int_done_map | priv->atl_done_map;
+
+ while (priv->int_done_map || priv->atl_done_map) {
+ if (priv->int_done_map) {
+ /* INT ptd */
+ slot = __ffs(priv->int_done_map);
+ priv->int_done_map &= ~(1 << slot);
+ slots = priv->int_slots;
+ /* This should not trigger, and could be removed if
+ noone have any problems with it triggering: */
+ if (!slots[slot].qh) {
+ WARN_ON(1);
+ continue;
+ }
+ ptd_offset = INT_PTD_OFFSET;
+ ptd_read(hcd->regs, INT_PTD_OFFSET, slot, &ptd);
+ state = check_int_transfer(hcd, &ptd,
+ slots[slot].qtd->urb);
+ } else {
+ /* ATL ptd */
+ slot = __ffs(priv->atl_done_map);
+ priv->atl_done_map &= ~(1 << slot);
+ slots = priv->atl_slots;
+ /* This should not trigger, and could be removed if
+ noone have any problems with it triggering: */
+ if (!slots[slot].qh) {
+ WARN_ON(1);
+ continue;
+ }
+ ptd_offset = ATL_PTD_OFFSET;
+ ptd_read(hcd->regs, ATL_PTD_OFFSET, slot, &ptd);
+ state = check_atl_transfer(hcd, &ptd,
+ slots[slot].qtd->urb);
+ }
+
+ qtd = slots[slot].qtd;
+ slots[slot].qtd = NULL;
+ qh = slots[slot].qh;
+ slots[slot].qh = NULL;
+ priv->active_ptds--;
+ qh->slot = -1;
+
+ WARN_ON(qtd->status != QTD_XFER_STARTED);
+
+ switch (state) {
+ case PTD_STATE_QTD_DONE:
+ if ((usb_pipeint(qtd->urb->pipe)) &&
+ (qtd->urb->dev->speed != USB_SPEED_HIGH))
+ qtd->actual_length =
+ FROM_DW3_SCS_NRBYTESTRANSFERRED(ptd.dw3);
+ else
+ qtd->actual_length =
+ FROM_DW3_NRBYTESTRANSFERRED(ptd.dw3);
+
+ qtd->status = QTD_XFER_COMPLETE;
+ if (list_is_last(&qtd->qtd_list, &qh->qtd_list) ||
+ is_short_bulk(qtd))
+ qtd = NULL;
+ else
+ qtd = list_entry(qtd->qtd_list.next,
+ typeof(*qtd), qtd_list);
+
+ qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3);
+ qh->ping = FROM_DW3_PING(ptd.dw3);
+ break;
+
+ case PTD_STATE_QTD_RELOAD: /* QTD_RETRY, for atls only */
+ qtd->status = QTD_PAYLOAD_ALLOC;
+ ptd.dw0 |= DW0_VALID_BIT;
+ /* RL counter = ERR counter */
+ ptd.dw3 &= ~TO_DW3_NAKCOUNT(0xf);
+ ptd.dw3 |= TO_DW3_NAKCOUNT(FROM_DW2_RL(ptd.dw2));
+ ptd.dw3 &= ~TO_DW3_CERR(3);
+ ptd.dw3 |= TO_DW3_CERR(ERR_COUNTER);
+ qh->toggle = FROM_DW3_DATA_TOGGLE(ptd.dw3);
+ qh->ping = FROM_DW3_PING(ptd.dw3);
+ break;
+
+ case PTD_STATE_URB_RETIRE:
+ qtd->status = QTD_RETIRE;
+ qtd = NULL;
+ qh->toggle = 0;
+ qh->ping = 0;
+ break;
+
+ default:
+ WARN_ON(1);
+ continue;
+ }
+
+ if (qtd && (qtd->status == QTD_PAYLOAD_ALLOC)) {
+ if (slots == priv->int_slots) {
+ if (state == PTD_STATE_QTD_RELOAD)
+ dev_err(hcd->self.controller,
+ "%s: PTD_STATE_QTD_RELOAD on "
+ "interrupt packet\n", __func__);
+ if (state != PTD_STATE_QTD_RELOAD)
+ create_ptd_int(qh, qtd, &ptd);
+ } else {
+ if (state != PTD_STATE_QTD_RELOAD)
+ create_ptd_atl(qh, qtd, &ptd);
+ }
+
+ start_bus_transfer(hcd, ptd_offset, slot, slots, qtd,
+ qh, &ptd);
+ }
+ }
+
+ if (modified)
+ schedule_ptds(hcd);
+
+ /* ISP1760 Errata 2 explains that interrupts may be missed (or not
+ happen?) if two USB devices are running simultaneously. Perhaps
+ this happens when a PTD is finished during interrupt handling;
+ enable SOF interrupts if PTDs are still scheduled when exiting this
+ interrupt handler, just to be safe. */
+
+ if (priv->active_ptds != last_active_ptds) {
+ if (priv->active_ptds > 0)
+ reg_write32(hcd->regs, HC_INTERRUPT_ENABLE,
+ INTERRUPT_ENABLE_SOT_MASK);
+ else
+ reg_write32(hcd->regs, HC_INTERRUPT_ENABLE,
+ INTERRUPT_ENABLE_MASK);
+ last_active_ptds = priv->active_ptds;
+ }
+
+ irqret = IRQ_HANDLED;
+leave:
+ spin_unlock(&priv->lock);
+
+ return irqret;
+}
+
+static int qtd_fill(struct isp1760_qtd *qtd, void *databuffer, size_t len)
+{
+ qtd->data_buffer = databuffer;
+
+ if (len > MAX_PAYLOAD_SIZE)
+ len = MAX_PAYLOAD_SIZE;
+ qtd->length = len;
+
+ return qtd->length;
+}
+
+static void qtd_list_free(struct list_head *qtd_list)
+{
+ struct isp1760_qtd *qtd, *qtd_next;
+
+ list_for_each_entry_safe(qtd, qtd_next, qtd_list, qtd_list) {
+ list_del(&qtd->qtd_list);
+ qtd_free(qtd);
+ }
+}
+
+/*
+ * Packetize urb->transfer_buffer into list of packets of size wMaxPacketSize.
+ * Also calculate the PID type (SETUP/IN/OUT) for each packet.
*/
#define max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff)
-static struct list_head *qh_urb_transaction(struct usb_hcd *hcd,
+static void packetize_urb(struct usb_hcd *hcd,
struct urb *urb, struct list_head *head, gfp_t flags)
{
struct isp1760_qtd *qtd;
void *buf;
- int len, maxpacket;
- int is_input;
- u32 token;
+ int len, maxpacketsize;
+ u8 packet_type;
/*
* URBs map to sequences of QTDs: one logical transaction
*/
- qtd = isp1760_qtd_alloc(flags);
- if (!qtd)
- return NULL;
- list_add_tail(&qtd->qtd_list, head);
- qtd->urb = urb;
- urb->status = -EINPROGRESS;
+ if (!urb->transfer_buffer && urb->transfer_buffer_length) {
+ /* XXX This looks like usb storage / SCSI bug */
+ dev_err(hcd->self.controller,
+ "buf is null, dma is %08lx len is %d\n",
+ (long unsigned)urb->transfer_dma,
+ urb->transfer_buffer_length);
+ WARN_ON(1);
+ }
- token = 0;
- /* for split transactions, SplitXState initialized to zero */
+ if (usb_pipein(urb->pipe))
+ packet_type = IN_PID;
+ else
+ packet_type = OUT_PID;
- len = urb->transfer_buffer_length;
- is_input = usb_pipein(urb->pipe);
if (usb_pipecontrol(urb->pipe)) {
- /* SETUP pid */
- qtd_fill(qtd, urb->setup_packet,
- sizeof(struct usb_ctrlrequest),
- token | SETUP_PID);
-
- /* ... and always at least one more pid */
- qtd = isp1760_qtd_alloc(flags);
+ qtd = qtd_alloc(flags, urb, SETUP_PID);
if (!qtd)
goto cleanup;
- qtd->urb = urb;
+ qtd_fill(qtd, urb->setup_packet, sizeof(struct usb_ctrlrequest));
list_add_tail(&qtd->qtd_list, head);
/* for zero length DATA stages, STATUS is always IN */
- if (len == 0)
- token |= IN_PID;
+ if (urb->transfer_buffer_length == 0)
+ packet_type = IN_PID;
}
- /*
- * data transfer stage: buffer setup
- */
- buf = urb->transfer_buffer;
-
- if (is_input)
- token |= IN_PID;
- else
- token |= OUT_PID;
-
- maxpacket = max_packet(usb_maxpacket(urb->dev, urb->pipe, !is_input));
+ maxpacketsize = max_packet(usb_maxpacket(urb->dev, urb->pipe,
+ usb_pipeout(urb->pipe)));
/*
* buffer gets wrapped in one or more qtds;
* last one may be "short" (including zero len)
* and may serve as a control status ack
*/
+ buf = urb->transfer_buffer;
+ len = urb->transfer_buffer_length;
+
for (;;) {
int this_qtd_len;
- if (!buf && len) {
- /* XXX This looks like usb storage / SCSI bug */
- dev_err(hcd->self.controller, "buf is null, dma is %08lx len is %d\n",
- (long unsigned)urb->transfer_dma, len);
- WARN_ON(1);
- }
+ qtd = qtd_alloc(flags, urb, packet_type);
+ if (!qtd)
+ goto cleanup;
+ this_qtd_len = qtd_fill(qtd, buf, len);
+ list_add_tail(&qtd->qtd_list, head);
- this_qtd_len = qtd_fill(qtd, buf, len, token);
len -= this_qtd_len;
buf += this_qtd_len;
if (len <= 0)
break;
-
- qtd = isp1760_qtd_alloc(flags);
- if (!qtd)
- goto cleanup;
- qtd->urb = urb;
- list_add_tail(&qtd->qtd_list, head);
}
/*
@@ -1510,184 +1435,204 @@
if (usb_pipecontrol(urb->pipe)) {
one_more = 1;
- /* "in" <--> "out" */
- token ^= IN_PID;
+ if (packet_type == IN_PID)
+ packet_type = OUT_PID;
+ else
+ packet_type = IN_PID;
} else if (usb_pipebulk(urb->pipe)
&& (urb->transfer_flags & URB_ZERO_PACKET)
- && !(urb->transfer_buffer_length % maxpacket)) {
+ && !(urb->transfer_buffer_length %
+ maxpacketsize)) {
one_more = 1;
}
if (one_more) {
- qtd = isp1760_qtd_alloc(flags);
+ qtd = qtd_alloc(flags, urb, packet_type);
if (!qtd)
goto cleanup;
- qtd->urb = urb;
- list_add_tail(&qtd->qtd_list, head);
/* never any data in such packets */
- qtd_fill(qtd, NULL, 0, token);
+ qtd_fill(qtd, NULL, 0);
+ list_add_tail(&qtd->qtd_list, head);
}
}
- qtd->status = 0;
- return head;
+ return;
cleanup:
- qtd_list_free(urb, head);
- return NULL;
+ qtd_list_free(head);
}
static int isp1760_urb_enqueue(struct usb_hcd *hcd, struct urb *urb,
gfp_t mem_flags)
{
- struct list_head qtd_list;
- packet_enqueue *pe;
-
- INIT_LIST_HEAD(&qtd_list);
+ struct isp1760_hcd *priv = hcd_to_priv(hcd);
+ struct list_head *ep_queue;
+ struct isp1760_qh *qh, *qhit;
+ unsigned long spinflags;
+ LIST_HEAD(new_qtds);
+ int retval;
+ int qh_in_queue;
switch (usb_pipetype(urb->pipe)) {
case PIPE_CONTROL:
+ ep_queue = &priv->controlqhs;
+ break;
case PIPE_BULK:
- if (!qh_urb_transaction(hcd, urb, &qtd_list, mem_flags))
- return -ENOMEM;
- pe = enqueue_an_ATL_packet;
+ ep_queue = &priv->bulkqhs;
break;
-
case PIPE_INTERRUPT:
- if (!qh_urb_transaction(hcd, urb, &qtd_list, mem_flags))
- return -ENOMEM;
- pe = enqueue_an_INT_packet;
+ if (urb->interval < 0)
+ return -EINVAL;
+ /* FIXME: Check bandwidth */
+ ep_queue = &priv->interruptqhs;
break;
-
case PIPE_ISOCHRONOUS:
- dev_err(hcd->self.controller, "PIPE_ISOCHRONOUS ain't supported\n");
+ dev_err(hcd->self.controller, "%s: isochronous USB packets "
+ "not yet supported\n",
+ __func__);
+ return -EPIPE;
default:
+ dev_err(hcd->self.controller, "%s: unknown pipe type\n",
+ __func__);
return -EPIPE;
}
- return isp1760_prepare_enqueue(hcd, urb, &qtd_list, mem_flags, pe);
-}
+ if (usb_pipein(urb->pipe))
+ urb->actual_length = 0;
-static int isp1760_urb_dequeue(struct usb_hcd *hcd, struct urb *urb, int status)
-{
- struct isp1760_hcd *priv = hcd_to_priv(hcd);
- struct inter_packet_info *ints;
- u32 i;
- u32 reg_base, or_reg, skip_reg;
- unsigned long flags;
- struct ptd ptd;
- packet_enqueue *pe;
+ packetize_urb(hcd, urb, &new_qtds, mem_flags);
+ if (list_empty(&new_qtds))
+ return -ENOMEM;
+ urb->hcpriv = NULL; /* Used to signal unlink to interrupt handler */
- switch (usb_pipetype(urb->pipe)) {
- case PIPE_ISOCHRONOUS:
- return -EPIPE;
- break;
+ retval = 0;
+ spin_lock_irqsave(&priv->lock, spinflags);
- case PIPE_INTERRUPT:
- ints = priv->int_ints;
- reg_base = INT_PTD_OFFSET;
- or_reg = HC_INT_IRQ_MASK_OR_REG;
- skip_reg = HC_INT_PTD_SKIPMAP_REG;
- pe = enqueue_an_INT_packet;
- break;
-
- default:
- ints = priv->atl_ints;
- reg_base = ATL_PTD_OFFSET;
- or_reg = HC_ATL_IRQ_MASK_OR_REG;
- skip_reg = HC_ATL_PTD_SKIPMAP_REG;
- pe = enqueue_an_ATL_packet;
- break;
+ if (!test_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags)) {
+ retval = -ESHUTDOWN;
+ goto out;
}
+ retval = usb_hcd_link_urb_to_ep(hcd, urb);
+ if (retval)
+ goto out;
- memset(&ptd, 0, sizeof(ptd));
- spin_lock_irqsave(&priv->lock, flags);
-
- for (i = 0; i < 32; i++) {
- if (!ints[i].qh)
- continue;
- BUG_ON(!ints[i].qtd);
-
- if (ints[i].qtd->urb == urb) {
- u32 skip_map;
- u32 or_map;
- struct isp1760_qtd *qtd;
- struct isp1760_qh *qh;
-
- skip_map = reg_read32(hcd->regs, skip_reg);
- skip_map |= 1 << i;
- reg_write32(hcd->regs, skip_reg, skip_map);
-
- or_map = reg_read32(hcd->regs, or_reg);
- or_map &= ~(1 << i);
- reg_write32(hcd->regs, or_reg, or_map);
-
- ptd_write(hcd->regs, reg_base, i, &ptd);
-
- qtd = ints[i].qtd;
- qh = ints[i].qh;
-
- free_mem(hcd, qtd);
- qtd = clean_up_qtdlist(qtd, qh);
-
- ints[i].qh = NULL;
- ints[i].qtd = NULL;
-
- urb->status = status;
- isp1760_urb_done(hcd, urb);
- if (qtd)
- pe(hcd, qh, qtd);
- break;
-
- } else {
- struct isp1760_qtd *qtd;
-
- list_for_each_entry(qtd, &ints[i].qtd->qtd_list,
- qtd_list) {
- if (qtd->urb == urb) {
- clean_up_qtdlist(qtd, ints[i].qh);
- isp1760_urb_done(hcd, urb);
- qtd = NULL;
- break;
- }
- }
-
- /* We found the urb before the last slot */
- if (!qtd)
+ qh = urb->ep->hcpriv;
+ if (qh) {
+ qh_in_queue = 0;
+ list_for_each_entry(qhit, ep_queue, qh_list) {
+ if (qhit == qh) {
+ qh_in_queue = 1;
break;
+ }
}
+ if (!qh_in_queue)
+ list_add_tail(&qh->qh_list, ep_queue);
+ } else {
+ qh = qh_alloc(GFP_ATOMIC);
+ if (!qh) {
+ retval = -ENOMEM;
+ goto out;
+ }
+ list_add_tail(&qh->qh_list, ep_queue);
+ urb->ep->hcpriv = qh;
}
- spin_unlock_irqrestore(&priv->lock, flags);
- return 0;
+ list_splice_tail(&new_qtds, &qh->qtd_list);
+ schedule_ptds(hcd);
+
+out:
+ spin_unlock_irqrestore(&priv->lock, spinflags);
+ return retval;
}
-static irqreturn_t isp1760_irq(struct usb_hcd *hcd)
+static void kill_transfer(struct usb_hcd *hcd, struct urb *urb,
+ struct isp1760_qh *qh)
{
struct isp1760_hcd *priv = hcd_to_priv(hcd);
- u32 imask;
- irqreturn_t irqret = IRQ_NONE;
+ int skip_map;
- spin_lock(&priv->lock);
+ WARN_ON(qh->slot == -1);
- if (!(hcd->state & HC_STATE_RUNNING))
- goto leave;
+ /* We need to forcefully reclaim the slot since some transfers never
+ return, e.g. interrupt transfers and NAKed bulk transfers. */
+ if (usb_pipebulk(urb->pipe)) {
+ skip_map = reg_read32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG);
+ skip_map |= (1 << qh->slot);
+ reg_write32(hcd->regs, HC_ATL_PTD_SKIPMAP_REG, skip_map);
+ priv->atl_slots[qh->slot].qh = NULL;
+ priv->atl_slots[qh->slot].qtd = NULL;
+ } else {
+ skip_map = reg_read32(hcd->regs, HC_INT_PTD_SKIPMAP_REG);
+ skip_map |= (1 << qh->slot);
+ reg_write32(hcd->regs, HC_INT_PTD_SKIPMAP_REG, skip_map);
+ priv->int_slots[qh->slot].qh = NULL;
+ priv->int_slots[qh->slot].qtd = NULL;
+ }
- imask = reg_read32(hcd->regs, HC_INTERRUPT_REG);
- if (unlikely(!imask))
- goto leave;
+ qh->slot = -1;
+ priv->active_ptds--;
+}
- reg_write32(hcd->regs, HC_INTERRUPT_REG, imask);
- if (imask & (HC_ATL_INT | HC_SOT_INT))
- do_atl_int(hcd);
+static int isp1760_urb_dequeue(struct usb_hcd *hcd, struct urb *urb,
+ int status)
+{
+ struct isp1760_hcd *priv = hcd_to_priv(hcd);
+ unsigned long spinflags;
+ struct isp1760_qh *qh;
+ struct isp1760_qtd *qtd;
+ int retval = 0;
- if (imask & HC_INTL_INT)
- do_intl_int(hcd);
+ spin_lock_irqsave(&priv->lock, spinflags);
- irqret = IRQ_HANDLED;
-leave:
- spin_unlock(&priv->lock);
- return irqret;
+ qh = urb->ep->hcpriv;
+ if (!qh) {
+ retval = -EINVAL;
+ goto out;
+ }
+
+ list_for_each_entry(qtd, &qh->qtd_list, qtd_list)
+ if (qtd->urb == urb) {
+ if (qtd->status == QTD_XFER_STARTED)
+ kill_transfer(hcd, urb, qh);
+ qtd->status = QTD_RETIRE;
+ }
+
+ urb->status = status;
+ schedule_ptds(hcd);
+
+out:
+ spin_unlock_irqrestore(&priv->lock, spinflags);
+ return retval;
+}
+
+static void isp1760_endpoint_disable(struct usb_hcd *hcd,
+ struct usb_host_endpoint *ep)
+{
+ struct isp1760_hcd *priv = hcd_to_priv(hcd);
+ unsigned long spinflags;
+ struct isp1760_qh *qh;
+ struct isp1760_qtd *qtd;
+
+ spin_lock_irqsave(&priv->lock, spinflags);
+
+ qh = ep->hcpriv;
+ if (!qh)
+ goto out;
+
+ list_for_each_entry(qtd, &qh->qtd_list, qtd_list) {
+ if (qtd->status == QTD_XFER_STARTED)
+ kill_transfer(hcd, qtd->urb, qh);
+ qtd->status = QTD_RETIRE;
+ qtd->urb->status = -ECONNRESET;
+ }
+
+ ep->hcpriv = NULL;
+ /* Cannot free qh here since it will be parsed by schedule_ptds() */
+
+ schedule_ptds(hcd);
+
+out:
+ spin_unlock_irqrestore(&priv->lock, spinflags);
}
static int isp1760_hub_status_data(struct usb_hcd *hcd, char *buf)
@@ -1778,7 +1723,7 @@
/* if reset finished and it's still not enabled -- handoff */
if (!(port_status & PORT_PE)) {
- dev_err(hcd->self.controller,
+ dev_info(hcd->self.controller,
"port %d full speed --> companion\n",
index + 1);
@@ -1787,7 +1732,7 @@
reg_write32(hcd->regs, HC_PORTSC1, port_status);
} else
- dev_err(hcd->self.controller, "port %d high speed\n",
+ dev_info(hcd->self.controller, "port %d high speed\n",
index + 1);
return port_status;
@@ -2059,51 +2004,6 @@
return retval;
}
-static void isp1760_endpoint_disable(struct usb_hcd *hcd,
- struct usb_host_endpoint *ep)
-{
- struct isp1760_hcd *priv = hcd_to_priv(hcd);
- struct isp1760_qh *qh;
- struct isp1760_qtd *qtd;
- unsigned long flags;
-
- spin_lock_irqsave(&priv->lock, flags);
- qh = ep->hcpriv;
- if (!qh)
- goto out;
-
- ep->hcpriv = NULL;
- do {
- /* more than entry might get removed */
- if (list_empty(&qh->qtd_list))
- break;
-
- qtd = list_first_entry(&qh->qtd_list, struct isp1760_qtd,
- qtd_list);
-
- if (qtd->status & URB_ENQUEUED) {
- spin_unlock_irqrestore(&priv->lock, flags);
- isp1760_urb_dequeue(hcd, qtd->urb, -ECONNRESET);
- spin_lock_irqsave(&priv->lock, flags);
- } else {
- struct urb *urb;
-
- urb = qtd->urb;
- clean_up_qtdlist(qtd, qh);
- urb->status = -ECONNRESET;
- isp1760_urb_done(hcd, urb);
- }
- } while (1);
-
- qh_destroy(qh);
- /* remove requests and leak them.
- * ATL are pretty fast done, INT could take a while...
- * The latter shoule be removed
- */
-out:
- spin_unlock_irqrestore(&priv->lock, flags);
-}
-
static int isp1760_get_frame(struct usb_hcd *hcd)
{
struct isp1760_hcd *priv = hcd_to_priv(hcd);
@@ -2165,6 +2065,13 @@
int __init init_kmem_once(void)
{
+ urb_listitem_cachep = kmem_cache_create("isp1760 urb_listitem",
+ sizeof(struct urb_listitem), 0, SLAB_TEMPORARY |
+ SLAB_MEM_SPREAD, NULL);
+
+ if (!urb_listitem_cachep)
+ return -ENOMEM;
+
qtd_cachep = kmem_cache_create("isp1760_qtd",
sizeof(struct isp1760_qtd), 0, SLAB_TEMPORARY |
SLAB_MEM_SPREAD, NULL);
@@ -2187,6 +2094,7 @@
{
kmem_cache_destroy(qtd_cachep);
kmem_cache_destroy(qh_cachep);
+ kmem_cache_destroy(urb_listitem_cachep);
}
struct usb_hcd *isp1760_register(phys_addr_t res_start, resource_size_t res_len,
diff --git a/drivers/usb/host/isp1760-hcd.h b/drivers/usb/host/isp1760-hcd.h
index 8705076..014a7df 100644
--- a/drivers/usb/host/isp1760-hcd.h
+++ b/drivers/usb/host/isp1760-hcd.h
@@ -49,10 +49,9 @@
#define SW_RESET_RESET_ALL (1 << 0)
#define HC_BUFFER_STATUS_REG 0x334
-#define ATL_BUFFER 0x1
-#define INT_BUFFER 0x2
-#define ISO_BUFFER 0x4
-#define BUFFER_MAP 0x7
+#define ISO_BUF_FILL (1 << 2)
+#define INT_BUF_FILL (1 << 1)
+#define ATL_BUF_FILL (1 << 0)
#define HC_MEMORY_REG 0x33c
#define ISP_BANK(x) ((x) << 16)
@@ -68,14 +67,13 @@
#define HC_INTERRUPT_REG 0x310
#define HC_INTERRUPT_ENABLE 0x314
-#define INTERRUPT_ENABLE_MASK (HC_INTL_INT | HC_ATL_INT | HC_EOT_INT)
-#define INTERRUPT_ENABLE_SOT_MASK (HC_INTL_INT | HC_SOT_INT | HC_EOT_INT)
-
#define HC_ISO_INT (1 << 9)
#define HC_ATL_INT (1 << 8)
#define HC_INTL_INT (1 << 7)
#define HC_EOT_INT (1 << 3)
#define HC_SOT_INT (1 << 1)
+#define INTERRUPT_ENABLE_MASK (HC_INTL_INT | HC_ATL_INT)
+#define INTERRUPT_ENABLE_SOT_MASK (HC_SOT_INT)
#define HC_ISO_IRQ_MASK_OR_REG 0x318
#define HC_INT_IRQ_MASK_OR_REG 0x31C
@@ -106,7 +104,7 @@
#define ATL_PTD_OFFSET 0x0c00
#define PAYLOAD_OFFSET 0x1000
-struct inter_packet_info {
+struct slotinfo {
struct isp1760_qh *qh;
struct isp1760_qtd *qtd;
};
@@ -156,54 +154,52 @@
/* ATL */
/* DW0 */
-#define PTD_VALID 1
-#define PTD_LENGTH(x) (((u32) x) << 3)
-#define PTD_MAXPACKET(x) (((u32) x) << 18)
-#define PTD_MULTI(x) (((u32) x) << 29)
-#define PTD_ENDPOINT(x) (((u32) x) << 31)
+#define DW0_VALID_BIT 1
+#define FROM_DW0_VALID(x) ((x) & 0x01)
+#define TO_DW0_LENGTH(x) (((u32) x) << 3)
+#define TO_DW0_MAXPACKET(x) (((u32) x) << 18)
+#define TO_DW0_MULTI(x) (((u32) x) << 29)
+#define TO_DW0_ENDPOINT(x) (((u32) x) << 31)
/* DW1 */
-#define PTD_DEVICE_ADDR(x) (((u32) x) << 3)
-#define PTD_PID_TOKEN(x) (((u32) x) << 10)
-#define PTD_TRANS_BULK ((u32) 2 << 12)
-#define PTD_TRANS_INT ((u32) 3 << 12)
-#define PTD_TRANS_SPLIT ((u32) 1 << 14)
-#define PTD_SE_USB_LOSPEED ((u32) 2 << 16)
-#define PTD_PORT_NUM(x) (((u32) x) << 18)
-#define PTD_HUB_NUM(x) (((u32) x) << 25)
-#define PTD_PING(x) (((u32) x) << 26)
+#define TO_DW1_DEVICE_ADDR(x) (((u32) x) << 3)
+#define TO_DW1_PID_TOKEN(x) (((u32) x) << 10)
+#define DW1_TRANS_BULK ((u32) 2 << 12)
+#define DW1_TRANS_INT ((u32) 3 << 12)
+#define DW1_TRANS_SPLIT ((u32) 1 << 14)
+#define DW1_SE_USB_LOSPEED ((u32) 2 << 16)
+#define TO_DW1_PORT_NUM(x) (((u32) x) << 18)
+#define TO_DW1_HUB_NUM(x) (((u32) x) << 25)
/* DW2 */
-#define PTD_RL_CNT(x) (((u32) x) << 25)
-#define PTD_DATA_START_ADDR(x) (((u32) x) << 8)
-#define BASE_ADDR 0x1000
+#define TO_DW2_DATA_START_ADDR(x) (((u32) x) << 8)
+#define TO_DW2_RL(x) ((x) << 25)
+#define FROM_DW2_RL(x) (((x) >> 25) & 0xf)
/* DW3 */
-#define PTD_CERR(x) (((u32) x) << 23)
-#define PTD_NAC_CNT(x) (((u32) x) << 19)
-#define PTD_ACTIVE ((u32) 1 << 31)
-#define PTD_DATA_TOGGLE(x) (((u32) x) << 25)
-
-#define DW3_HALT_BIT (1 << 30)
+#define FROM_DW3_NRBYTESTRANSFERRED(x) ((x) & 0x7fff)
+#define FROM_DW3_SCS_NRBYTESTRANSFERRED(x) ((x) & 0x07ff)
+#define TO_DW3_NAKCOUNT(x) ((x) << 19)
+#define FROM_DW3_NAKCOUNT(x) (((x) >> 19) & 0xf)
+#define TO_DW3_CERR(x) ((x) << 23)
+#define FROM_DW3_CERR(x) (((x) >> 23) & 0x3)
+#define TO_DW3_DATA_TOGGLE(x) ((x) << 25)
+#define FROM_DW3_DATA_TOGGLE(x) (((x) >> 25) & 0x1)
+#define TO_DW3_PING(x) ((x) << 26)
+#define FROM_DW3_PING(x) (((x) >> 26) & 0x1)
#define DW3_ERROR_BIT (1 << 28)
-#define DW3_QTD_ACTIVE (1 << 31)
+#define DW3_BABBLE_BIT (1 << 29)
+#define DW3_HALT_BIT (1 << 30)
+#define DW3_ACTIVE_BIT (1 << 31)
#define INT_UNDERRUN (1 << 2)
#define INT_BABBLE (1 << 1)
#define INT_EXACT (1 << 0)
-#define DW1_GET_PID(x) (((x) >> 10) & 0x3)
-#define PTD_XFERRED_LENGTH(x) ((x) & 0x7fff)
-#define PTD_XFERRED_LENGTH_LO(x) ((x) & 0x7ff)
-
#define SETUP_PID (2)
#define IN_PID (1)
#define OUT_PID (0)
-#define GET_QTD_TOKEN_TYPE(x) ((x) & 0x3)
-
-#define DATA_TOGGLE (1 << 31)
-#define GET_DATA_TOGGLE(x) ((x) >> 31)
/* Errata 1 */
#define RL_COUNTER (0)
#define NAK_COUNTER (0)
#define ERR_COUNTER (2)
-#endif
+#endif /* _ISP1760_HCD_H_ */
diff --git a/drivers/usb/host/octeon2-common.c b/drivers/usb/host/octeon2-common.c
index 72d672c..d9df423 100644
--- a/drivers/usb/host/octeon2-common.c
+++ b/drivers/usb/host/octeon2-common.c
@@ -3,18 +3,19 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
- * Copyright (C) 2010 Cavium Networks
+ * Copyright (C) 2010, 2011 Cavium Networks
*/
#include <linux/module.h>
+#include <linux/mutex.h>
#include <linux/delay.h>
-#include <asm/atomic.h>
-
#include <asm/octeon/octeon.h>
#include <asm/octeon/cvmx-uctlx-defs.h>
-static atomic_t octeon2_usb_clock_start_cnt = ATOMIC_INIT(0);
+static DEFINE_MUTEX(octeon2_usb_clocks_mutex);
+
+static int octeon2_usb_clock_start_cnt;
void octeon2_usb_clocks_start(void)
{
@@ -26,8 +27,12 @@
int i;
unsigned long io_clk_64_to_ns;
- if (atomic_inc_return(&octeon2_usb_clock_start_cnt) != 1)
- return;
+
+ mutex_lock(&octeon2_usb_clocks_mutex);
+
+ octeon2_usb_clock_start_cnt++;
+ if (octeon2_usb_clock_start_cnt != 1)
+ goto exit;
io_clk_64_to_ns = 64000000000ull / octeon_get_io_clock_rate();
@@ -43,6 +48,13 @@
/* Step 3: Configure the reference clock, PHY, and HCLK */
clk_rst_ctl.u64 = cvmx_read_csr(CVMX_UCTLX_CLK_RST_CTL(0));
+
+ /*
+ * If the UCTL looks like it has already been started, skip
+ * the initialization, otherwise bus errors are obtained.
+ */
+ if (clk_rst_ctl.s.hrst)
+ goto end_clock;
/* 3a */
clk_rst_ctl.s.p_por = 1;
clk_rst_ctl.s.hrst = 0;
@@ -158,28 +170,31 @@
clk_rst_ctl.s.hrst = 1;
cvmx_write_csr(CVMX_UCTLX_CLK_RST_CTL(0), clk_rst_ctl.u64);
+end_clock:
/* Now we can set some other registers. */
for (i = 0; i <= 1; i++) {
port_ctl_status.u64 =
cvmx_read_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0));
- /* Set txvreftune to 15 to obtain complient 'eye' diagram. */
+ /* Set txvreftune to 15 to obtain compliant 'eye' diagram. */
port_ctl_status.s.txvreftune = 15;
+ port_ctl_status.s.txrisetune = 1;
+ port_ctl_status.s.txpreemphasistune = 1;
cvmx_write_csr(CVMX_UCTLX_UPHY_PORTX_CTL_STATUS(i, 0),
port_ctl_status.u64);
}
+
+ /* Set uSOF cycle period to 60,000 bits. */
+ cvmx_write_csr(CVMX_UCTLX_EHCI_FLA(0), 0x20ull);
+exit:
+ mutex_unlock(&octeon2_usb_clocks_mutex);
}
EXPORT_SYMBOL(octeon2_usb_clocks_start);
void octeon2_usb_clocks_stop(void)
{
- union cvmx_uctlx_if_ena if_ena;
-
- if (atomic_dec_return(&octeon2_usb_clock_start_cnt) != 0)
- return;
-
- if_ena.u64 = 0;
- if_ena.s.en = 0;
- cvmx_write_csr(CVMX_UCTLX_IF_ENA(0), if_ena.u64);
+ mutex_lock(&octeon2_usb_clocks_mutex);
+ octeon2_usb_clock_start_cnt--;
+ mutex_unlock(&octeon2_usb_clocks_mutex);
}
EXPORT_SYMBOL(octeon2_usb_clocks_stop);
diff --git a/drivers/usb/host/ohci-ath79.c b/drivers/usb/host/ohci-ath79.c
new file mode 100644
index 0000000..ffea3e7
--- /dev/null
+++ b/drivers/usb/host/ohci-ath79.c
@@ -0,0 +1,151 @@
+/*
+ * OHCI HCD (Host Controller Driver) for USB.
+ *
+ * Bus Glue for Atheros AR71XX/AR724X built-in OHCI controller.
+ *
+ * Copyright (C) 2008-2011 Gabor Juhos <juhosg@openwrt.org>
+ * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
+ *
+ * Parts of this file are based on Atheros' 2.6.15 BSP
+ * Copyright (C) 2007 Atheros Communications, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published
+ * by the Free Software Foundation.
+ */
+
+#include <linux/platform_device.h>
+
+static int __devinit ohci_ath79_start(struct usb_hcd *hcd)
+{
+ struct ohci_hcd *ohci = hcd_to_ohci(hcd);
+ int ret;
+
+ ret = ohci_init(ohci);
+ if (ret < 0)
+ return ret;
+
+ ret = ohci_run(ohci);
+ if (ret < 0)
+ goto err;
+
+ return 0;
+
+err:
+ ohci_stop(hcd);
+ return ret;
+}
+
+static const struct hc_driver ohci_ath79_hc_driver = {
+ .description = hcd_name,
+ .product_desc = "Atheros built-in OHCI controller",
+ .hcd_priv_size = sizeof(struct ohci_hcd),
+
+ .irq = ohci_irq,
+ .flags = HCD_USB11 | HCD_MEMORY,
+
+ .start = ohci_ath79_start,
+ .stop = ohci_stop,
+ .shutdown = ohci_shutdown,
+
+ .urb_enqueue = ohci_urb_enqueue,
+ .urb_dequeue = ohci_urb_dequeue,
+ .endpoint_disable = ohci_endpoint_disable,
+
+ /*
+ * scheduling support
+ */
+ .get_frame_number = ohci_get_frame,
+
+ /*
+ * root hub support
+ */
+ .hub_status_data = ohci_hub_status_data,
+ .hub_control = ohci_hub_control,
+ .start_port_reset = ohci_start_port_reset,
+};
+
+static int ohci_ath79_probe(struct platform_device *pdev)
+{
+ struct usb_hcd *hcd;
+ struct resource *res;
+ int irq;
+ int ret;
+
+ if (usb_disabled())
+ return -ENODEV;
+
+ res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+ if (!res) {
+ dev_dbg(&pdev->dev, "no IRQ specified\n");
+ return -ENODEV;
+ }
+ irq = res->start;
+
+ hcd = usb_create_hcd(&ohci_ath79_hc_driver, &pdev->dev,
+ dev_name(&pdev->dev));
+ if (!hcd)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ dev_dbg(&pdev->dev, "no base address specified\n");
+ ret = -ENODEV;
+ goto err_put_hcd;
+ }
+ hcd->rsrc_start = res->start;
+ hcd->rsrc_len = res->end - res->start + 1;
+
+ if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) {
+ dev_dbg(&pdev->dev, "controller already in use\n");
+ ret = -EBUSY;
+ goto err_put_hcd;
+ }
+
+ hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
+ if (!hcd->regs) {
+ dev_dbg(&pdev->dev, "error mapping memory\n");
+ ret = -EFAULT;
+ goto err_release_region;
+ }
+
+ ohci_hcd_init(hcd_to_ohci(hcd));
+
+ ret = usb_add_hcd(hcd, irq, IRQF_DISABLED);
+ if (ret)
+ goto err_stop_hcd;
+
+ return 0;
+
+err_stop_hcd:
+ iounmap(hcd->regs);
+err_release_region:
+ release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
+err_put_hcd:
+ usb_put_hcd(hcd);
+ return ret;
+}
+
+static int ohci_ath79_remove(struct platform_device *pdev)
+{
+ struct usb_hcd *hcd = platform_get_drvdata(pdev);
+
+ usb_remove_hcd(hcd);
+ iounmap(hcd->regs);
+ release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
+ usb_put_hcd(hcd);
+
+ return 0;
+}
+
+static struct platform_driver ohci_hcd_ath79_driver = {
+ .probe = ohci_ath79_probe,
+ .remove = ohci_ath79_remove,
+ .shutdown = usb_hcd_platform_shutdown,
+ .driver = {
+ .name = "ath79-ohci",
+ .owner = THIS_MODULE,
+ },
+};
+
+MODULE_ALIAS(PLATFORM_MODULE_PREFIX "ath79-ohci");
diff --git a/drivers/usb/host/ohci-hcd.c b/drivers/usb/host/ohci-hcd.c
index d557235..9aa10bd 100644
--- a/drivers/usb/host/ohci-hcd.c
+++ b/drivers/usb/host/ohci-hcd.c
@@ -764,6 +764,7 @@
if (ints == ~(u32)0) {
disable (ohci);
ohci_dbg (ohci, "device removed!\n");
+ usb_hc_died(hcd);
return IRQ_HANDLED;
}
@@ -771,7 +772,7 @@
ints &= ohci_readl(ohci, ®s->intrenable);
/* interrupt for some other device? */
- if (ints == 0)
+ if (ints == 0 || unlikely(hcd->state == HC_STATE_HALT))
return IRQ_NOTMINE;
if (ints & OHCI_INTR_UE) {
@@ -788,6 +789,7 @@
} else {
disable (ohci);
ohci_err (ohci, "OHCI Unrecoverable Error, disabled\n");
+ usb_hc_died(hcd);
}
ohci_dump (ohci, 1);
@@ -1105,6 +1107,11 @@
#define PLATFORM_DRIVER ohci_hcd_cns3xxx_driver
#endif
+#ifdef CONFIG_USB_OHCI_ATH79
+#include "ohci-ath79.c"
+#define PLATFORM_DRIVER ohci_hcd_ath79_driver
+#endif
+
#if !defined(PCI_DRIVER) && \
!defined(PLATFORM_DRIVER) && \
!defined(OMAP1_PLATFORM_DRIVER) && \
diff --git a/drivers/usb/host/ohci-pci.c b/drivers/usb/host/ohci-pci.c
index d84d6f0..ad8166c 100644
--- a/drivers/usb/host/ohci-pci.c
+++ b/drivers/usb/host/ohci-pci.c
@@ -181,10 +181,18 @@
*/
static int ohci_quirk_nvidia_shutdown(struct usb_hcd *hcd)
{
+ struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
struct ohci_hcd *ohci = hcd_to_ohci(hcd);
- ohci->flags |= OHCI_QUIRK_SHUTDOWN;
- ohci_dbg(ohci, "enabled nVidia shutdown quirk\n");
+ /* Evidently nVidia fixed their later hardware; this is a guess at
+ * the changeover point.
+ */
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_USB 0x026d
+
+ if (pdev->device < PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_USB) {
+ ohci->flags |= OHCI_QUIRK_SHUTDOWN;
+ ohci_dbg(ohci, "enabled nVidia shutdown quirk\n");
+ }
return 0;
}
diff --git a/drivers/usb/host/ohci-s3c2410.c b/drivers/usb/host/ohci-s3c2410.c
index a68af2d..7c9a4d5 100644
--- a/drivers/usb/host/ohci-s3c2410.c
+++ b/drivers/usb/host/ohci-s3c2410.c
@@ -56,9 +56,8 @@
info->hcd = hcd;
info->report_oc = s3c2410_hcd_oc;
- if (info->enable_oc != NULL) {
+ if (info->enable_oc != NULL)
(info->enable_oc)(info, 1);
- }
}
}
@@ -72,9 +71,8 @@
info->report_oc = NULL;
info->hcd = NULL;
- if (info->enable_oc != NULL) {
+ if (info->enable_oc != NULL)
(info->enable_oc)(info, 0);
- }
}
clk_disable(clk);
@@ -88,14 +86,14 @@
*/
static int
-ohci_s3c2410_hub_status_data (struct usb_hcd *hcd, char *buf)
+ohci_s3c2410_hub_status_data(struct usb_hcd *hcd, char *buf)
{
struct s3c2410_hcd_info *info = to_s3c2410_info(hcd);
struct s3c2410_hcd_port *port;
int orig;
int portno;
- orig = ohci_hub_status_data (hcd, buf);
+ orig = ohci_hub_status_data(hcd, buf);
if (info == NULL)
return orig;
@@ -145,7 +143,7 @@
* request.
*/
-static int ohci_s3c2410_hub_control (
+static int ohci_s3c2410_hub_control(
struct usb_hcd *hcd,
u16 typeReq,
u16 wValue,
@@ -199,9 +197,8 @@
dev_dbg(hcd->self.controller,
"ClearPortFeature: OVER_CURRENT\n");
- if (valid_port(wIndex)) {
+ if (valid_port(wIndex))
info->port[wIndex-1].oc_status = 0;
- }
goto out;
@@ -242,8 +239,11 @@
desc->wHubCharacteristics |= cpu_to_le16(0x0001);
if (info->enable_oc) {
- desc->wHubCharacteristics &= ~cpu_to_le16(HUB_CHAR_OCPM);
- desc->wHubCharacteristics |= cpu_to_le16(0x0008|0x0001);
+ desc->wHubCharacteristics &= ~cpu_to_le16(
+ HUB_CHAR_OCPM);
+ desc->wHubCharacteristics |= cpu_to_le16(
+ 0x0008 |
+ 0x0001);
}
dev_dbg(hcd->self.controller, "wHubCharacteristics after 0x%04x\n",
@@ -257,13 +257,11 @@
dev_dbg(hcd->self.controller, "GetPortStatus(%d)\n", wIndex);
if (valid_port(wIndex)) {
- if (info->port[wIndex-1].oc_changed) {
+ if (info->port[wIndex-1].oc_changed)
*data |= cpu_to_le32(RH_PS_OCIC);
- }
- if (info->port[wIndex-1].oc_status) {
+ if (info->port[wIndex-1].oc_status)
*data |= cpu_to_le32(RH_PS_POCI);
- }
}
}
@@ -321,7 +319,7 @@
*/
static void
-usb_hcd_s3c2410_remove (struct usb_hcd *hcd, struct platform_device *dev)
+usb_hcd_s3c2410_remove(struct usb_hcd *hcd, struct platform_device *dev)
{
usb_remove_hcd(hcd);
s3c2410_stop_hc(dev);
@@ -339,7 +337,7 @@
* through the hotplug entry's driver_data.
*
*/
-static int usb_hcd_s3c2410_probe (const struct hc_driver *driver,
+static int usb_hcd_s3c2410_probe(const struct hc_driver *driver,
struct platform_device *dev)
{
struct usb_hcd *hcd = NULL;
@@ -353,7 +351,7 @@
return -ENOMEM;
hcd->rsrc_start = dev->resource[0].start;
- hcd->rsrc_len = dev->resource[0].end - dev->resource[0].start + 1;
+ hcd->rsrc_len = resource_size(&dev->resource[0]);
if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) {
dev_err(&dev->dev, "request_mem_region failed\n");
@@ -364,14 +362,14 @@
clk = clk_get(&dev->dev, "usb-host");
if (IS_ERR(clk)) {
dev_err(&dev->dev, "cannot get usb-host clock\n");
- retval = -ENOENT;
+ retval = PTR_ERR(clk);
goto err_mem;
}
usb_clk = clk_get(&dev->dev, "usb-bus-host");
if (IS_ERR(usb_clk)) {
dev_err(&dev->dev, "cannot get usb-bus-host clock\n");
- retval = -ENOENT;
+ retval = PTR_ERR(usb_clk);
goto err_clk;
}
@@ -411,17 +409,19 @@
/*-------------------------------------------------------------------------*/
static int
-ohci_s3c2410_start (struct usb_hcd *hcd)
+ohci_s3c2410_start(struct usb_hcd *hcd)
{
- struct ohci_hcd *ohci = hcd_to_ohci (hcd);
+ struct ohci_hcd *ohci = hcd_to_ohci(hcd);
int ret;
- if ((ret = ohci_init(ohci)) < 0)
+ ret = ohci_init(ohci);
+ if (ret < 0)
return ret;
- if ((ret = ohci_run (ohci)) < 0) {
- err ("can't start %s", hcd->self.bus_name);
- ohci_stop (hcd);
+ ret = ohci_run(ohci);
+ if (ret < 0) {
+ err("can't start %s", hcd->self.bus_name);
+ ohci_stop(hcd);
return ret;
}
@@ -473,12 +473,12 @@
/* device driver */
-static int ohci_hcd_s3c2410_drv_probe(struct platform_device *pdev)
+static int __devinit ohci_hcd_s3c2410_drv_probe(struct platform_device *pdev)
{
return usb_hcd_s3c2410_probe(&ohci_s3c2410_hc_driver, pdev);
}
-static int ohci_hcd_s3c2410_drv_remove(struct platform_device *pdev)
+static int __devexit ohci_hcd_s3c2410_drv_remove(struct platform_device *pdev)
{
struct usb_hcd *hcd = platform_get_drvdata(pdev);
@@ -488,7 +488,7 @@
static struct platform_driver ohci_hcd_s3c2410_driver = {
.probe = ohci_hcd_s3c2410_drv_probe,
- .remove = ohci_hcd_s3c2410_drv_remove,
+ .remove = __devexit_p(ohci_hcd_s3c2410_drv_remove),
.shutdown = usb_hcd_platform_shutdown,
/*.suspend = ohci_hcd_s3c2410_drv_suspend, */
/*.resume = ohci_hcd_s3c2410_drv_resume, */
diff --git a/drivers/usb/host/oxu210hp-hcd.c b/drivers/usb/host/oxu210hp-hcd.c
index 4a771f6..5fbe997 100644
--- a/drivers/usb/host/oxu210hp-hcd.c
+++ b/drivers/usb/host/oxu210hp-hcd.c
@@ -1884,6 +1884,7 @@
status = handshake(oxu, &oxu->regs->status, STS_PSS, 0, 9 * 125);
if (status != 0) {
oxu_to_hcd(oxu)->state = HC_STATE_HALT;
+ usb_hc_died(oxu_to_hcd(oxu));
return status;
}
@@ -1909,6 +1910,7 @@
status = handshake(oxu, &oxu->regs->status, STS_PSS, STS_PSS, 9 * 125);
if (status != 0) {
oxu_to_hcd(oxu)->state = HC_STATE_HALT;
+ usb_hc_died(oxu_to_hcd(oxu));
return status;
}
@@ -2449,8 +2451,9 @@
goto dead;
}
+ /* Shared IRQ? */
status &= INTR_MASK;
- if (!status) { /* irq sharing? */
+ if (!status || unlikely(hcd->state == HC_STATE_HALT)) {
spin_unlock(&oxu->lock);
return IRQ_NONE;
}
@@ -2516,6 +2519,7 @@
dead:
ehci_reset(oxu);
writel(0, &oxu->regs->configured_flag);
+ usb_hc_died(hcd);
/* generic layer kills/unlinks all urbs, then
* uses oxu_stop to clean up the rest
*/
diff --git a/drivers/usb/host/pci-quirks.c b/drivers/usb/host/pci-quirks.c
index 9b166d7..f16c59d 100644
--- a/drivers/usb/host/pci-quirks.c
+++ b/drivers/usb/host/pci-quirks.c
@@ -14,6 +14,7 @@
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/acpi.h>
+#include <linux/dmi.h>
#include "pci-quirks.h"
#include "xhci-ext-caps.h"
@@ -503,14 +504,84 @@
iounmap(base);
}
+static void __devinit ehci_bios_handoff(struct pci_dev *pdev,
+ void __iomem *op_reg_base,
+ u32 cap, u8 offset)
+{
+ int try_handoff = 1, tried_handoff = 0;
+
+ /* The Pegatron Lucid (ExoPC) tablet sporadically waits for 90
+ * seconds trying the handoff on its unused controller. Skip
+ * it. */
+ if (pdev->vendor == 0x8086 && pdev->device == 0x283a) {
+ const char *dmi_bn = dmi_get_system_info(DMI_BOARD_NAME);
+ const char *dmi_bv = dmi_get_system_info(DMI_BIOS_VERSION);
+ if (dmi_bn && !strcmp(dmi_bn, "EXOPG06411") &&
+ dmi_bv && !strcmp(dmi_bv, "Lucid-CE-133"))
+ try_handoff = 0;
+ }
+
+ if (try_handoff && (cap & EHCI_USBLEGSUP_BIOS)) {
+ dev_dbg(&pdev->dev, "EHCI: BIOS handoff\n");
+
+#if 0
+/* aleksey_gorelov@phoenix.com reports that some systems need SMI forced on,
+ * but that seems dubious in general (the BIOS left it off intentionally)
+ * and is known to prevent some systems from booting. so we won't do this
+ * unless maybe we can determine when we're on a system that needs SMI forced.
+ */
+ /* BIOS workaround (?): be sure the pre-Linux code
+ * receives the SMI
+ */
+ pci_read_config_dword(pdev, offset + EHCI_USBLEGCTLSTS, &val);
+ pci_write_config_dword(pdev, offset + EHCI_USBLEGCTLSTS,
+ val | EHCI_USBLEGCTLSTS_SOOE);
+#endif
+
+ /* some systems get upset if this semaphore is
+ * set for any other reason than forcing a BIOS
+ * handoff..
+ */
+ pci_write_config_byte(pdev, offset + 3, 1);
+ }
+
+ /* if boot firmware now owns EHCI, spin till it hands it over. */
+ if (try_handoff) {
+ int msec = 1000;
+ while ((cap & EHCI_USBLEGSUP_BIOS) && (msec > 0)) {
+ tried_handoff = 1;
+ msleep(10);
+ msec -= 10;
+ pci_read_config_dword(pdev, offset, &cap);
+ }
+ }
+
+ if (cap & EHCI_USBLEGSUP_BIOS) {
+ /* well, possibly buggy BIOS... try to shut it down,
+ * and hope nothing goes too wrong
+ */
+ if (try_handoff)
+ dev_warn(&pdev->dev, "EHCI: BIOS handoff failed"
+ " (BIOS bug?) %08x\n", cap);
+ pci_write_config_byte(pdev, offset + 2, 0);
+ }
+
+ /* just in case, always disable EHCI SMIs */
+ pci_write_config_dword(pdev, offset + EHCI_USBLEGCTLSTS, 0);
+
+ /* If the BIOS ever owned the controller then we can't expect
+ * any power sessions to remain intact.
+ */
+ if (tried_handoff)
+ writel(0, op_reg_base + EHCI_CONFIGFLAG);
+}
+
static void __devinit quirk_usb_disable_ehci(struct pci_dev *pdev)
{
- int wait_time, delta;
void __iomem *base, *op_reg_base;
- u32 hcc_params, val;
+ u32 hcc_params, cap, val;
u8 offset, cap_length;
- int count = 256/4;
- int tried_handoff = 0;
+ int wait_time, delta, count = 256/4;
if (!mmio_resource_enabled(pdev, 0))
return;
@@ -529,77 +600,17 @@
hcc_params = readl(base + EHCI_HCC_PARAMS);
offset = (hcc_params >> 8) & 0xff;
while (offset && --count) {
- u32 cap;
- int msec;
-
pci_read_config_dword(pdev, offset, &cap);
+
switch (cap & 0xff) {
- case 1: /* BIOS/SMM/... handoff support */
- if ((cap & EHCI_USBLEGSUP_BIOS)) {
- dev_dbg(&pdev->dev, "EHCI: BIOS handoff\n");
-
-#if 0
-/* aleksey_gorelov@phoenix.com reports that some systems need SMI forced on,
- * but that seems dubious in general (the BIOS left it off intentionally)
- * and is known to prevent some systems from booting. so we won't do this
- * unless maybe we can determine when we're on a system that needs SMI forced.
- */
- /* BIOS workaround (?): be sure the
- * pre-Linux code receives the SMI
- */
- pci_read_config_dword(pdev,
- offset + EHCI_USBLEGCTLSTS,
- &val);
- pci_write_config_dword(pdev,
- offset + EHCI_USBLEGCTLSTS,
- val | EHCI_USBLEGCTLSTS_SOOE);
-#endif
-
- /* some systems get upset if this semaphore is
- * set for any other reason than forcing a BIOS
- * handoff..
- */
- pci_write_config_byte(pdev, offset + 3, 1);
- }
-
- /* if boot firmware now owns EHCI, spin till
- * it hands it over.
- */
- msec = 1000;
- while ((cap & EHCI_USBLEGSUP_BIOS) && (msec > 0)) {
- tried_handoff = 1;
- msleep(10);
- msec -= 10;
- pci_read_config_dword(pdev, offset, &cap);
- }
-
- if (cap & EHCI_USBLEGSUP_BIOS) {
- /* well, possibly buggy BIOS... try to shut
- * it down, and hope nothing goes too wrong
- */
- dev_warn(&pdev->dev, "EHCI: BIOS handoff failed"
- " (BIOS bug?) %08x\n", cap);
- pci_write_config_byte(pdev, offset + 2, 0);
- }
-
- /* just in case, always disable EHCI SMIs */
- pci_write_config_dword(pdev,
- offset + EHCI_USBLEGCTLSTS,
- 0);
-
- /* If the BIOS ever owned the controller then we
- * can't expect any power sessions to remain intact.
- */
- if (tried_handoff)
- writel(0, op_reg_base + EHCI_CONFIGFLAG);
+ case 1:
+ ehci_bios_handoff(pdev, op_reg_base, cap, offset);
break;
- case 0: /* illegal reserved capability */
- cap = 0;
- /* FALLTHROUGH */
+ case 0: /* Illegal reserved cap, set cap=0 so we exit */
+ cap = 0; /* then fallthrough... */
default:
dev_warn(&pdev->dev, "EHCI: unrecognized capability "
- "%02x\n", cap & 0xff);
- break;
+ "%02x\n", cap & 0xff);
}
offset = (cap >> 8) & 0xff;
}
diff --git a/drivers/usb/host/sl811-hcd.c b/drivers/usb/host/sl811-hcd.c
index fafccc2..1a99624 100644
--- a/drivers/usb/host/sl811-hcd.c
+++ b/drivers/usb/host/sl811-hcd.c
@@ -72,12 +72,6 @@
/* for now, use only one transfer register bank */
#undef USE_B
-/* this doesn't understand urb->iso_frame_desc[], but if you had a driver
- * that just queued one ISO frame per URB then iso transfers "should" work
- * using the normal urb status fields.
- */
-#define DISABLE_ISO
-
// #define QUIRK2
#define QUIRK3
@@ -808,7 +802,7 @@
int retval;
struct usb_host_endpoint *hep = urb->ep;
-#ifdef DISABLE_ISO
+#ifndef CONFIG_USB_SL811_HCD_ISO
if (type == PIPE_ISOCHRONOUS)
return -ENOSPC;
#endif
diff --git a/drivers/usb/host/sl811_cs.c b/drivers/usb/host/sl811_cs.c
index 3775c03..3b6f50e 100644
--- a/drivers/usb/host/sl811_cs.c
+++ b/drivers/usb/host/sl811_cs.c
@@ -187,7 +187,7 @@
return sl811_cs_config(link);
}
-static struct pcmcia_device_id sl811_ids[] = {
+static const struct pcmcia_device_id sl811_ids[] = {
PCMCIA_DEVICE_MANF_CARD(0xc015, 0x0001), /* RATOC USB HOST CF+ Card */
PCMCIA_DEVICE_NULL,
};
diff --git a/drivers/usb/host/u132-hcd.c b/drivers/usb/host/u132-hcd.c
index b478593..533d12c 100644
--- a/drivers/usb/host/u132-hcd.c
+++ b/drivers/usb/host/u132-hcd.c
@@ -3230,8 +3230,7 @@
mutex_init(&u132_module_lock);
if (usb_disabled())
return -ENODEV;
- printk(KERN_INFO "driver %s built at %s on %s\n", hcd_name, __TIME__,
- __DATE__);
+ printk(KERN_INFO "driver %s\n", hcd_name);
workqueue = create_singlethread_workqueue("u132");
retval = platform_driver_register(&u132_platform_driver);
return retval;
diff --git a/drivers/usb/host/uhci-debug.c b/drivers/usb/host/uhci-debug.c
index ee60cd3..fc0b0da 100644
--- a/drivers/usb/host/uhci-debug.c
+++ b/drivers/usb/host/uhci-debug.c
@@ -37,7 +37,8 @@
}
}
-static int uhci_show_td(struct uhci_td *td, char *buf, int len, int space)
+static int uhci_show_td(struct uhci_hcd *uhci, struct uhci_td *td, char *buf,
+ int len, int space)
{
char *out = buf;
char *spid;
@@ -47,8 +48,9 @@
if (len < 160)
return 0;
- status = td_status(td);
- out += sprintf(out, "%*s[%p] link (%08x) ", space, "", td, le32_to_cpu(td->link));
+ status = td_status(uhci, td);
+ out += sprintf(out, "%*s[%p] link (%08x) ", space, "", td,
+ hc32_to_cpu(uhci, td->link));
out += sprintf(out, "e%d %s%s%s%s%s%s%s%s%s%sLength=%x ",
((status >> 27) & 3),
(status & TD_CTRL_SPD) ? "SPD " : "",
@@ -63,7 +65,7 @@
(status & TD_CTRL_BITSTUFF) ? "BitStuff " : "",
status & 0x7ff);
- token = td_token(td);
+ token = td_token(uhci, td);
switch (uhci_packetid(token)) {
case USB_PID_SETUP:
spid = "SETUP";
@@ -86,12 +88,13 @@
(token >> 8) & 127,
(token & 0xff),
spid);
- out += sprintf(out, "(buf=%08x)\n", le32_to_cpu(td->buffer));
+ out += sprintf(out, "(buf=%08x)\n", hc32_to_cpu(uhci, td->buffer));
return out - buf;
}
-static int uhci_show_urbp(struct urb_priv *urbp, char *buf, int len, int space)
+static int uhci_show_urbp(struct uhci_hcd *uhci, struct urb_priv *urbp,
+ char *buf, int len, int space)
{
char *out = buf;
struct uhci_td *td;
@@ -130,9 +133,10 @@
if (urbp->qh->type != USB_ENDPOINT_XFER_ISOC &&
(++i <= 10 || debug > 2)) {
out += sprintf(out, "%*s%d: ", space + 2, "", i);
- out += uhci_show_td(td, out, len - (out - buf), 0);
+ out += uhci_show_td(uhci, td, out,
+ len - (out - buf), 0);
} else {
- if (td_status(td) & TD_CTRL_ACTIVE)
+ if (td_status(uhci, td) & TD_CTRL_ACTIVE)
++nactive;
else
++ninactive;
@@ -151,7 +155,7 @@
{
char *out = buf;
int i, nurbs;
- __le32 element = qh_element(qh);
+ __hc32 element = qh_element(qh);
char *qtype;
/* Try to make sure there's enough memory */
@@ -168,7 +172,8 @@
out += sprintf(out, "%*s[%p] %s QH link (%08x) element (%08x)\n",
space, "", qh, qtype,
- le32_to_cpu(qh->link), le32_to_cpu(element));
+ hc32_to_cpu(uhci, qh->link),
+ hc32_to_cpu(uhci, element));
if (qh->type == USB_ENDPOINT_XFER_ISOC)
out += sprintf(out, "%*s period %d phase %d load %d us, "
"frame %x desc [%p]\n",
@@ -178,22 +183,22 @@
out += sprintf(out, "%*s period %d phase %d load %d us\n",
space, "", qh->period, qh->phase, qh->load);
- if (element & UHCI_PTR_QH)
+ if (element & UHCI_PTR_QH(uhci))
out += sprintf(out, "%*s Element points to QH (bug?)\n", space, "");
- if (element & UHCI_PTR_DEPTH)
+ if (element & UHCI_PTR_DEPTH(uhci))
out += sprintf(out, "%*s Depth traverse\n", space, "");
- if (element & cpu_to_le32(8))
+ if (element & cpu_to_hc32(uhci, 8))
out += sprintf(out, "%*s Bit 3 set (bug?)\n", space, "");
- if (!(element & ~(UHCI_PTR_QH | UHCI_PTR_DEPTH)))
+ if (!(element & ~(UHCI_PTR_QH(uhci) | UHCI_PTR_DEPTH(uhci))))
out += sprintf(out, "%*s Element is NULL (bug?)\n", space, "");
if (list_empty(&qh->queue)) {
out += sprintf(out, "%*s queue is empty\n", space, "");
if (qh == uhci->skel_async_qh)
- out += uhci_show_td(uhci->term_td, out,
+ out += uhci_show_td(uhci, uhci->term_td, out,
len - (out - buf), 0);
} else {
struct urb_priv *urbp = list_entry(qh->queue.next,
@@ -201,13 +206,13 @@
struct uhci_td *td = list_entry(urbp->td_list.next,
struct uhci_td, list);
- if (element != LINK_TO_TD(td))
+ if (element != LINK_TO_TD(uhci, td))
out += sprintf(out, "%*s Element != First TD\n",
space, "");
i = nurbs = 0;
list_for_each_entry(urbp, &qh->queue, node) {
if (++i <= 10)
- out += uhci_show_urbp(urbp, out,
+ out += uhci_show_urbp(uhci, urbp, out,
len - (out - buf), space + 2);
else
++nurbs;
@@ -219,7 +224,8 @@
if (qh->dummy_td) {
out += sprintf(out, "%*s Dummy TD\n", space, "");
- out += uhci_show_td(qh->dummy_td, out, len - (out - buf), 0);
+ out += uhci_show_td(uhci, qh->dummy_td, out,
+ len - (out - buf), 0);
}
return out - buf;
@@ -285,7 +291,6 @@
static int uhci_show_status(struct uhci_hcd *uhci, char *buf, int len)
{
char *out = buf;
- unsigned long io_addr = uhci->io_addr;
unsigned short usbcmd, usbstat, usbint, usbfrnum;
unsigned int flbaseadd;
unsigned char sof;
@@ -295,14 +300,14 @@
if (len < 80 * 9)
return 0;
- usbcmd = inw(io_addr + 0);
- usbstat = inw(io_addr + 2);
- usbint = inw(io_addr + 4);
- usbfrnum = inw(io_addr + 6);
- flbaseadd = inl(io_addr + 8);
- sof = inb(io_addr + 12);
- portsc1 = inw(io_addr + 16);
- portsc2 = inw(io_addr + 18);
+ usbcmd = uhci_readw(uhci, 0);
+ usbstat = uhci_readw(uhci, 2);
+ usbint = uhci_readw(uhci, 4);
+ usbfrnum = uhci_readw(uhci, 6);
+ flbaseadd = uhci_readl(uhci, 8);
+ sof = uhci_readb(uhci, 12);
+ portsc1 = uhci_readw(uhci, 16);
+ portsc2 = uhci_readw(uhci, 18);
out += sprintf(out, " usbcmd = %04x %s%s%s%s%s%s%s%s\n",
usbcmd,
@@ -347,8 +352,8 @@
struct uhci_td *td;
struct list_head *tmp, *head;
int nframes, nerrs;
- __le32 link;
- __le32 fsbr_link;
+ __hc32 link;
+ __hc32 fsbr_link;
static const char * const qh_names[] = {
"unlink", "iso", "int128", "int64", "int32", "int16",
@@ -376,7 +381,7 @@
nframes = 10;
nerrs = 0;
for (i = 0; i < UHCI_NUMFRAMES; ++i) {
- __le32 qh_dma;
+ __hc32 qh_dma;
j = 0;
td = uhci->frame_cpu[i];
@@ -386,7 +391,7 @@
if (nframes > 0) {
out += sprintf(out, "- Frame %d -> (%08x)\n",
- i, le32_to_cpu(link));
+ i, hc32_to_cpu(uhci, link));
j = 1;
}
@@ -395,7 +400,7 @@
do {
td = list_entry(tmp, struct uhci_td, fl_list);
tmp = tmp->next;
- if (link != LINK_TO_TD(td)) {
+ if (link != LINK_TO_TD(uhci, td)) {
if (nframes > 0)
out += sprintf(out, " link does "
"not match list entry!\n");
@@ -403,7 +408,7 @@
++nerrs;
}
if (nframes > 0)
- out += uhci_show_td(td, out,
+ out += uhci_show_td(uhci, td, out,
len - (out - buf), 4);
link = td->link;
} while (tmp != head);
@@ -415,11 +420,12 @@
if (!j) {
out += sprintf(out,
"- Frame %d -> (%08x)\n",
- i, le32_to_cpu(link));
+ i, hc32_to_cpu(uhci, link));
j = 1;
}
out += sprintf(out, " link does not match "
- "QH (%08x)!\n", le32_to_cpu(qh_dma));
+ "QH (%08x)!\n",
+ hc32_to_cpu(uhci, qh_dma));
} else
++nerrs;
}
@@ -440,11 +446,11 @@
/* Last QH is the Terminating QH, it's different */
if (i == SKEL_TERM) {
- if (qh_element(qh) != LINK_TO_TD(uhci->term_td))
+ if (qh_element(qh) != LINK_TO_TD(uhci, uhci->term_td))
out += sprintf(out, " skel_term_qh element is not set to term_td!\n");
link = fsbr_link;
if (!link)
- link = LINK_TO_QH(uhci->skel_term_qh);
+ link = LINK_TO_QH(uhci, uhci->skel_term_qh);
goto check_qh_link;
}
@@ -458,20 +464,20 @@
out += uhci_show_qh(uhci, qh, out,
len - (out - buf), 4);
if (!fsbr_link && qh->skel >= SKEL_FSBR)
- fsbr_link = LINK_TO_QH(qh);
+ fsbr_link = LINK_TO_QH(uhci, qh);
}
if ((cnt -= 10) > 0)
out += sprintf(out, " Skipped %d QHs\n", cnt);
- link = UHCI_PTR_TERM;
+ link = UHCI_PTR_TERM(uhci);
if (i <= SKEL_ISO)
;
else if (i < SKEL_ASYNC)
- link = LINK_TO_QH(uhci->skel_async_qh);
+ link = LINK_TO_QH(uhci, uhci->skel_async_qh);
else if (!uhci->fsbr_is_on)
;
else
- link = LINK_TO_QH(uhci->skel_term_qh);
+ link = LINK_TO_QH(uhci, uhci->skel_term_qh);
check_qh_link:
if (qh->link != link)
out += sprintf(out, " last QH not linked to next skeleton!\n");
diff --git a/drivers/usb/host/uhci-grlib.c b/drivers/usb/host/uhci-grlib.c
new file mode 100644
index 0000000..d01c1e2
--- /dev/null
+++ b/drivers/usb/host/uhci-grlib.c
@@ -0,0 +1,208 @@
+/*
+ * UHCI HCD (Host Controller Driver) for GRLIB GRUSBHC
+ *
+ * Copyright (c) 2011 Jan Andersson <jan@gaisler.com>
+ *
+ * This file is based on UHCI PCI HCD:
+ * (C) Copyright 1999 Linus Torvalds
+ * (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com
+ * (C) Copyright 1999 Randy Dunlap
+ * (C) Copyright 1999 Georg Acher, acher@in.tum.de
+ * (C) Copyright 1999 Deti Fliegl, deti@fliegl.de
+ * (C) Copyright 1999 Thomas Sailer, sailer@ife.ee.ethz.ch
+ * (C) Copyright 1999 Roman Weissgaerber, weissg@vienna.at
+ * (C) Copyright 2000 Yggdrasil Computing, Inc. (port of new PCI interface
+ * support from usb-ohci.c by Adam Richter, adam@yggdrasil.com).
+ * (C) Copyright 1999 Gregory P. Smith (from usb-ohci.c)
+ * (C) Copyright 2004-2007 Alan Stern, stern@rowland.harvard.edu
+ */
+
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+
+static int uhci_grlib_init(struct usb_hcd *hcd)
+{
+ struct uhci_hcd *uhci = hcd_to_uhci(hcd);
+
+ /*
+ * Probe to determine the endianness of the controller.
+ * We know that bit 7 of the PORTSC1 register is always set
+ * and bit 15 is always clear. If uhci_readw() yields a value
+ * with bit 7 (0x80) turned on then the current little-endian
+ * setting is correct. Otherwise we assume the value was
+ * byte-swapped; hence the register interface and presumably
+ * also the descriptors are big-endian.
+ */
+ if (!(uhci_readw(uhci, USBPORTSC1) & 0x80)) {
+ uhci->big_endian_mmio = 1;
+ uhci->big_endian_desc = 1;
+ }
+
+ uhci->rh_numports = uhci_count_ports(hcd);
+
+ /* Set up pointers to to generic functions */
+ uhci->reset_hc = uhci_generic_reset_hc;
+ uhci->check_and_reset_hc = uhci_generic_check_and_reset_hc;
+ /* No special actions need to be taken for the functions below */
+ uhci->configure_hc = NULL;
+ uhci->resume_detect_interrupts_are_broken = NULL;
+ uhci->global_suspend_mode_is_broken = NULL;
+
+ /* Reset if the controller isn't already safely quiescent. */
+ check_and_reset_hc(uhci);
+ return 0;
+}
+
+static const struct hc_driver uhci_grlib_hc_driver = {
+ .description = hcd_name,
+ .product_desc = "GRLIB GRUSBHC UHCI Host Controller",
+ .hcd_priv_size = sizeof(struct uhci_hcd),
+
+ /* Generic hardware linkage */
+ .irq = uhci_irq,
+ .flags = HCD_MEMORY | HCD_USB11,
+
+ /* Basic lifecycle operations */
+ .reset = uhci_grlib_init,
+ .start = uhci_start,
+#ifdef CONFIG_PM
+ .pci_suspend = NULL,
+ .pci_resume = NULL,
+ .bus_suspend = uhci_rh_suspend,
+ .bus_resume = uhci_rh_resume,
+#endif
+ .stop = uhci_stop,
+
+ .urb_enqueue = uhci_urb_enqueue,
+ .urb_dequeue = uhci_urb_dequeue,
+
+ .endpoint_disable = uhci_hcd_endpoint_disable,
+ .get_frame_number = uhci_hcd_get_frame_number,
+
+ .hub_status_data = uhci_hub_status_data,
+ .hub_control = uhci_hub_control,
+};
+
+
+static int __devinit uhci_hcd_grlib_probe(struct platform_device *op)
+{
+ struct device_node *dn = op->dev.of_node;
+ struct usb_hcd *hcd;
+ struct uhci_hcd *uhci = NULL;
+ struct resource res;
+ int irq;
+ int rv;
+
+ if (usb_disabled())
+ return -ENODEV;
+
+ dev_dbg(&op->dev, "initializing GRUSBHC UHCI USB Controller\n");
+
+ rv = of_address_to_resource(dn, 0, &res);
+ if (rv)
+ return rv;
+
+ /* usb_create_hcd requires dma_mask != NULL */
+ op->dev.dma_mask = &op->dev.coherent_dma_mask;
+ hcd = usb_create_hcd(&uhci_grlib_hc_driver, &op->dev,
+ "GRUSBHC UHCI USB");
+ if (!hcd)
+ return -ENOMEM;
+
+ hcd->rsrc_start = res.start;
+ hcd->rsrc_len = res.end - res.start + 1;
+
+ if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) {
+ printk(KERN_ERR "%s: request_mem_region failed\n", __FILE__);
+ rv = -EBUSY;
+ goto err_rmr;
+ }
+
+ irq = irq_of_parse_and_map(dn, 0);
+ if (irq == NO_IRQ) {
+ printk(KERN_ERR "%s: irq_of_parse_and_map failed\n", __FILE__);
+ rv = -EBUSY;
+ goto err_irq;
+ }
+
+ hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
+ if (!hcd->regs) {
+ printk(KERN_ERR "%s: ioremap failed\n", __FILE__);
+ rv = -ENOMEM;
+ goto err_ioremap;
+ }
+
+ uhci = hcd_to_uhci(hcd);
+
+ uhci->regs = hcd->regs;
+
+ rv = usb_add_hcd(hcd, irq, 0);
+ if (rv)
+ goto err_uhci;
+
+ return 0;
+
+err_uhci:
+ iounmap(hcd->regs);
+err_ioremap:
+ irq_dispose_mapping(irq);
+err_irq:
+ release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
+err_rmr:
+ usb_put_hcd(hcd);
+
+ return rv;
+}
+
+static int uhci_hcd_grlib_remove(struct platform_device *op)
+{
+ struct usb_hcd *hcd = dev_get_drvdata(&op->dev);
+
+ dev_set_drvdata(&op->dev, NULL);
+
+ dev_dbg(&op->dev, "stopping GRLIB GRUSBHC UHCI USB Controller\n");
+
+ usb_remove_hcd(hcd);
+
+ iounmap(hcd->regs);
+ irq_dispose_mapping(hcd->irq);
+ release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
+
+ usb_put_hcd(hcd);
+
+ return 0;
+}
+
+/* Make sure the controller is quiescent and that we're not using it
+ * any more. This is mainly for the benefit of programs which, like kexec,
+ * expect the hardware to be idle: not doing DMA or generating IRQs.
+ *
+ * This routine may be called in a damaged or failing kernel. Hence we
+ * do not acquire the spinlock before shutting down the controller.
+ */
+static void uhci_hcd_grlib_shutdown(struct platform_device *op)
+{
+ struct usb_hcd *hcd = dev_get_drvdata(&op->dev);
+
+ uhci_hc_died(hcd_to_uhci(hcd));
+}
+
+static const struct of_device_id uhci_hcd_grlib_of_match[] = {
+ { .name = "GAISLER_UHCI", },
+ { .name = "01_027", },
+ {},
+};
+MODULE_DEVICE_TABLE(of, uhci_hcd_grlib_of_match);
+
+
+static struct platform_driver uhci_grlib_driver = {
+ .probe = uhci_hcd_grlib_probe,
+ .remove = uhci_hcd_grlib_remove,
+ .shutdown = uhci_hcd_grlib_shutdown,
+ .driver = {
+ .name = "grlib-uhci",
+ .owner = THIS_MODULE,
+ .of_match_table = uhci_hcd_grlib_of_match,
+ },
+};
diff --git a/drivers/usb/host/uhci-hcd.c b/drivers/usb/host/uhci-hcd.c
index 448b9d1..fba99b1 100644
--- a/drivers/usb/host/uhci-hcd.c
+++ b/drivers/usb/host/uhci-hcd.c
@@ -48,7 +48,6 @@
#include <asm/system.h>
#include "uhci-hcd.h"
-#include "pci-quirks.h"
/*
* Version Information
@@ -94,7 +93,7 @@
/*
* Calculate the link pointer DMA value for the first Skeleton QH in a frame.
*/
-static __le32 uhci_frame_skel_link(struct uhci_hcd *uhci, int frame)
+static __hc32 uhci_frame_skel_link(struct uhci_hcd *uhci, int frame)
{
int skelnum;
@@ -116,7 +115,7 @@
skelnum = 8 - (int) __ffs(frame | UHCI_NUMFRAMES);
if (skelnum <= 1)
skelnum = 9;
- return LINK_TO_QH(uhci->skelqh[skelnum]);
+ return LINK_TO_QH(uhci, uhci->skelqh[skelnum]);
}
#include "uhci-debug.c"
@@ -135,15 +134,12 @@
* We have to clear them by hand.
*/
for (port = 0; port < uhci->rh_numports; ++port)
- outw(0, uhci->io_addr + USBPORTSC1 + (port * 2));
+ uhci_writew(uhci, 0, USBPORTSC1 + (port * 2));
uhci->port_c_suspend = uhci->resuming_ports = 0;
uhci->rh_state = UHCI_RH_RESET;
uhci->is_stopped = UHCI_IS_STOPPED;
- uhci_to_hcd(uhci)->state = HC_STATE_HALT;
clear_bit(HCD_FLAG_POLL_RH, &uhci_to_hcd(uhci)->flags);
-
- uhci->dead = 0; /* Full reset resurrects the controller */
}
/*
@@ -153,7 +149,7 @@
static void uhci_hc_died(struct uhci_hcd *uhci)
{
uhci_get_current_frame_number(uhci);
- uhci_reset_hc(to_pci_dev(uhci_dev(uhci)), uhci->io_addr);
+ uhci->reset_hc(uhci);
finish_reset(uhci);
uhci->dead = 1;
@@ -168,97 +164,118 @@
*/
static void check_and_reset_hc(struct uhci_hcd *uhci)
{
- if (uhci_check_and_reset_hc(to_pci_dev(uhci_dev(uhci)), uhci->io_addr))
+ if (uhci->check_and_reset_hc(uhci))
finish_reset(uhci);
}
+#if defined(CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC)
+/*
+ * The two functions below are generic reset functions that are used on systems
+ * that do not have keyboard and mouse legacy support. We assume that we are
+ * running on such a system if CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC is defined.
+ */
+
+/*
+ * Make sure the controller is completely inactive, unable to
+ * generate interrupts or do DMA.
+ */
+static void uhci_generic_reset_hc(struct uhci_hcd *uhci)
+{
+ /* Reset the HC - this will force us to get a
+ * new notification of any already connected
+ * ports due to the virtual disconnect that it
+ * implies.
+ */
+ uhci_writew(uhci, USBCMD_HCRESET, USBCMD);
+ mb();
+ udelay(5);
+ if (uhci_readw(uhci, USBCMD) & USBCMD_HCRESET)
+ dev_warn(uhci_dev(uhci), "HCRESET not completed yet!\n");
+
+ /* Just to be safe, disable interrupt requests and
+ * make sure the controller is stopped.
+ */
+ uhci_writew(uhci, 0, USBINTR);
+ uhci_writew(uhci, 0, USBCMD);
+}
+
+/*
+ * Initialize a controller that was newly discovered or has just been
+ * resumed. In either case we can't be sure of its previous state.
+ *
+ * Returns: 1 if the controller was reset, 0 otherwise.
+ */
+static int uhci_generic_check_and_reset_hc(struct uhci_hcd *uhci)
+{
+ unsigned int cmd, intr;
+
+ /*
+ * When restarting a suspended controller, we expect all the
+ * settings to be the same as we left them:
+ *
+ * Controller is stopped and configured with EGSM set;
+ * No interrupts enabled except possibly Resume Detect.
+ *
+ * If any of these conditions are violated we do a complete reset.
+ */
+
+ cmd = uhci_readw(uhci, USBCMD);
+ if ((cmd & USBCMD_RS) || !(cmd & USBCMD_CF) || !(cmd & USBCMD_EGSM)) {
+ dev_dbg(uhci_dev(uhci), "%s: cmd = 0x%04x\n",
+ __func__, cmd);
+ goto reset_needed;
+ }
+
+ intr = uhci_readw(uhci, USBINTR);
+ if (intr & (~USBINTR_RESUME)) {
+ dev_dbg(uhci_dev(uhci), "%s: intr = 0x%04x\n",
+ __func__, intr);
+ goto reset_needed;
+ }
+ return 0;
+
+reset_needed:
+ dev_dbg(uhci_dev(uhci), "Performing full reset\n");
+ uhci_generic_reset_hc(uhci);
+ return 1;
+}
+#endif /* CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC */
+
/*
* Store the basic register settings needed by the controller.
*/
static void configure_hc(struct uhci_hcd *uhci)
{
- struct pci_dev *pdev = to_pci_dev(uhci_dev(uhci));
-
/* Set the frame length to the default: 1 ms exactly */
- outb(USBSOF_DEFAULT, uhci->io_addr + USBSOF);
+ uhci_writeb(uhci, USBSOF_DEFAULT, USBSOF);
/* Store the frame list base address */
- outl(uhci->frame_dma_handle, uhci->io_addr + USBFLBASEADD);
+ uhci_writel(uhci, uhci->frame_dma_handle, USBFLBASEADD);
/* Set the current frame number */
- outw(uhci->frame_number & UHCI_MAX_SOF_NUMBER,
- uhci->io_addr + USBFRNUM);
+ uhci_writew(uhci, uhci->frame_number & UHCI_MAX_SOF_NUMBER,
+ USBFRNUM);
- /* Mark controller as not halted before we enable interrupts */
- uhci_to_hcd(uhci)->state = HC_STATE_SUSPENDED;
- mb();
-
- /* Enable PIRQ */
- pci_write_config_word(pdev, USBLEGSUP, USBLEGSUP_DEFAULT);
-
- /* Disable platform-specific non-PME# wakeup */
- if (pdev->vendor == PCI_VENDOR_ID_INTEL)
- pci_write_config_byte(pdev, USBRES_INTEL, 0);
+ /* perform any arch/bus specific configuration */
+ if (uhci->configure_hc)
+ uhci->configure_hc(uhci);
}
-
static int resume_detect_interrupts_are_broken(struct uhci_hcd *uhci)
{
- int port;
-
/* If we have to ignore overcurrent events then almost by definition
* we can't depend on resume-detect interrupts. */
if (ignore_oc)
return 1;
- switch (to_pci_dev(uhci_dev(uhci))->vendor) {
- default:
- break;
-
- case PCI_VENDOR_ID_GENESYS:
- /* Genesys Logic's GL880S controllers don't generate
- * resume-detect interrupts.
- */
- return 1;
-
- case PCI_VENDOR_ID_INTEL:
- /* Some of Intel's USB controllers have a bug that causes
- * resume-detect interrupts if any port has an over-current
- * condition. To make matters worse, some motherboards
- * hardwire unused USB ports' over-current inputs active!
- * To prevent problems, we will not enable resume-detect
- * interrupts if any ports are OC.
- */
- for (port = 0; port < uhci->rh_numports; ++port) {
- if (inw(uhci->io_addr + USBPORTSC1 + port * 2) &
- USBPORTSC_OC)
- return 1;
- }
- break;
- }
- return 0;
+ return uhci->resume_detect_interrupts_are_broken ?
+ uhci->resume_detect_interrupts_are_broken(uhci) : 0;
}
static int global_suspend_mode_is_broken(struct uhci_hcd *uhci)
{
- int port;
- const char *sys_info;
- static char bad_Asus_board[] = "A7V8X";
-
- /* One of Asus's motherboards has a bug which causes it to
- * wake up immediately from suspend-to-RAM if any of the ports
- * are connected. In such cases we will not set EGSM.
- */
- sys_info = dmi_get_system_info(DMI_BOARD_NAME);
- if (sys_info && !strcmp(sys_info, bad_Asus_board)) {
- for (port = 0; port < uhci->rh_numports; ++port) {
- if (inw(uhci->io_addr + USBPORTSC1 + port * 2) &
- USBPORTSC_CCS)
- return 1;
- }
- }
-
- return 0;
+ return uhci->global_suspend_mode_is_broken ?
+ uhci->global_suspend_mode_is_broken(uhci) : 0;
}
static void suspend_rh(struct uhci_hcd *uhci, enum uhci_rh_state new_state)
@@ -321,8 +338,8 @@
!int_enable)
uhci->RD_enable = int_enable = 0;
- outw(int_enable, uhci->io_addr + USBINTR);
- outw(egsm_enable | USBCMD_CF, uhci->io_addr + USBCMD);
+ uhci_writew(uhci, int_enable, USBINTR);
+ uhci_writew(uhci, egsm_enable | USBCMD_CF, USBCMD);
mb();
udelay(5);
@@ -331,7 +348,7 @@
* controller should stop after a few microseconds. Otherwise
* we will give the controller one frame to stop.
*/
- if (!auto_stop && !(inw(uhci->io_addr + USBSTS) & USBSTS_HCH)) {
+ if (!auto_stop && !(uhci_readw(uhci, USBSTS) & USBSTS_HCH)) {
uhci->rh_state = UHCI_RH_SUSPENDING;
spin_unlock_irq(&uhci->lock);
msleep(1);
@@ -339,7 +356,7 @@
if (uhci->dead)
return;
}
- if (!(inw(uhci->io_addr + USBSTS) & USBSTS_HCH))
+ if (!(uhci_readw(uhci, USBSTS) & USBSTS_HCH))
dev_warn(uhci_dev(uhci), "Controller not stopped yet!\n");
uhci_get_current_frame_number(uhci);
@@ -361,15 +378,14 @@
static void start_rh(struct uhci_hcd *uhci)
{
- uhci_to_hcd(uhci)->state = HC_STATE_RUNNING;
uhci->is_stopped = 0;
/* Mark it configured and running with a 64-byte max packet.
* All interrupts are enabled, even though RESUME won't do anything.
*/
- outw(USBCMD_RS | USBCMD_CF | USBCMD_MAXP, uhci->io_addr + USBCMD);
- outw(USBINTR_TIMEOUT | USBINTR_RESUME | USBINTR_IOC | USBINTR_SP,
- uhci->io_addr + USBINTR);
+ uhci_writew(uhci, USBCMD_RS | USBCMD_CF | USBCMD_MAXP, USBCMD);
+ uhci_writew(uhci, USBINTR_TIMEOUT | USBINTR_RESUME |
+ USBINTR_IOC | USBINTR_SP, USBINTR);
mb();
uhci->rh_state = UHCI_RH_RUNNING;
set_bit(HCD_FLAG_POLL_RH, &uhci_to_hcd(uhci)->flags);
@@ -392,9 +408,9 @@
unsigned egsm;
/* Keep EGSM on if it was set before */
- egsm = inw(uhci->io_addr + USBCMD) & USBCMD_EGSM;
+ egsm = uhci_readw(uhci, USBCMD) & USBCMD_EGSM;
uhci->rh_state = UHCI_RH_RESUMING;
- outw(USBCMD_FGR | USBCMD_CF | egsm, uhci->io_addr + USBCMD);
+ uhci_writew(uhci, USBCMD_FGR | USBCMD_CF | egsm, USBCMD);
spin_unlock_irq(&uhci->lock);
msleep(20);
spin_lock_irq(&uhci->lock);
@@ -402,10 +418,10 @@
return;
/* End Global Resume and wait for EOP to be sent */
- outw(USBCMD_CF, uhci->io_addr + USBCMD);
+ uhci_writew(uhci, USBCMD_CF, USBCMD);
mb();
udelay(4);
- if (inw(uhci->io_addr + USBCMD) & USBCMD_FGR)
+ if (uhci_readw(uhci, USBCMD) & USBCMD_FGR)
dev_warn(uhci_dev(uhci), "FGR not stopped yet!\n");
}
@@ -425,10 +441,10 @@
* interrupt cause. Contrary to the UHCI specification, the
* "HC Halted" status bit is persistent: it is RO, not R/WC.
*/
- status = inw(uhci->io_addr + USBSTS);
+ status = uhci_readw(uhci, USBSTS);
if (!(status & ~USBSTS_HCH)) /* shared interrupt, not mine */
return IRQ_NONE;
- outw(status, uhci->io_addr + USBSTS); /* Clear it */
+ uhci_writew(uhci, status, USBSTS); /* Clear it */
if (status & ~(USBSTS_USBINT | USBSTS_ERROR | USBSTS_RD)) {
if (status & USBSTS_HSE)
@@ -450,6 +466,7 @@
lprintk(errbuf);
}
uhci_hc_died(uhci);
+ usb_hc_died(hcd);
/* Force a callback in case there are
* pending unlinks */
@@ -483,7 +500,7 @@
if (!uhci->is_stopped) {
unsigned delta;
- delta = (inw(uhci->io_addr + USBFRNUM) - uhci->frame_number) &
+ delta = (uhci_readw(uhci, USBFRNUM) - uhci->frame_number) &
(UHCI_NUMFRAMES - 1);
uhci->frame_number += delta;
}
@@ -520,61 +537,6 @@
uhci->frame, uhci->frame_dma_handle);
}
-static int uhci_init(struct usb_hcd *hcd)
-{
- struct uhci_hcd *uhci = hcd_to_uhci(hcd);
- unsigned io_size = (unsigned) hcd->rsrc_len;
- int port;
-
- uhci->io_addr = (unsigned long) hcd->rsrc_start;
-
- /* The UHCI spec says devices must have 2 ports, and goes on to say
- * they may have more but gives no way to determine how many there
- * are. However according to the UHCI spec, Bit 7 of the port
- * status and control register is always set to 1. So we try to
- * use this to our advantage. Another common failure mode when
- * a nonexistent register is addressed is to return all ones, so
- * we test for that also.
- */
- for (port = 0; port < (io_size - USBPORTSC1) / 2; port++) {
- unsigned int portstatus;
-
- portstatus = inw(uhci->io_addr + USBPORTSC1 + (port * 2));
- if (!(portstatus & 0x0080) || portstatus == 0xffff)
- break;
- }
- if (debug)
- dev_info(uhci_dev(uhci), "detected %d ports\n", port);
-
- /* Anything greater than 7 is weird so we'll ignore it. */
- if (port > UHCI_RH_MAXCHILD) {
- dev_info(uhci_dev(uhci), "port count misdetected? "
- "forcing to 2 ports\n");
- port = 2;
- }
- uhci->rh_numports = port;
-
- /* Kick BIOS off this hardware and reset if the controller
- * isn't already safely quiescent.
- */
- check_and_reset_hc(uhci);
- return 0;
-}
-
-/* Make sure the controller is quiescent and that we're not using it
- * any more. This is mainly for the benefit of programs which, like kexec,
- * expect the hardware to be idle: not doing DMA or generating IRQs.
- *
- * This routine may be called in a damaged or failing kernel. Hence we
- * do not acquire the spinlock before shutting down the controller.
- */
-static void uhci_shutdown(struct pci_dev *pdev)
-{
- struct usb_hcd *hcd = pci_get_drvdata(pdev);
-
- uhci_hc_died(hcd_to_uhci(hcd));
-}
-
/*
* Allocate a frame list, and then setup the skeleton
*
@@ -669,16 +631,16 @@
* 8 Interrupt queues; link all higher int queues to int1 = async
*/
for (i = SKEL_ISO + 1; i < SKEL_ASYNC; ++i)
- uhci->skelqh[i]->link = LINK_TO_QH(uhci->skel_async_qh);
- uhci->skel_async_qh->link = UHCI_PTR_TERM;
- uhci->skel_term_qh->link = LINK_TO_QH(uhci->skel_term_qh);
+ uhci->skelqh[i]->link = LINK_TO_QH(uhci, uhci->skel_async_qh);
+ uhci->skel_async_qh->link = UHCI_PTR_TERM(uhci);
+ uhci->skel_term_qh->link = LINK_TO_QH(uhci, uhci->skel_term_qh);
/* This dummy TD is to work around a bug in Intel PIIX controllers */
- uhci_fill_td(uhci->term_td, 0, uhci_explen(0) |
+ uhci_fill_td(uhci, uhci->term_td, 0, uhci_explen(0) |
(0x7f << TD_TOKEN_DEVADDR_SHIFT) | USB_PID_IN, 0);
- uhci->term_td->link = UHCI_PTR_TERM;
+ uhci->term_td->link = UHCI_PTR_TERM(uhci);
uhci->skel_async_qh->element = uhci->skel_term_qh->element =
- LINK_TO_TD(uhci->term_td);
+ LINK_TO_TD(uhci, uhci->term_td);
/*
* Fill the frame list: make all entries point to the proper
@@ -791,86 +753,6 @@
return rc;
}
-static int uhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
-{
- struct uhci_hcd *uhci = hcd_to_uhci(hcd);
- struct pci_dev *pdev = to_pci_dev(uhci_dev(uhci));
- int rc = 0;
-
- dev_dbg(uhci_dev(uhci), "%s\n", __func__);
-
- spin_lock_irq(&uhci->lock);
- if (!HCD_HW_ACCESSIBLE(hcd) || uhci->dead)
- goto done_okay; /* Already suspended or dead */
-
- if (uhci->rh_state > UHCI_RH_SUSPENDED) {
- dev_warn(uhci_dev(uhci), "Root hub isn't suspended!\n");
- rc = -EBUSY;
- goto done;
- };
-
- /* All PCI host controllers are required to disable IRQ generation
- * at the source, so we must turn off PIRQ.
- */
- pci_write_config_word(pdev, USBLEGSUP, 0);
- clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
-
- /* Enable platform-specific non-PME# wakeup */
- if (do_wakeup) {
- if (pdev->vendor == PCI_VENDOR_ID_INTEL)
- pci_write_config_byte(pdev, USBRES_INTEL,
- USBPORT1EN | USBPORT2EN);
- }
-
-done_okay:
- clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
-done:
- spin_unlock_irq(&uhci->lock);
- return rc;
-}
-
-static int uhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
-{
- struct uhci_hcd *uhci = hcd_to_uhci(hcd);
-
- dev_dbg(uhci_dev(uhci), "%s\n", __func__);
-
- /* Since we aren't in D3 any more, it's safe to set this flag
- * even if the controller was dead.
- */
- set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
-
- spin_lock_irq(&uhci->lock);
-
- /* Make sure resume from hibernation re-enumerates everything */
- if (hibernated)
- uhci_hc_died(uhci);
-
- /* The firmware or a boot kernel may have changed the controller
- * settings during a system wakeup. Check it and reconfigure
- * to avoid problems.
- */
- check_and_reset_hc(uhci);
-
- /* If the controller was dead before, it's back alive now */
- configure_hc(uhci);
-
- /* Tell the core if the controller had to be reset */
- if (uhci->rh_state == UHCI_RH_RESET)
- usb_root_hub_lost_power(hcd->self.root_hub);
-
- spin_unlock_irq(&uhci->lock);
-
- /* If interrupts don't work and remote wakeup is enabled then
- * the suspended root hub needs to be polled.
- */
- if (!uhci->RD_enable && hcd->self.root_hub->do_remote_wakeup)
- set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
-
- /* Does the root hub have a port wakeup pending? */
- usb_hcd_poll_rh_status(hcd);
- return 0;
-}
#endif
/* Wait until a particular device/endpoint's QH is idle, and free it */
@@ -908,67 +790,62 @@
/* Minimize latency by avoiding the spinlock */
frame_number = uhci->frame_number;
barrier();
- delta = (inw(uhci->io_addr + USBFRNUM) - frame_number) &
+ delta = (uhci_readw(uhci, USBFRNUM) - frame_number) &
(UHCI_NUMFRAMES - 1);
return frame_number + delta;
}
+/* Determines number of ports on controller */
+static int uhci_count_ports(struct usb_hcd *hcd)
+{
+ struct uhci_hcd *uhci = hcd_to_uhci(hcd);
+ unsigned io_size = (unsigned) hcd->rsrc_len;
+ int port;
+
+ /* The UHCI spec says devices must have 2 ports, and goes on to say
+ * they may have more but gives no way to determine how many there
+ * are. However according to the UHCI spec, Bit 7 of the port
+ * status and control register is always set to 1. So we try to
+ * use this to our advantage. Another common failure mode when
+ * a nonexistent register is addressed is to return all ones, so
+ * we test for that also.
+ */
+ for (port = 0; port < (io_size - USBPORTSC1) / 2; port++) {
+ unsigned int portstatus;
+
+ portstatus = uhci_readw(uhci, USBPORTSC1 + (port * 2));
+ if (!(portstatus & 0x0080) || portstatus == 0xffff)
+ break;
+ }
+ if (debug)
+ dev_info(uhci_dev(uhci), "detected %d ports\n", port);
+
+ /* Anything greater than 7 is weird so we'll ignore it. */
+ if (port > UHCI_RH_MAXCHILD) {
+ dev_info(uhci_dev(uhci), "port count misdetected? "
+ "forcing to 2 ports\n");
+ port = 2;
+ }
+
+ return port;
+}
+
static const char hcd_name[] = "uhci_hcd";
-static const struct hc_driver uhci_driver = {
- .description = hcd_name,
- .product_desc = "UHCI Host Controller",
- .hcd_priv_size = sizeof(struct uhci_hcd),
-
- /* Generic hardware linkage */
- .irq = uhci_irq,
- .flags = HCD_USB11,
-
- /* Basic lifecycle operations */
- .reset = uhci_init,
- .start = uhci_start,
-#ifdef CONFIG_PM
- .pci_suspend = uhci_pci_suspend,
- .pci_resume = uhci_pci_resume,
- .bus_suspend = uhci_rh_suspend,
- .bus_resume = uhci_rh_resume,
+#ifdef CONFIG_PCI
+#include "uhci-pci.c"
+#define PCI_DRIVER uhci_pci_driver
#endif
- .stop = uhci_stop,
- .urb_enqueue = uhci_urb_enqueue,
- .urb_dequeue = uhci_urb_dequeue,
-
- .endpoint_disable = uhci_hcd_endpoint_disable,
- .get_frame_number = uhci_hcd_get_frame_number,
-
- .hub_status_data = uhci_hub_status_data,
- .hub_control = uhci_hub_control,
-};
-
-static const struct pci_device_id uhci_pci_ids[] = { {
- /* handle any USB UHCI controller */
- PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_UHCI, ~0),
- .driver_data = (unsigned long) &uhci_driver,
- }, { /* end: all zeroes */ }
-};
-
-MODULE_DEVICE_TABLE(pci, uhci_pci_ids);
-
-static struct pci_driver uhci_pci_driver = {
- .name = (char *)hcd_name,
- .id_table = uhci_pci_ids,
-
- .probe = usb_hcd_pci_probe,
- .remove = usb_hcd_pci_remove,
- .shutdown = uhci_shutdown,
-
-#ifdef CONFIG_PM_SLEEP
- .driver = {
- .pm = &usb_hcd_pci_pm_ops
- },
+#ifdef CONFIG_SPARC_LEON
+#include "uhci-grlib.c"
+#define PLATFORM_DRIVER uhci_grlib_driver
#endif
-};
-
+
+#if !defined(PCI_DRIVER) && !defined(PLATFORM_DRIVER)
+#error "missing bus glue for uhci-hcd"
+#endif
+
static int __init uhci_hcd_init(void)
{
int retval = -ENOMEM;
@@ -994,13 +871,27 @@
if (!uhci_up_cachep)
goto up_failed;
- retval = pci_register_driver(&uhci_pci_driver);
- if (retval)
- goto init_failed;
+#ifdef PLATFORM_DRIVER
+ retval = platform_driver_register(&PLATFORM_DRIVER);
+ if (retval < 0)
+ goto clean0;
+#endif
+
+#ifdef PCI_DRIVER
+ retval = pci_register_driver(&PCI_DRIVER);
+ if (retval < 0)
+ goto clean1;
+#endif
return 0;
-init_failed:
+#ifdef PCI_DRIVER
+clean1:
+#endif
+#ifdef PLATFORM_DRIVER
+ platform_driver_unregister(&PLATFORM_DRIVER);
+clean0:
+#endif
kmem_cache_destroy(uhci_up_cachep);
up_failed:
@@ -1017,7 +908,12 @@
static void __exit uhci_hcd_cleanup(void)
{
- pci_unregister_driver(&uhci_pci_driver);
+#ifdef PLATFORM_DRIVER
+ platform_driver_unregister(&PLATFORM_DRIVER);
+#endif
+#ifdef PCI_DRIVER
+ pci_unregister_driver(&PCI_DRIVER);
+#endif
kmem_cache_destroy(uhci_up_cachep);
debugfs_remove(uhci_debugfs_root);
kfree(errbuf);
diff --git a/drivers/usb/host/uhci-hcd.h b/drivers/usb/host/uhci-hcd.h
index 49bf279..7af2b70 100644
--- a/drivers/usb/host/uhci-hcd.h
+++ b/drivers/usb/host/uhci-hcd.h
@@ -78,11 +78,11 @@
#define USBPORT1EN 0x01
#define USBPORT2EN 0x02
-#define UHCI_PTR_BITS cpu_to_le32(0x000F)
-#define UHCI_PTR_TERM cpu_to_le32(0x0001)
-#define UHCI_PTR_QH cpu_to_le32(0x0002)
-#define UHCI_PTR_DEPTH cpu_to_le32(0x0004)
-#define UHCI_PTR_BREADTH cpu_to_le32(0x0000)
+#define UHCI_PTR_BITS(uhci) cpu_to_hc32((uhci), 0x000F)
+#define UHCI_PTR_TERM(uhci) cpu_to_hc32((uhci), 0x0001)
+#define UHCI_PTR_QH(uhci) cpu_to_hc32((uhci), 0x0002)
+#define UHCI_PTR_DEPTH(uhci) cpu_to_hc32((uhci), 0x0004)
+#define UHCI_PTR_BREADTH(uhci) cpu_to_hc32((uhci), 0x0000)
#define UHCI_NUMFRAMES 1024 /* in the frame list [array] */
#define UHCI_MAX_SOF_NUMBER 2047 /* in an SOF packet */
@@ -99,6 +99,22 @@
/*
+ * __hc32 and __hc16 are "Host Controller" types, they may be equivalent to
+ * __leXX (normally) or __beXX (given UHCI_BIG_ENDIAN_DESC), depending on
+ * the host controller implementation.
+ *
+ * To facilitate the strongest possible byte-order checking from "sparse"
+ * and so on, we use __leXX unless that's not practical.
+ */
+#ifdef CONFIG_USB_UHCI_BIG_ENDIAN_DESC
+typedef __u32 __bitwise __hc32;
+typedef __u16 __bitwise __hc16;
+#else
+#define __hc32 __le32
+#define __hc16 __le16
+#endif
+
+/*
* Queue Headers
*/
@@ -130,8 +146,8 @@
struct uhci_qh {
/* Hardware fields */
- __le32 link; /* Next QH in the schedule */
- __le32 element; /* Queue element (TD) pointer */
+ __hc32 link; /* Next QH in the schedule */
+ __hc32 element; /* Queue element (TD) pointer */
/* Software fields */
dma_addr_t dma_handle;
@@ -168,14 +184,10 @@
* We need a special accessor for the element pointer because it is
* subject to asynchronous updates by the controller.
*/
-static inline __le32 qh_element(struct uhci_qh *qh) {
- __le32 element = qh->element;
+#define qh_element(qh) ACCESS_ONCE((qh)->element)
- barrier();
- return element;
-}
-
-#define LINK_TO_QH(qh) (UHCI_PTR_QH | cpu_to_le32((qh)->dma_handle))
+#define LINK_TO_QH(uhci, qh) (UHCI_PTR_QH((uhci)) | \
+ cpu_to_hc32((uhci), (qh)->dma_handle))
/*
@@ -212,7 +224,7 @@
/*
* for TD <info>: (a.k.a. Token)
*/
-#define td_token(td) le32_to_cpu((td)->token)
+#define td_token(uhci, td) hc32_to_cpu((uhci), (td)->token)
#define TD_TOKEN_DEVADDR_SHIFT 8
#define TD_TOKEN_TOGGLE_SHIFT 19
#define TD_TOKEN_TOGGLE (1 << 19)
@@ -245,10 +257,10 @@
*/
struct uhci_td {
/* Hardware fields */
- __le32 link;
- __le32 status;
- __le32 token;
- __le32 buffer;
+ __hc32 link;
+ __hc32 status;
+ __hc32 token;
+ __hc32 buffer;
/* Software fields */
dma_addr_t dma_handle;
@@ -263,14 +275,10 @@
* We need a special accessor for the control/status word because it is
* subject to asynchronous updates by the controller.
*/
-static inline u32 td_status(struct uhci_td *td) {
- __le32 status = td->status;
+#define td_status(uhci, td) hc32_to_cpu((uhci), \
+ ACCESS_ONCE((td)->status))
- barrier();
- return le32_to_cpu(status);
-}
-
-#define LINK_TO_TD(td) (cpu_to_le32((td)->dma_handle))
+#define LINK_TO_TD(uhci, td) (cpu_to_hc32((uhci), (td)->dma_handle))
/*
@@ -380,6 +388,9 @@
/* Grabbed from PCI */
unsigned long io_addr;
+ /* Used when registers are memory mapped */
+ void __iomem *regs;
+
struct dma_pool *qh_pool;
struct dma_pool *td_pool;
@@ -390,7 +401,7 @@
spinlock_t lock;
dma_addr_t frame_dma_handle; /* Hardware frame list */
- __le32 *frame;
+ __hc32 *frame;
void **frame_cpu; /* CPU's frame list */
enum uhci_rh_state rh_state;
@@ -415,6 +426,12 @@
struct timer_list fsbr_timer; /* For turning off FBSR */
+ /* Silicon quirks */
+ unsigned int oc_low:1; /* OverCurrent bit active low */
+ unsigned int wait_for_hp:1; /* Wait for HP port reset */
+ unsigned int big_endian_mmio:1; /* Big endian registers */
+ unsigned int big_endian_desc:1; /* Big endian descriptors */
+
/* Support for port suspend/resume/reset */
unsigned long port_c_suspend; /* Bit-arrays of ports */
unsigned long resuming_ports;
@@ -429,6 +446,16 @@
int total_load; /* Sum of array values */
short load[MAX_PHASE]; /* Periodic allocations */
+
+ /* Reset host controller */
+ void (*reset_hc) (struct uhci_hcd *uhci);
+ int (*check_and_reset_hc) (struct uhci_hcd *uhci);
+ /* configure_hc should perform arch specific settings, if needed */
+ void (*configure_hc) (struct uhci_hcd *uhci);
+ /* Check for broken resume detect interrupts */
+ int (*resume_detect_interrupts_are_broken) (struct uhci_hcd *uhci);
+ /* Check for broken global suspend */
+ int (*global_suspend_mode_is_broken) (struct uhci_hcd *uhci);
};
/* Convert between a usb_hcd pointer and the corresponding uhci_hcd */
@@ -467,4 +494,171 @@
#define PCI_VENDOR_ID_GENESYS 0x17a0
#define PCI_DEVICE_ID_GL880S_UHCI 0x8083
+/*
+ * Functions used to access controller registers. The UCHI spec says that host
+ * controller I/O registers are mapped into PCI I/O space. For non-PCI hosts
+ * we use memory mapped registers.
+ */
+
+#ifndef CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC
+/* Support PCI only */
+static inline u32 uhci_readl(const struct uhci_hcd *uhci, int reg)
+{
+ return inl(uhci->io_addr + reg);
+}
+
+static inline void uhci_writel(const struct uhci_hcd *uhci, u32 val, int reg)
+{
+ outl(val, uhci->io_addr + reg);
+}
+
+static inline u16 uhci_readw(const struct uhci_hcd *uhci, int reg)
+{
+ return inw(uhci->io_addr + reg);
+}
+
+static inline void uhci_writew(const struct uhci_hcd *uhci, u16 val, int reg)
+{
+ outw(val, uhci->io_addr + reg);
+}
+
+static inline u8 uhci_readb(const struct uhci_hcd *uhci, int reg)
+{
+ return inb(uhci->io_addr + reg);
+}
+
+static inline void uhci_writeb(const struct uhci_hcd *uhci, u8 val, int reg)
+{
+ outb(val, uhci->io_addr + reg);
+}
+
+#else
+/* Support non-PCI host controllers */
+#ifdef CONFIG_PCI
+/* Support PCI and non-PCI host controllers */
+#define uhci_has_pci_registers(u) ((u)->io_addr != 0)
+#else
+/* Support non-PCI host controllers only */
+#define uhci_has_pci_registers(u) 0
+#endif
+
+#ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
+/* Support (non-PCI) big endian host controllers */
+#define uhci_big_endian_mmio(u) ((u)->big_endian_mmio)
+#else
+#define uhci_big_endian_mmio(u) 0
+#endif
+
+static inline u32 uhci_readl(const struct uhci_hcd *uhci, int reg)
+{
+ if (uhci_has_pci_registers(uhci))
+ return inl(uhci->io_addr + reg);
+#ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
+ else if (uhci_big_endian_mmio(uhci))
+ return readl_be(uhci->regs + reg);
+#endif
+ else
+ return readl(uhci->regs + reg);
+}
+
+static inline void uhci_writel(const struct uhci_hcd *uhci, u32 val, int reg)
+{
+ if (uhci_has_pci_registers(uhci))
+ outl(val, uhci->io_addr + reg);
+#ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
+ else if (uhci_big_endian_mmio(uhci))
+ writel_be(val, uhci->regs + reg);
+#endif
+ else
+ writel(val, uhci->regs + reg);
+}
+
+static inline u16 uhci_readw(const struct uhci_hcd *uhci, int reg)
+{
+ if (uhci_has_pci_registers(uhci))
+ return inw(uhci->io_addr + reg);
+#ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
+ else if (uhci_big_endian_mmio(uhci))
+ return readw_be(uhci->regs + reg);
+#endif
+ else
+ return readw(uhci->regs + reg);
+}
+
+static inline void uhci_writew(const struct uhci_hcd *uhci, u16 val, int reg)
+{
+ if (uhci_has_pci_registers(uhci))
+ outw(val, uhci->io_addr + reg);
+#ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
+ else if (uhci_big_endian_mmio(uhci))
+ writew_be(val, uhci->regs + reg);
+#endif
+ else
+ writew(val, uhci->regs + reg);
+}
+
+static inline u8 uhci_readb(const struct uhci_hcd *uhci, int reg)
+{
+ if (uhci_has_pci_registers(uhci))
+ return inb(uhci->io_addr + reg);
+#ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
+ else if (uhci_big_endian_mmio(uhci))
+ return readb_be(uhci->regs + reg);
+#endif
+ else
+ return readb(uhci->regs + reg);
+}
+
+static inline void uhci_writeb(const struct uhci_hcd *uhci, u8 val, int reg)
+{
+ if (uhci_has_pci_registers(uhci))
+ outb(val, uhci->io_addr + reg);
+#ifdef CONFIG_USB_UHCI_BIG_ENDIAN_MMIO
+ else if (uhci_big_endian_mmio(uhci))
+ writeb_be(val, uhci->regs + reg);
+#endif
+ else
+ writeb(val, uhci->regs + reg);
+}
+#endif /* CONFIG_USB_UHCI_SUPPORT_NON_PCI_HC */
+
+/*
+ * The GRLIB GRUSBHC controller can use big endian format for its descriptors.
+ *
+ * UHCI controllers accessed through PCI work normally (little-endian
+ * everywhere), so we don't bother supporting a BE-only mode.
+ */
+#ifdef CONFIG_USB_UHCI_BIG_ENDIAN_DESC
+#define uhci_big_endian_desc(u) ((u)->big_endian_desc)
+
+/* cpu to uhci */
+static inline __hc32 cpu_to_hc32(const struct uhci_hcd *uhci, const u32 x)
+{
+ return uhci_big_endian_desc(uhci)
+ ? (__force __hc32)cpu_to_be32(x)
+ : (__force __hc32)cpu_to_le32(x);
+}
+
+/* uhci to cpu */
+static inline u32 hc32_to_cpu(const struct uhci_hcd *uhci, const __hc32 x)
+{
+ return uhci_big_endian_desc(uhci)
+ ? be32_to_cpu((__force __be32)x)
+ : le32_to_cpu((__force __le32)x);
+}
+
+#else
+/* cpu to uhci */
+static inline __hc32 cpu_to_hc32(const struct uhci_hcd *uhci, const u32 x)
+{
+ return cpu_to_le32(x);
+}
+
+/* uhci to cpu */
+static inline u32 hc32_to_cpu(const struct uhci_hcd *uhci, const __hc32 x)
+{
+ return le32_to_cpu(x);
+}
+#endif
+
#endif
diff --git a/drivers/usb/host/uhci-hub.c b/drivers/usb/host/uhci-hub.c
index 6d59c0f..045cde4 100644
--- a/drivers/usb/host/uhci-hub.c
+++ b/drivers/usb/host/uhci-hub.c
@@ -44,7 +44,7 @@
int port;
for (port = 0; port < uhci->rh_numports; ++port) {
- if ((inw(uhci->io_addr + USBPORTSC1 + port * 2) &
+ if ((uhci_readw(uhci, USBPORTSC1 + port * 2) &
(USBPORTSC_CCS | RWC_BITS)) ||
test_bit(port, &uhci->port_c_suspend))
return 1;
@@ -68,7 +68,7 @@
*buf = 0;
for (port = 0; port < uhci->rh_numports; ++port) {
- if ((inw(uhci->io_addr + USBPORTSC1 + port * 2) & mask) ||
+ if ((uhci_readw(uhci, USBPORTSC1 + port * 2) & mask) ||
test_bit(port, &uhci->port_c_suspend))
*buf |= (1 << (port + 1));
}
@@ -78,17 +78,17 @@
#define OK(x) len = (x); break
#define CLR_RH_PORTSTAT(x) \
- status = inw(port_addr); \
+ status = uhci_readw(uhci, port_addr); \
status &= ~(RWC_BITS|WZ_BITS); \
status &= ~(x); \
status |= RWC_BITS & (x); \
- outw(status, port_addr)
+ uhci_writew(uhci, status, port_addr)
#define SET_RH_PORTSTAT(x) \
- status = inw(port_addr); \
+ status = uhci_readw(uhci, port_addr); \
status |= (x); \
status &= ~(RWC_BITS|WZ_BITS); \
- outw(status, port_addr)
+ uhci_writew(uhci, status, port_addr)
/* UHCI controllers don't automatically stop resume signalling after 20 msec,
* so we have to poll and check timeouts in order to take care of it.
@@ -99,7 +99,7 @@
int status;
int i;
- if (inw(port_addr) & SUSPEND_BITS) {
+ if (uhci_readw(uhci, port_addr) & SUSPEND_BITS) {
CLR_RH_PORTSTAT(SUSPEND_BITS);
if (test_bit(port, &uhci->resuming_ports))
set_bit(port, &uhci->port_c_suspend);
@@ -110,7 +110,7 @@
* Experiments show that some controllers take longer, so
* we'll poll for completion. */
for (i = 0; i < 10; ++i) {
- if (!(inw(port_addr) & SUSPEND_BITS))
+ if (!(uhci_readw(uhci, port_addr) & SUSPEND_BITS))
break;
udelay(1);
}
@@ -121,12 +121,12 @@
/* Wait for the UHCI controller in HP's iLO2 server management chip.
* It can take up to 250 us to finish a reset and set the CSC bit.
*/
-static void wait_for_HP(unsigned long port_addr)
+static void wait_for_HP(struct uhci_hcd *uhci, unsigned long port_addr)
{
int i;
for (i = 10; i < 250; i += 10) {
- if (inw(port_addr) & USBPORTSC_CSC)
+ if (uhci_readw(uhci, port_addr) & USBPORTSC_CSC)
return;
udelay(10);
}
@@ -140,8 +140,8 @@
int status;
for (port = 0; port < uhci->rh_numports; ++port) {
- port_addr = uhci->io_addr + USBPORTSC1 + 2 * port;
- status = inw(port_addr);
+ port_addr = USBPORTSC1 + 2 * port;
+ status = uhci_readw(uhci, port_addr);
if (unlikely(status & USBPORTSC_PR)) {
if (time_after_eq(jiffies, uhci->ports_timeout)) {
CLR_RH_PORTSTAT(USBPORTSC_PR);
@@ -149,9 +149,8 @@
/* HP's server management chip requires
* a longer delay. */
- if (to_pci_dev(uhci_dev(uhci))->vendor ==
- PCI_VENDOR_ID_HP)
- wait_for_HP(port_addr);
+ if (uhci->wait_for_hp)
+ wait_for_HP(uhci, port_addr);
/* If the port was enabled before, turning
* reset on caused a port enable change.
@@ -242,7 +241,7 @@
struct uhci_hcd *uhci = hcd_to_uhci(hcd);
int status, lstatus, retval = 0, len = 0;
unsigned int port = wIndex - 1;
- unsigned long port_addr = uhci->io_addr + USBPORTSC1 + 2 * port;
+ unsigned long port_addr = USBPORTSC1 + 2 * port;
u16 wPortChange, wPortStatus;
unsigned long flags;
@@ -260,14 +259,13 @@
goto err;
uhci_check_ports(uhci);
- status = inw(port_addr);
+ status = uhci_readw(uhci, port_addr);
/* Intel controllers report the OverCurrent bit active on.
* VIA controllers report it active off, so we'll adjust the
* bit value. (It's not standardized in the UHCI spec.)
*/
- if (to_pci_dev(hcd->self.controller)->vendor ==
- PCI_VENDOR_ID_VIA)
+ if (uhci->oc_low)
status ^= USBPORTSC_OC;
/* UHCI doesn't support C_RESET (always false) */
@@ -358,7 +356,7 @@
CLR_RH_PORTSTAT(USBPORTSC_PEC);
OK(0);
case USB_PORT_FEAT_SUSPEND:
- if (!(inw(port_addr) & USBPORTSC_SUSP)) {
+ if (!(uhci_readw(uhci, port_addr) & USBPORTSC_SUSP)) {
/* Make certain the port isn't suspended */
uhci_finish_suspend(uhci, port, port_addr);
@@ -370,7 +368,8 @@
* if the port is disabled. When this happens
* just skip the Resume signalling.
*/
- if (!(inw(port_addr) & USBPORTSC_RD))
+ if (!(uhci_readw(uhci, port_addr) &
+ USBPORTSC_RD))
uhci_finish_suspend(uhci, port,
port_addr);
else
diff --git a/drivers/usb/host/uhci-pci.c b/drivers/usb/host/uhci-pci.c
new file mode 100644
index 0000000..c300bd2f7
--- /dev/null
+++ b/drivers/usb/host/uhci-pci.c
@@ -0,0 +1,301 @@
+/*
+ * UHCI HCD (Host Controller Driver) PCI Bus Glue.
+ *
+ * Extracted from uhci-hcd.c:
+ * Maintainer: Alan Stern <stern@rowland.harvard.edu>
+ *
+ * (C) Copyright 1999 Linus Torvalds
+ * (C) Copyright 1999-2002 Johannes Erdfelt, johannes@erdfelt.com
+ * (C) Copyright 1999 Randy Dunlap
+ * (C) Copyright 1999 Georg Acher, acher@in.tum.de
+ * (C) Copyright 1999 Deti Fliegl, deti@fliegl.de
+ * (C) Copyright 1999 Thomas Sailer, sailer@ife.ee.ethz.ch
+ * (C) Copyright 1999 Roman Weissgaerber, weissg@vienna.at
+ * (C) Copyright 2000 Yggdrasil Computing, Inc. (port of new PCI interface
+ * support from usb-ohci.c by Adam Richter, adam@yggdrasil.com).
+ * (C) Copyright 1999 Gregory P. Smith (from usb-ohci.c)
+ * (C) Copyright 2004-2007 Alan Stern, stern@rowland.harvard.edu
+ */
+
+#include "pci-quirks.h"
+
+/*
+ * Make sure the controller is completely inactive, unable to
+ * generate interrupts or do DMA.
+ */
+static void uhci_pci_reset_hc(struct uhci_hcd *uhci)
+{
+ uhci_reset_hc(to_pci_dev(uhci_dev(uhci)), uhci->io_addr);
+}
+
+/*
+ * Initialize a controller that was newly discovered or has just been
+ * resumed. In either case we can't be sure of its previous state.
+ *
+ * Returns: 1 if the controller was reset, 0 otherwise.
+ */
+static int uhci_pci_check_and_reset_hc(struct uhci_hcd *uhci)
+{
+ return uhci_check_and_reset_hc(to_pci_dev(uhci_dev(uhci)),
+ uhci->io_addr);
+}
+
+/*
+ * Store the basic register settings needed by the controller.
+ * This function is called at the end of configure_hc in uhci-hcd.c.
+ */
+static void uhci_pci_configure_hc(struct uhci_hcd *uhci)
+{
+ struct pci_dev *pdev = to_pci_dev(uhci_dev(uhci));
+
+ /* Enable PIRQ */
+ pci_write_config_word(pdev, USBLEGSUP, USBLEGSUP_DEFAULT);
+
+ /* Disable platform-specific non-PME# wakeup */
+ if (pdev->vendor == PCI_VENDOR_ID_INTEL)
+ pci_write_config_byte(pdev, USBRES_INTEL, 0);
+}
+
+static int uhci_pci_resume_detect_interrupts_are_broken(struct uhci_hcd *uhci)
+{
+ int port;
+
+ switch (to_pci_dev(uhci_dev(uhci))->vendor) {
+ default:
+ break;
+
+ case PCI_VENDOR_ID_GENESYS:
+ /* Genesys Logic's GL880S controllers don't generate
+ * resume-detect interrupts.
+ */
+ return 1;
+
+ case PCI_VENDOR_ID_INTEL:
+ /* Some of Intel's USB controllers have a bug that causes
+ * resume-detect interrupts if any port has an over-current
+ * condition. To make matters worse, some motherboards
+ * hardwire unused USB ports' over-current inputs active!
+ * To prevent problems, we will not enable resume-detect
+ * interrupts if any ports are OC.
+ */
+ for (port = 0; port < uhci->rh_numports; ++port) {
+ if (inw(uhci->io_addr + USBPORTSC1 + port * 2) &
+ USBPORTSC_OC)
+ return 1;
+ }
+ break;
+ }
+ return 0;
+}
+
+static int uhci_pci_global_suspend_mode_is_broken(struct uhci_hcd *uhci)
+{
+ int port;
+ const char *sys_info;
+ static const char bad_Asus_board[] = "A7V8X";
+
+ /* One of Asus's motherboards has a bug which causes it to
+ * wake up immediately from suspend-to-RAM if any of the ports
+ * are connected. In such cases we will not set EGSM.
+ */
+ sys_info = dmi_get_system_info(DMI_BOARD_NAME);
+ if (sys_info && !strcmp(sys_info, bad_Asus_board)) {
+ for (port = 0; port < uhci->rh_numports; ++port) {
+ if (inw(uhci->io_addr + USBPORTSC1 + port * 2) &
+ USBPORTSC_CCS)
+ return 1;
+ }
+ }
+
+ return 0;
+}
+
+static int uhci_pci_init(struct usb_hcd *hcd)
+{
+ struct uhci_hcd *uhci = hcd_to_uhci(hcd);
+
+ uhci->io_addr = (unsigned long) hcd->rsrc_start;
+
+ uhci->rh_numports = uhci_count_ports(hcd);
+
+ /* Intel controllers report the OverCurrent bit active on.
+ * VIA controllers report it active off, so we'll adjust the
+ * bit value. (It's not standardized in the UHCI spec.)
+ */
+ if (to_pci_dev(uhci_dev(uhci))->vendor == PCI_VENDOR_ID_VIA)
+ uhci->oc_low = 1;
+
+ /* HP's server management chip requires a longer port reset delay. */
+ if (to_pci_dev(uhci_dev(uhci))->vendor == PCI_VENDOR_ID_HP)
+ uhci->wait_for_hp = 1;
+
+ /* Set up pointers to PCI-specific functions */
+ uhci->reset_hc = uhci_pci_reset_hc;
+ uhci->check_and_reset_hc = uhci_pci_check_and_reset_hc;
+ uhci->configure_hc = uhci_pci_configure_hc;
+ uhci->resume_detect_interrupts_are_broken =
+ uhci_pci_resume_detect_interrupts_are_broken;
+ uhci->global_suspend_mode_is_broken =
+ uhci_pci_global_suspend_mode_is_broken;
+
+
+ /* Kick BIOS off this hardware and reset if the controller
+ * isn't already safely quiescent.
+ */
+ check_and_reset_hc(uhci);
+ return 0;
+}
+
+/* Make sure the controller is quiescent and that we're not using it
+ * any more. This is mainly for the benefit of programs which, like kexec,
+ * expect the hardware to be idle: not doing DMA or generating IRQs.
+ *
+ * This routine may be called in a damaged or failing kernel. Hence we
+ * do not acquire the spinlock before shutting down the controller.
+ */
+static void uhci_shutdown(struct pci_dev *pdev)
+{
+ struct usb_hcd *hcd = pci_get_drvdata(pdev);
+
+ uhci_hc_died(hcd_to_uhci(hcd));
+}
+
+#ifdef CONFIG_PM
+
+static int uhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
+{
+ struct uhci_hcd *uhci = hcd_to_uhci(hcd);
+ struct pci_dev *pdev = to_pci_dev(uhci_dev(uhci));
+ int rc = 0;
+
+ dev_dbg(uhci_dev(uhci), "%s\n", __func__);
+
+ spin_lock_irq(&uhci->lock);
+ if (!HCD_HW_ACCESSIBLE(hcd) || uhci->dead)
+ goto done_okay; /* Already suspended or dead */
+
+ if (uhci->rh_state > UHCI_RH_SUSPENDED) {
+ dev_warn(uhci_dev(uhci), "Root hub isn't suspended!\n");
+ rc = -EBUSY;
+ goto done;
+ };
+
+ /* All PCI host controllers are required to disable IRQ generation
+ * at the source, so we must turn off PIRQ.
+ */
+ pci_write_config_word(pdev, USBLEGSUP, 0);
+ clear_bit(HCD_FLAG_POLL_RH, &hcd->flags);
+
+ /* Enable platform-specific non-PME# wakeup */
+ if (do_wakeup) {
+ if (pdev->vendor == PCI_VENDOR_ID_INTEL)
+ pci_write_config_byte(pdev, USBRES_INTEL,
+ USBPORT1EN | USBPORT2EN);
+ }
+
+done_okay:
+ clear_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
+done:
+ spin_unlock_irq(&uhci->lock);
+ return rc;
+}
+
+static int uhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
+{
+ struct uhci_hcd *uhci = hcd_to_uhci(hcd);
+
+ dev_dbg(uhci_dev(uhci), "%s\n", __func__);
+
+ /* Since we aren't in D3 any more, it's safe to set this flag
+ * even if the controller was dead.
+ */
+ set_bit(HCD_FLAG_HW_ACCESSIBLE, &hcd->flags);
+
+ spin_lock_irq(&uhci->lock);
+
+ /* Make sure resume from hibernation re-enumerates everything */
+ if (hibernated) {
+ uhci->reset_hc(uhci);
+ finish_reset(uhci);
+ }
+
+ /* The firmware may have changed the controller settings during
+ * a system wakeup. Check it and reconfigure to avoid problems.
+ */
+ else {
+ check_and_reset_hc(uhci);
+ }
+ configure_hc(uhci);
+
+ /* Tell the core if the controller had to be reset */
+ if (uhci->rh_state == UHCI_RH_RESET)
+ usb_root_hub_lost_power(hcd->self.root_hub);
+
+ spin_unlock_irq(&uhci->lock);
+
+ /* If interrupts don't work and remote wakeup is enabled then
+ * the suspended root hub needs to be polled.
+ */
+ if (!uhci->RD_enable && hcd->self.root_hub->do_remote_wakeup)
+ set_bit(HCD_FLAG_POLL_RH, &hcd->flags);
+
+ /* Does the root hub have a port wakeup pending? */
+ usb_hcd_poll_rh_status(hcd);
+ return 0;
+}
+
+#endif
+
+static const struct hc_driver uhci_driver = {
+ .description = hcd_name,
+ .product_desc = "UHCI Host Controller",
+ .hcd_priv_size = sizeof(struct uhci_hcd),
+
+ /* Generic hardware linkage */
+ .irq = uhci_irq,
+ .flags = HCD_USB11,
+
+ /* Basic lifecycle operations */
+ .reset = uhci_pci_init,
+ .start = uhci_start,
+#ifdef CONFIG_PM
+ .pci_suspend = uhci_pci_suspend,
+ .pci_resume = uhci_pci_resume,
+ .bus_suspend = uhci_rh_suspend,
+ .bus_resume = uhci_rh_resume,
+#endif
+ .stop = uhci_stop,
+
+ .urb_enqueue = uhci_urb_enqueue,
+ .urb_dequeue = uhci_urb_dequeue,
+
+ .endpoint_disable = uhci_hcd_endpoint_disable,
+ .get_frame_number = uhci_hcd_get_frame_number,
+
+ .hub_status_data = uhci_hub_status_data,
+ .hub_control = uhci_hub_control,
+};
+
+static DEFINE_PCI_DEVICE_TABLE(uhci_pci_ids) = { {
+ /* handle any USB UHCI controller */
+ PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_UHCI, ~0),
+ .driver_data = (unsigned long) &uhci_driver,
+ }, { /* end: all zeroes */ }
+};
+
+MODULE_DEVICE_TABLE(pci, uhci_pci_ids);
+
+static struct pci_driver uhci_pci_driver = {
+ .name = (char *)hcd_name,
+ .id_table = uhci_pci_ids,
+
+ .probe = usb_hcd_pci_probe,
+ .remove = usb_hcd_pci_remove,
+ .shutdown = uhci_shutdown,
+
+#ifdef CONFIG_PM_SLEEP
+ .driver = {
+ .pm = &usb_hcd_pci_pm_ops
+ },
+#endif
+};
diff --git a/drivers/usb/host/uhci-q.c b/drivers/usb/host/uhci-q.c
index af77abb..84ed28b3 100644
--- a/drivers/usb/host/uhci-q.c
+++ b/drivers/usb/host/uhci-q.c
@@ -29,12 +29,12 @@
{
if (uhci->is_stopped)
mod_timer(&uhci_to_hcd(uhci)->rh_timer, jiffies);
- uhci->term_td->status |= cpu_to_le32(TD_CTRL_IOC);
+ uhci->term_td->status |= cpu_to_hc32(uhci, TD_CTRL_IOC);
}
static inline void uhci_clear_next_interrupt(struct uhci_hcd *uhci)
{
- uhci->term_td->status &= ~cpu_to_le32(TD_CTRL_IOC);
+ uhci->term_td->status &= ~cpu_to_hc32(uhci, TD_CTRL_IOC);
}
@@ -53,7 +53,7 @@
uhci->fsbr_is_on = 1;
lqh = list_entry(uhci->skel_async_qh->node.prev,
struct uhci_qh, node);
- lqh->link = LINK_TO_QH(uhci->skel_term_qh);
+ lqh->link = LINK_TO_QH(uhci, uhci->skel_term_qh);
}
static void uhci_fsbr_off(struct uhci_hcd *uhci)
@@ -65,7 +65,7 @@
uhci->fsbr_is_on = 0;
lqh = list_entry(uhci->skel_async_qh->node.prev,
struct uhci_qh, node);
- lqh->link = UHCI_PTR_TERM;
+ lqh->link = UHCI_PTR_TERM(uhci);
}
static void uhci_add_fsbr(struct uhci_hcd *uhci, struct urb *urb)
@@ -131,12 +131,12 @@
dma_pool_free(uhci->td_pool, td, td->dma_handle);
}
-static inline void uhci_fill_td(struct uhci_td *td, u32 status,
- u32 token, u32 buffer)
+static inline void uhci_fill_td(struct uhci_hcd *uhci, struct uhci_td *td,
+ u32 status, u32 token, u32 buffer)
{
- td->status = cpu_to_le32(status);
- td->token = cpu_to_le32(token);
- td->buffer = cpu_to_le32(buffer);
+ td->status = cpu_to_hc32(uhci, status);
+ td->token = cpu_to_hc32(uhci, token);
+ td->buffer = cpu_to_hc32(uhci, buffer);
}
static void uhci_add_td_to_urbp(struct uhci_td *td, struct urb_priv *urbp)
@@ -170,11 +170,11 @@
td->link = ltd->link;
wmb();
- ltd->link = LINK_TO_TD(td);
+ ltd->link = LINK_TO_TD(uhci, td);
} else {
td->link = uhci->frame[framenum];
wmb();
- uhci->frame[framenum] = LINK_TO_TD(td);
+ uhci->frame[framenum] = LINK_TO_TD(uhci, td);
uhci->frame_cpu[framenum] = td;
}
}
@@ -198,7 +198,7 @@
ntd = list_entry(td->fl_list.next,
struct uhci_td,
fl_list);
- uhci->frame[td->frame] = LINK_TO_TD(ntd);
+ uhci->frame[td->frame] = LINK_TO_TD(uhci, ntd);
uhci->frame_cpu[td->frame] = ntd;
}
} else {
@@ -255,8 +255,8 @@
memset(qh, 0, sizeof(*qh));
qh->dma_handle = dma_handle;
- qh->element = UHCI_PTR_TERM;
- qh->link = UHCI_PTR_TERM;
+ qh->element = UHCI_PTR_TERM(uhci);
+ qh->link = UHCI_PTR_TERM(uhci);
INIT_LIST_HEAD(&qh->queue);
INIT_LIST_HEAD(&qh->node);
@@ -348,9 +348,9 @@
/* If the QH element pointer is UHCI_PTR_TERM then then currently
* executing URB has already been unlinked, so this one isn't it. */
- if (qh_element(qh) == UHCI_PTR_TERM)
+ if (qh_element(qh) == UHCI_PTR_TERM(uhci))
goto done;
- qh->element = UHCI_PTR_TERM;
+ qh->element = UHCI_PTR_TERM(uhci);
/* Control pipes don't have to worry about toggles */
if (qh->type == USB_ENDPOINT_XFER_CONTROL)
@@ -360,7 +360,7 @@
WARN_ON(list_empty(&urbp->td_list));
td = list_entry(urbp->td_list.next, struct uhci_td, list);
qh->needs_fixup = 1;
- qh->initial_toggle = uhci_toggle(td_token(td));
+ qh->initial_toggle = uhci_toggle(td_token(uhci, td));
done:
return ret;
@@ -370,7 +370,8 @@
* Fix up the data toggles for URBs in a queue, when one of them
* terminates early (short transfer, error, or dequeued).
*/
-static void uhci_fixup_toggles(struct uhci_qh *qh, int skip_first)
+static void uhci_fixup_toggles(struct uhci_hcd *uhci, struct uhci_qh *qh,
+ int skip_first)
{
struct urb_priv *urbp = NULL;
struct uhci_td *td;
@@ -384,7 +385,7 @@
/* When starting with the first URB, if the QH element pointer is
* still valid then we know the URB's toggles are okay. */
- else if (qh_element(qh) != UHCI_PTR_TERM)
+ else if (qh_element(qh) != UHCI_PTR_TERM(uhci))
toggle = 2;
/* Fix up the toggle for the URBs in the queue. Normally this
@@ -396,15 +397,15 @@
/* If the first TD has the right toggle value, we don't
* need to change any toggles in this URB */
td = list_entry(urbp->td_list.next, struct uhci_td, list);
- if (toggle > 1 || uhci_toggle(td_token(td)) == toggle) {
+ if (toggle > 1 || uhci_toggle(td_token(uhci, td)) == toggle) {
td = list_entry(urbp->td_list.prev, struct uhci_td,
list);
- toggle = uhci_toggle(td_token(td)) ^ 1;
+ toggle = uhci_toggle(td_token(uhci, td)) ^ 1;
/* Otherwise all the toggles in the URB have to be switched */
} else {
list_for_each_entry(td, &urbp->td_list, list) {
- td->token ^= cpu_to_le32(
+ td->token ^= cpu_to_hc32(uhci,
TD_TOKEN_TOGGLE);
toggle ^= 1;
}
@@ -441,7 +442,7 @@
pqh = list_entry(qh->node.prev, struct uhci_qh, node);
qh->link = pqh->link;
wmb();
- pqh->link = LINK_TO_QH(qh);
+ pqh->link = LINK_TO_QH(uhci, qh);
}
/*
@@ -451,7 +452,7 @@
static void link_async(struct uhci_hcd *uhci, struct uhci_qh *qh)
{
struct uhci_qh *pqh;
- __le32 link_to_new_qh;
+ __hc32 link_to_new_qh;
/* Find the predecessor QH for our new one and insert it in the list.
* The list of QHs is expected to be short, so linear search won't
@@ -465,7 +466,7 @@
/* Link it into the schedule */
qh->link = pqh->link;
wmb();
- link_to_new_qh = LINK_TO_QH(qh);
+ link_to_new_qh = LINK_TO_QH(uhci, qh);
pqh->link = link_to_new_qh;
/* If this is now the first FSBR QH, link the terminating skeleton
@@ -483,13 +484,13 @@
/* Set the element pointer if it isn't set already.
* This isn't needed for Isochronous queues, but it doesn't hurt. */
- if (qh_element(qh) == UHCI_PTR_TERM) {
+ if (qh_element(qh) == UHCI_PTR_TERM(uhci)) {
struct urb_priv *urbp = list_entry(qh->queue.next,
struct urb_priv, node);
struct uhci_td *td = list_entry(urbp->td_list.next,
struct uhci_td, list);
- qh->element = LINK_TO_TD(td);
+ qh->element = LINK_TO_TD(uhci, td);
}
/* Treat the queue as if it has just advanced */
@@ -533,7 +534,7 @@
static void unlink_async(struct uhci_hcd *uhci, struct uhci_qh *qh)
{
struct uhci_qh *pqh;
- __le32 link_to_next_qh = qh->link;
+ __hc32 link_to_next_qh = qh->link;
pqh = list_entry(qh->node.prev, struct uhci_qh, node);
pqh->link = link_to_next_qh;
@@ -757,8 +758,8 @@
/*
* Map status to standard result codes
*
- * <status> is (td_status(td) & 0xF60000), a.k.a.
- * uhci_status_bits(td_status(td)).
+ * <status> is (td_status(uhci, td) & 0xF60000), a.k.a.
+ * uhci_status_bits(td_status(uhci, td)).
* Note: <status> does not include the TD_CTRL_NAK bit.
* <dir_out> is True for output TDs and False for input TDs.
*/
@@ -794,7 +795,7 @@
int maxsze = le16_to_cpu(qh->hep->desc.wMaxPacketSize);
int len = urb->transfer_buffer_length;
dma_addr_t data = urb->transfer_dma;
- __le32 *plink;
+ __hc32 *plink;
struct urb_priv *urbp = urb->hcpriv;
int skel;
@@ -811,7 +812,7 @@
*/
td = qh->dummy_td;
uhci_add_td_to_urbp(td, urbp);
- uhci_fill_td(td, status, destination | uhci_explen(8),
+ uhci_fill_td(uhci, td, status, destination | uhci_explen(8),
urb->setup_dma);
plink = &td->link;
status |= TD_CTRL_ACTIVE;
@@ -844,14 +845,14 @@
td = uhci_alloc_td(uhci);
if (!td)
goto nomem;
- *plink = LINK_TO_TD(td);
+ *plink = LINK_TO_TD(uhci, td);
/* Alternate Data0/1 (start with Data1) */
destination ^= TD_TOKEN_TOGGLE;
uhci_add_td_to_urbp(td, urbp);
- uhci_fill_td(td, status, destination | uhci_explen(pktsze),
- data);
+ uhci_fill_td(uhci, td, status,
+ destination | uhci_explen(pktsze), data);
plink = &td->link;
data += pktsze;
@@ -864,14 +865,14 @@
td = uhci_alloc_td(uhci);
if (!td)
goto nomem;
- *plink = LINK_TO_TD(td);
+ *plink = LINK_TO_TD(uhci, td);
/* Change direction for the status transaction */
destination ^= (USB_PID_IN ^ USB_PID_OUT);
destination |= TD_TOKEN_TOGGLE; /* End in Data1 */
uhci_add_td_to_urbp(td, urbp);
- uhci_fill_td(td, status | TD_CTRL_IOC,
+ uhci_fill_td(uhci, td, status | TD_CTRL_IOC,
destination | uhci_explen(0), 0);
plink = &td->link;
@@ -881,11 +882,11 @@
td = uhci_alloc_td(uhci);
if (!td)
goto nomem;
- *plink = LINK_TO_TD(td);
+ *plink = LINK_TO_TD(uhci, td);
- uhci_fill_td(td, 0, USB_PID_OUT | uhci_explen(0), 0);
+ uhci_fill_td(uhci, td, 0, USB_PID_OUT | uhci_explen(0), 0);
wmb();
- qh->dummy_td->status |= cpu_to_le32(TD_CTRL_ACTIVE);
+ qh->dummy_td->status |= cpu_to_hc32(uhci, TD_CTRL_ACTIVE);
qh->dummy_td = td;
/* Low-speed transfers get a different queue, and won't hog the bus.
@@ -921,7 +922,7 @@
int len = urb->transfer_buffer_length;
int this_sg_len;
dma_addr_t data;
- __le32 *plink;
+ __hc32 *plink;
struct urb_priv *urbp = urb->hcpriv;
unsigned int toggle;
struct scatterlist *sg;
@@ -974,10 +975,10 @@
td = uhci_alloc_td(uhci);
if (!td)
goto nomem;
- *plink = LINK_TO_TD(td);
+ *plink = LINK_TO_TD(uhci, td);
}
uhci_add_td_to_urbp(td, urbp);
- uhci_fill_td(td, status,
+ uhci_fill_td(uhci, td, status,
destination | uhci_explen(pktsze) |
(toggle << TD_TOKEN_TOGGLE_SHIFT),
data);
@@ -1010,10 +1011,10 @@
td = uhci_alloc_td(uhci);
if (!td)
goto nomem;
- *plink = LINK_TO_TD(td);
+ *plink = LINK_TO_TD(uhci, td);
uhci_add_td_to_urbp(td, urbp);
- uhci_fill_td(td, status,
+ uhci_fill_td(uhci, td, status,
destination | uhci_explen(0) |
(toggle << TD_TOKEN_TOGGLE_SHIFT),
data);
@@ -1028,7 +1029,7 @@
* fast side but not enough to justify delaying an interrupt
* more than 2 or 3 URBs, so we will ignore the URB_NO_INTERRUPT
* flag setting. */
- td->status |= cpu_to_le32(TD_CTRL_IOC);
+ td->status |= cpu_to_hc32(uhci, TD_CTRL_IOC);
/*
* Build the new dummy TD and activate the old one
@@ -1036,11 +1037,11 @@
td = uhci_alloc_td(uhci);
if (!td)
goto nomem;
- *plink = LINK_TO_TD(td);
+ *plink = LINK_TO_TD(uhci, td);
- uhci_fill_td(td, 0, USB_PID_OUT | uhci_explen(0), 0);
+ uhci_fill_td(uhci, td, 0, USB_PID_OUT | uhci_explen(0), 0);
wmb();
- qh->dummy_td->status |= cpu_to_le32(TD_CTRL_ACTIVE);
+ qh->dummy_td->status |= cpu_to_hc32(uhci, TD_CTRL_ACTIVE);
qh->dummy_td = td;
usb_settoggle(urb->dev, usb_pipeendpoint(urb->pipe),
@@ -1133,7 +1134,7 @@
* the queue at the status stage transaction, which is
* the last TD. */
WARN_ON(list_empty(&urbp->td_list));
- qh->element = LINK_TO_TD(td);
+ qh->element = LINK_TO_TD(uhci, td);
tmp = td->list.prev;
ret = -EINPROGRESS;
@@ -1142,8 +1143,9 @@
/* When a bulk/interrupt transfer is short, we have to
* fix up the toggles of the following URBs on the queue
* before restarting the queue at the next URB. */
- qh->initial_toggle = uhci_toggle(td_token(qh->post_td)) ^ 1;
- uhci_fixup_toggles(qh, 1);
+ qh->initial_toggle =
+ uhci_toggle(td_token(uhci, qh->post_td)) ^ 1;
+ uhci_fixup_toggles(uhci, qh, 1);
if (list_empty(&urbp->td_list))
td = qh->post_td;
@@ -1178,7 +1180,7 @@
unsigned int ctrlstat;
int len;
- ctrlstat = td_status(td);
+ ctrlstat = td_status(uhci, td);
status = uhci_status_bits(ctrlstat);
if (status & TD_CTRL_ACTIVE)
return -EINPROGRESS;
@@ -1188,7 +1190,7 @@
if (status) {
ret = uhci_map_status(status,
- uhci_packetout(td_token(td)));
+ uhci_packetout(td_token(uhci, td)));
if ((debug == 1 && ret != -EPIPE) || debug > 1) {
/* Some debugging code */
dev_dbg(&urb->dev->dev,
@@ -1204,7 +1206,7 @@
}
/* Did we receive a short packet? */
- } else if (len < uhci_expected_length(td_token(td))) {
+ } else if (len < uhci_expected_length(td_token(uhci, td))) {
/* For control transfers, go to the status TD if
* this isn't already the last data TD */
@@ -1236,10 +1238,10 @@
if (ret < 0) {
/* Note that the queue has stopped and save
* the next toggle value */
- qh->element = UHCI_PTR_TERM;
+ qh->element = UHCI_PTR_TERM(uhci);
qh->is_stopped = 1;
qh->needs_fixup = (qh->type != USB_ENDPOINT_XFER_CONTROL);
- qh->initial_toggle = uhci_toggle(td_token(td)) ^
+ qh->initial_toggle = uhci_toggle(td_token(uhci, td)) ^
(ret == -EREMOTEIO);
} else /* Short packet received */
@@ -1335,14 +1337,14 @@
return -ENOMEM;
uhci_add_td_to_urbp(td, urbp);
- uhci_fill_td(td, status, destination |
+ uhci_fill_td(uhci, td, status, destination |
uhci_explen(urb->iso_frame_desc[i].length),
urb->transfer_dma +
urb->iso_frame_desc[i].offset);
}
/* Set the interrupt-on-completion flag on the last packet. */
- td->status |= cpu_to_le32(TD_CTRL_IOC);
+ td->status |= cpu_to_hc32(uhci, TD_CTRL_IOC);
/* Add the TDs to the frame list */
frame = urb->start_frame;
@@ -1378,7 +1380,7 @@
uhci_remove_tds_from_frame(uhci, qh->iso_frame);
- ctrlstat = td_status(td);
+ ctrlstat = td_status(uhci, td);
if (ctrlstat & TD_CTRL_ACTIVE) {
status = -EXDEV; /* TD was added too late? */
} else {
@@ -1629,7 +1631,7 @@
* queue, the QH can now be re-activated. */
if (!list_empty(&qh->queue)) {
if (qh->needs_fixup)
- uhci_fixup_toggles(qh, 0);
+ uhci_fixup_toggles(uhci, qh, 0);
/* If the first URB on the queue wants FSBR but its time
* limit has expired, set the next TD to interrupt on
@@ -1639,7 +1641,7 @@
struct uhci_td *td = list_entry(urbp->td_list.next,
struct uhci_td, list);
- td->status |= __cpu_to_le32(TD_CTRL_IOC);
+ td->status |= cpu_to_hc32(uhci, TD_CTRL_IOC);
}
uhci_activate_qh(uhci, qh);
@@ -1686,7 +1688,7 @@
} else {
urbp = list_entry(qh->queue.next, struct urb_priv, node);
td = list_entry(urbp->td_list.next, struct uhci_td, list);
- status = td_status(td);
+ status = td_status(uhci, td);
if (!(status & TD_CTRL_ACTIVE)) {
/* We're okay, the queue has advanced */
@@ -1704,7 +1706,8 @@
if (time_after(jiffies, qh->advance_jiffies + QH_WAIT_TIMEOUT)) {
/* Detect the Intel bug and work around it */
- if (qh->post_td && qh_element(qh) == LINK_TO_TD(qh->post_td)) {
+ if (qh->post_td && qh_element(qh) ==
+ LINK_TO_TD(uhci, qh->post_td)) {
qh->element = qh->post_td->link;
qh->advance_jiffies = jiffies;
ret = 1;
diff --git a/drivers/usb/host/xhci-dbg.c b/drivers/usb/host/xhci-dbg.c
index 0231814..2e04861 100644
--- a/drivers/usb/host/xhci-dbg.c
+++ b/drivers/usb/host/xhci-dbg.c
@@ -147,7 +147,7 @@
static void xhci_print_ports(struct xhci_hcd *xhci)
{
- u32 __iomem *addr;
+ __le32 __iomem *addr;
int i, j;
int ports;
char *names[NUM_PORT_REGS] = {
@@ -253,27 +253,27 @@
void xhci_debug_trb(struct xhci_hcd *xhci, union xhci_trb *trb)
{
u64 address;
- u32 type = xhci_readl(xhci, &trb->link.control) & TRB_TYPE_BITMASK;
+ u32 type = le32_to_cpu(trb->link.control) & TRB_TYPE_BITMASK;
switch (type) {
case TRB_TYPE(TRB_LINK):
xhci_dbg(xhci, "Link TRB:\n");
xhci_print_trb_offsets(xhci, trb);
- address = trb->link.segment_ptr;
+ address = le64_to_cpu(trb->link.segment_ptr);
xhci_dbg(xhci, "Next ring segment DMA address = 0x%llx\n", address);
xhci_dbg(xhci, "Interrupter target = 0x%x\n",
- GET_INTR_TARGET(trb->link.intr_target));
+ GET_INTR_TARGET(le32_to_cpu(trb->link.intr_target)));
xhci_dbg(xhci, "Cycle bit = %u\n",
- (unsigned int) (trb->link.control & TRB_CYCLE));
+ (unsigned int) (le32_to_cpu(trb->link.control) & TRB_CYCLE));
xhci_dbg(xhci, "Toggle cycle bit = %u\n",
- (unsigned int) (trb->link.control & LINK_TOGGLE));
+ (unsigned int) (le32_to_cpu(trb->link.control) & LINK_TOGGLE));
xhci_dbg(xhci, "No Snoop bit = %u\n",
- (unsigned int) (trb->link.control & TRB_NO_SNOOP));
+ (unsigned int) (le32_to_cpu(trb->link.control) & TRB_NO_SNOOP));
break;
case TRB_TYPE(TRB_TRANSFER):
- address = trb->trans_event.buffer;
+ address = le64_to_cpu(trb->trans_event.buffer);
/*
* FIXME: look at flags to figure out if it's an address or if
* the data is directly in the buffer field.
@@ -281,11 +281,12 @@
xhci_dbg(xhci, "DMA address or buffer contents= %llu\n", address);
break;
case TRB_TYPE(TRB_COMPLETION):
- address = trb->event_cmd.cmd_trb;
+ address = le64_to_cpu(trb->event_cmd.cmd_trb);
xhci_dbg(xhci, "Command TRB pointer = %llu\n", address);
xhci_dbg(xhci, "Completion status = %u\n",
- (unsigned int) GET_COMP_CODE(trb->event_cmd.status));
- xhci_dbg(xhci, "Flags = 0x%x\n", (unsigned int) trb->event_cmd.flags);
+ (unsigned int) GET_COMP_CODE(le32_to_cpu(trb->event_cmd.status)));
+ xhci_dbg(xhci, "Flags = 0x%x\n",
+ (unsigned int) le32_to_cpu(trb->event_cmd.flags));
break;
default:
xhci_dbg(xhci, "Unknown TRB with TRB type ID %u\n",
@@ -311,16 +312,16 @@
void xhci_debug_segment(struct xhci_hcd *xhci, struct xhci_segment *seg)
{
int i;
- u32 addr = (u32) seg->dma;
+ u64 addr = seg->dma;
union xhci_trb *trb = seg->trbs;
for (i = 0; i < TRBS_PER_SEGMENT; ++i) {
trb = &seg->trbs[i];
- xhci_dbg(xhci, "@%08x %08x %08x %08x %08x\n", addr,
- lower_32_bits(trb->link.segment_ptr),
- upper_32_bits(trb->link.segment_ptr),
- (unsigned int) trb->link.intr_target,
- (unsigned int) trb->link.control);
+ xhci_dbg(xhci, "@%016llx %08x %08x %08x %08x\n", addr,
+ (u32)lower_32_bits(le64_to_cpu(trb->link.segment_ptr)),
+ (u32)upper_32_bits(le64_to_cpu(trb->link.segment_ptr)),
+ (unsigned int) le32_to_cpu(trb->link.intr_target),
+ (unsigned int) le32_to_cpu(trb->link.control));
addr += sizeof(*trb);
}
}
@@ -391,18 +392,18 @@
void xhci_dbg_erst(struct xhci_hcd *xhci, struct xhci_erst *erst)
{
- u32 addr = (u32) erst->erst_dma_addr;
+ u64 addr = erst->erst_dma_addr;
int i;
struct xhci_erst_entry *entry;
for (i = 0; i < erst->num_entries; ++i) {
entry = &erst->entries[i];
- xhci_dbg(xhci, "@%08x %08x %08x %08x %08x\n",
- (unsigned int) addr,
- lower_32_bits(entry->seg_addr),
- upper_32_bits(entry->seg_addr),
- (unsigned int) entry->seg_size,
- (unsigned int) entry->rsvd);
+ xhci_dbg(xhci, "@%016llx %08x %08x %08x %08x\n",
+ addr,
+ lower_32_bits(le64_to_cpu(entry->seg_addr)),
+ upper_32_bits(le64_to_cpu(entry->seg_addr)),
+ (unsigned int) le32_to_cpu(entry->seg_size),
+ (unsigned int) le32_to_cpu(entry->rsvd));
addr += sizeof(*entry);
}
}
@@ -436,7 +437,7 @@
{
struct xhci_slot_ctx *slot_ctx = xhci_get_slot_ctx(xhci, ctx);
- switch (GET_SLOT_STATE(slot_ctx->dev_state)) {
+ switch (GET_SLOT_STATE(le32_to_cpu(slot_ctx->dev_state))) {
case 0:
return "enabled/disabled";
case 1:
diff --git a/drivers/usb/host/xhci-hub.c b/drivers/usb/host/xhci-hub.c
index 73f75d2..0be788c 100644
--- a/drivers/usb/host/xhci-hub.c
+++ b/drivers/usb/host/xhci-hub.c
@@ -50,7 +50,7 @@
temp |= 0x0008;
/* Bits 6:5 - no TTs in root ports */
/* Bit 7 - no port indicators */
- desc->wHubCharacteristics = (__force __u16) cpu_to_le16(temp);
+ desc->wHubCharacteristics = cpu_to_le16(temp);
}
/* Fill in the USB 2.0 roothub descriptor */
@@ -314,7 +314,7 @@
}
static void xhci_disable_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
- u16 wIndex, u32 __iomem *addr, u32 port_status)
+ u16 wIndex, __le32 __iomem *addr, u32 port_status)
{
/* Don't allow the USB core to disable SuperSpeed ports. */
if (hcd->speed == HCD_USB3) {
@@ -331,7 +331,7 @@
}
static void xhci_clear_port_change_bit(struct xhci_hcd *xhci, u16 wValue,
- u16 wIndex, u32 __iomem *addr, u32 port_status)
+ u16 wIndex, __le32 __iomem *addr, u32 port_status)
{
char *port_change_bit;
u32 status;
@@ -341,6 +341,10 @@
status = PORT_RC;
port_change_bit = "reset";
break;
+ case USB_PORT_FEAT_C_BH_PORT_RESET:
+ status = PORT_WRC;
+ port_change_bit = "warm(BH) reset";
+ break;
case USB_PORT_FEAT_C_CONNECTION:
status = PORT_CSC;
port_change_bit = "connect";
@@ -357,6 +361,10 @@
status = PORT_PLC;
port_change_bit = "suspend/resume";
break;
+ case USB_PORT_FEAT_C_PORT_LINK_STATE:
+ status = PORT_PLC;
+ port_change_bit = "link state";
+ break;
default:
/* Should never happen */
return;
@@ -368,25 +376,36 @@
port_change_bit, wIndex, port_status);
}
+static int xhci_get_ports(struct usb_hcd *hcd, __le32 __iomem ***port_array)
+{
+ int max_ports;
+ struct xhci_hcd *xhci = hcd_to_xhci(hcd);
+
+ if (hcd->speed == HCD_USB3) {
+ max_ports = xhci->num_usb3_ports;
+ *port_array = xhci->usb3_ports;
+ } else {
+ max_ports = xhci->num_usb2_ports;
+ *port_array = xhci->usb2_ports;
+ }
+
+ return max_ports;
+}
+
int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue,
u16 wIndex, char *buf, u16 wLength)
{
struct xhci_hcd *xhci = hcd_to_xhci(hcd);
- int ports;
+ int max_ports;
unsigned long flags;
u32 temp, temp1, status;
int retval = 0;
- u32 __iomem **port_array;
+ __le32 __iomem **port_array;
int slot_id;
struct xhci_bus_state *bus_state;
+ u16 link_state = 0;
- if (hcd->speed == HCD_USB3) {
- ports = xhci->num_usb3_ports;
- port_array = xhci->usb3_ports;
- } else {
- ports = xhci->num_usb2_ports;
- port_array = xhci->usb2_ports;
- }
+ max_ports = xhci_get_ports(hcd, &port_array);
bus_state = &xhci->bus_state[hcd_index(hcd)];
spin_lock_irqsave(&xhci->lock, flags);
@@ -411,7 +430,7 @@
(struct usb_hub_descriptor *) buf);
break;
case GetPortStatus:
- if (!wIndex || wIndex > ports)
+ if (!wIndex || wIndex > max_ports)
goto error;
wIndex--;
status = 0;
@@ -422,9 +441,6 @@
}
xhci_dbg(xhci, "get port status, actual port %d status = 0x%x\n", wIndex, temp);
- /* FIXME - should we return a port status value like the USB
- * 3.0 external hubs do?
- */
/* wPortChange bits */
if (temp & PORT_CSC)
status |= USB_PORT_STAT_C_CONNECTION << 16;
@@ -432,13 +448,21 @@
status |= USB_PORT_STAT_C_ENABLE << 16;
if ((temp & PORT_OCC))
status |= USB_PORT_STAT_C_OVERCURRENT << 16;
- /*
- * FIXME ignoring reset and USB 2.1/3.0 specific
- * changes
- */
- if ((temp & PORT_PLS_MASK) == XDEV_U3
- && (temp & PORT_POWER))
- status |= 1 << USB_PORT_FEAT_SUSPEND;
+ if ((temp & PORT_RC))
+ status |= USB_PORT_STAT_C_RESET << 16;
+ /* USB3.0 only */
+ if (hcd->speed == HCD_USB3) {
+ if ((temp & PORT_PLC))
+ status |= USB_PORT_STAT_C_LINK_STATE << 16;
+ if ((temp & PORT_WRC))
+ status |= USB_PORT_STAT_C_BH_RESET << 16;
+ }
+
+ if (hcd->speed != HCD_USB3) {
+ if ((temp & PORT_PLS_MASK) == XDEV_U3
+ && (temp & PORT_POWER))
+ status |= USB_PORT_STAT_SUSPEND;
+ }
if ((temp & PORT_PLS_MASK) == XDEV_RESUME) {
if ((temp & PORT_RESET) || !(temp & PORT_PE))
goto error;
@@ -469,7 +493,8 @@
&& (temp & PORT_POWER)
&& (bus_state->suspended_ports & (1 << wIndex))) {
bus_state->suspended_ports &= ~(1 << wIndex);
- bus_state->port_c_suspend |= 1 << wIndex;
+ if (hcd->speed != HCD_USB3)
+ bus_state->port_c_suspend |= 1 << wIndex;
}
if (temp & PORT_CONNECT) {
status |= USB_PORT_STAT_CONNECTION;
@@ -481,16 +506,30 @@
status |= USB_PORT_STAT_OVERCURRENT;
if (temp & PORT_RESET)
status |= USB_PORT_STAT_RESET;
- if (temp & PORT_POWER)
- status |= USB_PORT_STAT_POWER;
+ if (temp & PORT_POWER) {
+ if (hcd->speed == HCD_USB3)
+ status |= USB_SS_PORT_STAT_POWER;
+ else
+ status |= USB_PORT_STAT_POWER;
+ }
+ /* Port Link State */
+ if (hcd->speed == HCD_USB3) {
+ /* resume state is a xHCI internal state.
+ * Do not report it to usb core.
+ */
+ if ((temp & PORT_PLS_MASK) != XDEV_RESUME)
+ status |= (temp & PORT_PLS_MASK);
+ }
if (bus_state->port_c_suspend & (1 << wIndex))
status |= 1 << USB_PORT_FEAT_C_SUSPEND;
xhci_dbg(xhci, "Get port status returned 0x%x\n", status);
put_unaligned(cpu_to_le32(status), (__le32 *) buf);
break;
case SetPortFeature:
+ if (wValue == USB_PORT_FEAT_LINK_STATE)
+ link_state = (wIndex & 0xff00) >> 3;
wIndex &= 0xff;
- if (!wIndex || wIndex > ports)
+ if (!wIndex || wIndex > max_ports)
goto error;
wIndex--;
temp = xhci_readl(xhci, port_array[wIndex]);
@@ -537,6 +576,44 @@
temp = xhci_readl(xhci, port_array[wIndex]);
bus_state->suspended_ports |= 1 << wIndex;
break;
+ case USB_PORT_FEAT_LINK_STATE:
+ temp = xhci_readl(xhci, port_array[wIndex]);
+ /* Software should not attempt to set
+ * port link state above '5' (Rx.Detect) and the port
+ * must be enabled.
+ */
+ if ((temp & PORT_PE) == 0 ||
+ (link_state > USB_SS_PORT_LS_RX_DETECT)) {
+ xhci_warn(xhci, "Cannot set link state.\n");
+ goto error;
+ }
+
+ if (link_state == USB_SS_PORT_LS_U3) {
+ slot_id = xhci_find_slot_id_by_port(hcd, xhci,
+ wIndex + 1);
+ if (slot_id) {
+ /* unlock to execute stop endpoint
+ * commands */
+ spin_unlock_irqrestore(&xhci->lock,
+ flags);
+ xhci_stop_device(xhci, slot_id, 1);
+ spin_lock_irqsave(&xhci->lock, flags);
+ }
+ }
+
+ temp = xhci_port_state_to_neutral(temp);
+ temp &= ~PORT_PLS_MASK;
+ temp |= PORT_LINK_STROBE | link_state;
+ xhci_writel(xhci, temp, port_array[wIndex]);
+
+ spin_unlock_irqrestore(&xhci->lock, flags);
+ msleep(20); /* wait device to enter */
+ spin_lock_irqsave(&xhci->lock, flags);
+
+ temp = xhci_readl(xhci, port_array[wIndex]);
+ if (link_state == USB_SS_PORT_LS_U3)
+ bus_state->suspended_ports |= 1 << wIndex;
+ break;
case USB_PORT_FEAT_POWER:
/*
* Turn on ports, even if there isn't per-port switching.
@@ -557,6 +634,12 @@
temp = xhci_readl(xhci, port_array[wIndex]);
xhci_dbg(xhci, "set port reset, actual port %d status = 0x%x\n", wIndex, temp);
break;
+ case USB_PORT_FEAT_BH_PORT_RESET:
+ temp |= PORT_WR;
+ xhci_writel(xhci, temp, port_array[wIndex]);
+
+ temp = xhci_readl(xhci, port_array[wIndex]);
+ break;
default:
goto error;
}
@@ -564,7 +647,7 @@
temp = xhci_readl(xhci, port_array[wIndex]);
break;
case ClearPortFeature:
- if (!wIndex || wIndex > ports)
+ if (!wIndex || wIndex > max_ports)
goto error;
wIndex--;
temp = xhci_readl(xhci, port_array[wIndex]);
@@ -584,35 +667,27 @@
if (temp & XDEV_U3) {
if ((temp & PORT_PE) == 0)
goto error;
- if (DEV_SUPERSPEED(temp)) {
- temp = xhci_port_state_to_neutral(temp);
- temp &= ~PORT_PLS_MASK;
- temp |= PORT_LINK_STROBE | XDEV_U0;
- xhci_writel(xhci, temp,
- port_array[wIndex]);
- xhci_readl(xhci, port_array[wIndex]);
- } else {
- temp = xhci_port_state_to_neutral(temp);
- temp &= ~PORT_PLS_MASK;
- temp |= PORT_LINK_STROBE | XDEV_RESUME;
- xhci_writel(xhci, temp,
- port_array[wIndex]);
- spin_unlock_irqrestore(&xhci->lock,
- flags);
- msleep(20);
- spin_lock_irqsave(&xhci->lock, flags);
+ temp = xhci_port_state_to_neutral(temp);
+ temp &= ~PORT_PLS_MASK;
+ temp |= PORT_LINK_STROBE | XDEV_RESUME;
+ xhci_writel(xhci, temp,
+ port_array[wIndex]);
- temp = xhci_readl(xhci,
- port_array[wIndex]);
- temp = xhci_port_state_to_neutral(temp);
- temp &= ~PORT_PLS_MASK;
- temp |= PORT_LINK_STROBE | XDEV_U0;
- xhci_writel(xhci, temp,
- port_array[wIndex]);
- }
- bus_state->port_c_suspend |= 1 << wIndex;
+ spin_unlock_irqrestore(&xhci->lock,
+ flags);
+ msleep(20);
+ spin_lock_irqsave(&xhci->lock, flags);
+
+ temp = xhci_readl(xhci,
+ port_array[wIndex]);
+ temp = xhci_port_state_to_neutral(temp);
+ temp &= ~PORT_PLS_MASK;
+ temp |= PORT_LINK_STROBE | XDEV_U0;
+ xhci_writel(xhci, temp,
+ port_array[wIndex]);
}
+ bus_state->port_c_suspend |= 1 << wIndex;
slot_id = xhci_find_slot_id_by_port(hcd, xhci,
wIndex + 1);
@@ -625,9 +700,11 @@
case USB_PORT_FEAT_C_SUSPEND:
bus_state->port_c_suspend &= ~(1 << wIndex);
case USB_PORT_FEAT_C_RESET:
+ case USB_PORT_FEAT_C_BH_PORT_RESET:
case USB_PORT_FEAT_C_CONNECTION:
case USB_PORT_FEAT_C_OVER_CURRENT:
case USB_PORT_FEAT_C_ENABLE:
+ case USB_PORT_FEAT_C_PORT_LINK_STATE:
xhci_clear_port_change_bit(xhci, wValue, wIndex,
port_array[wIndex], temp);
break;
@@ -663,29 +740,23 @@
u32 mask;
int i, retval;
struct xhci_hcd *xhci = hcd_to_xhci(hcd);
- int ports;
- u32 __iomem **port_array;
+ int max_ports;
+ __le32 __iomem **port_array;
struct xhci_bus_state *bus_state;
- if (hcd->speed == HCD_USB3) {
- ports = xhci->num_usb3_ports;
- port_array = xhci->usb3_ports;
- } else {
- ports = xhci->num_usb2_ports;
- port_array = xhci->usb2_ports;
- }
+ max_ports = xhci_get_ports(hcd, &port_array);
bus_state = &xhci->bus_state[hcd_index(hcd)];
/* Initial status is no changes */
- retval = (ports + 8) / 8;
+ retval = (max_ports + 8) / 8;
memset(buf, 0, retval);
status = 0;
- mask = PORT_CSC | PORT_PEC | PORT_OCC;
+ mask = PORT_CSC | PORT_PEC | PORT_OCC | PORT_PLC;
spin_lock_irqsave(&xhci->lock, flags);
/* For each port, did anything change? If so, set that bit in buf. */
- for (i = 0; i < ports; i++) {
+ for (i = 0; i < max_ports; i++) {
temp = xhci_readl(xhci, port_array[i]);
if (temp == 0xffffffff) {
retval = -ENODEV;
@@ -709,19 +780,11 @@
{
struct xhci_hcd *xhci = hcd_to_xhci(hcd);
int max_ports, port_index;
- u32 __iomem **port_array;
+ __le32 __iomem **port_array;
struct xhci_bus_state *bus_state;
unsigned long flags;
- if (hcd->speed == HCD_USB3) {
- max_ports = xhci->num_usb3_ports;
- port_array = xhci->usb3_ports;
- xhci_dbg(xhci, "suspend USB 3.0 root hub\n");
- } else {
- max_ports = xhci->num_usb2_ports;
- port_array = xhci->usb2_ports;
- xhci_dbg(xhci, "suspend USB 2.0 root hub\n");
- }
+ max_ports = xhci_get_ports(hcd, &port_array);
bus_state = &xhci->bus_state[hcd_index(hcd)];
spin_lock_irqsave(&xhci->lock, flags);
@@ -779,7 +842,7 @@
if (hcd->speed != HCD_USB3) {
/* enable remote wake up for USB 2.0 */
- u32 __iomem *addr;
+ __le32 __iomem *addr;
u32 tmp;
/* Add one to the port status register address to get
@@ -801,20 +864,12 @@
{
struct xhci_hcd *xhci = hcd_to_xhci(hcd);
int max_ports, port_index;
- u32 __iomem **port_array;
+ __le32 __iomem **port_array;
struct xhci_bus_state *bus_state;
u32 temp;
unsigned long flags;
- if (hcd->speed == HCD_USB3) {
- max_ports = xhci->num_usb3_ports;
- port_array = xhci->usb3_ports;
- xhci_dbg(xhci, "resume USB 3.0 root hub\n");
- } else {
- max_ports = xhci->num_usb2_ports;
- port_array = xhci->usb2_ports;
- xhci_dbg(xhci, "resume USB 2.0 root hub\n");
- }
+ max_ports = xhci_get_ports(hcd, &port_array);
bus_state = &xhci->bus_state[hcd_index(hcd)];
if (time_before(jiffies, bus_state->next_statechange))
@@ -890,7 +945,7 @@
if (hcd->speed != HCD_USB3) {
/* disable remote wake up for USB 2.0 */
- u32 __iomem *addr;
+ __le32 __iomem *addr;
u32 tmp;
/* Add one to the port status register address to get
diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
index 627f343..26caba4 100644
--- a/drivers/usb/host/xhci-mem.c
+++ b/drivers/usb/host/xhci-mem.c
@@ -89,16 +89,17 @@
return;
prev->next = next;
if (link_trbs) {
- prev->trbs[TRBS_PER_SEGMENT-1].link.segment_ptr = next->dma;
+ prev->trbs[TRBS_PER_SEGMENT-1].link.
+ segment_ptr = cpu_to_le64(next->dma);
/* Set the last TRB in the segment to have a TRB type ID of Link TRB */
- val = prev->trbs[TRBS_PER_SEGMENT-1].link.control;
+ val = le32_to_cpu(prev->trbs[TRBS_PER_SEGMENT-1].link.control);
val &= ~TRB_TYPE_BITMASK;
val |= TRB_TYPE(TRB_LINK);
/* Always set the chain bit with 0.95 hardware */
if (xhci_link_trb_quirk(xhci))
val |= TRB_CHAIN;
- prev->trbs[TRBS_PER_SEGMENT-1].link.control = val;
+ prev->trbs[TRBS_PER_SEGMENT-1].link.control = cpu_to_le32(val);
}
xhci_dbg(xhci, "Linking segment 0x%llx to segment 0x%llx (DMA)\n",
(unsigned long long)prev->dma,
@@ -186,7 +187,8 @@
if (link_trbs) {
/* See section 4.9.2.1 and 6.4.4.1 */
- prev->trbs[TRBS_PER_SEGMENT-1].link.control |= (LINK_TOGGLE);
+ prev->trbs[TRBS_PER_SEGMENT-1].link.
+ control |= cpu_to_le32(LINK_TOGGLE);
xhci_dbg(xhci, "Wrote link toggle flag to"
" segment %p (virtual), 0x%llx (DMA)\n",
prev, (unsigned long long)prev->dma);
@@ -207,14 +209,13 @@
rings_cached = virt_dev->num_rings_cached;
if (rings_cached < XHCI_MAX_RINGS_CACHED) {
- virt_dev->num_rings_cached++;
- rings_cached = virt_dev->num_rings_cached;
virt_dev->ring_cache[rings_cached] =
virt_dev->eps[ep_index].ring;
+ virt_dev->num_rings_cached++;
xhci_dbg(xhci, "Cached old ring, "
"%d ring%s cached\n",
- rings_cached,
- (rings_cached > 1) ? "s" : "");
+ virt_dev->num_rings_cached,
+ (virt_dev->num_rings_cached > 1) ? "s" : "");
} else {
xhci_ring_free(xhci, virt_dev->eps[ep_index].ring);
xhci_dbg(xhci, "Ring cache full (%d rings), "
@@ -548,7 +549,8 @@
addr = cur_ring->first_seg->dma |
SCT_FOR_CTX(SCT_PRI_TR) |
cur_ring->cycle_state;
- stream_info->stream_ctx_array[cur_stream].stream_ring = addr;
+ stream_info->stream_ctx_array[cur_stream].
+ stream_ring = cpu_to_le64(addr);
xhci_dbg(xhci, "Setting stream %d ring ptr to 0x%08llx\n",
cur_stream, (unsigned long long) addr);
@@ -614,10 +616,10 @@
max_primary_streams = fls(stream_info->num_stream_ctxs) - 2;
xhci_dbg(xhci, "Setting number of stream ctx array entries to %u\n",
1 << (max_primary_streams + 1));
- ep_ctx->ep_info &= ~EP_MAXPSTREAMS_MASK;
- ep_ctx->ep_info |= EP_MAXPSTREAMS(max_primary_streams);
- ep_ctx->ep_info |= EP_HAS_LSA;
- ep_ctx->deq = stream_info->ctx_array_dma;
+ ep_ctx->ep_info &= cpu_to_le32(~EP_MAXPSTREAMS_MASK);
+ ep_ctx->ep_info |= cpu_to_le32(EP_MAXPSTREAMS(max_primary_streams)
+ | EP_HAS_LSA);
+ ep_ctx->deq = cpu_to_le64(stream_info->ctx_array_dma);
}
/*
@@ -630,10 +632,9 @@
struct xhci_virt_ep *ep)
{
dma_addr_t addr;
- ep_ctx->ep_info &= ~EP_MAXPSTREAMS_MASK;
- ep_ctx->ep_info &= ~EP_HAS_LSA;
+ ep_ctx->ep_info &= cpu_to_le32(~(EP_MAXPSTREAMS_MASK | EP_HAS_LSA));
addr = xhci_trb_virt_to_dma(ep->ring->deq_seg, ep->ring->dequeue);
- ep_ctx->deq = addr | ep->ring->cycle_state;
+ ep_ctx->deq = cpu_to_le64(addr | ep->ring->cycle_state);
}
/* Frees all stream contexts associated with the endpoint,
@@ -781,11 +782,11 @@
dev->udev = udev;
/* Point to output device context in dcbaa. */
- xhci->dcbaa->dev_context_ptrs[slot_id] = dev->out_ctx->dma;
+ xhci->dcbaa->dev_context_ptrs[slot_id] = cpu_to_le64(dev->out_ctx->dma);
xhci_dbg(xhci, "Set slot id %d dcbaa entry %p to 0x%llx\n",
- slot_id,
- &xhci->dcbaa->dev_context_ptrs[slot_id],
- (unsigned long long) xhci->dcbaa->dev_context_ptrs[slot_id]);
+ slot_id,
+ &xhci->dcbaa->dev_context_ptrs[slot_id],
+ (unsigned long long) le64_to_cpu(xhci->dcbaa->dev_context_ptrs[slot_id]));
return 1;
fail:
@@ -810,8 +811,9 @@
* configured device has reset, so all control transfers should have
* been completed or cancelled before the reset.
*/
- ep0_ctx->deq = xhci_trb_virt_to_dma(ep_ring->enq_seg, ep_ring->enqueue);
- ep0_ctx->deq |= ep_ring->cycle_state;
+ ep0_ctx->deq = cpu_to_le64(xhci_trb_virt_to_dma(ep_ring->enq_seg,
+ ep_ring->enqueue)
+ | ep_ring->cycle_state);
}
/*
@@ -885,24 +887,22 @@
slot_ctx = xhci_get_slot_ctx(xhci, dev->in_ctx);
/* 2) New slot context and endpoint 0 context are valid*/
- ctrl_ctx->add_flags = SLOT_FLAG | EP0_FLAG;
+ ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
/* 3) Only the control endpoint is valid - one endpoint context */
- slot_ctx->dev_info |= LAST_CTX(1);
-
- slot_ctx->dev_info |= (u32) udev->route;
+ slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1) | (u32) udev->route);
switch (udev->speed) {
case USB_SPEED_SUPER:
- slot_ctx->dev_info |= (u32) SLOT_SPEED_SS;
+ slot_ctx->dev_info |= cpu_to_le32((u32) SLOT_SPEED_SS);
break;
case USB_SPEED_HIGH:
- slot_ctx->dev_info |= (u32) SLOT_SPEED_HS;
+ slot_ctx->dev_info |= cpu_to_le32((u32) SLOT_SPEED_HS);
break;
case USB_SPEED_FULL:
- slot_ctx->dev_info |= (u32) SLOT_SPEED_FS;
+ slot_ctx->dev_info |= cpu_to_le32((u32) SLOT_SPEED_FS);
break;
case USB_SPEED_LOW:
- slot_ctx->dev_info |= (u32) SLOT_SPEED_LS;
+ slot_ctx->dev_info |= cpu_to_le32((u32) SLOT_SPEED_LS);
break;
case USB_SPEED_WIRELESS:
xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n");
@@ -916,7 +916,7 @@
port_num = xhci_find_real_port_number(xhci, udev);
if (!port_num)
return -EINVAL;
- slot_ctx->dev_info2 |= (u32) ROOT_HUB_PORT(port_num);
+ slot_ctx->dev_info2 |= cpu_to_le32((u32) ROOT_HUB_PORT(port_num));
/* Set the port number in the virtual_device to the faked port number */
for (top_dev = udev; top_dev->parent && top_dev->parent->parent;
top_dev = top_dev->parent)
@@ -927,31 +927,31 @@
/* Is this a LS/FS device under an external HS hub? */
if (udev->tt && udev->tt->hub->parent) {
- slot_ctx->tt_info = udev->tt->hub->slot_id;
- slot_ctx->tt_info |= udev->ttport << 8;
+ slot_ctx->tt_info = cpu_to_le32(udev->tt->hub->slot_id |
+ (udev->ttport << 8));
if (udev->tt->multi)
- slot_ctx->dev_info |= DEV_MTT;
+ slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
}
xhci_dbg(xhci, "udev->tt = %p\n", udev->tt);
xhci_dbg(xhci, "udev->ttport = 0x%x\n", udev->ttport);
/* Step 4 - ring already allocated */
/* Step 5 */
- ep0_ctx->ep_info2 = EP_TYPE(CTRL_EP);
+ ep0_ctx->ep_info2 = cpu_to_le32(EP_TYPE(CTRL_EP));
/*
* XXX: Not sure about wireless USB devices.
*/
switch (udev->speed) {
case USB_SPEED_SUPER:
- ep0_ctx->ep_info2 |= MAX_PACKET(512);
+ ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(512));
break;
case USB_SPEED_HIGH:
/* USB core guesses at a 64-byte max packet first for FS devices */
case USB_SPEED_FULL:
- ep0_ctx->ep_info2 |= MAX_PACKET(64);
+ ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(64));
break;
case USB_SPEED_LOW:
- ep0_ctx->ep_info2 |= MAX_PACKET(8);
+ ep0_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(8));
break;
case USB_SPEED_WIRELESS:
xhci_dbg(xhci, "FIXME xHCI doesn't support wireless speeds\n");
@@ -962,12 +962,10 @@
BUG();
}
/* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */
- ep0_ctx->ep_info2 |= MAX_BURST(0);
- ep0_ctx->ep_info2 |= ERROR_COUNT(3);
+ ep0_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(0) | ERROR_COUNT(3));
- ep0_ctx->deq =
- dev->eps[0].ring->first_seg->dma;
- ep0_ctx->deq |= dev->eps[0].ring->cycle_state;
+ ep0_ctx->deq = cpu_to_le64(dev->eps[0].ring->first_seg->dma |
+ dev->eps[0].ring->cycle_state);
/* Steps 7 and 8 were done in xhci_alloc_virt_device() */
@@ -1046,12 +1044,12 @@
break;
case USB_SPEED_FULL:
- if (usb_endpoint_xfer_int(&ep->desc)) {
+ if (usb_endpoint_xfer_isoc(&ep->desc)) {
interval = xhci_parse_exponent_interval(udev, ep);
break;
}
/*
- * Fall through for isochronous endpoint interval decoding
+ * Fall through for interrupt endpoint interval decoding
* since it uses the same rules as low speed interrupt
* endpoints.
*/
@@ -1131,10 +1129,10 @@
return 0;
if (udev->speed == USB_SPEED_SUPER)
- return ep->ss_ep_comp.wBytesPerInterval;
+ return le16_to_cpu(ep->ss_ep_comp.wBytesPerInterval);
- max_packet = GET_MAX_PACKET(ep->desc.wMaxPacketSize);
- max_burst = (ep->desc.wMaxPacketSize & 0x1800) >> 11;
+ max_packet = GET_MAX_PACKET(le16_to_cpu(ep->desc.wMaxPacketSize));
+ max_burst = (le16_to_cpu(ep->desc.wMaxPacketSize) & 0x1800) >> 11;
/* A 0 in max burst means 1 transfer per ESIT */
return max_packet * (max_burst + 1);
}
@@ -1183,33 +1181,33 @@
}
virt_dev->eps[ep_index].skip = false;
ep_ring = virt_dev->eps[ep_index].new_ring;
- ep_ctx->deq = ep_ring->first_seg->dma | ep_ring->cycle_state;
+ ep_ctx->deq = cpu_to_le64(ep_ring->first_seg->dma | ep_ring->cycle_state);
- ep_ctx->ep_info = xhci_get_endpoint_interval(udev, ep);
- ep_ctx->ep_info |= EP_MULT(xhci_get_endpoint_mult(udev, ep));
+ ep_ctx->ep_info = cpu_to_le32(xhci_get_endpoint_interval(udev, ep)
+ | EP_MULT(xhci_get_endpoint_mult(udev, ep)));
/* FIXME dig Mult and streams info out of ep companion desc */
/* Allow 3 retries for everything but isoc;
- * error count = 0 means infinite retries.
+ * CErr shall be set to 0 for Isoch endpoints.
*/
if (!usb_endpoint_xfer_isoc(&ep->desc))
- ep_ctx->ep_info2 = ERROR_COUNT(3);
+ ep_ctx->ep_info2 = cpu_to_le32(ERROR_COUNT(3));
else
- ep_ctx->ep_info2 = ERROR_COUNT(1);
+ ep_ctx->ep_info2 = cpu_to_le32(ERROR_COUNT(0));
- ep_ctx->ep_info2 |= xhci_get_endpoint_type(udev, ep);
+ ep_ctx->ep_info2 |= cpu_to_le32(xhci_get_endpoint_type(udev, ep));
/* Set the max packet size and max burst */
switch (udev->speed) {
case USB_SPEED_SUPER:
- max_packet = ep->desc.wMaxPacketSize;
- ep_ctx->ep_info2 |= MAX_PACKET(max_packet);
+ max_packet = le16_to_cpu(ep->desc.wMaxPacketSize);
+ ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet));
/* dig out max burst from ep companion desc */
max_packet = ep->ss_ep_comp.bMaxBurst;
if (!max_packet)
xhci_warn(xhci, "WARN no SS endpoint bMaxBurst\n");
- ep_ctx->ep_info2 |= MAX_BURST(max_packet);
+ ep_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(max_packet));
break;
case USB_SPEED_HIGH:
/* bits 11:12 specify the number of additional transaction
@@ -1217,20 +1215,21 @@
*/
if (usb_endpoint_xfer_isoc(&ep->desc) ||
usb_endpoint_xfer_int(&ep->desc)) {
- max_burst = (ep->desc.wMaxPacketSize & 0x1800) >> 11;
- ep_ctx->ep_info2 |= MAX_BURST(max_burst);
+ max_burst = (le16_to_cpu(ep->desc.wMaxPacketSize)
+ & 0x1800) >> 11;
+ ep_ctx->ep_info2 |= cpu_to_le32(MAX_BURST(max_burst));
}
/* Fall through */
case USB_SPEED_FULL:
case USB_SPEED_LOW:
- max_packet = GET_MAX_PACKET(ep->desc.wMaxPacketSize);
- ep_ctx->ep_info2 |= MAX_PACKET(max_packet);
+ max_packet = GET_MAX_PACKET(le16_to_cpu(ep->desc.wMaxPacketSize));
+ ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet));
break;
default:
BUG();
}
max_esit_payload = xhci_get_max_esit_payload(xhci, udev, ep);
- ep_ctx->tx_info = MAX_ESIT_PAYLOAD_FOR_EP(max_esit_payload);
+ ep_ctx->tx_info = cpu_to_le32(MAX_ESIT_PAYLOAD_FOR_EP(max_esit_payload));
/*
* XXX no idea how to calculate the average TRB buffer length for bulk
@@ -1246,8 +1245,15 @@
* including link TRBs, No-op TRBs, and Event data TRBs. Since we don't
* use Event Data TRBs, and we don't chain in a link TRB on short
* transfers, we're basically dividing by 1.
+ *
+ * xHCI 1.0 specification indicates that the Average TRB Length should
+ * be set to 8 for control endpoints.
*/
- ep_ctx->tx_info |= AVG_TRB_LENGTH_FOR_EP(max_esit_payload);
+ if (usb_endpoint_xfer_control(&ep->desc) && xhci->hci_version == 0x100)
+ ep_ctx->tx_info |= cpu_to_le32(AVG_TRB_LENGTH_FOR_EP(8));
+ else
+ ep_ctx->tx_info |=
+ cpu_to_le32(AVG_TRB_LENGTH_FOR_EP(max_esit_payload));
/* FIXME Debug endpoint context */
return 0;
@@ -1347,7 +1353,7 @@
if (!xhci->scratchpad->sp_dma_buffers)
goto fail_sp4;
- xhci->dcbaa->dev_context_ptrs[0] = xhci->scratchpad->sp_dma;
+ xhci->dcbaa->dev_context_ptrs[0] = cpu_to_le64(xhci->scratchpad->sp_dma);
for (i = 0; i < num_sp; i++) {
dma_addr_t dma;
void *buf = pci_alloc_consistent(to_pci_dev(dev),
@@ -1724,7 +1730,7 @@
}
static void xhci_add_in_port(struct xhci_hcd *xhci, unsigned int num_ports,
- u32 __iomem *addr, u8 major_revision)
+ __le32 __iomem *addr, u8 major_revision)
{
u32 temp, port_offset, port_count;
int i;
@@ -1789,7 +1795,7 @@
*/
static int xhci_setup_port_arrays(struct xhci_hcd *xhci, gfp_t flags)
{
- u32 __iomem *addr;
+ __le32 __iomem *addr;
u32 offset;
unsigned int num_ports;
int i, port_index;
@@ -2042,8 +2048,8 @@
/* set ring base address and size for each segment table entry */
for (val = 0, seg = xhci->event_ring->first_seg; val < ERST_NUM_SEGS; val++) {
struct xhci_erst_entry *entry = &xhci->erst.entries[val];
- entry->seg_addr = seg->dma;
- entry->seg_size = TRBS_PER_SEGMENT;
+ entry->seg_addr = cpu_to_le64(seg->dma);
+ entry->seg_size = cpu_to_le32(TRBS_PER_SEGMENT);
entry->rsvd = 0;
seg = seg->next;
}
diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c
index a10494c..cbc4d49 100644
--- a/drivers/usb/host/xhci-pci.c
+++ b/drivers/usb/host/xhci-pci.c
@@ -21,6 +21,7 @@
*/
#include <linux/pci.h>
+#include <linux/slab.h>
#include "xhci.h"
diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
index 7437386..237a765 100644
--- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c
@@ -100,7 +100,7 @@
return (trb == &seg->trbs[TRBS_PER_SEGMENT]) &&
(seg->next == xhci->event_ring->first_seg);
else
- return trb->link.control & LINK_TOGGLE;
+ return le32_to_cpu(trb->link.control) & LINK_TOGGLE;
}
/* Is this TRB a link TRB or was the last TRB the last TRB in this event ring
@@ -113,13 +113,15 @@
if (ring == xhci->event_ring)
return trb == &seg->trbs[TRBS_PER_SEGMENT];
else
- return (trb->link.control & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK);
+ return (le32_to_cpu(trb->link.control) & TRB_TYPE_BITMASK)
+ == TRB_TYPE(TRB_LINK);
}
static int enqueue_is_link_trb(struct xhci_ring *ring)
{
struct xhci_link_trb *link = &ring->enqueue->link;
- return ((link->control & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK));
+ return ((le32_to_cpu(link->control) & TRB_TYPE_BITMASK) ==
+ TRB_TYPE(TRB_LINK));
}
/* Updates trb to point to the next TRB in the ring, and updates seg if the next
@@ -197,7 +199,7 @@
union xhci_trb *next;
unsigned long long addr;
- chain = ring->enqueue->generic.field[3] & TRB_CHAIN;
+ chain = le32_to_cpu(ring->enqueue->generic.field[3]) & TRB_CHAIN;
next = ++(ring->enqueue);
ring->enq_updates++;
@@ -223,12 +225,14 @@
* (which may mean the chain bit is cleared).
*/
if (!xhci_link_trb_quirk(xhci)) {
- next->link.control &= ~TRB_CHAIN;
- next->link.control |= chain;
+ next->link.control &=
+ cpu_to_le32(~TRB_CHAIN);
+ next->link.control |=
+ cpu_to_le32(chain);
}
/* Give this link TRB to the hardware */
wmb();
- next->link.control ^= TRB_CYCLE;
+ next->link.control ^= cpu_to_le32(TRB_CYCLE);
}
/* Toggle the cycle bit after the last ring segment. */
if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
@@ -319,7 +323,7 @@
unsigned int ep_index,
unsigned int stream_id)
{
- __u32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
+ __le32 __iomem *db_addr = &xhci->dba->doorbell[slot_id];
struct xhci_virt_ep *ep = &xhci->devs[slot_id]->eps[ep_index];
unsigned int ep_state = ep->ep_state;
@@ -380,7 +384,7 @@
while (cur_seg->trbs > trb ||
&cur_seg->trbs[TRBS_PER_SEGMENT - 1] < trb) {
generic_trb = &cur_seg->trbs[TRBS_PER_SEGMENT - 1].generic;
- if (generic_trb->field[3] & LINK_TOGGLE)
+ if (le32_to_cpu(generic_trb->field[3]) & LINK_TOGGLE)
*cycle_state ^= 0x1;
cur_seg = cur_seg->next;
if (cur_seg == start_seg)
@@ -447,6 +451,10 @@
* any link TRBs with the toggle cycle bit set.
* - Finally we move the dequeue state one TRB further, toggling the cycle bit
* if we've moved it past a link TRB with the toggle cycle bit set.
+ *
+ * Some of the uses of xhci_generic_trb are grotty, but if they're done
+ * with correct __le32 accesses they should work fine. Only users of this are
+ * in here.
*/
void xhci_find_new_dequeue_state(struct xhci_hcd *xhci,
unsigned int slot_id, unsigned int ep_index,
@@ -480,7 +488,7 @@
/* Dig out the cycle state saved by the xHC during the stop ep cmd */
xhci_dbg(xhci, "Finding endpoint context\n");
ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
- state->new_cycle_state = 0x1 & ep_ctx->deq;
+ state->new_cycle_state = 0x1 & le64_to_cpu(ep_ctx->deq);
state->new_deq_ptr = cur_td->last_trb;
xhci_dbg(xhci, "Finding segment containing last TRB in TD.\n");
@@ -493,8 +501,8 @@
}
trb = &state->new_deq_ptr->generic;
- if ((trb->field[3] & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK) &&
- (trb->field[3] & LINK_TOGGLE))
+ if ((le32_to_cpu(trb->field[3]) & TRB_TYPE_BITMASK) ==
+ TRB_TYPE(TRB_LINK) && (le32_to_cpu(trb->field[3]) & LINK_TOGGLE))
state->new_cycle_state ^= 0x1;
next_trb(xhci, ep_ring, &state->new_deq_seg, &state->new_deq_ptr);
@@ -529,12 +537,12 @@
for (cur_seg = cur_td->start_seg, cur_trb = cur_td->first_trb;
true;
next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
- if ((cur_trb->generic.field[3] & TRB_TYPE_BITMASK) ==
- TRB_TYPE(TRB_LINK)) {
+ if ((le32_to_cpu(cur_trb->generic.field[3]) & TRB_TYPE_BITMASK)
+ == TRB_TYPE(TRB_LINK)) {
/* Unchain any chained Link TRBs, but
* leave the pointers intact.
*/
- cur_trb->generic.field[3] &= ~TRB_CHAIN;
+ cur_trb->generic.field[3] &= cpu_to_le32(~TRB_CHAIN);
xhci_dbg(xhci, "Cancel (unchain) link TRB\n");
xhci_dbg(xhci, "Address = %p (0x%llx dma); "
"in seg %p (0x%llx dma)\n",
@@ -547,8 +555,9 @@
cur_trb->generic.field[1] = 0;
cur_trb->generic.field[2] = 0;
/* Preserve only the cycle bit of this TRB */
- cur_trb->generic.field[3] &= TRB_CYCLE;
- cur_trb->generic.field[3] |= TRB_TYPE(TRB_TR_NOOP);
+ cur_trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
+ cur_trb->generic.field[3] |= cpu_to_le32(
+ TRB_TYPE(TRB_TR_NOOP));
xhci_dbg(xhci, "Cancel TRB %p (0x%llx dma) "
"in seg %p (0x%llx dma)\n",
cur_trb,
@@ -662,9 +671,9 @@
struct xhci_dequeue_state deq_state;
if (unlikely(TRB_TO_SUSPEND_PORT(
- xhci->cmd_ring->dequeue->generic.field[3]))) {
+ le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])))) {
slot_id = TRB_TO_SLOT_ID(
- xhci->cmd_ring->dequeue->generic.field[3]);
+ le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
virt_dev = xhci->devs[slot_id];
if (virt_dev)
handle_cmd_in_cmd_wait_list(xhci, virt_dev,
@@ -677,8 +686,8 @@
}
memset(&deq_state, 0, sizeof(deq_state));
- slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
- ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
+ slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
+ ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
ep = &xhci->devs[slot_id]->eps[ep_index];
if (list_empty(&ep->cancelled_td_list)) {
@@ -910,9 +919,9 @@
struct xhci_ep_ctx *ep_ctx;
struct xhci_slot_ctx *slot_ctx;
- slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
- ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
- stream_id = TRB_TO_STREAM_ID(trb->generic.field[2]);
+ slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
+ ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
+ stream_id = TRB_TO_STREAM_ID(le32_to_cpu(trb->generic.field[2]));
dev = xhci->devs[slot_id];
ep_ring = xhci_stream_id_to_ring(dev, ep_index, stream_id);
@@ -928,11 +937,11 @@
ep_ctx = xhci_get_ep_ctx(xhci, dev->out_ctx, ep_index);
slot_ctx = xhci_get_slot_ctx(xhci, dev->out_ctx);
- if (GET_COMP_CODE(event->status) != COMP_SUCCESS) {
+ if (GET_COMP_CODE(le32_to_cpu(event->status)) != COMP_SUCCESS) {
unsigned int ep_state;
unsigned int slot_state;
- switch (GET_COMP_CODE(event->status)) {
+ switch (GET_COMP_CODE(le32_to_cpu(event->status))) {
case COMP_TRB_ERR:
xhci_warn(xhci, "WARN Set TR Deq Ptr cmd invalid because "
"of stream ID configuration\n");
@@ -940,9 +949,9 @@
case COMP_CTX_STATE:
xhci_warn(xhci, "WARN Set TR Deq Ptr cmd failed due "
"to incorrect slot or ep state.\n");
- ep_state = ep_ctx->ep_info;
+ ep_state = le32_to_cpu(ep_ctx->ep_info);
ep_state &= EP_STATE_MASK;
- slot_state = slot_ctx->dev_state;
+ slot_state = le32_to_cpu(slot_ctx->dev_state);
slot_state = GET_SLOT_STATE(slot_state);
xhci_dbg(xhci, "Slot state = %u, EP state = %u\n",
slot_state, ep_state);
@@ -954,7 +963,7 @@
default:
xhci_warn(xhci, "WARN Set TR Deq Ptr cmd with unknown "
"completion code of %u.\n",
- GET_COMP_CODE(event->status));
+ GET_COMP_CODE(le32_to_cpu(event->status)));
break;
}
/* OK what do we do now? The endpoint state is hosed, and we
@@ -965,10 +974,10 @@
*/
} else {
xhci_dbg(xhci, "Successful Set TR Deq Ptr cmd, deq = @%08llx\n",
- ep_ctx->deq);
+ le64_to_cpu(ep_ctx->deq));
if (xhci_trb_virt_to_dma(dev->eps[ep_index].queued_deq_seg,
- dev->eps[ep_index].queued_deq_ptr) ==
- (ep_ctx->deq & ~(EP_CTX_CYCLE_MASK))) {
+ dev->eps[ep_index].queued_deq_ptr) ==
+ (le64_to_cpu(ep_ctx->deq) & ~(EP_CTX_CYCLE_MASK))) {
/* Update the ring's dequeue segment and dequeue pointer
* to reflect the new position.
*/
@@ -997,13 +1006,13 @@
int slot_id;
unsigned int ep_index;
- slot_id = TRB_TO_SLOT_ID(trb->generic.field[3]);
- ep_index = TRB_TO_EP_INDEX(trb->generic.field[3]);
+ slot_id = TRB_TO_SLOT_ID(le32_to_cpu(trb->generic.field[3]));
+ ep_index = TRB_TO_EP_INDEX(le32_to_cpu(trb->generic.field[3]));
/* This command will only fail if the endpoint wasn't halted,
* but we don't care.
*/
xhci_dbg(xhci, "Ignoring reset ep completion code of %u\n",
- (unsigned int) GET_COMP_CODE(event->status));
+ (unsigned int) GET_COMP_CODE(le32_to_cpu(event->status)));
/* HW with the reset endpoint quirk needs to have a configure endpoint
* command complete before the endpoint can be used. Queue that here
@@ -1040,8 +1049,7 @@
if (xhci->cmd_ring->dequeue != command->command_trb)
return 0;
- command->status =
- GET_COMP_CODE(event->status);
+ command->status = GET_COMP_CODE(le32_to_cpu(event->status));
list_del(&command->cmd_list);
if (command->completion)
complete(command->completion);
@@ -1053,7 +1061,7 @@
static void handle_cmd_completion(struct xhci_hcd *xhci,
struct xhci_event_cmd *event)
{
- int slot_id = TRB_TO_SLOT_ID(event->flags);
+ int slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
u64 cmd_dma;
dma_addr_t cmd_dequeue_dma;
struct xhci_input_control_ctx *ctrl_ctx;
@@ -1062,7 +1070,7 @@
struct xhci_ring *ep_ring;
unsigned int ep_state;
- cmd_dma = event->cmd_trb;
+ cmd_dma = le64_to_cpu(event->cmd_trb);
cmd_dequeue_dma = xhci_trb_virt_to_dma(xhci->cmd_ring->deq_seg,
xhci->cmd_ring->dequeue);
/* Is the command ring deq ptr out of sync with the deq seg ptr? */
@@ -1075,9 +1083,10 @@
xhci->error_bitmask |= 1 << 5;
return;
}
- switch (xhci->cmd_ring->dequeue->generic.field[3] & TRB_TYPE_BITMASK) {
+ switch (le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3])
+ & TRB_TYPE_BITMASK) {
case TRB_TYPE(TRB_ENABLE_SLOT):
- if (GET_COMP_CODE(event->status) == COMP_SUCCESS)
+ if (GET_COMP_CODE(le32_to_cpu(event->status)) == COMP_SUCCESS)
xhci->slot_id = slot_id;
else
xhci->slot_id = 0;
@@ -1102,7 +1111,7 @@
ctrl_ctx = xhci_get_input_control_ctx(xhci,
virt_dev->in_ctx);
/* Input ctx add_flags are the endpoint index plus one */
- ep_index = xhci_last_valid_endpoint(ctrl_ctx->add_flags) - 1;
+ ep_index = xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx->add_flags)) - 1;
/* A usb_set_interface() call directly after clearing a halted
* condition may race on this quirky hardware. Not worth
* worrying about, since this is prototype hardware. Not sure
@@ -1111,8 +1120,8 @@
*/
if (xhci->quirks & XHCI_RESET_EP_QUIRK &&
ep_index != (unsigned int) -1 &&
- ctrl_ctx->add_flags - SLOT_FLAG ==
- ctrl_ctx->drop_flags) {
+ le32_to_cpu(ctrl_ctx->add_flags) - SLOT_FLAG ==
+ le32_to_cpu(ctrl_ctx->drop_flags)) {
ep_ring = xhci->devs[slot_id]->eps[ep_index].ring;
ep_state = xhci->devs[slot_id]->eps[ep_index].ep_state;
if (!(ep_state & EP_HALTED))
@@ -1129,18 +1138,18 @@
bandwidth_change:
xhci_dbg(xhci, "Completed config ep cmd\n");
xhci->devs[slot_id]->cmd_status =
- GET_COMP_CODE(event->status);
+ GET_COMP_CODE(le32_to_cpu(event->status));
complete(&xhci->devs[slot_id]->cmd_completion);
break;
case TRB_TYPE(TRB_EVAL_CONTEXT):
virt_dev = xhci->devs[slot_id];
if (handle_cmd_in_cmd_wait_list(xhci, virt_dev, event))
break;
- xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status);
+ xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
complete(&xhci->devs[slot_id]->cmd_completion);
break;
case TRB_TYPE(TRB_ADDR_DEV):
- xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(event->status);
+ xhci->devs[slot_id]->cmd_status = GET_COMP_CODE(le32_to_cpu(event->status));
complete(&xhci->addr_dev);
break;
case TRB_TYPE(TRB_STOP_RING):
@@ -1157,7 +1166,7 @@
case TRB_TYPE(TRB_RESET_DEV):
xhci_dbg(xhci, "Completed reset device command.\n");
slot_id = TRB_TO_SLOT_ID(
- xhci->cmd_ring->dequeue->generic.field[3]);
+ le32_to_cpu(xhci->cmd_ring->dequeue->generic.field[3]));
virt_dev = xhci->devs[slot_id];
if (virt_dev)
handle_cmd_in_cmd_wait_list(xhci, virt_dev, event);
@@ -1171,8 +1180,8 @@
break;
}
xhci_dbg(xhci, "NEC firmware version %2x.%02x\n",
- NEC_FW_MAJOR(event->status),
- NEC_FW_MINOR(event->status));
+ NEC_FW_MAJOR(le32_to_cpu(event->status)),
+ NEC_FW_MINOR(le32_to_cpu(event->status)));
break;
default:
/* Skip over unknown commands on the event ring */
@@ -1187,7 +1196,7 @@
{
u32 trb_type;
- trb_type = TRB_FIELD_TO_TYPE(event->generic.field[3]);
+ trb_type = TRB_FIELD_TO_TYPE(le32_to_cpu(event->generic.field[3]));
xhci_dbg(xhci, "Vendor specific event TRB type = %u\n", trb_type);
if (trb_type == TRB_NEC_CMD_COMP && (xhci->quirks & XHCI_NEC_HOST))
handle_cmd_completion(xhci, &event->event_cmd);
@@ -1241,15 +1250,15 @@
unsigned int faked_port_index;
u8 major_revision;
struct xhci_bus_state *bus_state;
- u32 __iomem **port_array;
+ __le32 __iomem **port_array;
bool bogus_port_status = false;
/* Port status change events always have a successful completion code */
- if (GET_COMP_CODE(event->generic.field[2]) != COMP_SUCCESS) {
+ if (GET_COMP_CODE(le32_to_cpu(event->generic.field[2])) != COMP_SUCCESS) {
xhci_warn(xhci, "WARN: xHC returned failed port status event\n");
xhci->error_bitmask |= 1 << 8;
}
- port_id = GET_PORT_ID(event->generic.field[0]);
+ port_id = GET_PORT_ID(le32_to_cpu(event->generic.field[0]));
xhci_dbg(xhci, "Port Status Change Event for port %d\n", port_id);
max_ports = HCS_MAX_PORTS(xhci->hcs_params1);
@@ -1456,7 +1465,7 @@
* endpoint anyway. Check if a babble halted the
* endpoint.
*/
- if ((ep_ctx->ep_info & EP_STATE_MASK) == EP_STATE_HALTED)
+ if ((le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) == EP_STATE_HALTED)
return 1;
return 0;
@@ -1494,12 +1503,12 @@
struct urb_priv *urb_priv;
u32 trb_comp_code;
- slot_id = TRB_TO_SLOT_ID(event->flags);
+ slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
xdev = xhci->devs[slot_id];
- ep_index = TRB_TO_EP_ID(event->flags) - 1;
- ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
+ ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
+ ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
- trb_comp_code = GET_COMP_CODE(event->transfer_len);
+ trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
if (skip)
goto td_cleanup;
@@ -1602,12 +1611,12 @@
struct xhci_ep_ctx *ep_ctx;
u32 trb_comp_code;
- slot_id = TRB_TO_SLOT_ID(event->flags);
+ slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
xdev = xhci->devs[slot_id];
- ep_index = TRB_TO_EP_ID(event->flags) - 1;
- ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
+ ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
+ ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
- trb_comp_code = GET_COMP_CODE(event->transfer_len);
+ trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
xhci_debug_trb(xhci, xhci->event_ring->dequeue);
switch (trb_comp_code) {
@@ -1632,6 +1641,9 @@
else
*status = 0;
break;
+ case COMP_STOP_INVAL:
+ case COMP_STOP:
+ return finish_td(xhci, td, event_trb, event, ep, status, false);
default:
if (!xhci_requires_manual_halt_cleanup(xhci,
ep_ctx, trb_comp_code))
@@ -1646,7 +1658,7 @@
event_trb != td->last_trb)
td->urb->actual_length =
td->urb->transfer_buffer_length
- - TRB_LEN(event->transfer_len);
+ - TRB_LEN(le32_to_cpu(event->transfer_len));
else
td->urb->actual_length = 0;
@@ -1676,15 +1688,12 @@
}
} else {
/* Maybe the event was for the data stage? */
- if (trb_comp_code != COMP_STOP_INVAL) {
- /* We didn't stop on a link TRB in the middle */
- td->urb->actual_length =
- td->urb->transfer_buffer_length -
- TRB_LEN(event->transfer_len);
- xhci_dbg(xhci, "Waiting for status "
- "stage event\n");
- return 0;
- }
+ td->urb->actual_length =
+ td->urb->transfer_buffer_length -
+ TRB_LEN(le32_to_cpu(event->transfer_len));
+ xhci_dbg(xhci, "Waiting for status "
+ "stage event\n");
+ return 0;
}
}
@@ -1708,8 +1717,8 @@
u32 trb_comp_code;
bool skip_td = false;
- ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
- trb_comp_code = GET_COMP_CODE(event->transfer_len);
+ ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
+ trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
urb_priv = td->urb->hcpriv;
idx = urb_priv->td_cnt;
frame = &td->urb->iso_frame_desc[idx];
@@ -1752,15 +1761,14 @@
for (cur_trb = ep_ring->dequeue,
cur_seg = ep_ring->deq_seg; cur_trb != event_trb;
next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
- if ((cur_trb->generic.field[3] &
+ if ((le32_to_cpu(cur_trb->generic.field[3]) &
TRB_TYPE_BITMASK) != TRB_TYPE(TRB_TR_NOOP) &&
- (cur_trb->generic.field[3] &
+ (le32_to_cpu(cur_trb->generic.field[3]) &
TRB_TYPE_BITMASK) != TRB_TYPE(TRB_LINK))
- len +=
- TRB_LEN(cur_trb->generic.field[2]);
+ len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
}
- len += TRB_LEN(cur_trb->generic.field[2]) -
- TRB_LEN(event->transfer_len);
+ len += TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
+ TRB_LEN(le32_to_cpu(event->transfer_len));
if (trb_comp_code != COMP_STOP_INVAL) {
frame->actual_length = len;
@@ -1815,8 +1823,8 @@
struct xhci_segment *cur_seg;
u32 trb_comp_code;
- ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
- trb_comp_code = GET_COMP_CODE(event->transfer_len);
+ ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
+ trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
switch (trb_comp_code) {
case COMP_SUCCESS:
@@ -1852,18 +1860,18 @@
"%d bytes untransferred\n",
td->urb->ep->desc.bEndpointAddress,
td->urb->transfer_buffer_length,
- TRB_LEN(event->transfer_len));
+ TRB_LEN(le32_to_cpu(event->transfer_len)));
/* Fast path - was this the last TRB in the TD for this URB? */
if (event_trb == td->last_trb) {
- if (TRB_LEN(event->transfer_len) != 0) {
+ if (TRB_LEN(le32_to_cpu(event->transfer_len)) != 0) {
td->urb->actual_length =
td->urb->transfer_buffer_length -
- TRB_LEN(event->transfer_len);
+ TRB_LEN(le32_to_cpu(event->transfer_len));
if (td->urb->transfer_buffer_length <
td->urb->actual_length) {
xhci_warn(xhci, "HC gave bad length "
"of %d bytes left\n",
- TRB_LEN(event->transfer_len));
+ TRB_LEN(le32_to_cpu(event->transfer_len)));
td->urb->actual_length = 0;
if (td->urb->transfer_flags & URB_SHORT_NOT_OK)
*status = -EREMOTEIO;
@@ -1894,20 +1902,20 @@
for (cur_trb = ep_ring->dequeue, cur_seg = ep_ring->deq_seg;
cur_trb != event_trb;
next_trb(xhci, ep_ring, &cur_seg, &cur_trb)) {
- if ((cur_trb->generic.field[3] &
+ if ((le32_to_cpu(cur_trb->generic.field[3]) &
TRB_TYPE_BITMASK) != TRB_TYPE(TRB_TR_NOOP) &&
- (cur_trb->generic.field[3] &
+ (le32_to_cpu(cur_trb->generic.field[3]) &
TRB_TYPE_BITMASK) != TRB_TYPE(TRB_LINK))
td->urb->actual_length +=
- TRB_LEN(cur_trb->generic.field[2]);
+ TRB_LEN(le32_to_cpu(cur_trb->generic.field[2]));
}
/* If the ring didn't stop on a Link or No-op TRB, add
* in the actual bytes transferred from the Normal TRB
*/
if (trb_comp_code != COMP_STOP_INVAL)
td->urb->actual_length +=
- TRB_LEN(cur_trb->generic.field[2]) -
- TRB_LEN(event->transfer_len);
+ TRB_LEN(le32_to_cpu(cur_trb->generic.field[2])) -
+ TRB_LEN(le32_to_cpu(event->transfer_len));
}
return finish_td(xhci, td, event_trb, event, ep, status, false);
@@ -1937,7 +1945,7 @@
u32 trb_comp_code;
int ret = 0;
- slot_id = TRB_TO_SLOT_ID(event->flags);
+ slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->flags));
xdev = xhci->devs[slot_id];
if (!xdev) {
xhci_err(xhci, "ERROR Transfer event pointed to bad slot\n");
@@ -1945,20 +1953,21 @@
}
/* Endpoint ID is 1 based, our index is zero based */
- ep_index = TRB_TO_EP_ID(event->flags) - 1;
+ ep_index = TRB_TO_EP_ID(le32_to_cpu(event->flags)) - 1;
xhci_dbg(xhci, "%s - ep index = %d\n", __func__, ep_index);
ep = &xdev->eps[ep_index];
- ep_ring = xhci_dma_to_transfer_ring(ep, event->buffer);
+ ep_ring = xhci_dma_to_transfer_ring(ep, le64_to_cpu(event->buffer));
ep_ctx = xhci_get_ep_ctx(xhci, xdev->out_ctx, ep_index);
if (!ep_ring ||
- (ep_ctx->ep_info & EP_STATE_MASK) == EP_STATE_DISABLED) {
+ (le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) ==
+ EP_STATE_DISABLED) {
xhci_err(xhci, "ERROR Transfer event for disabled endpoint "
"or incorrect stream ring\n");
return -ENODEV;
}
- event_dma = event->buffer;
- trb_comp_code = GET_COMP_CODE(event->transfer_len);
+ event_dma = le64_to_cpu(event->buffer);
+ trb_comp_code = GET_COMP_CODE(le32_to_cpu(event->transfer_len));
/* Look for common error cases */
switch (trb_comp_code) {
/* Skip codes that require special handling depending on
@@ -2011,14 +2020,16 @@
if (!list_empty(&ep_ring->td_list))
xhci_dbg(xhci, "Underrun Event for slot %d ep %d "
"still with TDs queued?\n",
- TRB_TO_SLOT_ID(event->flags), ep_index);
+ TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
+ ep_index);
goto cleanup;
case COMP_OVERRUN:
xhci_dbg(xhci, "overrun event on endpoint\n");
if (!list_empty(&ep_ring->td_list))
xhci_dbg(xhci, "Overrun Event for slot %d ep %d "
"still with TDs queued?\n",
- TRB_TO_SLOT_ID(event->flags), ep_index);
+ TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
+ ep_index);
goto cleanup;
case COMP_MISSED_INT:
/*
@@ -2047,9 +2058,11 @@
if (list_empty(&ep_ring->td_list)) {
xhci_warn(xhci, "WARN Event TRB for slot %d ep %d "
"with no TDs queued?\n",
- TRB_TO_SLOT_ID(event->flags), ep_index);
+ TRB_TO_SLOT_ID(le32_to_cpu(event->flags)),
+ ep_index);
xhci_dbg(xhci, "Event TRB with TRB type ID %u\n",
- (unsigned int) (event->flags & TRB_TYPE_BITMASK)>>10);
+ (unsigned int) (le32_to_cpu(event->flags)
+ & TRB_TYPE_BITMASK)>>10);
xhci_print_trb_offsets(xhci, (union xhci_trb *) event);
if (ep->skip) {
ep->skip = false;
@@ -2092,7 +2105,8 @@
* corresponding TD has been cancelled. Just ignore
* the TD.
*/
- if ((event_trb->generic.field[3] & TRB_TYPE_BITMASK)
+ if ((le32_to_cpu(event_trb->generic.field[3])
+ & TRB_TYPE_BITMASK)
== TRB_TYPE(TRB_TR_NOOP)) {
xhci_dbg(xhci,
"event_trb is a no-op TRB. Skip it\n");
@@ -2157,8 +2171,10 @@
/*
* This function handles all OS-owned events on the event ring. It may drop
* xhci->lock between event processing (e.g. to pass up port status changes).
+ * Returns >0 for "possibly more events to process" (caller should call again),
+ * otherwise 0 if done. In future, <0 returns should indicate error code.
*/
-static void xhci_handle_event(struct xhci_hcd *xhci)
+static int xhci_handle_event(struct xhci_hcd *xhci)
{
union xhci_trb *event;
int update_ptrs = 1;
@@ -2167,20 +2183,25 @@
xhci_dbg(xhci, "In %s\n", __func__);
if (!xhci->event_ring || !xhci->event_ring->dequeue) {
xhci->error_bitmask |= 1 << 1;
- return;
+ return 0;
}
event = xhci->event_ring->dequeue;
/* Does the HC or OS own the TRB? */
- if ((event->event_cmd.flags & TRB_CYCLE) !=
- xhci->event_ring->cycle_state) {
+ if ((le32_to_cpu(event->event_cmd.flags) & TRB_CYCLE) !=
+ xhci->event_ring->cycle_state) {
xhci->error_bitmask |= 1 << 2;
- return;
+ return 0;
}
xhci_dbg(xhci, "%s - OS owns TRB\n", __func__);
+ /*
+ * Barrier between reading the TRB_CYCLE (valid) flag above and any
+ * speculative reads of the event's flags/data below.
+ */
+ rmb();
/* FIXME: Handle more event types. */
- switch ((event->event_cmd.flags & TRB_TYPE_BITMASK)) {
+ switch ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK)) {
case TRB_TYPE(TRB_COMPLETION):
xhci_dbg(xhci, "%s - calling handle_cmd_completion\n", __func__);
handle_cmd_completion(xhci, &event->event_cmd);
@@ -2202,7 +2223,8 @@
update_ptrs = 0;
break;
default:
- if ((event->event_cmd.flags & TRB_TYPE_BITMASK) >= TRB_TYPE(48))
+ if ((le32_to_cpu(event->event_cmd.flags) & TRB_TYPE_BITMASK) >=
+ TRB_TYPE(48))
handle_vendor_event(xhci, event);
else
xhci->error_bitmask |= 1 << 3;
@@ -2213,15 +2235,17 @@
if (xhci->xhc_state & XHCI_STATE_DYING) {
xhci_dbg(xhci, "xHCI host dying, returning from "
"event handler.\n");
- return;
+ return 0;
}
if (update_ptrs)
/* Update SW event ring dequeue pointer */
inc_deq(xhci, xhci->event_ring, true);
- /* Are there more items on the event ring? */
- xhci_handle_event(xhci);
+ /* Are there more items on the event ring? Caller will call us again to
+ * check.
+ */
+ return 1;
}
/*
@@ -2252,12 +2276,12 @@
xhci_dbg(xhci, "op reg status = %08x\n", status);
xhci_dbg(xhci, "Event ring dequeue ptr:\n");
xhci_dbg(xhci, "@%llx %08x %08x %08x %08x\n",
- (unsigned long long)
- xhci_trb_virt_to_dma(xhci->event_ring->deq_seg, trb),
- lower_32_bits(trb->link.segment_ptr),
- upper_32_bits(trb->link.segment_ptr),
- (unsigned int) trb->link.intr_target,
- (unsigned int) trb->link.control);
+ (unsigned long long)
+ xhci_trb_virt_to_dma(xhci->event_ring->deq_seg, trb),
+ lower_32_bits(le64_to_cpu(trb->link.segment_ptr)),
+ upper_32_bits(le64_to_cpu(trb->link.segment_ptr)),
+ (unsigned int) le32_to_cpu(trb->link.intr_target),
+ (unsigned int) le32_to_cpu(trb->link.control));
if (status & STS_FATAL) {
xhci_warn(xhci, "WARNING: Host System Error\n");
@@ -2303,7 +2327,7 @@
/* FIXME this should be a delayed service routine
* that clears the EHB.
*/
- xhci_handle_event(xhci);
+ while (xhci_handle_event(xhci) > 0) {}
temp_64 = xhci_read_64(xhci, &xhci->ir_set->erst_dequeue);
/* If necessary, update the HW's version of the event ring deq ptr. */
@@ -2358,10 +2382,10 @@
struct xhci_generic_trb *trb;
trb = &ring->enqueue->generic;
- trb->field[0] = field1;
- trb->field[1] = field2;
- trb->field[2] = field3;
- trb->field[3] = field4;
+ trb->field[0] = cpu_to_le32(field1);
+ trb->field[1] = cpu_to_le32(field2);
+ trb->field[2] = cpu_to_le32(field3);
+ trb->field[3] = cpu_to_le32(field4);
inc_enq(xhci, ring, consumer, more_trbs_coming);
}
@@ -2414,17 +2438,16 @@
next = ring->enqueue;
while (last_trb(xhci, ring, ring->enq_seg, next)) {
-
/* If we're not dealing with 0.95 hardware,
* clear the chain bit.
*/
if (!xhci_link_trb_quirk(xhci))
- next->link.control &= ~TRB_CHAIN;
+ next->link.control &= cpu_to_le32(~TRB_CHAIN);
else
- next->link.control |= TRB_CHAIN;
+ next->link.control |= cpu_to_le32(TRB_CHAIN);
wmb();
- next->link.control ^= (u32) TRB_CYCLE;
+ next->link.control ^= cpu_to_le32((u32) TRB_CYCLE);
/* Toggle the cycle bit after the last ring segment. */
if (last_trb_on_last_seg(xhci, ring, ring->enq_seg, next)) {
@@ -2467,8 +2490,8 @@
}
ret = prepare_ring(xhci, ep_ring,
- ep_ctx->ep_info & EP_STATE_MASK,
- num_trbs, mem_flags);
+ le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
+ num_trbs, mem_flags);
if (ret)
return ret;
@@ -2570,9 +2593,9 @@
*/
wmb();
if (start_cycle)
- start_trb->field[3] |= start_cycle;
+ start_trb->field[3] |= cpu_to_le32(start_cycle);
else
- start_trb->field[3] &= ~0x1;
+ start_trb->field[3] &= cpu_to_le32(~TRB_CYCLE);
xhci_ring_ep_doorbell(xhci, slot_id, ep_index, stream_id);
}
@@ -2590,7 +2613,7 @@
int xhci_interval;
int ep_interval;
- xhci_interval = EP_INTERVAL_TO_UFRAMES(ep_ctx->ep_info);
+ xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
ep_interval = urb->interval;
/* Convert to microframes */
if (urb->dev->speed == USB_SPEED_LOW ||
@@ -2632,6 +2655,35 @@
return (remainder >> 10) << 17;
}
+/*
+ * For xHCI 1.0 host controllers, TD size is the number of packets remaining in
+ * the TD (*not* including this TRB).
+ *
+ * Total TD packet count = total_packet_count =
+ * roundup(TD size in bytes / wMaxPacketSize)
+ *
+ * Packets transferred up to and including this TRB = packets_transferred =
+ * rounddown(total bytes transferred including this TRB / wMaxPacketSize)
+ *
+ * TD size = total_packet_count - packets_transferred
+ *
+ * It must fit in bits 21:17, so it can't be bigger than 31.
+ */
+
+static u32 xhci_v1_0_td_remainder(int running_total, int trb_buff_len,
+ unsigned int total_packet_count, struct urb *urb)
+{
+ int packets_transferred;
+
+ /* All the TRB queueing functions don't count the current TRB in
+ * running_total.
+ */
+ packets_transferred = (running_total + trb_buff_len) /
+ le16_to_cpu(urb->ep->desc.wMaxPacketSize);
+
+ return xhci_td_remainder(total_packet_count - packets_transferred);
+}
+
static int queue_bulk_sg_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
struct urb *urb, int slot_id, unsigned int ep_index)
{
@@ -2642,6 +2694,7 @@
struct scatterlist *sg;
int num_sgs;
int trb_buff_len, this_sg_len, running_total;
+ unsigned int total_packet_count;
bool first_trb;
u64 addr;
bool more_trbs_coming;
@@ -2655,6 +2708,8 @@
num_trbs = count_sg_trbs_needed(xhci, urb);
num_sgs = urb->num_sgs;
+ total_packet_count = roundup(urb->transfer_buffer_length,
+ le16_to_cpu(urb->ep->desc.wMaxPacketSize));
trb_buff_len = prepare_transfer(xhci, xhci->devs[slot_id],
ep_index, urb->stream_id,
@@ -2718,6 +2773,11 @@
td->last_trb = ep_ring->enqueue;
field |= TRB_IOC;
}
+
+ /* Only set interrupt on short packet for IN endpoints */
+ if (usb_urb_dir_in(urb))
+ field |= TRB_ISP;
+
xhci_dbg(xhci, " sg entry: dma = %#x, len = %#x (%d), "
"64KB boundary at %#x, end dma = %#x\n",
(unsigned int) addr, trb_buff_len, trb_buff_len,
@@ -2730,11 +2790,20 @@
(unsigned int) (addr + TRB_MAX_BUFF_SIZE) & ~(TRB_MAX_BUFF_SIZE - 1),
(unsigned int) addr + trb_buff_len);
}
- remainder = xhci_td_remainder(urb->transfer_buffer_length -
- running_total) ;
+
+ /* Set the TRB length, TD size, and interrupter fields. */
+ if (xhci->hci_version < 0x100) {
+ remainder = xhci_td_remainder(
+ urb->transfer_buffer_length -
+ running_total);
+ } else {
+ remainder = xhci_v1_0_td_remainder(running_total,
+ trb_buff_len, total_packet_count, urb);
+ }
length_field = TRB_LEN(trb_buff_len) |
remainder |
TRB_INTR_TARGET(0);
+
if (num_trbs > 1)
more_trbs_coming = true;
else
@@ -2743,12 +2812,7 @@
lower_32_bits(addr),
upper_32_bits(addr),
length_field,
- /* We always want to know if the TRB was short,
- * or we won't get an event when it completes.
- * (Unless we use event data TRBs, which are a
- * waste of space and HC resources.)
- */
- field | TRB_ISP | TRB_TYPE(TRB_NORMAL));
+ field | TRB_TYPE(TRB_NORMAL));
--num_trbs;
running_total += trb_buff_len;
@@ -2796,6 +2860,7 @@
u32 field, length_field;
int running_total, trb_buff_len, ret;
+ unsigned int total_packet_count;
u64 addr;
if (urb->num_sgs)
@@ -2850,6 +2915,8 @@
start_cycle = ep_ring->cycle_state;
running_total = 0;
+ total_packet_count = roundup(urb->transfer_buffer_length,
+ le16_to_cpu(urb->ep->desc.wMaxPacketSize));
/* How much data is in the first TRB? */
addr = (u64) urb->transfer_dma;
trb_buff_len = TRB_MAX_BUFF_SIZE -
@@ -2882,11 +2949,24 @@
td->last_trb = ep_ring->enqueue;
field |= TRB_IOC;
}
- remainder = xhci_td_remainder(urb->transfer_buffer_length -
- running_total);
+
+ /* Only set interrupt on short packet for IN endpoints */
+ if (usb_urb_dir_in(urb))
+ field |= TRB_ISP;
+
+ /* Set the TRB length, TD size, and interrupter fields. */
+ if (xhci->hci_version < 0x100) {
+ remainder = xhci_td_remainder(
+ urb->transfer_buffer_length -
+ running_total);
+ } else {
+ remainder = xhci_v1_0_td_remainder(running_total,
+ trb_buff_len, total_packet_count, urb);
+ }
length_field = TRB_LEN(trb_buff_len) |
remainder |
TRB_INTR_TARGET(0);
+
if (num_trbs > 1)
more_trbs_coming = true;
else
@@ -2895,12 +2975,7 @@
lower_32_bits(addr),
upper_32_bits(addr),
length_field,
- /* We always want to know if the TRB was short,
- * or we won't get an event when it completes.
- * (Unless we use event data TRBs, which are a
- * waste of space and HC resources.)
- */
- field | TRB_ISP | TRB_TYPE(TRB_NORMAL));
+ field | TRB_TYPE(TRB_NORMAL));
--num_trbs;
running_total += trb_buff_len;
@@ -2978,16 +3053,31 @@
field |= TRB_IDT | TRB_TYPE(TRB_SETUP);
if (start_cycle == 0)
field |= 0x1;
+
+ /* xHCI 1.0 6.4.1.2.1: Transfer Type field */
+ if (xhci->hci_version == 0x100) {
+ if (urb->transfer_buffer_length > 0) {
+ if (setup->bRequestType & USB_DIR_IN)
+ field |= TRB_TX_TYPE(TRB_DATA_IN);
+ else
+ field |= TRB_TX_TYPE(TRB_DATA_OUT);
+ }
+ }
+
queue_trb(xhci, ep_ring, false, true,
- /* FIXME endianness is probably going to bite my ass here. */
- setup->bRequestType | setup->bRequest << 8 | setup->wValue << 16,
- setup->wIndex | setup->wLength << 16,
- TRB_LEN(8) | TRB_INTR_TARGET(0),
- /* Immediate data in pointer */
- field);
+ setup->bRequestType | setup->bRequest << 8 | le16_to_cpu(setup->wValue) << 16,
+ le16_to_cpu(setup->wIndex) | le16_to_cpu(setup->wLength) << 16,
+ TRB_LEN(8) | TRB_INTR_TARGET(0),
+ /* Immediate data in pointer */
+ field);
/* If there's data, queue data TRBs */
- field = 0;
+ /* Only set interrupt on short packet for IN endpoints */
+ if (usb_urb_dir_in(urb))
+ field = TRB_ISP | TRB_TYPE(TRB_DATA);
+ else
+ field = TRB_TYPE(TRB_DATA);
+
length_field = TRB_LEN(urb->transfer_buffer_length) |
xhci_td_remainder(urb->transfer_buffer_length) |
TRB_INTR_TARGET(0);
@@ -2998,8 +3088,7 @@
lower_32_bits(urb->transfer_dma),
upper_32_bits(urb->transfer_dma),
length_field,
- /* Event on short tx */
- field | TRB_ISP | TRB_TYPE(TRB_DATA) | ep_ring->cycle_state);
+ field | ep_ring->cycle_state);
}
/* Save the DMA address of the last TRB in the TD */
@@ -3045,6 +3134,63 @@
return num_trbs;
}
+/*
+ * The transfer burst count field of the isochronous TRB defines the number of
+ * bursts that are required to move all packets in this TD. Only SuperSpeed
+ * devices can burst up to bMaxBurst number of packets per service interval.
+ * This field is zero based, meaning a value of zero in the field means one
+ * burst. Basically, for everything but SuperSpeed devices, this field will be
+ * zero. Only xHCI 1.0 host controllers support this field.
+ */
+static unsigned int xhci_get_burst_count(struct xhci_hcd *xhci,
+ struct usb_device *udev,
+ struct urb *urb, unsigned int total_packet_count)
+{
+ unsigned int max_burst;
+
+ if (xhci->hci_version < 0x100 || udev->speed != USB_SPEED_SUPER)
+ return 0;
+
+ max_burst = urb->ep->ss_ep_comp.bMaxBurst;
+ return roundup(total_packet_count, max_burst + 1) - 1;
+}
+
+/*
+ * Returns the number of packets in the last "burst" of packets. This field is
+ * valid for all speeds of devices. USB 2.0 devices can only do one "burst", so
+ * the last burst packet count is equal to the total number of packets in the
+ * TD. SuperSpeed endpoints can have up to 3 bursts. All but the last burst
+ * must contain (bMaxBurst + 1) number of packets, but the last burst can
+ * contain 1 to (bMaxBurst + 1) packets.
+ */
+static unsigned int xhci_get_last_burst_packet_count(struct xhci_hcd *xhci,
+ struct usb_device *udev,
+ struct urb *urb, unsigned int total_packet_count)
+{
+ unsigned int max_burst;
+ unsigned int residue;
+
+ if (xhci->hci_version < 0x100)
+ return 0;
+
+ switch (udev->speed) {
+ case USB_SPEED_SUPER:
+ /* bMaxBurst is zero based: 0 means 1 packet per burst */
+ max_burst = urb->ep->ss_ep_comp.bMaxBurst;
+ residue = total_packet_count % (max_burst + 1);
+ /* If residue is zero, the last burst contains (max_burst + 1)
+ * number of packets, but the TLBPC field is zero-based.
+ */
+ if (residue == 0)
+ return max_burst;
+ return residue - 1;
+ default:
+ if (total_packet_count == 0)
+ return 0;
+ return total_packet_count - 1;
+ }
+}
+
/* This is for isoc transfer */
static int xhci_queue_isoc_tx(struct xhci_hcd *xhci, gfp_t mem_flags,
struct urb *urb, int slot_id, unsigned int ep_index)
@@ -3085,12 +3231,22 @@
/* Queue the first TRB, even if it's zero-length */
for (i = 0; i < num_tds; i++) {
- first_trb = true;
+ unsigned int total_packet_count;
+ unsigned int burst_count;
+ unsigned int residue;
+ first_trb = true;
running_total = 0;
addr = start_addr + urb->iso_frame_desc[i].offset;
td_len = urb->iso_frame_desc[i].length;
td_remain_len = td_len;
+ /* FIXME: Ignoring zero-length packets, can those happen? */
+ total_packet_count = roundup(td_len,
+ le16_to_cpu(urb->ep->desc.wMaxPacketSize));
+ burst_count = xhci_get_burst_count(xhci, urb->dev, urb,
+ total_packet_count);
+ residue = xhci_get_last_burst_packet_count(xhci,
+ urb->dev, urb, total_packet_count);
trbs_per_td = count_isoc_trbs_needed(xhci, urb, i);
@@ -3104,7 +3260,7 @@
for (j = 0; j < trbs_per_td; j++) {
u32 remainder = 0;
- field = 0;
+ field = TRB_TBC(burst_count) | TRB_TLBPC(residue);
if (first_trb) {
/* Queue the isoc TRB */
@@ -3123,6 +3279,10 @@
field |= ep_ring->cycle_state;
}
+ /* Only set interrupt on short packet for IN EPs */
+ if (usb_urb_dir_in(urb))
+ field |= TRB_ISP;
+
/* Chain all the TRBs together; clear the chain bit in
* the last TRB to indicate it's the last TRB in the
* chain.
@@ -3133,6 +3293,11 @@
} else {
td->last_trb = ep_ring->enqueue;
field |= TRB_IOC;
+ if (xhci->hci_version == 0x100) {
+ /* Set BEI bit except for the last td */
+ if (i < num_tds - 1)
+ field |= TRB_BEI;
+ }
more_trbs_coming = false;
}
@@ -3142,20 +3307,24 @@
if (trb_buff_len > td_remain_len)
trb_buff_len = td_remain_len;
- remainder = xhci_td_remainder(td_len - running_total);
+ /* Set the TRB length, TD size, & interrupter fields. */
+ if (xhci->hci_version < 0x100) {
+ remainder = xhci_td_remainder(
+ td_len - running_total);
+ } else {
+ remainder = xhci_v1_0_td_remainder(
+ running_total, trb_buff_len,
+ total_packet_count, urb);
+ }
length_field = TRB_LEN(trb_buff_len) |
remainder |
TRB_INTR_TARGET(0);
+
queue_trb(xhci, ep_ring, false, more_trbs_coming,
lower_32_bits(addr),
upper_32_bits(addr),
length_field,
- /* We always want to know if the TRB was short,
- * or we won't get an event when it completes.
- * (Unless we use event data TRBs, which are a
- * waste of space and HC resources.)
- */
- field | TRB_ISP);
+ field);
running_total += trb_buff_len;
addr += trb_buff_len;
@@ -3211,8 +3380,8 @@
/* Check the ring to guarantee there is enough room for the whole urb.
* Do not insert any td of the urb to the ring if the check failed.
*/
- ret = prepare_ring(xhci, ep_ring, ep_ctx->ep_info & EP_STATE_MASK,
- num_trbs, mem_flags);
+ ret = prepare_ring(xhci, ep_ring, le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK,
+ num_trbs, mem_flags);
if (ret)
return ret;
@@ -3224,7 +3393,7 @@
urb->dev->speed == USB_SPEED_FULL)
urb->start_frame >>= 3;
- xhci_interval = EP_INTERVAL_TO_UFRAMES(ep_ctx->ep_info);
+ xhci_interval = EP_INTERVAL_TO_UFRAMES(le32_to_cpu(ep_ctx->ep_info));
ep_interval = urb->interval;
/* Convert to microframes */
if (urb->dev->speed == USB_SPEED_LOW ||
diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
index 81b976e..8f2a56e 100644
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -973,8 +973,8 @@
out_ctx = xhci->devs[slot_id]->out_ctx;
ep_ctx = xhci_get_ep_ctx(xhci, out_ctx, ep_index);
- hw_max_packet_size = MAX_PACKET_DECODED(ep_ctx->ep_info2);
- max_packet_size = urb->dev->ep0.desc.wMaxPacketSize;
+ hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
+ max_packet_size = le16_to_cpu(urb->dev->ep0.desc.wMaxPacketSize);
if (hw_max_packet_size != max_packet_size) {
xhci_dbg(xhci, "Max Packet Size for ep 0 changed.\n");
xhci_dbg(xhci, "Max packet size in usb_device = %d\n",
@@ -988,15 +988,15 @@
xhci->devs[slot_id]->out_ctx, ep_index);
in_ctx = xhci->devs[slot_id]->in_ctx;
ep_ctx = xhci_get_ep_ctx(xhci, in_ctx, ep_index);
- ep_ctx->ep_info2 &= ~MAX_PACKET_MASK;
- ep_ctx->ep_info2 |= MAX_PACKET(max_packet_size);
+ ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET_MASK);
+ ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
/* Set up the input context flags for the command */
/* FIXME: This won't work if a non-default control endpoint
* changes max packet sizes.
*/
ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
- ctrl_ctx->add_flags = EP0_FLAG;
+ ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
ctrl_ctx->drop_flags = 0;
xhci_dbg(xhci, "Slot %d input context\n", slot_id);
@@ -1010,7 +1010,7 @@
/* Clean up the input context for later use by bandwidth
* functions.
*/
- ctrl_ctx->add_flags = SLOT_FLAG;
+ ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
}
return ret;
}
@@ -1331,27 +1331,30 @@
/* If the HC already knows the endpoint is disabled,
* or the HCD has noted it is disabled, ignore this request
*/
- if ((ep_ctx->ep_info & EP_STATE_MASK) == EP_STATE_DISABLED ||
- ctrl_ctx->drop_flags & xhci_get_endpoint_flag(&ep->desc)) {
+ if ((le32_to_cpu(ep_ctx->ep_info) & EP_STATE_MASK) ==
+ EP_STATE_DISABLED ||
+ le32_to_cpu(ctrl_ctx->drop_flags) &
+ xhci_get_endpoint_flag(&ep->desc)) {
xhci_warn(xhci, "xHCI %s called with disabled ep %p\n",
__func__, ep);
return 0;
}
- ctrl_ctx->drop_flags |= drop_flag;
- new_drop_flags = ctrl_ctx->drop_flags;
+ ctrl_ctx->drop_flags |= cpu_to_le32(drop_flag);
+ new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
- ctrl_ctx->add_flags &= ~drop_flag;
- new_add_flags = ctrl_ctx->add_flags;
+ ctrl_ctx->add_flags &= cpu_to_le32(~drop_flag);
+ new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
- last_ctx = xhci_last_valid_endpoint(ctrl_ctx->add_flags);
+ last_ctx = xhci_last_valid_endpoint(le32_to_cpu(ctrl_ctx->add_flags));
slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
/* Update the last valid endpoint context, if we deleted the last one */
- if ((slot_ctx->dev_info & LAST_CTX_MASK) > LAST_CTX(last_ctx)) {
- slot_ctx->dev_info &= ~LAST_CTX_MASK;
- slot_ctx->dev_info |= LAST_CTX(last_ctx);
+ if ((le32_to_cpu(slot_ctx->dev_info) & LAST_CTX_MASK) >
+ LAST_CTX(last_ctx)) {
+ slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
+ slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(last_ctx));
}
- new_slot_info = slot_ctx->dev_info;
+ new_slot_info = le32_to_cpu(slot_ctx->dev_info);
xhci_endpoint_zero(xhci, xhci->devs[udev->slot_id], ep);
@@ -1419,7 +1422,8 @@
/* If the HCD has already noted the endpoint is enabled,
* ignore this request.
*/
- if (ctrl_ctx->add_flags & xhci_get_endpoint_flag(&ep->desc)) {
+ if (le32_to_cpu(ctrl_ctx->add_flags) &
+ xhci_get_endpoint_flag(&ep->desc)) {
xhci_warn(xhci, "xHCI %s called with enabled ep %p\n",
__func__, ep);
return 0;
@@ -1437,8 +1441,8 @@
return -ENOMEM;
}
- ctrl_ctx->add_flags |= added_ctxs;
- new_add_flags = ctrl_ctx->add_flags;
+ ctrl_ctx->add_flags |= cpu_to_le32(added_ctxs);
+ new_add_flags = le32_to_cpu(ctrl_ctx->add_flags);
/* If xhci_endpoint_disable() was called for this endpoint, but the
* xHC hasn't been notified yet through the check_bandwidth() call,
@@ -1446,15 +1450,16 @@
* descriptors. We must drop and re-add this endpoint, so we leave the
* drop flags alone.
*/
- new_drop_flags = ctrl_ctx->drop_flags;
+ new_drop_flags = le32_to_cpu(ctrl_ctx->drop_flags);
slot_ctx = xhci_get_slot_ctx(xhci, in_ctx);
/* Update the last valid endpoint context, if we just added one past */
- if ((slot_ctx->dev_info & LAST_CTX_MASK) < LAST_CTX(last_ctx)) {
- slot_ctx->dev_info &= ~LAST_CTX_MASK;
- slot_ctx->dev_info |= LAST_CTX(last_ctx);
+ if ((le32_to_cpu(slot_ctx->dev_info) & LAST_CTX_MASK) <
+ LAST_CTX(last_ctx)) {
+ slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
+ slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(last_ctx));
}
- new_slot_info = slot_ctx->dev_info;
+ new_slot_info = le32_to_cpu(slot_ctx->dev_info);
/* Store the usb_device pointer for later use */
ep->hcpriv = udev;
@@ -1484,9 +1489,9 @@
ctrl_ctx->drop_flags = 0;
ctrl_ctx->add_flags = 0;
slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
- slot_ctx->dev_info &= ~LAST_CTX_MASK;
+ slot_ctx->dev_info &= cpu_to_le32(~LAST_CTX_MASK);
/* Endpoint 0 is always valid */
- slot_ctx->dev_info |= LAST_CTX(1);
+ slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
for (i = 1; i < 31; ++i) {
ep_ctx = xhci_get_ep_ctx(xhci, virt_dev->in_ctx, i);
ep_ctx->ep_info = 0;
@@ -1497,7 +1502,7 @@
}
static int xhci_configure_endpoint_result(struct xhci_hcd *xhci,
- struct usb_device *udev, int *cmd_status)
+ struct usb_device *udev, u32 *cmd_status)
{
int ret;
@@ -1535,7 +1540,7 @@
}
static int xhci_evaluate_context_result(struct xhci_hcd *xhci,
- struct usb_device *udev, int *cmd_status)
+ struct usb_device *udev, u32 *cmd_status)
{
int ret;
struct xhci_virt_device *virt_dev = xhci->devs[udev->slot_id];
@@ -1555,6 +1560,11 @@
xhci_dbg_ctx(xhci, virt_dev->out_ctx, 1);
ret = -EINVAL;
break;
+ case COMP_MEL_ERR:
+ /* Max Exit Latency too large error */
+ dev_warn(&udev->dev, "WARN: Max Exit Latency too large\n");
+ ret = -EINVAL;
+ break;
case COMP_SUCCESS:
dev_dbg(&udev->dev, "Successful evaluate context command\n");
ret = 0;
@@ -1581,7 +1591,7 @@
unsigned long flags;
struct xhci_container_ctx *in_ctx;
struct completion *cmd_completion;
- int *cmd_status;
+ u32 *cmd_status;
struct xhci_virt_device *virt_dev;
spin_lock_irqsave(&xhci->lock, flags);
@@ -1595,8 +1605,8 @@
/* Enqueue pointer can be left pointing to the link TRB,
* we must handle that
*/
- if ((command->command_trb->link.control & TRB_TYPE_BITMASK)
- == TRB_TYPE(TRB_LINK))
+ if ((le32_to_cpu(command->command_trb->link.control)
+ & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK))
command->command_trb =
xhci->cmd_ring->enq_seg->next->trbs;
@@ -1672,14 +1682,13 @@
/* See section 4.6.6 - A0 = 1; A1 = D0 = D1 = 0 */
ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
- ctrl_ctx->add_flags |= SLOT_FLAG;
- ctrl_ctx->add_flags &= ~EP0_FLAG;
- ctrl_ctx->drop_flags &= ~SLOT_FLAG;
- ctrl_ctx->drop_flags &= ~EP0_FLAG;
+ ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
+ ctrl_ctx->add_flags &= cpu_to_le32(~EP0_FLAG);
+ ctrl_ctx->drop_flags &= cpu_to_le32(~(SLOT_FLAG | EP0_FLAG));
xhci_dbg(xhci, "New Input Control Context:\n");
slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
xhci_dbg_ctx(xhci, virt_dev->in_ctx,
- LAST_CTX_TO_EP_NUM(slot_ctx->dev_info));
+ LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info)));
ret = xhci_configure_endpoint(xhci, udev, NULL,
false, false);
@@ -1690,10 +1699,19 @@
xhci_dbg(xhci, "Output context after successful config ep cmd:\n");
xhci_dbg_ctx(xhci, virt_dev->out_ctx,
- LAST_CTX_TO_EP_NUM(slot_ctx->dev_info));
+ LAST_CTX_TO_EP_NUM(le32_to_cpu(slot_ctx->dev_info)));
+ /* Free any rings that were dropped, but not changed. */
+ for (i = 1; i < 31; ++i) {
+ if ((ctrl_ctx->drop_flags & (1 << (i + 1))) &&
+ !(ctrl_ctx->add_flags & (1 << (i + 1))))
+ xhci_free_or_cache_endpoint_ring(xhci, virt_dev, i);
+ }
xhci_zero_in_ctx(xhci, virt_dev);
- /* Install new rings and free or cache any old rings */
+ /*
+ * Install any rings for completely new endpoints or changed endpoints,
+ * and free or cache any old rings from changed endpoints.
+ */
for (i = 1; i < 31; ++i) {
if (!virt_dev->eps[i].new_ring)
continue;
@@ -1740,10 +1758,10 @@
{
struct xhci_input_control_ctx *ctrl_ctx;
ctrl_ctx = xhci_get_input_control_ctx(xhci, in_ctx);
- ctrl_ctx->add_flags = add_flags;
- ctrl_ctx->drop_flags = drop_flags;
+ ctrl_ctx->add_flags = cpu_to_le32(add_flags);
+ ctrl_ctx->drop_flags = cpu_to_le32(drop_flags);
xhci_slot_copy(xhci, in_ctx, out_ctx);
- ctrl_ctx->add_flags |= SLOT_FLAG;
+ ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
xhci_dbg(xhci, "Input Context:\n");
xhci_dbg_ctx(xhci, in_ctx, xhci_last_valid_endpoint(add_flags));
@@ -1772,7 +1790,7 @@
deq_state->new_deq_ptr);
return;
}
- ep_ctx->deq = addr | deq_state->new_cycle_state;
+ ep_ctx->deq = cpu_to_le64(addr | deq_state->new_cycle_state);
added_ctxs = xhci_get_endpoint_flag_from_index(ep_index);
xhci_setup_input_ctx_for_config_ep(xhci, xhci->devs[slot_id]->in_ctx,
@@ -2327,8 +2345,8 @@
/* Enqueue pointer can be left pointing to the link TRB,
* we must handle that
*/
- if ((reset_device_cmd->command_trb->link.control & TRB_TYPE_BITMASK)
- == TRB_TYPE(TRB_LINK))
+ if ((le32_to_cpu(reset_device_cmd->command_trb->link.control)
+ & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK))
reset_device_cmd->command_trb =
xhci->cmd_ring->enq_seg->next->trbs;
@@ -2542,6 +2560,17 @@
virt_dev = xhci->devs[udev->slot_id];
+ if (WARN_ON(!virt_dev)) {
+ /*
+ * In plug/unplug torture test with an NEC controller,
+ * a zero-dereference was observed once due to virt_dev = 0.
+ * Print useful debug rather than crash if it is observed again!
+ */
+ xhci_warn(xhci, "Virt dev invalid for slot_id 0x%x!\n",
+ udev->slot_id);
+ return -EINVAL;
+ }
+
slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->in_ctx);
/*
* If this is the first Set Address since device plug-in or
@@ -2609,10 +2638,10 @@
temp_64 = xhci_read_64(xhci, &xhci->op_regs->dcbaa_ptr);
xhci_dbg(xhci, "Op regs DCBAA ptr = %#016llx\n", temp_64);
xhci_dbg(xhci, "Slot ID %d dcbaa entry @%p = %#016llx\n",
- udev->slot_id,
- &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
- (unsigned long long)
- xhci->dcbaa->dev_context_ptrs[udev->slot_id]);
+ udev->slot_id,
+ &xhci->dcbaa->dev_context_ptrs[udev->slot_id],
+ (unsigned long long)
+ le64_to_cpu(xhci->dcbaa->dev_context_ptrs[udev->slot_id]));
xhci_dbg(xhci, "Output Context DMA address = %#08llx\n",
(unsigned long long)virt_dev->out_ctx->dma);
xhci_dbg(xhci, "Slot ID %d Input Context:\n", udev->slot_id);
@@ -2626,7 +2655,8 @@
slot_ctx = xhci_get_slot_ctx(xhci, virt_dev->out_ctx);
/* Use kernel assigned address for devices; store xHC assigned
* address locally. */
- virt_dev->address = (slot_ctx->dev_state & DEV_ADDR_MASK) + 1;
+ virt_dev->address = (le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK)
+ + 1;
/* Zero the input context control for later use */
ctrl_ctx = xhci_get_input_control_ctx(xhci, virt_dev->in_ctx);
ctrl_ctx->add_flags = 0;
@@ -2670,24 +2700,29 @@
spin_lock_irqsave(&xhci->lock, flags);
xhci_slot_copy(xhci, config_cmd->in_ctx, vdev->out_ctx);
ctrl_ctx = xhci_get_input_control_ctx(xhci, config_cmd->in_ctx);
- ctrl_ctx->add_flags |= SLOT_FLAG;
+ ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
slot_ctx = xhci_get_slot_ctx(xhci, config_cmd->in_ctx);
- slot_ctx->dev_info |= DEV_HUB;
+ slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
if (tt->multi)
- slot_ctx->dev_info |= DEV_MTT;
+ slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
if (xhci->hci_version > 0x95) {
xhci_dbg(xhci, "xHCI version %x needs hub "
"TT think time and number of ports\n",
(unsigned int) xhci->hci_version);
- slot_ctx->dev_info2 |= XHCI_MAX_PORTS(hdev->maxchild);
+ slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(hdev->maxchild));
/* Set TT think time - convert from ns to FS bit times.
* 0 = 8 FS bit times, 1 = 16 FS bit times,
* 2 = 24 FS bit times, 3 = 32 FS bit times.
+ *
+ * xHCI 1.0: this field shall be 0 if the device is not a
+ * High-spped hub.
*/
think_time = tt->think_time;
if (think_time != 0)
think_time = (think_time / 666) - 1;
- slot_ctx->tt_info |= TT_THINK_TIME(think_time);
+ if (xhci->hci_version < 0x100 || hdev->speed == USB_SPEED_HIGH)
+ slot_ctx->tt_info |=
+ cpu_to_le32(TT_THINK_TIME(think_time));
} else {
xhci_dbg(xhci, "xHCI version %x doesn't need hub "
"TT think time or number of ports\n",
diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
index ba1be6b..e12db7cf 100644
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
@@ -57,13 +57,13 @@
* @run_regs_off: RTSOFF - Runtime register space offset
*/
struct xhci_cap_regs {
- u32 hc_capbase;
- u32 hcs_params1;
- u32 hcs_params2;
- u32 hcs_params3;
- u32 hcc_params;
- u32 db_off;
- u32 run_regs_off;
+ __le32 hc_capbase;
+ __le32 hcs_params1;
+ __le32 hcs_params2;
+ __le32 hcs_params3;
+ __le32 hcc_params;
+ __le32 db_off;
+ __le32 run_regs_off;
/* Reserved up to (CAPLENGTH - 0x1C) */
};
@@ -155,26 +155,26 @@
* devices.
*/
struct xhci_op_regs {
- u32 command;
- u32 status;
- u32 page_size;
- u32 reserved1;
- u32 reserved2;
- u32 dev_notification;
- u64 cmd_ring;
+ __le32 command;
+ __le32 status;
+ __le32 page_size;
+ __le32 reserved1;
+ __le32 reserved2;
+ __le32 dev_notification;
+ __le64 cmd_ring;
/* rsvd: offset 0x20-2F */
- u32 reserved3[4];
- u64 dcbaa_ptr;
- u32 config_reg;
+ __le32 reserved3[4];
+ __le64 dcbaa_ptr;
+ __le32 config_reg;
/* rsvd: offset 0x3C-3FF */
- u32 reserved4[241];
+ __le32 reserved4[241];
/* port 1 registers, which serve as a base address for other ports */
- u32 port_status_base;
- u32 port_power_base;
- u32 port_link_base;
- u32 reserved5;
+ __le32 port_status_base;
+ __le32 port_power_base;
+ __le32 port_link_base;
+ __le32 reserved5;
/* registers for ports 2-255 */
- u32 reserved6[NUM_PORT_REGS*254];
+ __le32 reserved6[NUM_PORT_REGS*254];
};
/* USBCMD - USB command - command bitmasks */
@@ -382,12 +382,12 @@
* updates the dequeue pointer.
*/
struct xhci_intr_reg {
- u32 irq_pending;
- u32 irq_control;
- u32 erst_size;
- u32 rsvd;
- u64 erst_base;
- u64 erst_dequeue;
+ __le32 irq_pending;
+ __le32 irq_control;
+ __le32 erst_size;
+ __le32 rsvd;
+ __le64 erst_base;
+ __le64 erst_dequeue;
};
/* irq_pending bitmasks */
@@ -432,8 +432,8 @@
* or larger accesses"
*/
struct xhci_run_regs {
- u32 microframe_index;
- u32 rsvd[7];
+ __le32 microframe_index;
+ __le32 rsvd[7];
struct xhci_intr_reg ir_set[128];
};
@@ -447,7 +447,7 @@
* Section 5.6
*/
struct xhci_doorbell_array {
- u32 doorbell[256];
+ __le32 doorbell[256];
};
#define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16))
@@ -504,12 +504,12 @@
* reserved at the end of the slot context for HC internal use.
*/
struct xhci_slot_ctx {
- u32 dev_info;
- u32 dev_info2;
- u32 tt_info;
- u32 dev_state;
+ __le32 dev_info;
+ __le32 dev_info2;
+ __le32 tt_info;
+ __le32 dev_state;
/* offset 0x10 to 0x1f reserved for HC internal use */
- u32 reserved[4];
+ __le32 reserved[4];
};
/* dev_info bitmasks */
@@ -580,12 +580,12 @@
* reserved at the end of the endpoint context for HC internal use.
*/
struct xhci_ep_ctx {
- u32 ep_info;
- u32 ep_info2;
- u64 deq;
- u32 tx_info;
+ __le32 ep_info;
+ __le32 ep_info2;
+ __le64 deq;
+ __le32 tx_info;
/* offset 0x14 - 0x1f reserved for HC internal use */
- u32 reserved[3];
+ __le32 reserved[3];
};
/* ep_info bitmasks */
@@ -660,9 +660,9 @@
* @add_context: set the bit of the endpoint context you want to enable
*/
struct xhci_input_control_ctx {
- u32 drop_flags;
- u32 add_flags;
- u32 rsvd2[6];
+ __le32 drop_flags;
+ __le32 add_flags;
+ __le32 rsvd2[6];
};
/* Represents everything that is needed to issue a command on the command ring.
@@ -688,9 +688,9 @@
struct xhci_stream_ctx {
/* 64-bit stream ring address, cycle state, and stream type */
- u64 stream_ring;
+ __le64 stream_ring;
/* offset 0x14 - 0x1f reserved for HC internal use */
- u32 reserved[2];
+ __le32 reserved[2];
};
/* Stream Context Types (section 6.4.1) - bits 3:1 of stream ctx deq ptr */
@@ -803,7 +803,7 @@
*/
struct xhci_device_context_array {
/* 64-bit device addresses; we only write 32-bit addresses */
- u64 dev_context_ptrs[MAX_HC_SLOTS];
+ __le64 dev_context_ptrs[MAX_HC_SLOTS];
/* private xHCD pointers */
dma_addr_t dma;
};
@@ -816,10 +816,10 @@
struct xhci_transfer_event {
/* 64-bit buffer address, or immediate data */
- u64 buffer;
- u32 transfer_len;
+ __le64 buffer;
+ __le32 transfer_len;
/* This field is interpreted differently based on the type of TRB */
- u32 flags;
+ __le32 flags;
};
/** Transfer Event bit fields **/
@@ -881,7 +881,9 @@
#define COMP_STOP_INVAL 27
/* Control Abort Error - Debug Capability - control pipe aborted */
#define COMP_DBG_ABORT 28
-/* TRB type 29 and 30 reserved */
+/* Max Exit Latency Too Large Error */
+#define COMP_MEL_ERR 29
+/* TRB type 30 reserved */
/* Isoc Buffer Overrun - an isoc IN ep sent more data than could fit in TD */
#define COMP_BUFF_OVER 31
/* Event Lost Error - xHC has an "internal event overrun condition" */
@@ -898,9 +900,9 @@
struct xhci_link_trb {
/* 64-bit segment pointer*/
- u64 segment_ptr;
- u32 intr_target;
- u32 control;
+ __le64 segment_ptr;
+ __le32 intr_target;
+ __le32 control;
};
/* control bitfields */
@@ -909,9 +911,9 @@
/* Command completion event TRB */
struct xhci_event_cmd {
/* Pointer to command TRB, or the value passed by the event data trb */
- u64 cmd_trb;
- u32 status;
- u32 flags;
+ __le64 cmd_trb;
+ __le32 status;
+ __le32 flags;
};
/* flags bitmasks */
@@ -943,6 +945,8 @@
/* Interrupter Target - which MSI-X vector to target the completion event at */
#define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22)
#define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff)
+#define TRB_TBC(p) (((p) & 0x3) << 7)
+#define TRB_TLBPC(p) (((p) & 0xf) << 16)
/* Cycle bit - indicates TRB ownership by HC or HCD */
#define TRB_CYCLE (1<<0)
@@ -962,15 +966,20 @@
/* The buffer pointer contains immediate data */
#define TRB_IDT (1<<6)
+/* Block Event Interrupt */
+#define TRB_BEI (1<<9)
/* Control transfer TRB specific fields */
#define TRB_DIR_IN (1<<16)
+#define TRB_TX_TYPE(p) ((p) << 16)
+#define TRB_DATA_OUT 2
+#define TRB_DATA_IN 3
/* Isochronous TRB specific fields */
#define TRB_SIA (1<<31)
struct xhci_generic_trb {
- u32 field[4];
+ __le32 field[4];
};
union xhci_trb {
@@ -1118,10 +1127,10 @@
struct xhci_erst_entry {
/* 64-bit event ring segment address */
- u64 seg_addr;
- u32 seg_size;
+ __le64 seg_addr;
+ __le32 seg_size;
/* Set to zero */
- u32 rsvd;
+ __le32 rsvd;
};
struct xhci_erst {
@@ -1286,10 +1295,10 @@
/* Is each xHCI roothub port a USB 3.0, USB 2.0, or USB 1.1 port? */
u8 *port_array;
/* Array of pointers to USB 3.0 PORTSC registers */
- u32 __iomem **usb3_ports;
+ __le32 __iomem **usb3_ports;
unsigned int num_usb3_ports;
/* Array of pointers to USB 2.0 PORTSC registers */
- u32 __iomem **usb2_ports;
+ __le32 __iomem **usb2_ports;
unsigned int num_usb2_ports;
};
@@ -1322,12 +1331,12 @@
/* TODO: copied from ehci.h - can be refactored? */
/* xHCI spec says all registers are little endian */
static inline unsigned int xhci_readl(const struct xhci_hcd *xhci,
- __u32 __iomem *regs)
+ __le32 __iomem *regs)
{
return readl(regs);
}
static inline void xhci_writel(struct xhci_hcd *xhci,
- const unsigned int val, __u32 __iomem *regs)
+ const unsigned int val, __le32 __iomem *regs)
{
xhci_dbg(xhci,
"`MEM_WRITE_DWORD(3'b000, 32'h%p, 32'h%0x, 4'hf);\n",
@@ -1345,7 +1354,7 @@
* the high dword, and write order is irrelevant.
*/
static inline u64 xhci_read_64(const struct xhci_hcd *xhci,
- __u64 __iomem *regs)
+ __le64 __iomem *regs)
{
__u32 __iomem *ptr = (__u32 __iomem *) regs;
u64 val_lo = readl(ptr);
@@ -1353,7 +1362,7 @@
return val_lo + (val_hi << 32);
}
static inline void xhci_write_64(struct xhci_hcd *xhci,
- const u64 val, __u64 __iomem *regs)
+ const u64 val, __le64 __iomem *regs)
{
__u32 __iomem *ptr = (__u32 __iomem *) regs;
u32 val_lo = lower_32_bits(val);
diff --git a/drivers/usb/misc/ftdi-elan.c b/drivers/usb/misc/ftdi-elan.c
index 7839c98..b16bd3c 100644
--- a/drivers/usb/misc/ftdi-elan.c
+++ b/drivers/usb/misc/ftdi-elan.c
@@ -2889,8 +2889,7 @@
static int __init ftdi_elan_init(void)
{
int result;
- printk(KERN_INFO "driver %s built at %s on %s\n", ftdi_elan_driver.name,
- __TIME__, __DATE__);
+ printk(KERN_INFO "driver %s\n", ftdi_elan_driver.name);
mutex_init(&ftdi_module_lock);
INIT_LIST_HEAD(&ftdi_static_list);
status_queue = create_singlethread_workqueue("ftdi-status-control");
diff --git a/drivers/usb/misc/ldusb.c b/drivers/usb/misc/ldusb.c
index eefb827..cb40962 100644
--- a/drivers/usb/misc/ldusb.c
+++ b/drivers/usb/misc/ldusb.c
@@ -20,11 +20,6 @@
* Derived from Lego USB Tower driver
* Copyright (C) 2003 David Glance <advidgsf@sourceforge.net>
* 2001-2004 Juergen Stuber <starblue@users.sourceforge.net>
- *
- * V0.1 (mh) Initial version
- * V0.11 (mh) Added raw support for HID 1.0 devices (no interrupt out endpoint)
- * V0.12 (mh) Added kmalloc check for string buffer
- * V0.13 (mh) Added support for LD X-Ray and Machine Test System
*/
#include <linux/kernel.h>
@@ -41,20 +36,39 @@
/* Define these values to match your devices */
#define USB_VENDOR_ID_LD 0x0f11 /* USB Vendor ID of LD Didactic GmbH */
-#define USB_DEVICE_ID_LD_CASSY 0x1000 /* USB Product ID of CASSY-S */
+#define USB_DEVICE_ID_LD_CASSY 0x1000 /* USB Product ID of CASSY-S modules with 8 bytes endpoint size */
+#define USB_DEVICE_ID_LD_CASSY2 0x1001 /* USB Product ID of CASSY-S modules with 64 bytes endpoint size */
#define USB_DEVICE_ID_LD_POCKETCASSY 0x1010 /* USB Product ID of Pocket-CASSY */
+#define USB_DEVICE_ID_LD_POCKETCASSY2 0x1011 /* USB Product ID of Pocket-CASSY 2 (reserved) */
#define USB_DEVICE_ID_LD_MOBILECASSY 0x1020 /* USB Product ID of Mobile-CASSY */
+#define USB_DEVICE_ID_LD_MOBILECASSY2 0x1021 /* USB Product ID of Mobile-CASSY 2 (reserved) */
+#define USB_DEVICE_ID_LD_MICROCASSYVOLTAGE 0x1031 /* USB Product ID of Micro-CASSY Voltage */
+#define USB_DEVICE_ID_LD_MICROCASSYCURRENT 0x1032 /* USB Product ID of Micro-CASSY Current */
+#define USB_DEVICE_ID_LD_MICROCASSYTIME 0x1033 /* USB Product ID of Micro-CASSY Time (reserved) */
+#define USB_DEVICE_ID_LD_MICROCASSYTEMPERATURE 0x1035 /* USB Product ID of Micro-CASSY Temperature */
+#define USB_DEVICE_ID_LD_MICROCASSYPH 0x1038 /* USB Product ID of Micro-CASSY pH */
#define USB_DEVICE_ID_LD_JWM 0x1080 /* USB Product ID of Joule and Wattmeter */
#define USB_DEVICE_ID_LD_DMMP 0x1081 /* USB Product ID of Digital Multimeter P (reserved) */
#define USB_DEVICE_ID_LD_UMIP 0x1090 /* USB Product ID of UMI P */
-#define USB_DEVICE_ID_LD_XRAY1 0x1100 /* USB Product ID of X-Ray Apparatus */
-#define USB_DEVICE_ID_LD_XRAY2 0x1101 /* USB Product ID of X-Ray Apparatus */
+#define USB_DEVICE_ID_LD_UMIC 0x10A0 /* USB Product ID of UMI C */
+#define USB_DEVICE_ID_LD_UMIB 0x10B0 /* USB Product ID of UMI B */
+#define USB_DEVICE_ID_LD_XRAY 0x1100 /* USB Product ID of X-Ray Apparatus 55481 */
+#define USB_DEVICE_ID_LD_XRAY2 0x1101 /* USB Product ID of X-Ray Apparatus 554800 */
+#define USB_DEVICE_ID_LD_XRAYCT 0x1110 /* USB Product ID of X-Ray Apparatus CT 554821*/
#define USB_DEVICE_ID_LD_VIDEOCOM 0x1200 /* USB Product ID of VideoCom */
+#define USB_DEVICE_ID_LD_MOTOR 0x1210 /* USB Product ID of Motor (reserved) */
#define USB_DEVICE_ID_LD_COM3LAB 0x2000 /* USB Product ID of COM3LAB */
#define USB_DEVICE_ID_LD_TELEPORT 0x2010 /* USB Product ID of Terminal Adapter */
#define USB_DEVICE_ID_LD_NETWORKANALYSER 0x2020 /* USB Product ID of Network Analyser */
#define USB_DEVICE_ID_LD_POWERCONTROL 0x2030 /* USB Product ID of Converter Control Unit */
#define USB_DEVICE_ID_LD_MACHINETEST 0x2040 /* USB Product ID of Machine Test System */
+#define USB_DEVICE_ID_LD_MOSTANALYSER 0x2050 /* USB Product ID of MOST Protocol Analyser */
+#define USB_DEVICE_ID_LD_MOSTANALYSER2 0x2051 /* USB Product ID of MOST Protocol Analyser 2 */
+#define USB_DEVICE_ID_LD_ABSESP 0x2060 /* USB Product ID of ABS ESP */
+#define USB_DEVICE_ID_LD_AUTODATABUS 0x2070 /* USB Product ID of Automotive Data Buses */
+#define USB_DEVICE_ID_LD_MCT 0x2080 /* USB Product ID of Microcontroller technique */
+#define USB_DEVICE_ID_LD_HYBRID 0x2090 /* USB Product ID of Automotive Hybrid */
+#define USB_DEVICE_ID_LD_HEATCONTROL 0x20A0 /* USB Product ID of Heat control */
#define USB_VENDOR_ID_VERNIER 0x08f7
#define USB_DEVICE_ID_VERNIER_GOTEMP 0x0002
@@ -71,19 +85,37 @@
/* table of devices that work with this driver */
static const struct usb_device_id ld_usb_table[] = {
{ USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_CASSY) },
+ { USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_CASSY2) },
{ USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_POCKETCASSY) },
+ { USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_POCKETCASSY2) },
{ USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_MOBILECASSY) },
+ { USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_MOBILECASSY2) },
+ { USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_MICROCASSYVOLTAGE) },
+ { USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_MICROCASSYCURRENT) },
+ { USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_MICROCASSYTIME) },
+ { USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_MICROCASSYTEMPERATURE) },
+ { USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_MICROCASSYPH) },
{ USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_JWM) },
{ USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_DMMP) },
{ USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_UMIP) },
- { USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_XRAY1) },
+ { USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_UMIC) },
+ { USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_UMIB) },
+ { USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_XRAY) },
{ USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_XRAY2) },
{ USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_VIDEOCOM) },
+ { USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_MOTOR) },
{ USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_COM3LAB) },
{ USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_TELEPORT) },
{ USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_NETWORKANALYSER) },
{ USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_POWERCONTROL) },
{ USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_MACHINETEST) },
+ { USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_MOSTANALYSER) },
+ { USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_MOSTANALYSER2) },
+ { USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_ABSESP) },
+ { USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_AUTODATABUS) },
+ { USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_MCT) },
+ { USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_HYBRID) },
+ { USB_DEVICE(USB_VENDOR_ID_LD, USB_DEVICE_ID_LD_HEATCONTROL) },
{ USB_DEVICE(USB_VENDOR_ID_VERNIER, USB_DEVICE_ID_VERNIER_GOTEMP) },
{ USB_DEVICE(USB_VENDOR_ID_VERNIER, USB_DEVICE_ID_VERNIER_SKIP) },
{ USB_DEVICE(USB_VENDOR_ID_VERNIER, USB_DEVICE_ID_VERNIER_CYCLOPS) },
@@ -91,7 +123,7 @@
{ } /* Terminating entry */
};
MODULE_DEVICE_TABLE(usb, ld_usb_table);
-MODULE_VERSION("V0.13");
+MODULE_VERSION("V0.14");
MODULE_AUTHOR("Michael Hund <mhund@ld-didactic.de>");
MODULE_DESCRIPTION("LD USB Driver");
MODULE_LICENSE("GPL");
diff --git a/drivers/usb/misc/usbtest.c b/drivers/usb/misc/usbtest.c
index ff9a01f..bb10846 100644
--- a/drivers/usb/misc/usbtest.c
+++ b/drivers/usb/misc/usbtest.c
@@ -268,9 +268,9 @@
}
}
-static inline unsigned buffer_offset(void *buf)
+static inline unsigned long buffer_offset(void *buf)
{
- return (unsigned)buf & (ARCH_KMALLOC_MINALIGN - 1);
+ return (unsigned long)buf & (ARCH_KMALLOC_MINALIGN - 1);
}
static int check_guard_bytes(struct usbtest_dev *tdev, struct urb *urb)
@@ -329,7 +329,7 @@
static void simple_free_urb(struct urb *urb)
{
- unsigned offset = buffer_offset(urb->transfer_buffer);
+ unsigned long offset = buffer_offset(urb->transfer_buffer);
if (urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP)
usb_free_coherent(
@@ -1030,6 +1030,8 @@
req.wValue = cpu_to_le16((USB_DT_DEVICE << 8) | 0);
/* device descriptor size == 18 bytes */
len = udev->descriptor.bMaxPacketSize0;
+ if (udev->speed == USB_SPEED_SUPER)
+ len = 512;
switch (len) {
case 8:
len = 24;
@@ -1195,6 +1197,104 @@
/*-------------------------------------------------------------------------*/
+struct queued_ctx {
+ struct completion complete;
+ atomic_t pending;
+ unsigned num;
+ int status;
+ struct urb **urbs;
+};
+
+static void unlink_queued_callback(struct urb *urb)
+{
+ int status = urb->status;
+ struct queued_ctx *ctx = urb->context;
+
+ if (ctx->status)
+ goto done;
+ if (urb == ctx->urbs[ctx->num - 4] || urb == ctx->urbs[ctx->num - 2]) {
+ if (status == -ECONNRESET)
+ goto done;
+ /* What error should we report if the URB completed normally? */
+ }
+ if (status != 0)
+ ctx->status = status;
+
+ done:
+ if (atomic_dec_and_test(&ctx->pending))
+ complete(&ctx->complete);
+}
+
+static int unlink_queued(struct usbtest_dev *dev, int pipe, unsigned num,
+ unsigned size)
+{
+ struct queued_ctx ctx;
+ struct usb_device *udev = testdev_to_usbdev(dev);
+ void *buf;
+ dma_addr_t buf_dma;
+ int i;
+ int retval = -ENOMEM;
+
+ init_completion(&ctx.complete);
+ atomic_set(&ctx.pending, 1); /* One more than the actual value */
+ ctx.num = num;
+ ctx.status = 0;
+
+ buf = usb_alloc_coherent(udev, size, GFP_KERNEL, &buf_dma);
+ if (!buf)
+ return retval;
+ memset(buf, 0, size);
+
+ /* Allocate and init the urbs we'll queue */
+ ctx.urbs = kcalloc(num, sizeof(struct urb *), GFP_KERNEL);
+ if (!ctx.urbs)
+ goto free_buf;
+ for (i = 0; i < num; i++) {
+ ctx.urbs[i] = usb_alloc_urb(0, GFP_KERNEL);
+ if (!ctx.urbs[i])
+ goto free_urbs;
+ usb_fill_bulk_urb(ctx.urbs[i], udev, pipe, buf, size,
+ unlink_queued_callback, &ctx);
+ ctx.urbs[i]->transfer_dma = buf_dma;
+ ctx.urbs[i]->transfer_flags = URB_NO_TRANSFER_DMA_MAP;
+ }
+
+ /* Submit all the URBs and then unlink URBs num - 4 and num - 2. */
+ for (i = 0; i < num; i++) {
+ atomic_inc(&ctx.pending);
+ retval = usb_submit_urb(ctx.urbs[i], GFP_KERNEL);
+ if (retval != 0) {
+ dev_err(&dev->intf->dev, "submit urbs[%d] fail %d\n",
+ i, retval);
+ atomic_dec(&ctx.pending);
+ ctx.status = retval;
+ break;
+ }
+ }
+ if (i == num) {
+ usb_unlink_urb(ctx.urbs[num - 4]);
+ usb_unlink_urb(ctx.urbs[num - 2]);
+ } else {
+ while (--i >= 0)
+ usb_unlink_urb(ctx.urbs[i]);
+ }
+
+ if (atomic_dec_and_test(&ctx.pending)) /* The extra count */
+ complete(&ctx.complete);
+ wait_for_completion(&ctx.complete);
+ retval = ctx.status;
+
+ free_urbs:
+ for (i = 0; i < num; i++)
+ usb_free_urb(ctx.urbs[i]);
+ kfree(ctx.urbs);
+ free_buf:
+ usb_free_coherent(udev, size, buf, buf_dma);
+ return retval;
+}
+
+/*-------------------------------------------------------------------------*/
+
static int verify_not_halted(struct usbtest_dev *tdev, int ep, struct urb *urb)
{
int retval;
@@ -1970,8 +2070,6 @@
dev->in_iso_pipe, dev->iso_in, 0);
break;
- /* FIXME unlink from queue (ring with N urbs) */
-
/* FIXME scatterlist cancel (needs helper thread) */
/* Tests for bulk I/O using DMA mapping by core and odd address */
@@ -2064,6 +2162,26 @@
dev->in_iso_pipe, dev->iso_in, 1);
break;
+ /* unlink URBs from a bulk-OUT queue */
+ case 24:
+ if (dev->out_pipe == 0 || !param->length || param->sglen < 4)
+ break;
+ retval = 0;
+ dev_info(&intf->dev, "TEST 17: unlink from %d queues of "
+ "%d %d-byte writes\n",
+ param->iterations, param->sglen, param->length);
+ for (i = param->iterations; retval == 0 && i > 0; --i) {
+ retval = unlink_queued(dev, dev->out_pipe,
+ param->sglen, param->length);
+ if (retval) {
+ dev_err(&intf->dev,
+ "unlink queued writes failed %d, "
+ "iterations left %d\n", retval, i);
+ break;
+ }
+ }
+ break;
+
}
do_gettimeofday(¶m->duration);
param->duration.tv_sec -= start.tv_sec;
@@ -2192,6 +2310,9 @@
case USB_SPEED_HIGH:
tmp = "high";
break;
+ case USB_SPEED_SUPER:
+ tmp = "super";
+ break;
default:
tmp = "unknown";
break;
diff --git a/drivers/usb/musb/Kconfig b/drivers/usb/musb/Kconfig
index 74073b3..1309348 100644
--- a/drivers/usb/musb/Kconfig
+++ b/drivers/usb/musb/Kconfig
@@ -14,7 +14,7 @@
select TWL4030_USB if MACH_OMAP_3430SDP
select TWL6030_USB if MACH_OMAP_4430SDP || MACH_OMAP4_PANDA
select USB_OTG_UTILS
- bool 'Inventra Highspeed Dual Role Controller (TI, ADI, ...)'
+ tristate 'Inventra Highspeed Dual Role Controller (TI, ADI, ...)'
help
Say Y here if your system has a dual role high speed USB
controller based on the Mentor Graphics silicon IP. Then
@@ -30,39 +30,39 @@
If you do not know what this is, please say N.
-# To compile this driver as a module, choose M here; the
-# module will be called "musb-hdrc".
+ To compile this driver as a module, choose M here; the
+ module will be called "musb-hdrc".
choice
prompt "Platform Glue Layer"
depends on USB_MUSB_HDRC
config USB_MUSB_DAVINCI
- bool "DaVinci"
+ tristate "DaVinci"
depends on ARCH_DAVINCI_DMx
config USB_MUSB_DA8XX
- bool "DA8xx/OMAP-L1x"
+ tristate "DA8xx/OMAP-L1x"
depends on ARCH_DAVINCI_DA8XX
config USB_MUSB_TUSB6010
- bool "TUSB6010"
+ tristate "TUSB6010"
depends on ARCH_OMAP
config USB_MUSB_OMAP2PLUS
- bool "OMAP2430 and onwards"
+ tristate "OMAP2430 and onwards"
depends on ARCH_OMAP2PLUS
config USB_MUSB_AM35X
- bool "AM35x"
+ tristate "AM35x"
depends on ARCH_OMAP
config USB_MUSB_BLACKFIN
- bool "Blackfin"
+ tristate "Blackfin"
depends on (BF54x && !BF544) || (BF52x && ! BF522 && !BF523)
config USB_MUSB_UX500
- bool "U8500 and U5500"
+ tristate "U8500 and U5500"
depends on (ARCH_U8500 && AB8500_USB) || (ARCH_U5500)
endchoice
@@ -153,6 +153,13 @@
you can still disable it at run time using the "use_dma=n" module
parameter.
+config USB_UX500_DMA
+ bool
+ depends on USB_MUSB_HDRC && !MUSB_PIO_ONLY
+ default USB_MUSB_UX500
+ help
+ Enable DMA transfers on UX500 platforms.
+
config USB_INVENTRA_DMA
bool
depends on USB_MUSB_HDRC && !MUSB_PIO_ONLY
@@ -176,11 +183,3 @@
help
Enable DMA transfers on TUSB 6010 when OMAP DMA is available.
-config USB_MUSB_DEBUG
- depends on USB_MUSB_HDRC
- bool "Enable debugging messages"
- default n
- help
- This enables musb debugging. To set the logging level use the debug
- module parameter. Starting at level 3, per-transfer (urb, usb_request,
- packet, or dma transfer) tracing may kick in.
diff --git a/drivers/usb/musb/Makefile b/drivers/usb/musb/Makefile
index 74df528..c4d228b 100644
--- a/drivers/usb/musb/Makefile
+++ b/drivers/usb/musb/Makefile
@@ -2,8 +2,6 @@
# for USB OTG silicon based on Mentor Graphics INVENTRA designs
#
-ccflags-$(CONFIG_USB_MUSB_DEBUG) := -DDEBUG
-
obj-$(CONFIG_USB_MUSB_HDRC) += musb_hdrc.o
musb_hdrc-y := musb_core.o
@@ -39,6 +37,11 @@
ifeq ($(CONFIG_USB_TUSB_OMAP_DMA),y)
musb_hdrc-y += tusb6010_omap.o
+ else
+ ifeq ($(CONFIG_USB_UX500_DMA),y)
+ musb_hdrc-y += ux500_dma.o
+
+ endif
endif
endif
endif
diff --git a/drivers/usb/musb/am35x.c b/drivers/usb/musb/am35x.c
index d5a3da3..23ac28f 100644
--- a/drivers/usb/musb/am35x.c
+++ b/drivers/usb/musb/am35x.c
@@ -151,7 +151,8 @@
* status change events (from the transceiver) otherwise.
*/
devctl = musb_readb(mregs, MUSB_DEVCTL);
- DBG(7, "Poll devctl %02x (%s)\n", devctl, otg_state_string(musb));
+ dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
+ otg_state_string(musb->xceiv->state));
spin_lock_irqsave(&musb->lock, flags);
switch (musb->xceiv->state) {
@@ -202,20 +203,22 @@
/* Never idle if active, or when VBUS timeout is not set as host */
if (musb->is_active || (musb->a_wait_bcon == 0 &&
musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
- DBG(4, "%s active, deleting timer\n", otg_state_string(musb));
+ dev_dbg(musb->controller, "%s active, deleting timer\n",
+ otg_state_string(musb->xceiv->state));
del_timer(&otg_workaround);
last_timer = jiffies;
return;
}
if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) {
- DBG(4, "Longer idle timer already pending, ignoring...\n");
+ dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n");
return;
}
last_timer = timeout;
- DBG(4, "%s inactive, starting idle timer for %u ms\n",
- otg_state_string(musb), jiffies_to_msecs(timeout - jiffies));
+ dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
+ otg_state_string(musb->xceiv->state),
+ jiffies_to_msecs(timeout - jiffies));
mod_timer(&otg_workaround, timeout);
}
@@ -302,9 +305,9 @@
}
/* NOTE: this must complete power-on within 100 ms. */
- DBG(2, "VBUS %s (%s)%s, devctl %02x\n",
+ dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
drvvbus ? "on" : "off",
- otg_state_string(musb),
+ otg_state_string(musb->xceiv->state),
err ? " ERROR" : "",
devctl);
ret = IRQ_HANDLED;
diff --git a/drivers/usb/musb/blackfin.c b/drivers/usb/musb/blackfin.c
index 8e2a1ff..ae8c396 100644
--- a/drivers/usb/musb/blackfin.c
+++ b/drivers/usb/musb/blackfin.c
@@ -35,6 +35,7 @@
*/
void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
{
+ struct musb *musb = hw_ep->musb;
void __iomem *fifo = hw_ep->fifo;
void __iomem *epio = hw_ep->regs;
u8 epnum = hw_ep->epnum;
@@ -43,7 +44,7 @@
musb_writew(epio, MUSB_TXCOUNT, len);
- DBG(4, "TX ep%d fifo %p count %d buf %p, epio %p\n",
+ dev_dbg(musb->controller, "TX ep%d fifo %p count %d buf %p, epio %p\n",
hw_ep->epnum, fifo, len, src, epio);
dump_fifo_data(src, len);
@@ -98,6 +99,7 @@
*/
void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
{
+ struct musb *musb = hw_ep->musb;
void __iomem *fifo = hw_ep->fifo;
u8 epnum = hw_ep->epnum;
@@ -154,7 +156,7 @@
*(dst + len - 1) = (u8)inw((unsigned long)fifo + 4);
}
}
- DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
+ dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
'R', hw_ep->epnum, fifo, len, dst);
dump_fifo_data(dst, len);
@@ -279,12 +281,14 @@
}
break;
default:
- DBG(1, "%s state not handled\n", otg_state_string(musb));
+ dev_dbg(musb->controller, "%s state not handled\n",
+ otg_state_string(musb->xceiv->state));
break;
}
spin_unlock_irqrestore(&musb->lock, flags);
- DBG(4, "state is %s\n", otg_state_string(musb));
+ dev_dbg(musb->controller, "state is %s\n",
+ otg_state_string(musb->xceiv->state));
}
static void bfin_musb_enable(struct musb *musb)
@@ -306,9 +310,9 @@
value = !value;
gpio_set_value(musb->config->gpio_vrsel, value);
- DBG(1, "VBUS %s, devctl %02x "
+ dev_dbg(musb->controller, "VBUS %s, devctl %02x "
/* otg %3x conf %08x prcm %08x */ "\n",
- otg_state_string(musb),
+ otg_state_string(musb->xceiv->state),
musb_readb(musb->mregs, MUSB_DEVCTL));
}
diff --git a/drivers/usb/musb/cppi_dma.c b/drivers/usb/musb/cppi_dma.c
index ab434fb..149f3f3 100644
--- a/drivers/usb/musb/cppi_dma.c
+++ b/drivers/usb/musb/cppi_dma.c
@@ -236,7 +236,7 @@
musb_writel(tibase, DAVINCI_RXCPPI_INTCLR_REG,
DAVINCI_DMA_ALL_CHANNELS_ENABLE);
- DBG(1, "Tearing down RX and TX Channels\n");
+ dev_dbg(musb->controller, "Tearing down RX and TX Channels\n");
for (i = 0; i < ARRAY_SIZE(controller->tx); i++) {
/* FIXME restructure of txdma to use bds like rxdma */
controller->tx[i].last_processed = NULL;
@@ -301,13 +301,13 @@
*/
if (transmit) {
if (index >= ARRAY_SIZE(controller->tx)) {
- DBG(1, "no %cX%d CPPI channel\n", 'T', index);
+ dev_dbg(musb->controller, "no %cX%d CPPI channel\n", 'T', index);
return NULL;
}
cppi_ch = controller->tx + index;
} else {
if (index >= ARRAY_SIZE(controller->rx)) {
- DBG(1, "no %cX%d CPPI channel\n", 'R', index);
+ dev_dbg(musb->controller, "no %cX%d CPPI channel\n", 'R', index);
return NULL;
}
cppi_ch = controller->rx + index;
@@ -318,13 +318,13 @@
* with the other DMA engine too
*/
if (cppi_ch->hw_ep)
- DBG(1, "re-allocating DMA%d %cX channel %p\n",
+ dev_dbg(musb->controller, "re-allocating DMA%d %cX channel %p\n",
index, transmit ? 'T' : 'R', cppi_ch);
cppi_ch->hw_ep = ep;
cppi_ch->channel.status = MUSB_DMA_STATUS_FREE;
cppi_ch->channel.max_len = 0x7fffffff;
- DBG(4, "Allocate CPPI%d %cX\n", index, transmit ? 'T' : 'R');
+ dev_dbg(musb->controller, "Allocate CPPI%d %cX\n", index, transmit ? 'T' : 'R');
return &cppi_ch->channel;
}
@@ -339,7 +339,7 @@
c = container_of(channel, struct cppi_channel, channel);
tibase = c->controller->tibase;
if (!c->hw_ep)
- DBG(1, "releasing idle DMA channel %p\n", c);
+ dev_dbg(musb->controller, "releasing idle DMA channel %p\n", c);
else if (!c->transmit)
core_rxirq_enable(tibase, c->index + 1);
@@ -597,7 +597,7 @@
length = min(n_bds * maxpacket, length);
}
- DBG(4, "TX DMA%d, pktSz %d %s bds %d dma 0x%llx len %u\n",
+ dev_dbg(musb->controller, "TX DMA%d, pktSz %d %s bds %d dma 0x%llx len %u\n",
tx->index,
maxpacket,
rndis ? "rndis" : "transparent",
@@ -654,7 +654,7 @@
bd->hw_options |= CPPI_ZERO_SET;
}
- DBG(5, "TXBD %p: nxt %08x buf %08x len %04x opt %08x\n",
+ dev_dbg(musb->controller, "TXBD %p: nxt %08x buf %08x len %04x opt %08x\n",
bd, bd->hw_next, bd->hw_bufp,
bd->hw_off_len, bd->hw_options);
@@ -819,7 +819,7 @@
length = min(n_bds * maxpacket, length);
- DBG(4, "RX DMA%d seg, maxp %d %s bds %d (cnt %d) "
+ dev_dbg(musb->controller, "RX DMA%d seg, maxp %d %s bds %d (cnt %d) "
"dma 0x%llx len %u %u/%u\n",
rx->index, maxpacket,
onepacket
@@ -936,7 +936,7 @@
DAVINCI_RXCPPI_BUFCNT0_REG + (rx->index * 4))
& 0xffff;
if (i < (2 + n_bds)) {
- DBG(2, "bufcnt%d underrun - %d (for %d)\n",
+ dev_dbg(musb->controller, "bufcnt%d underrun - %d (for %d)\n",
rx->index, i, n_bds);
musb_writel(tibase,
DAVINCI_RXCPPI_BUFCNT0_REG + (rx->index * 4),
@@ -985,7 +985,7 @@
/* WARN_ON(1); */
break;
case MUSB_DMA_STATUS_UNKNOWN:
- DBG(1, "%cX DMA%d not allocated!\n",
+ dev_dbg(musb->controller, "%cX DMA%d not allocated!\n",
cppi_ch->transmit ? 'T' : 'R',
cppi_ch->index);
/* FALLTHROUGH */
@@ -1040,7 +1040,7 @@
if (!completed && (bd->hw_options & CPPI_OWN_SET))
break;
- DBG(5, "C/RXBD %llx: nxt %08x buf %08x "
+ dev_dbg(musb->controller, "C/RXBD %llx: nxt %08x buf %08x "
"off.len %08x opt.len %08x (%d)\n",
(unsigned long long)bd->dma, bd->hw_next, bd->hw_bufp,
bd->hw_off_len, bd->hw_options,
@@ -1062,7 +1062,7 @@
* CPPI ignores those BDs even though OWN is still set.
*/
completed = true;
- DBG(3, "rx short %d/%d (%d)\n",
+ dev_dbg(musb->controller, "rx short %d/%d (%d)\n",
len, bd->buflen,
rx->channel.actual_len);
}
@@ -1112,7 +1112,7 @@
musb_ep_select(cppi->mregs, rx->index + 1);
csr = musb_readw(regs, MUSB_RXCSR);
if (csr & MUSB_RXCSR_DMAENAB) {
- DBG(4, "list%d %p/%p, last %llx%s, csr %04x\n",
+ dev_dbg(musb->controller, "list%d %p/%p, last %llx%s, csr %04x\n",
rx->index,
rx->head, rx->tail,
rx->last_processed
@@ -1175,7 +1175,7 @@
return IRQ_NONE;
}
- DBG(4, "CPPI IRQ Tx%x Rx%x\n", tx, rx);
+ dev_dbg(musb->controller, "CPPI IRQ Tx%x Rx%x\n", tx, rx);
/* process TX channels */
for (index = 0; tx; tx = tx >> 1, index++) {
@@ -1203,7 +1203,7 @@
* that needs to be acknowledged.
*/
if (NULL == bd) {
- DBG(1, "null BD\n");
+ dev_dbg(musb->controller, "null BD\n");
musb_writel(&tx_ram->tx_complete, 0, 0);
continue;
}
@@ -1218,7 +1218,7 @@
if (bd->hw_options & CPPI_OWN_SET)
break;
- DBG(5, "C/TXBD %p n %x b %x off %x opt %x\n",
+ dev_dbg(musb->controller, "C/TXBD %p n %x b %x off %x opt %x\n",
bd, bd->hw_next, bd->hw_bufp,
bd->hw_off_len, bd->hw_options);
diff --git a/drivers/usb/musb/da8xx.c b/drivers/usb/musb/da8xx.c
index 69a0da3..662ed34 100644
--- a/drivers/usb/musb/da8xx.c
+++ b/drivers/usb/musb/da8xx.c
@@ -199,7 +199,8 @@
* status change events (from the transceiver) otherwise.
*/
devctl = musb_readb(mregs, MUSB_DEVCTL);
- DBG(7, "Poll devctl %02x (%s)\n", devctl, otg_state_string(musb));
+ dev_dbg(musb->controller, "Poll devctl %02x (%s)\n", devctl,
+ otg_state_string(musb->xceiv->state));
spin_lock_irqsave(&musb->lock, flags);
switch (musb->xceiv->state) {
@@ -273,20 +274,22 @@
/* Never idle if active, or when VBUS timeout is not set as host */
if (musb->is_active || (musb->a_wait_bcon == 0 &&
musb->xceiv->state == OTG_STATE_A_WAIT_BCON)) {
- DBG(4, "%s active, deleting timer\n", otg_state_string(musb));
+ dev_dbg(musb->controller, "%s active, deleting timer\n",
+ otg_state_string(musb->xceiv->state));
del_timer(&otg_workaround);
last_timer = jiffies;
return;
}
if (time_after(last_timer, timeout) && timer_pending(&otg_workaround)) {
- DBG(4, "Longer idle timer already pending, ignoring...\n");
+ dev_dbg(musb->controller, "Longer idle timer already pending, ignoring...\n");
return;
}
last_timer = timeout;
- DBG(4, "%s inactive, starting idle timer for %u ms\n",
- otg_state_string(musb), jiffies_to_msecs(timeout - jiffies));
+ dev_dbg(musb->controller, "%s inactive, starting idle timer for %u ms\n",
+ otg_state_string(musb->xceiv->state),
+ jiffies_to_msecs(timeout - jiffies));
mod_timer(&otg_workaround, timeout);
}
@@ -311,7 +314,7 @@
goto eoi;
musb_writel(reg_base, DA8XX_USB_INTR_SRC_CLEAR_REG, status);
- DBG(4, "USB IRQ %08x\n", status);
+ dev_dbg(musb->controller, "USB IRQ %08x\n", status);
musb->int_rx = (status & DA8XX_INTR_RX_MASK) >> DA8XX_INTR_RX_SHIFT;
musb->int_tx = (status & DA8XX_INTR_TX_MASK) >> DA8XX_INTR_TX_SHIFT;
@@ -363,9 +366,9 @@
portstate(musb->port1_status &= ~USB_PORT_STAT_POWER);
}
- DBG(2, "VBUS %s (%s)%s, devctl %02x\n",
+ dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
drvvbus ? "on" : "off",
- otg_state_string(musb),
+ otg_state_string(musb->xceiv->state),
err ? " ERROR" : "",
devctl);
ret = IRQ_HANDLED;
@@ -410,7 +413,7 @@
break;
#endif
default:
- DBG(2, "Trying to set unsupported mode %u\n", musb_mode);
+ dev_dbg(musb->controller, "Trying to set unsupported mode %u\n", musb_mode);
}
__raw_writel(cfgchip2, CFGCHIP2);
diff --git a/drivers/usb/musb/davinci.c b/drivers/usb/musb/davinci.c
index e6de097..2a2adf6 100644
--- a/drivers/usb/musb/davinci.c
+++ b/drivers/usb/musb/davinci.c
@@ -220,7 +220,8 @@
* status change events (from the transceiver) otherwise.
*/
devctl = musb_readb(mregs, MUSB_DEVCTL);
- DBG(7, "poll devctl %02x (%s)\n", devctl, otg_state_string(musb));
+ dev_dbg(musb->controller, "poll devctl %02x (%s)\n", devctl,
+ otg_state_string(musb->xceiv->state));
spin_lock_irqsave(&musb->lock, flags);
switch (musb->xceiv->state) {
@@ -297,7 +298,7 @@
/* ack and handle non-CPPI interrupts */
tmp = musb_readl(tibase, DAVINCI_USB_INT_SRC_MASKED_REG);
musb_writel(tibase, DAVINCI_USB_INT_SRC_CLR_REG, tmp);
- DBG(4, "IRQ %08x\n", tmp);
+ dev_dbg(musb->controller, "IRQ %08x\n", tmp);
musb->int_rx = (tmp & DAVINCI_USB_RXINT_MASK)
>> DAVINCI_USB_RXINT_SHIFT;
@@ -354,9 +355,9 @@
* (OTG_TIME_A_WAIT_VRISE) but we don't check for that.
*/
davinci_musb_source_power(musb, drvvbus, 0);
- DBG(2, "VBUS %s (%s)%s, devctl %02x\n",
+ dev_dbg(musb->controller, "VBUS %s (%s)%s, devctl %02x\n",
drvvbus ? "on" : "off",
- otg_state_string(musb),
+ otg_state_string(musb->xceiv->state),
err ? " ERROR" : "",
devctl);
retval = IRQ_HANDLED;
@@ -484,7 +485,7 @@
break;
if ((devctl & MUSB_DEVCTL_VBUS) != warn) {
warn = devctl & MUSB_DEVCTL_VBUS;
- DBG(1, "VBUS %d\n",
+ dev_dbg(musb->controller, "VBUS %d\n",
warn >> MUSB_DEVCTL_VBUS_SHIFT);
}
msleep(1000);
@@ -493,7 +494,7 @@
/* in OTG mode, another host might be connected */
if (devctl & MUSB_DEVCTL_VBUS)
- DBG(1, "VBUS off timeout (devctl %02x)\n", devctl);
+ dev_dbg(musb->controller, "VBUS off timeout (devctl %02x)\n", devctl);
}
phy_off();
diff --git a/drivers/usb/musb/musb_core.c b/drivers/usb/musb/musb_core.c
index f10ff00..ab8e100 100644
--- a/drivers/usb/musb/musb_core.c
+++ b/drivers/usb/musb/musb_core.c
@@ -104,10 +104,6 @@
#define TA_WAIT_BCON(m) max_t(int, (m)->a_wait_bcon, OTG_TIME_A_WAIT_BCON)
-unsigned musb_debug;
-module_param_named(debug, musb_debug, uint, S_IRUGO | S_IWUSR);
-MODULE_PARM_DESC(debug, "Debug message level. Default = 0");
-
#define DRIVER_AUTHOR "Mentor Graphics, Texas Instruments, Nokia"
#define DRIVER_DESC "Inventra Dual-Role USB Controller Driver"
@@ -157,10 +153,8 @@
while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
& MUSB_ULPI_REG_CMPLT)) {
i++;
- if (i == 10000) {
- DBG(3, "ULPI read timed out\n");
+ if (i == 10000)
return -ETIMEDOUT;
- }
}
r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
@@ -190,10 +184,8 @@
while (!(musb_readb(addr, MUSB_ULPI_REG_CONTROL)
& MUSB_ULPI_REG_CMPLT)) {
i++;
- if (i == 10000) {
- DBG(3, "ULPI write timed out\n");
+ if (i == 10000)
return -ETIMEDOUT;
- }
}
r = musb_readb(addr, MUSB_ULPI_REG_CONTROL);
@@ -221,11 +213,12 @@
*/
void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
{
+ struct musb *musb = hw_ep->musb;
void __iomem *fifo = hw_ep->fifo;
prefetch((u8 *)src);
- DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
+ dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
'T', hw_ep->epnum, fifo, len, src);
/* we can't assume unaligned reads work */
@@ -262,9 +255,10 @@
*/
void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
{
+ struct musb *musb = hw_ep->musb;
void __iomem *fifo = hw_ep->fifo;
- DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
+ dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
'R', hw_ep->epnum, fifo, len, dst);
/* we can't assume unaligned writes work */
@@ -333,26 +327,6 @@
/*-------------------------------------------------------------------------*/
-const char *otg_state_string(struct musb *musb)
-{
- switch (musb->xceiv->state) {
- case OTG_STATE_A_IDLE: return "a_idle";
- case OTG_STATE_A_WAIT_VRISE: return "a_wait_vrise";
- case OTG_STATE_A_WAIT_BCON: return "a_wait_bcon";
- case OTG_STATE_A_HOST: return "a_host";
- case OTG_STATE_A_SUSPEND: return "a_suspend";
- case OTG_STATE_A_PERIPHERAL: return "a_peripheral";
- case OTG_STATE_A_WAIT_VFALL: return "a_wait_vfall";
- case OTG_STATE_A_VBUS_ERR: return "a_vbus_err";
- case OTG_STATE_B_IDLE: return "b_idle";
- case OTG_STATE_B_SRP_INIT: return "b_srp_init";
- case OTG_STATE_B_PERIPHERAL: return "b_peripheral";
- case OTG_STATE_B_WAIT_ACON: return "b_wait_acon";
- case OTG_STATE_B_HOST: return "b_host";
- default: return "UNDEFINED";
- }
-}
-
#ifdef CONFIG_USB_MUSB_OTG
/*
@@ -366,19 +340,21 @@
spin_lock_irqsave(&musb->lock, flags);
switch (musb->xceiv->state) {
case OTG_STATE_B_WAIT_ACON:
- DBG(1, "HNP: b_wait_acon timeout; back to b_peripheral\n");
+ dev_dbg(musb->controller, "HNP: b_wait_acon timeout; back to b_peripheral\n");
musb_g_disconnect(musb);
musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
musb->is_active = 0;
break;
case OTG_STATE_A_SUSPEND:
case OTG_STATE_A_WAIT_BCON:
- DBG(1, "HNP: %s timeout\n", otg_state_string(musb));
+ dev_dbg(musb->controller, "HNP: %s timeout\n",
+ otg_state_string(musb->xceiv->state));
musb_platform_set_vbus(musb, 0);
musb->xceiv->state = OTG_STATE_A_WAIT_VFALL;
break;
default:
- DBG(1, "HNP: Unhandled mode %s\n", otg_state_string(musb));
+ dev_dbg(musb->controller, "HNP: Unhandled mode %s\n",
+ otg_state_string(musb->xceiv->state));
}
musb->ignore_disconnect = 0;
spin_unlock_irqrestore(&musb->lock, flags);
@@ -393,15 +369,16 @@
void __iomem *mbase = musb->mregs;
u8 reg;
- DBG(1, "HNP: stop from %s\n", otg_state_string(musb));
+ dev_dbg(musb->controller, "HNP: stop from %s\n", otg_state_string(musb->xceiv->state));
switch (musb->xceiv->state) {
case OTG_STATE_A_PERIPHERAL:
musb_g_disconnect(musb);
- DBG(1, "HNP: back to %s\n", otg_state_string(musb));
+ dev_dbg(musb->controller, "HNP: back to %s\n",
+ otg_state_string(musb->xceiv->state));
break;
case OTG_STATE_B_HOST:
- DBG(1, "HNP: Disabling HR\n");
+ dev_dbg(musb->controller, "HNP: Disabling HR\n");
hcd->self.is_b_host = 0;
musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
MUSB_DEV_MODE(musb);
@@ -411,8 +388,8 @@
/* REVISIT: Start SESSION_REQUEST here? */
break;
default:
- DBG(1, "HNP: Stopping in unknown state %s\n",
- otg_state_string(musb));
+ dev_dbg(musb->controller, "HNP: Stopping in unknown state %s\n",
+ otg_state_string(musb->xceiv->state));
}
/*
@@ -442,7 +419,7 @@
{
irqreturn_t handled = IRQ_NONE;
- DBG(3, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl,
+ dev_dbg(musb->controller, "<== Power=%02x, DevCtl=%02x, int_usb=0x%x\n", power, devctl,
int_usb);
/* in host mode, the peripheral may issue remote wakeup.
@@ -451,7 +428,7 @@
*/
if (int_usb & MUSB_INTR_RESUME) {
handled = IRQ_HANDLED;
- DBG(3, "RESUME (%s)\n", otg_state_string(musb));
+ dev_dbg(musb->controller, "RESUME (%s)\n", otg_state_string(musb->xceiv->state));
if (devctl & MUSB_DEVCTL_HM) {
#ifdef CONFIG_USB_MUSB_HDRC_HCD
@@ -466,7 +443,7 @@
if (power & MUSB_POWER_SUSPENDM) {
/* spurious */
musb->int_usb &= ~MUSB_INTR_SUSPEND;
- DBG(2, "Spurious SUSPENDM\n");
+ dev_dbg(musb->controller, "Spurious SUSPENDM\n");
break;
}
@@ -492,7 +469,7 @@
default:
WARNING("bogus %s RESUME (%s)\n",
"host",
- otg_state_string(musb));
+ otg_state_string(musb->xceiv->state));
}
#endif
} else {
@@ -526,7 +503,7 @@
default:
WARNING("bogus %s RESUME (%s)\n",
"peripheral",
- otg_state_string(musb));
+ otg_state_string(musb->xceiv->state));
}
}
}
@@ -538,11 +515,12 @@
if ((devctl & MUSB_DEVCTL_VBUS) == MUSB_DEVCTL_VBUS
&& (devctl & MUSB_DEVCTL_BDEVICE)) {
- DBG(3, "SessReq while on B state\n");
+ dev_dbg(musb->controller, "SessReq while on B state\n");
return IRQ_HANDLED;
}
- DBG(1, "SESSION_REQUEST (%s)\n", otg_state_string(musb));
+ dev_dbg(musb->controller, "SESSION_REQUEST (%s)\n",
+ otg_state_string(musb->xceiv->state));
/* IRQ arrives from ID pin sense or (later, if VBUS power
* is removed) SRP. responses are time critical:
@@ -606,8 +584,8 @@
break;
}
- DBG(1, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
- otg_state_string(musb),
+ dev_dbg(musb->controller, "VBUS_ERROR in %s (%02x, %s), retry #%d, port1 %08x\n",
+ otg_state_string(musb->xceiv->state),
devctl,
({ char *s;
switch (devctl & MUSB_DEVCTL_VBUS) {
@@ -632,8 +610,8 @@
#endif
if (int_usb & MUSB_INTR_SUSPEND) {
- DBG(1, "SUSPEND (%s) devctl %02x power %02x\n",
- otg_state_string(musb), devctl, power);
+ dev_dbg(musb->controller, "SUSPEND (%s) devctl %02x power %02x\n",
+ otg_state_string(musb->xceiv->state), devctl, power);
handled = IRQ_HANDLED;
switch (musb->xceiv->state) {
@@ -665,7 +643,7 @@
if (musb->is_active) {
#ifdef CONFIG_USB_MUSB_OTG
musb->xceiv->state = OTG_STATE_B_WAIT_ACON;
- DBG(1, "HNP: Setting timer for b_ase0_brst\n");
+ dev_dbg(musb->controller, "HNP: Setting timer for b_ase0_brst\n");
mod_timer(&musb->otg_timer, jiffies
+ msecs_to_jiffies(
OTG_TIME_B_ASE0_BRST));
@@ -684,7 +662,7 @@
break;
case OTG_STATE_B_HOST:
/* Transition to B_PERIPHERAL, see 6.8.2.6 p 44 */
- DBG(1, "REVISIT: SUSPEND as B_HOST\n");
+ dev_dbg(musb->controller, "REVISIT: SUSPEND as B_HOST\n");
break;
default:
/* "should not happen" */
@@ -727,14 +705,14 @@
switch (musb->xceiv->state) {
case OTG_STATE_B_PERIPHERAL:
if (int_usb & MUSB_INTR_SUSPEND) {
- DBG(1, "HNP: SUSPEND+CONNECT, now b_host\n");
+ dev_dbg(musb->controller, "HNP: SUSPEND+CONNECT, now b_host\n");
int_usb &= ~MUSB_INTR_SUSPEND;
goto b_host;
} else
- DBG(1, "CONNECT as b_peripheral???\n");
+ dev_dbg(musb->controller, "CONNECT as b_peripheral???\n");
break;
case OTG_STATE_B_WAIT_ACON:
- DBG(1, "HNP: CONNECT, now b_host\n");
+ dev_dbg(musb->controller, "HNP: CONNECT, now b_host\n");
b_host:
musb->xceiv->state = OTG_STATE_B_HOST;
hcd->self.is_b_host = 1;
@@ -757,14 +735,14 @@
else
usb_hcd_resume_root_hub(hcd);
- DBG(1, "CONNECT (%s) devctl %02x\n",
- otg_state_string(musb), devctl);
+ dev_dbg(musb->controller, "CONNECT (%s) devctl %02x\n",
+ otg_state_string(musb->xceiv->state), devctl);
}
#endif /* CONFIG_USB_MUSB_HDRC_HCD */
if ((int_usb & MUSB_INTR_DISCONNECT) && !musb->ignore_disconnect) {
- DBG(1, "DISCONNECT (%s) as %s, devctl %02x\n",
- otg_state_string(musb),
+ dev_dbg(musb->controller, "DISCONNECT (%s) as %s, devctl %02x\n",
+ otg_state_string(musb->xceiv->state),
MUSB_MODE(musb), devctl);
handled = IRQ_HANDLED;
@@ -807,7 +785,7 @@
#endif /* GADGET */
default:
WARNING("unhandled DISCONNECT transition (%s)\n",
- otg_state_string(musb));
+ otg_state_string(musb->xceiv->state));
break;
}
}
@@ -826,13 +804,14 @@
* stop the session.
*/
if (devctl & (MUSB_DEVCTL_FSDEV | MUSB_DEVCTL_LSDEV))
- DBG(1, "BABBLE devctl: %02x\n", devctl);
+ dev_dbg(musb->controller, "BABBLE devctl: %02x\n", devctl);
else {
ERR("Stopping host session -- babble\n");
musb_writeb(musb->mregs, MUSB_DEVCTL, 0);
}
} else if (is_peripheral_capable()) {
- DBG(1, "BUS RESET as %s\n", otg_state_string(musb));
+ dev_dbg(musb->controller, "BUS RESET as %s\n",
+ otg_state_string(musb->xceiv->state));
switch (musb->xceiv->state) {
#ifdef CONFIG_USB_OTG
case OTG_STATE_A_SUSPEND:
@@ -845,9 +824,9 @@
/* FALLTHROUGH */
case OTG_STATE_A_WAIT_BCON: /* OPT TD.4.7-900ms */
/* never use invalid T(a_wait_bcon) */
- DBG(1, "HNP: in %s, %d msec timeout\n",
- otg_state_string(musb),
- TA_WAIT_BCON(musb));
+ dev_dbg(musb->controller, "HNP: in %s, %d msec timeout\n",
+ otg_state_string(musb->xceiv->state),
+ TA_WAIT_BCON(musb));
mod_timer(&musb->otg_timer, jiffies
+ msecs_to_jiffies(TA_WAIT_BCON(musb)));
break;
@@ -857,8 +836,8 @@
musb_g_reset(musb);
break;
case OTG_STATE_B_WAIT_ACON:
- DBG(1, "HNP: RESET (%s), to b_peripheral\n",
- otg_state_string(musb));
+ dev_dbg(musb->controller, "HNP: RESET (%s), to b_peripheral\n",
+ otg_state_string(musb->xceiv->state));
musb->xceiv->state = OTG_STATE_B_PERIPHERAL;
musb_g_reset(musb);
break;
@@ -870,8 +849,8 @@
musb_g_reset(musb);
break;
default:
- DBG(1, "Unhandled BUS RESET as %s\n",
- otg_state_string(musb));
+ dev_dbg(musb->controller, "Unhandled BUS RESET as %s\n",
+ otg_state_string(musb->xceiv->state));
}
}
}
@@ -894,7 +873,7 @@
u8 epnum;
u16 frame;
- DBG(6, "START_OF_FRAME\n");
+ dev_dbg(musb->controller, "START_OF_FRAME\n");
handled = IRQ_HANDLED;
/* start any periodic Tx transfers waiting for current frame */
@@ -936,7 +915,7 @@
void __iomem *regs = musb->mregs;
u8 devctl = musb_readb(regs, MUSB_DEVCTL);
- DBG(2, "<== devctl %02x\n", devctl);
+ dev_dbg(musb->controller, "<== devctl %02x\n", devctl);
/* Set INT enable registers, enable interrupts */
musb_writew(regs, MUSB_INTRTXE, musb->epmask);
@@ -1013,7 +992,7 @@
/* stop IRQs, timers, ... */
musb_platform_disable(musb);
musb_generic_disable(musb);
- DBG(3, "HDRC disabled\n");
+ dev_dbg(musb->controller, "HDRC disabled\n");
/* FIXME
* - mark host and/or peripheral drivers unusable/inactive
@@ -1359,7 +1338,7 @@
void *mbase = musb->mregs;
int ret = 0;
- DBG(2, "<== static silicon ep config\n");
+ dev_dbg(musb->controller, "<== static silicon ep config\n");
/* FIXME pick up ep0 maxpacket size */
@@ -1506,7 +1485,7 @@
#endif
if (hw_ep->max_packet_sz_tx) {
- DBG(1,
+ dev_dbg(musb->controller,
"%s: hw_ep %d%s, %smax %d\n",
musb_driver_name, i,
hw_ep->is_shared_fifo ? "shared" : "tx",
@@ -1515,7 +1494,7 @@
hw_ep->max_packet_sz_tx);
}
if (hw_ep->max_packet_sz_rx && !hw_ep->is_shared_fifo) {
- DBG(1,
+ dev_dbg(musb->controller,
"%s: hw_ep %d%s, %smax %d\n",
musb_driver_name, i,
"rx",
@@ -1524,7 +1503,7 @@
hw_ep->max_packet_sz_rx);
}
if (!(hw_ep->max_packet_sz_tx || hw_ep->max_packet_sz_rx))
- DBG(1, "hw_ep %d not configured\n", i);
+ dev_dbg(musb->controller, "hw_ep %d not configured\n", i);
}
return 0;
@@ -1577,14 +1556,14 @@
devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
power = musb_readb(musb->mregs, MUSB_POWER);
- DBG(4, "** IRQ %s usb%04x tx%04x rx%04x\n",
+ dev_dbg(musb->controller, "** IRQ %s usb%04x tx%04x rx%04x\n",
(devctl & MUSB_DEVCTL_HM) ? "host" : "peripheral",
musb->int_usb, musb->int_tx, musb->int_rx);
#ifdef CONFIG_USB_GADGET_MUSB_HDRC
if (is_otg_enabled(musb) || is_peripheral_enabled(musb))
if (!musb->gadget_driver) {
- DBG(5, "No gadget driver loaded\n");
+ dev_dbg(musb->controller, "No gadget driver loaded\n");
return IRQ_HANDLED;
}
#endif
@@ -1649,7 +1628,7 @@
return retval;
}
-
+EXPORT_SYMBOL_GPL(musb_interrupt);
#ifndef CONFIG_MUSB_PIO_ONLY
static int __initdata use_dma = 1;
@@ -1713,7 +1692,7 @@
int ret = -EINVAL;
spin_lock_irqsave(&musb->lock, flags);
- ret = sprintf(buf, "%s\n", otg_state_string(musb));
+ ret = sprintf(buf, "%s\n", otg_state_string(musb->xceiv->state));
spin_unlock_irqrestore(&musb->lock, flags);
return ret;
@@ -2075,7 +2054,7 @@
status = usb_add_hcd(musb_to_hcd(musb), -1, 0);
hcd->self.uses_pio_for_control = 1;
- DBG(1, "%s mode, status %d, devctl %02x %c\n",
+ dev_dbg(musb->controller, "%s mode, status %d, devctl %02x %c\n",
"HOST", status,
musb_readb(musb->mregs, MUSB_DEVCTL),
(musb_readb(musb->mregs, MUSB_DEVCTL)
@@ -2089,7 +2068,7 @@
status = musb_gadget_setup(musb);
- DBG(1, "%s mode, status %d, dev%02x\n",
+ dev_dbg(musb->controller, "%s mode, status %d, dev%02x\n",
is_otg_enabled(musb) ? "OTG" : "PERIPHERAL",
status,
musb_readb(musb->mregs, MUSB_DEVCTL));
@@ -2460,6 +2439,8 @@
"musb-dma"
#elif defined(CONFIG_USB_TUSB_OMAP_DMA)
"tusb-omap-dma"
+#elif defined(CONFIG_USB_UX500_DMA)
+ "ux500-dma"
#else
"?dma?"
#endif
@@ -2471,8 +2452,8 @@
#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
"host"
#endif
- ", debug=%d\n",
- musb_driver_name, musb_debug);
+ ,
+ musb_driver_name);
return platform_driver_probe(&musb_driver, musb_probe);
}
diff --git a/drivers/usb/musb/musb_debug.h b/drivers/usb/musb/musb_debug.h
index 94f6973..742eada 100644
--- a/drivers/usb/musb/musb_debug.h
+++ b/drivers/usb/musb/musb_debug.h
@@ -42,20 +42,6 @@
#define INFO(fmt, args...) yprintk(KERN_INFO, fmt, ## args)
#define ERR(fmt, args...) yprintk(KERN_ERR, fmt, ## args)
-#define DBG(level, format, args...) do { \
- if (_dbg_level(level)) \
- pr_debug("%s %d: " format, __func__, __LINE__, ## args); \
- } while (0)
-
-extern unsigned musb_debug;
-
-static inline int _dbg_level(unsigned l)
-{
- return musb_debug >= l;
-}
-
-extern const char *otg_state_string(struct musb *);
-
#ifdef CONFIG_DEBUG_FS
extern int musb_init_debugfs(struct musb *musb);
extern void musb_exit_debugfs(struct musb *musb);
diff --git a/drivers/usb/musb/musb_gadget.c b/drivers/usb/musb/musb_gadget.c
index f47c201..0a50a35 100644
--- a/drivers/usb/musb/musb_gadget.c
+++ b/drivers/usb/musb/musb_gadget.c
@@ -147,7 +147,8 @@
return;
if (request->request.dma == DMA_ADDR_INVALID) {
- DBG(20, "not unmapping a never mapped buffer\n");
+ dev_vdbg(musb->controller,
+ "not unmapping a never mapped buffer\n");
return;
}
if (request->map_state == MUSB_MAPPED) {
@@ -198,11 +199,11 @@
spin_unlock(&musb->lock);
unmap_dma_buffer(req, musb);
if (request->status == 0)
- DBG(5, "%s done request %p, %d/%d\n",
+ dev_dbg(musb->controller, "%s done request %p, %d/%d\n",
ep->end_point.name, request,
req->request.actual, req->request.length);
else
- DBG(2, "%s request %p, %d/%d fault %d\n",
+ dev_dbg(musb->controller, "%s request %p, %d/%d fault %d\n",
ep->end_point.name, request,
req->request.actual, req->request.length,
request->status);
@@ -219,6 +220,7 @@
*/
static void nuke(struct musb_ep *ep, const int status)
{
+ struct musb *musb = ep->musb;
struct musb_request *req = NULL;
void __iomem *epio = ep->musb->endpoints[ep->current_epnum].regs;
@@ -246,7 +248,8 @@
}
value = c->channel_abort(ep->dma);
- DBG(value ? 1 : 6, "%s: abort DMA --> %d\n", ep->name, value);
+ dev_dbg(musb->controller, "%s: abort DMA --> %d\n",
+ ep->name, value);
c->channel_release(ep->dma);
ep->dma = NULL;
}
@@ -329,7 +332,7 @@
/* we shouldn't get here while DMA is active ... but we do ... */
if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
- DBG(4, "dma pending...\n");
+ dev_dbg(musb->controller, "dma pending...\n");
return;
}
@@ -341,18 +344,18 @@
(int)(request->length - request->actual));
if (csr & MUSB_TXCSR_TXPKTRDY) {
- DBG(5, "%s old packet still ready , txcsr %03x\n",
+ dev_dbg(musb->controller, "%s old packet still ready , txcsr %03x\n",
musb_ep->end_point.name, csr);
return;
}
if (csr & MUSB_TXCSR_P_SENDSTALL) {
- DBG(5, "%s stalling, txcsr %03x\n",
+ dev_dbg(musb->controller, "%s stalling, txcsr %03x\n",
musb_ep->end_point.name, csr);
return;
}
- DBG(4, "hw_ep%d, maxpacket %d, fifo count %d, txcsr %03x\n",
+ dev_dbg(musb->controller, "hw_ep%d, maxpacket %d, fifo count %d, txcsr %03x\n",
epnum, musb_ep->packet_sz, fifo_count,
csr);
@@ -369,7 +372,7 @@
/* MUSB_TXCSR_P_ISO is still set correctly */
-#ifdef CONFIG_USB_INVENTRA_DMA
+#if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA)
{
if (request_size < musb_ep->packet_sz)
musb_ep->dma->desired_mode = 0;
@@ -469,7 +472,7 @@
}
/* host may already have the data when this message shows... */
- DBG(3, "%s TX/IN %s len %d/%d, txcsr %04x, fifo %d/%d\n",
+ dev_dbg(musb->controller, "%s TX/IN %s len %d/%d, txcsr %04x, fifo %d/%d\n",
musb_ep->end_point.name, use_dma ? "dma" : "pio",
request->actual, request->length,
musb_readw(epio, MUSB_TXCSR),
@@ -496,7 +499,7 @@
request = &req->request;
csr = musb_readw(epio, MUSB_TXCSR);
- DBG(4, "<== %s, txcsr %04x\n", musb_ep->end_point.name, csr);
+ dev_dbg(musb->controller, "<== %s, txcsr %04x\n", musb_ep->end_point.name, csr);
dma = is_dma_capable() ? musb_ep->dma : NULL;
@@ -516,7 +519,8 @@
csr |= MUSB_TXCSR_P_WZC_BITS;
csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
musb_writew(epio, MUSB_TXCSR, csr);
- DBG(20, "underrun on ep%d, req %p\n", epnum, request);
+ dev_vdbg(musb->controller, "underrun on ep%d, req %p\n",
+ epnum, request);
}
if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
@@ -524,7 +528,7 @@
* SHOULD NOT HAPPEN... has with CPPI though, after
* changing SENDSTALL (and other cases); harmless?
*/
- DBG(5, "%s dma still busy?\n", musb_ep->end_point.name);
+ dev_dbg(musb->controller, "%s dma still busy?\n", musb_ep->end_point.name);
return;
}
@@ -540,7 +544,7 @@
/* Ensure writebuffer is empty. */
csr = musb_readw(epio, MUSB_TXCSR);
request->actual += musb_ep->dma->actual_len;
- DBG(4, "TXCSR%d %04x, DMA off, len %zu, req %p\n",
+ dev_dbg(musb->controller, "TXCSR%d %04x, DMA off, len %zu, req %p\n",
epnum, csr, musb_ep->dma->actual_len, request);
}
@@ -551,7 +555,7 @@
if ((request->zero && request->length
&& (request->length % musb_ep->packet_sz == 0)
&& (request->actual == request->length))
-#ifdef CONFIG_USB_INVENTRA_DMA
+#if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_UX500_DMA)
|| (is_dma && (!dma->desired_mode ||
(request->actual &
(musb_ep->packet_sz - 1))))
@@ -564,7 +568,7 @@
if (csr & MUSB_TXCSR_TXPKTRDY)
return;
- DBG(4, "sending zero pkt\n");
+ dev_dbg(musb->controller, "sending zero pkt\n");
musb_writew(epio, MUSB_TXCSR, MUSB_TXCSR_MODE
| MUSB_TXCSR_TXPKTRDY);
request->zero = 0;
@@ -574,7 +578,7 @@
musb_g_giveback(musb_ep, request, 0);
req = musb_ep->desc ? next_request(musb_ep) : NULL;
if (!req) {
- DBG(4, "%s idle now\n",
+ dev_dbg(musb->controller, "%s idle now\n",
musb_ep->end_point.name);
return;
}
@@ -640,12 +644,12 @@
/* We shouldn't get here while DMA is active, but we do... */
if (dma_channel_status(musb_ep->dma) == MUSB_DMA_STATUS_BUSY) {
- DBG(4, "DMA pending...\n");
+ dev_dbg(musb->controller, "DMA pending...\n");
return;
}
if (csr & MUSB_RXCSR_P_SENDSTALL) {
- DBG(5, "%s stalling, RXCSR %04x\n",
+ dev_dbg(musb->controller, "%s stalling, RXCSR %04x\n",
musb_ep->end_point.name, csr);
return;
}
@@ -754,10 +758,57 @@
if (use_dma)
return;
}
+#elif defined(CONFIG_USB_UX500_DMA)
+ if ((is_buffer_mapped(req)) &&
+ (request->actual < request->length)) {
+
+ struct dma_controller *c;
+ struct dma_channel *channel;
+ int transfer_size = 0;
+
+ c = musb->dma_controller;
+ channel = musb_ep->dma;
+
+ /* In case first packet is short */
+ if (len < musb_ep->packet_sz)
+ transfer_size = len;
+ else if (request->short_not_ok)
+ transfer_size = min(request->length -
+ request->actual,
+ channel->max_len);
+ else
+ transfer_size = min(request->length -
+ request->actual,
+ (unsigned)len);
+
+ csr &= ~MUSB_RXCSR_DMAMODE;
+ csr |= (MUSB_RXCSR_DMAENAB |
+ MUSB_RXCSR_AUTOCLEAR);
+
+ musb_writew(epio, MUSB_RXCSR, csr);
+
+ if (transfer_size <= musb_ep->packet_sz) {
+ musb_ep->dma->desired_mode = 0;
+ } else {
+ musb_ep->dma->desired_mode = 1;
+ /* Mode must be set after DMAENAB */
+ csr |= MUSB_RXCSR_DMAMODE;
+ musb_writew(epio, MUSB_RXCSR, csr);
+ }
+
+ if (c->channel_program(channel,
+ musb_ep->packet_sz,
+ channel->desired_mode,
+ request->dma
+ + request->actual,
+ transfer_size))
+
+ return;
+ }
#endif /* Mentor's DMA */
fifo_count = request->length - request->actual;
- DBG(3, "%s OUT/RX pio fifo %d/%d, maxpacket %d\n",
+ dev_dbg(musb->controller, "%s OUT/RX pio fifo %d/%d, maxpacket %d\n",
musb_ep->end_point.name,
len, fifo_count,
musb_ep->packet_sz);
@@ -846,7 +897,7 @@
csr = musb_readw(epio, MUSB_RXCSR);
dma = is_dma_capable() ? musb_ep->dma : NULL;
- DBG(4, "<== %s, rxcsr %04x%s %p\n", musb_ep->end_point.name,
+ dev_dbg(musb->controller, "<== %s, rxcsr %04x%s %p\n", musb_ep->end_point.name,
csr, dma ? " (dma)" : "", request);
if (csr & MUSB_RXCSR_P_SENTSTALL) {
@@ -861,19 +912,18 @@
csr &= ~MUSB_RXCSR_P_OVERRUN;
musb_writew(epio, MUSB_RXCSR, csr);
- DBG(3, "%s iso overrun on %p\n", musb_ep->name, request);
+ dev_dbg(musb->controller, "%s iso overrun on %p\n", musb_ep->name, request);
if (request->status == -EINPROGRESS)
request->status = -EOVERFLOW;
}
if (csr & MUSB_RXCSR_INCOMPRX) {
/* REVISIT not necessarily an error */
- DBG(4, "%s, incomprx\n", musb_ep->end_point.name);
+ dev_dbg(musb->controller, "%s, incomprx\n", musb_ep->end_point.name);
}
if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
/* "should not happen"; likely RXPKTRDY pending for DMA */
- DBG((csr & MUSB_RXCSR_DMAENAB) ? 4 : 1,
- "%s busy, csr %04x\n",
+ dev_dbg(musb->controller, "%s busy, csr %04x\n",
musb_ep->end_point.name, csr);
return;
}
@@ -887,12 +937,13 @@
request->actual += musb_ep->dma->actual_len;
- DBG(4, "RXCSR%d %04x, dma off, %04x, len %zu, req %p\n",
+ dev_dbg(musb->controller, "RXCSR%d %04x, dma off, %04x, len %zu, req %p\n",
epnum, csr,
musb_readw(epio, MUSB_RXCSR),
musb_ep->dma->actual_len, request);
-#if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA)
+#if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \
+ defined(CONFIG_USB_UX500_DMA)
/* Autoclear doesn't clear RxPktRdy for short packets */
if ((dma->desired_mode == 0 && !hw_ep->rx_double_buffered)
|| (dma->actual_len
@@ -922,7 +973,8 @@
if (!req)
return;
}
-#if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA)
+#if defined(CONFIG_USB_INVENTRA_DMA) || defined(CONFIG_USB_TUSB_OMAP_DMA) || \
+ defined(CONFIG_USB_UX500_DMA)
exit:
#endif
/* Analyze request */
@@ -978,7 +1030,7 @@
ok = musb->hb_iso_rx;
if (!ok) {
- DBG(4, "no support for high bandwidth ISO\n");
+ dev_dbg(musb->controller, "no support for high bandwidth ISO\n");
goto fail;
}
musb_ep->hb_mult = (tmp >> 11) & 3;
@@ -1002,7 +1054,7 @@
goto fail;
if (tmp > hw_ep->max_packet_sz_tx) {
- DBG(4, "packet size beyond hardware FIFO size\n");
+ dev_dbg(musb->controller, "packet size beyond hardware FIFO size\n");
goto fail;
}
@@ -1042,7 +1094,7 @@
goto fail;
if (tmp > hw_ep->max_packet_sz_rx) {
- DBG(4, "packet size beyond hardware FIFO size\n");
+ dev_dbg(musb->controller, "packet size beyond hardware FIFO size\n");
goto fail;
}
@@ -1155,7 +1207,7 @@
spin_unlock_irqrestore(&(musb->lock), flags);
- DBG(2, "%s\n", musb_ep->end_point.name);
+ dev_dbg(musb->controller, "%s\n", musb_ep->end_point.name);
return status;
}
@@ -1167,11 +1219,12 @@
struct usb_request *musb_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
{
struct musb_ep *musb_ep = to_musb_ep(ep);
+ struct musb *musb = musb_ep->musb;
struct musb_request *request = NULL;
request = kzalloc(sizeof *request, gfp_flags);
if (!request) {
- DBG(4, "not enough memory\n");
+ dev_dbg(musb->controller, "not enough memory\n");
return NULL;
}
@@ -1205,7 +1258,7 @@
*/
void musb_ep_restart(struct musb *musb, struct musb_request *req)
{
- DBG(3, "<== %s request %p len %u on hw_ep%d\n",
+ dev_dbg(musb->controller, "<== %s request %p len %u on hw_ep%d\n",
req->tx ? "TX/IN" : "RX/OUT",
&req->request, req->request.length, req->epnum);
@@ -1239,7 +1292,7 @@
if (request->ep != musb_ep)
return -EINVAL;
- DBG(4, "<== to %s request=%p\n", ep->name, req);
+ dev_dbg(musb->controller, "<== to %s request=%p\n", ep->name, req);
/* request is mine now... */
request->request.actual = 0;
@@ -1253,7 +1306,7 @@
/* don't queue if the ep is down */
if (!musb_ep->desc) {
- DBG(4, "req %p queued to %s while ep %s\n",
+ dev_dbg(musb->controller, "req %p queued to %s while ep %s\n",
req, ep->name, "disabled");
status = -ESHUTDOWN;
goto cleanup;
@@ -1290,7 +1343,7 @@
break;
}
if (r != req) {
- DBG(3, "request %p not queued to %s\n", request, ep->name);
+ dev_dbg(musb->controller, "request %p not queued to %s\n", request, ep->name);
status = -EINVAL;
goto done;
}
@@ -1356,7 +1409,7 @@
request = next_request(musb_ep);
if (value) {
if (request) {
- DBG(3, "request in progress, cannot halt %s\n",
+ dev_dbg(musb->controller, "request in progress, cannot halt %s\n",
ep->name);
status = -EAGAIN;
goto done;
@@ -1365,7 +1418,7 @@
if (musb_ep->is_in) {
csr = musb_readw(epio, MUSB_TXCSR);
if (csr & MUSB_TXCSR_FIFONOTEMPTY) {
- DBG(3, "FIFO busy, cannot halt %s\n", ep->name);
+ dev_dbg(musb->controller, "FIFO busy, cannot halt %s\n", ep->name);
status = -EAGAIN;
goto done;
}
@@ -1374,7 +1427,7 @@
musb_ep->wedged = 0;
/* set/clear the stall and toggle bits */
- DBG(2, "%s: %s stall\n", ep->name, value ? "set" : "clear");
+ dev_dbg(musb->controller, "%s: %s stall\n", ep->name, value ? "set" : "clear");
if (musb_ep->is_in) {
csr = musb_readw(epio, MUSB_TXCSR);
csr |= MUSB_TXCSR_P_WZC_BITS
@@ -1401,7 +1454,7 @@
/* maybe start the first request in the queue */
if (!musb_ep->busy && !value && request) {
- DBG(3, "restarting the request\n");
+ dev_dbg(musb->controller, "restarting the request\n");
musb_ep_restart(musb, request);
}
@@ -1532,7 +1585,7 @@
case OTG_STATE_B_IDLE:
/* Start SRP ... OTG not required. */
devctl = musb_readb(mregs, MUSB_DEVCTL);
- DBG(2, "Sending SRP: devctl: %02x\n", devctl);
+ dev_dbg(musb->controller, "Sending SRP: devctl: %02x\n", devctl);
devctl |= MUSB_DEVCTL_SESSION;
musb_writeb(mregs, MUSB_DEVCTL, devctl);
devctl = musb_readb(mregs, MUSB_DEVCTL);
@@ -1549,6 +1602,10 @@
break;
}
+ spin_unlock_irqrestore(&musb->lock, flags);
+ otg_start_srp(musb->xceiv);
+ spin_lock_irqsave(&musb->lock, flags);
+
/* Block idling for at least 1s */
musb_platform_try_idle(musb,
jiffies + msecs_to_jiffies(1 * HZ));
@@ -1556,7 +1613,8 @@
status = 0;
goto done;
default:
- DBG(2, "Unhandled wake: %s\n", otg_state_string(musb));
+ dev_dbg(musb->controller, "Unhandled wake: %s\n",
+ otg_state_string(musb->xceiv->state));
goto done;
}
@@ -1565,7 +1623,7 @@
power = musb_readb(mregs, MUSB_POWER);
power |= MUSB_POWER_RESUME;
musb_writeb(mregs, MUSB_POWER, power);
- DBG(2, "issue wakeup\n");
+ dev_dbg(musb->controller, "issue wakeup\n");
/* FIXME do this next chunk in a timer callback, no udelay */
mdelay(2);
@@ -1599,7 +1657,7 @@
/* FIXME if on, HdrcStart; if off, HdrcStop */
- DBG(3, "gadget %s D+ pullup %s\n",
+ dev_dbg(musb->controller, "gadget %s D+ pullup %s\n",
musb->gadget_driver->function, is_on ? "on" : "off");
musb_writeb(musb->mregs, MUSB_POWER, power);
}
@@ -1607,7 +1665,7 @@
#if 0
static int musb_gadget_vbus_session(struct usb_gadget *gadget, int is_active)
{
- DBG(2, "<= %s =>\n", __func__);
+ dev_dbg(musb->controller, "<= %s =>\n", __func__);
/*
* FIXME iff driver's softconnect flag is set (as it is during probe,
@@ -1816,17 +1874,17 @@
/* driver must be initialized to support peripheral mode */
if (!musb) {
- DBG(1, "no dev??\n");
+ dev_dbg(musb->controller, "no dev??\n");
retval = -ENODEV;
goto err0;
}
pm_runtime_get_sync(musb->controller);
- DBG(3, "registering driver %s\n", driver->function);
+ dev_dbg(musb->controller, "registering driver %s\n", driver->function);
if (musb->gadget_driver) {
- DBG(1, "%s is already bound to %s\n",
+ dev_dbg(musb->controller, "%s is already bound to %s\n",
musb_driver_name,
musb->gadget_driver->driver.name);
retval = -EBUSY;
@@ -1842,7 +1900,7 @@
retval = bind(&musb->g);
if (retval) {
- DBG(3, "bind to driver %s failed --> %d\n",
+ dev_dbg(musb->controller, "bind to driver %s failed --> %d\n",
driver->driver.name, retval);
goto err1;
}
@@ -1870,7 +1928,7 @@
if (is_otg_enabled(musb)) {
struct usb_hcd *hcd = musb_to_hcd(musb);
- DBG(3, "OTG startup...\n");
+ dev_dbg(musb->controller, "OTG startup...\n");
/* REVISIT: funcall to other code, which also
* handles power budgeting ... this way also
@@ -1878,7 +1936,7 @@
*/
retval = usb_add_hcd(musb_to_hcd(musb), -1, 0);
if (retval < 0) {
- DBG(1, "add_hcd failed, %d\n", retval);
+ dev_dbg(musb->controller, "add_hcd failed, %d\n", retval);
goto err2;
}
@@ -1985,7 +2043,7 @@
stop_activity(musb, driver);
otg_set_peripheral(musb->xceiv, NULL);
- DBG(3, "unregistering driver %s\n", driver->function);
+ dev_dbg(musb->controller, "unregistering driver %s\n", driver->function);
spin_unlock_irqrestore(&musb->lock, flags);
driver->unbind(&musb->g);
@@ -2037,7 +2095,7 @@
break;
default:
WARNING("unhandled RESUME transition (%s)\n",
- otg_state_string(musb));
+ otg_state_string(musb->xceiv->state));
}
}
@@ -2047,7 +2105,7 @@
u8 devctl;
devctl = musb_readb(musb->mregs, MUSB_DEVCTL);
- DBG(3, "devctl %02x\n", devctl);
+ dev_dbg(musb->controller, "devctl %02x\n", devctl);
switch (musb->xceiv->state) {
case OTG_STATE_B_IDLE:
@@ -2067,7 +2125,7 @@
* A_PERIPHERAL may need care too
*/
WARNING("unhandled SUSPEND transition (%s)\n",
- otg_state_string(musb));
+ otg_state_string(musb->xceiv->state));
}
}
@@ -2083,7 +2141,7 @@
void __iomem *mregs = musb->mregs;
u8 devctl = musb_readb(mregs, MUSB_DEVCTL);
- DBG(3, "devctl %02x\n", devctl);
+ dev_dbg(musb->controller, "devctl %02x\n", devctl);
/* clear HR */
musb_writeb(mregs, MUSB_DEVCTL, devctl & MUSB_DEVCTL_SESSION);
@@ -2101,8 +2159,8 @@
switch (musb->xceiv->state) {
default:
#ifdef CONFIG_USB_MUSB_OTG
- DBG(2, "Unhandled disconnect %s, setting a_idle\n",
- otg_state_string(musb));
+ dev_dbg(musb->controller, "Unhandled disconnect %s, setting a_idle\n",
+ otg_state_string(musb->xceiv->state));
musb->xceiv->state = OTG_STATE_A_IDLE;
MUSB_HST_MODE(musb);
break;
@@ -2132,7 +2190,7 @@
u8 devctl = musb_readb(mbase, MUSB_DEVCTL);
u8 power;
- DBG(3, "<== %s addr=%x driver '%s'\n",
+ dev_dbg(musb->controller, "<== %s addr=%x driver '%s'\n",
(devctl & MUSB_DEVCTL_BDEVICE)
? "B-Device" : "A-Device",
musb_readb(mbase, MUSB_FADDR),
diff --git a/drivers/usb/musb/musb_gadget_ep0.c b/drivers/usb/musb/musb_gadget_ep0.c
index 75a542e..b2faff2 100644
--- a/drivers/usb/musb/musb_gadget_ep0.c
+++ b/drivers/usb/musb/musb_gadget_ep0.c
@@ -209,7 +209,7 @@
void __iomem *mbase = musb->mregs;
u8 devctl;
- DBG(1, "HNP: Setting HR\n");
+ dev_dbg(musb->controller, "HNP: Setting HR\n");
devctl = musb_readb(mbase, MUSB_DEVCTL);
musb_writeb(mbase, MUSB_DEVCTL, devctl | MUSB_DEVCTL_HR);
}
@@ -306,7 +306,7 @@
/* Maybe start the first request in the queue */
request = next_request(musb_ep);
if (!musb_ep->busy && request) {
- DBG(3, "restarting the request\n");
+ dev_dbg(musb->controller, "restarting the request\n");
musb_ep_restart(musb, request);
}
@@ -553,7 +553,7 @@
if (!req) {
/* WARN_ON(1); */
- DBG(2, "odd; csr0 %04x\n", musb_readw(regs, MUSB_CSR0));
+ dev_dbg(musb->controller, "odd; csr0 %04x\n", musb_readw(regs, MUSB_CSR0));
return;
}
@@ -610,7 +610,7 @@
/* NOTE: earlier 2.6 versions changed setup packets to host
* order, but now USB packets always stay in USB byte order.
*/
- DBG(3, "SETUP req%02x.%02x v%04x i%04x l%d\n",
+ dev_dbg(musb->controller, "SETUP req%02x.%02x v%04x i%04x l%d\n",
req->bRequestType,
req->bRequest,
le16_to_cpu(req->wValue),
@@ -678,7 +678,7 @@
csr = musb_readw(regs, MUSB_CSR0);
len = musb_readb(regs, MUSB_COUNT0);
- DBG(4, "csr %04x, count %d, myaddr %d, ep0stage %s\n",
+ dev_dbg(musb->controller, "csr %04x, count %d, myaddr %d, ep0stage %s\n",
csr, len,
musb_readb(mbase, MUSB_FADDR),
decode_ep0stage(musb->ep0_state));
@@ -749,7 +749,7 @@
/* enter test mode if needed (exit by reset) */
else if (musb->test_mode) {
- DBG(1, "entering TESTMODE\n");
+ dev_dbg(musb->controller, "entering TESTMODE\n");
if (MUSB_TEST_PACKET == musb->test_mode_nr)
musb_load_testpacket(musb);
@@ -861,7 +861,7 @@
break;
}
- DBG(3, "handled %d, csr %04x, ep0stage %s\n",
+ dev_dbg(musb->controller, "handled %d, csr %04x, ep0stage %s\n",
handled, csr,
decode_ep0stage(musb->ep0_state));
@@ -878,7 +878,7 @@
if (handled < 0) {
musb_ep_select(mbase, 0);
stall:
- DBG(3, "stall (%d)\n", handled);
+ dev_dbg(musb->controller, "stall (%d)\n", handled);
musb->ackpend |= MUSB_CSR0_P_SENDSTALL;
musb->ep0_state = MUSB_EP0_STAGE_IDLE;
finish:
@@ -958,7 +958,7 @@
status = 0;
break;
default:
- DBG(1, "ep0 request queued in state %d\n",
+ dev_dbg(musb->controller, "ep0 request queued in state %d\n",
musb->ep0_state);
status = -EINVAL;
goto cleanup;
@@ -967,7 +967,7 @@
/* add request to the list */
list_add_tail(&req->list, &ep->req_list);
- DBG(3, "queue to %s (%s), length=%d\n",
+ dev_dbg(musb->controller, "queue to %s (%s), length=%d\n",
ep->name, ep->is_in ? "IN/TX" : "OUT/RX",
req->request.length);
@@ -1060,7 +1060,7 @@
musb->ackpend = 0;
break;
default:
- DBG(1, "ep0 can't halt in state %d\n", musb->ep0_state);
+ dev_dbg(musb->controller, "ep0 can't halt in state %d\n", musb->ep0_state);
status = -EINVAL;
}
diff --git a/drivers/usb/musb/musb_host.c b/drivers/usb/musb/musb_host.c
index 5eef4a8..7295e31 100644
--- a/drivers/usb/musb/musb_host.c
+++ b/drivers/usb/musb/musb_host.c
@@ -106,6 +106,7 @@
*/
static void musb_h_tx_flush_fifo(struct musb_hw_ep *ep)
{
+ struct musb *musb = ep->musb;
void __iomem *epio = ep->regs;
u16 csr;
u16 lastcsr = 0;
@@ -114,7 +115,7 @@
csr = musb_readw(epio, MUSB_TXCSR);
while (csr & MUSB_TXCSR_FIFONOTEMPTY) {
if (csr != lastcsr)
- DBG(3, "Host TX FIFONOTEMPTY csr: %02x\n", csr);
+ dev_dbg(musb->controller, "Host TX FIFONOTEMPTY csr: %02x\n", csr);
lastcsr = csr;
csr |= MUSB_TXCSR_FLUSHFIFO;
musb_writew(epio, MUSB_TXCSR, csr);
@@ -240,7 +241,7 @@
len = urb->transfer_buffer_length - urb->actual_length;
}
- DBG(4, "qh %p urb %p dev%d ep%d%s%s, hw_ep %d, %p/%d\n",
+ dev_dbg(musb->controller, "qh %p urb %p dev%d ep%d%s%s, hw_ep %d, %p/%d\n",
qh, urb, address, qh->epnum,
is_in ? "in" : "out",
({char *s; switch (qh->type) {
@@ -263,7 +264,7 @@
switch (qh->type) {
case USB_ENDPOINT_XFER_ISOC:
case USB_ENDPOINT_XFER_INT:
- DBG(3, "check whether there's still time for periodic Tx\n");
+ dev_dbg(musb->controller, "check whether there's still time for periodic Tx\n");
frame = musb_readw(mbase, MUSB_FRAME);
/* FIXME this doesn't implement that scheduling policy ...
* or handle framecounter wrapping
@@ -278,7 +279,7 @@
} else {
qh->frame = urb->start_frame;
/* enable SOF interrupt so we can count down */
- DBG(1, "SOF for %d\n", epnum);
+ dev_dbg(musb->controller, "SOF for %d\n", epnum);
#if 1 /* ifndef CONFIG_ARCH_DAVINCI */
musb_writeb(mbase, MUSB_INTRUSBE, 0xff);
#endif
@@ -286,7 +287,7 @@
break;
default:
start:
- DBG(4, "Start TX%d %s\n", epnum,
+ dev_dbg(musb->controller, "Start TX%d %s\n", epnum,
hw_ep->tx_channel ? "dma" : "pio");
if (!hw_ep->tx_channel)
@@ -301,21 +302,7 @@
__releases(musb->lock)
__acquires(musb->lock)
{
- DBG(({ int level; switch (status) {
- case 0:
- level = 4;
- break;
- /* common/boring faults */
- case -EREMOTEIO:
- case -ESHUTDOWN:
- case -ECONNRESET:
- case -EPIPE:
- level = 3;
- break;
- default:
- level = 2;
- break;
- }; level; }),
+ dev_dbg(musb->controller,
"complete %p %pF (%d), dev%d ep%d%s, %d/%d\n",
urb, urb->complete, status,
usb_pipedevice(urb->pipe),
@@ -426,7 +413,7 @@
}
if (qh != NULL && qh->is_ready) {
- DBG(4, "... next ep%d %cX urb %p\n",
+ dev_dbg(musb->controller, "... next ep%d %cX urb %p\n",
hw_ep->epnum, is_in ? 'R' : 'T', next_urb(qh));
musb_start_urb(musb, is_in, qh);
}
@@ -471,7 +458,7 @@
/* musb_ep_select(mbase, epnum); */
rx_count = musb_readw(epio, MUSB_RXCOUNT);
- DBG(3, "RX%d count %d, buffer %p len %d/%d\n", epnum, rx_count,
+ dev_dbg(musb->controller, "RX%d count %d, buffer %p len %d/%d\n", epnum, rx_count,
urb->transfer_buffer, qh->offset,
urb->transfer_buffer_length);
@@ -493,7 +480,7 @@
status = -EOVERFLOW;
urb->error_count++;
}
- DBG(2, "** OVERFLOW %d into %d\n", rx_count, length);
+ dev_dbg(musb->controller, "** OVERFLOW %d into %d\n", rx_count, length);
do_flush = 1;
} else
length = rx_count;
@@ -511,7 +498,7 @@
if (rx_count > length) {
if (urb->status == -EINPROGRESS)
urb->status = -EOVERFLOW;
- DBG(2, "** OVERFLOW %d into %d\n", rx_count, length);
+ dev_dbg(musb->controller, "** OVERFLOW %d into %d\n", rx_count, length);
do_flush = 1;
} else
length = rx_count;
@@ -697,7 +684,7 @@
struct musb_qh *qh = musb_ep_get_qh(hw_ep, !is_out);
u16 packet_sz = qh->maxpacket;
- DBG(3, "%s hw%d urb %p spd%d dev%d ep%d%s "
+ dev_dbg(musb->controller, "%s hw%d urb %p spd%d dev%d ep%d%s "
"h_addr%02x h_port%02x bytes %d\n",
is_out ? "-->" : "<--",
epnum, urb, urb->dev->speed,
@@ -850,37 +837,32 @@
/* kick things off */
if ((is_cppi_enabled() || tusb_dma_omap()) && dma_channel) {
- /* candidate for DMA */
- if (dma_channel) {
- dma_channel->actual_len = 0L;
- qh->segsize = len;
+ /* Candidate for DMA */
+ dma_channel->actual_len = 0L;
+ qh->segsize = len;
- /* AUTOREQ is in a DMA register */
- musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
- csr = musb_readw(hw_ep->regs,
- MUSB_RXCSR);
+ /* AUTOREQ is in a DMA register */
+ musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
+ csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
- /* unless caller treats short rx transfers as
- * errors, we dare not queue multiple transfers.
- */
- dma_ok = dma_controller->channel_program(
- dma_channel, packet_sz,
- !(urb->transfer_flags
- & URB_SHORT_NOT_OK),
- urb->transfer_dma + offset,
- qh->segsize);
- if (!dma_ok) {
- dma_controller->channel_release(
- dma_channel);
- hw_ep->rx_channel = NULL;
- dma_channel = NULL;
- } else
- csr |= MUSB_RXCSR_DMAENAB;
- }
+ /*
+ * Unless caller treats short RX transfers as
+ * errors, we dare not queue multiple transfers.
+ */
+ dma_ok = dma_controller->channel_program(dma_channel,
+ packet_sz, !(urb->transfer_flags &
+ URB_SHORT_NOT_OK),
+ urb->transfer_dma + offset,
+ qh->segsize);
+ if (!dma_ok) {
+ dma_controller->channel_release(dma_channel);
+ hw_ep->rx_channel = dma_channel = NULL;
+ } else
+ csr |= MUSB_RXCSR_DMAENAB;
}
csr |= MUSB_RXCSR_H_REQPKT;
- DBG(7, "RXCSR%d := %04x\n", epnum, csr);
+ dev_dbg(musb->controller, "RXCSR%d := %04x\n", epnum, csr);
musb_writew(hw_ep->regs, MUSB_RXCSR, csr);
csr = musb_readw(hw_ep->regs, MUSB_RXCSR);
}
@@ -923,15 +905,15 @@
request = (struct usb_ctrlrequest *) urb->setup_packet;
if (!request->wLength) {
- DBG(4, "start no-DATA\n");
+ dev_dbg(musb->controller, "start no-DATA\n");
break;
} else if (request->bRequestType & USB_DIR_IN) {
- DBG(4, "start IN-DATA\n");
+ dev_dbg(musb->controller, "start IN-DATA\n");
musb->ep0_stage = MUSB_EP0_IN;
more = true;
break;
} else {
- DBG(4, "start OUT-DATA\n");
+ dev_dbg(musb->controller, "start OUT-DATA\n");
musb->ep0_stage = MUSB_EP0_OUT;
more = true;
}
@@ -943,7 +925,7 @@
if (fifo_count) {
fifo_dest = (u8 *) (urb->transfer_buffer
+ urb->actual_length);
- DBG(3, "Sending %d byte%s to ep0 fifo %p\n",
+ dev_dbg(musb->controller, "Sending %d byte%s to ep0 fifo %p\n",
fifo_count,
(fifo_count == 1) ? "" : "s",
fifo_dest);
@@ -988,7 +970,7 @@
? musb_readb(epio, MUSB_COUNT0)
: 0;
- DBG(4, "<== csr0 %04x, qh %p, count %d, urb %p, stage %d\n",
+ dev_dbg(musb->controller, "<== csr0 %04x, qh %p, count %d, urb %p, stage %d\n",
csr, qh, len, urb, musb->ep0_stage);
/* if we just did status stage, we are done */
@@ -999,15 +981,15 @@
/* prepare status */
if (csr & MUSB_CSR0_H_RXSTALL) {
- DBG(6, "STALLING ENDPOINT\n");
+ dev_dbg(musb->controller, "STALLING ENDPOINT\n");
status = -EPIPE;
} else if (csr & MUSB_CSR0_H_ERROR) {
- DBG(2, "no response, csr0 %04x\n", csr);
+ dev_dbg(musb->controller, "no response, csr0 %04x\n", csr);
status = -EPROTO;
} else if (csr & MUSB_CSR0_H_NAKTIMEOUT) {
- DBG(2, "control NAK timeout\n");
+ dev_dbg(musb->controller, "control NAK timeout\n");
/* NOTE: this code path would be a good place to PAUSE a
* control transfer, if another one is queued, so that
@@ -1022,7 +1004,7 @@
}
if (status) {
- DBG(6, "aborting\n");
+ dev_dbg(musb->controller, "aborting\n");
retval = IRQ_HANDLED;
if (urb)
urb->status = status;
@@ -1072,7 +1054,7 @@
/* flag status stage */
musb->ep0_stage = MUSB_EP0_STATUS;
- DBG(5, "ep0 STATUS, csr %04x\n", csr);
+ dev_dbg(musb->controller, "ep0 STATUS, csr %04x\n", csr);
}
musb_writew(epio, MUSB_CSR0, csr);
@@ -1126,31 +1108,31 @@
/* with CPPI, DMA sometimes triggers "extra" irqs */
if (!urb) {
- DBG(4, "extra TX%d ready, csr %04x\n", epnum, tx_csr);
+ dev_dbg(musb->controller, "extra TX%d ready, csr %04x\n", epnum, tx_csr);
return;
}
pipe = urb->pipe;
dma = is_dma_capable() ? hw_ep->tx_channel : NULL;
- DBG(4, "OUT/TX%d end, csr %04x%s\n", epnum, tx_csr,
+ dev_dbg(musb->controller, "OUT/TX%d end, csr %04x%s\n", epnum, tx_csr,
dma ? ", dma" : "");
/* check for errors */
if (tx_csr & MUSB_TXCSR_H_RXSTALL) {
/* dma was disabled, fifo flushed */
- DBG(3, "TX end %d stall\n", epnum);
+ dev_dbg(musb->controller, "TX end %d stall\n", epnum);
/* stall; record URB status */
status = -EPIPE;
} else if (tx_csr & MUSB_TXCSR_H_ERROR) {
/* (NON-ISO) dma was disabled, fifo flushed */
- DBG(3, "TX 3strikes on ep=%d\n", epnum);
+ dev_dbg(musb->controller, "TX 3strikes on ep=%d\n", epnum);
status = -ETIMEDOUT;
} else if (tx_csr & MUSB_TXCSR_H_NAKTIMEOUT) {
- DBG(6, "TX end=%d device not responding\n", epnum);
+ dev_dbg(musb->controller, "TX end=%d device not responding\n", epnum);
/* NOTE: this code path would be a good place to PAUSE a
* transfer, if there's some other (nonperiodic) tx urb
@@ -1195,7 +1177,7 @@
/* second cppi case */
if (dma_channel_status(dma) == MUSB_DMA_STATUS_BUSY) {
- DBG(4, "extra TX%d ready, csr %04x\n", epnum, tx_csr);
+ dev_dbg(musb->controller, "extra TX%d ready, csr %04x\n", epnum, tx_csr);
return;
}
@@ -1254,7 +1236,7 @@
* FIFO mode too...
*/
if (tx_csr & (MUSB_TXCSR_FIFONOTEMPTY | MUSB_TXCSR_TXPKTRDY)) {
- DBG(2, "DMA complete but packet still in FIFO, "
+ dev_dbg(musb->controller, "DMA complete but packet still in FIFO, "
"CSR %04x\n", tx_csr);
return;
}
@@ -1321,7 +1303,7 @@
return;
}
} else if (tx_csr & MUSB_TXCSR_DMAENAB) {
- DBG(1, "not complete, but DMA enabled?\n");
+ dev_dbg(musb->controller, "not complete, but DMA enabled?\n");
return;
}
@@ -1462,7 +1444,7 @@
* usbtest #11 (unlinks) triggers it regularly, sometimes
* with fifo full. (Only with DMA??)
*/
- DBG(3, "BOGUS RX%d ready, csr %04x, count %d\n", epnum, val,
+ dev_dbg(musb->controller, "BOGUS RX%d ready, csr %04x, count %d\n", epnum, val,
musb_readw(epio, MUSB_RXCOUNT));
musb_h_flush_rxfifo(hw_ep, MUSB_RXCSR_CLRDATATOG);
return;
@@ -1470,20 +1452,20 @@
pipe = urb->pipe;
- DBG(5, "<== hw %d rxcsr %04x, urb actual %d (+dma %zu)\n",
+ dev_dbg(musb->controller, "<== hw %d rxcsr %04x, urb actual %d (+dma %zu)\n",
epnum, rx_csr, urb->actual_length,
dma ? dma->actual_len : 0);
/* check for errors, concurrent stall & unlink is not really
* handled yet! */
if (rx_csr & MUSB_RXCSR_H_RXSTALL) {
- DBG(3, "RX end %d STALL\n", epnum);
+ dev_dbg(musb->controller, "RX end %d STALL\n", epnum);
/* stall; record URB status */
status = -EPIPE;
} else if (rx_csr & MUSB_RXCSR_H_ERROR) {
- DBG(3, "end %d RX proto error\n", epnum);
+ dev_dbg(musb->controller, "end %d RX proto error\n", epnum);
status = -EPROTO;
musb_writeb(epio, MUSB_RXINTERVAL, 0);
@@ -1491,7 +1473,7 @@
} else if (rx_csr & MUSB_RXCSR_DATAERROR) {
if (USB_ENDPOINT_XFER_ISOC != qh->type) {
- DBG(6, "RX end %d NAK timeout\n", epnum);
+ dev_dbg(musb->controller, "RX end %d NAK timeout\n", epnum);
/* NOTE: NAKing is *NOT* an error, so we want to
* continue. Except ... if there's a request for
@@ -1514,12 +1496,12 @@
goto finish;
} else {
- DBG(4, "RX end %d ISO data error\n", epnum);
+ dev_dbg(musb->controller, "RX end %d ISO data error\n", epnum);
/* packet error reported later */
iso_err = true;
}
} else if (rx_csr & MUSB_RXCSR_INCOMPRX) {
- DBG(3, "end %d high bandwidth incomplete ISO packet RX\n",
+ dev_dbg(musb->controller, "end %d high bandwidth incomplete ISO packet RX\n",
epnum);
status = -EPROTO;
}
@@ -1565,7 +1547,7 @@
done = true;
}
- DBG(2, "RXCSR%d %04x, reqpkt, len %zu%s\n", epnum, rx_csr,
+ dev_dbg(musb->controller, "RXCSR%d %04x, reqpkt, len %zu%s\n", epnum, rx_csr,
xfer_len, dma ? ", dma" : "");
rx_csr &= ~MUSB_RXCSR_H_REQPKT;
@@ -1615,7 +1597,7 @@
MUSB_RXCSR_H_WZC_BITS | val);
}
- DBG(4, "ep %d dma %s, rxcsr %04x, rxcount %d\n", epnum,
+ dev_dbg(musb->controller, "ep %d dma %s, rxcsr %04x, rxcount %d\n", epnum,
done ? "off" : "reset",
musb_readw(epio, MUSB_RXCSR),
musb_readw(epio, MUSB_RXCOUNT));
@@ -1648,7 +1630,7 @@
rx_count = musb_readw(epio, MUSB_RXCOUNT);
- DBG(2, "RX%d count %d, buffer 0x%x len %d/%d\n",
+ dev_dbg(musb->controller, "RX%d count %d, buffer 0x%x len %d/%d\n",
epnum, rx_count,
urb->transfer_dma
+ urb->actual_length,
@@ -1672,7 +1654,7 @@
d_status = -EOVERFLOW;
urb->error_count++;
}
- DBG(2, "** OVERFLOW %d into %d\n",\
+ dev_dbg(musb->controller, "** OVERFLOW %d into %d\n",\
rx_count, d->length);
length = d->length;
@@ -1760,7 +1742,7 @@
usb_hcd_unmap_urb_for_dma(musb_to_hcd(musb), urb);
done = musb_host_packet_rx(musb, urb,
epnum, iso_err);
- DBG(6, "read %spacket\n", done ? "last " : "");
+ dev_dbg(musb->controller, "read %spacket\n", done ? "last " : "");
}
}
@@ -1881,7 +1863,7 @@
idle = 1;
qh->mux = 0;
hw_ep = musb->endpoints + best_end;
- DBG(4, "qh %p periodic slot %d\n", qh, best_end);
+ dev_dbg(musb->controller, "qh %p periodic slot %d\n", qh, best_end);
success:
if (head) {
idle = list_empty(head);
@@ -2087,6 +2069,7 @@
static int musb_cleanup_urb(struct urb *urb, struct musb_qh *qh)
{
struct musb_hw_ep *ep = qh->hw_ep;
+ struct musb *musb = ep->musb;
void __iomem *epio = ep->regs;
unsigned hw_end = ep->epnum;
void __iomem *regs = ep->musb->mregs;
@@ -2102,7 +2085,7 @@
dma = is_in ? ep->rx_channel : ep->tx_channel;
if (dma) {
status = ep->musb->dma_controller->channel_abort(dma);
- DBG(status ? 1 : 3,
+ dev_dbg(musb->controller,
"abort %cX%d DMA for urb %p --> %d\n",
is_in ? 'R' : 'T', ep->epnum,
urb, status);
@@ -2149,7 +2132,7 @@
int is_in = usb_pipein(urb->pipe);
int ret;
- DBG(4, "urb=%p, dev%d ep%d%s\n", urb,
+ dev_dbg(musb->controller, "urb=%p, dev%d ep%d%s\n", urb,
usb_pipedevice(urb->pipe),
usb_pipeendpoint(urb->pipe),
is_in ? "in" : "out");
@@ -2304,7 +2287,7 @@
if (musb->is_active) {
WARNING("trying to suspend as %s while active\n",
- otg_state_string(musb));
+ otg_state_string(musb->xceiv->state));
return -EBUSY;
} else
return 0;
diff --git a/drivers/usb/musb/musb_virthub.c b/drivers/usb/musb/musb_virthub.c
index 489104a..2d80a57 100644
--- a/drivers/usb/musb/musb_virthub.c
+++ b/drivers/usb/musb/musb_virthub.c
@@ -74,7 +74,7 @@
break;
}
- DBG(3, "Root port suspended, power %02x\n", power);
+ dev_dbg(musb->controller, "Root port suspended, power %02x\n", power);
musb->port1_status |= USB_PORT_STAT_SUSPEND;
switch (musb->xceiv->state) {
@@ -97,15 +97,15 @@
break;
#endif
default:
- DBG(1, "bogus rh suspend? %s\n",
- otg_state_string(musb));
+ dev_dbg(musb->controller, "bogus rh suspend? %s\n",
+ otg_state_string(musb->xceiv->state));
}
} else if (power & MUSB_POWER_SUSPENDM) {
power &= ~MUSB_POWER_SUSPENDM;
power |= MUSB_POWER_RESUME;
musb_writeb(mbase, MUSB_POWER, power);
- DBG(3, "Root port resuming, power %02x\n", power);
+ dev_dbg(musb->controller, "Root port resuming, power %02x\n", power);
/* later, GetPortStatus will stop RESUME signaling */
musb->port1_status |= MUSB_PORT_STAT_RESUME;
@@ -120,7 +120,7 @@
#ifdef CONFIG_USB_MUSB_OTG
if (musb->xceiv->state == OTG_STATE_B_IDLE) {
- DBG(2, "HNP: Returning from HNP; no hub reset from b_idle\n");
+ dev_dbg(musb->controller, "HNP: Returning from HNP; no hub reset from b_idle\n");
musb->port1_status &= ~USB_PORT_STAT_RESET;
return;
}
@@ -159,7 +159,7 @@
musb->port1_status &= ~USB_PORT_STAT_ENABLE;
musb->rh_timer = jiffies + msecs_to_jiffies(50);
} else {
- DBG(4, "root port reset stopped\n");
+ dev_dbg(musb->controller, "root port reset stopped\n");
musb_writeb(mbase, MUSB_POWER,
power & ~MUSB_POWER_RESET);
@@ -167,7 +167,7 @@
power = musb_readb(mbase, MUSB_POWER);
if (power & MUSB_POWER_HSMODE) {
- DBG(4, "high-speed device connected\n");
+ dev_dbg(musb->controller, "high-speed device connected\n");
musb->port1_status |= USB_PORT_STAT_HIGH_SPEED;
}
@@ -208,7 +208,8 @@
musb->xceiv->state = OTG_STATE_B_IDLE;
break;
default:
- DBG(1, "host disconnect (%s)\n", otg_state_string(musb));
+ dev_dbg(musb->controller, "host disconnect (%s)\n",
+ otg_state_string(musb->xceiv->state));
}
}
@@ -287,7 +288,7 @@
default:
goto error;
}
- DBG(5, "clear feature %d\n", wValue);
+ dev_dbg(musb->controller, "clear feature %d\n", wValue);
musb->port1_status &= ~(1 << wValue);
break;
case GetHubDescriptor:
@@ -329,7 +330,7 @@
power = musb_readb(musb->mregs, MUSB_POWER);
power &= ~MUSB_POWER_RESUME;
- DBG(4, "root port resume stopped, power %02x\n",
+ dev_dbg(musb->controller, "root port resume stopped, power %02x\n",
power);
musb_writeb(musb->mregs, MUSB_POWER, power);
@@ -352,7 +353,7 @@
(__le32 *) buf);
/* port change status is more interesting */
- DBG(get_unaligned((u16 *)(buf+2)) ? 2 : 5, "port status %08x\n",
+ dev_dbg(musb->controller, "port status %08x\n",
musb->port1_status);
break;
case SetPortFeature:
@@ -423,7 +424,7 @@
default:
goto error;
}
- DBG(5, "set feature %d\n", wValue);
+ dev_dbg(musb->controller, "set feature %d\n", wValue);
musb->port1_status |= 1 << wValue;
break;
diff --git a/drivers/usb/musb/musbhsdma.c b/drivers/usb/musb/musbhsdma.c
index d281792..f70c5a5 100644
--- a/drivers/usb/musb/musbhsdma.c
+++ b/drivers/usb/musb/musbhsdma.c
@@ -122,11 +122,12 @@
{
struct musb_dma_channel *musb_channel = channel->private_data;
struct musb_dma_controller *controller = musb_channel->controller;
+ struct musb *musb = controller->private_data;
void __iomem *mbase = controller->base;
u8 bchannel = musb_channel->idx;
u16 csr = 0;
- DBG(4, "%p, pkt_sz %d, addr 0x%x, len %d, mode %d\n",
+ dev_dbg(musb->controller, "%p, pkt_sz %d, addr 0x%x, len %d, mode %d\n",
channel, packet_sz, dma_addr, len, mode);
if (mode) {
@@ -161,7 +162,7 @@
struct musb_dma_controller *controller = musb_channel->controller;
struct musb *musb = controller->private_data;
- DBG(2, "ep%d-%s pkt_sz %d, dma_addr 0x%x length %d, mode %d\n",
+ dev_dbg(musb->controller, "ep%d-%s pkt_sz %d, dma_addr 0x%x length %d, mode %d\n",
musb_channel->epnum,
musb_channel->transmit ? "Tx" : "Rx",
packet_sz, dma_addr, len, mode);
@@ -274,7 +275,7 @@
#endif
if (!int_hsdma) {
- DBG(2, "spurious DMA irq\n");
+ dev_dbg(musb->controller, "spurious DMA irq\n");
for (bchannel = 0; bchannel < MUSB_HSDMA_CHANNELS; bchannel++) {
musb_channel = (struct musb_dma_channel *)
@@ -288,7 +289,7 @@
}
}
- DBG(2, "int_hsdma = 0x%x\n", int_hsdma);
+ dev_dbg(musb->controller, "int_hsdma = 0x%x\n", int_hsdma);
if (!int_hsdma)
goto done;
@@ -315,7 +316,7 @@
channel->actual_len = addr
- musb_channel->start_addr;
- DBG(2, "ch %p, 0x%x -> 0x%x (%zu / %d) %s\n",
+ dev_dbg(musb->controller, "ch %p, 0x%x -> 0x%x (%zu / %d) %s\n",
channel, musb_channel->start_addr,
addr, channel->actual_len,
musb_channel->len,
diff --git a/drivers/usb/musb/omap2430.c b/drivers/usb/musb/omap2430.c
index e9e60b6..c5d4c44 100644
--- a/drivers/usb/musb/omap2430.c
+++ b/drivers/usb/musb/omap2430.c
@@ -76,7 +76,7 @@
if (musb->port1_status & MUSB_PORT_STAT_RESUME) {
power = musb_readb(musb->mregs, MUSB_POWER);
power &= ~MUSB_POWER_RESUME;
- DBG(1, "root port resume stopped, power %02x\n", power);
+ dev_dbg(musb->controller, "root port resume stopped, power %02x\n", power);
musb_writeb(musb->mregs, MUSB_POWER, power);
musb->is_active = 1;
musb->port1_status &= ~(USB_PORT_STAT_SUSPEND
@@ -114,7 +114,8 @@
/* Never idle if active, or when VBUS timeout is not set as host */
if (musb->is_active || ((musb->a_wait_bcon == 0)
&& (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) {
- DBG(4, "%s active, deleting timer\n", otg_state_string(musb));
+ dev_dbg(musb->controller, "%s active, deleting timer\n",
+ otg_state_string(musb->xceiv->state));
del_timer(&musb_idle_timer);
last_timer = jiffies;
return;
@@ -124,14 +125,14 @@
if (!timer_pending(&musb_idle_timer))
last_timer = timeout;
else {
- DBG(4, "Longer idle timer already pending, ignoring\n");
+ dev_dbg(musb->controller, "Longer idle timer already pending, ignoring\n");
return;
}
}
last_timer = timeout;
- DBG(4, "%s inactive, for idle timer for %lu ms\n",
- otg_state_string(musb),
+ dev_dbg(musb->controller, "%s inactive, for idle timer for %lu ms\n",
+ otg_state_string(musb->xceiv->state),
(unsigned long)jiffies_to_msecs(timeout - jiffies));
mod_timer(&musb_idle_timer, timeout);
}
@@ -193,9 +194,9 @@
}
musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
- DBG(1, "VBUS %s, devctl %02x "
+ dev_dbg(musb->controller, "VBUS %s, devctl %02x "
/* otg %3x conf %08x prcm %08x */ "\n",
- otg_state_string(musb),
+ otg_state_string(musb->xceiv->state),
musb_readb(musb->mregs, MUSB_DEVCTL));
}
@@ -239,7 +240,7 @@
switch (event) {
case USB_EVENT_ID:
- DBG(4, "ID GND\n");
+ dev_dbg(musb->controller, "ID GND\n");
if (is_otg_enabled(musb)) {
#ifdef CONFIG_USB_GADGET_MUSB_HDRC
@@ -257,7 +258,7 @@
break;
case USB_EVENT_VBUS:
- DBG(4, "VBUS Connect\n");
+ dev_dbg(musb->controller, "VBUS Connect\n");
#ifdef CONFIG_USB_GADGET_MUSB_HDRC
if (musb->gadget_driver)
@@ -267,7 +268,7 @@
break;
case USB_EVENT_NONE:
- DBG(4, "VBUS Disconnect\n");
+ dev_dbg(musb->controller, "VBUS Disconnect\n");
#ifdef CONFIG_USB_GADGET_MUSB_HDRC
if (is_otg_enabled(musb) || is_peripheral_enabled(musb))
@@ -285,7 +286,7 @@
otg_shutdown(musb->xceiv);
break;
default:
- DBG(4, "ID float\n");
+ dev_dbg(musb->controller, "ID float\n");
return NOTIFY_DONE;
}
@@ -339,7 +340,7 @@
status = otg_register_notifier(musb->xceiv, &musb->nb);
if (status)
- DBG(1, "notification register failed\n");
+ dev_dbg(musb->controller, "notification register failed\n");
setup_timer(&musb_idle_timer, musb_do_idle, (unsigned long) musb);
diff --git a/drivers/usb/musb/tusb6010.c b/drivers/usb/musb/tusb6010.c
index c47aac4..b410357 100644
--- a/drivers/usb/musb/tusb6010.c
+++ b/drivers/usb/musb/tusb6010.c
@@ -106,7 +106,7 @@
tmp = phy_otg_ena & ~WBUS_QUIRK_MASK;
tmp |= TUSB_PHY_OTG_CTRL_WRPROTECT | TUSB_PHY_OTG_CTRL_TESTM2;
musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
- DBG(2, "Enabled tusb wbus quirk ctrl %08x ena %08x\n",
+ dev_dbg(musb->controller, "Enabled tusb wbus quirk ctrl %08x ena %08x\n",
musb_readl(tbase, TUSB_PHY_OTG_CTRL),
musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
} else if (musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE)
@@ -115,7 +115,7 @@
musb_writel(tbase, TUSB_PHY_OTG_CTRL, tmp);
tmp = TUSB_PHY_OTG_CTRL_WRPROTECT | phy_otg_ena;
musb_writel(tbase, TUSB_PHY_OTG_CTRL_ENABLE, tmp);
- DBG(2, "Disabled tusb wbus quirk ctrl %08x ena %08x\n",
+ dev_dbg(musb->controller, "Disabled tusb wbus quirk ctrl %08x ena %08x\n",
musb_readl(tbase, TUSB_PHY_OTG_CTRL),
musb_readl(tbase, TUSB_PHY_OTG_CTRL_ENABLE));
phy_otg_ctrl = 0;
@@ -172,13 +172,14 @@
void musb_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *buf)
{
+ struct musb *musb = hw_ep->musb;
void __iomem *ep_conf = hw_ep->conf;
void __iomem *fifo = hw_ep->fifo;
u8 epnum = hw_ep->epnum;
prefetch(buf);
- DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
+ dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
'T', epnum, fifo, len, buf);
if (epnum)
@@ -221,11 +222,12 @@
void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *buf)
{
+ struct musb *musb = hw_ep->musb;
void __iomem *ep_conf = hw_ep->conf;
void __iomem *fifo = hw_ep->fifo;
u8 epnum = hw_ep->epnum;
- DBG(4, "%cX ep%d fifo %p count %d buf %p\n",
+ dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
'R', epnum, fifo, len, buf);
if (epnum)
@@ -304,7 +306,7 @@
}
musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
- DBG(2, "draw max %d mA VBUS\n", mA);
+ dev_dbg(musb->controller, "draw max %d mA VBUS\n", mA);
return 0;
}
@@ -374,7 +376,7 @@
reg |= TUSB_PRCM_MNGMT_PM_IDLE | TUSB_PRCM_MNGMT_DEV_IDLE;
musb_writel(tbase, TUSB_PRCM_MNGMT, reg);
- DBG(6, "idle, wake on %02x\n", wakeup_enables);
+ dev_dbg(musb->controller, "idle, wake on %02x\n", wakeup_enables);
}
/*
@@ -421,8 +423,8 @@
if ((musb->a_wait_bcon != 0)
&& (musb->idle_timeout == 0
|| time_after(jiffies, musb->idle_timeout))) {
- DBG(4, "Nothing connected %s, turning off VBUS\n",
- otg_state_string(musb));
+ dev_dbg(musb->controller, "Nothing connected %s, turning off VBUS\n",
+ otg_state_string(musb->xceiv->state));
}
/* FALLTHROUGH */
case OTG_STATE_A_IDLE:
@@ -481,7 +483,8 @@
/* Never idle if active, or when VBUS timeout is not set as host */
if (musb->is_active || ((musb->a_wait_bcon == 0)
&& (musb->xceiv->state == OTG_STATE_A_WAIT_BCON))) {
- DBG(4, "%s active, deleting timer\n", otg_state_string(musb));
+ dev_dbg(musb->controller, "%s active, deleting timer\n",
+ otg_state_string(musb->xceiv->state));
del_timer(&musb_idle_timer);
last_timer = jiffies;
return;
@@ -491,14 +494,14 @@
if (!timer_pending(&musb_idle_timer))
last_timer = timeout;
else {
- DBG(4, "Longer idle timer already pending, ignoring\n");
+ dev_dbg(musb->controller, "Longer idle timer already pending, ignoring\n");
return;
}
}
last_timer = timeout;
- DBG(4, "%s inactive, for idle timer for %lu ms\n",
- otg_state_string(musb),
+ dev_dbg(musb->controller, "%s inactive, for idle timer for %lu ms\n",
+ otg_state_string(musb->xceiv->state),
(unsigned long)jiffies_to_msecs(timeout - jiffies));
mod_timer(&musb_idle_timer, timeout);
}
@@ -572,8 +575,8 @@
musb_writel(tbase, TUSB_DEV_CONF, conf);
musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
- DBG(1, "VBUS %s, devctl %02x otg %3x conf %08x prcm %08x\n",
- otg_state_string(musb),
+ dev_dbg(musb->controller, "VBUS %s, devctl %02x otg %3x conf %08x prcm %08x\n",
+ otg_state_string(musb->xceiv->state),
musb_readb(musb->mregs, MUSB_DEVCTL),
musb_readl(tbase, TUSB_DEV_OTG_STAT),
conf, prcm);
@@ -633,7 +636,7 @@
#endif
default:
- DBG(2, "Trying to set mode %i\n", musb_mode);
+ dev_dbg(musb->controller, "Trying to set mode %i\n", musb_mode);
return -EINVAL;
}
@@ -666,7 +669,7 @@
default_a = !(otg_stat & TUSB_DEV_OTG_STAT_ID_STATUS);
else
default_a = is_host_enabled(musb);
- DBG(2, "Default-%c\n", default_a ? 'A' : 'B');
+ dev_dbg(musb->controller, "Default-%c\n", default_a ? 'A' : 'B');
musb->xceiv->default_a = default_a;
tusb_musb_set_vbus(musb, default_a);
@@ -693,7 +696,7 @@
#endif
if (otg_stat & TUSB_DEV_OTG_STAT_SESS_END) {
- DBG(1, "Forcing disconnect (no interrupt)\n");
+ dev_dbg(musb->controller, "Forcing disconnect (no interrupt)\n");
if (musb->xceiv->state != OTG_STATE_B_IDLE) {
/* INTR_DISCONNECT can hide... */
musb->xceiv->state = OTG_STATE_B_IDLE;
@@ -701,18 +704,18 @@
}
musb->is_active = 0;
}
- DBG(2, "vbus change, %s, otg %03x\n",
- otg_state_string(musb), otg_stat);
+ dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
+ otg_state_string(musb->xceiv->state), otg_stat);
idle_timeout = jiffies + (1 * HZ);
schedule_work(&musb->irq_work);
} else /* A-dev state machine */ {
- DBG(2, "vbus change, %s, otg %03x\n",
- otg_state_string(musb), otg_stat);
+ dev_dbg(musb->controller, "vbus change, %s, otg %03x\n",
+ otg_state_string(musb->xceiv->state), otg_stat);
switch (musb->xceiv->state) {
case OTG_STATE_A_IDLE:
- DBG(2, "Got SRP, turning on VBUS\n");
+ dev_dbg(musb->controller, "Got SRP, turning on VBUS\n");
musb_platform_set_vbus(musb, 1);
/* CONNECT can wake if a_wait_bcon is set */
@@ -756,7 +759,8 @@
if (int_src & TUSB_INT_SRC_OTG_TIMEOUT) {
u8 devctl;
- DBG(4, "%s timer, %03x\n", otg_state_string(musb), otg_stat);
+ dev_dbg(musb->controller, "%s timer, %03x\n",
+ otg_state_string(musb->xceiv->state), otg_stat);
switch (musb->xceiv->state) {
case OTG_STATE_A_WAIT_VRISE:
@@ -767,7 +771,7 @@
if (otg_stat & TUSB_DEV_OTG_STAT_VBUS_VALID) {
if ((devctl & MUSB_DEVCTL_VBUS)
!= MUSB_DEVCTL_VBUS) {
- DBG(2, "devctl %02x\n", devctl);
+ dev_dbg(musb->controller, "devctl %02x\n", devctl);
break;
}
musb->xceiv->state = OTG_STATE_A_WAIT_BCON;
@@ -812,7 +816,7 @@
musb_writel(tbase, TUSB_INT_MASK, ~TUSB_INT_MASK_RESERVED_BITS);
int_src = musb_readl(tbase, TUSB_INT_SRC) & ~TUSB_INT_SRC_RESERVED_BITS;
- DBG(3, "TUSB IRQ %08x\n", int_src);
+ dev_dbg(musb->controller, "TUSB IRQ %08x\n", int_src);
musb->int_usb = (u8) int_src;
@@ -833,7 +837,7 @@
reg = musb_readl(tbase, TUSB_SCRATCH_PAD);
if (reg == i)
break;
- DBG(6, "TUSB NOR not ready\n");
+ dev_dbg(musb->controller, "TUSB NOR not ready\n");
}
/* work around issue 13 (2nd half) */
@@ -845,7 +849,7 @@
musb->is_active = 1;
schedule_work(&musb->irq_work);
}
- DBG(3, "wake %sactive %02x\n",
+ dev_dbg(musb->controller, "wake %sactive %02x\n",
musb->is_active ? "" : "in", reg);
/* REVISIT host side TUSB_PRCM_WHOSTDISCON, TUSB_PRCM_WBUS */
@@ -867,7 +871,7 @@
u32 dma_src = musb_readl(tbase, TUSB_DMA_INT_SRC);
u32 real_dma_src = musb_readl(tbase, TUSB_DMA_INT_MASK);
- DBG(3, "DMA IRQ %08x\n", dma_src);
+ dev_dbg(musb->controller, "DMA IRQ %08x\n", dma_src);
real_dma_src = ~real_dma_src & dma_src;
if (tusb_dma_omap() && real_dma_src) {
int tx_source = (real_dma_src & 0xffff);
@@ -875,7 +879,7 @@
for (i = 1; i <= 15; i++) {
if (tx_source & (1 << i)) {
- DBG(3, "completing ep%i %s\n", i, "tx");
+ dev_dbg(musb->controller, "completing ep%i %s\n", i, "tx");
musb_dma_completion(musb, i, 1);
}
}
diff --git a/drivers/usb/musb/tusb6010_omap.c b/drivers/usb/musb/tusb6010_omap.c
index 99cb541..c784e6c 100644
--- a/drivers/usb/musb/tusb6010_omap.c
+++ b/drivers/usb/musb/tusb6010_omap.c
@@ -65,7 +65,7 @@
tusb_dma = container_of(c, struct tusb_omap_dma, controller);
- /* DBG(3, "ep%i ch: %i\n", chdat->epnum, chdat->ch); */
+ /* dev_dbg(musb->controller, "ep%i ch: %i\n", chdat->epnum, chdat->ch); */
return 0;
}
@@ -76,7 +76,7 @@
tusb_dma = container_of(c, struct tusb_omap_dma, controller);
- /* DBG(3, "ep%i ch: %i\n", chdat->epnum, chdat->ch); */
+ /* dev_dbg(musb->controller, "ep%i ch: %i\n", chdat->epnum, chdat->ch); */
return 0;
}
@@ -89,7 +89,7 @@
u32 reg = musb_readl(chdat->tbase, TUSB_DMA_EP_MAP);
if (reg != 0) {
- DBG(3, "ep%i dmareq0 is busy for ep%i\n",
+ dev_dbg(musb->controller, "ep%i dmareq0 is busy for ep%i\n",
chdat->epnum, reg & 0xf);
return -EAGAIN;
}
@@ -143,7 +143,7 @@
if (ch_status != OMAP_DMA_BLOCK_IRQ)
printk(KERN_ERR "TUSB DMA error status: %i\n", ch_status);
- DBG(3, "ep%i %s dma callback ch: %i status: %x\n",
+ dev_dbg(musb->controller, "ep%i %s dma callback ch: %i status: %x\n",
chdat->epnum, chdat->tx ? "tx" : "rx",
ch, ch_status);
@@ -156,7 +156,7 @@
/* HW issue #10: XFR_SIZE may get corrupt on DMA (both async & sync) */
if (unlikely(remaining > chdat->transfer_len)) {
- DBG(2, "Corrupt %s dma ch%i XFR_SIZE: 0x%08lx\n",
+ dev_dbg(musb->controller, "Corrupt %s dma ch%i XFR_SIZE: 0x%08lx\n",
chdat->tx ? "tx" : "rx", chdat->ch,
remaining);
remaining = 0;
@@ -165,13 +165,13 @@
channel->actual_len = chdat->transfer_len - remaining;
pio = chdat->len - channel->actual_len;
- DBG(3, "DMA remaining %lu/%u\n", remaining, chdat->transfer_len);
+ dev_dbg(musb->controller, "DMA remaining %lu/%u\n", remaining, chdat->transfer_len);
/* Transfer remaining 1 - 31 bytes */
if (pio > 0 && pio < 32) {
u8 *buf;
- DBG(3, "Using PIO for remaining %lu bytes\n", pio);
+ dev_dbg(musb->controller, "Using PIO for remaining %lu bytes\n", pio);
buf = phys_to_virt((u32)chdat->dma_addr) + chdat->transfer_len;
if (chdat->tx) {
dma_unmap_single(dev, chdat->dma_addr,
@@ -209,7 +209,7 @@
u16 csr;
if (chdat->tx) {
- DBG(3, "terminating short tx packet\n");
+ dev_dbg(musb->controller, "terminating short tx packet\n");
musb_ep_select(mbase, chdat->epnum);
csr = musb_readw(hw_ep->regs, MUSB_TXCSR);
csr |= MUSB_TXCSR_MODE | MUSB_TXCSR_TXPKTRDY
@@ -264,7 +264,7 @@
dma_remaining = TUSB_EP_CONFIG_XFR_SIZE(dma_remaining);
if (dma_remaining) {
- DBG(2, "Busy %s dma ch%i, not using: %08x\n",
+ dev_dbg(musb->controller, "Busy %s dma ch%i, not using: %08x\n",
chdat->tx ? "tx" : "rx", chdat->ch,
dma_remaining);
return false;
@@ -283,7 +283,7 @@
sync_dev = chdat->sync_dev;
} else {
if (tusb_omap_use_shared_dmareq(chdat) != 0) {
- DBG(3, "could not get dma for ep%i\n", chdat->epnum);
+ dev_dbg(musb->controller, "could not get dma for ep%i\n", chdat->epnum);
return false;
}
if (tusb_dma->ch < 0) {
@@ -326,7 +326,7 @@
dma_params.frame_count = chdat->transfer_len / 32; /* Burst sz frame */
- DBG(3, "ep%i %s dma ch%i dma: %08x len: %u(%u) packet_sz: %i(%i)\n",
+ dev_dbg(musb->controller, "ep%i %s dma ch%i dma: %08x len: %u(%u) packet_sz: %i(%i)\n",
chdat->epnum, chdat->tx ? "tx" : "rx",
ch, dma_addr, chdat->transfer_len, len,
chdat->transfer_packet_sz, packet_sz);
@@ -370,7 +370,7 @@
dst_burst = OMAP_DMA_DATA_BURST_16; /* 16x32 write */
}
- DBG(3, "ep%i %s using %i-bit %s dma from 0x%08lx to 0x%08lx\n",
+ dev_dbg(musb->controller, "ep%i %s using %i-bit %s dma from 0x%08lx to 0x%08lx\n",
chdat->epnum, chdat->tx ? "tx" : "rx",
(dma_params.data_type == OMAP_DMA_DATA_TYPE_S32) ? 32 : 16,
((dma_addr & 0x3) == 0) ? "sync" : "async",
@@ -525,7 +525,7 @@
/* REVISIT: Why does dmareq5 not work? */
if (hw_ep->epnum == 0) {
- DBG(3, "Not allowing DMA for ep0 %s\n", tx ? "tx" : "rx");
+ dev_dbg(musb->controller, "Not allowing DMA for ep0 %s\n", tx ? "tx" : "rx");
return NULL;
}
@@ -585,7 +585,7 @@
chdat->ch = -1;
}
- DBG(3, "ep%i %s dma: %s dma%i dmareq%i sync%i\n",
+ dev_dbg(musb->controller, "ep%i %s dma: %s dma%i dmareq%i sync%i\n",
chdat->epnum,
chdat->tx ? "tx" : "rx",
chdat->ch >= 0 ? "dedicated" : "shared",
@@ -598,7 +598,7 @@
free_dmareq:
tusb_omap_dma_free_dmareq(chdat);
- DBG(3, "ep%i: Could not get a DMA channel\n", chdat->epnum);
+ dev_dbg(musb->controller, "ep%i: Could not get a DMA channel\n", chdat->epnum);
channel->status = MUSB_DMA_STATUS_UNKNOWN;
return NULL;
@@ -611,7 +611,7 @@
void __iomem *tbase = musb->ctrl_base;
u32 reg;
- DBG(3, "ep%i ch%i\n", chdat->epnum, chdat->ch);
+ dev_dbg(musb->controller, "ep%i ch%i\n", chdat->epnum, chdat->ch);
reg = musb_readl(tbase, TUSB_DMA_INT_MASK);
if (chdat->tx)
diff --git a/drivers/usb/musb/ux500_dma.c b/drivers/usb/musb/ux500_dma.c
new file mode 100644
index 0000000..cecace4
--- /dev/null
+++ b/drivers/usb/musb/ux500_dma.c
@@ -0,0 +1,422 @@
+/*
+ * drivers/usb/musb/ux500_dma.c
+ *
+ * U8500 and U5500 DMA support code
+ *
+ * Copyright (C) 2009 STMicroelectronics
+ * Copyright (C) 2011 ST-Ericsson SA
+ * Authors:
+ * Mian Yousaf Kaukab <mian.yousaf.kaukab@stericsson.com>
+ * Praveena Nadahally <praveen.nadahally@stericsson.com>
+ * Rajaram Regupathy <ragupathy.rajaram@stericsson.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/device.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/dma-mapping.h>
+#include <linux/dmaengine.h>
+#include <linux/pfn.h>
+#include <mach/usb.h>
+#include "musb_core.h"
+
+struct ux500_dma_channel {
+ struct dma_channel channel;
+ struct ux500_dma_controller *controller;
+ struct musb_hw_ep *hw_ep;
+ struct work_struct channel_work;
+ struct dma_chan *dma_chan;
+ unsigned int cur_len;
+ dma_cookie_t cookie;
+ u8 ch_num;
+ u8 is_tx;
+ u8 is_allocated;
+};
+
+struct ux500_dma_controller {
+ struct dma_controller controller;
+ struct ux500_dma_channel rx_channel[UX500_MUSB_DMA_NUM_RX_CHANNELS];
+ struct ux500_dma_channel tx_channel[UX500_MUSB_DMA_NUM_TX_CHANNELS];
+ u32 num_rx_channels;
+ u32 num_tx_channels;
+ void *private_data;
+ dma_addr_t phy_base;
+};
+
+/* Work function invoked from DMA callback to handle tx transfers. */
+static void ux500_tx_work(struct work_struct *data)
+{
+ struct ux500_dma_channel *ux500_channel = container_of(data,
+ struct ux500_dma_channel, channel_work);
+ struct musb_hw_ep *hw_ep = ux500_channel->hw_ep;
+ struct musb *musb = hw_ep->musb;
+ unsigned long flags;
+
+ DBG(4, "DMA tx transfer done on hw_ep=%d\n", hw_ep->epnum);
+
+ spin_lock_irqsave(&musb->lock, flags);
+ ux500_channel->channel.actual_len = ux500_channel->cur_len;
+ ux500_channel->channel.status = MUSB_DMA_STATUS_FREE;
+ musb_dma_completion(musb, hw_ep->epnum,
+ ux500_channel->is_tx);
+ spin_unlock_irqrestore(&musb->lock, flags);
+}
+
+/* Work function invoked from DMA callback to handle rx transfers. */
+static void ux500_rx_work(struct work_struct *data)
+{
+ struct ux500_dma_channel *ux500_channel = container_of(data,
+ struct ux500_dma_channel, channel_work);
+ struct musb_hw_ep *hw_ep = ux500_channel->hw_ep;
+ struct musb *musb = hw_ep->musb;
+ unsigned long flags;
+
+ DBG(4, "DMA rx transfer done on hw_ep=%d\n", hw_ep->epnum);
+
+ spin_lock_irqsave(&musb->lock, flags);
+ ux500_channel->channel.actual_len = ux500_channel->cur_len;
+ ux500_channel->channel.status = MUSB_DMA_STATUS_FREE;
+ musb_dma_completion(musb, hw_ep->epnum,
+ ux500_channel->is_tx);
+ spin_unlock_irqrestore(&musb->lock, flags);
+}
+
+void ux500_dma_callback(void *private_data)
+{
+ struct dma_channel *channel = (struct dma_channel *)private_data;
+ struct ux500_dma_channel *ux500_channel = channel->private_data;
+
+ schedule_work(&ux500_channel->channel_work);
+}
+
+static bool ux500_configure_channel(struct dma_channel *channel,
+ u16 packet_sz, u8 mode,
+ dma_addr_t dma_addr, u32 len)
+{
+ struct ux500_dma_channel *ux500_channel = channel->private_data;
+ struct musb_hw_ep *hw_ep = ux500_channel->hw_ep;
+ struct dma_chan *dma_chan = ux500_channel->dma_chan;
+ struct dma_async_tx_descriptor *dma_desc;
+ enum dma_data_direction direction;
+ struct scatterlist sg;
+ struct dma_slave_config slave_conf;
+ enum dma_slave_buswidth addr_width;
+ dma_addr_t usb_fifo_addr = (MUSB_FIFO_OFFSET(hw_ep->epnum) +
+ ux500_channel->controller->phy_base);
+
+ DBG(4, "packet_sz=%d, mode=%d, dma_addr=0x%x, len=%d is_tx=%d\n",
+ packet_sz, mode, dma_addr, len, ux500_channel->is_tx);
+
+ ux500_channel->cur_len = len;
+
+ sg_init_table(&sg, 1);
+ sg_set_page(&sg, pfn_to_page(PFN_DOWN(dma_addr)), len,
+ offset_in_page(dma_addr));
+ sg_dma_address(&sg) = dma_addr;
+ sg_dma_len(&sg) = len;
+
+ direction = ux500_channel->is_tx ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
+ addr_width = (len & 0x3) ? DMA_SLAVE_BUSWIDTH_1_BYTE :
+ DMA_SLAVE_BUSWIDTH_4_BYTES;
+
+ slave_conf.direction = direction;
+ if (direction == DMA_FROM_DEVICE) {
+ slave_conf.src_addr = usb_fifo_addr;
+ slave_conf.src_addr_width = addr_width;
+ slave_conf.src_maxburst = 16;
+ } else {
+ slave_conf.dst_addr = usb_fifo_addr;
+ slave_conf.dst_addr_width = addr_width;
+ slave_conf.dst_maxburst = 16;
+ }
+ dma_chan->device->device_control(dma_chan, DMA_SLAVE_CONFIG,
+ (unsigned long) &slave_conf);
+
+ dma_desc = dma_chan->device->
+ device_prep_slave_sg(dma_chan, &sg, 1, direction,
+ DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
+ if (!dma_desc)
+ return false;
+
+ dma_desc->callback = ux500_dma_callback;
+ dma_desc->callback_param = channel;
+ ux500_channel->cookie = dma_desc->tx_submit(dma_desc);
+
+ dma_async_issue_pending(dma_chan);
+
+ return true;
+}
+
+static struct dma_channel *ux500_dma_channel_allocate(struct dma_controller *c,
+ struct musb_hw_ep *hw_ep, u8 is_tx)
+{
+ struct ux500_dma_controller *controller = container_of(c,
+ struct ux500_dma_controller, controller);
+ struct ux500_dma_channel *ux500_channel = NULL;
+ u8 ch_num = hw_ep->epnum - 1;
+ u32 max_ch;
+
+ /* Max 8 DMA channels (0 - 7). Each DMA channel can only be allocated
+ * to specified hw_ep. For example DMA channel 0 can only be allocated
+ * to hw_ep 1 and 9.
+ */
+ if (ch_num > 7)
+ ch_num -= 8;
+
+ max_ch = is_tx ? controller->num_tx_channels :
+ controller->num_rx_channels;
+
+ if (ch_num >= max_ch)
+ return NULL;
+
+ ux500_channel = is_tx ? &(controller->tx_channel[ch_num]) :
+ &(controller->rx_channel[ch_num]) ;
+
+ /* Check if channel is already used. */
+ if (ux500_channel->is_allocated)
+ return NULL;
+
+ ux500_channel->hw_ep = hw_ep;
+ ux500_channel->is_allocated = 1;
+
+ DBG(7, "hw_ep=%d, is_tx=0x%x, channel=%d\n",
+ hw_ep->epnum, is_tx, ch_num);
+
+ return &(ux500_channel->channel);
+}
+
+static void ux500_dma_channel_release(struct dma_channel *channel)
+{
+ struct ux500_dma_channel *ux500_channel = channel->private_data;
+
+ DBG(7, "channel=%d\n", ux500_channel->ch_num);
+
+ if (ux500_channel->is_allocated) {
+ ux500_channel->is_allocated = 0;
+ channel->status = MUSB_DMA_STATUS_FREE;
+ channel->actual_len = 0;
+ }
+}
+
+static int ux500_dma_is_compatible(struct dma_channel *channel,
+ u16 maxpacket, void *buf, u32 length)
+{
+ if ((maxpacket & 0x3) ||
+ ((int)buf & 0x3) ||
+ (length < 512) ||
+ (length & 0x3))
+ return false;
+ else
+ return true;
+}
+
+static int ux500_dma_channel_program(struct dma_channel *channel,
+ u16 packet_sz, u8 mode,
+ dma_addr_t dma_addr, u32 len)
+{
+ int ret;
+
+ BUG_ON(channel->status == MUSB_DMA_STATUS_UNKNOWN ||
+ channel->status == MUSB_DMA_STATUS_BUSY);
+
+ if (!ux500_dma_is_compatible(channel, packet_sz, (void *)dma_addr, len))
+ return false;
+
+ channel->status = MUSB_DMA_STATUS_BUSY;
+ channel->actual_len = 0;
+ ret = ux500_configure_channel(channel, packet_sz, mode, dma_addr, len);
+ if (!ret)
+ channel->status = MUSB_DMA_STATUS_FREE;
+
+ return ret;
+}
+
+static int ux500_dma_channel_abort(struct dma_channel *channel)
+{
+ struct ux500_dma_channel *ux500_channel = channel->private_data;
+ struct ux500_dma_controller *controller = ux500_channel->controller;
+ struct musb *musb = controller->private_data;
+ void __iomem *epio = musb->endpoints[ux500_channel->hw_ep->epnum].regs;
+ u16 csr;
+
+ DBG(4, "channel=%d, is_tx=%d\n", ux500_channel->ch_num,
+ ux500_channel->is_tx);
+
+ if (channel->status == MUSB_DMA_STATUS_BUSY) {
+ if (ux500_channel->is_tx) {
+ csr = musb_readw(epio, MUSB_TXCSR);
+ csr &= ~(MUSB_TXCSR_AUTOSET |
+ MUSB_TXCSR_DMAENAB |
+ MUSB_TXCSR_DMAMODE);
+ musb_writew(epio, MUSB_TXCSR, csr);
+ } else {
+ csr = musb_readw(epio, MUSB_RXCSR);
+ csr &= ~(MUSB_RXCSR_AUTOCLEAR |
+ MUSB_RXCSR_DMAENAB |
+ MUSB_RXCSR_DMAMODE);
+ musb_writew(epio, MUSB_RXCSR, csr);
+ }
+
+ ux500_channel->dma_chan->device->
+ device_control(ux500_channel->dma_chan,
+ DMA_TERMINATE_ALL, 0);
+ channel->status = MUSB_DMA_STATUS_FREE;
+ }
+ return 0;
+}
+
+static int ux500_dma_controller_stop(struct dma_controller *c)
+{
+ struct ux500_dma_controller *controller = container_of(c,
+ struct ux500_dma_controller, controller);
+ struct ux500_dma_channel *ux500_channel;
+ struct dma_channel *channel;
+ u8 ch_num;
+
+ for (ch_num = 0; ch_num < controller->num_rx_channels; ch_num++) {
+ channel = &controller->rx_channel[ch_num].channel;
+ ux500_channel = channel->private_data;
+
+ ux500_dma_channel_release(channel);
+
+ if (ux500_channel->dma_chan)
+ dma_release_channel(ux500_channel->dma_chan);
+ }
+
+ for (ch_num = 0; ch_num < controller->num_tx_channels; ch_num++) {
+ channel = &controller->tx_channel[ch_num].channel;
+ ux500_channel = channel->private_data;
+
+ ux500_dma_channel_release(channel);
+
+ if (ux500_channel->dma_chan)
+ dma_release_channel(ux500_channel->dma_chan);
+ }
+
+ return 0;
+}
+
+static int ux500_dma_controller_start(struct dma_controller *c)
+{
+ struct ux500_dma_controller *controller = container_of(c,
+ struct ux500_dma_controller, controller);
+ struct ux500_dma_channel *ux500_channel = NULL;
+ struct musb *musb = controller->private_data;
+ struct device *dev = musb->controller;
+ struct musb_hdrc_platform_data *plat = dev->platform_data;
+ struct ux500_musb_board_data *data = plat->board_data;
+ struct dma_channel *dma_channel = NULL;
+ u32 ch_num;
+ u8 dir;
+ u8 is_tx = 0;
+
+ void **param_array;
+ struct ux500_dma_channel *channel_array;
+ u32 ch_count;
+ void (*musb_channel_work)(struct work_struct *);
+ dma_cap_mask_t mask;
+
+ if ((data->num_rx_channels > UX500_MUSB_DMA_NUM_RX_CHANNELS) ||
+ (data->num_tx_channels > UX500_MUSB_DMA_NUM_TX_CHANNELS))
+ return -EINVAL;
+
+ controller->num_rx_channels = data->num_rx_channels;
+ controller->num_tx_channels = data->num_tx_channels;
+
+ dma_cap_zero(mask);
+ dma_cap_set(DMA_SLAVE, mask);
+
+ /* Prepare the loop for RX channels */
+ channel_array = controller->rx_channel;
+ ch_count = data->num_rx_channels;
+ param_array = data->dma_rx_param_array;
+ musb_channel_work = ux500_rx_work;
+
+ for (dir = 0; dir < 2; dir++) {
+ for (ch_num = 0; ch_num < ch_count; ch_num++) {
+ ux500_channel = &channel_array[ch_num];
+ ux500_channel->controller = controller;
+ ux500_channel->ch_num = ch_num;
+ ux500_channel->is_tx = is_tx;
+
+ dma_channel = &(ux500_channel->channel);
+ dma_channel->private_data = ux500_channel;
+ dma_channel->status = MUSB_DMA_STATUS_FREE;
+ dma_channel->max_len = SZ_16M;
+
+ ux500_channel->dma_chan = dma_request_channel(mask,
+ data->dma_filter,
+ param_array[ch_num]);
+ if (!ux500_channel->dma_chan) {
+ ERR("Dma pipe allocation error dir=%d ch=%d\n",
+ dir, ch_num);
+
+ /* Release already allocated channels */
+ ux500_dma_controller_stop(c);
+
+ return -EBUSY;
+ }
+
+ INIT_WORK(&ux500_channel->channel_work,
+ musb_channel_work);
+ }
+
+ /* Prepare the loop for TX channels */
+ channel_array = controller->tx_channel;
+ ch_count = data->num_tx_channels;
+ param_array = data->dma_tx_param_array;
+ musb_channel_work = ux500_tx_work;
+ is_tx = 1;
+ }
+
+ return 0;
+}
+
+void dma_controller_destroy(struct dma_controller *c)
+{
+ struct ux500_dma_controller *controller = container_of(c,
+ struct ux500_dma_controller, controller);
+
+ kfree(controller);
+}
+
+struct dma_controller *__init
+dma_controller_create(struct musb *musb, void __iomem *base)
+{
+ struct ux500_dma_controller *controller;
+ struct platform_device *pdev = to_platform_device(musb->controller);
+ struct resource *iomem;
+
+ controller = kzalloc(sizeof(*controller), GFP_KERNEL);
+ if (!controller)
+ return NULL;
+
+ controller->private_data = musb;
+
+ /* Save physical address for DMA controller. */
+ iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ controller->phy_base = (dma_addr_t) iomem->start;
+
+ controller->controller.start = ux500_dma_controller_start;
+ controller->controller.stop = ux500_dma_controller_stop;
+ controller->controller.channel_alloc = ux500_dma_channel_allocate;
+ controller->controller.channel_release = ux500_dma_channel_release;
+ controller->controller.channel_program = ux500_dma_channel_program;
+ controller->controller.channel_abort = ux500_dma_channel_abort;
+ controller->controller.is_compatible = ux500_dma_is_compatible;
+
+ return &controller->controller;
+}
diff --git a/drivers/usb/otg/Kconfig b/drivers/usb/otg/Kconfig
index daf3e5f..c66481a 100644
--- a/drivers/usb/otg/Kconfig
+++ b/drivers/usb/otg/Kconfig
@@ -122,4 +122,12 @@
This transceiver supports high and full speed devices plus,
in host mode, low speed.
+config FSL_USB2_OTG
+ bool "Freescale USB OTG Transceiver Driver"
+ depends on USB_EHCI_FSL && USB_GADGET_FSL_USB2
+ select USB_OTG
+ select USB_OTG_UTILS
+ help
+ Enable this to support Freescale USB OTG transceiver.
+
endif # USB || OTG
diff --git a/drivers/usb/otg/Makefile b/drivers/usb/otg/Makefile
index e22d917..566655c 100644
--- a/drivers/usb/otg/Makefile
+++ b/drivers/usb/otg/Makefile
@@ -19,3 +19,5 @@
obj-$(CONFIG_USB_ULPI_VIEWPORT) += ulpi_viewport.o
obj-$(CONFIG_USB_MSM_OTG) += msm_otg.o
obj-$(CONFIG_AB8500_USB) += ab8500-usb.o
+fsl_usb2_otg-objs := fsl_otg.o otg_fsm.o
+obj-$(CONFIG_FSL_USB2_OTG) += fsl_usb2_otg.o
diff --git a/drivers/usb/otg/fsl_otg.c b/drivers/usb/otg/fsl_otg.c
new file mode 100644
index 0000000..0f420b2
--- /dev/null
+++ b/drivers/usb/otg/fsl_otg.c
@@ -0,0 +1,1169 @@
+/*
+ * Copyright (C) 2007,2008 Freescale semiconductor, Inc.
+ *
+ * Author: Li Yang <LeoLi@freescale.com>
+ * Jerry Huang <Chang-Ming.Huang@freescale.com>
+ *
+ * Initialization based on code from Shlomi Gridish.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/slab.h>
+#include <linux/proc_fs.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/timer.h>
+#include <linux/usb.h>
+#include <linux/device.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#include <linux/workqueue.h>
+#include <linux/time.h>
+#include <linux/fsl_devices.h>
+#include <linux/platform_device.h>
+#include <linux/uaccess.h>
+
+#include <asm/unaligned.h>
+
+#include "fsl_otg.h"
+
+#define DRIVER_VERSION "Rev. 1.55"
+#define DRIVER_AUTHOR "Jerry Huang/Li Yang"
+#define DRIVER_DESC "Freescale USB OTG Transceiver Driver"
+#define DRIVER_INFO DRIVER_DESC " " DRIVER_VERSION
+
+static const char driver_name[] = "fsl-usb2-otg";
+
+const pm_message_t otg_suspend_state = {
+ .event = 1,
+};
+
+#define HA_DATA_PULSE
+
+static struct usb_dr_mmap *usb_dr_regs;
+static struct fsl_otg *fsl_otg_dev;
+static int srp_wait_done;
+
+/* FSM timers */
+struct fsl_otg_timer *a_wait_vrise_tmr, *a_wait_bcon_tmr, *a_aidl_bdis_tmr,
+ *b_ase0_brst_tmr, *b_se0_srp_tmr;
+
+/* Driver specific timers */
+struct fsl_otg_timer *b_data_pulse_tmr, *b_vbus_pulse_tmr, *b_srp_fail_tmr,
+ *b_srp_wait_tmr, *a_wait_enum_tmr;
+
+static struct list_head active_timers;
+
+static struct fsl_otg_config fsl_otg_initdata = {
+ .otg_port = 1,
+};
+
+#ifdef CONFIG_PPC32
+static u32 _fsl_readl_be(const unsigned __iomem *p)
+{
+ return in_be32(p);
+}
+
+static u32 _fsl_readl_le(const unsigned __iomem *p)
+{
+ return in_le32(p);
+}
+
+static void _fsl_writel_be(u32 v, unsigned __iomem *p)
+{
+ out_be32(p, v);
+}
+
+static void _fsl_writel_le(u32 v, unsigned __iomem *p)
+{
+ out_le32(p, v);
+}
+
+static u32 (*_fsl_readl)(const unsigned __iomem *p);
+static void (*_fsl_writel)(u32 v, unsigned __iomem *p);
+
+#define fsl_readl(p) (*_fsl_readl)((p))
+#define fsl_writel(v, p) (*_fsl_writel)((v), (p))
+
+#else
+#define fsl_readl(addr) readl(addr)
+#define fsl_writel(val, addr) writel(val, addr)
+#endif /* CONFIG_PPC32 */
+
+/* Routines to access transceiver ULPI registers */
+u8 view_ulpi(u8 addr)
+{
+ u32 temp;
+
+ temp = 0x40000000 | (addr << 16);
+ fsl_writel(temp, &usb_dr_regs->ulpiview);
+ udelay(1000);
+ while (temp & 0x40)
+ temp = fsl_readl(&usb_dr_regs->ulpiview);
+ return (le32_to_cpu(temp) & 0x0000ff00) >> 8;
+}
+
+int write_ulpi(u8 addr, u8 data)
+{
+ u32 temp;
+
+ temp = 0x60000000 | (addr << 16) | data;
+ fsl_writel(temp, &usb_dr_regs->ulpiview);
+ return 0;
+}
+
+/* -------------------------------------------------------------*/
+/* Operations that will be called from OTG Finite State Machine */
+
+/* Charge vbus for vbus pulsing in SRP */
+void fsl_otg_chrg_vbus(int on)
+{
+ u32 tmp;
+
+ tmp = fsl_readl(&usb_dr_regs->otgsc) & ~OTGSC_INTSTS_MASK;
+
+ if (on)
+ /* stop discharging, start charging */
+ tmp = (tmp & ~OTGSC_CTRL_VBUS_DISCHARGE) |
+ OTGSC_CTRL_VBUS_CHARGE;
+ else
+ /* stop charging */
+ tmp &= ~OTGSC_CTRL_VBUS_CHARGE;
+
+ fsl_writel(tmp, &usb_dr_regs->otgsc);
+}
+
+/* Discharge vbus through a resistor to ground */
+void fsl_otg_dischrg_vbus(int on)
+{
+ u32 tmp;
+
+ tmp = fsl_readl(&usb_dr_regs->otgsc) & ~OTGSC_INTSTS_MASK;
+
+ if (on)
+ /* stop charging, start discharging */
+ tmp = (tmp & ~OTGSC_CTRL_VBUS_CHARGE) |
+ OTGSC_CTRL_VBUS_DISCHARGE;
+ else
+ /* stop discharging */
+ tmp &= ~OTGSC_CTRL_VBUS_DISCHARGE;
+
+ fsl_writel(tmp, &usb_dr_regs->otgsc);
+}
+
+/* A-device driver vbus, controlled through PP bit in PORTSC */
+void fsl_otg_drv_vbus(int on)
+{
+ u32 tmp;
+
+ if (on) {
+ tmp = fsl_readl(&usb_dr_regs->portsc) & ~PORTSC_W1C_BITS;
+ fsl_writel(tmp | PORTSC_PORT_POWER, &usb_dr_regs->portsc);
+ } else {
+ tmp = fsl_readl(&usb_dr_regs->portsc) &
+ ~PORTSC_W1C_BITS & ~PORTSC_PORT_POWER;
+ fsl_writel(tmp, &usb_dr_regs->portsc);
+ }
+}
+
+/*
+ * Pull-up D+, signalling connect by periperal. Also used in
+ * data-line pulsing in SRP
+ */
+void fsl_otg_loc_conn(int on)
+{
+ u32 tmp;
+
+ tmp = fsl_readl(&usb_dr_regs->otgsc) & ~OTGSC_INTSTS_MASK;
+
+ if (on)
+ tmp |= OTGSC_CTRL_DATA_PULSING;
+ else
+ tmp &= ~OTGSC_CTRL_DATA_PULSING;
+
+ fsl_writel(tmp, &usb_dr_regs->otgsc);
+}
+
+/*
+ * Generate SOF by host. This is controlled through suspend/resume the
+ * port. In host mode, controller will automatically send SOF.
+ * Suspend will block the data on the port.
+ */
+void fsl_otg_loc_sof(int on)
+{
+ u32 tmp;
+
+ tmp = fsl_readl(&fsl_otg_dev->dr_mem_map->portsc) & ~PORTSC_W1C_BITS;
+ if (on)
+ tmp |= PORTSC_PORT_FORCE_RESUME;
+ else
+ tmp |= PORTSC_PORT_SUSPEND;
+
+ fsl_writel(tmp, &fsl_otg_dev->dr_mem_map->portsc);
+
+}
+
+/* Start SRP pulsing by data-line pulsing, followed with v-bus pulsing. */
+void fsl_otg_start_pulse(void)
+{
+ u32 tmp;
+
+ srp_wait_done = 0;
+#ifdef HA_DATA_PULSE
+ tmp = fsl_readl(&usb_dr_regs->otgsc) & ~OTGSC_INTSTS_MASK;
+ tmp |= OTGSC_HA_DATA_PULSE;
+ fsl_writel(tmp, &usb_dr_regs->otgsc);
+#else
+ fsl_otg_loc_conn(1);
+#endif
+
+ fsl_otg_add_timer(b_data_pulse_tmr);
+}
+
+void b_data_pulse_end(unsigned long foo)
+{
+#ifdef HA_DATA_PULSE
+#else
+ fsl_otg_loc_conn(0);
+#endif
+
+ /* Do VBUS pulse after data pulse */
+ fsl_otg_pulse_vbus();
+}
+
+void fsl_otg_pulse_vbus(void)
+{
+ srp_wait_done = 0;
+ fsl_otg_chrg_vbus(1);
+ /* start the timer to end vbus charge */
+ fsl_otg_add_timer(b_vbus_pulse_tmr);
+}
+
+void b_vbus_pulse_end(unsigned long foo)
+{
+ fsl_otg_chrg_vbus(0);
+
+ /*
+ * As USB3300 using the same a_sess_vld and b_sess_vld voltage
+ * we need to discharge the bus for a while to distinguish
+ * residual voltage of vbus pulsing and A device pull up
+ */
+ fsl_otg_dischrg_vbus(1);
+ fsl_otg_add_timer(b_srp_wait_tmr);
+}
+
+void b_srp_end(unsigned long foo)
+{
+ fsl_otg_dischrg_vbus(0);
+ srp_wait_done = 1;
+
+ if ((fsl_otg_dev->otg.state == OTG_STATE_B_SRP_INIT) &&
+ fsl_otg_dev->fsm.b_sess_vld)
+ fsl_otg_dev->fsm.b_srp_done = 1;
+}
+
+/*
+ * Workaround for a_host suspending too fast. When a_bus_req=0,
+ * a_host will start by SRP. It needs to set b_hnp_enable before
+ * actually suspending to start HNP
+ */
+void a_wait_enum(unsigned long foo)
+{
+ VDBG("a_wait_enum timeout\n");
+ if (!fsl_otg_dev->otg.host->b_hnp_enable)
+ fsl_otg_add_timer(a_wait_enum_tmr);
+ else
+ otg_statemachine(&fsl_otg_dev->fsm);
+}
+
+/* The timeout callback function to set time out bit */
+void set_tmout(unsigned long indicator)
+{
+ *(int *)indicator = 1;
+}
+
+/* Initialize timers */
+int fsl_otg_init_timers(struct otg_fsm *fsm)
+{
+ /* FSM used timers */
+ a_wait_vrise_tmr = otg_timer_initializer(&set_tmout, TA_WAIT_VRISE,
+ (unsigned long)&fsm->a_wait_vrise_tmout);
+ if (!a_wait_vrise_tmr)
+ return -ENOMEM;
+
+ a_wait_bcon_tmr = otg_timer_initializer(&set_tmout, TA_WAIT_BCON,
+ (unsigned long)&fsm->a_wait_bcon_tmout);
+ if (!a_wait_bcon_tmr)
+ return -ENOMEM;
+
+ a_aidl_bdis_tmr = otg_timer_initializer(&set_tmout, TA_AIDL_BDIS,
+ (unsigned long)&fsm->a_aidl_bdis_tmout);
+ if (!a_aidl_bdis_tmr)
+ return -ENOMEM;
+
+ b_ase0_brst_tmr = otg_timer_initializer(&set_tmout, TB_ASE0_BRST,
+ (unsigned long)&fsm->b_ase0_brst_tmout);
+ if (!b_ase0_brst_tmr)
+ return -ENOMEM;
+
+ b_se0_srp_tmr = otg_timer_initializer(&set_tmout, TB_SE0_SRP,
+ (unsigned long)&fsm->b_se0_srp);
+ if (!b_se0_srp_tmr)
+ return -ENOMEM;
+
+ b_srp_fail_tmr = otg_timer_initializer(&set_tmout, TB_SRP_FAIL,
+ (unsigned long)&fsm->b_srp_done);
+ if (!b_srp_fail_tmr)
+ return -ENOMEM;
+
+ a_wait_enum_tmr = otg_timer_initializer(&a_wait_enum, 10,
+ (unsigned long)&fsm);
+ if (!a_wait_enum_tmr)
+ return -ENOMEM;
+
+ /* device driver used timers */
+ b_srp_wait_tmr = otg_timer_initializer(&b_srp_end, TB_SRP_WAIT, 0);
+ if (!b_srp_wait_tmr)
+ return -ENOMEM;
+
+ b_data_pulse_tmr = otg_timer_initializer(&b_data_pulse_end,
+ TB_DATA_PLS, 0);
+ if (!b_data_pulse_tmr)
+ return -ENOMEM;
+
+ b_vbus_pulse_tmr = otg_timer_initializer(&b_vbus_pulse_end,
+ TB_VBUS_PLS, 0);
+ if (!b_vbus_pulse_tmr)
+ return -ENOMEM;
+
+ return 0;
+}
+
+/* Uninitialize timers */
+void fsl_otg_uninit_timers(void)
+{
+ /* FSM used timers */
+ if (a_wait_vrise_tmr != NULL)
+ kfree(a_wait_vrise_tmr);
+ if (a_wait_bcon_tmr != NULL)
+ kfree(a_wait_bcon_tmr);
+ if (a_aidl_bdis_tmr != NULL)
+ kfree(a_aidl_bdis_tmr);
+ if (b_ase0_brst_tmr != NULL)
+ kfree(b_ase0_brst_tmr);
+ if (b_se0_srp_tmr != NULL)
+ kfree(b_se0_srp_tmr);
+ if (b_srp_fail_tmr != NULL)
+ kfree(b_srp_fail_tmr);
+ if (a_wait_enum_tmr != NULL)
+ kfree(a_wait_enum_tmr);
+
+ /* device driver used timers */
+ if (b_srp_wait_tmr != NULL)
+ kfree(b_srp_wait_tmr);
+ if (b_data_pulse_tmr != NULL)
+ kfree(b_data_pulse_tmr);
+ if (b_vbus_pulse_tmr != NULL)
+ kfree(b_vbus_pulse_tmr);
+}
+
+/* Add timer to timer list */
+void fsl_otg_add_timer(void *gtimer)
+{
+ struct fsl_otg_timer *timer = gtimer;
+ struct fsl_otg_timer *tmp_timer;
+
+ /*
+ * Check if the timer is already in the active list,
+ * if so update timer count
+ */
+ list_for_each_entry(tmp_timer, &active_timers, list)
+ if (tmp_timer == timer) {
+ timer->count = timer->expires;
+ return;
+ }
+ timer->count = timer->expires;
+ list_add_tail(&timer->list, &active_timers);
+}
+
+/* Remove timer from the timer list; clear timeout status */
+void fsl_otg_del_timer(void *gtimer)
+{
+ struct fsl_otg_timer *timer = gtimer;
+ struct fsl_otg_timer *tmp_timer, *del_tmp;
+
+ list_for_each_entry_safe(tmp_timer, del_tmp, &active_timers, list)
+ if (tmp_timer == timer)
+ list_del(&timer->list);
+}
+
+/*
+ * Reduce timer count by 1, and find timeout conditions.
+ * Called by fsl_otg 1ms timer interrupt
+ */
+int fsl_otg_tick_timer(void)
+{
+ struct fsl_otg_timer *tmp_timer, *del_tmp;
+ int expired = 0;
+
+ list_for_each_entry_safe(tmp_timer, del_tmp, &active_timers, list) {
+ tmp_timer->count--;
+ /* check if timer expires */
+ if (!tmp_timer->count) {
+ list_del(&tmp_timer->list);
+ tmp_timer->function(tmp_timer->data);
+ expired = 1;
+ }
+ }
+
+ return expired;
+}
+
+/* Reset controller, not reset the bus */
+void otg_reset_controller(void)
+{
+ u32 command;
+
+ command = fsl_readl(&usb_dr_regs->usbcmd);
+ command |= (1 << 1);
+ fsl_writel(command, &usb_dr_regs->usbcmd);
+ while (fsl_readl(&usb_dr_regs->usbcmd) & (1 << 1))
+ ;
+}
+
+/* Call suspend/resume routines in host driver */
+int fsl_otg_start_host(struct otg_fsm *fsm, int on)
+{
+ struct otg_transceiver *xceiv = fsm->transceiver;
+ struct device *dev;
+ struct fsl_otg *otg_dev = container_of(xceiv, struct fsl_otg, otg);
+ u32 retval = 0;
+
+ if (!xceiv->host)
+ return -ENODEV;
+ dev = xceiv->host->controller;
+
+ /*
+ * Update a_vbus_vld state as a_vbus_vld int is disabled
+ * in device mode
+ */
+ fsm->a_vbus_vld =
+ !!(fsl_readl(&usb_dr_regs->otgsc) & OTGSC_STS_A_VBUS_VALID);
+ if (on) {
+ /* start fsl usb host controller */
+ if (otg_dev->host_working)
+ goto end;
+ else {
+ otg_reset_controller();
+ VDBG("host on......\n");
+ if (dev->driver->pm && dev->driver->pm->resume) {
+ retval = dev->driver->pm->resume(dev);
+ if (fsm->id) {
+ /* default-b */
+ fsl_otg_drv_vbus(1);
+ /*
+ * Workaround: b_host can't driver
+ * vbus, but PP in PORTSC needs to
+ * be 1 for host to work.
+ * So we set drv_vbus bit in
+ * transceiver to 0 thru ULPI.
+ */
+ write_ulpi(0x0c, 0x20);
+ }
+ }
+
+ otg_dev->host_working = 1;
+ }
+ } else {
+ /* stop fsl usb host controller */
+ if (!otg_dev->host_working)
+ goto end;
+ else {
+ VDBG("host off......\n");
+ if (dev && dev->driver) {
+ if (dev->driver->pm && dev->driver->pm->suspend)
+ retval = dev->driver->pm->suspend(dev);
+ if (fsm->id)
+ /* default-b */
+ fsl_otg_drv_vbus(0);
+ }
+ otg_dev->host_working = 0;
+ }
+ }
+end:
+ return retval;
+}
+
+/*
+ * Call suspend and resume function in udc driver
+ * to stop and start udc driver.
+ */
+int fsl_otg_start_gadget(struct otg_fsm *fsm, int on)
+{
+ struct otg_transceiver *xceiv = fsm->transceiver;
+ struct device *dev;
+
+ if (!xceiv->gadget || !xceiv->gadget->dev.parent)
+ return -ENODEV;
+
+ VDBG("gadget %s\n", on ? "on" : "off");
+ dev = xceiv->gadget->dev.parent;
+
+ if (on) {
+ if (dev->driver->resume)
+ dev->driver->resume(dev);
+ } else {
+ if (dev->driver->suspend)
+ dev->driver->suspend(dev, otg_suspend_state);
+ }
+
+ return 0;
+}
+
+/*
+ * Called by initialization code of host driver. Register host controller
+ * to the OTG. Suspend host for OTG role detection.
+ */
+static int fsl_otg_set_host(struct otg_transceiver *otg_p, struct usb_bus *host)
+{
+ struct fsl_otg *otg_dev = container_of(otg_p, struct fsl_otg, otg);
+
+ if (!otg_p || otg_dev != fsl_otg_dev)
+ return -ENODEV;
+
+ otg_p->host = host;
+
+ otg_dev->fsm.a_bus_drop = 0;
+ otg_dev->fsm.a_bus_req = 1;
+
+ if (host) {
+ VDBG("host off......\n");
+
+ otg_p->host->otg_port = fsl_otg_initdata.otg_port;
+ otg_p->host->is_b_host = otg_dev->fsm.id;
+ /*
+ * must leave time for khubd to finish its thing
+ * before yanking the host driver out from under it,
+ * so suspend the host after a short delay.
+ */
+ otg_dev->host_working = 1;
+ schedule_delayed_work(&otg_dev->otg_event, 100);
+ return 0;
+ } else {
+ /* host driver going away */
+ if (!(fsl_readl(&otg_dev->dr_mem_map->otgsc) &
+ OTGSC_STS_USB_ID)) {
+ /* Mini-A cable connected */
+ struct otg_fsm *fsm = &otg_dev->fsm;
+
+ otg_p->state = OTG_STATE_UNDEFINED;
+ fsm->protocol = PROTO_UNDEF;
+ }
+ }
+
+ otg_dev->host_working = 0;
+
+ otg_statemachine(&otg_dev->fsm);
+
+ return 0;
+}
+
+/* Called by initialization code of udc. Register udc to OTG. */
+static int fsl_otg_set_peripheral(struct otg_transceiver *otg_p,
+ struct usb_gadget *gadget)
+{
+ struct fsl_otg *otg_dev = container_of(otg_p, struct fsl_otg, otg);
+
+ VDBG("otg_dev 0x%x\n", (int)otg_dev);
+ VDBG("fsl_otg_dev 0x%x\n", (int)fsl_otg_dev);
+
+ if (!otg_p || otg_dev != fsl_otg_dev)
+ return -ENODEV;
+
+ if (!gadget) {
+ if (!otg_dev->otg.default_a)
+ otg_p->gadget->ops->vbus_draw(otg_p->gadget, 0);
+ usb_gadget_vbus_disconnect(otg_dev->otg.gadget);
+ otg_dev->otg.gadget = 0;
+ otg_dev->fsm.b_bus_req = 0;
+ otg_statemachine(&otg_dev->fsm);
+ return 0;
+ }
+
+ otg_p->gadget = gadget;
+ otg_p->gadget->is_a_peripheral = !otg_dev->fsm.id;
+
+ otg_dev->fsm.b_bus_req = 1;
+
+ /* start the gadget right away if the ID pin says Mini-B */
+ DBG("ID pin=%d\n", otg_dev->fsm.id);
+ if (otg_dev->fsm.id == 1) {
+ fsl_otg_start_host(&otg_dev->fsm, 0);
+ otg_drv_vbus(&otg_dev->fsm, 0);
+ fsl_otg_start_gadget(&otg_dev->fsm, 1);
+ }
+
+ return 0;
+}
+
+/* Set OTG port power, only for B-device */
+static int fsl_otg_set_power(struct otg_transceiver *otg_p, unsigned mA)
+{
+ if (!fsl_otg_dev)
+ return -ENODEV;
+ if (otg_p->state == OTG_STATE_B_PERIPHERAL)
+ pr_info("FSL OTG: Draw %d mA\n", mA);
+
+ return 0;
+}
+
+/*
+ * Delayed pin detect interrupt processing.
+ *
+ * When the Mini-A cable is disconnected from the board,
+ * the pin-detect interrupt happens before the disconnnect
+ * interrupts for the connected device(s). In order to
+ * process the disconnect interrupt(s) prior to switching
+ * roles, the pin-detect interrupts are delayed, and handled
+ * by this routine.
+ */
+static void fsl_otg_event(struct work_struct *work)
+{
+ struct fsl_otg *og = container_of(work, struct fsl_otg, otg_event.work);
+ struct otg_fsm *fsm = &og->fsm;
+
+ if (fsm->id) { /* switch to gadget */
+ fsl_otg_start_host(fsm, 0);
+ otg_drv_vbus(fsm, 0);
+ fsl_otg_start_gadget(fsm, 1);
+ }
+}
+
+/* B-device start SRP */
+static int fsl_otg_start_srp(struct otg_transceiver *otg_p)
+{
+ struct fsl_otg *otg_dev = container_of(otg_p, struct fsl_otg, otg);
+
+ if (!otg_p || otg_dev != fsl_otg_dev
+ || otg_p->state != OTG_STATE_B_IDLE)
+ return -ENODEV;
+
+ otg_dev->fsm.b_bus_req = 1;
+ otg_statemachine(&otg_dev->fsm);
+
+ return 0;
+}
+
+/* A_host suspend will call this function to start hnp */
+static int fsl_otg_start_hnp(struct otg_transceiver *otg_p)
+{
+ struct fsl_otg *otg_dev = container_of(otg_p, struct fsl_otg, otg);
+
+ if (!otg_p || otg_dev != fsl_otg_dev)
+ return -ENODEV;
+
+ DBG("start_hnp...n");
+
+ /* clear a_bus_req to enter a_suspend state */
+ otg_dev->fsm.a_bus_req = 0;
+ otg_statemachine(&otg_dev->fsm);
+
+ return 0;
+}
+
+/*
+ * Interrupt handler. OTG/host/peripheral share the same int line.
+ * OTG driver clears OTGSC interrupts and leaves USB interrupts
+ * intact. It needs to have knowledge of some USB interrupts
+ * such as port change.
+ */
+irqreturn_t fsl_otg_isr(int irq, void *dev_id)
+{
+ struct otg_fsm *fsm = &((struct fsl_otg *)dev_id)->fsm;
+ struct otg_transceiver *otg = &((struct fsl_otg *)dev_id)->otg;
+ u32 otg_int_src, otg_sc;
+
+ otg_sc = fsl_readl(&usb_dr_regs->otgsc);
+ otg_int_src = otg_sc & OTGSC_INTSTS_MASK & (otg_sc >> 8);
+
+ /* Only clear otg interrupts */
+ fsl_writel(otg_sc, &usb_dr_regs->otgsc);
+
+ /*FIXME: ID change not generate when init to 0 */
+ fsm->id = (otg_sc & OTGSC_STS_USB_ID) ? 1 : 0;
+ otg->default_a = (fsm->id == 0);
+
+ /* process OTG interrupts */
+ if (otg_int_src) {
+ if (otg_int_src & OTGSC_INTSTS_USB_ID) {
+ fsm->id = (otg_sc & OTGSC_STS_USB_ID) ? 1 : 0;
+ otg->default_a = (fsm->id == 0);
+ /* clear conn information */
+ if (fsm->id)
+ fsm->b_conn = 0;
+ else
+ fsm->a_conn = 0;
+
+ if (otg->host)
+ otg->host->is_b_host = fsm->id;
+ if (otg->gadget)
+ otg->gadget->is_a_peripheral = !fsm->id;
+ VDBG("ID int (ID is %d)\n", fsm->id);
+
+ if (fsm->id) { /* switch to gadget */
+ schedule_delayed_work(
+ &((struct fsl_otg *)dev_id)->otg_event,
+ 100);
+ } else { /* switch to host */
+ cancel_delayed_work(&
+ ((struct fsl_otg *)dev_id)->
+ otg_event);
+ fsl_otg_start_gadget(fsm, 0);
+ otg_drv_vbus(fsm, 1);
+ fsl_otg_start_host(fsm, 1);
+ }
+ return IRQ_HANDLED;
+ }
+ }
+ return IRQ_NONE;
+}
+
+static struct otg_fsm_ops fsl_otg_ops = {
+ .chrg_vbus = fsl_otg_chrg_vbus,
+ .drv_vbus = fsl_otg_drv_vbus,
+ .loc_conn = fsl_otg_loc_conn,
+ .loc_sof = fsl_otg_loc_sof,
+ .start_pulse = fsl_otg_start_pulse,
+
+ .add_timer = fsl_otg_add_timer,
+ .del_timer = fsl_otg_del_timer,
+
+ .start_host = fsl_otg_start_host,
+ .start_gadget = fsl_otg_start_gadget,
+};
+
+/* Initialize the global variable fsl_otg_dev and request IRQ for OTG */
+static int fsl_otg_conf(struct platform_device *pdev)
+{
+ struct fsl_otg *fsl_otg_tc;
+ int status;
+
+ if (fsl_otg_dev)
+ return 0;
+
+ /* allocate space to fsl otg device */
+ fsl_otg_tc = kzalloc(sizeof(struct fsl_otg), GFP_KERNEL);
+ if (!fsl_otg_tc)
+ return -ENOMEM;
+
+ INIT_DELAYED_WORK(&fsl_otg_tc->otg_event, fsl_otg_event);
+
+ INIT_LIST_HEAD(&active_timers);
+ status = fsl_otg_init_timers(&fsl_otg_tc->fsm);
+ if (status) {
+ pr_info("Couldn't init OTG timers\n");
+ goto err;
+ }
+ spin_lock_init(&fsl_otg_tc->fsm.lock);
+
+ /* Set OTG state machine operations */
+ fsl_otg_tc->fsm.ops = &fsl_otg_ops;
+
+ /* initialize the otg structure */
+ fsl_otg_tc->otg.label = DRIVER_DESC;
+ fsl_otg_tc->otg.set_host = fsl_otg_set_host;
+ fsl_otg_tc->otg.set_peripheral = fsl_otg_set_peripheral;
+ fsl_otg_tc->otg.set_power = fsl_otg_set_power;
+ fsl_otg_tc->otg.start_hnp = fsl_otg_start_hnp;
+ fsl_otg_tc->otg.start_srp = fsl_otg_start_srp;
+
+ fsl_otg_dev = fsl_otg_tc;
+
+ /* Store the otg transceiver */
+ status = otg_set_transceiver(&fsl_otg_tc->otg);
+ if (status) {
+ pr_warn(FSL_OTG_NAME ": unable to register OTG transceiver.\n");
+ goto err;
+ }
+
+ return 0;
+err:
+ fsl_otg_uninit_timers();
+ kfree(fsl_otg_tc);
+ return status;
+}
+
+/* OTG Initialization */
+int usb_otg_start(struct platform_device *pdev)
+{
+ struct fsl_otg *p_otg;
+ struct otg_transceiver *otg_trans = otg_get_transceiver();
+ struct otg_fsm *fsm;
+ int status;
+ struct resource *res;
+ u32 temp;
+ struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
+
+ p_otg = container_of(otg_trans, struct fsl_otg, otg);
+ fsm = &p_otg->fsm;
+
+ /* Initialize the state machine structure with default values */
+ SET_OTG_STATE(otg_trans, OTG_STATE_UNDEFINED);
+ fsm->transceiver = &p_otg->otg;
+
+ /* We don't require predefined MEM/IRQ resource index */
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res)
+ return -ENXIO;
+
+ /* We don't request_mem_region here to enable resource sharing
+ * with host/device */
+
+ usb_dr_regs = ioremap(res->start, sizeof(struct usb_dr_mmap));
+ p_otg->dr_mem_map = (struct usb_dr_mmap *)usb_dr_regs;
+ pdata->regs = (void *)usb_dr_regs;
+
+ if (pdata->init && pdata->init(pdev) != 0)
+ return -EINVAL;
+
+ if (pdata->big_endian_mmio) {
+ _fsl_readl = _fsl_readl_be;
+ _fsl_writel = _fsl_writel_be;
+ } else {
+ _fsl_readl = _fsl_readl_le;
+ _fsl_writel = _fsl_writel_le;
+ }
+
+ /* request irq */
+ p_otg->irq = platform_get_irq(pdev, 0);
+ status = request_irq(p_otg->irq, fsl_otg_isr,
+ IRQF_SHARED, driver_name, p_otg);
+ if (status) {
+ dev_dbg(p_otg->otg.dev, "can't get IRQ %d, error %d\n",
+ p_otg->irq, status);
+ iounmap(p_otg->dr_mem_map);
+ kfree(p_otg);
+ return status;
+ }
+
+ /* stop the controller */
+ temp = fsl_readl(&p_otg->dr_mem_map->usbcmd);
+ temp &= ~USB_CMD_RUN_STOP;
+ fsl_writel(temp, &p_otg->dr_mem_map->usbcmd);
+
+ /* reset the controller */
+ temp = fsl_readl(&p_otg->dr_mem_map->usbcmd);
+ temp |= USB_CMD_CTRL_RESET;
+ fsl_writel(temp, &p_otg->dr_mem_map->usbcmd);
+
+ /* wait reset completed */
+ while (fsl_readl(&p_otg->dr_mem_map->usbcmd) & USB_CMD_CTRL_RESET)
+ ;
+
+ /* configure the VBUSHS as IDLE(both host and device) */
+ temp = USB_MODE_STREAM_DISABLE | (pdata->es ? USB_MODE_ES : 0);
+ fsl_writel(temp, &p_otg->dr_mem_map->usbmode);
+
+ /* configure PHY interface */
+ temp = fsl_readl(&p_otg->dr_mem_map->portsc);
+ temp &= ~(PORTSC_PHY_TYPE_SEL | PORTSC_PTW);
+ switch (pdata->phy_mode) {
+ case FSL_USB2_PHY_ULPI:
+ temp |= PORTSC_PTS_ULPI;
+ break;
+ case FSL_USB2_PHY_UTMI_WIDE:
+ temp |= PORTSC_PTW_16BIT;
+ /* fall through */
+ case FSL_USB2_PHY_UTMI:
+ temp |= PORTSC_PTS_UTMI;
+ /* fall through */
+ default:
+ break;
+ }
+ fsl_writel(temp, &p_otg->dr_mem_map->portsc);
+
+ if (pdata->have_sysif_regs) {
+ /* configure control enable IO output, big endian register */
+ temp = __raw_readl(&p_otg->dr_mem_map->control);
+ temp |= USB_CTRL_IOENB;
+ __raw_writel(temp, &p_otg->dr_mem_map->control);
+ }
+
+ /* disable all interrupt and clear all OTGSC status */
+ temp = fsl_readl(&p_otg->dr_mem_map->otgsc);
+ temp &= ~OTGSC_INTERRUPT_ENABLE_BITS_MASK;
+ temp |= OTGSC_INTERRUPT_STATUS_BITS_MASK | OTGSC_CTRL_VBUS_DISCHARGE;
+ fsl_writel(temp, &p_otg->dr_mem_map->otgsc);
+
+ /*
+ * The identification (id) input is FALSE when a Mini-A plug is inserted
+ * in the devices Mini-AB receptacle. Otherwise, this input is TRUE.
+ * Also: record initial state of ID pin
+ */
+ if (fsl_readl(&p_otg->dr_mem_map->otgsc) & OTGSC_STS_USB_ID) {
+ p_otg->otg.state = OTG_STATE_UNDEFINED;
+ p_otg->fsm.id = 1;
+ } else {
+ p_otg->otg.state = OTG_STATE_A_IDLE;
+ p_otg->fsm.id = 0;
+ }
+
+ DBG("initial ID pin=%d\n", p_otg->fsm.id);
+
+ /* enable OTG ID pin interrupt */
+ temp = fsl_readl(&p_otg->dr_mem_map->otgsc);
+ temp |= OTGSC_INTR_USB_ID_EN;
+ temp &= ~(OTGSC_CTRL_VBUS_DISCHARGE | OTGSC_INTR_1MS_TIMER_EN);
+ fsl_writel(temp, &p_otg->dr_mem_map->otgsc);
+
+ return 0;
+}
+
+/*
+ * state file in sysfs
+ */
+static int show_fsl_usb2_otg_state(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct otg_fsm *fsm = &fsl_otg_dev->fsm;
+ char *next = buf;
+ unsigned size = PAGE_SIZE;
+ unsigned long flags;
+ int t;
+
+ spin_lock_irqsave(&fsm->lock, flags);
+
+ /* basic driver infomation */
+ t = scnprintf(next, size,
+ DRIVER_DESC "\n" "fsl_usb2_otg version: %s\n\n",
+ DRIVER_VERSION);
+ size -= t;
+ next += t;
+
+ /* Registers */
+ t = scnprintf(next, size,
+ "OTGSC: 0x%08x\n"
+ "PORTSC: 0x%08x\n"
+ "USBMODE: 0x%08x\n"
+ "USBCMD: 0x%08x\n"
+ "USBSTS: 0x%08x\n"
+ "USBINTR: 0x%08x\n",
+ fsl_readl(&usb_dr_regs->otgsc),
+ fsl_readl(&usb_dr_regs->portsc),
+ fsl_readl(&usb_dr_regs->usbmode),
+ fsl_readl(&usb_dr_regs->usbcmd),
+ fsl_readl(&usb_dr_regs->usbsts),
+ fsl_readl(&usb_dr_regs->usbintr));
+ size -= t;
+ next += t;
+
+ /* State */
+ t = scnprintf(next, size,
+ "OTG state: %s\n\n",
+ otg_state_string(fsl_otg_dev->otg.state));
+ size -= t;
+ next += t;
+
+ /* State Machine Variables */
+ t = scnprintf(next, size,
+ "a_bus_req: %d\n"
+ "b_bus_req: %d\n"
+ "a_bus_resume: %d\n"
+ "a_bus_suspend: %d\n"
+ "a_conn: %d\n"
+ "a_sess_vld: %d\n"
+ "a_srp_det: %d\n"
+ "a_vbus_vld: %d\n"
+ "b_bus_resume: %d\n"
+ "b_bus_suspend: %d\n"
+ "b_conn: %d\n"
+ "b_se0_srp: %d\n"
+ "b_sess_end: %d\n"
+ "b_sess_vld: %d\n"
+ "id: %d\n",
+ fsm->a_bus_req,
+ fsm->b_bus_req,
+ fsm->a_bus_resume,
+ fsm->a_bus_suspend,
+ fsm->a_conn,
+ fsm->a_sess_vld,
+ fsm->a_srp_det,
+ fsm->a_vbus_vld,
+ fsm->b_bus_resume,
+ fsm->b_bus_suspend,
+ fsm->b_conn,
+ fsm->b_se0_srp,
+ fsm->b_sess_end,
+ fsm->b_sess_vld,
+ fsm->id);
+ size -= t;
+ next += t;
+
+ spin_unlock_irqrestore(&fsm->lock, flags);
+
+ return PAGE_SIZE - size;
+}
+
+static DEVICE_ATTR(fsl_usb2_otg_state, S_IRUGO, show_fsl_usb2_otg_state, NULL);
+
+
+/* Char driver interface to control some OTG input */
+
+/*
+ * Handle some ioctl command, such as get otg
+ * status and set host suspend
+ */
+static long fsl_otg_ioctl(struct file *file, unsigned int cmd,
+ unsigned long arg)
+{
+ u32 retval = 0;
+
+ switch (cmd) {
+ case GET_OTG_STATUS:
+ retval = fsl_otg_dev->host_working;
+ break;
+
+ case SET_A_SUSPEND_REQ:
+ fsl_otg_dev->fsm.a_suspend_req = arg;
+ break;
+
+ case SET_A_BUS_DROP:
+ fsl_otg_dev->fsm.a_bus_drop = arg;
+ break;
+
+ case SET_A_BUS_REQ:
+ fsl_otg_dev->fsm.a_bus_req = arg;
+ break;
+
+ case SET_B_BUS_REQ:
+ fsl_otg_dev->fsm.b_bus_req = arg;
+ break;
+
+ default:
+ break;
+ }
+
+ otg_statemachine(&fsl_otg_dev->fsm);
+
+ return retval;
+}
+
+static int fsl_otg_open(struct inode *inode, struct file *file)
+{
+ return 0;
+}
+
+static int fsl_otg_release(struct inode *inode, struct file *file)
+{
+ return 0;
+}
+
+static const struct file_operations otg_fops = {
+ .owner = THIS_MODULE,
+ .llseek = NULL,
+ .read = NULL,
+ .write = NULL,
+ .unlocked_ioctl = fsl_otg_ioctl,
+ .open = fsl_otg_open,
+ .release = fsl_otg_release,
+};
+
+static int __devinit fsl_otg_probe(struct platform_device *pdev)
+{
+ int ret;
+
+ if (!pdev->dev.platform_data)
+ return -ENODEV;
+
+ /* configure the OTG */
+ ret = fsl_otg_conf(pdev);
+ if (ret) {
+ dev_err(&pdev->dev, "Couldn't configure OTG module\n");
+ return ret;
+ }
+
+ /* start OTG */
+ ret = usb_otg_start(pdev);
+ if (ret) {
+ dev_err(&pdev->dev, "Can't init FSL OTG device\n");
+ return ret;
+ }
+
+ ret = register_chrdev(FSL_OTG_MAJOR, FSL_OTG_NAME, &otg_fops);
+ if (ret) {
+ dev_err(&pdev->dev, "unable to register FSL OTG device\n");
+ return ret;
+ }
+
+ ret = device_create_file(&pdev->dev, &dev_attr_fsl_usb2_otg_state);
+ if (ret)
+ dev_warn(&pdev->dev, "Can't register sysfs attribute\n");
+
+ return ret;
+}
+
+static int __devexit fsl_otg_remove(struct platform_device *pdev)
+{
+ struct fsl_usb2_platform_data *pdata = pdev->dev.platform_data;
+
+ otg_set_transceiver(NULL);
+ free_irq(fsl_otg_dev->irq, fsl_otg_dev);
+
+ iounmap((void *)usb_dr_regs);
+
+ fsl_otg_uninit_timers();
+ kfree(fsl_otg_dev);
+
+ device_remove_file(&pdev->dev, &dev_attr_fsl_usb2_otg_state);
+
+ unregister_chrdev(FSL_OTG_MAJOR, FSL_OTG_NAME);
+
+ if (pdata->exit)
+ pdata->exit(pdev);
+
+ return 0;
+}
+
+struct platform_driver fsl_otg_driver = {
+ .probe = fsl_otg_probe,
+ .remove = __devexit_p(fsl_otg_remove),
+ .driver = {
+ .name = driver_name,
+ .owner = THIS_MODULE,
+ },
+};
+
+static int __init fsl_usb_otg_init(void)
+{
+ pr_info(DRIVER_INFO "\n");
+ return platform_driver_register(&fsl_otg_driver);
+}
+module_init(fsl_usb_otg_init);
+
+static void __exit fsl_usb_otg_exit(void)
+{
+ platform_driver_unregister(&fsl_otg_driver);
+}
+module_exit(fsl_usb_otg_exit);
+
+MODULE_DESCRIPTION(DRIVER_INFO);
+MODULE_AUTHOR(DRIVER_AUTHOR);
+MODULE_LICENSE("GPL");
diff --git a/drivers/usb/otg/fsl_otg.h b/drivers/usb/otg/fsl_otg.h
new file mode 100644
index 0000000..3f8ef73
--- /dev/null
+++ b/drivers/usb/otg/fsl_otg.h
@@ -0,0 +1,406 @@
+/* Copyright (C) 2007,2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include "otg_fsm.h"
+#include <linux/usb/otg.h>
+#include <linux/ioctl.h>
+
+/* USB Command Register Bit Masks */
+#define USB_CMD_RUN_STOP (0x1<<0)
+#define USB_CMD_CTRL_RESET (0x1<<1)
+#define USB_CMD_PERIODIC_SCHEDULE_EN (0x1<<4)
+#define USB_CMD_ASYNC_SCHEDULE_EN (0x1<<5)
+#define USB_CMD_INT_AA_DOORBELL (0x1<<6)
+#define USB_CMD_ASP (0x3<<8)
+#define USB_CMD_ASYNC_SCH_PARK_EN (0x1<<11)
+#define USB_CMD_SUTW (0x1<<13)
+#define USB_CMD_ATDTW (0x1<<14)
+#define USB_CMD_ITC (0xFF<<16)
+
+/* bit 15,3,2 are frame list size */
+#define USB_CMD_FRAME_SIZE_1024 (0x0<<15 | 0x0<<2)
+#define USB_CMD_FRAME_SIZE_512 (0x0<<15 | 0x1<<2)
+#define USB_CMD_FRAME_SIZE_256 (0x0<<15 | 0x2<<2)
+#define USB_CMD_FRAME_SIZE_128 (0x0<<15 | 0x3<<2)
+#define USB_CMD_FRAME_SIZE_64 (0x1<<15 | 0x0<<2)
+#define USB_CMD_FRAME_SIZE_32 (0x1<<15 | 0x1<<2)
+#define USB_CMD_FRAME_SIZE_16 (0x1<<15 | 0x2<<2)
+#define USB_CMD_FRAME_SIZE_8 (0x1<<15 | 0x3<<2)
+
+/* bit 9-8 are async schedule park mode count */
+#define USB_CMD_ASP_00 (0x0<<8)
+#define USB_CMD_ASP_01 (0x1<<8)
+#define USB_CMD_ASP_10 (0x2<<8)
+#define USB_CMD_ASP_11 (0x3<<8)
+#define USB_CMD_ASP_BIT_POS (8)
+
+/* bit 23-16 are interrupt threshold control */
+#define USB_CMD_ITC_NO_THRESHOLD (0x00<<16)
+#define USB_CMD_ITC_1_MICRO_FRM (0x01<<16)
+#define USB_CMD_ITC_2_MICRO_FRM (0x02<<16)
+#define USB_CMD_ITC_4_MICRO_FRM (0x04<<16)
+#define USB_CMD_ITC_8_MICRO_FRM (0x08<<16)
+#define USB_CMD_ITC_16_MICRO_FRM (0x10<<16)
+#define USB_CMD_ITC_32_MICRO_FRM (0x20<<16)
+#define USB_CMD_ITC_64_MICRO_FRM (0x40<<16)
+#define USB_CMD_ITC_BIT_POS (16)
+
+/* USB Status Register Bit Masks */
+#define USB_STS_INT (0x1<<0)
+#define USB_STS_ERR (0x1<<1)
+#define USB_STS_PORT_CHANGE (0x1<<2)
+#define USB_STS_FRM_LST_ROLL (0x1<<3)
+#define USB_STS_SYS_ERR (0x1<<4)
+#define USB_STS_IAA (0x1<<5)
+#define USB_STS_RESET_RECEIVED (0x1<<6)
+#define USB_STS_SOF (0x1<<7)
+#define USB_STS_DCSUSPEND (0x1<<8)
+#define USB_STS_HC_HALTED (0x1<<12)
+#define USB_STS_RCL (0x1<<13)
+#define USB_STS_PERIODIC_SCHEDULE (0x1<<14)
+#define USB_STS_ASYNC_SCHEDULE (0x1<<15)
+
+/* USB Interrupt Enable Register Bit Masks */
+#define USB_INTR_INT_EN (0x1<<0)
+#define USB_INTR_ERR_INT_EN (0x1<<1)
+#define USB_INTR_PC_DETECT_EN (0x1<<2)
+#define USB_INTR_FRM_LST_ROLL_EN (0x1<<3)
+#define USB_INTR_SYS_ERR_EN (0x1<<4)
+#define USB_INTR_ASYN_ADV_EN (0x1<<5)
+#define USB_INTR_RESET_EN (0x1<<6)
+#define USB_INTR_SOF_EN (0x1<<7)
+#define USB_INTR_DEVICE_SUSPEND (0x1<<8)
+
+/* Device Address bit masks */
+#define USB_DEVICE_ADDRESS_MASK (0x7F<<25)
+#define USB_DEVICE_ADDRESS_BIT_POS (25)
+/* PORTSC Register Bit Masks,Only one PORT in OTG mode*/
+#define PORTSC_CURRENT_CONNECT_STATUS (0x1<<0)
+#define PORTSC_CONNECT_STATUS_CHANGE (0x1<<1)
+#define PORTSC_PORT_ENABLE (0x1<<2)
+#define PORTSC_PORT_EN_DIS_CHANGE (0x1<<3)
+#define PORTSC_OVER_CURRENT_ACT (0x1<<4)
+#define PORTSC_OVER_CUURENT_CHG (0x1<<5)
+#define PORTSC_PORT_FORCE_RESUME (0x1<<6)
+#define PORTSC_PORT_SUSPEND (0x1<<7)
+#define PORTSC_PORT_RESET (0x1<<8)
+#define PORTSC_LINE_STATUS_BITS (0x3<<10)
+#define PORTSC_PORT_POWER (0x1<<12)
+#define PORTSC_PORT_INDICTOR_CTRL (0x3<<14)
+#define PORTSC_PORT_TEST_CTRL (0xF<<16)
+#define PORTSC_WAKE_ON_CONNECT_EN (0x1<<20)
+#define PORTSC_WAKE_ON_CONNECT_DIS (0x1<<21)
+#define PORTSC_WAKE_ON_OVER_CURRENT (0x1<<22)
+#define PORTSC_PHY_LOW_POWER_SPD (0x1<<23)
+#define PORTSC_PORT_FORCE_FULL_SPEED (0x1<<24)
+#define PORTSC_PORT_SPEED_MASK (0x3<<26)
+#define PORTSC_TRANSCEIVER_WIDTH (0x1<<28)
+#define PORTSC_PHY_TYPE_SEL (0x3<<30)
+/* bit 11-10 are line status */
+#define PORTSC_LINE_STATUS_SE0 (0x0<<10)
+#define PORTSC_LINE_STATUS_JSTATE (0x1<<10)
+#define PORTSC_LINE_STATUS_KSTATE (0x2<<10)
+#define PORTSC_LINE_STATUS_UNDEF (0x3<<10)
+#define PORTSC_LINE_STATUS_BIT_POS (10)
+
+/* bit 15-14 are port indicator control */
+#define PORTSC_PIC_OFF (0x0<<14)
+#define PORTSC_PIC_AMBER (0x1<<14)
+#define PORTSC_PIC_GREEN (0x2<<14)
+#define PORTSC_PIC_UNDEF (0x3<<14)
+#define PORTSC_PIC_BIT_POS (14)
+
+/* bit 19-16 are port test control */
+#define PORTSC_PTC_DISABLE (0x0<<16)
+#define PORTSC_PTC_JSTATE (0x1<<16)
+#define PORTSC_PTC_KSTATE (0x2<<16)
+#define PORTSC_PTC_SEQNAK (0x3<<16)
+#define PORTSC_PTC_PACKET (0x4<<16)
+#define PORTSC_PTC_FORCE_EN (0x5<<16)
+#define PORTSC_PTC_BIT_POS (16)
+
+/* bit 27-26 are port speed */
+#define PORTSC_PORT_SPEED_FULL (0x0<<26)
+#define PORTSC_PORT_SPEED_LOW (0x1<<26)
+#define PORTSC_PORT_SPEED_HIGH (0x2<<26)
+#define PORTSC_PORT_SPEED_UNDEF (0x3<<26)
+#define PORTSC_SPEED_BIT_POS (26)
+
+/* bit 28 is parallel transceiver width for UTMI interface */
+#define PORTSC_PTW (0x1<<28)
+#define PORTSC_PTW_8BIT (0x0<<28)
+#define PORTSC_PTW_16BIT (0x1<<28)
+
+/* bit 31-30 are port transceiver select */
+#define PORTSC_PTS_UTMI (0x0<<30)
+#define PORTSC_PTS_ULPI (0x2<<30)
+#define PORTSC_PTS_FSLS_SERIAL (0x3<<30)
+#define PORTSC_PTS_BIT_POS (30)
+
+#define PORTSC_W1C_BITS \
+ (PORTSC_CONNECT_STATUS_CHANGE | \
+ PORTSC_PORT_EN_DIS_CHANGE | \
+ PORTSC_OVER_CUURENT_CHG)
+
+/* OTG Status Control Register Bit Masks */
+#define OTGSC_CTRL_VBUS_DISCHARGE (0x1<<0)
+#define OTGSC_CTRL_VBUS_CHARGE (0x1<<1)
+#define OTGSC_CTRL_OTG_TERMINATION (0x1<<3)
+#define OTGSC_CTRL_DATA_PULSING (0x1<<4)
+#define OTGSC_CTRL_ID_PULL_EN (0x1<<5)
+#define OTGSC_HA_DATA_PULSE (0x1<<6)
+#define OTGSC_HA_BA (0x1<<7)
+#define OTGSC_STS_USB_ID (0x1<<8)
+#define OTGSC_STS_A_VBUS_VALID (0x1<<9)
+#define OTGSC_STS_A_SESSION_VALID (0x1<<10)
+#define OTGSC_STS_B_SESSION_VALID (0x1<<11)
+#define OTGSC_STS_B_SESSION_END (0x1<<12)
+#define OTGSC_STS_1MS_TOGGLE (0x1<<13)
+#define OTGSC_STS_DATA_PULSING (0x1<<14)
+#define OTGSC_INTSTS_USB_ID (0x1<<16)
+#define OTGSC_INTSTS_A_VBUS_VALID (0x1<<17)
+#define OTGSC_INTSTS_A_SESSION_VALID (0x1<<18)
+#define OTGSC_INTSTS_B_SESSION_VALID (0x1<<19)
+#define OTGSC_INTSTS_B_SESSION_END (0x1<<20)
+#define OTGSC_INTSTS_1MS (0x1<<21)
+#define OTGSC_INTSTS_DATA_PULSING (0x1<<22)
+#define OTGSC_INTR_USB_ID_EN (0x1<<24)
+#define OTGSC_INTR_A_VBUS_VALID_EN (0x1<<25)
+#define OTGSC_INTR_A_SESSION_VALID_EN (0x1<<26)
+#define OTGSC_INTR_B_SESSION_VALID_EN (0x1<<27)
+#define OTGSC_INTR_B_SESSION_END_EN (0x1<<28)
+#define OTGSC_INTR_1MS_TIMER_EN (0x1<<29)
+#define OTGSC_INTR_DATA_PULSING_EN (0x1<<30)
+#define OTGSC_INTSTS_MASK (0x00ff0000)
+
+/* USB MODE Register Bit Masks */
+#define USB_MODE_CTRL_MODE_IDLE (0x0<<0)
+#define USB_MODE_CTRL_MODE_DEVICE (0x2<<0)
+#define USB_MODE_CTRL_MODE_HOST (0x3<<0)
+#define USB_MODE_CTRL_MODE_RSV (0x1<<0)
+#define USB_MODE_SETUP_LOCK_OFF (0x1<<3)
+#define USB_MODE_STREAM_DISABLE (0x1<<4)
+#define USB_MODE_ES (0x1<<2) /* Endian Select */
+
+/* control Register Bit Masks */
+#define USB_CTRL_IOENB (0x1<<2)
+#define USB_CTRL_ULPI_INT0EN (0x1<<0)
+
+/* BCSR5 */
+#define BCSR5_INT_USB (0x02)
+
+/* USB module clk cfg */
+#define SCCR_OFFS (0xA08)
+#define SCCR_USB_CLK_DISABLE (0x00000000) /* USB clk disable */
+#define SCCR_USB_MPHCM_11 (0x00c00000)
+#define SCCR_USB_MPHCM_01 (0x00400000)
+#define SCCR_USB_MPHCM_10 (0x00800000)
+#define SCCR_USB_DRCM_11 (0x00300000)
+#define SCCR_USB_DRCM_01 (0x00100000)
+#define SCCR_USB_DRCM_10 (0x00200000)
+
+#define SICRL_OFFS (0x114)
+#define SICRL_USB0 (0x40000000)
+#define SICRL_USB1 (0x20000000)
+
+#define SICRH_OFFS (0x118)
+#define SICRH_USB_UTMI (0x00020000)
+
+/* OTG interrupt enable bit masks */
+#define OTGSC_INTERRUPT_ENABLE_BITS_MASK \
+ (OTGSC_INTR_USB_ID_EN | \
+ OTGSC_INTR_1MS_TIMER_EN | \
+ OTGSC_INTR_A_VBUS_VALID_EN | \
+ OTGSC_INTR_A_SESSION_VALID_EN | \
+ OTGSC_INTR_B_SESSION_VALID_EN | \
+ OTGSC_INTR_B_SESSION_END_EN | \
+ OTGSC_INTR_DATA_PULSING_EN)
+
+/* OTG interrupt status bit masks */
+#define OTGSC_INTERRUPT_STATUS_BITS_MASK \
+ (OTGSC_INTSTS_USB_ID | \
+ OTGSC_INTR_1MS_TIMER_EN | \
+ OTGSC_INTSTS_A_VBUS_VALID | \
+ OTGSC_INTSTS_A_SESSION_VALID | \
+ OTGSC_INTSTS_B_SESSION_VALID | \
+ OTGSC_INTSTS_B_SESSION_END | \
+ OTGSC_INTSTS_DATA_PULSING)
+
+/*
+ * A-DEVICE timing constants
+ */
+
+/* Wait for VBUS Rise */
+#define TA_WAIT_VRISE (100) /* a_wait_vrise 100 ms, section: 6.6.5.1 */
+
+/* Wait for B-Connect */
+#define TA_WAIT_BCON (10000) /* a_wait_bcon > 1 sec, section: 6.6.5.2
+ * This is only used to get out of
+ * OTG_STATE_A_WAIT_BCON state if there was
+ * no connection for these many milliseconds
+ */
+
+/* A-Idle to B-Disconnect */
+/* It is necessary for this timer to be more than 750 ms because of a bug in OPT
+ * test 5.4 in which B OPT disconnects after 750 ms instead of 75ms as stated
+ * in the test description
+ */
+#define TA_AIDL_BDIS (5000) /* a_suspend minimum 200 ms, section: 6.6.5.3 */
+
+/* B-Idle to A-Disconnect */
+#define TA_BIDL_ADIS (12) /* 3 to 200 ms */
+
+/* B-device timing constants */
+
+
+/* Data-Line Pulse Time*/
+#define TB_DATA_PLS (10) /* b_srp_init,continue 5~10ms, section:5.3.3 */
+#define TB_DATA_PLS_MIN (5) /* minimum 5 ms */
+#define TB_DATA_PLS_MAX (10) /* maximum 10 ms */
+
+/* SRP Initiate Time */
+#define TB_SRP_INIT (100) /* b_srp_init,maximum 100 ms, section:5.3.8 */
+
+/* SRP Fail Time */
+#define TB_SRP_FAIL (7000) /* b_srp_init,Fail time 5~30s, section:6.8.2.2*/
+
+/* SRP result wait time */
+#define TB_SRP_WAIT (60)
+
+/* VBus time */
+#define TB_VBUS_PLS (30) /* time to keep vbus pulsing asserted */
+
+/* Discharge time */
+/* This time should be less than 10ms. It varies from system to system. */
+#define TB_VBUS_DSCHRG (8)
+
+/* A-SE0 to B-Reset */
+#define TB_ASE0_BRST (20) /* b_wait_acon, mini 3.125 ms,section:6.8.2.4 */
+
+/* A bus suspend timer before we can switch to b_wait_aconn */
+#define TB_A_SUSPEND (7)
+#define TB_BUS_RESUME (12)
+
+/* SE0 Time Before SRP */
+#define TB_SE0_SRP (2) /* b_idle,minimum 2 ms, section:5.3.2 */
+
+#define SET_OTG_STATE(otg_ptr, newstate) ((otg_ptr)->state = newstate)
+
+struct usb_dr_mmap {
+ /* Capability register */
+ u8 res1[256];
+ u16 caplength; /* Capability Register Length */
+ u16 hciversion; /* Host Controller Interface Version */
+ u32 hcsparams; /* Host Controller Structual Parameters */
+ u32 hccparams; /* Host Controller Capability Parameters */
+ u8 res2[20];
+ u32 dciversion; /* Device Controller Interface Version */
+ u32 dccparams; /* Device Controller Capability Parameters */
+ u8 res3[24];
+ /* Operation register */
+ u32 usbcmd; /* USB Command Register */
+ u32 usbsts; /* USB Status Register */
+ u32 usbintr; /* USB Interrupt Enable Register */
+ u32 frindex; /* Frame Index Register */
+ u8 res4[4];
+ u32 deviceaddr; /* Device Address */
+ u32 endpointlistaddr; /* Endpoint List Address Register */
+ u8 res5[4];
+ u32 burstsize; /* Master Interface Data Burst Size Register */
+ u32 txttfilltuning; /* Transmit FIFO Tuning Controls Register */
+ u8 res6[8];
+ u32 ulpiview; /* ULPI register access */
+ u8 res7[12];
+ u32 configflag; /* Configure Flag Register */
+ u32 portsc; /* Port 1 Status and Control Register */
+ u8 res8[28];
+ u32 otgsc; /* On-The-Go Status and Control */
+ u32 usbmode; /* USB Mode Register */
+ u32 endptsetupstat; /* Endpoint Setup Status Register */
+ u32 endpointprime; /* Endpoint Initialization Register */
+ u32 endptflush; /* Endpoint Flush Register */
+ u32 endptstatus; /* Endpoint Status Register */
+ u32 endptcomplete; /* Endpoint Complete Register */
+ u32 endptctrl[6]; /* Endpoint Control Registers */
+ u8 res9[552];
+ u32 snoop1;
+ u32 snoop2;
+ u32 age_cnt_thresh; /* Age Count Threshold Register */
+ u32 pri_ctrl; /* Priority Control Register */
+ u32 si_ctrl; /* System Interface Control Register */
+ u8 res10[236];
+ u32 control; /* General Purpose Control Register */
+};
+
+struct fsl_otg_timer {
+ unsigned long expires; /* Number of count increase to timeout */
+ unsigned long count; /* Tick counter */
+ void (*function)(unsigned long); /* Timeout function */
+ unsigned long data; /* Data passed to function */
+ struct list_head list;
+};
+
+inline struct fsl_otg_timer *otg_timer_initializer
+(void (*function)(unsigned long), unsigned long expires, unsigned long data)
+{
+ struct fsl_otg_timer *timer;
+
+ timer = kmalloc(sizeof(struct fsl_otg_timer), GFP_KERNEL);
+ if (!timer)
+ return NULL;
+ timer->function = function;
+ timer->expires = expires;
+ timer->data = data;
+ return timer;
+}
+
+struct fsl_otg {
+ struct otg_transceiver otg;
+ struct otg_fsm fsm;
+ struct usb_dr_mmap *dr_mem_map;
+ struct delayed_work otg_event;
+
+ /* used for usb host */
+ struct work_struct work_wq;
+ u8 host_working;
+
+ int irq;
+};
+
+struct fsl_otg_config {
+ u8 otg_port;
+};
+
+/* For SRP and HNP handle */
+#define FSL_OTG_MAJOR 240
+#define FSL_OTG_NAME "fsl-usb2-otg"
+/* Command to OTG driver ioctl */
+#define OTG_IOCTL_MAGIC FSL_OTG_MAJOR
+/* if otg work as host, it should return 1, otherwise return 0 */
+#define GET_OTG_STATUS _IOR(OTG_IOCTL_MAGIC, 1, int)
+#define SET_A_SUSPEND_REQ _IOW(OTG_IOCTL_MAGIC, 2, int)
+#define SET_A_BUS_DROP _IOW(OTG_IOCTL_MAGIC, 3, int)
+#define SET_A_BUS_REQ _IOW(OTG_IOCTL_MAGIC, 4, int)
+#define SET_B_BUS_REQ _IOW(OTG_IOCTL_MAGIC, 5, int)
+#define GET_A_SUSPEND_REQ _IOR(OTG_IOCTL_MAGIC, 6, int)
+#define GET_A_BUS_DROP _IOR(OTG_IOCTL_MAGIC, 7, int)
+#define GET_A_BUS_REQ _IOR(OTG_IOCTL_MAGIC, 8, int)
+#define GET_B_BUS_REQ _IOR(OTG_IOCTL_MAGIC, 9, int)
+
+void fsl_otg_add_timer(void *timer);
+void fsl_otg_del_timer(void *timer);
+void fsl_otg_pulse_vbus(void);
diff --git a/drivers/usb/otg/gpio_vbus.c b/drivers/usb/otg/gpio_vbus.c
index 221c444..52733d9 100644
--- a/drivers/usb/otg/gpio_vbus.c
+++ b/drivers/usb/otg/gpio_vbus.c
@@ -279,6 +279,13 @@
}
INIT_WORK(&gpio_vbus->work, gpio_vbus_work);
+ gpio_vbus->vbus_draw = regulator_get(&pdev->dev, "vbus_draw");
+ if (IS_ERR(gpio_vbus->vbus_draw)) {
+ dev_dbg(&pdev->dev, "can't get vbus_draw regulator, err: %ld\n",
+ PTR_ERR(gpio_vbus->vbus_draw));
+ gpio_vbus->vbus_draw = NULL;
+ }
+
/* only active when a gadget is registered */
err = otg_set_transceiver(&gpio_vbus->otg);
if (err) {
@@ -287,13 +294,6 @@
goto err_otg;
}
- gpio_vbus->vbus_draw = regulator_get(&pdev->dev, "vbus_draw");
- if (IS_ERR(gpio_vbus->vbus_draw)) {
- dev_dbg(&pdev->dev, "can't get vbus_draw regulator, err: %ld\n",
- PTR_ERR(gpio_vbus->vbus_draw));
- gpio_vbus->vbus_draw = NULL;
- }
-
return 0;
err_otg:
free_irq(irq, &pdev->dev);
diff --git a/drivers/usb/otg/isp1301_omap.c b/drivers/usb/otg/isp1301_omap.c
index e25700f..8c28225 100644
--- a/drivers/usb/otg/isp1301_omap.c
+++ b/drivers/usb/otg/isp1301_omap.c
@@ -234,29 +234,9 @@
/*-------------------------------------------------------------------------*/
-static const char *state_string(enum usb_otg_state state)
-{
- switch (state) {
- case OTG_STATE_A_IDLE: return "a_idle";
- case OTG_STATE_A_WAIT_VRISE: return "a_wait_vrise";
- case OTG_STATE_A_WAIT_BCON: return "a_wait_bcon";
- case OTG_STATE_A_HOST: return "a_host";
- case OTG_STATE_A_SUSPEND: return "a_suspend";
- case OTG_STATE_A_PERIPHERAL: return "a_peripheral";
- case OTG_STATE_A_WAIT_VFALL: return "a_wait_vfall";
- case OTG_STATE_A_VBUS_ERR: return "a_vbus_err";
- case OTG_STATE_B_IDLE: return "b_idle";
- case OTG_STATE_B_SRP_INIT: return "b_srp_init";
- case OTG_STATE_B_PERIPHERAL: return "b_peripheral";
- case OTG_STATE_B_WAIT_ACON: return "b_wait_acon";
- case OTG_STATE_B_HOST: return "b_host";
- default: return "UNDEFINED";
- }
-}
-
static inline const char *state_name(struct isp1301 *isp)
{
- return state_string(isp->otg.state);
+ return otg_state_string(isp->otg.state);
}
/*-------------------------------------------------------------------------*/
@@ -501,7 +481,7 @@
if (isp->otg.state == state && !extra)
return;
pr_debug("otg: %s FSM %s/%02x, %s, %06x\n", tag,
- state_string(state), fsm, state_name(isp),
+ otg_state_string(state), fsm, state_name(isp),
omap_readl(OTG_CTRL));
}
@@ -1095,7 +1075,7 @@
if (state != isp->otg.state)
pr_debug(" isp, %s -> %s\n",
- state_string(state), state_name(isp));
+ otg_state_string(state), state_name(isp));
#ifdef CONFIG_USB_OTG
/* update the OTG controller state to match the isp1301; may
diff --git a/drivers/usb/otg/langwell_otg.c b/drivers/usb/otg/langwell_otg.c
index e973ff1..f08f784 100644
--- a/drivers/usb/otg/langwell_otg.c
+++ b/drivers/usb/otg/langwell_otg.c
@@ -82,40 +82,6 @@
.resume = langwell_otg_resume,
};
-static const char *state_string(enum usb_otg_state state)
-{
- switch (state) {
- case OTG_STATE_A_IDLE:
- return "a_idle";
- case OTG_STATE_A_WAIT_VRISE:
- return "a_wait_vrise";
- case OTG_STATE_A_WAIT_BCON:
- return "a_wait_bcon";
- case OTG_STATE_A_HOST:
- return "a_host";
- case OTG_STATE_A_SUSPEND:
- return "a_suspend";
- case OTG_STATE_A_PERIPHERAL:
- return "a_peripheral";
- case OTG_STATE_A_WAIT_VFALL:
- return "a_wait_vfall";
- case OTG_STATE_A_VBUS_ERR:
- return "a_vbus_err";
- case OTG_STATE_B_IDLE:
- return "b_idle";
- case OTG_STATE_B_SRP_INIT:
- return "b_srp_init";
- case OTG_STATE_B_PERIPHERAL:
- return "b_peripheral";
- case OTG_STATE_B_WAIT_ACON:
- return "b_wait_acon";
- case OTG_STATE_B_HOST:
- return "b_host";
- default:
- return "UNDEFINED";
- }
-}
-
/* HSM timers */
static inline struct langwell_otg_timer *otg_timer_initializer
(void (*function)(unsigned long), unsigned long expires, unsigned long data)
@@ -968,7 +934,7 @@
pdev = to_pci_dev(lnw->dev);
dev_dbg(lnw->dev, "%s: old state = %s\n", __func__,
- state_string(iotg->otg.state));
+ otg_state_string(iotg->otg.state));
switch (iotg->otg.state) {
case OTG_STATE_UNDEFINED:
@@ -1703,7 +1669,7 @@
}
dev_dbg(lnw->dev, "%s: new state = %s\n", __func__,
- state_string(iotg->otg.state));
+ otg_state_string(iotg->otg.state));
}
static ssize_t
@@ -1789,7 +1755,7 @@
"b_bus_req = \t%d\n"
"b_bus_suspend_tmout = \t%d\n"
"b_bus_suspend_vld = \t%d\n",
- state_string(iotg->otg.state),
+ otg_state_string(iotg->otg.state),
iotg->hsm.a_bus_resume,
iotg->hsm.a_bus_suspend,
iotg->hsm.a_conn,
diff --git a/drivers/usb/otg/msm_otg.c b/drivers/usb/otg/msm_otg.c
index 2965986..b276f8f 100644
--- a/drivers/usb/otg/msm_otg.c
+++ b/drivers/usb/otg/msm_otg.c
@@ -1,4 +1,4 @@
-/* Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved.
+/* Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
@@ -38,6 +38,7 @@
#include <linux/usb/hcd.h>
#include <linux/usb/msm_hsusb.h>
#include <linux/usb/msm_hsusb_hw.h>
+#include <linux/regulator/consumer.h>
#include <mach/clk.h>
@@ -45,6 +46,195 @@
#define DRIVER_NAME "msm_otg"
#define ULPI_IO_TIMEOUT_USEC (10 * 1000)
+
+#define USB_PHY_3P3_VOL_MIN 3050000 /* uV */
+#define USB_PHY_3P3_VOL_MAX 3300000 /* uV */
+#define USB_PHY_3P3_HPM_LOAD 50000 /* uA */
+#define USB_PHY_3P3_LPM_LOAD 4000 /* uA */
+
+#define USB_PHY_1P8_VOL_MIN 1800000 /* uV */
+#define USB_PHY_1P8_VOL_MAX 1800000 /* uV */
+#define USB_PHY_1P8_HPM_LOAD 50000 /* uA */
+#define USB_PHY_1P8_LPM_LOAD 4000 /* uA */
+
+#define USB_PHY_VDD_DIG_VOL_MIN 1000000 /* uV */
+#define USB_PHY_VDD_DIG_VOL_MAX 1320000 /* uV */
+
+static struct regulator *hsusb_3p3;
+static struct regulator *hsusb_1p8;
+static struct regulator *hsusb_vddcx;
+
+static int msm_hsusb_init_vddcx(struct msm_otg *motg, int init)
+{
+ int ret = 0;
+
+ if (init) {
+ hsusb_vddcx = regulator_get(motg->otg.dev, "HSUSB_VDDCX");
+ if (IS_ERR(hsusb_vddcx)) {
+ dev_err(motg->otg.dev, "unable to get hsusb vddcx\n");
+ return PTR_ERR(hsusb_vddcx);
+ }
+
+ ret = regulator_set_voltage(hsusb_vddcx,
+ USB_PHY_VDD_DIG_VOL_MIN,
+ USB_PHY_VDD_DIG_VOL_MAX);
+ if (ret) {
+ dev_err(motg->otg.dev, "unable to set the voltage "
+ "for hsusb vddcx\n");
+ regulator_put(hsusb_vddcx);
+ return ret;
+ }
+
+ ret = regulator_enable(hsusb_vddcx);
+ if (ret) {
+ dev_err(motg->otg.dev, "unable to enable hsusb vddcx\n");
+ regulator_put(hsusb_vddcx);
+ }
+ } else {
+ ret = regulator_set_voltage(hsusb_vddcx, 0,
+ USB_PHY_VDD_DIG_VOL_MAX);
+ if (ret)
+ dev_err(motg->otg.dev, "unable to set the voltage "
+ "for hsusb vddcx\n");
+ ret = regulator_disable(hsusb_vddcx);
+ if (ret)
+ dev_err(motg->otg.dev, "unable to disable hsusb vddcx\n");
+
+ regulator_put(hsusb_vddcx);
+ }
+
+ return ret;
+}
+
+static int msm_hsusb_ldo_init(struct msm_otg *motg, int init)
+{
+ int rc = 0;
+
+ if (init) {
+ hsusb_3p3 = regulator_get(motg->otg.dev, "HSUSB_3p3");
+ if (IS_ERR(hsusb_3p3)) {
+ dev_err(motg->otg.dev, "unable to get hsusb 3p3\n");
+ return PTR_ERR(hsusb_3p3);
+ }
+
+ rc = regulator_set_voltage(hsusb_3p3, USB_PHY_3P3_VOL_MIN,
+ USB_PHY_3P3_VOL_MAX);
+ if (rc) {
+ dev_err(motg->otg.dev, "unable to set voltage level "
+ "for hsusb 3p3\n");
+ goto put_3p3;
+ }
+ rc = regulator_enable(hsusb_3p3);
+ if (rc) {
+ dev_err(motg->otg.dev, "unable to enable the hsusb 3p3\n");
+ goto put_3p3;
+ }
+ hsusb_1p8 = regulator_get(motg->otg.dev, "HSUSB_1p8");
+ if (IS_ERR(hsusb_1p8)) {
+ dev_err(motg->otg.dev, "unable to get hsusb 1p8\n");
+ rc = PTR_ERR(hsusb_1p8);
+ goto disable_3p3;
+ }
+ rc = regulator_set_voltage(hsusb_1p8, USB_PHY_1P8_VOL_MIN,
+ USB_PHY_1P8_VOL_MAX);
+ if (rc) {
+ dev_err(motg->otg.dev, "unable to set voltage level "
+ "for hsusb 1p8\n");
+ goto put_1p8;
+ }
+ rc = regulator_enable(hsusb_1p8);
+ if (rc) {
+ dev_err(motg->otg.dev, "unable to enable the hsusb 1p8\n");
+ goto put_1p8;
+ }
+
+ return 0;
+ }
+
+ regulator_disable(hsusb_1p8);
+put_1p8:
+ regulator_put(hsusb_1p8);
+disable_3p3:
+ regulator_disable(hsusb_3p3);
+put_3p3:
+ regulator_put(hsusb_3p3);
+ return rc;
+}
+
+#ifdef CONFIG_PM_SLEEP
+#define USB_PHY_SUSP_DIG_VOL 500000
+static int msm_hsusb_config_vddcx(int high)
+{
+ int max_vol = USB_PHY_VDD_DIG_VOL_MAX;
+ int min_vol;
+ int ret;
+
+ if (high)
+ min_vol = USB_PHY_VDD_DIG_VOL_MIN;
+ else
+ min_vol = USB_PHY_SUSP_DIG_VOL;
+
+ ret = regulator_set_voltage(hsusb_vddcx, min_vol, max_vol);
+ if (ret) {
+ pr_err("%s: unable to set the voltage for regulator "
+ "HSUSB_VDDCX\n", __func__);
+ return ret;
+ }
+
+ pr_debug("%s: min_vol:%d max_vol:%d\n", __func__, min_vol, max_vol);
+
+ return ret;
+}
+#endif
+
+static int msm_hsusb_ldo_set_mode(int on)
+{
+ int ret = 0;
+
+ if (!hsusb_1p8 || IS_ERR(hsusb_1p8)) {
+ pr_err("%s: HSUSB_1p8 is not initialized\n", __func__);
+ return -ENODEV;
+ }
+
+ if (!hsusb_3p3 || IS_ERR(hsusb_3p3)) {
+ pr_err("%s: HSUSB_3p3 is not initialized\n", __func__);
+ return -ENODEV;
+ }
+
+ if (on) {
+ ret = regulator_set_optimum_mode(hsusb_1p8,
+ USB_PHY_1P8_HPM_LOAD);
+ if (ret < 0) {
+ pr_err("%s: Unable to set HPM of the regulator "
+ "HSUSB_1p8\n", __func__);
+ return ret;
+ }
+ ret = regulator_set_optimum_mode(hsusb_3p3,
+ USB_PHY_3P3_HPM_LOAD);
+ if (ret < 0) {
+ pr_err("%s: Unable to set HPM of the regulator "
+ "HSUSB_3p3\n", __func__);
+ regulator_set_optimum_mode(hsusb_1p8,
+ USB_PHY_1P8_LPM_LOAD);
+ return ret;
+ }
+ } else {
+ ret = regulator_set_optimum_mode(hsusb_1p8,
+ USB_PHY_1P8_LPM_LOAD);
+ if (ret < 0)
+ pr_err("%s: Unable to set LPM of the regulator "
+ "HSUSB_1p8\n", __func__);
+ ret = regulator_set_optimum_mode(hsusb_3p3,
+ USB_PHY_3P3_LPM_LOAD);
+ if (ret < 0)
+ pr_err("%s: Unable to set LPM of the regulator "
+ "HSUSB_3p3\n", __func__);
+ }
+
+ pr_debug("reg (%s)\n", on ? "HPM" : "LPM");
+ return ret < 0 ? ret : 0;
+}
+
static int ulpi_read(struct otg_transceiver *otg, u32 reg)
{
struct msm_otg *motg = container_of(otg, struct msm_otg, otg);
@@ -268,27 +458,28 @@
disable_irq(motg->irq);
/*
+ * Chipidea 45-nm PHY suspend sequence:
+ *
* Interrupt Latch Register auto-clear feature is not present
* in all PHY versions. Latch register is clear on read type.
* Clear latch register to avoid spurious wakeup from
* low power mode (LPM).
- */
- ulpi_read(otg, 0x14);
-
- /*
+ *
* PHY comparators are disabled when PHY enters into low power
* mode (LPM). Keep PHY comparators ON in LPM only when we expect
* VBUS/Id notifications from USB PHY. Otherwise turn off USB
* PHY comparators. This save significant amount of power.
- */
- if (pdata->otg_control == OTG_PHY_CONTROL)
- ulpi_write(otg, 0x01, 0x30);
-
- /*
+ *
* PLL is not turned off when PHY enters into low power mode (LPM).
* Disable PLL for maximum power savings.
*/
- ulpi_write(otg, 0x08, 0x09);
+
+ if (motg->pdata->phy_type == CI_45NM_INTEGRATED_PHY) {
+ ulpi_read(otg, 0x14);
+ if (pdata->otg_control == OTG_PHY_CONTROL)
+ ulpi_write(otg, 0x01, 0x30);
+ ulpi_write(otg, 0x08, 0x09);
+ }
/*
* PHY may take some time or even fail to enter into low power
@@ -319,11 +510,24 @@
*/
writel(readl(USB_USBCMD) | ASYNC_INTR_CTRL | ULPI_STP_CTRL, USB_USBCMD);
+ if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
+ motg->pdata->otg_control == OTG_PMIC_CONTROL)
+ writel(readl(USB_PHY_CTRL) | PHY_RETEN, USB_PHY_CTRL);
+
clk_disable(motg->pclk);
clk_disable(motg->clk);
if (motg->core_clk)
clk_disable(motg->core_clk);
+ if (!IS_ERR(motg->pclk_src))
+ clk_disable(motg->pclk_src);
+
+ if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
+ motg->pdata->otg_control == OTG_PMIC_CONTROL) {
+ msm_hsusb_ldo_set_mode(0);
+ msm_hsusb_config_vddcx(0);
+ }
+
if (device_may_wakeup(otg->dev))
enable_irq_wake(motg->irq);
if (bus)
@@ -347,11 +551,21 @@
if (!atomic_read(&motg->in_lpm))
return 0;
+ if (!IS_ERR(motg->pclk_src))
+ clk_enable(motg->pclk_src);
+
clk_enable(motg->pclk);
clk_enable(motg->clk);
if (motg->core_clk)
clk_enable(motg->core_clk);
+ if (motg->pdata->phy_type == SNPS_28NM_INTEGRATED_PHY &&
+ motg->pdata->otg_control == OTG_PMIC_CONTROL) {
+ msm_hsusb_ldo_set_mode(1);
+ msm_hsusb_config_vddcx(1);
+ writel(readl(USB_PHY_CTRL) & ~PHY_RETEN, USB_PHY_CTRL);
+ }
+
temp = readl(USB_USBCMD);
temp &= ~ASYNC_INTR_CTRL;
temp &= ~ULPI_STP_CTRL;
@@ -389,20 +603,47 @@
if (bus)
set_bit(HCD_FLAG_HW_ACCESSIBLE, &(bus_to_hcd(bus))->flags);
+ atomic_set(&motg->in_lpm, 0);
+
if (motg->async_int) {
motg->async_int = 0;
pm_runtime_put(otg->dev);
enable_irq(motg->irq);
}
- atomic_set(&motg->in_lpm, 0);
-
dev_info(otg->dev, "USB exited from low power mode\n");
return 0;
}
#endif
+static void msm_otg_notify_charger(struct msm_otg *motg, unsigned mA)
+{
+ if (motg->cur_power == mA)
+ return;
+
+ /* TODO: Notify PMIC about available current */
+ dev_info(motg->otg.dev, "Avail curr from USB = %u\n", mA);
+ motg->cur_power = mA;
+}
+
+static int msm_otg_set_power(struct otg_transceiver *otg, unsigned mA)
+{
+ struct msm_otg *motg = container_of(otg, struct msm_otg, otg);
+
+ /*
+ * Gadget driver uses set_power method to notify about the
+ * available current based on suspend/configured states.
+ *
+ * IDEV_CHG can be drawn irrespective of suspend/un-configured
+ * states when CDP/ACA is connected.
+ */
+ if (motg->chg_type == USB_SDP_CHARGER)
+ msm_otg_notify_charger(motg, mA);
+
+ return 0;
+}
+
static void msm_otg_start_host(struct otg_transceiver *otg, int on)
{
struct msm_otg *motg = container_of(otg, struct msm_otg, otg);
@@ -557,6 +798,306 @@
return 0;
}
+static bool msm_chg_check_secondary_det(struct msm_otg *motg)
+{
+ struct otg_transceiver *otg = &motg->otg;
+ u32 chg_det;
+ bool ret = false;
+
+ switch (motg->pdata->phy_type) {
+ case CI_45NM_INTEGRATED_PHY:
+ chg_det = ulpi_read(otg, 0x34);
+ ret = chg_det & (1 << 4);
+ break;
+ case SNPS_28NM_INTEGRATED_PHY:
+ chg_det = ulpi_read(otg, 0x87);
+ ret = chg_det & 1;
+ break;
+ default:
+ break;
+ }
+ return ret;
+}
+
+static void msm_chg_enable_secondary_det(struct msm_otg *motg)
+{
+ struct otg_transceiver *otg = &motg->otg;
+ u32 chg_det;
+
+ switch (motg->pdata->phy_type) {
+ case CI_45NM_INTEGRATED_PHY:
+ chg_det = ulpi_read(otg, 0x34);
+ /* Turn off charger block */
+ chg_det |= ~(1 << 1);
+ ulpi_write(otg, chg_det, 0x34);
+ udelay(20);
+ /* control chg block via ULPI */
+ chg_det &= ~(1 << 3);
+ ulpi_write(otg, chg_det, 0x34);
+ /* put it in host mode for enabling D- source */
+ chg_det &= ~(1 << 2);
+ ulpi_write(otg, chg_det, 0x34);
+ /* Turn on chg detect block */
+ chg_det &= ~(1 << 1);
+ ulpi_write(otg, chg_det, 0x34);
+ udelay(20);
+ /* enable chg detection */
+ chg_det &= ~(1 << 0);
+ ulpi_write(otg, chg_det, 0x34);
+ break;
+ case SNPS_28NM_INTEGRATED_PHY:
+ /*
+ * Configure DM as current source, DP as current sink
+ * and enable battery charging comparators.
+ */
+ ulpi_write(otg, 0x8, 0x85);
+ ulpi_write(otg, 0x2, 0x85);
+ ulpi_write(otg, 0x1, 0x85);
+ break;
+ default:
+ break;
+ }
+}
+
+static bool msm_chg_check_primary_det(struct msm_otg *motg)
+{
+ struct otg_transceiver *otg = &motg->otg;
+ u32 chg_det;
+ bool ret = false;
+
+ switch (motg->pdata->phy_type) {
+ case CI_45NM_INTEGRATED_PHY:
+ chg_det = ulpi_read(otg, 0x34);
+ ret = chg_det & (1 << 4);
+ break;
+ case SNPS_28NM_INTEGRATED_PHY:
+ chg_det = ulpi_read(otg, 0x87);
+ ret = chg_det & 1;
+ break;
+ default:
+ break;
+ }
+ return ret;
+}
+
+static void msm_chg_enable_primary_det(struct msm_otg *motg)
+{
+ struct otg_transceiver *otg = &motg->otg;
+ u32 chg_det;
+
+ switch (motg->pdata->phy_type) {
+ case CI_45NM_INTEGRATED_PHY:
+ chg_det = ulpi_read(otg, 0x34);
+ /* enable chg detection */
+ chg_det &= ~(1 << 0);
+ ulpi_write(otg, chg_det, 0x34);
+ break;
+ case SNPS_28NM_INTEGRATED_PHY:
+ /*
+ * Configure DP as current source, DM as current sink
+ * and enable battery charging comparators.
+ */
+ ulpi_write(otg, 0x2, 0x85);
+ ulpi_write(otg, 0x1, 0x85);
+ break;
+ default:
+ break;
+ }
+}
+
+static bool msm_chg_check_dcd(struct msm_otg *motg)
+{
+ struct otg_transceiver *otg = &motg->otg;
+ u32 line_state;
+ bool ret = false;
+
+ switch (motg->pdata->phy_type) {
+ case CI_45NM_INTEGRATED_PHY:
+ line_state = ulpi_read(otg, 0x15);
+ ret = !(line_state & 1);
+ break;
+ case SNPS_28NM_INTEGRATED_PHY:
+ line_state = ulpi_read(otg, 0x87);
+ ret = line_state & 2;
+ break;
+ default:
+ break;
+ }
+ return ret;
+}
+
+static void msm_chg_disable_dcd(struct msm_otg *motg)
+{
+ struct otg_transceiver *otg = &motg->otg;
+ u32 chg_det;
+
+ switch (motg->pdata->phy_type) {
+ case CI_45NM_INTEGRATED_PHY:
+ chg_det = ulpi_read(otg, 0x34);
+ chg_det &= ~(1 << 5);
+ ulpi_write(otg, chg_det, 0x34);
+ break;
+ case SNPS_28NM_INTEGRATED_PHY:
+ ulpi_write(otg, 0x10, 0x86);
+ break;
+ default:
+ break;
+ }
+}
+
+static void msm_chg_enable_dcd(struct msm_otg *motg)
+{
+ struct otg_transceiver *otg = &motg->otg;
+ u32 chg_det;
+
+ switch (motg->pdata->phy_type) {
+ case CI_45NM_INTEGRATED_PHY:
+ chg_det = ulpi_read(otg, 0x34);
+ /* Turn on D+ current source */
+ chg_det |= (1 << 5);
+ ulpi_write(otg, chg_det, 0x34);
+ break;
+ case SNPS_28NM_INTEGRATED_PHY:
+ /* Data contact detection enable */
+ ulpi_write(otg, 0x10, 0x85);
+ break;
+ default:
+ break;
+ }
+}
+
+static void msm_chg_block_on(struct msm_otg *motg)
+{
+ struct otg_transceiver *otg = &motg->otg;
+ u32 func_ctrl, chg_det;
+
+ /* put the controller in non-driving mode */
+ func_ctrl = ulpi_read(otg, ULPI_FUNC_CTRL);
+ func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
+ func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NONDRIVING;
+ ulpi_write(otg, func_ctrl, ULPI_FUNC_CTRL);
+
+ switch (motg->pdata->phy_type) {
+ case CI_45NM_INTEGRATED_PHY:
+ chg_det = ulpi_read(otg, 0x34);
+ /* control chg block via ULPI */
+ chg_det &= ~(1 << 3);
+ ulpi_write(otg, chg_det, 0x34);
+ /* Turn on chg detect block */
+ chg_det &= ~(1 << 1);
+ ulpi_write(otg, chg_det, 0x34);
+ udelay(20);
+ break;
+ case SNPS_28NM_INTEGRATED_PHY:
+ /* Clear charger detecting control bits */
+ ulpi_write(otg, 0x3F, 0x86);
+ /* Clear alt interrupt latch and enable bits */
+ ulpi_write(otg, 0x1F, 0x92);
+ ulpi_write(otg, 0x1F, 0x95);
+ udelay(100);
+ break;
+ default:
+ break;
+ }
+}
+
+static void msm_chg_block_off(struct msm_otg *motg)
+{
+ struct otg_transceiver *otg = &motg->otg;
+ u32 func_ctrl, chg_det;
+
+ switch (motg->pdata->phy_type) {
+ case CI_45NM_INTEGRATED_PHY:
+ chg_det = ulpi_read(otg, 0x34);
+ /* Turn off charger block */
+ chg_det |= ~(1 << 1);
+ ulpi_write(otg, chg_det, 0x34);
+ break;
+ case SNPS_28NM_INTEGRATED_PHY:
+ /* Clear charger detecting control bits */
+ ulpi_write(otg, 0x3F, 0x86);
+ /* Clear alt interrupt latch and enable bits */
+ ulpi_write(otg, 0x1F, 0x92);
+ ulpi_write(otg, 0x1F, 0x95);
+ break;
+ default:
+ break;
+ }
+
+ /* put the controller in normal mode */
+ func_ctrl = ulpi_read(otg, ULPI_FUNC_CTRL);
+ func_ctrl &= ~ULPI_FUNC_CTRL_OPMODE_MASK;
+ func_ctrl |= ULPI_FUNC_CTRL_OPMODE_NORMAL;
+ ulpi_write(otg, func_ctrl, ULPI_FUNC_CTRL);
+}
+
+#define MSM_CHG_DCD_POLL_TIME (100 * HZ/1000) /* 100 msec */
+#define MSM_CHG_DCD_MAX_RETRIES 6 /* Tdcd_tmout = 6 * 100 msec */
+#define MSM_CHG_PRIMARY_DET_TIME (40 * HZ/1000) /* TVDPSRC_ON */
+#define MSM_CHG_SECONDARY_DET_TIME (40 * HZ/1000) /* TVDMSRC_ON */
+static void msm_chg_detect_work(struct work_struct *w)
+{
+ struct msm_otg *motg = container_of(w, struct msm_otg, chg_work.work);
+ struct otg_transceiver *otg = &motg->otg;
+ bool is_dcd, tmout, vout;
+ unsigned long delay;
+
+ dev_dbg(otg->dev, "chg detection work\n");
+ switch (motg->chg_state) {
+ case USB_CHG_STATE_UNDEFINED:
+ pm_runtime_get_sync(otg->dev);
+ msm_chg_block_on(motg);
+ msm_chg_enable_dcd(motg);
+ motg->chg_state = USB_CHG_STATE_WAIT_FOR_DCD;
+ motg->dcd_retries = 0;
+ delay = MSM_CHG_DCD_POLL_TIME;
+ break;
+ case USB_CHG_STATE_WAIT_FOR_DCD:
+ is_dcd = msm_chg_check_dcd(motg);
+ tmout = ++motg->dcd_retries == MSM_CHG_DCD_MAX_RETRIES;
+ if (is_dcd || tmout) {
+ msm_chg_disable_dcd(motg);
+ msm_chg_enable_primary_det(motg);
+ delay = MSM_CHG_PRIMARY_DET_TIME;
+ motg->chg_state = USB_CHG_STATE_DCD_DONE;
+ } else {
+ delay = MSM_CHG_DCD_POLL_TIME;
+ }
+ break;
+ case USB_CHG_STATE_DCD_DONE:
+ vout = msm_chg_check_primary_det(motg);
+ if (vout) {
+ msm_chg_enable_secondary_det(motg);
+ delay = MSM_CHG_SECONDARY_DET_TIME;
+ motg->chg_state = USB_CHG_STATE_PRIMARY_DONE;
+ } else {
+ motg->chg_type = USB_SDP_CHARGER;
+ motg->chg_state = USB_CHG_STATE_DETECTED;
+ delay = 0;
+ }
+ break;
+ case USB_CHG_STATE_PRIMARY_DONE:
+ vout = msm_chg_check_secondary_det(motg);
+ if (vout)
+ motg->chg_type = USB_DCP_CHARGER;
+ else
+ motg->chg_type = USB_CDP_CHARGER;
+ motg->chg_state = USB_CHG_STATE_SECONDARY_DONE;
+ /* fall through */
+ case USB_CHG_STATE_SECONDARY_DONE:
+ motg->chg_state = USB_CHG_STATE_DETECTED;
+ case USB_CHG_STATE_DETECTED:
+ msm_chg_block_off(motg);
+ dev_dbg(otg->dev, "charger = %d\n", motg->chg_type);
+ schedule_work(&motg->sm_work);
+ return;
+ default:
+ return;
+ }
+
+ schedule_delayed_work(&motg->chg_work, delay);
+}
+
/*
* We support OTG, Peripheral only and Host only configurations. In case
* of OTG, mode switch (host-->peripheral/peripheral-->host) can happen
@@ -627,9 +1168,48 @@
writel(readl(USB_OTGSC) & ~OTGSC_BSVIE, USB_OTGSC);
msm_otg_start_host(otg, 1);
otg->state = OTG_STATE_A_HOST;
- } else if (test_bit(B_SESS_VLD, &motg->inputs) && otg->gadget) {
- msm_otg_start_peripheral(otg, 1);
- otg->state = OTG_STATE_B_PERIPHERAL;
+ } else if (test_bit(B_SESS_VLD, &motg->inputs)) {
+ switch (motg->chg_state) {
+ case USB_CHG_STATE_UNDEFINED:
+ msm_chg_detect_work(&motg->chg_work.work);
+ break;
+ case USB_CHG_STATE_DETECTED:
+ switch (motg->chg_type) {
+ case USB_DCP_CHARGER:
+ msm_otg_notify_charger(motg,
+ IDEV_CHG_MAX);
+ break;
+ case USB_CDP_CHARGER:
+ msm_otg_notify_charger(motg,
+ IDEV_CHG_MAX);
+ msm_otg_start_peripheral(otg, 1);
+ otg->state = OTG_STATE_B_PERIPHERAL;
+ break;
+ case USB_SDP_CHARGER:
+ msm_otg_notify_charger(motg, IUNIT);
+ msm_otg_start_peripheral(otg, 1);
+ otg->state = OTG_STATE_B_PERIPHERAL;
+ break;
+ default:
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+ } else {
+ /*
+ * If charger detection work is pending, decrement
+ * the pm usage counter to balance with the one that
+ * is incremented in charger detection work.
+ */
+ if (cancel_delayed_work_sync(&motg->chg_work)) {
+ pm_runtime_put_sync(otg->dev);
+ msm_otg_reset(otg);
+ }
+ msm_otg_notify_charger(motg, 0);
+ motg->chg_state = USB_CHG_STATE_UNDEFINED;
+ motg->chg_type = USB_INVALID_CHARGER;
}
pm_runtime_put_sync(otg->dev);
break;
@@ -637,7 +1217,10 @@
dev_dbg(otg->dev, "OTG_STATE_B_PERIPHERAL state\n");
if (!test_bit(B_SESS_VLD, &motg->inputs) ||
!test_bit(ID, &motg->inputs)) {
+ msm_otg_notify_charger(motg, 0);
msm_otg_start_peripheral(otg, 0);
+ motg->chg_state = USB_CHG_STATE_UNDEFINED;
+ motg->chg_type = USB_INVALID_CHARGER;
otg->state = OTG_STATE_B_IDLE;
msm_otg_reset(otg);
schedule_work(w);
@@ -862,12 +1445,31 @@
ret = PTR_ERR(motg->clk);
goto put_phy_reset_clk;
}
+ clk_set_rate(motg->clk, 60000000);
+
+ /*
+ * If USB Core is running its protocol engine based on CORE CLK,
+ * CORE CLK must be running at >55Mhz for correct HSUSB
+ * operation and USB core cannot tolerate frequency changes on
+ * CORE CLK. For such USB cores, vote for maximum clk frequency
+ * on pclk source
+ */
+ if (motg->pdata->pclk_src_name) {
+ motg->pclk_src = clk_get(&pdev->dev,
+ motg->pdata->pclk_src_name);
+ if (IS_ERR(motg->pclk_src))
+ goto put_clk;
+ clk_set_rate(motg->pclk_src, INT_MAX);
+ clk_enable(motg->pclk_src);
+ } else
+ motg->pclk_src = ERR_PTR(-ENOENT);
+
motg->pclk = clk_get(&pdev->dev, "usb_hs_pclk");
if (IS_ERR(motg->pclk)) {
dev_err(&pdev->dev, "failed to get usb_hs_pclk\n");
ret = PTR_ERR(motg->pclk);
- goto put_clk;
+ goto put_pclk_src;
}
/*
@@ -903,6 +1505,24 @@
clk_enable(motg->clk);
clk_enable(motg->pclk);
+
+ ret = msm_hsusb_init_vddcx(motg, 1);
+ if (ret) {
+ dev_err(&pdev->dev, "hsusb vddcx configuration failed\n");
+ goto free_regs;
+ }
+
+ ret = msm_hsusb_ldo_init(motg, 1);
+ if (ret) {
+ dev_err(&pdev->dev, "hsusb vreg configuration failed\n");
+ goto vddcx_exit;
+ }
+ ret = msm_hsusb_ldo_set_mode(1);
+ if (ret) {
+ dev_err(&pdev->dev, "hsusb vreg enable failed\n");
+ goto ldo_exit;
+ }
+
if (motg->core_clk)
clk_enable(motg->core_clk);
@@ -910,6 +1530,7 @@
writel(0, USB_OTGSC);
INIT_WORK(&motg->sm_work, msm_otg_sm_work);
+ INIT_DELAYED_WORK(&motg->chg_work, msm_chg_detect_work);
ret = request_irq(motg->irq, msm_otg_irq, IRQF_SHARED,
"msm_otg", motg);
if (ret) {
@@ -920,6 +1541,7 @@
otg->init = msm_otg_reset;
otg->set_host = msm_otg_set_host;
otg->set_peripheral = msm_otg_set_peripheral;
+ otg->set_power = msm_otg_set_power;
otg->io_ops = &msm_otg_io_ops;
@@ -949,12 +1571,21 @@
disable_clks:
clk_disable(motg->pclk);
clk_disable(motg->clk);
+ldo_exit:
+ msm_hsusb_ldo_init(motg, 0);
+vddcx_exit:
+ msm_hsusb_init_vddcx(motg, 0);
free_regs:
iounmap(motg->regs);
put_core_clk:
if (motg->core_clk)
clk_put(motg->core_clk);
clk_put(motg->pclk);
+put_pclk_src:
+ if (!IS_ERR(motg->pclk_src)) {
+ clk_disable(motg->pclk_src);
+ clk_put(motg->pclk_src);
+ }
put_clk:
clk_put(motg->clk);
put_phy_reset_clk:
@@ -974,6 +1605,7 @@
return -EBUSY;
msm_otg_debugfs_cleanup();
+ cancel_delayed_work_sync(&motg->chg_work);
cancel_work_sync(&motg->sm_work);
pm_runtime_resume(&pdev->dev);
@@ -1004,6 +1636,11 @@
clk_disable(motg->clk);
if (motg->core_clk)
clk_disable(motg->core_clk);
+ if (!IS_ERR(motg->pclk_src)) {
+ clk_disable(motg->pclk_src);
+ clk_put(motg->pclk_src);
+ }
+ msm_hsusb_ldo_init(motg, 0);
iounmap(motg->regs);
pm_runtime_set_suspended(&pdev->dev);
diff --git a/drivers/usb/otg/otg.c b/drivers/usb/otg/otg.c
index 0a43a7d..fb7adef 100644
--- a/drivers/usb/otg/otg.c
+++ b/drivers/usb/otg/otg.c
@@ -64,3 +64,38 @@
return 0;
}
EXPORT_SYMBOL(otg_set_transceiver);
+
+const char *otg_state_string(enum usb_otg_state state)
+{
+ switch (state) {
+ case OTG_STATE_A_IDLE:
+ return "a_idle";
+ case OTG_STATE_A_WAIT_VRISE:
+ return "a_wait_vrise";
+ case OTG_STATE_A_WAIT_BCON:
+ return "a_wait_bcon";
+ case OTG_STATE_A_HOST:
+ return "a_host";
+ case OTG_STATE_A_SUSPEND:
+ return "a_suspend";
+ case OTG_STATE_A_PERIPHERAL:
+ return "a_peripheral";
+ case OTG_STATE_A_WAIT_VFALL:
+ return "a_wait_vfall";
+ case OTG_STATE_A_VBUS_ERR:
+ return "a_vbus_err";
+ case OTG_STATE_B_IDLE:
+ return "b_idle";
+ case OTG_STATE_B_SRP_INIT:
+ return "b_srp_init";
+ case OTG_STATE_B_PERIPHERAL:
+ return "b_peripheral";
+ case OTG_STATE_B_WAIT_ACON:
+ return "b_wait_acon";
+ case OTG_STATE_B_HOST:
+ return "b_host";
+ default:
+ return "UNDEFINED";
+ }
+}
+EXPORT_SYMBOL(otg_state_string);
diff --git a/drivers/usb/otg/otg_fsm.c b/drivers/usb/otg/otg_fsm.c
new file mode 100644
index 0000000..b0cc422
--- /dev/null
+++ b/drivers/usb/otg/otg_fsm.c
@@ -0,0 +1,349 @@
+/*
+ * OTG Finite State Machine from OTG spec
+ *
+ * Copyright (C) 2007,2008 Freescale Semiconductor, Inc.
+ *
+ * Author: Li Yang <LeoLi@freescale.com>
+ * Jerry Huang <Chang-Ming.Huang@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/spinlock.h>
+#include <linux/delay.h>
+#include <linux/usb.h>
+#include <linux/usb/gadget.h>
+#include <linux/usb/otg.h>
+#include <linux/types.h>
+
+#include "otg_fsm.h"
+
+/* Change USB protocol when there is a protocol change */
+static int otg_set_protocol(struct otg_fsm *fsm, int protocol)
+{
+ int ret = 0;
+
+ if (fsm->protocol != protocol) {
+ VDBG("Changing role fsm->protocol= %d; new protocol= %d\n",
+ fsm->protocol, protocol);
+ /* stop old protocol */
+ if (fsm->protocol == PROTO_HOST)
+ ret = fsm->ops->start_host(fsm, 0);
+ else if (fsm->protocol == PROTO_GADGET)
+ ret = fsm->ops->start_gadget(fsm, 0);
+ if (ret)
+ return ret;
+
+ /* start new protocol */
+ if (protocol == PROTO_HOST)
+ ret = fsm->ops->start_host(fsm, 1);
+ else if (protocol == PROTO_GADGET)
+ ret = fsm->ops->start_gadget(fsm, 1);
+ if (ret)
+ return ret;
+
+ fsm->protocol = protocol;
+ return 0;
+ }
+
+ return 0;
+}
+
+static int state_changed;
+
+/* Called when leaving a state. Do state clean up jobs here */
+void otg_leave_state(struct otg_fsm *fsm, enum usb_otg_state old_state)
+{
+ switch (old_state) {
+ case OTG_STATE_B_IDLE:
+ otg_del_timer(fsm, b_se0_srp_tmr);
+ fsm->b_se0_srp = 0;
+ break;
+ case OTG_STATE_B_SRP_INIT:
+ fsm->b_srp_done = 0;
+ break;
+ case OTG_STATE_B_PERIPHERAL:
+ break;
+ case OTG_STATE_B_WAIT_ACON:
+ otg_del_timer(fsm, b_ase0_brst_tmr);
+ fsm->b_ase0_brst_tmout = 0;
+ break;
+ case OTG_STATE_B_HOST:
+ break;
+ case OTG_STATE_A_IDLE:
+ break;
+ case OTG_STATE_A_WAIT_VRISE:
+ otg_del_timer(fsm, a_wait_vrise_tmr);
+ fsm->a_wait_vrise_tmout = 0;
+ break;
+ case OTG_STATE_A_WAIT_BCON:
+ otg_del_timer(fsm, a_wait_bcon_tmr);
+ fsm->a_wait_bcon_tmout = 0;
+ break;
+ case OTG_STATE_A_HOST:
+ otg_del_timer(fsm, a_wait_enum_tmr);
+ break;
+ case OTG_STATE_A_SUSPEND:
+ otg_del_timer(fsm, a_aidl_bdis_tmr);
+ fsm->a_aidl_bdis_tmout = 0;
+ fsm->a_suspend_req = 0;
+ break;
+ case OTG_STATE_A_PERIPHERAL:
+ break;
+ case OTG_STATE_A_WAIT_VFALL:
+ otg_del_timer(fsm, a_wait_vrise_tmr);
+ break;
+ case OTG_STATE_A_VBUS_ERR:
+ break;
+ default:
+ break;
+ }
+}
+
+/* Called when entering a state */
+int otg_set_state(struct otg_fsm *fsm, enum usb_otg_state new_state)
+{
+ state_changed = 1;
+ if (fsm->transceiver->state == new_state)
+ return 0;
+ VDBG("Set state: %s\n", otg_state_string(new_state));
+ otg_leave_state(fsm, fsm->transceiver->state);
+ switch (new_state) {
+ case OTG_STATE_B_IDLE:
+ otg_drv_vbus(fsm, 0);
+ otg_chrg_vbus(fsm, 0);
+ otg_loc_conn(fsm, 0);
+ otg_loc_sof(fsm, 0);
+ otg_set_protocol(fsm, PROTO_UNDEF);
+ otg_add_timer(fsm, b_se0_srp_tmr);
+ break;
+ case OTG_STATE_B_SRP_INIT:
+ otg_start_pulse(fsm);
+ otg_loc_sof(fsm, 0);
+ otg_set_protocol(fsm, PROTO_UNDEF);
+ otg_add_timer(fsm, b_srp_fail_tmr);
+ break;
+ case OTG_STATE_B_PERIPHERAL:
+ otg_chrg_vbus(fsm, 0);
+ otg_loc_conn(fsm, 1);
+ otg_loc_sof(fsm, 0);
+ otg_set_protocol(fsm, PROTO_GADGET);
+ break;
+ case OTG_STATE_B_WAIT_ACON:
+ otg_chrg_vbus(fsm, 0);
+ otg_loc_conn(fsm, 0);
+ otg_loc_sof(fsm, 0);
+ otg_set_protocol(fsm, PROTO_HOST);
+ otg_add_timer(fsm, b_ase0_brst_tmr);
+ fsm->a_bus_suspend = 0;
+ break;
+ case OTG_STATE_B_HOST:
+ otg_chrg_vbus(fsm, 0);
+ otg_loc_conn(fsm, 0);
+ otg_loc_sof(fsm, 1);
+ otg_set_protocol(fsm, PROTO_HOST);
+ usb_bus_start_enum(fsm->transceiver->host,
+ fsm->transceiver->host->otg_port);
+ break;
+ case OTG_STATE_A_IDLE:
+ otg_drv_vbus(fsm, 0);
+ otg_chrg_vbus(fsm, 0);
+ otg_loc_conn(fsm, 0);
+ otg_loc_sof(fsm, 0);
+ otg_set_protocol(fsm, PROTO_HOST);
+ break;
+ case OTG_STATE_A_WAIT_VRISE:
+ otg_drv_vbus(fsm, 1);
+ otg_loc_conn(fsm, 0);
+ otg_loc_sof(fsm, 0);
+ otg_set_protocol(fsm, PROTO_HOST);
+ otg_add_timer(fsm, a_wait_vrise_tmr);
+ break;
+ case OTG_STATE_A_WAIT_BCON:
+ otg_drv_vbus(fsm, 1);
+ otg_loc_conn(fsm, 0);
+ otg_loc_sof(fsm, 0);
+ otg_set_protocol(fsm, PROTO_HOST);
+ otg_add_timer(fsm, a_wait_bcon_tmr);
+ break;
+ case OTG_STATE_A_HOST:
+ otg_drv_vbus(fsm, 1);
+ otg_loc_conn(fsm, 0);
+ otg_loc_sof(fsm, 1);
+ otg_set_protocol(fsm, PROTO_HOST);
+ /*
+ * When HNP is triggered while a_bus_req = 0, a_host will
+ * suspend too fast to complete a_set_b_hnp_en
+ */
+ if (!fsm->a_bus_req || fsm->a_suspend_req)
+ otg_add_timer(fsm, a_wait_enum_tmr);
+ break;
+ case OTG_STATE_A_SUSPEND:
+ otg_drv_vbus(fsm, 1);
+ otg_loc_conn(fsm, 0);
+ otg_loc_sof(fsm, 0);
+ otg_set_protocol(fsm, PROTO_HOST);
+ otg_add_timer(fsm, a_aidl_bdis_tmr);
+
+ break;
+ case OTG_STATE_A_PERIPHERAL:
+ otg_loc_conn(fsm, 1);
+ otg_loc_sof(fsm, 0);
+ otg_set_protocol(fsm, PROTO_GADGET);
+ otg_drv_vbus(fsm, 1);
+ break;
+ case OTG_STATE_A_WAIT_VFALL:
+ otg_drv_vbus(fsm, 0);
+ otg_loc_conn(fsm, 0);
+ otg_loc_sof(fsm, 0);
+ otg_set_protocol(fsm, PROTO_HOST);
+ break;
+ case OTG_STATE_A_VBUS_ERR:
+ otg_drv_vbus(fsm, 0);
+ otg_loc_conn(fsm, 0);
+ otg_loc_sof(fsm, 0);
+ otg_set_protocol(fsm, PROTO_UNDEF);
+ break;
+ default:
+ break;
+ }
+
+ fsm->transceiver->state = new_state;
+ return 0;
+}
+
+/* State change judgement */
+int otg_statemachine(struct otg_fsm *fsm)
+{
+ enum usb_otg_state state;
+ unsigned long flags;
+
+ spin_lock_irqsave(&fsm->lock, flags);
+
+ state = fsm->transceiver->state;
+ state_changed = 0;
+ /* State machine state change judgement */
+
+ switch (state) {
+ case OTG_STATE_UNDEFINED:
+ VDBG("fsm->id = %d\n", fsm->id);
+ if (fsm->id)
+ otg_set_state(fsm, OTG_STATE_B_IDLE);
+ else
+ otg_set_state(fsm, OTG_STATE_A_IDLE);
+ break;
+ case OTG_STATE_B_IDLE:
+ if (!fsm->id)
+ otg_set_state(fsm, OTG_STATE_A_IDLE);
+ else if (fsm->b_sess_vld && fsm->transceiver->gadget)
+ otg_set_state(fsm, OTG_STATE_B_PERIPHERAL);
+ else if (fsm->b_bus_req && fsm->b_sess_end && fsm->b_se0_srp)
+ otg_set_state(fsm, OTG_STATE_B_SRP_INIT);
+ break;
+ case OTG_STATE_B_SRP_INIT:
+ if (!fsm->id || fsm->b_srp_done)
+ otg_set_state(fsm, OTG_STATE_B_IDLE);
+ break;
+ case OTG_STATE_B_PERIPHERAL:
+ if (!fsm->id || !fsm->b_sess_vld)
+ otg_set_state(fsm, OTG_STATE_B_IDLE);
+ else if (fsm->b_bus_req && fsm->transceiver->
+ gadget->b_hnp_enable && fsm->a_bus_suspend)
+ otg_set_state(fsm, OTG_STATE_B_WAIT_ACON);
+ break;
+ case OTG_STATE_B_WAIT_ACON:
+ if (fsm->a_conn)
+ otg_set_state(fsm, OTG_STATE_B_HOST);
+ else if (!fsm->id || !fsm->b_sess_vld)
+ otg_set_state(fsm, OTG_STATE_B_IDLE);
+ else if (fsm->a_bus_resume || fsm->b_ase0_brst_tmout) {
+ fsm->b_ase0_brst_tmout = 0;
+ otg_set_state(fsm, OTG_STATE_B_PERIPHERAL);
+ }
+ break;
+ case OTG_STATE_B_HOST:
+ if (!fsm->id || !fsm->b_sess_vld)
+ otg_set_state(fsm, OTG_STATE_B_IDLE);
+ else if (!fsm->b_bus_req || !fsm->a_conn)
+ otg_set_state(fsm, OTG_STATE_B_PERIPHERAL);
+ break;
+ case OTG_STATE_A_IDLE:
+ if (fsm->id)
+ otg_set_state(fsm, OTG_STATE_B_IDLE);
+ else if (!fsm->a_bus_drop && (fsm->a_bus_req || fsm->a_srp_det))
+ otg_set_state(fsm, OTG_STATE_A_WAIT_VRISE);
+ break;
+ case OTG_STATE_A_WAIT_VRISE:
+ if (fsm->id || fsm->a_bus_drop || fsm->a_vbus_vld ||
+ fsm->a_wait_vrise_tmout) {
+ otg_set_state(fsm, OTG_STATE_A_WAIT_BCON);
+ }
+ break;
+ case OTG_STATE_A_WAIT_BCON:
+ if (!fsm->a_vbus_vld)
+ otg_set_state(fsm, OTG_STATE_A_VBUS_ERR);
+ else if (fsm->b_conn)
+ otg_set_state(fsm, OTG_STATE_A_HOST);
+ else if (fsm->id | fsm->a_bus_drop | fsm->a_wait_bcon_tmout)
+ otg_set_state(fsm, OTG_STATE_A_WAIT_VFALL);
+ break;
+ case OTG_STATE_A_HOST:
+ if ((!fsm->a_bus_req || fsm->a_suspend_req) &&
+ fsm->transceiver->host->b_hnp_enable)
+ otg_set_state(fsm, OTG_STATE_A_SUSPEND);
+ else if (fsm->id || !fsm->b_conn || fsm->a_bus_drop)
+ otg_set_state(fsm, OTG_STATE_A_WAIT_BCON);
+ else if (!fsm->a_vbus_vld)
+ otg_set_state(fsm, OTG_STATE_A_VBUS_ERR);
+ break;
+ case OTG_STATE_A_SUSPEND:
+ if (!fsm->b_conn && fsm->transceiver->host->b_hnp_enable)
+ otg_set_state(fsm, OTG_STATE_A_PERIPHERAL);
+ else if (!fsm->b_conn && !fsm->transceiver->host->b_hnp_enable)
+ otg_set_state(fsm, OTG_STATE_A_WAIT_BCON);
+ else if (fsm->a_bus_req || fsm->b_bus_resume)
+ otg_set_state(fsm, OTG_STATE_A_HOST);
+ else if (fsm->id || fsm->a_bus_drop || fsm->a_aidl_bdis_tmout)
+ otg_set_state(fsm, OTG_STATE_A_WAIT_VFALL);
+ else if (!fsm->a_vbus_vld)
+ otg_set_state(fsm, OTG_STATE_A_VBUS_ERR);
+ break;
+ case OTG_STATE_A_PERIPHERAL:
+ if (fsm->id || fsm->a_bus_drop)
+ otg_set_state(fsm, OTG_STATE_A_WAIT_VFALL);
+ else if (fsm->b_bus_suspend)
+ otg_set_state(fsm, OTG_STATE_A_WAIT_BCON);
+ else if (!fsm->a_vbus_vld)
+ otg_set_state(fsm, OTG_STATE_A_VBUS_ERR);
+ break;
+ case OTG_STATE_A_WAIT_VFALL:
+ if (fsm->id || fsm->a_bus_req || (!fsm->a_sess_vld &&
+ !fsm->b_conn))
+ otg_set_state(fsm, OTG_STATE_A_IDLE);
+ break;
+ case OTG_STATE_A_VBUS_ERR:
+ if (fsm->id || fsm->a_bus_drop || fsm->a_clr_err)
+ otg_set_state(fsm, OTG_STATE_A_WAIT_VFALL);
+ break;
+ default:
+ break;
+ }
+ spin_unlock_irqrestore(&fsm->lock, flags);
+
+ VDBG("quit statemachine, changed = %d\n", state_changed);
+ return state_changed;
+}
diff --git a/drivers/usb/otg/otg_fsm.h b/drivers/usb/otg/otg_fsm.h
new file mode 100644
index 0000000..0cecf1d
--- /dev/null
+++ b/drivers/usb/otg/otg_fsm.h
@@ -0,0 +1,154 @@
+/* Copyright (C) 2007,2008 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#undef DEBUG
+#undef VERBOSE
+
+#ifdef DEBUG
+#define DBG(fmt, args...) printk(KERN_DEBUG "[%s] " fmt , \
+ __func__, ## args)
+#else
+#define DBG(fmt, args...) do {} while (0)
+#endif
+
+#ifdef VERBOSE
+#define VDBG DBG
+#else
+#define VDBG(stuff...) do {} while (0)
+#endif
+
+#ifdef VERBOSE
+#define MPC_LOC printk("Current Location [%s]:[%d]\n", __FILE__, __LINE__)
+#else
+#define MPC_LOC do {} while (0)
+#endif
+
+#define PROTO_UNDEF (0)
+#define PROTO_HOST (1)
+#define PROTO_GADGET (2)
+
+/* OTG state machine according to the OTG spec */
+struct otg_fsm {
+ /* Input */
+ int a_bus_resume;
+ int a_bus_suspend;
+ int a_conn;
+ int a_sess_vld;
+ int a_srp_det;
+ int a_vbus_vld;
+ int b_bus_resume;
+ int b_bus_suspend;
+ int b_conn;
+ int b_se0_srp;
+ int b_sess_end;
+ int b_sess_vld;
+ int id;
+
+ /* Internal variables */
+ int a_set_b_hnp_en;
+ int b_srp_done;
+ int b_hnp_enable;
+
+ /* Timeout indicator for timers */
+ int a_wait_vrise_tmout;
+ int a_wait_bcon_tmout;
+ int a_aidl_bdis_tmout;
+ int b_ase0_brst_tmout;
+
+ /* Informative variables */
+ int a_bus_drop;
+ int a_bus_req;
+ int a_clr_err;
+ int a_suspend_req;
+ int b_bus_req;
+
+ /* Output */
+ int drv_vbus;
+ int loc_conn;
+ int loc_sof;
+
+ struct otg_fsm_ops *ops;
+ struct otg_transceiver *transceiver;
+
+ /* Current usb protocol used: 0:undefine; 1:host; 2:client */
+ int protocol;
+ spinlock_t lock;
+};
+
+struct otg_fsm_ops {
+ void (*chrg_vbus)(int on);
+ void (*drv_vbus)(int on);
+ void (*loc_conn)(int on);
+ void (*loc_sof)(int on);
+ void (*start_pulse)(void);
+ void (*add_timer)(void *timer);
+ void (*del_timer)(void *timer);
+ int (*start_host)(struct otg_fsm *fsm, int on);
+ int (*start_gadget)(struct otg_fsm *fsm, int on);
+};
+
+
+static inline void otg_chrg_vbus(struct otg_fsm *fsm, int on)
+{
+ fsm->ops->chrg_vbus(on);
+}
+
+static inline void otg_drv_vbus(struct otg_fsm *fsm, int on)
+{
+ if (fsm->drv_vbus != on) {
+ fsm->drv_vbus = on;
+ fsm->ops->drv_vbus(on);
+ }
+}
+
+static inline void otg_loc_conn(struct otg_fsm *fsm, int on)
+{
+ if (fsm->loc_conn != on) {
+ fsm->loc_conn = on;
+ fsm->ops->loc_conn(on);
+ }
+}
+
+static inline void otg_loc_sof(struct otg_fsm *fsm, int on)
+{
+ if (fsm->loc_sof != on) {
+ fsm->loc_sof = on;
+ fsm->ops->loc_sof(on);
+ }
+}
+
+static inline void otg_start_pulse(struct otg_fsm *fsm)
+{
+ fsm->ops->start_pulse();
+}
+
+static inline void otg_add_timer(struct otg_fsm *fsm, void *timer)
+{
+ fsm->ops->add_timer(timer);
+}
+
+static inline void otg_del_timer(struct otg_fsm *fsm, void *timer)
+{
+ fsm->ops->del_timer(timer);
+}
+
+int otg_statemachine(struct otg_fsm *fsm);
+
+/* Defined by device specific driver, for different timer implementation */
+extern struct fsl_otg_timer *a_wait_vrise_tmr, *a_wait_bcon_tmr,
+ *a_aidl_bdis_tmr, *b_ase0_brst_tmr, *b_se0_srp_tmr, *b_srp_fail_tmr,
+ *a_wait_enum_tmr;
diff --git a/drivers/usb/otg/twl4030-usb.c b/drivers/usb/otg/twl4030-usb.c
index e01b073..efeb4d1 100644
--- a/drivers/usb/otg/twl4030-usb.c
+++ b/drivers/usb/otg/twl4030-usb.c
@@ -160,6 +160,7 @@
int irq;
u8 linkstat;
+ bool vbus_supplied;
u8 asleep;
bool irq_enabled;
};
@@ -250,6 +251,8 @@
int status;
int linkstat = USB_EVENT_NONE;
+ twl->vbus_supplied = false;
+
/*
* For ID/VBUS sensing, see manual section 15.4.8 ...
* except when using only battery backup power, two
@@ -265,6 +268,9 @@
if (status < 0)
dev_err(twl->dev, "USB link status err %d\n", status);
else if (status & (BIT(7) | BIT(2))) {
+ if (status & (BIT(7)))
+ twl->vbus_supplied = true;
+
if (status & BIT(2))
linkstat = USB_EVENT_ID;
else
@@ -484,7 +490,7 @@
spin_lock_irqsave(&twl->lock, flags);
ret = sprintf(buf, "%s\n",
- (twl->linkstat == USB_EVENT_VBUS) ? "on" : "off");
+ twl->vbus_supplied ? "on" : "off");
spin_unlock_irqrestore(&twl->lock, flags);
return ret;
@@ -608,6 +614,7 @@
twl->otg.set_peripheral = twl4030_set_peripheral;
twl->otg.set_suspend = twl4030_set_suspend;
twl->usb_mode = pdata->usb_mode;
+ twl->vbus_supplied = false;
twl->asleep = 1;
/* init spinlock for workqueue */
diff --git a/drivers/usb/otg/twl6030-usb.c b/drivers/usb/otg/twl6030-usb.c
index 8a91b4b..3f2e070 100644
--- a/drivers/usb/otg/twl6030-usb.c
+++ b/drivers/usb/otg/twl6030-usb.c
@@ -31,6 +31,7 @@
#include <linux/err.h>
#include <linux/notifier.h>
#include <linux/slab.h>
+#include <linux/delay.h>
/* usb register definitions */
#define USB_VENDOR_ID_LSB 0x00
@@ -101,7 +102,7 @@
bool irq_enabled;
};
-#define xceiv_to_twl(x) container_of((x), struct twl6030_usb, otg);
+#define xceiv_to_twl(x) container_of((x), struct twl6030_usb, otg)
/*-------------------------------------------------------------------------*/
@@ -188,6 +189,19 @@
return 0;
}
+static int twl6030_start_srp(struct otg_transceiver *x)
+{
+ struct twl6030_usb *twl = xceiv_to_twl(x);
+
+ twl6030_writeb(twl, TWL_MODULE_USB, 0x24, USB_VBUS_CTRL_SET);
+ twl6030_writeb(twl, TWL_MODULE_USB, 0x84, USB_VBUS_CTRL_SET);
+
+ mdelay(100);
+ twl6030_writeb(twl, TWL_MODULE_USB, 0xa0, USB_VBUS_CTRL_CLR);
+
+ return 0;
+}
+
static int twl6030_usb_ldo_init(struct twl6030_usb *twl)
{
@@ -403,6 +417,7 @@
twl->otg.init = twl6030_phy_init;
twl->otg.shutdown = twl6030_phy_shutdown;
twl->otg.set_suspend = twl6030_phy_suspend;
+ twl->otg.start_srp = twl6030_start_srp;
/* init spinlock for workqueue */
spin_lock_init(&twl->lock);
diff --git a/drivers/usb/renesas_usbhs/Kconfig b/drivers/usb/renesas_usbhs/Kconfig
new file mode 100644
index 0000000..b2e6491
--- /dev/null
+++ b/drivers/usb/renesas_usbhs/Kconfig
@@ -0,0 +1,16 @@
+#
+# Renesas USB Controller Drivers
+#
+
+config USB_RENESAS_USBHS
+ tristate 'Renesas USBHS controller'
+ depends on SUPERH || ARCH_SHMOBILE
+ default n
+ help
+ Renesas USBHS is a discrete USB host and peripheral controller chip
+ that supports both full and high speed USB 2.0 data transfers.
+ It has nine or more configurable endpoints, and endpoint zero.
+
+ Say "y" to link the driver statically, or "m" to build a
+ dynamically linked module called "renesas_usbhs" and force all
+ gadget drivers to also be dynamically linked.
diff --git a/drivers/usb/renesas_usbhs/Makefile b/drivers/usb/renesas_usbhs/Makefile
new file mode 100644
index 0000000..b8798ad
--- /dev/null
+++ b/drivers/usb/renesas_usbhs/Makefile
@@ -0,0 +1,9 @@
+#
+# for Renesas USB
+#
+
+obj-$(CONFIG_USB_RENESAS_USBHS) += renesas_usbhs.o
+
+renesas_usbhs-y := common.o mod.o pipe.o
+
+renesas_usbhs-$(CONFIG_USB_RENESAS_USBHS_UDC) += mod_gadget.o
diff --git a/drivers/usb/renesas_usbhs/common.c b/drivers/usb/renesas_usbhs/common.c
new file mode 100644
index 0000000..f3664d6
--- /dev/null
+++ b/drivers/usb/renesas_usbhs/common.c
@@ -0,0 +1,437 @@
+/*
+ * Renesas USB driver
+ *
+ * Copyright (C) 2011 Renesas Solutions Corp.
+ * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ */
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/pm_runtime.h>
+#include <linux/slab.h>
+#include <linux/sysfs.h>
+#include "./common.h"
+
+#define USBHSF_RUNTIME_PWCTRL (1 << 0)
+
+/* status */
+#define usbhsc_flags_init(p) do {(p)->flags = 0; } while (0)
+#define usbhsc_flags_set(p, b) ((p)->flags |= (b))
+#define usbhsc_flags_clr(p, b) ((p)->flags &= ~(b))
+#define usbhsc_flags_has(p, b) ((p)->flags & (b))
+
+/*
+ * platform call back
+ *
+ * renesas usb support platform callback function.
+ * Below macro call it.
+ * if platform doesn't have callback, it return 0 (no error)
+ */
+#define usbhs_platform_call(priv, func, args...)\
+ (!(priv) ? -ENODEV : \
+ !((priv)->pfunc->func) ? 0 : \
+ (priv)->pfunc->func(args))
+
+/*
+ * common functions
+ */
+u16 usbhs_read(struct usbhs_priv *priv, u32 reg)
+{
+ return ioread16(priv->base + reg);
+}
+
+void usbhs_write(struct usbhs_priv *priv, u32 reg, u16 data)
+{
+ iowrite16(data, priv->base + reg);
+}
+
+void usbhs_bset(struct usbhs_priv *priv, u32 reg, u16 mask, u16 data)
+{
+ u16 val = usbhs_read(priv, reg);
+
+ val &= ~mask;
+ val |= data & mask;
+
+ usbhs_write(priv, reg, val);
+}
+
+struct usbhs_priv *usbhs_pdev_to_priv(struct platform_device *pdev)
+{
+ return dev_get_drvdata(&pdev->dev);
+}
+
+/*
+ * syscfg functions
+ */
+void usbhs_sys_clock_ctrl(struct usbhs_priv *priv, int enable)
+{
+ usbhs_bset(priv, SYSCFG, SCKE, enable ? SCKE : 0);
+}
+
+void usbhs_sys_hispeed_ctrl(struct usbhs_priv *priv, int enable)
+{
+ usbhs_bset(priv, SYSCFG, HSE, enable ? HSE : 0);
+}
+
+void usbhs_sys_usb_ctrl(struct usbhs_priv *priv, int enable)
+{
+ usbhs_bset(priv, SYSCFG, USBE, enable ? USBE : 0);
+}
+
+void usbhs_sys_host_ctrl(struct usbhs_priv *priv, int enable)
+{
+ u16 mask = DCFM | DRPD | DPRPU;
+ u16 val = DCFM | DRPD;
+
+ /*
+ * if enable
+ *
+ * - select Host mode
+ * - D+ Line/D- Line Pull-down
+ */
+ usbhs_bset(priv, SYSCFG, mask, enable ? val : 0);
+}
+
+void usbhs_sys_function_ctrl(struct usbhs_priv *priv, int enable)
+{
+ u16 mask = DCFM | DRPD | DPRPU;
+ u16 val = DPRPU;
+
+ /*
+ * if enable
+ *
+ * - select Function mode
+ * - D+ Line Pull-up
+ */
+ usbhs_bset(priv, SYSCFG, mask, enable ? val : 0);
+}
+
+/*
+ * frame functions
+ */
+int usbhs_frame_get_num(struct usbhs_priv *priv)
+{
+ return usbhs_read(priv, FRMNUM) & FRNM_MASK;
+}
+
+/*
+ * local functions
+ */
+static void usbhsc_bus_ctrl(struct usbhs_priv *priv, int enable)
+{
+ int wait = usbhs_get_dparam(priv, buswait_bwait);
+ u16 data = 0;
+
+ if (enable) {
+ /* set bus wait if platform have */
+ if (wait)
+ usbhs_bset(priv, BUSWAIT, 0x000F, wait);
+ }
+ usbhs_write(priv, DVSTCTR, data);
+}
+
+/*
+ * platform default param
+ */
+static u32 usbhsc_default_pipe_type[] = {
+ USB_ENDPOINT_XFER_CONTROL,
+ USB_ENDPOINT_XFER_ISOC,
+ USB_ENDPOINT_XFER_ISOC,
+ USB_ENDPOINT_XFER_BULK,
+ USB_ENDPOINT_XFER_BULK,
+ USB_ENDPOINT_XFER_BULK,
+ USB_ENDPOINT_XFER_INT,
+ USB_ENDPOINT_XFER_INT,
+ USB_ENDPOINT_XFER_INT,
+ USB_ENDPOINT_XFER_INT,
+};
+
+/*
+ * power control
+ */
+static void usbhsc_power_ctrl(struct usbhs_priv *priv, int enable)
+{
+ struct device *dev = usbhs_priv_to_dev(priv);
+
+ if (enable) {
+ /* enable PM */
+ pm_runtime_get_sync(dev);
+
+ /* USB on */
+ usbhs_sys_clock_ctrl(priv, enable);
+ usbhsc_bus_ctrl(priv, enable);
+ } else {
+ /* USB off */
+ usbhsc_bus_ctrl(priv, enable);
+ usbhs_sys_clock_ctrl(priv, enable);
+
+ /* disable PM */
+ pm_runtime_put_sync(dev);
+ }
+}
+
+/*
+ * notify hotplug
+ */
+static void usbhsc_notify_hotplug(struct work_struct *work)
+{
+ struct usbhs_priv *priv = container_of(work,
+ struct usbhs_priv,
+ notify_hotplug_work.work);
+ struct platform_device *pdev = usbhs_priv_to_pdev(priv);
+ struct usbhs_mod *mod = usbhs_mod_get_current(priv);
+ int id;
+ int enable;
+ int ret;
+
+ /*
+ * get vbus status from platform
+ */
+ enable = usbhs_platform_call(priv, get_vbus, pdev);
+
+ /*
+ * get id from platform
+ */
+ id = usbhs_platform_call(priv, get_id, pdev);
+
+ if (enable && !mod) {
+ ret = usbhs_mod_change(priv, id);
+ if (ret < 0)
+ return;
+
+ dev_dbg(&pdev->dev, "%s enable\n", __func__);
+
+ /* power on */
+ if (usbhsc_flags_has(priv, USBHSF_RUNTIME_PWCTRL))
+ usbhsc_power_ctrl(priv, enable);
+
+ /* module start */
+ usbhs_mod_call(priv, start, priv);
+
+ } else if (!enable && mod) {
+ dev_dbg(&pdev->dev, "%s disable\n", __func__);
+
+ /* module stop */
+ usbhs_mod_call(priv, stop, priv);
+
+ /* power off */
+ if (usbhsc_flags_has(priv, USBHSF_RUNTIME_PWCTRL))
+ usbhsc_power_ctrl(priv, enable);
+
+ usbhs_mod_change(priv, -1);
+
+ /* reset phy for next connection */
+ usbhs_platform_call(priv, phy_reset, pdev);
+ }
+}
+
+int usbhsc_drvcllbck_notify_hotplug(struct platform_device *pdev)
+{
+ struct usbhs_priv *priv = usbhs_pdev_to_priv(pdev);
+ int delay = usbhs_get_dparam(priv, detection_delay);
+
+ /*
+ * This functions will be called in interrupt.
+ * To make sure safety context,
+ * use workqueue for usbhs_notify_hotplug
+ */
+ schedule_delayed_work(&priv->notify_hotplug_work, delay);
+ return 0;
+}
+
+/*
+ * platform functions
+ */
+static int __devinit usbhs_probe(struct platform_device *pdev)
+{
+ struct renesas_usbhs_platform_info *info = pdev->dev.platform_data;
+ struct renesas_usbhs_driver_callback *dfunc;
+ struct usbhs_priv *priv;
+ struct resource *res;
+ unsigned int irq;
+ int ret;
+
+ /* check platform information */
+ if (!info ||
+ !info->platform_callback.get_id) {
+ dev_err(&pdev->dev, "no platform information\n");
+ return -EINVAL;
+ }
+
+ /* platform data */
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ irq = platform_get_irq(pdev, 0);
+ if (!res || (int)irq <= 0) {
+ dev_err(&pdev->dev, "Not enough Renesas USB platform resources.\n");
+ return -ENODEV;
+ }
+
+ /* usb private data */
+ priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+ if (!priv) {
+ dev_err(&pdev->dev, "Could not allocate priv\n");
+ return -ENOMEM;
+ }
+
+ priv->base = ioremap_nocache(res->start, resource_size(res));
+ if (!priv->base) {
+ dev_err(&pdev->dev, "ioremap error.\n");
+ ret = -ENOMEM;
+ goto probe_end_kfree;
+ }
+
+ /*
+ * care platform info
+ */
+ priv->pfunc = &info->platform_callback;
+ priv->dparam = &info->driver_param;
+
+ /* set driver callback functions for platform */
+ dfunc = &info->driver_callback;
+ dfunc->notify_hotplug = usbhsc_drvcllbck_notify_hotplug;
+
+ /* set default param if platform doesn't have */
+ if (!priv->dparam->pipe_type) {
+ priv->dparam->pipe_type = usbhsc_default_pipe_type;
+ priv->dparam->pipe_size = ARRAY_SIZE(usbhsc_default_pipe_type);
+ }
+
+ /* FIXME */
+ /* runtime power control ? */
+ if (priv->pfunc->get_vbus)
+ usbhsc_flags_set(priv, USBHSF_RUNTIME_PWCTRL);
+
+ /*
+ * priv settings
+ */
+ priv->irq = irq;
+ priv->pdev = pdev;
+ INIT_DELAYED_WORK(&priv->notify_hotplug_work, usbhsc_notify_hotplug);
+ spin_lock_init(usbhs_priv_to_lock(priv));
+
+ /* call pipe and module init */
+ ret = usbhs_pipe_probe(priv);
+ if (ret < 0)
+ goto probe_end_iounmap;
+
+ ret = usbhs_mod_probe(priv);
+ if (ret < 0)
+ goto probe_end_pipe_exit;
+
+ /* dev_set_drvdata should be called after usbhs_mod_init */
+ dev_set_drvdata(&pdev->dev, priv);
+
+ /*
+ * deviece reset here because
+ * USB device might be used in boot loader.
+ */
+ usbhs_sys_clock_ctrl(priv, 0);
+
+ /*
+ * platform call
+ *
+ * USB phy setup might depend on CPU/Board.
+ * If platform has its callback functions,
+ * call it here.
+ */
+ ret = usbhs_platform_call(priv, hardware_init, pdev);
+ if (ret < 0) {
+ dev_err(&pdev->dev, "platform prove failed.\n");
+ goto probe_end_mod_exit;
+ }
+
+ /* reset phy for connection */
+ usbhs_platform_call(priv, phy_reset, pdev);
+
+ /* power control */
+ pm_runtime_enable(&pdev->dev);
+ if (!usbhsc_flags_has(priv, USBHSF_RUNTIME_PWCTRL)) {
+ usbhsc_power_ctrl(priv, 1);
+ usbhs_mod_autonomy_mode(priv);
+ }
+
+ /*
+ * manual call notify_hotplug for cold plug
+ */
+ ret = usbhsc_drvcllbck_notify_hotplug(pdev);
+ if (ret < 0)
+ goto probe_end_call_remove;
+
+ dev_info(&pdev->dev, "probed\n");
+
+ return ret;
+
+probe_end_call_remove:
+ usbhs_platform_call(priv, hardware_exit, pdev);
+probe_end_mod_exit:
+ usbhs_mod_remove(priv);
+probe_end_pipe_exit:
+ usbhs_pipe_remove(priv);
+probe_end_iounmap:
+ iounmap(priv->base);
+probe_end_kfree:
+ kfree(priv);
+
+ dev_info(&pdev->dev, "probe failed\n");
+
+ return ret;
+}
+
+static int __devexit usbhs_remove(struct platform_device *pdev)
+{
+ struct usbhs_priv *priv = usbhs_pdev_to_priv(pdev);
+ struct renesas_usbhs_platform_info *info = pdev->dev.platform_data;
+ struct renesas_usbhs_driver_callback *dfunc = &info->driver_callback;
+
+ dev_dbg(&pdev->dev, "usb remove\n");
+
+ dfunc->notify_hotplug = NULL;
+
+ /* power off */
+ if (!usbhsc_flags_has(priv, USBHSF_RUNTIME_PWCTRL))
+ usbhsc_power_ctrl(priv, 0);
+
+ pm_runtime_disable(&pdev->dev);
+
+ usbhs_platform_call(priv, hardware_exit, pdev);
+ usbhs_mod_remove(priv);
+ usbhs_pipe_remove(priv);
+ iounmap(priv->base);
+ kfree(priv);
+
+ return 0;
+}
+
+static struct platform_driver renesas_usbhs_driver = {
+ .driver = {
+ .name = "renesas_usbhs",
+ },
+ .probe = usbhs_probe,
+ .remove = __devexit_p(usbhs_remove),
+};
+
+static int __init usbhs_init(void)
+{
+ return platform_driver_register(&renesas_usbhs_driver);
+}
+
+static void __exit usbhs_exit(void)
+{
+ platform_driver_unregister(&renesas_usbhs_driver);
+}
+
+module_init(usbhs_init);
+module_exit(usbhs_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("Renesas USB driver");
+MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>");
diff --git a/drivers/usb/renesas_usbhs/common.h b/drivers/usb/renesas_usbhs/common.h
new file mode 100644
index 0000000..0aadcb4
--- /dev/null
+++ b/drivers/usb/renesas_usbhs/common.h
@@ -0,0 +1,230 @@
+/*
+ * Renesas USB driver
+ *
+ * Copyright (C) 2011 Renesas Solutions Corp.
+ * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ */
+#ifndef RENESAS_USB_DRIVER_H
+#define RENESAS_USB_DRIVER_H
+
+#include <linux/platform_device.h>
+#include <linux/usb/renesas_usbhs.h>
+
+struct usbhs_priv;
+
+#include "./mod.h"
+#include "./pipe.h"
+
+/*
+ *
+ * register define
+ *
+ */
+#define SYSCFG 0x0000
+#define BUSWAIT 0x0002
+#define DVSTCTR 0x0008
+#define CFIFO 0x0014
+#define CFIFOSEL 0x0020
+#define CFIFOCTR 0x0022
+#define INTENB0 0x0030
+#define INTENB1 0x0032
+#define BRDYENB 0x0036
+#define NRDYENB 0x0038
+#define BEMPENB 0x003A
+#define INTSTS0 0x0040
+#define INTSTS1 0x0042
+#define BRDYSTS 0x0046
+#define NRDYSTS 0x0048
+#define BEMPSTS 0x004A
+#define FRMNUM 0x004C
+#define USBREQ 0x0054 /* USB request type register */
+#define USBVAL 0x0056 /* USB request value register */
+#define USBINDX 0x0058 /* USB request index register */
+#define USBLENG 0x005A /* USB request length register */
+#define DCPCFG 0x005C
+#define DCPMAXP 0x005E
+#define DCPCTR 0x0060
+#define PIPESEL 0x0064
+#define PIPECFG 0x0068
+#define PIPEBUF 0x006A
+#define PIPEMAXP 0x006C
+#define PIPEPERI 0x006E
+#define PIPEnCTR 0x0070
+
+/* SYSCFG */
+#define SCKE (1 << 10) /* USB Module Clock Enable */
+#define HSE (1 << 7) /* High-Speed Operation Enable */
+#define DCFM (1 << 6) /* Controller Function Select */
+#define DRPD (1 << 5) /* D+ Line/D- Line Resistance Control */
+#define DPRPU (1 << 4) /* D+ Line Resistance Control */
+#define USBE (1 << 0) /* USB Module Operation Enable */
+
+/* DVSTCTR */
+#define EXTLP (1 << 10) /* Controls the EXTLP pin output state */
+#define PWEN (1 << 9) /* Controls the PWEN pin output state */
+#define RHST (0x7) /* Reset Handshake */
+#define RHST_LOW_SPEED 1 /* Low-speed connection */
+#define RHST_FULL_SPEED 2 /* Full-speed connection */
+#define RHST_HIGH_SPEED 3 /* High-speed connection */
+
+/* CFIFOSEL */
+#define MBW_32 (0x2 << 10) /* CFIFO Port Access Bit Width */
+
+/* CFIFOCTR */
+#define BVAL (1 << 15) /* Buffer Memory Enable Flag */
+#define BCLR (1 << 14) /* CPU buffer clear */
+#define FRDY (1 << 13) /* FIFO Port Ready */
+#define DTLN_MASK (0x0FFF) /* Receive Data Length */
+
+/* INTENB0 */
+#define VBSE (1 << 15) /* Enable IRQ VBUS_0 and VBUSIN_0 */
+#define RSME (1 << 14) /* Enable IRQ Resume */
+#define SOFE (1 << 13) /* Enable IRQ Frame Number Update */
+#define DVSE (1 << 12) /* Enable IRQ Device State Transition */
+#define CTRE (1 << 11) /* Enable IRQ Control Stage Transition */
+#define BEMPE (1 << 10) /* Enable IRQ Buffer Empty */
+#define NRDYE (1 << 9) /* Enable IRQ Buffer Not Ready Response */
+#define BRDYE (1 << 8) /* Enable IRQ Buffer Ready */
+
+/* INTENB1 */
+#define BCHGE (1 << 14) /* USB Bus Change Interrupt Enable */
+#define DTCHE (1 << 12) /* Disconnection Detect Interrupt Enable */
+#define ATTCHE (1 << 11) /* Connection Detect Interrupt Enable */
+#define EOFERRE (1 << 6) /* EOF Error Detect Interrupt Enable */
+#define SIGNE (1 << 5) /* Setup Transaction Error Interrupt Enable */
+#define SACKE (1 << 4) /* Setup Transaction ACK Interrupt Enable */
+
+/* INTSTS0 */
+#define VBINT (1 << 15) /* VBUS0_0 and VBUS1_0 Interrupt Status */
+#define DVST (1 << 12) /* Device State Transition Interrupt Status */
+#define CTRT (1 << 11) /* Control Stage Interrupt Status */
+#define BEMP (1 << 10) /* Buffer Empty Interrupt Status */
+#define BRDY (1 << 8) /* Buffer Ready Interrupt Status */
+#define VBSTS (1 << 7) /* VBUS_0 and VBUSIN_0 Input Status */
+#define VALID (1 << 3) /* USB Request Receive */
+
+#define DVSQ_MASK (0x3 << 4) /* Device State */
+#define POWER_STATE (0 << 4)
+#define DEFAULT_STATE (1 << 4)
+#define ADDRESS_STATE (2 << 4)
+#define CONFIGURATION_STATE (3 << 4)
+
+#define CTSQ_MASK (0x7) /* Control Transfer Stage */
+#define IDLE_SETUP_STAGE 0 /* Idle stage or setup stage */
+#define READ_DATA_STAGE 1 /* Control read data stage */
+#define READ_STATUS_STAGE 2 /* Control read status stage */
+#define WRITE_DATA_STAGE 3 /* Control write data stage */
+#define WRITE_STATUS_STAGE 4 /* Control write status stage */
+#define NODATA_STATUS_STAGE 5 /* Control write NoData status stage */
+#define SEQUENCE_ERROR 6 /* Control transfer sequence error */
+
+/* PIPECFG */
+/* DCPCFG */
+#define TYPE_NONE (0 << 14) /* Transfer Type */
+#define TYPE_BULK (1 << 14)
+#define TYPE_INT (2 << 14)
+#define TYPE_ISO (3 << 14)
+#define DBLB (1 << 9) /* Double Buffer Mode */
+#define SHTNAK (1 << 7) /* Pipe Disable in Transfer End */
+#define DIR_OUT (1 << 4) /* Transfer Direction */
+
+/* PIPEMAXP */
+/* DCPMAXP */
+#define DEVSEL_MASK (0xF << 12) /* Device Select */
+#define DCP_MAXP_MASK (0x7F)
+#define PIPE_MAXP_MASK (0x7FF)
+
+/* PIPEBUF */
+#define BUFSIZE_SHIFT 10
+#define BUFSIZE_MASK (0x1F << BUFSIZE_SHIFT)
+#define BUFNMB_MASK (0xFF)
+
+/* PIPEnCTR */
+/* DCPCTR */
+#define BSTS (1 << 15) /* Buffer Status */
+#define CSSTS (1 << 12) /* CSSTS Status */
+#define SQCLR (1 << 8) /* Toggle Bit Clear */
+#define ACLRM (1 << 9) /* Buffer Auto-Clear Mode */
+#define PBUSY (1 << 5) /* Pipe Busy */
+#define PID_MASK (0x3) /* Response PID */
+#define PID_NAK 0
+#define PID_BUF 1
+#define PID_STALL10 2
+#define PID_STALL11 3
+
+#define CCPL (1 << 2) /* Control Transfer End Enable */
+
+/* FRMNUM */
+#define FRNM_MASK (0x7FF)
+
+/*
+ * struct
+ */
+struct usbhs_priv {
+
+ void __iomem *base;
+ unsigned int irq;
+
+ struct renesas_usbhs_platform_callback *pfunc;
+ struct renesas_usbhs_driver_param *dparam;
+
+ struct delayed_work notify_hotplug_work;
+ struct platform_device *pdev;
+
+ spinlock_t lock;
+
+ u32 flags;
+
+ /*
+ * module control
+ */
+ struct usbhs_mod_info mod_info;
+
+ /*
+ * pipe control
+ */
+ struct usbhs_pipe_info pipe_info;
+};
+
+/*
+ * common
+ */
+u16 usbhs_read(struct usbhs_priv *priv, u32 reg);
+void usbhs_write(struct usbhs_priv *priv, u32 reg, u16 data);
+void usbhs_bset(struct usbhs_priv *priv, u32 reg, u16 mask, u16 data);
+
+int usbhsc_drvcllbck_notify_hotplug(struct platform_device *pdev);
+/*
+ * sysconfig
+ */
+void usbhs_sys_clock_ctrl(struct usbhs_priv *priv, int enable);
+void usbhs_sys_hispeed_ctrl(struct usbhs_priv *priv, int enable);
+void usbhs_sys_usb_ctrl(struct usbhs_priv *priv, int enable);
+void usbhs_sys_host_ctrl(struct usbhs_priv *priv, int enable);
+void usbhs_sys_function_ctrl(struct usbhs_priv *priv, int enable);
+
+/*
+ * frame
+ */
+int usbhs_frame_get_num(struct usbhs_priv *priv);
+
+/*
+ * data
+ */
+struct usbhs_priv *usbhs_pdev_to_priv(struct platform_device *pdev);
+#define usbhs_get_dparam(priv, param) (priv->dparam->param)
+#define usbhs_priv_to_pdev(priv) (priv->pdev)
+#define usbhs_priv_to_dev(priv) (&priv->pdev->dev)
+#define usbhs_priv_to_lock(priv) (&priv->lock)
+
+#endif /* RENESAS_USB_DRIVER_H */
diff --git a/drivers/usb/renesas_usbhs/mod.c b/drivers/usb/renesas_usbhs/mod.c
new file mode 100644
index 0000000..a577f8f
--- /dev/null
+++ b/drivers/usb/renesas_usbhs/mod.c
@@ -0,0 +1,328 @@
+/*
+ * Renesas USB driver
+ *
+ * Copyright (C) 2011 Renesas Solutions Corp.
+ * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ */
+#include <linux/interrupt.h>
+
+#include "./common.h"
+#include "./mod.h"
+
+#define usbhs_priv_to_modinfo(priv) (&priv->mod_info)
+#define usbhs_mod_info_call(priv, func, param...) \
+({ \
+ struct usbhs_mod_info *info; \
+ info = usbhs_priv_to_modinfo(priv); \
+ !info->func ? 0 : \
+ info->func(param); \
+})
+
+/*
+ * autonomy
+ *
+ * these functions are used if platform doesn't have external phy.
+ * -> there is no "notify_hotplug" callback from platform
+ * -> call "notify_hotplug" by itself
+ * -> use own interrupt to connect/disconnect
+ * -> it mean module clock is always ON
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~
+ */
+static int usbhsm_autonomy_get_vbus(struct platform_device *pdev)
+{
+ struct usbhs_priv *priv = usbhs_pdev_to_priv(pdev);
+
+ return VBSTS & usbhs_read(priv, INTSTS0);
+}
+
+static int usbhsm_autonomy_irq_vbus(struct usbhs_priv *priv,
+ struct usbhs_irq_state *irq_state)
+{
+ struct platform_device *pdev = usbhs_priv_to_pdev(priv);
+
+ return usbhsc_drvcllbck_notify_hotplug(pdev);
+}
+
+void usbhs_mod_autonomy_mode(struct usbhs_priv *priv)
+{
+ struct usbhs_mod_info *info = usbhs_priv_to_modinfo(priv);
+
+ info->irq_vbus = usbhsm_autonomy_irq_vbus;
+ priv->pfunc->get_vbus = usbhsm_autonomy_get_vbus;
+
+ usbhs_irq_callback_update(priv, NULL);
+}
+
+/*
+ * host / gadget functions
+ *
+ * renesas_usbhs host/gadget can register itself by below functions.
+ * these functions are called when probe
+ *
+ */
+void usbhs_mod_register(struct usbhs_priv *priv, struct usbhs_mod *mod, int id)
+{
+ struct usbhs_mod_info *info = usbhs_priv_to_modinfo(priv);
+
+ info->mod[id] = mod;
+ mod->priv = priv;
+}
+
+struct usbhs_mod *usbhs_mod_get(struct usbhs_priv *priv, int id)
+{
+ struct usbhs_mod_info *info = usbhs_priv_to_modinfo(priv);
+ struct usbhs_mod *ret = NULL;
+
+ switch (id) {
+ case USBHS_HOST:
+ case USBHS_GADGET:
+ ret = info->mod[id];
+ break;
+ }
+
+ return ret;
+}
+
+int usbhs_mod_is_host(struct usbhs_priv *priv, struct usbhs_mod *mod)
+{
+ struct usbhs_mod_info *info = usbhs_priv_to_modinfo(priv);
+
+ if (!mod)
+ return -EINVAL;
+
+ return info->mod[USBHS_HOST] == mod;
+}
+
+struct usbhs_mod *usbhs_mod_get_current(struct usbhs_priv *priv)
+{
+ struct usbhs_mod_info *info = usbhs_priv_to_modinfo(priv);
+
+ return info->curt;
+}
+
+int usbhs_mod_change(struct usbhs_priv *priv, int id)
+{
+ struct usbhs_mod_info *info = usbhs_priv_to_modinfo(priv);
+ struct usbhs_mod *mod = NULL;
+ int ret = 0;
+
+ /* id < 0 mean no current */
+ switch (id) {
+ case USBHS_HOST:
+ case USBHS_GADGET:
+ mod = info->mod[id];
+ break;
+ default:
+ ret = -EINVAL;
+ }
+ info->curt = mod;
+
+ return ret;
+}
+
+static irqreturn_t usbhs_interrupt(int irq, void *data);
+int usbhs_mod_probe(struct usbhs_priv *priv)
+{
+ struct device *dev = usbhs_priv_to_dev(priv);
+ int ret;
+
+ /*
+ * install host/gadget driver
+ */
+ ret = usbhs_mod_gadget_probe(priv);
+ if (ret < 0)
+ return ret;
+
+ /* irq settings */
+ ret = request_irq(priv->irq, usbhs_interrupt,
+ IRQF_DISABLED, dev_name(dev), priv);
+ if (ret) {
+ dev_err(dev, "irq request err\n");
+ goto mod_init_gadget_err;
+ }
+
+ return ret;
+
+mod_init_gadget_err:
+ usbhs_mod_gadget_remove(priv);
+
+ return ret;
+}
+
+void usbhs_mod_remove(struct usbhs_priv *priv)
+{
+ usbhs_mod_gadget_remove(priv);
+ free_irq(priv->irq, priv);
+}
+
+/*
+ * status functions
+ */
+int usbhs_status_get_usb_speed(struct usbhs_irq_state *irq_state)
+{
+ switch (irq_state->dvstctr & RHST) {
+ case RHST_LOW_SPEED:
+ return USB_SPEED_LOW;
+ case RHST_FULL_SPEED:
+ return USB_SPEED_FULL;
+ case RHST_HIGH_SPEED:
+ return USB_SPEED_HIGH;
+ }
+
+ return USB_SPEED_UNKNOWN;
+}
+
+int usbhs_status_get_device_state(struct usbhs_irq_state *irq_state)
+{
+ int state = irq_state->intsts0 & DVSQ_MASK;
+
+ switch (state) {
+ case POWER_STATE:
+ case DEFAULT_STATE:
+ case ADDRESS_STATE:
+ case CONFIGURATION_STATE:
+ return state;
+ }
+
+ return -EIO;
+}
+
+int usbhs_status_get_ctrl_stage(struct usbhs_irq_state *irq_state)
+{
+ /*
+ * return value
+ *
+ * IDLE_SETUP_STAGE
+ * READ_DATA_STAGE
+ * READ_STATUS_STAGE
+ * WRITE_DATA_STAGE
+ * WRITE_STATUS_STAGE
+ * NODATA_STATUS_STAGE
+ * SEQUENCE_ERROR
+ */
+ return (int)irq_state->intsts0 & CTSQ_MASK;
+}
+
+static void usbhs_status_get_each_irq(struct usbhs_priv *priv,
+ struct usbhs_irq_state *state)
+{
+ struct usbhs_mod *mod = usbhs_mod_get_current(priv);
+
+ state->intsts0 = usbhs_read(priv, INTSTS0);
+ state->intsts1 = usbhs_read(priv, INTSTS1);
+
+ state->dvstctr = usbhs_read(priv, DVSTCTR);
+
+ /* mask */
+ if (mod) {
+ state->brdysts = usbhs_read(priv, BRDYSTS);
+ state->nrdysts = usbhs_read(priv, NRDYSTS);
+ state->bempsts = usbhs_read(priv, BEMPSTS);
+
+ state->bempsts &= mod->irq_bempsts;
+ state->brdysts &= mod->irq_brdysts;
+ }
+}
+
+/*
+ * interrupt
+ */
+#define INTSTS0_MAGIC 0xF800 /* acknowledge magical interrupt sources */
+#define INTSTS1_MAGIC 0xA870 /* acknowledge magical interrupt sources */
+static irqreturn_t usbhs_interrupt(int irq, void *data)
+{
+ struct usbhs_priv *priv = data;
+ struct usbhs_irq_state irq_state;
+
+ usbhs_status_get_each_irq(priv, &irq_state);
+
+ /*
+ * clear interrupt
+ *
+ * The hardware is _very_ picky to clear interrupt bit.
+ * Especially INTSTS0_MAGIC, INTSTS1_MAGIC value.
+ *
+ * see
+ * "Operation"
+ * - "Control Transfer (DCP)"
+ * - Function :: VALID bit should 0
+ */
+ usbhs_write(priv, INTSTS0, ~irq_state.intsts0 & INTSTS0_MAGIC);
+ usbhs_write(priv, INTSTS1, ~irq_state.intsts1 & INTSTS1_MAGIC);
+
+ usbhs_write(priv, BRDYSTS, 0);
+ usbhs_write(priv, NRDYSTS, 0);
+ usbhs_write(priv, BEMPSTS, 0);
+
+ /*
+ * call irq callback functions
+ * see also
+ * usbhs_irq_setting_update
+ */
+ if (irq_state.intsts0 & VBINT)
+ usbhs_mod_info_call(priv, irq_vbus, priv, &irq_state);
+
+ if (irq_state.intsts0 & DVST)
+ usbhs_mod_call(priv, irq_dev_state, priv, &irq_state);
+
+ if (irq_state.intsts0 & CTRT)
+ usbhs_mod_call(priv, irq_ctrl_stage, priv, &irq_state);
+
+ if (irq_state.intsts0 & BEMP)
+ usbhs_mod_call(priv, irq_empty, priv, &irq_state);
+
+ if (irq_state.intsts0 & BRDY)
+ usbhs_mod_call(priv, irq_ready, priv, &irq_state);
+
+ return IRQ_HANDLED;
+}
+
+void usbhs_irq_callback_update(struct usbhs_priv *priv, struct usbhs_mod *mod)
+{
+ u16 intenb0 = 0;
+ struct usbhs_mod_info *info = usbhs_priv_to_modinfo(priv);
+
+ usbhs_write(priv, INTENB0, 0);
+
+ usbhs_write(priv, BEMPENB, 0);
+ usbhs_write(priv, BRDYENB, 0);
+
+ /*
+ * see also
+ * usbhs_interrupt
+ */
+
+ /*
+ * it don't enable DVSE (intenb0) here
+ * but "mod->irq_dev_state" will be called.
+ */
+ if (info->irq_vbus)
+ intenb0 |= VBSE;
+
+ if (mod) {
+ if (mod->irq_ctrl_stage)
+ intenb0 |= CTRE;
+
+ if (mod->irq_empty && mod->irq_bempsts) {
+ usbhs_write(priv, BEMPENB, mod->irq_bempsts);
+ intenb0 |= BEMPE;
+ }
+
+ if (mod->irq_ready && mod->irq_brdysts) {
+ usbhs_write(priv, BRDYENB, mod->irq_brdysts);
+ intenb0 |= BRDYE;
+ }
+ }
+
+ usbhs_write(priv, INTENB0, intenb0);
+}
diff --git a/drivers/usb/renesas_usbhs/mod.h b/drivers/usb/renesas_usbhs/mod.h
new file mode 100644
index 0000000..5c845a2
--- /dev/null
+++ b/drivers/usb/renesas_usbhs/mod.h
@@ -0,0 +1,137 @@
+/*
+ * Renesas USB driver
+ *
+ * Copyright (C) 2011 Renesas Solutions Corp.
+ * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ */
+#ifndef RENESAS_USB_MOD_H
+#define RENESAS_USB_MOD_H
+
+#include <linux/spinlock.h>
+#include <linux/usb/renesas_usbhs.h>
+#include "./common.h"
+
+/*
+ * struct
+ */
+struct usbhs_irq_state {
+ u16 intsts0;
+ u16 intsts1;
+ u16 brdysts;
+ u16 nrdysts;
+ u16 bempsts;
+ u16 dvstctr;
+};
+
+struct usbhs_mod {
+ char *name;
+
+ /*
+ * entry point from common.c
+ */
+ int (*start)(struct usbhs_priv *priv);
+ int (*stop)(struct usbhs_priv *priv);
+
+ /* INTSTS0 :: DVST (DVSQ) */
+ int (*irq_dev_state)(struct usbhs_priv *priv,
+ struct usbhs_irq_state *irq_state);
+
+ /* INTSTS0 :: CTRT (CTSQ) */
+ int (*irq_ctrl_stage)(struct usbhs_priv *priv,
+ struct usbhs_irq_state *irq_state);
+
+ /* INTSTS0 :: BEMP */
+ /* BEMPSTS */
+ int (*irq_empty)(struct usbhs_priv *priv,
+ struct usbhs_irq_state *irq_state);
+ u16 irq_bempsts;
+
+ /* INTSTS0 :: BRDY */
+ /* BRDYSTS */
+ int (*irq_ready)(struct usbhs_priv *priv,
+ struct usbhs_irq_state *irq_state);
+ u16 irq_brdysts;
+
+ struct usbhs_priv *priv;
+};
+
+struct usbhs_mod_info {
+ struct usbhs_mod *mod[USBHS_MAX];
+ struct usbhs_mod *curt; /* current mod */
+
+ /*
+ * INTSTS0 :: VBINT
+ *
+ * This function will be used as autonomy mode
+ * when platform cannot call notify_hotplug.
+ *
+ * This callback cannot be member of "struct usbhs_mod"
+ * because it will be used even though
+ * host/gadget has not been selected.
+ */
+ int (*irq_vbus)(struct usbhs_priv *priv,
+ struct usbhs_irq_state *irq_state);
+};
+
+/*
+ * for host/gadget module
+ */
+struct usbhs_mod *usbhs_mod_get(struct usbhs_priv *priv, int id);
+struct usbhs_mod *usbhs_mod_get_current(struct usbhs_priv *priv);
+void usbhs_mod_register(struct usbhs_priv *priv, struct usbhs_mod *usb, int id);
+int usbhs_mod_is_host(struct usbhs_priv *priv, struct usbhs_mod *mod);
+int usbhs_mod_change(struct usbhs_priv *priv, int id);
+int usbhs_mod_probe(struct usbhs_priv *priv);
+void usbhs_mod_remove(struct usbhs_priv *priv);
+
+void usbhs_mod_autonomy_mode(struct usbhs_priv *priv);
+
+/*
+ * status functions
+ */
+int usbhs_status_get_usb_speed(struct usbhs_irq_state *irq_state);
+int usbhs_status_get_device_state(struct usbhs_irq_state *irq_state);
+int usbhs_status_get_ctrl_stage(struct usbhs_irq_state *irq_state);
+
+/*
+ * callback functions
+ */
+void usbhs_irq_callback_update(struct usbhs_priv *priv, struct usbhs_mod *mod);
+
+
+#define usbhs_mod_call(priv, func, param...) \
+ ({ \
+ struct usbhs_mod *mod; \
+ mod = usbhs_mod_get_current(priv); \
+ !mod ? -ENODEV : \
+ !mod->func ? 0 : \
+ mod->func(param); \
+ })
+
+/*
+ * gadget control
+ */
+#ifdef CONFIG_USB_RENESAS_USBHS_UDC
+extern int __devinit usbhs_mod_gadget_probe(struct usbhs_priv *priv);
+extern void __devexit usbhs_mod_gadget_remove(struct usbhs_priv *priv);
+#else
+static inline int usbhs_mod_gadget_probe(struct usbhs_priv *priv)
+{
+ return 0;
+}
+static inline void usbhs_mod_gadget_remove(struct usbhs_priv *priv)
+{
+}
+#endif
+
+#endif /* RENESAS_USB_MOD_H */
diff --git a/drivers/usb/renesas_usbhs/mod_gadget.c b/drivers/usb/renesas_usbhs/mod_gadget.c
new file mode 100644
index 0000000..206cfab
--- /dev/null
+++ b/drivers/usb/renesas_usbhs/mod_gadget.c
@@ -0,0 +1,1384 @@
+/*
+ * Renesas USB driver
+ *
+ * Copyright (C) 2011 Renesas Solutions Corp.
+ * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ */
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#include "common.h"
+
+/*
+ * struct
+ */
+struct usbhsg_request {
+ struct usb_request req;
+ struct list_head node;
+};
+
+#define EP_NAME_SIZE 8
+struct usbhsg_gpriv;
+struct usbhsg_pipe_handle;
+struct usbhsg_uep {
+ struct usb_ep ep;
+ struct usbhs_pipe *pipe;
+ struct list_head list;
+
+ char ep_name[EP_NAME_SIZE];
+
+ struct usbhsg_gpriv *gpriv;
+ struct usbhsg_pipe_handle *handler;
+};
+
+struct usbhsg_gpriv {
+ struct usb_gadget gadget;
+ struct usbhs_mod mod;
+
+ struct usbhsg_uep *uep;
+ int uep_size;
+
+ struct usb_gadget_driver *driver;
+
+ u32 status;
+#define USBHSG_STATUS_STARTED (1 << 0)
+#define USBHSG_STATUS_REGISTERD (1 << 1)
+#define USBHSG_STATUS_WEDGE (1 << 2)
+};
+
+struct usbhsg_pipe_handle {
+ int (*prepare)(struct usbhsg_uep *uep, struct usbhsg_request *ureq);
+ int (*try_run)(struct usbhsg_uep *uep, struct usbhsg_request *ureq);
+ void (*irq_mask)(struct usbhsg_uep *uep, int enable);
+};
+
+struct usbhsg_recip_handle {
+ char *name;
+ int (*device)(struct usbhs_priv *priv, struct usbhsg_uep *uep,
+ struct usb_ctrlrequest *ctrl);
+ int (*interface)(struct usbhs_priv *priv, struct usbhsg_uep *uep,
+ struct usb_ctrlrequest *ctrl);
+ int (*endpoint)(struct usbhs_priv *priv, struct usbhsg_uep *uep,
+ struct usb_ctrlrequest *ctrl);
+};
+
+/*
+ * macro
+ */
+#define usbhsg_priv_to_gpriv(priv) \
+ container_of( \
+ usbhs_mod_get(priv, USBHS_GADGET), \
+ struct usbhsg_gpriv, mod)
+
+#define __usbhsg_for_each_uep(start, pos, g, i) \
+ for (i = start, pos = (g)->uep; \
+ i < (g)->uep_size; \
+ i++, pos = (g)->uep + i)
+
+#define usbhsg_for_each_uep(pos, gpriv, i) \
+ __usbhsg_for_each_uep(1, pos, gpriv, i)
+
+#define usbhsg_for_each_uep_with_dcp(pos, gpriv, i) \
+ __usbhsg_for_each_uep(0, pos, gpriv, i)
+
+#define usbhsg_gadget_to_gpriv(g)\
+ container_of(g, struct usbhsg_gpriv, gadget)
+
+#define usbhsg_req_to_ureq(r)\
+ container_of(r, struct usbhsg_request, req)
+
+#define usbhsg_ep_to_uep(e) container_of(e, struct usbhsg_uep, ep)
+#define usbhsg_gpriv_to_lock(gp) usbhs_priv_to_lock((gp)->mod.priv)
+#define usbhsg_gpriv_to_dev(gp) usbhs_priv_to_dev((gp)->mod.priv)
+#define usbhsg_gpriv_to_priv(gp) ((gp)->mod.priv)
+#define usbhsg_gpriv_to_dcp(gp) ((gp)->uep)
+#define usbhsg_gpriv_to_nth_uep(gp, i) ((gp)->uep + i)
+#define usbhsg_uep_to_gpriv(u) ((u)->gpriv)
+#define usbhsg_uep_to_pipe(u) ((u)->pipe)
+#define usbhsg_pipe_to_uep(p) ((p)->mod_private)
+#define usbhsg_is_dcp(u) ((u) == usbhsg_gpriv_to_dcp((u)->gpriv))
+
+#define usbhsg_is_not_connected(gp) ((gp)->gadget.speed == USB_SPEED_UNKNOWN)
+
+/* status */
+#define usbhsg_status_init(gp) do {(gp)->status = 0; } while (0)
+#define usbhsg_status_set(gp, b) (gp->status |= b)
+#define usbhsg_status_clr(gp, b) (gp->status &= ~b)
+#define usbhsg_status_has(gp, b) (gp->status & b)
+
+/*
+ * usbhsg_trylock
+ *
+ * This driver don't use spin_try_lock
+ * to avoid warning of CONFIG_DEBUG_SPINLOCK
+ */
+static spinlock_t *usbhsg_trylock(struct usbhsg_gpriv *gpriv,
+ unsigned long *flags)
+{
+ spinlock_t *lock = usbhsg_gpriv_to_lock(gpriv);
+
+ /* check spin lock status
+ * to avoid deadlock/nest */
+ if (spin_is_locked(lock))
+ return NULL;
+
+ spin_lock_irqsave(lock, *flags);
+
+ return lock;
+}
+
+static void usbhsg_unlock(spinlock_t *lock, unsigned long *flags)
+{
+ if (!lock)
+ return;
+
+ spin_unlock_irqrestore(lock, *flags);
+}
+
+/*
+ * list push/pop
+ */
+static void usbhsg_queue_push(struct usbhsg_uep *uep,
+ struct usbhsg_request *ureq)
+{
+ struct usbhsg_gpriv *gpriv = usbhsg_uep_to_gpriv(uep);
+ struct device *dev = usbhsg_gpriv_to_dev(gpriv);
+ struct usbhs_pipe *pipe = usbhsg_uep_to_pipe(uep);
+
+ /*
+ ********* assume under spin lock *********
+ */
+ list_del_init(&ureq->node);
+ list_add_tail(&ureq->node, &uep->list);
+ ureq->req.actual = 0;
+ ureq->req.status = -EINPROGRESS;
+
+ dev_dbg(dev, "pipe %d : queue push (%d)\n",
+ usbhs_pipe_number(pipe),
+ ureq->req.length);
+}
+
+static struct usbhsg_request *usbhsg_queue_get(struct usbhsg_uep *uep)
+{
+ /*
+ ********* assume under spin lock *********
+ */
+ if (list_empty(&uep->list))
+ return NULL;
+
+ return list_entry(uep->list.next, struct usbhsg_request, node);
+}
+
+#define usbhsg_queue_prepare(uep) __usbhsg_queue_handler(uep, 1);
+#define usbhsg_queue_handle(uep) __usbhsg_queue_handler(uep, 0);
+static int __usbhsg_queue_handler(struct usbhsg_uep *uep, int prepare)
+{
+ struct usbhsg_gpriv *gpriv = usbhsg_uep_to_gpriv(uep);
+ struct device *dev = usbhsg_gpriv_to_dev(gpriv);
+ struct usbhsg_request *ureq;
+ spinlock_t *lock;
+ unsigned long flags;
+ int ret = 0;
+
+ if (!uep->handler) {
+ dev_err(dev, "no handler function\n");
+ return -EIO;
+ }
+
+ /*
+ * CAUTION [*queue handler*]
+ *
+ * This function will be called for start/restart queue operation.
+ * OTOH the most much worry for USB driver is spinlock nest.
+ * Specially it are
+ * - usb_ep_ops :: queue
+ * - usb_request :: complete
+ *
+ * But the caller of this function need not care about spinlock.
+ * This function is using usbhsg_trylock for it.
+ * if "is_locked" is 1, this mean this function lock it.
+ * but if it is 0, this mean it is already under spin lock.
+ * see also
+ * CAUTION [*endpoint queue*]
+ * CAUTION [*request complete*]
+ */
+
+ /****************** spin try lock *******************/
+ lock = usbhsg_trylock(gpriv, &flags);
+
+ ureq = usbhsg_queue_get(uep);
+ if (ureq) {
+ if (prepare)
+ ret = uep->handler->prepare(uep, ureq);
+ else
+ ret = uep->handler->try_run(uep, ureq);
+ }
+ usbhsg_unlock(lock, &flags);
+ /******************** spin unlock ******************/
+
+ return ret;
+}
+
+static void usbhsg_queue_pop(struct usbhsg_uep *uep,
+ struct usbhsg_request *ureq,
+ int status)
+{
+ struct usbhsg_gpriv *gpriv = usbhsg_uep_to_gpriv(uep);
+ struct usbhs_pipe *pipe = usbhsg_uep_to_pipe(uep);
+ struct device *dev = usbhsg_gpriv_to_dev(gpriv);
+
+ /*
+ ********* assume under spin lock *********
+ */
+
+ /*
+ * CAUTION [*request complete*]
+ *
+ * There is a possibility not to be called in correct order
+ * if "complete" is called without spinlock.
+ *
+ * So, this function assume it is under spinlock,
+ * and call usb_request :: complete.
+ *
+ * But this "complete" will push next usb_request.
+ * It mean "usb_ep_ops :: queue" which is using spinlock is called
+ * under spinlock.
+ *
+ * To avoid dead-lock, this driver is using usbhsg_trylock.
+ * CAUTION [*endpoint queue*]
+ * CAUTION [*queue handler*]
+ */
+
+ dev_dbg(dev, "pipe %d : queue pop\n", usbhs_pipe_number(pipe));
+
+ list_del_init(&ureq->node);
+
+ ureq->req.status = status;
+ ureq->req.complete(&uep->ep, &ureq->req);
+
+ /* more request ? */
+ if (0 == status)
+ usbhsg_queue_prepare(uep);
+}
+
+/*
+ * irq enable/disable function
+ */
+#define usbhsg_irq_callback_ctrl(uep, status, enable) \
+ ({ \
+ struct usbhsg_gpriv *gpriv = usbhsg_uep_to_gpriv(uep); \
+ struct usbhs_pipe *pipe = usbhsg_uep_to_pipe(uep); \
+ struct usbhs_priv *priv = usbhsg_gpriv_to_priv(gpriv); \
+ struct usbhs_mod *mod = usbhs_mod_get_current(priv); \
+ if (!mod) \
+ return; \
+ if (enable) \
+ mod->irq_##status |= (1 << usbhs_pipe_number(pipe)); \
+ else \
+ mod->irq_##status &= ~(1 << usbhs_pipe_number(pipe)); \
+ usbhs_irq_callback_update(priv, mod); \
+ })
+
+static void usbhsg_irq_empty_ctrl(struct usbhsg_uep *uep, int enable)
+{
+ usbhsg_irq_callback_ctrl(uep, bempsts, enable);
+}
+
+static void usbhsg_irq_ready_ctrl(struct usbhsg_uep *uep, int enable)
+{
+ usbhsg_irq_callback_ctrl(uep, brdysts, enable);
+}
+
+/*
+ * handler function
+ */
+static int usbhsg_try_run_ctrl_stage_end(struct usbhsg_uep *uep,
+ struct usbhsg_request *ureq)
+{
+ struct usbhs_pipe *pipe = usbhsg_uep_to_pipe(uep);
+
+ /*
+ ********* assume under spin lock *********
+ */
+
+ usbhs_dcp_control_transfer_done(pipe);
+ usbhsg_queue_pop(uep, ureq, 0);
+
+ return 0;
+}
+
+static int usbhsg_try_run_send_packet(struct usbhsg_uep *uep,
+ struct usbhsg_request *ureq)
+{
+ struct usbhs_pipe *pipe = usbhsg_uep_to_pipe(uep);
+ struct usb_request *req = &ureq->req;
+ struct usbhsg_gpriv *gpriv = usbhsg_uep_to_gpriv(uep);
+ struct device *dev = usbhsg_gpriv_to_dev(gpriv);
+ void *buf;
+ int remainder, send;
+ int is_done = 0;
+ int enable;
+ int maxp;
+
+ /*
+ ********* assume under spin lock *********
+ */
+
+ maxp = usbhs_pipe_get_maxpacket(pipe);
+ buf = req->buf + req->actual;
+ remainder = req->length - req->actual;
+
+ send = usbhs_fifo_write(pipe, buf, remainder);
+
+ /*
+ * send < 0 : pipe busy
+ * send = 0 : send zero packet
+ * send > 0 : send data
+ *
+ * send <= max_packet
+ */
+ if (send > 0)
+ req->actual += send;
+
+ /* send all packet ? */
+ if (send < remainder)
+ is_done = 0; /* there are remainder data */
+ else if (send < maxp)
+ is_done = 1; /* short packet */
+ else
+ is_done = !req->zero; /* send zero packet ? */
+
+ dev_dbg(dev, " send %d (%d/ %d/ %d/ %d)\n",
+ usbhs_pipe_number(pipe),
+ remainder, send, is_done, req->zero);
+
+ /*
+ * enable interrupt and send again in irq handler
+ * if it still have remainder data which should be sent.
+ */
+ enable = !is_done;
+ uep->handler->irq_mask(uep, enable);
+
+ /*
+ * usbhs_fifo_enable execute
+ * - after callback_update,
+ * - before queue_pop / stage_end
+ */
+ usbhs_fifo_enable(pipe);
+
+ /*
+ * all data were sent ?
+ */
+ if (is_done) {
+ /* it care below call in
+ "function mode" */
+ if (usbhsg_is_dcp(uep))
+ usbhs_dcp_control_transfer_done(pipe);
+
+ usbhsg_queue_pop(uep, ureq, 0);
+ }
+
+ return 0;
+}
+
+static int usbhsg_prepare_send_packet(struct usbhsg_uep *uep,
+ struct usbhsg_request *ureq)
+{
+ struct usbhs_pipe *pipe = usbhsg_uep_to_pipe(uep);
+
+ /*
+ ********* assume under spin lock *********
+ */
+
+ usbhs_fifo_prepare_write(pipe);
+ usbhsg_try_run_send_packet(uep, ureq);
+
+ return 0;
+}
+
+static int usbhsg_try_run_receive_packet(struct usbhsg_uep *uep,
+ struct usbhsg_request *ureq)
+{
+ struct usbhs_pipe *pipe = usbhsg_uep_to_pipe(uep);
+ struct usb_request *req = &ureq->req;
+ struct usbhsg_gpriv *gpriv = usbhsg_uep_to_gpriv(uep);
+ struct device *dev = usbhsg_gpriv_to_dev(gpriv);
+ void *buf;
+ int maxp;
+ int remainder, recv;
+ int is_done = 0;
+
+ /*
+ ********* assume under spin lock *********
+ */
+
+ maxp = usbhs_pipe_get_maxpacket(pipe);
+ buf = req->buf + req->actual;
+ remainder = req->length - req->actual;
+
+ recv = usbhs_fifo_read(pipe, buf, remainder);
+ /*
+ * recv < 0 : pipe busy
+ * recv >= 0 : receive data
+ *
+ * recv <= max_packet
+ */
+ if (recv < 0)
+ return -EBUSY;
+
+ /* update parameters */
+ req->actual += recv;
+
+ if ((recv == remainder) || /* receive all data */
+ (recv < maxp)) /* short packet */
+ is_done = 1;
+
+ dev_dbg(dev, " recv %d (%d/ %d/ %d/ %d)\n",
+ usbhs_pipe_number(pipe),
+ remainder, recv, is_done, req->zero);
+
+ /* read all data ? */
+ if (is_done) {
+ int disable = 0;
+
+ uep->handler->irq_mask(uep, disable);
+ usbhs_fifo_disable(pipe);
+ usbhsg_queue_pop(uep, ureq, 0);
+ }
+
+ return 0;
+}
+
+static int usbhsg_prepare_receive_packet(struct usbhsg_uep *uep,
+ struct usbhsg_request *ureq)
+{
+ struct usbhs_pipe *pipe = usbhsg_uep_to_pipe(uep);
+ int enable = 1;
+ int ret;
+
+ /*
+ ********* assume under spin lock *********
+ */
+
+ ret = usbhs_fifo_prepare_read(pipe);
+ if (ret < 0)
+ return ret;
+
+ /*
+ * data will be read in interrupt handler
+ */
+ uep->handler->irq_mask(uep, enable);
+
+ return ret;
+}
+
+static struct usbhsg_pipe_handle usbhsg_handler_send_by_empty = {
+ .prepare = usbhsg_prepare_send_packet,
+ .try_run = usbhsg_try_run_send_packet,
+ .irq_mask = usbhsg_irq_empty_ctrl,
+};
+
+static struct usbhsg_pipe_handle usbhsg_handler_send_by_ready = {
+ .prepare = usbhsg_prepare_send_packet,
+ .try_run = usbhsg_try_run_send_packet,
+ .irq_mask = usbhsg_irq_ready_ctrl,
+};
+
+static struct usbhsg_pipe_handle usbhsg_handler_recv_by_ready = {
+ .prepare = usbhsg_prepare_receive_packet,
+ .try_run = usbhsg_try_run_receive_packet,
+ .irq_mask = usbhsg_irq_ready_ctrl,
+};
+
+static struct usbhsg_pipe_handle usbhsg_handler_ctrl_stage_end = {
+ .prepare = usbhsg_try_run_ctrl_stage_end,
+ .try_run = usbhsg_try_run_ctrl_stage_end,
+};
+
+/*
+ * DCP pipe can NOT use "ready interrupt" for "send"
+ * it should use "empty" interrupt.
+ * see
+ * "Operation" - "Interrupt Function" - "BRDY Interrupt"
+ *
+ * on the other hand, normal pipe can use "ready interrupt" for "send"
+ * even though it is single/double buffer
+ */
+#define usbhsg_handler_send_ctrl usbhsg_handler_send_by_empty
+#define usbhsg_handler_recv_ctrl usbhsg_handler_recv_by_ready
+
+#define usbhsg_handler_send_packet usbhsg_handler_send_by_ready
+#define usbhsg_handler_recv_packet usbhsg_handler_recv_by_ready
+
+/*
+ * USB_TYPE_STANDARD / clear feature functions
+ */
+static int usbhsg_recip_handler_std_control_done(struct usbhs_priv *priv,
+ struct usbhsg_uep *uep,
+ struct usb_ctrlrequest *ctrl)
+{
+ struct usbhsg_gpriv *gpriv = usbhsg_priv_to_gpriv(priv);
+ struct usbhsg_uep *dcp = usbhsg_gpriv_to_dcp(gpriv);
+ struct usbhs_pipe *pipe = usbhsg_uep_to_pipe(dcp);
+
+ usbhs_dcp_control_transfer_done(pipe);
+
+ return 0;
+}
+
+static int usbhsg_recip_handler_std_clear_endpoint(struct usbhs_priv *priv,
+ struct usbhsg_uep *uep,
+ struct usb_ctrlrequest *ctrl)
+{
+ struct usbhsg_gpriv *gpriv = usbhsg_uep_to_gpriv(uep);
+ struct usbhs_pipe *pipe = usbhsg_uep_to_pipe(uep);
+
+ if (!usbhsg_status_has(gpriv, USBHSG_STATUS_WEDGE)) {
+ usbhs_fifo_disable(pipe);
+ usbhs_pipe_clear_sequence(pipe);
+ usbhs_fifo_enable(pipe);
+ }
+
+ usbhsg_recip_handler_std_control_done(priv, uep, ctrl);
+
+ usbhsg_queue_prepare(uep);
+
+ return 0;
+}
+
+struct usbhsg_recip_handle req_clear_feature = {
+ .name = "clear feature",
+ .device = usbhsg_recip_handler_std_control_done,
+ .interface = usbhsg_recip_handler_std_control_done,
+ .endpoint = usbhsg_recip_handler_std_clear_endpoint,
+};
+
+/*
+ * USB_TYPE handler
+ */
+static int usbhsg_recip_run_handle(struct usbhs_priv *priv,
+ struct usbhsg_recip_handle *handler,
+ struct usb_ctrlrequest *ctrl)
+{
+ struct usbhsg_gpriv *gpriv = usbhsg_priv_to_gpriv(priv);
+ struct device *dev = usbhsg_gpriv_to_dev(gpriv);
+ struct usbhsg_uep *uep;
+ int recip = ctrl->bRequestType & USB_RECIP_MASK;
+ int nth = le16_to_cpu(ctrl->wIndex) & USB_ENDPOINT_NUMBER_MASK;
+ int ret;
+ int (*func)(struct usbhs_priv *priv, struct usbhsg_uep *uep,
+ struct usb_ctrlrequest *ctrl);
+ char *msg;
+
+ uep = usbhsg_gpriv_to_nth_uep(gpriv, nth);
+ if (!usbhsg_uep_to_pipe(uep)) {
+ dev_err(dev, "wrong recip request\n");
+ return -EINVAL;
+ }
+
+ switch (recip) {
+ case USB_RECIP_DEVICE:
+ msg = "DEVICE";
+ func = handler->device;
+ break;
+ case USB_RECIP_INTERFACE:
+ msg = "INTERFACE";
+ func = handler->interface;
+ break;
+ case USB_RECIP_ENDPOINT:
+ msg = "ENDPOINT";
+ func = handler->endpoint;
+ break;
+ default:
+ dev_warn(dev, "unsupported RECIP(%d)\n", recip);
+ func = NULL;
+ ret = -EINVAL;
+ }
+
+ if (func) {
+ dev_dbg(dev, "%s (pipe %d :%s)\n", handler->name, nth, msg);
+ ret = func(priv, uep, ctrl);
+ }
+
+ return ret;
+}
+
+/*
+ * irq functions
+ *
+ * it will be called from usbhs_interrupt
+ */
+static int usbhsg_irq_dev_state(struct usbhs_priv *priv,
+ struct usbhs_irq_state *irq_state)
+{
+ struct usbhsg_gpriv *gpriv = usbhsg_priv_to_gpriv(priv);
+ struct device *dev = usbhsg_gpriv_to_dev(gpriv);
+
+ gpriv->gadget.speed = usbhs_status_get_usb_speed(irq_state);
+
+ dev_dbg(dev, "state = %x : speed : %d\n",
+ usbhs_status_get_device_state(irq_state),
+ gpriv->gadget.speed);
+
+ return 0;
+}
+
+static int usbhsg_irq_ctrl_stage(struct usbhs_priv *priv,
+ struct usbhs_irq_state *irq_state)
+{
+ struct usbhsg_gpriv *gpriv = usbhsg_priv_to_gpriv(priv);
+ struct usbhsg_uep *dcp = usbhsg_gpriv_to_dcp(gpriv);
+ struct usbhs_pipe *pipe = usbhsg_uep_to_pipe(dcp);
+ struct device *dev = usbhsg_gpriv_to_dev(gpriv);
+ struct usb_ctrlrequest ctrl;
+ struct usbhsg_recip_handle *recip_handler = NULL;
+ int stage = usbhs_status_get_ctrl_stage(irq_state);
+ int ret = 0;
+
+ dev_dbg(dev, "stage = %d\n", stage);
+
+ /*
+ * see Manual
+ *
+ * "Operation"
+ * - "Interrupt Function"
+ * - "Control Transfer Stage Transition Interrupt"
+ * - Fig. "Control Transfer Stage Transitions"
+ */
+
+ switch (stage) {
+ case READ_DATA_STAGE:
+ dcp->handler = &usbhsg_handler_send_ctrl;
+ break;
+ case WRITE_DATA_STAGE:
+ dcp->handler = &usbhsg_handler_recv_ctrl;
+ break;
+ case NODATA_STATUS_STAGE:
+ dcp->handler = &usbhsg_handler_ctrl_stage_end;
+ break;
+ default:
+ return ret;
+ }
+
+ /*
+ * get usb request
+ */
+ usbhs_usbreq_get_val(priv, &ctrl);
+
+ switch (ctrl.bRequestType & USB_TYPE_MASK) {
+ case USB_TYPE_STANDARD:
+ switch (ctrl.bRequest) {
+ case USB_REQ_CLEAR_FEATURE:
+ recip_handler = &req_clear_feature;
+ break;
+ }
+ }
+
+ /*
+ * setup stage / run recip
+ */
+ if (recip_handler)
+ ret = usbhsg_recip_run_handle(priv, recip_handler, &ctrl);
+ else
+ ret = gpriv->driver->setup(&gpriv->gadget, &ctrl);
+
+ if (ret < 0)
+ usbhs_fifo_stall(pipe);
+
+ return ret;
+}
+
+static int usbhsg_irq_empty(struct usbhs_priv *priv,
+ struct usbhs_irq_state *irq_state)
+{
+ struct usbhsg_gpriv *gpriv = usbhsg_priv_to_gpriv(priv);
+ struct usbhsg_uep *uep;
+ struct usbhs_pipe *pipe;
+ struct device *dev = usbhsg_gpriv_to_dev(gpriv);
+ int i, ret;
+
+ if (!irq_state->bempsts) {
+ dev_err(dev, "debug %s !!\n", __func__);
+ return -EIO;
+ }
+
+ dev_dbg(dev, "irq empty [0x%04x]\n", irq_state->bempsts);
+
+ /*
+ * search interrupted "pipe"
+ * not "uep".
+ */
+ usbhs_for_each_pipe_with_dcp(pipe, priv, i) {
+ if (!(irq_state->bempsts & (1 << i)))
+ continue;
+
+ uep = usbhsg_pipe_to_uep(pipe);
+ ret = usbhsg_queue_handle(uep);
+ if (ret < 0)
+ dev_err(dev, "send error %d : %d\n", i, ret);
+ }
+
+ return 0;
+}
+
+static int usbhsg_irq_ready(struct usbhs_priv *priv,
+ struct usbhs_irq_state *irq_state)
+{
+ struct usbhsg_gpriv *gpriv = usbhsg_priv_to_gpriv(priv);
+ struct usbhsg_uep *uep;
+ struct usbhs_pipe *pipe;
+ struct device *dev = usbhsg_gpriv_to_dev(gpriv);
+ int i, ret;
+
+ if (!irq_state->brdysts) {
+ dev_err(dev, "debug %s !!\n", __func__);
+ return -EIO;
+ }
+
+ dev_dbg(dev, "irq ready [0x%04x]\n", irq_state->brdysts);
+
+ /*
+ * search interrupted "pipe"
+ * not "uep".
+ */
+ usbhs_for_each_pipe_with_dcp(pipe, priv, i) {
+ if (!(irq_state->brdysts & (1 << i)))
+ continue;
+
+ uep = usbhsg_pipe_to_uep(pipe);
+ ret = usbhsg_queue_handle(uep);
+ if (ret < 0)
+ dev_err(dev, "receive error %d : %d\n", i, ret);
+ }
+
+ return 0;
+}
+
+/*
+ *
+ * usb_dcp_ops
+ *
+ */
+static int usbhsg_dcp_enable(struct usbhsg_uep *uep)
+{
+ struct usbhsg_gpriv *gpriv = usbhsg_uep_to_gpriv(uep);
+ struct usbhs_priv *priv = usbhsg_gpriv_to_priv(gpriv);
+ struct usbhs_pipe *pipe;
+
+ /*
+ ********* assume under spin lock *********
+ */
+
+ pipe = usbhs_dcp_malloc(priv);
+ if (!pipe)
+ return -EIO;
+
+ uep->pipe = pipe;
+ uep->pipe->mod_private = uep;
+ INIT_LIST_HEAD(&uep->list);
+
+ return 0;
+}
+
+#define usbhsg_dcp_disable usbhsg_pipe_disable
+static int usbhsg_pipe_disable(struct usbhsg_uep *uep)
+{
+ struct usbhs_pipe *pipe = usbhsg_uep_to_pipe(uep);
+ struct usbhsg_request *ureq;
+ int disable = 0;
+
+ /*
+ ********* assume under spin lock *********
+ */
+
+ usbhs_fifo_disable(pipe);
+
+ /*
+ * disable pipe irq
+ */
+ usbhsg_irq_empty_ctrl(uep, disable);
+ usbhsg_irq_ready_ctrl(uep, disable);
+
+ while (1) {
+ ureq = usbhsg_queue_get(uep);
+ if (!ureq)
+ break;
+
+ usbhsg_queue_pop(uep, ureq, -ECONNRESET);
+ }
+
+ return 0;
+}
+
+static void usbhsg_uep_init(struct usbhsg_gpriv *gpriv)
+{
+ int i;
+ struct usbhsg_uep *uep;
+
+ usbhsg_for_each_uep_with_dcp(uep, gpriv, i)
+ uep->pipe = NULL;
+}
+
+/*
+ *
+ * usb_ep_ops
+ *
+ */
+static int usbhsg_ep_enable(struct usb_ep *ep,
+ const struct usb_endpoint_descriptor *desc)
+{
+ struct usbhsg_uep *uep = usbhsg_ep_to_uep(ep);
+ struct usbhsg_gpriv *gpriv = usbhsg_uep_to_gpriv(uep);
+ struct usbhs_priv *priv = usbhsg_gpriv_to_priv(gpriv);
+ struct usbhs_pipe *pipe;
+ spinlock_t *lock;
+ unsigned long flags;
+ int ret = -EIO;
+
+ /*
+ * if it already have pipe,
+ * nothing to do
+ */
+ if (uep->pipe)
+ return 0;
+
+ /******************** spin lock ********************/
+ lock = usbhsg_trylock(gpriv, &flags);
+
+ pipe = usbhs_pipe_malloc(priv, desc);
+ if (pipe) {
+ uep->pipe = pipe;
+ pipe->mod_private = uep;
+ INIT_LIST_HEAD(&uep->list);
+
+ if (usb_endpoint_dir_in(desc))
+ uep->handler = &usbhsg_handler_send_packet;
+ else
+ uep->handler = &usbhsg_handler_recv_packet;
+
+ ret = 0;
+ }
+
+ usbhsg_unlock(lock, &flags);
+ /******************** spin unlock ******************/
+
+ return ret;
+}
+
+static int usbhsg_ep_disable(struct usb_ep *ep)
+{
+ struct usbhsg_uep *uep = usbhsg_ep_to_uep(ep);
+ struct usbhsg_gpriv *gpriv = usbhsg_uep_to_gpriv(uep);
+ spinlock_t *lock;
+ unsigned long flags;
+ int ret;
+
+ /******************** spin lock ********************/
+ lock = usbhsg_trylock(gpriv, &flags);
+
+ ret = usbhsg_pipe_disable(uep);
+
+ usbhsg_unlock(lock, &flags);
+ /******************** spin unlock ******************/
+
+ return ret;
+}
+
+static struct usb_request *usbhsg_ep_alloc_request(struct usb_ep *ep,
+ gfp_t gfp_flags)
+{
+ struct usbhsg_request *ureq;
+
+ ureq = kzalloc(sizeof *ureq, gfp_flags);
+ if (!ureq)
+ return NULL;
+
+ INIT_LIST_HEAD(&ureq->node);
+ return &ureq->req;
+}
+
+static void usbhsg_ep_free_request(struct usb_ep *ep,
+ struct usb_request *req)
+{
+ struct usbhsg_request *ureq = usbhsg_req_to_ureq(req);
+
+ WARN_ON(!list_empty(&ureq->node));
+ kfree(ureq);
+}
+
+static int usbhsg_ep_queue(struct usb_ep *ep, struct usb_request *req,
+ gfp_t gfp_flags)
+{
+ struct usbhsg_uep *uep = usbhsg_ep_to_uep(ep);
+ struct usbhsg_gpriv *gpriv = usbhsg_uep_to_gpriv(uep);
+ struct usbhsg_request *ureq = usbhsg_req_to_ureq(req);
+ struct usbhs_pipe *pipe = usbhsg_uep_to_pipe(uep);
+ spinlock_t *lock;
+ unsigned long flags;
+ int ret = 0;
+
+ /*
+ * CAUTION [*endpoint queue*]
+ *
+ * This function will be called from usb_request :: complete
+ * or usb driver timing.
+ * If this function is called from usb_request :: complete,
+ * it is already under spinlock on this driver.
+ * but it is called frm usb driver, this function should call spinlock.
+ *
+ * This function is using usbshg_trylock to solve this issue.
+ * if "is_locked" is 1, this mean this function lock it.
+ * but if it is 0, this mean it is already under spin lock.
+ * see also
+ * CAUTION [*queue handler*]
+ * CAUTION [*request complete*]
+ */
+
+ /******************** spin lock ********************/
+ lock = usbhsg_trylock(gpriv, &flags);
+
+ /* param check */
+ if (usbhsg_is_not_connected(gpriv) ||
+ unlikely(!gpriv->driver) ||
+ unlikely(!pipe))
+ ret = -ESHUTDOWN;
+ else
+ usbhsg_queue_push(uep, ureq);
+
+ usbhsg_unlock(lock, &flags);
+ /******************** spin unlock ******************/
+
+ usbhsg_queue_prepare(uep);
+
+ return ret;
+}
+
+static int usbhsg_ep_dequeue(struct usb_ep *ep, struct usb_request *req)
+{
+ struct usbhsg_uep *uep = usbhsg_ep_to_uep(ep);
+ struct usbhsg_request *ureq = usbhsg_req_to_ureq(req);
+ struct usbhsg_gpriv *gpriv = usbhsg_uep_to_gpriv(uep);
+ spinlock_t *lock;
+ unsigned long flags;
+
+ /*
+ * see
+ * CAUTION [*queue handler*]
+ * CAUTION [*endpoint queue*]
+ * CAUTION [*request complete*]
+ */
+
+ /******************** spin lock ********************/
+ lock = usbhsg_trylock(gpriv, &flags);
+
+ usbhsg_queue_pop(uep, ureq, -ECONNRESET);
+
+ usbhsg_unlock(lock, &flags);
+ /******************** spin unlock ******************/
+
+ return 0;
+}
+
+static int __usbhsg_ep_set_halt_wedge(struct usb_ep *ep, int halt, int wedge)
+{
+ struct usbhsg_uep *uep = usbhsg_ep_to_uep(ep);
+ struct usbhs_pipe *pipe = usbhsg_uep_to_pipe(uep);
+ struct usbhsg_gpriv *gpriv = usbhsg_uep_to_gpriv(uep);
+ struct device *dev = usbhsg_gpriv_to_dev(gpriv);
+ spinlock_t *lock;
+ unsigned long flags;
+ int ret = -EAGAIN;
+
+ /*
+ * see
+ * CAUTION [*queue handler*]
+ * CAUTION [*endpoint queue*]
+ * CAUTION [*request complete*]
+ */
+
+ /******************** spin lock ********************/
+ lock = usbhsg_trylock(gpriv, &flags);
+ if (!usbhsg_queue_get(uep)) {
+
+ dev_dbg(dev, "set halt %d (pipe %d)\n",
+ halt, usbhs_pipe_number(pipe));
+
+ if (halt)
+ usbhs_fifo_stall(pipe);
+ else
+ usbhs_fifo_disable(pipe);
+
+ if (halt && wedge)
+ usbhsg_status_set(gpriv, USBHSG_STATUS_WEDGE);
+ else
+ usbhsg_status_clr(gpriv, USBHSG_STATUS_WEDGE);
+
+ ret = 0;
+ }
+
+ usbhsg_unlock(lock, &flags);
+ /******************** spin unlock ******************/
+
+ return ret;
+}
+
+static int usbhsg_ep_set_halt(struct usb_ep *ep, int value)
+{
+ return __usbhsg_ep_set_halt_wedge(ep, value, 0);
+}
+
+static int usbhsg_ep_set_wedge(struct usb_ep *ep)
+{
+ return __usbhsg_ep_set_halt_wedge(ep, 1, 1);
+}
+
+static struct usb_ep_ops usbhsg_ep_ops = {
+ .enable = usbhsg_ep_enable,
+ .disable = usbhsg_ep_disable,
+
+ .alloc_request = usbhsg_ep_alloc_request,
+ .free_request = usbhsg_ep_free_request,
+
+ .queue = usbhsg_ep_queue,
+ .dequeue = usbhsg_ep_dequeue,
+
+ .set_halt = usbhsg_ep_set_halt,
+ .set_wedge = usbhsg_ep_set_wedge,
+};
+
+/*
+ * usb module start/end
+ */
+static int usbhsg_try_start(struct usbhs_priv *priv, u32 status)
+{
+ struct usbhsg_gpriv *gpriv = usbhsg_priv_to_gpriv(priv);
+ struct usbhsg_uep *dcp = usbhsg_gpriv_to_dcp(gpriv);
+ struct usbhs_mod *mod = usbhs_mod_get_current(priv);
+ struct device *dev = usbhs_priv_to_dev(priv);
+ spinlock_t *lock;
+ unsigned long flags;
+
+ /******************** spin lock ********************/
+ lock = usbhsg_trylock(gpriv, &flags);
+
+ /*
+ * enable interrupt and systems if ready
+ */
+ usbhsg_status_set(gpriv, status);
+ if (!(usbhsg_status_has(gpriv, USBHSG_STATUS_STARTED) &&
+ usbhsg_status_has(gpriv, USBHSG_STATUS_REGISTERD)))
+ goto usbhsg_try_start_unlock;
+
+ dev_dbg(dev, "start gadget\n");
+
+ /*
+ * pipe initialize and enable DCP
+ */
+ usbhs_pipe_init(priv);
+ usbhsg_uep_init(gpriv);
+ usbhsg_dcp_enable(dcp);
+
+ /*
+ * system config enble
+ * - HI speed
+ * - function
+ * - usb module
+ */
+ usbhs_sys_hispeed_ctrl(priv, 1);
+ usbhs_sys_function_ctrl(priv, 1);
+ usbhs_sys_usb_ctrl(priv, 1);
+
+ /*
+ * enable irq callback
+ */
+ mod->irq_dev_state = usbhsg_irq_dev_state;
+ mod->irq_ctrl_stage = usbhsg_irq_ctrl_stage;
+ mod->irq_empty = usbhsg_irq_empty;
+ mod->irq_ready = usbhsg_irq_ready;
+ mod->irq_bempsts = 0;
+ mod->irq_brdysts = 0;
+ usbhs_irq_callback_update(priv, mod);
+
+usbhsg_try_start_unlock:
+ usbhsg_unlock(lock, &flags);
+ /******************** spin unlock ********************/
+
+ return 0;
+}
+
+static int usbhsg_try_stop(struct usbhs_priv *priv, u32 status)
+{
+ struct usbhsg_gpriv *gpriv = usbhsg_priv_to_gpriv(priv);
+ struct usbhs_mod *mod = usbhs_mod_get_current(priv);
+ struct usbhsg_uep *dcp = usbhsg_gpriv_to_dcp(gpriv);
+ struct device *dev = usbhs_priv_to_dev(priv);
+ spinlock_t *lock;
+ unsigned long flags;
+
+ /******************** spin lock ********************/
+ lock = usbhsg_trylock(gpriv, &flags);
+
+ /*
+ * disable interrupt and systems if 1st try
+ */
+ usbhsg_status_clr(gpriv, status);
+ if (!usbhsg_status_has(gpriv, USBHSG_STATUS_STARTED) &&
+ !usbhsg_status_has(gpriv, USBHSG_STATUS_REGISTERD))
+ goto usbhsg_try_stop_unlock;
+
+ /* disable all irq */
+ mod->irq_dev_state = NULL;
+ mod->irq_ctrl_stage = NULL;
+ mod->irq_empty = NULL;
+ mod->irq_ready = NULL;
+ mod->irq_bempsts = 0;
+ mod->irq_brdysts = 0;
+ usbhs_irq_callback_update(priv, mod);
+
+ usbhsg_dcp_disable(dcp);
+
+ gpriv->gadget.speed = USB_SPEED_UNKNOWN;
+
+ /* disable sys */
+ usbhs_sys_hispeed_ctrl(priv, 0);
+ usbhs_sys_function_ctrl(priv, 0);
+ usbhs_sys_usb_ctrl(priv, 0);
+
+ usbhsg_unlock(lock, &flags);
+ /******************** spin unlock ********************/
+
+ if (gpriv->driver &&
+ gpriv->driver->disconnect)
+ gpriv->driver->disconnect(&gpriv->gadget);
+
+ dev_dbg(dev, "stop gadget\n");
+
+ return 0;
+
+usbhsg_try_stop_unlock:
+ usbhsg_unlock(lock, &flags);
+
+ return 0;
+}
+
+/*
+ *
+ * linux usb function
+ *
+ */
+struct usbhsg_gpriv *the_controller;
+int usb_gadget_probe_driver(struct usb_gadget_driver *driver,
+ int (*bind)(struct usb_gadget *))
+{
+ struct usbhsg_gpriv *gpriv = the_controller;
+ struct usbhs_priv *priv;
+ struct device *dev;
+ int ret;
+
+ if (!bind ||
+ !driver ||
+ !driver->setup ||
+ driver->speed != USB_SPEED_HIGH)
+ return -EINVAL;
+ if (!gpriv)
+ return -ENODEV;
+ if (gpriv->driver)
+ return -EBUSY;
+
+ dev = usbhsg_gpriv_to_dev(gpriv);
+ priv = usbhsg_gpriv_to_priv(gpriv);
+
+ /* first hook up the driver ... */
+ gpriv->driver = driver;
+ gpriv->gadget.dev.driver = &driver->driver;
+
+ ret = device_add(&gpriv->gadget.dev);
+ if (ret) {
+ dev_err(dev, "device_add error %d\n", ret);
+ goto add_fail;
+ }
+
+ ret = bind(&gpriv->gadget);
+ if (ret) {
+ dev_err(dev, "bind to driver %s error %d\n",
+ driver->driver.name, ret);
+ goto bind_fail;
+ }
+
+ dev_dbg(dev, "bind %s\n", driver->driver.name);
+
+ return usbhsg_try_start(priv, USBHSG_STATUS_REGISTERD);
+
+bind_fail:
+ device_del(&gpriv->gadget.dev);
+add_fail:
+ gpriv->driver = NULL;
+ gpriv->gadget.dev.driver = NULL;
+
+ return ret;
+}
+EXPORT_SYMBOL(usb_gadget_probe_driver);
+
+int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
+{
+ struct usbhsg_gpriv *gpriv = the_controller;
+ struct usbhs_priv *priv;
+ struct device *dev = usbhsg_gpriv_to_dev(gpriv);
+
+ if (!gpriv)
+ return -ENODEV;
+
+ if (!driver ||
+ !driver->unbind ||
+ driver != gpriv->driver)
+ return -EINVAL;
+
+ dev = usbhsg_gpriv_to_dev(gpriv);
+ priv = usbhsg_gpriv_to_priv(gpriv);
+
+ usbhsg_try_stop(priv, USBHSG_STATUS_REGISTERD);
+ device_del(&gpriv->gadget.dev);
+ gpriv->driver = NULL;
+
+ if (driver->disconnect)
+ driver->disconnect(&gpriv->gadget);
+
+ driver->unbind(&gpriv->gadget);
+ dev_dbg(dev, "unbind %s\n", driver->driver.name);
+
+ return 0;
+}
+EXPORT_SYMBOL(usb_gadget_unregister_driver);
+
+/*
+ * usb gadget ops
+ */
+static int usbhsg_get_frame(struct usb_gadget *gadget)
+{
+ struct usbhsg_gpriv *gpriv = usbhsg_gadget_to_gpriv(gadget);
+ struct usbhs_priv *priv = usbhsg_gpriv_to_priv(gpriv);
+
+ return usbhs_frame_get_num(priv);
+}
+
+static struct usb_gadget_ops usbhsg_gadget_ops = {
+ .get_frame = usbhsg_get_frame,
+};
+
+static int usbhsg_start(struct usbhs_priv *priv)
+{
+ return usbhsg_try_start(priv, USBHSG_STATUS_STARTED);
+}
+
+static int usbhsg_stop(struct usbhs_priv *priv)
+{
+ return usbhsg_try_stop(priv, USBHSG_STATUS_STARTED);
+}
+
+int __devinit usbhs_mod_gadget_probe(struct usbhs_priv *priv)
+{
+ struct usbhsg_gpriv *gpriv;
+ struct usbhsg_uep *uep;
+ struct device *dev = usbhs_priv_to_dev(priv);
+ int pipe_size = usbhs_get_dparam(priv, pipe_size);
+ int i;
+
+ gpriv = kzalloc(sizeof(struct usbhsg_gpriv), GFP_KERNEL);
+ if (!gpriv) {
+ dev_err(dev, "Could not allocate gadget priv\n");
+ return -ENOMEM;
+ }
+
+ uep = kzalloc(sizeof(struct usbhsg_uep) * pipe_size, GFP_KERNEL);
+ if (!uep) {
+ dev_err(dev, "Could not allocate ep\n");
+ goto usbhs_mod_gadget_probe_err_gpriv;
+ }
+
+ /*
+ * CAUTION
+ *
+ * There is no guarantee that it is possible to access usb module here.
+ * Don't accesses to it.
+ * The accesse will be enable after "usbhsg_start"
+ */
+
+ /*
+ * register itself
+ */
+ usbhs_mod_register(priv, &gpriv->mod, USBHS_GADGET);
+
+ /* init gpriv */
+ gpriv->mod.name = "gadget";
+ gpriv->mod.start = usbhsg_start;
+ gpriv->mod.stop = usbhsg_stop;
+ gpriv->uep = uep;
+ gpriv->uep_size = pipe_size;
+ usbhsg_status_init(gpriv);
+
+ /*
+ * init gadget
+ */
+ device_initialize(&gpriv->gadget.dev);
+ dev_set_name(&gpriv->gadget.dev, "gadget");
+ gpriv->gadget.dev.parent = dev;
+ gpriv->gadget.name = "renesas_usbhs_udc";
+ gpriv->gadget.ops = &usbhsg_gadget_ops;
+ gpriv->gadget.is_dualspeed = 1;
+
+ INIT_LIST_HEAD(&gpriv->gadget.ep_list);
+
+ /*
+ * init usb_ep
+ */
+ usbhsg_for_each_uep_with_dcp(uep, gpriv, i) {
+ uep->gpriv = gpriv;
+ snprintf(uep->ep_name, EP_NAME_SIZE, "ep%d", i);
+
+ uep->ep.name = uep->ep_name;
+ uep->ep.ops = &usbhsg_ep_ops;
+ INIT_LIST_HEAD(&uep->ep.ep_list);
+ INIT_LIST_HEAD(&uep->list);
+
+ /* init DCP */
+ if (usbhsg_is_dcp(uep)) {
+ gpriv->gadget.ep0 = &uep->ep;
+ uep->ep.maxpacket = 64;
+ }
+ /* init normal pipe */
+ else {
+ uep->ep.maxpacket = 512;
+ list_add_tail(&uep->ep.ep_list, &gpriv->gadget.ep_list);
+ }
+ }
+
+ the_controller = gpriv;
+
+ dev_info(dev, "gadget probed\n");
+
+ return 0;
+
+usbhs_mod_gadget_probe_err_gpriv:
+ kfree(gpriv);
+
+ return -ENOMEM;
+}
+
+void __devexit usbhs_mod_gadget_remove(struct usbhs_priv *priv)
+{
+ struct usbhsg_gpriv *gpriv = usbhsg_priv_to_gpriv(priv);
+
+ kfree(gpriv);
+}
diff --git a/drivers/usb/renesas_usbhs/pipe.c b/drivers/usb/renesas_usbhs/pipe.c
new file mode 100644
index 0000000..bc4521c
--- /dev/null
+++ b/drivers/usb/renesas_usbhs/pipe.c
@@ -0,0 +1,874 @@
+/*
+ * Renesas USB driver
+ *
+ * Copyright (C) 2011 Renesas Solutions Corp.
+ * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ */
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include "./common.h"
+#include "./pipe.h"
+
+/*
+ * macros
+ */
+#define usbhsp_priv_to_pipeinfo(pr) (&(pr)->pipe_info)
+#define usbhsp_pipe_to_priv(p) ((p)->priv)
+
+#define usbhsp_addr_offset(p) ((usbhs_pipe_number(p) - 1) * 2)
+
+#define usbhsp_is_dcp(p) ((p)->priv->pipe_info.pipe == (p))
+
+#define usbhsp_flags_set(p, f) ((p)->flags |= USBHS_PIPE_FLAGS_##f)
+#define usbhsp_flags_clr(p, f) ((p)->flags &= ~USBHS_PIPE_FLAGS_##f)
+#define usbhsp_flags_has(p, f) ((p)->flags & USBHS_PIPE_FLAGS_##f)
+#define usbhsp_flags_init(p) do {(p)->flags = 0; } while (0)
+
+#define usbhsp_type(p) ((p)->pipe_type)
+#define usbhsp_type_is(p, t) ((p)->pipe_type == t)
+
+/*
+ * for debug
+ */
+static char *usbhsp_pipe_name[] = {
+ [USB_ENDPOINT_XFER_CONTROL] = "DCP",
+ [USB_ENDPOINT_XFER_BULK] = "BULK",
+ [USB_ENDPOINT_XFER_INT] = "INT",
+ [USB_ENDPOINT_XFER_ISOC] = "ISO",
+};
+
+/*
+ * usb request functions
+ */
+void usbhs_usbreq_get_val(struct usbhs_priv *priv, struct usb_ctrlrequest *req)
+{
+ u16 val;
+
+ val = usbhs_read(priv, USBREQ);
+ req->bRequest = (val >> 8) & 0xFF;
+ req->bRequestType = (val >> 0) & 0xFF;
+
+ req->wValue = usbhs_read(priv, USBVAL);
+ req->wIndex = usbhs_read(priv, USBINDX);
+ req->wLength = usbhs_read(priv, USBLENG);
+}
+
+void usbhs_usbreq_set_val(struct usbhs_priv *priv, struct usb_ctrlrequest *req)
+{
+ usbhs_write(priv, USBREQ, (req->bRequest << 8) | req->bRequestType);
+ usbhs_write(priv, USBVAL, req->wValue);
+ usbhs_write(priv, USBINDX, req->wIndex);
+ usbhs_write(priv, USBLENG, req->wLength);
+}
+
+/*
+ * DCPCTR/PIPEnCTR functions
+ */
+static void usbhsp_pipectrl_set(struct usbhs_pipe *pipe, u16 mask, u16 val)
+{
+ struct usbhs_priv *priv = usbhsp_pipe_to_priv(pipe);
+ int offset = usbhsp_addr_offset(pipe);
+
+ if (usbhsp_is_dcp(pipe))
+ usbhs_bset(priv, DCPCTR, mask, val);
+ else
+ usbhs_bset(priv, PIPEnCTR + offset, mask, val);
+}
+
+static u16 usbhsp_pipectrl_get(struct usbhs_pipe *pipe)
+{
+ struct usbhs_priv *priv = usbhsp_pipe_to_priv(pipe);
+ int offset = usbhsp_addr_offset(pipe);
+
+ if (usbhsp_is_dcp(pipe))
+ return usbhs_read(priv, DCPCTR);
+ else
+ return usbhs_read(priv, PIPEnCTR + offset);
+}
+
+/*
+ * DCP/PIPE functions
+ */
+static void __usbhsp_pipe_xxx_set(struct usbhs_pipe *pipe,
+ u16 dcp_reg, u16 pipe_reg,
+ u16 mask, u16 val)
+{
+ struct usbhs_priv *priv = usbhsp_pipe_to_priv(pipe);
+
+ if (usbhsp_is_dcp(pipe))
+ usbhs_bset(priv, dcp_reg, mask, val);
+ else
+ usbhs_bset(priv, pipe_reg, mask, val);
+}
+
+static u16 __usbhsp_pipe_xxx_get(struct usbhs_pipe *pipe,
+ u16 dcp_reg, u16 pipe_reg)
+{
+ struct usbhs_priv *priv = usbhsp_pipe_to_priv(pipe);
+
+ if (usbhsp_is_dcp(pipe))
+ return usbhs_read(priv, dcp_reg);
+ else
+ return usbhs_read(priv, pipe_reg);
+}
+
+/*
+ * DCPCFG/PIPECFG functions
+ */
+static void usbhsp_pipe_cfg_set(struct usbhs_pipe *pipe, u16 mask, u16 val)
+{
+ __usbhsp_pipe_xxx_set(pipe, DCPCFG, PIPECFG, mask, val);
+}
+
+/*
+ * PIPEBUF
+ */
+static void usbhsp_pipe_buf_set(struct usbhs_pipe *pipe, u16 mask, u16 val)
+{
+ if (usbhsp_is_dcp(pipe))
+ return;
+
+ __usbhsp_pipe_xxx_set(pipe, 0, PIPEBUF, mask, val);
+}
+
+/*
+ * DCPMAXP/PIPEMAXP
+ */
+static void usbhsp_pipe_maxp_set(struct usbhs_pipe *pipe, u16 mask, u16 val)
+{
+ __usbhsp_pipe_xxx_set(pipe, DCPMAXP, PIPEMAXP, mask, val);
+}
+
+static u16 usbhsp_pipe_maxp_get(struct usbhs_pipe *pipe)
+{
+ return __usbhsp_pipe_xxx_get(pipe, DCPMAXP, PIPEMAXP);
+}
+
+/*
+ * pipe control functions
+ */
+static void usbhsp_pipe_select(struct usbhs_pipe *pipe)
+{
+ struct usbhs_priv *priv = usbhsp_pipe_to_priv(pipe);
+
+ /*
+ * On pipe, this is necessary before
+ * accesses to below registers.
+ *
+ * PIPESEL : usbhsp_pipe_select
+ * PIPECFG : usbhsp_pipe_cfg_xxx
+ * PIPEBUF : usbhsp_pipe_buf_xxx
+ * PIPEMAXP : usbhsp_pipe_maxp_xxx
+ * PIPEPERI
+ */
+
+ /*
+ * if pipe is dcp, no pipe is selected.
+ * it is no problem, because dcp have its register
+ */
+ usbhs_write(priv, PIPESEL, 0xF & usbhs_pipe_number(pipe));
+}
+
+static int usbhsp_pipe_barrier(struct usbhs_pipe *pipe)
+{
+ struct usbhs_priv *priv = usbhsp_pipe_to_priv(pipe);
+ int timeout = 1024;
+ u16 val;
+
+ /*
+ * make sure....
+ *
+ * Modify these bits when CSSTS = 0, PID = NAK, and no pipe number is
+ * specified by the CURPIPE bits.
+ * When changing the setting of this bit after changing
+ * the PID bits for the selected pipe from BUF to NAK,
+ * check that CSSTS = 0 and PBUSY = 0.
+ */
+
+ /*
+ * CURPIPE bit = 0
+ *
+ * see also
+ * "Operation"
+ * - "Pipe Control"
+ * - "Pipe Control Registers Switching Procedure"
+ */
+ usbhs_write(priv, CFIFOSEL, 0);
+ usbhs_fifo_disable(pipe);
+
+ do {
+ val = usbhsp_pipectrl_get(pipe);
+ val &= CSSTS | PID_MASK;
+ if (!val)
+ return 0;
+
+ udelay(10);
+
+ } while (timeout--);
+
+ return -EBUSY;
+}
+
+static int usbhsp_pipe_is_accessible(struct usbhs_pipe *pipe)
+{
+ u16 val;
+
+ val = usbhsp_pipectrl_get(pipe);
+ if (val & BSTS)
+ return 0;
+
+ return -EBUSY;
+}
+
+/*
+ * PID ctrl
+ */
+static void __usbhsp_pid_try_nak_if_stall(struct usbhs_pipe *pipe)
+{
+ u16 pid = usbhsp_pipectrl_get(pipe);
+
+ pid &= PID_MASK;
+
+ /*
+ * see
+ * "Pipe n Control Register" - "PID"
+ */
+ switch (pid) {
+ case PID_STALL11:
+ usbhsp_pipectrl_set(pipe, PID_MASK, PID_STALL10);
+ /* fall-through */
+ case PID_STALL10:
+ usbhsp_pipectrl_set(pipe, PID_MASK, PID_NAK);
+ }
+}
+
+void usbhs_fifo_disable(struct usbhs_pipe *pipe)
+{
+ int timeout = 1024;
+ u16 val;
+
+ /* see "Pipe n Control Register" - "PID" */
+ __usbhsp_pid_try_nak_if_stall(pipe);
+
+ usbhsp_pipectrl_set(pipe, PID_MASK, PID_NAK);
+
+ do {
+ val = usbhsp_pipectrl_get(pipe);
+ val &= PBUSY;
+ if (!val)
+ break;
+
+ udelay(10);
+ } while (timeout--);
+}
+
+void usbhs_fifo_enable(struct usbhs_pipe *pipe)
+{
+ /* see "Pipe n Control Register" - "PID" */
+ __usbhsp_pid_try_nak_if_stall(pipe);
+
+ usbhsp_pipectrl_set(pipe, PID_MASK, PID_BUF);
+}
+
+void usbhs_fifo_stall(struct usbhs_pipe *pipe)
+{
+ u16 pid = usbhsp_pipectrl_get(pipe);
+
+ pid &= PID_MASK;
+
+ /*
+ * see
+ * "Pipe n Control Register" - "PID"
+ */
+ switch (pid) {
+ case PID_NAK:
+ usbhsp_pipectrl_set(pipe, PID_MASK, PID_STALL10);
+ break;
+ case PID_BUF:
+ usbhsp_pipectrl_set(pipe, PID_MASK, PID_STALL11);
+ break;
+ }
+}
+
+/*
+ * CFIFO ctrl
+ */
+void usbhs_fifo_send_terminator(struct usbhs_pipe *pipe)
+{
+ struct usbhs_priv *priv = usbhsp_pipe_to_priv(pipe);
+
+ usbhs_bset(priv, CFIFOCTR, BVAL, BVAL);
+}
+
+static void usbhsp_fifo_clear(struct usbhs_pipe *pipe)
+{
+ struct usbhs_priv *priv = usbhsp_pipe_to_priv(pipe);
+
+ usbhs_write(priv, CFIFOCTR, BCLR);
+}
+
+static int usbhsp_fifo_barrier(struct usbhs_priv *priv)
+{
+ int timeout = 1024;
+
+ do {
+ /* The FIFO port is accessible */
+ if (usbhs_read(priv, CFIFOCTR) & FRDY)
+ return 0;
+
+ udelay(10);
+ } while (timeout--);
+
+ return -EBUSY;
+}
+
+static int usbhsp_fifo_rcv_len(struct usbhs_priv *priv)
+{
+ return usbhs_read(priv, CFIFOCTR) & DTLN_MASK;
+}
+
+static int usbhsp_fifo_select(struct usbhs_pipe *pipe, int write)
+{
+ struct usbhs_priv *priv = usbhsp_pipe_to_priv(pipe);
+ struct device *dev = usbhs_priv_to_dev(priv);
+ int timeout = 1024;
+ u16 mask = ((1 << 5) | 0xF); /* mask of ISEL | CURPIPE */
+ u16 base = usbhs_pipe_number(pipe); /* CURPIPE */
+
+ if (usbhsp_is_dcp(pipe))
+ base |= (1 == write) << 5; /* ISEL */
+
+ /* "base" will be used below */
+ usbhs_write(priv, CFIFOSEL, base | MBW_32);
+
+ /* check ISEL and CURPIPE value */
+ while (timeout--) {
+ if (base == (mask & usbhs_read(priv, CFIFOSEL)))
+ return 0;
+ udelay(10);
+ }
+
+ dev_err(dev, "fifo select error\n");
+
+ return -EIO;
+}
+
+int usbhs_fifo_prepare_write(struct usbhs_pipe *pipe)
+{
+ return usbhsp_fifo_select(pipe, 1);
+}
+
+int usbhs_fifo_write(struct usbhs_pipe *pipe, u8 *buf, int len)
+{
+ struct usbhs_priv *priv = usbhsp_pipe_to_priv(pipe);
+ void __iomem *addr = priv->base + CFIFO;
+ int maxp = usbhs_pipe_get_maxpacket(pipe);
+ int total_len;
+ int i, ret;
+
+ ret = usbhsp_pipe_is_accessible(pipe);
+ if (ret < 0)
+ return ret;
+
+ ret = usbhsp_fifo_select(pipe, 1);
+ if (ret < 0)
+ return ret;
+
+ ret = usbhsp_fifo_barrier(priv);
+ if (ret < 0)
+ return ret;
+
+ len = min(len, maxp);
+ total_len = len;
+
+ /*
+ * FIXME
+ *
+ * 32-bit access only
+ */
+ if (len >= 4 &&
+ !((unsigned long)buf & 0x03)) {
+ iowrite32_rep(addr, buf, len / 4);
+ len %= 4;
+ buf += total_len - len;
+ }
+
+ /* the rest operation */
+ for (i = 0; i < len; i++)
+ iowrite8(buf[i], addr + (0x03 - (i & 0x03)));
+
+ if (total_len < maxp)
+ usbhs_fifo_send_terminator(pipe);
+
+ return total_len;
+}
+
+int usbhs_fifo_prepare_read(struct usbhs_pipe *pipe)
+{
+ int ret;
+
+ /*
+ * select pipe and enable it to prepare packet receive
+ */
+ ret = usbhsp_fifo_select(pipe, 0);
+ if (ret < 0)
+ return ret;
+
+ usbhs_fifo_enable(pipe);
+
+ return ret;
+}
+
+int usbhs_fifo_read(struct usbhs_pipe *pipe, u8 *buf, int len)
+{
+ struct usbhs_priv *priv = usbhsp_pipe_to_priv(pipe);
+ void __iomem *addr = priv->base + CFIFO;
+ int rcv_len;
+ int i, ret;
+ int total_len;
+ u32 data = 0;
+
+ ret = usbhsp_fifo_select(pipe, 0);
+ if (ret < 0)
+ return ret;
+
+ ret = usbhsp_fifo_barrier(priv);
+ if (ret < 0)
+ return ret;
+
+ rcv_len = usbhsp_fifo_rcv_len(priv);
+
+ /*
+ * Buffer clear if Zero-Length packet
+ *
+ * see
+ * "Operation" - "FIFO Buffer Memory" - "FIFO Port Function"
+ */
+ if (0 == rcv_len) {
+ usbhsp_fifo_clear(pipe);
+ return 0;
+ }
+
+ len = min(rcv_len, len);
+ total_len = len;
+
+ /*
+ * FIXME
+ *
+ * 32-bit access only
+ */
+ if (len >= 4 &&
+ !((unsigned long)buf & 0x03)) {
+ ioread32_rep(addr, buf, len / 4);
+ len %= 4;
+ buf += rcv_len - len;
+ }
+
+ /* the rest operation */
+ for (i = 0; i < len; i++) {
+ if (!(i & 0x03))
+ data = ioread32(addr);
+
+ buf[i] = (data >> ((i & 0x03) * 8)) & 0xff;
+ }
+
+ return total_len;
+}
+
+/*
+ * pipe setup
+ */
+static int usbhsp_possible_double_buffer(struct usbhs_pipe *pipe)
+{
+ /*
+ * only ISO / BULK pipe can use double buffer
+ */
+ if (usbhsp_type_is(pipe, USB_ENDPOINT_XFER_BULK) ||
+ usbhsp_type_is(pipe, USB_ENDPOINT_XFER_ISOC))
+ return 1;
+
+ return 0;
+}
+
+static u16 usbhsp_setup_pipecfg(struct usbhs_pipe *pipe,
+ const struct usb_endpoint_descriptor *desc,
+ int is_host)
+{
+ u16 type = 0;
+ u16 bfre = 0;
+ u16 dblb = 0;
+ u16 cntmd = 0;
+ u16 dir = 0;
+ u16 epnum = 0;
+ u16 shtnak = 0;
+ u16 type_array[] = {
+ [USB_ENDPOINT_XFER_BULK] = TYPE_BULK,
+ [USB_ENDPOINT_XFER_INT] = TYPE_INT,
+ [USB_ENDPOINT_XFER_ISOC] = TYPE_ISO,
+ };
+ int is_double = usbhsp_possible_double_buffer(pipe);
+
+ if (usbhsp_is_dcp(pipe))
+ return -EINVAL;
+
+ /*
+ * PIPECFG
+ *
+ * see
+ * - "Register Descriptions" - "PIPECFG" register
+ * - "Features" - "Pipe configuration"
+ * - "Operation" - "Pipe Control"
+ */
+
+ /* TYPE */
+ type = type_array[usbhsp_type(pipe)];
+
+ /* BFRE */
+ if (usbhsp_type_is(pipe, USB_ENDPOINT_XFER_ISOC) ||
+ usbhsp_type_is(pipe, USB_ENDPOINT_XFER_BULK))
+ bfre = 0; /* FIXME */
+
+ /* DBLB */
+ if (usbhsp_type_is(pipe, USB_ENDPOINT_XFER_ISOC) ||
+ usbhsp_type_is(pipe, USB_ENDPOINT_XFER_BULK))
+ dblb = (is_double) ? DBLB : 0;
+
+ /* CNTMD */
+ if (usbhsp_type_is(pipe, USB_ENDPOINT_XFER_BULK))
+ cntmd = 0; /* FIXME */
+
+ /* DIR */
+ if (usb_endpoint_dir_in(desc))
+ usbhsp_flags_set(pipe, IS_DIR_IN);
+
+ if ((is_host && usb_endpoint_dir_out(desc)) ||
+ (!is_host && usb_endpoint_dir_in(desc)))
+ dir |= DIR_OUT;
+
+ /* SHTNAK */
+ if (usbhsp_type_is(pipe, USB_ENDPOINT_XFER_BULK) &&
+ !dir)
+ shtnak = SHTNAK;
+
+ /* EPNUM */
+ epnum = 0xF & usb_endpoint_num(desc);
+
+ return type |
+ bfre |
+ dblb |
+ cntmd |
+ dir |
+ shtnak |
+ epnum;
+}
+
+static u16 usbhsp_setup_pipemaxp(struct usbhs_pipe *pipe,
+ const struct usb_endpoint_descriptor *desc,
+ int is_host)
+{
+ /* host should set DEVSEL */
+
+ /* reutn MXPS */
+ return PIPE_MAXP_MASK & le16_to_cpu(desc->wMaxPacketSize);
+}
+
+static u16 usbhsp_setup_pipebuff(struct usbhs_pipe *pipe,
+ const struct usb_endpoint_descriptor *desc,
+ int is_host)
+{
+ struct usbhs_priv *priv = usbhsp_pipe_to_priv(pipe);
+ struct usbhs_pipe_info *info = usbhsp_priv_to_pipeinfo(priv);
+ struct device *dev = usbhs_priv_to_dev(priv);
+ int pipe_num = usbhs_pipe_number(pipe);
+ int is_double = usbhsp_possible_double_buffer(pipe);
+ u16 buff_size;
+ u16 bufnmb;
+ u16 bufnmb_cnt;
+
+ /*
+ * PIPEBUF
+ *
+ * see
+ * - "Register Descriptions" - "PIPEBUF" register
+ * - "Features" - "Pipe configuration"
+ * - "Operation" - "FIFO Buffer Memory"
+ * - "Operation" - "Pipe Control"
+ *
+ * ex) if pipe6 - pipe9 are USB_ENDPOINT_XFER_INT (SH7724)
+ *
+ * BUFNMB: PIPE
+ * 0: pipe0 (DCP 256byte)
+ * 1: -
+ * 2: -
+ * 3: -
+ * 4: pipe6 (INT 64byte)
+ * 5: pipe7 (INT 64byte)
+ * 6: pipe8 (INT 64byte)
+ * 7: pipe9 (INT 64byte)
+ * 8 - xx: free (for BULK, ISOC)
+ */
+
+ /*
+ * FIXME
+ *
+ * it doesn't have good buffer allocator
+ *
+ * DCP : 256 byte
+ * BULK: 512 byte
+ * INT : 64 byte
+ * ISOC: 512 byte
+ */
+ if (usbhsp_type_is(pipe, USB_ENDPOINT_XFER_CONTROL))
+ buff_size = 256;
+ else if (usbhsp_type_is(pipe, USB_ENDPOINT_XFER_INT))
+ buff_size = 64;
+ else
+ buff_size = 512;
+
+ /* change buff_size to register value */
+ bufnmb_cnt = (buff_size / 64) - 1;
+
+ /* BUFNMB has been reserved for INT pipe
+ * see above */
+ if (usbhsp_type_is(pipe, USB_ENDPOINT_XFER_INT)) {
+ bufnmb = pipe_num - 2;
+ } else {
+ bufnmb = info->bufnmb_last;
+ info->bufnmb_last += bufnmb_cnt + 1;
+
+ /*
+ * double buffer
+ */
+ if (is_double)
+ info->bufnmb_last += bufnmb_cnt + 1;
+ }
+
+ dev_dbg(dev, "pipe : %d : buff_size 0x%x: bufnmb 0x%x\n",
+ pipe_num, buff_size, bufnmb);
+
+ return (0x1f & bufnmb_cnt) << 10 |
+ (0xff & bufnmb) << 0;
+}
+
+/*
+ * pipe control
+ */
+int usbhs_pipe_get_maxpacket(struct usbhs_pipe *pipe)
+{
+ u16 mask = usbhsp_is_dcp(pipe) ? DCP_MAXP_MASK : PIPE_MAXP_MASK;
+
+ usbhsp_pipe_select(pipe);
+
+ return (int)(usbhsp_pipe_maxp_get(pipe) & mask);
+}
+
+int usbhs_pipe_is_dir_in(struct usbhs_pipe *pipe)
+{
+ return usbhsp_flags_has(pipe, IS_DIR_IN);
+}
+
+void usbhs_pipe_clear_sequence(struct usbhs_pipe *pipe)
+{
+ usbhsp_pipectrl_set(pipe, SQCLR, SQCLR);
+}
+
+static struct usbhs_pipe *usbhsp_get_pipe(struct usbhs_priv *priv, u32 type)
+{
+ struct usbhs_pipe *pos, *pipe;
+ int i;
+
+ /*
+ * find target pipe
+ */
+ pipe = NULL;
+ usbhs_for_each_pipe_with_dcp(pos, priv, i) {
+ if (!usbhsp_type_is(pos, type))
+ continue;
+ if (usbhsp_flags_has(pos, IS_USED))
+ continue;
+
+ pipe = pos;
+ break;
+ }
+
+ if (!pipe)
+ return NULL;
+
+ /*
+ * initialize pipe flags
+ */
+ usbhsp_flags_init(pipe);
+ usbhsp_flags_set(pipe, IS_USED);
+
+ return pipe;
+}
+
+void usbhs_pipe_init(struct usbhs_priv *priv)
+{
+ struct usbhs_pipe_info *info = usbhsp_priv_to_pipeinfo(priv);
+ struct usbhs_pipe *pipe;
+ int i;
+
+ /*
+ * FIXME
+ *
+ * driver needs good allocator.
+ *
+ * find first free buffer area (BULK, ISOC)
+ * (DCP, INT area is fixed)
+ *
+ * buffer number 0 - 3 have been reserved for DCP
+ * see
+ * usbhsp_to_bufnmb
+ */
+ info->bufnmb_last = 4;
+ usbhs_for_each_pipe_with_dcp(pipe, priv, i) {
+ if (usbhsp_type_is(pipe, USB_ENDPOINT_XFER_INT))
+ info->bufnmb_last++;
+
+ usbhsp_flags_init(pipe);
+ pipe->mod_private = NULL;
+
+ usbhsp_fifo_clear(pipe);
+ }
+}
+
+struct usbhs_pipe *usbhs_pipe_malloc(struct usbhs_priv *priv,
+ const struct usb_endpoint_descriptor *desc)
+{
+ struct device *dev = usbhs_priv_to_dev(priv);
+ struct usbhs_mod *mod = usbhs_mod_get_current(priv);
+ struct usbhs_pipe *pipe;
+ int is_host = usbhs_mod_is_host(priv, mod);
+ int ret;
+ u16 pipecfg, pipebuf, pipemaxp;
+
+ pipe = usbhsp_get_pipe(priv, usb_endpoint_type(desc));
+ if (!pipe) {
+ dev_err(dev, "can't get pipe (%s)\n",
+ usbhsp_pipe_name[usb_endpoint_type(desc)]);
+ return NULL;
+ }
+
+ usbhs_fifo_disable(pipe);
+
+ /* make sure pipe is not busy */
+ ret = usbhsp_pipe_barrier(pipe);
+ if (ret < 0) {
+ dev_err(dev, "pipe setup failed %d\n", usbhs_pipe_number(pipe));
+ return NULL;
+ }
+
+ pipecfg = usbhsp_setup_pipecfg(pipe, desc, is_host);
+ pipebuf = usbhsp_setup_pipebuff(pipe, desc, is_host);
+ pipemaxp = usbhsp_setup_pipemaxp(pipe, desc, is_host);
+
+ /* buffer clear
+ * see PIPECFG :: BFRE */
+ usbhsp_pipectrl_set(pipe, ACLRM, ACLRM);
+ usbhsp_pipectrl_set(pipe, ACLRM, 0);
+
+ usbhsp_pipe_select(pipe);
+ usbhsp_pipe_cfg_set(pipe, 0xFFFF, pipecfg);
+ usbhsp_pipe_buf_set(pipe, 0xFFFF, pipebuf);
+ usbhsp_pipe_maxp_set(pipe, 0xFFFF, pipemaxp);
+
+ usbhs_pipe_clear_sequence(pipe);
+
+ dev_dbg(dev, "enable pipe %d : %s (%s)\n",
+ usbhs_pipe_number(pipe),
+ usbhsp_pipe_name[usb_endpoint_type(desc)],
+ usbhs_pipe_is_dir_in(pipe) ? "in" : "out");
+
+ return pipe;
+}
+
+/*
+ * dcp control
+ */
+struct usbhs_pipe *usbhs_dcp_malloc(struct usbhs_priv *priv)
+{
+ struct usbhs_pipe *pipe;
+
+ pipe = usbhsp_get_pipe(priv, USB_ENDPOINT_XFER_CONTROL);
+ if (!pipe)
+ return NULL;
+
+ /*
+ * dcpcfg : default
+ * dcpmaxp : default
+ * pipebuf : nothing to do
+ */
+
+ usbhsp_pipe_select(pipe);
+ usbhs_pipe_clear_sequence(pipe);
+
+ return pipe;
+}
+
+void usbhs_dcp_control_transfer_done(struct usbhs_pipe *pipe)
+{
+ WARN_ON(!usbhsp_is_dcp(pipe));
+
+ usbhs_fifo_enable(pipe);
+ usbhsp_pipectrl_set(pipe, CCPL, CCPL);
+}
+
+
+/*
+ * pipe module function
+ */
+int usbhs_pipe_probe(struct usbhs_priv *priv)
+{
+ struct usbhs_pipe_info *info = usbhsp_priv_to_pipeinfo(priv);
+ struct usbhs_pipe *pipe;
+ struct device *dev = usbhs_priv_to_dev(priv);
+ u32 *pipe_type = usbhs_get_dparam(priv, pipe_type);
+ int pipe_size = usbhs_get_dparam(priv, pipe_size);
+ int i;
+
+ /* This driver expects 1st pipe is DCP */
+ if (pipe_type[0] != USB_ENDPOINT_XFER_CONTROL) {
+ dev_err(dev, "1st PIPE is not DCP\n");
+ return -EINVAL;
+ }
+
+ info->pipe = kzalloc(sizeof(struct usbhs_pipe) * pipe_size, GFP_KERNEL);
+ if (!info->pipe) {
+ dev_err(dev, "Could not allocate pipe\n");
+ return -ENOMEM;
+ }
+
+ info->size = pipe_size;
+
+ /*
+ * init pipe
+ */
+ usbhs_for_each_pipe_with_dcp(pipe, priv, i) {
+ pipe->priv = priv;
+ usbhsp_type(pipe) = pipe_type[i] & USB_ENDPOINT_XFERTYPE_MASK;
+
+ dev_dbg(dev, "pipe %x\t: %s\n",
+ i, usbhsp_pipe_name[pipe_type[i]]);
+ }
+
+ return 0;
+}
+
+void usbhs_pipe_remove(struct usbhs_priv *priv)
+{
+ struct usbhs_pipe_info *info = usbhsp_priv_to_pipeinfo(priv);
+
+ kfree(info->pipe);
+}
diff --git a/drivers/usb/renesas_usbhs/pipe.h b/drivers/usb/renesas_usbhs/pipe.h
new file mode 100644
index 0000000..1cca9b7
--- /dev/null
+++ b/drivers/usb/renesas_usbhs/pipe.h
@@ -0,0 +1,104 @@
+/*
+ * Renesas USB driver
+ *
+ * Copyright (C) 2011 Renesas Solutions Corp.
+ * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ */
+#ifndef RENESAS_USB_PIPE_H
+#define RENESAS_USB_PIPE_H
+
+#include "./common.h"
+
+/*
+ * struct
+ */
+struct usbhs_pipe {
+ u32 pipe_type; /* USB_ENDPOINT_XFER_xxx */
+
+ struct usbhs_priv *priv;
+
+ u32 flags;
+#define USBHS_PIPE_FLAGS_IS_USED (1 << 0)
+#define USBHS_PIPE_FLAGS_IS_DIR_IN (1 << 1)
+
+ void *mod_private;
+};
+
+struct usbhs_pipe_info {
+ struct usbhs_pipe *pipe;
+ int size; /* array size of "pipe" */
+ int bufnmb_last; /* FIXME : driver needs good allocator */
+};
+
+/*
+ * pipe list
+ */
+#define __usbhs_for_each_pipe(start, pos, info, i) \
+ for (i = start, pos = (info)->pipe; \
+ i < (info)->size; \
+ i++, pos = (info)->pipe + i)
+
+#define usbhs_for_each_pipe(pos, priv, i) \
+ __usbhs_for_each_pipe(1, pos, &((priv)->pipe_info), i)
+
+#define usbhs_for_each_pipe_with_dcp(pos, priv, i) \
+ __usbhs_for_each_pipe(0, pos, &((priv)->pipe_info), i)
+
+/*
+ * pipe module probe / remove
+ */
+int usbhs_pipe_probe(struct usbhs_priv *priv);
+void usbhs_pipe_remove(struct usbhs_priv *priv);
+
+/*
+ * cfifo
+ */
+int usbhs_fifo_write(struct usbhs_pipe *pipe, u8 *buf, int len);
+int usbhs_fifo_read(struct usbhs_pipe *pipe, u8 *buf, int len);
+int usbhs_fifo_prepare_write(struct usbhs_pipe *pipe);
+int usbhs_fifo_prepare_read(struct usbhs_pipe *pipe);
+
+void usbhs_fifo_enable(struct usbhs_pipe *pipe);
+void usbhs_fifo_disable(struct usbhs_pipe *pipe);
+void usbhs_fifo_stall(struct usbhs_pipe *pipe);
+
+void usbhs_fifo_send_terminator(struct usbhs_pipe *pipe);
+
+
+/*
+ * usb request
+ */
+void usbhs_usbreq_get_val(struct usbhs_priv *priv, struct usb_ctrlrequest *req);
+void usbhs_usbreq_set_val(struct usbhs_priv *priv, struct usb_ctrlrequest *req);
+
+/*
+ * pipe control
+ */
+struct usbhs_pipe
+*usbhs_pipe_malloc(struct usbhs_priv *priv,
+ const struct usb_endpoint_descriptor *desc);
+
+int usbhs_pipe_is_dir_in(struct usbhs_pipe *pipe);
+void usbhs_pipe_init(struct usbhs_priv *priv);
+int usbhs_pipe_get_maxpacket(struct usbhs_pipe *pipe);
+void usbhs_pipe_clear_sequence(struct usbhs_pipe *pipe);
+
+#define usbhs_pipe_number(p) (int)((p) - (p)->priv->pipe_info.pipe)
+
+/*
+ * dcp control
+ */
+struct usbhs_pipe *usbhs_dcp_malloc(struct usbhs_priv *priv);
+void usbhs_dcp_control_transfer_done(struct usbhs_pipe *pipe);
+
+#endif /* RENESAS_USB_PIPE_H */
diff --git a/drivers/usb/serial/Kconfig b/drivers/usb/serial/Kconfig
index c2b2976..b71e309 100644
--- a/drivers/usb/serial/Kconfig
+++ b/drivers/usb/serial/Kconfig
@@ -527,15 +527,6 @@
bool "USB Secure Encapsulated Driver - Padded"
depends on USB_SERIAL_SAFE
-config USB_SERIAL_SAMBA
- tristate "USB Atmel SAM Boot Assistant (SAM-BA) driver"
- help
- Say Y here if you want to access the SAM-BA boot application of an
- Atmel AT91SAM device.
-
- To compile this driver as a module, choose M here: the
- module will be called sam-ba.
-
config USB_SERIAL_SIEMENS_MPI
tristate "USB Siemens MPI driver"
help
diff --git a/drivers/usb/serial/Makefile b/drivers/usb/serial/Makefile
index 9a2117f..9e536ee 100644
--- a/drivers/usb/serial/Makefile
+++ b/drivers/usb/serial/Makefile
@@ -48,7 +48,6 @@
obj-$(CONFIG_USB_SERIAL_QCAUX) += qcaux.o
obj-$(CONFIG_USB_SERIAL_QUALCOMM) += qcserial.o
obj-$(CONFIG_USB_SERIAL_SAFE) += safe_serial.o
-obj-$(CONFIG_USB_SERIAL_SAMBA) += sam-ba.o
obj-$(CONFIG_USB_SERIAL_SIEMENS_MPI) += siemens_mpi.o
obj-$(CONFIG_USB_SERIAL_SIERRAWIRELESS) += sierra.o
obj-$(CONFIG_USB_SERIAL_SPCP8X5) += spcp8x5.o
diff --git a/drivers/usb/serial/cp210x.c b/drivers/usb/serial/cp210x.c
index 0f11afd..fd67cc5 100644
--- a/drivers/usb/serial/cp210x.c
+++ b/drivers/usb/serial/cp210x.c
@@ -102,7 +102,7 @@
{ USB_DEVICE(0x10C4, 0x8218) }, /* Lipowsky Industrie Elektronik GmbH, HARP-1 */
{ USB_DEVICE(0x10C4, 0x822B) }, /* Modem EDGE(GSM) Comander 2 */
{ USB_DEVICE(0x10C4, 0x826B) }, /* Cygnal Integrated Products, Inc., Fasttrax GPS demonstration module */
- { USB_DEVICE(0x10C4, 0x8293) }, /* Telegesys ETRX2USB */
+ { USB_DEVICE(0x10C4, 0x8293) }, /* Telegesis ETRX2USB */
{ USB_DEVICE(0x10C4, 0x82F9) }, /* Procyon AVS */
{ USB_DEVICE(0x10C4, 0x8341) }, /* Siemens MC35PU GPRS Modem */
{ USB_DEVICE(0x10C4, 0x8382) }, /* Cygnal Integrated Products, Inc. */
@@ -112,6 +112,10 @@
{ USB_DEVICE(0x10C4, 0x8418) }, /* IRZ Automation Teleport SG-10 GSM/GPRS Modem */
{ USB_DEVICE(0x10C4, 0x846E) }, /* BEI USB Sensor Interface (VCP) */
{ USB_DEVICE(0x10C4, 0x8477) }, /* Balluff RFID */
+ { USB_DEVICE(0x10C4, 0x85EA) }, /* AC-Services IBUS-IF */
+ { USB_DEVICE(0x10C4, 0x85EB) }, /* AC-Services CIS-IBUS */
+ { USB_DEVICE(0x10C4, 0x8664) }, /* AC-Services CAN-IF */
+ { USB_DEVICE(0x10C4, 0x8665) }, /* AC-Services OBD-IF */
{ USB_DEVICE(0x10C4, 0xEA60) }, /* Silicon Labs factory default */
{ USB_DEVICE(0x10C4, 0xEA61) }, /* Silicon Labs factory default */
{ USB_DEVICE(0x10C4, 0xEA71) }, /* Infinity GPS-MIC-1 Radio Monophone */
diff --git a/drivers/usb/serial/ftdi_sio.c b/drivers/usb/serial/ftdi_sio.c
index 4de6ef0..e8dbde5 100644
--- a/drivers/usb/serial/ftdi_sio.c
+++ b/drivers/usb/serial/ftdi_sio.c
@@ -566,6 +566,7 @@
{ USB_DEVICE(FTDI_VID, FTDI_IBS_APP70_PID) },
{ USB_DEVICE(FTDI_VID, FTDI_IBS_PEDO_PID) },
{ USB_DEVICE(FTDI_VID, FTDI_IBS_PROD_PID) },
+ { USB_DEVICE(FTDI_VID, FTDI_TAVIR_STK500_PID) },
/*
* ELV devices:
*/
diff --git a/drivers/usb/serial/ftdi_sio_ids.h b/drivers/usb/serial/ftdi_sio_ids.h
index efffc23..1d946cd 100644
--- a/drivers/usb/serial/ftdi_sio_ids.h
+++ b/drivers/usb/serial/ftdi_sio_ids.h
@@ -491,6 +491,11 @@
/* www.canusb.com Lawicel CANUSB device (FTDI_VID) */
#define FTDI_CANUSB_PID 0xFFA8 /* Product Id */
+/*
+ * TavIR AVR product ids (FTDI_VID)
+ */
+#define FTDI_TAVIR_STK500_PID 0xFA33 /* STK500 AVR programmer */
+
/********************************/
diff --git a/drivers/usb/serial/garmin_gps.c b/drivers/usb/serial/garmin_gps.c
index 26710b1..b0a7a9e 100644
--- a/drivers/usb/serial/garmin_gps.c
+++ b/drivers/usb/serial/garmin_gps.c
@@ -1,7 +1,7 @@
/*
* Garmin GPS driver
*
- * Copyright (C) 2006-2009 Hermann Kneissel herkne@users.sourceforge.net
+ * Copyright (C) 2006-2011 Hermann Kneissel herkne@gmx.de
*
* The latest version of the driver can be found at
* http://sourceforge.net/projects/garmin-gps/
@@ -51,7 +51,7 @@
*/
#define VERSION_MAJOR 0
-#define VERSION_MINOR 33
+#define VERSION_MINOR 36
#define _STR(s) #s
#define _DRIVER_VERSION(a, b) "v" _STR(a) "." _STR(b)
@@ -410,6 +410,7 @@
*/
static int gsp_rec_packet(struct garmin_data *garmin_data_p, int count)
{
+ unsigned long flags;
const __u8 *recpkt = garmin_data_p->inbuffer+GSP_INITIAL_OFFSET;
__le32 *usbdata = (__le32 *) garmin_data_p->inbuffer;
@@ -458,7 +459,9 @@
/* if this was an abort-transfer command, flush all
queued data. */
if (isAbortTrfCmnd(garmin_data_p->inbuffer)) {
+ spin_lock_irqsave(&garmin_data_p->lock, flags);
garmin_data_p->flags |= FLAGS_DROP_DATA;
+ spin_unlock_irqrestore(&garmin_data_p->lock, flags);
pkt_clear(garmin_data_p);
}
@@ -943,7 +946,7 @@
spin_lock_irqsave(&garmin_data_p->lock, flags);
garmin_data_p->mode = initial_mode;
garmin_data_p->count = 0;
- garmin_data_p->flags = 0;
+ garmin_data_p->flags &= FLAGS_SESSION_REPLY1_SEEN;
spin_unlock_irqrestore(&garmin_data_p->lock, flags);
/* shutdown any bulk reads that might be going on */
@@ -1178,7 +1181,8 @@
static void garmin_read_process(struct garmin_data *garmin_data_p,
- unsigned char *data, unsigned data_length)
+ unsigned char *data, unsigned data_length,
+ int bulk_data)
{
unsigned long flags;
@@ -1193,7 +1197,8 @@
send it directly to the tty port */
if (garmin_data_p->flags & FLAGS_QUEUING) {
pkt_add(garmin_data_p, data, data_length);
- } else if (getLayerId(data) == GARMIN_LAYERID_APPL) {
+ } else if (bulk_data ||
+ getLayerId(data) == GARMIN_LAYERID_APPL) {
spin_lock_irqsave(&garmin_data_p->lock, flags);
garmin_data_p->flags |= APP_RESP_SEEN;
@@ -1237,7 +1242,7 @@
usb_serial_debug_data(debug, &port->dev,
__func__, urb->actual_length, data);
- garmin_read_process(garmin_data_p, data, urb->actual_length);
+ garmin_read_process(garmin_data_p, data, urb->actual_length, 1);
if (urb->actual_length == 0 &&
0 != (garmin_data_p->flags & FLAGS_BULK_IN_RESTART)) {
@@ -1346,7 +1351,7 @@
__func__, garmin_data_p->serial_num);
}
- garmin_read_process(garmin_data_p, data, urb->actual_length);
+ garmin_read_process(garmin_data_p, data, urb->actual_length, 0);
port->interrupt_in_urb->dev = port->serial->dev;
retval = usb_submit_urb(urb, GFP_ATOMIC);
@@ -1461,6 +1466,7 @@
garmin_data_p->timer.function = timeout_handler;
garmin_data_p->port = port;
garmin_data_p->state = 0;
+ garmin_data_p->flags = 0;
garmin_data_p->count = 0;
usb_set_serial_port_data(port, garmin_data_p);
diff --git a/drivers/usb/serial/moto_modem.c b/drivers/usb/serial/moto_modem.c
index 653465f..e2bfecc 100644
--- a/drivers/usb/serial/moto_modem.c
+++ b/drivers/usb/serial/moto_modem.c
@@ -25,6 +25,7 @@
{ USB_DEVICE(0x05c6, 0x3197) }, /* unknown Motorola phone */
{ USB_DEVICE(0x0c44, 0x0022) }, /* unknown Mororola phone */
{ USB_DEVICE(0x22b8, 0x2a64) }, /* Motorola KRZR K1m */
+ { USB_DEVICE(0x22b8, 0x2c84) }, /* Motorola VE240 phone */
{ USB_DEVICE(0x22b8, 0x2c64) }, /* Motorola V950 phone */
{ },
};
diff --git a/drivers/usb/serial/opticon.c b/drivers/usb/serial/opticon.c
index 1b5633f..96423f3 100644
--- a/drivers/usb/serial/opticon.c
+++ b/drivers/usb/serial/opticon.c
@@ -289,8 +289,11 @@
/* The conncected devices do not have a bulk write endpoint,
* to transmit data to de barcode device the control endpoint is used */
dr = kmalloc(sizeof(struct usb_ctrlrequest), GFP_NOIO);
- if (!dr)
- return -ENOMEM;
+ if (!dr) {
+ dev_err(&port->dev, "out of memory\n");
+ count = -ENOMEM;
+ goto error;
+ }
dr->bRequestType = USB_TYPE_VENDOR | USB_RECIP_INTERFACE | USB_DIR_OUT;
dr->bRequest = 0x01;
diff --git a/drivers/usb/serial/option.c b/drivers/usb/serial/option.c
index d77ff04..318dd00 100644
--- a/drivers/usb/serial/option.c
+++ b/drivers/usb/serial/option.c
@@ -149,6 +149,7 @@
#define HUAWEI_PRODUCT_K3765 0x1465
#define HUAWEI_PRODUCT_E14AC 0x14AC
#define HUAWEI_PRODUCT_ETS1220 0x1803
+#define HUAWEI_PRODUCT_E353 0x1506
#define QUANTA_VENDOR_ID 0x0408
#define QUANTA_PRODUCT_Q101 0xEA02
@@ -532,6 +533,7 @@
{ USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_K3765, 0xff, 0xff, 0xff) },
{ USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_ETS1220, 0xff, 0xff, 0xff) },
{ USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E14AC, 0xff, 0xff, 0xff) },
+ { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_E353, 0xff, 0x01, 0x01) },
{ USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, NOVATELWIRELESS_PRODUCT_V640) },
{ USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, NOVATELWIRELESS_PRODUCT_V620) },
{ USB_DEVICE(NOVATELWIRELESS_VENDOR_ID, NOVATELWIRELESS_PRODUCT_V740) },
@@ -972,7 +974,7 @@
{ USB_DEVICE(OLIVETTI_VENDOR_ID, OLIVETTI_PRODUCT_OLICARD100) },
{ USB_DEVICE(CELOT_VENDOR_ID, CELOT_PRODUCT_CT680M) }, /* CT-650 CDMA 450 1xEVDO modem */
{ USB_DEVICE(ONDA_VENDOR_ID, ONDA_MT825UP) }, /* ONDA MT825UP modem */
- { USB_DEVICE_AND_INTERFACE_INFO(SAMSUNG_VENDOR_ID, SAMSUNG_PRODUCT_GT_B3730, USB_CLASS_CDC_DATA, 0x00, 0x00) }, /* Samsung GT-B3730/GT-B3710 LTE USB modem.*/
+ { USB_DEVICE_AND_INTERFACE_INFO(SAMSUNG_VENDOR_ID, SAMSUNG_PRODUCT_GT_B3730, USB_CLASS_CDC_DATA, 0x00, 0x00) }, /* Samsung GT-B3730 LTE USB modem.*/
{ } /* Terminating entry */
};
MODULE_DEVICE_TABLE(usb, option_ids);
@@ -1109,6 +1111,12 @@
serial->interface->cur_altsetting->desc.bInterfaceNumber == 1)
return -ENODEV;
+ /* Don't bind network interface on Samsung GT-B3730, it is handled by a separate module */
+ if (serial->dev->descriptor.idVendor == SAMSUNG_VENDOR_ID &&
+ serial->dev->descriptor.idProduct == SAMSUNG_PRODUCT_GT_B3730 &&
+ serial->interface->cur_altsetting->desc.bInterfaceClass != USB_CLASS_CDC_DATA)
+ return -ENODEV;
+
data = serial->private = kzalloc(sizeof(struct usb_wwan_intf_private), GFP_KERNEL);
if (!data)
diff --git a/drivers/usb/serial/sam-ba.c b/drivers/usb/serial/sam-ba.c
deleted file mode 100644
index e3bba64..0000000
--- a/drivers/usb/serial/sam-ba.c
+++ /dev/null
@@ -1,206 +0,0 @@
-/*
- * Atmel SAM Boot Assistant (SAM-BA) driver
- *
- * Copyright (C) 2010 Johan Hovold <jhovold@gmail.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License version
- * 2 as published by the Free Software Foundation.
- */
-
-#include <linux/kernel.h>
-#include <linux/tty.h>
-#include <linux/module.h>
-#include <linux/moduleparam.h>
-#include <linux/usb.h>
-#include <linux/usb/serial.h>
-
-
-#define DRIVER_VERSION "v1.0"
-#define DRIVER_AUTHOR "Johan Hovold <jhovold@gmail.com>"
-#define DRIVER_DESC "Atmel SAM Boot Assistant (SAM-BA) driver"
-
-#define SAMBA_VENDOR_ID 0x3eb
-#define SAMBA_PRODUCT_ID 0x6124
-
-
-static int debug;
-
-static const struct usb_device_id id_table[] = {
- /*
- * NOTE: Only match the CDC Data interface.
- */
- { USB_DEVICE_AND_INTERFACE_INFO(SAMBA_VENDOR_ID, SAMBA_PRODUCT_ID,
- USB_CLASS_CDC_DATA, 0, 0) },
- { }
-};
-MODULE_DEVICE_TABLE(usb, id_table);
-
-static struct usb_driver samba_driver = {
- .name = "sam-ba",
- .probe = usb_serial_probe,
- .disconnect = usb_serial_disconnect,
- .id_table = id_table,
- .no_dynamic_id = 1,
-};
-
-
-/*
- * NOTE: The SAM-BA firmware cannot handle merged write requests so we cannot
- * use the generic write implementation (which uses the port write fifo).
- */
-static int samba_write(struct tty_struct *tty, struct usb_serial_port *port,
- const unsigned char *buf, int count)
-{
- struct urb *urb;
- unsigned long flags;
- int result;
- int i;
-
- if (!count)
- return 0;
-
- count = min_t(int, count, port->bulk_out_size);
-
- spin_lock_irqsave(&port->lock, flags);
- if (!port->write_urbs_free) {
- spin_unlock_irqrestore(&port->lock, flags);
- return 0;
- }
- i = find_first_bit(&port->write_urbs_free,
- ARRAY_SIZE(port->write_urbs));
- __clear_bit(i, &port->write_urbs_free);
- port->tx_bytes += count;
- spin_unlock_irqrestore(&port->lock, flags);
-
- urb = port->write_urbs[i];
- memcpy(urb->transfer_buffer, buf, count);
- urb->transfer_buffer_length = count;
- usb_serial_debug_data(debug, &port->dev, __func__, count,
- urb->transfer_buffer);
- result = usb_submit_urb(urb, GFP_ATOMIC);
- if (result) {
- dev_err(&port->dev, "%s - error submitting urb: %d\n",
- __func__, result);
- spin_lock_irqsave(&port->lock, flags);
- __set_bit(i, &port->write_urbs_free);
- port->tx_bytes -= count;
- spin_unlock_irqrestore(&port->lock, flags);
-
- return result;
- }
-
- return count;
-}
-
-static int samba_write_room(struct tty_struct *tty)
-{
- struct usb_serial_port *port = tty->driver_data;
- unsigned long flags;
- unsigned long free;
- int count;
- int room;
-
- spin_lock_irqsave(&port->lock, flags);
- free = port->write_urbs_free;
- spin_unlock_irqrestore(&port->lock, flags);
-
- count = hweight_long(free);
- room = count * port->bulk_out_size;
-
- dbg("%s - returns %d", __func__, room);
-
- return room;
-}
-
-static int samba_chars_in_buffer(struct tty_struct *tty)
-{
- struct usb_serial_port *port = tty->driver_data;
- unsigned long flags;
- int chars;
-
- spin_lock_irqsave(&port->lock, flags);
- chars = port->tx_bytes;
- spin_unlock_irqrestore(&port->lock, flags);
-
- dbg("%s - returns %d", __func__, chars);
-
- return chars;
-}
-
-static void samba_write_bulk_callback(struct urb *urb)
-{
- struct usb_serial_port *port = urb->context;
- unsigned long flags;
- int i;
-
- dbg("%s - port %d", __func__, port->number);
-
- for (i = 0; i < ARRAY_SIZE(port->write_urbs); ++i) {
- if (port->write_urbs[i] == urb)
- break;
- }
- spin_lock_irqsave(&port->lock, flags);
- __set_bit(i, &port->write_urbs_free);
- port->tx_bytes -= urb->transfer_buffer_length;
- spin_unlock_irqrestore(&port->lock, flags);
-
- if (urb->status)
- dbg("%s - non-zero urb status: %d", __func__, urb->status);
-
- usb_serial_port_softint(port);
-}
-
-static struct usb_serial_driver samba_device = {
- .driver = {
- .owner = THIS_MODULE,
- .name = "sam-ba",
- },
- .usb_driver = &samba_driver,
- .id_table = id_table,
- .num_ports = 1,
- .bulk_in_size = 512,
- .bulk_out_size = 2048,
- .write = samba_write,
- .write_room = samba_write_room,
- .chars_in_buffer = samba_chars_in_buffer,
- .write_bulk_callback = samba_write_bulk_callback,
- .throttle = usb_serial_generic_throttle,
- .unthrottle = usb_serial_generic_unthrottle,
-};
-
-static int __init samba_init(void)
-{
- int retval;
-
- retval = usb_serial_register(&samba_device);
- if (retval)
- return retval;
-
- retval = usb_register(&samba_driver);
- if (retval) {
- usb_serial_deregister(&samba_device);
- return retval;
- }
-
- printk(KERN_INFO KBUILD_MODNAME ": " DRIVER_VERSION ": "
- DRIVER_DESC "\n");
- return 0;
-}
-
-static void __exit samba_exit(void)
-{
- usb_deregister(&samba_driver);
- usb_serial_deregister(&samba_device);
-}
-
-module_init(samba_init);
-module_exit(samba_exit);
-
-MODULE_AUTHOR(DRIVER_AUTHOR);
-MODULE_DESCRIPTION(DRIVER_DESC);
-MODULE_VERSION(DRIVER_VERSION);
-MODULE_LICENSE("GPL");
-
-module_param(debug, bool, S_IRUGO | S_IWUSR);
-MODULE_PARM_DESC(debug, "Enable verbose debugging messages");
diff --git a/drivers/usb/storage/unusual_realtek.h b/drivers/usb/storage/unusual_realtek.h
index 3236e03..e41f50c 100644
--- a/drivers/usb/storage/unusual_realtek.h
+++ b/drivers/usb/storage/unusual_realtek.h
@@ -23,19 +23,19 @@
#if defined(CONFIG_USB_STORAGE_REALTEK) || \
defined(CONFIG_USB_STORAGE_REALTEK_MODULE)
-UNUSUAL_DEV(0x0bda, 0x0159, 0x0000, 0x9999,
+UNUSUAL_DEV(0x0bda, 0x0138, 0x0000, 0x9999,
"Realtek",
"USB Card Reader",
- USB_SC_SCSI, USB_PR_BULK, init_realtek_cr, 0),
+ USB_SC_DEVICE, USB_PR_DEVICE, init_realtek_cr, 0),
UNUSUAL_DEV(0x0bda, 0x0158, 0x0000, 0x9999,
"Realtek",
"USB Card Reader",
- USB_SC_SCSI, USB_PR_BULK, init_realtek_cr, 0),
+ USB_SC_DEVICE, USB_PR_DEVICE, init_realtek_cr, 0),
-UNUSUAL_DEV(0x0bda, 0x0138, 0x0000, 0x9999,
+UNUSUAL_DEV(0x0bda, 0x0159, 0x0000, 0x9999,
"Realtek",
"USB Card Reader",
- USB_SC_SCSI, USB_PR_BULK, init_realtek_cr, 0),
+ USB_SC_DEVICE, USB_PR_DEVICE, init_realtek_cr, 0),
#endif /* defined(CONFIG_USB_STORAGE_REALTEK) || ... */
diff --git a/drivers/usb/storage/usb.c b/drivers/usb/storage/usb.c
index 4219c19..5ee7ac4 100644
--- a/drivers/usb/storage/usb.c
+++ b/drivers/usb/storage/usb.c
@@ -439,7 +439,8 @@
US_FL_CAPACITY_HEURISTICS | US_FL_IGNORE_DEVICE |
US_FL_NOT_LOCKABLE | US_FL_MAX_SECTORS_64 |
US_FL_CAPACITY_OK | US_FL_IGNORE_RESIDUE |
- US_FL_SINGLE_LUN | US_FL_NO_WP_DETECT);
+ US_FL_SINGLE_LUN | US_FL_NO_WP_DETECT |
+ US_FL_NO_READ_DISC_INFO | US_FL_NO_READ_CAPACITY_16);
p = quirks;
while (*p) {
@@ -471,6 +472,12 @@
case 'c':
f |= US_FL_FIX_CAPACITY;
break;
+ case 'd':
+ f |= US_FL_NO_READ_DISC_INFO;
+ break;
+ case 'e':
+ f |= US_FL_NO_READ_CAPACITY_16;
+ break;
case 'h':
f |= US_FL_CAPACITY_HEURISTICS;
break;
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 6d13967..549b960 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -8,9 +8,6 @@
config HAVE_FB_ATMEL
bool
-config HAVE_FB_IMX
- bool
-
config SH_MIPI_DSI
tristate
depends on (SUPERH || ARCH_SHMOBILE) && HAVE_CLK
@@ -359,7 +356,7 @@
config FB_IMX
tristate "Freescale i.MX LCD support"
- depends on FB && (HAVE_FB_IMX || ARCH_MX1 || ARCH_MX2)
+ depends on FB && IMX_HAVE_PLATFORM_IMX_FB
select FB_CFB_FILLRECT
select FB_CFB_COPYAREA
select FB_CFB_IMAGEBLIT
@@ -1463,6 +1460,14 @@
---help---
Driver for graphics boards with S3 Trio / S3 Virge chip.
+config FB_S3_DDC
+ bool "DDC for S3 support"
+ depends on FB_S3
+ select FB_DDC
+ default y
+ help
+ Say Y here if you want DDC support for your S3 graphics card.
+
config FB_SAVAGE
tristate "S3 Savage support"
depends on FB && PCI && EXPERIMENTAL
@@ -1986,6 +1991,18 @@
---help---
Driver for the on-chip SH-Mobile HDMI controller.
+config FB_SH_MOBILE_MERAM
+ tristate "SuperH Mobile MERAM read ahead support for LCDC"
+ depends on FB_SH_MOBILE_LCDC
+ default y
+ ---help---
+ Enable MERAM support for the SH-Mobile LCD controller.
+
+ This will allow for caching of the framebuffer to provide more
+ reliable access under heavy main memory bus traffic situations.
+ Up to 4 memory channels can be configured, allowing 4 RGB or
+ 2 YCbCr framebuffers to be configured.
+
config FB_TMIO
tristate "Toshiba Mobile IO FrameBuffer support"
depends on FB && MFD_CORE
@@ -2249,29 +2266,43 @@
config FB_MB862XX
tristate "Fujitsu MB862xx GDC support"
depends on FB
+ depends on PCI || (OF && PPC)
select FB_CFB_FILLRECT
select FB_CFB_COPYAREA
select FB_CFB_IMAGEBLIT
---help---
Frame buffer driver for Fujitsu Carmine/Coral-P(A)/Lime controllers.
+choice
+ prompt "GDC variant"
+ depends on FB_MB862XX
+
config FB_MB862XX_PCI_GDC
bool "Carmine/Coral-P(A) GDC"
- depends on PCI && FB_MB862XX
+ depends on PCI
---help---
This enables framebuffer support for Fujitsu Carmine/Coral-P(A)
PCI graphics controller devices.
config FB_MB862XX_LIME
bool "Lime GDC"
- depends on FB_MB862XX
- depends on OF && !FB_MB862XX_PCI_GDC
- depends on PPC
+ depends on OF && PPC
select FB_FOREIGN_ENDIAN
select FB_LITTLE_ENDIAN
---help---
Framebuffer support for Fujitsu Lime GDC on host CPU bus.
+endchoice
+
+config FB_MB862XX_I2C
+ bool "Support I2C bus on MB862XX GDC"
+ depends on FB_MB862XX && I2C
+ default y
+ help
+ Selecting this option adds Coral-P(A)/Lime GDC I2C bus adapter
+ driver to support accessing I2C devices on controller's I2C bus.
+ These are usually some video decoder chips.
+
config FB_EP93XX
tristate "EP93XX frame buffer support"
depends on FB && ARCH_EP93XX
diff --git a/drivers/video/Makefile b/drivers/video/Makefile
index 2ea44b6..8b83129 100644
--- a/drivers/video/Makefile
+++ b/drivers/video/Makefile
@@ -130,6 +130,7 @@
obj-$(CONFIG_FB_XILINX) += xilinxfb.o
obj-$(CONFIG_SH_MIPI_DSI) += sh_mipi_dsi.o
obj-$(CONFIG_FB_SH_MOBILE_HDMI) += sh_mobile_hdmi.o
+obj-$(CONFIG_FB_SH_MOBILE_MERAM) += sh_mobile_meram.o
obj-$(CONFIG_FB_SH_MOBILE_LCDC) += sh_mobile_lcdcfb.o
obj-$(CONFIG_FB_OMAP) += omap/
obj-y += omap2/
diff --git a/drivers/video/amifb.c b/drivers/video/amifb.c
index e5d6b56..5ea6596 100644
--- a/drivers/video/amifb.c
+++ b/drivers/video/amifb.c
@@ -2224,22 +2224,23 @@
* Allocate, Clear and Align a Block of Chip Memory
*/
-static u_long unaligned_chipptr = 0;
+static void *aligned_chipptr;
static inline u_long __init chipalloc(u_long size)
{
- size += PAGE_SIZE-1;
- if (!(unaligned_chipptr = (u_long)amiga_chip_alloc(size,
- "amifb [RAM]")))
- panic("No Chip RAM for frame buffer");
- memset((void *)unaligned_chipptr, 0, size);
- return PAGE_ALIGN(unaligned_chipptr);
+ aligned_chipptr = amiga_chip_alloc(size, "amifb [RAM]");
+ if (!aligned_chipptr) {
+ pr_err("amifb: No Chip RAM for frame buffer");
+ return 0;
+ }
+ memset(aligned_chipptr, 0, size);
+ return (u_long)aligned_chipptr;
}
static inline void chipfree(void)
{
- if (unaligned_chipptr)
- amiga_chip_free((void *)unaligned_chipptr);
+ if (aligned_chipptr)
+ amiga_chip_free(aligned_chipptr);
}
@@ -2295,7 +2296,7 @@
defmode = amiga_vblank == 50 ? DEFMODE_PAL
: DEFMODE_NTSC;
if (amiga_chip_avail()-CHIPRAM_SAFETY_LIMIT >
- VIDEOMEMSIZE_ECS_1M)
+ VIDEOMEMSIZE_ECS_2M)
fb_info.fix.smem_len = VIDEOMEMSIZE_ECS_2M;
else
fb_info.fix.smem_len = VIDEOMEMSIZE_ECS_1M;
@@ -2312,7 +2313,7 @@
maxfmode = TAG_FMODE_4;
defmode = DEFMODE_AGA;
if (amiga_chip_avail()-CHIPRAM_SAFETY_LIMIT >
- VIDEOMEMSIZE_AGA_1M)
+ VIDEOMEMSIZE_AGA_2M)
fb_info.fix.smem_len = VIDEOMEMSIZE_AGA_2M;
else
fb_info.fix.smem_len = VIDEOMEMSIZE_AGA_1M;
@@ -2385,6 +2386,10 @@
DUMMYSPRITEMEMSIZE+
COPINITSIZE+
4*COPLISTSIZE);
+ if (!chipptr) {
+ err = -ENOMEM;
+ goto amifb_error;
+ }
assignchunk(videomemory, u_long, chipptr, fb_info.fix.smem_len);
assignchunk(spritememory, u_long, chipptr, SPRITEMEMSIZE);
diff --git a/drivers/video/backlight/adp5520_bl.c b/drivers/video/backlight/adp5520_bl.c
index af31197..d1aee73 100644
--- a/drivers/video/backlight/adp5520_bl.c
+++ b/drivers/video/backlight/adp5520_bl.c
@@ -211,8 +211,12 @@
const char *buf, size_t count)
{
struct adp5520_bl *data = dev_get_drvdata(dev);
+ int ret;
- strict_strtoul(buf, 10, &data->cached_daylight_max);
+ ret = strict_strtoul(buf, 10, &data->cached_daylight_max);
+ if (ret < 0)
+ return ret;
+
return adp5520_store(dev, buf, count, ADP5520_DAYLIGHT_MAX);
}
static DEVICE_ATTR(daylight_max, 0664, adp5520_bl_daylight_max_show,
diff --git a/drivers/video/da8xx-fb.c b/drivers/video/da8xx-fb.c
index 8b7d473..fcdac87 100644
--- a/drivers/video/da8xx-fb.c
+++ b/drivers/video/da8xx-fb.c
@@ -899,7 +899,7 @@
.fb_blank = cfb_blank,
};
-static int __init fb_probe(struct platform_device *device)
+static int __devinit fb_probe(struct platform_device *device)
{
struct da8xx_lcdc_platform_data *fb_pdata =
device->dev.platform_data;
@@ -1165,7 +1165,7 @@
static struct platform_driver da8xx_fb_driver = {
.probe = fb_probe,
- .remove = fb_remove,
+ .remove = __devexit_p(fb_remove),
.suspend = fb_suspend,
.resume = fb_resume,
.driver = {
diff --git a/drivers/video/efifb.c b/drivers/video/efifb.c
index 4eb38db..fb20584 100644
--- a/drivers/video/efifb.c
+++ b/drivers/video/efifb.c
@@ -242,9 +242,9 @@
return 0;
}
- printk(KERN_INFO "efifb: dmi detected %s - framebuffer at %p "
+ printk(KERN_INFO "efifb: dmi detected %s - framebuffer at 0x%08x "
"(%dx%d, stride %d)\n", id->ident,
- (void *)screen_info.lfb_base, screen_info.lfb_width,
+ screen_info.lfb_base, screen_info.lfb_width,
screen_info.lfb_height, screen_info.lfb_linelength);
diff --git a/drivers/video/imxfb.c b/drivers/video/imxfb.c
index ef72cb4..d2ccfd6 100644
--- a/drivers/video/imxfb.c
+++ b/drivers/video/imxfb.c
@@ -65,12 +65,6 @@
#define CPOS_OP (1<<28)
#define CPOS_CXP(x) (((x) & 3ff) << 16)
-#ifdef CONFIG_ARCH_MX1
-#define CPOS_CYP(y) ((y) & 0x1ff)
-#else
-#define CPOS_CYP(y) ((y) & 0x3ff)
-#endif
-
#define LCDC_LCWHB 0x10
#define LCWHB_BK_EN (1<<31)
#define LCWHB_CW(w) (((w) & 0x1f) << 24)
@@ -79,16 +73,6 @@
#define LCDC_LCHCC 0x14
-#ifdef CONFIG_ARCH_MX1
-#define LCHCC_CUR_COL_R(r) (((r) & 0x1f) << 11)
-#define LCHCC_CUR_COL_G(g) (((g) & 0x3f) << 5)
-#define LCHCC_CUR_COL_B(b) ((b) & 0x1f)
-#else
-#define LCHCC_CUR_COL_R(r) (((r) & 0x3f) << 12)
-#define LCHCC_CUR_COL_G(g) (((g) & 0x3f) << 6)
-#define LCHCC_CUR_COL_B(b) ((b) & 0x3f)
-#endif
-
#define LCDC_PCR 0x18
#define LCDC_HCR 0x1C
@@ -115,11 +99,7 @@
#define LCDC_RMCR 0x34
-#ifdef CONFIG_ARCH_MX1
-#define RMCR_LCDC_EN (1<<1)
-#else
-#define RMCR_LCDC_EN 0
-#endif
+#define RMCR_LCDC_EN_MX1 (1<<1)
#define RMCR_SELF_REF (1<<0)
@@ -536,7 +516,11 @@
writel(readl(fbi->regs + LCDC_CPOS) & ~(CPOS_CC0 | CPOS_CC1),
fbi->regs + LCDC_CPOS);
- writel(RMCR_LCDC_EN, fbi->regs + LCDC_RMCR);
+ /*
+ * RMCR_LCDC_EN_MX1 is present on i.MX1 only, but doesn't hurt
+ * on other SoCs
+ */
+ writel(RMCR_LCDC_EN_MX1, fbi->regs + LCDC_RMCR);
clk_enable(fbi->clk);
diff --git a/drivers/video/mb862xx/Makefile b/drivers/video/mb862xx/Makefile
index d777771..5707ed0 100644
--- a/drivers/video/mb862xx/Makefile
+++ b/drivers/video/mb862xx/Makefile
@@ -2,4 +2,7 @@
# Makefile for the MB862xx framebuffer driver
#
-obj-$(CONFIG_FB_MB862XX) := mb862xxfb.o mb862xxfb_accel.o
+obj-$(CONFIG_FB_MB862XX) += mb862xxfb.o
+
+mb862xxfb-y := mb862xxfbdrv.o mb862xxfb_accel.o
+mb862xxfb-$(CONFIG_FB_MB862XX_I2C) += mb862xx-i2c.o
diff --git a/drivers/video/mb862xx/mb862xx-i2c.c b/drivers/video/mb862xx/mb862xx-i2c.c
new file mode 100644
index 0000000..cb77d3b
--- /dev/null
+++ b/drivers/video/mb862xx/mb862xx-i2c.c
@@ -0,0 +1,177 @@
+/*
+ * Coral-P(A)/Lime I2C adapter driver
+ *
+ * (C) 2011 DENX Software Engineering, Anatolij Gustschin <agust@denx.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#include <linux/fb.h>
+#include <linux/i2c.h>
+#include <linux/io.h>
+
+#include "mb862xxfb.h"
+#include "mb862xx_reg.h"
+
+static int mb862xx_i2c_wait_event(struct i2c_adapter *adap)
+{
+ struct mb862xxfb_par *par = adap->algo_data;
+ u32 reg;
+
+ do {
+ udelay(1);
+ reg = inreg(i2c, GC_I2C_BCR);
+ if (reg & (I2C_INT | I2C_BER))
+ break;
+ } while (1);
+
+ return (reg & I2C_BER) ? 0 : 1;
+}
+
+static int mb862xx_i2c_do_address(struct i2c_adapter *adap, int addr)
+{
+ struct mb862xxfb_par *par = adap->algo_data;
+
+ outreg(i2c, GC_I2C_DAR, addr);
+ outreg(i2c, GC_I2C_CCR, I2C_CLOCK_AND_ENABLE);
+ outreg(i2c, GC_I2C_BCR, par->i2c_rs ? I2C_REPEATED_START : I2C_START);
+ if (!mb862xx_i2c_wait_event(adap))
+ return -EIO;
+ par->i2c_rs = !(inreg(i2c, GC_I2C_BSR) & I2C_LRB);
+ return par->i2c_rs;
+}
+
+static int mb862xx_i2c_write_byte(struct i2c_adapter *adap, u8 byte)
+{
+ struct mb862xxfb_par *par = adap->algo_data;
+
+ outreg(i2c, GC_I2C_DAR, byte);
+ outreg(i2c, GC_I2C_BCR, I2C_START);
+ if (!mb862xx_i2c_wait_event(adap))
+ return -EIO;
+ return !(inreg(i2c, GC_I2C_BSR) & I2C_LRB);
+}
+
+static int mb862xx_i2c_read_byte(struct i2c_adapter *adap, u8 *byte, int last)
+{
+ struct mb862xxfb_par *par = adap->algo_data;
+
+ outreg(i2c, GC_I2C_BCR, I2C_START | (last ? 0 : I2C_ACK));
+ if (!mb862xx_i2c_wait_event(adap))
+ return 0;
+ *byte = inreg(i2c, GC_I2C_DAR);
+ return 1;
+}
+
+void mb862xx_i2c_stop(struct i2c_adapter *adap)
+{
+ struct mb862xxfb_par *par = adap->algo_data;
+
+ outreg(i2c, GC_I2C_BCR, I2C_STOP);
+ outreg(i2c, GC_I2C_CCR, I2C_DISABLE);
+ par->i2c_rs = 0;
+}
+
+static int mb862xx_i2c_read(struct i2c_adapter *adap, struct i2c_msg *m)
+{
+ int i, ret = 0;
+ int last = m->len - 1;
+
+ for (i = 0; i < m->len; i++) {
+ if (!mb862xx_i2c_read_byte(adap, &m->buf[i], i == last)) {
+ ret = -EIO;
+ break;
+ }
+ }
+ return ret;
+}
+
+static int mb862xx_i2c_write(struct i2c_adapter *adap, struct i2c_msg *m)
+{
+ int i, ret = 0;
+
+ for (i = 0; i < m->len; i++) {
+ if (!mb862xx_i2c_write_byte(adap, m->buf[i])) {
+ ret = -EIO;
+ break;
+ }
+ }
+ return ret;
+}
+
+static int mb862xx_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
+ int num)
+{
+ struct mb862xxfb_par *par = adap->algo_data;
+ struct i2c_msg *m;
+ int addr;
+ int i = 0, err = 0;
+
+ dev_dbg(par->dev, "%s: %d msgs\n", __func__, num);
+
+ for (i = 0; i < num; i++) {
+ m = &msgs[i];
+ if (!m->len) {
+ dev_dbg(par->dev, "%s: null msgs\n", __func__);
+ continue;
+ }
+ addr = m->addr;
+ if (m->flags & I2C_M_RD)
+ addr |= 1;
+
+ err = mb862xx_i2c_do_address(adap, addr);
+ if (err < 0)
+ break;
+ if (m->flags & I2C_M_RD)
+ err = mb862xx_i2c_read(adap, m);
+ else
+ err = mb862xx_i2c_write(adap, m);
+ }
+
+ if (i)
+ mb862xx_i2c_stop(adap);
+
+ return (err < 0) ? err : i;
+}
+
+static u32 mb862xx_func(struct i2c_adapter *adap)
+{
+ return I2C_FUNC_SMBUS_BYTE_DATA;
+}
+
+static const struct i2c_algorithm mb862xx_algo = {
+ .master_xfer = mb862xx_xfer,
+ .functionality = mb862xx_func,
+};
+
+static struct i2c_adapter mb862xx_i2c_adapter = {
+ .name = "MB862xx I2C adapter",
+ .algo = &mb862xx_algo,
+ .owner = THIS_MODULE,
+};
+
+int mb862xx_i2c_init(struct mb862xxfb_par *par)
+{
+ int ret;
+
+ mb862xx_i2c_adapter.algo_data = par;
+ par->adap = &mb862xx_i2c_adapter;
+
+ ret = i2c_add_adapter(par->adap);
+ if (ret < 0) {
+ dev_err(par->dev, "failed to add %s\n",
+ mb862xx_i2c_adapter.name);
+ }
+ return ret;
+}
+
+void mb862xx_i2c_exit(struct mb862xxfb_par *par)
+{
+ if (par->adap) {
+ i2c_del_adapter(par->adap);
+ par->adap = NULL;
+ }
+}
diff --git a/drivers/video/mb862xx/mb862xx_reg.h b/drivers/video/mb862xx/mb862xx_reg.h
index 2ba65e1..9df48b8 100644
--- a/drivers/video/mb862xx/mb862xx_reg.h
+++ b/drivers/video/mb862xx/mb862xx_reg.h
@@ -5,11 +5,8 @@
#ifndef _MB862XX_REG_H
#define _MB862XX_REG_H
-#ifdef MB862XX_MMIO_BOTTOM
-#define MB862XX_MMIO_BASE 0x03fc0000
-#else
#define MB862XX_MMIO_BASE 0x01fc0000
-#endif
+#define MB862XX_MMIO_HIGH_BASE 0x03fc0000
#define MB862XX_I2C_BASE 0x0000c000
#define MB862XX_DISP_BASE 0x00010000
#define MB862XX_CAP_BASE 0x00018000
@@ -23,6 +20,7 @@
#define GC_IMASK 0x00000024
#define GC_SRST 0x0000002c
#define GC_CCF 0x00000038
+#define GC_RSW 0x0000005c
#define GC_CID 0x000000f0
#define GC_REVISION 0x00000084
@@ -53,10 +51,16 @@
#define GC_L0OA0 0x00000024
#define GC_L0DA0 0x00000028
#define GC_L0DY_L0DX 0x0000002c
+#define GC_L1M 0x00000030
+#define GC_L1DA 0x00000034
#define GC_DCM1 0x00000100
#define GC_L0EM 0x00000110
#define GC_L0WY_L0WX 0x00000114
#define GC_L0WH_L0WW 0x00000118
+#define GC_L1EM 0x00000120
+#define GC_L1WY_L1WX 0x00000124
+#define GC_L1WH_L1WW 0x00000128
+#define GC_DLS 0x00000180
#define GC_DCM2 0x00000104
#define GC_DCM3 0x00000108
#define GC_CPM_CUTC 0x000000a0
@@ -68,6 +72,11 @@
#define GC_CPM_CEN0 0x00100000
#define GC_CPM_CEN1 0x00200000
+#define GC_DCM1_DEN 0x80000000
+#define GC_DCM1_L1E 0x00020000
+#define GC_L1M_16 0x80000000
+#define GC_L1M_YC 0x40000000
+#define GC_L1M_CS 0x20000000
#define GC_DCM01_ESY 0x00000004
#define GC_DCM01_SC 0x00003f00
@@ -79,9 +88,50 @@
#define GC_L0M_L0C_16 0x80000000
#define GC_L0EM_L0EC_24 0x40000000
#define GC_L0M_L0W_UNIT 64
+#define GC_L1EM_DM 0x02000000
#define GC_DISP_REFCLK_400 400
+/* I2C */
+#define GC_I2C_BSR 0x00000000 /* BSR */
+#define GC_I2C_BCR 0x00000004 /* BCR */
+#define GC_I2C_CCR 0x00000008 /* CCR */
+#define GC_I2C_ADR 0x0000000C /* ADR */
+#define GC_I2C_DAR 0x00000010 /* DAR */
+
+#define I2C_DISABLE 0x00000000
+#define I2C_STOP 0x00000000
+#define I2C_START 0x00000010
+#define I2C_REPEATED_START 0x00000030
+#define I2C_CLOCK_AND_ENABLE 0x0000003f
+#define I2C_READY 0x01
+#define I2C_INT 0x01
+#define I2C_INTE 0x02
+#define I2C_ACK 0x08
+#define I2C_BER 0x80
+#define I2C_BEIE 0x40
+#define I2C_TRX 0x80
+#define I2C_LRB 0x10
+
+/* Capture registers and bits */
+#define GC_CAP_VCM 0x00000000
+#define GC_CAP_CSC 0x00000004
+#define GC_CAP_VCS 0x00000008
+#define GC_CAP_CBM 0x00000010
+#define GC_CAP_CBOA 0x00000014
+#define GC_CAP_CBLA 0x00000018
+#define GC_CAP_IMG_START 0x0000001C
+#define GC_CAP_IMG_END 0x00000020
+#define GC_CAP_CMSS 0x00000048
+#define GC_CAP_CMDS 0x0000004C
+
+#define GC_VCM_VIE 0x80000000
+#define GC_VCM_CM 0x03000000
+#define GC_VCM_VS_PAL 0x00000002
+#define GC_CBM_OO 0x80000000
+#define GC_CBM_HRV 0x00000010
+#define GC_CBM_CBST 0x00000001
+
/* Carmine specific */
#define MB86297_DRAW_BASE 0x00020000
#define MB86297_DISP0_BASE 0x00100000
diff --git a/drivers/video/mb862xx/mb862xxfb.c b/drivers/video/mb862xx/mb862xxfb.c
deleted file mode 100644
index c76e663..0000000
--- a/drivers/video/mb862xx/mb862xxfb.c
+++ /dev/null
@@ -1,1063 +0,0 @@
-/*
- * drivers/mb862xx/mb862xxfb.c
- *
- * Fujitsu Carmine/Coral-P(A)/Lime framebuffer driver
- *
- * (C) 2008 Anatolij Gustschin <agust@denx.de>
- * DENX Software Engineering
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#undef DEBUG
-
-#include <linux/fb.h>
-#include <linux/delay.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/pci.h>
-#if defined(CONFIG_OF)
-#include <linux/of_platform.h>
-#endif
-#include "mb862xxfb.h"
-#include "mb862xx_reg.h"
-
-#define NR_PALETTE 256
-#define MB862XX_MEM_SIZE 0x1000000
-#define CORALP_MEM_SIZE 0x4000000
-#define CARMINE_MEM_SIZE 0x8000000
-#define DRV_NAME "mb862xxfb"
-
-#if defined(CONFIG_SOCRATES)
-static struct mb862xx_gc_mode socrates_gc_mode = {
- /* Mode for Prime View PM070WL4 TFT LCD Panel */
- { "800x480", 45, 800, 480, 40000, 86, 42, 33, 10, 128, 2, 0, 0, 0 },
- /* 16 bits/pixel, 16MB, 133MHz, SDRAM memory mode value */
- 16, 0x1000000, GC_CCF_COT_133, 0x4157ba63
-};
-#endif
-
-/* Helpers */
-static inline int h_total(struct fb_var_screeninfo *var)
-{
- return var->xres + var->left_margin +
- var->right_margin + var->hsync_len;
-}
-
-static inline int v_total(struct fb_var_screeninfo *var)
-{
- return var->yres + var->upper_margin +
- var->lower_margin + var->vsync_len;
-}
-
-static inline int hsp(struct fb_var_screeninfo *var)
-{
- return var->xres + var->right_margin - 1;
-}
-
-static inline int vsp(struct fb_var_screeninfo *var)
-{
- return var->yres + var->lower_margin - 1;
-}
-
-static inline int d_pitch(struct fb_var_screeninfo *var)
-{
- return var->xres * var->bits_per_pixel / 8;
-}
-
-static inline unsigned int chan_to_field(unsigned int chan,
- struct fb_bitfield *bf)
-{
- chan &= 0xffff;
- chan >>= 16 - bf->length;
- return chan << bf->offset;
-}
-
-static int mb862xxfb_setcolreg(unsigned regno,
- unsigned red, unsigned green, unsigned blue,
- unsigned transp, struct fb_info *info)
-{
- struct mb862xxfb_par *par = info->par;
- unsigned int val;
-
- switch (info->fix.visual) {
- case FB_VISUAL_TRUECOLOR:
- if (regno < 16) {
- val = chan_to_field(red, &info->var.red);
- val |= chan_to_field(green, &info->var.green);
- val |= chan_to_field(blue, &info->var.blue);
- par->pseudo_palette[regno] = val;
- }
- break;
- case FB_VISUAL_PSEUDOCOLOR:
- if (regno < 256) {
- val = (red >> 8) << 16;
- val |= (green >> 8) << 8;
- val |= blue >> 8;
- outreg(disp, GC_L0PAL0 + (regno * 4), val);
- }
- break;
- default:
- return 1; /* unsupported type */
- }
- return 0;
-}
-
-static int mb862xxfb_check_var(struct fb_var_screeninfo *var,
- struct fb_info *fbi)
-{
- unsigned long tmp;
-
- if (fbi->dev)
- dev_dbg(fbi->dev, "%s\n", __func__);
-
- /* check if these values fit into the registers */
- if (var->hsync_len > 255 || var->vsync_len > 255)
- return -EINVAL;
-
- if ((var->xres + var->right_margin) >= 4096)
- return -EINVAL;
-
- if ((var->yres + var->lower_margin) > 4096)
- return -EINVAL;
-
- if (h_total(var) > 4096 || v_total(var) > 4096)
- return -EINVAL;
-
- if (var->xres_virtual > 4096 || var->yres_virtual > 4096)
- return -EINVAL;
-
- if (var->bits_per_pixel <= 8)
- var->bits_per_pixel = 8;
- else if (var->bits_per_pixel <= 16)
- var->bits_per_pixel = 16;
- else if (var->bits_per_pixel <= 32)
- var->bits_per_pixel = 32;
-
- /*
- * can cope with 8,16 or 24/32bpp if resulting
- * pitch is divisible by 64 without remainder
- */
- if (d_pitch(&fbi->var) % GC_L0M_L0W_UNIT) {
- int r;
-
- var->bits_per_pixel = 0;
- do {
- var->bits_per_pixel += 8;
- r = d_pitch(&fbi->var) % GC_L0M_L0W_UNIT;
- } while (r && var->bits_per_pixel <= 32);
-
- if (d_pitch(&fbi->var) % GC_L0M_L0W_UNIT)
- return -EINVAL;
- }
-
- /* line length is going to be 128 bit aligned */
- tmp = (var->xres * var->bits_per_pixel) / 8;
- if ((tmp & 15) != 0)
- return -EINVAL;
-
- /* set r/g/b positions and validate bpp */
- switch (var->bits_per_pixel) {
- case 8:
- var->red.length = var->bits_per_pixel;
- var->green.length = var->bits_per_pixel;
- var->blue.length = var->bits_per_pixel;
- var->red.offset = 0;
- var->green.offset = 0;
- var->blue.offset = 0;
- var->transp.length = 0;
- break;
- case 16:
- var->red.length = 5;
- var->green.length = 5;
- var->blue.length = 5;
- var->red.offset = 10;
- var->green.offset = 5;
- var->blue.offset = 0;
- var->transp.length = 0;
- break;
- case 24:
- case 32:
- var->transp.length = 8;
- var->red.length = 8;
- var->green.length = 8;
- var->blue.length = 8;
- var->transp.offset = 24;
- var->red.offset = 16;
- var->green.offset = 8;
- var->blue.offset = 0;
- break;
- default:
- return -EINVAL;
- }
- return 0;
-}
-
-/*
- * set display parameters
- */
-static int mb862xxfb_set_par(struct fb_info *fbi)
-{
- struct mb862xxfb_par *par = fbi->par;
- unsigned long reg, sc;
-
- dev_dbg(par->dev, "%s\n", __func__);
- if (par->type == BT_CORALP)
- mb862xxfb_init_accel(fbi, fbi->var.xres);
-
- if (par->pre_init)
- return 0;
-
- /* disp off */
- reg = inreg(disp, GC_DCM1);
- reg &= ~GC_DCM01_DEN;
- outreg(disp, GC_DCM1, reg);
-
- /* set display reference clock div. */
- sc = par->refclk / (1000000 / fbi->var.pixclock) - 1;
- reg = inreg(disp, GC_DCM1);
- reg &= ~(GC_DCM01_CKS | GC_DCM01_RESV | GC_DCM01_SC);
- reg |= sc << 8;
- outreg(disp, GC_DCM1, reg);
- dev_dbg(par->dev, "SC 0x%lx\n", sc);
-
- /* disp dimension, format */
- reg = pack(d_pitch(&fbi->var) / GC_L0M_L0W_UNIT,
- (fbi->var.yres - 1));
- if (fbi->var.bits_per_pixel == 16)
- reg |= GC_L0M_L0C_16;
- outreg(disp, GC_L0M, reg);
-
- if (fbi->var.bits_per_pixel == 32) {
- reg = inreg(disp, GC_L0EM);
- outreg(disp, GC_L0EM, reg | GC_L0EM_L0EC_24);
- }
- outreg(disp, GC_WY_WX, 0);
- reg = pack(fbi->var.yres - 1, fbi->var.xres);
- outreg(disp, GC_WH_WW, reg);
- outreg(disp, GC_L0OA0, 0);
- outreg(disp, GC_L0DA0, 0);
- outreg(disp, GC_L0DY_L0DX, 0);
- outreg(disp, GC_L0WY_L0WX, 0);
- outreg(disp, GC_L0WH_L0WW, reg);
-
- /* both HW-cursors off */
- reg = inreg(disp, GC_CPM_CUTC);
- reg &= ~(GC_CPM_CEN0 | GC_CPM_CEN1);
- outreg(disp, GC_CPM_CUTC, reg);
-
- /* timings */
- reg = pack(fbi->var.xres - 1, fbi->var.xres - 1);
- outreg(disp, GC_HDB_HDP, reg);
- reg = pack((fbi->var.yres - 1), vsp(&fbi->var));
- outreg(disp, GC_VDP_VSP, reg);
- reg = ((fbi->var.vsync_len - 1) << 24) |
- pack((fbi->var.hsync_len - 1), hsp(&fbi->var));
- outreg(disp, GC_VSW_HSW_HSP, reg);
- outreg(disp, GC_HTP, pack(h_total(&fbi->var) - 1, 0));
- outreg(disp, GC_VTR, pack(v_total(&fbi->var) - 1, 0));
-
- /* display on */
- reg = inreg(disp, GC_DCM1);
- reg |= GC_DCM01_DEN | GC_DCM01_L0E;
- reg &= ~GC_DCM01_ESY;
- outreg(disp, GC_DCM1, reg);
- return 0;
-}
-
-static int mb862xxfb_pan(struct fb_var_screeninfo *var,
- struct fb_info *info)
-{
- struct mb862xxfb_par *par = info->par;
- unsigned long reg;
-
- reg = pack(var->yoffset, var->xoffset);
- outreg(disp, GC_L0WY_L0WX, reg);
-
- reg = pack(var->yres_virtual, var->xres_virtual);
- outreg(disp, GC_L0WH_L0WW, reg);
- return 0;
-}
-
-static int mb862xxfb_blank(int mode, struct fb_info *fbi)
-{
- struct mb862xxfb_par *par = fbi->par;
- unsigned long reg;
-
- dev_dbg(fbi->dev, "blank mode=%d\n", mode);
-
- switch (mode) {
- case FB_BLANK_POWERDOWN:
- reg = inreg(disp, GC_DCM1);
- reg &= ~GC_DCM01_DEN;
- outreg(disp, GC_DCM1, reg);
- break;
- case FB_BLANK_UNBLANK:
- reg = inreg(disp, GC_DCM1);
- reg |= GC_DCM01_DEN;
- outreg(disp, GC_DCM1, reg);
- break;
- case FB_BLANK_NORMAL:
- case FB_BLANK_VSYNC_SUSPEND:
- case FB_BLANK_HSYNC_SUSPEND:
- default:
- return 1;
- }
- return 0;
-}
-
-/* framebuffer ops */
-static struct fb_ops mb862xxfb_ops = {
- .owner = THIS_MODULE,
- .fb_check_var = mb862xxfb_check_var,
- .fb_set_par = mb862xxfb_set_par,
- .fb_setcolreg = mb862xxfb_setcolreg,
- .fb_blank = mb862xxfb_blank,
- .fb_pan_display = mb862xxfb_pan,
- .fb_fillrect = cfb_fillrect,
- .fb_copyarea = cfb_copyarea,
- .fb_imageblit = cfb_imageblit,
-};
-
-/* initialize fb_info data */
-static int mb862xxfb_init_fbinfo(struct fb_info *fbi)
-{
- struct mb862xxfb_par *par = fbi->par;
- struct mb862xx_gc_mode *mode = par->gc_mode;
- unsigned long reg;
-
- fbi->fbops = &mb862xxfb_ops;
- fbi->pseudo_palette = par->pseudo_palette;
- fbi->screen_base = par->fb_base;
- fbi->screen_size = par->mapped_vram;
-
- strcpy(fbi->fix.id, DRV_NAME);
- fbi->fix.smem_start = (unsigned long)par->fb_base_phys;
- fbi->fix.smem_len = par->mapped_vram;
- fbi->fix.mmio_start = (unsigned long)par->mmio_base_phys;
- fbi->fix.mmio_len = par->mmio_len;
- fbi->fix.accel = FB_ACCEL_NONE;
- fbi->fix.type = FB_TYPE_PACKED_PIXELS;
- fbi->fix.type_aux = 0;
- fbi->fix.xpanstep = 1;
- fbi->fix.ypanstep = 1;
- fbi->fix.ywrapstep = 0;
-
- reg = inreg(disp, GC_DCM1);
- if (reg & GC_DCM01_DEN && reg & GC_DCM01_L0E) {
- /* get the disp mode from active display cfg */
- unsigned long sc = ((reg & GC_DCM01_SC) >> 8) + 1;
- unsigned long hsp, vsp, ht, vt;
-
- dev_dbg(par->dev, "using bootloader's disp. mode\n");
- fbi->var.pixclock = (sc * 1000000) / par->refclk;
- fbi->var.xres = (inreg(disp, GC_HDB_HDP) & 0x0fff) + 1;
- reg = inreg(disp, GC_VDP_VSP);
- fbi->var.yres = ((reg >> 16) & 0x0fff) + 1;
- vsp = (reg & 0x0fff) + 1;
- fbi->var.xres_virtual = fbi->var.xres;
- fbi->var.yres_virtual = fbi->var.yres;
- reg = inreg(disp, GC_L0EM);
- if (reg & GC_L0EM_L0EC_24) {
- fbi->var.bits_per_pixel = 32;
- } else {
- reg = inreg(disp, GC_L0M);
- if (reg & GC_L0M_L0C_16)
- fbi->var.bits_per_pixel = 16;
- else
- fbi->var.bits_per_pixel = 8;
- }
- reg = inreg(disp, GC_VSW_HSW_HSP);
- fbi->var.hsync_len = ((reg & 0xff0000) >> 16) + 1;
- fbi->var.vsync_len = ((reg & 0x3f000000) >> 24) + 1;
- hsp = (reg & 0xffff) + 1;
- ht = ((inreg(disp, GC_HTP) & 0xfff0000) >> 16) + 1;
- fbi->var.right_margin = hsp - fbi->var.xres;
- fbi->var.left_margin = ht - hsp - fbi->var.hsync_len;
- vt = ((inreg(disp, GC_VTR) & 0xfff0000) >> 16) + 1;
- fbi->var.lower_margin = vsp - fbi->var.yres;
- fbi->var.upper_margin = vt - vsp - fbi->var.vsync_len;
- } else if (mode) {
- dev_dbg(par->dev, "using supplied mode\n");
- fb_videomode_to_var(&fbi->var, (struct fb_videomode *)mode);
- fbi->var.bits_per_pixel = mode->def_bpp ? mode->def_bpp : 8;
- } else {
- int ret;
-
- ret = fb_find_mode(&fbi->var, fbi, "640x480-16@60",
- NULL, 0, NULL, 16);
- if (ret == 0 || ret == 4) {
- dev_err(par->dev,
- "failed to get initial mode\n");
- return -EINVAL;
- }
- }
-
- fbi->var.xoffset = 0;
- fbi->var.yoffset = 0;
- fbi->var.grayscale = 0;
- fbi->var.nonstd = 0;
- fbi->var.height = -1;
- fbi->var.width = -1;
- fbi->var.accel_flags = 0;
- fbi->var.vmode = FB_VMODE_NONINTERLACED;
- fbi->var.activate = FB_ACTIVATE_NOW;
- fbi->flags = FBINFO_DEFAULT |
-#ifdef __BIG_ENDIAN
- FBINFO_FOREIGN_ENDIAN |
-#endif
- FBINFO_HWACCEL_XPAN |
- FBINFO_HWACCEL_YPAN;
-
- /* check and possibly fix bpp */
- if ((fbi->fbops->fb_check_var)(&fbi->var, fbi))
- dev_err(par->dev, "check_var() failed on initial setup?\n");
-
- fbi->fix.visual = fbi->var.bits_per_pixel == 8 ?
- FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
- fbi->fix.line_length = (fbi->var.xres_virtual *
- fbi->var.bits_per_pixel) / 8;
- return 0;
-}
-
-/*
- * show some display controller and cursor registers
- */
-static ssize_t mb862xxfb_show_dispregs(struct device *dev,
- struct device_attribute *attr, char *buf)
-{
- struct fb_info *fbi = dev_get_drvdata(dev);
- struct mb862xxfb_par *par = fbi->par;
- char *ptr = buf;
- unsigned int reg;
-
- for (reg = GC_DCM0; reg <= GC_L0DY_L0DX; reg += 4)
- ptr += sprintf(ptr, "%08x = %08x\n",
- reg, inreg(disp, reg));
-
- for (reg = GC_CPM_CUTC; reg <= GC_CUY1_CUX1; reg += 4)
- ptr += sprintf(ptr, "%08x = %08x\n",
- reg, inreg(disp, reg));
-
- for (reg = GC_DCM1; reg <= GC_L0WH_L0WW; reg += 4)
- ptr += sprintf(ptr, "%08x = %08x\n",
- reg, inreg(disp, reg));
-
- for (reg = 0x400; reg <= 0x410; reg += 4)
- ptr += sprintf(ptr, "geo %08x = %08x\n",
- reg, inreg(geo, reg));
-
- for (reg = 0x400; reg <= 0x410; reg += 4)
- ptr += sprintf(ptr, "draw %08x = %08x\n",
- reg, inreg(draw, reg));
-
- for (reg = 0x440; reg <= 0x450; reg += 4)
- ptr += sprintf(ptr, "draw %08x = %08x\n",
- reg, inreg(draw, reg));
-
- return ptr - buf;
-}
-
-static DEVICE_ATTR(dispregs, 0444, mb862xxfb_show_dispregs, NULL);
-
-irqreturn_t mb862xx_intr(int irq, void *dev_id)
-{
- struct mb862xxfb_par *par = (struct mb862xxfb_par *) dev_id;
- unsigned long reg_ist, mask;
-
- if (!par)
- return IRQ_NONE;
-
- if (par->type == BT_CARMINE) {
- /* Get Interrupt Status */
- reg_ist = inreg(ctrl, GC_CTRL_STATUS);
- mask = inreg(ctrl, GC_CTRL_INT_MASK);
- if (reg_ist == 0)
- return IRQ_HANDLED;
-
- reg_ist &= mask;
- if (reg_ist == 0)
- return IRQ_HANDLED;
-
- /* Clear interrupt status */
- outreg(ctrl, 0x0, reg_ist);
- } else {
- /* Get status */
- reg_ist = inreg(host, GC_IST);
- mask = inreg(host, GC_IMASK);
-
- reg_ist &= mask;
- if (reg_ist == 0)
- return IRQ_HANDLED;
-
- /* Clear status */
- outreg(host, GC_IST, ~reg_ist);
- }
- return IRQ_HANDLED;
-}
-
-#if defined(CONFIG_FB_MB862XX_LIME)
-/*
- * GDC (Lime, Coral(B/Q), Mint, ...) on host bus
- */
-static int mb862xx_gdc_init(struct mb862xxfb_par *par)
-{
- unsigned long ccf, mmr;
- unsigned long ver, rev;
-
- if (!par)
- return -ENODEV;
-
-#if defined(CONFIG_FB_PRE_INIT_FB)
- par->pre_init = 1;
-#endif
- par->host = par->mmio_base;
- par->i2c = par->mmio_base + MB862XX_I2C_BASE;
- par->disp = par->mmio_base + MB862XX_DISP_BASE;
- par->cap = par->mmio_base + MB862XX_CAP_BASE;
- par->draw = par->mmio_base + MB862XX_DRAW_BASE;
- par->geo = par->mmio_base + MB862XX_GEO_BASE;
- par->pio = par->mmio_base + MB862XX_PIO_BASE;
-
- par->refclk = GC_DISP_REFCLK_400;
-
- ver = inreg(host, GC_CID);
- rev = inreg(pio, GC_REVISION);
- if ((ver == 0x303) && (rev & 0xffffff00) == 0x20050100) {
- dev_info(par->dev, "Fujitsu Lime v1.%d found\n",
- (int)rev & 0xff);
- par->type = BT_LIME;
- ccf = par->gc_mode ? par->gc_mode->ccf : GC_CCF_COT_100;
- mmr = par->gc_mode ? par->gc_mode->mmr : 0x414fb7f2;
- } else {
- dev_info(par->dev, "? GDC, CID/Rev.: 0x%lx/0x%lx \n", ver, rev);
- return -ENODEV;
- }
-
- if (!par->pre_init) {
- outreg(host, GC_CCF, ccf);
- udelay(200);
- outreg(host, GC_MMR, mmr);
- udelay(10);
- }
-
- /* interrupt status */
- outreg(host, GC_IST, 0);
- outreg(host, GC_IMASK, GC_INT_EN);
- return 0;
-}
-
-static int __devinit of_platform_mb862xx_probe(struct platform_device *ofdev)
-{
- struct device_node *np = ofdev->dev.of_node;
- struct device *dev = &ofdev->dev;
- struct mb862xxfb_par *par;
- struct fb_info *info;
- struct resource res;
- resource_size_t res_size;
- unsigned long ret = -ENODEV;
-
- if (of_address_to_resource(np, 0, &res)) {
- dev_err(dev, "Invalid address\n");
- return -ENXIO;
- }
-
- info = framebuffer_alloc(sizeof(struct mb862xxfb_par), dev);
- if (info == NULL) {
- dev_err(dev, "cannot allocate framebuffer\n");
- return -ENOMEM;
- }
-
- par = info->par;
- par->info = info;
- par->dev = dev;
-
- par->irq = irq_of_parse_and_map(np, 0);
- if (par->irq == NO_IRQ) {
- dev_err(dev, "failed to map irq\n");
- ret = -ENODEV;
- goto fbrel;
- }
-
- res_size = 1 + res.end - res.start;
- par->res = request_mem_region(res.start, res_size, DRV_NAME);
- if (par->res == NULL) {
- dev_err(dev, "Cannot claim framebuffer/mmio\n");
- ret = -ENXIO;
- goto irqdisp;
- }
-
-#if defined(CONFIG_SOCRATES)
- par->gc_mode = &socrates_gc_mode;
-#endif
-
- par->fb_base_phys = res.start;
- par->mmio_base_phys = res.start + MB862XX_MMIO_BASE;
- par->mmio_len = MB862XX_MMIO_SIZE;
- if (par->gc_mode)
- par->mapped_vram = par->gc_mode->max_vram;
- else
- par->mapped_vram = MB862XX_MEM_SIZE;
-
- par->fb_base = ioremap(par->fb_base_phys, par->mapped_vram);
- if (par->fb_base == NULL) {
- dev_err(dev, "Cannot map framebuffer\n");
- goto rel_reg;
- }
-
- par->mmio_base = ioremap(par->mmio_base_phys, par->mmio_len);
- if (par->mmio_base == NULL) {
- dev_err(dev, "Cannot map registers\n");
- goto fb_unmap;
- }
-
- dev_dbg(dev, "fb phys 0x%llx 0x%lx\n",
- (u64)par->fb_base_phys, (ulong)par->mapped_vram);
- dev_dbg(dev, "mmio phys 0x%llx 0x%lx, (irq = %d)\n",
- (u64)par->mmio_base_phys, (ulong)par->mmio_len, par->irq);
-
- if (mb862xx_gdc_init(par))
- goto io_unmap;
-
- if (request_irq(par->irq, mb862xx_intr, IRQF_DISABLED,
- DRV_NAME, (void *)par)) {
- dev_err(dev, "Cannot request irq\n");
- goto io_unmap;
- }
-
- mb862xxfb_init_fbinfo(info);
-
- if (fb_alloc_cmap(&info->cmap, NR_PALETTE, 0) < 0) {
- dev_err(dev, "Could not allocate cmap for fb_info.\n");
- goto free_irq;
- }
-
- if ((info->fbops->fb_set_par)(info))
- dev_err(dev, "set_var() failed on initial setup?\n");
-
- if (register_framebuffer(info)) {
- dev_err(dev, "failed to register framebuffer\n");
- goto rel_cmap;
- }
-
- dev_set_drvdata(dev, info);
-
- if (device_create_file(dev, &dev_attr_dispregs))
- dev_err(dev, "Can't create sysfs regdump file\n");
- return 0;
-
-rel_cmap:
- fb_dealloc_cmap(&info->cmap);
-free_irq:
- outreg(host, GC_IMASK, 0);
- free_irq(par->irq, (void *)par);
-io_unmap:
- iounmap(par->mmio_base);
-fb_unmap:
- iounmap(par->fb_base);
-rel_reg:
- release_mem_region(res.start, res_size);
-irqdisp:
- irq_dispose_mapping(par->irq);
-fbrel:
- dev_set_drvdata(dev, NULL);
- framebuffer_release(info);
- return ret;
-}
-
-static int __devexit of_platform_mb862xx_remove(struct platform_device *ofdev)
-{
- struct fb_info *fbi = dev_get_drvdata(&ofdev->dev);
- struct mb862xxfb_par *par = fbi->par;
- resource_size_t res_size = 1 + par->res->end - par->res->start;
- unsigned long reg;
-
- dev_dbg(fbi->dev, "%s release\n", fbi->fix.id);
-
- /* display off */
- reg = inreg(disp, GC_DCM1);
- reg &= ~(GC_DCM01_DEN | GC_DCM01_L0E);
- outreg(disp, GC_DCM1, reg);
-
- /* disable interrupts */
- outreg(host, GC_IMASK, 0);
-
- free_irq(par->irq, (void *)par);
- irq_dispose_mapping(par->irq);
-
- device_remove_file(&ofdev->dev, &dev_attr_dispregs);
-
- unregister_framebuffer(fbi);
- fb_dealloc_cmap(&fbi->cmap);
-
- iounmap(par->mmio_base);
- iounmap(par->fb_base);
-
- dev_set_drvdata(&ofdev->dev, NULL);
- release_mem_region(par->res->start, res_size);
- framebuffer_release(fbi);
- return 0;
-}
-
-/*
- * common types
- */
-static struct of_device_id __devinitdata of_platform_mb862xx_tbl[] = {
- { .compatible = "fujitsu,MB86276", },
- { .compatible = "fujitsu,lime", },
- { .compatible = "fujitsu,MB86277", },
- { .compatible = "fujitsu,mint", },
- { .compatible = "fujitsu,MB86293", },
- { .compatible = "fujitsu,MB86294", },
- { .compatible = "fujitsu,coral", },
- { /* end */ }
-};
-
-static struct platform_driver of_platform_mb862xxfb_driver = {
- .driver = {
- .name = DRV_NAME,
- .owner = THIS_MODULE,
- .of_match_table = of_platform_mb862xx_tbl,
- },
- .probe = of_platform_mb862xx_probe,
- .remove = __devexit_p(of_platform_mb862xx_remove),
-};
-#endif
-
-#if defined(CONFIG_FB_MB862XX_PCI_GDC)
-static int coralp_init(struct mb862xxfb_par *par)
-{
- int cn, ver;
-
- par->host = par->mmio_base;
- par->i2c = par->mmio_base + MB862XX_I2C_BASE;
- par->disp = par->mmio_base + MB862XX_DISP_BASE;
- par->cap = par->mmio_base + MB862XX_CAP_BASE;
- par->draw = par->mmio_base + MB862XX_DRAW_BASE;
- par->geo = par->mmio_base + MB862XX_GEO_BASE;
- par->pio = par->mmio_base + MB862XX_PIO_BASE;
-
- par->refclk = GC_DISP_REFCLK_400;
-
- ver = inreg(host, GC_CID);
- cn = (ver & GC_CID_CNAME_MSK) >> 8;
- ver = ver & GC_CID_VERSION_MSK;
- if (cn == 3) {
- dev_info(par->dev, "Fujitsu Coral-%s GDC Rev.%d found\n",\
- (ver == 6) ? "P" : (ver == 8) ? "PA" : "?",
- par->pdev->revision);
- outreg(host, GC_CCF, GC_CCF_CGE_166 | GC_CCF_COT_133);
- udelay(200);
- outreg(host, GC_MMR, GC_MMR_CORALP_EVB_VAL);
- udelay(10);
- /* Clear interrupt status */
- outreg(host, GC_IST, 0);
- } else {
- return -ENODEV;
- }
- return 0;
-}
-
-static int init_dram_ctrl(struct mb862xxfb_par *par)
-{
- unsigned long i = 0;
-
- /*
- * Set io mode first! Spec. says IC may be destroyed
- * if not set to SSTL2/LVCMOS before init.
- */
- outreg(dram_ctrl, GC_DCTL_IOCONT1_IOCONT0, GC_EVB_DCTL_IOCONT1_IOCONT0);
-
- /* DRAM init */
- outreg(dram_ctrl, GC_DCTL_MODE_ADD, GC_EVB_DCTL_MODE_ADD);
- outreg(dram_ctrl, GC_DCTL_SETTIME1_EMODE, GC_EVB_DCTL_SETTIME1_EMODE);
- outreg(dram_ctrl, GC_DCTL_REFRESH_SETTIME2,
- GC_EVB_DCTL_REFRESH_SETTIME2);
- outreg(dram_ctrl, GC_DCTL_RSV2_RSV1, GC_EVB_DCTL_RSV2_RSV1);
- outreg(dram_ctrl, GC_DCTL_DDRIF2_DDRIF1, GC_EVB_DCTL_DDRIF2_DDRIF1);
- outreg(dram_ctrl, GC_DCTL_RSV0_STATES, GC_EVB_DCTL_RSV0_STATES);
-
- /* DLL reset done? */
- while ((inreg(dram_ctrl, GC_DCTL_RSV0_STATES) & GC_DCTL_STATES_MSK)) {
- udelay(GC_DCTL_INIT_WAIT_INTERVAL);
- if (i++ > GC_DCTL_INIT_WAIT_CNT) {
- dev_err(par->dev, "VRAM init failed.\n");
- return -EINVAL;
- }
- }
- outreg(dram_ctrl, GC_DCTL_MODE_ADD, GC_EVB_DCTL_MODE_ADD_AFT_RST);
- outreg(dram_ctrl, GC_DCTL_RSV0_STATES, GC_EVB_DCTL_RSV0_STATES_AFT_RST);
- return 0;
-}
-
-static int carmine_init(struct mb862xxfb_par *par)
-{
- unsigned long reg;
-
- par->ctrl = par->mmio_base + MB86297_CTRL_BASE;
- par->i2c = par->mmio_base + MB86297_I2C_BASE;
- par->disp = par->mmio_base + MB86297_DISP0_BASE;
- par->disp1 = par->mmio_base + MB86297_DISP1_BASE;
- par->cap = par->mmio_base + MB86297_CAP0_BASE;
- par->cap1 = par->mmio_base + MB86297_CAP1_BASE;
- par->draw = par->mmio_base + MB86297_DRAW_BASE;
- par->dram_ctrl = par->mmio_base + MB86297_DRAMCTRL_BASE;
- par->wrback = par->mmio_base + MB86297_WRBACK_BASE;
-
- par->refclk = GC_DISP_REFCLK_533;
-
- /* warm up */
- reg = GC_CTRL_CLK_EN_DRAM | GC_CTRL_CLK_EN_2D3D | GC_CTRL_CLK_EN_DISP0;
- outreg(ctrl, GC_CTRL_CLK_ENABLE, reg);
-
- /* check for engine module revision */
- if (inreg(draw, GC_2D3D_REV) == GC_RE_REVISION)
- dev_info(par->dev, "Fujitsu Carmine GDC Rev.%d found\n",
- par->pdev->revision);
- else
- goto err_init;
-
- reg &= ~GC_CTRL_CLK_EN_2D3D;
- outreg(ctrl, GC_CTRL_CLK_ENABLE, reg);
-
- /* set up vram */
- if (init_dram_ctrl(par) < 0)
- goto err_init;
-
- outreg(ctrl, GC_CTRL_INT_MASK, 0);
- return 0;
-
-err_init:
- outreg(ctrl, GC_CTRL_CLK_ENABLE, 0);
- return -EINVAL;
-}
-
-static inline int mb862xx_pci_gdc_init(struct mb862xxfb_par *par)
-{
- switch (par->type) {
- case BT_CORALP:
- return coralp_init(par);
- case BT_CARMINE:
- return carmine_init(par);
- default:
- return -ENODEV;
- }
-}
-
-#define CHIP_ID(id) \
- { PCI_DEVICE(PCI_VENDOR_ID_FUJITSU_LIMITED, id) }
-
-static struct pci_device_id mb862xx_pci_tbl[] __devinitdata = {
- /* MB86295/MB86296 */
- CHIP_ID(PCI_DEVICE_ID_FUJITSU_CORALP),
- CHIP_ID(PCI_DEVICE_ID_FUJITSU_CORALPA),
- /* MB86297 */
- CHIP_ID(PCI_DEVICE_ID_FUJITSU_CARMINE),
- { 0, }
-};
-
-MODULE_DEVICE_TABLE(pci, mb862xx_pci_tbl);
-
-static int __devinit mb862xx_pci_probe(struct pci_dev *pdev,
- const struct pci_device_id *ent)
-{
- struct mb862xxfb_par *par;
- struct fb_info *info;
- struct device *dev = &pdev->dev;
- int ret;
-
- ret = pci_enable_device(pdev);
- if (ret < 0) {
- dev_err(dev, "Cannot enable PCI device\n");
- goto out;
- }
-
- info = framebuffer_alloc(sizeof(struct mb862xxfb_par), dev);
- if (!info) {
- dev_err(dev, "framebuffer alloc failed\n");
- ret = -ENOMEM;
- goto dis_dev;
- }
-
- par = info->par;
- par->info = info;
- par->dev = dev;
- par->pdev = pdev;
- par->irq = pdev->irq;
-
- ret = pci_request_regions(pdev, DRV_NAME);
- if (ret < 0) {
- dev_err(dev, "Cannot reserve region(s) for PCI device\n");
- goto rel_fb;
- }
-
- switch (pdev->device) {
- case PCI_DEVICE_ID_FUJITSU_CORALP:
- case PCI_DEVICE_ID_FUJITSU_CORALPA:
- par->fb_base_phys = pci_resource_start(par->pdev, 0);
- par->mapped_vram = CORALP_MEM_SIZE;
- par->mmio_base_phys = par->fb_base_phys + MB862XX_MMIO_BASE;
- par->mmio_len = MB862XX_MMIO_SIZE;
- par->type = BT_CORALP;
- break;
- case PCI_DEVICE_ID_FUJITSU_CARMINE:
- par->fb_base_phys = pci_resource_start(par->pdev, 2);
- par->mmio_base_phys = pci_resource_start(par->pdev, 3);
- par->mmio_len = pci_resource_len(par->pdev, 3);
- par->mapped_vram = CARMINE_MEM_SIZE;
- par->type = BT_CARMINE;
- break;
- default:
- /* should never occur */
- goto rel_reg;
- }
-
- par->fb_base = ioremap(par->fb_base_phys, par->mapped_vram);
- if (par->fb_base == NULL) {
- dev_err(dev, "Cannot map framebuffer\n");
- goto rel_reg;
- }
-
- par->mmio_base = ioremap(par->mmio_base_phys, par->mmio_len);
- if (par->mmio_base == NULL) {
- dev_err(dev, "Cannot map registers\n");
- ret = -EIO;
- goto fb_unmap;
- }
-
- dev_dbg(dev, "fb phys 0x%llx 0x%lx\n",
- (unsigned long long)par->fb_base_phys, (ulong)par->mapped_vram);
- dev_dbg(dev, "mmio phys 0x%llx 0x%lx\n",
- (unsigned long long)par->mmio_base_phys, (ulong)par->mmio_len);
-
- if (mb862xx_pci_gdc_init(par))
- goto io_unmap;
-
- if (request_irq(par->irq, mb862xx_intr, IRQF_DISABLED | IRQF_SHARED,
- DRV_NAME, (void *)par)) {
- dev_err(dev, "Cannot request irq\n");
- goto io_unmap;
- }
-
- mb862xxfb_init_fbinfo(info);
-
- if (fb_alloc_cmap(&info->cmap, NR_PALETTE, 0) < 0) {
- dev_err(dev, "Could not allocate cmap for fb_info.\n");
- ret = -ENOMEM;
- goto free_irq;
- }
-
- if ((info->fbops->fb_set_par)(info))
- dev_err(dev, "set_var() failed on initial setup?\n");
-
- ret = register_framebuffer(info);
- if (ret < 0) {
- dev_err(dev, "failed to register framebuffer\n");
- goto rel_cmap;
- }
-
- pci_set_drvdata(pdev, info);
-
- if (device_create_file(dev, &dev_attr_dispregs))
- dev_err(dev, "Can't create sysfs regdump file\n");
-
- if (par->type == BT_CARMINE)
- outreg(ctrl, GC_CTRL_INT_MASK, GC_CARMINE_INT_EN);
- else
- outreg(host, GC_IMASK, GC_INT_EN);
-
- return 0;
-
-rel_cmap:
- fb_dealloc_cmap(&info->cmap);
-free_irq:
- free_irq(par->irq, (void *)par);
-io_unmap:
- iounmap(par->mmio_base);
-fb_unmap:
- iounmap(par->fb_base);
-rel_reg:
- pci_release_regions(pdev);
-rel_fb:
- framebuffer_release(info);
-dis_dev:
- pci_disable_device(pdev);
-out:
- return ret;
-}
-
-static void __devexit mb862xx_pci_remove(struct pci_dev *pdev)
-{
- struct fb_info *fbi = pci_get_drvdata(pdev);
- struct mb862xxfb_par *par = fbi->par;
- unsigned long reg;
-
- dev_dbg(fbi->dev, "%s release\n", fbi->fix.id);
-
- /* display off */
- reg = inreg(disp, GC_DCM1);
- reg &= ~(GC_DCM01_DEN | GC_DCM01_L0E);
- outreg(disp, GC_DCM1, reg);
-
- if (par->type == BT_CARMINE) {
- outreg(ctrl, GC_CTRL_INT_MASK, 0);
- outreg(ctrl, GC_CTRL_CLK_ENABLE, 0);
- } else {
- outreg(host, GC_IMASK, 0);
- }
-
- device_remove_file(&pdev->dev, &dev_attr_dispregs);
-
- pci_set_drvdata(pdev, NULL);
- unregister_framebuffer(fbi);
- fb_dealloc_cmap(&fbi->cmap);
-
- free_irq(par->irq, (void *)par);
- iounmap(par->mmio_base);
- iounmap(par->fb_base);
-
- pci_release_regions(pdev);
- framebuffer_release(fbi);
- pci_disable_device(pdev);
-}
-
-static struct pci_driver mb862xxfb_pci_driver = {
- .name = DRV_NAME,
- .id_table = mb862xx_pci_tbl,
- .probe = mb862xx_pci_probe,
- .remove = __devexit_p(mb862xx_pci_remove),
-};
-#endif
-
-static int __devinit mb862xxfb_init(void)
-{
- int ret = -ENODEV;
-
-#if defined(CONFIG_FB_MB862XX_LIME)
- ret = platform_driver_register(&of_platform_mb862xxfb_driver);
-#endif
-#if defined(CONFIG_FB_MB862XX_PCI_GDC)
- ret = pci_register_driver(&mb862xxfb_pci_driver);
-#endif
- return ret;
-}
-
-static void __exit mb862xxfb_exit(void)
-{
-#if defined(CONFIG_FB_MB862XX_LIME)
- platform_driver_unregister(&of_platform_mb862xxfb_driver);
-#endif
-#if defined(CONFIG_FB_MB862XX_PCI_GDC)
- pci_unregister_driver(&mb862xxfb_pci_driver);
-#endif
-}
-
-module_init(mb862xxfb_init);
-module_exit(mb862xxfb_exit);
-
-MODULE_DESCRIPTION("Fujitsu MB862xx Framebuffer driver");
-MODULE_AUTHOR("Anatolij Gustschin <agust@denx.de>");
-MODULE_LICENSE("GPL v2");
diff --git a/drivers/video/mb862xx/mb862xxfb.h b/drivers/video/mb862xx/mb862xxfb.h
index d7e7cb7..8550630 100644
--- a/drivers/video/mb862xx/mb862xxfb.h
+++ b/drivers/video/mb862xx/mb862xxfb.h
@@ -1,6 +1,26 @@
#ifndef __MB862XX_H__
#define __MB862XX_H__
+struct mb862xx_l1_cfg {
+ unsigned short sx;
+ unsigned short sy;
+ unsigned short sw;
+ unsigned short sh;
+ unsigned short dx;
+ unsigned short dy;
+ unsigned short dw;
+ unsigned short dh;
+ int mirror;
+};
+
+#define MB862XX_BASE 'M'
+#define MB862XX_L1_GET_CFG _IOR(MB862XX_BASE, 0, struct mb862xx_l1_cfg*)
+#define MB862XX_L1_SET_CFG _IOW(MB862XX_BASE, 1, struct mb862xx_l1_cfg*)
+#define MB862XX_L1_ENABLE _IOW(MB862XX_BASE, 2, int)
+#define MB862XX_L1_CAP_CTL _IOW(MB862XX_BASE, 3, int)
+
+#ifdef __KERNEL__
+
#define PCI_VENDOR_ID_FUJITSU_LIMITED 0x10cf
#define PCI_DEVICE_ID_FUJITSU_CORALP 0x2019
#define PCI_DEVICE_ID_FUJITSU_CORALPA 0x201e
@@ -38,6 +58,8 @@
void __iomem *mmio_base; /* remapped registers */
size_t mapped_vram; /* length of remapped vram */
size_t mmio_len; /* length of register region */
+ unsigned long cap_buf; /* capture buffers offset */
+ size_t cap_len; /* length of capture buffers */
void __iomem *host; /* relocatable reg. bases */
void __iomem *i2c;
@@ -57,11 +79,23 @@
unsigned int refclk; /* disp. reference clock */
struct mb862xx_gc_mode *gc_mode; /* GDC mode init data */
int pre_init; /* don't init display if 1 */
+ struct i2c_adapter *adap; /* GDC I2C bus adapter */
+ int i2c_rs;
+
+ struct mb862xx_l1_cfg l1_cfg;
+ int l1_stride;
u32 pseudo_palette[16];
};
extern void mb862xxfb_init_accel(struct fb_info *info, int xres);
+#ifdef CONFIG_FB_MB862XX_I2C
+extern int mb862xx_i2c_init(struct mb862xxfb_par *par);
+extern void mb862xx_i2c_exit(struct mb862xxfb_par *par);
+#else
+static inline int mb862xx_i2c_init(struct mb862xxfb_par *par) { return 0; }
+static inline void mb862xx_i2c_exit(struct mb862xxfb_par *par) { }
+#endif
#if defined(CONFIG_FB_MB862XX_LIME) && defined(CONFIG_FB_MB862XX_PCI_GDC)
#error "Select Lime GDC or CoralP/Carmine support, but not both together"
@@ -82,4 +116,6 @@
#define pack(a, b) (((a) << 16) | (b))
+#endif /* __KERNEL__ */
+
#endif
diff --git a/drivers/video/mb862xx/mb862xxfbdrv.c b/drivers/video/mb862xx/mb862xxfbdrv.c
new file mode 100644
index 0000000..ea39336
--- /dev/null
+++ b/drivers/video/mb862xx/mb862xxfbdrv.c
@@ -0,0 +1,1201 @@
+/*
+ * drivers/mb862xx/mb862xxfb.c
+ *
+ * Fujitsu Carmine/Coral-P(A)/Lime framebuffer driver
+ *
+ * (C) 2008 Anatolij Gustschin <agust@denx.de>
+ * DENX Software Engineering
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#undef DEBUG
+
+#include <linux/fb.h>
+#include <linux/delay.h>
+#include <linux/init.h>
+#include <linux/interrupt.h>
+#include <linux/pci.h>
+#if defined(CONFIG_OF)
+#include <linux/of_platform.h>
+#endif
+#include "mb862xxfb.h"
+#include "mb862xx_reg.h"
+
+#define NR_PALETTE 256
+#define MB862XX_MEM_SIZE 0x1000000
+#define CORALP_MEM_SIZE 0x2000000
+#define CARMINE_MEM_SIZE 0x8000000
+#define DRV_NAME "mb862xxfb"
+
+#if defined(CONFIG_SOCRATES)
+static struct mb862xx_gc_mode socrates_gc_mode = {
+ /* Mode for Prime View PM070WL4 TFT LCD Panel */
+ { "800x480", 45, 800, 480, 40000, 86, 42, 33, 10, 128, 2, 0, 0, 0 },
+ /* 16 bits/pixel, 16MB, 133MHz, SDRAM memory mode value */
+ 16, 0x1000000, GC_CCF_COT_133, 0x4157ba63
+};
+#endif
+
+/* Helpers */
+static inline int h_total(struct fb_var_screeninfo *var)
+{
+ return var->xres + var->left_margin +
+ var->right_margin + var->hsync_len;
+}
+
+static inline int v_total(struct fb_var_screeninfo *var)
+{
+ return var->yres + var->upper_margin +
+ var->lower_margin + var->vsync_len;
+}
+
+static inline int hsp(struct fb_var_screeninfo *var)
+{
+ return var->xres + var->right_margin - 1;
+}
+
+static inline int vsp(struct fb_var_screeninfo *var)
+{
+ return var->yres + var->lower_margin - 1;
+}
+
+static inline int d_pitch(struct fb_var_screeninfo *var)
+{
+ return var->xres * var->bits_per_pixel / 8;
+}
+
+static inline unsigned int chan_to_field(unsigned int chan,
+ struct fb_bitfield *bf)
+{
+ chan &= 0xffff;
+ chan >>= 16 - bf->length;
+ return chan << bf->offset;
+}
+
+static int mb862xxfb_setcolreg(unsigned regno,
+ unsigned red, unsigned green, unsigned blue,
+ unsigned transp, struct fb_info *info)
+{
+ struct mb862xxfb_par *par = info->par;
+ unsigned int val;
+
+ switch (info->fix.visual) {
+ case FB_VISUAL_TRUECOLOR:
+ if (regno < 16) {
+ val = chan_to_field(red, &info->var.red);
+ val |= chan_to_field(green, &info->var.green);
+ val |= chan_to_field(blue, &info->var.blue);
+ par->pseudo_palette[regno] = val;
+ }
+ break;
+ case FB_VISUAL_PSEUDOCOLOR:
+ if (regno < 256) {
+ val = (red >> 8) << 16;
+ val |= (green >> 8) << 8;
+ val |= blue >> 8;
+ outreg(disp, GC_L0PAL0 + (regno * 4), val);
+ }
+ break;
+ default:
+ return 1; /* unsupported type */
+ }
+ return 0;
+}
+
+static int mb862xxfb_check_var(struct fb_var_screeninfo *var,
+ struct fb_info *fbi)
+{
+ unsigned long tmp;
+
+ if (fbi->dev)
+ dev_dbg(fbi->dev, "%s\n", __func__);
+
+ /* check if these values fit into the registers */
+ if (var->hsync_len > 255 || var->vsync_len > 255)
+ return -EINVAL;
+
+ if ((var->xres + var->right_margin) >= 4096)
+ return -EINVAL;
+
+ if ((var->yres + var->lower_margin) > 4096)
+ return -EINVAL;
+
+ if (h_total(var) > 4096 || v_total(var) > 4096)
+ return -EINVAL;
+
+ if (var->xres_virtual > 4096 || var->yres_virtual > 4096)
+ return -EINVAL;
+
+ if (var->bits_per_pixel <= 8)
+ var->bits_per_pixel = 8;
+ else if (var->bits_per_pixel <= 16)
+ var->bits_per_pixel = 16;
+ else if (var->bits_per_pixel <= 32)
+ var->bits_per_pixel = 32;
+
+ /*
+ * can cope with 8,16 or 24/32bpp if resulting
+ * pitch is divisible by 64 without remainder
+ */
+ if (d_pitch(&fbi->var) % GC_L0M_L0W_UNIT) {
+ int r;
+
+ var->bits_per_pixel = 0;
+ do {
+ var->bits_per_pixel += 8;
+ r = d_pitch(&fbi->var) % GC_L0M_L0W_UNIT;
+ } while (r && var->bits_per_pixel <= 32);
+
+ if (d_pitch(&fbi->var) % GC_L0M_L0W_UNIT)
+ return -EINVAL;
+ }
+
+ /* line length is going to be 128 bit aligned */
+ tmp = (var->xres * var->bits_per_pixel) / 8;
+ if ((tmp & 15) != 0)
+ return -EINVAL;
+
+ /* set r/g/b positions and validate bpp */
+ switch (var->bits_per_pixel) {
+ case 8:
+ var->red.length = var->bits_per_pixel;
+ var->green.length = var->bits_per_pixel;
+ var->blue.length = var->bits_per_pixel;
+ var->red.offset = 0;
+ var->green.offset = 0;
+ var->blue.offset = 0;
+ var->transp.length = 0;
+ break;
+ case 16:
+ var->red.length = 5;
+ var->green.length = 5;
+ var->blue.length = 5;
+ var->red.offset = 10;
+ var->green.offset = 5;
+ var->blue.offset = 0;
+ var->transp.length = 0;
+ break;
+ case 24:
+ case 32:
+ var->transp.length = 8;
+ var->red.length = 8;
+ var->green.length = 8;
+ var->blue.length = 8;
+ var->transp.offset = 24;
+ var->red.offset = 16;
+ var->green.offset = 8;
+ var->blue.offset = 0;
+ break;
+ default:
+ return -EINVAL;
+ }
+ return 0;
+}
+
+/*
+ * set display parameters
+ */
+static int mb862xxfb_set_par(struct fb_info *fbi)
+{
+ struct mb862xxfb_par *par = fbi->par;
+ unsigned long reg, sc;
+
+ dev_dbg(par->dev, "%s\n", __func__);
+ if (par->type == BT_CORALP)
+ mb862xxfb_init_accel(fbi, fbi->var.xres);
+
+ if (par->pre_init)
+ return 0;
+
+ /* disp off */
+ reg = inreg(disp, GC_DCM1);
+ reg &= ~GC_DCM01_DEN;
+ outreg(disp, GC_DCM1, reg);
+
+ /* set display reference clock div. */
+ sc = par->refclk / (1000000 / fbi->var.pixclock) - 1;
+ reg = inreg(disp, GC_DCM1);
+ reg &= ~(GC_DCM01_CKS | GC_DCM01_RESV | GC_DCM01_SC);
+ reg |= sc << 8;
+ outreg(disp, GC_DCM1, reg);
+ dev_dbg(par->dev, "SC 0x%lx\n", sc);
+
+ /* disp dimension, format */
+ reg = pack(d_pitch(&fbi->var) / GC_L0M_L0W_UNIT,
+ (fbi->var.yres - 1));
+ if (fbi->var.bits_per_pixel == 16)
+ reg |= GC_L0M_L0C_16;
+ outreg(disp, GC_L0M, reg);
+
+ if (fbi->var.bits_per_pixel == 32) {
+ reg = inreg(disp, GC_L0EM);
+ outreg(disp, GC_L0EM, reg | GC_L0EM_L0EC_24);
+ }
+ outreg(disp, GC_WY_WX, 0);
+ reg = pack(fbi->var.yres - 1, fbi->var.xres);
+ outreg(disp, GC_WH_WW, reg);
+ outreg(disp, GC_L0OA0, 0);
+ outreg(disp, GC_L0DA0, 0);
+ outreg(disp, GC_L0DY_L0DX, 0);
+ outreg(disp, GC_L0WY_L0WX, 0);
+ outreg(disp, GC_L0WH_L0WW, reg);
+
+ /* both HW-cursors off */
+ reg = inreg(disp, GC_CPM_CUTC);
+ reg &= ~(GC_CPM_CEN0 | GC_CPM_CEN1);
+ outreg(disp, GC_CPM_CUTC, reg);
+
+ /* timings */
+ reg = pack(fbi->var.xres - 1, fbi->var.xres - 1);
+ outreg(disp, GC_HDB_HDP, reg);
+ reg = pack((fbi->var.yres - 1), vsp(&fbi->var));
+ outreg(disp, GC_VDP_VSP, reg);
+ reg = ((fbi->var.vsync_len - 1) << 24) |
+ pack((fbi->var.hsync_len - 1), hsp(&fbi->var));
+ outreg(disp, GC_VSW_HSW_HSP, reg);
+ outreg(disp, GC_HTP, pack(h_total(&fbi->var) - 1, 0));
+ outreg(disp, GC_VTR, pack(v_total(&fbi->var) - 1, 0));
+
+ /* display on */
+ reg = inreg(disp, GC_DCM1);
+ reg |= GC_DCM01_DEN | GC_DCM01_L0E;
+ reg &= ~GC_DCM01_ESY;
+ outreg(disp, GC_DCM1, reg);
+ return 0;
+}
+
+static int mb862xxfb_pan(struct fb_var_screeninfo *var,
+ struct fb_info *info)
+{
+ struct mb862xxfb_par *par = info->par;
+ unsigned long reg;
+
+ reg = pack(var->yoffset, var->xoffset);
+ outreg(disp, GC_L0WY_L0WX, reg);
+
+ reg = pack(var->yres_virtual, var->xres_virtual);
+ outreg(disp, GC_L0WH_L0WW, reg);
+ return 0;
+}
+
+static int mb862xxfb_blank(int mode, struct fb_info *fbi)
+{
+ struct mb862xxfb_par *par = fbi->par;
+ unsigned long reg;
+
+ dev_dbg(fbi->dev, "blank mode=%d\n", mode);
+
+ switch (mode) {
+ case FB_BLANK_POWERDOWN:
+ reg = inreg(disp, GC_DCM1);
+ reg &= ~GC_DCM01_DEN;
+ outreg(disp, GC_DCM1, reg);
+ break;
+ case FB_BLANK_UNBLANK:
+ reg = inreg(disp, GC_DCM1);
+ reg |= GC_DCM01_DEN;
+ outreg(disp, GC_DCM1, reg);
+ break;
+ case FB_BLANK_NORMAL:
+ case FB_BLANK_VSYNC_SUSPEND:
+ case FB_BLANK_HSYNC_SUSPEND:
+ default:
+ return 1;
+ }
+ return 0;
+}
+
+static int mb862xxfb_ioctl(struct fb_info *fbi, unsigned int cmd,
+ unsigned long arg)
+{
+ struct mb862xxfb_par *par = fbi->par;
+ struct mb862xx_l1_cfg *l1_cfg = &par->l1_cfg;
+ void __user *argp = (void __user *)arg;
+ int *enable;
+ u32 l1em = 0;
+
+ switch (cmd) {
+ case MB862XX_L1_GET_CFG:
+ if (copy_to_user(argp, l1_cfg, sizeof(*l1_cfg)))
+ return -EFAULT;
+ break;
+ case MB862XX_L1_SET_CFG:
+ if (copy_from_user(l1_cfg, argp, sizeof(*l1_cfg)))
+ return -EFAULT;
+ if ((l1_cfg->sw >= l1_cfg->dw) && (l1_cfg->sh >= l1_cfg->dh)) {
+ /* downscaling */
+ outreg(cap, GC_CAP_CSC,
+ pack((l1_cfg->sh << 11) / l1_cfg->dh,
+ (l1_cfg->sw << 11) / l1_cfg->dw));
+ l1em = inreg(disp, GC_L1EM);
+ l1em &= ~GC_L1EM_DM;
+ } else if ((l1_cfg->sw <= l1_cfg->dw) &&
+ (l1_cfg->sh <= l1_cfg->dh)) {
+ /* upscaling */
+ outreg(cap, GC_CAP_CSC,
+ pack((l1_cfg->sh << 11) / l1_cfg->dh,
+ (l1_cfg->sw << 11) / l1_cfg->dw));
+ outreg(cap, GC_CAP_CMSS,
+ pack(l1_cfg->sw >> 1, l1_cfg->sh));
+ outreg(cap, GC_CAP_CMDS,
+ pack(l1_cfg->dw >> 1, l1_cfg->dh));
+ l1em = inreg(disp, GC_L1EM);
+ l1em |= GC_L1EM_DM;
+ }
+
+ if (l1_cfg->mirror) {
+ outreg(cap, GC_CAP_CBM,
+ inreg(cap, GC_CAP_CBM) | GC_CBM_HRV);
+ l1em |= l1_cfg->dw * 2 - 8;
+ } else {
+ outreg(cap, GC_CAP_CBM,
+ inreg(cap, GC_CAP_CBM) & ~GC_CBM_HRV);
+ l1em &= 0xffff0000;
+ }
+ outreg(disp, GC_L1EM, l1em);
+ break;
+ case MB862XX_L1_ENABLE:
+ enable = (int *)arg;
+ if (*enable) {
+ outreg(disp, GC_L1DA, par->cap_buf);
+ outreg(cap, GC_CAP_IMG_START,
+ pack(l1_cfg->sy >> 1, l1_cfg->sx));
+ outreg(cap, GC_CAP_IMG_END,
+ pack(l1_cfg->sh, l1_cfg->sw));
+ outreg(disp, GC_L1M, GC_L1M_16 | GC_L1M_YC | GC_L1M_CS |
+ (par->l1_stride << 16));
+ outreg(disp, GC_L1WY_L1WX,
+ pack(l1_cfg->dy, l1_cfg->dx));
+ outreg(disp, GC_L1WH_L1WW,
+ pack(l1_cfg->dh - 1, l1_cfg->dw));
+ outreg(disp, GC_DLS, 1);
+ outreg(cap, GC_CAP_VCM,
+ GC_VCM_VIE | GC_VCM_CM | GC_VCM_VS_PAL);
+ outreg(disp, GC_DCM1, inreg(disp, GC_DCM1) |
+ GC_DCM1_DEN | GC_DCM1_L1E);
+ } else {
+ outreg(cap, GC_CAP_VCM,
+ inreg(cap, GC_CAP_VCM) & ~GC_VCM_VIE);
+ outreg(disp, GC_DCM1,
+ inreg(disp, GC_DCM1) & ~GC_DCM1_L1E);
+ }
+ break;
+ case MB862XX_L1_CAP_CTL:
+ enable = (int *)arg;
+ if (*enable) {
+ outreg(cap, GC_CAP_VCM,
+ inreg(cap, GC_CAP_VCM) | GC_VCM_VIE);
+ } else {
+ outreg(cap, GC_CAP_VCM,
+ inreg(cap, GC_CAP_VCM) & ~GC_VCM_VIE);
+ }
+ break;
+ default:
+ return -EINVAL;
+ }
+ return 0;
+}
+
+/* framebuffer ops */
+static struct fb_ops mb862xxfb_ops = {
+ .owner = THIS_MODULE,
+ .fb_check_var = mb862xxfb_check_var,
+ .fb_set_par = mb862xxfb_set_par,
+ .fb_setcolreg = mb862xxfb_setcolreg,
+ .fb_blank = mb862xxfb_blank,
+ .fb_pan_display = mb862xxfb_pan,
+ .fb_fillrect = cfb_fillrect,
+ .fb_copyarea = cfb_copyarea,
+ .fb_imageblit = cfb_imageblit,
+ .fb_ioctl = mb862xxfb_ioctl,
+};
+
+/* initialize fb_info data */
+static int mb862xxfb_init_fbinfo(struct fb_info *fbi)
+{
+ struct mb862xxfb_par *par = fbi->par;
+ struct mb862xx_gc_mode *mode = par->gc_mode;
+ unsigned long reg;
+ int stride;
+
+ fbi->fbops = &mb862xxfb_ops;
+ fbi->pseudo_palette = par->pseudo_palette;
+ fbi->screen_base = par->fb_base;
+ fbi->screen_size = par->mapped_vram;
+
+ strcpy(fbi->fix.id, DRV_NAME);
+ fbi->fix.smem_start = (unsigned long)par->fb_base_phys;
+ fbi->fix.mmio_start = (unsigned long)par->mmio_base_phys;
+ fbi->fix.mmio_len = par->mmio_len;
+ fbi->fix.accel = FB_ACCEL_NONE;
+ fbi->fix.type = FB_TYPE_PACKED_PIXELS;
+ fbi->fix.type_aux = 0;
+ fbi->fix.xpanstep = 1;
+ fbi->fix.ypanstep = 1;
+ fbi->fix.ywrapstep = 0;
+
+ reg = inreg(disp, GC_DCM1);
+ if (reg & GC_DCM01_DEN && reg & GC_DCM01_L0E) {
+ /* get the disp mode from active display cfg */
+ unsigned long sc = ((reg & GC_DCM01_SC) >> 8) + 1;
+ unsigned long hsp, vsp, ht, vt;
+
+ dev_dbg(par->dev, "using bootloader's disp. mode\n");
+ fbi->var.pixclock = (sc * 1000000) / par->refclk;
+ fbi->var.xres = (inreg(disp, GC_HDB_HDP) & 0x0fff) + 1;
+ reg = inreg(disp, GC_VDP_VSP);
+ fbi->var.yres = ((reg >> 16) & 0x0fff) + 1;
+ vsp = (reg & 0x0fff) + 1;
+ fbi->var.xres_virtual = fbi->var.xres;
+ fbi->var.yres_virtual = fbi->var.yres;
+ reg = inreg(disp, GC_L0EM);
+ if (reg & GC_L0EM_L0EC_24) {
+ fbi->var.bits_per_pixel = 32;
+ } else {
+ reg = inreg(disp, GC_L0M);
+ if (reg & GC_L0M_L0C_16)
+ fbi->var.bits_per_pixel = 16;
+ else
+ fbi->var.bits_per_pixel = 8;
+ }
+ reg = inreg(disp, GC_VSW_HSW_HSP);
+ fbi->var.hsync_len = ((reg & 0xff0000) >> 16) + 1;
+ fbi->var.vsync_len = ((reg & 0x3f000000) >> 24) + 1;
+ hsp = (reg & 0xffff) + 1;
+ ht = ((inreg(disp, GC_HTP) & 0xfff0000) >> 16) + 1;
+ fbi->var.right_margin = hsp - fbi->var.xres;
+ fbi->var.left_margin = ht - hsp - fbi->var.hsync_len;
+ vt = ((inreg(disp, GC_VTR) & 0xfff0000) >> 16) + 1;
+ fbi->var.lower_margin = vsp - fbi->var.yres;
+ fbi->var.upper_margin = vt - vsp - fbi->var.vsync_len;
+ } else if (mode) {
+ dev_dbg(par->dev, "using supplied mode\n");
+ fb_videomode_to_var(&fbi->var, (struct fb_videomode *)mode);
+ fbi->var.bits_per_pixel = mode->def_bpp ? mode->def_bpp : 8;
+ } else {
+ int ret;
+
+ ret = fb_find_mode(&fbi->var, fbi, "640x480-16@60",
+ NULL, 0, NULL, 16);
+ if (ret == 0 || ret == 4) {
+ dev_err(par->dev,
+ "failed to get initial mode\n");
+ return -EINVAL;
+ }
+ }
+
+ fbi->var.xoffset = 0;
+ fbi->var.yoffset = 0;
+ fbi->var.grayscale = 0;
+ fbi->var.nonstd = 0;
+ fbi->var.height = -1;
+ fbi->var.width = -1;
+ fbi->var.accel_flags = 0;
+ fbi->var.vmode = FB_VMODE_NONINTERLACED;
+ fbi->var.activate = FB_ACTIVATE_NOW;
+ fbi->flags = FBINFO_DEFAULT |
+#ifdef __BIG_ENDIAN
+ FBINFO_FOREIGN_ENDIAN |
+#endif
+ FBINFO_HWACCEL_XPAN |
+ FBINFO_HWACCEL_YPAN;
+
+ /* check and possibly fix bpp */
+ if ((fbi->fbops->fb_check_var)(&fbi->var, fbi))
+ dev_err(par->dev, "check_var() failed on initial setup?\n");
+
+ fbi->fix.visual = fbi->var.bits_per_pixel == 8 ?
+ FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
+ fbi->fix.line_length = (fbi->var.xres_virtual *
+ fbi->var.bits_per_pixel) / 8;
+ fbi->fix.smem_len = fbi->fix.line_length * fbi->var.yres_virtual;
+
+ /*
+ * reserve space for capture buffers and two cursors
+ * at the end of vram: 720x576 * 2 * 2.2 + 64x64 * 16.
+ */
+ par->cap_buf = par->mapped_vram - 0x1bd800 - 0x10000;
+ par->cap_len = 0x1bd800;
+ par->l1_cfg.sx = 0;
+ par->l1_cfg.sy = 0;
+ par->l1_cfg.sw = 720;
+ par->l1_cfg.sh = 576;
+ par->l1_cfg.dx = 0;
+ par->l1_cfg.dy = 0;
+ par->l1_cfg.dw = 720;
+ par->l1_cfg.dh = 576;
+ stride = par->l1_cfg.sw * (fbi->var.bits_per_pixel / 8);
+ par->l1_stride = stride / 64 + ((stride % 64) ? 1 : 0);
+ outreg(cap, GC_CAP_CBM, GC_CBM_OO | GC_CBM_CBST |
+ (par->l1_stride << 16));
+ outreg(cap, GC_CAP_CBOA, par->cap_buf);
+ outreg(cap, GC_CAP_CBLA, par->cap_buf + par->cap_len);
+ return 0;
+}
+
+/*
+ * show some display controller and cursor registers
+ */
+static ssize_t mb862xxfb_show_dispregs(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ struct fb_info *fbi = dev_get_drvdata(dev);
+ struct mb862xxfb_par *par = fbi->par;
+ char *ptr = buf;
+ unsigned int reg;
+
+ for (reg = GC_DCM0; reg <= GC_L0DY_L0DX; reg += 4)
+ ptr += sprintf(ptr, "%08x = %08x\n",
+ reg, inreg(disp, reg));
+
+ for (reg = GC_CPM_CUTC; reg <= GC_CUY1_CUX1; reg += 4)
+ ptr += sprintf(ptr, "%08x = %08x\n",
+ reg, inreg(disp, reg));
+
+ for (reg = GC_DCM1; reg <= GC_L0WH_L0WW; reg += 4)
+ ptr += sprintf(ptr, "%08x = %08x\n",
+ reg, inreg(disp, reg));
+
+ for (reg = 0x400; reg <= 0x410; reg += 4)
+ ptr += sprintf(ptr, "geo %08x = %08x\n",
+ reg, inreg(geo, reg));
+
+ for (reg = 0x400; reg <= 0x410; reg += 4)
+ ptr += sprintf(ptr, "draw %08x = %08x\n",
+ reg, inreg(draw, reg));
+
+ for (reg = 0x440; reg <= 0x450; reg += 4)
+ ptr += sprintf(ptr, "draw %08x = %08x\n",
+ reg, inreg(draw, reg));
+
+ return ptr - buf;
+}
+
+static DEVICE_ATTR(dispregs, 0444, mb862xxfb_show_dispregs, NULL);
+
+irqreturn_t mb862xx_intr(int irq, void *dev_id)
+{
+ struct mb862xxfb_par *par = (struct mb862xxfb_par *) dev_id;
+ unsigned long reg_ist, mask;
+
+ if (!par)
+ return IRQ_NONE;
+
+ if (par->type == BT_CARMINE) {
+ /* Get Interrupt Status */
+ reg_ist = inreg(ctrl, GC_CTRL_STATUS);
+ mask = inreg(ctrl, GC_CTRL_INT_MASK);
+ if (reg_ist == 0)
+ return IRQ_HANDLED;
+
+ reg_ist &= mask;
+ if (reg_ist == 0)
+ return IRQ_HANDLED;
+
+ /* Clear interrupt status */
+ outreg(ctrl, 0x0, reg_ist);
+ } else {
+ /* Get status */
+ reg_ist = inreg(host, GC_IST);
+ mask = inreg(host, GC_IMASK);
+
+ reg_ist &= mask;
+ if (reg_ist == 0)
+ return IRQ_HANDLED;
+
+ /* Clear status */
+ outreg(host, GC_IST, ~reg_ist);
+ }
+ return IRQ_HANDLED;
+}
+
+#if defined(CONFIG_FB_MB862XX_LIME)
+/*
+ * GDC (Lime, Coral(B/Q), Mint, ...) on host bus
+ */
+static int mb862xx_gdc_init(struct mb862xxfb_par *par)
+{
+ unsigned long ccf, mmr;
+ unsigned long ver, rev;
+
+ if (!par)
+ return -ENODEV;
+
+#if defined(CONFIG_FB_PRE_INIT_FB)
+ par->pre_init = 1;
+#endif
+ par->host = par->mmio_base;
+ par->i2c = par->mmio_base + MB862XX_I2C_BASE;
+ par->disp = par->mmio_base + MB862XX_DISP_BASE;
+ par->cap = par->mmio_base + MB862XX_CAP_BASE;
+ par->draw = par->mmio_base + MB862XX_DRAW_BASE;
+ par->geo = par->mmio_base + MB862XX_GEO_BASE;
+ par->pio = par->mmio_base + MB862XX_PIO_BASE;
+
+ par->refclk = GC_DISP_REFCLK_400;
+
+ ver = inreg(host, GC_CID);
+ rev = inreg(pio, GC_REVISION);
+ if ((ver == 0x303) && (rev & 0xffffff00) == 0x20050100) {
+ dev_info(par->dev, "Fujitsu Lime v1.%d found\n",
+ (int)rev & 0xff);
+ par->type = BT_LIME;
+ ccf = par->gc_mode ? par->gc_mode->ccf : GC_CCF_COT_100;
+ mmr = par->gc_mode ? par->gc_mode->mmr : 0x414fb7f2;
+ } else {
+ dev_info(par->dev, "? GDC, CID/Rev.: 0x%lx/0x%lx \n", ver, rev);
+ return -ENODEV;
+ }
+
+ if (!par->pre_init) {
+ outreg(host, GC_CCF, ccf);
+ udelay(200);
+ outreg(host, GC_MMR, mmr);
+ udelay(10);
+ }
+
+ /* interrupt status */
+ outreg(host, GC_IST, 0);
+ outreg(host, GC_IMASK, GC_INT_EN);
+ return 0;
+}
+
+static int __devinit of_platform_mb862xx_probe(struct platform_device *ofdev)
+{
+ struct device_node *np = ofdev->dev.of_node;
+ struct device *dev = &ofdev->dev;
+ struct mb862xxfb_par *par;
+ struct fb_info *info;
+ struct resource res;
+ resource_size_t res_size;
+ unsigned long ret = -ENODEV;
+
+ if (of_address_to_resource(np, 0, &res)) {
+ dev_err(dev, "Invalid address\n");
+ return -ENXIO;
+ }
+
+ info = framebuffer_alloc(sizeof(struct mb862xxfb_par), dev);
+ if (info == NULL) {
+ dev_err(dev, "cannot allocate framebuffer\n");
+ return -ENOMEM;
+ }
+
+ par = info->par;
+ par->info = info;
+ par->dev = dev;
+
+ par->irq = irq_of_parse_and_map(np, 0);
+ if (par->irq == NO_IRQ) {
+ dev_err(dev, "failed to map irq\n");
+ ret = -ENODEV;
+ goto fbrel;
+ }
+
+ res_size = 1 + res.end - res.start;
+ par->res = request_mem_region(res.start, res_size, DRV_NAME);
+ if (par->res == NULL) {
+ dev_err(dev, "Cannot claim framebuffer/mmio\n");
+ ret = -ENXIO;
+ goto irqdisp;
+ }
+
+#if defined(CONFIG_SOCRATES)
+ par->gc_mode = &socrates_gc_mode;
+#endif
+
+ par->fb_base_phys = res.start;
+ par->mmio_base_phys = res.start + MB862XX_MMIO_BASE;
+ par->mmio_len = MB862XX_MMIO_SIZE;
+ if (par->gc_mode)
+ par->mapped_vram = par->gc_mode->max_vram;
+ else
+ par->mapped_vram = MB862XX_MEM_SIZE;
+
+ par->fb_base = ioremap(par->fb_base_phys, par->mapped_vram);
+ if (par->fb_base == NULL) {
+ dev_err(dev, "Cannot map framebuffer\n");
+ goto rel_reg;
+ }
+
+ par->mmio_base = ioremap(par->mmio_base_phys, par->mmio_len);
+ if (par->mmio_base == NULL) {
+ dev_err(dev, "Cannot map registers\n");
+ goto fb_unmap;
+ }
+
+ dev_dbg(dev, "fb phys 0x%llx 0x%lx\n",
+ (u64)par->fb_base_phys, (ulong)par->mapped_vram);
+ dev_dbg(dev, "mmio phys 0x%llx 0x%lx, (irq = %d)\n",
+ (u64)par->mmio_base_phys, (ulong)par->mmio_len, par->irq);
+
+ if (mb862xx_gdc_init(par))
+ goto io_unmap;
+
+ if (request_irq(par->irq, mb862xx_intr, IRQF_DISABLED,
+ DRV_NAME, (void *)par)) {
+ dev_err(dev, "Cannot request irq\n");
+ goto io_unmap;
+ }
+
+ mb862xxfb_init_fbinfo(info);
+
+ if (fb_alloc_cmap(&info->cmap, NR_PALETTE, 0) < 0) {
+ dev_err(dev, "Could not allocate cmap for fb_info.\n");
+ goto free_irq;
+ }
+
+ if ((info->fbops->fb_set_par)(info))
+ dev_err(dev, "set_var() failed on initial setup?\n");
+
+ if (register_framebuffer(info)) {
+ dev_err(dev, "failed to register framebuffer\n");
+ goto rel_cmap;
+ }
+
+ dev_set_drvdata(dev, info);
+
+ if (device_create_file(dev, &dev_attr_dispregs))
+ dev_err(dev, "Can't create sysfs regdump file\n");
+ return 0;
+
+rel_cmap:
+ fb_dealloc_cmap(&info->cmap);
+free_irq:
+ outreg(host, GC_IMASK, 0);
+ free_irq(par->irq, (void *)par);
+io_unmap:
+ iounmap(par->mmio_base);
+fb_unmap:
+ iounmap(par->fb_base);
+rel_reg:
+ release_mem_region(res.start, res_size);
+irqdisp:
+ irq_dispose_mapping(par->irq);
+fbrel:
+ dev_set_drvdata(dev, NULL);
+ framebuffer_release(info);
+ return ret;
+}
+
+static int __devexit of_platform_mb862xx_remove(struct platform_device *ofdev)
+{
+ struct fb_info *fbi = dev_get_drvdata(&ofdev->dev);
+ struct mb862xxfb_par *par = fbi->par;
+ resource_size_t res_size = 1 + par->res->end - par->res->start;
+ unsigned long reg;
+
+ dev_dbg(fbi->dev, "%s release\n", fbi->fix.id);
+
+ /* display off */
+ reg = inreg(disp, GC_DCM1);
+ reg &= ~(GC_DCM01_DEN | GC_DCM01_L0E);
+ outreg(disp, GC_DCM1, reg);
+
+ /* disable interrupts */
+ outreg(host, GC_IMASK, 0);
+
+ free_irq(par->irq, (void *)par);
+ irq_dispose_mapping(par->irq);
+
+ device_remove_file(&ofdev->dev, &dev_attr_dispregs);
+
+ unregister_framebuffer(fbi);
+ fb_dealloc_cmap(&fbi->cmap);
+
+ iounmap(par->mmio_base);
+ iounmap(par->fb_base);
+
+ dev_set_drvdata(&ofdev->dev, NULL);
+ release_mem_region(par->res->start, res_size);
+ framebuffer_release(fbi);
+ return 0;
+}
+
+/*
+ * common types
+ */
+static struct of_device_id __devinitdata of_platform_mb862xx_tbl[] = {
+ { .compatible = "fujitsu,MB86276", },
+ { .compatible = "fujitsu,lime", },
+ { .compatible = "fujitsu,MB86277", },
+ { .compatible = "fujitsu,mint", },
+ { .compatible = "fujitsu,MB86293", },
+ { .compatible = "fujitsu,MB86294", },
+ { .compatible = "fujitsu,coral", },
+ { /* end */ }
+};
+
+static struct platform_driver of_platform_mb862xxfb_driver = {
+ .driver = {
+ .name = DRV_NAME,
+ .owner = THIS_MODULE,
+ .of_match_table = of_platform_mb862xx_tbl,
+ },
+ .probe = of_platform_mb862xx_probe,
+ .remove = __devexit_p(of_platform_mb862xx_remove),
+};
+#endif
+
+#if defined(CONFIG_FB_MB862XX_PCI_GDC)
+static int coralp_init(struct mb862xxfb_par *par)
+{
+ int cn, ver;
+
+ par->host = par->mmio_base;
+ par->i2c = par->mmio_base + MB862XX_I2C_BASE;
+ par->disp = par->mmio_base + MB862XX_DISP_BASE;
+ par->cap = par->mmio_base + MB862XX_CAP_BASE;
+ par->draw = par->mmio_base + MB862XX_DRAW_BASE;
+ par->geo = par->mmio_base + MB862XX_GEO_BASE;
+ par->pio = par->mmio_base + MB862XX_PIO_BASE;
+
+ par->refclk = GC_DISP_REFCLK_400;
+
+ if (par->mapped_vram >= 0x2000000) {
+ /* relocate gdc registers space */
+ writel(1, par->fb_base + MB862XX_MMIO_BASE + GC_RSW);
+ udelay(1); /* wait at least 20 bus cycles */
+ }
+
+ ver = inreg(host, GC_CID);
+ cn = (ver & GC_CID_CNAME_MSK) >> 8;
+ ver = ver & GC_CID_VERSION_MSK;
+ if (cn == 3) {
+ unsigned long reg;
+
+ dev_info(par->dev, "Fujitsu Coral-%s GDC Rev.%d found\n",\
+ (ver == 6) ? "P" : (ver == 8) ? "PA" : "?",
+ par->pdev->revision);
+ reg = inreg(disp, GC_DCM1);
+ if (reg & GC_DCM01_DEN && reg & GC_DCM01_L0E)
+ par->pre_init = 1;
+
+ if (!par->pre_init) {
+ outreg(host, GC_CCF, GC_CCF_CGE_166 | GC_CCF_COT_133);
+ udelay(200);
+ outreg(host, GC_MMR, GC_MMR_CORALP_EVB_VAL);
+ udelay(10);
+ }
+ /* Clear interrupt status */
+ outreg(host, GC_IST, 0);
+ } else {
+ return -ENODEV;
+ }
+
+ mb862xx_i2c_init(par);
+ return 0;
+}
+
+static int init_dram_ctrl(struct mb862xxfb_par *par)
+{
+ unsigned long i = 0;
+
+ /*
+ * Set io mode first! Spec. says IC may be destroyed
+ * if not set to SSTL2/LVCMOS before init.
+ */
+ outreg(dram_ctrl, GC_DCTL_IOCONT1_IOCONT0, GC_EVB_DCTL_IOCONT1_IOCONT0);
+
+ /* DRAM init */
+ outreg(dram_ctrl, GC_DCTL_MODE_ADD, GC_EVB_DCTL_MODE_ADD);
+ outreg(dram_ctrl, GC_DCTL_SETTIME1_EMODE, GC_EVB_DCTL_SETTIME1_EMODE);
+ outreg(dram_ctrl, GC_DCTL_REFRESH_SETTIME2,
+ GC_EVB_DCTL_REFRESH_SETTIME2);
+ outreg(dram_ctrl, GC_DCTL_RSV2_RSV1, GC_EVB_DCTL_RSV2_RSV1);
+ outreg(dram_ctrl, GC_DCTL_DDRIF2_DDRIF1, GC_EVB_DCTL_DDRIF2_DDRIF1);
+ outreg(dram_ctrl, GC_DCTL_RSV0_STATES, GC_EVB_DCTL_RSV0_STATES);
+
+ /* DLL reset done? */
+ while ((inreg(dram_ctrl, GC_DCTL_RSV0_STATES) & GC_DCTL_STATES_MSK)) {
+ udelay(GC_DCTL_INIT_WAIT_INTERVAL);
+ if (i++ > GC_DCTL_INIT_WAIT_CNT) {
+ dev_err(par->dev, "VRAM init failed.\n");
+ return -EINVAL;
+ }
+ }
+ outreg(dram_ctrl, GC_DCTL_MODE_ADD, GC_EVB_DCTL_MODE_ADD_AFT_RST);
+ outreg(dram_ctrl, GC_DCTL_RSV0_STATES, GC_EVB_DCTL_RSV0_STATES_AFT_RST);
+ return 0;
+}
+
+static int carmine_init(struct mb862xxfb_par *par)
+{
+ unsigned long reg;
+
+ par->ctrl = par->mmio_base + MB86297_CTRL_BASE;
+ par->i2c = par->mmio_base + MB86297_I2C_BASE;
+ par->disp = par->mmio_base + MB86297_DISP0_BASE;
+ par->disp1 = par->mmio_base + MB86297_DISP1_BASE;
+ par->cap = par->mmio_base + MB86297_CAP0_BASE;
+ par->cap1 = par->mmio_base + MB86297_CAP1_BASE;
+ par->draw = par->mmio_base + MB86297_DRAW_BASE;
+ par->dram_ctrl = par->mmio_base + MB86297_DRAMCTRL_BASE;
+ par->wrback = par->mmio_base + MB86297_WRBACK_BASE;
+
+ par->refclk = GC_DISP_REFCLK_533;
+
+ /* warm up */
+ reg = GC_CTRL_CLK_EN_DRAM | GC_CTRL_CLK_EN_2D3D | GC_CTRL_CLK_EN_DISP0;
+ outreg(ctrl, GC_CTRL_CLK_ENABLE, reg);
+
+ /* check for engine module revision */
+ if (inreg(draw, GC_2D3D_REV) == GC_RE_REVISION)
+ dev_info(par->dev, "Fujitsu Carmine GDC Rev.%d found\n",
+ par->pdev->revision);
+ else
+ goto err_init;
+
+ reg &= ~GC_CTRL_CLK_EN_2D3D;
+ outreg(ctrl, GC_CTRL_CLK_ENABLE, reg);
+
+ /* set up vram */
+ if (init_dram_ctrl(par) < 0)
+ goto err_init;
+
+ outreg(ctrl, GC_CTRL_INT_MASK, 0);
+ return 0;
+
+err_init:
+ outreg(ctrl, GC_CTRL_CLK_ENABLE, 0);
+ return -EINVAL;
+}
+
+static inline int mb862xx_pci_gdc_init(struct mb862xxfb_par *par)
+{
+ switch (par->type) {
+ case BT_CORALP:
+ return coralp_init(par);
+ case BT_CARMINE:
+ return carmine_init(par);
+ default:
+ return -ENODEV;
+ }
+}
+
+#define CHIP_ID(id) \
+ { PCI_DEVICE(PCI_VENDOR_ID_FUJITSU_LIMITED, id) }
+
+static struct pci_device_id mb862xx_pci_tbl[] __devinitdata = {
+ /* MB86295/MB86296 */
+ CHIP_ID(PCI_DEVICE_ID_FUJITSU_CORALP),
+ CHIP_ID(PCI_DEVICE_ID_FUJITSU_CORALPA),
+ /* MB86297 */
+ CHIP_ID(PCI_DEVICE_ID_FUJITSU_CARMINE),
+ { 0, }
+};
+
+MODULE_DEVICE_TABLE(pci, mb862xx_pci_tbl);
+
+static int __devinit mb862xx_pci_probe(struct pci_dev *pdev,
+ const struct pci_device_id *ent)
+{
+ struct mb862xxfb_par *par;
+ struct fb_info *info;
+ struct device *dev = &pdev->dev;
+ int ret;
+
+ ret = pci_enable_device(pdev);
+ if (ret < 0) {
+ dev_err(dev, "Cannot enable PCI device\n");
+ goto out;
+ }
+
+ info = framebuffer_alloc(sizeof(struct mb862xxfb_par), dev);
+ if (!info) {
+ dev_err(dev, "framebuffer alloc failed\n");
+ ret = -ENOMEM;
+ goto dis_dev;
+ }
+
+ par = info->par;
+ par->info = info;
+ par->dev = dev;
+ par->pdev = pdev;
+ par->irq = pdev->irq;
+
+ ret = pci_request_regions(pdev, DRV_NAME);
+ if (ret < 0) {
+ dev_err(dev, "Cannot reserve region(s) for PCI device\n");
+ goto rel_fb;
+ }
+
+ switch (pdev->device) {
+ case PCI_DEVICE_ID_FUJITSU_CORALP:
+ case PCI_DEVICE_ID_FUJITSU_CORALPA:
+ par->fb_base_phys = pci_resource_start(par->pdev, 0);
+ par->mapped_vram = CORALP_MEM_SIZE;
+ if (par->mapped_vram >= 0x2000000) {
+ par->mmio_base_phys = par->fb_base_phys +
+ MB862XX_MMIO_HIGH_BASE;
+ } else {
+ par->mmio_base_phys = par->fb_base_phys +
+ MB862XX_MMIO_BASE;
+ }
+ par->mmio_len = MB862XX_MMIO_SIZE;
+ par->type = BT_CORALP;
+ break;
+ case PCI_DEVICE_ID_FUJITSU_CARMINE:
+ par->fb_base_phys = pci_resource_start(par->pdev, 2);
+ par->mmio_base_phys = pci_resource_start(par->pdev, 3);
+ par->mmio_len = pci_resource_len(par->pdev, 3);
+ par->mapped_vram = CARMINE_MEM_SIZE;
+ par->type = BT_CARMINE;
+ break;
+ default:
+ /* should never occur */
+ goto rel_reg;
+ }
+
+ par->fb_base = ioremap(par->fb_base_phys, par->mapped_vram);
+ if (par->fb_base == NULL) {
+ dev_err(dev, "Cannot map framebuffer\n");
+ goto rel_reg;
+ }
+
+ par->mmio_base = ioremap(par->mmio_base_phys, par->mmio_len);
+ if (par->mmio_base == NULL) {
+ dev_err(dev, "Cannot map registers\n");
+ ret = -EIO;
+ goto fb_unmap;
+ }
+
+ dev_dbg(dev, "fb phys 0x%llx 0x%lx\n",
+ (unsigned long long)par->fb_base_phys, (ulong)par->mapped_vram);
+ dev_dbg(dev, "mmio phys 0x%llx 0x%lx\n",
+ (unsigned long long)par->mmio_base_phys, (ulong)par->mmio_len);
+
+ if (mb862xx_pci_gdc_init(par))
+ goto io_unmap;
+
+ if (request_irq(par->irq, mb862xx_intr, IRQF_DISABLED | IRQF_SHARED,
+ DRV_NAME, (void *)par)) {
+ dev_err(dev, "Cannot request irq\n");
+ goto io_unmap;
+ }
+
+ mb862xxfb_init_fbinfo(info);
+
+ if (fb_alloc_cmap(&info->cmap, NR_PALETTE, 0) < 0) {
+ dev_err(dev, "Could not allocate cmap for fb_info.\n");
+ ret = -ENOMEM;
+ goto free_irq;
+ }
+
+ if ((info->fbops->fb_set_par)(info))
+ dev_err(dev, "set_var() failed on initial setup?\n");
+
+ ret = register_framebuffer(info);
+ if (ret < 0) {
+ dev_err(dev, "failed to register framebuffer\n");
+ goto rel_cmap;
+ }
+
+ pci_set_drvdata(pdev, info);
+
+ if (device_create_file(dev, &dev_attr_dispregs))
+ dev_err(dev, "Can't create sysfs regdump file\n");
+
+ if (par->type == BT_CARMINE)
+ outreg(ctrl, GC_CTRL_INT_MASK, GC_CARMINE_INT_EN);
+ else
+ outreg(host, GC_IMASK, GC_INT_EN);
+
+ return 0;
+
+rel_cmap:
+ fb_dealloc_cmap(&info->cmap);
+free_irq:
+ free_irq(par->irq, (void *)par);
+io_unmap:
+ iounmap(par->mmio_base);
+fb_unmap:
+ iounmap(par->fb_base);
+rel_reg:
+ pci_release_regions(pdev);
+rel_fb:
+ framebuffer_release(info);
+dis_dev:
+ pci_disable_device(pdev);
+out:
+ return ret;
+}
+
+static void __devexit mb862xx_pci_remove(struct pci_dev *pdev)
+{
+ struct fb_info *fbi = pci_get_drvdata(pdev);
+ struct mb862xxfb_par *par = fbi->par;
+ unsigned long reg;
+
+ dev_dbg(fbi->dev, "%s release\n", fbi->fix.id);
+
+ /* display off */
+ reg = inreg(disp, GC_DCM1);
+ reg &= ~(GC_DCM01_DEN | GC_DCM01_L0E);
+ outreg(disp, GC_DCM1, reg);
+
+ if (par->type == BT_CARMINE) {
+ outreg(ctrl, GC_CTRL_INT_MASK, 0);
+ outreg(ctrl, GC_CTRL_CLK_ENABLE, 0);
+ } else {
+ outreg(host, GC_IMASK, 0);
+ }
+
+ mb862xx_i2c_exit(par);
+
+ device_remove_file(&pdev->dev, &dev_attr_dispregs);
+
+ pci_set_drvdata(pdev, NULL);
+ unregister_framebuffer(fbi);
+ fb_dealloc_cmap(&fbi->cmap);
+
+ free_irq(par->irq, (void *)par);
+ iounmap(par->mmio_base);
+ iounmap(par->fb_base);
+
+ pci_release_regions(pdev);
+ framebuffer_release(fbi);
+ pci_disable_device(pdev);
+}
+
+static struct pci_driver mb862xxfb_pci_driver = {
+ .name = DRV_NAME,
+ .id_table = mb862xx_pci_tbl,
+ .probe = mb862xx_pci_probe,
+ .remove = __devexit_p(mb862xx_pci_remove),
+};
+#endif
+
+static int __devinit mb862xxfb_init(void)
+{
+ int ret = -ENODEV;
+
+#if defined(CONFIG_FB_MB862XX_LIME)
+ ret = platform_driver_register(&of_platform_mb862xxfb_driver);
+#endif
+#if defined(CONFIG_FB_MB862XX_PCI_GDC)
+ ret = pci_register_driver(&mb862xxfb_pci_driver);
+#endif
+ return ret;
+}
+
+static void __exit mb862xxfb_exit(void)
+{
+#if defined(CONFIG_FB_MB862XX_LIME)
+ platform_driver_unregister(&of_platform_mb862xxfb_driver);
+#endif
+#if defined(CONFIG_FB_MB862XX_PCI_GDC)
+ pci_unregister_driver(&mb862xxfb_pci_driver);
+#endif
+}
+
+module_init(mb862xxfb_init);
+module_exit(mb862xxfb_exit);
+
+MODULE_DESCRIPTION("Fujitsu MB862xx Framebuffer driver");
+MODULE_AUTHOR("Anatolij Gustschin <agust@denx.de>");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/video/omap/dispc.c b/drivers/video/omap/dispc.c
index 5294834..0ccd7ad 100644
--- a/drivers/video/omap/dispc.c
+++ b/drivers/video/omap/dispc.c
@@ -922,14 +922,14 @@
return PTR_ERR(dispc.dss_ick);
}
- dispc.dss1_fck = clk_get(&dispc.fbdev->dssdev->dev, "dss1_fck");
+ dispc.dss1_fck = clk_get(&dispc.fbdev->dssdev->dev, "fck");
if (IS_ERR(dispc.dss1_fck)) {
dev_err(dispc.fbdev->dev, "can't get dss1_fck\n");
clk_put(dispc.dss_ick);
return PTR_ERR(dispc.dss1_fck);
}
- dispc.dss_54m_fck = clk_get(&dispc.fbdev->dssdev->dev, "tv_fck");
+ dispc.dss_54m_fck = clk_get(&dispc.fbdev->dssdev->dev, "tv_clk");
if (IS_ERR(dispc.dss_54m_fck)) {
dev_err(dispc.fbdev->dev, "can't get tv_fck\n");
clk_put(dispc.dss_ick);
diff --git a/drivers/video/omap/omapfb_main.c b/drivers/video/omap/omapfb_main.c
index e264efd..b3ddd74 100644
--- a/drivers/video/omap/omapfb_main.c
+++ b/drivers/video/omap/omapfb_main.c
@@ -90,7 +90,7 @@
/* dummy device for clocks */
static struct platform_device omapdss_device = {
- .name = "omapdss",
+ .name = "omapdss_dss",
.id = -1,
.dev = {
.release = omapdss_release,
diff --git a/drivers/video/omap/rfbi.c b/drivers/video/omap/rfbi.c
index eada9f1..0c6981f 100644
--- a/drivers/video/omap/rfbi.c
+++ b/drivers/video/omap/rfbi.c
@@ -90,7 +90,7 @@
return PTR_ERR(rfbi.dss_ick);
}
- rfbi.dss1_fck = clk_get(&rfbi.fbdev->dssdev->dev, "dss1_fck");
+ rfbi.dss1_fck = clk_get(&rfbi.fbdev->dssdev->dev, "fck");
if (IS_ERR(rfbi.dss1_fck)) {
dev_err(rfbi.fbdev->dev, "can't get dss1_fck\n");
clk_put(rfbi.dss_ick);
diff --git a/drivers/video/omap2/Makefile b/drivers/video/omap2/Makefile
index d853d05..5ddef12 100644
--- a/drivers/video/omap2/Makefile
+++ b/drivers/video/omap2/Makefile
@@ -1,6 +1,6 @@
obj-$(CONFIG_OMAP2_VRAM) += vram.o
obj-$(CONFIG_OMAP2_VRFB) += vrfb.o
-obj-y += dss/
-obj-y += omapfb/
+obj-$(CONFIG_OMAP2_DSS) += dss/
+obj-$(CONFIG_FB_OMAP2) += omapfb/
obj-y += displays/
diff --git a/drivers/video/omap2/displays/Kconfig b/drivers/video/omap2/displays/Kconfig
index d18ad6b..609a280 100644
--- a/drivers/video/omap2/displays/Kconfig
+++ b/drivers/video/omap2/displays/Kconfig
@@ -3,6 +3,7 @@
config PANEL_GENERIC_DPI
tristate "Generic DPI Panel"
+ depends on OMAP2_DSS_DPI
help
Generic DPI panel driver.
Supports DVI output for Beagle and OMAP3 SDP.
@@ -11,20 +12,20 @@
config PANEL_LGPHILIPS_LB035Q02
tristate "LG.Philips LB035Q02 LCD Panel"
- depends on OMAP2_DSS && SPI
+ depends on OMAP2_DSS_DPI && SPI
help
LCD Panel used on the Gumstix Overo Palo35
config PANEL_SHARP_LS037V7DW01
tristate "Sharp LS037V7DW01 LCD Panel"
- depends on OMAP2_DSS
+ depends on OMAP2_DSS_DPI
select BACKLIGHT_CLASS_DEVICE
help
LCD Panel used in TI's SDP3430 and EVM boards
config PANEL_NEC_NL8048HL11_01B
tristate "NEC NL8048HL11-01B Panel"
- depends on OMAP2_DSS
+ depends on OMAP2_DSS_DPI
help
This NEC NL8048HL11-01B panel is TFT LCD
used in the Zoom2/3/3630 sdp boards.
@@ -37,7 +38,7 @@
config PANEL_TPO_TD043MTEA1
tristate "TPO TD043MTEA1 LCD Panel"
- depends on OMAP2_DSS && SPI
+ depends on OMAP2_DSS_DPI && SPI
help
LCD Panel used in OMAP3 Pandora
diff --git a/drivers/video/omap2/displays/panel-acx565akm.c b/drivers/video/omap2/displays/panel-acx565akm.c
index 7e04c92..dbd59b8 100644
--- a/drivers/video/omap2/displays/panel-acx565akm.c
+++ b/drivers/video/omap2/displays/panel-acx565akm.c
@@ -30,7 +30,7 @@
#include <linux/backlight.h>
#include <linux/fb.h>
-#include <plat/display.h>
+#include <video/omapdss.h>
#define MIPID_CMD_READ_DISP_ID 0x04
#define MIPID_CMD_READ_RED 0x06
diff --git a/drivers/video/omap2/displays/panel-generic-dpi.c b/drivers/video/omap2/displays/panel-generic-dpi.c
index 4a9b9ff..9c90f75 100644
--- a/drivers/video/omap2/displays/panel-generic-dpi.c
+++ b/drivers/video/omap2/displays/panel-generic-dpi.c
@@ -33,8 +33,9 @@
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/slab.h>
+#include <video/omapdss.h>
-#include <plat/panel-generic-dpi.h>
+#include <video/omap-panel-generic-dpi.h>
struct panel_config {
struct omap_video_timings timings;
@@ -181,6 +182,56 @@
.power_off_delay = 0,
.name = "samsung_lte430wq_f0c",
},
+
+ /* Seiko 70WVW1TZ3Z3 */
+ {
+ {
+ .x_res = 800,
+ .y_res = 480,
+
+ .pixel_clock = 33000,
+
+ .hsw = 128,
+ .hfp = 10,
+ .hbp = 10,
+
+ .vsw = 2,
+ .vfp = 4,
+ .vbp = 11,
+ },
+ .acbi = 0x0,
+ .acb = 0x0,
+ .config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS |
+ OMAP_DSS_LCD_IHS,
+ .power_on_delay = 0,
+ .power_off_delay = 0,
+ .name = "seiko_70wvw1tz3",
+ },
+
+ /* Powertip PH480272T */
+ {
+ {
+ .x_res = 480,
+ .y_res = 272,
+
+ .pixel_clock = 9000,
+
+ .hsw = 40,
+ .hfp = 2,
+ .hbp = 2,
+
+ .vsw = 10,
+ .vfp = 2,
+ .vbp = 2,
+ },
+ .acbi = 0x0,
+ .acb = 0x0,
+ .config = OMAP_DSS_LCD_TFT | OMAP_DSS_LCD_IVS |
+ OMAP_DSS_LCD_IHS | OMAP_DSS_LCD_IEO,
+ .power_on_delay = 0,
+ .power_off_delay = 0,
+ .name = "powertip_ph480272t",
+ },
};
struct panel_drv_data {
@@ -285,7 +336,7 @@
return 0;
}
-static void generic_dpi_panel_remove(struct omap_dss_device *dssdev)
+static void __exit generic_dpi_panel_remove(struct omap_dss_device *dssdev)
{
struct panel_drv_data *drv_data = dev_get_drvdata(&dssdev->dev);
@@ -358,7 +409,7 @@
static struct omap_dss_driver dpi_driver = {
.probe = generic_dpi_panel_probe,
- .remove = generic_dpi_panel_remove,
+ .remove = __exit_p(generic_dpi_panel_remove),
.enable = generic_dpi_panel_enable,
.disable = generic_dpi_panel_disable,
diff --git a/drivers/video/omap2/displays/panel-lgphilips-lb035q02.c b/drivers/video/omap2/displays/panel-lgphilips-lb035q02.c
index 271324d..e0eb35b 100644
--- a/drivers/video/omap2/displays/panel-lgphilips-lb035q02.c
+++ b/drivers/video/omap2/displays/panel-lgphilips-lb035q02.c
@@ -21,7 +21,7 @@
#include <linux/spi/spi.h>
#include <linux/mutex.h>
-#include <plat/display.h>
+#include <video/omapdss.h>
struct lb035q02_data {
struct mutex lock;
diff --git a/drivers/video/omap2/displays/panel-nec-nl8048hl11-01b.c b/drivers/video/omap2/displays/panel-nec-nl8048hl11-01b.c
index 925e0fa..2ba9d0c 100644
--- a/drivers/video/omap2/displays/panel-nec-nl8048hl11-01b.c
+++ b/drivers/video/omap2/displays/panel-nec-nl8048hl11-01b.c
@@ -22,7 +22,7 @@
#include <linux/backlight.h>
#include <linux/fb.h>
-#include <plat/display.h>
+#include <video/omapdss.h>
#define LCD_XRES 800
#define LCD_YRES 480
diff --git a/drivers/video/omap2/displays/panel-sharp-ls037v7dw01.c b/drivers/video/omap2/displays/panel-sharp-ls037v7dw01.c
index d2b35d2..ba38b3a 100644
--- a/drivers/video/omap2/displays/panel-sharp-ls037v7dw01.c
+++ b/drivers/video/omap2/displays/panel-sharp-ls037v7dw01.c
@@ -25,7 +25,7 @@
#include <linux/err.h>
#include <linux/slab.h>
-#include <plat/display.h>
+#include <video/omapdss.h>
struct sharp_data {
struct backlight_device *bl;
@@ -120,7 +120,7 @@
return 0;
}
-static void sharp_ls_panel_remove(struct omap_dss_device *dssdev)
+static void __exit sharp_ls_panel_remove(struct omap_dss_device *dssdev)
{
struct sharp_data *sd = dev_get_drvdata(&dssdev->dev);
struct backlight_device *bl = sd->bl;
@@ -205,7 +205,7 @@
static struct omap_dss_driver sharp_ls_driver = {
.probe = sharp_ls_panel_probe,
- .remove = sharp_ls_panel_remove,
+ .remove = __exit_p(sharp_ls_panel_remove),
.enable = sharp_ls_panel_enable,
.disable = sharp_ls_panel_disable,
diff --git a/drivers/video/omap2/displays/panel-taal.c b/drivers/video/omap2/displays/panel-taal.c
index adc9900..fdd5d4ae 100644
--- a/drivers/video/omap2/displays/panel-taal.c
+++ b/drivers/video/omap2/displays/panel-taal.c
@@ -33,8 +33,8 @@
#include <linux/regulator/consumer.h>
#include <linux/mutex.h>
-#include <plat/display.h>
-#include <plat/nokia-dsi-panel.h>
+#include <video/omapdss.h>
+#include <video/omap-panel-nokia-dsi.h>
/* DSI Virtual channel. Hardcoded for now. */
#define TCH 0
@@ -63,12 +63,12 @@
#define DCS_GET_ID2 0xdb
#define DCS_GET_ID3 0xdc
-#define TAAL_ESD_CHECK_PERIOD msecs_to_jiffies(5000)
-
static irqreturn_t taal_te_isr(int irq, void *data);
static void taal_te_timeout_work_callback(struct work_struct *work);
static int _taal_enable_te(struct omap_dss_device *dssdev, bool enable);
+static int taal_panel_reset(struct omap_dss_device *dssdev);
+
struct panel_regulator {
struct regulator *regulator;
const char *name;
@@ -229,8 +229,14 @@
bool intro_printed;
- struct workqueue_struct *esd_wq;
+ struct workqueue_struct *workqueue;
+
struct delayed_work esd_work;
+ unsigned esd_interval;
+
+ bool ulps_enabled;
+ unsigned ulps_timeout;
+ struct delayed_work ulps_work;
struct panel_config *panel_config;
};
@@ -242,6 +248,7 @@
}
static void taal_esd_work(struct work_struct *work);
+static void taal_ulps_work(struct work_struct *work);
static void hw_guard_start(struct taal_data *td, int guard_msec)
{
@@ -264,7 +271,7 @@
int r;
u8 buf[1];
- r = dsi_vc_dcs_read(td->channel, dcs_cmd, buf, 1);
+ r = dsi_vc_dcs_read(td->dssdev, td->channel, dcs_cmd, buf, 1);
if (r < 0)
return r;
@@ -276,7 +283,7 @@
static int taal_dcs_write_0(struct taal_data *td, u8 dcs_cmd)
{
- return dsi_vc_dcs_write(td->channel, &dcs_cmd, 1);
+ return dsi_vc_dcs_write(td->dssdev, td->channel, &dcs_cmd, 1);
}
static int taal_dcs_write_1(struct taal_data *td, u8 dcs_cmd, u8 param)
@@ -284,7 +291,7 @@
u8 buf[2];
buf[0] = dcs_cmd;
buf[1] = param;
- return dsi_vc_dcs_write(td->channel, buf, 2);
+ return dsi_vc_dcs_write(td->dssdev, td->channel, buf, 2);
}
static int taal_sleep_in(struct taal_data *td)
@@ -296,7 +303,7 @@
hw_guard_wait(td);
cmd = DCS_SLEEP_IN;
- r = dsi_vc_dcs_write_nosync(td->channel, &cmd, 1);
+ r = dsi_vc_dcs_write_nosync(td->dssdev, td->channel, &cmd, 1);
if (r)
return r;
@@ -402,7 +409,7 @@
buf[3] = (x2 >> 8) & 0xff;
buf[4] = (x2 >> 0) & 0xff;
- r = dsi_vc_dcs_write_nosync(td->channel, buf, sizeof(buf));
+ r = dsi_vc_dcs_write_nosync(td->dssdev, td->channel, buf, sizeof(buf));
if (r)
return r;
@@ -412,15 +419,132 @@
buf[3] = (y2 >> 8) & 0xff;
buf[4] = (y2 >> 0) & 0xff;
- r = dsi_vc_dcs_write_nosync(td->channel, buf, sizeof(buf));
+ r = dsi_vc_dcs_write_nosync(td->dssdev, td->channel, buf, sizeof(buf));
if (r)
return r;
- dsi_vc_send_bta_sync(td->channel);
+ dsi_vc_send_bta_sync(td->dssdev, td->channel);
return r;
}
+static void taal_queue_esd_work(struct omap_dss_device *dssdev)
+{
+ struct taal_data *td = dev_get_drvdata(&dssdev->dev);
+
+ if (td->esd_interval > 0)
+ queue_delayed_work(td->workqueue, &td->esd_work,
+ msecs_to_jiffies(td->esd_interval));
+}
+
+static void taal_cancel_esd_work(struct omap_dss_device *dssdev)
+{
+ struct taal_data *td = dev_get_drvdata(&dssdev->dev);
+
+ cancel_delayed_work(&td->esd_work);
+}
+
+static void taal_queue_ulps_work(struct omap_dss_device *dssdev)
+{
+ struct taal_data *td = dev_get_drvdata(&dssdev->dev);
+
+ if (td->ulps_timeout > 0)
+ queue_delayed_work(td->workqueue, &td->ulps_work,
+ msecs_to_jiffies(td->ulps_timeout));
+}
+
+static void taal_cancel_ulps_work(struct omap_dss_device *dssdev)
+{
+ struct taal_data *td = dev_get_drvdata(&dssdev->dev);
+
+ cancel_delayed_work(&td->ulps_work);
+}
+
+static int taal_enter_ulps(struct omap_dss_device *dssdev)
+{
+ struct taal_data *td = dev_get_drvdata(&dssdev->dev);
+ struct nokia_dsi_panel_data *panel_data = get_panel_data(dssdev);
+ int r;
+
+ if (td->ulps_enabled)
+ return 0;
+
+ taal_cancel_ulps_work(dssdev);
+
+ r = _taal_enable_te(dssdev, false);
+ if (r)
+ goto err;
+
+ disable_irq(gpio_to_irq(panel_data->ext_te_gpio));
+
+ omapdss_dsi_display_disable(dssdev, false, true);
+
+ td->ulps_enabled = true;
+
+ return 0;
+
+err:
+ dev_err(&dssdev->dev, "enter ULPS failed");
+ taal_panel_reset(dssdev);
+
+ td->ulps_enabled = false;
+
+ taal_queue_ulps_work(dssdev);
+
+ return r;
+}
+
+static int taal_exit_ulps(struct omap_dss_device *dssdev)
+{
+ struct taal_data *td = dev_get_drvdata(&dssdev->dev);
+ struct nokia_dsi_panel_data *panel_data = get_panel_data(dssdev);
+ int r;
+
+ if (!td->ulps_enabled)
+ return 0;
+
+ r = omapdss_dsi_display_enable(dssdev);
+ if (r)
+ goto err;
+
+ omapdss_dsi_vc_enable_hs(dssdev, td->channel, true);
+
+ r = _taal_enable_te(dssdev, true);
+ if (r)
+ goto err;
+
+ enable_irq(gpio_to_irq(panel_data->ext_te_gpio));
+
+ taal_queue_ulps_work(dssdev);
+
+ td->ulps_enabled = false;
+
+ return 0;
+
+err:
+ dev_err(&dssdev->dev, "exit ULPS failed");
+ r = taal_panel_reset(dssdev);
+
+ enable_irq(gpio_to_irq(panel_data->ext_te_gpio));
+ td->ulps_enabled = false;
+
+ taal_queue_ulps_work(dssdev);
+
+ return r;
+}
+
+static int taal_wake_up(struct omap_dss_device *dssdev)
+{
+ struct taal_data *td = dev_get_drvdata(&dssdev->dev);
+
+ if (td->ulps_enabled)
+ return taal_exit_ulps(dssdev);
+
+ taal_cancel_ulps_work(dssdev);
+ taal_queue_ulps_work(dssdev);
+ return 0;
+}
+
static int taal_bl_update_status(struct backlight_device *dev)
{
struct omap_dss_device *dssdev = dev_get_drvdata(&dev->dev);
@@ -441,9 +565,13 @@
if (td->use_dsi_bl) {
if (td->enabled) {
- dsi_bus_lock();
- r = taal_dcs_write_1(td, DCS_BRIGHTNESS, level);
- dsi_bus_unlock();
+ dsi_bus_lock(dssdev);
+
+ r = taal_wake_up(dssdev);
+ if (!r)
+ r = taal_dcs_write_1(td, DCS_BRIGHTNESS, level);
+
+ dsi_bus_unlock(dssdev);
} else {
r = 0;
}
@@ -504,9 +632,13 @@
mutex_lock(&td->lock);
if (td->enabled) {
- dsi_bus_lock();
- r = taal_dcs_read_1(td, DCS_READ_NUM_ERRORS, &errors);
- dsi_bus_unlock();
+ dsi_bus_lock(dssdev);
+
+ r = taal_wake_up(dssdev);
+ if (!r)
+ r = taal_dcs_read_1(td, DCS_READ_NUM_ERRORS, &errors);
+
+ dsi_bus_unlock(dssdev);
} else {
r = -ENODEV;
}
@@ -530,9 +662,13 @@
mutex_lock(&td->lock);
if (td->enabled) {
- dsi_bus_lock();
- r = taal_get_id(td, &id1, &id2, &id3);
- dsi_bus_unlock();
+ dsi_bus_lock(dssdev);
+
+ r = taal_wake_up(dssdev);
+ if (!r)
+ r = taal_get_id(td, &id1, &id2, &id3);
+
+ dsi_bus_unlock(dssdev);
} else {
r = -ENODEV;
}
@@ -579,6 +715,7 @@
struct omap_dss_device *dssdev = to_dss_device(dev);
struct taal_data *td = dev_get_drvdata(&dssdev->dev);
int i;
+ int r;
for (i = 0; i < ARRAY_SIZE(cabc_modes); i++) {
if (sysfs_streq(cabc_modes[i], buf))
@@ -591,10 +728,19 @@
mutex_lock(&td->lock);
if (td->enabled) {
- dsi_bus_lock();
- if (!td->cabc_broken)
- taal_dcs_write_1(td, DCS_WRITE_CABC, i);
- dsi_bus_unlock();
+ dsi_bus_lock(dssdev);
+
+ if (!td->cabc_broken) {
+ r = taal_wake_up(dssdev);
+ if (r)
+ goto err;
+
+ r = taal_dcs_write_1(td, DCS_WRITE_CABC, i);
+ if (r)
+ goto err;
+ }
+
+ dsi_bus_unlock(dssdev);
}
td->cabc_mode = i;
@@ -602,6 +748,10 @@
mutex_unlock(&td->lock);
return count;
+err:
+ dsi_bus_unlock(dssdev);
+ mutex_unlock(&td->lock);
+ return r;
}
static ssize_t show_cabc_available_modes(struct device *dev,
@@ -620,18 +770,161 @@
return len < PAGE_SIZE ? len : PAGE_SIZE - 1;
}
+static ssize_t taal_store_esd_interval(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct omap_dss_device *dssdev = to_dss_device(dev);
+ struct taal_data *td = dev_get_drvdata(&dssdev->dev);
+
+ unsigned long t;
+ int r;
+
+ r = strict_strtoul(buf, 10, &t);
+ if (r)
+ return r;
+
+ mutex_lock(&td->lock);
+ taal_cancel_esd_work(dssdev);
+ td->esd_interval = t;
+ if (td->enabled)
+ taal_queue_esd_work(dssdev);
+ mutex_unlock(&td->lock);
+
+ return count;
+}
+
+static ssize_t taal_show_esd_interval(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct omap_dss_device *dssdev = to_dss_device(dev);
+ struct taal_data *td = dev_get_drvdata(&dssdev->dev);
+ unsigned t;
+
+ mutex_lock(&td->lock);
+ t = td->esd_interval;
+ mutex_unlock(&td->lock);
+
+ return snprintf(buf, PAGE_SIZE, "%u\n", t);
+}
+
+static ssize_t taal_store_ulps(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct omap_dss_device *dssdev = to_dss_device(dev);
+ struct taal_data *td = dev_get_drvdata(&dssdev->dev);
+ unsigned long t;
+ int r;
+
+ r = strict_strtoul(buf, 10, &t);
+ if (r)
+ return r;
+
+ mutex_lock(&td->lock);
+
+ if (td->enabled) {
+ dsi_bus_lock(dssdev);
+
+ if (t)
+ r = taal_enter_ulps(dssdev);
+ else
+ r = taal_wake_up(dssdev);
+
+ dsi_bus_unlock(dssdev);
+ }
+
+ mutex_unlock(&td->lock);
+
+ if (r)
+ return r;
+
+ return count;
+}
+
+static ssize_t taal_show_ulps(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct omap_dss_device *dssdev = to_dss_device(dev);
+ struct taal_data *td = dev_get_drvdata(&dssdev->dev);
+ unsigned t;
+
+ mutex_lock(&td->lock);
+ t = td->ulps_enabled;
+ mutex_unlock(&td->lock);
+
+ return snprintf(buf, PAGE_SIZE, "%u\n", t);
+}
+
+static ssize_t taal_store_ulps_timeout(struct device *dev,
+ struct device_attribute *attr,
+ const char *buf, size_t count)
+{
+ struct omap_dss_device *dssdev = to_dss_device(dev);
+ struct taal_data *td = dev_get_drvdata(&dssdev->dev);
+ unsigned long t;
+ int r;
+
+ r = strict_strtoul(buf, 10, &t);
+ if (r)
+ return r;
+
+ mutex_lock(&td->lock);
+ td->ulps_timeout = t;
+
+ if (td->enabled) {
+ /* taal_wake_up will restart the timer */
+ dsi_bus_lock(dssdev);
+ r = taal_wake_up(dssdev);
+ dsi_bus_unlock(dssdev);
+ }
+
+ mutex_unlock(&td->lock);
+
+ if (r)
+ return r;
+
+ return count;
+}
+
+static ssize_t taal_show_ulps_timeout(struct device *dev,
+ struct device_attribute *attr,
+ char *buf)
+{
+ struct omap_dss_device *dssdev = to_dss_device(dev);
+ struct taal_data *td = dev_get_drvdata(&dssdev->dev);
+ unsigned t;
+
+ mutex_lock(&td->lock);
+ t = td->ulps_timeout;
+ mutex_unlock(&td->lock);
+
+ return snprintf(buf, PAGE_SIZE, "%u\n", t);
+}
+
static DEVICE_ATTR(num_dsi_errors, S_IRUGO, taal_num_errors_show, NULL);
static DEVICE_ATTR(hw_revision, S_IRUGO, taal_hw_revision_show, NULL);
static DEVICE_ATTR(cabc_mode, S_IRUGO | S_IWUSR,
show_cabc_mode, store_cabc_mode);
static DEVICE_ATTR(cabc_available_modes, S_IRUGO,
show_cabc_available_modes, NULL);
+static DEVICE_ATTR(esd_interval, S_IRUGO | S_IWUSR,
+ taal_show_esd_interval, taal_store_esd_interval);
+static DEVICE_ATTR(ulps, S_IRUGO | S_IWUSR,
+ taal_show_ulps, taal_store_ulps);
+static DEVICE_ATTR(ulps_timeout, S_IRUGO | S_IWUSR,
+ taal_show_ulps_timeout, taal_store_ulps_timeout);
static struct attribute *taal_attrs[] = {
&dev_attr_num_dsi_errors.attr,
&dev_attr_hw_revision.attr,
&dev_attr_cabc_mode.attr,
&dev_attr_cabc_available_modes.attr,
+ &dev_attr_esd_interval.attr,
+ &dev_attr_ulps.attr,
+ &dev_attr_ulps_timeout.attr,
NULL,
};
@@ -700,6 +993,9 @@
}
td->dssdev = dssdev;
td->panel_config = panel_config;
+ td->esd_interval = panel_data->esd_interval;
+ td->ulps_enabled = false;
+ td->ulps_timeout = panel_data->ulps_timeout;
mutex_init(&td->lock);
@@ -710,13 +1006,14 @@
if (r)
goto err_reg;
- td->esd_wq = create_singlethread_workqueue("taal_esd");
- if (td->esd_wq == NULL) {
+ td->workqueue = create_singlethread_workqueue("taal_esd");
+ if (td->workqueue == NULL) {
dev_err(&dssdev->dev, "can't create ESD workqueue\n");
r = -ENOMEM;
goto err_wq;
}
INIT_DELAYED_WORK_DEFERRABLE(&td->esd_work, taal_esd_work);
+ INIT_DELAYED_WORK(&td->ulps_work, taal_ulps_work);
dev_set_drvdata(&dssdev->dev, td);
@@ -734,8 +1031,8 @@
props.max_brightness = 127;
props.type = BACKLIGHT_RAW;
- bldev = backlight_device_register("taal", &dssdev->dev, dssdev,
- &taal_bl_ops, &props);
+ bldev = backlight_device_register(dev_name(&dssdev->dev), &dssdev->dev,
+ dssdev, &taal_bl_ops, &props);
if (IS_ERR(bldev)) {
r = PTR_ERR(bldev);
goto err_bl;
@@ -810,7 +1107,7 @@
err_gpio:
backlight_device_unregister(bldev);
err_bl:
- destroy_workqueue(td->esd_wq);
+ destroy_workqueue(td->workqueue);
err_wq:
free_regulators(panel_config->regulators, panel_config->num_regulators);
err_reg:
@@ -819,7 +1116,7 @@
return r;
}
-static void taal_remove(struct omap_dss_device *dssdev)
+static void __exit taal_remove(struct omap_dss_device *dssdev)
{
struct taal_data *td = dev_get_drvdata(&dssdev->dev);
struct nokia_dsi_panel_data *panel_data = get_panel_data(dssdev);
@@ -841,8 +1138,9 @@
taal_bl_update_status(bldev);
backlight_device_unregister(bldev);
- cancel_delayed_work(&td->esd_work);
- destroy_workqueue(td->esd_wq);
+ taal_cancel_ulps_work(dssdev);
+ taal_cancel_esd_work(dssdev);
+ destroy_workqueue(td->workqueue);
/* reset, to be sure that the panel is in a valid state */
taal_hw_reset(dssdev);
@@ -867,7 +1165,7 @@
taal_hw_reset(dssdev);
- omapdss_dsi_vc_enable_hs(td->channel, false);
+ omapdss_dsi_vc_enable_hs(dssdev, td->channel, false);
r = taal_sleep_out(td);
if (r)
@@ -924,7 +1222,7 @@
td->intro_printed = true;
}
- omapdss_dsi_vc_enable_hs(td->channel, true);
+ omapdss_dsi_vc_enable_hs(dssdev, td->channel, true);
return 0;
err:
@@ -932,7 +1230,7 @@
taal_hw_reset(dssdev);
- omapdss_dsi_display_disable(dssdev);
+ omapdss_dsi_display_disable(dssdev, true, false);
err0:
return r;
}
@@ -955,15 +1253,23 @@
taal_hw_reset(dssdev);
}
- omapdss_dsi_display_disable(dssdev);
+ omapdss_dsi_display_disable(dssdev, true, false);
td->enabled = 0;
}
+static int taal_panel_reset(struct omap_dss_device *dssdev)
+{
+ dev_err(&dssdev->dev, "performing LCD reset\n");
+
+ taal_power_off(dssdev);
+ taal_hw_reset(dssdev);
+ return taal_power_on(dssdev);
+}
+
static int taal_enable(struct omap_dss_device *dssdev)
{
struct taal_data *td = dev_get_drvdata(&dssdev->dev);
- struct nokia_dsi_panel_data *panel_data = get_panel_data(dssdev);
int r;
dev_dbg(&dssdev->dev, "enable\n");
@@ -975,18 +1281,16 @@
goto err;
}
- dsi_bus_lock();
+ dsi_bus_lock(dssdev);
r = taal_power_on(dssdev);
- dsi_bus_unlock();
+ dsi_bus_unlock(dssdev);
if (r)
goto err;
- if (panel_data->use_esd_check)
- queue_delayed_work(td->esd_wq, &td->esd_work,
- TAAL_ESD_CHECK_PERIOD);
+ taal_queue_esd_work(dssdev);
dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
@@ -1007,14 +1311,17 @@
mutex_lock(&td->lock);
- cancel_delayed_work(&td->esd_work);
+ taal_cancel_ulps_work(dssdev);
+ taal_cancel_esd_work(dssdev);
- dsi_bus_lock();
+ dsi_bus_lock(dssdev);
- if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE)
+ if (dssdev->state == OMAP_DSS_DISPLAY_ACTIVE) {
+ taal_wake_up(dssdev);
taal_power_off(dssdev);
+ }
- dsi_bus_unlock();
+ dsi_bus_unlock(dssdev);
dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
@@ -1035,13 +1342,16 @@
goto err;
}
- cancel_delayed_work(&td->esd_work);
+ taal_cancel_ulps_work(dssdev);
+ taal_cancel_esd_work(dssdev);
- dsi_bus_lock();
+ dsi_bus_lock(dssdev);
- taal_power_off(dssdev);
+ r = taal_wake_up(dssdev);
+ if (!r)
+ taal_power_off(dssdev);
- dsi_bus_unlock();
+ dsi_bus_unlock(dssdev);
dssdev->state = OMAP_DSS_DISPLAY_SUSPENDED;
@@ -1056,7 +1366,6 @@
static int taal_resume(struct omap_dss_device *dssdev)
{
struct taal_data *td = dev_get_drvdata(&dssdev->dev);
- struct nokia_dsi_panel_data *panel_data = get_panel_data(dssdev);
int r;
dev_dbg(&dssdev->dev, "resume\n");
@@ -1068,19 +1377,17 @@
goto err;
}
- dsi_bus_lock();
+ dsi_bus_lock(dssdev);
r = taal_power_on(dssdev);
- dsi_bus_unlock();
+ dsi_bus_unlock(dssdev);
if (r) {
dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
} else {
dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
- if (panel_data->use_esd_check)
- queue_delayed_work(td->esd_wq, &td->esd_work,
- TAAL_ESD_CHECK_PERIOD);
+ taal_queue_esd_work(dssdev);
}
mutex_unlock(&td->lock);
@@ -1095,7 +1402,7 @@
{
struct omap_dss_device *dssdev = data;
dev_dbg(&dssdev->dev, "framedone, err %d\n", err);
- dsi_bus_unlock();
+ dsi_bus_unlock(dssdev);
}
static irqreturn_t taal_te_isr(int irq, void *data)
@@ -1123,7 +1430,7 @@
return IRQ_HANDLED;
err:
dev_err(&dssdev->dev, "start update failed\n");
- dsi_bus_unlock();
+ dsi_bus_unlock(dssdev);
return IRQ_HANDLED;
}
@@ -1136,7 +1443,7 @@
dev_err(&dssdev->dev, "TE not received for 250ms!\n");
atomic_set(&td->do_update, 0);
- dsi_bus_unlock();
+ dsi_bus_unlock(dssdev);
}
static int taal_update(struct omap_dss_device *dssdev,
@@ -1149,7 +1456,11 @@
dev_dbg(&dssdev->dev, "update %d, %d, %d x %d\n", x, y, w, h);
mutex_lock(&td->lock);
- dsi_bus_lock();
+ dsi_bus_lock(dssdev);
+
+ r = taal_wake_up(dssdev);
+ if (r)
+ goto err;
if (!td->enabled) {
r = 0;
@@ -1184,7 +1495,7 @@
mutex_unlock(&td->lock);
return 0;
err:
- dsi_bus_unlock();
+ dsi_bus_unlock(dssdev);
mutex_unlock(&td->lock);
return r;
}
@@ -1196,8 +1507,8 @@
dev_dbg(&dssdev->dev, "sync\n");
mutex_lock(&td->lock);
- dsi_bus_lock();
- dsi_bus_unlock();
+ dsi_bus_lock(dssdev);
+ dsi_bus_unlock(dssdev);
mutex_unlock(&td->lock);
dev_dbg(&dssdev->dev, "sync done\n");
@@ -1235,9 +1546,13 @@
if (td->te_enabled == enable)
goto end;
- dsi_bus_lock();
+ dsi_bus_lock(dssdev);
if (td->enabled) {
+ r = taal_wake_up(dssdev);
+ if (r)
+ goto err;
+
r = _taal_enable_te(dssdev, enable);
if (r)
goto err;
@@ -1245,13 +1560,13 @@
td->te_enabled = enable;
- dsi_bus_unlock();
+ dsi_bus_unlock(dssdev);
end:
mutex_unlock(&td->lock);
return 0;
err:
- dsi_bus_unlock();
+ dsi_bus_unlock(dssdev);
mutex_unlock(&td->lock);
return r;
@@ -1281,9 +1596,13 @@
if (td->rotate == rotate)
goto end;
- dsi_bus_lock();
+ dsi_bus_lock(dssdev);
if (td->enabled) {
+ r = taal_wake_up(dssdev);
+ if (r)
+ goto err;
+
r = taal_set_addr_mode(td, rotate, td->mirror);
if (r)
goto err;
@@ -1291,12 +1610,12 @@
td->rotate = rotate;
- dsi_bus_unlock();
+ dsi_bus_unlock(dssdev);
end:
mutex_unlock(&td->lock);
return 0;
err:
- dsi_bus_unlock();
+ dsi_bus_unlock(dssdev);
mutex_unlock(&td->lock);
return r;
}
@@ -1325,8 +1644,12 @@
if (td->mirror == enable)
goto end;
- dsi_bus_lock();
+ dsi_bus_lock(dssdev);
if (td->enabled) {
+ r = taal_wake_up(dssdev);
+ if (r)
+ goto err;
+
r = taal_set_addr_mode(td, td->rotate, enable);
if (r)
goto err;
@@ -1334,12 +1657,12 @@
td->mirror = enable;
- dsi_bus_unlock();
+ dsi_bus_unlock(dssdev);
end:
mutex_unlock(&td->lock);
return 0;
err:
- dsi_bus_unlock();
+ dsi_bus_unlock(dssdev);
mutex_unlock(&td->lock);
return r;
}
@@ -1369,7 +1692,11 @@
goto err1;
}
- dsi_bus_lock();
+ dsi_bus_lock(dssdev);
+
+ r = taal_wake_up(dssdev);
+ if (r)
+ goto err2;
r = taal_dcs_read_1(td, DCS_GET_ID1, &id1);
if (r)
@@ -1381,11 +1708,11 @@
if (r)
goto err2;
- dsi_bus_unlock();
+ dsi_bus_unlock(dssdev);
mutex_unlock(&td->lock);
return 0;
err2:
- dsi_bus_unlock();
+ dsi_bus_unlock(dssdev);
err1:
mutex_unlock(&td->lock);
return r;
@@ -1415,7 +1742,11 @@
dssdev->panel.timings.x_res *
dssdev->panel.timings.y_res * 3);
- dsi_bus_lock();
+ dsi_bus_lock(dssdev);
+
+ r = taal_wake_up(dssdev);
+ if (r)
+ goto err2;
/* plen 1 or 2 goes into short packet. until checksum error is fixed,
* use short packets. plen 32 works, but bigger packets seem to cause
@@ -1427,7 +1758,7 @@
taal_set_update_window(td, x, y, w, h);
- r = dsi_vc_set_max_rx_packet_size(td->channel, plen);
+ r = dsi_vc_set_max_rx_packet_size(dssdev, td->channel, plen);
if (r)
goto err2;
@@ -1435,7 +1766,7 @@
u8 dcs_cmd = first ? 0x2e : 0x3e;
first = 0;
- r = dsi_vc_dcs_read(td->channel, dcs_cmd,
+ r = dsi_vc_dcs_read(dssdev, td->channel, dcs_cmd,
buf + buf_used, size - buf_used);
if (r < 0) {
@@ -1461,14 +1792,35 @@
r = buf_used;
err3:
- dsi_vc_set_max_rx_packet_size(td->channel, 1);
+ dsi_vc_set_max_rx_packet_size(dssdev, td->channel, 1);
err2:
- dsi_bus_unlock();
+ dsi_bus_unlock(dssdev);
err1:
mutex_unlock(&td->lock);
return r;
}
+static void taal_ulps_work(struct work_struct *work)
+{
+ struct taal_data *td = container_of(work, struct taal_data,
+ ulps_work.work);
+ struct omap_dss_device *dssdev = td->dssdev;
+
+ mutex_lock(&td->lock);
+
+ if (dssdev->state != OMAP_DSS_DISPLAY_ACTIVE || !td->enabled) {
+ mutex_unlock(&td->lock);
+ return;
+ }
+
+ dsi_bus_lock(dssdev);
+
+ taal_enter_ulps(dssdev);
+
+ dsi_bus_unlock(dssdev);
+ mutex_unlock(&td->lock);
+}
+
static void taal_esd_work(struct work_struct *work)
{
struct taal_data *td = container_of(work, struct taal_data,
@@ -1485,7 +1837,13 @@
return;
}
- dsi_bus_lock();
+ dsi_bus_lock(dssdev);
+
+ r = taal_wake_up(dssdev);
+ if (r) {
+ dev_err(&dssdev->dev, "failed to exit ULPS\n");
+ goto err;
+ }
r = taal_dcs_read_1(td, DCS_RDDSDR, &state1);
if (r) {
@@ -1521,22 +1879,20 @@
goto err;
}
- dsi_bus_unlock();
+ dsi_bus_unlock(dssdev);
- queue_delayed_work(td->esd_wq, &td->esd_work, TAAL_ESD_CHECK_PERIOD);
+ taal_queue_esd_work(dssdev);
mutex_unlock(&td->lock);
return;
err:
dev_err(&dssdev->dev, "performing LCD reset\n");
- taal_power_off(dssdev);
- taal_hw_reset(dssdev);
- taal_power_on(dssdev);
+ taal_panel_reset(dssdev);
- dsi_bus_unlock();
+ dsi_bus_unlock(dssdev);
- queue_delayed_work(td->esd_wq, &td->esd_work, TAAL_ESD_CHECK_PERIOD);
+ taal_queue_esd_work(dssdev);
mutex_unlock(&td->lock);
}
@@ -1557,7 +1913,7 @@
static struct omap_dss_driver taal_driver = {
.probe = taal_probe,
- .remove = taal_remove,
+ .remove = __exit_p(taal_remove),
.enable = taal_enable,
.disable = taal_disable,
diff --git a/drivers/video/omap2/displays/panel-tpo-td043mtea1.c b/drivers/video/omap2/displays/panel-tpo-td043mtea1.c
index dbe9d43..2462b9e 100644
--- a/drivers/video/omap2/displays/panel-tpo-td043mtea1.c
+++ b/drivers/video/omap2/displays/panel-tpo-td043mtea1.c
@@ -17,7 +17,7 @@
#include <linux/err.h>
#include <linux/slab.h>
-#include <plat/display.h>
+#include <video/omapdss.h>
#define TPO_R02_MODE(x) ((x) & 7)
#define TPO_R02_MODE_800x480 7
@@ -144,13 +144,15 @@
struct device_attribute *attr, const char *buf, size_t count)
{
struct tpo_td043_device *tpo_td043 = dev_get_drvdata(dev);
- long val;
+ int val;
int ret;
- ret = strict_strtol(buf, 0, &val);
+ ret = kstrtoint(buf, 0, &val);
if (ret < 0)
return ret;
+ val = !!val;
+
ret = tpo_td043_write_mirror(tpo_td043->spi, tpo_td043->hmirror, val);
if (ret < 0)
return ret;
@@ -175,7 +177,7 @@
long val;
int ret;
- ret = strict_strtol(buf, 0, &val);
+ ret = kstrtol(buf, 0, &val);
if (ret != 0 || val & ~7)
return -EINVAL;
diff --git a/drivers/video/omap2/dss/Kconfig b/drivers/video/omap2/dss/Kconfig
index bfc5da0..6b3e2da 100644
--- a/drivers/video/omap2/dss/Kconfig
+++ b/drivers/video/omap2/dss/Kconfig
@@ -80,7 +80,7 @@
config OMAP2_DSS_DSI
bool "DSI support"
- depends on ARCH_OMAP3
+ depends on ARCH_OMAP3 || ARCH_OMAP4
default n
help
MIPI DSI (Display Serial Interface) support.
@@ -90,14 +90,6 @@
See http://www.mipi.org/ for DSI spesifications.
-config OMAP2_DSS_USE_DSI_PLL
- bool "Use DSI PLL for PCLK (EXPERIMENTAL)"
- default n
- depends on OMAP2_DSS_DSI
- help
- Use DSI PLL to generate pixel clock. Currently only for DPI output.
- DSI PLL can be used to generate higher and more precise pixel clocks.
-
config OMAP2_DSS_FAKE_VSYNC
bool "Fake VSYNC irq from manual update displays"
default n
@@ -125,4 +117,27 @@
Max FCK is 173MHz, so this doesn't work if your PCK
is very high.
+config OMAP2_DSS_SLEEP_BEFORE_RESET
+ bool "Sleep 50ms before DSS reset"
+ default y
+ help
+ For some unknown reason we may get SYNC_LOST errors from the display
+ subsystem at initialization time if we don't sleep before resetting
+ the DSS. See the source (dss.c) for more comments.
+
+ However, 50ms is quite long time to sleep, and with some
+ configurations the SYNC_LOST may never happen, so the sleep can
+ be disabled here.
+
+config OMAP2_DSS_SLEEP_AFTER_VENC_RESET
+ bool "Sleep 20ms after VENC reset"
+ default y
+ help
+ There is a 20ms sleep after VENC reset which seemed to fix the
+ reset. The reason for the bug is unclear, and it's also unclear
+ on what platforms this happens.
+
+ This option enables the sleep, and is enabled by default. You can
+ disable the sleep if it doesn't cause problems on your platform.
+
endif
diff --git a/drivers/video/omap2/dss/core.c b/drivers/video/omap2/dss/core.c
index 1aa2ed1..3da4267 100644
--- a/drivers/video/omap2/dss/core.c
+++ b/drivers/video/omap2/dss/core.c
@@ -33,7 +33,7 @@
#include <linux/device.h>
#include <linux/regulator/consumer.h>
-#include <plat/display.h>
+#include <video/omapdss.h>
#include "dss.h"
#include "dss_features.h"
@@ -54,6 +54,9 @@
module_param_named(debug, dss_debug, bool, 0644);
#endif
+static int omap_dss_register_device(struct omap_dss_device *);
+static void omap_dss_unregister_device(struct omap_dss_device *);
+
/* REGULATORS */
struct regulator *dss_get_vdds_dsi(void)
@@ -124,8 +127,7 @@
#endif
#if defined(CONFIG_OMAP2_DSS_DSI) && defined(CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS)
- debugfs_create_file("dsi_irq", S_IRUGO, dss_debugfs_dir,
- &dsi_dump_irqs, &dss_debug_fops);
+ dsi_create_debugfs_files_irq(dss_debugfs_dir, &dss_debug_fops);
#endif
debugfs_create_file("dss", S_IRUGO, dss_debugfs_dir,
@@ -137,8 +139,7 @@
&rfbi_dump_regs, &dss_debug_fops);
#endif
#ifdef CONFIG_OMAP2_DSS_DSI
- debugfs_create_file("dsi", S_IRUGO, dss_debugfs_dir,
- &dsi_dump_regs, &dss_debug_fops);
+ dsi_create_debugfs_files_reg(dss_debugfs_dir, &dss_debug_fops);
#endif
#ifdef CONFIG_OMAP2_DSS_VENC
debugfs_create_file("venc", S_IRUGO, dss_debugfs_dir,
@@ -480,7 +481,7 @@
reset_device(dev, 0);
}
-int omap_dss_register_device(struct omap_dss_device *dssdev)
+static int omap_dss_register_device(struct omap_dss_device *dssdev)
{
static int dev_num;
@@ -494,7 +495,7 @@
return device_register(&dssdev->dev);
}
-void omap_dss_unregister_device(struct omap_dss_device *dssdev)
+static void omap_dss_unregister_device(struct omap_dss_device *dssdev)
{
device_unregister(&dssdev->dev);
}
diff --git a/drivers/video/omap2/dss/dispc.c b/drivers/video/omap2/dss/dispc.c
index 7804779..7a9a2e7 100644
--- a/drivers/video/omap2/dss/dispc.c
+++ b/drivers/video/omap2/dss/dispc.c
@@ -37,99 +37,15 @@
#include <plat/sram.h>
#include <plat/clock.h>
-#include <plat/display.h>
+#include <video/omapdss.h>
#include "dss.h"
#include "dss_features.h"
+#include "dispc.h"
/* DISPC */
#define DISPC_SZ_REGS SZ_4K
-struct dispc_reg { u16 idx; };
-
-#define DISPC_REG(idx) ((const struct dispc_reg) { idx })
-
-/*
- * DISPC common registers and
- * DISPC channel registers , ch = 0 for LCD, ch = 1 for
- * DIGIT, and ch = 2 for LCD2
- */
-#define DISPC_REVISION DISPC_REG(0x0000)
-#define DISPC_SYSCONFIG DISPC_REG(0x0010)
-#define DISPC_SYSSTATUS DISPC_REG(0x0014)
-#define DISPC_IRQSTATUS DISPC_REG(0x0018)
-#define DISPC_IRQENABLE DISPC_REG(0x001C)
-#define DISPC_CONTROL DISPC_REG(0x0040)
-#define DISPC_CONTROL2 DISPC_REG(0x0238)
-#define DISPC_CONFIG DISPC_REG(0x0044)
-#define DISPC_CONFIG2 DISPC_REG(0x0620)
-#define DISPC_CAPABLE DISPC_REG(0x0048)
-#define DISPC_DEFAULT_COLOR(ch) DISPC_REG(ch == 0 ? 0x004C : \
- (ch == 1 ? 0x0050 : 0x03AC))
-#define DISPC_TRANS_COLOR(ch) DISPC_REG(ch == 0 ? 0x0054 : \
- (ch == 1 ? 0x0058 : 0x03B0))
-#define DISPC_LINE_STATUS DISPC_REG(0x005C)
-#define DISPC_LINE_NUMBER DISPC_REG(0x0060)
-#define DISPC_TIMING_H(ch) DISPC_REG(ch != 2 ? 0x0064 : 0x0400)
-#define DISPC_TIMING_V(ch) DISPC_REG(ch != 2 ? 0x0068 : 0x0404)
-#define DISPC_POL_FREQ(ch) DISPC_REG(ch != 2 ? 0x006C : 0x0408)
-#define DISPC_DIVISORo(ch) DISPC_REG(ch != 2 ? 0x0070 : 0x040C)
-#define DISPC_GLOBAL_ALPHA DISPC_REG(0x0074)
-#define DISPC_SIZE_DIG DISPC_REG(0x0078)
-#define DISPC_SIZE_LCD(ch) DISPC_REG(ch != 2 ? 0x007C : 0x03CC)
-
-/* DISPC GFX plane */
-#define DISPC_GFX_BA0 DISPC_REG(0x0080)
-#define DISPC_GFX_BA1 DISPC_REG(0x0084)
-#define DISPC_GFX_POSITION DISPC_REG(0x0088)
-#define DISPC_GFX_SIZE DISPC_REG(0x008C)
-#define DISPC_GFX_ATTRIBUTES DISPC_REG(0x00A0)
-#define DISPC_GFX_FIFO_THRESHOLD DISPC_REG(0x00A4)
-#define DISPC_GFX_FIFO_SIZE_STATUS DISPC_REG(0x00A8)
-#define DISPC_GFX_ROW_INC DISPC_REG(0x00AC)
-#define DISPC_GFX_PIXEL_INC DISPC_REG(0x00B0)
-#define DISPC_GFX_WINDOW_SKIP DISPC_REG(0x00B4)
-#define DISPC_GFX_TABLE_BA DISPC_REG(0x00B8)
-
-#define DISPC_DATA_CYCLE1(ch) DISPC_REG(ch != 2 ? 0x01D4 : 0x03C0)
-#define DISPC_DATA_CYCLE2(ch) DISPC_REG(ch != 2 ? 0x01D8 : 0x03C4)
-#define DISPC_DATA_CYCLE3(ch) DISPC_REG(ch != 2 ? 0x01DC : 0x03C8)
-#define DISPC_CPR_COEF_R(ch) DISPC_REG(ch != 2 ? 0x0220 : 0x03BC)
-#define DISPC_CPR_COEF_G(ch) DISPC_REG(ch != 2 ? 0x0224 : 0x03B8)
-#define DISPC_CPR_COEF_B(ch) DISPC_REG(ch != 2 ? 0x0228 : 0x03B4)
-
-#define DISPC_GFX_PRELOAD DISPC_REG(0x022C)
-
-/* DISPC Video plane, n = 0 for VID1 and n = 1 for VID2 */
-#define DISPC_VID_REG(n, idx) DISPC_REG(0x00BC + (n)*0x90 + idx)
-
-#define DISPC_VID_BA0(n) DISPC_VID_REG(n, 0x0000)
-#define DISPC_VID_BA1(n) DISPC_VID_REG(n, 0x0004)
-#define DISPC_VID_POSITION(n) DISPC_VID_REG(n, 0x0008)
-#define DISPC_VID_SIZE(n) DISPC_VID_REG(n, 0x000C)
-#define DISPC_VID_ATTRIBUTES(n) DISPC_VID_REG(n, 0x0010)
-#define DISPC_VID_FIFO_THRESHOLD(n) DISPC_VID_REG(n, 0x0014)
-#define DISPC_VID_FIFO_SIZE_STATUS(n) DISPC_VID_REG(n, 0x0018)
-#define DISPC_VID_ROW_INC(n) DISPC_VID_REG(n, 0x001C)
-#define DISPC_VID_PIXEL_INC(n) DISPC_VID_REG(n, 0x0020)
-#define DISPC_VID_FIR(n) DISPC_VID_REG(n, 0x0024)
-#define DISPC_VID_PICTURE_SIZE(n) DISPC_VID_REG(n, 0x0028)
-#define DISPC_VID_ACCU0(n) DISPC_VID_REG(n, 0x002C)
-#define DISPC_VID_ACCU1(n) DISPC_VID_REG(n, 0x0030)
-
-/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
-#define DISPC_VID_FIR_COEF_H(n, i) DISPC_REG(0x00F0 + (n)*0x90 + (i)*0x8)
-/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
-#define DISPC_VID_FIR_COEF_HV(n, i) DISPC_REG(0x00F4 + (n)*0x90 + (i)*0x8)
-/* coef index i = {0, 1, 2, 3, 4} */
-#define DISPC_VID_CONV_COEF(n, i) DISPC_REG(0x0130 + (n)*0x90 + (i)*0x4)
-/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
-#define DISPC_VID_FIR_COEF_V(n, i) DISPC_REG(0x01E0 + (n)*0x20 + (i)*0x4)
-
-#define DISPC_VID_PRELOAD(n) DISPC_REG(0x230 + (n)*0x04)
-
-#define DISPC_DIVISOR DISPC_REG(0x0804)
-
#define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
DISPC_IRQ_OCP_ERR | \
DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
@@ -167,10 +83,6 @@
#define REG_FLD_MOD(idx, val, start, end) \
dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
-static const struct dispc_reg dispc_reg_att[] = { DISPC_GFX_ATTRIBUTES,
- DISPC_VID_ATTRIBUTES(0),
- DISPC_VID_ATTRIBUTES(1) };
-
struct dispc_irq_stats {
unsigned long last_reset;
unsigned irq_count;
@@ -198,25 +110,38 @@
#endif
} dispc;
+enum omap_color_component {
+ /* used for all color formats for OMAP3 and earlier
+ * and for RGB and Y color component on OMAP4
+ */
+ DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
+ /* used for UV component for
+ * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
+ * color formats on OMAP4
+ */
+ DISPC_COLOR_COMPONENT_UV = 1 << 1,
+};
+
static void _omap_dispc_set_irqs(void);
-static inline void dispc_write_reg(const struct dispc_reg idx, u32 val)
+static inline void dispc_write_reg(const u16 idx, u32 val)
{
- __raw_writel(val, dispc.base + idx.idx);
+ __raw_writel(val, dispc.base + idx);
}
-static inline u32 dispc_read_reg(const struct dispc_reg idx)
+static inline u32 dispc_read_reg(const u16 idx)
{
- return __raw_readl(dispc.base + idx.idx);
+ return __raw_readl(dispc.base + idx);
}
#define SR(reg) \
- dispc.ctx[(DISPC_##reg).idx / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
+ dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
#define RR(reg) \
- dispc_write_reg(DISPC_##reg, dispc.ctx[(DISPC_##reg).idx / sizeof(u32)])
+ dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
void dispc_save_context(void)
{
+ int i;
if (cpu_is_omap24xx())
return;
@@ -224,157 +149,153 @@
SR(IRQENABLE);
SR(CONTROL);
SR(CONFIG);
- SR(DEFAULT_COLOR(0));
- SR(DEFAULT_COLOR(1));
- SR(TRANS_COLOR(0));
- SR(TRANS_COLOR(1));
+ SR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD));
+ SR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_DIGIT));
+ SR(TRANS_COLOR(OMAP_DSS_CHANNEL_LCD));
+ SR(TRANS_COLOR(OMAP_DSS_CHANNEL_DIGIT));
SR(LINE_NUMBER);
- SR(TIMING_H(0));
- SR(TIMING_V(0));
- SR(POL_FREQ(0));
- SR(DIVISORo(0));
+ SR(TIMING_H(OMAP_DSS_CHANNEL_LCD));
+ SR(TIMING_V(OMAP_DSS_CHANNEL_LCD));
+ SR(POL_FREQ(OMAP_DSS_CHANNEL_LCD));
+ SR(DIVISORo(OMAP_DSS_CHANNEL_LCD));
SR(GLOBAL_ALPHA);
- SR(SIZE_DIG);
- SR(SIZE_LCD(0));
+ SR(SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT));
+ SR(SIZE_MGR(OMAP_DSS_CHANNEL_LCD));
if (dss_has_feature(FEAT_MGR_LCD2)) {
SR(CONTROL2);
- SR(DEFAULT_COLOR(2));
- SR(TRANS_COLOR(2));
- SR(SIZE_LCD(2));
- SR(TIMING_H(2));
- SR(TIMING_V(2));
- SR(POL_FREQ(2));
- SR(DIVISORo(2));
+ SR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD2));
+ SR(TRANS_COLOR(OMAP_DSS_CHANNEL_LCD2));
+ SR(SIZE_MGR(OMAP_DSS_CHANNEL_LCD2));
+ SR(TIMING_H(OMAP_DSS_CHANNEL_LCD2));
+ SR(TIMING_V(OMAP_DSS_CHANNEL_LCD2));
+ SR(POL_FREQ(OMAP_DSS_CHANNEL_LCD2));
+ SR(DIVISORo(OMAP_DSS_CHANNEL_LCD2));
SR(CONFIG2);
}
- SR(GFX_BA0);
- SR(GFX_BA1);
- SR(GFX_POSITION);
- SR(GFX_SIZE);
- SR(GFX_ATTRIBUTES);
- SR(GFX_FIFO_THRESHOLD);
- SR(GFX_ROW_INC);
- SR(GFX_PIXEL_INC);
- SR(GFX_WINDOW_SKIP);
- SR(GFX_TABLE_BA);
+ SR(OVL_BA0(OMAP_DSS_GFX));
+ SR(OVL_BA1(OMAP_DSS_GFX));
+ SR(OVL_POSITION(OMAP_DSS_GFX));
+ SR(OVL_SIZE(OMAP_DSS_GFX));
+ SR(OVL_ATTRIBUTES(OMAP_DSS_GFX));
+ SR(OVL_FIFO_THRESHOLD(OMAP_DSS_GFX));
+ SR(OVL_ROW_INC(OMAP_DSS_GFX));
+ SR(OVL_PIXEL_INC(OMAP_DSS_GFX));
+ SR(OVL_WINDOW_SKIP(OMAP_DSS_GFX));
+ SR(OVL_TABLE_BA(OMAP_DSS_GFX));
- SR(DATA_CYCLE1(0));
- SR(DATA_CYCLE2(0));
- SR(DATA_CYCLE3(0));
+ SR(DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD));
+ SR(DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD));
+ SR(DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD));
- SR(CPR_COEF_R(0));
- SR(CPR_COEF_G(0));
- SR(CPR_COEF_B(0));
+ SR(CPR_COEF_R(OMAP_DSS_CHANNEL_LCD));
+ SR(CPR_COEF_G(OMAP_DSS_CHANNEL_LCD));
+ SR(CPR_COEF_B(OMAP_DSS_CHANNEL_LCD));
if (dss_has_feature(FEAT_MGR_LCD2)) {
- SR(CPR_COEF_B(2));
- SR(CPR_COEF_G(2));
- SR(CPR_COEF_R(2));
+ SR(CPR_COEF_B(OMAP_DSS_CHANNEL_LCD2));
+ SR(CPR_COEF_G(OMAP_DSS_CHANNEL_LCD2));
+ SR(CPR_COEF_R(OMAP_DSS_CHANNEL_LCD2));
- SR(DATA_CYCLE1(2));
- SR(DATA_CYCLE2(2));
- SR(DATA_CYCLE3(2));
+ SR(DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD2));
+ SR(DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD2));
+ SR(DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD2));
}
- SR(GFX_PRELOAD);
+ SR(OVL_PRELOAD(OMAP_DSS_GFX));
/* VID1 */
- SR(VID_BA0(0));
- SR(VID_BA1(0));
- SR(VID_POSITION(0));
- SR(VID_SIZE(0));
- SR(VID_ATTRIBUTES(0));
- SR(VID_FIFO_THRESHOLD(0));
- SR(VID_ROW_INC(0));
- SR(VID_PIXEL_INC(0));
- SR(VID_FIR(0));
- SR(VID_PICTURE_SIZE(0));
- SR(VID_ACCU0(0));
- SR(VID_ACCU1(0));
+ SR(OVL_BA0(OMAP_DSS_VIDEO1));
+ SR(OVL_BA1(OMAP_DSS_VIDEO1));
+ SR(OVL_POSITION(OMAP_DSS_VIDEO1));
+ SR(OVL_SIZE(OMAP_DSS_VIDEO1));
+ SR(OVL_ATTRIBUTES(OMAP_DSS_VIDEO1));
+ SR(OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO1));
+ SR(OVL_ROW_INC(OMAP_DSS_VIDEO1));
+ SR(OVL_PIXEL_INC(OMAP_DSS_VIDEO1));
+ SR(OVL_FIR(OMAP_DSS_VIDEO1));
+ SR(OVL_PICTURE_SIZE(OMAP_DSS_VIDEO1));
+ SR(OVL_ACCU0(OMAP_DSS_VIDEO1));
+ SR(OVL_ACCU1(OMAP_DSS_VIDEO1));
- SR(VID_FIR_COEF_H(0, 0));
- SR(VID_FIR_COEF_H(0, 1));
- SR(VID_FIR_COEF_H(0, 2));
- SR(VID_FIR_COEF_H(0, 3));
- SR(VID_FIR_COEF_H(0, 4));
- SR(VID_FIR_COEF_H(0, 5));
- SR(VID_FIR_COEF_H(0, 6));
- SR(VID_FIR_COEF_H(0, 7));
+ for (i = 0; i < 8; i++)
+ SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, i));
- SR(VID_FIR_COEF_HV(0, 0));
- SR(VID_FIR_COEF_HV(0, 1));
- SR(VID_FIR_COEF_HV(0, 2));
- SR(VID_FIR_COEF_HV(0, 3));
- SR(VID_FIR_COEF_HV(0, 4));
- SR(VID_FIR_COEF_HV(0, 5));
- SR(VID_FIR_COEF_HV(0, 6));
- SR(VID_FIR_COEF_HV(0, 7));
+ for (i = 0; i < 8; i++)
+ SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, i));
- SR(VID_CONV_COEF(0, 0));
- SR(VID_CONV_COEF(0, 1));
- SR(VID_CONV_COEF(0, 2));
- SR(VID_CONV_COEF(0, 3));
- SR(VID_CONV_COEF(0, 4));
+ for (i = 0; i < 5; i++)
+ SR(OVL_CONV_COEF(OMAP_DSS_VIDEO1, i));
- SR(VID_FIR_COEF_V(0, 0));
- SR(VID_FIR_COEF_V(0, 1));
- SR(VID_FIR_COEF_V(0, 2));
- SR(VID_FIR_COEF_V(0, 3));
- SR(VID_FIR_COEF_V(0, 4));
- SR(VID_FIR_COEF_V(0, 5));
- SR(VID_FIR_COEF_V(0, 6));
- SR(VID_FIR_COEF_V(0, 7));
+ for (i = 0; i < 8; i++)
+ SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, i));
- SR(VID_PRELOAD(0));
+ if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
+ SR(OVL_BA0_UV(OMAP_DSS_VIDEO1));
+ SR(OVL_BA1_UV(OMAP_DSS_VIDEO1));
+ SR(OVL_FIR2(OMAP_DSS_VIDEO1));
+ SR(OVL_ACCU2_0(OMAP_DSS_VIDEO1));
+ SR(OVL_ACCU2_1(OMAP_DSS_VIDEO1));
+
+ for (i = 0; i < 8; i++)
+ SR(OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, i));
+
+ for (i = 0; i < 8; i++)
+ SR(OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, i));
+
+ for (i = 0; i < 8; i++)
+ SR(OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, i));
+ }
+ if (dss_has_feature(FEAT_ATTR2))
+ SR(OVL_ATTRIBUTES2(OMAP_DSS_VIDEO1));
+
+ SR(OVL_PRELOAD(OMAP_DSS_VIDEO1));
/* VID2 */
- SR(VID_BA0(1));
- SR(VID_BA1(1));
- SR(VID_POSITION(1));
- SR(VID_SIZE(1));
- SR(VID_ATTRIBUTES(1));
- SR(VID_FIFO_THRESHOLD(1));
- SR(VID_ROW_INC(1));
- SR(VID_PIXEL_INC(1));
- SR(VID_FIR(1));
- SR(VID_PICTURE_SIZE(1));
- SR(VID_ACCU0(1));
- SR(VID_ACCU1(1));
+ SR(OVL_BA0(OMAP_DSS_VIDEO2));
+ SR(OVL_BA1(OMAP_DSS_VIDEO2));
+ SR(OVL_POSITION(OMAP_DSS_VIDEO2));
+ SR(OVL_SIZE(OMAP_DSS_VIDEO2));
+ SR(OVL_ATTRIBUTES(OMAP_DSS_VIDEO2));
+ SR(OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO2));
+ SR(OVL_ROW_INC(OMAP_DSS_VIDEO2));
+ SR(OVL_PIXEL_INC(OMAP_DSS_VIDEO2));
+ SR(OVL_FIR(OMAP_DSS_VIDEO2));
+ SR(OVL_PICTURE_SIZE(OMAP_DSS_VIDEO2));
+ SR(OVL_ACCU0(OMAP_DSS_VIDEO2));
+ SR(OVL_ACCU1(OMAP_DSS_VIDEO2));
- SR(VID_FIR_COEF_H(1, 0));
- SR(VID_FIR_COEF_H(1, 1));
- SR(VID_FIR_COEF_H(1, 2));
- SR(VID_FIR_COEF_H(1, 3));
- SR(VID_FIR_COEF_H(1, 4));
- SR(VID_FIR_COEF_H(1, 5));
- SR(VID_FIR_COEF_H(1, 6));
- SR(VID_FIR_COEF_H(1, 7));
+ for (i = 0; i < 8; i++)
+ SR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, i));
- SR(VID_FIR_COEF_HV(1, 0));
- SR(VID_FIR_COEF_HV(1, 1));
- SR(VID_FIR_COEF_HV(1, 2));
- SR(VID_FIR_COEF_HV(1, 3));
- SR(VID_FIR_COEF_HV(1, 4));
- SR(VID_FIR_COEF_HV(1, 5));
- SR(VID_FIR_COEF_HV(1, 6));
- SR(VID_FIR_COEF_HV(1, 7));
+ for (i = 0; i < 8; i++)
+ SR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, i));
- SR(VID_CONV_COEF(1, 0));
- SR(VID_CONV_COEF(1, 1));
- SR(VID_CONV_COEF(1, 2));
- SR(VID_CONV_COEF(1, 3));
- SR(VID_CONV_COEF(1, 4));
+ for (i = 0; i < 5; i++)
+ SR(OVL_CONV_COEF(OMAP_DSS_VIDEO2, i));
- SR(VID_FIR_COEF_V(1, 0));
- SR(VID_FIR_COEF_V(1, 1));
- SR(VID_FIR_COEF_V(1, 2));
- SR(VID_FIR_COEF_V(1, 3));
- SR(VID_FIR_COEF_V(1, 4));
- SR(VID_FIR_COEF_V(1, 5));
- SR(VID_FIR_COEF_V(1, 6));
- SR(VID_FIR_COEF_V(1, 7));
+ for (i = 0; i < 8; i++)
+ SR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, i));
- SR(VID_PRELOAD(1));
+ if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
+ SR(OVL_BA0_UV(OMAP_DSS_VIDEO2));
+ SR(OVL_BA1_UV(OMAP_DSS_VIDEO2));
+ SR(OVL_FIR2(OMAP_DSS_VIDEO2));
+ SR(OVL_ACCU2_0(OMAP_DSS_VIDEO2));
+ SR(OVL_ACCU2_1(OMAP_DSS_VIDEO2));
+
+ for (i = 0; i < 8; i++)
+ SR(OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, i));
+
+ for (i = 0; i < 8; i++)
+ SR(OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, i));
+
+ for (i = 0; i < 8; i++)
+ SR(OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, i));
+ }
+ if (dss_has_feature(FEAT_ATTR2))
+ SR(OVL_ATTRIBUTES2(OMAP_DSS_VIDEO2));
+
+ SR(OVL_PRELOAD(OMAP_DSS_VIDEO2));
if (dss_has_feature(FEAT_CORE_CLK_DIV))
SR(DIVISOR);
@@ -382,160 +303,158 @@
void dispc_restore_context(void)
{
+ int i;
RR(SYSCONFIG);
/*RR(IRQENABLE);*/
/*RR(CONTROL);*/
RR(CONFIG);
- RR(DEFAULT_COLOR(0));
- RR(DEFAULT_COLOR(1));
- RR(TRANS_COLOR(0));
- RR(TRANS_COLOR(1));
+ RR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD));
+ RR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_DIGIT));
+ RR(TRANS_COLOR(OMAP_DSS_CHANNEL_LCD));
+ RR(TRANS_COLOR(OMAP_DSS_CHANNEL_DIGIT));
RR(LINE_NUMBER);
- RR(TIMING_H(0));
- RR(TIMING_V(0));
- RR(POL_FREQ(0));
- RR(DIVISORo(0));
+ RR(TIMING_H(OMAP_DSS_CHANNEL_LCD));
+ RR(TIMING_V(OMAP_DSS_CHANNEL_LCD));
+ RR(POL_FREQ(OMAP_DSS_CHANNEL_LCD));
+ RR(DIVISORo(OMAP_DSS_CHANNEL_LCD));
RR(GLOBAL_ALPHA);
- RR(SIZE_DIG);
- RR(SIZE_LCD(0));
+ RR(SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT));
+ RR(SIZE_MGR(OMAP_DSS_CHANNEL_LCD));
if (dss_has_feature(FEAT_MGR_LCD2)) {
- RR(DEFAULT_COLOR(2));
- RR(TRANS_COLOR(2));
- RR(SIZE_LCD(2));
- RR(TIMING_H(2));
- RR(TIMING_V(2));
- RR(POL_FREQ(2));
- RR(DIVISORo(2));
+ RR(DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD2));
+ RR(TRANS_COLOR(OMAP_DSS_CHANNEL_LCD2));
+ RR(SIZE_MGR(OMAP_DSS_CHANNEL_LCD2));
+ RR(TIMING_H(OMAP_DSS_CHANNEL_LCD2));
+ RR(TIMING_V(OMAP_DSS_CHANNEL_LCD2));
+ RR(POL_FREQ(OMAP_DSS_CHANNEL_LCD2));
+ RR(DIVISORo(OMAP_DSS_CHANNEL_LCD2));
RR(CONFIG2);
}
- RR(GFX_BA0);
- RR(GFX_BA1);
- RR(GFX_POSITION);
- RR(GFX_SIZE);
- RR(GFX_ATTRIBUTES);
- RR(GFX_FIFO_THRESHOLD);
- RR(GFX_ROW_INC);
- RR(GFX_PIXEL_INC);
- RR(GFX_WINDOW_SKIP);
- RR(GFX_TABLE_BA);
+ RR(OVL_BA0(OMAP_DSS_GFX));
+ RR(OVL_BA1(OMAP_DSS_GFX));
+ RR(OVL_POSITION(OMAP_DSS_GFX));
+ RR(OVL_SIZE(OMAP_DSS_GFX));
+ RR(OVL_ATTRIBUTES(OMAP_DSS_GFX));
+ RR(OVL_FIFO_THRESHOLD(OMAP_DSS_GFX));
+ RR(OVL_ROW_INC(OMAP_DSS_GFX));
+ RR(OVL_PIXEL_INC(OMAP_DSS_GFX));
+ RR(OVL_WINDOW_SKIP(OMAP_DSS_GFX));
+ RR(OVL_TABLE_BA(OMAP_DSS_GFX));
- RR(DATA_CYCLE1(0));
- RR(DATA_CYCLE2(0));
- RR(DATA_CYCLE3(0));
- RR(CPR_COEF_R(0));
- RR(CPR_COEF_G(0));
- RR(CPR_COEF_B(0));
+ RR(DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD));
+ RR(DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD));
+ RR(DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD));
+
+ RR(CPR_COEF_R(OMAP_DSS_CHANNEL_LCD));
+ RR(CPR_COEF_G(OMAP_DSS_CHANNEL_LCD));
+ RR(CPR_COEF_B(OMAP_DSS_CHANNEL_LCD));
if (dss_has_feature(FEAT_MGR_LCD2)) {
- RR(DATA_CYCLE1(2));
- RR(DATA_CYCLE2(2));
- RR(DATA_CYCLE3(2));
+ RR(DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD2));
+ RR(DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD2));
+ RR(DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD2));
- RR(CPR_COEF_B(2));
- RR(CPR_COEF_G(2));
- RR(CPR_COEF_R(2));
+ RR(CPR_COEF_B(OMAP_DSS_CHANNEL_LCD2));
+ RR(CPR_COEF_G(OMAP_DSS_CHANNEL_LCD2));
+ RR(CPR_COEF_R(OMAP_DSS_CHANNEL_LCD2));
}
- RR(GFX_PRELOAD);
+ RR(OVL_PRELOAD(OMAP_DSS_GFX));
/* VID1 */
- RR(VID_BA0(0));
- RR(VID_BA1(0));
- RR(VID_POSITION(0));
- RR(VID_SIZE(0));
- RR(VID_ATTRIBUTES(0));
- RR(VID_FIFO_THRESHOLD(0));
- RR(VID_ROW_INC(0));
- RR(VID_PIXEL_INC(0));
- RR(VID_FIR(0));
- RR(VID_PICTURE_SIZE(0));
- RR(VID_ACCU0(0));
- RR(VID_ACCU1(0));
+ RR(OVL_BA0(OMAP_DSS_VIDEO1));
+ RR(OVL_BA1(OMAP_DSS_VIDEO1));
+ RR(OVL_POSITION(OMAP_DSS_VIDEO1));
+ RR(OVL_SIZE(OMAP_DSS_VIDEO1));
+ RR(OVL_ATTRIBUTES(OMAP_DSS_VIDEO1));
+ RR(OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO1));
+ RR(OVL_ROW_INC(OMAP_DSS_VIDEO1));
+ RR(OVL_PIXEL_INC(OMAP_DSS_VIDEO1));
+ RR(OVL_FIR(OMAP_DSS_VIDEO1));
+ RR(OVL_PICTURE_SIZE(OMAP_DSS_VIDEO1));
+ RR(OVL_ACCU0(OMAP_DSS_VIDEO1));
+ RR(OVL_ACCU1(OMAP_DSS_VIDEO1));
- RR(VID_FIR_COEF_H(0, 0));
- RR(VID_FIR_COEF_H(0, 1));
- RR(VID_FIR_COEF_H(0, 2));
- RR(VID_FIR_COEF_H(0, 3));
- RR(VID_FIR_COEF_H(0, 4));
- RR(VID_FIR_COEF_H(0, 5));
- RR(VID_FIR_COEF_H(0, 6));
- RR(VID_FIR_COEF_H(0, 7));
+ for (i = 0; i < 8; i++)
+ RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, i));
- RR(VID_FIR_COEF_HV(0, 0));
- RR(VID_FIR_COEF_HV(0, 1));
- RR(VID_FIR_COEF_HV(0, 2));
- RR(VID_FIR_COEF_HV(0, 3));
- RR(VID_FIR_COEF_HV(0, 4));
- RR(VID_FIR_COEF_HV(0, 5));
- RR(VID_FIR_COEF_HV(0, 6));
- RR(VID_FIR_COEF_HV(0, 7));
+ for (i = 0; i < 8; i++)
+ RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, i));
- RR(VID_CONV_COEF(0, 0));
- RR(VID_CONV_COEF(0, 1));
- RR(VID_CONV_COEF(0, 2));
- RR(VID_CONV_COEF(0, 3));
- RR(VID_CONV_COEF(0, 4));
+ for (i = 0; i < 5; i++)
+ RR(OVL_CONV_COEF(OMAP_DSS_VIDEO1, i));
- RR(VID_FIR_COEF_V(0, 0));
- RR(VID_FIR_COEF_V(0, 1));
- RR(VID_FIR_COEF_V(0, 2));
- RR(VID_FIR_COEF_V(0, 3));
- RR(VID_FIR_COEF_V(0, 4));
- RR(VID_FIR_COEF_V(0, 5));
- RR(VID_FIR_COEF_V(0, 6));
- RR(VID_FIR_COEF_V(0, 7));
+ for (i = 0; i < 8; i++)
+ RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, i));
- RR(VID_PRELOAD(0));
+ if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
+ RR(OVL_BA0_UV(OMAP_DSS_VIDEO1));
+ RR(OVL_BA1_UV(OMAP_DSS_VIDEO1));
+ RR(OVL_FIR2(OMAP_DSS_VIDEO1));
+ RR(OVL_ACCU2_0(OMAP_DSS_VIDEO1));
+ RR(OVL_ACCU2_1(OMAP_DSS_VIDEO1));
+
+ for (i = 0; i < 8; i++)
+ RR(OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, i));
+
+ for (i = 0; i < 8; i++)
+ RR(OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, i));
+
+ for (i = 0; i < 8; i++)
+ RR(OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, i));
+ }
+ if (dss_has_feature(FEAT_ATTR2))
+ RR(OVL_ATTRIBUTES2(OMAP_DSS_VIDEO1));
+
+ RR(OVL_PRELOAD(OMAP_DSS_VIDEO1));
/* VID2 */
- RR(VID_BA0(1));
- RR(VID_BA1(1));
- RR(VID_POSITION(1));
- RR(VID_SIZE(1));
- RR(VID_ATTRIBUTES(1));
- RR(VID_FIFO_THRESHOLD(1));
- RR(VID_ROW_INC(1));
- RR(VID_PIXEL_INC(1));
- RR(VID_FIR(1));
- RR(VID_PICTURE_SIZE(1));
- RR(VID_ACCU0(1));
- RR(VID_ACCU1(1));
+ RR(OVL_BA0(OMAP_DSS_VIDEO2));
+ RR(OVL_BA1(OMAP_DSS_VIDEO2));
+ RR(OVL_POSITION(OMAP_DSS_VIDEO2));
+ RR(OVL_SIZE(OMAP_DSS_VIDEO2));
+ RR(OVL_ATTRIBUTES(OMAP_DSS_VIDEO2));
+ RR(OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO2));
+ RR(OVL_ROW_INC(OMAP_DSS_VIDEO2));
+ RR(OVL_PIXEL_INC(OMAP_DSS_VIDEO2));
+ RR(OVL_FIR(OMAP_DSS_VIDEO2));
+ RR(OVL_PICTURE_SIZE(OMAP_DSS_VIDEO2));
+ RR(OVL_ACCU0(OMAP_DSS_VIDEO2));
+ RR(OVL_ACCU1(OMAP_DSS_VIDEO2));
- RR(VID_FIR_COEF_H(1, 0));
- RR(VID_FIR_COEF_H(1, 1));
- RR(VID_FIR_COEF_H(1, 2));
- RR(VID_FIR_COEF_H(1, 3));
- RR(VID_FIR_COEF_H(1, 4));
- RR(VID_FIR_COEF_H(1, 5));
- RR(VID_FIR_COEF_H(1, 6));
- RR(VID_FIR_COEF_H(1, 7));
+ for (i = 0; i < 8; i++)
+ RR(OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, i));
- RR(VID_FIR_COEF_HV(1, 0));
- RR(VID_FIR_COEF_HV(1, 1));
- RR(VID_FIR_COEF_HV(1, 2));
- RR(VID_FIR_COEF_HV(1, 3));
- RR(VID_FIR_COEF_HV(1, 4));
- RR(VID_FIR_COEF_HV(1, 5));
- RR(VID_FIR_COEF_HV(1, 6));
- RR(VID_FIR_COEF_HV(1, 7));
+ for (i = 0; i < 8; i++)
+ RR(OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, i));
- RR(VID_CONV_COEF(1, 0));
- RR(VID_CONV_COEF(1, 1));
- RR(VID_CONV_COEF(1, 2));
- RR(VID_CONV_COEF(1, 3));
- RR(VID_CONV_COEF(1, 4));
+ for (i = 0; i < 5; i++)
+ RR(OVL_CONV_COEF(OMAP_DSS_VIDEO2, i));
- RR(VID_FIR_COEF_V(1, 0));
- RR(VID_FIR_COEF_V(1, 1));
- RR(VID_FIR_COEF_V(1, 2));
- RR(VID_FIR_COEF_V(1, 3));
- RR(VID_FIR_COEF_V(1, 4));
- RR(VID_FIR_COEF_V(1, 5));
- RR(VID_FIR_COEF_V(1, 6));
- RR(VID_FIR_COEF_V(1, 7));
+ for (i = 0; i < 8; i++)
+ RR(OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, i));
- RR(VID_PRELOAD(1));
+ if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
+ RR(OVL_BA0_UV(OMAP_DSS_VIDEO2));
+ RR(OVL_BA1_UV(OMAP_DSS_VIDEO2));
+ RR(OVL_FIR2(OMAP_DSS_VIDEO2));
+ RR(OVL_ACCU2_0(OMAP_DSS_VIDEO2));
+ RR(OVL_ACCU2_1(OMAP_DSS_VIDEO2));
+
+ for (i = 0; i < 8; i++)
+ RR(OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, i));
+
+ for (i = 0; i < 8; i++)
+ RR(OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, i));
+
+ for (i = 0; i < 8; i++)
+ RR(OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, i));
+ }
+ if (dss_has_feature(FEAT_ATTR2))
+ RR(OVL_ATTRIBUTES2(OMAP_DSS_VIDEO2));
+
+ RR(OVL_PRELOAD(OMAP_DSS_VIDEO2));
if (dss_has_feature(FEAT_CORE_CLK_DIV))
RR(DIVISOR);
@@ -632,27 +551,43 @@
static void _dispc_write_firh_reg(enum omap_plane plane, int reg, u32 value)
{
- BUG_ON(plane == OMAP_DSS_GFX);
-
- dispc_write_reg(DISPC_VID_FIR_COEF_H(plane-1, reg), value);
+ dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
}
static void _dispc_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
{
- BUG_ON(plane == OMAP_DSS_GFX);
-
- dispc_write_reg(DISPC_VID_FIR_COEF_HV(plane-1, reg), value);
+ dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
}
static void _dispc_write_firv_reg(enum omap_plane plane, int reg, u32 value)
{
+ dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
+}
+
+static void _dispc_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
+{
BUG_ON(plane == OMAP_DSS_GFX);
- dispc_write_reg(DISPC_VID_FIR_COEF_V(plane-1, reg), value);
+ dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
+}
+
+static void _dispc_write_firhv2_reg(enum omap_plane plane, int reg, u32 value)
+{
+ BUG_ON(plane == OMAP_DSS_GFX);
+
+ dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
+}
+
+static void _dispc_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
+{
+ BUG_ON(plane == OMAP_DSS_GFX);
+
+ dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
}
static void _dispc_set_scale_coef(enum omap_plane plane, int hscaleup,
- int vscaleup, int five_taps)
+ int vscaleup, int five_taps,
+ enum omap_color_component color_comp)
{
/* Coefficients for horizontal up-sampling */
static const struct dispc_h_coef coef_hup[8] = {
@@ -750,8 +685,14 @@
| FLD_VAL(v_coef[i].vc1, 23, 16)
| FLD_VAL(v_coef[i].vc2, 31, 24);
- _dispc_write_firh_reg(plane, i, h);
- _dispc_write_firhv_reg(plane, i, hv);
+ if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
+ _dispc_write_firh_reg(plane, i, h);
+ _dispc_write_firhv_reg(plane, i, hv);
+ } else {
+ _dispc_write_firh2_reg(plane, i, h);
+ _dispc_write_firhv2_reg(plane, i, hv);
+ }
+
}
if (five_taps) {
@@ -759,7 +700,10 @@
u32 v;
v = FLD_VAL(v_coef[i].vc00, 7, 0)
| FLD_VAL(v_coef[i].vc22, 15, 8);
- _dispc_write_firv_reg(plane, i, v);
+ if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
+ _dispc_write_firv_reg(plane, i, v);
+ else
+ _dispc_write_firv2_reg(plane, i, v);
}
}
}
@@ -779,72 +723,83 @@
ct = &ctbl_bt601_5;
- dispc_write_reg(DISPC_VID_CONV_COEF(0, 0), CVAL(ct->rcr, ct->ry));
- dispc_write_reg(DISPC_VID_CONV_COEF(0, 1), CVAL(ct->gy, ct->rcb));
- dispc_write_reg(DISPC_VID_CONV_COEF(0, 2), CVAL(ct->gcb, ct->gcr));
- dispc_write_reg(DISPC_VID_CONV_COEF(0, 3), CVAL(ct->bcr, ct->by));
- dispc_write_reg(DISPC_VID_CONV_COEF(0, 4), CVAL(0, ct->bcb));
+ dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 0),
+ CVAL(ct->rcr, ct->ry));
+ dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 1),
+ CVAL(ct->gy, ct->rcb));
+ dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 2),
+ CVAL(ct->gcb, ct->gcr));
+ dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 3),
+ CVAL(ct->bcr, ct->by));
+ dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 4),
+ CVAL(0, ct->bcb));
- dispc_write_reg(DISPC_VID_CONV_COEF(1, 0), CVAL(ct->rcr, ct->ry));
- dispc_write_reg(DISPC_VID_CONV_COEF(1, 1), CVAL(ct->gy, ct->rcb));
- dispc_write_reg(DISPC_VID_CONV_COEF(1, 2), CVAL(ct->gcb, ct->gcr));
- dispc_write_reg(DISPC_VID_CONV_COEF(1, 3), CVAL(ct->bcr, ct->by));
- dispc_write_reg(DISPC_VID_CONV_COEF(1, 4), CVAL(0, ct->bcb));
+ dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 0),
+ CVAL(ct->rcr, ct->ry));
+ dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 1),
+ CVAL(ct->gy, ct->rcb));
+ dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 2),
+ CVAL(ct->gcb, ct->gcr));
+ dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 3),
+ CVAL(ct->bcr, ct->by));
+ dispc_write_reg(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 4),
+ CVAL(0, ct->bcb));
#undef CVAL
- REG_FLD_MOD(DISPC_VID_ATTRIBUTES(0), ct->full_range, 11, 11);
- REG_FLD_MOD(DISPC_VID_ATTRIBUTES(1), ct->full_range, 11, 11);
+ REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(OMAP_DSS_VIDEO1),
+ ct->full_range, 11, 11);
+ REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(OMAP_DSS_VIDEO2),
+ ct->full_range, 11, 11);
}
static void _dispc_set_plane_ba0(enum omap_plane plane, u32 paddr)
{
- const struct dispc_reg ba0_reg[] = { DISPC_GFX_BA0,
- DISPC_VID_BA0(0),
- DISPC_VID_BA0(1) };
-
- dispc_write_reg(ba0_reg[plane], paddr);
+ dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
}
static void _dispc_set_plane_ba1(enum omap_plane plane, u32 paddr)
{
- const struct dispc_reg ba1_reg[] = { DISPC_GFX_BA1,
- DISPC_VID_BA1(0),
- DISPC_VID_BA1(1) };
+ dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
+}
- dispc_write_reg(ba1_reg[plane], paddr);
+static void _dispc_set_plane_ba0_uv(enum omap_plane plane, u32 paddr)
+{
+ dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
+}
+
+static void _dispc_set_plane_ba1_uv(enum omap_plane plane, u32 paddr)
+{
+ dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
}
static void _dispc_set_plane_pos(enum omap_plane plane, int x, int y)
{
- const struct dispc_reg pos_reg[] = { DISPC_GFX_POSITION,
- DISPC_VID_POSITION(0),
- DISPC_VID_POSITION(1) };
-
u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
- dispc_write_reg(pos_reg[plane], val);
+
+ dispc_write_reg(DISPC_OVL_POSITION(plane), val);
}
static void _dispc_set_pic_size(enum omap_plane plane, int width, int height)
{
- const struct dispc_reg siz_reg[] = { DISPC_GFX_SIZE,
- DISPC_VID_PICTURE_SIZE(0),
- DISPC_VID_PICTURE_SIZE(1) };
u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
- dispc_write_reg(siz_reg[plane], val);
+
+ if (plane == OMAP_DSS_GFX)
+ dispc_write_reg(DISPC_OVL_SIZE(plane), val);
+ else
+ dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
}
static void _dispc_set_vid_size(enum omap_plane plane, int width, int height)
{
u32 val;
- const struct dispc_reg vsi_reg[] = { DISPC_VID_SIZE(0),
- DISPC_VID_SIZE(1) };
BUG_ON(plane == OMAP_DSS_GFX);
val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
- dispc_write_reg(vsi_reg[plane-1], val);
+
+ dispc_write_reg(DISPC_OVL_SIZE(plane), val);
}
static void _dispc_set_pre_mult_alpha(enum omap_plane plane, bool enable)
@@ -856,7 +811,7 @@
plane == OMAP_DSS_VIDEO1)
return;
- REG_FLD_MOD(dispc_reg_att[plane], enable ? 1 : 0, 28, 28);
+ REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
}
static void _dispc_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
@@ -876,61 +831,93 @@
static void _dispc_set_pix_inc(enum omap_plane plane, s32 inc)
{
- const struct dispc_reg ri_reg[] = { DISPC_GFX_PIXEL_INC,
- DISPC_VID_PIXEL_INC(0),
- DISPC_VID_PIXEL_INC(1) };
-
- dispc_write_reg(ri_reg[plane], inc);
+ dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
}
static void _dispc_set_row_inc(enum omap_plane plane, s32 inc)
{
- const struct dispc_reg ri_reg[] = { DISPC_GFX_ROW_INC,
- DISPC_VID_ROW_INC(0),
- DISPC_VID_ROW_INC(1) };
-
- dispc_write_reg(ri_reg[plane], inc);
+ dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
}
static void _dispc_set_color_mode(enum omap_plane plane,
enum omap_color_mode color_mode)
{
u32 m = 0;
-
- switch (color_mode) {
- case OMAP_DSS_COLOR_CLUT1:
- m = 0x0; break;
- case OMAP_DSS_COLOR_CLUT2:
- m = 0x1; break;
- case OMAP_DSS_COLOR_CLUT4:
- m = 0x2; break;
- case OMAP_DSS_COLOR_CLUT8:
- m = 0x3; break;
- case OMAP_DSS_COLOR_RGB12U:
- m = 0x4; break;
- case OMAP_DSS_COLOR_ARGB16:
- m = 0x5; break;
- case OMAP_DSS_COLOR_RGB16:
- m = 0x6; break;
- case OMAP_DSS_COLOR_RGB24U:
- m = 0x8; break;
- case OMAP_DSS_COLOR_RGB24P:
- m = 0x9; break;
- case OMAP_DSS_COLOR_YUV2:
- m = 0xa; break;
- case OMAP_DSS_COLOR_UYVY:
- m = 0xb; break;
- case OMAP_DSS_COLOR_ARGB32:
- m = 0xc; break;
- case OMAP_DSS_COLOR_RGBA32:
- m = 0xd; break;
- case OMAP_DSS_COLOR_RGBX32:
- m = 0xe; break;
- default:
- BUG(); break;
+ if (plane != OMAP_DSS_GFX) {
+ switch (color_mode) {
+ case OMAP_DSS_COLOR_NV12:
+ m = 0x0; break;
+ case OMAP_DSS_COLOR_RGB12U:
+ m = 0x1; break;
+ case OMAP_DSS_COLOR_RGBA16:
+ m = 0x2; break;
+ case OMAP_DSS_COLOR_RGBX16:
+ m = 0x4; break;
+ case OMAP_DSS_COLOR_ARGB16:
+ m = 0x5; break;
+ case OMAP_DSS_COLOR_RGB16:
+ m = 0x6; break;
+ case OMAP_DSS_COLOR_ARGB16_1555:
+ m = 0x7; break;
+ case OMAP_DSS_COLOR_RGB24U:
+ m = 0x8; break;
+ case OMAP_DSS_COLOR_RGB24P:
+ m = 0x9; break;
+ case OMAP_DSS_COLOR_YUV2:
+ m = 0xa; break;
+ case OMAP_DSS_COLOR_UYVY:
+ m = 0xb; break;
+ case OMAP_DSS_COLOR_ARGB32:
+ m = 0xc; break;
+ case OMAP_DSS_COLOR_RGBA32:
+ m = 0xd; break;
+ case OMAP_DSS_COLOR_RGBX32:
+ m = 0xe; break;
+ case OMAP_DSS_COLOR_XRGB16_1555:
+ m = 0xf; break;
+ default:
+ BUG(); break;
+ }
+ } else {
+ switch (color_mode) {
+ case OMAP_DSS_COLOR_CLUT1:
+ m = 0x0; break;
+ case OMAP_DSS_COLOR_CLUT2:
+ m = 0x1; break;
+ case OMAP_DSS_COLOR_CLUT4:
+ m = 0x2; break;
+ case OMAP_DSS_COLOR_CLUT8:
+ m = 0x3; break;
+ case OMAP_DSS_COLOR_RGB12U:
+ m = 0x4; break;
+ case OMAP_DSS_COLOR_ARGB16:
+ m = 0x5; break;
+ case OMAP_DSS_COLOR_RGB16:
+ m = 0x6; break;
+ case OMAP_DSS_COLOR_ARGB16_1555:
+ m = 0x7; break;
+ case OMAP_DSS_COLOR_RGB24U:
+ m = 0x8; break;
+ case OMAP_DSS_COLOR_RGB24P:
+ m = 0x9; break;
+ case OMAP_DSS_COLOR_YUV2:
+ m = 0xa; break;
+ case OMAP_DSS_COLOR_UYVY:
+ m = 0xb; break;
+ case OMAP_DSS_COLOR_ARGB32:
+ m = 0xc; break;
+ case OMAP_DSS_COLOR_RGBA32:
+ m = 0xd; break;
+ case OMAP_DSS_COLOR_RGBX32:
+ m = 0xe; break;
+ case OMAP_DSS_COLOR_XRGB16_1555:
+ m = 0xf; break;
+ default:
+ BUG(); break;
+ }
}
- REG_FLD_MOD(dispc_reg_att[plane], m, 4, 1);
+ REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
}
static void _dispc_set_channel_out(enum omap_plane plane,
@@ -953,7 +940,7 @@
return;
}
- val = dispc_read_reg(dispc_reg_att[plane]);
+ val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
if (dss_has_feature(FEAT_MGR_LCD2)) {
switch (channel) {
case OMAP_DSS_CHANNEL_LCD:
@@ -977,7 +964,7 @@
} else {
val = FLD_MOD(val, channel, shift, shift);
}
- dispc_write_reg(dispc_reg_att[plane], val);
+ dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
}
void dispc_set_burst_size(enum omap_plane plane,
@@ -1001,9 +988,9 @@
return;
}
- val = dispc_read_reg(dispc_reg_att[plane]);
+ val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
val = FLD_MOD(val, burst_size, shift+1, shift);
- dispc_write_reg(dispc_reg_att[plane], val);
+ dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
enable_clocks(0);
}
@@ -1028,9 +1015,9 @@
BUG_ON(plane == OMAP_DSS_GFX);
- val = dispc_read_reg(dispc_reg_att[plane]);
+ val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
val = FLD_MOD(val, enable, 9, 9);
- dispc_write_reg(dispc_reg_att[plane], val);
+ dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
}
void dispc_enable_replication(enum omap_plane plane, bool enable)
@@ -1043,7 +1030,7 @@
bit = 10;
enable_clocks(1);
- REG_FLD_MOD(dispc_reg_att[plane], enable, bit, bit);
+ REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit);
enable_clocks(0);
}
@@ -1053,7 +1040,7 @@
BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
enable_clocks(1);
- dispc_write_reg(DISPC_SIZE_LCD(channel), val);
+ dispc_write_reg(DISPC_SIZE_MGR(channel), val);
enable_clocks(0);
}
@@ -1063,15 +1050,12 @@
BUG_ON((width > (1 << 11)) || (height > (1 << 11)));
val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
enable_clocks(1);
- dispc_write_reg(DISPC_SIZE_DIG, val);
+ dispc_write_reg(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT), val);
enable_clocks(0);
}
static void dispc_read_plane_fifo_sizes(void)
{
- const struct dispc_reg fsz_reg[] = { DISPC_GFX_FIFO_SIZE_STATUS,
- DISPC_VID_FIFO_SIZE_STATUS(0),
- DISPC_VID_FIFO_SIZE_STATUS(1) };
u32 size;
int plane;
u8 start, end;
@@ -1081,7 +1065,8 @@
dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
for (plane = 0; plane < ARRAY_SIZE(dispc.fifo_size); ++plane) {
- size = FLD_GET(dispc_read_reg(fsz_reg[plane]), start, end);
+ size = FLD_GET(dispc_read_reg(DISPC_OVL_FIFO_SIZE_STATUS(plane)),
+ start, end);
dispc.fifo_size[plane] = size;
}
@@ -1095,23 +1080,22 @@
void dispc_setup_plane_fifo(enum omap_plane plane, u32 low, u32 high)
{
- const struct dispc_reg ftrs_reg[] = { DISPC_GFX_FIFO_THRESHOLD,
- DISPC_VID_FIFO_THRESHOLD(0),
- DISPC_VID_FIFO_THRESHOLD(1) };
u8 hi_start, hi_end, lo_start, lo_end;
+ dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
+ dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
+
enable_clocks(1);
DSSDBG("fifo(%d) low/high old %u/%u, new %u/%u\n",
plane,
- REG_GET(ftrs_reg[plane], 11, 0),
- REG_GET(ftrs_reg[plane], 27, 16),
+ REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
+ lo_start, lo_end),
+ REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
+ hi_start, hi_end),
low, high);
- dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
- dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
-
- dispc_write_reg(ftrs_reg[plane],
+ dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
FLD_VAL(high, hi_start, hi_end) |
FLD_VAL(low, lo_start, lo_end));
@@ -1128,106 +1112,120 @@
enable_clocks(0);
}
-static void _dispc_set_fir(enum omap_plane plane, int hinc, int vinc)
+static void _dispc_set_fir(enum omap_plane plane,
+ int hinc, int vinc,
+ enum omap_color_component color_comp)
{
u32 val;
- const struct dispc_reg fir_reg[] = { DISPC_VID_FIR(0),
- DISPC_VID_FIR(1) };
- u8 hinc_start, hinc_end, vinc_start, vinc_end;
- BUG_ON(plane == OMAP_DSS_GFX);
+ if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
+ u8 hinc_start, hinc_end, vinc_start, vinc_end;
- dss_feat_get_reg_field(FEAT_REG_FIRHINC, &hinc_start, &hinc_end);
- dss_feat_get_reg_field(FEAT_REG_FIRVINC, &vinc_start, &vinc_end);
+ dss_feat_get_reg_field(FEAT_REG_FIRHINC,
+ &hinc_start, &hinc_end);
+ dss_feat_get_reg_field(FEAT_REG_FIRVINC,
+ &vinc_start, &vinc_end);
+ val = FLD_VAL(vinc, vinc_start, vinc_end) |
+ FLD_VAL(hinc, hinc_start, hinc_end);
- val = FLD_VAL(vinc, vinc_start, vinc_end) |
- FLD_VAL(hinc, hinc_start, hinc_end);
-
- dispc_write_reg(fir_reg[plane-1], val);
+ dispc_write_reg(DISPC_OVL_FIR(plane), val);
+ } else {
+ val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
+ dispc_write_reg(DISPC_OVL_FIR2(plane), val);
+ }
}
static void _dispc_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
{
u32 val;
- const struct dispc_reg ac0_reg[] = { DISPC_VID_ACCU0(0),
- DISPC_VID_ACCU0(1) };
u8 hor_start, hor_end, vert_start, vert_end;
- BUG_ON(plane == OMAP_DSS_GFX);
-
dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
val = FLD_VAL(vaccu, vert_start, vert_end) |
FLD_VAL(haccu, hor_start, hor_end);
- dispc_write_reg(ac0_reg[plane-1], val);
+ dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
}
static void _dispc_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
{
u32 val;
- const struct dispc_reg ac1_reg[] = { DISPC_VID_ACCU1(0),
- DISPC_VID_ACCU1(1) };
u8 hor_start, hor_end, vert_start, vert_end;
- BUG_ON(plane == OMAP_DSS_GFX);
-
dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
val = FLD_VAL(vaccu, vert_start, vert_end) |
FLD_VAL(haccu, hor_start, hor_end);
- dispc_write_reg(ac1_reg[plane-1], val);
+ dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
}
+static void _dispc_set_vid_accu2_0(enum omap_plane plane, int haccu, int vaccu)
+{
+ u32 val;
-static void _dispc_set_scaling(enum omap_plane plane,
+ val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
+ dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
+}
+
+static void _dispc_set_vid_accu2_1(enum omap_plane plane, int haccu, int vaccu)
+{
+ u32 val;
+
+ val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
+ dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
+}
+
+static void _dispc_set_scale_param(enum omap_plane plane,
u16 orig_width, u16 orig_height,
u16 out_width, u16 out_height,
- bool ilace, bool five_taps,
- bool fieldmode)
+ bool five_taps, u8 rotation,
+ enum omap_color_component color_comp)
{
- int fir_hinc;
- int fir_vinc;
+ int fir_hinc, fir_vinc;
int hscaleup, vscaleup;
- int accu0 = 0;
- int accu1 = 0;
- u32 l;
-
- BUG_ON(plane == OMAP_DSS_GFX);
hscaleup = orig_width <= out_width;
vscaleup = orig_height <= out_height;
- _dispc_set_scale_coef(plane, hscaleup, vscaleup, five_taps);
+ _dispc_set_scale_coef(plane, hscaleup, vscaleup, five_taps, color_comp);
- if (!orig_width || orig_width == out_width)
- fir_hinc = 0;
- else
- fir_hinc = 1024 * orig_width / out_width;
+ fir_hinc = 1024 * orig_width / out_width;
+ fir_vinc = 1024 * orig_height / out_height;
- if (!orig_height || orig_height == out_height)
- fir_vinc = 0;
- else
- fir_vinc = 1024 * orig_height / out_height;
+ _dispc_set_fir(plane, fir_hinc, fir_vinc, color_comp);
+}
- _dispc_set_fir(plane, fir_hinc, fir_vinc);
+static void _dispc_set_scaling_common(enum omap_plane plane,
+ u16 orig_width, u16 orig_height,
+ u16 out_width, u16 out_height,
+ bool ilace, bool five_taps,
+ bool fieldmode, enum omap_color_mode color_mode,
+ u8 rotation)
+{
+ int accu0 = 0;
+ int accu1 = 0;
+ u32 l;
- l = dispc_read_reg(dispc_reg_att[plane]);
+ _dispc_set_scale_param(plane, orig_width, orig_height,
+ out_width, out_height, five_taps,
+ rotation, DISPC_COLOR_COMPONENT_RGB_Y);
+ l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
/* RESIZEENABLE and VERTICALTAPS */
l &= ~((0x3 << 5) | (0x1 << 21));
- l |= fir_hinc ? (1 << 5) : 0;
- l |= fir_vinc ? (1 << 6) : 0;
+ l |= (orig_width != out_width) ? (1 << 5) : 0;
+ l |= (orig_height != out_height) ? (1 << 6) : 0;
l |= five_taps ? (1 << 21) : 0;
/* VRESIZECONF and HRESIZECONF */
if (dss_has_feature(FEAT_RESIZECONF)) {
l &= ~(0x3 << 7);
- l |= hscaleup ? 0 : (1 << 7);
- l |= vscaleup ? 0 : (1 << 8);
+ l |= (orig_width <= out_width) ? 0 : (1 << 7);
+ l |= (orig_height <= out_height) ? 0 : (1 << 8);
}
/* LINEBUFFERSPLIT */
@@ -1236,7 +1234,7 @@
l |= five_taps ? (1 << 22) : 0;
}
- dispc_write_reg(dispc_reg_att[plane], l);
+ dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
/*
* field 0 = even field = bottom field
@@ -1244,7 +1242,7 @@
*/
if (ilace && !fieldmode) {
accu1 = 0;
- accu0 = (fir_vinc / 2) & 0x3ff;
+ accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
if (accu0 >= 1024/2) {
accu1 = 1024/2;
accu0 -= accu1;
@@ -1255,6 +1253,93 @@
_dispc_set_vid_accu1(plane, 0, accu1);
}
+static void _dispc_set_scaling_uv(enum omap_plane plane,
+ u16 orig_width, u16 orig_height,
+ u16 out_width, u16 out_height,
+ bool ilace, bool five_taps,
+ bool fieldmode, enum omap_color_mode color_mode,
+ u8 rotation)
+{
+ int scale_x = out_width != orig_width;
+ int scale_y = out_height != orig_height;
+
+ if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
+ return;
+ if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
+ color_mode != OMAP_DSS_COLOR_UYVY &&
+ color_mode != OMAP_DSS_COLOR_NV12)) {
+ /* reset chroma resampling for RGB formats */
+ REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
+ return;
+ }
+ switch (color_mode) {
+ case OMAP_DSS_COLOR_NV12:
+ /* UV is subsampled by 2 vertically*/
+ orig_height >>= 1;
+ /* UV is subsampled by 2 horz.*/
+ orig_width >>= 1;
+ break;
+ case OMAP_DSS_COLOR_YUV2:
+ case OMAP_DSS_COLOR_UYVY:
+ /*For YUV422 with 90/270 rotation,
+ *we don't upsample chroma
+ */
+ if (rotation == OMAP_DSS_ROT_0 ||
+ rotation == OMAP_DSS_ROT_180)
+ /* UV is subsampled by 2 hrz*/
+ orig_width >>= 1;
+ /* must use FIR for YUV422 if rotated */
+ if (rotation != OMAP_DSS_ROT_0)
+ scale_x = scale_y = true;
+ break;
+ default:
+ BUG();
+ }
+
+ if (out_width != orig_width)
+ scale_x = true;
+ if (out_height != orig_height)
+ scale_y = true;
+
+ _dispc_set_scale_param(plane, orig_width, orig_height,
+ out_width, out_height, five_taps,
+ rotation, DISPC_COLOR_COMPONENT_UV);
+
+ REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
+ (scale_x || scale_y) ? 1 : 0, 8, 8);
+ /* set H scaling */
+ REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
+ /* set V scaling */
+ REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
+
+ _dispc_set_vid_accu2_0(plane, 0x80, 0);
+ _dispc_set_vid_accu2_1(plane, 0x80, 0);
+}
+
+static void _dispc_set_scaling(enum omap_plane plane,
+ u16 orig_width, u16 orig_height,
+ u16 out_width, u16 out_height,
+ bool ilace, bool five_taps,
+ bool fieldmode, enum omap_color_mode color_mode,
+ u8 rotation)
+{
+ BUG_ON(plane == OMAP_DSS_GFX);
+
+ _dispc_set_scaling_common(plane,
+ orig_width, orig_height,
+ out_width, out_height,
+ ilace, five_taps,
+ fieldmode, color_mode,
+ rotation);
+
+ _dispc_set_scaling_uv(plane,
+ orig_width, orig_height,
+ out_width, out_height,
+ ilace, five_taps,
+ fieldmode, color_mode,
+ rotation);
+}
+
static void _dispc_set_rotation_attrs(enum omap_plane plane, u8 rotation,
bool mirroring, enum omap_color_mode color_mode)
{
@@ -1302,9 +1387,10 @@
row_repeat = false;
}
- REG_FLD_MOD(dispc_reg_att[plane], vidrot, 13, 12);
+ REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
if (dss_has_feature(FEAT_ROWREPEATENABLE))
- REG_FLD_MOD(dispc_reg_att[plane], row_repeat ? 1 : 0, 18, 18);
+ REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
+ row_repeat ? 1 : 0, 18, 18);
}
static int color_mode_to_bpp(enum omap_color_mode color_mode)
@@ -1317,12 +1403,17 @@
case OMAP_DSS_COLOR_CLUT4:
return 4;
case OMAP_DSS_COLOR_CLUT8:
+ case OMAP_DSS_COLOR_NV12:
return 8;
case OMAP_DSS_COLOR_RGB12U:
case OMAP_DSS_COLOR_RGB16:
case OMAP_DSS_COLOR_ARGB16:
case OMAP_DSS_COLOR_YUV2:
case OMAP_DSS_COLOR_UYVY:
+ case OMAP_DSS_COLOR_RGBA16:
+ case OMAP_DSS_COLOR_RGBX16:
+ case OMAP_DSS_COLOR_ARGB16_1555:
+ case OMAP_DSS_COLOR_XRGB16_1555:
return 16;
case OMAP_DSS_COLOR_RGB24P:
return 24;
@@ -1655,7 +1746,7 @@
enum omap_dss_rotation_type rotation_type,
u8 rotation, int mirror,
u8 global_alpha, u8 pre_mult_alpha,
- enum omap_channel channel)
+ enum omap_channel channel, u32 puv_addr)
{
const int maxdownscale = cpu_is_omap34xx() ? 4 : 2;
bool five_taps = 0;
@@ -1704,7 +1795,8 @@
return -EINVAL;
if (color_mode == OMAP_DSS_COLOR_YUV2 ||
- color_mode == OMAP_DSS_COLOR_UYVY)
+ color_mode == OMAP_DSS_COLOR_UYVY ||
+ color_mode == OMAP_DSS_COLOR_NV12)
cconv = 1;
/* Must use 5-tap filter? */
@@ -1778,6 +1870,12 @@
_dispc_set_plane_ba0(plane, paddr + offset0);
_dispc_set_plane_ba1(plane, paddr + offset1);
+ if (OMAP_DSS_COLOR_NV12 == color_mode) {
+ _dispc_set_plane_ba0_uv(plane, puv_addr + offset0);
+ _dispc_set_plane_ba1_uv(plane, puv_addr + offset1);
+ }
+
+
_dispc_set_row_inc(plane, row_inc);
_dispc_set_pix_inc(plane, pix_inc);
@@ -1791,7 +1889,8 @@
if (plane != OMAP_DSS_GFX) {
_dispc_set_scaling(plane, width, height,
out_width, out_height,
- ilace, five_taps, fieldmode);
+ ilace, five_taps, fieldmode,
+ color_mode, rotation);
_dispc_set_vid_size(plane, out_width, out_height);
_dispc_set_vid_color_conv(plane, cconv);
}
@@ -1806,7 +1905,7 @@
static void _dispc_enable_plane(enum omap_plane plane, bool enable)
{
- REG_FLD_MOD(dispc_reg_att[plane], enable ? 1 : 0, 0, 0);
+ REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
}
static void dispc_disable_isr(void *data, u32 mask)
@@ -2353,14 +2452,20 @@
unsigned long dispc_fclk_rate(void)
{
+ struct platform_device *dsidev;
unsigned long r = 0;
switch (dss_get_dispc_clk_source()) {
- case DSS_CLK_SRC_FCK:
+ case OMAP_DSS_CLK_SRC_FCK:
r = dss_clk_get_rate(DSS_CLK_FCK);
break;
- case DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
- r = dsi_get_pll_hsdiv_dispc_rate();
+ case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
+ dsidev = dsi_get_dsidev_from_id(0);
+ r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
+ break;
+ case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
+ dsidev = dsi_get_dsidev_from_id(1);
+ r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
break;
default:
BUG();
@@ -2371,6 +2476,7 @@
unsigned long dispc_lclk_rate(enum omap_channel channel)
{
+ struct platform_device *dsidev;
int lcd;
unsigned long r;
u32 l;
@@ -2380,11 +2486,16 @@
lcd = FLD_GET(l, 23, 16);
switch (dss_get_lcd_clk_source(channel)) {
- case DSS_CLK_SRC_FCK:
+ case OMAP_DSS_CLK_SRC_FCK:
r = dss_clk_get_rate(DSS_CLK_FCK);
break;
- case DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
- r = dsi_get_pll_hsdiv_dispc_rate();
+ case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
+ dsidev = dsi_get_dsidev_from_id(0);
+ r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
+ break;
+ case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
+ dsidev = dsi_get_dsidev_from_id(1);
+ r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
break;
default:
BUG();
@@ -2412,8 +2523,8 @@
{
int lcd, pcd;
u32 l;
- enum dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
- enum dss_clk_source lcd_clk_src;
+ enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
+ enum omap_dss_clk_source lcd_clk_src;
enable_clocks(1);
@@ -2516,7 +2627,7 @@
void dispc_dump_regs(struct seq_file *s)
{
-#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dispc_read_reg(r))
+#define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
@@ -2528,152 +2639,227 @@
DUMPREG(DISPC_CONTROL);
DUMPREG(DISPC_CONFIG);
DUMPREG(DISPC_CAPABLE);
- DUMPREG(DISPC_DEFAULT_COLOR(0));
- DUMPREG(DISPC_DEFAULT_COLOR(1));
- DUMPREG(DISPC_TRANS_COLOR(0));
- DUMPREG(DISPC_TRANS_COLOR(1));
+ DUMPREG(DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD));
+ DUMPREG(DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_DIGIT));
+ DUMPREG(DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_LCD));
+ DUMPREG(DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_DIGIT));
DUMPREG(DISPC_LINE_STATUS);
DUMPREG(DISPC_LINE_NUMBER);
- DUMPREG(DISPC_TIMING_H(0));
- DUMPREG(DISPC_TIMING_V(0));
- DUMPREG(DISPC_POL_FREQ(0));
- DUMPREG(DISPC_DIVISORo(0));
+ DUMPREG(DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD));
+ DUMPREG(DISPC_TIMING_V(OMAP_DSS_CHANNEL_LCD));
+ DUMPREG(DISPC_POL_FREQ(OMAP_DSS_CHANNEL_LCD));
+ DUMPREG(DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD));
DUMPREG(DISPC_GLOBAL_ALPHA);
- DUMPREG(DISPC_SIZE_DIG);
- DUMPREG(DISPC_SIZE_LCD(0));
+ DUMPREG(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_DIGIT));
+ DUMPREG(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_LCD));
if (dss_has_feature(FEAT_MGR_LCD2)) {
DUMPREG(DISPC_CONTROL2);
DUMPREG(DISPC_CONFIG2);
- DUMPREG(DISPC_DEFAULT_COLOR(2));
- DUMPREG(DISPC_TRANS_COLOR(2));
- DUMPREG(DISPC_TIMING_H(2));
- DUMPREG(DISPC_TIMING_V(2));
- DUMPREG(DISPC_POL_FREQ(2));
- DUMPREG(DISPC_DIVISORo(2));
- DUMPREG(DISPC_SIZE_LCD(2));
+ DUMPREG(DISPC_DEFAULT_COLOR(OMAP_DSS_CHANNEL_LCD2));
+ DUMPREG(DISPC_TRANS_COLOR(OMAP_DSS_CHANNEL_LCD2));
+ DUMPREG(DISPC_TIMING_H(OMAP_DSS_CHANNEL_LCD2));
+ DUMPREG(DISPC_TIMING_V(OMAP_DSS_CHANNEL_LCD2));
+ DUMPREG(DISPC_POL_FREQ(OMAP_DSS_CHANNEL_LCD2));
+ DUMPREG(DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD2));
+ DUMPREG(DISPC_SIZE_MGR(OMAP_DSS_CHANNEL_LCD2));
}
- DUMPREG(DISPC_GFX_BA0);
- DUMPREG(DISPC_GFX_BA1);
- DUMPREG(DISPC_GFX_POSITION);
- DUMPREG(DISPC_GFX_SIZE);
- DUMPREG(DISPC_GFX_ATTRIBUTES);
- DUMPREG(DISPC_GFX_FIFO_THRESHOLD);
- DUMPREG(DISPC_GFX_FIFO_SIZE_STATUS);
- DUMPREG(DISPC_GFX_ROW_INC);
- DUMPREG(DISPC_GFX_PIXEL_INC);
- DUMPREG(DISPC_GFX_WINDOW_SKIP);
- DUMPREG(DISPC_GFX_TABLE_BA);
+ DUMPREG(DISPC_OVL_BA0(OMAP_DSS_GFX));
+ DUMPREG(DISPC_OVL_BA1(OMAP_DSS_GFX));
+ DUMPREG(DISPC_OVL_POSITION(OMAP_DSS_GFX));
+ DUMPREG(DISPC_OVL_SIZE(OMAP_DSS_GFX));
+ DUMPREG(DISPC_OVL_ATTRIBUTES(OMAP_DSS_GFX));
+ DUMPREG(DISPC_OVL_FIFO_THRESHOLD(OMAP_DSS_GFX));
+ DUMPREG(DISPC_OVL_FIFO_SIZE_STATUS(OMAP_DSS_GFX));
+ DUMPREG(DISPC_OVL_ROW_INC(OMAP_DSS_GFX));
+ DUMPREG(DISPC_OVL_PIXEL_INC(OMAP_DSS_GFX));
+ DUMPREG(DISPC_OVL_WINDOW_SKIP(OMAP_DSS_GFX));
+ DUMPREG(DISPC_OVL_TABLE_BA(OMAP_DSS_GFX));
- DUMPREG(DISPC_DATA_CYCLE1(0));
- DUMPREG(DISPC_DATA_CYCLE2(0));
- DUMPREG(DISPC_DATA_CYCLE3(0));
+ DUMPREG(DISPC_DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD));
+ DUMPREG(DISPC_DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD));
+ DUMPREG(DISPC_DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD));
- DUMPREG(DISPC_CPR_COEF_R(0));
- DUMPREG(DISPC_CPR_COEF_G(0));
- DUMPREG(DISPC_CPR_COEF_B(0));
+ DUMPREG(DISPC_CPR_COEF_R(OMAP_DSS_CHANNEL_LCD));
+ DUMPREG(DISPC_CPR_COEF_G(OMAP_DSS_CHANNEL_LCD));
+ DUMPREG(DISPC_CPR_COEF_B(OMAP_DSS_CHANNEL_LCD));
if (dss_has_feature(FEAT_MGR_LCD2)) {
- DUMPREG(DISPC_DATA_CYCLE1(2));
- DUMPREG(DISPC_DATA_CYCLE2(2));
- DUMPREG(DISPC_DATA_CYCLE3(2));
+ DUMPREG(DISPC_DATA_CYCLE1(OMAP_DSS_CHANNEL_LCD2));
+ DUMPREG(DISPC_DATA_CYCLE2(OMAP_DSS_CHANNEL_LCD2));
+ DUMPREG(DISPC_DATA_CYCLE3(OMAP_DSS_CHANNEL_LCD2));
- DUMPREG(DISPC_CPR_COEF_R(2));
- DUMPREG(DISPC_CPR_COEF_G(2));
- DUMPREG(DISPC_CPR_COEF_B(2));
+ DUMPREG(DISPC_CPR_COEF_R(OMAP_DSS_CHANNEL_LCD2));
+ DUMPREG(DISPC_CPR_COEF_G(OMAP_DSS_CHANNEL_LCD2));
+ DUMPREG(DISPC_CPR_COEF_B(OMAP_DSS_CHANNEL_LCD2));
}
- DUMPREG(DISPC_GFX_PRELOAD);
+ DUMPREG(DISPC_OVL_PRELOAD(OMAP_DSS_GFX));
- DUMPREG(DISPC_VID_BA0(0));
- DUMPREG(DISPC_VID_BA1(0));
- DUMPREG(DISPC_VID_POSITION(0));
- DUMPREG(DISPC_VID_SIZE(0));
- DUMPREG(DISPC_VID_ATTRIBUTES(0));
- DUMPREG(DISPC_VID_FIFO_THRESHOLD(0));
- DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(0));
- DUMPREG(DISPC_VID_ROW_INC(0));
- DUMPREG(DISPC_VID_PIXEL_INC(0));
- DUMPREG(DISPC_VID_FIR(0));
- DUMPREG(DISPC_VID_PICTURE_SIZE(0));
- DUMPREG(DISPC_VID_ACCU0(0));
- DUMPREG(DISPC_VID_ACCU1(0));
+ DUMPREG(DISPC_OVL_BA0(OMAP_DSS_VIDEO1));
+ DUMPREG(DISPC_OVL_BA1(OMAP_DSS_VIDEO1));
+ DUMPREG(DISPC_OVL_POSITION(OMAP_DSS_VIDEO1));
+ DUMPREG(DISPC_OVL_SIZE(OMAP_DSS_VIDEO1));
+ DUMPREG(DISPC_OVL_ATTRIBUTES(OMAP_DSS_VIDEO1));
+ DUMPREG(DISPC_OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO1));
+ DUMPREG(DISPC_OVL_FIFO_SIZE_STATUS(OMAP_DSS_VIDEO1));
+ DUMPREG(DISPC_OVL_ROW_INC(OMAP_DSS_VIDEO1));
+ DUMPREG(DISPC_OVL_PIXEL_INC(OMAP_DSS_VIDEO1));
+ DUMPREG(DISPC_OVL_FIR(OMAP_DSS_VIDEO1));
+ DUMPREG(DISPC_OVL_PICTURE_SIZE(OMAP_DSS_VIDEO1));
+ DUMPREG(DISPC_OVL_ACCU0(OMAP_DSS_VIDEO1));
+ DUMPREG(DISPC_OVL_ACCU1(OMAP_DSS_VIDEO1));
- DUMPREG(DISPC_VID_BA0(1));
- DUMPREG(DISPC_VID_BA1(1));
- DUMPREG(DISPC_VID_POSITION(1));
- DUMPREG(DISPC_VID_SIZE(1));
- DUMPREG(DISPC_VID_ATTRIBUTES(1));
- DUMPREG(DISPC_VID_FIFO_THRESHOLD(1));
- DUMPREG(DISPC_VID_FIFO_SIZE_STATUS(1));
- DUMPREG(DISPC_VID_ROW_INC(1));
- DUMPREG(DISPC_VID_PIXEL_INC(1));
- DUMPREG(DISPC_VID_FIR(1));
- DUMPREG(DISPC_VID_PICTURE_SIZE(1));
- DUMPREG(DISPC_VID_ACCU0(1));
- DUMPREG(DISPC_VID_ACCU1(1));
+ DUMPREG(DISPC_OVL_BA0(OMAP_DSS_VIDEO2));
+ DUMPREG(DISPC_OVL_BA1(OMAP_DSS_VIDEO2));
+ DUMPREG(DISPC_OVL_POSITION(OMAP_DSS_VIDEO2));
+ DUMPREG(DISPC_OVL_SIZE(OMAP_DSS_VIDEO2));
+ DUMPREG(DISPC_OVL_ATTRIBUTES(OMAP_DSS_VIDEO2));
+ DUMPREG(DISPC_OVL_FIFO_THRESHOLD(OMAP_DSS_VIDEO2));
+ DUMPREG(DISPC_OVL_FIFO_SIZE_STATUS(OMAP_DSS_VIDEO2));
+ DUMPREG(DISPC_OVL_ROW_INC(OMAP_DSS_VIDEO2));
+ DUMPREG(DISPC_OVL_PIXEL_INC(OMAP_DSS_VIDEO2));
+ DUMPREG(DISPC_OVL_FIR(OMAP_DSS_VIDEO2));
+ DUMPREG(DISPC_OVL_PICTURE_SIZE(OMAP_DSS_VIDEO2));
+ DUMPREG(DISPC_OVL_ACCU0(OMAP_DSS_VIDEO2));
+ DUMPREG(DISPC_OVL_ACCU1(OMAP_DSS_VIDEO2));
- DUMPREG(DISPC_VID_FIR_COEF_H(0, 0));
- DUMPREG(DISPC_VID_FIR_COEF_H(0, 1));
- DUMPREG(DISPC_VID_FIR_COEF_H(0, 2));
- DUMPREG(DISPC_VID_FIR_COEF_H(0, 3));
- DUMPREG(DISPC_VID_FIR_COEF_H(0, 4));
- DUMPREG(DISPC_VID_FIR_COEF_H(0, 5));
- DUMPREG(DISPC_VID_FIR_COEF_H(0, 6));
- DUMPREG(DISPC_VID_FIR_COEF_H(0, 7));
- DUMPREG(DISPC_VID_FIR_COEF_HV(0, 0));
- DUMPREG(DISPC_VID_FIR_COEF_HV(0, 1));
- DUMPREG(DISPC_VID_FIR_COEF_HV(0, 2));
- DUMPREG(DISPC_VID_FIR_COEF_HV(0, 3));
- DUMPREG(DISPC_VID_FIR_COEF_HV(0, 4));
- DUMPREG(DISPC_VID_FIR_COEF_HV(0, 5));
- DUMPREG(DISPC_VID_FIR_COEF_HV(0, 6));
- DUMPREG(DISPC_VID_FIR_COEF_HV(0, 7));
- DUMPREG(DISPC_VID_CONV_COEF(0, 0));
- DUMPREG(DISPC_VID_CONV_COEF(0, 1));
- DUMPREG(DISPC_VID_CONV_COEF(0, 2));
- DUMPREG(DISPC_VID_CONV_COEF(0, 3));
- DUMPREG(DISPC_VID_CONV_COEF(0, 4));
- DUMPREG(DISPC_VID_FIR_COEF_V(0, 0));
- DUMPREG(DISPC_VID_FIR_COEF_V(0, 1));
- DUMPREG(DISPC_VID_FIR_COEF_V(0, 2));
- DUMPREG(DISPC_VID_FIR_COEF_V(0, 3));
- DUMPREG(DISPC_VID_FIR_COEF_V(0, 4));
- DUMPREG(DISPC_VID_FIR_COEF_V(0, 5));
- DUMPREG(DISPC_VID_FIR_COEF_V(0, 6));
- DUMPREG(DISPC_VID_FIR_COEF_V(0, 7));
+ DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 0));
+ DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 1));
+ DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 2));
+ DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 3));
+ DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 4));
+ DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 5));
+ DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 6));
+ DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO1, 7));
+ DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 0));
+ DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 1));
+ DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 2));
+ DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 3));
+ DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 4));
+ DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 5));
+ DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 6));
+ DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO1, 7));
+ DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 0));
+ DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 1));
+ DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 2));
+ DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 3));
+ DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO1, 4));
+ DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 0));
+ DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 1));
+ DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 2));
+ DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 3));
+ DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 4));
+ DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 5));
+ DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 6));
+ DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO1, 7));
- DUMPREG(DISPC_VID_FIR_COEF_H(1, 0));
- DUMPREG(DISPC_VID_FIR_COEF_H(1, 1));
- DUMPREG(DISPC_VID_FIR_COEF_H(1, 2));
- DUMPREG(DISPC_VID_FIR_COEF_H(1, 3));
- DUMPREG(DISPC_VID_FIR_COEF_H(1, 4));
- DUMPREG(DISPC_VID_FIR_COEF_H(1, 5));
- DUMPREG(DISPC_VID_FIR_COEF_H(1, 6));
- DUMPREG(DISPC_VID_FIR_COEF_H(1, 7));
- DUMPREG(DISPC_VID_FIR_COEF_HV(1, 0));
- DUMPREG(DISPC_VID_FIR_COEF_HV(1, 1));
- DUMPREG(DISPC_VID_FIR_COEF_HV(1, 2));
- DUMPREG(DISPC_VID_FIR_COEF_HV(1, 3));
- DUMPREG(DISPC_VID_FIR_COEF_HV(1, 4));
- DUMPREG(DISPC_VID_FIR_COEF_HV(1, 5));
- DUMPREG(DISPC_VID_FIR_COEF_HV(1, 6));
- DUMPREG(DISPC_VID_FIR_COEF_HV(1, 7));
- DUMPREG(DISPC_VID_CONV_COEF(1, 0));
- DUMPREG(DISPC_VID_CONV_COEF(1, 1));
- DUMPREG(DISPC_VID_CONV_COEF(1, 2));
- DUMPREG(DISPC_VID_CONV_COEF(1, 3));
- DUMPREG(DISPC_VID_CONV_COEF(1, 4));
- DUMPREG(DISPC_VID_FIR_COEF_V(1, 0));
- DUMPREG(DISPC_VID_FIR_COEF_V(1, 1));
- DUMPREG(DISPC_VID_FIR_COEF_V(1, 2));
- DUMPREG(DISPC_VID_FIR_COEF_V(1, 3));
- DUMPREG(DISPC_VID_FIR_COEF_V(1, 4));
- DUMPREG(DISPC_VID_FIR_COEF_V(1, 5));
- DUMPREG(DISPC_VID_FIR_COEF_V(1, 6));
- DUMPREG(DISPC_VID_FIR_COEF_V(1, 7));
+ if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
+ DUMPREG(DISPC_OVL_BA0_UV(OMAP_DSS_VIDEO1));
+ DUMPREG(DISPC_OVL_BA1_UV(OMAP_DSS_VIDEO1));
+ DUMPREG(DISPC_OVL_FIR2(OMAP_DSS_VIDEO1));
+ DUMPREG(DISPC_OVL_ACCU2_0(OMAP_DSS_VIDEO1));
+ DUMPREG(DISPC_OVL_ACCU2_1(OMAP_DSS_VIDEO1));
- DUMPREG(DISPC_VID_PRELOAD(0));
- DUMPREG(DISPC_VID_PRELOAD(1));
+ DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 0));
+ DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 1));
+ DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 2));
+ DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 3));
+ DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 4));
+ DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 5));
+ DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 6));
+ DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO1, 7));
+
+ DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 0));
+ DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 1));
+ DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 2));
+ DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 3));
+ DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 4));
+ DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 5));
+ DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 6));
+ DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO1, 7));
+
+ DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 0));
+ DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 1));
+ DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 2));
+ DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 3));
+ DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 4));
+ DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 5));
+ DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 6));
+ DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO1, 7));
+ }
+ if (dss_has_feature(FEAT_ATTR2))
+ DUMPREG(DISPC_OVL_ATTRIBUTES2(OMAP_DSS_VIDEO1));
+
+
+ DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 0));
+ DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 1));
+ DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 2));
+ DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 3));
+ DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 4));
+ DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 5));
+ DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 6));
+ DUMPREG(DISPC_OVL_FIR_COEF_H(OMAP_DSS_VIDEO2, 7));
+ DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 0));
+ DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 1));
+ DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 2));
+ DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 3));
+ DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 4));
+ DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 5));
+ DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 6));
+ DUMPREG(DISPC_OVL_FIR_COEF_HV(OMAP_DSS_VIDEO2, 7));
+ DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 0));
+ DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 1));
+ DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 2));
+ DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 3));
+ DUMPREG(DISPC_OVL_CONV_COEF(OMAP_DSS_VIDEO2, 4));
+ DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 0));
+ DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 1));
+ DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 2));
+ DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 3));
+ DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 4));
+ DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 5));
+ DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 6));
+ DUMPREG(DISPC_OVL_FIR_COEF_V(OMAP_DSS_VIDEO2, 7));
+
+ if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
+ DUMPREG(DISPC_OVL_BA0_UV(OMAP_DSS_VIDEO2));
+ DUMPREG(DISPC_OVL_BA1_UV(OMAP_DSS_VIDEO2));
+ DUMPREG(DISPC_OVL_FIR2(OMAP_DSS_VIDEO2));
+ DUMPREG(DISPC_OVL_ACCU2_0(OMAP_DSS_VIDEO2));
+ DUMPREG(DISPC_OVL_ACCU2_1(OMAP_DSS_VIDEO2));
+
+ DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 0));
+ DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 1));
+ DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 2));
+ DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 3));
+ DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 4));
+ DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 5));
+ DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 6));
+ DUMPREG(DISPC_OVL_FIR_COEF_H2(OMAP_DSS_VIDEO2, 7));
+
+ DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 0));
+ DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 1));
+ DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 2));
+ DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 3));
+ DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 4));
+ DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 5));
+ DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 6));
+ DUMPREG(DISPC_OVL_FIR_COEF_HV2(OMAP_DSS_VIDEO2, 7));
+
+ DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 0));
+ DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 1));
+ DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 2));
+ DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 3));
+ DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 4));
+ DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 5));
+ DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 6));
+ DUMPREG(DISPC_OVL_FIR_COEF_V2(OMAP_DSS_VIDEO2, 7));
+ }
+ if (dss_has_feature(FEAT_ATTR2))
+ DUMPREG(DISPC_OVL_ATTRIBUTES2(OMAP_DSS_VIDEO2));
+
+ DUMPREG(DISPC_OVL_PRELOAD(OMAP_DSS_VIDEO1));
+ DUMPREG(DISPC_OVL_PRELOAD(OMAP_DSS_VIDEO2));
dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
#undef DUMPREG
@@ -3388,11 +3574,12 @@
bool ilace,
enum omap_dss_rotation_type rotation_type,
u8 rotation, bool mirror, u8 global_alpha,
- u8 pre_mult_alpha, enum omap_channel channel)
+ u8 pre_mult_alpha, enum omap_channel channel,
+ u32 puv_addr)
{
int r = 0;
- DSSDBG("dispc_setup_plane %d, pa %x, sw %d, %d,%d, %dx%d -> "
+ DSSDBG("dispc_setup_plane %d, pa %x, sw %d, %d, %d, %dx%d -> "
"%dx%d, ilace %d, cmode %x, rot %d, mir %d chan %d\n",
plane, paddr, screen_width, pos_x, pos_y,
width, height,
@@ -3411,7 +3598,8 @@
rotation_type,
rotation, mirror,
global_alpha,
- pre_mult_alpha, channel);
+ pre_mult_alpha,
+ channel, puv_addr);
enable_clocks(0);
diff --git a/drivers/video/omap2/dss/dispc.h b/drivers/video/omap2/dss/dispc.h
new file mode 100644
index 0000000..6c9ee0a
--- /dev/null
+++ b/drivers/video/omap2/dss/dispc.h
@@ -0,0 +1,691 @@
+/*
+ * linux/drivers/video/omap2/dss/dispc.h
+ *
+ * Copyright (C) 2011 Texas Instruments
+ * Author: Archit Taneja <archit@ti.com>
+ *
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __OMAP2_DISPC_REG_H
+#define __OMAP2_DISPC_REG_H
+
+/* DISPC common registers */
+#define DISPC_REVISION 0x0000
+#define DISPC_SYSCONFIG 0x0010
+#define DISPC_SYSSTATUS 0x0014
+#define DISPC_IRQSTATUS 0x0018
+#define DISPC_IRQENABLE 0x001C
+#define DISPC_CONTROL 0x0040
+#define DISPC_CONFIG 0x0044
+#define DISPC_CAPABLE 0x0048
+#define DISPC_LINE_STATUS 0x005C
+#define DISPC_LINE_NUMBER 0x0060
+#define DISPC_GLOBAL_ALPHA 0x0074
+#define DISPC_CONTROL2 0x0238
+#define DISPC_CONFIG2 0x0620
+#define DISPC_DIVISOR 0x0804
+
+/* DISPC overlay registers */
+#define DISPC_OVL_BA0(n) (DISPC_OVL_BASE(n) + \
+ DISPC_BA0_OFFSET(n))
+#define DISPC_OVL_BA1(n) (DISPC_OVL_BASE(n) + \
+ DISPC_BA1_OFFSET(n))
+#define DISPC_OVL_BA0_UV(n) (DISPC_OVL_BASE(n) + \
+ DISPC_BA0_UV_OFFSET(n))
+#define DISPC_OVL_BA1_UV(n) (DISPC_OVL_BASE(n) + \
+ DISPC_BA1_UV_OFFSET(n))
+#define DISPC_OVL_POSITION(n) (DISPC_OVL_BASE(n) + \
+ DISPC_POS_OFFSET(n))
+#define DISPC_OVL_SIZE(n) (DISPC_OVL_BASE(n) + \
+ DISPC_SIZE_OFFSET(n))
+#define DISPC_OVL_ATTRIBUTES(n) (DISPC_OVL_BASE(n) + \
+ DISPC_ATTR_OFFSET(n))
+#define DISPC_OVL_ATTRIBUTES2(n) (DISPC_OVL_BASE(n) + \
+ DISPC_ATTR2_OFFSET(n))
+#define DISPC_OVL_FIFO_THRESHOLD(n) (DISPC_OVL_BASE(n) + \
+ DISPC_FIFO_THRESH_OFFSET(n))
+#define DISPC_OVL_FIFO_SIZE_STATUS(n) (DISPC_OVL_BASE(n) + \
+ DISPC_FIFO_SIZE_STATUS_OFFSET(n))
+#define DISPC_OVL_ROW_INC(n) (DISPC_OVL_BASE(n) + \
+ DISPC_ROW_INC_OFFSET(n))
+#define DISPC_OVL_PIXEL_INC(n) (DISPC_OVL_BASE(n) + \
+ DISPC_PIX_INC_OFFSET(n))
+#define DISPC_OVL_WINDOW_SKIP(n) (DISPC_OVL_BASE(n) + \
+ DISPC_WINDOW_SKIP_OFFSET(n))
+#define DISPC_OVL_TABLE_BA(n) (DISPC_OVL_BASE(n) + \
+ DISPC_TABLE_BA_OFFSET(n))
+#define DISPC_OVL_FIR(n) (DISPC_OVL_BASE(n) + \
+ DISPC_FIR_OFFSET(n))
+#define DISPC_OVL_FIR2(n) (DISPC_OVL_BASE(n) + \
+ DISPC_FIR2_OFFSET(n))
+#define DISPC_OVL_PICTURE_SIZE(n) (DISPC_OVL_BASE(n) + \
+ DISPC_PIC_SIZE_OFFSET(n))
+#define DISPC_OVL_ACCU0(n) (DISPC_OVL_BASE(n) + \
+ DISPC_ACCU0_OFFSET(n))
+#define DISPC_OVL_ACCU1(n) (DISPC_OVL_BASE(n) + \
+ DISPC_ACCU1_OFFSET(n))
+#define DISPC_OVL_ACCU2_0(n) (DISPC_OVL_BASE(n) + \
+ DISPC_ACCU2_0_OFFSET(n))
+#define DISPC_OVL_ACCU2_1(n) (DISPC_OVL_BASE(n) + \
+ DISPC_ACCU2_1_OFFSET(n))
+#define DISPC_OVL_FIR_COEF_H(n, i) (DISPC_OVL_BASE(n) + \
+ DISPC_FIR_COEF_H_OFFSET(n, i))
+#define DISPC_OVL_FIR_COEF_HV(n, i) (DISPC_OVL_BASE(n) + \
+ DISPC_FIR_COEF_HV_OFFSET(n, i))
+#define DISPC_OVL_FIR_COEF_H2(n, i) (DISPC_OVL_BASE(n) + \
+ DISPC_FIR_COEF_H2_OFFSET(n, i))
+#define DISPC_OVL_FIR_COEF_HV2(n, i) (DISPC_OVL_BASE(n) + \
+ DISPC_FIR_COEF_HV2_OFFSET(n, i))
+#define DISPC_OVL_CONV_COEF(n, i) (DISPC_OVL_BASE(n) + \
+ DISPC_CONV_COEF_OFFSET(n, i))
+#define DISPC_OVL_FIR_COEF_V(n, i) (DISPC_OVL_BASE(n) + \
+ DISPC_FIR_COEF_V_OFFSET(n, i))
+#define DISPC_OVL_FIR_COEF_V2(n, i) (DISPC_OVL_BASE(n) + \
+ DISPC_FIR_COEF_V2_OFFSET(n, i))
+#define DISPC_OVL_PRELOAD(n) (DISPC_OVL_BASE(n) + \
+ DISPC_PRELOAD_OFFSET(n))
+
+/* DISPC manager/channel specific registers */
+static inline u16 DISPC_DEFAULT_COLOR(enum omap_channel channel)
+{
+ switch (channel) {
+ case OMAP_DSS_CHANNEL_LCD:
+ return 0x004C;
+ case OMAP_DSS_CHANNEL_DIGIT:
+ return 0x0050;
+ case OMAP_DSS_CHANNEL_LCD2:
+ return 0x03AC;
+ default:
+ BUG();
+ }
+}
+
+static inline u16 DISPC_TRANS_COLOR(enum omap_channel channel)
+{
+ switch (channel) {
+ case OMAP_DSS_CHANNEL_LCD:
+ return 0x0054;
+ case OMAP_DSS_CHANNEL_DIGIT:
+ return 0x0058;
+ case OMAP_DSS_CHANNEL_LCD2:
+ return 0x03B0;
+ default:
+ BUG();
+ }
+}
+
+static inline u16 DISPC_TIMING_H(enum omap_channel channel)
+{
+ switch (channel) {
+ case OMAP_DSS_CHANNEL_LCD:
+ return 0x0064;
+ case OMAP_DSS_CHANNEL_DIGIT:
+ BUG();
+ case OMAP_DSS_CHANNEL_LCD2:
+ return 0x0400;
+ default:
+ BUG();
+ }
+}
+
+static inline u16 DISPC_TIMING_V(enum omap_channel channel)
+{
+ switch (channel) {
+ case OMAP_DSS_CHANNEL_LCD:
+ return 0x0068;
+ case OMAP_DSS_CHANNEL_DIGIT:
+ BUG();
+ case OMAP_DSS_CHANNEL_LCD2:
+ return 0x0404;
+ default:
+ BUG();
+ }
+}
+
+static inline u16 DISPC_POL_FREQ(enum omap_channel channel)
+{
+ switch (channel) {
+ case OMAP_DSS_CHANNEL_LCD:
+ return 0x006C;
+ case OMAP_DSS_CHANNEL_DIGIT:
+ BUG();
+ case OMAP_DSS_CHANNEL_LCD2:
+ return 0x0408;
+ default:
+ BUG();
+ }
+}
+
+static inline u16 DISPC_DIVISORo(enum omap_channel channel)
+{
+ switch (channel) {
+ case OMAP_DSS_CHANNEL_LCD:
+ return 0x0070;
+ case OMAP_DSS_CHANNEL_DIGIT:
+ BUG();
+ case OMAP_DSS_CHANNEL_LCD2:
+ return 0x040C;
+ default:
+ BUG();
+ }
+}
+
+/* Named as DISPC_SIZE_LCD, DISPC_SIZE_DIGIT and DISPC_SIZE_LCD2 in TRM */
+static inline u16 DISPC_SIZE_MGR(enum omap_channel channel)
+{
+ switch (channel) {
+ case OMAP_DSS_CHANNEL_LCD:
+ return 0x007C;
+ case OMAP_DSS_CHANNEL_DIGIT:
+ return 0x0078;
+ case OMAP_DSS_CHANNEL_LCD2:
+ return 0x03CC;
+ default:
+ BUG();
+ }
+}
+
+static inline u16 DISPC_DATA_CYCLE1(enum omap_channel channel)
+{
+ switch (channel) {
+ case OMAP_DSS_CHANNEL_LCD:
+ return 0x01D4;
+ case OMAP_DSS_CHANNEL_DIGIT:
+ BUG();
+ case OMAP_DSS_CHANNEL_LCD2:
+ return 0x03C0;
+ default:
+ BUG();
+ }
+}
+
+static inline u16 DISPC_DATA_CYCLE2(enum omap_channel channel)
+{
+ switch (channel) {
+ case OMAP_DSS_CHANNEL_LCD:
+ return 0x01D8;
+ case OMAP_DSS_CHANNEL_DIGIT:
+ BUG();
+ case OMAP_DSS_CHANNEL_LCD2:
+ return 0x03C4;
+ default:
+ BUG();
+ }
+}
+
+static inline u16 DISPC_DATA_CYCLE3(enum omap_channel channel)
+{
+ switch (channel) {
+ case OMAP_DSS_CHANNEL_LCD:
+ return 0x01DC;
+ case OMAP_DSS_CHANNEL_DIGIT:
+ BUG();
+ case OMAP_DSS_CHANNEL_LCD2:
+ return 0x03C8;
+ default:
+ BUG();
+ }
+}
+
+static inline u16 DISPC_CPR_COEF_R(enum omap_channel channel)
+{
+ switch (channel) {
+ case OMAP_DSS_CHANNEL_LCD:
+ return 0x0220;
+ case OMAP_DSS_CHANNEL_DIGIT:
+ BUG();
+ case OMAP_DSS_CHANNEL_LCD2:
+ return 0x03BC;
+ default:
+ BUG();
+ }
+}
+
+static inline u16 DISPC_CPR_COEF_G(enum omap_channel channel)
+{
+ switch (channel) {
+ case OMAP_DSS_CHANNEL_LCD:
+ return 0x0224;
+ case OMAP_DSS_CHANNEL_DIGIT:
+ BUG();
+ case OMAP_DSS_CHANNEL_LCD2:
+ return 0x03B8;
+ default:
+ BUG();
+ }
+}
+
+static inline u16 DISPC_CPR_COEF_B(enum omap_channel channel)
+{
+ switch (channel) {
+ case OMAP_DSS_CHANNEL_LCD:
+ return 0x0228;
+ case OMAP_DSS_CHANNEL_DIGIT:
+ BUG();
+ case OMAP_DSS_CHANNEL_LCD2:
+ return 0x03B4;
+ default:
+ BUG();
+ }
+}
+
+/* DISPC overlay register base addresses */
+static inline u16 DISPC_OVL_BASE(enum omap_plane plane)
+{
+ switch (plane) {
+ case OMAP_DSS_GFX:
+ return 0x0080;
+ case OMAP_DSS_VIDEO1:
+ return 0x00BC;
+ case OMAP_DSS_VIDEO2:
+ return 0x014C;
+ default:
+ BUG();
+ }
+}
+
+/* DISPC overlay register offsets */
+static inline u16 DISPC_BA0_OFFSET(enum omap_plane plane)
+{
+ switch (plane) {
+ case OMAP_DSS_GFX:
+ case OMAP_DSS_VIDEO1:
+ case OMAP_DSS_VIDEO2:
+ return 0x0000;
+ default:
+ BUG();
+ }
+}
+
+static inline u16 DISPC_BA1_OFFSET(enum omap_plane plane)
+{
+ switch (plane) {
+ case OMAP_DSS_GFX:
+ case OMAP_DSS_VIDEO1:
+ case OMAP_DSS_VIDEO2:
+ return 0x0004;
+ default:
+ BUG();
+ }
+}
+
+static inline u16 DISPC_BA0_UV_OFFSET(enum omap_plane plane)
+{
+ switch (plane) {
+ case OMAP_DSS_GFX:
+ BUG();
+ case OMAP_DSS_VIDEO1:
+ return 0x0544;
+ case OMAP_DSS_VIDEO2:
+ return 0x04BC;
+ default:
+ BUG();
+ }
+}
+
+static inline u16 DISPC_BA1_UV_OFFSET(enum omap_plane plane)
+{
+ switch (plane) {
+ case OMAP_DSS_GFX:
+ BUG();
+ case OMAP_DSS_VIDEO1:
+ return 0x0548;
+ case OMAP_DSS_VIDEO2:
+ return 0x04C0;
+ default:
+ BUG();
+ }
+}
+
+static inline u16 DISPC_POS_OFFSET(enum omap_plane plane)
+{
+ switch (plane) {
+ case OMAP_DSS_GFX:
+ case OMAP_DSS_VIDEO1:
+ case OMAP_DSS_VIDEO2:
+ return 0x0008;
+ default:
+ BUG();
+ }
+}
+
+static inline u16 DISPC_SIZE_OFFSET(enum omap_plane plane)
+{
+ switch (plane) {
+ case OMAP_DSS_GFX:
+ case OMAP_DSS_VIDEO1:
+ case OMAP_DSS_VIDEO2:
+ return 0x000C;
+ default:
+ BUG();
+ }
+}
+
+static inline u16 DISPC_ATTR_OFFSET(enum omap_plane plane)
+{
+ switch (plane) {
+ case OMAP_DSS_GFX:
+ return 0x0020;
+ case OMAP_DSS_VIDEO1:
+ case OMAP_DSS_VIDEO2:
+ return 0x0010;
+ default:
+ BUG();
+ }
+}
+
+static inline u16 DISPC_ATTR2_OFFSET(enum omap_plane plane)
+{
+ switch (plane) {
+ case OMAP_DSS_GFX:
+ BUG();
+ case OMAP_DSS_VIDEO1:
+ return 0x0568;
+ case OMAP_DSS_VIDEO2:
+ return 0x04DC;
+ default:
+ BUG();
+ }
+}
+
+static inline u16 DISPC_FIFO_THRESH_OFFSET(enum omap_plane plane)
+{
+ switch (plane) {
+ case OMAP_DSS_GFX:
+ return 0x0024;
+ case OMAP_DSS_VIDEO1:
+ case OMAP_DSS_VIDEO2:
+ return 0x0014;
+ default:
+ BUG();
+ }
+}
+
+static inline u16 DISPC_FIFO_SIZE_STATUS_OFFSET(enum omap_plane plane)
+{
+ switch (plane) {
+ case OMAP_DSS_GFX:
+ return 0x0028;
+ case OMAP_DSS_VIDEO1:
+ case OMAP_DSS_VIDEO2:
+ return 0x0018;
+ default:
+ BUG();
+ }
+}
+
+static inline u16 DISPC_ROW_INC_OFFSET(enum omap_plane plane)
+{
+ switch (plane) {
+ case OMAP_DSS_GFX:
+ return 0x002C;
+ case OMAP_DSS_VIDEO1:
+ case OMAP_DSS_VIDEO2:
+ return 0x001C;
+ default:
+ BUG();
+ }
+}
+
+static inline u16 DISPC_PIX_INC_OFFSET(enum omap_plane plane)
+{
+ switch (plane) {
+ case OMAP_DSS_GFX:
+ return 0x0030;
+ case OMAP_DSS_VIDEO1:
+ case OMAP_DSS_VIDEO2:
+ return 0x0020;
+ default:
+ BUG();
+ }
+}
+
+static inline u16 DISPC_WINDOW_SKIP_OFFSET(enum omap_plane plane)
+{
+ switch (plane) {
+ case OMAP_DSS_GFX:
+ return 0x0034;
+ case OMAP_DSS_VIDEO1:
+ case OMAP_DSS_VIDEO2:
+ BUG();
+ default:
+ BUG();
+ }
+}
+
+static inline u16 DISPC_TABLE_BA_OFFSET(enum omap_plane plane)
+{
+ switch (plane) {
+ case OMAP_DSS_GFX:
+ return 0x0038;
+ case OMAP_DSS_VIDEO1:
+ case OMAP_DSS_VIDEO2:
+ BUG();
+ default:
+ BUG();
+ }
+}
+
+static inline u16 DISPC_FIR_OFFSET(enum omap_plane plane)
+{
+ switch (plane) {
+ case OMAP_DSS_GFX:
+ BUG();
+ case OMAP_DSS_VIDEO1:
+ case OMAP_DSS_VIDEO2:
+ return 0x0024;
+ default:
+ BUG();
+ }
+}
+
+static inline u16 DISPC_FIR2_OFFSET(enum omap_plane plane)
+{
+ switch (plane) {
+ case OMAP_DSS_GFX:
+ BUG();
+ case OMAP_DSS_VIDEO1:
+ return 0x0580;
+ case OMAP_DSS_VIDEO2:
+ return 0x055C;
+ default:
+ BUG();
+ }
+}
+
+static inline u16 DISPC_PIC_SIZE_OFFSET(enum omap_plane plane)
+{
+ switch (plane) {
+ case OMAP_DSS_GFX:
+ BUG();
+ case OMAP_DSS_VIDEO1:
+ case OMAP_DSS_VIDEO2:
+ return 0x0028;
+ default:
+ BUG();
+ }
+}
+
+
+static inline u16 DISPC_ACCU0_OFFSET(enum omap_plane plane)
+{
+ switch (plane) {
+ case OMAP_DSS_GFX:
+ BUG();
+ case OMAP_DSS_VIDEO1:
+ case OMAP_DSS_VIDEO2:
+ return 0x002C;
+ default:
+ BUG();
+ }
+}
+
+static inline u16 DISPC_ACCU2_0_OFFSET(enum omap_plane plane)
+{
+ switch (plane) {
+ case OMAP_DSS_GFX:
+ BUG();
+ case OMAP_DSS_VIDEO1:
+ return 0x0584;
+ case OMAP_DSS_VIDEO2:
+ return 0x0560;
+ default:
+ BUG();
+ }
+}
+
+static inline u16 DISPC_ACCU1_OFFSET(enum omap_plane plane)
+{
+ switch (plane) {
+ case OMAP_DSS_GFX:
+ BUG();
+ case OMAP_DSS_VIDEO1:
+ case OMAP_DSS_VIDEO2:
+ return 0x0030;
+ default:
+ BUG();
+ }
+}
+
+static inline u16 DISPC_ACCU2_1_OFFSET(enum omap_plane plane)
+{
+ switch (plane) {
+ case OMAP_DSS_GFX:
+ BUG();
+ case OMAP_DSS_VIDEO1:
+ return 0x0588;
+ case OMAP_DSS_VIDEO2:
+ return 0x0564;
+ default:
+ BUG();
+ }
+}
+
+/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
+static inline u16 DISPC_FIR_COEF_H_OFFSET(enum omap_plane plane, u16 i)
+{
+ switch (plane) {
+ case OMAP_DSS_GFX:
+ BUG();
+ case OMAP_DSS_VIDEO1:
+ case OMAP_DSS_VIDEO2:
+ return 0x0034 + i * 0x8;
+ default:
+ BUG();
+ }
+}
+
+/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
+static inline u16 DISPC_FIR_COEF_H2_OFFSET(enum omap_plane plane, u16 i)
+{
+ switch (plane) {
+ case OMAP_DSS_GFX:
+ BUG();
+ case OMAP_DSS_VIDEO1:
+ return 0x058C + i * 0x8;
+ case OMAP_DSS_VIDEO2:
+ return 0x0568 + i * 0x8;
+ default:
+ BUG();
+ }
+}
+
+/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
+static inline u16 DISPC_FIR_COEF_HV_OFFSET(enum omap_plane plane, u16 i)
+{
+ switch (plane) {
+ case OMAP_DSS_GFX:
+ BUG();
+ case OMAP_DSS_VIDEO1:
+ case OMAP_DSS_VIDEO2:
+ return 0x0038 + i * 0x8;
+ default:
+ BUG();
+ }
+}
+
+/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
+static inline u16 DISPC_FIR_COEF_HV2_OFFSET(enum omap_plane plane, u16 i)
+{
+ switch (plane) {
+ case OMAP_DSS_GFX:
+ BUG();
+ case OMAP_DSS_VIDEO1:
+ return 0x0590 + i * 8;
+ case OMAP_DSS_VIDEO2:
+ return 0x056C + i * 0x8;
+ default:
+ BUG();
+ }
+}
+
+/* coef index i = {0, 1, 2, 3, 4,} */
+static inline u16 DISPC_CONV_COEF_OFFSET(enum omap_plane plane, u16 i)
+{
+ switch (plane) {
+ case OMAP_DSS_GFX:
+ BUG();
+ case OMAP_DSS_VIDEO1:
+ case OMAP_DSS_VIDEO2:
+ return 0x0074 + i * 0x4;
+ default:
+ BUG();
+ }
+}
+
+/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
+static inline u16 DISPC_FIR_COEF_V_OFFSET(enum omap_plane plane, u16 i)
+{
+ switch (plane) {
+ case OMAP_DSS_GFX:
+ BUG();
+ case OMAP_DSS_VIDEO1:
+ return 0x0124 + i * 0x4;
+ case OMAP_DSS_VIDEO2:
+ return 0x00B4 + i * 0x4;
+ default:
+ BUG();
+ }
+}
+
+/* coef index i = {0, 1, 2, 3, 4, 5, 6, 7} */
+static inline u16 DISPC_FIR_COEF_V2_OFFSET(enum omap_plane plane, u16 i)
+{
+ switch (plane) {
+ case OMAP_DSS_GFX:
+ BUG();
+ case OMAP_DSS_VIDEO1:
+ return 0x05CC + i * 0x4;
+ case OMAP_DSS_VIDEO2:
+ return 0x05A8 + i * 0x4;
+ default:
+ BUG();
+ }
+}
+
+static inline u16 DISPC_PRELOAD_OFFSET(enum omap_plane plane)
+{
+ switch (plane) {
+ case OMAP_DSS_GFX:
+ return 0x01AC;
+ case OMAP_DSS_VIDEO1:
+ return 0x0174;
+ case OMAP_DSS_VIDEO2:
+ return 0x00E8;
+ default:
+ BUG();
+ }
+}
+#endif
diff --git a/drivers/video/omap2/dss/display.c b/drivers/video/omap2/dss/display.c
index a85a6f3..c2dfc8c 100644
--- a/drivers/video/omap2/dss/display.c
+++ b/drivers/video/omap2/dss/display.c
@@ -27,7 +27,7 @@
#include <linux/jiffies.h>
#include <linux/platform_device.h>
-#include <plat/display.h>
+#include <video/omapdss.h>
#include "dss.h"
static ssize_t display_enabled_show(struct device *dev,
@@ -44,9 +44,13 @@
const char *buf, size_t size)
{
struct omap_dss_device *dssdev = to_dss_device(dev);
- bool enabled, r;
+ int r, enabled;
- enabled = simple_strtoul(buf, NULL, 10);
+ r = kstrtoint(buf, 0, &enabled);
+ if (r)
+ return r;
+
+ enabled = !!enabled;
if (enabled != (dssdev->state != OMAP_DSS_DISPLAY_DISABLED)) {
if (enabled) {
@@ -82,7 +86,9 @@
if (!dssdev->driver->set_update_mode)
return -EINVAL;
- val = simple_strtoul(buf, NULL, 10);
+ r = kstrtoint(buf, 0, &val);
+ if (r)
+ return r;
switch (val) {
case OMAP_DSS_UPDATE_DISABLED:
@@ -114,13 +120,16 @@
struct device_attribute *attr, const char *buf, size_t size)
{
struct omap_dss_device *dssdev = to_dss_device(dev);
- unsigned long te;
- int r;
+ int te, r;
if (!dssdev->driver->enable_te || !dssdev->driver->get_te)
return -ENOENT;
- te = simple_strtoul(buf, NULL, 0);
+ r = kstrtoint(buf, 0, &te);
+ if (r)
+ return r;
+
+ te = !!te;
r = dssdev->driver->enable_te(dssdev, te);
if (r)
@@ -196,13 +205,14 @@
struct device_attribute *attr, const char *buf, size_t size)
{
struct omap_dss_device *dssdev = to_dss_device(dev);
- unsigned long rot;
- int r;
+ int rot, r;
if (!dssdev->driver->set_rotate || !dssdev->driver->get_rotate)
return -ENOENT;
- rot = simple_strtoul(buf, NULL, 0);
+ r = kstrtoint(buf, 0, &rot);
+ if (r)
+ return r;
r = dssdev->driver->set_rotate(dssdev, rot);
if (r)
@@ -226,13 +236,16 @@
struct device_attribute *attr, const char *buf, size_t size)
{
struct omap_dss_device *dssdev = to_dss_device(dev);
- unsigned long mirror;
- int r;
+ int mirror, r;
if (!dssdev->driver->set_mirror || !dssdev->driver->get_mirror)
return -ENOENT;
- mirror = simple_strtoul(buf, NULL, 0);
+ r = kstrtoint(buf, 0, &mirror);
+ if (r)
+ return r;
+
+ mirror = !!mirror;
r = dssdev->driver->set_mirror(dssdev, mirror);
if (r)
@@ -259,14 +272,15 @@
struct device_attribute *attr, const char *buf, size_t size)
{
struct omap_dss_device *dssdev = to_dss_device(dev);
- unsigned long wss;
+ u32 wss;
int r;
if (!dssdev->driver->get_wss || !dssdev->driver->set_wss)
return -ENOENT;
- if (strict_strtoul(buf, 0, &wss))
- return -EINVAL;
+ r = kstrtou32(buf, 0, &wss);
+ if (r)
+ return r;
if (wss > 0xfffff)
return -EINVAL;
diff --git a/drivers/video/omap2/dss/dpi.c b/drivers/video/omap2/dss/dpi.c
index 2d3ca4c..ff6bd30 100644
--- a/drivers/video/omap2/dss/dpi.c
+++ b/drivers/video/omap2/dss/dpi.c
@@ -30,16 +30,40 @@
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
-#include <plat/display.h>
+#include <video/omapdss.h>
#include <plat/cpu.h>
#include "dss.h"
static struct {
struct regulator *vdds_dsi_reg;
+ struct platform_device *dsidev;
} dpi;
-#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
+static struct platform_device *dpi_get_dsidev(enum omap_dss_clk_source clk)
+{
+ int dsi_module;
+
+ dsi_module = clk == OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC ? 0 : 1;
+
+ return dsi_get_dsidev_from_id(dsi_module);
+}
+
+static bool dpi_use_dsi_pll(struct omap_dss_device *dssdev)
+{
+ if (dssdev->clocks.dispc.dispc_fclk_src ==
+ OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC ||
+ dssdev->clocks.dispc.dispc_fclk_src ==
+ OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC ||
+ dssdev->clocks.dispc.channel.lcd_clk_src ==
+ OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC ||
+ dssdev->clocks.dispc.channel.lcd_clk_src ==
+ OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC)
+ return true;
+ else
+ return false;
+}
+
static int dpi_set_dsi_clk(struct omap_dss_device *dssdev, bool is_tft,
unsigned long pck_req, unsigned long *fck, int *lck_div,
int *pck_div)
@@ -48,16 +72,16 @@
struct dispc_clock_info dispc_cinfo;
int r;
- r = dsi_pll_calc_clock_div_pck(is_tft, pck_req, &dsi_cinfo,
- &dispc_cinfo);
+ r = dsi_pll_calc_clock_div_pck(dpi.dsidev, is_tft, pck_req,
+ &dsi_cinfo, &dispc_cinfo);
if (r)
return r;
- r = dsi_pll_set_clock_div(&dsi_cinfo);
+ r = dsi_pll_set_clock_div(dpi.dsidev, &dsi_cinfo);
if (r)
return r;
- dss_select_dispc_clk_source(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC);
+ dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src);
r = dispc_set_clock_div(dssdev->manager->id, &dispc_cinfo);
if (r)
@@ -69,7 +93,7 @@
return 0;
}
-#else
+
static int dpi_set_dispc_clk(struct omap_dss_device *dssdev, bool is_tft,
unsigned long pck_req, unsigned long *fck, int *lck_div,
int *pck_div)
@@ -96,13 +120,12 @@
return 0;
}
-#endif
static int dpi_set_mode(struct omap_dss_device *dssdev)
{
struct omap_video_timings *t = &dssdev->panel.timings;
- int lck_div, pck_div;
- unsigned long fck;
+ int lck_div = 0, pck_div = 0;
+ unsigned long fck = 0;
unsigned long pck;
bool is_tft;
int r = 0;
@@ -114,13 +137,12 @@
is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;
-#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
- r = dpi_set_dsi_clk(dssdev, is_tft, t->pixel_clock * 1000, &fck,
- &lck_div, &pck_div);
-#else
- r = dpi_set_dispc_clk(dssdev, is_tft, t->pixel_clock * 1000, &fck,
- &lck_div, &pck_div);
-#endif
+ if (dpi_use_dsi_pll(dssdev))
+ r = dpi_set_dsi_clk(dssdev, is_tft, t->pixel_clock * 1000,
+ &fck, &lck_div, &pck_div);
+ else
+ r = dpi_set_dispc_clk(dssdev, is_tft, t->pixel_clock * 1000,
+ &fck, &lck_div, &pck_div);
if (r)
goto err0;
@@ -179,12 +201,13 @@
if (r)
goto err2;
-#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
- dss_clk_enable(DSS_CLK_SYSCK);
- r = dsi_pll_init(dssdev, 0, 1);
- if (r)
- goto err3;
-#endif
+ if (dpi_use_dsi_pll(dssdev)) {
+ dss_clk_enable(DSS_CLK_SYSCK);
+ r = dsi_pll_init(dpi.dsidev, 0, 1);
+ if (r)
+ goto err3;
+ }
+
r = dpi_set_mode(dssdev);
if (r)
goto err4;
@@ -196,11 +219,11 @@
return 0;
err4:
-#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
- dsi_pll_uninit();
+ if (dpi_use_dsi_pll(dssdev))
+ dsi_pll_uninit(dpi.dsidev, true);
err3:
- dss_clk_disable(DSS_CLK_SYSCK);
-#endif
+ if (dpi_use_dsi_pll(dssdev))
+ dss_clk_disable(DSS_CLK_SYSCK);
err2:
dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
if (cpu_is_omap34xx())
@@ -216,11 +239,11 @@
{
dssdev->manager->disable(dssdev->manager);
-#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
- dss_select_dispc_clk_source(DSS_CLK_SRC_FCK);
- dsi_pll_uninit();
- dss_clk_disable(DSS_CLK_SYSCK);
-#endif
+ if (dpi_use_dsi_pll(dssdev)) {
+ dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
+ dsi_pll_uninit(dpi.dsidev, true);
+ dss_clk_disable(DSS_CLK_SYSCK);
+ }
dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
@@ -251,6 +274,7 @@
int lck_div, pck_div;
unsigned long fck;
unsigned long pck;
+ struct dispc_clock_info dispc_cinfo;
if (!dispc_lcd_timings_ok(timings))
return -EINVAL;
@@ -260,11 +284,9 @@
is_tft = (dssdev->panel.config & OMAP_DSS_LCD_TFT) != 0;
-#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
- {
+ if (dpi_use_dsi_pll(dssdev)) {
struct dsi_clock_info dsi_cinfo;
- struct dispc_clock_info dispc_cinfo;
- r = dsi_pll_calc_clock_div_pck(is_tft,
+ r = dsi_pll_calc_clock_div_pck(dpi.dsidev, is_tft,
timings->pixel_clock * 1000,
&dsi_cinfo, &dispc_cinfo);
@@ -272,13 +294,8 @@
return r;
fck = dsi_cinfo.dsi_pll_hsdiv_dispc_clk;
- lck_div = dispc_cinfo.lck_div;
- pck_div = dispc_cinfo.pck_div;
- }
-#else
- {
+ } else {
struct dss_clock_info dss_cinfo;
- struct dispc_clock_info dispc_cinfo;
r = dss_calc_clock_div(is_tft, timings->pixel_clock * 1000,
&dss_cinfo, &dispc_cinfo);
@@ -286,10 +303,10 @@
return r;
fck = dss_cinfo.fck;
- lck_div = dispc_cinfo.lck_div;
- pck_div = dispc_cinfo.pck_div;
}
-#endif
+
+ lck_div = dispc_cinfo.lck_div;
+ pck_div = dispc_cinfo.pck_div;
pck = fck / lck_div / pck_div / 1000;
@@ -316,6 +333,12 @@
dpi.vdds_dsi_reg = vdds_dsi;
}
+ if (dpi_use_dsi_pll(dssdev)) {
+ enum omap_dss_clk_source dispc_fclk_src =
+ dssdev->clocks.dispc.dispc_fclk_src;
+ dpi.dsidev = dpi_get_dsidev(dispc_fclk_src);
+ }
+
return 0;
}
diff --git a/drivers/video/omap2/dss/dsi.c b/drivers/video/omap2/dss/dsi.c
index 0a7f1a4..345757c 100644
--- a/drivers/video/omap2/dss/dsi.c
+++ b/drivers/video/omap2/dss/dsi.c
@@ -33,8 +33,11 @@
#include <linux/regulator/consumer.h>
#include <linux/wait.h>
#include <linux/workqueue.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/debugfs.h>
-#include <plat/display.h>
+#include <video/omapdss.h>
#include <plat/clock.h>
#include "dss.h"
@@ -56,6 +59,7 @@
#define DSI_IRQSTATUS DSI_REG(0x0018)
#define DSI_IRQENABLE DSI_REG(0x001C)
#define DSI_CTRL DSI_REG(0x0040)
+#define DSI_GNQ DSI_REG(0x0044)
#define DSI_COMPLEXIO_CFG1 DSI_REG(0x0048)
#define DSI_COMPLEXIO_IRQ_STATUS DSI_REG(0x004C)
#define DSI_COMPLEXIO_IRQ_ENABLE DSI_REG(0x0050)
@@ -90,6 +94,7 @@
#define DSI_DSIPHY_CFG1 DSI_REG(0x200 + 0x0004)
#define DSI_DSIPHY_CFG2 DSI_REG(0x200 + 0x0008)
#define DSI_DSIPHY_CFG5 DSI_REG(0x200 + 0x0014)
+#define DSI_DSIPHY_CFG10 DSI_REG(0x200 + 0x0028)
/* DSI_PLL_CTRL_SCP */
@@ -99,11 +104,11 @@
#define DSI_PLL_CONFIGURATION1 DSI_REG(0x300 + 0x000C)
#define DSI_PLL_CONFIGURATION2 DSI_REG(0x300 + 0x0010)
-#define REG_GET(idx, start, end) \
- FLD_GET(dsi_read_reg(idx), start, end)
+#define REG_GET(dsidev, idx, start, end) \
+ FLD_GET(dsi_read_reg(dsidev, idx), start, end)
-#define REG_FLD_MOD(idx, val, start, end) \
- dsi_write_reg(idx, FLD_MOD(dsi_read_reg(idx), val, start, end))
+#define REG_FLD_MOD(dsidev, idx, val, start, end) \
+ dsi_write_reg(dsidev, idx, FLD_MOD(dsi_read_reg(dsidev, idx), val, start, end))
/* Global interrupts */
#define DSI_IRQ_VC0 (1 << 0)
@@ -147,31 +152,50 @@
#define DSI_CIO_IRQ_ERRSYNCESC1 (1 << 0)
#define DSI_CIO_IRQ_ERRSYNCESC2 (1 << 1)
#define DSI_CIO_IRQ_ERRSYNCESC3 (1 << 2)
+#define DSI_CIO_IRQ_ERRSYNCESC4 (1 << 3)
+#define DSI_CIO_IRQ_ERRSYNCESC5 (1 << 4)
#define DSI_CIO_IRQ_ERRESC1 (1 << 5)
#define DSI_CIO_IRQ_ERRESC2 (1 << 6)
#define DSI_CIO_IRQ_ERRESC3 (1 << 7)
+#define DSI_CIO_IRQ_ERRESC4 (1 << 8)
+#define DSI_CIO_IRQ_ERRESC5 (1 << 9)
#define DSI_CIO_IRQ_ERRCONTROL1 (1 << 10)
#define DSI_CIO_IRQ_ERRCONTROL2 (1 << 11)
#define DSI_CIO_IRQ_ERRCONTROL3 (1 << 12)
+#define DSI_CIO_IRQ_ERRCONTROL4 (1 << 13)
+#define DSI_CIO_IRQ_ERRCONTROL5 (1 << 14)
#define DSI_CIO_IRQ_STATEULPS1 (1 << 15)
#define DSI_CIO_IRQ_STATEULPS2 (1 << 16)
#define DSI_CIO_IRQ_STATEULPS3 (1 << 17)
+#define DSI_CIO_IRQ_STATEULPS4 (1 << 18)
+#define DSI_CIO_IRQ_STATEULPS5 (1 << 19)
#define DSI_CIO_IRQ_ERRCONTENTIONLP0_1 (1 << 20)
#define DSI_CIO_IRQ_ERRCONTENTIONLP1_1 (1 << 21)
#define DSI_CIO_IRQ_ERRCONTENTIONLP0_2 (1 << 22)
#define DSI_CIO_IRQ_ERRCONTENTIONLP1_2 (1 << 23)
#define DSI_CIO_IRQ_ERRCONTENTIONLP0_3 (1 << 24)
#define DSI_CIO_IRQ_ERRCONTENTIONLP1_3 (1 << 25)
+#define DSI_CIO_IRQ_ERRCONTENTIONLP0_4 (1 << 26)
+#define DSI_CIO_IRQ_ERRCONTENTIONLP1_4 (1 << 27)
+#define DSI_CIO_IRQ_ERRCONTENTIONLP0_5 (1 << 28)
+#define DSI_CIO_IRQ_ERRCONTENTIONLP1_5 (1 << 29)
#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL0 (1 << 30)
#define DSI_CIO_IRQ_ULPSACTIVENOT_ALL1 (1 << 31)
#define DSI_CIO_IRQ_ERROR_MASK \
(DSI_CIO_IRQ_ERRSYNCESC1 | DSI_CIO_IRQ_ERRSYNCESC2 | \
- DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \
- DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRCONTROL1 | \
- DSI_CIO_IRQ_ERRCONTROL2 | DSI_CIO_IRQ_ERRCONTROL3 | \
+ DSI_CIO_IRQ_ERRSYNCESC3 | DSI_CIO_IRQ_ERRSYNCESC4 | \
+ DSI_CIO_IRQ_ERRSYNCESC5 | \
+ DSI_CIO_IRQ_ERRESC1 | DSI_CIO_IRQ_ERRESC2 | \
+ DSI_CIO_IRQ_ERRESC3 | DSI_CIO_IRQ_ERRESC4 | \
+ DSI_CIO_IRQ_ERRESC5 | \
+ DSI_CIO_IRQ_ERRCONTROL1 | DSI_CIO_IRQ_ERRCONTROL2 | \
+ DSI_CIO_IRQ_ERRCONTROL3 | DSI_CIO_IRQ_ERRCONTROL4 | \
+ DSI_CIO_IRQ_ERRCONTROL5 | \
DSI_CIO_IRQ_ERRCONTENTIONLP0_1 | DSI_CIO_IRQ_ERRCONTENTIONLP1_1 | \
DSI_CIO_IRQ_ERRCONTENTIONLP0_2 | DSI_CIO_IRQ_ERRCONTENTIONLP1_2 | \
- DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3)
+ DSI_CIO_IRQ_ERRCONTENTIONLP0_3 | DSI_CIO_IRQ_ERRCONTENTIONLP1_3 | \
+ DSI_CIO_IRQ_ERRCONTENTIONLP0_4 | DSI_CIO_IRQ_ERRCONTENTIONLP1_4 | \
+ DSI_CIO_IRQ_ERRCONTENTIONLP0_5 | DSI_CIO_IRQ_ERRCONTENTIONLP1_5)
#define DSI_DT_DCS_SHORT_WRITE_0 0x05
#define DSI_DT_DCS_SHORT_WRITE_1 0x15
@@ -208,6 +232,19 @@
DSI_VC_MODE_VP,
};
+enum dsi_lane {
+ DSI_CLK_P = 1 << 0,
+ DSI_CLK_N = 1 << 1,
+ DSI_DATA1_P = 1 << 2,
+ DSI_DATA1_N = 1 << 3,
+ DSI_DATA2_P = 1 << 4,
+ DSI_DATA2_N = 1 << 5,
+ DSI_DATA3_P = 1 << 6,
+ DSI_DATA3_N = 1 << 7,
+ DSI_DATA4_P = 1 << 8,
+ DSI_DATA4_N = 1 << 9,
+};
+
struct dsi_update_region {
u16 x, y, w, h;
struct omap_dss_device *device;
@@ -227,14 +264,16 @@
struct dsi_isr_data isr_table_cio[DSI_MAX_NR_ISRS];
};
-static struct
-{
+struct dsi_data {
struct platform_device *pdev;
void __iomem *base;
int irq;
+ void (*dsi_mux_pads)(bool enable);
+
struct dsi_clock_info current_cinfo;
+ bool vdds_dsi_enabled;
struct regulator *vdds_dsi_reg;
struct {
@@ -258,8 +297,7 @@
struct dsi_update_region update_region;
bool te_enabled;
-
- struct workqueue_struct *workqueue;
+ bool ulps_enabled;
void (*framedone_callback)(int, void *);
void *framedone_data;
@@ -292,21 +330,63 @@
unsigned long regm_dispc_max, regm_dsi_max;
unsigned long fint_min, fint_max;
unsigned long lpdiv_max;
-} dsi;
+
+ int num_data_lanes;
+
+ unsigned scp_clk_refcount;
+};
+
+struct dsi_packet_sent_handler_data {
+ struct platform_device *dsidev;
+ struct completion *completion;
+};
+
+static struct platform_device *dsi_pdev_map[MAX_NUM_DSI];
#ifdef DEBUG
static unsigned int dsi_perf;
module_param_named(dsi_perf, dsi_perf, bool, 0644);
#endif
-static inline void dsi_write_reg(const struct dsi_reg idx, u32 val)
+static inline struct dsi_data *dsi_get_dsidrv_data(struct platform_device *dsidev)
{
- __raw_writel(val, dsi.base + idx.idx);
+ return dev_get_drvdata(&dsidev->dev);
}
-static inline u32 dsi_read_reg(const struct dsi_reg idx)
+static inline struct platform_device *dsi_get_dsidev_from_dssdev(struct omap_dss_device *dssdev)
{
- return __raw_readl(dsi.base + idx.idx);
+ return dsi_pdev_map[dssdev->phy.dsi.module];
+}
+
+struct platform_device *dsi_get_dsidev_from_id(int module)
+{
+ return dsi_pdev_map[module];
+}
+
+static int dsi_get_dsidev_id(struct platform_device *dsidev)
+{
+ /* TEMP: Pass 0 as the dsi module index till the time the dsi platform
+ * device names aren't changed to the form "omapdss_dsi.0",
+ * "omapdss_dsi.1" and so on */
+ BUG_ON(dsidev->id != -1);
+
+ return 0;
+}
+
+static inline void dsi_write_reg(struct platform_device *dsidev,
+ const struct dsi_reg idx, u32 val)
+{
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
+
+ __raw_writel(val, dsi->base + idx.idx);
+}
+
+static inline u32 dsi_read_reg(struct platform_device *dsidev,
+ const struct dsi_reg idx)
+{
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
+
+ return __raw_readl(dsi->base + idx.idx);
}
@@ -318,21 +398,29 @@
{
}
-void dsi_bus_lock(void)
+void dsi_bus_lock(struct omap_dss_device *dssdev)
{
- down(&dsi.bus_lock);
+ struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
+
+ down(&dsi->bus_lock);
}
EXPORT_SYMBOL(dsi_bus_lock);
-void dsi_bus_unlock(void)
+void dsi_bus_unlock(struct omap_dss_device *dssdev)
{
- up(&dsi.bus_lock);
+ struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
+
+ up(&dsi->bus_lock);
}
EXPORT_SYMBOL(dsi_bus_unlock);
-static bool dsi_bus_is_locked(void)
+static bool dsi_bus_is_locked(struct platform_device *dsidev)
{
- return dsi.bus_lock.count == 0;
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
+
+ return dsi->bus_lock.count == 0;
}
static void dsi_completion_handler(void *data, u32 mask)
@@ -340,12 +428,12 @@
complete((struct completion *)data);
}
-static inline int wait_for_bit_change(const struct dsi_reg idx, int bitnum,
- int value)
+static inline int wait_for_bit_change(struct platform_device *dsidev,
+ const struct dsi_reg idx, int bitnum, int value)
{
int t = 100000;
- while (REG_GET(idx, bitnum, bitnum) != value) {
+ while (REG_GET(dsidev, idx, bitnum, bitnum) != value) {
if (--t == 0)
return !value;
}
@@ -354,18 +442,21 @@
}
#ifdef DEBUG
-static void dsi_perf_mark_setup(void)
+static void dsi_perf_mark_setup(struct platform_device *dsidev)
{
- dsi.perf_setup_time = ktime_get();
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
+ dsi->perf_setup_time = ktime_get();
}
-static void dsi_perf_mark_start(void)
+static void dsi_perf_mark_start(struct platform_device *dsidev)
{
- dsi.perf_start_time = ktime_get();
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
+ dsi->perf_start_time = ktime_get();
}
-static void dsi_perf_show(const char *name)
+static void dsi_perf_show(struct platform_device *dsidev, const char *name)
{
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
ktime_t t, setup_time, trans_time;
u32 total_bytes;
u32 setup_us, trans_us, total_us;
@@ -375,21 +466,21 @@
t = ktime_get();
- setup_time = ktime_sub(dsi.perf_start_time, dsi.perf_setup_time);
+ setup_time = ktime_sub(dsi->perf_start_time, dsi->perf_setup_time);
setup_us = (u32)ktime_to_us(setup_time);
if (setup_us == 0)
setup_us = 1;
- trans_time = ktime_sub(t, dsi.perf_start_time);
+ trans_time = ktime_sub(t, dsi->perf_start_time);
trans_us = (u32)ktime_to_us(trans_time);
if (trans_us == 0)
trans_us = 1;
total_us = setup_us + trans_us;
- total_bytes = dsi.update_region.w *
- dsi.update_region.h *
- dsi.update_region.device->ctrl.pixel_size / 8;
+ total_bytes = dsi->update_region.w *
+ dsi->update_region.h *
+ dsi->update_region.device->ctrl.pixel_size / 8;
printk(KERN_INFO "DSI(%s): %u us + %u us = %u us (%uHz), "
"%u bytes, %u kbytes/sec\n",
@@ -402,9 +493,9 @@
total_bytes * 1000 / total_us);
}
#else
-#define dsi_perf_mark_setup()
-#define dsi_perf_mark_start()
-#define dsi_perf_show(x)
+#define dsi_perf_mark_setup(x)
+#define dsi_perf_mark_start(x)
+#define dsi_perf_show(x, y)
#endif
static void print_irq_status(u32 status)
@@ -510,38 +601,42 @@
}
#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
-static void dsi_collect_irq_stats(u32 irqstatus, u32 *vcstatus, u32 ciostatus)
+static void dsi_collect_irq_stats(struct platform_device *dsidev, u32 irqstatus,
+ u32 *vcstatus, u32 ciostatus)
{
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
int i;
- spin_lock(&dsi.irq_stats_lock);
+ spin_lock(&dsi->irq_stats_lock);
- dsi.irq_stats.irq_count++;
- dss_collect_irq_stats(irqstatus, dsi.irq_stats.dsi_irqs);
+ dsi->irq_stats.irq_count++;
+ dss_collect_irq_stats(irqstatus, dsi->irq_stats.dsi_irqs);
for (i = 0; i < 4; ++i)
- dss_collect_irq_stats(vcstatus[i], dsi.irq_stats.vc_irqs[i]);
+ dss_collect_irq_stats(vcstatus[i], dsi->irq_stats.vc_irqs[i]);
- dss_collect_irq_stats(ciostatus, dsi.irq_stats.cio_irqs);
+ dss_collect_irq_stats(ciostatus, dsi->irq_stats.cio_irqs);
- spin_unlock(&dsi.irq_stats_lock);
+ spin_unlock(&dsi->irq_stats_lock);
}
#else
-#define dsi_collect_irq_stats(irqstatus, vcstatus, ciostatus)
+#define dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus)
#endif
static int debug_irq;
-static void dsi_handle_irq_errors(u32 irqstatus, u32 *vcstatus, u32 ciostatus)
+static void dsi_handle_irq_errors(struct platform_device *dsidev, u32 irqstatus,
+ u32 *vcstatus, u32 ciostatus)
{
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
int i;
if (irqstatus & DSI_IRQ_ERROR_MASK) {
DSSERR("DSI error, irqstatus %x\n", irqstatus);
print_irq_status(irqstatus);
- spin_lock(&dsi.errors_lock);
- dsi.errors |= irqstatus & DSI_IRQ_ERROR_MASK;
- spin_unlock(&dsi.errors_lock);
+ spin_lock(&dsi->errors_lock);
+ dsi->errors |= irqstatus & DSI_IRQ_ERROR_MASK;
+ spin_unlock(&dsi->errors_lock);
} else if (debug_irq) {
print_irq_status(irqstatus);
}
@@ -602,22 +697,27 @@
static irqreturn_t omap_dsi_irq_handler(int irq, void *arg)
{
+ struct platform_device *dsidev;
+ struct dsi_data *dsi;
u32 irqstatus, vcstatus[4], ciostatus;
int i;
- spin_lock(&dsi.irq_lock);
+ dsidev = (struct platform_device *) arg;
+ dsi = dsi_get_dsidrv_data(dsidev);
- irqstatus = dsi_read_reg(DSI_IRQSTATUS);
+ spin_lock(&dsi->irq_lock);
+
+ irqstatus = dsi_read_reg(dsidev, DSI_IRQSTATUS);
/* IRQ is not for us */
if (!irqstatus) {
- spin_unlock(&dsi.irq_lock);
+ spin_unlock(&dsi->irq_lock);
return IRQ_NONE;
}
- dsi_write_reg(DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
+ dsi_write_reg(dsidev, DSI_IRQSTATUS, irqstatus & ~DSI_IRQ_CHANNEL_MASK);
/* flush posted write */
- dsi_read_reg(DSI_IRQSTATUS);
+ dsi_read_reg(dsidev, DSI_IRQSTATUS);
for (i = 0; i < 4; ++i) {
if ((irqstatus & (1 << i)) == 0) {
@@ -625,45 +725,47 @@
continue;
}
- vcstatus[i] = dsi_read_reg(DSI_VC_IRQSTATUS(i));
+ vcstatus[i] = dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
- dsi_write_reg(DSI_VC_IRQSTATUS(i), vcstatus[i]);
+ dsi_write_reg(dsidev, DSI_VC_IRQSTATUS(i), vcstatus[i]);
/* flush posted write */
- dsi_read_reg(DSI_VC_IRQSTATUS(i));
+ dsi_read_reg(dsidev, DSI_VC_IRQSTATUS(i));
}
if (irqstatus & DSI_IRQ_COMPLEXIO_ERR) {
- ciostatus = dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
+ ciostatus = dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
- dsi_write_reg(DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
+ dsi_write_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS, ciostatus);
/* flush posted write */
- dsi_read_reg(DSI_COMPLEXIO_IRQ_STATUS);
+ dsi_read_reg(dsidev, DSI_COMPLEXIO_IRQ_STATUS);
} else {
ciostatus = 0;
}
#ifdef DSI_CATCH_MISSING_TE
if (irqstatus & DSI_IRQ_TE_TRIGGER)
- del_timer(&dsi.te_timer);
+ del_timer(&dsi->te_timer);
#endif
/* make a copy and unlock, so that isrs can unregister
* themselves */
- memcpy(&dsi.isr_tables_copy, &dsi.isr_tables, sizeof(dsi.isr_tables));
+ memcpy(&dsi->isr_tables_copy, &dsi->isr_tables,
+ sizeof(dsi->isr_tables));
- spin_unlock(&dsi.irq_lock);
+ spin_unlock(&dsi->irq_lock);
- dsi_handle_isrs(&dsi.isr_tables_copy, irqstatus, vcstatus, ciostatus);
+ dsi_handle_isrs(&dsi->isr_tables_copy, irqstatus, vcstatus, ciostatus);
- dsi_handle_irq_errors(irqstatus, vcstatus, ciostatus);
+ dsi_handle_irq_errors(dsidev, irqstatus, vcstatus, ciostatus);
- dsi_collect_irq_stats(irqstatus, vcstatus, ciostatus);
+ dsi_collect_irq_stats(dsidev, irqstatus, vcstatus, ciostatus);
return IRQ_HANDLED;
}
-/* dsi.irq_lock has to be locked by the caller */
-static void _omap_dsi_configure_irqs(struct dsi_isr_data *isr_array,
+/* dsi->irq_lock has to be locked by the caller */
+static void _omap_dsi_configure_irqs(struct platform_device *dsidev,
+ struct dsi_isr_data *isr_array,
unsigned isr_array_size, u32 default_mask,
const struct dsi_reg enable_reg,
const struct dsi_reg status_reg)
@@ -684,61 +786,67 @@
mask |= isr_data->mask;
}
- old_mask = dsi_read_reg(enable_reg);
+ old_mask = dsi_read_reg(dsidev, enable_reg);
/* clear the irqstatus for newly enabled irqs */
- dsi_write_reg(status_reg, (mask ^ old_mask) & mask);
- dsi_write_reg(enable_reg, mask);
+ dsi_write_reg(dsidev, status_reg, (mask ^ old_mask) & mask);
+ dsi_write_reg(dsidev, enable_reg, mask);
/* flush posted writes */
- dsi_read_reg(enable_reg);
- dsi_read_reg(status_reg);
+ dsi_read_reg(dsidev, enable_reg);
+ dsi_read_reg(dsidev, status_reg);
}
-/* dsi.irq_lock has to be locked by the caller */
-static void _omap_dsi_set_irqs(void)
+/* dsi->irq_lock has to be locked by the caller */
+static void _omap_dsi_set_irqs(struct platform_device *dsidev)
{
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
u32 mask = DSI_IRQ_ERROR_MASK;
#ifdef DSI_CATCH_MISSING_TE
mask |= DSI_IRQ_TE_TRIGGER;
#endif
- _omap_dsi_configure_irqs(dsi.isr_tables.isr_table,
- ARRAY_SIZE(dsi.isr_tables.isr_table), mask,
+ _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table,
+ ARRAY_SIZE(dsi->isr_tables.isr_table), mask,
DSI_IRQENABLE, DSI_IRQSTATUS);
}
-/* dsi.irq_lock has to be locked by the caller */
-static void _omap_dsi_set_irqs_vc(int vc)
+/* dsi->irq_lock has to be locked by the caller */
+static void _omap_dsi_set_irqs_vc(struct platform_device *dsidev, int vc)
{
- _omap_dsi_configure_irqs(dsi.isr_tables.isr_table_vc[vc],
- ARRAY_SIZE(dsi.isr_tables.isr_table_vc[vc]),
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
+
+ _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_vc[vc],
+ ARRAY_SIZE(dsi->isr_tables.isr_table_vc[vc]),
DSI_VC_IRQ_ERROR_MASK,
DSI_VC_IRQENABLE(vc), DSI_VC_IRQSTATUS(vc));
}
-/* dsi.irq_lock has to be locked by the caller */
-static void _omap_dsi_set_irqs_cio(void)
+/* dsi->irq_lock has to be locked by the caller */
+static void _omap_dsi_set_irqs_cio(struct platform_device *dsidev)
{
- _omap_dsi_configure_irqs(dsi.isr_tables.isr_table_cio,
- ARRAY_SIZE(dsi.isr_tables.isr_table_cio),
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
+
+ _omap_dsi_configure_irqs(dsidev, dsi->isr_tables.isr_table_cio,
+ ARRAY_SIZE(dsi->isr_tables.isr_table_cio),
DSI_CIO_IRQ_ERROR_MASK,
DSI_COMPLEXIO_IRQ_ENABLE, DSI_COMPLEXIO_IRQ_STATUS);
}
-static void _dsi_initialize_irq(void)
+static void _dsi_initialize_irq(struct platform_device *dsidev)
{
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
unsigned long flags;
int vc;
- spin_lock_irqsave(&dsi.irq_lock, flags);
+ spin_lock_irqsave(&dsi->irq_lock, flags);
- memset(&dsi.isr_tables, 0, sizeof(dsi.isr_tables));
+ memset(&dsi->isr_tables, 0, sizeof(dsi->isr_tables));
- _omap_dsi_set_irqs();
+ _omap_dsi_set_irqs(dsidev);
for (vc = 0; vc < 4; ++vc)
- _omap_dsi_set_irqs_vc(vc);
- _omap_dsi_set_irqs_cio();
+ _omap_dsi_set_irqs_vc(dsidev, vc);
+ _omap_dsi_set_irqs_cio(dsidev);
- spin_unlock_irqrestore(&dsi.irq_lock, flags);
+ spin_unlock_irqrestore(&dsi->irq_lock, flags);
}
static int _dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask,
@@ -797,126 +905,137 @@
return -EINVAL;
}
-static int dsi_register_isr(omap_dsi_isr_t isr, void *arg, u32 mask)
+static int dsi_register_isr(struct platform_device *dsidev, omap_dsi_isr_t isr,
+ void *arg, u32 mask)
{
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
unsigned long flags;
int r;
- spin_lock_irqsave(&dsi.irq_lock, flags);
+ spin_lock_irqsave(&dsi->irq_lock, flags);
- r = _dsi_register_isr(isr, arg, mask, dsi.isr_tables.isr_table,
- ARRAY_SIZE(dsi.isr_tables.isr_table));
+ r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table,
+ ARRAY_SIZE(dsi->isr_tables.isr_table));
if (r == 0)
- _omap_dsi_set_irqs();
+ _omap_dsi_set_irqs(dsidev);
- spin_unlock_irqrestore(&dsi.irq_lock, flags);
+ spin_unlock_irqrestore(&dsi->irq_lock, flags);
return r;
}
-static int dsi_unregister_isr(omap_dsi_isr_t isr, void *arg, u32 mask)
+static int dsi_unregister_isr(struct platform_device *dsidev,
+ omap_dsi_isr_t isr, void *arg, u32 mask)
{
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
unsigned long flags;
int r;
- spin_lock_irqsave(&dsi.irq_lock, flags);
+ spin_lock_irqsave(&dsi->irq_lock, flags);
- r = _dsi_unregister_isr(isr, arg, mask, dsi.isr_tables.isr_table,
- ARRAY_SIZE(dsi.isr_tables.isr_table));
+ r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table,
+ ARRAY_SIZE(dsi->isr_tables.isr_table));
if (r == 0)
- _omap_dsi_set_irqs();
+ _omap_dsi_set_irqs(dsidev);
- spin_unlock_irqrestore(&dsi.irq_lock, flags);
+ spin_unlock_irqrestore(&dsi->irq_lock, flags);
return r;
}
-static int dsi_register_isr_vc(int channel, omap_dsi_isr_t isr, void *arg,
- u32 mask)
+static int dsi_register_isr_vc(struct platform_device *dsidev, int channel,
+ omap_dsi_isr_t isr, void *arg, u32 mask)
{
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
unsigned long flags;
int r;
- spin_lock_irqsave(&dsi.irq_lock, flags);
+ spin_lock_irqsave(&dsi->irq_lock, flags);
r = _dsi_register_isr(isr, arg, mask,
- dsi.isr_tables.isr_table_vc[channel],
- ARRAY_SIZE(dsi.isr_tables.isr_table_vc[channel]));
+ dsi->isr_tables.isr_table_vc[channel],
+ ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
if (r == 0)
- _omap_dsi_set_irqs_vc(channel);
+ _omap_dsi_set_irqs_vc(dsidev, channel);
- spin_unlock_irqrestore(&dsi.irq_lock, flags);
+ spin_unlock_irqrestore(&dsi->irq_lock, flags);
return r;
}
-static int dsi_unregister_isr_vc(int channel, omap_dsi_isr_t isr, void *arg,
- u32 mask)
+static int dsi_unregister_isr_vc(struct platform_device *dsidev, int channel,
+ omap_dsi_isr_t isr, void *arg, u32 mask)
{
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
unsigned long flags;
int r;
- spin_lock_irqsave(&dsi.irq_lock, flags);
+ spin_lock_irqsave(&dsi->irq_lock, flags);
r = _dsi_unregister_isr(isr, arg, mask,
- dsi.isr_tables.isr_table_vc[channel],
- ARRAY_SIZE(dsi.isr_tables.isr_table_vc[channel]));
+ dsi->isr_tables.isr_table_vc[channel],
+ ARRAY_SIZE(dsi->isr_tables.isr_table_vc[channel]));
if (r == 0)
- _omap_dsi_set_irqs_vc(channel);
+ _omap_dsi_set_irqs_vc(dsidev, channel);
- spin_unlock_irqrestore(&dsi.irq_lock, flags);
+ spin_unlock_irqrestore(&dsi->irq_lock, flags);
return r;
}
-static int dsi_register_isr_cio(omap_dsi_isr_t isr, void *arg, u32 mask)
+static int dsi_register_isr_cio(struct platform_device *dsidev,
+ omap_dsi_isr_t isr, void *arg, u32 mask)
{
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
unsigned long flags;
int r;
- spin_lock_irqsave(&dsi.irq_lock, flags);
+ spin_lock_irqsave(&dsi->irq_lock, flags);
- r = _dsi_register_isr(isr, arg, mask, dsi.isr_tables.isr_table_cio,
- ARRAY_SIZE(dsi.isr_tables.isr_table_cio));
+ r = _dsi_register_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
+ ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
if (r == 0)
- _omap_dsi_set_irqs_cio();
+ _omap_dsi_set_irqs_cio(dsidev);
- spin_unlock_irqrestore(&dsi.irq_lock, flags);
+ spin_unlock_irqrestore(&dsi->irq_lock, flags);
return r;
}
-static int dsi_unregister_isr_cio(omap_dsi_isr_t isr, void *arg, u32 mask)
+static int dsi_unregister_isr_cio(struct platform_device *dsidev,
+ omap_dsi_isr_t isr, void *arg, u32 mask)
{
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
unsigned long flags;
int r;
- spin_lock_irqsave(&dsi.irq_lock, flags);
+ spin_lock_irqsave(&dsi->irq_lock, flags);
- r = _dsi_unregister_isr(isr, arg, mask, dsi.isr_tables.isr_table_cio,
- ARRAY_SIZE(dsi.isr_tables.isr_table_cio));
+ r = _dsi_unregister_isr(isr, arg, mask, dsi->isr_tables.isr_table_cio,
+ ARRAY_SIZE(dsi->isr_tables.isr_table_cio));
if (r == 0)
- _omap_dsi_set_irqs_cio();
+ _omap_dsi_set_irqs_cio(dsidev);
- spin_unlock_irqrestore(&dsi.irq_lock, flags);
+ spin_unlock_irqrestore(&dsi->irq_lock, flags);
return r;
}
-static u32 dsi_get_errors(void)
+static u32 dsi_get_errors(struct platform_device *dsidev)
{
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
unsigned long flags;
u32 e;
- spin_lock_irqsave(&dsi.errors_lock, flags);
- e = dsi.errors;
- dsi.errors = 0;
- spin_unlock_irqrestore(&dsi.errors_lock, flags);
+ spin_lock_irqsave(&dsi->errors_lock, flags);
+ e = dsi->errors;
+ dsi->errors = 0;
+ spin_unlock_irqrestore(&dsi->errors_lock, flags);
return e;
}
@@ -930,23 +1049,27 @@
}
/* source clock for DSI PLL. this could also be PCLKFREE */
-static inline void dsi_enable_pll_clock(bool enable)
+static inline void dsi_enable_pll_clock(struct platform_device *dsidev,
+ bool enable)
{
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
+
if (enable)
dss_clk_enable(DSS_CLK_SYSCK);
else
dss_clk_disable(DSS_CLK_SYSCK);
- if (enable && dsi.pll_locked) {
- if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1)
+ if (enable && dsi->pll_locked) {
+ if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1)
DSSERR("cannot lock PLL when enabling clocks\n");
}
}
#ifdef DEBUG
-static void _dsi_print_reset_status(void)
+static void _dsi_print_reset_status(struct platform_device *dsidev)
{
u32 l;
+ int b0, b1, b2;
if (!dss_debug)
return;
@@ -954,35 +1077,47 @@
/* A dummy read using the SCP interface to any DSIPHY register is
* required after DSIPHY reset to complete the reset of the DSI complex
* I/O. */
- l = dsi_read_reg(DSI_DSIPHY_CFG5);
+ l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
printk(KERN_DEBUG "DSI resets: ");
- l = dsi_read_reg(DSI_PLL_STATUS);
+ l = dsi_read_reg(dsidev, DSI_PLL_STATUS);
printk("PLL (%d) ", FLD_GET(l, 0, 0));
- l = dsi_read_reg(DSI_COMPLEXIO_CFG1);
+ l = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1);
printk("CIO (%d) ", FLD_GET(l, 29, 29));
- l = dsi_read_reg(DSI_DSIPHY_CFG5);
- printk("PHY (%x, %d, %d, %d)\n",
- FLD_GET(l, 28, 26),
+ if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) {
+ b0 = 28;
+ b1 = 27;
+ b2 = 26;
+ } else {
+ b0 = 24;
+ b1 = 25;
+ b2 = 26;
+ }
+
+ l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
+ printk("PHY (%x%x%x, %d, %d, %d)\n",
+ FLD_GET(l, b0, b0),
+ FLD_GET(l, b1, b1),
+ FLD_GET(l, b2, b2),
FLD_GET(l, 29, 29),
FLD_GET(l, 30, 30),
FLD_GET(l, 31, 31));
}
#else
-#define _dsi_print_reset_status()
+#define _dsi_print_reset_status(x)
#endif
-static inline int dsi_if_enable(bool enable)
+static inline int dsi_if_enable(struct platform_device *dsidev, bool enable)
{
DSSDBG("dsi_if_enable(%d)\n", enable);
enable = enable ? 1 : 0;
- REG_FLD_MOD(DSI_CTRL, enable, 0, 0); /* IF_EN */
+ REG_FLD_MOD(dsidev, DSI_CTRL, enable, 0, 0); /* IF_EN */
- if (wait_for_bit_change(DSI_CTRL, 0, enable) != enable) {
+ if (wait_for_bit_change(dsidev, DSI_CTRL, 0, enable) != enable) {
DSSERR("Failed to set dsi_if_enable to %d\n", enable);
return -EIO;
}
@@ -990,31 +1125,38 @@
return 0;
}
-unsigned long dsi_get_pll_hsdiv_dispc_rate(void)
+unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev)
{
- return dsi.current_cinfo.dsi_pll_hsdiv_dispc_clk;
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
+
+ return dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk;
}
-static unsigned long dsi_get_pll_hsdiv_dsi_rate(void)
+static unsigned long dsi_get_pll_hsdiv_dsi_rate(struct platform_device *dsidev)
{
- return dsi.current_cinfo.dsi_pll_hsdiv_dsi_clk;
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
+
+ return dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk;
}
-static unsigned long dsi_get_txbyteclkhs(void)
+static unsigned long dsi_get_txbyteclkhs(struct platform_device *dsidev)
{
- return dsi.current_cinfo.clkin4ddr / 16;
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
+
+ return dsi->current_cinfo.clkin4ddr / 16;
}
-static unsigned long dsi_fclk_rate(void)
+static unsigned long dsi_fclk_rate(struct platform_device *dsidev)
{
unsigned long r;
+ int dsi_module = dsi_get_dsidev_id(dsidev);
- if (dss_get_dsi_clk_source() == DSS_CLK_SRC_FCK) {
+ if (dss_get_dsi_clk_source(dsi_module) == OMAP_DSS_CLK_SRC_FCK) {
/* DSI FCLK source is DSS_CLK_FCK */
r = dss_clk_get_rate(DSS_CLK_FCK);
} else {
/* DSI FCLK source is dsi_pll_hsdiv_dsi_clk */
- r = dsi_get_pll_hsdiv_dsi_rate();
+ r = dsi_get_pll_hsdiv_dsi_rate(dsidev);
}
return r;
@@ -1022,31 +1164,50 @@
static int dsi_set_lp_clk_divisor(struct omap_dss_device *dssdev)
{
+ struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
unsigned long dsi_fclk;
unsigned lp_clk_div;
unsigned long lp_clk;
- lp_clk_div = dssdev->phy.dsi.div.lp_clk_div;
+ lp_clk_div = dssdev->clocks.dsi.lp_clk_div;
- if (lp_clk_div == 0 || lp_clk_div > dsi.lpdiv_max)
+ if (lp_clk_div == 0 || lp_clk_div > dsi->lpdiv_max)
return -EINVAL;
- dsi_fclk = dsi_fclk_rate();
+ dsi_fclk = dsi_fclk_rate(dsidev);
lp_clk = dsi_fclk / 2 / lp_clk_div;
DSSDBG("LP_CLK_DIV %u, LP_CLK %lu\n", lp_clk_div, lp_clk);
- dsi.current_cinfo.lp_clk = lp_clk;
- dsi.current_cinfo.lp_clk_div = lp_clk_div;
+ dsi->current_cinfo.lp_clk = lp_clk;
+ dsi->current_cinfo.lp_clk_div = lp_clk_div;
- REG_FLD_MOD(DSI_CLK_CTRL, lp_clk_div, 12, 0); /* LP_CLK_DIVISOR */
+ /* LP_CLK_DIVISOR */
+ REG_FLD_MOD(dsidev, DSI_CLK_CTRL, lp_clk_div, 12, 0);
- REG_FLD_MOD(DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0,
- 21, 21); /* LP_RX_SYNCHRO_ENABLE */
+ /* LP_RX_SYNCHRO_ENABLE */
+ REG_FLD_MOD(dsidev, DSI_CLK_CTRL, dsi_fclk > 30000000 ? 1 : 0, 21, 21);
return 0;
}
+static void dsi_enable_scp_clk(struct platform_device *dsidev)
+{
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
+
+ if (dsi->scp_clk_refcount++ == 0)
+ REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 14, 14); /* CIO_CLK_ICG */
+}
+
+static void dsi_disable_scp_clk(struct platform_device *dsidev)
+{
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
+
+ WARN_ON(dsi->scp_clk_refcount == 0);
+ if (--dsi->scp_clk_refcount == 0)
+ REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 14, 14); /* CIO_CLK_ICG */
+}
enum dsi_pll_power_state {
DSI_PLL_POWER_OFF = 0x0,
@@ -1055,14 +1216,21 @@
DSI_PLL_POWER_ON_DIV = 0x3,
};
-static int dsi_pll_power(enum dsi_pll_power_state state)
+static int dsi_pll_power(struct platform_device *dsidev,
+ enum dsi_pll_power_state state)
{
int t = 0;
- REG_FLD_MOD(DSI_CLK_CTRL, state, 31, 30); /* PLL_PWR_CMD */
+ /* DSI-PLL power command 0x3 is not working */
+ if (dss_has_feature(FEAT_DSI_PLL_PWR_BUG) &&
+ state == DSI_PLL_POWER_ON_DIV)
+ state = DSI_PLL_POWER_ON_ALL;
+
+ /* PLL_PWR_CMD */
+ REG_FLD_MOD(dsidev, DSI_CLK_CTRL, state, 31, 30);
/* PLL_PWR_STATUS */
- while (FLD_GET(dsi_read_reg(DSI_CLK_CTRL), 29, 28) != state) {
+ while (FLD_GET(dsi_read_reg(dsidev, DSI_CLK_CTRL), 29, 28) != state) {
if (++t > 1000) {
DSSERR("Failed to set DSI PLL power mode to %d\n",
state);
@@ -1078,16 +1246,19 @@
static int dsi_calc_clock_rates(struct omap_dss_device *dssdev,
struct dsi_clock_info *cinfo)
{
- if (cinfo->regn == 0 || cinfo->regn > dsi.regn_max)
+ struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
+
+ if (cinfo->regn == 0 || cinfo->regn > dsi->regn_max)
return -EINVAL;
- if (cinfo->regm == 0 || cinfo->regm > dsi.regm_max)
+ if (cinfo->regm == 0 || cinfo->regm > dsi->regm_max)
return -EINVAL;
- if (cinfo->regm_dispc > dsi.regm_dispc_max)
+ if (cinfo->regm_dispc > dsi->regm_dispc_max)
return -EINVAL;
- if (cinfo->regm_dsi > dsi.regm_dsi_max)
+ if (cinfo->regm_dsi > dsi->regm_dsi_max)
return -EINVAL;
if (cinfo->use_sys_clk) {
@@ -1106,7 +1277,7 @@
cinfo->fint = cinfo->clkin / (cinfo->regn * (cinfo->highfreq ? 2 : 1));
- if (cinfo->fint > dsi.fint_max || cinfo->fint < dsi.fint_min)
+ if (cinfo->fint > dsi->fint_max || cinfo->fint < dsi->fint_min)
return -EINVAL;
cinfo->clkin4ddr = 2 * cinfo->regm * cinfo->fint;
@@ -1129,10 +1300,11 @@
return 0;
}
-int dsi_pll_calc_clock_div_pck(bool is_tft, unsigned long req_pck,
- struct dsi_clock_info *dsi_cinfo,
+int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev, bool is_tft,
+ unsigned long req_pck, struct dsi_clock_info *dsi_cinfo,
struct dispc_clock_info *dispc_cinfo)
{
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
struct dsi_clock_info cur, best;
struct dispc_clock_info best_dispc;
int min_fck_per_pck;
@@ -1143,10 +1315,10 @@
max_dss_fck = dss_feat_get_param_max(FEAT_PARAM_DSS_FCK);
- if (req_pck == dsi.cache_req_pck &&
- dsi.cache_cinfo.clkin == dss_sys_clk) {
+ if (req_pck == dsi->cache_req_pck &&
+ dsi->cache_cinfo.clkin == dss_sys_clk) {
DSSDBG("DSI clock info found from cache\n");
- *dsi_cinfo = dsi.cache_cinfo;
+ *dsi_cinfo = dsi->cache_cinfo;
dispc_find_clk_divs(is_tft, req_pck,
dsi_cinfo->dsi_pll_hsdiv_dispc_clk, dispc_cinfo);
return 0;
@@ -1176,17 +1348,17 @@
/* no highfreq: 0.75MHz < Fint = clkin / regn < 2.1MHz */
/* highfreq: 0.75MHz < Fint = clkin / (2*regn) < 2.1MHz */
/* To reduce PLL lock time, keep Fint high (around 2 MHz) */
- for (cur.regn = 1; cur.regn < dsi.regn_max; ++cur.regn) {
+ for (cur.regn = 1; cur.regn < dsi->regn_max; ++cur.regn) {
if (cur.highfreq == 0)
cur.fint = cur.clkin / cur.regn;
else
cur.fint = cur.clkin / (2 * cur.regn);
- if (cur.fint > dsi.fint_max || cur.fint < dsi.fint_min)
+ if (cur.fint > dsi->fint_max || cur.fint < dsi->fint_min)
continue;
/* DSIPHY(MHz) = (2 * regm / regn) * (clkin / (highfreq + 1)) */
- for (cur.regm = 1; cur.regm < dsi.regm_max; ++cur.regm) {
+ for (cur.regm = 1; cur.regm < dsi->regm_max; ++cur.regm) {
unsigned long a, b;
a = 2 * cur.regm * (cur.clkin/1000);
@@ -1198,8 +1370,8 @@
/* dsi_pll_hsdiv_dispc_clk(MHz) =
* DSIPHY(MHz) / regm_dispc < 173MHz/186Mhz */
- for (cur.regm_dispc = 1; cur.regm_dispc < dsi.regm_dispc_max;
- ++cur.regm_dispc) {
+ for (cur.regm_dispc = 1; cur.regm_dispc <
+ dsi->regm_dispc_max; ++cur.regm_dispc) {
struct dispc_clock_info cur_dispc;
cur.dsi_pll_hsdiv_dispc_clk =
cur.clkin4ddr / cur.regm_dispc;
@@ -1259,34 +1431,39 @@
if (dispc_cinfo)
*dispc_cinfo = best_dispc;
- dsi.cache_req_pck = req_pck;
- dsi.cache_clk_freq = 0;
- dsi.cache_cinfo = best;
+ dsi->cache_req_pck = req_pck;
+ dsi->cache_clk_freq = 0;
+ dsi->cache_cinfo = best;
return 0;
}
-int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo)
+int dsi_pll_set_clock_div(struct platform_device *dsidev,
+ struct dsi_clock_info *cinfo)
{
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
int r = 0;
u32 l;
- int f;
+ int f = 0;
u8 regn_start, regn_end, regm_start, regm_end;
u8 regm_dispc_start, regm_dispc_end, regm_dsi_start, regm_dsi_end;
DSSDBGF();
- dsi.current_cinfo.fint = cinfo->fint;
- dsi.current_cinfo.clkin4ddr = cinfo->clkin4ddr;
- dsi.current_cinfo.dsi_pll_hsdiv_dispc_clk =
+ dsi->current_cinfo.use_sys_clk = cinfo->use_sys_clk;
+ dsi->current_cinfo.highfreq = cinfo->highfreq;
+
+ dsi->current_cinfo.fint = cinfo->fint;
+ dsi->current_cinfo.clkin4ddr = cinfo->clkin4ddr;
+ dsi->current_cinfo.dsi_pll_hsdiv_dispc_clk =
cinfo->dsi_pll_hsdiv_dispc_clk;
- dsi.current_cinfo.dsi_pll_hsdiv_dsi_clk =
+ dsi->current_cinfo.dsi_pll_hsdiv_dsi_clk =
cinfo->dsi_pll_hsdiv_dsi_clk;
- dsi.current_cinfo.regn = cinfo->regn;
- dsi.current_cinfo.regm = cinfo->regm;
- dsi.current_cinfo.regm_dispc = cinfo->regm_dispc;
- dsi.current_cinfo.regm_dsi = cinfo->regm_dsi;
+ dsi->current_cinfo.regn = cinfo->regn;
+ dsi->current_cinfo.regm = cinfo->regm;
+ dsi->current_cinfo.regm_dispc = cinfo->regm_dispc;
+ dsi->current_cinfo.regm_dsi = cinfo->regm_dsi;
DSSDBG("DSI Fint %ld\n", cinfo->fint);
@@ -1309,12 +1486,12 @@
DSSDBG("Clock lane freq %ld Hz\n", cinfo->clkin4ddr / 4);
DSSDBG("regm_dispc = %d, %s (%s) = %lu\n", cinfo->regm_dispc,
- dss_get_generic_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
- dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
+ dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
+ dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
cinfo->dsi_pll_hsdiv_dispc_clk);
DSSDBG("regm_dsi = %d, %s (%s) = %lu\n", cinfo->regm_dsi,
- dss_get_generic_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
- dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
+ dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
+ dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
cinfo->dsi_pll_hsdiv_dsi_clk);
dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGN, ®n_start, ®n_end);
@@ -1324,9 +1501,10 @@
dss_feat_get_reg_field(FEAT_REG_DSIPLL_REGM_DSI, ®m_dsi_start,
®m_dsi_end);
- REG_FLD_MOD(DSI_PLL_CONTROL, 0, 0, 0); /* DSI_PLL_AUTOMODE = manual */
+ /* DSI_PLL_AUTOMODE = manual */
+ REG_FLD_MOD(dsidev, DSI_PLL_CONTROL, 0, 0, 0);
- l = dsi_read_reg(DSI_PLL_CONFIGURATION1);
+ l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION1);
l = FLD_MOD(l, 1, 0, 0); /* DSI_PLL_STOPMODE */
/* DSI_PLL_REGN */
l = FLD_MOD(l, cinfo->regn - 1, regn_start, regn_end);
@@ -1338,22 +1516,22 @@
/* DSIPROTO_CLOCK_DIV */
l = FLD_MOD(l, cinfo->regm_dsi > 0 ? cinfo->regm_dsi - 1 : 0,
regm_dsi_start, regm_dsi_end);
- dsi_write_reg(DSI_PLL_CONFIGURATION1, l);
+ dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION1, l);
- BUG_ON(cinfo->fint < dsi.fint_min || cinfo->fint > dsi.fint_max);
- if (cinfo->fint < 1000000)
- f = 0x3;
- else if (cinfo->fint < 1250000)
- f = 0x4;
- else if (cinfo->fint < 1500000)
- f = 0x5;
- else if (cinfo->fint < 1750000)
- f = 0x6;
- else
- f = 0x7;
+ BUG_ON(cinfo->fint < dsi->fint_min || cinfo->fint > dsi->fint_max);
- l = dsi_read_reg(DSI_PLL_CONFIGURATION2);
- l = FLD_MOD(l, f, 4, 1); /* DSI_PLL_FREQSEL */
+ if (dss_has_feature(FEAT_DSI_PLL_FREQSEL)) {
+ f = cinfo->fint < 1000000 ? 0x3 :
+ cinfo->fint < 1250000 ? 0x4 :
+ cinfo->fint < 1500000 ? 0x5 :
+ cinfo->fint < 1750000 ? 0x6 :
+ 0x7;
+ }
+
+ l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2);
+
+ if (dss_has_feature(FEAT_DSI_PLL_FREQSEL))
+ l = FLD_MOD(l, f, 4, 1); /* DSI_PLL_FREQSEL */
l = FLD_MOD(l, cinfo->use_sys_clk ? 0 : 1,
11, 11); /* DSI_PLL_CLKSEL */
l = FLD_MOD(l, cinfo->highfreq,
@@ -1361,25 +1539,25 @@
l = FLD_MOD(l, 1, 13, 13); /* DSI_PLL_REFEN */
l = FLD_MOD(l, 0, 14, 14); /* DSIPHY_CLKINEN */
l = FLD_MOD(l, 1, 20, 20); /* DSI_HSDIVBYPASS */
- dsi_write_reg(DSI_PLL_CONFIGURATION2, l);
+ dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l);
- REG_FLD_MOD(DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */
+ REG_FLD_MOD(dsidev, DSI_PLL_GO, 1, 0, 0); /* DSI_PLL_GO */
- if (wait_for_bit_change(DSI_PLL_GO, 0, 0) != 0) {
+ if (wait_for_bit_change(dsidev, DSI_PLL_GO, 0, 0) != 0) {
DSSERR("dsi pll go bit not going down.\n");
r = -EIO;
goto err;
}
- if (wait_for_bit_change(DSI_PLL_STATUS, 1, 1) != 1) {
+ if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 1, 1) != 1) {
DSSERR("cannot lock PLL\n");
r = -EIO;
goto err;
}
- dsi.pll_locked = 1;
+ dsi->pll_locked = 1;
- l = dsi_read_reg(DSI_PLL_CONFIGURATION2);
+ l = dsi_read_reg(dsidev, DSI_PLL_CONFIGURATION2);
l = FLD_MOD(l, 0, 0, 0); /* DSI_PLL_IDLE */
l = FLD_MOD(l, 0, 5, 5); /* DSI_PLL_PLLLPMODE */
l = FLD_MOD(l, 0, 6, 6); /* DSI_PLL_LOWCURRSTBY */
@@ -1394,52 +1572,53 @@
l = FLD_MOD(l, 1, 18, 18); /* DSI_PROTO_CLOCK_EN */
l = FLD_MOD(l, 0, 19, 19); /* DSI_PROTO_CLOCK_PWDN */
l = FLD_MOD(l, 0, 20, 20); /* DSI_HSDIVBYPASS */
- dsi_write_reg(DSI_PLL_CONFIGURATION2, l);
+ dsi_write_reg(dsidev, DSI_PLL_CONFIGURATION2, l);
DSSDBG("PLL config done\n");
err:
return r;
}
-int dsi_pll_init(struct omap_dss_device *dssdev, bool enable_hsclk,
+int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk,
bool enable_hsdiv)
{
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
int r = 0;
enum dsi_pll_power_state pwstate;
DSSDBG("PLL init\n");
-#ifdef CONFIG_OMAP2_DSS_USE_DSI_PLL
- /*
- * HACK: this is just a quick hack to get the USE_DSI_PLL
- * option working. USE_DSI_PLL is itself a big hack, and
- * should be removed.
- */
- if (dsi.vdds_dsi_reg == NULL) {
+ if (dsi->vdds_dsi_reg == NULL) {
struct regulator *vdds_dsi;
- vdds_dsi = regulator_get(&dsi.pdev->dev, "vdds_dsi");
+ vdds_dsi = regulator_get(&dsi->pdev->dev, "vdds_dsi");
if (IS_ERR(vdds_dsi)) {
DSSERR("can't get VDDS_DSI regulator\n");
return PTR_ERR(vdds_dsi);
}
- dsi.vdds_dsi_reg = vdds_dsi;
+ dsi->vdds_dsi_reg = vdds_dsi;
}
-#endif
enable_clocks(1);
- dsi_enable_pll_clock(1);
+ dsi_enable_pll_clock(dsidev, 1);
+ /*
+ * Note: SCP CLK is not required on OMAP3, but it is required on OMAP4.
+ */
+ dsi_enable_scp_clk(dsidev);
- r = regulator_enable(dsi.vdds_dsi_reg);
- if (r)
- goto err0;
+ if (!dsi->vdds_dsi_enabled) {
+ r = regulator_enable(dsi->vdds_dsi_reg);
+ if (r)
+ goto err0;
+ dsi->vdds_dsi_enabled = true;
+ }
/* XXX PLL does not come out of reset without this... */
dispc_pck_free_enable(1);
- if (wait_for_bit_change(DSI_PLL_STATUS, 0, 1) != 1) {
+ if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 0, 1) != 1) {
DSSERR("PLL not coming out of reset.\n");
r = -ENODEV;
dispc_pck_free_enable(0);
@@ -1459,7 +1638,7 @@
else
pwstate = DSI_PLL_POWER_OFF;
- r = dsi_pll_power(pwstate);
+ r = dsi_pll_power(dsidev, pwstate);
if (r)
goto err1;
@@ -1468,42 +1647,53 @@
return 0;
err1:
- regulator_disable(dsi.vdds_dsi_reg);
+ if (dsi->vdds_dsi_enabled) {
+ regulator_disable(dsi->vdds_dsi_reg);
+ dsi->vdds_dsi_enabled = false;
+ }
err0:
+ dsi_disable_scp_clk(dsidev);
enable_clocks(0);
- dsi_enable_pll_clock(0);
+ dsi_enable_pll_clock(dsidev, 0);
return r;
}
-void dsi_pll_uninit(void)
+void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes)
{
- enable_clocks(0);
- dsi_enable_pll_clock(0);
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
- dsi.pll_locked = 0;
- dsi_pll_power(DSI_PLL_POWER_OFF);
- regulator_disable(dsi.vdds_dsi_reg);
+ dsi->pll_locked = 0;
+ dsi_pll_power(dsidev, DSI_PLL_POWER_OFF);
+ if (disconnect_lanes) {
+ WARN_ON(!dsi->vdds_dsi_enabled);
+ regulator_disable(dsi->vdds_dsi_reg);
+ dsi->vdds_dsi_enabled = false;
+ }
+
+ dsi_disable_scp_clk(dsidev);
+ enable_clocks(0);
+ dsi_enable_pll_clock(dsidev, 0);
+
DSSDBG("PLL uninit done\n");
}
-void dsi_dump_clocks(struct seq_file *s)
+static void dsi_dump_dsidev_clocks(struct platform_device *dsidev,
+ struct seq_file *s)
{
- int clksel;
- struct dsi_clock_info *cinfo = &dsi.current_cinfo;
- enum dss_clk_source dispc_clk_src, dsi_clk_src;
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
+ struct dsi_clock_info *cinfo = &dsi->current_cinfo;
+ enum omap_dss_clk_source dispc_clk_src, dsi_clk_src;
+ int dsi_module = dsi_get_dsidev_id(dsidev);
dispc_clk_src = dss_get_dispc_clk_source();
- dsi_clk_src = dss_get_dsi_clk_source();
+ dsi_clk_src = dss_get_dsi_clk_source(dsi_module);
enable_clocks(1);
- clksel = REG_GET(DSI_PLL_CONFIGURATION2, 11, 11);
-
- seq_printf(s, "- DSI PLL -\n");
+ seq_printf(s, "- DSI%d PLL -\n", dsi_module + 1);
seq_printf(s, "dsi pll source = %s\n",
- clksel == 0 ?
- "dss_sys_clk" : "pclkfree");
+ cinfo->use_sys_clk ? "dss_sys_clk" : "pclkfree");
seq_printf(s, "Fint\t\t%-16luregn %u\n", cinfo->fint, cinfo->regn);
@@ -1515,7 +1705,7 @@
dss_feat_get_clk_source_name(dispc_clk_src),
cinfo->dsi_pll_hsdiv_dispc_clk,
cinfo->regm_dispc,
- dispc_clk_src == DSS_CLK_SRC_FCK ?
+ dispc_clk_src == OMAP_DSS_CLK_SRC_FCK ?
"off" : "on");
seq_printf(s, "%s (%s)\t%-16luregm_dsi %u\t(%s)\n",
@@ -1523,45 +1713,55 @@
dss_feat_get_clk_source_name(dsi_clk_src),
cinfo->dsi_pll_hsdiv_dsi_clk,
cinfo->regm_dsi,
- dsi_clk_src == DSS_CLK_SRC_FCK ?
+ dsi_clk_src == OMAP_DSS_CLK_SRC_FCK ?
"off" : "on");
- seq_printf(s, "- DSI -\n");
+ seq_printf(s, "- DSI%d -\n", dsi_module + 1);
seq_printf(s, "dsi fclk source = %s (%s)\n",
dss_get_generic_clk_source_name(dsi_clk_src),
dss_feat_get_clk_source_name(dsi_clk_src));
- seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate());
+ seq_printf(s, "DSI_FCLK\t%lu\n", dsi_fclk_rate(dsidev));
seq_printf(s, "DDR_CLK\t\t%lu\n",
cinfo->clkin4ddr / 4);
- seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs());
+ seq_printf(s, "TxByteClkHS\t%lu\n", dsi_get_txbyteclkhs(dsidev));
seq_printf(s, "LP_CLK\t\t%lu\n", cinfo->lp_clk);
- seq_printf(s, "VP_CLK\t\t%lu\n"
- "VP_PCLK\t\t%lu\n",
- dispc_lclk_rate(OMAP_DSS_CHANNEL_LCD),
- dispc_pclk_rate(OMAP_DSS_CHANNEL_LCD));
-
enable_clocks(0);
}
-#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
-void dsi_dump_irqs(struct seq_file *s)
+void dsi_dump_clocks(struct seq_file *s)
{
+ struct platform_device *dsidev;
+ int i;
+
+ for (i = 0; i < MAX_NUM_DSI; i++) {
+ dsidev = dsi_get_dsidev_from_id(i);
+ if (dsidev)
+ dsi_dump_dsidev_clocks(dsidev, s);
+ }
+}
+
+#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
+static void dsi_dump_dsidev_irqs(struct platform_device *dsidev,
+ struct seq_file *s)
+{
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
unsigned long flags;
struct dsi_irq_stats stats;
+ int dsi_module = dsi_get_dsidev_id(dsidev);
- spin_lock_irqsave(&dsi.irq_stats_lock, flags);
+ spin_lock_irqsave(&dsi->irq_stats_lock, flags);
- stats = dsi.irq_stats;
- memset(&dsi.irq_stats, 0, sizeof(dsi.irq_stats));
- dsi.irq_stats.last_reset = jiffies;
+ stats = dsi->irq_stats;
+ memset(&dsi->irq_stats, 0, sizeof(dsi->irq_stats));
+ dsi->irq_stats.last_reset = jiffies;
- spin_unlock_irqrestore(&dsi.irq_stats_lock, flags);
+ spin_unlock_irqrestore(&dsi->irq_stats_lock, flags);
seq_printf(s, "period %u ms\n",
jiffies_to_msecs(jiffies - stats.last_reset));
@@ -1570,7 +1770,7 @@
#define PIS(x) \
seq_printf(s, "%-20s %10d\n", #x, stats.dsi_irqs[ffs(DSI_IRQ_##x)-1]);
- seq_printf(s, "-- DSI interrupts --\n");
+ seq_printf(s, "-- DSI%d interrupts --\n", dsi_module + 1);
PIS(VC0);
PIS(VC1);
PIS(VC2);
@@ -1636,13 +1836,45 @@
PIS(ULPSACTIVENOT_ALL1);
#undef PIS
}
+
+static void dsi1_dump_irqs(struct seq_file *s)
+{
+ struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
+
+ dsi_dump_dsidev_irqs(dsidev, s);
+}
+
+static void dsi2_dump_irqs(struct seq_file *s)
+{
+ struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
+
+ dsi_dump_dsidev_irqs(dsidev, s);
+}
+
+void dsi_create_debugfs_files_irq(struct dentry *debugfs_dir,
+ const struct file_operations *debug_fops)
+{
+ struct platform_device *dsidev;
+
+ dsidev = dsi_get_dsidev_from_id(0);
+ if (dsidev)
+ debugfs_create_file("dsi1_irqs", S_IRUGO, debugfs_dir,
+ &dsi1_dump_irqs, debug_fops);
+
+ dsidev = dsi_get_dsidev_from_id(1);
+ if (dsidev)
+ debugfs_create_file("dsi2_irqs", S_IRUGO, debugfs_dir,
+ &dsi2_dump_irqs, debug_fops);
+}
#endif
-void dsi_dump_regs(struct seq_file *s)
+static void dsi_dump_dsidev_regs(struct platform_device *dsidev,
+ struct seq_file *s)
{
-#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(r))
+#define DUMPREG(r) seq_printf(s, "%-35s %08x\n", #r, dsi_read_reg(dsidev, r))
dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
+ dsi_enable_scp_clk(dsidev);
DUMPREG(DSI_REVISION);
DUMPREG(DSI_SYSCONFIG);
@@ -1714,25 +1946,57 @@
DUMPREG(DSI_PLL_CONFIGURATION1);
DUMPREG(DSI_PLL_CONFIGURATION2);
+ dsi_disable_scp_clk(dsidev);
dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
#undef DUMPREG
}
-enum dsi_complexio_power_state {
+static void dsi1_dump_regs(struct seq_file *s)
+{
+ struct platform_device *dsidev = dsi_get_dsidev_from_id(0);
+
+ dsi_dump_dsidev_regs(dsidev, s);
+}
+
+static void dsi2_dump_regs(struct seq_file *s)
+{
+ struct platform_device *dsidev = dsi_get_dsidev_from_id(1);
+
+ dsi_dump_dsidev_regs(dsidev, s);
+}
+
+void dsi_create_debugfs_files_reg(struct dentry *debugfs_dir,
+ const struct file_operations *debug_fops)
+{
+ struct platform_device *dsidev;
+
+ dsidev = dsi_get_dsidev_from_id(0);
+ if (dsidev)
+ debugfs_create_file("dsi1_regs", S_IRUGO, debugfs_dir,
+ &dsi1_dump_regs, debug_fops);
+
+ dsidev = dsi_get_dsidev_from_id(1);
+ if (dsidev)
+ debugfs_create_file("dsi2_regs", S_IRUGO, debugfs_dir,
+ &dsi2_dump_regs, debug_fops);
+}
+enum dsi_cio_power_state {
DSI_COMPLEXIO_POWER_OFF = 0x0,
DSI_COMPLEXIO_POWER_ON = 0x1,
DSI_COMPLEXIO_POWER_ULPS = 0x2,
};
-static int dsi_complexio_power(enum dsi_complexio_power_state state)
+static int dsi_cio_power(struct platform_device *dsidev,
+ enum dsi_cio_power_state state)
{
int t = 0;
/* PWR_CMD */
- REG_FLD_MOD(DSI_COMPLEXIO_CFG1, state, 28, 27);
+ REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG1, state, 28, 27);
/* PWR_STATUS */
- while (FLD_GET(dsi_read_reg(DSI_COMPLEXIO_CFG1), 26, 25) != state) {
+ while (FLD_GET(dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1),
+ 26, 25) != state) {
if (++t > 1000) {
DSSERR("failed to set complexio power state to "
"%d\n", state);
@@ -1744,9 +2008,70 @@
return 0;
}
-static void dsi_complexio_config(struct omap_dss_device *dssdev)
+/* Number of data lanes present on DSI interface */
+static inline int dsi_get_num_data_lanes(struct platform_device *dsidev)
{
+ /* DSI on OMAP3 doesn't have register DSI_GNQ, set number
+ * of data lanes as 2 by default */
+ if (dss_has_feature(FEAT_DSI_GNQ))
+ return REG_GET(dsidev, DSI_GNQ, 11, 9); /* NB_DATA_LANES */
+ else
+ return 2;
+}
+
+/* Number of data lanes used by the dss device */
+static inline int dsi_get_num_data_lanes_dssdev(struct omap_dss_device *dssdev)
+{
+ int num_data_lanes = 0;
+
+ if (dssdev->phy.dsi.data1_lane != 0)
+ num_data_lanes++;
+ if (dssdev->phy.dsi.data2_lane != 0)
+ num_data_lanes++;
+ if (dssdev->phy.dsi.data3_lane != 0)
+ num_data_lanes++;
+ if (dssdev->phy.dsi.data4_lane != 0)
+ num_data_lanes++;
+
+ return num_data_lanes;
+}
+
+static unsigned dsi_get_line_buf_size(struct platform_device *dsidev)
+{
+ int val;
+
+ /* line buffer on OMAP3 is 1024 x 24bits */
+ /* XXX: for some reason using full buffer size causes
+ * considerable TX slowdown with update sizes that fill the
+ * whole buffer */
+ if (!dss_has_feature(FEAT_DSI_GNQ))
+ return 1023 * 3;
+
+ val = REG_GET(dsidev, DSI_GNQ, 14, 12); /* VP1_LINE_BUFFER_SIZE */
+
+ switch (val) {
+ case 1:
+ return 512 * 3; /* 512x24 bits */
+ case 2:
+ return 682 * 3; /* 682x24 bits */
+ case 3:
+ return 853 * 3; /* 853x24 bits */
+ case 4:
+ return 1024 * 3; /* 1024x24 bits */
+ case 5:
+ return 1194 * 3; /* 1194x24 bits */
+ case 6:
+ return 1365 * 3; /* 1365x24 bits */
+ default:
+ BUG();
+ }
+}
+
+static void dsi_set_lane_config(struct omap_dss_device *dssdev)
+{
+ struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
u32 r;
+ int num_data_lanes_dssdev = dsi_get_num_data_lanes_dssdev(dssdev);
int clk_lane = dssdev->phy.dsi.clk_lane;
int data1_lane = dssdev->phy.dsi.data1_lane;
@@ -1755,14 +2080,28 @@
int data1_pol = dssdev->phy.dsi.data1_pol;
int data2_pol = dssdev->phy.dsi.data2_pol;
- r = dsi_read_reg(DSI_COMPLEXIO_CFG1);
+ r = dsi_read_reg(dsidev, DSI_COMPLEXIO_CFG1);
r = FLD_MOD(r, clk_lane, 2, 0);
r = FLD_MOD(r, clk_pol, 3, 3);
r = FLD_MOD(r, data1_lane, 6, 4);
r = FLD_MOD(r, data1_pol, 7, 7);
r = FLD_MOD(r, data2_lane, 10, 8);
r = FLD_MOD(r, data2_pol, 11, 11);
- dsi_write_reg(DSI_COMPLEXIO_CFG1, r);
+ if (num_data_lanes_dssdev > 2) {
+ int data3_lane = dssdev->phy.dsi.data3_lane;
+ int data3_pol = dssdev->phy.dsi.data3_pol;
+
+ r = FLD_MOD(r, data3_lane, 14, 12);
+ r = FLD_MOD(r, data3_pol, 15, 15);
+ }
+ if (num_data_lanes_dssdev > 3) {
+ int data4_lane = dssdev->phy.dsi.data4_lane;
+ int data4_pol = dssdev->phy.dsi.data4_pol;
+
+ r = FLD_MOD(r, data4_lane, 18, 16);
+ r = FLD_MOD(r, data4_pol, 19, 19);
+ }
+ dsi_write_reg(dsidev, DSI_COMPLEXIO_CFG1, r);
/* The configuration of the DSI complex I/O (number of data lanes,
position, differential order) should not be changed while
@@ -1776,27 +2115,31 @@
DSI complex I/O configuration is unknown. */
/*
- REG_FLD_MOD(DSI_CTRL, 1, 0, 0);
- REG_FLD_MOD(DSI_CTRL, 0, 0, 0);
- REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20);
- REG_FLD_MOD(DSI_CTRL, 1, 0, 0);
+ REG_FLD_MOD(dsidev, DSI_CTRL, 1, 0, 0);
+ REG_FLD_MOD(dsidev, DSI_CTRL, 0, 0, 0);
+ REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20);
+ REG_FLD_MOD(dsidev, DSI_CTRL, 1, 0, 0);
*/
}
-static inline unsigned ns2ddr(unsigned ns)
+static inline unsigned ns2ddr(struct platform_device *dsidev, unsigned ns)
{
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
+
/* convert time in ns to ddr ticks, rounding up */
- unsigned long ddr_clk = dsi.current_cinfo.clkin4ddr / 4;
+ unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4;
return (ns * (ddr_clk / 1000 / 1000) + 999) / 1000;
}
-static inline unsigned ddr2ns(unsigned ddr)
+static inline unsigned ddr2ns(struct platform_device *dsidev, unsigned ddr)
{
- unsigned long ddr_clk = dsi.current_cinfo.clkin4ddr / 4;
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
+
+ unsigned long ddr_clk = dsi->current_cinfo.clkin4ddr / 4;
return ddr * 1000 * 1000 / (ddr_clk / 1000);
}
-static void dsi_complexio_timings(void)
+static void dsi_cio_timings(struct platform_device *dsidev)
{
u32 r;
u32 ths_prepare, ths_prepare_ths_zero, ths_trail, ths_exit;
@@ -1808,139 +2151,323 @@
/* 1 * DDR_CLK = 2 * UI */
/* min 40ns + 4*UI max 85ns + 6*UI */
- ths_prepare = ns2ddr(70) + 2;
+ ths_prepare = ns2ddr(dsidev, 70) + 2;
/* min 145ns + 10*UI */
- ths_prepare_ths_zero = ns2ddr(175) + 2;
+ ths_prepare_ths_zero = ns2ddr(dsidev, 175) + 2;
/* min max(8*UI, 60ns+4*UI) */
- ths_trail = ns2ddr(60) + 5;
+ ths_trail = ns2ddr(dsidev, 60) + 5;
/* min 100ns */
- ths_exit = ns2ddr(145);
+ ths_exit = ns2ddr(dsidev, 145);
/* tlpx min 50n */
- tlpx_half = ns2ddr(25);
+ tlpx_half = ns2ddr(dsidev, 25);
/* min 60ns */
- tclk_trail = ns2ddr(60) + 2;
+ tclk_trail = ns2ddr(dsidev, 60) + 2;
/* min 38ns, max 95ns */
- tclk_prepare = ns2ddr(65);
+ tclk_prepare = ns2ddr(dsidev, 65);
/* min tclk-prepare + tclk-zero = 300ns */
- tclk_zero = ns2ddr(260);
+ tclk_zero = ns2ddr(dsidev, 260);
DSSDBG("ths_prepare %u (%uns), ths_prepare_ths_zero %u (%uns)\n",
- ths_prepare, ddr2ns(ths_prepare),
- ths_prepare_ths_zero, ddr2ns(ths_prepare_ths_zero));
+ ths_prepare, ddr2ns(dsidev, ths_prepare),
+ ths_prepare_ths_zero, ddr2ns(dsidev, ths_prepare_ths_zero));
DSSDBG("ths_trail %u (%uns), ths_exit %u (%uns)\n",
- ths_trail, ddr2ns(ths_trail),
- ths_exit, ddr2ns(ths_exit));
+ ths_trail, ddr2ns(dsidev, ths_trail),
+ ths_exit, ddr2ns(dsidev, ths_exit));
DSSDBG("tlpx_half %u (%uns), tclk_trail %u (%uns), "
"tclk_zero %u (%uns)\n",
- tlpx_half, ddr2ns(tlpx_half),
- tclk_trail, ddr2ns(tclk_trail),
- tclk_zero, ddr2ns(tclk_zero));
+ tlpx_half, ddr2ns(dsidev, tlpx_half),
+ tclk_trail, ddr2ns(dsidev, tclk_trail),
+ tclk_zero, ddr2ns(dsidev, tclk_zero));
DSSDBG("tclk_prepare %u (%uns)\n",
- tclk_prepare, ddr2ns(tclk_prepare));
+ tclk_prepare, ddr2ns(dsidev, tclk_prepare));
/* program timings */
- r = dsi_read_reg(DSI_DSIPHY_CFG0);
+ r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
r = FLD_MOD(r, ths_prepare, 31, 24);
r = FLD_MOD(r, ths_prepare_ths_zero, 23, 16);
r = FLD_MOD(r, ths_trail, 15, 8);
r = FLD_MOD(r, ths_exit, 7, 0);
- dsi_write_reg(DSI_DSIPHY_CFG0, r);
+ dsi_write_reg(dsidev, DSI_DSIPHY_CFG0, r);
- r = dsi_read_reg(DSI_DSIPHY_CFG1);
+ r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
r = FLD_MOD(r, tlpx_half, 22, 16);
r = FLD_MOD(r, tclk_trail, 15, 8);
r = FLD_MOD(r, tclk_zero, 7, 0);
- dsi_write_reg(DSI_DSIPHY_CFG1, r);
+ dsi_write_reg(dsidev, DSI_DSIPHY_CFG1, r);
- r = dsi_read_reg(DSI_DSIPHY_CFG2);
+ r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
r = FLD_MOD(r, tclk_prepare, 7, 0);
- dsi_write_reg(DSI_DSIPHY_CFG2, r);
+ dsi_write_reg(dsidev, DSI_DSIPHY_CFG2, r);
}
-
-static int dsi_complexio_init(struct omap_dss_device *dssdev)
+static void dsi_cio_enable_lane_override(struct omap_dss_device *dssdev,
+ enum dsi_lane lanes)
{
- int r = 0;
+ struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
+ int clk_lane = dssdev->phy.dsi.clk_lane;
+ int data1_lane = dssdev->phy.dsi.data1_lane;
+ int data2_lane = dssdev->phy.dsi.data2_lane;
+ int data3_lane = dssdev->phy.dsi.data3_lane;
+ int data4_lane = dssdev->phy.dsi.data4_lane;
+ int clk_pol = dssdev->phy.dsi.clk_pol;
+ int data1_pol = dssdev->phy.dsi.data1_pol;
+ int data2_pol = dssdev->phy.dsi.data2_pol;
+ int data3_pol = dssdev->phy.dsi.data3_pol;
+ int data4_pol = dssdev->phy.dsi.data4_pol;
- DSSDBG("dsi_complexio_init\n");
+ u32 l = 0;
+ u8 lptxscp_start = dsi->num_data_lanes == 2 ? 22 : 26;
- /* CIO_CLK_ICG, enable L3 clk to CIO */
- REG_FLD_MOD(DSI_CLK_CTRL, 1, 14, 14);
+ if (lanes & DSI_CLK_P)
+ l |= 1 << ((clk_lane - 1) * 2 + (clk_pol ? 0 : 1));
+ if (lanes & DSI_CLK_N)
+ l |= 1 << ((clk_lane - 1) * 2 + (clk_pol ? 1 : 0));
+
+ if (lanes & DSI_DATA1_P)
+ l |= 1 << ((data1_lane - 1) * 2 + (data1_pol ? 0 : 1));
+ if (lanes & DSI_DATA1_N)
+ l |= 1 << ((data1_lane - 1) * 2 + (data1_pol ? 1 : 0));
+
+ if (lanes & DSI_DATA2_P)
+ l |= 1 << ((data2_lane - 1) * 2 + (data2_pol ? 0 : 1));
+ if (lanes & DSI_DATA2_N)
+ l |= 1 << ((data2_lane - 1) * 2 + (data2_pol ? 1 : 0));
+
+ if (lanes & DSI_DATA3_P)
+ l |= 1 << ((data3_lane - 1) * 2 + (data3_pol ? 0 : 1));
+ if (lanes & DSI_DATA3_N)
+ l |= 1 << ((data3_lane - 1) * 2 + (data3_pol ? 1 : 0));
+
+ if (lanes & DSI_DATA4_P)
+ l |= 1 << ((data4_lane - 1) * 2 + (data4_pol ? 0 : 1));
+ if (lanes & DSI_DATA4_N)
+ l |= 1 << ((data4_lane - 1) * 2 + (data4_pol ? 1 : 0));
+ /*
+ * Bits in REGLPTXSCPDAT4TO0DXDY:
+ * 17: DY0 18: DX0
+ * 19: DY1 20: DX1
+ * 21: DY2 22: DX2
+ * 23: DY3 24: DX3
+ * 25: DY4 26: DX4
+ */
+
+ /* Set the lane override configuration */
+
+ /* REGLPTXSCPDAT4TO0DXDY */
+ REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, l, lptxscp_start, 17);
+
+ /* Enable lane override */
+
+ /* ENLPTXSCPDAT */
+ REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 1, 27, 27);
+}
+
+static void dsi_cio_disable_lane_override(struct platform_device *dsidev)
+{
+ /* Disable lane override */
+ REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 27, 27); /* ENLPTXSCPDAT */
+ /* Reset the lane override configuration */
+ /* REGLPTXSCPDAT4TO0DXDY */
+ REG_FLD_MOD(dsidev, DSI_DSIPHY_CFG10, 0, 22, 17);
+}
+
+static int dsi_cio_wait_tx_clk_esc_reset(struct omap_dss_device *dssdev)
+{
+ struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
+ int t;
+ int bits[3];
+ bool in_use[3];
+
+ if (dss_has_feature(FEAT_DSI_REVERSE_TXCLKESC)) {
+ bits[0] = 28;
+ bits[1] = 27;
+ bits[2] = 26;
+ } else {
+ bits[0] = 24;
+ bits[1] = 25;
+ bits[2] = 26;
+ }
+
+ in_use[0] = false;
+ in_use[1] = false;
+ in_use[2] = false;
+
+ if (dssdev->phy.dsi.clk_lane != 0)
+ in_use[dssdev->phy.dsi.clk_lane - 1] = true;
+ if (dssdev->phy.dsi.data1_lane != 0)
+ in_use[dssdev->phy.dsi.data1_lane - 1] = true;
+ if (dssdev->phy.dsi.data2_lane != 0)
+ in_use[dssdev->phy.dsi.data2_lane - 1] = true;
+
+ t = 100000;
+ while (true) {
+ u32 l;
+ int i;
+ int ok;
+
+ l = dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
+
+ ok = 0;
+ for (i = 0; i < 3; ++i) {
+ if (!in_use[i] || (l & (1 << bits[i])))
+ ok++;
+ }
+
+ if (ok == 3)
+ break;
+
+ if (--t == 0) {
+ for (i = 0; i < 3; ++i) {
+ if (!in_use[i] || (l & (1 << bits[i])))
+ continue;
+
+ DSSERR("CIO TXCLKESC%d domain not coming " \
+ "out of reset\n", i);
+ }
+ return -EIO;
+ }
+ }
+
+ return 0;
+}
+
+static int dsi_cio_init(struct omap_dss_device *dssdev)
+{
+ struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
+ int r;
+ int num_data_lanes_dssdev = dsi_get_num_data_lanes_dssdev(dssdev);
+ u32 l;
+
+ DSSDBGF();
+
+ if (dsi->dsi_mux_pads)
+ dsi->dsi_mux_pads(true);
+
+ dsi_enable_scp_clk(dsidev);
/* A dummy read using the SCP interface to any DSIPHY register is
* required after DSIPHY reset to complete the reset of the DSI complex
* I/O. */
- dsi_read_reg(DSI_DSIPHY_CFG5);
+ dsi_read_reg(dsidev, DSI_DSIPHY_CFG5);
- if (wait_for_bit_change(DSI_DSIPHY_CFG5, 30, 1) != 1) {
- DSSERR("ComplexIO PHY not coming out of reset.\n");
- r = -ENODEV;
- goto err;
+ if (wait_for_bit_change(dsidev, DSI_DSIPHY_CFG5, 30, 1) != 1) {
+ DSSERR("CIO SCP Clock domain not coming out of reset.\n");
+ r = -EIO;
+ goto err_scp_clk_dom;
}
- dsi_complexio_config(dssdev);
+ dsi_set_lane_config(dssdev);
- r = dsi_complexio_power(DSI_COMPLEXIO_POWER_ON);
+ /* set TX STOP MODE timer to maximum for this operation */
+ l = dsi_read_reg(dsidev, DSI_TIMING1);
+ l = FLD_MOD(l, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
+ l = FLD_MOD(l, 1, 14, 14); /* STOP_STATE_X16_IO */
+ l = FLD_MOD(l, 1, 13, 13); /* STOP_STATE_X4_IO */
+ l = FLD_MOD(l, 0x1fff, 12, 0); /* STOP_STATE_COUNTER_IO */
+ dsi_write_reg(dsidev, DSI_TIMING1, l);
+ if (dsi->ulps_enabled) {
+ u32 lane_mask = DSI_CLK_P | DSI_DATA1_P | DSI_DATA2_P;
+
+ DSSDBG("manual ulps exit\n");
+
+ /* ULPS is exited by Mark-1 state for 1ms, followed by
+ * stop state. DSS HW cannot do this via the normal
+ * ULPS exit sequence, as after reset the DSS HW thinks
+ * that we are not in ULPS mode, and refuses to send the
+ * sequence. So we need to send the ULPS exit sequence
+ * manually.
+ */
+
+ if (num_data_lanes_dssdev > 2)
+ lane_mask |= DSI_DATA3_P;
+
+ if (num_data_lanes_dssdev > 3)
+ lane_mask |= DSI_DATA4_P;
+
+ dsi_cio_enable_lane_override(dssdev, lane_mask);
+ }
+
+ r = dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ON);
if (r)
- goto err;
+ goto err_cio_pwr;
- if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
- DSSERR("ComplexIO not coming out of reset.\n");
+ if (wait_for_bit_change(dsidev, DSI_COMPLEXIO_CFG1, 29, 1) != 1) {
+ DSSERR("CIO PWR clock domain not coming out of reset.\n");
r = -ENODEV;
- goto err;
+ goto err_cio_pwr_dom;
}
- if (wait_for_bit_change(DSI_COMPLEXIO_CFG1, 21, 1) != 1) {
- DSSERR("ComplexIO LDO power down.\n");
- r = -ENODEV;
- goto err;
+ dsi_if_enable(dsidev, true);
+ dsi_if_enable(dsidev, false);
+ REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
+
+ r = dsi_cio_wait_tx_clk_esc_reset(dssdev);
+ if (r)
+ goto err_tx_clk_esc_rst;
+
+ if (dsi->ulps_enabled) {
+ /* Keep Mark-1 state for 1ms (as per DSI spec) */
+ ktime_t wait = ns_to_ktime(1000 * 1000);
+ set_current_state(TASK_UNINTERRUPTIBLE);
+ schedule_hrtimeout(&wait, HRTIMER_MODE_REL);
+
+ /* Disable the override. The lanes should be set to Mark-11
+ * state by the HW */
+ dsi_cio_disable_lane_override(dsidev);
}
- dsi_complexio_timings();
+ /* FORCE_TX_STOP_MODE_IO */
+ REG_FLD_MOD(dsidev, DSI_TIMING1, 0, 15, 15);
- /*
- The configuration of the DSI complex I/O (number of data lanes,
- position, differential order) should not be changed while
- DSS.DSI_CLK_CRTRL[20] LP_CLK_ENABLE bit is set to 1. For the
- hardware to recognize a new configuration of the complex I/O (done
- in DSS.DSI_COMPLEXIO_CFG1 register), it is recommended to follow
- this sequence: First set the DSS.DSI_CTRL[0] IF_EN bit to 1, next
- reset the DSS.DSI_CTRL[0] IF_EN to 0, then set DSS.DSI_CLK_CTRL[20]
- LP_CLK_ENABLE to 1, and finally, set again the DSS.DSI_CTRL[0] IF_EN
- bit to 1. If the sequence is not followed, the DSi complex I/O
- configuration is undetermined.
- */
- dsi_if_enable(1);
- dsi_if_enable(0);
- REG_FLD_MOD(DSI_CLK_CTRL, 1, 20, 20); /* LP_CLK_ENABLE */
- dsi_if_enable(1);
- dsi_if_enable(0);
+ dsi_cio_timings(dsidev);
+
+ dsi->ulps_enabled = false;
DSSDBG("CIO init done\n");
-err:
+
+ return 0;
+
+err_tx_clk_esc_rst:
+ REG_FLD_MOD(dsidev, DSI_CLK_CTRL, 0, 20, 20); /* LP_CLK_ENABLE */
+err_cio_pwr_dom:
+ dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
+err_cio_pwr:
+ if (dsi->ulps_enabled)
+ dsi_cio_disable_lane_override(dsidev);
+err_scp_clk_dom:
+ dsi_disable_scp_clk(dsidev);
+ if (dsi->dsi_mux_pads)
+ dsi->dsi_mux_pads(false);
return r;
}
-static void dsi_complexio_uninit(void)
+static void dsi_cio_uninit(struct platform_device *dsidev)
{
- dsi_complexio_power(DSI_COMPLEXIO_POWER_OFF);
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
+
+ dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_OFF);
+ dsi_disable_scp_clk(dsidev);
+ if (dsi->dsi_mux_pads)
+ dsi->dsi_mux_pads(false);
}
-static int _dsi_wait_reset(void)
+static int _dsi_wait_reset(struct platform_device *dsidev)
{
int t = 0;
- while (REG_GET(DSI_SYSSTATUS, 0, 0) == 0) {
+ while (REG_GET(dsidev, DSI_SYSSTATUS, 0, 0) == 0) {
if (++t > 5) {
DSSERR("soft reset failed\n");
return -ENODEV;
@@ -1951,28 +2478,30 @@
return 0;
}
-static int _dsi_reset(void)
+static int _dsi_reset(struct platform_device *dsidev)
{
/* Soft reset */
- REG_FLD_MOD(DSI_SYSCONFIG, 1, 1, 1);
- return _dsi_wait_reset();
+ REG_FLD_MOD(dsidev, DSI_SYSCONFIG, 1, 1, 1);
+ return _dsi_wait_reset(dsidev);
}
-static void dsi_config_tx_fifo(enum fifo_size size1, enum fifo_size size2,
+static void dsi_config_tx_fifo(struct platform_device *dsidev,
+ enum fifo_size size1, enum fifo_size size2,
enum fifo_size size3, enum fifo_size size4)
{
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
u32 r = 0;
int add = 0;
int i;
- dsi.vc[0].fifo_size = size1;
- dsi.vc[1].fifo_size = size2;
- dsi.vc[2].fifo_size = size3;
- dsi.vc[3].fifo_size = size4;
+ dsi->vc[0].fifo_size = size1;
+ dsi->vc[1].fifo_size = size2;
+ dsi->vc[2].fifo_size = size3;
+ dsi->vc[3].fifo_size = size4;
for (i = 0; i < 4; i++) {
u8 v;
- int size = dsi.vc[i].fifo_size;
+ int size = dsi->vc[i].fifo_size;
if (add + size > 4) {
DSSERR("Illegal FIFO configuration\n");
@@ -1985,24 +2514,26 @@
add += size;
}
- dsi_write_reg(DSI_TX_FIFO_VC_SIZE, r);
+ dsi_write_reg(dsidev, DSI_TX_FIFO_VC_SIZE, r);
}
-static void dsi_config_rx_fifo(enum fifo_size size1, enum fifo_size size2,
+static void dsi_config_rx_fifo(struct platform_device *dsidev,
+ enum fifo_size size1, enum fifo_size size2,
enum fifo_size size3, enum fifo_size size4)
{
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
u32 r = 0;
int add = 0;
int i;
- dsi.vc[0].fifo_size = size1;
- dsi.vc[1].fifo_size = size2;
- dsi.vc[2].fifo_size = size3;
- dsi.vc[3].fifo_size = size4;
+ dsi->vc[0].fifo_size = size1;
+ dsi->vc[1].fifo_size = size2;
+ dsi->vc[2].fifo_size = size3;
+ dsi->vc[3].fifo_size = size4;
for (i = 0; i < 4; i++) {
u8 v;
- int size = dsi.vc[i].fifo_size;
+ int size = dsi->vc[i].fifo_size;
if (add + size > 4) {
DSSERR("Illegal FIFO configuration\n");
@@ -2015,18 +2546,18 @@
add += size;
}
- dsi_write_reg(DSI_RX_FIFO_VC_SIZE, r);
+ dsi_write_reg(dsidev, DSI_RX_FIFO_VC_SIZE, r);
}
-static int dsi_force_tx_stop_mode_io(void)
+static int dsi_force_tx_stop_mode_io(struct platform_device *dsidev)
{
u32 r;
- r = dsi_read_reg(DSI_TIMING1);
+ r = dsi_read_reg(dsidev, DSI_TIMING1);
r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
- dsi_write_reg(DSI_TIMING1, r);
+ dsi_write_reg(dsidev, DSI_TIMING1, r);
- if (wait_for_bit_change(DSI_TIMING1, 15, 0) != 0) {
+ if (wait_for_bit_change(dsidev, DSI_TIMING1, 15, 0) != 0) {
DSSERR("TX_STOP bit not going down\n");
return -EIO;
}
@@ -2034,16 +2565,135 @@
return 0;
}
-static int dsi_vc_enable(int channel, bool enable)
+static bool dsi_vc_is_enabled(struct platform_device *dsidev, int channel)
+{
+ return REG_GET(dsidev, DSI_VC_CTRL(channel), 0, 0);
+}
+
+static void dsi_packet_sent_handler_vp(void *data, u32 mask)
+{
+ struct dsi_packet_sent_handler_data *vp_data =
+ (struct dsi_packet_sent_handler_data *) data;
+ struct dsi_data *dsi = dsi_get_dsidrv_data(vp_data->dsidev);
+ const int channel = dsi->update_channel;
+ u8 bit = dsi->te_enabled ? 30 : 31;
+
+ if (REG_GET(vp_data->dsidev, DSI_VC_TE(channel), bit, bit) == 0)
+ complete(vp_data->completion);
+}
+
+static int dsi_sync_vc_vp(struct platform_device *dsidev, int channel)
+{
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
+ DECLARE_COMPLETION_ONSTACK(completion);
+ struct dsi_packet_sent_handler_data vp_data = { dsidev, &completion };
+ int r = 0;
+ u8 bit;
+
+ bit = dsi->te_enabled ? 30 : 31;
+
+ r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
+ &vp_data, DSI_VC_IRQ_PACKET_SENT);
+ if (r)
+ goto err0;
+
+ /* Wait for completion only if TE_EN/TE_START is still set */
+ if (REG_GET(dsidev, DSI_VC_TE(channel), bit, bit)) {
+ if (wait_for_completion_timeout(&completion,
+ msecs_to_jiffies(10)) == 0) {
+ DSSERR("Failed to complete previous frame transfer\n");
+ r = -EIO;
+ goto err1;
+ }
+ }
+
+ dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
+ &vp_data, DSI_VC_IRQ_PACKET_SENT);
+
+ return 0;
+err1:
+ dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_vp,
+ &vp_data, DSI_VC_IRQ_PACKET_SENT);
+err0:
+ return r;
+}
+
+static void dsi_packet_sent_handler_l4(void *data, u32 mask)
+{
+ struct dsi_packet_sent_handler_data *l4_data =
+ (struct dsi_packet_sent_handler_data *) data;
+ struct dsi_data *dsi = dsi_get_dsidrv_data(l4_data->dsidev);
+ const int channel = dsi->update_channel;
+
+ if (REG_GET(l4_data->dsidev, DSI_VC_CTRL(channel), 5, 5) == 0)
+ complete(l4_data->completion);
+}
+
+static int dsi_sync_vc_l4(struct platform_device *dsidev, int channel)
+{
+ DECLARE_COMPLETION_ONSTACK(completion);
+ struct dsi_packet_sent_handler_data l4_data = { dsidev, &completion };
+ int r = 0;
+
+ r = dsi_register_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
+ &l4_data, DSI_VC_IRQ_PACKET_SENT);
+ if (r)
+ goto err0;
+
+ /* Wait for completion only if TX_FIFO_NOT_EMPTY is still set */
+ if (REG_GET(dsidev, DSI_VC_CTRL(channel), 5, 5)) {
+ if (wait_for_completion_timeout(&completion,
+ msecs_to_jiffies(10)) == 0) {
+ DSSERR("Failed to complete previous l4 transfer\n");
+ r = -EIO;
+ goto err1;
+ }
+ }
+
+ dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
+ &l4_data, DSI_VC_IRQ_PACKET_SENT);
+
+ return 0;
+err1:
+ dsi_unregister_isr_vc(dsidev, channel, dsi_packet_sent_handler_l4,
+ &l4_data, DSI_VC_IRQ_PACKET_SENT);
+err0:
+ return r;
+}
+
+static int dsi_sync_vc(struct platform_device *dsidev, int channel)
+{
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
+
+ WARN_ON(!dsi_bus_is_locked(dsidev));
+
+ WARN_ON(in_interrupt());
+
+ if (!dsi_vc_is_enabled(dsidev, channel))
+ return 0;
+
+ switch (dsi->vc[channel].mode) {
+ case DSI_VC_MODE_VP:
+ return dsi_sync_vc_vp(dsidev, channel);
+ case DSI_VC_MODE_L4:
+ return dsi_sync_vc_l4(dsidev, channel);
+ default:
+ BUG();
+ }
+}
+
+static int dsi_vc_enable(struct platform_device *dsidev, int channel,
+ bool enable)
{
DSSDBG("dsi_vc_enable channel %d, enable %d\n",
channel, enable);
enable = enable ? 1 : 0;
- REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 0, 0);
+ REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 0, 0);
- if (wait_for_bit_change(DSI_VC_CTRL(channel), 0, enable) != enable) {
+ if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel),
+ 0, enable) != enable) {
DSSERR("Failed to set dsi_vc_enable to %d\n", enable);
return -EIO;
}
@@ -2051,13 +2701,13 @@
return 0;
}
-static void dsi_vc_initial_config(int channel)
+static void dsi_vc_initial_config(struct platform_device *dsidev, int channel)
{
u32 r;
DSSDBGF("%d", channel);
- r = dsi_read_reg(DSI_VC_CTRL(channel));
+ r = dsi_read_reg(dsidev, DSI_VC_CTRL(channel));
if (FLD_GET(r, 15, 15)) /* VC_BUSY */
DSSERR("VC(%d) busy when trying to configure it!\n",
@@ -2070,85 +2720,107 @@
r = FLD_MOD(r, 1, 7, 7); /* CS_TX_EN */
r = FLD_MOD(r, 1, 8, 8); /* ECC_TX_EN */
r = FLD_MOD(r, 0, 9, 9); /* MODE_SPEED, high speed on/off */
+ if (dss_has_feature(FEAT_DSI_VC_OCP_WIDTH))
+ r = FLD_MOD(r, 3, 11, 10); /* OCP_WIDTH = 32 bit */
r = FLD_MOD(r, 4, 29, 27); /* DMA_RX_REQ_NB = no dma */
r = FLD_MOD(r, 4, 23, 21); /* DMA_TX_REQ_NB = no dma */
- dsi_write_reg(DSI_VC_CTRL(channel), r);
+ dsi_write_reg(dsidev, DSI_VC_CTRL(channel), r);
}
-static int dsi_vc_config_l4(int channel)
+static int dsi_vc_config_l4(struct platform_device *dsidev, int channel)
{
- if (dsi.vc[channel].mode == DSI_VC_MODE_L4)
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
+
+ if (dsi->vc[channel].mode == DSI_VC_MODE_L4)
return 0;
DSSDBGF("%d", channel);
- dsi_vc_enable(channel, 0);
+ dsi_sync_vc(dsidev, channel);
+
+ dsi_vc_enable(dsidev, channel, 0);
/* VC_BUSY */
- if (wait_for_bit_change(DSI_VC_CTRL(channel), 15, 0) != 0) {
+ if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), 15, 0) != 0) {
DSSERR("vc(%d) busy when trying to config for L4\n", channel);
return -EIO;
}
- REG_FLD_MOD(DSI_VC_CTRL(channel), 0, 1, 1); /* SOURCE, 0 = L4 */
+ REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 0, 1, 1); /* SOURCE, 0 = L4 */
- dsi_vc_enable(channel, 1);
+ /* DCS_CMD_ENABLE */
+ if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC))
+ REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 0, 30, 30);
- dsi.vc[channel].mode = DSI_VC_MODE_L4;
+ dsi_vc_enable(dsidev, channel, 1);
+
+ dsi->vc[channel].mode = DSI_VC_MODE_L4;
return 0;
}
-static int dsi_vc_config_vp(int channel)
+static int dsi_vc_config_vp(struct platform_device *dsidev, int channel)
{
- if (dsi.vc[channel].mode == DSI_VC_MODE_VP)
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
+
+ if (dsi->vc[channel].mode == DSI_VC_MODE_VP)
return 0;
DSSDBGF("%d", channel);
- dsi_vc_enable(channel, 0);
+ dsi_sync_vc(dsidev, channel);
+
+ dsi_vc_enable(dsidev, channel, 0);
/* VC_BUSY */
- if (wait_for_bit_change(DSI_VC_CTRL(channel), 15, 0) != 0) {
+ if (wait_for_bit_change(dsidev, DSI_VC_CTRL(channel), 15, 0) != 0) {
DSSERR("vc(%d) busy when trying to config for VP\n", channel);
return -EIO;
}
- REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 1, 1); /* SOURCE, 1 = video port */
+ /* SOURCE, 1 = video port */
+ REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 1, 1);
- dsi_vc_enable(channel, 1);
+ /* DCS_CMD_ENABLE */
+ if (dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC))
+ REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 30, 30);
- dsi.vc[channel].mode = DSI_VC_MODE_VP;
+ dsi_vc_enable(dsidev, channel, 1);
+
+ dsi->vc[channel].mode = DSI_VC_MODE_VP;
return 0;
}
-void omapdss_dsi_vc_enable_hs(int channel, bool enable)
+void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
+ bool enable)
{
+ struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
+
DSSDBG("dsi_vc_enable_hs(%d, %d)\n", channel, enable);
- WARN_ON(!dsi_bus_is_locked());
+ WARN_ON(!dsi_bus_is_locked(dsidev));
- dsi_vc_enable(channel, 0);
- dsi_if_enable(0);
+ dsi_vc_enable(dsidev, channel, 0);
+ dsi_if_enable(dsidev, 0);
- REG_FLD_MOD(DSI_VC_CTRL(channel), enable, 9, 9);
+ REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), enable, 9, 9);
- dsi_vc_enable(channel, 1);
- dsi_if_enable(1);
+ dsi_vc_enable(dsidev, channel, 1);
+ dsi_if_enable(dsidev, 1);
- dsi_force_tx_stop_mode_io();
+ dsi_force_tx_stop_mode_io(dsidev);
}
EXPORT_SYMBOL(omapdss_dsi_vc_enable_hs);
-static void dsi_vc_flush_long_data(int channel)
+static void dsi_vc_flush_long_data(struct platform_device *dsidev, int channel)
{
- while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
+ while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
u32 val;
- val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
+ val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
DSSDBG("\t\tb1 %#02x b2 %#02x b3 %#02x b4 %#02x\n",
(val >> 0) & 0xff,
(val >> 8) & 0xff,
@@ -2194,13 +2866,14 @@
DSSERR("\t\tDSI Protocol Violation\n");
}
-static u16 dsi_vc_flush_receive_data(int channel)
+static u16 dsi_vc_flush_receive_data(struct platform_device *dsidev,
+ int channel)
{
/* RX_FIFO_NOT_EMPTY */
- while (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
+ while (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
u32 val;
u8 dt;
- val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
+ val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
DSSERR("\trawval %#08x\n", val);
dt = FLD_GET(val, 5, 0);
if (dt == DSI_DT_RX_ACK_WITH_ERR) {
@@ -2215,7 +2888,7 @@
} else if (dt == DSI_DT_RX_DCS_LONG_READ) {
DSSERR("\tDCS long response, len %d\n",
FLD_GET(val, 23, 8));
- dsi_vc_flush_long_data(channel);
+ dsi_vc_flush_long_data(dsidev, channel);
} else {
DSSERR("\tunknown datatype 0x%02x\n", dt);
}
@@ -2223,40 +2896,44 @@
return 0;
}
-static int dsi_vc_send_bta(int channel)
+static int dsi_vc_send_bta(struct platform_device *dsidev, int channel)
{
- if (dsi.debug_write || dsi.debug_read)
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
+
+ if (dsi->debug_write || dsi->debug_read)
DSSDBG("dsi_vc_send_bta %d\n", channel);
- WARN_ON(!dsi_bus_is_locked());
+ WARN_ON(!dsi_bus_is_locked(dsidev));
- if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) { /* RX_FIFO_NOT_EMPTY */
+ /* RX_FIFO_NOT_EMPTY */
+ if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
DSSERR("rx fifo not empty when sending BTA, dumping data:\n");
- dsi_vc_flush_receive_data(channel);
+ dsi_vc_flush_receive_data(dsidev, channel);
}
- REG_FLD_MOD(DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
+ REG_FLD_MOD(dsidev, DSI_VC_CTRL(channel), 1, 6, 6); /* BTA_EN */
return 0;
}
-int dsi_vc_send_bta_sync(int channel)
+int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel)
{
+ struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
DECLARE_COMPLETION_ONSTACK(completion);
int r = 0;
u32 err;
- r = dsi_register_isr_vc(channel, dsi_completion_handler,
+ r = dsi_register_isr_vc(dsidev, channel, dsi_completion_handler,
&completion, DSI_VC_IRQ_BTA);
if (r)
goto err0;
- r = dsi_register_isr(dsi_completion_handler, &completion,
+ r = dsi_register_isr(dsidev, dsi_completion_handler, &completion,
DSI_IRQ_ERROR_MASK);
if (r)
goto err1;
- r = dsi_vc_send_bta(channel);
+ r = dsi_vc_send_bta(dsidev, channel);
if (r)
goto err2;
@@ -2267,41 +2944,42 @@
goto err2;
}
- err = dsi_get_errors();
+ err = dsi_get_errors(dsidev);
if (err) {
DSSERR("Error while sending BTA: %x\n", err);
r = -EIO;
goto err2;
}
err2:
- dsi_unregister_isr(dsi_completion_handler, &completion,
+ dsi_unregister_isr(dsidev, dsi_completion_handler, &completion,
DSI_IRQ_ERROR_MASK);
err1:
- dsi_unregister_isr_vc(channel, dsi_completion_handler,
+ dsi_unregister_isr_vc(dsidev, channel, dsi_completion_handler,
&completion, DSI_VC_IRQ_BTA);
err0:
return r;
}
EXPORT_SYMBOL(dsi_vc_send_bta_sync);
-static inline void dsi_vc_write_long_header(int channel, u8 data_type,
- u16 len, u8 ecc)
+static inline void dsi_vc_write_long_header(struct platform_device *dsidev,
+ int channel, u8 data_type, u16 len, u8 ecc)
{
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
u32 val;
u8 data_id;
- WARN_ON(!dsi_bus_is_locked());
+ WARN_ON(!dsi_bus_is_locked(dsidev));
- data_id = data_type | dsi.vc[channel].vc_id << 6;
+ data_id = data_type | dsi->vc[channel].vc_id << 6;
val = FLD_VAL(data_id, 7, 0) | FLD_VAL(len, 23, 8) |
FLD_VAL(ecc, 31, 24);
- dsi_write_reg(DSI_VC_LONG_PACKET_HEADER(channel), val);
+ dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_HEADER(channel), val);
}
-static inline void dsi_vc_write_long_payload(int channel,
- u8 b1, u8 b2, u8 b3, u8 b4)
+static inline void dsi_vc_write_long_payload(struct platform_device *dsidev,
+ int channel, u8 b1, u8 b2, u8 b3, u8 b4)
{
u32 val;
@@ -2310,34 +2988,35 @@
/* DSSDBG("\twriting %02x, %02x, %02x, %02x (%#010x)\n",
b1, b2, b3, b4, val); */
- dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
+ dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_PAYLOAD(channel), val);
}
-static int dsi_vc_send_long(int channel, u8 data_type, u8 *data, u16 len,
- u8 ecc)
+static int dsi_vc_send_long(struct platform_device *dsidev, int channel,
+ u8 data_type, u8 *data, u16 len, u8 ecc)
{
/*u32 val; */
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
int i;
u8 *p;
int r = 0;
u8 b1, b2, b3, b4;
- if (dsi.debug_write)
+ if (dsi->debug_write)
DSSDBG("dsi_vc_send_long, %d bytes\n", len);
/* len + header */
- if (dsi.vc[channel].fifo_size * 32 * 4 < len + 4) {
+ if (dsi->vc[channel].fifo_size * 32 * 4 < len + 4) {
DSSERR("unable to send long packet: packet too long.\n");
return -EINVAL;
}
- dsi_vc_config_l4(channel);
+ dsi_vc_config_l4(dsidev, channel);
- dsi_vc_write_long_header(channel, data_type, len, ecc);
+ dsi_vc_write_long_header(dsidev, channel, data_type, len, ecc);
p = data;
for (i = 0; i < len >> 2; i++) {
- if (dsi.debug_write)
+ if (dsi->debug_write)
DSSDBG("\tsending full packet %d\n", i);
b1 = *p++;
@@ -2345,14 +3024,14 @@
b3 = *p++;
b4 = *p++;
- dsi_vc_write_long_payload(channel, b1, b2, b3, b4);
+ dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, b4);
}
i = len % 4;
if (i) {
b1 = 0; b2 = 0; b3 = 0;
- if (dsi.debug_write)
+ if (dsi->debug_write)
DSSDBG("\tsending remainder bytes %d\n", i);
switch (i) {
@@ -2370,62 +3049,69 @@
break;
}
- dsi_vc_write_long_payload(channel, b1, b2, b3, 0);
+ dsi_vc_write_long_payload(dsidev, channel, b1, b2, b3, 0);
}
return r;
}
-static int dsi_vc_send_short(int channel, u8 data_type, u16 data, u8 ecc)
+static int dsi_vc_send_short(struct platform_device *dsidev, int channel,
+ u8 data_type, u16 data, u8 ecc)
{
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
u32 r;
u8 data_id;
- WARN_ON(!dsi_bus_is_locked());
+ WARN_ON(!dsi_bus_is_locked(dsidev));
- if (dsi.debug_write)
+ if (dsi->debug_write)
DSSDBG("dsi_vc_send_short(ch%d, dt %#x, b1 %#x, b2 %#x)\n",
channel,
data_type, data & 0xff, (data >> 8) & 0xff);
- dsi_vc_config_l4(channel);
+ dsi_vc_config_l4(dsidev, channel);
- if (FLD_GET(dsi_read_reg(DSI_VC_CTRL(channel)), 16, 16)) {
+ if (FLD_GET(dsi_read_reg(dsidev, DSI_VC_CTRL(channel)), 16, 16)) {
DSSERR("ERROR FIFO FULL, aborting transfer\n");
return -EINVAL;
}
- data_id = data_type | dsi.vc[channel].vc_id << 6;
+ data_id = data_type | dsi->vc[channel].vc_id << 6;
r = (data_id << 0) | (data << 8) | (ecc << 24);
- dsi_write_reg(DSI_VC_SHORT_PACKET_HEADER(channel), r);
+ dsi_write_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel), r);
return 0;
}
-int dsi_vc_send_null(int channel)
+int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel)
{
+ struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
u8 nullpkg[] = {0, 0, 0, 0};
- return dsi_vc_send_long(channel, DSI_DT_NULL_PACKET, nullpkg, 4, 0);
+
+ return dsi_vc_send_long(dsidev, channel, DSI_DT_NULL_PACKET, nullpkg,
+ 4, 0);
}
EXPORT_SYMBOL(dsi_vc_send_null);
-int dsi_vc_dcs_write_nosync(int channel, u8 *data, int len)
+int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
+ u8 *data, int len)
{
+ struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
int r;
BUG_ON(len == 0);
if (len == 1) {
- r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_0,
+ r = dsi_vc_send_short(dsidev, channel, DSI_DT_DCS_SHORT_WRITE_0,
data[0], 0);
} else if (len == 2) {
- r = dsi_vc_send_short(channel, DSI_DT_DCS_SHORT_WRITE_1,
+ r = dsi_vc_send_short(dsidev, channel, DSI_DT_DCS_SHORT_WRITE_1,
data[0] | (data[1] << 8), 0);
} else {
/* 0x39 = DCS Long Write */
- r = dsi_vc_send_long(channel, DSI_DT_DCS_LONG_WRITE,
+ r = dsi_vc_send_long(dsidev, channel, DSI_DT_DCS_LONG_WRITE,
data, len, 0);
}
@@ -2433,21 +3119,24 @@
}
EXPORT_SYMBOL(dsi_vc_dcs_write_nosync);
-int dsi_vc_dcs_write(int channel, u8 *data, int len)
+int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
+ int len)
{
+ struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
int r;
- r = dsi_vc_dcs_write_nosync(channel, data, len);
+ r = dsi_vc_dcs_write_nosync(dssdev, channel, data, len);
if (r)
goto err;
- r = dsi_vc_send_bta_sync(channel);
+ r = dsi_vc_send_bta_sync(dssdev, channel);
if (r)
goto err;
- if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) { /* RX_FIFO_NOT_EMPTY */
+ /* RX_FIFO_NOT_EMPTY */
+ if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20)) {
DSSERR("rx fifo not empty after write, dumping data:\n");
- dsi_vc_flush_receive_data(channel);
+ dsi_vc_flush_receive_data(dsidev, channel);
r = -EIO;
goto err;
}
@@ -2460,47 +3149,51 @@
}
EXPORT_SYMBOL(dsi_vc_dcs_write);
-int dsi_vc_dcs_write_0(int channel, u8 dcs_cmd)
+int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd)
{
- return dsi_vc_dcs_write(channel, &dcs_cmd, 1);
+ return dsi_vc_dcs_write(dssdev, channel, &dcs_cmd, 1);
}
EXPORT_SYMBOL(dsi_vc_dcs_write_0);
-int dsi_vc_dcs_write_1(int channel, u8 dcs_cmd, u8 param)
+int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
+ u8 param)
{
u8 buf[2];
buf[0] = dcs_cmd;
buf[1] = param;
- return dsi_vc_dcs_write(channel, buf, 2);
+ return dsi_vc_dcs_write(dssdev, channel, buf, 2);
}
EXPORT_SYMBOL(dsi_vc_dcs_write_1);
-int dsi_vc_dcs_read(int channel, u8 dcs_cmd, u8 *buf, int buflen)
+int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
+ u8 *buf, int buflen)
{
+ struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
u32 val;
u8 dt;
int r;
- if (dsi.debug_read)
+ if (dsi->debug_read)
DSSDBG("dsi_vc_dcs_read(ch%d, dcs_cmd %x)\n", channel, dcs_cmd);
- r = dsi_vc_send_short(channel, DSI_DT_DCS_READ, dcs_cmd, 0);
+ r = dsi_vc_send_short(dsidev, channel, DSI_DT_DCS_READ, dcs_cmd, 0);
if (r)
goto err;
- r = dsi_vc_send_bta_sync(channel);
+ r = dsi_vc_send_bta_sync(dssdev, channel);
if (r)
goto err;
/* RX_FIFO_NOT_EMPTY */
- if (REG_GET(DSI_VC_CTRL(channel), 20, 20) == 0) {
+ if (REG_GET(dsidev, DSI_VC_CTRL(channel), 20, 20) == 0) {
DSSERR("RX fifo empty when trying to read.\n");
r = -EIO;
goto err;
}
- val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
- if (dsi.debug_read)
+ val = dsi_read_reg(dsidev, DSI_VC_SHORT_PACKET_HEADER(channel));
+ if (dsi->debug_read)
DSSDBG("\theader: %08x\n", val);
dt = FLD_GET(val, 5, 0);
if (dt == DSI_DT_RX_ACK_WITH_ERR) {
@@ -2511,7 +3204,7 @@
} else if (dt == DSI_DT_RX_SHORT_READ_1) {
u8 data = FLD_GET(val, 15, 8);
- if (dsi.debug_read)
+ if (dsi->debug_read)
DSSDBG("\tDCS short response, 1 byte: %02x\n", data);
if (buflen < 1) {
@@ -2524,7 +3217,7 @@
return 1;
} else if (dt == DSI_DT_RX_SHORT_READ_2) {
u16 data = FLD_GET(val, 23, 8);
- if (dsi.debug_read)
+ if (dsi->debug_read)
DSSDBG("\tDCS short response, 2 byte: %04x\n", data);
if (buflen < 2) {
@@ -2539,7 +3232,7 @@
} else if (dt == DSI_DT_RX_DCS_LONG_READ) {
int w;
int len = FLD_GET(val, 23, 8);
- if (dsi.debug_read)
+ if (dsi->debug_read)
DSSDBG("\tDCS long response, len %d\n", len);
if (len > buflen) {
@@ -2550,8 +3243,9 @@
/* two byte checksum ends the packet, not included in len */
for (w = 0; w < len + 2;) {
int b;
- val = dsi_read_reg(DSI_VC_SHORT_PACKET_HEADER(channel));
- if (dsi.debug_read)
+ val = dsi_read_reg(dsidev,
+ DSI_VC_SHORT_PACKET_HEADER(channel));
+ if (dsi->debug_read)
DSSDBG("\t\t%02x %02x %02x %02x\n",
(val >> 0) & 0xff,
(val >> 8) & 0xff,
@@ -2582,11 +3276,12 @@
}
EXPORT_SYMBOL(dsi_vc_dcs_read);
-int dsi_vc_dcs_read_1(int channel, u8 dcs_cmd, u8 *data)
+int dsi_vc_dcs_read_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
+ u8 *data)
{
int r;
- r = dsi_vc_dcs_read(channel, dcs_cmd, data, 1);
+ r = dsi_vc_dcs_read(dssdev, channel, dcs_cmd, data, 1);
if (r < 0)
return r;
@@ -2598,12 +3293,13 @@
}
EXPORT_SYMBOL(dsi_vc_dcs_read_1);
-int dsi_vc_dcs_read_2(int channel, u8 dcs_cmd, u8 *data1, u8 *data2)
+int dsi_vc_dcs_read_2(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
+ u8 *data1, u8 *data2)
{
u8 buf[2];
int r;
- r = dsi_vc_dcs_read(channel, dcs_cmd, buf, 2);
+ r = dsi_vc_dcs_read(dssdev, channel, dcs_cmd, buf, 2);
if (r < 0)
return r;
@@ -2618,14 +3314,94 @@
}
EXPORT_SYMBOL(dsi_vc_dcs_read_2);
-int dsi_vc_set_max_rx_packet_size(int channel, u16 len)
+int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
+ u16 len)
{
- return dsi_vc_send_short(channel, DSI_DT_SET_MAX_RET_PKG_SIZE,
+ struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
+
+ return dsi_vc_send_short(dsidev, channel, DSI_DT_SET_MAX_RET_PKG_SIZE,
len, 0);
}
EXPORT_SYMBOL(dsi_vc_set_max_rx_packet_size);
-static void dsi_set_lp_rx_timeout(unsigned ticks, bool x4, bool x16)
+static int dsi_enter_ulps(struct platform_device *dsidev)
+{
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
+ DECLARE_COMPLETION_ONSTACK(completion);
+ int r;
+
+ DSSDBGF();
+
+ WARN_ON(!dsi_bus_is_locked(dsidev));
+
+ WARN_ON(dsi->ulps_enabled);
+
+ if (dsi->ulps_enabled)
+ return 0;
+
+ if (REG_GET(dsidev, DSI_CLK_CTRL, 13, 13)) {
+ DSSERR("DDR_CLK_ALWAYS_ON enabled when entering ULPS\n");
+ return -EIO;
+ }
+
+ dsi_sync_vc(dsidev, 0);
+ dsi_sync_vc(dsidev, 1);
+ dsi_sync_vc(dsidev, 2);
+ dsi_sync_vc(dsidev, 3);
+
+ dsi_force_tx_stop_mode_io(dsidev);
+
+ dsi_vc_enable(dsidev, 0, false);
+ dsi_vc_enable(dsidev, 1, false);
+ dsi_vc_enable(dsidev, 2, false);
+ dsi_vc_enable(dsidev, 3, false);
+
+ if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 16, 16)) { /* HS_BUSY */
+ DSSERR("HS busy when enabling ULPS\n");
+ return -EIO;
+ }
+
+ if (REG_GET(dsidev, DSI_COMPLEXIO_CFG2, 17, 17)) { /* LP_BUSY */
+ DSSERR("LP busy when enabling ULPS\n");
+ return -EIO;
+ }
+
+ r = dsi_register_isr_cio(dsidev, dsi_completion_handler, &completion,
+ DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
+ if (r)
+ return r;
+
+ /* Assert TxRequestEsc for data lanes and TxUlpsClk for clk lane */
+ /* LANEx_ULPS_SIG2 */
+ REG_FLD_MOD(dsidev, DSI_COMPLEXIO_CFG2, (1 << 0) | (1 << 1) | (1 << 2),
+ 7, 5);
+
+ if (wait_for_completion_timeout(&completion,
+ msecs_to_jiffies(1000)) == 0) {
+ DSSERR("ULPS enable timeout\n");
+ r = -EIO;
+ goto err;
+ }
+
+ dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
+ DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
+
+ dsi_cio_power(dsidev, DSI_COMPLEXIO_POWER_ULPS);
+
+ dsi_if_enable(dsidev, false);
+
+ dsi->ulps_enabled = true;
+
+ return 0;
+
+err:
+ dsi_unregister_isr_cio(dsidev, dsi_completion_handler, &completion,
+ DSI_CIO_IRQ_ULPSACTIVENOT_ALL0);
+ return r;
+}
+
+static void dsi_set_lp_rx_timeout(struct platform_device *dsidev,
+ unsigned ticks, bool x4, bool x16)
{
unsigned long fck;
unsigned long total_ticks;
@@ -2634,14 +3410,14 @@
BUG_ON(ticks > 0x1fff);
/* ticks in DSI_FCK */
- fck = dsi_fclk_rate();
+ fck = dsi_fclk_rate(dsidev);
- r = dsi_read_reg(DSI_TIMING2);
+ r = dsi_read_reg(dsidev, DSI_TIMING2);
r = FLD_MOD(r, 1, 15, 15); /* LP_RX_TO */
r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* LP_RX_TO_X16 */
r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* LP_RX_TO_X4 */
r = FLD_MOD(r, ticks, 12, 0); /* LP_RX_COUNTER */
- dsi_write_reg(DSI_TIMING2, r);
+ dsi_write_reg(dsidev, DSI_TIMING2, r);
total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
@@ -2651,7 +3427,8 @@
(total_ticks * 1000) / (fck / 1000 / 1000));
}
-static void dsi_set_ta_timeout(unsigned ticks, bool x8, bool x16)
+static void dsi_set_ta_timeout(struct platform_device *dsidev, unsigned ticks,
+ bool x8, bool x16)
{
unsigned long fck;
unsigned long total_ticks;
@@ -2660,14 +3437,14 @@
BUG_ON(ticks > 0x1fff);
/* ticks in DSI_FCK */
- fck = dsi_fclk_rate();
+ fck = dsi_fclk_rate(dsidev);
- r = dsi_read_reg(DSI_TIMING1);
+ r = dsi_read_reg(dsidev, DSI_TIMING1);
r = FLD_MOD(r, 1, 31, 31); /* TA_TO */
r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* TA_TO_X16 */
r = FLD_MOD(r, x8 ? 1 : 0, 29, 29); /* TA_TO_X8 */
r = FLD_MOD(r, ticks, 28, 16); /* TA_TO_COUNTER */
- dsi_write_reg(DSI_TIMING1, r);
+ dsi_write_reg(dsidev, DSI_TIMING1, r);
total_ticks = ticks * (x16 ? 16 : 1) * (x8 ? 8 : 1);
@@ -2677,7 +3454,8 @@
(total_ticks * 1000) / (fck / 1000 / 1000));
}
-static void dsi_set_stop_state_counter(unsigned ticks, bool x4, bool x16)
+static void dsi_set_stop_state_counter(struct platform_device *dsidev,
+ unsigned ticks, bool x4, bool x16)
{
unsigned long fck;
unsigned long total_ticks;
@@ -2686,14 +3464,14 @@
BUG_ON(ticks > 0x1fff);
/* ticks in DSI_FCK */
- fck = dsi_fclk_rate();
+ fck = dsi_fclk_rate(dsidev);
- r = dsi_read_reg(DSI_TIMING1);
+ r = dsi_read_reg(dsidev, DSI_TIMING1);
r = FLD_MOD(r, 1, 15, 15); /* FORCE_TX_STOP_MODE_IO */
r = FLD_MOD(r, x16 ? 1 : 0, 14, 14); /* STOP_STATE_X16_IO */
r = FLD_MOD(r, x4 ? 1 : 0, 13, 13); /* STOP_STATE_X4_IO */
r = FLD_MOD(r, ticks, 12, 0); /* STOP_STATE_COUNTER_IO */
- dsi_write_reg(DSI_TIMING1, r);
+ dsi_write_reg(dsidev, DSI_TIMING1, r);
total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
@@ -2703,7 +3481,8 @@
(total_ticks * 1000) / (fck / 1000 / 1000));
}
-static void dsi_set_hs_tx_timeout(unsigned ticks, bool x4, bool x16)
+static void dsi_set_hs_tx_timeout(struct platform_device *dsidev,
+ unsigned ticks, bool x4, bool x16)
{
unsigned long fck;
unsigned long total_ticks;
@@ -2712,14 +3491,14 @@
BUG_ON(ticks > 0x1fff);
/* ticks in TxByteClkHS */
- fck = dsi_get_txbyteclkhs();
+ fck = dsi_get_txbyteclkhs(dsidev);
- r = dsi_read_reg(DSI_TIMING2);
+ r = dsi_read_reg(dsidev, DSI_TIMING2);
r = FLD_MOD(r, 1, 31, 31); /* HS_TX_TO */
r = FLD_MOD(r, x16 ? 1 : 0, 30, 30); /* HS_TX_TO_X16 */
r = FLD_MOD(r, x4 ? 1 : 0, 29, 29); /* HS_TX_TO_X8 (4 really) */
r = FLD_MOD(r, ticks, 28, 16); /* HS_TX_TO_COUNTER */
- dsi_write_reg(DSI_TIMING2, r);
+ dsi_write_reg(dsidev, DSI_TIMING2, r);
total_ticks = ticks * (x16 ? 16 : 1) * (x4 ? 4 : 1);
@@ -2730,24 +3509,25 @@
}
static int dsi_proto_config(struct omap_dss_device *dssdev)
{
+ struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
u32 r;
int buswidth = 0;
- dsi_config_tx_fifo(DSI_FIFO_SIZE_32,
+ dsi_config_tx_fifo(dsidev, DSI_FIFO_SIZE_32,
DSI_FIFO_SIZE_32,
DSI_FIFO_SIZE_32,
DSI_FIFO_SIZE_32);
- dsi_config_rx_fifo(DSI_FIFO_SIZE_32,
+ dsi_config_rx_fifo(dsidev, DSI_FIFO_SIZE_32,
DSI_FIFO_SIZE_32,
DSI_FIFO_SIZE_32,
DSI_FIFO_SIZE_32);
/* XXX what values for the timeouts? */
- dsi_set_stop_state_counter(0x1000, false, false);
- dsi_set_ta_timeout(0x1fff, true, true);
- dsi_set_lp_rx_timeout(0x1fff, true, true);
- dsi_set_hs_tx_timeout(0x1fff, true, true);
+ dsi_set_stop_state_counter(dsidev, 0x1000, false, false);
+ dsi_set_ta_timeout(dsidev, 0x1fff, true, true);
+ dsi_set_lp_rx_timeout(dsidev, 0x1fff, true, true);
+ dsi_set_hs_tx_timeout(dsidev, 0x1fff, true, true);
switch (dssdev->ctrl.pixel_size) {
case 16:
@@ -2763,7 +3543,7 @@
BUG();
}
- r = dsi_read_reg(DSI_CTRL);
+ r = dsi_read_reg(dsidev, DSI_CTRL);
r = FLD_MOD(r, 1, 1, 1); /* CS_RX_EN */
r = FLD_MOD(r, 1, 2, 2); /* ECC_RX_EN */
r = FLD_MOD(r, 1, 3, 3); /* TX_FIFO_ARBITRATION */
@@ -2773,21 +3553,25 @@
r = FLD_MOD(r, 2, 13, 12); /* LINE_BUFFER, 2 lines */
r = FLD_MOD(r, 1, 14, 14); /* TRIGGER_RESET_MODE */
r = FLD_MOD(r, 1, 19, 19); /* EOT_ENABLE */
- r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */
- r = FLD_MOD(r, 0, 25, 25); /* DCS_CMD_CODE, 1=start, 0=continue */
+ if (!dss_has_feature(FEAT_DSI_DCS_CMD_CONFIG_VC)) {
+ r = FLD_MOD(r, 1, 24, 24); /* DCS_CMD_ENABLE */
+ /* DCS_CMD_CODE, 1=start, 0=continue */
+ r = FLD_MOD(r, 0, 25, 25);
+ }
- dsi_write_reg(DSI_CTRL, r);
+ dsi_write_reg(dsidev, DSI_CTRL, r);
- dsi_vc_initial_config(0);
- dsi_vc_initial_config(1);
- dsi_vc_initial_config(2);
- dsi_vc_initial_config(3);
+ dsi_vc_initial_config(dsidev, 0);
+ dsi_vc_initial_config(dsidev, 1);
+ dsi_vc_initial_config(dsidev, 2);
+ dsi_vc_initial_config(dsidev, 3);
return 0;
}
static void dsi_proto_timings(struct omap_dss_device *dssdev)
{
+ struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
unsigned tlpx, tclk_zero, tclk_prepare, tclk_trail;
unsigned tclk_pre, tclk_post;
unsigned ths_prepare, ths_prepare_ths_zero, ths_zero;
@@ -2797,32 +3581,27 @@
unsigned ths_eot;
u32 r;
- r = dsi_read_reg(DSI_DSIPHY_CFG0);
+ r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG0);
ths_prepare = FLD_GET(r, 31, 24);
ths_prepare_ths_zero = FLD_GET(r, 23, 16);
ths_zero = ths_prepare_ths_zero - ths_prepare;
ths_trail = FLD_GET(r, 15, 8);
ths_exit = FLD_GET(r, 7, 0);
- r = dsi_read_reg(DSI_DSIPHY_CFG1);
+ r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG1);
tlpx = FLD_GET(r, 22, 16) * 2;
tclk_trail = FLD_GET(r, 15, 8);
tclk_zero = FLD_GET(r, 7, 0);
- r = dsi_read_reg(DSI_DSIPHY_CFG2);
+ r = dsi_read_reg(dsidev, DSI_DSIPHY_CFG2);
tclk_prepare = FLD_GET(r, 7, 0);
/* min 8*UI */
tclk_pre = 20;
/* min 60ns + 52*UI */
- tclk_post = ns2ddr(60) + 26;
+ tclk_post = ns2ddr(dsidev, 60) + 26;
- /* ths_eot is 2 for 2 datalanes and 4 for 1 datalane */
- if (dssdev->phy.dsi.data1_lane != 0 &&
- dssdev->phy.dsi.data2_lane != 0)
- ths_eot = 2;
- else
- ths_eot = 4;
+ ths_eot = DIV_ROUND_UP(4, dsi_get_num_data_lanes_dssdev(dssdev));
ddr_clk_pre = DIV_ROUND_UP(tclk_pre + tlpx + tclk_zero + tclk_prepare,
4);
@@ -2831,10 +3610,10 @@
BUG_ON(ddr_clk_pre == 0 || ddr_clk_pre > 255);
BUG_ON(ddr_clk_post == 0 || ddr_clk_post > 255);
- r = dsi_read_reg(DSI_CLK_TIMING);
+ r = dsi_read_reg(dsidev, DSI_CLK_TIMING);
r = FLD_MOD(r, ddr_clk_pre, 15, 8);
r = FLD_MOD(r, ddr_clk_post, 7, 0);
- dsi_write_reg(DSI_CLK_TIMING, r);
+ dsi_write_reg(dsidev, DSI_CLK_TIMING, r);
DSSDBG("ddr_clk_pre %u, ddr_clk_post %u\n",
ddr_clk_pre,
@@ -2848,7 +3627,7 @@
r = FLD_VAL(enter_hs_mode_lat, 31, 16) |
FLD_VAL(exit_hs_mode_lat, 15, 0);
- dsi_write_reg(DSI_VM_TIMING7, r);
+ dsi_write_reg(dsidev, DSI_VM_TIMING7, r);
DSSDBG("enter_hs_mode_lat %u, exit_hs_mode_lat %u\n",
enter_hs_mode_lat, exit_hs_mode_lat);
@@ -2858,25 +3637,27 @@
#define DSI_DECL_VARS \
int __dsi_cb = 0; u32 __dsi_cv = 0;
-#define DSI_FLUSH(ch) \
+#define DSI_FLUSH(dsidev, ch) \
if (__dsi_cb > 0) { \
/*DSSDBG("sending long packet %#010x\n", __dsi_cv);*/ \
- dsi_write_reg(DSI_VC_LONG_PACKET_PAYLOAD(ch), __dsi_cv); \
+ dsi_write_reg(dsidev, DSI_VC_LONG_PACKET_PAYLOAD(ch), __dsi_cv); \
__dsi_cb = __dsi_cv = 0; \
}
-#define DSI_PUSH(ch, data) \
+#define DSI_PUSH(dsidev, ch, data) \
do { \
__dsi_cv |= (data) << (__dsi_cb * 8); \
/*DSSDBG("cv = %#010x, cb = %d\n", __dsi_cv, __dsi_cb);*/ \
if (++__dsi_cb > 3) \
- DSI_FLUSH(ch); \
+ DSI_FLUSH(dsidev, ch); \
} while (0)
static int dsi_update_screen_l4(struct omap_dss_device *dssdev,
int x, int y, int w, int h)
{
/* Note: supports only 24bit colors in 32bit container */
+ struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
int first = 1;
int fifo_stalls = 0;
int max_dsi_packet_size;
@@ -2915,7 +3696,7 @@
* in fifo */
/* When using CPU, max long packet size is TX buffer size */
- max_dsi_packet_size = dsi.vc[0].fifo_size * 32 * 4;
+ max_dsi_packet_size = dsi->vc[0].fifo_size * 32 * 4;
/* we seem to get better perf if we divide the tx fifo to half,
and while the other half is being sent, we fill the other half
@@ -2944,35 +3725,36 @@
#if 1
/* using fifo not empty */
/* TX_FIFO_NOT_EMPTY */
- while (FLD_GET(dsi_read_reg(DSI_VC_CTRL(0)), 5, 5)) {
+ while (FLD_GET(dsi_read_reg(dsidev, DSI_VC_CTRL(0)), 5, 5)) {
fifo_stalls++;
if (fifo_stalls > 0xfffff) {
DSSERR("fifo stalls overflow, pixels left %d\n",
pixels_left);
- dsi_if_enable(0);
+ dsi_if_enable(dsidev, 0);
return -EIO;
}
udelay(1);
}
#elif 1
/* using fifo emptiness */
- while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 <
+ while ((REG_GET(dsidev, DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 <
max_dsi_packet_size) {
fifo_stalls++;
if (fifo_stalls > 0xfffff) {
DSSERR("fifo stalls overflow, pixels left %d\n",
pixels_left);
- dsi_if_enable(0);
+ dsi_if_enable(dsidev, 0);
return -EIO;
}
}
#else
- while ((REG_GET(DSI_TX_FIFO_VC_EMPTINESS, 7, 0)+1)*4 == 0) {
+ while ((REG_GET(dsidev, DSI_TX_FIFO_VC_EMPTINESS,
+ 7, 0) + 1) * 4 == 0) {
fifo_stalls++;
if (fifo_stalls > 0xfffff) {
DSSERR("fifo stalls overflow, pixels left %d\n",
pixels_left);
- dsi_if_enable(0);
+ dsi_if_enable(dsidev, 0);
return -EIO;
}
}
@@ -2981,17 +3763,17 @@
pixels_left -= pixels;
- dsi_vc_write_long_header(0, DSI_DT_DCS_LONG_WRITE,
+ dsi_vc_write_long_header(dsidev, 0, DSI_DT_DCS_LONG_WRITE,
1 + pixels * bytespp, 0);
- DSI_PUSH(0, dcs_cmd);
+ DSI_PUSH(dsidev, 0, dcs_cmd);
while (pixels-- > 0) {
u32 pix = __raw_readl(data++);
- DSI_PUSH(0, (pix >> 16) & 0xff);
- DSI_PUSH(0, (pix >> 8) & 0xff);
- DSI_PUSH(0, (pix >> 0) & 0xff);
+ DSI_PUSH(dsidev, 0, (pix >> 16) & 0xff);
+ DSI_PUSH(dsidev, 0, (pix >> 8) & 0xff);
+ DSI_PUSH(dsidev, 0, (pix >> 0) & 0xff);
current_x++;
if (current_x == x+w) {
@@ -3000,7 +3782,7 @@
}
}
- DSI_FLUSH(0);
+ DSI_FLUSH(dsidev, 0);
}
return 0;
@@ -3009,6 +3791,8 @@
static void dsi_update_screen_dispc(struct omap_dss_device *dssdev,
u16 x, u16 y, u16 w, u16 h)
{
+ struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
unsigned bytespp;
unsigned bytespl;
unsigned bytespf;
@@ -3017,16 +3801,13 @@
unsigned packet_len;
u32 l;
int r;
- const unsigned channel = dsi.update_channel;
- /* line buffer is 1024 x 24bits */
- /* XXX: for some reason using full buffer size causes considerable TX
- * slowdown with update sizes that fill the whole buffer */
- const unsigned line_buf_size = 1023 * 3;
+ const unsigned channel = dsi->update_channel;
+ const unsigned line_buf_size = dsi_get_line_buf_size(dsidev);
DSSDBG("dsi_update_screen_dispc(%d,%d %dx%d)\n",
x, y, w, h);
- dsi_vc_config_vp(channel);
+ dsi_vc_config_vp(dsidev, channel);
bytespp = dssdev->ctrl.pixel_size / 8;
bytespl = w * bytespp;
@@ -3047,15 +3828,16 @@
total_len += (bytespf % packet_payload) + 1;
l = FLD_VAL(total_len, 23, 0); /* TE_SIZE */
- dsi_write_reg(DSI_VC_TE(channel), l);
+ dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
- dsi_vc_write_long_header(channel, DSI_DT_DCS_LONG_WRITE, packet_len, 0);
+ dsi_vc_write_long_header(dsidev, channel, DSI_DT_DCS_LONG_WRITE,
+ packet_len, 0);
- if (dsi.te_enabled)
+ if (dsi->te_enabled)
l = FLD_MOD(l, 1, 30, 30); /* TE_EN */
else
l = FLD_MOD(l, 1, 31, 31); /* TE_START */
- dsi_write_reg(DSI_VC_TE(channel), l);
+ dsi_write_reg(dsidev, DSI_VC_TE(channel), l);
/* We put SIDLEMODE to no-idle for the duration of the transfer,
* because DSS interrupts are not capable of waking up the CPU and the
@@ -3065,23 +3847,23 @@
*/
dispc_disable_sidle();
- dsi_perf_mark_start();
+ dsi_perf_mark_start(dsidev);
- r = queue_delayed_work(dsi.workqueue, &dsi.framedone_timeout_work,
- msecs_to_jiffies(250));
+ r = schedule_delayed_work(&dsi->framedone_timeout_work,
+ msecs_to_jiffies(250));
BUG_ON(r == 0);
dss_start_update(dssdev);
- if (dsi.te_enabled) {
+ if (dsi->te_enabled) {
/* disable LP_RX_TO, so that we can receive TE. Time to wait
* for TE is longer than the timer allows */
- REG_FLD_MOD(DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
+ REG_FLD_MOD(dsidev, DSI_TIMING2, 0, 15, 15); /* LP_RX_TO */
- dsi_vc_send_bta(channel);
+ dsi_vc_send_bta(dsidev, channel);
#ifdef DSI_CATCH_MISSING_TE
- mod_timer(&dsi.te_timer, jiffies + msecs_to_jiffies(250));
+ mod_timer(&dsi->te_timer, jiffies + msecs_to_jiffies(250));
#endif
}
}
@@ -3093,41 +3875,28 @@
}
#endif
-static void dsi_framedone_bta_callback(void *data, u32 mask);
-
-static void dsi_handle_framedone(int error)
+static void dsi_handle_framedone(struct platform_device *dsidev, int error)
{
- const int channel = dsi.update_channel;
-
- dsi_unregister_isr_vc(channel, dsi_framedone_bta_callback,
- NULL, DSI_VC_IRQ_BTA);
-
- cancel_delayed_work(&dsi.framedone_timeout_work);
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
/* SIDLEMODE back to smart-idle */
dispc_enable_sidle();
- if (dsi.te_enabled) {
+ if (dsi->te_enabled) {
/* enable LP_RX_TO again after the TE */
- REG_FLD_MOD(DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
+ REG_FLD_MOD(dsidev, DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
}
- /* RX_FIFO_NOT_EMPTY */
- if (REG_GET(DSI_VC_CTRL(channel), 20, 20)) {
- DSSERR("Received error during frame transfer:\n");
- dsi_vc_flush_receive_data(channel);
- if (!error)
- error = -EIO;
- }
-
- dsi.framedone_callback(error, dsi.framedone_data);
+ dsi->framedone_callback(error, dsi->framedone_data);
if (!error)
- dsi_perf_show("DISPC");
+ dsi_perf_show(dsidev, "DISPC");
}
static void dsi_framedone_timeout_work_callback(struct work_struct *work)
{
+ struct dsi_data *dsi = container_of(work, struct dsi_data,
+ framedone_timeout_work.work);
/* XXX While extremely unlikely, we could get FRAMEDONE interrupt after
* 250ms which would conflict with this timeout work. What should be
* done is first cancel the transfer on the HW, and then cancel the
@@ -3137,70 +3906,34 @@
DSSERR("Framedone not received for 250ms!\n");
- dsi_handle_framedone(-ETIMEDOUT);
-}
-
-static void dsi_framedone_bta_callback(void *data, u32 mask)
-{
- dsi_handle_framedone(0);
-
-#ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
- dispc_fake_vsync_irq();
-#endif
+ dsi_handle_framedone(dsi->pdev, -ETIMEDOUT);
}
static void dsi_framedone_irq_callback(void *data, u32 mask)
{
- const int channel = dsi.update_channel;
- int r;
+ struct omap_dss_device *dssdev = (struct omap_dss_device *) data;
+ struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
/* Note: We get FRAMEDONE when DISPC has finished sending pixels and
* turns itself off. However, DSI still has the pixels in its buffers,
* and is sending the data.
*/
- if (dsi.te_enabled) {
- /* enable LP_RX_TO again after the TE */
- REG_FLD_MOD(DSI_TIMING2, 1, 15, 15); /* LP_RX_TO */
- }
+ __cancel_delayed_work(&dsi->framedone_timeout_work);
- /* Send BTA after the frame. We need this for the TE to work, as TE
- * trigger is only sent for BTAs without preceding packet. Thus we need
- * to BTA after the pixel packets so that next BTA will cause TE
- * trigger.
- *
- * This is not needed when TE is not in use, but we do it anyway to
- * make sure that the transfer has been completed. It would be more
- * optimal, but more complex, to wait only just before starting next
- * transfer.
- *
- * Also, as there's no interrupt telling when the transfer has been
- * done and the channel could be reconfigured, the only way is to
- * busyloop until TE_SIZE is zero. With BTA we can do this
- * asynchronously.
- * */
+ dsi_handle_framedone(dsidev, 0);
- r = dsi_register_isr_vc(channel, dsi_framedone_bta_callback,
- NULL, DSI_VC_IRQ_BTA);
- if (r) {
- DSSERR("Failed to register BTA ISR\n");
- dsi_handle_framedone(-EIO);
- return;
- }
-
- r = dsi_vc_send_bta(channel);
- if (r) {
- DSSERR("BTA after framedone failed\n");
- dsi_unregister_isr_vc(channel, dsi_framedone_bta_callback,
- NULL, DSI_VC_IRQ_BTA);
- dsi_handle_framedone(-EIO);
- }
+#ifdef CONFIG_OMAP2_DSS_FAKE_VSYNC
+ dispc_fake_vsync_irq();
+#endif
}
int omap_dsi_prepare_update(struct omap_dss_device *dssdev,
u16 *x, u16 *y, u16 *w, u16 *h,
bool enlarge_update_area)
{
+ struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
u16 dw, dh;
dssdev->driver->get_resolution(dssdev, &dw, &dh);
@@ -3220,7 +3953,7 @@
if (*w == 0 || *h == 0)
return -EINVAL;
- dsi_perf_mark_setup();
+ dsi_perf_mark_setup(dsidev);
if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
dss_setup_partial_planes(dssdev, x, y, w, h,
@@ -3237,7 +3970,10 @@
u16 x, u16 y, u16 w, u16 h,
void (*callback)(int, void *), void *data)
{
- dsi.update_channel = channel;
+ struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
+
+ dsi->update_channel = channel;
/* OMAP DSS cannot send updates of odd widths.
* omap_dsi_prepare_update() makes the widths even, but add a BUG_ON
@@ -3246,14 +3982,14 @@
BUG_ON(x % 2 == 1);
if (dssdev->manager->caps & OMAP_DSS_OVL_MGR_CAP_DISPC) {
- dsi.framedone_callback = callback;
- dsi.framedone_data = data;
+ dsi->framedone_callback = callback;
+ dsi->framedone_data = data;
- dsi.update_region.x = x;
- dsi.update_region.y = y;
- dsi.update_region.w = w;
- dsi.update_region.h = h;
- dsi.update_region.device = dssdev;
+ dsi->update_region.x = x;
+ dsi->update_region.y = y;
+ dsi->update_region.w = w;
+ dsi->update_region.h = h;
+ dsi->update_region.device = dssdev;
dsi_update_screen_dispc(dssdev, x, y, w, h);
} else {
@@ -3263,7 +3999,7 @@
if (r)
return r;
- dsi_perf_show("L4");
+ dsi_perf_show(dsidev, "L4");
callback(0, data);
}
@@ -3276,9 +4012,13 @@
static int dsi_display_init_dispc(struct omap_dss_device *dssdev)
{
int r;
+ u32 irq;
- r = omap_dispc_register_isr(dsi_framedone_irq_callback, NULL,
- DISPC_IRQ_FRAMEDONE);
+ irq = dssdev->manager->id == OMAP_DSS_CHANNEL_LCD ?
+ DISPC_IRQ_FRAMEDONE : DISPC_IRQ_FRAMEDONE2;
+
+ r = omap_dispc_register_isr(dsi_framedone_irq_callback, (void *) dssdev,
+ irq);
if (r) {
DSSERR("can't get FRAMEDONE irq\n");
return r;
@@ -3311,28 +4051,34 @@
static void dsi_display_uninit_dispc(struct omap_dss_device *dssdev)
{
- omap_dispc_unregister_isr(dsi_framedone_irq_callback, NULL,
- DISPC_IRQ_FRAMEDONE);
+ u32 irq;
+
+ irq = dssdev->manager->id == OMAP_DSS_CHANNEL_LCD ?
+ DISPC_IRQ_FRAMEDONE : DISPC_IRQ_FRAMEDONE2;
+
+ omap_dispc_unregister_isr(dsi_framedone_irq_callback, (void *) dssdev,
+ irq);
}
static int dsi_configure_dsi_clocks(struct omap_dss_device *dssdev)
{
+ struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
struct dsi_clock_info cinfo;
int r;
/* we always use DSS_CLK_SYSCK as input clock */
cinfo.use_sys_clk = true;
- cinfo.regn = dssdev->phy.dsi.div.regn;
- cinfo.regm = dssdev->phy.dsi.div.regm;
- cinfo.regm_dispc = dssdev->phy.dsi.div.regm_dispc;
- cinfo.regm_dsi = dssdev->phy.dsi.div.regm_dsi;
+ cinfo.regn = dssdev->clocks.dsi.regn;
+ cinfo.regm = dssdev->clocks.dsi.regm;
+ cinfo.regm_dispc = dssdev->clocks.dsi.regm_dispc;
+ cinfo.regm_dsi = dssdev->clocks.dsi.regm_dsi;
r = dsi_calc_clock_rates(dssdev, &cinfo);
if (r) {
DSSERR("Failed to calc dsi clocks\n");
return r;
}
- r = dsi_pll_set_clock_div(&cinfo);
+ r = dsi_pll_set_clock_div(dsidev, &cinfo);
if (r) {
DSSERR("Failed to set dsi clocks\n");
return r;
@@ -3343,14 +4089,15 @@
static int dsi_configure_dispc_clocks(struct omap_dss_device *dssdev)
{
+ struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
struct dispc_clock_info dispc_cinfo;
int r;
unsigned long long fck;
- fck = dsi_get_pll_hsdiv_dispc_rate();
+ fck = dsi_get_pll_hsdiv_dispc_rate(dsidev);
- dispc_cinfo.lck_div = dssdev->phy.dsi.div.lck_div;
- dispc_cinfo.pck_div = dssdev->phy.dsi.div.pck_div;
+ dispc_cinfo.lck_div = dssdev->clocks.dispc.channel.lck_div;
+ dispc_cinfo.pck_div = dssdev->clocks.dispc.channel.pck_div;
r = dispc_calc_clock_rates(fck, &dispc_cinfo);
if (r) {
@@ -3369,11 +4116,11 @@
static int dsi_display_init_dsi(struct omap_dss_device *dssdev)
{
+ struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
+ int dsi_module = dsi_get_dsidev_id(dsidev);
int r;
- _dsi_print_reset_status();
-
- r = dsi_pll_init(dssdev, true, true);
+ r = dsi_pll_init(dsidev, true, true);
if (r)
goto err0;
@@ -3381,8 +4128,10 @@
if (r)
goto err1;
- dss_select_dispc_clk_source(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC);
- dss_select_dsi_clk_source(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI);
+ dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src);
+ dss_select_dsi_clk_source(dsi_module, dssdev->clocks.dsi.dsi_fclk_src);
+ dss_select_lcd_clk_source(dssdev->manager->id,
+ dssdev->clocks.dispc.channel.lcd_clk_src);
DSSDBG("PLL OK\n");
@@ -3390,82 +4139,92 @@
if (r)
goto err2;
- r = dsi_complexio_init(dssdev);
+ r = dsi_cio_init(dssdev);
if (r)
goto err2;
- _dsi_print_reset_status();
+ _dsi_print_reset_status(dsidev);
dsi_proto_timings(dssdev);
dsi_set_lp_clk_divisor(dssdev);
if (1)
- _dsi_print_reset_status();
+ _dsi_print_reset_status(dsidev);
r = dsi_proto_config(dssdev);
if (r)
goto err3;
/* enable interface */
- dsi_vc_enable(0, 1);
- dsi_vc_enable(1, 1);
- dsi_vc_enable(2, 1);
- dsi_vc_enable(3, 1);
- dsi_if_enable(1);
- dsi_force_tx_stop_mode_io();
+ dsi_vc_enable(dsidev, 0, 1);
+ dsi_vc_enable(dsidev, 1, 1);
+ dsi_vc_enable(dsidev, 2, 1);
+ dsi_vc_enable(dsidev, 3, 1);
+ dsi_if_enable(dsidev, 1);
+ dsi_force_tx_stop_mode_io(dsidev);
return 0;
err3:
- dsi_complexio_uninit();
+ dsi_cio_uninit(dsidev);
err2:
- dss_select_dispc_clk_source(DSS_CLK_SRC_FCK);
- dss_select_dsi_clk_source(DSS_CLK_SRC_FCK);
+ dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
+ dss_select_dsi_clk_source(dsi_module, OMAP_DSS_CLK_SRC_FCK);
err1:
- dsi_pll_uninit();
+ dsi_pll_uninit(dsidev, true);
err0:
return r;
}
-static void dsi_display_uninit_dsi(struct omap_dss_device *dssdev)
+static void dsi_display_uninit_dsi(struct omap_dss_device *dssdev,
+ bool disconnect_lanes, bool enter_ulps)
{
- /* disable interface */
- dsi_if_enable(0);
- dsi_vc_enable(0, 0);
- dsi_vc_enable(1, 0);
- dsi_vc_enable(2, 0);
- dsi_vc_enable(3, 0);
+ struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
+ int dsi_module = dsi_get_dsidev_id(dsidev);
- dss_select_dispc_clk_source(DSS_CLK_SRC_FCK);
- dss_select_dsi_clk_source(DSS_CLK_SRC_FCK);
- dsi_complexio_uninit();
- dsi_pll_uninit();
+ if (enter_ulps && !dsi->ulps_enabled)
+ dsi_enter_ulps(dsidev);
+
+ /* disable interface */
+ dsi_if_enable(dsidev, 0);
+ dsi_vc_enable(dsidev, 0, 0);
+ dsi_vc_enable(dsidev, 1, 0);
+ dsi_vc_enable(dsidev, 2, 0);
+ dsi_vc_enable(dsidev, 3, 0);
+
+ dss_select_dispc_clk_source(OMAP_DSS_CLK_SRC_FCK);
+ dss_select_dsi_clk_source(dsi_module, OMAP_DSS_CLK_SRC_FCK);
+ dsi_cio_uninit(dsidev);
+ dsi_pll_uninit(dsidev, disconnect_lanes);
}
-static int dsi_core_init(void)
+static int dsi_core_init(struct platform_device *dsidev)
{
/* Autoidle */
- REG_FLD_MOD(DSI_SYSCONFIG, 1, 0, 0);
+ REG_FLD_MOD(dsidev, DSI_SYSCONFIG, 1, 0, 0);
/* ENWAKEUP */
- REG_FLD_MOD(DSI_SYSCONFIG, 1, 2, 2);
+ REG_FLD_MOD(dsidev, DSI_SYSCONFIG, 1, 2, 2);
/* SIDLEMODE smart-idle */
- REG_FLD_MOD(DSI_SYSCONFIG, 2, 4, 3);
+ REG_FLD_MOD(dsidev, DSI_SYSCONFIG, 2, 4, 3);
- _dsi_initialize_irq();
+ _dsi_initialize_irq(dsidev);
return 0;
}
int omapdss_dsi_display_enable(struct omap_dss_device *dssdev)
{
+ struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
int r = 0;
DSSDBG("dsi_display_enable\n");
- WARN_ON(!dsi_bus_is_locked());
+ WARN_ON(!dsi_bus_is_locked(dsidev));
- mutex_lock(&dsi.lock);
+ mutex_lock(&dsi->lock);
r = omap_dss_start_device(dssdev);
if (r) {
@@ -3474,13 +4233,13 @@
}
enable_clocks(1);
- dsi_enable_pll_clock(1);
+ dsi_enable_pll_clock(dsidev, 1);
- r = _dsi_reset();
+ r = _dsi_reset(dsidev);
if (r)
goto err1;
- dsi_core_init();
+ dsi_core_init(dsidev);
r = dsi_display_init_dispc(dssdev);
if (r)
@@ -3490,7 +4249,7 @@
if (r)
goto err2;
- mutex_unlock(&dsi.lock);
+ mutex_unlock(&dsi->lock);
return 0;
@@ -3498,39 +4257,46 @@
dsi_display_uninit_dispc(dssdev);
err1:
enable_clocks(0);
- dsi_enable_pll_clock(0);
+ dsi_enable_pll_clock(dsidev, 0);
omap_dss_stop_device(dssdev);
err0:
- mutex_unlock(&dsi.lock);
+ mutex_unlock(&dsi->lock);
DSSDBG("dsi_display_enable FAILED\n");
return r;
}
EXPORT_SYMBOL(omapdss_dsi_display_enable);
-void omapdss_dsi_display_disable(struct omap_dss_device *dssdev)
+void omapdss_dsi_display_disable(struct omap_dss_device *dssdev,
+ bool disconnect_lanes, bool enter_ulps)
{
+ struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
+
DSSDBG("dsi_display_disable\n");
- WARN_ON(!dsi_bus_is_locked());
+ WARN_ON(!dsi_bus_is_locked(dsidev));
- mutex_lock(&dsi.lock);
+ mutex_lock(&dsi->lock);
dsi_display_uninit_dispc(dssdev);
- dsi_display_uninit_dsi(dssdev);
+ dsi_display_uninit_dsi(dssdev, disconnect_lanes, enter_ulps);
enable_clocks(0);
- dsi_enable_pll_clock(0);
+ dsi_enable_pll_clock(dsidev, 0);
omap_dss_stop_device(dssdev);
- mutex_unlock(&dsi.lock);
+ mutex_unlock(&dsi->lock);
}
EXPORT_SYMBOL(omapdss_dsi_display_disable);
int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable)
{
- dsi.te_enabled = enable;
+ struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
+
+ dsi->te_enabled = enable;
return 0;
}
EXPORT_SYMBOL(omapdss_dsi_enable_te);
@@ -3550,23 +4316,33 @@
int dsi_init_display(struct omap_dss_device *dssdev)
{
+ struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
+ int dsi_module = dsi_get_dsidev_id(dsidev);
+
DSSDBG("DSI init\n");
/* XXX these should be figured out dynamically */
dssdev->caps = OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE |
OMAP_DSS_DISPLAY_CAP_TEAR_ELIM;
- if (dsi.vdds_dsi_reg == NULL) {
+ if (dsi->vdds_dsi_reg == NULL) {
struct regulator *vdds_dsi;
- vdds_dsi = regulator_get(&dsi.pdev->dev, "vdds_dsi");
+ vdds_dsi = regulator_get(&dsi->pdev->dev, "vdds_dsi");
if (IS_ERR(vdds_dsi)) {
DSSERR("can't get VDDS_DSI regulator\n");
return PTR_ERR(vdds_dsi);
}
- dsi.vdds_dsi_reg = vdds_dsi;
+ dsi->vdds_dsi_reg = vdds_dsi;
+ }
+
+ if (dsi_get_num_data_lanes_dssdev(dssdev) > dsi->num_data_lanes) {
+ DSSERR("DSI%d can't support more than %d data lanes\n",
+ dsi_module + 1, dsi->num_data_lanes);
+ return -EINVAL;
}
return 0;
@@ -3574,11 +4350,13 @@
int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel)
{
+ struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
int i;
- for (i = 0; i < ARRAY_SIZE(dsi.vc); i++) {
- if (!dsi.vc[i].dssdev) {
- dsi.vc[i].dssdev = dssdev;
+ for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
+ if (!dsi->vc[i].dssdev) {
+ dsi->vc[i].dssdev = dssdev;
*channel = i;
return 0;
}
@@ -3591,6 +4369,9 @@
int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id)
{
+ struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
+
if (vc_id < 0 || vc_id > 3) {
DSSERR("VC ID out of range\n");
return -EINVAL;
@@ -3601,13 +4382,13 @@
return -EINVAL;
}
- if (dsi.vc[channel].dssdev != dssdev) {
+ if (dsi->vc[channel].dssdev != dssdev) {
DSSERR("Virtual Channel not allocated to display %s\n",
dssdev->name);
return -EINVAL;
}
- dsi.vc[channel].vc_id = vc_id;
+ dsi->vc[channel].vc_id = vc_id;
return 0;
}
@@ -3615,143 +4396,172 @@
void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel)
{
+ struct platform_device *dsidev = dsi_get_dsidev_from_dssdev(dssdev);
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
+
if ((channel >= 0 && channel <= 3) &&
- dsi.vc[channel].dssdev == dssdev) {
- dsi.vc[channel].dssdev = NULL;
- dsi.vc[channel].vc_id = 0;
+ dsi->vc[channel].dssdev == dssdev) {
+ dsi->vc[channel].dssdev = NULL;
+ dsi->vc[channel].vc_id = 0;
}
}
EXPORT_SYMBOL(omap_dsi_release_vc);
-void dsi_wait_pll_hsdiv_dispc_active(void)
+void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev)
{
- if (wait_for_bit_change(DSI_PLL_STATUS, 7, 1) != 1)
+ if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 7, 1) != 1)
DSSERR("%s (%s) not active\n",
- dss_get_generic_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
- dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC));
+ dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC),
+ dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC));
}
-void dsi_wait_pll_hsdiv_dsi_active(void)
+void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev)
{
- if (wait_for_bit_change(DSI_PLL_STATUS, 8, 1) != 1)
+ if (wait_for_bit_change(dsidev, DSI_PLL_STATUS, 8, 1) != 1)
DSSERR("%s (%s) not active\n",
- dss_get_generic_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
- dss_feat_get_clk_source_name(DSS_CLK_SRC_DSI_PLL_HSDIV_DSI));
+ dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI),
+ dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI));
}
-static void dsi_calc_clock_param_ranges(void)
+static void dsi_calc_clock_param_ranges(struct platform_device *dsidev)
{
- dsi.regn_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGN);
- dsi.regm_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM);
- dsi.regm_dispc_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DISPC);
- dsi.regm_dsi_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DSI);
- dsi.fint_min = dss_feat_get_param_min(FEAT_PARAM_DSIPLL_FINT);
- dsi.fint_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_FINT);
- dsi.lpdiv_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV);
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
+
+ dsi->regn_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGN);
+ dsi->regm_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM);
+ dsi->regm_dispc_max =
+ dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DISPC);
+ dsi->regm_dsi_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_REGM_DSI);
+ dsi->fint_min = dss_feat_get_param_min(FEAT_PARAM_DSIPLL_FINT);
+ dsi->fint_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_FINT);
+ dsi->lpdiv_max = dss_feat_get_param_max(FEAT_PARAM_DSIPLL_LPDIV);
}
-static int dsi_init(struct platform_device *pdev)
+static int dsi_init(struct platform_device *dsidev)
{
+ struct omap_display_platform_data *dss_plat_data;
+ struct omap_dss_board_info *board_info;
u32 rev;
- int r, i;
+ int r, i, dsi_module = dsi_get_dsidev_id(dsidev);
struct resource *dsi_mem;
+ struct dsi_data *dsi;
- spin_lock_init(&dsi.irq_lock);
- spin_lock_init(&dsi.errors_lock);
- dsi.errors = 0;
+ dsi = kzalloc(sizeof(*dsi), GFP_KERNEL);
+ if (!dsi) {
+ r = -ENOMEM;
+ goto err0;
+ }
+
+ dsi->pdev = dsidev;
+ dsi_pdev_map[dsi_module] = dsidev;
+ dev_set_drvdata(&dsidev->dev, dsi);
+
+ dss_plat_data = dsidev->dev.platform_data;
+ board_info = dss_plat_data->board_data;
+ dsi->dsi_mux_pads = board_info->dsi_mux_pads;
+
+ spin_lock_init(&dsi->irq_lock);
+ spin_lock_init(&dsi->errors_lock);
+ dsi->errors = 0;
#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
- spin_lock_init(&dsi.irq_stats_lock);
- dsi.irq_stats.last_reset = jiffies;
+ spin_lock_init(&dsi->irq_stats_lock);
+ dsi->irq_stats.last_reset = jiffies;
#endif
- mutex_init(&dsi.lock);
- sema_init(&dsi.bus_lock, 1);
+ mutex_init(&dsi->lock);
+ sema_init(&dsi->bus_lock, 1);
- dsi.workqueue = create_singlethread_workqueue("dsi");
- if (dsi.workqueue == NULL)
- return -ENOMEM;
-
- INIT_DELAYED_WORK_DEFERRABLE(&dsi.framedone_timeout_work,
+ INIT_DELAYED_WORK_DEFERRABLE(&dsi->framedone_timeout_work,
dsi_framedone_timeout_work_callback);
#ifdef DSI_CATCH_MISSING_TE
- init_timer(&dsi.te_timer);
- dsi.te_timer.function = dsi_te_timeout;
- dsi.te_timer.data = 0;
+ init_timer(&dsi->te_timer);
+ dsi->te_timer.function = dsi_te_timeout;
+ dsi->te_timer.data = 0;
#endif
- dsi_mem = platform_get_resource(dsi.pdev, IORESOURCE_MEM, 0);
+ dsi_mem = platform_get_resource(dsi->pdev, IORESOURCE_MEM, 0);
if (!dsi_mem) {
DSSERR("can't get IORESOURCE_MEM DSI\n");
r = -EINVAL;
goto err1;
}
- dsi.base = ioremap(dsi_mem->start, resource_size(dsi_mem));
- if (!dsi.base) {
+ dsi->base = ioremap(dsi_mem->start, resource_size(dsi_mem));
+ if (!dsi->base) {
DSSERR("can't ioremap DSI\n");
r = -ENOMEM;
goto err1;
}
- dsi.irq = platform_get_irq(dsi.pdev, 0);
- if (dsi.irq < 0) {
+ dsi->irq = platform_get_irq(dsi->pdev, 0);
+ if (dsi->irq < 0) {
DSSERR("platform_get_irq failed\n");
r = -ENODEV;
goto err2;
}
- r = request_irq(dsi.irq, omap_dsi_irq_handler, IRQF_SHARED,
- "OMAP DSI1", dsi.pdev);
+ r = request_irq(dsi->irq, omap_dsi_irq_handler, IRQF_SHARED,
+ dev_name(&dsidev->dev), dsi->pdev);
if (r < 0) {
DSSERR("request_irq failed\n");
goto err2;
}
/* DSI VCs initialization */
- for (i = 0; i < ARRAY_SIZE(dsi.vc); i++) {
- dsi.vc[i].mode = DSI_VC_MODE_L4;
- dsi.vc[i].dssdev = NULL;
- dsi.vc[i].vc_id = 0;
+ for (i = 0; i < ARRAY_SIZE(dsi->vc); i++) {
+ dsi->vc[i].mode = DSI_VC_MODE_L4;
+ dsi->vc[i].dssdev = NULL;
+ dsi->vc[i].vc_id = 0;
}
- dsi_calc_clock_param_ranges();
+ dsi_calc_clock_param_ranges(dsidev);
enable_clocks(1);
- rev = dsi_read_reg(DSI_REVISION);
- dev_dbg(&pdev->dev, "OMAP DSI rev %d.%d\n",
+ rev = dsi_read_reg(dsidev, DSI_REVISION);
+ dev_dbg(&dsidev->dev, "OMAP DSI rev %d.%d\n",
FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
+ dsi->num_data_lanes = dsi_get_num_data_lanes(dsidev);
+
enable_clocks(0);
return 0;
err2:
- iounmap(dsi.base);
+ iounmap(dsi->base);
err1:
- destroy_workqueue(dsi.workqueue);
+ kfree(dsi);
+err0:
return r;
}
-static void dsi_exit(void)
+static void dsi_exit(struct platform_device *dsidev)
{
- if (dsi.vdds_dsi_reg != NULL) {
- regulator_put(dsi.vdds_dsi_reg);
- dsi.vdds_dsi_reg = NULL;
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
+
+ if (dsi->vdds_dsi_reg != NULL) {
+ if (dsi->vdds_dsi_enabled) {
+ regulator_disable(dsi->vdds_dsi_reg);
+ dsi->vdds_dsi_enabled = false;
+ }
+
+ regulator_put(dsi->vdds_dsi_reg);
+ dsi->vdds_dsi_reg = NULL;
}
- free_irq(dsi.irq, dsi.pdev);
- iounmap(dsi.base);
+ free_irq(dsi->irq, dsi->pdev);
+ iounmap(dsi->base);
- destroy_workqueue(dsi.workqueue);
+ kfree(dsi);
DSSDBG("omap_dsi_exit\n");
}
/* DSI1 HW IP initialisation */
-static int omap_dsi1hw_probe(struct platform_device *pdev)
+static int omap_dsi1hw_probe(struct platform_device *dsidev)
{
int r;
- dsi.pdev = pdev;
- r = dsi_init(pdev);
+
+ r = dsi_init(dsidev);
if (r) {
DSSERR("Failed to initialize DSI\n");
goto err_dsi;
@@ -3760,9 +4570,12 @@
return r;
}
-static int omap_dsi1hw_remove(struct platform_device *pdev)
+static int omap_dsi1hw_remove(struct platform_device *dsidev)
{
- dsi_exit();
+ struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev);
+
+ dsi_exit(dsidev);
+ WARN_ON(dsi->scp_clk_refcount > 0);
return 0;
}
diff --git a/drivers/video/omap2/dss/dss.c b/drivers/video/omap2/dss/dss.c
index 3f1fee6..d9489d5 100644
--- a/drivers/video/omap2/dss/dss.c
+++ b/drivers/video/omap2/dss/dss.c
@@ -29,7 +29,7 @@
#include <linux/seq_file.h>
#include <linux/clk.h>
-#include <plat/display.h>
+#include <video/omapdss.h>
#include <plat/clock.h>
#include "dss.h"
#include "dss_features.h"
@@ -45,7 +45,6 @@
#define DSS_REVISION DSS_REG(0x0000)
#define DSS_SYSCONFIG DSS_REG(0x0010)
#define DSS_SYSSTATUS DSS_REG(0x0014)
-#define DSS_IRQSTATUS DSS_REG(0x0018)
#define DSS_CONTROL DSS_REG(0x0040)
#define DSS_SDI_CONTROL DSS_REG(0x0044)
#define DSS_PLL_CONTROL DSS_REG(0x0048)
@@ -75,17 +74,17 @@
struct dss_clock_info cache_dss_cinfo;
struct dispc_clock_info cache_dispc_cinfo;
- enum dss_clk_source dsi_clk_source;
- enum dss_clk_source dispc_clk_source;
- enum dss_clk_source lcd_clk_source[MAX_DSS_LCD_MANAGERS];
+ enum omap_dss_clk_source dsi_clk_source[MAX_NUM_DSI];
+ enum omap_dss_clk_source dispc_clk_source;
+ enum omap_dss_clk_source lcd_clk_source[MAX_DSS_LCD_MANAGERS];
u32 ctx[DSS_SZ_REGS / sizeof(u32)];
} dss;
static const char * const dss_generic_clk_source_names[] = {
- [DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "DSI_PLL_HSDIV_DISPC",
- [DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "DSI_PLL_HSDIV_DSI",
- [DSS_CLK_SRC_FCK] = "DSS_FCK",
+ [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "DSI_PLL_HSDIV_DISPC",
+ [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "DSI_PLL_HSDIV_DSI",
+ [OMAP_DSS_CLK_SRC_FCK] = "DSS_FCK",
};
static void dss_clk_enable_all_no_ctx(void);
@@ -230,7 +229,7 @@
REG_FLD_MOD(DSS_PLL_CONTROL, 0, 18, 18); /* SDI_PLL_SYSRESET */
}
-const char *dss_get_generic_clk_source_name(enum dss_clk_source clk_src)
+const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src)
{
return dss_generic_clk_source_names[clk_src];
}
@@ -246,8 +245,8 @@
seq_printf(s, "- DSS -\n");
- fclk_name = dss_get_generic_clk_source_name(DSS_CLK_SRC_FCK);
- fclk_real_name = dss_feat_get_clk_source_name(DSS_CLK_SRC_FCK);
+ fclk_name = dss_get_generic_clk_source_name(OMAP_DSS_CLK_SRC_FCK);
+ fclk_real_name = dss_feat_get_clk_source_name(OMAP_DSS_CLK_SRC_FCK);
fclk_rate = dss_clk_get_rate(DSS_CLK_FCK);
if (dss.dpll4_m4_ck) {
@@ -286,7 +285,6 @@
DUMPREG(DSS_REVISION);
DUMPREG(DSS_SYSCONFIG);
DUMPREG(DSS_SYSSTATUS);
- DUMPREG(DSS_IRQSTATUS);
DUMPREG(DSS_CONTROL);
if (dss_feat_get_supported_displays(OMAP_DSS_CHANNEL_LCD) &
@@ -300,18 +298,25 @@
#undef DUMPREG
}
-void dss_select_dispc_clk_source(enum dss_clk_source clk_src)
+void dss_select_dispc_clk_source(enum omap_dss_clk_source clk_src)
{
+ struct platform_device *dsidev;
int b;
u8 start, end;
switch (clk_src) {
- case DSS_CLK_SRC_FCK:
+ case OMAP_DSS_CLK_SRC_FCK:
b = 0;
break;
- case DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
+ case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
b = 1;
- dsi_wait_pll_hsdiv_dispc_active();
+ dsidev = dsi_get_dsidev_from_id(0);
+ dsi_wait_pll_hsdiv_dispc_active(dsidev);
+ break;
+ case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
+ b = 2;
+ dsidev = dsi_get_dsidev_from_id(1);
+ dsi_wait_pll_hsdiv_dispc_active(dsidev);
break;
default:
BUG();
@@ -324,17 +329,27 @@
dss.dispc_clk_source = clk_src;
}
-void dss_select_dsi_clk_source(enum dss_clk_source clk_src)
+void dss_select_dsi_clk_source(int dsi_module,
+ enum omap_dss_clk_source clk_src)
{
+ struct platform_device *dsidev;
int b;
switch (clk_src) {
- case DSS_CLK_SRC_FCK:
+ case OMAP_DSS_CLK_SRC_FCK:
b = 0;
break;
- case DSS_CLK_SRC_DSI_PLL_HSDIV_DSI:
+ case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI:
+ BUG_ON(dsi_module != 0);
b = 1;
- dsi_wait_pll_hsdiv_dsi_active();
+ dsidev = dsi_get_dsidev_from_id(0);
+ dsi_wait_pll_hsdiv_dsi_active(dsidev);
+ break;
+ case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI:
+ BUG_ON(dsi_module != 1);
+ b = 1;
+ dsidev = dsi_get_dsidev_from_id(1);
+ dsi_wait_pll_hsdiv_dsi_active(dsidev);
break;
default:
BUG();
@@ -342,25 +357,33 @@
REG_FLD_MOD(DSS_CONTROL, b, 1, 1); /* DSI_CLK_SWITCH */
- dss.dsi_clk_source = clk_src;
+ dss.dsi_clk_source[dsi_module] = clk_src;
}
void dss_select_lcd_clk_source(enum omap_channel channel,
- enum dss_clk_source clk_src)
+ enum omap_dss_clk_source clk_src)
{
+ struct platform_device *dsidev;
int b, ix, pos;
if (!dss_has_feature(FEAT_LCD_CLK_SRC))
return;
switch (clk_src) {
- case DSS_CLK_SRC_FCK:
+ case OMAP_DSS_CLK_SRC_FCK:
b = 0;
break;
- case DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
+ case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
BUG_ON(channel != OMAP_DSS_CHANNEL_LCD);
b = 1;
- dsi_wait_pll_hsdiv_dispc_active();
+ dsidev = dsi_get_dsidev_from_id(0);
+ dsi_wait_pll_hsdiv_dispc_active(dsidev);
+ break;
+ case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
+ BUG_ON(channel != OMAP_DSS_CHANNEL_LCD2);
+ b = 1;
+ dsidev = dsi_get_dsidev_from_id(1);
+ dsi_wait_pll_hsdiv_dispc_active(dsidev);
break;
default:
BUG();
@@ -373,20 +396,26 @@
dss.lcd_clk_source[ix] = clk_src;
}
-enum dss_clk_source dss_get_dispc_clk_source(void)
+enum omap_dss_clk_source dss_get_dispc_clk_source(void)
{
return dss.dispc_clk_source;
}
-enum dss_clk_source dss_get_dsi_clk_source(void)
+enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module)
{
- return dss.dsi_clk_source;
+ return dss.dsi_clk_source[dsi_module];
}
-enum dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel)
+enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel)
{
- int ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 1;
- return dss.lcd_clk_source[ix];
+ if (dss_has_feature(FEAT_LCD_CLK_SRC)) {
+ int ix = channel == OMAP_DSS_CHANNEL_LCD ? 0 : 1;
+ return dss.lcd_clk_source[ix];
+ } else {
+ /* LCD_CLK source is the same as DISPC_FCLK source for
+ * OMAP2 and OMAP3 */
+ return dss.dispc_clk_source;
+ }
}
/* calculate clock rates using dividers in cinfo */
@@ -659,13 +688,18 @@
* the kernel resets it */
omap_writel(omap_readl(0x48050440) & ~0x3, 0x48050440);
+#ifdef CONFIG_OMAP2_DSS_SLEEP_BEFORE_RESET
/* We need to wait here a bit, otherwise we sometimes start to
* get synclost errors, and after that only power cycle will
* restore DSS functionality. I have no idea why this happens.
* And we have to wait _before_ resetting the DSS, but after
* enabling clocks.
+ *
+ * This bug was at least present on OMAP3430. It's unknown
+ * if it happens on OMAP2 or OMAP3630.
*/
msleep(50);
+#endif
_omap_dss_reset();
@@ -700,10 +734,11 @@
dss.dpll4_m4_ck = dpll4_m4_ck;
- dss.dsi_clk_source = DSS_CLK_SRC_FCK;
- dss.dispc_clk_source = DSS_CLK_SRC_FCK;
- dss.lcd_clk_source[0] = DSS_CLK_SRC_FCK;
- dss.lcd_clk_source[1] = DSS_CLK_SRC_FCK;
+ dss.dsi_clk_source[0] = OMAP_DSS_CLK_SRC_FCK;
+ dss.dsi_clk_source[1] = OMAP_DSS_CLK_SRC_FCK;
+ dss.dispc_clk_source = OMAP_DSS_CLK_SRC_FCK;
+ dss.lcd_clk_source[0] = OMAP_DSS_CLK_SRC_FCK;
+ dss.lcd_clk_source[1] = OMAP_DSS_CLK_SRC_FCK;
dss_save_context();
@@ -1015,6 +1050,14 @@
dss.dss_video_fck
};
+ const char *names[5] = {
+ "ick",
+ "fck",
+ "sys_clk",
+ "tv_fck",
+ "video_fck"
+ };
+
seq_printf(s, "- CORE -\n");
seq_printf(s, "internal clk count\t\t%u\n", dss.num_clks_enabled);
@@ -1022,8 +1065,11 @@
for (i = 0; i < 5; i++) {
if (!clocks[i])
continue;
- seq_printf(s, "%-15s\t%lu\t%d\n",
+ seq_printf(s, "%s (%s)%*s\t%lu\t%d\n",
+ names[i],
clocks[i]->name,
+ 24 - strlen(names[i]) - strlen(clocks[i]->name),
+ "",
clk_get_rate(clocks[i]),
clocks[i]->usecount);
}
diff --git a/drivers/video/omap2/dss/dss.h b/drivers/video/omap2/dss/dss.h
index c2f582bb19..8ab6d43 100644
--- a/drivers/video/omap2/dss/dss.h
+++ b/drivers/video/omap2/dss/dss.h
@@ -117,15 +117,6 @@
DSS_CLK_VIDFCK = 1 << 4, /* DSS_96M_FCLK*/
};
-enum dss_clk_source {
- DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, /* OMAP3: DSI1_PLL_FCLK
- * OMAP4: PLL1_CLK1 */
- DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, /* OMAP3: DSI2_PLL_FCLK
- * OMAP4: PLL1_CLK2 */
- DSS_CLK_SRC_FCK, /* OMAP2/3: DSS1_ALWON_FCLK
- * OMAP4: DSS_FCLK */
-};
-
enum dss_hdmi_venc_clk_source_select {
DSS_VENC_TV_CLK = 0,
DSS_HDMI_M_PCLK = 1,
@@ -236,7 +227,7 @@
void dss_clk_disable(enum dss_clock clks);
unsigned long dss_clk_get_rate(enum dss_clock clk);
int dss_need_ctx_restore(void);
-const char *dss_get_generic_clk_source_name(enum dss_clk_source clk_src);
+const char *dss_get_generic_clk_source_name(enum omap_dss_clk_source clk_src);
void dss_dump_clocks(struct seq_file *s);
void dss_dump_regs(struct seq_file *s);
@@ -248,13 +239,14 @@
int dss_sdi_enable(void);
void dss_sdi_disable(void);
-void dss_select_dispc_clk_source(enum dss_clk_source clk_src);
-void dss_select_dsi_clk_source(enum dss_clk_source clk_src);
+void dss_select_dispc_clk_source(enum omap_dss_clk_source clk_src);
+void dss_select_dsi_clk_source(int dsi_module,
+ enum omap_dss_clk_source clk_src);
void dss_select_lcd_clk_source(enum omap_channel channel,
- enum dss_clk_source clk_src);
-enum dss_clk_source dss_get_dispc_clk_source(void);
-enum dss_clk_source dss_get_dsi_clk_source(void);
-enum dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel);
+ enum omap_dss_clk_source clk_src);
+enum omap_dss_clk_source dss_get_dispc_clk_source(void);
+enum omap_dss_clk_source dss_get_dsi_clk_source(int dsi_module);
+enum omap_dss_clk_source dss_get_lcd_clk_source(enum omap_channel channel);
void dss_set_venc_output(enum omap_dss_venc_type type);
void dss_set_dac_pwrdn_bgz(bool enable);
@@ -284,31 +276,39 @@
/* DSI */
#ifdef CONFIG_OMAP2_DSS_DSI
+
+struct dentry;
+struct file_operations;
+
int dsi_init_platform_driver(void);
void dsi_uninit_platform_driver(void);
void dsi_dump_clocks(struct seq_file *s);
-void dsi_dump_irqs(struct seq_file *s);
-void dsi_dump_regs(struct seq_file *s);
+void dsi_create_debugfs_files_irq(struct dentry *debugfs_dir,
+ const struct file_operations *debug_fops);
+void dsi_create_debugfs_files_reg(struct dentry *debugfs_dir,
+ const struct file_operations *debug_fops);
void dsi_save_context(void);
void dsi_restore_context(void);
int dsi_init_display(struct omap_dss_device *display);
void dsi_irq_handler(void);
-unsigned long dsi_get_pll_hsdiv_dispc_rate(void);
-int dsi_pll_set_clock_div(struct dsi_clock_info *cinfo);
-int dsi_pll_calc_clock_div_pck(bool is_tft, unsigned long req_pck,
- struct dsi_clock_info *cinfo,
+unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev);
+int dsi_pll_set_clock_div(struct platform_device *dsidev,
+ struct dsi_clock_info *cinfo);
+int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev, bool is_tft,
+ unsigned long req_pck, struct dsi_clock_info *cinfo,
struct dispc_clock_info *dispc_cinfo);
-int dsi_pll_init(struct omap_dss_device *dssdev, bool enable_hsclk,
+int dsi_pll_init(struct platform_device *dsidev, bool enable_hsclk,
bool enable_hsdiv);
-void dsi_pll_uninit(void);
+void dsi_pll_uninit(struct platform_device *dsidev, bool disconnect_lanes);
void dsi_get_overlay_fifo_thresholds(enum omap_plane plane,
u32 fifo_size, enum omap_burst_size *burst_size,
u32 *fifo_low, u32 *fifo_high);
-void dsi_wait_pll_hsdiv_dispc_active(void);
-void dsi_wait_pll_hsdiv_dsi_active(void);
+void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev);
+void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev);
+struct platform_device *dsi_get_dsidev_from_id(int module);
#else
static inline int dsi_init_platform_driver(void)
{
@@ -317,17 +317,47 @@
static inline void dsi_uninit_platform_driver(void)
{
}
-static inline unsigned long dsi_get_pll_hsdiv_dispc_rate(void)
+static inline unsigned long dsi_get_pll_hsdiv_dispc_rate(struct platform_device *dsidev)
{
WARN("%s: DSI not compiled in, returning rate as 0\n", __func__);
return 0;
}
-static inline void dsi_wait_pll_hsdiv_dispc_active(void)
+static inline int dsi_pll_set_clock_div(struct platform_device *dsidev,
+ struct dsi_clock_info *cinfo)
+{
+ WARN("%s: DSI not compiled in\n", __func__);
+ return -ENODEV;
+}
+static inline int dsi_pll_calc_clock_div_pck(struct platform_device *dsidev,
+ bool is_tft, unsigned long req_pck,
+ struct dsi_clock_info *dsi_cinfo,
+ struct dispc_clock_info *dispc_cinfo)
+{
+ WARN("%s: DSI not compiled in\n", __func__);
+ return -ENODEV;
+}
+static inline int dsi_pll_init(struct platform_device *dsidev,
+ bool enable_hsclk, bool enable_hsdiv)
+{
+ WARN("%s: DSI not compiled in\n", __func__);
+ return -ENODEV;
+}
+static inline void dsi_pll_uninit(struct platform_device *dsidev,
+ bool disconnect_lanes)
{
}
-static inline void dsi_wait_pll_hsdiv_dsi_active(void)
+static inline void dsi_wait_pll_hsdiv_dispc_active(struct platform_device *dsidev)
{
}
+static inline void dsi_wait_pll_hsdiv_dsi_active(struct platform_device *dsidev)
+{
+}
+static inline struct platform_device *dsi_get_dsidev_from_id(int module)
+{
+ WARN("%s: DSI not compiled in, returning platform device as NULL\n",
+ __func__);
+ return NULL;
+}
#endif
/* DPI */
@@ -391,7 +421,8 @@
enum omap_dss_rotation_type rotation_type,
u8 rotation, bool mirror,
u8 global_alpha, u8 pre_mult_alpha,
- enum omap_channel channel);
+ enum omap_channel channel,
+ u32 puv_addr);
bool dispc_go_busy(enum omap_channel channel);
void dispc_go(enum omap_channel channel);
@@ -485,13 +516,6 @@
int rfbi_init_platform_driver(void);
void rfbi_uninit_platform_driver(void);
void rfbi_dump_regs(struct seq_file *s);
-
-int rfbi_configure(int rfbi_module, int bpp, int lines);
-void rfbi_enable_rfbi(bool enable);
-void rfbi_transfer_area(struct omap_dss_device *dssdev, u16 width,
- u16 height, void (callback)(void *data), void *data);
-void rfbi_set_timings(int rfbi_module, struct rfbi_timings *t);
-unsigned long rfbi_get_max_tx_rate(void);
int rfbi_init_display(struct omap_dss_device *display);
#else
static inline int rfbi_init_platform_driver(void)
diff --git a/drivers/video/omap2/dss/dss_features.c b/drivers/video/omap2/dss/dss_features.c
index aa16222..1c18888 100644
--- a/drivers/video/omap2/dss/dss_features.c
+++ b/drivers/video/omap2/dss/dss_features.c
@@ -22,7 +22,7 @@
#include <linux/err.h>
#include <linux/slab.h>
-#include <plat/display.h>
+#include <video/omapdss.h>
#include <plat/cpu.h>
#include "dss.h"
@@ -52,7 +52,7 @@
};
/* This struct is assigned to one of the below during initialization */
-static struct omap_dss_features *omap_current_dss_features;
+static const struct omap_dss_features *omap_current_dss_features;
static const struct dss_reg_field omap2_dss_reg_fields[] = {
[FEAT_REG_FIRHINC] = { 11, 0 },
@@ -177,22 +177,55 @@
OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32,
};
+static const enum omap_color_mode omap4_dss_supported_color_modes[] = {
+ /* OMAP_DSS_GFX */
+ OMAP_DSS_COLOR_CLUT1 | OMAP_DSS_COLOR_CLUT2 |
+ OMAP_DSS_COLOR_CLUT4 | OMAP_DSS_COLOR_CLUT8 |
+ OMAP_DSS_COLOR_RGB12U | OMAP_DSS_COLOR_ARGB16 |
+ OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB24U |
+ OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_ARGB32 |
+ OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_RGBX32 |
+ OMAP_DSS_COLOR_ARGB16_1555,
+
+ /* OMAP_DSS_VIDEO1 */
+ OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB12U |
+ OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_ARGB16_1555 |
+ OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_NV12 |
+ OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_RGB24U |
+ OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_UYVY |
+ OMAP_DSS_COLOR_ARGB16 | OMAP_DSS_COLOR_XRGB16_1555 |
+ OMAP_DSS_COLOR_ARGB32 | OMAP_DSS_COLOR_RGBX16 |
+ OMAP_DSS_COLOR_RGBX32,
+
+ /* OMAP_DSS_VIDEO2 */
+ OMAP_DSS_COLOR_RGB16 | OMAP_DSS_COLOR_RGB12U |
+ OMAP_DSS_COLOR_YUV2 | OMAP_DSS_COLOR_ARGB16_1555 |
+ OMAP_DSS_COLOR_RGBA32 | OMAP_DSS_COLOR_NV12 |
+ OMAP_DSS_COLOR_RGBA16 | OMAP_DSS_COLOR_RGB24U |
+ OMAP_DSS_COLOR_RGB24P | OMAP_DSS_COLOR_UYVY |
+ OMAP_DSS_COLOR_ARGB16 | OMAP_DSS_COLOR_XRGB16_1555 |
+ OMAP_DSS_COLOR_ARGB32 | OMAP_DSS_COLOR_RGBX16 |
+ OMAP_DSS_COLOR_RGBX32,
+};
+
static const char * const omap2_dss_clk_source_names[] = {
- [DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "N/A",
- [DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "N/A",
- [DSS_CLK_SRC_FCK] = "DSS_FCLK1",
+ [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "N/A",
+ [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "N/A",
+ [OMAP_DSS_CLK_SRC_FCK] = "DSS_FCLK1",
};
static const char * const omap3_dss_clk_source_names[] = {
- [DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "DSI1_PLL_FCLK",
- [DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "DSI2_PLL_FCLK",
- [DSS_CLK_SRC_FCK] = "DSS1_ALWON_FCLK",
+ [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "DSI1_PLL_FCLK",
+ [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "DSI2_PLL_FCLK",
+ [OMAP_DSS_CLK_SRC_FCK] = "DSS1_ALWON_FCLK",
};
static const char * const omap4_dss_clk_source_names[] = {
- [DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "PLL1_CLK1",
- [DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "PLL1_CLK2",
- [DSS_CLK_SRC_FCK] = "DSS_FCLK",
+ [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC] = "PLL1_CLK1",
+ [OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI] = "PLL1_CLK2",
+ [OMAP_DSS_CLK_SRC_FCK] = "DSS_FCLK",
+ [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC] = "PLL2_CLK1",
+ [OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI] = "PLL2_CLK2",
};
static const struct dss_param_range omap2_dss_param_range[] = {
@@ -226,7 +259,7 @@
};
/* OMAP2 DSS Features */
-static struct omap_dss_features omap2_dss_features = {
+static const struct omap_dss_features omap2_dss_features = {
.reg_fields = omap2_dss_reg_fields,
.num_reg_fields = ARRAY_SIZE(omap2_dss_reg_fields),
@@ -244,7 +277,7 @@
};
/* OMAP3 DSS Features */
-static struct omap_dss_features omap3430_dss_features = {
+static const struct omap_dss_features omap3430_dss_features = {
.reg_fields = omap3_dss_reg_fields,
.num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields),
@@ -252,7 +285,8 @@
FEAT_GLOBAL_ALPHA | FEAT_LCDENABLEPOL |
FEAT_LCDENABLESIGNAL | FEAT_PCKFREEENABLE |
FEAT_FUNCGATED | FEAT_ROWREPEATENABLE |
- FEAT_LINEBUFFERSPLIT | FEAT_RESIZECONF,
+ FEAT_LINEBUFFERSPLIT | FEAT_RESIZECONF |
+ FEAT_DSI_PLL_FREQSEL | FEAT_DSI_REVERSE_TXCLKESC,
.num_mgrs = 2,
.num_ovls = 3,
@@ -262,7 +296,7 @@
.dss_params = omap3_dss_param_range,
};
-static struct omap_dss_features omap3630_dss_features = {
+static const struct omap_dss_features omap3630_dss_features = {
.reg_fields = omap3_dss_reg_fields,
.num_reg_fields = ARRAY_SIZE(omap3_dss_reg_fields),
@@ -271,7 +305,8 @@
FEAT_LCDENABLESIGNAL | FEAT_PCKFREEENABLE |
FEAT_PRE_MULT_ALPHA | FEAT_FUNCGATED |
FEAT_ROWREPEATENABLE | FEAT_LINEBUFFERSPLIT |
- FEAT_RESIZECONF,
+ FEAT_RESIZECONF | FEAT_DSI_PLL_PWR_BUG |
+ FEAT_DSI_PLL_FREQSEL,
.num_mgrs = 2,
.num_ovls = 3,
@@ -282,19 +317,43 @@
};
/* OMAP4 DSS Features */
-static struct omap_dss_features omap4_dss_features = {
+/* For OMAP4430 ES 1.0 revision */
+static const struct omap_dss_features omap4430_es1_0_dss_features = {
.reg_fields = omap4_dss_reg_fields,
.num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields),
.has_feature =
FEAT_GLOBAL_ALPHA | FEAT_PRE_MULT_ALPHA |
FEAT_MGR_LCD2 | FEAT_GLOBAL_ALPHA_VID1 |
- FEAT_CORE_CLK_DIV | FEAT_LCD_CLK_SRC,
+ FEAT_CORE_CLK_DIV | FEAT_LCD_CLK_SRC |
+ FEAT_DSI_DCS_CMD_CONFIG_VC | FEAT_DSI_VC_OCP_WIDTH |
+ FEAT_DSI_GNQ | FEAT_HANDLE_UV_SEPARATE | FEAT_ATTR2,
.num_mgrs = 3,
.num_ovls = 3,
.supported_displays = omap4_dss_supported_displays,
- .supported_color_modes = omap3_dss_supported_color_modes,
+ .supported_color_modes = omap4_dss_supported_color_modes,
+ .clksrc_names = omap4_dss_clk_source_names,
+ .dss_params = omap4_dss_param_range,
+};
+
+/* For all the other OMAP4 versions */
+static const struct omap_dss_features omap4_dss_features = {
+ .reg_fields = omap4_dss_reg_fields,
+ .num_reg_fields = ARRAY_SIZE(omap4_dss_reg_fields),
+
+ .has_feature =
+ FEAT_GLOBAL_ALPHA | FEAT_PRE_MULT_ALPHA |
+ FEAT_MGR_LCD2 | FEAT_GLOBAL_ALPHA_VID1 |
+ FEAT_CORE_CLK_DIV | FEAT_LCD_CLK_SRC |
+ FEAT_DSI_DCS_CMD_CONFIG_VC | FEAT_DSI_VC_OCP_WIDTH |
+ FEAT_DSI_GNQ | FEAT_HDMI_CTS_SWMODE |
+ FEAT_HANDLE_UV_SEPARATE | FEAT_ATTR2,
+
+ .num_mgrs = 3,
+ .num_ovls = 3,
+ .supported_displays = omap4_dss_supported_displays,
+ .supported_color_modes = omap4_dss_supported_color_modes,
.clksrc_names = omap4_dss_clk_source_names,
.dss_params = omap4_dss_param_range,
};
@@ -337,7 +396,7 @@
color_mode;
}
-const char *dss_feat_get_clk_source_name(enum dss_clk_source id)
+const char *dss_feat_get_clk_source_name(enum omap_dss_clk_source id)
{
return omap_current_dss_features->clksrc_names[id];
}
@@ -365,6 +424,10 @@
omap_current_dss_features = &omap3630_dss_features;
else if (cpu_is_omap34xx())
omap_current_dss_features = &omap3430_dss_features;
- else
+ else if (omap_rev() == OMAP4430_REV_ES1_0)
+ omap_current_dss_features = &omap4430_es1_0_dss_features;
+ else if (cpu_is_omap44xx())
omap_current_dss_features = &omap4_dss_features;
+ else
+ DSSWARN("Unsupported OMAP version");
}
diff --git a/drivers/video/omap2/dss/dss_features.h b/drivers/video/omap2/dss/dss_features.h
index 12e9c4e..07b346f 100644
--- a/drivers/video/omap2/dss/dss_features.h
+++ b/drivers/video/omap2/dss/dss_features.h
@@ -23,23 +23,34 @@
#define MAX_DSS_MANAGERS 3
#define MAX_DSS_OVERLAYS 3
#define MAX_DSS_LCD_MANAGERS 2
+#define MAX_NUM_DSI 2
/* DSS has feature id */
enum dss_feat_id {
- FEAT_GLOBAL_ALPHA = 1 << 0,
- FEAT_GLOBAL_ALPHA_VID1 = 1 << 1,
- FEAT_PRE_MULT_ALPHA = 1 << 2,
- FEAT_LCDENABLEPOL = 1 << 3,
- FEAT_LCDENABLESIGNAL = 1 << 4,
- FEAT_PCKFREEENABLE = 1 << 5,
- FEAT_FUNCGATED = 1 << 6,
- FEAT_MGR_LCD2 = 1 << 7,
- FEAT_LINEBUFFERSPLIT = 1 << 8,
- FEAT_ROWREPEATENABLE = 1 << 9,
- FEAT_RESIZECONF = 1 << 10,
+ FEAT_GLOBAL_ALPHA = 1 << 0,
+ FEAT_GLOBAL_ALPHA_VID1 = 1 << 1,
+ FEAT_PRE_MULT_ALPHA = 1 << 2,
+ FEAT_LCDENABLEPOL = 1 << 3,
+ FEAT_LCDENABLESIGNAL = 1 << 4,
+ FEAT_PCKFREEENABLE = 1 << 5,
+ FEAT_FUNCGATED = 1 << 6,
+ FEAT_MGR_LCD2 = 1 << 7,
+ FEAT_LINEBUFFERSPLIT = 1 << 8,
+ FEAT_ROWREPEATENABLE = 1 << 9,
+ FEAT_RESIZECONF = 1 << 10,
/* Independent core clk divider */
- FEAT_CORE_CLK_DIV = 1 << 11,
- FEAT_LCD_CLK_SRC = 1 << 12,
+ FEAT_CORE_CLK_DIV = 1 << 11,
+ FEAT_LCD_CLK_SRC = 1 << 12,
+ /* DSI-PLL power command 0x3 is not working */
+ FEAT_DSI_PLL_PWR_BUG = 1 << 13,
+ FEAT_DSI_PLL_FREQSEL = 1 << 14,
+ FEAT_DSI_DCS_CMD_CONFIG_VC = 1 << 15,
+ FEAT_DSI_VC_OCP_WIDTH = 1 << 16,
+ FEAT_DSI_REVERSE_TXCLKESC = 1 << 17,
+ FEAT_DSI_GNQ = 1 << 18,
+ FEAT_HDMI_CTS_SWMODE = 1 << 19,
+ FEAT_HANDLE_UV_SEPARATE = 1 << 20,
+ FEAT_ATTR2 = 1 << 21,
};
/* DSS register field id */
@@ -77,7 +88,7 @@
enum omap_color_mode dss_feat_get_supported_color_modes(enum omap_plane plane);
bool dss_feat_color_mode_supported(enum omap_plane plane,
enum omap_color_mode color_mode);
-const char *dss_feat_get_clk_source_name(enum dss_clk_source id);
+const char *dss_feat_get_clk_source_name(enum omap_dss_clk_source id);
bool dss_has_feature(enum dss_feat_id id);
void dss_feat_get_reg_field(enum dss_feat_reg_field id, u8 *start, u8 *end);
diff --git a/drivers/video/omap2/dss/hdmi.c b/drivers/video/omap2/dss/hdmi.c
index a981def..b0555f4 100644
--- a/drivers/video/omap2/dss/hdmi.c
+++ b/drivers/video/omap2/dss/hdmi.c
@@ -29,10 +29,16 @@
#include <linux/mutex.h>
#include <linux/delay.h>
#include <linux/string.h>
-#include <plat/display.h>
+#include <video/omapdss.h>
+#if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
+ defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
+#include <sound/soc.h>
+#include <sound/pcm_params.h>
+#endif
#include "dss.h"
#include "hdmi.h"
+#include "dss_features.h"
static struct {
struct mutex lock;
@@ -1052,25 +1058,26 @@
cfg->timings.hsync_pol = cea_vesa_timings[code].hsync_pol;
}
-static void hdmi_compute_pll(unsigned long clkin, int phy,
- int n, struct hdmi_pll_info *pi)
+static void hdmi_compute_pll(struct omap_dss_device *dssdev, int phy,
+ struct hdmi_pll_info *pi)
{
- unsigned long refclk;
+ unsigned long clkin, refclk;
u32 mf;
+ clkin = dss_clk_get_rate(DSS_CLK_SYSCK) / 10000;
/*
* Input clock is predivided by N + 1
* out put of which is reference clk
*/
- refclk = clkin / (n + 1);
- pi->regn = n;
+ pi->regn = dssdev->clocks.hdmi.regn;
+ refclk = clkin / (pi->regn + 1);
/*
* multiplier is pixel_clk/ref_clk
* Multiplying by 100 to avoid fractional part removal
*/
- pi->regm = (phy * 100/(refclk))/100;
- pi->regm2 = 1;
+ pi->regm = (phy * 100 / (refclk)) / 100;
+ pi->regm2 = dssdev->clocks.hdmi.regm2;
/*
* fractional multiplier is remainder of the difference between
@@ -1078,14 +1085,14 @@
* multiplied by 2^18(262144) divided by the reference clock
*/
mf = (phy - pi->regm * refclk) * 262144;
- pi->regmf = mf/(refclk);
+ pi->regmf = mf / (refclk);
/*
* Dcofreq should be set to 1 if required pixel clock
* is greater than 1000MHz
*/
pi->dcofreq = phy > 1000 * 100;
- pi->regsd = ((pi->regm * clkin / 10) / ((n + 1) * 250) + 5) / 10;
+ pi->regsd = ((pi->regm * clkin / 10) / ((pi->regn + 1) * 250) + 5) / 10;
DSSDBG("M = %d Mf = %d\n", pi->regm, pi->regmf);
DSSDBG("range = %d sd = %d\n", pi->dcofreq, pi->regsd);
@@ -1106,7 +1113,7 @@
int r, code = 0;
struct hdmi_pll_info pll_data;
struct omap_video_timings *p;
- int clkin, n, phy;
+ unsigned long phy;
hdmi_enable_clocks(1);
@@ -1126,11 +1133,9 @@
dssdev->panel.timings = cea_vesa_timings[code].timings;
update_hdmi_timings(&hdmi.cfg, p, code);
- clkin = 3840; /* 38.4 MHz */
- n = 15; /* this is a constant for our math */
phy = p->pixel_clock;
- hdmi_compute_pll(clkin, phy, n, &pll_data);
+ hdmi_compute_pll(dssdev, phy, &pll_data);
hdmi_wp_video_start(0);
@@ -1160,7 +1165,7 @@
* dynamically by user. This can be moved to single location , say
* Boardfile.
*/
- dss_select_dispc_clk_source(DSS_CLK_SRC_FCK);
+ dss_select_dispc_clk_source(dssdev->clocks.dispc.dispc_fclk_src);
/* bypass TV gamma table */
dispc_enable_gamma_table(0);
@@ -1275,10 +1280,420 @@
mutex_unlock(&hdmi.lock);
}
+#if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
+ defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
+static void hdmi_wp_audio_config_format(
+ struct hdmi_audio_format *aud_fmt)
+{
+ u32 r;
+
+ DSSDBG("Enter hdmi_wp_audio_config_format\n");
+
+ r = hdmi_read_reg(HDMI_WP_AUDIO_CFG);
+ r = FLD_MOD(r, aud_fmt->stereo_channels, 26, 24);
+ r = FLD_MOD(r, aud_fmt->active_chnnls_msk, 23, 16);
+ r = FLD_MOD(r, aud_fmt->en_sig_blk_strt_end, 5, 5);
+ r = FLD_MOD(r, aud_fmt->type, 4, 4);
+ r = FLD_MOD(r, aud_fmt->justification, 3, 3);
+ r = FLD_MOD(r, aud_fmt->sample_order, 2, 2);
+ r = FLD_MOD(r, aud_fmt->samples_per_word, 1, 1);
+ r = FLD_MOD(r, aud_fmt->sample_size, 0, 0);
+ hdmi_write_reg(HDMI_WP_AUDIO_CFG, r);
+}
+
+static void hdmi_wp_audio_config_dma(struct hdmi_audio_dma *aud_dma)
+{
+ u32 r;
+
+ DSSDBG("Enter hdmi_wp_audio_config_dma\n");
+
+ r = hdmi_read_reg(HDMI_WP_AUDIO_CFG2);
+ r = FLD_MOD(r, aud_dma->transfer_size, 15, 8);
+ r = FLD_MOD(r, aud_dma->block_size, 7, 0);
+ hdmi_write_reg(HDMI_WP_AUDIO_CFG2, r);
+
+ r = hdmi_read_reg(HDMI_WP_AUDIO_CTRL);
+ r = FLD_MOD(r, aud_dma->mode, 9, 9);
+ r = FLD_MOD(r, aud_dma->fifo_threshold, 8, 0);
+ hdmi_write_reg(HDMI_WP_AUDIO_CTRL, r);
+}
+
+static void hdmi_core_audio_config(struct hdmi_core_audio_config *cfg)
+{
+ u32 r;
+
+ /* audio clock recovery parameters */
+ r = hdmi_read_reg(HDMI_CORE_AV_ACR_CTRL);
+ r = FLD_MOD(r, cfg->use_mclk, 2, 2);
+ r = FLD_MOD(r, cfg->en_acr_pkt, 1, 1);
+ r = FLD_MOD(r, cfg->cts_mode, 0, 0);
+ hdmi_write_reg(HDMI_CORE_AV_ACR_CTRL, r);
+
+ REG_FLD_MOD(HDMI_CORE_AV_N_SVAL1, cfg->n, 7, 0);
+ REG_FLD_MOD(HDMI_CORE_AV_N_SVAL2, cfg->n >> 8, 7, 0);
+ REG_FLD_MOD(HDMI_CORE_AV_N_SVAL3, cfg->n >> 16, 7, 0);
+
+ if (cfg->cts_mode == HDMI_AUDIO_CTS_MODE_SW) {
+ REG_FLD_MOD(HDMI_CORE_AV_CTS_SVAL1, cfg->cts, 7, 0);
+ REG_FLD_MOD(HDMI_CORE_AV_CTS_SVAL2, cfg->cts >> 8, 7, 0);
+ REG_FLD_MOD(HDMI_CORE_AV_CTS_SVAL3, cfg->cts >> 16, 7, 0);
+ } else {
+ /*
+ * HDMI IP uses this configuration to divide the MCLK to
+ * update CTS value.
+ */
+ REG_FLD_MOD(HDMI_CORE_AV_FREQ_SVAL, cfg->mclk_mode, 2, 0);
+
+ /* Configure clock for audio packets */
+ REG_FLD_MOD(HDMI_CORE_AV_AUD_PAR_BUSCLK_1,
+ cfg->aud_par_busclk, 7, 0);
+ REG_FLD_MOD(HDMI_CORE_AV_AUD_PAR_BUSCLK_2,
+ (cfg->aud_par_busclk >> 8), 7, 0);
+ REG_FLD_MOD(HDMI_CORE_AV_AUD_PAR_BUSCLK_3,
+ (cfg->aud_par_busclk >> 16), 7, 0);
+ }
+
+ /* Override of SPDIF sample frequency with value in I2S_CHST4 */
+ REG_FLD_MOD(HDMI_CORE_AV_SPDIF_CTRL, cfg->fs_override, 1, 1);
+
+ /* I2S parameters */
+ REG_FLD_MOD(HDMI_CORE_AV_I2S_CHST4, cfg->freq_sample, 3, 0);
+
+ r = hdmi_read_reg(HDMI_CORE_AV_I2S_IN_CTRL);
+ r = FLD_MOD(r, cfg->i2s_cfg.en_high_bitrate_aud, 7, 7);
+ r = FLD_MOD(r, cfg->i2s_cfg.sck_edge_mode, 6, 6);
+ r = FLD_MOD(r, cfg->i2s_cfg.cbit_order, 5, 5);
+ r = FLD_MOD(r, cfg->i2s_cfg.vbit, 4, 4);
+ r = FLD_MOD(r, cfg->i2s_cfg.ws_polarity, 3, 3);
+ r = FLD_MOD(r, cfg->i2s_cfg.justification, 2, 2);
+ r = FLD_MOD(r, cfg->i2s_cfg.direction, 1, 1);
+ r = FLD_MOD(r, cfg->i2s_cfg.shift, 0, 0);
+ hdmi_write_reg(HDMI_CORE_AV_I2S_IN_CTRL, r);
+
+ r = hdmi_read_reg(HDMI_CORE_AV_I2S_CHST5);
+ r = FLD_MOD(r, cfg->freq_sample, 7, 4);
+ r = FLD_MOD(r, cfg->i2s_cfg.word_length, 3, 1);
+ r = FLD_MOD(r, cfg->i2s_cfg.word_max_length, 0, 0);
+ hdmi_write_reg(HDMI_CORE_AV_I2S_CHST5, r);
+
+ REG_FLD_MOD(HDMI_CORE_AV_I2S_IN_LEN, cfg->i2s_cfg.in_length_bits, 3, 0);
+
+ /* Audio channels and mode parameters */
+ REG_FLD_MOD(HDMI_CORE_AV_HDMI_CTRL, cfg->layout, 2, 1);
+ r = hdmi_read_reg(HDMI_CORE_AV_AUD_MODE);
+ r = FLD_MOD(r, cfg->i2s_cfg.active_sds, 7, 4);
+ r = FLD_MOD(r, cfg->en_dsd_audio, 3, 3);
+ r = FLD_MOD(r, cfg->en_parallel_aud_input, 2, 2);
+ r = FLD_MOD(r, cfg->en_spdif, 1, 1);
+ hdmi_write_reg(HDMI_CORE_AV_AUD_MODE, r);
+}
+
+static void hdmi_core_audio_infoframe_config(
+ struct hdmi_core_infoframe_audio *info_aud)
+{
+ u8 val;
+ u8 sum = 0, checksum = 0;
+
+ /*
+ * Set audio info frame type, version and length as
+ * described in HDMI 1.4a Section 8.2.2 specification.
+ * Checksum calculation is defined in Section 5.3.5.
+ */
+ hdmi_write_reg(HDMI_CORE_AV_AUDIO_TYPE, 0x84);
+ hdmi_write_reg(HDMI_CORE_AV_AUDIO_VERS, 0x01);
+ hdmi_write_reg(HDMI_CORE_AV_AUDIO_LEN, 0x0a);
+ sum += 0x84 + 0x001 + 0x00a;
+
+ val = (info_aud->db1_coding_type << 4)
+ | (info_aud->db1_channel_count - 1);
+ hdmi_write_reg(HDMI_CORE_AV_AUD_DBYTE(0), val);
+ sum += val;
+
+ val = (info_aud->db2_sample_freq << 2) | info_aud->db2_sample_size;
+ hdmi_write_reg(HDMI_CORE_AV_AUD_DBYTE(1), val);
+ sum += val;
+
+ hdmi_write_reg(HDMI_CORE_AV_AUD_DBYTE(2), 0x00);
+
+ val = info_aud->db4_channel_alloc;
+ hdmi_write_reg(HDMI_CORE_AV_AUD_DBYTE(3), val);
+ sum += val;
+
+ val = (info_aud->db5_downmix_inh << 7) | (info_aud->db5_lsv << 3);
+ hdmi_write_reg(HDMI_CORE_AV_AUD_DBYTE(4), val);
+ sum += val;
+
+ hdmi_write_reg(HDMI_CORE_AV_AUD_DBYTE(5), 0x00);
+ hdmi_write_reg(HDMI_CORE_AV_AUD_DBYTE(6), 0x00);
+ hdmi_write_reg(HDMI_CORE_AV_AUD_DBYTE(7), 0x00);
+ hdmi_write_reg(HDMI_CORE_AV_AUD_DBYTE(8), 0x00);
+ hdmi_write_reg(HDMI_CORE_AV_AUD_DBYTE(9), 0x00);
+
+ checksum = 0x100 - sum;
+ hdmi_write_reg(HDMI_CORE_AV_AUDIO_CHSUM, checksum);
+
+ /*
+ * TODO: Add MPEG and SPD enable and repeat cfg when EDID parsing
+ * is available.
+ */
+}
+
+static int hdmi_config_audio_acr(u32 sample_freq, u32 *n, u32 *cts)
+{
+ u32 r;
+ u32 deep_color = 0;
+ u32 pclk = hdmi.cfg.timings.timings.pixel_clock;
+
+ if (n == NULL || cts == NULL)
+ return -EINVAL;
+ /*
+ * Obtain current deep color configuration. This needed
+ * to calculate the TMDS clock based on the pixel clock.
+ */
+ r = REG_GET(HDMI_WP_VIDEO_CFG, 1, 0);
+ switch (r) {
+ case 1: /* No deep color selected */
+ deep_color = 100;
+ break;
+ case 2: /* 10-bit deep color selected */
+ deep_color = 125;
+ break;
+ case 3: /* 12-bit deep color selected */
+ deep_color = 150;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ switch (sample_freq) {
+ case 32000:
+ if ((deep_color == 125) && ((pclk == 54054)
+ || (pclk == 74250)))
+ *n = 8192;
+ else
+ *n = 4096;
+ break;
+ case 44100:
+ *n = 6272;
+ break;
+ case 48000:
+ if ((deep_color == 125) && ((pclk == 54054)
+ || (pclk == 74250)))
+ *n = 8192;
+ else
+ *n = 6144;
+ break;
+ default:
+ *n = 0;
+ return -EINVAL;
+ }
+
+ /* Calculate CTS. See HDMI 1.3a or 1.4a specifications */
+ *cts = pclk * (*n / 128) * deep_color / (sample_freq / 10);
+
+ return 0;
+}
+
+static int hdmi_audio_hw_params(struct snd_pcm_substream *substream,
+ struct snd_pcm_hw_params *params,
+ struct snd_soc_dai *dai)
+{
+ struct hdmi_audio_format audio_format;
+ struct hdmi_audio_dma audio_dma;
+ struct hdmi_core_audio_config core_cfg;
+ struct hdmi_core_infoframe_audio aud_if_cfg;
+ int err, n, cts;
+ enum hdmi_core_audio_sample_freq sample_freq;
+
+ switch (params_format(params)) {
+ case SNDRV_PCM_FORMAT_S16_LE:
+ core_cfg.i2s_cfg.word_max_length =
+ HDMI_AUDIO_I2S_MAX_WORD_20BITS;
+ core_cfg.i2s_cfg.word_length = HDMI_AUDIO_I2S_CHST_WORD_16_BITS;
+ core_cfg.i2s_cfg.in_length_bits =
+ HDMI_AUDIO_I2S_INPUT_LENGTH_16;
+ core_cfg.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_LEFT;
+ audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_TWOSAMPLES;
+ audio_format.sample_size = HDMI_AUDIO_SAMPLE_16BITS;
+ audio_format.justification = HDMI_AUDIO_JUSTIFY_LEFT;
+ audio_dma.transfer_size = 0x10;
+ break;
+ case SNDRV_PCM_FORMAT_S24_LE:
+ core_cfg.i2s_cfg.word_max_length =
+ HDMI_AUDIO_I2S_MAX_WORD_24BITS;
+ core_cfg.i2s_cfg.word_length = HDMI_AUDIO_I2S_CHST_WORD_24_BITS;
+ core_cfg.i2s_cfg.in_length_bits =
+ HDMI_AUDIO_I2S_INPUT_LENGTH_24;
+ audio_format.samples_per_word = HDMI_AUDIO_ONEWORD_ONESAMPLE;
+ audio_format.sample_size = HDMI_AUDIO_SAMPLE_24BITS;
+ audio_format.justification = HDMI_AUDIO_JUSTIFY_RIGHT;
+ core_cfg.i2s_cfg.justification = HDMI_AUDIO_JUSTIFY_RIGHT;
+ audio_dma.transfer_size = 0x20;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ switch (params_rate(params)) {
+ case 32000:
+ sample_freq = HDMI_AUDIO_FS_32000;
+ break;
+ case 44100:
+ sample_freq = HDMI_AUDIO_FS_44100;
+ break;
+ case 48000:
+ sample_freq = HDMI_AUDIO_FS_48000;
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ err = hdmi_config_audio_acr(params_rate(params), &n, &cts);
+ if (err < 0)
+ return err;
+
+ /* Audio wrapper config */
+ audio_format.stereo_channels = HDMI_AUDIO_STEREO_ONECHANNEL;
+ audio_format.active_chnnls_msk = 0x03;
+ audio_format.type = HDMI_AUDIO_TYPE_LPCM;
+ audio_format.sample_order = HDMI_AUDIO_SAMPLE_LEFT_FIRST;
+ /* Disable start/stop signals of IEC 60958 blocks */
+ audio_format.en_sig_blk_strt_end = HDMI_AUDIO_BLOCK_SIG_STARTEND_OFF;
+
+ audio_dma.block_size = 0xC0;
+ audio_dma.mode = HDMI_AUDIO_TRANSF_DMA;
+ audio_dma.fifo_threshold = 0x20; /* in number of samples */
+
+ hdmi_wp_audio_config_dma(&audio_dma);
+ hdmi_wp_audio_config_format(&audio_format);
+
+ /*
+ * I2S config
+ */
+ core_cfg.i2s_cfg.en_high_bitrate_aud = false;
+ /* Only used with high bitrate audio */
+ core_cfg.i2s_cfg.cbit_order = false;
+ /* Serial data and word select should change on sck rising edge */
+ core_cfg.i2s_cfg.sck_edge_mode = HDMI_AUDIO_I2S_SCK_EDGE_RISING;
+ core_cfg.i2s_cfg.vbit = HDMI_AUDIO_I2S_VBIT_FOR_PCM;
+ /* Set I2S word select polarity */
+ core_cfg.i2s_cfg.ws_polarity = HDMI_AUDIO_I2S_WS_POLARITY_LOW_IS_LEFT;
+ core_cfg.i2s_cfg.direction = HDMI_AUDIO_I2S_MSB_SHIFTED_FIRST;
+ /* Set serial data to word select shift. See Phillips spec. */
+ core_cfg.i2s_cfg.shift = HDMI_AUDIO_I2S_FIRST_BIT_SHIFT;
+ /* Enable one of the four available serial data channels */
+ core_cfg.i2s_cfg.active_sds = HDMI_AUDIO_I2S_SD0_EN;
+
+ /* Core audio config */
+ core_cfg.freq_sample = sample_freq;
+ core_cfg.n = n;
+ core_cfg.cts = cts;
+ if (dss_has_feature(FEAT_HDMI_CTS_SWMODE)) {
+ core_cfg.aud_par_busclk = 0;
+ core_cfg.cts_mode = HDMI_AUDIO_CTS_MODE_SW;
+ core_cfg.use_mclk = false;
+ } else {
+ core_cfg.aud_par_busclk = (((128 * 31) - 1) << 8);
+ core_cfg.cts_mode = HDMI_AUDIO_CTS_MODE_HW;
+ core_cfg.use_mclk = true;
+ core_cfg.mclk_mode = HDMI_AUDIO_MCLK_128FS;
+ }
+ core_cfg.layout = HDMI_AUDIO_LAYOUT_2CH;
+ core_cfg.en_spdif = false;
+ /* Use sample frequency from channel status word */
+ core_cfg.fs_override = true;
+ /* Enable ACR packets */
+ core_cfg.en_acr_pkt = true;
+ /* Disable direct streaming digital audio */
+ core_cfg.en_dsd_audio = false;
+ /* Use parallel audio interface */
+ core_cfg.en_parallel_aud_input = true;
+
+ hdmi_core_audio_config(&core_cfg);
+
+ /*
+ * Configure packet
+ * info frame audio see doc CEA861-D page 74
+ */
+ aud_if_cfg.db1_coding_type = HDMI_INFOFRAME_AUDIO_DB1CT_FROM_STREAM;
+ aud_if_cfg.db1_channel_count = 2;
+ aud_if_cfg.db2_sample_freq = HDMI_INFOFRAME_AUDIO_DB2SF_FROM_STREAM;
+ aud_if_cfg.db2_sample_size = HDMI_INFOFRAME_AUDIO_DB2SS_FROM_STREAM;
+ aud_if_cfg.db4_channel_alloc = 0x00;
+ aud_if_cfg.db5_downmix_inh = false;
+ aud_if_cfg.db5_lsv = 0;
+
+ hdmi_core_audio_infoframe_config(&aud_if_cfg);
+ return 0;
+}
+
+static int hdmi_audio_trigger(struct snd_pcm_substream *substream, int cmd,
+ struct snd_soc_dai *dai)
+{
+ int err = 0;
+ switch (cmd) {
+ case SNDRV_PCM_TRIGGER_START:
+ case SNDRV_PCM_TRIGGER_RESUME:
+ case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
+ REG_FLD_MOD(HDMI_CORE_AV_AUD_MODE, 1, 0, 0);
+ REG_FLD_MOD(HDMI_WP_AUDIO_CTRL, 1, 31, 31);
+ REG_FLD_MOD(HDMI_WP_AUDIO_CTRL, 1, 30, 30);
+ break;
+
+ case SNDRV_PCM_TRIGGER_STOP:
+ case SNDRV_PCM_TRIGGER_SUSPEND:
+ case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
+ REG_FLD_MOD(HDMI_CORE_AV_AUD_MODE, 0, 0, 0);
+ REG_FLD_MOD(HDMI_WP_AUDIO_CTRL, 0, 30, 30);
+ REG_FLD_MOD(HDMI_WP_AUDIO_CTRL, 0, 31, 31);
+ break;
+ default:
+ err = -EINVAL;
+ }
+ return err;
+}
+
+static int hdmi_audio_startup(struct snd_pcm_substream *substream,
+ struct snd_soc_dai *dai)
+{
+ if (!hdmi.mode) {
+ pr_err("Current video settings do not support audio.\n");
+ return -EIO;
+ }
+ return 0;
+}
+
+static struct snd_soc_codec_driver hdmi_audio_codec_drv = {
+};
+
+static struct snd_soc_dai_ops hdmi_audio_codec_ops = {
+ .hw_params = hdmi_audio_hw_params,
+ .trigger = hdmi_audio_trigger,
+ .startup = hdmi_audio_startup,
+};
+
+static struct snd_soc_dai_driver hdmi_codec_dai_drv = {
+ .name = "hdmi-audio-codec",
+ .playback = {
+ .channels_min = 2,
+ .channels_max = 2,
+ .rates = SNDRV_PCM_RATE_32000 |
+ SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_48000,
+ .formats = SNDRV_PCM_FMTBIT_S16_LE |
+ SNDRV_PCM_FMTBIT_S24_LE,
+ },
+ .ops = &hdmi_audio_codec_ops,
+};
+#endif
+
/* HDMI HW IP initialisation */
static int omapdss_hdmihw_probe(struct platform_device *pdev)
{
struct resource *hdmi_mem;
+#if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
+ defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
+ int ret;
+#endif
hdmi.pdata = pdev->dev.platform_data;
hdmi.pdev = pdev;
@@ -1300,6 +1715,17 @@
hdmi_panel_init();
+#if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
+ defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
+
+ /* Register ASoC codec DAI */
+ ret = snd_soc_register_codec(&pdev->dev, &hdmi_audio_codec_drv,
+ &hdmi_codec_dai_drv, 1);
+ if (ret) {
+ DSSERR("can't register ASoC HDMI audio codec\n");
+ return ret;
+ }
+#endif
return 0;
}
@@ -1307,6 +1733,11 @@
{
hdmi_panel_exit();
+#if defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI) || \
+ defined(CONFIG_SND_OMAP_SOC_OMAP4_HDMI_MODULE)
+ snd_soc_unregister_codec(&pdev->dev);
+#endif
+
iounmap(hdmi.base_wp);
return 0;
diff --git a/drivers/video/omap2/dss/hdmi.h b/drivers/video/omap2/dss/hdmi.h
index 9887ab9..c885f9c 100644
--- a/drivers/video/omap2/dss/hdmi.h
+++ b/drivers/video/omap2/dss/hdmi.h
@@ -22,7 +22,7 @@
#define _OMAP4_DSS_HDMI_H_
#include <linux/string.h>
-#include <plat/display.h>
+#include <video/omapdss.h>
#define HDMI_WP 0x0
#define HDMI_CORE_SYS 0x400
@@ -48,6 +48,10 @@
#define HDMI_WP_VIDEO_TIMING_H HDMI_WP_REG(0x68)
#define HDMI_WP_VIDEO_TIMING_V HDMI_WP_REG(0x6C)
#define HDMI_WP_WP_CLK HDMI_WP_REG(0x70)
+#define HDMI_WP_AUDIO_CFG HDMI_WP_REG(0x80)
+#define HDMI_WP_AUDIO_CFG2 HDMI_WP_REG(0x84)
+#define HDMI_WP_AUDIO_CTRL HDMI_WP_REG(0x88)
+#define HDMI_WP_AUDIO_DATA HDMI_WP_REG(0x8C)
/* HDMI IP Core System */
#define HDMI_CORE_SYS_REG(idx) HDMI_REG(HDMI_CORE_SYS + idx)
@@ -105,6 +109,8 @@
#define HDMI_CORE_AV_AVI_DBYTE_NELEMS HDMI_CORE_AV_REG(15)
#define HDMI_CORE_AV_SPD_DBYTE HDMI_CORE_AV_REG(0x190)
#define HDMI_CORE_AV_SPD_DBYTE_NELEMS HDMI_CORE_AV_REG(27)
+#define HDMI_CORE_AV_AUD_DBYTE(n) HDMI_CORE_AV_REG(n * 4 + 0x210)
+#define HDMI_CORE_AV_AUD_DBYTE_NELEMS HDMI_CORE_AV_REG(10)
#define HDMI_CORE_AV_MPEG_DBYTE HDMI_CORE_AV_REG(0x290)
#define HDMI_CORE_AV_MPEG_DBYTE_NELEMS HDMI_CORE_AV_REG(27)
#define HDMI_CORE_AV_GEN_DBYTE HDMI_CORE_AV_REG(0x300)
@@ -153,6 +159,10 @@
#define HDMI_CORE_AV_SPD_VERS HDMI_CORE_AV_REG(0x184)
#define HDMI_CORE_AV_SPD_LEN HDMI_CORE_AV_REG(0x188)
#define HDMI_CORE_AV_SPD_CHSUM HDMI_CORE_AV_REG(0x18C)
+#define HDMI_CORE_AV_AUDIO_TYPE HDMI_CORE_AV_REG(0x200)
+#define HDMI_CORE_AV_AUDIO_VERS HDMI_CORE_AV_REG(0x204)
+#define HDMI_CORE_AV_AUDIO_LEN HDMI_CORE_AV_REG(0x208)
+#define HDMI_CORE_AV_AUDIO_CHSUM HDMI_CORE_AV_REG(0x20C)
#define HDMI_CORE_AV_MPEG_TYPE HDMI_CORE_AV_REG(0x280)
#define HDMI_CORE_AV_MPEG_VERS HDMI_CORE_AV_REG(0x284)
#define HDMI_CORE_AV_MPEG_LEN HDMI_CORE_AV_REG(0x288)
@@ -272,7 +282,7 @@
HDMI_PACKETREPEATOFF = 0
};
-/* INFOFRAME_AVI_ definitions */
+/* INFOFRAME_AVI_ and INFOFRAME_AUDIO_ definitions */
enum hdmi_core_infoframe {
HDMI_INFOFRAME_AVI_DB1Y_RGB = 0,
HDMI_INFOFRAME_AVI_DB1Y_YUV422 = 1,
@@ -317,7 +327,36 @@
HDMI_INFOFRAME_AVI_DB5PR_7 = 6,
HDMI_INFOFRAME_AVI_DB5PR_8 = 7,
HDMI_INFOFRAME_AVI_DB5PR_9 = 8,
- HDMI_INFOFRAME_AVI_DB5PR_10 = 9
+ HDMI_INFOFRAME_AVI_DB5PR_10 = 9,
+ HDMI_INFOFRAME_AUDIO_DB1CT_FROM_STREAM = 0,
+ HDMI_INFOFRAME_AUDIO_DB1CT_IEC60958 = 1,
+ HDMI_INFOFRAME_AUDIO_DB1CT_AC3 = 2,
+ HDMI_INFOFRAME_AUDIO_DB1CT_MPEG1 = 3,
+ HDMI_INFOFRAME_AUDIO_DB1CT_MP3 = 4,
+ HDMI_INFOFRAME_AUDIO_DB1CT_MPEG2_MULTICH = 5,
+ HDMI_INFOFRAME_AUDIO_DB1CT_AAC = 6,
+ HDMI_INFOFRAME_AUDIO_DB1CT_DTS = 7,
+ HDMI_INFOFRAME_AUDIO_DB1CT_ATRAC = 8,
+ HDMI_INFOFRAME_AUDIO_DB1CT_ONEBIT = 9,
+ HDMI_INFOFRAME_AUDIO_DB1CT_DOLBY_DIGITAL_PLUS = 10,
+ HDMI_INFOFRAME_AUDIO_DB1CT_DTS_HD = 11,
+ HDMI_INFOFRAME_AUDIO_DB1CT_MAT = 12,
+ HDMI_INFOFRAME_AUDIO_DB1CT_DST = 13,
+ HDMI_INFOFRAME_AUDIO_DB1CT_WMA_PRO = 14,
+ HDMI_INFOFRAME_AUDIO_DB2SF_FROM_STREAM = 0,
+ HDMI_INFOFRAME_AUDIO_DB2SF_32000 = 1,
+ HDMI_INFOFRAME_AUDIO_DB2SF_44100 = 2,
+ HDMI_INFOFRAME_AUDIO_DB2SF_48000 = 3,
+ HDMI_INFOFRAME_AUDIO_DB2SF_88200 = 4,
+ HDMI_INFOFRAME_AUDIO_DB2SF_96000 = 5,
+ HDMI_INFOFRAME_AUDIO_DB2SF_176400 = 6,
+ HDMI_INFOFRAME_AUDIO_DB2SF_192000 = 7,
+ HDMI_INFOFRAME_AUDIO_DB2SS_FROM_STREAM = 0,
+ HDMI_INFOFRAME_AUDIO_DB2SS_16BIT = 1,
+ HDMI_INFOFRAME_AUDIO_DB2SS_20BIT = 2,
+ HDMI_INFOFRAME_AUDIO_DB2SS_24BIT = 3,
+ HDMI_INFOFRAME_AUDIO_DB5_DM_INH_PERMITTED = 0,
+ HDMI_INFOFRAME_AUDIO_DB5_DM_INH_PROHIBITED = 1
};
enum hdmi_packing_mode {
@@ -327,6 +366,121 @@
HDMI_PACK_ALREADYPACKED = 7
};
+enum hdmi_core_audio_sample_freq {
+ HDMI_AUDIO_FS_32000 = 0x3,
+ HDMI_AUDIO_FS_44100 = 0x0,
+ HDMI_AUDIO_FS_48000 = 0x2,
+ HDMI_AUDIO_FS_88200 = 0x8,
+ HDMI_AUDIO_FS_96000 = 0xA,
+ HDMI_AUDIO_FS_176400 = 0xC,
+ HDMI_AUDIO_FS_192000 = 0xE,
+ HDMI_AUDIO_FS_NOT_INDICATED = 0x1
+};
+
+enum hdmi_core_audio_layout {
+ HDMI_AUDIO_LAYOUT_2CH = 0,
+ HDMI_AUDIO_LAYOUT_8CH = 1
+};
+
+enum hdmi_core_cts_mode {
+ HDMI_AUDIO_CTS_MODE_HW = 0,
+ HDMI_AUDIO_CTS_MODE_SW = 1
+};
+
+enum hdmi_stereo_channels {
+ HDMI_AUDIO_STEREO_NOCHANNELS = 0,
+ HDMI_AUDIO_STEREO_ONECHANNEL = 1,
+ HDMI_AUDIO_STEREO_TWOCHANNELS = 2,
+ HDMI_AUDIO_STEREO_THREECHANNELS = 3,
+ HDMI_AUDIO_STEREO_FOURCHANNELS = 4
+};
+
+enum hdmi_audio_type {
+ HDMI_AUDIO_TYPE_LPCM = 0,
+ HDMI_AUDIO_TYPE_IEC = 1
+};
+
+enum hdmi_audio_justify {
+ HDMI_AUDIO_JUSTIFY_LEFT = 0,
+ HDMI_AUDIO_JUSTIFY_RIGHT = 1
+};
+
+enum hdmi_audio_sample_order {
+ HDMI_AUDIO_SAMPLE_RIGHT_FIRST = 0,
+ HDMI_AUDIO_SAMPLE_LEFT_FIRST = 1
+};
+
+enum hdmi_audio_samples_perword {
+ HDMI_AUDIO_ONEWORD_ONESAMPLE = 0,
+ HDMI_AUDIO_ONEWORD_TWOSAMPLES = 1
+};
+
+enum hdmi_audio_sample_size {
+ HDMI_AUDIO_SAMPLE_16BITS = 0,
+ HDMI_AUDIO_SAMPLE_24BITS = 1
+};
+
+enum hdmi_audio_transf_mode {
+ HDMI_AUDIO_TRANSF_DMA = 0,
+ HDMI_AUDIO_TRANSF_IRQ = 1
+};
+
+enum hdmi_audio_blk_strt_end_sig {
+ HDMI_AUDIO_BLOCK_SIG_STARTEND_ON = 0,
+ HDMI_AUDIO_BLOCK_SIG_STARTEND_OFF = 1
+};
+
+enum hdmi_audio_i2s_config {
+ HDMI_AUDIO_I2S_WS_POLARITY_LOW_IS_LEFT = 0,
+ HDMI_AUDIO_I2S_WS_POLARIT_YLOW_IS_RIGHT = 1,
+ HDMI_AUDIO_I2S_MSB_SHIFTED_FIRST = 0,
+ HDMI_AUDIO_I2S_LSB_SHIFTED_FIRST = 1,
+ HDMI_AUDIO_I2S_MAX_WORD_20BITS = 0,
+ HDMI_AUDIO_I2S_MAX_WORD_24BITS = 1,
+ HDMI_AUDIO_I2S_CHST_WORD_NOT_SPECIFIED = 0,
+ HDMI_AUDIO_I2S_CHST_WORD_16_BITS = 1,
+ HDMI_AUDIO_I2S_CHST_WORD_17_BITS = 6,
+ HDMI_AUDIO_I2S_CHST_WORD_18_BITS = 2,
+ HDMI_AUDIO_I2S_CHST_WORD_19_BITS = 4,
+ HDMI_AUDIO_I2S_CHST_WORD_20_BITS_20MAX = 5,
+ HDMI_AUDIO_I2S_CHST_WORD_20_BITS_24MAX = 1,
+ HDMI_AUDIO_I2S_CHST_WORD_21_BITS = 6,
+ HDMI_AUDIO_I2S_CHST_WORD_22_BITS = 2,
+ HDMI_AUDIO_I2S_CHST_WORD_23_BITS = 4,
+ HDMI_AUDIO_I2S_CHST_WORD_24_BITS = 5,
+ HDMI_AUDIO_I2S_SCK_EDGE_FALLING = 0,
+ HDMI_AUDIO_I2S_SCK_EDGE_RISING = 1,
+ HDMI_AUDIO_I2S_VBIT_FOR_PCM = 0,
+ HDMI_AUDIO_I2S_VBIT_FOR_COMPRESSED = 1,
+ HDMI_AUDIO_I2S_INPUT_LENGTH_NA = 0,
+ HDMI_AUDIO_I2S_INPUT_LENGTH_16 = 2,
+ HDMI_AUDIO_I2S_INPUT_LENGTH_17 = 12,
+ HDMI_AUDIO_I2S_INPUT_LENGTH_18 = 4,
+ HDMI_AUDIO_I2S_INPUT_LENGTH_19 = 8,
+ HDMI_AUDIO_I2S_INPUT_LENGTH_20 = 10,
+ HDMI_AUDIO_I2S_INPUT_LENGTH_21 = 13,
+ HDMI_AUDIO_I2S_INPUT_LENGTH_22 = 5,
+ HDMI_AUDIO_I2S_INPUT_LENGTH_23 = 9,
+ HDMI_AUDIO_I2S_INPUT_LENGTH_24 = 11,
+ HDMI_AUDIO_I2S_FIRST_BIT_SHIFT = 0,
+ HDMI_AUDIO_I2S_FIRST_BIT_NO_SHIFT = 1,
+ HDMI_AUDIO_I2S_SD0_EN = 1,
+ HDMI_AUDIO_I2S_SD1_EN = 1 << 1,
+ HDMI_AUDIO_I2S_SD2_EN = 1 << 2,
+ HDMI_AUDIO_I2S_SD3_EN = 1 << 3,
+};
+
+enum hdmi_audio_mclk_mode {
+ HDMI_AUDIO_MCLK_128FS = 0,
+ HDMI_AUDIO_MCLK_256FS = 1,
+ HDMI_AUDIO_MCLK_384FS = 2,
+ HDMI_AUDIO_MCLK_512FS = 3,
+ HDMI_AUDIO_MCLK_768FS = 4,
+ HDMI_AUDIO_MCLK_1024FS = 5,
+ HDMI_AUDIO_MCLK_1152FS = 6,
+ HDMI_AUDIO_MCLK_192FS = 7
+};
+
struct hdmi_core_video_config {
enum hdmi_core_inputbus_width ip_bus_width;
enum hdmi_core_dither_trunc op_dither_truc;
@@ -376,6 +530,19 @@
u16 db12_13_pixel_sofright;
/* Pixel number start of right bar */
};
+/*
+ * Refer to section 8.2 in HDMI 1.3 specification for
+ * details about infoframe databytes
+ */
+struct hdmi_core_infoframe_audio {
+ u8 db1_coding_type;
+ u8 db1_channel_count;
+ u8 db2_sample_freq;
+ u8 db2_sample_size;
+ u8 db4_channel_alloc;
+ bool db5_downmix_inh;
+ u8 db5_lsv; /* Level shift values for downmix */
+};
struct hdmi_core_packet_enable_repeat {
u32 audio_pkt;
@@ -412,4 +579,53 @@
struct hdmi_cm cm;
};
+struct hdmi_audio_format {
+ enum hdmi_stereo_channels stereo_channels;
+ u8 active_chnnls_msk;
+ enum hdmi_audio_type type;
+ enum hdmi_audio_justify justification;
+ enum hdmi_audio_sample_order sample_order;
+ enum hdmi_audio_samples_perword samples_per_word;
+ enum hdmi_audio_sample_size sample_size;
+ enum hdmi_audio_blk_strt_end_sig en_sig_blk_strt_end;
+};
+
+struct hdmi_audio_dma {
+ u8 transfer_size;
+ u8 block_size;
+ enum hdmi_audio_transf_mode mode;
+ u16 fifo_threshold;
+};
+
+struct hdmi_core_audio_i2s_config {
+ u8 word_max_length;
+ u8 word_length;
+ u8 in_length_bits;
+ u8 justification;
+ u8 en_high_bitrate_aud;
+ u8 sck_edge_mode;
+ u8 cbit_order;
+ u8 vbit;
+ u8 ws_polarity;
+ u8 direction;
+ u8 shift;
+ u8 active_sds;
+};
+
+struct hdmi_core_audio_config {
+ struct hdmi_core_audio_i2s_config i2s_cfg;
+ enum hdmi_core_audio_sample_freq freq_sample;
+ bool fs_override;
+ u32 n;
+ u32 cts;
+ u32 aud_par_busclk;
+ enum hdmi_core_audio_layout layout;
+ enum hdmi_core_cts_mode cts_mode;
+ bool use_mclk;
+ enum hdmi_audio_mclk_mode mclk_mode;
+ bool en_acr_pkt;
+ bool en_dsd_audio;
+ bool en_parallel_aud_input;
+ bool en_spdif;
+};
#endif
diff --git a/drivers/video/omap2/dss/hdmi_omap4_panel.c b/drivers/video/omap2/dss/hdmi_omap4_panel.c
index ffb5de9..7d4f2bd 100644
--- a/drivers/video/omap2/dss/hdmi_omap4_panel.c
+++ b/drivers/video/omap2/dss/hdmi_omap4_panel.c
@@ -24,7 +24,7 @@
#include <linux/io.h>
#include <linux/mutex.h>
#include <linux/module.h>
-#include <plat/display.h>
+#include <video/omapdss.h>
#include "dss.h"
diff --git a/drivers/video/omap2/dss/manager.c b/drivers/video/omap2/dss/manager.c
index bcd37ec..9aeea50 100644
--- a/drivers/video/omap2/dss/manager.c
+++ b/drivers/video/omap2/dss/manager.c
@@ -29,7 +29,7 @@
#include <linux/spinlock.h>
#include <linux/jiffies.h>
-#include <plat/display.h>
+#include <video/omapdss.h>
#include <plat/cpu.h>
#include "dss.h"
@@ -393,6 +393,7 @@
u32 paddr;
void __iomem *vaddr;
+ u32 p_uv_addr; /* relevant for NV12 format only */
u16 screen_width;
u16 width;
u16 height;
@@ -775,10 +776,17 @@
}
switch (c->color_mode) {
+ case OMAP_DSS_COLOR_NV12:
+ bpp = 8;
+ break;
case OMAP_DSS_COLOR_RGB16:
case OMAP_DSS_COLOR_ARGB16:
case OMAP_DSS_COLOR_YUV2:
case OMAP_DSS_COLOR_UYVY:
+ case OMAP_DSS_COLOR_RGBA16:
+ case OMAP_DSS_COLOR_RGBX16:
+ case OMAP_DSS_COLOR_ARGB16_1555:
+ case OMAP_DSS_COLOR_XRGB16_1555:
bpp = 16;
break;
@@ -854,7 +862,8 @@
c->mirror,
c->global_alpha,
c->pre_mult_alpha,
- c->channel);
+ c->channel,
+ c->p_uv_addr);
if (r) {
/* this shouldn't happen */
@@ -1269,6 +1278,7 @@
oc->paddr = ovl->info.paddr;
oc->vaddr = ovl->info.vaddr;
+ oc->p_uv_addr = ovl->info.p_uv_addr;
oc->screen_width = ovl->info.screen_width;
oc->width = ovl->info.width;
oc->height = ovl->info.height;
diff --git a/drivers/video/omap2/dss/overlay.c b/drivers/video/omap2/dss/overlay.c
index f1aca6d..0f08025 100644
--- a/drivers/video/omap2/dss/overlay.c
+++ b/drivers/video/omap2/dss/overlay.c
@@ -31,7 +31,7 @@
#include <linux/delay.h>
#include <linux/slab.h>
-#include <plat/display.h>
+#include <video/omapdss.h>
#include <plat/cpu.h>
#include "dss.h"
@@ -201,12 +201,16 @@
static ssize_t overlay_enabled_store(struct omap_overlay *ovl, const char *buf,
size_t size)
{
- int r;
+ int r, enable;
struct omap_overlay_info info;
ovl->get_overlay_info(ovl, &info);
- info.enabled = simple_strtoul(buf, NULL, 10);
+ r = kstrtoint(buf, 0, &enable);
+ if (r)
+ return r;
+
+ info.enabled = !!enable;
r = ovl->set_overlay_info(ovl, &info);
if (r)
@@ -231,8 +235,13 @@
const char *buf, size_t size)
{
int r;
+ u8 alpha;
struct omap_overlay_info info;
+ r = kstrtou8(buf, 0, &alpha);
+ if (r)
+ return r;
+
ovl->get_overlay_info(ovl, &info);
/* Video1 plane does not support global alpha
@@ -242,7 +251,7 @@
ovl->id == OMAP_DSS_VIDEO1)
info.global_alpha = 255;
else
- info.global_alpha = simple_strtoul(buf, NULL, 10);
+ info.global_alpha = alpha;
r = ovl->set_overlay_info(ovl, &info);
if (r)
@@ -268,8 +277,13 @@
const char *buf, size_t size)
{
int r;
+ u8 alpha;
struct omap_overlay_info info;
+ r = kstrtou8(buf, 0, &alpha);
+ if (r)
+ return r;
+
ovl->get_overlay_info(ovl, &info);
/* only GFX and Video2 plane support pre alpha multiplied
@@ -279,7 +293,7 @@
ovl->id == OMAP_DSS_VIDEO1)
info.pre_mult_alpha = 0;
else
- info.pre_mult_alpha = simple_strtoul(buf, NULL, 10);
+ info.pre_mult_alpha = alpha;
r = ovl->set_overlay_info(ovl, &info);
if (r)
@@ -491,13 +505,18 @@
ovl->manager = mgr;
dss_clk_enable(DSS_CLK_ICK | DSS_CLK_FCK);
- /* XXX: on manual update display, in auto update mode, a bug happens
- * here. When an overlay is first enabled on LCD, then it's disabled,
- * and the manager is changed to TV, we sometimes get SYNC_LOST_DIGIT
- * errors. Waiting before changing the channel_out fixes it. I'm
- * guessing that the overlay is still somehow being used for the LCD,
- * but I don't understand how or why. */
- msleep(40);
+ /* XXX: When there is an overlay on a DSI manual update display, and
+ * the overlay is first disabled, then moved to tv, and enabled, we
+ * seem to get SYNC_LOST_DIGIT error.
+ *
+ * Waiting doesn't seem to help, but updating the manual update display
+ * after disabling the overlay seems to fix this. This hints that the
+ * overlay is perhaps somehow tied to the LCD output until the output
+ * is updated.
+ *
+ * Userspace workaround for this is to update the LCD after disabling
+ * the overlay, but before moving the overlay to TV.
+ */
dispc_set_channel_out(ovl->id, mgr->id);
dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
diff --git a/drivers/video/omap2/dss/rfbi.c b/drivers/video/omap2/dss/rfbi.c
index 5ea17f4..c06fbe0 100644
--- a/drivers/video/omap2/dss/rfbi.c
+++ b/drivers/video/omap2/dss/rfbi.c
@@ -32,8 +32,9 @@
#include <linux/ktime.h>
#include <linux/hrtimer.h>
#include <linux/seq_file.h>
+#include <linux/semaphore.h>
-#include <plat/display.h>
+#include <video/omapdss.h>
#include "dss.h"
struct rfbi_reg { u16 idx; };
@@ -65,9 +66,6 @@
#define REG_FLD_MOD(idx, val, start, end) \
rfbi_write_reg(idx, FLD_MOD(rfbi_read_reg(idx), val, start, end))
-/* To work around an RFBI transfer rate limitation */
-#define OMAP_RFBI_RATE_LIMIT 1
-
enum omap_rfbi_cycleformat {
OMAP_DSS_RFBI_CYCLEFORMAT_1_1 = 0,
OMAP_DSS_RFBI_CYCLEFORMAT_2_1 = 1,
@@ -89,11 +87,6 @@
OMAP_DSS_RFBI_PARALLELMODE_16 = 3,
};
-enum update_cmd {
- RFBI_CMD_UPDATE = 0,
- RFBI_CMD_SYNC = 1,
-};
-
static int rfbi_convert_timings(struct rfbi_timings *t);
static void rfbi_get_clk_info(u32 *clk_period, u32 *max_clk_div);
@@ -114,20 +107,9 @@
struct omap_dss_device *dssdev[2];
- struct kfifo cmd_fifo;
- spinlock_t cmd_lock;
- struct completion cmd_done;
- atomic_t cmd_fifo_full;
- atomic_t cmd_pending;
+ struct semaphore bus_lock;
} rfbi;
-struct update_region {
- u16 x;
- u16 y;
- u16 w;
- u16 h;
-};
-
static inline void rfbi_write_reg(const struct rfbi_reg idx, u32 val)
{
__raw_writel(val, rfbi.base + idx.idx);
@@ -146,9 +128,20 @@
dss_clk_disable(DSS_CLK_ICK | DSS_CLK_FCK);
}
+void rfbi_bus_lock(void)
+{
+ down(&rfbi.bus_lock);
+}
+EXPORT_SYMBOL(rfbi_bus_lock);
+
+void rfbi_bus_unlock(void)
+{
+ up(&rfbi.bus_lock);
+}
+EXPORT_SYMBOL(rfbi_bus_unlock);
+
void omap_rfbi_write_command(const void *buf, u32 len)
{
- rfbi_enable_clocks(1);
switch (rfbi.parallelmode) {
case OMAP_DSS_RFBI_PARALLELMODE_8:
{
@@ -172,13 +165,11 @@
default:
BUG();
}
- rfbi_enable_clocks(0);
}
EXPORT_SYMBOL(omap_rfbi_write_command);
void omap_rfbi_read_data(void *buf, u32 len)
{
- rfbi_enable_clocks(1);
switch (rfbi.parallelmode) {
case OMAP_DSS_RFBI_PARALLELMODE_8:
{
@@ -206,13 +197,11 @@
default:
BUG();
}
- rfbi_enable_clocks(0);
}
EXPORT_SYMBOL(omap_rfbi_read_data);
void omap_rfbi_write_data(const void *buf, u32 len)
{
- rfbi_enable_clocks(1);
switch (rfbi.parallelmode) {
case OMAP_DSS_RFBI_PARALLELMODE_8:
{
@@ -237,7 +226,6 @@
BUG();
}
- rfbi_enable_clocks(0);
}
EXPORT_SYMBOL(omap_rfbi_write_data);
@@ -249,8 +237,6 @@
int horiz_offset = scr_width - w;
int i;
- rfbi_enable_clocks(1);
-
if (rfbi.datatype == OMAP_DSS_RFBI_DATATYPE_16 &&
rfbi.parallelmode == OMAP_DSS_RFBI_PARALLELMODE_8) {
const u16 __iomem *pd = buf;
@@ -295,12 +281,10 @@
} else {
BUG();
}
-
- rfbi_enable_clocks(0);
}
EXPORT_SYMBOL(omap_rfbi_write_pixels);
-void rfbi_transfer_area(struct omap_dss_device *dssdev, u16 width,
+static void rfbi_transfer_area(struct omap_dss_device *dssdev, u16 width,
u16 height, void (*callback)(void *data), void *data)
{
u32 l;
@@ -317,8 +301,6 @@
rfbi.framedone_callback = callback;
rfbi.framedone_callback_data = data;
- rfbi_enable_clocks(1);
-
rfbi_write_reg(RFBI_PIXEL_CNT, width * height);
l = rfbi_read_reg(RFBI_CONTROL);
@@ -337,15 +319,11 @@
REG_FLD_MOD(RFBI_CONTROL, 0, 0, 0);
- rfbi_enable_clocks(0);
-
callback = rfbi.framedone_callback;
rfbi.framedone_callback = NULL;
if (callback != NULL)
callback(rfbi.framedone_callback_data);
-
- atomic_set(&rfbi.cmd_pending, 0);
}
#if 1 /* VERBOSE */
@@ -435,7 +413,7 @@
}
-void rfbi_set_timings(int rfbi_module, struct rfbi_timings *t)
+static void rfbi_set_timings(int rfbi_module, struct rfbi_timings *t)
{
int r;
@@ -447,7 +425,6 @@
BUG_ON(!t->converted);
- rfbi_enable_clocks(1);
rfbi_write_reg(RFBI_ONOFF_TIME(rfbi_module), t->tim[0]);
rfbi_write_reg(RFBI_CYCLE_TIME(rfbi_module), t->tim[1]);
@@ -456,7 +433,6 @@
(t->tim[2] ? 1 : 0), 4, 4);
rfbi_print_timings();
- rfbi_enable_clocks(0);
}
static int ps_to_rfbi_ticks(int time, int div)
@@ -472,59 +448,6 @@
return ret;
}
-#ifdef OMAP_RFBI_RATE_LIMIT
-unsigned long rfbi_get_max_tx_rate(void)
-{
- unsigned long l4_rate, dss1_rate;
- int min_l4_ticks = 0;
- int i;
-
- /* According to TI this can't be calculated so make the
- * adjustments for a couple of known frequencies and warn for
- * others.
- */
- static const struct {
- unsigned long l4_clk; /* HZ */
- unsigned long dss1_clk; /* HZ */
- unsigned long min_l4_ticks;
- } ftab[] = {
- { 55, 132, 7, }, /* 7.86 MPix/s */
- { 110, 110, 12, }, /* 9.16 MPix/s */
- { 110, 132, 10, }, /* 11 Mpix/s */
- { 120, 120, 10, }, /* 12 Mpix/s */
- { 133, 133, 10, }, /* 13.3 Mpix/s */
- };
-
- l4_rate = rfbi.l4_khz / 1000;
- dss1_rate = dss_clk_get_rate(DSS_CLK_FCK) / 1000000;
-
- for (i = 0; i < ARRAY_SIZE(ftab); i++) {
- /* Use a window instead of an exact match, to account
- * for different DPLL multiplier / divider pairs.
- */
- if (abs(ftab[i].l4_clk - l4_rate) < 3 &&
- abs(ftab[i].dss1_clk - dss1_rate) < 3) {
- min_l4_ticks = ftab[i].min_l4_ticks;
- break;
- }
- }
- if (i == ARRAY_SIZE(ftab)) {
- /* Can't be sure, return anyway the maximum not
- * rate-limited. This might cause a problem only for the
- * tearing synchronisation.
- */
- DSSERR("can't determine maximum RFBI transfer rate\n");
- return rfbi.l4_khz * 1000;
- }
- return rfbi.l4_khz * 1000 / min_l4_ticks;
-}
-#else
-int rfbi_get_max_tx_rate(void)
-{
- return rfbi.l4_khz * 1000;
-}
-#endif
-
static void rfbi_get_clk_info(u32 *clk_period, u32 *max_clk_div)
{
*clk_period = 1000000000 / rfbi.l4_khz;
@@ -644,7 +567,6 @@
DSSDBG("setup_te: mode %d hs %d vs %d hs_inv %d vs_inv %d\n",
mode, hs, vs, hs_pol_inv, vs_pol_inv);
- rfbi_enable_clocks(1);
rfbi_write_reg(RFBI_HSYNC_WIDTH, hs);
rfbi_write_reg(RFBI_VSYNC_WIDTH, vs);
@@ -657,7 +579,6 @@
l &= ~(1 << 20);
else
l |= 1 << 20;
- rfbi_enable_clocks(0);
return 0;
}
@@ -672,7 +593,6 @@
if (line > (1 << 11) - 1)
return -EINVAL;
- rfbi_enable_clocks(1);
l = rfbi_read_reg(RFBI_CONFIG(0));
l &= ~(0x3 << 2);
if (enable) {
@@ -682,50 +602,12 @@
rfbi.te_enabled = 0;
rfbi_write_reg(RFBI_CONFIG(0), l);
rfbi_write_reg(RFBI_LINE_NUMBER, line);
- rfbi_enable_clocks(0);
return 0;
}
EXPORT_SYMBOL(omap_rfbi_enable_te);
-#if 0
-static void rfbi_enable_config(int enable1, int enable2)
-{
- u32 l;
- int cs = 0;
-
- if (enable1)
- cs |= 1<<0;
- if (enable2)
- cs |= 1<<1;
-
- rfbi_enable_clocks(1);
-
- l = rfbi_read_reg(RFBI_CONTROL);
-
- l = FLD_MOD(l, cs, 3, 2);
- l = FLD_MOD(l, 0, 1, 1);
-
- rfbi_write_reg(RFBI_CONTROL, l);
-
-
- l = rfbi_read_reg(RFBI_CONFIG(0));
- l = FLD_MOD(l, 0, 3, 2); /* TRIGGERMODE: ITE */
- /*l |= FLD_VAL(2, 8, 7); */ /* L4FORMAT, 2pix/L4 */
- /*l |= FLD_VAL(0, 8, 7); */ /* L4FORMAT, 1pix/L4 */
-
- l = FLD_MOD(l, 0, 16, 16); /* A0POLARITY */
- l = FLD_MOD(l, 1, 20, 20); /* TE_VSYNC_POLARITY */
- l = FLD_MOD(l, 1, 21, 21); /* HSYNCPOLARITY */
-
- l = FLD_MOD(l, OMAP_DSS_RFBI_PARALLELMODE_8, 1, 0);
- rfbi_write_reg(RFBI_CONFIG(0), l);
-
- rfbi_enable_clocks(0);
-}
-#endif
-
-int rfbi_configure(int rfbi_module, int bpp, int lines)
+static int rfbi_configure(int rfbi_module, int bpp, int lines)
{
u32 l;
int cycle1 = 0, cycle2 = 0, cycle3 = 0;
@@ -821,8 +703,6 @@
break;
}
- rfbi_enable_clocks(1);
-
REG_FLD_MOD(RFBI_CONTROL, 0, 3, 2); /* clear CS */
l = 0;
@@ -856,11 +736,15 @@
DSSDBG("RFBI config: bpp %d, lines %d, cycles: 0x%x 0x%x 0x%x\n",
bpp, lines, cycle1, cycle2, cycle3);
- rfbi_enable_clocks(0);
-
return 0;
}
-EXPORT_SYMBOL(rfbi_configure);
+
+int omap_rfbi_configure(struct omap_dss_device *dssdev, int pixel_size,
+ int data_lines)
+{
+ return rfbi_configure(dssdev->phy.rfbi.channel, pixel_size, data_lines);
+}
+EXPORT_SYMBOL(omap_rfbi_configure);
int omap_rfbi_prepare_update(struct omap_dss_device *dssdev,
u16 *x, u16 *y, u16 *w, u16 *h)
@@ -960,6 +844,8 @@
{
int r;
+ rfbi_enable_clocks(1);
+
r = omap_dss_start_device(dssdev);
if (r) {
DSSERR("failed to start device\n");
@@ -1002,6 +888,8 @@
omap_dispc_unregister_isr(framedone_callback, NULL,
DISPC_IRQ_FRAMEDONE);
omap_dss_stop_device(dssdev);
+
+ rfbi_enable_clocks(0);
}
EXPORT_SYMBOL(omapdss_rfbi_display_disable);
@@ -1021,11 +909,7 @@
rfbi.pdev = pdev;
- spin_lock_init(&rfbi.cmd_lock);
-
- init_completion(&rfbi.cmd_done);
- atomic_set(&rfbi.cmd_fifo_full, 0);
- atomic_set(&rfbi.cmd_pending, 0);
+ sema_init(&rfbi.bus_lock, 1);
rfbi_mem = platform_get_resource(rfbi.pdev, IORESOURCE_MEM, 0);
if (!rfbi_mem) {
diff --git a/drivers/video/omap2/dss/sdi.c b/drivers/video/omap2/dss/sdi.c
index 54a53e6..0bd4b03 100644
--- a/drivers/video/omap2/dss/sdi.c
+++ b/drivers/video/omap2/dss/sdi.c
@@ -25,7 +25,7 @@
#include <linux/err.h>
#include <linux/regulator/consumer.h>
-#include <plat/display.h>
+#include <video/omapdss.h>
#include <plat/cpu.h>
#include "dss.h"
diff --git a/drivers/video/omap2/dss/venc.c b/drivers/video/omap2/dss/venc.c
index 8e35a5b..980f919 100644
--- a/drivers/video/omap2/dss/venc.c
+++ b/drivers/video/omap2/dss/venc.c
@@ -34,7 +34,7 @@
#include <linux/platform_device.h>
#include <linux/regulator/consumer.h>
-#include <plat/display.h>
+#include <video/omapdss.h>
#include <plat/cpu.h>
#include "dss.h"
@@ -373,8 +373,11 @@
}
}
+#ifdef CONFIG_OMAP2_DSS_SLEEP_AFTER_VENC_RESET
/* the magical sleep that makes things work */
+ /* XXX more info? What bug this circumvents? */
msleep(20);
+#endif
}
static void venc_enable_clocks(int enable)
@@ -473,6 +476,12 @@
mutex_lock(&venc.venc_lock);
+ r = omap_dss_start_device(dssdev);
+ if (r) {
+ DSSERR("failed to start device\n");
+ goto err0;
+ }
+
if (dssdev->state != OMAP_DSS_DISPLAY_DISABLED) {
r = -EINVAL;
goto err1;
@@ -484,10 +493,11 @@
dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
- /* wait couple of vsyncs until enabling the LCD */
- msleep(50);
-
+ mutex_unlock(&venc.venc_lock);
+ return 0;
err1:
+ omap_dss_stop_device(dssdev);
+err0:
mutex_unlock(&venc.venc_lock);
return r;
@@ -510,10 +520,9 @@
venc_power_off(dssdev);
- /* wait at least 5 vsyncs after disabling the LCD */
- msleep(100);
-
dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
+
+ omap_dss_stop_device(dssdev);
end:
mutex_unlock(&venc.venc_lock);
}
diff --git a/drivers/video/omap2/omapfb/omapfb-ioctl.c b/drivers/video/omap2/omapfb/omapfb-ioctl.c
index 6f43545..cff4503 100644
--- a/drivers/video/omap2/omapfb/omapfb-ioctl.c
+++ b/drivers/video/omap2/omapfb/omapfb-ioctl.c
@@ -28,7 +28,7 @@
#include <linux/omapfb.h>
#include <linux/vmalloc.h>
-#include <plat/display.h>
+#include <video/omapdss.h>
#include <plat/vrfb.h>
#include <plat/vram.h>
@@ -895,8 +895,16 @@
p.display_info.xres = xres;
p.display_info.yres = yres;
- p.display_info.width = 0;
- p.display_info.height = 0;
+
+ if (display->driver->get_dimensions) {
+ u32 w, h;
+ display->driver->get_dimensions(display, &w, &h);
+ p.display_info.width = w;
+ p.display_info.height = h;
+ } else {
+ p.display_info.width = 0;
+ p.display_info.height = 0;
+ }
if (copy_to_user((void __user *)arg, &p.display_info,
sizeof(p.display_info)))
diff --git a/drivers/video/omap2/omapfb/omapfb-main.c b/drivers/video/omap2/omapfb/omapfb-main.c
index 505ec667..505bc12 100644
--- a/drivers/video/omap2/omapfb/omapfb-main.c
+++ b/drivers/video/omap2/omapfb/omapfb-main.c
@@ -30,7 +30,7 @@
#include <linux/platform_device.h>
#include <linux/omapfb.h>
-#include <plat/display.h>
+#include <video/omapdss.h>
#include <plat/vram.h>
#include <plat/vrfb.h>
@@ -702,8 +702,16 @@
var->xres, var->yres,
var->xres_virtual, var->yres_virtual);
- var->height = -1;
- var->width = -1;
+ if (display && display->driver->get_dimensions) {
+ u32 w, h;
+ display->driver->get_dimensions(display, &w, &h);
+ var->width = DIV_ROUND_CLOSEST(w, 1000);
+ var->height = DIV_ROUND_CLOSEST(h, 1000);
+ } else {
+ var->height = -1;
+ var->width = -1;
+ }
+
var->grayscale = 0;
if (display && display->driver->get_timings) {
@@ -749,35 +757,6 @@
static int omapfb_release(struct fb_info *fbi, int user)
{
-#if 0
- struct omapfb_info *ofbi = FB2OFB(fbi);
- struct omapfb2_device *fbdev = ofbi->fbdev;
- struct omap_dss_device *display = fb2display(fbi);
-
- DBG("Closing fb with plane index %d\n", ofbi->id);
-
- omapfb_lock(fbdev);
-
- if (display && display->get_update_mode && display->update) {
- /* XXX this update should be removed, I think. But it's
- * good for debugging */
- if (display->get_update_mode(display) ==
- OMAP_DSS_UPDATE_MANUAL) {
- u16 w, h;
-
- if (display->sync)
- display->sync(display);
-
- display->get_resolution(display, &w, &h);
- display->update(display, 0, 0, w, h);
- }
- }
-
- if (display && display->sync)
- display->sync(display);
-
- omapfb_unlock(fbdev);
-#endif
return 0;
}
@@ -1263,7 +1242,6 @@
struct omapfb_info *ofbi = FB2OFB(fbi);
struct omapfb2_device *fbdev = ofbi->fbdev;
struct omap_dss_device *display = fb2display(fbi);
- int do_update = 0;
int r = 0;
if (!display)
@@ -1279,11 +1257,6 @@
if (display->driver->resume)
r = display->driver->resume(display);
- if (r == 0 && display->driver->get_update_mode &&
- display->driver->get_update_mode(display) ==
- OMAP_DSS_UPDATE_MANUAL)
- do_update = 1;
-
break;
case FB_BLANK_NORMAL:
@@ -1307,13 +1280,6 @@
exit:
omapfb_unlock(fbdev);
- if (r == 0 && do_update && display->driver->update) {
- u16 w, h;
- display->driver->get_resolution(display, &w, &h);
-
- r = display->driver->update(display, 0, 0, w, h);
- }
-
return r;
}
@@ -2030,9 +1996,9 @@
static int omapfb_mode_to_timings(const char *mode_str,
struct omap_video_timings *timings, u8 *bpp)
{
- struct fb_info fbi;
- struct fb_var_screeninfo var;
- struct fb_ops fbops;
+ struct fb_info *fbi;
+ struct fb_var_screeninfo *var;
+ struct fb_ops *fbops;
int r;
#ifdef CONFIG_OMAP2_DSS_VENC
@@ -2050,39 +2016,66 @@
/* this is quite a hack, but I wanted to use the modedb and for
* that we need fb_info and var, so we create dummy ones */
- memset(&fbi, 0, sizeof(fbi));
- memset(&var, 0, sizeof(var));
- memset(&fbops, 0, sizeof(fbops));
- fbi.fbops = &fbops;
+ *bpp = 0;
+ fbi = NULL;
+ var = NULL;
+ fbops = NULL;
- r = fb_find_mode(&var, &fbi, mode_str, NULL, 0, NULL, 24);
-
- if (r != 0) {
- timings->pixel_clock = PICOS2KHZ(var.pixclock);
- timings->hbp = var.left_margin;
- timings->hfp = var.right_margin;
- timings->vbp = var.upper_margin;
- timings->vfp = var.lower_margin;
- timings->hsw = var.hsync_len;
- timings->vsw = var.vsync_len;
- timings->x_res = var.xres;
- timings->y_res = var.yres;
-
- switch (var.bits_per_pixel) {
- case 16:
- *bpp = 16;
- break;
- case 24:
- case 32:
- default:
- *bpp = 24;
- break;
- }
-
- return 0;
- } else {
- return -EINVAL;
+ fbi = kzalloc(sizeof(*fbi), GFP_KERNEL);
+ if (fbi == NULL) {
+ r = -ENOMEM;
+ goto err;
}
+
+ var = kzalloc(sizeof(*var), GFP_KERNEL);
+ if (var == NULL) {
+ r = -ENOMEM;
+ goto err;
+ }
+
+ fbops = kzalloc(sizeof(*fbops), GFP_KERNEL);
+ if (fbops == NULL) {
+ r = -ENOMEM;
+ goto err;
+ }
+
+ fbi->fbops = fbops;
+
+ r = fb_find_mode(var, fbi, mode_str, NULL, 0, NULL, 24);
+ if (r == 0) {
+ r = -EINVAL;
+ goto err;
+ }
+
+ timings->pixel_clock = PICOS2KHZ(var->pixclock);
+ timings->hbp = var->left_margin;
+ timings->hfp = var->right_margin;
+ timings->vbp = var->upper_margin;
+ timings->vfp = var->lower_margin;
+ timings->hsw = var->hsync_len;
+ timings->vsw = var->vsync_len;
+ timings->x_res = var->xres;
+ timings->y_res = var->yres;
+
+ switch (var->bits_per_pixel) {
+ case 16:
+ *bpp = 16;
+ break;
+ case 24:
+ case 32:
+ default:
+ *bpp = 24;
+ break;
+ }
+
+ r = 0;
+
+err:
+ kfree(fbi);
+ kfree(var);
+ kfree(fbops);
+
+ return r;
}
static int omapfb_set_def_mode(struct omapfb2_device *fbdev,
@@ -2185,6 +2178,61 @@
return r;
}
+static int omapfb_init_display(struct omapfb2_device *fbdev,
+ struct omap_dss_device *dssdev)
+{
+ struct omap_dss_driver *dssdrv = dssdev->driver;
+ int r;
+
+ r = dssdrv->enable(dssdev);
+ if (r) {
+ dev_warn(fbdev->dev, "Failed to enable display '%s'\n",
+ dssdev->name);
+ return r;
+ }
+
+ if (dssdev->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE) {
+ u16 w, h;
+ if (dssdrv->enable_te) {
+ r = dssdrv->enable_te(dssdev, 1);
+ if (r) {
+ dev_err(fbdev->dev, "Failed to set TE\n");
+ return r;
+ }
+ }
+
+ if (dssdrv->set_update_mode) {
+ r = dssdrv->set_update_mode(dssdev,
+ OMAP_DSS_UPDATE_MANUAL);
+ if (r) {
+ dev_err(fbdev->dev,
+ "Failed to set update mode\n");
+ return r;
+ }
+ }
+
+ dssdrv->get_resolution(dssdev, &w, &h);
+ r = dssdrv->update(dssdev, 0, 0, w, h);
+ if (r) {
+ dev_err(fbdev->dev,
+ "Failed to update display\n");
+ return r;
+ }
+ } else {
+ if (dssdrv->set_update_mode) {
+ r = dssdrv->set_update_mode(dssdev,
+ OMAP_DSS_UPDATE_AUTO);
+ if (r) {
+ dev_err(fbdev->dev,
+ "Failed to set update mode\n");
+ return r;
+ }
+ }
+ }
+
+ return 0;
+}
+
static int omapfb_probe(struct platform_device *pdev)
{
struct omapfb2_device *fbdev = NULL;
@@ -2284,30 +2332,13 @@
}
if (def_display) {
- struct omap_dss_driver *dssdrv = def_display->driver;
-
- r = def_display->driver->enable(def_display);
+ r = omapfb_init_display(fbdev, def_display);
if (r) {
- dev_warn(fbdev->dev, "Failed to enable display '%s'\n",
- def_display->name);
+ dev_err(fbdev->dev,
+ "failed to initialize default "
+ "display\n");
goto cleanup;
}
-
- if (def_display->caps & OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE) {
- u16 w, h;
- if (dssdrv->enable_te)
- dssdrv->enable_te(def_display, 1);
- if (dssdrv->set_update_mode)
- dssdrv->set_update_mode(def_display,
- OMAP_DSS_UPDATE_MANUAL);
-
- dssdrv->get_resolution(def_display, &w, &h);
- def_display->driver->update(def_display, 0, 0, w, h);
- } else {
- if (dssdrv->set_update_mode)
- dssdrv->set_update_mode(def_display,
- OMAP_DSS_UPDATE_AUTO);
- }
}
DBG("create sysfs for fbs\n");
diff --git a/drivers/video/omap2/omapfb/omapfb-sysfs.c b/drivers/video/omap2/omapfb/omapfb-sysfs.c
index 6f9c72c..2f5e817 100644
--- a/drivers/video/omap2/omapfb/omapfb-sysfs.c
+++ b/drivers/video/omap2/omapfb/omapfb-sysfs.c
@@ -29,7 +29,7 @@
#include <linux/mm.h>
#include <linux/omapfb.h>
-#include <plat/display.h>
+#include <video/omapdss.h>
#include <plat/vrfb.h>
#include "omapfb.h"
@@ -50,10 +50,12 @@
struct fb_info *fbi = dev_get_drvdata(dev);
struct omapfb_info *ofbi = FB2OFB(fbi);
struct omapfb2_mem_region *rg;
- enum omap_dss_rotation_type rot_type;
+ int rot_type;
int r;
- rot_type = simple_strtoul(buf, NULL, 0);
+ r = kstrtoint(buf, 0, &rot_type);
+ if (r)
+ return r;
if (rot_type != OMAP_DSS_ROT_DMA && rot_type != OMAP_DSS_ROT_VRFB)
return -EINVAL;
@@ -102,14 +104,15 @@
{
struct fb_info *fbi = dev_get_drvdata(dev);
struct omapfb_info *ofbi = FB2OFB(fbi);
- unsigned long mirror;
+ int mirror;
int r;
struct fb_var_screeninfo new_var;
- mirror = simple_strtoul(buf, NULL, 0);
+ r = kstrtoint(buf, 0, &mirror);
+ if (r)
+ return r;
- if (mirror != 0 && mirror != 1)
- return -EINVAL;
+ mirror = !!mirror;
if (!lock_fb_info(fbi))
return -ENODEV;
@@ -445,7 +448,11 @@
int r;
int i;
- size = PAGE_ALIGN(simple_strtoul(buf, NULL, 0));
+ r = kstrtoul(buf, 0, &size);
+ if (r)
+ return r;
+
+ size = PAGE_ALIGN(size);
if (!lock_fb_info(fbi))
return -ENODEV;
diff --git a/drivers/video/omap2/omapfb/omapfb.h b/drivers/video/omap2/omapfb/omapfb.h
index 1305fc9..aa1b1d9 100644
--- a/drivers/video/omap2/omapfb/omapfb.h
+++ b/drivers/video/omap2/omapfb/omapfb.h
@@ -29,13 +29,15 @@
#include <linux/rwsem.h>
-#include <plat/display.h>
+#include <video/omapdss.h>
#ifdef DEBUG
extern unsigned int omapfb_debug;
#define DBG(format, ...) \
- if (omapfb_debug) \
- printk(KERN_DEBUG "OMAPFB: " format, ## __VA_ARGS__)
+ do { \
+ if (omapfb_debug) \
+ printk(KERN_DEBUG "OMAPFB: " format, ## __VA_ARGS__); \
+ } while (0)
#else
#define DBG(format, ...)
#endif
diff --git a/drivers/video/s3c-fb.c b/drivers/video/s3c-fb.c
index 3b6cdca..0352afa 100644
--- a/drivers/video/s3c-fb.c
+++ b/drivers/video/s3c-fb.c
@@ -182,6 +182,7 @@
/**
* struct s3c_fb - overall hardware state of the hardware
+ * @slock: The spinlock protection for this data sturcture.
* @dev: The device that we bound to, for printing, etc.
* @regs_res: The resource we claimed for the IO registers.
* @bus_clk: The clk (hclk) feeding our interface and possibly pixclk.
@@ -195,6 +196,7 @@
* @vsync_info: VSYNC-related information (count, queues...)
*/
struct s3c_fb {
+ spinlock_t slock;
struct device *dev;
struct resource *regs_res;
struct clk *bus_clk;
@@ -300,6 +302,7 @@
var->blue.length = 5;
break;
+ case 32:
case 28:
case 25:
var->transp.length = var->bits_per_pixel - 24;
@@ -308,7 +311,6 @@
case 24:
/* our 24bpp is unpacked, so 32bpp */
var->bits_per_pixel = 32;
- case 32:
var->red.offset = 16;
var->red.length = 8;
var->green.offset = 8;
@@ -947,6 +949,8 @@
void __iomem *regs = sfb->regs;
u32 irq_sts_reg;
+ spin_lock(&sfb->slock);
+
irq_sts_reg = readl(regs + VIDINTCON1);
if (irq_sts_reg & VIDINTCON1_INT_FRAME) {
@@ -963,6 +967,7 @@
*/
s3c_fb_disable_irq(sfb);
+ spin_unlock(&sfb->slock);
return IRQ_HANDLED;
}
@@ -1339,6 +1344,8 @@
sfb->pdata = pd;
sfb->variant = fbdrv->variant;
+ spin_lock_init(&sfb->slock);
+
sfb->bus_clk = clk_get(dev, "lcd");
if (IS_ERR(sfb->bus_clk)) {
dev_err(dev, "failed to get bus clock\n");
@@ -1442,8 +1449,7 @@
iounmap(sfb->regs);
err_req_region:
- release_resource(sfb->regs_res);
- kfree(sfb->regs_res);
+ release_mem_region(sfb->regs_res->start, resource_size(sfb->regs_res));
err_clk:
clk_disable(sfb->bus_clk);
@@ -1479,8 +1485,7 @@
clk_disable(sfb->bus_clk);
clk_put(sfb->bus_clk);
- release_resource(sfb->regs_res);
- kfree(sfb->regs_res);
+ release_mem_region(sfb->regs_res->start, resource_size(sfb->regs_res));
kfree(sfb);
@@ -1521,7 +1526,8 @@
clk_enable(sfb->bus_clk);
- /* setup registers */
+ /* setup gpio and output polarity controls */
+ pd->setup_gpio();
writel(pd->vidcon1, sfb->regs + VIDCON1);
/* zero all windows before we do anything */
@@ -1549,7 +1555,7 @@
return 0;
}
-int s3c_fb_runtime_suspend(struct device *dev)
+static int s3c_fb_runtime_suspend(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct s3c_fb *sfb = platform_get_drvdata(pdev);
@@ -1569,7 +1575,7 @@
return 0;
}
-int s3c_fb_runtime_resume(struct device *dev)
+static int s3c_fb_runtime_resume(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct s3c_fb *sfb = platform_get_drvdata(pdev);
@@ -1579,7 +1585,8 @@
clk_enable(sfb->bus_clk);
- /* setup registers */
+ /* setup gpio and output polarity controls */
+ pd->setup_gpio();
writel(pd->vidcon1, sfb->regs + VIDCON1);
/* zero all windows before we do anything */
@@ -1623,28 +1630,31 @@
.has_osd_c = 1,
.osd_size_off = 0x8,
.palette_sz = 256,
- .valid_bpp = VALID_BPP1248 | VALID_BPP(16) | VALID_BPP(24),
+ .valid_bpp = (VALID_BPP1248 | VALID_BPP(16) |
+ VALID_BPP(18) | VALID_BPP(24)),
},
[1] = {
.has_osd_c = 1,
.has_osd_d = 1,
- .osd_size_off = 0x12,
+ .osd_size_off = 0xc,
.has_osd_alpha = 1,
.palette_sz = 256,
.valid_bpp = (VALID_BPP1248 | VALID_BPP(16) |
VALID_BPP(18) | VALID_BPP(19) |
- VALID_BPP(24) | VALID_BPP(25)),
+ VALID_BPP(24) | VALID_BPP(25) |
+ VALID_BPP(28)),
},
[2] = {
.has_osd_c = 1,
.has_osd_d = 1,
- .osd_size_off = 0x12,
+ .osd_size_off = 0xc,
.has_osd_alpha = 1,
.palette_sz = 16,
.palette_16bpp = 1,
.valid_bpp = (VALID_BPP1248 | VALID_BPP(16) |
VALID_BPP(18) | VALID_BPP(19) |
- VALID_BPP(24) | VALID_BPP(25)),
+ VALID_BPP(24) | VALID_BPP(25) |
+ VALID_BPP(28)),
},
[3] = {
.has_osd_c = 1,
@@ -1653,7 +1663,8 @@
.palette_16bpp = 1,
.valid_bpp = (VALID_BPP124 | VALID_BPP(16) |
VALID_BPP(18) | VALID_BPP(19) |
- VALID_BPP(24) | VALID_BPP(25)),
+ VALID_BPP(24) | VALID_BPP(25) |
+ VALID_BPP(28)),
},
[4] = {
.has_osd_c = 1,
@@ -1662,7 +1673,65 @@
.palette_16bpp = 1,
.valid_bpp = (VALID_BPP(1) | VALID_BPP(2) |
VALID_BPP(16) | VALID_BPP(18) |
- VALID_BPP(24) | VALID_BPP(25)),
+ VALID_BPP(19) | VALID_BPP(24) |
+ VALID_BPP(25) | VALID_BPP(28)),
+ },
+};
+
+static struct s3c_fb_win_variant s3c_fb_data_s5p_wins[] = {
+ [0] = {
+ .has_osd_c = 1,
+ .osd_size_off = 0x8,
+ .palette_sz = 256,
+ .valid_bpp = (VALID_BPP1248 | VALID_BPP(13) |
+ VALID_BPP(15) | VALID_BPP(16) |
+ VALID_BPP(18) | VALID_BPP(19) |
+ VALID_BPP(24) | VALID_BPP(25) |
+ VALID_BPP(32)),
+ },
+ [1] = {
+ .has_osd_c = 1,
+ .has_osd_d = 1,
+ .osd_size_off = 0xc,
+ .has_osd_alpha = 1,
+ .palette_sz = 256,
+ .valid_bpp = (VALID_BPP1248 | VALID_BPP(13) |
+ VALID_BPP(15) | VALID_BPP(16) |
+ VALID_BPP(18) | VALID_BPP(19) |
+ VALID_BPP(24) | VALID_BPP(25) |
+ VALID_BPP(32)),
+ },
+ [2] = {
+ .has_osd_c = 1,
+ .has_osd_d = 1,
+ .osd_size_off = 0xc,
+ .has_osd_alpha = 1,
+ .palette_sz = 256,
+ .valid_bpp = (VALID_BPP1248 | VALID_BPP(13) |
+ VALID_BPP(15) | VALID_BPP(16) |
+ VALID_BPP(18) | VALID_BPP(19) |
+ VALID_BPP(24) | VALID_BPP(25) |
+ VALID_BPP(32)),
+ },
+ [3] = {
+ .has_osd_c = 1,
+ .has_osd_alpha = 1,
+ .palette_sz = 256,
+ .valid_bpp = (VALID_BPP1248 | VALID_BPP(13) |
+ VALID_BPP(15) | VALID_BPP(16) |
+ VALID_BPP(18) | VALID_BPP(19) |
+ VALID_BPP(24) | VALID_BPP(25) |
+ VALID_BPP(32)),
+ },
+ [4] = {
+ .has_osd_c = 1,
+ .has_osd_alpha = 1,
+ .palette_sz = 256,
+ .valid_bpp = (VALID_BPP1248 | VALID_BPP(13) |
+ VALID_BPP(15) | VALID_BPP(16) |
+ VALID_BPP(18) | VALID_BPP(19) |
+ VALID_BPP(24) | VALID_BPP(25) |
+ VALID_BPP(32)),
},
};
@@ -1719,11 +1788,11 @@
.has_prtcon = 1,
},
- .win[0] = &s3c_fb_data_64xx_wins[0],
- .win[1] = &s3c_fb_data_64xx_wins[1],
- .win[2] = &s3c_fb_data_64xx_wins[2],
- .win[3] = &s3c_fb_data_64xx_wins[3],
- .win[4] = &s3c_fb_data_64xx_wins[4],
+ .win[0] = &s3c_fb_data_s5p_wins[0],
+ .win[1] = &s3c_fb_data_s5p_wins[1],
+ .win[2] = &s3c_fb_data_s5p_wins[2],
+ .win[3] = &s3c_fb_data_s5p_wins[3],
+ .win[4] = &s3c_fb_data_s5p_wins[4],
};
static struct s3c_fb_driverdata s3c_fb_data_s5pv210 = {
@@ -1749,11 +1818,11 @@
.has_shadowcon = 1,
},
- .win[0] = &s3c_fb_data_64xx_wins[0],
- .win[1] = &s3c_fb_data_64xx_wins[1],
- .win[2] = &s3c_fb_data_64xx_wins[2],
- .win[3] = &s3c_fb_data_64xx_wins[3],
- .win[4] = &s3c_fb_data_64xx_wins[4],
+ .win[0] = &s3c_fb_data_s5p_wins[0],
+ .win[1] = &s3c_fb_data_s5p_wins[1],
+ .win[2] = &s3c_fb_data_s5p_wins[2],
+ .win[3] = &s3c_fb_data_s5p_wins[3],
+ .win[4] = &s3c_fb_data_s5p_wins[4],
};
/* S3C2443/S3C2416 style hardware */
diff --git a/drivers/video/s3c2410fb.c b/drivers/video/s3c2410fb.c
index 61c819e3..0aa1376 100644
--- a/drivers/video/s3c2410fb.c
+++ b/drivers/video/s3c2410fb.c
@@ -867,7 +867,7 @@
goto dealloc_fb;
}
- size = (res->end - res->start) + 1;
+ size = resource_size(res);
info->mem = request_mem_region(res->start, size, pdev->name);
if (info->mem == NULL) {
dev_err(&pdev->dev, "failed to get memory region\n");
@@ -997,8 +997,7 @@
release_regs:
iounmap(info->io);
release_mem:
- release_resource(info->mem);
- kfree(info->mem);
+ release_mem_region(res->start, size);
dealloc_fb:
platform_set_drvdata(pdev, NULL);
framebuffer_release(fbinfo);
@@ -1044,8 +1043,7 @@
iounmap(info->io);
- release_resource(info->mem);
- kfree(info->mem);
+ release_mem_region(info->mem->start, resource_size(info->mem));
platform_set_drvdata(pdev, NULL);
framebuffer_release(fbinfo);
diff --git a/drivers/video/s3fb.c b/drivers/video/s3fb.c
index c4482f2..4ca5d0c 100644
--- a/drivers/video/s3fb.c
+++ b/drivers/video/s3fb.c
@@ -25,6 +25,9 @@
#include <linux/console.h> /* Why should fb driver call console functions? because console_lock() */
#include <video/vga.h>
+#include <linux/i2c.h>
+#include <linux/i2c-algo-bit.h>
+
#ifdef CONFIG_MTRR
#include <asm/mtrr.h>
#endif
@@ -36,6 +39,12 @@
struct mutex open_lock;
unsigned int ref_count;
u32 pseudo_palette[16];
+#ifdef CONFIG_FB_S3_DDC
+ u8 __iomem *mmio;
+ bool ddc_registered;
+ struct i2c_adapter ddc_adapter;
+ struct i2c_algo_bit_data ddc_algo;
+#endif
};
@@ -105,6 +114,9 @@
#define CHIP_UNDECIDED_FLAG 0x80
#define CHIP_MASK 0xFF
+#define MMIO_OFFSET 0x1000000
+#define MMIO_SIZE 0x10000
+
/* CRT timing register sets */
static const struct vga_regset s3_h_total_regs[] = {{0x00, 0, 7}, {0x5D, 0, 0}, VGA_REGSET_END};
@@ -140,7 +152,7 @@
/* Module parameters */
-static char *mode_option __devinitdata = "640x480-8@60";
+static char *mode_option __devinitdata;
#ifdef CONFIG_MTRR
static int mtrr __devinitdata = 1;
@@ -169,6 +181,119 @@
/* ------------------------------------------------------------------------- */
+#ifdef CONFIG_FB_S3_DDC
+
+#define DDC_REG 0xaa /* Trio 3D/1X/2X */
+#define DDC_MMIO_REG 0xff20 /* all other chips */
+#define DDC_SCL_OUT (1 << 0)
+#define DDC_SDA_OUT (1 << 1)
+#define DDC_SCL_IN (1 << 2)
+#define DDC_SDA_IN (1 << 3)
+#define DDC_DRIVE_EN (1 << 4)
+
+static bool s3fb_ddc_needs_mmio(int chip)
+{
+ return !(chip == CHIP_360_TRIO3D_1X ||
+ chip == CHIP_362_TRIO3D_2X ||
+ chip == CHIP_368_TRIO3D_2X);
+}
+
+static u8 s3fb_ddc_read(struct s3fb_info *par)
+{
+ if (s3fb_ddc_needs_mmio(par->chip))
+ return readb(par->mmio + DDC_MMIO_REG);
+ else
+ return vga_rcrt(par->state.vgabase, DDC_REG);
+}
+
+static void s3fb_ddc_write(struct s3fb_info *par, u8 val)
+{
+ if (s3fb_ddc_needs_mmio(par->chip))
+ writeb(val, par->mmio + DDC_MMIO_REG);
+ else
+ vga_wcrt(par->state.vgabase, DDC_REG, val);
+}
+
+static void s3fb_ddc_setscl(void *data, int val)
+{
+ struct s3fb_info *par = data;
+ unsigned char reg;
+
+ reg = s3fb_ddc_read(par) | DDC_DRIVE_EN;
+ if (val)
+ reg |= DDC_SCL_OUT;
+ else
+ reg &= ~DDC_SCL_OUT;
+ s3fb_ddc_write(par, reg);
+}
+
+static void s3fb_ddc_setsda(void *data, int val)
+{
+ struct s3fb_info *par = data;
+ unsigned char reg;
+
+ reg = s3fb_ddc_read(par) | DDC_DRIVE_EN;
+ if (val)
+ reg |= DDC_SDA_OUT;
+ else
+ reg &= ~DDC_SDA_OUT;
+ s3fb_ddc_write(par, reg);
+}
+
+static int s3fb_ddc_getscl(void *data)
+{
+ struct s3fb_info *par = data;
+
+ return !!(s3fb_ddc_read(par) & DDC_SCL_IN);
+}
+
+static int s3fb_ddc_getsda(void *data)
+{
+ struct s3fb_info *par = data;
+
+ return !!(s3fb_ddc_read(par) & DDC_SDA_IN);
+}
+
+static int __devinit s3fb_setup_ddc_bus(struct fb_info *info)
+{
+ struct s3fb_info *par = info->par;
+
+ strlcpy(par->ddc_adapter.name, info->fix.id,
+ sizeof(par->ddc_adapter.name));
+ par->ddc_adapter.owner = THIS_MODULE;
+ par->ddc_adapter.class = I2C_CLASS_DDC;
+ par->ddc_adapter.algo_data = &par->ddc_algo;
+ par->ddc_adapter.dev.parent = info->device;
+ par->ddc_algo.setsda = s3fb_ddc_setsda;
+ par->ddc_algo.setscl = s3fb_ddc_setscl;
+ par->ddc_algo.getsda = s3fb_ddc_getsda;
+ par->ddc_algo.getscl = s3fb_ddc_getscl;
+ par->ddc_algo.udelay = 10;
+ par->ddc_algo.timeout = 20;
+ par->ddc_algo.data = par;
+
+ i2c_set_adapdata(&par->ddc_adapter, par);
+
+ /*
+ * some Virge cards have external MUX to switch chip I2C bus between
+ * DDC and extension pins - switch it do DDC
+ */
+/* vga_wseq(par->state.vgabase, 0x08, 0x06); - not needed, already unlocked */
+ if (par->chip == CHIP_357_VIRGE_GX2 ||
+ par->chip == CHIP_359_VIRGE_GX2P)
+ svga_wseq_mask(par->state.vgabase, 0x0d, 0x01, 0x03);
+ else
+ svga_wseq_mask(par->state.vgabase, 0x0d, 0x00, 0x03);
+ /* some Virge need this or the DDC is ignored */
+ svga_wcrt_mask(par->state.vgabase, 0x5c, 0x03, 0x03);
+
+ return i2c_bit_add_bus(&par->ddc_adapter);
+}
+#endif /* CONFIG_FB_S3_DDC */
+
+
+/* ------------------------------------------------------------------------- */
+
/* Set font in S3 fast text mode */
static void s3fb_settile_fast(struct fb_info *info, struct fb_tilemap *map)
@@ -994,6 +1119,7 @@
struct s3fb_info *par;
int rc;
u8 regval, cr38, cr39;
+ bool found = false;
/* Ignore secondary VGA device because there is no VGA arbitration */
if (! svga_primary_device(dev)) {
@@ -1110,12 +1236,69 @@
info->fix.ypanstep = 0;
info->fix.accel = FB_ACCEL_NONE;
info->pseudo_palette = (void*) (par->pseudo_palette);
+ info->var.bits_per_pixel = 8;
+
+#ifdef CONFIG_FB_S3_DDC
+ /* Enable MMIO if needed */
+ if (s3fb_ddc_needs_mmio(par->chip)) {
+ par->mmio = ioremap(info->fix.smem_start + MMIO_OFFSET, MMIO_SIZE);
+ if (par->mmio)
+ svga_wcrt_mask(par->state.vgabase, 0x53, 0x08, 0x08); /* enable MMIO */
+ else
+ dev_err(info->device, "unable to map MMIO at 0x%lx, disabling DDC",
+ info->fix.smem_start + MMIO_OFFSET);
+ }
+ if (!s3fb_ddc_needs_mmio(par->chip) || par->mmio)
+ if (s3fb_setup_ddc_bus(info) == 0) {
+ u8 *edid = fb_ddc_read(&par->ddc_adapter);
+ par->ddc_registered = true;
+ if (edid) {
+ fb_edid_to_monspecs(edid, &info->monspecs);
+ kfree(edid);
+ if (!info->monspecs.modedb)
+ dev_err(info->device, "error getting mode database\n");
+ else {
+ const struct fb_videomode *m;
+
+ fb_videomode_to_modelist(info->monspecs.modedb,
+ info->monspecs.modedb_len,
+ &info->modelist);
+ m = fb_find_best_display(&info->monspecs, &info->modelist);
+ if (m) {
+ fb_videomode_to_var(&info->var, m);
+ /* fill all other info->var's fields */
+ if (s3fb_check_var(&info->var, info) == 0)
+ found = true;
+ }
+ }
+ }
+ }
+#endif
+ if (!mode_option && !found)
+ mode_option = "640x480-8@60";
/* Prepare startup mode */
- rc = fb_find_mode(&(info->var), info, mode_option, NULL, 0, NULL, 8);
- if (! ((rc == 1) || (rc == 2))) {
- rc = -EINVAL;
- dev_err(info->device, "mode %s not found\n", mode_option);
+ if (mode_option) {
+ rc = fb_find_mode(&info->var, info, mode_option,
+ info->monspecs.modedb, info->monspecs.modedb_len,
+ NULL, info->var.bits_per_pixel);
+ if (!rc || rc == 4) {
+ rc = -EINVAL;
+ dev_err(info->device, "mode %s not found\n", mode_option);
+ fb_destroy_modedb(info->monspecs.modedb);
+ info->monspecs.modedb = NULL;
+ goto err_find_mode;
+ }
+ }
+
+ fb_destroy_modedb(info->monspecs.modedb);
+ info->monspecs.modedb = NULL;
+
+ /* maximize virtual vertical size for fast scrolling */
+ info->var.yres_virtual = info->fix.smem_len * 8 /
+ (info->var.bits_per_pixel * info->var.xres_virtual);
+ if (info->var.yres_virtual < info->var.yres) {
+ dev_err(info->device, "virtual vertical size smaller than real\n");
goto err_find_mode;
}
@@ -1164,6 +1347,12 @@
fb_dealloc_cmap(&info->cmap);
err_alloc_cmap:
err_find_mode:
+#ifdef CONFIG_FB_S3_DDC
+ if (par->ddc_registered)
+ i2c_del_adapter(&par->ddc_adapter);
+ if (par->mmio)
+ iounmap(par->mmio);
+#endif
pci_iounmap(dev, info->screen_base);
err_iomap:
pci_release_regions(dev);
@@ -1180,12 +1369,11 @@
static void __devexit s3_pci_remove(struct pci_dev *dev)
{
struct fb_info *info = pci_get_drvdata(dev);
+ struct s3fb_info __maybe_unused *par = info->par;
if (info) {
#ifdef CONFIG_MTRR
- struct s3fb_info *par = info->par;
-
if (par->mtrr_reg >= 0) {
mtrr_del(par->mtrr_reg, 0, 0);
par->mtrr_reg = -1;
@@ -1195,6 +1383,13 @@
unregister_framebuffer(info);
fb_dealloc_cmap(&info->cmap);
+#ifdef CONFIG_FB_S3_DDC
+ if (par->ddc_registered)
+ i2c_del_adapter(&par->ddc_adapter);
+ if (par->mmio)
+ iounmap(par->mmio);
+#endif
+
pci_iounmap(dev, info->screen_base);
pci_release_regions(dev);
/* pci_disable_device(dev); */
diff --git a/drivers/video/savage/savagefb-i2c.c b/drivers/video/savage/savagefb-i2c.c
index bb71fea..80fa87e 100644
--- a/drivers/video/savage/savagefb-i2c.c
+++ b/drivers/video/savage/savagefb-i2c.c
@@ -171,6 +171,8 @@
switch (par->chip) {
case S3_PROSAVAGE:
+ case S3_PROSAVAGEDDR:
+ case S3_TWISTER:
par->chan.reg = CR_SERIAL2;
par->chan.ioaddr = par->mmio.vbase;
par->chan.algo.setsda = prosavage_gpio_setsda;
diff --git a/drivers/video/savage/savagefb.h b/drivers/video/savage/savagefb.h
index 4e9490c..32549d1 100644
--- a/drivers/video/savage/savagefb.h
+++ b/drivers/video/savage/savagefb.h
@@ -36,7 +36,6 @@
#define PCI_CHIP_SAVAGE_IX 0x8c13
#define PCI_CHIP_PROSAVAGE_PM 0x8a25
#define PCI_CHIP_PROSAVAGE_KM 0x8a26
- /* Twister is a code name; hope I get the real name soon. */
#define PCI_CHIP_S3TWISTER_P 0x8d01
#define PCI_CHIP_S3TWISTER_K 0x8d02
#define PCI_CHIP_PROSAVAGE_DDR 0x8d03
@@ -52,14 +51,15 @@
#define PCI_CHIP_SUPSAV_IXCDDR 0x8c2f
+#define S3_SAVAGE_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE2000))
#define S3_SAVAGE3D_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE_MX))
-#define S3_SAVAGE4_SERIES(chip) ((chip==S3_SAVAGE4) || (chip==S3_PROSAVAGE))
+#define S3_SAVAGE4_SERIES(chip) ((chip>=S3_SAVAGE4) || (chip<=S3_PROSAVAGEDDR))
#define S3_SAVAGE_MOBILE_SERIES(chip) ((chip==S3_SAVAGE_MX) || (chip==S3_SUPERSAVAGE))
-#define S3_SAVAGE_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE2000))
+#define S3_MOBILE_TWISTER_SERIES(chip) ((chip==S3_TWISTER) || (chip==S3_PROSAVAGEDDR))
/* Chip tags. These are used to group the adapters into
* related families.
@@ -71,6 +71,8 @@
S3_SAVAGE_MX,
S3_SAVAGE4,
S3_PROSAVAGE,
+ S3_TWISTER,
+ S3_PROSAVAGEDDR,
S3_SUPERSAVAGE,
S3_SAVAGE2000,
S3_LAST
diff --git a/drivers/video/savage/savagefb_driver.c b/drivers/video/savage/savagefb_driver.c
index a2dc1a7..3b7f2f5 100644
--- a/drivers/video/savage/savagefb_driver.c
+++ b/drivers/video/savage/savagefb_driver.c
@@ -328,7 +328,9 @@
savage_out32(0x48C18, savage_in32(0x48C18, par) | 0x0C, par);
break;
case S3_SAVAGE4:
+ case S3_TWISTER:
case S3_PROSAVAGE:
+ case S3_PROSAVAGEDDR:
case S3_SUPERSAVAGE:
/* Disable BCI */
savage_out32(0x48C18, savage_in32(0x48C18, par) & 0x3FF0, par);
@@ -1886,6 +1888,8 @@
break;
case S3_PROSAVAGE:
+ case S3_PROSAVAGEDDR:
+ case S3_TWISTER:
videoRam = RamSavageNB[(config1 & 0xE0) >> 5] * 1024;
break;
@@ -1963,7 +1967,8 @@
}
}
- if (S3_SAVAGE_MOBILE_SERIES(par->chip) && !par->crtonly)
+ if ((S3_SAVAGE_MOBILE_SERIES(par->chip) ||
+ S3_MOBILE_TWISTER_SERIES(par->chip)) && !par->crtonly)
par->display_type = DISP_LCD;
else if (dvi || (par->chip == S3_SAVAGE4 && par->dvi))
par->display_type = DISP_DFP;
@@ -2111,19 +2116,19 @@
snprintf(info->fix.id, 16, "ProSavageKM");
break;
case FB_ACCEL_S3TWISTER_P:
- par->chip = S3_PROSAVAGE;
+ par->chip = S3_TWISTER;
snprintf(info->fix.id, 16, "TwisterP");
break;
case FB_ACCEL_S3TWISTER_K:
- par->chip = S3_PROSAVAGE;
+ par->chip = S3_TWISTER;
snprintf(info->fix.id, 16, "TwisterK");
break;
case FB_ACCEL_PROSAVAGE_DDR:
- par->chip = S3_PROSAVAGE;
+ par->chip = S3_PROSAVAGEDDR;
snprintf(info->fix.id, 16, "ProSavageDDR");
break;
case FB_ACCEL_PROSAVAGE_DDRK:
- par->chip = S3_PROSAVAGE;
+ par->chip = S3_PROSAVAGEDDR;
snprintf(info->fix.id, 16, "ProSavage8");
break;
}
diff --git a/drivers/video/sh7760fb.c b/drivers/video/sh7760fb.c
index 8fe1958..45e47d8 100644
--- a/drivers/video/sh7760fb.c
+++ b/drivers/video/sh7760fb.c
@@ -551,8 +551,7 @@
free_irq(par->irq, &par->vsync);
iounmap(par->base);
out_res:
- release_resource(par->ioarea);
- kfree(par->ioarea);
+ release_mem_region(res->start, resource_size(res));
out_fb:
framebuffer_release(info);
return ret;
@@ -570,8 +569,7 @@
if (par->irq >= 0)
free_irq(par->irq, par);
iounmap(par->base);
- release_resource(par->ioarea);
- kfree(par->ioarea);
+ release_mem_region(par->ioarea->start, resource_size(par->ioarea));
framebuffer_release(info);
platform_set_drvdata(dev, NULL);
diff --git a/drivers/video/sh_mobile_hdmi.c b/drivers/video/sh_mobile_hdmi.c
index 2b9e56a..6ae40b6 100644
--- a/drivers/video/sh_mobile_hdmi.c
+++ b/drivers/video/sh_mobile_hdmi.c
@@ -1131,15 +1131,19 @@
pm_runtime_get_sync(hdmi->dev);
ret = sh_hdmi_read_edid(hdmi, &hdmi_rate, &parent_rate);
- if (ret < 0)
+ if (ret < 0) {
+ pm_runtime_put(hdmi->dev);
goto out;
+ }
hdmi->hp_state = HDMI_HOTPLUG_EDID_DONE;
/* Reconfigure the clock */
ret = sh_hdmi_clk_configure(hdmi, hdmi_rate, parent_rate);
- if (ret < 0)
+ if (ret < 0) {
+ pm_runtime_put(hdmi->dev);
goto out;
+ }
msleep(10);
sh_hdmi_configure(hdmi);
@@ -1336,6 +1340,7 @@
ecodec:
free_irq(irq, hdmi);
ereqirq:
+ pm_runtime_suspend(&pdev->dev);
pm_runtime_disable(&pdev->dev);
iounmap(hdmi->base);
emap:
@@ -1372,6 +1377,7 @@
free_irq(irq, hdmi);
/* Wait for already scheduled work */
cancel_delayed_work_sync(&hdmi->edid_work);
+ pm_runtime_suspend(&pdev->dev);
pm_runtime_disable(&pdev->dev);
clk_disable(hdmi->hdmi_clk);
clk_put(hdmi->hdmi_clk);
diff --git a/drivers/video/sh_mobile_lcdcfb.c b/drivers/video/sh_mobile_lcdcfb.c
index 9bcc61b..404c03b 100644
--- a/drivers/video/sh_mobile_lcdcfb.c
+++ b/drivers/video/sh_mobile_lcdcfb.c
@@ -27,6 +27,7 @@
#include <asm/atomic.h>
#include "sh_mobile_lcdcfb.h"
+#include "sh_mobile_meram.h"
#define SIDE_B_OFFSET 0x1000
#define MIRROR_OFFSET 0x2000
@@ -143,6 +144,7 @@
unsigned long saved_shared_regs[NR_SHARED_REGS];
int started;
int forced_bpp; /* 2 channel LCDC must share bpp setting */
+ struct sh_mobile_meram_info *meram_dev;
};
static bool banked(int reg_nr)
@@ -469,7 +471,6 @@
int bpp = 0;
unsigned long ldddsr;
int k, m;
- int ret = 0;
/* enable clocks before accessing the hardware */
for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
@@ -538,11 +539,12 @@
lcdc_write_chan(ch, LDPMR, 0);
board_cfg = &ch->cfg.board_cfg;
- if (board_cfg->setup_sys)
- ret = board_cfg->setup_sys(board_cfg->board_data, ch,
- &sh_mobile_lcdc_sys_bus_ops);
- if (ret)
- return ret;
+ if (board_cfg->setup_sys) {
+ int ret = board_cfg->setup_sys(board_cfg->board_data,
+ ch, &sh_mobile_lcdc_sys_bus_ops);
+ if (ret)
+ return ret;
+ }
}
/* word and long word swap */
@@ -564,6 +566,9 @@
}
for (k = 0; k < ARRAY_SIZE(priv->ch); k++) {
+ unsigned long base_addr_y;
+ unsigned long base_addr_c = 0;
+ int pitch;
ch = &priv->ch[k];
if (!priv->ch[k].enabled)
@@ -598,16 +603,68 @@
}
lcdc_write_chan(ch, LDDFR, tmp);
- /* point out our frame buffer */
- lcdc_write_chan(ch, LDSA1R, ch->info->fix.smem_start);
- if (ch->info->var.nonstd)
- lcdc_write_chan(ch, LDSA2R,
- ch->info->fix.smem_start +
+ base_addr_y = ch->info->fix.smem_start;
+ base_addr_c = base_addr_y +
ch->info->var.xres *
- ch->info->var.yres_virtual);
+ ch->info->var.yres_virtual;
+ pitch = ch->info->fix.line_length;
+
+ /* test if we can enable meram */
+ if (ch->cfg.meram_cfg && priv->meram_dev &&
+ priv->meram_dev->ops) {
+ struct sh_mobile_meram_cfg *cfg;
+ struct sh_mobile_meram_info *mdev;
+ unsigned long icb_addr_y, icb_addr_c;
+ int icb_pitch;
+ int pf;
+
+ cfg = ch->cfg.meram_cfg;
+ mdev = priv->meram_dev;
+ /* we need to de-init configured ICBs before we
+ * we can re-initialize them.
+ */
+ if (ch->meram_enabled)
+ mdev->ops->meram_unregister(mdev, cfg);
+
+ ch->meram_enabled = 0;
+
+ if (ch->info->var.nonstd) {
+ if (ch->info->var.bits_per_pixel == 24)
+ pf = SH_MOBILE_MERAM_PF_NV24;
+ else
+ pf = SH_MOBILE_MERAM_PF_NV;
+ } else {
+ pf = SH_MOBILE_MERAM_PF_RGB;
+ }
+
+ ret = mdev->ops->meram_register(mdev, cfg, pitch,
+ ch->info->var.yres,
+ pf,
+ base_addr_y,
+ base_addr_c,
+ &icb_addr_y,
+ &icb_addr_c,
+ &icb_pitch);
+ if (!ret) {
+ /* set LDSA1R value */
+ base_addr_y = icb_addr_y;
+ pitch = icb_pitch;
+
+ /* set LDSA2R value if required */
+ if (base_addr_c)
+ base_addr_c = icb_addr_c;
+
+ ch->meram_enabled = 1;
+ }
+ }
+
+ /* point out our frame buffer */
+ lcdc_write_chan(ch, LDSA1R, base_addr_y);
+ if (ch->info->var.nonstd)
+ lcdc_write_chan(ch, LDSA2R, base_addr_c);
/* set line size */
- lcdc_write_chan(ch, LDMLSR, ch->info->fix.line_length);
+ lcdc_write_chan(ch, LDMLSR, pitch);
/* setup deferred io if SYS bus */
tmp = ch->cfg.sys_bus_cfg.deferred_io_msec;
@@ -692,6 +749,17 @@
board_cfg->display_off(board_cfg->board_data);
module_put(board_cfg->owner);
}
+
+ /* disable the meram */
+ if (ch->meram_enabled) {
+ struct sh_mobile_meram_cfg *cfg;
+ struct sh_mobile_meram_info *mdev;
+ cfg = ch->cfg.meram_cfg;
+ mdev = priv->meram_dev;
+ mdev->ops->meram_unregister(mdev, cfg);
+ ch->meram_enabled = 0;
+ }
+
}
/* stop the lcdc */
@@ -875,9 +943,29 @@
} else
base_addr_c = 0;
- lcdc_write_chan_mirror(ch, LDSA1R, base_addr_y);
- if (base_addr_c)
- lcdc_write_chan_mirror(ch, LDSA2R, base_addr_c);
+ if (!ch->meram_enabled) {
+ lcdc_write_chan_mirror(ch, LDSA1R, base_addr_y);
+ if (base_addr_c)
+ lcdc_write_chan_mirror(ch, LDSA2R, base_addr_c);
+ } else {
+ struct sh_mobile_meram_cfg *cfg;
+ struct sh_mobile_meram_info *mdev;
+ unsigned long icb_addr_y, icb_addr_c;
+ int ret;
+
+ cfg = ch->cfg.meram_cfg;
+ mdev = priv->meram_dev;
+ ret = mdev->ops->meram_update(mdev, cfg,
+ base_addr_y, base_addr_c,
+ &icb_addr_y, &icb_addr_c);
+ if (ret)
+ return ret;
+
+ lcdc_write_chan_mirror(ch, LDSA1R, icb_addr_y);
+ if (icb_addr_c)
+ lcdc_write_chan_mirror(ch, LDSA2R, icb_addr_c);
+
+ }
if (lcdc_chan_is_sublcd(ch))
lcdc_write(ch->lcdc, _LDRCNTR, ldrcntr ^ LDRCNTR_SRS);
@@ -1288,7 +1376,6 @@
struct fb_info *info = event->info;
struct sh_mobile_lcdc_chan *ch = info->par;
struct sh_mobile_lcdc_board_cfg *board_cfg = &ch->cfg.board_cfg;
- int ret;
if (&ch->lcdc->notifier != nb)
return NOTIFY_DONE;
@@ -1302,7 +1389,6 @@
board_cfg->display_off(board_cfg->board_data);
module_put(board_cfg->owner);
}
- pm_runtime_put(info->device);
sh_mobile_lcdc_stop(ch->lcdc);
break;
case FB_EVENT_RESUME:
@@ -1316,9 +1402,7 @@
module_put(board_cfg->owner);
}
- ret = sh_mobile_lcdc_start(ch->lcdc);
- if (!ret)
- pm_runtime_get_sync(info->device);
+ sh_mobile_lcdc_start(ch->lcdc);
}
return NOTIFY_OK;
@@ -1420,6 +1504,8 @@
goto err1;
}
+ priv->meram_dev = pdata->meram_dev;
+
for (i = 0; i < j; i++) {
struct fb_var_screeninfo *var;
const struct fb_videomode *lcd_cfg, *max_cfg = NULL;
diff --git a/drivers/video/sh_mobile_lcdcfb.h b/drivers/video/sh_mobile_lcdcfb.h
index f16cb56..aeed668 100644
--- a/drivers/video/sh_mobile_lcdcfb.h
+++ b/drivers/video/sh_mobile_lcdcfb.h
@@ -39,6 +39,7 @@
int use_count;
int blank_status;
struct mutex open_lock; /* protects the use counter */
+ int meram_enabled;
};
#endif
diff --git a/drivers/video/sh_mobile_meram.c b/drivers/video/sh_mobile_meram.c
new file mode 100644
index 0000000..9170c82
--- /dev/null
+++ b/drivers/video/sh_mobile_meram.c
@@ -0,0 +1,567 @@
+/*
+ * SuperH Mobile MERAM Driver for SuperH Mobile LCDC Driver
+ *
+ * Copyright (c) 2011 Damian Hobson-Garcia <dhobsong@igel.co.jp>
+ * Takanari Hayama <taki@igel.co.jp>
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/device.h>
+#include <linux/io.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+
+#include "sh_mobile_meram.h"
+
+/* meram registers */
+#define MExxCTL 0x0
+#define MExxBSIZE 0x4
+#define MExxMNCF 0x8
+#define MExxSARA 0x10
+#define MExxSARB 0x14
+#define MExxSBSIZE 0x18
+
+#define MERAM_MExxCTL_VAL(ctl, next_icb, addr) \
+ ((ctl) | (((next_icb) & 0x1f) << 11) | (((addr) & 0x7ff) << 16))
+#define MERAM_MExxBSIZE_VAL(a, b, c) \
+ (((a) << 28) | ((b) << 16) | (c))
+
+#define MEVCR1 0x4
+#define MEACTS 0x10
+#define MEQSEL1 0x40
+#define MEQSEL2 0x44
+
+/* settings */
+#define MERAM_SEC_LINE 15
+#define MERAM_LINE_WIDTH 2048
+
+/*
+ * MERAM/ICB access functions
+ */
+
+#define MERAM_ICB_OFFSET(base, idx, off) \
+ ((base) + (0x400 + ((idx) * 0x20) + (off)))
+
+static inline void meram_write_icb(void __iomem *base, int idx, int off,
+ unsigned long val)
+{
+ iowrite32(val, MERAM_ICB_OFFSET(base, idx, off));
+}
+
+static inline unsigned long meram_read_icb(void __iomem *base, int idx, int off)
+{
+ return ioread32(MERAM_ICB_OFFSET(base, idx, off));
+}
+
+static inline void meram_write_reg(void __iomem *base, int off,
+ unsigned long val)
+{
+ iowrite32(val, base + off);
+}
+
+static inline unsigned long meram_read_reg(void __iomem *base, int off)
+{
+ return ioread32(base + off);
+}
+
+/*
+ * register ICB
+ */
+
+#define MERAM_CACHE_START(p) ((p) >> 16)
+#define MERAM_CACHE_END(p) ((p) & 0xffff)
+#define MERAM_CACHE_SET(o, s) ((((o) & 0xffff) << 16) | \
+ (((o) + (s) - 1) & 0xffff))
+
+/*
+ * check if there's no overlaps in MERAM allocation.
+ */
+
+static inline int meram_check_overlap(struct sh_mobile_meram_priv *priv,
+ struct sh_mobile_meram_icb *new)
+{
+ int i;
+ int used_start, used_end, meram_start, meram_end;
+
+ /* valid ICB? */
+ if (new->marker_icb & ~0x1f || new->cache_icb & ~0x1f)
+ return 1;
+
+ if (test_bit(new->marker_icb, &priv->used_icb) ||
+ test_bit(new->cache_icb, &priv->used_icb))
+ return 1;
+
+ for (i = 0; i < priv->used_meram_cache_regions; i++) {
+ used_start = MERAM_CACHE_START(priv->used_meram_cache[i]);
+ used_end = MERAM_CACHE_END(priv->used_meram_cache[i]);
+ meram_start = new->meram_offset;
+ meram_end = new->meram_offset + new->meram_size;
+
+ if ((meram_start >= used_start && meram_start < used_end) ||
+ (meram_end > used_start && meram_end < used_end))
+ return 1;
+ }
+
+ return 0;
+}
+
+/*
+ * mark the specified ICB as used
+ */
+
+static inline void meram_mark(struct sh_mobile_meram_priv *priv,
+ struct sh_mobile_meram_icb *new)
+{
+ int n;
+
+ if (new->marker_icb < 0 || new->cache_icb < 0)
+ return;
+
+ __set_bit(new->marker_icb, &priv->used_icb);
+ __set_bit(new->cache_icb, &priv->used_icb);
+
+ n = priv->used_meram_cache_regions;
+
+ priv->used_meram_cache[n] = MERAM_CACHE_SET(new->meram_offset,
+ new->meram_size);
+
+ priv->used_meram_cache_regions++;
+}
+
+/*
+ * unmark the specified ICB as used
+ */
+
+static inline void meram_unmark(struct sh_mobile_meram_priv *priv,
+ struct sh_mobile_meram_icb *icb)
+{
+ int i;
+ unsigned long pattern;
+
+ if (icb->marker_icb < 0 || icb->cache_icb < 0)
+ return;
+
+ __clear_bit(icb->marker_icb, &priv->used_icb);
+ __clear_bit(icb->cache_icb, &priv->used_icb);
+
+ pattern = MERAM_CACHE_SET(icb->meram_offset, icb->meram_size);
+ for (i = 0; i < priv->used_meram_cache_regions; i++) {
+ if (priv->used_meram_cache[i] == pattern) {
+ while (i < priv->used_meram_cache_regions - 1) {
+ priv->used_meram_cache[i] =
+ priv->used_meram_cache[i + 1] ;
+ i++;
+ }
+ priv->used_meram_cache[i] = 0;
+ priv->used_meram_cache_regions--;
+ break;
+ }
+ }
+}
+
+/*
+ * is this a YCbCr(NV12, NV16 or NV24) colorspace
+ */
+static inline int is_nvcolor(int cspace)
+{
+ if (cspace == SH_MOBILE_MERAM_PF_NV ||
+ cspace == SH_MOBILE_MERAM_PF_NV24)
+ return 1;
+ return 0;
+}
+
+/*
+ * set the next address to fetch
+ */
+static inline void meram_set_next_addr(struct sh_mobile_meram_priv *priv,
+ struct sh_mobile_meram_cfg *cfg,
+ unsigned long base_addr_y,
+ unsigned long base_addr_c)
+{
+ unsigned long target;
+
+ target = (cfg->current_reg) ? MExxSARA : MExxSARB;
+ cfg->current_reg ^= 1;
+
+ /* set the next address to fetch */
+ meram_write_icb(priv->base, cfg->icb[0].cache_icb, target,
+ base_addr_y);
+ meram_write_icb(priv->base, cfg->icb[0].marker_icb, target,
+ base_addr_y + cfg->icb[0].cache_unit);
+
+ if (is_nvcolor(cfg->pixelformat)) {
+ meram_write_icb(priv->base, cfg->icb[1].cache_icb, target,
+ base_addr_c);
+ meram_write_icb(priv->base, cfg->icb[1].marker_icb, target,
+ base_addr_c + cfg->icb[1].cache_unit);
+ }
+}
+
+/*
+ * get the next ICB address
+ */
+static inline void meram_get_next_icb_addr(struct sh_mobile_meram_info *pdata,
+ struct sh_mobile_meram_cfg *cfg,
+ unsigned long *icb_addr_y,
+ unsigned long *icb_addr_c)
+{
+ unsigned long icb_offset;
+
+ if (pdata->addr_mode == SH_MOBILE_MERAM_MODE0)
+ icb_offset = 0x80000000 | (cfg->current_reg << 29);
+ else
+ icb_offset = 0xc0000000 | (cfg->current_reg << 23);
+
+ *icb_addr_y = icb_offset | (cfg->icb[0].marker_icb << 24);
+ if ((*icb_addr_c) && is_nvcolor(cfg->pixelformat))
+ *icb_addr_c = icb_offset | (cfg->icb[1].marker_icb << 24);
+}
+
+#define MERAM_CALC_BYTECOUNT(x, y) \
+ (((x) * (y) + (MERAM_LINE_WIDTH - 1)) & ~(MERAM_LINE_WIDTH - 1))
+
+/*
+ * initialize MERAM
+ */
+
+static int meram_init(struct sh_mobile_meram_priv *priv,
+ struct sh_mobile_meram_icb *icb,
+ int xres, int yres, int *out_pitch)
+{
+ unsigned long total_byte_count = MERAM_CALC_BYTECOUNT(xres, yres);
+ unsigned long bnm;
+ int lcdc_pitch, xpitch, line_cnt;
+ int save_lines;
+
+ /* adjust pitch to 1024, 2048, 4096 or 8192 */
+ lcdc_pitch = (xres - 1) | 1023;
+ lcdc_pitch = lcdc_pitch | (lcdc_pitch >> 1);
+ lcdc_pitch = lcdc_pitch | (lcdc_pitch >> 2);
+ lcdc_pitch += 1;
+
+ /* derive settings */
+ if (lcdc_pitch == 8192 && yres >= 1024) {
+ lcdc_pitch = xpitch = MERAM_LINE_WIDTH;
+ line_cnt = total_byte_count >> 11;
+ *out_pitch = xres;
+ save_lines = (icb->meram_size / 16 / MERAM_SEC_LINE);
+ save_lines *= MERAM_SEC_LINE;
+ } else {
+ xpitch = xres;
+ line_cnt = yres;
+ *out_pitch = lcdc_pitch;
+ save_lines = icb->meram_size / (lcdc_pitch >> 10) / 2;
+ save_lines &= 0xff;
+ }
+ bnm = (save_lines - 1) << 16;
+
+ /* TODO: we better to check if we have enough MERAM buffer size */
+
+ /* set up ICB */
+ meram_write_icb(priv->base, icb->cache_icb, MExxBSIZE,
+ MERAM_MExxBSIZE_VAL(0x0, line_cnt - 1, xpitch - 1));
+ meram_write_icb(priv->base, icb->marker_icb, MExxBSIZE,
+ MERAM_MExxBSIZE_VAL(0xf, line_cnt - 1, xpitch - 1));
+
+ meram_write_icb(priv->base, icb->cache_icb, MExxMNCF, bnm);
+ meram_write_icb(priv->base, icb->marker_icb, MExxMNCF, bnm);
+
+ meram_write_icb(priv->base, icb->cache_icb, MExxSBSIZE, xpitch);
+ meram_write_icb(priv->base, icb->marker_icb, MExxSBSIZE, xpitch);
+
+ /* save a cache unit size */
+ icb->cache_unit = xres * save_lines;
+
+ /*
+ * Set MERAM for framebuffer
+ *
+ * 0x70f: WD = 0x3, WS=0x1, CM=0x1, MD=FB mode
+ * we also chain the cache_icb and the marker_icb.
+ * we also split the allocated MERAM buffer between two ICBs.
+ */
+ meram_write_icb(priv->base, icb->cache_icb, MExxCTL,
+ MERAM_MExxCTL_VAL(0x70f, icb->marker_icb,
+ icb->meram_offset));
+ meram_write_icb(priv->base, icb->marker_icb, MExxCTL,
+ MERAM_MExxCTL_VAL(0x70f, icb->cache_icb,
+ icb->meram_offset +
+ icb->meram_size / 2));
+
+ return 0;
+}
+
+static void meram_deinit(struct sh_mobile_meram_priv *priv,
+ struct sh_mobile_meram_icb *icb)
+{
+ /* disable ICB */
+ meram_write_icb(priv->base, icb->cache_icb, MExxCTL, 0);
+ meram_write_icb(priv->base, icb->marker_icb, MExxCTL, 0);
+ icb->cache_unit = 0;
+}
+
+/*
+ * register the ICB
+ */
+
+static int sh_mobile_meram_register(struct sh_mobile_meram_info *pdata,
+ struct sh_mobile_meram_cfg *cfg,
+ int xres, int yres, int pixelformat,
+ unsigned long base_addr_y,
+ unsigned long base_addr_c,
+ unsigned long *icb_addr_y,
+ unsigned long *icb_addr_c,
+ int *pitch)
+{
+ struct platform_device *pdev;
+ struct sh_mobile_meram_priv *priv;
+ int n, out_pitch;
+ int error = 0;
+
+ if (!pdata || !pdata->priv || !pdata->pdev || !cfg)
+ return -EINVAL;
+
+ if (pixelformat != SH_MOBILE_MERAM_PF_NV &&
+ pixelformat != SH_MOBILE_MERAM_PF_NV24 &&
+ pixelformat != SH_MOBILE_MERAM_PF_RGB)
+ return -EINVAL;
+
+ priv = pdata->priv;
+ pdev = pdata->pdev;
+
+ dev_dbg(&pdev->dev, "registering %dx%d (%s) (y=%08lx, c=%08lx)",
+ xres, yres, (!pixelformat) ? "yuv" : "rgb",
+ base_addr_y, base_addr_c);
+
+ mutex_lock(&priv->lock);
+
+ /* we can't handle wider than 8192px */
+ if (xres > 8192) {
+ dev_err(&pdev->dev, "width exceeding the limit (> 8192).");
+ error = -EINVAL;
+ goto err;
+ }
+
+ if (priv->used_meram_cache_regions + 2 > SH_MOBILE_MERAM_ICB_NUM) {
+ dev_err(&pdev->dev, "no more ICB available.");
+ error = -EINVAL;
+ goto err;
+ }
+
+ /* do we have at least one ICB config? */
+ if (cfg->icb[0].marker_icb < 0 || cfg->icb[0].cache_icb < 0) {
+ dev_err(&pdev->dev, "at least one ICB is required.");
+ error = -EINVAL;
+ goto err;
+ }
+
+ /* make sure that there's no overlaps */
+ if (meram_check_overlap(priv, &cfg->icb[0])) {
+ dev_err(&pdev->dev, "conflicting config detected.");
+ error = -EINVAL;
+ goto err;
+ }
+ n = 1;
+
+ /* do the same if we have the second ICB set */
+ if (cfg->icb[1].marker_icb >= 0 && cfg->icb[1].cache_icb >= 0) {
+ if (meram_check_overlap(priv, &cfg->icb[1])) {
+ dev_err(&pdev->dev, "conflicting config detected.");
+ error = -EINVAL;
+ goto err;
+ }
+ n = 2;
+ }
+
+ if (is_nvcolor(pixelformat) && n != 2) {
+ dev_err(&pdev->dev, "requires two ICB sets for planar Y/C.");
+ error = -EINVAL;
+ goto err;
+ }
+
+ /* we now register the ICB */
+ cfg->pixelformat = pixelformat;
+ meram_mark(priv, &cfg->icb[0]);
+ if (is_nvcolor(pixelformat))
+ meram_mark(priv, &cfg->icb[1]);
+
+ /* initialize MERAM */
+ meram_init(priv, &cfg->icb[0], xres, yres, &out_pitch);
+ *pitch = out_pitch;
+ if (pixelformat == SH_MOBILE_MERAM_PF_NV)
+ meram_init(priv, &cfg->icb[1], xres, (yres + 1) / 2,
+ &out_pitch);
+ else if (pixelformat == SH_MOBILE_MERAM_PF_NV24)
+ meram_init(priv, &cfg->icb[1], 2 * xres, (yres + 1) / 2,
+ &out_pitch);
+
+ cfg->current_reg = 1;
+ meram_set_next_addr(priv, cfg, base_addr_y, base_addr_c);
+ meram_get_next_icb_addr(pdata, cfg, icb_addr_y, icb_addr_c);
+
+ dev_dbg(&pdev->dev, "registered - can access via y=%08lx, c=%08lx",
+ *icb_addr_y, *icb_addr_c);
+
+err:
+ mutex_unlock(&priv->lock);
+ return error;
+}
+
+static int sh_mobile_meram_unregister(struct sh_mobile_meram_info *pdata,
+ struct sh_mobile_meram_cfg *cfg)
+{
+ struct sh_mobile_meram_priv *priv;
+
+ if (!pdata || !pdata->priv || !cfg)
+ return -EINVAL;
+
+ priv = pdata->priv;
+
+ mutex_lock(&priv->lock);
+
+ /* deinit & unmark */
+ if (is_nvcolor(cfg->pixelformat)) {
+ meram_deinit(priv, &cfg->icb[1]);
+ meram_unmark(priv, &cfg->icb[1]);
+ }
+ meram_deinit(priv, &cfg->icb[0]);
+ meram_unmark(priv, &cfg->icb[0]);
+
+ mutex_unlock(&priv->lock);
+
+ return 0;
+}
+
+static int sh_mobile_meram_update(struct sh_mobile_meram_info *pdata,
+ struct sh_mobile_meram_cfg *cfg,
+ unsigned long base_addr_y,
+ unsigned long base_addr_c,
+ unsigned long *icb_addr_y,
+ unsigned long *icb_addr_c)
+{
+ struct sh_mobile_meram_priv *priv;
+
+ if (!pdata || !pdata->priv || !cfg)
+ return -EINVAL;
+
+ priv = pdata->priv;
+
+ mutex_lock(&priv->lock);
+
+ meram_set_next_addr(priv, cfg, base_addr_y, base_addr_c);
+ meram_get_next_icb_addr(pdata, cfg, icb_addr_y, icb_addr_c);
+
+ mutex_unlock(&priv->lock);
+
+ return 0;
+}
+
+static struct sh_mobile_meram_ops sh_mobile_meram_ops = {
+ .module = THIS_MODULE,
+ .meram_register = sh_mobile_meram_register,
+ .meram_unregister = sh_mobile_meram_unregister,
+ .meram_update = sh_mobile_meram_update,
+};
+
+/*
+ * initialize MERAM
+ */
+
+static int sh_mobile_meram_remove(struct platform_device *pdev);
+
+static int __devinit sh_mobile_meram_probe(struct platform_device *pdev)
+{
+ struct sh_mobile_meram_priv *priv;
+ struct sh_mobile_meram_info *pdata = pdev->dev.platform_data;
+ struct resource *res;
+ int error;
+
+ if (!pdata) {
+ dev_err(&pdev->dev, "no platform data defined\n");
+ return -EINVAL;
+ }
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ if (!res) {
+ dev_err(&pdev->dev, "cannot get platform resources\n");
+ return -ENOENT;
+ }
+
+ priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+ if (!priv) {
+ dev_err(&pdev->dev, "cannot allocate device data\n");
+ return -ENOMEM;
+ }
+
+ platform_set_drvdata(pdev, priv);
+
+ /* initialize private data */
+ mutex_init(&priv->lock);
+ priv->base = ioremap_nocache(res->start, resource_size(res));
+ if (!priv->base) {
+ dev_err(&pdev->dev, "ioremap failed\n");
+ error = -EFAULT;
+ goto err;
+ }
+ pdata->ops = &sh_mobile_meram_ops;
+ pdata->priv = priv;
+ pdata->pdev = pdev;
+
+ /* initialize ICB addressing mode */
+ if (pdata->addr_mode == SH_MOBILE_MERAM_MODE1)
+ meram_write_reg(priv->base, MEVCR1, 1 << 29);
+
+ dev_info(&pdev->dev, "sh_mobile_meram initialized.");
+
+ return 0;
+
+err:
+ sh_mobile_meram_remove(pdev);
+
+ return error;
+}
+
+
+static int sh_mobile_meram_remove(struct platform_device *pdev)
+{
+ struct sh_mobile_meram_priv *priv = platform_get_drvdata(pdev);
+
+ if (priv->base)
+ iounmap(priv->base);
+
+ mutex_destroy(&priv->lock);
+
+ kfree(priv);
+
+ return 0;
+}
+
+static struct platform_driver sh_mobile_meram_driver = {
+ .driver = {
+ .name = "sh_mobile_meram",
+ .owner = THIS_MODULE,
+ },
+ .probe = sh_mobile_meram_probe,
+ .remove = sh_mobile_meram_remove,
+};
+
+static int __init sh_mobile_meram_init(void)
+{
+ return platform_driver_register(&sh_mobile_meram_driver);
+}
+
+static void __exit sh_mobile_meram_exit(void)
+{
+ platform_driver_unregister(&sh_mobile_meram_driver);
+}
+
+module_init(sh_mobile_meram_init);
+module_exit(sh_mobile_meram_exit);
+
+MODULE_DESCRIPTION("SuperH Mobile MERAM driver");
+MODULE_AUTHOR("Damian Hobson-Garcia / Takanari Hayama");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/video/sh_mobile_meram.h b/drivers/video/sh_mobile_meram.h
new file mode 100644
index 0000000..82c54fb
--- /dev/null
+++ b/drivers/video/sh_mobile_meram.h
@@ -0,0 +1,41 @@
+#ifndef __sh_mobile_meram_h__
+#define __sh_mobile_meram_h__
+
+#include <linux/mutex.h>
+#include <video/sh_mobile_meram.h>
+
+/*
+ * MERAM private
+ */
+
+#define MERAM_ICB_Y 0x1
+#define MERAM_ICB_C 0x2
+
+/* MERAM cache size */
+#define SH_MOBILE_MERAM_ICB_NUM 32
+
+#define SH_MOBILE_MERAM_CACHE_OFFSET(p) ((p) >> 16)
+#define SH_MOBILE_MERAM_CACHE_SIZE(p) ((p) & 0xffff)
+
+struct sh_mobile_meram_priv {
+ void __iomem *base;
+ struct mutex lock;
+ unsigned long used_icb;
+ int used_meram_cache_regions;
+ unsigned long used_meram_cache[SH_MOBILE_MERAM_ICB_NUM];
+};
+
+int sh_mobile_meram_alloc_icb(const struct sh_mobile_meram_cfg *cfg,
+ int xres,
+ int yres,
+ unsigned int base_addr,
+ int yuv_mode,
+ int *marker_icb,
+ int *out_pitch);
+
+void sh_mobile_meram_free_icb(int marker_icb);
+
+#define SH_MOBILE_MERAM_START(ind, ab) \
+ (0xC0000000 | ((ab & 0x1) << 23) | ((ind & 0x1F) << 24))
+
+#endif /* !__sh_mobile_meram_h__ */
diff --git a/drivers/video/sm501fb.c b/drivers/video/sm501fb.c
index 56ef6b3..87f0be1 100644
--- a/drivers/video/sm501fb.c
+++ b/drivers/video/sm501fb.c
@@ -1625,22 +1625,22 @@
return 0; /* everything is setup */
err_mem_res:
- release_resource(info->fbmem_res);
- kfree(info->fbmem_res);
+ release_mem_region(info->fbmem_res->start,
+ resource_size(info->fbmem_res));
err_regs2d_map:
iounmap(info->regs2d);
err_regs2d_res:
- release_resource(info->regs2d_res);
- kfree(info->regs2d_res);
+ release_mem_region(info->regs2d_res->start,
+ resource_size(info->regs2d_res));
err_regs_map:
iounmap(info->regs);
err_regs_res:
- release_resource(info->regs_res);
- kfree(info->regs_res);
+ release_mem_region(info->regs_res->start,
+ resource_size(info->regs_res));
err_release:
return ret;
@@ -1652,16 +1652,16 @@
sm501_unit_power(info->dev->parent, SM501_GATE_DISPLAY, 0);
iounmap(info->fbmem);
- release_resource(info->fbmem_res);
- kfree(info->fbmem_res);
+ release_mem_region(info->fbmem_res->start,
+ resource_size(info->fbmem_res));
iounmap(info->regs2d);
- release_resource(info->regs2d_res);
- kfree(info->regs2d_res);
+ release_mem_region(info->regs2d_res->start,
+ resource_size(info->regs2d_res));
iounmap(info->regs);
- release_resource(info->regs_res);
- kfree(info->regs_res);
+ release_mem_region(info->regs_res->start,
+ resource_size(info->regs_res));
}
static int sm501fb_init_fb(struct fb_info *fb,
diff --git a/drivers/video/udlfb.c b/drivers/video/udlfb.c
index 695066b..52b0f3e 100644
--- a/drivers/video/udlfb.c
+++ b/drivers/video/udlfb.c
@@ -29,6 +29,7 @@
#include <linux/slab.h>
#include <linux/prefetch.h>
#include <linux/delay.h>
+#include <linux/prefetch.h>
#include <video/udlfb.h>
#include "edid.h"
@@ -1587,10 +1588,19 @@
goto error;
}
- for (i = 0; i < ARRAY_SIZE(fb_device_attrs); i++)
- device_create_file(info->dev, &fb_device_attrs[i]);
+ for (i = 0; i < ARRAY_SIZE(fb_device_attrs); i++) {
+ retval = device_create_file(info->dev, &fb_device_attrs[i]);
+ if (retval) {
+ pr_err("device_create_file failed %d\n", retval);
+ goto err_del_attrs;
+ }
+ }
- device_create_bin_file(info->dev, &edid_attr);
+ retval = device_create_bin_file(info->dev, &edid_attr);
+ if (retval) {
+ pr_err("device_create_bin_file failed %d\n", retval);
+ goto err_del_attrs;
+ }
pr_info("DisplayLink USB device /dev/fb%d attached. %dx%d resolution."
" Using %dK framebuffer memory\n", info->node,
@@ -1599,6 +1609,10 @@
info->fix.smem_len * 2 : info->fix.smem_len) >> 10);
return 0;
+err_del_attrs:
+ for (i -= 1; i >= 0; i--)
+ device_remove_file(info->dev, &fb_device_attrs[i]);
+
error:
if (dev) {
diff --git a/fs/9p/Kconfig b/fs/9p/Kconfig
index 814ac4e..0a93dc1 100644
--- a/fs/9p/Kconfig
+++ b/fs/9p/Kconfig
@@ -1,6 +1,6 @@
config 9P_FS
- tristate "Plan 9 Resource Sharing Support (9P2000) (Experimental)"
- depends on INET && NET_9P && EXPERIMENTAL
+ tristate "Plan 9 Resource Sharing Support (9P2000)"
+ depends on INET && NET_9P
help
If you say Y here, you will get experimental support for
Plan 9 resource sharing via the 9P2000 protocol.
@@ -10,7 +10,6 @@
If unsure, say N.
if 9P_FS
-
config 9P_FSCACHE
bool "Enable 9P client caching support (EXPERIMENTAL)"
depends on EXPERIMENTAL
diff --git a/fs/9p/vfs_inode_dotl.c b/fs/9p/vfs_inode_dotl.c
index 82a7c38..691c78f 100644
--- a/fs/9p/vfs_inode_dotl.c
+++ b/fs/9p/vfs_inode_dotl.c
@@ -259,7 +259,7 @@
if (IS_ERR(inode_fid)) {
err = PTR_ERR(inode_fid);
mutex_unlock(&v9inode->v_mutex);
- goto error;
+ goto err_clunk_old_fid;
}
v9inode->writeback_fid = (void *) inode_fid;
}
@@ -267,8 +267,8 @@
/* Since we are opening a file, assign the open fid to the file */
filp = lookup_instantiate_filp(nd, dentry, generic_file_open);
if (IS_ERR(filp)) {
- p9_client_clunk(ofid);
- return PTR_ERR(filp);
+ err = PTR_ERR(filp);
+ goto err_clunk_old_fid;
}
filp->private_data = ofid;
#ifdef CONFIG_9P_FSCACHE
@@ -278,10 +278,11 @@
return 0;
error:
- if (ofid)
- p9_client_clunk(ofid);
if (fid)
p9_client_clunk(fid);
+err_clunk_old_fid:
+ if (ofid)
+ p9_client_clunk(ofid);
return err;
}
diff --git a/fs/Kconfig b/fs/Kconfig
index f3aa9b0..979992d 100644
--- a/fs/Kconfig
+++ b/fs/Kconfig
@@ -121,9 +121,25 @@
See <file:Documentation/filesystems/tmpfs.txt> for details.
+config TMPFS_XATTR
+ bool "Tmpfs extended attributes"
+ depends on TMPFS
+ default n
+ help
+ Extended attributes are name:value pairs associated with inodes by
+ the kernel or by users (see the attr(5) manual page, or visit
+ <http://acl.bestbits.at/> for details).
+
+ Currently this enables support for the trusted.* and
+ security.* namespaces.
+
+ If unsure, say N.
+
+ You need this for POSIX ACL support on tmpfs.
+
config TMPFS_POSIX_ACL
bool "Tmpfs POSIX Access Control Lists"
- depends on TMPFS
+ depends on TMPFS_XATTR
select GENERIC_ACL
help
POSIX Access Control Lists (ACLs) support permissions for users and
diff --git a/fs/binfmt_flat.c b/fs/binfmt_flat.c
index 397d305..1bffbe0 100644
--- a/fs/binfmt_flat.c
+++ b/fs/binfmt_flat.c
@@ -820,6 +820,8 @@
int res;
char buf[16];
+ memset(&bprm, 0, sizeof(bprm));
+
/* Create the file name */
sprintf(buf, "/lib/lib%d.so", id);
@@ -835,6 +837,12 @@
if (!bprm.cred)
goto out;
+ /* We don't really care about recalculating credentials at this point
+ * as we're past the point of no return and are dealing with shared
+ * libraries.
+ */
+ bprm.cred_prepared = 1;
+
res = prepare_binprm(&bprm);
if (!IS_ERR_VALUE(res))
diff --git a/fs/block_dev.c b/fs/block_dev.c
index bf9c7a7..1f2b199 100644
--- a/fs/block_dev.c
+++ b/fs/block_dev.c
@@ -1238,6 +1238,8 @@
res = __blkdev_get(bdev, mode, 0);
if (whole) {
+ struct gendisk *disk = whole->bd_disk;
+
/* finish claiming */
mutex_lock(&bdev->bd_mutex);
spin_lock(&bdev_lock);
@@ -1264,15 +1266,16 @@
spin_unlock(&bdev_lock);
/*
- * Block event polling for write claims. Any write
- * holder makes the write_holder state stick until all
- * are released. This is good enough and tracking
- * individual writeable reference is too fragile given
- * the way @mode is used in blkdev_get/put().
+ * Block event polling for write claims if requested. Any
+ * write holder makes the write_holder state stick until
+ * all are released. This is good enough and tracking
+ * individual writeable reference is too fragile given the
+ * way @mode is used in blkdev_get/put().
*/
- if (!res && (mode & FMODE_WRITE) && !bdev->bd_write_holder) {
+ if ((disk->flags & GENHD_FL_BLOCK_EVENTS_ON_EXCL_WRITE) &&
+ !res && (mode & FMODE_WRITE) && !bdev->bd_write_holder) {
bdev->bd_write_holder = true;
- disk_block_events(bdev->bd_disk);
+ disk_block_events(disk);
}
mutex_unlock(&bdev->bd_mutex);
diff --git a/fs/ceph/addr.c b/fs/ceph/addr.c
index 38b8ab5..33da49d 100644
--- a/fs/ceph/addr.c
+++ b/fs/ceph/addr.c
@@ -848,7 +848,8 @@
op->payload_len = cpu_to_le32(len);
req->r_request->hdr.data_len = cpu_to_le32(len);
- ceph_osdc_start_request(&fsc->client->osdc, req, true);
+ rc = ceph_osdc_start_request(&fsc->client->osdc, req, true);
+ BUG_ON(rc);
req = NULL;
/* continue? */
@@ -880,8 +881,6 @@
out:
if (req)
ceph_osdc_put_request(req);
- if (rc > 0)
- rc = 0; /* vfs expects us to return 0 */
ceph_put_snap_context(snapc);
dout("writepages done, rc = %d\n", rc);
return rc;
diff --git a/fs/ceph/caps.c b/fs/ceph/caps.c
index 2a5404c..1f72b00 100644
--- a/fs/ceph/caps.c
+++ b/fs/ceph/caps.c
@@ -569,7 +569,8 @@
list_add_tail(&cap->session_caps, &session->s_caps);
session->s_nr_caps++;
spin_unlock(&session->s_cap_lock);
- }
+ } else if (new_cap)
+ ceph_put_cap(mdsc, new_cap);
if (!ci->i_snap_realm) {
/*
@@ -2634,6 +2635,7 @@
struct ceph_mds_session *session,
int *open_target_sessions)
{
+ struct ceph_mds_client *mdsc = ceph_inode_to_client(inode)->mdsc;
struct ceph_inode_info *ci = ceph_inode(inode);
int mds = session->s_mds;
unsigned mseq = le32_to_cpu(ex->migrate_seq);
@@ -2670,6 +2672,19 @@
* export targets, so that we get the matching IMPORT
*/
*open_target_sessions = 1;
+
+ /*
+ * we can't flush dirty caps that we've seen the
+ * EXPORT but no IMPORT for
+ */
+ spin_lock(&mdsc->cap_dirty_lock);
+ if (!list_empty(&ci->i_dirty_item)) {
+ dout(" moving %p to cap_dirty_migrating\n",
+ inode);
+ list_move(&ci->i_dirty_item,
+ &mdsc->cap_dirty_migrating);
+ }
+ spin_unlock(&mdsc->cap_dirty_lock);
}
__ceph_remove_cap(cap);
}
@@ -2707,6 +2722,13 @@
ci->i_cap_exporting_issued = 0;
ci->i_cap_exporting_mseq = 0;
ci->i_cap_exporting_mds = -1;
+
+ spin_lock(&mdsc->cap_dirty_lock);
+ if (!list_empty(&ci->i_dirty_item)) {
+ dout(" moving %p back to cap_dirty\n", inode);
+ list_move(&ci->i_dirty_item, &mdsc->cap_dirty);
+ }
+ spin_unlock(&mdsc->cap_dirty_lock);
} else {
dout("handle_cap_import inode %p ci %p mds%d mseq %d\n",
inode, ci, mds, mseq);
@@ -2910,38 +2932,16 @@
*/
void ceph_flush_dirty_caps(struct ceph_mds_client *mdsc)
{
- struct ceph_inode_info *ci, *nci = NULL;
- struct inode *inode, *ninode = NULL;
- struct list_head *p, *n;
+ struct ceph_inode_info *ci;
+ struct inode *inode;
dout("flush_dirty_caps\n");
spin_lock(&mdsc->cap_dirty_lock);
- list_for_each_safe(p, n, &mdsc->cap_dirty) {
- if (nci) {
- ci = nci;
- inode = ninode;
- ci->i_ceph_flags &= ~CEPH_I_NOFLUSH;
- dout("flush_dirty_caps inode %p (was next inode)\n",
- inode);
- } else {
- ci = list_entry(p, struct ceph_inode_info,
- i_dirty_item);
- inode = igrab(&ci->vfs_inode);
- BUG_ON(!inode);
- dout("flush_dirty_caps inode %p\n", inode);
- }
- if (n != &mdsc->cap_dirty) {
- nci = list_entry(n, struct ceph_inode_info,
- i_dirty_item);
- ninode = igrab(&nci->vfs_inode);
- BUG_ON(!ninode);
- nci->i_ceph_flags |= CEPH_I_NOFLUSH;
- dout("flush_dirty_caps next inode %p, noflush\n",
- ninode);
- } else {
- nci = NULL;
- ninode = NULL;
- }
+ while (!list_empty(&mdsc->cap_dirty)) {
+ ci = list_first_entry(&mdsc->cap_dirty, struct ceph_inode_info,
+ i_dirty_item);
+ inode = igrab(&ci->vfs_inode);
+ dout("flush_dirty_caps %p\n", inode);
spin_unlock(&mdsc->cap_dirty_lock);
if (inode) {
ceph_check_caps(ci, CHECK_CAPS_NODELAY|CHECK_CAPS_FLUSH,
@@ -2951,6 +2951,7 @@
spin_lock(&mdsc->cap_dirty_lock);
}
spin_unlock(&mdsc->cap_dirty_lock);
+ dout("flush_dirty_caps done\n");
}
/*
diff --git a/fs/ceph/dir.c b/fs/ceph/dir.c
index 1a867a3..33729e8 100644
--- a/fs/ceph/dir.c
+++ b/fs/ceph/dir.c
@@ -360,7 +360,7 @@
rinfo = &fi->last_readdir->r_reply_info;
dout("readdir frag %x num %d off %d chunkoff %d\n", frag,
rinfo->dir_nr, off, fi->offset);
- while (off - fi->offset >= 0 && off - fi->offset < rinfo->dir_nr) {
+ while (off >= fi->offset && off - fi->offset < rinfo->dir_nr) {
u64 pos = ceph_make_fpos(frag, off);
struct ceph_mds_reply_inode *in =
rinfo->dir_in[off - fi->offset].in;
@@ -1066,16 +1066,17 @@
struct inode *inode = file->f_dentry->d_inode;
struct ceph_inode_info *ci = ceph_inode(inode);
int left;
+ const int bufsize = 1024;
if (!ceph_test_mount_opt(ceph_sb_to_client(inode->i_sb), DIRSTAT))
return -EISDIR;
if (!cf->dir_info) {
- cf->dir_info = kmalloc(1024, GFP_NOFS);
+ cf->dir_info = kmalloc(bufsize, GFP_NOFS);
if (!cf->dir_info)
return -ENOMEM;
cf->dir_info_len =
- sprintf(cf->dir_info,
+ snprintf(cf->dir_info, bufsize,
"entries: %20lld\n"
" files: %20lld\n"
" subdirs: %20lld\n"
diff --git a/fs/ceph/export.c b/fs/ceph/export.c
index e410561..a610d3d 100644
--- a/fs/ceph/export.c
+++ b/fs/ceph/export.c
@@ -86,6 +86,7 @@
static struct dentry *__fh_to_dentry(struct super_block *sb,
struct ceph_nfs_fh *fh)
{
+ struct ceph_mds_client *mdsc = ceph_sb_to_client(sb)->mdsc;
struct inode *inode;
struct dentry *dentry;
struct ceph_vino vino;
@@ -95,8 +96,24 @@
vino.ino = fh->ino;
vino.snap = CEPH_NOSNAP;
inode = ceph_find_inode(sb, vino);
- if (!inode)
- return ERR_PTR(-ESTALE);
+ if (!inode) {
+ struct ceph_mds_request *req;
+
+ req = ceph_mdsc_create_request(mdsc, CEPH_MDS_OP_LOOKUPINO,
+ USE_ANY_MDS);
+ if (IS_ERR(req))
+ return ERR_CAST(req);
+
+ req->r_ino1 = vino;
+ req->r_num_caps = 1;
+ err = ceph_mdsc_do_request(mdsc, NULL, req);
+ inode = req->r_target_inode;
+ if (inode)
+ igrab(inode);
+ ceph_mdsc_put_request(req);
+ if (!inode)
+ return ERR_PTR(-ESTALE);
+ }
dentry = d_obtain_alias(inode);
if (IS_ERR(dentry)) {
@@ -148,8 +165,10 @@
snprintf(req->r_path2, 16, "%d", cfh->parent_name_hash);
req->r_num_caps = 1;
err = ceph_mdsc_do_request(mdsc, NULL, req);
+ inode = req->r_target_inode;
+ if (inode)
+ igrab(inode);
ceph_mdsc_put_request(req);
- inode = ceph_find_inode(sb, vino);
if (!inode)
return ERR_PTR(err ? err : -ESTALE);
}
diff --git a/fs/ceph/mds_client.c b/fs/ceph/mds_client.c
index d0fae4c..79743d1 100644
--- a/fs/ceph/mds_client.c
+++ b/fs/ceph/mds_client.c
@@ -578,6 +578,7 @@
if (dir) {
struct ceph_inode_info *ci = ceph_inode(dir);
+ ihold(dir);
spin_lock(&ci->i_unsafe_lock);
req->r_unsafe_dir = dir;
list_add_tail(&req->r_unsafe_dir_item, &ci->i_unsafe_dirops);
@@ -598,6 +599,9 @@
spin_lock(&ci->i_unsafe_lock);
list_del_init(&req->r_unsafe_dir_item);
spin_unlock(&ci->i_unsafe_lock);
+
+ iput(req->r_unsafe_dir);
+ req->r_unsafe_dir = NULL;
}
ceph_mdsc_put_request(req);
@@ -2691,7 +2695,6 @@
{
struct super_block *sb = mdsc->fsc->sb;
struct inode *inode;
- struct ceph_inode_info *ci;
struct dentry *parent, *dentry;
struct ceph_dentry_info *di;
int mds = session->s_mds;
@@ -2728,7 +2731,6 @@
dout("handle_lease no inode %llx\n", vino.ino);
goto release;
}
- ci = ceph_inode(inode);
/* dentry */
parent = d_find_alias(inode);
@@ -3002,6 +3004,7 @@
spin_lock_init(&mdsc->snap_flush_lock);
mdsc->cap_flush_seq = 0;
INIT_LIST_HEAD(&mdsc->cap_dirty);
+ INIT_LIST_HEAD(&mdsc->cap_dirty_migrating);
mdsc->num_cap_flushing = 0;
spin_lock_init(&mdsc->cap_dirty_lock);
init_waitqueue_head(&mdsc->cap_flushing_wq);
diff --git a/fs/ceph/mds_client.h b/fs/ceph/mds_client.h
index 4e3a9cc..7d8a0d6 100644
--- a/fs/ceph/mds_client.h
+++ b/fs/ceph/mds_client.h
@@ -278,6 +278,7 @@
u64 cap_flush_seq;
struct list_head cap_dirty; /* inodes with dirty caps */
+ struct list_head cap_dirty_migrating; /* ...that are migration... */
int num_cap_flushing; /* # caps we are flushing */
spinlock_t cap_dirty_lock; /* protects above items */
wait_queue_head_t cap_flushing_wq;
diff --git a/fs/dcache.c b/fs/dcache.c
index 18b2a1f..37f72ee 100644
--- a/fs/dcache.c
+++ b/fs/dcache.c
@@ -1220,7 +1220,7 @@
EXPORT_SYMBOL(shrink_dcache_parent);
/*
- * Scan `nr' dentries and return the number which remain.
+ * Scan `sc->nr_slab_to_reclaim' dentries and return the number which remain.
*
* We need to avoid reentering the filesystem if the caller is performing a
* GFP_NOFS allocation attempt. One example deadlock is:
@@ -1231,8 +1231,12 @@
*
* In this case we return -1 to tell the caller that we baled.
*/
-static int shrink_dcache_memory(struct shrinker *shrink, int nr, gfp_t gfp_mask)
+static int shrink_dcache_memory(struct shrinker *shrink,
+ struct shrink_control *sc)
{
+ int nr = sc->nr_to_scan;
+ gfp_t gfp_mask = sc->gfp_mask;
+
if (nr) {
if (!(gfp_mask & __GFP_FS))
return -1;
diff --git a/fs/dlm/config.c b/fs/dlm/config.c
index 0d329ff..9b026ea 100644
--- a/fs/dlm/config.c
+++ b/fs/dlm/config.c
@@ -100,6 +100,7 @@
unsigned int cl_log_debug;
unsigned int cl_protocol;
unsigned int cl_timewarn_cs;
+ unsigned int cl_waitwarn_us;
};
enum {
@@ -114,6 +115,7 @@
CLUSTER_ATTR_LOG_DEBUG,
CLUSTER_ATTR_PROTOCOL,
CLUSTER_ATTR_TIMEWARN_CS,
+ CLUSTER_ATTR_WAITWARN_US,
};
struct cluster_attribute {
@@ -166,6 +168,7 @@
CLUSTER_ATTR(log_debug, 0);
CLUSTER_ATTR(protocol, 0);
CLUSTER_ATTR(timewarn_cs, 1);
+CLUSTER_ATTR(waitwarn_us, 0);
static struct configfs_attribute *cluster_attrs[] = {
[CLUSTER_ATTR_TCP_PORT] = &cluster_attr_tcp_port.attr,
@@ -179,6 +182,7 @@
[CLUSTER_ATTR_LOG_DEBUG] = &cluster_attr_log_debug.attr,
[CLUSTER_ATTR_PROTOCOL] = &cluster_attr_protocol.attr,
[CLUSTER_ATTR_TIMEWARN_CS] = &cluster_attr_timewarn_cs.attr,
+ [CLUSTER_ATTR_WAITWARN_US] = &cluster_attr_waitwarn_us.attr,
NULL,
};
@@ -439,6 +443,7 @@
cl->cl_log_debug = dlm_config.ci_log_debug;
cl->cl_protocol = dlm_config.ci_protocol;
cl->cl_timewarn_cs = dlm_config.ci_timewarn_cs;
+ cl->cl_waitwarn_us = dlm_config.ci_waitwarn_us;
space_list = &sps->ss_group;
comm_list = &cms->cs_group;
@@ -986,6 +991,7 @@
#define DEFAULT_LOG_DEBUG 0
#define DEFAULT_PROTOCOL 0
#define DEFAULT_TIMEWARN_CS 500 /* 5 sec = 500 centiseconds */
+#define DEFAULT_WAITWARN_US 0
struct dlm_config_info dlm_config = {
.ci_tcp_port = DEFAULT_TCP_PORT,
@@ -998,6 +1004,7 @@
.ci_scan_secs = DEFAULT_SCAN_SECS,
.ci_log_debug = DEFAULT_LOG_DEBUG,
.ci_protocol = DEFAULT_PROTOCOL,
- .ci_timewarn_cs = DEFAULT_TIMEWARN_CS
+ .ci_timewarn_cs = DEFAULT_TIMEWARN_CS,
+ .ci_waitwarn_us = DEFAULT_WAITWARN_US
};
diff --git a/fs/dlm/config.h b/fs/dlm/config.h
index 4f1d6fc..dd0ce24 100644
--- a/fs/dlm/config.h
+++ b/fs/dlm/config.h
@@ -28,6 +28,7 @@
int ci_log_debug;
int ci_protocol;
int ci_timewarn_cs;
+ int ci_waitwarn_us;
};
extern struct dlm_config_info dlm_config;
diff --git a/fs/dlm/dlm_internal.h b/fs/dlm/dlm_internal.h
index b942049..0262451 100644
--- a/fs/dlm/dlm_internal.h
+++ b/fs/dlm/dlm_internal.h
@@ -209,6 +209,7 @@
#define DLM_IFL_WATCH_TIMEWARN 0x00400000
#define DLM_IFL_TIMEOUT_CANCEL 0x00800000
#define DLM_IFL_DEADLOCK_CANCEL 0x01000000
+#define DLM_IFL_STUB_MS 0x02000000 /* magic number for m_flags */
#define DLM_IFL_USER 0x00000001
#define DLM_IFL_ORPHAN 0x00000002
@@ -245,6 +246,7 @@
int8_t lkb_wait_type; /* type of reply waiting for */
int8_t lkb_wait_count;
+ int lkb_wait_nodeid; /* for debugging */
struct list_head lkb_idtbl_list; /* lockspace lkbtbl */
struct list_head lkb_statequeue; /* rsb g/c/w list */
@@ -254,6 +256,7 @@
struct list_head lkb_ownqueue; /* list of locks for a process */
struct list_head lkb_time_list;
ktime_t lkb_timestamp;
+ ktime_t lkb_wait_time;
unsigned long lkb_timeout_cs;
struct dlm_callback lkb_callbacks[DLM_CALLBACKS_SIZE];
diff --git a/fs/dlm/lock.c b/fs/dlm/lock.c
index 56d6bfc..f71d0b5 100644
--- a/fs/dlm/lock.c
+++ b/fs/dlm/lock.c
@@ -799,10 +799,84 @@
return -1;
}
+static int nodeid_warned(int nodeid, int num_nodes, int *warned)
+{
+ int i;
+
+ for (i = 0; i < num_nodes; i++) {
+ if (!warned[i]) {
+ warned[i] = nodeid;
+ return 0;
+ }
+ if (warned[i] == nodeid)
+ return 1;
+ }
+ return 0;
+}
+
+void dlm_scan_waiters(struct dlm_ls *ls)
+{
+ struct dlm_lkb *lkb;
+ ktime_t zero = ktime_set(0, 0);
+ s64 us;
+ s64 debug_maxus = 0;
+ u32 debug_scanned = 0;
+ u32 debug_expired = 0;
+ int num_nodes = 0;
+ int *warned = NULL;
+
+ if (!dlm_config.ci_waitwarn_us)
+ return;
+
+ mutex_lock(&ls->ls_waiters_mutex);
+
+ list_for_each_entry(lkb, &ls->ls_waiters, lkb_wait_reply) {
+ if (ktime_equal(lkb->lkb_wait_time, zero))
+ continue;
+
+ debug_scanned++;
+
+ us = ktime_to_us(ktime_sub(ktime_get(), lkb->lkb_wait_time));
+
+ if (us < dlm_config.ci_waitwarn_us)
+ continue;
+
+ lkb->lkb_wait_time = zero;
+
+ debug_expired++;
+ if (us > debug_maxus)
+ debug_maxus = us;
+
+ if (!num_nodes) {
+ num_nodes = ls->ls_num_nodes;
+ warned = kmalloc(GFP_KERNEL, num_nodes * sizeof(int));
+ if (warned)
+ memset(warned, 0, num_nodes * sizeof(int));
+ }
+ if (!warned)
+ continue;
+ if (nodeid_warned(lkb->lkb_wait_nodeid, num_nodes, warned))
+ continue;
+
+ log_error(ls, "waitwarn %x %lld %d us check connection to "
+ "node %d", lkb->lkb_id, (long long)us,
+ dlm_config.ci_waitwarn_us, lkb->lkb_wait_nodeid);
+ }
+ mutex_unlock(&ls->ls_waiters_mutex);
+
+ if (warned)
+ kfree(warned);
+
+ if (debug_expired)
+ log_debug(ls, "scan_waiters %u warn %u over %d us max %lld us",
+ debug_scanned, debug_expired,
+ dlm_config.ci_waitwarn_us, (long long)debug_maxus);
+}
+
/* add/remove lkb from global waiters list of lkb's waiting for
a reply from a remote node */
-static int add_to_waiters(struct dlm_lkb *lkb, int mstype)
+static int add_to_waiters(struct dlm_lkb *lkb, int mstype, int to_nodeid)
{
struct dlm_ls *ls = lkb->lkb_resource->res_ls;
int error = 0;
@@ -842,6 +916,8 @@
lkb->lkb_wait_count++;
lkb->lkb_wait_type = mstype;
+ lkb->lkb_wait_time = ktime_get();
+ lkb->lkb_wait_nodeid = to_nodeid; /* for debugging */
hold_lkb(lkb);
list_add(&lkb->lkb_wait_reply, &ls->ls_waiters);
out:
@@ -961,10 +1037,10 @@
struct dlm_ls *ls = lkb->lkb_resource->res_ls;
int error;
- if (ms != &ls->ls_stub_ms)
+ if (ms->m_flags != DLM_IFL_STUB_MS)
mutex_lock(&ls->ls_waiters_mutex);
error = _remove_from_waiters(lkb, ms->m_type, ms);
- if (ms != &ls->ls_stub_ms)
+ if (ms->m_flags != DLM_IFL_STUB_MS)
mutex_unlock(&ls->ls_waiters_mutex);
return error;
}
@@ -1157,6 +1233,16 @@
list_for_each_entry(lkb, &ls->ls_timeout, lkb_time_list)
lkb->lkb_timestamp = ktime_add_us(lkb->lkb_timestamp, adj_us);
mutex_unlock(&ls->ls_timeout_mutex);
+
+ if (!dlm_config.ci_waitwarn_us)
+ return;
+
+ mutex_lock(&ls->ls_waiters_mutex);
+ list_for_each_entry(lkb, &ls->ls_waiters, lkb_wait_reply) {
+ if (ktime_to_us(lkb->lkb_wait_time))
+ lkb->lkb_wait_time = ktime_get();
+ }
+ mutex_unlock(&ls->ls_waiters_mutex);
}
/* lkb is master or local copy */
@@ -1376,14 +1462,8 @@
ALTPR/ALTCW: our rqmode may have been changed to PR or CW to become
compatible with other granted locks */
-static void munge_demoted(struct dlm_lkb *lkb, struct dlm_message *ms)
+static void munge_demoted(struct dlm_lkb *lkb)
{
- if (ms->m_type != DLM_MSG_CONVERT_REPLY) {
- log_print("munge_demoted %x invalid reply type %d",
- lkb->lkb_id, ms->m_type);
- return;
- }
-
if (lkb->lkb_rqmode == DLM_LOCK_IV || lkb->lkb_grmode == DLM_LOCK_IV) {
log_print("munge_demoted %x invalid modes gr %d rq %d",
lkb->lkb_id, lkb->lkb_grmode, lkb->lkb_rqmode);
@@ -2844,12 +2924,12 @@
struct dlm_mhandle *mh;
int to_nodeid, error;
- error = add_to_waiters(lkb, mstype);
+ to_nodeid = r->res_nodeid;
+
+ error = add_to_waiters(lkb, mstype, to_nodeid);
if (error)
return error;
- to_nodeid = r->res_nodeid;
-
error = create_message(r, lkb, to_nodeid, mstype, &ms, &mh);
if (error)
goto fail;
@@ -2880,9 +2960,9 @@
/* down conversions go without a reply from the master */
if (!error && down_conversion(lkb)) {
remove_from_waiters(lkb, DLM_MSG_CONVERT_REPLY);
+ r->res_ls->ls_stub_ms.m_flags = DLM_IFL_STUB_MS;
r->res_ls->ls_stub_ms.m_type = DLM_MSG_CONVERT_REPLY;
r->res_ls->ls_stub_ms.m_result = 0;
- r->res_ls->ls_stub_ms.m_flags = lkb->lkb_flags;
__receive_convert_reply(r, lkb, &r->res_ls->ls_stub_ms);
}
@@ -2951,12 +3031,12 @@
struct dlm_mhandle *mh;
int to_nodeid, error;
- error = add_to_waiters(lkb, DLM_MSG_LOOKUP);
+ to_nodeid = dlm_dir_nodeid(r);
+
+ error = add_to_waiters(lkb, DLM_MSG_LOOKUP, to_nodeid);
if (error)
return error;
- to_nodeid = dlm_dir_nodeid(r);
-
error = create_message(r, NULL, to_nodeid, DLM_MSG_LOOKUP, &ms, &mh);
if (error)
goto fail;
@@ -3070,6 +3150,9 @@
static void receive_flags_reply(struct dlm_lkb *lkb, struct dlm_message *ms)
{
+ if (ms->m_flags == DLM_IFL_STUB_MS)
+ return;
+
lkb->lkb_sbflags = ms->m_sbflags;
lkb->lkb_flags = (lkb->lkb_flags & 0xFFFF0000) |
(ms->m_flags & 0x0000FFFF);
@@ -3612,7 +3695,7 @@
/* convert was queued on remote master */
receive_flags_reply(lkb, ms);
if (is_demoted(lkb))
- munge_demoted(lkb, ms);
+ munge_demoted(lkb);
del_lkb(r, lkb);
add_lkb(r, lkb, DLM_LKSTS_CONVERT);
add_timeout(lkb);
@@ -3622,7 +3705,7 @@
/* convert was granted on remote master */
receive_flags_reply(lkb, ms);
if (is_demoted(lkb))
- munge_demoted(lkb, ms);
+ munge_demoted(lkb);
grant_lock_pc(r, lkb, ms);
queue_cast(r, lkb, 0);
break;
@@ -3996,15 +4079,17 @@
dlm_put_lockspace(ls);
}
-static void recover_convert_waiter(struct dlm_ls *ls, struct dlm_lkb *lkb)
+static void recover_convert_waiter(struct dlm_ls *ls, struct dlm_lkb *lkb,
+ struct dlm_message *ms_stub)
{
if (middle_conversion(lkb)) {
hold_lkb(lkb);
- ls->ls_stub_ms.m_type = DLM_MSG_CONVERT_REPLY;
- ls->ls_stub_ms.m_result = -EINPROGRESS;
- ls->ls_stub_ms.m_flags = lkb->lkb_flags;
- ls->ls_stub_ms.m_header.h_nodeid = lkb->lkb_nodeid;
- _receive_convert_reply(lkb, &ls->ls_stub_ms);
+ memset(ms_stub, 0, sizeof(struct dlm_message));
+ ms_stub->m_flags = DLM_IFL_STUB_MS;
+ ms_stub->m_type = DLM_MSG_CONVERT_REPLY;
+ ms_stub->m_result = -EINPROGRESS;
+ ms_stub->m_header.h_nodeid = lkb->lkb_nodeid;
+ _receive_convert_reply(lkb, ms_stub);
/* Same special case as in receive_rcom_lock_args() */
lkb->lkb_grmode = DLM_LOCK_IV;
@@ -4045,13 +4130,27 @@
void dlm_recover_waiters_pre(struct dlm_ls *ls)
{
struct dlm_lkb *lkb, *safe;
+ struct dlm_message *ms_stub;
int wait_type, stub_unlock_result, stub_cancel_result;
+ ms_stub = kmalloc(GFP_KERNEL, sizeof(struct dlm_message));
+ if (!ms_stub) {
+ log_error(ls, "dlm_recover_waiters_pre no mem");
+ return;
+ }
+
mutex_lock(&ls->ls_waiters_mutex);
list_for_each_entry_safe(lkb, safe, &ls->ls_waiters, lkb_wait_reply) {
- log_debug(ls, "pre recover waiter lkid %x type %d flags %x",
- lkb->lkb_id, lkb->lkb_wait_type, lkb->lkb_flags);
+
+ /* exclude debug messages about unlocks because there can be so
+ many and they aren't very interesting */
+
+ if (lkb->lkb_wait_type != DLM_MSG_UNLOCK) {
+ log_debug(ls, "recover_waiter %x nodeid %d "
+ "msg %d to %d", lkb->lkb_id, lkb->lkb_nodeid,
+ lkb->lkb_wait_type, lkb->lkb_wait_nodeid);
+ }
/* all outstanding lookups, regardless of destination will be
resent after recovery is done */
@@ -4097,26 +4196,28 @@
break;
case DLM_MSG_CONVERT:
- recover_convert_waiter(ls, lkb);
+ recover_convert_waiter(ls, lkb, ms_stub);
break;
case DLM_MSG_UNLOCK:
hold_lkb(lkb);
- ls->ls_stub_ms.m_type = DLM_MSG_UNLOCK_REPLY;
- ls->ls_stub_ms.m_result = stub_unlock_result;
- ls->ls_stub_ms.m_flags = lkb->lkb_flags;
- ls->ls_stub_ms.m_header.h_nodeid = lkb->lkb_nodeid;
- _receive_unlock_reply(lkb, &ls->ls_stub_ms);
+ memset(ms_stub, 0, sizeof(struct dlm_message));
+ ms_stub->m_flags = DLM_IFL_STUB_MS;
+ ms_stub->m_type = DLM_MSG_UNLOCK_REPLY;
+ ms_stub->m_result = stub_unlock_result;
+ ms_stub->m_header.h_nodeid = lkb->lkb_nodeid;
+ _receive_unlock_reply(lkb, ms_stub);
dlm_put_lkb(lkb);
break;
case DLM_MSG_CANCEL:
hold_lkb(lkb);
- ls->ls_stub_ms.m_type = DLM_MSG_CANCEL_REPLY;
- ls->ls_stub_ms.m_result = stub_cancel_result;
- ls->ls_stub_ms.m_flags = lkb->lkb_flags;
- ls->ls_stub_ms.m_header.h_nodeid = lkb->lkb_nodeid;
- _receive_cancel_reply(lkb, &ls->ls_stub_ms);
+ memset(ms_stub, 0, sizeof(struct dlm_message));
+ ms_stub->m_flags = DLM_IFL_STUB_MS;
+ ms_stub->m_type = DLM_MSG_CANCEL_REPLY;
+ ms_stub->m_result = stub_cancel_result;
+ ms_stub->m_header.h_nodeid = lkb->lkb_nodeid;
+ _receive_cancel_reply(lkb, ms_stub);
dlm_put_lkb(lkb);
break;
@@ -4127,6 +4228,7 @@
schedule();
}
mutex_unlock(&ls->ls_waiters_mutex);
+ kfree(ms_stub);
}
static struct dlm_lkb *find_resend_waiter(struct dlm_ls *ls)
@@ -4191,8 +4293,8 @@
ou = is_overlap_unlock(lkb);
err = 0;
- log_debug(ls, "recover_waiters_post %x type %d flags %x %s",
- lkb->lkb_id, mstype, lkb->lkb_flags, r->res_name);
+ log_debug(ls, "recover_waiter %x nodeid %d msg %d r_nodeid %d",
+ lkb->lkb_id, lkb->lkb_nodeid, mstype, r->res_nodeid);
/* At this point we assume that we won't get a reply to any
previous op or overlap op on this lock. First, do a big
diff --git a/fs/dlm/lock.h b/fs/dlm/lock.h
index 88e93c8..265017a 100644
--- a/fs/dlm/lock.h
+++ b/fs/dlm/lock.h
@@ -24,6 +24,7 @@
void dlm_scan_rsbs(struct dlm_ls *ls);
int dlm_lock_recovery_try(struct dlm_ls *ls);
void dlm_unlock_recovery(struct dlm_ls *ls);
+void dlm_scan_waiters(struct dlm_ls *ls);
void dlm_scan_timeout(struct dlm_ls *ls);
void dlm_adjust_timeouts(struct dlm_ls *ls);
diff --git a/fs/dlm/lockspace.c b/fs/dlm/lockspace.c
index f994a7d..14cbf40 100644
--- a/fs/dlm/lockspace.c
+++ b/fs/dlm/lockspace.c
@@ -243,7 +243,6 @@
static int dlm_scand(void *data)
{
struct dlm_ls *ls;
- int timeout_jiffies = dlm_config.ci_scan_secs * HZ;
while (!kthread_should_stop()) {
ls = find_ls_to_scan();
@@ -252,13 +251,14 @@
ls->ls_scan_time = jiffies;
dlm_scan_rsbs(ls);
dlm_scan_timeout(ls);
+ dlm_scan_waiters(ls);
dlm_unlock_recovery(ls);
} else {
ls->ls_scan_time += HZ;
}
- } else {
- schedule_timeout_interruptible(timeout_jiffies);
+ continue;
}
+ schedule_timeout_interruptible(dlm_config.ci_scan_secs * HZ);
}
return 0;
}
diff --git a/fs/dlm/plock.c b/fs/dlm/plock.c
index 30d8b85..e2b8780 100644
--- a/fs/dlm/plock.c
+++ b/fs/dlm/plock.c
@@ -71,6 +71,36 @@
wake_up(&send_wq);
}
+/* If a process was killed while waiting for the only plock on a file,
+ locks_remove_posix will not see any lock on the file so it won't
+ send an unlock-close to us to pass on to userspace to clean up the
+ abandoned waiter. So, we have to insert the unlock-close when the
+ lock call is interrupted. */
+
+static void do_unlock_close(struct dlm_ls *ls, u64 number,
+ struct file *file, struct file_lock *fl)
+{
+ struct plock_op *op;
+
+ op = kzalloc(sizeof(*op), GFP_NOFS);
+ if (!op)
+ return;
+
+ op->info.optype = DLM_PLOCK_OP_UNLOCK;
+ op->info.pid = fl->fl_pid;
+ op->info.fsid = ls->ls_global_id;
+ op->info.number = number;
+ op->info.start = 0;
+ op->info.end = OFFSET_MAX;
+ if (fl->fl_lmops && fl->fl_lmops->fl_grant)
+ op->info.owner = (__u64) fl->fl_pid;
+ else
+ op->info.owner = (__u64)(long) fl->fl_owner;
+
+ op->info.flags |= DLM_PLOCK_FL_CLOSE;
+ send_op(op);
+}
+
int dlm_posix_lock(dlm_lockspace_t *lockspace, u64 number, struct file *file,
int cmd, struct file_lock *fl)
{
@@ -114,9 +144,19 @@
send_op(op);
- if (xop->callback == NULL)
- wait_event(recv_wq, (op->done != 0));
- else {
+ if (xop->callback == NULL) {
+ rv = wait_event_killable(recv_wq, (op->done != 0));
+ if (rv == -ERESTARTSYS) {
+ log_debug(ls, "dlm_posix_lock: wait killed %llx",
+ (unsigned long long)number);
+ spin_lock(&ops_lock);
+ list_del(&op->list);
+ spin_unlock(&ops_lock);
+ kfree(xop);
+ do_unlock_close(ls, number, file, fl);
+ goto out;
+ }
+ } else {
rv = FILE_LOCK_DEFERRED;
goto out;
}
@@ -233,6 +273,13 @@
else
op->info.owner = (__u64)(long) fl->fl_owner;
+ if (fl->fl_flags & FL_CLOSE) {
+ op->info.flags |= DLM_PLOCK_FL_CLOSE;
+ send_op(op);
+ rv = 0;
+ goto out;
+ }
+
send_op(op);
wait_event(recv_wq, (op->done != 0));
@@ -334,7 +381,10 @@
spin_lock(&ops_lock);
if (!list_empty(&send_list)) {
op = list_entry(send_list.next, struct plock_op, list);
- list_move(&op->list, &recv_list);
+ if (op->info.flags & DLM_PLOCK_FL_CLOSE)
+ list_del(&op->list);
+ else
+ list_move(&op->list, &recv_list);
memcpy(&info, &op->info, sizeof(info));
}
spin_unlock(&ops_lock);
@@ -342,6 +392,13 @@
if (!op)
return -EAGAIN;
+ /* there is no need to get a reply from userspace for unlocks
+ that were generated by the vfs cleaning up for a close
+ (the process did not make an unlock call). */
+
+ if (op->info.flags & DLM_PLOCK_FL_CLOSE)
+ kfree(op);
+
if (copy_to_user(u, &info, sizeof(info)))
return -EFAULT;
return sizeof(info);
diff --git a/fs/dlm/user.c b/fs/dlm/user.c
index d5ab3fe..e96bf3e 100644
--- a/fs/dlm/user.c
+++ b/fs/dlm/user.c
@@ -611,7 +611,6 @@
out_sig:
sigprocmask(SIG_SETMASK, &tmpsig, NULL);
- recalc_sigpending();
out_free:
kfree(kbuf);
return error;
diff --git a/fs/drop_caches.c b/fs/drop_caches.c
index 98b77c8..c00e055 100644
--- a/fs/drop_caches.c
+++ b/fs/drop_caches.c
@@ -40,9 +40,12 @@
static void drop_slab(void)
{
int nr_objects;
+ struct shrink_control shrink = {
+ .gfp_mask = GFP_KERNEL,
+ };
do {
- nr_objects = shrink_slab(1000, GFP_KERNEL, 1000);
+ nr_objects = shrink_slab(&shrink, 1000, 1000);
} while (nr_objects > 10);
}
diff --git a/fs/exec.c b/fs/exec.c
index c016896..936f577 100644
--- a/fs/exec.c
+++ b/fs/exec.c
@@ -200,7 +200,7 @@
#ifdef CONFIG_STACK_GROWSUP
if (write) {
- ret = expand_stack_downwards(bprm->vma, pos);
+ ret = expand_downwards(bprm->vma, pos);
if (ret < 0)
return NULL;
}
@@ -600,7 +600,7 @@
unsigned long length = old_end - old_start;
unsigned long new_start = old_start - shift;
unsigned long new_end = old_end - shift;
- struct mmu_gather *tlb;
+ struct mmu_gather tlb;
BUG_ON(new_start > new_end);
@@ -626,12 +626,12 @@
return -ENOMEM;
lru_add_drain();
- tlb = tlb_gather_mmu(mm, 0);
+ tlb_gather_mmu(&tlb, mm, 0);
if (new_end > old_start) {
/*
* when the old and new regions overlap clear from new_end.
*/
- free_pgd_range(tlb, new_end, old_end, new_end,
+ free_pgd_range(&tlb, new_end, old_end, new_end,
vma->vm_next ? vma->vm_next->vm_start : 0);
} else {
/*
@@ -640,10 +640,10 @@
* have constraints on va-space that make this illegal (IA64) -
* for the others its just a little faster.
*/
- free_pgd_range(tlb, old_start, old_end, new_end,
+ free_pgd_range(&tlb, old_start, old_end, new_end,
vma->vm_next ? vma->vm_next->vm_start : 0);
}
- tlb_finish_mmu(tlb, new_end, old_end);
+ tlb_finish_mmu(&tlb, new_end, old_end);
/*
* Shrink the vma to just the new range. Always succeeds.
@@ -1051,6 +1051,7 @@
task_unlock(tsk);
return buf;
}
+EXPORT_SYMBOL_GPL(get_task_comm);
void set_task_comm(struct task_struct *tsk, char *buf)
{
diff --git a/fs/ext2/super.c b/fs/ext2/super.c
index 0a78dae..1dd62ed 100644
--- a/fs/ext2/super.c
+++ b/fs/ext2/super.c
@@ -898,7 +898,8 @@
brelse(bh);
if (!sb_set_blocksize(sb, blocksize)) {
- ext2_msg(sb, KERN_ERR, "error: blocksize is too small");
+ ext2_msg(sb, KERN_ERR,
+ "error: bad blocksize %d", blocksize);
goto failed_sbi;
}
diff --git a/fs/ext3/namei.c b/fs/ext3/namei.c
index 32f3b86..34b6d9b 100644
--- a/fs/ext3/namei.c
+++ b/fs/ext3/namei.c
@@ -1416,10 +1416,19 @@
frame->at = entries;
frame->bh = bh;
bh = bh2;
+ /*
+ * Mark buffers dirty here so that if do_split() fails we write a
+ * consistent set of buffers to disk.
+ */
+ ext3_journal_dirty_metadata(handle, frame->bh);
+ ext3_journal_dirty_metadata(handle, bh);
de = do_split(handle,dir, &bh, frame, &hinfo, &retval);
- dx_release (frames);
- if (!(de))
+ if (!de) {
+ ext3_mark_inode_dirty(handle, dir);
+ dx_release(frames);
return retval;
+ }
+ dx_release(frames);
return add_dirent_to_buf(handle, dentry, inode, de, bh);
}
@@ -2189,6 +2198,7 @@
handle_t *handle;
struct inode * inode;
int l, err, retries = 0;
+ int credits;
l = strlen(symname)+1;
if (l > dir->i_sb->s_blocksize)
@@ -2196,10 +2206,26 @@
dquot_initialize(dir);
+ if (l > EXT3_N_BLOCKS * 4) {
+ /*
+ * For non-fast symlinks, we just allocate inode and put it on
+ * orphan list in the first transaction => we need bitmap,
+ * group descriptor, sb, inode block, quota blocks.
+ */
+ credits = 4 + EXT3_MAXQUOTAS_INIT_BLOCKS(dir->i_sb);
+ } else {
+ /*
+ * Fast symlink. We have to add entry to directory
+ * (EXT3_DATA_TRANS_BLOCKS + EXT3_INDEX_EXTRA_TRANS_BLOCKS),
+ * allocate new inode (bitmap, group descriptor, inode block,
+ * quota blocks, sb is already counted in previous macros).
+ */
+ credits = EXT3_DATA_TRANS_BLOCKS(dir->i_sb) +
+ EXT3_INDEX_EXTRA_TRANS_BLOCKS + 3 +
+ EXT3_MAXQUOTAS_INIT_BLOCKS(dir->i_sb);
+ }
retry:
- handle = ext3_journal_start(dir, EXT3_DATA_TRANS_BLOCKS(dir->i_sb) +
- EXT3_INDEX_EXTRA_TRANS_BLOCKS + 5 +
- EXT3_MAXQUOTAS_INIT_BLOCKS(dir->i_sb));
+ handle = ext3_journal_start(dir, credits);
if (IS_ERR(handle))
return PTR_ERR(handle);
@@ -2211,21 +2237,45 @@
if (IS_ERR(inode))
goto out_stop;
- if (l > sizeof (EXT3_I(inode)->i_data)) {
+ if (l > EXT3_N_BLOCKS * 4) {
inode->i_op = &ext3_symlink_inode_operations;
ext3_set_aops(inode);
/*
- * page_symlink() calls into ext3_prepare/commit_write.
- * We have a transaction open. All is sweetness. It also sets
- * i_size in generic_commit_write().
+ * We cannot call page_symlink() with transaction started
+ * because it calls into ext3_write_begin() which acquires page
+ * lock which ranks below transaction start (and it can also
+ * wait for journal commit if we are running out of space). So
+ * we have to stop transaction now and restart it when symlink
+ * contents is written.
+ *
+ * To keep fs consistent in case of crash, we have to put inode
+ * to orphan list in the mean time.
*/
+ drop_nlink(inode);
+ err = ext3_orphan_add(handle, inode);
+ ext3_journal_stop(handle);
+ if (err)
+ goto err_drop_inode;
err = __page_symlink(inode, symname, l, 1);
+ if (err)
+ goto err_drop_inode;
+ /*
+ * Now inode is being linked into dir (EXT3_DATA_TRANS_BLOCKS
+ * + EXT3_INDEX_EXTRA_TRANS_BLOCKS), inode is also modified
+ */
+ handle = ext3_journal_start(dir,
+ EXT3_DATA_TRANS_BLOCKS(dir->i_sb) +
+ EXT3_INDEX_EXTRA_TRANS_BLOCKS + 1);
+ if (IS_ERR(handle)) {
+ err = PTR_ERR(handle);
+ goto err_drop_inode;
+ }
+ inc_nlink(inode);
+ err = ext3_orphan_del(handle, inode);
if (err) {
+ ext3_journal_stop(handle);
drop_nlink(inode);
- unlock_new_inode(inode);
- ext3_mark_inode_dirty(handle, inode);
- iput (inode);
- goto out_stop;
+ goto err_drop_inode;
}
} else {
inode->i_op = &ext3_fast_symlink_inode_operations;
@@ -2239,6 +2289,10 @@
if (err == -ENOSPC && ext3_should_retry_alloc(dir->i_sb, &retries))
goto retry;
return err;
+err_drop_inode:
+ unlock_new_inode(inode);
+ iput(inode);
+ return err;
}
static int ext3_link (struct dentry * old_dentry,
diff --git a/fs/fat/cache.c b/fs/fat/cache.c
index ae8200f..1cc7038 100644
--- a/fs/fat/cache.c
+++ b/fs/fat/cache.c
@@ -151,6 +151,13 @@
spin_unlock(&MSDOS_I(inode)->cache_lru_lock);
tmp = fat_cache_alloc(inode);
+ if (!tmp) {
+ spin_lock(&MSDOS_I(inode)->cache_lru_lock);
+ MSDOS_I(inode)->nr_caches--;
+ spin_unlock(&MSDOS_I(inode)->cache_lru_lock);
+ return;
+ }
+
spin_lock(&MSDOS_I(inode)->cache_lru_lock);
cache = fat_cache_merge(inode, new);
if (cache != NULL) {
diff --git a/fs/fat/dir.c b/fs/fat/dir.c
index ee42b9e..4ad6473 100644
--- a/fs/fat/dir.c
+++ b/fs/fat/dir.c
@@ -98,7 +98,7 @@
*bh = sb_bread(sb, phys);
if (*bh == NULL) {
- printk(KERN_ERR "FAT: Directory bread(block %llu) failed\n",
+ fat_msg(sb, KERN_ERR, "Directory bread(block %llu) failed",
(llu)phys);
/* skip this block */
*pos = (iblock + 1) << sb->s_blocksize_bits;
@@ -136,9 +136,10 @@
* but ignore that right now.
* Ahem... Stack smashing in ring 0 isn't fun. Fixed.
*/
-static int uni16_to_x8(unsigned char *ascii, const wchar_t *uni, int len,
- int uni_xlate, struct nls_table *nls)
+static int uni16_to_x8(struct super_block *sb, unsigned char *ascii,
+ const wchar_t *uni, int len, struct nls_table *nls)
{
+ int uni_xlate = MSDOS_SB(sb)->options.unicode_xlate;
const wchar_t *ip;
wchar_t ec;
unsigned char *op;
@@ -166,23 +167,23 @@
}
if (unlikely(*ip)) {
- printk(KERN_WARNING "FAT: filename was truncated while "
- "converting.");
+ fat_msg(sb, KERN_WARNING, "filename was truncated while "
+ "converting.");
}
*op = 0;
return (op - ascii);
}
-static inline int fat_uni_to_x8(struct msdos_sb_info *sbi, const wchar_t *uni,
+static inline int fat_uni_to_x8(struct super_block *sb, const wchar_t *uni,
unsigned char *buf, int size)
{
+ struct msdos_sb_info *sbi = MSDOS_SB(sb);
if (sbi->options.utf8)
return utf16s_to_utf8s(uni, FAT_MAX_UNI_CHARS,
UTF16_HOST_ENDIAN, buf, size);
else
- return uni16_to_x8(buf, uni, size, sbi->options.unicode_xlate,
- sbi->nls_io);
+ return uni16_to_x8(sb, buf, uni, size, sbi->nls_io);
}
static inline int
@@ -419,7 +420,7 @@
/* Compare shortname */
bufuname[last_u] = 0x0000;
- len = fat_uni_to_x8(sbi, bufuname, bufname, sizeof(bufname));
+ len = fat_uni_to_x8(sb, bufuname, bufname, sizeof(bufname));
if (fat_name_match(sbi, name, name_len, bufname, len))
goto found;
@@ -428,7 +429,7 @@
int size = PATH_MAX - FAT_MAX_UNI_SIZE;
/* Compare longname */
- len = fat_uni_to_x8(sbi, unicode, longname, size);
+ len = fat_uni_to_x8(sb, unicode, longname, size);
if (fat_name_match(sbi, name, name_len, longname, len))
goto found;
}
@@ -545,7 +546,7 @@
if (nr_slots) {
void *longname = unicode + FAT_MAX_UNI_CHARS;
int size = PATH_MAX - FAT_MAX_UNI_SIZE;
- int len = fat_uni_to_x8(sbi, unicode, longname, size);
+ int len = fat_uni_to_x8(sb, unicode, longname, size);
fill_name = longname;
fill_len = len;
@@ -621,7 +622,7 @@
if (isvfat) {
bufuname[j] = 0x0000;
- i = fat_uni_to_x8(sbi, bufuname, bufname, sizeof(bufname));
+ i = fat_uni_to_x8(sb, bufuname, bufname, sizeof(bufname));
}
if (nr_slots) {
/* hack for fat_ioctl_filldir() */
@@ -979,6 +980,7 @@
int fat_remove_entries(struct inode *dir, struct fat_slot_info *sinfo)
{
+ struct super_block *sb = dir->i_sb;
struct msdos_dir_entry *de;
struct buffer_head *bh;
int err = 0, nr_slots;
@@ -1013,8 +1015,8 @@
*/
err = __fat_remove_entries(dir, sinfo->slot_off, nr_slots);
if (err) {
- printk(KERN_WARNING
- "FAT: Couldn't remove the long name slots\n");
+ fat_msg(sb, KERN_WARNING,
+ "Couldn't remove the long name slots");
}
}
@@ -1265,7 +1267,7 @@
if (sbi->fat_bits != 32)
goto error;
} else if (MSDOS_I(dir)->i_start == 0) {
- printk(KERN_ERR "FAT: Corrupted directory (i_pos %lld)\n",
+ fat_msg(sb, KERN_ERR, "Corrupted directory (i_pos %lld)",
MSDOS_I(dir)->i_pos);
err = -EIO;
goto error;
diff --git a/fs/fat/fat.h b/fs/fat/fat.h
index f504089..8276cc2 100644
--- a/fs/fat/fat.h
+++ b/fs/fat/fat.h
@@ -319,19 +319,20 @@
struct msdos_dir_entry *de, loff_t i_pos);
extern int fat_sync_inode(struct inode *inode);
extern int fat_fill_super(struct super_block *sb, void *data, int silent,
- const struct inode_operations *fs_dir_inode_ops,
- int isvfat, void (*setup)(struct super_block *));
+ int isvfat, void (*setup)(struct super_block *));
extern int fat_flush_inodes(struct super_block *sb, struct inode *i1,
struct inode *i2);
/* fat/misc.c */
extern void
-__fat_fs_error(struct super_block *s, int report, const char *fmt, ...)
+__fat_fs_error(struct super_block *sb, int report, const char *fmt, ...)
__attribute__ ((format (printf, 3, 4))) __cold;
-#define fat_fs_error(s, fmt, args...) \
- __fat_fs_error(s, 1, fmt , ## args)
-#define fat_fs_error_ratelimit(s, fmt, args...) \
- __fat_fs_error(s, __ratelimit(&MSDOS_SB(s)->ratelimit), fmt , ## args)
+#define fat_fs_error(sb, fmt, args...) \
+ __fat_fs_error(sb, 1, fmt , ## args)
+#define fat_fs_error_ratelimit(sb, fmt, args...) \
+ __fat_fs_error(sb, __ratelimit(&MSDOS_SB(sb)->ratelimit), fmt , ## args)
+void fat_msg(struct super_block *sb, const char *level, const char *fmt, ...)
+ __attribute__ ((format (printf, 3, 4))) __cold;
extern int fat_clusters_flush(struct super_block *sb);
extern int fat_chain_add(struct inode *inode, int new_dclus, int nr_cluster);
extern void fat_time_fat2unix(struct msdos_sb_info *sbi, struct timespec *ts,
diff --git a/fs/fat/fatent.c b/fs/fat/fatent.c
index b47d2c9..2e81ac0 100644
--- a/fs/fat/fatent.c
+++ b/fs/fat/fatent.c
@@ -95,7 +95,7 @@
err_brelse:
brelse(bhs[0]);
err:
- printk(KERN_ERR "FAT: FAT read failed (blocknr %llu)\n", (llu)blocknr);
+ fat_msg(sb, KERN_ERR, "FAT read failed (blocknr %llu)", (llu)blocknr);
return -EIO;
}
@@ -108,7 +108,7 @@
fatent->fat_inode = MSDOS_SB(sb)->fat_inode;
fatent->bhs[0] = sb_bread(sb, blocknr);
if (!fatent->bhs[0]) {
- printk(KERN_ERR "FAT: FAT read failed (blocknr %llu)\n",
+ fat_msg(sb, KERN_ERR, "FAT read failed (blocknr %llu)",
(llu)blocknr);
return -EIO;
}
diff --git a/fs/fat/inode.c b/fs/fat/inode.c
index 8d68690..cb8d839 100644
--- a/fs/fat/inode.c
+++ b/fs/fat/inode.c
@@ -581,7 +581,8 @@
buf->f_bavail = sbi->free_clusters;
buf->f_fsid.val[0] = (u32)id;
buf->f_fsid.val[1] = (u32)(id >> 32);
- buf->f_namelen = sbi->options.isvfat ? FAT_LFN_LEN : 12;
+ buf->f_namelen =
+ (sbi->options.isvfat ? FAT_LFN_LEN : 12) * NLS_MAX_CHARSET_SIZE;
return 0;
}
@@ -619,8 +620,8 @@
bh = sb_bread(sb, i_pos >> sbi->dir_per_block_bits);
if (!bh) {
- printk(KERN_ERR "FAT: unable to read inode block "
- "for updating (i_pos %lld)\n", i_pos);
+ fat_msg(sb, KERN_ERR, "unable to read inode block "
+ "for updating (i_pos %lld)", i_pos);
return -EIO;
}
spin_lock(&sbi->inode_hash_lock);
@@ -976,8 +977,8 @@
{Opt_err, NULL}
};
-static int parse_options(char *options, int is_vfat, int silent, int *debug,
- struct fat_mount_options *opts)
+static int parse_options(struct super_block *sb, char *options, int is_vfat,
+ int silent, int *debug, struct fat_mount_options *opts)
{
char *p;
substring_t args[MAX_OPT_ARGS];
@@ -1168,15 +1169,15 @@
/* obsolete mount options */
case Opt_obsolate:
- printk(KERN_INFO "FAT: \"%s\" option is obsolete, "
- "not supported now\n", p);
+ fat_msg(sb, KERN_INFO, "\"%s\" option is obsolete, "
+ "not supported now", p);
break;
/* unknown option */
default:
if (!silent) {
- printk(KERN_ERR
- "FAT: Unrecognized mount option \"%s\" "
- "or missing value\n", p);
+ fat_msg(sb, KERN_ERR,
+ "Unrecognized mount option \"%s\" "
+ "or missing value", p);
}
return -EINVAL;
}
@@ -1185,7 +1186,7 @@
out:
/* UTF-8 doesn't provide FAT semantics */
if (!strcmp(opts->iocharset, "utf8")) {
- printk(KERN_ERR "FAT: utf8 is not a recommended IO charset"
+ fat_msg(sb, KERN_ERR, "utf8 is not a recommended IO charset"
" for FAT filesystems, filesystem will be "
"case sensitive!\n");
}
@@ -1238,8 +1239,7 @@
/*
* Read the super block of an MS-DOS FS.
*/
-int fat_fill_super(struct super_block *sb, void *data, int silent,
- const struct inode_operations *fs_dir_inode_ops, int isvfat,
+int fat_fill_super(struct super_block *sb, void *data, int silent, int isvfat,
void (*setup)(struct super_block *))
{
struct inode *root_inode = NULL, *fat_inode = NULL;
@@ -1268,11 +1268,10 @@
sb->s_magic = MSDOS_SUPER_MAGIC;
sb->s_op = &fat_sops;
sb->s_export_op = &fat_export_ops;
- sbi->dir_ops = fs_dir_inode_ops;
ratelimit_state_init(&sbi->ratelimit, DEFAULT_RATELIMIT_INTERVAL,
DEFAULT_RATELIMIT_BURST);
- error = parse_options(data, isvfat, silent, &debug, &sbi->options);
+ error = parse_options(sb, data, isvfat, silent, &debug, &sbi->options);
if (error)
goto out_fail;
@@ -1282,20 +1281,20 @@
sb_min_blocksize(sb, 512);
bh = sb_bread(sb, 0);
if (bh == NULL) {
- printk(KERN_ERR "FAT: unable to read boot sector\n");
+ fat_msg(sb, KERN_ERR, "unable to read boot sector");
goto out_fail;
}
b = (struct fat_boot_sector *) bh->b_data;
if (!b->reserved) {
if (!silent)
- printk(KERN_ERR "FAT: bogus number of reserved sectors\n");
+ fat_msg(sb, KERN_ERR, "bogus number of reserved sectors");
brelse(bh);
goto out_invalid;
}
if (!b->fats) {
if (!silent)
- printk(KERN_ERR "FAT: bogus number of FAT structure\n");
+ fat_msg(sb, KERN_ERR, "bogus number of FAT structure");
brelse(bh);
goto out_invalid;
}
@@ -1308,7 +1307,7 @@
media = b->media;
if (!fat_valid_media(media)) {
if (!silent)
- printk(KERN_ERR "FAT: invalid media value (0x%02x)\n",
+ fat_msg(sb, KERN_ERR, "invalid media value (0x%02x)",
media);
brelse(bh);
goto out_invalid;
@@ -1318,7 +1317,7 @@
|| (logical_sector_size < 512)
|| (logical_sector_size > 4096)) {
if (!silent)
- printk(KERN_ERR "FAT: bogus logical sector size %u\n",
+ fat_msg(sb, KERN_ERR, "bogus logical sector size %u",
logical_sector_size);
brelse(bh);
goto out_invalid;
@@ -1326,15 +1325,15 @@
sbi->sec_per_clus = b->sec_per_clus;
if (!is_power_of_2(sbi->sec_per_clus)) {
if (!silent)
- printk(KERN_ERR "FAT: bogus sectors per cluster %u\n",
+ fat_msg(sb, KERN_ERR, "bogus sectors per cluster %u",
sbi->sec_per_clus);
brelse(bh);
goto out_invalid;
}
if (logical_sector_size < sb->s_blocksize) {
- printk(KERN_ERR "FAT: logical sector size too small for device"
- " (logical sector size = %u)\n", logical_sector_size);
+ fat_msg(sb, KERN_ERR, "logical sector size too small for device"
+ " (logical sector size = %u)", logical_sector_size);
brelse(bh);
goto out_fail;
}
@@ -1342,14 +1341,14 @@
brelse(bh);
if (!sb_set_blocksize(sb, logical_sector_size)) {
- printk(KERN_ERR "FAT: unable to set blocksize %u\n",
+ fat_msg(sb, KERN_ERR, "unable to set blocksize %u",
logical_sector_size);
goto out_fail;
}
bh = sb_bread(sb, 0);
if (bh == NULL) {
- printk(KERN_ERR "FAT: unable to read boot sector"
- " (logical sector size = %lu)\n",
+ fat_msg(sb, KERN_ERR, "unable to read boot sector"
+ " (logical sector size = %lu)",
sb->s_blocksize);
goto out_fail;
}
@@ -1385,16 +1384,16 @@
fsinfo_bh = sb_bread(sb, sbi->fsinfo_sector);
if (fsinfo_bh == NULL) {
- printk(KERN_ERR "FAT: bread failed, FSINFO block"
- " (sector = %lu)\n", sbi->fsinfo_sector);
+ fat_msg(sb, KERN_ERR, "bread failed, FSINFO block"
+ " (sector = %lu)", sbi->fsinfo_sector);
brelse(bh);
goto out_fail;
}
fsinfo = (struct fat_boot_fsinfo *)fsinfo_bh->b_data;
if (!IS_FSINFO(fsinfo)) {
- printk(KERN_WARNING "FAT: Invalid FSINFO signature: "
- "0x%08x, 0x%08x (sector = %lu)\n",
+ fat_msg(sb, KERN_WARNING, "Invalid FSINFO signature: "
+ "0x%08x, 0x%08x (sector = %lu)",
le32_to_cpu(fsinfo->signature1),
le32_to_cpu(fsinfo->signature2),
sbi->fsinfo_sector);
@@ -1415,8 +1414,8 @@
sbi->dir_entries = get_unaligned_le16(&b->dir_entries);
if (sbi->dir_entries & (sbi->dir_per_block - 1)) {
if (!silent)
- printk(KERN_ERR "FAT: bogus directroy-entries per block"
- " (%u)\n", sbi->dir_entries);
+ fat_msg(sb, KERN_ERR, "bogus directroy-entries per block"
+ " (%u)", sbi->dir_entries);
brelse(bh);
goto out_invalid;
}
@@ -1438,7 +1437,7 @@
total_clusters = min(total_clusters, fat_clusters - FAT_START_ENT);
if (total_clusters > MAX_FAT(sb)) {
if (!silent)
- printk(KERN_ERR "FAT: count of clusters too big (%u)\n",
+ fat_msg(sb, KERN_ERR, "count of clusters too big (%u)",
total_clusters);
brelse(bh);
goto out_invalid;
@@ -1471,7 +1470,7 @@
sprintf(buf, "cp%d", sbi->options.codepage);
sbi->nls_disk = load_nls(buf);
if (!sbi->nls_disk) {
- printk(KERN_ERR "FAT: codepage %s not found\n", buf);
+ fat_msg(sb, KERN_ERR, "codepage %s not found", buf);
goto out_fail;
}
@@ -1479,7 +1478,7 @@
if (sbi->options.isvfat) {
sbi->nls_io = load_nls(sbi->options.iocharset);
if (!sbi->nls_io) {
- printk(KERN_ERR "FAT: IO charset %s not found\n",
+ fat_msg(sb, KERN_ERR, "IO charset %s not found",
sbi->options.iocharset);
goto out_fail;
}
@@ -1503,7 +1502,7 @@
insert_inode_hash(root_inode);
sb->s_root = d_alloc_root(root_inode);
if (!sb->s_root) {
- printk(KERN_ERR "FAT: get root inode failed\n");
+ fat_msg(sb, KERN_ERR, "get root inode failed");
goto out_fail;
}
@@ -1512,8 +1511,7 @@
out_invalid:
error = -EINVAL;
if (!silent)
- printk(KERN_INFO "VFS: Can't find a valid FAT filesystem"
- " on dev %s.\n", sb->s_id);
+ fat_msg(sb, KERN_INFO, "Can't find a valid FAT filesystem");
out_fail:
if (fat_inode)
diff --git a/fs/fat/misc.c b/fs/fat/misc.c
index 970e682..6d93360 100644
--- a/fs/fat/misc.c
+++ b/fs/fat/misc.c
@@ -20,30 +20,46 @@
* In case the file system is remounted read-only, it can be made writable
* again by remounting it.
*/
-void __fat_fs_error(struct super_block *s, int report, const char *fmt, ...)
+void __fat_fs_error(struct super_block *sb, int report, const char *fmt, ...)
{
- struct fat_mount_options *opts = &MSDOS_SB(s)->options;
+ struct fat_mount_options *opts = &MSDOS_SB(sb)->options;
va_list args;
+ struct va_format vaf;
if (report) {
- printk(KERN_ERR "FAT: Filesystem error (dev %s)\n", s->s_id);
-
- printk(KERN_ERR " ");
va_start(args, fmt);
- vprintk(fmt, args);
+ vaf.fmt = fmt;
+ vaf.va = &args;
+ printk(KERN_ERR "FAT-fs (%s): error, %pV\n", sb->s_id, &vaf);
va_end(args);
- printk("\n");
}
if (opts->errors == FAT_ERRORS_PANIC)
- panic("FAT: fs panic from previous error\n");
- else if (opts->errors == FAT_ERRORS_RO && !(s->s_flags & MS_RDONLY)) {
- s->s_flags |= MS_RDONLY;
- printk(KERN_ERR "FAT: Filesystem has been set read-only\n");
+ panic("FAT-fs (%s): fs panic from previous error\n", sb->s_id);
+ else if (opts->errors == FAT_ERRORS_RO && !(sb->s_flags & MS_RDONLY)) {
+ sb->s_flags |= MS_RDONLY;
+ printk(KERN_ERR "FAT-fs (%s): Filesystem has been "
+ "set read-only\n", sb->s_id);
}
}
EXPORT_SYMBOL_GPL(__fat_fs_error);
+/**
+ * fat_msg() - print preformated FAT specific messages. Every thing what is
+ * not fat_fs_error() should be fat_msg().
+ */
+void fat_msg(struct super_block *sb, const char *level, const char *fmt, ...)
+{
+ struct va_format vaf;
+ va_list args;
+
+ va_start(args, fmt);
+ vaf.fmt = fmt;
+ vaf.va = &args;
+ printk("%sFAT-fs (%s): %pV\n", level, sb->s_id, &vaf);
+ va_end(args);
+}
+
/* Flushes the number of free clusters on FAT32 */
/* XXX: Need to write one per FSINFO block. Currently only writes 1 */
int fat_clusters_flush(struct super_block *sb)
@@ -57,15 +73,15 @@
bh = sb_bread(sb, sbi->fsinfo_sector);
if (bh == NULL) {
- printk(KERN_ERR "FAT: bread failed in fat_clusters_flush\n");
+ fat_msg(sb, KERN_ERR, "bread failed in fat_clusters_flush");
return -EIO;
}
fsinfo = (struct fat_boot_fsinfo *)bh->b_data;
/* Sanity check */
if (!IS_FSINFO(fsinfo)) {
- printk(KERN_ERR "FAT: Invalid FSINFO signature: "
- "0x%08x, 0x%08x (sector = %lu)\n",
+ fat_msg(sb, KERN_ERR, "Invalid FSINFO signature: "
+ "0x%08x, 0x%08x (sector = %lu)",
le32_to_cpu(fsinfo->signature1),
le32_to_cpu(fsinfo->signature2),
sbi->fsinfo_sector);
diff --git a/fs/fat/namei_msdos.c b/fs/fat/namei_msdos.c
index 7114990..3b222da 100644
--- a/fs/fat/namei_msdos.c
+++ b/fs/fat/namei_msdos.c
@@ -659,14 +659,14 @@
static void setup(struct super_block *sb)
{
+ MSDOS_SB(sb)->dir_ops = &msdos_dir_inode_operations;
sb->s_d_op = &msdos_dentry_operations;
sb->s_flags |= MS_NOATIME;
}
static int msdos_fill_super(struct super_block *sb, void *data, int silent)
{
- return fat_fill_super(sb, data, silent, &msdos_dir_inode_operations,
- 0, setup);
+ return fat_fill_super(sb, data, silent, 0, setup);
}
static struct dentry *msdos_mount(struct file_system_type *fs_type,
diff --git a/fs/fat/namei_vfat.c b/fs/fat/namei_vfat.c
index adae3fb..20b4ea5 100644
--- a/fs/fat/namei_vfat.c
+++ b/fs/fat/namei_vfat.c
@@ -1065,6 +1065,7 @@
static void setup(struct super_block *sb)
{
+ MSDOS_SB(sb)->dir_ops = &vfat_dir_inode_operations;
if (MSDOS_SB(sb)->options.name_check != 's')
sb->s_d_op = &vfat_ci_dentry_ops;
else
@@ -1073,8 +1074,7 @@
static int vfat_fill_super(struct super_block *sb, void *data, int silent)
{
- return fat_fill_super(sb, data, silent, &vfat_dir_inode_operations,
- 1, setup);
+ return fat_fill_super(sb, data, silent, 1, setup);
}
static struct dentry *vfat_mount(struct file_system_type *fs_type,
diff --git a/fs/fscache/operation.c b/fs/fscache/operation.c
index 48a18f1..30afdfa 100644
--- a/fs/fscache/operation.c
+++ b/fs/fscache/operation.c
@@ -33,8 +33,6 @@
_enter("{OBJ%x OP%x,%u}",
op->object->debug_id, op->debug_id, atomic_read(&op->usage));
- fscache_set_op_state(op, "EnQ");
-
ASSERT(list_empty(&op->pend_link));
ASSERT(op->processor != NULL);
ASSERTCMP(op->object->state, >=, FSCACHE_OBJECT_AVAILABLE);
@@ -66,8 +64,6 @@
static void fscache_run_op(struct fscache_object *object,
struct fscache_operation *op)
{
- fscache_set_op_state(op, "Run");
-
object->n_in_progress++;
if (test_and_clear_bit(FSCACHE_OP_WAITING, &op->flags))
wake_up_bit(&op->flags, FSCACHE_OP_WAITING);
@@ -88,8 +84,6 @@
_enter("{OBJ%x OP%x},", object->debug_id, op->debug_id);
- fscache_set_op_state(op, "SubmitX");
-
spin_lock(&object->lock);
ASSERTCMP(object->n_ops, >=, object->n_in_progress);
ASSERTCMP(object->n_ops, >=, object->n_exclusive);
@@ -194,8 +188,6 @@
ASSERTCMP(atomic_read(&op->usage), >, 0);
- fscache_set_op_state(op, "Submit");
-
spin_lock(&object->lock);
ASSERTCMP(object->n_ops, >=, object->n_in_progress);
ASSERTCMP(object->n_ops, >=, object->n_exclusive);
@@ -335,8 +327,6 @@
if (!atomic_dec_and_test(&op->usage))
return;
- fscache_set_op_state(op, "Put");
-
_debug("PUT OP");
if (test_and_set_bit(FSCACHE_OP_DEAD, &op->flags))
BUG();
diff --git a/fs/fscache/page.c b/fs/fscache/page.c
index 41c441c..a2a5d19 100644
--- a/fs/fscache/page.c
+++ b/fs/fscache/page.c
@@ -155,11 +155,9 @@
fscache_stat(&fscache_n_attr_changed_calls);
if (fscache_object_is_active(object)) {
- fscache_set_op_state(op, "CallFS");
fscache_stat(&fscache_n_cop_attr_changed);
ret = object->cache->ops->attr_changed(object);
fscache_stat_d(&fscache_n_cop_attr_changed);
- fscache_set_op_state(op, "Done");
if (ret < 0)
fscache_abort_object(object);
}
@@ -190,7 +188,6 @@
fscache_operation_init(op, fscache_attr_changed_op, NULL);
op->flags = FSCACHE_OP_ASYNC | (1 << FSCACHE_OP_EXCLUSIVE);
- fscache_set_op_name(op, "Attr");
spin_lock(&cookie->lock);
@@ -257,7 +254,6 @@
op->context = context;
op->start_time = jiffies;
INIT_LIST_HEAD(&op->to_do);
- fscache_set_op_name(&op->op, "Retr");
return op;
}
@@ -368,7 +364,6 @@
_leave(" = -ENOMEM");
return -ENOMEM;
}
- fscache_set_op_name(&op->op, "RetrRA1");
spin_lock(&cookie->lock);
@@ -487,7 +482,6 @@
op = fscache_alloc_retrieval(mapping, end_io_func, context);
if (!op)
return -ENOMEM;
- fscache_set_op_name(&op->op, "RetrRAN");
spin_lock(&cookie->lock);
@@ -589,7 +583,6 @@
op = fscache_alloc_retrieval(page->mapping, NULL, NULL);
if (!op)
return -ENOMEM;
- fscache_set_op_name(&op->op, "RetrAL1");
spin_lock(&cookie->lock);
@@ -662,8 +655,6 @@
_enter("{OP%x,%d}", op->op.debug_id, atomic_read(&op->op.usage));
- fscache_set_op_state(&op->op, "GetPage");
-
spin_lock(&object->lock);
cookie = object->cookie;
@@ -698,15 +689,12 @@
spin_unlock(&cookie->stores_lock);
spin_unlock(&object->lock);
- fscache_set_op_state(&op->op, "Store");
fscache_stat(&fscache_n_store_pages);
fscache_stat(&fscache_n_cop_write_page);
ret = object->cache->ops->write_page(op, page);
fscache_stat_d(&fscache_n_cop_write_page);
- fscache_set_op_state(&op->op, "EndWrite");
fscache_end_page_write(object, page);
if (ret < 0) {
- fscache_set_op_state(&op->op, "Abort");
fscache_abort_object(object);
} else {
fscache_enqueue_operation(&op->op);
@@ -778,7 +766,6 @@
fscache_operation_init(&op->op, fscache_write_op,
fscache_release_write_op);
op->op.flags = FSCACHE_OP_ASYNC | (1 << FSCACHE_OP_WAITING);
- fscache_set_op_name(&op->op, "Write1");
ret = radix_tree_preload(gfp & ~__GFP_HIGHMEM);
if (ret < 0)
diff --git a/fs/gfs2/glock.c b/fs/gfs2/glock.c
index a2a6abb..2792a79 100644
--- a/fs/gfs2/glock.c
+++ b/fs/gfs2/glock.c
@@ -1346,11 +1346,14 @@
}
-static int gfs2_shrink_glock_memory(struct shrinker *shrink, int nr, gfp_t gfp_mask)
+static int gfs2_shrink_glock_memory(struct shrinker *shrink,
+ struct shrink_control *sc)
{
struct gfs2_glock *gl;
int may_demote;
int nr_skipped = 0;
+ int nr = sc->nr_to_scan;
+ gfp_t gfp_mask = sc->gfp_mask;
LIST_HEAD(skipped);
if (nr == 0)
diff --git a/fs/gfs2/quota.c b/fs/gfs2/quota.c
index e23d986..42e8d23 100644
--- a/fs/gfs2/quota.c
+++ b/fs/gfs2/quota.c
@@ -38,6 +38,7 @@
#include <linux/sched.h>
#include <linux/slab.h>
+#include <linux/mm.h>
#include <linux/spinlock.h>
#include <linux/completion.h>
#include <linux/buffer_head.h>
@@ -77,19 +78,20 @@
static atomic_t qd_lru_count = ATOMIC_INIT(0);
static DEFINE_SPINLOCK(qd_lru_lock);
-int gfs2_shrink_qd_memory(struct shrinker *shrink, int nr, gfp_t gfp_mask)
+int gfs2_shrink_qd_memory(struct shrinker *shrink, struct shrink_control *sc)
{
struct gfs2_quota_data *qd;
struct gfs2_sbd *sdp;
+ int nr_to_scan = sc->nr_to_scan;
- if (nr == 0)
+ if (nr_to_scan == 0)
goto out;
- if (!(gfp_mask & __GFP_FS))
+ if (!(sc->gfp_mask & __GFP_FS))
return -1;
spin_lock(&qd_lru_lock);
- while (nr && !list_empty(&qd_lru_list)) {
+ while (nr_to_scan && !list_empty(&qd_lru_list)) {
qd = list_entry(qd_lru_list.next,
struct gfs2_quota_data, qd_reclaim);
sdp = qd->qd_gl->gl_sbd;
@@ -110,7 +112,7 @@
spin_unlock(&qd_lru_lock);
kmem_cache_free(gfs2_quotad_cachep, qd);
spin_lock(&qd_lru_lock);
- nr--;
+ nr_to_scan--;
}
spin_unlock(&qd_lru_lock);
diff --git a/fs/gfs2/quota.h b/fs/gfs2/quota.h
index e7d236c..90bf1c3 100644
--- a/fs/gfs2/quota.h
+++ b/fs/gfs2/quota.h
@@ -12,6 +12,7 @@
struct gfs2_inode;
struct gfs2_sbd;
+struct shrink_control;
#define NO_QUOTA_CHANGE ((u32)-1)
@@ -51,7 +52,8 @@
return ret;
}
-extern int gfs2_shrink_qd_memory(struct shrinker *shrink, int nr, gfp_t gfp_mask);
+extern int gfs2_shrink_qd_memory(struct shrinker *shrink,
+ struct shrink_control *sc);
extern const struct quotactl_ops gfs2_quotactl_ops;
#endif /* __QUOTA_DOT_H__ */
diff --git a/fs/hugetlbfs/inode.c b/fs/hugetlbfs/inode.c
index b9eeb1c..e7a0357 100644
--- a/fs/hugetlbfs/inode.c
+++ b/fs/hugetlbfs/inode.c
@@ -412,10 +412,10 @@
pgoff = offset >> PAGE_SHIFT;
i_size_write(inode, offset);
- spin_lock(&mapping->i_mmap_lock);
+ mutex_lock(&mapping->i_mmap_mutex);
if (!prio_tree_empty(&mapping->i_mmap))
hugetlb_vmtruncate_list(&mapping->i_mmap, pgoff);
- spin_unlock(&mapping->i_mmap_lock);
+ mutex_unlock(&mapping->i_mmap_mutex);
truncate_hugepages(inode, offset);
return 0;
}
diff --git a/fs/inode.c b/fs/inode.c
index 05f4fa5..990d284 100644
--- a/fs/inode.c
+++ b/fs/inode.c
@@ -326,12 +326,11 @@
memset(mapping, 0, sizeof(*mapping));
INIT_RADIX_TREE(&mapping->page_tree, GFP_ATOMIC);
spin_lock_init(&mapping->tree_lock);
- spin_lock_init(&mapping->i_mmap_lock);
+ mutex_init(&mapping->i_mmap_mutex);
INIT_LIST_HEAD(&mapping->private_list);
spin_lock_init(&mapping->private_lock);
INIT_RAW_PRIO_TREE_ROOT(&mapping->i_mmap);
INIT_LIST_HEAD(&mapping->i_mmap_nonlinear);
- mutex_init(&mapping->unmap_mutex);
}
EXPORT_SYMBOL(address_space_init_once);
@@ -752,8 +751,12 @@
* This function is passed the number of inodes to scan, and it returns the
* total number of remaining possibly-reclaimable inodes.
*/
-static int shrink_icache_memory(struct shrinker *shrink, int nr, gfp_t gfp_mask)
+static int shrink_icache_memory(struct shrinker *shrink,
+ struct shrink_control *sc)
{
+ int nr = sc->nr_to_scan;
+ gfp_t gfp_mask = sc->gfp_mask;
+
if (nr) {
/*
* Nasty deadlock avoidance. We may hold various FS locks,
diff --git a/fs/jbd/commit.c b/fs/jbd/commit.c
index 69b1804..72ffa97 100644
--- a/fs/jbd/commit.c
+++ b/fs/jbd/commit.c
@@ -302,12 +302,6 @@
* all outstanding updates to complete.
*/
-#ifdef COMMIT_STATS
- spin_lock(&journal->j_list_lock);
- summarise_journal_usage(journal);
- spin_unlock(&journal->j_list_lock);
-#endif
-
/* Do we need to erase the effects of a prior journal_flush? */
if (journal->j_flags & JFS_FLUSHED) {
jbd_debug(3, "super block updated\n");
@@ -722,8 +716,13 @@
required. */
JBUFFER_TRACE(jh, "file as BJ_Forget");
journal_file_buffer(jh, commit_transaction, BJ_Forget);
- /* Wake up any transactions which were waiting for this
- IO to complete */
+ /*
+ * Wake up any transactions which were waiting for this
+ * IO to complete. The barrier must be here so that changes
+ * by journal_file_buffer() take effect before wake_up_bit()
+ * does the waitqueue check.
+ */
+ smp_mb();
wake_up_bit(&bh->b_state, BH_Unshadow);
JBUFFER_TRACE(jh, "brelse shadowed buffer");
__brelse(bh);
diff --git a/fs/jbd/journal.c b/fs/jbd/journal.c
index b3713af..e2d4285 100644
--- a/fs/jbd/journal.c
+++ b/fs/jbd/journal.c
@@ -437,9 +437,12 @@
int __log_start_commit(journal_t *journal, tid_t target)
{
/*
- * Are we already doing a recent enough commit?
+ * The only transaction we can possibly wait upon is the
+ * currently running transaction (if it exists). Otherwise,
+ * the target tid must be an old one.
*/
- if (!tid_geq(journal->j_commit_request, target)) {
+ if (journal->j_running_transaction &&
+ journal->j_running_transaction->t_tid == target) {
/*
* We want a new commit: OK, mark the request and wakeup the
* commit thread. We do _not_ do the commit ourselves.
@@ -451,7 +454,14 @@
journal->j_commit_sequence);
wake_up(&journal->j_wait_commit);
return 1;
- }
+ } else if (!tid_geq(journal->j_commit_request, target))
+ /* This should never happen, but if it does, preserve
+ the evidence before kjournald goes into a loop and
+ increments j_commit_sequence beyond all recognition. */
+ WARN_ONCE(1, "jbd: bad log_start_commit: %u %u %u %u\n",
+ journal->j_commit_request, journal->j_commit_sequence,
+ target, journal->j_running_transaction ?
+ journal->j_running_transaction->t_tid : 0);
return 0;
}
diff --git a/fs/jbd/transaction.c b/fs/jbd/transaction.c
index 60d2319..f7ee81a 100644
--- a/fs/jbd/transaction.c
+++ b/fs/jbd/transaction.c
@@ -266,7 +266,8 @@
* This function is visible to journal users (like ext3fs), so is not
* called with the journal already locked.
*
- * Return a pointer to a newly allocated handle, or NULL on failure
+ * Return a pointer to a newly allocated handle, or an ERR_PTR() value
+ * on failure.
*/
handle_t *journal_start(journal_t *journal, int nblocks)
{
diff --git a/fs/jbd2/commit.c b/fs/jbd2/commit.c
index 6e28000..29148a8 100644
--- a/fs/jbd2/commit.c
+++ b/fs/jbd2/commit.c
@@ -338,12 +338,6 @@
* all outstanding updates to complete.
*/
-#ifdef COMMIT_STATS
- spin_lock(&journal->j_list_lock);
- summarise_journal_usage(journal);
- spin_unlock(&journal->j_list_lock);
-#endif
-
/* Do we need to erase the effects of a prior jbd2_journal_flush? */
if (journal->j_flags & JBD2_FLUSHED) {
jbd_debug(3, "super block updated\n");
diff --git a/fs/mbcache.c b/fs/mbcache.c
index 2f174be..8c32ef3 100644
--- a/fs/mbcache.c
+++ b/fs/mbcache.c
@@ -90,7 +90,8 @@
* What the mbcache registers as to get shrunk dynamically.
*/
-static int mb_cache_shrink_fn(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask);
+static int mb_cache_shrink_fn(struct shrinker *shrink,
+ struct shrink_control *sc);
static struct shrinker mb_cache_shrinker = {
.shrink = mb_cache_shrink_fn,
@@ -156,18 +157,19 @@
* gets low.
*
* @shrink: (ignored)
- * @nr_to_scan: Number of objects to scan
- * @gfp_mask: (ignored)
+ * @sc: shrink_control passed from reclaim
*
* Returns the number of objects which are present in the cache.
*/
static int
-mb_cache_shrink_fn(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask)
+mb_cache_shrink_fn(struct shrinker *shrink, struct shrink_control *sc)
{
LIST_HEAD(free_list);
struct mb_cache *cache;
struct mb_cache_entry *entry, *tmp;
int count = 0;
+ int nr_to_scan = sc->nr_to_scan;
+ gfp_t gfp_mask = sc->gfp_mask;
mb_debug("trying to free %d entries", nr_to_scan);
spin_lock(&mb_cache_spinlock);
diff --git a/fs/ncpfs/inode.c b/fs/ncpfs/inode.c
index 0250e4c..202f370 100644
--- a/fs/ncpfs/inode.c
+++ b/fs/ncpfs/inode.c
@@ -461,7 +461,7 @@
#endif
struct ncp_entry_info finfo;
- data.wdog_pid = NULL;
+ memset(&data, 0, sizeof(data));
server = kzalloc(sizeof(struct ncp_server), GFP_KERNEL);
if (!server)
return -ENOMEM;
@@ -496,7 +496,6 @@
struct ncp_mount_data_v4* md = (struct ncp_mount_data_v4*)raw_data;
data.flags = md->flags;
- data.int_flags = 0;
data.mounted_uid = md->mounted_uid;
data.wdog_pid = find_get_pid(md->wdog_pid);
data.ncp_fd = md->ncp_fd;
@@ -507,7 +506,6 @@
data.file_mode = md->file_mode;
data.dir_mode = md->dir_mode;
data.info_fd = -1;
- data.mounted_vol[0] = 0;
}
break;
default:
diff --git a/fs/nfs/dir.c b/fs/nfs/dir.c
index 7237672..424e477 100644
--- a/fs/nfs/dir.c
+++ b/fs/nfs/dir.c
@@ -2042,11 +2042,14 @@
}
}
-int nfs_access_cache_shrinker(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask)
+int nfs_access_cache_shrinker(struct shrinker *shrink,
+ struct shrink_control *sc)
{
LIST_HEAD(head);
struct nfs_inode *nfsi, *next;
struct nfs_access_entry *cache;
+ int nr_to_scan = sc->nr_to_scan;
+ gfp_t gfp_mask = sc->gfp_mask;
if ((gfp_mask & GFP_KERNEL) != GFP_KERNEL)
return (nr_to_scan == 0) ? 0 : -1;
diff --git a/fs/nfs/internal.h b/fs/nfs/internal.h
index ce118ce..2df6ca7 100644
--- a/fs/nfs/internal.h
+++ b/fs/nfs/internal.h
@@ -234,7 +234,7 @@
/* dir.c */
extern int nfs_access_cache_shrinker(struct shrinker *shrink,
- int nr_to_scan, gfp_t gfp_mask);
+ struct shrink_control *sc);
/* inode.c */
extern struct workqueue_struct *nfsiod_workqueue;
diff --git a/fs/partitions/check.c b/fs/partitions/check.c
index d545e97..8ed4d34 100644
--- a/fs/partitions/check.c
+++ b/fs/partitions/check.c
@@ -255,7 +255,11 @@
struct device_attribute *attr, char *buf)
{
struct hd_struct *p = dev_to_part(dev);
- return sprintf(buf, "%u\n", p->discard_alignment);
+ struct gendisk *disk = dev_to_disk(dev);
+
+ return sprintf(buf, "%u\n",
+ queue_limit_discard_alignment(&disk->queue->limits,
+ p->start_sect));
}
ssize_t part_stat_show(struct device *dev,
@@ -449,8 +453,6 @@
p->start_sect = start;
p->alignment_offset =
queue_limit_alignment_offset(&disk->queue->limits, start);
- p->discard_alignment =
- queue_limit_discard_alignment(&disk->queue->limits, start);
p->nr_sects = len;
p->partno = partno;
p->policy = get_disk_ro(disk);
diff --git a/fs/proc/internal.h b/fs/proc/internal.h
index c03e8d3..3763b43 100644
--- a/fs/proc/internal.h
+++ b/fs/proc/internal.h
@@ -61,6 +61,14 @@
extern const struct file_operations proc_net_operations;
extern const struct inode_operations proc_net_inode_operations;
+struct proc_maps_private {
+ struct pid *pid;
+ struct task_struct *task;
+#ifdef CONFIG_MMU
+ struct vm_area_struct *tail_vma;
+#endif
+};
+
void proc_init_inodecache(void);
static inline struct pid *proc_pid(struct inode *inode)
diff --git a/fs/proc/task_mmu.c b/fs/proc/task_mmu.c
index 318d865..2c9db29 100644
--- a/fs/proc/task_mmu.c
+++ b/fs/proc/task_mmu.c
@@ -858,7 +858,192 @@
#endif /* CONFIG_PROC_PAGE_MONITOR */
#ifdef CONFIG_NUMA
-extern int show_numa_map(struct seq_file *m, void *v);
+
+struct numa_maps {
+ struct vm_area_struct *vma;
+ unsigned long pages;
+ unsigned long anon;
+ unsigned long active;
+ unsigned long writeback;
+ unsigned long mapcount_max;
+ unsigned long dirty;
+ unsigned long swapcache;
+ unsigned long node[MAX_NUMNODES];
+};
+
+struct numa_maps_private {
+ struct proc_maps_private proc_maps;
+ struct numa_maps md;
+};
+
+static void gather_stats(struct page *page, struct numa_maps *md, int pte_dirty)
+{
+ int count = page_mapcount(page);
+
+ md->pages++;
+ if (pte_dirty || PageDirty(page))
+ md->dirty++;
+
+ if (PageSwapCache(page))
+ md->swapcache++;
+
+ if (PageActive(page) || PageUnevictable(page))
+ md->active++;
+
+ if (PageWriteback(page))
+ md->writeback++;
+
+ if (PageAnon(page))
+ md->anon++;
+
+ if (count > md->mapcount_max)
+ md->mapcount_max = count;
+
+ md->node[page_to_nid(page)]++;
+}
+
+static int gather_pte_stats(pmd_t *pmd, unsigned long addr,
+ unsigned long end, struct mm_walk *walk)
+{
+ struct numa_maps *md;
+ spinlock_t *ptl;
+ pte_t *orig_pte;
+ pte_t *pte;
+
+ md = walk->private;
+ orig_pte = pte = pte_offset_map_lock(walk->mm, pmd, addr, &ptl);
+ do {
+ struct page *page;
+ int nid;
+
+ if (!pte_present(*pte))
+ continue;
+
+ page = vm_normal_page(md->vma, addr, *pte);
+ if (!page)
+ continue;
+
+ if (PageReserved(page))
+ continue;
+
+ nid = page_to_nid(page);
+ if (!node_isset(nid, node_states[N_HIGH_MEMORY]))
+ continue;
+
+ gather_stats(page, md, pte_dirty(*pte));
+
+ } while (pte++, addr += PAGE_SIZE, addr != end);
+ pte_unmap_unlock(orig_pte, ptl);
+ return 0;
+}
+#ifdef CONFIG_HUGETLB_PAGE
+static int gather_hugetbl_stats(pte_t *pte, unsigned long hmask,
+ unsigned long addr, unsigned long end, struct mm_walk *walk)
+{
+ struct numa_maps *md;
+ struct page *page;
+
+ if (pte_none(*pte))
+ return 0;
+
+ page = pte_page(*pte);
+ if (!page)
+ return 0;
+
+ md = walk->private;
+ gather_stats(page, md, pte_dirty(*pte));
+ return 0;
+}
+
+#else
+static int gather_hugetbl_stats(pte_t *pte, unsigned long hmask,
+ unsigned long addr, unsigned long end, struct mm_walk *walk)
+{
+ return 0;
+}
+#endif
+
+/*
+ * Display pages allocated per node and memory policy via /proc.
+ */
+static int show_numa_map(struct seq_file *m, void *v)
+{
+ struct numa_maps_private *numa_priv = m->private;
+ struct proc_maps_private *proc_priv = &numa_priv->proc_maps;
+ struct vm_area_struct *vma = v;
+ struct numa_maps *md = &numa_priv->md;
+ struct file *file = vma->vm_file;
+ struct mm_struct *mm = vma->vm_mm;
+ struct mm_walk walk = {};
+ struct mempolicy *pol;
+ int n;
+ char buffer[50];
+
+ if (!mm)
+ return 0;
+
+ /* Ensure we start with an empty set of numa_maps statistics. */
+ memset(md, 0, sizeof(*md));
+
+ md->vma = vma;
+
+ walk.hugetlb_entry = gather_hugetbl_stats;
+ walk.pmd_entry = gather_pte_stats;
+ walk.private = md;
+ walk.mm = mm;
+
+ pol = get_vma_policy(proc_priv->task, vma, vma->vm_start);
+ mpol_to_str(buffer, sizeof(buffer), pol, 0);
+ mpol_cond_put(pol);
+
+ seq_printf(m, "%08lx %s", vma->vm_start, buffer);
+
+ if (file) {
+ seq_printf(m, " file=");
+ seq_path(m, &file->f_path, "\n\t= ");
+ } else if (vma->vm_start <= mm->brk && vma->vm_end >= mm->start_brk) {
+ seq_printf(m, " heap");
+ } else if (vma->vm_start <= mm->start_stack &&
+ vma->vm_end >= mm->start_stack) {
+ seq_printf(m, " stack");
+ }
+
+ walk_page_range(vma->vm_start, vma->vm_end, &walk);
+
+ if (!md->pages)
+ goto out;
+
+ if (md->anon)
+ seq_printf(m, " anon=%lu", md->anon);
+
+ if (md->dirty)
+ seq_printf(m, " dirty=%lu", md->dirty);
+
+ if (md->pages != md->anon && md->pages != md->dirty)
+ seq_printf(m, " mapped=%lu", md->pages);
+
+ if (md->mapcount_max > 1)
+ seq_printf(m, " mapmax=%lu", md->mapcount_max);
+
+ if (md->swapcache)
+ seq_printf(m, " swapcache=%lu", md->swapcache);
+
+ if (md->active < md->pages && !is_vm_hugetlb_page(vma))
+ seq_printf(m, " active=%lu", md->active);
+
+ if (md->writeback)
+ seq_printf(m, " writeback=%lu", md->writeback);
+
+ for_each_node_state(n, N_HIGH_MEMORY)
+ if (md->node[n])
+ seq_printf(m, " N%d=%lu", n, md->node[n]);
+out:
+ seq_putc(m, '\n');
+
+ if (m->count < m->size)
+ m->version = (vma != proc_priv->tail_vma) ? vma->vm_start : 0;
+ return 0;
+}
static const struct seq_operations proc_pid_numa_maps_op = {
.start = m_start,
@@ -869,7 +1054,20 @@
static int numa_maps_open(struct inode *inode, struct file *file)
{
- return do_maps_open(inode, file, &proc_pid_numa_maps_op);
+ struct numa_maps_private *priv;
+ int ret = -ENOMEM;
+ priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+ if (priv) {
+ priv->proc_maps.pid = proc_pid(inode);
+ ret = seq_open(file, &proc_pid_numa_maps_op);
+ if (!ret) {
+ struct seq_file *m = file->private_data;
+ m->private = priv;
+ } else {
+ kfree(priv);
+ }
+ }
+ return ret;
}
const struct file_operations proc_numa_maps_operations = {
@@ -878,4 +1076,4 @@
.llseek = seq_lseek,
.release = seq_release_private,
};
-#endif
+#endif /* CONFIG_NUMA */
diff --git a/fs/quota/dquot.c b/fs/quota/dquot.c
index d3c032f..5b572c8 100644
--- a/fs/quota/dquot.c
+++ b/fs/quota/dquot.c
@@ -691,8 +691,11 @@
* This is called from kswapd when we think we need some
* more memory
*/
-static int shrink_dqcache_memory(struct shrinker *shrink, int nr, gfp_t gfp_mask)
+static int shrink_dqcache_memory(struct shrinker *shrink,
+ struct shrink_control *sc)
{
+ int nr = sc->nr_to_scan;
+
if (nr) {
spin_lock(&dq_list_lock);
prune_dqcache(nr);
diff --git a/fs/splice.c b/fs/splice.c
index 50a5d978..aa866d3 100644
--- a/fs/splice.c
+++ b/fs/splice.c
@@ -162,6 +162,14 @@
.get = generic_pipe_buf_get,
};
+static void wakeup_pipe_readers(struct pipe_inode_info *pipe)
+{
+ smp_mb();
+ if (waitqueue_active(&pipe->wait))
+ wake_up_interruptible(&pipe->wait);
+ kill_fasync(&pipe->fasync_readers, SIGIO, POLL_IN);
+}
+
/**
* splice_to_pipe - fill passed data into a pipe
* @pipe: pipe to fill
@@ -247,12 +255,8 @@
pipe_unlock(pipe);
- if (do_wakeup) {
- smp_mb();
- if (waitqueue_active(&pipe->wait))
- wake_up_interruptible(&pipe->wait);
- kill_fasync(&pipe->fasync_readers, SIGIO, POLL_IN);
- }
+ if (do_wakeup)
+ wakeup_pipe_readers(pipe);
while (page_nr < spd_pages)
spd->spd_release(spd, page_nr++);
@@ -1892,12 +1896,9 @@
/*
* If we put data in the output pipe, wakeup any potential readers.
*/
- if (ret > 0) {
- smp_mb();
- if (waitqueue_active(&opipe->wait))
- wake_up_interruptible(&opipe->wait);
- kill_fasync(&opipe->fasync_readers, SIGIO, POLL_IN);
- }
+ if (ret > 0)
+ wakeup_pipe_readers(opipe);
+
if (input_wakeup)
wakeup_pipe_writers(ipipe);
@@ -1976,12 +1977,8 @@
/*
* If we put data in the output pipe, wakeup any potential readers.
*/
- if (ret > 0) {
- smp_mb();
- if (waitqueue_active(&opipe->wait))
- wake_up_interruptible(&opipe->wait);
- kill_fasync(&opipe->fasync_readers, SIGIO, POLL_IN);
- }
+ if (ret > 0)
+ wakeup_pipe_readers(opipe);
return ret;
}
diff --git a/fs/timerfd.c b/fs/timerfd.c
index 8c4fc14..f67acbd 100644
--- a/fs/timerfd.c
+++ b/fs/timerfd.c
@@ -22,16 +22,24 @@
#include <linux/anon_inodes.h>
#include <linux/timerfd.h>
#include <linux/syscalls.h>
+#include <linux/rcupdate.h>
struct timerfd_ctx {
struct hrtimer tmr;
ktime_t tintv;
+ ktime_t moffs;
wait_queue_head_t wqh;
u64 ticks;
int expired;
int clockid;
+ struct rcu_head rcu;
+ struct list_head clist;
+ bool might_cancel;
};
+static LIST_HEAD(cancel_list);
+static DEFINE_SPINLOCK(cancel_lock);
+
/*
* This gets called when the timer event triggers. We set the "expired"
* flag, but we do not re-arm the timer (in case it's necessary,
@@ -51,6 +59,63 @@
return HRTIMER_NORESTART;
}
+/*
+ * Called when the clock was set to cancel the timers in the cancel
+ * list.
+ */
+void timerfd_clock_was_set(void)
+{
+ ktime_t moffs = ktime_get_monotonic_offset();
+ struct timerfd_ctx *ctx;
+ unsigned long flags;
+
+ rcu_read_lock();
+ list_for_each_entry_rcu(ctx, &cancel_list, clist) {
+ if (!ctx->might_cancel)
+ continue;
+ spin_lock_irqsave(&ctx->wqh.lock, flags);
+ if (ctx->moffs.tv64 != moffs.tv64) {
+ ctx->moffs.tv64 = KTIME_MAX;
+ wake_up_locked(&ctx->wqh);
+ }
+ spin_unlock_irqrestore(&ctx->wqh.lock, flags);
+ }
+ rcu_read_unlock();
+}
+
+static void timerfd_remove_cancel(struct timerfd_ctx *ctx)
+{
+ if (ctx->might_cancel) {
+ ctx->might_cancel = false;
+ spin_lock(&cancel_lock);
+ list_del_rcu(&ctx->clist);
+ spin_unlock(&cancel_lock);
+ }
+}
+
+static bool timerfd_canceled(struct timerfd_ctx *ctx)
+{
+ if (!ctx->might_cancel || ctx->moffs.tv64 != KTIME_MAX)
+ return false;
+ ctx->moffs = ktime_get_monotonic_offset();
+ return true;
+}
+
+static void timerfd_setup_cancel(struct timerfd_ctx *ctx, int flags)
+{
+ if (ctx->clockid == CLOCK_REALTIME && (flags & TFD_TIMER_ABSTIME) &&
+ (flags & TFD_TIMER_CANCEL_ON_SET)) {
+ if (!ctx->might_cancel) {
+ ctx->might_cancel = true;
+ spin_lock(&cancel_lock);
+ list_add_rcu(&ctx->clist, &cancel_list);
+ spin_unlock(&cancel_lock);
+ }
+ } else if (ctx->might_cancel) {
+ timerfd_remove_cancel(ctx);
+ }
+}
+
static ktime_t timerfd_get_remaining(struct timerfd_ctx *ctx)
{
ktime_t remaining;
@@ -59,11 +124,12 @@
return remaining.tv64 < 0 ? ktime_set(0, 0): remaining;
}
-static void timerfd_setup(struct timerfd_ctx *ctx, int flags,
- const struct itimerspec *ktmr)
+static int timerfd_setup(struct timerfd_ctx *ctx, int flags,
+ const struct itimerspec *ktmr)
{
enum hrtimer_mode htmode;
ktime_t texp;
+ int clockid = ctx->clockid;
htmode = (flags & TFD_TIMER_ABSTIME) ?
HRTIMER_MODE_ABS: HRTIMER_MODE_REL;
@@ -72,19 +138,24 @@
ctx->expired = 0;
ctx->ticks = 0;
ctx->tintv = timespec_to_ktime(ktmr->it_interval);
- hrtimer_init(&ctx->tmr, ctx->clockid, htmode);
+ hrtimer_init(&ctx->tmr, clockid, htmode);
hrtimer_set_expires(&ctx->tmr, texp);
ctx->tmr.function = timerfd_tmrproc;
- if (texp.tv64 != 0)
+ if (texp.tv64 != 0) {
hrtimer_start(&ctx->tmr, texp, htmode);
+ if (timerfd_canceled(ctx))
+ return -ECANCELED;
+ }
+ return 0;
}
static int timerfd_release(struct inode *inode, struct file *file)
{
struct timerfd_ctx *ctx = file->private_data;
+ timerfd_remove_cancel(ctx);
hrtimer_cancel(&ctx->tmr);
- kfree(ctx);
+ kfree_rcu(ctx, rcu);
return 0;
}
@@ -118,8 +189,21 @@
res = -EAGAIN;
else
res = wait_event_interruptible_locked_irq(ctx->wqh, ctx->ticks);
+
+ /*
+ * If clock has changed, we do not care about the
+ * ticks and we do not rearm the timer. Userspace must
+ * reevaluate anyway.
+ */
+ if (timerfd_canceled(ctx)) {
+ ctx->ticks = 0;
+ ctx->expired = 0;
+ res = -ECANCELED;
+ }
+
if (ctx->ticks) {
ticks = ctx->ticks;
+
if (ctx->expired && ctx->tintv.tv64) {
/*
* If tintv.tv64 != 0, this is a periodic timer that
@@ -183,6 +267,7 @@
init_waitqueue_head(&ctx->wqh);
ctx->clockid = clockid;
hrtimer_init(&ctx->tmr, clockid, HRTIMER_MODE_ABS);
+ ctx->moffs = ktime_get_monotonic_offset();
ufd = anon_inode_getfd("[timerfd]", &timerfd_fops, ctx,
O_RDWR | (flags & TFD_SHARED_FCNTL_FLAGS));
@@ -199,6 +284,7 @@
struct file *file;
struct timerfd_ctx *ctx;
struct itimerspec ktmr, kotmr;
+ int ret;
if (copy_from_user(&ktmr, utmr, sizeof(ktmr)))
return -EFAULT;
@@ -213,6 +299,8 @@
return PTR_ERR(file);
ctx = file->private_data;
+ timerfd_setup_cancel(ctx, flags);
+
/*
* We need to stop the existing timer before reprogramming
* it to the new values.
@@ -240,14 +328,14 @@
/*
* Re-program the timer to the new value ...
*/
- timerfd_setup(ctx, flags, &ktmr);
+ ret = timerfd_setup(ctx, flags, &ktmr);
spin_unlock_irq(&ctx->wqh.lock);
fput(file);
if (otmr && copy_to_user(otmr, &kotmr, sizeof(kotmr)))
return -EFAULT;
- return 0;
+ return ret;
}
SYSCALL_DEFINE2(timerfd_gettime, int, ufd, struct itimerspec __user *, otmr)
diff --git a/fs/ubifs/budget.c b/fs/ubifs/budget.c
index 8b3a7da..315de66 100644
--- a/fs/ubifs/budget.c
+++ b/fs/ubifs/budget.c
@@ -106,7 +106,7 @@
long long liab;
spin_lock(&c->space_lock);
- liab = c->budg_idx_growth + c->budg_data_growth + c->budg_dd_growth;
+ liab = c->bi.idx_growth + c->bi.data_growth + c->bi.dd_growth;
spin_unlock(&c->space_lock);
return liab;
}
@@ -180,7 +180,7 @@
int idx_lebs;
long long idx_size;
- idx_size = c->old_idx_sz + c->budg_idx_growth + c->budg_uncommitted_idx;
+ idx_size = c->bi.old_idx_sz + c->bi.idx_growth + c->bi.uncommitted_idx;
/* And make sure we have thrice the index size of space reserved */
idx_size += idx_size << 1;
/*
@@ -292,13 +292,13 @@
* budgeted index space to the size of the current index, multiplies this by 3,
* and makes sure this does not exceed the amount of free LEBs.
*
- * Notes about @c->min_idx_lebs and @c->lst.idx_lebs variables:
+ * Notes about @c->bi.min_idx_lebs and @c->lst.idx_lebs variables:
* o @c->lst.idx_lebs is the number of LEBs the index currently uses. It might
* be large, because UBIFS does not do any index consolidation as long as
* there is free space. IOW, the index may take a lot of LEBs, but the LEBs
* will contain a lot of dirt.
- * o @c->min_idx_lebs is the number of LEBS the index presumably takes. IOW,
- * the index may be consolidated to take up to @c->min_idx_lebs LEBs.
+ * o @c->bi.min_idx_lebs is the number of LEBS the index presumably takes. IOW,
+ * the index may be consolidated to take up to @c->bi.min_idx_lebs LEBs.
*
* This function returns zero in case of success, and %-ENOSPC in case of
* failure.
@@ -343,13 +343,13 @@
c->lst.taken_empty_lebs;
if (unlikely(rsvd_idx_lebs > lebs)) {
dbg_budg("out of indexing space: min_idx_lebs %d (old %d), "
- "rsvd_idx_lebs %d", min_idx_lebs, c->min_idx_lebs,
+ "rsvd_idx_lebs %d", min_idx_lebs, c->bi.min_idx_lebs,
rsvd_idx_lebs);
return -ENOSPC;
}
available = ubifs_calc_available(c, min_idx_lebs);
- outstanding = c->budg_data_growth + c->budg_dd_growth;
+ outstanding = c->bi.data_growth + c->bi.dd_growth;
if (unlikely(available < outstanding)) {
dbg_budg("out of data space: available %lld, outstanding %lld",
@@ -360,7 +360,7 @@
if (available - outstanding <= c->rp_size && !can_use_rp(c))
return -ENOSPC;
- c->min_idx_lebs = min_idx_lebs;
+ c->bi.min_idx_lebs = min_idx_lebs;
return 0;
}
@@ -393,11 +393,11 @@
{
int data_growth;
- data_growth = req->new_ino ? c->inode_budget : 0;
+ data_growth = req->new_ino ? c->bi.inode_budget : 0;
if (req->new_page)
- data_growth += c->page_budget;
+ data_growth += c->bi.page_budget;
if (req->new_dent)
- data_growth += c->dent_budget;
+ data_growth += c->bi.dent_budget;
data_growth += req->new_ino_d;
return data_growth;
}
@@ -413,12 +413,12 @@
{
int dd_growth;
- dd_growth = req->dirtied_page ? c->page_budget : 0;
+ dd_growth = req->dirtied_page ? c->bi.page_budget : 0;
if (req->dirtied_ino)
- dd_growth += c->inode_budget << (req->dirtied_ino - 1);
+ dd_growth += c->bi.inode_budget << (req->dirtied_ino - 1);
if (req->mod_dent)
- dd_growth += c->dent_budget;
+ dd_growth += c->bi.dent_budget;
dd_growth += req->dirtied_ino_d;
return dd_growth;
}
@@ -460,19 +460,19 @@
again:
spin_lock(&c->space_lock);
- ubifs_assert(c->budg_idx_growth >= 0);
- ubifs_assert(c->budg_data_growth >= 0);
- ubifs_assert(c->budg_dd_growth >= 0);
+ ubifs_assert(c->bi.idx_growth >= 0);
+ ubifs_assert(c->bi.data_growth >= 0);
+ ubifs_assert(c->bi.dd_growth >= 0);
- if (unlikely(c->nospace) && (c->nospace_rp || !can_use_rp(c))) {
+ if (unlikely(c->bi.nospace) && (c->bi.nospace_rp || !can_use_rp(c))) {
dbg_budg("no space");
spin_unlock(&c->space_lock);
return -ENOSPC;
}
- c->budg_idx_growth += idx_growth;
- c->budg_data_growth += data_growth;
- c->budg_dd_growth += dd_growth;
+ c->bi.idx_growth += idx_growth;
+ c->bi.data_growth += data_growth;
+ c->bi.dd_growth += dd_growth;
err = do_budget_space(c);
if (likely(!err)) {
@@ -484,9 +484,9 @@
}
/* Restore the old values */
- c->budg_idx_growth -= idx_growth;
- c->budg_data_growth -= data_growth;
- c->budg_dd_growth -= dd_growth;
+ c->bi.idx_growth -= idx_growth;
+ c->bi.data_growth -= data_growth;
+ c->bi.dd_growth -= dd_growth;
spin_unlock(&c->space_lock);
if (req->fast) {
@@ -506,9 +506,9 @@
goto again;
}
dbg_budg("FS is full, -ENOSPC");
- c->nospace = 1;
+ c->bi.nospace = 1;
if (can_use_rp(c) || c->rp_size == 0)
- c->nospace_rp = 1;
+ c->bi.nospace_rp = 1;
smp_wmb();
} else
ubifs_err("cannot budget space, error %d", err);
@@ -523,8 +523,8 @@
* This function releases the space budgeted by 'ubifs_budget_space()'. Note,
* since the index changes (which were budgeted for in @req->idx_growth) will
* only be written to the media on commit, this function moves the index budget
- * from @c->budg_idx_growth to @c->budg_uncommitted_idx. The latter will be
- * zeroed by the commit operation.
+ * from @c->bi.idx_growth to @c->bi.uncommitted_idx. The latter will be zeroed
+ * by the commit operation.
*/
void ubifs_release_budget(struct ubifs_info *c, struct ubifs_budget_req *req)
{
@@ -553,23 +553,23 @@
if (!req->data_growth && !req->dd_growth)
return;
- c->nospace = c->nospace_rp = 0;
+ c->bi.nospace = c->bi.nospace_rp = 0;
smp_wmb();
spin_lock(&c->space_lock);
- c->budg_idx_growth -= req->idx_growth;
- c->budg_uncommitted_idx += req->idx_growth;
- c->budg_data_growth -= req->data_growth;
- c->budg_dd_growth -= req->dd_growth;
- c->min_idx_lebs = ubifs_calc_min_idx_lebs(c);
+ c->bi.idx_growth -= req->idx_growth;
+ c->bi.uncommitted_idx += req->idx_growth;
+ c->bi.data_growth -= req->data_growth;
+ c->bi.dd_growth -= req->dd_growth;
+ c->bi.min_idx_lebs = ubifs_calc_min_idx_lebs(c);
- ubifs_assert(c->budg_idx_growth >= 0);
- ubifs_assert(c->budg_data_growth >= 0);
- ubifs_assert(c->budg_dd_growth >= 0);
- ubifs_assert(c->min_idx_lebs < c->main_lebs);
- ubifs_assert(!(c->budg_idx_growth & 7));
- ubifs_assert(!(c->budg_data_growth & 7));
- ubifs_assert(!(c->budg_dd_growth & 7));
+ ubifs_assert(c->bi.idx_growth >= 0);
+ ubifs_assert(c->bi.data_growth >= 0);
+ ubifs_assert(c->bi.dd_growth >= 0);
+ ubifs_assert(c->bi.min_idx_lebs < c->main_lebs);
+ ubifs_assert(!(c->bi.idx_growth & 7));
+ ubifs_assert(!(c->bi.data_growth & 7));
+ ubifs_assert(!(c->bi.dd_growth & 7));
spin_unlock(&c->space_lock);
}
@@ -586,13 +586,13 @@
{
spin_lock(&c->space_lock);
/* Release the index growth reservation */
- c->budg_idx_growth -= c->max_idx_node_sz << UBIFS_BLOCKS_PER_PAGE_SHIFT;
+ c->bi.idx_growth -= c->max_idx_node_sz << UBIFS_BLOCKS_PER_PAGE_SHIFT;
/* Release the data growth reservation */
- c->budg_data_growth -= c->page_budget;
+ c->bi.data_growth -= c->bi.page_budget;
/* Increase the dirty data growth reservation instead */
- c->budg_dd_growth += c->page_budget;
+ c->bi.dd_growth += c->bi.page_budget;
/* And re-calculate the indexing space reservation */
- c->min_idx_lebs = ubifs_calc_min_idx_lebs(c);
+ c->bi.min_idx_lebs = ubifs_calc_min_idx_lebs(c);
spin_unlock(&c->space_lock);
}
@@ -612,7 +612,7 @@
memset(&req, 0, sizeof(struct ubifs_budget_req));
/* The "no space" flags will be cleared because dd_growth is > 0 */
- req.dd_growth = c->inode_budget + ALIGN(ui->data_len, 8);
+ req.dd_growth = c->bi.inode_budget + ALIGN(ui->data_len, 8);
ubifs_release_budget(c, &req);
}
@@ -682,9 +682,9 @@
int rsvd_idx_lebs, lebs;
long long available, outstanding, free;
- ubifs_assert(c->min_idx_lebs == ubifs_calc_min_idx_lebs(c));
- outstanding = c->budg_data_growth + c->budg_dd_growth;
- available = ubifs_calc_available(c, c->min_idx_lebs);
+ ubifs_assert(c->bi.min_idx_lebs == ubifs_calc_min_idx_lebs(c));
+ outstanding = c->bi.data_growth + c->bi.dd_growth;
+ available = ubifs_calc_available(c, c->bi.min_idx_lebs);
/*
* When reporting free space to user-space, UBIFS guarantees that it is
@@ -697,8 +697,8 @@
* Note, the calculations below are similar to what we have in
* 'do_budget_space()', so refer there for comments.
*/
- if (c->min_idx_lebs > c->lst.idx_lebs)
- rsvd_idx_lebs = c->min_idx_lebs - c->lst.idx_lebs;
+ if (c->bi.min_idx_lebs > c->lst.idx_lebs)
+ rsvd_idx_lebs = c->bi.min_idx_lebs - c->lst.idx_lebs;
else
rsvd_idx_lebs = 0;
lebs = c->lst.empty_lebs + c->freeable_cnt + c->idx_gc_cnt -
diff --git a/fs/ubifs/commit.c b/fs/ubifs/commit.c
index 1bd01de..87cd0ea 100644
--- a/fs/ubifs/commit.c
+++ b/fs/ubifs/commit.c
@@ -182,7 +182,7 @@
c->mst_node->root_len = cpu_to_le32(zroot.len);
c->mst_node->ihead_lnum = cpu_to_le32(c->ihead_lnum);
c->mst_node->ihead_offs = cpu_to_le32(c->ihead_offs);
- c->mst_node->index_size = cpu_to_le64(c->old_idx_sz);
+ c->mst_node->index_size = cpu_to_le64(c->bi.old_idx_sz);
c->mst_node->lpt_lnum = cpu_to_le32(c->lpt_lnum);
c->mst_node->lpt_offs = cpu_to_le32(c->lpt_offs);
c->mst_node->nhead_lnum = cpu_to_le32(c->nhead_lnum);
diff --git a/fs/ubifs/debug.c b/fs/ubifs/debug.c
index 004d374..0bb2bce 100644
--- a/fs/ubifs/debug.c
+++ b/fs/ubifs/debug.c
@@ -34,7 +34,6 @@
#include <linux/moduleparam.h>
#include <linux/debugfs.h>
#include <linux/math64.h>
-#include <linux/slab.h>
#ifdef CONFIG_UBIFS_FS_DEBUG
@@ -43,15 +42,12 @@
static char dbg_key_buf0[128];
static char dbg_key_buf1[128];
-unsigned int ubifs_msg_flags;
unsigned int ubifs_chk_flags;
unsigned int ubifs_tst_flags;
-module_param_named(debug_msgs, ubifs_msg_flags, uint, S_IRUGO | S_IWUSR);
module_param_named(debug_chks, ubifs_chk_flags, uint, S_IRUGO | S_IWUSR);
module_param_named(debug_tsts, ubifs_tst_flags, uint, S_IRUGO | S_IWUSR);
-MODULE_PARM_DESC(debug_msgs, "Debug message type flags");
MODULE_PARM_DESC(debug_chks, "Debug check flags");
MODULE_PARM_DESC(debug_tsts, "Debug special test flags");
@@ -317,6 +313,8 @@
printk(KERN_DEBUG "\tflags %#x\n", sup_flags);
printk(KERN_DEBUG "\t big_lpt %u\n",
!!(sup_flags & UBIFS_FLG_BIGLPT));
+ printk(KERN_DEBUG "\t space_fixup %u\n",
+ !!(sup_flags & UBIFS_FLG_SPACE_FIXUP));
printk(KERN_DEBUG "\tmin_io_size %u\n",
le32_to_cpu(sup->min_io_size));
printk(KERN_DEBUG "\tleb_size %u\n",
@@ -602,7 +600,7 @@
spin_unlock(&dbg_lock);
}
-void dbg_dump_budg(struct ubifs_info *c)
+void dbg_dump_budg(struct ubifs_info *c, const struct ubifs_budg_info *bi)
{
int i;
struct rb_node *rb;
@@ -610,26 +608,42 @@
struct ubifs_gced_idx_leb *idx_gc;
long long available, outstanding, free;
- ubifs_assert(spin_is_locked(&c->space_lock));
+ spin_lock(&c->space_lock);
spin_lock(&dbg_lock);
- printk(KERN_DEBUG "(pid %d) Budgeting info: budg_data_growth %lld, "
- "budg_dd_growth %lld, budg_idx_growth %lld\n", current->pid,
- c->budg_data_growth, c->budg_dd_growth, c->budg_idx_growth);
- printk(KERN_DEBUG "\tdata budget sum %lld, total budget sum %lld, "
- "freeable_cnt %d\n", c->budg_data_growth + c->budg_dd_growth,
- c->budg_data_growth + c->budg_dd_growth + c->budg_idx_growth,
- c->freeable_cnt);
- printk(KERN_DEBUG "\tmin_idx_lebs %d, old_idx_sz %lld, "
- "calc_idx_sz %lld, idx_gc_cnt %d\n", c->min_idx_lebs,
- c->old_idx_sz, c->calc_idx_sz, c->idx_gc_cnt);
+ printk(KERN_DEBUG "(pid %d) Budgeting info: data budget sum %lld, "
+ "total budget sum %lld\n", current->pid,
+ bi->data_growth + bi->dd_growth,
+ bi->data_growth + bi->dd_growth + bi->idx_growth);
+ printk(KERN_DEBUG "\tbudg_data_growth %lld, budg_dd_growth %lld, "
+ "budg_idx_growth %lld\n", bi->data_growth, bi->dd_growth,
+ bi->idx_growth);
+ printk(KERN_DEBUG "\tmin_idx_lebs %d, old_idx_sz %llu, "
+ "uncommitted_idx %lld\n", bi->min_idx_lebs, bi->old_idx_sz,
+ bi->uncommitted_idx);
+ printk(KERN_DEBUG "\tpage_budget %d, inode_budget %d, dent_budget %d\n",
+ bi->page_budget, bi->inode_budget, bi->dent_budget);
+ printk(KERN_DEBUG "\tnospace %u, nospace_rp %u\n",
+ bi->nospace, bi->nospace_rp);
+ printk(KERN_DEBUG "\tdark_wm %d, dead_wm %d, max_idx_node_sz %d\n",
+ c->dark_wm, c->dead_wm, c->max_idx_node_sz);
+
+ if (bi != &c->bi)
+ /*
+ * If we are dumping saved budgeting data, do not print
+ * additional information which is about the current state, not
+ * the old one which corresponded to the saved budgeting data.
+ */
+ goto out_unlock;
+
+ printk(KERN_DEBUG "\tfreeable_cnt %d, calc_idx_sz %lld, idx_gc_cnt %d\n",
+ c->freeable_cnt, c->calc_idx_sz, c->idx_gc_cnt);
printk(KERN_DEBUG "\tdirty_pg_cnt %ld, dirty_zn_cnt %ld, "
"clean_zn_cnt %ld\n", atomic_long_read(&c->dirty_pg_cnt),
atomic_long_read(&c->dirty_zn_cnt),
atomic_long_read(&c->clean_zn_cnt));
- printk(KERN_DEBUG "\tdark_wm %d, dead_wm %d, max_idx_node_sz %d\n",
- c->dark_wm, c->dead_wm, c->max_idx_node_sz);
printk(KERN_DEBUG "\tgc_lnum %d, ihead_lnum %d\n",
c->gc_lnum, c->ihead_lnum);
+
/* If we are in R/O mode, journal heads do not exist */
if (c->jheads)
for (i = 0; i < c->jhead_cnt; i++)
@@ -648,13 +662,15 @@
printk(KERN_DEBUG "\tcommit state %d\n", c->cmt_state);
/* Print budgeting predictions */
- available = ubifs_calc_available(c, c->min_idx_lebs);
- outstanding = c->budg_data_growth + c->budg_dd_growth;
+ available = ubifs_calc_available(c, c->bi.min_idx_lebs);
+ outstanding = c->bi.data_growth + c->bi.dd_growth;
free = ubifs_get_free_space_nolock(c);
printk(KERN_DEBUG "Budgeting predictions:\n");
printk(KERN_DEBUG "\tavailable: %lld, outstanding %lld, free %lld\n",
available, outstanding, free);
+out_unlock:
spin_unlock(&dbg_lock);
+ spin_unlock(&c->space_lock);
}
void dbg_dump_lprop(const struct ubifs_info *c, const struct ubifs_lprops *lp)
@@ -729,7 +745,13 @@
if (bud->lnum == lp->lnum) {
int head = 0;
for (i = 0; i < c->jhead_cnt; i++) {
- if (lp->lnum == c->jheads[i].wbuf.lnum) {
+ /*
+ * Note, if we are in R/O mode or in the middle
+ * of mounting/re-mounting, the write-buffers do
+ * not exist.
+ */
+ if (c->jheads &&
+ lp->lnum == c->jheads[i].wbuf.lnum) {
printk(KERN_CONT ", jhead %s",
dbg_jhead(i));
head = 1;
@@ -976,6 +998,8 @@
spin_lock(&c->space_lock);
memcpy(&d->saved_lst, &c->lst, sizeof(struct ubifs_lp_stats));
+ memcpy(&d->saved_bi, &c->bi, sizeof(struct ubifs_budg_info));
+ d->saved_idx_gc_cnt = c->idx_gc_cnt;
/*
* We use a dirty hack here and zero out @c->freeable_cnt, because it
@@ -1042,14 +1066,14 @@
out:
ubifs_msg("saved lprops statistics dump");
dbg_dump_lstats(&d->saved_lst);
- ubifs_get_lp_stats(c, &lst);
-
+ ubifs_msg("saved budgeting info dump");
+ dbg_dump_budg(c, &d->saved_bi);
+ ubifs_msg("saved idx_gc_cnt %d", d->saved_idx_gc_cnt);
ubifs_msg("current lprops statistics dump");
+ ubifs_get_lp_stats(c, &lst);
dbg_dump_lstats(&lst);
-
- spin_lock(&c->space_lock);
- dbg_dump_budg(c);
- spin_unlock(&c->space_lock);
+ ubifs_msg("current budgeting info dump");
+ dbg_dump_budg(c, &c->bi);
dump_stack();
return -EINVAL;
}
@@ -1793,6 +1817,8 @@
struct rb_node **p, *parent = NULL;
struct fsck_inode *fscki;
ino_t inum = key_inum_flash(c, &ino->key);
+ struct inode *inode;
+ struct ubifs_inode *ui;
p = &fsckd->inodes.rb_node;
while (*p) {
@@ -1816,19 +1842,46 @@
if (!fscki)
return ERR_PTR(-ENOMEM);
+ inode = ilookup(c->vfs_sb, inum);
+
fscki->inum = inum;
- fscki->nlink = le32_to_cpu(ino->nlink);
- fscki->size = le64_to_cpu(ino->size);
- fscki->xattr_cnt = le32_to_cpu(ino->xattr_cnt);
- fscki->xattr_sz = le32_to_cpu(ino->xattr_size);
- fscki->xattr_nms = le32_to_cpu(ino->xattr_names);
- fscki->mode = le32_to_cpu(ino->mode);
+ /*
+ * If the inode is present in the VFS inode cache, use it instead of
+ * the on-flash inode which might be out-of-date. E.g., the size might
+ * be out-of-date. If we do not do this, the following may happen, for
+ * example:
+ * 1. A power cut happens
+ * 2. We mount the file-system R/O, the replay process fixes up the
+ * inode size in the VFS cache, but on on-flash.
+ * 3. 'check_leaf()' fails because it hits a data node beyond inode
+ * size.
+ */
+ if (!inode) {
+ fscki->nlink = le32_to_cpu(ino->nlink);
+ fscki->size = le64_to_cpu(ino->size);
+ fscki->xattr_cnt = le32_to_cpu(ino->xattr_cnt);
+ fscki->xattr_sz = le32_to_cpu(ino->xattr_size);
+ fscki->xattr_nms = le32_to_cpu(ino->xattr_names);
+ fscki->mode = le32_to_cpu(ino->mode);
+ } else {
+ ui = ubifs_inode(inode);
+ fscki->nlink = inode->i_nlink;
+ fscki->size = inode->i_size;
+ fscki->xattr_cnt = ui->xattr_cnt;
+ fscki->xattr_sz = ui->xattr_size;
+ fscki->xattr_nms = ui->xattr_names;
+ fscki->mode = inode->i_mode;
+ iput(inode);
+ }
+
if (S_ISDIR(fscki->mode)) {
fscki->calc_sz = UBIFS_INO_NODE_SZ;
fscki->calc_cnt = 2;
}
+
rb_link_node(&fscki->rb, parent, p);
rb_insert_color(&fscki->rb, &fsckd->inodes);
+
return fscki;
}
@@ -2421,7 +2474,8 @@
hashb = key_block(c, &sb->key);
if (hasha > hashb) {
- ubifs_err("larger hash %u goes before %u", hasha, hashb);
+ ubifs_err("larger hash %u goes before %u",
+ hasha, hashb);
goto error_dump;
}
}
@@ -2437,14 +2491,12 @@
return 0;
}
-static int invocation_cnt;
-
int dbg_force_in_the_gaps(void)
{
- if (!dbg_force_in_the_gaps_enabled)
+ if (!(ubifs_chk_flags & UBIFS_CHK_GEN))
return 0;
- /* Force in-the-gaps every 8th commit */
- return !((invocation_cnt++) & 0x7);
+
+ return !(random32() & 7);
}
/* Failure mode for recovery testing */
@@ -2632,7 +2684,7 @@
int len, int check)
{
if (in_failure_mode(desc))
- return -EIO;
+ return -EROFS;
return ubi_leb_read(desc, lnum, buf, offset, len, check);
}
@@ -2642,7 +2694,7 @@
int err, failing;
if (in_failure_mode(desc))
- return -EIO;
+ return -EROFS;
failing = do_fail(desc, lnum, 1);
if (failing)
cut_data(buf, len);
@@ -2650,7 +2702,7 @@
if (err)
return err;
if (failing)
- return -EIO;
+ return -EROFS;
return 0;
}
@@ -2660,12 +2712,12 @@
int err;
if (do_fail(desc, lnum, 1))
- return -EIO;
+ return -EROFS;
err = ubi_leb_change(desc, lnum, buf, len, dtype);
if (err)
return err;
if (do_fail(desc, lnum, 1))
- return -EIO;
+ return -EROFS;
return 0;
}
@@ -2674,12 +2726,12 @@
int err;
if (do_fail(desc, lnum, 0))
- return -EIO;
+ return -EROFS;
err = ubi_leb_erase(desc, lnum);
if (err)
return err;
if (do_fail(desc, lnum, 0))
- return -EIO;
+ return -EROFS;
return 0;
}
@@ -2688,19 +2740,19 @@
int err;
if (do_fail(desc, lnum, 0))
- return -EIO;
+ return -EROFS;
err = ubi_leb_unmap(desc, lnum);
if (err)
return err;
if (do_fail(desc, lnum, 0))
- return -EIO;
+ return -EROFS;
return 0;
}
int dbg_is_mapped(struct ubi_volume_desc *desc, int lnum)
{
if (in_failure_mode(desc))
- return -EIO;
+ return -EROFS;
return ubi_is_mapped(desc, lnum);
}
@@ -2709,12 +2761,12 @@
int err;
if (do_fail(desc, lnum, 0))
- return -EIO;
+ return -EROFS;
err = ubi_leb_map(desc, lnum, dtype);
if (err)
return err;
if (do_fail(desc, lnum, 0))
- return -EIO;
+ return -EROFS;
return 0;
}
@@ -2784,7 +2836,7 @@
static int open_debugfs_file(struct inode *inode, struct file *file)
{
file->private_data = inode->i_private;
- return 0;
+ return nonseekable_open(inode, file);
}
static ssize_t write_debugfs_file(struct file *file, const char __user *buf,
@@ -2795,18 +2847,15 @@
if (file->f_path.dentry == d->dfs_dump_lprops)
dbg_dump_lprops(c);
- else if (file->f_path.dentry == d->dfs_dump_budg) {
- spin_lock(&c->space_lock);
- dbg_dump_budg(c);
- spin_unlock(&c->space_lock);
- } else if (file->f_path.dentry == d->dfs_dump_tnc) {
+ else if (file->f_path.dentry == d->dfs_dump_budg)
+ dbg_dump_budg(c, &c->bi);
+ else if (file->f_path.dentry == d->dfs_dump_tnc) {
mutex_lock(&c->tnc_mutex);
dbg_dump_tnc(c);
mutex_unlock(&c->tnc_mutex);
} else
return -EINVAL;
- *ppos += count;
return count;
}
@@ -2814,7 +2863,7 @@
.open = open_debugfs_file,
.write = write_debugfs_file,
.owner = THIS_MODULE,
- .llseek = default_llseek,
+ .llseek = no_llseek,
};
/**
diff --git a/fs/ubifs/debug.h b/fs/ubifs/debug.h
index e6493ca..a811ac4 100644
--- a/fs/ubifs/debug.h
+++ b/fs/ubifs/debug.h
@@ -31,6 +31,8 @@
#ifdef CONFIG_UBIFS_FS_DEBUG
+#include <linux/random.h>
+
/**
* ubifs_debug_info - per-FS debugging information.
* @old_zroot: old index root - used by 'dbg_check_old_index()'
@@ -50,13 +52,15 @@
* @new_ihead_offs: used by debugging to check @c->ihead_offs
*
* @saved_lst: saved lprops statistics (used by 'dbg_save_space_info()')
- * @saved_free: saved free space (used by 'dbg_save_space_info()')
+ * @saved_bi: saved budgeting information
+ * @saved_free: saved amount of free space
+ * @saved_idx_gc_cnt: saved value of @c->idx_gc_cnt
*
- * dfs_dir_name: name of debugfs directory containing this file-system's files
- * dfs_dir: direntry object of the file-system debugfs directory
- * dfs_dump_lprops: "dump lprops" debugfs knob
- * dfs_dump_budg: "dump budgeting information" debugfs knob
- * dfs_dump_tnc: "dump TNC" debugfs knob
+ * @dfs_dir_name: name of debugfs directory containing this file-system's files
+ * @dfs_dir: direntry object of the file-system debugfs directory
+ * @dfs_dump_lprops: "dump lprops" debugfs knob
+ * @dfs_dump_budg: "dump budgeting information" debugfs knob
+ * @dfs_dump_tnc: "dump TNC" debugfs knob
*/
struct ubifs_debug_info {
struct ubifs_zbranch old_zroot;
@@ -76,7 +80,9 @@
int new_ihead_offs;
struct ubifs_lp_stats saved_lst;
+ struct ubifs_budg_info saved_bi;
long long saved_free;
+ int saved_idx_gc_cnt;
char dfs_dir_name[100];
struct dentry *dfs_dir;
@@ -101,23 +107,7 @@
} \
} while (0)
-#define dbg_dump_stack() do { \
- if (!dbg_failure_mode) \
- dump_stack(); \
-} while (0)
-
-/* Generic debugging messages */
-#define dbg_msg(fmt, ...) do { \
- spin_lock(&dbg_lock); \
- printk(KERN_DEBUG "UBIFS DBG (pid %d): %s: " fmt "\n", current->pid, \
- __func__, ##__VA_ARGS__); \
- spin_unlock(&dbg_lock); \
-} while (0)
-
-#define dbg_do_msg(typ, fmt, ...) do { \
- if (ubifs_msg_flags & typ) \
- dbg_msg(fmt, ##__VA_ARGS__); \
-} while (0)
+#define dbg_dump_stack() dump_stack()
#define dbg_err(fmt, ...) do { \
spin_lock(&dbg_lock); \
@@ -137,77 +127,40 @@
#define DBGKEY(key) dbg_key_str0(c, (key))
#define DBGKEY1(key) dbg_key_str1(c, (key))
+#define ubifs_dbg_msg(type, fmt, ...) do { \
+ spin_lock(&dbg_lock); \
+ pr_debug("UBIFS DBG " type ": " fmt "\n", ##__VA_ARGS__); \
+ spin_unlock(&dbg_lock); \
+} while (0)
+
+/* Just a debugging messages not related to any specific UBIFS subsystem */
+#define dbg_msg(fmt, ...) ubifs_dbg_msg("msg", fmt, ##__VA_ARGS__)
/* General messages */
-#define dbg_gen(fmt, ...) dbg_do_msg(UBIFS_MSG_GEN, fmt, ##__VA_ARGS__)
-
+#define dbg_gen(fmt, ...) ubifs_dbg_msg("gen", fmt, ##__VA_ARGS__)
/* Additional journal messages */
-#define dbg_jnl(fmt, ...) dbg_do_msg(UBIFS_MSG_JNL, fmt, ##__VA_ARGS__)
-
+#define dbg_jnl(fmt, ...) ubifs_dbg_msg("jnl", fmt, ##__VA_ARGS__)
/* Additional TNC messages */
-#define dbg_tnc(fmt, ...) dbg_do_msg(UBIFS_MSG_TNC, fmt, ##__VA_ARGS__)
-
+#define dbg_tnc(fmt, ...) ubifs_dbg_msg("tnc", fmt, ##__VA_ARGS__)
/* Additional lprops messages */
-#define dbg_lp(fmt, ...) dbg_do_msg(UBIFS_MSG_LP, fmt, ##__VA_ARGS__)
-
+#define dbg_lp(fmt, ...) ubifs_dbg_msg("lp", fmt, ##__VA_ARGS__)
/* Additional LEB find messages */
-#define dbg_find(fmt, ...) dbg_do_msg(UBIFS_MSG_FIND, fmt, ##__VA_ARGS__)
-
+#define dbg_find(fmt, ...) ubifs_dbg_msg("find", fmt, ##__VA_ARGS__)
/* Additional mount messages */
-#define dbg_mnt(fmt, ...) dbg_do_msg(UBIFS_MSG_MNT, fmt, ##__VA_ARGS__)
-
+#define dbg_mnt(fmt, ...) ubifs_dbg_msg("mnt", fmt, ##__VA_ARGS__)
/* Additional I/O messages */
-#define dbg_io(fmt, ...) dbg_do_msg(UBIFS_MSG_IO, fmt, ##__VA_ARGS__)
-
+#define dbg_io(fmt, ...) ubifs_dbg_msg("io", fmt, ##__VA_ARGS__)
/* Additional commit messages */
-#define dbg_cmt(fmt, ...) dbg_do_msg(UBIFS_MSG_CMT, fmt, ##__VA_ARGS__)
-
+#define dbg_cmt(fmt, ...) ubifs_dbg_msg("cmt", fmt, ##__VA_ARGS__)
/* Additional budgeting messages */
-#define dbg_budg(fmt, ...) dbg_do_msg(UBIFS_MSG_BUDG, fmt, ##__VA_ARGS__)
-
+#define dbg_budg(fmt, ...) ubifs_dbg_msg("budg", fmt, ##__VA_ARGS__)
/* Additional log messages */
-#define dbg_log(fmt, ...) dbg_do_msg(UBIFS_MSG_LOG, fmt, ##__VA_ARGS__)
-
+#define dbg_log(fmt, ...) ubifs_dbg_msg("log", fmt, ##__VA_ARGS__)
/* Additional gc messages */
-#define dbg_gc(fmt, ...) dbg_do_msg(UBIFS_MSG_GC, fmt, ##__VA_ARGS__)
-
+#define dbg_gc(fmt, ...) ubifs_dbg_msg("gc", fmt, ##__VA_ARGS__)
/* Additional scan messages */
-#define dbg_scan(fmt, ...) dbg_do_msg(UBIFS_MSG_SCAN, fmt, ##__VA_ARGS__)
-
+#define dbg_scan(fmt, ...) ubifs_dbg_msg("scan", fmt, ##__VA_ARGS__)
/* Additional recovery messages */
-#define dbg_rcvry(fmt, ...) dbg_do_msg(UBIFS_MSG_RCVRY, fmt, ##__VA_ARGS__)
-
-/*
- * Debugging message type flags.
- *
- * UBIFS_MSG_GEN: general messages
- * UBIFS_MSG_JNL: journal messages
- * UBIFS_MSG_MNT: mount messages
- * UBIFS_MSG_CMT: commit messages
- * UBIFS_MSG_FIND: LEB find messages
- * UBIFS_MSG_BUDG: budgeting messages
- * UBIFS_MSG_GC: garbage collection messages
- * UBIFS_MSG_TNC: TNC messages
- * UBIFS_MSG_LP: lprops messages
- * UBIFS_MSG_IO: I/O messages
- * UBIFS_MSG_LOG: log messages
- * UBIFS_MSG_SCAN: scan messages
- * UBIFS_MSG_RCVRY: recovery messages
- */
-enum {
- UBIFS_MSG_GEN = 0x1,
- UBIFS_MSG_JNL = 0x2,
- UBIFS_MSG_MNT = 0x4,
- UBIFS_MSG_CMT = 0x8,
- UBIFS_MSG_FIND = 0x10,
- UBIFS_MSG_BUDG = 0x20,
- UBIFS_MSG_GC = 0x40,
- UBIFS_MSG_TNC = 0x80,
- UBIFS_MSG_LP = 0x100,
- UBIFS_MSG_IO = 0x200,
- UBIFS_MSG_LOG = 0x400,
- UBIFS_MSG_SCAN = 0x800,
- UBIFS_MSG_RCVRY = 0x1000,
-};
+#define dbg_rcvry(fmt, ...) ubifs_dbg_msg("rcvry", fmt, ##__VA_ARGS__)
/*
* Debugging check flags.
@@ -233,11 +186,9 @@
/*
* Special testing flags.
*
- * UBIFS_TST_FORCE_IN_THE_GAPS: force the use of in-the-gaps method
* UBIFS_TST_RCVRY: failure mode for recovery testing
*/
enum {
- UBIFS_TST_FORCE_IN_THE_GAPS = 0x2,
UBIFS_TST_RCVRY = 0x4,
};
@@ -262,7 +213,7 @@
int offs);
void dbg_dump_budget_req(const struct ubifs_budget_req *req);
void dbg_dump_lstats(const struct ubifs_lp_stats *lst);
-void dbg_dump_budg(struct ubifs_info *c);
+void dbg_dump_budg(struct ubifs_info *c, const struct ubifs_budg_info *bi);
void dbg_dump_lprop(const struct ubifs_info *c, const struct ubifs_lprops *lp);
void dbg_dump_lprops(struct ubifs_info *c);
void dbg_dump_lpt_info(struct ubifs_info *c);
@@ -304,18 +255,16 @@
int dbg_check_nondata_nodes_order(struct ubifs_info *c, struct list_head *head);
/* Force the use of in-the-gaps method for testing */
-
-#define dbg_force_in_the_gaps_enabled \
- (ubifs_tst_flags & UBIFS_TST_FORCE_IN_THE_GAPS)
-
+static inline int dbg_force_in_the_gaps_enabled(void)
+{
+ return ubifs_chk_flags & UBIFS_CHK_GEN;
+}
int dbg_force_in_the_gaps(void);
/* Failure mode for recovery testing */
-
#define dbg_failure_mode (ubifs_tst_flags & UBIFS_TST_RCVRY)
#ifndef UBIFS_DBG_PRESERVE_UBI
-
#define ubi_leb_read dbg_leb_read
#define ubi_leb_write dbg_leb_write
#define ubi_leb_change dbg_leb_change
@@ -323,7 +272,6 @@
#define ubi_leb_unmap dbg_leb_unmap
#define ubi_is_mapped dbg_is_mapped
#define ubi_leb_map dbg_leb_map
-
#endif
int dbg_leb_read(struct ubi_volume_desc *desc, int lnum, char *buf, int offset,
@@ -370,33 +318,33 @@
__func__, __LINE__, current->pid); \
} while (0)
-#define dbg_err(fmt, ...) do { \
- if (0) \
- ubifs_err(fmt, ##__VA_ARGS__); \
+#define dbg_err(fmt, ...) do { \
+ if (0) \
+ ubifs_err(fmt, ##__VA_ARGS__); \
} while (0)
-#define dbg_msg(fmt, ...) do { \
- if (0) \
- printk(KERN_DEBUG "UBIFS DBG (pid %d): %s: " fmt "\n", \
- current->pid, __func__, ##__VA_ARGS__); \
+#define ubifs_dbg_msg(fmt, ...) do { \
+ if (0) \
+ pr_debug(fmt "\n", ##__VA_ARGS__); \
} while (0)
#define dbg_dump_stack()
#define ubifs_assert_cmt_locked(c)
-#define dbg_gen(fmt, ...) dbg_msg(fmt, ##__VA_ARGS__)
-#define dbg_jnl(fmt, ...) dbg_msg(fmt, ##__VA_ARGS__)
-#define dbg_tnc(fmt, ...) dbg_msg(fmt, ##__VA_ARGS__)
-#define dbg_lp(fmt, ...) dbg_msg(fmt, ##__VA_ARGS__)
-#define dbg_find(fmt, ...) dbg_msg(fmt, ##__VA_ARGS__)
-#define dbg_mnt(fmt, ...) dbg_msg(fmt, ##__VA_ARGS__)
-#define dbg_io(fmt, ...) dbg_msg(fmt, ##__VA_ARGS__)
-#define dbg_cmt(fmt, ...) dbg_msg(fmt, ##__VA_ARGS__)
-#define dbg_budg(fmt, ...) dbg_msg(fmt, ##__VA_ARGS__)
-#define dbg_log(fmt, ...) dbg_msg(fmt, ##__VA_ARGS__)
-#define dbg_gc(fmt, ...) dbg_msg(fmt, ##__VA_ARGS__)
-#define dbg_scan(fmt, ...) dbg_msg(fmt, ##__VA_ARGS__)
-#define dbg_rcvry(fmt, ...) dbg_msg(fmt, ##__VA_ARGS__)
+#define dbg_msg(fmt, ...) ubifs_dbg_msg(fmt, ##__VA_ARGS__)
+#define dbg_gen(fmt, ...) ubifs_dbg_msg(fmt, ##__VA_ARGS__)
+#define dbg_jnl(fmt, ...) ubifs_dbg_msg(fmt, ##__VA_ARGS__)
+#define dbg_tnc(fmt, ...) ubifs_dbg_msg(fmt, ##__VA_ARGS__)
+#define dbg_lp(fmt, ...) ubifs_dbg_msg(fmt, ##__VA_ARGS__)
+#define dbg_find(fmt, ...) ubifs_dbg_msg(fmt, ##__VA_ARGS__)
+#define dbg_mnt(fmt, ...) ubifs_dbg_msg(fmt, ##__VA_ARGS__)
+#define dbg_io(fmt, ...) ubifs_dbg_msg(fmt, ##__VA_ARGS__)
+#define dbg_cmt(fmt, ...) ubifs_dbg_msg(fmt, ##__VA_ARGS__)
+#define dbg_budg(fmt, ...) ubifs_dbg_msg(fmt, ##__VA_ARGS__)
+#define dbg_log(fmt, ...) ubifs_dbg_msg(fmt, ##__VA_ARGS__)
+#define dbg_gc(fmt, ...) ubifs_dbg_msg(fmt, ##__VA_ARGS__)
+#define dbg_scan(fmt, ...) ubifs_dbg_msg(fmt, ##__VA_ARGS__)
+#define dbg_rcvry(fmt, ...) ubifs_dbg_msg(fmt, ##__VA_ARGS__)
#define DBGKEY(key) ((char *)(key))
#define DBGKEY1(key) ((char *)(key))
@@ -420,7 +368,9 @@
dbg_dump_budget_req(const struct ubifs_budget_req *req) { return; }
static inline void
dbg_dump_lstats(const struct ubifs_lp_stats *lst) { return; }
-static inline void dbg_dump_budg(struct ubifs_info *c) { return; }
+static inline void
+dbg_dump_budg(struct ubifs_info *c,
+ const struct ubifs_budg_info *bi) { return; }
static inline void dbg_dump_lprop(const struct ubifs_info *c,
const struct ubifs_lprops *lp) { return; }
static inline void dbg_dump_lprops(struct ubifs_info *c) { return; }
@@ -482,8 +432,8 @@
struct list_head *head) { return 0; }
static inline int dbg_force_in_the_gaps(void) { return 0; }
-#define dbg_force_in_the_gaps_enabled 0
-#define dbg_failure_mode 0
+#define dbg_force_in_the_gaps_enabled() 0
+#define dbg_failure_mode 0
static inline int dbg_debugfs_init(void) { return 0; }
static inline void dbg_debugfs_exit(void) { return; }
diff --git a/fs/ubifs/dir.c b/fs/ubifs/dir.c
index 7217d67..ef5abd3 100644
--- a/fs/ubifs/dir.c
+++ b/fs/ubifs/dir.c
@@ -603,7 +603,7 @@
ubifs_release_budget(c, &req);
else {
/* We've deleted something - clean the "no space" flags */
- c->nospace = c->nospace_rp = 0;
+ c->bi.nospace = c->bi.nospace_rp = 0;
smp_wmb();
}
return 0;
@@ -693,7 +693,7 @@
ubifs_release_budget(c, &req);
else {
/* We've deleted something - clean the "no space" flags */
- c->nospace = c->nospace_rp = 0;
+ c->bi.nospace = c->bi.nospace_rp = 0;
smp_wmb();
}
return 0;
diff --git a/fs/ubifs/file.c b/fs/ubifs/file.c
index b286db7..5e7fccf 100644
--- a/fs/ubifs/file.c
+++ b/fs/ubifs/file.c
@@ -212,7 +212,7 @@
*/
static void release_existing_page_budget(struct ubifs_info *c)
{
- struct ubifs_budget_req req = { .dd_growth = c->page_budget};
+ struct ubifs_budget_req req = { .dd_growth = c->bi.page_budget};
ubifs_release_budget(c, &req);
}
@@ -971,11 +971,11 @@
* the page locked, and it locks @ui_mutex. However, write-back does take inode
* @i_mutex, which means other VFS operations may be run on this inode at the
* same time. And the problematic one is truncation to smaller size, from where
- * we have to call 'truncate_setsize()', which first changes @inode->i_size, then
- * drops the truncated pages. And while dropping the pages, it takes the page
- * lock. This means that 'do_truncation()' cannot call 'truncate_setsize()' with
- * @ui_mutex locked, because it would deadlock with 'ubifs_writepage()'. This
- * means that @inode->i_size is changed while @ui_mutex is unlocked.
+ * we have to call 'truncate_setsize()', which first changes @inode->i_size,
+ * then drops the truncated pages. And while dropping the pages, it takes the
+ * page lock. This means that 'do_truncation()' cannot call 'truncate_setsize()'
+ * with @ui_mutex locked, because it would deadlock with 'ubifs_writepage()'.
+ * This means that @inode->i_size is changed while @ui_mutex is unlocked.
*
* XXX(truncate): with the new truncate sequence this is not true anymore,
* and the calls to truncate_setsize can be move around freely. They should
@@ -1189,7 +1189,7 @@
if (budgeted)
ubifs_release_budget(c, &req);
else {
- c->nospace = c->nospace_rp = 0;
+ c->bi.nospace = c->bi.nospace_rp = 0;
smp_wmb();
}
return err;
@@ -1312,7 +1312,11 @@
dbg_gen("syncing inode %lu", inode->i_ino);
- if (inode->i_sb->s_flags & MS_RDONLY)
+ if (c->ro_mount)
+ /*
+ * For some really strange reasons VFS does not filter out
+ * 'fsync()' for R/O mounted file-systems as per 2.6.39.
+ */
return 0;
/*
@@ -1432,10 +1436,11 @@
}
/*
- * mmap()d file has taken write protection fault and is being made
- * writable. UBIFS must ensure page is budgeted for.
+ * mmap()d file has taken write protection fault and is being made writable.
+ * UBIFS must ensure page is budgeted for.
*/
-static int ubifs_vm_page_mkwrite(struct vm_area_struct *vma, struct vm_fault *vmf)
+static int ubifs_vm_page_mkwrite(struct vm_area_struct *vma,
+ struct vm_fault *vmf)
{
struct page *page = vmf->page;
struct inode *inode = vma->vm_file->f_path.dentry->d_inode;
@@ -1536,7 +1541,6 @@
{
int err;
- /* 'generic_file_mmap()' takes care of NOMMU case */
err = generic_file_mmap(file, vma);
if (err)
return err;
diff --git a/fs/ubifs/find.c b/fs/ubifs/find.c
index 1d54383..2559d17 100644
--- a/fs/ubifs/find.c
+++ b/fs/ubifs/find.c
@@ -252,8 +252,8 @@
* But if the index takes fewer LEBs than it is reserved for it,
* this function must avoid picking those reserved LEBs.
*/
- if (c->min_idx_lebs >= c->lst.idx_lebs) {
- rsvd_idx_lebs = c->min_idx_lebs - c->lst.idx_lebs;
+ if (c->bi.min_idx_lebs >= c->lst.idx_lebs) {
+ rsvd_idx_lebs = c->bi.min_idx_lebs - c->lst.idx_lebs;
exclude_index = 1;
}
spin_unlock(&c->space_lock);
@@ -276,7 +276,7 @@
pick_free = 0;
} else {
spin_lock(&c->space_lock);
- exclude_index = (c->min_idx_lebs >= c->lst.idx_lebs);
+ exclude_index = (c->bi.min_idx_lebs >= c->lst.idx_lebs);
spin_unlock(&c->space_lock);
}
@@ -501,8 +501,8 @@
/* Check if there are enough empty LEBs for commit */
spin_lock(&c->space_lock);
- if (c->min_idx_lebs > c->lst.idx_lebs)
- rsvd_idx_lebs = c->min_idx_lebs - c->lst.idx_lebs;
+ if (c->bi.min_idx_lebs > c->lst.idx_lebs)
+ rsvd_idx_lebs = c->bi.min_idx_lebs - c->lst.idx_lebs;
else
rsvd_idx_lebs = 0;
lebs = c->lst.empty_lebs + c->freeable_cnt + c->idx_gc_cnt -
diff --git a/fs/ubifs/gc.c b/fs/ubifs/gc.c
index 151f108..ded29f6 100644
--- a/fs/ubifs/gc.c
+++ b/fs/ubifs/gc.c
@@ -100,6 +100,10 @@
if (err)
return err;
+ err = ubifs_wbuf_sync_nolock(wbuf);
+ if (err)
+ return err;
+
err = ubifs_add_bud_to_log(c, GCHD, gc_lnum, 0);
if (err)
return err;
@@ -118,7 +122,7 @@
* This function compares data nodes @a and @b. Returns %1 if @a has greater
* inode or block number, and %-1 otherwise.
*/
-int data_nodes_cmp(void *priv, struct list_head *a, struct list_head *b)
+static int data_nodes_cmp(void *priv, struct list_head *a, struct list_head *b)
{
ino_t inuma, inumb;
struct ubifs_info *c = priv;
@@ -161,7 +165,8 @@
* first and sorted by length in descending order. Directory entry nodes go
* after inode nodes and are sorted in ascending hash valuer order.
*/
-int nondata_nodes_cmp(void *priv, struct list_head *a, struct list_head *b)
+static int nondata_nodes_cmp(void *priv, struct list_head *a,
+ struct list_head *b)
{
ino_t inuma, inumb;
struct ubifs_info *c = priv;
@@ -473,6 +478,37 @@
ubifs_assert(c->gc_lnum != lnum);
ubifs_assert(wbuf->lnum != lnum);
+ if (lp->free + lp->dirty == c->leb_size) {
+ /* Special case - a free LEB */
+ dbg_gc("LEB %d is free, return it", lp->lnum);
+ ubifs_assert(!(lp->flags & LPROPS_INDEX));
+
+ if (lp->free != c->leb_size) {
+ /*
+ * Write buffers must be sync'd before unmapping
+ * freeable LEBs, because one of them may contain data
+ * which obsoletes something in 'lp->pnum'.
+ */
+ err = gc_sync_wbufs(c);
+ if (err)
+ return err;
+ err = ubifs_change_one_lp(c, lp->lnum, c->leb_size,
+ 0, 0, 0, 0);
+ if (err)
+ return err;
+ }
+ err = ubifs_leb_unmap(c, lp->lnum);
+ if (err)
+ return err;
+
+ if (c->gc_lnum == -1) {
+ c->gc_lnum = lnum;
+ return LEB_RETAINED;
+ }
+
+ return LEB_FREED;
+ }
+
/*
* We scan the entire LEB even though we only really need to scan up to
* (c->leb_size - lp->free).
@@ -682,37 +718,6 @@
"(min. space %d)", lp.lnum, lp.free, lp.dirty,
lp.free + lp.dirty, min_space);
- if (lp.free + lp.dirty == c->leb_size) {
- /* An empty LEB was returned */
- dbg_gc("LEB %d is free, return it", lp.lnum);
- /*
- * ubifs_find_dirty_leb() doesn't return freeable index
- * LEBs.
- */
- ubifs_assert(!(lp.flags & LPROPS_INDEX));
- if (lp.free != c->leb_size) {
- /*
- * Write buffers must be sync'd before
- * unmapping freeable LEBs, because one of them
- * may contain data which obsoletes something
- * in 'lp.pnum'.
- */
- ret = gc_sync_wbufs(c);
- if (ret)
- goto out;
- ret = ubifs_change_one_lp(c, lp.lnum,
- c->leb_size, 0, 0, 0,
- 0);
- if (ret)
- goto out;
- }
- ret = ubifs_leb_unmap(c, lp.lnum);
- if (ret)
- goto out;
- ret = lp.lnum;
- break;
- }
-
space_before = c->leb_size - wbuf->offs - wbuf->used;
if (wbuf->lnum == -1)
space_before = 0;
diff --git a/fs/ubifs/io.c b/fs/ubifs/io.c
index dfd168b..166951e 100644
--- a/fs/ubifs/io.c
+++ b/fs/ubifs/io.c
@@ -393,7 +393,7 @@
ubifs_assert(wbuf->size % c->min_io_size == 0);
ubifs_assert(!c->ro_media && !c->ro_mount);
if (c->leb_size - wbuf->offs >= c->max_write_size)
- ubifs_assert(!((wbuf->offs + wbuf->size) % c->max_write_size ));
+ ubifs_assert(!((wbuf->offs + wbuf->size) % c->max_write_size));
if (c->ro_error)
return -EROFS;
@@ -452,8 +452,8 @@
* @dtype: data type
*
* This function targets the write-buffer to logical eraseblock @lnum:@offs.
- * The write-buffer is synchronized if it is not empty. Returns zero in case of
- * success and a negative error code in case of failure.
+ * The write-buffer has to be empty. Returns zero in case of success and a
+ * negative error code in case of failure.
*/
int ubifs_wbuf_seek_nolock(struct ubifs_wbuf *wbuf, int lnum, int offs,
int dtype)
@@ -465,13 +465,7 @@
ubifs_assert(offs >= 0 && offs <= c->leb_size);
ubifs_assert(offs % c->min_io_size == 0 && !(offs & 7));
ubifs_assert(lnum != wbuf->lnum);
-
- if (wbuf->used > 0) {
- int err = ubifs_wbuf_sync_nolock(wbuf);
-
- if (err)
- return err;
- }
+ ubifs_assert(wbuf->used == 0);
spin_lock(&wbuf->lock);
wbuf->lnum = lnum;
@@ -573,7 +567,7 @@
int ubifs_wbuf_write_nolock(struct ubifs_wbuf *wbuf, void *buf, int len)
{
struct ubifs_info *c = wbuf->c;
- int err, written, n, aligned_len = ALIGN(len, 8), offs;
+ int err, written, n, aligned_len = ALIGN(len, 8);
dbg_io("%d bytes (%s) to jhead %s wbuf at LEB %d:%d", len,
dbg_ntype(((struct ubifs_ch *)buf)->node_type),
@@ -588,7 +582,7 @@
ubifs_assert(mutex_is_locked(&wbuf->io_mutex));
ubifs_assert(!c->ro_media && !c->ro_mount);
if (c->leb_size - wbuf->offs >= c->max_write_size)
- ubifs_assert(!((wbuf->offs + wbuf->size) % c->max_write_size ));
+ ubifs_assert(!((wbuf->offs + wbuf->size) % c->max_write_size));
if (c->leb_size - wbuf->offs - wbuf->used < aligned_len) {
err = -ENOSPC;
@@ -636,7 +630,6 @@
goto exit;
}
- offs = wbuf->offs;
written = 0;
if (wbuf->used) {
@@ -653,7 +646,7 @@
if (err)
goto out;
- offs += wbuf->size;
+ wbuf->offs += wbuf->size;
len -= wbuf->avail;
aligned_len -= wbuf->avail;
written += wbuf->avail;
@@ -672,7 +665,7 @@
if (err)
goto out;
- offs += wbuf->size;
+ wbuf->offs += wbuf->size;
len -= wbuf->size;
aligned_len -= wbuf->size;
written += wbuf->size;
@@ -687,12 +680,13 @@
n = aligned_len >> c->max_write_shift;
if (n) {
n <<= c->max_write_shift;
- dbg_io("write %d bytes to LEB %d:%d", n, wbuf->lnum, offs);
- err = ubi_leb_write(c->ubi, wbuf->lnum, buf + written, offs, n,
- wbuf->dtype);
+ dbg_io("write %d bytes to LEB %d:%d", n, wbuf->lnum,
+ wbuf->offs);
+ err = ubi_leb_write(c->ubi, wbuf->lnum, buf + written,
+ wbuf->offs, n, wbuf->dtype);
if (err)
goto out;
- offs += n;
+ wbuf->offs += n;
aligned_len -= n;
len -= n;
written += n;
@@ -707,7 +701,6 @@
*/
memcpy(wbuf->buf, buf + written, len);
- wbuf->offs = offs;
if (c->leb_size - wbuf->offs >= c->max_write_size)
wbuf->size = c->max_write_size;
else
diff --git a/fs/ubifs/journal.c b/fs/ubifs/journal.c
index aed25e8..34b1679 100644
--- a/fs/ubifs/journal.c
+++ b/fs/ubifs/journal.c
@@ -141,14 +141,8 @@
* LEB with some empty space.
*/
lnum = ubifs_find_free_space(c, len, &offs, squeeze);
- if (lnum >= 0) {
- /* Found an LEB, add it to the journal head */
- err = ubifs_add_bud_to_log(c, jhead, lnum, offs);
- if (err)
- goto out_return;
- /* A new bud was successfully allocated and added to the log */
+ if (lnum >= 0)
goto out;
- }
err = lnum;
if (err != -ENOSPC)
@@ -203,12 +197,23 @@
return 0;
}
- err = ubifs_add_bud_to_log(c, jhead, lnum, 0);
- if (err)
- goto out_return;
offs = 0;
out:
+ /*
+ * Make sure we synchronize the write-buffer before we add the new bud
+ * to the log. Otherwise we may have a power cut after the log
+ * reference node for the last bud (@lnum) is written but before the
+ * write-buffer data are written to the next-to-last bud
+ * (@wbuf->lnum). And the effect would be that the recovery would see
+ * that there is corruption in the next-to-last bud.
+ */
+ err = ubifs_wbuf_sync_nolock(wbuf);
+ if (err)
+ goto out_return;
+ err = ubifs_add_bud_to_log(c, jhead, lnum, offs);
+ if (err)
+ goto out_return;
err = ubifs_wbuf_seek_nolock(wbuf, lnum, offs, wbuf->dtype);
if (err)
goto out_unlock;
@@ -380,10 +385,8 @@
if (err == -ENOSPC) {
/* This are some budgeting problems, print useful information */
down_write(&c->commit_sem);
- spin_lock(&c->space_lock);
dbg_dump_stack();
- dbg_dump_budg(c);
- spin_unlock(&c->space_lock);
+ dbg_dump_budg(c, &c->bi);
dbg_dump_lprops(c);
cmt_retries = dbg_check_lprops(c);
up_write(&c->commit_sem);
diff --git a/fs/ubifs/log.c b/fs/ubifs/log.c
index 40fa780..affea94 100644
--- a/fs/ubifs/log.c
+++ b/fs/ubifs/log.c
@@ -100,20 +100,6 @@
}
/**
- * next_log_lnum - switch to the next log LEB.
- * @c: UBIFS file-system description object
- * @lnum: current log LEB
- */
-static inline int next_log_lnum(const struct ubifs_info *c, int lnum)
-{
- lnum += 1;
- if (lnum > c->log_last)
- lnum = UBIFS_LOG_LNUM;
-
- return lnum;
-}
-
-/**
* empty_log_bytes - calculate amount of empty space in the log.
* @c: UBIFS file-system description object
*/
@@ -257,7 +243,7 @@
ref->jhead = cpu_to_le32(jhead);
if (c->lhead_offs > c->leb_size - c->ref_node_alsz) {
- c->lhead_lnum = next_log_lnum(c, c->lhead_lnum);
+ c->lhead_lnum = ubifs_next_log_lnum(c, c->lhead_lnum);
c->lhead_offs = 0;
}
@@ -425,7 +411,7 @@
/* Switch to the next log LEB */
if (c->lhead_offs) {
- c->lhead_lnum = next_log_lnum(c, c->lhead_lnum);
+ c->lhead_lnum = ubifs_next_log_lnum(c, c->lhead_lnum);
c->lhead_offs = 0;
}
@@ -446,7 +432,7 @@
c->lhead_offs += len;
if (c->lhead_offs == c->leb_size) {
- c->lhead_lnum = next_log_lnum(c, c->lhead_lnum);
+ c->lhead_lnum = ubifs_next_log_lnum(c, c->lhead_lnum);
c->lhead_offs = 0;
}
@@ -533,7 +519,7 @@
}
mutex_lock(&c->log_mutex);
for (lnum = old_ltail_lnum; lnum != c->ltail_lnum;
- lnum = next_log_lnum(c, lnum)) {
+ lnum = ubifs_next_log_lnum(c, lnum)) {
dbg_log("unmap log LEB %d", lnum);
err = ubifs_leb_unmap(c, lnum);
if (err)
@@ -642,7 +628,7 @@
err = ubifs_leb_change(c, *lnum, buf, sz, UBI_SHORTTERM);
if (err)
return err;
- *lnum = next_log_lnum(c, *lnum);
+ *lnum = ubifs_next_log_lnum(c, *lnum);
*offs = 0;
}
memcpy(buf + *offs, node, len);
@@ -712,7 +698,7 @@
ubifs_scan_destroy(sleb);
if (lnum == c->lhead_lnum)
break;
- lnum = next_log_lnum(c, lnum);
+ lnum = ubifs_next_log_lnum(c, lnum);
}
if (offs) {
int sz = ALIGN(offs, c->min_io_size);
@@ -732,7 +718,7 @@
/* Unmap remaining LEBs */
lnum = write_lnum;
do {
- lnum = next_log_lnum(c, lnum);
+ lnum = ubifs_next_log_lnum(c, lnum);
err = ubifs_leb_unmap(c, lnum);
if (err)
return err;
diff --git a/fs/ubifs/lprops.c b/fs/ubifs/lprops.c
index 0ee0847..667884f 100644
--- a/fs/ubifs/lprops.c
+++ b/fs/ubifs/lprops.c
@@ -1007,21 +1007,11 @@
}
/**
- * struct scan_check_data - data provided to scan callback function.
- * @lst: LEB properties statistics
- * @err: error code
- */
-struct scan_check_data {
- struct ubifs_lp_stats lst;
- int err;
-};
-
-/**
* scan_check_cb - scan callback.
* @c: the UBIFS file-system description object
* @lp: LEB properties to scan
* @in_tree: whether the LEB properties are in main memory
- * @data: information passed to and from the caller of the scan
+ * @lst: lprops statistics to update
*
* This function returns a code that indicates whether the scan should continue
* (%LPT_SCAN_CONTINUE), whether the LEB properties should be added to the tree
@@ -1030,11 +1020,10 @@
*/
static int scan_check_cb(struct ubifs_info *c,
const struct ubifs_lprops *lp, int in_tree,
- struct scan_check_data *data)
+ struct ubifs_lp_stats *lst)
{
struct ubifs_scan_leb *sleb;
struct ubifs_scan_node *snod;
- struct ubifs_lp_stats *lst = &data->lst;
int cat, lnum = lp->lnum, is_idx = 0, used = 0, free, dirty, ret;
void *buf = NULL;
@@ -1044,7 +1033,7 @@
if (cat != (lp->flags & LPROPS_CAT_MASK)) {
ubifs_err("bad LEB category %d expected %d",
(lp->flags & LPROPS_CAT_MASK), cat);
- goto out;
+ return -EINVAL;
}
}
@@ -1078,7 +1067,7 @@
}
if (!found) {
ubifs_err("bad LPT list (category %d)", cat);
- goto out;
+ return -EINVAL;
}
}
}
@@ -1090,45 +1079,40 @@
if ((lp->hpos != -1 && heap->arr[lp->hpos]->lnum != lnum) ||
lp != heap->arr[lp->hpos]) {
ubifs_err("bad LPT heap (category %d)", cat);
- goto out;
+ return -EINVAL;
}
}
buf = __vmalloc(c->leb_size, GFP_NOFS, PAGE_KERNEL);
- if (!buf) {
- ubifs_err("cannot allocate memory to scan LEB %d", lnum);
- goto out;
+ if (!buf)
+ return -ENOMEM;
+
+ /*
+ * After an unclean unmount, empty and freeable LEBs
+ * may contain garbage - do not scan them.
+ */
+ if (lp->free == c->leb_size) {
+ lst->empty_lebs += 1;
+ lst->total_free += c->leb_size;
+ lst->total_dark += ubifs_calc_dark(c, c->leb_size);
+ return LPT_SCAN_CONTINUE;
+ }
+ if (lp->free + lp->dirty == c->leb_size &&
+ !(lp->flags & LPROPS_INDEX)) {
+ lst->total_free += lp->free;
+ lst->total_dirty += lp->dirty;
+ lst->total_dark += ubifs_calc_dark(c, c->leb_size);
+ return LPT_SCAN_CONTINUE;
}
sleb = ubifs_scan(c, lnum, 0, buf, 0);
if (IS_ERR(sleb)) {
- /*
- * After an unclean unmount, empty and freeable LEBs
- * may contain garbage.
- */
- if (lp->free == c->leb_size) {
- ubifs_err("scan errors were in empty LEB "
- "- continuing checking");
- lst->empty_lebs += 1;
- lst->total_free += c->leb_size;
- lst->total_dark += ubifs_calc_dark(c, c->leb_size);
- ret = LPT_SCAN_CONTINUE;
- goto exit;
+ ret = PTR_ERR(sleb);
+ if (ret == -EUCLEAN) {
+ dbg_dump_lprops(c);
+ dbg_dump_budg(c, &c->bi);
}
-
- if (lp->free + lp->dirty == c->leb_size &&
- !(lp->flags & LPROPS_INDEX)) {
- ubifs_err("scan errors were in freeable LEB "
- "- continuing checking");
- lst->total_free += lp->free;
- lst->total_dirty += lp->dirty;
- lst->total_dark += ubifs_calc_dark(c, c->leb_size);
- ret = LPT_SCAN_CONTINUE;
- goto exit;
- }
- data->err = PTR_ERR(sleb);
- ret = LPT_SCAN_STOP;
- goto exit;
+ goto out;
}
is_idx = -1;
@@ -1246,10 +1230,8 @@
}
ubifs_scan_destroy(sleb);
- ret = LPT_SCAN_CONTINUE;
-exit:
vfree(buf);
- return ret;
+ return LPT_SCAN_CONTINUE;
out_print:
ubifs_err("bad accounting of LEB %d: free %d, dirty %d flags %#x, "
@@ -1258,10 +1240,10 @@
dbg_dump_leb(c, lnum);
out_destroy:
ubifs_scan_destroy(sleb);
+ ret = -EINVAL;
out:
vfree(buf);
- data->err = -EINVAL;
- return LPT_SCAN_STOP;
+ return ret;
}
/**
@@ -1278,8 +1260,7 @@
int dbg_check_lprops(struct ubifs_info *c)
{
int i, err;
- struct scan_check_data data;
- struct ubifs_lp_stats *lst = &data.lst;
+ struct ubifs_lp_stats lst;
if (!(ubifs_chk_flags & UBIFS_CHK_LPROPS))
return 0;
@@ -1294,29 +1275,23 @@
return err;
}
- memset(lst, 0, sizeof(struct ubifs_lp_stats));
-
- data.err = 0;
+ memset(&lst, 0, sizeof(struct ubifs_lp_stats));
err = ubifs_lpt_scan_nolock(c, c->main_first, c->leb_cnt - 1,
(ubifs_lpt_scan_callback)scan_check_cb,
- &data);
+ &lst);
if (err && err != -ENOSPC)
goto out;
- if (data.err) {
- err = data.err;
- goto out;
- }
- if (lst->empty_lebs != c->lst.empty_lebs ||
- lst->idx_lebs != c->lst.idx_lebs ||
- lst->total_free != c->lst.total_free ||
- lst->total_dirty != c->lst.total_dirty ||
- lst->total_used != c->lst.total_used) {
+ if (lst.empty_lebs != c->lst.empty_lebs ||
+ lst.idx_lebs != c->lst.idx_lebs ||
+ lst.total_free != c->lst.total_free ||
+ lst.total_dirty != c->lst.total_dirty ||
+ lst.total_used != c->lst.total_used) {
ubifs_err("bad overall accounting");
ubifs_err("calculated: empty_lebs %d, idx_lebs %d, "
"total_free %lld, total_dirty %lld, total_used %lld",
- lst->empty_lebs, lst->idx_lebs, lst->total_free,
- lst->total_dirty, lst->total_used);
+ lst.empty_lebs, lst.idx_lebs, lst.total_free,
+ lst.total_dirty, lst.total_used);
ubifs_err("read from lprops: empty_lebs %d, idx_lebs %d, "
"total_free %lld, total_dirty %lld, total_used %lld",
c->lst.empty_lebs, c->lst.idx_lebs, c->lst.total_free,
@@ -1325,11 +1300,11 @@
goto out;
}
- if (lst->total_dead != c->lst.total_dead ||
- lst->total_dark != c->lst.total_dark) {
+ if (lst.total_dead != c->lst.total_dead ||
+ lst.total_dark != c->lst.total_dark) {
ubifs_err("bad dead/dark space accounting");
ubifs_err("calculated: total_dead %lld, total_dark %lld",
- lst->total_dead, lst->total_dark);
+ lst.total_dead, lst.total_dark);
ubifs_err("read from lprops: total_dead %lld, total_dark %lld",
c->lst.total_dead, c->lst.total_dark);
err = -EINVAL;
diff --git a/fs/ubifs/lpt_commit.c b/fs/ubifs/lpt_commit.c
index 0c9c69b..dfcb574 100644
--- a/fs/ubifs/lpt_commit.c
+++ b/fs/ubifs/lpt_commit.c
@@ -29,6 +29,12 @@
#include <linux/slab.h>
#include "ubifs.h"
+#ifdef CONFIG_UBIFS_FS_DEBUG
+static int dbg_populate_lsave(struct ubifs_info *c);
+#else
+#define dbg_populate_lsave(c) 0
+#endif
+
/**
* first_dirty_cnode - find first dirty cnode.
* @c: UBIFS file-system description object
@@ -586,7 +592,7 @@
if (nnode->nbranch[iip].lnum)
break;
}
- } while (iip >= UBIFS_LPT_FANOUT);
+ } while (iip >= UBIFS_LPT_FANOUT);
/* Go right */
nnode = ubifs_get_nnode(c, nnode, iip);
@@ -815,6 +821,10 @@
c->lpt_drty_flgs |= LSAVE_DIRTY;
ubifs_add_lpt_dirt(c, c->lsave_lnum, c->lsave_sz);
}
+
+ if (dbg_populate_lsave(c))
+ return;
+
list_for_each_entry(lprops, &c->empty_list, list) {
c->lsave[cnt++] = lprops->lnum;
if (cnt >= c->lsave_cnt)
@@ -1994,4 +2004,47 @@
current->pid);
}
+/**
+ * dbg_populate_lsave - debugging version of 'populate_lsave()'
+ * @c: UBIFS file-system description object
+ *
+ * This is a debugging version for 'populate_lsave()' which populates lsave
+ * with random LEBs instead of useful LEBs, which is good for test coverage.
+ * Returns zero if lsave has not been populated (this debugging feature is
+ * disabled) an non-zero if lsave has been populated.
+ */
+static int dbg_populate_lsave(struct ubifs_info *c)
+{
+ struct ubifs_lprops *lprops;
+ struct ubifs_lpt_heap *heap;
+ int i;
+
+ if (!(ubifs_chk_flags & UBIFS_CHK_GEN))
+ return 0;
+ if (random32() & 3)
+ return 0;
+
+ for (i = 0; i < c->lsave_cnt; i++)
+ c->lsave[i] = c->main_first;
+
+ list_for_each_entry(lprops, &c->empty_list, list)
+ c->lsave[random32() % c->lsave_cnt] = lprops->lnum;
+ list_for_each_entry(lprops, &c->freeable_list, list)
+ c->lsave[random32() % c->lsave_cnt] = lprops->lnum;
+ list_for_each_entry(lprops, &c->frdi_idx_list, list)
+ c->lsave[random32() % c->lsave_cnt] = lprops->lnum;
+
+ heap = &c->lpt_heap[LPROPS_DIRTY_IDX - 1];
+ for (i = 0; i < heap->cnt; i++)
+ c->lsave[random32() % c->lsave_cnt] = heap->arr[i]->lnum;
+ heap = &c->lpt_heap[LPROPS_DIRTY - 1];
+ for (i = 0; i < heap->cnt; i++)
+ c->lsave[random32() % c->lsave_cnt] = heap->arr[i]->lnum;
+ heap = &c->lpt_heap[LPROPS_FREE - 1];
+ for (i = 0; i < heap->cnt; i++)
+ c->lsave[random32() % c->lsave_cnt] = heap->arr[i]->lnum;
+
+ return 1;
+}
+
#endif /* CONFIG_UBIFS_FS_DEBUG */
diff --git a/fs/ubifs/master.c b/fs/ubifs/master.c
index 21f47af..278c238 100644
--- a/fs/ubifs/master.c
+++ b/fs/ubifs/master.c
@@ -148,7 +148,7 @@
}
main_sz = (long long)c->main_lebs * c->leb_size;
- if (c->old_idx_sz & 7 || c->old_idx_sz >= main_sz) {
+ if (c->bi.old_idx_sz & 7 || c->bi.old_idx_sz >= main_sz) {
err = 9;
goto out;
}
@@ -218,7 +218,7 @@
}
if (c->lst.total_dead + c->lst.total_dark +
- c->lst.total_used + c->old_idx_sz > main_sz) {
+ c->lst.total_used + c->bi.old_idx_sz > main_sz) {
err = 21;
goto out;
}
@@ -286,7 +286,7 @@
c->gc_lnum = le32_to_cpu(c->mst_node->gc_lnum);
c->ihead_lnum = le32_to_cpu(c->mst_node->ihead_lnum);
c->ihead_offs = le32_to_cpu(c->mst_node->ihead_offs);
- c->old_idx_sz = le64_to_cpu(c->mst_node->index_size);
+ c->bi.old_idx_sz = le64_to_cpu(c->mst_node->index_size);
c->lpt_lnum = le32_to_cpu(c->mst_node->lpt_lnum);
c->lpt_offs = le32_to_cpu(c->mst_node->lpt_offs);
c->nhead_lnum = le32_to_cpu(c->mst_node->nhead_lnum);
@@ -305,7 +305,7 @@
c->lst.total_dead = le64_to_cpu(c->mst_node->total_dead);
c->lst.total_dark = le64_to_cpu(c->mst_node->total_dark);
- c->calc_idx_sz = c->old_idx_sz;
+ c->calc_idx_sz = c->bi.old_idx_sz;
if (c->mst_node->flags & cpu_to_le32(UBIFS_MST_NO_ORPHS))
c->no_orphs = 1;
diff --git a/fs/ubifs/misc.h b/fs/ubifs/misc.h
index c3de04d..0b5296a 100644
--- a/fs/ubifs/misc.h
+++ b/fs/ubifs/misc.h
@@ -340,4 +340,21 @@
mutex_unlock(&c->lp_mutex);
}
+/**
+ * ubifs_next_log_lnum - switch to the next log LEB.
+ * @c: UBIFS file-system description object
+ * @lnum: current log LEB
+ *
+ * This helper function returns the log LEB number which goes next after LEB
+ * 'lnum'.
+ */
+static inline int ubifs_next_log_lnum(const struct ubifs_info *c, int lnum)
+{
+ lnum += 1;
+ if (lnum > c->log_last)
+ lnum = UBIFS_LOG_LNUM;
+
+ return lnum;
+}
+
#endif /* __UBIFS_MISC_H__ */
diff --git a/fs/ubifs/orphan.c b/fs/ubifs/orphan.c
index 09df318..bd644bf 100644
--- a/fs/ubifs/orphan.c
+++ b/fs/ubifs/orphan.c
@@ -673,7 +673,8 @@
sleb = ubifs_scan(c, lnum, 0, c->sbuf, 1);
if (IS_ERR(sleb)) {
if (PTR_ERR(sleb) == -EUCLEAN)
- sleb = ubifs_recover_leb(c, lnum, 0, c->sbuf, 0);
+ sleb = ubifs_recover_leb(c, lnum, 0,
+ c->sbuf, 0);
if (IS_ERR(sleb)) {
err = PTR_ERR(sleb);
break;
diff --git a/fs/ubifs/recovery.c b/fs/ubifs/recovery.c
index 3dbad6f..731d9e2 100644
--- a/fs/ubifs/recovery.c
+++ b/fs/ubifs/recovery.c
@@ -564,13 +564,16 @@
}
/**
- * drop_incomplete_group - drop nodes from an incomplete group.
+ * drop_last_node - drop the last node or group of nodes.
* @sleb: scanned LEB information
* @offs: offset of dropped nodes is returned here
+ * @grouped: non-zero if whole group of nodes have to be dropped
*
- * This function returns %1 if nodes are dropped and %0 otherwise.
+ * This is a helper function for 'ubifs_recover_leb()' which drops the last
+ * node of the scanned LEB or the last group of nodes if @grouped is not zero.
+ * This function returns %1 if a node was dropped and %0 otherwise.
*/
-static int drop_incomplete_group(struct ubifs_scan_leb *sleb, int *offs)
+static int drop_last_node(struct ubifs_scan_leb *sleb, int *offs, int grouped)
{
int dropped = 0;
@@ -589,6 +592,8 @@
kfree(snod);
sleb->nodes_cnt -= 1;
dropped = 1;
+ if (!grouped)
+ break;
}
return dropped;
}
@@ -609,8 +614,7 @@
struct ubifs_scan_leb *ubifs_recover_leb(struct ubifs_info *c, int lnum,
int offs, void *sbuf, int grouped)
{
- int err, len = c->leb_size - offs, need_clean = 0, quiet = 1;
- int empty_chkd = 0, start = offs;
+ int ret = 0, err, len = c->leb_size - offs, start = offs, min_io_unit;
struct ubifs_scan_leb *sleb;
void *buf = sbuf + offs;
@@ -620,12 +624,8 @@
if (IS_ERR(sleb))
return sleb;
- if (sleb->ecc)
- need_clean = 1;
-
+ ubifs_assert(len >= 8);
while (len >= 8) {
- int ret;
-
dbg_scan("look at LEB %d:%d (%d bytes left)",
lnum, offs, len);
@@ -635,8 +635,7 @@
* Scan quietly until there is an error from which we cannot
* recover
*/
- ret = ubifs_scan_a_node(c, buf, len, lnum, offs, quiet);
-
+ ret = ubifs_scan_a_node(c, buf, len, lnum, offs, 0);
if (ret == SCANNED_A_NODE) {
/* A valid node, and not a padding node */
struct ubifs_ch *ch = buf;
@@ -649,70 +648,32 @@
offs += node_len;
buf += node_len;
len -= node_len;
- continue;
- }
-
- if (ret > 0) {
+ } else if (ret > 0) {
/* Padding bytes or a valid padding node */
offs += ret;
buf += ret;
len -= ret;
- continue;
- }
-
- if (ret == SCANNED_EMPTY_SPACE) {
- if (!is_empty(buf, len)) {
- if (!is_last_write(c, buf, offs))
- break;
- clean_buf(c, &buf, lnum, &offs, &len);
- need_clean = 1;
- }
- empty_chkd = 1;
+ } else if (ret == SCANNED_EMPTY_SPACE ||
+ ret == SCANNED_GARBAGE ||
+ ret == SCANNED_A_BAD_PAD_NODE ||
+ ret == SCANNED_A_CORRUPT_NODE) {
+ dbg_rcvry("found corruption - %d", ret);
break;
- }
-
- if (ret == SCANNED_GARBAGE || ret == SCANNED_A_BAD_PAD_NODE)
- if (is_last_write(c, buf, offs)) {
- clean_buf(c, &buf, lnum, &offs, &len);
- need_clean = 1;
- empty_chkd = 1;
- break;
- }
-
- if (ret == SCANNED_A_CORRUPT_NODE)
- if (no_more_nodes(c, buf, len, lnum, offs)) {
- clean_buf(c, &buf, lnum, &offs, &len);
- need_clean = 1;
- empty_chkd = 1;
- break;
- }
-
- if (quiet) {
- /* Redo the last scan but noisily */
- quiet = 0;
- continue;
- }
-
- switch (ret) {
- case SCANNED_GARBAGE:
- dbg_err("garbage");
- goto corrupted;
- case SCANNED_A_CORRUPT_NODE:
- case SCANNED_A_BAD_PAD_NODE:
- dbg_err("bad node");
- goto corrupted;
- default:
- dbg_err("unknown");
+ } else {
+ dbg_err("unexpected return value %d", ret);
err = -EINVAL;
goto error;
}
}
- if (!empty_chkd && !is_empty(buf, len)) {
- if (is_last_write(c, buf, offs)) {
- clean_buf(c, &buf, lnum, &offs, &len);
- need_clean = 1;
- } else {
+ if (ret == SCANNED_GARBAGE || ret == SCANNED_A_BAD_PAD_NODE) {
+ if (!is_last_write(c, buf, offs))
+ goto corrupted_rescan;
+ } else if (ret == SCANNED_A_CORRUPT_NODE) {
+ if (!no_more_nodes(c, buf, len, lnum, offs))
+ goto corrupted_rescan;
+ } else if (!is_empty(buf, len)) {
+ if (!is_last_write(c, buf, offs)) {
int corruption = first_non_ff(buf, len);
/*
@@ -728,29 +689,82 @@
}
}
- /* Drop nodes from incomplete group */
- if (grouped && drop_incomplete_group(sleb, &offs)) {
- buf = sbuf + offs;
- len = c->leb_size - offs;
- clean_buf(c, &buf, lnum, &offs, &len);
- need_clean = 1;
- }
+ min_io_unit = round_down(offs, c->min_io_size);
+ if (grouped)
+ /*
+ * If nodes are grouped, always drop the incomplete group at
+ * the end.
+ */
+ drop_last_node(sleb, &offs, 1);
- if (offs % c->min_io_size) {
- clean_buf(c, &buf, lnum, &offs, &len);
- need_clean = 1;
- }
+ /*
+ * While we are in the middle of the same min. I/O unit keep dropping
+ * nodes. So basically, what we want is to make sure that the last min.
+ * I/O unit where we saw the corruption is dropped completely with all
+ * the uncorrupted node which may possibly sit there.
+ *
+ * In other words, let's name the min. I/O unit where the corruption
+ * starts B, and the previous min. I/O unit A. The below code tries to
+ * deal with a situation when half of B contains valid nodes or the end
+ * of a valid node, and the second half of B contains corrupted data or
+ * garbage. This means that UBIFS had been writing to B just before the
+ * power cut happened. I do not know how realistic is this scenario
+ * that half of the min. I/O unit had been written successfully and the
+ * other half not, but this is possible in our 'failure mode emulation'
+ * infrastructure at least.
+ *
+ * So what is the problem, why we need to drop those nodes? Whey can't
+ * we just clean-up the second half of B by putting a padding node
+ * there? We can, and this works fine with one exception which was
+ * reproduced with power cut emulation testing and happens extremely
+ * rarely. The description follows, but it is worth noting that that is
+ * only about the GC head, so we could do this trick only if the bud
+ * belongs to the GC head, but it does not seem to be worth an
+ * additional "if" statement.
+ *
+ * So, imagine the file-system is full, we run GC which is moving valid
+ * nodes from LEB X to LEB Y (obviously, LEB Y is the current GC head
+ * LEB). The @c->gc_lnum is -1, which means that GC will retain LEB X
+ * and will try to continue. Imagine that LEB X is currently the
+ * dirtiest LEB, and the amount of used space in LEB Y is exactly the
+ * same as amount of free space in LEB X.
+ *
+ * And a power cut happens when nodes are moved from LEB X to LEB Y. We
+ * are here trying to recover LEB Y which is the GC head LEB. We find
+ * the min. I/O unit B as described above. Then we clean-up LEB Y by
+ * padding min. I/O unit. And later 'ubifs_rcvry_gc_commit()' function
+ * fails, because it cannot find a dirty LEB which could be GC'd into
+ * LEB Y! Even LEB X does not match because the amount of valid nodes
+ * there does not fit the free space in LEB Y any more! And this is
+ * because of the padding node which we added to LEB Y. The
+ * user-visible effect of this which I once observed and analysed is
+ * that we cannot mount the file-system with -ENOSPC error.
+ *
+ * So obviously, to make sure that situation does not happen we should
+ * free min. I/O unit B in LEB Y completely and the last used min. I/O
+ * unit in LEB Y should be A. This is basically what the below code
+ * tries to do.
+ */
+ while (min_io_unit == round_down(offs, c->min_io_size) &&
+ min_io_unit != offs &&
+ drop_last_node(sleb, &offs, grouped));
+ buf = sbuf + offs;
+ len = c->leb_size - offs;
+
+ clean_buf(c, &buf, lnum, &offs, &len);
ubifs_end_scan(c, sleb, lnum, offs);
- if (need_clean) {
- err = fix_unclean_leb(c, sleb, start);
- if (err)
- goto error;
- }
+ err = fix_unclean_leb(c, sleb, start);
+ if (err)
+ goto error;
return sleb;
+corrupted_rescan:
+ /* Re-scan the corrupted data with verbose messages */
+ dbg_err("corruptio %d", ret);
+ ubifs_scan_a_node(c, buf, len, lnum, offs, 1);
corrupted:
ubifs_scanned_corruption(c, lnum, offs, buf);
err = -EUCLEAN;
@@ -1070,6 +1084,53 @@
}
/**
+ * grab_empty_leb - grab an empty LEB to use as GC LEB and run commit.
+ * @c: UBIFS file-system description object
+ *
+ * This is a helper function for 'ubifs_rcvry_gc_commit()' which grabs an empty
+ * LEB to be used as GC LEB (@c->gc_lnum), and then runs the commit. Returns
+ * zero in case of success and a negative error code in case of failure.
+ */
+static int grab_empty_leb(struct ubifs_info *c)
+{
+ int lnum, err;
+
+ /*
+ * Note, it is very important to first search for an empty LEB and then
+ * run the commit, not vice-versa. The reason is that there might be
+ * only one empty LEB at the moment, the one which has been the
+ * @c->gc_lnum just before the power cut happened. During the regular
+ * UBIFS operation (not now) @c->gc_lnum is marked as "taken", so no
+ * one but GC can grab it. But at this moment this single empty LEB is
+ * not marked as taken, so if we run commit - what happens? Right, the
+ * commit will grab it and write the index there. Remember that the
+ * index always expands as long as there is free space, and it only
+ * starts consolidating when we run out of space.
+ *
+ * IOW, if we run commit now, we might not be able to find a free LEB
+ * after this.
+ */
+ lnum = ubifs_find_free_leb_for_idx(c);
+ if (lnum < 0) {
+ dbg_err("could not find an empty LEB");
+ dbg_dump_lprops(c);
+ dbg_dump_budg(c, &c->bi);
+ return lnum;
+ }
+
+ /* Reset the index flag */
+ err = ubifs_change_one_lp(c, lnum, LPROPS_NC, LPROPS_NC, 0,
+ LPROPS_INDEX, 0);
+ if (err)
+ return err;
+
+ c->gc_lnum = lnum;
+ dbg_rcvry("found empty LEB %d, run commit", lnum);
+
+ return ubifs_run_commit(c);
+}
+
+/**
* ubifs_rcvry_gc_commit - recover the GC LEB number and run the commit.
* @c: UBIFS file-system description object
*
@@ -1091,71 +1152,26 @@
{
struct ubifs_wbuf *wbuf = &c->jheads[GCHD].wbuf;
struct ubifs_lprops lp;
- int lnum, err;
+ int err;
+
+ dbg_rcvry("GC head LEB %d, offs %d", wbuf->lnum, wbuf->offs);
c->gc_lnum = -1;
- if (wbuf->lnum == -1) {
- dbg_rcvry("no GC head LEB");
- goto find_free;
- }
- /*
- * See whether the used space in the dirtiest LEB fits in the GC head
- * LEB.
- */
- if (wbuf->offs == c->leb_size) {
- dbg_rcvry("no room in GC head LEB");
- goto find_free;
- }
+ if (wbuf->lnum == -1 || wbuf->offs == c->leb_size)
+ return grab_empty_leb(c);
+
err = ubifs_find_dirty_leb(c, &lp, wbuf->offs, 2);
if (err) {
- /*
- * There are no dirty or empty LEBs subject to here being
- * enough for the index. Try to use
- * 'ubifs_find_free_leb_for_idx()', which will return any empty
- * LEBs (ignoring index requirements). If the index then
- * doesn't have enough LEBs the recovery commit will fail -
- * which is the same result anyway i.e. recovery fails. So
- * there is no problem ignoring index requirements and just
- * grabbing a free LEB since we have already established there
- * is not a dirty LEB we could have used instead.
- */
- if (err == -ENOSPC) {
- dbg_rcvry("could not find a dirty LEB");
- goto find_free;
- }
- return err;
+ if (err != -ENOSPC)
+ return err;
+
+ dbg_rcvry("could not find a dirty LEB");
+ return grab_empty_leb(c);
}
+
ubifs_assert(!(lp.flags & LPROPS_INDEX));
- lnum = lp.lnum;
- if (lp.free + lp.dirty == c->leb_size) {
- /* An empty LEB was returned */
- if (lp.free != c->leb_size) {
- err = ubifs_change_one_lp(c, lnum, c->leb_size,
- 0, 0, 0, 0);
- if (err)
- return err;
- }
- err = ubifs_leb_unmap(c, lnum);
- if (err)
- return err;
- c->gc_lnum = lnum;
- dbg_rcvry("allocated LEB %d for GC", lnum);
- /* Run the commit */
- dbg_rcvry("committing");
- return ubifs_run_commit(c);
- }
- /*
- * There was no empty LEB so the used space in the dirtiest LEB must fit
- * in the GC head LEB.
- */
- if (lp.free + lp.dirty < wbuf->offs) {
- dbg_rcvry("LEB %d doesn't fit in GC head LEB %d:%d",
- lnum, wbuf->lnum, wbuf->offs);
- err = ubifs_return_leb(c, lnum);
- if (err)
- return err;
- goto find_free;
- }
+ ubifs_assert(lp.free + lp.dirty >= wbuf->offs);
+
/*
* We run the commit before garbage collection otherwise subsequent
* mounts will see the GC and orphan deletion in a different order.
@@ -1164,11 +1180,8 @@
err = ubifs_run_commit(c);
if (err)
return err;
- /*
- * The data in the dirtiest LEB fits in the GC head LEB, so do the GC
- * - use locking to keep 'ubifs_assert()' happy.
- */
- dbg_rcvry("GC'ing LEB %d", lnum);
+
+ dbg_rcvry("GC'ing LEB %d", lp.lnum);
mutex_lock_nested(&wbuf->io_mutex, wbuf->jhead);
err = ubifs_garbage_collect_leb(c, &lp);
if (err >= 0) {
@@ -1184,37 +1197,17 @@
err = -EINVAL;
return err;
}
- if (err != LEB_RETAINED) {
- dbg_err("GC returned %d", err);
+
+ ubifs_assert(err == LEB_RETAINED);
+ if (err != LEB_RETAINED)
return -EINVAL;
- }
+
err = ubifs_leb_unmap(c, c->gc_lnum);
if (err)
return err;
- dbg_rcvry("allocated LEB %d for GC", lnum);
- return 0;
-find_free:
- /*
- * There is no GC head LEB or the free space in the GC head LEB is too
- * small, or there are not dirty LEBs. Allocate gc_lnum by calling
- * 'ubifs_find_free_leb_for_idx()' so GC is not run.
- */
- lnum = ubifs_find_free_leb_for_idx(c);
- if (lnum < 0) {
- dbg_err("could not find an empty LEB");
- return lnum;
- }
- /* And reset the index flag */
- err = ubifs_change_one_lp(c, lnum, LPROPS_NC, LPROPS_NC, 0,
- LPROPS_INDEX, 0);
- if (err)
- return err;
- c->gc_lnum = lnum;
- dbg_rcvry("allocated LEB %d for GC", lnum);
- /* Run the commit */
- dbg_rcvry("committing");
- return ubifs_run_commit(c);
+ dbg_rcvry("allocated LEB %d for GC", lp.lnum);
+ return 0;
}
/**
@@ -1456,7 +1449,7 @@
err = ubi_leb_change(c->ubi, lnum, c->sbuf, len, UBI_UNKNOWN);
if (err)
goto out;
- dbg_rcvry("inode %lu at %d:%d size %lld -> %lld ",
+ dbg_rcvry("inode %lu at %d:%d size %lld -> %lld",
(unsigned long)e->inum, lnum, offs, i_size, e->d_size);
return 0;
@@ -1505,20 +1498,27 @@
e->i_size = le64_to_cpu(ino->size);
}
}
+
if (e->exists && e->i_size < e->d_size) {
- if (!e->inode && c->ro_mount) {
+ if (c->ro_mount) {
/* Fix the inode size and pin it in memory */
struct inode *inode;
+ struct ubifs_inode *ui;
+
+ ubifs_assert(!e->inode);
inode = ubifs_iget(c->vfs_sb, e->inum);
if (IS_ERR(inode))
return PTR_ERR(inode);
+
+ ui = ubifs_inode(inode);
if (inode->i_size < e->d_size) {
dbg_rcvry("ino %lu size %lld -> %lld",
(unsigned long)e->inum,
- e->d_size, inode->i_size);
+ inode->i_size, e->d_size);
inode->i_size = e->d_size;
- ubifs_inode(inode)->ui_size = e->d_size;
+ ui->ui_size = e->d_size;
+ ui->synced_i_size = e->d_size;
e->inode = inode;
this = rb_next(this);
continue;
@@ -1533,9 +1533,11 @@
iput(e->inode);
}
}
+
this = rb_next(this);
rb_erase(&e->rb, &c->size_tree);
kfree(e);
}
+
return 0;
}
diff --git a/fs/ubifs/replay.c b/fs/ubifs/replay.c
index d3d6d36..6617280 100644
--- a/fs/ubifs/replay.c
+++ b/fs/ubifs/replay.c
@@ -33,44 +33,32 @@
*/
#include "ubifs.h"
-
-/*
- * Replay flags.
- *
- * REPLAY_DELETION: node was deleted
- * REPLAY_REF: node is a reference node
- */
-enum {
- REPLAY_DELETION = 1,
- REPLAY_REF = 2,
-};
+#include <linux/list_sort.h>
/**
- * struct replay_entry - replay tree entry.
+ * struct replay_entry - replay list entry.
* @lnum: logical eraseblock number of the node
* @offs: node offset
* @len: node length
+ * @deletion: non-zero if this entry corresponds to a node deletion
* @sqnum: node sequence number
- * @flags: replay flags
- * @rb: links the replay tree
+ * @list: links the replay list
* @key: node key
* @nm: directory entry name
* @old_size: truncation old size
* @new_size: truncation new size
- * @free: amount of free space in a bud
- * @dirty: amount of dirty space in a bud from padding and deletion nodes
- * @jhead: journal head number of the bud
*
- * UBIFS journal replay must compare node sequence numbers, which means it must
- * build a tree of node information to insert into the TNC.
+ * The replay process first scans all buds and builds the replay list, then
+ * sorts the replay list in nodes sequence number order, and then inserts all
+ * the replay entries to the TNC.
*/
struct replay_entry {
int lnum;
int offs;
int len;
+ unsigned int deletion:1;
unsigned long long sqnum;
- int flags;
- struct rb_node rb;
+ struct list_head list;
union ubifs_key key;
union {
struct qstr nm;
@@ -78,11 +66,6 @@
loff_t old_size;
loff_t new_size;
};
- struct {
- int free;
- int dirty;
- int jhead;
- };
};
};
@@ -90,57 +73,64 @@
* struct bud_entry - entry in the list of buds to replay.
* @list: next bud in the list
* @bud: bud description object
- * @free: free bytes in the bud
* @sqnum: reference node sequence number
+ * @free: free bytes in the bud
+ * @dirty: dirty bytes in the bud
*/
struct bud_entry {
struct list_head list;
struct ubifs_bud *bud;
- int free;
unsigned long long sqnum;
+ int free;
+ int dirty;
};
/**
* set_bud_lprops - set free and dirty space used by a bud.
* @c: UBIFS file-system description object
- * @r: replay entry of bud
+ * @b: bud entry which describes the bud
+ *
+ * This function makes sure the LEB properties of bud @b are set correctly
+ * after the replay. Returns zero in case of success and a negative error code
+ * in case of failure.
*/
-static int set_bud_lprops(struct ubifs_info *c, struct replay_entry *r)
+static int set_bud_lprops(struct ubifs_info *c, struct bud_entry *b)
{
const struct ubifs_lprops *lp;
int err = 0, dirty;
ubifs_get_lprops(c);
- lp = ubifs_lpt_lookup_dirty(c, r->lnum);
+ lp = ubifs_lpt_lookup_dirty(c, b->bud->lnum);
if (IS_ERR(lp)) {
err = PTR_ERR(lp);
goto out;
}
dirty = lp->dirty;
- if (r->offs == 0 && (lp->free != c->leb_size || lp->dirty != 0)) {
+ if (b->bud->start == 0 && (lp->free != c->leb_size || lp->dirty != 0)) {
/*
* The LEB was added to the journal with a starting offset of
* zero which means the LEB must have been empty. The LEB
- * property values should be lp->free == c->leb_size and
- * lp->dirty == 0, but that is not the case. The reason is that
- * the LEB was garbage collected. The garbage collector resets
- * the free and dirty space without recording it anywhere except
- * lprops, so if there is not a commit then lprops does not have
- * that information next time the file system is mounted.
+ * property values should be @lp->free == @c->leb_size and
+ * @lp->dirty == 0, but that is not the case. The reason is that
+ * the LEB had been garbage collected before it became the bud,
+ * and there was not commit inbetween. The garbage collector
+ * resets the free and dirty space without recording it
+ * anywhere except lprops, so if there was no commit then
+ * lprops does not have that information.
*
* We do not need to adjust free space because the scan has told
* us the exact value which is recorded in the replay entry as
- * r->free.
+ * @b->free.
*
* However we do need to subtract from the dirty space the
* amount of space that the garbage collector reclaimed, which
* is the whole LEB minus the amount of space that was free.
*/
- dbg_mnt("bud LEB %d was GC'd (%d free, %d dirty)", r->lnum,
+ dbg_mnt("bud LEB %d was GC'd (%d free, %d dirty)", b->bud->lnum,
lp->free, lp->dirty);
- dbg_gc("bud LEB %d was GC'd (%d free, %d dirty)", r->lnum,
+ dbg_gc("bud LEB %d was GC'd (%d free, %d dirty)", b->bud->lnum,
lp->free, lp->dirty);
dirty -= c->leb_size - lp->free;
/*
@@ -152,10 +142,10 @@
*/
if (dirty != 0)
dbg_msg("LEB %d lp: %d free %d dirty "
- "replay: %d free %d dirty", r->lnum, lp->free,
- lp->dirty, r->free, r->dirty);
+ "replay: %d free %d dirty", b->bud->lnum,
+ lp->free, lp->dirty, b->free, b->dirty);
}
- lp = ubifs_change_lp(c, lp, r->free, dirty + r->dirty,
+ lp = ubifs_change_lp(c, lp, b->free, dirty + b->dirty,
lp->flags | LPROPS_TAKEN, 0);
if (IS_ERR(lp)) {
err = PTR_ERR(lp);
@@ -163,8 +153,9 @@
}
/* Make sure the journal head points to the latest bud */
- err = ubifs_wbuf_seek_nolock(&c->jheads[r->jhead].wbuf, r->lnum,
- c->leb_size - r->free, UBI_SHORTTERM);
+ err = ubifs_wbuf_seek_nolock(&c->jheads[b->bud->jhead].wbuf,
+ b->bud->lnum, c->leb_size - b->free,
+ UBI_SHORTTERM);
out:
ubifs_release_lprops(c);
@@ -172,6 +163,27 @@
}
/**
+ * set_buds_lprops - set free and dirty space for all replayed buds.
+ * @c: UBIFS file-system description object
+ *
+ * This function sets LEB properties for all replayed buds. Returns zero in
+ * case of success and a negative error code in case of failure.
+ */
+static int set_buds_lprops(struct ubifs_info *c)
+{
+ struct bud_entry *b;
+ int err;
+
+ list_for_each_entry(b, &c->replay_buds, list) {
+ err = set_bud_lprops(c, b);
+ if (err)
+ return err;
+ }
+
+ return 0;
+}
+
+/**
* trun_remove_range - apply a replay entry for a truncation to the TNC.
* @c: UBIFS file-system description object
* @r: replay entry of truncation
@@ -207,24 +219,22 @@
*/
static int apply_replay_entry(struct ubifs_info *c, struct replay_entry *r)
{
- int err, deletion = ((r->flags & REPLAY_DELETION) != 0);
+ int err;
- dbg_mnt("LEB %d:%d len %d flgs %d sqnum %llu %s", r->lnum,
- r->offs, r->len, r->flags, r->sqnum, DBGKEY(&r->key));
+ dbg_mnt("LEB %d:%d len %d deletion %d sqnum %llu %s", r->lnum,
+ r->offs, r->len, r->deletion, r->sqnum, DBGKEY(&r->key));
/* Set c->replay_sqnum to help deal with dangling branches. */
c->replay_sqnum = r->sqnum;
- if (r->flags & REPLAY_REF)
- err = set_bud_lprops(c, r);
- else if (is_hash_key(c, &r->key)) {
- if (deletion)
+ if (is_hash_key(c, &r->key)) {
+ if (r->deletion)
err = ubifs_tnc_remove_nm(c, &r->key, &r->nm);
else
err = ubifs_tnc_add_nm(c, &r->key, r->lnum, r->offs,
r->len, &r->nm);
} else {
- if (deletion)
+ if (r->deletion)
switch (key_type(c, &r->key)) {
case UBIFS_INO_KEY:
{
@@ -247,7 +257,7 @@
return err;
if (c->need_recovery)
- err = ubifs_recover_size_accum(c, &r->key, deletion,
+ err = ubifs_recover_size_accum(c, &r->key, r->deletion,
r->new_size);
}
@@ -255,68 +265,77 @@
}
/**
- * destroy_replay_tree - destroy the replay.
- * @c: UBIFS file-system description object
+ * replay_entries_cmp - compare 2 replay entries.
+ * @priv: UBIFS file-system description object
+ * @a: first replay entry
+ * @a: second replay entry
*
- * Destroy the replay tree.
+ * This is a comparios function for 'list_sort()' which compares 2 replay
+ * entries @a and @b by comparing their sequence numer. Returns %1 if @a has
+ * greater sequence number and %-1 otherwise.
*/
-static void destroy_replay_tree(struct ubifs_info *c)
+static int replay_entries_cmp(void *priv, struct list_head *a,
+ struct list_head *b)
{
- struct rb_node *this = c->replay_tree.rb_node;
- struct replay_entry *r;
+ struct replay_entry *ra, *rb;
- while (this) {
- if (this->rb_left) {
- this = this->rb_left;
- continue;
- } else if (this->rb_right) {
- this = this->rb_right;
- continue;
- }
- r = rb_entry(this, struct replay_entry, rb);
- this = rb_parent(this);
- if (this) {
- if (this->rb_left == &r->rb)
- this->rb_left = NULL;
- else
- this->rb_right = NULL;
- }
- if (is_hash_key(c, &r->key))
- kfree(r->nm.name);
- kfree(r);
- }
- c->replay_tree = RB_ROOT;
+ cond_resched();
+ if (a == b)
+ return 0;
+
+ ra = list_entry(a, struct replay_entry, list);
+ rb = list_entry(b, struct replay_entry, list);
+ ubifs_assert(ra->sqnum != rb->sqnum);
+ if (ra->sqnum > rb->sqnum)
+ return 1;
+ return -1;
}
/**
- * apply_replay_tree - apply the replay tree to the TNC.
+ * apply_replay_list - apply the replay list to the TNC.
* @c: UBIFS file-system description object
*
- * Apply the replay tree.
- * Returns zero in case of success and a negative error code in case of
- * failure.
+ * Apply all entries in the replay list to the TNC. Returns zero in case of
+ * success and a negative error code in case of failure.
*/
-static int apply_replay_tree(struct ubifs_info *c)
+static int apply_replay_list(struct ubifs_info *c)
{
- struct rb_node *this = rb_first(&c->replay_tree);
+ struct replay_entry *r;
+ int err;
- while (this) {
- struct replay_entry *r;
- int err;
+ list_sort(c, &c->replay_list, &replay_entries_cmp);
+ list_for_each_entry(r, &c->replay_list, list) {
cond_resched();
- r = rb_entry(this, struct replay_entry, rb);
err = apply_replay_entry(c, r);
if (err)
return err;
- this = rb_next(this);
}
+
return 0;
}
/**
- * insert_node - insert a node to the replay tree.
+ * destroy_replay_list - destroy the replay.
+ * @c: UBIFS file-system description object
+ *
+ * Destroy the replay list.
+ */
+static void destroy_replay_list(struct ubifs_info *c)
+{
+ struct replay_entry *r, *tmp;
+
+ list_for_each_entry_safe(r, tmp, &c->replay_list, list) {
+ if (is_hash_key(c, &r->key))
+ kfree(r->nm.name);
+ list_del(&r->list);
+ kfree(r);
+ }
+}
+
+/**
+ * insert_node - insert a node to the replay list
* @c: UBIFS file-system description object
* @lnum: node logical eraseblock number
* @offs: node offset
@@ -328,39 +347,25 @@
* @old_size: truncation old size
* @new_size: truncation new size
*
- * This function inserts a scanned non-direntry node to the replay tree. The
- * replay tree is an RB-tree containing @struct replay_entry elements which are
- * indexed by the sequence number. The replay tree is applied at the very end
- * of the replay process. Since the tree is sorted in sequence number order,
- * the older modifications are applied first. This function returns zero in
- * case of success and a negative error code in case of failure.
+ * This function inserts a scanned non-direntry node to the replay list. The
+ * replay list contains @struct replay_entry elements, and we sort this list in
+ * sequence number order before applying it. The replay list is applied at the
+ * very end of the replay process. Since the list is sorted in sequence number
+ * order, the older modifications are applied first. This function returns zero
+ * in case of success and a negative error code in case of failure.
*/
static int insert_node(struct ubifs_info *c, int lnum, int offs, int len,
union ubifs_key *key, unsigned long long sqnum,
int deletion, int *used, loff_t old_size,
loff_t new_size)
{
- struct rb_node **p = &c->replay_tree.rb_node, *parent = NULL;
struct replay_entry *r;
+ dbg_mnt("add LEB %d:%d, key %s", lnum, offs, DBGKEY(key));
+
if (key_inum(c, key) >= c->highest_inum)
c->highest_inum = key_inum(c, key);
- dbg_mnt("add LEB %d:%d, key %s", lnum, offs, DBGKEY(key));
- while (*p) {
- parent = *p;
- r = rb_entry(parent, struct replay_entry, rb);
- if (sqnum < r->sqnum) {
- p = &(*p)->rb_left;
- continue;
- } else if (sqnum > r->sqnum) {
- p = &(*p)->rb_right;
- continue;
- }
- ubifs_err("duplicate sqnum in replay");
- return -EINVAL;
- }
-
r = kzalloc(sizeof(struct replay_entry), GFP_KERNEL);
if (!r)
return -ENOMEM;
@@ -370,19 +375,18 @@
r->lnum = lnum;
r->offs = offs;
r->len = len;
+ r->deletion = !!deletion;
r->sqnum = sqnum;
- r->flags = (deletion ? REPLAY_DELETION : 0);
+ key_copy(c, key, &r->key);
r->old_size = old_size;
r->new_size = new_size;
- key_copy(c, key, &r->key);
- rb_link_node(&r->rb, parent, p);
- rb_insert_color(&r->rb, &c->replay_tree);
+ list_add_tail(&r->list, &c->replay_list);
return 0;
}
/**
- * insert_dent - insert a directory entry node into the replay tree.
+ * insert_dent - insert a directory entry node into the replay list.
* @c: UBIFS file-system description object
* @lnum: node logical eraseblock number
* @offs: node offset
@@ -394,43 +398,25 @@
* @deletion: non-zero if this is a deletion
* @used: number of bytes in use in a LEB
*
- * This function inserts a scanned directory entry node to the replay tree.
- * Returns zero in case of success and a negative error code in case of
- * failure.
- *
- * This function is also used for extended attribute entries because they are
- * implemented as directory entry nodes.
+ * This function inserts a scanned directory entry node or an extended
+ * attribute entry to the replay list. Returns zero in case of success and a
+ * negative error code in case of failure.
*/
static int insert_dent(struct ubifs_info *c, int lnum, int offs, int len,
union ubifs_key *key, const char *name, int nlen,
unsigned long long sqnum, int deletion, int *used)
{
- struct rb_node **p = &c->replay_tree.rb_node, *parent = NULL;
struct replay_entry *r;
char *nbuf;
+ dbg_mnt("add LEB %d:%d, key %s", lnum, offs, DBGKEY(key));
if (key_inum(c, key) >= c->highest_inum)
c->highest_inum = key_inum(c, key);
- dbg_mnt("add LEB %d:%d, key %s", lnum, offs, DBGKEY(key));
- while (*p) {
- parent = *p;
- r = rb_entry(parent, struct replay_entry, rb);
- if (sqnum < r->sqnum) {
- p = &(*p)->rb_left;
- continue;
- }
- if (sqnum > r->sqnum) {
- p = &(*p)->rb_right;
- continue;
- }
- ubifs_err("duplicate sqnum in replay");
- return -EINVAL;
- }
-
r = kzalloc(sizeof(struct replay_entry), GFP_KERNEL);
if (!r)
return -ENOMEM;
+
nbuf = kmalloc(nlen + 1, GFP_KERNEL);
if (!nbuf) {
kfree(r);
@@ -442,17 +428,15 @@
r->lnum = lnum;
r->offs = offs;
r->len = len;
+ r->deletion = !!deletion;
r->sqnum = sqnum;
+ key_copy(c, key, &r->key);
r->nm.len = nlen;
memcpy(nbuf, name, nlen);
nbuf[nlen] = '\0';
r->nm.name = nbuf;
- r->flags = (deletion ? REPLAY_DELETION : 0);
- key_copy(c, key, &r->key);
- ubifs_assert(!*p);
- rb_link_node(&r->rb, parent, p);
- rb_insert_color(&r->rb, &c->replay_tree);
+ list_add_tail(&r->list, &c->replay_list);
return 0;
}
@@ -489,29 +473,92 @@
}
/**
+ * is_last_bud - check if the bud is the last in the journal head.
+ * @c: UBIFS file-system description object
+ * @bud: bud description object
+ *
+ * This function checks if bud @bud is the last bud in its journal head. This
+ * information is then used by 'replay_bud()' to decide whether the bud can
+ * have corruptions or not. Indeed, only last buds can be corrupted by power
+ * cuts. Returns %1 if this is the last bud, and %0 if not.
+ */
+static int is_last_bud(struct ubifs_info *c, struct ubifs_bud *bud)
+{
+ struct ubifs_jhead *jh = &c->jheads[bud->jhead];
+ struct ubifs_bud *next;
+ uint32_t data;
+ int err;
+
+ if (list_is_last(&bud->list, &jh->buds_list))
+ return 1;
+
+ /*
+ * The following is a quirk to make sure we work correctly with UBIFS
+ * images used with older UBIFS.
+ *
+ * Normally, the last bud will be the last in the journal head's list
+ * of bud. However, there is one exception if the UBIFS image belongs
+ * to older UBIFS. This is fairly unlikely: one would need to use old
+ * UBIFS, then have a power cut exactly at the right point, and then
+ * try to mount this image with new UBIFS.
+ *
+ * The exception is: it is possible to have 2 buds A and B, A goes
+ * before B, and B is the last, bud B is contains no data, and bud A is
+ * corrupted at the end. The reason is that in older versions when the
+ * journal code switched the next bud (from A to B), it first added a
+ * log reference node for the new bud (B), and only after this it
+ * synchronized the write-buffer of current bud (A). But later this was
+ * changed and UBIFS started to always synchronize the write-buffer of
+ * the bud (A) before writing the log reference for the new bud (B).
+ *
+ * But because older UBIFS always synchronized A's write-buffer before
+ * writing to B, we can recognize this exceptional situation but
+ * checking the contents of bud B - if it is empty, then A can be
+ * treated as the last and we can recover it.
+ *
+ * TODO: remove this piece of code in a couple of years (today it is
+ * 16.05.2011).
+ */
+ next = list_entry(bud->list.next, struct ubifs_bud, list);
+ if (!list_is_last(&next->list, &jh->buds_list))
+ return 0;
+
+ err = ubi_read(c->ubi, next->lnum, (char *)&data,
+ next->start, 4);
+ if (err)
+ return 0;
+
+ return data == 0xFFFFFFFF;
+}
+
+/**
* replay_bud - replay a bud logical eraseblock.
* @c: UBIFS file-system description object
- * @lnum: bud logical eraseblock number to replay
- * @offs: bud start offset
- * @jhead: journal head to which this bud belongs
- * @free: amount of free space in the bud is returned here
- * @dirty: amount of dirty space from padding and deletion nodes is returned
- * here
+ * @b: bud entry which describes the bud
*
- * This function returns zero in case of success and a negative error code in
- * case of failure.
+ * This function replays bud @bud, recovers it if needed, and adds all nodes
+ * from this bud to the replay list. Returns zero in case of success and a
+ * negative error code in case of failure.
*/
-static int replay_bud(struct ubifs_info *c, int lnum, int offs, int jhead,
- int *free, int *dirty)
+static int replay_bud(struct ubifs_info *c, struct bud_entry *b)
{
- int err = 0, used = 0;
+ int is_last = is_last_bud(c, b->bud);
+ int err = 0, used = 0, lnum = b->bud->lnum, offs = b->bud->start;
struct ubifs_scan_leb *sleb;
struct ubifs_scan_node *snod;
- struct ubifs_bud *bud;
- dbg_mnt("replay bud LEB %d, head %d", lnum, jhead);
- if (c->need_recovery)
- sleb = ubifs_recover_leb(c, lnum, offs, c->sbuf, jhead != GCHD);
+ dbg_mnt("replay bud LEB %d, head %d, offs %d, is_last %d",
+ lnum, b->bud->jhead, offs, is_last);
+
+ if (c->need_recovery && is_last)
+ /*
+ * Recover only last LEBs in the journal heads, because power
+ * cuts may cause corruptions only in these LEBs, because only
+ * these LEBs could possibly be written to at the power cut
+ * time.
+ */
+ sleb = ubifs_recover_leb(c, lnum, offs, c->sbuf,
+ b->bud->jhead != GCHD);
else
sleb = ubifs_scan(c, lnum, offs, c->sbuf, 0);
if (IS_ERR(sleb))
@@ -627,15 +674,13 @@
goto out;
}
- bud = ubifs_search_bud(c, lnum);
- if (!bud)
- BUG();
-
+ ubifs_assert(ubifs_search_bud(c, lnum));
ubifs_assert(sleb->endpt - offs >= used);
ubifs_assert(sleb->endpt % c->min_io_size == 0);
- *dirty = sleb->endpt - offs - used;
- *free = c->leb_size - sleb->endpt;
+ b->dirty = sleb->endpt - offs - used;
+ b->free = c->leb_size - sleb->endpt;
+ dbg_mnt("bud LEB %d replied: dirty %d, free %d", lnum, b->dirty, b->free);
out:
ubifs_scan_destroy(sleb);
@@ -649,58 +694,6 @@
}
/**
- * insert_ref_node - insert a reference node to the replay tree.
- * @c: UBIFS file-system description object
- * @lnum: node logical eraseblock number
- * @offs: node offset
- * @sqnum: sequence number
- * @free: amount of free space in bud
- * @dirty: amount of dirty space from padding and deletion nodes
- * @jhead: journal head number for the bud
- *
- * This function inserts a reference node to the replay tree and returns zero
- * in case of success or a negative error code in case of failure.
- */
-static int insert_ref_node(struct ubifs_info *c, int lnum, int offs,
- unsigned long long sqnum, int free, int dirty,
- int jhead)
-{
- struct rb_node **p = &c->replay_tree.rb_node, *parent = NULL;
- struct replay_entry *r;
-
- dbg_mnt("add ref LEB %d:%d", lnum, offs);
- while (*p) {
- parent = *p;
- r = rb_entry(parent, struct replay_entry, rb);
- if (sqnum < r->sqnum) {
- p = &(*p)->rb_left;
- continue;
- } else if (sqnum > r->sqnum) {
- p = &(*p)->rb_right;
- continue;
- }
- ubifs_err("duplicate sqnum in replay tree");
- return -EINVAL;
- }
-
- r = kzalloc(sizeof(struct replay_entry), GFP_KERNEL);
- if (!r)
- return -ENOMEM;
-
- r->lnum = lnum;
- r->offs = offs;
- r->sqnum = sqnum;
- r->flags = REPLAY_REF;
- r->free = free;
- r->dirty = dirty;
- r->jhead = jhead;
-
- rb_link_node(&r->rb, parent, p);
- rb_insert_color(&r->rb, &c->replay_tree);
- return 0;
-}
-
-/**
* replay_buds - replay all buds.
* @c: UBIFS file-system description object
*
@@ -710,17 +703,16 @@
static int replay_buds(struct ubifs_info *c)
{
struct bud_entry *b;
- int err, uninitialized_var(free), uninitialized_var(dirty);
+ int err;
+ unsigned long long prev_sqnum = 0;
list_for_each_entry(b, &c->replay_buds, list) {
- err = replay_bud(c, b->bud->lnum, b->bud->start, b->bud->jhead,
- &free, &dirty);
+ err = replay_bud(c, b);
if (err)
return err;
- err = insert_ref_node(c, b->bud->lnum, b->bud->start, b->sqnum,
- free, dirty, b->bud->jhead);
- if (err)
- return err;
+
+ ubifs_assert(b->sqnum > prev_sqnum);
+ prev_sqnum = b->sqnum;
}
return 0;
@@ -1060,25 +1052,29 @@
if (err)
goto out;
- err = apply_replay_tree(c);
+ err = apply_replay_list(c);
+ if (err)
+ goto out;
+
+ err = set_buds_lprops(c);
if (err)
goto out;
/*
- * UBIFS budgeting calculations use @c->budg_uncommitted_idx variable
- * to roughly estimate index growth. Things like @c->min_idx_lebs
+ * UBIFS budgeting calculations use @c->bi.uncommitted_idx variable
+ * to roughly estimate index growth. Things like @c->bi.min_idx_lebs
* depend on it. This means we have to initialize it to make sure
* budgeting works properly.
*/
- c->budg_uncommitted_idx = atomic_long_read(&c->dirty_zn_cnt);
- c->budg_uncommitted_idx *= c->max_idx_node_sz;
+ c->bi.uncommitted_idx = atomic_long_read(&c->dirty_zn_cnt);
+ c->bi.uncommitted_idx *= c->max_idx_node_sz;
ubifs_assert(c->bud_bytes <= c->max_bud_bytes || c->need_recovery);
dbg_mnt("finished, log head LEB %d:%d, max_sqnum %llu, "
"highest_inum %lu", c->lhead_lnum, c->lhead_offs, c->max_sqnum,
(unsigned long)c->highest_inum);
out:
- destroy_replay_tree(c);
+ destroy_replay_list(c);
destroy_bud_list(c);
c->replaying = 0;
return err;
diff --git a/fs/ubifs/sb.c b/fs/ubifs/sb.c
index bf31b47..c606f01 100644
--- a/fs/ubifs/sb.c
+++ b/fs/ubifs/sb.c
@@ -475,7 +475,8 @@
* @c: UBIFS file-system description object
*
* This function returns a pointer to the superblock node or a negative error
- * code.
+ * code. Note, the user of this function is responsible of kfree()'ing the
+ * returned superblock buffer.
*/
struct ubifs_sb_node *ubifs_read_sb_node(struct ubifs_info *c)
{
@@ -616,6 +617,7 @@
c->vfs_sb->s_time_gran = le32_to_cpu(sup->time_gran);
memcpy(&c->uuid, &sup->uuid, 16);
c->big_lpt = !!(sup_flags & UBIFS_FLG_BIGLPT);
+ c->space_fixup = !!(sup_flags & UBIFS_FLG_SPACE_FIXUP);
/* Automatically increase file system size to the maximum size */
c->old_leb_cnt = c->leb_cnt;
@@ -650,3 +652,152 @@
kfree(sup);
return err;
}
+
+/**
+ * fixup_leb - fixup/unmap an LEB containing free space.
+ * @c: UBIFS file-system description object
+ * @lnum: the LEB number to fix up
+ * @len: number of used bytes in LEB (starting at offset 0)
+ *
+ * This function reads the contents of the given LEB number @lnum, then fixes
+ * it up, so that empty min. I/O units in the end of LEB are actually erased on
+ * flash (rather than being just all-0xff real data). If the LEB is completely
+ * empty, it is simply unmapped.
+ */
+static int fixup_leb(struct ubifs_info *c, int lnum, int len)
+{
+ int err;
+
+ ubifs_assert(len >= 0);
+ ubifs_assert(len % c->min_io_size == 0);
+ ubifs_assert(len < c->leb_size);
+
+ if (len == 0) {
+ dbg_mnt("unmap empty LEB %d", lnum);
+ return ubi_leb_unmap(c->ubi, lnum);
+ }
+
+ dbg_mnt("fixup LEB %d, data len %d", lnum, len);
+ err = ubi_read(c->ubi, lnum, c->sbuf, 0, len);
+ if (err)
+ return err;
+
+ return ubi_leb_change(c->ubi, lnum, c->sbuf, len, UBI_UNKNOWN);
+}
+
+/**
+ * fixup_free_space - find & remap all LEBs containing free space.
+ * @c: UBIFS file-system description object
+ *
+ * This function walks through all LEBs in the filesystem and fiexes up those
+ * containing free/empty space.
+ */
+static int fixup_free_space(struct ubifs_info *c)
+{
+ int lnum, err = 0;
+ struct ubifs_lprops *lprops;
+
+ ubifs_get_lprops(c);
+
+ /* Fixup LEBs in the master area */
+ for (lnum = UBIFS_MST_LNUM; lnum < UBIFS_LOG_LNUM; lnum++) {
+ err = fixup_leb(c, lnum, c->mst_offs + c->mst_node_alsz);
+ if (err)
+ goto out;
+ }
+
+ /* Unmap unused log LEBs */
+ lnum = ubifs_next_log_lnum(c, c->lhead_lnum);
+ while (lnum != c->ltail_lnum) {
+ err = fixup_leb(c, lnum, 0);
+ if (err)
+ goto out;
+ lnum = ubifs_next_log_lnum(c, lnum);
+ }
+
+ /* Fixup the current log head */
+ err = fixup_leb(c, c->lhead_lnum, c->lhead_offs);
+ if (err)
+ goto out;
+
+ /* Fixup LEBs in the LPT area */
+ for (lnum = c->lpt_first; lnum <= c->lpt_last; lnum++) {
+ int free = c->ltab[lnum - c->lpt_first].free;
+
+ if (free > 0) {
+ err = fixup_leb(c, lnum, c->leb_size - free);
+ if (err)
+ goto out;
+ }
+ }
+
+ /* Unmap LEBs in the orphans area */
+ for (lnum = c->orph_first; lnum <= c->orph_last; lnum++) {
+ err = fixup_leb(c, lnum, 0);
+ if (err)
+ goto out;
+ }
+
+ /* Fixup LEBs in the main area */
+ for (lnum = c->main_first; lnum < c->leb_cnt; lnum++) {
+ lprops = ubifs_lpt_lookup(c, lnum);
+ if (IS_ERR(lprops)) {
+ err = PTR_ERR(lprops);
+ goto out;
+ }
+
+ if (lprops->free > 0) {
+ err = fixup_leb(c, lnum, c->leb_size - lprops->free);
+ if (err)
+ goto out;
+ }
+ }
+
+out:
+ ubifs_release_lprops(c);
+ return err;
+}
+
+/**
+ * ubifs_fixup_free_space - find & fix all LEBs with free space.
+ * @c: UBIFS file-system description object
+ *
+ * This function fixes up LEBs containing free space on first mount, if the
+ * appropriate flag was set when the FS was created. Each LEB with one or more
+ * empty min. I/O unit (i.e. free-space-count > 0) is re-written, to make sure
+ * the free space is actually erased. E.g., this is necessary for some NAND
+ * chips, since the free space may have been programmed like real "0xff" data
+ * (generating a non-0xff ECC), causing future writes to the not-really-erased
+ * NAND pages to behave badly. After the space is fixed up, the superblock flag
+ * is cleared, so that this is skipped for all future mounts.
+ */
+int ubifs_fixup_free_space(struct ubifs_info *c)
+{
+ int err;
+ struct ubifs_sb_node *sup;
+
+ ubifs_assert(c->space_fixup);
+ ubifs_assert(!c->ro_mount);
+
+ ubifs_msg("start fixing up free space");
+
+ err = fixup_free_space(c);
+ if (err)
+ return err;
+
+ sup = ubifs_read_sb_node(c);
+ if (IS_ERR(sup))
+ return PTR_ERR(sup);
+
+ /* Free-space fixup is no longer required */
+ c->space_fixup = 0;
+ sup->flags &= cpu_to_le32(~UBIFS_FLG_SPACE_FIXUP);
+
+ err = ubifs_write_sb_node(c, sup);
+ kfree(sup);
+ if (err)
+ return err;
+
+ ubifs_msg("free space fixup complete");
+ return err;
+}
diff --git a/fs/ubifs/super.c b/fs/ubifs/super.c
index 04ad07f..6db0bdaa 100644
--- a/fs/ubifs/super.c
+++ b/fs/ubifs/super.c
@@ -375,7 +375,7 @@
ubifs_release_dirty_inode_budget(c, ui);
else {
/* We've deleted something - clean the "no space" flags */
- c->nospace = c->nospace_rp = 0;
+ c->bi.nospace = c->bi.nospace_rp = 0;
smp_wmb();
}
done:
@@ -694,11 +694,11 @@
* be compressed and direntries are of the maximum size.
*
* Note, data, which may be stored in inodes is budgeted separately, so
- * it is not included into 'c->inode_budget'.
+ * it is not included into 'c->bi.inode_budget'.
*/
- c->page_budget = UBIFS_MAX_DATA_NODE_SZ * UBIFS_BLOCKS_PER_PAGE;
- c->inode_budget = UBIFS_INO_NODE_SZ;
- c->dent_budget = UBIFS_MAX_DENT_NODE_SZ;
+ c->bi.page_budget = UBIFS_MAX_DATA_NODE_SZ * UBIFS_BLOCKS_PER_PAGE;
+ c->bi.inode_budget = UBIFS_INO_NODE_SZ;
+ c->bi.dent_budget = UBIFS_MAX_DENT_NODE_SZ;
/*
* When the amount of flash space used by buds becomes
@@ -742,7 +742,7 @@
{
long long tmp64;
- c->min_idx_lebs = ubifs_calc_min_idx_lebs(c);
+ c->bi.min_idx_lebs = ubifs_calc_min_idx_lebs(c);
c->report_rp_size = ubifs_reported_space(c, c->rp_size);
/*
@@ -1144,8 +1144,8 @@
{
ubifs_assert(c->dark_wm > 0);
if (c->lst.total_free + c->lst.total_dirty < c->dark_wm) {
- ubifs_err("insufficient free space to mount in read/write mode");
- dbg_dump_budg(c);
+ ubifs_err("insufficient free space to mount in R/W mode");
+ dbg_dump_budg(c, &c->bi);
dbg_dump_lprops(c);
return -ENOSPC;
}
@@ -1304,7 +1304,7 @@
if (err)
goto out_lpt;
- err = dbg_check_idx_size(c, c->old_idx_sz);
+ err = dbg_check_idx_size(c, c->bi.old_idx_sz);
if (err)
goto out_lpt;
@@ -1313,7 +1313,7 @@
goto out_journal;
/* Calculate 'min_idx_lebs' after journal replay */
- c->min_idx_lebs = ubifs_calc_min_idx_lebs(c);
+ c->bi.min_idx_lebs = ubifs_calc_min_idx_lebs(c);
err = ubifs_mount_orphans(c, c->need_recovery, c->ro_mount);
if (err)
@@ -1396,6 +1396,12 @@
} else
ubifs_assert(c->lst.taken_empty_lebs > 0);
+ if (!c->ro_mount && c->space_fixup) {
+ err = ubifs_fixup_free_space(c);
+ if (err)
+ goto out_infos;
+ }
+
err = dbg_check_filesystem(c);
if (err)
goto out_infos;
@@ -1442,7 +1448,8 @@
c->main_lebs, c->main_first, c->leb_cnt - 1);
dbg_msg("index LEBs: %d", c->lst.idx_lebs);
dbg_msg("total index bytes: %lld (%lld KiB, %lld MiB)",
- c->old_idx_sz, c->old_idx_sz >> 10, c->old_idx_sz >> 20);
+ c->bi.old_idx_sz, c->bi.old_idx_sz >> 10,
+ c->bi.old_idx_sz >> 20);
dbg_msg("key hash type: %d", c->key_hash_type);
dbg_msg("tree fanout: %d", c->fanout);
dbg_msg("reserved GC LEB: %d", c->gc_lnum);
@@ -1456,7 +1463,7 @@
dbg_msg("node sizes: ref %zu, cmt. start %zu, orph %zu",
UBIFS_REF_NODE_SZ, UBIFS_CS_NODE_SZ, UBIFS_ORPH_NODE_SZ);
dbg_msg("max. node sizes: data %zu, inode %zu dentry %zu, idx %d",
- UBIFS_MAX_DATA_NODE_SZ, UBIFS_MAX_INO_NODE_SZ,
+ UBIFS_MAX_DATA_NODE_SZ, UBIFS_MAX_INO_NODE_SZ,
UBIFS_MAX_DENT_NODE_SZ, ubifs_idx_node_sz(c, c->fanout));
dbg_msg("dead watermark: %d", c->dead_wm);
dbg_msg("dark watermark: %d", c->dark_wm);
@@ -1584,6 +1591,7 @@
}
sup->leb_cnt = cpu_to_le32(c->leb_cnt);
err = ubifs_write_sb_node(c, sup);
+ kfree(sup);
if (err)
goto out;
}
@@ -1684,6 +1692,13 @@
*/
err = dbg_check_space_info(c);
}
+
+ if (c->space_fixup) {
+ err = ubifs_fixup_free_space(c);
+ if (err)
+ goto out;
+ }
+
mutex_unlock(&c->umount_mutex);
return err;
@@ -1766,10 +1781,9 @@
* to write them back because of I/O errors.
*/
if (!c->ro_error) {
- ubifs_assert(atomic_long_read(&c->dirty_pg_cnt) == 0);
- ubifs_assert(c->budg_idx_growth == 0);
- ubifs_assert(c->budg_dd_growth == 0);
- ubifs_assert(c->budg_data_growth == 0);
+ ubifs_assert(c->bi.idx_growth == 0);
+ ubifs_assert(c->bi.dd_growth == 0);
+ ubifs_assert(c->bi.data_growth == 0);
}
/*
diff --git a/fs/ubifs/tnc.c b/fs/ubifs/tnc.c
index de48597..8119b1f 100644
--- a/fs/ubifs/tnc.c
+++ b/fs/ubifs/tnc.c
@@ -2557,11 +2557,11 @@
if (err) {
/* Ensure the znode is dirtied */
if (znode->cnext || !ubifs_zn_dirty(znode)) {
- znode = dirty_cow_bottom_up(c, znode);
- if (IS_ERR(znode)) {
- err = PTR_ERR(znode);
- goto out_unlock;
- }
+ znode = dirty_cow_bottom_up(c, znode);
+ if (IS_ERR(znode)) {
+ err = PTR_ERR(znode);
+ goto out_unlock;
+ }
}
err = tnc_delete(c, znode, n);
}
diff --git a/fs/ubifs/tnc_commit.c b/fs/ubifs/tnc_commit.c
index 53288e5..41920f3 100644
--- a/fs/ubifs/tnc_commit.c
+++ b/fs/ubifs/tnc_commit.c
@@ -377,15 +377,13 @@
c->gap_lebs = NULL;
return err;
}
- if (!dbg_force_in_the_gaps_enabled) {
+ if (dbg_force_in_the_gaps_enabled()) {
/*
* Do not print scary warnings if the debugging
* option which forces in-the-gaps is enabled.
*/
- ubifs_err("out of space");
- spin_lock(&c->space_lock);
- dbg_dump_budg(c);
- spin_unlock(&c->space_lock);
+ ubifs_warn("out of space");
+ dbg_dump_budg(c, &c->bi);
dbg_dump_lprops(c);
}
/* Try to commit anyway */
@@ -796,16 +794,16 @@
spin_lock(&c->space_lock);
/*
* Although we have not finished committing yet, update size of the
- * committed index ('c->old_idx_sz') and zero out the index growth
+ * committed index ('c->bi.old_idx_sz') and zero out the index growth
* budget. It is OK to do this now, because we've reserved all the
* space which is needed to commit the index, and it is save for the
* budgeting subsystem to assume the index is already committed,
* even though it is not.
*/
- ubifs_assert(c->min_idx_lebs == ubifs_calc_min_idx_lebs(c));
- c->old_idx_sz = c->calc_idx_sz;
- c->budg_uncommitted_idx = 0;
- c->min_idx_lebs = ubifs_calc_min_idx_lebs(c);
+ ubifs_assert(c->bi.min_idx_lebs == ubifs_calc_min_idx_lebs(c));
+ c->bi.old_idx_sz = c->calc_idx_sz;
+ c->bi.uncommitted_idx = 0;
+ c->bi.min_idx_lebs = ubifs_calc_min_idx_lebs(c);
spin_unlock(&c->space_lock);
mutex_unlock(&c->tnc_mutex);
diff --git a/fs/ubifs/ubifs-media.h b/fs/ubifs/ubifs-media.h
index 191ca78..e24380c 100644
--- a/fs/ubifs/ubifs-media.h
+++ b/fs/ubifs/ubifs-media.h
@@ -408,9 +408,11 @@
* Superblock flags.
*
* UBIFS_FLG_BIGLPT: if "big" LPT model is used if set
+ * UBIFS_FLG_SPACE_FIXUP: first-mount "fixup" of free space within LEBs needed
*/
enum {
UBIFS_FLG_BIGLPT = 0x02,
+ UBIFS_FLG_SPACE_FIXUP = 0x04,
};
/**
@@ -434,7 +436,7 @@
__u8 node_type;
__u8 group_type;
__u8 padding[2];
-} __attribute__ ((packed));
+} __packed;
/**
* union ubifs_dev_desc - device node descriptor.
@@ -448,7 +450,7 @@
union ubifs_dev_desc {
__le32 new;
__le64 huge;
-} __attribute__ ((packed));
+} __packed;
/**
* struct ubifs_ino_node - inode node.
@@ -509,7 +511,7 @@
__le16 compr_type;
__u8 padding2[26]; /* Watch 'zero_ino_node_unused()' if changing! */
__u8 data[];
-} __attribute__ ((packed));
+} __packed;
/**
* struct ubifs_dent_node - directory entry node.
@@ -534,7 +536,7 @@
__le16 nlen;
__u8 padding2[4]; /* Watch 'zero_dent_node_unused()' if changing! */
__u8 name[];
-} __attribute__ ((packed));
+} __packed;
/**
* struct ubifs_data_node - data node.
@@ -555,7 +557,7 @@
__le16 compr_type;
__u8 padding[2]; /* Watch 'zero_data_node_unused()' if changing! */
__u8 data[];
-} __attribute__ ((packed));
+} __packed;
/**
* struct ubifs_trun_node - truncation node.
@@ -575,7 +577,7 @@
__u8 padding[12]; /* Watch 'zero_trun_node_unused()' if changing! */
__le64 old_size;
__le64 new_size;
-} __attribute__ ((packed));
+} __packed;
/**
* struct ubifs_pad_node - padding node.
@@ -586,7 +588,7 @@
struct ubifs_pad_node {
struct ubifs_ch ch;
__le32 pad_len;
-} __attribute__ ((packed));
+} __packed;
/**
* struct ubifs_sb_node - superblock node.
@@ -644,7 +646,7 @@
__u8 uuid[16];
__le32 ro_compat_version;
__u8 padding2[3968];
-} __attribute__ ((packed));
+} __packed;
/**
* struct ubifs_mst_node - master node.
@@ -711,7 +713,7 @@
__le32 idx_lebs;
__le32 leb_cnt;
__u8 padding[344];
-} __attribute__ ((packed));
+} __packed;
/**
* struct ubifs_ref_node - logical eraseblock reference node.
@@ -727,7 +729,7 @@
__le32 offs;
__le32 jhead;
__u8 padding[28];
-} __attribute__ ((packed));
+} __packed;
/**
* struct ubifs_branch - key/reference/length branch
@@ -741,7 +743,7 @@
__le32 offs;
__le32 len;
__u8 key[];
-} __attribute__ ((packed));
+} __packed;
/**
* struct ubifs_idx_node - indexing node.
@@ -755,7 +757,7 @@
__le16 child_cnt;
__le16 level;
__u8 branches[];
-} __attribute__ ((packed));
+} __packed;
/**
* struct ubifs_cs_node - commit start node.
@@ -765,7 +767,7 @@
struct ubifs_cs_node {
struct ubifs_ch ch;
__le64 cmt_no;
-} __attribute__ ((packed));
+} __packed;
/**
* struct ubifs_orph_node - orphan node.
@@ -777,6 +779,6 @@
struct ubifs_ch ch;
__le64 cmt_no;
__le64 inos[];
-} __attribute__ ((packed));
+} __packed;
#endif /* __UBIFS_MEDIA_H__ */
diff --git a/fs/ubifs/ubifs.h b/fs/ubifs/ubifs.h
index 8c40ad3..93d1412 100644
--- a/fs/ubifs/ubifs.h
+++ b/fs/ubifs/ubifs.h
@@ -389,9 +389,9 @@
* The @ui_size is a "shadow" variable for @inode->i_size and UBIFS uses
* @ui_size instead of @inode->i_size. The reason for this is that UBIFS cannot
* make sure @inode->i_size is always changed under @ui_mutex, because it
- * cannot call 'truncate_setsize()' with @ui_mutex locked, because it would deadlock
- * with 'ubifs_writepage()' (see file.c). All the other inode fields are
- * changed under @ui_mutex, so they do not need "shadow" fields. Note, one
+ * cannot call 'truncate_setsize()' with @ui_mutex locked, because it would
+ * deadlock with 'ubifs_writepage()' (see file.c). All the other inode fields
+ * are changed under @ui_mutex, so they do not need "shadow" fields. Note, one
* could consider to rework locking and base it on "shadow" fields.
*/
struct ubifs_inode {
@@ -937,6 +937,40 @@
unsigned int compr_type:2;
};
+/**
+ * struct ubifs_budg_info - UBIFS budgeting information.
+ * @idx_growth: amount of bytes budgeted for index growth
+ * @data_growth: amount of bytes budgeted for cached data
+ * @dd_growth: amount of bytes budgeted for cached data that will make
+ * other data dirty
+ * @uncommitted_idx: amount of bytes were budgeted for growth of the index, but
+ * which still have to be taken into account because the index
+ * has not been committed so far
+ * @old_idx_sz: size of index on flash
+ * @min_idx_lebs: minimum number of LEBs required for the index
+ * @nospace: non-zero if the file-system does not have flash space (used as
+ * optimization)
+ * @nospace_rp: the same as @nospace, but additionally means that even reserved
+ * pool is full
+ * @page_budget: budget for a page (constant, nenver changed after mount)
+ * @inode_budget: budget for an inode (constant, nenver changed after mount)
+ * @dent_budget: budget for a directory entry (constant, nenver changed after
+ * mount)
+ */
+struct ubifs_budg_info {
+ long long idx_growth;
+ long long data_growth;
+ long long dd_growth;
+ long long uncommitted_idx;
+ unsigned long long old_idx_sz;
+ int min_idx_lebs;
+ unsigned int nospace:1;
+ unsigned int nospace_rp:1;
+ int page_budget;
+ int inode_budget;
+ int dent_budget;
+};
+
struct ubifs_debug_info;
/**
@@ -980,6 +1014,7 @@
* @cmt_wq: wait queue to sleep on if the log is full and a commit is running
*
* @big_lpt: flag that LPT is too big to write whole during commit
+ * @space_fixup: flag indicating that free space in LEBs needs to be cleaned up
* @no_chk_data_crc: do not check CRCs when reading data nodes (except during
* recovery)
* @bulk_read: enable bulk-reads
@@ -1057,32 +1092,14 @@
* @dirty_zn_cnt: number of dirty znodes
* @clean_zn_cnt: number of clean znodes
*
- * @budg_idx_growth: amount of bytes budgeted for index growth
- * @budg_data_growth: amount of bytes budgeted for cached data
- * @budg_dd_growth: amount of bytes budgeted for cached data that will make
- * other data dirty
- * @budg_uncommitted_idx: amount of bytes were budgeted for growth of the index,
- * but which still have to be taken into account because
- * the index has not been committed so far
- * @space_lock: protects @budg_idx_growth, @budg_data_growth, @budg_dd_growth,
- * @budg_uncommited_idx, @min_idx_lebs, @old_idx_sz, @lst,
- * @nospace, and @nospace_rp;
- * @min_idx_lebs: minimum number of LEBs required for the index
- * @old_idx_sz: size of index on flash
+ * @space_lock: protects @bi and @lst
+ * @lst: lprops statistics
+ * @bi: budgeting information
* @calc_idx_sz: temporary variable which is used to calculate new index size
* (contains accurate new index size at end of TNC commit start)
- * @lst: lprops statistics
- * @nospace: non-zero if the file-system does not have flash space (used as
- * optimization)
- * @nospace_rp: the same as @nospace, but additionally means that even reserved
- * pool is full
- *
- * @page_budget: budget for a page
- * @inode_budget: budget for an inode
- * @dent_budget: budget for a directory entry
*
* @ref_node_alsz: size of the LEB reference node aligned to the min. flash
- * I/O unit
+ * I/O unit
* @mst_node_alsz: master node aligned size
* @min_idx_node_sz: minimum indexing node aligned on 8-bytes boundary
* @max_idx_node_sz: maximum indexing node aligned on 8-bytes boundary
@@ -1189,7 +1206,6 @@
* @replaying: %1 during journal replay
* @mounting: %1 while mounting
* @remounting_rw: %1 while re-mounting from R/O mode to R/W mode
- * @replay_tree: temporary tree used during journal replay
* @replay_list: temporary list used during journal replay
* @replay_buds: list of buds to replay
* @cs_sqnum: sequence number of first node in the log (commit start node)
@@ -1238,6 +1254,7 @@
wait_queue_head_t cmt_wq;
unsigned int big_lpt:1;
+ unsigned int space_fixup:1;
unsigned int no_chk_data_crc:1;
unsigned int bulk_read:1;
unsigned int default_compr:2;
@@ -1308,21 +1325,10 @@
atomic_long_t dirty_zn_cnt;
atomic_long_t clean_zn_cnt;
- long long budg_idx_growth;
- long long budg_data_growth;
- long long budg_dd_growth;
- long long budg_uncommitted_idx;
spinlock_t space_lock;
- int min_idx_lebs;
- unsigned long long old_idx_sz;
- unsigned long long calc_idx_sz;
struct ubifs_lp_stats lst;
- unsigned int nospace:1;
- unsigned int nospace_rp:1;
-
- int page_budget;
- int inode_budget;
- int dent_budget;
+ struct ubifs_budg_info bi;
+ unsigned long long calc_idx_sz;
int ref_node_alsz;
int mst_node_alsz;
@@ -1430,7 +1436,6 @@
unsigned int replaying:1;
unsigned int mounting:1;
unsigned int remounting_rw:1;
- struct rb_root replay_tree;
struct list_head replay_list;
struct list_head replay_buds;
unsigned long long cs_sqnum;
@@ -1628,6 +1633,7 @@
int ubifs_read_superblock(struct ubifs_info *c);
struct ubifs_sb_node *ubifs_read_sb_node(struct ubifs_info *c);
int ubifs_write_sb_node(struct ubifs_info *c, struct ubifs_sb_node *sup);
+int ubifs_fixup_free_space(struct ubifs_info *c);
/* replay.c */
int ubifs_validate_entry(struct ubifs_info *c,
diff --git a/fs/ubifs/xattr.c b/fs/ubifs/xattr.c
index 3299f46..16f19f5 100644
--- a/fs/ubifs/xattr.c
+++ b/fs/ubifs/xattr.c
@@ -80,8 +80,8 @@
SECURITY_XATTR,
};
-static const struct inode_operations none_inode_operations;
-static const struct file_operations none_file_operations;
+static const struct inode_operations empty_iops;
+static const struct file_operations empty_fops;
/**
* create_xattr - create an extended attribute.
@@ -131,8 +131,8 @@
/* Re-define all operations to be "nothing" */
inode->i_mapping->a_ops = &empty_aops;
- inode->i_op = &none_inode_operations;
- inode->i_fop = &none_file_operations;
+ inode->i_op = &empty_iops;
+ inode->i_fop = &empty_fops;
inode->i_flags |= S_SYNC | S_NOATIME | S_NOCMTIME | S_NOQUOTA;
ui = ubifs_inode(inode);
diff --git a/fs/xfs/linux-2.6/xfs_buf.c b/fs/xfs/linux-2.6/xfs_buf.c
index 9ef9ed2..5e68099 100644
--- a/fs/xfs/linux-2.6/xfs_buf.c
+++ b/fs/xfs/linux-2.6/xfs_buf.c
@@ -33,7 +33,6 @@
#include <linux/migrate.h>
#include <linux/backing-dev.h>
#include <linux/freezer.h>
-#include <linux/list_sort.h>
#include "xfs_sb.h"
#include "xfs_inum.h"
@@ -709,6 +708,27 @@
return bp;
}
+/*
+ * Return a buffer allocated as an empty buffer and associated to external
+ * memory via xfs_buf_associate_memory() back to it's empty state.
+ */
+void
+xfs_buf_set_empty(
+ struct xfs_buf *bp,
+ size_t len)
+{
+ if (bp->b_pages)
+ _xfs_buf_free_pages(bp);
+
+ bp->b_pages = NULL;
+ bp->b_page_count = 0;
+ bp->b_addr = NULL;
+ bp->b_file_offset = 0;
+ bp->b_buffer_length = bp->b_count_desired = len;
+ bp->b_bn = XFS_BUF_DADDR_NULL;
+ bp->b_flags &= ~XBF_MAPPED;
+}
+
static inline struct page *
mem_to_page(
void *addr)
@@ -1402,12 +1422,12 @@
int
xfs_buftarg_shrink(
struct shrinker *shrink,
- int nr_to_scan,
- gfp_t mask)
+ struct shrink_control *sc)
{
struct xfs_buftarg *btp = container_of(shrink,
struct xfs_buftarg, bt_shrinker);
struct xfs_buf *bp;
+ int nr_to_scan = sc->nr_to_scan;
LIST_HEAD(dispose);
if (!nr_to_scan)
diff --git a/fs/xfs/linux-2.6/xfs_buf.h b/fs/xfs/linux-2.6/xfs_buf.h
index a9a1c45..50a7d5f 100644
--- a/fs/xfs/linux-2.6/xfs_buf.h
+++ b/fs/xfs/linux-2.6/xfs_buf.h
@@ -178,6 +178,7 @@
xfs_buf_flags_t);
extern xfs_buf_t *xfs_buf_get_empty(size_t, xfs_buftarg_t *);
+extern void xfs_buf_set_empty(struct xfs_buf *bp, size_t len);
extern xfs_buf_t *xfs_buf_get_uncached(struct xfs_buftarg *, size_t, int);
extern int xfs_buf_associate_memory(xfs_buf_t *, void *, size_t);
extern void xfs_buf_hold(xfs_buf_t *);
diff --git a/fs/xfs/linux-2.6/xfs_ioctl32.c b/fs/xfs/linux-2.6/xfs_ioctl32.c
index b3486df..54e623b 100644
--- a/fs/xfs/linux-2.6/xfs_ioctl32.c
+++ b/fs/xfs/linux-2.6/xfs_ioctl32.c
@@ -586,7 +586,8 @@
case XFS_IOC_RESVSP_32:
case XFS_IOC_UNRESVSP_32:
case XFS_IOC_RESVSP64_32:
- case XFS_IOC_UNRESVSP64_32: {
+ case XFS_IOC_UNRESVSP64_32:
+ case XFS_IOC_ZERO_RANGE_32: {
struct xfs_flock64 bf;
if (xfs_compat_flock64_copyin(&bf, arg))
diff --git a/fs/xfs/linux-2.6/xfs_ioctl32.h b/fs/xfs/linux-2.6/xfs_ioctl32.h
index 08b6057..80f4060 100644
--- a/fs/xfs/linux-2.6/xfs_ioctl32.h
+++ b/fs/xfs/linux-2.6/xfs_ioctl32.h
@@ -184,6 +184,7 @@
#define XFS_IOC_UNRESVSP_32 _IOW('X', 41, struct compat_xfs_flock64)
#define XFS_IOC_RESVSP64_32 _IOW('X', 42, struct compat_xfs_flock64)
#define XFS_IOC_UNRESVSP64_32 _IOW('X', 43, struct compat_xfs_flock64)
+#define XFS_IOC_ZERO_RANGE_32 _IOW('X', 57, struct compat_xfs_flock64)
typedef struct compat_xfs_fsop_geom_v1 {
__u32 blocksize; /* filesystem (data) block size */
diff --git a/fs/xfs/linux-2.6/xfs_linux.h b/fs/xfs/linux-2.6/xfs_linux.h
index 244be9c..8633521 100644
--- a/fs/xfs/linux-2.6/xfs_linux.h
+++ b/fs/xfs/linux-2.6/xfs_linux.h
@@ -70,6 +70,7 @@
#include <linux/ctype.h>
#include <linux/writeback.h>
#include <linux/capability.h>
+#include <linux/list_sort.h>
#include <asm/page.h>
#include <asm/div64.h>
diff --git a/fs/xfs/linux-2.6/xfs_message.c b/fs/xfs/linux-2.6/xfs_message.c
index 9f76cce..bd672de 100644
--- a/fs/xfs/linux-2.6/xfs_message.c
+++ b/fs/xfs/linux-2.6/xfs_message.c
@@ -41,23 +41,6 @@
printk("%sXFS: %pV\n", level, vaf);
}
-void xfs_printk(
- const char *level,
- const struct xfs_mount *mp,
- const char *fmt, ...)
-{
- struct va_format vaf;
- va_list args;
-
- va_start(args, fmt);
-
- vaf.fmt = fmt;
- vaf.va = &args;
-
- __xfs_printk(level, mp, &vaf);
- va_end(args);
-}
-
#define define_xfs_printk_level(func, kern_level) \
void func(const struct xfs_mount *mp, const char *fmt, ...) \
{ \
@@ -95,8 +78,7 @@
int do_panic = 0;
if (xfs_panic_mask && (xfs_panic_mask & panic_tag)) {
- xfs_printk(KERN_ALERT, mp,
- "XFS: Transforming an alert into a BUG.");
+ xfs_alert(mp, "Transforming an alert into a BUG.");
do_panic = 1;
}
diff --git a/fs/xfs/linux-2.6/xfs_message.h b/fs/xfs/linux-2.6/xfs_message.h
index f1b3fc1..7fb7ea0 100644
--- a/fs/xfs/linux-2.6/xfs_message.h
+++ b/fs/xfs/linux-2.6/xfs_message.h
@@ -3,9 +3,6 @@
struct xfs_mount;
-extern void xfs_printk(const char *level, const struct xfs_mount *mp,
- const char *fmt, ...)
- __attribute__ ((format (printf, 3, 4)));
extern void xfs_emerg(const struct xfs_mount *mp, const char *fmt, ...)
__attribute__ ((format (printf, 2, 3)));
extern void xfs_alert(const struct xfs_mount *mp, const char *fmt, ...)
@@ -28,7 +25,9 @@
extern void xfs_debug(const struct xfs_mount *mp, const char *fmt, ...)
__attribute__ ((format (printf, 2, 3)));
#else
-static inline void xfs_debug(const struct xfs_mount *mp, const char *fmt, ...)
+static inline void
+__attribute__ ((format (printf, 2, 3)))
+xfs_debug(const struct xfs_mount *mp, const char *fmt, ...)
{
}
#endif
diff --git a/fs/xfs/linux-2.6/xfs_super.c b/fs/xfs/linux-2.6/xfs_super.c
index b38e58d..b0aa59e 100644
--- a/fs/xfs/linux-2.6/xfs_super.c
+++ b/fs/xfs/linux-2.6/xfs_super.c
@@ -1787,10 +1787,6 @@
if (error)
goto out_cleanup_procfs;
- error = xfs_init_workqueues();
- if (error)
- goto out_sysctl_unregister;
-
vfs_initquota();
error = register_filesystem(&xfs_fs_type);
diff --git a/fs/xfs/linux-2.6/xfs_sync.c b/fs/xfs/linux-2.6/xfs_sync.c
index 3e898a4..8ecad5f 100644
--- a/fs/xfs/linux-2.6/xfs_sync.c
+++ b/fs/xfs/linux-2.6/xfs_sync.c
@@ -267,6 +267,16 @@
error = xfs_iflush(ip, flags);
+ /*
+ * We don't want to try again on non-blocking flushes that can't run
+ * again immediately. If an inode really must be written, then that's
+ * what the SYNC_WAIT flag is for.
+ */
+ if (error == EAGAIN) {
+ ASSERT(!(flags & SYNC_WAIT));
+ error = 0;
+ }
+
out_unlock:
xfs_iunlock(ip, XFS_ILOCK_SHARED);
return error;
@@ -1022,13 +1032,14 @@
static int
xfs_reclaim_inode_shrink(
struct shrinker *shrink,
- int nr_to_scan,
- gfp_t gfp_mask)
+ struct shrink_control *sc)
{
struct xfs_mount *mp;
struct xfs_perag *pag;
xfs_agnumber_t ag;
int reclaimable;
+ int nr_to_scan = sc->nr_to_scan;
+ gfp_t gfp_mask = sc->gfp_mask;
mp = container_of(shrink, struct xfs_mount, m_inode_shrink);
if (nr_to_scan) {
diff --git a/fs/xfs/linux-2.6/xfs_trace.h b/fs/xfs/linux-2.6/xfs_trace.h
index 2d0bcb4..d48b7a5 100644
--- a/fs/xfs/linux-2.6/xfs_trace.h
+++ b/fs/xfs/linux-2.6/xfs_trace.h
@@ -1151,44 +1151,7 @@
);
-#define XFS_BUSY_SYNC \
- { 0, "async" }, \
- { 1, "sync" }
-
-TRACE_EVENT(xfs_alloc_busy,
- TP_PROTO(struct xfs_trans *trans, xfs_agnumber_t agno,
- xfs_agblock_t agbno, xfs_extlen_t len, int sync),
- TP_ARGS(trans, agno, agbno, len, sync),
- TP_STRUCT__entry(
- __field(dev_t, dev)
- __field(struct xfs_trans *, tp)
- __field(int, tid)
- __field(xfs_agnumber_t, agno)
- __field(xfs_agblock_t, agbno)
- __field(xfs_extlen_t, len)
- __field(int, sync)
- ),
- TP_fast_assign(
- __entry->dev = trans->t_mountp->m_super->s_dev;
- __entry->tp = trans;
- __entry->tid = trans->t_ticket->t_tid;
- __entry->agno = agno;
- __entry->agbno = agbno;
- __entry->len = len;
- __entry->sync = sync;
- ),
- TP_printk("dev %d:%d trans 0x%p tid 0x%x agno %u agbno %u len %u %s",
- MAJOR(__entry->dev), MINOR(__entry->dev),
- __entry->tp,
- __entry->tid,
- __entry->agno,
- __entry->agbno,
- __entry->len,
- __print_symbolic(__entry->sync, XFS_BUSY_SYNC))
-
-);
-
-TRACE_EVENT(xfs_alloc_unbusy,
+DECLARE_EVENT_CLASS(xfs_busy_class,
TP_PROTO(struct xfs_mount *mp, xfs_agnumber_t agno,
xfs_agblock_t agbno, xfs_extlen_t len),
TP_ARGS(mp, agno, agbno, len),
@@ -1210,35 +1173,45 @@
__entry->agbno,
__entry->len)
);
+#define DEFINE_BUSY_EVENT(name) \
+DEFINE_EVENT(xfs_busy_class, name, \
+ TP_PROTO(struct xfs_mount *mp, xfs_agnumber_t agno, \
+ xfs_agblock_t agbno, xfs_extlen_t len), \
+ TP_ARGS(mp, agno, agbno, len))
+DEFINE_BUSY_EVENT(xfs_alloc_busy);
+DEFINE_BUSY_EVENT(xfs_alloc_busy_enomem);
+DEFINE_BUSY_EVENT(xfs_alloc_busy_force);
+DEFINE_BUSY_EVENT(xfs_alloc_busy_reuse);
+DEFINE_BUSY_EVENT(xfs_alloc_busy_clear);
-#define XFS_BUSY_STATES \
- { 0, "missing" }, \
- { 1, "found" }
-
-TRACE_EVENT(xfs_alloc_busysearch,
+TRACE_EVENT(xfs_alloc_busy_trim,
TP_PROTO(struct xfs_mount *mp, xfs_agnumber_t agno,
- xfs_agblock_t agbno, xfs_extlen_t len, int found),
- TP_ARGS(mp, agno, agbno, len, found),
+ xfs_agblock_t agbno, xfs_extlen_t len,
+ xfs_agblock_t tbno, xfs_extlen_t tlen),
+ TP_ARGS(mp, agno, agbno, len, tbno, tlen),
TP_STRUCT__entry(
__field(dev_t, dev)
__field(xfs_agnumber_t, agno)
__field(xfs_agblock_t, agbno)
__field(xfs_extlen_t, len)
- __field(int, found)
+ __field(xfs_agblock_t, tbno)
+ __field(xfs_extlen_t, tlen)
),
TP_fast_assign(
__entry->dev = mp->m_super->s_dev;
__entry->agno = agno;
__entry->agbno = agbno;
__entry->len = len;
- __entry->found = found;
+ __entry->tbno = tbno;
+ __entry->tlen = tlen;
),
- TP_printk("dev %d:%d agno %u agbno %u len %u %s",
+ TP_printk("dev %d:%d agno %u agbno %u len %u tbno %u tlen %u",
MAJOR(__entry->dev), MINOR(__entry->dev),
__entry->agno,
__entry->agbno,
__entry->len,
- __print_symbolic(__entry->found, XFS_BUSY_STATES))
+ __entry->tbno,
+ __entry->tlen)
);
TRACE_EVENT(xfs_trans_commit_lsn,
@@ -1418,7 +1391,7 @@
__entry->wasfromfl,
__entry->isfl,
__entry->userdata,
- __entry->firstblock)
+ (unsigned long long)__entry->firstblock)
)
#define DEFINE_ALLOC_EVENT(name) \
@@ -1433,11 +1406,14 @@
DEFINE_ALLOC_EVENT(xfs_alloc_near_greater);
DEFINE_ALLOC_EVENT(xfs_alloc_near_lesser);
DEFINE_ALLOC_EVENT(xfs_alloc_near_error);
+DEFINE_ALLOC_EVENT(xfs_alloc_near_noentry);
+DEFINE_ALLOC_EVENT(xfs_alloc_near_busy);
DEFINE_ALLOC_EVENT(xfs_alloc_size_neither);
DEFINE_ALLOC_EVENT(xfs_alloc_size_noentry);
DEFINE_ALLOC_EVENT(xfs_alloc_size_nominleft);
DEFINE_ALLOC_EVENT(xfs_alloc_size_done);
DEFINE_ALLOC_EVENT(xfs_alloc_size_error);
+DEFINE_ALLOC_EVENT(xfs_alloc_size_busy);
DEFINE_ALLOC_EVENT(xfs_alloc_small_freelist);
DEFINE_ALLOC_EVENT(xfs_alloc_small_notenough);
DEFINE_ALLOC_EVENT(xfs_alloc_small_done);
diff --git a/fs/xfs/quota/xfs_qm.c b/fs/xfs/quota/xfs_qm.c
index 69228aa..b94dace 100644
--- a/fs/xfs/quota/xfs_qm.c
+++ b/fs/xfs/quota/xfs_qm.c
@@ -60,7 +60,7 @@
STATIC int xfs_qm_init_quotainos(xfs_mount_t *);
STATIC int xfs_qm_init_quotainfo(xfs_mount_t *);
-STATIC int xfs_qm_shake(struct shrinker *, int, gfp_t);
+STATIC int xfs_qm_shake(struct shrinker *, struct shrink_control *);
static struct shrinker xfs_qm_shaker = {
.shrink = xfs_qm_shake,
@@ -2009,10 +2009,10 @@
STATIC int
xfs_qm_shake(
struct shrinker *shrink,
- int nr_to_scan,
- gfp_t gfp_mask)
+ struct shrink_control *sc)
{
int ndqused, nfree, n;
+ gfp_t gfp_mask = sc->gfp_mask;
if (!kmem_shake_allow(gfp_mask))
return 0;
diff --git a/fs/xfs/xfs_ag.h b/fs/xfs/xfs_ag.h
index 58632cc..da0a561 100644
--- a/fs/xfs/xfs_ag.h
+++ b/fs/xfs/xfs_ag.h
@@ -187,7 +187,6 @@
xfs_agnumber_t agno;
xfs_agblock_t bno;
xfs_extlen_t length;
- xlog_tid_t tid; /* transaction that created this */
};
/*
diff --git a/fs/xfs/xfs_alloc.c b/fs/xfs/xfs_alloc.c
index 27d64d7..acdced8 100644
--- a/fs/xfs/xfs_alloc.c
+++ b/fs/xfs/xfs_alloc.c
@@ -41,19 +41,13 @@
#define XFSA_FIXUP_BNO_OK 1
#define XFSA_FIXUP_CNT_OK 2
-/*
- * Prototypes for per-ag allocation routines
- */
-
STATIC int xfs_alloc_ag_vextent_exact(xfs_alloc_arg_t *);
STATIC int xfs_alloc_ag_vextent_near(xfs_alloc_arg_t *);
STATIC int xfs_alloc_ag_vextent_size(xfs_alloc_arg_t *);
STATIC int xfs_alloc_ag_vextent_small(xfs_alloc_arg_t *,
- xfs_btree_cur_t *, xfs_agblock_t *, xfs_extlen_t *, int *);
-
-/*
- * Internal functions.
- */
+ xfs_btree_cur_t *, xfs_agblock_t *, xfs_extlen_t *, int *);
+STATIC void xfs_alloc_busy_trim(struct xfs_alloc_arg *,
+ xfs_agblock_t, xfs_extlen_t, xfs_agblock_t *, xfs_extlen_t *);
/*
* Lookup the record equal to [bno, len] in the btree given by cur.
@@ -154,19 +148,21 @@
xfs_extlen_t *reslen) /* result length */
{
xfs_agblock_t bno;
- xfs_extlen_t diff;
xfs_extlen_t len;
- if (args->alignment > 1 && foundlen >= args->minlen) {
- bno = roundup(foundbno, args->alignment);
- diff = bno - foundbno;
- len = diff >= foundlen ? 0 : foundlen - diff;
+ /* Trim busy sections out of found extent */
+ xfs_alloc_busy_trim(args, foundbno, foundlen, &bno, &len);
+
+ if (args->alignment > 1 && len >= args->minlen) {
+ xfs_agblock_t aligned_bno = roundup(bno, args->alignment);
+ xfs_extlen_t diff = aligned_bno - bno;
+
+ *resbno = aligned_bno;
+ *reslen = diff >= len ? 0 : len - diff;
} else {
- bno = foundbno;
- len = foundlen;
+ *resbno = bno;
+ *reslen = len;
}
- *resbno = bno;
- *reslen = len;
}
/*
@@ -280,7 +276,6 @@
return 1;
agf = XFS_BUF_TO_AGF(args->agbp);
diff = be32_to_cpu(agf->agf_freeblks)
- + be32_to_cpu(agf->agf_flcount)
- args->len - args->minleft;
if (diff >= 0)
return 1;
@@ -541,16 +536,8 @@
if (error)
return error;
- /*
- * Search the busylist for these blocks and mark the
- * transaction as synchronous if blocks are found. This
- * avoids the need to block due to a synchronous log
- * force to ensure correct ordering as the synchronous
- * transaction will guarantee that for us.
- */
- if (xfs_alloc_busy_search(args->mp, args->agno,
- args->agbno, args->len))
- xfs_trans_set_sync(args->tp);
+ ASSERT(!xfs_alloc_busy_search(args->mp, args->agno,
+ args->agbno, args->len));
}
if (!args->isfl) {
@@ -577,14 +564,14 @@
{
xfs_btree_cur_t *bno_cur;/* by block-number btree cursor */
xfs_btree_cur_t *cnt_cur;/* by count btree cursor */
- xfs_agblock_t end; /* end of allocated extent */
int error;
xfs_agblock_t fbno; /* start block of found extent */
- xfs_agblock_t fend; /* end block of found extent */
xfs_extlen_t flen; /* length of found extent */
+ xfs_agblock_t tbno; /* start block of trimmed extent */
+ xfs_extlen_t tlen; /* length of trimmed extent */
+ xfs_agblock_t tend; /* end block of trimmed extent */
+ xfs_agblock_t end; /* end of allocated extent */
int i; /* success/failure of operation */
- xfs_agblock_t maxend; /* end of maximal extent */
- xfs_agblock_t minend; /* end of minimal extent */
xfs_extlen_t rlen; /* length of returned extent */
ASSERT(args->alignment == 1);
@@ -614,14 +601,22 @@
goto error0;
XFS_WANT_CORRUPTED_GOTO(i == 1, error0);
ASSERT(fbno <= args->agbno);
- minend = args->agbno + args->minlen;
- maxend = args->agbno + args->maxlen;
- fend = fbno + flen;
/*
- * Give up if the freespace isn't long enough for the minimum request.
+ * Check for overlapping busy extents.
*/
- if (fend < minend)
+ xfs_alloc_busy_trim(args, fbno, flen, &tbno, &tlen);
+
+ /*
+ * Give up if the start of the extent is busy, or the freespace isn't
+ * long enough for the minimum request.
+ */
+ if (tbno > args->agbno)
+ goto not_found;
+ if (tlen < args->minlen)
+ goto not_found;
+ tend = tbno + tlen;
+ if (tend < args->agbno + args->minlen)
goto not_found;
/*
@@ -630,14 +625,14 @@
*
* Fix the length according to mod and prod if given.
*/
- end = XFS_AGBLOCK_MIN(fend, maxend);
+ end = XFS_AGBLOCK_MIN(tend, args->agbno + args->maxlen);
args->len = end - args->agbno;
xfs_alloc_fix_len(args);
if (!xfs_alloc_fix_minleft(args))
goto not_found;
rlen = args->len;
- ASSERT(args->agbno + rlen <= fend);
+ ASSERT(args->agbno + rlen <= tend);
end = args->agbno + rlen;
/*
@@ -686,11 +681,11 @@
struct xfs_btree_cur **scur, /* searching cursor */
xfs_agblock_t gdiff, /* difference for search comparison */
xfs_agblock_t *sbno, /* extent found by search */
- xfs_extlen_t *slen,
- xfs_extlen_t *slena, /* aligned length */
+ xfs_extlen_t *slen, /* extent length */
+ xfs_agblock_t *sbnoa, /* aligned extent found by search */
+ xfs_extlen_t *slena, /* aligned extent length */
int dir) /* 0 = search right, 1 = search left */
{
- xfs_agblock_t bno;
xfs_agblock_t new;
xfs_agblock_t sdiff;
int error;
@@ -708,16 +703,16 @@
if (error)
goto error0;
XFS_WANT_CORRUPTED_GOTO(i == 1, error0);
- xfs_alloc_compute_aligned(args, *sbno, *slen, &bno, slena);
+ xfs_alloc_compute_aligned(args, *sbno, *slen, sbnoa, slena);
/*
* The good extent is closer than this one.
*/
if (!dir) {
- if (bno >= args->agbno + gdiff)
+ if (*sbnoa >= args->agbno + gdiff)
goto out_use_good;
} else {
- if (bno <= args->agbno - gdiff)
+ if (*sbnoa <= args->agbno - gdiff)
goto out_use_good;
}
@@ -729,8 +724,8 @@
xfs_alloc_fix_len(args);
sdiff = xfs_alloc_compute_diff(args->agbno, args->len,
- args->alignment, *sbno,
- *slen, &new);
+ args->alignment, *sbnoa,
+ *slena, &new);
/*
* Choose closer size and invalidate other cursor.
@@ -780,7 +775,7 @@
xfs_agblock_t gtbnoa; /* aligned ... */
xfs_extlen_t gtdiff; /* difference to right side entry */
xfs_extlen_t gtlen; /* length of right side entry */
- xfs_extlen_t gtlena = 0; /* aligned ... */
+ xfs_extlen_t gtlena; /* aligned ... */
xfs_agblock_t gtnew; /* useful start bno of right side */
int error; /* error code */
int i; /* result code, temporary */
@@ -789,9 +784,10 @@
xfs_agblock_t ltbnoa; /* aligned ... */
xfs_extlen_t ltdiff; /* difference to left side entry */
xfs_extlen_t ltlen; /* length of left side entry */
- xfs_extlen_t ltlena = 0; /* aligned ... */
+ xfs_extlen_t ltlena; /* aligned ... */
xfs_agblock_t ltnew; /* useful start bno of left side */
xfs_extlen_t rlen; /* length of returned extent */
+ int forced = 0;
#if defined(DEBUG) && defined(__KERNEL__)
/*
* Randomly don't execute the first algorithm.
@@ -800,13 +796,20 @@
dofirst = random32() & 1;
#endif
+
+restart:
+ bno_cur_lt = NULL;
+ bno_cur_gt = NULL;
+ ltlen = 0;
+ gtlena = 0;
+ ltlena = 0;
+
/*
* Get a cursor for the by-size btree.
*/
cnt_cur = xfs_allocbt_init_cursor(args->mp, args->tp, args->agbp,
args->agno, XFS_BTNUM_CNT);
- ltlen = 0;
- bno_cur_lt = bno_cur_gt = NULL;
+
/*
* See if there are any free extents as big as maxlen.
*/
@@ -822,11 +825,13 @@
goto error0;
if (i == 0 || ltlen == 0) {
xfs_btree_del_cursor(cnt_cur, XFS_BTREE_NOERROR);
+ trace_xfs_alloc_near_noentry(args);
return 0;
}
ASSERT(i == 1);
}
args->wasfromfl = 0;
+
/*
* First algorithm.
* If the requested extent is large wrt the freespaces available
@@ -890,7 +895,7 @@
if (args->len < blen)
continue;
ltdiff = xfs_alloc_compute_diff(args->agbno, args->len,
- args->alignment, ltbno, ltlen, <new);
+ args->alignment, ltbnoa, ltlena, <new);
if (ltnew != NULLAGBLOCK &&
(args->len > blen || ltdiff < bdiff)) {
bdiff = ltdiff;
@@ -1042,11 +1047,12 @@
args->len = XFS_EXTLEN_MIN(ltlena, args->maxlen);
xfs_alloc_fix_len(args);
ltdiff = xfs_alloc_compute_diff(args->agbno, args->len,
- args->alignment, ltbno, ltlen, <new);
+ args->alignment, ltbnoa, ltlena, <new);
error = xfs_alloc_find_best_extent(args,
&bno_cur_lt, &bno_cur_gt,
- ltdiff, >bno, >len, >lena,
+ ltdiff, >bno, >len,
+ >bnoa, >lena,
0 /* search right */);
} else {
ASSERT(gtlena >= args->minlen);
@@ -1057,11 +1063,12 @@
args->len = XFS_EXTLEN_MIN(gtlena, args->maxlen);
xfs_alloc_fix_len(args);
gtdiff = xfs_alloc_compute_diff(args->agbno, args->len,
- args->alignment, gtbno, gtlen, >new);
+ args->alignment, gtbnoa, gtlena, >new);
error = xfs_alloc_find_best_extent(args,
&bno_cur_gt, &bno_cur_lt,
- gtdiff, <bno, <len, <lena,
+ gtdiff, <bno, <len,
+ <bnoa, <lena,
1 /* search left */);
}
@@ -1073,6 +1080,12 @@
* If we couldn't get anything, give up.
*/
if (bno_cur_lt == NULL && bno_cur_gt == NULL) {
+ if (!forced++) {
+ trace_xfs_alloc_near_busy(args);
+ xfs_log_force(args->mp, XFS_LOG_SYNC);
+ goto restart;
+ }
+
trace_xfs_alloc_size_neither(args);
args->agbno = NULLAGBLOCK;
return 0;
@@ -1107,12 +1120,13 @@
return 0;
}
rlen = args->len;
- (void)xfs_alloc_compute_diff(args->agbno, rlen, args->alignment, ltbno,
- ltlen, <new);
+ (void)xfs_alloc_compute_diff(args->agbno, rlen, args->alignment,
+ ltbnoa, ltlena, <new);
ASSERT(ltnew >= ltbno);
- ASSERT(ltnew + rlen <= ltbno + ltlen);
+ ASSERT(ltnew + rlen <= ltbnoa + ltlena);
ASSERT(ltnew + rlen <= be32_to_cpu(XFS_BUF_TO_AGF(args->agbp)->agf_length));
args->agbno = ltnew;
+
if ((error = xfs_alloc_fixup_trees(cnt_cur, bno_cur_lt, ltbno, ltlen,
ltnew, rlen, XFSA_FIXUP_BNO_OK)))
goto error0;
@@ -1155,26 +1169,35 @@
int i; /* temp status variable */
xfs_agblock_t rbno; /* returned block number */
xfs_extlen_t rlen; /* length of returned extent */
+ int forced = 0;
+restart:
/*
* Allocate and initialize a cursor for the by-size btree.
*/
cnt_cur = xfs_allocbt_init_cursor(args->mp, args->tp, args->agbp,
args->agno, XFS_BTNUM_CNT);
bno_cur = NULL;
+
/*
* Look for an entry >= maxlen+alignment-1 blocks.
*/
if ((error = xfs_alloc_lookup_ge(cnt_cur, 0,
args->maxlen + args->alignment - 1, &i)))
goto error0;
+
/*
- * If none, then pick up the last entry in the tree unless the
- * tree is empty.
+ * If none or we have busy extents that we cannot allocate from, then
+ * we have to settle for a smaller extent. In the case that there are
+ * no large extents, this will return the last entry in the tree unless
+ * the tree is empty. In the case that there are only busy large
+ * extents, this will return the largest small extent unless there
+ * are no smaller extents available.
*/
- if (!i) {
- if ((error = xfs_alloc_ag_vextent_small(args, cnt_cur, &fbno,
- &flen, &i)))
+ if (!i || forced > 1) {
+ error = xfs_alloc_ag_vextent_small(args, cnt_cur,
+ &fbno, &flen, &i);
+ if (error)
goto error0;
if (i == 0 || flen == 0) {
xfs_btree_del_cursor(cnt_cur, XFS_BTREE_NOERROR);
@@ -1182,22 +1205,56 @@
return 0;
}
ASSERT(i == 1);
+ xfs_alloc_compute_aligned(args, fbno, flen, &rbno, &rlen);
+ } else {
+ /*
+ * Search for a non-busy extent that is large enough.
+ * If we are at low space, don't check, or if we fall of
+ * the end of the btree, turn off the busy check and
+ * restart.
+ */
+ for (;;) {
+ error = xfs_alloc_get_rec(cnt_cur, &fbno, &flen, &i);
+ if (error)
+ goto error0;
+ XFS_WANT_CORRUPTED_GOTO(i == 1, error0);
+
+ xfs_alloc_compute_aligned(args, fbno, flen,
+ &rbno, &rlen);
+
+ if (rlen >= args->maxlen)
+ break;
+
+ error = xfs_btree_increment(cnt_cur, 0, &i);
+ if (error)
+ goto error0;
+ if (i == 0) {
+ /*
+ * Our only valid extents must have been busy.
+ * Make it unbusy by forcing the log out and
+ * retrying. If we've been here before, forcing
+ * the log isn't making the extents available,
+ * which means they have probably been freed in
+ * this transaction. In that case, we have to
+ * give up on them and we'll attempt a minlen
+ * allocation the next time around.
+ */
+ xfs_btree_del_cursor(cnt_cur,
+ XFS_BTREE_NOERROR);
+ trace_xfs_alloc_size_busy(args);
+ if (!forced++)
+ xfs_log_force(args->mp, XFS_LOG_SYNC);
+ goto restart;
+ }
+ }
}
- /*
- * There's a freespace as big as maxlen+alignment-1, get it.
- */
- else {
- if ((error = xfs_alloc_get_rec(cnt_cur, &fbno, &flen, &i)))
- goto error0;
- XFS_WANT_CORRUPTED_GOTO(i == 1, error0);
- }
+
/*
* In the first case above, we got the last entry in the
* by-size btree. Now we check to see if the space hits maxlen
* once aligned; if not, we search left for something better.
* This can't happen in the second case above.
*/
- xfs_alloc_compute_aligned(args, fbno, flen, &rbno, &rlen);
rlen = XFS_EXTLEN_MIN(args->maxlen, rlen);
XFS_WANT_CORRUPTED_GOTO(rlen == 0 ||
(rlen <= flen && rbno + rlen <= fbno + flen), error0);
@@ -1251,13 +1308,19 @@
* Fix up the length.
*/
args->len = rlen;
- xfs_alloc_fix_len(args);
- if (rlen < args->minlen || !xfs_alloc_fix_minleft(args)) {
- xfs_btree_del_cursor(cnt_cur, XFS_BTREE_NOERROR);
- trace_xfs_alloc_size_nominleft(args);
- args->agbno = NULLAGBLOCK;
- return 0;
+ if (rlen < args->minlen) {
+ if (!forced++) {
+ xfs_btree_del_cursor(cnt_cur, XFS_BTREE_NOERROR);
+ trace_xfs_alloc_size_busy(args);
+ xfs_log_force(args->mp, XFS_LOG_SYNC);
+ goto restart;
+ }
+ goto out_nominleft;
}
+ xfs_alloc_fix_len(args);
+
+ if (!xfs_alloc_fix_minleft(args))
+ goto out_nominleft;
rlen = args->len;
XFS_WANT_CORRUPTED_GOTO(rlen <= flen, error0);
/*
@@ -1287,6 +1350,12 @@
if (bno_cur)
xfs_btree_del_cursor(bno_cur, XFS_BTREE_ERROR);
return error;
+
+out_nominleft:
+ xfs_btree_del_cursor(cnt_cur, XFS_BTREE_NOERROR);
+ trace_xfs_alloc_size_nominleft(args);
+ args->agbno = NULLAGBLOCK;
+ return 0;
}
/*
@@ -1326,6 +1395,9 @@
if (error)
goto error0;
if (fbno != NULLAGBLOCK) {
+ xfs_alloc_busy_reuse(args->mp, args->agno, fbno, 1,
+ args->userdata);
+
if (args->userdata) {
xfs_buf_t *bp;
@@ -1617,18 +1689,6 @@
trace_xfs_free_extent(mp, agno, bno, len, isfl, haveleft, haveright);
- /*
- * Since blocks move to the free list without the coordination
- * used in xfs_bmap_finish, we can't allow block to be available
- * for reallocation and non-transaction writing (user data)
- * until we know that the transaction that moved it to the free
- * list is permanently on disk. We track the blocks by declaring
- * these blocks as "busy"; the busy list is maintained on a per-ag
- * basis and each transaction records which entries should be removed
- * when the iclog commits to disk. If a busy block is allocated,
- * the iclog is pushed up to the LSN that freed the block.
- */
- xfs_alloc_busy_insert(tp, agno, bno, len);
return 0;
error0:
@@ -1923,21 +1983,6 @@
xfs_alloc_log_agf(tp, agbp, logflags);
*bnop = bno;
- /*
- * As blocks are freed, they are added to the per-ag busy list and
- * remain there until the freeing transaction is committed to disk.
- * Now that we have allocated blocks, this list must be searched to see
- * if a block is being reused. If one is, then the freeing transaction
- * must be pushed to disk before this transaction.
- *
- * We do this by setting the current transaction to a sync transaction
- * which guarantees that the freeing transaction is on disk before this
- * transaction. This is done instead of a synchronous log force here so
- * that we don't sit and wait with the AGF locked in the transaction
- * during the log force.
- */
- if (xfs_alloc_busy_search(mp, be32_to_cpu(agf->agf_seqno), bno, 1))
- xfs_trans_set_sync(tp);
return 0;
}
@@ -2423,105 +2468,13 @@
}
error = xfs_free_ag_extent(tp, args.agbp, args.agno, args.agbno, len, 0);
+ if (!error)
+ xfs_alloc_busy_insert(tp, args.agno, args.agbno, len);
error0:
xfs_perag_put(args.pag);
return error;
}
-
-/*
- * AG Busy list management
- * The busy list contains block ranges that have been freed but whose
- * transactions have not yet hit disk. If any block listed in a busy
- * list is reused, the transaction that freed it must be forced to disk
- * before continuing to use the block.
- *
- * xfs_alloc_busy_insert - add to the per-ag busy list
- * xfs_alloc_busy_clear - remove an item from the per-ag busy list
- * xfs_alloc_busy_search - search for a busy extent
- */
-
-/*
- * Insert a new extent into the busy tree.
- *
- * The busy extent tree is indexed by the start block of the busy extent.
- * there can be multiple overlapping ranges in the busy extent tree but only
- * ever one entry at a given start block. The reason for this is that
- * multi-block extents can be freed, then smaller chunks of that extent
- * allocated and freed again before the first transaction commit is on disk.
- * If the exact same start block is freed a second time, we have to wait for
- * that busy extent to pass out of the tree before the new extent is inserted.
- * There are two main cases we have to handle here.
- *
- * The first case is a transaction that triggers a "free - allocate - free"
- * cycle. This can occur during btree manipulations as a btree block is freed
- * to the freelist, then allocated from the free list, then freed again. In
- * this case, the second extxpnet free is what triggers the duplicate and as
- * such the transaction IDs should match. Because the extent was allocated in
- * this transaction, the transaction must be marked as synchronous. This is
- * true for all cases where the free/alloc/free occurs in the one transaction,
- * hence the addition of the ASSERT(tp->t_flags & XFS_TRANS_SYNC) to this case.
- * This serves to catch violations of the second case quite effectively.
- *
- * The second case is where the free/alloc/free occur in different
- * transactions. In this case, the thread freeing the extent the second time
- * can't mark the extent busy immediately because it is already tracked in a
- * transaction that may be committing. When the log commit for the existing
- * busy extent completes, the busy extent will be removed from the tree. If we
- * allow the second busy insert to continue using that busy extent structure,
- * it can be freed before this transaction is safely in the log. Hence our
- * only option in this case is to force the log to remove the existing busy
- * extent from the list before we insert the new one with the current
- * transaction ID.
- *
- * The problem we are trying to avoid in the free-alloc-free in separate
- * transactions is most easily described with a timeline:
- *
- * Thread 1 Thread 2 Thread 3 xfslogd
- * xact alloc
- * free X
- * mark busy
- * commit xact
- * free xact
- * xact alloc
- * alloc X
- * busy search
- * mark xact sync
- * commit xact
- * free xact
- * force log
- * checkpoint starts
- * ....
- * xact alloc
- * free X
- * mark busy
- * finds match
- * *** KABOOM! ***
- * ....
- * log IO completes
- * unbusy X
- * checkpoint completes
- *
- * By issuing a log force in thread 3 @ "KABOOM", the thread will block until
- * the checkpoint completes, and the busy extent it matched will have been
- * removed from the tree when it is woken. Hence it can then continue safely.
- *
- * However, to ensure this matching process is robust, we need to use the
- * transaction ID for identifying transaction, as delayed logging results in
- * the busy extent and transaction lifecycles being different. i.e. the busy
- * extent is active for a lot longer than the transaction. Hence the
- * transaction structure can be freed and reallocated, then mark the same
- * extent busy again in the new transaction. In this case the new transaction
- * will have a different tid but can have the same address, and hence we need
- * to check against the tid.
- *
- * Future: for delayed logging, we could avoid the log force if the extent was
- * first freed in the current checkpoint sequence. This, however, requires the
- * ability to pin the current checkpoint in memory until this transaction
- * commits to ensure that both the original free and the current one combine
- * logically into the one checkpoint. If the checkpoint sequences are
- * different, however, we still need to wait on a log force.
- */
void
xfs_alloc_busy_insert(
struct xfs_trans *tp,
@@ -2533,9 +2486,7 @@
struct xfs_busy_extent *busyp;
struct xfs_perag *pag;
struct rb_node **rbp;
- struct rb_node *parent;
- int match;
-
+ struct rb_node *parent = NULL;
new = kmem_zalloc(sizeof(struct xfs_busy_extent), KM_MAYFAIL);
if (!new) {
@@ -2544,7 +2495,7 @@
* block, make this a synchronous transaction to insure that
* the block is not reused before this transaction commits.
*/
- trace_xfs_alloc_busy(tp, agno, bno, len, 1);
+ trace_xfs_alloc_busy_enomem(tp->t_mountp, agno, bno, len);
xfs_trans_set_sync(tp);
return;
}
@@ -2552,66 +2503,28 @@
new->agno = agno;
new->bno = bno;
new->length = len;
- new->tid = xfs_log_get_trans_ident(tp);
-
INIT_LIST_HEAD(&new->list);
/* trace before insert to be able to see failed inserts */
- trace_xfs_alloc_busy(tp, agno, bno, len, 0);
+ trace_xfs_alloc_busy(tp->t_mountp, agno, bno, len);
pag = xfs_perag_get(tp->t_mountp, new->agno);
-restart:
spin_lock(&pag->pagb_lock);
rbp = &pag->pagb_tree.rb_node;
- parent = NULL;
- busyp = NULL;
- match = 0;
- while (*rbp && match >= 0) {
+ while (*rbp) {
parent = *rbp;
busyp = rb_entry(parent, struct xfs_busy_extent, rb_node);
if (new->bno < busyp->bno) {
- /* may overlap, but exact start block is lower */
rbp = &(*rbp)->rb_left;
- if (new->bno + new->length > busyp->bno)
- match = busyp->tid == new->tid ? 1 : -1;
+ ASSERT(new->bno + new->length <= busyp->bno);
} else if (new->bno > busyp->bno) {
- /* may overlap, but exact start block is higher */
rbp = &(*rbp)->rb_right;
- if (bno < busyp->bno + busyp->length)
- match = busyp->tid == new->tid ? 1 : -1;
+ ASSERT(bno >= busyp->bno + busyp->length);
} else {
- match = busyp->tid == new->tid ? 1 : -1;
- break;
+ ASSERT(0);
}
}
- if (match < 0) {
- /* overlap marked busy in different transaction */
- spin_unlock(&pag->pagb_lock);
- xfs_log_force(tp->t_mountp, XFS_LOG_SYNC);
- goto restart;
- }
- if (match > 0) {
- /*
- * overlap marked busy in same transaction. Update if exact
- * start block match, otherwise combine the busy extents into
- * a single range.
- */
- if (busyp->bno == new->bno) {
- busyp->length = max(busyp->length, new->length);
- spin_unlock(&pag->pagb_lock);
- ASSERT(tp->t_flags & XFS_TRANS_SYNC);
- xfs_perag_put(pag);
- kmem_free(new);
- return;
- }
- rb_erase(&busyp->rb_node, &pag->pagb_tree);
- new->length = max(busyp->bno + busyp->length,
- new->bno + new->length) -
- min(busyp->bno, new->bno);
- new->bno = min(busyp->bno, new->bno);
- } else
- busyp = NULL;
rb_link_node(&new->rb_node, parent, rbp);
rb_insert_color(&new->rb_node, &pag->pagb_tree);
@@ -2619,7 +2532,6 @@
list_add(&new->list, &tp->t_busy);
spin_unlock(&pag->pagb_lock);
xfs_perag_put(pag);
- kmem_free(busyp);
}
/*
@@ -2668,31 +2580,443 @@
}
}
spin_unlock(&pag->pagb_lock);
- trace_xfs_alloc_busysearch(mp, agno, bno, len, !!match);
xfs_perag_put(pag);
return match;
}
+/*
+ * The found free extent [fbno, fend] overlaps part or all of the given busy
+ * extent. If the overlap covers the beginning, the end, or all of the busy
+ * extent, the overlapping portion can be made unbusy and used for the
+ * allocation. We can't split a busy extent because we can't modify a
+ * transaction/CIL context busy list, but we can update an entries block
+ * number or length.
+ *
+ * Returns true if the extent can safely be reused, or false if the search
+ * needs to be restarted.
+ */
+STATIC bool
+xfs_alloc_busy_update_extent(
+ struct xfs_mount *mp,
+ struct xfs_perag *pag,
+ struct xfs_busy_extent *busyp,
+ xfs_agblock_t fbno,
+ xfs_extlen_t flen,
+ bool userdata)
+{
+ xfs_agblock_t fend = fbno + flen;
+ xfs_agblock_t bbno = busyp->bno;
+ xfs_agblock_t bend = bbno + busyp->length;
+
+ /*
+ * If there is a busy extent overlapping a user allocation, we have
+ * no choice but to force the log and retry the search.
+ *
+ * Fortunately this does not happen during normal operation, but
+ * only if the filesystem is very low on space and has to dip into
+ * the AGFL for normal allocations.
+ */
+ if (userdata)
+ goto out_force_log;
+
+ if (bbno < fbno && bend > fend) {
+ /*
+ * Case 1:
+ * bbno bend
+ * +BBBBBBBBBBBBBBBBB+
+ * +---------+
+ * fbno fend
+ */
+
+ /*
+ * We would have to split the busy extent to be able to track
+ * it correct, which we cannot do because we would have to
+ * modify the list of busy extents attached to the transaction
+ * or CIL context, which is immutable.
+ *
+ * Force out the log to clear the busy extent and retry the
+ * search.
+ */
+ goto out_force_log;
+ } else if (bbno >= fbno && bend <= fend) {
+ /*
+ * Case 2:
+ * bbno bend
+ * +BBBBBBBBBBBBBBBBB+
+ * +-----------------+
+ * fbno fend
+ *
+ * Case 3:
+ * bbno bend
+ * +BBBBBBBBBBBBBBBBB+
+ * +--------------------------+
+ * fbno fend
+ *
+ * Case 4:
+ * bbno bend
+ * +BBBBBBBBBBBBBBBBB+
+ * +--------------------------+
+ * fbno fend
+ *
+ * Case 5:
+ * bbno bend
+ * +BBBBBBBBBBBBBBBBB+
+ * +-----------------------------------+
+ * fbno fend
+ *
+ */
+
+ /*
+ * The busy extent is fully covered by the extent we are
+ * allocating, and can simply be removed from the rbtree.
+ * However we cannot remove it from the immutable list
+ * tracking busy extents in the transaction or CIL context,
+ * so set the length to zero to mark it invalid.
+ *
+ * We also need to restart the busy extent search from the
+ * tree root, because erasing the node can rearrange the
+ * tree topology.
+ */
+ rb_erase(&busyp->rb_node, &pag->pagb_tree);
+ busyp->length = 0;
+ return false;
+ } else if (fend < bend) {
+ /*
+ * Case 6:
+ * bbno bend
+ * +BBBBBBBBBBBBBBBBB+
+ * +---------+
+ * fbno fend
+ *
+ * Case 7:
+ * bbno bend
+ * +BBBBBBBBBBBBBBBBB+
+ * +------------------+
+ * fbno fend
+ *
+ */
+ busyp->bno = fend;
+ } else if (bbno < fbno) {
+ /*
+ * Case 8:
+ * bbno bend
+ * +BBBBBBBBBBBBBBBBB+
+ * +-------------+
+ * fbno fend
+ *
+ * Case 9:
+ * bbno bend
+ * +BBBBBBBBBBBBBBBBB+
+ * +----------------------+
+ * fbno fend
+ */
+ busyp->length = fbno - busyp->bno;
+ } else {
+ ASSERT(0);
+ }
+
+ trace_xfs_alloc_busy_reuse(mp, pag->pag_agno, fbno, flen);
+ return true;
+
+out_force_log:
+ spin_unlock(&pag->pagb_lock);
+ xfs_log_force(mp, XFS_LOG_SYNC);
+ trace_xfs_alloc_busy_force(mp, pag->pag_agno, fbno, flen);
+ spin_lock(&pag->pagb_lock);
+ return false;
+}
+
+
+/*
+ * For a given extent [fbno, flen], make sure we can reuse it safely.
+ */
+void
+xfs_alloc_busy_reuse(
+ struct xfs_mount *mp,
+ xfs_agnumber_t agno,
+ xfs_agblock_t fbno,
+ xfs_extlen_t flen,
+ bool userdata)
+{
+ struct xfs_perag *pag;
+ struct rb_node *rbp;
+
+ ASSERT(flen > 0);
+
+ pag = xfs_perag_get(mp, agno);
+ spin_lock(&pag->pagb_lock);
+restart:
+ rbp = pag->pagb_tree.rb_node;
+ while (rbp) {
+ struct xfs_busy_extent *busyp =
+ rb_entry(rbp, struct xfs_busy_extent, rb_node);
+ xfs_agblock_t bbno = busyp->bno;
+ xfs_agblock_t bend = bbno + busyp->length;
+
+ if (fbno + flen <= bbno) {
+ rbp = rbp->rb_left;
+ continue;
+ } else if (fbno >= bend) {
+ rbp = rbp->rb_right;
+ continue;
+ }
+
+ if (!xfs_alloc_busy_update_extent(mp, pag, busyp, fbno, flen,
+ userdata))
+ goto restart;
+ }
+ spin_unlock(&pag->pagb_lock);
+ xfs_perag_put(pag);
+}
+
+/*
+ * For a given extent [fbno, flen], search the busy extent list to find a
+ * subset of the extent that is not busy. If *rlen is smaller than
+ * args->minlen no suitable extent could be found, and the higher level
+ * code needs to force out the log and retry the allocation.
+ */
+STATIC void
+xfs_alloc_busy_trim(
+ struct xfs_alloc_arg *args,
+ xfs_agblock_t bno,
+ xfs_extlen_t len,
+ xfs_agblock_t *rbno,
+ xfs_extlen_t *rlen)
+{
+ xfs_agblock_t fbno;
+ xfs_extlen_t flen;
+ struct rb_node *rbp;
+
+ ASSERT(len > 0);
+
+ spin_lock(&args->pag->pagb_lock);
+restart:
+ fbno = bno;
+ flen = len;
+ rbp = args->pag->pagb_tree.rb_node;
+ while (rbp && flen >= args->minlen) {
+ struct xfs_busy_extent *busyp =
+ rb_entry(rbp, struct xfs_busy_extent, rb_node);
+ xfs_agblock_t fend = fbno + flen;
+ xfs_agblock_t bbno = busyp->bno;
+ xfs_agblock_t bend = bbno + busyp->length;
+
+ if (fend <= bbno) {
+ rbp = rbp->rb_left;
+ continue;
+ } else if (fbno >= bend) {
+ rbp = rbp->rb_right;
+ continue;
+ }
+
+ /*
+ * If this is a metadata allocation, try to reuse the busy
+ * extent instead of trimming the allocation.
+ */
+ if (!args->userdata) {
+ if (!xfs_alloc_busy_update_extent(args->mp, args->pag,
+ busyp, fbno, flen,
+ false))
+ goto restart;
+ continue;
+ }
+
+ if (bbno <= fbno) {
+ /* start overlap */
+
+ /*
+ * Case 1:
+ * bbno bend
+ * +BBBBBBBBBBBBBBBBB+
+ * +---------+
+ * fbno fend
+ *
+ * Case 2:
+ * bbno bend
+ * +BBBBBBBBBBBBBBBBB+
+ * +-------------+
+ * fbno fend
+ *
+ * Case 3:
+ * bbno bend
+ * +BBBBBBBBBBBBBBBBB+
+ * +-------------+
+ * fbno fend
+ *
+ * Case 4:
+ * bbno bend
+ * +BBBBBBBBBBBBBBBBB+
+ * +-----------------+
+ * fbno fend
+ *
+ * No unbusy region in extent, return failure.
+ */
+ if (fend <= bend)
+ goto fail;
+
+ /*
+ * Case 5:
+ * bbno bend
+ * +BBBBBBBBBBBBBBBBB+
+ * +----------------------+
+ * fbno fend
+ *
+ * Case 6:
+ * bbno bend
+ * +BBBBBBBBBBBBBBBBB+
+ * +--------------------------+
+ * fbno fend
+ *
+ * Needs to be trimmed to:
+ * +-------+
+ * fbno fend
+ */
+ fbno = bend;
+ } else if (bend >= fend) {
+ /* end overlap */
+
+ /*
+ * Case 7:
+ * bbno bend
+ * +BBBBBBBBBBBBBBBBB+
+ * +------------------+
+ * fbno fend
+ *
+ * Case 8:
+ * bbno bend
+ * +BBBBBBBBBBBBBBBBB+
+ * +--------------------------+
+ * fbno fend
+ *
+ * Needs to be trimmed to:
+ * +-------+
+ * fbno fend
+ */
+ fend = bbno;
+ } else {
+ /* middle overlap */
+
+ /*
+ * Case 9:
+ * bbno bend
+ * +BBBBBBBBBBBBBBBBB+
+ * +-----------------------------------+
+ * fbno fend
+ *
+ * Can be trimmed to:
+ * +-------+ OR +-------+
+ * fbno fend fbno fend
+ *
+ * Backward allocation leads to significant
+ * fragmentation of directories, which degrades
+ * directory performance, therefore we always want to
+ * choose the option that produces forward allocation
+ * patterns.
+ * Preferring the lower bno extent will make the next
+ * request use "fend" as the start of the next
+ * allocation; if the segment is no longer busy at
+ * that point, we'll get a contiguous allocation, but
+ * even if it is still busy, we will get a forward
+ * allocation.
+ * We try to avoid choosing the segment at "bend",
+ * because that can lead to the next allocation
+ * taking the segment at "fbno", which would be a
+ * backward allocation. We only use the segment at
+ * "fbno" if it is much larger than the current
+ * requested size, because in that case there's a
+ * good chance subsequent allocations will be
+ * contiguous.
+ */
+ if (bbno - fbno >= args->maxlen) {
+ /* left candidate fits perfect */
+ fend = bbno;
+ } else if (fend - bend >= args->maxlen * 4) {
+ /* right candidate has enough free space */
+ fbno = bend;
+ } else if (bbno - fbno >= args->minlen) {
+ /* left candidate fits minimum requirement */
+ fend = bbno;
+ } else {
+ goto fail;
+ }
+ }
+
+ flen = fend - fbno;
+ }
+ spin_unlock(&args->pag->pagb_lock);
+
+ if (fbno != bno || flen != len) {
+ trace_xfs_alloc_busy_trim(args->mp, args->agno, bno, len,
+ fbno, flen);
+ }
+ *rbno = fbno;
+ *rlen = flen;
+ return;
+fail:
+ /*
+ * Return a zero extent length as failure indications. All callers
+ * re-check if the trimmed extent satisfies the minlen requirement.
+ */
+ spin_unlock(&args->pag->pagb_lock);
+ trace_xfs_alloc_busy_trim(args->mp, args->agno, bno, len, fbno, 0);
+ *rbno = fbno;
+ *rlen = 0;
+}
+
+static void
+xfs_alloc_busy_clear_one(
+ struct xfs_mount *mp,
+ struct xfs_perag *pag,
+ struct xfs_busy_extent *busyp)
+{
+ if (busyp->length) {
+ trace_xfs_alloc_busy_clear(mp, busyp->agno, busyp->bno,
+ busyp->length);
+ rb_erase(&busyp->rb_node, &pag->pagb_tree);
+ }
+
+ list_del_init(&busyp->list);
+ kmem_free(busyp);
+}
+
void
xfs_alloc_busy_clear(
struct xfs_mount *mp,
- struct xfs_busy_extent *busyp)
+ struct list_head *list)
{
- struct xfs_perag *pag;
+ struct xfs_busy_extent *busyp, *n;
+ struct xfs_perag *pag = NULL;
+ xfs_agnumber_t agno = NULLAGNUMBER;
- trace_xfs_alloc_unbusy(mp, busyp->agno, busyp->bno,
- busyp->length);
+ list_for_each_entry_safe(busyp, n, list, list) {
+ if (busyp->agno != agno) {
+ if (pag) {
+ spin_unlock(&pag->pagb_lock);
+ xfs_perag_put(pag);
+ }
+ pag = xfs_perag_get(mp, busyp->agno);
+ spin_lock(&pag->pagb_lock);
+ agno = busyp->agno;
+ }
- ASSERT(xfs_alloc_busy_search(mp, busyp->agno, busyp->bno,
- busyp->length) == 1);
+ xfs_alloc_busy_clear_one(mp, pag, busyp);
+ }
- list_del_init(&busyp->list);
+ if (pag) {
+ spin_unlock(&pag->pagb_lock);
+ xfs_perag_put(pag);
+ }
+}
- pag = xfs_perag_get(mp, busyp->agno);
- spin_lock(&pag->pagb_lock);
- rb_erase(&busyp->rb_node, &pag->pagb_tree);
- spin_unlock(&pag->pagb_lock);
- xfs_perag_put(pag);
-
- kmem_free(busyp);
+/*
+ * Callback for list_sort to sort busy extents by the AG they reside in.
+ */
+int
+xfs_busy_extent_ag_cmp(
+ void *priv,
+ struct list_head *a,
+ struct list_head *b)
+{
+ return container_of(a, struct xfs_busy_extent, list)->agno -
+ container_of(b, struct xfs_busy_extent, list)->agno;
}
diff --git a/fs/xfs/xfs_alloc.h b/fs/xfs/xfs_alloc.h
index d0b3bc7..240ad28 100644
--- a/fs/xfs/xfs_alloc.h
+++ b/fs/xfs/xfs_alloc.h
@@ -140,11 +140,24 @@
xfs_agblock_t bno, xfs_extlen_t len);
void
-xfs_alloc_busy_clear(struct xfs_mount *mp, struct xfs_busy_extent *busyp);
+xfs_alloc_busy_clear(struct xfs_mount *mp, struct list_head *list);
int
xfs_alloc_busy_search(struct xfs_mount *mp, xfs_agnumber_t agno,
xfs_agblock_t bno, xfs_extlen_t len);
+
+void
+xfs_alloc_busy_reuse(struct xfs_mount *mp, xfs_agnumber_t agno,
+ xfs_agblock_t fbno, xfs_extlen_t flen, bool userdata);
+
+int
+xfs_busy_extent_ag_cmp(void *priv, struct list_head *a, struct list_head *b);
+
+static inline void xfs_alloc_busy_sort(struct list_head *list)
+{
+ list_sort(NULL, list, xfs_busy_extent_ag_cmp);
+}
+
#endif /* __KERNEL__ */
/*
diff --git a/fs/xfs/xfs_alloc_btree.c b/fs/xfs/xfs_alloc_btree.c
index 3916925..8b469d5 100644
--- a/fs/xfs/xfs_alloc_btree.c
+++ b/fs/xfs/xfs_alloc_btree.c
@@ -95,6 +95,8 @@
return 0;
}
+ xfs_alloc_busy_reuse(cur->bc_mp, cur->bc_private.a.agno, bno, 1, false);
+
xfs_trans_agbtree_delta(cur->bc_tp, 1);
new->s = cpu_to_be32(bno);
@@ -118,17 +120,6 @@
if (error)
return error;
- /*
- * Since blocks move to the free list without the coordination used in
- * xfs_bmap_finish, we can't allow block to be available for
- * reallocation and non-transaction writing (user data) until we know
- * that the transaction that moved it to the free list is permanently
- * on disk. We track the blocks by declaring these blocks as "busy";
- * the busy list is maintained on a per-ag basis and each transaction
- * records which entries should be removed when the iclog commits to
- * disk. If a busy block is allocated, the iclog is pushed up to the
- * LSN that freed the block.
- */
xfs_alloc_busy_insert(cur->bc_tp, be32_to_cpu(agf->agf_seqno), bno, 1);
xfs_trans_agbtree_delta(cur->bc_tp, -1);
return 0;
diff --git a/fs/xfs/xfs_dfrag.c b/fs/xfs/xfs_dfrag.c
index be628677..9a84a85 100644
--- a/fs/xfs/xfs_dfrag.c
+++ b/fs/xfs/xfs_dfrag.c
@@ -202,7 +202,7 @@
xfs_inode_t *tip, /* tmp inode */
xfs_swapext_t *sxp)
{
- xfs_mount_t *mp;
+ xfs_mount_t *mp = ip->i_mount;
xfs_trans_t *tp;
xfs_bstat_t *sbp = &sxp->sx_stat;
xfs_ifork_t *tempifp, *ifp, *tifp;
@@ -212,16 +212,12 @@
int taforkblks = 0;
__uint64_t tmp;
- mp = ip->i_mount;
-
tempifp = kmem_alloc(sizeof(xfs_ifork_t), KM_MAYFAIL);
if (!tempifp) {
error = XFS_ERROR(ENOMEM);
goto out;
}
- sbp = &sxp->sx_stat;
-
/*
* we have to do two separate lock calls here to keep lockdep
* happy. If we try to get all the locks in one call, lock will
diff --git a/fs/xfs/xfs_inode.c b/fs/xfs/xfs_inode.c
index d11ce61..c8e3349 100644
--- a/fs/xfs/xfs_inode.c
+++ b/fs/xfs/xfs_inode.c
@@ -1354,7 +1354,7 @@
return 0;
}
last_byte = xfs_file_last_byte(ip);
- trace_xfs_itruncate_start(ip, flags, new_size, toss_start, last_byte);
+ trace_xfs_itruncate_start(ip, new_size, flags, toss_start, last_byte);
if (last_byte > toss_start) {
if (flags & XFS_ITRUNC_DEFINITE) {
xfs_tosspages(ip, toss_start,
diff --git a/fs/xfs/xfs_inode_item.c b/fs/xfs/xfs_inode_item.c
index 576fdfe..09983a3 100644
--- a/fs/xfs/xfs_inode_item.c
+++ b/fs/xfs/xfs_inode_item.c
@@ -970,7 +970,6 @@
{
xfs_inode_log_item_t *iip = ip->i_itemp;
- iip = ip->i_itemp;
if (iip) {
struct xfs_ail *ailp = iip->ili_item.li_ailp;
if (iip->ili_item.li_flags & XFS_LI_IN_AIL) {
diff --git a/fs/xfs/xfs_log.c b/fs/xfs/xfs_log.c
index b612ce4..2119302 100644
--- a/fs/xfs/xfs_log.c
+++ b/fs/xfs/xfs_log.c
@@ -1449,6 +1449,13 @@
xlog_cil_destroy(log);
+ /*
+ * always need to ensure that the extra buffer does not point to memory
+ * owned by another log buffer before we free it.
+ */
+ xfs_buf_set_empty(log->l_xbuf, log->l_iclog_size);
+ xfs_buf_free(log->l_xbuf);
+
iclog = log->l_iclog;
for (i=0; i<log->l_iclog_bufs; i++) {
xfs_buf_free(iclog->ic_bp);
@@ -1458,7 +1465,6 @@
}
spinlock_destroy(&log->l_icloglock);
- xfs_buf_free(log->l_xbuf);
log->l_mp->m_log = NULL;
kmem_free(log);
} /* xlog_dealloc_log */
@@ -3248,13 +3254,6 @@
return ticket;
}
-xlog_tid_t
-xfs_log_get_trans_ident(
- struct xfs_trans *tp)
-{
- return tp->t_ticket->t_tid;
-}
-
/*
* Allocate and initialise a new log ticket.
*/
diff --git a/fs/xfs/xfs_log.h b/fs/xfs/xfs_log.h
index 3bd3291..78c9039 100644
--- a/fs/xfs/xfs_log.h
+++ b/fs/xfs/xfs_log.h
@@ -189,8 +189,6 @@
struct xlog_ticket *xfs_log_ticket_get(struct xlog_ticket *ticket);
void xfs_log_ticket_put(struct xlog_ticket *ticket);
-xlog_tid_t xfs_log_get_trans_ident(struct xfs_trans *tp);
-
void xfs_log_commit_cil(struct xfs_mount *mp, struct xfs_trans *tp,
struct xfs_log_vec *log_vector,
xfs_lsn_t *commit_lsn, int flags);
diff --git a/fs/xfs/xfs_log_cil.c b/fs/xfs/xfs_log_cil.c
index 9ca59be..7d56e88 100644
--- a/fs/xfs/xfs_log_cil.c
+++ b/fs/xfs/xfs_log_cil.c
@@ -361,13 +361,12 @@
int abort)
{
struct xfs_cil_ctx *ctx = args;
- struct xfs_busy_extent *busyp, *n;
xfs_trans_committed_bulk(ctx->cil->xc_log->l_ailp, ctx->lv_chain,
ctx->start_lsn, abort);
- list_for_each_entry_safe(busyp, n, &ctx->busy_extents, list)
- xfs_alloc_busy_clear(ctx->cil->xc_log->l_mp, busyp);
+ xfs_alloc_busy_sort(&ctx->busy_extents);
+ xfs_alloc_busy_clear(ctx->cil->xc_log->l_mp, &ctx->busy_extents);
spin_lock(&ctx->cil->xc_cil_lock);
list_del(&ctx->committing);
diff --git a/fs/xfs/xfs_log_priv.h b/fs/xfs/xfs_log_priv.h
index 5864850..2d3b6a4 100644
--- a/fs/xfs/xfs_log_priv.h
+++ b/fs/xfs/xfs_log_priv.h
@@ -146,6 +146,8 @@
shutdown */
#define XLOG_TAIL_WARN 0x10 /* log tail verify warning issued */
+typedef __uint32_t xlog_tid_t;
+
#ifdef __KERNEL__
/*
* Below are states for covering allocation transactions.
diff --git a/fs/xfs/xfs_log_recover.c b/fs/xfs/xfs_log_recover.c
index 5cc464a..04142ca 100644
--- a/fs/xfs/xfs_log_recover.c
+++ b/fs/xfs/xfs_log_recover.c
@@ -205,6 +205,35 @@
}
/*
+ * Read at an offset into the buffer. Returns with the buffer in it's original
+ * state regardless of the result of the read.
+ */
+STATIC int
+xlog_bread_offset(
+ xlog_t *log,
+ xfs_daddr_t blk_no, /* block to read from */
+ int nbblks, /* blocks to read */
+ xfs_buf_t *bp,
+ xfs_caddr_t offset)
+{
+ xfs_caddr_t orig_offset = XFS_BUF_PTR(bp);
+ int orig_len = bp->b_buffer_length;
+ int error, error2;
+
+ error = XFS_BUF_SET_PTR(bp, offset, BBTOB(nbblks));
+ if (error)
+ return error;
+
+ error = xlog_bread_noalign(log, blk_no, nbblks, bp);
+
+ /* must reset buffer pointer even on error */
+ error2 = XFS_BUF_SET_PTR(bp, orig_offset, orig_len);
+ if (error)
+ return error;
+ return error2;
+}
+
+/*
* Write out the buffer at the given block for the given number of blocks.
* The buffer is kept locked across the write and is returned locked.
* This can only be used for synchronous log writes.
@@ -1229,20 +1258,12 @@
*/
ealign = round_down(end_block, sectbb);
if (j == 0 && (start_block + endcount > ealign)) {
- offset = XFS_BUF_PTR(bp);
- balign = BBTOB(ealign - start_block);
- error = XFS_BUF_SET_PTR(bp, offset + balign,
- BBTOB(sectbb));
+ offset = XFS_BUF_PTR(bp) + BBTOB(ealign - start_block);
+ error = xlog_bread_offset(log, ealign, sectbb,
+ bp, offset);
if (error)
break;
- error = xlog_bread_noalign(log, ealign, sectbb, bp);
- if (error)
- break;
-
- error = XFS_BUF_SET_PTR(bp, offset, bufblks);
- if (error)
- break;
}
offset = xlog_align(log, start_block, endcount, bp);
@@ -3448,19 +3469,9 @@
* - order is important.
*/
wrapped_hblks = hblks - split_hblks;
- error = XFS_BUF_SET_PTR(hbp,
- offset + BBTOB(split_hblks),
- BBTOB(hblks - split_hblks));
- if (error)
- goto bread_err2;
-
- error = xlog_bread_noalign(log, 0,
- wrapped_hblks, hbp);
- if (error)
- goto bread_err2;
-
- error = XFS_BUF_SET_PTR(hbp, offset,
- BBTOB(hblks));
+ error = xlog_bread_offset(log, 0,
+ wrapped_hblks, hbp,
+ offset + BBTOB(split_hblks));
if (error)
goto bread_err2;
}
@@ -3511,19 +3522,9 @@
* _first_, then the log start (LR header end)
* - order is important.
*/
- error = XFS_BUF_SET_PTR(dbp,
- offset + BBTOB(split_bblks),
- BBTOB(bblks - split_bblks));
- if (error)
- goto bread_err2;
-
- error = xlog_bread_noalign(log, wrapped_hblks,
- bblks - split_bblks,
- dbp);
- if (error)
- goto bread_err2;
-
- error = XFS_BUF_SET_PTR(dbp, offset, h_size);
+ error = xlog_bread_offset(log, 0,
+ bblks - split_bblks, hbp,
+ offset + BBTOB(split_bblks));
if (error)
goto bread_err2;
}
diff --git a/fs/xfs/xfs_mount.c b/fs/xfs/xfs_mount.c
index bb3f9a7..b49b823 100644
--- a/fs/xfs/xfs_mount.c
+++ b/fs/xfs/xfs_mount.c
@@ -1900,7 +1900,7 @@
uint nmsb,
int rsvd)
{
- xfs_mod_sb_t *msbp = &msb[0];
+ xfs_mod_sb_t *msbp;
int error = 0;
/*
@@ -1910,7 +1910,7 @@
* changes will be atomic.
*/
spin_lock(&mp->m_sb_lock);
- for (msbp = &msbp[0]; msbp < (msb + nmsb); msbp++) {
+ for (msbp = msb; msbp < (msb + nmsb); msbp++) {
ASSERT(msbp->msb_field < XFS_SBS_ICOUNT ||
msbp->msb_field > XFS_SBS_FDBLOCKS);
diff --git a/fs/xfs/xfs_trans.c b/fs/xfs/xfs_trans.c
index 7692279..d1f2485 100644
--- a/fs/xfs/xfs_trans.c
+++ b/fs/xfs/xfs_trans.c
@@ -608,10 +608,8 @@
xfs_trans_free(
struct xfs_trans *tp)
{
- struct xfs_busy_extent *busyp, *n;
-
- list_for_each_entry_safe(busyp, n, &tp->t_busy, list)
- xfs_alloc_busy_clear(tp->t_mountp, busyp);
+ xfs_alloc_busy_sort(&tp->t_busy);
+ xfs_alloc_busy_clear(tp->t_mountp, &tp->t_busy);
atomic_dec(&tp->t_mountp->m_active_trans);
xfs_trans_free_dqinfo(tp);
diff --git a/fs/xfs/xfs_types.h b/fs/xfs/xfs_types.h
index 26d1867..65584b5 100644
--- a/fs/xfs/xfs_types.h
+++ b/fs/xfs/xfs_types.h
@@ -73,8 +73,6 @@
typedef __uint32_t xfs_dablk_t; /* dir/attr block number (in file) */
typedef __uint32_t xfs_dahash_t; /* dir/attr hash value */
-typedef __uint32_t xlog_tid_t; /* transaction ID type */
-
/*
* These types are 64 bits on disk but are either 32 or 64 bits in memory.
* Disk based types:
diff --git a/include/asm-generic/audit_change_attr.h b/include/asm-generic/audit_change_attr.h
index bcbab3e..89b73e5 100644
--- a/include/asm-generic/audit_change_attr.h
+++ b/include/asm-generic/audit_change_attr.h
@@ -1,4 +1,6 @@
+#ifdef __NR_chmod
__NR_chmod,
+#endif
__NR_fchmod,
#ifdef __NR_chown
__NR_chown,
@@ -20,7 +22,9 @@
__NR_fchown32,
__NR_lchown32,
#endif
+#ifdef __NR_link
__NR_link,
+#endif
#ifdef __NR_linkat
__NR_linkat,
#endif
diff --git a/include/asm-generic/audit_dir_write.h b/include/asm-generic/audit_dir_write.h
index 6621bd8..7b61db4 100644
--- a/include/asm-generic/audit_dir_write.h
+++ b/include/asm-generic/audit_dir_write.h
@@ -1,13 +1,27 @@
+#ifdef __NR_rename
__NR_rename,
+#endif
+#ifdef __NR_mkdir
__NR_mkdir,
+#endif
+#ifdef __NR_rmdir
__NR_rmdir,
+#endif
#ifdef __NR_creat
__NR_creat,
#endif
+#ifdef __NR_link
__NR_link,
+#endif
+#ifdef __NR_unlink
__NR_unlink,
+#endif
+#ifdef __NR_symlink
__NR_symlink,
+#endif
+#ifdef __NR_mknod
__NR_mknod,
+#endif
#ifdef __NR_mkdirat
__NR_mkdirat,
__NR_mknodat,
diff --git a/include/asm-generic/audit_read.h b/include/asm-generic/audit_read.h
index 0e87464..3b249cb 100644
--- a/include/asm-generic/audit_read.h
+++ b/include/asm-generic/audit_read.h
@@ -1,4 +1,6 @@
+#ifdef __NR_readlink
__NR_readlink,
+#endif
__NR_quotactl,
__NR_listxattr,
__NR_llistxattr,
@@ -6,3 +8,6 @@
__NR_getxattr,
__NR_lgetxattr,
__NR_fgetxattr,
+#ifdef __NR_readlinkat
+__NR_readlinkat,
+#endif
diff --git a/include/asm-generic/audit_write.h b/include/asm-generic/audit_write.h
index c5f1c2c..e7020c5 100644
--- a/include/asm-generic/audit_write.h
+++ b/include/asm-generic/audit_write.h
@@ -4,7 +4,9 @@
__NR_swapon,
#endif
__NR_quotactl,
+#ifdef __NR_truncate
__NR_truncate,
+#endif
#ifdef __NR_truncate64
__NR_truncate64,
#endif
diff --git a/include/asm-generic/cacheflush.h b/include/asm-generic/cacheflush.h
index 57b5c3c..87bc536 100644
--- a/include/asm-generic/cacheflush.h
+++ b/include/asm-generic/cacheflush.h
@@ -24,7 +24,10 @@
#define flush_cache_vunmap(start, end) do { } while (0)
#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
- memcpy(dst, src, len)
+ do { \
+ memcpy(dst, src, len); \
+ flush_icache_user_range(vma, page, vaddr, len); \
+ } while (0)
#define copy_from_user_page(vma, page, vaddr, dst, src, len) \
memcpy(dst, src, len)
diff --git a/include/asm-generic/pgtable.h b/include/asm-generic/pgtable.h
index b4bfe33..e9b8e59 100644
--- a/include/asm-generic/pgtable.h
+++ b/include/asm-generic/pgtable.h
@@ -184,22 +184,18 @@
#endif /* CONFIG_TRANSPARENT_HUGEPAGE */
#endif
-#ifndef __HAVE_ARCH_PAGE_TEST_DIRTY
-#define page_test_dirty(page) (0)
+#ifndef __HAVE_ARCH_PAGE_TEST_AND_CLEAR_DIRTY
+#define page_test_and_clear_dirty(pfn, mapped) (0)
#endif
-#ifndef __HAVE_ARCH_PAGE_CLEAR_DIRTY
-#define page_clear_dirty(page, mapped) do { } while (0)
-#endif
-
-#ifndef __HAVE_ARCH_PAGE_TEST_DIRTY
+#ifndef __HAVE_ARCH_PAGE_TEST_AND_CLEAR_DIRTY
#define pte_maybe_dirty(pte) pte_dirty(pte)
#else
#define pte_maybe_dirty(pte) (1)
#endif
#ifndef __HAVE_ARCH_PAGE_TEST_AND_CLEAR_YOUNG
-#define page_test_and_clear_young(page) (0)
+#define page_test_and_clear_young(pfn) (0)
#endif
#ifndef __HAVE_ARCH_PGD_OFFSET_GATE
diff --git a/include/asm-generic/resource.h b/include/asm-generic/resource.h
index 587566f..61fa862 100644
--- a/include/asm-generic/resource.h
+++ b/include/asm-generic/resource.h
@@ -78,7 +78,7 @@
[RLIMIT_CORE] = { 0, RLIM_INFINITY }, \
[RLIMIT_RSS] = { RLIM_INFINITY, RLIM_INFINITY }, \
[RLIMIT_NPROC] = { 0, 0 }, \
- [RLIMIT_NOFILE] = { INR_OPEN, INR_OPEN }, \
+ [RLIMIT_NOFILE] = { INR_OPEN_CUR, INR_OPEN_MAX }, \
[RLIMIT_MEMLOCK] = { MLOCK_LIMIT, MLOCK_LIMIT }, \
[RLIMIT_AS] = { RLIM_INFINITY, RLIM_INFINITY }, \
[RLIMIT_LOCKS] = { RLIM_INFINITY, RLIM_INFINITY }, \
diff --git a/include/asm-generic/tlb.h b/include/asm-generic/tlb.h
index e43f976..e58fa77 100644
--- a/include/asm-generic/tlb.h
+++ b/include/asm-generic/tlb.h
@@ -5,6 +5,8 @@
* Copyright 2001 Red Hat, Inc.
* Based on code from mm/memory.c Copyright Linus Torvalds and others.
*
+ * Copyright 2011 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
+ *
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
@@ -17,97 +19,111 @@
#include <asm/pgalloc.h>
#include <asm/tlbflush.h>
+#ifdef CONFIG_HAVE_RCU_TABLE_FREE
/*
- * For UP we don't need to worry about TLB flush
- * and page free order so much..
+ * Semi RCU freeing of the page directories.
+ *
+ * This is needed by some architectures to implement software pagetable walkers.
+ *
+ * gup_fast() and other software pagetable walkers do a lockless page-table
+ * walk and therefore needs some synchronization with the freeing of the page
+ * directories. The chosen means to accomplish that is by disabling IRQs over
+ * the walk.
+ *
+ * Architectures that use IPIs to flush TLBs will then automagically DTRT,
+ * since we unlink the page, flush TLBs, free the page. Since the disabling of
+ * IRQs delays the completion of the TLB flush we can never observe an already
+ * freed page.
+ *
+ * Architectures that do not have this (PPC) need to delay the freeing by some
+ * other means, this is that means.
+ *
+ * What we do is batch the freed directory pages (tables) and RCU free them.
+ * We use the sched RCU variant, as that guarantees that IRQ/preempt disabling
+ * holds off grace periods.
+ *
+ * However, in order to batch these pages we need to allocate storage, this
+ * allocation is deep inside the MM code and can thus easily fail on memory
+ * pressure. To guarantee progress we fall back to single table freeing, see
+ * the implementation of tlb_remove_table_one().
+ *
*/
-#ifdef CONFIG_SMP
- #ifdef ARCH_FREE_PTR_NR
- #define FREE_PTR_NR ARCH_FREE_PTR_NR
- #else
- #define FREE_PTE_NR 506
- #endif
- #define tlb_fast_mode(tlb) ((tlb)->nr == ~0U)
-#else
- #define FREE_PTE_NR 1
- #define tlb_fast_mode(tlb) 1
+struct mmu_table_batch {
+ struct rcu_head rcu;
+ unsigned int nr;
+ void *tables[0];
+};
+
+#define MAX_TABLE_BATCH \
+ ((PAGE_SIZE - sizeof(struct mmu_table_batch)) / sizeof(void *))
+
+extern void tlb_table_flush(struct mmu_gather *tlb);
+extern void tlb_remove_table(struct mmu_gather *tlb, void *table);
+
#endif
+/*
+ * If we can't allocate a page to make a big batch of page pointers
+ * to work on, then just handle a few from the on-stack structure.
+ */
+#define MMU_GATHER_BUNDLE 8
+
+struct mmu_gather_batch {
+ struct mmu_gather_batch *next;
+ unsigned int nr;
+ unsigned int max;
+ struct page *pages[0];
+};
+
+#define MAX_GATHER_BATCH \
+ ((PAGE_SIZE - sizeof(struct mmu_gather_batch)) / sizeof(void *))
+
/* struct mmu_gather is an opaque type used by the mm code for passing around
* any data needed by arch specific code for tlb_remove_page.
*/
struct mmu_gather {
struct mm_struct *mm;
- unsigned int nr; /* set to ~0U means fast mode */
- unsigned int need_flush;/* Really unmapped some ptes? */
- unsigned int fullmm; /* non-zero means full mm flush */
- struct page * pages[FREE_PTE_NR];
+#ifdef CONFIG_HAVE_RCU_TABLE_FREE
+ struct mmu_table_batch *batch;
+#endif
+ unsigned int need_flush : 1, /* Did free PTEs */
+ fast_mode : 1; /* No batching */
+
+ unsigned int fullmm;
+
+ struct mmu_gather_batch *active;
+ struct mmu_gather_batch local;
+ struct page *__pages[MMU_GATHER_BUNDLE];
};
-/* Users of the generic TLB shootdown code must declare this storage space. */
-DECLARE_PER_CPU(struct mmu_gather, mmu_gathers);
+#define HAVE_GENERIC_MMU_GATHER
-/* tlb_gather_mmu
- * Return a pointer to an initialized struct mmu_gather.
- */
-static inline struct mmu_gather *
-tlb_gather_mmu(struct mm_struct *mm, unsigned int full_mm_flush)
+static inline int tlb_fast_mode(struct mmu_gather *tlb)
{
- struct mmu_gather *tlb = &get_cpu_var(mmu_gathers);
-
- tlb->mm = mm;
-
- /* Use fast mode if only one CPU is online */
- tlb->nr = num_online_cpus() > 1 ? 0U : ~0U;
-
- tlb->fullmm = full_mm_flush;
-
- return tlb;
+#ifdef CONFIG_SMP
+ return tlb->fast_mode;
+#else
+ /*
+ * For UP we don't need to worry about TLB flush
+ * and page free order so much..
+ */
+ return 1;
+#endif
}
-static inline void
-tlb_flush_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end)
-{
- if (!tlb->need_flush)
- return;
- tlb->need_flush = 0;
- tlb_flush(tlb);
- if (!tlb_fast_mode(tlb)) {
- free_pages_and_swap_cache(tlb->pages, tlb->nr);
- tlb->nr = 0;
- }
-}
-
-/* tlb_finish_mmu
- * Called at the end of the shootdown operation to free up any resources
- * that were required.
- */
-static inline void
-tlb_finish_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end)
-{
- tlb_flush_mmu(tlb, start, end);
-
- /* keep the page table cache within bounds */
- check_pgt_cache();
-
- put_cpu_var(mmu_gathers);
-}
+void tlb_gather_mmu(struct mmu_gather *tlb, struct mm_struct *mm, bool fullmm);
+void tlb_flush_mmu(struct mmu_gather *tlb);
+void tlb_finish_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end);
+int __tlb_remove_page(struct mmu_gather *tlb, struct page *page);
/* tlb_remove_page
- * Must perform the equivalent to __free_pte(pte_get_and_clear(ptep)), while
- * handling the additional races in SMP caused by other CPUs caching valid
- * mappings in their TLBs.
+ * Similar to __tlb_remove_page but will call tlb_flush_mmu() itself when
+ * required.
*/
static inline void tlb_remove_page(struct mmu_gather *tlb, struct page *page)
{
- tlb->need_flush = 1;
- if (tlb_fast_mode(tlb)) {
- free_page_and_swap_cache(page);
- return;
- }
- tlb->pages[tlb->nr++] = page;
- if (tlb->nr >= FREE_PTE_NR)
- tlb_flush_mmu(tlb, 0, 0);
+ if (!__tlb_remove_page(tlb, page))
+ tlb_flush_mmu(tlb);
}
/**
diff --git a/include/asm-generic/unistd.h b/include/asm-generic/unistd.h
index 07c40d5..33d52470 100644
--- a/include/asm-generic/unistd.h
+++ b/include/asm-generic/unistd.h
@@ -24,16 +24,24 @@
#define __SC_3264(_nr, _32, _64) __SYSCALL(_nr, _64)
#endif
+#ifdef __SYSCALL_COMPAT
+#define __SC_COMP(_nr, _sys, _comp) __SYSCALL(_nr, _comp)
+#define __SC_COMP_3264(_nr, _32, _64, _comp) __SYSCALL(_nr, _comp)
+#else
+#define __SC_COMP(_nr, _sys, _comp) __SYSCALL(_nr, _sys)
+#define __SC_COMP_3264(_nr, _32, _64, _comp) __SC_3264(_nr, _32, _64)
+#endif
+
#define __NR_io_setup 0
-__SYSCALL(__NR_io_setup, sys_io_setup)
+__SC_COMP(__NR_io_setup, sys_io_setup, compat_sys_io_setup)
#define __NR_io_destroy 1
__SYSCALL(__NR_io_destroy, sys_io_destroy)
#define __NR_io_submit 2
-__SYSCALL(__NR_io_submit, sys_io_submit)
+__SC_COMP(__NR_io_submit, sys_io_submit, compat_sys_io_submit)
#define __NR_io_cancel 3
__SYSCALL(__NR_io_cancel, sys_io_cancel)
#define __NR_io_getevents 4
-__SYSCALL(__NR_io_getevents, sys_io_getevents)
+__SC_COMP(__NR_io_getevents, sys_io_getevents, compat_sys_io_getevents)
/* fs/xattr.c */
#define __NR_setxattr 5
@@ -67,7 +75,7 @@
/* fs/cookies.c */
#define __NR_lookup_dcookie 18
-__SYSCALL(__NR_lookup_dcookie, sys_lookup_dcookie)
+__SC_COMP(__NR_lookup_dcookie, sys_lookup_dcookie, compat_sys_lookup_dcookie)
/* fs/eventfd.c */
#define __NR_eventfd2 19
@@ -79,7 +87,7 @@
#define __NR_epoll_ctl 21
__SYSCALL(__NR_epoll_ctl, sys_epoll_ctl)
#define __NR_epoll_pwait 22
-__SYSCALL(__NR_epoll_pwait, sys_epoll_pwait)
+__SC_COMP(__NR_epoll_pwait, sys_epoll_pwait, compat_sys_epoll_pwait)
/* fs/fcntl.c */
#define __NR_dup 23
@@ -87,7 +95,7 @@
#define __NR_dup3 24
__SYSCALL(__NR_dup3, sys_dup3)
#define __NR3264_fcntl 25
-__SC_3264(__NR3264_fcntl, sys_fcntl64, sys_fcntl)
+__SC_COMP_3264(__NR3264_fcntl, sys_fcntl64, sys_fcntl, compat_sys_fcntl64)
/* fs/inotify_user.c */
#define __NR_inotify_init1 26
@@ -99,7 +107,7 @@
/* fs/ioctl.c */
#define __NR_ioctl 29
-__SYSCALL(__NR_ioctl, sys_ioctl)
+__SC_COMP(__NR_ioctl, sys_ioctl, compat_sys_ioctl)
/* fs/ioprio.c */
#define __NR_ioprio_set 30
@@ -129,26 +137,30 @@
#define __NR_umount2 39
__SYSCALL(__NR_umount2, sys_umount)
#define __NR_mount 40
-__SYSCALL(__NR_mount, sys_mount)
+__SC_COMP(__NR_mount, sys_mount, compat_sys_mount)
#define __NR_pivot_root 41
__SYSCALL(__NR_pivot_root, sys_pivot_root)
/* fs/nfsctl.c */
#define __NR_nfsservctl 42
-__SYSCALL(__NR_nfsservctl, sys_nfsservctl)
+__SC_COMP(__NR_nfsservctl, sys_nfsservctl, compat_sys_nfsservctl)
/* fs/open.c */
#define __NR3264_statfs 43
-__SC_3264(__NR3264_statfs, sys_statfs64, sys_statfs)
+__SC_COMP_3264(__NR3264_statfs, sys_statfs64, sys_statfs, \
+ compat_sys_statfs64)
#define __NR3264_fstatfs 44
-__SC_3264(__NR3264_fstatfs, sys_fstatfs64, sys_fstatfs)
+__SC_COMP_3264(__NR3264_fstatfs, sys_fstatfs64, sys_fstatfs, \
+ compat_sys_fstatfs64)
#define __NR3264_truncate 45
-__SC_3264(__NR3264_truncate, sys_truncate64, sys_truncate)
+__SC_COMP_3264(__NR3264_truncate, sys_truncate64, sys_truncate, \
+ compat_sys_truncate64)
#define __NR3264_ftruncate 46
-__SC_3264(__NR3264_ftruncate, sys_ftruncate64, sys_ftruncate)
+__SC_COMP_3264(__NR3264_ftruncate, sys_ftruncate64, sys_ftruncate, \
+ compat_sys_ftruncate64)
#define __NR_fallocate 47
-__SYSCALL(__NR_fallocate, sys_fallocate)
+__SC_COMP(__NR_fallocate, sys_fallocate, compat_sys_fallocate)
#define __NR_faccessat 48
__SYSCALL(__NR_faccessat, sys_faccessat)
#define __NR_chdir 49
@@ -166,7 +178,7 @@
#define __NR_fchown 55
__SYSCALL(__NR_fchown, sys_fchown)
#define __NR_openat 56
-__SYSCALL(__NR_openat, sys_openat)
+__SC_COMP(__NR_openat, sys_openat, compat_sys_openat)
#define __NR_close 57
__SYSCALL(__NR_close, sys_close)
#define __NR_vhangup 58
@@ -182,7 +194,7 @@
/* fs/readdir.c */
#define __NR_getdents64 61
-__SYSCALL(__NR_getdents64, sys_getdents64)
+__SC_COMP(__NR_getdents64, sys_getdents64, compat_sys_getdents64)
/* fs/read_write.c */
#define __NR3264_lseek 62
@@ -192,17 +204,17 @@
#define __NR_write 64
__SYSCALL(__NR_write, sys_write)
#define __NR_readv 65
-__SYSCALL(__NR_readv, sys_readv)
+__SC_COMP(__NR_readv, sys_readv, compat_sys_readv)
#define __NR_writev 66
-__SYSCALL(__NR_writev, sys_writev)
+__SC_COMP(__NR_writev, sys_writev, compat_sys_writev)
#define __NR_pread64 67
-__SYSCALL(__NR_pread64, sys_pread64)
+__SC_COMP(__NR_pread64, sys_pread64, compat_sys_pread64)
#define __NR_pwrite64 68
-__SYSCALL(__NR_pwrite64, sys_pwrite64)
+__SC_COMP(__NR_pwrite64, sys_pwrite64, compat_sys_pwrite64)
#define __NR_preadv 69
-__SYSCALL(__NR_preadv, sys_preadv)
+__SC_COMP(__NR_preadv, sys_preadv, compat_sys_preadv)
#define __NR_pwritev 70
-__SYSCALL(__NR_pwritev, sys_pwritev)
+__SC_COMP(__NR_pwritev, sys_pwritev, compat_sys_pwritev)
/* fs/sendfile.c */
#define __NR3264_sendfile 71
@@ -210,17 +222,17 @@
/* fs/select.c */
#define __NR_pselect6 72
-__SYSCALL(__NR_pselect6, sys_pselect6)
+__SC_COMP(__NR_pselect6, sys_pselect6, compat_sys_pselect6)
#define __NR_ppoll 73
-__SYSCALL(__NR_ppoll, sys_ppoll)
+__SC_COMP(__NR_ppoll, sys_ppoll, compat_sys_ppoll)
/* fs/signalfd.c */
#define __NR_signalfd4 74
-__SYSCALL(__NR_signalfd4, sys_signalfd4)
+__SC_COMP(__NR_signalfd4, sys_signalfd4, compat_sys_signalfd4)
/* fs/splice.c */
#define __NR_vmsplice 75
-__SYSCALL(__NR_vmsplice, sys_vmsplice)
+__SC_COMP(__NR_vmsplice, sys_vmsplice, compat_sys_vmsplice)
#define __NR_splice 76
__SYSCALL(__NR_splice, sys_splice)
#define __NR_tee 77
@@ -243,23 +255,27 @@
__SYSCALL(__NR_fdatasync, sys_fdatasync)
#ifdef __ARCH_WANT_SYNC_FILE_RANGE2
#define __NR_sync_file_range2 84
-__SYSCALL(__NR_sync_file_range2, sys_sync_file_range2)
+__SC_COMP(__NR_sync_file_range2, sys_sync_file_range2, \
+ compat_sys_sync_file_range2)
#else
#define __NR_sync_file_range 84
-__SYSCALL(__NR_sync_file_range, sys_sync_file_range)
+__SC_COMP(__NR_sync_file_range, sys_sync_file_range, \
+ compat_sys_sync_file_range)
#endif
/* fs/timerfd.c */
#define __NR_timerfd_create 85
__SYSCALL(__NR_timerfd_create, sys_timerfd_create)
#define __NR_timerfd_settime 86
-__SYSCALL(__NR_timerfd_settime, sys_timerfd_settime)
+__SC_COMP(__NR_timerfd_settime, sys_timerfd_settime, \
+ compat_sys_timerfd_settime)
#define __NR_timerfd_gettime 87
-__SYSCALL(__NR_timerfd_gettime, sys_timerfd_gettime)
+__SC_COMP(__NR_timerfd_gettime, sys_timerfd_gettime, \
+ compat_sys_timerfd_gettime)
/* fs/utimes.c */
#define __NR_utimensat 88
-__SYSCALL(__NR_utimensat, sys_utimensat)
+__SC_COMP(__NR_utimensat, sys_utimensat, compat_sys_utimensat)
/* kernel/acct.c */
#define __NR_acct 89
@@ -281,7 +297,7 @@
#define __NR_exit_group 94
__SYSCALL(__NR_exit_group, sys_exit_group)
#define __NR_waitid 95
-__SYSCALL(__NR_waitid, sys_waitid)
+__SC_COMP(__NR_waitid, sys_waitid, compat_sys_waitid)
/* kernel/fork.c */
#define __NR_set_tid_address 96
@@ -291,25 +307,27 @@
/* kernel/futex.c */
#define __NR_futex 98
-__SYSCALL(__NR_futex, sys_futex)
+__SC_COMP(__NR_futex, sys_futex, compat_sys_futex)
#define __NR_set_robust_list 99
-__SYSCALL(__NR_set_robust_list, sys_set_robust_list)
+__SC_COMP(__NR_set_robust_list, sys_set_robust_list, \
+ compat_sys_set_robust_list)
#define __NR_get_robust_list 100
-__SYSCALL(__NR_get_robust_list, sys_get_robust_list)
+__SC_COMP(__NR_get_robust_list, sys_get_robust_list, \
+ compat_sys_get_robust_list)
/* kernel/hrtimer.c */
#define __NR_nanosleep 101
-__SYSCALL(__NR_nanosleep, sys_nanosleep)
+__SC_COMP(__NR_nanosleep, sys_nanosleep, compat_sys_nanosleep)
/* kernel/itimer.c */
#define __NR_getitimer 102
-__SYSCALL(__NR_getitimer, sys_getitimer)
+__SC_COMP(__NR_getitimer, sys_getitimer, compat_sys_getitimer)
#define __NR_setitimer 103
-__SYSCALL(__NR_setitimer, sys_setitimer)
+__SC_COMP(__NR_setitimer, sys_setitimer, compat_sys_setitimer)
/* kernel/kexec.c */
#define __NR_kexec_load 104
-__SYSCALL(__NR_kexec_load, sys_kexec_load)
+__SC_COMP(__NR_kexec_load, sys_kexec_load, compat_sys_kexec_load)
/* kernel/module.c */
#define __NR_init_module 105
@@ -319,23 +337,24 @@
/* kernel/posix-timers.c */
#define __NR_timer_create 107
-__SYSCALL(__NR_timer_create, sys_timer_create)
+__SC_COMP(__NR_timer_create, sys_timer_create, compat_sys_timer_create)
#define __NR_timer_gettime 108
-__SYSCALL(__NR_timer_gettime, sys_timer_gettime)
+__SC_COMP(__NR_timer_gettime, sys_timer_gettime, compat_sys_timer_gettime)
#define __NR_timer_getoverrun 109
__SYSCALL(__NR_timer_getoverrun, sys_timer_getoverrun)
#define __NR_timer_settime 110
-__SYSCALL(__NR_timer_settime, sys_timer_settime)
+__SC_COMP(__NR_timer_settime, sys_timer_settime, compat_sys_timer_settime)
#define __NR_timer_delete 111
__SYSCALL(__NR_timer_delete, sys_timer_delete)
#define __NR_clock_settime 112
-__SYSCALL(__NR_clock_settime, sys_clock_settime)
+__SC_COMP(__NR_clock_settime, sys_clock_settime, compat_sys_clock_settime)
#define __NR_clock_gettime 113
-__SYSCALL(__NR_clock_gettime, sys_clock_gettime)
+__SC_COMP(__NR_clock_gettime, sys_clock_gettime, compat_sys_clock_gettime)
#define __NR_clock_getres 114
-__SYSCALL(__NR_clock_getres, sys_clock_getres)
+__SC_COMP(__NR_clock_getres, sys_clock_getres, compat_sys_clock_getres)
#define __NR_clock_nanosleep 115
-__SYSCALL(__NR_clock_nanosleep, sys_clock_nanosleep)
+__SC_COMP(__NR_clock_nanosleep, sys_clock_nanosleep, \
+ compat_sys_clock_nanosleep)
/* kernel/printk.c */
#define __NR_syslog 116
@@ -355,9 +374,11 @@
#define __NR_sched_getparam 121
__SYSCALL(__NR_sched_getparam, sys_sched_getparam)
#define __NR_sched_setaffinity 122
-__SYSCALL(__NR_sched_setaffinity, sys_sched_setaffinity)
+__SC_COMP(__NR_sched_setaffinity, sys_sched_setaffinity, \
+ compat_sys_sched_setaffinity)
#define __NR_sched_getaffinity 123
-__SYSCALL(__NR_sched_getaffinity, sys_sched_getaffinity)
+__SC_COMP(__NR_sched_getaffinity, sys_sched_getaffinity, \
+ compat_sys_sched_getaffinity)
#define __NR_sched_yield 124
__SYSCALL(__NR_sched_yield, sys_sched_yield)
#define __NR_sched_get_priority_max 125
@@ -365,7 +386,8 @@
#define __NR_sched_get_priority_min 126
__SYSCALL(__NR_sched_get_priority_min, sys_sched_get_priority_min)
#define __NR_sched_rr_get_interval 127
-__SYSCALL(__NR_sched_rr_get_interval, sys_sched_rr_get_interval)
+__SC_COMP(__NR_sched_rr_get_interval, sys_sched_rr_get_interval, \
+ compat_sys_sched_rr_get_interval)
/* kernel/signal.c */
#define __NR_restart_syscall 128
@@ -377,21 +399,23 @@
#define __NR_tgkill 131
__SYSCALL(__NR_tgkill, sys_tgkill)
#define __NR_sigaltstack 132
-__SYSCALL(__NR_sigaltstack, sys_sigaltstack)
+__SC_COMP(__NR_sigaltstack, sys_sigaltstack, compat_sys_sigaltstack)
#define __NR_rt_sigsuspend 133
-__SYSCALL(__NR_rt_sigsuspend, sys_rt_sigsuspend) /* __ARCH_WANT_SYS_RT_SIGSUSPEND */
+__SC_COMP(__NR_rt_sigsuspend, sys_rt_sigsuspend, compat_sys_rt_sigsuspend)
#define __NR_rt_sigaction 134
-__SYSCALL(__NR_rt_sigaction, sys_rt_sigaction) /* __ARCH_WANT_SYS_RT_SIGACTION */
+__SC_COMP(__NR_rt_sigaction, sys_rt_sigaction, compat_sys_rt_sigaction)
#define __NR_rt_sigprocmask 135
__SYSCALL(__NR_rt_sigprocmask, sys_rt_sigprocmask)
#define __NR_rt_sigpending 136
__SYSCALL(__NR_rt_sigpending, sys_rt_sigpending)
#define __NR_rt_sigtimedwait 137
-__SYSCALL(__NR_rt_sigtimedwait, sys_rt_sigtimedwait)
+__SC_COMP(__NR_rt_sigtimedwait, sys_rt_sigtimedwait, \
+ compat_sys_rt_sigtimedwait)
#define __NR_rt_sigqueueinfo 138
-__SYSCALL(__NR_rt_sigqueueinfo, sys_rt_sigqueueinfo)
+__SC_COMP(__NR_rt_sigqueueinfo, sys_rt_sigqueueinfo, \
+ compat_sys_rt_sigqueueinfo)
#define __NR_rt_sigreturn 139
-__SYSCALL(__NR_rt_sigreturn, sys_rt_sigreturn) /* sys_rt_sigreturn_wrapper, */
+__SC_COMP(__NR_rt_sigreturn, sys_rt_sigreturn, compat_sys_rt_sigreturn)
/* kernel/sys.c */
#define __NR_setpriority 140
@@ -421,7 +445,7 @@
#define __NR_setfsgid 152
__SYSCALL(__NR_setfsgid, sys_setfsgid)
#define __NR_times 153
-__SYSCALL(__NR_times, sys_times)
+__SC_COMP(__NR_times, sys_times, compat_sys_times)
#define __NR_setpgid 154
__SYSCALL(__NR_setpgid, sys_setpgid)
#define __NR_getpgid 155
@@ -441,11 +465,11 @@
#define __NR_setdomainname 162
__SYSCALL(__NR_setdomainname, sys_setdomainname)
#define __NR_getrlimit 163
-__SYSCALL(__NR_getrlimit, sys_getrlimit)
+__SC_COMP(__NR_getrlimit, sys_getrlimit, compat_sys_getrlimit)
#define __NR_setrlimit 164
-__SYSCALL(__NR_setrlimit, sys_setrlimit)
+__SC_COMP(__NR_setrlimit, sys_setrlimit, compat_sys_setrlimit)
#define __NR_getrusage 165
-__SYSCALL(__NR_getrusage, sys_getrusage)
+__SC_COMP(__NR_getrusage, sys_getrusage, compat_sys_getrusage)
#define __NR_umask 166
__SYSCALL(__NR_umask, sys_umask)
#define __NR_prctl 167
@@ -455,11 +479,11 @@
/* kernel/time.c */
#define __NR_gettimeofday 169
-__SYSCALL(__NR_gettimeofday, sys_gettimeofday)
+__SC_COMP(__NR_gettimeofday, sys_gettimeofday, compat_sys_gettimeofday)
#define __NR_settimeofday 170
-__SYSCALL(__NR_settimeofday, sys_settimeofday)
+__SC_COMP(__NR_settimeofday, sys_settimeofday, compat_sys_settimeofday)
#define __NR_adjtimex 171
-__SYSCALL(__NR_adjtimex, sys_adjtimex)
+__SC_COMP(__NR_adjtimex, sys_adjtimex, compat_sys_adjtimex)
/* kernel/timer.c */
#define __NR_getpid 172
@@ -477,39 +501,40 @@
#define __NR_gettid 178
__SYSCALL(__NR_gettid, sys_gettid)
#define __NR_sysinfo 179
-__SYSCALL(__NR_sysinfo, sys_sysinfo)
+__SC_COMP(__NR_sysinfo, sys_sysinfo, compat_sys_sysinfo)
/* ipc/mqueue.c */
#define __NR_mq_open 180
-__SYSCALL(__NR_mq_open, sys_mq_open)
+__SC_COMP(__NR_mq_open, sys_mq_open, compat_sys_mq_open)
#define __NR_mq_unlink 181
__SYSCALL(__NR_mq_unlink, sys_mq_unlink)
#define __NR_mq_timedsend 182
-__SYSCALL(__NR_mq_timedsend, sys_mq_timedsend)
+__SC_COMP(__NR_mq_timedsend, sys_mq_timedsend, compat_sys_mq_timedsend)
#define __NR_mq_timedreceive 183
-__SYSCALL(__NR_mq_timedreceive, sys_mq_timedreceive)
+__SC_COMP(__NR_mq_timedreceive, sys_mq_timedreceive, \
+ compat_sys_mq_timedreceive)
#define __NR_mq_notify 184
-__SYSCALL(__NR_mq_notify, sys_mq_notify)
+__SC_COMP(__NR_mq_notify, sys_mq_notify, compat_sys_mq_notify)
#define __NR_mq_getsetattr 185
-__SYSCALL(__NR_mq_getsetattr, sys_mq_getsetattr)
+__SC_COMP(__NR_mq_getsetattr, sys_mq_getsetattr, compat_sys_mq_getsetattr)
/* ipc/msg.c */
#define __NR_msgget 186
__SYSCALL(__NR_msgget, sys_msgget)
#define __NR_msgctl 187
-__SYSCALL(__NR_msgctl, sys_msgctl)
+__SC_COMP(__NR_msgctl, sys_msgctl, compat_sys_msgctl)
#define __NR_msgrcv 188
-__SYSCALL(__NR_msgrcv, sys_msgrcv)
+__SC_COMP(__NR_msgrcv, sys_msgrcv, compat_sys_msgrcv)
#define __NR_msgsnd 189
-__SYSCALL(__NR_msgsnd, sys_msgsnd)
+__SC_COMP(__NR_msgsnd, sys_msgsnd, compat_sys_msgsnd)
/* ipc/sem.c */
#define __NR_semget 190
__SYSCALL(__NR_semget, sys_semget)
#define __NR_semctl 191
-__SYSCALL(__NR_semctl, sys_semctl)
+__SC_COMP(__NR_semctl, sys_semctl, compat_sys_semctl)
#define __NR_semtimedop 192
-__SYSCALL(__NR_semtimedop, sys_semtimedop)
+__SC_COMP(__NR_semtimedop, sys_semtimedop, compat_sys_semtimedop)
#define __NR_semop 193
__SYSCALL(__NR_semop, sys_semop)
@@ -517,9 +542,9 @@
#define __NR_shmget 194
__SYSCALL(__NR_shmget, sys_shmget)
#define __NR_shmctl 195
-__SYSCALL(__NR_shmctl, sys_shmctl)
+__SC_COMP(__NR_shmctl, sys_shmctl, compat_sys_shmctl)
#define __NR_shmat 196
-__SYSCALL(__NR_shmat, sys_shmat)
+__SC_COMP(__NR_shmat, sys_shmat, compat_sys_shmat)
#define __NR_shmdt 197
__SYSCALL(__NR_shmdt, sys_shmdt)
@@ -543,21 +568,21 @@
#define __NR_sendto 206
__SYSCALL(__NR_sendto, sys_sendto)
#define __NR_recvfrom 207
-__SYSCALL(__NR_recvfrom, sys_recvfrom)
+__SC_COMP(__NR_recvfrom, sys_recvfrom, compat_sys_recvfrom)
#define __NR_setsockopt 208
-__SYSCALL(__NR_setsockopt, sys_setsockopt)
+__SC_COMP(__NR_setsockopt, sys_setsockopt, compat_sys_setsockopt)
#define __NR_getsockopt 209
-__SYSCALL(__NR_getsockopt, sys_getsockopt)
+__SC_COMP(__NR_getsockopt, sys_getsockopt, compat_sys_getsockopt)
#define __NR_shutdown 210
__SYSCALL(__NR_shutdown, sys_shutdown)
#define __NR_sendmsg 211
-__SYSCALL(__NR_sendmsg, sys_sendmsg)
+__SC_COMP(__NR_sendmsg, sys_sendmsg, compat_sys_sendmsg)
#define __NR_recvmsg 212
-__SYSCALL(__NR_recvmsg, sys_recvmsg)
+__SC_COMP(__NR_recvmsg, sys_recvmsg, compat_sys_recvmsg)
/* mm/filemap.c */
#define __NR_readahead 213
-__SYSCALL(__NR_readahead, sys_readahead)
+__SC_COMP(__NR_readahead, sys_readahead, compat_sys_readahead)
/* mm/nommu.c, also with MMU */
#define __NR_brk 214
@@ -573,19 +598,19 @@
#define __NR_request_key 218
__SYSCALL(__NR_request_key, sys_request_key)
#define __NR_keyctl 219
-__SYSCALL(__NR_keyctl, sys_keyctl)
+__SC_COMP(__NR_keyctl, sys_keyctl, compat_sys_keyctl)
/* arch/example/kernel/sys_example.c */
#define __NR_clone 220
-__SYSCALL(__NR_clone, sys_clone) /* .long sys_clone_wrapper */
+__SYSCALL(__NR_clone, sys_clone)
#define __NR_execve 221
-__SYSCALL(__NR_execve, sys_execve) /* .long sys_execve_wrapper */
+__SC_COMP(__NR_execve, sys_execve, compat_sys_execve)
#define __NR3264_mmap 222
__SC_3264(__NR3264_mmap, sys_mmap2, sys_mmap)
/* mm/fadvise.c */
#define __NR3264_fadvise64 223
-__SYSCALL(__NR3264_fadvise64, sys_fadvise64_64)
+__SC_COMP(__NR3264_fadvise64, sys_fadvise64_64, compat_sys_fadvise64_64)
/* mm/, CONFIG_MMU only */
#ifndef __ARCH_NOMMU
@@ -612,25 +637,26 @@
#define __NR_remap_file_pages 234
__SYSCALL(__NR_remap_file_pages, sys_remap_file_pages)
#define __NR_mbind 235
-__SYSCALL(__NR_mbind, sys_mbind)
+__SC_COMP(__NR_mbind, sys_mbind, compat_sys_mbind)
#define __NR_get_mempolicy 236
-__SYSCALL(__NR_get_mempolicy, sys_get_mempolicy)
+__SC_COMP(__NR_get_mempolicy, sys_get_mempolicy, compat_sys_get_mempolicy)
#define __NR_set_mempolicy 237
-__SYSCALL(__NR_set_mempolicy, sys_set_mempolicy)
+__SC_COMP(__NR_set_mempolicy, sys_set_mempolicy, compat_sys_set_mempolicy)
#define __NR_migrate_pages 238
-__SYSCALL(__NR_migrate_pages, sys_migrate_pages)
+__SC_COMP(__NR_migrate_pages, sys_migrate_pages, compat_sys_migrate_pages)
#define __NR_move_pages 239
-__SYSCALL(__NR_move_pages, sys_move_pages)
+__SC_COMP(__NR_move_pages, sys_move_pages, compat_sys_move_pages)
#endif
#define __NR_rt_tgsigqueueinfo 240
-__SYSCALL(__NR_rt_tgsigqueueinfo, sys_rt_tgsigqueueinfo)
+__SC_COMP(__NR_rt_tgsigqueueinfo, sys_rt_tgsigqueueinfo, \
+ compat_sys_rt_tgsigqueueinfo)
#define __NR_perf_event_open 241
__SYSCALL(__NR_perf_event_open, sys_perf_event_open)
#define __NR_accept4 242
__SYSCALL(__NR_accept4, sys_accept4)
#define __NR_recvmmsg 243
-__SYSCALL(__NR_recvmmsg, sys_recvmmsg)
+__SC_COMP(__NR_recvmmsg, sys_recvmmsg, compat_sys_recvmmsg)
/*
* Architectures may provide up to 16 syscalls of their own
@@ -639,19 +665,20 @@
#define __NR_arch_specific_syscall 244
#define __NR_wait4 260
-__SYSCALL(__NR_wait4, sys_wait4)
+__SC_COMP(__NR_wait4, sys_wait4, compat_sys_wait4)
#define __NR_prlimit64 261
__SYSCALL(__NR_prlimit64, sys_prlimit64)
#define __NR_fanotify_init 262
__SYSCALL(__NR_fanotify_init, sys_fanotify_init)
#define __NR_fanotify_mark 263
__SYSCALL(__NR_fanotify_mark, sys_fanotify_mark)
-#define __NR_name_to_handle_at 264
+#define __NR_name_to_handle_at 264
__SYSCALL(__NR_name_to_handle_at, sys_name_to_handle_at)
-#define __NR_open_by_handle_at 265
-__SYSCALL(__NR_open_by_handle_at, sys_open_by_handle_at)
+#define __NR_open_by_handle_at 265
+__SC_COMP(__NR_open_by_handle_at, sys_open_by_handle_at, \
+ compat_sys_open_by_handle_at)
#define __NR_clock_adjtime 266
-__SYSCALL(__NR_clock_adjtime, sys_clock_adjtime)
+__SC_COMP(__NR_clock_adjtime, sys_clock_adjtime, compat_sys_clock_adjtime)
#define __NR_syncfs 267
__SYSCALL(__NR_syncfs, sys_syncfs)
diff --git a/include/asm-generic/vmlinux.lds.h b/include/asm-generic/vmlinux.lds.h
index 077c00d..db22d13 100644
--- a/include/asm-generic/vmlinux.lds.h
+++ b/include/asm-generic/vmlinux.lds.h
@@ -15,7 +15,7 @@
* HEAD_TEXT_SECTION
* INIT_TEXT_SECTION(PAGE_SIZE)
* INIT_DATA_SECTION(...)
- * PERCPU(CACHELINE_SIZE, PAGE_SIZE)
+ * PERCPU_SECTION(CACHELINE_SIZE)
* __init_end = .;
*
* _stext = .;
@@ -682,6 +682,28 @@
}
/**
+ * PERCPU_INPUT - the percpu input sections
+ * @cacheline: cacheline size
+ *
+ * The core percpu section names and core symbols which do not rely
+ * directly upon load addresses.
+ *
+ * @cacheline is used to align subsections to avoid false cacheline
+ * sharing between subsections for different purposes.
+ */
+#define PERCPU_INPUT(cacheline) \
+ VMLINUX_SYMBOL(__per_cpu_start) = .; \
+ *(.data..percpu..first) \
+ . = ALIGN(PAGE_SIZE); \
+ *(.data..percpu..page_aligned) \
+ . = ALIGN(cacheline); \
+ *(.data..percpu..readmostly) \
+ . = ALIGN(cacheline); \
+ *(.data..percpu) \
+ *(.data..percpu..shared_aligned) \
+ VMLINUX_SYMBOL(__per_cpu_end) = .;
+
+/**
* PERCPU_VADDR - define output section for percpu area
* @cacheline: cacheline size
* @vaddr: explicit base address (optional)
@@ -703,52 +725,33 @@
*
* Note that this macros defines __per_cpu_load as an absolute symbol.
* If there is no need to put the percpu section at a predetermined
- * address, use PERCPU().
+ * address, use PERCPU_SECTION.
*/
#define PERCPU_VADDR(cacheline, vaddr, phdr) \
VMLINUX_SYMBOL(__per_cpu_load) = .; \
.data..percpu vaddr : AT(VMLINUX_SYMBOL(__per_cpu_load) \
- LOAD_OFFSET) { \
- VMLINUX_SYMBOL(__per_cpu_start) = .; \
- *(.data..percpu..first) \
- . = ALIGN(PAGE_SIZE); \
- *(.data..percpu..page_aligned) \
- . = ALIGN(cacheline); \
- *(.data..percpu..readmostly) \
- . = ALIGN(cacheline); \
- *(.data..percpu) \
- *(.data..percpu..shared_aligned) \
- VMLINUX_SYMBOL(__per_cpu_end) = .; \
+ PERCPU_INPUT(cacheline) \
} phdr \
. = VMLINUX_SYMBOL(__per_cpu_load) + SIZEOF(.data..percpu);
/**
- * PERCPU - define output section for percpu area, simple version
+ * PERCPU_SECTION - define output section for percpu area, simple version
* @cacheline: cacheline size
- * @align: required alignment
*
- * Align to @align and outputs output section for percpu area. This macro
- * doesn't manipulate @vaddr or @phdr and __per_cpu_load and
+ * Align to PAGE_SIZE and outputs output section for percpu area. This
+ * macro doesn't manipulate @vaddr or @phdr and __per_cpu_load and
* __per_cpu_start will be identical.
*
- * This macro is equivalent to ALIGN(@align); PERCPU_VADDR(@cacheline,,)
+ * This macro is equivalent to ALIGN(PAGE_SIZE); PERCPU_VADDR(@cacheline,,)
* except that __per_cpu_load is defined as a relative symbol against
* .data..percpu which is required for relocatable x86_32 configuration.
*/
-#define PERCPU(cacheline, align) \
- . = ALIGN(align); \
+#define PERCPU_SECTION(cacheline) \
+ . = ALIGN(PAGE_SIZE); \
.data..percpu : AT(ADDR(.data..percpu) - LOAD_OFFSET) { \
VMLINUX_SYMBOL(__per_cpu_load) = .; \
- VMLINUX_SYMBOL(__per_cpu_start) = .; \
- *(.data..percpu..first) \
- . = ALIGN(PAGE_SIZE); \
- *(.data..percpu..page_aligned) \
- . = ALIGN(cacheline); \
- *(.data..percpu..readmostly) \
- . = ALIGN(cacheline); \
- *(.data..percpu) \
- *(.data..percpu..shared_aligned) \
- VMLINUX_SYMBOL(__per_cpu_end) = .; \
+ PERCPU_INPUT(cacheline) \
}
diff --git a/include/drm/drmP.h b/include/drm/drmP.h
index 202424d..738b3a5 100644
--- a/include/drm/drmP.h
+++ b/include/drm/drmP.h
@@ -122,10 +122,14 @@
* using the DRM_DEBUG_KMS and DRM_DEBUG.
*/
-extern void drm_ut_debug_printk(unsigned int request_level,
+extern __attribute__((format (printf, 4, 5)))
+void drm_ut_debug_printk(unsigned int request_level,
const char *prefix,
const char *function_name,
const char *format, ...);
+extern __attribute__((format (printf, 2, 3)))
+int drm_err(const char *func, const char *format, ...);
+
/***********************************************************************/
/** \name DRM template customization defaults */
/*@{*/
@@ -181,21 +185,11 @@
* \param fmt printf() like format string.
* \param arg arguments
*/
-#define DRM_ERROR(fmt, arg...) \
- printk(KERN_ERR "[" DRM_NAME ":%s] *ERROR* " fmt , __func__ , ##arg)
+#define DRM_ERROR(fmt, ...) \
+ drm_err(__func__, fmt, ##__VA_ARGS__)
-/**
- * Memory error output.
- *
- * \param area memory area where the error occurred.
- * \param fmt printf() like format string.
- * \param arg arguments
- */
-#define DRM_MEM_ERROR(area, fmt, arg...) \
- printk(KERN_ERR "[" DRM_NAME ":%s:%s] *ERROR* " fmt , __func__, \
- drm_mem_stats[area].name , ##arg)
-
-#define DRM_INFO(fmt, arg...) printk(KERN_INFO "[" DRM_NAME "] " fmt , ##arg)
+#define DRM_INFO(fmt, ...) \
+ printk(KERN_INFO "[" DRM_NAME "] " fmt, ##__VA_ARGS__)
/**
* Debug output.
@@ -1000,6 +994,22 @@
struct drm_mode_group mode_group;
};
+/* mode specified on the command line */
+struct drm_cmdline_mode {
+ bool specified;
+ bool refresh_specified;
+ bool bpp_specified;
+ int xres, yres;
+ int bpp;
+ int refresh;
+ bool rb;
+ bool interlace;
+ bool cvt;
+ bool margins;
+ enum drm_connector_force force;
+};
+
+
struct drm_pending_vblank_event {
struct drm_pending_event base;
int pipe;
@@ -1395,6 +1405,15 @@
struct drm_crtc *refcrtc);
extern void drm_calc_timestamping_constants(struct drm_crtc *crtc);
+extern bool
+drm_mode_parse_command_line_for_connector(const char *mode_option,
+ struct drm_connector *connector,
+ struct drm_cmdline_mode *mode);
+
+extern struct drm_display_mode *
+drm_mode_create_from_cmdline_mode(struct drm_device *dev,
+ struct drm_cmdline_mode *cmd);
+
/* Modesetting support */
extern void drm_vblank_pre_modeset(struct drm_device *dev, int crtc);
extern void drm_vblank_post_modeset(struct drm_device *dev, int crtc);
diff --git a/include/drm/drm_crtc.h b/include/drm/drm_crtc.h
index d94684b..9573e0c 100644
--- a/include/drm/drm_crtc.h
+++ b/include/drm/drm_crtc.h
@@ -183,7 +183,9 @@
SubPixelNone,
};
-
+#define DRM_COLOR_FORMAT_RGB444 (1<<0)
+#define DRM_COLOR_FORMAT_YCRCB444 (1<<1)
+#define DRM_COLOR_FORMAT_YCRCB422 (1<<2)
/*
* Describes a given display (e.g. CRT or flat panel) and its limitations.
*/
@@ -198,8 +200,10 @@
unsigned int min_vfreq, max_vfreq;
unsigned int min_hfreq, max_hfreq;
unsigned int pixel_clock;
+ unsigned int bpc;
enum subpixel_order subpixel_order;
+ u32 color_formats;
char *raw_edid; /* if any */
};
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 83a389e..91567bb 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -53,6 +53,7 @@
#define DP_MAX_LANE_COUNT 0x002
# define DP_MAX_LANE_COUNT_MASK 0x1f
+# define DP_TPS3_SUPPORTED (1 << 6)
# define DP_ENHANCED_FRAME_CAP (1 << 7)
#define DP_MAX_DOWNSPREAD 0x003
@@ -71,10 +72,13 @@
#define DP_MAIN_LINK_CHANNEL_CODING 0x006
+#define DP_TRAINING_AUX_RD_INTERVAL 0x00e
+
/* link configuration */
#define DP_LINK_BW_SET 0x100
# define DP_LINK_BW_1_62 0x06
# define DP_LINK_BW_2_7 0x0a
+# define DP_LINK_BW_5_4 0x14
#define DP_LANE_COUNT_SET 0x101
# define DP_LANE_COUNT_MASK 0x0f
@@ -84,6 +88,7 @@
# define DP_TRAINING_PATTERN_DISABLE 0
# define DP_TRAINING_PATTERN_1 1
# define DP_TRAINING_PATTERN_2 2
+# define DP_TRAINING_PATTERN_3 3
# define DP_TRAINING_PATTERN_MASK 0x3
# define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2)
diff --git a/include/drm/drm_edid.h b/include/drm/drm_edid.h
index 5881fad..eacb415 100644
--- a/include/drm/drm_edid.h
+++ b/include/drm/drm_edid.h
@@ -155,12 +155,35 @@
#define DRM_EDID_INPUT_SEPARATE_SYNCS (1 << 3)
#define DRM_EDID_INPUT_BLANK_TO_BLACK (1 << 4)
#define DRM_EDID_INPUT_VIDEO_LEVEL (3 << 5)
-#define DRM_EDID_INPUT_DIGITAL (1 << 7) /* bits below must be zero if set */
+#define DRM_EDID_INPUT_DIGITAL (1 << 7)
+#define DRM_EDID_DIGITAL_DEPTH_MASK (7 << 4)
+#define DRM_EDID_DIGITAL_DEPTH_UNDEF (0 << 4)
+#define DRM_EDID_DIGITAL_DEPTH_6 (1 << 4)
+#define DRM_EDID_DIGITAL_DEPTH_8 (2 << 4)
+#define DRM_EDID_DIGITAL_DEPTH_10 (3 << 4)
+#define DRM_EDID_DIGITAL_DEPTH_12 (4 << 4)
+#define DRM_EDID_DIGITAL_DEPTH_14 (5 << 4)
+#define DRM_EDID_DIGITAL_DEPTH_16 (6 << 4)
+#define DRM_EDID_DIGITAL_DEPTH_RSVD (7 << 4)
+#define DRM_EDID_DIGITAL_TYPE_UNDEF (0)
+#define DRM_EDID_DIGITAL_TYPE_DVI (1)
+#define DRM_EDID_DIGITAL_TYPE_HDMI_A (2)
+#define DRM_EDID_DIGITAL_TYPE_HDMI_B (3)
+#define DRM_EDID_DIGITAL_TYPE_MDDI (4)
+#define DRM_EDID_DIGITAL_TYPE_DP (5)
#define DRM_EDID_FEATURE_DEFAULT_GTF (1 << 0)
#define DRM_EDID_FEATURE_PREFERRED_TIMING (1 << 1)
#define DRM_EDID_FEATURE_STANDARD_COLOR (1 << 2)
+/* If analog */
#define DRM_EDID_FEATURE_DISPLAY_TYPE (3 << 3) /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */
+/* If digital */
+#define DRM_EDID_FEATURE_COLOR_MASK (3 << 3)
+#define DRM_EDID_FEATURE_RGB (0 << 3)
+#define DRM_EDID_FEATURE_RGB_YCRCB444 (1 << 3)
+#define DRM_EDID_FEATURE_RGB_YCRCB422 (2 << 3)
+#define DRM_EDID_FEATURE_RGB_YCRCB (3 << 3) /* both 4:4:4 and 4:2:2 */
+
#define DRM_EDID_FEATURE_PM_ACTIVE_OFF (1 << 5)
#define DRM_EDID_FEATURE_PM_SUSPEND (1 << 6)
#define DRM_EDID_FEATURE_PM_STANDBY (1 << 7)
diff --git a/include/drm/drm_fb_helper.h b/include/drm/drm_fb_helper.h
index c99c3d3..6e3076a 100644
--- a/include/drm/drm_fb_helper.h
+++ b/include/drm/drm_fb_helper.h
@@ -40,20 +40,6 @@
struct drm_display_mode *desired_mode;
};
-/* mode specified on the command line */
-struct drm_fb_helper_cmdline_mode {
- bool specified;
- bool refresh_specified;
- bool bpp_specified;
- int xres, yres;
- int bpp;
- int refresh;
- bool rb;
- bool interlace;
- bool cvt;
- bool margins;
-};
-
struct drm_fb_helper_surface_size {
u32 fb_width;
u32 fb_height;
@@ -74,8 +60,8 @@
};
struct drm_fb_helper_connector {
- struct drm_fb_helper_cmdline_mode cmdline_mode;
struct drm_connector *connector;
+ struct drm_cmdline_mode cmdline_mode;
};
struct drm_fb_helper {
diff --git a/include/linux/Kbuild b/include/linux/Kbuild
index 75cf611..01f6362 100644
--- a/include/linux/Kbuild
+++ b/include/linux/Kbuild
@@ -4,6 +4,7 @@
header-y += dvb/
header-y += hdlc/
header-y += isdn/
+header-y += mmc/
header-y += nfsd/
header-y += raid/
header-y += spi/
@@ -302,6 +303,7 @@
header-y += ppp_defs.h
header-y += pps.h
header-y += prctl.h
+header-y += ptp_clock.h
header-y += ptrace.h
header-y += qnx4_fs.h
header-y += qnxtypes.h
@@ -372,6 +374,7 @@
header-y += usbdevice_fs.h
header-y += utime.h
header-y += utsname.h
+header-y += uvcvideo.h
header-y += v4l2-mediabus.h
header-y += v4l2-subdev.h
header-y += veth.h
diff --git a/include/linux/bitmap.h b/include/linux/bitmap.h
index daf8c48..dcafe0b 100644
--- a/include/linux/bitmap.h
+++ b/include/linux/bitmap.h
@@ -55,7 +55,8 @@
* bitmap_parse(buf, buflen, dst, nbits) Parse bitmap dst from kernel buf
* bitmap_parse_user(ubuf, ulen, dst, nbits) Parse bitmap dst from user buf
* bitmap_scnlistprintf(buf, len, src, nbits) Print bitmap src as list to buf
- * bitmap_parselist(buf, dst, nbits) Parse bitmap dst from list
+ * bitmap_parselist(buf, dst, nbits) Parse bitmap dst from kernel buf
+ * bitmap_parselist_user(buf, dst, nbits) Parse bitmap dst from user buf
* bitmap_find_free_region(bitmap, bits, order) Find and allocate bit region
* bitmap_release_region(bitmap, pos, order) Free specified bit region
* bitmap_allocate_region(bitmap, pos, order) Allocate specified bit region
@@ -129,6 +130,8 @@
const unsigned long *src, int nbits);
extern int bitmap_parselist(const char *buf, unsigned long *maskp,
int nmaskbits);
+extern int bitmap_parselist_user(const char __user *ubuf, unsigned int ulen,
+ unsigned long *dst, int nbits);
extern void bitmap_remap(unsigned long *dst, const unsigned long *src,
const unsigned long *old, const unsigned long *new, int bits);
extern int bitmap_bitremap(int oldbit,
diff --git a/include/linux/blk_types.h b/include/linux/blk_types.h
index be50d9e..2a7cea5 100644
--- a/include/linux/blk_types.h
+++ b/include/linux/blk_types.h
@@ -151,7 +151,6 @@
__REQ_IO_STAT, /* account I/O stat */
__REQ_MIXED_MERGE, /* merge of different types, fail separately */
__REQ_SECURE, /* secure discard (used with __REQ_DISCARD) */
- __REQ_ON_PLUG, /* on plug list */
__REQ_NR_BITS, /* stops here */
};
@@ -192,6 +191,5 @@
#define REQ_IO_STAT (1 << __REQ_IO_STAT)
#define REQ_MIXED_MERGE (1 << __REQ_MIXED_MERGE)
#define REQ_SECURE (1 << __REQ_SECURE)
-#define REQ_ON_PLUG (1 << __REQ_ON_PLUG)
#endif /* __LINUX_BLK_TYPES_H */
diff --git a/include/linux/blkdev.h b/include/linux/blkdev.h
index 2ad95fa..ae9091a 100644
--- a/include/linux/blkdev.h
+++ b/include/linux/blkdev.h
@@ -257,7 +257,7 @@
unsigned char misaligned;
unsigned char discard_misaligned;
unsigned char cluster;
- signed char discard_zeroes_data;
+ unsigned char discard_zeroes_data;
};
struct request_queue
@@ -364,6 +364,8 @@
* for flush operations
*/
unsigned int flush_flags;
+ unsigned int flush_not_queueable:1;
+ unsigned int flush_queue_delayed:1;
unsigned int flush_pending_idx:1;
unsigned int flush_running_idx:1;
unsigned long flush_pending_since;
@@ -843,6 +845,7 @@
extern void blk_queue_rq_timed_out(struct request_queue *, rq_timed_out_fn *);
extern void blk_queue_rq_timeout(struct request_queue *, unsigned int);
extern void blk_queue_flush(struct request_queue *q, unsigned int flush);
+extern void blk_queue_flush_queueable(struct request_queue *q, bool queueable);
extern struct backing_dev_info *blk_get_backing_dev_info(struct block_device *bdev);
extern int blk_rq_map_sg(struct request_queue *, struct request *, struct scatterlist *);
@@ -1066,13 +1069,16 @@
{
unsigned int alignment = (sector << 9) & (lim->discard_granularity - 1);
+ if (!lim->max_discard_sectors)
+ return 0;
+
return (lim->discard_granularity + lim->discard_alignment - alignment)
& (lim->discard_granularity - 1);
}
static inline unsigned int queue_discard_zeroes_data(struct request_queue *q)
{
- if (q->limits.discard_zeroes_data == 1)
+ if (q->limits.max_discard_sectors && q->limits.discard_zeroes_data == 1)
return 1;
return 0;
@@ -1111,6 +1117,11 @@
return bdev->bd_block_size;
}
+static inline bool queue_flush_queueable(struct request_queue *q)
+{
+ return !q->flush_not_queueable;
+}
+
typedef struct {struct page *v;} Sector;
unsigned char *read_dev_sector(struct block_device *, sector_t, Sector *);
diff --git a/include/linux/bootmem.h b/include/linux/bootmem.h
index 01eca17..ab344a5 100644
--- a/include/linux/bootmem.h
+++ b/include/linux/bootmem.h
@@ -99,24 +99,31 @@
unsigned long align,
unsigned long goal);
+#ifdef CONFIG_NO_BOOTMEM
+/* We are using top down, so it is safe to use 0 here */
+#define BOOTMEM_LOW_LIMIT 0
+#else
+#define BOOTMEM_LOW_LIMIT __pa(MAX_DMA_ADDRESS)
+#endif
+
#define alloc_bootmem(x) \
- __alloc_bootmem(x, SMP_CACHE_BYTES, __pa(MAX_DMA_ADDRESS))
+ __alloc_bootmem(x, SMP_CACHE_BYTES, BOOTMEM_LOW_LIMIT)
#define alloc_bootmem_align(x, align) \
- __alloc_bootmem(x, align, __pa(MAX_DMA_ADDRESS))
+ __alloc_bootmem(x, align, BOOTMEM_LOW_LIMIT)
#define alloc_bootmem_nopanic(x) \
- __alloc_bootmem_nopanic(x, SMP_CACHE_BYTES, __pa(MAX_DMA_ADDRESS))
+ __alloc_bootmem_nopanic(x, SMP_CACHE_BYTES, BOOTMEM_LOW_LIMIT)
#define alloc_bootmem_pages(x) \
- __alloc_bootmem(x, PAGE_SIZE, __pa(MAX_DMA_ADDRESS))
+ __alloc_bootmem(x, PAGE_SIZE, BOOTMEM_LOW_LIMIT)
#define alloc_bootmem_pages_nopanic(x) \
- __alloc_bootmem_nopanic(x, PAGE_SIZE, __pa(MAX_DMA_ADDRESS))
+ __alloc_bootmem_nopanic(x, PAGE_SIZE, BOOTMEM_LOW_LIMIT)
#define alloc_bootmem_node(pgdat, x) \
- __alloc_bootmem_node(pgdat, x, SMP_CACHE_BYTES, __pa(MAX_DMA_ADDRESS))
+ __alloc_bootmem_node(pgdat, x, SMP_CACHE_BYTES, BOOTMEM_LOW_LIMIT)
#define alloc_bootmem_node_nopanic(pgdat, x) \
- __alloc_bootmem_node_nopanic(pgdat, x, SMP_CACHE_BYTES, __pa(MAX_DMA_ADDRESS))
+ __alloc_bootmem_node_nopanic(pgdat, x, SMP_CACHE_BYTES, BOOTMEM_LOW_LIMIT)
#define alloc_bootmem_pages_node(pgdat, x) \
- __alloc_bootmem_node(pgdat, x, PAGE_SIZE, __pa(MAX_DMA_ADDRESS))
+ __alloc_bootmem_node(pgdat, x, PAGE_SIZE, BOOTMEM_LOW_LIMIT)
#define alloc_bootmem_pages_node_nopanic(pgdat, x) \
- __alloc_bootmem_node_nopanic(pgdat, x, PAGE_SIZE, __pa(MAX_DMA_ADDRESS))
+ __alloc_bootmem_node_nopanic(pgdat, x, PAGE_SIZE, BOOTMEM_LOW_LIMIT)
#define alloc_bootmem_low(x) \
__alloc_bootmem_low(x, SMP_CACHE_BYTES, 0)
diff --git a/include/linux/c2port.h b/include/linux/c2port.h
index 2a5cd86..a2f7d74 100644
--- a/include/linux/c2port.h
+++ b/include/linux/c2port.h
@@ -60,9 +60,6 @@
* Exported functions
*/
-#define to_class_dev(obj) container_of((obj), struct class_device, kobj)
-#define to_c2port_device(obj) container_of((obj), struct c2port_device, class)
-
extern struct c2port_device *c2port_device_register(char *name,
struct c2port_ops *ops, void *devdata);
extern void c2port_device_unregister(struct c2port_device *dev);
diff --git a/include/linux/capability.h b/include/linux/capability.h
index 4554db0..c421123 100644
--- a/include/linux/capability.h
+++ b/include/linux/capability.h
@@ -417,7 +417,6 @@
# define CAP_EMPTY_SET ((kernel_cap_t){{ 0, 0 }})
# define CAP_FULL_SET ((kernel_cap_t){{ ~0, ~0 }})
-# define CAP_INIT_EFF_SET ((kernel_cap_t){{ ~CAP_TO_MASK(CAP_SETPCAP), ~0 }})
# define CAP_FS_SET ((kernel_cap_t){{ CAP_FS_MASK_B0 \
| CAP_TO_MASK(CAP_LINUX_IMMUTABLE), \
CAP_FS_MASK_B1 } })
@@ -427,11 +426,7 @@
#endif /* _KERNEL_CAPABILITY_U32S != 2 */
-#define CAP_INIT_INH_SET CAP_EMPTY_SET
-
# define cap_clear(c) do { (c) = __cap_empty_set; } while (0)
-# define cap_set_full(c) do { (c) = __cap_full_set; } while (0)
-# define cap_set_init_eff(c) do { (c) = __cap_init_eff_set; } while (0)
#define cap_raise(c, flag) ((c).cap[CAP_TO_INDEX(flag)] |= CAP_TO_MASK(flag))
#define cap_lower(c, flag) ((c).cap[CAP_TO_INDEX(flag)] &= ~CAP_TO_MASK(flag))
diff --git a/include/linux/ceph/ceph_fs.h b/include/linux/ceph/ceph_fs.h
index b8e995f..b8c6069 100644
--- a/include/linux/ceph/ceph_fs.h
+++ b/include/linux/ceph/ceph_fs.h
@@ -313,6 +313,7 @@
CEPH_MDS_OP_GETATTR = 0x00101,
CEPH_MDS_OP_LOOKUPHASH = 0x00102,
CEPH_MDS_OP_LOOKUPPARENT = 0x00103,
+ CEPH_MDS_OP_LOOKUPINO = 0x00104,
CEPH_MDS_OP_SETXATTR = 0x01105,
CEPH_MDS_OP_RMXATTR = 0x01106,
diff --git a/include/linux/clocksource.h b/include/linux/clocksource.h
index c918fbd..d4646b4 100644
--- a/include/linux/clocksource.h
+++ b/include/linux/clocksource.h
@@ -337,6 +337,14 @@
extern void timekeeping_notify(struct clocksource *clock);
+extern cycle_t clocksource_mmio_readl_up(struct clocksource *);
+extern cycle_t clocksource_mmio_readl_down(struct clocksource *);
+extern cycle_t clocksource_mmio_readw_up(struct clocksource *);
+extern cycle_t clocksource_mmio_readw_down(struct clocksource *);
+
+extern int clocksource_mmio_init(void __iomem *, const char *,
+ unsigned long, int, unsigned, cycle_t (*)(struct clocksource *));
+
extern int clocksource_i8253_init(void);
#endif /* _LINUX_CLOCKSOURCE_H */
diff --git a/include/linux/compat.h b/include/linux/compat.h
index 5778b55..ddcb7db 100644
--- a/include/linux/compat.h
+++ b/include/linux/compat.h
@@ -12,6 +12,8 @@
#include <linux/sem.h>
#include <linux/socket.h>
#include <linux/if.h>
+#include <linux/fs.h>
+#include <linux/aio_abi.h> /* for aio_context_t */
#include <asm/compat.h>
#include <asm/siginfo.h>
@@ -26,7 +28,7 @@
struct compat_sel_arg_struct;
struct rusage;
-struct compat_itimerspec {
+struct compat_itimerspec {
struct compat_timespec it_interval;
struct compat_timespec it_value;
};
@@ -70,9 +72,9 @@
compat_long_t stbcnt;
compat_int_t tai;
- compat_int_t :32; compat_int_t :32; compat_int_t :32; compat_int_t :32;
- compat_int_t :32; compat_int_t :32; compat_int_t :32; compat_int_t :32;
- compat_int_t :32; compat_int_t :32; compat_int_t :32;
+ compat_int_t:32; compat_int_t:32; compat_int_t:32; compat_int_t:32;
+ compat_int_t:32; compat_int_t:32; compat_int_t:32; compat_int_t:32;
+ compat_int_t:32; compat_int_t:32; compat_int_t:32;
};
#define _COMPAT_NSIG_WORDS (_COMPAT_NSIG / _COMPAT_NSIG_BPW)
@@ -81,8 +83,10 @@
compat_sigset_word sig[_COMPAT_NSIG_WORDS];
} compat_sigset_t;
-extern int get_compat_timespec(struct timespec *, const struct compat_timespec __user *);
-extern int put_compat_timespec(const struct timespec *, struct compat_timespec __user *);
+extern int get_compat_timespec(struct timespec *,
+ const struct compat_timespec __user *);
+extern int put_compat_timespec(const struct timespec *,
+ struct compat_timespec __user *);
struct compat_iovec {
compat_uptr_t iov_base;
@@ -113,7 +117,8 @@
compat_long_t ru_nivcsw;
};
-extern int put_compat_rusage(const struct rusage *, struct compat_rusage __user *);
+extern int put_compat_rusage(const struct rusage *,
+ struct compat_rusage __user *);
struct compat_siginfo;
@@ -166,8 +171,7 @@
unsigned char port;
};
-struct compat_if_settings
-{
+struct compat_if_settings {
unsigned int type; /* Type of physical device or protocol */
unsigned int size; /* Size of the data allocated by the caller */
compat_uptr_t ifs_ifsu; /* union of pointers */
@@ -195,8 +199,8 @@
};
struct compat_ifconf {
- compat_int_t ifc_len; /* size of buffer */
- compat_caddr_t ifcbuf;
+ compat_int_t ifc_len; /* size of buffer */
+ compat_caddr_t ifcbuf;
};
struct compat_robust_list {
@@ -209,6 +213,18 @@
compat_uptr_t list_op_pending;
};
+struct compat_statfs;
+struct compat_statfs64;
+struct compat_old_linux_dirent;
+struct compat_linux_dirent;
+struct linux_dirent64;
+struct compat_msghdr;
+struct compat_mmsghdr;
+struct compat_sysinfo;
+struct compat_sysctl_args;
+struct compat_kexec_segment;
+struct compat_mq_attr;
+
extern void compat_exit_robust_list(struct task_struct *curr);
asmlinkage long
@@ -243,8 +259,8 @@
const struct compat_iovec __user *vec,
unsigned long vlen, u32 pos_low, u32 pos_high);
-int compat_do_execve(char * filename, compat_uptr_t __user *argv,
- compat_uptr_t __user *envp, struct pt_regs * regs);
+int compat_do_execve(char *filename, compat_uptr_t __user *argv,
+ compat_uptr_t __user *envp, struct pt_regs *regs);
asmlinkage long compat_sys_select(int n, compat_ulong_t __user *inp,
compat_ulong_t __user *outp, compat_ulong_t __user *exp,
@@ -331,12 +347,18 @@
const compat_sigset_t __user *sigmask,
compat_size_t sigsetsize);
-asmlinkage long compat_sys_utimensat(unsigned int dfd, const char __user *filename,
- struct compat_timespec __user *t, int flags);
+asmlinkage long compat_sys_utime(const char __user *filename,
+ struct compat_utimbuf __user *t);
+asmlinkage long compat_sys_utimensat(unsigned int dfd,
+ const char __user *filename,
+ struct compat_timespec __user *t,
+ int flags);
+asmlinkage long compat_sys_time(compat_time_t __user *tloc);
+asmlinkage long compat_sys_stime(compat_time_t __user *tptr);
asmlinkage long compat_sys_signalfd(int ufd,
- const compat_sigset_t __user *sigmask,
- compat_size_t sigsetsize);
+ const compat_sigset_t __user *sigmask,
+ compat_size_t sigsetsize);
asmlinkage long compat_sys_timerfd_settime(int ufd, int flags,
const struct compat_itimerspec __user *utmr,
struct compat_itimerspec __user *otmr);
@@ -348,16 +370,190 @@
const int __user *nodes,
int __user *status,
int flags);
-asmlinkage long compat_sys_futimesat(unsigned int dfd, const char __user *filename,
+asmlinkage long compat_sys_futimesat(unsigned int dfd,
+ const char __user *filename,
struct compat_timeval __user *t);
-asmlinkage long compat_sys_newfstatat(unsigned int dfd, const char __user * filename,
+asmlinkage long compat_sys_utimes(const char __user *filename,
+ struct compat_timeval __user *t);
+asmlinkage long compat_sys_newstat(const char __user *filename,
+ struct compat_stat __user *statbuf);
+asmlinkage long compat_sys_newlstat(const char __user *filename,
+ struct compat_stat __user *statbuf);
+asmlinkage long compat_sys_newfstatat(unsigned int dfd,
+ const char __user *filename,
struct compat_stat __user *statbuf,
int flag);
+asmlinkage long compat_sys_newfstat(unsigned int fd,
+ struct compat_stat __user *statbuf);
+asmlinkage long compat_sys_statfs(const char __user *pathname,
+ struct compat_statfs __user *buf);
+asmlinkage long compat_sys_fstatfs(unsigned int fd,
+ struct compat_statfs __user *buf);
+asmlinkage long compat_sys_statfs64(const char __user *pathname,
+ compat_size_t sz,
+ struct compat_statfs64 __user *buf);
+asmlinkage long compat_sys_fstatfs64(unsigned int fd, compat_size_t sz,
+ struct compat_statfs64 __user *buf);
+asmlinkage long compat_sys_fcntl64(unsigned int fd, unsigned int cmd,
+ unsigned long arg);
+asmlinkage long compat_sys_fcntl(unsigned int fd, unsigned int cmd,
+ unsigned long arg);
+asmlinkage long compat_sys_io_setup(unsigned nr_reqs, u32 __user *ctx32p);
+asmlinkage long compat_sys_io_getevents(aio_context_t ctx_id,
+ unsigned long min_nr,
+ unsigned long nr,
+ struct io_event __user *events,
+ struct compat_timespec __user *timeout);
+asmlinkage long compat_sys_io_submit(aio_context_t ctx_id, int nr,
+ u32 __user *iocb);
+asmlinkage long compat_sys_mount(const char __user *dev_name,
+ const char __user *dir_name,
+ const char __user *type, unsigned long flags,
+ const void __user *data);
+asmlinkage long compat_sys_old_readdir(unsigned int fd,
+ struct compat_old_linux_dirent __user *,
+ unsigned int count);
+asmlinkage long compat_sys_getdents(unsigned int fd,
+ struct compat_linux_dirent __user *dirent,
+ unsigned int count);
+asmlinkage long compat_sys_getdents64(unsigned int fd,
+ struct linux_dirent64 __user *dirent,
+ unsigned int count);
+asmlinkage long compat_sys_vmsplice(int fd, const struct compat_iovec __user *,
+ unsigned int nr_segs, unsigned int flags);
+asmlinkage long compat_sys_open(const char __user *filename, int flags,
+ int mode);
asmlinkage long compat_sys_openat(unsigned int dfd, const char __user *filename,
int flags, int mode);
+asmlinkage long compat_sys_open_by_handle_at(int mountdirfd,
+ struct file_handle __user *handle,
+ int flags);
+asmlinkage long compat_sys_pselect6(int n, compat_ulong_t __user *inp,
+ compat_ulong_t __user *outp,
+ compat_ulong_t __user *exp,
+ struct compat_timespec __user *tsp,
+ void __user *sig);
+asmlinkage long compat_sys_ppoll(struct pollfd __user *ufds,
+ unsigned int nfds,
+ struct compat_timespec __user *tsp,
+ const compat_sigset_t __user *sigmask,
+ compat_size_t sigsetsize);
+#if (defined(CONFIG_NFSD) || defined(CONFIG_NFSD_MODULE)) && \
+ !defined(CONFIG_NFSD_DEPRECATED)
+union compat_nfsctl_res;
+struct compat_nfsctl_arg;
+asmlinkage long compat_sys_nfsservctl(int cmd,
+ struct compat_nfsctl_arg __user *arg,
+ union compat_nfsctl_res __user *res);
+#else
+asmlinkage long compat_sys_nfsservctl(int cmd, void *notused, void *notused2);
+#endif
+asmlinkage long compat_sys_signalfd4(int ufd,
+ const compat_sigset_t __user *sigmask,
+ compat_size_t sigsetsize, int flags);
+asmlinkage long compat_sys_get_mempolicy(int __user *policy,
+ compat_ulong_t __user *nmask,
+ compat_ulong_t maxnode,
+ compat_ulong_t addr,
+ compat_ulong_t flags);
+asmlinkage long compat_sys_set_mempolicy(int mode, compat_ulong_t __user *nmask,
+ compat_ulong_t maxnode);
+asmlinkage long compat_sys_mbind(compat_ulong_t start, compat_ulong_t len,
+ compat_ulong_t mode,
+ compat_ulong_t __user *nmask,
+ compat_ulong_t maxnode, compat_ulong_t flags);
+
+asmlinkage long compat_sys_setsockopt(int fd, int level, int optname,
+ char __user *optval, unsigned int optlen);
+asmlinkage long compat_sys_sendmsg(int fd, struct compat_msghdr __user *msg,
+ unsigned flags);
+asmlinkage long compat_sys_recvmsg(int fd, struct compat_msghdr __user *msg,
+ unsigned int flags);
+asmlinkage long compat_sys_recv(int fd, void __user *buf, size_t len,
+ unsigned flags);
+asmlinkage long compat_sys_recvfrom(int fd, void __user *buf, size_t len,
+ unsigned flags, struct sockaddr __user *addr,
+ int __user *addrlen);
+asmlinkage long compat_sys_recvmmsg(int fd, struct compat_mmsghdr __user *mmsg,
+ unsigned vlen, unsigned int flags,
+ struct compat_timespec __user *timeout);
+asmlinkage long compat_sys_nanosleep(struct compat_timespec __user *rqtp,
+ struct compat_timespec __user *rmtp);
+asmlinkage long compat_sys_getitimer(int which,
+ struct compat_itimerval __user *it);
+asmlinkage long compat_sys_setitimer(int which,
+ struct compat_itimerval __user *in,
+ struct compat_itimerval __user *out);
+asmlinkage long compat_sys_times(struct compat_tms __user *tbuf);
+asmlinkage long compat_sys_setrlimit(unsigned int resource,
+ struct compat_rlimit __user *rlim);
+asmlinkage long compat_sys_getrlimit(unsigned int resource,
+ struct compat_rlimit __user *rlim);
+asmlinkage long compat_sys_getrusage(int who, struct compat_rusage __user *ru);
+asmlinkage long compat_sys_sched_setaffinity(compat_pid_t pid,
+ unsigned int len,
+ compat_ulong_t __user *user_mask_ptr);
+asmlinkage long compat_sys_sched_getaffinity(compat_pid_t pid,
+ unsigned int len,
+ compat_ulong_t __user *user_mask_ptr);
+asmlinkage long compat_sys_timer_create(clockid_t which_clock,
+ struct compat_sigevent __user *timer_event_spec,
+ timer_t __user *created_timer_id);
+asmlinkage long compat_sys_timer_settime(timer_t timer_id, int flags,
+ struct compat_itimerspec __user *new,
+ struct compat_itimerspec __user *old);
+asmlinkage long compat_sys_timer_gettime(timer_t timer_id,
+ struct compat_itimerspec __user *setting);
+asmlinkage long compat_sys_clock_settime(clockid_t which_clock,
+ struct compat_timespec __user *tp);
+asmlinkage long compat_sys_clock_gettime(clockid_t which_clock,
+ struct compat_timespec __user *tp);
+asmlinkage long compat_sys_clock_adjtime(clockid_t which_clock,
+ struct compat_timex __user *tp);
+asmlinkage long compat_sys_clock_getres(clockid_t which_clock,
+ struct compat_timespec __user *tp);
+asmlinkage long compat_sys_clock_nanosleep(clockid_t which_clock, int flags,
+ struct compat_timespec __user *rqtp,
+ struct compat_timespec __user *rmtp);
+asmlinkage long compat_sys_rt_sigtimedwait(compat_sigset_t __user *uthese,
+ struct compat_siginfo __user *uinfo,
+ struct compat_timespec __user *uts, compat_size_t sigsetsize);
+asmlinkage long compat_sys_rt_sigsuspend(compat_sigset_t __user *unewset,
+ compat_size_t sigsetsize);
+asmlinkage long compat_sys_sysinfo(struct compat_sysinfo __user *info);
+asmlinkage long compat_sys_ioctl(unsigned int fd, unsigned int cmd,
+ unsigned long arg);
+asmlinkage long compat_sys_futex(u32 __user *uaddr, int op, u32 val,
+ struct compat_timespec __user *utime, u32 __user *uaddr2,
+ u32 val3);
+asmlinkage long compat_sys_getsockopt(int fd, int level, int optname,
+ char __user *optval, int __user *optlen);
+asmlinkage long compat_sys_kexec_load(unsigned long entry,
+ unsigned long nr_segments,
+ struct compat_kexec_segment __user *,
+ unsigned long flags);
+asmlinkage long compat_sys_mq_getsetattr(mqd_t mqdes,
+ const struct compat_mq_attr __user *u_mqstat,
+ struct compat_mq_attr __user *u_omqstat);
+asmlinkage long compat_sys_mq_notify(mqd_t mqdes,
+ const struct compat_sigevent __user *u_notification);
+asmlinkage long compat_sys_mq_open(const char __user *u_name,
+ int oflag, compat_mode_t mode,
+ struct compat_mq_attr __user *u_attr);
+asmlinkage long compat_sys_mq_timedsend(mqd_t mqdes,
+ const char __user *u_msg_ptr,
+ size_t msg_len, unsigned int msg_prio,
+ const struct compat_timespec __user *u_abs_timeout);
+asmlinkage ssize_t compat_sys_mq_timedreceive(mqd_t mqdes,
+ char __user *u_msg_ptr,
+ size_t msg_len, unsigned int __user *u_msg_prio,
+ const struct compat_timespec __user *u_abs_timeout);
+asmlinkage long compat_sys_socketcall(int call, u32 __user *args);
+asmlinkage long compat_sys_sysctl(struct compat_sysctl_args __user *args);
extern ssize_t compat_rw_copy_check_uvector(int type,
- const struct compat_iovec __user *uvector, unsigned long nr_segs,
+ const struct compat_iovec __user *uvector,
+ unsigned long nr_segs,
unsigned long fast_segs, struct iovec *fast_pointer,
struct iovec **ret_pointer);
diff --git a/include/linux/compiler-gcc.h b/include/linux/compiler-gcc.h
index cb4c1eb7..59e4028 100644
--- a/include/linux/compiler-gcc.h
+++ b/include/linux/compiler-gcc.h
@@ -34,8 +34,12 @@
__asm__ ("" : "=r"(__ptr) : "0"(ptr)); \
(typeof(ptr)) (__ptr + (off)); })
+#ifdef __CHECKER__
+#define __must_be_array(arr) 0
+#else
/* &a[0] degrades to a pointer: a different type from an array */
#define __must_be_array(a) BUILD_BUG_ON_ZERO(__same_type((a), &(a)[0]))
+#endif
/*
* Force always-inline if the user requests it so via the .config,
diff --git a/include/linux/compiler-gcc4.h b/include/linux/compiler-gcc4.h
index 64b7c00..dfadc96 100644
--- a/include/linux/compiler-gcc4.h
+++ b/include/linux/compiler-gcc4.h
@@ -51,7 +51,7 @@
#if __GNUC_MINOR__ > 0
#define __compiletime_object_size(obj) __builtin_object_size(obj, 0)
#endif
-#if __GNUC_MINOR__ >= 4
+#if __GNUC_MINOR__ >= 4 && !defined(__CHECKER__)
#define __compiletime_warning(message) __attribute__((warning(message)))
#define __compiletime_error(message) __attribute__((error(message)))
#endif
diff --git a/include/linux/cpumask.h b/include/linux/cpumask.h
index bae6fe2..b24ac56 100644
--- a/include/linux/cpumask.h
+++ b/include/linux/cpumask.h
@@ -547,6 +547,21 @@
}
/**
+ * cpumask_parselist_user - extract a cpumask from a user string
+ * @buf: the buffer to extract from
+ * @len: the length of the buffer
+ * @dstp: the cpumask to set.
+ *
+ * Returns -errno, or 0 for success.
+ */
+static inline int cpumask_parselist_user(const char __user *buf, int len,
+ struct cpumask *dstp)
+{
+ return bitmap_parselist_user(buf, len, cpumask_bits(dstp),
+ nr_cpumask_bits);
+}
+
+/**
* cpulist_scnprintf - print a cpumask into a string as comma-separated list
* @buf: the buffer to sprintf into
* @len: the length of the buffer
diff --git a/include/linux/dlm_plock.h b/include/linux/dlm_plock.h
index 2dd2124..3b1cc1b 100644
--- a/include/linux/dlm_plock.h
+++ b/include/linux/dlm_plock.h
@@ -14,7 +14,7 @@
#define DLM_PLOCK_MISC_NAME "dlm_plock"
#define DLM_PLOCK_VERSION_MAJOR 1
-#define DLM_PLOCK_VERSION_MINOR 1
+#define DLM_PLOCK_VERSION_MINOR 2
#define DLM_PLOCK_VERSION_PATCH 0
enum {
@@ -23,12 +23,14 @@
DLM_PLOCK_OP_GET,
};
+#define DLM_PLOCK_FL_CLOSE 1
+
struct dlm_plock_info {
__u32 version[3];
__u8 optype;
__u8 ex;
__u8 wait;
- __u8 pad;
+ __u8 flags;
__u32 pid;
__s32 nodeid;
__s32 rv;
diff --git a/include/linux/drbd.h b/include/linux/drbd.h
index cec467f..9e5f560 100644
--- a/include/linux/drbd.h
+++ b/include/linux/drbd.h
@@ -38,7 +38,7 @@
/* Although the Linux source code makes a difference between
generic endianness and the bitfields' endianness, there is no
- architecture as of Linux-2.6.24-rc4 where the bitfileds' endianness
+ architecture as of Linux-2.6.24-rc4 where the bitfields' endianness
does not match the generic endianness. */
#if __BYTE_ORDER == __LITTLE_ENDIAN
@@ -53,7 +53,7 @@
extern const char *drbd_buildtag(void);
-#define REL_VERSION "8.3.10"
+#define REL_VERSION "8.3.11"
#define API_VERSION 88
#define PRO_VERSION_MIN 86
#define PRO_VERSION_MAX 96
@@ -195,7 +195,7 @@
C_WF_REPORT_PARAMS, /* we have a socket */
C_CONNECTED, /* we have introduced each other */
C_STARTING_SYNC_S, /* starting full sync by admin request. */
- C_STARTING_SYNC_T, /* stariing full sync by admin request. */
+ C_STARTING_SYNC_T, /* starting full sync by admin request. */
C_WF_BITMAP_S,
C_WF_BITMAP_T,
C_WF_SYNC_UUID,
@@ -236,7 +236,7 @@
* pointed out by Maxim Uvarov q<muvarov@ru.mvista.com>
* even though we transmit as "cpu_to_be32(state)",
* the offsets of the bitfields still need to be swapped
- * on different endianess.
+ * on different endianness.
*/
struct {
#if defined(__LITTLE_ENDIAN_BITFIELD)
@@ -266,7 +266,7 @@
unsigned peer:2 ; /* 3/4 primary/secondary/unknown */
unsigned role:2 ; /* 3/4 primary/secondary/unknown */
#else
-# error "this endianess is not supported"
+# error "this endianness is not supported"
#endif
};
unsigned int i;
diff --git a/include/linux/drbd_tag_magic.h b/include/linux/drbd_tag_magic.h
index f14a165..0695431 100644
--- a/include/linux/drbd_tag_magic.h
+++ b/include/linux/drbd_tag_magic.h
@@ -30,7 +30,7 @@
int tag_and_len ## member;
#include "linux/drbd_nl.h"
-/* declate tag-list-sizes */
+/* declare tag-list-sizes */
static const int tag_list_sizes[] = {
#define NL_PACKET(name, number, fields) 2 fields ,
#define NL_INTEGER(pn, pr, member) + 4 + 4
diff --git a/include/linux/dvb/frontend.h b/include/linux/dvb/frontend.h
index 493a2bf..36a3ed6 100644
--- a/include/linux/dvb/frontend.h
+++ b/include/linux/dvb/frontend.h
@@ -175,14 +175,20 @@
TRANSMISSION_MODE_2K,
TRANSMISSION_MODE_8K,
TRANSMISSION_MODE_AUTO,
- TRANSMISSION_MODE_4K
+ TRANSMISSION_MODE_4K,
+ TRANSMISSION_MODE_1K,
+ TRANSMISSION_MODE_16K,
+ TRANSMISSION_MODE_32K,
} fe_transmit_mode_t;
typedef enum fe_bandwidth {
BANDWIDTH_8_MHZ,
BANDWIDTH_7_MHZ,
BANDWIDTH_6_MHZ,
- BANDWIDTH_AUTO
+ BANDWIDTH_AUTO,
+ BANDWIDTH_5_MHZ,
+ BANDWIDTH_10_MHZ,
+ BANDWIDTH_1_712_MHZ,
} fe_bandwidth_t;
@@ -191,7 +197,10 @@
GUARD_INTERVAL_1_16,
GUARD_INTERVAL_1_8,
GUARD_INTERVAL_1_4,
- GUARD_INTERVAL_AUTO
+ GUARD_INTERVAL_AUTO,
+ GUARD_INTERVAL_1_128,
+ GUARD_INTERVAL_19_128,
+ GUARD_INTERVAL_19_256,
} fe_guard_interval_t;
@@ -305,7 +314,9 @@
#define DTV_ISDBS_TS_ID 42
-#define DTV_MAX_COMMAND DTV_ISDBS_TS_ID
+#define DTV_DVBT2_PLP_ID 43
+
+#define DTV_MAX_COMMAND DTV_DVBT2_PLP_ID
typedef enum fe_pilot {
PILOT_ON,
@@ -337,6 +348,7 @@
SYS_DMBTH,
SYS_CMMB,
SYS_DAB,
+ SYS_DVBT2,
} fe_delivery_system_t;
struct dtv_cmds_h {
diff --git a/include/linux/dvb/version.h b/include/linux/dvb/version.h
index 5a7546c..1421cc8 100644
--- a/include/linux/dvb/version.h
+++ b/include/linux/dvb/version.h
@@ -24,6 +24,6 @@
#define _DVBVERSION_H_
#define DVB_API_VERSION 5
-#define DVB_API_VERSION_MINOR 2
+#define DVB_API_VERSION_MINOR 3
#endif /*_DVBVERSION_H_*/
diff --git a/include/linux/elf.h b/include/linux/elf.h
index 4d60801..110821c 100644
--- a/include/linux/elf.h
+++ b/include/linux/elf.h
@@ -395,6 +395,7 @@
#define NT_S390_CTRS 0x304 /* s390 control registers */
#define NT_S390_PREFIX 0x305 /* s390 prefix register */
#define NT_S390_LAST_BREAK 0x306 /* s390 breaking event address */
+#define NT_ARM_VFP 0x400 /* ARM VFP/NEON registers */
/* Note header in a PT_NOTE section */
diff --git a/include/linux/fs.h b/include/linux/fs.h
index cdf9495..3f9d325 100644
--- a/include/linux/fs.h
+++ b/include/linux/fs.h
@@ -23,7 +23,8 @@
/* Fixed constants first: */
#undef NR_OPEN
-#define INR_OPEN 1024 /* Initial setting for nfile rlimits */
+#define INR_OPEN_CUR 1024 /* Initial setting for nfile rlimits */
+#define INR_OPEN_MAX 4096 /* Hard limit for nfile rlimits */
#define BLOCK_SIZE_BITS 10
#define BLOCK_SIZE (1<<BLOCK_SIZE_BITS)
@@ -634,8 +635,7 @@
unsigned int i_mmap_writable;/* count VM_SHARED mappings */
struct prio_tree_root i_mmap; /* tree of private and shared mappings */
struct list_head i_mmap_nonlinear;/*list VM_NONLINEAR mappings */
- spinlock_t i_mmap_lock; /* protect tree, count, list */
- unsigned int truncate_count; /* Cover race condition with truncate */
+ struct mutex i_mmap_mutex; /* protect tree, count, list */
unsigned long nrpages; /* number of total pages */
pgoff_t writeback_index;/* writeback starts here */
const struct address_space_operations *a_ops; /* methods */
@@ -644,7 +644,6 @@
spinlock_t private_lock; /* for use by the address_space */
struct list_head private_list; /* ditto */
struct address_space *assoc_mapping; /* ditto */
- struct mutex unmap_mutex; /* to protect unmapping */
} __attribute__((aligned(sizeof(long))));
/*
* On most architectures that alignment is already the case; but
diff --git a/include/linux/fscache-cache.h b/include/linux/fscache-cache.h
index 76427e6..af095b5 100644
--- a/include/linux/fscache-cache.h
+++ b/include/linux/fscache-cache.h
@@ -100,17 +100,6 @@
/* operation releaser */
fscache_operation_release_t release;
-
-#ifdef CONFIG_WORKQUEUE_DEBUGFS
- struct work_struct put_work; /* work to delay operation put */
- const char *name; /* operation name */
- const char *state; /* operation state */
-#define fscache_set_op_name(OP, N) do { (OP)->name = (N); } while(0)
-#define fscache_set_op_state(OP, S) do { (OP)->state = (S); } while(0)
-#else
-#define fscache_set_op_name(OP, N) do { } while(0)
-#define fscache_set_op_state(OP, S) do { } while(0)
-#endif
};
extern atomic_t fscache_op_debug_id;
@@ -137,7 +126,6 @@
op->processor = processor;
op->release = release;
INIT_LIST_HEAD(&op->pend_link);
- fscache_set_op_state(op, "Init");
}
/*
diff --git a/include/linux/fsl_devices.h b/include/linux/fsl_devices.h
index 4eb56ed..fffdf00 100644
--- a/include/linux/fsl_devices.h
+++ b/include/linux/fsl_devices.h
@@ -72,6 +72,7 @@
void (*exit)(struct platform_device *);
void __iomem *regs; /* ioremap'd register base */
struct clk *clk;
+ unsigned power_budget; /* hcd->power_budget */
unsigned big_endian_mmio:1;
unsigned big_endian_desc:1;
unsigned es:1; /* need USBMODE:ES */
@@ -79,6 +80,21 @@
unsigned have_sysif_regs:1;
unsigned invert_drvvbus:1;
unsigned invert_pwr_fault:1;
+
+ unsigned suspended:1;
+ unsigned already_suspended:1;
+
+ /* register save area for suspend/resume */
+ u32 pm_command;
+ u32 pm_status;
+ u32 pm_intr_enable;
+ u32 pm_frame_index;
+ u32 pm_segment;
+ u32 pm_frame_list;
+ u32 pm_async_next;
+ u32 pm_configured_flag;
+ u32 pm_portsc;
+ u32 pm_usbgenctrl;
};
/* Flags in fsl_usb2_mph_platform_data */
diff --git a/include/linux/genalloc.h b/include/linux/genalloc.h
index 9869ef3..5bbebda 100644
--- a/include/linux/genalloc.h
+++ b/include/linux/genalloc.h
@@ -9,6 +9,8 @@
*/
+#ifndef __GENALLOC_H__
+#define __GENALLOC_H__
/*
* General purpose special memory pool descriptor.
*/
@@ -24,13 +26,34 @@
struct gen_pool_chunk {
spinlock_t lock;
struct list_head next_chunk; /* next chunk in pool */
+ phys_addr_t phys_addr; /* physical starting address of memory chunk */
unsigned long start_addr; /* starting address of memory chunk */
unsigned long end_addr; /* ending address of memory chunk */
unsigned long bits[0]; /* bitmap for allocating memory chunk */
};
extern struct gen_pool *gen_pool_create(int, int);
-extern int gen_pool_add(struct gen_pool *, unsigned long, size_t, int);
+extern phys_addr_t gen_pool_virt_to_phys(struct gen_pool *pool, unsigned long);
+extern int gen_pool_add_virt(struct gen_pool *, unsigned long, phys_addr_t,
+ size_t, int);
+/**
+ * gen_pool_add - add a new chunk of special memory to the pool
+ * @pool: pool to add new memory chunk to
+ * @addr: starting address of memory chunk to add to pool
+ * @size: size in bytes of the memory chunk to add to pool
+ * @nid: node id of the node the chunk structure and bitmap should be
+ * allocated on, or -1
+ *
+ * Add a new chunk of special memory to the specified pool.
+ *
+ * Returns 0 on success or a -ve errno on failure.
+ */
+static inline int gen_pool_add(struct gen_pool *pool, unsigned long addr,
+ size_t size, int nid)
+{
+ return gen_pool_add_virt(pool, addr, -1, size, nid);
+}
extern void gen_pool_destroy(struct gen_pool *);
extern unsigned long gen_pool_alloc(struct gen_pool *, size_t);
extern void gen_pool_free(struct gen_pool *, unsigned long, size_t);
+#endif /* __GENALLOC_H__ */
diff --git a/include/linux/genhd.h b/include/linux/genhd.h
index d764a42..b78956b 100644
--- a/include/linux/genhd.h
+++ b/include/linux/genhd.h
@@ -100,7 +100,6 @@
sector_t start_sect;
sector_t nr_sects;
sector_t alignment_offset;
- unsigned int discard_alignment;
struct device __dev;
struct kobject *holder_dir;
int policy, partno;
@@ -127,6 +126,7 @@
#define GENHD_FL_SUPPRESS_PARTITION_INFO 32
#define GENHD_FL_EXT_DEVT 64 /* allow extended devt */
#define GENHD_FL_NATIVE_CAPACITY 128
+#define GENHD_FL_BLOCK_EVENTS_ON_EXCL_WRITE 256
enum {
DISK_EVENT_MEDIA_CHANGE = 1 << 0, /* media changed */
diff --git a/include/linux/gfp.h b/include/linux/gfp.h
index 56d8fc8..cb40892 100644
--- a/include/linux/gfp.h
+++ b/include/linux/gfp.h
@@ -249,14 +249,7 @@
z = (GFP_ZONE_TABLE >> (bit * ZONES_SHIFT)) &
((1 << ZONES_SHIFT) - 1);
-
- if (__builtin_constant_p(bit))
- BUILD_BUG_ON((GFP_ZONE_BAD >> bit) & 1);
- else {
-#ifdef CONFIG_DEBUG_VM
- BUG_ON((GFP_ZONE_BAD >> bit) & 1);
-#endif
- }
+ VM_BUG_ON((GFP_ZONE_BAD >> bit) & 1);
return z;
}
diff --git a/include/linux/gpio_keys.h b/include/linux/gpio_keys.h
index dd1a56f..b5ca4b2 100644
--- a/include/linux/gpio_keys.h
+++ b/include/linux/gpio_keys.h
@@ -3,14 +3,15 @@
struct gpio_keys_button {
/* Configuration parameters */
- int code; /* input event code (KEY_*, SW_*) */
+ unsigned int code; /* input event code (KEY_*, SW_*) */
int gpio;
int active_low;
- char *desc;
- int type; /* input event type (EV_KEY, EV_SW) */
+ const char *desc;
+ unsigned int type; /* input event type (EV_KEY, EV_SW, EV_ABS) */
int wakeup; /* configure the button as a wake-up source */
int debounce_interval; /* debounce ticks interval in msecs */
bool can_disable;
+ int value; /* axis value for EV_ABS */
};
struct gpio_keys_platform_data {
@@ -21,6 +22,7 @@
unsigned int rep:1; /* enable input subsystem auto repeat */
int (*enable)(struct device *dev);
void (*disable)(struct device *dev);
+ const char *name; /* input device name */
};
#endif
diff --git a/include/linux/hrtimer.h b/include/linux/hrtimer.h
index 62f500c..51932e5 100644
--- a/include/linux/hrtimer.h
+++ b/include/linux/hrtimer.h
@@ -143,19 +143,18 @@
*/
struct hrtimer_clock_base {
struct hrtimer_cpu_base *cpu_base;
- clockid_t index;
+ int index;
+ clockid_t clockid;
struct timerqueue_head active;
ktime_t resolution;
ktime_t (*get_time)(void);
ktime_t softirq_time;
-#ifdef CONFIG_HIGH_RES_TIMERS
ktime_t offset;
-#endif
};
enum hrtimer_base_type {
- HRTIMER_BASE_REALTIME,
HRTIMER_BASE_MONOTONIC,
+ HRTIMER_BASE_REALTIME,
HRTIMER_BASE_BOOTTIME,
HRTIMER_MAX_CLOCK_BASES,
};
@@ -164,7 +163,7 @@
* struct hrtimer_cpu_base - the per cpu clock bases
* @lock: lock protecting the base and associated clock bases
* and timers
- * @clock_base: array of clock bases for this cpu
+ * @active_bases: Bitfield to mark bases with active timers
* @expires_next: absolute time of the next event which was scheduled
* via clock_set_next_event()
* @hres_active: State of high resolution mode
@@ -173,10 +172,11 @@
* @nr_retries: Total number of hrtimer interrupt retries
* @nr_hangs: Total number of hrtimer interrupt hangs
* @max_hang_time: Maximum time spent in hrtimer_interrupt
+ * @clock_base: array of clock bases for this cpu
*/
struct hrtimer_cpu_base {
raw_spinlock_t lock;
- struct hrtimer_clock_base clock_base[HRTIMER_MAX_CLOCK_BASES];
+ unsigned long active_bases;
#ifdef CONFIG_HIGH_RES_TIMERS
ktime_t expires_next;
int hres_active;
@@ -186,6 +186,7 @@
unsigned long nr_hangs;
ktime_t max_hang_time;
#endif
+ struct hrtimer_clock_base clock_base[HRTIMER_MAX_CLOCK_BASES];
};
static inline void hrtimer_set_expires(struct hrtimer *timer, ktime_t time)
@@ -256,8 +257,6 @@
#ifdef CONFIG_HIGH_RES_TIMERS
struct clock_event_device;
-extern void clock_was_set(void);
-extern void hres_timers_resume(void);
extern void hrtimer_interrupt(struct clock_event_device *dev);
/*
@@ -291,16 +290,8 @@
# define MONOTONIC_RES_NSEC LOW_RES_NSEC
# define KTIME_MONOTONIC_RES KTIME_LOW_RES
-/*
- * clock_was_set() is a NOP for non- high-resolution systems. The
- * time-sorted order guarantees that a timer does not expire early and
- * is expired in the next softirq when the clock was advanced.
- */
-static inline void clock_was_set(void) { }
static inline void hrtimer_peek_ahead_timers(void) { }
-static inline void hres_timers_resume(void) { }
-
/*
* In non high resolution mode the time reference is taken from
* the base softirq time variable.
@@ -316,10 +307,18 @@
}
#endif
+extern void clock_was_set(void);
+#ifdef CONFIG_TIMERFD
+extern void timerfd_clock_was_set(void);
+#else
+static inline void timerfd_clock_was_set(void) { }
+#endif
+extern void hrtimers_resume(void);
+
extern ktime_t ktime_get(void);
extern ktime_t ktime_get_real(void);
extern ktime_t ktime_get_boottime(void);
-
+extern ktime_t ktime_get_monotonic_offset(void);
DECLARE_PER_CPU(struct tick_device, tick_cpu_device);
diff --git a/include/linux/huge_mm.h b/include/linux/huge_mm.h
index 8847c8c..48c32eb 100644
--- a/include/linux/huge_mm.h
+++ b/include/linux/huge_mm.h
@@ -92,12 +92,8 @@
#define wait_split_huge_page(__anon_vma, __pmd) \
do { \
pmd_t *____pmd = (__pmd); \
- spin_unlock_wait(&(__anon_vma)->root->lock); \
- /* \
- * spin_unlock_wait() is just a loop in C and so the \
- * CPU can reorder anything around it. \
- */ \
- smp_mb(); \
+ anon_vma_lock(__anon_vma); \
+ anon_vma_unlock(__anon_vma); \
BUG_ON(pmd_trans_splitting(*____pmd) || \
pmd_trans_huge(*____pmd)); \
} while (0)
diff --git a/include/linux/i2c.h b/include/linux/i2c.h
index f1e3ff5..a6c652e 100644
--- a/include/linux/i2c.h
+++ b/include/linux/i2c.h
@@ -409,7 +409,7 @@
/* i2c adapter classes (bitmask) */
#define I2C_CLASS_HWMON (1<<0) /* lm_sensors, ... */
#define I2C_CLASS_DDC (1<<3) /* DDC bus on graphics adapters */
-#define I2C_CLASS_SPD (1<<7) /* SPD EEPROMs and similar */
+#define I2C_CLASS_SPD (1<<7) /* Memory modules */
/* Internal numbers to terminate lists */
#define I2C_CLIENT_END 0xfffeU
diff --git a/include/linux/i2c/i2c-sh_mobile.h b/include/linux/i2c/i2c-sh_mobile.h
new file mode 100644
index 0000000..beda708
--- /dev/null
+++ b/include/linux/i2c/i2c-sh_mobile.h
@@ -0,0 +1,10 @@
+#ifndef __I2C_SH_MOBILE_H__
+#define __I2C_SH_MOBILE_H__
+
+#include <linux/platform_device.h>
+
+struct i2c_sh_mobile_platform_data {
+ unsigned long bus_speed;
+};
+
+#endif /* __I2C_SH_MOBILE_H__ */
diff --git a/include/linux/i2c/mpr121_touchkey.h b/include/linux/i2c/mpr121_touchkey.h
new file mode 100644
index 0000000..f0bcc38
--- /dev/null
+++ b/include/linux/i2c/mpr121_touchkey.h
@@ -0,0 +1,20 @@
+/* Header file for Freescale MPR121 Capacitive Touch Sensor */
+
+#ifndef _MPR121_TOUCHKEY_H
+#define _MPR121_TOUCHKEY_H
+
+/**
+ * struct mpr121_platform_data - platform data for mpr121 sensor
+ * @keymap: pointer to array of KEY_* values representing keymap
+ * @keymap_size: size of the keymap
+ * @wakeup: configure the button as a wake-up source
+ * @vdd_uv: VDD voltage in uV
+ */
+struct mpr121_platform_data {
+ const unsigned short *keymap;
+ unsigned int keymap_size;
+ bool wakeup;
+ int vdd_uv;
+};
+
+#endif /* _MPR121_TOUCHKEY_H */
diff --git a/include/linux/i2c/tsc2007.h b/include/linux/i2c/tsc2007.h
index c6361fb..591427a 100644
--- a/include/linux/i2c/tsc2007.h
+++ b/include/linux/i2c/tsc2007.h
@@ -6,6 +6,13 @@
struct tsc2007_platform_data {
u16 model; /* 2007. */
u16 x_plate_ohms;
+ u16 max_rt; /* max. resistance above which samples are ignored */
+ unsigned long poll_delay; /* delay (in ms) after pen-down event
+ before polling starts */
+ unsigned long poll_period; /* time (in ms) between samples */
+ int fuzzx; /* fuzz factor for X, Y and pressure axes */
+ int fuzzy;
+ int fuzzz;
int (*get_pendown_state)(void);
void (*clear_penirq)(void); /* If needed, clear 2nd level
diff --git a/include/linux/init_task.h b/include/linux/init_task.h
index 689496b..bafc58c 100644
--- a/include/linux/init_task.h
+++ b/include/linux/init_task.h
@@ -83,13 +83,6 @@
#define INIT_IDS
#endif
-/*
- * Because of the reduced scope of CAP_SETPCAP when filesystem
- * capabilities are in effect, it is safe to allow CAP_SETPCAP to
- * be available in the default configuration.
- */
-# define CAP_INIT_BSET CAP_FULL_SET
-
#ifdef CONFIG_RCU_BOOST
#define INIT_TASK_RCU_BOOST() \
.rcu_boost_mutex = NULL,
diff --git a/include/linux/input/ad714x.h b/include/linux/input/ad714x.h
index 0cbe5e8..d388d85 100644
--- a/include/linux/input/ad714x.h
+++ b/include/linux/input/ad714x.h
@@ -6,7 +6,7 @@
* The platform_data for the device's "struct device" holds this
* information.
*
- * Copyright 2009 Analog Devices Inc.
+ * Copyright 2009-2011 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
@@ -58,6 +58,7 @@
struct ad714x_button_plat *button;
unsigned short stage_cfg_reg[STAGE_NUM][STAGE_CFGREG_NUM];
unsigned short sys_cfg_reg[SYS_CFGREG_NUM];
+ unsigned long irqflags;
};
#endif
diff --git a/include/linux/input/adp5589.h b/include/linux/input/adp5589.h
new file mode 100644
index 0000000..ef792ec
--- /dev/null
+++ b/include/linux/input/adp5589.h
@@ -0,0 +1,213 @@
+/*
+ * Analog Devices ADP5589 I/O Expander and QWERTY Keypad Controller
+ *
+ * Copyright 2010-2011 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2.
+ */
+
+#ifndef _ADP5589_H
+#define _ADP5589_H
+
+#define ADP5589_ID 0x00
+#define ADP5589_INT_STATUS 0x01
+#define ADP5589_STATUS 0x02
+#define ADP5589_FIFO_1 0x03
+#define ADP5589_FIFO_2 0x04
+#define ADP5589_FIFO_3 0x05
+#define ADP5589_FIFO_4 0x06
+#define ADP5589_FIFO_5 0x07
+#define ADP5589_FIFO_6 0x08
+#define ADP5589_FIFO_7 0x09
+#define ADP5589_FIFO_8 0x0A
+#define ADP5589_FIFO_9 0x0B
+#define ADP5589_FIFO_10 0x0C
+#define ADP5589_FIFO_11 0x0D
+#define ADP5589_FIFO_12 0x0E
+#define ADP5589_FIFO_13 0x0F
+#define ADP5589_FIFO_14 0x10
+#define ADP5589_FIFO_15 0x11
+#define ADP5589_FIFO_16 0x12
+#define ADP5589_GPI_INT_STAT_A 0x13
+#define ADP5589_GPI_INT_STAT_B 0x14
+#define ADP5589_GPI_INT_STAT_C 0x15
+#define ADP5589_GPI_STATUS_A 0x16
+#define ADP5589_GPI_STATUS_B 0x17
+#define ADP5589_GPI_STATUS_C 0x18
+#define ADP5589_RPULL_CONFIG_A 0x19
+#define ADP5589_RPULL_CONFIG_B 0x1A
+#define ADP5589_RPULL_CONFIG_C 0x1B
+#define ADP5589_RPULL_CONFIG_D 0x1C
+#define ADP5589_RPULL_CONFIG_E 0x1D
+#define ADP5589_GPI_INT_LEVEL_A 0x1E
+#define ADP5589_GPI_INT_LEVEL_B 0x1F
+#define ADP5589_GPI_INT_LEVEL_C 0x20
+#define ADP5589_GPI_EVENT_EN_A 0x21
+#define ADP5589_GPI_EVENT_EN_B 0x22
+#define ADP5589_GPI_EVENT_EN_C 0x23
+#define ADP5589_GPI_INTERRUPT_EN_A 0x24
+#define ADP5589_GPI_INTERRUPT_EN_B 0x25
+#define ADP5589_GPI_INTERRUPT_EN_C 0x26
+#define ADP5589_DEBOUNCE_DIS_A 0x27
+#define ADP5589_DEBOUNCE_DIS_B 0x28
+#define ADP5589_DEBOUNCE_DIS_C 0x29
+#define ADP5589_GPO_DATA_OUT_A 0x2A
+#define ADP5589_GPO_DATA_OUT_B 0x2B
+#define ADP5589_GPO_DATA_OUT_C 0x2C
+#define ADP5589_GPO_OUT_MODE_A 0x2D
+#define ADP5589_GPO_OUT_MODE_B 0x2E
+#define ADP5589_GPO_OUT_MODE_C 0x2F
+#define ADP5589_GPIO_DIRECTION_A 0x30
+#define ADP5589_GPIO_DIRECTION_B 0x31
+#define ADP5589_GPIO_DIRECTION_C 0x32
+#define ADP5589_UNLOCK1 0x33
+#define ADP5589_UNLOCK2 0x34
+#define ADP5589_EXT_LOCK_EVENT 0x35
+#define ADP5589_UNLOCK_TIMERS 0x36
+#define ADP5589_LOCK_CFG 0x37
+#define ADP5589_RESET1_EVENT_A 0x38
+#define ADP5589_RESET1_EVENT_B 0x39
+#define ADP5589_RESET1_EVENT_C 0x3A
+#define ADP5589_RESET2_EVENT_A 0x3B
+#define ADP5589_RESET2_EVENT_B 0x3C
+#define ADP5589_RESET_CFG 0x3D
+#define ADP5589_PWM_OFFT_LOW 0x3E
+#define ADP5589_PWM_OFFT_HIGH 0x3F
+#define ADP5589_PWM_ONT_LOW 0x40
+#define ADP5589_PWM_ONT_HIGH 0x41
+#define ADP5589_PWM_CFG 0x42
+#define ADP5589_CLOCK_DIV_CFG 0x43
+#define ADP5589_LOGIC_1_CFG 0x44
+#define ADP5589_LOGIC_2_CFG 0x45
+#define ADP5589_LOGIC_FF_CFG 0x46
+#define ADP5589_LOGIC_INT_EVENT_EN 0x47
+#define ADP5589_POLL_PTIME_CFG 0x48
+#define ADP5589_PIN_CONFIG_A 0x49
+#define ADP5589_PIN_CONFIG_B 0x4A
+#define ADP5589_PIN_CONFIG_C 0x4B
+#define ADP5589_PIN_CONFIG_D 0x4C
+#define ADP5589_GENERAL_CFG 0x4D
+#define ADP5589_INT_EN 0x4E
+
+#define ADP5589_DEVICE_ID_MASK 0xF
+
+/* Put one of these structures in i2c_board_info platform_data */
+
+#define ADP5589_KEYMAPSIZE 88
+
+#define ADP5589_GPI_PIN_ROW0 97
+#define ADP5589_GPI_PIN_ROW1 98
+#define ADP5589_GPI_PIN_ROW2 99
+#define ADP5589_GPI_PIN_ROW3 100
+#define ADP5589_GPI_PIN_ROW4 101
+#define ADP5589_GPI_PIN_ROW5 102
+#define ADP5589_GPI_PIN_ROW6 103
+#define ADP5589_GPI_PIN_ROW7 104
+#define ADP5589_GPI_PIN_COL0 105
+#define ADP5589_GPI_PIN_COL1 106
+#define ADP5589_GPI_PIN_COL2 107
+#define ADP5589_GPI_PIN_COL3 108
+#define ADP5589_GPI_PIN_COL4 109
+#define ADP5589_GPI_PIN_COL5 110
+#define ADP5589_GPI_PIN_COL6 111
+#define ADP5589_GPI_PIN_COL7 112
+#define ADP5589_GPI_PIN_COL8 113
+#define ADP5589_GPI_PIN_COL9 114
+#define ADP5589_GPI_PIN_COL10 115
+#define GPI_LOGIC1 116
+#define GPI_LOGIC2 117
+
+#define ADP5589_GPI_PIN_ROW_BASE ADP5589_GPI_PIN_ROW0
+#define ADP5589_GPI_PIN_ROW_END ADP5589_GPI_PIN_ROW7
+#define ADP5589_GPI_PIN_COL_BASE ADP5589_GPI_PIN_COL0
+#define ADP5589_GPI_PIN_COL_END ADP5589_GPI_PIN_COL10
+
+#define ADP5589_GPI_PIN_BASE ADP5589_GPI_PIN_ROW_BASE
+#define ADP5589_GPI_PIN_END ADP5589_GPI_PIN_COL_END
+
+#define ADP5589_GPIMAPSIZE_MAX (ADP5589_GPI_PIN_END - ADP5589_GPI_PIN_BASE + 1)
+
+struct adp5589_gpi_map {
+ unsigned short pin;
+ unsigned short sw_evt;
+};
+
+/* scan_cycle_time */
+#define ADP5589_SCAN_CYCLE_10ms 0
+#define ADP5589_SCAN_CYCLE_20ms 1
+#define ADP5589_SCAN_CYCLE_30ms 2
+#define ADP5589_SCAN_CYCLE_40ms 3
+
+/* RESET_CFG */
+#define RESET_PULSE_WIDTH_500us 0
+#define RESET_PULSE_WIDTH_1ms 1
+#define RESET_PULSE_WIDTH_2ms 2
+#define RESET_PULSE_WIDTH_10ms 3
+
+#define RESET_TRIG_TIME_0ms (0 << 2)
+#define RESET_TRIG_TIME_1000ms (1 << 2)
+#define RESET_TRIG_TIME_1500ms (2 << 2)
+#define RESET_TRIG_TIME_2000ms (3 << 2)
+#define RESET_TRIG_TIME_2500ms (4 << 2)
+#define RESET_TRIG_TIME_3000ms (5 << 2)
+#define RESET_TRIG_TIME_3500ms (6 << 2)
+#define RESET_TRIG_TIME_4000ms (7 << 2)
+
+#define RESET_PASSTHRU_EN (1 << 5)
+#define RESET1_POL_HIGH (1 << 6)
+#define RESET1_POL_LOW (0 << 6)
+#define RESET2_POL_HIGH (1 << 7)
+#define RESET2_POL_LOW (0 << 7)
+
+/* Mask Bits:
+ * C C C C C C C C C C C | R R R R R R R R
+ * 1 9 8 7 6 5 4 3 2 1 0 | 7 6 5 4 3 2 1 0
+ * 0
+ * ---------------- BIT ------------------
+ * 1 1 1 1 1 1 1 1 1 0 0 | 0 0 0 0 0 0 0 0
+ * 8 7 6 5 4 3 2 1 0 9 8 | 7 6 5 4 3 2 1 0
+ */
+
+#define ADP_ROW(x) (1 << (x))
+#define ADP_COL(x) (1 << (x + 8))
+
+struct adp5589_kpad_platform_data {
+ unsigned keypad_en_mask; /* Keypad (Rows/Columns) enable mask */
+ const unsigned short *keymap; /* Pointer to keymap */
+ unsigned short keymapsize; /* Keymap size */
+ bool repeat; /* Enable key repeat */
+ bool en_keylock; /* Enable key lock feature */
+ unsigned char unlock_key1; /* Unlock Key 1 */
+ unsigned char unlock_key2; /* Unlock Key 2 */
+ unsigned char unlock_timer; /* Time in seconds [0..7] between the two unlock keys 0=disable */
+ unsigned char scan_cycle_time; /* Time between consecutive scan cycles */
+ unsigned char reset_cfg; /* Reset config */
+ unsigned short reset1_key_1; /* Reset Key 1 */
+ unsigned short reset1_key_2; /* Reset Key 2 */
+ unsigned short reset1_key_3; /* Reset Key 3 */
+ unsigned short reset2_key_1; /* Reset Key 1 */
+ unsigned short reset2_key_2; /* Reset Key 2 */
+ unsigned debounce_dis_mask; /* Disable debounce mask */
+ unsigned pull_dis_mask; /* Disable all pull resistors mask */
+ unsigned pullup_en_100k; /* Pull-Up 100k Enable Mask */
+ unsigned pullup_en_300k; /* Pull-Up 300k Enable Mask */
+ unsigned pulldown_en_300k; /* Pull-Down 300k Enable Mask */
+ const struct adp5589_gpi_map *gpimap;
+ unsigned short gpimapsize;
+ const struct adp5589_gpio_platform_data *gpio_data;
+};
+
+struct i2c_client; /* forward declaration */
+
+struct adp5589_gpio_platform_data {
+ int gpio_start; /* GPIO Chip base # */
+ int (*setup)(struct i2c_client *client,
+ int gpio, unsigned ngpio,
+ void *context);
+ int (*teardown)(struct i2c_client *client,
+ int gpio, unsigned ngpio,
+ void *context);
+ void *context;
+};
+
+#endif
diff --git a/include/linux/kernel.h b/include/linux/kernel.h
index f37ba71..fb0e732 100644
--- a/include/linux/kernel.h
+++ b/include/linux/kernel.h
@@ -248,6 +248,37 @@
int __must_check kstrtou8(const char *s, unsigned int base, u8 *res);
int __must_check kstrtos8(const char *s, unsigned int base, s8 *res);
+int __must_check kstrtoull_from_user(const char __user *s, size_t count, unsigned int base, unsigned long long *res);
+int __must_check kstrtoll_from_user(const char __user *s, size_t count, unsigned int base, long long *res);
+int __must_check kstrtoul_from_user(const char __user *s, size_t count, unsigned int base, unsigned long *res);
+int __must_check kstrtol_from_user(const char __user *s, size_t count, unsigned int base, long *res);
+int __must_check kstrtouint_from_user(const char __user *s, size_t count, unsigned int base, unsigned int *res);
+int __must_check kstrtoint_from_user(const char __user *s, size_t count, unsigned int base, int *res);
+int __must_check kstrtou16_from_user(const char __user *s, size_t count, unsigned int base, u16 *res);
+int __must_check kstrtos16_from_user(const char __user *s, size_t count, unsigned int base, s16 *res);
+int __must_check kstrtou8_from_user(const char __user *s, size_t count, unsigned int base, u8 *res);
+int __must_check kstrtos8_from_user(const char __user *s, size_t count, unsigned int base, s8 *res);
+
+static inline int __must_check kstrtou64_from_user(const char __user *s, size_t count, unsigned int base, u64 *res)
+{
+ return kstrtoull_from_user(s, count, base, res);
+}
+
+static inline int __must_check kstrtos64_from_user(const char __user *s, size_t count, unsigned int base, s64 *res)
+{
+ return kstrtoll_from_user(s, count, base, res);
+}
+
+static inline int __must_check kstrtou32_from_user(const char __user *s, size_t count, unsigned int base, u32 *res)
+{
+ return kstrtouint_from_user(s, count, base, res);
+}
+
+static inline int __must_check kstrtos32_from_user(const char __user *s, size_t count, unsigned int base, s32 *res)
+{
+ return kstrtoint_from_user(s, count, base, res);
+}
+
extern unsigned long simple_strtoul(const char *,char **,unsigned int);
extern long simple_strtol(const char *,char **,unsigned int);
extern unsigned long long simple_strtoull(const char *,char **,unsigned int);
@@ -638,6 +669,13 @@
char _f[20-2*sizeof(long)-sizeof(int)]; /* Padding: libc5 uses this.. */
};
+#ifdef __CHECKER__
+#define BUILD_BUG_ON_NOT_POWER_OF_2(n)
+#define BUILD_BUG_ON_ZERO(e)
+#define BUILD_BUG_ON_NULL(e)
+#define BUILD_BUG_ON(condition)
+#else /* __CHECKER__ */
+
/* Force a compilation error if a constant expression is not a power of 2 */
#define BUILD_BUG_ON_NOT_POWER_OF_2(n) \
BUILD_BUG_ON((n) == 0 || (((n) & ((n) - 1)) != 0))
@@ -674,6 +712,7 @@
if (condition) __build_bug_on_failed = 1; \
} while(0)
#endif
+#endif /* __CHECKER__ */
/* Trap pasters of __FUNCTION__ at compile-time */
#define __FUNCTION__ (__func__)
diff --git a/include/linux/key.h b/include/linux/key.h
index b2bb017..ef19b99 100644
--- a/include/linux/key.h
+++ b/include/linux/key.h
@@ -276,6 +276,19 @@
return key ? key->serial : 0;
}
+/**
+ * key_is_instantiated - Determine if a key has been positively instantiated
+ * @key: The key to check.
+ *
+ * Return true if the specified key has been positively instantiated, false
+ * otherwise.
+ */
+static inline bool key_is_instantiated(const struct key *key)
+{
+ return test_bit(KEY_FLAG_INSTANTIATED, &key->flags) &&
+ !test_bit(KEY_FLAG_NEGATIVE, &key->flags);
+}
+
#define rcu_dereference_key(KEY) \
(rcu_dereference_protected((KEY)->payload.rcudata, \
rwsem_is_locked(&((struct key *)(KEY))->sem)))
diff --git a/include/linux/kmod.h b/include/linux/kmod.h
index 3102318..d4a5c84 100644
--- a/include/linux/kmod.h
+++ b/include/linux/kmod.h
@@ -24,6 +24,7 @@
#include <linux/errno.h>
#include <linux/compiler.h>
#include <linux/workqueue.h>
+#include <linux/sysctl.h>
#define KMOD_PATH_LEN 256
@@ -109,6 +110,8 @@
NULL, NULL, NULL);
}
+extern struct ctl_table usermodehelper_table[];
+
extern void usermodehelper_init(void);
extern int usermodehelper_disable(void);
diff --git a/include/linux/kvm_host.h b/include/linux/kvm_host.h
index b9c3299..31ebb59 100644
--- a/include/linux/kvm_host.h
+++ b/include/linux/kvm_host.h
@@ -517,6 +517,7 @@
struct kvm *kvm;
spinlock_t intx_lock;
char irq_name[32];
+ struct pci_saved_state *pci_saved_state;
};
struct kvm_irq_mask_notifier {
diff --git a/include/linux/leds-pca9532.h b/include/linux/leds-pca9532.h
index f158eb1..b8d6fff 100644
--- a/include/linux/leds-pca9532.h
+++ b/include/linux/leds-pca9532.h
@@ -25,7 +25,7 @@
};
enum pca9532_type { PCA9532_TYPE_NONE, PCA9532_TYPE_LED,
- PCA9532_TYPE_N2100_BEEP };
+ PCA9532_TYPE_N2100_BEEP, PCA9532_TYPE_GPIO };
struct pca9532_led {
u8 id;
@@ -41,6 +41,7 @@
struct pca9532_led leds[16];
u8 pwm[2];
u8 psc[2];
+ int gpio_base;
};
#endif /* __LINUX_PCA9532_H */
diff --git a/include/linux/leds.h b/include/linux/leds.h
index 61e0340..5884def 100644
--- a/include/linux/leds.h
+++ b/include/linux/leds.h
@@ -207,5 +207,7 @@
unsigned long *delay_off);
};
+struct platform_device *gpio_led_register_device(
+ int id, const struct gpio_led_platform_data *pdata);
#endif /* __LINUX_LEDS_H_INCLUDED */
diff --git a/include/linux/linkage.h b/include/linux/linkage.h
index 7135ebc..3f46aed 100644
--- a/include/linux/linkage.h
+++ b/include/linux/linkage.h
@@ -14,10 +14,6 @@
#define asmlinkage CPP_ASMLINKAGE
#endif
-#ifndef asmregparm
-# define asmregparm
-#endif
-
#define __page_aligned_data __section(.data..page_aligned) __aligned(PAGE_SIZE)
#define __page_aligned_bss __section(.bss..page_aligned) __aligned(PAGE_SIZE)
diff --git a/include/linux/lockdep.h b/include/linux/lockdep.h
index 4aef1dd..ef820a3 100644
--- a/include/linux/lockdep.h
+++ b/include/linux/lockdep.h
@@ -487,12 +487,15 @@
#ifdef CONFIG_DEBUG_LOCK_ALLOC
# ifdef CONFIG_PROVE_LOCKING
# define mutex_acquire(l, s, t, i) lock_acquire(l, s, t, 0, 2, NULL, i)
+# define mutex_acquire_nest(l, s, t, n, i) lock_acquire(l, s, t, 0, 2, n, i)
# else
# define mutex_acquire(l, s, t, i) lock_acquire(l, s, t, 0, 1, NULL, i)
+# define mutex_acquire_nest(l, s, t, n, i) lock_acquire(l, s, t, 0, 1, n, i)
# endif
# define mutex_release(l, n, i) lock_release(l, n, i)
#else
# define mutex_acquire(l, s, t, i) do { } while (0)
+# define mutex_acquire_nest(l, s, t, n, i) do { } while (0)
# define mutex_release(l, n, i) do { } while (0)
#endif
diff --git a/include/linux/lru_cache.h b/include/linux/lru_cache.h
index 6a4fab7..7a71ffa 100644
--- a/include/linux/lru_cache.h
+++ b/include/linux/lru_cache.h
@@ -139,9 +139,9 @@
* .list is on one of three lists:
* in_use: currently in use (refcnt > 0, lc_number != LC_FREE)
* lru: unused but ready to be reused or recycled
- * (ts_refcnt == 0, lc_number != LC_FREE),
+ * (lc_refcnt == 0, lc_number != LC_FREE),
* free: unused but ready to be recycled
- * (ts_refcnt == 0, lc_number == LC_FREE),
+ * (lc_refcnt == 0, lc_number == LC_FREE),
*
* an element is said to be "in the active set",
* if either on "in_use" or "lru", i.e. lc_number != LC_FREE.
@@ -160,8 +160,8 @@
struct hlist_node colision;
struct list_head list; /* LRU list or free list */
unsigned refcnt;
- /* back "pointer" into ts_cache->element[index],
- * for paranoia, and for "ts_element_to_index" */
+ /* back "pointer" into lc_cache->element[index],
+ * for paranoia, and for "lc_element_to_index" */
unsigned lc_index;
/* if we want to track a larger set of objects,
* it needs to become arch independend u64 */
@@ -190,8 +190,8 @@
/* Arbitrary limit on maximum tracked objects. Practical limit is much
* lower due to allocation failures, probably. For typical use cases,
* nr_elements should be a few thousand at most.
- * This also limits the maximum value of ts_element.ts_index, allowing the
- * 8 high bits of .ts_index to be overloaded with flags in the future. */
+ * This also limits the maximum value of lc_element.lc_index, allowing the
+ * 8 high bits of .lc_index to be overloaded with flags in the future. */
#define LC_MAX_ACTIVE (1<<24)
/* statistics */
diff --git a/include/linux/lsm_audit.h b/include/linux/lsm_audit.h
index 112a550..88e78de 100644
--- a/include/linux/lsm_audit.h
+++ b/include/linux/lsm_audit.h
@@ -27,7 +27,7 @@
/* Auxiliary data to use in generating the audit record. */
struct common_audit_data {
char type;
-#define LSM_AUDIT_DATA_FS 1
+#define LSM_AUDIT_DATA_PATH 1
#define LSM_AUDIT_DATA_NET 2
#define LSM_AUDIT_DATA_CAP 3
#define LSM_AUDIT_DATA_IPC 4
@@ -35,12 +35,13 @@
#define LSM_AUDIT_DATA_KEY 6
#define LSM_AUDIT_DATA_NONE 7
#define LSM_AUDIT_DATA_KMOD 8
+#define LSM_AUDIT_DATA_INODE 9
+#define LSM_AUDIT_DATA_DENTRY 10
struct task_struct *tsk;
union {
- struct {
- struct path path;
- struct inode *inode;
- } fs;
+ struct path path;
+ struct dentry *dentry;
+ struct inode *inode;
struct {
int netif;
struct sock *sk;
diff --git a/include/linux/memblock.h b/include/linux/memblock.h
index 62a10c2..7525e38 100644
--- a/include/linux/memblock.h
+++ b/include/linux/memblock.h
@@ -2,6 +2,8 @@
#define _LINUX_MEMBLOCK_H
#ifdef __KERNEL__
+#define MEMBLOCK_ERROR 0
+
#ifdef CONFIG_HAVE_MEMBLOCK
/*
* Logical memory blocks.
@@ -20,7 +22,6 @@
#include <asm/memblock.h>
#define INIT_MEMBLOCK_REGIONS 128
-#define MEMBLOCK_ERROR 0
struct memblock_region {
phys_addr_t base;
@@ -160,6 +161,12 @@
#define __initdata_memblock
#endif
+#else
+static inline phys_addr_t memblock_alloc(phys_addr_t size, phys_addr_t align)
+{
+ return MEMBLOCK_ERROR;
+}
+
#endif /* CONFIG_HAVE_MEMBLOCK */
#endif /* __KERNEL__ */
diff --git a/include/linux/mempolicy.h b/include/linux/mempolicy.h
index 31ac26c..7978eec 100644
--- a/include/linux/mempolicy.h
+++ b/include/linux/mempolicy.h
@@ -199,6 +199,9 @@
struct mempolicy *mpol_shared_policy_lookup(struct shared_policy *sp,
unsigned long idx);
+struct mempolicy *get_vma_policy(struct task_struct *tsk,
+ struct vm_area_struct *vma, unsigned long addr);
+
extern void numa_default_policy(void);
extern void numa_policy_init(void);
extern void mpol_rebind_task(struct task_struct *tsk, const nodemask_t *new,
@@ -228,10 +231,10 @@
#ifdef CONFIG_TMPFS
extern int mpol_parse_str(char *str, struct mempolicy **mpol, int no_context);
+#endif
extern int mpol_to_str(char *buffer, int maxlen, struct mempolicy *pol,
int no_context);
-#endif
/* Check if a vma is migratable */
static inline int vma_migratable(struct vm_area_struct *vma)
@@ -368,13 +371,13 @@
{
return 1; /* error */
}
+#endif
static inline int mpol_to_str(char *buffer, int maxlen, struct mempolicy *pol,
int no_context)
{
return 0;
}
-#endif
#endif /* CONFIG_NUMA */
#endif /* __KERNEL__ */
diff --git a/include/linux/mfd/db5500-prcmu.h b/include/linux/mfd/db5500-prcmu.h
new file mode 100644
index 0000000..f097798
--- /dev/null
+++ b/include/linux/mfd/db5500-prcmu.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * License Terms: GNU General Public License v2
+ *
+ * U5500 PRCMU API.
+ */
+#ifndef __MACH_PRCMU_U5500_H
+#define __MACH_PRCMU_U5500_H
+
+#ifdef CONFIG_UX500_SOC_DB5500
+
+void db5500_prcmu_early_init(void);
+
+int db5500_prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
+int db5500_prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
+
+#else /* !CONFIG_UX500_SOC_DB5500 */
+
+static inline void db5500_prcmu_early_init(void)
+{
+}
+
+static inline int db5500_prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
+{
+ return -ENOSYS;
+}
+
+static inline int db5500_prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
+{
+ return -ENOSYS;
+}
+
+#endif /* CONFIG_UX500_SOC_DB5500 */
+
+static inline int db5500_prcmu_config_abb_event_readout(u32 abb_events)
+{
+#ifdef CONFIG_MACH_U5500_SIMULATOR
+ return 0;
+#else
+ return -1;
+#endif
+}
+
+#endif /* __MACH_PRCMU_U5500_H */
diff --git a/include/linux/mfd/db8500-prcmu.h b/include/linux/mfd/db8500-prcmu.h
new file mode 100644
index 0000000..917dbcab
--- /dev/null
+++ b/include/linux/mfd/db8500-prcmu.h
@@ -0,0 +1,978 @@
+/*
+ * Copyright (C) STMicroelectronics 2009
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * License Terms: GNU General Public License v2
+ * Author: Kumar Sanghvi <kumar.sanghvi@stericsson.com>
+ *
+ * PRCMU f/w APIs
+ */
+#ifndef __MFD_DB8500_PRCMU_H
+#define __MFD_DB8500_PRCMU_H
+
+#include <linux/interrupt.h>
+#include <linux/notifier.h>
+
+/* This portion previously known as <mach/prcmu-fw-defs_v1.h> */
+
+/**
+ * enum state - ON/OFF state definition
+ * @OFF: State is ON
+ * @ON: State is OFF
+ *
+ */
+enum state {
+ OFF = 0x0,
+ ON = 0x1,
+};
+
+/**
+ * enum ret_state - general purpose On/Off/Retention states
+ *
+ */
+enum ret_state {
+ OFFST = 0,
+ ONST = 1,
+ RETST = 2
+};
+
+/**
+ * enum clk_arm - ARM Cortex A9 clock schemes
+ * @A9_OFF:
+ * @A9_BOOT:
+ * @A9_OPPT1:
+ * @A9_OPPT2:
+ * @A9_EXTCLK:
+ */
+enum clk_arm {
+ A9_OFF,
+ A9_BOOT,
+ A9_OPPT1,
+ A9_OPPT2,
+ A9_EXTCLK
+};
+
+/**
+ * enum clk_gen - GEN#0/GEN#1 clock schemes
+ * @GEN_OFF:
+ * @GEN_BOOT:
+ * @GEN_OPPT1:
+ */
+enum clk_gen {
+ GEN_OFF,
+ GEN_BOOT,
+ GEN_OPPT1,
+};
+
+/* some information between arm and xp70 */
+
+/**
+ * enum romcode_write - Romcode message written by A9 AND read by XP70
+ * @RDY_2_DS: Value set when ApDeepSleep state can be executed by XP70
+ * @RDY_2_XP70_RST: Value set when 0x0F has been successfully polled by the
+ * romcode. The xp70 will go into self-reset
+ */
+enum romcode_write {
+ RDY_2_DS = 0x09,
+ RDY_2_XP70_RST = 0x10
+};
+
+/**
+ * enum romcode_read - Romcode message written by XP70 and read by A9
+ * @INIT: Init value when romcode field is not used
+ * @FS_2_DS: Value set when power state is going from ApExecute to
+ * ApDeepSleep
+ * @END_DS: Value set when ApDeepSleep power state is reached coming from
+ * ApExecute state
+ * @DS_TO_FS: Value set when power state is going from ApDeepSleep to
+ * ApExecute
+ * @END_FS: Value set when ApExecute power state is reached coming from
+ * ApDeepSleep state
+ * @SWR: Value set when power state is going to ApReset
+ * @END_SWR: Value set when the xp70 finished executing ApReset actions and
+ * waits for romcode acknowledgment to go to self-reset
+ */
+enum romcode_read {
+ INIT = 0x00,
+ FS_2_DS = 0x0A,
+ END_DS = 0x0B,
+ DS_TO_FS = 0x0C,
+ END_FS = 0x0D,
+ SWR = 0x0E,
+ END_SWR = 0x0F
+};
+
+/**
+ * enum ap_pwrst - current power states defined in PRCMU firmware
+ * @NO_PWRST: Current power state init
+ * @AP_BOOT: Current power state is apBoot
+ * @AP_EXECUTE: Current power state is apExecute
+ * @AP_DEEP_SLEEP: Current power state is apDeepSleep
+ * @AP_SLEEP: Current power state is apSleep
+ * @AP_IDLE: Current power state is apIdle
+ * @AP_RESET: Current power state is apReset
+ */
+enum ap_pwrst {
+ NO_PWRST = 0x00,
+ AP_BOOT = 0x01,
+ AP_EXECUTE = 0x02,
+ AP_DEEP_SLEEP = 0x03,
+ AP_SLEEP = 0x04,
+ AP_IDLE = 0x05,
+ AP_RESET = 0x06
+};
+
+/**
+ * enum ap_pwrst_trans - Transition states defined in PRCMU firmware
+ * @NO_TRANSITION: No power state transition
+ * @APEXECUTE_TO_APSLEEP: Power state transition from ApExecute to ApSleep
+ * @APIDLE_TO_APSLEEP: Power state transition from ApIdle to ApSleep
+ * @APBOOT_TO_APEXECUTE: Power state transition from ApBoot to ApExecute
+ * @APEXECUTE_TO_APDEEPSLEEP: Power state transition from ApExecute to
+ * ApDeepSleep
+ * @APEXECUTE_TO_APIDLE: Power state transition from ApExecute to ApIdle
+ */
+enum ap_pwrst_trans {
+ NO_TRANSITION = 0x00,
+ APEXECUTE_TO_APSLEEP = 0x01,
+ APIDLE_TO_APSLEEP = 0x02, /* To be removed */
+ PRCMU_AP_SLEEP = 0x01,
+ APBOOT_TO_APEXECUTE = 0x03,
+ APEXECUTE_TO_APDEEPSLEEP = 0x04, /* To be removed */
+ PRCMU_AP_DEEP_SLEEP = 0x04,
+ APEXECUTE_TO_APIDLE = 0x05, /* To be removed */
+ PRCMU_AP_IDLE = 0x05,
+ PRCMU_AP_DEEP_IDLE = 0x07,
+};
+
+/**
+ * enum ddr_pwrst - DDR power states definition
+ * @DDR_PWR_STATE_UNCHANGED: SDRAM and DDR controller state is unchanged
+ * @DDR_PWR_STATE_ON:
+ * @DDR_PWR_STATE_OFFLOWLAT:
+ * @DDR_PWR_STATE_OFFHIGHLAT:
+ */
+enum ddr_pwrst {
+ DDR_PWR_STATE_UNCHANGED = 0x00,
+ DDR_PWR_STATE_ON = 0x01,
+ DDR_PWR_STATE_OFFLOWLAT = 0x02,
+ DDR_PWR_STATE_OFFHIGHLAT = 0x03
+};
+
+/**
+ * enum arm_opp - ARM OPP states definition
+ * @ARM_OPP_INIT:
+ * @ARM_NO_CHANGE: The ARM operating point is unchanged
+ * @ARM_100_OPP: The new ARM operating point is arm100opp
+ * @ARM_50_OPP: The new ARM operating point is arm50opp
+ * @ARM_MAX_OPP: Operating point is "max" (more than 100)
+ * @ARM_MAX_FREQ100OPP: Set max opp if available, else 100
+ * @ARM_EXTCLK: The new ARM operating point is armExtClk
+ */
+enum arm_opp {
+ ARM_OPP_INIT = 0x00,
+ ARM_NO_CHANGE = 0x01,
+ ARM_100_OPP = 0x02,
+ ARM_50_OPP = 0x03,
+ ARM_MAX_OPP = 0x04,
+ ARM_MAX_FREQ100OPP = 0x05,
+ ARM_EXTCLK = 0x07
+};
+
+/**
+ * enum ape_opp - APE OPP states definition
+ * @APE_OPP_INIT:
+ * @APE_NO_CHANGE: The APE operating point is unchanged
+ * @APE_100_OPP: The new APE operating point is ape100opp
+ * @APE_50_OPP: 50%
+ */
+enum ape_opp {
+ APE_OPP_INIT = 0x00,
+ APE_NO_CHANGE = 0x01,
+ APE_100_OPP = 0x02,
+ APE_50_OPP = 0x03
+};
+
+/**
+ * enum hw_acc_state - State definition for hardware accelerator
+ * @HW_NO_CHANGE: The hardware accelerator state must remain unchanged
+ * @HW_OFF: The hardware accelerator must be switched off
+ * @HW_OFF_RAMRET: The hardware accelerator must be switched off with its
+ * internal RAM in retention
+ * @HW_ON: The hwa hardware accelerator hwa must be switched on
+ *
+ * NOTE! Deprecated, to be removed when all users switched over to use the
+ * regulator API.
+ */
+enum hw_acc_state {
+ HW_NO_CHANGE = 0x00,
+ HW_OFF = 0x01,
+ HW_OFF_RAMRET = 0x02,
+ HW_ON = 0x04
+};
+
+/**
+ * enum mbox_2_arm_stat - Status messages definition for mbox_arm
+ * @BOOT_TO_EXECUTEOK: The apBoot to apExecute state transition has been
+ * completed
+ * @DEEPSLEEPOK: The apExecute to apDeepSleep state transition has been
+ * completed
+ * @SLEEPOK: The apExecute to apSleep state transition has been completed
+ * @IDLEOK: The apExecute to apIdle state transition has been completed
+ * @SOFTRESETOK: The A9 watchdog/ SoftReset state has been completed
+ * @SOFTRESETGO : The A9 watchdog/SoftReset state is on going
+ * @BOOT_TO_EXECUTE: The apBoot to apExecute state transition is on going
+ * @EXECUTE_TO_DEEPSLEEP: The apExecute to apDeepSleep state transition is on
+ * going
+ * @DEEPSLEEP_TO_EXECUTE: The apDeepSleep to apExecute state transition is on
+ * going
+ * @DEEPSLEEP_TO_EXECUTEOK: The apDeepSleep to apExecute state transition has
+ * been completed
+ * @EXECUTE_TO_SLEEP: The apExecute to apSleep state transition is on going
+ * @SLEEP_TO_EXECUTE: The apSleep to apExecute state transition is on going
+ * @SLEEP_TO_EXECUTEOK: The apSleep to apExecute state transition has been
+ * completed
+ * @EXECUTE_TO_IDLE: The apExecute to apIdle state transition is on going
+ * @IDLE_TO_EXECUTE: The apIdle to apExecute state transition is on going
+ * @IDLE_TO_EXECUTEOK: The apIdle to apExecute state transition has been
+ * completed
+ * @INIT_STATUS: Status init
+ */
+enum ap_pwrsttr_status {
+ BOOT_TO_EXECUTEOK = 0xFF,
+ DEEPSLEEPOK = 0xFE,
+ SLEEPOK = 0xFD,
+ IDLEOK = 0xFC,
+ SOFTRESETOK = 0xFB,
+ SOFTRESETGO = 0xFA,
+ BOOT_TO_EXECUTE = 0xF9,
+ EXECUTE_TO_DEEPSLEEP = 0xF8,
+ DEEPSLEEP_TO_EXECUTE = 0xF7,
+ DEEPSLEEP_TO_EXECUTEOK = 0xF6,
+ EXECUTE_TO_SLEEP = 0xF5,
+ SLEEP_TO_EXECUTE = 0xF4,
+ SLEEP_TO_EXECUTEOK = 0xF3,
+ EXECUTE_TO_IDLE = 0xF2,
+ IDLE_TO_EXECUTE = 0xF1,
+ IDLE_TO_EXECUTEOK = 0xF0,
+ RDYTODS_RETURNTOEXE = 0xEF,
+ NORDYTODS_RETURNTOEXE = 0xEE,
+ EXETOSLEEP_RETURNTOEXE = 0xED,
+ EXETOIDLE_RETURNTOEXE = 0xEC,
+ INIT_STATUS = 0xEB,
+
+ /*error messages */
+ INITERROR = 0x00,
+ PLLARMLOCKP_ER = 0x01,
+ PLLDDRLOCKP_ER = 0x02,
+ PLLSOCLOCKP_ER = 0x03,
+ PLLSOCK1LOCKP_ER = 0x04,
+ ARMWFI_ER = 0x05,
+ SYSCLKOK_ER = 0x06,
+ I2C_NACK_DATA_ER = 0x07,
+ BOOT_ER = 0x08,
+ I2C_STATUS_ALWAYS_1 = 0x0A,
+ I2C_NACK_REG_ADDR_ER = 0x0B,
+ I2C_NACK_DATA0123_ER = 0x1B,
+ I2C_NACK_ADDR_ER = 0x1F,
+ CURAPPWRSTISNOT_BOOT = 0x20,
+ CURAPPWRSTISNOT_EXECUTE = 0x21,
+ CURAPPWRSTISNOT_SLEEPMODE = 0x22,
+ CURAPPWRSTISNOT_CORRECTFORIT10 = 0x23,
+ FIFO4500WUISNOT_WUPEVENT = 0x24,
+ PLL32KLOCKP_ER = 0x29,
+ DDRDEEPSLEEPOK_ER = 0x2A,
+ ROMCODEREADY_ER = 0x50,
+ WUPBEFOREDS = 0x51,
+ DDRCONFIG_ER = 0x52,
+ WUPBEFORESLEEP = 0x53,
+ WUPBEFOREIDLE = 0x54
+}; /* earlier called as mbox_2_arm_stat */
+
+/**
+ * enum dvfs_stat - DVFS status messages definition
+ * @DVFS_GO: A state transition DVFS is on going
+ * @DVFS_ARM100OPPOK: The state transition DVFS has been completed for 100OPP
+ * @DVFS_ARM50OPPOK: The state transition DVFS has been completed for 50OPP
+ * @DVFS_ARMEXTCLKOK: The state transition DVFS has been completed for EXTCLK
+ * @DVFS_NOCHGTCLKOK: The state transition DVFS has been completed for
+ * NOCHGCLK
+ * @DVFS_INITSTATUS: Value init
+ */
+enum dvfs_stat {
+ DVFS_GO = 0xFF,
+ DVFS_ARM100OPPOK = 0xFE,
+ DVFS_ARM50OPPOK = 0xFD,
+ DVFS_ARMEXTCLKOK = 0xFC,
+ DVFS_NOCHGTCLKOK = 0xFB,
+ DVFS_INITSTATUS = 0x00
+};
+
+/**
+ * enum sva_mmdsp_stat - SVA MMDSP status messages
+ * @SVA_MMDSP_GO: SVAMMDSP interrupt has happened
+ * @SVA_MMDSP_INIT: Status init
+ */
+enum sva_mmdsp_stat {
+ SVA_MMDSP_GO = 0xFF,
+ SVA_MMDSP_INIT = 0x00
+};
+
+/**
+ * enum sia_mmdsp_stat - SIA MMDSP status messages
+ * @SIA_MMDSP_GO: SIAMMDSP interrupt has happened
+ * @SIA_MMDSP_INIT: Status init
+ */
+enum sia_mmdsp_stat {
+ SIA_MMDSP_GO = 0xFF,
+ SIA_MMDSP_INIT = 0x00
+};
+
+/**
+ * enum mbox_to_arm_err - Error messages definition
+ * @INIT_ERR: Init value
+ * @PLLARMLOCKP_ERR: PLLARM has not been correctly locked in given time
+ * @PLLDDRLOCKP_ERR: PLLDDR has not been correctly locked in the given time
+ * @PLLSOC0LOCKP_ERR: PLLSOC0 has not been correctly locked in the given time
+ * @PLLSOC1LOCKP_ERR: PLLSOC1 has not been correctly locked in the given time
+ * @ARMWFI_ERR: The ARM WFI has not been correctly executed in the given time
+ * @SYSCLKOK_ERR: The SYSCLK is not available in the given time
+ * @BOOT_ERR: Romcode has not validated the XP70 self reset in the given time
+ * @ROMCODESAVECONTEXT: The Romcode didn.t correctly save it secure context
+ * @VARMHIGHSPEEDVALTO_ERR: The ARM high speed supply value transfered
+ * through I2C has not been correctly executed in the given time
+ * @VARMHIGHSPEEDACCESS_ERR: The command value of VarmHighSpeedVal transfered
+ * through I2C has not been correctly executed in the given time
+ * @VARMLOWSPEEDVALTO_ERR:The ARM low speed supply value transfered through
+ * I2C has not been correctly executed in the given time
+ * @VARMLOWSPEEDACCESS_ERR: The command value of VarmLowSpeedVal transfered
+ * through I2C has not been correctly executed in the given time
+ * @VARMRETENTIONVALTO_ERR: The ARM retention supply value transfered through
+ * I2C has not been correctly executed in the given time
+ * @VARMRETENTIONACCESS_ERR: The command value of VarmRetentionVal transfered
+ * through I2C has not been correctly executed in the given time
+ * @VAPEHIGHSPEEDVALTO_ERR: The APE highspeed supply value transfered through
+ * I2C has not been correctly executed in the given time
+ * @VSAFEHPVALTO_ERR: The SAFE high power supply value transfered through I2C
+ * has not been correctly executed in the given time
+ * @VMODSEL1VALTO_ERR: The MODEM sel1 supply value transfered through I2C has
+ * not been correctly executed in the given time
+ * @VMODSEL2VALTO_ERR: The MODEM sel2 supply value transfered through I2C has
+ * not been correctly executed in the given time
+ * @VARMOFFACCESS_ERR: The command value of Varm ON/OFF transfered through
+ * I2C has not been correctly executed in the given time
+ * @VAPEOFFACCESS_ERR: The command value of Vape ON/OFF transfered through
+ * I2C has not been correctly executed in the given time
+ * @VARMRETACCES_ERR: The command value of Varm retention ON/OFF transfered
+ * through I2C has not been correctly executed in the given time
+ * @CURAPPWRSTISNOTBOOT:Generated when Arm want to do power state transition
+ * ApBoot to ApExecute but the power current state is not Apboot
+ * @CURAPPWRSTISNOTEXECUTE: Generated when Arm want to do power state
+ * transition from ApExecute to others power state but the
+ * power current state is not ApExecute
+ * @CURAPPWRSTISNOTSLEEPMODE: Generated when wake up events are transmitted
+ * but the power current state is not ApDeepSleep/ApSleep/ApIdle
+ * @CURAPPWRSTISNOTCORRECTDBG: Generated when wake up events are transmitted
+ * but the power current state is not correct
+ * @ARMREGU1VALTO_ERR:The ArmRegu1 value transferred through I2C has not
+ * been correctly executed in the given time
+ * @ARMREGU2VALTO_ERR: The ArmRegu2 value transferred through I2C has not
+ * been correctly executed in the given time
+ * @VAPEREGUVALTO_ERR: The VApeRegu value transfered through I2C has not
+ * been correctly executed in the given time
+ * @VSMPS3REGUVALTO_ERR: The VSmps3Regu value transfered through I2C has not
+ * been correctly executed in the given time
+ * @VMODREGUVALTO_ERR: The VModemRegu value transfered through I2C has not
+ * been correctly executed in the given time
+ */
+enum mbox_to_arm_err {
+ INIT_ERR = 0x00,
+ PLLARMLOCKP_ERR = 0x01,
+ PLLDDRLOCKP_ERR = 0x02,
+ PLLSOC0LOCKP_ERR = 0x03,
+ PLLSOC1LOCKP_ERR = 0x04,
+ ARMWFI_ERR = 0x05,
+ SYSCLKOK_ERR = 0x06,
+ BOOT_ERR = 0x07,
+ ROMCODESAVECONTEXT = 0x08,
+ VARMHIGHSPEEDVALTO_ERR = 0x10,
+ VARMHIGHSPEEDACCESS_ERR = 0x11,
+ VARMLOWSPEEDVALTO_ERR = 0x12,
+ VARMLOWSPEEDACCESS_ERR = 0x13,
+ VARMRETENTIONVALTO_ERR = 0x14,
+ VARMRETENTIONACCESS_ERR = 0x15,
+ VAPEHIGHSPEEDVALTO_ERR = 0x16,
+ VSAFEHPVALTO_ERR = 0x17,
+ VMODSEL1VALTO_ERR = 0x18,
+ VMODSEL2VALTO_ERR = 0x19,
+ VARMOFFACCESS_ERR = 0x1A,
+ VAPEOFFACCESS_ERR = 0x1B,
+ VARMRETACCES_ERR = 0x1C,
+ CURAPPWRSTISNOTBOOT = 0x20,
+ CURAPPWRSTISNOTEXECUTE = 0x21,
+ CURAPPWRSTISNOTSLEEPMODE = 0x22,
+ CURAPPWRSTISNOTCORRECTDBG = 0x23,
+ ARMREGU1VALTO_ERR = 0x24,
+ ARMREGU2VALTO_ERR = 0x25,
+ VAPEREGUVALTO_ERR = 0x26,
+ VSMPS3REGUVALTO_ERR = 0x27,
+ VMODREGUVALTO_ERR = 0x28
+};
+
+enum hw_acc {
+ SVAMMDSP = 0,
+ SVAPIPE = 1,
+ SIAMMDSP = 2,
+ SIAPIPE = 3,
+ SGA = 4,
+ B2R2MCDE = 5,
+ ESRAM12 = 6,
+ ESRAM34 = 7,
+};
+
+enum cs_pwrmgt {
+ PWRDNCS0 = 0,
+ WKUPCS0 = 1,
+ PWRDNCS1 = 2,
+ WKUPCS1 = 3
+};
+
+/* Defs related to autonomous power management */
+
+/**
+ * enum sia_sva_pwr_policy - Power policy
+ * @NO_CHGT: No change
+ * @DSPOFF_HWPOFF:
+ * @DSPOFFRAMRET_HWPOFF:
+ * @DSPCLKOFF_HWPOFF:
+ * @DSPCLKOFF_HWPCLKOFF:
+ *
+ */
+enum sia_sva_pwr_policy {
+ NO_CHGT = 0x0,
+ DSPOFF_HWPOFF = 0x1,
+ DSPOFFRAMRET_HWPOFF = 0x2,
+ DSPCLKOFF_HWPOFF = 0x3,
+ DSPCLKOFF_HWPCLKOFF = 0x4,
+};
+
+/**
+ * enum auto_enable - Auto Power enable
+ * @AUTO_OFF:
+ * @AUTO_ON:
+ *
+ */
+enum auto_enable {
+ AUTO_OFF = 0x0,
+ AUTO_ON = 0x1,
+};
+
+/* End of file previously known as prcmu-fw-defs_v1.h */
+
+/* PRCMU Wakeup defines */
+enum prcmu_wakeup_index {
+ PRCMU_WAKEUP_INDEX_RTC,
+ PRCMU_WAKEUP_INDEX_RTT0,
+ PRCMU_WAKEUP_INDEX_RTT1,
+ PRCMU_WAKEUP_INDEX_HSI0,
+ PRCMU_WAKEUP_INDEX_HSI1,
+ PRCMU_WAKEUP_INDEX_USB,
+ PRCMU_WAKEUP_INDEX_ABB,
+ PRCMU_WAKEUP_INDEX_ABB_FIFO,
+ PRCMU_WAKEUP_INDEX_ARM,
+ NUM_PRCMU_WAKEUP_INDICES
+};
+#define PRCMU_WAKEUP(_name) (BIT(PRCMU_WAKEUP_INDEX_##_name))
+
+/* PRCMU QoS APE OPP class */
+#define PRCMU_QOS_APE_OPP 1
+#define PRCMU_QOS_DDR_OPP 2
+#define PRCMU_QOS_DEFAULT_VALUE -1
+
+/**
+ * enum hw_acc_dev - enum for hw accelerators
+ * @HW_ACC_SVAMMDSP: for SVAMMDSP
+ * @HW_ACC_SVAPIPE: for SVAPIPE
+ * @HW_ACC_SIAMMDSP: for SIAMMDSP
+ * @HW_ACC_SIAPIPE: for SIAPIPE
+ * @HW_ACC_SGA: for SGA
+ * @HW_ACC_B2R2: for B2R2
+ * @HW_ACC_MCDE: for MCDE
+ * @HW_ACC_ESRAM1: for ESRAM1
+ * @HW_ACC_ESRAM2: for ESRAM2
+ * @HW_ACC_ESRAM3: for ESRAM3
+ * @HW_ACC_ESRAM4: for ESRAM4
+ * @NUM_HW_ACC: number of hardware accelerators
+ *
+ * Different hw accelerators which can be turned ON/
+ * OFF or put into retention (MMDSPs and ESRAMs).
+ * Used with EPOD API.
+ *
+ * NOTE! Deprecated, to be removed when all users switched over to use the
+ * regulator API.
+ */
+enum hw_acc_dev {
+ HW_ACC_SVAMMDSP,
+ HW_ACC_SVAPIPE,
+ HW_ACC_SIAMMDSP,
+ HW_ACC_SIAPIPE,
+ HW_ACC_SGA,
+ HW_ACC_B2R2,
+ HW_ACC_MCDE,
+ HW_ACC_ESRAM1,
+ HW_ACC_ESRAM2,
+ HW_ACC_ESRAM3,
+ HW_ACC_ESRAM4,
+ NUM_HW_ACC
+};
+
+/*
+ * Ids for all EPODs (power domains)
+ * - EPOD_ID_SVAMMDSP: power domain for SVA MMDSP
+ * - EPOD_ID_SVAPIPE: power domain for SVA pipe
+ * - EPOD_ID_SIAMMDSP: power domain for SIA MMDSP
+ * - EPOD_ID_SIAPIPE: power domain for SIA pipe
+ * - EPOD_ID_SGA: power domain for SGA
+ * - EPOD_ID_B2R2_MCDE: power domain for B2R2 and MCDE
+ * - EPOD_ID_ESRAM12: power domain for ESRAM 1 and 2
+ * - EPOD_ID_ESRAM34: power domain for ESRAM 3 and 4
+ * - NUM_EPOD_ID: number of power domains
+ */
+#define EPOD_ID_SVAMMDSP 0
+#define EPOD_ID_SVAPIPE 1
+#define EPOD_ID_SIAMMDSP 2
+#define EPOD_ID_SIAPIPE 3
+#define EPOD_ID_SGA 4
+#define EPOD_ID_B2R2_MCDE 5
+#define EPOD_ID_ESRAM12 6
+#define EPOD_ID_ESRAM34 7
+#define NUM_EPOD_ID 8
+
+/*
+ * state definition for EPOD (power domain)
+ * - EPOD_STATE_NO_CHANGE: The EPOD should remain unchanged
+ * - EPOD_STATE_OFF: The EPOD is switched off
+ * - EPOD_STATE_RAMRET: The EPOD is switched off with its internal RAM in
+ * retention
+ * - EPOD_STATE_ON_CLK_OFF: The EPOD is switched on, clock is still off
+ * - EPOD_STATE_ON: Same as above, but with clock enabled
+ */
+#define EPOD_STATE_NO_CHANGE 0x00
+#define EPOD_STATE_OFF 0x01
+#define EPOD_STATE_RAMRET 0x02
+#define EPOD_STATE_ON_CLK_OFF 0x03
+#define EPOD_STATE_ON 0x04
+
+/*
+ * CLKOUT sources
+ */
+#define PRCMU_CLKSRC_CLK38M 0x00
+#define PRCMU_CLKSRC_ACLK 0x01
+#define PRCMU_CLKSRC_SYSCLK 0x02
+#define PRCMU_CLKSRC_LCDCLK 0x03
+#define PRCMU_CLKSRC_SDMMCCLK 0x04
+#define PRCMU_CLKSRC_TVCLK 0x05
+#define PRCMU_CLKSRC_TIMCLK 0x06
+#define PRCMU_CLKSRC_CLK009 0x07
+/* These are only valid for CLKOUT1: */
+#define PRCMU_CLKSRC_SIAMMDSPCLK 0x40
+#define PRCMU_CLKSRC_I2CCLK 0x41
+#define PRCMU_CLKSRC_MSP02CLK 0x42
+#define PRCMU_CLKSRC_ARMPLL_OBSCLK 0x43
+#define PRCMU_CLKSRC_HSIRXCLK 0x44
+#define PRCMU_CLKSRC_HSITXCLK 0x45
+#define PRCMU_CLKSRC_ARMCLKFIX 0x46
+#define PRCMU_CLKSRC_HDMICLK 0x47
+
+/*
+ * Definitions for autonomous power management configuration.
+ */
+
+#define PRCMU_AUTO_PM_OFF 0
+#define PRCMU_AUTO_PM_ON 1
+
+#define PRCMU_AUTO_PM_POWER_ON_HSEM BIT(0)
+#define PRCMU_AUTO_PM_POWER_ON_ABB_FIFO_IT BIT(1)
+
+enum prcmu_auto_pm_policy {
+ PRCMU_AUTO_PM_POLICY_NO_CHANGE,
+ PRCMU_AUTO_PM_POLICY_DSP_OFF_HWP_OFF,
+ PRCMU_AUTO_PM_POLICY_DSP_OFF_RAMRET_HWP_OFF,
+ PRCMU_AUTO_PM_POLICY_DSP_CLK_OFF_HWP_OFF,
+ PRCMU_AUTO_PM_POLICY_DSP_CLK_OFF_HWP_CLK_OFF,
+};
+
+/**
+ * struct prcmu_auto_pm_config - Autonomous power management configuration.
+ * @sia_auto_pm_enable: SIA autonomous pm enable. (PRCMU_AUTO_PM_{OFF,ON})
+ * @sia_power_on: SIA power ON enable. (PRCMU_AUTO_PM_POWER_ON_* bitmask)
+ * @sia_policy: SIA power policy. (enum prcmu_auto_pm_policy)
+ * @sva_auto_pm_enable: SVA autonomous pm enable. (PRCMU_AUTO_PM_{OFF,ON})
+ * @sva_power_on: SVA power ON enable. (PRCMU_AUTO_PM_POWER_ON_* bitmask)
+ * @sva_policy: SVA power policy. (enum prcmu_auto_pm_policy)
+ */
+struct prcmu_auto_pm_config {
+ u8 sia_auto_pm_enable;
+ u8 sia_power_on;
+ u8 sia_policy;
+ u8 sva_auto_pm_enable;
+ u8 sva_power_on;
+ u8 sva_policy;
+};
+
+/**
+ * enum ddr_opp - DDR OPP states definition
+ * @DDR_100_OPP: The new DDR operating point is ddr100opp
+ * @DDR_50_OPP: The new DDR operating point is ddr50opp
+ * @DDR_25_OPP: The new DDR operating point is ddr25opp
+ */
+enum ddr_opp {
+ DDR_100_OPP = 0x00,
+ DDR_50_OPP = 0x01,
+ DDR_25_OPP = 0x02,
+};
+
+/*
+ * Clock identifiers.
+ */
+enum prcmu_clock {
+ PRCMU_SGACLK,
+ PRCMU_UARTCLK,
+ PRCMU_MSP02CLK,
+ PRCMU_MSP1CLK,
+ PRCMU_I2CCLK,
+ PRCMU_SDMMCCLK,
+ PRCMU_SLIMCLK,
+ PRCMU_PER1CLK,
+ PRCMU_PER2CLK,
+ PRCMU_PER3CLK,
+ PRCMU_PER5CLK,
+ PRCMU_PER6CLK,
+ PRCMU_PER7CLK,
+ PRCMU_LCDCLK,
+ PRCMU_BMLCLK,
+ PRCMU_HSITXCLK,
+ PRCMU_HSIRXCLK,
+ PRCMU_HDMICLK,
+ PRCMU_APEATCLK,
+ PRCMU_APETRACECLK,
+ PRCMU_MCDECLK,
+ PRCMU_IPI2CCLK,
+ PRCMU_DSIALTCLK,
+ PRCMU_DMACLK,
+ PRCMU_B2R2CLK,
+ PRCMU_TVCLK,
+ PRCMU_SSPCLK,
+ PRCMU_RNGCLK,
+ PRCMU_UICCCLK,
+ PRCMU_NUM_REG_CLOCKS,
+ PRCMU_SYSCLK = PRCMU_NUM_REG_CLOCKS,
+ PRCMU_TIMCLK,
+};
+
+/*
+ * Definitions for controlling ESRAM0 in deep sleep.
+ */
+#define ESRAM0_DEEP_SLEEP_STATE_OFF 1
+#define ESRAM0_DEEP_SLEEP_STATE_RET 2
+
+#ifdef CONFIG_MFD_DB8500_PRCMU
+void __init prcmu_early_init(void);
+int prcmu_set_display_clocks(void);
+int prcmu_disable_dsipll(void);
+int prcmu_enable_dsipll(void);
+#else
+static inline void __init prcmu_early_init(void) {}
+#endif
+
+#ifdef CONFIG_MFD_DB8500_PRCMU
+
+int prcmu_set_rc_a2p(enum romcode_write);
+enum romcode_read prcmu_get_rc_p2a(void);
+enum ap_pwrst prcmu_get_xp70_current_state(void);
+int prcmu_set_power_state(u8 state, bool keep_ulp_clk, bool keep_ap_pll);
+
+void prcmu_enable_wakeups(u32 wakeups);
+static inline void prcmu_disable_wakeups(void)
+{
+ prcmu_enable_wakeups(0);
+}
+
+void prcmu_config_abb_event_readout(u32 abb_events);
+void prcmu_get_abb_event_buffer(void __iomem **buf);
+int prcmu_set_arm_opp(u8 opp);
+int prcmu_get_arm_opp(void);
+bool prcmu_has_arm_maxopp(void);
+bool prcmu_is_u8400(void);
+int prcmu_set_ape_opp(u8 opp);
+int prcmu_get_ape_opp(void);
+int prcmu_request_ape_opp_100_voltage(bool enable);
+int prcmu_release_usb_wakeup_state(void);
+int prcmu_set_ddr_opp(u8 opp);
+int prcmu_get_ddr_opp(void);
+unsigned long prcmu_qos_get_cpufreq_opp_delay(void);
+void prcmu_qos_set_cpufreq_opp_delay(unsigned long);
+/* NOTE! Use regulator framework instead */
+int prcmu_set_hwacc(u16 hw_acc_dev, u8 state);
+int prcmu_set_epod(u16 epod_id, u8 epod_state);
+void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
+ struct prcmu_auto_pm_config *idle);
+bool prcmu_is_auto_pm_enabled(void);
+
+int prcmu_config_clkout(u8 clkout, u8 source, u8 div);
+int prcmu_request_clock(u8 clock, bool enable);
+int prcmu_set_clock_divider(u8 clock, u8 divider);
+int prcmu_config_esram0_deep_sleep(u8 state);
+int prcmu_config_hotdog(u8 threshold);
+int prcmu_config_hotmon(u8 low, u8 high);
+int prcmu_start_temp_sense(u16 cycles32k);
+int prcmu_stop_temp_sense(void);
+int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
+int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
+
+void prcmu_ac_wake_req(void);
+void prcmu_ac_sleep_req(void);
+void prcmu_system_reset(u16 reset_code);
+void prcmu_modem_reset(void);
+bool prcmu_is_ac_wake_requested(void);
+void prcmu_enable_spi2(void);
+void prcmu_disable_spi2(void);
+
+#else /* !CONFIG_MFD_DB8500_PRCMU */
+
+static inline int prcmu_set_rc_a2p(enum romcode_write code)
+{
+ return 0;
+}
+
+static inline enum romcode_read prcmu_get_rc_p2a(void)
+{
+ return INIT;
+}
+
+static inline enum ap_pwrst prcmu_get_xp70_current_state(void)
+{
+ return AP_EXECUTE;
+}
+
+static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
+ bool keep_ap_pll)
+{
+ return 0;
+}
+
+static inline void prcmu_enable_wakeups(u32 wakeups) {}
+
+static inline void prcmu_disable_wakeups(void) {}
+
+static inline void prcmu_config_abb_event_readout(u32 abb_events) {}
+
+static inline int prcmu_set_arm_opp(u8 opp)
+{
+ return 0;
+}
+
+static inline int prcmu_get_arm_opp(void)
+{
+ return ARM_100_OPP;
+}
+
+static bool prcmu_has_arm_maxopp(void)
+{
+ return false;
+}
+
+static bool prcmu_is_u8400(void)
+{
+ return false;
+}
+
+static inline int prcmu_set_ape_opp(u8 opp)
+{
+ return 0;
+}
+
+static inline int prcmu_get_ape_opp(void)
+{
+ return APE_100_OPP;
+}
+
+static inline int prcmu_request_ape_opp_100_voltage(bool enable)
+{
+ return 0;
+}
+
+static inline int prcmu_release_usb_wakeup_state(void)
+{
+ return 0;
+}
+
+static inline int prcmu_set_ddr_opp(u8 opp)
+{
+ return 0;
+}
+
+static inline int prcmu_get_ddr_opp(void)
+{
+ return DDR_100_OPP;
+}
+
+static inline unsigned long prcmu_qos_get_cpufreq_opp_delay(void)
+{
+ return 0;
+}
+
+static inline void prcmu_qos_set_cpufreq_opp_delay(unsigned long n) {}
+
+static inline int prcmu_set_hwacc(u16 hw_acc_dev, u8 state)
+{
+ return 0;
+}
+
+static inline void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
+ struct prcmu_auto_pm_config *idle)
+{
+}
+
+static inline bool prcmu_is_auto_pm_enabled(void)
+{
+ return false;
+}
+
+static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
+{
+ return 0;
+}
+
+static inline int prcmu_request_clock(u8 clock, bool enable)
+{
+ return 0;
+}
+
+static inline int prcmu_set_clock_divider(u8 clock, u8 divider)
+{
+ return 0;
+}
+
+int prcmu_config_esram0_deep_sleep(u8 state)
+{
+ return 0;
+}
+
+static inline int prcmu_config_hotdog(u8 threshold)
+{
+ return 0;
+}
+
+static inline int prcmu_config_hotmon(u8 low, u8 high)
+{
+ return 0;
+}
+
+static inline int prcmu_start_temp_sense(u16 cycles32k)
+{
+ return 0;
+}
+
+static inline int prcmu_stop_temp_sense(void)
+{
+ return 0;
+}
+
+static inline int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
+{
+ return -ENOSYS;
+}
+
+static inline int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
+{
+ return -ENOSYS;
+}
+
+static inline void prcmu_ac_wake_req(void) {}
+
+static inline void prcmu_ac_sleep_req(void) {}
+
+static inline void prcmu_system_reset(u16 reset_code) {}
+
+static inline void prcmu_modem_reset(void) {}
+
+static inline bool prcmu_is_ac_wake_requested(void)
+{
+ return false;
+}
+
+#ifndef CONFIG_UX500_SOC_DB5500
+static inline int prcmu_set_display_clocks(void)
+{
+ return 0;
+}
+
+static inline int prcmu_disable_dsipll(void)
+{
+ return 0;
+}
+
+static inline int prcmu_enable_dsipll(void)
+{
+ return 0;
+}
+#endif
+
+static inline int prcmu_enable_spi2(void)
+{
+ return 0;
+}
+
+static inline int prcmu_disable_spi2(void)
+{
+ return 0;
+}
+
+#endif /* !CONFIG_MFD_DB8500_PRCMU */
+
+#ifdef CONFIG_UX500_PRCMU_QOS_POWER
+int prcmu_qos_requirement(int pm_qos_class);
+int prcmu_qos_add_requirement(int pm_qos_class, char *name, s32 value);
+int prcmu_qos_update_requirement(int pm_qos_class, char *name, s32 new_value);
+void prcmu_qos_remove_requirement(int pm_qos_class, char *name);
+int prcmu_qos_add_notifier(int prcmu_qos_class,
+ struct notifier_block *notifier);
+int prcmu_qos_remove_notifier(int prcmu_qos_class,
+ struct notifier_block *notifier);
+#else
+static inline int prcmu_qos_requirement(int prcmu_qos_class)
+{
+ return 0;
+}
+
+static inline int prcmu_qos_add_requirement(int prcmu_qos_class,
+ char *name, s32 value)
+{
+ return 0;
+}
+
+static inline int prcmu_qos_update_requirement(int prcmu_qos_class,
+ char *name, s32 new_value)
+{
+ return 0;
+}
+
+static inline void prcmu_qos_remove_requirement(int prcmu_qos_class, char *name)
+{
+}
+
+static inline int prcmu_qos_add_notifier(int prcmu_qos_class,
+ struct notifier_block *notifier)
+{
+ return 0;
+}
+static inline int prcmu_qos_remove_notifier(int prcmu_qos_class,
+ struct notifier_block *notifier)
+{
+ return 0;
+}
+
+#endif
+
+#endif /* __MFD_DB8500_PRCMU_H */
diff --git a/include/linux/mfd/tmio.h b/include/linux/mfd/tmio.h
index 8e70310..5a90266 100644
--- a/include/linux/mfd/tmio.h
+++ b/include/linux/mfd/tmio.h
@@ -4,6 +4,7 @@
#include <linux/fb.h>
#include <linux/io.h>
#include <linux/platform_device.h>
+#include <linux/pm_runtime.h>
#define tmio_ioread8(addr) readb(addr)
#define tmio_ioread16(addr) readw(addr)
@@ -61,6 +62,12 @@
* Some controllers can support SDIO IRQ signalling.
*/
#define TMIO_MMC_SDIO_IRQ (1 << 2)
+/*
+ * Some platforms can detect card insertion events with controller powered
+ * down, in which case they have to call tmio_mmc_cd_wakeup() to power up the
+ * controller and report the event to the driver.
+ */
+#define TMIO_MMC_HAS_COLD_CD (1 << 3)
int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base);
int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base);
@@ -82,11 +89,21 @@
unsigned long flags;
u32 ocr_mask; /* available voltages */
struct tmio_mmc_dma *dma;
+ struct device *dev;
+ bool power;
void (*set_pwr)(struct platform_device *host, int state);
void (*set_clk_div)(struct platform_device *host, int state);
int (*get_cd)(struct platform_device *host);
};
+static inline void tmio_mmc_cd_wakeup(struct tmio_mmc_data *pdata)
+{
+ if (pdata && !pdata->power) {
+ pdata->power = true;
+ pm_runtime_get(pdata->dev);
+ }
+}
+
/*
* data for the NAND controller
*/
diff --git a/include/linux/mm.h b/include/linux/mm.h
index 6507dde..8eb969e 100644
--- a/include/linux/mm.h
+++ b/include/linux/mm.h
@@ -153,6 +153,7 @@
#define FAULT_FLAG_MKWRITE 0x04 /* Fault was mkwrite of existing pte */
#define FAULT_FLAG_ALLOW_RETRY 0x08 /* Retry fault if blocking */
#define FAULT_FLAG_RETRY_NOWAIT 0x10 /* Don't drop mmap_sem and wait when retrying */
+#define FAULT_FLAG_KILLABLE 0x20 /* The fault task is in SIGKILL killable region */
/*
* This interface is used by x86 PAT code to identify a pfn mapping that is
@@ -604,10 +605,6 @@
#define NODE_NOT_IN_PAGE_FLAGS
#endif
-#ifndef PFN_SECTION_SHIFT
-#define PFN_SECTION_SHIFT 0
-#endif
-
/*
* Define the bit shifts to access each section. For non-existent
* sections we define the shift as 0; that plus a 0 mask ensures
@@ -681,6 +678,12 @@
}
#if defined(CONFIG_SPARSEMEM) && !defined(CONFIG_SPARSEMEM_VMEMMAP)
+static inline void set_page_section(struct page *page, unsigned long section)
+{
+ page->flags &= ~(SECTIONS_MASK << SECTIONS_PGSHIFT);
+ page->flags |= (section & SECTIONS_MASK) << SECTIONS_PGSHIFT;
+}
+
static inline unsigned long page_to_section(struct page *page)
{
return (page->flags >> SECTIONS_PGSHIFT) & SECTIONS_MASK;
@@ -699,18 +702,14 @@
page->flags |= (node & NODES_MASK) << NODES_PGSHIFT;
}
-static inline void set_page_section(struct page *page, unsigned long section)
-{
- page->flags &= ~(SECTIONS_MASK << SECTIONS_PGSHIFT);
- page->flags |= (section & SECTIONS_MASK) << SECTIONS_PGSHIFT;
-}
-
static inline void set_page_links(struct page *page, enum zone_type zone,
unsigned long node, unsigned long pfn)
{
set_page_zone(page, zone);
set_page_node(page, node);
+#if defined(CONFIG_SPARSEMEM) && !defined(CONFIG_SPARSEMEM_VMEMMAP)
set_page_section(page, pfn_to_section_nr(pfn));
+#endif
}
/*
@@ -862,26 +861,18 @@
#define offset_in_page(p) ((unsigned long)(p) & ~PAGE_MASK)
/*
- * Flags passed to show_mem() and __show_free_areas() to suppress output in
+ * Flags passed to show_mem() and show_free_areas() to suppress output in
* various contexts.
*/
#define SHOW_MEM_FILTER_NODES (0x0001u) /* filter disallowed nodes */
-extern void show_free_areas(void);
-extern void __show_free_areas(unsigned int flags);
+extern void show_free_areas(unsigned int flags);
+extern bool skip_free_areas_node(unsigned int flags, int nid);
int shmem_lock(struct file *file, int lock, struct user_struct *user);
struct file *shmem_file_setup(const char *name, loff_t size, unsigned long flags);
int shmem_zero_setup(struct vm_area_struct *);
-#ifndef CONFIG_MMU
-extern unsigned long shmem_get_unmapped_area(struct file *file,
- unsigned long addr,
- unsigned long len,
- unsigned long pgoff,
- unsigned long flags);
-#endif
-
extern int can_do_mlock(void);
extern int user_shm_lock(size_t, struct user_struct *);
extern void user_shm_unlock(size_t, struct user_struct *);
@@ -894,8 +885,6 @@
struct address_space *check_mapping; /* Check page->mapping if set */
pgoff_t first_index; /* Lowest page->index to unmap */
pgoff_t last_index; /* Highest page->index to unmap */
- spinlock_t *i_mmap_lock; /* For unmap_mapping_range: */
- unsigned long truncate_count; /* Compare vm_truncate_count */
};
struct page *vm_normal_page(struct vm_area_struct *vma, unsigned long addr,
@@ -905,7 +894,7 @@
unsigned long size);
unsigned long zap_page_range(struct vm_area_struct *vma, unsigned long address,
unsigned long size, struct zap_details *);
-unsigned long unmap_vmas(struct mmu_gather **tlb,
+unsigned long unmap_vmas(struct mmu_gather *tlb,
struct vm_area_struct *start_vma, unsigned long start_addr,
unsigned long end_addr, unsigned long *nr_accounted,
struct zap_details *);
@@ -1056,17 +1045,19 @@
/*
* per-process(per-mm_struct) statistics.
*/
-#if defined(SPLIT_RSS_COUNTING)
-/*
- * The mm counters are not protected by its page_table_lock,
- * so must be incremented atomically.
- */
static inline void set_mm_counter(struct mm_struct *mm, int member, long value)
{
atomic_long_set(&mm->rss_stat.count[member], value);
}
+#if defined(SPLIT_RSS_COUNTING)
unsigned long get_mm_counter(struct mm_struct *mm, int member);
+#else
+static inline unsigned long get_mm_counter(struct mm_struct *mm, int member)
+{
+ return atomic_long_read(&mm->rss_stat.count[member]);
+}
+#endif
static inline void add_mm_counter(struct mm_struct *mm, int member, long value)
{
@@ -1083,38 +1074,6 @@
atomic_long_dec(&mm->rss_stat.count[member]);
}
-#else /* !USE_SPLIT_PTLOCKS */
-/*
- * The mm counters are protected by its page_table_lock,
- * so can be incremented directly.
- */
-static inline void set_mm_counter(struct mm_struct *mm, int member, long value)
-{
- mm->rss_stat.count[member] = value;
-}
-
-static inline unsigned long get_mm_counter(struct mm_struct *mm, int member)
-{
- return mm->rss_stat.count[member];
-}
-
-static inline void add_mm_counter(struct mm_struct *mm, int member, long value)
-{
- mm->rss_stat.count[member] += value;
-}
-
-static inline void inc_mm_counter(struct mm_struct *mm, int member)
-{
- mm->rss_stat.count[member]++;
-}
-
-static inline void dec_mm_counter(struct mm_struct *mm, int member)
-{
- mm->rss_stat.count[member]--;
-}
-
-#endif /* !USE_SPLIT_PTLOCKS */
-
static inline unsigned long get_mm_rss(struct mm_struct *mm)
{
return get_mm_counter(mm, MM_FILEPAGES) +
@@ -1163,13 +1122,24 @@
#endif
/*
+ * This struct is used to pass information from page reclaim to the shrinkers.
+ * We consolidate the values for easier extention later.
+ */
+struct shrink_control {
+ gfp_t gfp_mask;
+
+ /* How many slab objects shrinker() should scan and try to reclaim */
+ unsigned long nr_to_scan;
+};
+
+/*
* A callback you can register to apply pressure to ageable caches.
*
- * 'shrink' is passed a count 'nr_to_scan' and a 'gfpmask'. It should
- * look through the least-recently-used 'nr_to_scan' entries and
- * attempt to free them up. It should return the number of objects
- * which remain in the cache. If it returns -1, it means it cannot do
- * any scanning at this time (eg. there is a risk of deadlock).
+ * 'sc' is passed shrink_control which includes a count 'nr_to_scan'
+ * and a 'gfpmask'. It should look through the least-recently-used
+ * 'nr_to_scan' entries and attempt to free them up. It should return
+ * the number of objects which remain in the cache. If it returns -1, it means
+ * it cannot do any scanning at this time (eg. there is a risk of deadlock).
*
* The 'gfpmask' refers to the allocation we are currently trying to
* fulfil.
@@ -1178,7 +1148,7 @@
* querying the cache size, so a fastpath for that case is appropriate.
*/
struct shrinker {
- int (*shrink)(struct shrinker *, int nr_to_scan, gfp_t gfp_mask);
+ int (*shrink)(struct shrinker *, struct shrink_control *sc);
int seeks; /* seeks to recreate an obj */
/* These are for internal use */
@@ -1380,7 +1350,7 @@
extern void memmap_init_zone(unsigned long, int, unsigned long,
unsigned long, enum memmap_context);
extern void setup_per_zone_wmarks(void);
-extern void calculate_zone_inactive_ratio(struct zone *zone);
+extern int __meminit init_per_zone_wmark_min(void);
extern void mem_init(void);
extern void __init mmap_init(void);
extern void show_mem(unsigned int flags);
@@ -1388,6 +1358,8 @@
extern void si_meminfo_node(struct sysinfo *val, int nid);
extern int after_bootmem;
+extern void warn_alloc_failed(gfp_t gfp_mask, int order, const char *fmt, ...);
+
extern void setup_per_cpu_pageset(void);
extern void zone_pcp_update(struct zone *zone);
@@ -1517,15 +1489,17 @@
struct address_space *mapping,
struct file *filp);
-/* Do stack extension */
+/* Generic expand stack which grows the stack according to GROWS{UP,DOWN} */
extern int expand_stack(struct vm_area_struct *vma, unsigned long address);
+
+/* CONFIG_STACK_GROWSUP still needs to to grow downwards at some places */
+extern int expand_downwards(struct vm_area_struct *vma,
+ unsigned long address);
#if VM_GROWSUP
extern int expand_upwards(struct vm_area_struct *vma, unsigned long address);
#else
#define expand_upwards(vma, address) do { } while (0)
#endif
-extern int expand_stack_downwards(struct vm_area_struct *vma,
- unsigned long address);
/* Look up the first VMA which satisfies addr < vm_end, NULL if none. */
extern struct vm_area_struct * find_vma(struct mm_struct * mm, unsigned long addr);
@@ -1627,8 +1601,9 @@
int drop_caches_sysctl_handler(struct ctl_table *, int,
void __user *, size_t *, loff_t *);
-unsigned long shrink_slab(unsigned long scanned, gfp_t gfp_mask,
- unsigned long lru_pages);
+unsigned long shrink_slab(struct shrink_control *shrink,
+ unsigned long nr_pages_scanned,
+ unsigned long lru_pages);
#ifndef CONFIG_MMU
#define randomize_va_space 0
diff --git a/include/linux/mm_types.h b/include/linux/mm_types.h
index 02aa561..071d459 100644
--- a/include/linux/mm_types.h
+++ b/include/linux/mm_types.h
@@ -175,7 +175,6 @@
units, *not* PAGE_CACHE_SIZE */
struct file * vm_file; /* File we map to (can be NULL). */
void * vm_private_data; /* was vm_pte (shared mem) */
- unsigned long vm_truncate_count;/* truncate_count or restart_addr */
#ifndef CONFIG_MMU
struct vm_region *vm_region; /* NOMMU mapping region */
@@ -205,19 +204,16 @@
#if USE_SPLIT_PTLOCKS && defined(CONFIG_MMU)
#define SPLIT_RSS_COUNTING
-struct mm_rss_stat {
- atomic_long_t count[NR_MM_COUNTERS];
-};
/* per-thread cached information, */
struct task_rss_stat {
int events; /* for synchronization threshold */
int count[NR_MM_COUNTERS];
};
-#else /* !USE_SPLIT_PTLOCKS */
+#endif /* USE_SPLIT_PTLOCKS */
+
struct mm_rss_stat {
- unsigned long count[NR_MM_COUNTERS];
+ atomic_long_t count[NR_MM_COUNTERS];
};
-#endif /* !USE_SPLIT_PTLOCKS */
struct mm_struct {
struct vm_area_struct * mmap; /* list of VMAs */
@@ -266,8 +262,6 @@
struct linux_binfmt *binfmt;
- cpumask_t cpu_vm_mask;
-
/* Architecture-specific MM context */
mm_context_t context;
@@ -317,9 +311,14 @@
#ifdef CONFIG_TRANSPARENT_HUGEPAGE
pgtable_t pmd_huge_pte; /* protected by page_table_lock */
#endif
+
+ cpumask_var_t cpu_vm_mask_var;
};
/* Future-safe accessor for struct mm_struct's cpu_vm_mask. */
-#define mm_cpumask(mm) (&(mm)->cpu_vm_mask)
+static inline cpumask_t *mm_cpumask(struct mm_struct *mm)
+{
+ return mm->cpu_vm_mask_var;
+}
#endif /* _LINUX_MM_TYPES_H */
diff --git a/include/linux/mmc/Kbuild b/include/linux/mmc/Kbuild
new file mode 100644
index 0000000..1fb2644
--- /dev/null
+++ b/include/linux/mmc/Kbuild
@@ -0,0 +1 @@
+header-y += ioctl.h
diff --git a/include/linux/mmc/card.h b/include/linux/mmc/card.h
index adb4888..c6927a4 100644
--- a/include/linux/mmc/card.h
+++ b/include/linux/mmc/card.h
@@ -11,6 +11,7 @@
#define LINUX_MMC_CARD_H
#include <linux/mmc/core.h>
+#include <linux/mod_devicetable.h>
struct mmc_cid {
unsigned int manfid;
@@ -29,6 +30,7 @@
unsigned short cmdclass;
unsigned short tacc_clks;
unsigned int tacc_ns;
+ unsigned int c_size;
unsigned int r2w_factor;
unsigned int max_dtr;
unsigned int erase_size; /* In sectors */
@@ -45,6 +47,10 @@
u8 rev;
u8 erase_group_def;
u8 sec_feature_support;
+ u8 rel_sectors;
+ u8 rel_param;
+ u8 part_config;
+ unsigned int part_time; /* Units: ms */
unsigned int sa_timeout; /* Units: 100ns */
unsigned int hs_max_dtr;
unsigned int sectors;
@@ -57,13 +63,18 @@
bool enhanced_area_en; /* enable bit */
unsigned long long enhanced_area_offset; /* Units: Byte */
unsigned int enhanced_area_size; /* Units: KB */
+ unsigned int boot_size; /* in bytes */
};
struct sd_scr {
unsigned char sda_vsn;
+ unsigned char sda_spec3;
unsigned char bus_widths;
#define SD_SCR_BUS_WIDTH_1 (1<<0)
#define SD_SCR_BUS_WIDTH_4 (1<<2)
+ unsigned char cmds;
+#define SD_SCR_CMD20_SUPPORT (1<<0)
+#define SD_SCR_CMD23_SUPPORT (1<<1)
};
struct sd_ssr {
@@ -74,6 +85,39 @@
struct sd_switch_caps {
unsigned int hs_max_dtr;
+ unsigned int uhs_max_dtr;
+#define UHS_SDR104_MAX_DTR 208000000
+#define UHS_SDR50_MAX_DTR 100000000
+#define UHS_DDR50_MAX_DTR 50000000
+#define UHS_SDR25_MAX_DTR UHS_DDR50_MAX_DTR
+#define UHS_SDR12_MAX_DTR 25000000
+ unsigned int sd3_bus_mode;
+#define UHS_SDR12_BUS_SPEED 0
+#define UHS_SDR25_BUS_SPEED 1
+#define UHS_SDR50_BUS_SPEED 2
+#define UHS_SDR104_BUS_SPEED 3
+#define UHS_DDR50_BUS_SPEED 4
+
+#define SD_MODE_UHS_SDR12 (1 << UHS_SDR12_BUS_SPEED)
+#define SD_MODE_UHS_SDR25 (1 << UHS_SDR25_BUS_SPEED)
+#define SD_MODE_UHS_SDR50 (1 << UHS_SDR50_BUS_SPEED)
+#define SD_MODE_UHS_SDR104 (1 << UHS_SDR104_BUS_SPEED)
+#define SD_MODE_UHS_DDR50 (1 << UHS_DDR50_BUS_SPEED)
+ unsigned int sd3_drv_type;
+#define SD_DRIVER_TYPE_B 0x01
+#define SD_DRIVER_TYPE_A 0x02
+#define SD_DRIVER_TYPE_C 0x04
+#define SD_DRIVER_TYPE_D 0x08
+ unsigned int sd3_curr_limit;
+#define SD_SET_CURRENT_LIMIT_200 0
+#define SD_SET_CURRENT_LIMIT_400 1
+#define SD_SET_CURRENT_LIMIT_600 2
+#define SD_SET_CURRENT_LIMIT_800 3
+
+#define SD_MAX_CURRENT_200 (1 << SD_SET_CURRENT_LIMIT_200)
+#define SD_MAX_CURRENT_400 (1 << SD_SET_CURRENT_LIMIT_400)
+#define SD_MAX_CURRENT_600 (1 << SD_SET_CURRENT_LIMIT_600)
+#define SD_MAX_CURRENT_800 (1 << SD_SET_CURRENT_LIMIT_800)
};
struct sdio_cccr {
@@ -118,6 +162,8 @@
#define MMC_STATE_HIGHSPEED (1<<2) /* card is in high speed mode */
#define MMC_STATE_BLOCKADDR (1<<3) /* card uses block-addressing */
#define MMC_STATE_HIGHSPEED_DDR (1<<4) /* card is in high speed mode */
+#define MMC_STATE_ULTRAHIGHSPEED (1<<5) /* card is in ultra high speed mode */
+#define MMC_CARD_SDXC (1<<6) /* card is SDXC */
unsigned int quirks; /* card quirks */
#define MMC_QUIRK_LENIENT_FN0 (1<<0) /* allow SDIO FN0 writes outside of the VS CCCR range */
#define MMC_QUIRK_BLKSZ_FOR_BYTE_MODE (1<<1) /* use func->cur_blksize */
@@ -125,6 +171,10 @@
#define MMC_QUIRK_NONSTD_SDIO (1<<2) /* non-standard SDIO card attached */
/* (missing CIA registers) */
#define MMC_QUIRK_BROKEN_CLK_GATING (1<<3) /* clock gating the sdio bus will make card fail */
+#define MMC_QUIRK_NONSTD_FUNC_IF (1<<4) /* SDIO card has nonstd function interfaces */
+#define MMC_QUIRK_DISABLE_CD (1<<5) /* disconnect CD/DAT[3] resistor */
+#define MMC_QUIRK_INAND_CMD38 (1<<6) /* iNAND devices have broken CMD38 */
+#define MMC_QUIRK_BLK_NO_CMD23 (1<<7) /* Avoid CMD23 for regular multiblock */
unsigned int erase_size; /* erase size in sectors */
unsigned int erase_shift; /* if erase unit is power 2 */
@@ -145,14 +195,100 @@
struct sdio_cccr cccr; /* common card info */
struct sdio_cis cis; /* common tuple info */
struct sdio_func *sdio_func[SDIO_MAX_FUNCS]; /* SDIO functions (devices) */
+ struct sdio_func *sdio_single_irq; /* SDIO function when only one IRQ active */
unsigned num_info; /* number of info strings */
const char **info; /* info strings */
struct sdio_func_tuple *tuples; /* unknown common tuples */
+ unsigned int sd_bus_speed; /* Bus Speed Mode set for the card */
+
struct dentry *debugfs_root;
};
-void mmc_fixup_device(struct mmc_card *dev);
+/*
+ * The world is not perfect and supplies us with broken mmc/sdio devices.
+ * For at least some of these bugs we need a work-around.
+ */
+
+struct mmc_fixup {
+ /* CID-specific fields. */
+ const char *name;
+
+ /* Valid revision range */
+ u64 rev_start, rev_end;
+
+ unsigned int manfid;
+ unsigned short oemid;
+
+ /* SDIO-specfic fields. You can use SDIO_ANY_ID here of course */
+ u16 cis_vendor, cis_device;
+
+ void (*vendor_fixup)(struct mmc_card *card, int data);
+ int data;
+};
+
+#define CID_MANFID_ANY (-1u)
+#define CID_OEMID_ANY ((unsigned short) -1)
+#define CID_NAME_ANY (NULL)
+
+#define END_FIXUP { 0 }
+
+#define _FIXUP_EXT(_name, _manfid, _oemid, _rev_start, _rev_end, \
+ _cis_vendor, _cis_device, \
+ _fixup, _data) \
+ { \
+ .name = (_name), \
+ .manfid = (_manfid), \
+ .oemid = (_oemid), \
+ .rev_start = (_rev_start), \
+ .rev_end = (_rev_end), \
+ .cis_vendor = (_cis_vendor), \
+ .cis_device = (_cis_device), \
+ .vendor_fixup = (_fixup), \
+ .data = (_data), \
+ }
+
+#define MMC_FIXUP_REV(_name, _manfid, _oemid, _rev_start, _rev_end, \
+ _fixup, _data) \
+ _FIXUP_EXT(_name, _manfid, \
+ _oemid, _rev_start, _rev_end, \
+ SDIO_ANY_ID, SDIO_ANY_ID, \
+ _fixup, _data) \
+
+#define MMC_FIXUP(_name, _manfid, _oemid, _fixup, _data) \
+ MMC_FIXUP_REV(_name, _manfid, _oemid, 0, -1ull, _fixup, _data)
+
+#define SDIO_FIXUP(_vendor, _device, _fixup, _data) \
+ _FIXUP_EXT(CID_NAME_ANY, CID_MANFID_ANY, \
+ CID_OEMID_ANY, 0, -1ull, \
+ _vendor, _device, \
+ _fixup, _data) \
+
+#define cid_rev(hwrev, fwrev, year, month) \
+ (((u64) hwrev) << 40 | \
+ ((u64) fwrev) << 32 | \
+ ((u64) year) << 16 | \
+ ((u64) month))
+
+#define cid_rev_card(card) \
+ cid_rev(card->cid.hwrev, \
+ card->cid.fwrev, \
+ card->cid.year, \
+ card->cid.month)
+
+/*
+ * Unconditionally quirk add/remove.
+ */
+
+static inline void __maybe_unused add_quirk(struct mmc_card *card, int data)
+{
+ card->quirks |= data;
+}
+
+static inline void __maybe_unused remove_quirk(struct mmc_card *card, int data)
+{
+ card->quirks &= ~data;
+}
#define mmc_card_mmc(c) ((c)->type == MMC_TYPE_MMC)
#define mmc_card_sd(c) ((c)->type == MMC_TYPE_SD)
@@ -163,12 +299,50 @@
#define mmc_card_highspeed(c) ((c)->state & MMC_STATE_HIGHSPEED)
#define mmc_card_blockaddr(c) ((c)->state & MMC_STATE_BLOCKADDR)
#define mmc_card_ddr_mode(c) ((c)->state & MMC_STATE_HIGHSPEED_DDR)
+#define mmc_sd_card_uhs(c) ((c)->state & MMC_STATE_ULTRAHIGHSPEED)
+#define mmc_card_ext_capacity(c) ((c)->state & MMC_CARD_SDXC)
#define mmc_card_set_present(c) ((c)->state |= MMC_STATE_PRESENT)
#define mmc_card_set_readonly(c) ((c)->state |= MMC_STATE_READONLY)
#define mmc_card_set_highspeed(c) ((c)->state |= MMC_STATE_HIGHSPEED)
#define mmc_card_set_blockaddr(c) ((c)->state |= MMC_STATE_BLOCKADDR)
#define mmc_card_set_ddr_mode(c) ((c)->state |= MMC_STATE_HIGHSPEED_DDR)
+#define mmc_sd_card_set_uhs(c) ((c)->state |= MMC_STATE_ULTRAHIGHSPEED)
+#define mmc_card_set_ext_capacity(c) ((c)->state |= MMC_CARD_SDXC)
+
+/*
+ * Quirk add/remove for MMC products.
+ */
+
+static inline void __maybe_unused add_quirk_mmc(struct mmc_card *card, int data)
+{
+ if (mmc_card_mmc(card))
+ card->quirks |= data;
+}
+
+static inline void __maybe_unused remove_quirk_mmc(struct mmc_card *card,
+ int data)
+{
+ if (mmc_card_mmc(card))
+ card->quirks &= ~data;
+}
+
+/*
+ * Quirk add/remove for SD products.
+ */
+
+static inline void __maybe_unused add_quirk_sd(struct mmc_card *card, int data)
+{
+ if (mmc_card_sd(card))
+ card->quirks |= data;
+}
+
+static inline void __maybe_unused remove_quirk_sd(struct mmc_card *card,
+ int data)
+{
+ if (mmc_card_sd(card))
+ card->quirks &= ~data;
+}
static inline int mmc_card_lenient_fn0(const struct mmc_card *c)
{
@@ -180,6 +354,16 @@
return c->quirks & MMC_QUIRK_BLKSZ_FOR_BYTE_MODE;
}
+static inline int mmc_card_disable_cd(const struct mmc_card *c)
+{
+ return c->quirks & MMC_QUIRK_DISABLE_CD;
+}
+
+static inline int mmc_card_nonstd_func_interface(const struct mmc_card *c)
+{
+ return c->quirks & MMC_QUIRK_NONSTD_FUNC_IF;
+}
+
#define mmc_card_name(c) ((c)->cid.prod_name)
#define mmc_card_id(c) (dev_name(&(c)->dev))
@@ -203,4 +387,7 @@
extern int mmc_register_driver(struct mmc_driver *);
extern void mmc_unregister_driver(struct mmc_driver *);
+extern void mmc_fixup_device(struct mmc_card *card,
+ const struct mmc_fixup *table);
+
#endif
diff --git a/include/linux/mmc/core.h b/include/linux/mmc/core.h
index 07f27af..b6718e5 100644
--- a/include/linux/mmc/core.h
+++ b/include/linux/mmc/core.h
@@ -92,7 +92,7 @@
* actively failing requests
*/
- unsigned int erase_timeout; /* in milliseconds */
+ unsigned int cmd_timeout_ms; /* in milliseconds */
struct mmc_data *data; /* data segment associated with cmd */
struct mmc_request *mrq; /* associated request */
@@ -120,6 +120,7 @@
};
struct mmc_request {
+ struct mmc_command *sbc; /* SET_BLOCK_COUNT for multiblock */
struct mmc_command *cmd;
struct mmc_data *data;
struct mmc_command *stop;
@@ -133,8 +134,10 @@
extern void mmc_wait_for_req(struct mmc_host *, struct mmc_request *);
extern int mmc_wait_for_cmd(struct mmc_host *, struct mmc_command *, int);
+extern int mmc_app_cmd(struct mmc_host *, struct mmc_card *);
extern int mmc_wait_for_app_cmd(struct mmc_host *, struct mmc_card *,
struct mmc_command *, int);
+extern int mmc_switch(struct mmc_card *, u8, u8, u8, unsigned int);
#define MMC_ERASE_ARG 0x00000000
#define MMC_SECURE_ERASE_ARG 0x80000000
diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
index bcb793e..1ee4424 100644
--- a/include/linux/mmc/host.h
+++ b/include/linux/mmc/host.h
@@ -50,12 +50,30 @@
#define MMC_TIMING_LEGACY 0
#define MMC_TIMING_MMC_HS 1
#define MMC_TIMING_SD_HS 2
+#define MMC_TIMING_UHS_SDR12 MMC_TIMING_LEGACY
+#define MMC_TIMING_UHS_SDR25 MMC_TIMING_SD_HS
+#define MMC_TIMING_UHS_SDR50 3
+#define MMC_TIMING_UHS_SDR104 4
+#define MMC_TIMING_UHS_DDR50 5
unsigned char ddr; /* dual data rate used */
#define MMC_SDR_MODE 0
#define MMC_1_2V_DDR_MODE 1
#define MMC_1_8V_DDR_MODE 2
+
+ unsigned char signal_voltage; /* signalling voltage (1.8V or 3.3V) */
+
+#define MMC_SIGNAL_VOLTAGE_330 0
+#define MMC_SIGNAL_VOLTAGE_180 1
+#define MMC_SIGNAL_VOLTAGE_120 2
+
+ unsigned char drv_type; /* driver type (A, B, C, D) */
+
+#define MMC_SET_DRIVER_TYPE_B 0
+#define MMC_SET_DRIVER_TYPE_A 1
+#define MMC_SET_DRIVER_TYPE_C 2
+#define MMC_SET_DRIVER_TYPE_D 3
};
struct mmc_host_ops {
@@ -117,6 +135,10 @@
/* optional callback for HC quirks */
void (*init_card)(struct mmc_host *host, struct mmc_card *card);
+
+ int (*start_signal_voltage_switch)(struct mmc_host *host, struct mmc_ios *ios);
+ int (*execute_tuning)(struct mmc_host *host);
+ void (*enable_preset_value)(struct mmc_host *host, bool enable);
};
struct mmc_card;
@@ -173,6 +195,22 @@
/* DDR mode at 1.2V */
#define MMC_CAP_POWER_OFF_CARD (1 << 13) /* Can power off after boot */
#define MMC_CAP_BUS_WIDTH_TEST (1 << 14) /* CMD14/CMD19 bus width ok */
+#define MMC_CAP_UHS_SDR12 (1 << 15) /* Host supports UHS SDR12 mode */
+#define MMC_CAP_UHS_SDR25 (1 << 16) /* Host supports UHS SDR25 mode */
+#define MMC_CAP_UHS_SDR50 (1 << 17) /* Host supports UHS SDR50 mode */
+#define MMC_CAP_UHS_SDR104 (1 << 18) /* Host supports UHS SDR104 mode */
+#define MMC_CAP_UHS_DDR50 (1 << 19) /* Host supports UHS DDR50 mode */
+#define MMC_CAP_SET_XPC_330 (1 << 20) /* Host supports >150mA current at 3.3V */
+#define MMC_CAP_SET_XPC_300 (1 << 21) /* Host supports >150mA current at 3.0V */
+#define MMC_CAP_SET_XPC_180 (1 << 22) /* Host supports >150mA current at 1.8V */
+#define MMC_CAP_DRIVER_TYPE_A (1 << 23) /* Host supports Driver Type A */
+#define MMC_CAP_DRIVER_TYPE_C (1 << 24) /* Host supports Driver Type C */
+#define MMC_CAP_DRIVER_TYPE_D (1 << 25) /* Host supports Driver Type D */
+#define MMC_CAP_MAX_CURRENT_200 (1 << 26) /* Host max current limit is 200mA */
+#define MMC_CAP_MAX_CURRENT_400 (1 << 27) /* Host max current limit is 400mA */
+#define MMC_CAP_MAX_CURRENT_600 (1 << 28) /* Host max current limit is 600mA */
+#define MMC_CAP_MAX_CURRENT_800 (1 << 29) /* Host max current limit is 800mA */
+#define MMC_CAP_CMD23 (1 << 30) /* CMD23 supported. */
mmc_pm_flag_t pm_caps; /* supported pm features */
@@ -321,10 +359,19 @@
return !(host->caps & MMC_CAP_NONREMOVABLE) && mmc_assume_removable;
}
-static inline int mmc_card_is_powered_resumed(struct mmc_host *host)
+static inline int mmc_card_keep_power(struct mmc_host *host)
{
return host->pm_flags & MMC_PM_KEEP_POWER;
}
+static inline int mmc_card_wake_sdio_irq(struct mmc_host *host)
+{
+ return host->pm_flags & MMC_PM_WAKE_SDIO_IRQ;
+}
+
+static inline int mmc_host_cmd23(struct mmc_host *host)
+{
+ return host->caps & MMC_CAP_CMD23;
+}
#endif
diff --git a/include/linux/mmc/ioctl.h b/include/linux/mmc/ioctl.h
new file mode 100644
index 0000000..5baf298
--- /dev/null
+++ b/include/linux/mmc/ioctl.h
@@ -0,0 +1,54 @@
+#ifndef LINUX_MMC_IOCTL_H
+#define LINUX_MMC_IOCTL_H
+struct mmc_ioc_cmd {
+ /* Implies direction of data. true = write, false = read */
+ int write_flag;
+
+ /* Application-specific command. true = precede with CMD55 */
+ int is_acmd;
+
+ __u32 opcode;
+ __u32 arg;
+ __u32 response[4]; /* CMD response */
+ unsigned int flags;
+ unsigned int blksz;
+ unsigned int blocks;
+
+ /*
+ * Sleep at least postsleep_min_us useconds, and at most
+ * postsleep_max_us useconds *after* issuing command. Needed for
+ * some read commands for which cards have no other way of indicating
+ * they're ready for the next command (i.e. there is no equivalent of
+ * a "busy" indicator for read operations).
+ */
+ unsigned int postsleep_min_us;
+ unsigned int postsleep_max_us;
+
+ /*
+ * Override driver-computed timeouts. Note the difference in units!
+ */
+ unsigned int data_timeout_ns;
+ unsigned int cmd_timeout_ms;
+
+ /*
+ * For 64-bit machines, the next member, ``__u64 data_ptr``, wants to
+ * be 8-byte aligned. Make sure this struct is the same size when
+ * built for 32-bit.
+ */
+ __u32 __pad;
+
+ /* DAT buffer */
+ __u64 data_ptr;
+};
+#define mmc_ioc_cmd_set_data(ic, ptr) ic.data_ptr = (__u64)(unsigned long) ptr
+
+#define MMC_IOC_CMD _IOWR(MMC_BLOCK_MAJOR, 0, struct mmc_ioc_cmd)
+
+/*
+ * Since this ioctl is only meant to enhance (and not replace) normal access
+ * to the mmc bus device, an upper data transfer limit of MMC_IOC_MAX_BYTES
+ * is enforced per ioctl call. For larger data transfers, use the normal
+ * block device operations.
+ */
+#define MMC_IOC_MAX_BYTES (512L * 256)
+#endif /* LINUX_MMC_IOCTL_H */
diff --git a/include/linux/mmc/mmc.h b/include/linux/mmc/mmc.h
index 264ba54..ac26a68 100644
--- a/include/linux/mmc/mmc.h
+++ b/include/linux/mmc/mmc.h
@@ -50,6 +50,7 @@
#define MMC_SET_BLOCKLEN 16 /* ac [31:0] block len R1 */
#define MMC_READ_SINGLE_BLOCK 17 /* adtc [31:0] data addr R1 */
#define MMC_READ_MULTIPLE_BLOCK 18 /* adtc [31:0] data addr R1 */
+#define MMC_SEND_TUNING_BLOCK 19 /* adtc R1 */
/* class 3 */
#define MMC_WRITE_DAT_UNTIL_STOP 20 /* adtc [31:0] data addr R1 */
@@ -82,6 +83,12 @@
#define MMC_APP_CMD 55 /* ac [31:16] RCA R1 */
#define MMC_GEN_CMD 56 /* adtc [0] RD/WR R1 */
+static inline bool mmc_op_multi(u32 opcode)
+{
+ return opcode == MMC_WRITE_MULTIPLE_BLOCK ||
+ opcode == MMC_READ_MULTIPLE_BLOCK;
+}
+
/*
* MMC_SWITCH argument format:
*
@@ -255,18 +262,23 @@
#define EXT_CSD_PARTITION_ATTRIBUTE 156 /* R/W */
#define EXT_CSD_PARTITION_SUPPORT 160 /* RO */
+#define EXT_CSD_WR_REL_PARAM 166 /* RO */
#define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */
+#define EXT_CSD_PART_CONFIG 179 /* R/W */
#define EXT_CSD_ERASED_MEM_CONT 181 /* RO */
#define EXT_CSD_BUS_WIDTH 183 /* R/W */
#define EXT_CSD_HS_TIMING 185 /* R/W */
#define EXT_CSD_REV 192 /* RO */
#define EXT_CSD_STRUCTURE 194 /* RO */
#define EXT_CSD_CARD_TYPE 196 /* RO */
+#define EXT_CSD_PART_SWITCH_TIME 199 /* RO */
#define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
#define EXT_CSD_S_A_TIMEOUT 217 /* RO */
+#define EXT_CSD_REL_WR_SEC_C 222 /* RO */
#define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */
#define EXT_CSD_ERASE_TIMEOUT_MULT 223 /* RO */
#define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
+#define EXT_CSD_BOOT_MULT 226 /* RO */
#define EXT_CSD_SEC_TRIM_MULT 229 /* RO */
#define EXT_CSD_SEC_ERASE_MULT 230 /* RO */
#define EXT_CSD_SEC_FEATURE_SUPPORT 231 /* RO */
@@ -276,6 +288,12 @@
* EXT_CSD field definitions
*/
+#define EXT_CSD_WR_REL_PARAM_EN (1<<2)
+
+#define EXT_CSD_PART_CONFIG_ACC_MASK (0x7)
+#define EXT_CSD_PART_CONFIG_ACC_BOOT0 (0x1)
+#define EXT_CSD_PART_CONFIG_ACC_BOOT1 (0x2)
+
#define EXT_CSD_CMD_SET_NORMAL (1<<0)
#define EXT_CSD_CMD_SET_SECURE (1<<1)
#define EXT_CSD_CMD_SET_CPSECURE (1<<2)
diff --git a/include/linux/mmc/sd.h b/include/linux/mmc/sd.h
index 3fd85e0..7d35d52 100644
--- a/include/linux/mmc/sd.h
+++ b/include/linux/mmc/sd.h
@@ -17,6 +17,7 @@
/* This is basically the same command as for MMC with some quirks. */
#define SD_SEND_RELATIVE_ADDR 3 /* bcr R6 */
#define SD_SEND_IF_COND 8 /* bcr [11:0] See below R7 */
+#define SD_SWITCH_VOLTAGE 11 /* ac R1 */
/* class 10 */
#define SD_SWITCH 6 /* adtc [31:0] See below R1 */
@@ -32,6 +33,12 @@
#define SD_APP_OP_COND 41 /* bcr [31:0] OCR R3 */
#define SD_APP_SEND_SCR 51 /* adtc R1 */
+/* OCR bit definitions */
+#define SD_OCR_S18R (1 << 24) /* 1.8V switching request */
+#define SD_ROCR_S18A SD_OCR_S18R /* 1.8V switching accepted by card */
+#define SD_OCR_XPC (1 << 28) /* SDXC power control */
+#define SD_OCR_CCS (1 << 30) /* Card Capacity Status */
+
/*
* SD_SWITCH argument format:
*
@@ -59,7 +66,7 @@
#define SCR_SPEC_VER_0 0 /* Implements system specification 1.0 - 1.01 */
#define SCR_SPEC_VER_1 1 /* Implements system specification 1.10 */
-#define SCR_SPEC_VER_2 2 /* Implements system specification 2.00 */
+#define SCR_SPEC_VER_2 2 /* Implements system specification 2.00-3.0X */
/*
* SD bus widths
diff --git a/include/linux/mmc/sdhci.h b/include/linux/mmc/sdhci.h
index 83bd9f7..6a68c4e 100644
--- a/include/linux/mmc/sdhci.h
+++ b/include/linux/mmc/sdhci.h
@@ -85,6 +85,8 @@
#define SDHCI_QUIRK_NO_HISPD_BIT (1<<29)
/* Controller treats ADMA descriptors with length 0000h incorrectly */
#define SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC (1<<30)
+/* The read-only detection via SDHCI_PRESENT_STATE register is unstable */
+#define SDHCI_QUIRK_UNSTABLE_RO_DETECT (1<<31)
int irq; /* Device IRQ */
void __iomem *ioaddr; /* Mapped address */
@@ -109,11 +111,16 @@
#define SDHCI_USE_ADMA (1<<1) /* Host is ADMA capable */
#define SDHCI_REQ_USE_DMA (1<<2) /* Use DMA for this req. */
#define SDHCI_DEVICE_DEAD (1<<3) /* Device unresponsive */
+#define SDHCI_SDR50_NEEDS_TUNING (1<<4) /* SDR50 needs tuning */
+#define SDHCI_NEEDS_RETUNING (1<<5) /* Host needs retuning */
+#define SDHCI_AUTO_CMD12 (1<<6) /* Auto CMD12 support */
+#define SDHCI_AUTO_CMD23 (1<<7) /* Auto CMD23 support */
unsigned int version; /* SDHCI spec. version */
unsigned int max_clk; /* Max possible freq (MHz) */
unsigned int timeout_clk; /* Timeout freq (KHz) */
+ unsigned int clk_mul; /* Clock Muliplier value */
unsigned int clock; /* Current clock (MHz) */
u8 pwr; /* Current voltage */
@@ -145,6 +152,14 @@
unsigned int ocr_avail_sd;
unsigned int ocr_avail_mmc;
+ wait_queue_head_t buf_ready_int; /* Waitqueue for Buffer Read Ready interrupt */
+ unsigned int tuning_done; /* Condition flag set when CMD19 succeeds */
+
+ unsigned int tuning_count; /* Timer count for re-tuning */
+ unsigned int tuning_mode; /* Re-tuning mode supported by host */
+#define SDHCI_TUNING_MODE_1 0
+ struct timer_list tuning_timer; /* Timer for tuning */
+
unsigned long private[0] ____cacheline_aligned;
};
#endif /* __SDHCI_H */
diff --git a/include/linux/mmc/sh_mobile_sdhi.h b/include/linux/mmc/sh_mobile_sdhi.h
index c981b95..faf32b6 100644
--- a/include/linux/mmc/sh_mobile_sdhi.h
+++ b/include/linux/mmc/sh_mobile_sdhi.h
@@ -3,12 +3,16 @@
#include <linux/types.h>
+struct platform_device;
+struct tmio_mmc_data;
+
struct sh_mobile_sdhi_info {
int dma_slave_tx;
int dma_slave_rx;
unsigned long tmio_flags;
unsigned long tmio_caps;
u32 tmio_ocr_mask; /* available MMC voltages */
+ struct tmio_mmc_data *pdata;
void (*set_pwr)(struct platform_device *pdev, int state);
int (*get_cd)(struct platform_device *pdev);
};
diff --git a/include/linux/mmu_notifier.h b/include/linux/mmu_notifier.h
index cc2e7df..1d1b1e1 100644
--- a/include/linux/mmu_notifier.h
+++ b/include/linux/mmu_notifier.h
@@ -150,7 +150,7 @@
* Therefore notifier chains can only be traversed when either
*
* 1. mmap_sem is held.
- * 2. One of the reverse map locks is held (i_mmap_lock or anon_vma->lock).
+ * 2. One of the reverse map locks is held (i_mmap_mutex or anon_vma->mutex).
* 3. No other concurrent thread can access the list (release)
*/
struct mmu_notifier {
diff --git a/include/linux/mmzone.h b/include/linux/mmzone.h
index e56f835..217bcf6 100644
--- a/include/linux/mmzone.h
+++ b/include/linux/mmzone.h
@@ -928,9 +928,6 @@
#define pfn_to_nid(pfn) (0)
#endif
-#define pfn_to_section_nr(pfn) ((pfn) >> PFN_SECTION_SHIFT)
-#define section_nr_to_pfn(sec) ((sec) << PFN_SECTION_SHIFT)
-
#ifdef CONFIG_SPARSEMEM
/*
@@ -956,6 +953,12 @@
#error Allocator MAX_ORDER exceeds SECTION_SIZE
#endif
+#define pfn_to_section_nr(pfn) ((pfn) >> PFN_SECTION_SHIFT)
+#define section_nr_to_pfn(sec) ((sec) << PFN_SECTION_SHIFT)
+
+#define SECTION_ALIGN_UP(pfn) (((pfn) + PAGES_PER_SECTION - 1) & PAGE_SECTION_MASK)
+#define SECTION_ALIGN_DOWN(pfn) ((pfn) & PAGE_SECTION_MASK)
+
struct page;
struct page_cgroup;
struct mem_section {
diff --git a/include/linux/mtd/physmap.h b/include/linux/mtd/physmap.h
index bcfd9f7..49b9590 100644
--- a/include/linux/mtd/physmap.h
+++ b/include/linux/mtd/physmap.h
@@ -22,7 +22,9 @@
struct physmap_flash_data {
unsigned int width;
- void (*set_vpp)(struct map_info *, int);
+ int (*init)(struct platform_device *);
+ void (*exit)(struct platform_device *);
+ void (*set_vpp)(struct platform_device *, int);
unsigned int nr_parts;
unsigned int pfow_base;
char *probe_type;
diff --git a/include/linux/mtd/ubi.h b/include/linux/mtd/ubi.h
index 84854ed..15da0e9 100644
--- a/include/linux/mtd/ubi.h
+++ b/include/linux/mtd/ubi.h
@@ -21,7 +21,7 @@
#ifndef __LINUX_UBI_H__
#define __LINUX_UBI_H__
-#include <asm/ioctl.h>
+#include <linux/ioctl.h>
#include <linux/types.h>
#include <mtd/ubi-user.h>
@@ -87,7 +87,7 @@
* physical eraseblock size and on how much bytes UBI headers consume. But
* because of the volume alignment (@alignment), the usable size of logical
* eraseblocks if a volume may be less. The following equation is true:
- * @usable_leb_size = LEB size - (LEB size mod @alignment),
+ * @usable_leb_size = LEB size - (LEB size mod @alignment),
* where LEB size is the logical eraseblock size defined by the UBI device.
*
* The alignment is multiple to the minimal flash input/output unit size or %1
diff --git a/include/linux/mutex.h b/include/linux/mutex.h
index c75471d..a940fe4 100644
--- a/include/linux/mutex.h
+++ b/include/linux/mutex.h
@@ -132,6 +132,7 @@
*/
#ifdef CONFIG_DEBUG_LOCK_ALLOC
extern void mutex_lock_nested(struct mutex *lock, unsigned int subclass);
+extern void _mutex_lock_nest_lock(struct mutex *lock, struct lockdep_map *nest_lock);
extern int __must_check mutex_lock_interruptible_nested(struct mutex *lock,
unsigned int subclass);
extern int __must_check mutex_lock_killable_nested(struct mutex *lock,
@@ -140,6 +141,13 @@
#define mutex_lock(lock) mutex_lock_nested(lock, 0)
#define mutex_lock_interruptible(lock) mutex_lock_interruptible_nested(lock, 0)
#define mutex_lock_killable(lock) mutex_lock_killable_nested(lock, 0)
+
+#define mutex_lock_nest_lock(lock, nest_lock) \
+do { \
+ typecheck(struct lockdep_map *, &(nest_lock)->dep_map); \
+ _mutex_lock_nest_lock(lock, &(nest_lock)->dep_map); \
+} while (0)
+
#else
extern void mutex_lock(struct mutex *lock);
extern int __must_check mutex_lock_interruptible(struct mutex *lock);
@@ -148,6 +156,7 @@
# define mutex_lock_nested(lock, subclass) mutex_lock(lock)
# define mutex_lock_interruptible_nested(lock, subclass) mutex_lock_interruptible(lock)
# define mutex_lock_killable_nested(lock, subclass) mutex_lock_killable(lock)
+# define mutex_lock_nest_lock(lock, nest_lock) mutex_lock(lock)
#endif
/*
diff --git a/include/linux/mxm-wmi.h b/include/linux/mxm-wmi.h
new file mode 100644
index 0000000..617a295
--- /dev/null
+++ b/include/linux/mxm-wmi.h
@@ -0,0 +1,33 @@
+/*
+ * MXM WMI driver
+ *
+ * Copyright(C) 2010 Red Hat.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef MXM_WMI_H
+#define MXM_WMI_H
+
+/* discrete adapters */
+#define MXM_MXDS_ADAPTER_0 0x0
+#define MXM_MXDS_ADAPTER_1 0x0
+/* integrated adapter */
+#define MXM_MXDS_ADAPTER_IGD 0x10
+int mxm_wmi_call_mxds(int adapter);
+int mxm_wmi_call_mxmx(int adapter);
+bool mxm_wmi_supported(void);
+
+#endif
diff --git a/include/linux/oom.h b/include/linux/oom.h
index 5e3aa83..4952fb8 100644
--- a/include/linux/oom.h
+++ b/include/linux/oom.h
@@ -40,6 +40,8 @@
CONSTRAINT_MEMCG,
};
+extern int test_set_oom_score_adj(int new_val);
+
extern unsigned int oom_badness(struct task_struct *p, struct mem_cgroup *mem,
const nodemask_t *nodemask, unsigned long totalpages);
extern int try_set_zonelist_oom(struct zonelist *zonelist, gfp_t gfp_flags);
diff --git a/include/linux/page-flags.h b/include/linux/page-flags.h
index 811183d..79a6700 100644
--- a/include/linux/page-flags.h
+++ b/include/linux/page-flags.h
@@ -308,7 +308,7 @@
{
#ifdef CONFIG_S390
if (!test_and_set_bit(PG_uptodate, &page->flags))
- page_clear_dirty(page, 0);
+ page_set_storage_key(page_to_pfn(page), PAGE_DEFAULT_KEY, 0);
#else
/*
* Memory barrier must be issued before setting the PG_uptodate bit,
diff --git a/include/linux/pagemap.h b/include/linux/pagemap.h
index c119506..716875e 100644
--- a/include/linux/pagemap.h
+++ b/include/linux/pagemap.h
@@ -219,6 +219,12 @@
return __page_cache_alloc(mapping_gfp_mask(x)|__GFP_COLD);
}
+static inline struct page *page_cache_alloc_readahead(struct address_space *x)
+{
+ return __page_cache_alloc(mapping_gfp_mask(x) |
+ __GFP_COLD | __GFP_NORETRY | __GFP_NOWARN);
+}
+
typedef int filler_t(void *, struct page *);
extern struct page * find_get_page(struct address_space *mapping,
@@ -357,6 +363,15 @@
*/
extern void wait_on_page_bit(struct page *page, int bit_nr);
+extern int wait_on_page_bit_killable(struct page *page, int bit_nr);
+
+static inline int wait_on_page_locked_killable(struct page *page)
+{
+ if (PageLocked(page))
+ return wait_on_page_bit_killable(page, PG_locked);
+ return 0;
+}
+
/*
* Wait for a page to be unlocked.
*
diff --git a/include/linux/pci-aspm.h b/include/linux/pci-aspm.h
index 67cb3ae..7cea7b6 100644
--- a/include/linux/pci-aspm.h
+++ b/include/linux/pci-aspm.h
@@ -28,6 +28,7 @@
extern void pcie_aspm_pm_state_change(struct pci_dev *pdev);
extern void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
extern void pci_disable_link_state(struct pci_dev *pdev, int state);
+extern void pci_disable_link_state_locked(struct pci_dev *pdev, int state);
extern void pcie_clear_aspm(void);
extern void pcie_no_aspm(void);
#else
diff --git a/include/linux/pci.h b/include/linux/pci.h
index 96f70d7..c446b5c 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -214,10 +214,15 @@
PCI_SPEED_UNKNOWN = 0xff,
};
+struct pci_cap_saved_data {
+ char cap_nr;
+ unsigned int size;
+ u32 data[0];
+};
+
struct pci_cap_saved_state {
struct hlist_node next;
- char cap_nr;
- u32 data[0];
+ struct pci_cap_saved_data cap;
};
struct pcie_link_state;
@@ -366,7 +371,7 @@
struct hlist_node *pos;
hlist_for_each_entry(tmp, pos, &pci_dev->saved_cap_space, next) {
- if (tmp->cap_nr == cap)
+ if (tmp->cap.cap_nr == cap)
return tmp;
}
return NULL;
@@ -807,6 +812,10 @@
/* Power management related routines */
int pci_save_state(struct pci_dev *dev);
void pci_restore_state(struct pci_dev *dev);
+struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev);
+int pci_load_saved_state(struct pci_dev *dev, struct pci_saved_state *state);
+int pci_load_and_free_saved_state(struct pci_dev *dev,
+ struct pci_saved_state **state);
int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state);
int pci_set_power_state(struct pci_dev *dev, pci_power_t state);
pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state);
@@ -828,6 +837,23 @@
return __pci_enable_wake(dev, state, false, enable);
}
+#define PCI_EXP_IDO_REQUEST (1<<0)
+#define PCI_EXP_IDO_COMPLETION (1<<1)
+void pci_enable_ido(struct pci_dev *dev, unsigned long type);
+void pci_disable_ido(struct pci_dev *dev, unsigned long type);
+
+enum pci_obff_signal_type {
+ PCI_EXP_OBFF_SIGNAL_L0,
+ PCI_EXP_OBFF_SIGNAL_ALWAYS,
+};
+int pci_enable_obff(struct pci_dev *dev, enum pci_obff_signal_type);
+void pci_disable_obff(struct pci_dev *dev);
+
+bool pci_ltr_supported(struct pci_dev *dev);
+int pci_enable_ltr(struct pci_dev *dev);
+void pci_disable_ltr(struct pci_dev *dev);
+int pci_set_ltr(struct pci_dev *dev, int snoop_lat_ns, int nosnoop_lat_ns);
+
/* For use by arch with custom probe code */
void set_pcie_port_type(struct pci_dev *pdev);
void set_pcie_hotplug_bridge(struct pci_dev *pdev);
@@ -915,8 +941,11 @@
int pci_cfg_space_size(struct pci_dev *dev);
unsigned char pci_bus_max_busnr(struct pci_bus *bus);
+#define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0)
+#define PCI_VGA_STATE_CHANGE_DECODES (1 << 1)
+
int pci_set_vga_state(struct pci_dev *pdev, bool decode,
- unsigned int command_bits, bool change_bridge);
+ unsigned int command_bits, u32 flags);
/* kmem_cache style wrapper around pci_alloc_consistent() */
#include <linux/pci-dma.h>
@@ -1061,7 +1090,7 @@
/* some architectures require additional setup to direct VGA traffic */
typedef int (*arch_set_vga_state_t)(struct pci_dev *pdev, bool decode,
- unsigned int command_bits, bool change_bridge);
+ unsigned int command_bits, u32 flags);
extern void pci_register_set_vga_state(arch_set_vga_state_t func);
#else /* CONFIG_PCI is not enabled */
@@ -1207,6 +1236,23 @@
return 0;
}
+static inline void pci_enable_ido(struct pci_dev *dev, unsigned long type)
+{
+}
+
+static inline void pci_disable_ido(struct pci_dev *dev, unsigned long type)
+{
+}
+
+static inline int pci_enable_obff(struct pci_dev *dev, unsigned long type)
+{
+ return 0;
+}
+
+static inline void pci_disable_obff(struct pci_dev *dev)
+{
+}
+
static inline int pci_request_regions(struct pci_dev *dev, const char *res_name)
{
return -EIO;
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index 8652a4f..24787b7 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -2483,6 +2483,8 @@
#define PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX 0x1c5f
#define PCI_DEVICE_ID_INTEL_PATSBURG_LPC_0 0x1d40
#define PCI_DEVICE_ID_INTEL_PATSBURG_LPC_1 0x1d41
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN 0x1e40
+#define PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX 0x1e5f
#define PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MIN 0x2310
#define PCI_DEVICE_ID_INTEL_DH89XXCC_LPC_MAX 0x231f
#define PCI_DEVICE_ID_INTEL_82801AA_0 0x2410
diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h
index be01380..e884096 100644
--- a/include/linux/pci_regs.h
+++ b/include/linux/pci_regs.h
@@ -508,8 +508,18 @@
#define PCI_EXP_RTSTA_PENDING 0x20000 /* PME pending */
#define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */
#define PCI_EXP_DEVCAP2_ARI 0x20 /* Alternative Routing-ID */
+#define PCI_EXP_DEVCAP2_LTR 0x800 /* Latency tolerance reporting */
+#define PCI_EXP_OBFF_MASK 0xc0000 /* OBFF support mechanism */
+#define PCI_EXP_OBFF_MSG 0x40000 /* New message signaling */
+#define PCI_EXP_OBFF_WAKE 0x80000 /* Re-use WAKE# for OBFF */
#define PCI_EXP_DEVCTL2 40 /* Device Control 2 */
#define PCI_EXP_DEVCTL2_ARI 0x20 /* Alternative Routing-ID */
+#define PCI_EXP_IDO_REQ_EN 0x100 /* ID-based ordering request enable */
+#define PCI_EXP_IDO_CMP_EN 0x200 /* ID-based ordering completion enable */
+#define PCI_EXP_LTR_EN 0x400 /* Latency tolerance reporting */
+#define PCI_EXP_OBFF_MSGA_EN 0x2000 /* OBFF enable with Message type A */
+#define PCI_EXP_OBFF_MSGB_EN 0x4000 /* OBFF enable with Message type B */
+#define PCI_EXP_OBFF_WAKE_EN 0x6000 /* OBFF using WAKE# signaling */
#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */
#define PCI_EXP_SLTCTL2 56 /* Slot Control 2 */
@@ -527,6 +537,7 @@
#define PCI_EXT_CAP_ID_ARI 14
#define PCI_EXT_CAP_ID_ATS 15
#define PCI_EXT_CAP_ID_SRIOV 16
+#define PCI_EXT_CAP_ID_LTR 24
/* Advanced Error Reporting */
#define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */
@@ -683,6 +694,12 @@
#define PCI_SRIOV_VFM_MO 0x2 /* Active.MigrateOut */
#define PCI_SRIOV_VFM_AV 0x3 /* Active.Available */
+#define PCI_LTR_MAX_SNOOP_LAT 0x4
+#define PCI_LTR_MAX_NOSNOOP_LAT 0x6
+#define PCI_LTR_VALUE_MASK 0x000003ff
+#define PCI_LTR_SCALE_MASK 0x00001c00
+#define PCI_LTR_SCALE_SHIFT 10
+
/* Access Control Service */
#define PCI_ACS_CAP 0x04 /* ACS Capability Register */
#define PCI_ACS_SV 0x01 /* Source Validation */
diff --git a/include/linux/percpu_counter.h b/include/linux/percpu_counter.h
index 46f6ba5..5edc901 100644
--- a/include/linux/percpu_counter.h
+++ b/include/linux/percpu_counter.h
@@ -75,7 +75,7 @@
barrier(); /* Prevent reloads of fbc->count */
if (ret >= 0)
return ret;
- return 1;
+ return 0;
}
static inline int percpu_counter_initialized(struct percpu_counter *fbc)
@@ -133,6 +133,10 @@
return fbc->count;
}
+/*
+ * percpu_counter is intended to track positive numbers. In the UP case the
+ * number should never be negative.
+ */
static inline s64 percpu_counter_read_positive(struct percpu_counter *fbc)
{
return fbc->count;
diff --git a/include/linux/posix-timers.h b/include/linux/posix-timers.h
index 808227d..959c141 100644
--- a/include/linux/posix-timers.h
+++ b/include/linux/posix-timers.h
@@ -82,6 +82,7 @@
unsigned long expires;
} mmtimer;
struct alarm alarmtimer;
+ struct rcu_head rcu;
} it;
};
diff --git a/include/linux/printk.h b/include/linux/printk.h
index ee048e7..0101d55 100644
--- a/include/linux/printk.h
+++ b/include/linux/printk.h
@@ -1,6 +1,8 @@
#ifndef __KERNEL_PRINTK__
#define __KERNEL_PRINTK__
+#include <linux/init.h>
+
extern const char linux_banner[];
extern const char linux_proc_banner[];
@@ -113,6 +115,7 @@
extern int kptr_restrict;
void log_buf_kexec_setup(void);
+void __init setup_log_buf(int early);
#else
static inline __attribute__ ((format (printf, 1, 0)))
int vprintk(const char *s, va_list args)
@@ -137,6 +140,10 @@
static inline void log_buf_kexec_setup(void)
{
}
+
+static inline void setup_log_buf(int early)
+{
+}
#endif
extern void dump_stack(void) __cold;
diff --git a/include/linux/proc_fs.h b/include/linux/proc_fs.h
index eaf4350..3686cd6 100644
--- a/include/linux/proc_fs.h
+++ b/include/linux/proc_fs.h
@@ -288,12 +288,4 @@
return pde->parent->data;
}
-struct proc_maps_private {
- struct pid *pid;
- struct task_struct *task;
-#ifdef CONFIG_MMU
- struct vm_area_struct *tail_vma;
-#endif
-};
-
#endif /* _LINUX_PROC_FS_H */
diff --git a/include/linux/pti.h b/include/linux/pti.h
new file mode 100644
index 0000000..81af667
--- /dev/null
+++ b/include/linux/pti.h
@@ -0,0 +1,42 @@
+/*
+ * Copyright (C) Intel 2011
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ * The PTI (Parallel Trace Interface) driver directs trace data routed from
+ * various parts in the system out through the Intel Penwell PTI port and
+ * out of the mobile device for analysis with a debugging tool
+ * (Lauterbach, Fido). This is part of a solution for the MIPI P1149.7,
+ * compact JTAG, standard.
+ *
+ * This header file will allow other parts of the OS to use the
+ * interface to write out it's contents for debugging a mobile system.
+ */
+
+#ifndef PTI_H_
+#define PTI_H_
+
+/* offset for last dword of any PTI message. Part of MIPI P1149.7 */
+#define PTI_LASTDWORD_DTS 0x30
+
+/* basic structure used as a write address to the PTI HW */
+struct pti_masterchannel {
+ u8 master;
+ u8 channel;
+};
+
+/* the following functions are defined in misc/pti.c */
+void pti_writedata(struct pti_masterchannel *mc, u8 *buf, int count);
+struct pti_masterchannel *pti_request_masterchannel(u8 type);
+void pti_release_masterchannel(struct pti_masterchannel *mc);
+
+#endif /*PTI_H_*/
diff --git a/include/linux/ptp_classify.h b/include/linux/ptp_classify.h
index 943a85a..e07e274 100644
--- a/include/linux/ptp_classify.h
+++ b/include/linux/ptp_classify.h
@@ -25,6 +25,7 @@
#include <linux/if_ether.h>
#include <linux/if_vlan.h>
+#include <linux/ip.h>
#include <linux/filter.h>
#ifdef __KERNEL__
#include <linux/in.h>
@@ -58,6 +59,12 @@
#define OFF_NEXT 6
#define OFF_UDP_DST 2
+#define OFF_PTP_SOURCE_UUID 22 /* PTPv1 only */
+#define OFF_PTP_SEQUENCE_ID 30
+#define OFF_PTP_CONTROL 32 /* PTPv1 only */
+
+#define IPV4_HLEN(data) (((struct iphdr *)(data + OFF_IHL))->ihl << 2)
+
#define IP6_HLEN 40
#define UDP_HLEN 8
diff --git a/include/linux/ptp_clock.h b/include/linux/ptp_clock.h
new file mode 100644
index 0000000..94e981f
--- /dev/null
+++ b/include/linux/ptp_clock.h
@@ -0,0 +1,84 @@
+/*
+ * PTP 1588 clock support - user space interface
+ *
+ * Copyright (C) 2010 OMICRON electronics GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef _PTP_CLOCK_H_
+#define _PTP_CLOCK_H_
+
+#include <linux/ioctl.h>
+#include <linux/types.h>
+
+/* PTP_xxx bits, for the flags field within the request structures. */
+#define PTP_ENABLE_FEATURE (1<<0)
+#define PTP_RISING_EDGE (1<<1)
+#define PTP_FALLING_EDGE (1<<2)
+
+/*
+ * struct ptp_clock_time - represents a time value
+ *
+ * The sign of the seconds field applies to the whole value. The
+ * nanoseconds field is always unsigned. The reserved field is
+ * included for sub-nanosecond resolution, should the demand for
+ * this ever appear.
+ *
+ */
+struct ptp_clock_time {
+ __s64 sec; /* seconds */
+ __u32 nsec; /* nanoseconds */
+ __u32 reserved;
+};
+
+struct ptp_clock_caps {
+ int max_adj; /* Maximum frequency adjustment in parts per billon. */
+ int n_alarm; /* Number of programmable alarms. */
+ int n_ext_ts; /* Number of external time stamp channels. */
+ int n_per_out; /* Number of programmable periodic signals. */
+ int pps; /* Whether the clock supports a PPS callback. */
+ int rsv[15]; /* Reserved for future use. */
+};
+
+struct ptp_extts_request {
+ unsigned int index; /* Which channel to configure. */
+ unsigned int flags; /* Bit field for PTP_xxx flags. */
+ unsigned int rsv[2]; /* Reserved for future use. */
+};
+
+struct ptp_perout_request {
+ struct ptp_clock_time start; /* Absolute start time. */
+ struct ptp_clock_time period; /* Desired period, zero means disable. */
+ unsigned int index; /* Which channel to configure. */
+ unsigned int flags; /* Reserved for future use. */
+ unsigned int rsv[4]; /* Reserved for future use. */
+};
+
+#define PTP_CLK_MAGIC '='
+
+#define PTP_CLOCK_GETCAPS _IOR(PTP_CLK_MAGIC, 1, struct ptp_clock_caps)
+#define PTP_EXTTS_REQUEST _IOW(PTP_CLK_MAGIC, 2, struct ptp_extts_request)
+#define PTP_PEROUT_REQUEST _IOW(PTP_CLK_MAGIC, 3, struct ptp_perout_request)
+#define PTP_ENABLE_PPS _IOW(PTP_CLK_MAGIC, 4, int)
+
+struct ptp_extts_event {
+ struct ptp_clock_time t; /* Time event occured. */
+ unsigned int index; /* Which channel produced the event. */
+ unsigned int flags; /* Reserved for future use. */
+ unsigned int rsv[2]; /* Reserved for future use. */
+};
+
+#endif
diff --git a/include/linux/ptp_clock_kernel.h b/include/linux/ptp_clock_kernel.h
new file mode 100644
index 0000000..dd2e44f
--- /dev/null
+++ b/include/linux/ptp_clock_kernel.h
@@ -0,0 +1,139 @@
+/*
+ * PTP 1588 clock support
+ *
+ * Copyright (C) 2010 OMICRON electronics GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef _PTP_CLOCK_KERNEL_H_
+#define _PTP_CLOCK_KERNEL_H_
+
+#include <linux/ptp_clock.h>
+
+
+struct ptp_clock_request {
+ enum {
+ PTP_CLK_REQ_EXTTS,
+ PTP_CLK_REQ_PEROUT,
+ PTP_CLK_REQ_PPS,
+ } type;
+ union {
+ struct ptp_extts_request extts;
+ struct ptp_perout_request perout;
+ };
+};
+
+/**
+ * struct ptp_clock_info - decribes a PTP hardware clock
+ *
+ * @owner: The clock driver should set to THIS_MODULE.
+ * @name: A short name to identify the clock.
+ * @max_adj: The maximum possible frequency adjustment, in parts per billon.
+ * @n_alarm: The number of programmable alarms.
+ * @n_ext_ts: The number of external time stamp channels.
+ * @n_per_out: The number of programmable periodic signals.
+ * @pps: Indicates whether the clock supports a PPS callback.
+ *
+ * clock operations
+ *
+ * @adjfreq: Adjusts the frequency of the hardware clock.
+ * parameter delta: Desired period change in parts per billion.
+ *
+ * @adjtime: Shifts the time of the hardware clock.
+ * parameter delta: Desired change in nanoseconds.
+ *
+ * @gettime: Reads the current time from the hardware clock.
+ * parameter ts: Holds the result.
+ *
+ * @settime: Set the current time on the hardware clock.
+ * parameter ts: Time value to set.
+ *
+ * @enable: Request driver to enable or disable an ancillary feature.
+ * parameter request: Desired resource to enable or disable.
+ * parameter on: Caller passes one to enable or zero to disable.
+ *
+ * Drivers should embed their ptp_clock_info within a private
+ * structure, obtaining a reference to it using container_of().
+ *
+ * The callbacks must all return zero on success, non-zero otherwise.
+ */
+
+struct ptp_clock_info {
+ struct module *owner;
+ char name[16];
+ s32 max_adj;
+ int n_alarm;
+ int n_ext_ts;
+ int n_per_out;
+ int pps;
+ int (*adjfreq)(struct ptp_clock_info *ptp, s32 delta);
+ int (*adjtime)(struct ptp_clock_info *ptp, s64 delta);
+ int (*gettime)(struct ptp_clock_info *ptp, struct timespec *ts);
+ int (*settime)(struct ptp_clock_info *ptp, const struct timespec *ts);
+ int (*enable)(struct ptp_clock_info *ptp,
+ struct ptp_clock_request *request, int on);
+};
+
+struct ptp_clock;
+
+/**
+ * ptp_clock_register() - register a PTP hardware clock driver
+ *
+ * @info: Structure describing the new clock.
+ */
+
+extern struct ptp_clock *ptp_clock_register(struct ptp_clock_info *info);
+
+/**
+ * ptp_clock_unregister() - unregister a PTP hardware clock driver
+ *
+ * @ptp: The clock to remove from service.
+ */
+
+extern int ptp_clock_unregister(struct ptp_clock *ptp);
+
+
+enum ptp_clock_events {
+ PTP_CLOCK_ALARM,
+ PTP_CLOCK_EXTTS,
+ PTP_CLOCK_PPS,
+};
+
+/**
+ * struct ptp_clock_event - decribes a PTP hardware clock event
+ *
+ * @type: One of the ptp_clock_events enumeration values.
+ * @index: Identifies the source of the event.
+ * @timestamp: When the event occured.
+ */
+
+struct ptp_clock_event {
+ int type;
+ int index;
+ u64 timestamp;
+};
+
+/**
+ * ptp_clock_event() - notify the PTP layer about an event
+ *
+ * @ptp: The clock obtained from ptp_clock_register().
+ * @event: Message structure describing the event.
+ */
+
+extern void ptp_clock_event(struct ptp_clock *ptp,
+ struct ptp_clock_event *event);
+
+#endif
diff --git a/include/linux/regulator/db8500-prcmu.h b/include/linux/regulator/db8500-prcmu.h
new file mode 100644
index 0000000..6120623
--- /dev/null
+++ b/include/linux/regulator/db8500-prcmu.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright (C) ST-Ericsson SA 2010
+ *
+ * License Terms: GNU General Public License v2
+ *
+ * Author: Bengt Jonsson <bengt.g.jonsson@stericsson.com> for ST-Ericsson
+ *
+ * Interface to power domain regulators on DB8500
+ */
+
+#ifndef __REGULATOR_H__
+#define __REGULATOR_H__
+
+/* Number of DB8500 regulators and regulator enumeration */
+enum db8500_regulator_id {
+ DB8500_REGULATOR_VAPE,
+ DB8500_REGULATOR_VARM,
+ DB8500_REGULATOR_VMODEM,
+ DB8500_REGULATOR_VPLL,
+ DB8500_REGULATOR_VSMPS1,
+ DB8500_REGULATOR_VSMPS2,
+ DB8500_REGULATOR_VSMPS3,
+ DB8500_REGULATOR_VRF1,
+ DB8500_REGULATOR_SWITCH_SVAMMDSP,
+ DB8500_REGULATOR_SWITCH_SVAMMDSPRET,
+ DB8500_REGULATOR_SWITCH_SVAPIPE,
+ DB8500_REGULATOR_SWITCH_SIAMMDSP,
+ DB8500_REGULATOR_SWITCH_SIAMMDSPRET,
+ DB8500_REGULATOR_SWITCH_SIAPIPE,
+ DB8500_REGULATOR_SWITCH_SGA,
+ DB8500_REGULATOR_SWITCH_B2R2_MCDE,
+ DB8500_REGULATOR_SWITCH_ESRAM12,
+ DB8500_REGULATOR_SWITCH_ESRAM12RET,
+ DB8500_REGULATOR_SWITCH_ESRAM34,
+ DB8500_REGULATOR_SWITCH_ESRAM34RET,
+ DB8500_NUM_REGULATORS
+};
+
+/*
+ * Exported interface for CPUIdle only. This function is called with all
+ * interrupts turned off.
+ */
+int power_state_active_is_enabled(void);
+
+#endif
diff --git a/include/linux/rmap.h b/include/linux/rmap.h
index 830e65d..2148b12 100644
--- a/include/linux/rmap.h
+++ b/include/linux/rmap.h
@@ -7,7 +7,7 @@
#include <linux/list.h>
#include <linux/slab.h>
#include <linux/mm.h>
-#include <linux/spinlock.h>
+#include <linux/mutex.h>
#include <linux/memcontrol.h>
/*
@@ -26,7 +26,7 @@
*/
struct anon_vma {
struct anon_vma *root; /* Root of this anon_vma tree */
- spinlock_t lock; /* Serialize access to vma list */
+ struct mutex mutex; /* Serialize access to vma list */
/*
* The refcount is taken on an anon_vma when there is no
* guarantee that the vma of page tables will exist for
@@ -64,7 +64,7 @@
struct vm_area_struct *vma;
struct anon_vma *anon_vma;
struct list_head same_vma; /* locked by mmap_sem & page_table_lock */
- struct list_head same_anon_vma; /* locked by anon_vma->lock */
+ struct list_head same_anon_vma; /* locked by anon_vma->mutex */
};
#ifdef CONFIG_MMU
@@ -93,24 +93,24 @@
{
struct anon_vma *anon_vma = vma->anon_vma;
if (anon_vma)
- spin_lock(&anon_vma->root->lock);
+ mutex_lock(&anon_vma->root->mutex);
}
static inline void vma_unlock_anon_vma(struct vm_area_struct *vma)
{
struct anon_vma *anon_vma = vma->anon_vma;
if (anon_vma)
- spin_unlock(&anon_vma->root->lock);
+ mutex_unlock(&anon_vma->root->mutex);
}
static inline void anon_vma_lock(struct anon_vma *anon_vma)
{
- spin_lock(&anon_vma->root->lock);
+ mutex_lock(&anon_vma->root->mutex);
}
static inline void anon_vma_unlock(struct anon_vma *anon_vma)
{
- spin_unlock(&anon_vma->root->lock);
+ mutex_unlock(&anon_vma->root->mutex);
}
/*
@@ -218,20 +218,7 @@
/*
* Called by memory-failure.c to kill processes.
*/
-struct anon_vma *__page_lock_anon_vma(struct page *page);
-
-static inline struct anon_vma *page_lock_anon_vma(struct page *page)
-{
- struct anon_vma *anon_vma;
-
- __cond_lock(RCU, anon_vma = __page_lock_anon_vma(page));
-
- /* (void) is needed to make gcc happy */
- (void) __cond_lock(&anon_vma->root->lock, anon_vma);
-
- return anon_vma;
-}
-
+struct anon_vma *page_lock_anon_vma(struct page *page);
void page_unlock_anon_vma(struct anon_vma *anon_vma);
int page_mapped_in_vma(struct page *page, struct vm_area_struct *vma);
diff --git a/include/linux/rotary_encoder.h b/include/linux/rotary_encoder.h
index 215278b..3f594dc 100644
--- a/include/linux/rotary_encoder.h
+++ b/include/linux/rotary_encoder.h
@@ -10,6 +10,7 @@
unsigned int inverted_b;
bool relative_axis;
bool rollover;
+ bool half_period;
};
#endif /* __ROTARY_ENCODER_H__ */
diff --git a/include/linux/sched.h b/include/linux/sched.h
index 340f5ee..f18300e 100644
--- a/include/linux/sched.h
+++ b/include/linux/sched.h
@@ -786,17 +786,39 @@
};
/*
- * sched-domains (multiprocessor balancing) declarations:
+ * Increase resolution of nice-level calculations for 64-bit architectures.
+ * The extra resolution improves shares distribution and load balancing of
+ * low-weight task groups (eg. nice +19 on an autogroup), deeper taskgroup
+ * hierarchies, especially on larger systems. This is not a user-visible change
+ * and does not change the user-interface for setting shares/weights.
+ *
+ * We increase resolution only if we have enough bits to allow this increased
+ * resolution (i.e. BITS_PER_LONG > 32). The costs for increasing resolution
+ * when BITS_PER_LONG <= 32 are pretty high and the returns do not justify the
+ * increased costs.
*/
+#if BITS_PER_LONG > 32
+# define SCHED_LOAD_RESOLUTION 10
+# define scale_load(w) ((w) << SCHED_LOAD_RESOLUTION)
+# define scale_load_down(w) ((w) >> SCHED_LOAD_RESOLUTION)
+#else
+# define SCHED_LOAD_RESOLUTION 0
+# define scale_load(w) (w)
+# define scale_load_down(w) (w)
+#endif
-/*
- * Increase resolution of nice-level calculations:
- */
-#define SCHED_LOAD_SHIFT 10
+#define SCHED_LOAD_SHIFT (10 + SCHED_LOAD_RESOLUTION)
#define SCHED_LOAD_SCALE (1L << SCHED_LOAD_SHIFT)
-#define SCHED_LOAD_SCALE_FUZZ SCHED_LOAD_SCALE
+/*
+ * Increase resolution of cpu_power calculations
+ */
+#define SCHED_POWER_SHIFT 10
+#define SCHED_POWER_SCALE (1L << SCHED_POWER_SHIFT)
+/*
+ * sched-domains (multiprocessor balancing) declarations:
+ */
#ifdef CONFIG_SMP
#define SD_LOAD_BALANCE 0x0001 /* Do load balancing on this domain. */
#define SD_BALANCE_NEWIDLE 0x0002 /* Balance when about to become idle */
@@ -1731,7 +1753,6 @@
#define PF_FROZEN 0x00010000 /* frozen for system suspend */
#define PF_FSTRANS 0x00020000 /* inside a filesystem transaction */
#define PF_KSWAPD 0x00040000 /* I am kswapd */
-#define PF_OOM_ORIGIN 0x00080000 /* Allocating much memory to others */
#define PF_LESS_THROTTLE 0x00100000 /* Throttle me less: I clean memory */
#define PF_KTHREAD 0x00200000 /* I am a kernel thread */
#define PF_RANDOMIZE 0x00400000 /* randomize virtual address space */
@@ -2155,6 +2176,7 @@
if (unlikely(atomic_dec_and_test(&mm->mm_count)))
__mmdrop(mm);
}
+extern int mm_init_cpumask(struct mm_struct *mm, struct mm_struct *oldmm);
/* mmput gets rid of the mappings and all user-space */
extern void mmput(struct mm_struct *);
diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h
index 758c5b0..a5c3114 100644
--- a/include/linux/serial_core.h
+++ b/include/linux/serial_core.h
@@ -45,7 +45,8 @@
#define PORT_OCTEON 17 /* Cavium OCTEON internal UART */
#define PORT_AR7 18 /* Texas Instruments AR7 internal UART */
#define PORT_U6_16550A 19 /* ST-Ericsson U6xxx internal UART */
-#define PORT_MAX_8250 19 /* max port ID */
+#define PORT_TEGRA 20 /* NVIDIA Tegra internal UART */
+#define PORT_MAX_8250 20 /* max port ID */
/*
* ARM specific type numbers. These are not currently guaranteed
@@ -202,6 +203,9 @@
/* VIA VT8500 SoC */
#define PORT_VT8500 97
+/* Xilinx PSS UART */
+#define PORT_XUARTPS 98
+
#ifdef __KERNEL__
#include <linux/compiler.h>
diff --git a/include/linux/serial_reg.h b/include/linux/serial_reg.h
index 3ecb71a..c75bda3 100644
--- a/include/linux/serial_reg.h
+++ b/include/linux/serial_reg.h
@@ -57,6 +57,7 @@
* ST16C654: 8 16 56 60 8 16 32 56 PORT_16654
* TI16C750: 1 16 32 56 xx xx xx xx PORT_16750
* TI16C752: 8 16 56 60 8 16 32 56
+ * Tegra: 1 4 8 14 16 8 4 1 PORT_TEGRA
*/
#define UART_FCR_R_TRIG_00 0x00
#define UART_FCR_R_TRIG_01 0x40
@@ -118,6 +119,7 @@
#define UART_MCR_DTR 0x01 /* DTR complement */
#define UART_LSR 5 /* In: Line Status Register */
+#define UART_LSR_FIFOE 0x80 /* Fifo error */
#define UART_LSR_TEMT 0x40 /* Transmitter empty */
#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
#define UART_LSR_BI 0x10 /* Break interrupt indicator */
diff --git a/include/linux/shmem_fs.h b/include/linux/shmem_fs.h
index 399be5a..2b7fec8 100644
--- a/include/linux/shmem_fs.h
+++ b/include/linux/shmem_fs.h
@@ -9,6 +9,8 @@
#define SHMEM_NR_DIRECT 16
+#define SHMEM_SYMLINK_INLINE_LEN (SHMEM_NR_DIRECT * sizeof(swp_entry_t))
+
struct shmem_inode_info {
spinlock_t lock;
unsigned long flags;
@@ -17,8 +19,12 @@
unsigned long next_index; /* highest alloced index + 1 */
struct shared_policy policy; /* NUMA memory alloc policy */
struct page *i_indirect; /* top indirect blocks page */
- swp_entry_t i_direct[SHMEM_NR_DIRECT]; /* first blocks */
+ union {
+ swp_entry_t i_direct[SHMEM_NR_DIRECT]; /* first blocks */
+ char inline_symlink[SHMEM_SYMLINK_INLINE_LEN];
+ };
struct list_head swaplist; /* chain of maybes on swap */
+ struct list_head xattr_list; /* list of shmem_xattr */
struct inode vfs_inode;
};
diff --git a/include/linux/spi/ads7846.h b/include/linux/spi/ads7846.h
index 92bd083..c64de9d 100644
--- a/include/linux/spi/ads7846.h
+++ b/include/linux/spi/ads7846.h
@@ -14,7 +14,8 @@
struct ads7846_platform_data {
u16 model; /* 7843, 7845, 7846, 7873. */
u16 vref_delay_usecs; /* 0 for external vref; etc */
- u16 vref_mv; /* external vref value, milliVolts */
+ u16 vref_mv; /* external vref value, milliVolts
+ * ads7846: if 0, use internal vref */
bool keep_vref_on; /* set to keep vref on for differential
* measurements as well */
bool swap_xy; /* swap x and y axes */
diff --git a/include/linux/thread_info.h b/include/linux/thread_info.h
index 20fc303..8d03f07 100644
--- a/include/linux/thread_info.h
+++ b/include/linux/thread_info.h
@@ -29,7 +29,7 @@
} futex;
/* For nanosleep */
struct {
- clockid_t index;
+ clockid_t clockid;
struct timespec __user *rmtp;
#ifdef CONFIG_COMPAT
struct compat_timespec __user *compat_rmtp;
diff --git a/include/linux/timerfd.h b/include/linux/timerfd.h
index 2d07929..d3b57fa 100644
--- a/include/linux/timerfd.h
+++ b/include/linux/timerfd.h
@@ -19,6 +19,7 @@
* shared O_* flags.
*/
#define TFD_TIMER_ABSTIME (1 << 0)
+#define TFD_TIMER_CANCEL_ON_SET (1 << 1)
#define TFD_CLOEXEC O_CLOEXEC
#define TFD_NONBLOCK O_NONBLOCK
@@ -26,6 +27,6 @@
/* Flags for timerfd_create. */
#define TFD_CREATE_FLAGS TFD_SHARED_FCNTL_FLAGS
/* Flags for timerfd_settime. */
-#define TFD_SETTIME_FLAGS TFD_TIMER_ABSTIME
+#define TFD_SETTIME_FLAGS (TFD_TIMER_ABSTIME | TFD_TIMER_CANCEL_ON_SET)
#endif /* _LINUX_TIMERFD_H */
diff --git a/include/linux/tty.h b/include/linux/tty.h
index 9f469c7..d6f0529 100644
--- a/include/linux/tty.h
+++ b/include/linux/tty.h
@@ -50,6 +50,8 @@
#define N_CAIF 20 /* CAIF protocol for talking to modems */
#define N_GSM0710 21 /* GSM 0710 Mux */
#define N_TI_WL 22 /* for TI's WL BT, FM, GPS combo chips */
+#define N_TRACESINK 23 /* Trace data routing for MIPI P1149.7 */
+#define N_TRACEROUTER 24 /* Trace data routing for MIPI P1149.7 */
/*
* This character is the same as _POSIX_VDISABLE: it cannot be used as
@@ -472,6 +474,7 @@
extern void free_tty_struct(struct tty_struct *tty);
extern void initialize_tty_struct(struct tty_struct *tty,
struct tty_driver *driver, int idx);
+extern void deinitialize_tty_struct(struct tty_struct *tty);
extern struct tty_struct *tty_init_dev(struct tty_driver *driver, int idx,
int first_ok);
extern int tty_release(struct inode *inode, struct file *filp);
@@ -525,6 +528,7 @@
extern int tty_ldisc_setup(struct tty_struct *tty, struct tty_struct *o_tty);
extern void tty_ldisc_release(struct tty_struct *tty, struct tty_struct *o_tty);
extern void tty_ldisc_init(struct tty_struct *tty);
+extern void tty_ldisc_deinit(struct tty_struct *tty);
extern void tty_ldisc_begin(void);
/* This last one is just for the tty layer internals and shouldn't be used elsewhere */
extern void tty_ldisc_enable(struct tty_struct *tty);
diff --git a/include/linux/tty_ldisc.h b/include/linux/tty_ldisc.h
index ff7dc08..5b07792 100644
--- a/include/linux/tty_ldisc.h
+++ b/include/linux/tty_ldisc.h
@@ -76,7 +76,7 @@
* tty device. It is solely the responsibility of the line
* discipline to handle poll requests.
*
- * void (*receive_buf)(struct tty_struct *, const unsigned char *cp,
+ * unsigned int (*receive_buf)(struct tty_struct *, const unsigned char *cp,
* char *fp, int count);
*
* This function is called by the low-level tty driver to send
@@ -84,7 +84,8 @@
* processing. <cp> is a pointer to the buffer of input
* character received by the device. <fp> is a pointer to a
* pointer of flag bytes which indicate whether a character was
- * received with a parity error, etc.
+ * received with a parity error, etc. Returns the amount of bytes
+ * received.
*
* void (*write_wakeup)(struct tty_struct *);
*
@@ -140,8 +141,8 @@
/*
* The following routines are called from below.
*/
- void (*receive_buf)(struct tty_struct *, const unsigned char *cp,
- char *fp, int count);
+ unsigned int (*receive_buf)(struct tty_struct *,
+ const unsigned char *cp, char *fp, int count);
void (*write_wakeup)(struct tty_struct *);
void (*dcd_change)(struct tty_struct *, unsigned int,
struct pps_event_time *);
diff --git a/include/linux/usb.h b/include/linux/usb.h
index 65f78ca..73c7df4 100644
--- a/include/linux/usb.h
+++ b/include/linux/usb.h
@@ -806,8 +806,10 @@
* @resume: Called when the device is being resumed by the system.
* @reset_resume: Called when the suspended device has been reset instead
* of being resumed.
- * @pre_reset: Called by usb_reset_device() when the device
- * is about to be reset.
+ * @pre_reset: Called by usb_reset_device() when the device is about to be
+ * reset. This routine must not return until the driver has no active
+ * URBs for the device, and no more URBs may be submitted until the
+ * post_reset method is called.
* @post_reset: Called by usb_reset_device() after the device
* has been reset
* @id_table: USB drivers use ID table to support hotplugging.
diff --git a/include/linux/usb/ch9.h b/include/linux/usb/ch9.h
index b72f305..0fd3fbd 100644
--- a/include/linux/usb/ch9.h
+++ b/include/linux/usb/ch9.h
@@ -579,7 +579,7 @@
__u8 bMaxBurst;
__u8 bmAttributes;
- __u16 wBytesPerInterval;
+ __le16 wBytesPerInterval;
} __attribute__ ((packed));
#define USB_DT_SS_EP_COMP_SIZE 6
diff --git a/include/linux/usb/composite.h b/include/linux/usb/composite.h
index 882a084..b78cba4 100644
--- a/include/linux/usb/composite.h
+++ b/include/linux/usb/composite.h
@@ -37,6 +37,14 @@
#include <linux/usb/ch9.h>
#include <linux/usb/gadget.h>
+/*
+ * USB function drivers should return USB_GADGET_DELAYED_STATUS if they
+ * wish to delay the data/status stages of the control transfer till they
+ * are ready. The control transfer will then be kept from completing till
+ * all the function drivers that requested for USB_GADGET_DELAYED_STAUS
+ * invoke usb_composite_setup_continue().
+ */
+#define USB_GADGET_DELAYED_STATUS 0x7fff /* Impossibly large value */
struct usb_configuration;
@@ -285,6 +293,7 @@
extern int usb_composite_probe(struct usb_composite_driver *driver,
int (*bind)(struct usb_composite_dev *cdev));
extern void usb_composite_unregister(struct usb_composite_driver *driver);
+extern void usb_composite_setup_continue(struct usb_composite_dev *cdev);
/**
@@ -342,7 +351,12 @@
*/
unsigned deactivations;
- /* protects at least deactivation count */
+ /* the composite driver won't complete the control transfer's
+ * data/status stages till delayed_status is zero.
+ */
+ int delayed_status;
+
+ /* protects deactivations and delayed_status counts*/
spinlock_t lock;
};
diff --git a/include/linux/usb/ehci_def.h b/include/linux/usb/ehci_def.h
index e49dfd4..7cc95ee 100644
--- a/include/linux/usb/ehci_def.h
+++ b/include/linux/usb/ehci_def.h
@@ -25,10 +25,15 @@
struct ehci_caps {
/* these fields are specified as 8 and 16 bit registers,
* but some hosts can't perform 8 or 16 bit PCI accesses.
+ * some hosts treat caplength and hciversion as parts of a 32-bit
+ * register, others treat them as two separate registers, this
+ * affects the memory map for big endian controllers.
*/
u32 hc_capbase;
-#define HC_LENGTH(p) (((p)>>00)&0x00ff) /* bits 7:0 */
-#define HC_VERSION(p) (((p)>>16)&0xffff) /* bits 31:16 */
+#define HC_LENGTH(ehci, p) (0x00ff&((p) >> /* bits 7:0 / offset 00h */ \
+ (ehci_big_endian_capbase(ehci) ? 24 : 0)))
+#define HC_VERSION(ehci, p) (0xffff&((p) >> /* bits 31:16 / offset 02h */ \
+ (ehci_big_endian_capbase(ehci) ? 0 : 16)))
u32 hcs_params; /* HCSPARAMS - offset 0x4 */
#define HCS_DEBUG_PORT(p) (((p)>>20)&0xf) /* bits 23:20, debug port? */
#define HCS_INDICATOR(p) ((p)&(1 << 16)) /* true: has port indicators */
@@ -52,7 +57,7 @@
#define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1)) /* true: periodic_size changes*/
#define HCC_64BIT_ADDR(p) ((p)&(1)) /* true: can use 64-bit addr */
u8 portroute[8]; /* nibbles for routing - offset 0xC */
-} __attribute__ ((packed));
+};
/* Section 2.3 Host Controller Operational Registers */
@@ -150,7 +155,7 @@
#define PORT_CSC (1<<1) /* connect status change */
#define PORT_CONNECT (1<<0) /* device connected */
#define PORT_RWC_BITS (PORT_CSC | PORT_PEC | PORT_OCC)
-} __attribute__ ((packed));
+};
#define USBMODE 0x68 /* USB Device mode */
#define USBMODE_SDIS (1<<3) /* Stream disable */
@@ -194,7 +199,7 @@
u32 data47;
u32 address;
#define DBGP_EPADDR(dev, ep) (((dev)<<8)|(ep))
-} __attribute__ ((packed));
+};
#ifdef CONFIG_EARLY_PRINTK_DBGP
#include <linux/init.h>
diff --git a/include/linux/usb/gadget.h b/include/linux/usb/gadget.h
index e538172..dd1571d 100644
--- a/include/linux/usb/gadget.h
+++ b/include/linux/usb/gadget.h
@@ -890,8 +890,8 @@
/* utility wrapping a simple endpoint selection policy */
extern struct usb_ep *usb_ep_autoconfig(struct usb_gadget *,
- struct usb_endpoint_descriptor *) __devinit;
+ struct usb_endpoint_descriptor *);
-extern void usb_ep_autoconfig_reset(struct usb_gadget *) __devinit;
+extern void usb_ep_autoconfig_reset(struct usb_gadget *);
#endif /* __LINUX_USB_GADGET_H */
diff --git a/include/linux/usb/msm_hsusb.h b/include/linux/usb/msm_hsusb.h
index 3657403..00311fe 100644
--- a/include/linux/usb/msm_hsusb.h
+++ b/include/linux/usb/msm_hsusb.h
@@ -2,7 +2,7 @@
*
* Copyright (C) 2008 Google, Inc.
* Author: Brian Swetland <swetland@google.com>
- * Copyright (c) 2009-2010, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
@@ -54,6 +54,64 @@
};
/**
+ * PHY used in
+ *
+ * INVALID_PHY Unsupported PHY
+ * CI_45NM_INTEGRATED_PHY Chipidea 45nm integrated PHY
+ * SNPS_28NM_INTEGRATED_PHY Synopsis 28nm integrated PHY
+ *
+ */
+enum msm_usb_phy_type {
+ INVALID_PHY = 0,
+ CI_45NM_INTEGRATED_PHY,
+ SNPS_28NM_INTEGRATED_PHY,
+};
+
+#define IDEV_CHG_MAX 1500
+#define IUNIT 100
+
+/**
+ * Different states involved in USB charger detection.
+ *
+ * USB_CHG_STATE_UNDEFINED USB charger is not connected or detection
+ * process is not yet started.
+ * USB_CHG_STATE_WAIT_FOR_DCD Waiting for Data pins contact.
+ * USB_CHG_STATE_DCD_DONE Data pin contact is detected.
+ * USB_CHG_STATE_PRIMARY_DONE Primary detection is completed (Detects
+ * between SDP and DCP/CDP).
+ * USB_CHG_STATE_SECONDARY_DONE Secondary detection is completed (Detects
+ * between DCP and CDP).
+ * USB_CHG_STATE_DETECTED USB charger type is determined.
+ *
+ */
+enum usb_chg_state {
+ USB_CHG_STATE_UNDEFINED = 0,
+ USB_CHG_STATE_WAIT_FOR_DCD,
+ USB_CHG_STATE_DCD_DONE,
+ USB_CHG_STATE_PRIMARY_DONE,
+ USB_CHG_STATE_SECONDARY_DONE,
+ USB_CHG_STATE_DETECTED,
+};
+
+/**
+ * USB charger types
+ *
+ * USB_INVALID_CHARGER Invalid USB charger.
+ * USB_SDP_CHARGER Standard downstream port. Refers to a downstream port
+ * on USB2.0 compliant host/hub.
+ * USB_DCP_CHARGER Dedicated charger port (AC charger/ Wall charger).
+ * USB_CDP_CHARGER Charging downstream port. Enumeration can happen and
+ * IDEV_CHG_MAX can be drawn irrespective of USB state.
+ *
+ */
+enum usb_chg_type {
+ USB_INVALID_CHARGER = 0,
+ USB_SDP_CHARGER,
+ USB_DCP_CHARGER,
+ USB_CDP_CHARGER,
+};
+
+/**
* struct msm_otg_platform_data - platform device data
* for msm_otg driver.
* @phy_init_seq: PHY configuration sequence. val, reg pairs
@@ -64,7 +122,8 @@
* @otg_control: OTG switch controlled by user/Id pin
* @default_mode: Default operational mode. Applicable only if
* OTG switch is controller by user.
- *
+ * @pclk_src_name: pclk is derived from ebi1_usb_clk in case of 7x27 and 8k
+ * dfab_usb_hs_clk in case of 8660 and 8960.
*/
struct msm_otg_platform_data {
int *phy_init_seq;
@@ -73,7 +132,9 @@
enum usb_mode_type mode;
enum otg_control_type otg_control;
enum usb_mode_type default_mode;
+ enum msm_usb_phy_type phy_type;
void (*setup_gpio)(enum usb_otg_state state);
+ char *pclk_src_name;
};
/**
@@ -83,6 +144,7 @@
* @irq: IRQ number assigned for HSUSB controller.
* @clk: clock struct of usb_hs_clk.
* @pclk: clock struct of usb_hs_pclk.
+ * @pclk_src: pclk source for voting.
* @phy_reset_clk: clock struct of usb_phy_clk.
* @core_clk: clock struct of usb_hs_core_clk.
* @regs: ioremapped register base address.
@@ -90,7 +152,12 @@
* @sm_work: OTG state machine work.
* @in_lpm: indicates low power mode (LPM) state.
* @async_int: Async interrupt arrived.
- *
+ * @cur_power: The amount of mA available from downstream port.
+ * @chg_work: Charger detection work.
+ * @chg_state: The state of charger detection process.
+ * @chg_type: The type of charger attached.
+ * @dcd_retires: The retry count used to track Data contact
+ * detection process.
*/
struct msm_otg {
struct otg_transceiver otg;
@@ -98,6 +165,7 @@
int irq;
struct clk *clk;
struct clk *pclk;
+ struct clk *pclk_src;
struct clk *phy_reset_clk;
struct clk *core_clk;
void __iomem *regs;
@@ -107,6 +175,11 @@
struct work_struct sm_work;
atomic_t in_lpm;
int async_int;
+ unsigned cur_power;
+ struct delayed_work chg_work;
+ enum usb_chg_state chg_state;
+ enum usb_chg_type chg_type;
+ u8 dcd_retries;
};
#endif
diff --git a/include/linux/usb/msm_hsusb_hw.h b/include/linux/usb/msm_hsusb_hw.h
index 7d1babb..6e97a2d 100644
--- a/include/linux/usb/msm_hsusb_hw.h
+++ b/include/linux/usb/msm_hsusb_hw.h
@@ -24,6 +24,7 @@
#define USB_PORTSC (MSM_USB_BASE + 0x0184)
#define USB_OTGSC (MSM_USB_BASE + 0x01A4)
#define USB_USBMODE (MSM_USB_BASE + 0x01A8)
+#define USB_PHY_CTRL (MSM_USB_BASE + 0x0240)
#define USBCMD_RESET 2
#define USB_USBINTR (MSM_USB_BASE + 0x0148)
@@ -42,6 +43,7 @@
#define ASYNC_INTR_CTRL (1 << 29) /* Enable async interrupt */
#define ULPI_STP_CTRL (1 << 30) /* Block communication with PHY */
+#define PHY_RETEN (1 << 1) /* PHY retention enable/disable */
/* OTG definitions */
#define OTGSC_INTSTS_MASK (0x7f << 16)
diff --git a/include/linux/usb/otg.h b/include/linux/usb/otg.h
index 6e40718..d87f44f 100644
--- a/include/linux/usb/otg.h
+++ b/include/linux/usb/otg.h
@@ -168,6 +168,7 @@
#ifdef CONFIG_USB_OTG_UTILS
extern struct otg_transceiver *otg_get_transceiver(void);
extern void otg_put_transceiver(struct otg_transceiver *);
+extern const char *otg_state_string(enum usb_otg_state state);
#else
static inline struct otg_transceiver *otg_get_transceiver(void)
{
@@ -177,6 +178,11 @@
static inline void otg_put_transceiver(struct otg_transceiver *x)
{
}
+
+static inline const char *otg_state_string(enum usb_otg_state state)
+{
+ return NULL;
+}
#endif
/* Context: can sleep */
diff --git a/include/linux/usb/renesas_usbhs.h b/include/linux/usb/renesas_usbhs.h
new file mode 100644
index 0000000..3a7f1d9
--- /dev/null
+++ b/include/linux/usb/renesas_usbhs.h
@@ -0,0 +1,156 @@
+/*
+ * Renesas USB
+ *
+ * Copyright (C) 2011 Renesas Solutions Corp.
+ * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ */
+#ifndef RENESAS_USB_H
+#define RENESAS_USB_H
+#include <linux/platform_device.h>
+#include <linux/usb/ch9.h>
+
+/*
+ * module type
+ *
+ * it will be return value from get_id
+ */
+enum {
+ USBHS_HOST = 0,
+ USBHS_GADGET,
+ USBHS_MAX,
+};
+
+/*
+ * callback functions table for driver
+ *
+ * These functions are called from platform for driver.
+ * Callback function's pointer will be set before
+ * renesas_usbhs_platform_callback :: hardware_init was called
+ */
+struct renesas_usbhs_driver_callback {
+ int (*notify_hotplug)(struct platform_device *pdev);
+};
+
+/*
+ * callback functions for platform
+ *
+ * These functions are called from driver for platform
+ */
+struct renesas_usbhs_platform_callback {
+
+ /*
+ * option:
+ *
+ * Hardware init function for platform.
+ * it is called when driver was probed.
+ */
+ int (*hardware_init)(struct platform_device *pdev);
+
+ /*
+ * option:
+ *
+ * Hardware exit function for platform.
+ * it is called when driver was removed
+ */
+ void (*hardware_exit)(struct platform_device *pdev);
+
+ /*
+ * option:
+ *
+ * Phy reset for platform
+ */
+ void (*phy_reset)(struct platform_device *pdev);
+
+ /*
+ * get USB ID function
+ * - USBHS_HOST
+ * - USBHS_GADGET
+ */
+ int (*get_id)(struct platform_device *pdev);
+
+ /*
+ * get VBUS status function.
+ */
+ int (*get_vbus)(struct platform_device *pdev);
+};
+
+/*
+ * parameters for renesas usbhs
+ *
+ * some register needs USB chip specific parameters.
+ * This struct show it to driver
+ */
+struct renesas_usbhs_driver_param {
+ /*
+ * pipe settings
+ */
+ u32 *pipe_type; /* array of USB_ENDPOINT_XFER_xxx (from ep0) */
+ int pipe_size; /* pipe_type array size */
+
+ /*
+ * option:
+ *
+ * for BUSWAIT :: BWAIT
+ * */
+ int buswait_bwait;
+
+ /*
+ * option:
+ *
+ * delay time from notify_hotplug callback
+ */
+ int detection_delay;
+};
+
+/*
+ * option:
+ *
+ * platform information for renesas_usbhs driver.
+ */
+struct renesas_usbhs_platform_info {
+ /*
+ * option:
+ *
+ * platform set these functions before
+ * call platform_add_devices if needed
+ */
+ struct renesas_usbhs_platform_callback platform_callback;
+
+ /*
+ * driver set these callback functions pointer.
+ * platform can use it on callback functions
+ */
+ struct renesas_usbhs_driver_callback driver_callback;
+
+ /*
+ * option:
+ *
+ * driver use these param for some register
+ */
+ struct renesas_usbhs_driver_param driver_param;
+};
+
+/*
+ * macro for platform
+ */
+#define renesas_usbhs_get_info(pdev)\
+ ((struct renesas_usbhs_platform_info *)(pdev)->dev.platform_data)
+
+#define renesas_usbhs_call_notify_hotplug(pdev) \
+ ({ \
+ struct renesas_usbhs_driver_callback *dc; \
+ dc = &(renesas_usbhs_get_info(pdev)->driver_callback); \
+ if (dc && dc->notify_hotplug) \
+ dc->notify_hotplug(pdev); \
+ })
+#endif /* RENESAS_USB_H */
diff --git a/include/linux/uvcvideo.h b/include/linux/uvcvideo.h
new file mode 100644
index 0000000..f46a53f
--- /dev/null
+++ b/include/linux/uvcvideo.h
@@ -0,0 +1,69 @@
+#ifndef __LINUX_UVCVIDEO_H_
+#define __LINUX_UVCVIDEO_H_
+
+#include <linux/ioctl.h>
+#include <linux/types.h>
+
+/*
+ * Dynamic controls
+ */
+
+/* Data types for UVC control data */
+#define UVC_CTRL_DATA_TYPE_RAW 0
+#define UVC_CTRL_DATA_TYPE_SIGNED 1
+#define UVC_CTRL_DATA_TYPE_UNSIGNED 2
+#define UVC_CTRL_DATA_TYPE_BOOLEAN 3
+#define UVC_CTRL_DATA_TYPE_ENUM 4
+#define UVC_CTRL_DATA_TYPE_BITMASK 5
+
+/* Control flags */
+#define UVC_CTRL_FLAG_SET_CUR (1 << 0)
+#define UVC_CTRL_FLAG_GET_CUR (1 << 1)
+#define UVC_CTRL_FLAG_GET_MIN (1 << 2)
+#define UVC_CTRL_FLAG_GET_MAX (1 << 3)
+#define UVC_CTRL_FLAG_GET_RES (1 << 4)
+#define UVC_CTRL_FLAG_GET_DEF (1 << 5)
+/* Control should be saved at suspend and restored at resume. */
+#define UVC_CTRL_FLAG_RESTORE (1 << 6)
+/* Control can be updated by the camera. */
+#define UVC_CTRL_FLAG_AUTO_UPDATE (1 << 7)
+
+#define UVC_CTRL_FLAG_GET_RANGE \
+ (UVC_CTRL_FLAG_GET_CUR | UVC_CTRL_FLAG_GET_MIN | \
+ UVC_CTRL_FLAG_GET_MAX | UVC_CTRL_FLAG_GET_RES | \
+ UVC_CTRL_FLAG_GET_DEF)
+
+struct uvc_menu_info {
+ __u32 value;
+ __u8 name[32];
+};
+
+struct uvc_xu_control_mapping {
+ __u32 id;
+ __u8 name[32];
+ __u8 entity[16];
+ __u8 selector;
+
+ __u8 size;
+ __u8 offset;
+ __u32 v4l2_type;
+ __u32 data_type;
+
+ struct uvc_menu_info __user *menu_info;
+ __u32 menu_count;
+
+ __u32 reserved[4];
+};
+
+struct uvc_xu_control_query {
+ __u8 unit;
+ __u8 selector;
+ __u8 query;
+ __u16 size;
+ __u8 __user *data;
+};
+
+#define UVCIOC_CTRL_MAP _IOWR('u', 0x20, struct uvc_xu_control_mapping)
+#define UVCIOC_CTRL_QUERY _IOWR('u', 0x21, struct uvc_xu_control_query)
+
+#endif
diff --git a/include/linux/v4l2-mediabus.h b/include/linux/v4l2-mediabus.h
index de5c159..5ea7f75 100644
--- a/include/linux/v4l2-mediabus.h
+++ b/include/linux/v4l2-mediabus.h
@@ -89,6 +89,9 @@
V4L2_MBUS_FMT_SGBRG12_1X12 = 0x3010,
V4L2_MBUS_FMT_SGRBG12_1X12 = 0x3011,
V4L2_MBUS_FMT_SRGGB12_1X12 = 0x3012,
+
+ /* JPEG compressed formats - next is 0x4002 */
+ V4L2_MBUS_FMT_JPEG_1X8 = 0x4001,
};
/**
diff --git a/include/linux/videodev2.h b/include/linux/videodev2.h
index be82c8e..8a4c309 100644
--- a/include/linux/videodev2.h
+++ b/include/linux/videodev2.h
@@ -311,6 +311,9 @@
#define V4L2_PIX_FMT_Y12 v4l2_fourcc('Y', '1', '2', ' ') /* 12 Greyscale */
#define V4L2_PIX_FMT_Y16 v4l2_fourcc('Y', '1', '6', ' ') /* 16 Greyscale */
+/* Grey bit-packed formats */
+#define V4L2_PIX_FMT_Y10BPACK v4l2_fourcc('Y', '1', '0', 'B') /* 10 Greyscale bit-packed */
+
/* Palette formats */
#define V4L2_PIX_FMT_PAL8 v4l2_fourcc('P', 'A', 'L', '8') /* 8 8-bit palette */
@@ -333,6 +336,7 @@
#define V4L2_PIX_FMT_YUV420 v4l2_fourcc('Y', 'U', '1', '2') /* 12 YUV 4:2:0 */
#define V4L2_PIX_FMT_HI240 v4l2_fourcc('H', 'I', '2', '4') /* 8 8-bit color */
#define V4L2_PIX_FMT_HM12 v4l2_fourcc('H', 'M', '1', '2') /* 8 YUV 4:2:0 16x16 macroblocks */
+#define V4L2_PIX_FMT_M420 v4l2_fourcc('M', '4', '2', '0') /* 12 YUV 4:2:0 2 lines y, 1 line uv interleaved */
/* two planes -- one Y, one Cr + Cb interleaved */
#define V4L2_PIX_FMT_NV12 v4l2_fourcc('N', 'V', '1', '2') /* 12 Y/CbCr 4:2:0 */
diff --git a/include/linux/vmstat.h b/include/linux/vmstat.h
index 2b3831b..5135983 100644
--- a/include/linux/vmstat.h
+++ b/include/linux/vmstat.h
@@ -261,6 +261,7 @@
extern void __dec_zone_state(struct zone *, enum zone_stat_item);
void refresh_cpu_vm_stats(int);
+void refresh_zone_stat_thresholds(void);
int calculate_pressure_threshold(struct zone *zone);
int calculate_normal_threshold(struct zone *zone);
@@ -313,6 +314,10 @@
#define set_pgdat_percpu_threshold(pgdat, callback) { }
static inline void refresh_cpu_vm_stats(int cpu) { }
-#endif
+static inline void refresh_zone_stat_thresholds(void) { }
+
+#endif /* CONFIG_SMP */
+
+extern const char * const vmstat_text[];
#endif /* _LINUX_VMSTAT_H */
diff --git a/include/linux/xattr.h b/include/linux/xattr.h
index 6050783..aed54c5 100644
--- a/include/linux/xattr.h
+++ b/include/linux/xattr.h
@@ -13,10 +13,6 @@
#define XATTR_CREATE 0x1 /* set value, fail if attr already exists */
#define XATTR_REPLACE 0x2 /* set value, fail if attr does not exist */
-#ifdef __KERNEL__
-
-#include <linux/types.h>
-
/* Namespaces */
#define XATTR_OS2_PREFIX "os2."
#define XATTR_OS2_PREFIX_LEN (sizeof (XATTR_OS2_PREFIX) - 1)
@@ -53,6 +49,10 @@
#define XATTR_CAPS_SUFFIX "capability"
#define XATTR_NAME_CAPS XATTR_SECURITY_PREFIX XATTR_CAPS_SUFFIX
+#ifdef __KERNEL__
+
+#include <linux/types.h>
+
struct inode;
struct dentry;
diff --git a/include/media/mt9v032.h b/include/media/mt9v032.h
new file mode 100644
index 0000000..5e27f9b
--- /dev/null
+++ b/include/media/mt9v032.h
@@ -0,0 +1,12 @@
+#ifndef _MEDIA_MT9V032_H
+#define _MEDIA_MT9V032_H
+
+struct v4l2_subdev;
+
+struct mt9v032_platform_data {
+ unsigned int clk_pol:1;
+
+ void (*set_clock)(struct v4l2_subdev *subdev, unsigned int rate);
+};
+
+#endif
diff --git a/include/media/rc-core.h b/include/media/rc-core.h
index 2963263..60536c7 100644
--- a/include/media/rc-core.h
+++ b/include/media/rc-core.h
@@ -40,10 +40,12 @@
* @driver_name: name of the hardware driver which registered this device
* @map_name: name of the default keymap
* @rc_map: current scan/key table
+ * @lock: used to ensure we've filled in all protocol details before
+ * anyone can call show_protocols or store_protocols
* @devno: unique remote control device number
* @raw: additional data for raw pulse/space devices
* @input_dev: the input child device used to communicate events to userspace
- * @driver_type: specifies if protocol decoding is done in hardware or software
+ * @driver_type: specifies if protocol decoding is done in hardware or software
* @idle: used to keep track of RX state
* @allowed_protos: bitmask with the supported RC_TYPE_* protocols
* @scanmask: some hardware decoders are not capable of providing the full
@@ -86,7 +88,8 @@
struct input_id input_id;
char *driver_name;
const char *map_name;
- struct rc_map rc_map;
+ struct rc_map rc_map;
+ struct mutex lock;
unsigned long devno;
struct ir_raw_event_ctrl *raw;
struct input_dev *input_dev;
diff --git a/include/media/rc-map.h b/include/media/rc-map.h
index 9184751..4e1409e 100644
--- a/include/media/rc-map.h
+++ b/include/media/rc-map.h
@@ -136,6 +136,7 @@
#define RC_MAP_TERRATEC_SLIM "rc-terratec-slim"
#define RC_MAP_TERRATEC_SLIM_2 "rc-terratec-slim-2"
#define RC_MAP_TEVII_NEC "rc-tevii-nec"
+#define RC_MAP_TIVO "rc-tivo"
#define RC_MAP_TOTAL_MEDIA_IN_HAND "rc-total-media-in-hand"
#define RC_MAP_TREKSTOR "rc-trekstor"
#define RC_MAP_TT_1500 "rc-tt-1500"
diff --git a/include/media/soc_camera.h b/include/media/soc_camera.h
index f80b537..238bd33 100644
--- a/include/media/soc_camera.h
+++ b/include/media/soc_camera.h
@@ -80,6 +80,11 @@
int (*cropcap)(struct soc_camera_device *, struct v4l2_cropcap *);
int (*get_crop)(struct soc_camera_device *, struct v4l2_crop *);
int (*set_crop)(struct soc_camera_device *, struct v4l2_crop *);
+ /*
+ * The difference to .set_crop() is, that .set_livecrop is not allowed
+ * to change the output sizes
+ */
+ int (*set_livecrop)(struct soc_camera_device *, struct v4l2_crop *);
int (*set_fmt)(struct soc_camera_device *, struct v4l2_format *);
int (*try_fmt)(struct soc_camera_device *, struct v4l2_format *);
void (*init_videobuf)(struct videobuf_queue *,
@@ -104,6 +109,12 @@
#define SOCAM_SENSOR_INVERT_HSYNC (1 << 2)
#define SOCAM_SENSOR_INVERT_VSYNC (1 << 3)
#define SOCAM_SENSOR_INVERT_DATA (1 << 4)
+#define SOCAM_MIPI_1LANE (1 << 5)
+#define SOCAM_MIPI_2LANE (1 << 6)
+#define SOCAM_MIPI_3LANE (1 << 7)
+#define SOCAM_MIPI_4LANE (1 << 8)
+#define SOCAM_MIPI (SOCAM_MIPI_1LANE | SOCAM_MIPI_2LANE | \
+ SOCAM_MIPI_3LANE | SOCAM_MIPI_4LANE)
struct i2c_board_info;
struct regulator_bulk_data;
@@ -268,6 +279,7 @@
unsigned long camera_flags, unsigned long bus_flags)
{
unsigned long common_flags, hsync, vsync, pclk, data, buswidth, mode;
+ unsigned long mipi;
common_flags = camera_flags & bus_flags;
@@ -277,8 +289,9 @@
data = common_flags & (SOCAM_DATA_ACTIVE_HIGH | SOCAM_DATA_ACTIVE_LOW);
mode = common_flags & (SOCAM_MASTER | SOCAM_SLAVE);
buswidth = common_flags & SOCAM_DATAWIDTH_MASK;
+ mipi = common_flags & SOCAM_MIPI;
- return (!hsync || !vsync || !pclk || !data || !mode || !buswidth) ? 0 :
+ return ((!hsync || !vsync || !pclk || !data || !mode || !buswidth) && !mipi) ? 0 :
common_flags;
}
diff --git a/include/media/soc_camera_platform.h b/include/media/soc_camera_platform.h
index 0ecefe2..6d7a4fd 100644
--- a/include/media/soc_camera_platform.h
+++ b/include/media/soc_camera_platform.h
@@ -25,4 +25,54 @@
int (*set_capture)(struct soc_camera_platform_info *info, int enable);
};
+static inline void soc_camera_platform_release(struct platform_device **pdev)
+{
+ *pdev = NULL;
+}
+
+static inline int soc_camera_platform_add(const struct soc_camera_link *icl,
+ struct device *dev,
+ struct platform_device **pdev,
+ struct soc_camera_link *plink,
+ void (*release)(struct device *dev),
+ int id)
+{
+ struct soc_camera_platform_info *info = plink->priv;
+ int ret;
+
+ if (icl != plink)
+ return -ENODEV;
+
+ if (*pdev)
+ return -EBUSY;
+
+ *pdev = platform_device_alloc("soc_camera_platform", id);
+ if (!*pdev)
+ return -ENOMEM;
+
+ info->dev = dev;
+
+ (*pdev)->dev.platform_data = info;
+ (*pdev)->dev.release = release;
+
+ ret = platform_device_add(*pdev);
+ if (ret < 0) {
+ platform_device_put(*pdev);
+ *pdev = NULL;
+ info->dev = NULL;
+ }
+
+ return ret;
+}
+
+static inline void soc_camera_platform_del(const struct soc_camera_link *icl,
+ struct platform_device *pdev,
+ const struct soc_camera_link *plink)
+{
+ if (icl != plink || !pdev)
+ return;
+
+ platform_device_unregister(pdev);
+}
+
#endif /* __SOC_CAMERA_H__ */
diff --git a/include/media/soc_mediabus.h b/include/media/soc_mediabus.h
index b338108..fae4325 100644
--- a/include/media/soc_mediabus.h
+++ b/include/media/soc_mediabus.h
@@ -16,18 +16,24 @@
/**
* enum soc_mbus_packing - data packing types on the media-bus
- * @SOC_MBUS_PACKING_NONE: no packing, bit-for-bit transfer to RAM
+ * @SOC_MBUS_PACKING_NONE: no packing, bit-for-bit transfer to RAM, one
+ * sample represents one pixel
* @SOC_MBUS_PACKING_2X8_PADHI: 16 bits transferred in 2 8-bit samples, in the
* possibly incomplete byte high bits are padding
* @SOC_MBUS_PACKING_2X8_PADLO: as above, but low bits are padding
* @SOC_MBUS_PACKING_EXTEND16: sample width (e.g., 10 bits) has to be extended
* to 16 bits
+ * @SOC_MBUS_PACKING_VARIABLE: compressed formats with variable packing
+ * @SOC_MBUS_PACKING_1_5X8: used for packed YUV 4:2:0 formats, where 4
+ * pixels occupy 6 bytes in RAM
*/
enum soc_mbus_packing {
SOC_MBUS_PACKING_NONE,
SOC_MBUS_PACKING_2X8_PADHI,
SOC_MBUS_PACKING_2X8_PADLO,
SOC_MBUS_PACKING_EXTEND16,
+ SOC_MBUS_PACKING_VARIABLE,
+ SOC_MBUS_PACKING_1_5X8,
};
/**
@@ -57,9 +63,24 @@
u8 bits_per_sample;
};
+/**
+ * struct soc_mbus_lookup - Lookup FOURCC IDs by mediabus codes for pass-through
+ * @code: mediabus pixel-code
+ * @fmt: pixel format description
+ */
+struct soc_mbus_lookup {
+ enum v4l2_mbus_pixelcode code;
+ struct soc_mbus_pixelfmt fmt;
+};
+
+const struct soc_mbus_pixelfmt *soc_mbus_find_fmtdesc(
+ enum v4l2_mbus_pixelcode code,
+ const struct soc_mbus_lookup *lookup,
+ int n);
const struct soc_mbus_pixelfmt *soc_mbus_get_fmtdesc(
enum v4l2_mbus_pixelcode code);
s32 soc_mbus_bytes_per_line(u32 width, const struct soc_mbus_pixelfmt *mf);
-int soc_mbus_samples_per_pixel(const struct soc_mbus_pixelfmt *mf);
+int soc_mbus_samples_per_pixel(const struct soc_mbus_pixelfmt *mf,
+ unsigned int *numerator, unsigned int *denominator);
#endif
diff --git a/include/media/v4l2-dev.h b/include/media/v4l2-dev.h
index 8266d5a..93e96fb 100644
--- a/include/media/v4l2-dev.h
+++ b/include/media/v4l2-dev.h
@@ -62,6 +62,8 @@
unsigned int (*poll) (struct file *, struct poll_table_struct *);
long (*ioctl) (struct file *, unsigned int, unsigned long);
long (*unlocked_ioctl) (struct file *, unsigned int, unsigned long);
+ unsigned long (*get_unmapped_area) (struct file *, unsigned long,
+ unsigned long, unsigned long, unsigned long);
int (*mmap) (struct file *, struct vm_area_struct *);
int (*open) (struct file *);
int (*release) (struct file *);
diff --git a/include/mtd/ubi-user.h b/include/mtd/ubi-user.h
index c0d47ad..3c41097 100644
--- a/include/mtd/ubi-user.h
+++ b/include/mtd/ubi-user.h
@@ -131,7 +131,7 @@
* ~~~~~~~~~~~~~~~~~~~~~~~~~
*
* To set an UBI volume property the %UBI_IOCSETPROP ioctl command should be
- * used. A pointer to a &struct ubi_set_prop_req object is expected to be
+ * used. A pointer to a &struct ubi_set_vol_prop_req object is expected to be
* passed. The object describes which property should be set, and to which value
* it should be set.
*/
@@ -186,7 +186,8 @@
/* Check if LEB is mapped command */
#define UBI_IOCEBISMAP _IOR(UBI_VOL_IOC_MAGIC, 5, __s32)
/* Set an UBI volume property */
-#define UBI_IOCSETPROP _IOW(UBI_VOL_IOC_MAGIC, 6, struct ubi_set_prop_req)
+#define UBI_IOCSETVOLPROP _IOW(UBI_VOL_IOC_MAGIC, 6, \
+ struct ubi_set_vol_prop_req)
/* Maximum MTD device name length supported by UBI */
#define MAX_UBI_MTD_NAME_LEN 127
@@ -223,13 +224,14 @@
};
/*
- * UBI set property ioctl constants
+ * UBI set volume property ioctl constants.
*
- * @UBI_PROP_DIRECT_WRITE: allow / disallow user to directly write and
- * erase individual eraseblocks on dynamic volumes
+ * @UBI_VOL_PROP_DIRECT_WRITE: allow (any non-zero value) or disallow (value 0)
+ * user to directly write and erase individual
+ * eraseblocks on dynamic volumes
*/
enum {
- UBI_PROP_DIRECT_WRITE = 1,
+ UBI_VOL_PROP_DIRECT_WRITE = 1,
};
/**
@@ -308,7 +310,7 @@
__s16 name_len;
__s8 padding2[4];
char name[UBI_MAX_VOLUME_NAME + 1];
-} __attribute__ ((packed));
+} __packed;
/**
* struct ubi_rsvol_req - a data structure used in volume re-size requests.
@@ -324,7 +326,7 @@
struct ubi_rsvol_req {
__s64 bytes;
__s32 vol_id;
-} __attribute__ ((packed));
+} __packed;
/**
* struct ubi_rnvol_req - volumes re-name request.
@@ -366,7 +368,7 @@
__s8 padding2[2];
char name[UBI_MAX_VOLUME_NAME + 1];
} ents[UBI_MAX_RNVOL];
-} __attribute__ ((packed));
+} __packed;
/**
* struct ubi_leb_change_req - a data structure used in atomic LEB change
@@ -381,7 +383,7 @@
__s32 bytes;
__s8 dtype;
__s8 padding[7];
-} __attribute__ ((packed));
+} __packed;
/**
* struct ubi_map_req - a data structure used in map LEB requests.
@@ -393,20 +395,20 @@
__s32 lnum;
__s8 dtype;
__s8 padding[3];
-} __attribute__ ((packed));
+} __packed;
/**
- * struct ubi_set_prop_req - a data structure used to set an ubi volume
- * property.
- * @property: property to set (%UBI_PROP_DIRECT_WRITE)
+ * struct ubi_set_vol_prop_req - a data structure used to set an UBI volume
+ * property.
+ * @property: property to set (%UBI_VOL_PROP_DIRECT_WRITE)
* @padding: reserved for future, not used, has to be zeroed
* @value: value to set
*/
-struct ubi_set_prop_req {
- __u8 property;
- __u8 padding[7];
- __u64 value;
-} __attribute__ ((packed));
+struct ubi_set_vol_prop_req {
+ __u8 property;
+ __u8 padding[7];
+ __u64 value;
+} __packed;
#endif /* __UBI_USER_H__ */
diff --git a/include/net/9p/9p.h b/include/net/9p/9p.h
index d2df55b..008711e 100644
--- a/include/net/9p/9p.h
+++ b/include/net/9p/9p.h
@@ -241,10 +241,10 @@
/**
* enum p9_perm_t - 9P permissions
- * @P9_DMDIR: mode bite for directories
+ * @P9_DMDIR: mode bit for directories
* @P9_DMAPPEND: mode bit for is append-only
* @P9_DMEXCL: mode bit for excluse use (only one open handle allowed)
- * @P9_DMMOUNT: mode bite for mount points
+ * @P9_DMMOUNT: mode bit for mount points
* @P9_DMAUTH: mode bit for authentication file
* @P9_DMTMP: mode bit for non-backed-up files
* @P9_DMSYMLINK: mode bit for symbolic links (9P2000.u)
@@ -362,7 +362,7 @@
};
/**
- * struct p9_stat - file system metadata information
+ * struct p9_wstat - file system metadata information
* @size: length prefix for this stat structure instance
* @type: the type of the server (equivalent to a major number)
* @dev: the sub-type of the server (equivalent to a minor number)
@@ -687,10 +687,10 @@
* @size: prefixed length of the structure
* @id: protocol operating identifier of type &p9_msg_t
* @tag: transaction id of the request
- * @offset: used by marshalling routines to track currentposition in buffer
+ * @offset: used by marshalling routines to track current position in buffer
* @capacity: used by marshalling routines to track total malloc'd capacity
* @pubuf: Payload user buffer given by the caller
- * @pubuf: Payload kernel buffer given by the caller
+ * @pkbuf: Payload kernel buffer given by the caller
* @pbuf_size: pubuf/pkbuf(only one will be !NULL) size to be read/write.
* @private: For transport layer's use.
* @sdata: payload
@@ -714,7 +714,7 @@
size_t pbuf_size;
void *private;
- uint8_t *sdata;
+ u8 *sdata;
};
struct p9_idpool;
@@ -728,7 +728,6 @@
int p9_idpool_check(int id, struct p9_idpool *p);
int p9_error_init(void);
-int p9_errstr2errno(char *, int);
int p9_trans_fd_init(void);
void p9_trans_fd_exit(void);
#endif /* NET_9P_H */
diff --git a/include/net/9p/client.h b/include/net/9p/client.h
index 051a99f..d26d5e9 100644
--- a/include/net/9p/client.h
+++ b/include/net/9p/client.h
@@ -60,7 +60,7 @@
};
/**
- * enum p9_req_status_t - virtio request status
+ * enum p9_req_status_t - status of a request
* @REQ_STATUS_IDLE: request slot unused
* @REQ_STATUS_ALLOC: request has been allocated but not sent
* @REQ_STATUS_UNSENT: request waiting to be sent
diff --git a/include/net/9p/transport.h b/include/net/9p/transport.h
index 8f08c73..d8549fb 100644
--- a/include/net/9p/transport.h
+++ b/include/net/9p/transport.h
@@ -41,6 +41,7 @@
* @pref: Preferences of this transport
* @def: set if this transport should be considered the default
* @create: member function to create a new connection on this transport
+ * @close: member function to discard a connection on this transport
* @request: member function to issue a request to the transport
* @cancel: member function to cancel a request (if it hasn't been sent)
*
@@ -48,7 +49,7 @@
* transport module with the 9P core network module and used by the client
* to instantiate a new connection on a transport.
*
- * BUGS: the transport module list isn't protected.
+ * The transport module list is protected by v9fs_trans_lock.
*/
struct p9_trans_module {
diff --git a/include/pcmcia/ds.h b/include/pcmcia/ds.h
index 3fd5064..7b82080 100644
--- a/include/pcmcia/ds.h
+++ b/include/pcmcia/ds.h
@@ -56,7 +56,7 @@
int (*resume) (struct pcmcia_device *dev);
struct module *owner;
- struct pcmcia_device_id *id_table;
+ const struct pcmcia_device_id *id_table;
struct device_driver drv;
struct pcmcia_dynids dynids;
};
diff --git a/include/video/omap-panel-generic-dpi.h b/include/video/omap-panel-generic-dpi.h
new file mode 100644
index 0000000..127e3f2
--- /dev/null
+++ b/include/video/omap-panel-generic-dpi.h
@@ -0,0 +1,37 @@
+/*
+ * Header for generic DPI panel driver
+ *
+ * Copyright (C) 2010 Canonical Ltd.
+ * Author: Bryan Wu <bryan.wu@canonical.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __OMAP_PANEL_GENERIC_DPI_H
+#define __OMAP_PANEL_GENERIC_DPI_H
+
+struct omap_dss_device;
+
+/**
+ * struct panel_generic_dpi_data - panel driver configuration data
+ * @name: panel name
+ * @platform_enable: platform specific panel enable function
+ * @platform_disable: platform specific panel disable function
+ */
+struct panel_generic_dpi_data {
+ const char *name;
+ int (*platform_enable)(struct omap_dss_device *dssdev);
+ void (*platform_disable)(struct omap_dss_device *dssdev);
+};
+
+#endif /* __OMAP_PANEL_GENERIC_DPI_H */
diff --git a/include/video/omap-panel-nokia-dsi.h b/include/video/omap-panel-nokia-dsi.h
new file mode 100644
index 0000000..921ae93
--- /dev/null
+++ b/include/video/omap-panel-nokia-dsi.h
@@ -0,0 +1,33 @@
+#ifndef __OMAP_NOKIA_DSI_PANEL_H
+#define __OMAP_NOKIA_DSI_PANEL_H
+
+struct omap_dss_device;
+
+/**
+ * struct nokia_dsi_panel_data - Nokia DSI panel driver configuration
+ * @name: panel name
+ * @use_ext_te: use external TE
+ * @ext_te_gpio: external TE GPIO
+ * @esd_interval: interval of ESD checks, 0 = disabled (ms)
+ * @ulps_timeout: time to wait before entering ULPS, 0 = disabled (ms)
+ * @max_backlight_level: maximum backlight level
+ * @set_backlight: pointer to backlight set function
+ * @get_backlight: pointer to backlight get function
+ */
+struct nokia_dsi_panel_data {
+ const char *name;
+
+ int reset_gpio;
+
+ bool use_ext_te;
+ int ext_te_gpio;
+
+ unsigned esd_interval;
+ unsigned ulps_timeout;
+
+ int max_backlight_level;
+ int (*set_backlight)(struct omap_dss_device *dssdev, int level);
+ int (*get_backlight)(struct omap_dss_device *dssdev);
+};
+
+#endif /* __OMAP_NOKIA_DSI_PANEL_H */
diff --git a/include/video/omapdss.h b/include/video/omapdss.h
new file mode 100644
index 0000000..892b97f
--- /dev/null
+++ b/include/video/omapdss.h
@@ -0,0 +1,641 @@
+/*
+ * Copyright (C) 2008 Nokia Corporation
+ * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __OMAP_OMAPDSS_H
+#define __OMAP_OMAPDSS_H
+
+#include <linux/list.h>
+#include <linux/kobject.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+#include <asm/atomic.h>
+
+#define DISPC_IRQ_FRAMEDONE (1 << 0)
+#define DISPC_IRQ_VSYNC (1 << 1)
+#define DISPC_IRQ_EVSYNC_EVEN (1 << 2)
+#define DISPC_IRQ_EVSYNC_ODD (1 << 3)
+#define DISPC_IRQ_ACBIAS_COUNT_STAT (1 << 4)
+#define DISPC_IRQ_PROG_LINE_NUM (1 << 5)
+#define DISPC_IRQ_GFX_FIFO_UNDERFLOW (1 << 6)
+#define DISPC_IRQ_GFX_END_WIN (1 << 7)
+#define DISPC_IRQ_PAL_GAMMA_MASK (1 << 8)
+#define DISPC_IRQ_OCP_ERR (1 << 9)
+#define DISPC_IRQ_VID1_FIFO_UNDERFLOW (1 << 10)
+#define DISPC_IRQ_VID1_END_WIN (1 << 11)
+#define DISPC_IRQ_VID2_FIFO_UNDERFLOW (1 << 12)
+#define DISPC_IRQ_VID2_END_WIN (1 << 13)
+#define DISPC_IRQ_SYNC_LOST (1 << 14)
+#define DISPC_IRQ_SYNC_LOST_DIGIT (1 << 15)
+#define DISPC_IRQ_WAKEUP (1 << 16)
+#define DISPC_IRQ_SYNC_LOST2 (1 << 17)
+#define DISPC_IRQ_VSYNC2 (1 << 18)
+#define DISPC_IRQ_ACBIAS_COUNT_STAT2 (1 << 21)
+#define DISPC_IRQ_FRAMEDONE2 (1 << 22)
+
+struct omap_dss_device;
+struct omap_overlay_manager;
+
+enum omap_display_type {
+ OMAP_DISPLAY_TYPE_NONE = 0,
+ OMAP_DISPLAY_TYPE_DPI = 1 << 0,
+ OMAP_DISPLAY_TYPE_DBI = 1 << 1,
+ OMAP_DISPLAY_TYPE_SDI = 1 << 2,
+ OMAP_DISPLAY_TYPE_DSI = 1 << 3,
+ OMAP_DISPLAY_TYPE_VENC = 1 << 4,
+ OMAP_DISPLAY_TYPE_HDMI = 1 << 5,
+};
+
+enum omap_plane {
+ OMAP_DSS_GFX = 0,
+ OMAP_DSS_VIDEO1 = 1,
+ OMAP_DSS_VIDEO2 = 2
+};
+
+enum omap_channel {
+ OMAP_DSS_CHANNEL_LCD = 0,
+ OMAP_DSS_CHANNEL_DIGIT = 1,
+ OMAP_DSS_CHANNEL_LCD2 = 2,
+};
+
+enum omap_color_mode {
+ OMAP_DSS_COLOR_CLUT1 = 1 << 0, /* BITMAP 1 */
+ OMAP_DSS_COLOR_CLUT2 = 1 << 1, /* BITMAP 2 */
+ OMAP_DSS_COLOR_CLUT4 = 1 << 2, /* BITMAP 4 */
+ OMAP_DSS_COLOR_CLUT8 = 1 << 3, /* BITMAP 8 */
+ OMAP_DSS_COLOR_RGB12U = 1 << 4, /* RGB12, 16-bit container */
+ OMAP_DSS_COLOR_ARGB16 = 1 << 5, /* ARGB16 */
+ OMAP_DSS_COLOR_RGB16 = 1 << 6, /* RGB16 */
+ OMAP_DSS_COLOR_RGB24U = 1 << 7, /* RGB24, 32-bit container */
+ OMAP_DSS_COLOR_RGB24P = 1 << 8, /* RGB24, 24-bit container */
+ OMAP_DSS_COLOR_YUV2 = 1 << 9, /* YUV2 4:2:2 co-sited */
+ OMAP_DSS_COLOR_UYVY = 1 << 10, /* UYVY 4:2:2 co-sited */
+ OMAP_DSS_COLOR_ARGB32 = 1 << 11, /* ARGB32 */
+ OMAP_DSS_COLOR_RGBA32 = 1 << 12, /* RGBA32 */
+ OMAP_DSS_COLOR_RGBX32 = 1 << 13, /* RGBx32 */
+ OMAP_DSS_COLOR_NV12 = 1 << 14, /* NV12 format: YUV 4:2:0 */
+ OMAP_DSS_COLOR_RGBA16 = 1 << 15, /* RGBA16 - 4444 */
+ OMAP_DSS_COLOR_RGBX16 = 1 << 16, /* RGBx16 - 4444 */
+ OMAP_DSS_COLOR_ARGB16_1555 = 1 << 17, /* ARGB16 - 1555 */
+ OMAP_DSS_COLOR_XRGB16_1555 = 1 << 18, /* xRGB16 - 1555 */
+};
+
+enum omap_lcd_display_type {
+ OMAP_DSS_LCD_DISPLAY_STN,
+ OMAP_DSS_LCD_DISPLAY_TFT,
+};
+
+enum omap_dss_load_mode {
+ OMAP_DSS_LOAD_CLUT_AND_FRAME = 0,
+ OMAP_DSS_LOAD_CLUT_ONLY = 1,
+ OMAP_DSS_LOAD_FRAME_ONLY = 2,
+ OMAP_DSS_LOAD_CLUT_ONCE_FRAME = 3,
+};
+
+enum omap_dss_trans_key_type {
+ OMAP_DSS_COLOR_KEY_GFX_DST = 0,
+ OMAP_DSS_COLOR_KEY_VID_SRC = 1,
+};
+
+enum omap_rfbi_te_mode {
+ OMAP_DSS_RFBI_TE_MODE_1 = 1,
+ OMAP_DSS_RFBI_TE_MODE_2 = 2,
+};
+
+enum omap_panel_config {
+ OMAP_DSS_LCD_IVS = 1<<0,
+ OMAP_DSS_LCD_IHS = 1<<1,
+ OMAP_DSS_LCD_IPC = 1<<2,
+ OMAP_DSS_LCD_IEO = 1<<3,
+ OMAP_DSS_LCD_RF = 1<<4,
+ OMAP_DSS_LCD_ONOFF = 1<<5,
+
+ OMAP_DSS_LCD_TFT = 1<<20,
+};
+
+enum omap_dss_venc_type {
+ OMAP_DSS_VENC_TYPE_COMPOSITE,
+ OMAP_DSS_VENC_TYPE_SVIDEO,
+};
+
+enum omap_display_caps {
+ OMAP_DSS_DISPLAY_CAP_MANUAL_UPDATE = 1 << 0,
+ OMAP_DSS_DISPLAY_CAP_TEAR_ELIM = 1 << 1,
+};
+
+enum omap_dss_update_mode {
+ OMAP_DSS_UPDATE_DISABLED = 0,
+ OMAP_DSS_UPDATE_AUTO,
+ OMAP_DSS_UPDATE_MANUAL,
+};
+
+enum omap_dss_display_state {
+ OMAP_DSS_DISPLAY_DISABLED = 0,
+ OMAP_DSS_DISPLAY_ACTIVE,
+ OMAP_DSS_DISPLAY_SUSPENDED,
+};
+
+/* XXX perhaps this should be removed */
+enum omap_dss_overlay_managers {
+ OMAP_DSS_OVL_MGR_LCD,
+ OMAP_DSS_OVL_MGR_TV,
+ OMAP_DSS_OVL_MGR_LCD2,
+};
+
+enum omap_dss_rotation_type {
+ OMAP_DSS_ROT_DMA = 0,
+ OMAP_DSS_ROT_VRFB = 1,
+};
+
+/* clockwise rotation angle */
+enum omap_dss_rotation_angle {
+ OMAP_DSS_ROT_0 = 0,
+ OMAP_DSS_ROT_90 = 1,
+ OMAP_DSS_ROT_180 = 2,
+ OMAP_DSS_ROT_270 = 3,
+};
+
+enum omap_overlay_caps {
+ OMAP_DSS_OVL_CAP_SCALE = 1 << 0,
+ OMAP_DSS_OVL_CAP_DISPC = 1 << 1,
+};
+
+enum omap_overlay_manager_caps {
+ OMAP_DSS_OVL_MGR_CAP_DISPC = 1 << 0,
+};
+
+enum omap_dss_clk_source {
+ OMAP_DSS_CLK_SRC_FCK = 0, /* OMAP2/3: DSS1_ALWON_FCLK
+ * OMAP4: DSS_FCLK */
+ OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC, /* OMAP3: DSI1_PLL_FCLK
+ * OMAP4: PLL1_CLK1 */
+ OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DSI, /* OMAP3: DSI2_PLL_FCLK
+ * OMAP4: PLL1_CLK2 */
+ OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC, /* OMAP4: PLL2_CLK1 */
+ OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DSI, /* OMAP4: PLL2_CLK2 */
+};
+
+/* RFBI */
+
+struct rfbi_timings {
+ int cs_on_time;
+ int cs_off_time;
+ int we_on_time;
+ int we_off_time;
+ int re_on_time;
+ int re_off_time;
+ int we_cycle_time;
+ int re_cycle_time;
+ int cs_pulse_width;
+ int access_time;
+
+ int clk_div;
+
+ u32 tim[5]; /* set by rfbi_convert_timings() */
+
+ int converted;
+};
+
+void omap_rfbi_write_command(const void *buf, u32 len);
+void omap_rfbi_read_data(void *buf, u32 len);
+void omap_rfbi_write_data(const void *buf, u32 len);
+void omap_rfbi_write_pixels(const void __iomem *buf, int scr_width,
+ u16 x, u16 y,
+ u16 w, u16 h);
+int omap_rfbi_enable_te(bool enable, unsigned line);
+int omap_rfbi_setup_te(enum omap_rfbi_te_mode mode,
+ unsigned hs_pulse_time, unsigned vs_pulse_time,
+ int hs_pol_inv, int vs_pol_inv, int extif_div);
+void rfbi_bus_lock(void);
+void rfbi_bus_unlock(void);
+
+/* DSI */
+void dsi_bus_lock(struct omap_dss_device *dssdev);
+void dsi_bus_unlock(struct omap_dss_device *dssdev);
+int dsi_vc_dcs_write(struct omap_dss_device *dssdev, int channel, u8 *data,
+ int len);
+int dsi_vc_dcs_write_0(struct omap_dss_device *dssdev, int channel,
+ u8 dcs_cmd);
+int dsi_vc_dcs_write_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
+ u8 param);
+int dsi_vc_dcs_write_nosync(struct omap_dss_device *dssdev, int channel,
+ u8 *data, int len);
+int dsi_vc_dcs_read(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
+ u8 *buf, int buflen);
+int dsi_vc_dcs_read_1(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
+ u8 *data);
+int dsi_vc_dcs_read_2(struct omap_dss_device *dssdev, int channel, u8 dcs_cmd,
+ u8 *data1, u8 *data2);
+int dsi_vc_set_max_rx_packet_size(struct omap_dss_device *dssdev, int channel,
+ u16 len);
+int dsi_vc_send_null(struct omap_dss_device *dssdev, int channel);
+int dsi_vc_send_bta_sync(struct omap_dss_device *dssdev, int channel);
+
+/* Board specific data */
+struct omap_dss_board_info {
+ int (*get_last_off_on_transaction_id)(struct device *dev);
+ int num_devices;
+ struct omap_dss_device **devices;
+ struct omap_dss_device *default_device;
+ void (*dsi_mux_pads)(bool enable);
+};
+
+#if defined(CONFIG_OMAP2_DSS_MODULE) || defined(CONFIG_OMAP2_DSS)
+/* Init with the board info */
+extern int omap_display_init(struct omap_dss_board_info *board_data);
+#else
+static inline int omap_display_init(struct omap_dss_board_info *board_data)
+{
+ return 0;
+}
+#endif
+
+struct omap_display_platform_data {
+ struct omap_dss_board_info *board_data;
+ /* TODO: Additional members to be added when PM is considered */
+
+ bool (*opt_clock_available)(const char *clk_role);
+};
+
+struct omap_video_timings {
+ /* Unit: pixels */
+ u16 x_res;
+ /* Unit: pixels */
+ u16 y_res;
+ /* Unit: KHz */
+ u32 pixel_clock;
+ /* Unit: pixel clocks */
+ u16 hsw; /* Horizontal synchronization pulse width */
+ /* Unit: pixel clocks */
+ u16 hfp; /* Horizontal front porch */
+ /* Unit: pixel clocks */
+ u16 hbp; /* Horizontal back porch */
+ /* Unit: line clocks */
+ u16 vsw; /* Vertical synchronization pulse width */
+ /* Unit: line clocks */
+ u16 vfp; /* Vertical front porch */
+ /* Unit: line clocks */
+ u16 vbp; /* Vertical back porch */
+};
+
+#ifdef CONFIG_OMAP2_DSS_VENC
+/* Hardcoded timings for tv modes. Venc only uses these to
+ * identify the mode, and does not actually use the configs
+ * itself. However, the configs should be something that
+ * a normal monitor can also show */
+extern const struct omap_video_timings omap_dss_pal_timings;
+extern const struct omap_video_timings omap_dss_ntsc_timings;
+#endif
+
+struct omap_overlay_info {
+ bool enabled;
+
+ u32 paddr;
+ void __iomem *vaddr;
+ u32 p_uv_addr; /* for NV12 format */
+ u16 screen_width;
+ u16 width;
+ u16 height;
+ enum omap_color_mode color_mode;
+ u8 rotation;
+ enum omap_dss_rotation_type rotation_type;
+ bool mirror;
+
+ u16 pos_x;
+ u16 pos_y;
+ u16 out_width; /* if 0, out_width == width */
+ u16 out_height; /* if 0, out_height == height */
+ u8 global_alpha;
+ u8 pre_mult_alpha;
+};
+
+struct omap_overlay {
+ struct kobject kobj;
+ struct list_head list;
+
+ /* static fields */
+ const char *name;
+ int id;
+ enum omap_color_mode supported_modes;
+ enum omap_overlay_caps caps;
+
+ /* dynamic fields */
+ struct omap_overlay_manager *manager;
+ struct omap_overlay_info info;
+
+ /* if true, info has been changed, but not applied() yet */
+ bool info_dirty;
+
+ int (*set_manager)(struct omap_overlay *ovl,
+ struct omap_overlay_manager *mgr);
+ int (*unset_manager)(struct omap_overlay *ovl);
+
+ int (*set_overlay_info)(struct omap_overlay *ovl,
+ struct omap_overlay_info *info);
+ void (*get_overlay_info)(struct omap_overlay *ovl,
+ struct omap_overlay_info *info);
+
+ int (*wait_for_go)(struct omap_overlay *ovl);
+};
+
+struct omap_overlay_manager_info {
+ u32 default_color;
+
+ enum omap_dss_trans_key_type trans_key_type;
+ u32 trans_key;
+ bool trans_enabled;
+
+ bool alpha_enabled;
+};
+
+struct omap_overlay_manager {
+ struct kobject kobj;
+ struct list_head list;
+
+ /* static fields */
+ const char *name;
+ int id;
+ enum omap_overlay_manager_caps caps;
+ int num_overlays;
+ struct omap_overlay **overlays;
+ enum omap_display_type supported_displays;
+
+ /* dynamic fields */
+ struct omap_dss_device *device;
+ struct omap_overlay_manager_info info;
+
+ bool device_changed;
+ /* if true, info has been changed but not applied() yet */
+ bool info_dirty;
+
+ int (*set_device)(struct omap_overlay_manager *mgr,
+ struct omap_dss_device *dssdev);
+ int (*unset_device)(struct omap_overlay_manager *mgr);
+
+ int (*set_manager_info)(struct omap_overlay_manager *mgr,
+ struct omap_overlay_manager_info *info);
+ void (*get_manager_info)(struct omap_overlay_manager *mgr,
+ struct omap_overlay_manager_info *info);
+
+ int (*apply)(struct omap_overlay_manager *mgr);
+ int (*wait_for_go)(struct omap_overlay_manager *mgr);
+ int (*wait_for_vsync)(struct omap_overlay_manager *mgr);
+
+ int (*enable)(struct omap_overlay_manager *mgr);
+ int (*disable)(struct omap_overlay_manager *mgr);
+};
+
+struct omap_dss_device {
+ struct device dev;
+
+ enum omap_display_type type;
+
+ enum omap_channel channel;
+
+ union {
+ struct {
+ u8 data_lines;
+ } dpi;
+
+ struct {
+ u8 channel;
+ u8 data_lines;
+ } rfbi;
+
+ struct {
+ u8 datapairs;
+ } sdi;
+
+ struct {
+ u8 clk_lane;
+ u8 clk_pol;
+ u8 data1_lane;
+ u8 data1_pol;
+ u8 data2_lane;
+ u8 data2_pol;
+ u8 data3_lane;
+ u8 data3_pol;
+ u8 data4_lane;
+ u8 data4_pol;
+
+ int module;
+
+ bool ext_te;
+ u8 ext_te_gpio;
+ } dsi;
+
+ struct {
+ enum omap_dss_venc_type type;
+ bool invert_polarity;
+ } venc;
+ } phy;
+
+ struct {
+ struct {
+ struct {
+ u16 lck_div;
+ u16 pck_div;
+ enum omap_dss_clk_source lcd_clk_src;
+ } channel;
+
+ enum omap_dss_clk_source dispc_fclk_src;
+ } dispc;
+
+ struct {
+ u16 regn;
+ u16 regm;
+ u16 regm_dispc;
+ u16 regm_dsi;
+
+ u16 lp_clk_div;
+ enum omap_dss_clk_source dsi_fclk_src;
+ } dsi;
+
+ struct {
+ u16 regn;
+ u16 regm2;
+ } hdmi;
+ } clocks;
+
+ struct {
+ struct omap_video_timings timings;
+
+ int acbi; /* ac-bias pin transitions per interrupt */
+ /* Unit: line clocks */
+ int acb; /* ac-bias pin frequency */
+
+ enum omap_panel_config config;
+ } panel;
+
+ struct {
+ u8 pixel_size;
+ struct rfbi_timings rfbi_timings;
+ } ctrl;
+
+ int reset_gpio;
+
+ int max_backlight_level;
+
+ const char *name;
+
+ /* used to match device to driver */
+ const char *driver_name;
+
+ void *data;
+
+ struct omap_dss_driver *driver;
+
+ /* helper variable for driver suspend/resume */
+ bool activate_after_resume;
+
+ enum omap_display_caps caps;
+
+ struct omap_overlay_manager *manager;
+
+ enum omap_dss_display_state state;
+
+ /* platform specific */
+ int (*platform_enable)(struct omap_dss_device *dssdev);
+ void (*platform_disable)(struct omap_dss_device *dssdev);
+ int (*set_backlight)(struct omap_dss_device *dssdev, int level);
+ int (*get_backlight)(struct omap_dss_device *dssdev);
+};
+
+struct omap_dss_driver {
+ struct device_driver driver;
+
+ int (*probe)(struct omap_dss_device *);
+ void (*remove)(struct omap_dss_device *);
+
+ int (*enable)(struct omap_dss_device *display);
+ void (*disable)(struct omap_dss_device *display);
+ int (*suspend)(struct omap_dss_device *display);
+ int (*resume)(struct omap_dss_device *display);
+ int (*run_test)(struct omap_dss_device *display, int test);
+
+ int (*set_update_mode)(struct omap_dss_device *dssdev,
+ enum omap_dss_update_mode);
+ enum omap_dss_update_mode (*get_update_mode)(
+ struct omap_dss_device *dssdev);
+
+ int (*update)(struct omap_dss_device *dssdev,
+ u16 x, u16 y, u16 w, u16 h);
+ int (*sync)(struct omap_dss_device *dssdev);
+
+ int (*enable_te)(struct omap_dss_device *dssdev, bool enable);
+ int (*get_te)(struct omap_dss_device *dssdev);
+
+ u8 (*get_rotate)(struct omap_dss_device *dssdev);
+ int (*set_rotate)(struct omap_dss_device *dssdev, u8 rotate);
+
+ bool (*get_mirror)(struct omap_dss_device *dssdev);
+ int (*set_mirror)(struct omap_dss_device *dssdev, bool enable);
+
+ int (*memory_read)(struct omap_dss_device *dssdev,
+ void *buf, size_t size,
+ u16 x, u16 y, u16 w, u16 h);
+
+ void (*get_resolution)(struct omap_dss_device *dssdev,
+ u16 *xres, u16 *yres);
+ void (*get_dimensions)(struct omap_dss_device *dssdev,
+ u32 *width, u32 *height);
+ int (*get_recommended_bpp)(struct omap_dss_device *dssdev);
+
+ int (*check_timings)(struct omap_dss_device *dssdev,
+ struct omap_video_timings *timings);
+ void (*set_timings)(struct omap_dss_device *dssdev,
+ struct omap_video_timings *timings);
+ void (*get_timings)(struct omap_dss_device *dssdev,
+ struct omap_video_timings *timings);
+
+ int (*set_wss)(struct omap_dss_device *dssdev, u32 wss);
+ u32 (*get_wss)(struct omap_dss_device *dssdev);
+};
+
+int omap_dss_register_driver(struct omap_dss_driver *);
+void omap_dss_unregister_driver(struct omap_dss_driver *);
+
+void omap_dss_get_device(struct omap_dss_device *dssdev);
+void omap_dss_put_device(struct omap_dss_device *dssdev);
+#define for_each_dss_dev(d) while ((d = omap_dss_get_next_device(d)) != NULL)
+struct omap_dss_device *omap_dss_get_next_device(struct omap_dss_device *from);
+struct omap_dss_device *omap_dss_find_device(void *data,
+ int (*match)(struct omap_dss_device *dssdev, void *data));
+
+int omap_dss_start_device(struct omap_dss_device *dssdev);
+void omap_dss_stop_device(struct omap_dss_device *dssdev);
+
+int omap_dss_get_num_overlay_managers(void);
+struct omap_overlay_manager *omap_dss_get_overlay_manager(int num);
+
+int omap_dss_get_num_overlays(void);
+struct omap_overlay *omap_dss_get_overlay(int num);
+
+void omapdss_default_get_resolution(struct omap_dss_device *dssdev,
+ u16 *xres, u16 *yres);
+int omapdss_default_get_recommended_bpp(struct omap_dss_device *dssdev);
+
+typedef void (*omap_dispc_isr_t) (void *arg, u32 mask);
+int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
+int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask);
+
+int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout);
+int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
+ unsigned long timeout);
+
+#define to_dss_driver(x) container_of((x), struct omap_dss_driver, driver)
+#define to_dss_device(x) container_of((x), struct omap_dss_device, dev)
+
+void omapdss_dsi_vc_enable_hs(struct omap_dss_device *dssdev, int channel,
+ bool enable);
+int omapdss_dsi_enable_te(struct omap_dss_device *dssdev, bool enable);
+
+int omap_dsi_prepare_update(struct omap_dss_device *dssdev,
+ u16 *x, u16 *y, u16 *w, u16 *h,
+ bool enlarge_update_area);
+int omap_dsi_update(struct omap_dss_device *dssdev,
+ int channel,
+ u16 x, u16 y, u16 w, u16 h,
+ void (*callback)(int, void *), void *data);
+int omap_dsi_request_vc(struct omap_dss_device *dssdev, int *channel);
+int omap_dsi_set_vc_id(struct omap_dss_device *dssdev, int channel, int vc_id);
+void omap_dsi_release_vc(struct omap_dss_device *dssdev, int channel);
+
+int omapdss_dsi_display_enable(struct omap_dss_device *dssdev);
+void omapdss_dsi_display_disable(struct omap_dss_device *dssdev,
+ bool disconnect_lanes, bool enter_ulps);
+
+int omapdss_dpi_display_enable(struct omap_dss_device *dssdev);
+void omapdss_dpi_display_disable(struct omap_dss_device *dssdev);
+void dpi_set_timings(struct omap_dss_device *dssdev,
+ struct omap_video_timings *timings);
+int dpi_check_timings(struct omap_dss_device *dssdev,
+ struct omap_video_timings *timings);
+
+int omapdss_sdi_display_enable(struct omap_dss_device *dssdev);
+void omapdss_sdi_display_disable(struct omap_dss_device *dssdev);
+
+int omapdss_rfbi_display_enable(struct omap_dss_device *dssdev);
+void omapdss_rfbi_display_disable(struct omap_dss_device *dssdev);
+int omap_rfbi_prepare_update(struct omap_dss_device *dssdev,
+ u16 *x, u16 *y, u16 *w, u16 *h);
+int omap_rfbi_update(struct omap_dss_device *dssdev,
+ u16 x, u16 y, u16 w, u16 h,
+ void (*callback)(void *), void *data);
+int omap_rfbi_configure(struct omap_dss_device *dssdev, int pixel_size,
+ int data_lines);
+
+#endif
diff --git a/include/video/sh_mobile_lcdc.h b/include/video/sh_mobile_lcdc.h
index 2c8d369..d964e68 100644
--- a/include/video/sh_mobile_lcdc.h
+++ b/include/video/sh_mobile_lcdc.h
@@ -2,6 +2,7 @@
#define __ASM_SH_MOBILE_LCDC_H__
#include <linux/fb.h>
+#include <video/sh_mobile_meram.h>
enum {
RGB8, /* 24bpp, 8:8:8 */
@@ -87,11 +88,13 @@
struct sh_mobile_lcdc_bl_info bl_info;
struct sh_mobile_lcdc_sys_bus_cfg sys_bus_cfg; /* only for SYSn I/F */
int nonstd;
+ struct sh_mobile_meram_cfg *meram_cfg;
};
struct sh_mobile_lcdc_info {
int clock_source;
struct sh_mobile_lcdc_chan_cfg ch[2];
+ struct sh_mobile_meram_info *meram_dev;
};
#endif /* __ASM_SH_MOBILE_LCDC_H__ */
diff --git a/include/video/sh_mobile_meram.h b/include/video/sh_mobile_meram.h
new file mode 100644
index 0000000..af602d6
--- /dev/null
+++ b/include/video/sh_mobile_meram.h
@@ -0,0 +1,68 @@
+#ifndef __VIDEO_SH_MOBILE_MERAM_H__
+#define __VIDEO_SH_MOBILE_MERAM_H__
+
+/* For sh_mobile_meram_info.addr_mode */
+enum {
+ SH_MOBILE_MERAM_MODE0 = 0,
+ SH_MOBILE_MERAM_MODE1
+};
+
+enum {
+ SH_MOBILE_MERAM_PF_NV = 0,
+ SH_MOBILE_MERAM_PF_RGB,
+ SH_MOBILE_MERAM_PF_NV24
+};
+
+
+struct sh_mobile_meram_priv;
+struct sh_mobile_meram_ops;
+
+struct sh_mobile_meram_info {
+ int addr_mode;
+ struct sh_mobile_meram_ops *ops;
+ struct sh_mobile_meram_priv *priv;
+ struct platform_device *pdev;
+};
+
+/* icb config */
+struct sh_mobile_meram_icb {
+ int marker_icb; /* ICB # for Marker ICB */
+ int cache_icb; /* ICB # for Cache ICB */
+ int meram_offset; /* MERAM Buffer Offset to use */
+ int meram_size; /* MERAM Buffer Size to use */
+
+ int cache_unit; /* bytes to cache per ICB */
+};
+
+struct sh_mobile_meram_cfg {
+ struct sh_mobile_meram_icb icb[2];
+ int pixelformat;
+ int current_reg;
+};
+
+struct module;
+struct sh_mobile_meram_ops {
+ struct module *module;
+ /* register usage of meram */
+ int (*meram_register)(struct sh_mobile_meram_info *meram_dev,
+ struct sh_mobile_meram_cfg *cfg,
+ int xres, int yres, int pixelformat,
+ unsigned long base_addr_y,
+ unsigned long base_addr_c,
+ unsigned long *icb_addr_y,
+ unsigned long *icb_addr_c, int *pitch);
+
+ /* unregister usage of meram */
+ int (*meram_unregister)(struct sh_mobile_meram_info *meram_dev,
+ struct sh_mobile_meram_cfg *cfg);
+
+ /* update meram settings */
+ int (*meram_update)(struct sh_mobile_meram_info *meram_dev,
+ struct sh_mobile_meram_cfg *cfg,
+ unsigned long base_addr_y,
+ unsigned long base_addr_c,
+ unsigned long *icb_addr_y,
+ unsigned long *icb_addr_c);
+};
+
+#endif /* __VIDEO_SH_MOBILE_MERAM_H__ */
diff --git a/include/xen/interface/io/blkif.h b/include/xen/interface/io/blkif.h
index 61e523a..3d5d6db 100644
--- a/include/xen/interface/io/blkif.h
+++ b/include/xen/interface/io/blkif.h
@@ -45,6 +45,19 @@
#define BLKIF_OP_WRITE_BARRIER 2
/*
+ * Recognised if "feature-flush-cache" is present in backend xenbus
+ * info. A flush will ask the underlying storage hardware to flush its
+ * non-volatile caches as appropriate. The "feature-flush-cache" node
+ * contains a boolean indicating whether flush requests are likely to
+ * succeed or fail. Either way, a flush request may fail at any time
+ * with BLKIF_RSP_EOPNOTSUPP if it is unsupported by the underlying
+ * block-device hardware. The boolean simply indicates whether or not it
+ * is worthwhile for the frontend to attempt flushes. If a backend does
+ * not recognise BLKIF_OP_WRITE_FLUSH_CACHE, it should *not* create the
+ * "feature-flush-cache" node!
+ */
+#define BLKIF_OP_FLUSH_DISKCACHE 3
+/*
* Maximum scatter/gather segments per request.
* This is carefully chosen so that sizeof(struct blkif_ring) <= PAGE_SIZE.
* NB. This could be 12 if the ring indexes weren't stored in the same page.
diff --git a/init/Kconfig b/init/Kconfig
index c8b172e..332aac6 100644
--- a/init/Kconfig
+++ b/init/Kconfig
@@ -959,24 +959,18 @@
bool "Include all symbols in kallsyms"
depends on DEBUG_KERNEL && KALLSYMS
help
- Normally kallsyms only contains the symbols of functions, for nicer
- OOPS messages. Some debuggers can use kallsyms for other
- symbols too: say Y here to include all symbols, if you need them
- and you don't care about adding 300k to the size of your kernel.
+ Normally kallsyms only contains the symbols of functions for nicer
+ OOPS messages and backtraces (i.e., symbols from the text and inittext
+ sections). This is sufficient for most cases. And only in very rare
+ cases (e.g., when a debugger is used) all symbols are required (e.g.,
+ names of variables from the data sections, etc).
- Say N.
+ This option makes sure that all symbols are loaded into the kernel
+ image (i.e., symbols from all sections) in cost of increased kernel
+ size (depending on the kernel configuration, it may be 300KiB or
+ something like this).
-config KALLSYMS_EXTRA_PASS
- bool "Do an extra kallsyms pass"
- depends on KALLSYMS
- help
- If kallsyms is not working correctly, the build will fail with
- inconsistent kallsyms data. If that occurs, log a bug report and
- turn on KALLSYMS_EXTRA_PASS which should result in a stable build.
- Always say N here unless you find a bug in kallsyms, which must be
- reported. KALLSYMS_EXTRA_PASS is only a temporary workaround while
- you wait for kallsyms to be fixed.
-
+ Say N unless you really need all symbols.
config HOTPLUG
bool "Support for hot-pluggable devices" if EXPERT
diff --git a/init/calibrate.c b/init/calibrate.c
index 76ac919..cfd7000 100644
--- a/init/calibrate.c
+++ b/init/calibrate.c
@@ -38,6 +38,9 @@
unsigned long timer_rate_min, timer_rate_max;
unsigned long good_timer_sum = 0;
unsigned long good_timer_count = 0;
+ unsigned long measured_times[MAX_DIRECT_CALIBRATION_RETRIES];
+ int max = -1; /* index of measured_times with max/min values or not set */
+ int min = -1;
int i;
if (read_current_timer(&pre_start) < 0 )
@@ -90,18 +93,78 @@
* If the upper limit and lower limit of the timer_rate is
* >= 12.5% apart, redo calibration.
*/
- if (pre_start != 0 && pre_end != 0 &&
+ printk(KERN_DEBUG "calibrate_delay_direct() timer_rate_max=%lu "
+ "timer_rate_min=%lu pre_start=%lu pre_end=%lu\n",
+ timer_rate_max, timer_rate_min, pre_start, pre_end);
+ if (start >= post_end)
+ printk(KERN_NOTICE "calibrate_delay_direct() ignoring "
+ "timer_rate as we had a TSC wrap around"
+ " start=%lu >=post_end=%lu\n",
+ start, post_end);
+ if (start < post_end && pre_start != 0 && pre_end != 0 &&
(timer_rate_max - timer_rate_min) < (timer_rate_max >> 3)) {
good_timer_count++;
good_timer_sum += timer_rate_max;
- }
+ measured_times[i] = timer_rate_max;
+ if (max < 0 || timer_rate_max > measured_times[max])
+ max = i;
+ if (min < 0 || timer_rate_max < measured_times[min])
+ min = i;
+ } else
+ measured_times[i] = 0;
+
}
- if (good_timer_count)
- return (good_timer_sum/good_timer_count);
+ /*
+ * Find the maximum & minimum - if they differ too much throw out the
+ * one with the largest difference from the mean and try again...
+ */
+ while (good_timer_count > 1) {
+ unsigned long estimate;
+ unsigned long maxdiff;
- printk(KERN_WARNING "calibrate_delay_direct() failed to get a good "
- "estimate for loops_per_jiffy.\nProbably due to long platform interrupts. Consider using \"lpj=\" boot option.\n");
+ /* compute the estimate */
+ estimate = (good_timer_sum/good_timer_count);
+ maxdiff = estimate >> 3;
+
+ /* if range is within 12% let's take it */
+ if ((measured_times[max] - measured_times[min]) < maxdiff)
+ return estimate;
+
+ /* ok - drop the worse value and try again... */
+ good_timer_sum = 0;
+ good_timer_count = 0;
+ if ((measured_times[max] - estimate) <
+ (estimate - measured_times[min])) {
+ printk(KERN_NOTICE "calibrate_delay_direct() dropping "
+ "min bogoMips estimate %d = %lu\n",
+ min, measured_times[min]);
+ measured_times[min] = 0;
+ min = max;
+ } else {
+ printk(KERN_NOTICE "calibrate_delay_direct() dropping "
+ "max bogoMips estimate %d = %lu\n",
+ max, measured_times[max]);
+ measured_times[max] = 0;
+ max = min;
+ }
+
+ for (i = 0; i < MAX_DIRECT_CALIBRATION_RETRIES; i++) {
+ if (measured_times[i] == 0)
+ continue;
+ good_timer_count++;
+ good_timer_sum += measured_times[i];
+ if (measured_times[i] < measured_times[min])
+ min = i;
+ if (measured_times[i] > measured_times[max])
+ max = i;
+ }
+
+ }
+
+ printk(KERN_NOTICE "calibrate_delay_direct() failed to get a good "
+ "estimate for loops_per_jiffy.\nProbably due to long platform "
+ "interrupts. Consider using \"lpj=\" boot option.\n");
return 0;
}
#else
diff --git a/init/main.c b/init/main.c
index 48df882..d2f1e08 100644
--- a/init/main.c
+++ b/init/main.c
@@ -504,11 +504,14 @@
* These use large bootmem allocations and must precede
* kmem_cache_init()
*/
+ setup_log_buf(0);
pidhash_init();
vfs_caches_init_early();
sort_main_extable();
trap_init();
mm_init();
+ BUG_ON(mm_init_cpumask(&init_mm, 0));
+
/*
* Set up the scheduler prior starting any interrupts (such as the
* timer interrupt). Full topology setup happens at smp_init()
diff --git a/kernel/capability.c b/kernel/capability.c
index 32a80e0..283c529 100644
--- a/kernel/capability.c
+++ b/kernel/capability.c
@@ -22,12 +22,8 @@
*/
const kernel_cap_t __cap_empty_set = CAP_EMPTY_SET;
-const kernel_cap_t __cap_full_set = CAP_FULL_SET;
-const kernel_cap_t __cap_init_eff_set = CAP_INIT_EFF_SET;
EXPORT_SYMBOL(__cap_empty_set);
-EXPORT_SYMBOL(__cap_full_set);
-EXPORT_SYMBOL(__cap_init_eff_set);
int file_caps_enabled = 1;
diff --git a/kernel/compat.c b/kernel/compat.c
index 9214dcd..fc9eb093 100644
--- a/kernel/compat.c
+++ b/kernel/compat.c
@@ -293,6 +293,8 @@
return compat_jiffies_to_clock_t(jiffies);
}
+#ifdef __ARCH_WANT_SYS_SIGPENDING
+
/*
* Assumption: old_sigset_t and compat_old_sigset_t are both
* types that can be passed to put_user()/get_user().
@@ -312,6 +314,10 @@
return ret;
}
+#endif
+
+#ifdef __ARCH_WANT_SYS_SIGPROCMASK
+
asmlinkage long compat_sys_sigprocmask(int how, compat_old_sigset_t __user *set,
compat_old_sigset_t __user *oset)
{
@@ -333,6 +339,8 @@
return ret;
}
+#endif
+
asmlinkage long compat_sys_setrlimit(unsigned int resource,
struct compat_rlimit __user *rlim)
{
diff --git a/kernel/cred.c b/kernel/cred.c
index 8093c16..e12c8af 100644
--- a/kernel/cred.c
+++ b/kernel/cred.c
@@ -49,10 +49,10 @@
.magic = CRED_MAGIC,
#endif
.securebits = SECUREBITS_DEFAULT,
- .cap_inheritable = CAP_INIT_INH_SET,
+ .cap_inheritable = CAP_EMPTY_SET,
.cap_permitted = CAP_FULL_SET,
- .cap_effective = CAP_INIT_EFF_SET,
- .cap_bset = CAP_INIT_BSET,
+ .cap_effective = CAP_FULL_SET,
+ .cap_bset = CAP_FULL_SET,
.user = INIT_USER,
.user_ns = &init_user_ns,
.group_info = &init_groups,
diff --git a/kernel/fork.c b/kernel/fork.c
index 2b44d82..8e7e135 100644
--- a/kernel/fork.c
+++ b/kernel/fork.c
@@ -383,15 +383,14 @@
get_file(file);
if (tmp->vm_flags & VM_DENYWRITE)
atomic_dec(&inode->i_writecount);
- spin_lock(&mapping->i_mmap_lock);
+ mutex_lock(&mapping->i_mmap_mutex);
if (tmp->vm_flags & VM_SHARED)
mapping->i_mmap_writable++;
- tmp->vm_truncate_count = mpnt->vm_truncate_count;
flush_dcache_mmap_lock(mapping);
/* insert tmp into the share list, just after mpnt */
vma_prio_tree_add(tmp, mpnt);
flush_dcache_mmap_unlock(mapping);
- spin_unlock(&mapping->i_mmap_lock);
+ mutex_unlock(&mapping->i_mmap_mutex);
}
/*
@@ -486,6 +485,20 @@
#endif
}
+int mm_init_cpumask(struct mm_struct *mm, struct mm_struct *oldmm)
+{
+#ifdef CONFIG_CPUMASK_OFFSTACK
+ if (!alloc_cpumask_var(&mm->cpu_vm_mask_var, GFP_KERNEL))
+ return -ENOMEM;
+
+ if (oldmm)
+ cpumask_copy(mm_cpumask(mm), mm_cpumask(oldmm));
+ else
+ memset(mm_cpumask(mm), 0, cpumask_size());
+#endif
+ return 0;
+}
+
static struct mm_struct * mm_init(struct mm_struct * mm, struct task_struct *p)
{
atomic_set(&mm->mm_users, 1);
@@ -522,10 +535,20 @@
struct mm_struct * mm;
mm = allocate_mm();
- if (mm) {
- memset(mm, 0, sizeof(*mm));
- mm = mm_init(mm, current);
+ if (!mm)
+ return NULL;
+
+ memset(mm, 0, sizeof(*mm));
+ mm = mm_init(mm, current);
+ if (!mm)
+ return NULL;
+
+ if (mm_init_cpumask(mm, NULL)) {
+ mm_free_pgd(mm);
+ free_mm(mm);
+ return NULL;
}
+
return mm;
}
@@ -537,6 +560,7 @@
void __mmdrop(struct mm_struct *mm)
{
BUG_ON(mm == &init_mm);
+ free_cpumask_var(mm->cpu_vm_mask_var);
mm_free_pgd(mm);
destroy_context(mm);
mmu_notifier_mm_destroy(mm);
@@ -691,6 +715,9 @@
if (!mm_init(mm, tsk))
goto fail_nomem;
+ if (mm_init_cpumask(mm, oldmm))
+ goto fail_nocpumask;
+
if (init_new_context(tsk, mm))
goto fail_nocontext;
@@ -717,6 +744,9 @@
return NULL;
fail_nocontext:
+ free_cpumask_var(mm->cpu_vm_mask_var);
+
+fail_nocpumask:
/*
* If init_new_context() failed, we cannot use mmput() to free the mm
* because it calls destroy_context()
diff --git a/kernel/hrtimer.c b/kernel/hrtimer.c
index dbbbf7d..a9205e3 100644
--- a/kernel/hrtimer.c
+++ b/kernel/hrtimer.c
@@ -64,17 +64,20 @@
.clock_base =
{
{
- .index = CLOCK_REALTIME,
- .get_time = &ktime_get_real,
- .resolution = KTIME_LOW_RES,
- },
- {
- .index = CLOCK_MONOTONIC,
+ .index = HRTIMER_BASE_MONOTONIC,
+ .clockid = CLOCK_MONOTONIC,
.get_time = &ktime_get,
.resolution = KTIME_LOW_RES,
},
{
- .index = CLOCK_BOOTTIME,
+ .index = HRTIMER_BASE_REALTIME,
+ .clockid = CLOCK_REALTIME,
+ .get_time = &ktime_get_real,
+ .resolution = KTIME_LOW_RES,
+ },
+ {
+ .index = HRTIMER_BASE_BOOTTIME,
+ .clockid = CLOCK_BOOTTIME,
.get_time = &ktime_get_boottime,
.resolution = KTIME_LOW_RES,
},
@@ -196,7 +199,7 @@
struct hrtimer_cpu_base *new_cpu_base;
int this_cpu = smp_processor_id();
int cpu = hrtimer_get_target(this_cpu, pinned);
- int basenum = hrtimer_clockid_to_base(base->index);
+ int basenum = base->index;
again:
new_cpu_base = &per_cpu(hrtimer_bases, cpu);
@@ -621,66 +624,6 @@
return res;
}
-
-/*
- * Retrigger next event is called after clock was set
- *
- * Called with interrupts disabled via on_each_cpu()
- */
-static void retrigger_next_event(void *arg)
-{
- struct hrtimer_cpu_base *base;
- struct timespec realtime_offset, wtm, sleep;
-
- if (!hrtimer_hres_active())
- return;
-
- get_xtime_and_monotonic_and_sleep_offset(&realtime_offset, &wtm,
- &sleep);
- set_normalized_timespec(&realtime_offset, -wtm.tv_sec, -wtm.tv_nsec);
-
- base = &__get_cpu_var(hrtimer_bases);
-
- /* Adjust CLOCK_REALTIME offset */
- raw_spin_lock(&base->lock);
- base->clock_base[HRTIMER_BASE_REALTIME].offset =
- timespec_to_ktime(realtime_offset);
- base->clock_base[HRTIMER_BASE_BOOTTIME].offset =
- timespec_to_ktime(sleep);
-
- hrtimer_force_reprogram(base, 0);
- raw_spin_unlock(&base->lock);
-}
-
-/*
- * Clock realtime was set
- *
- * Change the offset of the realtime clock vs. the monotonic
- * clock.
- *
- * We might have to reprogram the high resolution timer interrupt. On
- * SMP we call the architecture specific code to retrigger _all_ high
- * resolution timer interrupts. On UP we just disable interrupts and
- * call the high resolution interrupt code.
- */
-void clock_was_set(void)
-{
- /* Retrigger the CPU local events everywhere */
- on_each_cpu(retrigger_next_event, NULL, 1);
-}
-
-/*
- * During resume we might have to reprogram the high resolution timer
- * interrupt (on the local CPU):
- */
-void hres_timers_resume(void)
-{
- WARN_ONCE(!irqs_disabled(),
- KERN_INFO "hres_timers_resume() called with IRQs enabled!");
-
- retrigger_next_event(NULL);
-}
-
/*
* Initialize the high resolution related parts of cpu_base
*/
@@ -715,11 +658,39 @@
}
/*
+ * Retrigger next event is called after clock was set
+ *
+ * Called with interrupts disabled via on_each_cpu()
+ */
+static void retrigger_next_event(void *arg)
+{
+ struct hrtimer_cpu_base *base = &__get_cpu_var(hrtimer_bases);
+ struct timespec realtime_offset, xtim, wtm, sleep;
+
+ if (!hrtimer_hres_active())
+ return;
+
+ /* Optimized out for !HIGH_RES */
+ get_xtime_and_monotonic_and_sleep_offset(&xtim, &wtm, &sleep);
+ set_normalized_timespec(&realtime_offset, -wtm.tv_sec, -wtm.tv_nsec);
+
+ /* Adjust CLOCK_REALTIME offset */
+ raw_spin_lock(&base->lock);
+ base->clock_base[HRTIMER_BASE_REALTIME].offset =
+ timespec_to_ktime(realtime_offset);
+ base->clock_base[HRTIMER_BASE_BOOTTIME].offset =
+ timespec_to_ktime(sleep);
+
+ hrtimer_force_reprogram(base, 0);
+ raw_spin_unlock(&base->lock);
+}
+
+/*
* Switch to high resolution mode
*/
static int hrtimer_switch_to_hres(void)
{
- int cpu = smp_processor_id();
+ int i, cpu = smp_processor_id();
struct hrtimer_cpu_base *base = &per_cpu(hrtimer_bases, cpu);
unsigned long flags;
@@ -735,9 +706,8 @@
return 0;
}
base->hres_active = 1;
- base->clock_base[HRTIMER_BASE_REALTIME].resolution = KTIME_HIGH_RES;
- base->clock_base[HRTIMER_BASE_MONOTONIC].resolution = KTIME_HIGH_RES;
- base->clock_base[HRTIMER_BASE_BOOTTIME].resolution = KTIME_HIGH_RES;
+ for (i = 0; i < HRTIMER_MAX_CLOCK_BASES; i++)
+ base->clock_base[i].resolution = KTIME_HIGH_RES;
tick_setup_sched_timer();
@@ -761,9 +731,43 @@
return 0;
}
static inline void hrtimer_init_hres(struct hrtimer_cpu_base *base) { }
+static inline void retrigger_next_event(void *arg) { }
#endif /* CONFIG_HIGH_RES_TIMERS */
+/*
+ * Clock realtime was set
+ *
+ * Change the offset of the realtime clock vs. the monotonic
+ * clock.
+ *
+ * We might have to reprogram the high resolution timer interrupt. On
+ * SMP we call the architecture specific code to retrigger _all_ high
+ * resolution timer interrupts. On UP we just disable interrupts and
+ * call the high resolution interrupt code.
+ */
+void clock_was_set(void)
+{
+#ifdef CONFIG_HIGH_RES_TIMERS
+ /* Retrigger the CPU local events everywhere */
+ on_each_cpu(retrigger_next_event, NULL, 1);
+#endif
+ timerfd_clock_was_set();
+}
+
+/*
+ * During resume we might have to reprogram the high resolution timer
+ * interrupt (on the local CPU):
+ */
+void hrtimers_resume(void)
+{
+ WARN_ONCE(!irqs_disabled(),
+ KERN_INFO "hrtimers_resume() called with IRQs enabled!");
+
+ retrigger_next_event(NULL);
+ timerfd_clock_was_set();
+}
+
static inline void timer_stats_hrtimer_set_start_info(struct hrtimer *timer)
{
#ifdef CONFIG_TIMER_STATS
@@ -856,6 +860,7 @@
debug_activate(timer);
timerqueue_add(&base->active, &timer->node);
+ base->cpu_base->active_bases |= 1 << base->index;
/*
* HRTIMER_STATE_ENQUEUED is or'ed to the current state to preserve the
@@ -897,6 +902,8 @@
#endif
}
timerqueue_del(&base->active, &timer->node);
+ if (!timerqueue_getnext(&base->active))
+ base->cpu_base->active_bases &= ~(1 << base->index);
out:
timer->state = newstate;
}
@@ -1234,7 +1241,6 @@
void hrtimer_interrupt(struct clock_event_device *dev)
{
struct hrtimer_cpu_base *cpu_base = &__get_cpu_var(hrtimer_bases);
- struct hrtimer_clock_base *base;
ktime_t expires_next, now, entry_time, delta;
int i, retries = 0;
@@ -1256,12 +1262,15 @@
*/
cpu_base->expires_next.tv64 = KTIME_MAX;
- base = cpu_base->clock_base;
-
for (i = 0; i < HRTIMER_MAX_CLOCK_BASES; i++) {
- ktime_t basenow;
+ struct hrtimer_clock_base *base;
struct timerqueue_node *node;
+ ktime_t basenow;
+ if (!(cpu_base->active_bases & (1 << i)))
+ continue;
+
+ base = cpu_base->clock_base + i;
basenow = ktime_add(now, base->offset);
while ((node = timerqueue_getnext(&base->active))) {
@@ -1294,7 +1303,6 @@
__run_hrtimer(timer, &basenow);
}
- base++;
}
/*
@@ -1525,7 +1533,7 @@
struct timespec __user *rmtp;
int ret = 0;
- hrtimer_init_on_stack(&t.timer, restart->nanosleep.index,
+ hrtimer_init_on_stack(&t.timer, restart->nanosleep.clockid,
HRTIMER_MODE_ABS);
hrtimer_set_expires_tv64(&t.timer, restart->nanosleep.expires);
@@ -1577,7 +1585,7 @@
restart = ¤t_thread_info()->restart_block;
restart->fn = hrtimer_nanosleep_restart;
- restart->nanosleep.index = t.timer.base->index;
+ restart->nanosleep.clockid = t.timer.base->clockid;
restart->nanosleep.rmtp = rmtp;
restart->nanosleep.expires = hrtimer_get_expires_tv64(&t.timer);
diff --git a/kernel/irq/proc.c b/kernel/irq/proc.c
index 834899f..64e3df6 100644
--- a/kernel/irq/proc.c
+++ b/kernel/irq/proc.c
@@ -19,7 +19,7 @@
#ifdef CONFIG_SMP
-static int irq_affinity_proc_show(struct seq_file *m, void *v)
+static int show_irq_affinity(int type, struct seq_file *m, void *v)
{
struct irq_desc *desc = irq_to_desc((long)m->private);
const struct cpumask *mask = desc->irq_data.affinity;
@@ -28,7 +28,10 @@
if (irqd_is_setaffinity_pending(&desc->irq_data))
mask = desc->pending_mask;
#endif
- seq_cpumask(m, mask);
+ if (type)
+ seq_cpumask_list(m, mask);
+ else
+ seq_cpumask(m, mask);
seq_putc(m, '\n');
return 0;
}
@@ -59,7 +62,18 @@
#endif
int no_irq_affinity;
-static ssize_t irq_affinity_proc_write(struct file *file,
+static int irq_affinity_proc_show(struct seq_file *m, void *v)
+{
+ return show_irq_affinity(0, m, v);
+}
+
+static int irq_affinity_list_proc_show(struct seq_file *m, void *v)
+{
+ return show_irq_affinity(1, m, v);
+}
+
+
+static ssize_t write_irq_affinity(int type, struct file *file,
const char __user *buffer, size_t count, loff_t *pos)
{
unsigned int irq = (int)(long)PDE(file->f_path.dentry->d_inode)->data;
@@ -72,7 +86,10 @@
if (!alloc_cpumask_var(&new_value, GFP_KERNEL))
return -ENOMEM;
- err = cpumask_parse_user(buffer, count, new_value);
+ if (type)
+ err = cpumask_parselist_user(buffer, count, new_value);
+ else
+ err = cpumask_parse_user(buffer, count, new_value);
if (err)
goto free_cpumask;
@@ -100,11 +117,28 @@
return err;
}
+static ssize_t irq_affinity_proc_write(struct file *file,
+ const char __user *buffer, size_t count, loff_t *pos)
+{
+ return write_irq_affinity(0, file, buffer, count, pos);
+}
+
+static ssize_t irq_affinity_list_proc_write(struct file *file,
+ const char __user *buffer, size_t count, loff_t *pos)
+{
+ return write_irq_affinity(1, file, buffer, count, pos);
+}
+
static int irq_affinity_proc_open(struct inode *inode, struct file *file)
{
return single_open(file, irq_affinity_proc_show, PDE(inode)->data);
}
+static int irq_affinity_list_proc_open(struct inode *inode, struct file *file)
+{
+ return single_open(file, irq_affinity_list_proc_show, PDE(inode)->data);
+}
+
static int irq_affinity_hint_proc_open(struct inode *inode, struct file *file)
{
return single_open(file, irq_affinity_hint_proc_show, PDE(inode)->data);
@@ -125,6 +159,14 @@
.release = single_release,
};
+static const struct file_operations irq_affinity_list_proc_fops = {
+ .open = irq_affinity_list_proc_open,
+ .read = seq_read,
+ .llseek = seq_lseek,
+ .release = single_release,
+ .write = irq_affinity_list_proc_write,
+};
+
static int default_affinity_show(struct seq_file *m, void *v)
{
seq_cpumask(m, irq_default_affinity);
@@ -289,6 +331,10 @@
proc_create_data("affinity_hint", 0400, desc->dir,
&irq_affinity_hint_proc_fops, (void *)(long)irq);
+ /* create /proc/irq/<irq>/smp_affinity_list */
+ proc_create_data("smp_affinity_list", 0600, desc->dir,
+ &irq_affinity_list_proc_fops, (void *)(long)irq);
+
proc_create_data("node", 0444, desc->dir,
&irq_node_proc_fops, (void *)(long)irq);
#endif
diff --git a/kernel/kmod.c b/kernel/kmod.c
index 5ae0ff3..ad6a81c 100644
--- a/kernel/kmod.c
+++ b/kernel/kmod.c
@@ -25,6 +25,7 @@
#include <linux/kmod.h>
#include <linux/slab.h>
#include <linux/completion.h>
+#include <linux/cred.h>
#include <linux/file.h>
#include <linux/fdtable.h>
#include <linux/workqueue.h>
@@ -43,6 +44,13 @@
static struct workqueue_struct *khelper_wq;
+#define CAP_BSET (void *)1
+#define CAP_PI (void *)2
+
+static kernel_cap_t usermodehelper_bset = CAP_FULL_SET;
+static kernel_cap_t usermodehelper_inheritable = CAP_FULL_SET;
+static DEFINE_SPINLOCK(umh_sysctl_lock);
+
#ifdef CONFIG_MODULES
/*
@@ -132,6 +140,7 @@
static int ____call_usermodehelper(void *data)
{
struct subprocess_info *sub_info = data;
+ struct cred *new;
int retval;
spin_lock_irq(¤t->sighand->siglock);
@@ -153,6 +162,19 @@
goto fail;
}
+ retval = -ENOMEM;
+ new = prepare_kernel_cred(current);
+ if (!new)
+ goto fail;
+
+ spin_lock(&umh_sysctl_lock);
+ new->cap_bset = cap_intersect(usermodehelper_bset, new->cap_bset);
+ new->cap_inheritable = cap_intersect(usermodehelper_inheritable,
+ new->cap_inheritable);
+ spin_unlock(&umh_sysctl_lock);
+
+ commit_creds(new);
+
retval = kernel_execve(sub_info->path,
(const char *const *)sub_info->argv,
(const char *const *)sub_info->envp);
@@ -420,6 +442,84 @@
}
EXPORT_SYMBOL(call_usermodehelper_exec);
+static int proc_cap_handler(struct ctl_table *table, int write,
+ void __user *buffer, size_t *lenp, loff_t *ppos)
+{
+ struct ctl_table t;
+ unsigned long cap_array[_KERNEL_CAPABILITY_U32S];
+ kernel_cap_t new_cap;
+ int err, i;
+
+ if (write && (!capable(CAP_SETPCAP) ||
+ !capable(CAP_SYS_MODULE)))
+ return -EPERM;
+
+ /*
+ * convert from the global kernel_cap_t to the ulong array to print to
+ * userspace if this is a read.
+ */
+ spin_lock(&umh_sysctl_lock);
+ for (i = 0; i < _KERNEL_CAPABILITY_U32S; i++) {
+ if (table->data == CAP_BSET)
+ cap_array[i] = usermodehelper_bset.cap[i];
+ else if (table->data == CAP_PI)
+ cap_array[i] = usermodehelper_inheritable.cap[i];
+ else
+ BUG();
+ }
+ spin_unlock(&umh_sysctl_lock);
+
+ t = *table;
+ t.data = &cap_array;
+
+ /*
+ * actually read or write and array of ulongs from userspace. Remember
+ * these are least significant 32 bits first
+ */
+ err = proc_doulongvec_minmax(&t, write, buffer, lenp, ppos);
+ if (err < 0)
+ return err;
+
+ /*
+ * convert from the sysctl array of ulongs to the kernel_cap_t
+ * internal representation
+ */
+ for (i = 0; i < _KERNEL_CAPABILITY_U32S; i++)
+ new_cap.cap[i] = cap_array[i];
+
+ /*
+ * Drop everything not in the new_cap (but don't add things)
+ */
+ spin_lock(&umh_sysctl_lock);
+ if (write) {
+ if (table->data == CAP_BSET)
+ usermodehelper_bset = cap_intersect(usermodehelper_bset, new_cap);
+ if (table->data == CAP_PI)
+ usermodehelper_inheritable = cap_intersect(usermodehelper_inheritable, new_cap);
+ }
+ spin_unlock(&umh_sysctl_lock);
+
+ return 0;
+}
+
+struct ctl_table usermodehelper_table[] = {
+ {
+ .procname = "bset",
+ .data = CAP_BSET,
+ .maxlen = _KERNEL_CAPABILITY_U32S * sizeof(unsigned long),
+ .mode = 0600,
+ .proc_handler = proc_cap_handler,
+ },
+ {
+ .procname = "inheritable",
+ .data = CAP_PI,
+ .maxlen = _KERNEL_CAPABILITY_U32S * sizeof(unsigned long),
+ .mode = 0600,
+ .proc_handler = proc_cap_handler,
+ },
+ { }
+};
+
void __init usermodehelper_init(void)
{
khelper_wq = create_singlethread_workqueue("khelper");
diff --git a/kernel/module.c b/kernel/module.c
index 2287972..795bdc7 100644
--- a/kernel/module.c
+++ b/kernel/module.c
@@ -2812,7 +2812,7 @@
}
/* This has to be done once we're sure module name is unique. */
- if (!mod->taints)
+ if (!mod->taints || mod->taints == (1U<<TAINT_CRAP))
dynamic_debug_setup(info.debug, info.num_debug);
/* Find duplicate symbols */
@@ -2849,7 +2849,7 @@
module_bug_cleanup(mod);
ddebug:
- if (!mod->taints)
+ if (!mod->taints || mod->taints == (1U<<TAINT_CRAP))
dynamic_debug_remove(info.debug);
unlock:
mutex_unlock(&module_mutex);
diff --git a/kernel/mutex.c b/kernel/mutex.c
index 2c938e2..d607ed5 100644
--- a/kernel/mutex.c
+++ b/kernel/mutex.c
@@ -131,14 +131,14 @@
*/
static inline int __sched
__mutex_lock_common(struct mutex *lock, long state, unsigned int subclass,
- unsigned long ip)
+ struct lockdep_map *nest_lock, unsigned long ip)
{
struct task_struct *task = current;
struct mutex_waiter waiter;
unsigned long flags;
preempt_disable();
- mutex_acquire(&lock->dep_map, subclass, 0, ip);
+ mutex_acquire_nest(&lock->dep_map, subclass, 0, nest_lock, ip);
#ifdef CONFIG_MUTEX_SPIN_ON_OWNER
/*
@@ -269,16 +269,25 @@
mutex_lock_nested(struct mutex *lock, unsigned int subclass)
{
might_sleep();
- __mutex_lock_common(lock, TASK_UNINTERRUPTIBLE, subclass, _RET_IP_);
+ __mutex_lock_common(lock, TASK_UNINTERRUPTIBLE, subclass, NULL, _RET_IP_);
}
EXPORT_SYMBOL_GPL(mutex_lock_nested);
+void __sched
+_mutex_lock_nest_lock(struct mutex *lock, struct lockdep_map *nest)
+{
+ might_sleep();
+ __mutex_lock_common(lock, TASK_UNINTERRUPTIBLE, 0, nest, _RET_IP_);
+}
+
+EXPORT_SYMBOL_GPL(_mutex_lock_nest_lock);
+
int __sched
mutex_lock_killable_nested(struct mutex *lock, unsigned int subclass)
{
might_sleep();
- return __mutex_lock_common(lock, TASK_KILLABLE, subclass, _RET_IP_);
+ return __mutex_lock_common(lock, TASK_KILLABLE, subclass, NULL, _RET_IP_);
}
EXPORT_SYMBOL_GPL(mutex_lock_killable_nested);
@@ -287,7 +296,7 @@
{
might_sleep();
return __mutex_lock_common(lock, TASK_INTERRUPTIBLE,
- subclass, _RET_IP_);
+ subclass, NULL, _RET_IP_);
}
EXPORT_SYMBOL_GPL(mutex_lock_interruptible_nested);
@@ -393,7 +402,7 @@
{
struct mutex *lock = container_of(lock_count, struct mutex, count);
- __mutex_lock_common(lock, TASK_UNINTERRUPTIBLE, 0, _RET_IP_);
+ __mutex_lock_common(lock, TASK_UNINTERRUPTIBLE, 0, NULL, _RET_IP_);
}
static noinline int __sched
@@ -401,7 +410,7 @@
{
struct mutex *lock = container_of(lock_count, struct mutex, count);
- return __mutex_lock_common(lock, TASK_KILLABLE, 0, _RET_IP_);
+ return __mutex_lock_common(lock, TASK_KILLABLE, 0, NULL, _RET_IP_);
}
static noinline int __sched
@@ -409,7 +418,7 @@
{
struct mutex *lock = container_of(lock_count, struct mutex, count);
- return __mutex_lock_common(lock, TASK_INTERRUPTIBLE, 0, _RET_IP_);
+ return __mutex_lock_common(lock, TASK_INTERRUPTIBLE, 0, NULL, _RET_IP_);
}
#endif
diff --git a/kernel/posix-cpu-timers.c b/kernel/posix-cpu-timers.c
index 0791b13..58f405b 100644
--- a/kernel/posix-cpu-timers.c
+++ b/kernel/posix-cpu-timers.c
@@ -1514,7 +1514,7 @@
return -EFAULT;
restart_block->fn = posix_cpu_nsleep_restart;
- restart_block->nanosleep.index = which_clock;
+ restart_block->nanosleep.clockid = which_clock;
restart_block->nanosleep.rmtp = rmtp;
restart_block->nanosleep.expires = timespec_to_ns(rqtp);
}
@@ -1523,7 +1523,7 @@
static long posix_cpu_nsleep_restart(struct restart_block *restart_block)
{
- clockid_t which_clock = restart_block->nanosleep.index;
+ clockid_t which_clock = restart_block->nanosleep.clockid;
struct timespec t;
struct itimerspec it;
int error;
diff --git a/kernel/posix-timers.c b/kernel/posix-timers.c
index e5498d7..4556182 100644
--- a/kernel/posix-timers.c
+++ b/kernel/posix-timers.c
@@ -491,6 +491,13 @@
return tmr;
}
+static void k_itimer_rcu_free(struct rcu_head *head)
+{
+ struct k_itimer *tmr = container_of(head, struct k_itimer, it.rcu);
+
+ kmem_cache_free(posix_timers_cache, tmr);
+}
+
#define IT_ID_SET 1
#define IT_ID_NOT_SET 0
static void release_posix_timer(struct k_itimer *tmr, int it_id_set)
@@ -503,7 +510,7 @@
}
put_pid(tmr->it_pid);
sigqueue_free(tmr->sigq);
- kmem_cache_free(posix_timers_cache, tmr);
+ call_rcu(&tmr->it.rcu, k_itimer_rcu_free);
}
static struct k_clock *clockid_to_kclock(const clockid_t id)
@@ -631,22 +638,18 @@
static struct k_itimer *__lock_timer(timer_t timer_id, unsigned long *flags)
{
struct k_itimer *timr;
- /*
- * Watch out here. We do a irqsave on the idr_lock and pass the
- * flags part over to the timer lock. Must not let interrupts in
- * while we are moving the lock.
- */
- spin_lock_irqsave(&idr_lock, *flags);
+
+ rcu_read_lock();
timr = idr_find(&posix_timers_id, (int)timer_id);
if (timr) {
- spin_lock(&timr->it_lock);
+ spin_lock_irqsave(&timr->it_lock, *flags);
if (timr->it_signal == current->signal) {
- spin_unlock(&idr_lock);
+ rcu_read_unlock();
return timr;
}
- spin_unlock(&timr->it_lock);
+ spin_unlock_irqrestore(&timr->it_lock, *flags);
}
- spin_unlock_irqrestore(&idr_lock, *flags);
+ rcu_read_unlock();
return NULL;
}
@@ -1056,7 +1059,7 @@
*/
long clock_nanosleep_restart(struct restart_block *restart_block)
{
- clockid_t which_clock = restart_block->nanosleep.index;
+ clockid_t which_clock = restart_block->nanosleep.clockid;
struct k_clock *kc = clockid_to_kclock(which_clock);
if (WARN_ON_ONCE(!kc || !kc->nsleep_restart))
diff --git a/kernel/printk.c b/kernel/printk.c
index da8ca81..3518539 100644
--- a/kernel/printk.c
+++ b/kernel/printk.c
@@ -31,6 +31,7 @@
#include <linux/smp.h>
#include <linux/security.h>
#include <linux/bootmem.h>
+#include <linux/memblock.h>
#include <linux/syscalls.h>
#include <linux/kexec.h>
#include <linux/kdb.h>
@@ -167,46 +168,74 @@
}
#endif
+/* requested log_buf_len from kernel cmdline */
+static unsigned long __initdata new_log_buf_len;
+
+/* save requested log_buf_len since it's too early to process it */
static int __init log_buf_len_setup(char *str)
{
unsigned size = memparse(str, &str);
- unsigned long flags;
if (size)
size = roundup_pow_of_two(size);
- if (size > log_buf_len) {
- unsigned start, dest_idx, offset;
- char *new_log_buf;
+ if (size > log_buf_len)
+ new_log_buf_len = size;
- new_log_buf = alloc_bootmem(size);
- if (!new_log_buf) {
- printk(KERN_WARNING "log_buf_len: allocation failed\n");
- goto out;
- }
-
- spin_lock_irqsave(&logbuf_lock, flags);
- log_buf_len = size;
- log_buf = new_log_buf;
-
- offset = start = min(con_start, log_start);
- dest_idx = 0;
- while (start != log_end) {
- log_buf[dest_idx] = __log_buf[start & (__LOG_BUF_LEN - 1)];
- start++;
- dest_idx++;
- }
- log_start -= offset;
- con_start -= offset;
- log_end -= offset;
- spin_unlock_irqrestore(&logbuf_lock, flags);
-
- printk(KERN_NOTICE "log_buf_len: %d\n", log_buf_len);
- }
-out:
- return 1;
+ return 0;
}
+early_param("log_buf_len", log_buf_len_setup);
-__setup("log_buf_len=", log_buf_len_setup);
+void __init setup_log_buf(int early)
+{
+ unsigned long flags;
+ unsigned start, dest_idx, offset;
+ char *new_log_buf;
+ int free;
+
+ if (!new_log_buf_len)
+ return;
+
+ if (early) {
+ unsigned long mem;
+
+ mem = memblock_alloc(new_log_buf_len, PAGE_SIZE);
+ if (mem == MEMBLOCK_ERROR)
+ return;
+ new_log_buf = __va(mem);
+ } else {
+ new_log_buf = alloc_bootmem_nopanic(new_log_buf_len);
+ }
+
+ if (unlikely(!new_log_buf)) {
+ pr_err("log_buf_len: %ld bytes not available\n",
+ new_log_buf_len);
+ return;
+ }
+
+ spin_lock_irqsave(&logbuf_lock, flags);
+ log_buf_len = new_log_buf_len;
+ log_buf = new_log_buf;
+ new_log_buf_len = 0;
+ free = __LOG_BUF_LEN - log_end;
+
+ offset = start = min(con_start, log_start);
+ dest_idx = 0;
+ while (start != log_end) {
+ unsigned log_idx_mask = start & (__LOG_BUF_LEN - 1);
+
+ log_buf[dest_idx] = __log_buf[log_idx_mask];
+ start++;
+ dest_idx++;
+ }
+ log_start -= offset;
+ con_start -= offset;
+ log_end -= offset;
+ spin_unlock_irqrestore(&logbuf_lock, flags);
+
+ pr_info("log_buf_len: %d\n", log_buf_len);
+ pr_info("early log buf free: %d(%d%%)\n",
+ free, (free * 100) / __LOG_BUF_LEN);
+}
#ifdef CONFIG_BOOT_PRINTK_DELAY
diff --git a/kernel/profile.c b/kernel/profile.c
index 66f841b..14c9f87 100644
--- a/kernel/profile.c
+++ b/kernel/profile.c
@@ -126,11 +126,9 @@
if (prof_buffer)
return 0;
- prof_buffer = vmalloc(buffer_bytes);
- if (prof_buffer) {
- memset(prof_buffer, 0, buffer_bytes);
+ prof_buffer = vzalloc(buffer_bytes);
+ if (prof_buffer)
return 0;
- }
free_cpumask_var(prof_cpu_mask);
return -ENOMEM;
diff --git a/kernel/ptrace.c b/kernel/ptrace.c
index 7a81fc0..2df1157 100644
--- a/kernel/ptrace.c
+++ b/kernel/ptrace.c
@@ -562,7 +562,7 @@
}
child->exit_code = data;
- wake_up_process(child);
+ wake_up_state(child, __TASK_TRACED);
return 0;
}
diff --git a/kernel/sched.c b/kernel/sched.c
index 0516af4..2d12893 100644
--- a/kernel/sched.c
+++ b/kernel/sched.c
@@ -293,7 +293,7 @@
* limitation from this.)
*/
#define MIN_SHARES 2
-#define MAX_SHARES (1UL << 18)
+#define MAX_SHARES (1UL << (18 + SCHED_LOAD_RESOLUTION))
static int root_task_group_load = ROOT_TASK_GROUP_LOAD;
#endif
@@ -1330,13 +1330,25 @@
{
u64 tmp;
- tmp = (u64)delta_exec * weight;
+ /*
+ * weight can be less than 2^SCHED_LOAD_RESOLUTION for task group sched
+ * entities since MIN_SHARES = 2. Treat weight as 1 if less than
+ * 2^SCHED_LOAD_RESOLUTION.
+ */
+ if (likely(weight > (1UL << SCHED_LOAD_RESOLUTION)))
+ tmp = (u64)delta_exec * scale_load_down(weight);
+ else
+ tmp = (u64)delta_exec;
if (!lw->inv_weight) {
- if (BITS_PER_LONG > 32 && unlikely(lw->weight >= WMULT_CONST))
+ unsigned long w = scale_load_down(lw->weight);
+
+ if (BITS_PER_LONG > 32 && unlikely(w >= WMULT_CONST))
lw->inv_weight = 1;
+ else if (unlikely(!w))
+ lw->inv_weight = WMULT_CONST;
else
- lw->inv_weight = WMULT_CONST / lw->weight;
+ lw->inv_weight = WMULT_CONST / w;
}
/*
@@ -1778,17 +1790,20 @@
static void set_load_weight(struct task_struct *p)
{
+ int prio = p->static_prio - MAX_RT_PRIO;
+ struct load_weight *load = &p->se.load;
+
/*
* SCHED_IDLE tasks get minimal weight:
*/
if (p->policy == SCHED_IDLE) {
- p->se.load.weight = WEIGHT_IDLEPRIO;
- p->se.load.inv_weight = WMULT_IDLEPRIO;
+ load->weight = scale_load(WEIGHT_IDLEPRIO);
+ load->inv_weight = WMULT_IDLEPRIO;
return;
}
- p->se.load.weight = prio_to_weight[p->static_prio - MAX_RT_PRIO];
- p->se.load.inv_weight = prio_to_wmult[p->static_prio - MAX_RT_PRIO];
+ load->weight = scale_load(prio_to_weight[prio]);
+ load->inv_weight = prio_to_wmult[prio];
}
static void enqueue_task(struct rq *rq, struct task_struct *p, int flags)
@@ -6527,7 +6542,7 @@
cpulist_scnprintf(str, sizeof(str), sched_group_cpus(group));
printk(KERN_CONT " %s", str);
- if (group->cpu_power != SCHED_LOAD_SCALE) {
+ if (group->cpu_power != SCHED_POWER_SCALE) {
printk(KERN_CONT " (cpu_power = %d)",
group->cpu_power);
}
@@ -7902,7 +7917,7 @@
#ifdef CONFIG_SMP
rq->sd = NULL;
rq->rd = NULL;
- rq->cpu_power = SCHED_LOAD_SCALE;
+ rq->cpu_power = SCHED_POWER_SCALE;
rq->post_schedule = 0;
rq->active_balance = 0;
rq->next_balance = jiffies;
@@ -8806,14 +8821,14 @@
static int cpu_shares_write_u64(struct cgroup *cgrp, struct cftype *cftype,
u64 shareval)
{
- return sched_group_set_shares(cgroup_tg(cgrp), shareval);
+ return sched_group_set_shares(cgroup_tg(cgrp), scale_load(shareval));
}
static u64 cpu_shares_read_u64(struct cgroup *cgrp, struct cftype *cft)
{
struct task_group *tg = cgroup_tg(cgrp);
- return (u64) tg->shares;
+ return (u64) scale_load_down(tg->shares);
}
#endif /* CONFIG_FAIR_GROUP_SCHED */
diff --git a/kernel/sched_fair.c b/kernel/sched_fair.c
index 37f2262..e32a9b7 100644
--- a/kernel/sched_fair.c
+++ b/kernel/sched_fair.c
@@ -1584,7 +1584,7 @@
}
/* Adjust by relative CPU power of the group */
- avg_load = (avg_load * SCHED_LOAD_SCALE) / group->cpu_power;
+ avg_load = (avg_load * SCHED_POWER_SCALE) / group->cpu_power;
if (local_group) {
this_load = avg_load;
@@ -1722,7 +1722,7 @@
nr_running += cpu_rq(i)->cfs.nr_running;
}
- capacity = DIV_ROUND_CLOSEST(power, SCHED_LOAD_SCALE);
+ capacity = DIV_ROUND_CLOSEST(power, SCHED_POWER_SCALE);
if (tmp->flags & SD_POWERSAVINGS_BALANCE)
nr_running /= 2;
@@ -2570,7 +2570,7 @@
unsigned long default_scale_freq_power(struct sched_domain *sd, int cpu)
{
- return SCHED_LOAD_SCALE;
+ return SCHED_POWER_SCALE;
}
unsigned long __weak arch_scale_freq_power(struct sched_domain *sd, int cpu)
@@ -2607,10 +2607,10 @@
available = total - rq->rt_avg;
}
- if (unlikely((s64)total < SCHED_LOAD_SCALE))
- total = SCHED_LOAD_SCALE;
+ if (unlikely((s64)total < SCHED_POWER_SCALE))
+ total = SCHED_POWER_SCALE;
- total >>= SCHED_LOAD_SHIFT;
+ total >>= SCHED_POWER_SHIFT;
return div_u64(available, total);
}
@@ -2618,7 +2618,7 @@
static void update_cpu_power(struct sched_domain *sd, int cpu)
{
unsigned long weight = sd->span_weight;
- unsigned long power = SCHED_LOAD_SCALE;
+ unsigned long power = SCHED_POWER_SCALE;
struct sched_group *sdg = sd->groups;
if ((sd->flags & SD_SHARE_CPUPOWER) && weight > 1) {
@@ -2627,7 +2627,7 @@
else
power *= default_scale_smt_power(sd, cpu);
- power >>= SCHED_LOAD_SHIFT;
+ power >>= SCHED_POWER_SHIFT;
}
sdg->cpu_power_orig = power;
@@ -2637,10 +2637,10 @@
else
power *= default_scale_freq_power(sd, cpu);
- power >>= SCHED_LOAD_SHIFT;
+ power >>= SCHED_POWER_SHIFT;
power *= scale_rt_power(cpu);
- power >>= SCHED_LOAD_SHIFT;
+ power >>= SCHED_POWER_SHIFT;
if (!power)
power = 1;
@@ -2682,7 +2682,7 @@
fix_small_capacity(struct sched_domain *sd, struct sched_group *group)
{
/*
- * Only siblings can have significantly less than SCHED_LOAD_SCALE
+ * Only siblings can have significantly less than SCHED_POWER_SCALE
*/
if (!(sd->flags & SD_SHARE_CPUPOWER))
return 0;
@@ -2770,7 +2770,7 @@
}
/* Adjust by relative CPU power of the group */
- sgs->avg_load = (sgs->group_load * SCHED_LOAD_SCALE) / group->cpu_power;
+ sgs->avg_load = (sgs->group_load*SCHED_POWER_SCALE) / group->cpu_power;
/*
* Consider the group unbalanced when the imbalance is larger
@@ -2787,7 +2787,8 @@
if ((max_cpu_load - min_cpu_load) >= avg_load_per_task && max_nr_running > 1)
sgs->group_imb = 1;
- sgs->group_capacity = DIV_ROUND_CLOSEST(group->cpu_power, SCHED_LOAD_SCALE);
+ sgs->group_capacity = DIV_ROUND_CLOSEST(group->cpu_power,
+ SCHED_POWER_SCALE);
if (!sgs->group_capacity)
sgs->group_capacity = fix_small_capacity(sd, group);
sgs->group_weight = group->group_weight;
@@ -2961,7 +2962,7 @@
return 0;
*imbalance = DIV_ROUND_CLOSEST(sds->max_load * sds->busiest->cpu_power,
- SCHED_LOAD_SCALE);
+ SCHED_POWER_SCALE);
return 1;
}
@@ -2990,7 +2991,7 @@
cpu_avg_load_per_task(this_cpu);
scaled_busy_load_per_task = sds->busiest_load_per_task
- * SCHED_LOAD_SCALE;
+ * SCHED_POWER_SCALE;
scaled_busy_load_per_task /= sds->busiest->cpu_power;
if (sds->max_load - sds->this_load + scaled_busy_load_per_task >=
@@ -3009,10 +3010,10 @@
min(sds->busiest_load_per_task, sds->max_load);
pwr_now += sds->this->cpu_power *
min(sds->this_load_per_task, sds->this_load);
- pwr_now /= SCHED_LOAD_SCALE;
+ pwr_now /= SCHED_POWER_SCALE;
/* Amount of load we'd subtract */
- tmp = (sds->busiest_load_per_task * SCHED_LOAD_SCALE) /
+ tmp = (sds->busiest_load_per_task * SCHED_POWER_SCALE) /
sds->busiest->cpu_power;
if (sds->max_load > tmp)
pwr_move += sds->busiest->cpu_power *
@@ -3020,15 +3021,15 @@
/* Amount of load we'd add */
if (sds->max_load * sds->busiest->cpu_power <
- sds->busiest_load_per_task * SCHED_LOAD_SCALE)
+ sds->busiest_load_per_task * SCHED_POWER_SCALE)
tmp = (sds->max_load * sds->busiest->cpu_power) /
sds->this->cpu_power;
else
- tmp = (sds->busiest_load_per_task * SCHED_LOAD_SCALE) /
+ tmp = (sds->busiest_load_per_task * SCHED_POWER_SCALE) /
sds->this->cpu_power;
pwr_move += sds->this->cpu_power *
min(sds->this_load_per_task, sds->this_load + tmp);
- pwr_move /= SCHED_LOAD_SCALE;
+ pwr_move /= SCHED_POWER_SCALE;
/* Move if we gain throughput */
if (pwr_move > pwr_now)
@@ -3070,7 +3071,7 @@
load_above_capacity = (sds->busiest_nr_running -
sds->busiest_group_capacity);
- load_above_capacity *= (SCHED_LOAD_SCALE * SCHED_LOAD_SCALE);
+ load_above_capacity *= (SCHED_LOAD_SCALE * SCHED_POWER_SCALE);
load_above_capacity /= sds->busiest->cpu_power;
}
@@ -3090,7 +3091,7 @@
/* How much load to actually move to equalise the imbalance */
*imbalance = min(max_pull * sds->busiest->cpu_power,
(sds->avg_load - sds->this_load) * sds->this->cpu_power)
- / SCHED_LOAD_SCALE;
+ / SCHED_POWER_SCALE;
/*
* if *imbalance is less than the average load per runnable task
@@ -3159,7 +3160,7 @@
if (!sds.busiest || sds.busiest_nr_running == 0)
goto out_balanced;
- sds.avg_load = (SCHED_LOAD_SCALE * sds.total_load) / sds.total_pwr;
+ sds.avg_load = (SCHED_POWER_SCALE * sds.total_load) / sds.total_pwr;
/*
* If the busiest group is imbalanced the below checks don't
@@ -3238,7 +3239,8 @@
for_each_cpu(i, sched_group_cpus(group)) {
unsigned long power = power_of(i);
- unsigned long capacity = DIV_ROUND_CLOSEST(power, SCHED_LOAD_SCALE);
+ unsigned long capacity = DIV_ROUND_CLOSEST(power,
+ SCHED_POWER_SCALE);
unsigned long wl;
if (!capacity)
@@ -3263,7 +3265,7 @@
* the load can be moved away from the cpu that is potentially
* running at a lower capacity.
*/
- wl = (wl * SCHED_LOAD_SCALE) / power;
+ wl = (wl * SCHED_POWER_SCALE) / power;
if (wl > max_load) {
max_load = wl;
diff --git a/kernel/signal.c b/kernel/signal.c
index ad5e818..86c32b8 100644
--- a/kernel/signal.c
+++ b/kernel/signal.c
@@ -3023,8 +3023,10 @@
SYSCALL_DEFINE0(pause)
{
- current->state = TASK_INTERRUPTIBLE;
- schedule();
+ while (!signal_pending(current)) {
+ current->state = TASK_INTERRUPTIBLE;
+ schedule();
+ }
return -ERESTARTNOHAND;
}
diff --git a/kernel/sysctl.c b/kernel/sysctl.c
index 3dd0c46..4fc9244 100644
--- a/kernel/sysctl.c
+++ b/kernel/sysctl.c
@@ -56,6 +56,7 @@
#include <linux/kprobes.h>
#include <linux/pipe_fs_i.h>
#include <linux/oom.h>
+#include <linux/kmod.h>
#include <asm/uaccess.h>
#include <asm/processor.h>
@@ -616,6 +617,11 @@
.child = random_table,
},
{
+ .procname = "usermodehelper",
+ .mode = 0555,
+ .child = usermodehelper_table,
+ },
+ {
.procname = "overflowuid",
.data = &overflowuid,
.maxlen = sizeof(int),
@@ -1500,7 +1506,7 @@
static struct ctl_table debug_table[] = {
#if defined(CONFIG_X86) || defined(CONFIG_PPC) || defined(CONFIG_SPARC) || \
- defined(CONFIG_S390)
+ defined(CONFIG_S390) || defined(CONFIG_TILE)
{
.procname = "exception-trace",
.data = &show_unhandled_signals,
diff --git a/kernel/time/alarmtimer.c b/kernel/time/alarmtimer.c
index 9265014..2d96624 100644
--- a/kernel/time/alarmtimer.c
+++ b/kernel/time/alarmtimer.c
@@ -494,7 +494,7 @@
*/
static long __sched alarm_timer_nsleep_restart(struct restart_block *restart)
{
- enum alarmtimer_type type = restart->nanosleep.index;
+ enum alarmtimer_type type = restart->nanosleep.clockid;
ktime_t exp;
struct timespec __user *rmtp;
struct alarm alarm;
@@ -573,7 +573,7 @@
restart = ¤t_thread_info()->restart_block;
restart->fn = alarm_timer_nsleep_restart;
- restart->nanosleep.index = type;
+ restart->nanosleep.clockid = type;
restart->nanosleep.expires = exp.tv64;
restart->nanosleep.rmtp = rmtp;
ret = -ERESTART_RESTARTBLOCK;
@@ -669,12 +669,20 @@
*/
static int __init alarmtimer_init_late(void)
{
+ struct device *dev;
char *str;
/* Find an rtc device and init the rtc_timer */
- class_find_device(rtc_class, NULL, &str, has_wakealarm);
- if (str)
+ dev = class_find_device(rtc_class, NULL, &str, has_wakealarm);
+ /* If we have a device then str is valid. See has_wakealarm() */
+ if (dev) {
rtcdev = rtc_class_open(str);
+ /*
+ * Drop the reference we got in class_find_device,
+ * rtc_open takes its own.
+ */
+ put_device(dev);
+ }
if (!rtcdev) {
printk(KERN_WARNING "No RTC device found, ALARM timers will"
" not wake from suspend");
diff --git a/kernel/time/tick-broadcast.c b/kernel/time/tick-broadcast.c
index 723c763..c7218d1 100644
--- a/kernel/time/tick-broadcast.c
+++ b/kernel/time/tick-broadcast.c
@@ -456,23 +456,27 @@
unsigned long flags;
int cpu;
- raw_spin_lock_irqsave(&tick_broadcast_lock, flags);
-
/*
* Periodic mode does not care about the enter/exit of power
* states
*/
if (tick_broadcast_device.mode == TICKDEV_MODE_PERIODIC)
- goto out;
+ return;
- bc = tick_broadcast_device.evtdev;
+ /*
+ * We are called with preemtion disabled from the depth of the
+ * idle code, so we can't be moved away.
+ */
cpu = smp_processor_id();
td = &per_cpu(tick_cpu_device, cpu);
dev = td->evtdev;
if (!(dev->features & CLOCK_EVT_FEAT_C3STOP))
- goto out;
+ return;
+ bc = tick_broadcast_device.evtdev;
+
+ raw_spin_lock_irqsave(&tick_broadcast_lock, flags);
if (reason == CLOCK_EVT_NOTIFY_BROADCAST_ENTER) {
if (!cpumask_test_cpu(cpu, tick_get_broadcast_oneshot_mask())) {
cpumask_set_cpu(cpu, tick_get_broadcast_oneshot_mask());
@@ -489,8 +493,6 @@
tick_program_event(dev->next_event, 1);
}
}
-
-out:
raw_spin_unlock_irqrestore(&tick_broadcast_lock, flags);
}
diff --git a/kernel/time/timekeeping.c b/kernel/time/timekeeping.c
index 8e6a05a..342408c 100644
--- a/kernel/time/timekeeping.c
+++ b/kernel/time/timekeeping.c
@@ -680,7 +680,7 @@
clockevents_notify(CLOCK_EVT_NOTIFY_RESUME, NULL);
/* Resume hrtimers */
- hres_timers_resume();
+ hrtimers_resume();
}
static int timekeeping_suspend(void)
@@ -1099,6 +1099,21 @@
}
/**
+ * ktime_get_monotonic_offset() - get wall_to_monotonic in ktime_t format
+ */
+ktime_t ktime_get_monotonic_offset(void)
+{
+ unsigned long seq;
+ struct timespec wtom;
+
+ do {
+ seq = read_seqbegin(&xtime_lock);
+ wtom = wall_to_monotonic;
+ } while (read_seqretry(&xtime_lock, seq));
+ return timespec_to_ktime(wtom);
+}
+
+/**
* xtime_update() - advances the timekeeping infrastructure
* @ticks: number of ticks, that have elapsed since the last call.
*
diff --git a/kernel/watchdog.c b/kernel/watchdog.c
index 6e63097..7daa4b0 100644
--- a/kernel/watchdog.c
+++ b/kernel/watchdog.c
@@ -98,7 +98,7 @@
* the thresholds with a factor: we make the soft threshold twice the amount of
* time the hard threshold is.
*/
-static int get_softlockup_thresh()
+static int get_softlockup_thresh(void)
{
return watchdog_thresh * 2;
}
diff --git a/kernel/workqueue.c b/kernel/workqueue.c
index e3378e8..0400553 100644
--- a/kernel/workqueue.c
+++ b/kernel/workqueue.c
@@ -2866,9 +2866,7 @@
}
}
- /* just in case, make sure it's actually aligned
- * - this is affected by PERCPU() alignment in vmlinux.lds.S
- */
+ /* just in case, make sure it's actually aligned */
BUG_ON(!IS_ALIGNED(wq->cpu_wq.v, align));
return wq->cpu_wq.v ? 0 : -ENOMEM;
}
diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug
index 0efcdca..28afa4c 100644
--- a/lib/Kconfig.debug
+++ b/lib/Kconfig.debug
@@ -670,6 +670,15 @@
bool
depends on STACKTRACE_SUPPORT
+config DEBUG_STACK_USAGE
+ bool "Stack utilization instrumentation"
+ depends on DEBUG_KERNEL
+ help
+ Enables the display of the minimum amount of free stack which each
+ task has ever had available in the sysrq-T and sysrq-P debug output.
+
+ This option will slow down process creation somewhat.
+
config DEBUG_KOBJECT
bool "kobject debugging"
depends on DEBUG_KERNEL
@@ -983,6 +992,17 @@
To ensure that generic code follows the above rules, this
option forces all percpu variables to be defined as weak.
+config DEBUG_PER_CPU_MAPS
+ bool "Debug access to per_cpu maps"
+ depends on DEBUG_KERNEL
+ depends on SMP
+ help
+ Say Y to verify that the per_cpu map being accessed has
+ been set up. This adds a fair amount of code to kernel memory
+ and decreases performance.
+
+ Say N if unsure.
+
config LKDTM
tristate "Linux Kernel Dump Test Tool Module"
depends on DEBUG_FS
diff --git a/lib/audit.c b/lib/audit.c
index 8e7dc1c..76bbed4 100644
--- a/lib/audit.c
+++ b/lib/audit.c
@@ -36,8 +36,10 @@
int audit_classify_syscall(int abi, unsigned syscall)
{
switch(syscall) {
+#ifdef __NR_open
case __NR_open:
return 2;
+#endif
#ifdef __NR_openat
case __NR_openat:
return 3;
diff --git a/lib/bitmap.c b/lib/bitmap.c
index 91e0ccf..41baf02 100644
--- a/lib/bitmap.c
+++ b/lib/bitmap.c
@@ -571,8 +571,11 @@
EXPORT_SYMBOL(bitmap_scnlistprintf);
/**
- * bitmap_parselist - convert list format ASCII string to bitmap
+ * __bitmap_parselist - convert list format ASCII string to bitmap
* @bp: read nul-terminated user string from this buffer
+ * @buflen: buffer size in bytes. If string is smaller than this
+ * then it must be terminated with a \0.
+ * @is_user: location of buffer, 0 indicates kernel space
* @maskp: write resulting mask here
* @nmaskbits: number of bits in mask to be written
*
@@ -587,20 +590,63 @@
* %-EINVAL: invalid character in string
* %-ERANGE: bit number specified too large for mask
*/
-int bitmap_parselist(const char *bp, unsigned long *maskp, int nmaskbits)
+static int __bitmap_parselist(const char *buf, unsigned int buflen,
+ int is_user, unsigned long *maskp,
+ int nmaskbits)
{
unsigned a, b;
+ int c, old_c, totaldigits;
+ const char __user *ubuf = buf;
+ int exp_digit, in_range;
+ totaldigits = c = 0;
bitmap_zero(maskp, nmaskbits);
do {
- if (!isdigit(*bp))
- return -EINVAL;
- b = a = simple_strtoul(bp, (char **)&bp, BASEDEC);
- if (*bp == '-') {
- bp++;
- if (!isdigit(*bp))
+ exp_digit = 1;
+ in_range = 0;
+ a = b = 0;
+
+ /* Get the next cpu# or a range of cpu#'s */
+ while (buflen) {
+ old_c = c;
+ if (is_user) {
+ if (__get_user(c, ubuf++))
+ return -EFAULT;
+ } else
+ c = *buf++;
+ buflen--;
+ if (isspace(c))
+ continue;
+
+ /*
+ * If the last character was a space and the current
+ * character isn't '\0', we've got embedded whitespace.
+ * This is a no-no, so throw an error.
+ */
+ if (totaldigits && c && isspace(old_c))
return -EINVAL;
- b = simple_strtoul(bp, (char **)&bp, BASEDEC);
+
+ /* A '\0' or a ',' signal the end of a cpu# or range */
+ if (c == '\0' || c == ',')
+ break;
+
+ if (c == '-') {
+ if (exp_digit || in_range)
+ return -EINVAL;
+ b = 0;
+ in_range = 1;
+ exp_digit = 1;
+ continue;
+ }
+
+ if (!isdigit(c))
+ return -EINVAL;
+
+ b = b * 10 + (c - '0');
+ if (!in_range)
+ a = b;
+ exp_digit = 0;
+ totaldigits++;
}
if (!(a <= b))
return -EINVAL;
@@ -610,13 +656,52 @@
set_bit(a, maskp);
a++;
}
- if (*bp == ',')
- bp++;
- } while (*bp != '\0' && *bp != '\n');
+ } while (buflen && c == ',');
return 0;
}
+
+int bitmap_parselist(const char *bp, unsigned long *maskp, int nmaskbits)
+{
+ char *nl = strchr(bp, '\n');
+ int len;
+
+ if (nl)
+ len = nl - bp;
+ else
+ len = strlen(bp);
+
+ return __bitmap_parselist(bp, len, 0, maskp, nmaskbits);
+}
EXPORT_SYMBOL(bitmap_parselist);
+
+/**
+ * bitmap_parselist_user()
+ *
+ * @ubuf: pointer to user buffer containing string.
+ * @ulen: buffer size in bytes. If string is smaller than this
+ * then it must be terminated with a \0.
+ * @maskp: pointer to bitmap array that will contain result.
+ * @nmaskbits: size of bitmap, in bits.
+ *
+ * Wrapper for bitmap_parselist(), providing it with user buffer.
+ *
+ * We cannot have this as an inline function in bitmap.h because it needs
+ * linux/uaccess.h to get the access_ok() declaration and this causes
+ * cyclic dependencies.
+ */
+int bitmap_parselist_user(const char __user *ubuf,
+ unsigned int ulen, unsigned long *maskp,
+ int nmaskbits)
+{
+ if (!access_ok(VERIFY_READ, ubuf, ulen))
+ return -EFAULT;
+ return __bitmap_parselist((const char *)ubuf,
+ ulen, 1, maskp, nmaskbits);
+}
+EXPORT_SYMBOL(bitmap_parselist_user);
+
+
/**
* bitmap_pos_to_ord - find ordinal of set bit at given position in bitmap
* @buf: pointer to a bitmap
diff --git a/lib/flex_array.c b/lib/flex_array.c
index 854b57b..cab7621 100644
--- a/lib/flex_array.c
+++ b/lib/flex_array.c
@@ -88,8 +88,11 @@
gfp_t flags)
{
struct flex_array *ret;
- int max_size = FLEX_ARRAY_NR_BASE_PTRS *
- FLEX_ARRAY_ELEMENTS_PER_PART(element_size);
+ int max_size = 0;
+
+ if (element_size)
+ max_size = FLEX_ARRAY_NR_BASE_PTRS *
+ FLEX_ARRAY_ELEMENTS_PER_PART(element_size);
/* max_size will end up 0 if element_size > PAGE_SIZE */
if (total > max_size)
@@ -183,15 +186,18 @@
int flex_array_put(struct flex_array *fa, unsigned int element_nr, void *src,
gfp_t flags)
{
- int part_nr = fa_element_to_part_nr(fa, element_nr);
+ int part_nr;
struct flex_array_part *part;
void *dst;
if (element_nr >= fa->total_nr_elements)
return -ENOSPC;
+ if (!fa->element_size)
+ return 0;
if (elements_fit_in_base(fa))
part = (struct flex_array_part *)&fa->parts[0];
else {
+ part_nr = fa_element_to_part_nr(fa, element_nr);
part = __fa_get_part(fa, part_nr, flags);
if (!part)
return -ENOMEM;
@@ -211,15 +217,18 @@
*/
int flex_array_clear(struct flex_array *fa, unsigned int element_nr)
{
- int part_nr = fa_element_to_part_nr(fa, element_nr);
+ int part_nr;
struct flex_array_part *part;
void *dst;
if (element_nr >= fa->total_nr_elements)
return -ENOSPC;
+ if (!fa->element_size)
+ return 0;
if (elements_fit_in_base(fa))
part = (struct flex_array_part *)&fa->parts[0];
else {
+ part_nr = fa_element_to_part_nr(fa, element_nr);
part = fa->parts[part_nr];
if (!part)
return -EINVAL;
@@ -264,6 +273,8 @@
if (end >= fa->total_nr_elements)
return -ENOSPC;
+ if (!fa->element_size)
+ return 0;
if (elements_fit_in_base(fa))
return 0;
start_part = fa_element_to_part_nr(fa, start);
@@ -291,14 +302,17 @@
*/
void *flex_array_get(struct flex_array *fa, unsigned int element_nr)
{
- int part_nr = fa_element_to_part_nr(fa, element_nr);
+ int part_nr;
struct flex_array_part *part;
+ if (!fa->element_size)
+ return NULL;
if (element_nr >= fa->total_nr_elements)
return NULL;
if (elements_fit_in_base(fa))
part = (struct flex_array_part *)&fa->parts[0];
else {
+ part_nr = fa_element_to_part_nr(fa, element_nr);
part = fa->parts[part_nr];
if (!part)
return NULL;
@@ -353,7 +367,7 @@
int part_nr;
int ret = 0;
- if (!fa->total_nr_elements)
+ if (!fa->total_nr_elements || !fa->element_size)
return 0;
if (elements_fit_in_base(fa))
return ret;
diff --git a/lib/genalloc.c b/lib/genalloc.c
index 1923f14..577ddf8 100644
--- a/lib/genalloc.c
+++ b/lib/genalloc.c
@@ -39,17 +39,20 @@
EXPORT_SYMBOL(gen_pool_create);
/**
- * gen_pool_add - add a new chunk of special memory to the pool
+ * gen_pool_add_virt - add a new chunk of special memory to the pool
* @pool: pool to add new memory chunk to
- * @addr: starting address of memory chunk to add to pool
+ * @virt: virtual starting address of memory chunk to add to pool
+ * @phys: physical starting address of memory chunk to add to pool
* @size: size in bytes of the memory chunk to add to pool
* @nid: node id of the node the chunk structure and bitmap should be
* allocated on, or -1
*
* Add a new chunk of special memory to the specified pool.
+ *
+ * Returns 0 on success or a -ve errno on failure.
*/
-int gen_pool_add(struct gen_pool *pool, unsigned long addr, size_t size,
- int nid)
+int gen_pool_add_virt(struct gen_pool *pool, unsigned long virt, phys_addr_t phys,
+ size_t size, int nid)
{
struct gen_pool_chunk *chunk;
int nbits = size >> pool->min_alloc_order;
@@ -58,11 +61,12 @@
chunk = kmalloc_node(nbytes, GFP_KERNEL | __GFP_ZERO, nid);
if (unlikely(chunk == NULL))
- return -1;
+ return -ENOMEM;
spin_lock_init(&chunk->lock);
- chunk->start_addr = addr;
- chunk->end_addr = addr + size;
+ chunk->phys_addr = phys;
+ chunk->start_addr = virt;
+ chunk->end_addr = virt + size;
write_lock(&pool->lock);
list_add(&chunk->next_chunk, &pool->chunks);
@@ -70,7 +74,32 @@
return 0;
}
-EXPORT_SYMBOL(gen_pool_add);
+EXPORT_SYMBOL(gen_pool_add_virt);
+
+/**
+ * gen_pool_virt_to_phys - return the physical address of memory
+ * @pool: pool to allocate from
+ * @addr: starting address of memory
+ *
+ * Returns the physical address on success, or -1 on error.
+ */
+phys_addr_t gen_pool_virt_to_phys(struct gen_pool *pool, unsigned long addr)
+{
+ struct list_head *_chunk;
+ struct gen_pool_chunk *chunk;
+
+ read_lock(&pool->lock);
+ list_for_each(_chunk, &pool->chunks) {
+ chunk = list_entry(_chunk, struct gen_pool_chunk, next_chunk);
+
+ if (addr >= chunk->start_addr && addr < chunk->end_addr)
+ return chunk->phys_addr + addr - chunk->start_addr;
+ }
+ read_unlock(&pool->lock);
+
+ return -1;
+}
+EXPORT_SYMBOL(gen_pool_virt_to_phys);
/**
* gen_pool_destroy - destroy a special memory pool
diff --git a/lib/kstrtox.c b/lib/kstrtox.c
index a235f3c..2dbae88 100644
--- a/lib/kstrtox.c
+++ b/lib/kstrtox.c
@@ -17,6 +17,7 @@
#include <linux/math64.h>
#include <linux/module.h>
#include <linux/types.h>
+#include <asm/uaccess.h>
static inline char _tolower(const char c)
{
@@ -222,3 +223,28 @@
return 0;
}
EXPORT_SYMBOL(kstrtos8);
+
+#define kstrto_from_user(f, g, type) \
+int f(const char __user *s, size_t count, unsigned int base, type *res) \
+{ \
+ /* sign, base 2 representation, newline, terminator */ \
+ char buf[1 + sizeof(type) * 8 + 1 + 1]; \
+ \
+ count = min(count, sizeof(buf) - 1); \
+ if (copy_from_user(buf, s, count)) \
+ return -EFAULT; \
+ buf[count] = '\0'; \
+ return g(buf, base, res); \
+} \
+EXPORT_SYMBOL(f)
+
+kstrto_from_user(kstrtoull_from_user, kstrtoull, unsigned long long);
+kstrto_from_user(kstrtoll_from_user, kstrtoll, long long);
+kstrto_from_user(kstrtoul_from_user, kstrtoul, unsigned long);
+kstrto_from_user(kstrtol_from_user, kstrtol, long);
+kstrto_from_user(kstrtouint_from_user, kstrtouint, unsigned int);
+kstrto_from_user(kstrtoint_from_user, kstrtoint, int);
+kstrto_from_user(kstrtou16_from_user, kstrtou16, u16);
+kstrto_from_user(kstrtos16_from_user, kstrtos16, s16);
+kstrto_from_user(kstrtou8_from_user, kstrtou8, u8);
+kstrto_from_user(kstrtos8_from_user, kstrtos8, s8);
diff --git a/lib/lru_cache.c b/lib/lru_cache.c
index 270de9d..a07e726 100644
--- a/lib/lru_cache.c
+++ b/lib/lru_cache.c
@@ -84,7 +84,7 @@
if (e_count > LC_MAX_ACTIVE)
return NULL;
- slot = kzalloc(e_count * sizeof(struct hlist_head*), GFP_KERNEL);
+ slot = kcalloc(e_count, sizeof(struct hlist_head), GFP_KERNEL);
if (!slot)
goto out_fail;
element = kzalloc(e_count * sizeof(struct lc_element *), GFP_KERNEL);
diff --git a/lib/show_mem.c b/lib/show_mem.c
index 90cbe4b..4407f8c 100644
--- a/lib/show_mem.c
+++ b/lib/show_mem.c
@@ -16,7 +16,7 @@
nonshared = 0, highmem = 0;
printk("Mem-Info:\n");
- __show_free_areas(filter);
+ show_free_areas(filter);
for_each_online_pgdat(pgdat) {
unsigned long i, flags;
diff --git a/lib/vsprintf.c b/lib/vsprintf.c
index 1d659d7..c112056 100644
--- a/lib/vsprintf.c
+++ b/lib/vsprintf.c
@@ -898,7 +898,7 @@
case 'U':
return uuid_string(buf, end, ptr, spec, fmt);
case 'V':
- return buf + vsnprintf(buf, end - buf,
+ return buf + vsnprintf(buf, end > buf ? end - buf : 0,
((struct va_format *)ptr)->fmt,
*(((struct va_format *)ptr)->va));
case 'K':
diff --git a/mm/backing-dev.c b/mm/backing-dev.c
index befc875..f032e6e 100644
--- a/mm/backing-dev.c
+++ b/mm/backing-dev.c
@@ -63,10 +63,10 @@
unsigned long background_thresh;
unsigned long dirty_thresh;
unsigned long bdi_thresh;
- unsigned long nr_dirty, nr_io, nr_more_io, nr_wb;
+ unsigned long nr_dirty, nr_io, nr_more_io;
struct inode *inode;
- nr_wb = nr_dirty = nr_io = nr_more_io = 0;
+ nr_dirty = nr_io = nr_more_io = 0;
spin_lock(&inode_wb_list_lock);
list_for_each_entry(inode, &wb->b_dirty, i_wb_list)
nr_dirty++;
diff --git a/mm/filemap.c b/mm/filemap.c
index c641edf..68e782b 100644
--- a/mm/filemap.c
+++ b/mm/filemap.c
@@ -58,16 +58,16 @@
/*
* Lock ordering:
*
- * ->i_mmap_lock (truncate_pagecache)
+ * ->i_mmap_mutex (truncate_pagecache)
* ->private_lock (__free_pte->__set_page_dirty_buffers)
* ->swap_lock (exclusive_swap_page, others)
* ->mapping->tree_lock
*
* ->i_mutex
- * ->i_mmap_lock (truncate->unmap_mapping_range)
+ * ->i_mmap_mutex (truncate->unmap_mapping_range)
*
* ->mmap_sem
- * ->i_mmap_lock
+ * ->i_mmap_mutex
* ->page_table_lock or pte_lock (various, mainly in memory.c)
* ->mapping->tree_lock (arch-dependent flush_dcache_mmap_lock)
*
@@ -84,7 +84,7 @@
* sb_lock (fs/fs-writeback.c)
* ->mapping->tree_lock (__sync_single_inode)
*
- * ->i_mmap_lock
+ * ->i_mmap_mutex
* ->anon_vma.lock (vma_adjust)
*
* ->anon_vma.lock
@@ -106,7 +106,7 @@
*
* (code doesn't rely on that order, so you could switch it around)
* ->tasklist_lock (memory_failure, collect_procs_ao)
- * ->i_mmap_lock
+ * ->i_mmap_mutex
*/
/*
@@ -562,6 +562,17 @@
}
EXPORT_SYMBOL(wait_on_page_bit);
+int wait_on_page_bit_killable(struct page *page, int bit_nr)
+{
+ DEFINE_WAIT_BIT(wait, &page->flags, bit_nr);
+
+ if (!test_bit(bit_nr, &page->flags))
+ return 0;
+
+ return __wait_on_bit(page_waitqueue(page), &wait,
+ sleep_on_page_killable, TASK_KILLABLE);
+}
+
/**
* add_page_wait_queue - Add an arbitrary waiter to a page's wait queue
* @page: Page defining the wait queue of interest
@@ -643,15 +654,32 @@
int __lock_page_or_retry(struct page *page, struct mm_struct *mm,
unsigned int flags)
{
- if (!(flags & FAULT_FLAG_ALLOW_RETRY)) {
- __lock_page(page);
- return 1;
- } else {
- if (!(flags & FAULT_FLAG_RETRY_NOWAIT)) {
- up_read(&mm->mmap_sem);
+ if (flags & FAULT_FLAG_ALLOW_RETRY) {
+ /*
+ * CAUTION! In this case, mmap_sem is not released
+ * even though return 0.
+ */
+ if (flags & FAULT_FLAG_RETRY_NOWAIT)
+ return 0;
+
+ up_read(&mm->mmap_sem);
+ if (flags & FAULT_FLAG_KILLABLE)
+ wait_on_page_locked_killable(page);
+ else
wait_on_page_locked(page);
- }
return 0;
+ } else {
+ if (flags & FAULT_FLAG_KILLABLE) {
+ int ret;
+
+ ret = __lock_page_killable(page);
+ if (ret) {
+ up_read(&mm->mmap_sem);
+ return 0;
+ }
+ } else
+ __lock_page(page);
+ return 1;
}
}
@@ -1528,15 +1556,17 @@
/* If we don't want any read-ahead, don't bother */
if (VM_RandomReadHint(vma))
return;
+ if (!ra->ra_pages)
+ return;
- if (VM_SequentialReadHint(vma) ||
- offset - 1 == (ra->prev_pos >> PAGE_CACHE_SHIFT)) {
+ if (VM_SequentialReadHint(vma)) {
page_cache_sync_readahead(mapping, ra, file, offset,
ra->ra_pages);
return;
}
- if (ra->mmap_miss < INT_MAX)
+ /* Avoid banging the cache line if not needed */
+ if (ra->mmap_miss < MMAP_LOTSAMISS * 10)
ra->mmap_miss++;
/*
@@ -1550,12 +1580,10 @@
* mmap read-around
*/
ra_pages = max_sane_readahead(ra->ra_pages);
- if (ra_pages) {
- ra->start = max_t(long, 0, offset - ra_pages/2);
- ra->size = ra_pages;
- ra->async_size = 0;
- ra_submit(ra, mapping, file);
- }
+ ra->start = max_t(long, 0, offset - ra_pages / 2);
+ ra->size = ra_pages;
+ ra->async_size = ra_pages / 4;
+ ra_submit(ra, mapping, file);
}
/*
@@ -1660,7 +1688,6 @@
return VM_FAULT_SIGBUS;
}
- ra->prev_pos = (loff_t)offset << PAGE_CACHE_SHIFT;
vmf->page = page;
return ret | VM_FAULT_LOCKED;
diff --git a/mm/filemap_xip.c b/mm/filemap_xip.c
index 83364df..93356cd 100644
--- a/mm/filemap_xip.c
+++ b/mm/filemap_xip.c
@@ -183,7 +183,7 @@
return;
retry:
- spin_lock(&mapping->i_mmap_lock);
+ mutex_lock(&mapping->i_mmap_mutex);
vma_prio_tree_foreach(vma, &iter, &mapping->i_mmap, pgoff, pgoff) {
mm = vma->vm_mm;
address = vma->vm_start +
@@ -201,7 +201,7 @@
page_cache_release(page);
}
}
- spin_unlock(&mapping->i_mmap_lock);
+ mutex_unlock(&mapping->i_mmap_mutex);
if (locked) {
mutex_unlock(&xip_sparse_mutex);
diff --git a/mm/fremap.c b/mm/fremap.c
index ec520c7..7f41230 100644
--- a/mm/fremap.c
+++ b/mm/fremap.c
@@ -211,13 +211,13 @@
}
goto out;
}
- spin_lock(&mapping->i_mmap_lock);
+ mutex_lock(&mapping->i_mmap_mutex);
flush_dcache_mmap_lock(mapping);
vma->vm_flags |= VM_NONLINEAR;
vma_prio_tree_remove(vma, &mapping->i_mmap);
vma_nonlinear_insert(vma, &mapping->i_mmap_nonlinear);
flush_dcache_mmap_unlock(mapping);
- spin_unlock(&mapping->i_mmap_lock);
+ mutex_unlock(&mapping->i_mmap_mutex);
}
if (vma->vm_flags & VM_LOCKED) {
diff --git a/mm/huge_memory.c b/mm/huge_memory.c
index 83326ad..615d974 100644
--- a/mm/huge_memory.c
+++ b/mm/huge_memory.c
@@ -1139,7 +1139,7 @@
* We can't temporarily set the pmd to null in order
* to split it, the pmd must remain marked huge at all
* times or the VM won't take the pmd_trans_huge paths
- * and it won't wait on the anon_vma->root->lock to
+ * and it won't wait on the anon_vma->root->mutex to
* serialize against split_huge_page*.
*/
pmdp_splitting_flush_notify(vma, address, pmd);
@@ -1333,7 +1333,7 @@
return ret;
}
-/* must be called with anon_vma->root->lock hold */
+/* must be called with anon_vma->root->mutex hold */
static void __split_huge_page(struct page *page,
struct anon_vma *anon_vma)
{
@@ -1771,12 +1771,9 @@
VM_BUG_ON(address & ~HPAGE_PMD_MASK);
#ifndef CONFIG_NUMA
+ up_read(&mm->mmap_sem);
VM_BUG_ON(!*hpage);
new_page = *hpage;
- if (unlikely(mem_cgroup_newpage_charge(new_page, mm, GFP_KERNEL))) {
- up_read(&mm->mmap_sem);
- return;
- }
#else
VM_BUG_ON(*hpage);
/*
@@ -1791,22 +1788,26 @@
*/
new_page = alloc_hugepage_vma(khugepaged_defrag(), vma, address,
node, __GFP_OTHER_NODE);
+
+ /*
+ * After allocating the hugepage, release the mmap_sem read lock in
+ * preparation for taking it in write mode.
+ */
+ up_read(&mm->mmap_sem);
if (unlikely(!new_page)) {
- up_read(&mm->mmap_sem);
count_vm_event(THP_COLLAPSE_ALLOC_FAILED);
*hpage = ERR_PTR(-ENOMEM);
return;
}
- count_vm_event(THP_COLLAPSE_ALLOC);
- if (unlikely(mem_cgroup_newpage_charge(new_page, mm, GFP_KERNEL))) {
- up_read(&mm->mmap_sem);
- put_page(new_page);
- return;
- }
#endif
- /* after allocating the hugepage upgrade to mmap_sem write mode */
- up_read(&mm->mmap_sem);
+ count_vm_event(THP_COLLAPSE_ALLOC);
+ if (unlikely(mem_cgroup_newpage_charge(new_page, mm, GFP_KERNEL))) {
+#ifdef CONFIG_NUMA
+ put_page(new_page);
+#endif
+ return;
+ }
/*
* Prevent all access to pagetables with the exception of
diff --git a/mm/hugetlb.c b/mm/hugetlb.c
index bbb4a5b..5fd68b9 100644
--- a/mm/hugetlb.c
+++ b/mm/hugetlb.c
@@ -2205,7 +2205,7 @@
unsigned long sz = huge_page_size(h);
/*
- * A page gathering list, protected by per file i_mmap_lock. The
+ * A page gathering list, protected by per file i_mmap_mutex. The
* lock is used to avoid list corruption from multiple unmapping
* of the same page since we are using page->lru.
*/
@@ -2274,9 +2274,9 @@
void unmap_hugepage_range(struct vm_area_struct *vma, unsigned long start,
unsigned long end, struct page *ref_page)
{
- spin_lock(&vma->vm_file->f_mapping->i_mmap_lock);
+ mutex_lock(&vma->vm_file->f_mapping->i_mmap_mutex);
__unmap_hugepage_range(vma, start, end, ref_page);
- spin_unlock(&vma->vm_file->f_mapping->i_mmap_lock);
+ mutex_unlock(&vma->vm_file->f_mapping->i_mmap_mutex);
}
/*
@@ -2308,7 +2308,7 @@
* this mapping should be shared between all the VMAs,
* __unmap_hugepage_range() is called as the lock is already held
*/
- spin_lock(&mapping->i_mmap_lock);
+ mutex_lock(&mapping->i_mmap_mutex);
vma_prio_tree_foreach(iter_vma, &iter, &mapping->i_mmap, pgoff, pgoff) {
/* Do not unmap the current VMA */
if (iter_vma == vma)
@@ -2326,7 +2326,7 @@
address, address + huge_page_size(h),
page);
}
- spin_unlock(&mapping->i_mmap_lock);
+ mutex_unlock(&mapping->i_mmap_mutex);
return 1;
}
@@ -2810,7 +2810,7 @@
BUG_ON(address >= end);
flush_cache_range(vma, address, end);
- spin_lock(&vma->vm_file->f_mapping->i_mmap_lock);
+ mutex_lock(&vma->vm_file->f_mapping->i_mmap_mutex);
spin_lock(&mm->page_table_lock);
for (; address < end; address += huge_page_size(h)) {
ptep = huge_pte_offset(mm, address);
@@ -2825,7 +2825,7 @@
}
}
spin_unlock(&mm->page_table_lock);
- spin_unlock(&vma->vm_file->f_mapping->i_mmap_lock);
+ mutex_unlock(&vma->vm_file->f_mapping->i_mmap_mutex);
flush_tlb_range(vma, start, end);
}
diff --git a/mm/init-mm.c b/mm/init-mm.c
index 1d29cdf..4019979 100644
--- a/mm/init-mm.c
+++ b/mm/init-mm.c
@@ -21,6 +21,5 @@
.mmap_sem = __RWSEM_INITIALIZER(init_mm.mmap_sem),
.page_table_lock = __SPIN_LOCK_UNLOCKED(init_mm.page_table_lock),
.mmlist = LIST_HEAD_INIT(init_mm.mmlist),
- .cpu_vm_mask = CPU_MASK_ALL,
INIT_MM_CONTEXT(init_mm)
};
diff --git a/mm/internal.h b/mm/internal.h
index 9d0ced8..d071d38 100644
--- a/mm/internal.h
+++ b/mm/internal.h
@@ -66,6 +66,10 @@
return page_private(page);
}
+/* mm/util.c */
+void __vma_link_list(struct mm_struct *mm, struct vm_area_struct *vma,
+ struct vm_area_struct *prev, struct rb_node *rb_parent);
+
#ifdef CONFIG_MMU
extern long mlock_vma_pages_range(struct vm_area_struct *vma,
unsigned long start, unsigned long end);
diff --git a/mm/ksm.c b/mm/ksm.c
index 942dfc7..d708b3e 100644
--- a/mm/ksm.c
+++ b/mm/ksm.c
@@ -35,6 +35,7 @@
#include <linux/ksm.h>
#include <linux/hash.h>
#include <linux/freezer.h>
+#include <linux/oom.h>
#include <asm/tlbflush.h>
#include "internal.h"
@@ -1894,9 +1895,11 @@
if (ksm_run != flags) {
ksm_run = flags;
if (flags & KSM_RUN_UNMERGE) {
- current->flags |= PF_OOM_ORIGIN;
+ int oom_score_adj;
+
+ oom_score_adj = test_set_oom_score_adj(OOM_SCORE_ADJ_MAX);
err = unmerge_and_remove_all_rmap_items();
- current->flags &= ~PF_OOM_ORIGIN;
+ test_set_oom_score_adj(oom_score_adj);
if (err) {
ksm_run = KSM_RUN_STOP;
count = err;
diff --git a/mm/memcontrol.c b/mm/memcontrol.c
index 010f916..d5fd3dc 100644
--- a/mm/memcontrol.c
+++ b/mm/memcontrol.c
@@ -5169,19 +5169,12 @@
static int __init enable_swap_account(char *s)
{
/* consider enabled if no parameter or 1 is given */
- if (!(*s) || !strcmp(s, "=1"))
+ if (!strcmp(s, "1"))
really_do_swap_account = 1;
- else if (!strcmp(s, "=0"))
+ else if (!strcmp(s, "0"))
really_do_swap_account = 0;
return 1;
}
-__setup("swapaccount", enable_swap_account);
+__setup("swapaccount=", enable_swap_account);
-static int __init disable_swap_account(char *s)
-{
- printk_once("noswapaccount is deprecated and will be removed in 2.6.40. Use swapaccount=0 instead\n");
- enable_swap_account("=0");
- return 1;
-}
-__setup("noswapaccount", disable_swap_account);
#endif
diff --git a/mm/memory-failure.c b/mm/memory-failure.c
index 2b9a5ee..5c8f7e0 100644
--- a/mm/memory-failure.c
+++ b/mm/memory-failure.c
@@ -239,7 +239,11 @@
if (access) {
int nr;
do {
- nr = shrink_slab(1000, GFP_KERNEL, 1000);
+ struct shrink_control shrink = {
+ .gfp_mask = GFP_KERNEL,
+ };
+
+ nr = shrink_slab(&shrink, 1000, 1000);
if (page_count(p) == 1)
break;
} while (nr > 10);
@@ -429,7 +433,7 @@
*/
read_lock(&tasklist_lock);
- spin_lock(&mapping->i_mmap_lock);
+ mutex_lock(&mapping->i_mmap_mutex);
for_each_process(tsk) {
pgoff_t pgoff = page->index << (PAGE_CACHE_SHIFT - PAGE_SHIFT);
@@ -449,7 +453,7 @@
add_to_kill(tsk, page, vma, to_kill, tkc);
}
}
- spin_unlock(&mapping->i_mmap_lock);
+ mutex_unlock(&mapping->i_mmap_mutex);
read_unlock(&tasklist_lock);
}
@@ -1440,16 +1444,12 @@
*/
ret = invalidate_inode_page(page);
unlock_page(page);
-
/*
- * Drop count because page migration doesn't like raised
- * counts. The page could get re-allocated, but if it becomes
- * LRU the isolation will just fail.
* RED-PEN would be better to keep it isolated here, but we
* would need to fix isolation locking first.
*/
- put_page(page);
if (ret == 1) {
+ put_page(page);
ret = 0;
pr_info("soft_offline: %#lx: invalidated\n", pfn);
goto done;
@@ -1461,6 +1461,11 @@
* handles a large number of cases for us.
*/
ret = isolate_lru_page(page);
+ /*
+ * Drop page reference which is came from get_any_page()
+ * successful isolate_lru_page() already took another one.
+ */
+ put_page(page);
if (!ret) {
LIST_HEAD(pagelist);
diff --git a/mm/memory.c b/mm/memory.c
index 61e66f0..b73f677 100644
--- a/mm/memory.c
+++ b/mm/memory.c
@@ -182,7 +182,7 @@
{
__sync_task_rss_stat(task, mm);
}
-#else
+#else /* SPLIT_RSS_COUNTING */
#define inc_mm_counter_fast(mm, member) inc_mm_counter(mm, member)
#define dec_mm_counter_fast(mm, member) dec_mm_counter(mm, member)
@@ -191,7 +191,204 @@
{
}
+#endif /* SPLIT_RSS_COUNTING */
+
+#ifdef HAVE_GENERIC_MMU_GATHER
+
+static int tlb_next_batch(struct mmu_gather *tlb)
+{
+ struct mmu_gather_batch *batch;
+
+ batch = tlb->active;
+ if (batch->next) {
+ tlb->active = batch->next;
+ return 1;
+ }
+
+ batch = (void *)__get_free_pages(GFP_NOWAIT | __GFP_NOWARN, 0);
+ if (!batch)
+ return 0;
+
+ batch->next = NULL;
+ batch->nr = 0;
+ batch->max = MAX_GATHER_BATCH;
+
+ tlb->active->next = batch;
+ tlb->active = batch;
+
+ return 1;
+}
+
+/* tlb_gather_mmu
+ * Called to initialize an (on-stack) mmu_gather structure for page-table
+ * tear-down from @mm. The @fullmm argument is used when @mm is without
+ * users and we're going to destroy the full address space (exit/execve).
+ */
+void tlb_gather_mmu(struct mmu_gather *tlb, struct mm_struct *mm, bool fullmm)
+{
+ tlb->mm = mm;
+
+ tlb->fullmm = fullmm;
+ tlb->need_flush = 0;
+ tlb->fast_mode = (num_possible_cpus() == 1);
+ tlb->local.next = NULL;
+ tlb->local.nr = 0;
+ tlb->local.max = ARRAY_SIZE(tlb->__pages);
+ tlb->active = &tlb->local;
+
+#ifdef CONFIG_HAVE_RCU_TABLE_FREE
+ tlb->batch = NULL;
#endif
+}
+
+void tlb_flush_mmu(struct mmu_gather *tlb)
+{
+ struct mmu_gather_batch *batch;
+
+ if (!tlb->need_flush)
+ return;
+ tlb->need_flush = 0;
+ tlb_flush(tlb);
+#ifdef CONFIG_HAVE_RCU_TABLE_FREE
+ tlb_table_flush(tlb);
+#endif
+
+ if (tlb_fast_mode(tlb))
+ return;
+
+ for (batch = &tlb->local; batch; batch = batch->next) {
+ free_pages_and_swap_cache(batch->pages, batch->nr);
+ batch->nr = 0;
+ }
+ tlb->active = &tlb->local;
+}
+
+/* tlb_finish_mmu
+ * Called at the end of the shootdown operation to free up any resources
+ * that were required.
+ */
+void tlb_finish_mmu(struct mmu_gather *tlb, unsigned long start, unsigned long end)
+{
+ struct mmu_gather_batch *batch, *next;
+
+ tlb_flush_mmu(tlb);
+
+ /* keep the page table cache within bounds */
+ check_pgt_cache();
+
+ for (batch = tlb->local.next; batch; batch = next) {
+ next = batch->next;
+ free_pages((unsigned long)batch, 0);
+ }
+ tlb->local.next = NULL;
+}
+
+/* __tlb_remove_page
+ * Must perform the equivalent to __free_pte(pte_get_and_clear(ptep)), while
+ * handling the additional races in SMP caused by other CPUs caching valid
+ * mappings in their TLBs. Returns the number of free page slots left.
+ * When out of page slots we must call tlb_flush_mmu().
+ */
+int __tlb_remove_page(struct mmu_gather *tlb, struct page *page)
+{
+ struct mmu_gather_batch *batch;
+
+ tlb->need_flush = 1;
+
+ if (tlb_fast_mode(tlb)) {
+ free_page_and_swap_cache(page);
+ return 1; /* avoid calling tlb_flush_mmu() */
+ }
+
+ batch = tlb->active;
+ batch->pages[batch->nr++] = page;
+ if (batch->nr == batch->max) {
+ if (!tlb_next_batch(tlb))
+ return 0;
+ }
+ VM_BUG_ON(batch->nr > batch->max);
+
+ return batch->max - batch->nr;
+}
+
+#endif /* HAVE_GENERIC_MMU_GATHER */
+
+#ifdef CONFIG_HAVE_RCU_TABLE_FREE
+
+/*
+ * See the comment near struct mmu_table_batch.
+ */
+
+static void tlb_remove_table_smp_sync(void *arg)
+{
+ /* Simply deliver the interrupt */
+}
+
+static void tlb_remove_table_one(void *table)
+{
+ /*
+ * This isn't an RCU grace period and hence the page-tables cannot be
+ * assumed to be actually RCU-freed.
+ *
+ * It is however sufficient for software page-table walkers that rely on
+ * IRQ disabling. See the comment near struct mmu_table_batch.
+ */
+ smp_call_function(tlb_remove_table_smp_sync, NULL, 1);
+ __tlb_remove_table(table);
+}
+
+static void tlb_remove_table_rcu(struct rcu_head *head)
+{
+ struct mmu_table_batch *batch;
+ int i;
+
+ batch = container_of(head, struct mmu_table_batch, rcu);
+
+ for (i = 0; i < batch->nr; i++)
+ __tlb_remove_table(batch->tables[i]);
+
+ free_page((unsigned long)batch);
+}
+
+void tlb_table_flush(struct mmu_gather *tlb)
+{
+ struct mmu_table_batch **batch = &tlb->batch;
+
+ if (*batch) {
+ call_rcu_sched(&(*batch)->rcu, tlb_remove_table_rcu);
+ *batch = NULL;
+ }
+}
+
+void tlb_remove_table(struct mmu_gather *tlb, void *table)
+{
+ struct mmu_table_batch **batch = &tlb->batch;
+
+ tlb->need_flush = 1;
+
+ /*
+ * When there's less then two users of this mm there cannot be a
+ * concurrent page-table walk.
+ */
+ if (atomic_read(&tlb->mm->mm_users) < 2) {
+ __tlb_remove_table(table);
+ return;
+ }
+
+ if (*batch == NULL) {
+ *batch = (struct mmu_table_batch *)__get_free_page(GFP_NOWAIT | __GFP_NOWARN);
+ if (*batch == NULL) {
+ tlb_remove_table_one(table);
+ return;
+ }
+ (*batch)->nr = 0;
+ }
+ (*batch)->tables[(*batch)->nr++] = table;
+ if ((*batch)->nr == MAX_TABLE_BATCH)
+ tlb_table_flush(tlb);
+}
+
+#endif /* CONFIG_HAVE_RCU_TABLE_FREE */
/*
* If a p?d_bad entry is found while walking page tables, report
@@ -909,26 +1106,24 @@
static unsigned long zap_pte_range(struct mmu_gather *tlb,
struct vm_area_struct *vma, pmd_t *pmd,
unsigned long addr, unsigned long end,
- long *zap_work, struct zap_details *details)
+ struct zap_details *details)
{
struct mm_struct *mm = tlb->mm;
- pte_t *pte;
- spinlock_t *ptl;
+ int force_flush = 0;
int rss[NR_MM_COUNTERS];
+ spinlock_t *ptl;
+ pte_t *pte;
+again:
init_rss_vec(rss);
-
pte = pte_offset_map_lock(mm, pmd, addr, &ptl);
arch_enter_lazy_mmu_mode();
do {
pte_t ptent = *pte;
if (pte_none(ptent)) {
- (*zap_work)--;
continue;
}
- (*zap_work) -= PAGE_SIZE;
-
if (pte_present(ptent)) {
struct page *page;
@@ -974,7 +1169,9 @@
page_remove_rmap(page);
if (unlikely(page_mapcount(page) < 0))
print_bad_pte(vma, addr, ptent, page);
- tlb_remove_page(tlb, page);
+ force_flush = !__tlb_remove_page(tlb, page);
+ if (force_flush)
+ break;
continue;
}
/*
@@ -995,19 +1192,31 @@
print_bad_pte(vma, addr, ptent, NULL);
}
pte_clear_not_present_full(mm, addr, pte, tlb->fullmm);
- } while (pte++, addr += PAGE_SIZE, (addr != end && *zap_work > 0));
+ } while (pte++, addr += PAGE_SIZE, addr != end);
add_mm_rss_vec(mm, rss);
arch_leave_lazy_mmu_mode();
pte_unmap_unlock(pte - 1, ptl);
+ /*
+ * mmu_gather ran out of room to batch pages, we break out of
+ * the PTE lock to avoid doing the potential expensive TLB invalidate
+ * and page-free while holding it.
+ */
+ if (force_flush) {
+ force_flush = 0;
+ tlb_flush_mmu(tlb);
+ if (addr != end)
+ goto again;
+ }
+
return addr;
}
static inline unsigned long zap_pmd_range(struct mmu_gather *tlb,
struct vm_area_struct *vma, pud_t *pud,
unsigned long addr, unsigned long end,
- long *zap_work, struct zap_details *details)
+ struct zap_details *details)
{
pmd_t *pmd;
unsigned long next;
@@ -1019,19 +1228,15 @@
if (next-addr != HPAGE_PMD_SIZE) {
VM_BUG_ON(!rwsem_is_locked(&tlb->mm->mmap_sem));
split_huge_page_pmd(vma->vm_mm, pmd);
- } else if (zap_huge_pmd(tlb, vma, pmd)) {
- (*zap_work)--;
+ } else if (zap_huge_pmd(tlb, vma, pmd))
continue;
- }
/* fall through */
}
- if (pmd_none_or_clear_bad(pmd)) {
- (*zap_work)--;
+ if (pmd_none_or_clear_bad(pmd))
continue;
- }
- next = zap_pte_range(tlb, vma, pmd, addr, next,
- zap_work, details);
- } while (pmd++, addr = next, (addr != end && *zap_work > 0));
+ next = zap_pte_range(tlb, vma, pmd, addr, next, details);
+ cond_resched();
+ } while (pmd++, addr = next, addr != end);
return addr;
}
@@ -1039,7 +1244,7 @@
static inline unsigned long zap_pud_range(struct mmu_gather *tlb,
struct vm_area_struct *vma, pgd_t *pgd,
unsigned long addr, unsigned long end,
- long *zap_work, struct zap_details *details)
+ struct zap_details *details)
{
pud_t *pud;
unsigned long next;
@@ -1047,13 +1252,10 @@
pud = pud_offset(pgd, addr);
do {
next = pud_addr_end(addr, end);
- if (pud_none_or_clear_bad(pud)) {
- (*zap_work)--;
+ if (pud_none_or_clear_bad(pud))
continue;
- }
- next = zap_pmd_range(tlb, vma, pud, addr, next,
- zap_work, details);
- } while (pud++, addr = next, (addr != end && *zap_work > 0));
+ next = zap_pmd_range(tlb, vma, pud, addr, next, details);
+ } while (pud++, addr = next, addr != end);
return addr;
}
@@ -1061,7 +1263,7 @@
static unsigned long unmap_page_range(struct mmu_gather *tlb,
struct vm_area_struct *vma,
unsigned long addr, unsigned long end,
- long *zap_work, struct zap_details *details)
+ struct zap_details *details)
{
pgd_t *pgd;
unsigned long next;
@@ -1075,13 +1277,10 @@
pgd = pgd_offset(vma->vm_mm, addr);
do {
next = pgd_addr_end(addr, end);
- if (pgd_none_or_clear_bad(pgd)) {
- (*zap_work)--;
+ if (pgd_none_or_clear_bad(pgd))
continue;
- }
- next = zap_pud_range(tlb, vma, pgd, addr, next,
- zap_work, details);
- } while (pgd++, addr = next, (addr != end && *zap_work > 0));
+ next = zap_pud_range(tlb, vma, pgd, addr, next, details);
+ } while (pgd++, addr = next, addr != end);
tlb_end_vma(tlb, vma);
mem_cgroup_uncharge_end();
@@ -1121,17 +1320,12 @@
* ensure that any thus-far unmapped pages are flushed before unmap_vmas()
* drops the lock and schedules.
*/
-unsigned long unmap_vmas(struct mmu_gather **tlbp,
+unsigned long unmap_vmas(struct mmu_gather *tlb,
struct vm_area_struct *vma, unsigned long start_addr,
unsigned long end_addr, unsigned long *nr_accounted,
struct zap_details *details)
{
- long zap_work = ZAP_BLOCK_SIZE;
- unsigned long tlb_start = 0; /* For tlb_finish_mmu */
- int tlb_start_valid = 0;
unsigned long start = start_addr;
- spinlock_t *i_mmap_lock = details? details->i_mmap_lock: NULL;
- int fullmm = (*tlbp)->fullmm;
struct mm_struct *mm = vma->vm_mm;
mmu_notifier_invalidate_range_start(mm, start_addr, end_addr);
@@ -1152,11 +1346,6 @@
untrack_pfn_vma(vma, 0, 0);
while (start != end) {
- if (!tlb_start_valid) {
- tlb_start = start;
- tlb_start_valid = 1;
- }
-
if (unlikely(is_vm_hugetlb_page(vma))) {
/*
* It is undesirable to test vma->vm_file as it
@@ -1169,39 +1358,15 @@
* Since no pte has actually been setup, it is
* safe to do nothing in this case.
*/
- if (vma->vm_file) {
+ if (vma->vm_file)
unmap_hugepage_range(vma, start, end, NULL);
- zap_work -= (end - start) /
- pages_per_huge_page(hstate_vma(vma));
- }
start = end;
} else
- start = unmap_page_range(*tlbp, vma,
- start, end, &zap_work, details);
-
- if (zap_work > 0) {
- BUG_ON(start != end);
- break;
- }
-
- tlb_finish_mmu(*tlbp, tlb_start, start);
-
- if (need_resched() ||
- (i_mmap_lock && spin_needbreak(i_mmap_lock))) {
- if (i_mmap_lock) {
- *tlbp = NULL;
- goto out;
- }
- cond_resched();
- }
-
- *tlbp = tlb_gather_mmu(vma->vm_mm, fullmm);
- tlb_start_valid = 0;
- zap_work = ZAP_BLOCK_SIZE;
+ start = unmap_page_range(tlb, vma, start, end, details);
}
}
-out:
+
mmu_notifier_invalidate_range_end(mm, start_addr, end_addr);
return start; /* which is now the end (or restart) address */
}
@@ -1217,16 +1382,15 @@
unsigned long size, struct zap_details *details)
{
struct mm_struct *mm = vma->vm_mm;
- struct mmu_gather *tlb;
+ struct mmu_gather tlb;
unsigned long end = address + size;
unsigned long nr_accounted = 0;
lru_add_drain();
- tlb = tlb_gather_mmu(mm, 0);
+ tlb_gather_mmu(&tlb, mm, 0);
update_hiwater_rss(mm);
end = unmap_vmas(&tlb, vma, address, end, &nr_accounted, details);
- if (tlb)
- tlb_finish_mmu(tlb, address, end);
+ tlb_finish_mmu(&tlb, address, end);
return end;
}
@@ -2535,96 +2699,11 @@
return ret;
}
-/*
- * Helper functions for unmap_mapping_range().
- *
- * __ Notes on dropping i_mmap_lock to reduce latency while unmapping __
- *
- * We have to restart searching the prio_tree whenever we drop the lock,
- * since the iterator is only valid while the lock is held, and anyway
- * a later vma might be split and reinserted earlier while lock dropped.
- *
- * The list of nonlinear vmas could be handled more efficiently, using
- * a placeholder, but handle it in the same way until a need is shown.
- * It is important to search the prio_tree before nonlinear list: a vma
- * may become nonlinear and be shifted from prio_tree to nonlinear list
- * while the lock is dropped; but never shifted from list to prio_tree.
- *
- * In order to make forward progress despite restarting the search,
- * vm_truncate_count is used to mark a vma as now dealt with, so we can
- * quickly skip it next time around. Since the prio_tree search only
- * shows us those vmas affected by unmapping the range in question, we
- * can't efficiently keep all vmas in step with mapping->truncate_count:
- * so instead reset them all whenever it wraps back to 0 (then go to 1).
- * mapping->truncate_count and vma->vm_truncate_count are protected by
- * i_mmap_lock.
- *
- * In order to make forward progress despite repeatedly restarting some
- * large vma, note the restart_addr from unmap_vmas when it breaks out:
- * and restart from that address when we reach that vma again. It might
- * have been split or merged, shrunk or extended, but never shifted: so
- * restart_addr remains valid so long as it remains in the vma's range.
- * unmap_mapping_range forces truncate_count to leap over page-aligned
- * values so we can save vma's restart_addr in its truncate_count field.
- */
-#define is_restart_addr(truncate_count) (!((truncate_count) & ~PAGE_MASK))
-
-static void reset_vma_truncate_counts(struct address_space *mapping)
-{
- struct vm_area_struct *vma;
- struct prio_tree_iter iter;
-
- vma_prio_tree_foreach(vma, &iter, &mapping->i_mmap, 0, ULONG_MAX)
- vma->vm_truncate_count = 0;
- list_for_each_entry(vma, &mapping->i_mmap_nonlinear, shared.vm_set.list)
- vma->vm_truncate_count = 0;
-}
-
-static int unmap_mapping_range_vma(struct vm_area_struct *vma,
+static void unmap_mapping_range_vma(struct vm_area_struct *vma,
unsigned long start_addr, unsigned long end_addr,
struct zap_details *details)
{
- unsigned long restart_addr;
- int need_break;
-
- /*
- * files that support invalidating or truncating portions of the
- * file from under mmaped areas must have their ->fault function
- * return a locked page (and set VM_FAULT_LOCKED in the return).
- * This provides synchronisation against concurrent unmapping here.
- */
-
-again:
- restart_addr = vma->vm_truncate_count;
- if (is_restart_addr(restart_addr) && start_addr < restart_addr) {
- start_addr = restart_addr;
- if (start_addr >= end_addr) {
- /* Top of vma has been split off since last time */
- vma->vm_truncate_count = details->truncate_count;
- return 0;
- }
- }
-
- restart_addr = zap_page_range(vma, start_addr,
- end_addr - start_addr, details);
- need_break = need_resched() || spin_needbreak(details->i_mmap_lock);
-
- if (restart_addr >= end_addr) {
- /* We have now completed this vma: mark it so */
- vma->vm_truncate_count = details->truncate_count;
- if (!need_break)
- return 0;
- } else {
- /* Note restart_addr in vma's truncate_count field */
- vma->vm_truncate_count = restart_addr;
- if (!need_break)
- goto again;
- }
-
- spin_unlock(details->i_mmap_lock);
- cond_resched();
- spin_lock(details->i_mmap_lock);
- return -EINTR;
+ zap_page_range(vma, start_addr, end_addr - start_addr, details);
}
static inline void unmap_mapping_range_tree(struct prio_tree_root *root,
@@ -2634,12 +2713,8 @@
struct prio_tree_iter iter;
pgoff_t vba, vea, zba, zea;
-restart:
vma_prio_tree_foreach(vma, &iter, root,
details->first_index, details->last_index) {
- /* Skip quickly over those we have already dealt with */
- if (vma->vm_truncate_count == details->truncate_count)
- continue;
vba = vma->vm_pgoff;
vea = vba + ((vma->vm_end - vma->vm_start) >> PAGE_SHIFT) - 1;
@@ -2651,11 +2726,10 @@
if (zea > vea)
zea = vea;
- if (unmap_mapping_range_vma(vma,
+ unmap_mapping_range_vma(vma,
((zba - vba) << PAGE_SHIFT) + vma->vm_start,
((zea - vba + 1) << PAGE_SHIFT) + vma->vm_start,
- details) < 0)
- goto restart;
+ details);
}
}
@@ -2670,15 +2744,9 @@
* across *all* the pages in each nonlinear VMA, not just the pages
* whose virtual address lies outside the file truncation point.
*/
-restart:
list_for_each_entry(vma, head, shared.vm_set.list) {
- /* Skip quickly over those we have already dealt with */
- if (vma->vm_truncate_count == details->truncate_count)
- continue;
details->nonlinear_vma = vma;
- if (unmap_mapping_range_vma(vma, vma->vm_start,
- vma->vm_end, details) < 0)
- goto restart;
+ unmap_mapping_range_vma(vma, vma->vm_start, vma->vm_end, details);
}
}
@@ -2717,26 +2785,14 @@
details.last_index = hba + hlen - 1;
if (details.last_index < details.first_index)
details.last_index = ULONG_MAX;
- details.i_mmap_lock = &mapping->i_mmap_lock;
- mutex_lock(&mapping->unmap_mutex);
- spin_lock(&mapping->i_mmap_lock);
- /* Protect against endless unmapping loops */
- mapping->truncate_count++;
- if (unlikely(is_restart_addr(mapping->truncate_count))) {
- if (mapping->truncate_count == 0)
- reset_vma_truncate_counts(mapping);
- mapping->truncate_count++;
- }
- details.truncate_count = mapping->truncate_count;
-
+ mutex_lock(&mapping->i_mmap_mutex);
if (unlikely(!prio_tree_empty(&mapping->i_mmap)))
unmap_mapping_range_tree(&mapping->i_mmap, &details);
if (unlikely(!list_empty(&mapping->i_mmap_nonlinear)))
unmap_mapping_range_list(&mapping->i_mmap_nonlinear, &details);
- spin_unlock(&mapping->i_mmap_lock);
- mutex_unlock(&mapping->unmap_mutex);
+ mutex_unlock(&mapping->i_mmap_mutex);
}
EXPORT_SYMBOL(unmap_mapping_range);
@@ -2966,7 +3022,7 @@
if (prev && prev->vm_end == address)
return prev->vm_flags & VM_GROWSDOWN ? 0 : -ENOMEM;
- expand_stack(vma, address - PAGE_SIZE);
+ expand_downwards(vma, address - PAGE_SIZE);
}
if ((vma->vm_flags & VM_GROWSUP) && address + PAGE_SIZE == vma->vm_end) {
struct vm_area_struct *next = vma->vm_next;
diff --git a/mm/memory_hotplug.c b/mm/memory_hotplug.c
index 9ca1d60..9f64637 100644
--- a/mm/memory_hotplug.c
+++ b/mm/memory_hotplug.c
@@ -374,10 +374,6 @@
totalhigh_pages++;
#endif
-#ifdef CONFIG_FLATMEM
- max_mapnr = max(pfn, max_mapnr);
-#endif
-
ClearPageReserved(page);
init_page_count(page);
__free_page(page);
@@ -400,7 +396,7 @@
}
-int online_pages(unsigned long pfn, unsigned long nr_pages)
+int __ref online_pages(unsigned long pfn, unsigned long nr_pages)
{
unsigned long onlined_pages = 0;
struct zone *zone;
@@ -459,8 +455,9 @@
zone_pcp_update(zone);
mutex_unlock(&zonelists_mutex);
- setup_per_zone_wmarks();
- calculate_zone_inactive_ratio(zone);
+
+ init_per_zone_wmark_min();
+
if (onlined_pages) {
kswapd_run(zone_to_nid(zone));
node_set_state(zone_to_nid(zone), N_HIGH_MEMORY);
@@ -705,7 +702,7 @@
if (!pfn_valid(pfn))
continue;
page = pfn_to_page(pfn);
- if (!page_count(page))
+ if (!get_page_unless_zero(page))
continue;
/*
* We can skip free pages. And we can only deal with pages on
@@ -713,6 +710,7 @@
*/
ret = isolate_lru_page(page);
if (!ret) { /* Success */
+ put_page(page);
list_add_tail(&page->lru, &source);
move_pages--;
inc_zone_page_state(page, NR_ISOLATED_ANON +
@@ -724,6 +722,7 @@
pfn);
dump_page(page);
#endif
+ put_page(page);
/* Because we don't have big zone->lock. we should
check this again here. */
if (page_count(page)) {
@@ -795,7 +794,7 @@
return offlined;
}
-static int offline_pages(unsigned long start_pfn,
+static int __ref offline_pages(unsigned long start_pfn,
unsigned long end_pfn, unsigned long timeout)
{
unsigned long pfn, nr_pages, expire;
@@ -893,8 +892,8 @@
zone->zone_pgdat->node_present_pages -= offlined_pages;
totalram_pages -= offlined_pages;
- setup_per_zone_wmarks();
- calculate_zone_inactive_ratio(zone);
+ init_per_zone_wmark_min();
+
if (!node_present_pages(node)) {
node_clear_state(node, N_HIGH_MEMORY);
kswapd_stop(node);
diff --git a/mm/mempolicy.c b/mm/mempolicy.c
index 959a8b8..e7fb9d2 100644
--- a/mm/mempolicy.c
+++ b/mm/mempolicy.c
@@ -99,7 +99,6 @@
/* Internal flags */
#define MPOL_MF_DISCONTIG_OK (MPOL_MF_INTERNAL << 0) /* Skip checks for continuous vmas */
#define MPOL_MF_INVERT (MPOL_MF_INTERNAL << 1) /* Invert check for nodemask */
-#define MPOL_MF_STATS (MPOL_MF_INTERNAL << 2) /* Gather statistics */
static struct kmem_cache *policy_cache;
static struct kmem_cache *sn_cache;
@@ -457,7 +456,6 @@
},
};
-static void gather_stats(struct page *, void *, int pte_dirty);
static void migrate_page_add(struct page *page, struct list_head *pagelist,
unsigned long flags);
@@ -492,9 +490,7 @@
if (node_isset(nid, *nodes) == !!(flags & MPOL_MF_INVERT))
continue;
- if (flags & MPOL_MF_STATS)
- gather_stats(page, private, pte_dirty(*pte));
- else if (flags & (MPOL_MF_MOVE | MPOL_MF_MOVE_ALL))
+ if (flags & (MPOL_MF_MOVE | MPOL_MF_MOVE_ALL))
migrate_page_add(page, private, flags);
else
break;
@@ -1489,7 +1485,7 @@
* freeing by another task. It is the caller's responsibility to free the
* extra reference for shared policies.
*/
-static struct mempolicy *get_vma_policy(struct task_struct *task,
+struct mempolicy *get_vma_policy(struct task_struct *task,
struct vm_area_struct *vma, unsigned long addr)
{
struct mempolicy *pol = task->mempolicy;
@@ -2529,159 +2525,3 @@
}
return p - buffer;
}
-
-struct numa_maps {
- unsigned long pages;
- unsigned long anon;
- unsigned long active;
- unsigned long writeback;
- unsigned long mapcount_max;
- unsigned long dirty;
- unsigned long swapcache;
- unsigned long node[MAX_NUMNODES];
-};
-
-static void gather_stats(struct page *page, void *private, int pte_dirty)
-{
- struct numa_maps *md = private;
- int count = page_mapcount(page);
-
- md->pages++;
- if (pte_dirty || PageDirty(page))
- md->dirty++;
-
- if (PageSwapCache(page))
- md->swapcache++;
-
- if (PageActive(page) || PageUnevictable(page))
- md->active++;
-
- if (PageWriteback(page))
- md->writeback++;
-
- if (PageAnon(page))
- md->anon++;
-
- if (count > md->mapcount_max)
- md->mapcount_max = count;
-
- md->node[page_to_nid(page)]++;
-}
-
-#ifdef CONFIG_HUGETLB_PAGE
-static void check_huge_range(struct vm_area_struct *vma,
- unsigned long start, unsigned long end,
- struct numa_maps *md)
-{
- unsigned long addr;
- struct page *page;
- struct hstate *h = hstate_vma(vma);
- unsigned long sz = huge_page_size(h);
-
- for (addr = start; addr < end; addr += sz) {
- pte_t *ptep = huge_pte_offset(vma->vm_mm,
- addr & huge_page_mask(h));
- pte_t pte;
-
- if (!ptep)
- continue;
-
- pte = *ptep;
- if (pte_none(pte))
- continue;
-
- page = pte_page(pte);
- if (!page)
- continue;
-
- gather_stats(page, md, pte_dirty(*ptep));
- }
-}
-#else
-static inline void check_huge_range(struct vm_area_struct *vma,
- unsigned long start, unsigned long end,
- struct numa_maps *md)
-{
-}
-#endif
-
-/*
- * Display pages allocated per node and memory policy via /proc.
- */
-int show_numa_map(struct seq_file *m, void *v)
-{
- struct proc_maps_private *priv = m->private;
- struct vm_area_struct *vma = v;
- struct numa_maps *md;
- struct file *file = vma->vm_file;
- struct mm_struct *mm = vma->vm_mm;
- struct mempolicy *pol;
- int n;
- char buffer[50];
-
- if (!mm)
- return 0;
-
- md = kzalloc(sizeof(struct numa_maps), GFP_KERNEL);
- if (!md)
- return 0;
-
- pol = get_vma_policy(priv->task, vma, vma->vm_start);
- mpol_to_str(buffer, sizeof(buffer), pol, 0);
- mpol_cond_put(pol);
-
- seq_printf(m, "%08lx %s", vma->vm_start, buffer);
-
- if (file) {
- seq_printf(m, " file=");
- seq_path(m, &file->f_path, "\n\t= ");
- } else if (vma->vm_start <= mm->brk && vma->vm_end >= mm->start_brk) {
- seq_printf(m, " heap");
- } else if (vma->vm_start <= mm->start_stack &&
- vma->vm_end >= mm->start_stack) {
- seq_printf(m, " stack");
- }
-
- if (is_vm_hugetlb_page(vma)) {
- check_huge_range(vma, vma->vm_start, vma->vm_end, md);
- seq_printf(m, " huge");
- } else {
- check_pgd_range(vma, vma->vm_start, vma->vm_end,
- &node_states[N_HIGH_MEMORY], MPOL_MF_STATS, md);
- }
-
- if (!md->pages)
- goto out;
-
- if (md->anon)
- seq_printf(m," anon=%lu",md->anon);
-
- if (md->dirty)
- seq_printf(m," dirty=%lu",md->dirty);
-
- if (md->pages != md->anon && md->pages != md->dirty)
- seq_printf(m, " mapped=%lu", md->pages);
-
- if (md->mapcount_max > 1)
- seq_printf(m, " mapmax=%lu", md->mapcount_max);
-
- if (md->swapcache)
- seq_printf(m," swapcache=%lu", md->swapcache);
-
- if (md->active < md->pages && !is_vm_hugetlb_page(vma))
- seq_printf(m," active=%lu", md->active);
-
- if (md->writeback)
- seq_printf(m," writeback=%lu", md->writeback);
-
- for_each_node_state(n, N_HIGH_MEMORY)
- if (md->node[n])
- seq_printf(m, " N%d=%lu", n, md->node[n]);
-out:
- seq_putc(m, '\n');
- kfree(md);
-
- if (m->count < m->size)
- m->version = (vma != priv->tail_vma) ? vma->vm_start : 0;
- return 0;
-}
diff --git a/mm/migrate.c b/mm/migrate.c
index 34132f8..e4a5c91 100644
--- a/mm/migrate.c
+++ b/mm/migrate.c
@@ -721,15 +721,11 @@
* Only page_lock_anon_vma() understands the subtleties of
* getting a hold on an anon_vma from outside one of its mms.
*/
- anon_vma = page_lock_anon_vma(page);
+ anon_vma = page_get_anon_vma(page);
if (anon_vma) {
/*
- * Take a reference count on the anon_vma if the
- * page is mapped so that it is guaranteed to
- * exist when the page is remapped later
+ * Anon page
*/
- get_anon_vma(anon_vma);
- page_unlock_anon_vma(anon_vma);
} else if (PageSwapCache(page)) {
/*
* We cannot be sure that the anon_vma of an unmapped
@@ -857,13 +853,8 @@
lock_page(hpage);
}
- if (PageAnon(hpage)) {
- anon_vma = page_lock_anon_vma(hpage);
- if (anon_vma) {
- get_anon_vma(anon_vma);
- page_unlock_anon_vma(anon_vma);
- }
- }
+ if (PageAnon(hpage))
+ anon_vma = page_get_anon_vma(hpage);
try_to_unmap(hpage, TTU_MIGRATION|TTU_IGNORE_MLOCK|TTU_IGNORE_ACCESS);
diff --git a/mm/mmap.c b/mm/mmap.c
index 772140c..ac2631b 100644
--- a/mm/mmap.c
+++ b/mm/mmap.c
@@ -84,10 +84,14 @@
}
EXPORT_SYMBOL(vm_get_page_prot);
-int sysctl_overcommit_memory = OVERCOMMIT_GUESS; /* heuristic overcommit */
-int sysctl_overcommit_ratio = 50; /* default is 50% */
+int sysctl_overcommit_memory __read_mostly = OVERCOMMIT_GUESS; /* heuristic overcommit */
+int sysctl_overcommit_ratio __read_mostly = 50; /* default is 50% */
int sysctl_max_map_count __read_mostly = DEFAULT_MAX_MAP_COUNT;
-struct percpu_counter vm_committed_as;
+/*
+ * Make sure vm_committed_as in one cacheline and not cacheline shared with
+ * other variables. It can be updated by several CPUs frequently.
+ */
+struct percpu_counter vm_committed_as ____cacheline_aligned_in_smp;
/*
* Check that a process has enough memory to allocate a new virtual
@@ -190,7 +194,7 @@
}
/*
- * Requires inode->i_mapping->i_mmap_lock
+ * Requires inode->i_mapping->i_mmap_mutex
*/
static void __remove_shared_vm_struct(struct vm_area_struct *vma,
struct file *file, struct address_space *mapping)
@@ -218,9 +222,9 @@
if (file) {
struct address_space *mapping = file->f_mapping;
- spin_lock(&mapping->i_mmap_lock);
+ mutex_lock(&mapping->i_mmap_mutex);
__remove_shared_vm_struct(vma, file, mapping);
- spin_unlock(&mapping->i_mmap_lock);
+ mutex_unlock(&mapping->i_mmap_mutex);
}
}
@@ -394,29 +398,6 @@
return vma;
}
-static inline void
-__vma_link_list(struct mm_struct *mm, struct vm_area_struct *vma,
- struct vm_area_struct *prev, struct rb_node *rb_parent)
-{
- struct vm_area_struct *next;
-
- vma->vm_prev = prev;
- if (prev) {
- next = prev->vm_next;
- prev->vm_next = vma;
- } else {
- mm->mmap = vma;
- if (rb_parent)
- next = rb_entry(rb_parent,
- struct vm_area_struct, vm_rb);
- else
- next = NULL;
- }
- vma->vm_next = next;
- if (next)
- next->vm_prev = vma;
-}
-
void __vma_link_rb(struct mm_struct *mm, struct vm_area_struct *vma,
struct rb_node **rb_link, struct rb_node *rb_parent)
{
@@ -464,16 +445,14 @@
if (vma->vm_file)
mapping = vma->vm_file->f_mapping;
- if (mapping) {
- spin_lock(&mapping->i_mmap_lock);
- vma->vm_truncate_count = mapping->truncate_count;
- }
+ if (mapping)
+ mutex_lock(&mapping->i_mmap_mutex);
__vma_link(mm, vma, prev, rb_link, rb_parent);
__vma_link_file(vma);
if (mapping)
- spin_unlock(&mapping->i_mmap_lock);
+ mutex_unlock(&mapping->i_mmap_mutex);
mm->map_count++;
validate_mm(mm);
@@ -576,17 +555,8 @@
mapping = file->f_mapping;
if (!(vma->vm_flags & VM_NONLINEAR))
root = &mapping->i_mmap;
- spin_lock(&mapping->i_mmap_lock);
- if (importer &&
- vma->vm_truncate_count != next->vm_truncate_count) {
- /*
- * unmap_mapping_range might be in progress:
- * ensure that the expanding vma is rescanned.
- */
- importer->vm_truncate_count = 0;
- }
+ mutex_lock(&mapping->i_mmap_mutex);
if (insert) {
- insert->vm_truncate_count = vma->vm_truncate_count;
/*
* Put into prio_tree now, so instantiated pages
* are visible to arm/parisc __flush_dcache_page
@@ -605,7 +575,7 @@
* lock may be shared between many sibling processes. Skipping
* the lock for brk adjustments makes a difference sometimes.
*/
- if (vma->anon_vma && (insert || importer || start != vma->vm_start)) {
+ if (vma->anon_vma && (importer || start != vma->vm_start)) {
anon_vma = vma->anon_vma;
anon_vma_lock(anon_vma);
}
@@ -652,7 +622,7 @@
if (anon_vma)
anon_vma_unlock(anon_vma);
if (mapping)
- spin_unlock(&mapping->i_mmap_lock);
+ mutex_unlock(&mapping->i_mmap_mutex);
if (remove_next) {
if (file) {
@@ -699,9 +669,17 @@
}
static inline int is_mergeable_anon_vma(struct anon_vma *anon_vma1,
- struct anon_vma *anon_vma2)
+ struct anon_vma *anon_vma2,
+ struct vm_area_struct *vma)
{
- return !anon_vma1 || !anon_vma2 || (anon_vma1 == anon_vma2);
+ /*
+ * The list_is_singular() test is to avoid merging VMA cloned from
+ * parents. This can improve scalability caused by anon_vma lock.
+ */
+ if ((!anon_vma1 || !anon_vma2) && (!vma ||
+ list_is_singular(&vma->anon_vma_chain)))
+ return 1;
+ return anon_vma1 == anon_vma2;
}
/*
@@ -720,7 +698,7 @@
struct anon_vma *anon_vma, struct file *file, pgoff_t vm_pgoff)
{
if (is_mergeable_vma(vma, file, vm_flags) &&
- is_mergeable_anon_vma(anon_vma, vma->anon_vma)) {
+ is_mergeable_anon_vma(anon_vma, vma->anon_vma, vma)) {
if (vma->vm_pgoff == vm_pgoff)
return 1;
}
@@ -739,7 +717,7 @@
struct anon_vma *anon_vma, struct file *file, pgoff_t vm_pgoff)
{
if (is_mergeable_vma(vma, file, vm_flags) &&
- is_mergeable_anon_vma(anon_vma, vma->anon_vma)) {
+ is_mergeable_anon_vma(anon_vma, vma->anon_vma, vma)) {
pgoff_t vm_pglen;
vm_pglen = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT;
if (vma->vm_pgoff + vm_pglen == vm_pgoff)
@@ -817,7 +795,7 @@
can_vma_merge_before(next, vm_flags,
anon_vma, file, pgoff+pglen) &&
is_mergeable_anon_vma(prev->anon_vma,
- next->anon_vma)) {
+ next->anon_vma, NULL)) {
/* cases 1, 6 */
err = vma_adjust(prev, prev->vm_start,
next->vm_end, prev->vm_pgoff, NULL);
@@ -1785,7 +1763,7 @@
/*
* vma is the first one with address < vma->vm_start. Have to extend vma.
*/
-static int expand_downwards(struct vm_area_struct *vma,
+int expand_downwards(struct vm_area_struct *vma,
unsigned long address)
{
int error;
@@ -1832,11 +1810,6 @@
return error;
}
-int expand_stack_downwards(struct vm_area_struct *vma, unsigned long address)
-{
- return expand_downwards(vma, address);
-}
-
#ifdef CONFIG_STACK_GROWSUP
int expand_stack(struct vm_area_struct *vma, unsigned long address)
{
@@ -1919,17 +1892,17 @@
unsigned long start, unsigned long end)
{
struct vm_area_struct *next = prev? prev->vm_next: mm->mmap;
- struct mmu_gather *tlb;
+ struct mmu_gather tlb;
unsigned long nr_accounted = 0;
lru_add_drain();
- tlb = tlb_gather_mmu(mm, 0);
+ tlb_gather_mmu(&tlb, mm, 0);
update_hiwater_rss(mm);
unmap_vmas(&tlb, vma, start, end, &nr_accounted, NULL);
vm_unacct_memory(nr_accounted);
- free_pgtables(tlb, vma, prev? prev->vm_end: FIRST_USER_ADDRESS,
- next? next->vm_start: 0);
- tlb_finish_mmu(tlb, start, end);
+ free_pgtables(&tlb, vma, prev ? prev->vm_end : FIRST_USER_ADDRESS,
+ next ? next->vm_start : 0);
+ tlb_finish_mmu(&tlb, start, end);
}
/*
@@ -2271,7 +2244,7 @@
/* Release all mmaps. */
void exit_mmap(struct mm_struct *mm)
{
- struct mmu_gather *tlb;
+ struct mmu_gather tlb;
struct vm_area_struct *vma;
unsigned long nr_accounted = 0;
unsigned long end;
@@ -2296,14 +2269,14 @@
lru_add_drain();
flush_cache_mm(mm);
- tlb = tlb_gather_mmu(mm, 1);
+ tlb_gather_mmu(&tlb, mm, 1);
/* update_hiwater_rss(mm) here? but nobody should be looking */
/* Use -1 here to ensure all VMAs in the mm are unmapped */
end = unmap_vmas(&tlb, vma, 0, -1, &nr_accounted, NULL);
vm_unacct_memory(nr_accounted);
- free_pgtables(tlb, vma, FIRST_USER_ADDRESS, 0);
- tlb_finish_mmu(tlb, 0, end);
+ free_pgtables(&tlb, vma, FIRST_USER_ADDRESS, 0);
+ tlb_finish_mmu(&tlb, 0, end);
/*
* Walk the list again, actually closing and freeing it,
@@ -2317,7 +2290,7 @@
/* Insert vm structure into process list sorted by address
* and into the inode's i_mmap tree. If vm_file is non-NULL
- * then i_mmap_lock is taken here.
+ * then i_mmap_mutex is taken here.
*/
int insert_vm_struct(struct mm_struct * mm, struct vm_area_struct * vma)
{
@@ -2529,15 +2502,15 @@
* The LSB of head.next can't change from under us
* because we hold the mm_all_locks_mutex.
*/
- spin_lock_nest_lock(&anon_vma->root->lock, &mm->mmap_sem);
+ mutex_lock_nest_lock(&anon_vma->root->mutex, &mm->mmap_sem);
/*
* We can safely modify head.next after taking the
- * anon_vma->root->lock. If some other vma in this mm shares
+ * anon_vma->root->mutex. If some other vma in this mm shares
* the same anon_vma we won't take it again.
*
* No need of atomic instructions here, head.next
* can't change from under us thanks to the
- * anon_vma->root->lock.
+ * anon_vma->root->mutex.
*/
if (__test_and_set_bit(0, (unsigned long *)
&anon_vma->root->head.next))
@@ -2559,7 +2532,7 @@
*/
if (test_and_set_bit(AS_MM_ALL_LOCKS, &mapping->flags))
BUG();
- spin_lock_nest_lock(&mapping->i_mmap_lock, &mm->mmap_sem);
+ mutex_lock_nest_lock(&mapping->i_mmap_mutex, &mm->mmap_sem);
}
}
@@ -2586,7 +2559,7 @@
* vma in this mm is backed by the same anon_vma or address_space.
*
* We can take all the locks in random order because the VM code
- * taking i_mmap_lock or anon_vma->lock outside the mmap_sem never
+ * taking i_mmap_mutex or anon_vma->mutex outside the mmap_sem never
* takes more than one of them in a row. Secondly we're protected
* against a concurrent mm_take_all_locks() by the mm_all_locks_mutex.
*
@@ -2642,7 +2615,7 @@
*
* No need of atomic instructions here, head.next
* can't change from under us until we release the
- * anon_vma->root->lock.
+ * anon_vma->root->mutex.
*/
if (!__test_and_clear_bit(0, (unsigned long *)
&anon_vma->root->head.next))
@@ -2658,7 +2631,7 @@
* AS_MM_ALL_LOCKS can't change to 0 from under us
* because we hold the mm_all_locks_mutex.
*/
- spin_unlock(&mapping->i_mmap_lock);
+ mutex_unlock(&mapping->i_mmap_mutex);
if (!test_and_clear_bit(AS_MM_ALL_LOCKS,
&mapping->flags))
BUG();
diff --git a/mm/mremap.c b/mm/mremap.c
index a7c1f9f..506fa44 100644
--- a/mm/mremap.c
+++ b/mm/mremap.c
@@ -93,8 +93,7 @@
* and we propagate stale pages into the dst afterward.
*/
mapping = vma->vm_file->f_mapping;
- spin_lock(&mapping->i_mmap_lock);
- new_vma->vm_truncate_count = 0;
+ mutex_lock(&mapping->i_mmap_mutex);
}
/*
@@ -123,7 +122,7 @@
pte_unmap(new_pte - 1);
pte_unmap_unlock(old_pte - 1, old_ptl);
if (mapping)
- spin_unlock(&mapping->i_mmap_lock);
+ mutex_unlock(&mapping->i_mmap_mutex);
mmu_notifier_invalidate_range_end(vma->vm_mm, old_start, old_end);
}
diff --git a/mm/nobootmem.c b/mm/nobootmem.c
index 9109049..6e93dc7 100644
--- a/mm/nobootmem.c
+++ b/mm/nobootmem.c
@@ -307,30 +307,7 @@
void * __init __alloc_bootmem_node_high(pg_data_t *pgdat, unsigned long size,
unsigned long align, unsigned long goal)
{
-#ifdef MAX_DMA32_PFN
- unsigned long end_pfn;
-
- if (WARN_ON_ONCE(slab_is_available()))
- return kzalloc_node(size, GFP_NOWAIT, pgdat->node_id);
-
- /* update goal according ...MAX_DMA32_PFN */
- end_pfn = pgdat->node_start_pfn + pgdat->node_spanned_pages;
-
- if (end_pfn > MAX_DMA32_PFN + (128 >> (20 - PAGE_SHIFT)) &&
- (goal >> PAGE_SHIFT) < MAX_DMA32_PFN) {
- void *ptr;
- unsigned long new_goal;
-
- new_goal = MAX_DMA32_PFN << PAGE_SHIFT;
- ptr = __alloc_memory_core_early(pgdat->node_id, size, align,
- new_goal, -1ULL);
- if (ptr)
- return ptr;
- }
-#endif
-
return __alloc_bootmem_node(pgdat, size, align, goal);
-
}
#ifdef CONFIG_SPARSEMEM
diff --git a/mm/nommu.c b/mm/nommu.c
index c4c542c..1fd0c51 100644
--- a/mm/nommu.c
+++ b/mm/nommu.c
@@ -680,9 +680,9 @@
*/
static void add_vma_to_mm(struct mm_struct *mm, struct vm_area_struct *vma)
{
- struct vm_area_struct *pvma, **pp, *next;
+ struct vm_area_struct *pvma, *prev;
struct address_space *mapping;
- struct rb_node **p, *parent;
+ struct rb_node **p, *parent, *rb_prev;
kenter(",%p", vma);
@@ -703,7 +703,7 @@
}
/* add the VMA to the tree */
- parent = NULL;
+ parent = rb_prev = NULL;
p = &mm->mm_rb.rb_node;
while (*p) {
parent = *p;
@@ -713,17 +713,20 @@
* (the latter is necessary as we may get identical VMAs) */
if (vma->vm_start < pvma->vm_start)
p = &(*p)->rb_left;
- else if (vma->vm_start > pvma->vm_start)
+ else if (vma->vm_start > pvma->vm_start) {
+ rb_prev = parent;
p = &(*p)->rb_right;
- else if (vma->vm_end < pvma->vm_end)
+ } else if (vma->vm_end < pvma->vm_end)
p = &(*p)->rb_left;
- else if (vma->vm_end > pvma->vm_end)
+ else if (vma->vm_end > pvma->vm_end) {
+ rb_prev = parent;
p = &(*p)->rb_right;
- else if (vma < pvma)
+ } else if (vma < pvma)
p = &(*p)->rb_left;
- else if (vma > pvma)
+ else if (vma > pvma) {
+ rb_prev = parent;
p = &(*p)->rb_right;
- else
+ } else
BUG();
}
@@ -731,20 +734,11 @@
rb_insert_color(&vma->vm_rb, &mm->mm_rb);
/* add VMA to the VMA list also */
- for (pp = &mm->mmap; (pvma = *pp); pp = &(*pp)->vm_next) {
- if (pvma->vm_start > vma->vm_start)
- break;
- if (pvma->vm_start < vma->vm_start)
- continue;
- if (pvma->vm_end < vma->vm_end)
- break;
- }
+ prev = NULL;
+ if (rb_prev)
+ prev = rb_entry(rb_prev, struct vm_area_struct, vm_rb);
- next = *pp;
- *pp = vma;
- vma->vm_next = next;
- if (next)
- next->vm_prev = vma;
+ __vma_link_list(mm, vma, prev, parent);
}
/*
@@ -752,7 +746,6 @@
*/
static void delete_vma_from_mm(struct vm_area_struct *vma)
{
- struct vm_area_struct **pp;
struct address_space *mapping;
struct mm_struct *mm = vma->vm_mm;
@@ -775,12 +768,14 @@
/* remove from the MM's tree and list */
rb_erase(&vma->vm_rb, &mm->mm_rb);
- for (pp = &mm->mmap; *pp; pp = &(*pp)->vm_next) {
- if (*pp == vma) {
- *pp = vma->vm_next;
- break;
- }
- }
+
+ if (vma->vm_prev)
+ vma->vm_prev->vm_next = vma->vm_next;
+ else
+ mm->mmap = vma->vm_next;
+
+ if (vma->vm_next)
+ vma->vm_next->vm_prev = vma->vm_prev;
vma->vm_mm = NULL;
}
@@ -809,17 +804,15 @@
struct vm_area_struct *find_vma(struct mm_struct *mm, unsigned long addr)
{
struct vm_area_struct *vma;
- struct rb_node *n = mm->mm_rb.rb_node;
/* check the cache first */
vma = mm->mmap_cache;
if (vma && vma->vm_start <= addr && vma->vm_end > addr)
return vma;
- /* trawl the tree (there may be multiple mappings in which addr
+ /* trawl the list (there may be multiple mappings in which addr
* resides) */
- for (n = rb_first(&mm->mm_rb); n; n = rb_next(n)) {
- vma = rb_entry(n, struct vm_area_struct, vm_rb);
+ for (vma = mm->mmap; vma; vma = vma->vm_next) {
if (vma->vm_start > addr)
return NULL;
if (vma->vm_end > addr) {
@@ -859,7 +852,6 @@
unsigned long len)
{
struct vm_area_struct *vma;
- struct rb_node *n = mm->mm_rb.rb_node;
unsigned long end = addr + len;
/* check the cache first */
@@ -867,10 +859,9 @@
if (vma && vma->vm_start == addr && vma->vm_end == end)
return vma;
- /* trawl the tree (there may be multiple mappings in which addr
+ /* trawl the list (there may be multiple mappings in which addr
* resides) */
- for (n = rb_first(&mm->mm_rb); n; n = rb_next(n)) {
- vma = rb_entry(n, struct vm_area_struct, vm_rb);
+ for (vma = mm->mmap; vma; vma = vma->vm_next) {
if (vma->vm_start < addr)
continue;
if (vma->vm_start > addr)
@@ -1133,7 +1124,7 @@
unsigned long capabilities)
{
struct page *pages;
- unsigned long total, point, n, rlen;
+ unsigned long total, point, n;
void *base;
int ret, order;
@@ -1157,13 +1148,12 @@
* make a private copy of the data and map that instead */
}
- rlen = PAGE_ALIGN(len);
/* allocate some memory to hold the mapping
* - note that this may not return a page-aligned address if the object
* we're allocating is smaller than a page
*/
- order = get_order(rlen);
+ order = get_order(len);
kdebug("alloc order %d for %lx", order, len);
pages = alloc_pages(GFP_KERNEL, order);
@@ -1173,7 +1163,7 @@
total = 1 << order;
atomic_long_add(total, &mmap_pages_allocated);
- point = rlen >> PAGE_SHIFT;
+ point = len >> PAGE_SHIFT;
/* we allocated a power-of-2 sized page set, so we may want to trim off
* the excess */
@@ -1195,7 +1185,7 @@
base = page_address(pages);
region->vm_flags = vma->vm_flags |= VM_MAPPED_COPY;
region->vm_start = (unsigned long) base;
- region->vm_end = region->vm_start + rlen;
+ region->vm_end = region->vm_start + len;
region->vm_top = region->vm_start + (total << PAGE_SHIFT);
vma->vm_start = region->vm_start;
@@ -1211,22 +1201,22 @@
old_fs = get_fs();
set_fs(KERNEL_DS);
- ret = vma->vm_file->f_op->read(vma->vm_file, base, rlen, &fpos);
+ ret = vma->vm_file->f_op->read(vma->vm_file, base, len, &fpos);
set_fs(old_fs);
if (ret < 0)
goto error_free;
/* clear the last little bit */
- if (ret < rlen)
- memset(base + ret, 0, rlen - ret);
+ if (ret < len)
+ memset(base + ret, 0, len - ret);
}
return 0;
error_free:
- free_page_series(region->vm_start, region->vm_end);
+ free_page_series(region->vm_start, region->vm_top);
region->vm_start = vma->vm_start = 0;
region->vm_end = vma->vm_end = 0;
region->vm_top = 0;
@@ -1235,7 +1225,7 @@
enomem:
printk("Allocation of length %lu from process %d (%s) failed\n",
len, current->pid, current->comm);
- show_free_areas();
+ show_free_areas(0);
return -ENOMEM;
}
@@ -1268,6 +1258,7 @@
/* we ignore the address hint */
addr = 0;
+ len = PAGE_ALIGN(len);
/* we've determined that we can make the mapping, now translate what we
* now know into VMA flags */
@@ -1385,15 +1376,15 @@
if (capabilities & BDI_CAP_MAP_DIRECT) {
addr = file->f_op->get_unmapped_area(file, addr, len,
pgoff, flags);
- if (IS_ERR((void *) addr)) {
+ if (IS_ERR_VALUE(addr)) {
ret = addr;
- if (ret != (unsigned long) -ENOSYS)
+ if (ret != -ENOSYS)
goto error_just_free;
/* the driver refused to tell us where to site
* the mapping so we'll have to attempt to copy
* it */
- ret = (unsigned long) -ENODEV;
+ ret = -ENODEV;
if (!(capabilities & BDI_CAP_MAP_COPY))
goto error_just_free;
@@ -1468,14 +1459,14 @@
printk(KERN_WARNING "Allocation of vma for %lu byte allocation"
" from process %d failed\n",
len, current->pid);
- show_free_areas();
+ show_free_areas(0);
return -ENOMEM;
error_getting_region:
printk(KERN_WARNING "Allocation of vm region for %lu byte allocation"
" from process %d failed\n",
len, current->pid);
- show_free_areas();
+ show_free_areas(0);
return -ENOMEM;
}
EXPORT_SYMBOL(do_mmap_pgoff);
@@ -1644,15 +1635,17 @@
int do_munmap(struct mm_struct *mm, unsigned long start, size_t len)
{
struct vm_area_struct *vma;
- struct rb_node *rb;
- unsigned long end = start + len;
+ unsigned long end;
int ret;
kenter(",%lx,%zx", start, len);
+ len = PAGE_ALIGN(len);
if (len == 0)
return -EINVAL;
+ end = start + len;
+
/* find the first potentially overlapping VMA */
vma = find_vma(mm, start);
if (!vma) {
@@ -1677,9 +1670,8 @@
}
if (end == vma->vm_end)
goto erase_whole_vma;
- rb = rb_next(&vma->vm_rb);
- vma = rb_entry(rb, struct vm_area_struct, vm_rb);
- } while (rb);
+ vma = vma->vm_next;
+ } while (vma);
kleave(" = -EINVAL [split file]");
return -EINVAL;
} else {
@@ -1773,6 +1765,8 @@
struct vm_area_struct *vma;
/* insanity checks first */
+ old_len = PAGE_ALIGN(old_len);
+ new_len = PAGE_ALIGN(new_len);
if (old_len == 0 || new_len == 0)
return (unsigned long) -EINVAL;
diff --git a/mm/oom_kill.c b/mm/oom_kill.c
index f52e85c..e4b0991 100644
--- a/mm/oom_kill.c
+++ b/mm/oom_kill.c
@@ -38,6 +38,33 @@
int sysctl_oom_dump_tasks = 1;
static DEFINE_SPINLOCK(zone_scan_lock);
+/**
+ * test_set_oom_score_adj() - set current's oom_score_adj and return old value
+ * @new_val: new oom_score_adj value
+ *
+ * Sets the oom_score_adj value for current to @new_val with proper
+ * synchronization and returns the old value. Usually used to temporarily
+ * set a value, save the old value in the caller, and then reinstate it later.
+ */
+int test_set_oom_score_adj(int new_val)
+{
+ struct sighand_struct *sighand = current->sighand;
+ int old_val;
+
+ spin_lock_irq(&sighand->siglock);
+ old_val = current->signal->oom_score_adj;
+ if (new_val != old_val) {
+ if (new_val == OOM_SCORE_ADJ_MIN)
+ atomic_inc(¤t->mm->oom_disable_count);
+ else if (old_val == OOM_SCORE_ADJ_MIN)
+ atomic_dec(¤t->mm->oom_disable_count);
+ current->signal->oom_score_adj = new_val;
+ }
+ spin_unlock_irq(&sighand->siglock);
+
+ return old_val;
+}
+
#ifdef CONFIG_NUMA
/**
* has_intersects_mems_allowed() - check task eligiblity for kill
@@ -155,15 +182,6 @@
}
/*
- * When the PF_OOM_ORIGIN bit is set, it indicates the task should have
- * priority for oom killing.
- */
- if (p->flags & PF_OOM_ORIGIN) {
- task_unlock(p);
- return 1000;
- }
-
- /*
* The memory controller may have a limit of 0 bytes, so avoid a divide
* by zero, if necessary.
*/
diff --git a/mm/page_alloc.c b/mm/page_alloc.c
index 9d5498e..2a00f17 100644
--- a/mm/page_alloc.c
+++ b/mm/page_alloc.c
@@ -30,6 +30,7 @@
#include <linux/pagevec.h>
#include <linux/blkdev.h>
#include <linux/slab.h>
+#include <linux/ratelimit.h>
#include <linux/oom.h>
#include <linux/notifier.h>
#include <linux/topology.h>
@@ -39,6 +40,7 @@
#include <linux/memory_hotplug.h>
#include <linux/nodemask.h>
#include <linux/vmalloc.h>
+#include <linux/vmstat.h>
#include <linux/mempolicy.h>
#include <linux/stop_machine.h>
#include <linux/sort.h>
@@ -1735,6 +1737,45 @@
return ret;
}
+static DEFINE_RATELIMIT_STATE(nopage_rs,
+ DEFAULT_RATELIMIT_INTERVAL,
+ DEFAULT_RATELIMIT_BURST);
+
+void warn_alloc_failed(gfp_t gfp_mask, int order, const char *fmt, ...)
+{
+ va_list args;
+ unsigned int filter = SHOW_MEM_FILTER_NODES;
+
+ if ((gfp_mask & __GFP_NOWARN) || !__ratelimit(&nopage_rs))
+ return;
+
+ /*
+ * This documents exceptions given to allocations in certain
+ * contexts that are allowed to allocate outside current's set
+ * of allowed nodes.
+ */
+ if (!(gfp_mask & __GFP_NOMEMALLOC))
+ if (test_thread_flag(TIF_MEMDIE) ||
+ (current->flags & (PF_MEMALLOC | PF_EXITING)))
+ filter &= ~SHOW_MEM_FILTER_NODES;
+ if (in_interrupt() || !(gfp_mask & __GFP_WAIT))
+ filter &= ~SHOW_MEM_FILTER_NODES;
+
+ if (fmt) {
+ printk(KERN_WARNING);
+ va_start(args, fmt);
+ vprintk(fmt, args);
+ va_end(args);
+ }
+
+ pr_warning("%s: page allocation failure: order:%d, mode:0x%x\n",
+ current->comm, order, gfp_mask);
+
+ dump_stack();
+ if (!should_suppress_show_mem())
+ show_mem(filter);
+}
+
static inline int
should_alloc_retry(gfp_t gfp_mask, unsigned int order,
unsigned long pages_reclaimed)
@@ -2065,6 +2106,7 @@
first_zones_zonelist(zonelist, high_zoneidx, NULL,
&preferred_zone);
+rebalance:
/* This is the last chance, in general, before the goto nopage. */
page = get_page_from_freelist(gfp_mask, nodemask, order, zonelist,
high_zoneidx, alloc_flags & ~ALLOC_NO_WATERMARKS,
@@ -2072,7 +2114,6 @@
if (page)
goto got_pg;
-rebalance:
/* Allocate without watermarks if the context allows */
if (alloc_flags & ALLOC_NO_WATERMARKS) {
page = __alloc_pages_high_priority(gfp_mask, order,
@@ -2106,7 +2147,7 @@
sync_migration);
if (page)
goto got_pg;
- sync_migration = !(gfp_mask & __GFP_NO_KSWAPD);
+ sync_migration = true;
/* Try direct reclaim and then allocating */
page = __alloc_pages_direct_reclaim(gfp_mask, order,
@@ -2177,27 +2218,7 @@
}
nopage:
- if (!(gfp_mask & __GFP_NOWARN) && printk_ratelimit()) {
- unsigned int filter = SHOW_MEM_FILTER_NODES;
-
- /*
- * This documents exceptions given to allocations in certain
- * contexts that are allowed to allocate outside current's set
- * of allowed nodes.
- */
- if (!(gfp_mask & __GFP_NOMEMALLOC))
- if (test_thread_flag(TIF_MEMDIE) ||
- (current->flags & (PF_MEMALLOC | PF_EXITING)))
- filter &= ~SHOW_MEM_FILTER_NODES;
- if (in_interrupt() || !wait)
- filter &= ~SHOW_MEM_FILTER_NODES;
-
- pr_warning("%s: page allocation failure. order:%d, mode:0x%x\n",
- current->comm, order, gfp_mask);
- dump_stack();
- if (!should_suppress_show_mem())
- show_mem(filter);
- }
+ warn_alloc_failed(gfp_mask, order, NULL);
return page;
got_pg:
if (kmemcheck_enabled)
@@ -2226,6 +2247,10 @@
if (should_fail_alloc_page(gfp_mask, order))
return NULL;
+#ifndef CONFIG_ZONE_DMA
+ if (WARN_ON_ONCE(gfp_mask & __GFP_DMA))
+ return NULL;
+#endif
/*
* Check the zones suitable for the gfp_mask contain at least one
@@ -2473,10 +2498,10 @@
#endif
/*
- * Determine whether the zone's node should be displayed or not, depending on
- * whether SHOW_MEM_FILTER_NODES was passed to __show_free_areas().
+ * Determine whether the node should be displayed or not, depending on whether
+ * SHOW_MEM_FILTER_NODES was passed to show_free_areas().
*/
-static bool skip_free_areas_zone(unsigned int flags, const struct zone *zone)
+bool skip_free_areas_node(unsigned int flags, int nid)
{
bool ret = false;
@@ -2484,8 +2509,7 @@
goto out;
get_mems_allowed();
- ret = !node_isset(zone->zone_pgdat->node_id,
- cpuset_current_mems_allowed);
+ ret = !node_isset(nid, cpuset_current_mems_allowed);
put_mems_allowed();
out:
return ret;
@@ -2500,13 +2524,13 @@
* Suppresses nodes that are not allowed by current's cpuset if
* SHOW_MEM_FILTER_NODES is passed.
*/
-void __show_free_areas(unsigned int filter)
+void show_free_areas(unsigned int filter)
{
int cpu;
struct zone *zone;
for_each_populated_zone(zone) {
- if (skip_free_areas_zone(filter, zone))
+ if (skip_free_areas_node(filter, zone_to_nid(zone)))
continue;
show_node(zone);
printk("%s per-cpu:\n", zone->name);
@@ -2549,7 +2573,7 @@
for_each_populated_zone(zone) {
int i;
- if (skip_free_areas_zone(filter, zone))
+ if (skip_free_areas_node(filter, zone_to_nid(zone)))
continue;
show_node(zone);
printk("%s"
@@ -2618,7 +2642,7 @@
for_each_populated_zone(zone) {
unsigned long nr[MAX_ORDER], flags, order, total = 0;
- if (skip_free_areas_zone(filter, zone))
+ if (skip_free_areas_node(filter, zone_to_nid(zone)))
continue;
show_node(zone);
printk("%s: ", zone->name);
@@ -2639,11 +2663,6 @@
show_swap_cache_info();
}
-void show_free_areas(void)
-{
- __show_free_areas(0);
-}
-
static void zoneref_set_zone(struct zone *zone, struct zoneref *zoneref)
{
zoneref->zone = zone;
@@ -3314,6 +3333,20 @@
#define LONG_ALIGN(x) (((x)+(sizeof(long))-1)&~((sizeof(long))-1))
/*
+ * Check if a pageblock contains reserved pages
+ */
+static int pageblock_is_reserved(unsigned long start_pfn, unsigned long end_pfn)
+{
+ unsigned long pfn;
+
+ for (pfn = start_pfn; pfn < end_pfn; pfn++) {
+ if (!pfn_valid_within(pfn) || PageReserved(pfn_to_page(pfn)))
+ return 1;
+ }
+ return 0;
+}
+
+/*
* Mark a number of pageblocks as MIGRATE_RESERVE. The number
* of blocks reserved is based on min_wmark_pages(zone). The memory within
* the reserve will tend to store contiguous free pages. Setting min_free_kbytes
@@ -3322,7 +3355,7 @@
*/
static void setup_zone_migrate_reserve(struct zone *zone)
{
- unsigned long start_pfn, pfn, end_pfn;
+ unsigned long start_pfn, pfn, end_pfn, block_end_pfn;
struct page *page;
unsigned long block_migratetype;
int reserve;
@@ -3352,7 +3385,8 @@
continue;
/* Blocks with reserved pages will never free, skip them. */
- if (PageReserved(page))
+ block_end_pfn = min(pfn + pageblock_nr_pages, end_pfn);
+ if (pageblock_is_reserved(pfn, block_end_pfn))
continue;
block_migratetype = get_pageblock_migratetype(page);
@@ -5100,7 +5134,7 @@
* 1TB 101 10GB
* 10TB 320 32GB
*/
-void calculate_zone_inactive_ratio(struct zone *zone)
+static void __meminit calculate_zone_inactive_ratio(struct zone *zone)
{
unsigned int gb, ratio;
@@ -5114,7 +5148,7 @@
zone->inactive_ratio = ratio;
}
-static void __init setup_per_zone_inactive_ratio(void)
+static void __meminit setup_per_zone_inactive_ratio(void)
{
struct zone *zone;
@@ -5146,7 +5180,7 @@
* 8192MB: 11584k
* 16384MB: 16384k
*/
-static int __init init_per_zone_wmark_min(void)
+int __meminit init_per_zone_wmark_min(void)
{
unsigned long lowmem_kbytes;
@@ -5158,6 +5192,7 @@
if (min_free_kbytes > 65536)
min_free_kbytes = 65536;
setup_per_zone_wmarks();
+ refresh_zone_stat_thresholds();
setup_per_zone_lowmem_reserve();
setup_per_zone_inactive_ratio();
return 0;
@@ -5508,10 +5543,8 @@
struct memory_isolate_notify arg;
int notifier_ret;
int ret = -EBUSY;
- int zone_idx;
zone = page_zone(page);
- zone_idx = zone_idx(zone);
spin_lock_irqsave(&zone->lock, flags);
diff --git a/mm/percpu.c b/mm/percpu.c
index a160db3..bf80e55 100644
--- a/mm/percpu.c
+++ b/mm/percpu.c
@@ -1215,8 +1215,10 @@
PCPU_SETUP_BUG_ON(ai->nr_groups <= 0);
#ifdef CONFIG_SMP
PCPU_SETUP_BUG_ON(!ai->static_size);
+ PCPU_SETUP_BUG_ON((unsigned long)__per_cpu_start & ~PAGE_MASK);
#endif
PCPU_SETUP_BUG_ON(!base_addr);
+ PCPU_SETUP_BUG_ON((unsigned long)base_addr & ~PAGE_MASK);
PCPU_SETUP_BUG_ON(ai->unit_size < size_sum);
PCPU_SETUP_BUG_ON(ai->unit_size & ~PAGE_MASK);
PCPU_SETUP_BUG_ON(ai->unit_size < PCPU_MIN_UNIT_SIZE);
@@ -1645,8 +1647,8 @@
/* warn if maximum distance is further than 75% of vmalloc space */
if (max_distance > (VMALLOC_END - VMALLOC_START) * 3 / 4) {
pr_warning("PERCPU: max_distance=0x%zx too large for vmalloc "
- "space 0x%lx\n",
- max_distance, VMALLOC_END - VMALLOC_START);
+ "space 0x%lx\n", max_distance,
+ (unsigned long)(VMALLOC_END - VMALLOC_START));
#ifdef CONFIG_NEED_PER_CPU_PAGE_FIRST_CHUNK
/* and fail if we have fallback */
rc = -EINVAL;
diff --git a/mm/readahead.c b/mm/readahead.c
index 2c0cc48..867f9dd 100644
--- a/mm/readahead.c
+++ b/mm/readahead.c
@@ -180,7 +180,7 @@
if (page)
continue;
- page = page_cache_alloc_cold(mapping);
+ page = page_cache_alloc_readahead(mapping);
if (!page)
break;
page->index = page_offset;
diff --git a/mm/rmap.c b/mm/rmap.c
index 8da044a..3a39b51 100644
--- a/mm/rmap.c
+++ b/mm/rmap.c
@@ -24,8 +24,8 @@
* inode->i_alloc_sem (vmtruncate_range)
* mm->mmap_sem
* page->flags PG_locked (lock_page)
- * mapping->i_mmap_lock
- * anon_vma->lock
+ * mapping->i_mmap_mutex
+ * anon_vma->mutex
* mm->page_table_lock or pte_lock
* zone->lru_lock (in mark_page_accessed, isolate_lru_page)
* swap_lock (in swap_duplicate, swap_info_get)
@@ -40,7 +40,7 @@
*
* (code doesn't rely on that order so it could be switched around)
* ->tasklist_lock
- * anon_vma->lock (memory_failure, collect_procs_anon)
+ * anon_vma->mutex (memory_failure, collect_procs_anon)
* pte map lock
*/
@@ -86,6 +86,29 @@
static inline void anon_vma_free(struct anon_vma *anon_vma)
{
VM_BUG_ON(atomic_read(&anon_vma->refcount));
+
+ /*
+ * Synchronize against page_lock_anon_vma() such that
+ * we can safely hold the lock without the anon_vma getting
+ * freed.
+ *
+ * Relies on the full mb implied by the atomic_dec_and_test() from
+ * put_anon_vma() against the acquire barrier implied by
+ * mutex_trylock() from page_lock_anon_vma(). This orders:
+ *
+ * page_lock_anon_vma() VS put_anon_vma()
+ * mutex_trylock() atomic_dec_and_test()
+ * LOCK MB
+ * atomic_read() mutex_is_locked()
+ *
+ * LOCK should suffice since the actual taking of the lock must
+ * happen _before_ what follows.
+ */
+ if (mutex_is_locked(&anon_vma->root->mutex)) {
+ anon_vma_lock(anon_vma);
+ anon_vma_unlock(anon_vma);
+ }
+
kmem_cache_free(anon_vma_cachep, anon_vma);
}
@@ -307,7 +330,7 @@
{
struct anon_vma *anon_vma = data;
- spin_lock_init(&anon_vma->lock);
+ mutex_init(&anon_vma->mutex);
atomic_set(&anon_vma->refcount, 0);
INIT_LIST_HEAD(&anon_vma->head);
}
@@ -320,12 +343,26 @@
}
/*
- * Getting a lock on a stable anon_vma from a page off the LRU is
- * tricky: page_lock_anon_vma rely on RCU to guard against the races.
+ * Getting a lock on a stable anon_vma from a page off the LRU is tricky!
+ *
+ * Since there is no serialization what so ever against page_remove_rmap()
+ * the best this function can do is return a locked anon_vma that might
+ * have been relevant to this page.
+ *
+ * The page might have been remapped to a different anon_vma or the anon_vma
+ * returned may already be freed (and even reused).
+ *
+ * All users of this function must be very careful when walking the anon_vma
+ * chain and verify that the page in question is indeed mapped in it
+ * [ something equivalent to page_mapped_in_vma() ].
+ *
+ * Since anon_vma's slab is DESTROY_BY_RCU and we know from page_remove_rmap()
+ * that the anon_vma pointer from page->mapping is valid if there is a
+ * mapcount, we can dereference the anon_vma after observing those.
*/
-struct anon_vma *__page_lock_anon_vma(struct page *page)
+struct anon_vma *page_get_anon_vma(struct page *page)
{
- struct anon_vma *anon_vma, *root_anon_vma;
+ struct anon_vma *anon_vma = NULL;
unsigned long anon_mapping;
rcu_read_lock();
@@ -336,32 +373,97 @@
goto out;
anon_vma = (struct anon_vma *) (anon_mapping - PAGE_MAPPING_ANON);
- root_anon_vma = ACCESS_ONCE(anon_vma->root);
- spin_lock(&root_anon_vma->lock);
+ if (!atomic_inc_not_zero(&anon_vma->refcount)) {
+ anon_vma = NULL;
+ goto out;
+ }
/*
* If this page is still mapped, then its anon_vma cannot have been
- * freed. But if it has been unmapped, we have no security against
- * the anon_vma structure being freed and reused (for another anon_vma:
- * SLAB_DESTROY_BY_RCU guarantees that - so the spin_lock above cannot
- * corrupt): with anon_vma_prepare() or anon_vma_fork() redirecting
- * anon_vma->root before page_unlock_anon_vma() is called to unlock.
+ * freed. But if it has been unmapped, we have no security against the
+ * anon_vma structure being freed and reused (for another anon_vma:
+ * SLAB_DESTROY_BY_RCU guarantees that - so the atomic_inc_not_zero()
+ * above cannot corrupt).
*/
- if (page_mapped(page))
- return anon_vma;
-
- spin_unlock(&root_anon_vma->lock);
+ if (!page_mapped(page)) {
+ put_anon_vma(anon_vma);
+ anon_vma = NULL;
+ }
out:
rcu_read_unlock();
- return NULL;
+
+ return anon_vma;
+}
+
+/*
+ * Similar to page_get_anon_vma() except it locks the anon_vma.
+ *
+ * Its a little more complex as it tries to keep the fast path to a single
+ * atomic op -- the trylock. If we fail the trylock, we fall back to getting a
+ * reference like with page_get_anon_vma() and then block on the mutex.
+ */
+struct anon_vma *page_lock_anon_vma(struct page *page)
+{
+ struct anon_vma *anon_vma = NULL;
+ unsigned long anon_mapping;
+
+ rcu_read_lock();
+ anon_mapping = (unsigned long) ACCESS_ONCE(page->mapping);
+ if ((anon_mapping & PAGE_MAPPING_FLAGS) != PAGE_MAPPING_ANON)
+ goto out;
+ if (!page_mapped(page))
+ goto out;
+
+ anon_vma = (struct anon_vma *) (anon_mapping - PAGE_MAPPING_ANON);
+ if (mutex_trylock(&anon_vma->root->mutex)) {
+ /*
+ * If we observe a !0 refcount, then holding the lock ensures
+ * the anon_vma will not go away, see __put_anon_vma().
+ */
+ if (!atomic_read(&anon_vma->refcount)) {
+ anon_vma_unlock(anon_vma);
+ anon_vma = NULL;
+ }
+ goto out;
+ }
+
+ /* trylock failed, we got to sleep */
+ if (!atomic_inc_not_zero(&anon_vma->refcount)) {
+ anon_vma = NULL;
+ goto out;
+ }
+
+ if (!page_mapped(page)) {
+ put_anon_vma(anon_vma);
+ anon_vma = NULL;
+ goto out;
+ }
+
+ /* we pinned the anon_vma, its safe to sleep */
+ rcu_read_unlock();
+ anon_vma_lock(anon_vma);
+
+ if (atomic_dec_and_test(&anon_vma->refcount)) {
+ /*
+ * Oops, we held the last refcount, release the lock
+ * and bail -- can't simply use put_anon_vma() because
+ * we'll deadlock on the anon_vma_lock() recursion.
+ */
+ anon_vma_unlock(anon_vma);
+ __put_anon_vma(anon_vma);
+ anon_vma = NULL;
+ }
+
+ return anon_vma;
+
+out:
+ rcu_read_unlock();
+ return anon_vma;
}
void page_unlock_anon_vma(struct anon_vma *anon_vma)
- __releases(&anon_vma->root->lock)
- __releases(RCU)
{
anon_vma_unlock(anon_vma);
- rcu_read_unlock();
}
/*
@@ -646,14 +748,14 @@
* The page lock not only makes sure that page->mapping cannot
* suddenly be NULLified by truncation, it makes sure that the
* structure at mapping cannot be freed and reused yet,
- * so we can safely take mapping->i_mmap_lock.
+ * so we can safely take mapping->i_mmap_mutex.
*/
BUG_ON(!PageLocked(page));
- spin_lock(&mapping->i_mmap_lock);
+ mutex_lock(&mapping->i_mmap_mutex);
/*
- * i_mmap_lock does not stabilize mapcount at all, but mapcount
+ * i_mmap_mutex does not stabilize mapcount at all, but mapcount
* is more likely to be accurate if we note it after spinning.
*/
mapcount = page_mapcount(page);
@@ -675,7 +777,7 @@
break;
}
- spin_unlock(&mapping->i_mmap_lock);
+ mutex_unlock(&mapping->i_mmap_mutex);
return referenced;
}
@@ -719,7 +821,7 @@
unlock_page(page);
}
out:
- if (page_test_and_clear_young(page))
+ if (page_test_and_clear_young(page_to_pfn(page)))
referenced++;
return referenced;
@@ -762,7 +864,7 @@
BUG_ON(PageAnon(page));
- spin_lock(&mapping->i_mmap_lock);
+ mutex_lock(&mapping->i_mmap_mutex);
vma_prio_tree_foreach(vma, &iter, &mapping->i_mmap, pgoff, pgoff) {
if (vma->vm_flags & VM_SHARED) {
unsigned long address = vma_address(page, vma);
@@ -771,7 +873,7 @@
ret += page_mkclean_one(page, vma, address);
}
}
- spin_unlock(&mapping->i_mmap_lock);
+ mutex_unlock(&mapping->i_mmap_mutex);
return ret;
}
@@ -785,10 +887,8 @@
struct address_space *mapping = page_mapping(page);
if (mapping) {
ret = page_mkclean_file(mapping, page);
- if (page_test_dirty(page)) {
- page_clear_dirty(page, 1);
+ if (page_test_and_clear_dirty(page_to_pfn(page), 1))
ret = 1;
- }
}
}
@@ -981,10 +1081,9 @@
* not if it's in swapcache - there might be another pte slot
* containing the swap entry, but page not yet written to swap.
*/
- if ((!PageAnon(page) || PageSwapCache(page)) && page_test_dirty(page)) {
- page_clear_dirty(page, 1);
+ if ((!PageAnon(page) || PageSwapCache(page)) &&
+ page_test_and_clear_dirty(page_to_pfn(page), 1))
set_page_dirty(page);
- }
/*
* Hugepages are not counted in NR_ANON_PAGES nor NR_FILE_MAPPED
* and not charged by memcg for now.
@@ -1122,7 +1221,7 @@
/*
* We need mmap_sem locking, Otherwise VM_LOCKED check makes
* unstable result and race. Plus, We can't wait here because
- * we now hold anon_vma->lock or mapping->i_mmap_lock.
+ * we now hold anon_vma->mutex or mapping->i_mmap_mutex.
* if trylock failed, the page remain in evictable lru and later
* vmscan could retry to move the page to unevictable lru if the
* page is actually mlocked.
@@ -1348,7 +1447,7 @@
unsigned long max_nl_size = 0;
unsigned int mapcount;
- spin_lock(&mapping->i_mmap_lock);
+ mutex_lock(&mapping->i_mmap_mutex);
vma_prio_tree_foreach(vma, &iter, &mapping->i_mmap, pgoff, pgoff) {
unsigned long address = vma_address(page, vma);
if (address == -EFAULT)
@@ -1394,7 +1493,7 @@
mapcount = page_mapcount(page);
if (!mapcount)
goto out;
- cond_resched_lock(&mapping->i_mmap_lock);
+ cond_resched();
max_nl_size = (max_nl_size + CLUSTER_SIZE - 1) & CLUSTER_MASK;
if (max_nl_cursor == 0)
@@ -1416,7 +1515,7 @@
}
vma->vm_private_data = (void *) max_nl_cursor;
}
- cond_resched_lock(&mapping->i_mmap_lock);
+ cond_resched();
max_nl_cursor += CLUSTER_SIZE;
} while (max_nl_cursor <= max_nl_size);
@@ -1428,7 +1527,7 @@
list_for_each_entry(vma, &mapping->i_mmap_nonlinear, shared.vm_set.list)
vma->vm_private_data = NULL;
out:
- spin_unlock(&mapping->i_mmap_lock);
+ mutex_unlock(&mapping->i_mmap_mutex);
return ret;
}
@@ -1547,7 +1646,7 @@
if (!mapping)
return ret;
- spin_lock(&mapping->i_mmap_lock);
+ mutex_lock(&mapping->i_mmap_mutex);
vma_prio_tree_foreach(vma, &iter, &mapping->i_mmap, pgoff, pgoff) {
unsigned long address = vma_address(page, vma);
if (address == -EFAULT)
@@ -1561,7 +1660,7 @@
* never contain migration ptes. Decide what to do about this
* limitation to linear when we need rmap_walk() on nonlinear.
*/
- spin_unlock(&mapping->i_mmap_lock);
+ mutex_unlock(&mapping->i_mmap_mutex);
return ret;
}
diff --git a/mm/shmem.c b/mm/shmem.c
index ba4ad28..69edb45 100644
--- a/mm/shmem.c
+++ b/mm/shmem.c
@@ -99,6 +99,13 @@
/* Pretend that each entry is of this size in directory's i_size */
#define BOGO_DIRENT_SIZE 20
+struct shmem_xattr {
+ struct list_head list; /* anchored by shmem_inode_info->xattr_list */
+ char *name; /* xattr name */
+ size_t size;
+ char value[0];
+};
+
/* Flag allocation requirements to shmem_getpage and shmem_swp_alloc */
enum sgp_type {
SGP_READ, /* don't exceed i_size, don't allocate page */
@@ -822,6 +829,7 @@
static void shmem_evict_inode(struct inode *inode)
{
struct shmem_inode_info *info = SHMEM_I(inode);
+ struct shmem_xattr *xattr, *nxattr;
if (inode->i_mapping->a_ops == &shmem_aops) {
truncate_inode_pages(inode->i_mapping, 0);
@@ -834,6 +842,11 @@
mutex_unlock(&shmem_swaplist_mutex);
}
}
+
+ list_for_each_entry_safe(xattr, nxattr, &info->xattr_list, list) {
+ kfree(xattr->name);
+ kfree(xattr);
+ }
BUG_ON(inode->i_blocks);
shmem_free_inode(inode->i_sb);
end_writeback(inode);
@@ -1615,6 +1628,7 @@
spin_lock_init(&info->lock);
info->flags = flags & VM_NORESERVE;
INIT_LIST_HEAD(&info->swaplist);
+ INIT_LIST_HEAD(&info->xattr_list);
cache_no_acl(inode);
switch (mode & S_IFMT) {
@@ -2014,9 +2028,9 @@
info = SHMEM_I(inode);
inode->i_size = len-1;
- if (len <= (char *)inode - (char *)info) {
+ if (len <= SHMEM_SYMLINK_INLINE_LEN) {
/* do it inline */
- memcpy(info, symname, len);
+ memcpy(info->inline_symlink, symname, len);
inode->i_op = &shmem_symlink_inline_operations;
} else {
error = shmem_getpage(inode, 0, &page, SGP_WRITE, NULL);
@@ -2042,7 +2056,7 @@
static void *shmem_follow_link_inline(struct dentry *dentry, struct nameidata *nd)
{
- nd_set_link(nd, (char *)SHMEM_I(dentry->d_inode));
+ nd_set_link(nd, SHMEM_I(dentry->d_inode)->inline_symlink);
return NULL;
}
@@ -2066,63 +2080,253 @@
}
}
+#ifdef CONFIG_TMPFS_XATTR
+/*
+ * Superblocks without xattr inode operations may get some security.* xattr
+ * support from the LSM "for free". As soon as we have any other xattrs
+ * like ACLs, we also need to implement the security.* handlers at
+ * filesystem level, though.
+ */
+
+static int shmem_xattr_get(struct dentry *dentry, const char *name,
+ void *buffer, size_t size)
+{
+ struct shmem_inode_info *info;
+ struct shmem_xattr *xattr;
+ int ret = -ENODATA;
+
+ info = SHMEM_I(dentry->d_inode);
+
+ spin_lock(&info->lock);
+ list_for_each_entry(xattr, &info->xattr_list, list) {
+ if (strcmp(name, xattr->name))
+ continue;
+
+ ret = xattr->size;
+ if (buffer) {
+ if (size < xattr->size)
+ ret = -ERANGE;
+ else
+ memcpy(buffer, xattr->value, xattr->size);
+ }
+ break;
+ }
+ spin_unlock(&info->lock);
+ return ret;
+}
+
+static int shmem_xattr_set(struct dentry *dentry, const char *name,
+ const void *value, size_t size, int flags)
+{
+ struct inode *inode = dentry->d_inode;
+ struct shmem_inode_info *info = SHMEM_I(inode);
+ struct shmem_xattr *xattr;
+ struct shmem_xattr *new_xattr = NULL;
+ size_t len;
+ int err = 0;
+
+ /* value == NULL means remove */
+ if (value) {
+ /* wrap around? */
+ len = sizeof(*new_xattr) + size;
+ if (len <= sizeof(*new_xattr))
+ return -ENOMEM;
+
+ new_xattr = kmalloc(len, GFP_KERNEL);
+ if (!new_xattr)
+ return -ENOMEM;
+
+ new_xattr->name = kstrdup(name, GFP_KERNEL);
+ if (!new_xattr->name) {
+ kfree(new_xattr);
+ return -ENOMEM;
+ }
+
+ new_xattr->size = size;
+ memcpy(new_xattr->value, value, size);
+ }
+
+ spin_lock(&info->lock);
+ list_for_each_entry(xattr, &info->xattr_list, list) {
+ if (!strcmp(name, xattr->name)) {
+ if (flags & XATTR_CREATE) {
+ xattr = new_xattr;
+ err = -EEXIST;
+ } else if (new_xattr) {
+ list_replace(&xattr->list, &new_xattr->list);
+ } else {
+ list_del(&xattr->list);
+ }
+ goto out;
+ }
+ }
+ if (flags & XATTR_REPLACE) {
+ xattr = new_xattr;
+ err = -ENODATA;
+ } else {
+ list_add(&new_xattr->list, &info->xattr_list);
+ xattr = NULL;
+ }
+out:
+ spin_unlock(&info->lock);
+ if (xattr)
+ kfree(xattr->name);
+ kfree(xattr);
+ return err;
+}
+
+
+static const struct xattr_handler *shmem_xattr_handlers[] = {
+#ifdef CONFIG_TMPFS_POSIX_ACL
+ &generic_acl_access_handler,
+ &generic_acl_default_handler,
+#endif
+ NULL
+};
+
+static int shmem_xattr_validate(const char *name)
+{
+ struct { const char *prefix; size_t len; } arr[] = {
+ { XATTR_SECURITY_PREFIX, XATTR_SECURITY_PREFIX_LEN },
+ { XATTR_TRUSTED_PREFIX, XATTR_TRUSTED_PREFIX_LEN }
+ };
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(arr); i++) {
+ size_t preflen = arr[i].len;
+ if (strncmp(name, arr[i].prefix, preflen) == 0) {
+ if (!name[preflen])
+ return -EINVAL;
+ return 0;
+ }
+ }
+ return -EOPNOTSUPP;
+}
+
+static ssize_t shmem_getxattr(struct dentry *dentry, const char *name,
+ void *buffer, size_t size)
+{
+ int err;
+
+ /*
+ * If this is a request for a synthetic attribute in the system.*
+ * namespace use the generic infrastructure to resolve a handler
+ * for it via sb->s_xattr.
+ */
+ if (!strncmp(name, XATTR_SYSTEM_PREFIX, XATTR_SYSTEM_PREFIX_LEN))
+ return generic_getxattr(dentry, name, buffer, size);
+
+ err = shmem_xattr_validate(name);
+ if (err)
+ return err;
+
+ return shmem_xattr_get(dentry, name, buffer, size);
+}
+
+static int shmem_setxattr(struct dentry *dentry, const char *name,
+ const void *value, size_t size, int flags)
+{
+ int err;
+
+ /*
+ * If this is a request for a synthetic attribute in the system.*
+ * namespace use the generic infrastructure to resolve a handler
+ * for it via sb->s_xattr.
+ */
+ if (!strncmp(name, XATTR_SYSTEM_PREFIX, XATTR_SYSTEM_PREFIX_LEN))
+ return generic_setxattr(dentry, name, value, size, flags);
+
+ err = shmem_xattr_validate(name);
+ if (err)
+ return err;
+
+ if (size == 0)
+ value = ""; /* empty EA, do not remove */
+
+ return shmem_xattr_set(dentry, name, value, size, flags);
+
+}
+
+static int shmem_removexattr(struct dentry *dentry, const char *name)
+{
+ int err;
+
+ /*
+ * If this is a request for a synthetic attribute in the system.*
+ * namespace use the generic infrastructure to resolve a handler
+ * for it via sb->s_xattr.
+ */
+ if (!strncmp(name, XATTR_SYSTEM_PREFIX, XATTR_SYSTEM_PREFIX_LEN))
+ return generic_removexattr(dentry, name);
+
+ err = shmem_xattr_validate(name);
+ if (err)
+ return err;
+
+ return shmem_xattr_set(dentry, name, NULL, 0, XATTR_REPLACE);
+}
+
+static bool xattr_is_trusted(const char *name)
+{
+ return !strncmp(name, XATTR_TRUSTED_PREFIX, XATTR_TRUSTED_PREFIX_LEN);
+}
+
+static ssize_t shmem_listxattr(struct dentry *dentry, char *buffer, size_t size)
+{
+ bool trusted = capable(CAP_SYS_ADMIN);
+ struct shmem_xattr *xattr;
+ struct shmem_inode_info *info;
+ size_t used = 0;
+
+ info = SHMEM_I(dentry->d_inode);
+
+ spin_lock(&info->lock);
+ list_for_each_entry(xattr, &info->xattr_list, list) {
+ size_t len;
+
+ /* skip "trusted." attributes for unprivileged callers */
+ if (!trusted && xattr_is_trusted(xattr->name))
+ continue;
+
+ len = strlen(xattr->name) + 1;
+ used += len;
+ if (buffer) {
+ if (size < used) {
+ used = -ERANGE;
+ break;
+ }
+ memcpy(buffer, xattr->name, len);
+ buffer += len;
+ }
+ }
+ spin_unlock(&info->lock);
+
+ return used;
+}
+#endif /* CONFIG_TMPFS_XATTR */
+
static const struct inode_operations shmem_symlink_inline_operations = {
.readlink = generic_readlink,
.follow_link = shmem_follow_link_inline,
+#ifdef CONFIG_TMPFS_XATTR
+ .setxattr = shmem_setxattr,
+ .getxattr = shmem_getxattr,
+ .listxattr = shmem_listxattr,
+ .removexattr = shmem_removexattr,
+#endif
};
static const struct inode_operations shmem_symlink_inode_operations = {
.readlink = generic_readlink,
.follow_link = shmem_follow_link,
.put_link = shmem_put_link,
-};
-
-#ifdef CONFIG_TMPFS_POSIX_ACL
-/*
- * Superblocks without xattr inode operations will get security.* xattr
- * support from the VFS "for free". As soon as we have any other xattrs
- * like ACLs, we also need to implement the security.* handlers at
- * filesystem level, though.
- */
-
-static size_t shmem_xattr_security_list(struct dentry *dentry, char *list,
- size_t list_len, const char *name,
- size_t name_len, int handler_flags)
-{
- return security_inode_listsecurity(dentry->d_inode, list, list_len);
-}
-
-static int shmem_xattr_security_get(struct dentry *dentry, const char *name,
- void *buffer, size_t size, int handler_flags)
-{
- if (strcmp(name, "") == 0)
- return -EINVAL;
- return xattr_getsecurity(dentry->d_inode, name, buffer, size);
-}
-
-static int shmem_xattr_security_set(struct dentry *dentry, const char *name,
- const void *value, size_t size, int flags, int handler_flags)
-{
- if (strcmp(name, "") == 0)
- return -EINVAL;
- return security_inode_setsecurity(dentry->d_inode, name, value,
- size, flags);
-}
-
-static const struct xattr_handler shmem_xattr_security_handler = {
- .prefix = XATTR_SECURITY_PREFIX,
- .list = shmem_xattr_security_list,
- .get = shmem_xattr_security_get,
- .set = shmem_xattr_security_set,
-};
-
-static const struct xattr_handler *shmem_xattr_handlers[] = {
- &generic_acl_access_handler,
- &generic_acl_default_handler,
- &shmem_xattr_security_handler,
- NULL
-};
+#ifdef CONFIG_TMPFS_XATTR
+ .setxattr = shmem_setxattr,
+ .getxattr = shmem_getxattr,
+ .listxattr = shmem_listxattr,
+ .removexattr = shmem_removexattr,
#endif
+};
static struct dentry *shmem_get_parent(struct dentry *child)
{
@@ -2402,8 +2606,10 @@
sb->s_magic = TMPFS_MAGIC;
sb->s_op = &shmem_ops;
sb->s_time_gran = 1;
-#ifdef CONFIG_TMPFS_POSIX_ACL
+#ifdef CONFIG_TMPFS_XATTR
sb->s_xattr = shmem_xattr_handlers;
+#endif
+#ifdef CONFIG_TMPFS_POSIX_ACL
sb->s_flags |= MS_POSIXACL;
#endif
@@ -2501,11 +2707,13 @@
static const struct inode_operations shmem_inode_operations = {
.setattr = shmem_notify_change,
.truncate_range = shmem_truncate_range,
+#ifdef CONFIG_TMPFS_XATTR
+ .setxattr = shmem_setxattr,
+ .getxattr = shmem_getxattr,
+ .listxattr = shmem_listxattr,
+ .removexattr = shmem_removexattr,
+#endif
#ifdef CONFIG_TMPFS_POSIX_ACL
- .setxattr = generic_setxattr,
- .getxattr = generic_getxattr,
- .listxattr = generic_listxattr,
- .removexattr = generic_removexattr,
.check_acl = generic_check_acl,
#endif
@@ -2523,23 +2731,27 @@
.mknod = shmem_mknod,
.rename = shmem_rename,
#endif
+#ifdef CONFIG_TMPFS_XATTR
+ .setxattr = shmem_setxattr,
+ .getxattr = shmem_getxattr,
+ .listxattr = shmem_listxattr,
+ .removexattr = shmem_removexattr,
+#endif
#ifdef CONFIG_TMPFS_POSIX_ACL
.setattr = shmem_notify_change,
- .setxattr = generic_setxattr,
- .getxattr = generic_getxattr,
- .listxattr = generic_listxattr,
- .removexattr = generic_removexattr,
.check_acl = generic_check_acl,
#endif
};
static const struct inode_operations shmem_special_inode_operations = {
+#ifdef CONFIG_TMPFS_XATTR
+ .setxattr = shmem_setxattr,
+ .getxattr = shmem_getxattr,
+ .listxattr = shmem_listxattr,
+ .removexattr = shmem_removexattr,
+#endif
#ifdef CONFIG_TMPFS_POSIX_ACL
.setattr = shmem_notify_change,
- .setxattr = generic_setxattr,
- .getxattr = generic_getxattr,
- .listxattr = generic_listxattr,
- .removexattr = generic_removexattr,
.check_acl = generic_check_acl,
#endif
};
diff --git a/mm/slub.c b/mm/slub.c
index 4ea7f1a..4aad32d 100644
--- a/mm/slub.c
+++ b/mm/slub.c
@@ -1884,7 +1884,8 @@
deactivate_slab(s, c);
c->page = NULL;
c->node = NUMA_NO_NODE;
- goto unlock_out;
+ local_irq_restore(flags);
+ return object;
}
/*
diff --git a/mm/swap.c b/mm/swap.c
index 5602f1a..3a442f1 100644
--- a/mm/swap.c
+++ b/mm/swap.c
@@ -272,14 +272,10 @@
memcg_reclaim_stat->recent_rotated[file]++;
}
-/*
- * FIXME: speed this up?
- */
-void activate_page(struct page *page)
+static void __activate_page(struct page *page, void *arg)
{
struct zone *zone = page_zone(page);
- spin_lock_irq(&zone->lru_lock);
if (PageLRU(page) && !PageActive(page) && !PageUnevictable(page)) {
int file = page_is_file_cache(page);
int lru = page_lru_base_type(page);
@@ -292,8 +288,45 @@
update_page_reclaim_stat(zone, page, file, 1);
}
+}
+
+#ifdef CONFIG_SMP
+static DEFINE_PER_CPU(struct pagevec, activate_page_pvecs);
+
+static void activate_page_drain(int cpu)
+{
+ struct pagevec *pvec = &per_cpu(activate_page_pvecs, cpu);
+
+ if (pagevec_count(pvec))
+ pagevec_lru_move_fn(pvec, __activate_page, NULL);
+}
+
+void activate_page(struct page *page)
+{
+ if (PageLRU(page) && !PageActive(page) && !PageUnevictable(page)) {
+ struct pagevec *pvec = &get_cpu_var(activate_page_pvecs);
+
+ page_cache_get(page);
+ if (!pagevec_add(pvec, page))
+ pagevec_lru_move_fn(pvec, __activate_page, NULL);
+ put_cpu_var(activate_page_pvecs);
+ }
+}
+
+#else
+static inline void activate_page_drain(int cpu)
+{
+}
+
+void activate_page(struct page *page)
+{
+ struct zone *zone = page_zone(page);
+
+ spin_lock_irq(&zone->lru_lock);
+ __activate_page(page, NULL);
spin_unlock_irq(&zone->lru_lock);
}
+#endif
/*
* Mark a page as having seen activity.
@@ -464,6 +497,8 @@
pvec = &per_cpu(lru_deactivate_pvecs, cpu);
if (pagevec_count(pvec))
pagevec_lru_move_fn(pvec, lru_deactivate_fn, NULL);
+
+ activate_page_drain(cpu);
}
/**
@@ -476,6 +511,13 @@
*/
void deactivate_page(struct page *page)
{
+ /*
+ * In a workload with many unevictable page such as mprotect, unevictable
+ * page deactivation for accelerating reclaim is pointless.
+ */
+ if (PageUnevictable(page))
+ return;
+
if (likely(get_page_unless_zero(page))) {
struct pagevec *pvec = &get_cpu_var(lru_deactivate_pvecs);
diff --git a/mm/swapfile.c b/mm/swapfile.c
index 8c6b3ce..d537d29 100644
--- a/mm/swapfile.c
+++ b/mm/swapfile.c
@@ -31,6 +31,7 @@
#include <linux/syscalls.h>
#include <linux/memcontrol.h>
#include <linux/poll.h>
+#include <linux/oom.h>
#include <asm/pgtable.h>
#include <asm/tlbflush.h>
@@ -1555,6 +1556,7 @@
struct address_space *mapping;
struct inode *inode;
char *pathname;
+ int oom_score_adj;
int i, type, prev;
int err;
@@ -1613,9 +1615,9 @@
p->flags &= ~SWP_WRITEOK;
spin_unlock(&swap_lock);
- current->flags |= PF_OOM_ORIGIN;
+ oom_score_adj = test_set_oom_score_adj(OOM_SCORE_ADJ_MAX);
err = try_to_unuse(type);
- current->flags &= ~PF_OOM_ORIGIN;
+ test_set_oom_score_adj(oom_score_adj);
if (err) {
/*
diff --git a/mm/util.c b/mm/util.c
index e7b103a..88ea1bd 100644
--- a/mm/util.c
+++ b/mm/util.c
@@ -6,6 +6,8 @@
#include <linux/sched.h>
#include <asm/uaccess.h>
+#include "internal.h"
+
#define CREATE_TRACE_POINTS
#include <trace/events/kmem.h>
@@ -215,6 +217,28 @@
}
EXPORT_SYMBOL(strndup_user);
+void __vma_link_list(struct mm_struct *mm, struct vm_area_struct *vma,
+ struct vm_area_struct *prev, struct rb_node *rb_parent)
+{
+ struct vm_area_struct *next;
+
+ vma->vm_prev = prev;
+ if (prev) {
+ next = prev->vm_next;
+ prev->vm_next = vma;
+ } else {
+ mm->mmap = vma;
+ if (rb_parent)
+ next = rb_entry(rb_parent,
+ struct vm_area_struct, vm_rb);
+ else
+ next = NULL;
+ }
+ vma->vm_next = next;
+ if (next)
+ next->vm_prev = vma;
+}
+
#if defined(CONFIG_MMU) && !defined(HAVE_ARCH_PICK_MMAP_LAYOUT)
void arch_pick_mmap_layout(struct mm_struct *mm)
{
diff --git a/mm/vmalloc.c b/mm/vmalloc.c
index 5d60302..b5ccf31 100644
--- a/mm/vmalloc.c
+++ b/mm/vmalloc.c
@@ -375,7 +375,7 @@
/* find starting point for our search */
if (free_vmap_cache) {
first = rb_entry(free_vmap_cache, struct vmap_area, rb_node);
- addr = ALIGN(first->va_end + PAGE_SIZE, align);
+ addr = ALIGN(first->va_end, align);
if (addr < vstart)
goto nocache;
if (addr + size - 1 < addr)
@@ -406,10 +406,10 @@
}
/* from the starting point, walk areas until a suitable hole is found */
- while (addr + size >= first->va_start && addr + size <= vend) {
+ while (addr + size > first->va_start && addr + size <= vend) {
if (addr + cached_hole_size < first->va_start)
cached_hole_size = first->va_start - addr;
- addr = ALIGN(first->va_end + PAGE_SIZE, align);
+ addr = ALIGN(first->va_end, align);
if (addr + size - 1 < addr)
goto overflow;
@@ -1534,6 +1534,7 @@
static void *__vmalloc_area_node(struct vm_struct *area, gfp_t gfp_mask,
pgprot_t prot, int node, void *caller)
{
+ const int order = 0;
struct page **pages;
unsigned int nr_pages, array_size, i;
gfp_t nested_gfp = (gfp_mask & GFP_RECLAIM_MASK) | __GFP_ZERO;
@@ -1560,11 +1561,12 @@
for (i = 0; i < area->nr_pages; i++) {
struct page *page;
+ gfp_t tmp_mask = gfp_mask | __GFP_NOWARN;
if (node < 0)
- page = alloc_page(gfp_mask);
+ page = alloc_page(tmp_mask);
else
- page = alloc_pages_node(node, gfp_mask, 0);
+ page = alloc_pages_node(node, tmp_mask, order);
if (unlikely(!page)) {
/* Successfully allocated i pages, free them in __vunmap() */
@@ -1579,6 +1581,9 @@
return area->addr;
fail:
+ warn_alloc_failed(gfp_mask, order, "vmalloc: allocation failure, "
+ "allocated %ld of %ld bytes\n",
+ (area->nr_pages*PAGE_SIZE), area->size);
vfree(area->addr);
return NULL;
}
diff --git a/mm/vmscan.c b/mm/vmscan.c
index c917720..7e01161 100644
--- a/mm/vmscan.c
+++ b/mm/vmscan.c
@@ -202,6 +202,14 @@
}
EXPORT_SYMBOL(unregister_shrinker);
+static inline int do_shrinker_shrink(struct shrinker *shrinker,
+ struct shrink_control *sc,
+ unsigned long nr_to_scan)
+{
+ sc->nr_to_scan = nr_to_scan;
+ return (*shrinker->shrink)(shrinker, sc);
+}
+
#define SHRINK_BATCH 128
/*
* Call the shrink functions to age shrinkable caches
@@ -222,25 +230,29 @@
*
* Returns the number of slab objects which we shrunk.
*/
-unsigned long shrink_slab(unsigned long scanned, gfp_t gfp_mask,
- unsigned long lru_pages)
+unsigned long shrink_slab(struct shrink_control *shrink,
+ unsigned long nr_pages_scanned,
+ unsigned long lru_pages)
{
struct shrinker *shrinker;
unsigned long ret = 0;
- if (scanned == 0)
- scanned = SWAP_CLUSTER_MAX;
+ if (nr_pages_scanned == 0)
+ nr_pages_scanned = SWAP_CLUSTER_MAX;
- if (!down_read_trylock(&shrinker_rwsem))
- return 1; /* Assume we'll be able to shrink next time */
+ if (!down_read_trylock(&shrinker_rwsem)) {
+ /* Assume we'll be able to shrink next time */
+ ret = 1;
+ goto out;
+ }
list_for_each_entry(shrinker, &shrinker_list, list) {
unsigned long long delta;
unsigned long total_scan;
unsigned long max_pass;
- max_pass = (*shrinker->shrink)(shrinker, 0, gfp_mask);
- delta = (4 * scanned) / shrinker->seeks;
+ max_pass = do_shrinker_shrink(shrinker, shrink, 0);
+ delta = (4 * nr_pages_scanned) / shrinker->seeks;
delta *= max_pass;
do_div(delta, lru_pages + 1);
shrinker->nr += delta;
@@ -267,9 +279,9 @@
int shrink_ret;
int nr_before;
- nr_before = (*shrinker->shrink)(shrinker, 0, gfp_mask);
- shrink_ret = (*shrinker->shrink)(shrinker, this_scan,
- gfp_mask);
+ nr_before = do_shrinker_shrink(shrinker, shrink, 0);
+ shrink_ret = do_shrinker_shrink(shrinker, shrink,
+ this_scan);
if (shrink_ret == -1)
break;
if (shrink_ret < nr_before)
@@ -283,6 +295,8 @@
shrinker->nr += total_scan;
}
up_read(&shrinker_rwsem);
+out:
+ cond_resched();
return ret;
}
@@ -1202,13 +1216,16 @@
{
int ret = -EBUSY;
+ VM_BUG_ON(!page_count(page));
+
if (PageLRU(page)) {
struct zone *zone = page_zone(page);
spin_lock_irq(&zone->lru_lock);
- if (PageLRU(page) && get_page_unless_zero(page)) {
+ if (PageLRU(page)) {
int lru = page_lru(page);
ret = 0;
+ get_page(page);
ClearPageLRU(page);
del_page_from_lru_list(zone, page, lru);
@@ -2027,7 +2044,8 @@
* else, the number of pages reclaimed
*/
static unsigned long do_try_to_free_pages(struct zonelist *zonelist,
- struct scan_control *sc)
+ struct scan_control *sc,
+ struct shrink_control *shrink)
{
int priority;
unsigned long total_scanned = 0;
@@ -2061,7 +2079,7 @@
lru_pages += zone_reclaimable_pages(zone);
}
- shrink_slab(sc->nr_scanned, sc->gfp_mask, lru_pages);
+ shrink_slab(shrink, sc->nr_scanned, lru_pages);
if (reclaim_state) {
sc->nr_reclaimed += reclaim_state->reclaimed_slab;
reclaim_state->reclaimed_slab = 0;
@@ -2133,12 +2151,15 @@
.mem_cgroup = NULL,
.nodemask = nodemask,
};
+ struct shrink_control shrink = {
+ .gfp_mask = sc.gfp_mask,
+ };
trace_mm_vmscan_direct_reclaim_begin(order,
sc.may_writepage,
gfp_mask);
- nr_reclaimed = do_try_to_free_pages(zonelist, &sc);
+ nr_reclaimed = do_try_to_free_pages(zonelist, &sc, &shrink);
trace_mm_vmscan_direct_reclaim_end(nr_reclaimed);
@@ -2198,17 +2219,20 @@
.order = 0,
.mem_cgroup = mem_cont,
.nodemask = NULL, /* we don't care the placement */
+ .gfp_mask = (gfp_mask & GFP_RECLAIM_MASK) |
+ (GFP_HIGHUSER_MOVABLE & ~GFP_RECLAIM_MASK),
+ };
+ struct shrink_control shrink = {
+ .gfp_mask = sc.gfp_mask,
};
- sc.gfp_mask = (gfp_mask & GFP_RECLAIM_MASK) |
- (GFP_HIGHUSER_MOVABLE & ~GFP_RECLAIM_MASK);
zonelist = NODE_DATA(numa_node_id())->node_zonelists;
trace_mm_vmscan_memcg_reclaim_begin(0,
sc.may_writepage,
sc.gfp_mask);
- nr_reclaimed = do_try_to_free_pages(zonelist, &sc);
+ nr_reclaimed = do_try_to_free_pages(zonelist, &sc, &shrink);
trace_mm_vmscan_memcg_reclaim_end(nr_reclaimed);
@@ -2287,7 +2311,7 @@
* must be balanced
*/
if (order)
- return pgdat_balanced(pgdat, balanced, classzone_idx);
+ return !pgdat_balanced(pgdat, balanced, classzone_idx);
else
return !all_zones_ok;
}
@@ -2336,6 +2360,9 @@
.order = order,
.mem_cgroup = NULL,
};
+ struct shrink_control shrink = {
+ .gfp_mask = sc.gfp_mask,
+ };
loop_again:
total_scanned = 0;
sc.nr_reclaimed = 0;
@@ -2435,8 +2462,7 @@
end_zone, 0))
shrink_zone(priority, zone, &sc);
reclaim_state->reclaimed_slab = 0;
- nr_slab = shrink_slab(sc.nr_scanned, GFP_KERNEL,
- lru_pages);
+ nr_slab = shrink_slab(&shrink, sc.nr_scanned, lru_pages);
sc.nr_reclaimed += reclaim_state->reclaimed_slab;
total_scanned += sc.nr_scanned;
@@ -2788,7 +2814,10 @@
.swappiness = vm_swappiness,
.order = 0,
};
- struct zonelist * zonelist = node_zonelist(numa_node_id(), sc.gfp_mask);
+ struct shrink_control shrink = {
+ .gfp_mask = sc.gfp_mask,
+ };
+ struct zonelist *zonelist = node_zonelist(numa_node_id(), sc.gfp_mask);
struct task_struct *p = current;
unsigned long nr_reclaimed;
@@ -2797,7 +2826,7 @@
reclaim_state.reclaimed_slab = 0;
p->reclaim_state = &reclaim_state;
- nr_reclaimed = do_try_to_free_pages(zonelist, &sc);
+ nr_reclaimed = do_try_to_free_pages(zonelist, &sc, &shrink);
p->reclaim_state = NULL;
lockdep_clear_current_reclaim_state();
@@ -2972,6 +3001,9 @@
.swappiness = vm_swappiness,
.order = order,
};
+ struct shrink_control shrink = {
+ .gfp_mask = sc.gfp_mask,
+ };
unsigned long nr_slab_pages0, nr_slab_pages1;
cond_resched();
@@ -3013,7 +3045,7 @@
unsigned long lru_pages = zone_reclaimable_pages(zone);
/* No reclaimable slab or very low memory pressure */
- if (!shrink_slab(sc.nr_scanned, gfp_mask, lru_pages))
+ if (!shrink_slab(&shrink, sc.nr_scanned, lru_pages))
break;
/* Freed enough memory */
diff --git a/mm/vmstat.c b/mm/vmstat.c
index 897ea9e..20c18b7 100644
--- a/mm/vmstat.c
+++ b/mm/vmstat.c
@@ -157,7 +157,7 @@
/*
* Refresh the thresholds for each zone.
*/
-static void refresh_zone_stat_thresholds(void)
+void refresh_zone_stat_thresholds(void)
{
struct zone *zone;
int cpu;
@@ -659,6 +659,138 @@
}
#endif
+#if defined(CONFIG_PROC_FS) || defined(CONFIG_SYSFS)
+#ifdef CONFIG_ZONE_DMA
+#define TEXT_FOR_DMA(xx) xx "_dma",
+#else
+#define TEXT_FOR_DMA(xx)
+#endif
+
+#ifdef CONFIG_ZONE_DMA32
+#define TEXT_FOR_DMA32(xx) xx "_dma32",
+#else
+#define TEXT_FOR_DMA32(xx)
+#endif
+
+#ifdef CONFIG_HIGHMEM
+#define TEXT_FOR_HIGHMEM(xx) xx "_high",
+#else
+#define TEXT_FOR_HIGHMEM(xx)
+#endif
+
+#define TEXTS_FOR_ZONES(xx) TEXT_FOR_DMA(xx) TEXT_FOR_DMA32(xx) xx "_normal", \
+ TEXT_FOR_HIGHMEM(xx) xx "_movable",
+
+const char * const vmstat_text[] = {
+ /* Zoned VM counters */
+ "nr_free_pages",
+ "nr_inactive_anon",
+ "nr_active_anon",
+ "nr_inactive_file",
+ "nr_active_file",
+ "nr_unevictable",
+ "nr_mlock",
+ "nr_anon_pages",
+ "nr_mapped",
+ "nr_file_pages",
+ "nr_dirty",
+ "nr_writeback",
+ "nr_slab_reclaimable",
+ "nr_slab_unreclaimable",
+ "nr_page_table_pages",
+ "nr_kernel_stack",
+ "nr_unstable",
+ "nr_bounce",
+ "nr_vmscan_write",
+ "nr_writeback_temp",
+ "nr_isolated_anon",
+ "nr_isolated_file",
+ "nr_shmem",
+ "nr_dirtied",
+ "nr_written",
+
+#ifdef CONFIG_NUMA
+ "numa_hit",
+ "numa_miss",
+ "numa_foreign",
+ "numa_interleave",
+ "numa_local",
+ "numa_other",
+#endif
+ "nr_anon_transparent_hugepages",
+ "nr_dirty_threshold",
+ "nr_dirty_background_threshold",
+
+#ifdef CONFIG_VM_EVENT_COUNTERS
+ "pgpgin",
+ "pgpgout",
+ "pswpin",
+ "pswpout",
+
+ TEXTS_FOR_ZONES("pgalloc")
+
+ "pgfree",
+ "pgactivate",
+ "pgdeactivate",
+
+ "pgfault",
+ "pgmajfault",
+
+ TEXTS_FOR_ZONES("pgrefill")
+ TEXTS_FOR_ZONES("pgsteal")
+ TEXTS_FOR_ZONES("pgscan_kswapd")
+ TEXTS_FOR_ZONES("pgscan_direct")
+
+#ifdef CONFIG_NUMA
+ "zone_reclaim_failed",
+#endif
+ "pginodesteal",
+ "slabs_scanned",
+ "kswapd_steal",
+ "kswapd_inodesteal",
+ "kswapd_low_wmark_hit_quickly",
+ "kswapd_high_wmark_hit_quickly",
+ "kswapd_skip_congestion_wait",
+ "pageoutrun",
+ "allocstall",
+
+ "pgrotated",
+
+#ifdef CONFIG_COMPACTION
+ "compact_blocks_moved",
+ "compact_pages_moved",
+ "compact_pagemigrate_failed",
+ "compact_stall",
+ "compact_fail",
+ "compact_success",
+#endif
+
+#ifdef CONFIG_HUGETLB_PAGE
+ "htlb_buddy_alloc_success",
+ "htlb_buddy_alloc_fail",
+#endif
+ "unevictable_pgs_culled",
+ "unevictable_pgs_scanned",
+ "unevictable_pgs_rescued",
+ "unevictable_pgs_mlocked",
+ "unevictable_pgs_munlocked",
+ "unevictable_pgs_cleared",
+ "unevictable_pgs_stranded",
+ "unevictable_pgs_mlockfreed",
+
+#ifdef CONFIG_TRANSPARENT_HUGEPAGE
+ "thp_fault_alloc",
+ "thp_fault_fallback",
+ "thp_collapse_alloc",
+ "thp_collapse_alloc_failed",
+ "thp_split",
+#endif
+
+#endif /* CONFIG_VM_EVENTS_COUNTERS */
+};
+#endif /* CONFIG_PROC_FS || CONFIG_SYSFS */
+
+
#ifdef CONFIG_PROC_FS
static void frag_show_print(struct seq_file *m, pg_data_t *pgdat,
struct zone *zone)
@@ -831,135 +963,6 @@
.release = seq_release,
};
-#ifdef CONFIG_ZONE_DMA
-#define TEXT_FOR_DMA(xx) xx "_dma",
-#else
-#define TEXT_FOR_DMA(xx)
-#endif
-
-#ifdef CONFIG_ZONE_DMA32
-#define TEXT_FOR_DMA32(xx) xx "_dma32",
-#else
-#define TEXT_FOR_DMA32(xx)
-#endif
-
-#ifdef CONFIG_HIGHMEM
-#define TEXT_FOR_HIGHMEM(xx) xx "_high",
-#else
-#define TEXT_FOR_HIGHMEM(xx)
-#endif
-
-#define TEXTS_FOR_ZONES(xx) TEXT_FOR_DMA(xx) TEXT_FOR_DMA32(xx) xx "_normal", \
- TEXT_FOR_HIGHMEM(xx) xx "_movable",
-
-static const char * const vmstat_text[] = {
- /* Zoned VM counters */
- "nr_free_pages",
- "nr_inactive_anon",
- "nr_active_anon",
- "nr_inactive_file",
- "nr_active_file",
- "nr_unevictable",
- "nr_mlock",
- "nr_anon_pages",
- "nr_mapped",
- "nr_file_pages",
- "nr_dirty",
- "nr_writeback",
- "nr_slab_reclaimable",
- "nr_slab_unreclaimable",
- "nr_page_table_pages",
- "nr_kernel_stack",
- "nr_unstable",
- "nr_bounce",
- "nr_vmscan_write",
- "nr_writeback_temp",
- "nr_isolated_anon",
- "nr_isolated_file",
- "nr_shmem",
- "nr_dirtied",
- "nr_written",
-
-#ifdef CONFIG_NUMA
- "numa_hit",
- "numa_miss",
- "numa_foreign",
- "numa_interleave",
- "numa_local",
- "numa_other",
-#endif
- "nr_anon_transparent_hugepages",
- "nr_dirty_threshold",
- "nr_dirty_background_threshold",
-
-#ifdef CONFIG_VM_EVENT_COUNTERS
- "pgpgin",
- "pgpgout",
- "pswpin",
- "pswpout",
-
- TEXTS_FOR_ZONES("pgalloc")
-
- "pgfree",
- "pgactivate",
- "pgdeactivate",
-
- "pgfault",
- "pgmajfault",
-
- TEXTS_FOR_ZONES("pgrefill")
- TEXTS_FOR_ZONES("pgsteal")
- TEXTS_FOR_ZONES("pgscan_kswapd")
- TEXTS_FOR_ZONES("pgscan_direct")
-
-#ifdef CONFIG_NUMA
- "zone_reclaim_failed",
-#endif
- "pginodesteal",
- "slabs_scanned",
- "kswapd_steal",
- "kswapd_inodesteal",
- "kswapd_low_wmark_hit_quickly",
- "kswapd_high_wmark_hit_quickly",
- "kswapd_skip_congestion_wait",
- "pageoutrun",
- "allocstall",
-
- "pgrotated",
-
-#ifdef CONFIG_COMPACTION
- "compact_blocks_moved",
- "compact_pages_moved",
- "compact_pagemigrate_failed",
- "compact_stall",
- "compact_fail",
- "compact_success",
-#endif
-
-#ifdef CONFIG_HUGETLB_PAGE
- "htlb_buddy_alloc_success",
- "htlb_buddy_alloc_fail",
-#endif
- "unevictable_pgs_culled",
- "unevictable_pgs_scanned",
- "unevictable_pgs_rescued",
- "unevictable_pgs_mlocked",
- "unevictable_pgs_munlocked",
- "unevictable_pgs_cleared",
- "unevictable_pgs_stranded",
- "unevictable_pgs_mlockfreed",
-
-#ifdef CONFIG_TRANSPARENT_HUGEPAGE
- "thp_fault_alloc",
- "thp_fault_fallback",
- "thp_collapse_alloc",
- "thp_collapse_alloc_failed",
- "thp_split",
-#endif
-
-#endif /* CONFIG_VM_EVENTS_COUNTERS */
-};
-
static void zoneinfo_show_print(struct seq_file *m, pg_data_t *pgdat,
struct zone *zone)
{
@@ -1198,7 +1201,6 @@
#ifdef CONFIG_SMP
int cpu;
- refresh_zone_stat_thresholds();
register_cpu_notifier(&vmstat_notifier);
for_each_online_cpu(cpu)
diff --git a/net/9p/Kconfig b/net/9p/Kconfig
index 7ed75c7..d9ea09b 100644
--- a/net/9p/Kconfig
+++ b/net/9p/Kconfig
@@ -3,8 +3,8 @@
#
menuconfig NET_9P
- depends on NET && EXPERIMENTAL
- tristate "Plan 9 Resource Sharing Support (9P2000) (Experimental)"
+ depends on NET
+ tristate "Plan 9 Resource Sharing Support (9P2000)"
help
If you say Y here, you will get experimental support for
Plan 9 resource sharing via the 9P2000 protocol.
@@ -16,8 +16,8 @@
if NET_9P
config NET_9P_VIRTIO
- depends on EXPERIMENTAL && VIRTIO
- tristate "9P Virtio Transport (Experimental)"
+ depends on VIRTIO
+ tristate "9P Virtio Transport"
help
This builds support for a transports between
guest partitions and a host partition.
diff --git a/net/9p/client.c b/net/9p/client.c
index ceab943..9e3b0e6 100644
--- a/net/9p/client.c
+++ b/net/9p/client.c
@@ -92,9 +92,6 @@
return version;
}
-static struct p9_req_t *
-p9_client_rpc(struct p9_client *c, int8_t type, const char *fmt, ...);
-
/**
* parse_options - parse mount options into client structure
* @opts: options string passed from mount
@@ -307,12 +304,13 @@
c->tagpool = p9_idpool_create();
if (IS_ERR(c->tagpool)) {
err = PTR_ERR(c->tagpool);
- c->tagpool = NULL;
goto error;
}
-
- p9_idpool_get(c->tagpool); /* reserve tag 0 */
-
+ err = p9_idpool_get(c->tagpool); /* reserve tag 0 */
+ if (err < 0) {
+ p9_idpool_destroy(c->tagpool);
+ goto error;
+ }
c->max_tag = 0;
error:
return err;
@@ -518,12 +516,15 @@
return err;
}
+static struct p9_req_t *
+p9_client_rpc(struct p9_client *c, int8_t type, const char *fmt, ...);
+
/**
* p9_client_flush - flush (cancel) a request
* @c: client state
* @oldreq: request to cancel
*
- * This sents a flush for a particular requests and links
+ * This sents a flush for a particular request and links
* the flush request to the original request. The current
* code only supports a single flush request although the protocol
* allows for multiple flush requests to be sent for a single request.
@@ -789,11 +790,13 @@
spin_lock_init(&clnt->lock);
INIT_LIST_HEAD(&clnt->fidlist);
- p9_tag_init(clnt);
+ err = p9_tag_init(clnt);
+ if (err < 0)
+ goto free_client;
err = parse_opts(options, clnt);
if (err < 0)
- goto free_client;
+ goto destroy_tagpool;
if (!clnt->trans_mod)
clnt->trans_mod = v9fs_get_default_trans();
@@ -802,13 +805,12 @@
err = -EPROTONOSUPPORT;
P9_DPRINTK(P9_DEBUG_ERROR,
"No transport defined or default transport\n");
- goto free_client;
+ goto destroy_tagpool;
}
clnt->fidpool = p9_idpool_create();
if (IS_ERR(clnt->fidpool)) {
err = PTR_ERR(clnt->fidpool);
- clnt->fidpool = NULL;
goto put_trans;
}
@@ -834,6 +836,8 @@
p9_idpool_destroy(clnt->fidpool);
put_trans:
v9fs_put_trans(clnt->trans_mod);
+destroy_tagpool:
+ p9_idpool_destroy(clnt->tagpool);
free_client:
kfree(clnt);
return ERR_PTR(err);
@@ -1298,7 +1302,7 @@
if (count < rsize)
rsize = count;
- /* Don't bother zerocopy form small IO (< 1024) */
+ /* Don't bother zerocopy for small IO (< 1024) */
if (((clnt->trans_mod->pref & P9_TRANS_PREF_PAYLOAD_MASK) ==
P9_TRANS_PREF_PAYLOAD_SEP) && (rsize > 1024)) {
req = p9_client_rpc(clnt, P9_TREAD, "dqE", fid->fid, offset,
diff --git a/net/9p/mod.c b/net/9p/mod.c
index cf8a412..72c3982 100644
--- a/net/9p/mod.c
+++ b/net/9p/mod.c
@@ -139,7 +139,7 @@
}
/**
- * v9fs_init - Initialize module
+ * init_p9 - Initialize module
*
*/
static int __init init_p9(void)
@@ -154,7 +154,7 @@
}
/**
- * v9fs_init - shutdown module
+ * exit_p9 - shutdown module
*
*/
diff --git a/net/9p/trans_fd.c b/net/9p/trans_fd.c
index 4a90843..fdfdb57 100644
--- a/net/9p/trans_fd.c
+++ b/net/9p/trans_fd.c
@@ -916,8 +916,8 @@
sin_server.sin_family = AF_INET;
sin_server.sin_addr.s_addr = in_aton(addr);
sin_server.sin_port = htons(opts.port);
- err = sock_create_kern(PF_INET, SOCK_STREAM, IPPROTO_TCP, &csocket);
-
+ err = __sock_create(read_pnet(¤t->nsproxy->net_ns), PF_INET,
+ SOCK_STREAM, IPPROTO_TCP, &csocket, 1);
if (err) {
P9_EPRINTK(KERN_ERR, "p9_trans_tcp: problem creating socket\n");
return err;
@@ -954,7 +954,8 @@
sun_server.sun_family = PF_UNIX;
strcpy(sun_server.sun_path, addr);
- err = sock_create_kern(PF_UNIX, SOCK_STREAM, 0, &csocket);
+ err = __sock_create(read_pnet(¤t->nsproxy->net_ns), PF_UNIX,
+ SOCK_STREAM, 0, &csocket, 1);
if (err < 0) {
P9_EPRINTK(KERN_ERR, "p9_trans_unix: problem creating socket\n");
return err;
diff --git a/net/9p/util.c b/net/9p/util.c
index da6af81..9c1c934 100644
--- a/net/9p/util.c
+++ b/net/9p/util.c
@@ -93,7 +93,7 @@
retry:
if (idr_pre_get(&p->pool, GFP_NOFS) == 0)
- return 0;
+ return -1;
spin_lock_irqsave(&p->lock, flags);
diff --git a/net/ceph/messenger.c b/net/ceph/messenger.c
index e15a82c..78b55f4 100644
--- a/net/ceph/messenger.c
+++ b/net/ceph/messenger.c
@@ -76,7 +76,8 @@
break;
default:
- sprintf(s, "(unknown sockaddr family %d)", (int)ss->ss_family);
+ snprintf(s, MAX_ADDR_STR_LEN, "(unknown sockaddr family %d)",
+ (int)ss->ss_family);
}
return s;
@@ -598,7 +599,7 @@
* Connection negotiation.
*/
-static void prepare_connect_authorizer(struct ceph_connection *con)
+static int prepare_connect_authorizer(struct ceph_connection *con)
{
void *auth_buf;
int auth_len = 0;
@@ -612,13 +613,20 @@
con->auth_retry);
mutex_lock(&con->mutex);
+ if (test_bit(CLOSED, &con->state) ||
+ test_bit(OPENING, &con->state))
+ return -EAGAIN;
+
con->out_connect.authorizer_protocol = cpu_to_le32(auth_protocol);
con->out_connect.authorizer_len = cpu_to_le32(auth_len);
- con->out_kvec[con->out_kvec_left].iov_base = auth_buf;
- con->out_kvec[con->out_kvec_left].iov_len = auth_len;
- con->out_kvec_left++;
- con->out_kvec_bytes += auth_len;
+ if (auth_len) {
+ con->out_kvec[con->out_kvec_left].iov_base = auth_buf;
+ con->out_kvec[con->out_kvec_left].iov_len = auth_len;
+ con->out_kvec_left++;
+ con->out_kvec_bytes += auth_len;
+ }
+ return 0;
}
/*
@@ -640,9 +648,9 @@
set_bit(WRITE_PENDING, &con->state);
}
-static void prepare_write_connect(struct ceph_messenger *msgr,
- struct ceph_connection *con,
- int after_banner)
+static int prepare_write_connect(struct ceph_messenger *msgr,
+ struct ceph_connection *con,
+ int after_banner)
{
unsigned global_seq = get_global_seq(con->msgr, 0);
int proto;
@@ -683,7 +691,7 @@
con->out_more = 0;
set_bit(WRITE_PENDING, &con->state);
- prepare_connect_authorizer(con);
+ return prepare_connect_authorizer(con);
}
@@ -1065,8 +1073,10 @@
switch (ss->ss_family) {
case AF_INET:
((struct sockaddr_in *)ss)->sin_port = htons(p);
+ break;
case AF_INET6:
((struct sockaddr_in6 *)ss)->sin6_port = htons(p);
+ break;
}
}
@@ -1216,6 +1226,7 @@
u64 sup_feat = con->msgr->supported_features;
u64 req_feat = con->msgr->required_features;
u64 server_feat = le64_to_cpu(con->in_reply.features);
+ int ret;
dout("process_connect on %p tag %d\n", con, (int)con->in_tag);
@@ -1250,7 +1261,9 @@
return -1;
}
con->auth_retry = 1;
- prepare_write_connect(con->msgr, con, 0);
+ ret = prepare_write_connect(con->msgr, con, 0);
+ if (ret < 0)
+ return ret;
prepare_read_connect(con);
break;
@@ -1277,6 +1290,9 @@
if (con->ops->peer_reset)
con->ops->peer_reset(con);
mutex_lock(&con->mutex);
+ if (test_bit(CLOSED, &con->state) ||
+ test_bit(OPENING, &con->state))
+ return -EAGAIN;
break;
case CEPH_MSGR_TAG_RETRY_SESSION:
@@ -1341,7 +1357,9 @@
* to WAIT. This shouldn't happen if we are the
* client.
*/
- pr_err("process_connect peer connecting WAIT\n");
+ pr_err("process_connect got WAIT as client\n");
+ con->error_msg = "protocol error, got WAIT as client";
+ return -1;
default:
pr_err("connect protocol error, will retry\n");
@@ -1810,6 +1828,17 @@
more:
dout("try_read tag %d in_base_pos %d\n", (int)con->in_tag,
con->in_base_pos);
+
+ /*
+ * process_connect and process_message drop and re-take
+ * con->mutex. make sure we handle a racing close or reopen.
+ */
+ if (test_bit(CLOSED, &con->state) ||
+ test_bit(OPENING, &con->state)) {
+ ret = -EAGAIN;
+ goto out;
+ }
+
if (test_bit(CONNECTING, &con->state)) {
if (!test_bit(NEGOTIATING, &con->state)) {
dout("try_read connecting\n");
@@ -1938,8 +1967,10 @@
{
struct ceph_connection *con = container_of(work, struct ceph_connection,
work.work);
+ int ret;
mutex_lock(&con->mutex);
+restart:
if (test_and_clear_bit(BACKOFF, &con->state)) {
dout("con_work %p backing off\n", con);
if (queue_delayed_work(ceph_msgr_wq, &con->work,
@@ -1969,18 +2000,31 @@
con_close_socket(con);
}
- if (test_and_clear_bit(SOCK_CLOSED, &con->state) ||
- try_read(con) < 0 ||
- try_write(con) < 0) {
- mutex_unlock(&con->mutex);
- ceph_fault(con); /* error/fault path */
- goto done_unlocked;
- }
+ if (test_and_clear_bit(SOCK_CLOSED, &con->state))
+ goto fault;
+
+ ret = try_read(con);
+ if (ret == -EAGAIN)
+ goto restart;
+ if (ret < 0)
+ goto fault;
+
+ ret = try_write(con);
+ if (ret == -EAGAIN)
+ goto restart;
+ if (ret < 0)
+ goto fault;
done:
mutex_unlock(&con->mutex);
done_unlocked:
con->ops->put(con);
+ return;
+
+fault:
+ mutex_unlock(&con->mutex);
+ ceph_fault(con); /* error/fault path */
+ goto done_unlocked;
}
diff --git a/net/ceph/osd_client.c b/net/ceph/osd_client.c
index 6b5dda1..6ea2b89 100644
--- a/net/ceph/osd_client.c
+++ b/net/ceph/osd_client.c
@@ -124,7 +124,7 @@
ceph_calc_raw_layout(osdc, layout, vino.snap, off,
plen, &bno, req, op);
- sprintf(req->r_oid, "%llx.%08llx", vino.ino, bno);
+ snprintf(req->r_oid, sizeof(req->r_oid), "%llx.%08llx", vino.ino, bno);
req->r_oid_len = strlen(req->r_oid);
}
@@ -1421,6 +1421,15 @@
done:
downgrade_write(&osdc->map_sem);
ceph_monc_got_osdmap(&osdc->client->monc, osdc->osdmap->epoch);
+
+ /*
+ * subscribe to subsequent osdmap updates if full to ensure
+ * we find out when we are no longer full and stop returning
+ * ENOSPC.
+ */
+ if (ceph_osdmap_flag(osdc->osdmap, CEPH_OSDMAP_FULL))
+ ceph_monc_request_next_osdmap(&osdc->client->monc);
+
send_queued(osdc);
up_read(&osdc->map_sem);
wake_up_all(&osdc->client->auth_wq);
@@ -1677,8 +1686,14 @@
*/
if (req->r_sent == 0) {
rc = __map_request(osdc, req);
- if (rc < 0)
+ if (rc < 0) {
+ if (nofail) {
+ dout("osdc_start_request failed map, "
+ " will retry %lld\n", req->r_tid);
+ rc = 0;
+ }
goto out_unlock;
+ }
if (req->r_osd == NULL) {
dout("send_request %p no up osds in pg\n", req);
ceph_monc_request_next_osdmap(&osdc->client->monc);
diff --git a/net/ceph/osdmap.c b/net/ceph/osdmap.c
index 71603ac..e97c358 100644
--- a/net/ceph/osdmap.c
+++ b/net/ceph/osdmap.c
@@ -765,7 +765,7 @@
}
map->epoch++;
- map->modified = map->modified;
+ map->modified = modified;
if (newcrush) {
if (map->crush)
crush_destroy(map->crush);
@@ -830,15 +830,20 @@
map->osd_addr[osd] = addr;
}
- /* new_down */
+ /* new_state */
ceph_decode_32_safe(p, end, len, bad);
while (len--) {
u32 osd;
+ u8 xorstate;
ceph_decode_32_safe(p, end, osd, bad);
+ xorstate = **(u8 **)p;
(*p)++; /* clean flag */
- pr_info("osd%d down\n", osd);
+ if (xorstate == 0)
+ xorstate = CEPH_OSD_UP;
+ if (xorstate & CEPH_OSD_UP)
+ pr_info("osd%d down\n", osd);
if (osd < map->max_osd)
- map->osd_state[osd] &= ~CEPH_OSD_UP;
+ map->osd_state[osd] ^= xorstate;
}
/* new_weight */
diff --git a/net/dns_resolver/dns_key.c b/net/dns_resolver/dns_key.c
index cfa7a5e..fa000d2 100644
--- a/net/dns_resolver/dns_key.c
+++ b/net/dns_resolver/dns_key.c
@@ -212,10 +212,12 @@
int err = key->type_data.x[0];
seq_puts(m, key->description);
- if (err)
- seq_printf(m, ": %d", err);
- else
- seq_printf(m, ": %u", key->datalen);
+ if (key_is_instantiated(key)) {
+ if (err)
+ seq_printf(m, ": %d", err);
+ else
+ seq_printf(m, ": %u", key->datalen);
+ }
}
/*
diff --git a/net/sunrpc/auth.c b/net/sunrpc/auth.c
index 67e3127..cd6e4aa 100644
--- a/net/sunrpc/auth.c
+++ b/net/sunrpc/auth.c
@@ -326,10 +326,12 @@
* Run memory cache shrinker.
*/
static int
-rpcauth_cache_shrinker(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask)
+rpcauth_cache_shrinker(struct shrinker *shrink, struct shrink_control *sc)
{
LIST_HEAD(free);
int res;
+ int nr_to_scan = sc->nr_to_scan;
+ gfp_t gfp_mask = sc->gfp_mask;
if ((gfp_mask & GFP_KERNEL) != GFP_KERNEL)
return (nr_to_scan == 0) ? 0 : -1;
diff --git a/scripts/.gitignore b/scripts/.gitignore
index e2741d2..105b21f 100644
--- a/scripts/.gitignore
+++ b/scripts/.gitignore
@@ -8,3 +8,4 @@
unifdef
ihex2fw
recordmcount
+docproc
diff --git a/scripts/Kbuild.include b/scripts/Kbuild.include
index ed2773e..be39cd1 100644
--- a/scripts/Kbuild.include
+++ b/scripts/Kbuild.include
@@ -118,6 +118,11 @@
cc-option-align = $(subst -functions=0,,\
$(call cc-option,-falign-functions=0,-malign-functions=0))
+# cc-disable-warning
+# Usage: cflags-y += $(call cc-disable-warning,unused-but-set-variable)
+cc-disable-warning = $(call try-run,\
+ $(CC) $(KBUILD_CPPFLAGS) $(KBUILD_CFLAGS) -W$(strip $(1)) -c -xc /dev/null -o "$$TMP",-Wno-$(strip $(1)))
+
# cc-version
# Usage gcc-ver := $(call cc-version)
cc-version = $(shell $(CONFIG_SHELL) $(srctree)/scripts/gcc-version.sh $(CC))
@@ -141,6 +146,11 @@
ld-option = $(call try-run,\
$(CC) /dev/null -c -o "$$TMPO" ; $(LD) $(1) "$$TMPO" -o "$$TMP",$(1),$(2))
+# ar-option
+# Usage: KBUILD_ARFLAGS := $(call ar-option,D)
+# Important: no spaces around options
+ar-option = $(call try-run, $(AR) rc$(1) "$$TMP",$(1),$(2))
+
######
###
@@ -187,6 +197,8 @@
# User may override this check using make KBUILD_NOCMDDEP=1
arg-check = $(strip $(filter-out $(cmd_$(1)), $(cmd_$@)) \
$(filter-out $(cmd_$@), $(cmd_$(1))) )
+else
+arg-check = $(if $(strip $(cmd_$@)),,1)
endif
# >'< substitution is for echo to work,
diff --git a/scripts/Makefile b/scripts/Makefile
index fcea261..df7678f 100644
--- a/scripts/Makefile
+++ b/scripts/Makefile
@@ -6,6 +6,7 @@
# pnmttologo: Convert pnm files to logo files
# conmakehash: Create chartable
# conmakehash: Create arrays for initializing the kernel console tables
+# docproc: Used in Documentation/DocBook
hostprogs-$(CONFIG_KALLSYMS) += kallsyms
hostprogs-$(CONFIG_LOGO) += pnmtologo
@@ -16,12 +17,14 @@
always := $(hostprogs-y) $(hostprogs-m)
# The following hostprogs-y programs are only build on demand
-hostprogs-y += unifdef
+hostprogs-y += unifdef docproc
-# This target is used internally to avoid "is up to date" messages
+# These targets are used internally to avoid "is up to date" messages
PHONY += build_unifdef
build_unifdef: scripts/unifdef FORCE
@:
+build_docproc: scripts/docproc FORCE
+ @:
subdir-$(CONFIG_MODVERSIONS) += genksyms
subdir-y += mod
diff --git a/scripts/Makefile.asm-generic b/scripts/Makefile.asm-generic
new file mode 100644
index 0000000..490122c
--- /dev/null
+++ b/scripts/Makefile.asm-generic
@@ -0,0 +1,23 @@
+# include/asm-generic contains a lot of files that are used
+# verbatim by several architectures.
+#
+# This Makefile reads the file arch/$(SRCARCH)/include/asm/Kbuild
+# and for each file listed in this file with generic-y creates
+# a small wrapper file in $(obj) (arch/$(SRCARCH)/include/generated/asm)
+
+kbuild-file := $(srctree)/arch/$(SRCARCH)/include/asm/Kbuild
+-include $(kbuild-file)
+
+include scripts/Kbuild.include
+
+# Create output directory if not already present
+_dummy := $(shell [ -d $(obj) ] || mkdir -p $(obj))
+
+quiet_cmd_wrap = WRAP $@
+cmd_wrap = echo "\#include <asm-generic/$*.h>" >$@
+
+all: $(patsubst %, $(obj)/%, $(generic-y))
+
+$(obj)/%.h:
+ $(call cmd,wrap)
+
diff --git a/scripts/Makefile.build b/scripts/Makefile.build
index 6165622..a0fd502 100644
--- a/scripts/Makefile.build
+++ b/scripts/Makefile.build
@@ -51,36 +51,52 @@
endif
#
-# make W=1 settings
+# make W=... settings
#
-# $(call cc-option... ) handles gcc -W.. options which
+# W=1 - warnings that may be relevant and does not occur too often
+# W=2 - warnings that occur quite often but may still be relevant
+# W=3 - the more obscure warnings, can most likely be ignored
+#
+# $(call cc-option, -W...) handles gcc -W.. options which
# are not supported by all versions of the compiler
ifdef KBUILD_ENABLE_EXTRA_GCC_CHECKS
-KBUILD_EXTRA_WARNINGS := -Wextra
-KBUILD_EXTRA_WARNINGS += -Wunused -Wno-unused-parameter
-KBUILD_EXTRA_WARNINGS += -Waggregate-return
-KBUILD_EXTRA_WARNINGS += -Wbad-function-cast
-KBUILD_EXTRA_WARNINGS += -Wcast-qual
-KBUILD_EXTRA_WARNINGS += -Wcast-align
-KBUILD_EXTRA_WARNINGS += -Wconversion
-KBUILD_EXTRA_WARNINGS += -Wdisabled-optimization
-KBUILD_EXTRA_WARNINGS += -Wlogical-op
-KBUILD_EXTRA_WARNINGS += -Wmissing-declarations
-KBUILD_EXTRA_WARNINGS += -Wmissing-format-attribute
-KBUILD_EXTRA_WARNINGS += $(call cc-option, -Wmissing-include-dirs,)
-KBUILD_EXTRA_WARNINGS += -Wmissing-prototypes
-KBUILD_EXTRA_WARNINGS += -Wnested-externs
-KBUILD_EXTRA_WARNINGS += -Wold-style-definition
-KBUILD_EXTRA_WARNINGS += $(call cc-option, -Woverlength-strings,)
-KBUILD_EXTRA_WARNINGS += -Wpacked
-KBUILD_EXTRA_WARNINGS += -Wpacked-bitfield-compat
-KBUILD_EXTRA_WARNINGS += -Wpadded
-KBUILD_EXTRA_WARNINGS += -Wpointer-arith
-KBUILD_EXTRA_WARNINGS += -Wredundant-decls
-KBUILD_EXTRA_WARNINGS += -Wshadow
-KBUILD_EXTRA_WARNINGS += -Wswitch-default
-KBUILD_EXTRA_WARNINGS += $(call cc-option, -Wvla,)
-KBUILD_CFLAGS += $(KBUILD_EXTRA_WARNINGS)
+warning- := $(empty)
+
+warning-1 := -Wextra -Wunused -Wno-unused-parameter
+warning-1 += -Wmissing-declarations
+warning-1 += -Wmissing-format-attribute
+warning-1 += -Wmissing-prototypes
+warning-1 += -Wold-style-definition
+warning-1 += $(call cc-option, -Wmissing-include-dirs)
+warning-1 += $(call cc-option, -Wunused-but-set-variable)
+
+warning-2 := -Waggregate-return
+warning-2 += -Wcast-align
+warning-2 += -Wdisabled-optimization
+warning-2 += -Wnested-externs
+warning-2 += -Wshadow
+warning-2 += $(call cc-option, -Wlogical-op)
+
+warning-3 := -Wbad-function-cast
+warning-3 += -Wcast-qual
+warning-3 += -Wconversion
+warning-3 += -Wpacked
+warning-3 += -Wpadded
+warning-3 += -Wpointer-arith
+warning-3 += -Wredundant-decls
+warning-3 += -Wswitch-default
+warning-3 += $(call cc-option, -Wpacked-bitfield-compat)
+warning-3 += $(call cc-option, -Wvla)
+
+warning := $(warning-$(findstring 1, $(KBUILD_ENABLE_EXTRA_GCC_CHECKS)))
+warning += $(warning-$(findstring 2, $(KBUILD_ENABLE_EXTRA_GCC_CHECKS)))
+warning += $(warning-$(findstring 3, $(KBUILD_ENABLE_EXTRA_GCC_CHECKS)))
+
+ifeq ("$(strip $(warning))","")
+ $(error W=$(KBUILD_ENABLE_EXTRA_GCC_CHECKS) is unknown)
+endif
+
+KBUILD_CFLAGS += $(warning)
endif
include scripts/Makefile.lib
@@ -351,7 +367,7 @@
cmd_link_o_target = $(if $(strip $(obj-y)),\
$(LD) $(ld_flags) -r -o $@ $(filter $(obj-y), $^) \
$(cmd_secanalysis),\
- rm -f $@; $(AR) rcs $@)
+ rm -f $@; $(AR) rcs$(KBUILD_ARFLAGS) $@)
$(builtin-target): $(obj-y) FORCE
$(call if_changed,link_o_target)
@@ -377,7 +393,7 @@
#
ifdef lib-target
quiet_cmd_link_l_target = AR $@
-cmd_link_l_target = rm -f $@; $(AR) rcs $@ $(lib-y)
+cmd_link_l_target = rm -f $@; $(AR) rcs$(KBUILD_ARFLAGS) $@ $(lib-y)
$(lib-target): $(lib-y) FORCE
$(call if_changed,link_l_target)
diff --git a/scripts/Makefile.headersinst b/scripts/Makefile.headersinst
index f89cb87..a57f5bd 100644
--- a/scripts/Makefile.headersinst
+++ b/scripts/Makefile.headersinst
@@ -27,8 +27,13 @@
install-file := $(install)/.install
check-file := $(install)/.check
+# generic-y list all files an architecture uses from asm-generic
+# Use this to build a list of headers which require a wrapper
+wrapper-files := $(filter $(header-y), $(generic-y))
+
# all headers files for this dir
-all-files := $(header-y) $(objhdr-y)
+header-y := $(filter-out $(generic-y), $(header-y))
+all-files := $(header-y) $(objhdr-y) $(wrapper-files)
input-files := $(addprefix $(srctree)/$(obj)/,$(header-y)) \
$(addprefix $(objtree)/$(obj)/,$(objhdr-y))
output-files := $(addprefix $(install)/, $(all-files))
@@ -47,6 +52,9 @@
cmd_install = \
$(PERL) $< $(srctree)/$(obj) $(install) $(SRCARCH) $(header-y); \
$(PERL) $< $(objtree)/$(obj) $(install) $(SRCARCH) $(objhdr-y); \
+ for F in $(wrapper-files); do \
+ echo "\#include <asm-generic/$$F>" > $(install)/$$F; \
+ done; \
touch $@
quiet_cmd_remove = REMOVE $(unwanted)
diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib
index 1c702ca..93b2b59 100644
--- a/scripts/Makefile.lib
+++ b/scripts/Makefile.lib
@@ -197,7 +197,7 @@
# ---------------------------------------------------------------------------
quiet_cmd_gzip = GZIP $@
-cmd_gzip = (cat $(filter-out FORCE,$^) | gzip -f -9 > $@) || \
+cmd_gzip = (cat $(filter-out FORCE,$^) | gzip -n -f -9 > $@) || \
(rm -f $@ ; false)
# DTC
diff --git a/scripts/basic/.gitignore b/scripts/basic/.gitignore
index bf8b199..a776371 100644
--- a/scripts/basic/.gitignore
+++ b/scripts/basic/.gitignore
@@ -1,3 +1 @@
-hash
fixdep
-docproc
diff --git a/scripts/basic/Makefile b/scripts/basic/Makefile
index 4c324a1..4fcef87 100644
--- a/scripts/basic/Makefile
+++ b/scripts/basic/Makefile
@@ -7,9 +7,8 @@
# .config is included by main Makefile.
# ---------------------------------------------------------------------------
# fixdep: Used to generate dependency information during build process
-# docproc: Used in Documentation/DocBook
-hostprogs-y := fixdep docproc
+hostprogs-y := fixdep
always := $(hostprogs-y)
# fixdep is needed to compile other host programs
diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl
index d867081..8657f99 100755
--- a/scripts/checkpatch.pl
+++ b/scripts/checkpatch.pl
@@ -210,10 +210,10 @@
our $logFunctions = qr{(?x:
printk|
- pr_(debug|dbg|vdbg|devel|info|warning|err|notice|alert|crit|emerg|cont)|
- (dev|netdev|netif)_(printk|dbg|vdbg|info|warn|err|notice|alert|crit|emerg|WARN)|
+ [a-z]+_(emerg|alert|crit|err|warning|warn|notice|info|debug|dbg|vdbg|devel|cont|WARN)|
WARN|
- panic
+ panic|
+ MODULE_[A-Z_]+
)};
our @typeList = (
@@ -1462,7 +1462,7 @@
#80 column limit
if ($line =~ /^\+/ && $prevrawline !~ /\/\*\*/ &&
$rawline !~ /^.\s*\*\s*\@$Ident\s/ &&
- !($line =~ /^\+\s*$logFunctions\s*\(\s*(?:(KERN_\S+\s*|[^"]*))?"[X\t]*"\s*(?:,|\)\s*;)\s*$/ ||
+ !($line =~ /^\+\s*$logFunctions\s*\(\s*(?:(KERN_\S+\s*|[^"]*))?"[X\t]*"\s*(?:|,|\)\s*;)\s*$/ ||
$line =~ /^\+\s*"[^"]*"\s*(?:\s*|,|\)\s*;)\s*$/) &&
$length > 80)
{
@@ -2748,6 +2748,11 @@
WARN("sizeof(& should be avoided\n" . $herecurr);
}
+# check for line continuations in quoted strings with odd counts of "
+ if ($rawline =~ /\\$/ && $rawline =~ tr/"/"/ % 2) {
+ WARN("Avoid line continuations in quoted strings\n" . $herecurr);
+ }
+
# check for new externs in .c files.
if ($realfile =~ /\.c$/ && defined $stat &&
$stat =~ /^.\s*(?:extern\s+)?$Type\s+($Ident)(\s*)\(/s)
diff --git a/scripts/checkversion.pl b/scripts/checkversion.pl
index b444e89..5e490a8 100755
--- a/scripts/checkversion.pl
+++ b/scripts/checkversion.pl
@@ -12,6 +12,7 @@
my $debugging;
foreach my $file (@ARGV) {
+ next if $file =~ "include/linux/version\.h";
# Open this file.
open( my $f, '<', $file )
or die "Can't open $file: $!\n";
diff --git a/scripts/basic/docproc.c b/scripts/docproc.c
similarity index 100%
rename from scripts/basic/docproc.c
rename to scripts/docproc.c
diff --git a/scripts/export_report.pl b/scripts/export_report.pl
index 04dce7c..8f79b70 100644
--- a/scripts/export_report.pl
+++ b/scripts/export_report.pl
@@ -25,11 +25,12 @@
sub print_depends_on {
my ($href) = @_;
print "\n";
- while (my ($mod, $list) = each %$href) {
+ for my $mod (sort keys %$href) {
+ my $list = $href->{$mod};
print "\t$mod:\n";
foreach my $sym (sort numerically @{$list}) {
my ($symbol, $no) = split /\s+/, $sym;
- printf("\t\t%-25s\t%-25d\n", $symbol, $no);
+ printf("\t\t%-25s\n", $symbol);
}
print "\n";
}
@@ -49,8 +50,14 @@
}
sub collectcfiles {
- my @file
- = `cat .tmp_versions/*.mod | grep '.*\.ko\$' | sed s/\.ko$/.mod.c/`;
+ my @file;
+ while (<.tmp_versions/*.mod>) {
+ open my $fh, '<', $_ or die "cannot open $_: $!\n";
+ push (@file,
+ grep s/\.ko/.mod.c/, # change the suffix
+ grep m/.+\.ko/, # find the .ko path
+ <$fh>); # lines in opened file
+ }
chomp @file;
return @file;
}
@@ -95,6 +102,8 @@
#
# collect the usage count of each symbol.
#
+my $modversion_warnings = 0;
+
foreach my $thismod (@allcfiles) {
my $module;
@@ -125,7 +134,8 @@
}
}
if ($state != 2) {
- print "WARNING:$thismod is not built with CONFIG_MODVERSION enabled\n";
+ warn "WARNING:$thismod is not built with CONFIG_MODVERSIONS enabled\n";
+ $modversion_warnings++;
}
close($module);
}
@@ -159,8 +169,12 @@
modules. Each module lists the modules, and the symbols from that module that
it uses. Each listed symbol reports the number of modules using it\n");
+print "\nNOTE: Got $modversion_warnings CONFIG_MODVERSIONS warnings\n\n"
+ if $modversion_warnings;
+
print "~"x80 , "\n";
-while (my ($thismod, $list) = each %MODULE) {
+for my $thismod (sort keys %MODULE) {
+ my $list = $MODULE{$thismod};
my %depends;
$thismod =~ s/\.mod\.c/.ko/;
print "\t\t\t$thismod\n";
diff --git a/scripts/gen_initramfs_list.sh b/scripts/gen_initramfs_list.sh
index e12b1a7..b482f16 100644
--- a/scripts/gen_initramfs_list.sh
+++ b/scripts/gen_initramfs_list.sh
@@ -1,4 +1,4 @@
-#!/bin/bash
+#!/bin/sh
# Copyright (C) Martin Schlemmer <azarah@nosferatu.za.org>
# Copyright (C) 2006 Sam Ravnborg <sam@ravnborg.org>
#
@@ -105,9 +105,9 @@
# for links, devices etc the format differs. See gen_init_cpio for details
parse() {
local location="$1"
- local name="${location/${srcdir}//}"
+ local name="/${location#${srcdir}}"
# change '//' into '/'
- name="${name//\/\///}"
+ name=$(echo "$name" | sed -e 's://*:/:g')
local mode="$2"
local uid="$3"
local gid="$4"
@@ -117,8 +117,8 @@
[ "$root_gid" = "squash" ] && gid=0 || [ "$gid" -eq "$root_gid" ] && gid=0
local str="${mode} ${uid} ${gid}"
- [ "${ftype}" == "invalid" ] && return 0
- [ "${location}" == "${srcdir}" ] && return 0
+ [ "${ftype}" = "invalid" ] && return 0
+ [ "${location}" = "${srcdir}" ] && return 0
case "${ftype}" in
"file")
@@ -192,7 +192,7 @@
if [ -f "$1" ]; then
${dep_list}header "$1"
is_cpio="$(echo "$1" | sed 's/^.*\.cpio\(\..*\)\?/cpio/')"
- if [ $2 -eq 0 -a ${is_cpio} == "cpio" ]; then
+ if [ $2 -eq 0 -a ${is_cpio} = "cpio" ]; then
cpio_file=$1
echo "$1" | grep -q '^.*\.cpio\..*' && is_cpio_compressed="compressed"
[ ! -z ${dep_list} ] && echo "$1"
@@ -204,7 +204,7 @@
else
echo "$1 \\"
cat "$1" | while read type dir file perm ; do
- if [ "$type" == "file" ]; then
+ if [ "$type" = "file" ]; then
echo "$file \\";
fi
done
@@ -226,7 +226,7 @@
output="/dev/stdout"
output_file=""
is_cpio_compressed=
-compr="gzip -9 -f"
+compr="gzip -n -9 -f"
arg="$1"
case "$arg" in
@@ -240,7 +240,7 @@
output_file="$1"
cpio_list="$(mktemp ${TMPDIR:-/tmp}/cpiolist.XXXXXX)"
output=${cpio_list}
- echo "$output_file" | grep -q "\.gz$" && compr="gzip -9 -f"
+ echo "$output_file" | grep -q "\.gz$" && compr="gzip -n -9 -f"
echo "$output_file" | grep -q "\.bz2$" && compr="bzip2 -9 -f"
echo "$output_file" | grep -q "\.lzma$" && compr="lzma -9 -f"
echo "$output_file" | grep -q "\.xz$" && \
@@ -287,8 +287,15 @@
# we are careful to delete tmp files
if [ ! -z ${output_file} ]; then
if [ -z ${cpio_file} ]; then
+ timestamp=
+ if test -n "$KBUILD_BUILD_TIMESTAMP"; then
+ timestamp="$(date -d"$KBUILD_BUILD_TIMESTAMP" +%s || :)"
+ if test -n "$timestamp"; then
+ timestamp="-t $timestamp"
+ fi
+ fi
cpio_tfile="$(mktemp ${TMPDIR:-/tmp}/cpiofile.XXXXXX)"
- usr/gen_init_cpio ${cpio_list} > ${cpio_tfile}
+ usr/gen_init_cpio $timestamp ${cpio_list} > ${cpio_tfile}
else
cpio_tfile=${cpio_file}
fi
diff --git a/scripts/kallsyms.c b/scripts/kallsyms.c
index 60dd3eb..487ac6f 100644
--- a/scripts/kallsyms.c
+++ b/scripts/kallsyms.c
@@ -500,6 +500,8 @@
/* find the token with the breates profit value */
best = find_best_token();
+ if (token_profit[best] == 0)
+ break;
/* place it in the "best" table */
best_table_len[i] = 2;
diff --git a/scripts/kconfig/Makefile b/scripts/kconfig/Makefile
index 368ae30..faa9a47 100644
--- a/scripts/kconfig/Makefile
+++ b/scripts/kconfig/Makefile
@@ -77,14 +77,15 @@
# The symlink is used to repair a deficiency in arch/um
update-po-config: $(obj)/kxgettext $(obj)/gconf.glade.h
$(Q)echo " GEN config"
- $(Q)xgettext --default-domain=linux \
- --add-comments --keyword=_ --keyword=N_ \
- --from-code=UTF-8 \
- --files-from=scripts/kconfig/POTFILES.in \
+ $(Q)xgettext --default-domain=linux \
+ --add-comments --keyword=_ --keyword=N_ \
+ --from-code=UTF-8 \
+ --files-from=$(srctree)/scripts/kconfig/POTFILES.in \
+ --directory=$(srctree) --directory=$(objtree) \
--output $(obj)/config.pot
$(Q)sed -i s/CHARSET/UTF-8/ $(obj)/config.pot
- $(Q)ln -fs Kconfig.i386 arch/um/Kconfig.arch
- $(Q)(for i in `ls arch/*/Kconfig`; \
+ $(Q)ln -fs Kconfig.x86 arch/um/Kconfig
+ $(Q)(for i in `ls $(srctree)/arch/*/Kconfig`; \
do \
echo " GEN $$i"; \
$(obj)/kxgettext $$i \
@@ -92,7 +93,7 @@
done )
$(Q)msguniq --sort-by-file --to-code=UTF-8 $(obj)/config.pot \
--output $(obj)/linux.pot
- $(Q)rm -f arch/um/Kconfig.arch
+ $(Q)rm -f $(srctree)/arch/um/Kconfig
$(Q)rm -f $(obj)/config.pot
PHONY += allnoconfig allyesconfig allmodconfig alldefconfig randconfig
@@ -168,8 +169,11 @@
mconf-objs := mconf.o zconf.tab.o $(lxdialog)
nconf-objs := nconf.o zconf.tab.o nconf.gui.o
kxgettext-objs := kxgettext.o zconf.tab.o
+qconf-cxxobjs := qconf.o
+qconf-objs := kconfig_load.o zconf.tab.o
+gconf-objs := gconf.o kconfig_load.o zconf.tab.o
-hostprogs-y := conf qconf gconf kxgettext
+hostprogs-y := conf
ifeq ($(MAKECMDGOALS),nconfig)
hostprogs-y += nconf
@@ -179,6 +183,10 @@
hostprogs-y += mconf
endif
+ifeq ($(MAKECMDGOALS),update-po-config)
+ hostprogs-y += kxgettext
+endif
+
ifeq ($(MAKECMDGOALS),xconfig)
qconf-target := 1
endif
@@ -188,16 +196,15 @@
ifeq ($(qconf-target),1)
-qconf-cxxobjs := qconf.o
-qconf-objs := kconfig_load.o zconf.tab.o
+ hostprogs-y += qconf
endif
ifeq ($(gconf-target),1)
-gconf-objs := gconf.o kconfig_load.o zconf.tab.o
+ hostprogs-y += gconf
endif
-clean-files := lkc_defs.h qconf.moc .tmp_qtcheck \
- .tmp_gtkcheck zconf.tab.c lex.zconf.c zconf.hash.c gconf.glade.h
+clean-files := lkc_defs.h qconf.moc .tmp_qtcheck .tmp_gtkcheck
+clean-files += zconf.tab.c lex.zconf.c zconf.hash.c gconf.glade.h
clean-files += mconf qconf gconf nconf
clean-files += config.pot linux.pot
@@ -321,11 +328,12 @@
$(KC_QT_MOC) -i $< -o $@
$(obj)/lkc_defs.h: $(src)/lkc_proto.h
- sed < $< > $@ 's/P(\([^,]*\),.*/#define \1 (\*\1_p)/'
+ $(Q)sed < $< > $@ 's/P(\([^,]*\),.*/#define \1 (\*\1_p)/'
# Extract gconf menu items for I18N support
$(obj)/gconf.glade.h: $(obj)/gconf.glade
- intltool-extract --type=gettext/glade $(obj)/gconf.glade
+ $(Q)intltool-extract --type=gettext/glade --srcdir=$(srctree) \
+ $(obj)/gconf.glade
###
# The following requires flex/bison/gperf
diff --git a/scripts/kconfig/confdata.c b/scripts/kconfig/confdata.c
index 61c35bf..2bafd9a 100644
--- a/scripts/kconfig/confdata.c
+++ b/scripts/kconfig/confdata.c
@@ -560,8 +560,6 @@
const char *basename;
const char *str;
char dirname[PATH_MAX+1], tmpname[PATH_MAX+1], newname[PATH_MAX+1];
- time_t now;
- int use_timestamp = 1;
char *env;
dirname[0] = 0;
@@ -598,19 +596,11 @@
if (!out)
return 1;
- time(&now);
- env = getenv("KCONFIG_NOTIMESTAMP");
- if (env && *env)
- use_timestamp = 0;
-
fprintf(out, _("#\n"
"# Automatically generated make config: don't edit\n"
"# %s\n"
- "%s%s"
"#\n"),
- rootmenu.prompt->text,
- use_timestamp ? "# " : "",
- use_timestamp ? ctime(&now) : "");
+ rootmenu.prompt->text);
if (!conf_get_changed())
sym_clear_all_valid();
@@ -784,7 +774,6 @@
const char *str;
const char *name;
FILE *out, *tristate, *out_h;
- time_t now;
int i;
sym_clear_all_valid();
@@ -811,22 +800,19 @@
return 1;
}
- time(&now);
fprintf(out, "#\n"
"# Automatically generated make config: don't edit\n"
"# %s\n"
- "# %s"
"#\n",
- rootmenu.prompt->text, ctime(&now));
+ rootmenu.prompt->text);
fprintf(tristate, "#\n"
"# Automatically generated - do not edit\n"
"\n");
fprintf(out_h, "/*\n"
" * Automatically generated C config: don't edit\n"
" * %s\n"
- " * %s"
" */\n",
- rootmenu.prompt->text, ctime(&now));
+ rootmenu.prompt->text);
for_all_symbols(i, sym) {
sym_calc_value(sym);
diff --git a/scripts/kconfig/expr.h b/scripts/kconfig/expr.h
index 3d238db..16bfae2 100644
--- a/scripts/kconfig/expr.h
+++ b/scripts/kconfig/expr.h
@@ -20,12 +20,8 @@
struct file *parent;
const char *name;
int lineno;
- int flags;
};
-#define FILE_BUSY 0x0001
-#define FILE_SCANNED 0x0002
-
typedef enum tristate {
no, mod, yes
} tristate;
diff --git a/scripts/kconfig/gconf.c b/scripts/kconfig/gconf.c
index 4558961..a11d5f7 100644
--- a/scripts/kconfig/gconf.c
+++ b/scripts/kconfig/gconf.c
@@ -253,7 +253,7 @@
gtk_tree_view_set_model(view, model1);
gtk_tree_view_set_headers_visible(view, TRUE);
- gtk_tree_view_set_rules_hint(view, FALSE);
+ gtk_tree_view_set_rules_hint(view, TRUE);
column = gtk_tree_view_column_new();
gtk_tree_view_append_column(view, column);
@@ -298,7 +298,7 @@
gtk_tree_view_set_model(view, model2);
gtk_tree_view_set_headers_visible(view, TRUE);
- gtk_tree_view_set_rules_hint(view, FALSE);
+ gtk_tree_view_set_rules_hint(view, TRUE);
column = gtk_tree_view_column_new();
gtk_tree_view_append_column(view, column);
@@ -756,7 +756,6 @@
void on_single_clicked(GtkButton * button, gpointer user_data)
{
view_mode = SINGLE_VIEW;
- gtk_paned_set_position(GTK_PANED(hpaned), 0);
gtk_widget_hide(tree1_w);
current = &rootmenu;
display_tree_part();
@@ -782,7 +781,6 @@
void on_full_clicked(GtkButton * button, gpointer user_data)
{
view_mode = FULL_VIEW;
- gtk_paned_set_position(GTK_PANED(hpaned), 0);
gtk_widget_hide(tree1_w);
if (tree2)
gtk_tree_store_clear(tree2);
@@ -1444,6 +1442,12 @@
if (((menu != &rootmenu) && !(menu->flags & MENU_ROOT))
|| (view_mode == FULL_VIEW)
|| (view_mode == SPLIT_VIEW))*/
+
+ /* Change paned position if the view is not in 'split mode' */
+ if (view_mode == SINGLE_VIEW || view_mode == FULL_VIEW) {
+ gtk_paned_set_position(GTK_PANED(hpaned), 0);
+ }
+
if (((view_mode == SINGLE_VIEW) && (menu->flags & MENU_ROOT))
|| (view_mode == FULL_VIEW)
|| (view_mode == SPLIT_VIEW)) {
diff --git a/scripts/kconfig/lex.zconf.c_shipped b/scripts/kconfig/lex.zconf.c_shipped
index 6eb0397..d918291 100644
--- a/scripts/kconfig/lex.zconf.c_shipped
+++ b/scripts/kconfig/lex.zconf.c_shipped
@@ -2363,11 +2363,11 @@
current_file = file_lookup(name);
current_file->lineno = 1;
- current_file->flags = FILE_BUSY;
}
void zconf_nextfile(const char *name)
{
+ struct file *iter;
struct file *file = file_lookup(name);
struct buffer *buf = malloc(sizeof(*buf));
memset(buf, 0, sizeof(*buf));
@@ -2383,18 +2383,25 @@
buf->parent = current_buf;
current_buf = buf;
- if (file->flags & FILE_BUSY) {
- printf("%s:%d: do not source '%s' from itself\n",
- zconf_curname(), zconf_lineno(), name);
- exit(1);
+ for (iter = current_file->parent; iter; iter = iter->parent ) {
+ if (!strcmp(current_file->name,iter->name) ) {
+ printf("%s:%d: recursive inclusion detected. "
+ "Inclusion path:\n current file : '%s'\n",
+ zconf_curname(), zconf_lineno(),
+ zconf_curname());
+ iter = current_file->parent;
+ while (iter && \
+ strcmp(iter->name,current_file->name)) {
+ printf(" included from: '%s:%d'\n",
+ iter->name, iter->lineno-1);
+ iter = iter->parent;
+ }
+ if (iter)
+ printf(" included from: '%s:%d'\n",
+ iter->name, iter->lineno+1);
+ exit(1);
+ }
}
- if (file->flags & FILE_SCANNED) {
- printf("%s:%d: file '%s' is already sourced from '%s'\n",
- zconf_curname(), zconf_lineno(), name,
- file->parent->name);
- exit(1);
- }
- file->flags |= FILE_BUSY;
file->lineno = 1;
file->parent = current_file;
current_file = file;
@@ -2404,8 +2411,6 @@
{
struct buffer *parent;
- current_file->flags |= FILE_SCANNED;
- current_file->flags &= ~FILE_BUSY;
current_file = current_file->parent;
parent = current_buf->parent;
diff --git a/scripts/kconfig/nconf.c b/scripts/kconfig/nconf.c
index db56377..488dd74 100644
--- a/scripts/kconfig/nconf.c
+++ b/scripts/kconfig/nconf.c
@@ -373,18 +373,18 @@
const int skip = 1;
for (i = 0; i < function_keys_num; i++) {
- wattrset(main_window, attributes[FUNCTION_HIGHLIGHT]);
+ (void) wattrset(main_window, attributes[FUNCTION_HIGHLIGHT]);
mvwprintw(main_window, LINES-3, offset,
"%s",
function_keys[i].key_str);
- wattrset(main_window, attributes[FUNCTION_TEXT]);
+ (void) wattrset(main_window, attributes[FUNCTION_TEXT]);
offset += strlen(function_keys[i].key_str);
mvwprintw(main_window, LINES-3,
offset, "%s",
function_keys[i].func);
offset += strlen(function_keys[i].func) + skip;
}
- wattrset(main_window, attributes[NORMAL]);
+ (void) wattrset(main_window, attributes[NORMAL]);
}
/* help */
@@ -953,16 +953,16 @@
current_instructions = instructions;
clear();
- wattrset(main_window, attributes[NORMAL]);
+ (void) wattrset(main_window, attributes[NORMAL]);
print_in_middle(stdscr, 1, 0, COLS,
menu_backtitle,
attributes[MAIN_HEADING]);
- wattrset(main_window, attributes[MAIN_MENU_BOX]);
+ (void) wattrset(main_window, attributes[MAIN_MENU_BOX]);
box(main_window, 0, 0);
- wattrset(main_window, attributes[MAIN_MENU_HEADING]);
+ (void) wattrset(main_window, attributes[MAIN_MENU_HEADING]);
mvwprintw(main_window, 0, 3, " %s ", prompt);
- wattrset(main_window, attributes[NORMAL]);
+ (void) wattrset(main_window, attributes[NORMAL]);
set_menu_items(curses_menu, curses_menu_items);
diff --git a/scripts/kconfig/qconf.cc b/scripts/kconfig/qconf.cc
index 06dd2e3..c2796b8 100644
--- a/scripts/kconfig/qconf.cc
+++ b/scripts/kconfig/qconf.cc
@@ -1489,8 +1489,7 @@
QString s = Q3FileDialog::getSaveFileName(conf_get_configname(), NULL, this);
if (s.isNull())
return;
- if (conf_write(QFile::encodeName(s)))
- QMessageBox::information(this, "qconf", _("Unable to save configuration!"));
+ saveConfig();
}
void ConfigMainWindow::searchConfig(void)
@@ -1643,7 +1642,7 @@
mb.setButtonText(QMessageBox::Cancel, _("Cancel Exit"));
switch (mb.exec()) {
case QMessageBox::Yes:
- conf_write(NULL);
+ saveConfig();
case QMessageBox::No:
e->accept();
break;
diff --git a/scripts/kconfig/zconf.l b/scripts/kconfig/zconf.l
index 3dbaec1..b22f884 100644
--- a/scripts/kconfig/zconf.l
+++ b/scripts/kconfig/zconf.l
@@ -294,11 +294,11 @@
current_file = file_lookup(name);
current_file->lineno = 1;
- current_file->flags = FILE_BUSY;
}
void zconf_nextfile(const char *name)
{
+ struct file *iter;
struct file *file = file_lookup(name);
struct buffer *buf = malloc(sizeof(*buf));
memset(buf, 0, sizeof(*buf));
@@ -314,18 +314,25 @@
buf->parent = current_buf;
current_buf = buf;
- if (file->flags & FILE_BUSY) {
- printf("%s:%d: do not source '%s' from itself\n",
- zconf_curname(), zconf_lineno(), name);
- exit(1);
+ for (iter = current_file->parent; iter; iter = iter->parent ) {
+ if (!strcmp(current_file->name,iter->name) ) {
+ printf("%s:%d: recursive inclusion detected. "
+ "Inclusion path:\n current file : '%s'\n",
+ zconf_curname(), zconf_lineno(),
+ zconf_curname());
+ iter = current_file->parent;
+ while (iter && \
+ strcmp(iter->name,current_file->name)) {
+ printf(" included from: '%s:%d'\n",
+ iter->name, iter->lineno-1);
+ iter = iter->parent;
+ }
+ if (iter)
+ printf(" included from: '%s:%d'\n",
+ iter->name, iter->lineno+1);
+ exit(1);
+ }
}
- if (file->flags & FILE_SCANNED) {
- printf("%s:%d: file '%s' is already sourced from '%s'\n",
- zconf_curname(), zconf_lineno(), name,
- file->parent->name);
- exit(1);
- }
- file->flags |= FILE_BUSY;
file->lineno = 1;
file->parent = current_file;
current_file = file;
@@ -335,8 +342,6 @@
{
struct buffer *parent;
- current_file->flags |= FILE_SCANNED;
- current_file->flags &= ~FILE_BUSY;
current_file = current_file->parent;
parent = current_buf->parent;
diff --git a/scripts/mkcompile_h b/scripts/mkcompile_h
index 50ad317..f221ddf 100755
--- a/scripts/mkcompile_h
+++ b/scripts/mkcompile_h
@@ -42,6 +42,16 @@
else
TIMESTAMP=$KBUILD_BUILD_TIMESTAMP
fi
+if test -z "$KBUILD_BUILD_USER"; then
+ LINUX_COMPILE_BY=$(whoami | sed 's/\\/\\\\/')
+else
+ LINUX_COMPILE_BY=$KBUILD_BUILD_USER
+fi
+if test -z "$KBUILD_BUILD_HOST"; then
+ LINUX_COMPILE_HOST=`hostname`
+else
+ LINUX_COMPILE_HOST=$KBUILD_BUILD_HOST
+fi
UTS_VERSION="#$VERSION"
CONFIG_FLAGS=""
@@ -63,20 +73,8 @@
echo \#define UTS_VERSION \"`echo $UTS_VERSION | $UTS_TRUNCATE`\"
- echo \#define LINUX_COMPILE_TIME \"`date +%T`\"
- echo \#define LINUX_COMPILE_BY \"`whoami`\"
- echo \#define LINUX_COMPILE_HOST \"`hostname | $UTS_TRUNCATE`\"
-
- domain=`dnsdomainname 2> /dev/null`
- if [ -z "$domain" ]; then
- domain=`domainname 2> /dev/null`
- fi
-
- if [ -n "$domain" ]; then
- echo \#define LINUX_COMPILE_DOMAIN \"`echo $domain | $UTS_TRUNCATE`\"
- else
- echo \#define LINUX_COMPILE_DOMAIN
- fi
+ echo \#define LINUX_COMPILE_BY \"`echo $LINUX_COMPILE_BY | $UTS_TRUNCATE`\"
+ echo \#define LINUX_COMPILE_HOST \"`echo $LINUX_COMPILE_HOST | $UTS_TRUNCATE`\"
echo \#define LINUX_COMPILER \"`$CC -v 2>&1 | tail -n 1`\"
) > .tmpcompile
@@ -91,8 +89,8 @@
# first line.
if [ -r $TARGET ] && \
- grep -v 'UTS_VERSION\|LINUX_COMPILE_TIME' $TARGET > .tmpver.1 && \
- grep -v 'UTS_VERSION\|LINUX_COMPILE_TIME' .tmpcompile > .tmpver.2 && \
+ grep -v 'UTS_VERSION' $TARGET > .tmpver.1 && \
+ grep -v 'UTS_VERSION' .tmpcompile > .tmpver.2 && \
cmp -s .tmpver.1 .tmpver.2; then
rm -f .tmpcompile
else
diff --git a/scripts/package/Makefile b/scripts/package/Makefile
index a834b93..006960e 100644
--- a/scripts/package/Makefile
+++ b/scripts/package/Makefile
@@ -26,9 +26,9 @@
else echo rpm; fi)
# Remove hyphens since they have special meaning in RPM filenames
-KERNELPATH := kernel-$(subst -,,$(KERNELRELEASE))
+KERNELPATH := kernel-$(subst -,_,$(KERNELRELEASE))
MKSPEC := $(srctree)/scripts/package/mkspec
-PREV := set -e; cd ..;
+PREV := set -e; cd -P ..;
# rpm-pkg
# ---------------------------------------------------------------------------
diff --git a/scripts/package/mkspec b/scripts/package/mkspec
index e1c1d5b..4bf17dd 100755
--- a/scripts/package/mkspec
+++ b/scripts/package/mkspec
@@ -22,7 +22,7 @@
fi
PROVIDES="$PROVIDES kernel-$KERNELRELEASE"
-__KERNELRELEASE=`echo $KERNELRELEASE | sed -e "s/-//g"`
+__KERNELRELEASE=`echo $KERNELRELEASE | sed -e "s/-/_/g"`
echo "Name: kernel"
echo "Summary: The Linux Kernel"
@@ -47,6 +47,18 @@
echo "%description"
echo "The Linux Kernel, the operating system core itself"
echo ""
+echo "%package headers"
+echo "Summary: Header files for the Linux kernel for use by glibc"
+echo "Group: Development/System"
+echo "Obsoletes: kernel-headers"
+echo "Provides: kernel-headers = %{version}"
+echo "%description headers"
+echo "Kernel-headers includes the C header files that specify the interface"
+echo "between the Linux kernel and userspace libraries and programs. The"
+echo "header files define structures and constants that are needed for"
+echo "building most standard programs and are also needed for rebuilding the"
+echo "glibc package."
+echo ""
if ! $PREBUILT; then
echo "%prep"
@@ -83,6 +95,7 @@
echo "%endif"
echo "%endif"
+echo 'make %{?_smp_mflags} INSTALL_HDR_PATH=$RPM_BUILD_ROOT/usr headers_install'
echo 'cp System.map $RPM_BUILD_ROOT'"/boot/System.map-$KERNELRELEASE"
echo 'cp .config $RPM_BUILD_ROOT'"/boot/config-$KERNELRELEASE"
@@ -105,3 +118,7 @@
echo "/lib/firmware"
echo "/boot/*"
echo ""
+echo "%files headers"
+echo '%defattr (-, root, root)'
+echo "/usr/include"
+echo ""
diff --git a/scripts/patch-kernel b/scripts/patch-kernel
index 46a59ca..20fb25c 100755
--- a/scripts/patch-kernel
+++ b/scripts/patch-kernel
@@ -250,7 +250,7 @@
do
CURRENTFULLVERSION="$VERSION.$PATCHLEVEL.$SUBLEVEL"
EXTRAVER=
- if [ $STOPFULLVERSION = $CURRENTFULLVERSION ]; then
+ if [ x$STOPFULLVERSION = x$CURRENTFULLVERSION ]; then
echo "Stopping at $CURRENTFULLVERSION base as requested."
break
fi
diff --git a/security/Kconfig b/security/Kconfig
index 95accd4..e0f08b5 100644
--- a/security/Kconfig
+++ b/security/Kconfig
@@ -167,6 +167,7 @@
config LSM_MMAP_MIN_ADDR
int "Low address space for LSM to protect from user allocation"
depends on SECURITY && SECURITY_SELINUX
+ default 32768 if ARM
default 65536
help
This is the portion of low virtual memory which should be protected
diff --git a/security/commoncap.c b/security/commoncap.c
index f20e984..a93b3b7 100644
--- a/security/commoncap.c
+++ b/security/commoncap.c
@@ -529,15 +529,10 @@
new->suid = new->fsuid = new->euid;
new->sgid = new->fsgid = new->egid;
- /* For init, we want to retain the capabilities set in the initial
- * task. Thus we skip the usual capability rules
- */
- if (!is_global_init(current)) {
- if (effective)
- new->cap_effective = new->cap_permitted;
- else
- cap_clear(new->cap_effective);
- }
+ if (effective)
+ new->cap_effective = new->cap_permitted;
+ else
+ cap_clear(new->cap_effective);
bprm->cap_effective = effective;
/*
diff --git a/security/keys/internal.h b/security/keys/internal.h
index 07a025f..f375152 100644
--- a/security/keys/internal.h
+++ b/security/keys/internal.h
@@ -109,11 +109,13 @@
const struct cred *cred,
struct key_type *type,
const void *description,
- key_match_func_t match);
+ key_match_func_t match,
+ bool no_state_check);
extern key_ref_t search_my_process_keyrings(struct key_type *type,
const void *description,
key_match_func_t match,
+ bool no_state_check,
const struct cred *cred);
extern key_ref_t search_process_keyrings(struct key_type *type,
const void *description,
diff --git a/security/keys/keyctl.c b/security/keys/keyctl.c
index 427fddc..eca5191 100644
--- a/security/keys/keyctl.c
+++ b/security/keys/keyctl.c
@@ -206,8 +206,14 @@
goto error5;
}
+ /* wait for the key to finish being constructed */
+ ret = wait_for_key_construction(key, 1);
+ if (ret < 0)
+ goto error6;
+
ret = key->serial;
+error6:
key_put(key);
error5:
key_type_put(ktype);
diff --git a/security/keys/keyring.c b/security/keys/keyring.c
index cdd2f3f..a06ffab 100644
--- a/security/keys/keyring.c
+++ b/security/keys/keyring.c
@@ -176,13 +176,15 @@
else
seq_puts(m, "[anon]");
- rcu_read_lock();
- klist = rcu_dereference(keyring->payload.subscriptions);
- if (klist)
- seq_printf(m, ": %u/%u", klist->nkeys, klist->maxkeys);
- else
- seq_puts(m, ": empty");
- rcu_read_unlock();
+ if (key_is_instantiated(keyring)) {
+ rcu_read_lock();
+ klist = rcu_dereference(keyring->payload.subscriptions);
+ if (klist)
+ seq_printf(m, ": %u/%u", klist->nkeys, klist->maxkeys);
+ else
+ seq_puts(m, ": empty");
+ rcu_read_unlock();
+ }
}
/*
@@ -271,6 +273,7 @@
* @type: The type of key to search for.
* @description: Parameter for @match.
* @match: Function to rule on whether or not a key is the one required.
+ * @no_state_check: Don't check if a matching key is bad
*
* Search the supplied keyring tree for a key that matches the criteria given.
* The root keyring and any linked keyrings must grant Search permission to the
@@ -303,7 +306,8 @@
const struct cred *cred,
struct key_type *type,
const void *description,
- key_match_func_t match)
+ key_match_func_t match,
+ bool no_state_check)
{
struct {
struct keyring_list *keylist;
@@ -345,6 +349,8 @@
kflags = keyring->flags;
if (keyring->type == type && match(keyring, description)) {
key = keyring;
+ if (no_state_check)
+ goto found;
/* check it isn't negative and hasn't expired or been
* revoked */
@@ -384,11 +390,13 @@
continue;
/* skip revoked keys and expired keys */
- if (kflags & (1 << KEY_FLAG_REVOKED))
- continue;
+ if (!no_state_check) {
+ if (kflags & (1 << KEY_FLAG_REVOKED))
+ continue;
- if (key->expiry && now.tv_sec >= key->expiry)
- continue;
+ if (key->expiry && now.tv_sec >= key->expiry)
+ continue;
+ }
/* keys that don't match */
if (!match(key, description))
@@ -399,6 +407,9 @@
cred, KEY_SEARCH) < 0)
continue;
+ if (no_state_check)
+ goto found;
+
/* we set a different error code if we pass a negative key */
if (kflags & (1 << KEY_FLAG_NEGATIVE)) {
err = key->type_data.reject_error;
@@ -478,7 +489,7 @@
return ERR_PTR(-ENOKEY);
return keyring_search_aux(keyring, current->cred,
- type, description, type->match);
+ type, description, type->match, false);
}
EXPORT_SYMBOL(keyring_search);
diff --git a/security/keys/proc.c b/security/keys/proc.c
index 525cf8a..49bbc97 100644
--- a/security/keys/proc.c
+++ b/security/keys/proc.c
@@ -199,7 +199,7 @@
if (key->perm & KEY_POS_VIEW) {
skey_ref = search_my_process_keyrings(key->type, key,
lookup_user_key_possessed,
- cred);
+ true, cred);
if (!IS_ERR(skey_ref)) {
key_ref_put(skey_ref);
key_ref = make_key_ref(key, 1);
diff --git a/security/keys/process_keys.c b/security/keys/process_keys.c
index 930634e..6c0480d 100644
--- a/security/keys/process_keys.c
+++ b/security/keys/process_keys.c
@@ -331,6 +331,7 @@
key_ref_t search_my_process_keyrings(struct key_type *type,
const void *description,
key_match_func_t match,
+ bool no_state_check,
const struct cred *cred)
{
key_ref_t key_ref, ret, err;
@@ -350,7 +351,7 @@
if (cred->thread_keyring) {
key_ref = keyring_search_aux(
make_key_ref(cred->thread_keyring, 1),
- cred, type, description, match);
+ cred, type, description, match, no_state_check);
if (!IS_ERR(key_ref))
goto found;
@@ -371,7 +372,7 @@
if (cred->tgcred->process_keyring) {
key_ref = keyring_search_aux(
make_key_ref(cred->tgcred->process_keyring, 1),
- cred, type, description, match);
+ cred, type, description, match, no_state_check);
if (!IS_ERR(key_ref))
goto found;
@@ -395,7 +396,7 @@
make_key_ref(rcu_dereference(
cred->tgcred->session_keyring),
1),
- cred, type, description, match);
+ cred, type, description, match, no_state_check);
rcu_read_unlock();
if (!IS_ERR(key_ref))
@@ -417,7 +418,7 @@
else if (cred->user->session_keyring) {
key_ref = keyring_search_aux(
make_key_ref(cred->user->session_keyring, 1),
- cred, type, description, match);
+ cred, type, description, match, no_state_check);
if (!IS_ERR(key_ref))
goto found;
@@ -459,7 +460,8 @@
might_sleep();
- key_ref = search_my_process_keyrings(type, description, match, cred);
+ key_ref = search_my_process_keyrings(type, description, match,
+ false, cred);
if (!IS_ERR(key_ref))
goto found;
err = key_ref;
diff --git a/security/keys/request_key.c b/security/keys/request_key.c
index df3c041..b18a717 100644
--- a/security/keys/request_key.c
+++ b/security/keys/request_key.c
@@ -530,8 +530,7 @@
dest_keyring, flags);
/* search all the process keyrings for a key */
- key_ref = search_process_keyrings(type, description, type->match,
- cred);
+ key_ref = search_process_keyrings(type, description, type->match, cred);
if (!IS_ERR(key_ref)) {
key = key_ref_to_ptr(key_ref);
diff --git a/security/keys/request_key_auth.c b/security/keys/request_key_auth.c
index 6816403..f6337c9 100644
--- a/security/keys/request_key_auth.c
+++ b/security/keys/request_key_auth.c
@@ -59,7 +59,8 @@
seq_puts(m, "key:");
seq_puts(m, key->description);
- seq_printf(m, " pid:%d ci:%zu", rka->pid, rka->callout_len);
+ if (key_is_instantiated(key))
+ seq_printf(m, " pid:%d ci:%zu", rka->pid, rka->callout_len);
}
/*
diff --git a/security/keys/user_defined.c b/security/keys/user_defined.c
index f66baf4..5b366d7 100644
--- a/security/keys/user_defined.c
+++ b/security/keys/user_defined.c
@@ -157,8 +157,8 @@
void user_describe(const struct key *key, struct seq_file *m)
{
seq_puts(m, key->description);
-
- seq_printf(m, ": %u", key->datalen);
+ if (key_is_instantiated(key))
+ seq_printf(m, ": %u", key->datalen);
}
EXPORT_SYMBOL_GPL(user_describe);
diff --git a/security/lsm_audit.c b/security/lsm_audit.c
index 908aa71..893af8a 100644
--- a/security/lsm_audit.c
+++ b/security/lsm_audit.c
@@ -210,7 +210,6 @@
static void dump_common_audit_data(struct audit_buffer *ab,
struct common_audit_data *a)
{
- struct inode *inode = NULL;
struct task_struct *tsk = current;
if (a->tsk)
@@ -229,33 +228,47 @@
case LSM_AUDIT_DATA_CAP:
audit_log_format(ab, " capability=%d ", a->u.cap);
break;
- case LSM_AUDIT_DATA_FS:
- if (a->u.fs.path.dentry) {
- struct dentry *dentry = a->u.fs.path.dentry;
- if (a->u.fs.path.mnt) {
- audit_log_d_path(ab, "path=", &a->u.fs.path);
- } else {
- audit_log_format(ab, " name=");
- audit_log_untrustedstring(ab,
- dentry->d_name.name);
- }
- inode = dentry->d_inode;
- } else if (a->u.fs.inode) {
- struct dentry *dentry;
- inode = a->u.fs.inode;
- dentry = d_find_alias(inode);
- if (dentry) {
- audit_log_format(ab, " name=");
- audit_log_untrustedstring(ab,
- dentry->d_name.name);
- dput(dentry);
- }
- }
+ case LSM_AUDIT_DATA_PATH: {
+ struct inode *inode;
+
+ audit_log_d_path(ab, "path=", &a->u.path);
+
+ inode = a->u.path.dentry->d_inode;
if (inode)
audit_log_format(ab, " dev=%s ino=%lu",
inode->i_sb->s_id,
inode->i_ino);
break;
+ }
+ case LSM_AUDIT_DATA_DENTRY: {
+ struct inode *inode;
+
+ audit_log_format(ab, " name=");
+ audit_log_untrustedstring(ab, a->u.dentry->d_name.name);
+
+ inode = a->u.dentry->d_inode;
+ if (inode)
+ audit_log_format(ab, " dev=%s ino=%lu",
+ inode->i_sb->s_id,
+ inode->i_ino);
+ break;
+ }
+ case LSM_AUDIT_DATA_INODE: {
+ struct dentry *dentry;
+ struct inode *inode;
+
+ inode = a->u.inode;
+ dentry = d_find_alias(inode);
+ if (dentry) {
+ audit_log_format(ab, " name=");
+ audit_log_untrustedstring(ab,
+ dentry->d_name.name);
+ dput(dentry);
+ }
+ audit_log_format(ab, " dev=%s ino=%lu", inode->i_sb->s_id,
+ inode->i_ino);
+ break;
+ }
case LSM_AUDIT_DATA_TASK:
tsk = a->u.tsk;
if (tsk && tsk->pid) {
diff --git a/security/selinux/avc.c b/security/selinux/avc.c
index 3d2715f..fcb89cb 100644
--- a/security/selinux/avc.c
+++ b/security/selinux/avc.c
@@ -526,7 +526,7 @@
* during retry. However this is logically just as if the operation
* happened a little later.
*/
- if ((a->type == LSM_AUDIT_DATA_FS) &&
+ if ((a->type == LSM_AUDIT_DATA_INODE) &&
(flags & IPERM_FLAG_RCU))
return -ECHILD;
diff --git a/security/selinux/hooks.c b/security/selinux/hooks.c
index 8fb2488..a0d3845 100644
--- a/security/selinux/hooks.c
+++ b/security/selinux/hooks.c
@@ -990,6 +990,7 @@
continue;
default:
BUG();
+ return;
};
/* we need a comma before each option */
seq_putc(m, ',');
@@ -1443,6 +1444,7 @@
printk(KERN_ERR
"SELinux: out of range capability %d\n", cap);
BUG();
+ return -EINVAL;
}
rc = avc_has_perm_noaudit(sid, sid, sclass, av, 0, &avd);
@@ -1487,8 +1489,8 @@
if (!adp) {
adp = &ad;
- COMMON_AUDIT_DATA_INIT(&ad, FS);
- ad.u.fs.inode = inode;
+ COMMON_AUDIT_DATA_INIT(&ad, INODE);
+ ad.u.inode = inode;
}
return avc_has_perm_flags(sid, isec->sid, isec->sclass, perms, adp, flags);
@@ -1498,16 +1500,29 @@
the dentry to help the auditing code to more easily generate the
pathname if needed. */
static inline int dentry_has_perm(const struct cred *cred,
- struct vfsmount *mnt,
struct dentry *dentry,
u32 av)
{
struct inode *inode = dentry->d_inode;
struct common_audit_data ad;
- COMMON_AUDIT_DATA_INIT(&ad, FS);
- ad.u.fs.path.mnt = mnt;
- ad.u.fs.path.dentry = dentry;
+ COMMON_AUDIT_DATA_INIT(&ad, DENTRY);
+ ad.u.dentry = dentry;
+ return inode_has_perm(cred, inode, av, &ad, 0);
+}
+
+/* Same as inode_has_perm, but pass explicit audit data containing
+ the path to help the auditing code to more easily generate the
+ pathname if needed. */
+static inline int path_has_perm(const struct cred *cred,
+ struct path *path,
+ u32 av)
+{
+ struct inode *inode = path->dentry->d_inode;
+ struct common_audit_data ad;
+
+ COMMON_AUDIT_DATA_INIT(&ad, PATH);
+ ad.u.path = *path;
return inode_has_perm(cred, inode, av, &ad, 0);
}
@@ -1529,8 +1544,8 @@
u32 sid = cred_sid(cred);
int rc;
- COMMON_AUDIT_DATA_INIT(&ad, FS);
- ad.u.fs.path = file->f_path;
+ COMMON_AUDIT_DATA_INIT(&ad, PATH);
+ ad.u.path = file->f_path;
if (sid != fsec->sid) {
rc = avc_has_perm(sid, fsec->sid,
@@ -1568,8 +1583,8 @@
sid = tsec->sid;
newsid = tsec->create_sid;
- COMMON_AUDIT_DATA_INIT(&ad, FS);
- ad.u.fs.path.dentry = dentry;
+ COMMON_AUDIT_DATA_INIT(&ad, DENTRY);
+ ad.u.dentry = dentry;
rc = avc_has_perm(sid, dsec->sid, SECCLASS_DIR,
DIR__ADD_NAME | DIR__SEARCH,
@@ -1621,8 +1636,8 @@
dsec = dir->i_security;
isec = dentry->d_inode->i_security;
- COMMON_AUDIT_DATA_INIT(&ad, FS);
- ad.u.fs.path.dentry = dentry;
+ COMMON_AUDIT_DATA_INIT(&ad, DENTRY);
+ ad.u.dentry = dentry;
av = DIR__SEARCH;
av |= (kind ? DIR__REMOVE_NAME : DIR__ADD_NAME);
@@ -1667,9 +1682,9 @@
old_is_dir = S_ISDIR(old_dentry->d_inode->i_mode);
new_dsec = new_dir->i_security;
- COMMON_AUDIT_DATA_INIT(&ad, FS);
+ COMMON_AUDIT_DATA_INIT(&ad, DENTRY);
- ad.u.fs.path.dentry = old_dentry;
+ ad.u.dentry = old_dentry;
rc = avc_has_perm(sid, old_dsec->sid, SECCLASS_DIR,
DIR__REMOVE_NAME | DIR__SEARCH, &ad);
if (rc)
@@ -1685,7 +1700,7 @@
return rc;
}
- ad.u.fs.path.dentry = new_dentry;
+ ad.u.dentry = new_dentry;
av = DIR__ADD_NAME | DIR__SEARCH;
if (new_dentry->d_inode)
av |= DIR__REMOVE_NAME;
@@ -1895,7 +1910,7 @@
{
const struct cred *cred = current_cred();
- return dentry_has_perm(cred, NULL, dentry, FILE__QUOTAON);
+ return dentry_has_perm(cred, dentry, FILE__QUOTAON);
}
static int selinux_syslog(int type)
@@ -1992,8 +2007,8 @@
return rc;
}
- COMMON_AUDIT_DATA_INIT(&ad, FS);
- ad.u.fs.path = bprm->file->f_path;
+ COMMON_AUDIT_DATA_INIT(&ad, PATH);
+ ad.u.path = bprm->file->f_path;
if (bprm->file->f_path.mnt->mnt_flags & MNT_NOSUID)
new_tsec->sid = old_tsec->sid;
@@ -2121,7 +2136,7 @@
/* Revalidate access to inherited open files. */
- COMMON_AUDIT_DATA_INIT(&ad, FS);
+ COMMON_AUDIT_DATA_INIT(&ad, INODE);
spin_lock(&files->file_lock);
for (;;) {
@@ -2469,8 +2484,8 @@
if (flags & MS_KERNMOUNT)
return 0;
- COMMON_AUDIT_DATA_INIT(&ad, FS);
- ad.u.fs.path.dentry = sb->s_root;
+ COMMON_AUDIT_DATA_INIT(&ad, DENTRY);
+ ad.u.dentry = sb->s_root;
return superblock_has_perm(cred, sb, FILESYSTEM__MOUNT, &ad);
}
@@ -2479,8 +2494,8 @@
const struct cred *cred = current_cred();
struct common_audit_data ad;
- COMMON_AUDIT_DATA_INIT(&ad, FS);
- ad.u.fs.path.dentry = dentry->d_sb->s_root;
+ COMMON_AUDIT_DATA_INIT(&ad, DENTRY);
+ ad.u.dentry = dentry->d_sb->s_root;
return superblock_has_perm(cred, dentry->d_sb, FILESYSTEM__GETATTR, &ad);
}
@@ -2496,8 +2511,7 @@
return superblock_has_perm(cred, path->mnt->mnt_sb,
FILESYSTEM__REMOUNT, NULL);
else
- return dentry_has_perm(cred, path->mnt, path->dentry,
- FILE__MOUNTON);
+ return path_has_perm(cred, path, FILE__MOUNTON);
}
static int selinux_umount(struct vfsmount *mnt, int flags)
@@ -2630,14 +2644,14 @@
{
const struct cred *cred = current_cred();
- return dentry_has_perm(cred, NULL, dentry, FILE__READ);
+ return dentry_has_perm(cred, dentry, FILE__READ);
}
static int selinux_inode_follow_link(struct dentry *dentry, struct nameidata *nameidata)
{
const struct cred *cred = current_cred();
- return dentry_has_perm(cred, NULL, dentry, FILE__READ);
+ return dentry_has_perm(cred, dentry, FILE__READ);
}
static int selinux_inode_permission(struct inode *inode, int mask, unsigned flags)
@@ -2654,8 +2668,8 @@
if (!mask)
return 0;
- COMMON_AUDIT_DATA_INIT(&ad, FS);
- ad.u.fs.inode = inode;
+ COMMON_AUDIT_DATA_INIT(&ad, INODE);
+ ad.u.inode = inode;
if (from_access)
ad.selinux_audit_data.auditdeny |= FILE__AUDIT_ACCESS;
@@ -2680,16 +2694,20 @@
if (ia_valid & (ATTR_MODE | ATTR_UID | ATTR_GID |
ATTR_ATIME_SET | ATTR_MTIME_SET | ATTR_TIMES_SET))
- return dentry_has_perm(cred, NULL, dentry, FILE__SETATTR);
+ return dentry_has_perm(cred, dentry, FILE__SETATTR);
- return dentry_has_perm(cred, NULL, dentry, FILE__WRITE);
+ return dentry_has_perm(cred, dentry, FILE__WRITE);
}
static int selinux_inode_getattr(struct vfsmount *mnt, struct dentry *dentry)
{
const struct cred *cred = current_cred();
+ struct path path;
- return dentry_has_perm(cred, mnt, dentry, FILE__GETATTR);
+ path.dentry = dentry;
+ path.mnt = mnt;
+
+ return path_has_perm(cred, &path, FILE__GETATTR);
}
static int selinux_inode_setotherxattr(struct dentry *dentry, const char *name)
@@ -2710,7 +2728,7 @@
/* Not an attribute we recognize, so just check the
ordinary setattr permission. */
- return dentry_has_perm(cred, NULL, dentry, FILE__SETATTR);
+ return dentry_has_perm(cred, dentry, FILE__SETATTR);
}
static int selinux_inode_setxattr(struct dentry *dentry, const char *name,
@@ -2733,8 +2751,8 @@
if (!inode_owner_or_capable(inode))
return -EPERM;
- COMMON_AUDIT_DATA_INIT(&ad, FS);
- ad.u.fs.path.dentry = dentry;
+ COMMON_AUDIT_DATA_INIT(&ad, DENTRY);
+ ad.u.dentry = dentry;
rc = avc_has_perm(sid, isec->sid, isec->sclass,
FILE__RELABELFROM, &ad);
@@ -2797,14 +2815,14 @@
{
const struct cred *cred = current_cred();
- return dentry_has_perm(cred, NULL, dentry, FILE__GETATTR);
+ return dentry_has_perm(cred, dentry, FILE__GETATTR);
}
static int selinux_inode_listxattr(struct dentry *dentry)
{
const struct cred *cred = current_cred();
- return dentry_has_perm(cred, NULL, dentry, FILE__GETATTR);
+ return dentry_has_perm(cred, dentry, FILE__GETATTR);
}
static int selinux_inode_removexattr(struct dentry *dentry, const char *name)
diff --git a/security/selinux/include/security.h b/security/selinux/include/security.h
index 348eb00..3ba4feb 100644
--- a/security/selinux/include/security.h
+++ b/security/selinux/include/security.h
@@ -30,13 +30,14 @@
#define POLICYDB_VERSION_PERMISSIVE 23
#define POLICYDB_VERSION_BOUNDARY 24
#define POLICYDB_VERSION_FILENAME_TRANS 25
+#define POLICYDB_VERSION_ROLETRANS 26
/* Range of policy versions we understand*/
#define POLICYDB_VERSION_MIN POLICYDB_VERSION_BASE
#ifdef CONFIG_SECURITY_SELINUX_POLICYDB_VERSION_MAX
#define POLICYDB_VERSION_MAX CONFIG_SECURITY_SELINUX_POLICYDB_VERSION_MAX_VALUE
#else
-#define POLICYDB_VERSION_MAX POLICYDB_VERSION_FILENAME_TRANS
+#define POLICYDB_VERSION_MAX POLICYDB_VERSION_ROLETRANS
#endif
/* Mask for just the mount related flags */
@@ -85,7 +86,7 @@
int security_mls_enabled(void);
int security_load_policy(void *data, size_t len);
-int security_read_policy(void **data, ssize_t *len);
+int security_read_policy(void **data, size_t *len);
size_t security_policydb_len(void);
int security_policycap_supported(unsigned int req_cap);
@@ -111,8 +112,8 @@
int security_transition_sid(u32 ssid, u32 tsid, u16 tclass,
const struct qstr *qstr, u32 *out_sid);
-int security_transition_sid_user(u32 ssid, u32 tsid,
- u16 tclass, u32 *out_sid);
+int security_transition_sid_user(u32 ssid, u32 tsid, u16 tclass,
+ const char *objname, u32 *out_sid);
int security_member_sid(u32 ssid, u32 tsid,
u16 tclass, u32 *out_sid);
diff --git a/security/selinux/netnode.c b/security/selinux/netnode.c
index 65ebfe9..3618251 100644
--- a/security/selinux/netnode.c
+++ b/security/selinux/netnode.c
@@ -141,6 +141,7 @@
break;
default:
BUG();
+ return NULL;
}
list_for_each_entry_rcu(node, &sel_netnode_hash[idx].list, list)
diff --git a/security/selinux/selinuxfs.c b/security/selinux/selinuxfs.c
index 2d3373b..77d4413 100644
--- a/security/selinux/selinuxfs.c
+++ b/security/selinux/selinuxfs.c
@@ -28,6 +28,7 @@
#include <linux/percpu.h>
#include <linux/audit.h>
#include <linux/uaccess.h>
+#include <linux/kobject.h>
/* selinuxfs pseudo filesystem for exporting the security policy API.
Based on the proc code and the fs/nfsd/nfsctl.c code. */
@@ -753,11 +754,13 @@
static ssize_t sel_write_create(struct file *file, char *buf, size_t size)
{
char *scon = NULL, *tcon = NULL;
+ char *namebuf = NULL, *objname = NULL;
u32 ssid, tsid, newsid;
u16 tclass;
ssize_t length;
char *newcon = NULL;
u32 len;
+ int nargs;
length = task_has_security(current, SECURITY__COMPUTE_CREATE);
if (length)
@@ -773,10 +776,18 @@
if (!tcon)
goto out;
- length = -EINVAL;
- if (sscanf(buf, "%s %s %hu", scon, tcon, &tclass) != 3)
+ length = -ENOMEM;
+ namebuf = kzalloc(size + 1, GFP_KERNEL);
+ if (!namebuf)
goto out;
+ length = -EINVAL;
+ nargs = sscanf(buf, "%s %s %hu %s", scon, tcon, &tclass, namebuf);
+ if (nargs < 3 || nargs > 4)
+ goto out;
+ if (nargs == 4)
+ objname = namebuf;
+
length = security_context_to_sid(scon, strlen(scon) + 1, &ssid);
if (length)
goto out;
@@ -785,7 +796,8 @@
if (length)
goto out;
- length = security_transition_sid_user(ssid, tsid, tclass, &newsid);
+ length = security_transition_sid_user(ssid, tsid, tclass,
+ objname, &newsid);
if (length)
goto out;
@@ -804,6 +816,7 @@
length = len;
out:
kfree(newcon);
+ kfree(namebuf);
kfree(tcon);
kfree(scon);
return length;
@@ -1901,6 +1914,7 @@
};
struct vfsmount *selinuxfs_mount;
+static struct kobject *selinuxfs_kobj;
static int __init init_sel_fs(void)
{
@@ -1908,9 +1922,16 @@
if (!selinux_enabled)
return 0;
+
+ selinuxfs_kobj = kobject_create_and_add("selinux", fs_kobj);
+ if (!selinuxfs_kobj)
+ return -ENOMEM;
+
err = register_filesystem(&sel_fs_type);
- if (err)
+ if (err) {
+ kobject_put(selinuxfs_kobj);
return err;
+ }
selinuxfs_mount = kern_mount(&sel_fs_type);
if (IS_ERR(selinuxfs_mount)) {
@@ -1927,6 +1948,7 @@
#ifdef CONFIG_SECURITY_SELINUX_DISABLE
void exit_sel_fs(void)
{
+ kobject_put(selinuxfs_kobj);
unregister_filesystem(&sel_fs_type);
}
#endif
diff --git a/security/selinux/ss/policydb.c b/security/selinux/ss/policydb.c
index 7102457..102e9ec 100644
--- a/security/selinux/ss/policydb.c
+++ b/security/selinux/ss/policydb.c
@@ -128,6 +128,11 @@
.sym_num = SYM_NUM,
.ocon_num = OCON_NUM,
},
+ {
+ .version = POLICYDB_VERSION_ROLETRANS,
+ .sym_num = SYM_NUM,
+ .ocon_num = OCON_NUM,
+ },
};
static struct policydb_compat_info *policydb_lookup_compat(int version)
@@ -179,6 +184,43 @@
return rc;
}
+static u32 filenametr_hash(struct hashtab *h, const void *k)
+{
+ const struct filename_trans *ft = k;
+ unsigned long hash;
+ unsigned int byte_num;
+ unsigned char focus;
+
+ hash = ft->stype ^ ft->ttype ^ ft->tclass;
+
+ byte_num = 0;
+ while ((focus = ft->name[byte_num++]))
+ hash = partial_name_hash(focus, hash);
+ return hash & (h->size - 1);
+}
+
+static int filenametr_cmp(struct hashtab *h, const void *k1, const void *k2)
+{
+ const struct filename_trans *ft1 = k1;
+ const struct filename_trans *ft2 = k2;
+ int v;
+
+ v = ft1->stype - ft2->stype;
+ if (v)
+ return v;
+
+ v = ft1->ttype - ft2->ttype;
+ if (v)
+ return v;
+
+ v = ft1->tclass - ft2->tclass;
+ if (v)
+ return v;
+
+ return strcmp(ft1->name, ft2->name);
+
+}
+
static u32 rangetr_hash(struct hashtab *h, const void *k)
{
const struct range_trans *key = k;
@@ -231,15 +273,22 @@
if (rc)
goto out;
+ p->filename_trans = hashtab_create(filenametr_hash, filenametr_cmp, (1 << 10));
+ if (!p->filename_trans)
+ goto out;
+
p->range_tr = hashtab_create(rangetr_hash, rangetr_cmp, 256);
if (!p->range_tr)
goto out;
+ ebitmap_init(&p->filename_trans_ttypes);
ebitmap_init(&p->policycaps);
ebitmap_init(&p->permissive_map);
return 0;
out:
+ hashtab_destroy(p->filename_trans);
+ hashtab_destroy(p->range_tr);
for (i = 0; i < SYM_NUM; i++)
hashtab_destroy(p->symtab[i].table);
return rc;
@@ -417,32 +466,26 @@
};
#ifdef DEBUG_HASHES
-static void symtab_hash_eval(struct symtab *s)
-{
- int i;
-
- for (i = 0; i < SYM_NUM; i++) {
- struct hashtab *h = s[i].table;
- struct hashtab_info info;
-
- hashtab_stat(h, &info);
- printk(KERN_DEBUG "SELinux: %s: %d entries and %d/%d buckets used, "
- "longest chain length %d\n", symtab_name[i], h->nel,
- info.slots_used, h->size, info.max_chain_len);
- }
-}
-
-static void rangetr_hash_eval(struct hashtab *h)
+static void hash_eval(struct hashtab *h, const char *hash_name)
{
struct hashtab_info info;
hashtab_stat(h, &info);
- printk(KERN_DEBUG "SELinux: rangetr: %d entries and %d/%d buckets used, "
- "longest chain length %d\n", h->nel,
+ printk(KERN_DEBUG "SELinux: %s: %d entries and %d/%d buckets used, "
+ "longest chain length %d\n", hash_name, h->nel,
info.slots_used, h->size, info.max_chain_len);
}
+
+static void symtab_hash_eval(struct symtab *s)
+{
+ int i;
+
+ for (i = 0; i < SYM_NUM; i++)
+ hash_eval(s[i].table, symtab_name[i]);
+}
+
#else
-static inline void rangetr_hash_eval(struct hashtab *h)
+static inline void hash_eval(struct hashtab *h, char *hash_name)
{
}
#endif
@@ -675,6 +718,16 @@
cat_destroy,
};
+static int filenametr_destroy(void *key, void *datum, void *p)
+{
+ struct filename_trans *ft = key;
+ kfree(ft->name);
+ kfree(key);
+ kfree(datum);
+ cond_resched();
+ return 0;
+}
+
static int range_tr_destroy(void *key, void *datum, void *p)
{
struct mls_range *rt = datum;
@@ -709,7 +762,6 @@
int i;
struct role_allow *ra, *lra = NULL;
struct role_trans *tr, *ltr = NULL;
- struct filename_trans *ft, *nft;
for (i = 0; i < SYM_NUM; i++) {
cond_resched();
@@ -773,6 +825,9 @@
}
kfree(lra);
+ hashtab_map(p->filename_trans, filenametr_destroy, NULL);
+ hashtab_destroy(p->filename_trans);
+
hashtab_map(p->range_tr, range_tr_destroy, NULL);
hashtab_destroy(p->range_tr);
@@ -788,14 +843,7 @@
flex_array_free(p->type_attr_map_array);
}
- ft = p->filename_trans;
- while (ft) {
- nft = ft->next;
- kfree(ft->name);
- kfree(ft);
- ft = nft;
- }
-
+ ebitmap_destroy(&p->filename_trans_ttypes);
ebitmap_destroy(&p->policycaps);
ebitmap_destroy(&p->permissive_map);
@@ -1795,7 +1843,7 @@
rt = NULL;
r = NULL;
}
- rangetr_hash_eval(p->range_tr);
+ hash_eval(p->range_tr, "rangetr");
rc = 0;
out:
kfree(rt);
@@ -1805,9 +1853,10 @@
static int filename_trans_read(struct policydb *p, void *fp)
{
- struct filename_trans *ft, *last;
- u32 nel, len;
+ struct filename_trans *ft;
+ struct filename_trans_datum *otype;
char *name;
+ u32 nel, len;
__le32 buf[4];
int rc, i;
@@ -1816,25 +1865,23 @@
rc = next_entry(buf, fp, sizeof(u32));
if (rc)
- goto out;
+ return rc;
nel = le32_to_cpu(buf[0]);
- last = p->filename_trans;
- while (last && last->next)
- last = last->next;
-
for (i = 0; i < nel; i++) {
+ ft = NULL;
+ otype = NULL;
+ name = NULL;
+
rc = -ENOMEM;
ft = kzalloc(sizeof(*ft), GFP_KERNEL);
if (!ft)
goto out;
- /* add it to the tail of the list */
- if (!last)
- p->filename_trans = ft;
- else
- last->next = ft;
- last = ft;
+ rc = -ENOMEM;
+ otype = kmalloc(sizeof(*otype), GFP_KERNEL);
+ if (!otype)
+ goto out;
/* length of the path component string */
rc = next_entry(buf, fp, sizeof(u32));
@@ -1862,10 +1909,22 @@
ft->stype = le32_to_cpu(buf[0]);
ft->ttype = le32_to_cpu(buf[1]);
ft->tclass = le32_to_cpu(buf[2]);
- ft->otype = le32_to_cpu(buf[3]);
+
+ otype->otype = le32_to_cpu(buf[3]);
+
+ rc = ebitmap_set_bit(&p->filename_trans_ttypes, ft->ttype, 1);
+ if (rc)
+ goto out;
+
+ hashtab_insert(p->filename_trans, ft, otype);
}
- rc = 0;
+ hash_eval(p->filename_trans, "filenametr");
+ return 0;
out:
+ kfree(ft);
+ kfree(name);
+ kfree(otype);
+
return rc;
}
@@ -2266,6 +2325,11 @@
p->symtab[i].nprim = nprim;
}
+ rc = -EINVAL;
+ p->process_class = string_to_security_class(p, "process");
+ if (!p->process_class)
+ goto bad;
+
rc = avtab_read(&p->te_avtab, fp, p);
if (rc)
goto bad;
@@ -2298,8 +2362,17 @@
tr->role = le32_to_cpu(buf[0]);
tr->type = le32_to_cpu(buf[1]);
tr->new_role = le32_to_cpu(buf[2]);
+ if (p->policyvers >= POLICYDB_VERSION_ROLETRANS) {
+ rc = next_entry(buf, fp, sizeof(u32));
+ if (rc)
+ goto bad;
+ tr->tclass = le32_to_cpu(buf[0]);
+ } else
+ tr->tclass = p->process_class;
+
if (!policydb_role_isvalid(p, tr->role) ||
!policydb_type_isvalid(p, tr->type) ||
+ !policydb_class_isvalid(p, tr->tclass) ||
!policydb_role_isvalid(p, tr->new_role))
goto bad;
ltr = tr;
@@ -2341,11 +2414,6 @@
goto bad;
rc = -EINVAL;
- p->process_class = string_to_security_class(p, "process");
- if (!p->process_class)
- goto bad;
-
- rc = -EINVAL;
p->process_trans_perms = string_to_av_perm(p, p->process_class, "transition");
p->process_trans_perms |= string_to_av_perm(p, p->process_class, "dyntransition");
if (!p->process_trans_perms)
@@ -2517,8 +2585,9 @@
return 0;
}
-static int role_trans_write(struct role_trans *r, void *fp)
+static int role_trans_write(struct policydb *p, void *fp)
{
+ struct role_trans *r = p->role_tr;
struct role_trans *tr;
u32 buf[3];
size_t nel;
@@ -2538,6 +2607,12 @@
rc = put_entry(buf, sizeof(u32), 3, fp);
if (rc)
return rc;
+ if (p->policyvers >= POLICYDB_VERSION_ROLETRANS) {
+ buf[0] = cpu_to_le32(tr->tclass);
+ rc = put_entry(buf, sizeof(u32), 1, fp);
+ if (rc)
+ return rc;
+ }
}
return 0;
@@ -3045,7 +3120,7 @@
return 0;
}
-static int range_count(void *key, void *data, void *ptr)
+static int hashtab_cnt(void *key, void *data, void *ptr)
{
int *cnt = ptr;
*cnt = *cnt + 1;
@@ -3093,7 +3168,7 @@
/* count the number of entries in the hashtab */
nel = 0;
- rc = hashtab_map(p->range_tr, range_count, &nel);
+ rc = hashtab_map(p->range_tr, hashtab_cnt, &nel);
if (rc)
return rc;
@@ -3110,43 +3185,60 @@
return 0;
}
+static int filename_write_helper(void *key, void *data, void *ptr)
+{
+ __le32 buf[4];
+ struct filename_trans *ft = key;
+ struct filename_trans_datum *otype = data;
+ void *fp = ptr;
+ int rc;
+ u32 len;
+
+ len = strlen(ft->name);
+ buf[0] = cpu_to_le32(len);
+ rc = put_entry(buf, sizeof(u32), 1, fp);
+ if (rc)
+ return rc;
+
+ rc = put_entry(ft->name, sizeof(char), len, fp);
+ if (rc)
+ return rc;
+
+ buf[0] = ft->stype;
+ buf[1] = ft->ttype;
+ buf[2] = ft->tclass;
+ buf[3] = otype->otype;
+
+ rc = put_entry(buf, sizeof(u32), 4, fp);
+ if (rc)
+ return rc;
+
+ return 0;
+}
+
static int filename_trans_write(struct policydb *p, void *fp)
{
- struct filename_trans *ft;
- u32 len, nel = 0;
- __le32 buf[4];
+ u32 nel;
+ __le32 buf[1];
int rc;
- for (ft = p->filename_trans; ft; ft = ft->next)
- nel++;
+ nel = 0;
+ rc = hashtab_map(p->filename_trans, hashtab_cnt, &nel);
+ if (rc)
+ return rc;
buf[0] = cpu_to_le32(nel);
rc = put_entry(buf, sizeof(u32), 1, fp);
if (rc)
return rc;
- for (ft = p->filename_trans; ft; ft = ft->next) {
- len = strlen(ft->name);
- buf[0] = cpu_to_le32(len);
- rc = put_entry(buf, sizeof(u32), 1, fp);
- if (rc)
- return rc;
+ rc = hashtab_map(p->filename_trans, filename_write_helper, fp);
+ if (rc)
+ return rc;
- rc = put_entry(ft->name, sizeof(char), len, fp);
- if (rc)
- return rc;
-
- buf[0] = ft->stype;
- buf[1] = ft->ttype;
- buf[2] = ft->tclass;
- buf[3] = ft->otype;
-
- rc = put_entry(buf, sizeof(u32), 4, fp);
- if (rc)
- return rc;
- }
return 0;
}
+
/*
* Write the configuration data in a policy database
* structure to a policy database binary representation
@@ -3249,7 +3341,7 @@
if (rc)
return rc;
- rc = role_trans_write(p->role_tr, fp);
+ rc = role_trans_write(p, fp);
if (rc)
return rc;
diff --git a/security/selinux/ss/policydb.h b/security/selinux/ss/policydb.h
index 732ea4a..b846c03 100644
--- a/security/selinux/ss/policydb.h
+++ b/security/selinux/ss/policydb.h
@@ -72,17 +72,20 @@
struct role_trans {
u32 role; /* current role */
- u32 type; /* program executable type */
+ u32 type; /* program executable type, or new object type */
+ u32 tclass; /* process class, or new object class */
u32 new_role; /* new role */
struct role_trans *next;
};
struct filename_trans {
- struct filename_trans *next;
u32 stype; /* current process */
u32 ttype; /* parent dir context */
u16 tclass; /* class of new object */
const char *name; /* last path component */
+};
+
+struct filename_trans_datum {
u32 otype; /* expected of new object */
};
@@ -227,7 +230,10 @@
struct role_trans *role_tr;
/* file transitions with the last path component */
- struct filename_trans *filename_trans;
+ /* quickly exclude lookups when parent ttype has no rules */
+ struct ebitmap filename_trans_ttypes;
+ /* actual set of filename_trans rules */
+ struct hashtab *filename_trans;
/* bools indexed by (value - 1) */
struct cond_bool_datum **bool_val_to_struct;
diff --git a/security/selinux/ss/services.c b/security/selinux/ss/services.c
index 6ef4af4..c3e4b52 100644
--- a/security/selinux/ss/services.c
+++ b/security/selinux/ss/services.c
@@ -1359,26 +1359,35 @@
}
static void filename_compute_type(struct policydb *p, struct context *newcontext,
- u32 scon, u32 tcon, u16 tclass,
- const struct qstr *qstr)
+ u32 stype, u32 ttype, u16 tclass,
+ const char *objname)
{
- struct filename_trans *ft;
- for (ft = p->filename_trans; ft; ft = ft->next) {
- if (ft->stype == scon &&
- ft->ttype == tcon &&
- ft->tclass == tclass &&
- !strcmp(ft->name, qstr->name)) {
- newcontext->type = ft->otype;
- return;
- }
- }
+ struct filename_trans ft;
+ struct filename_trans_datum *otype;
+
+ /*
+ * Most filename trans rules are going to live in specific directories
+ * like /dev or /var/run. This bitmap will quickly skip rule searches
+ * if the ttype does not contain any rules.
+ */
+ if (!ebitmap_get_bit(&p->filename_trans_ttypes, ttype))
+ return;
+
+ ft.stype = stype;
+ ft.ttype = ttype;
+ ft.tclass = tclass;
+ ft.name = objname;
+
+ otype = hashtab_search(p->filename_trans, &ft);
+ if (otype)
+ newcontext->type = otype->otype;
}
static int security_compute_sid(u32 ssid,
u32 tsid,
u16 orig_tclass,
u32 specified,
- const struct qstr *qstr,
+ const char *objname,
u32 *out_sid,
bool kern)
{
@@ -1478,23 +1487,21 @@
newcontext.type = avdatum->data;
}
- /* if we have a qstr this is a file trans check so check those rules */
- if (qstr)
+ /* if we have a objname this is a file trans check so check those rules */
+ if (objname)
filename_compute_type(&policydb, &newcontext, scontext->type,
- tcontext->type, tclass, qstr);
+ tcontext->type, tclass, objname);
/* Check for class-specific changes. */
- if (tclass == policydb.process_class) {
- if (specified & AVTAB_TRANSITION) {
- /* Look for a role transition rule. */
- for (roletr = policydb.role_tr; roletr;
- roletr = roletr->next) {
- if (roletr->role == scontext->role &&
- roletr->type == tcontext->type) {
- /* Use the role transition rule. */
- newcontext.role = roletr->new_role;
- break;
- }
+ if (specified & AVTAB_TRANSITION) {
+ /* Look for a role transition rule. */
+ for (roletr = policydb.role_tr; roletr; roletr = roletr->next) {
+ if ((roletr->role == scontext->role) &&
+ (roletr->type == tcontext->type) &&
+ (roletr->tclass == tclass)) {
+ /* Use the role transition rule. */
+ newcontext.role = roletr->new_role;
+ break;
}
}
}
@@ -1541,13 +1548,14 @@
const struct qstr *qstr, u32 *out_sid)
{
return security_compute_sid(ssid, tsid, tclass, AVTAB_TRANSITION,
- qstr, out_sid, true);
+ qstr ? qstr->name : NULL, out_sid, true);
}
-int security_transition_sid_user(u32 ssid, u32 tsid, u16 tclass, u32 *out_sid)
+int security_transition_sid_user(u32 ssid, u32 tsid, u16 tclass,
+ const char *objname, u32 *out_sid)
{
return security_compute_sid(ssid, tsid, tclass, AVTAB_TRANSITION,
- NULL, out_sid, false);
+ objname, out_sid, false);
}
/**
@@ -3190,7 +3198,7 @@
* @len: length of data in bytes
*
*/
-int security_read_policy(void **data, ssize_t *len)
+int security_read_policy(void **data, size_t *len)
{
int rc;
struct policy_file fp;
diff --git a/security/smack/smack.h b/security/smack/smack.h
index b449cfd..2b6c6a5 100644
--- a/security/smack/smack.h
+++ b/security/smack/smack.h
@@ -316,22 +316,17 @@
static inline void smk_ad_setfield_u_fs_path_dentry(struct smk_audit_info *a,
struct dentry *d)
{
- a->a.u.fs.path.dentry = d;
-}
-static inline void smk_ad_setfield_u_fs_path_mnt(struct smk_audit_info *a,
- struct vfsmount *m)
-{
- a->a.u.fs.path.mnt = m;
+ a->a.u.dentry = d;
}
static inline void smk_ad_setfield_u_fs_inode(struct smk_audit_info *a,
struct inode *i)
{
- a->a.u.fs.inode = i;
+ a->a.u.inode = i;
}
static inline void smk_ad_setfield_u_fs_path(struct smk_audit_info *a,
struct path p)
{
- a->a.u.fs.path = p;
+ a->a.u.path = p;
}
static inline void smk_ad_setfield_u_net_sk(struct smk_audit_info *a,
struct sock *sk)
diff --git a/security/smack/smack_lsm.c b/security/smack/smack_lsm.c
index 400a5d5..9831a39 100644
--- a/security/smack/smack_lsm.c
+++ b/security/smack/smack_lsm.c
@@ -383,7 +383,7 @@
int rc;
struct smk_audit_info ad;
- smk_ad_init(&ad, __func__, LSM_AUDIT_DATA_FS);
+ smk_ad_init(&ad, __func__, LSM_AUDIT_DATA_DENTRY);
smk_ad_setfield_u_fs_path_dentry(&ad, dentry);
rc = smk_curacc(sbp->smk_floor, MAY_READ, &ad);
@@ -407,7 +407,7 @@
struct superblock_smack *sbp = path->mnt->mnt_sb->s_security;
struct smk_audit_info ad;
- smk_ad_init(&ad, __func__, LSM_AUDIT_DATA_FS);
+ smk_ad_init(&ad, __func__, LSM_AUDIT_DATA_PATH);
smk_ad_setfield_u_fs_path(&ad, *path);
return smk_curacc(sbp->smk_floor, MAY_WRITE, &ad);
@@ -425,10 +425,13 @@
{
struct superblock_smack *sbp;
struct smk_audit_info ad;
+ struct path path;
- smk_ad_init(&ad, __func__, LSM_AUDIT_DATA_FS);
- smk_ad_setfield_u_fs_path_dentry(&ad, mnt->mnt_root);
- smk_ad_setfield_u_fs_path_mnt(&ad, mnt);
+ path.dentry = mnt->mnt_root;
+ path.mnt = mnt;
+
+ smk_ad_init(&ad, __func__, LSM_AUDIT_DATA_PATH);
+ smk_ad_setfield_u_fs_path(&ad, path);
sbp = mnt->mnt_sb->s_security;
return smk_curacc(sbp->smk_floor, MAY_WRITE, &ad);
@@ -563,7 +566,7 @@
struct smk_audit_info ad;
int rc;
- smk_ad_init(&ad, __func__, LSM_AUDIT_DATA_FS);
+ smk_ad_init(&ad, __func__, LSM_AUDIT_DATA_DENTRY);
smk_ad_setfield_u_fs_path_dentry(&ad, old_dentry);
isp = smk_of_inode(old_dentry->d_inode);
@@ -592,7 +595,7 @@
struct smk_audit_info ad;
int rc;
- smk_ad_init(&ad, __func__, LSM_AUDIT_DATA_FS);
+ smk_ad_init(&ad, __func__, LSM_AUDIT_DATA_DENTRY);
smk_ad_setfield_u_fs_path_dentry(&ad, dentry);
/*
@@ -623,7 +626,7 @@
struct smk_audit_info ad;
int rc;
- smk_ad_init(&ad, __func__, LSM_AUDIT_DATA_FS);
+ smk_ad_init(&ad, __func__, LSM_AUDIT_DATA_DENTRY);
smk_ad_setfield_u_fs_path_dentry(&ad, dentry);
/*
@@ -663,7 +666,7 @@
char *isp;
struct smk_audit_info ad;
- smk_ad_init(&ad, __func__, LSM_AUDIT_DATA_FS);
+ smk_ad_init(&ad, __func__, LSM_AUDIT_DATA_DENTRY);
smk_ad_setfield_u_fs_path_dentry(&ad, old_dentry);
isp = smk_of_inode(old_dentry->d_inode);
@@ -700,7 +703,7 @@
/* May be droppable after audit */
if (flags & IPERM_FLAG_RCU)
return -ECHILD;
- smk_ad_init(&ad, __func__, LSM_AUDIT_DATA_FS);
+ smk_ad_init(&ad, __func__, LSM_AUDIT_DATA_INODE);
smk_ad_setfield_u_fs_inode(&ad, inode);
return smk_curacc(smk_of_inode(inode), mask, &ad);
}
@@ -720,7 +723,7 @@
*/
if (iattr->ia_valid & ATTR_FORCE)
return 0;
- smk_ad_init(&ad, __func__, LSM_AUDIT_DATA_FS);
+ smk_ad_init(&ad, __func__, LSM_AUDIT_DATA_DENTRY);
smk_ad_setfield_u_fs_path_dentry(&ad, dentry);
return smk_curacc(smk_of_inode(dentry->d_inode), MAY_WRITE, &ad);
@@ -736,10 +739,13 @@
static int smack_inode_getattr(struct vfsmount *mnt, struct dentry *dentry)
{
struct smk_audit_info ad;
+ struct path path;
- smk_ad_init(&ad, __func__, LSM_AUDIT_DATA_FS);
- smk_ad_setfield_u_fs_path_dentry(&ad, dentry);
- smk_ad_setfield_u_fs_path_mnt(&ad, mnt);
+ path.dentry = dentry;
+ path.mnt = mnt;
+
+ smk_ad_init(&ad, __func__, LSM_AUDIT_DATA_PATH);
+ smk_ad_setfield_u_fs_path(&ad, path);
return smk_curacc(smk_of_inode(dentry->d_inode), MAY_READ, &ad);
}
@@ -784,7 +790,7 @@
} else
rc = cap_inode_setxattr(dentry, name, value, size, flags);
- smk_ad_init(&ad, __func__, LSM_AUDIT_DATA_FS);
+ smk_ad_init(&ad, __func__, LSM_AUDIT_DATA_DENTRY);
smk_ad_setfield_u_fs_path_dentry(&ad, dentry);
if (rc == 0)
@@ -845,7 +851,7 @@
{
struct smk_audit_info ad;
- smk_ad_init(&ad, __func__, LSM_AUDIT_DATA_FS);
+ smk_ad_init(&ad, __func__, LSM_AUDIT_DATA_DENTRY);
smk_ad_setfield_u_fs_path_dentry(&ad, dentry);
return smk_curacc(smk_of_inode(dentry->d_inode), MAY_READ, &ad);
@@ -877,7 +883,7 @@
} else
rc = cap_inode_removexattr(dentry, name);
- smk_ad_init(&ad, __func__, LSM_AUDIT_DATA_FS);
+ smk_ad_init(&ad, __func__, LSM_AUDIT_DATA_DENTRY);
smk_ad_setfield_u_fs_path_dentry(&ad, dentry);
if (rc == 0)
rc = smk_curacc(smk_of_inode(dentry->d_inode), MAY_WRITE, &ad);
@@ -1047,7 +1053,7 @@
int rc = 0;
struct smk_audit_info ad;
- smk_ad_init(&ad, __func__, LSM_AUDIT_DATA_FS);
+ smk_ad_init(&ad, __func__, LSM_AUDIT_DATA_PATH);
smk_ad_setfield_u_fs_path(&ad, file->f_path);
if (_IOC_DIR(cmd) & _IOC_WRITE)
@@ -1070,8 +1076,8 @@
{
struct smk_audit_info ad;
- smk_ad_init(&ad, __func__, LSM_AUDIT_DATA_FS);
- smk_ad_setfield_u_fs_path_dentry(&ad, file->f_path.dentry);
+ smk_ad_init(&ad, __func__, LSM_AUDIT_DATA_PATH);
+ smk_ad_setfield_u_fs_path(&ad, file->f_path);
return smk_curacc(file->f_security, MAY_WRITE, &ad);
}
@@ -1089,7 +1095,7 @@
struct smk_audit_info ad;
int rc;
- smk_ad_init(&ad, __func__, LSM_AUDIT_DATA_FS);
+ smk_ad_init(&ad, __func__, LSM_AUDIT_DATA_PATH);
smk_ad_setfield_u_fs_path(&ad, file->f_path);
switch (cmd) {
diff --git a/security/tomoyo/common.c b/security/tomoyo/common.c
index 7556315..a0d09e5 100644
--- a/security/tomoyo/common.c
+++ b/security/tomoyo/common.c
@@ -108,10 +108,9 @@
head->read_user_buf += len;
w += len;
}
- if (*w) {
- head->r.w[0] = w;
+ head->r.w[0] = w;
+ if (*w)
return false;
- }
/* Add '\0' for query. */
if (head->poll) {
if (!head->read_user_buf_avail ||
@@ -459,8 +458,16 @@
if (profile == &tomoyo_default_profile)
return -EINVAL;
if (!strcmp(data, "COMMENT")) {
- const struct tomoyo_path_info *old_comment = profile->comment;
- profile->comment = tomoyo_get_name(cp);
+ static DEFINE_SPINLOCK(lock);
+ const struct tomoyo_path_info *new_comment
+ = tomoyo_get_name(cp);
+ const struct tomoyo_path_info *old_comment;
+ if (!new_comment)
+ return -ENOMEM;
+ spin_lock(&lock);
+ old_comment = profile->comment;
+ profile->comment = new_comment;
+ spin_unlock(&lock);
tomoyo_put_name(old_comment);
return 0;
}
diff --git a/security/tomoyo/file.c b/security/tomoyo/file.c
index cb09f1f..d64e8ec 100644
--- a/security/tomoyo/file.c
+++ b/security/tomoyo/file.c
@@ -1011,7 +1011,6 @@
break;
case TOMOYO_TYPE_RMDIR:
case TOMOYO_TYPE_CHROOT:
- case TOMOYO_TYPE_UMOUNT:
tomoyo_add_slash(&buf);
break;
}
diff --git a/security/tomoyo/memory.c b/security/tomoyo/memory.c
index 2976126..42a7b1b 100644
--- a/security/tomoyo/memory.c
+++ b/security/tomoyo/memory.c
@@ -75,6 +75,7 @@
memset(data, 0, size);
return ptr;
}
+ kfree(ptr);
return NULL;
}
diff --git a/security/tomoyo/mount.c b/security/tomoyo/mount.c
index 82bf8c2..162a864 100644
--- a/security/tomoyo/mount.c
+++ b/security/tomoyo/mount.c
@@ -143,6 +143,7 @@
goto out;
}
requested_dev_name = tomoyo_realpath_from_path(&path);
+ path_put(&path);
if (!requested_dev_name) {
error = -ENOENT;
goto out;
diff --git a/security/tomoyo/util.c b/security/tomoyo/util.c
index 9bfc1ee..6d53932 100644
--- a/security/tomoyo/util.c
+++ b/security/tomoyo/util.c
@@ -390,7 +390,7 @@
if (!cp)
break;
if (*domainname != '/' ||
- !tomoyo_correct_word2(domainname, cp - domainname - 1))
+ !tomoyo_correct_word2(domainname, cp - domainname))
goto out;
domainname = cp + 1;
}
diff --git a/sound/pcmcia/pdaudiocf/pdaudiocf.c b/sound/pcmcia/pdaudiocf/pdaudiocf.c
index 8cc4733..ce33be0 100644
--- a/sound/pcmcia/pdaudiocf/pdaudiocf.c
+++ b/sound/pcmcia/pdaudiocf/pdaudiocf.c
@@ -278,7 +278,7 @@
/*
* Module entry points
*/
-static struct pcmcia_device_id snd_pdacf_ids[] = {
+static const struct pcmcia_device_id snd_pdacf_ids[] = {
/* this is too general PCMCIA_DEVICE_MANF_CARD(0x015d, 0x4c45), */
PCMCIA_DEVICE_PROD_ID12("Core Sound","PDAudio-CF",0x396d19d2,0x71717b49),
PCMCIA_DEVICE_NULL
diff --git a/sound/pcmcia/vx/vxpocket.c b/sound/pcmcia/vx/vxpocket.c
index 80000d6..d9ef21d 100644
--- a/sound/pcmcia/vx/vxpocket.c
+++ b/sound/pcmcia/vx/vxpocket.c
@@ -350,7 +350,7 @@
* Module entry points
*/
-static struct pcmcia_device_id vxp_ids[] = {
+static const struct pcmcia_device_id vxp_ids[] = {
PCMCIA_DEVICE_MANF_CARD(0x01f1, 0x0100),
PCMCIA_DEVICE_NULL
};
diff --git a/sound/soc/codecs/cx20442.c b/sound/soc/codecs/cx20442.c
index d68ea53..f8c663d 100644
--- a/sound/soc/codecs/cx20442.c
+++ b/sound/soc/codecs/cx20442.c
@@ -262,14 +262,14 @@
}
/* Line discipline .receive_buf() */
-static void v253_receive(struct tty_struct *tty,
- const unsigned char *cp, char *fp, int count)
+static unsigned int v253_receive(struct tty_struct *tty,
+ const unsigned char *cp, char *fp, int count)
{
struct snd_soc_codec *codec = tty->disc_data;
struct cx20442_priv *cx20442;
if (!codec)
- return;
+ return count;
cx20442 = snd_soc_codec_get_drvdata(codec);
@@ -281,6 +281,8 @@
codec->hw_write = (hw_write_t)tty->ops->write;
codec->card->pop_time = 1;
}
+
+ return count;
}
/* Line discipline .write_wakeup() */
diff --git a/tools/perf/util/event.c b/tools/perf/util/event.c
index 252b72a..6635fcd 100644
--- a/tools/perf/util/event.c
+++ b/tools/perf/util/event.c
@@ -42,7 +42,7 @@
int i;
for (i = 0; i < 64; i++) {
- if (mask & (1UL << i))
+ if (mask & (1ULL << i))
size++;
}
diff --git a/usr/gen_init_cpio.c b/usr/gen_init_cpio.c
index 7f06884..af0f22f 100644
--- a/usr/gen_init_cpio.c
+++ b/usr/gen_init_cpio.c
@@ -22,6 +22,7 @@
static unsigned int offset;
static unsigned int ino = 721;
+static time_t default_mtime;
struct file_handler {
const char *type;
@@ -102,7 +103,6 @@
unsigned int mode, uid_t uid, gid_t gid)
{
char s[256];
- time_t mtime = time(NULL);
if (name[0] == '/')
name++;
@@ -114,7 +114,7 @@
(long) uid, /* uid */
(long) gid, /* gid */
1, /* nlink */
- (long) mtime, /* mtime */
+ (long) default_mtime, /* mtime */
(unsigned)strlen(target)+1, /* filesize */
3, /* major */
1, /* minor */
@@ -152,7 +152,6 @@
uid_t uid, gid_t gid)
{
char s[256];
- time_t mtime = time(NULL);
if (name[0] == '/')
name++;
@@ -164,7 +163,7 @@
(long) uid, /* uid */
(long) gid, /* gid */
2, /* nlink */
- (long) mtime, /* mtime */
+ (long) default_mtime, /* mtime */
0, /* filesize */
3, /* major */
1, /* minor */
@@ -242,7 +241,6 @@
unsigned int maj, unsigned int min)
{
char s[256];
- time_t mtime = time(NULL);
if (dev_type == 'b')
mode |= S_IFBLK;
@@ -259,7 +257,7 @@
(long) uid, /* uid */
(long) gid, /* gid */
1, /* nlink */
- (long) mtime, /* mtime */
+ (long) default_mtime, /* mtime */
0, /* filesize */
3, /* major */
1, /* minor */
@@ -460,7 +458,7 @@
static void usage(const char *prog)
{
fprintf(stderr, "Usage:\n"
- "\t%s <cpio_list>\n"
+ "\t%s [-t <timestamp>] <cpio_list>\n"
"\n"
"<cpio_list> is a file containing newline separated entries that\n"
"describe the files to be included in the initramfs archive:\n"
@@ -491,7 +489,11 @@
"nod /dev/console 0600 0 0 c 5 1\n"
"dir /root 0700 0 0\n"
"dir /sbin 0755 0 0\n"
- "file /sbin/kinit /usr/src/klibc/kinit/kinit 0755 0 0\n",
+ "file /sbin/kinit /usr/src/klibc/kinit/kinit 0755 0 0\n"
+ "\n"
+ "<timestamp> is time in seconds since Epoch that will be used\n"
+ "as mtime for symlinks, special files and directories. The default\n"
+ "is to use the current time for these entries.\n",
prog);
}
@@ -529,17 +531,42 @@
char *args, *type;
int ec = 0;
int line_nr = 0;
+ const char *filename;
- if (2 != argc) {
+ default_mtime = time(NULL);
+ while (1) {
+ int opt = getopt(argc, argv, "t:h");
+ char *invalid;
+
+ if (opt == -1)
+ break;
+ switch (opt) {
+ case 't':
+ default_mtime = strtol(optarg, &invalid, 10);
+ if (!*optarg || *invalid) {
+ fprintf(stderr, "Invalid timestamp: %s\n",
+ optarg);
+ usage(argv[0]);
+ exit(1);
+ }
+ break;
+ case 'h':
+ case '?':
+ usage(argv[0]);
+ exit(opt == 'h' ? 0 : 1);
+ }
+ }
+
+ if (argc - optind != 1) {
usage(argv[0]);
exit(1);
}
-
- if (!strcmp(argv[1], "-"))
+ filename = argv[optind];
+ if (!strcmp(filename, "-"))
cpio_list = stdin;
- else if (! (cpio_list = fopen(argv[1], "r"))) {
+ else if (!(cpio_list = fopen(filename, "r"))) {
fprintf(stderr, "ERROR: unable to open '%s': %s\n\n",
- argv[1], strerror(errno));
+ filename, strerror(errno));
usage(argv[0]);
exit(1);
}
diff --git a/virt/kvm/assigned-dev.c b/virt/kvm/assigned-dev.c
index ae72ae60..6cc4b97 100644
--- a/virt/kvm/assigned-dev.c
+++ b/virt/kvm/assigned-dev.c
@@ -197,8 +197,13 @@
{
kvm_free_assigned_irq(kvm, assigned_dev);
- __pci_reset_function(assigned_dev->dev);
- pci_restore_state(assigned_dev->dev);
+ pci_reset_function(assigned_dev->dev);
+ if (pci_load_and_free_saved_state(assigned_dev->dev,
+ &assigned_dev->pci_saved_state))
+ printk(KERN_INFO "%s: Couldn't reload %s saved state\n",
+ __func__, dev_name(&assigned_dev->dev->dev));
+ else
+ pci_restore_state(assigned_dev->dev);
pci_release_regions(assigned_dev->dev);
pci_disable_device(assigned_dev->dev);
@@ -516,7 +521,10 @@
pci_reset_function(dev);
pci_save_state(dev);
-
+ match->pci_saved_state = pci_store_saved_state(dev);
+ if (!match->pci_saved_state)
+ printk(KERN_DEBUG "%s: Couldn't store %s saved state\n",
+ __func__, dev_name(&dev->dev));
match->assigned_dev_id = assigned_dev->assigned_dev_id;
match->host_segnr = assigned_dev->segnr;
match->host_busnr = assigned_dev->busnr;
@@ -546,7 +554,9 @@
mutex_unlock(&kvm->lock);
return r;
out_list_del:
- pci_restore_state(dev);
+ if (pci_load_and_free_saved_state(dev, &match->pci_saved_state))
+ printk(KERN_INFO "%s: Couldn't reload %s saved state\n",
+ __func__, dev_name(&dev->dev));
list_del(&match->list);
pci_release_regions(dev);
out_disable:
